diff --git a/MCTEST/DE0-nano-HD/.qsys_edit/filters.xml b/MCTEST/DE0-nano-HD/.qsys_edit/filters.xml new file mode 100644 index 00000000..766ed17e --- /dev/null +++ b/MCTEST/DE0-nano-HD/.qsys_edit/filters.xml @@ -0,0 +1,2 @@ + + diff --git a/MCTEST/DE0-nano-HD/.qsys_edit/preferences.xml b/MCTEST/DE0-nano-HD/.qsys_edit/preferences.xml new file mode 100644 index 00000000..a059ddcf --- /dev/null +++ b/MCTEST/DE0-nano-HD/.qsys_edit/preferences.xml @@ -0,0 +1,20 @@ + + + + + + + + + + + + + + + + + + + diff --git a/MCTEST/DE0-nano-HD/DE0.qsf b/MCTEST/DE0-nano-HD/DE0.qsf new file mode 100644 index 00000000..af2f6226 --- /dev/null +++ b/MCTEST/DE0-nano-HD/DE0.qsf @@ -0,0 +1,383 @@ +# Copyright (C) 1991-2011 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. + +# Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. + + +set_global_assignment -name FAMILY "Cyclone IV E" +set_global_assignment -name DEVICE EP4CE22F17C6 +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 + +# Pin & Location Assignments +# ========================== +#============================================================ +# CLOCK +#============================================================ +set_location_assignment PIN_R8 -to CLOCK_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50 + +#============================================================ +# LED +#============================================================ +set_location_assignment PIN_A15 -to LED[0] +set_location_assignment PIN_A13 -to LED[1] +set_location_assignment PIN_B13 -to LED[2] +set_location_assignment PIN_A11 -to LED[3] +set_location_assignment PIN_D1 -to LED[4] +set_location_assignment PIN_F3 -to LED[5] +set_location_assignment PIN_B1 -to LED[6] +set_location_assignment PIN_L3 -to LED[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[7] + +#============================================================ +# KEY +#============================================================ +set_location_assignment PIN_J15 -to KEY[0] +set_location_assignment PIN_E1 -to KEY[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1] + +#============================================================ +# SW +#============================================================ +set_location_assignment PIN_M1 -to SW[0] +set_location_assignment PIN_T8 -to SW[1] +set_location_assignment PIN_B9 -to SW[2] +set_location_assignment PIN_M15 -to SW[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3] + +#============================================================ +# SDRAM +#============================================================ +set_location_assignment PIN_P2 -to DRAM_ADDR[0] +set_location_assignment PIN_N5 -to DRAM_ADDR[1] +set_location_assignment PIN_N6 -to DRAM_ADDR[2] +set_location_assignment PIN_M8 -to DRAM_ADDR[3] +set_location_assignment PIN_P8 -to DRAM_ADDR[4] +set_location_assignment PIN_T7 -to DRAM_ADDR[5] +set_location_assignment PIN_N8 -to DRAM_ADDR[6] +set_location_assignment PIN_T6 -to DRAM_ADDR[7] +set_location_assignment PIN_R1 -to DRAM_ADDR[8] +set_location_assignment PIN_P1 -to DRAM_ADDR[9] +set_location_assignment PIN_N2 -to DRAM_ADDR[10] +set_location_assignment PIN_N1 -to DRAM_ADDR[11] +set_location_assignment PIN_L4 -to DRAM_ADDR[12] +set_location_assignment PIN_M7 -to DRAM_BA[0] +set_location_assignment PIN_M6 -to DRAM_BA[1] +set_location_assignment PIN_L7 -to DRAM_CKE +set_location_assignment PIN_R4 -to DRAM_CLK +set_location_assignment PIN_P6 -to DRAM_CS_N +set_location_assignment PIN_G2 -to DRAM_DQ[0] +set_location_assignment PIN_G1 -to DRAM_DQ[1] +set_location_assignment PIN_L8 -to DRAM_DQ[2] +set_location_assignment PIN_K5 -to DRAM_DQ[3] +set_location_assignment PIN_K2 -to DRAM_DQ[4] +set_location_assignment PIN_J2 -to DRAM_DQ[5] +set_location_assignment PIN_J1 -to DRAM_DQ[6] +set_location_assignment PIN_R7 -to DRAM_DQ[7] +set_location_assignment PIN_T4 -to DRAM_DQ[8] +set_location_assignment PIN_T2 -to DRAM_DQ[9] +set_location_assignment PIN_T3 -to DRAM_DQ[10] +set_location_assignment PIN_R3 -to DRAM_DQ[11] +set_location_assignment PIN_R5 -to DRAM_DQ[12] +set_location_assignment PIN_P3 -to DRAM_DQ[13] +set_location_assignment PIN_N3 -to DRAM_DQ[14] +set_location_assignment PIN_K1 -to DRAM_DQ[15] +set_location_assignment PIN_R6 -to DRAM_DQM[0] +set_location_assignment PIN_T5 -to DRAM_DQM[1] +set_location_assignment PIN_L1 -to DRAM_CAS_N +set_location_assignment PIN_L2 -to DRAM_RAS_N +set_location_assignment PIN_C2 -to DRAM_WE_N + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CKE +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CAS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_RAS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_WE_N + +#============================================================ +# Accelerometer and EEPROM +#============================================================ +set_location_assignment PIN_F2 -to I2C_SCLK +set_location_assignment PIN_F1 -to I2C_SDAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to I2C_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to I2C_SDAT + +set_location_assignment PIN_G5 -to G_SENSOR_CS_N +set_location_assignment PIN_M2 -to G_SENSOR_INT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to G_SENSOR_CS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to G_SENSOR_INT + +#============================================================ +# ADC +#============================================================ +set_location_assignment PIN_A10 -to ADC_CS_N +set_location_assignment PIN_B10 -to ADC_SADDR +set_location_assignment PIN_B14 -to ADC_SCLK +set_location_assignment PIN_A9 -to ADC_SDAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SADDR +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDAT + +#============================================================ +# 2x13 GPIO Header +#============================================================ +set_location_assignment PIN_A14 -to GPIO_2[0] +set_location_assignment PIN_B16 -to GPIO_2[1] +set_location_assignment PIN_C14 -to GPIO_2[2] +set_location_assignment PIN_C16 -to GPIO_2[3] +set_location_assignment PIN_C15 -to GPIO_2[4] +set_location_assignment PIN_D16 -to GPIO_2[5] +set_location_assignment PIN_D15 -to GPIO_2[6] +set_location_assignment PIN_D14 -to GPIO_2[7] +set_location_assignment PIN_F15 -to GPIO_2[8] +set_location_assignment PIN_F16 -to GPIO_2[9] +set_location_assignment PIN_F14 -to GPIO_2[10] +set_location_assignment PIN_G16 -to GPIO_2[11] +set_location_assignment PIN_G15 -to GPIO_2[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[12] + +set_location_assignment PIN_E15 -to GPIO_2_IN[0] +set_location_assignment PIN_E16 -to GPIO_2_IN[1] +set_location_assignment PIN_M16 -to GPIO_2_IN[2] + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2_IN[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2_IN[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2_IN[2] + +#============================================================ +# GPIO_0, GPIO_0 connect to GPIO Default +#============================================================ +set_location_assignment PIN_A8 -to GPIO_0_IN[0] +set_location_assignment PIN_D3 -to GPIO_0[0] +set_location_assignment PIN_B8 -to GPIO_0_IN[1] +set_location_assignment PIN_C3 -to GPIO_0[1] +set_location_assignment PIN_A2 -to GPIO_0[2] +set_location_assignment PIN_A3 -to GPIO_0[3] +set_location_assignment PIN_B3 -to GPIO_0[4] +set_location_assignment PIN_B4 -to GPIO_0[5] +set_location_assignment PIN_A4 -to GPIO_0[6] +set_location_assignment PIN_B5 -to GPIO_0[7] +set_location_assignment PIN_A5 -to GPIO_0[8] +set_location_assignment PIN_D5 -to GPIO_0[9] +set_location_assignment PIN_B6 -to GPIO_0[10] +set_location_assignment PIN_A6 -to GPIO_0[11] +set_location_assignment PIN_B7 -to GPIO_0[12] +set_location_assignment PIN_D6 -to GPIO_0[13] +set_location_assignment PIN_A7 -to GPIO_0[14] +set_location_assignment PIN_C6 -to GPIO_0[15] +set_location_assignment PIN_C8 -to GPIO_0[16] +set_location_assignment PIN_E6 -to GPIO_0[17] +set_location_assignment PIN_E7 -to GPIO_0[18] +set_location_assignment PIN_D8 -to GPIO_0[19] +set_location_assignment PIN_E8 -to GPIO_0[20] +set_location_assignment PIN_F8 -to GPIO_0[21] +set_location_assignment PIN_F9 -to GPIO_0[22] +set_location_assignment PIN_E9 -to GPIO_0[23] +set_location_assignment PIN_C9 -to GPIO_0[24] +set_location_assignment PIN_D9 -to GPIO_0[25] +set_location_assignment PIN_E11 -to GPIO_0[26] +set_location_assignment PIN_E10 -to GPIO_0[27] +set_location_assignment PIN_C11 -to GPIO_0[28] +set_location_assignment PIN_B11 -to GPIO_0[29] +set_location_assignment PIN_A12 -to GPIO_0[30] +set_location_assignment PIN_D11 -to GPIO_0[31] +set_location_assignment PIN_D12 -to GPIO_0[32] +set_location_assignment PIN_B12 -to GPIO_0[33] + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_IN[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_IN[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[16] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[17] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[18] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[19] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[20] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[21] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[22] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[23] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[24] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[25] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[26] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[27] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[28] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[29] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[30] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[31] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[32] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[33] + +#============================================================ +# GPIO_0, GPIO_1 connect to GPIO Default +#============================================================ +set_location_assignment PIN_T9 -to GPIO_1_IN[0] +set_location_assignment PIN_F13 -to GPIO_1[0] +set_location_assignment PIN_R9 -to GPIO_1_IN[1] +set_location_assignment PIN_T15 -to GPIO_1[1] +set_location_assignment PIN_T14 -to GPIO_1[2] +set_location_assignment PIN_T13 -to GPIO_1[3] +set_location_assignment PIN_R13 -to GPIO_1[4] +set_location_assignment PIN_T12 -to GPIO_1[5] +set_location_assignment PIN_R12 -to GPIO_1[6] +set_location_assignment PIN_T11 -to GPIO_1[7] +set_location_assignment PIN_T10 -to GPIO_1[8] +set_location_assignment PIN_R11 -to GPIO_1[9] +set_location_assignment PIN_P11 -to GPIO_1[10] +set_location_assignment PIN_R10 -to GPIO_1[11] +set_location_assignment PIN_N12 -to GPIO_1[12] +set_location_assignment PIN_P9 -to GPIO_1[13] +set_location_assignment PIN_N9 -to GPIO_1[14] +set_location_assignment PIN_N11 -to GPIO_1[15] +set_location_assignment PIN_L16 -to GPIO_1[16] +set_location_assignment PIN_K16 -to GPIO_1[17] +set_location_assignment PIN_R16 -to GPIO_1[18] +set_location_assignment PIN_L15 -to GPIO_1[19] +set_location_assignment PIN_P15 -to GPIO_1[20] +set_location_assignment PIN_P16 -to GPIO_1[21] +set_location_assignment PIN_R14 -to GPIO_1[22] +set_location_assignment PIN_N16 -to GPIO_1[23] +set_location_assignment PIN_N15 -to GPIO_1[24] +set_location_assignment PIN_P14 -to GPIO_1[25] +set_location_assignment PIN_L14 -to GPIO_1[26] +set_location_assignment PIN_N14 -to GPIO_1[27] +set_location_assignment PIN_M10 -to GPIO_1[28] +set_location_assignment PIN_L13 -to GPIO_1[29] +set_location_assignment PIN_J16 -to GPIO_1[30] +set_location_assignment PIN_K15 -to GPIO_1[31] +set_location_assignment PIN_J13 -to GPIO_1[32] +set_location_assignment PIN_J14 -to GPIO_1[33] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_IN[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_IN[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[16] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[17] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[18] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[19] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[20] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[21] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[22] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[23] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[24] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[25] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[26] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[27] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[28] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[29] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[30] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[31] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[32] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[33] + +set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" +set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" + +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" + +set_instance_assignment -name FAST_INPUT_REGISTER ON -to * +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to * +set_instance_assignment -name TSU_REQUIREMENT "10 ns" -from * -to * +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to * + +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top diff --git a/MCTEST/DE0-nano-HD/PLLJ_PLLSPE_INFO.txt b/MCTEST/DE0-nano-HD/PLLJ_PLLSPE_INFO.txt new file mode 100644 index 00000000..6b5f1895 --- /dev/null +++ b/MCTEST/DE0-nano-HD/PLLJ_PLLSPE_INFO.txt @@ -0,0 +1,5 @@ +PLL_Name pll_sys:inst_pll_sys|altpll:altpll_component|pll_sys_altpll:auto_generated|pll1 +PLLJITTER 35 +PLLSPEmax 84 +PLLSPEmin -53 + diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0/.force_relink b/MCTEST/DE0-nano-HD/Software/.metadata/.lock similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0/.force_relink rename to MCTEST/DE0-nano-HD/Software/.metadata/.lock diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.log b/MCTEST/DE0-nano-HD/Software/.metadata/.log new file mode 100644 index 00000000..5803b16e --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.log @@ -0,0 +1,1986 @@ +!SESSION 2014-03-06 10:00:27.665 ----------------------------------------------- +eclipse.buildId=M20120208-0800 +java.version=1.6.0_23 +java.vendor=Sun Microsystems Inc. +BootLoader constants: OS=win32, ARCH=x86, WS=win32, NL=en_CA +Framework arguments: -product org.eclipse.epp.package.cpp.product -perspective com.altera.sbtgui.ui.cPerspective +Command-line arguments: -os win32 -ws win32 -arch x86 -product org.eclipse.epp.package.cpp.product -perspective com.altera.sbtgui.ui.cPerspective + +!ENTRY org.eclipse.cdt.core 1 0 2014-03-06 10:04:05.691 +!MESSAGE Indexed 'MCTest_bsp' (99 sources, 70 headers) in 0.98 sec: 2,374 declarations; 10,554 references; 129 unresolved inclusions; 5 syntax errors; 233 unresolved names (1.77%) + +!ENTRY org.eclipse.cdt.core 1 0 2014-03-06 10:04:08.045 +!MESSAGE Indexed 'MCTest' (1 sources, 13 headers) in 0.01 sec: 8 declarations; 23 references; 15 unresolved inclusions; 0 syntax errors; 6 unresolved names (16.22%) + +!ENTRY org.eclipse.cdt.core 1 0 2014-03-06 10:22:52.933 +!MESSAGE Indexed 'MCTest' (2 sources, 83 headers) in 0.43 sec: 2,294 declarations; 2,576 references; 0 unresolved inclusions; 2 syntax errors; 26 unresolved names (0.53%) + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-06 10:45:29.994 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-06 10:45:31.707 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-06 10:46:45.877 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-06 10:46:46.264 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-06 10:46:47.911 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-06 10:47:06.838 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-06 10:47:07.222 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-06 10:47:08.863 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-06 10:49:17.294 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-06 10:49:17.685 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-06 10:49:19.338 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-06 10:50:06.960 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-06 10:50:07.353 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-06 10:50:08.999 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-06 10:51:04.644 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-06 10:51:05.036 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-06 10:51:06.683 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-06 10:53:47.321 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-06 10:53:47.713 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-06 10:53:49.360 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-06 10:54:04.969 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-06 10:54:05.355 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-06 10:54:07.001 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-06 10:54:19.771 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-06 10:54:20.164 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-06 10:54:21.807 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-06 10:55:11.681 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-06 10:55:12.067 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-06 10:55:13.723 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-06 10:55:39.188 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-06 10:55:39.582 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-06 10:55:41.230 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-06 10:55:58.357 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-06 10:55:58.742 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-06 10:56:00.388 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-06 10:56:11.301 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-06 10:56:11.689 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-06 10:56:13.329 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-06 10:56:32.426 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-06 10:56:32.815 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-06 10:56:36.534 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --tcpport=auto --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY org.eclipse.ui 4 4 2014-03-06 10:56:40.710 +!MESSAGE Exception in org.eclipse.ui.internal.PageLayout.stackView: org.eclipse.ui.PartInitException: Could not create view: org.eclipse.cdt.debug.ui.DisassemblyView + +!ENTRY org.eclipse.ui 4 4 2014-03-06 10:56:40.712 +!MESSAGE Exception in org.eclipse.ui.internal.PageLayout.stackView: org.eclipse.ui.PartInitException: Could not create view: org.eclipse.cdt.debug.ui.DisassemblyView +!STACK 1 +org.eclipse.ui.PartInitException: Could not create view: org.eclipse.cdt.debug.ui.DisassemblyView + at org.eclipse.ui.internal.ViewFactory.createView(ViewFactory.java:158) + at org.eclipse.ui.internal.LayoutHelper.createView(LayoutHelper.java:162) + at org.eclipse.ui.internal.PageLayout.createView(PageLayout.java:554) + at org.eclipse.ui.internal.PageLayout.stackView(PageLayout.java:863) + at org.eclipse.ui.internal.registry.PerspectiveExtensionReader.processView(PerspectiveExtensionReader.java:270) + at org.eclipse.ui.internal.registry.PerspectiveExtensionReader.processExtension(PerspectiveExtensionReader.java:118) + at org.eclipse.ui.internal.registry.PerspectiveExtensionReader.readElement(PerspectiveExtensionReader.java:355) + at org.eclipse.ui.internal.registry.RegistryReader.readElements(RegistryReader.java:144) + at org.eclipse.ui.internal.registry.RegistryReader.readExtension(RegistryReader.java:155) + at org.eclipse.ui.internal.registry.RegistryReader.readRegistry(RegistryReader.java:176) + at org.eclipse.ui.internal.registry.PerspectiveExtensionReader.extendLayout(PerspectiveExtensionReader.java:82) + at org.eclipse.ui.internal.Perspective.loadPredefinedPersp(Perspective.java:818) + at org.eclipse.ui.internal.Perspective.createPresentation(Perspective.java:270) + at org.eclipse.ui.internal.Perspective.(Perspective.java:156) + at org.eclipse.ui.internal.tweaklets.Workbench3xImplementation.createPerspective(Workbench3xImplementation.java:55) + at org.eclipse.ui.internal.WorkbenchPage.createPerspective(WorkbenchPage.java:1748) + at org.eclipse.ui.internal.WorkbenchPage.busySetPerspective(WorkbenchPage.java:1108) + at org.eclipse.ui.internal.WorkbenchPage.access$16(WorkbenchPage.java:1099) + at org.eclipse.ui.internal.WorkbenchPage$19.run(WorkbenchPage.java:3814) + at org.eclipse.swt.custom.BusyIndicator.showWhile(BusyIndicator.java:70) + at org.eclipse.ui.internal.WorkbenchPage.setPerspective(WorkbenchPage.java:3812) + at org.eclipse.ui.internal.Workbench.showPerspective(Workbench.java:2875) + at org.eclipse.debug.internal.ui.launchConfigurations.PerspectiveManager.switchToPerspective(PerspectiveManager.java:316) + at org.eclipse.debug.internal.ui.launchConfigurations.PerspectiveManager$4.runInUIThread(PerspectiveManager.java:395) + at org.eclipse.ui.progress.UIJob$1.run(UIJob.java:95) + at org.eclipse.swt.widgets.RunnableLock.run(RunnableLock.java:35) + at org.eclipse.swt.widgets.Synchronizer.runAsyncMessages(Synchronizer.java:135) + at org.eclipse.swt.widgets.Display.runAsyncMessages(Display.java:4140) + at org.eclipse.swt.widgets.Display.readAndDispatch(Display.java:3757) + at org.eclipse.ui.internal.Workbench.runEventLoop(Workbench.java:2701) + at org.eclipse.ui.internal.Workbench.runUI(Workbench.java:2665) + at org.eclipse.ui.internal.Workbench.access$4(Workbench.java:2499) + at org.eclipse.ui.internal.Workbench$7.run(Workbench.java:679) + at org.eclipse.core.databinding.observable.Realm.runWithDefault(Realm.java:332) + at org.eclipse.ui.internal.Workbench.createAndRunWorkbench(Workbench.java:668) + at org.eclipse.ui.PlatformUI.createAndRunWorkbench(PlatformUI.java:149) + at org.eclipse.ui.internal.ide.application.IDEApplication.start(IDEApplication.java:123) + at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:196) + at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:110) + at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:79) + at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:344) + at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:179) + at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method) + at sun.reflect.NativeMethodAccessorImpl.invoke(Unknown Source) + at sun.reflect.DelegatingMethodAccessorImpl.invoke(Unknown Source) + at java.lang.reflect.Method.invoke(Unknown Source) + at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:622) + at org.eclipse.equinox.launcher.Main.basicRun(Main.java:577) + at org.eclipse.equinox.launcher.Main.run(Main.java:1410) + at org.eclipse.equinox.launcher.Main.main(Main.java:1386) +!SUBENTRY 1 org.eclipse.ui 4 0 2014-03-06 10:56:40.712 +!MESSAGE Could not create view: org.eclipse.cdt.debug.ui.DisassemblyView + +!ENTRY org.eclipse.cdt.debug.mi.core 4 42 2014-03-06 10:56:55.621 +!MESSAGE Internal Error +!STACK 0 +org.eclipse.cdt.debug.mi.core.cdi.MI2CDIException: Inferior terminated[] + at org.eclipse.cdt.debug.mi.core.cdi.SharedLibraryManager.getMIShareds(SharedLibraryManager.java:123) + at org.eclipse.cdt.debug.mi.core.cdi.SharedLibraryManager.updateState(SharedLibraryManager.java:188) + at org.eclipse.cdt.debug.mi.core.cdi.SharedLibraryManager.update(SharedLibraryManager.java:136) + at org.eclipse.cdt.debug.mi.core.cdi.EventManager.processSuspendedEvent(EventManager.java:326) + at org.eclipse.cdt.debug.mi.core.cdi.EventManager.update(EventManager.java:100) + at java.util.Observable.notifyObservers(Unknown Source) + at org.eclipse.cdt.debug.mi.core.MISession.notifyObservers(MISession.java:791) + at org.eclipse.cdt.debug.mi.core.EventThread.run(EventThread.java:46) + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-06 10:56:55.674 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-06 10:56:56.064 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-06 10:56:59.749 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --tcpport=auto --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY org.eclipse.cdt.dsf.gdb 4 5012 2014-03-06 10:57:39.322 +!MESSAGE Error in final launch sequence +!STACK 1 +org.eclipse.core.runtime.CoreException: Failed to execute MI command: +-exec-run +Error message from debugger back end: +Error creating process C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf, (error 193). + at org.eclipse.cdt.dsf.concurrent.Query.get(Query.java:114) + at org.eclipse.cdt.dsf.gdb.launching.GdbLaunchDelegate.launchDebugSession(GdbLaunchDelegate.java:211) + at org.eclipse.cdt.dsf.gdb.launching.GdbLaunchDelegate.launchDebugger(GdbLaunchDelegate.java:98) + at org.eclipse.cdt.dsf.gdb.launching.GdbLaunchDelegate.launch(GdbLaunchDelegate.java:87) + at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:854) + at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:703) + at org.eclipse.debug.internal.ui.DebugUIPlugin.buildAndLaunch(DebugUIPlugin.java:937) + at org.eclipse.debug.internal.ui.DebugUIPlugin$8.run(DebugUIPlugin.java:1141) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54) +Caused by: java.lang.Exception: Error creating process C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf, (error 193). + at org.eclipse.cdt.dsf.mi.service.command.AbstractMIControl$RxThread.processMIOutput(AbstractMIControl.java:889) + at org.eclipse.cdt.dsf.mi.service.command.AbstractMIControl$RxThread.run(AbstractMIControl.java:720) +!SUBENTRY 1 org.eclipse.cdt.dsf.gdb 4 10004 2014-03-06 10:57:39.322 +!MESSAGE Failed to execute MI command: +-exec-run +Error message from debugger back end: +Error creating process C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf, (error 193). +!STACK 0 +java.lang.Exception: Error creating process C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf, (error 193). + at org.eclipse.cdt.dsf.mi.service.command.AbstractMIControl$RxThread.processMIOutput(AbstractMIControl.java:889) + at org.eclipse.cdt.dsf.mi.service.command.AbstractMIControl$RxThread.run(AbstractMIControl.java:720) + +!ENTRY org.eclipse.cdt.dsf.gdb 4 5012 2014-03-06 10:57:51.026 +!MESSAGE Error in final launch sequence +!STACK 1 +org.eclipse.core.runtime.CoreException: Failed to execute MI command: +-exec-run +Error message from debugger back end: +Error creating process C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf, (error 193). + at org.eclipse.cdt.dsf.concurrent.Query.get(Query.java:114) + at org.eclipse.cdt.dsf.gdb.launching.GdbLaunchDelegate.launchDebugSession(GdbLaunchDelegate.java:211) + at org.eclipse.cdt.dsf.gdb.launching.GdbLaunchDelegate.launchDebugger(GdbLaunchDelegate.java:98) + at org.eclipse.cdt.dsf.gdb.launching.GdbLaunchDelegate.launch(GdbLaunchDelegate.java:87) + at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:854) + at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:703) + at org.eclipse.debug.internal.ui.DebugUIPlugin.buildAndLaunch(DebugUIPlugin.java:937) + at org.eclipse.debug.internal.ui.DebugUIPlugin$8.run(DebugUIPlugin.java:1141) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54) +Caused by: java.lang.Exception: Error creating process C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf, (error 193). + at org.eclipse.cdt.dsf.mi.service.command.AbstractMIControl$RxThread.processMIOutput(AbstractMIControl.java:889) + at org.eclipse.cdt.dsf.mi.service.command.AbstractMIControl$RxThread.run(AbstractMIControl.java:720) +!SUBENTRY 1 org.eclipse.cdt.dsf.gdb 4 10004 2014-03-06 10:57:51.026 +!MESSAGE Failed to execute MI command: +-exec-run +Error message from debugger back end: +Error creating process C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf, (error 193). +!STACK 0 +java.lang.Exception: Error creating process C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf, (error 193). + at org.eclipse.cdt.dsf.mi.service.command.AbstractMIControl$RxThread.processMIOutput(AbstractMIControl.java:889) + at org.eclipse.cdt.dsf.mi.service.command.AbstractMIControl$RxThread.run(AbstractMIControl.java:720) + +!ENTRY org.eclipse.cdt.launch 4 150 2014-03-06 10:59:40.219 +!MESSAGE Error starting process. +!STACK 0 +java.io.IOException: Cannot run program "C:\Users\gongal\Desktop\MCTEST\DE0-nano-HD\Software\MCTest\MCTest.elf": Launching failed + at org.eclipse.cdt.utils.spawner.Spawner.exec(Spawner.java:347) + at org.eclipse.cdt.utils.spawner.Spawner.(Spawner.java:89) + at org.eclipse.cdt.utils.spawner.ProcessFactory.exec(ProcessFactory.java:89) + at org.eclipse.cdt.launch.internal.LocalCDILaunchDelegate.exec(LocalCDILaunchDelegate.java:370) + at org.eclipse.cdt.launch.internal.LocalCDILaunchDelegate.runLocalApplication(LocalCDILaunchDelegate.java:96) + at org.eclipse.cdt.launch.internal.LocalCDILaunchDelegate.launch(LocalCDILaunchDelegate.java:70) + at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:854) + at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:703) + at org.eclipse.debug.internal.ui.DebugUIPlugin.buildAndLaunch(DebugUIPlugin.java:937) + at org.eclipse.debug.internal.ui.DebugUIPlugin$8.run(DebugUIPlugin.java:1141) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54) +!SUBENTRY 1 org.eclipse.cdt.launch 4 150 2014-03-06 10:59:40.219 +!MESSAGE Cannot run program "C:\Users\gongal\Desktop\MCTEST\DE0-nano-HD\Software\MCTest\MCTest.elf": Launching failed +!STACK 0 +java.io.IOException: Cannot run program "C:\Users\gongal\Desktop\MCTEST\DE0-nano-HD\Software\MCTest\MCTest.elf": Launching failed + at org.eclipse.cdt.utils.spawner.Spawner.exec(Spawner.java:347) + at org.eclipse.cdt.utils.spawner.Spawner.(Spawner.java:89) + at org.eclipse.cdt.utils.spawner.ProcessFactory.exec(ProcessFactory.java:89) + at org.eclipse.cdt.launch.internal.LocalCDILaunchDelegate.exec(LocalCDILaunchDelegate.java:370) + at org.eclipse.cdt.launch.internal.LocalCDILaunchDelegate.runLocalApplication(LocalCDILaunchDelegate.java:96) + at org.eclipse.cdt.launch.internal.LocalCDILaunchDelegate.launch(LocalCDILaunchDelegate.java:70) + at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:854) + at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:703) + at org.eclipse.debug.internal.ui.DebugUIPlugin.buildAndLaunch(DebugUIPlugin.java:937) + at org.eclipse.debug.internal.ui.DebugUIPlugin$8.run(DebugUIPlugin.java:1141) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54) + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-06 10:59:51.095 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-06 10:59:52.744 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-06 11:01:24.728 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-06 11:01:25.128 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-06 11:01:26.779 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-06 11:02:30.790 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-06 11:02:32.443 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-06 11:03:30.366 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-06 11:03:30.755 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-06 11:03:32.410 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-06 11:04:33.923 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-06 11:04:34.315 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-06 11:04:35.962 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-06 11:05:16.483 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-06 11:05:16.880 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-06 11:05:18.526 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-06 11:06:23.987 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 4 0 2014-03-06 11:42:06.222 +!MESSAGE FrameworkEvent ERROR +!STACK 0 +org.osgi.framework.BundleException: Exception in com.altera.sbtgui.launch.Activator.stop() of bundle com.altera.sbtgui.launch. + at org.eclipse.osgi.framework.internal.core.BundleContextImpl.stop(BundleContextImpl.java:791) + at org.eclipse.osgi.framework.internal.core.BundleHost.stopWorker(BundleHost.java:510) + at org.eclipse.osgi.framework.internal.core.AbstractBundle.suspend(AbstractBundle.java:565) + at org.eclipse.osgi.framework.internal.core.Framework.suspendBundle(Framework.java:1161) + at org.eclipse.osgi.framework.internal.core.StartLevelManager.decFWSL(StartLevelManager.java:595) + at org.eclipse.osgi.framework.internal.core.StartLevelManager.doSetStartLevel(StartLevelManager.java:257) + at org.eclipse.osgi.framework.internal.core.StartLevelManager.shutdown(StartLevelManager.java:215) + at org.eclipse.osgi.framework.internal.core.InternalSystemBundle.suspend(InternalSystemBundle.java:284) + at org.eclipse.osgi.framework.internal.core.Framework.shutdown(Framework.java:691) + at org.eclipse.osgi.framework.internal.core.Framework.close(Framework.java:598) + at org.eclipse.core.runtime.adaptor.EclipseStarter.shutdown(EclipseStarter.java:390) + at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:198) + at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method) + at sun.reflect.NativeMethodAccessorImpl.invoke(Unknown Source) + at sun.reflect.DelegatingMethodAccessorImpl.invoke(Unknown Source) + at java.lang.reflect.Method.invoke(Unknown Source) + at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:622) + at org.eclipse.equinox.launcher.Main.basicRun(Main.java:577) + at org.eclipse.equinox.launcher.Main.run(Main.java:1410) + at org.eclipse.equinox.launcher.Main.main(Main.java:1386) +Caused by: org.eclipse.core.runtime.CoreException: Problems terminating debug session: please terminate debug session manually before exiting. + at com.altera.sbtgui.launch.Activator.stop(Activator.java:123) + at org.eclipse.osgi.framework.internal.core.BundleContextImpl$2.run(BundleContextImpl.java:771) + at java.security.AccessController.doPrivileged(Native Method) + at org.eclipse.osgi.framework.internal.core.BundleContextImpl.stop(BundleContextImpl.java:764) + ... 19 more +Root exception: +org.eclipse.core.runtime.CoreException: Problems terminating debug session: please terminate debug session manually before exiting. + at com.altera.sbtgui.launch.Activator.stop(Activator.java:123) + at org.eclipse.osgi.framework.internal.core.BundleContextImpl$2.run(BundleContextImpl.java:771) + at java.security.AccessController.doPrivileged(Native Method) + at org.eclipse.osgi.framework.internal.core.BundleContextImpl.stop(BundleContextImpl.java:764) + at org.eclipse.osgi.framework.internal.core.BundleHost.stopWorker(BundleHost.java:510) + at org.eclipse.osgi.framework.internal.core.AbstractBundle.suspend(AbstractBundle.java:565) + at org.eclipse.osgi.framework.internal.core.Framework.suspendBundle(Framework.java:1161) + at org.eclipse.osgi.framework.internal.core.StartLevelManager.decFWSL(StartLevelManager.java:595) + at org.eclipse.osgi.framework.internal.core.StartLevelManager.doSetStartLevel(StartLevelManager.java:257) + at org.eclipse.osgi.framework.internal.core.StartLevelManager.shutdown(StartLevelManager.java:215) + at org.eclipse.osgi.framework.internal.core.InternalSystemBundle.suspend(InternalSystemBundle.java:284) + at org.eclipse.osgi.framework.internal.core.Framework.shutdown(Framework.java:691) + at org.eclipse.osgi.framework.internal.core.Framework.close(Framework.java:598) + at org.eclipse.core.runtime.adaptor.EclipseStarter.shutdown(EclipseStarter.java:390) + at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:198) + at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method) + at sun.reflect.NativeMethodAccessorImpl.invoke(Unknown Source) + at sun.reflect.DelegatingMethodAccessorImpl.invoke(Unknown Source) + at java.lang.reflect.Method.invoke(Unknown Source) + at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:622) + at org.eclipse.equinox.launcher.Main.basicRun(Main.java:577) + at org.eclipse.equinox.launcher.Main.run(Main.java:1410) + at org.eclipse.equinox.launcher.Main.main(Main.java:1386) + +!ENTRY org.eclipse.core.jobs 2 2 2014-03-06 11:42:06.618 +!MESSAGE Job found still running after platform shutdown. Jobs should be canceled by the plugin that scheduled them during shutdown: org.eclipse.debug.internal.ui.DebugUIPlugin$8 +!SESSION 2014-03-06 11:47:10.488 ----------------------------------------------- +eclipse.buildId=M20120208-0800 +java.version=1.6.0_23 +java.vendor=Sun Microsystems Inc. +BootLoader constants: OS=win32, ARCH=x86, WS=win32, NL=en_CA +Framework arguments: -product org.eclipse.epp.package.cpp.product -perspective com.altera.sbtgui.ui.cPerspective +Command-line arguments: -os win32 -ws win32 -arch x86 -product org.eclipse.epp.package.cpp.product -perspective com.altera.sbtgui.ui.cPerspective + +!ENTRY org.eclipse.ui 4 4 2014-03-06 11:47:33.510 +!MESSAGE Could not create view: 'org.eclipse.ui.internal.introview'. + +!ENTRY org.eclipse.ui 4 0 2014-03-06 11:47:35.189 +!MESSAGE Problems occurred restoring workbench. +!SUBENTRY 1 unknown 0 0 2014-03-06 11:47:35.189 +!MESSAGE OK +!SUBENTRY 1 unknown 0 0 2014-03-06 11:47:35.189 +!MESSAGE OK +!SUBENTRY 1 unknown 0 0 2014-03-06 11:47:35.189 +!MESSAGE OK +!SUBENTRY 1 unknown 0 0 2014-03-06 11:47:35.189 +!MESSAGE OK +!SUBENTRY 1 org.eclipse.ui 4 0 2014-03-06 11:47:35.189 +!MESSAGE Unable to restore perspective: Workspace - Nios II. +!SUBENTRY 2 org.eclipse.ui 0 0 2014-03-06 11:47:35.189 +!MESSAGE Problems occurred restoring perspective. +!SUBENTRY 3 org.eclipse.ui 0 0 2014-03-06 11:47:35.189 +!MESSAGE +!SUBENTRY 2 unknown 0 0 2014-03-06 11:47:35.190 +!MESSAGE OK +!SUBENTRY 2 unknown 0 0 2014-03-06 11:47:35.190 +!MESSAGE OK +!SUBENTRY 2 unknown 0 0 2014-03-06 11:47:35.190 +!MESSAGE OK +!SUBENTRY 2 unknown 0 0 2014-03-06 11:47:35.190 +!MESSAGE OK +!SUBENTRY 2 unknown 0 0 2014-03-06 11:47:35.190 +!MESSAGE OK +!SUBENTRY 2 unknown 0 0 2014-03-06 11:47:35.190 +!MESSAGE OK +!SUBENTRY 2 unknown 0 0 2014-03-06 11:47:35.190 +!MESSAGE OK +!SUBENTRY 2 unknown 0 0 2014-03-06 11:47:35.190 +!MESSAGE OK +!SUBENTRY 2 unknown 0 0 2014-03-06 11:47:35.190 +!MESSAGE OK +!SUBENTRY 2 org.eclipse.ui 4 0 2014-03-06 11:47:35.190 +!MESSAGE Could not find view: org.eclipse.ui.internal.introview +!SUBENTRY 1 unknown 0 0 2014-03-06 11:47:35.190 +!MESSAGE OK + +!ENTRY org.eclipse.cdt.core 1 0 2014-03-06 11:48:49.104 +!MESSAGE Indexed 'MCTest' (2 sources, 83 headers) in 0.56 sec: 2,297 declarations; 2,590 references; 0 unresolved inclusions; 2 syntax errors; 20 unresolved names (0.41%) +!SESSION 2014-03-14 08:58:20.013 ----------------------------------------------- +eclipse.buildId=M20120208-0800 +java.version=1.6.0_23 +java.vendor=Sun Microsystems Inc. +BootLoader constants: OS=win32, ARCH=x86, WS=win32, NL=en_CA +Framework arguments: -product org.eclipse.epp.package.cpp.product -perspective com.altera.sbtgui.ui.cPerspective +Command-line arguments: -os win32 -ws win32 -arch x86 -product org.eclipse.epp.package.cpp.product -perspective com.altera.sbtgui.ui.cPerspective + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 09:00:44.703 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 09:00:46.419 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 09:06:30.459 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 09:06:30.865 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 09:06:32.534 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 09:08:13.950 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 09:08:14.356 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 09:08:16.025 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 09:11:09.200 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 09:11:09.590 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 09:11:11.259 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 09:11:26.471 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 09:11:26.861 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 09:11:28.530 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 09:11:37.237 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 09:11:37.627 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 09:11:39.296 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 09:11:50.374 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 09:11:50.764 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 09:11:52.418 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 09:12:25.928 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 09:12:26.318 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 09:12:27.987 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 09:41:07.741 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 09:41:08.146 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 09:41:09.831 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 09:42:00.002 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 09:42:00.392 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 09:42:02.061 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 09:42:42.451 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 09:42:42.888 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 09:42:46.587 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --tcpport=auto --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 09:44:11.295 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY org.eclipse.cdt.debug.mi.core 4 42 2014-03-14 09:44:11.313 +!MESSAGE Internal Error +!STACK 0 +org.eclipse.cdt.debug.mi.core.cdi.MI2CDIException: Inferior terminated[] + at org.eclipse.cdt.debug.mi.core.cdi.SharedLibraryManager.getMIShareds(SharedLibraryManager.java:123) + at org.eclipse.cdt.debug.mi.core.cdi.SharedLibraryManager.updateState(SharedLibraryManager.java:188) + at org.eclipse.cdt.debug.mi.core.cdi.SharedLibraryManager.update(SharedLibraryManager.java:136) + at org.eclipse.cdt.debug.mi.core.cdi.EventManager.processSuspendedEvent(EventManager.java:326) + at org.eclipse.cdt.debug.mi.core.cdi.EventManager.update(EventManager.java:100) + at java.util.Observable.notifyObservers(Unknown Source) + at org.eclipse.cdt.debug.mi.core.MISession.notifyObservers(MISession.java:791) + at org.eclipse.cdt.debug.mi.core.EventThread.run(EventThread.java:46) + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 09:44:11.752 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 09:44:13.421 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 09:45:17.882 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 09:45:19.567 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 09:45:58.474 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 09:45:58.864 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 09:46:00.534 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 09:46:30.409 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 09:46:30.799 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 09:46:32.468 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 09:47:03.202 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 09:47:03.592 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 09:47:05.261 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 09:48:23.465 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 09:48:23.871 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 09:48:25.540 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] +!SESSION 2014-03-14 12:04:50.779 ----------------------------------------------- +eclipse.buildId=M20120208-0800 +java.version=1.6.0_23 +java.vendor=Sun Microsystems Inc. +BootLoader constants: OS=win32, ARCH=x86, WS=win32, NL=en_CA +Framework arguments: -product org.eclipse.epp.package.cpp.product -perspective com.altera.sbtgui.ui.cPerspective +Command-line arguments: -os win32 -ws win32 -arch x86 -product org.eclipse.epp.package.cpp.product -perspective com.altera.sbtgui.ui.cPerspective + +!ENTRY com.altera.sbtgui.launch 4 0 2014-03-14 12:23:17.614 +!MESSAGE Unable to validate connection settings. +!STACK 0 +java.lang.Exception + at com.altera.embeddedsw.flash.model.internal.SystemConsoleConnectionModel.validateConnectionSettings(SystemConsoleConnectionModel.java:555) + at com.altera.sbtgui.launch.hardware.AbstractNios2CLaunchDelegate.launch(AbstractNios2CLaunchDelegate.java:115) + at com.altera.sbtgui.launch.hardware.Nios2HardwareLaunchDelegate.launch(Nios2HardwareLaunchDelegate.java:98) + at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:854) + at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:703) + at org.eclipse.debug.internal.ui.DebugUIPlugin.buildAndLaunch(DebugUIPlugin.java:937) + at org.eclipse.debug.internal.ui.DebugUIPlugin$8.run(DebugUIPlugin.java:1141) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54) + +!ENTRY com.altera.sbtgui.launch 4 0 2014-03-14 12:23:17.629 +!MESSAGE Unable to validate connection settings. +!STACK 0 +java.lang.Exception + at com.altera.embeddedsw.flash.model.internal.SystemConsoleConnectionModel.validateConnectionSettings(SystemConsoleConnectionModel.java:555) + at com.altera.sbtgui.launch.hardware.AbstractNios2CLaunchDelegate.launch(AbstractNios2CLaunchDelegate.java:115) + at com.altera.sbtgui.launch.hardware.Nios2HardwareLaunchDelegate.launch(Nios2HardwareLaunchDelegate.java:98) + at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:854) + at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:703) + at org.eclipse.debug.internal.ui.DebugUIPlugin.buildAndLaunch(DebugUIPlugin.java:937) + at org.eclipse.debug.internal.ui.DebugUIPlugin$8.run(DebugUIPlugin.java:1141) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54) + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 12:23:53.105 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 12:23:54.806 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 12:24:17.070 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 12:24:18.739 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 12:25:26.213 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 12:25:26.618 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 12:25:28.272 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 12:26:05.277 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 12:26:05.652 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 12:26:07.305 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 12:28:30.111 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 12:28:30.501 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 12:28:32.170 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 12:28:46.774 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 12:28:47.164 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 12:28:48.833 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 12:29:26.509 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 12:29:26.899 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 12:29:28.568 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 12:38:16.053 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 12:38:17.722 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 12:42:55.072 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 12:42:55.540 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 12:42:57.241 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 12:45:43.553 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 12:45:44.084 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 12:45:45.753 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 12:46:40.604 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 12:46:40.994 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 12:46:42.663 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 12:48:17.825 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 12:48:18.230 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 12:48:19.915 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 13:10:37.775 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 13:10:39.460 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 13:11:11.270 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 13:11:11.660 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 13:11:13.345 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 13:11:39.477 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 13:11:39.883 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 13:11:41.552 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 13:12:12.130 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 13:12:12.629 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 13:12:14.298 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 13:12:18.574 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 13:12:18.964 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 13:12:20.634 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 13:14:25.856 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 13:14:26.355 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 13:14:28.274 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 13:14:55.420 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 13:14:55.841 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 13:14:57.510 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 13:16:32.562 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 13:16:33.046 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 13:16:34.715 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 13:16:52.597 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 13:16:53.050 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 13:16:54.719 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 13:18:17.531 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 13:18:17.968 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 13:18:19.638 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 13:18:48.567 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 13:18:49.004 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 13:18:50.674 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 13:20:01.448 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 13:20:01.931 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 13:20:03.601 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 13:21:18.797 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 13:21:19.765 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 13:21:21.450 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 13:22:39.076 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 13:22:39.825 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 13:22:41.494 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 13:38:15.170 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 13:38:16.776 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 13:38:18.602 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 13:38:40.646 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 13:38:41.099 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 13:38:42.783 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 13:38:58.791 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 13:38:59.228 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 13:39:00.912 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 13:39:24.096 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 13:39:24.502 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 13:39:26.171 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 13:49:34.483 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 13:49:35.466 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 13:49:37.400 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 13:50:02.175 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 13:50:02.596 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 13:50:04.281 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 14:12:49.104 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 4 0 2014-03-14 14:12:54.876 +!MESSAGE Unable to validate connection settings. +!STACK 0 +java.lang.Exception + at com.altera.embeddedsw.flash.model.internal.SystemConsoleConnectionModel.validateConnectionSettings(SystemConsoleConnectionModel.java:503) + at com.altera.sbtgui.launch.hardware.AbstractNios2CLaunchDelegate.launch(AbstractNios2CLaunchDelegate.java:115) + at com.altera.sbtgui.launch.hardware.Nios2HardwareLaunchDelegate.launch(Nios2HardwareLaunchDelegate.java:98) + at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:854) + at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:703) + at org.eclipse.debug.internal.ui.DebugUIPlugin.buildAndLaunch(DebugUIPlugin.java:937) + at org.eclipse.debug.internal.ui.DebugUIPlugin$8.run(DebugUIPlugin.java:1141) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54) + +!ENTRY com.altera.sbtgui.launch 4 0 2014-03-14 14:12:54.876 +!MESSAGE Unable to validate connection settings. +!STACK 0 +java.lang.Exception + at com.altera.embeddedsw.flash.model.internal.SystemConsoleConnectionModel.validateConnectionSettings(SystemConsoleConnectionModel.java:503) + at com.altera.sbtgui.launch.hardware.AbstractNios2CLaunchDelegate.launch(AbstractNios2CLaunchDelegate.java:115) + at com.altera.sbtgui.launch.hardware.Nios2HardwareLaunchDelegate.launch(Nios2HardwareLaunchDelegate.java:98) + at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:854) + at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:703) + at org.eclipse.debug.internal.ui.DebugUIPlugin.buildAndLaunch(DebugUIPlugin.java:937) + at org.eclipse.debug.internal.ui.DebugUIPlugin$8.run(DebugUIPlugin.java:1141) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54) + +!ENTRY com.altera.sbtgui.launch 4 0 2014-03-14 14:13:05.266 +!MESSAGE Unable to validate connection settings. +!STACK 0 +java.lang.Exception + at com.altera.embeddedsw.flash.model.internal.SystemConsoleConnectionModel.validateConnectionSettings(SystemConsoleConnectionModel.java:503) + at com.altera.sbtgui.launch.hardware.AbstractNios2CLaunchDelegate.launch(AbstractNios2CLaunchDelegate.java:115) + at com.altera.sbtgui.launch.hardware.Nios2HardwareLaunchDelegate.launch(Nios2HardwareLaunchDelegate.java:98) + at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:854) + at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:703) + at org.eclipse.debug.internal.ui.DebugUIPlugin.buildAndLaunch(DebugUIPlugin.java:937) + at org.eclipse.debug.internal.ui.DebugUIPlugin$8.run(DebugUIPlugin.java:1141) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54) + +!ENTRY com.altera.sbtgui.launch 4 0 2014-03-14 14:13:05.266 +!MESSAGE Unable to validate connection settings. +!STACK 0 +java.lang.Exception + at com.altera.embeddedsw.flash.model.internal.SystemConsoleConnectionModel.validateConnectionSettings(SystemConsoleConnectionModel.java:503) + at com.altera.sbtgui.launch.hardware.AbstractNios2CLaunchDelegate.launch(AbstractNios2CLaunchDelegate.java:115) + at com.altera.sbtgui.launch.hardware.Nios2HardwareLaunchDelegate.launch(Nios2HardwareLaunchDelegate.java:98) + at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:854) + at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:703) + at org.eclipse.debug.internal.ui.DebugUIPlugin.buildAndLaunch(DebugUIPlugin.java:937) + at org.eclipse.debug.internal.ui.DebugUIPlugin$8.run(DebugUIPlugin.java:1141) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54) + +!ENTRY com.altera.sbtgui.launch 4 0 2014-03-14 14:13:15.764 +!MESSAGE Unable to validate connection settings. +!STACK 0 +java.lang.Exception + at com.altera.embeddedsw.flash.model.internal.SystemConsoleConnectionModel.validateConnectionSettings(SystemConsoleConnectionModel.java:503) + at com.altera.sbtgui.launch.hardware.AbstractNios2CLaunchDelegate.launch(AbstractNios2CLaunchDelegate.java:115) + at com.altera.sbtgui.launch.hardware.Nios2HardwareLaunchDelegate.launch(Nios2HardwareLaunchDelegate.java:98) + at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:854) + at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:703) + at org.eclipse.debug.internal.ui.DebugUIPlugin.buildAndLaunch(DebugUIPlugin.java:937) + at org.eclipse.debug.internal.ui.DebugUIPlugin$8.run(DebugUIPlugin.java:1141) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54) + +!ENTRY com.altera.sbtgui.launch 4 0 2014-03-14 14:13:15.764 +!MESSAGE Unable to validate connection settings. +!STACK 0 +java.lang.Exception + at com.altera.embeddedsw.flash.model.internal.SystemConsoleConnectionModel.validateConnectionSettings(SystemConsoleConnectionModel.java:503) + at com.altera.sbtgui.launch.hardware.AbstractNios2CLaunchDelegate.launch(AbstractNios2CLaunchDelegate.java:115) + at com.altera.sbtgui.launch.hardware.Nios2HardwareLaunchDelegate.launch(Nios2HardwareLaunchDelegate.java:98) + at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:854) + at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:703) + at org.eclipse.debug.internal.ui.DebugUIPlugin.buildAndLaunch(DebugUIPlugin.java:937) + at org.eclipse.debug.internal.ui.DebugUIPlugin$8.run(DebugUIPlugin.java:1141) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54) +!SESSION 2014-03-14 14:14:17.328 ----------------------------------------------- +eclipse.buildId=M20120208-0800 +java.version=1.6.0_23 +java.vendor=Sun Microsystems Inc. +BootLoader constants: OS=win32, ARCH=x86, WS=win32, NL=en_CA +Framework arguments: -product org.eclipse.epp.package.cpp.product -perspective com.altera.sbtgui.ui.cPerspective +Command-line arguments: -os win32 -ws win32 -arch x86 -product org.eclipse.epp.package.cpp.product -perspective com.altera.sbtgui.ui.cPerspective + +!ENTRY org.eclipse.core.resources 2 10035 2014-03-14 14:14:20.885 +!MESSAGE The workspace exited with unsaved changes in the previous session; refreshing workspace to recover changes. + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 14:14:34.862 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 14:14:36.563 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 14:14:57.718 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 14:14:58.124 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 14:14:59.777 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 14:15:15.725 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 14:15:16.131 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 14:15:17.800 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 14:15:37.712 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 14:15:38.118 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 14:15:39.787 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 14:16:49.235 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 14:16:49.688 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 14:16:51.357 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 14:17:21.020 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 14:17:21.457 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 14:17:23.127 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 14:17:44.956 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 14:17:45.362 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 14:17:47.016 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 14:18:33.217 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 14:18:33.654 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 14:18:35.448 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 14:19:18.576 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 14:19:19.028 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 14:19:20.698 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 14:20:02.701 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 14:20:03.122 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 14:20:04.776 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 14:20:31.330 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 14:20:31.767 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 14:20:33.421 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 14:21:16.762 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 14:21:17.230 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 14:21:18.899 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 14:21:43.425 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 14:21:43.909 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 14:21:45.563 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 14:22:14.614 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 14:22:15.051 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 14:22:16.720 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 14:22:33.228 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 14:22:33.649 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 14:22:35.318 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 14:22:48.862 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 14:22:49.252 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 14:22:50.921 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 14:23:32.670 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 14:23:33.123 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 14:23:34.808 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 14:24:33.437 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 14:24:33.905 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 14:24:35.574 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 14:25:25.716 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 14:25:26.184 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 14:25:27.853 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 14:26:07.620 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 14:26:08.057 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 14:26:09.726 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 14:26:18.387 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 14:26:18.792 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 14:26:20.461 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 14:26:36.656 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 14:26:37.078 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 14:26:38.747 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 15:14:20.580 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 15:14:22.272 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 15:14:23.932 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 15:15:11.891 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 15:20:28.566 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY org.eclipse.ui.console 4 2 2014-03-14 15:20:28.593 +!MESSAGE Problems occurred when invoking code from plug-in: "org.eclipse.ui.console". +!STACK 0 +org.eclipse.swt.SWTException: Device is disposed + at org.eclipse.swt.SWT.error(SWT.java:4282) + at org.eclipse.swt.SWT.error(SWT.java:4197) + at org.eclipse.swt.SWT.error(SWT.java:4168) + at org.eclipse.swt.widgets.Display.error(Display.java:1258) + at org.eclipse.swt.widgets.Display.asyncExec(Display.java:709) + at org.eclipse.ui.internal.console.IOConsolePartitioner.setWaterMarks(IOConsolePartitioner.java:143) + at org.eclipse.ui.console.IOConsole.setWaterMarks(IOConsole.java:207) + at org.eclipse.debug.internal.ui.views.console.ProcessConsole.init(ProcessConsole.java:416) + at org.eclipse.ui.console.AbstractConsole.initialize(AbstractConsole.java:258) + at org.eclipse.ui.console.AbstractConsole$Lifecycle.consolesAdded(AbstractConsole.java:64) + at org.eclipse.ui.internal.console.ConsoleManager$ConsoleNotifier.run(ConsoleManager.java:152) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.ui.internal.console.ConsoleManager$ConsoleNotifier.notify(ConsoleManager.java:175) + at org.eclipse.ui.internal.console.ConsoleManager.fireUpdate(ConsoleManager.java:269) + at org.eclipse.ui.internal.console.ConsoleManager.addConsoles(ConsoleManager.java:231) + at org.eclipse.debug.internal.ui.views.console.ProcessConsoleManager.launchChanged(ProcessConsoleManager.java:149) + at org.eclipse.debug.internal.core.LaunchManager$LaunchNotifier.run(LaunchManager.java:447) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.debug.internal.core.LaunchManager$LaunchNotifier.notify(LaunchManager.java:428) + at org.eclipse.debug.internal.core.LaunchManager.fireUpdate(LaunchManager.java:990) + at org.eclipse.debug.core.Launch.fireChanged(Launch.java:388) + at org.eclipse.debug.core.Launch.addProcess(Launch.java:351) + at org.eclipse.debug.core.model.RuntimeProcess.(RuntimeProcess.java:125) + at com.altera.sbtgui.launch.hardware.Nios2HardwareLaunchDelegate$Nios2RemoteProcess.(Nios2HardwareLaunchDelegate.java:1105) + at com.altera.sbtgui.launch.hardware.Nios2HardwareLaunchDelegate$3.(Nios2HardwareLaunchDelegate.java:548) + at com.altera.sbtgui.launch.hardware.Nios2HardwareLaunchDelegate.stopProcessorProcess(Nios2HardwareLaunchDelegate.java:547) + at com.altera.sbtgui.launch.hardware.Nios2HardwareLaunchDelegate.launch(Nios2HardwareLaunchDelegate.java:105) + at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:854) + at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:703) + at org.eclipse.debug.internal.ui.DebugUIPlugin.buildAndLaunch(DebugUIPlugin.java:937) + at org.eclipse.debug.internal.ui.DebugUIPlugin$8.run(DebugUIPlugin.java:1141) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54) + +!ENTRY org.eclipse.ui.console 4 120 2014-03-14 15:20:28.596 +!MESSAGE An exception occurred during console notification +!STACK 0 +org.eclipse.swt.SWTException: Device is disposed + at org.eclipse.swt.SWT.error(SWT.java:4282) + at org.eclipse.swt.SWT.error(SWT.java:4197) + at org.eclipse.swt.SWT.error(SWT.java:4168) + at org.eclipse.swt.widgets.Display.error(Display.java:1258) + at org.eclipse.swt.widgets.Display.asyncExec(Display.java:709) + at org.eclipse.ui.internal.console.IOConsolePartitioner.setWaterMarks(IOConsolePartitioner.java:143) + at org.eclipse.ui.console.IOConsole.setWaterMarks(IOConsole.java:207) + at org.eclipse.debug.internal.ui.views.console.ProcessConsole.init(ProcessConsole.java:416) + at org.eclipse.ui.console.AbstractConsole.initialize(AbstractConsole.java:258) + at org.eclipse.ui.console.AbstractConsole$Lifecycle.consolesAdded(AbstractConsole.java:64) + at org.eclipse.ui.internal.console.ConsoleManager$ConsoleNotifier.run(ConsoleManager.java:152) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.ui.internal.console.ConsoleManager$ConsoleNotifier.notify(ConsoleManager.java:175) + at org.eclipse.ui.internal.console.ConsoleManager.fireUpdate(ConsoleManager.java:269) + at org.eclipse.ui.internal.console.ConsoleManager.addConsoles(ConsoleManager.java:231) + at org.eclipse.debug.internal.ui.views.console.ProcessConsoleManager.launchChanged(ProcessConsoleManager.java:149) + at org.eclipse.debug.internal.core.LaunchManager$LaunchNotifier.run(LaunchManager.java:447) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.debug.internal.core.LaunchManager$LaunchNotifier.notify(LaunchManager.java:428) + at org.eclipse.debug.internal.core.LaunchManager.fireUpdate(LaunchManager.java:990) + at org.eclipse.debug.core.Launch.fireChanged(Launch.java:388) + at org.eclipse.debug.core.Launch.addProcess(Launch.java:351) + at org.eclipse.debug.core.model.RuntimeProcess.(RuntimeProcess.java:125) + at com.altera.sbtgui.launch.hardware.Nios2HardwareLaunchDelegate$Nios2RemoteProcess.(Nios2HardwareLaunchDelegate.java:1105) + at com.altera.sbtgui.launch.hardware.Nios2HardwareLaunchDelegate$3.(Nios2HardwareLaunchDelegate.java:548) + at com.altera.sbtgui.launch.hardware.Nios2HardwareLaunchDelegate.stopProcessorProcess(Nios2HardwareLaunchDelegate.java:547) + at com.altera.sbtgui.launch.hardware.Nios2HardwareLaunchDelegate.launch(Nios2HardwareLaunchDelegate.java:105) + at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:854) + at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:703) + at org.eclipse.debug.internal.ui.DebugUIPlugin.buildAndLaunch(DebugUIPlugin.java:937) + at org.eclipse.debug.internal.ui.DebugUIPlugin$8.run(DebugUIPlugin.java:1141) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54) + +!ENTRY org.eclipse.cdt.managedbuilder.core 4 0 2014-03-14 15:20:28.758 +!MESSAGE Workspace is closed. +!STACK 0 +java.lang.IllegalStateException: Workspace is closed. + at org.eclipse.core.resources.ResourcesPlugin.getWorkspace(ResourcesPlugin.java:399) + at org.eclipse.cdt.managedbuilder.core.ExternalBuildRunner.invokeExternalBuild(ExternalBuildRunner.java:207) + at org.eclipse.cdt.managedbuilder.core.ExternalBuildRunner.invokeBuild(ExternalBuildRunner.java:85) + at org.eclipse.cdt.managedbuilder.internal.core.CommonBuilder.build(CommonBuilder.java:744) + at org.eclipse.cdt.managedbuilder.internal.core.CommonBuilder.build(CommonBuilder.java:501) + at org.eclipse.cdt.managedbuilder.internal.core.CommonBuilder.build(CommonBuilder.java:450) + at org.eclipse.core.internal.events.BuildManager$2.run(BuildManager.java:728) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.core.internal.events.BuildManager.basicBuild(BuildManager.java:199) + at org.eclipse.core.internal.events.BuildManager.basicBuild(BuildManager.java:239) + at org.eclipse.core.internal.events.BuildManager$1.run(BuildManager.java:292) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.core.internal.events.BuildManager.basicBuild(BuildManager.java:295) + at org.eclipse.core.internal.events.BuildManager.basicBuild(BuildManager.java:256) + at org.eclipse.core.internal.events.BuildManager.build(BuildManager.java:394) + at org.eclipse.core.internal.resources.Project$1.run(Project.java:618) + at org.eclipse.core.internal.resources.Workspace.run(Workspace.java:2344) + at org.eclipse.core.internal.resources.Project.internalBuild(Project.java:597) + at org.eclipse.core.internal.resources.Project.build(Project.java:114) + at org.eclipse.cdt.launch.AbstractCLaunchDelegate.buildForLaunch(AbstractCLaunchDelegate.java:615) + at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:822) + at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:703) + at org.eclipse.debug.internal.ui.DebugUIPlugin.buildAndLaunch(DebugUIPlugin.java:937) + at org.eclipse.debug.internal.ui.DebugUIPlugin$8.run(DebugUIPlugin.java:1141) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54) + +!ENTRY org.eclipse.core.resources 4 2 2014-03-14 15:20:28.760 +!MESSAGE Problems occurred when invoking code from plug-in: "org.eclipse.core.resources". +!STACK 1 +org.eclipse.core.runtime.CoreException: Workspace is closed. + at org.eclipse.cdt.managedbuilder.core.ExternalBuildRunner.invokeExternalBuild(ExternalBuildRunner.java:251) + at org.eclipse.cdt.managedbuilder.core.ExternalBuildRunner.invokeBuild(ExternalBuildRunner.java:85) + at org.eclipse.cdt.managedbuilder.internal.core.CommonBuilder.build(CommonBuilder.java:744) + at org.eclipse.cdt.managedbuilder.internal.core.CommonBuilder.build(CommonBuilder.java:501) + at org.eclipse.cdt.managedbuilder.internal.core.CommonBuilder.build(CommonBuilder.java:450) + at org.eclipse.core.internal.events.BuildManager$2.run(BuildManager.java:728) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.core.internal.events.BuildManager.basicBuild(BuildManager.java:199) + at org.eclipse.core.internal.events.BuildManager.basicBuild(BuildManager.java:239) + at org.eclipse.core.internal.events.BuildManager$1.run(BuildManager.java:292) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.core.internal.events.BuildManager.basicBuild(BuildManager.java:295) + at org.eclipse.core.internal.events.BuildManager.basicBuild(BuildManager.java:256) + at org.eclipse.core.internal.events.BuildManager.build(BuildManager.java:394) + at org.eclipse.core.internal.resources.Project$1.run(Project.java:618) + at org.eclipse.core.internal.resources.Workspace.run(Workspace.java:2344) + at org.eclipse.core.internal.resources.Project.internalBuild(Project.java:597) + at org.eclipse.core.internal.resources.Project.build(Project.java:114) + at org.eclipse.cdt.launch.AbstractCLaunchDelegate.buildForLaunch(AbstractCLaunchDelegate.java:615) + at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:822) + at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:703) + at org.eclipse.debug.internal.ui.DebugUIPlugin.buildAndLaunch(DebugUIPlugin.java:937) + at org.eclipse.debug.internal.ui.DebugUIPlugin$8.run(DebugUIPlugin.java:1141) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54) +Caused by: java.lang.IllegalStateException: Workspace is closed. + at org.eclipse.core.resources.ResourcesPlugin.getWorkspace(ResourcesPlugin.java:399) + at org.eclipse.cdt.managedbuilder.core.ExternalBuildRunner.invokeExternalBuild(ExternalBuildRunner.java:207) + ... 23 more +!SUBENTRY 1 org.eclipse.cdt.managedbuilder.core 4 0 2014-03-14 15:20:28.760 +!MESSAGE Workspace is closed. +!STACK 0 +java.lang.IllegalStateException: Workspace is closed. + at org.eclipse.core.resources.ResourcesPlugin.getWorkspace(ResourcesPlugin.java:399) + at org.eclipse.cdt.managedbuilder.core.ExternalBuildRunner.invokeExternalBuild(ExternalBuildRunner.java:207) + at org.eclipse.cdt.managedbuilder.core.ExternalBuildRunner.invokeBuild(ExternalBuildRunner.java:85) + at org.eclipse.cdt.managedbuilder.internal.core.CommonBuilder.build(CommonBuilder.java:744) + at org.eclipse.cdt.managedbuilder.internal.core.CommonBuilder.build(CommonBuilder.java:501) + at org.eclipse.cdt.managedbuilder.internal.core.CommonBuilder.build(CommonBuilder.java:450) + at org.eclipse.core.internal.events.BuildManager$2.run(BuildManager.java:728) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.core.internal.events.BuildManager.basicBuild(BuildManager.java:199) + at org.eclipse.core.internal.events.BuildManager.basicBuild(BuildManager.java:239) + at org.eclipse.core.internal.events.BuildManager$1.run(BuildManager.java:292) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.core.internal.events.BuildManager.basicBuild(BuildManager.java:295) + at org.eclipse.core.internal.events.BuildManager.basicBuild(BuildManager.java:256) + at org.eclipse.core.internal.events.BuildManager.build(BuildManager.java:394) + at org.eclipse.core.internal.resources.Project$1.run(Project.java:618) + at org.eclipse.core.internal.resources.Workspace.run(Workspace.java:2344) + at org.eclipse.core.internal.resources.Project.internalBuild(Project.java:597) + at org.eclipse.core.internal.resources.Project.build(Project.java:114) + at org.eclipse.cdt.launch.AbstractCLaunchDelegate.buildForLaunch(AbstractCLaunchDelegate.java:615) + at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:822) + at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:703) + at org.eclipse.debug.internal.ui.DebugUIPlugin.buildAndLaunch(DebugUIPlugin.java:937) + at org.eclipse.debug.internal.ui.DebugUIPlugin$8.run(DebugUIPlugin.java:1141) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54) +!SUBENTRY 1 org.eclipse.cdt.managedbuilder.core 4 0 2014-03-14 15:20:28.760 +!MESSAGE Workspace is closed. +!STACK 0 +java.lang.IllegalStateException: Workspace is closed. + at org.eclipse.core.resources.ResourcesPlugin.getWorkspace(ResourcesPlugin.java:399) + at org.eclipse.cdt.managedbuilder.core.ExternalBuildRunner.invokeExternalBuild(ExternalBuildRunner.java:207) + at org.eclipse.cdt.managedbuilder.core.ExternalBuildRunner.invokeBuild(ExternalBuildRunner.java:85) + at org.eclipse.cdt.managedbuilder.internal.core.CommonBuilder.build(CommonBuilder.java:744) + at org.eclipse.cdt.managedbuilder.internal.core.CommonBuilder.build(CommonBuilder.java:501) + at org.eclipse.cdt.managedbuilder.internal.core.CommonBuilder.build(CommonBuilder.java:450) + at org.eclipse.core.internal.events.BuildManager$2.run(BuildManager.java:728) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.core.internal.events.BuildManager.basicBuild(BuildManager.java:199) + at org.eclipse.core.internal.events.BuildManager.basicBuild(BuildManager.java:239) + at org.eclipse.core.internal.events.BuildManager$1.run(BuildManager.java:292) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.core.internal.events.BuildManager.basicBuild(BuildManager.java:295) + at org.eclipse.core.internal.events.BuildManager.basicBuild(BuildManager.java:256) + at org.eclipse.core.internal.events.BuildManager.build(BuildManager.java:394) + at org.eclipse.core.internal.resources.Project$1.run(Project.java:618) + at org.eclipse.core.internal.resources.Workspace.run(Workspace.java:2344) + at org.eclipse.core.internal.resources.Project.internalBuild(Project.java:597) + at org.eclipse.core.internal.resources.Project.build(Project.java:114) + at org.eclipse.cdt.launch.AbstractCLaunchDelegate.buildForLaunch(AbstractCLaunchDelegate.java:615) + at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:822) + at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:703) + at org.eclipse.debug.internal.ui.DebugUIPlugin.buildAndLaunch(DebugUIPlugin.java:937) + at org.eclipse.debug.internal.ui.DebugUIPlugin$8.run(DebugUIPlugin.java:1141) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54) + +!ENTRY org.eclipse.core.resources 4 2 2014-03-14 15:20:28.763 +!MESSAGE Problems occurred when invoking code from plug-in: "org.eclipse.core.resources". +!STACK 0 +java.lang.NullPointerException + at org.eclipse.core.internal.events.BuildManager.basicBuild(BuildManager.java:203) + at org.eclipse.core.internal.events.BuildManager.basicBuild(BuildManager.java:239) + at org.eclipse.core.internal.events.BuildManager$1.run(BuildManager.java:292) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.core.internal.events.BuildManager.basicBuild(BuildManager.java:295) + at org.eclipse.core.internal.events.BuildManager.basicBuild(BuildManager.java:256) + at org.eclipse.core.internal.events.BuildManager.build(BuildManager.java:394) + at org.eclipse.core.internal.resources.Project$1.run(Project.java:618) + at org.eclipse.core.internal.resources.Workspace.run(Workspace.java:2344) + at org.eclipse.core.internal.resources.Project.internalBuild(Project.java:597) + at org.eclipse.core.internal.resources.Project.build(Project.java:114) + at org.eclipse.cdt.launch.AbstractCLaunchDelegate.buildForLaunch(AbstractCLaunchDelegate.java:615) + at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:822) + at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:703) + at org.eclipse.debug.internal.ui.DebugUIPlugin.buildAndLaunch(DebugUIPlugin.java:937) + at org.eclipse.debug.internal.ui.DebugUIPlugin$8.run(DebugUIPlugin.java:1141) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54) + +!ENTRY org.eclipse.core.jobs 4 2 2014-03-14 15:20:28.765 +!MESSAGE An internal error occurred during: "Launching MCTest Nios II Hardware configuration". +!STACK 0 +java.lang.NullPointerException + at org.eclipse.cdt.launch.AbstractCLaunchDelegate.finalLaunchCheck(AbstractCLaunchDelegate.java:738) + at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:835) + at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:703) + at org.eclipse.debug.internal.ui.DebugUIPlugin.buildAndLaunch(DebugUIPlugin.java:937) + at org.eclipse.debug.internal.ui.DebugUIPlugin$8.run(DebugUIPlugin.java:1141) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54) + +!ENTRY org.eclipse.core.jobs 2 2 2014-03-14 15:20:29.018 +!MESSAGE Job found still running after platform shutdown. Jobs should be canceled by the plugin that scheduled them during shutdown: org.eclipse.debug.internal.ui.DebugUIPlugin$8 +!SESSION 2014-03-14 15:20:48.329 ----------------------------------------------- +eclipse.buildId=M20120208-0800 +java.version=1.6.0_23 +java.vendor=Sun Microsystems Inc. +BootLoader constants: OS=win32, ARCH=x86, WS=win32, NL=en_CA +Framework arguments: -product org.eclipse.epp.package.cpp.product -perspective com.altera.sbtgui.ui.cPerspective +Command-line arguments: -os win32 -ws win32 -arch x86 -product org.eclipse.epp.package.cpp.product -perspective com.altera.sbtgui.ui.cPerspective + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 15:21:05.618 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 15:21:07.294 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 15:21:58.631 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 15:21:59.064 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 15:22:00.713 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 15:22:55.374 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 15:22:55.841 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 15:22:57.489 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 15:54:36.241 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 15:54:38.333 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 15:54:40.553 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 15:56:30.718 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 4 0 2014-03-14 15:56:35.868 +!MESSAGE Unable to validate connection settings. +!STACK 0 +java.lang.Exception: Connected system ID hash not found on target at expected base address. + at com.altera.embeddedsw.flash.model.internal.SystemConsoleConnectionModel.assertTrue(SystemConsoleConnectionModel.java:645) + at com.altera.embeddedsw.flash.model.internal.SystemConsoleConnectionModel.validateSystemId(SystemConsoleConnectionModel.java:589) + at com.altera.embeddedsw.flash.model.internal.SystemConsoleConnectionModel.validateConnectionSettings(SystemConsoleConnectionModel.java:511) + at com.altera.sbtgui.launch.hardware.AbstractNios2CLaunchDelegate.launch(AbstractNios2CLaunchDelegate.java:115) + at com.altera.sbtgui.launch.hardware.Nios2HardwareLaunchDelegate.launch(Nios2HardwareLaunchDelegate.java:98) + at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:854) + at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:703) + at org.eclipse.debug.internal.ui.DebugUIPlugin.buildAndLaunch(DebugUIPlugin.java:937) + at org.eclipse.debug.internal.ui.DebugUIPlugin$8.run(DebugUIPlugin.java:1141) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54) + +!ENTRY com.altera.sbtgui.launch 4 0 2014-03-14 15:56:35.872 +!MESSAGE Unable to validate connection settings. +!STACK 0 +java.lang.Exception: Connected system ID hash not found on target at expected base address. + at com.altera.embeddedsw.flash.model.internal.SystemConsoleConnectionModel.assertTrue(SystemConsoleConnectionModel.java:645) + at com.altera.embeddedsw.flash.model.internal.SystemConsoleConnectionModel.validateSystemId(SystemConsoleConnectionModel.java:589) + at com.altera.embeddedsw.flash.model.internal.SystemConsoleConnectionModel.validateConnectionSettings(SystemConsoleConnectionModel.java:511) + at com.altera.sbtgui.launch.hardware.AbstractNios2CLaunchDelegate.launch(AbstractNios2CLaunchDelegate.java:115) + at com.altera.sbtgui.launch.hardware.Nios2HardwareLaunchDelegate.launch(Nios2HardwareLaunchDelegate.java:98) + at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:854) + at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:703) + at org.eclipse.debug.internal.ui.DebugUIPlugin.buildAndLaunch(DebugUIPlugin.java:937) + at org.eclipse.debug.internal.ui.DebugUIPlugin$8.run(DebugUIPlugin.java:1141) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54) + +!ENTRY com.altera.sbtgui.launch 4 0 2014-03-14 15:56:51.667 +!MESSAGE Unable to validate connection settings. +!STACK 0 +java.lang.Exception: Connected system ID hash not found on target at expected base address. + at com.altera.embeddedsw.flash.model.internal.SystemConsoleConnectionModel.assertTrue(SystemConsoleConnectionModel.java:645) + at com.altera.embeddedsw.flash.model.internal.SystemConsoleConnectionModel.validateSystemId(SystemConsoleConnectionModel.java:589) + at com.altera.embeddedsw.flash.model.internal.SystemConsoleConnectionModel.validateConnectionSettings(SystemConsoleConnectionModel.java:511) + at com.altera.sbtgui.launch.hardware.AbstractNios2CLaunchDelegate.launch(AbstractNios2CLaunchDelegate.java:115) + at com.altera.sbtgui.launch.hardware.Nios2HardwareLaunchDelegate.launch(Nios2HardwareLaunchDelegate.java:98) + at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:854) + at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:703) + at org.eclipse.debug.internal.ui.DebugUIPlugin.buildAndLaunch(DebugUIPlugin.java:937) + at org.eclipse.debug.internal.ui.DebugUIPlugin$8.run(DebugUIPlugin.java:1141) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54) + +!ENTRY com.altera.sbtgui.launch 4 0 2014-03-14 15:56:51.670 +!MESSAGE Unable to validate connection settings. +!STACK 0 +java.lang.Exception: Connected system ID hash not found on target at expected base address. + at com.altera.embeddedsw.flash.model.internal.SystemConsoleConnectionModel.assertTrue(SystemConsoleConnectionModel.java:645) + at com.altera.embeddedsw.flash.model.internal.SystemConsoleConnectionModel.validateSystemId(SystemConsoleConnectionModel.java:589) + at com.altera.embeddedsw.flash.model.internal.SystemConsoleConnectionModel.validateConnectionSettings(SystemConsoleConnectionModel.java:511) + at com.altera.sbtgui.launch.hardware.AbstractNios2CLaunchDelegate.launch(AbstractNios2CLaunchDelegate.java:115) + at com.altera.sbtgui.launch.hardware.Nios2HardwareLaunchDelegate.launch(Nios2HardwareLaunchDelegate.java:98) + at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:854) + at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:703) + at org.eclipse.debug.internal.ui.DebugUIPlugin.buildAndLaunch(DebugUIPlugin.java:937) + at org.eclipse.debug.internal.ui.DebugUIPlugin$8.run(DebugUIPlugin.java:1141) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54) +!SESSION 2014-03-14 15:58:59.154 ----------------------------------------------- +eclipse.buildId=M20120208-0800 +java.version=1.6.0_23 +java.vendor=Sun Microsystems Inc. +BootLoader constants: OS=win32, ARCH=x86, WS=win32, NL=en_CA +Framework arguments: -product org.eclipse.epp.package.cpp.product -perspective com.altera.sbtgui.ui.cPerspective +Command-line arguments: -os win32 -ws win32 -arch x86 -product org.eclipse.epp.package.cpp.product -perspective com.altera.sbtgui.ui.cPerspective + +!ENTRY org.eclipse.cdt.launch 4 150 2014-03-14 15:59:16.567 +!MESSAGE Error starting process. +!STACK 0 +java.io.IOException: Cannot run program "C:\Users\gongal\Desktop\MCTEST\DE0-nano-HD\Software\MCTest\MCTest.elf": Launching failed + at org.eclipse.cdt.utils.spawner.Spawner.exec(Spawner.java:347) + at org.eclipse.cdt.utils.spawner.Spawner.(Spawner.java:89) + at org.eclipse.cdt.utils.spawner.ProcessFactory.exec(ProcessFactory.java:89) + at org.eclipse.cdt.launch.internal.LocalCDILaunchDelegate.exec(LocalCDILaunchDelegate.java:370) + at org.eclipse.cdt.launch.internal.LocalCDILaunchDelegate.runLocalApplication(LocalCDILaunchDelegate.java:96) + at org.eclipse.cdt.launch.internal.LocalCDILaunchDelegate.launch(LocalCDILaunchDelegate.java:70) + at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:854) + at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:703) + at org.eclipse.debug.internal.ui.DebugUIPlugin.buildAndLaunch(DebugUIPlugin.java:937) + at org.eclipse.debug.internal.ui.DebugUIPlugin$8.run(DebugUIPlugin.java:1141) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54) +!SUBENTRY 1 org.eclipse.cdt.launch 4 150 2014-03-14 15:59:16.568 +!MESSAGE Cannot run program "C:\Users\gongal\Desktop\MCTEST\DE0-nano-HD\Software\MCTest\MCTest.elf": Launching failed +!STACK 0 +java.io.IOException: Cannot run program "C:\Users\gongal\Desktop\MCTEST\DE0-nano-HD\Software\MCTest\MCTest.elf": Launching failed + at org.eclipse.cdt.utils.spawner.Spawner.exec(Spawner.java:347) + at org.eclipse.cdt.utils.spawner.Spawner.(Spawner.java:89) + at org.eclipse.cdt.utils.spawner.ProcessFactory.exec(ProcessFactory.java:89) + at org.eclipse.cdt.launch.internal.LocalCDILaunchDelegate.exec(LocalCDILaunchDelegate.java:370) + at org.eclipse.cdt.launch.internal.LocalCDILaunchDelegate.runLocalApplication(LocalCDILaunchDelegate.java:96) + at org.eclipse.cdt.launch.internal.LocalCDILaunchDelegate.launch(LocalCDILaunchDelegate.java:70) + at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:854) + at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:703) + at org.eclipse.debug.internal.ui.DebugUIPlugin.buildAndLaunch(DebugUIPlugin.java:937) + at org.eclipse.debug.internal.ui.DebugUIPlugin$8.run(DebugUIPlugin.java:1141) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54) + +!ENTRY org.eclipse.cdt.launch 4 150 2014-03-14 15:59:26.946 +!MESSAGE Error starting process. +!STACK 0 +java.io.IOException: Cannot run program "C:\Users\gongal\Desktop\MCTEST\DE0-nano-HD\Software\MCTest\MCTest.elf": Launching failed + at org.eclipse.cdt.utils.spawner.Spawner.exec(Spawner.java:347) + at org.eclipse.cdt.utils.spawner.Spawner.(Spawner.java:89) + at org.eclipse.cdt.utils.spawner.ProcessFactory.exec(ProcessFactory.java:89) + at org.eclipse.cdt.launch.internal.LocalCDILaunchDelegate.exec(LocalCDILaunchDelegate.java:370) + at org.eclipse.cdt.launch.internal.LocalCDILaunchDelegate.runLocalApplication(LocalCDILaunchDelegate.java:96) + at org.eclipse.cdt.launch.internal.LocalCDILaunchDelegate.launch(LocalCDILaunchDelegate.java:70) + at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:854) + at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:703) + at org.eclipse.debug.internal.ui.DebugUIPlugin.buildAndLaunch(DebugUIPlugin.java:937) + at org.eclipse.debug.internal.ui.DebugUIPlugin$8.run(DebugUIPlugin.java:1141) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54) +!SUBENTRY 1 org.eclipse.cdt.launch 4 150 2014-03-14 15:59:26.946 +!MESSAGE Cannot run program "C:\Users\gongal\Desktop\MCTEST\DE0-nano-HD\Software\MCTest\MCTest.elf": Launching failed +!STACK 0 +java.io.IOException: Cannot run program "C:\Users\gongal\Desktop\MCTEST\DE0-nano-HD\Software\MCTest\MCTest.elf": Launching failed + at org.eclipse.cdt.utils.spawner.Spawner.exec(Spawner.java:347) + at org.eclipse.cdt.utils.spawner.Spawner.(Spawner.java:89) + at org.eclipse.cdt.utils.spawner.ProcessFactory.exec(ProcessFactory.java:89) + at org.eclipse.cdt.launch.internal.LocalCDILaunchDelegate.exec(LocalCDILaunchDelegate.java:370) + at org.eclipse.cdt.launch.internal.LocalCDILaunchDelegate.runLocalApplication(LocalCDILaunchDelegate.java:96) + at org.eclipse.cdt.launch.internal.LocalCDILaunchDelegate.launch(LocalCDILaunchDelegate.java:70) + at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:854) + at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:703) + at org.eclipse.debug.internal.ui.DebugUIPlugin.buildAndLaunch(DebugUIPlugin.java:937) + at org.eclipse.debug.internal.ui.DebugUIPlugin$8.run(DebugUIPlugin.java:1141) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54) + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 15:59:36.452 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 15:59:38.615 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 15:59:51.045 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 15:59:51.465 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 15:59:53.130 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 16:00:21.544 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 16:00:21.962 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 16:00:23.609 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 16:01:08.635 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 16:01:09.265 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 16:01:10.917 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 16:02:12.143 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 16:02:12.597 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 16:02:14.262 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 16:05:51.823 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 16:05:52.680 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 16:05:54.334 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 16:06:09.172 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 16:06:09.574 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 16:06:11.225 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 16:07:37.851 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 16:07:38.560 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 16:07:40.211 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 16:07:57.413 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 16:07:57.848 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 16:07:59.497 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 16:09:00.512 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 16:09:00.942 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 16:09:02.610 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 16:10:21.116 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 16:10:21.537 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 16:10:23.186 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 16:48:57.657 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 4 0 2014-03-14 16:49:02.892 +!MESSAGE Unable to validate connection settings. +!STACK 0 +java.lang.Exception: Connected system ID hash not found on target at expected base address. + at com.altera.embeddedsw.flash.model.internal.SystemConsoleConnectionModel.assertTrue(SystemConsoleConnectionModel.java:645) + at com.altera.embeddedsw.flash.model.internal.SystemConsoleConnectionModel.validateSystemId(SystemConsoleConnectionModel.java:589) + at com.altera.embeddedsw.flash.model.internal.SystemConsoleConnectionModel.validateConnectionSettings(SystemConsoleConnectionModel.java:511) + at com.altera.sbtgui.launch.hardware.AbstractNios2CLaunchDelegate.launch(AbstractNios2CLaunchDelegate.java:115) + at com.altera.sbtgui.launch.hardware.Nios2HardwareLaunchDelegate.launch(Nios2HardwareLaunchDelegate.java:98) + at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:854) + at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:703) + at org.eclipse.debug.internal.ui.DebugUIPlugin.buildAndLaunch(DebugUIPlugin.java:937) + at org.eclipse.debug.internal.ui.DebugUIPlugin$8.run(DebugUIPlugin.java:1141) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54) + +!ENTRY com.altera.sbtgui.launch 4 0 2014-03-14 16:49:02.897 +!MESSAGE Unable to validate connection settings. +!STACK 0 +java.lang.Exception: Connected system ID hash not found on target at expected base address. + at com.altera.embeddedsw.flash.model.internal.SystemConsoleConnectionModel.assertTrue(SystemConsoleConnectionModel.java:645) + at com.altera.embeddedsw.flash.model.internal.SystemConsoleConnectionModel.validateSystemId(SystemConsoleConnectionModel.java:589) + at com.altera.embeddedsw.flash.model.internal.SystemConsoleConnectionModel.validateConnectionSettings(SystemConsoleConnectionModel.java:511) + at com.altera.sbtgui.launch.hardware.AbstractNios2CLaunchDelegate.launch(AbstractNios2CLaunchDelegate.java:115) + at com.altera.sbtgui.launch.hardware.Nios2HardwareLaunchDelegate.launch(Nios2HardwareLaunchDelegate.java:98) + at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:854) + at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:703) + at org.eclipse.debug.internal.ui.DebugUIPlugin.buildAndLaunch(DebugUIPlugin.java:937) + at org.eclipse.debug.internal.ui.DebugUIPlugin$8.run(DebugUIPlugin.java:1141) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54) +!SESSION 2014-03-14 16:52:20.565 ----------------------------------------------- +eclipse.buildId=M20120208-0800 +java.version=1.6.0_23 +java.vendor=Sun Microsystems Inc. +BootLoader constants: OS=win32, ARCH=x86, WS=win32, NL=en_CA +Framework arguments: -product org.eclipse.epp.package.cpp.product -perspective com.altera.sbtgui.ui.cPerspective +Command-line arguments: -os win32 -ws win32 -arch x86 -product org.eclipse.epp.package.cpp.product -perspective com.altera.sbtgui.ui.cPerspective + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 16:52:35.117 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 16:52:36.764 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 4 0 2014-03-14 16:59:38.137 +!MESSAGE Unable to validate connection settings. +!STACK 0 +java.lang.Exception: Connected system ID hash not found on target at expected base address. + at com.altera.embeddedsw.flash.model.internal.SystemConsoleConnectionModel.assertTrue(SystemConsoleConnectionModel.java:645) + at com.altera.embeddedsw.flash.model.internal.SystemConsoleConnectionModel.validateSystemId(SystemConsoleConnectionModel.java:589) + at com.altera.embeddedsw.flash.model.internal.SystemConsoleConnectionModel.validateConnectionSettings(SystemConsoleConnectionModel.java:511) + at com.altera.sbtgui.launch.hardware.AbstractNios2CLaunchDelegate.launch(AbstractNios2CLaunchDelegate.java:115) + at com.altera.sbtgui.launch.hardware.Nios2HardwareLaunchDelegate.launch(Nios2HardwareLaunchDelegate.java:98) + at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:854) + at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:703) + at org.eclipse.debug.internal.ui.DebugUIPlugin.buildAndLaunch(DebugUIPlugin.java:937) + at org.eclipse.debug.internal.ui.DebugUIPlugin$8.run(DebugUIPlugin.java:1141) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54) + +!ENTRY com.altera.sbtgui.launch 4 0 2014-03-14 16:59:38.141 +!MESSAGE Unable to validate connection settings. +!STACK 0 +java.lang.Exception: Connected system ID hash not found on target at expected base address. + at com.altera.embeddedsw.flash.model.internal.SystemConsoleConnectionModel.assertTrue(SystemConsoleConnectionModel.java:645) + at com.altera.embeddedsw.flash.model.internal.SystemConsoleConnectionModel.validateSystemId(SystemConsoleConnectionModel.java:589) + at com.altera.embeddedsw.flash.model.internal.SystemConsoleConnectionModel.validateConnectionSettings(SystemConsoleConnectionModel.java:511) + at com.altera.sbtgui.launch.hardware.AbstractNios2CLaunchDelegate.launch(AbstractNios2CLaunchDelegate.java:115) + at com.altera.sbtgui.launch.hardware.Nios2HardwareLaunchDelegate.launch(Nios2HardwareLaunchDelegate.java:98) + at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:854) + at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:703) + at org.eclipse.debug.internal.ui.DebugUIPlugin.buildAndLaunch(DebugUIPlugin.java:937) + at org.eclipse.debug.internal.ui.DebugUIPlugin$8.run(DebugUIPlugin.java:1141) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54) +!SESSION 2014-03-14 17:00:10.678 ----------------------------------------------- +eclipse.buildId=M20120208-0800 +java.version=1.6.0_23 +java.vendor=Sun Microsystems Inc. +BootLoader constants: OS=win32, ARCH=x86, WS=win32, NL=en_CA +Framework arguments: -product org.eclipse.epp.package.cpp.product -perspective com.altera.sbtgui.ui.cPerspective +Command-line arguments: -os win32 -ws win32 -arch x86 -product org.eclipse.epp.package.cpp.product -perspective com.altera.sbtgui.ui.cPerspective + +!ENTRY com.altera.sbtgui.launch 4 0 2014-03-14 17:00:46.556 +!MESSAGE Unable to validate connection settings. +!STACK 0 +java.lang.Exception + at com.altera.embeddedsw.flash.model.internal.SystemConsoleConnectionModel.validateConnectionSettings(SystemConsoleConnectionModel.java:555) + at com.altera.sbtgui.launch.hardware.AbstractNios2CLaunchDelegate.launch(AbstractNios2CLaunchDelegate.java:115) + at com.altera.sbtgui.launch.hardware.Nios2HardwareLaunchDelegate.launch(Nios2HardwareLaunchDelegate.java:98) + at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:854) + at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:703) + at org.eclipse.debug.internal.ui.DebugUIPlugin.buildAndLaunch(DebugUIPlugin.java:937) + at org.eclipse.debug.internal.ui.DebugUIPlugin$8.run(DebugUIPlugin.java:1141) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54) + +!ENTRY com.altera.sbtgui.launch 4 0 2014-03-14 17:00:46.564 +!MESSAGE Unable to validate connection settings. +!STACK 0 +java.lang.Exception + at com.altera.embeddedsw.flash.model.internal.SystemConsoleConnectionModel.validateConnectionSettings(SystemConsoleConnectionModel.java:555) + at com.altera.sbtgui.launch.hardware.AbstractNios2CLaunchDelegate.launch(AbstractNios2CLaunchDelegate.java:115) + at com.altera.sbtgui.launch.hardware.Nios2HardwareLaunchDelegate.launch(Nios2HardwareLaunchDelegate.java:98) + at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:854) + at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:703) + at org.eclipse.debug.internal.ui.DebugUIPlugin.buildAndLaunch(DebugUIPlugin.java:937) + at org.eclipse.debug.internal.ui.DebugUIPlugin$8.run(DebugUIPlugin.java:1141) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54) +!SESSION 2014-03-14 17:01:33.034 ----------------------------------------------- +eclipse.buildId=M20120208-0800 +java.version=1.6.0_23 +java.vendor=Sun Microsystems Inc. +BootLoader constants: OS=win32, ARCH=x86, WS=win32, NL=en_CA +Framework arguments: -product org.eclipse.epp.package.cpp.product -perspective com.altera.sbtgui.ui.cPerspective +Command-line arguments: -os win32 -ws win32 -arch x86 -product org.eclipse.epp.package.cpp.product -perspective com.altera.sbtgui.ui.cPerspective + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 17:01:57.301 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 17:01:58.953 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 17:03:15.567 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 17:03:16.234 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 17:03:17.878 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 17:03:30.719 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 17:03:31.124 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 17:03:32.771 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 17:04:41.469 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 17:04:41.905 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 17:04:43.549 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 17:05:23.179 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 17:05:24.819 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 17:06:06.499 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 17:06:06.940 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 17:06:08.584 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 17:06:58.540 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 17:06:58.937 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 17:07:00.587 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 17:12:10.299 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 17:12:10.696 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-14 17:12:12.340 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/Desktop/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] +!SESSION 2014-03-19 11:43:38.092 ----------------------------------------------- +eclipse.buildId=M20120208-0800 +java.version=1.6.0_23 +java.vendor=Sun Microsystems Inc. +BootLoader constants: OS=win32, ARCH=x86, WS=win32, NL=en_CA +Framework arguments: -product org.eclipse.epp.package.cpp.product -perspective com.altera.sbtgui.ui.cPerspective +Command-line arguments: -os win32 -ws win32 -arch x86 -product org.eclipse.epp.package.cpp.product -perspective com.altera.sbtgui.ui.cPerspective + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-19 11:52:36.188 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-19 11:52:37.889 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/NewRepARCap/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-19 11:57:12.478 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-19 11:57:14.147 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/NewRepARCap/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] +!SESSION 2014-03-20 16:01:01.325 ----------------------------------------------- +eclipse.buildId=M20120208-0800 +java.version=1.6.0_23 +java.vendor=Sun Microsystems Inc. +BootLoader constants: OS=win32, ARCH=x86, WS=win32, NL=en_CA +Framework arguments: -product org.eclipse.epp.package.cpp.product -perspective com.altera.sbtgui.ui.cPerspective +Command-line arguments: -os win32 -ws win32 -arch x86 -product org.eclipse.epp.package.cpp.product -perspective com.altera.sbtgui.ui.cPerspective + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-20 18:07:54.135 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-20 18:07:55.845 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/NewRepARCap/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-20 18:08:50.150 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-20 18:08:50.550 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-20 18:08:52.220 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/NewRepARCap/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-20 18:11:58.795 +!MESSAGE Terminated Launch with connection: 10USB-Blaster on localhost [USB-0] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-20 18:11:59.195 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-20 18:12:00.865 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/NewRepARCap/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-20 18:14:28.047 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --stop --sidp=0x20010a0 --id=0x0 --timestamp=1394124174] + +!ENTRY com.altera.sbtgui.launch 1 0 2014-03-20 18:14:29.707 +!MESSAGE Executing: [C:/altera/12.1sp1/quartus\bin\cygwin\bin\bash.exe, -c, nios2-download '--cable=USB-Blaster on localhost [USB-0]' --device=1 --instance=0 --go --sidp=0x20010a0 --id=0x0 --timestamp=1394124174 /cygdrive/c/Users/gongal/NewRepARCap/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf] diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.mylyn/repositories.xml.zip b/MCTEST/DE0-nano-HD/Software/.metadata/.mylyn/repositories.xml.zip new file mode 100644 index 00000000..00aeb130 Binary files /dev/null and b/MCTEST/DE0-nano-HD/Software/.metadata/.mylyn/repositories.xml.zip differ diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.cdt.codan.ui/dialog_settings.xml b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.cdt.codan.ui/dialog_settings.xml new file mode 100644 index 00000000..39970e81 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.cdt.codan.ui/dialog_settings.xml @@ -0,0 +1,4 @@ + +
+ +
diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.cdt.core/.log b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.cdt.core/.log new file mode 100644 index 00000000..e4f0eacb --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.cdt.core/.log @@ -0,0 +1,15 @@ +*** SESSION Mar 06, 2014 10:00:43.86 ------------------------------------------- +*** SESSION Mar 06, 2014 11:47:32.49 ------------------------------------------- +*** SESSION Mar 10, 2014 16:30:59.48 ------------------------------------------- +*** SESSION Mar 14, 2014 08:58:25.89 ------------------------------------------- +*** SESSION Mar 14, 2014 14:14:22.06 ------------------------------------------- +*** SESSION Mar 14, 2014 15:20:52.72 ------------------------------------------- +*** SESSION Mar 14, 2014 15:59:07.38 ------------------------------------------- +*** SESSION Mar 14, 2014 16:52:23.75 ------------------------------------------- +*** SESSION Mar 14, 2014 17:00:13.53 ------------------------------------------- +*** SESSION Mar 14, 2014 17:01:44.06 ------------------------------------------- +*** SESSION Mar 19, 2014 11:41:31.61 ------------------------------------------- +*** SESSION Mar 19, 2014 11:43:44.43 ------------------------------------------- +*** SESSION Mar 20, 2014 12:42:31.63 ------------------------------------------- +*** SESSION Mar 20, 2014 16:00:43.08 ------------------------------------------- +*** SESSION Mar 20, 2014 16:01:05.21 ------------------------------------------- diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.cdt.core/MCTest.1394125448030.pdom b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.cdt.core/MCTest.1394125448030.pdom new file mode 100644 index 00000000..e8cbb12b Binary files /dev/null and b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.cdt.core/MCTest.1394125448030.pdom differ diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.cdt.core/MCTest_bsp.1394125444538.pdom b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.cdt.core/MCTest_bsp.1394125444538.pdom new file mode 100644 index 00000000..1044c055 Binary files /dev/null and b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.cdt.core/MCTest_bsp.1394125444538.pdom differ diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0/obj/default/.force_relink b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.cdt.make.core/.log similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0/obj/default/.force_relink rename to MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.cdt.make.core/.log diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.cdt.make.core/MCTest.sc b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.cdt.make.core/MCTest.sc new file mode 100644 index 00000000..448d748d --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.cdt.make.core/MCTest.sc @@ -0,0 +1,461 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.cdt.make.core/MCTest_bsp.sc b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.cdt.make.core/MCTest_bsp.sc new file mode 100644 index 00000000..e55f22c2 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.cdt.make.core/MCTest_bsp.sc @@ -0,0 +1,437 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.cdt.ui/MCTest.build.log b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.cdt.ui/MCTest.build.log new file mode 100644 index 00000000..626a824e --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.cdt.ui/MCTest.build.log @@ -0,0 +1,10 @@ + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.cdt.ui/MCTest_bsp.build.log b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.cdt.ui/MCTest_bsp.build.log new file mode 100644 index 00000000..0afb54d1 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.cdt.ui/MCTest_bsp.build.log @@ -0,0 +1,7 @@ + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.cdt.ui/dialog_settings.xml b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.cdt.ui/dialog_settings.xml new file mode 100644 index 00000000..d0a35072 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.cdt.ui/dialog_settings.xml @@ -0,0 +1,17 @@ + +
+
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diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.cdt.ui/global-build.log b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.cdt.ui/global-build.log new file mode 100644 index 00000000..86d2df6d --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.cdt.ui/global-build.log @@ -0,0 +1,7618 @@ + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling MotorHandler.cpp to obj/default/MotorHandler.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/MotorHandler.o MotorHandler.cpp +Info: Compiling main.cpp to obj/default/main.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/main.o main.cpp +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010a0 --timestamp 1394124174 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD" --jdi C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.jdi --sopcinfo C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo +Info: (MCTest.elf) 140 KBytes program size (code + initialized data). +Info: 16236 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling main.cpp to obj/default/main.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/main.o main.cpp +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010a0 --timestamp 1394124174 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD" --jdi C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.jdi --sopcinfo C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo +Info: (MCTest.elf) 140 KBytes program size (code + initialized data). +Info: 16236 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling main.cpp to obj/default/main.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/main.o main.cpp +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010a0 --timestamp 1394124174 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD" --jdi C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.jdi --sopcinfo C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo +Info: (MCTest.elf) 140 KBytes program size (code + initialized data). +Info: 16236 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling MotorHandler.cpp to obj/default/MotorHandler.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/MotorHandler.o MotorHandler.cpp +MotorHandler.cpp: In member function 'Status MotorHandler::init()': +MotorHandler.cpp:36: warning: format '%s' expects type 'char*', but argument 2 has type 'alt_up_rs232_dev*' +Info: Linking MCTest.elf +MotorHandler.cpp:36: warning: format '%s' expects type 'char*', but argument 2 has type 'alt_up_rs232_dev*' +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010a0 --timestamp 1394124174 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD" --jdi C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.jdi --sopcinfo C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo +Info: (MCTest.elf) 140 KBytes program size (code + initialized data). +Info: 16236 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling MotorHandler.cpp to obj/default/MotorHandler.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/MotorHandler.o MotorHandler.cpp +MotorHandler.cpp: In member function 'Status MotorHandler::init()': +Info: Linking MCTest.elf +MotorHandler.cpp:36: warning: format '%d' expects type 'int', but argument 2 has type 'alt_up_rs232_dev*' +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/main.o -lm +MotorHandler.cpp:36: warning: format '%d' expects type 'int', but argument 2 has type 'alt_up_rs232_dev*' +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010a0 --timestamp 1394124174 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD" --jdi C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.jdi --sopcinfo C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo +Info: (MCTest.elf) 140 KBytes program size (code + initialized data). +Info: 16236 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling MotorHandler.cpp to obj/default/MotorHandler.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/MotorHandler.o MotorHandler.cpp +MotorHandler.cpp: In member function 'Status MotorHandler::init()': +MotorHandler.cpp:34: error: expected `;' before '__builtin_stwio' +MotorHandler.cpp:37: warning: format '%d' expects type 'int', but argument 2 has type 'alt_up_rs232_dev*' +MotorHandler.cpp:37: warning: format '%d' expects type 'int', but argument 2 has type 'alt_up_rs232_dev*' +make: *** [obj/default/MotorHandler.o] Error 1 + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling MotorHandler.cpp to obj/default/MotorHandler.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/MotorHandler.o MotorHandler.cpp +MotorHandler.cpp: In member function 'Status MotorHandler::init()': +Info: Linking MCTest.elf +MotorHandler.cpp:37: warning: format '%d' expects type 'int', but argument 2 has type 'alt_up_rs232_dev*' +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/main.o -lm +MotorHandler.cpp:37: warning: format '%d' expects type 'int', but argument 2 has type 'alt_up_rs232_dev*' +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010a0 --timestamp 1394124174 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD" --jdi C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.jdi --sopcinfo C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo +Info: (MCTest.elf) 140 KBytes program size (code + initialized data). +Info: 16236 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling MotorHandler.cpp to obj/default/MotorHandler.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/MotorHandler.o MotorHandler.cpp +MotorHandler.cpp: In member function 'Status MotorHandler::init()': +MotorHandler.cpp:37: warning: format '%d' expects type 'int', but argument 2 has type 'alt_up_rs232_dev*' +Info: Compiling main.cpp to obj/default/main.o +MotorHandler.cpp:37: warning: format '%d' expects type 'int', but argument 2 has type 'alt_up_rs232_dev*' +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/main.o main.cpp +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010a0 --timestamp 1394124174 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD" --jdi C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.jdi --sopcinfo C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo +Info: (MCTest.elf) 140 KBytes program size (code + initialized data). +Info: 16236 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling MotorHandler.cpp to obj/default/MotorHandler.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/MotorHandler.o MotorHandler.cpp +MotorHandler.cpp: In member function 'Status MotorHandler::init()': +MotorHandler.cpp:36: warning: format '%d' expects type 'int', but argument 2 has type 'alt_up_rs232_dev*' +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/main.o -lm +MotorHandler.cpp:36: warning: format '%d' expects type 'int', but argument 2 has type 'alt_up_rs232_dev*' +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010a0 --timestamp 1394124174 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD" --jdi C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.jdi --sopcinfo C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo +Info: (MCTest.elf) 140 KBytes program size (code + initialized data). +Info: 16236 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling main.cpp to obj/default/main.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/main.o main.cpp +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010a0 --timestamp 1394124174 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD" --jdi C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.jdi --sopcinfo C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo +Info: (MCTest.elf) 140 KBytes program size (code + initialized data). +Info: 16236 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling main.cpp to obj/default/main.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/main.o main.cpp +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010a0 --timestamp 1394124174 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD" --jdi C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.jdi --sopcinfo C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo +Info: (MCTest.elf) 140 KBytes program size (code + initialized data). +Info: 16236 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling main.cpp to obj/default/main.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/main.o main.cpp +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010a0 --timestamp 1394124174 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD" --jdi C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.jdi --sopcinfo C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo +Info: (MCTest.elf) 140 KBytes program size (code + initialized data). +Info: 16236 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling main.cpp to obj/default/main.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/main.o main.cpp +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010a0 --timestamp 1394124174 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD" --jdi C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.jdi --sopcinfo C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo +Info: (MCTest.elf) 140 KBytes program size (code + initialized data). +Info: 16236 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling MotorHandler.cpp to obj/default/MotorHandler.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/MotorHandler.o MotorHandler.cpp +MotorHandler.cpp: In member function 'Status MotorHandler::init()': +Info: Compiling main.cpp to obj/default/main.o +MotorHandler.cpp:36: warning: format '%d' expects type 'int', but argument 2 has type 'alt_up_rs232_dev*' +MotorHandler.cpp:36: warning: format '%d' expects type 'int', but argument 2 has type 'alt_up_rs232_dev*' +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/main.o main.cpp +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010a0 --timestamp 1394124174 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD" --jdi C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.jdi --sopcinfo C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo +Info: (MCTest.elf) 140 KBytes program size (code + initialized data). +Info: 16236 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling MotorHandler.cpp to obj/default/MotorHandler.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/MotorHandler.o MotorHandler.cpp +Info: Compiling main.cpp to obj/default/main.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/main.o main.cpp +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010a0 --timestamp 1394124174 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD" --jdi C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.jdi --sopcinfo C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo +Info: (MCTest.elf) 140 KBytes program size (code + initialized data). +Info: 16236 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling main.cpp to obj/default/main.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/main.o main.cpp +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010a0 --timestamp 1394124174 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD" --jdi C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.jdi --sopcinfo C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo +Info: (MCTest.elf) 140 KBytes program size (code + initialized data). +Info: 16236 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling main.cpp to obj/default/main.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/main.o main.cpp +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010a0 --timestamp 1394124174 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD" --jdi C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.jdi --sopcinfo C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo +Info: (MCTest.elf) 140 KBytes program size (code + initialized data). +Info: 16236 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling main.cpp to obj/default/main.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/main.o main.cpp +main.cpp: In function 'void mc_task(void*)': +Info: Linking MCTest.elf +main.cpp:71: warning: converting to non-pointer type 'int' from NULL +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/main.o -lm +main.cpp:71: warning: NULL used in arithmetic +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010a0 --timestamp 1394124174 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD" --jdi C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.jdi --sopcinfo C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo +Info: (MCTest.elf) 140 KBytes program size (code + initialized data). +Info: 16236 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling main.cpp to obj/default/main.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/main.o main.cpp +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010a0 --timestamp 1394124174 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD" --jdi C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.jdi --sopcinfo C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo +Info: (MCTest.elf) 140 KBytes program size (code + initialized data). +Info: 16236 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Clean-only build of configuration Nios II for project MCTest **** + +make clean +[MCTest clean complete] + +**** Build Finished **** + +**** Clean-only build of configuration Nios II for project MCTest_bsp **** + +make clean +[BSP clean complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +Compiling alt_alarm_start.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_alarm_start.o HAL/src/alt_alarm_start.c +Compiling alt_busy_sleep.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_busy_sleep.o HAL/src/alt_busy_sleep.c +Compiling alt_close.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_close.o HAL/src/alt_close.c +Compiling alt_dcache_flush.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dcache_flush.o HAL/src/alt_dcache_flush.c +Compiling alt_dcache_flush_all.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dcache_flush_all.o HAL/src/alt_dcache_flush_all.c +Compiling alt_dcache_flush_no_writeback.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dcache_flush_no_writeback.o HAL/src/alt_dcache_flush_no_writeback.c +Compiling alt_dev.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dev.o HAL/src/alt_dev.c +Compiling alt_dev_llist_insert.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dev_llist_insert.o HAL/src/alt_dev_llist_insert.c +Compiling alt_dma_rxchan_open.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dma_rxchan_open.o HAL/src/alt_dma_rxchan_open.c +Compiling alt_dma_txchan_open.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dma_txchan_open.o HAL/src/alt_dma_txchan_open.c +Compiling alt_do_ctors.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_do_ctors.o HAL/src/alt_do_ctors.c +Compiling alt_do_dtors.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_do_dtors.o HAL/src/alt_do_dtors.c +Compiling alt_environ.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_environ.o HAL/src/alt_environ.c +Compiling alt_errno.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_errno.o HAL/src/alt_errno.c +Compiling alt_exception_entry.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_exception_entry.o HAL/src/alt_exception_entry.S +Compiling alt_exception_muldiv.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_exception_muldiv.o HAL/src/alt_exception_muldiv.S +Compiling alt_exception_trap.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_exception_trap.o HAL/src/alt_exception_trap.S +Compiling alt_execve.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_execve.o HAL/src/alt_execve.c +Compiling alt_exit.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_exit.o HAL/src/alt_exit.c +Compiling alt_fcntl.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fcntl.o HAL/src/alt_fcntl.c +Compiling alt_fd_lock.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fd_lock.o HAL/src/alt_fd_lock.c +Compiling alt_fd_unlock.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fd_unlock.o HAL/src/alt_fd_unlock.c +Compiling alt_find_dev.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_find_dev.o HAL/src/alt_find_dev.c +Compiling alt_find_file.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_find_file.o HAL/src/alt_find_file.c +Compiling alt_flash_dev.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_flash_dev.o HAL/src/alt_flash_dev.c +Compiling alt_fork.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fork.o HAL/src/alt_fork.c +Compiling alt_fs_reg.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fs_reg.o HAL/src/alt_fs_reg.c +Compiling alt_fstat.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fstat.o HAL/src/alt_fstat.c +Compiling alt_get_fd.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_get_fd.o HAL/src/alt_get_fd.c +Compiling alt_getchar.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_getchar.o HAL/src/alt_getchar.c +Compiling alt_getpid.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_getpid.o HAL/src/alt_getpid.c +Compiling alt_gettod.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_gettod.o HAL/src/alt_gettod.c +Compiling alt_gmon.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_gmon.o HAL/src/alt_gmon.c +Compiling alt_icache_flush.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_icache_flush.o HAL/src/alt_icache_flush.c +Compiling alt_icache_flush_all.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_icache_flush_all.o HAL/src/alt_icache_flush_all.c +Compiling alt_iic.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_iic.o HAL/src/alt_iic.c +Compiling alt_iic_isr_register.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_iic_isr_register.o HAL/src/alt_iic_isr_register.c +Compiling alt_instruction_exception_entry.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_instruction_exception_entry.o HAL/src/alt_instruction_exception_entry.c +Compiling alt_instruction_exception_register.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_instruction_exception_register.o HAL/src/alt_instruction_exception_register.c +Compiling alt_io_redirect.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_io_redirect.o HAL/src/alt_io_redirect.c +Compiling alt_ioctl.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_ioctl.o HAL/src/alt_ioctl.c +Compiling alt_irq_entry.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_irq_entry.o HAL/src/alt_irq_entry.S +Compiling alt_irq_handler.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_irq_handler.o HAL/src/alt_irq_handler.c +Compiling alt_irq_register.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_irq_register.o HAL/src/alt_irq_register.c +Compiling alt_irq_vars.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_irq_vars.o HAL/src/alt_irq_vars.c +Compiling alt_isatty.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_isatty.o HAL/src/alt_isatty.c +Compiling alt_kill.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_kill.o HAL/src/alt_kill.c +Compiling alt_link.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_link.o HAL/src/alt_link.c +Compiling alt_load.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_load.o HAL/src/alt_load.c +Compiling alt_log_macro.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_log_macro.o HAL/src/alt_log_macro.S +Compiling alt_log_printf.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_log_printf.o HAL/src/alt_log_printf.c +Compiling alt_lseek.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_lseek.o HAL/src/alt_lseek.c +Compiling alt_main.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_main.o HAL/src/alt_main.c +Compiling alt_mcount.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_mcount.o HAL/src/alt_mcount.S +Compiling alt_open.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_open.o HAL/src/alt_open.c +Compiling alt_printf.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_printf.o HAL/src/alt_printf.c +Compiling alt_putchar.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_putchar.o HAL/src/alt_putchar.c +Compiling alt_putstr.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_putstr.o HAL/src/alt_putstr.c +Compiling alt_read.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_read.o HAL/src/alt_read.c +Compiling alt_release_fd.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_release_fd.o HAL/src/alt_release_fd.c +Compiling alt_remap_cached.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_remap_cached.o HAL/src/alt_remap_cached.c +Compiling alt_remap_uncached.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_remap_uncached.o HAL/src/alt_remap_uncached.c +Compiling alt_rename.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_rename.o HAL/src/alt_rename.c +Compiling alt_sbrk.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_sbrk.o HAL/src/alt_sbrk.c +Compiling alt_settod.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_settod.o HAL/src/alt_settod.c +Compiling alt_software_exception.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_software_exception.o HAL/src/alt_software_exception.S +Compiling alt_stat.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_stat.o HAL/src/alt_stat.c +Compiling alt_tick.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_tick.o HAL/src/alt_tick.c +Compiling alt_times.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_times.o HAL/src/alt_times.c +Compiling alt_uncached_free.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_uncached_free.o HAL/src/alt_uncached_free.c +Compiling alt_uncached_malloc.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_uncached_malloc.o HAL/src/alt_uncached_malloc.c +Compiling alt_unlink.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_unlink.o HAL/src/alt_unlink.c +Compiling alt_usleep.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_usleep.o HAL/src/alt_usleep.c +Compiling alt_wait.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_wait.o HAL/src/alt_wait.c +Compiling alt_write.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_write.o HAL/src/alt_write.c +Compiling altera_nios2_qsys_irq.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/altera_nios2_qsys_irq.o HAL/src/altera_nios2_qsys_irq.c +Compiling crt0.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/crt0.o HAL/src/crt0.S +Compiling os_cpu_a.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/os_cpu_a.o HAL/src/os_cpu_a.S +Compiling os_cpu_c.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/os_cpu_c.o HAL/src/os_cpu_c.c +Compiling alt_env_lock.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/alt_env_lock.o UCOSII/src/alt_env_lock.c +Compiling alt_malloc_lock.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/alt_malloc_lock.o UCOSII/src/alt_malloc_lock.c +Compiling os_core.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_core.o UCOSII/src/os_core.c +Compiling os_dbg.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_dbg.o UCOSII/src/os_dbg.c +Compiling os_flag.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_flag.o UCOSII/src/os_flag.c +Compiling os_mbox.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_mbox.o UCOSII/src/os_mbox.c +Compiling os_mem.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_mem.o UCOSII/src/os_mem.c +Compiling os_mutex.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_mutex.o UCOSII/src/os_mutex.c +Compiling os_q.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_q.o UCOSII/src/os_q.c +Compiling os_sem.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_sem.o UCOSII/src/os_sem.c +Compiling os_task.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_task.o UCOSII/src/os_task.c +Compiling os_time.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_time.o UCOSII/src/os_time.c +Compiling os_tmr.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_tmr.o UCOSII/src/os_tmr.c +Compiling alt_sys_init.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/alt_sys_init.o alt_sys_init.c +Compiling altera_avalon_jtag_uart_fd.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_jtag_uart_fd.o drivers/src/altera_avalon_jtag_uart_fd.c +Compiling altera_avalon_jtag_uart_init.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_jtag_uart_init.o drivers/src/altera_avalon_jtag_uart_init.c +Compiling altera_avalon_jtag_uart_ioctl.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_jtag_uart_ioctl.o drivers/src/altera_avalon_jtag_uart_ioctl.c +Compiling altera_avalon_jtag_uart_read.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_jtag_uart_read.o drivers/src/altera_avalon_jtag_uart_read.c +Compiling altera_avalon_jtag_uart_write.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_jtag_uart_write.o drivers/src/altera_avalon_jtag_uart_write.c +Compiling altera_avalon_sysid_qsys.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_sysid_qsys.o drivers/src/altera_avalon_sysid_qsys.c +Compiling altera_avalon_timer_sc.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_timer_sc.o drivers/src/altera_avalon_timer_sc.c +Compiling altera_avalon_timer_ts.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_timer_ts.o drivers/src/altera_avalon_timer_ts.c +Compiling altera_avalon_timer_vars.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_timer_vars.o drivers/src/altera_avalon_timer_vars.c +Compiling altera_avalon_uart_fd.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_uart_fd.o drivers/src/altera_avalon_uart_fd.c +Compiling altera_avalon_uart_init.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_uart_init.o drivers/src/altera_avalon_uart_init.c +Compiling altera_avalon_uart_ioctl.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_uart_ioctl.o drivers/src/altera_avalon_uart_ioctl.c +Compiling altera_avalon_uart_read.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_uart_read.o drivers/src/altera_avalon_uart_read.c +Compiling altera_avalon_uart_write.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_uart_write.o drivers/src/altera_avalon_uart_write.c +drivers/src/altera_up_avalon_rs232.c: In function 'alt_up_rs232_read_fd': +Compiling altera_up_avalon_rs232.c... +drivers/src/altera_up_avalon_rs232.c:110: warning: pointer targets in passing argument 2 of 'alt_up_rs232_read_data' differ in signedness +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_up_avalon_rs232.o drivers/src/altera_up_avalon_rs232.c +Creating libucosii_bsp.a... +rm -f -f libucosii_bsp.a +nios2-elf-ar -src libucosii_bsp.a obj/HAL/src/alt_alarm_start.o obj/HAL/src/alt_busy_sleep.o obj/HAL/src/alt_close.o obj/HAL/src/alt_dcache_flush.o obj/HAL/src/alt_dcache_flush_all.o obj/HAL/src/alt_dcache_flush_no_writeback.o obj/HAL/src/alt_dev.o obj/HAL/src/alt_dev_llist_insert.o obj/HAL/src/alt_dma_rxchan_open.o obj/HAL/src/alt_dma_txchan_open.o obj/HAL/src/alt_do_ctors.o obj/HAL/src/alt_do_dtors.o obj/HAL/src/alt_environ.o obj/HAL/src/alt_errno.o obj/HAL/src/alt_exception_entry.o obj/HAL/src/alt_exception_muldiv.o obj/HAL/src/alt_exception_trap.o obj/HAL/src/alt_execve.o obj/HAL/src/alt_exit.o obj/HAL/src/alt_fcntl.o obj/HAL/src/alt_fd_lock.o obj/HAL/src/alt_fd_unlock.o obj/HAL/src/alt_find_dev.o obj/HAL/src/alt_find_file.o obj/HAL/src/alt_flash_dev.o obj/HAL/src/alt_fork.o obj/HAL/src/alt_fs_reg.o obj/HAL/src/alt_fstat.o obj/HAL/src/alt_get_fd.o obj/HAL/src/alt_getchar.o obj/HAL/src/alt_getpid.o obj/HAL/src/alt_gettod.o obj/HAL/src/alt_gmon.o obj/HAL/src/alt_icache_flush.o obj/HAL/src/alt_icache_flush_all.o obj/HAL/src/alt_iic.o obj/HAL/src/alt_iic_isr_register.o obj/HAL/src/alt_instruction_exception_entry.o obj/HAL/src/alt_instruction_exception_register.o obj/HAL/src/alt_io_redirect.o obj/HAL/src/alt_ioctl.o obj/HAL/src/alt_irq_entry.o obj/HAL/src/alt_irq_handler.o obj/HAL/src/alt_irq_register.o obj/HAL/src/alt_irq_vars.o obj/HAL/src/alt_isatty.o obj/HAL/src/alt_kill.o obj/HAL/src/alt_link.o obj/HAL/src/alt_load.o obj/HAL/src/alt_log_macro.o obj/HAL/src/alt_log_printf.o obj/HAL/src/alt_lseek.o obj/HAL/src/alt_main.o obj/HAL/src/alt_mcount.o obj/HAL/src/alt_open.o obj/HAL/src/alt_printf.o obj/HAL/src/alt_putchar.o obj/HAL/src/alt_putstr.o obj/HAL/src/alt_read.o obj/HAL/src/alt_release_fd.o obj/HAL/src/alt_remap_cached.o obj/HAL/src/alt_remap_uncached.o obj/HAL/src/alt_rename.o obj/HAL/src/alt_sbrk.o obj/HAL/src/alt_settod.o obj/HAL/src/alt_software_exception.o obj/HAL/src/alt_stat.o obj/HAL/src/alt_tick.o obj/HAL/src/alt_times.o obj/HAL/src/alt_uncached_free.o obj/HAL/src/alt_uncached_malloc.o obj/HAL/src/alt_unlink.o obj/HAL/src/alt_usleep.o obj/HAL/src/alt_wait.o obj/HAL/src/alt_write.o obj/HAL/src/altera_nios2_qsys_irq.o obj/HAL/src/crt0.o obj/HAL/src/os_cpu_a.o obj/HAL/src/os_cpu_c.o obj/UCOSII/src/alt_env_lock.o obj/UCOSII/src/alt_malloc_lock.o obj/UCOSII/src/os_core.o obj/UCOSII/src/os_dbg.o obj/UCOSII/src/os_flag.o obj/UCOSII/src/os_mbox.o obj/UCOSII/src/os_mem.o obj/UCOSII/src/os_mutex.o obj/UCOSII/src/os_q.o obj/UCOSII/src/os_sem.o obj/UCOSII/src/os_task.o obj/UCOSII/src/os_time.o obj/UCOSII/src/os_tmr.o obj/alt_sys_init.o obj/drivers/src/altera_avalon_jtag_uart_fd.o obj/drivers/src/altera_avalon_jtag_uart_init.o obj/drivers/src/altera_avalon_jtag_uart_ioctl.o obj/drivers/src/altera_avalon_jtag_uart_read.o obj/drivers/src/altera_avalon_jtag_uart_write.o obj/drivers/src/altera_avalon_sysid_qsys.o obj/drivers/src/altera_avalon_timer_sc.o obj/drivers/src/altera_avalon_timer_ts.o obj/drivers/src/altera_avalon_timer_vars.o obj/drivers/src/altera_avalon_uart_fd.o obj/drivers/src/altera_avalon_uart_init.o obj/drivers/src/altera_avalon_uart_ioctl.o obj/drivers/src/altera_avalon_uart_read.o obj/drivers/src/altera_avalon_uart_write.o obj/drivers/src/altera_up_avalon_rs232.o +[BSP build complete] +Info: Compiling MotorHandler.cpp to obj/default/MotorHandler.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/MotorHandler.o MotorHandler.cpp +Info: Compiling main.cpp to obj/default/main.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/main.o main.cpp +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010a0 --timestamp 1394124174 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD" --jdi C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.jdi --sopcinfo C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo +Info: (MCTest.elf) 140 KBytes program size (code + initialized data). + 0 [main] perl 2228 child_info_fork::abort: C:\altera\12.1sp1\quartus\bin\cygwin\bin\cyggcc_s-1.dll: Loaded to different address: parent(0x2B0000) != child(0x3B0000) +Info: 16236 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling main.cpp to obj/default/main.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/main.o main.cpp +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010a0 --timestamp 1394124174 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD" --jdi C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.jdi --sopcinfo C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo +Info: (MCTest.elf) 140 KBytes program size (code + initialized data). +Info: 16236 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Clean-only build of configuration Nios II for project MCTest **** + +make clean +[MCTest clean complete] + +**** Build Finished **** + +**** Clean-only build of configuration Nios II for project MCTest_bsp **** + +make clean +[BSP clean complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +Compiling alt_alarm_start.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_alarm_start.o HAL/src/alt_alarm_start.c +Compiling alt_busy_sleep.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_busy_sleep.o HAL/src/alt_busy_sleep.c +Compiling alt_close.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_close.o HAL/src/alt_close.c +Compiling alt_dcache_flush.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dcache_flush.o HAL/src/alt_dcache_flush.c +Compiling alt_dcache_flush_all.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dcache_flush_all.o HAL/src/alt_dcache_flush_all.c +Compiling alt_dcache_flush_no_writeback.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dcache_flush_no_writeback.o HAL/src/alt_dcache_flush_no_writeback.c +Compiling alt_dev.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dev.o HAL/src/alt_dev.c +Compiling alt_dev_llist_insert.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dev_llist_insert.o HAL/src/alt_dev_llist_insert.c +Compiling alt_dma_rxchan_open.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dma_rxchan_open.o HAL/src/alt_dma_rxchan_open.c +Compiling alt_dma_txchan_open.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dma_txchan_open.o HAL/src/alt_dma_txchan_open.c +Compiling alt_do_ctors.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_do_ctors.o HAL/src/alt_do_ctors.c +Compiling alt_do_dtors.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_do_dtors.o HAL/src/alt_do_dtors.c +Compiling alt_environ.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_environ.o HAL/src/alt_environ.c +Compiling alt_errno.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_errno.o HAL/src/alt_errno.c +Compiling alt_exception_entry.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_exception_entry.o HAL/src/alt_exception_entry.S +Compiling alt_exception_muldiv.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_exception_muldiv.o HAL/src/alt_exception_muldiv.S +Compiling alt_exception_trap.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_exception_trap.o HAL/src/alt_exception_trap.S +Compiling alt_execve.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_execve.o HAL/src/alt_execve.c +Compiling alt_exit.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_exit.o HAL/src/alt_exit.c +Compiling alt_fcntl.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fcntl.o HAL/src/alt_fcntl.c +Compiling alt_fd_lock.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fd_lock.o HAL/src/alt_fd_lock.c +Compiling alt_fd_unlock.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fd_unlock.o HAL/src/alt_fd_unlock.c +Compiling alt_find_dev.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_find_dev.o HAL/src/alt_find_dev.c +Compiling alt_find_file.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_find_file.o HAL/src/alt_find_file.c +Compiling alt_flash_dev.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_flash_dev.o HAL/src/alt_flash_dev.c +Compiling alt_fork.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fork.o HAL/src/alt_fork.c +Compiling alt_fs_reg.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fs_reg.o HAL/src/alt_fs_reg.c +Compiling alt_fstat.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fstat.o HAL/src/alt_fstat.c +Compiling alt_get_fd.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_get_fd.o HAL/src/alt_get_fd.c +Compiling alt_getchar.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_getchar.o HAL/src/alt_getchar.c +Compiling alt_getpid.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_getpid.o HAL/src/alt_getpid.c +Compiling alt_gettod.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_gettod.o HAL/src/alt_gettod.c +Compiling alt_gmon.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_gmon.o HAL/src/alt_gmon.c +Compiling alt_icache_flush.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_icache_flush.o HAL/src/alt_icache_flush.c +Compiling alt_icache_flush_all.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_icache_flush_all.o HAL/src/alt_icache_flush_all.c +Compiling alt_iic.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_iic.o HAL/src/alt_iic.c +Compiling alt_iic_isr_register.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_iic_isr_register.o HAL/src/alt_iic_isr_register.c +Compiling alt_instruction_exception_entry.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_instruction_exception_entry.o HAL/src/alt_instruction_exception_entry.c +Compiling alt_instruction_exception_register.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_instruction_exception_register.o HAL/src/alt_instruction_exception_register.c +Compiling alt_io_redirect.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_io_redirect.o HAL/src/alt_io_redirect.c +Compiling alt_ioctl.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_ioctl.o HAL/src/alt_ioctl.c +Compiling alt_irq_entry.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_irq_entry.o HAL/src/alt_irq_entry.S +Compiling alt_irq_handler.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_irq_handler.o HAL/src/alt_irq_handler.c +Compiling alt_irq_register.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_irq_register.o HAL/src/alt_irq_register.c +Compiling alt_irq_vars.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_irq_vars.o HAL/src/alt_irq_vars.c +Compiling alt_isatty.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_isatty.o HAL/src/alt_isatty.c +Compiling alt_kill.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_kill.o HAL/src/alt_kill.c +Compiling alt_link.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_link.o HAL/src/alt_link.c +Compiling alt_load.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_load.o HAL/src/alt_load.c +Compiling alt_log_macro.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_log_macro.o HAL/src/alt_log_macro.S +Compiling alt_log_printf.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_log_printf.o HAL/src/alt_log_printf.c +Compiling alt_lseek.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_lseek.o HAL/src/alt_lseek.c +Compiling alt_main.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_main.o HAL/src/alt_main.c +Compiling alt_mcount.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_mcount.o HAL/src/alt_mcount.S +Compiling alt_open.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_open.o HAL/src/alt_open.c +Compiling alt_printf.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_printf.o HAL/src/alt_printf.c +Compiling alt_putchar.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_putchar.o HAL/src/alt_putchar.c +Compiling alt_putstr.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_putstr.o HAL/src/alt_putstr.c +Compiling alt_read.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_read.o HAL/src/alt_read.c +Compiling alt_release_fd.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_release_fd.o HAL/src/alt_release_fd.c +Compiling alt_remap_cached.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_remap_cached.o HAL/src/alt_remap_cached.c +Compiling alt_remap_uncached.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_remap_uncached.o HAL/src/alt_remap_uncached.c +Compiling alt_rename.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_rename.o HAL/src/alt_rename.c +Compiling alt_sbrk.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_sbrk.o HAL/src/alt_sbrk.c +Compiling alt_settod.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_settod.o HAL/src/alt_settod.c +Compiling alt_software_exception.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_software_exception.o HAL/src/alt_software_exception.S +Compiling alt_stat.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_stat.o HAL/src/alt_stat.c +Compiling alt_tick.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_tick.o HAL/src/alt_tick.c +Compiling alt_times.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_times.o HAL/src/alt_times.c +Compiling alt_uncached_free.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_uncached_free.o HAL/src/alt_uncached_free.c +Compiling alt_uncached_malloc.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_uncached_malloc.o HAL/src/alt_uncached_malloc.c +Compiling alt_unlink.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_unlink.o HAL/src/alt_unlink.c +Compiling alt_usleep.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_usleep.o HAL/src/alt_usleep.c +Compiling alt_wait.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_wait.o HAL/src/alt_wait.c +Compiling alt_write.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_write.o HAL/src/alt_write.c +Compiling altera_nios2_qsys_irq.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/altera_nios2_qsys_irq.o HAL/src/altera_nios2_qsys_irq.c +Compiling crt0.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/crt0.o HAL/src/crt0.S +Compiling os_cpu_a.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/os_cpu_a.o HAL/src/os_cpu_a.S +Compiling os_cpu_c.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/os_cpu_c.o HAL/src/os_cpu_c.c +Compiling alt_env_lock.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/alt_env_lock.o UCOSII/src/alt_env_lock.c +Compiling alt_malloc_lock.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/alt_malloc_lock.o UCOSII/src/alt_malloc_lock.c +Compiling os_core.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_core.o UCOSII/src/os_core.c +Compiling os_dbg.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_dbg.o UCOSII/src/os_dbg.c +Compiling os_flag.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_flag.o UCOSII/src/os_flag.c +Compiling os_mbox.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_mbox.o UCOSII/src/os_mbox.c +Compiling os_mem.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_mem.o UCOSII/src/os_mem.c +Compiling os_mutex.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_mutex.o UCOSII/src/os_mutex.c +Compiling os_q.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_q.o UCOSII/src/os_q.c +Compiling os_sem.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_sem.o UCOSII/src/os_sem.c +Compiling os_task.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_task.o UCOSII/src/os_task.c +Compiling os_time.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_time.o UCOSII/src/os_time.c +Compiling os_tmr.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_tmr.o UCOSII/src/os_tmr.c +Compiling alt_sys_init.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/alt_sys_init.o alt_sys_init.c +Compiling altera_avalon_jtag_uart_fd.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_jtag_uart_fd.o drivers/src/altera_avalon_jtag_uart_fd.c +Compiling altera_avalon_jtag_uart_init.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_jtag_uart_init.o drivers/src/altera_avalon_jtag_uart_init.c +Compiling altera_avalon_jtag_uart_ioctl.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_jtag_uart_ioctl.o drivers/src/altera_avalon_jtag_uart_ioctl.c +Compiling altera_avalon_jtag_uart_read.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_jtag_uart_read.o drivers/src/altera_avalon_jtag_uart_read.c +Compiling altera_avalon_jtag_uart_write.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_jtag_uart_write.o drivers/src/altera_avalon_jtag_uart_write.c +Compiling altera_avalon_sysid_qsys.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_sysid_qsys.o drivers/src/altera_avalon_sysid_qsys.c +Compiling altera_avalon_timer_sc.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_timer_sc.o drivers/src/altera_avalon_timer_sc.c +Compiling altera_avalon_timer_ts.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_timer_ts.o drivers/src/altera_avalon_timer_ts.c +Compiling altera_avalon_timer_vars.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_timer_vars.o drivers/src/altera_avalon_timer_vars.c +Compiling altera_avalon_uart_fd.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_uart_fd.o drivers/src/altera_avalon_uart_fd.c +Compiling altera_avalon_uart_init.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_uart_init.o drivers/src/altera_avalon_uart_init.c +Compiling altera_avalon_uart_ioctl.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_uart_ioctl.o drivers/src/altera_avalon_uart_ioctl.c +Compiling altera_avalon_uart_read.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_uart_read.o drivers/src/altera_avalon_uart_read.c +Compiling altera_avalon_uart_write.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_uart_write.o drivers/src/altera_avalon_uart_write.c +drivers/src/altera_up_avalon_rs232.c: In function 'alt_up_rs232_read_fd': +Compiling altera_up_avalon_rs232.c... +drivers/src/altera_up_avalon_rs232.c:110: warning: pointer targets in passing argument 2 of 'alt_up_rs232_read_data' differ in signedness +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_up_avalon_rs232.o drivers/src/altera_up_avalon_rs232.c +Creating libucosii_bsp.a... +rm -f -f libucosii_bsp.a +nios2-elf-ar -src libucosii_bsp.a obj/HAL/src/alt_alarm_start.o obj/HAL/src/alt_busy_sleep.o obj/HAL/src/alt_close.o obj/HAL/src/alt_dcache_flush.o obj/HAL/src/alt_dcache_flush_all.o obj/HAL/src/alt_dcache_flush_no_writeback.o obj/HAL/src/alt_dev.o obj/HAL/src/alt_dev_llist_insert.o obj/HAL/src/alt_dma_rxchan_open.o obj/HAL/src/alt_dma_txchan_open.o obj/HAL/src/alt_do_ctors.o obj/HAL/src/alt_do_dtors.o obj/HAL/src/alt_environ.o obj/HAL/src/alt_errno.o obj/HAL/src/alt_exception_entry.o obj/HAL/src/alt_exception_muldiv.o obj/HAL/src/alt_exception_trap.o obj/HAL/src/alt_execve.o obj/HAL/src/alt_exit.o obj/HAL/src/alt_fcntl.o obj/HAL/src/alt_fd_lock.o obj/HAL/src/alt_fd_unlock.o obj/HAL/src/alt_find_dev.o obj/HAL/src/alt_find_file.o obj/HAL/src/alt_flash_dev.o obj/HAL/src/alt_fork.o obj/HAL/src/alt_fs_reg.o obj/HAL/src/alt_fstat.o obj/HAL/src/alt_get_fd.o obj/HAL/src/alt_getchar.o obj/HAL/src/alt_getpid.o obj/HAL/src/alt_gettod.o obj/HAL/src/alt_gmon.o obj/HAL/src/alt_icache_flush.o obj/HAL/src/alt_icache_flush_all.o obj/HAL/src/alt_iic.o obj/HAL/src/alt_iic_isr_register.o obj/HAL/src/alt_instruction_exception_entry.o obj/HAL/src/alt_instruction_exception_register.o obj/HAL/src/alt_io_redirect.o obj/HAL/src/alt_ioctl.o obj/HAL/src/alt_irq_entry.o obj/HAL/src/alt_irq_handler.o obj/HAL/src/alt_irq_register.o obj/HAL/src/alt_irq_vars.o obj/HAL/src/alt_isatty.o obj/HAL/src/alt_kill.o obj/HAL/src/alt_link.o obj/HAL/src/alt_load.o obj/HAL/src/alt_log_macro.o obj/HAL/src/alt_log_printf.o obj/HAL/src/alt_lseek.o obj/HAL/src/alt_main.o obj/HAL/src/alt_mcount.o obj/HAL/src/alt_open.o obj/HAL/src/alt_printf.o obj/HAL/src/alt_putchar.o obj/HAL/src/alt_putstr.o obj/HAL/src/alt_read.o obj/HAL/src/alt_release_fd.o obj/HAL/src/alt_remap_cached.o obj/HAL/src/alt_remap_uncached.o obj/HAL/src/alt_rename.o obj/HAL/src/alt_sbrk.o obj/HAL/src/alt_settod.o obj/HAL/src/alt_software_exception.o obj/HAL/src/alt_stat.o obj/HAL/src/alt_tick.o obj/HAL/src/alt_times.o obj/HAL/src/alt_uncached_free.o obj/HAL/src/alt_uncached_malloc.o obj/HAL/src/alt_unlink.o obj/HAL/src/alt_usleep.o obj/HAL/src/alt_wait.o obj/HAL/src/alt_write.o obj/HAL/src/altera_nios2_qsys_irq.o obj/HAL/src/crt0.o obj/HAL/src/os_cpu_a.o obj/HAL/src/os_cpu_c.o obj/UCOSII/src/alt_env_lock.o obj/UCOSII/src/alt_malloc_lock.o obj/UCOSII/src/os_core.o obj/UCOSII/src/os_dbg.o obj/UCOSII/src/os_flag.o obj/UCOSII/src/os_mbox.o obj/UCOSII/src/os_mem.o obj/UCOSII/src/os_mutex.o obj/UCOSII/src/os_q.o obj/UCOSII/src/os_sem.o obj/UCOSII/src/os_task.o obj/UCOSII/src/os_time.o obj/UCOSII/src/os_tmr.o obj/alt_sys_init.o obj/drivers/src/altera_avalon_jtag_uart_fd.o obj/drivers/src/altera_avalon_jtag_uart_init.o obj/drivers/src/altera_avalon_jtag_uart_ioctl.o obj/drivers/src/altera_avalon_jtag_uart_read.o obj/drivers/src/altera_avalon_jtag_uart_write.o obj/drivers/src/altera_avalon_sysid_qsys.o obj/drivers/src/altera_avalon_timer_sc.o obj/drivers/src/altera_avalon_timer_ts.o obj/drivers/src/altera_avalon_timer_vars.o obj/drivers/src/altera_avalon_uart_fd.o obj/drivers/src/altera_avalon_uart_init.o obj/drivers/src/altera_avalon_uart_ioctl.o obj/drivers/src/altera_avalon_uart_read.o obj/drivers/src/altera_avalon_uart_write.o obj/drivers/src/altera_up_avalon_rs232.o +[BSP build complete] +Info: Compiling MotorHandler.cpp to obj/default/MotorHandler.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/MotorHandler.o MotorHandler.cpp +Info: Compiling main.cpp to obj/default/main.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/main.o main.cpp +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010a0 --timestamp 1394124174 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD" --jdi C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.jdi --sopcinfo C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo +Info: (MCTest.elf) 140 KBytes program size (code + initialized data). +Info: 16236 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Clean-only build of configuration Nios II for project MCTest **** + +make clean +[MCTest clean complete] + +**** Build Finished **** + +**** Clean-only build of configuration Nios II for project MCTest_bsp **** + +make clean +[BSP clean complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +Compiling alt_alarm_start.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_alarm_start.o HAL/src/alt_alarm_start.c +Compiling alt_busy_sleep.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_busy_sleep.o HAL/src/alt_busy_sleep.c +Compiling alt_close.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_close.o HAL/src/alt_close.c +Compiling alt_dcache_flush.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dcache_flush.o HAL/src/alt_dcache_flush.c +Compiling alt_dcache_flush_all.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dcache_flush_all.o HAL/src/alt_dcache_flush_all.c +Compiling alt_dcache_flush_no_writeback.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dcache_flush_no_writeback.o HAL/src/alt_dcache_flush_no_writeback.c +Compiling alt_dev.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dev.o HAL/src/alt_dev.c +Compiling alt_dev_llist_insert.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dev_llist_insert.o HAL/src/alt_dev_llist_insert.c +Compiling alt_dma_rxchan_open.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dma_rxchan_open.o HAL/src/alt_dma_rxchan_open.c +Compiling alt_dma_txchan_open.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dma_txchan_open.o HAL/src/alt_dma_txchan_open.c +Compiling alt_do_ctors.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_do_ctors.o HAL/src/alt_do_ctors.c +Compiling alt_do_dtors.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_do_dtors.o HAL/src/alt_do_dtors.c +Compiling alt_environ.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_environ.o HAL/src/alt_environ.c +Compiling alt_errno.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_errno.o HAL/src/alt_errno.c +Compiling alt_exception_entry.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_exception_entry.o HAL/src/alt_exception_entry.S +Compiling alt_exception_muldiv.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_exception_muldiv.o HAL/src/alt_exception_muldiv.S +Compiling alt_exception_trap.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_exception_trap.o HAL/src/alt_exception_trap.S +Compiling alt_execve.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_execve.o HAL/src/alt_execve.c +Compiling alt_exit.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_exit.o HAL/src/alt_exit.c +Compiling alt_fcntl.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fcntl.o HAL/src/alt_fcntl.c +Compiling alt_fd_lock.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fd_lock.o HAL/src/alt_fd_lock.c +Compiling alt_fd_unlock.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fd_unlock.o HAL/src/alt_fd_unlock.c +Compiling alt_find_dev.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_find_dev.o HAL/src/alt_find_dev.c +Compiling alt_find_file.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_find_file.o HAL/src/alt_find_file.c +Compiling alt_flash_dev.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_flash_dev.o HAL/src/alt_flash_dev.c +Compiling alt_fork.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fork.o HAL/src/alt_fork.c +Compiling alt_fs_reg.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fs_reg.o HAL/src/alt_fs_reg.c +Compiling alt_fstat.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fstat.o HAL/src/alt_fstat.c +Compiling alt_get_fd.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_get_fd.o HAL/src/alt_get_fd.c +Compiling alt_getchar.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_getchar.o HAL/src/alt_getchar.c +Compiling alt_getpid.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_getpid.o HAL/src/alt_getpid.c +Compiling alt_gettod.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_gettod.o HAL/src/alt_gettod.c +Compiling alt_gmon.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_gmon.o HAL/src/alt_gmon.c +Compiling alt_icache_flush.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_icache_flush.o HAL/src/alt_icache_flush.c +Compiling alt_icache_flush_all.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_icache_flush_all.o HAL/src/alt_icache_flush_all.c +Compiling alt_iic.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_iic.o HAL/src/alt_iic.c +Compiling alt_iic_isr_register.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_iic_isr_register.o HAL/src/alt_iic_isr_register.c +Compiling alt_instruction_exception_entry.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_instruction_exception_entry.o HAL/src/alt_instruction_exception_entry.c +Compiling alt_instruction_exception_register.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_instruction_exception_register.o HAL/src/alt_instruction_exception_register.c +Compiling alt_io_redirect.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_io_redirect.o HAL/src/alt_io_redirect.c +Compiling alt_ioctl.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_ioctl.o HAL/src/alt_ioctl.c +Compiling alt_irq_entry.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_irq_entry.o HAL/src/alt_irq_entry.S +Compiling alt_irq_handler.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_irq_handler.o HAL/src/alt_irq_handler.c +Compiling alt_irq_register.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_irq_register.o HAL/src/alt_irq_register.c +Compiling alt_irq_vars.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_irq_vars.o HAL/src/alt_irq_vars.c +Compiling alt_isatty.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_isatty.o HAL/src/alt_isatty.c +Compiling alt_kill.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_kill.o HAL/src/alt_kill.c +Compiling alt_link.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_link.o HAL/src/alt_link.c +Compiling alt_load.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_load.o HAL/src/alt_load.c +Compiling alt_log_macro.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_log_macro.o HAL/src/alt_log_macro.S +Compiling alt_log_printf.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_log_printf.o HAL/src/alt_log_printf.c +Compiling alt_lseek.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_lseek.o HAL/src/alt_lseek.c +Compiling alt_main.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_main.o HAL/src/alt_main.c +Compiling alt_mcount.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_mcount.o HAL/src/alt_mcount.S +Compiling alt_open.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_open.o HAL/src/alt_open.c +Compiling alt_printf.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_printf.o HAL/src/alt_printf.c +Compiling alt_putchar.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_putchar.o HAL/src/alt_putchar.c +Compiling alt_putstr.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_putstr.o HAL/src/alt_putstr.c +Compiling alt_read.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_read.o HAL/src/alt_read.c +Compiling alt_release_fd.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_release_fd.o HAL/src/alt_release_fd.c +Compiling alt_remap_cached.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_remap_cached.o HAL/src/alt_remap_cached.c +Compiling alt_remap_uncached.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_remap_uncached.o HAL/src/alt_remap_uncached.c +Compiling alt_rename.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_rename.o HAL/src/alt_rename.c +Compiling alt_sbrk.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_sbrk.o HAL/src/alt_sbrk.c +Compiling alt_settod.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_settod.o HAL/src/alt_settod.c +Compiling alt_software_exception.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_software_exception.o HAL/src/alt_software_exception.S +Compiling alt_stat.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_stat.o HAL/src/alt_stat.c +Compiling alt_tick.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_tick.o HAL/src/alt_tick.c +Compiling alt_times.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_times.o HAL/src/alt_times.c +Compiling alt_uncached_free.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_uncached_free.o HAL/src/alt_uncached_free.c +Compiling alt_uncached_malloc.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_uncached_malloc.o HAL/src/alt_uncached_malloc.c +Compiling alt_unlink.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_unlink.o HAL/src/alt_unlink.c +Compiling alt_usleep.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_usleep.o HAL/src/alt_usleep.c +Compiling alt_wait.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_wait.o HAL/src/alt_wait.c +Compiling alt_write.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_write.o HAL/src/alt_write.c +Compiling altera_nios2_qsys_irq.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/altera_nios2_qsys_irq.o HAL/src/altera_nios2_qsys_irq.c +Compiling crt0.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/crt0.o HAL/src/crt0.S +Compiling os_cpu_a.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/os_cpu_a.o HAL/src/os_cpu_a.S +Compiling os_cpu_c.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/os_cpu_c.o HAL/src/os_cpu_c.c +Compiling alt_env_lock.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/alt_env_lock.o UCOSII/src/alt_env_lock.c +Compiling alt_malloc_lock.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/alt_malloc_lock.o UCOSII/src/alt_malloc_lock.c +Compiling os_core.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_core.o UCOSII/src/os_core.c +Compiling os_dbg.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_dbg.o UCOSII/src/os_dbg.c +Compiling os_flag.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_flag.o UCOSII/src/os_flag.c +Compiling os_mbox.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_mbox.o UCOSII/src/os_mbox.c +Compiling os_mem.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_mem.o UCOSII/src/os_mem.c +Compiling os_mutex.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_mutex.o UCOSII/src/os_mutex.c +Compiling os_q.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_q.o UCOSII/src/os_q.c +Compiling os_sem.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_sem.o UCOSII/src/os_sem.c +Compiling os_task.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_task.o UCOSII/src/os_task.c +Compiling os_time.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_time.o UCOSII/src/os_time.c +Compiling os_tmr.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_tmr.o UCOSII/src/os_tmr.c +Compiling alt_sys_init.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/alt_sys_init.o alt_sys_init.c +Compiling altera_avalon_jtag_uart_fd.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_jtag_uart_fd.o drivers/src/altera_avalon_jtag_uart_fd.c +Compiling altera_avalon_jtag_uart_init.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_jtag_uart_init.o drivers/src/altera_avalon_jtag_uart_init.c +Compiling altera_avalon_jtag_uart_ioctl.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_jtag_uart_ioctl.o drivers/src/altera_avalon_jtag_uart_ioctl.c +Compiling altera_avalon_jtag_uart_read.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_jtag_uart_read.o drivers/src/altera_avalon_jtag_uart_read.c +Compiling altera_avalon_jtag_uart_write.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_jtag_uart_write.o drivers/src/altera_avalon_jtag_uart_write.c +Compiling altera_avalon_sysid_qsys.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_sysid_qsys.o drivers/src/altera_avalon_sysid_qsys.c +Compiling altera_avalon_timer_sc.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_timer_sc.o drivers/src/altera_avalon_timer_sc.c +Compiling altera_avalon_timer_ts.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_timer_ts.o drivers/src/altera_avalon_timer_ts.c +Compiling altera_avalon_timer_vars.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_timer_vars.o drivers/src/altera_avalon_timer_vars.c +Compiling altera_avalon_uart_fd.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_uart_fd.o drivers/src/altera_avalon_uart_fd.c +Compiling altera_avalon_uart_init.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_uart_init.o drivers/src/altera_avalon_uart_init.c +Compiling altera_avalon_uart_ioctl.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_uart_ioctl.o drivers/src/altera_avalon_uart_ioctl.c +Compiling altera_avalon_uart_read.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_uart_read.o drivers/src/altera_avalon_uart_read.c +Compiling altera_avalon_uart_write.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_uart_write.o drivers/src/altera_avalon_uart_write.c +drivers/src/altera_up_avalon_rs232.c: In function 'alt_up_rs232_read_fd': +Compiling altera_up_avalon_rs232.c... +drivers/src/altera_up_avalon_rs232.c:110: warning: pointer targets in passing argument 2 of 'alt_up_rs232_read_data' differ in signedness +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_up_avalon_rs232.o drivers/src/altera_up_avalon_rs232.c +Creating libucosii_bsp.a... +rm -f -f libucosii_bsp.a +nios2-elf-ar -src libucosii_bsp.a obj/HAL/src/alt_alarm_start.o obj/HAL/src/alt_busy_sleep.o obj/HAL/src/alt_close.o obj/HAL/src/alt_dcache_flush.o obj/HAL/src/alt_dcache_flush_all.o obj/HAL/src/alt_dcache_flush_no_writeback.o obj/HAL/src/alt_dev.o obj/HAL/src/alt_dev_llist_insert.o obj/HAL/src/alt_dma_rxchan_open.o obj/HAL/src/alt_dma_txchan_open.o obj/HAL/src/alt_do_ctors.o obj/HAL/src/alt_do_dtors.o obj/HAL/src/alt_environ.o obj/HAL/src/alt_errno.o obj/HAL/src/alt_exception_entry.o obj/HAL/src/alt_exception_muldiv.o obj/HAL/src/alt_exception_trap.o obj/HAL/src/alt_execve.o obj/HAL/src/alt_exit.o obj/HAL/src/alt_fcntl.o obj/HAL/src/alt_fd_lock.o obj/HAL/src/alt_fd_unlock.o obj/HAL/src/alt_find_dev.o obj/HAL/src/alt_find_file.o obj/HAL/src/alt_flash_dev.o obj/HAL/src/alt_fork.o obj/HAL/src/alt_fs_reg.o obj/HAL/src/alt_fstat.o obj/HAL/src/alt_get_fd.o obj/HAL/src/alt_getchar.o obj/HAL/src/alt_getpid.o obj/HAL/src/alt_gettod.o obj/HAL/src/alt_gmon.o obj/HAL/src/alt_icache_flush.o obj/HAL/src/alt_icache_flush_all.o obj/HAL/src/alt_iic.o obj/HAL/src/alt_iic_isr_register.o obj/HAL/src/alt_instruction_exception_entry.o obj/HAL/src/alt_instruction_exception_register.o obj/HAL/src/alt_io_redirect.o obj/HAL/src/alt_ioctl.o obj/HAL/src/alt_irq_entry.o obj/HAL/src/alt_irq_handler.o obj/HAL/src/alt_irq_register.o obj/HAL/src/alt_irq_vars.o obj/HAL/src/alt_isatty.o obj/HAL/src/alt_kill.o obj/HAL/src/alt_link.o obj/HAL/src/alt_load.o obj/HAL/src/alt_log_macro.o obj/HAL/src/alt_log_printf.o obj/HAL/src/alt_lseek.o obj/HAL/src/alt_main.o obj/HAL/src/alt_mcount.o obj/HAL/src/alt_open.o obj/HAL/src/alt_printf.o obj/HAL/src/alt_putchar.o obj/HAL/src/alt_putstr.o obj/HAL/src/alt_read.o obj/HAL/src/alt_release_fd.o obj/HAL/src/alt_remap_cached.o obj/HAL/src/alt_remap_uncached.o obj/HAL/src/alt_rename.o obj/HAL/src/alt_sbrk.o obj/HAL/src/alt_settod.o obj/HAL/src/alt_software_exception.o obj/HAL/src/alt_stat.o obj/HAL/src/alt_tick.o obj/HAL/src/alt_times.o obj/HAL/src/alt_uncached_free.o obj/HAL/src/alt_uncached_malloc.o obj/HAL/src/alt_unlink.o obj/HAL/src/alt_usleep.o obj/HAL/src/alt_wait.o obj/HAL/src/alt_write.o obj/HAL/src/altera_nios2_qsys_irq.o obj/HAL/src/crt0.o obj/HAL/src/os_cpu_a.o obj/HAL/src/os_cpu_c.o obj/UCOSII/src/alt_env_lock.o obj/UCOSII/src/alt_malloc_lock.o obj/UCOSII/src/os_core.o obj/UCOSII/src/os_dbg.o obj/UCOSII/src/os_flag.o obj/UCOSII/src/os_mbox.o obj/UCOSII/src/os_mem.o obj/UCOSII/src/os_mutex.o obj/UCOSII/src/os_q.o obj/UCOSII/src/os_sem.o obj/UCOSII/src/os_task.o obj/UCOSII/src/os_time.o obj/UCOSII/src/os_tmr.o obj/alt_sys_init.o obj/drivers/src/altera_avalon_jtag_uart_fd.o obj/drivers/src/altera_avalon_jtag_uart_init.o obj/drivers/src/altera_avalon_jtag_uart_ioctl.o obj/drivers/src/altera_avalon_jtag_uart_read.o obj/drivers/src/altera_avalon_jtag_uart_write.o obj/drivers/src/altera_avalon_sysid_qsys.o obj/drivers/src/altera_avalon_timer_sc.o obj/drivers/src/altera_avalon_timer_ts.o obj/drivers/src/altera_avalon_timer_vars.o obj/drivers/src/altera_avalon_uart_fd.o obj/drivers/src/altera_avalon_uart_init.o obj/drivers/src/altera_avalon_uart_ioctl.o obj/drivers/src/altera_avalon_uart_read.o obj/drivers/src/altera_avalon_uart_write.o obj/drivers/src/altera_up_avalon_rs232.o +[BSP build complete] +Info: Compiling MotorHandler.cpp to obj/default/MotorHandler.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/MotorHandler.o MotorHandler.cpp +Info: Compiling main.cpp to obj/default/main.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/main.o main.cpp +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010a0 --timestamp 1394124174 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD" --jdi C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.jdi --sopcinfo C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo +Info: (MCTest.elf) 140 KBytes program size (code + initialized data). +Info: 16236 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Clean-only build of configuration Nios II for project MCTest **** + +make clean +[MCTest clean complete] + +**** Build Finished **** + +**** Clean-only build of configuration Nios II for project MCTest_bsp **** + +make clean +[BSP clean complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +Compiling alt_alarm_start.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_alarm_start.o HAL/src/alt_alarm_start.c +Compiling alt_busy_sleep.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_busy_sleep.o HAL/src/alt_busy_sleep.c +Compiling alt_close.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_close.o HAL/src/alt_close.c +Compiling alt_dcache_flush.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dcache_flush.o HAL/src/alt_dcache_flush.c +Compiling alt_dcache_flush_all.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dcache_flush_all.o HAL/src/alt_dcache_flush_all.c +Compiling alt_dcache_flush_no_writeback.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dcache_flush_no_writeback.o HAL/src/alt_dcache_flush_no_writeback.c +Compiling alt_dev.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dev.o HAL/src/alt_dev.c +Compiling alt_dev_llist_insert.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dev_llist_insert.o HAL/src/alt_dev_llist_insert.c +Compiling alt_dma_rxchan_open.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dma_rxchan_open.o HAL/src/alt_dma_rxchan_open.c +Compiling alt_dma_txchan_open.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dma_txchan_open.o HAL/src/alt_dma_txchan_open.c +Compiling alt_do_ctors.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_do_ctors.o HAL/src/alt_do_ctors.c +Compiling alt_do_dtors.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_do_dtors.o HAL/src/alt_do_dtors.c +Compiling alt_environ.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_environ.o HAL/src/alt_environ.c +Compiling alt_errno.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_errno.o HAL/src/alt_errno.c +Compiling alt_exception_entry.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_exception_entry.o HAL/src/alt_exception_entry.S +Compiling alt_exception_muldiv.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_exception_muldiv.o HAL/src/alt_exception_muldiv.S +Compiling alt_exception_trap.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_exception_trap.o HAL/src/alt_exception_trap.S +Compiling alt_execve.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_execve.o HAL/src/alt_execve.c +Compiling alt_exit.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_exit.o HAL/src/alt_exit.c +Compiling alt_fcntl.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fcntl.o HAL/src/alt_fcntl.c +Compiling alt_fd_lock.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fd_lock.o HAL/src/alt_fd_lock.c +Compiling alt_fd_unlock.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fd_unlock.o HAL/src/alt_fd_unlock.c +Compiling alt_find_dev.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_find_dev.o HAL/src/alt_find_dev.c +Compiling alt_find_file.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_find_file.o HAL/src/alt_find_file.c +Compiling alt_flash_dev.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_flash_dev.o HAL/src/alt_flash_dev.c +Compiling alt_fork.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fork.o HAL/src/alt_fork.c +Compiling alt_fs_reg.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fs_reg.o HAL/src/alt_fs_reg.c +Compiling alt_fstat.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fstat.o HAL/src/alt_fstat.c +Compiling alt_get_fd.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_get_fd.o HAL/src/alt_get_fd.c +Compiling alt_getchar.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_getchar.o HAL/src/alt_getchar.c +Compiling alt_getpid.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_getpid.o HAL/src/alt_getpid.c +Compiling alt_gettod.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_gettod.o HAL/src/alt_gettod.c +Compiling alt_gmon.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_gmon.o HAL/src/alt_gmon.c +Compiling alt_icache_flush.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_icache_flush.o HAL/src/alt_icache_flush.c +Compiling alt_icache_flush_all.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_icache_flush_all.o HAL/src/alt_icache_flush_all.c +Compiling alt_iic.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_iic.o HAL/src/alt_iic.c +Compiling alt_iic_isr_register.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_iic_isr_register.o HAL/src/alt_iic_isr_register.c +Compiling alt_instruction_exception_entry.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_instruction_exception_entry.o HAL/src/alt_instruction_exception_entry.c +Compiling alt_instruction_exception_register.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_instruction_exception_register.o HAL/src/alt_instruction_exception_register.c +Compiling alt_io_redirect.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_io_redirect.o HAL/src/alt_io_redirect.c +Compiling alt_ioctl.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_ioctl.o HAL/src/alt_ioctl.c +Compiling alt_irq_entry.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_irq_entry.o HAL/src/alt_irq_entry.S +Compiling alt_irq_handler.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_irq_handler.o HAL/src/alt_irq_handler.c +Compiling alt_irq_register.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_irq_register.o HAL/src/alt_irq_register.c +Compiling alt_irq_vars.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_irq_vars.o HAL/src/alt_irq_vars.c +Compiling alt_isatty.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_isatty.o HAL/src/alt_isatty.c +Compiling alt_kill.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_kill.o HAL/src/alt_kill.c +Compiling alt_link.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_link.o HAL/src/alt_link.c +Compiling alt_load.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_load.o HAL/src/alt_load.c +Compiling alt_log_macro.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_log_macro.o HAL/src/alt_log_macro.S +Compiling alt_log_printf.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_log_printf.o HAL/src/alt_log_printf.c +Compiling alt_lseek.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_lseek.o HAL/src/alt_lseek.c +Compiling alt_main.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_main.o HAL/src/alt_main.c +Compiling alt_mcount.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_mcount.o HAL/src/alt_mcount.S +Compiling alt_open.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_open.o HAL/src/alt_open.c +Compiling alt_printf.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_printf.o HAL/src/alt_printf.c +Compiling alt_putchar.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_putchar.o HAL/src/alt_putchar.c +Compiling alt_putstr.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_putstr.o HAL/src/alt_putstr.c +Compiling alt_read.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_read.o HAL/src/alt_read.c +Compiling alt_release_fd.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_release_fd.o HAL/src/alt_release_fd.c +Compiling alt_remap_cached.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_remap_cached.o HAL/src/alt_remap_cached.c +Compiling alt_remap_uncached.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_remap_uncached.o HAL/src/alt_remap_uncached.c +Compiling alt_rename.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_rename.o HAL/src/alt_rename.c +Compiling alt_sbrk.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_sbrk.o HAL/src/alt_sbrk.c +Compiling alt_settod.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_settod.o HAL/src/alt_settod.c +Compiling alt_software_exception.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_software_exception.o HAL/src/alt_software_exception.S +Compiling alt_stat.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_stat.o HAL/src/alt_stat.c +Compiling alt_tick.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_tick.o HAL/src/alt_tick.c +Compiling alt_times.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_times.o HAL/src/alt_times.c +Compiling alt_uncached_free.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_uncached_free.o HAL/src/alt_uncached_free.c +Compiling alt_uncached_malloc.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_uncached_malloc.o HAL/src/alt_uncached_malloc.c +Compiling alt_unlink.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_unlink.o HAL/src/alt_unlink.c +Compiling alt_usleep.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_usleep.o HAL/src/alt_usleep.c +Compiling alt_wait.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_wait.o HAL/src/alt_wait.c +Compiling alt_write.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_write.o HAL/src/alt_write.c +Compiling altera_nios2_qsys_irq.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/altera_nios2_qsys_irq.o HAL/src/altera_nios2_qsys_irq.c +Compiling crt0.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/crt0.o HAL/src/crt0.S +Compiling os_cpu_a.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/os_cpu_a.o HAL/src/os_cpu_a.S +Compiling os_cpu_c.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/os_cpu_c.o HAL/src/os_cpu_c.c +Compiling alt_env_lock.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/alt_env_lock.o UCOSII/src/alt_env_lock.c +Compiling alt_malloc_lock.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/alt_malloc_lock.o UCOSII/src/alt_malloc_lock.c +Compiling os_core.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_core.o UCOSII/src/os_core.c +Compiling os_dbg.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_dbg.o UCOSII/src/os_dbg.c +Compiling os_flag.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_flag.o UCOSII/src/os_flag.c +Compiling os_mbox.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_mbox.o UCOSII/src/os_mbox.c +Compiling os_mem.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_mem.o UCOSII/src/os_mem.c +Compiling os_mutex.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_mutex.o UCOSII/src/os_mutex.c +Compiling os_q.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_q.o UCOSII/src/os_q.c +Compiling os_sem.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_sem.o UCOSII/src/os_sem.c +Compiling os_task.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_task.o UCOSII/src/os_task.c +Compiling os_time.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_time.o UCOSII/src/os_time.c +Compiling os_tmr.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_tmr.o UCOSII/src/os_tmr.c +Compiling alt_sys_init.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/alt_sys_init.o alt_sys_init.c +Compiling altera_avalon_jtag_uart_fd.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_jtag_uart_fd.o drivers/src/altera_avalon_jtag_uart_fd.c +Compiling altera_avalon_jtag_uart_init.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_jtag_uart_init.o drivers/src/altera_avalon_jtag_uart_init.c +Compiling altera_avalon_jtag_uart_ioctl.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_jtag_uart_ioctl.o drivers/src/altera_avalon_jtag_uart_ioctl.c +Compiling altera_avalon_jtag_uart_read.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_jtag_uart_read.o drivers/src/altera_avalon_jtag_uart_read.c +Compiling altera_avalon_jtag_uart_write.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_jtag_uart_write.o drivers/src/altera_avalon_jtag_uart_write.c +Compiling altera_avalon_sysid_qsys.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_sysid_qsys.o drivers/src/altera_avalon_sysid_qsys.c +Compiling altera_avalon_timer_sc.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_timer_sc.o drivers/src/altera_avalon_timer_sc.c +Compiling altera_avalon_timer_ts.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_timer_ts.o drivers/src/altera_avalon_timer_ts.c +Compiling altera_avalon_timer_vars.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_timer_vars.o drivers/src/altera_avalon_timer_vars.c +Compiling altera_avalon_uart_fd.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_uart_fd.o drivers/src/altera_avalon_uart_fd.c +Compiling altera_avalon_uart_init.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_uart_init.o drivers/src/altera_avalon_uart_init.c +Compiling altera_avalon_uart_ioctl.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_uart_ioctl.o drivers/src/altera_avalon_uart_ioctl.c +Compiling altera_avalon_uart_read.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_uart_read.o drivers/src/altera_avalon_uart_read.c +Compiling altera_avalon_uart_write.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_uart_write.o drivers/src/altera_avalon_uart_write.c +drivers/src/altera_up_avalon_rs232.c: In function 'alt_up_rs232_read_fd': +Compiling altera_up_avalon_rs232.c... +drivers/src/altera_up_avalon_rs232.c:110: warning: pointer targets in passing argument 2 of 'alt_up_rs232_read_data' differ in signedness +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_up_avalon_rs232.o drivers/src/altera_up_avalon_rs232.c +Creating libucosii_bsp.a... +rm -f -f libucosii_bsp.a +nios2-elf-ar -src libucosii_bsp.a obj/HAL/src/alt_alarm_start.o obj/HAL/src/alt_busy_sleep.o obj/HAL/src/alt_close.o obj/HAL/src/alt_dcache_flush.o obj/HAL/src/alt_dcache_flush_all.o obj/HAL/src/alt_dcache_flush_no_writeback.o obj/HAL/src/alt_dev.o obj/HAL/src/alt_dev_llist_insert.o obj/HAL/src/alt_dma_rxchan_open.o obj/HAL/src/alt_dma_txchan_open.o obj/HAL/src/alt_do_ctors.o obj/HAL/src/alt_do_dtors.o obj/HAL/src/alt_environ.o obj/HAL/src/alt_errno.o obj/HAL/src/alt_exception_entry.o obj/HAL/src/alt_exception_muldiv.o obj/HAL/src/alt_exception_trap.o obj/HAL/src/alt_execve.o obj/HAL/src/alt_exit.o obj/HAL/src/alt_fcntl.o obj/HAL/src/alt_fd_lock.o obj/HAL/src/alt_fd_unlock.o obj/HAL/src/alt_find_dev.o obj/HAL/src/alt_find_file.o obj/HAL/src/alt_flash_dev.o obj/HAL/src/alt_fork.o obj/HAL/src/alt_fs_reg.o obj/HAL/src/alt_fstat.o obj/HAL/src/alt_get_fd.o obj/HAL/src/alt_getchar.o obj/HAL/src/alt_getpid.o obj/HAL/src/alt_gettod.o obj/HAL/src/alt_gmon.o obj/HAL/src/alt_icache_flush.o obj/HAL/src/alt_icache_flush_all.o obj/HAL/src/alt_iic.o obj/HAL/src/alt_iic_isr_register.o obj/HAL/src/alt_instruction_exception_entry.o obj/HAL/src/alt_instruction_exception_register.o obj/HAL/src/alt_io_redirect.o obj/HAL/src/alt_ioctl.o obj/HAL/src/alt_irq_entry.o obj/HAL/src/alt_irq_handler.o obj/HAL/src/alt_irq_register.o obj/HAL/src/alt_irq_vars.o obj/HAL/src/alt_isatty.o obj/HAL/src/alt_kill.o obj/HAL/src/alt_link.o obj/HAL/src/alt_load.o obj/HAL/src/alt_log_macro.o obj/HAL/src/alt_log_printf.o obj/HAL/src/alt_lseek.o obj/HAL/src/alt_main.o obj/HAL/src/alt_mcount.o obj/HAL/src/alt_open.o obj/HAL/src/alt_printf.o obj/HAL/src/alt_putchar.o obj/HAL/src/alt_putstr.o obj/HAL/src/alt_read.o obj/HAL/src/alt_release_fd.o obj/HAL/src/alt_remap_cached.o obj/HAL/src/alt_remap_uncached.o obj/HAL/src/alt_rename.o obj/HAL/src/alt_sbrk.o obj/HAL/src/alt_settod.o obj/HAL/src/alt_software_exception.o obj/HAL/src/alt_stat.o obj/HAL/src/alt_tick.o obj/HAL/src/alt_times.o obj/HAL/src/alt_uncached_free.o obj/HAL/src/alt_uncached_malloc.o obj/HAL/src/alt_unlink.o obj/HAL/src/alt_usleep.o obj/HAL/src/alt_wait.o obj/HAL/src/alt_write.o obj/HAL/src/altera_nios2_qsys_irq.o obj/HAL/src/crt0.o obj/HAL/src/os_cpu_a.o obj/HAL/src/os_cpu_c.o obj/UCOSII/src/alt_env_lock.o obj/UCOSII/src/alt_malloc_lock.o obj/UCOSII/src/os_core.o obj/UCOSII/src/os_dbg.o obj/UCOSII/src/os_flag.o obj/UCOSII/src/os_mbox.o obj/UCOSII/src/os_mem.o obj/UCOSII/src/os_mutex.o obj/UCOSII/src/os_q.o obj/UCOSII/src/os_sem.o obj/UCOSII/src/os_task.o obj/UCOSII/src/os_time.o obj/UCOSII/src/os_tmr.o obj/alt_sys_init.o obj/drivers/src/altera_avalon_jtag_uart_fd.o obj/drivers/src/altera_avalon_jtag_uart_init.o obj/drivers/src/altera_avalon_jtag_uart_ioctl.o obj/drivers/src/altera_avalon_jtag_uart_read.o obj/drivers/src/altera_avalon_jtag_uart_write.o obj/drivers/src/altera_avalon_sysid_qsys.o obj/drivers/src/altera_avalon_timer_sc.o obj/drivers/src/altera_avalon_timer_ts.o obj/drivers/src/altera_avalon_timer_vars.o obj/drivers/src/altera_avalon_uart_fd.o obj/drivers/src/altera_avalon_uart_init.o obj/drivers/src/altera_avalon_uart_ioctl.o obj/drivers/src/altera_avalon_uart_read.o obj/drivers/src/altera_avalon_uart_write.o obj/drivers/src/altera_up_avalon_rs232.o +[BSP build complete] +Info: Compiling MotorHandler.cpp to obj/default/MotorHandler.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/MotorHandler.o MotorHandler.cpp +Info: Compiling main.cpp to obj/default/main.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/main.o main.cpp +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010a0 --timestamp 1394124174 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD" --jdi C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.jdi --sopcinfo C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo +Info: (MCTest.elf) 140 KBytes program size (code + initialized data). +Info: 16236 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Clean-only build of configuration Nios II for project MCTest **** + +make clean +[MCTest clean complete] + +**** Build Finished **** + +**** Clean-only build of configuration Nios II for project MCTest_bsp **** + +make clean +[BSP clean complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +Compiling alt_alarm_start.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_alarm_start.o HAL/src/alt_alarm_start.c +Compiling alt_busy_sleep.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_busy_sleep.o HAL/src/alt_busy_sleep.c +Compiling alt_close.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_close.o HAL/src/alt_close.c +Compiling alt_dcache_flush.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dcache_flush.o HAL/src/alt_dcache_flush.c +Compiling alt_dcache_flush_all.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dcache_flush_all.o HAL/src/alt_dcache_flush_all.c +Compiling alt_dcache_flush_no_writeback.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dcache_flush_no_writeback.o HAL/src/alt_dcache_flush_no_writeback.c +Compiling alt_dev.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dev.o HAL/src/alt_dev.c +Compiling alt_dev_llist_insert.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dev_llist_insert.o HAL/src/alt_dev_llist_insert.c +Compiling alt_dma_rxchan_open.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dma_rxchan_open.o HAL/src/alt_dma_rxchan_open.c +Compiling alt_dma_txchan_open.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dma_txchan_open.o HAL/src/alt_dma_txchan_open.c +Compiling alt_do_ctors.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_do_ctors.o HAL/src/alt_do_ctors.c +Compiling alt_do_dtors.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_do_dtors.o HAL/src/alt_do_dtors.c +Compiling alt_environ.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_environ.o HAL/src/alt_environ.c +Compiling alt_errno.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_errno.o HAL/src/alt_errno.c +Compiling alt_exception_entry.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_exception_entry.o HAL/src/alt_exception_entry.S +Compiling alt_exception_muldiv.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_exception_muldiv.o HAL/src/alt_exception_muldiv.S +Compiling alt_exception_trap.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_exception_trap.o HAL/src/alt_exception_trap.S +Compiling alt_execve.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_execve.o HAL/src/alt_execve.c +Compiling alt_exit.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_exit.o HAL/src/alt_exit.c +Compiling alt_fcntl.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fcntl.o HAL/src/alt_fcntl.c +Compiling alt_fd_lock.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fd_lock.o HAL/src/alt_fd_lock.c +Compiling alt_fd_unlock.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fd_unlock.o HAL/src/alt_fd_unlock.c +Compiling alt_find_dev.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_find_dev.o HAL/src/alt_find_dev.c +Compiling alt_find_file.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_find_file.o HAL/src/alt_find_file.c +Compiling alt_flash_dev.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_flash_dev.o HAL/src/alt_flash_dev.c +Compiling alt_fork.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fork.o HAL/src/alt_fork.c +Compiling alt_fs_reg.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fs_reg.o HAL/src/alt_fs_reg.c +Compiling alt_fstat.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fstat.o HAL/src/alt_fstat.c +Compiling alt_get_fd.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_get_fd.o HAL/src/alt_get_fd.c +Compiling alt_getchar.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_getchar.o HAL/src/alt_getchar.c +Compiling alt_getpid.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_getpid.o HAL/src/alt_getpid.c +Compiling alt_gettod.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_gettod.o HAL/src/alt_gettod.c +Compiling alt_gmon.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_gmon.o HAL/src/alt_gmon.c +Compiling alt_icache_flush.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_icache_flush.o HAL/src/alt_icache_flush.c +Compiling alt_icache_flush_all.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_icache_flush_all.o HAL/src/alt_icache_flush_all.c +Compiling alt_iic.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_iic.o HAL/src/alt_iic.c +Compiling alt_iic_isr_register.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_iic_isr_register.o HAL/src/alt_iic_isr_register.c +Compiling alt_instruction_exception_entry.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_instruction_exception_entry.o HAL/src/alt_instruction_exception_entry.c +Compiling alt_instruction_exception_register.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_instruction_exception_register.o HAL/src/alt_instruction_exception_register.c +Compiling alt_io_redirect.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_io_redirect.o HAL/src/alt_io_redirect.c +Compiling alt_ioctl.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_ioctl.o HAL/src/alt_ioctl.c +Compiling alt_irq_entry.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_irq_entry.o HAL/src/alt_irq_entry.S +Compiling alt_irq_handler.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_irq_handler.o HAL/src/alt_irq_handler.c +Compiling alt_irq_register.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_irq_register.o HAL/src/alt_irq_register.c +Compiling alt_irq_vars.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_irq_vars.o HAL/src/alt_irq_vars.c +Compiling alt_isatty.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_isatty.o HAL/src/alt_isatty.c +Compiling alt_kill.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_kill.o HAL/src/alt_kill.c +Compiling alt_link.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_link.o HAL/src/alt_link.c +Compiling alt_load.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_load.o HAL/src/alt_load.c +Compiling alt_log_macro.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_log_macro.o HAL/src/alt_log_macro.S +Compiling alt_log_printf.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_log_printf.o HAL/src/alt_log_printf.c +Compiling alt_lseek.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_lseek.o HAL/src/alt_lseek.c +Compiling alt_main.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_main.o HAL/src/alt_main.c +Compiling alt_mcount.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_mcount.o HAL/src/alt_mcount.S +Compiling alt_open.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_open.o HAL/src/alt_open.c +Compiling alt_printf.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_printf.o HAL/src/alt_printf.c +Compiling alt_putchar.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_putchar.o HAL/src/alt_putchar.c +Compiling alt_putstr.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_putstr.o HAL/src/alt_putstr.c +Compiling alt_read.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_read.o HAL/src/alt_read.c +Compiling alt_release_fd.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_release_fd.o HAL/src/alt_release_fd.c +Compiling alt_remap_cached.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_remap_cached.o HAL/src/alt_remap_cached.c +Compiling alt_remap_uncached.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_remap_uncached.o HAL/src/alt_remap_uncached.c +Compiling alt_rename.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_rename.o HAL/src/alt_rename.c +Compiling alt_sbrk.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_sbrk.o HAL/src/alt_sbrk.c +Compiling alt_settod.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_settod.o HAL/src/alt_settod.c +Compiling alt_software_exception.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_software_exception.o HAL/src/alt_software_exception.S +Compiling alt_stat.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_stat.o HAL/src/alt_stat.c +Compiling alt_tick.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_tick.o HAL/src/alt_tick.c +Compiling alt_times.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_times.o HAL/src/alt_times.c +Compiling alt_uncached_free.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_uncached_free.o HAL/src/alt_uncached_free.c +Compiling alt_uncached_malloc.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_uncached_malloc.o HAL/src/alt_uncached_malloc.c +Compiling alt_unlink.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_unlink.o HAL/src/alt_unlink.c +Compiling alt_usleep.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_usleep.o HAL/src/alt_usleep.c +Compiling alt_wait.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_wait.o HAL/src/alt_wait.c +Compiling alt_write.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_write.o HAL/src/alt_write.c +Compiling altera_nios2_qsys_irq.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/altera_nios2_qsys_irq.o HAL/src/altera_nios2_qsys_irq.c +Compiling crt0.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/crt0.o HAL/src/crt0.S +Compiling os_cpu_a.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/os_cpu_a.o HAL/src/os_cpu_a.S +Compiling os_cpu_c.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/os_cpu_c.o HAL/src/os_cpu_c.c +Compiling alt_env_lock.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/alt_env_lock.o UCOSII/src/alt_env_lock.c +Compiling alt_malloc_lock.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/alt_malloc_lock.o UCOSII/src/alt_malloc_lock.c +Compiling os_core.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_core.o UCOSII/src/os_core.c +Compiling os_dbg.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_dbg.o UCOSII/src/os_dbg.c +Compiling os_flag.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_flag.o UCOSII/src/os_flag.c +Compiling os_mbox.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_mbox.o UCOSII/src/os_mbox.c +Compiling os_mem.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_mem.o UCOSII/src/os_mem.c +Compiling os_mutex.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_mutex.o UCOSII/src/os_mutex.c +Compiling os_q.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_q.o UCOSII/src/os_q.c +Compiling os_sem.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_sem.o UCOSII/src/os_sem.c +Compiling os_task.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_task.o UCOSII/src/os_task.c +Compiling os_time.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_time.o UCOSII/src/os_time.c +Compiling os_tmr.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_tmr.o UCOSII/src/os_tmr.c +Compiling alt_sys_init.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/alt_sys_init.o alt_sys_init.c +Compiling altera_avalon_jtag_uart_fd.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_jtag_uart_fd.o drivers/src/altera_avalon_jtag_uart_fd.c +Compiling altera_avalon_jtag_uart_init.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_jtag_uart_init.o drivers/src/altera_avalon_jtag_uart_init.c +Compiling altera_avalon_jtag_uart_ioctl.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_jtag_uart_ioctl.o drivers/src/altera_avalon_jtag_uart_ioctl.c +Compiling altera_avalon_jtag_uart_read.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_jtag_uart_read.o drivers/src/altera_avalon_jtag_uart_read.c +Compiling altera_avalon_jtag_uart_write.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_jtag_uart_write.o drivers/src/altera_avalon_jtag_uart_write.c +Compiling altera_avalon_sysid_qsys.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_sysid_qsys.o drivers/src/altera_avalon_sysid_qsys.c +Compiling altera_avalon_timer_sc.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_timer_sc.o drivers/src/altera_avalon_timer_sc.c +Compiling altera_avalon_timer_ts.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_timer_ts.o drivers/src/altera_avalon_timer_ts.c +Compiling altera_avalon_timer_vars.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_timer_vars.o drivers/src/altera_avalon_timer_vars.c +Compiling altera_avalon_uart_fd.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_uart_fd.o drivers/src/altera_avalon_uart_fd.c +Compiling altera_avalon_uart_init.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_uart_init.o drivers/src/altera_avalon_uart_init.c +Compiling altera_avalon_uart_ioctl.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_uart_ioctl.o drivers/src/altera_avalon_uart_ioctl.c +Compiling altera_avalon_uart_read.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_uart_read.o drivers/src/altera_avalon_uart_read.c +Compiling altera_avalon_uart_write.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_uart_write.o drivers/src/altera_avalon_uart_write.c +drivers/src/altera_up_avalon_rs232.c: In function 'alt_up_rs232_read_fd': +Compiling altera_up_avalon_rs232.c... +drivers/src/altera_up_avalon_rs232.c:110: warning: pointer targets in passing argument 2 of 'alt_up_rs232_read_data' differ in signedness +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_up_avalon_rs232.o drivers/src/altera_up_avalon_rs232.c +Creating libucosii_bsp.a... +rm -f -f libucosii_bsp.a +nios2-elf-ar -src libucosii_bsp.a obj/HAL/src/alt_alarm_start.o obj/HAL/src/alt_busy_sleep.o obj/HAL/src/alt_close.o obj/HAL/src/alt_dcache_flush.o obj/HAL/src/alt_dcache_flush_all.o obj/HAL/src/alt_dcache_flush_no_writeback.o obj/HAL/src/alt_dev.o obj/HAL/src/alt_dev_llist_insert.o obj/HAL/src/alt_dma_rxchan_open.o obj/HAL/src/alt_dma_txchan_open.o obj/HAL/src/alt_do_ctors.o obj/HAL/src/alt_do_dtors.o obj/HAL/src/alt_environ.o obj/HAL/src/alt_errno.o obj/HAL/src/alt_exception_entry.o obj/HAL/src/alt_exception_muldiv.o obj/HAL/src/alt_exception_trap.o obj/HAL/src/alt_execve.o obj/HAL/src/alt_exit.o obj/HAL/src/alt_fcntl.o obj/HAL/src/alt_fd_lock.o obj/HAL/src/alt_fd_unlock.o obj/HAL/src/alt_find_dev.o obj/HAL/src/alt_find_file.o obj/HAL/src/alt_flash_dev.o obj/HAL/src/alt_fork.o obj/HAL/src/alt_fs_reg.o obj/HAL/src/alt_fstat.o obj/HAL/src/alt_get_fd.o obj/HAL/src/alt_getchar.o obj/HAL/src/alt_getpid.o obj/HAL/src/alt_gettod.o obj/HAL/src/alt_gmon.o obj/HAL/src/alt_icache_flush.o obj/HAL/src/alt_icache_flush_all.o obj/HAL/src/alt_iic.o obj/HAL/src/alt_iic_isr_register.o obj/HAL/src/alt_instruction_exception_entry.o obj/HAL/src/alt_instruction_exception_register.o obj/HAL/src/alt_io_redirect.o obj/HAL/src/alt_ioctl.o obj/HAL/src/alt_irq_entry.o obj/HAL/src/alt_irq_handler.o obj/HAL/src/alt_irq_register.o obj/HAL/src/alt_irq_vars.o obj/HAL/src/alt_isatty.o obj/HAL/src/alt_kill.o obj/HAL/src/alt_link.o obj/HAL/src/alt_load.o obj/HAL/src/alt_log_macro.o obj/HAL/src/alt_log_printf.o obj/HAL/src/alt_lseek.o obj/HAL/src/alt_main.o obj/HAL/src/alt_mcount.o obj/HAL/src/alt_open.o obj/HAL/src/alt_printf.o obj/HAL/src/alt_putchar.o obj/HAL/src/alt_putstr.o obj/HAL/src/alt_read.o obj/HAL/src/alt_release_fd.o obj/HAL/src/alt_remap_cached.o obj/HAL/src/alt_remap_uncached.o obj/HAL/src/alt_rename.o obj/HAL/src/alt_sbrk.o obj/HAL/src/alt_settod.o obj/HAL/src/alt_software_exception.o obj/HAL/src/alt_stat.o obj/HAL/src/alt_tick.o obj/HAL/src/alt_times.o obj/HAL/src/alt_uncached_free.o obj/HAL/src/alt_uncached_malloc.o obj/HAL/src/alt_unlink.o obj/HAL/src/alt_usleep.o obj/HAL/src/alt_wait.o obj/HAL/src/alt_write.o obj/HAL/src/altera_nios2_qsys_irq.o obj/HAL/src/crt0.o obj/HAL/src/os_cpu_a.o obj/HAL/src/os_cpu_c.o obj/UCOSII/src/alt_env_lock.o obj/UCOSII/src/alt_malloc_lock.o obj/UCOSII/src/os_core.o obj/UCOSII/src/os_dbg.o obj/UCOSII/src/os_flag.o obj/UCOSII/src/os_mbox.o obj/UCOSII/src/os_mem.o obj/UCOSII/src/os_mutex.o obj/UCOSII/src/os_q.o obj/UCOSII/src/os_sem.o obj/UCOSII/src/os_task.o obj/UCOSII/src/os_time.o obj/UCOSII/src/os_tmr.o obj/alt_sys_init.o obj/drivers/src/altera_avalon_jtag_uart_fd.o obj/drivers/src/altera_avalon_jtag_uart_init.o obj/drivers/src/altera_avalon_jtag_uart_ioctl.o obj/drivers/src/altera_avalon_jtag_uart_read.o obj/drivers/src/altera_avalon_jtag_uart_write.o obj/drivers/src/altera_avalon_sysid_qsys.o obj/drivers/src/altera_avalon_timer_sc.o obj/drivers/src/altera_avalon_timer_ts.o obj/drivers/src/altera_avalon_timer_vars.o obj/drivers/src/altera_avalon_uart_fd.o obj/drivers/src/altera_avalon_uart_init.o obj/drivers/src/altera_avalon_uart_ioctl.o obj/drivers/src/altera_avalon_uart_read.o obj/drivers/src/altera_avalon_uart_write.o obj/drivers/src/altera_up_avalon_rs232.o +[BSP build complete] +Info: Compiling MotorHandler.cpp to obj/default/MotorHandler.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/MotorHandler.o MotorHandler.cpp +Info: Compiling main.cpp to obj/default/main.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/main.o main.cpp +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010a0 --timestamp 1394124174 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD" --jdi C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.jdi --sopcinfo C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo +Info: (MCTest.elf) 140 KBytes program size (code + initialized data). +Info: 16236 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling MotorHandler.cpp to obj/default/MotorHandler.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/MotorHandler.o MotorHandler.cpp +MotorHandler.cpp:148: error: no 'void MotorHandler::resetMC()' member function declared in class 'MotorHandler' +make: *** [obj/default/MotorHandler.o] Error 1 + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling MotorHandler.cpp to obj/default/MotorHandler.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/MotorHandler.o MotorHandler.cpp +MotorHandler.cpp:148: error: no 'void MotorHandler::resetMC()' member function declared in class 'MotorHandler' +make: *** [obj/default/MotorHandler.o] Error 1 + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling MotorHandler.cpp to obj/default/MotorHandler.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/MotorHandler.o MotorHandler.cpp +Info: Compiling main.cpp to obj/default/main.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/main.o main.cpp +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010a0 --timestamp 1394124174 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD" --jdi C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.jdi --sopcinfo C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo +Info: (MCTest.elf) 140 KBytes program size (code + initialized data). +Info: 16236 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling MotorHandler.cpp to obj/default/MotorHandler.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/MotorHandler.o MotorHandler.cpp +Info: Compiling main.cpp to obj/default/main.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/main.o main.cpp +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010a0 --timestamp 1394124174 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD" --jdi C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.jdi --sopcinfo C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo +Info: (MCTest.elf) 140 KBytes program size (code + initialized data). +Info: 16236 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling MotorHandler.cpp to obj/default/MotorHandler.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/MotorHandler.o MotorHandler.cpp +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010a0 --timestamp 1394124174 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD" --jdi C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.jdi --sopcinfo C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo +Info: (MCTest.elf) 140 KBytes program size (code + initialized data). +Info: 16236 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling MotorHandler.cpp to obj/default/MotorHandler.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/MotorHandler.o MotorHandler.cpp +Info: Compiling main.cpp to obj/default/main.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/main.o main.cpp +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010a0 --timestamp 1394124174 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD" --jdi C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.jdi --sopcinfo C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo +Info: (MCTest.elf) 140 KBytes program size (code + initialized data). +Info: 16236 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling MotorHandler.cpp to obj/default/MotorHandler.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/MotorHandler.o MotorHandler.cpp +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010a0 --timestamp 1394124174 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD" --jdi C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.jdi --sopcinfo C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo +Info: (MCTest.elf) 140 KBytes program size (code + initialized data). +Info: 16236 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling MotorHandler.cpp to obj/default/MotorHandler.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/MotorHandler.o MotorHandler.cpp +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010a0 --timestamp 1394124174 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD" --jdi C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.jdi --sopcinfo C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo +Info: (MCTest.elf) 140 KBytes program size (code + initialized data). +Info: 16236 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling MotorHandler.cpp to obj/default/MotorHandler.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/MotorHandler.o MotorHandler.cpp +Info: Compiling main.cpp to obj/default/main.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/main.o main.cpp +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010a0 --timestamp 1394124174 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD" --jdi C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.jdi --sopcinfo C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo +Info: (MCTest.elf) 140 KBytes program size (code + initialized data). +Info: 16236 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling main.cpp to obj/default/main.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/main.o main.cpp +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010a0 --timestamp 1394124174 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD" --jdi C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.jdi --sopcinfo C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo +Info: (MCTest.elf) 140 KBytes program size (code + initialized data). +Info: 16236 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling main.cpp to obj/default/main.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/main.o main.cpp +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010a0 --timestamp 1394124174 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD" --jdi C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.jdi --sopcinfo C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo +Info: (MCTest.elf) 140 KBytes program size (code + initialized data). +Info: 16236 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling main.cpp to obj/default/main.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/main.o main.cpp +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010a0 --timestamp 1394124174 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD" --jdi C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.jdi --sopcinfo C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo +Info: (MCTest.elf) 140 KBytes program size (code + initialized data). +Info: 16236 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling main.cpp to obj/default/main.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/main.o main.cpp +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010a0 --timestamp 1394124174 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD" --jdi C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.jdi --sopcinfo C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo +Info: (MCTest.elf) 140 KBytes program size (code + initialized data). +Info: 16236 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling main.cpp to obj/default/main.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/main.o main.cpp +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010a0 --timestamp 1394124174 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD" --jdi C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.jdi --sopcinfo C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo +Info: (MCTest.elf) 140 KBytes program size (code + initialized data). +Info: 16236 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling main.cpp to obj/default/main.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/main.o main.cpp +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010a0 --timestamp 1394124174 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD" --jdi C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.jdi --sopcinfo C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo +Info: (MCTest.elf) 140 KBytes program size (code + initialized data). +Info: 16236 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling MotorHandler.cpp to obj/default/MotorHandler.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/MotorHandler.o MotorHandler.cpp +Info: Compiling main.cpp to obj/default/main.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/main.o main.cpp +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010a0 --timestamp 1394124174 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD" --jdi C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.jdi --sopcinfo C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo +Info: (MCTest.elf) 140 KBytes program size (code + initialized data). +Info: 16236 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling main.cpp to obj/default/main.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/main.o main.cpp +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010a0 --timestamp 1394124174 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD" --jdi C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.jdi --sopcinfo C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo +Info: (MCTest.elf) 140 KBytes program size (code + initialized data). +Info: 16236 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling MotorHandler.cpp to obj/default/MotorHandler.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/MotorHandler.o MotorHandler.cpp +Info: Compiling main.cpp to obj/default/main.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/main.o main.cpp +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010a0 --timestamp 1394124174 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD" --jdi C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.jdi --sopcinfo C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo +Info: (MCTest.elf) 140 KBytes program size (code + initialized data). +Info: 16236 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling main.cpp to obj/default/main.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/main.o main.cpp +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010a0 --timestamp 1394124174 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD" --jdi C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.jdi --sopcinfo C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo +Info: (MCTest.elf) 140 KBytes program size (code + initialized data). +Info: 16236 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Clean-only build of configuration Nios II for project MCTest **** + +make clean +[MCTest clean complete] + +**** Build Finished **** + +**** Clean-only build of configuration Nios II for project MCTest_bsp **** + +make clean +[BSP clean complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +Compiling alt_alarm_start.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_alarm_start.o HAL/src/alt_alarm_start.c +Compiling alt_busy_sleep.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_busy_sleep.o HAL/src/alt_busy_sleep.c +Compiling alt_close.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_close.o HAL/src/alt_close.c +Compiling alt_dcache_flush.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dcache_flush.o HAL/src/alt_dcache_flush.c +Compiling alt_dcache_flush_all.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dcache_flush_all.o HAL/src/alt_dcache_flush_all.c +Compiling alt_dcache_flush_no_writeback.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dcache_flush_no_writeback.o HAL/src/alt_dcache_flush_no_writeback.c +Compiling alt_dev.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dev.o HAL/src/alt_dev.c +Compiling alt_dev_llist_insert.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dev_llist_insert.o HAL/src/alt_dev_llist_insert.c +Compiling alt_dma_rxchan_open.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dma_rxchan_open.o HAL/src/alt_dma_rxchan_open.c +Compiling alt_dma_txchan_open.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dma_txchan_open.o HAL/src/alt_dma_txchan_open.c +Compiling alt_do_ctors.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_do_ctors.o HAL/src/alt_do_ctors.c +Compiling alt_do_dtors.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_do_dtors.o HAL/src/alt_do_dtors.c +Compiling alt_environ.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_environ.o HAL/src/alt_environ.c +Compiling alt_errno.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_errno.o HAL/src/alt_errno.c +Compiling alt_exception_entry.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_exception_entry.o HAL/src/alt_exception_entry.S +Compiling alt_exception_muldiv.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_exception_muldiv.o HAL/src/alt_exception_muldiv.S +Compiling alt_exception_trap.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_exception_trap.o HAL/src/alt_exception_trap.S +Compiling alt_execve.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_execve.o HAL/src/alt_execve.c +Compiling alt_exit.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_exit.o HAL/src/alt_exit.c +Compiling alt_fcntl.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fcntl.o HAL/src/alt_fcntl.c +Compiling alt_fd_lock.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fd_lock.o HAL/src/alt_fd_lock.c +Compiling alt_fd_unlock.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fd_unlock.o HAL/src/alt_fd_unlock.c +Compiling alt_find_dev.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_find_dev.o HAL/src/alt_find_dev.c +Compiling alt_find_file.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_find_file.o HAL/src/alt_find_file.c +Compiling alt_flash_dev.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_flash_dev.o HAL/src/alt_flash_dev.c +Compiling alt_fork.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fork.o HAL/src/alt_fork.c +Compiling alt_fs_reg.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fs_reg.o HAL/src/alt_fs_reg.c +Compiling alt_fstat.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fstat.o HAL/src/alt_fstat.c +Compiling alt_get_fd.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_get_fd.o HAL/src/alt_get_fd.c +Compiling alt_getchar.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_getchar.o HAL/src/alt_getchar.c +Compiling alt_getpid.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_getpid.o HAL/src/alt_getpid.c +Compiling alt_gettod.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_gettod.o HAL/src/alt_gettod.c +Compiling alt_gmon.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_gmon.o HAL/src/alt_gmon.c +Compiling alt_icache_flush.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_icache_flush.o HAL/src/alt_icache_flush.c +Compiling alt_icache_flush_all.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_icache_flush_all.o HAL/src/alt_icache_flush_all.c +Compiling alt_iic.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_iic.o HAL/src/alt_iic.c +Compiling alt_iic_isr_register.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_iic_isr_register.o HAL/src/alt_iic_isr_register.c +Compiling alt_instruction_exception_entry.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_instruction_exception_entry.o HAL/src/alt_instruction_exception_entry.c +Compiling alt_instruction_exception_register.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_instruction_exception_register.o HAL/src/alt_instruction_exception_register.c +Compiling alt_io_redirect.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_io_redirect.o HAL/src/alt_io_redirect.c +Compiling alt_ioctl.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_ioctl.o HAL/src/alt_ioctl.c +Compiling alt_irq_entry.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_irq_entry.o HAL/src/alt_irq_entry.S +Compiling alt_irq_handler.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_irq_handler.o HAL/src/alt_irq_handler.c +Compiling alt_irq_register.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_irq_register.o HAL/src/alt_irq_register.c +Compiling alt_irq_vars.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_irq_vars.o HAL/src/alt_irq_vars.c +Compiling alt_isatty.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_isatty.o HAL/src/alt_isatty.c +Compiling alt_kill.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_kill.o HAL/src/alt_kill.c +Compiling alt_link.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_link.o HAL/src/alt_link.c +Compiling alt_load.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_load.o HAL/src/alt_load.c +Compiling alt_log_macro.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_log_macro.o HAL/src/alt_log_macro.S +Compiling alt_log_printf.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_log_printf.o HAL/src/alt_log_printf.c +Compiling alt_lseek.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_lseek.o HAL/src/alt_lseek.c +Compiling alt_main.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_main.o HAL/src/alt_main.c +Compiling alt_mcount.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_mcount.o HAL/src/alt_mcount.S +Compiling alt_open.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_open.o HAL/src/alt_open.c +Compiling alt_printf.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_printf.o HAL/src/alt_printf.c +Compiling alt_putchar.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_putchar.o HAL/src/alt_putchar.c +Compiling alt_putstr.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_putstr.o HAL/src/alt_putstr.c +Compiling alt_read.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_read.o HAL/src/alt_read.c +Compiling alt_release_fd.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_release_fd.o HAL/src/alt_release_fd.c +Compiling alt_remap_cached.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_remap_cached.o HAL/src/alt_remap_cached.c +Compiling alt_remap_uncached.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_remap_uncached.o HAL/src/alt_remap_uncached.c +Compiling alt_rename.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_rename.o HAL/src/alt_rename.c +Compiling alt_sbrk.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_sbrk.o HAL/src/alt_sbrk.c +Compiling alt_settod.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_settod.o HAL/src/alt_settod.c +Compiling alt_software_exception.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_software_exception.o HAL/src/alt_software_exception.S +Compiling alt_stat.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_stat.o HAL/src/alt_stat.c +Compiling alt_tick.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_tick.o HAL/src/alt_tick.c +Compiling alt_times.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_times.o HAL/src/alt_times.c +Compiling alt_uncached_free.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_uncached_free.o HAL/src/alt_uncached_free.c +Compiling alt_uncached_malloc.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_uncached_malloc.o HAL/src/alt_uncached_malloc.c +Compiling alt_unlink.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_unlink.o HAL/src/alt_unlink.c +Compiling alt_usleep.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_usleep.o HAL/src/alt_usleep.c +Compiling alt_wait.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_wait.o HAL/src/alt_wait.c +Compiling alt_write.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_write.o HAL/src/alt_write.c +Compiling altera_nios2_qsys_irq.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/altera_nios2_qsys_irq.o HAL/src/altera_nios2_qsys_irq.c +Compiling crt0.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/crt0.o HAL/src/crt0.S +Compiling os_cpu_a.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/os_cpu_a.o HAL/src/os_cpu_a.S +Compiling os_cpu_c.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/os_cpu_c.o HAL/src/os_cpu_c.c +Compiling alt_env_lock.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/alt_env_lock.o UCOSII/src/alt_env_lock.c +Compiling alt_malloc_lock.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/alt_malloc_lock.o UCOSII/src/alt_malloc_lock.c +Compiling os_core.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_core.o UCOSII/src/os_core.c +Compiling os_dbg.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_dbg.o UCOSII/src/os_dbg.c +Compiling os_flag.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_flag.o UCOSII/src/os_flag.c +Compiling os_mbox.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_mbox.o UCOSII/src/os_mbox.c +Compiling os_mem.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_mem.o UCOSII/src/os_mem.c +Compiling os_mutex.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_mutex.o UCOSII/src/os_mutex.c +Compiling os_q.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_q.o UCOSII/src/os_q.c +Compiling os_sem.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_sem.o UCOSII/src/os_sem.c +Compiling os_task.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_task.o UCOSII/src/os_task.c +Compiling os_time.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_time.o UCOSII/src/os_time.c +Compiling os_tmr.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_tmr.o UCOSII/src/os_tmr.c +Compiling alt_sys_init.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/alt_sys_init.o alt_sys_init.c +Compiling altera_avalon_jtag_uart_fd.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_jtag_uart_fd.o drivers/src/altera_avalon_jtag_uart_fd.c +Compiling altera_avalon_jtag_uart_init.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_jtag_uart_init.o drivers/src/altera_avalon_jtag_uart_init.c +Compiling altera_avalon_jtag_uart_ioctl.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_jtag_uart_ioctl.o drivers/src/altera_avalon_jtag_uart_ioctl.c +Compiling altera_avalon_jtag_uart_read.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_jtag_uart_read.o drivers/src/altera_avalon_jtag_uart_read.c +Compiling altera_avalon_jtag_uart_write.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_jtag_uart_write.o drivers/src/altera_avalon_jtag_uart_write.c +Compiling altera_avalon_sysid_qsys.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_sysid_qsys.o drivers/src/altera_avalon_sysid_qsys.c +Compiling altera_avalon_timer_sc.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_timer_sc.o drivers/src/altera_avalon_timer_sc.c +Compiling altera_avalon_timer_ts.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_timer_ts.o drivers/src/altera_avalon_timer_ts.c +Compiling altera_avalon_timer_vars.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_timer_vars.o drivers/src/altera_avalon_timer_vars.c +Compiling altera_avalon_uart_fd.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_uart_fd.o drivers/src/altera_avalon_uart_fd.c +Compiling altera_avalon_uart_init.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_uart_init.o drivers/src/altera_avalon_uart_init.c +Compiling altera_avalon_uart_ioctl.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_uart_ioctl.o drivers/src/altera_avalon_uart_ioctl.c +Compiling altera_avalon_uart_read.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_uart_read.o drivers/src/altera_avalon_uart_read.c +Compiling altera_avalon_uart_write.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_uart_write.o drivers/src/altera_avalon_uart_write.c +drivers/src/altera_up_avalon_rs232.c: In function 'alt_up_rs232_read_fd': +Compiling altera_up_avalon_rs232.c... +drivers/src/altera_up_avalon_rs232.c:110: warning: pointer targets in passing argument 2 of 'alt_up_rs232_read_data' differ in signedness +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_up_avalon_rs232.o drivers/src/altera_up_avalon_rs232.c +Creating libucosii_bsp.a... +rm -f -f libucosii_bsp.a +nios2-elf-ar -src libucosii_bsp.a obj/HAL/src/alt_alarm_start.o obj/HAL/src/alt_busy_sleep.o obj/HAL/src/alt_close.o obj/HAL/src/alt_dcache_flush.o obj/HAL/src/alt_dcache_flush_all.o obj/HAL/src/alt_dcache_flush_no_writeback.o obj/HAL/src/alt_dev.o obj/HAL/src/alt_dev_llist_insert.o obj/HAL/src/alt_dma_rxchan_open.o obj/HAL/src/alt_dma_txchan_open.o obj/HAL/src/alt_do_ctors.o obj/HAL/src/alt_do_dtors.o obj/HAL/src/alt_environ.o obj/HAL/src/alt_errno.o obj/HAL/src/alt_exception_entry.o obj/HAL/src/alt_exception_muldiv.o obj/HAL/src/alt_exception_trap.o obj/HAL/src/alt_execve.o obj/HAL/src/alt_exit.o obj/HAL/src/alt_fcntl.o obj/HAL/src/alt_fd_lock.o obj/HAL/src/alt_fd_unlock.o obj/HAL/src/alt_find_dev.o obj/HAL/src/alt_find_file.o obj/HAL/src/alt_flash_dev.o obj/HAL/src/alt_fork.o obj/HAL/src/alt_fs_reg.o obj/HAL/src/alt_fstat.o obj/HAL/src/alt_get_fd.o obj/HAL/src/alt_getchar.o obj/HAL/src/alt_getpid.o obj/HAL/src/alt_gettod.o obj/HAL/src/alt_gmon.o obj/HAL/src/alt_icache_flush.o obj/HAL/src/alt_icache_flush_all.o obj/HAL/src/alt_iic.o obj/HAL/src/alt_iic_isr_register.o obj/HAL/src/alt_instruction_exception_entry.o obj/HAL/src/alt_instruction_exception_register.o obj/HAL/src/alt_io_redirect.o obj/HAL/src/alt_ioctl.o obj/HAL/src/alt_irq_entry.o obj/HAL/src/alt_irq_handler.o obj/HAL/src/alt_irq_register.o obj/HAL/src/alt_irq_vars.o obj/HAL/src/alt_isatty.o obj/HAL/src/alt_kill.o obj/HAL/src/alt_link.o obj/HAL/src/alt_load.o obj/HAL/src/alt_log_macro.o obj/HAL/src/alt_log_printf.o obj/HAL/src/alt_lseek.o obj/HAL/src/alt_main.o obj/HAL/src/alt_mcount.o obj/HAL/src/alt_open.o obj/HAL/src/alt_printf.o obj/HAL/src/alt_putchar.o obj/HAL/src/alt_putstr.o obj/HAL/src/alt_read.o obj/HAL/src/alt_release_fd.o obj/HAL/src/alt_remap_cached.o obj/HAL/src/alt_remap_uncached.o obj/HAL/src/alt_rename.o obj/HAL/src/alt_sbrk.o obj/HAL/src/alt_settod.o obj/HAL/src/alt_software_exception.o obj/HAL/src/alt_stat.o obj/HAL/src/alt_tick.o obj/HAL/src/alt_times.o obj/HAL/src/alt_uncached_free.o obj/HAL/src/alt_uncached_malloc.o obj/HAL/src/alt_unlink.o obj/HAL/src/alt_usleep.o obj/HAL/src/alt_wait.o obj/HAL/src/alt_write.o obj/HAL/src/altera_nios2_qsys_irq.o obj/HAL/src/crt0.o obj/HAL/src/os_cpu_a.o obj/HAL/src/os_cpu_c.o obj/UCOSII/src/alt_env_lock.o obj/UCOSII/src/alt_malloc_lock.o obj/UCOSII/src/os_core.o obj/UCOSII/src/os_dbg.o obj/UCOSII/src/os_flag.o obj/UCOSII/src/os_mbox.o obj/UCOSII/src/os_mem.o obj/UCOSII/src/os_mutex.o obj/UCOSII/src/os_q.o obj/UCOSII/src/os_sem.o obj/UCOSII/src/os_task.o obj/UCOSII/src/os_time.o obj/UCOSII/src/os_tmr.o obj/alt_sys_init.o obj/drivers/src/altera_avalon_jtag_uart_fd.o obj/drivers/src/altera_avalon_jtag_uart_init.o obj/drivers/src/altera_avalon_jtag_uart_ioctl.o obj/drivers/src/altera_avalon_jtag_uart_read.o obj/drivers/src/altera_avalon_jtag_uart_write.o obj/drivers/src/altera_avalon_sysid_qsys.o obj/drivers/src/altera_avalon_timer_sc.o obj/drivers/src/altera_avalon_timer_ts.o obj/drivers/src/altera_avalon_timer_vars.o obj/drivers/src/altera_avalon_uart_fd.o obj/drivers/src/altera_avalon_uart_init.o obj/drivers/src/altera_avalon_uart_ioctl.o obj/drivers/src/altera_avalon_uart_read.o obj/drivers/src/altera_avalon_uart_write.o obj/drivers/src/altera_up_avalon_rs232.o +[BSP build complete] +Info: Compiling MotorHandler.cpp to obj/default/MotorHandler.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/MotorHandler.o MotorHandler.cpp +Info: Compiling main.cpp to obj/default/main.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/main.o main.cpp +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010a0 --timestamp 1394124174 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD" --jdi C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.jdi --sopcinfo C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo +Info: (MCTest.elf) 140 KBytes program size (code + initialized data). +Info: 16236 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling main.cpp to obj/default/main.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/main.o main.cpp +main.cpp: In function 'void mc_task(void*)': +main.cpp:79: error: 'OSTimeDlyHMS' was not declared in this scope +make: *** [obj/default/main.o] Error 1 + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling main.cpp to obj/default/main.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/main.o main.cpp +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010a0 --timestamp 1394124174 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD" --jdi C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.jdi --sopcinfo C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo +Info: (MCTest.elf) 140 KBytes program size (code + initialized data). +Info: 16236 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling main.cpp to obj/default/main.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/main.o main.cpp +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010a0 --timestamp 1394124174 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD" --jdi C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.jdi --sopcinfo C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo +Info: (MCTest.elf) 140 KBytes program size (code + initialized data). +Info: 16236 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling MotorHandler.cpp to obj/default/MotorHandler.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/MotorHandler.o MotorHandler.cpp +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010a0 --timestamp 1394124174 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD" --jdi C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.jdi --sopcinfo C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo +Info: (MCTest.elf) 140 KBytes program size (code + initialized data). +Info: 16236 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling MotorHandler.cpp to obj/default/MotorHandler.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/MotorHandler.o MotorHandler.cpp +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010a0 --timestamp 1394124174 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD" --jdi C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.jdi --sopcinfo C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo +Info: (MCTest.elf) 140 KBytes program size (code + initialized data). +Info: 16236 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling main.cpp to obj/default/main.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/main.o main.cpp +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010a0 --timestamp 1394124174 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD" --jdi C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.jdi --sopcinfo C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo +Info: (MCTest.elf) 140 KBytes program size (code + initialized data). +Info: 16236 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling main.cpp to obj/default/main.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/main.o main.cpp +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010a0 --timestamp 1394124174 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD" --jdi C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.jdi --sopcinfo C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo +Info: (MCTest.elf) 140 KBytes program size (code + initialized data). +Info: 16236 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling MotorHandler.cpp to obj/default/MotorHandler.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/MotorHandler.o MotorHandler.cpp +Info: Compiling main.cpp to obj/default/main.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/main.o main.cpp +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010a0 --timestamp 1394124174 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD" --jdi C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.jdi --sopcinfo C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo +Info: (MCTest.elf) 140 KBytes program size (code + initialized data). +Info: 16236 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling MotorHandler.cpp to obj/default/MotorHandler.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/MotorHandler.o MotorHandler.cpp +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010a0 --timestamp 1394124174 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD" --jdi C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.jdi --sopcinfo C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo +Info: (MCTest.elf) 140 KBytes program size (code + initialized data). +Info: 16236 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling MotorHandler.cpp to obj/default/MotorHandler.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/MotorHandler.o MotorHandler.cpp +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010a0 --timestamp 1394124174 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD" --jdi C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.jdi --sopcinfo C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo +Info: (MCTest.elf) 140 KBytes program size (code + initialized data). +Info: 16236 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling main.cpp to obj/default/main.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/main.o main.cpp +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010a0 --timestamp 1394124174 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD" --jdi C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.jdi --sopcinfo C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo +Info: (MCTest.elf) 140 KBytes program size (code + initialized data). +Info: 16236 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling main.cpp to obj/default/main.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/main.o main.cpp +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010a0 --timestamp 1394124174 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD" --jdi C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.jdi --sopcinfo C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo +Info: (MCTest.elf) 140 KBytes program size (code + initialized data). +Info: 16236 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling MotorHandler.cpp to obj/default/MotorHandler.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/MotorHandler.o MotorHandler.cpp +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010a0 --timestamp 1394124174 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD" --jdi C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.jdi --sopcinfo C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo +Info: (MCTest.elf) 140 KBytes program size (code + initialized data). +Info: 16236 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Clean-only build of configuration Nios II for project MCTest **** + +make clean +[MCTest clean complete] + +**** Build Finished **** + +**** Clean-only build of configuration Nios II for project MCTest_bsp **** + +make clean +[BSP clean complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +Compiling alt_alarm_start.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_alarm_start.o HAL/src/alt_alarm_start.c +Compiling alt_busy_sleep.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_busy_sleep.o HAL/src/alt_busy_sleep.c +Compiling alt_close.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_close.o HAL/src/alt_close.c +Compiling alt_dcache_flush.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dcache_flush.o HAL/src/alt_dcache_flush.c +Compiling alt_dcache_flush_all.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dcache_flush_all.o HAL/src/alt_dcache_flush_all.c +Compiling alt_dcache_flush_no_writeback.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dcache_flush_no_writeback.o HAL/src/alt_dcache_flush_no_writeback.c +Compiling alt_dev.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dev.o HAL/src/alt_dev.c +Compiling alt_dev_llist_insert.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dev_llist_insert.o HAL/src/alt_dev_llist_insert.c +Compiling alt_dma_rxchan_open.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dma_rxchan_open.o HAL/src/alt_dma_rxchan_open.c +Compiling alt_dma_txchan_open.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dma_txchan_open.o HAL/src/alt_dma_txchan_open.c +Compiling alt_do_ctors.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_do_ctors.o HAL/src/alt_do_ctors.c +Compiling alt_do_dtors.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_do_dtors.o HAL/src/alt_do_dtors.c +Compiling alt_environ.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_environ.o HAL/src/alt_environ.c +Compiling alt_errno.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_errno.o HAL/src/alt_errno.c +Compiling alt_exception_entry.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_exception_entry.o HAL/src/alt_exception_entry.S +Compiling alt_exception_muldiv.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_exception_muldiv.o HAL/src/alt_exception_muldiv.S +Compiling alt_exception_trap.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_exception_trap.o HAL/src/alt_exception_trap.S +Compiling alt_execve.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_execve.o HAL/src/alt_execve.c +Compiling alt_exit.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_exit.o HAL/src/alt_exit.c +Compiling alt_fcntl.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fcntl.o HAL/src/alt_fcntl.c +Compiling alt_fd_lock.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fd_lock.o HAL/src/alt_fd_lock.c +Compiling alt_fd_unlock.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fd_unlock.o HAL/src/alt_fd_unlock.c +Compiling alt_find_dev.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_find_dev.o HAL/src/alt_find_dev.c +Compiling alt_find_file.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_find_file.o HAL/src/alt_find_file.c +Compiling alt_flash_dev.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_flash_dev.o HAL/src/alt_flash_dev.c +Compiling alt_fork.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fork.o HAL/src/alt_fork.c +Compiling alt_fs_reg.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fs_reg.o HAL/src/alt_fs_reg.c +Compiling alt_fstat.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fstat.o HAL/src/alt_fstat.c +Compiling alt_get_fd.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_get_fd.o HAL/src/alt_get_fd.c +Compiling alt_getchar.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_getchar.o HAL/src/alt_getchar.c +Compiling alt_getpid.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_getpid.o HAL/src/alt_getpid.c +Compiling alt_gettod.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_gettod.o HAL/src/alt_gettod.c +Compiling alt_gmon.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_gmon.o HAL/src/alt_gmon.c +Compiling alt_icache_flush.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_icache_flush.o HAL/src/alt_icache_flush.c +Compiling alt_icache_flush_all.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_icache_flush_all.o HAL/src/alt_icache_flush_all.c +Compiling alt_iic.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_iic.o HAL/src/alt_iic.c +Compiling alt_iic_isr_register.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_iic_isr_register.o HAL/src/alt_iic_isr_register.c +Compiling alt_instruction_exception_entry.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_instruction_exception_entry.o HAL/src/alt_instruction_exception_entry.c +Compiling alt_instruction_exception_register.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_instruction_exception_register.o HAL/src/alt_instruction_exception_register.c +Compiling alt_io_redirect.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_io_redirect.o HAL/src/alt_io_redirect.c +Compiling alt_ioctl.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_ioctl.o HAL/src/alt_ioctl.c +Compiling alt_irq_entry.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_irq_entry.o HAL/src/alt_irq_entry.S +Compiling alt_irq_handler.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_irq_handler.o HAL/src/alt_irq_handler.c +Compiling alt_irq_register.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_irq_register.o HAL/src/alt_irq_register.c +Compiling alt_irq_vars.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_irq_vars.o HAL/src/alt_irq_vars.c +Compiling alt_isatty.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_isatty.o HAL/src/alt_isatty.c +Compiling alt_kill.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_kill.o HAL/src/alt_kill.c +Compiling alt_link.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_link.o HAL/src/alt_link.c +Compiling alt_load.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_load.o HAL/src/alt_load.c +Compiling alt_log_macro.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_log_macro.o HAL/src/alt_log_macro.S +Compiling alt_log_printf.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_log_printf.o HAL/src/alt_log_printf.c +Compiling alt_lseek.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_lseek.o HAL/src/alt_lseek.c +Compiling alt_main.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_main.o HAL/src/alt_main.c +Compiling alt_mcount.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_mcount.o HAL/src/alt_mcount.S +Compiling alt_open.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_open.o HAL/src/alt_open.c +Compiling alt_printf.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_printf.o HAL/src/alt_printf.c +Compiling alt_putchar.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_putchar.o HAL/src/alt_putchar.c +Compiling alt_putstr.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_putstr.o HAL/src/alt_putstr.c +Compiling alt_read.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_read.o HAL/src/alt_read.c +Compiling alt_release_fd.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_release_fd.o HAL/src/alt_release_fd.c +Compiling alt_remap_cached.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_remap_cached.o HAL/src/alt_remap_cached.c +Compiling alt_remap_uncached.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_remap_uncached.o HAL/src/alt_remap_uncached.c +Compiling alt_rename.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_rename.o HAL/src/alt_rename.c +Compiling alt_sbrk.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_sbrk.o HAL/src/alt_sbrk.c +Compiling alt_settod.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_settod.o HAL/src/alt_settod.c +Compiling alt_software_exception.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_software_exception.o HAL/src/alt_software_exception.S +Compiling alt_stat.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_stat.o HAL/src/alt_stat.c +Compiling alt_tick.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_tick.o HAL/src/alt_tick.c +Compiling alt_times.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_times.o HAL/src/alt_times.c +Compiling alt_uncached_free.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_uncached_free.o HAL/src/alt_uncached_free.c +Compiling alt_uncached_malloc.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_uncached_malloc.o HAL/src/alt_uncached_malloc.c +Compiling alt_unlink.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_unlink.o HAL/src/alt_unlink.c +Compiling alt_usleep.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_usleep.o HAL/src/alt_usleep.c +Compiling alt_wait.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_wait.o HAL/src/alt_wait.c +Compiling alt_write.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_write.o HAL/src/alt_write.c +Compiling altera_nios2_qsys_irq.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/altera_nios2_qsys_irq.o HAL/src/altera_nios2_qsys_irq.c +Compiling crt0.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/crt0.o HAL/src/crt0.S +Compiling os_cpu_a.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/os_cpu_a.o HAL/src/os_cpu_a.S +Compiling os_cpu_c.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/os_cpu_c.o HAL/src/os_cpu_c.c +Compiling alt_env_lock.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/alt_env_lock.o UCOSII/src/alt_env_lock.c +Compiling alt_malloc_lock.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/alt_malloc_lock.o UCOSII/src/alt_malloc_lock.c +Compiling os_core.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_core.o UCOSII/src/os_core.c +Compiling os_dbg.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_dbg.o UCOSII/src/os_dbg.c +Compiling os_flag.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_flag.o UCOSII/src/os_flag.c +Compiling os_mbox.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_mbox.o UCOSII/src/os_mbox.c +Compiling os_mem.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_mem.o UCOSII/src/os_mem.c +Compiling os_mutex.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_mutex.o UCOSII/src/os_mutex.c +Compiling os_q.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_q.o UCOSII/src/os_q.c +Compiling os_sem.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_sem.o UCOSII/src/os_sem.c +Compiling os_task.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_task.o UCOSII/src/os_task.c +Compiling os_time.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_time.o UCOSII/src/os_time.c +Compiling os_tmr.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_tmr.o UCOSII/src/os_tmr.c +Compiling alt_sys_init.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/alt_sys_init.o alt_sys_init.c +Compiling altera_avalon_jtag_uart_fd.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_jtag_uart_fd.o drivers/src/altera_avalon_jtag_uart_fd.c +Compiling altera_avalon_jtag_uart_init.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_jtag_uart_init.o drivers/src/altera_avalon_jtag_uart_init.c +Compiling altera_avalon_jtag_uart_ioctl.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_jtag_uart_ioctl.o drivers/src/altera_avalon_jtag_uart_ioctl.c +Compiling altera_avalon_jtag_uart_read.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_jtag_uart_read.o drivers/src/altera_avalon_jtag_uart_read.c +Compiling altera_avalon_jtag_uart_write.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_jtag_uart_write.o drivers/src/altera_avalon_jtag_uart_write.c +Compiling altera_avalon_sysid_qsys.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_sysid_qsys.o drivers/src/altera_avalon_sysid_qsys.c +Compiling altera_avalon_timer_sc.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_timer_sc.o drivers/src/altera_avalon_timer_sc.c +Compiling altera_avalon_timer_ts.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_timer_ts.o drivers/src/altera_avalon_timer_ts.c +Compiling altera_avalon_timer_vars.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_timer_vars.o drivers/src/altera_avalon_timer_vars.c +Compiling altera_avalon_uart_fd.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_uart_fd.o drivers/src/altera_avalon_uart_fd.c +Compiling altera_avalon_uart_init.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_uart_init.o drivers/src/altera_avalon_uart_init.c +Compiling altera_avalon_uart_ioctl.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_uart_ioctl.o drivers/src/altera_avalon_uart_ioctl.c +Compiling altera_avalon_uart_read.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_uart_read.o drivers/src/altera_avalon_uart_read.c +Compiling altera_avalon_uart_write.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_uart_write.o drivers/src/altera_avalon_uart_write.c +drivers/src/altera_up_avalon_rs232.c: In function 'alt_up_rs232_read_fd': +Compiling altera_up_avalon_rs232.c... +drivers/src/altera_up_avalon_rs232.c:110: warning: pointer targets in passing argument 2 of 'alt_up_rs232_read_data' differ in signedness +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_up_avalon_rs232.o drivers/src/altera_up_avalon_rs232.c +Creating libucosii_bsp.a... +rm -f -f libucosii_bsp.a +nios2-elf-ar -src libucosii_bsp.a obj/HAL/src/alt_alarm_start.o obj/HAL/src/alt_busy_sleep.o obj/HAL/src/alt_close.o obj/HAL/src/alt_dcache_flush.o obj/HAL/src/alt_dcache_flush_all.o obj/HAL/src/alt_dcache_flush_no_writeback.o obj/HAL/src/alt_dev.o obj/HAL/src/alt_dev_llist_insert.o obj/HAL/src/alt_dma_rxchan_open.o obj/HAL/src/alt_dma_txchan_open.o obj/HAL/src/alt_do_ctors.o obj/HAL/src/alt_do_dtors.o obj/HAL/src/alt_environ.o obj/HAL/src/alt_errno.o obj/HAL/src/alt_exception_entry.o obj/HAL/src/alt_exception_muldiv.o obj/HAL/src/alt_exception_trap.o obj/HAL/src/alt_execve.o obj/HAL/src/alt_exit.o obj/HAL/src/alt_fcntl.o obj/HAL/src/alt_fd_lock.o obj/HAL/src/alt_fd_unlock.o obj/HAL/src/alt_find_dev.o obj/HAL/src/alt_find_file.o obj/HAL/src/alt_flash_dev.o obj/HAL/src/alt_fork.o obj/HAL/src/alt_fs_reg.o obj/HAL/src/alt_fstat.o obj/HAL/src/alt_get_fd.o obj/HAL/src/alt_getchar.o obj/HAL/src/alt_getpid.o obj/HAL/src/alt_gettod.o obj/HAL/src/alt_gmon.o obj/HAL/src/alt_icache_flush.o obj/HAL/src/alt_icache_flush_all.o obj/HAL/src/alt_iic.o obj/HAL/src/alt_iic_isr_register.o obj/HAL/src/alt_instruction_exception_entry.o obj/HAL/src/alt_instruction_exception_register.o obj/HAL/src/alt_io_redirect.o obj/HAL/src/alt_ioctl.o obj/HAL/src/alt_irq_entry.o obj/HAL/src/alt_irq_handler.o obj/HAL/src/alt_irq_register.o obj/HAL/src/alt_irq_vars.o obj/HAL/src/alt_isatty.o obj/HAL/src/alt_kill.o obj/HAL/src/alt_link.o obj/HAL/src/alt_load.o obj/HAL/src/alt_log_macro.o obj/HAL/src/alt_log_printf.o obj/HAL/src/alt_lseek.o obj/HAL/src/alt_main.o obj/HAL/src/alt_mcount.o obj/HAL/src/alt_open.o obj/HAL/src/alt_printf.o obj/HAL/src/alt_putchar.o obj/HAL/src/alt_putstr.o obj/HAL/src/alt_read.o obj/HAL/src/alt_release_fd.o obj/HAL/src/alt_remap_cached.o obj/HAL/src/alt_remap_uncached.o obj/HAL/src/alt_rename.o obj/HAL/src/alt_sbrk.o obj/HAL/src/alt_settod.o obj/HAL/src/alt_software_exception.o obj/HAL/src/alt_stat.o obj/HAL/src/alt_tick.o obj/HAL/src/alt_times.o obj/HAL/src/alt_uncached_free.o obj/HAL/src/alt_uncached_malloc.o obj/HAL/src/alt_unlink.o obj/HAL/src/alt_usleep.o obj/HAL/src/alt_wait.o obj/HAL/src/alt_write.o obj/HAL/src/altera_nios2_qsys_irq.o obj/HAL/src/crt0.o obj/HAL/src/os_cpu_a.o obj/HAL/src/os_cpu_c.o obj/UCOSII/src/alt_env_lock.o obj/UCOSII/src/alt_malloc_lock.o obj/UCOSII/src/os_core.o obj/UCOSII/src/os_dbg.o obj/UCOSII/src/os_flag.o obj/UCOSII/src/os_mbox.o obj/UCOSII/src/os_mem.o obj/UCOSII/src/os_mutex.o obj/UCOSII/src/os_q.o obj/UCOSII/src/os_sem.o obj/UCOSII/src/os_task.o obj/UCOSII/src/os_time.o obj/UCOSII/src/os_tmr.o obj/alt_sys_init.o obj/drivers/src/altera_avalon_jtag_uart_fd.o obj/drivers/src/altera_avalon_jtag_uart_init.o obj/drivers/src/altera_avalon_jtag_uart_ioctl.o obj/drivers/src/altera_avalon_jtag_uart_read.o obj/drivers/src/altera_avalon_jtag_uart_write.o obj/drivers/src/altera_avalon_sysid_qsys.o obj/drivers/src/altera_avalon_timer_sc.o obj/drivers/src/altera_avalon_timer_ts.o obj/drivers/src/altera_avalon_timer_vars.o obj/drivers/src/altera_avalon_uart_fd.o obj/drivers/src/altera_avalon_uart_init.o obj/drivers/src/altera_avalon_uart_ioctl.o obj/drivers/src/altera_avalon_uart_read.o obj/drivers/src/altera_avalon_uart_write.o obj/drivers/src/altera_up_avalon_rs232.o +[BSP build complete] +Info: Compiling MotorHandler.cpp to obj/default/MotorHandler.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/MotorHandler.o MotorHandler.cpp +Info: Compiling main.cpp to obj/default/main.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/main.o main.cpp +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010a0 --timestamp 1394124174 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD" --jdi C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.jdi --sopcinfo C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo +Info: (MCTest.elf) 140 KBytes program size (code + initialized data). +Info: 16236 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling main.cpp to obj/default/main.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/main.o main.cpp +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010a0 --timestamp 1394124174 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD" --jdi C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.jdi --sopcinfo C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo +Info: (MCTest.elf) 140 KBytes program size (code + initialized data). +Info: 16236 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling MotorHandler.cpp to obj/default/MotorHandler.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/MotorHandler.o MotorHandler.cpp +Info: Compiling main.cpp to obj/default/main.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/main.o main.cpp +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010a0 --timestamp 1394124174 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD" --jdi C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.jdi --sopcinfo C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo +Info: (MCTest.elf) 140 KBytes program size (code + initialized data). +Info: 16236 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Clean-only build of configuration Nios II for project MCTest **** + +make clean +[MCTest clean complete] + +**** Build Finished **** + +**** Clean-only build of configuration Nios II for project MCTest_bsp **** + +make clean +[BSP clean complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +Compiling alt_alarm_start.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_alarm_start.o HAL/src/alt_alarm_start.c +Compiling alt_busy_sleep.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_busy_sleep.o HAL/src/alt_busy_sleep.c +Compiling alt_close.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_close.o HAL/src/alt_close.c +Compiling alt_dcache_flush.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dcache_flush.o HAL/src/alt_dcache_flush.c +Compiling alt_dcache_flush_all.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dcache_flush_all.o HAL/src/alt_dcache_flush_all.c +Compiling alt_dcache_flush_no_writeback.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dcache_flush_no_writeback.o HAL/src/alt_dcache_flush_no_writeback.c +Compiling alt_dev.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dev.o HAL/src/alt_dev.c +Compiling alt_dev_llist_insert.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dev_llist_insert.o HAL/src/alt_dev_llist_insert.c +Compiling alt_dma_rxchan_open.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dma_rxchan_open.o HAL/src/alt_dma_rxchan_open.c +Compiling alt_dma_txchan_open.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dma_txchan_open.o HAL/src/alt_dma_txchan_open.c +Compiling alt_do_ctors.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_do_ctors.o HAL/src/alt_do_ctors.c +Compiling alt_do_dtors.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_do_dtors.o HAL/src/alt_do_dtors.c +Compiling alt_environ.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_environ.o HAL/src/alt_environ.c +Compiling alt_errno.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_errno.o HAL/src/alt_errno.c +Compiling alt_exception_entry.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_exception_entry.o HAL/src/alt_exception_entry.S +Compiling alt_exception_muldiv.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_exception_muldiv.o HAL/src/alt_exception_muldiv.S +Compiling alt_exception_trap.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_exception_trap.o HAL/src/alt_exception_trap.S +Compiling alt_execve.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_execve.o HAL/src/alt_execve.c +Compiling alt_exit.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_exit.o HAL/src/alt_exit.c +Compiling alt_fcntl.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fcntl.o HAL/src/alt_fcntl.c +Compiling alt_fd_lock.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fd_lock.o HAL/src/alt_fd_lock.c +Compiling alt_fd_unlock.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fd_unlock.o HAL/src/alt_fd_unlock.c +Compiling alt_find_dev.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_find_dev.o HAL/src/alt_find_dev.c +Compiling alt_find_file.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_find_file.o HAL/src/alt_find_file.c +Compiling alt_flash_dev.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_flash_dev.o HAL/src/alt_flash_dev.c +Compiling alt_fork.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fork.o HAL/src/alt_fork.c +Compiling alt_fs_reg.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fs_reg.o HAL/src/alt_fs_reg.c +Compiling alt_fstat.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fstat.o HAL/src/alt_fstat.c +Compiling alt_get_fd.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_get_fd.o HAL/src/alt_get_fd.c +Compiling alt_getchar.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_getchar.o HAL/src/alt_getchar.c +Compiling alt_getpid.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_getpid.o HAL/src/alt_getpid.c +Compiling alt_gettod.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_gettod.o HAL/src/alt_gettod.c +Compiling alt_gmon.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_gmon.o HAL/src/alt_gmon.c +Compiling alt_icache_flush.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_icache_flush.o HAL/src/alt_icache_flush.c +Compiling alt_icache_flush_all.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_icache_flush_all.o HAL/src/alt_icache_flush_all.c +Compiling alt_iic.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_iic.o HAL/src/alt_iic.c +Compiling alt_iic_isr_register.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_iic_isr_register.o HAL/src/alt_iic_isr_register.c +Compiling alt_instruction_exception_entry.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_instruction_exception_entry.o HAL/src/alt_instruction_exception_entry.c +Compiling alt_instruction_exception_register.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_instruction_exception_register.o HAL/src/alt_instruction_exception_register.c +Compiling alt_io_redirect.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_io_redirect.o HAL/src/alt_io_redirect.c +Compiling alt_ioctl.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_ioctl.o HAL/src/alt_ioctl.c +Compiling alt_irq_entry.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_irq_entry.o HAL/src/alt_irq_entry.S +Compiling alt_irq_handler.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_irq_handler.o HAL/src/alt_irq_handler.c +Compiling alt_irq_register.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_irq_register.o HAL/src/alt_irq_register.c +Compiling alt_irq_vars.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_irq_vars.o HAL/src/alt_irq_vars.c +Compiling alt_isatty.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_isatty.o HAL/src/alt_isatty.c +Compiling alt_kill.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_kill.o HAL/src/alt_kill.c +Compiling alt_link.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_link.o HAL/src/alt_link.c +Compiling alt_load.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_load.o HAL/src/alt_load.c +Compiling alt_log_macro.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_log_macro.o HAL/src/alt_log_macro.S +Compiling alt_log_printf.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_log_printf.o HAL/src/alt_log_printf.c +Compiling alt_lseek.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_lseek.o HAL/src/alt_lseek.c +Compiling alt_main.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_main.o HAL/src/alt_main.c +Compiling alt_mcount.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_mcount.o HAL/src/alt_mcount.S +Compiling alt_open.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_open.o HAL/src/alt_open.c +Compiling alt_printf.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_printf.o HAL/src/alt_printf.c +Compiling alt_putchar.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_putchar.o HAL/src/alt_putchar.c +Compiling alt_putstr.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_putstr.o HAL/src/alt_putstr.c +Compiling alt_read.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_read.o HAL/src/alt_read.c +Compiling alt_release_fd.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_release_fd.o HAL/src/alt_release_fd.c +Compiling alt_remap_cached.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_remap_cached.o HAL/src/alt_remap_cached.c +Compiling alt_remap_uncached.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_remap_uncached.o HAL/src/alt_remap_uncached.c +Compiling alt_rename.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_rename.o HAL/src/alt_rename.c +Compiling alt_sbrk.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_sbrk.o HAL/src/alt_sbrk.c +Compiling alt_settod.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_settod.o HAL/src/alt_settod.c +Compiling alt_software_exception.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_software_exception.o HAL/src/alt_software_exception.S +Compiling alt_stat.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_stat.o HAL/src/alt_stat.c +Compiling alt_tick.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_tick.o HAL/src/alt_tick.c +Compiling alt_times.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_times.o HAL/src/alt_times.c +Compiling alt_uncached_free.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_uncached_free.o HAL/src/alt_uncached_free.c +Compiling alt_uncached_malloc.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_uncached_malloc.o HAL/src/alt_uncached_malloc.c +Compiling alt_unlink.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_unlink.o HAL/src/alt_unlink.c +Compiling alt_usleep.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_usleep.o HAL/src/alt_usleep.c +Compiling alt_wait.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_wait.o HAL/src/alt_wait.c +Compiling alt_write.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_write.o HAL/src/alt_write.c +Compiling altera_nios2_qsys_irq.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/altera_nios2_qsys_irq.o HAL/src/altera_nios2_qsys_irq.c +Compiling crt0.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/crt0.o HAL/src/crt0.S +Compiling os_cpu_a.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/os_cpu_a.o HAL/src/os_cpu_a.S +Compiling os_cpu_c.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/os_cpu_c.o HAL/src/os_cpu_c.c +Compiling alt_env_lock.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/alt_env_lock.o UCOSII/src/alt_env_lock.c +Compiling alt_malloc_lock.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/alt_malloc_lock.o UCOSII/src/alt_malloc_lock.c +Compiling os_core.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_core.o UCOSII/src/os_core.c +Compiling os_dbg.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_dbg.o UCOSII/src/os_dbg.c +Compiling os_flag.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_flag.o UCOSII/src/os_flag.c +Compiling os_mbox.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_mbox.o UCOSII/src/os_mbox.c +Compiling os_mem.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_mem.o UCOSII/src/os_mem.c +Compiling os_mutex.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_mutex.o UCOSII/src/os_mutex.c +Compiling os_q.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_q.o UCOSII/src/os_q.c +Compiling os_sem.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_sem.o UCOSII/src/os_sem.c +Compiling os_task.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_task.o UCOSII/src/os_task.c +Compiling os_time.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_time.o UCOSII/src/os_time.c +Compiling os_tmr.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_tmr.o UCOSII/src/os_tmr.c +Compiling alt_sys_init.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/alt_sys_init.o alt_sys_init.c +Compiling altera_avalon_jtag_uart_fd.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_jtag_uart_fd.o drivers/src/altera_avalon_jtag_uart_fd.c +Compiling altera_avalon_jtag_uart_init.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_jtag_uart_init.o drivers/src/altera_avalon_jtag_uart_init.c +Compiling altera_avalon_jtag_uart_ioctl.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_jtag_uart_ioctl.o drivers/src/altera_avalon_jtag_uart_ioctl.c +Compiling altera_avalon_jtag_uart_read.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_jtag_uart_read.o drivers/src/altera_avalon_jtag_uart_read.c +Compiling altera_avalon_jtag_uart_write.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_jtag_uart_write.o drivers/src/altera_avalon_jtag_uart_write.c +Compiling altera_avalon_sysid_qsys.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_sysid_qsys.o drivers/src/altera_avalon_sysid_qsys.c +Compiling altera_avalon_timer_sc.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_timer_sc.o drivers/src/altera_avalon_timer_sc.c +Compiling altera_avalon_timer_ts.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_timer_ts.o drivers/src/altera_avalon_timer_ts.c +Compiling altera_avalon_timer_vars.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_timer_vars.o drivers/src/altera_avalon_timer_vars.c +Compiling altera_avalon_uart_fd.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_uart_fd.o drivers/src/altera_avalon_uart_fd.c +Compiling altera_avalon_uart_init.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_uart_init.o drivers/src/altera_avalon_uart_init.c +Compiling altera_avalon_uart_ioctl.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_uart_ioctl.o drivers/src/altera_avalon_uart_ioctl.c +Compiling altera_avalon_uart_read.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_uart_read.o drivers/src/altera_avalon_uart_read.c +Compiling altera_avalon_uart_write.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_uart_write.o drivers/src/altera_avalon_uart_write.c +drivers/src/altera_up_avalon_rs232.c: In function 'alt_up_rs232_read_fd': +Compiling altera_up_avalon_rs232.c... +drivers/src/altera_up_avalon_rs232.c:110: warning: pointer targets in passing argument 2 of 'alt_up_rs232_read_data' differ in signedness +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_up_avalon_rs232.o drivers/src/altera_up_avalon_rs232.c +Creating libucosii_bsp.a... +rm -f -f libucosii_bsp.a +nios2-elf-ar -src libucosii_bsp.a obj/HAL/src/alt_alarm_start.o obj/HAL/src/alt_busy_sleep.o obj/HAL/src/alt_close.o obj/HAL/src/alt_dcache_flush.o obj/HAL/src/alt_dcache_flush_all.o obj/HAL/src/alt_dcache_flush_no_writeback.o obj/HAL/src/alt_dev.o obj/HAL/src/alt_dev_llist_insert.o obj/HAL/src/alt_dma_rxchan_open.o obj/HAL/src/alt_dma_txchan_open.o obj/HAL/src/alt_do_ctors.o obj/HAL/src/alt_do_dtors.o obj/HAL/src/alt_environ.o obj/HAL/src/alt_errno.o obj/HAL/src/alt_exception_entry.o obj/HAL/src/alt_exception_muldiv.o obj/HAL/src/alt_exception_trap.o obj/HAL/src/alt_execve.o obj/HAL/src/alt_exit.o obj/HAL/src/alt_fcntl.o obj/HAL/src/alt_fd_lock.o obj/HAL/src/alt_fd_unlock.o obj/HAL/src/alt_find_dev.o obj/HAL/src/alt_find_file.o obj/HAL/src/alt_flash_dev.o obj/HAL/src/alt_fork.o obj/HAL/src/alt_fs_reg.o obj/HAL/src/alt_fstat.o obj/HAL/src/alt_get_fd.o obj/HAL/src/alt_getchar.o obj/HAL/src/alt_getpid.o obj/HAL/src/alt_gettod.o obj/HAL/src/alt_gmon.o obj/HAL/src/alt_icache_flush.o obj/HAL/src/alt_icache_flush_all.o obj/HAL/src/alt_iic.o obj/HAL/src/alt_iic_isr_register.o obj/HAL/src/alt_instruction_exception_entry.o obj/HAL/src/alt_instruction_exception_register.o obj/HAL/src/alt_io_redirect.o obj/HAL/src/alt_ioctl.o obj/HAL/src/alt_irq_entry.o obj/HAL/src/alt_irq_handler.o obj/HAL/src/alt_irq_register.o obj/HAL/src/alt_irq_vars.o obj/HAL/src/alt_isatty.o obj/HAL/src/alt_kill.o obj/HAL/src/alt_link.o obj/HAL/src/alt_load.o obj/HAL/src/alt_log_macro.o obj/HAL/src/alt_log_printf.o obj/HAL/src/alt_lseek.o obj/HAL/src/alt_main.o obj/HAL/src/alt_mcount.o obj/HAL/src/alt_open.o obj/HAL/src/alt_printf.o obj/HAL/src/alt_putchar.o obj/HAL/src/alt_putstr.o obj/HAL/src/alt_read.o obj/HAL/src/alt_release_fd.o obj/HAL/src/alt_remap_cached.o obj/HAL/src/alt_remap_uncached.o obj/HAL/src/alt_rename.o obj/HAL/src/alt_sbrk.o obj/HAL/src/alt_settod.o obj/HAL/src/alt_software_exception.o obj/HAL/src/alt_stat.o obj/HAL/src/alt_tick.o obj/HAL/src/alt_times.o obj/HAL/src/alt_uncached_free.o obj/HAL/src/alt_uncached_malloc.o obj/HAL/src/alt_unlink.o obj/HAL/src/alt_usleep.o obj/HAL/src/alt_wait.o obj/HAL/src/alt_write.o obj/HAL/src/altera_nios2_qsys_irq.o obj/HAL/src/crt0.o obj/HAL/src/os_cpu_a.o obj/HAL/src/os_cpu_c.o obj/UCOSII/src/alt_env_lock.o obj/UCOSII/src/alt_malloc_lock.o obj/UCOSII/src/os_core.o obj/UCOSII/src/os_dbg.o obj/UCOSII/src/os_flag.o obj/UCOSII/src/os_mbox.o obj/UCOSII/src/os_mem.o obj/UCOSII/src/os_mutex.o obj/UCOSII/src/os_q.o obj/UCOSII/src/os_sem.o obj/UCOSII/src/os_task.o obj/UCOSII/src/os_time.o obj/UCOSII/src/os_tmr.o obj/alt_sys_init.o obj/drivers/src/altera_avalon_jtag_uart_fd.o obj/drivers/src/altera_avalon_jtag_uart_init.o obj/drivers/src/altera_avalon_jtag_uart_ioctl.o obj/drivers/src/altera_avalon_jtag_uart_read.o obj/drivers/src/altera_avalon_jtag_uart_write.o obj/drivers/src/altera_avalon_sysid_qsys.o obj/drivers/src/altera_avalon_timer_sc.o obj/drivers/src/altera_avalon_timer_ts.o obj/drivers/src/altera_avalon_timer_vars.o obj/drivers/src/altera_avalon_uart_fd.o obj/drivers/src/altera_avalon_uart_init.o obj/drivers/src/altera_avalon_uart_ioctl.o obj/drivers/src/altera_avalon_uart_read.o obj/drivers/src/altera_avalon_uart_write.o obj/drivers/src/altera_up_avalon_rs232.o +[BSP build complete] +Info: Compiling MotorHandler.cpp to obj/default/MotorHandler.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/MotorHandler.o MotorHandler.cpp +Info: Compiling main.cpp to obj/default/main.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/main.o main.cpp +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010a0 --timestamp 1394124174 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD" --jdi C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.jdi --sopcinfo C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo +Info: (MCTest.elf) 140 KBytes program size (code + initialized data). +Info: 16236 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Clean-only build of configuration Nios II for project MCTest **** + +make clean +[MCTest clean complete] + +**** Build Finished **** + +**** Clean-only build of configuration Nios II for project MCTest_bsp **** + +make clean +[BSP clean complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +Compiling alt_alarm_start.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_alarm_start.o HAL/src/alt_alarm_start.c +Compiling alt_busy_sleep.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_busy_sleep.o HAL/src/alt_busy_sleep.c +Compiling alt_close.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_close.o HAL/src/alt_close.c +Compiling alt_dcache_flush.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dcache_flush.o HAL/src/alt_dcache_flush.c +Compiling alt_dcache_flush_all.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dcache_flush_all.o HAL/src/alt_dcache_flush_all.c +Compiling alt_dcache_flush_no_writeback.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dcache_flush_no_writeback.o HAL/src/alt_dcache_flush_no_writeback.c +Compiling alt_dev.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dev.o HAL/src/alt_dev.c +Compiling alt_dev_llist_insert.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dev_llist_insert.o HAL/src/alt_dev_llist_insert.c +Compiling alt_dma_rxchan_open.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dma_rxchan_open.o HAL/src/alt_dma_rxchan_open.c +Compiling alt_dma_txchan_open.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dma_txchan_open.o HAL/src/alt_dma_txchan_open.c +Compiling alt_do_ctors.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_do_ctors.o HAL/src/alt_do_ctors.c +Compiling alt_do_dtors.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_do_dtors.o HAL/src/alt_do_dtors.c +Compiling alt_environ.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_environ.o HAL/src/alt_environ.c +Compiling alt_errno.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_errno.o HAL/src/alt_errno.c +Compiling alt_exception_entry.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_exception_entry.o HAL/src/alt_exception_entry.S +Compiling alt_exception_muldiv.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_exception_muldiv.o HAL/src/alt_exception_muldiv.S +Compiling alt_exception_trap.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_exception_trap.o HAL/src/alt_exception_trap.S +Compiling alt_execve.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_execve.o HAL/src/alt_execve.c +Compiling alt_exit.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_exit.o HAL/src/alt_exit.c +Compiling alt_fcntl.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fcntl.o HAL/src/alt_fcntl.c +Compiling alt_fd_lock.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fd_lock.o HAL/src/alt_fd_lock.c +Compiling alt_fd_unlock.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fd_unlock.o HAL/src/alt_fd_unlock.c +Compiling alt_find_dev.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_find_dev.o HAL/src/alt_find_dev.c +Compiling alt_find_file.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_find_file.o HAL/src/alt_find_file.c +Compiling alt_flash_dev.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_flash_dev.o HAL/src/alt_flash_dev.c +Compiling alt_fork.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fork.o HAL/src/alt_fork.c +Compiling alt_fs_reg.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fs_reg.o HAL/src/alt_fs_reg.c +Compiling alt_fstat.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fstat.o HAL/src/alt_fstat.c +Compiling alt_get_fd.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_get_fd.o HAL/src/alt_get_fd.c +Compiling alt_getchar.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_getchar.o HAL/src/alt_getchar.c +Compiling alt_getpid.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_getpid.o HAL/src/alt_getpid.c +Compiling alt_gettod.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_gettod.o HAL/src/alt_gettod.c +Compiling alt_gmon.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_gmon.o HAL/src/alt_gmon.c +Compiling alt_icache_flush.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_icache_flush.o HAL/src/alt_icache_flush.c +Compiling alt_icache_flush_all.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_icache_flush_all.o HAL/src/alt_icache_flush_all.c +Compiling alt_iic.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_iic.o HAL/src/alt_iic.c +Compiling alt_iic_isr_register.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_iic_isr_register.o HAL/src/alt_iic_isr_register.c +Compiling alt_instruction_exception_entry.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_instruction_exception_entry.o HAL/src/alt_instruction_exception_entry.c +Compiling alt_instruction_exception_register.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_instruction_exception_register.o HAL/src/alt_instruction_exception_register.c +Compiling alt_io_redirect.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_io_redirect.o HAL/src/alt_io_redirect.c +Compiling alt_ioctl.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_ioctl.o HAL/src/alt_ioctl.c +Compiling alt_irq_entry.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_irq_entry.o HAL/src/alt_irq_entry.S +Compiling alt_irq_handler.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_irq_handler.o HAL/src/alt_irq_handler.c +Compiling alt_irq_register.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_irq_register.o HAL/src/alt_irq_register.c +Compiling alt_irq_vars.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_irq_vars.o HAL/src/alt_irq_vars.c +Compiling alt_isatty.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_isatty.o HAL/src/alt_isatty.c +Compiling alt_kill.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_kill.o HAL/src/alt_kill.c +Compiling alt_link.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_link.o HAL/src/alt_link.c +Compiling alt_load.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_load.o HAL/src/alt_load.c +Compiling alt_log_macro.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_log_macro.o HAL/src/alt_log_macro.S +Compiling alt_log_printf.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_log_printf.o HAL/src/alt_log_printf.c +Compiling alt_lseek.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_lseek.o HAL/src/alt_lseek.c +Compiling alt_main.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_main.o HAL/src/alt_main.c +Compiling alt_mcount.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_mcount.o HAL/src/alt_mcount.S +Compiling alt_open.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_open.o HAL/src/alt_open.c +Compiling alt_printf.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_printf.o HAL/src/alt_printf.c +Compiling alt_putchar.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_putchar.o HAL/src/alt_putchar.c +Compiling alt_putstr.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_putstr.o HAL/src/alt_putstr.c +Compiling alt_read.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_read.o HAL/src/alt_read.c +Compiling alt_release_fd.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_release_fd.o HAL/src/alt_release_fd.c +Compiling alt_remap_cached.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_remap_cached.o HAL/src/alt_remap_cached.c +Compiling alt_remap_uncached.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_remap_uncached.o HAL/src/alt_remap_uncached.c +Compiling alt_rename.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_rename.o HAL/src/alt_rename.c +Compiling alt_sbrk.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_sbrk.o HAL/src/alt_sbrk.c +Compiling alt_settod.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_settod.o HAL/src/alt_settod.c +Compiling alt_software_exception.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_software_exception.o HAL/src/alt_software_exception.S +Compiling alt_stat.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_stat.o HAL/src/alt_stat.c +Compiling alt_tick.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_tick.o HAL/src/alt_tick.c +Compiling alt_times.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_times.o HAL/src/alt_times.c +Compiling alt_uncached_free.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_uncached_free.o HAL/src/alt_uncached_free.c +Compiling alt_uncached_malloc.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_uncached_malloc.o HAL/src/alt_uncached_malloc.c +Compiling alt_unlink.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_unlink.o HAL/src/alt_unlink.c +Compiling alt_usleep.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_usleep.o HAL/src/alt_usleep.c +Compiling alt_wait.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_wait.o HAL/src/alt_wait.c +Compiling alt_write.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_write.o HAL/src/alt_write.c +Compiling altera_nios2_qsys_irq.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/altera_nios2_qsys_irq.o HAL/src/altera_nios2_qsys_irq.c +Compiling crt0.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/crt0.o HAL/src/crt0.S +Compiling os_cpu_a.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/os_cpu_a.o HAL/src/os_cpu_a.S +Compiling os_cpu_c.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/os_cpu_c.o HAL/src/os_cpu_c.c +Compiling alt_env_lock.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/alt_env_lock.o UCOSII/src/alt_env_lock.c +Compiling alt_malloc_lock.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/alt_malloc_lock.o UCOSII/src/alt_malloc_lock.c +Compiling os_core.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_core.o UCOSII/src/os_core.c +Compiling os_dbg.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_dbg.o UCOSII/src/os_dbg.c +Compiling os_flag.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_flag.o UCOSII/src/os_flag.c +Compiling os_mbox.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_mbox.o UCOSII/src/os_mbox.c +Compiling os_mem.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_mem.o UCOSII/src/os_mem.c +Compiling os_mutex.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_mutex.o UCOSII/src/os_mutex.c +Compiling os_q.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_q.o UCOSII/src/os_q.c +Compiling os_sem.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_sem.o UCOSII/src/os_sem.c +Compiling os_task.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_task.o UCOSII/src/os_task.c +Compiling os_time.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_time.o UCOSII/src/os_time.c +Compiling os_tmr.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_tmr.o UCOSII/src/os_tmr.c +Compiling alt_sys_init.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/alt_sys_init.o alt_sys_init.c +Compiling altera_avalon_jtag_uart_fd.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_jtag_uart_fd.o drivers/src/altera_avalon_jtag_uart_fd.c +Compiling altera_avalon_jtag_uart_init.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_jtag_uart_init.o drivers/src/altera_avalon_jtag_uart_init.c +Compiling altera_avalon_jtag_uart_ioctl.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_jtag_uart_ioctl.o drivers/src/altera_avalon_jtag_uart_ioctl.c +Compiling altera_avalon_jtag_uart_read.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_jtag_uart_read.o drivers/src/altera_avalon_jtag_uart_read.c +Compiling altera_avalon_jtag_uart_write.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_jtag_uart_write.o drivers/src/altera_avalon_jtag_uart_write.c +Compiling altera_avalon_sysid_qsys.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_sysid_qsys.o drivers/src/altera_avalon_sysid_qsys.c +Compiling altera_avalon_timer_sc.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_timer_sc.o drivers/src/altera_avalon_timer_sc.c +Compiling altera_avalon_timer_ts.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_timer_ts.o drivers/src/altera_avalon_timer_ts.c +Compiling altera_avalon_timer_vars.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_timer_vars.o drivers/src/altera_avalon_timer_vars.c +Compiling altera_avalon_uart_fd.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_uart_fd.o drivers/src/altera_avalon_uart_fd.c +Compiling altera_avalon_uart_init.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_uart_init.o drivers/src/altera_avalon_uart_init.c +Compiling altera_avalon_uart_ioctl.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_uart_ioctl.o drivers/src/altera_avalon_uart_ioctl.c +Compiling altera_avalon_uart_read.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_uart_read.o drivers/src/altera_avalon_uart_read.c +Compiling altera_avalon_uart_write.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_uart_write.o drivers/src/altera_avalon_uart_write.c +drivers/src/altera_up_avalon_rs232.c: In function 'alt_up_rs232_read_fd': +Compiling altera_up_avalon_rs232.c... +drivers/src/altera_up_avalon_rs232.c:110: warning: pointer targets in passing argument 2 of 'alt_up_rs232_read_data' differ in signedness +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_up_avalon_rs232.o drivers/src/altera_up_avalon_rs232.c +Creating libucosii_bsp.a... +rm -f -f libucosii_bsp.a +nios2-elf-ar -src libucosii_bsp.a obj/HAL/src/alt_alarm_start.o obj/HAL/src/alt_busy_sleep.o obj/HAL/src/alt_close.o obj/HAL/src/alt_dcache_flush.o obj/HAL/src/alt_dcache_flush_all.o obj/HAL/src/alt_dcache_flush_no_writeback.o obj/HAL/src/alt_dev.o obj/HAL/src/alt_dev_llist_insert.o obj/HAL/src/alt_dma_rxchan_open.o obj/HAL/src/alt_dma_txchan_open.o obj/HAL/src/alt_do_ctors.o obj/HAL/src/alt_do_dtors.o obj/HAL/src/alt_environ.o obj/HAL/src/alt_errno.o obj/HAL/src/alt_exception_entry.o obj/HAL/src/alt_exception_muldiv.o obj/HAL/src/alt_exception_trap.o obj/HAL/src/alt_execve.o obj/HAL/src/alt_exit.o obj/HAL/src/alt_fcntl.o obj/HAL/src/alt_fd_lock.o obj/HAL/src/alt_fd_unlock.o obj/HAL/src/alt_find_dev.o obj/HAL/src/alt_find_file.o obj/HAL/src/alt_flash_dev.o obj/HAL/src/alt_fork.o obj/HAL/src/alt_fs_reg.o obj/HAL/src/alt_fstat.o obj/HAL/src/alt_get_fd.o obj/HAL/src/alt_getchar.o obj/HAL/src/alt_getpid.o obj/HAL/src/alt_gettod.o obj/HAL/src/alt_gmon.o obj/HAL/src/alt_icache_flush.o obj/HAL/src/alt_icache_flush_all.o obj/HAL/src/alt_iic.o obj/HAL/src/alt_iic_isr_register.o obj/HAL/src/alt_instruction_exception_entry.o obj/HAL/src/alt_instruction_exception_register.o obj/HAL/src/alt_io_redirect.o obj/HAL/src/alt_ioctl.o obj/HAL/src/alt_irq_entry.o obj/HAL/src/alt_irq_handler.o obj/HAL/src/alt_irq_register.o obj/HAL/src/alt_irq_vars.o obj/HAL/src/alt_isatty.o obj/HAL/src/alt_kill.o obj/HAL/src/alt_link.o obj/HAL/src/alt_load.o obj/HAL/src/alt_log_macro.o obj/HAL/src/alt_log_printf.o obj/HAL/src/alt_lseek.o obj/HAL/src/alt_main.o obj/HAL/src/alt_mcount.o obj/HAL/src/alt_open.o obj/HAL/src/alt_printf.o obj/HAL/src/alt_putchar.o obj/HAL/src/alt_putstr.o obj/HAL/src/alt_read.o obj/HAL/src/alt_release_fd.o obj/HAL/src/alt_remap_cached.o obj/HAL/src/alt_remap_uncached.o obj/HAL/src/alt_rename.o obj/HAL/src/alt_sbrk.o obj/HAL/src/alt_settod.o obj/HAL/src/alt_software_exception.o obj/HAL/src/alt_stat.o obj/HAL/src/alt_tick.o obj/HAL/src/alt_times.o obj/HAL/src/alt_uncached_free.o obj/HAL/src/alt_uncached_malloc.o obj/HAL/src/alt_unlink.o obj/HAL/src/alt_usleep.o obj/HAL/src/alt_wait.o obj/HAL/src/alt_write.o obj/HAL/src/altera_nios2_qsys_irq.o obj/HAL/src/crt0.o obj/HAL/src/os_cpu_a.o obj/HAL/src/os_cpu_c.o obj/UCOSII/src/alt_env_lock.o obj/UCOSII/src/alt_malloc_lock.o obj/UCOSII/src/os_core.o obj/UCOSII/src/os_dbg.o obj/UCOSII/src/os_flag.o obj/UCOSII/src/os_mbox.o obj/UCOSII/src/os_mem.o obj/UCOSII/src/os_mutex.o obj/UCOSII/src/os_q.o obj/UCOSII/src/os_sem.o obj/UCOSII/src/os_task.o obj/UCOSII/src/os_time.o obj/UCOSII/src/os_tmr.o obj/alt_sys_init.o obj/drivers/src/altera_avalon_jtag_uart_fd.o obj/drivers/src/altera_avalon_jtag_uart_init.o obj/drivers/src/altera_avalon_jtag_uart_ioctl.o obj/drivers/src/altera_avalon_jtag_uart_read.o obj/drivers/src/altera_avalon_jtag_uart_write.o obj/drivers/src/altera_avalon_sysid_qsys.o obj/drivers/src/altera_avalon_timer_sc.o obj/drivers/src/altera_avalon_timer_ts.o obj/drivers/src/altera_avalon_timer_vars.o obj/drivers/src/altera_avalon_uart_fd.o obj/drivers/src/altera_avalon_uart_init.o obj/drivers/src/altera_avalon_uart_ioctl.o obj/drivers/src/altera_avalon_uart_read.o obj/drivers/src/altera_avalon_uart_write.o obj/drivers/src/altera_up_avalon_rs232.o +[BSP build complete] +Info: Compiling MotorHandler.cpp to obj/default/MotorHandler.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/MotorHandler.o MotorHandler.cpp +Info: Compiling main.cpp to obj/default/main.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/main.o main.cpp +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010a0 --timestamp 1394124174 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD" --jdi C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.jdi --sopcinfo C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo +Info: (MCTest.elf) 140 KBytes program size (code + initialized data). +Info: 16236 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling main.cpp to obj/default/main.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/main.o main.cpp +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010a0 --timestamp 1394124174 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD" --jdi C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.jdi --sopcinfo C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo +Info: (MCTest.elf) 140 KBytes program size (code + initialized data). +Info: 16236 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling MotorHandler.cpp to obj/default/MotorHandler.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/MotorHandler.o MotorHandler.cpp +Info: Compiling main.cpp to obj/default/main.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/main.o main.cpp +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010a0 --timestamp 1394124174 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD" --jdi C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.jdi --sopcinfo C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo +Info: (MCTest.elf) 140 KBytes program size (code + initialized data). +Info: 16236 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling main.cpp to obj/default/main.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/main.o main.cpp +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010a0 --timestamp 1394124174 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD" --jdi C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.jdi --sopcinfo C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo +Info: (MCTest.elf) 140 KBytes program size (code + initialized data). +Info: 16236 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling main.cpp to obj/default/main.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/main.o main.cpp +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010a0 --timestamp 1394124174 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD" --jdi C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.jdi --sopcinfo C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo +Info: (MCTest.elf) 140 KBytes program size (code + initialized data). +Info: 16236 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling main.cpp to obj/default/main.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/main.o main.cpp +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010a0 --timestamp 1394124174 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD" --jdi C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.jdi --sopcinfo C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo +Info: (MCTest.elf) 140 KBytes program size (code + initialized data). +Info: 16236 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling main.cpp to obj/default/main.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/main.o main.cpp +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010a0 --timestamp 1394124174 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD" --jdi C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.jdi --sopcinfo C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo +Info: (MCTest.elf) 140 KBytes program size (code + initialized data). +Info: 16236 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling main.cpp to obj/default/main.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/main.o main.cpp +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010a0 --timestamp 1394124174 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD" --jdi C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.jdi --sopcinfo C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo +Info: (MCTest.elf) 140 KBytes program size (code + initialized data). +Info: 16236 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Clean-only build of configuration Nios II for project MCTest **** + +make clean +[MCTest clean complete] + +**** Build Finished **** + +**** Clean-only build of configuration Nios II for project MCTest_bsp **** + +make clean +[BSP clean complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +Compiling alt_alarm_start.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_alarm_start.o HAL/src/alt_alarm_start.c +Compiling alt_busy_sleep.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_busy_sleep.o HAL/src/alt_busy_sleep.c +Compiling alt_close.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_close.o HAL/src/alt_close.c +Compiling alt_dcache_flush.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dcache_flush.o HAL/src/alt_dcache_flush.c +Compiling alt_dcache_flush_all.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dcache_flush_all.o HAL/src/alt_dcache_flush_all.c +Compiling alt_dcache_flush_no_writeback.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dcache_flush_no_writeback.o HAL/src/alt_dcache_flush_no_writeback.c +Compiling alt_dev.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dev.o HAL/src/alt_dev.c +Compiling alt_dev_llist_insert.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dev_llist_insert.o HAL/src/alt_dev_llist_insert.c +Compiling alt_dma_rxchan_open.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dma_rxchan_open.o HAL/src/alt_dma_rxchan_open.c +Compiling alt_dma_txchan_open.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dma_txchan_open.o HAL/src/alt_dma_txchan_open.c +Compiling alt_do_ctors.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_do_ctors.o HAL/src/alt_do_ctors.c +Compiling alt_do_dtors.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_do_dtors.o HAL/src/alt_do_dtors.c +Compiling alt_environ.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_environ.o HAL/src/alt_environ.c +Compiling alt_errno.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_errno.o HAL/src/alt_errno.c +Compiling alt_exception_entry.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_exception_entry.o HAL/src/alt_exception_entry.S +Compiling alt_exception_muldiv.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_exception_muldiv.o HAL/src/alt_exception_muldiv.S +Compiling alt_exception_trap.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_exception_trap.o HAL/src/alt_exception_trap.S +Compiling alt_execve.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_execve.o HAL/src/alt_execve.c +Compiling alt_exit.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_exit.o HAL/src/alt_exit.c +Compiling alt_fcntl.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fcntl.o HAL/src/alt_fcntl.c +Compiling alt_fd_lock.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fd_lock.o HAL/src/alt_fd_lock.c +Compiling alt_fd_unlock.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fd_unlock.o HAL/src/alt_fd_unlock.c +Compiling alt_find_dev.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_find_dev.o HAL/src/alt_find_dev.c +Compiling alt_find_file.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_find_file.o HAL/src/alt_find_file.c +Compiling alt_flash_dev.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_flash_dev.o HAL/src/alt_flash_dev.c +Compiling alt_fork.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fork.o HAL/src/alt_fork.c +Compiling alt_fs_reg.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fs_reg.o HAL/src/alt_fs_reg.c +Compiling alt_fstat.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fstat.o HAL/src/alt_fstat.c +Compiling alt_get_fd.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_get_fd.o HAL/src/alt_get_fd.c +Compiling alt_getchar.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_getchar.o HAL/src/alt_getchar.c +Compiling alt_getpid.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_getpid.o HAL/src/alt_getpid.c +Compiling alt_gettod.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_gettod.o HAL/src/alt_gettod.c +Compiling alt_gmon.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_gmon.o HAL/src/alt_gmon.c +Compiling alt_icache_flush.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_icache_flush.o HAL/src/alt_icache_flush.c +Compiling alt_icache_flush_all.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_icache_flush_all.o HAL/src/alt_icache_flush_all.c +Compiling alt_iic.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_iic.o HAL/src/alt_iic.c +Compiling alt_iic_isr_register.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_iic_isr_register.o HAL/src/alt_iic_isr_register.c +Compiling alt_instruction_exception_entry.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_instruction_exception_entry.o HAL/src/alt_instruction_exception_entry.c +Compiling alt_instruction_exception_register.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_instruction_exception_register.o HAL/src/alt_instruction_exception_register.c +Compiling alt_io_redirect.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_io_redirect.o HAL/src/alt_io_redirect.c +Compiling alt_ioctl.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_ioctl.o HAL/src/alt_ioctl.c +Compiling alt_irq_entry.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_irq_entry.o HAL/src/alt_irq_entry.S +Compiling alt_irq_handler.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_irq_handler.o HAL/src/alt_irq_handler.c +Compiling alt_irq_register.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_irq_register.o HAL/src/alt_irq_register.c +Compiling alt_irq_vars.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_irq_vars.o HAL/src/alt_irq_vars.c +Compiling alt_isatty.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_isatty.o HAL/src/alt_isatty.c +Compiling alt_kill.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_kill.o HAL/src/alt_kill.c +Compiling alt_link.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_link.o HAL/src/alt_link.c +Compiling alt_load.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_load.o HAL/src/alt_load.c +Compiling alt_log_macro.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_log_macro.o HAL/src/alt_log_macro.S +Compiling alt_log_printf.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_log_printf.o HAL/src/alt_log_printf.c +Compiling alt_lseek.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_lseek.o HAL/src/alt_lseek.c +Compiling alt_main.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_main.o HAL/src/alt_main.c +Compiling alt_mcount.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_mcount.o HAL/src/alt_mcount.S +Compiling alt_open.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_open.o HAL/src/alt_open.c +Compiling alt_printf.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_printf.o HAL/src/alt_printf.c +Compiling alt_putchar.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_putchar.o HAL/src/alt_putchar.c +Compiling alt_putstr.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_putstr.o HAL/src/alt_putstr.c +Compiling alt_read.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_read.o HAL/src/alt_read.c +Compiling alt_release_fd.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_release_fd.o HAL/src/alt_release_fd.c +Compiling alt_remap_cached.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_remap_cached.o HAL/src/alt_remap_cached.c +Compiling alt_remap_uncached.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_remap_uncached.o HAL/src/alt_remap_uncached.c +Compiling alt_rename.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_rename.o HAL/src/alt_rename.c +Compiling alt_sbrk.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_sbrk.o HAL/src/alt_sbrk.c +Compiling alt_settod.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_settod.o HAL/src/alt_settod.c +Compiling alt_software_exception.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_software_exception.o HAL/src/alt_software_exception.S +Compiling alt_stat.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_stat.o HAL/src/alt_stat.c +Compiling alt_tick.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_tick.o HAL/src/alt_tick.c +Compiling alt_times.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_times.o HAL/src/alt_times.c +Compiling alt_uncached_free.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_uncached_free.o HAL/src/alt_uncached_free.c +Compiling alt_uncached_malloc.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_uncached_malloc.o HAL/src/alt_uncached_malloc.c +Compiling alt_unlink.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_unlink.o HAL/src/alt_unlink.c +Compiling alt_usleep.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_usleep.o HAL/src/alt_usleep.c +Compiling alt_wait.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_wait.o HAL/src/alt_wait.c +Compiling alt_write.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_write.o HAL/src/alt_write.c +Compiling altera_nios2_qsys_irq.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/altera_nios2_qsys_irq.o HAL/src/altera_nios2_qsys_irq.c +Compiling crt0.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/crt0.o HAL/src/crt0.S +Compiling os_cpu_a.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/os_cpu_a.o HAL/src/os_cpu_a.S +Compiling os_cpu_c.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/os_cpu_c.o HAL/src/os_cpu_c.c +Compiling alt_env_lock.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/alt_env_lock.o UCOSII/src/alt_env_lock.c +Compiling alt_malloc_lock.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/alt_malloc_lock.o UCOSII/src/alt_malloc_lock.c +Compiling os_core.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_core.o UCOSII/src/os_core.c +Compiling os_dbg.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_dbg.o UCOSII/src/os_dbg.c +Compiling os_flag.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_flag.o UCOSII/src/os_flag.c +Compiling os_mbox.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_mbox.o UCOSII/src/os_mbox.c +Compiling os_mem.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_mem.o UCOSII/src/os_mem.c +Compiling os_mutex.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_mutex.o UCOSII/src/os_mutex.c +Compiling os_q.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_q.o UCOSII/src/os_q.c +Compiling os_sem.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_sem.o UCOSII/src/os_sem.c +Compiling os_task.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_task.o UCOSII/src/os_task.c +Compiling os_time.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_time.o UCOSII/src/os_time.c +Compiling os_tmr.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_tmr.o UCOSII/src/os_tmr.c +Compiling alt_sys_init.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/alt_sys_init.o alt_sys_init.c +Compiling altera_avalon_jtag_uart_fd.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_jtag_uart_fd.o drivers/src/altera_avalon_jtag_uart_fd.c +Compiling altera_avalon_jtag_uart_init.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_jtag_uart_init.o drivers/src/altera_avalon_jtag_uart_init.c +Compiling altera_avalon_jtag_uart_ioctl.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_jtag_uart_ioctl.o drivers/src/altera_avalon_jtag_uart_ioctl.c +Compiling altera_avalon_jtag_uart_read.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_jtag_uart_read.o drivers/src/altera_avalon_jtag_uart_read.c +Compiling altera_avalon_jtag_uart_write.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_jtag_uart_write.o drivers/src/altera_avalon_jtag_uart_write.c +Compiling altera_avalon_sysid_qsys.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_sysid_qsys.o drivers/src/altera_avalon_sysid_qsys.c +Compiling altera_avalon_timer_sc.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_timer_sc.o drivers/src/altera_avalon_timer_sc.c +Compiling altera_avalon_timer_ts.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_timer_ts.o drivers/src/altera_avalon_timer_ts.c +Compiling altera_avalon_timer_vars.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_timer_vars.o drivers/src/altera_avalon_timer_vars.c +Compiling altera_avalon_uart_fd.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_uart_fd.o drivers/src/altera_avalon_uart_fd.c +Compiling altera_avalon_uart_init.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_uart_init.o drivers/src/altera_avalon_uart_init.c +Compiling altera_avalon_uart_ioctl.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_uart_ioctl.o drivers/src/altera_avalon_uart_ioctl.c +Compiling altera_avalon_uart_read.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_uart_read.o drivers/src/altera_avalon_uart_read.c +Compiling altera_avalon_uart_write.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_uart_write.o drivers/src/altera_avalon_uart_write.c +Compiling altera_up_avalon_rs232.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_up_avalon_rs232.o drivers/src/altera_up_avalon_rs232.c +drivers/src/altera_up_avalon_rs232.c: In function 'alt_up_rs232_read_fd': +drivers/src/altera_up_avalon_rs232.c:110: warning: pointer targets in passing argument 2 of 'alt_up_rs232_read_data' differ in signedness +Creating libucosii_bsp.a... +rm -f -f libucosii_bsp.a +nios2-elf-ar -src libucosii_bsp.a obj/HAL/src/alt_alarm_start.o obj/HAL/src/alt_busy_sleep.o obj/HAL/src/alt_close.o obj/HAL/src/alt_dcache_flush.o obj/HAL/src/alt_dcache_flush_all.o obj/HAL/src/alt_dcache_flush_no_writeback.o obj/HAL/src/alt_dev.o obj/HAL/src/alt_dev_llist_insert.o obj/HAL/src/alt_dma_rxchan_open.o obj/HAL/src/alt_dma_txchan_open.o obj/HAL/src/alt_do_ctors.o obj/HAL/src/alt_do_dtors.o obj/HAL/src/alt_environ.o obj/HAL/src/alt_errno.o obj/HAL/src/alt_exception_entry.o obj/HAL/src/alt_exception_muldiv.o obj/HAL/src/alt_exception_trap.o obj/HAL/src/alt_execve.o obj/HAL/src/alt_exit.o obj/HAL/src/alt_fcntl.o obj/HAL/src/alt_fd_lock.o obj/HAL/src/alt_fd_unlock.o obj/HAL/src/alt_find_dev.o obj/HAL/src/alt_find_file.o obj/HAL/src/alt_flash_dev.o obj/HAL/src/alt_fork.o obj/HAL/src/alt_fs_reg.o obj/HAL/src/alt_fstat.o obj/HAL/src/alt_get_fd.o obj/HAL/src/alt_getchar.o obj/HAL/src/alt_getpid.o obj/HAL/src/alt_gettod.o obj/HAL/src/alt_gmon.o obj/HAL/src/alt_icache_flush.o obj/HAL/src/alt_icache_flush_all.o obj/HAL/src/alt_iic.o obj/HAL/src/alt_iic_isr_register.o obj/HAL/src/alt_instruction_exception_entry.o obj/HAL/src/alt_instruction_exception_register.o obj/HAL/src/alt_io_redirect.o obj/HAL/src/alt_ioctl.o obj/HAL/src/alt_irq_entry.o obj/HAL/src/alt_irq_handler.o obj/HAL/src/alt_irq_register.o obj/HAL/src/alt_irq_vars.o obj/HAL/src/alt_isatty.o obj/HAL/src/alt_kill.o obj/HAL/src/alt_link.o obj/HAL/src/alt_load.o obj/HAL/src/alt_log_macro.o obj/HAL/src/alt_log_printf.o obj/HAL/src/alt_lseek.o obj/HAL/src/alt_main.o obj/HAL/src/alt_mcount.o obj/HAL/src/alt_open.o obj/HAL/src/alt_printf.o obj/HAL/src/alt_putchar.o obj/HAL/src/alt_putstr.o obj/HAL/src/alt_read.o obj/HAL/src/alt_release_fd.o obj/HAL/src/alt_remap_cached.o obj/HAL/src/alt_remap_uncached.o obj/HAL/src/alt_rename.o obj/HAL/src/alt_sbrk.o obj/HAL/src/alt_settod.o obj/HAL/src/alt_software_exception.o obj/HAL/src/alt_stat.o obj/HAL/src/alt_tick.o obj/HAL/src/alt_times.o obj/HAL/src/alt_uncached_free.o obj/HAL/src/alt_uncached_malloc.o obj/HAL/src/alt_unlink.o obj/HAL/src/alt_usleep.o obj/HAL/src/alt_wait.o obj/HAL/src/alt_write.o obj/HAL/src/altera_nios2_qsys_irq.o obj/HAL/src/crt0.o obj/HAL/src/os_cpu_a.o obj/HAL/src/os_cpu_c.o obj/UCOSII/src/alt_env_lock.o obj/UCOSII/src/alt_malloc_lock.o obj/UCOSII/src/os_core.o obj/UCOSII/src/os_dbg.o obj/UCOSII/src/os_flag.o obj/UCOSII/src/os_mbox.o obj/UCOSII/src/os_mem.o obj/UCOSII/src/os_mutex.o obj/UCOSII/src/os_q.o obj/UCOSII/src/os_sem.o obj/UCOSII/src/os_task.o obj/UCOSII/src/os_time.o obj/UCOSII/src/os_tmr.o obj/alt_sys_init.o obj/drivers/src/altera_avalon_jtag_uart_fd.o obj/drivers/src/altera_avalon_jtag_uart_init.o obj/drivers/src/altera_avalon_jtag_uart_ioctl.o obj/drivers/src/altera_avalon_jtag_uart_read.o obj/drivers/src/altera_avalon_jtag_uart_write.o obj/drivers/src/altera_avalon_sysid_qsys.o obj/drivers/src/altera_avalon_timer_sc.o obj/drivers/src/altera_avalon_timer_ts.o obj/drivers/src/altera_avalon_timer_vars.o obj/drivers/src/altera_avalon_uart_fd.o obj/drivers/src/altera_avalon_uart_init.o obj/drivers/src/altera_avalon_uart_ioctl.o obj/drivers/src/altera_avalon_uart_read.o obj/drivers/src/altera_avalon_uart_write.o obj/drivers/src/altera_up_avalon_rs232.o +[BSP build complete] +Info: Compiling MotorHandler.cpp to obj/default/MotorHandler.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/MotorHandler.o MotorHandler.cpp +Info: Compiling main.cpp to obj/default/main.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/main.o main.cpp +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010a0 --timestamp 1394124174 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/NewRepARCap/MCTEST/DE0-nano-HD" --jdi C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.jdi --sopcinfo C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo +Info: (MCTest.elf) 140 KBytes program size (code + initialized data). +Info: 16236 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling main.cpp to obj/default/main.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/main.o main.cpp +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010a0 --timestamp 1394124174 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/NewRepARCap/MCTEST/DE0-nano-HD" --jdi C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.jdi --sopcinfo C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo +Info: (MCTest.elf) 140 KBytes program size (code + initialized data). +Info: 16236 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling MotorHandler.cpp to obj/default/MotorHandler.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/MotorHandler.o MotorHandler.cpp +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010a0 --timestamp 1394124174 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/NewRepARCap/MCTEST/DE0-nano-HD" --jdi C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.jdi --sopcinfo C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo +Info: (MCTest.elf) 140 KBytes program size (code + initialized data). +Info: 16236 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling main.cpp to obj/default/main.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/main.o main.cpp +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010a0 --timestamp 1394124174 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/NewRepARCap/MCTEST/DE0-nano-HD" --jdi C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.jdi --sopcinfo C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo +Info: (MCTest.elf) 140 KBytes program size (code + initialized data). +Info: 16236 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling MotorHandler.cpp to obj/default/MotorHandler.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/MotorHandler.o MotorHandler.cpp +MotorHandler.cpp:102: error: variable or field 'move' declared void +MotorHandler.cpp:102: error: 'int MotorHandler::move' is not a static member of 'class MotorHandler' +MotorHandler.cpp:102: error: 'MotorDirection' was not declared in this scope +MotorHandler.cpp:102: error: 'Speed' was not declared in this scope +MotorHandler.cpp:102: error: 'Description' was not declared in this scope +MotorHandler.cpp:102: error: initializer expression list treated as compound expression +MotorHandler.cpp:102: error: expected ',' or ';' before '{' token +make: *** [obj/default/MotorHandler.o] Error 1 + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling MotorHandler.cpp to obj/default/MotorHandler.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/MotorHandler.o MotorHandler.cpp +MotorHandler.h:64: error: 'void MotorHandler::move(char, char, char*)' cannot be overloaded +MotorHandler.h:37: error: with 'void MotorHandler::move(char, char, char*)' +MotorHandler.cpp: In member function 'void MotorHandler::forward()': +MotorHandler.cpp:65: error: 'MOTOR_BOTH_FORWARD' was not declared in this scope +MotorHandler.cpp: In member function 'void MotorHandler::backward()': +MotorHandler.cpp:73: error: 'MOTOR_BOTH_BACKWARD' was not declared in this scope +MotorHandler.cpp: In member function 'void MotorHandler::left()': +MotorHandler.cpp:81: error: 'MOTOR_MOTOR1_FORWARD' was not declared in this scope +MotorHandler.cpp: In member function 'void MotorHandler::right()': +MotorHandler.cpp:88: error: 'MOTOR_MOTOR2_FORWARD' was not declared in this scope +MotorHandler.cpp: In member function 'void MotorHandler::stop()': +MotorHandler.cpp:95: error: 'MOTOR_MOTOR1_FORWARD' was not declared in this scope +MotorHandler.cpp:96: error: 'MOTOR_MOTOR2_FORWARD' was not declared in this scope +make: *** [obj/default/MotorHandler.o] Error 1 + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling MotorHandler.cpp to obj/default/MotorHandler.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/MotorHandler.o MotorHandler.cpp +MotorHandler.h:64: error: 'void MotorHandler::move(char, char, char*)' cannot be overloaded +MotorHandler.h:37: error: with 'void MotorHandler::move(char, char, char*)' +make: *** [obj/default/MotorHandler.o] Error 1 + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling MotorHandler.cpp to obj/default/MotorHandler.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/MotorHandler.o MotorHandler.cpp +MotorHandler.h:64: error: 'void MotorHandler::move(char, char, char*)' cannot be overloaded +MotorHandler.h:37: error: with 'void MotorHandler::move(char, char, char*)' +make: *** [obj/default/MotorHandler.o] Error 1 + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling MotorHandler.cpp to obj/default/MotorHandler.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/MotorHandler.o MotorHandler.cpp +Info: Compiling main.cpp to obj/default/main.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/main.o main.cpp +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/main.o -lm +obj/default/main.o: In function `mc_task(void*)': +C:\Users\gongal\NewRepARCap\MCTEST\DE0-nano-HD\Software\MCTest/main.cpp:77: undefined reference to `MotorHandler::forward()' +C:\Users\gongal\NewRepARCap\MCTEST\DE0-nano-HD\Software\MCTest/main.cpp:79: undefined reference to `MotorHandler::stop()' +C:\Users\gongal\NewRepARCap\MCTEST\DE0-nano-HD\Software\MCTest/main.cpp:85: undefined reference to `MotorHandler::backward()' +C:\Users\gongal\NewRepARCap\MCTEST\DE0-nano-HD\Software\MCTest/main.cpp:87: undefined reference to `MotorHandler::stop()' +collect2: ld returned 1 exit status +make: *** [MCTest.elf] Error 1 + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling main.cpp to obj/default/main.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/main.o main.cpp +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/main.o -lm +obj/default/main.o: In function `mc_task(void*)': +C:\Users\gongal\NewRepARCap\MCTEST\DE0-nano-HD\Software\MCTest/main.cpp:79: undefined reference to `MotorHandler::stop()' +collect2: ld returned 1 exit status +make: *** [MCTest.elf] Error 1 + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling main.cpp to obj/default/main.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/main.o main.cpp +main.cpp:79:16: error: invalid suffix "x05" on integer constant +make: *** [obj/default/main.o] Error 1 + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling main.cpp to obj/default/main.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/main.o main.cpp +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010a0 --timestamp 1394124174 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/NewRepARCap/MCTEST/DE0-nano-HD" --jdi C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.jdi --sopcinfo C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo +Info: (MCTest.elf) 139 KBytes program size (code + initialized data). +Info: 16237 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling MotorHandler.cpp to obj/default/MotorHandler.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/MotorHandler.o MotorHandler.cpp +MotorHandler.h:38: error: 'string' has not been declared +MotorHandler.h:38: error: 'string' has not been declared +MotorHandler.cpp: In member function 'Status MotorHandler::init()': +MotorHandler.cpp:34: error: 'reset' was not declared in this scope +MotorHandler.cpp: At global scope: +MotorHandler.cpp:45: error: no 'void MotorHandler::configure()' member function declared in class 'MotorHandler' +MotorHandler.cpp:97: error: no 'void MotorHandler::reset()' member function declared in class 'MotorHandler' +make: *** [obj/default/MotorHandler.o] Error 1 + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Clean-only build of configuration Nios II for project MCTest **** + +make clean +[MCTest clean complete] + +**** Build Finished **** + +**** Clean-only build of configuration Nios II for project MCTest_bsp **** + +make clean +[BSP clean complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +Compiling alt_alarm_start.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_alarm_start.o HAL/src/alt_alarm_start.c +Compiling alt_busy_sleep.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_busy_sleep.o HAL/src/alt_busy_sleep.c +Compiling alt_close.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_close.o HAL/src/alt_close.c +Compiling alt_dcache_flush.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dcache_flush.o HAL/src/alt_dcache_flush.c +Compiling alt_dcache_flush_all.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dcache_flush_all.o HAL/src/alt_dcache_flush_all.c +Compiling alt_dcache_flush_no_writeback.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dcache_flush_no_writeback.o HAL/src/alt_dcache_flush_no_writeback.c +Compiling alt_dev.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dev.o HAL/src/alt_dev.c +Compiling alt_dev_llist_insert.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dev_llist_insert.o HAL/src/alt_dev_llist_insert.c +Compiling alt_dma_rxchan_open.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dma_rxchan_open.o HAL/src/alt_dma_rxchan_open.c +Compiling alt_dma_txchan_open.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dma_txchan_open.o HAL/src/alt_dma_txchan_open.c +Compiling alt_do_ctors.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_do_ctors.o HAL/src/alt_do_ctors.c +Compiling alt_do_dtors.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_do_dtors.o HAL/src/alt_do_dtors.c +Compiling alt_environ.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_environ.o HAL/src/alt_environ.c +Compiling alt_errno.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_errno.o HAL/src/alt_errno.c +Compiling alt_exception_entry.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_exception_entry.o HAL/src/alt_exception_entry.S +Compiling alt_exception_muldiv.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_exception_muldiv.o HAL/src/alt_exception_muldiv.S +Compiling alt_exception_trap.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_exception_trap.o HAL/src/alt_exception_trap.S +Compiling alt_execve.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_execve.o HAL/src/alt_execve.c +Compiling alt_exit.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_exit.o HAL/src/alt_exit.c +Compiling alt_fcntl.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fcntl.o HAL/src/alt_fcntl.c +Compiling alt_fd_lock.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fd_lock.o HAL/src/alt_fd_lock.c +Compiling alt_fd_unlock.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fd_unlock.o HAL/src/alt_fd_unlock.c +Compiling alt_find_dev.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_find_dev.o HAL/src/alt_find_dev.c +Compiling alt_find_file.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_find_file.o HAL/src/alt_find_file.c +Compiling alt_flash_dev.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_flash_dev.o HAL/src/alt_flash_dev.c +Compiling alt_fork.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fork.o HAL/src/alt_fork.c +Compiling alt_fs_reg.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fs_reg.o HAL/src/alt_fs_reg.c +Compiling alt_fstat.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fstat.o HAL/src/alt_fstat.c +Compiling alt_get_fd.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_get_fd.o HAL/src/alt_get_fd.c +Compiling alt_getchar.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_getchar.o HAL/src/alt_getchar.c +Compiling alt_getpid.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_getpid.o HAL/src/alt_getpid.c +Compiling alt_gettod.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_gettod.o HAL/src/alt_gettod.c +Compiling alt_gmon.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_gmon.o HAL/src/alt_gmon.c +Compiling alt_icache_flush.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_icache_flush.o HAL/src/alt_icache_flush.c +Compiling alt_icache_flush_all.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_icache_flush_all.o HAL/src/alt_icache_flush_all.c +Compiling alt_iic.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_iic.o HAL/src/alt_iic.c +Compiling alt_iic_isr_register.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_iic_isr_register.o HAL/src/alt_iic_isr_register.c +Compiling alt_instruction_exception_entry.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_instruction_exception_entry.o HAL/src/alt_instruction_exception_entry.c +Compiling alt_instruction_exception_register.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_instruction_exception_register.o HAL/src/alt_instruction_exception_register.c +Compiling alt_io_redirect.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_io_redirect.o HAL/src/alt_io_redirect.c +Compiling alt_ioctl.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_ioctl.o HAL/src/alt_ioctl.c +Compiling alt_irq_entry.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_irq_entry.o HAL/src/alt_irq_entry.S +Compiling alt_irq_handler.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_irq_handler.o HAL/src/alt_irq_handler.c +Compiling alt_irq_register.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_irq_register.o HAL/src/alt_irq_register.c +Compiling alt_irq_vars.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_irq_vars.o HAL/src/alt_irq_vars.c +Compiling alt_isatty.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_isatty.o HAL/src/alt_isatty.c +Compiling alt_kill.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_kill.o HAL/src/alt_kill.c +Compiling alt_link.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_link.o HAL/src/alt_link.c +Compiling alt_load.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_load.o HAL/src/alt_load.c +Compiling alt_log_macro.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_log_macro.o HAL/src/alt_log_macro.S +Compiling alt_log_printf.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_log_printf.o HAL/src/alt_log_printf.c +Compiling alt_lseek.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_lseek.o HAL/src/alt_lseek.c +Compiling alt_main.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_main.o HAL/src/alt_main.c +Compiling alt_mcount.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_mcount.o HAL/src/alt_mcount.S +Compiling alt_open.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_open.o HAL/src/alt_open.c +Compiling alt_printf.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_printf.o HAL/src/alt_printf.c +Compiling alt_putchar.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_putchar.o HAL/src/alt_putchar.c +Compiling alt_putstr.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_putstr.o HAL/src/alt_putstr.c +Compiling alt_read.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_read.o HAL/src/alt_read.c +Compiling alt_release_fd.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_release_fd.o HAL/src/alt_release_fd.c +Compiling alt_remap_cached.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_remap_cached.o HAL/src/alt_remap_cached.c +Compiling alt_remap_uncached.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_remap_uncached.o HAL/src/alt_remap_uncached.c +Compiling alt_rename.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_rename.o HAL/src/alt_rename.c +Compiling alt_sbrk.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_sbrk.o HAL/src/alt_sbrk.c +Compiling alt_settod.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_settod.o HAL/src/alt_settod.c +Compiling alt_software_exception.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_software_exception.o HAL/src/alt_software_exception.S +Compiling alt_stat.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_stat.o HAL/src/alt_stat.c +Compiling alt_tick.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_tick.o HAL/src/alt_tick.c +Compiling alt_times.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_times.o HAL/src/alt_times.c +Compiling alt_uncached_free.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_uncached_free.o HAL/src/alt_uncached_free.c +Compiling alt_uncached_malloc.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_uncached_malloc.o HAL/src/alt_uncached_malloc.c +Compiling alt_unlink.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_unlink.o HAL/src/alt_unlink.c +Compiling alt_usleep.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_usleep.o HAL/src/alt_usleep.c +Compiling alt_wait.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_wait.o HAL/src/alt_wait.c +Compiling alt_write.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_write.o HAL/src/alt_write.c +Compiling altera_nios2_qsys_irq.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/altera_nios2_qsys_irq.o HAL/src/altera_nios2_qsys_irq.c +Compiling crt0.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/crt0.o HAL/src/crt0.S +Compiling os_cpu_a.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/os_cpu_a.o HAL/src/os_cpu_a.S +Compiling os_cpu_c.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/os_cpu_c.o HAL/src/os_cpu_c.c +Compiling alt_env_lock.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/alt_env_lock.o UCOSII/src/alt_env_lock.c +Compiling alt_malloc_lock.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/alt_malloc_lock.o UCOSII/src/alt_malloc_lock.c +Compiling os_core.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_core.o UCOSII/src/os_core.c +Compiling os_dbg.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_dbg.o UCOSII/src/os_dbg.c +Compiling os_flag.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_flag.o UCOSII/src/os_flag.c +Compiling os_mbox.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_mbox.o UCOSII/src/os_mbox.c +Compiling os_mem.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_mem.o UCOSII/src/os_mem.c +Compiling os_mutex.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_mutex.o UCOSII/src/os_mutex.c +Compiling os_q.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_q.o UCOSII/src/os_q.c +Compiling os_sem.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_sem.o UCOSII/src/os_sem.c +Compiling os_task.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_task.o UCOSII/src/os_task.c +Compiling os_time.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_time.o UCOSII/src/os_time.c +Compiling os_tmr.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_tmr.o UCOSII/src/os_tmr.c +Compiling alt_sys_init.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/alt_sys_init.o alt_sys_init.c +Compiling altera_avalon_jtag_uart_fd.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_jtag_uart_fd.o drivers/src/altera_avalon_jtag_uart_fd.c +Compiling altera_avalon_jtag_uart_init.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_jtag_uart_init.o drivers/src/altera_avalon_jtag_uart_init.c +Compiling altera_avalon_jtag_uart_ioctl.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_jtag_uart_ioctl.o drivers/src/altera_avalon_jtag_uart_ioctl.c +Compiling altera_avalon_jtag_uart_read.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_jtag_uart_read.o drivers/src/altera_avalon_jtag_uart_read.c +Compiling altera_avalon_jtag_uart_write.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_jtag_uart_write.o drivers/src/altera_avalon_jtag_uart_write.c +Compiling altera_avalon_sysid_qsys.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_sysid_qsys.o drivers/src/altera_avalon_sysid_qsys.c +Compiling altera_avalon_timer_sc.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_timer_sc.o drivers/src/altera_avalon_timer_sc.c +Compiling altera_avalon_timer_ts.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_timer_ts.o drivers/src/altera_avalon_timer_ts.c +Compiling altera_avalon_timer_vars.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_timer_vars.o drivers/src/altera_avalon_timer_vars.c +Compiling altera_avalon_uart_fd.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_uart_fd.o drivers/src/altera_avalon_uart_fd.c +Compiling altera_avalon_uart_init.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_uart_init.o drivers/src/altera_avalon_uart_init.c +Compiling altera_avalon_uart_ioctl.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_uart_ioctl.o drivers/src/altera_avalon_uart_ioctl.c +Compiling altera_avalon_uart_read.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_uart_read.o drivers/src/altera_avalon_uart_read.c +Compiling altera_avalon_uart_write.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_uart_write.o drivers/src/altera_avalon_uart_write.c +Compiling altera_up_avalon_rs232.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_up_avalon_rs232.o drivers/src/altera_up_avalon_rs232.c +drivers/src/altera_up_avalon_rs232.c: In function 'alt_up_rs232_read_fd': +Creating libucosii_bsp.a... +drivers/src/altera_up_avalon_rs232.c:110: warning: pointer targets in passing argument 2 of 'alt_up_rs232_read_data' differ in signedness +rm -f -f libucosii_bsp.a +nios2-elf-ar -src libucosii_bsp.a obj/HAL/src/alt_alarm_start.o obj/HAL/src/alt_busy_sleep.o obj/HAL/src/alt_close.o obj/HAL/src/alt_dcache_flush.o obj/HAL/src/alt_dcache_flush_all.o obj/HAL/src/alt_dcache_flush_no_writeback.o obj/HAL/src/alt_dev.o obj/HAL/src/alt_dev_llist_insert.o obj/HAL/src/alt_dma_rxchan_open.o obj/HAL/src/alt_dma_txchan_open.o obj/HAL/src/alt_do_ctors.o obj/HAL/src/alt_do_dtors.o obj/HAL/src/alt_environ.o obj/HAL/src/alt_errno.o obj/HAL/src/alt_exception_entry.o obj/HAL/src/alt_exception_muldiv.o obj/HAL/src/alt_exception_trap.o obj/HAL/src/alt_execve.o obj/HAL/src/alt_exit.o obj/HAL/src/alt_fcntl.o obj/HAL/src/alt_fd_lock.o obj/HAL/src/alt_fd_unlock.o obj/HAL/src/alt_find_dev.o obj/HAL/src/alt_find_file.o obj/HAL/src/alt_flash_dev.o obj/HAL/src/alt_fork.o obj/HAL/src/alt_fs_reg.o obj/HAL/src/alt_fstat.o obj/HAL/src/alt_get_fd.o obj/HAL/src/alt_getchar.o obj/HAL/src/alt_getpid.o obj/HAL/src/alt_gettod.o obj/HAL/src/alt_gmon.o obj/HAL/src/alt_icache_flush.o obj/HAL/src/alt_icache_flush_all.o obj/HAL/src/alt_iic.o obj/HAL/src/alt_iic_isr_register.o obj/HAL/src/alt_instruction_exception_entry.o obj/HAL/src/alt_instruction_exception_register.o obj/HAL/src/alt_io_redirect.o obj/HAL/src/alt_ioctl.o obj/HAL/src/alt_irq_entry.o obj/HAL/src/alt_irq_handler.o obj/HAL/src/alt_irq_register.o obj/HAL/src/alt_irq_vars.o obj/HAL/src/alt_isatty.o obj/HAL/src/alt_kill.o obj/HAL/src/alt_link.o obj/HAL/src/alt_load.o obj/HAL/src/alt_log_macro.o obj/HAL/src/alt_log_printf.o obj/HAL/src/alt_lseek.o obj/HAL/src/alt_main.o obj/HAL/src/alt_mcount.o obj/HAL/src/alt_open.o obj/HAL/src/alt_printf.o obj/HAL/src/alt_putchar.o obj/HAL/src/alt_putstr.o obj/HAL/src/alt_read.o obj/HAL/src/alt_release_fd.o obj/HAL/src/alt_remap_cached.o obj/HAL/src/alt_remap_uncached.o obj/HAL/src/alt_rename.o obj/HAL/src/alt_sbrk.o obj/HAL/src/alt_settod.o obj/HAL/src/alt_software_exception.o obj/HAL/src/alt_stat.o obj/HAL/src/alt_tick.o obj/HAL/src/alt_times.o obj/HAL/src/alt_uncached_free.o obj/HAL/src/alt_uncached_malloc.o obj/HAL/src/alt_unlink.o obj/HAL/src/alt_usleep.o obj/HAL/src/alt_wait.o obj/HAL/src/alt_write.o obj/HAL/src/altera_nios2_qsys_irq.o obj/HAL/src/crt0.o obj/HAL/src/os_cpu_a.o obj/HAL/src/os_cpu_c.o obj/UCOSII/src/alt_env_lock.o obj/UCOSII/src/alt_malloc_lock.o obj/UCOSII/src/os_core.o obj/UCOSII/src/os_dbg.o obj/UCOSII/src/os_flag.o obj/UCOSII/src/os_mbox.o obj/UCOSII/src/os_mem.o obj/UCOSII/src/os_mutex.o obj/UCOSII/src/os_q.o obj/UCOSII/src/os_sem.o obj/UCOSII/src/os_task.o obj/UCOSII/src/os_time.o obj/UCOSII/src/os_tmr.o obj/alt_sys_init.o obj/drivers/src/altera_avalon_jtag_uart_fd.o obj/drivers/src/altera_avalon_jtag_uart_init.o obj/drivers/src/altera_avalon_jtag_uart_ioctl.o obj/drivers/src/altera_avalon_jtag_uart_read.o obj/drivers/src/altera_avalon_jtag_uart_write.o obj/drivers/src/altera_avalon_sysid_qsys.o obj/drivers/src/altera_avalon_timer_sc.o obj/drivers/src/altera_avalon_timer_ts.o obj/drivers/src/altera_avalon_timer_vars.o obj/drivers/src/altera_avalon_uart_fd.o obj/drivers/src/altera_avalon_uart_init.o obj/drivers/src/altera_avalon_uart_ioctl.o obj/drivers/src/altera_avalon_uart_read.o obj/drivers/src/altera_avalon_uart_write.o obj/drivers/src/altera_up_avalon_rs232.o +[BSP build complete] +Info: Compiling MotorHandler.cpp to obj/default/MotorHandler.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/MotorHandler.o MotorHandler.cpp +MotorHandler.h:38: error: 'string' has not been declared +MotorHandler.h:38: error: 'string' has not been declared +MotorHandler.cpp: In member function 'Status MotorHandler::init()': +MotorHandler.cpp:34: error: 'reset' was not declared in this scope +MotorHandler.cpp: At global scope: +MotorHandler.cpp:45: error: no 'void MotorHandler::configure()' member function declared in class 'MotorHandler' +MotorHandler.cpp:97: error: no 'void MotorHandler::reset()' member function declared in class 'MotorHandler' +make: *** [obj/default/MotorHandler.o] Error 1 + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling MotorHandler.cpp to obj/default/MotorHandler.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/MotorHandler.o MotorHandler.cpp +MotorHandler.cpp: In member function 'Status MotorHandler::init()': +MotorHandler.cpp:34: error: 'reset' was not declared in this scope +MotorHandler.cpp: At global scope: +MotorHandler.cpp:45: error: no 'void MotorHandler::configure()' member function declared in class 'MotorHandler' +MotorHandler.cpp:97: error: no 'void MotorHandler::reset()' member function declared in class 'MotorHandler' +make: *** [obj/default/MotorHandler.o] Error 1 + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling MotorHandler.cpp to obj/default/MotorHandler.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/MotorHandler.o MotorHandler.cpp +Info: Compiling main.cpp to obj/default/main.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/main.o main.cpp +MotorHandler.h: In function 'void mc_task(void*)': +MotorHandler.h:53: error: 'void MotorHandler::move(char, char, char*)' is private +main.cpp:77: error: within this context +MotorHandler.h:53: error: 'void MotorHandler::move(char, char, char*)' is private +main.cpp:79: error: within this context +make: *** [obj/default/main.o] Error 1 + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling main.cpp to obj/default/main.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/main.o main.cpp +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010a0 --timestamp 1394124174 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/NewRepARCap/MCTEST/DE0-nano-HD" --jdi C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.jdi --sopcinfo C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo +Info: (MCTest.elf) 139 KBytes program size (code + initialized data). +Info: 16237 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling MotorHandler.cpp to obj/default/MotorHandler.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/MotorHandler.o MotorHandler.cpp +MotorHandler.cpp: In member function 'void MotorHandler::motorCommand(std::string, std::string, std::string)': +MotorHandler.cpp:60: error: declaration of 'char motor' shadows a parameter +MotorHandler.cpp:60: error: argument of type 'char (MotorHandler::)(std::string)' does not match 'char' +MotorHandler.cpp:60: warning: unused variable 'motor' +make: *** [obj/default/MotorHandler.o] Error 1 + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling MotorHandler.cpp to obj/default/MotorHandler.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/MotorHandler.o MotorHandler.cpp +MotorHandler.cpp: In member function 'void MotorHandler::motorCommand(std::string, std::string, std::string)': +MotorHandler.cpp:60: error: declaration of 'char motor' shadows a parameter +MotorHandler.cpp:60: error: invalid conversion from 'char' to 'const char*' +MotorHandler.cpp:60: error: initializing argument 1 of 'std::basic_string<_CharT, _Traits, _Alloc>::basic_string(const _CharT*, const _Alloc&) [with _CharT = char, _Traits = std::char_traits, _Alloc = std::allocator]' +make: *** [obj/default/MotorHandler.o] Error 1 + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling MotorHandler.cpp to obj/default/MotorHandler.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/MotorHandler.o MotorHandler.cpp +MotorHandler.cpp: In member function 'void MotorHandler::motorCommand(std::string, std::string, std::string)': +MotorHandler.cpp:60: warning: unused variable 'motorC' +MotorHandler.cpp: In member function 'char MotorHandler::interpretDirection(std::string, int)': +MotorHandler.cpp:69: warning: control reaches end of non-void function +MotorHandler.cpp: In member function 'char MotorHandler::interpretMotor(std::string)': +MotorHandler.cpp:65: warning: control reaches end of non-void function +Info: Compiling main.cpp to obj/default/main.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/main.o main.cpp +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010a0 --timestamp 1394124174 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/NewRepARCap/MCTEST/DE0-nano-HD" --jdi C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.jdi --sopcinfo C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo +Info: (MCTest.elf) 165 KBytes program size (code + initialized data). +Info: 16211 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling MotorHandler.cpp to obj/default/MotorHandler.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/MotorHandler.o MotorHandler.cpp +MotorHandler.cpp: In member function 'void MotorHandler::motorCommand(std::string, std::string, std::string)': +MotorHandler.cpp:60: warning: unused variable 'motorC' +MotorHandler.cpp: In member function 'char MotorHandler::interpretMotor(std::string)': +MotorHandler.cpp:65: error: 'MOTOR_lEFT_CHAR' was not declared in this scope +make: *** [obj/default/MotorHandler.o] Error 1 + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling MotorHandler.cpp to obj/default/MotorHandler.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/MotorHandler.o MotorHandler.cpp +MotorHandler.cpp: In member function 'void MotorHandler::motorCommand(std::string, std::string, std::string)': +MotorHandler.cpp:60: warning: unused variable 'motorC' +MotorHandler.cpp: In member function 'char MotorHandler::interpretDirection(std::string, int)': +MotorHandler.cpp:71: warning: control reaches end of non-void function +MotorHandler.cpp: In member function 'char MotorHandler::interpretMotor(std::string)': +MotorHandler.cpp:67: warning: control reaches end of non-void function +Info: Compiling main.cpp to obj/default/main.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/main.o main.cpp +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010a0 --timestamp 1394124174 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/NewRepARCap/MCTEST/DE0-nano-HD" --jdi C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.jdi --sopcinfo C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo +Info: (MCTest.elf) 165 KBytes program size (code + initialized data). +Info: 16211 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling MotorHandler.cpp to obj/default/MotorHandler.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/MotorHandler.o MotorHandler.cpp +MotorHandler.cpp: In member function 'void MotorHandler::motorCommand(std::string, std::string, std::string)': +MotorHandler.cpp:60: warning: unused variable 'motorC' +MotorHandler.cpp: In member function 'char MotorHandler::interpretDirection(std::string, int)': +MotorHandler.cpp:73: warning: control reaches end of non-void function +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010a0 --timestamp 1394124174 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/NewRepARCap/MCTEST/DE0-nano-HD" --jdi C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.jdi --sopcinfo C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo +Info: (MCTest.elf) 165 KBytes program size (code + initialized data). +Info: 16211 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling MotorHandler.cpp to obj/default/MotorHandler.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/MotorHandler.o MotorHandler.cpp +MotorHandler.cpp: In member function 'void MotorHandler::motorCommand(std::string, std::string, std::string)': +MotorHandler.cpp:61: warning: unused variable 'Direction' +MotorHandler.cpp: In member function 'char MotorHandler::interpretDirection(std::string, int)': +MotorHandler.cpp:74: warning: control reaches end of non-void function +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010a0 --timestamp 1394124174 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/NewRepARCap/MCTEST/DE0-nano-HD" --jdi C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.jdi --sopcinfo C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo +Info: (MCTest.elf) 165 KBytes program size (code + initialized data). +Info: 16211 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling MotorHandler.cpp to obj/default/MotorHandler.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/MotorHandler.o MotorHandler.cpp +MotorHandler.cpp: In member function 'void MotorHandler::motorCommand(std::string, std::string, std::string)': +MotorHandler.cpp:61: warning: unused variable 'Direction' +MotorHandler.cpp: In member function 'char MotorHandler::interpretDirection(std::string, int)': +MotorHandler.cpp:76: error: expected ';' before '}' token +MotorHandler.cpp:80: error: expected primary-expression before '}' token +MotorHandler.cpp:80: error: expected `;' before '}' token +make: *** [obj/default/MotorHandler.o] Error 1 + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling MotorHandler.cpp to obj/default/MotorHandler.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/MotorHandler.o MotorHandler.cpp +MotorHandler.cpp: In member function 'void MotorHandler::motorCommand(std::string, std::string, std::string)': +MotorHandler.cpp:61: warning: unused variable 'Direction' +MotorHandler.cpp: In member function 'char MotorHandler::interpretDirection(std::string, int)': +MotorHandler.cpp:80: error: expected primary-expression before '}' token +MotorHandler.cpp:80: error: expected `;' before '}' token +make: *** [obj/default/MotorHandler.o] Error 1 + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling MotorHandler.cpp to obj/default/MotorHandler.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/MotorHandler.o MotorHandler.cpp +MotorHandler.cpp: In member function 'void MotorHandler::motorCommand(std::string, std::string, std::string)': +MotorHandler.cpp:61: warning: unused variable 'Direction' +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010a0 --timestamp 1394124174 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/NewRepARCap/MCTEST/DE0-nano-HD" --jdi C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.jdi --sopcinfo C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo +Info: (MCTest.elf) 166 KBytes program size (code + initialized data). +Info: 16210 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling MotorHandler.cpp to obj/default/MotorHandler.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/MotorHandler.o MotorHandler.cpp +MotorHandler.cpp: In member function 'void MotorHandler::motorCommand(std::string, std::string, std::string)': +MotorHandler.cpp:62: error: cannot convert 'std::string' to 'const char*' for argument '1' to 'long int atol(const char*)' +MotorHandler.cpp:63: error: no matching function for call to 'MotorHandler::move(char&, std::string&, const char [11])' +MotorHandler.h:63: note: candidates are: void MotorHandler::move(char, char, char*) +MotorHandler.cpp:62: warning: unused variable 'Speed' +make: *** [obj/default/MotorHandler.o] Error 1 + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling MotorHandler.cpp to obj/default/MotorHandler.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/MotorHandler.o MotorHandler.cpp +MotorHandler.cpp: In member function 'void MotorHandler::motorCommand(std::string, std::string, std::string)': +MotorHandler.cpp:62: error: cannot convert 'std::string' to 'const char*' for argument '1' to 'long int atol(const char*)' +make: *** [obj/default/MotorHandler.o] Error 1 + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling MotorHandler.cpp to obj/default/MotorHandler.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/MotorHandler.o MotorHandler.cpp +MotorHandler.cpp: In member function 'void MotorHandler::motorCommand(std::string, std::string, std::string)': +MotorHandler.cpp:62: error: cannot convert 'std::string' to 'const char*' for argument '1' to 'long int atol(const char*)' +make: *** [obj/default/MotorHandler.o] Error 1 + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Clean-only build of configuration Nios II for project MCTest **** + +make clean +[MCTest clean complete] + +**** Build Finished **** + +**** Clean-only build of configuration Nios II for project MCTest_bsp **** + +make clean +[BSP clean complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +Compiling alt_alarm_start.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_alarm_start.o HAL/src/alt_alarm_start.c +Compiling alt_busy_sleep.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_busy_sleep.o HAL/src/alt_busy_sleep.c +Compiling alt_close.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_close.o HAL/src/alt_close.c +Compiling alt_dcache_flush.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dcache_flush.o HAL/src/alt_dcache_flush.c +Compiling alt_dcache_flush_all.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dcache_flush_all.o HAL/src/alt_dcache_flush_all.c +Compiling alt_dcache_flush_no_writeback.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dcache_flush_no_writeback.o HAL/src/alt_dcache_flush_no_writeback.c +Compiling alt_dev.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dev.o HAL/src/alt_dev.c +Compiling alt_dev_llist_insert.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dev_llist_insert.o HAL/src/alt_dev_llist_insert.c +Compiling alt_dma_rxchan_open.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dma_rxchan_open.o HAL/src/alt_dma_rxchan_open.c +Compiling alt_dma_txchan_open.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dma_txchan_open.o HAL/src/alt_dma_txchan_open.c +Compiling alt_do_ctors.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_do_ctors.o HAL/src/alt_do_ctors.c +Compiling alt_do_dtors.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_do_dtors.o HAL/src/alt_do_dtors.c +Compiling alt_environ.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_environ.o HAL/src/alt_environ.c +Compiling alt_errno.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_errno.o HAL/src/alt_errno.c +Compiling alt_exception_entry.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_exception_entry.o HAL/src/alt_exception_entry.S +Compiling alt_exception_muldiv.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_exception_muldiv.o HAL/src/alt_exception_muldiv.S +Compiling alt_exception_trap.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_exception_trap.o HAL/src/alt_exception_trap.S +Compiling alt_execve.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_execve.o HAL/src/alt_execve.c +Compiling alt_exit.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_exit.o HAL/src/alt_exit.c +Compiling alt_fcntl.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fcntl.o HAL/src/alt_fcntl.c +Compiling alt_fd_lock.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fd_lock.o HAL/src/alt_fd_lock.c +Compiling alt_fd_unlock.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fd_unlock.o HAL/src/alt_fd_unlock.c +Compiling alt_find_dev.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_find_dev.o HAL/src/alt_find_dev.c +Compiling alt_find_file.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_find_file.o HAL/src/alt_find_file.c +Compiling alt_flash_dev.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_flash_dev.o HAL/src/alt_flash_dev.c +Compiling alt_fork.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fork.o HAL/src/alt_fork.c +Compiling alt_fs_reg.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fs_reg.o HAL/src/alt_fs_reg.c +Compiling alt_fstat.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fstat.o HAL/src/alt_fstat.c +Compiling alt_get_fd.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_get_fd.o HAL/src/alt_get_fd.c +Compiling alt_getchar.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_getchar.o HAL/src/alt_getchar.c +Compiling alt_getpid.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_getpid.o HAL/src/alt_getpid.c +Compiling alt_gettod.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_gettod.o HAL/src/alt_gettod.c +Compiling alt_gmon.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_gmon.o HAL/src/alt_gmon.c +Compiling alt_icache_flush.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_icache_flush.o HAL/src/alt_icache_flush.c +Compiling alt_icache_flush_all.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_icache_flush_all.o HAL/src/alt_icache_flush_all.c +Compiling alt_iic.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_iic.o HAL/src/alt_iic.c +Compiling alt_iic_isr_register.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_iic_isr_register.o HAL/src/alt_iic_isr_register.c +Compiling alt_instruction_exception_entry.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_instruction_exception_entry.o HAL/src/alt_instruction_exception_entry.c +Compiling alt_instruction_exception_register.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_instruction_exception_register.o HAL/src/alt_instruction_exception_register.c +Compiling alt_io_redirect.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_io_redirect.o HAL/src/alt_io_redirect.c +Compiling alt_ioctl.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_ioctl.o HAL/src/alt_ioctl.c +Compiling alt_irq_entry.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_irq_entry.o HAL/src/alt_irq_entry.S +Compiling alt_irq_handler.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_irq_handler.o HAL/src/alt_irq_handler.c +Compiling alt_irq_register.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_irq_register.o HAL/src/alt_irq_register.c +Compiling alt_irq_vars.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_irq_vars.o HAL/src/alt_irq_vars.c +Compiling alt_isatty.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_isatty.o HAL/src/alt_isatty.c +Compiling alt_kill.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_kill.o HAL/src/alt_kill.c +Compiling alt_link.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_link.o HAL/src/alt_link.c +Compiling alt_load.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_load.o HAL/src/alt_load.c +Compiling alt_log_macro.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_log_macro.o HAL/src/alt_log_macro.S +Compiling alt_log_printf.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_log_printf.o HAL/src/alt_log_printf.c +Compiling alt_lseek.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_lseek.o HAL/src/alt_lseek.c +Compiling alt_main.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_main.o HAL/src/alt_main.c +Compiling alt_mcount.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_mcount.o HAL/src/alt_mcount.S +Compiling alt_open.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_open.o HAL/src/alt_open.c +Compiling alt_printf.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_printf.o HAL/src/alt_printf.c +Compiling alt_putchar.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_putchar.o HAL/src/alt_putchar.c +Compiling alt_putstr.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_putstr.o HAL/src/alt_putstr.c +Compiling alt_read.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_read.o HAL/src/alt_read.c +Compiling alt_release_fd.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_release_fd.o HAL/src/alt_release_fd.c +Compiling alt_remap_cached.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_remap_cached.o HAL/src/alt_remap_cached.c +Compiling alt_remap_uncached.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_remap_uncached.o HAL/src/alt_remap_uncached.c +Compiling alt_rename.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_rename.o HAL/src/alt_rename.c +Compiling alt_sbrk.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_sbrk.o HAL/src/alt_sbrk.c +Compiling alt_settod.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_settod.o HAL/src/alt_settod.c +Compiling alt_software_exception.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_software_exception.o HAL/src/alt_software_exception.S +Compiling alt_stat.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_stat.o HAL/src/alt_stat.c +Compiling alt_tick.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_tick.o HAL/src/alt_tick.c +Compiling alt_times.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_times.o HAL/src/alt_times.c +Compiling alt_uncached_free.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_uncached_free.o HAL/src/alt_uncached_free.c +Compiling alt_uncached_malloc.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_uncached_malloc.o HAL/src/alt_uncached_malloc.c +Compiling alt_unlink.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_unlink.o HAL/src/alt_unlink.c +Compiling alt_usleep.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_usleep.o HAL/src/alt_usleep.c +Compiling alt_wait.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_wait.o HAL/src/alt_wait.c +Compiling alt_write.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_write.o HAL/src/alt_write.c +Compiling altera_nios2_qsys_irq.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/altera_nios2_qsys_irq.o HAL/src/altera_nios2_qsys_irq.c +Compiling crt0.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/crt0.o HAL/src/crt0.S +Compiling os_cpu_a.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/os_cpu_a.o HAL/src/os_cpu_a.S +Compiling os_cpu_c.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/os_cpu_c.o HAL/src/os_cpu_c.c +Compiling alt_env_lock.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/alt_env_lock.o UCOSII/src/alt_env_lock.c +Compiling alt_malloc_lock.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/alt_malloc_lock.o UCOSII/src/alt_malloc_lock.c +Compiling os_core.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_core.o UCOSII/src/os_core.c +Compiling os_dbg.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_dbg.o UCOSII/src/os_dbg.c +Compiling os_flag.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_flag.o UCOSII/src/os_flag.c +Compiling os_mbox.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_mbox.o UCOSII/src/os_mbox.c +Compiling os_mem.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_mem.o UCOSII/src/os_mem.c +Compiling os_mutex.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_mutex.o UCOSII/src/os_mutex.c +Compiling os_q.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_q.o UCOSII/src/os_q.c +Compiling os_sem.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_sem.o UCOSII/src/os_sem.c +Compiling os_task.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_task.o UCOSII/src/os_task.c +Compiling os_time.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_time.o UCOSII/src/os_time.c +Compiling os_tmr.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_tmr.o UCOSII/src/os_tmr.c +Compiling alt_sys_init.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/alt_sys_init.o alt_sys_init.c +Compiling altera_avalon_jtag_uart_fd.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_jtag_uart_fd.o drivers/src/altera_avalon_jtag_uart_fd.c +Compiling altera_avalon_jtag_uart_init.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_jtag_uart_init.o drivers/src/altera_avalon_jtag_uart_init.c +Compiling altera_avalon_jtag_uart_ioctl.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_jtag_uart_ioctl.o drivers/src/altera_avalon_jtag_uart_ioctl.c +Compiling altera_avalon_jtag_uart_read.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_jtag_uart_read.o drivers/src/altera_avalon_jtag_uart_read.c +Compiling altera_avalon_jtag_uart_write.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_jtag_uart_write.o drivers/src/altera_avalon_jtag_uart_write.c +Compiling altera_avalon_sysid_qsys.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_sysid_qsys.o drivers/src/altera_avalon_sysid_qsys.c +Compiling altera_avalon_timer_sc.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_timer_sc.o drivers/src/altera_avalon_timer_sc.c +Compiling altera_avalon_timer_ts.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_timer_ts.o drivers/src/altera_avalon_timer_ts.c +Compiling altera_avalon_timer_vars.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_timer_vars.o drivers/src/altera_avalon_timer_vars.c +Compiling altera_avalon_uart_fd.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_uart_fd.o drivers/src/altera_avalon_uart_fd.c +Compiling altera_avalon_uart_init.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_uart_init.o drivers/src/altera_avalon_uart_init.c +Compiling altera_avalon_uart_ioctl.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_uart_ioctl.o drivers/src/altera_avalon_uart_ioctl.c +Compiling altera_avalon_uart_read.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_uart_read.o drivers/src/altera_avalon_uart_read.c +Compiling altera_avalon_uart_write.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_uart_write.o drivers/src/altera_avalon_uart_write.c +drivers/src/altera_up_avalon_rs232.c: In function 'alt_up_rs232_read_fd': +Compiling altera_up_avalon_rs232.c... +drivers/src/altera_up_avalon_rs232.c:110: warning: pointer targets in passing argument 2 of 'alt_up_rs232_read_data' differ in signedness +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_up_avalon_rs232.o drivers/src/altera_up_avalon_rs232.c +Creating libucosii_bsp.a... +rm -f -f libucosii_bsp.a +nios2-elf-ar -src libucosii_bsp.a obj/HAL/src/alt_alarm_start.o obj/HAL/src/alt_busy_sleep.o obj/HAL/src/alt_close.o obj/HAL/src/alt_dcache_flush.o obj/HAL/src/alt_dcache_flush_all.o obj/HAL/src/alt_dcache_flush_no_writeback.o obj/HAL/src/alt_dev.o obj/HAL/src/alt_dev_llist_insert.o obj/HAL/src/alt_dma_rxchan_open.o obj/HAL/src/alt_dma_txchan_open.o obj/HAL/src/alt_do_ctors.o obj/HAL/src/alt_do_dtors.o obj/HAL/src/alt_environ.o obj/HAL/src/alt_errno.o obj/HAL/src/alt_exception_entry.o obj/HAL/src/alt_exception_muldiv.o obj/HAL/src/alt_exception_trap.o obj/HAL/src/alt_execve.o obj/HAL/src/alt_exit.o obj/HAL/src/alt_fcntl.o obj/HAL/src/alt_fd_lock.o obj/HAL/src/alt_fd_unlock.o obj/HAL/src/alt_find_dev.o obj/HAL/src/alt_find_file.o obj/HAL/src/alt_flash_dev.o obj/HAL/src/alt_fork.o obj/HAL/src/alt_fs_reg.o obj/HAL/src/alt_fstat.o obj/HAL/src/alt_get_fd.o obj/HAL/src/alt_getchar.o obj/HAL/src/alt_getpid.o obj/HAL/src/alt_gettod.o obj/HAL/src/alt_gmon.o obj/HAL/src/alt_icache_flush.o obj/HAL/src/alt_icache_flush_all.o obj/HAL/src/alt_iic.o obj/HAL/src/alt_iic_isr_register.o obj/HAL/src/alt_instruction_exception_entry.o obj/HAL/src/alt_instruction_exception_register.o obj/HAL/src/alt_io_redirect.o obj/HAL/src/alt_ioctl.o obj/HAL/src/alt_irq_entry.o obj/HAL/src/alt_irq_handler.o obj/HAL/src/alt_irq_register.o obj/HAL/src/alt_irq_vars.o obj/HAL/src/alt_isatty.o obj/HAL/src/alt_kill.o obj/HAL/src/alt_link.o obj/HAL/src/alt_load.o obj/HAL/src/alt_log_macro.o obj/HAL/src/alt_log_printf.o obj/HAL/src/alt_lseek.o obj/HAL/src/alt_main.o obj/HAL/src/alt_mcount.o obj/HAL/src/alt_open.o obj/HAL/src/alt_printf.o obj/HAL/src/alt_putchar.o obj/HAL/src/alt_putstr.o obj/HAL/src/alt_read.o obj/HAL/src/alt_release_fd.o obj/HAL/src/alt_remap_cached.o obj/HAL/src/alt_remap_uncached.o obj/HAL/src/alt_rename.o obj/HAL/src/alt_sbrk.o obj/HAL/src/alt_settod.o obj/HAL/src/alt_software_exception.o obj/HAL/src/alt_stat.o obj/HAL/src/alt_tick.o obj/HAL/src/alt_times.o obj/HAL/src/alt_uncached_free.o obj/HAL/src/alt_uncached_malloc.o obj/HAL/src/alt_unlink.o obj/HAL/src/alt_usleep.o obj/HAL/src/alt_wait.o obj/HAL/src/alt_write.o obj/HAL/src/altera_nios2_qsys_irq.o obj/HAL/src/crt0.o obj/HAL/src/os_cpu_a.o obj/HAL/src/os_cpu_c.o obj/UCOSII/src/alt_env_lock.o obj/UCOSII/src/alt_malloc_lock.o obj/UCOSII/src/os_core.o obj/UCOSII/src/os_dbg.o obj/UCOSII/src/os_flag.o obj/UCOSII/src/os_mbox.o obj/UCOSII/src/os_mem.o obj/UCOSII/src/os_mutex.o obj/UCOSII/src/os_q.o obj/UCOSII/src/os_sem.o obj/UCOSII/src/os_task.o obj/UCOSII/src/os_time.o obj/UCOSII/src/os_tmr.o obj/alt_sys_init.o obj/drivers/src/altera_avalon_jtag_uart_fd.o obj/drivers/src/altera_avalon_jtag_uart_init.o obj/drivers/src/altera_avalon_jtag_uart_ioctl.o obj/drivers/src/altera_avalon_jtag_uart_read.o obj/drivers/src/altera_avalon_jtag_uart_write.o obj/drivers/src/altera_avalon_sysid_qsys.o obj/drivers/src/altera_avalon_timer_sc.o obj/drivers/src/altera_avalon_timer_ts.o obj/drivers/src/altera_avalon_timer_vars.o obj/drivers/src/altera_avalon_uart_fd.o obj/drivers/src/altera_avalon_uart_init.o obj/drivers/src/altera_avalon_uart_ioctl.o obj/drivers/src/altera_avalon_uart_read.o obj/drivers/src/altera_avalon_uart_write.o obj/drivers/src/altera_up_avalon_rs232.o +[BSP build complete] +Info: Compiling MotorHandler.cpp to obj/default/MotorHandler.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/MotorHandler.o MotorHandler.cpp +MotorHandler.cpp: In member function 'void MotorHandler::motorCommand(std::string, std::string, std::string)': +MotorHandler.cpp:62: error: cannot convert 'std::string' to 'const char*' for argument '1' to 'long int atol(const char*)' +make: *** [obj/default/MotorHandler.o] Error 1 + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling MotorHandler.cpp to obj/default/MotorHandler.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/MotorHandler.o MotorHandler.cpp +c:\altera\12.1sp1\nios2eds\bin\gnu\h-i686-mingw32\bin\../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/include/stdlib.h: In member function 'void MotorHandler::motorCommand(std::string, std::string, std::string)': +c:\altera\12.1sp1\nios2eds\bin\gnu\h-i686-mingw32\bin\../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/include/stdlib.h:117: error: too few arguments to function 'long int strtol(const char*, char**, int)' +MotorHandler.cpp:62: error: at this point in file +make: *** [obj/default/MotorHandler.o] Error 1 + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling MotorHandler.cpp to obj/default/MotorHandler.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/MotorHandler.o MotorHandler.cpp +Info: Compiling main.cpp to obj/default/main.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/main.o main.cpp +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010a0 --timestamp 1394124174 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/NewRepARCap/MCTEST/DE0-nano-HD" --jdi C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.jdi --sopcinfo C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo +Info: (MCTest.elf) 167 KBytes program size (code + initialized data). +Info: 16209 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling MotorHandler.cpp to obj/default/MotorHandler.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/MotorHandler.o MotorHandler.cpp +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010a0 --timestamp 1394124174 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/NewRepARCap/MCTEST/DE0-nano-HD" --jdi C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.jdi --sopcinfo C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo +Info: (MCTest.elf) 167 KBytes program size (code + initialized data). +Info: 16209 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling MotorHandler.cpp to obj/default/MotorHandler.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/MotorHandler.o MotorHandler.cpp +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010a0 --timestamp 1394124174 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/NewRepARCap/MCTEST/DE0-nano-HD" --jdi C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.jdi --sopcinfo C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo +Info: (MCTest.elf) 167 KBytes program size (code + initialized data). +Info: 16209 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling MotorHandler.cpp to obj/default/MotorHandler.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/MotorHandler.o MotorHandler.cpp +MotorHandler.cpp: In member function 'void MotorHandler::motorCommand(std::string, std::string, std::string)': +MotorHandler.cpp:64: error: no matching function for call to 'MotorHandler::move(char&, int&, std::basic_string, std::allocator >&)' +MotorHandler.h:63: note: candidates are: void MotorHandler::move(char, char, char*) +make: *** [obj/default/MotorHandler.o] Error 1 + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling MotorHandler.cpp to obj/default/MotorHandler.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/MotorHandler.o MotorHandler.cpp +MotorHandler.cpp: In member function 'void MotorHandler::send(char, std::string)': +MotorHandler.cpp:116: warning: cannot pass objects of non-POD type 'struct std::string' through '...'; call will abort at runtime +MotorHandler.cpp:116: warning: format '%s' expects type 'char*', but argument 3 has type 'int' +MotorHandler.cpp:116: warning: format '%s' expects type 'char*', but argument 3 has type 'int' +MotorHandler.cpp:125: warning: cannot pass objects of non-POD type 'struct std::string' through '...'; call will abort at runtime +MotorHandler.cpp:125: warning: format '%s' expects type 'char*', but argument 3 has type 'int' +MotorHandler.cpp:125: warning: format '%s' expects type 'char*', but argument 3 has type 'int' +Info: Compiling main.cpp to obj/default/main.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/main.o main.cpp +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010a0 --timestamp 1394124174 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/NewRepARCap/MCTEST/DE0-nano-HD" --jdi C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.jdi --sopcinfo C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo +Info: (MCTest.elf) 168 KBytes program size (code + initialized data). +Info: 16208 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Clean-only build of configuration Nios II for project MCTest **** + +make clean +[MCTest clean complete] + +**** Build Finished **** + +**** Clean-only build of configuration Nios II for project MCTest_bsp **** + +make clean +[BSP clean complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +Compiling alt_alarm_start.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_alarm_start.o HAL/src/alt_alarm_start.c +Compiling alt_busy_sleep.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_busy_sleep.o HAL/src/alt_busy_sleep.c +Compiling alt_close.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_close.o HAL/src/alt_close.c +Compiling alt_dcache_flush.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dcache_flush.o HAL/src/alt_dcache_flush.c +Compiling alt_dcache_flush_all.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dcache_flush_all.o HAL/src/alt_dcache_flush_all.c +Compiling alt_dcache_flush_no_writeback.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dcache_flush_no_writeback.o HAL/src/alt_dcache_flush_no_writeback.c +Compiling alt_dev.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dev.o HAL/src/alt_dev.c +Compiling alt_dev_llist_insert.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dev_llist_insert.o HAL/src/alt_dev_llist_insert.c +Compiling alt_dma_rxchan_open.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dma_rxchan_open.o HAL/src/alt_dma_rxchan_open.c +Compiling alt_dma_txchan_open.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dma_txchan_open.o HAL/src/alt_dma_txchan_open.c +Compiling alt_do_ctors.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_do_ctors.o HAL/src/alt_do_ctors.c +Compiling alt_do_dtors.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_do_dtors.o HAL/src/alt_do_dtors.c +Compiling alt_environ.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_environ.o HAL/src/alt_environ.c +Compiling alt_errno.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_errno.o HAL/src/alt_errno.c +Compiling alt_exception_entry.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_exception_entry.o HAL/src/alt_exception_entry.S +Compiling alt_exception_muldiv.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_exception_muldiv.o HAL/src/alt_exception_muldiv.S +Compiling alt_exception_trap.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_exception_trap.o HAL/src/alt_exception_trap.S +Compiling alt_execve.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_execve.o HAL/src/alt_execve.c +Compiling alt_exit.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_exit.o HAL/src/alt_exit.c +Compiling alt_fcntl.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fcntl.o HAL/src/alt_fcntl.c +Compiling alt_fd_lock.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fd_lock.o HAL/src/alt_fd_lock.c +Compiling alt_fd_unlock.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fd_unlock.o HAL/src/alt_fd_unlock.c +Compiling alt_find_dev.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_find_dev.o HAL/src/alt_find_dev.c +Compiling alt_find_file.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_find_file.o HAL/src/alt_find_file.c +Compiling alt_flash_dev.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_flash_dev.o HAL/src/alt_flash_dev.c +Compiling alt_fork.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fork.o HAL/src/alt_fork.c +Compiling alt_fs_reg.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fs_reg.o HAL/src/alt_fs_reg.c +Compiling alt_fstat.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fstat.o HAL/src/alt_fstat.c +Compiling alt_get_fd.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_get_fd.o HAL/src/alt_get_fd.c +Compiling alt_getchar.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_getchar.o HAL/src/alt_getchar.c +Compiling alt_getpid.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_getpid.o HAL/src/alt_getpid.c +Compiling alt_gettod.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_gettod.o HAL/src/alt_gettod.c +Compiling alt_gmon.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_gmon.o HAL/src/alt_gmon.c +Compiling alt_icache_flush.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_icache_flush.o HAL/src/alt_icache_flush.c +Compiling alt_icache_flush_all.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_icache_flush_all.o HAL/src/alt_icache_flush_all.c +Compiling alt_iic.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_iic.o HAL/src/alt_iic.c +Compiling alt_iic_isr_register.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_iic_isr_register.o HAL/src/alt_iic_isr_register.c +Compiling alt_instruction_exception_entry.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_instruction_exception_entry.o HAL/src/alt_instruction_exception_entry.c +Compiling alt_instruction_exception_register.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_instruction_exception_register.o HAL/src/alt_instruction_exception_register.c +Compiling alt_io_redirect.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_io_redirect.o HAL/src/alt_io_redirect.c +Compiling alt_ioctl.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_ioctl.o HAL/src/alt_ioctl.c +Compiling alt_irq_entry.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_irq_entry.o HAL/src/alt_irq_entry.S +Compiling alt_irq_handler.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_irq_handler.o HAL/src/alt_irq_handler.c +Compiling alt_irq_register.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_irq_register.o HAL/src/alt_irq_register.c +Compiling alt_irq_vars.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_irq_vars.o HAL/src/alt_irq_vars.c +Compiling alt_isatty.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_isatty.o HAL/src/alt_isatty.c +Compiling alt_kill.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_kill.o HAL/src/alt_kill.c +Compiling alt_link.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_link.o HAL/src/alt_link.c +Compiling alt_load.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_load.o HAL/src/alt_load.c +Compiling alt_log_macro.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_log_macro.o HAL/src/alt_log_macro.S +Compiling alt_log_printf.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_log_printf.o HAL/src/alt_log_printf.c +Compiling alt_lseek.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_lseek.o HAL/src/alt_lseek.c +Compiling alt_main.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_main.o HAL/src/alt_main.c +Compiling alt_mcount.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_mcount.o HAL/src/alt_mcount.S +Compiling alt_open.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_open.o HAL/src/alt_open.c +Compiling alt_printf.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_printf.o HAL/src/alt_printf.c +Compiling alt_putchar.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_putchar.o HAL/src/alt_putchar.c +Compiling alt_putstr.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_putstr.o HAL/src/alt_putstr.c +Compiling alt_read.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_read.o HAL/src/alt_read.c +Compiling alt_release_fd.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_release_fd.o HAL/src/alt_release_fd.c +Compiling alt_remap_cached.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_remap_cached.o HAL/src/alt_remap_cached.c +Compiling alt_remap_uncached.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_remap_uncached.o HAL/src/alt_remap_uncached.c +Compiling alt_rename.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_rename.o HAL/src/alt_rename.c +Compiling alt_sbrk.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_sbrk.o HAL/src/alt_sbrk.c +Compiling alt_settod.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_settod.o HAL/src/alt_settod.c +Compiling alt_software_exception.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_software_exception.o HAL/src/alt_software_exception.S +Compiling alt_stat.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_stat.o HAL/src/alt_stat.c +Compiling alt_tick.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_tick.o HAL/src/alt_tick.c +Compiling alt_times.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_times.o HAL/src/alt_times.c +Compiling alt_uncached_free.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_uncached_free.o HAL/src/alt_uncached_free.c +Compiling alt_uncached_malloc.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_uncached_malloc.o HAL/src/alt_uncached_malloc.c +Compiling alt_unlink.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_unlink.o HAL/src/alt_unlink.c +Compiling alt_usleep.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_usleep.o HAL/src/alt_usleep.c +Compiling alt_wait.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_wait.o HAL/src/alt_wait.c +Compiling alt_write.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_write.o HAL/src/alt_write.c +Compiling altera_nios2_qsys_irq.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/altera_nios2_qsys_irq.o HAL/src/altera_nios2_qsys_irq.c +Compiling crt0.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/crt0.o HAL/src/crt0.S +Compiling os_cpu_a.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/os_cpu_a.o HAL/src/os_cpu_a.S +Compiling os_cpu_c.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/os_cpu_c.o HAL/src/os_cpu_c.c +Compiling alt_env_lock.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/alt_env_lock.o UCOSII/src/alt_env_lock.c +Compiling alt_malloc_lock.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/alt_malloc_lock.o UCOSII/src/alt_malloc_lock.c +Compiling os_core.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_core.o UCOSII/src/os_core.c +Compiling os_dbg.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_dbg.o UCOSII/src/os_dbg.c +Compiling os_flag.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_flag.o UCOSII/src/os_flag.c +Compiling os_mbox.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_mbox.o UCOSII/src/os_mbox.c +Compiling os_mem.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_mem.o UCOSII/src/os_mem.c +Compiling os_mutex.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_mutex.o UCOSII/src/os_mutex.c +Compiling os_q.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_q.o UCOSII/src/os_q.c +Compiling os_sem.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_sem.o UCOSII/src/os_sem.c +Compiling os_task.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_task.o UCOSII/src/os_task.c +Compiling os_time.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_time.o UCOSII/src/os_time.c +Compiling os_tmr.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_tmr.o UCOSII/src/os_tmr.c +Compiling alt_sys_init.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/alt_sys_init.o alt_sys_init.c +Compiling altera_avalon_jtag_uart_fd.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_jtag_uart_fd.o drivers/src/altera_avalon_jtag_uart_fd.c +Compiling altera_avalon_jtag_uart_init.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_jtag_uart_init.o drivers/src/altera_avalon_jtag_uart_init.c +Compiling altera_avalon_jtag_uart_ioctl.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_jtag_uart_ioctl.o drivers/src/altera_avalon_jtag_uart_ioctl.c +Compiling altera_avalon_jtag_uart_read.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_jtag_uart_read.o drivers/src/altera_avalon_jtag_uart_read.c +Compiling altera_avalon_jtag_uart_write.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_jtag_uart_write.o drivers/src/altera_avalon_jtag_uart_write.c +Compiling altera_avalon_sysid_qsys.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_sysid_qsys.o drivers/src/altera_avalon_sysid_qsys.c +Compiling altera_avalon_timer_sc.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_timer_sc.o drivers/src/altera_avalon_timer_sc.c +Compiling altera_avalon_timer_ts.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_timer_ts.o drivers/src/altera_avalon_timer_ts.c +Compiling altera_avalon_timer_vars.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_timer_vars.o drivers/src/altera_avalon_timer_vars.c +Compiling altera_avalon_uart_fd.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_uart_fd.o drivers/src/altera_avalon_uart_fd.c +Compiling altera_avalon_uart_init.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_uart_init.o drivers/src/altera_avalon_uart_init.c +Compiling altera_avalon_uart_ioctl.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_uart_ioctl.o drivers/src/altera_avalon_uart_ioctl.c +Compiling altera_avalon_uart_read.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_uart_read.o drivers/src/altera_avalon_uart_read.c +Compiling altera_avalon_uart_write.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_uart_write.o drivers/src/altera_avalon_uart_write.c +drivers/src/altera_up_avalon_rs232.c: In function 'alt_up_rs232_read_fd': +Compiling altera_up_avalon_rs232.c... +drivers/src/altera_up_avalon_rs232.c:110: warning: pointer targets in passing argument 2 of 'alt_up_rs232_read_data' differ in signedness +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_up_avalon_rs232.o drivers/src/altera_up_avalon_rs232.c +Creating libucosii_bsp.a... +rm -f -f libucosii_bsp.a +nios2-elf-ar -src libucosii_bsp.a obj/HAL/src/alt_alarm_start.o obj/HAL/src/alt_busy_sleep.o obj/HAL/src/alt_close.o obj/HAL/src/alt_dcache_flush.o obj/HAL/src/alt_dcache_flush_all.o obj/HAL/src/alt_dcache_flush_no_writeback.o obj/HAL/src/alt_dev.o obj/HAL/src/alt_dev_llist_insert.o obj/HAL/src/alt_dma_rxchan_open.o obj/HAL/src/alt_dma_txchan_open.o obj/HAL/src/alt_do_ctors.o obj/HAL/src/alt_do_dtors.o obj/HAL/src/alt_environ.o obj/HAL/src/alt_errno.o obj/HAL/src/alt_exception_entry.o obj/HAL/src/alt_exception_muldiv.o obj/HAL/src/alt_exception_trap.o obj/HAL/src/alt_execve.o obj/HAL/src/alt_exit.o obj/HAL/src/alt_fcntl.o obj/HAL/src/alt_fd_lock.o obj/HAL/src/alt_fd_unlock.o obj/HAL/src/alt_find_dev.o obj/HAL/src/alt_find_file.o obj/HAL/src/alt_flash_dev.o obj/HAL/src/alt_fork.o obj/HAL/src/alt_fs_reg.o obj/HAL/src/alt_fstat.o obj/HAL/src/alt_get_fd.o obj/HAL/src/alt_getchar.o obj/HAL/src/alt_getpid.o obj/HAL/src/alt_gettod.o obj/HAL/src/alt_gmon.o obj/HAL/src/alt_icache_flush.o obj/HAL/src/alt_icache_flush_all.o obj/HAL/src/alt_iic.o obj/HAL/src/alt_iic_isr_register.o obj/HAL/src/alt_instruction_exception_entry.o obj/HAL/src/alt_instruction_exception_register.o obj/HAL/src/alt_io_redirect.o obj/HAL/src/alt_ioctl.o obj/HAL/src/alt_irq_entry.o obj/HAL/src/alt_irq_handler.o obj/HAL/src/alt_irq_register.o obj/HAL/src/alt_irq_vars.o obj/HAL/src/alt_isatty.o obj/HAL/src/alt_kill.o obj/HAL/src/alt_link.o obj/HAL/src/alt_load.o obj/HAL/src/alt_log_macro.o obj/HAL/src/alt_log_printf.o obj/HAL/src/alt_lseek.o obj/HAL/src/alt_main.o obj/HAL/src/alt_mcount.o obj/HAL/src/alt_open.o obj/HAL/src/alt_printf.o obj/HAL/src/alt_putchar.o obj/HAL/src/alt_putstr.o obj/HAL/src/alt_read.o obj/HAL/src/alt_release_fd.o obj/HAL/src/alt_remap_cached.o obj/HAL/src/alt_remap_uncached.o obj/HAL/src/alt_rename.o obj/HAL/src/alt_sbrk.o obj/HAL/src/alt_settod.o obj/HAL/src/alt_software_exception.o obj/HAL/src/alt_stat.o obj/HAL/src/alt_tick.o obj/HAL/src/alt_times.o obj/HAL/src/alt_uncached_free.o obj/HAL/src/alt_uncached_malloc.o obj/HAL/src/alt_unlink.o obj/HAL/src/alt_usleep.o obj/HAL/src/alt_wait.o obj/HAL/src/alt_write.o obj/HAL/src/altera_nios2_qsys_irq.o obj/HAL/src/crt0.o obj/HAL/src/os_cpu_a.o obj/HAL/src/os_cpu_c.o obj/UCOSII/src/alt_env_lock.o obj/UCOSII/src/alt_malloc_lock.o obj/UCOSII/src/os_core.o obj/UCOSII/src/os_dbg.o obj/UCOSII/src/os_flag.o obj/UCOSII/src/os_mbox.o obj/UCOSII/src/os_mem.o obj/UCOSII/src/os_mutex.o obj/UCOSII/src/os_q.o obj/UCOSII/src/os_sem.o obj/UCOSII/src/os_task.o obj/UCOSII/src/os_time.o obj/UCOSII/src/os_tmr.o obj/alt_sys_init.o obj/drivers/src/altera_avalon_jtag_uart_fd.o obj/drivers/src/altera_avalon_jtag_uart_init.o obj/drivers/src/altera_avalon_jtag_uart_ioctl.o obj/drivers/src/altera_avalon_jtag_uart_read.o obj/drivers/src/altera_avalon_jtag_uart_write.o obj/drivers/src/altera_avalon_sysid_qsys.o obj/drivers/src/altera_avalon_timer_sc.o obj/drivers/src/altera_avalon_timer_ts.o obj/drivers/src/altera_avalon_timer_vars.o obj/drivers/src/altera_avalon_uart_fd.o obj/drivers/src/altera_avalon_uart_init.o obj/drivers/src/altera_avalon_uart_ioctl.o obj/drivers/src/altera_avalon_uart_read.o obj/drivers/src/altera_avalon_uart_write.o obj/drivers/src/altera_up_avalon_rs232.o +[BSP build complete] +Info: Compiling MotorHandler.cpp to obj/default/MotorHandler.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/MotorHandler.o MotorHandler.cpp +MotorHandler.cpp: In member function 'void MotorHandler::send(char, std::string)': +MotorHandler.cpp:116: warning: cannot pass objects of non-POD type 'struct std::string' through '...'; call will abort at runtime +MotorHandler.cpp:116: warning: format '%s' expects type 'char*', but argument 3 has type 'int' +MotorHandler.cpp:116: warning: format '%s' expects type 'char*', but argument 3 has type 'int' +MotorHandler.cpp:125: warning: cannot pass objects of non-POD type 'struct std::string' through '...'; call will abort at runtime +Info: Compiling main.cpp to obj/default/main.o +MotorHandler.cpp:125: warning: format '%s' expects type 'char*', but argument 3 has type 'int' +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/main.o main.cpp +MotorHandler.cpp:125: warning: format '%s' expects type 'char*', but argument 3 has type 'int' +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010a0 --timestamp 1394124174 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/NewRepARCap/MCTEST/DE0-nano-HD" --jdi C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.jdi --sopcinfo C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo +Info: (MCTest.elf) 168 KBytes program size (code + initialized data). +Info: 16208 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling MotorHandler.cpp to obj/default/MotorHandler.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/MotorHandler.o MotorHandler.cpp +MotorHandler.cpp: In member function 'void MotorHandler::motorCommand(std::string, std::string, std::string)': +MotorHandler.cpp:64: error: invalid conversion from 'const char*' to 'char*' +MotorHandler.cpp:64: error: initializing argument 3 of 'void MotorHandler::move(char, char, char*)' +make: *** [obj/default/MotorHandler.o] Error 1 + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling MotorHandler.cpp to obj/default/MotorHandler.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/MotorHandler.o MotorHandler.cpp +MotorHandler.cpp: In member function 'void MotorHandler::motorCommand(std::string, std::string, std::string)': +MotorHandler.cpp:64: error: invalid conversion from 'const char*' to 'char*' +MotorHandler.cpp:64: error: initializing argument 3 of 'void MotorHandler::move(char, char, char*)' +MotorHandler.cpp: At global scope: +MotorHandler.cpp:95: error: prototype for 'void MotorHandler::move(char, char, const char*)' does not match any in class 'MotorHandler' +MotorHandler.h:63: error: candidate is: void MotorHandler::move(char, char, char*) +MotorHandler.cpp: In member function 'void MotorHandler::move(char, char, const char*)': +MotorHandler.cpp:98: error: invalid conversion from 'const char*' to 'char*' +MotorHandler.cpp:98: error: initializing argument 2 of 'void MotorHandler::send(char, char*)' +MotorHandler.cpp: At global scope: +MotorHandler.cpp:109: error: prototype for 'void MotorHandler::send(char, const char*)' does not match any in class 'MotorHandler' +MotorHandler.h:70: error: candidate is: void MotorHandler::send(char, char*) +make: *** [obj/default/MotorHandler.o] Error 1 + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling MotorHandler.cpp to obj/default/MotorHandler.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/MotorHandler.o MotorHandler.cpp +Info: Compiling main.cpp to obj/default/main.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/main.o main.cpp +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010a0 --timestamp 1394124174 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/NewRepARCap/MCTEST/DE0-nano-HD" --jdi C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.jdi --sopcinfo C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo +Info: (MCTest.elf) 167 KBytes program size (code + initialized data). +Info: 16209 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling main.cpp to obj/default/main.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/main.o main.cpp +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010a0 --timestamp 1394124174 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/NewRepARCap/MCTEST/DE0-nano-HD" --jdi C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.jdi --sopcinfo C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo +Info: (MCTest.elf) 168 KBytes program size (code + initialized data). +Info: 16208 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling main.cpp to obj/default/main.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/main.o main.cpp +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010a0 --timestamp 1394124174 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/NewRepARCap/MCTEST/DE0-nano-HD" --jdi C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.jdi --sopcinfo C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo +Info: (MCTest.elf) 168 KBytes program size (code + initialized data). +Info: 16208 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling main.cpp to obj/default/main.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/main.o main.cpp +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010a0 --timestamp 1394124174 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/NewRepARCap/MCTEST/DE0-nano-HD" --jdi C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.jdi --sopcinfo C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo +Info: (MCTest.elf) 173 KBytes program size (code + initialized data). +Info: 16203 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/1/a042d9cc8bb000131eb0f6c547a05c39 b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/1/a042d9cc8bb000131eb0f6c547a05c39 new file mode 100644 index 00000000..73c6d899 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/1/a042d9cc8bb000131eb0f6c547a05c39 @@ -0,0 +1,73 @@ +/* + * MotorHandler.h + * + * Created on: 2014-03-03 + * Author: Amshu Gongal + */ + +#ifndef MOTORHANDLER_H_ +#define MOTORHANDLER_H_ + +#include "altera_up_avalon_rs232.h" +#include "altera_up_avalon_rs232_regs.h" +#include +using namespace std; +#include +#include "Status.h" + +//Commands from network handler +#define MOTOR_LEFT "left" +#define MOTOR_RIGHT "right" +#define MOTOR_FORWARD "forward" +#define MOTOR_BACKWARD "backward" + + +// Motor messages are LSB first +#define MOTOR_START_BYTE 0x80 +#define MOTOR_DEVICE_TYPE 0x00 +#define MOTOR_LEFT_CHAR 0x02 // motor 1 backward +#define MOTOR_RIGHT_CHAR 0x03 // motor 2 backward +#define MOTOR_LEFT_FORWARD 0x05 // motor 1 forward +#define MOTOR_RIGHT_FORWARD 0x07 // motor 2 forward +#define MOTOR_CONST_SPEED 0x5F +#define MOTOR_STOP_SPEED 0x00 +#define MOTOR_CHANGE_CONFIGURATION 0X02 + +class MotorHandler { +public: + MotorHandler(); + virtual ~MotorHandler(); + + /* + * Initializes this handler. + * @return OK if the handler was initialized without error + */ + Status init(); + void reset(); + void configure(); + void motorCommand(string motor, string motorDirection, string speed); + +private: + /* The device used to send serial commands to the motor controller. */ + alt_up_rs232_dev *motor_dev; + + char interpretMotor(string motor); + char interpretDirection(string direction, int motor); + + /* + * Moves in the given direction at constant speed. + * @param direction - the motor and direction to move in, e.g. MOTOR_MOTOR1_FORWARD + * @param speed speed of the motor + * @param description - the string description of the movement, for debugging + */ + void move(char direction, char speed, char *description); + + /* + * Sends a byte-length message to the motor controller. + * @param message - the message to send + * @param description - the string description of the message, for debugging + */ + void send(char message, char *description); +}; + +#endif /* MOTORHANDLER_H_ */ diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/15/209406a28fab001311dbfe770f133bca b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/15/209406a28fab001311dbfe770f133bca new file mode 100644 index 00000000..eb79e77c --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/15/209406a28fab001311dbfe770f133bca @@ -0,0 +1,148 @@ +/************************************************************************* + * ARCap + * Amshu Gongal, Kenan Kigunda + * February 18, 2014 + ************************************************************************** + * Description: * + * Prototype testing for infrared and mc. + **************************************************************************/ + +#include +#include "includes.h" +#include "altera_avalon_pio_regs.h" +#include "altera_avalon_uart_regs.h" +#include "sys/alt_irq.h" +#include "alt_types.h" +#include "altera_up_avalon_rs232.h" +#include "altera_up_avalon_rs232_regs.h" + +#include "MotorHandler.h" +#include "Status.h" + +/* Task stacks */ +#define TASK_STACKSIZE 2048 +OS_STK ir_task_stk[TASK_STACKSIZE]; +OS_STK mc_task_stk[TASK_STACKSIZE]; +/* Task priorities */ +#define IR_TASK_PRIORITY 2 +#define MC_TASK_PRIORITY 1 + + +#define SW_READ 1 +#define SW_WRITE 2 +#define WRITE_FIFO_EMPTY 0x80 +#define READ_FIFO_EMPTY 0x0 +OS_EVENT *SWQ; +OS_EVENT *RS232Q; +INT8U err; + + +/* Error status */ +#define OK 0 + +/* Message queues */ +#define WAIT_FOREVER 0 + +// ==== INFRARED ==== + +/* Infrared message queue */ +#define IR_MAX_MESSAGES 4 +int ir_messages[IR_MAX_MESSAGES]; +OS_EVENT *ir_queue; + +/* Infrared messages */ +// Together these avoid passing 0 to the queue (which is not allowed since queue messages cannot be null) +// and invert pushbutton input (since the pushbutton returns 0 when it is pushed down). +#define IR_QUEUE_SEND_BASE 1 // Use: IR_QUEUE_SEND_BASE + IORD +#define IR_QUEUE_RECEIVE_BASE 2 // Use: IR_QUEUE_RECEIVE_BASE - OSQPend + + +MotorHandler *motor= new MotorHandler(); + + +// ==== mc + +#define mc_GUARD_TIME 1 + +void mc_task(void *pdata) +{ + printf("mc task\n"); + printf("MotorHandler [init"); + if (motor->init() == OK) { + printf("]\n\n"); + motor->forward(); + } else { + printf( ", error]\n"); + } + while(1){ + motor->forward(); + OSTimeDlyHMSM(0, 0, 0, 100); + } +} + + + +// ==== GENERAL + +void queue_init() { + ir_queue = OSQCreate((void**)&ir_messages, IR_MAX_MESSAGES); +} + +/* The main function creates the LCD task, registers the edge counter polling interrupt, + * and starts the OS. */ +int main(void) +{ + int status = OK; + // Initialize components. + queue_init(); + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 0); + OSTimeDlyHMSM(0,0,0,100); + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 1); + // Create the mc task. + OSTaskCreateExt(mc_task, + NULL, + &mc_task_stk[TASK_STACKSIZE - 1], + MC_TASK_PRIORITY, + MC_TASK_PRIORITY, + mc_task_stk, + TASK_STACKSIZE, + NULL, + 0); + + if (status == OK) { + OSStart(); + } + + return 0; +} + +/****************************************************************************** + * * + * License Agreement * + * * + * Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * + * All rights reserved. * + * * + * Permission is hereby granted, free of charge, to any person obtaining a * + * copy of this software and associated documentation files (the "Software"), * + * to deal in the Software without restriction, including without limitation * + * the rights to use, copy, modify, merge, publish, distribute, sublicense, * + * and/or sell copies of the Software, and to permit persons to whom the * + * Software is furnished to do so, subject to the following conditions: * + * * + * The above copyright notice and this permission notice shall be included in * + * all copies or substantial portions of the Software. * + * * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * + * DEALINGS IN THE SOFTWARE. * + * * + * This agreement shall be governed in all respects by the laws of the State * + * of California and by the laws of the United States of America. * + * Altera does not recommend, suggest or require that this reference design * + * file be used in conjunction or combination with any other product. * + ******************************************************************************/ diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/17/80984a2087b000131eb0f6c547a05c39 b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/17/80984a2087b000131eb0f6c547a05c39 new file mode 100644 index 00000000..52f532d2 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/17/80984a2087b000131eb0f6c547a05c39 @@ -0,0 +1,121 @@ +/* + * MotorHandler.cpp + * + * Created on: 2014-03-03 + * Author: Amshu Gongal + */ + + +#include + +#include "altera_avalon_pio_regs.h" +#include "includes.h" +#include "system.h" + +#include "MotorHandler.h" + +#define WRITE_FIFO_EMPTY 0x80 +#define MOTOR_ENABLE 1 +#define MOTOR_RESET 0 + +// ALLOCATION +MotorHandler::MotorHandler() {} +MotorHandler::~MotorHandler() {} + + +// INITIALIZATION + +/* + * Initializes this handler. + * @return OK if the handler was initialized without error + */ +Status MotorHandler::init() { + // Enable the motor controller. + reset(); + // Open the serial device to send commands to the motor controller. + motor_dev = alt_up_rs232_open_dev(RS232_MOTOR_NAME); + //printf("%d", motor_dev); + if (motor_dev == NULL) { + return ERR_MOTOR_OPEN; + } else { + return OK; + } +} + +void MotorHandler::configure(){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_CHANGE_CONFIGURATION, "change configuration"); + send(0X01, "2 MOTOR CONFIG"); + printf("\n"); +} + +//Command Interpreter +/* + * Interprets the command from the network handler and sends move commands + * @param motor The motor to move eg. Left or Right + * @param motorDirection The direction of the given motor to move + * @param speed The speed the motor is to move + */ +void MotorHandler::motorCommand(string motor, string motorDirection, string speed){ + char motor = interpretMotor; +} + +char MotorHandler::interpretMotor(string motor){ + +} + +char MotorHandler::interpretDirection(string direction, int motor){ + +} + +// MOTOR CONTROL + +/*Moves the given motor in specified direction by Motor Direction with specified + * Speed + * @param MotorDirection Motor and direction to move + * @param Speed the speed to move at + * @param string description of motor movement + */ + +void MotorHandler::move(char MotorDirection,char Speed,char * Description){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_DEVICE_TYPE, "device"); + send(MotorDirection, Description); + send(Speed, "speed"); + printf("\n"); +} + +// MOTOR CONTROL HELPERS +/* + * Sends a byte-length message to the motor controller. + * @param message - the message to send + * @param description - the string description of the message, for debugging + */ +void MotorHandler::send(char message, char *description) { + alt_u32 write_space; + // Check for write space. + write_space = alt_up_rs232_get_available_space_in_write_FIFO(motor_dev); + if (write_space >= WRITE_FIFO_EMPTY) { + // If space, write. + int status = alt_up_rs232_write_data(motor_dev, message); + printf("MotorHandler [message: 0x%02x, description: %s", message, description); + // Log errors. + if (status == OK) { + printf("]\n"); + } else { + printf(", error: cannot write]\n"); + } + } else { + // If no space, wait and retry. + printf("MotorHandler [message: 0x%02x, description: %s, error: no write space; retrying]\n", message, description); + OSTimeDlyHMSM(0, 0, 0, 10); + send(message, description); + } +} + +void MotorHandler::reset(){ + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 0); + OSTimeDlyHMSM(0, 0, 0,200 ); + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 1); + OSTimeDlyHMSM(0, 0, 0, 200); +} diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/19/6014b7aa89b000131eb0f6c547a05c39 b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/19/6014b7aa89b000131eb0f6c547a05c39 new file mode 100644 index 00000000..71cc9613 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/19/6014b7aa89b000131eb0f6c547a05c39 @@ -0,0 +1,134 @@ +/* + * MotorHandler.cpp + * + * Created on: 2014-03-03 + * Author: Amshu Gongal + */ + + +#include + +#include "altera_avalon_pio_regs.h" +#include "includes.h" +#include "system.h" + +#include "MotorHandler.h" + +#define WRITE_FIFO_EMPTY 0x80 +#define MOTOR_ENABLE 1 +#define MOTOR_RESET 0 + +// ALLOCATION +MotorHandler::MotorHandler() {} +MotorHandler::~MotorHandler() {} + + +// INITIALIZATION + +/* + * Initializes this handler. + * @return OK if the handler was initialized without error + */ +Status MotorHandler::init() { + // Enable the motor controller. + reset(); + // Open the serial device to send commands to the motor controller. + motor_dev = alt_up_rs232_open_dev(RS232_MOTOR_NAME); + //printf("%d", motor_dev); + if (motor_dev == NULL) { + return ERR_MOTOR_OPEN; + } else { + return OK; + } +} + +void MotorHandler::configure(){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_CHANGE_CONFIGURATION, "change configuration"); + send(0X01, "2 MOTOR CONFIG"); + printf("\n"); +} + +//Command Interpreter +/* + * Interprets the command from the network handler and sends move commands + * @param motor The motor to move eg. Left or Right + * @param motorDirection The direction of the given motor to move + * @param speed The speed the motor is to move + */ +void MotorHandler::motorCommand(string motor, string motorDirection, string speed){ + char motorID = interpretMotor(motor); + char Direction = interpretDirection(motorDirection, int(motorID)); + int Speed = atol(speed); + move(Direction, Speed, "Move Motor"); +} + +char MotorHandler::interpretMotor(string motor){ + if(motor.compare(MOTOR_LEFT) == 0){ + return MOTOR_LEFT_CHAR; + } + else{ + return MOTOR_RIGHT_CHAR; + } +} + +char MotorHandler::interpretDirection(string direction, int motor){ + if(direction.compare(MOTOR_FORWARD) == 0){ + return (char) (motor*2 + 1); + } + else{ + return (char) (motor*2); + } +} + +// MOTOR CONTROL + +/*Moves the given motor in specified direction by Motor Direction with specified + * Speed + * @param MotorDirection Motor and direction to move + * @param Speed the speed to move at + * @param string description of motor movement + */ + +void MotorHandler::move(char MotorDirection,char Speed,char * Description){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_DEVICE_TYPE, "device"); + send(MotorDirection, Description); + send(Speed, "speed"); + printf("\n"); +} + +// MOTOR CONTROL HELPERS +/* + * Sends a byte-length message to the motor controller. + * @param message - the message to send + * @param description - the string description of the message, for debugging + */ +void MotorHandler::send(char message, char *description) { + alt_u32 write_space; + // Check for write space. + write_space = alt_up_rs232_get_available_space_in_write_FIFO(motor_dev); + if (write_space >= WRITE_FIFO_EMPTY) { + // If space, write. + int status = alt_up_rs232_write_data(motor_dev, message); + printf("MotorHandler [message: 0x%02x, description: %s", message, description); + // Log errors. + if (status == OK) { + printf("]\n"); + } else { + printf(", error: cannot write]\n"); + } + } else { + // If no space, wait and retry. + printf("MotorHandler [message: 0x%02x, description: %s, error: no write space; retrying]\n", message, description); + OSTimeDlyHMSM(0, 0, 0, 10); + send(message, description); + } +} + +void MotorHandler::reset(){ + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 0); + OSTimeDlyHMSM(0, 0, 0,200 ); + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 1); + OSTimeDlyHMSM(0, 0, 0, 200); +} diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/19/604849308faf0013110bf3236575307b b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/19/604849308faf0013110bf3236575307b new file mode 100644 index 00000000..5e7a6814 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/19/604849308faf0013110bf3236575307b @@ -0,0 +1,159 @@ +/************************************************************************* + * ARCap + * Amshu Gongal, Kenan Kigunda + * February 18, 2014 + ************************************************************************** + * Description: * + * Prototype testing for infrared and mc. + **************************************************************************/ + +#include +#include "includes.h" +#include "altera_avalon_pio_regs.h" +#include "altera_avalon_uart_regs.h" +#include "sys/alt_irq.h" +#include "alt_types.h" +#include "altera_up_avalon_rs232.h" +#include "altera_up_avalon_rs232_regs.h" + +#include "MotorHandler.h" +#include "Status.h" + +/* Task stacks */ +#define TASK_STACKSIZE 2048 +OS_STK ir_task_stk[TASK_STACKSIZE]; +OS_STK mc_task_stk[TASK_STACKSIZE]; +/* Task priorities */ +#define IR_TASK_PRIORITY 2 +#define MC_TASK_PRIORITY 1 + + +#define SW_READ 1 +#define SW_WRITE 2 +#define WRITE_FIFO_EMPTY 0x80 +#define READ_FIFO_EMPTY 0x0 +OS_EVENT *SWQ; +OS_EVENT *RS232Q; +INT8U err; + + +/* Error status */ +#define OK 0 + +/* Message queues */ +#define WAIT_FOREVER 0 + +// ==== INFRARED ==== + +/* Infrared message queue */ +#define IR_MAX_MESSAGES 4 +int ir_messages[IR_MAX_MESSAGES]; +OS_EVENT *ir_queue; + +/* Infrared messages */ +// Together these avoid passing 0 to the queue (which is not allowed since queue messages cannot be null) +// and invert pushbutton input (since the pushbutton returns 0 when it is pushed down). +#define IR_QUEUE_SEND_BASE 1 // Use: IR_QUEUE_SEND_BASE + IORD +#define IR_QUEUE_RECEIVE_BASE 2 // Use: IR_QUEUE_RECEIVE_BASE - OSQPend + + +MotorHandler *motor= new MotorHandler(); + + +// ==== mc + +#define mc_GUARD_TIME 1 + +void mc_task(void *pdata) +{ + printf("mc task\n"); + printf("MotorHandler [init"); + if (motor->init() == OK) { + printf("]\n\n"); + } else { + printf( ", error]\n"); + } + while(1){ + motor->forward(); +// OSTimeDlyHMSM(0, 0, 10, 0); +// motor->stop(); +// OSTimeDlyHMSM(0, 0, 3,0); +// motor->left(); +// OSTimeDlyHMSM(0, 0, 10, 0); +// motor->stop(); +// OSTimeDlyHMSM(0, 0, 3,0); +// motor->backward(); +// OSTimeDlyHMSM(0, 0, 10,0); +// motor->stop(); +// OSTimeDlyHMSM(0, 0, 3,0); +// motor->right(); +// OSTimeDlyHMSM(0, 0, 10,0); +// motor->stop(); +// OSTimeDlyHMSM(0, 0, 3,0); + + } +} + + + +// ==== GENERAL + +void queue_init() { + ir_queue = OSQCreate((void**)&ir_messages, IR_MAX_MESSAGES); +} + +/* The main function creates the LCD task, registers the edge counter polling interrupt, + * and starts the OS. */ +int main(void) +{ + int status = OK; + // Initialize components. + queue_init(); + // Create the mc task. + OSTaskCreateExt(mc_task, + NULL, + &mc_task_stk[TASK_STACKSIZE - 1], + MC_TASK_PRIORITY, + MC_TASK_PRIORITY, + mc_task_stk, + TASK_STACKSIZE, + NULL, + 0); + + if (status == OK) { + OSStart(); + } + + return 0; +} + +/****************************************************************************** + * * + * License Agreement * + * * + * Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * + * All rights reserved. * + * * + * Permission is hereby granted, free of charge, to any person obtaining a * + * copy of this software and associated documentation files (the "Software"), * + * to deal in the Software without restriction, including without limitation * + * the rights to use, copy, modify, merge, publish, distribute, sublicense, * + * and/or sell copies of the Software, and to permit persons to whom the * + * Software is furnished to do so, subject to the following conditions: * + * * + * The above copyright notice and this permission notice shall be included in * + * all copies or substantial portions of the Software. * + * * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * + * DEALINGS IN THE SOFTWARE. * + * * + * This agreement shall be governed in all respects by the laws of the State * + * of California and by the laws of the United States of America. * + * Altera does not recommend, suggest or require that this reference design * + * file be used in conjunction or combination with any other product. * + ******************************************************************************/ diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/1c/904774b1a8ab001311f2ce252b4696cb b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/1c/904774b1a8ab001311f2ce252b4696cb new file mode 100644 index 00000000..b62f2e1e --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/1c/904774b1a8ab001311f2ce252b4696cb @@ -0,0 +1,144 @@ +/************************************************************************* + * ARCap + * Amshu Gongal, Kenan Kigunda + * February 18, 2014 + ************************************************************************** + * Description: * + * Prototype testing for infrared and mc. + **************************************************************************/ + +#include +#include "includes.h" +#include "altera_avalon_pio_regs.h" +#include "altera_avalon_uart_regs.h" +#include "sys/alt_irq.h" +#include "alt_types.h" +#include "altera_up_avalon_rs232.h" +#include "altera_up_avalon_rs232_regs.h" + +#include "MotorHandler.h" +#include "Status.h" + +/* Task stacks */ +#define TASK_STACKSIZE 2048 +OS_STK ir_task_stk[TASK_STACKSIZE]; +OS_STK mc_task_stk[TASK_STACKSIZE]; +/* Task priorities */ +#define IR_TASK_PRIORITY 2 +#define MC_TASK_PRIORITY 1 + + +#define SW_READ 1 +#define SW_WRITE 2 +#define WRITE_FIFO_EMPTY 0x80 +#define READ_FIFO_EMPTY 0x0 +OS_EVENT *SWQ; +OS_EVENT *RS232Q; +INT8U err; + + +/* Error status */ +#define OK 0 + +/* Message queues */ +#define WAIT_FOREVER 0 + +// ==== INFRARED ==== + +/* Infrared message queue */ +#define IR_MAX_MESSAGES 4 +int ir_messages[IR_MAX_MESSAGES]; +OS_EVENT *ir_queue; + +/* Infrared messages */ +// Together these avoid passing 0 to the queue (which is not allowed since queue messages cannot be null) +// and invert pushbutton input (since the pushbutton returns 0 when it is pushed down). +#define IR_QUEUE_SEND_BASE 1 // Use: IR_QUEUE_SEND_BASE + IORD +#define IR_QUEUE_RECEIVE_BASE 2 // Use: IR_QUEUE_RECEIVE_BASE - OSQPend + + +MotorHandler *motor= new MotorHandler(); + + +// ==== mc + +#define mc_GUARD_TIME 1 + +void mc_task(void *pdata) +{ + printf("mc task\n"); + printf("MotorHandler [init"); + if (motor->init() == OK) { + printf("]\n\n"); + motor->forward(); + } else { + printf( ", error]\n"); + } + while(1){ + motor->forward(); + } +} + + + +// ==== GENERAL + +void queue_init() { + ir_queue = OSQCreate((void**)&ir_messages, IR_MAX_MESSAGES); +} + +/* The main function creates the LCD task, registers the edge counter polling interrupt, + * and starts the OS. */ +int main(void) +{ + int status = OK; + // Initialize components. + queue_init(); + // Create the mc task. + OSTaskCreateExt(mc_task, + NULL, + &mc_task_stk[TASK_STACKSIZE - 1], + MC_TASK_PRIORITY, + MC_TASK_PRIORITY, + mc_task_stk, + TASK_STACKSIZE, + NULL, + 0); + + if (status == OK) { + OSStart(); + } + + return 0; +} + +/****************************************************************************** + * * + * License Agreement * + * * + * Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * + * All rights reserved. * + * * + * Permission is hereby granted, free of charge, to any person obtaining a * + * copy of this software and associated documentation files (the "Software"), * + * to deal in the Software without restriction, including without limitation * + * the rights to use, copy, modify, merge, publish, distribute, sublicense, * + * and/or sell copies of the Software, and to permit persons to whom the * + * Software is furnished to do so, subject to the following conditions: * + * * + * The above copyright notice and this permission notice shall be included in * + * all copies or substantial portions of the Software. * + * * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * + * DEALINGS IN THE SOFTWARE. * + * * + * This agreement shall be governed in all respects by the laws of the State * + * of California and by the laws of the United States of America. * + * Altera does not recommend, suggest or require that this reference design * + * file be used in conjunction or combination with any other product. * + ******************************************************************************/ diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/1f/30273bcb84b000131eb0f6c547a05c39 b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/1f/30273bcb84b000131eb0f6c547a05c39 new file mode 100644 index 00000000..36ba0f4d --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/1f/30273bcb84b000131eb0f6c547a05c39 @@ -0,0 +1,67 @@ +/* + * MotorHandler.h + * + * Created on: 2014-03-03 + * Author: Amshu Gongal + */ + +#ifndef MOTORHANDLER_H_ +#define MOTORHANDLER_H_ + +#include "altera_up_avalon_rs232.h" +#include "altera_up_avalon_rs232_regs.h" +#include +using namespace std; +#include +#include "Status.h" +//Commands from network handler +#define MOTOR_LEFT "left" +#define MOTOR_RIGHT "right" +#define MOTOR_FORWARD "forward" +#define MOTOR_BACKWARD "backward" +// Motor messages are LSB first +#define MOTOR_START_BYTE 0x80 +#define MOTOR_DEVICE_TYPE 0x00 +#define MOTOR_LEFT_BACKWARD 0x04 // motor 1 backward +#define MOTOR_RIGHT_BACKWARD 0x06 // motor 2 backward +#define MOTOR_LEFT_FORWARD 0x05 // motor 1 forward +#define MOTOR_RIGHT_FORWARD 0x07 // motor 2 forward +#define MOTOR_CONST_SPEED 0x5F +#define MOTOR_STOP_SPEED 0x00 +#define MOTOR_CHANGE_CONFIGURATION 0X02 + +class MotorHandler { +public: + MotorHandler(); + virtual ~MotorHandler(); + + /* + * Initializes this handler. + * @return OK if the handler was initialized without error + */ + Status init(); + void reset(); + void configure(); + void motorCommand(string motor, string motorDirection, char); + +private: + /* The device used to send serial commands to the motor controller. */ + alt_up_rs232_dev *motor_dev; + + /* + * Moves in the given direction at constant speed. + * @param direction - the motor and direction to move in, e.g. MOTOR_MOTOR1_FORWARD + * @param speed speed of the motor + * @param description - the string description of the movement, for debugging + */ + void move(char direction, char speed, char *description); + + /* + * Sends a byte-length message to the motor controller. + * @param message - the message to send + * @param description - the string description of the message, for debugging + */ + void send(char message, char *description); +}; + +#endif /* MOTORHANDLER_H_ */ diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/21/0083b9ffcdab001312eeeea4d67ccb1b b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/21/0083b9ffcdab001312eeeea4d67ccb1b new file mode 100644 index 00000000..f0ea3902 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/21/0083b9ffcdab001312eeeea4d67ccb1b @@ -0,0 +1,148 @@ +/************************************************************************* + * ARCap + * Amshu Gongal, Kenan Kigunda + * February 18, 2014 + ************************************************************************** + * Description: * + * Prototype testing for infrared and mc. + **************************************************************************/ + +#include +#include "includes.h" +#include "altera_avalon_pio_regs.h" +#include "altera_avalon_uart_regs.h" +#include "sys/alt_irq.h" +#include "alt_types.h" +#include "altera_up_avalon_rs232.h" +#include "altera_up_avalon_rs232_regs.h" + +#include "MotorHandler.h" +#include "Status.h" + +/* Task stacks */ +#define TASK_STACKSIZE 2048 +OS_STK ir_task_stk[TASK_STACKSIZE]; +OS_STK mc_task_stk[TASK_STACKSIZE]; +/* Task priorities */ +#define IR_TASK_PRIORITY 2 +#define MC_TASK_PRIORITY 1 + + +#define SW_READ 1 +#define SW_WRITE 2 +#define WRITE_FIFO_EMPTY 0x80 +#define READ_FIFO_EMPTY 0x0 +OS_EVENT *SWQ; +OS_EVENT *RS232Q; +INT8U err; + + +/* Error status */ +#define OK 0 + +/* Message queues */ +#define WAIT_FOREVER 0 + +// ==== INFRARED ==== + +/* Infrared message queue */ +#define IR_MAX_MESSAGES 4 +int ir_messages[IR_MAX_MESSAGES]; +OS_EVENT *ir_queue; + +/* Infrared messages */ +// Together these avoid passing 0 to the queue (which is not allowed since queue messages cannot be null) +// and invert pushbutton input (since the pushbutton returns 0 when it is pushed down). +#define IR_QUEUE_SEND_BASE 1 // Use: IR_QUEUE_SEND_BASE + IORD +#define IR_QUEUE_RECEIVE_BASE 2 // Use: IR_QUEUE_RECEIVE_BASE - OSQPend + + +MotorHandler *motor= new MotorHandler(); + + +// ==== mc + +#define mc_GUARD_TIME 1 + +void mc_task(void *pdata) +{ + printf("mc task\n"); + printf("MotorHandler [init"); + if (motor->init() == OK) { + printf("]\n\n"); + motor->forward(); + } else { + printf( ", error]\n"); + } + while(1){ + motor->forward(); + OSTimeDlyHMSM(0, 0, 10, 0); + motor->stop(); + OSTimeDlyHMSM(0, 0, 3,0); + + } +} + + + +// ==== GENERAL + +void queue_init() { + ir_queue = OSQCreate((void**)&ir_messages, IR_MAX_MESSAGES); +} + +/* The main function creates the LCD task, registers the edge counter polling interrupt, + * and starts the OS. */ +int main(void) +{ + int status = OK; + // Initialize components. + queue_init(); + // Create the mc task. + OSTaskCreateExt(mc_task, + NULL, + &mc_task_stk[TASK_STACKSIZE - 1], + MC_TASK_PRIORITY, + MC_TASK_PRIORITY, + mc_task_stk, + TASK_STACKSIZE, + NULL, + 0); + + if (status == OK) { + OSStart(); + } + + return 0; +} + +/****************************************************************************** + * * + * License Agreement * + * * + * Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * + * All rights reserved. * + * * + * Permission is hereby granted, free of charge, to any person obtaining a * + * copy of this software and associated documentation files (the "Software"), * + * to deal in the Software without restriction, including without limitation * + * the rights to use, copy, modify, merge, publish, distribute, sublicense, * + * and/or sell copies of the Software, and to permit persons to whom the * + * Software is furnished to do so, subject to the following conditions: * + * * + * The above copyright notice and this permission notice shall be included in * + * all copies or substantial portions of the Software. * + * * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * + * DEALINGS IN THE SOFTWARE. * + * * + * This agreement shall be governed in all respects by the laws of the State * + * of California and by the laws of the United States of America. * + * Altera does not recommend, suggest or require that this reference design * + * file be used in conjunction or combination with any other product. * + ******************************************************************************/ diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/21/00c341948ab000131eb0f6c547a05c39 b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/21/00c341948ab000131eb0f6c547a05c39 new file mode 100644 index 00000000..d6879252 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/21/00c341948ab000131eb0f6c547a05c39 @@ -0,0 +1,136 @@ +/* + * MotorHandler.cpp + * + * Created on: 2014-03-03 + * Author: Amshu Gongal + */ + + +#include +#include + +#include "altera_avalon_pio_regs.h" +#include "includes.h" +#include "system.h" + +#include "MotorHandler.h" + +#define WRITE_FIFO_EMPTY 0x80 +#define MOTOR_ENABLE 1 +#define MOTOR_RESET 0 + +// ALLOCATION +MotorHandler::MotorHandler() {} +MotorHandler::~MotorHandler() {} + + +// INITIALIZATION + +/* + * Initializes this handler. + * @return OK if the handler was initialized without error + */ +Status MotorHandler::init() { + // Enable the motor controller. + reset(); + // Open the serial device to send commands to the motor controller. + motor_dev = alt_up_rs232_open_dev(RS232_MOTOR_NAME); + //printf("%d", motor_dev); + if (motor_dev == NULL) { + return ERR_MOTOR_OPEN; + } else { + return OK; + } +} + +void MotorHandler::configure(){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_CHANGE_CONFIGURATION, "change configuration"); + send(0X01, "2 MOTOR CONFIG"); + printf("\n"); +} + +//Command Interpreter +/* + * Interprets the command from the network handler and sends move commands + * @param motor The motor to move eg. Left or Right + * @param motorDirection The direction of the given motor to move + * @param speed The speed the motor is to move + */ +void MotorHandler::motorCommand(string motor, string motorDirection, string speed){ + char motorID = interpretMotor(motor); + char directionByte = interpretDirection(motorDirection, int(motorID)); + int speedByte = strtol(speed.c_str(), NULL, 0); + move(directionByte, speedByte, "Move Motor"); +} + + +char MotorHandler::interpretMotor(string motor){ + if(motor.compare(MOTOR_LEFT) == 0){ + return MOTOR_LEFT_CHAR; + } + else{ + return MOTOR_RIGHT_CHAR; + } +} + +char MotorHandler::interpretDirection(string direction, int motor){ + if(direction.compare(MOTOR_FORWARD) == 0){ + return (char) (motor*2 + 1); + } + else{ + return (char) (motor*2); + } +} + +// MOTOR CONTROL + +/*Moves the given motor in specified direction by Motor Direction with specified + * Speed + * @param MotorDirection Motor and direction to move + * @param Speed the speed to move at + * @param string description of motor movement + */ + +void MotorHandler::move(char motorDirection,char Speed,char * Description){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_DEVICE_TYPE, "device"); + send(motorDirection, Description); + send(Speed, "speed"); + printf("\n"); +} + +// MOTOR CONTROL HELPERS +/* + * Sends a byte-length message to the motor controller. + * @param message - the message to send + * @param description - the string description of the message, for debugging + */ +void MotorHandler::send(char message, char *description) { + alt_u32 write_space; + // Check for write space. + write_space = alt_up_rs232_get_available_space_in_write_FIFO(motor_dev); + if (write_space >= WRITE_FIFO_EMPTY) { + // If space, write. + int status = alt_up_rs232_write_data(motor_dev, message); + printf("MotorHandler [message: 0x%02x, description: %s", message, description); + // Log errors. + if (status == OK) { + printf("]\n"); + } else { + printf(", error: cannot write]\n"); + } + } else { + // If no space, wait and retry. + printf("MotorHandler [message: 0x%02x, description: %s, error: no write space; retrying]\n", message, description); + OSTimeDlyHMSM(0, 0, 0, 10); + send(message, description); + } +} + +void MotorHandler::reset(){ + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 0); + OSTimeDlyHMSM(0, 0, 0,200 ); + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 1); + OSTimeDlyHMSM(0, 0, 0, 200); +} diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/24/101f68e989b000131eb0f6c547a05c39 b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/24/101f68e989b000131eb0f6c547a05c39 new file mode 100644 index 00000000..17ed2323 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/24/101f68e989b000131eb0f6c547a05c39 @@ -0,0 +1,135 @@ +/* + * MotorHandler.cpp + * + * Created on: 2014-03-03 + * Author: Amshu Gongal + */ + + +#include +#include + +#include "altera_avalon_pio_regs.h" +#include "includes.h" +#include "system.h" + +#include "MotorHandler.h" + +#define WRITE_FIFO_EMPTY 0x80 +#define MOTOR_ENABLE 1 +#define MOTOR_RESET 0 + +// ALLOCATION +MotorHandler::MotorHandler() {} +MotorHandler::~MotorHandler() {} + + +// INITIALIZATION + +/* + * Initializes this handler. + * @return OK if the handler was initialized without error + */ +Status MotorHandler::init() { + // Enable the motor controller. + reset(); + // Open the serial device to send commands to the motor controller. + motor_dev = alt_up_rs232_open_dev(RS232_MOTOR_NAME); + //printf("%d", motor_dev); + if (motor_dev == NULL) { + return ERR_MOTOR_OPEN; + } else { + return OK; + } +} + +void MotorHandler::configure(){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_CHANGE_CONFIGURATION, "change configuration"); + send(0X01, "2 MOTOR CONFIG"); + printf("\n"); +} + +//Command Interpreter +/* + * Interprets the command from the network handler and sends move commands + * @param motor The motor to move eg. Left or Right + * @param motorDirection The direction of the given motor to move + * @param speed The speed the motor is to move + */ +void MotorHandler::motorCommand(string motor, string motorDirection, string speed){ + char motorID = interpretMotor(motor); + char directionByte = interpretDirection(motorDirection, int(motorID)); + int speedByte = speed.c_str() + move(directionByte, speedByte, "Move Motor"); +} + +char MotorHandler::interpretMotor(string motor){ + if(motor.compare(MOTOR_LEFT) == 0){ + return MOTOR_LEFT_CHAR; + } + else{ + return MOTOR_RIGHT_CHAR; + } +} + +char MotorHandler::interpretDirection(string direction, int motor){ + if(direction.compare(MOTOR_FORWARD) == 0){ + return (char) (motor*2 + 1); + } + else{ + return (char) (motor*2); + } +} + +// MOTOR CONTROL + +/*Moves the given motor in specified direction by Motor Direction with specified + * Speed + * @param MotorDirection Motor and direction to move + * @param Speed the speed to move at + * @param string description of motor movement + */ + +void MotorHandler::move(char MotorDirection,char Speed,char * Description){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_DEVICE_TYPE, "device"); + send(MotorDirection, Description); + send(Speed, "speed"); + printf("\n"); +} + +// MOTOR CONTROL HELPERS +/* + * Sends a byte-length message to the motor controller. + * @param message - the message to send + * @param description - the string description of the message, for debugging + */ +void MotorHandler::send(char message, char *description) { + alt_u32 write_space; + // Check for write space. + write_space = alt_up_rs232_get_available_space_in_write_FIFO(motor_dev); + if (write_space >= WRITE_FIFO_EMPTY) { + // If space, write. + int status = alt_up_rs232_write_data(motor_dev, message); + printf("MotorHandler [message: 0x%02x, description: %s", message, description); + // Log errors. + if (status == OK) { + printf("]\n"); + } else { + printf(", error: cannot write]\n"); + } + } else { + // If no space, wait and retry. + printf("MotorHandler [message: 0x%02x, description: %s, error: no write space; retrying]\n", message, description); + OSTimeDlyHMSM(0, 0, 0, 10); + send(message, description); + } +} + +void MotorHandler::reset(){ + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 0); + OSTimeDlyHMSM(0, 0, 0,200 ); + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 1); + OSTimeDlyHMSM(0, 0, 0, 200); +} diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/2b/7016b1fa87b000131eb0f6c547a05c39 b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/2b/7016b1fa87b000131eb0f6c547a05c39 new file mode 100644 index 00000000..b7d23ebd --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/2b/7016b1fa87b000131eb0f6c547a05c39 @@ -0,0 +1,126 @@ +/* + * MotorHandler.cpp + * + * Created on: 2014-03-03 + * Author: Amshu Gongal + */ + + +#include + +#include "altera_avalon_pio_regs.h" +#include "includes.h" +#include "system.h" + +#include "MotorHandler.h" + +#define WRITE_FIFO_EMPTY 0x80 +#define MOTOR_ENABLE 1 +#define MOTOR_RESET 0 + +// ALLOCATION +MotorHandler::MotorHandler() {} +MotorHandler::~MotorHandler() {} + + +// INITIALIZATION + +/* + * Initializes this handler. + * @return OK if the handler was initialized without error + */ +Status MotorHandler::init() { + // Enable the motor controller. + reset(); + // Open the serial device to send commands to the motor controller. + motor_dev = alt_up_rs232_open_dev(RS232_MOTOR_NAME); + //printf("%d", motor_dev); + if (motor_dev == NULL) { + return ERR_MOTOR_OPEN; + } else { + return OK; + } +} + +void MotorHandler::configure(){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_CHANGE_CONFIGURATION, "change configuration"); + send(0X01, "2 MOTOR CONFIG"); + printf("\n"); +} + +//Command Interpreter +/* + * Interprets the command from the network handler and sends move commands + * @param motor The motor to move eg. Left or Right + * @param motorDirection The direction of the given motor to move + * @param speed The speed the motor is to move + */ +void MotorHandler::motorCommand(string motor, string motorDirection, string speed){ + char motorID = interpretMotor(motor); + char Direction = interpretDirection(motorDirection, int(motorID)); +} + +char MotorHandler::interpretMotor(string motor){ + if(motor.compare(MOTOR_LEFT) == 0){ + return MOTOR_LEFT_CHAR; + } + else + return MOTOR_RIGHT_CHAR; +} + +char MotorHandler::interpretDirection(string direction, int motor){ + +} + +// MOTOR CONTROL + +/*Moves the given motor in specified direction by Motor Direction with specified + * Speed + * @param MotorDirection Motor and direction to move + * @param Speed the speed to move at + * @param string description of motor movement + */ + +void MotorHandler::move(char MotorDirection,char Speed,char * Description){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_DEVICE_TYPE, "device"); + send(MotorDirection, Description); + send(Speed, "speed"); + printf("\n"); +} + +// MOTOR CONTROL HELPERS +/* + * Sends a byte-length message to the motor controller. + * @param message - the message to send + * @param description - the string description of the message, for debugging + */ +void MotorHandler::send(char message, char *description) { + alt_u32 write_space; + // Check for write space. + write_space = alt_up_rs232_get_available_space_in_write_FIFO(motor_dev); + if (write_space >= WRITE_FIFO_EMPTY) { + // If space, write. + int status = alt_up_rs232_write_data(motor_dev, message); + printf("MotorHandler [message: 0x%02x, description: %s", message, description); + // Log errors. + if (status == OK) { + printf("]\n"); + } else { + printf(", error: cannot write]\n"); + } + } else { + // If no space, wait and retry. + printf("MotorHandler [message: 0x%02x, description: %s, error: no write space; retrying]\n", message, description); + OSTimeDlyHMSM(0, 0, 0, 10); + send(message, description); + } +} + +void MotorHandler::reset(){ + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 0); + OSTimeDlyHMSM(0, 0, 0,200 ); + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 1); + OSTimeDlyHMSM(0, 0, 0, 200); +} diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/2d/8042f23d86b000131eb0f6c547a05c39 b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/2d/8042f23d86b000131eb0f6c547a05c39 new file mode 100644 index 00000000..a940b7ba --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/2d/8042f23d86b000131eb0f6c547a05c39 @@ -0,0 +1,70 @@ +/* + * MotorHandler.h + * + * Created on: 2014-03-03 + * Author: Amshu Gongal + */ + +#ifndef MOTORHANDLER_H_ +#define MOTORHANDLER_H_ + +#include "altera_up_avalon_rs232.h" +#include "altera_up_avalon_rs232_regs.h" +#include +using namespace std; +#include +#include "Status.h" + +//Commands from network handler +#define MOTOR_LEFT "left" +#define MOTOR_RIGHT "right" +#define MOTOR_FORWARD "forward" +#define MOTOR_BACKWARD "backward" + + +// Motor messages are LSB first +#define MOTOR_START_BYTE 0x80 +#define MOTOR_DEVICE_TYPE 0x00 +#define MOTOR_LEFT_BACKWARD 0x04 // motor 1 backward +#define MOTOR_RIGHT_BACKWARD 0x06 // motor 2 backward +#define MOTOR_LEFT_FORWARD 0x05 // motor 1 forward +#define MOTOR_RIGHT_FORWARD 0x07 // motor 2 forward +#define MOTOR_CONST_SPEED 0x5F +#define MOTOR_STOP_SPEED 0x00 +#define MOTOR_CHANGE_CONFIGURATION 0X02 + +class MotorHandler { +public: + MotorHandler(); + virtual ~MotorHandler(); + + /* + * Initializes this handler. + * @return OK if the handler was initialized without error + */ + Status init(); + void reset(); + void configure(); + void motorCommand(string motor, string motorDirection, char); + +private: + /* The device used to send serial commands to the motor controller. */ + alt_up_rs232_dev *motor_dev; + + /* + * Moves in the given direction at constant speed. + * @param direction - the motor and direction to move in, e.g. MOTOR_MOTOR1_FORWARD + * @param speed speed of the motor + * @param description - the string description of the movement, for debugging + */ + void move(char direction, char speed, char *description); + + /* + * Sends a byte-length message to the motor controller. + * @param message - the message to send + * @param description - the string description of the message, for debugging + */ + void send(char message, char *description); +}; + +#endif /* MOTORHANDLER_H_ */ diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/2d/908d65f7a8ab001311f2ce252b4696cb b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/2d/908d65f7a8ab001311f2ce252b4696cb new file mode 100644 index 00000000..57a7749b --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/2d/908d65f7a8ab001311f2ce252b4696cb @@ -0,0 +1,152 @@ +/************************************************************************* + * ARCap + * Amshu Gongal, Kenan Kigunda + * February 18, 2014 + ************************************************************************** + * Description: * + * Prototype testing for infrared and mc. + **************************************************************************/ + +#include +#include "includes.h" +#include "altera_avalon_pio_regs.h" +#include "altera_avalon_uart_regs.h" +#include "sys/alt_irq.h" +#include "alt_types.h" +#include "altera_up_avalon_rs232.h" +#include "altera_up_avalon_rs232_regs.h" + +#include "MotorHandler.h" +#include "Status.h" + +/* Task stacks */ +#define TASK_STACKSIZE 2048 +OS_STK ir_task_stk[TASK_STACKSIZE]; +OS_STK mc_task_stk[TASK_STACKSIZE]; +/* Task priorities */ +#define IR_TASK_PRIORITY 2 +#define MC_TASK_PRIORITY 1 + + +#define SW_READ 1 +#define SW_WRITE 2 +#define WRITE_FIFO_EMPTY 0x80 +#define READ_FIFO_EMPTY 0x0 +OS_EVENT *SWQ; +OS_EVENT *RS232Q; +INT8U err; + + +/* Error status */ +#define OK 0 + +/* Message queues */ +#define WAIT_FOREVER 0 + +// ==== INFRARED ==== + +/* Infrared message queue */ +#define IR_MAX_MESSAGES 4 +int ir_messages[IR_MAX_MESSAGES]; +OS_EVENT *ir_queue; + +/* Infrared messages */ +// Together these avoid passing 0 to the queue (which is not allowed since queue messages cannot be null) +// and invert pushbutton input (since the pushbutton returns 0 when it is pushed down). +#define IR_QUEUE_SEND_BASE 1 // Use: IR_QUEUE_SEND_BASE + IORD +#define IR_QUEUE_RECEIVE_BASE 2 // Use: IR_QUEUE_RECEIVE_BASE - OSQPend + + +MotorHandler *motor= new MotorHandler(); + + +// ==== mc + +#define mc_GUARD_TIME 1 + +void mc_task(void *pdata) +{ + printf("mc task\n"); + printf("MotorHandler [init"); + if (motor->init() == OK) { + printf("]\n\n"); + motor->forward(); + } else { + printf( ", error]\n"); + } + while(1){ + motor->forward(); + OSTimeDlyHMSM(0, 0, 2,0 ); + motor->backward(); + OSTimeDlyHMSM(0, 0, 2,0 ); + motor->left(); + OSTimeDlyHMSM(0, 0, 2,0 ); + motor->right(); + OSTimeDlyHMSM(0, 0, 2,0 ); + + } +} + + + +// ==== GENERAL + +void queue_init() { + ir_queue = OSQCreate((void**)&ir_messages, IR_MAX_MESSAGES); +} + +/* The main function creates the LCD task, registers the edge counter polling interrupt, + * and starts the OS. */ +int main(void) +{ + int status = OK; + // Initialize components. + queue_init(); + // Create the mc task. + OSTaskCreateExt(mc_task, + NULL, + &mc_task_stk[TASK_STACKSIZE - 1], + MC_TASK_PRIORITY, + MC_TASK_PRIORITY, + mc_task_stk, + TASK_STACKSIZE, + NULL, + 0); + + if (status == OK) { + OSStart(); + } + + return 0; +} + +/****************************************************************************** + * * + * License Agreement * + * * + * Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * + * All rights reserved. * + * * + * Permission is hereby granted, free of charge, to any person obtaining a * + * copy of this software and associated documentation files (the "Software"), * + * to deal in the Software without restriction, including without limitation * + * the rights to use, copy, modify, merge, publish, distribute, sublicense, * + * and/or sell copies of the Software, and to permit persons to whom the * + * Software is furnished to do so, subject to the following conditions: * + * * + * The above copyright notice and this permission notice shall be included in * + * all copies or substantial portions of the Software. * + * * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * + * DEALINGS IN THE SOFTWARE. * + * * + * This agreement shall be governed in all respects by the laws of the State * + * of California and by the laws of the United States of America. * + * Altera does not recommend, suggest or require that this reference design * + * file be used in conjunction or combination with any other product. * + ******************************************************************************/ diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/2f/200a2c798bab001311dbfe770f133bca b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/2f/200a2c798bab001311dbfe770f133bca new file mode 100644 index 00000000..1098a755 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/2f/200a2c798bab001311dbfe770f133bca @@ -0,0 +1,74 @@ +/* + * MotorHandler.h + * + * Created on: 2014-03-03 + * Author: Amshu Gongal + */ + +#ifndef MOTORHANDLER_H_ +#define MOTORHANDLER_H_ + +#include "altera_up_avalon_rs232.h" +#include "altera_up_avalon_rs232_regs.h" +#include +#include "Status.h" + +// Motor messages are LSB first +#define MOTOR_START_BYTE 0x80 +#define MOTOR_DEVICE_TYPE 0x00 +#define MOTOR_MOTOR1_BACKWARD 0x40 // motor 1 backward +#define MOTOR_MOTOR2_BACKWARD 0x60 // motor 2 backward +#define MOTOR_MOTOR1_FORWARD 0x05 // motor 1 forward +#define MOTOR_MOTOR2_FORWARD 0x07 // motor 2 forward +#define MOTOR_CONST_SPEED 0x5F +#define MOTOR_STOP_SPEED 0x00 +#define MOTOR_CHANGE_CONFIGURATION 0X02 + +class MotorHandler { +public: + MotorHandler(); + virtual ~MotorHandler(); + + /* + * Initializes this handler. + * @return OK if the handler was initialized without error + */ + Status init(); + + void forward(); + void backward(); + void right(); + void left(); + void stop(); + void configure(); + void test(); + void reset(); + +private: + /* The device used to send serial commands to the motor controller. */ + alt_up_rs232_dev *motor_dev; + + /* + * Moves in the given direction at constant speed. + * @param direction - the motor and direction to move in, e.g. MOTOR_MOTOR1_FORWARD + * @param description - the string description of the movement, for debugging + */ + void move(char direction, char *description); + + /* + * Moves in the given direction and speed. + * @param direction - the motor and direction to move in, e.g. MOTOR_MOTOR1_FORWARD + * @param speed - the speed to move at, i.e. MOTOR_CONST_SPEED or MOTOR_STOP_SPEED + * @param description - the string description of the movement, for debugging + */ + void move(char direction, char speed, char *description); + + /* + * Sends a byte-length message to the motor controller. + * @param message - the message to send + * @param description - the string description of the message, for debugging + */ + void send(char message, char *description); +}; + +#endif /* MOTORHANDLER_H_ */ diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/2f/d053080980b000131eb0f6c547a05c39 b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/2f/d053080980b000131eb0f6c547a05c39 new file mode 100644 index 00000000..1feadc9a --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/2f/d053080980b000131eb0f6c547a05c39 @@ -0,0 +1,141 @@ +/* + * MotorHandler.cpp + * + * Created on: 2014-03-03 + * Author: Amshu Gongal + */ + + +#include + +#include "altera_avalon_pio_regs.h" +#include "includes.h" +#include "system.h" + +#include "MotorHandler.h" + +#define WRITE_FIFO_EMPTY 0x80 +#define MOTOR_ENABLE 1 +#define MOTOR_RESET 0 + +// ALLOCATION +MotorHandler::MotorHandler() {} +MotorHandler::~MotorHandler() {} + + + + +// INITIALIZATION + +/* + * Initializes this handler. + * @return OK if the handler was initialized without error + */ +Status MotorHandler::init() { + // Enable the motor controller. + reset(); + // Open the serial device to send commands to the motor controller. + motor_dev = alt_up_rs232_open_dev(RS232_MOTOR_NAME); + //printf("%d", motor_dev); + if (motor_dev == NULL) { + return ERR_MOTOR_OPEN; + } else { + return OK; + } +} + +void MotorHandler::configure(){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_CHANGE_CONFIGURATION, "change configuration"); + send(0X01, "2 MOTOR CONFIG"); + printf("\n"); +} +// TESTING + +void MotorHandler::test() { + send(MOTOR_START_BYTE, "test start"); +} + +// MOTOR CONTROL + +/* + * Move rover forward by activating both motors. + */ +void MotorHandler::forward() { + move(MOTOR_BOTH_FORWARD, "motor both forward"); + //move(MOTOR_MOTOR2_FORWARD, "motor 2 forward"); +} + +/* + * Move rover backward by activating both motor backwards. + */ +void MotorHandler::backward() { + move(MOTOR_BOTH_BACKWARD, "motor both backward"); + // move(MOTOR_MOTOR2_BACKWARD, "motor 2 backward"); +} + +/* + * Turn rover left. + */ +void MotorHandler::left() { + move(MOTOR_MOTOR1_FORWARD, "motor 1 forward"); +} + +/* + * Turn rover right. + */ +void MotorHandler::right() { + move(MOTOR_MOTOR2_FORWARD, "motor 2 forward"); +} + +/* + * Stop the rover. + */ +void MotorHandler::stop() { + move(MOTOR_MOTOR1_FORWARD, MOTOR_STOP_SPEED, "motor 1 stop"); + move(MOTOR_MOTOR2_FORWARD, MOTOR_STOP_SPEED, "motor 2 stop"); +} + +// MOTOR CONTROL HELPERS + + +void MotorHandler::move(MotorDirection, Speed, Description){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_DEVICE_TYPE, "device"); + send(MotorDirection, Description); + send(Speed, "speed"); + printf("\n"); +} +/* + * Sends a byte-length message to the motor controller. + * @param message - the message to send + * @param description - the string description of the message, for debugging + */ +void MotorHandler::send(char message, char *description) { + alt_u32 write_space; + // Check for write space. + write_space = alt_up_rs232_get_available_space_in_write_FIFO(motor_dev); + if (write_space >= WRITE_FIFO_EMPTY) { + // If space, write. + int status = alt_up_rs232_write_data(motor_dev, message); + printf("MotorHandler [message: 0x%02x, description: %s", message, description); + // Log errors. + if (status == OK) { + printf("]\n"); + } else { + printf(", error: cannot write]\n"); + } + } else { + // If no space, wait and retry. + printf("MotorHandler [message: 0x%02x, description: %s, error: no write space; retrying]\n", message, description); + OSTimeDlyHMSM(0, 0, 0, 10); + send(message, description); + } +} + +void MotorHandler::reset(){ + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 0); + OSTimeDlyHMSM(0, 0, 0,200 ); + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 1); + OSTimeDlyHMSM(0, 0, 0, 200); +} diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/32/802b4cdd8aab001311dbfe770f133bca b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/32/802b4cdd8aab001311dbfe770f133bca new file mode 100644 index 00000000..c579c551 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/32/802b4cdd8aab001311dbfe770f133bca @@ -0,0 +1,153 @@ +/* + * MotorHandler.cpp + * + * Created on: 2014-03-03 + * Author: Amshu Gongal + */ + + +#include + +#include "altera_avalon_pio_regs.h" +#include "includes.h" +#include "system.h" + +#include "MotorHandler.h" + +#define WRITE_FIFO_EMPTY 0x80 +#define MOTOR_ENABLE 1 +#define MOTOR_RESET 0 + +// ALLOCATION +MotorHandler::MotorHandler() {} +MotorHandler::~MotorHandler() {} + +// INITIALIZATION + +/* + * Initializes this handler. + * @return OK if the handler was initialized without error + */ +Status MotorHandler::init() { + // Enable the motor controller. + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, MOTOR_ENABLE); + // Open the serial device to send commands to the motor controller. + motor_dev = alt_up_rs232_open_dev(RS232_MOTOR_NAME); + //printf("%d", motor_dev); + if (motor_dev == NULL) { + return ERR_MOTOR_OPEN; + } else { + return OK; + } +} + +void MotorHandler::configure(){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_CHANGE_CONFIGURATION, "change configuration"); + send(0X01, "2 MOTOR CONFIG"); + printf("\n"); +} +// TESTING + +void MotorHandler::test() { + send(MOTOR_START_BYTE, "test start"); +} + +// MOTOR CONTROL + +/* + * Move rover forward by activating both motors. + */ +void MotorHandler::forward() { + move(MOTOR_MOTOR1_FORWARD, "motor 1 forward"); + move(MOTOR_MOTOR2_FORWARD, "motor 2 forward"); +} + +/* + * Move rover backward by activating both motor backwards. + */ +void MotorHandler::backward() { + move(MOTOR_MOTOR1_BACKWARD, "motor 1 backward"); + move(MOTOR_MOTOR2_BACKWARD, "motor 2 backward"); +} + +/* + * Turn rover left. + */ +void MotorHandler::left() { + move(MOTOR_MOTOR2_FORWARD, "motor 1 forward"); +} + +/* + * Turn rover right. + */ +void MotorHandler::right() { + move(MOTOR_MOTOR2_FORWARD, "motor 2 forward"); +} + +/* + * Stop the rover. + */ +void MotorHandler::stop() { + move(MOTOR_MOTOR1_FORWARD, MOTOR_STOP_SPEED, "motor 1 stop"); + move(MOTOR_MOTOR2_FORWARD, MOTOR_STOP_SPEED, "motor 2 stop"); +} + +// MOTOR CONTROL HELPERS + +/* + * Moves in the given direction at constant speed. + * @param direction - the motor and direction to move in, e.g. MOTOR_MOTOR1_FORWARD + * @param description - the string description of the movement, for debugging + */ +void MotorHandler::move(char direction, char *description) { + move(direction, MOTOR_CONST_SPEED, description); +} + +/* + * Moves in the given direction and speed. + * @param direction - the motor and direction to move in, e.g. MOTOR_MOTOR1_FORWARD + * @param speed - the speed to move at, i.e. MOTOR_CONST_SPEED or MOTOR_STOP_SPEED + * @param description - the string description of the movement, for debugging + */ +void MotorHandler::move(char direction, char speed, char *description) { + send(MOTOR_START_BYTE, "start"); + send(MOTOR_DEVICE_TYPE, "device"); + send(direction, description); + send(speed, "speed"); + printf("\n"); +} + +/* + * Sends a byte-length message to the motor controller. + * @param message - the message to send + * @param description - the string description of the message, for debugging + */ +void MotorHandler::send(char message, char *description) { + alt_u32 write_space; + // Check for write space. + write_space = alt_up_rs232_get_available_space_in_write_FIFO(motor_dev); + if (write_space >= WRITE_FIFO_EMPTY) { + // If space, write. + int status = alt_up_rs232_write_data(motor_dev, message); + printf("MotorHandler [message: 0x%02x, description: %s", message, description); + // Log errors. + if (status == OK) { + printf("]\n"); + } else { + printf(", error: cannot write]\n"); + } + } else { + // If no space, wait and retry. + printf("MotorHandler [message: 0x%02x, description: %s, error: no write space; retrying]\n", message, description); + OSTimeDlyHMSM(0, 0, 0, 10); + send(message, description); + } +} + +void MotorHandler::reset(){ +// IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 0); +// OSTimeDlyHMSM(0, 0, 0, 100); + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 1); + OSTimeDlyHMSM(0, 0, 0, 100); +} diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/39/20587dfe8eab001311dbfe770f133bca b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/39/20587dfe8eab001311dbfe770f133bca new file mode 100644 index 00000000..c306ca4b --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/39/20587dfe8eab001311dbfe770f133bca @@ -0,0 +1,143 @@ +/************************************************************************* + * ARCap + * Amshu Gongal, Kenan Kigunda + * February 18, 2014 + ************************************************************************** + * Description: * + * Prototype testing for infrared and mc. + **************************************************************************/ + +#include +#include "includes.h" +#include "altera_avalon_pio_regs.h" +#include "altera_avalon_uart_regs.h" +#include "sys/alt_irq.h" +#include "alt_types.h" +#include "altera_up_avalon_rs232.h" +#include "altera_up_avalon_rs232_regs.h" + +#include "MotorHandler.h" +#include "Status.h" + +/* Task stacks */ +#define TASK_STACKSIZE 2048 +OS_STK ir_task_stk[TASK_STACKSIZE]; +OS_STK mc_task_stk[TASK_STACKSIZE]; +/* Task priorities */ +#define IR_TASK_PRIORITY 2 +#define MC_TASK_PRIORITY 1 + + +#define SW_READ 1 +#define SW_WRITE 2 +#define WRITE_FIFO_EMPTY 0x80 +#define READ_FIFO_EMPTY 0x0 +OS_EVENT *SWQ; +OS_EVENT *RS232Q; +INT8U err; + + +/* Error status */ +#define OK 0 + +/* Message queues */ +#define WAIT_FOREVER 0 + +// ==== INFRARED ==== + +/* Infrared message queue */ +#define IR_MAX_MESSAGES 4 +int ir_messages[IR_MAX_MESSAGES]; +OS_EVENT *ir_queue; + +/* Infrared messages */ +// Together these avoid passing 0 to the queue (which is not allowed since queue messages cannot be null) +// and invert pushbutton input (since the pushbutton returns 0 when it is pushed down). +#define IR_QUEUE_SEND_BASE 1 // Use: IR_QUEUE_SEND_BASE + IORD +#define IR_QUEUE_RECEIVE_BASE 2 // Use: IR_QUEUE_RECEIVE_BASE - OSQPend + + +MotorHandler *motor= new MotorHandler(); + + +// ==== mc + +#define mc_GUARD_TIME 1 + +void mc_task(void *pdata) +{ + printf("mc task\n"); + printf("MotorHandler [init"); + if (motor->init() == OK) { + printf("]\n\n"); + motor->forward(); + } else { + printf( ", error]\n"); + } + motor->forward(); +} + + + +// ==== GENERAL + +void queue_init() { + ir_queue = OSQCreate((void**)&ir_messages, IR_MAX_MESSAGES); +} + +/* The main function creates the LCD task, registers the edge counter polling interrupt, + * and starts the OS. */ +int main(void) +{ + int status = OK; + // Initialize components. + queue_init(); + motor->reset(); + // Create the mc task. + OSTaskCreateExt(mc_task, + NULL, + &mc_task_stk[TASK_STACKSIZE - 1], + MC_TASK_PRIORITY, + MC_TASK_PRIORITY, + mc_task_stk, + TASK_STACKSIZE, + NULL, + 0); + + if (status == OK) { + OSStart(); + } + + return 0; +} + +/****************************************************************************** + * * + * License Agreement * + * * + * Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * + * All rights reserved. * + * * + * Permission is hereby granted, free of charge, to any person obtaining a * + * copy of this software and associated documentation files (the "Software"), * + * to deal in the Software without restriction, including without limitation * + * the rights to use, copy, modify, merge, publish, distribute, sublicense, * + * and/or sell copies of the Software, and to permit persons to whom the * + * Software is furnished to do so, subject to the following conditions: * + * * + * The above copyright notice and this permission notice shall be included in * + * all copies or substantial portions of the Software. * + * * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * + * DEALINGS IN THE SOFTWARE. * + * * + * This agreement shall be governed in all respects by the laws of the State * + * of California and by the laws of the United States of America. * + * Altera does not recommend, suggest or require that this reference design * + * file be used in conjunction or combination with any other product. * + ******************************************************************************/ diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/3a/40cb6d9eb6ab00131274ac4b6fee418c b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/3a/40cb6d9eb6ab00131274ac4b6fee418c new file mode 100644 index 00000000..f5a8981b --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/3a/40cb6d9eb6ab00131274ac4b6fee418c @@ -0,0 +1,145 @@ +/************************************************************************* + * ARCap + * Amshu Gongal, Kenan Kigunda + * February 18, 2014 + ************************************************************************** + * Description: * + * Prototype testing for infrared and mc. + **************************************************************************/ + +#include +#include "includes.h" +#include "altera_avalon_pio_regs.h" +#include "altera_avalon_uart_regs.h" +#include "sys/alt_irq.h" +#include "alt_types.h" +#include "altera_up_avalon_rs232.h" +#include "altera_up_avalon_rs232_regs.h" + +#include "MotorHandler.h" +#include "Status.h" + +/* Task stacks */ +#define TASK_STACKSIZE 2048 +OS_STK ir_task_stk[TASK_STACKSIZE]; +OS_STK mc_task_stk[TASK_STACKSIZE]; +/* Task priorities */ +#define IR_TASK_PRIORITY 2 +#define MC_TASK_PRIORITY 1 + + +#define SW_READ 1 +#define SW_WRITE 2 +#define WRITE_FIFO_EMPTY 0x80 +#define READ_FIFO_EMPTY 0x0 +OS_EVENT *SWQ; +OS_EVENT *RS232Q; +INT8U err; + + +/* Error status */ +#define OK 0 + +/* Message queues */ +#define WAIT_FOREVER 0 + +// ==== INFRARED ==== + +/* Infrared message queue */ +#define IR_MAX_MESSAGES 4 +int ir_messages[IR_MAX_MESSAGES]; +OS_EVENT *ir_queue; + +/* Infrared messages */ +// Together these avoid passing 0 to the queue (which is not allowed since queue messages cannot be null) +// and invert pushbutton input (since the pushbutton returns 0 when it is pushed down). +#define IR_QUEUE_SEND_BASE 1 // Use: IR_QUEUE_SEND_BASE + IORD +#define IR_QUEUE_RECEIVE_BASE 2 // Use: IR_QUEUE_RECEIVE_BASE - OSQPend + + +MotorHandler *motor= new MotorHandler(); + + +// ==== mc + +#define mc_GUARD_TIME 1 + +void mc_task(void *pdata) +{ + printf("mc task\n"); + printf("MotorHandler [init"); + if (motor->init() == OK) { + printf("]\n\n"); + motor->right(); + } else { + printf( ", error]\n"); + } + while(1){ + motor->right(); + + } +} + + + +// ==== GENERAL + +void queue_init() { + ir_queue = OSQCreate((void**)&ir_messages, IR_MAX_MESSAGES); +} + +/* The main function creates the LCD task, registers the edge counter polling interrupt, + * and starts the OS. */ +int main(void) +{ + int status = OK; + // Initialize components. + queue_init(); + // Create the mc task. + OSTaskCreateExt(mc_task, + NULL, + &mc_task_stk[TASK_STACKSIZE - 1], + MC_TASK_PRIORITY, + MC_TASK_PRIORITY, + mc_task_stk, + TASK_STACKSIZE, + NULL, + 0); + + if (status == OK) { + OSStart(); + } + + return 0; +} + +/****************************************************************************** + * * + * License Agreement * + * * + * Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * + * All rights reserved. * + * * + * Permission is hereby granted, free of charge, to any person obtaining a * + * copy of this software and associated documentation files (the "Software"), * + * to deal in the Software without restriction, including without limitation * + * the rights to use, copy, modify, merge, publish, distribute, sublicense, * + * and/or sell copies of the Software, and to permit persons to whom the * + * Software is furnished to do so, subject to the following conditions: * + * * + * The above copyright notice and this permission notice shall be included in * + * all copies or substantial portions of the Software. * + * * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * + * DEALINGS IN THE SOFTWARE. * + * * + * This agreement shall be governed in all respects by the laws of the State * + * of California and by the laws of the United States of America. * + * Altera does not recommend, suggest or require that this reference design * + * file be used in conjunction or combination with any other product. * + ******************************************************************************/ diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/3b/90912189acab001311f2ce252b4696cb b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/3b/90912189acab001311f2ce252b4696cb new file mode 100644 index 00000000..3eb6a12c --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/3b/90912189acab001311f2ce252b4696cb @@ -0,0 +1,151 @@ +/************************************************************************* + * ARCap + * Amshu Gongal, Kenan Kigunda + * February 18, 2014 + ************************************************************************** + * Description: * + * Prototype testing for infrared and mc. + **************************************************************************/ + +#include +#include "includes.h" +#include "altera_avalon_pio_regs.h" +#include "altera_avalon_uart_regs.h" +#include "sys/alt_irq.h" +#include "alt_types.h" +#include "altera_up_avalon_rs232.h" +#include "altera_up_avalon_rs232_regs.h" + +#include "MotorHandler.h" +#include "Status.h" + +/* Task stacks */ +#define TASK_STACKSIZE 2048 +OS_STK ir_task_stk[TASK_STACKSIZE]; +OS_STK mc_task_stk[TASK_STACKSIZE]; +/* Task priorities */ +#define IR_TASK_PRIORITY 2 +#define MC_TASK_PRIORITY 1 + + +#define SW_READ 1 +#define SW_WRITE 2 +#define WRITE_FIFO_EMPTY 0x80 +#define READ_FIFO_EMPTY 0x0 +OS_EVENT *SWQ; +OS_EVENT *RS232Q; +INT8U err; + + +/* Error status */ +#define OK 0 + +/* Message queues */ +#define WAIT_FOREVER 0 + +// ==== INFRARED ==== + +/* Infrared message queue */ +#define IR_MAX_MESSAGES 4 +int ir_messages[IR_MAX_MESSAGES]; +OS_EVENT *ir_queue; + +/* Infrared messages */ +// Together these avoid passing 0 to the queue (which is not allowed since queue messages cannot be null) +// and invert pushbutton input (since the pushbutton returns 0 when it is pushed down). +#define IR_QUEUE_SEND_BASE 1 // Use: IR_QUEUE_SEND_BASE + IORD +#define IR_QUEUE_RECEIVE_BASE 2 // Use: IR_QUEUE_RECEIVE_BASE - OSQPend + + +MotorHandler *motor= new MotorHandler(); + + +// ==== mc + +#define mc_GUARD_TIME 1 + +void mc_task(void *pdata) +{ + printf("mc task\n"); + printf("MotorHandler [init"); + if (motor->init() == OK) { + printf("]\n\n"); + motor->forward(); + } else { + printf( ", error]\n"); + } + while(1){ + motor->forward(); + OSTimeDlyHMSM(0, 0, 2,0 ); + motor->stop(); + OSTimeDlyHMSM(0, 0, 2,0 ); + motor->backward(); + OSTimeDlyHMSM(0, 0, 2,0 ); + motor->stop(); + OSTimeDlyHMSM(0, 0, 2,0 ); + } +} + + + +// ==== GENERAL + +void queue_init() { + ir_queue = OSQCreate((void**)&ir_messages, IR_MAX_MESSAGES); +} + +/* The main function creates the LCD task, registers the edge counter polling interrupt, + * and starts the OS. */ +int main(void) +{ + int status = OK; + // Initialize components. + queue_init(); + // Create the mc task. + OSTaskCreateExt(mc_task, + NULL, + &mc_task_stk[TASK_STACKSIZE - 1], + MC_TASK_PRIORITY, + MC_TASK_PRIORITY, + mc_task_stk, + TASK_STACKSIZE, + NULL, + 0); + + if (status == OK) { + OSStart(); + } + + return 0; +} + +/****************************************************************************** + * * + * License Agreement * + * * + * Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * + * All rights reserved. * + * * + * Permission is hereby granted, free of charge, to any person obtaining a * + * copy of this software and associated documentation files (the "Software"), * + * to deal in the Software without restriction, including without limitation * + * the rights to use, copy, modify, merge, publish, distribute, sublicense, * + * and/or sell copies of the Software, and to permit persons to whom the * + * Software is furnished to do so, subject to the following conditions: * + * * + * The above copyright notice and this permission notice shall be included in * + * all copies or substantial portions of the Software. * + * * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * + * DEALINGS IN THE SOFTWARE. * + * * + * This agreement shall be governed in all respects by the laws of the State * + * of California and by the laws of the United States of America. * + * Altera does not recommend, suggest or require that this reference design * + * file be used in conjunction or combination with any other product. * + ******************************************************************************/ diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/3b/c043e522a9ab001311f2ce252b4696cb b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/3b/c043e522a9ab001311f2ce252b4696cb new file mode 100644 index 00000000..b0629ed1 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/3b/c043e522a9ab001311f2ce252b4696cb @@ -0,0 +1,153 @@ +/* + * MotorHandler.cpp + * + * Created on: 2014-03-03 + * Author: Amshu Gongal + */ + + +#include + +#include "altera_avalon_pio_regs.h" +#include "includes.h" +#include "system.h" + +#include "MotorHandler.h" + +#define WRITE_FIFO_EMPTY 0x80 +#define MOTOR_ENABLE 1 +#define MOTOR_RESET 0 + +// ALLOCATION +MotorHandler::MotorHandler() {} +MotorHandler::~MotorHandler() {} + +// INITIALIZATION + +/* + * Initializes this handler. + * @return OK if the handler was initialized without error + */ +Status MotorHandler::init() { + // Enable the motor controller. + reset(); + // Open the serial device to send commands to the motor controller. + motor_dev = alt_up_rs232_open_dev(RS232_MOTOR_NAME); + //printf("%d", motor_dev); + if (motor_dev == NULL) { + return ERR_MOTOR_OPEN; + } else { + return OK; + } +} + +void MotorHandler::configure(){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_CHANGE_CONFIGURATION, "change configuration"); + send(0X01, "2 MOTOR CONFIG"); + printf("\n"); +} +// TESTING + +void MotorHandler::test() { + send(MOTOR_START_BYTE, "test start"); +} + +// MOTOR CONTROL + +/* + * Move rover forward by activating both motors. + */ +void MotorHandler::forward() { + move(MOTOR_MOTOR1_FORWARD, "motor 1 forward"); + move(MOTOR_MOTOR2_FORWARD, "motor 2 forward"); +} + +/* + * Move rover backward by activating both motor backwards. + */ +void MotorHandler::backward() { + move(MOTOR_MOTOR1_BACKWARD, "motor 1 backward"); + move(MOTOR_MOTOR2_BACKWARD, "motor 2 backward"); +} + +/* + * Turn rover left. + */ +void MotorHandler::left() { + move(MOTOR_MOTOR2_FORWARD, "motor 1 forward"); +} + +/* + * Turn rover right. + */ +void MotorHandler::right() { + move(MOTOR_MOTOR2_FORWARD, "motor 2 forward"); +} + +/* + * Stop the rover. + */ +void MotorHandler::stop() { + move(MOTOR_MOTOR1_FORWARD, MOTOR_STOP_SPEED, "motor 1 stop"); + move(MOTOR_MOTOR2_FORWARD, MOTOR_STOP_SPEED, "motor 2 stop"); +} + +// MOTOR CONTROL HELPERS + +/* + * Moves in the given direction at constant speed. + * @param direction - the motor and direction to move in, e.g. MOTOR_MOTOR1_FORWARD + * @param description - the string description of the movement, for debugging + */ +void MotorHandler::move(char direction, char *description) { + move(direction, MOTOR_CONST_SPEED, description); +} + +/* + * Moves in the given direction and speed. + * @param direction - the motor and direction to move in, e.g. MOTOR_MOTOR1_FORWARD + * @param speed - the speed to move at, i.e. MOTOR_CONST_SPEED or MOTOR_STOP_SPEED + * @param description - the string description of the movement, for debugging + */ +void MotorHandler::move(char direction, char speed, char *description) { + send(MOTOR_START_BYTE, "start"); + send(MOTOR_DEVICE_TYPE, "device"); + send(direction, description); + send(speed, "speed"); + printf("\n"); +} + +/* + * Sends a byte-length message to the motor controller. + * @param message - the message to send + * @param description - the string description of the message, for debugging + */ +void MotorHandler::send(char message, char *description) { + alt_u32 write_space; + // Check for write space. + write_space = alt_up_rs232_get_available_space_in_write_FIFO(motor_dev); + if (write_space >= WRITE_FIFO_EMPTY) { + // If space, write. + int status = alt_up_rs232_write_data(motor_dev, message); + printf("MotorHandler [message: 0x%02x, description: %s", message, description); + // Log errors. + if (status == OK) { + printf("]\n"); + } else { + printf(", error: cannot write]\n"); + } + } else { + // If no space, wait and retry. + printf("MotorHandler [message: 0x%02x, description: %s, error: no write space; retrying]\n", message, description); + OSTimeDlyHMSM(0, 0, 0, 10); + send(message, description); + } +} + +void MotorHandler::reset(){ + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 0); + OSTimeDlyHMSM(0, 0, 2,0 ); + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 1); + OSTimeDlyHMSM(0, 0, 2, 100); +} diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/3c/b0f9dc1889b000131eb0f6c547a05c39 b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/3c/b0f9dc1889b000131eb0f6c547a05c39 new file mode 100644 index 00000000..7f29a5cc --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/3c/b0f9dc1889b000131eb0f6c547a05c39 @@ -0,0 +1,134 @@ +/* + * MotorHandler.cpp + * + * Created on: 2014-03-03 + * Author: Amshu Gongal + */ + + +#include + +#include "altera_avalon_pio_regs.h" +#include "includes.h" +#include "system.h" + +#include "MotorHandler.h" + +#define WRITE_FIFO_EMPTY 0x80 +#define MOTOR_ENABLE 1 +#define MOTOR_RESET 0 + +// ALLOCATION +MotorHandler::MotorHandler() {} +MotorHandler::~MotorHandler() {} + + +// INITIALIZATION + +/* + * Initializes this handler. + * @return OK if the handler was initialized without error + */ +Status MotorHandler::init() { + // Enable the motor controller. + reset(); + // Open the serial device to send commands to the motor controller. + motor_dev = alt_up_rs232_open_dev(RS232_MOTOR_NAME); + //printf("%d", motor_dev); + if (motor_dev == NULL) { + return ERR_MOTOR_OPEN; + } else { + return OK; + } +} + +void MotorHandler::configure(){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_CHANGE_CONFIGURATION, "change configuration"); + send(0X01, "2 MOTOR CONFIG"); + printf("\n"); +} + +//Command Interpreter +/* + * Interprets the command from the network handler and sends move commands + * @param motor The motor to move eg. Left or Right + * @param motorDirection The direction of the given motor to move + * @param speed The speed the motor is to move + */ +void MotorHandler::motorCommand(string motor, string motorDirection, string speed){ + char motorID = interpretMotor(motor); + char Direction = interpretDirection(motorDirection, int(motorID)); + char Speed = (char) atol(speed); + move(Direction, Speed, "Move Motor"); +} + +char MotorHandler::interpretMotor(string motor){ + if(motor.compare(MOTOR_LEFT) == 0){ + return MOTOR_LEFT_CHAR; + } + else{ + return MOTOR_RIGHT_CHAR; + } +} + +char MotorHandler::interpretDirection(string direction, int motor){ + if(direction.compare(MOTOR_FORWARD) == 0){ + return (char) (motor*2 + 1); + } + else{ + return (char) (motor*2); + } +} + +// MOTOR CONTROL + +/*Moves the given motor in specified direction by Motor Direction with specified + * Speed + * @param MotorDirection Motor and direction to move + * @param Speed the speed to move at + * @param string description of motor movement + */ + +void MotorHandler::move(char MotorDirection,char Speed,char * Description){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_DEVICE_TYPE, "device"); + send(MotorDirection, Description); + send(Speed, "speed"); + printf("\n"); +} + +// MOTOR CONTROL HELPERS +/* + * Sends a byte-length message to the motor controller. + * @param message - the message to send + * @param description - the string description of the message, for debugging + */ +void MotorHandler::send(char message, char *description) { + alt_u32 write_space; + // Check for write space. + write_space = alt_up_rs232_get_available_space_in_write_FIFO(motor_dev); + if (write_space >= WRITE_FIFO_EMPTY) { + // If space, write. + int status = alt_up_rs232_write_data(motor_dev, message); + printf("MotorHandler [message: 0x%02x, description: %s", message, description); + // Log errors. + if (status == OK) { + printf("]\n"); + } else { + printf(", error: cannot write]\n"); + } + } else { + // If no space, wait and retry. + printf("MotorHandler [message: 0x%02x, description: %s, error: no write space; retrying]\n", message, description); + OSTimeDlyHMSM(0, 0, 0, 10); + send(message, description); + } +} + +void MotorHandler::reset(){ + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 0); + OSTimeDlyHMSM(0, 0, 0,200 ); + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 1); + OSTimeDlyHMSM(0, 0, 0, 200); +} diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/3e/a00a96ec82b000131eb0f6c547a05c39 b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/3e/a00a96ec82b000131eb0f6c547a05c39 new file mode 100644 index 00000000..0a3dfb4f --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/3e/a00a96ec82b000131eb0f6c547a05c39 @@ -0,0 +1,60 @@ +/* + * MotorHandler.h + * + * Created on: 2014-03-03 + * Author: Amshu Gongal + */ + +#ifndef MOTORHANDLER_H_ +#define MOTORHANDLER_H_ + +#include "altera_up_avalon_rs232.h" +#include "altera_up_avalon_rs232_regs.h" +#include +#include +#include "Status.h" + +// Motor messages are LSB first +#define MOTOR_START_BYTE 0x80 +#define MOTOR_DEVICE_TYPE 0x00 +#define MOTOR_LEFT_BACKWARD 0x04 // motor 1 backward +#define MOTOR_RIGHT_BACKWARD 0x06 // motor 2 backward +#define MOTOR_LEFT_FORWARD 0x05 // motor 1 forward +#define MOTOR_RIGHT_FORWARD 0x07 // motor 2 forward +#define MOTOR_CONST_SPEED 0x5F +#define MOTOR_STOP_SPEED 0x00 +#define MOTOR_CHANGE_CONFIGURATION 0X02 + +class MotorHandler { +public: + MotorHandler(); + virtual ~MotorHandler(); + + /* + * Initializes this handler. + * @return OK if the handler was initialized without error + */ + Status init(); + void motorCommand(string motor, string motorDirection, char); + +private: + /* The device used to send serial commands to the motor controller. */ + alt_up_rs232_dev *motor_dev; + + /* + * Moves in the given direction at constant speed. + * @param direction - the motor and direction to move in, e.g. MOTOR_MOTOR1_FORWARD + * @param speed speed of the motor + * @param description - the string description of the movement, for debugging + */ + void move(char direction, char speed, char *description); + + /* + * Sends a byte-length message to the motor controller. + * @param message - the message to send + * @param description - the string description of the message, for debugging + */ + void send(char message, char *description); +}; + +#endif /* MOTORHANDLER_H_ */ diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/41/90d8fa1f8cb000131eb0f6c547a05c39 b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/41/90d8fa1f8cb000131eb0f6c547a05c39 new file mode 100644 index 00000000..b8aa22bf --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/41/90d8fa1f8cb000131eb0f6c547a05c39 @@ -0,0 +1,147 @@ +/************************************************************************* + * ARCap + * Amshu Gongal, Kenan Kigunda + * February 18, 2014 + ************************************************************************** + * Description: * + * Prototype testing for infrared and mc. + **************************************************************************/ + +#include +#include "includes.h" +#include "altera_avalon_pio_regs.h" +#include "altera_avalon_uart_regs.h" +#include "sys/alt_irq.h" +#include "alt_types.h" +#include "altera_up_avalon_rs232.h" +#include "altera_up_avalon_rs232_regs.h" + +#include "MotorHandler.h" +#include "Status.h" + +/* Task stacks */ +#define TASK_STACKSIZE 2048 +OS_STK ir_task_stk[TASK_STACKSIZE]; +OS_STK mc_task_stk[TASK_STACKSIZE]; +/* Task priorities */ +#define IR_TASK_PRIORITY 2 +#define MC_TASK_PRIORITY 1 + + +#define SW_READ 1 +#define SW_WRITE 2 +#define WRITE_FIFO_EMPTY 0x80 +#define READ_FIFO_EMPTY 0x0 +OS_EVENT *SWQ; +OS_EVENT *RS232Q; +INT8U err; + + +/* Error status */ +#define OK 0 + +/* Message queues */ +#define WAIT_FOREVER 0 + +// ==== INFRARED ==== + +/* Infrared message queue */ +#define IR_MAX_MESSAGES 4 +int ir_messages[IR_MAX_MESSAGES]; +OS_EVENT *ir_queue; + +/* Infrared messages */ +// Together these avoid passing 0 to the queue (which is not allowed since queue messages cannot be null) +// and invert pushbutton input (since the pushbutton returns 0 when it is pushed down). +#define IR_QUEUE_SEND_BASE 1 // Use: IR_QUEUE_SEND_BASE + IORD +#define IR_QUEUE_RECEIVE_BASE 2 // Use: IR_QUEUE_RECEIVE_BASE - OSQPend + + +MotorHandler *motor= new MotorHandler(); + + +// ==== mc + +#define mc_GUARD_TIME 1 + +void mc_task(void *pdata) +{ + printf("mc task\n"); + printf("MotorHandler [init"); + if (motor->init() == OK) { + printf("]\n\n"); + } else { + printf( ", error]\n"); + } + while(1){ +// motor->move(0x05, 0x6F, "Left Motor Forward"); +// OSTimeDlyHMSM(0, 0, 5, 0); +// motor->move(0x05,0x00, "Left Motor Stop"); +// OSTimeDlyHMSM(0, 0, 3,0); + + } +} + + + +// ==== GENERAL + +void queue_init() { + ir_queue = OSQCreate((void**)&ir_messages, IR_MAX_MESSAGES); +} + +/* The main function creates the LCD task, registers the edge counter polling interrupt, + * and starts the OS. */ +int main(void) +{ + int status = OK; + // Initialize components. + queue_init(); + // Create the mc task. + OSTaskCreateExt(mc_task, + NULL, + &mc_task_stk[TASK_STACKSIZE - 1], + MC_TASK_PRIORITY, + MC_TASK_PRIORITY, + mc_task_stk, + TASK_STACKSIZE, + NULL, + 0); + + if (status == OK) { + OSStart(); + } + + return 0; +} + +/****************************************************************************** + * * + * License Agreement * + * * + * Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * + * All rights reserved. * + * * + * Permission is hereby granted, free of charge, to any person obtaining a * + * copy of this software and associated documentation files (the "Software"), * + * to deal in the Software without restriction, including without limitation * + * the rights to use, copy, modify, merge, publish, distribute, sublicense, * + * and/or sell copies of the Software, and to permit persons to whom the * + * Software is furnished to do so, subject to the following conditions: * + * * + * The above copyright notice and this permission notice shall be included in * + * all copies or substantial portions of the Software. * + * * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * + * DEALINGS IN THE SOFTWARE. * + * * + * This agreement shall be governed in all respects by the laws of the State * + * of California and by the laws of the United States of America. * + * Altera does not recommend, suggest or require that this reference design * + * file be used in conjunction or combination with any other product. * + ******************************************************************************/ diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/4b/c0363df27fb000131eb0f6c547a05c39 b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/4b/c0363df27fb000131eb0f6c547a05c39 new file mode 100644 index 00000000..81b2ea3a --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/4b/c0363df27fb000131eb0f6c547a05c39 @@ -0,0 +1,153 @@ +/* + * MotorHandler.cpp + * + * Created on: 2014-03-03 + * Author: Amshu Gongal + */ + + +#include + +#include "altera_avalon_pio_regs.h" +#include "includes.h" +#include "system.h" + +#include "MotorHandler.h" + +#define WRITE_FIFO_EMPTY 0x80 +#define MOTOR_ENABLE 1 +#define MOTOR_RESET 0 + +// ALLOCATION +MotorHandler::MotorHandler() {} +MotorHandler::~MotorHandler() {} + +// INITIALIZATION + +/* + * Initializes this handler. + * @return OK if the handler was initialized without error + */ +Status MotorHandler::init() { + // Enable the motor controller. + reset(); + // Open the serial device to send commands to the motor controller. + motor_dev = alt_up_rs232_open_dev(RS232_MOTOR_NAME); + //printf("%d", motor_dev); + if (motor_dev == NULL) { + return ERR_MOTOR_OPEN; + } else { + return OK; + } +} + +void MotorHandler::configure(){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_CHANGE_CONFIGURATION, "change configuration"); + send(0X01, "2 MOTOR CONFIG"); + printf("\n"); +} +// TESTING + +void MotorHandler::test() { + send(MOTOR_START_BYTE, "test start"); +} + +// MOTOR CONTROL + +/* + * Move rover forward by activating both motors. + */ +void MotorHandler::forward() { + move(MOTOR_BOTH_FORWARD, "motor both forward"); + //move(MOTOR_MOTOR2_FORWARD, "motor 2 forward"); +} + +/* + * Move rover backward by activating both motor backwards. + */ +void MotorHandler::backward() { + move(MOTOR_BOTH_BACKWARD, "motor both backward"); + // move(MOTOR_MOTOR2_BACKWARD, "motor 2 backward"); +} + +/* + * Turn rover left. + */ +void MotorHandler::left() { + move(MOTOR_MOTOR1_FORWARD, "motor 1 forward"); +} + +/* + * Turn rover right. + */ +void MotorHandler::right() { + move(MOTOR_MOTOR2_FORWARD, "motor 2 forward"); +} + +/* + * Stop the rover. + */ +void MotorHandler::stop() { + move(MOTOR_MOTOR1_FORWARD, MOTOR_STOP_SPEED, "motor 1 stop"); + move(MOTOR_MOTOR2_FORWARD, MOTOR_STOP_SPEED, "motor 2 stop"); +} + +// MOTOR CONTROL HELPERS + +/* + * Moves in the given direction at constant speed. + * @param direction - the motor and direction to move in, e.g. MOTOR_MOTOR1_FORWARD + * @param description - the string description of the movement, for debugging + */ +void MotorHandler::move(char direction, char *description) { + move(direction, MOTOR_CONST_SPEED, description); +} + +/* + * Moves in the given direction and speed. + * @param direction - the motor and direction to move in, e.g. MOTOR_MOTOR1_FORWARD + * @param speed - the speed to move at, i.e. MOTOR_CONST_SPEED or MOTOR_STOP_SPEED + * @param description - the string description of the movement, for debugging + */ +void MotorHandler::move(char direction, char speed, char *description) { + send(MOTOR_START_BYTE, "start"); + send(MOTOR_DEVICE_TYPE, "device"); + send(direction, description); + send(speed, "speed"); + printf("\n"); +} + +/* + * Sends a byte-length message to the motor controller. + * @param message - the message to send + * @param description - the string description of the message, for debugging + */ +void MotorHandler::send(char message, char *description) { + alt_u32 write_space; + // Check for write space. + write_space = alt_up_rs232_get_available_space_in_write_FIFO(motor_dev); + if (write_space >= WRITE_FIFO_EMPTY) { + // If space, write. + int status = alt_up_rs232_write_data(motor_dev, message); + printf("MotorHandler [message: 0x%02x, description: %s", message, description); + // Log errors. + if (status == OK) { + printf("]\n"); + } else { + printf(", error: cannot write]\n"); + } + } else { + // If no space, wait and retry. + printf("MotorHandler [message: 0x%02x, description: %s, error: no write space; retrying]\n", message, description); + OSTimeDlyHMSM(0, 0, 0, 10); + send(message, description); + } +} + +void MotorHandler::reset(){ + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 0); + OSTimeDlyHMSM(0, 0, 0,200 ); + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 1); + OSTimeDlyHMSM(0, 0, 0, 200); +} diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/4d/d016a3e28faf0013110bf3236575307b b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/4d/d016a3e28faf0013110bf3236575307b new file mode 100644 index 00000000..841a456f --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/4d/d016a3e28faf0013110bf3236575307b @@ -0,0 +1,159 @@ +/************************************************************************* + * ARCap + * Amshu Gongal, Kenan Kigunda + * February 18, 2014 + ************************************************************************** + * Description: * + * Prototype testing for infrared and mc. + **************************************************************************/ + +#include +#include "includes.h" +#include "altera_avalon_pio_regs.h" +#include "altera_avalon_uart_regs.h" +#include "sys/alt_irq.h" +#include "alt_types.h" +#include "altera_up_avalon_rs232.h" +#include "altera_up_avalon_rs232_regs.h" + +#include "MotorHandler.h" +#include "Status.h" + +/* Task stacks */ +#define TASK_STACKSIZE 2048 +OS_STK ir_task_stk[TASK_STACKSIZE]; +OS_STK mc_task_stk[TASK_STACKSIZE]; +/* Task priorities */ +#define IR_TASK_PRIORITY 2 +#define MC_TASK_PRIORITY 1 + + +#define SW_READ 1 +#define SW_WRITE 2 +#define WRITE_FIFO_EMPTY 0x80 +#define READ_FIFO_EMPTY 0x0 +OS_EVENT *SWQ; +OS_EVENT *RS232Q; +INT8U err; + + +/* Error status */ +#define OK 0 + +/* Message queues */ +#define WAIT_FOREVER 0 + +// ==== INFRARED ==== + +/* Infrared message queue */ +#define IR_MAX_MESSAGES 4 +int ir_messages[IR_MAX_MESSAGES]; +OS_EVENT *ir_queue; + +/* Infrared messages */ +// Together these avoid passing 0 to the queue (which is not allowed since queue messages cannot be null) +// and invert pushbutton input (since the pushbutton returns 0 when it is pushed down). +#define IR_QUEUE_SEND_BASE 1 // Use: IR_QUEUE_SEND_BASE + IORD +#define IR_QUEUE_RECEIVE_BASE 2 // Use: IR_QUEUE_RECEIVE_BASE - OSQPend + + +MotorHandler *motor= new MotorHandler(); + + +// ==== mc + +#define mc_GUARD_TIME 1 + +void mc_task(void *pdata) +{ + printf("mc task\n"); + printf("MotorHandler [init"); + if (motor->init() == OK) { + printf("]\n\n"); + } else { + printf( ", error]\n"); + } + while(1){ + motor->forward(); + OSTimeDlyHMSM(0, 0, 5, 0); + motor->stop(); + OSTimeDlyHMSM(0, 0, 3,0); + motor->left(); + OSTimeDlyHMSM(0, 0, 5, 0); + motor->stop(); + OSTimeDlyHMSM(0, 0, 3,0); + motor->backward(); + OSTimeDlyHMSM(0, 0, 5,0); + motor->stop(); + OSTimeDlyHMSM(0, 0, 3,0); + motor->right(); + OSTimeDlyHMSM(0, 0,5,0); + motor->stop(); + OSTimeDlyHMSM(0, 0, 3,0); + + } +} + + + +// ==== GENERAL + +void queue_init() { + ir_queue = OSQCreate((void**)&ir_messages, IR_MAX_MESSAGES); +} + +/* The main function creates the LCD task, registers the edge counter polling interrupt, + * and starts the OS. */ +int main(void) +{ + int status = OK; + // Initialize components. + queue_init(); + // Create the mc task. + OSTaskCreateExt(mc_task, + NULL, + &mc_task_stk[TASK_STACKSIZE - 1], + MC_TASK_PRIORITY, + MC_TASK_PRIORITY, + mc_task_stk, + TASK_STACKSIZE, + NULL, + 0); + + if (status == OK) { + OSStart(); + } + + return 0; +} + +/****************************************************************************** + * * + * License Agreement * + * * + * Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * + * All rights reserved. * + * * + * Permission is hereby granted, free of charge, to any person obtaining a * + * copy of this software and associated documentation files (the "Software"), * + * to deal in the Software without restriction, including without limitation * + * the rights to use, copy, modify, merge, publish, distribute, sublicense, * + * and/or sell copies of the Software, and to permit persons to whom the * + * Software is furnished to do so, subject to the following conditions: * + * * + * The above copyright notice and this permission notice shall be included in * + * all copies or substantial portions of the Software. * + * * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * + * DEALINGS IN THE SOFTWARE. * + * * + * This agreement shall be governed in all respects by the laws of the State * + * of California and by the laws of the United States of America. * + * Altera does not recommend, suggest or require that this reference design * + * file be used in conjunction or combination with any other product. * + ******************************************************************************/ diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/55/e005066a87b000131eb0f6c547a05c39 b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/55/e005066a87b000131eb0f6c547a05c39 new file mode 100644 index 00000000..20fee504 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/55/e005066a87b000131eb0f6c547a05c39 @@ -0,0 +1,121 @@ +/* + * MotorHandler.cpp + * + * Created on: 2014-03-03 + * Author: Amshu Gongal + */ + + +#include + +#include "altera_avalon_pio_regs.h" +#include "includes.h" +#include "system.h" + +#include "MotorHandler.h" + +#define WRITE_FIFO_EMPTY 0x80 +#define MOTOR_ENABLE 1 +#define MOTOR_RESET 0 + +// ALLOCATION +MotorHandler::MotorHandler() {} +MotorHandler::~MotorHandler() {} + + +// INITIALIZATION + +/* + * Initializes this handler. + * @return OK if the handler was initialized without error + */ +Status MotorHandler::init() { + // Enable the motor controller. + reset(); + // Open the serial device to send commands to the motor controller. + motor_dev = alt_up_rs232_open_dev(RS232_MOTOR_NAME); + //printf("%d", motor_dev); + if (motor_dev == NULL) { + return ERR_MOTOR_OPEN; + } else { + return OK; + } +} + +void MotorHandler::configure(){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_CHANGE_CONFIGURATION, "change configuration"); + send(0X01, "2 MOTOR CONFIG"); + printf("\n"); +} + +//Command Interpreter +/* + * Interprets the command from the network handler and sends move commands + * @param motor The motor to move eg. Left or Right + * @param motorDirection The direction of the given motor to move + * @param speed The speed the motor is to move + */ +void MotorHandler::motorCommand(string motor, string motorDirection, string speed){ + char motorC = interpretMotor(motor); +} + +char MotorHandler::interpretMotor(string motor){ + +} + +char MotorHandler::interpretDirection(string direction, int motor){ + +} + +// MOTOR CONTROL + +/*Moves the given motor in specified direction by Motor Direction with specified + * Speed + * @param MotorDirection Motor and direction to move + * @param Speed the speed to move at + * @param string description of motor movement + */ + +void MotorHandler::move(char MotorDirection,char Speed,char * Description){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_DEVICE_TYPE, "device"); + send(MotorDirection, Description); + send(Speed, "speed"); + printf("\n"); +} + +// MOTOR CONTROL HELPERS +/* + * Sends a byte-length message to the motor controller. + * @param message - the message to send + * @param description - the string description of the message, for debugging + */ +void MotorHandler::send(char message, char *description) { + alt_u32 write_space; + // Check for write space. + write_space = alt_up_rs232_get_available_space_in_write_FIFO(motor_dev); + if (write_space >= WRITE_FIFO_EMPTY) { + // If space, write. + int status = alt_up_rs232_write_data(motor_dev, message); + printf("MotorHandler [message: 0x%02x, description: %s", message, description); + // Log errors. + if (status == OK) { + printf("]\n"); + } else { + printf(", error: cannot write]\n"); + } + } else { + // If no space, wait and retry. + printf("MotorHandler [message: 0x%02x, description: %s, error: no write space; retrying]\n", message, description); + OSTimeDlyHMSM(0, 0, 0, 10); + send(message, description); + } +} + +void MotorHandler::reset(){ + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 0); + OSTimeDlyHMSM(0, 0, 0,200 ); + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 1); + OSTimeDlyHMSM(0, 0, 0, 200); +} diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/56/3025ad5481b000131eb0f6c547a05c39 b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/56/3025ad5481b000131eb0f6c547a05c39 new file mode 100644 index 00000000..aea166ab --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/56/3025ad5481b000131eb0f6c547a05c39 @@ -0,0 +1,104 @@ +/* + * MotorHandler.cpp + * + * Created on: 2014-03-03 + * Author: Amshu Gongal + */ + + +#include + +#include "altera_avalon_pio_regs.h" +#include "includes.h" +#include "system.h" + +#include "MotorHandler.h" + +#define WRITE_FIFO_EMPTY 0x80 +#define MOTOR_ENABLE 1 +#define MOTOR_RESET 0 + +// ALLOCATION +MotorHandler::MotorHandler() {} +MotorHandler::~MotorHandler() {} + + + + +// INITIALIZATION + +/* + * Initializes this handler. + * @return OK if the handler was initialized without error + */ +Status MotorHandler::init() { + // Enable the motor controller. + reset(); + // Open the serial device to send commands to the motor controller. + motor_dev = alt_up_rs232_open_dev(RS232_MOTOR_NAME); + //printf("%d", motor_dev); + if (motor_dev == NULL) { + return ERR_MOTOR_OPEN; + } else { + return OK; + } +} + +void MotorHandler::configure(){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_CHANGE_CONFIGURATION, "change configuration"); + send(0X01, "2 MOTOR CONFIG"); + printf("\n"); +} +// TESTING + +void MotorHandler::test() { + send(MOTOR_START_BYTE, "test start"); +} + +// MOTOR CONTROL + +void MotorHandler::move(char MotorDirection,char Speed,char * Description){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_DEVICE_TYPE, "device"); + send(MotorDirection, Description); + send(Speed, "speed"); + printf("\n"); +} + +// MOTOR CONTROL HELPERS + + +/* + * Sends a byte-length message to the motor controller. + * @param message - the message to send + * @param description - the string description of the message, for debugging + */ +void MotorHandler::send(char message, char *description) { + alt_u32 write_space; + // Check for write space. + write_space = alt_up_rs232_get_available_space_in_write_FIFO(motor_dev); + if (write_space >= WRITE_FIFO_EMPTY) { + // If space, write. + int status = alt_up_rs232_write_data(motor_dev, message); + printf("MotorHandler [message: 0x%02x, description: %s", message, description); + // Log errors. + if (status == OK) { + printf("]\n"); + } else { + printf(", error: cannot write]\n"); + } + } else { + // If no space, wait and retry. + printf("MotorHandler [message: 0x%02x, description: %s, error: no write space; retrying]\n", message, description); + OSTimeDlyHMSM(0, 0, 0, 10); + send(message, description); + } +} + +void MotorHandler::reset(){ + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 0); + OSTimeDlyHMSM(0, 0, 0,200 ); + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 1); + OSTimeDlyHMSM(0, 0, 0, 200); +} diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/59/60df3899adab001311f2ce252b4696cb b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/59/60df3899adab001311f2ce252b4696cb new file mode 100644 index 00000000..96c89928 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/59/60df3899adab001311f2ce252b4696cb @@ -0,0 +1,153 @@ +/* + * MotorHandler.cpp + * + * Created on: 2014-03-03 + * Author: Amshu Gongal + */ + + +#include + +#include "altera_avalon_pio_regs.h" +#include "includes.h" +#include "system.h" + +#include "MotorHandler.h" + +#define WRITE_FIFO_EMPTY 0x80 +#define MOTOR_ENABLE 1 +#define MOTOR_RESET 0 + +// ALLOCATION +MotorHandler::MotorHandler() {} +MotorHandler::~MotorHandler() {} + +// INITIALIZATION + +/* + * Initializes this handler. + * @return OK if the handler was initialized without error + */ +Status MotorHandler::init() { + // Enable the motor controller. + reset(); + // Open the serial device to send commands to the motor controller. + motor_dev = alt_up_rs232_open_dev(RS232_MOTOR_NAME); + //printf("%d", motor_dev); + if (motor_dev == NULL) { + return ERR_MOTOR_OPEN; + } else { + return OK; + } +} + +void MotorHandler::configure(){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_CHANGE_CONFIGURATION, "change configuration"); + send(0X01, "2 MOTOR CONFIG"); + printf("\n"); +} +// TESTING + +void MotorHandler::test() { + send(MOTOR_START_BYTE, "test start"); +} + +// MOTOR CONTROL + +/* + * Move rover forward by activating both motors. + */ +void MotorHandler::forward() { + move(MOTOR_BOTH_FORWARD, "both motors forward"); +// move(MOTOR_MOTOR2_FORWARD, "motor 2 forward"); +} + +/* + * Move rover backward by activating both motor backwards. + */ +void MotorHandler::backward() { + move(MOTOR_BOTH_BACKWARD, "both motors backward"); +// move(MOTOR_MOTOR2_BACKWARD, "motor 2 backward"); +} + +/* + * Turn rover left. + */ +void MotorHandler::left() { + move(MOTOR_MOTOR2_FORWARD, "motor 1 forward"); +} + +/* + * Turn rover right. + */ +void MotorHandler::right() { + move(MOTOR_MOTOR2_FORWARD, "motor 2 forward"); +} + +/* + * Stop the rover. + */ +void MotorHandler::stop() { + move(MOTOR_MOTOR1_FORWARD, MOTOR_STOP_SPEED, "motor 1 stop"); + move(MOTOR_MOTOR2_FORWARD, MOTOR_STOP_SPEED, "motor 2 stop"); +} + +// MOTOR CONTROL HELPERS + +/* + * Moves in the given direction at constant speed. + * @param direction - the motor and direction to move in, e.g. MOTOR_MOTOR1_FORWARD + * @param description - the string description of the movement, for debugging + */ +void MotorHandler::move(char direction, char *description) { + move(direction, MOTOR_CONST_SPEED, description); +} + +/* + * Moves in the given direction and speed. + * @param direction - the motor and direction to move in, e.g. MOTOR_MOTOR1_FORWARD + * @param speed - the speed to move at, i.e. MOTOR_CONST_SPEED or MOTOR_STOP_SPEED + * @param description - the string description of the movement, for debugging + */ +void MotorHandler::move(char direction, char speed, char *description) { + send(MOTOR_START_BYTE, "start"); + send(MOTOR_DEVICE_TYPE, "device"); + send(direction, description); + send(speed, "speed"); + printf("\n"); +} + +/* + * Sends a byte-length message to the motor controller. + * @param message - the message to send + * @param description - the string description of the message, for debugging + */ +void MotorHandler::send(char message, char *description) { + alt_u32 write_space; + // Check for write space. + write_space = alt_up_rs232_get_available_space_in_write_FIFO(motor_dev); + if (write_space >= WRITE_FIFO_EMPTY) { + // If space, write. + int status = alt_up_rs232_write_data(motor_dev, message); + printf("MotorHandler [message: 0x%02x, description: %s", message, description); + // Log errors. + if (status == OK) { + printf("]\n"); + } else { + printf(", error: cannot write]\n"); + } + } else { + // If no space, wait and retry. + printf("MotorHandler [message: 0x%02x, description: %s, error: no write space; retrying]\n", message, description); + OSTimeDlyHMSM(0, 0, 0, 10); + send(message, description); + } +} + +void MotorHandler::reset(){ + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 0); + OSTimeDlyHMSM(0, 0, 2,0 ); + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 1); + OSTimeDlyHMSM(0, 0, 2, 100); +} diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/5a/309b4201a6ab001311f2ce252b4696cb b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/5a/309b4201a6ab001311f2ce252b4696cb new file mode 100644 index 00000000..55322778 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/5a/309b4201a6ab001311f2ce252b4696cb @@ -0,0 +1,145 @@ +/************************************************************************* + * ARCap + * Amshu Gongal, Kenan Kigunda + * February 18, 2014 + ************************************************************************** + * Description: * + * Prototype testing for infrared and mc. + **************************************************************************/ + +#include +#include "includes.h" +#include "altera_avalon_pio_regs.h" +#include "altera_avalon_uart_regs.h" +#include "sys/alt_irq.h" +#include "alt_types.h" +#include "altera_up_avalon_rs232.h" +#include "altera_up_avalon_rs232_regs.h" + +#include "MotorHandler.h" +#include "Status.h" + +/* Task stacks */ +#define TASK_STACKSIZE 2048 +OS_STK ir_task_stk[TASK_STACKSIZE]; +OS_STK mc_task_stk[TASK_STACKSIZE]; +/* Task priorities */ +#define IR_TASK_PRIORITY 2 +#define MC_TASK_PRIORITY 1 + + +#define SW_READ 1 +#define SW_WRITE 2 +#define WRITE_FIFO_EMPTY 0x80 +#define READ_FIFO_EMPTY 0x0 +OS_EVENT *SWQ; +OS_EVENT *RS232Q; +INT8U err; + + +/* Error status */ +#define OK 0 + +/* Message queues */ +#define WAIT_FOREVER 0 + +// ==== INFRARED ==== + +/* Infrared message queue */ +#define IR_MAX_MESSAGES 4 +int ir_messages[IR_MAX_MESSAGES]; +OS_EVENT *ir_queue; + +/* Infrared messages */ +// Together these avoid passing 0 to the queue (which is not allowed since queue messages cannot be null) +// and invert pushbutton input (since the pushbutton returns 0 when it is pushed down). +#define IR_QUEUE_SEND_BASE 1 // Use: IR_QUEUE_SEND_BASE + IORD +#define IR_QUEUE_RECEIVE_BASE 2 // Use: IR_QUEUE_RECEIVE_BASE - OSQPend + + +MotorHandler *motor= new MotorHandler(); + + +// ==== mc + +#define mc_GUARD_TIME 1 + +void mc_task(void *pdata) +{ + printf("mc task\n"); + printf("MotorHandler [init"); + if (motor->init() == OK) { + printf("]\n\n"); + motor->forward(); + } else { + printf( ", error]\n"); + } + while(1){ + motor->reset(); + } +} + + + +// ==== GENERAL + +void queue_init() { + ir_queue = OSQCreate((void**)&ir_messages, IR_MAX_MESSAGES); +} + +/* The main function creates the LCD task, registers the edge counter polling interrupt, + * and starts the OS. */ +int main(void) +{ + int status = OK; + // Initialize components. + queue_init(); + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 1); + // Create the mc task. + OSTaskCreateExt(mc_task, + NULL, + &mc_task_stk[TASK_STACKSIZE - 1], + MC_TASK_PRIORITY, + MC_TASK_PRIORITY, + mc_task_stk, + TASK_STACKSIZE, + NULL, + 0); + + if (status == OK) { + OSStart(); + } + + return 0; +} + +/****************************************************************************** + * * + * License Agreement * + * * + * Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * + * All rights reserved. * + * * + * Permission is hereby granted, free of charge, to any person obtaining a * + * copy of this software and associated documentation files (the "Software"), * + * to deal in the Software without restriction, including without limitation * + * the rights to use, copy, modify, merge, publish, distribute, sublicense, * + * and/or sell copies of the Software, and to permit persons to whom the * + * Software is furnished to do so, subject to the following conditions: * + * * + * The above copyright notice and this permission notice shall be included in * + * all copies or substantial portions of the Software. * + * * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * + * DEALINGS IN THE SOFTWARE. * + * * + * This agreement shall be governed in all respects by the laws of the State * + * of California and by the laws of the United States of America. * + * Altera does not recommend, suggest or require that this reference design * + * file be used in conjunction or combination with any other product. * + ******************************************************************************/ diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/5a/e0f12e4bcdab001312eeeea4d67ccb1b b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/5a/e0f12e4bcdab001312eeeea4d67ccb1b new file mode 100644 index 00000000..2ba5cd44 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/5a/e0f12e4bcdab001312eeeea4d67ccb1b @@ -0,0 +1,148 @@ +/************************************************************************* + * ARCap + * Amshu Gongal, Kenan Kigunda + * February 18, 2014 + ************************************************************************** + * Description: * + * Prototype testing for infrared and mc. + **************************************************************************/ + +#include +#include "includes.h" +#include "altera_avalon_pio_regs.h" +#include "altera_avalon_uart_regs.h" +#include "sys/alt_irq.h" +#include "alt_types.h" +#include "altera_up_avalon_rs232.h" +#include "altera_up_avalon_rs232_regs.h" + +#include "MotorHandler.h" +#include "Status.h" + +/* Task stacks */ +#define TASK_STACKSIZE 2048 +OS_STK ir_task_stk[TASK_STACKSIZE]; +OS_STK mc_task_stk[TASK_STACKSIZE]; +/* Task priorities */ +#define IR_TASK_PRIORITY 2 +#define MC_TASK_PRIORITY 1 + + +#define SW_READ 1 +#define SW_WRITE 2 +#define WRITE_FIFO_EMPTY 0x80 +#define READ_FIFO_EMPTY 0x0 +OS_EVENT *SWQ; +OS_EVENT *RS232Q; +INT8U err; + + +/* Error status */ +#define OK 0 + +/* Message queues */ +#define WAIT_FOREVER 0 + +// ==== INFRARED ==== + +/* Infrared message queue */ +#define IR_MAX_MESSAGES 4 +int ir_messages[IR_MAX_MESSAGES]; +OS_EVENT *ir_queue; + +/* Infrared messages */ +// Together these avoid passing 0 to the queue (which is not allowed since queue messages cannot be null) +// and invert pushbutton input (since the pushbutton returns 0 when it is pushed down). +#define IR_QUEUE_SEND_BASE 1 // Use: IR_QUEUE_SEND_BASE + IORD +#define IR_QUEUE_RECEIVE_BASE 2 // Use: IR_QUEUE_RECEIVE_BASE - OSQPend + + +MotorHandler *motor= new MotorHandler(); + + +// ==== mc + +#define mc_GUARD_TIME 1 + +void mc_task(void *pdata) +{ + printf("mc task\n"); + printf("MotorHandler [init"); + if (motor->init() == OK) { + printf("]\n\n"); + motor->forward(); + } else { + printf( ", error]\n"); + } + while(1){ + motor->forward(); + OSTimeDlyHMSM(0, 0, 0, 200); + motor->stop(); + OSTimeDlyHMSM(0, 0, 3,0); + + } +} + + + +// ==== GENERAL + +void queue_init() { + ir_queue = OSQCreate((void**)&ir_messages, IR_MAX_MESSAGES); +} + +/* The main function creates the LCD task, registers the edge counter polling interrupt, + * and starts the OS. */ +int main(void) +{ + int status = OK; + // Initialize components. + queue_init(); + // Create the mc task. + OSTaskCreateExt(mc_task, + NULL, + &mc_task_stk[TASK_STACKSIZE - 1], + MC_TASK_PRIORITY, + MC_TASK_PRIORITY, + mc_task_stk, + TASK_STACKSIZE, + NULL, + 0); + + if (status == OK) { + OSStart(); + } + + return 0; +} + +/****************************************************************************** + * * + * License Agreement * + * * + * Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * + * All rights reserved. * + * * + * Permission is hereby granted, free of charge, to any person obtaining a * + * copy of this software and associated documentation files (the "Software"), * + * to deal in the Software without restriction, including without limitation * + * the rights to use, copy, modify, merge, publish, distribute, sublicense, * + * and/or sell copies of the Software, and to permit persons to whom the * + * Software is furnished to do so, subject to the following conditions: * + * * + * The above copyright notice and this permission notice shall be included in * + * all copies or substantial portions of the Software. * + * * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * + * DEALINGS IN THE SOFTWARE. * + * * + * This agreement shall be governed in all respects by the laws of the State * + * of California and by the laws of the United States of America. * + * Altera does not recommend, suggest or require that this reference design * + * file be used in conjunction or combination with any other product. * + ******************************************************************************/ diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/5c/e05bd365a9ab001311f2ce252b4696cb b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/5c/e05bd365a9ab001311f2ce252b4696cb new file mode 100644 index 00000000..e146dcbf --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/5c/e05bd365a9ab001311f2ce252b4696cb @@ -0,0 +1,152 @@ +/************************************************************************* + * ARCap + * Amshu Gongal, Kenan Kigunda + * February 18, 2014 + ************************************************************************** + * Description: * + * Prototype testing for infrared and mc. + **************************************************************************/ + +#include +#include "includes.h" +#include "altera_avalon_pio_regs.h" +#include "altera_avalon_uart_regs.h" +#include "sys/alt_irq.h" +#include "alt_types.h" +#include "altera_up_avalon_rs232.h" +#include "altera_up_avalon_rs232_regs.h" + +#include "MotorHandler.h" +#include "Status.h" + +/* Task stacks */ +#define TASK_STACKSIZE 2048 +OS_STK ir_task_stk[TASK_STACKSIZE]; +OS_STK mc_task_stk[TASK_STACKSIZE]; +/* Task priorities */ +#define IR_TASK_PRIORITY 2 +#define MC_TASK_PRIORITY 1 + + +#define SW_READ 1 +#define SW_WRITE 2 +#define WRITE_FIFO_EMPTY 0x80 +#define READ_FIFO_EMPTY 0x0 +OS_EVENT *SWQ; +OS_EVENT *RS232Q; +INT8U err; + + +/* Error status */ +#define OK 0 + +/* Message queues */ +#define WAIT_FOREVER 0 + +// ==== INFRARED ==== + +/* Infrared message queue */ +#define IR_MAX_MESSAGES 4 +int ir_messages[IR_MAX_MESSAGES]; +OS_EVENT *ir_queue; + +/* Infrared messages */ +// Together these avoid passing 0 to the queue (which is not allowed since queue messages cannot be null) +// and invert pushbutton input (since the pushbutton returns 0 when it is pushed down). +#define IR_QUEUE_SEND_BASE 1 // Use: IR_QUEUE_SEND_BASE + IORD +#define IR_QUEUE_RECEIVE_BASE 2 // Use: IR_QUEUE_RECEIVE_BASE - OSQPend + + +MotorHandler *motor= new MotorHandler(); + + +// ==== mc + +#define mc_GUARD_TIME 1 + +void mc_task(void *pdata) +{ + printf("mc task\n"); + printf("MotorHandler [init"); + if (motor->init() == OK) { + printf("]\n\n"); + motor->forward(); + } else { + printf( ", error]\n"); + } + while(1){ +// motor->forward(); +// OSTimeDlyHMSM(0, 0, 2,0 ); + motor->backward(); + OSTimeDlyHMSM(0, 0, 2,0 ); + motor->left(); + OSTimeDlyHMSM(0, 0, 2,0 ); + motor->right(); + OSTimeDlyHMSM(0, 0, 2,0 ); + + } +} + + + +// ==== GENERAL + +void queue_init() { + ir_queue = OSQCreate((void**)&ir_messages, IR_MAX_MESSAGES); +} + +/* The main function creates the LCD task, registers the edge counter polling interrupt, + * and starts the OS. */ +int main(void) +{ + int status = OK; + // Initialize components. + queue_init(); + // Create the mc task. + OSTaskCreateExt(mc_task, + NULL, + &mc_task_stk[TASK_STACKSIZE - 1], + MC_TASK_PRIORITY, + MC_TASK_PRIORITY, + mc_task_stk, + TASK_STACKSIZE, + NULL, + 0); + + if (status == OK) { + OSStart(); + } + + return 0; +} + +/****************************************************************************** + * * + * License Agreement * + * * + * Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * + * All rights reserved. * + * * + * Permission is hereby granted, free of charge, to any person obtaining a * + * copy of this software and associated documentation files (the "Software"), * + * to deal in the Software without restriction, including without limitation * + * the rights to use, copy, modify, merge, publish, distribute, sublicense, * + * and/or sell copies of the Software, and to permit persons to whom the * + * Software is furnished to do so, subject to the following conditions: * + * * + * The above copyright notice and this permission notice shall be included in * + * all copies or substantial portions of the Software. * + * * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * + * DEALINGS IN THE SOFTWARE. * + * * + * This agreement shall be governed in all respects by the laws of the State * + * of California and by the laws of the United States of America. * + * Altera does not recommend, suggest or require that this reference design * + * file be used in conjunction or combination with any other product. * + ******************************************************************************/ diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/61/70c97b7080b000131eb0f6c547a05c39 b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/61/70c97b7080b000131eb0f6c547a05c39 new file mode 100644 index 00000000..041fb450 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/61/70c97b7080b000131eb0f6c547a05c39 @@ -0,0 +1,159 @@ +/************************************************************************* + * ARCap + * Amshu Gongal, Kenan Kigunda + * February 18, 2014 + ************************************************************************** + * Description: * + * Prototype testing for infrared and mc. + **************************************************************************/ + +#include +#include "includes.h" +#include "altera_avalon_pio_regs.h" +#include "altera_avalon_uart_regs.h" +#include "sys/alt_irq.h" +#include "alt_types.h" +#include "altera_up_avalon_rs232.h" +#include "altera_up_avalon_rs232_regs.h" + +#include "MotorHandler.h" +#include "Status.h" + +/* Task stacks */ +#define TASK_STACKSIZE 2048 +OS_STK ir_task_stk[TASK_STACKSIZE]; +OS_STK mc_task_stk[TASK_STACKSIZE]; +/* Task priorities */ +#define IR_TASK_PRIORITY 2 +#define MC_TASK_PRIORITY 1 + + +#define SW_READ 1 +#define SW_WRITE 2 +#define WRITE_FIFO_EMPTY 0x80 +#define READ_FIFO_EMPTY 0x0 +OS_EVENT *SWQ; +OS_EVENT *RS232Q; +INT8U err; + + +/* Error status */ +#define OK 0 + +/* Message queues */ +#define WAIT_FOREVER 0 + +// ==== INFRARED ==== + +/* Infrared message queue */ +#define IR_MAX_MESSAGES 4 +int ir_messages[IR_MAX_MESSAGES]; +OS_EVENT *ir_queue; + +/* Infrared messages */ +// Together these avoid passing 0 to the queue (which is not allowed since queue messages cannot be null) +// and invert pushbutton input (since the pushbutton returns 0 when it is pushed down). +#define IR_QUEUE_SEND_BASE 1 // Use: IR_QUEUE_SEND_BASE + IORD +#define IR_QUEUE_RECEIVE_BASE 2 // Use: IR_QUEUE_RECEIVE_BASE - OSQPend + + +MotorHandler *motor= new MotorHandler(); + + +// ==== mc + +#define mc_GUARD_TIME 1 + +void mc_task(void *pdata) +{ + printf("mc task\n"); + printf("MotorHandler [init"); + if (motor->init() == OK) { + printf("]\n\n"); + } else { + printf( ", error]\n"); + } + while(1){ + motor->forward(); + OSTimeDlyHMSM(0, 0, 5, 0); + motor->stop(); + OSTimeDlyHMSM(0, 0, 3,0); +// motor->left(); +// OSTimeDlyHMSM(0, 0, 5, 0); +// motor->stop(); +// OSTimeDlyHMSM(0, 0, 3,0); + motor->backward(); + OSTimeDlyHMSM(0, 0, 5,0); + motor->stop(); + OSTimeDlyHMSM(0, 0, 3,0); +// motor->right(); +// OSTimeDlyHMSM(0, 0,5,0); +// motor->stop(); +// OSTimeDlyHMSM(0, 0, 3,0); + + } +} + + + +// ==== GENERAL + +void queue_init() { + ir_queue = OSQCreate((void**)&ir_messages, IR_MAX_MESSAGES); +} + +/* The main function creates the LCD task, registers the edge counter polling interrupt, + * and starts the OS. */ +int main(void) +{ + int status = OK; + // Initialize components. + queue_init(); + // Create the mc task. + OSTaskCreateExt(mc_task, + NULL, + &mc_task_stk[TASK_STACKSIZE - 1], + MC_TASK_PRIORITY, + MC_TASK_PRIORITY, + mc_task_stk, + TASK_STACKSIZE, + NULL, + 0); + + if (status == OK) { + OSStart(); + } + + return 0; +} + +/****************************************************************************** + * * + * License Agreement * + * * + * Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * + * All rights reserved. * + * * + * Permission is hereby granted, free of charge, to any person obtaining a * + * copy of this software and associated documentation files (the "Software"), * + * to deal in the Software without restriction, including without limitation * + * the rights to use, copy, modify, merge, publish, distribute, sublicense, * + * and/or sell copies of the Software, and to permit persons to whom the * + * Software is furnished to do so, subject to the following conditions: * + * * + * The above copyright notice and this permission notice shall be included in * + * all copies or substantial portions of the Software. * + * * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * + * DEALINGS IN THE SOFTWARE. * + * * + * This agreement shall be governed in all respects by the laws of the State * + * of California and by the laws of the United States of America. * + * Altera does not recommend, suggest or require that this reference design * + * file be used in conjunction or combination with any other product. * + ******************************************************************************/ diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/64/4090373e83b000131eb0f6c547a05c39 b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/64/4090373e83b000131eb0f6c547a05c39 new file mode 100644 index 00000000..6d1d4c31 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/64/4090373e83b000131eb0f6c547a05c39 @@ -0,0 +1,102 @@ +/* + * MotorHandler.cpp + * + * Created on: 2014-03-03 + * Author: Amshu Gongal + */ + + +#include + +#include "altera_avalon_pio_regs.h" +#include "includes.h" +#include "system.h" + +#include "MotorHandler.h" + +#define WRITE_FIFO_EMPTY 0x80 +#define MOTOR_ENABLE 1 +#define MOTOR_RESET 0 + +// ALLOCATION +MotorHandler::MotorHandler() {} +MotorHandler::~MotorHandler() {} + + +// INITIALIZATION + +/* + * Initializes this handler. + * @return OK if the handler was initialized without error + */ +Status MotorHandler::init() { + // Enable the motor controller. + reset(); + // Open the serial device to send commands to the motor controller. + motor_dev = alt_up_rs232_open_dev(RS232_MOTOR_NAME); + //printf("%d", motor_dev); + if (motor_dev == NULL) { + return ERR_MOTOR_OPEN; + } else { + return OK; + } +} + +void MotorHandler::configure(){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_CHANGE_CONFIGURATION, "change configuration"); + send(0X01, "2 MOTOR CONFIG"); + printf("\n"); +} + +// MOTOR CONTROL + +/*Moves the given motor in specified direction by Motor Direction with specified + * Speed + * @param MotorDirection Motor and direction to move + * @param Speed the speed to move at + * @param string description of motor movement + */ + +void MotorHandler::move(char MotorDirection,char Speed,char * Description){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_DEVICE_TYPE, "device"); + send(MotorDirection, Description); + send(Speed, "speed"); + printf("\n"); +} + +// MOTOR CONTROL HELPERS +/* + * Sends a byte-length message to the motor controller. + * @param message - the message to send + * @param description - the string description of the message, for debugging + */ +void MotorHandler::send(char message, char *description) { + alt_u32 write_space; + // Check for write space. + write_space = alt_up_rs232_get_available_space_in_write_FIFO(motor_dev); + if (write_space >= WRITE_FIFO_EMPTY) { + // If space, write. + int status = alt_up_rs232_write_data(motor_dev, message); + printf("MotorHandler [message: 0x%02x, description: %s", message, description); + // Log errors. + if (status == OK) { + printf("]\n"); + } else { + printf(", error: cannot write]\n"); + } + } else { + // If no space, wait and retry. + printf("MotorHandler [message: 0x%02x, description: %s, error: no write space; retrying]\n", message, description); + OSTimeDlyHMSM(0, 0, 0, 10); + send(message, description); + } +} + +void MotorHandler::reset(){ + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 0); + OSTimeDlyHMSM(0, 0, 0,200 ); + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 1); + OSTimeDlyHMSM(0, 0, 0, 200); +} diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/66/20496af988b000131eb0f6c547a05c39 b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/66/20496af988b000131eb0f6c547a05c39 new file mode 100644 index 00000000..de916d92 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/66/20496af988b000131eb0f6c547a05c39 @@ -0,0 +1,133 @@ +/* + * MotorHandler.cpp + * + * Created on: 2014-03-03 + * Author: Amshu Gongal + */ + + +#include + +#include "altera_avalon_pio_regs.h" +#include "includes.h" +#include "system.h" + +#include "MotorHandler.h" + +#define WRITE_FIFO_EMPTY 0x80 +#define MOTOR_ENABLE 1 +#define MOTOR_RESET 0 + +// ALLOCATION +MotorHandler::MotorHandler() {} +MotorHandler::~MotorHandler() {} + + +// INITIALIZATION + +/* + * Initializes this handler. + * @return OK if the handler was initialized without error + */ +Status MotorHandler::init() { + // Enable the motor controller. + reset(); + // Open the serial device to send commands to the motor controller. + motor_dev = alt_up_rs232_open_dev(RS232_MOTOR_NAME); + //printf("%d", motor_dev); + if (motor_dev == NULL) { + return ERR_MOTOR_OPEN; + } else { + return OK; + } +} + +void MotorHandler::configure(){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_CHANGE_CONFIGURATION, "change configuration"); + send(0X01, "2 MOTOR CONFIG"); + printf("\n"); +} + +//Command Interpreter +/* + * Interprets the command from the network handler and sends move commands + * @param motor The motor to move eg. Left or Right + * @param motorDirection The direction of the given motor to move + * @param speed The speed the motor is to move + */ +void MotorHandler::motorCommand(string motor, string motorDirection, string speed){ + char motorID = interpretMotor(motor); + char Direction = interpretDirection(motorDirection, int(motorID)); + move(Direction, speed, "Move Motor"); +} + +char MotorHandler::interpretMotor(string motor){ + if(motor.compare(MOTOR_LEFT) == 0){ + return MOTOR_LEFT_CHAR; + } + else{ + return MOTOR_RIGHT_CHAR; + } +} + +char MotorHandler::interpretDirection(string direction, int motor){ + if(direction.compare(MOTOR_FORWARD) == 0){ + return (char) (motor*2 + 1); + } + else{ + return (char) (motor*2); + } +} + +// MOTOR CONTROL + +/*Moves the given motor in specified direction by Motor Direction with specified + * Speed + * @param MotorDirection Motor and direction to move + * @param Speed the speed to move at + * @param string description of motor movement + */ + +void MotorHandler::move(char MotorDirection,char Speed,char * Description){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_DEVICE_TYPE, "device"); + send(MotorDirection, Description); + send(Speed, "speed"); + printf("\n"); +} + +// MOTOR CONTROL HELPERS +/* + * Sends a byte-length message to the motor controller. + * @param message - the message to send + * @param description - the string description of the message, for debugging + */ +void MotorHandler::send(char message, char *description) { + alt_u32 write_space; + // Check for write space. + write_space = alt_up_rs232_get_available_space_in_write_FIFO(motor_dev); + if (write_space >= WRITE_FIFO_EMPTY) { + // If space, write. + int status = alt_up_rs232_write_data(motor_dev, message); + printf("MotorHandler [message: 0x%02x, description: %s", message, description); + // Log errors. + if (status == OK) { + printf("]\n"); + } else { + printf(", error: cannot write]\n"); + } + } else { + // If no space, wait and retry. + printf("MotorHandler [message: 0x%02x, description: %s, error: no write space; retrying]\n", message, description); + OSTimeDlyHMSM(0, 0, 0, 10); + send(message, description); + } +} + +void MotorHandler::reset(){ + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 0); + OSTimeDlyHMSM(0, 0, 0,200 ); + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 1); + OSTimeDlyHMSM(0, 0, 0, 200); +} diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/66/80badd09c5ab001312b0c9eb155e9cea b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/66/80badd09c5ab001312b0c9eb155e9cea new file mode 100644 index 00000000..fe712a22 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/66/80badd09c5ab001312b0c9eb155e9cea @@ -0,0 +1,76 @@ +/* + * MotorHandler.h + * + * Created on: 2014-03-03 + * Author: Amshu Gongal + */ + +#ifndef MOTORHANDLER_H_ +#define MOTORHANDLER_H_ + +#include "altera_up_avalon_rs232.h" +#include "altera_up_avalon_rs232_regs.h" +#include +#include "Status.h" + +// Motor messages are LSB first +#define MOTOR_START_BYTE 0x80 +#define MOTOR_DEVICE_TYPE 0x00 +#define MOTOR_BOTH_FORWARD 0x01 // both motor forward +#define MOTOR_BOTH_BACKWARD 0x00 //both motor backward +#define MOTOR_MOTOR1_BACKWARD 0x40 // motor 1 backward +#define MOTOR_MOTOR2_BACKWARD 0x60 // motor 2 backward +#define MOTOR_MOTOR1_FORWARD 0x05 // motor 1 forward +#define MOTOR_MOTOR2_FORWARD 0x07 // motor 2 forward +#define MOTOR_CONST_SPEED 0x7F +#define MOTOR_STOP_SPEED 0x00 +#define MOTOR_CHANGE_CONFIGURATION 0X02 + +class MotorHandler { +public: + MotorHandler(); + virtual ~MotorHandler(); + + /* + * Initializes this handler. + * @return OK if the handler was initialized without error + */ + Status init(); + + void forward(); + void backward(); + void right(); + void left(); + void stop(); + void configure(); + void test(); + void reset(); + +private: + /* The device used to send serial commands to the motor controller. */ + alt_up_rs232_dev *motor_dev; + + /* + * Moves in the given direction at constant speed. + * @param direction - the motor and direction to move in, e.g. MOTOR_MOTOR1_FORWARD + * @param description - the string description of the movement, for debugging + */ + void move(char direction, char *description); + + /* + * Moves in the given direction and speed. + * @param direction - the motor and direction to move in, e.g. MOTOR_MOTOR1_FORWARD + * @param speed - the speed to move at, i.e. MOTOR_CONST_SPEED or MOTOR_STOP_SPEED + * @param description - the string description of the movement, for debugging + */ + void move(char direction, char speed, char *description); + + /* + * Sends a byte-length message to the motor controller. + * @param message - the message to send + * @param description - the string description of the message, for debugging + */ + void send(char message, char *description); +}; + +#endif /* MOTORHANDLER_H_ */ diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/67/d0be64b5acab001311f2ce252b4696cb b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/67/d0be64b5acab001311f2ce252b4696cb new file mode 100644 index 00000000..1165a646 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/67/d0be64b5acab001311f2ce252b4696cb @@ -0,0 +1,76 @@ +/* + * MotorHandler.h + * + * Created on: 2014-03-03 + * Author: Amshu Gongal + */ + +#ifndef MOTORHANDLER_H_ +#define MOTORHANDLER_H_ + +#include "altera_up_avalon_rs232.h" +#include "altera_up_avalon_rs232_regs.h" +#include +#include "Status.h" + +// Motor messages are LSB first +#define MOTOR_START_BYTE 0x80 +#define MOTOR_DEVICE_TYPE 0x00 +#define MOTOR_BOTH_FORWARD 0x01 // both motor forward +#define MOTOR_BOTH_BACKWARD 0x00 //both motor backward +#define MOTOR_MOTOR1_BACKWARD 0x40 // motor 1 backward +#define MOTOR_MOTOR2_BACKWARD 0x60 // motor 2 backward +#define MOTOR_MOTOR1_FORWARD 0x05 // motor 1 forward +#define MOTOR_MOTOR2_FORWARD 0x07 // motor 2 forward +#define MOTOR_CONST_SPEED 0x5F +#define MOTOR_STOP_SPEED 0x00 +#define MOTOR_CHANGE_CONFIGURATION 0X02 + +class MotorHandler { +public: + MotorHandler(); + virtual ~MotorHandler(); + + /* + * Initializes this handler. + * @return OK if the handler was initialized without error + */ + Status init(); + + void forward(); + void backward(); + void right(); + void left(); + void stop(); + void configure(); + void test(); + void reset(); + +private: + /* The device used to send serial commands to the motor controller. */ + alt_up_rs232_dev *motor_dev; + + /* + * Moves in the given direction at constant speed. + * @param direction - the motor and direction to move in, e.g. MOTOR_MOTOR1_FORWARD + * @param description - the string description of the movement, for debugging + */ + void move(char direction, char *description); + + /* + * Moves in the given direction and speed. + * @param direction - the motor and direction to move in, e.g. MOTOR_MOTOR1_FORWARD + * @param speed - the speed to move at, i.e. MOTOR_CONST_SPEED or MOTOR_STOP_SPEED + * @param description - the string description of the movement, for debugging + */ + void move(char direction, char speed, char *description); + + /* + * Sends a byte-length message to the motor controller. + * @param message - the message to send + * @param description - the string description of the message, for debugging + */ + void send(char message, char *description); +}; + +#endif /* MOTORHANDLER_H_ */ diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/69/c063f2b386b000131eb0f6c547a05c39 b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/69/c063f2b386b000131eb0f6c547a05c39 new file mode 100644 index 00000000..6e7508b4 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/69/c063f2b386b000131eb0f6c547a05c39 @@ -0,0 +1,118 @@ +/* + * MotorHandler.cpp + * + * Created on: 2014-03-03 + * Author: Amshu Gongal + */ + + +#include + +#include "altera_avalon_pio_regs.h" +#include "includes.h" +#include "system.h" + +#include "MotorHandler.h" + +#define WRITE_FIFO_EMPTY 0x80 +#define MOTOR_ENABLE 1 +#define MOTOR_RESET 0 + +// ALLOCATION +MotorHandler::MotorHandler() {} +MotorHandler::~MotorHandler() {} + + +// INITIALIZATION + +/* + * Initializes this handler. + * @return OK if the handler was initialized without error + */ +Status MotorHandler::init() { + // Enable the motor controller. + reset(); + // Open the serial device to send commands to the motor controller. + motor_dev = alt_up_rs232_open_dev(RS232_MOTOR_NAME); + //printf("%d", motor_dev); + if (motor_dev == NULL) { + return ERR_MOTOR_OPEN; + } else { + return OK; + } +} + +void MotorHandler::configure(){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_CHANGE_CONFIGURATION, "change configuration"); + send(0X01, "2 MOTOR CONFIG"); + printf("\n"); +} + +//Command Interpreter +/* + * Interprets the command from the network handler and sends move commands + * @param motor The motor to move eg. Left or Right + * @param motorDirection The direction of the given motor to move + * @param speed The speed the motor is to move + */ +void MotorHandler::motorCommand(string motor, string motorDirection, string speed){ + if(motor.compare(MOTOR_LEFT) == 0){ + + } + else if (motor.compare(MOTOR_RIGHT) == 0){ + + } +} + +// MOTOR CONTROL + +/*Moves the given motor in specified direction by Motor Direction with specified + * Speed + * @param MotorDirection Motor and direction to move + * @param Speed the speed to move at + * @param string description of motor movement + */ + +void MotorHandler::move(char MotorDirection,char Speed,char * Description){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_DEVICE_TYPE, "device"); + send(MotorDirection, Description); + send(Speed, "speed"); + printf("\n"); +} + +// MOTOR CONTROL HELPERS +/* + * Sends a byte-length message to the motor controller. + * @param message - the message to send + * @param description - the string description of the message, for debugging + */ +void MotorHandler::send(char message, char *description) { + alt_u32 write_space; + // Check for write space. + write_space = alt_up_rs232_get_available_space_in_write_FIFO(motor_dev); + if (write_space >= WRITE_FIFO_EMPTY) { + // If space, write. + int status = alt_up_rs232_write_data(motor_dev, message); + printf("MotorHandler [message: 0x%02x, description: %s", message, description); + // Log errors. + if (status == OK) { + printf("]\n"); + } else { + printf(", error: cannot write]\n"); + } + } else { + // If no space, wait and retry. + printf("MotorHandler [message: 0x%02x, description: %s, error: no write space; retrying]\n", message, description); + OSTimeDlyHMSM(0, 0, 0, 10); + send(message, description); + } +} + +void MotorHandler::reset(){ + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 0); + OSTimeDlyHMSM(0, 0, 0,200 ); + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 1); + OSTimeDlyHMSM(0, 0, 0, 200); +} diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/6a/d06e4d69a6ab001311f2ce252b4696cb b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/6a/d06e4d69a6ab001311f2ce252b4696cb new file mode 100644 index 00000000..d94125ca --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/6a/d06e4d69a6ab001311f2ce252b4696cb @@ -0,0 +1,153 @@ +/* + * MotorHandler.cpp + * + * Created on: 2014-03-03 + * Author: Amshu Gongal + */ + + +#include + +#include "altera_avalon_pio_regs.h" +#include "includes.h" +#include "system.h" + +#include "MotorHandler.h" + +#define WRITE_FIFO_EMPTY 0x80 +#define MOTOR_ENABLE 1 +#define MOTOR_RESET 0 + +// ALLOCATION +MotorHandler::MotorHandler() {} +MotorHandler::~MotorHandler() {} + +// INITIALIZATION + +/* + * Initializes this handler. + * @return OK if the handler was initialized without error + */ +Status MotorHandler::init() { + // Enable the motor controller. + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, MOTOR_ENABLE); + // Open the serial device to send commands to the motor controller. + motor_dev = alt_up_rs232_open_dev(RS232_MOTOR_NAME); + //printf("%d", motor_dev); + if (motor_dev == NULL) { + return ERR_MOTOR_OPEN; + } else { + return OK; + } +} + +void MotorHandler::configure(){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_CHANGE_CONFIGURATION, "change configuration"); + send(0X01, "2 MOTOR CONFIG"); + printf("\n"); +} +// TESTING + +void MotorHandler::test() { + send(MOTOR_START_BYTE, "test start"); +} + +// MOTOR CONTROL + +/* + * Move rover forward by activating both motors. + */ +void MotorHandler::forward() { + move(MOTOR_MOTOR1_FORWARD, "motor 1 forward"); + move(MOTOR_MOTOR2_FORWARD, "motor 2 forward"); +} + +/* + * Move rover backward by activating both motor backwards. + */ +void MotorHandler::backward() { + move(MOTOR_MOTOR1_BACKWARD, "motor 1 backward"); + move(MOTOR_MOTOR2_BACKWARD, "motor 2 backward"); +} + +/* + * Turn rover left. + */ +void MotorHandler::left() { + move(MOTOR_MOTOR2_FORWARD, "motor 1 forward"); +} + +/* + * Turn rover right. + */ +void MotorHandler::right() { + move(MOTOR_MOTOR2_FORWARD, "motor 2 forward"); +} + +/* + * Stop the rover. + */ +void MotorHandler::stop() { + move(MOTOR_MOTOR1_FORWARD, MOTOR_STOP_SPEED, "motor 1 stop"); + move(MOTOR_MOTOR2_FORWARD, MOTOR_STOP_SPEED, "motor 2 stop"); +} + +// MOTOR CONTROL HELPERS + +/* + * Moves in the given direction at constant speed. + * @param direction - the motor and direction to move in, e.g. MOTOR_MOTOR1_FORWARD + * @param description - the string description of the movement, for debugging + */ +void MotorHandler::move(char direction, char *description) { + move(direction, MOTOR_CONST_SPEED, description); +} + +/* + * Moves in the given direction and speed. + * @param direction - the motor and direction to move in, e.g. MOTOR_MOTOR1_FORWARD + * @param speed - the speed to move at, i.e. MOTOR_CONST_SPEED or MOTOR_STOP_SPEED + * @param description - the string description of the movement, for debugging + */ +void MotorHandler::move(char direction, char speed, char *description) { + send(MOTOR_START_BYTE, "start"); + send(MOTOR_DEVICE_TYPE, "device"); + send(direction, description); + send(speed, "speed"); + printf("\n"); +} + +/* + * Sends a byte-length message to the motor controller. + * @param message - the message to send + * @param description - the string description of the message, for debugging + */ +void MotorHandler::send(char message, char *description) { + alt_u32 write_space; + // Check for write space. + write_space = alt_up_rs232_get_available_space_in_write_FIFO(motor_dev); + if (write_space >= WRITE_FIFO_EMPTY) { + // If space, write. + int status = alt_up_rs232_write_data(motor_dev, message); + printf("MotorHandler [message: 0x%02x, description: %s", message, description); + // Log errors. + if (status == OK) { + printf("]\n"); + } else { + printf(", error: cannot write]\n"); + } + } else { + // If no space, wait and retry. + printf("MotorHandler [message: 0x%02x, description: %s, error: no write space; retrying]\n", message, description); + OSTimeDlyHMSM(0, 0, 0, 10); + send(message, description); + } +} + +void MotorHandler::reset(){ + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 0); + OSTimeDlyHMSM(0, 0, 2,0 ); + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 1); + OSTimeDlyHMSM(0, 0, 2, 100); +} diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/6d/b08b19358aab001311dbfe770f133bca b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/6d/b08b19358aab001311dbfe770f133bca new file mode 100644 index 00000000..6d74e7d4 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/6d/b08b19358aab001311dbfe770f133bca @@ -0,0 +1,143 @@ +/************************************************************************* + * ARCap + * Amshu Gongal, Kenan Kigunda + * February 18, 2014 + ************************************************************************** + * Description: * + * Prototype testing for infrared and mc. + **************************************************************************/ + +#include +#include "includes.h" +#include "altera_avalon_pio_regs.h" +#include "altera_avalon_uart_regs.h" +#include "sys/alt_irq.h" +#include "alt_types.h" +#include "altera_up_avalon_rs232.h" +#include "altera_up_avalon_rs232_regs.h" + +#include "MotorHandler.h" +#include "Status.h" + +/* Task stacks */ +#define TASK_STACKSIZE 2048 +OS_STK ir_task_stk[TASK_STACKSIZE]; +OS_STK mc_task_stk[TASK_STACKSIZE]; +/* Task priorities */ +#define IR_TASK_PRIORITY 2 +#define MC_TASK_PRIORITY 1 + + +#define SW_READ 1 +#define SW_WRITE 2 +#define WRITE_FIFO_EMPTY 0x80 +#define READ_FIFO_EMPTY 0x0 +OS_EVENT *SWQ; +OS_EVENT *RS232Q; +INT8U err; + + +/* Error status */ +#define OK 0 + +/* Message queues */ +#define WAIT_FOREVER 0 + +// ==== INFRARED ==== + +/* Infrared message queue */ +#define IR_MAX_MESSAGES 4 +int ir_messages[IR_MAX_MESSAGES]; +OS_EVENT *ir_queue; + +/* Infrared messages */ +// Together these avoid passing 0 to the queue (which is not allowed since queue messages cannot be null) +// and invert pushbutton input (since the pushbutton returns 0 when it is pushed down). +#define IR_QUEUE_SEND_BASE 1 // Use: IR_QUEUE_SEND_BASE + IORD +#define IR_QUEUE_RECEIVE_BASE 2 // Use: IR_QUEUE_RECEIVE_BASE - OSQPend + + +MotorHandler *motor= new MotorHandler(); + + +// ==== mc + +#define mc_GUARD_TIME 1 + +void mc_task(void *pdata) +{ + printf("mc task\n"); + printf("MotorHandler [init"); + if (motor->init() == OK) { + printf("]\n\n"); + motor->configure(); + } else { + printf( ", error]\n"); + } + motor->forward(); +} + + + +// ==== GENERAL + +void queue_init() { + ir_queue = OSQCreate((void**)&ir_messages, IR_MAX_MESSAGES); +} + +/* The main function creates the LCD task, registers the edge counter polling interrupt, + * and starts the OS. */ +int main(void) +{ + int status = OK; + // Initialize components. + queue_init(); + + // Create the mc task. + OSTaskCreateExt(mc_task, + NULL, + &mc_task_stk[TASK_STACKSIZE - 1], + MC_TASK_PRIORITY, + MC_TASK_PRIORITY, + mc_task_stk, + TASK_STACKSIZE, + NULL, + 0); + + if (status == OK) { + OSStart(); + } + + return 0; +} + +/****************************************************************************** + * * + * License Agreement * + * * + * Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * + * All rights reserved. * + * * + * Permission is hereby granted, free of charge, to any person obtaining a * + * copy of this software and associated documentation files (the "Software"), * + * to deal in the Software without restriction, including without limitation * + * the rights to use, copy, modify, merge, publish, distribute, sublicense, * + * and/or sell copies of the Software, and to permit persons to whom the * + * Software is furnished to do so, subject to the following conditions: * + * * + * The above copyright notice and this permission notice shall be included in * + * all copies or substantial portions of the Software. * + * * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * + * DEALINGS IN THE SOFTWARE. * + * * + * This agreement shall be governed in all respects by the laws of the State * + * of California and by the laws of the United States of America. * + * Altera does not recommend, suggest or require that this reference design * + * file be used in conjunction or combination with any other product. * + ******************************************************************************/ diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/6e/2089764780b000131eb0f6c547a05c39 b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/6e/2089764780b000131eb0f6c547a05c39 new file mode 100644 index 00000000..cef219b4 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/6e/2089764780b000131eb0f6c547a05c39 @@ -0,0 +1,74 @@ +/* + * MotorHandler.h + * + * Created on: 2014-03-03 + * Author: Amshu Gongal + */ + +#ifndef MOTORHANDLER_H_ +#define MOTORHANDLER_H_ + +#include "altera_up_avalon_rs232.h" +#include "altera_up_avalon_rs232_regs.h" +#include +#include "Status.h" + +// Motor messages are LSB first +#define MOTOR_START_BYTE 0x80 +#define MOTOR_DEVICE_TYPE 0x00 +#define MOTOR_LEFT_BACKWARD 0x04 // motor 1 backward +#define MOTOR_RIGHT_BACKWARD 0x06 // motor 2 backward +#define MOTOR_LEFT_FORWARD 0x05 // motor 1 forward +#define MOTOR_RIGHT_FORWARD 0x07 // motor 2 forward +#define MOTOR_CONST_SPEED 0x5F +#define MOTOR_STOP_SPEED 0x00 +#define MOTOR_CHANGE_CONFIGURATION 0X02 + +class MotorHandler { +public: + MotorHandler(); + virtual ~MotorHandler(); + + /* + * Initializes this handler. + * @return OK if the handler was initialized without error + */ + Status init(); + void move(char , char, char *); + void forward(); + void backward(); + void right(); + void left(); + void stop(); + void configure(); + void test(); + void reset(); + +private: + /* The device used to send serial commands to the motor controller. */ + alt_up_rs232_dev *motor_dev; + + /* + * Moves in the given direction at constant speed. + * @param direction - the motor and direction to move in, e.g. MOTOR_MOTOR1_FORWARD + * @param description - the string description of the movement, for debugging + */ + void move(char direction, char *description); + + /* + * Moves in the given direction and speed. + * @param direction - the motor and direction to move in, e.g. MOTOR_MOTOR1_FORWARD + * @param speed - the speed to move at, i.e. MOTOR_CONST_SPEED or MOTOR_STOP_SPEED + * @param description - the string description of the movement, for debugging + */ + void move(char direction, char speed, char *description); + + /* + * Sends a byte-length message to the motor controller. + * @param message - the message to send + * @param description - the string description of the message, for debugging + */ + void send(char message, char *description); +}; + +#endif /* MOTORHANDLER_H_ */ diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/7/20c1611887b000131eb0f6c547a05c39 b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/7/20c1611887b000131eb0f6c547a05c39 new file mode 100644 index 00000000..aa22ceb0 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/7/20c1611887b000131eb0f6c547a05c39 @@ -0,0 +1,122 @@ +/* + * MotorHandler.cpp + * + * Created on: 2014-03-03 + * Author: Amshu Gongal + */ + + +#include + +#include "altera_avalon_pio_regs.h" +#include "includes.h" +#include "system.h" + +#include "MotorHandler.h" + +#define WRITE_FIFO_EMPTY 0x80 +#define MOTOR_ENABLE 1 +#define MOTOR_RESET 0 + +// ALLOCATION +MotorHandler::MotorHandler() {} +MotorHandler::~MotorHandler() {} + + +// INITIALIZATION + +/* + * Initializes this handler. + * @return OK if the handler was initialized without error + */ +Status MotorHandler::init() { + // Enable the motor controller. + reset(); + // Open the serial device to send commands to the motor controller. + motor_dev = alt_up_rs232_open_dev(RS232_MOTOR_NAME); + //printf("%d", motor_dev); + if (motor_dev == NULL) { + return ERR_MOTOR_OPEN; + } else { + return OK; + } +} + +void MotorHandler::configure(){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_CHANGE_CONFIGURATION, "change configuration"); + send(0X01, "2 MOTOR CONFIG"); + printf("\n"); +} + +//Command Interpreter +/* + * Interprets the command from the network handler and sends move commands + * @param motor The motor to move eg. Left or Right + * @param motorDirection The direction of the given motor to move + * @param speed The speed the motor is to move + */ +void MotorHandler::motorCommand(string motor, string motorDirection, string speed){ + if(motor.compare(MOTOR_LEFT) == 0){ + + } + else if (motor.compare(MOTOR_RIGHT) == 0){ + + } +} + +char MotorHandler::interpretMotor(string motor){ + +} + +// MOTOR CONTROL + +/*Moves the given motor in specified direction by Motor Direction with specified + * Speed + * @param MotorDirection Motor and direction to move + * @param Speed the speed to move at + * @param string description of motor movement + */ + +void MotorHandler::move(char MotorDirection,char Speed,char * Description){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_DEVICE_TYPE, "device"); + send(MotorDirection, Description); + send(Speed, "speed"); + printf("\n"); +} + +// MOTOR CONTROL HELPERS +/* + * Sends a byte-length message to the motor controller. + * @param message - the message to send + * @param description - the string description of the message, for debugging + */ +void MotorHandler::send(char message, char *description) { + alt_u32 write_space; + // Check for write space. + write_space = alt_up_rs232_get_available_space_in_write_FIFO(motor_dev); + if (write_space >= WRITE_FIFO_EMPTY) { + // If space, write. + int status = alt_up_rs232_write_data(motor_dev, message); + printf("MotorHandler [message: 0x%02x, description: %s", message, description); + // Log errors. + if (status == OK) { + printf("]\n"); + } else { + printf(", error: cannot write]\n"); + } + } else { + // If no space, wait and retry. + printf("MotorHandler [message: 0x%02x, description: %s, error: no write space; retrying]\n", message, description); + OSTimeDlyHMSM(0, 0, 0, 10); + send(message, description); + } +} + +void MotorHandler::reset(){ + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 0); + OSTimeDlyHMSM(0, 0, 0,200 ); + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 1); + OSTimeDlyHMSM(0, 0, 0, 200); +} diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/7/8097b03f8ab000131eb0f6c547a05c39 b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/7/8097b03f8ab000131eb0f6c547a05c39 new file mode 100644 index 00000000..11d84477 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/7/8097b03f8ab000131eb0f6c547a05c39 @@ -0,0 +1,135 @@ +/* + * MotorHandler.cpp + * + * Created on: 2014-03-03 + * Author: Amshu Gongal + */ + + +#include +#include + +#include "altera_avalon_pio_regs.h" +#include "includes.h" +#include "system.h" + +#include "MotorHandler.h" + +#define WRITE_FIFO_EMPTY 0x80 +#define MOTOR_ENABLE 1 +#define MOTOR_RESET 0 + +// ALLOCATION +MotorHandler::MotorHandler() {} +MotorHandler::~MotorHandler() {} + + +// INITIALIZATION + +/* + * Initializes this handler. + * @return OK if the handler was initialized without error + */ +Status MotorHandler::init() { + // Enable the motor controller. + reset(); + // Open the serial device to send commands to the motor controller. + motor_dev = alt_up_rs232_open_dev(RS232_MOTOR_NAME); + //printf("%d", motor_dev); + if (motor_dev == NULL) { + return ERR_MOTOR_OPEN; + } else { + return OK; + } +} + +void MotorHandler::configure(){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_CHANGE_CONFIGURATION, "change configuration"); + send(0X01, "2 MOTOR CONFIG"); + printf("\n"); +} + +//Command Interpreter +/* + * Interprets the command from the network handler and sends move commands + * @param motor The motor to move eg. Left or Right + * @param motorDirection The direction of the given motor to move + * @param speed The speed the motor is to move + */ +void MotorHandler::motorCommand(string motor, string motorDirection, string speed){ + char motorID = interpretMotor(motor); + char directionByte = interpretDirection(motorDirection, int(motorID)); + int speedByte = strtol(speed.c_str(), NULL, 0); + move(directionByte, speedByte, "Move Motor"); +} + +char MotorHandler::interpretMotor(string motor){ + if(motor.compare(MOTOR_LEFT) == 0){ + return MOTOR_LEFT_CHAR; + } + else{ + return MOTOR_RIGHT_CHAR; + } +} + +char MotorHandler::interpretDirection(string direction, int motor){ + if(direction.compare(MOTOR_FORWARD) == 0){ + return (char) (motor*2 + 1); + } + else{ + return (char) (motor*2); + } +} + +// MOTOR CONTROL + +/*Moves the given motor in specified direction by Motor Direction with specified + * Speed + * @param MotorDirection Motor and direction to move + * @param Speed the speed to move at + * @param string description of motor movement + */ + +void MotorHandler::move(char MotorDirection,char Speed,char * Description){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_DEVICE_TYPE, "device"); + send(MotorDirection, Description); + send(Speed, "speed"); + printf("\n"); +} + +// MOTOR CONTROL HELPERS +/* + * Sends a byte-length message to the motor controller. + * @param message - the message to send + * @param description - the string description of the message, for debugging + */ +void MotorHandler::send(char message, char *description) { + alt_u32 write_space; + // Check for write space. + write_space = alt_up_rs232_get_available_space_in_write_FIFO(motor_dev); + if (write_space >= WRITE_FIFO_EMPTY) { + // If space, write. + int status = alt_up_rs232_write_data(motor_dev, message); + printf("MotorHandler [message: 0x%02x, description: %s", message, description); + // Log errors. + if (status == OK) { + printf("]\n"); + } else { + printf(", error: cannot write]\n"); + } + } else { + // If no space, wait and retry. + printf("MotorHandler [message: 0x%02x, description: %s, error: no write space; retrying]\n", message, description); + OSTimeDlyHMSM(0, 0, 0, 10); + send(message, description); + } +} + +void MotorHandler::reset(){ + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 0); + OSTimeDlyHMSM(0, 0, 0,200 ); + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 1); + OSTimeDlyHMSM(0, 0, 0, 200); +} diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/7/c0e8dececcab001312eeeea4d67ccb1b b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/7/c0e8dececcab001312eeeea4d67ccb1b new file mode 100644 index 00000000..f5a8981b --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/7/c0e8dececcab001312eeeea4d67ccb1b @@ -0,0 +1,145 @@ +/************************************************************************* + * ARCap + * Amshu Gongal, Kenan Kigunda + * February 18, 2014 + ************************************************************************** + * Description: * + * Prototype testing for infrared and mc. + **************************************************************************/ + +#include +#include "includes.h" +#include "altera_avalon_pio_regs.h" +#include "altera_avalon_uart_regs.h" +#include "sys/alt_irq.h" +#include "alt_types.h" +#include "altera_up_avalon_rs232.h" +#include "altera_up_avalon_rs232_regs.h" + +#include "MotorHandler.h" +#include "Status.h" + +/* Task stacks */ +#define TASK_STACKSIZE 2048 +OS_STK ir_task_stk[TASK_STACKSIZE]; +OS_STK mc_task_stk[TASK_STACKSIZE]; +/* Task priorities */ +#define IR_TASK_PRIORITY 2 +#define MC_TASK_PRIORITY 1 + + +#define SW_READ 1 +#define SW_WRITE 2 +#define WRITE_FIFO_EMPTY 0x80 +#define READ_FIFO_EMPTY 0x0 +OS_EVENT *SWQ; +OS_EVENT *RS232Q; +INT8U err; + + +/* Error status */ +#define OK 0 + +/* Message queues */ +#define WAIT_FOREVER 0 + +// ==== INFRARED ==== + +/* Infrared message queue */ +#define IR_MAX_MESSAGES 4 +int ir_messages[IR_MAX_MESSAGES]; +OS_EVENT *ir_queue; + +/* Infrared messages */ +// Together these avoid passing 0 to the queue (which is not allowed since queue messages cannot be null) +// and invert pushbutton input (since the pushbutton returns 0 when it is pushed down). +#define IR_QUEUE_SEND_BASE 1 // Use: IR_QUEUE_SEND_BASE + IORD +#define IR_QUEUE_RECEIVE_BASE 2 // Use: IR_QUEUE_RECEIVE_BASE - OSQPend + + +MotorHandler *motor= new MotorHandler(); + + +// ==== mc + +#define mc_GUARD_TIME 1 + +void mc_task(void *pdata) +{ + printf("mc task\n"); + printf("MotorHandler [init"); + if (motor->init() == OK) { + printf("]\n\n"); + motor->right(); + } else { + printf( ", error]\n"); + } + while(1){ + motor->right(); + + } +} + + + +// ==== GENERAL + +void queue_init() { + ir_queue = OSQCreate((void**)&ir_messages, IR_MAX_MESSAGES); +} + +/* The main function creates the LCD task, registers the edge counter polling interrupt, + * and starts the OS. */ +int main(void) +{ + int status = OK; + // Initialize components. + queue_init(); + // Create the mc task. + OSTaskCreateExt(mc_task, + NULL, + &mc_task_stk[TASK_STACKSIZE - 1], + MC_TASK_PRIORITY, + MC_TASK_PRIORITY, + mc_task_stk, + TASK_STACKSIZE, + NULL, + 0); + + if (status == OK) { + OSStart(); + } + + return 0; +} + +/****************************************************************************** + * * + * License Agreement * + * * + * Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * + * All rights reserved. * + * * + * Permission is hereby granted, free of charge, to any person obtaining a * + * copy of this software and associated documentation files (the "Software"), * + * to deal in the Software without restriction, including without limitation * + * the rights to use, copy, modify, merge, publish, distribute, sublicense, * + * and/or sell copies of the Software, and to permit persons to whom the * + * Software is furnished to do so, subject to the following conditions: * + * * + * The above copyright notice and this permission notice shall be included in * + * all copies or substantial portions of the Software. * + * * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * + * DEALINGS IN THE SOFTWARE. * + * * + * This agreement shall be governed in all respects by the laws of the State * + * of California and by the laws of the United States of America. * + * Altera does not recommend, suggest or require that this reference design * + * file be used in conjunction or combination with any other product. * + ******************************************************************************/ diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/7/e008c4bfb6ab00131274ac4b6fee418c b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/7/e008c4bfb6ab00131274ac4b6fee418c new file mode 100644 index 00000000..bb836177 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/7/e008c4bfb6ab00131274ac4b6fee418c @@ -0,0 +1,153 @@ +/* + * MotorHandler.cpp + * + * Created on: 2014-03-03 + * Author: Amshu Gongal + */ + + +#include + +#include "altera_avalon_pio_regs.h" +#include "includes.h" +#include "system.h" + +#include "MotorHandler.h" + +#define WRITE_FIFO_EMPTY 0x80 +#define MOTOR_ENABLE 1 +#define MOTOR_RESET 0 + +// ALLOCATION +MotorHandler::MotorHandler() {} +MotorHandler::~MotorHandler() {} + +// INITIALIZATION + +/* + * Initializes this handler. + * @return OK if the handler was initialized without error + */ +Status MotorHandler::init() { + // Enable the motor controller. + reset(); + // Open the serial device to send commands to the motor controller. + motor_dev = alt_up_rs232_open_dev(RS232_MOTOR_NAME); + //printf("%d", motor_dev); + if (motor_dev == NULL) { + return ERR_MOTOR_OPEN; + } else { + return OK; + } +} + +void MotorHandler::configure(){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_CHANGE_CONFIGURATION, "change configuration"); + send(0X01, "2 MOTOR CONFIG"); + printf("\n"); +} +// TESTING + +void MotorHandler::test() { + send(MOTOR_START_BYTE, "test start"); +} + +// MOTOR CONTROL + +/* + * Move rover forward by activating both motors. + */ +void MotorHandler::forward() { + move(MOTOR_MOTOR1_FORWARD, "motor 1 forward"); + move(MOTOR_MOTOR2_FORWARD, "motor 2 forward"); +} + +/* + * Move rover backward by activating both motor backwards. + */ +void MotorHandler::backward() { + move(MOTOR_BOTH_BACKWARD, "both motors backward"); +// move(MOTOR_MOTOR2_BACKWARD, "motor 2 backward"); +} + +/* + * Turn rover left. + */ +void MotorHandler::left() { + move(MOTOR_MOTOR2_FORWARD, "motor 1 forward"); +} + +/* + * Turn rover right. + */ +void MotorHandler::right() { + move(MOTOR_MOTOR2_FORWARD, "motor 2 forward"); +} + +/* + * Stop the rover. + */ +void MotorHandler::stop() { + move(MOTOR_MOTOR1_FORWARD, MOTOR_STOP_SPEED, "motor 1 stop"); + move(MOTOR_MOTOR2_FORWARD, MOTOR_STOP_SPEED, "motor 2 stop"); +} + +// MOTOR CONTROL HELPERS + +/* + * Moves in the given direction at constant speed. + * @param direction - the motor and direction to move in, e.g. MOTOR_MOTOR1_FORWARD + * @param description - the string description of the movement, for debugging + */ +void MotorHandler::move(char direction, char *description) { + move(direction, MOTOR_CONST_SPEED, description); +} + +/* + * Moves in the given direction and speed. + * @param direction - the motor and direction to move in, e.g. MOTOR_MOTOR1_FORWARD + * @param speed - the speed to move at, i.e. MOTOR_CONST_SPEED or MOTOR_STOP_SPEED + * @param description - the string description of the movement, for debugging + */ +void MotorHandler::move(char direction, char speed, char *description) { + send(MOTOR_START_BYTE, "start"); + send(MOTOR_DEVICE_TYPE, "device"); + send(direction, description); + send(speed, "speed"); + printf("\n"); +} + +/* + * Sends a byte-length message to the motor controller. + * @param message - the message to send + * @param description - the string description of the message, for debugging + */ +void MotorHandler::send(char message, char *description) { + alt_u32 write_space; + // Check for write space. + write_space = alt_up_rs232_get_available_space_in_write_FIFO(motor_dev); + if (write_space >= WRITE_FIFO_EMPTY) { + // If space, write. + int status = alt_up_rs232_write_data(motor_dev, message); + printf("MotorHandler [message: 0x%02x, description: %s", message, description); + // Log errors. + if (status == OK) { + printf("]\n"); + } else { + printf(", error: cannot write]\n"); + } + } else { + // If no space, wait and retry. + printf("MotorHandler [message: 0x%02x, description: %s, error: no write space; retrying]\n", message, description); + OSTimeDlyHMSM(0, 0, 0, 10); + send(message, description); + } +} + +void MotorHandler::reset(){ + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 0); + OSTimeDlyHMSM(0, 0, 0,200 ); + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 1); + OSTimeDlyHMSM(0, 0, 0, 200); +} diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/75/f005280880b000131eb0f6c547a05c39 b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/75/f005280880b000131eb0f6c547a05c39 new file mode 100644 index 00000000..34221b9f --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/75/f005280880b000131eb0f6c547a05c39 @@ -0,0 +1,76 @@ +/* + * MotorHandler.h + * + * Created on: 2014-03-03 + * Author: Amshu Gongal + */ + +#ifndef MOTORHANDLER_H_ +#define MOTORHANDLER_H_ + +#include "altera_up_avalon_rs232.h" +#include "altera_up_avalon_rs232_regs.h" +#include +#include "Status.h" + +// Motor messages are LSB first +#define MOTOR_START_BYTE 0x80 +#define MOTOR_DEVICE_TYPE 0x00 +#define MOTOR_BOTH_FORWARD 0x01 // both motor forward +#define MOTOR_BOTH_BACKWARD 0x00 //both motor backward +#define MOTOR_MOTOR1_BACKWARD 0x04 // motor 1 backward +#define MOTOR_MOTOR2_BACKWARD 0x06 // motor 2 backward +#define MOTOR_MOTOR1_FORWARD 0x05 // motor 1 forward +#define MOTOR_MOTOR2_FORWARD 0x07 // motor 2 forward +#define MOTOR_CONST_SPEED 0x5F +#define MOTOR_STOP_SPEED 0x00 +#define MOTOR_CHANGE_CONFIGURATION 0X02 + +class MotorHandler { +public: + MotorHandler(); + virtual ~MotorHandler(); + + /* + * Initializes this handler. + * @return OK if the handler was initialized without error + */ + Status init(); + + void forward(); + void backward(); + void right(); + void left(); + void stop(); + void configure(); + void test(); + void reset(); + +private: + /* The device used to send serial commands to the motor controller. */ + alt_up_rs232_dev *motor_dev; + + /* + * Moves in the given direction at constant speed. + * @param direction - the motor and direction to move in, e.g. MOTOR_MOTOR1_FORWARD + * @param description - the string description of the movement, for debugging + */ + void move(char direction, char *description); + + /* + * Moves in the given direction and speed. + * @param direction - the motor and direction to move in, e.g. MOTOR_MOTOR1_FORWARD + * @param speed - the speed to move at, i.e. MOTOR_CONST_SPEED or MOTOR_STOP_SPEED + * @param description - the string description of the movement, for debugging + */ + void move(char direction, char speed, char *description); + + /* + * Sends a byte-length message to the motor controller. + * @param message - the message to send + * @param description - the string description of the message, for debugging + */ + void send(char message, char *description); +}; + +#endif /* MOTORHANDLER_H_ */ diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/76/50acbc028bab001311dbfe770f133bca b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/76/50acbc028bab001311dbfe770f133bca new file mode 100644 index 00000000..33180630 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/76/50acbc028bab001311dbfe770f133bca @@ -0,0 +1,156 @@ +/* + * MotorHandler.cpp + * + * Created on: 2014-03-03 + * Author: Amshu Gongal + */ + + +#include + +#include "altera_avalon_pio_regs.h" +#include "includes.h" +#include "system.h" + +#include "MotorHandler.h" + +#define WRITE_FIFO_EMPTY 0x80 +#define MOTOR_ENABLE 1 +#define MOTOR_RESET 0 + +// ALLOCATION +MotorHandler::MotorHandler() {} +MotorHandler::~MotorHandler() {} + +// INITIALIZATION + +/* + * Initializes this handler. + * @return OK if the handler was initialized without error + */ +Status MotorHandler::init() { + // Enable the motor controller. + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, MOTOR_ENABLE); + // Open the serial device to send commands to the motor controller. + motor_dev = alt_up_rs232_open_dev(RS232_MOTOR_NAME); + //printf("%d", motor_dev); + if (motor_dev == NULL) { + return ERR_MOTOR_OPEN; + } else { + return OK; + } +} + +void MotorHandler::configure(){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_CHANGE_CONFIGURATION, "change configuration"); + send(0X01, "2 MOTOR CONFIG"); + printf("\n"); +} +// TESTING + +void MotorHandler::test() { + send(MOTOR_START_BYTE, "test start"); +} + +// MOTOR CONTROL + +/* + * Move rover forward by activating both motors. + */ +void MotorHandler::forward() { + move(MOTOR_MOTOR1_FORWARD, "motor 1 forward"); + move(MOTOR_MOTOR2_FORWARD, "motor 2 forward"); +} + +/* + * Move rover backward by activating both motor backwards. + */ +void MotorHandler::backward() { + move(MOTOR_MOTOR1_BACKWARD, "motor 1 backward"); + move(MOTOR_MOTOR2_BACKWARD, "motor 2 backward"); +} + +/* + * Turn rover left. + */ +void MotorHandler::left() { + move(MOTOR_MOTOR2_FORWARD, "motor 1 forward"); +} + +/* + * Turn rover right. + */ +void MotorHandler::right() { + move(MOTOR_MOTOR2_FORWARD, "motor 2 forward"); +} + +/* + * Stop the rover. + */ +void MotorHandler::stop() { + move(MOTOR_MOTOR1_FORWARD, MOTOR_STOP_SPEED, "motor 1 stop"); + move(MOTOR_MOTOR2_FORWARD, MOTOR_STOP_SPEED, "motor 2 stop"); +} + +// MOTOR CONTROL HELPERS + +/* + * Moves in the given direction at constant speed. + * @param direction - the motor and direction to move in, e.g. MOTOR_MOTOR1_FORWARD + * @param description - the string description of the movement, for debugging + */ +void MotorHandler::move(char direction, char *description) { + move(direction, MOTOR_CONST_SPEED, description); +} + +/* + * Moves in the given direction and speed. + * @param direction - the motor and direction to move in, e.g. MOTOR_MOTOR1_FORWARD + * @param speed - the speed to move at, i.e. MOTOR_CONST_SPEED or MOTOR_STOP_SPEED + * @param description - the string description of the movement, for debugging + */ +void MotorHandler::move(char direction, char speed, char *description) { + send(MOTOR_START_BYTE, "start"); + send(MOTOR_DEVICE_TYPE, "device"); + send(direction, description); + send(speed, "speed"); + printf("\n"); +} + +/* + * Sends a byte-length message to the motor controller. + * @param message - the message to send + * @param description - the string description of the message, for debugging + */ +void MotorHandler::send(char message, char *description) { + alt_u32 write_space; + // Check for write space. + write_space = alt_up_rs232_get_available_space_in_write_FIFO(motor_dev); + if (write_space >= WRITE_FIFO_EMPTY) { + // If space, write. + int status = alt_up_rs232_write_data(motor_dev, message); + printf("MotorHandler [message: 0x%02x, description: %s", message, description); + // Log errors. + if (status == OK) { + printf("]\n"); + } else { + printf(", error: cannot write]\n"); + } + } else { + // If no space, wait and retry. + printf("MotorHandler [message: 0x%02x, description: %s, error: no write space; retrying]\n", message, description); + OSTimeDlyHMSM(0, 0, 0, 10); + send(message, description); + } +} + +void MotorHandler::reset(){ + + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 1); + OSTimeDlyHMSM(0, 0, 0, 100); + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 0); + OSTimeDlyHMSM(0, 0, 0, 100); + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 1); + OSTimeDlyHMSM(0, 0, 0, 100); +} diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/79/c079a6ba88b000131eb0f6c547a05c39 b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/79/c079a6ba88b000131eb0f6c547a05c39 new file mode 100644 index 00000000..cb405a01 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/79/c079a6ba88b000131eb0f6c547a05c39 @@ -0,0 +1,132 @@ +/* + * MotorHandler.cpp + * + * Created on: 2014-03-03 + * Author: Amshu Gongal + */ + + +#include + +#include "altera_avalon_pio_regs.h" +#include "includes.h" +#include "system.h" + +#include "MotorHandler.h" + +#define WRITE_FIFO_EMPTY 0x80 +#define MOTOR_ENABLE 1 +#define MOTOR_RESET 0 + +// ALLOCATION +MotorHandler::MotorHandler() {} +MotorHandler::~MotorHandler() {} + + +// INITIALIZATION + +/* + * Initializes this handler. + * @return OK if the handler was initialized without error + */ +Status MotorHandler::init() { + // Enable the motor controller. + reset(); + // Open the serial device to send commands to the motor controller. + motor_dev = alt_up_rs232_open_dev(RS232_MOTOR_NAME); + //printf("%d", motor_dev); + if (motor_dev == NULL) { + return ERR_MOTOR_OPEN; + } else { + return OK; + } +} + +void MotorHandler::configure(){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_CHANGE_CONFIGURATION, "change configuration"); + send(0X01, "2 MOTOR CONFIG"); + printf("\n"); +} + +//Command Interpreter +/* + * Interprets the command from the network handler and sends move commands + * @param motor The motor to move eg. Left or Right + * @param motorDirection The direction of the given motor to move + * @param speed The speed the motor is to move + */ +void MotorHandler::motorCommand(string motor, string motorDirection, string speed){ + char motorID = interpretMotor(motor); + char Direction = interpretDirection(motorDirection, int(motorID)); +} + +char MotorHandler::interpretMotor(string motor){ + if(motor.compare(MOTOR_LEFT) == 0){ + return MOTOR_LEFT_CHAR; + } + else{ + return MOTOR_RIGHT_CHAR; + } +} + +char MotorHandler::interpretDirection(string direction, int motor){ + if(direction.compare(MOTOR_FORWARD) == 0){ + return (char) (motor*2 + 1); + } + else{ + return (char) (motor*2); + } +} + +// MOTOR CONTROL + +/*Moves the given motor in specified direction by Motor Direction with specified + * Speed + * @param MotorDirection Motor and direction to move + * @param Speed the speed to move at + * @param string description of motor movement + */ + +void MotorHandler::move(char MotorDirection,char Speed,char * Description){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_DEVICE_TYPE, "device"); + send(MotorDirection, Description); + send(Speed, "speed"); + printf("\n"); +} + +// MOTOR CONTROL HELPERS +/* + * Sends a byte-length message to the motor controller. + * @param message - the message to send + * @param description - the string description of the message, for debugging + */ +void MotorHandler::send(char message, char *description) { + alt_u32 write_space; + // Check for write space. + write_space = alt_up_rs232_get_available_space_in_write_FIFO(motor_dev); + if (write_space >= WRITE_FIFO_EMPTY) { + // If space, write. + int status = alt_up_rs232_write_data(motor_dev, message); + printf("MotorHandler [message: 0x%02x, description: %s", message, description); + // Log errors. + if (status == OK) { + printf("]\n"); + } else { + printf(", error: cannot write]\n"); + } + } else { + // If no space, wait and retry. + printf("MotorHandler [message: 0x%02x, description: %s, error: no write space; retrying]\n", message, description); + OSTimeDlyHMSM(0, 0, 0, 10); + send(message, description); + } +} + +void MotorHandler::reset(){ + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 0); + OSTimeDlyHMSM(0, 0, 0,200 ); + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 1); + OSTimeDlyHMSM(0, 0, 0, 200); +} diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/7b/50114b32a9ab001311f2ce252b4696cb b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/7b/50114b32a9ab001311f2ce252b4696cb new file mode 100644 index 00000000..0cb9bfdb --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/7b/50114b32a9ab001311f2ce252b4696cb @@ -0,0 +1,153 @@ +/* + * MotorHandler.cpp + * + * Created on: 2014-03-03 + * Author: Amshu Gongal + */ + + +#include + +#include "altera_avalon_pio_regs.h" +#include "includes.h" +#include "system.h" + +#include "MotorHandler.h" + +#define WRITE_FIFO_EMPTY 0x80 +#define MOTOR_ENABLE 1 +#define MOTOR_RESET 0 + +// ALLOCATION +MotorHandler::MotorHandler() {} +MotorHandler::~MotorHandler() {} + +// INITIALIZATION + +/* + * Initializes this handler. + * @return OK if the handler was initialized without error + */ +Status MotorHandler::init() { + // Enable the motor controller. + reset(); + // Open the serial device to send commands to the motor controller. + motor_dev = alt_up_rs232_open_dev(RS232_MOTOR_NAME); + //printf("%d", motor_dev); + if (motor_dev == NULL) { + return ERR_MOTOR_OPEN; + } else { + return OK; + } +} + +void MotorHandler::configure(){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_CHANGE_CONFIGURATION, "change configuration"); + send(0X01, "2 MOTOR CONFIG"); + printf("\n"); +} +// TESTING + +void MotorHandler::test() { + send(MOTOR_START_BYTE, "test start"); +} + +// MOTOR CONTROL + +/* + * Move rover forward by activating both motors. + */ +void MotorHandler::forward() { + move(MOTOR_BOTH_FORWARD, "motor 1 forward"); +// move(MOTOR_MOTOR2_FORWARD, "motor 2 forward"); +} + +/* + * Move rover backward by activating both motor backwards. + */ +void MotorHandler::backward() { + move(MOTOR_BOTH_BACKWARD, "motor 1 backward"); +// move(MOTOR_MOTOR2_BACKWARD, "motor 2 backward"); +} + +/* + * Turn rover left. + */ +void MotorHandler::left() { + move(MOTOR_MOTOR2_FORWARD, "motor 1 forward"); +} + +/* + * Turn rover right. + */ +void MotorHandler::right() { + move(MOTOR_MOTOR2_FORWARD, "motor 2 forward"); +} + +/* + * Stop the rover. + */ +void MotorHandler::stop() { + move(MOTOR_MOTOR1_FORWARD, MOTOR_STOP_SPEED, "motor 1 stop"); + move(MOTOR_MOTOR2_FORWARD, MOTOR_STOP_SPEED, "motor 2 stop"); +} + +// MOTOR CONTROL HELPERS + +/* + * Moves in the given direction at constant speed. + * @param direction - the motor and direction to move in, e.g. MOTOR_MOTOR1_FORWARD + * @param description - the string description of the movement, for debugging + */ +void MotorHandler::move(char direction, char *description) { + move(direction, MOTOR_CONST_SPEED, description); +} + +/* + * Moves in the given direction and speed. + * @param direction - the motor and direction to move in, e.g. MOTOR_MOTOR1_FORWARD + * @param speed - the speed to move at, i.e. MOTOR_CONST_SPEED or MOTOR_STOP_SPEED + * @param description - the string description of the movement, for debugging + */ +void MotorHandler::move(char direction, char speed, char *description) { + send(MOTOR_START_BYTE, "start"); + send(MOTOR_DEVICE_TYPE, "device"); + send(direction, description); + send(speed, "speed"); + printf("\n"); +} + +/* + * Sends a byte-length message to the motor controller. + * @param message - the message to send + * @param description - the string description of the message, for debugging + */ +void MotorHandler::send(char message, char *description) { + alt_u32 write_space; + // Check for write space. + write_space = alt_up_rs232_get_available_space_in_write_FIFO(motor_dev); + if (write_space >= WRITE_FIFO_EMPTY) { + // If space, write. + int status = alt_up_rs232_write_data(motor_dev, message); + printf("MotorHandler [message: 0x%02x, description: %s", message, description); + // Log errors. + if (status == OK) { + printf("]\n"); + } else { + printf(", error: cannot write]\n"); + } + } else { + // If no space, wait and retry. + printf("MotorHandler [message: 0x%02x, description: %s, error: no write space; retrying]\n", message, description); + OSTimeDlyHMSM(0, 0, 0, 10); + send(message, description); + } +} + +void MotorHandler::reset(){ + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 0); + OSTimeDlyHMSM(0, 0, 2,0 ); + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 1); + OSTimeDlyHMSM(0, 0, 2, 100); +} diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/7b/903d0f0083b000131eb0f6c547a05c39 b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/7b/903d0f0083b000131eb0f6c547a05c39 new file mode 100644 index 00000000..8fb64857 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/7b/903d0f0083b000131eb0f6c547a05c39 @@ -0,0 +1,61 @@ +/* + * MotorHandler.h + * + * Created on: 2014-03-03 + * Author: Amshu Gongal + */ + +#ifndef MOTORHANDLER_H_ +#define MOTORHANDLER_H_ + +#include "altera_up_avalon_rs232.h" +#include "altera_up_avalon_rs232_regs.h" +#include +using namespace std; +#include +#include "Status.h" + +// Motor messages are LSB first +#define MOTOR_START_BYTE 0x80 +#define MOTOR_DEVICE_TYPE 0x00 +#define MOTOR_LEFT_BACKWARD 0x04 // motor 1 backward +#define MOTOR_RIGHT_BACKWARD 0x06 // motor 2 backward +#define MOTOR_LEFT_FORWARD 0x05 // motor 1 forward +#define MOTOR_RIGHT_FORWARD 0x07 // motor 2 forward +#define MOTOR_CONST_SPEED 0x5F +#define MOTOR_STOP_SPEED 0x00 +#define MOTOR_CHANGE_CONFIGURATION 0X02 + +class MotorHandler { +public: + MotorHandler(); + virtual ~MotorHandler(); + + /* + * Initializes this handler. + * @return OK if the handler was initialized without error + */ + Status init(); + void motorCommand(string motor, string motorDirection, char); + +private: + /* The device used to send serial commands to the motor controller. */ + alt_up_rs232_dev *motor_dev; + + /* + * Moves in the given direction at constant speed. + * @param direction - the motor and direction to move in, e.g. MOTOR_MOTOR1_FORWARD + * @param speed speed of the motor + * @param description - the string description of the movement, for debugging + */ + void move(char direction, char speed, char *description); + + /* + * Sends a byte-length message to the motor controller. + * @param message - the message to send + * @param description - the string description of the message, for debugging + */ + void send(char message, char *description); +}; + +#endif /* MOTORHANDLER_H_ */ diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/8/20ed070eceab001312eeeea4d67ccb1b b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/8/20ed070eceab001312eeeea4d67ccb1b new file mode 100644 index 00000000..258547c4 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/8/20ed070eceab001312eeeea4d67ccb1b @@ -0,0 +1,149 @@ +/************************************************************************* + * ARCap + * Amshu Gongal, Kenan Kigunda + * February 18, 2014 + ************************************************************************** + * Description: * + * Prototype testing for infrared and mc. + **************************************************************************/ + +#include +#include "includes.h" +#include "altera_avalon_pio_regs.h" +#include "altera_avalon_uart_regs.h" +#include "sys/alt_irq.h" +#include "alt_types.h" +#include "altera_up_avalon_rs232.h" +#include "altera_up_avalon_rs232_regs.h" + +#include "MotorHandler.h" +#include "Status.h" + +/* Task stacks */ +#define TASK_STACKSIZE 2048 +OS_STK ir_task_stk[TASK_STACKSIZE]; +OS_STK mc_task_stk[TASK_STACKSIZE]; +/* Task priorities */ +#define IR_TASK_PRIORITY 2 +#define MC_TASK_PRIORITY 1 + + +#define SW_READ 1 +#define SW_WRITE 2 +#define WRITE_FIFO_EMPTY 0x80 +#define READ_FIFO_EMPTY 0x0 +OS_EVENT *SWQ; +OS_EVENT *RS232Q; +INT8U err; + + +/* Error status */ +#define OK 0 + +/* Message queues */ +#define WAIT_FOREVER 0 + +// ==== INFRARED ==== + +/* Infrared message queue */ +#define IR_MAX_MESSAGES 4 +int ir_messages[IR_MAX_MESSAGES]; +OS_EVENT *ir_queue; + +/* Infrared messages */ +// Together these avoid passing 0 to the queue (which is not allowed since queue messages cannot be null) +// and invert pushbutton input (since the pushbutton returns 0 when it is pushed down). +#define IR_QUEUE_SEND_BASE 1 // Use: IR_QUEUE_SEND_BASE + IORD +#define IR_QUEUE_RECEIVE_BASE 2 // Use: IR_QUEUE_RECEIVE_BASE - OSQPend + + +MotorHandler *motor= new MotorHandler(); + + +// ==== mc + +#define mc_GUARD_TIME 1 + +void mc_task(void *pdata) +{ + printf("mc task\n"); + printf("MotorHandler [init"); + if (motor->init() == OK) { + printf("]\n\n"); + motor->forward(); + } else { + printf( ", error]\n"); + } + while(1){ + motor->forward(); + OSTimeDlyHMSM(0, 0, 10, 0); + motor->stop(); + OSTimeDlyHMSM(0, 0, 3,0); + motor->left(); + + } +} + + + +// ==== GENERAL + +void queue_init() { + ir_queue = OSQCreate((void**)&ir_messages, IR_MAX_MESSAGES); +} + +/* The main function creates the LCD task, registers the edge counter polling interrupt, + * and starts the OS. */ +int main(void) +{ + int status = OK; + // Initialize components. + queue_init(); + // Create the mc task. + OSTaskCreateExt(mc_task, + NULL, + &mc_task_stk[TASK_STACKSIZE - 1], + MC_TASK_PRIORITY, + MC_TASK_PRIORITY, + mc_task_stk, + TASK_STACKSIZE, + NULL, + 0); + + if (status == OK) { + OSStart(); + } + + return 0; +} + +/****************************************************************************** + * * + * License Agreement * + * * + * Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * + * All rights reserved. * + * * + * Permission is hereby granted, free of charge, to any person obtaining a * + * copy of this software and associated documentation files (the "Software"), * + * to deal in the Software without restriction, including without limitation * + * the rights to use, copy, modify, merge, publish, distribute, sublicense, * + * and/or sell copies of the Software, and to permit persons to whom the * + * Software is furnished to do so, subject to the following conditions: * + * * + * The above copyright notice and this permission notice shall be included in * + * all copies or substantial portions of the Software. * + * * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * + * DEALINGS IN THE SOFTWARE. * + * * + * This agreement shall be governed in all respects by the laws of the State * + * of California and by the laws of the United States of America. * + * Altera does not recommend, suggest or require that this reference design * + * file be used in conjunction or combination with any other product. * + ******************************************************************************/ diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/8/605896c9c4ab001312b0c9eb155e9cea b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/8/605896c9c4ab001312b0c9eb155e9cea new file mode 100644 index 00000000..463feb0c --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/8/605896c9c4ab001312b0c9eb155e9cea @@ -0,0 +1,145 @@ +/************************************************************************* + * ARCap + * Amshu Gongal, Kenan Kigunda + * February 18, 2014 + ************************************************************************** + * Description: * + * Prototype testing for infrared and mc. + **************************************************************************/ + +#include +#include "includes.h" +#include "altera_avalon_pio_regs.h" +#include "altera_avalon_uart_regs.h" +#include "sys/alt_irq.h" +#include "alt_types.h" +#include "altera_up_avalon_rs232.h" +#include "altera_up_avalon_rs232_regs.h" + +#include "MotorHandler.h" +#include "Status.h" + +/* Task stacks */ +#define TASK_STACKSIZE 2048 +OS_STK ir_task_stk[TASK_STACKSIZE]; +OS_STK mc_task_stk[TASK_STACKSIZE]; +/* Task priorities */ +#define IR_TASK_PRIORITY 2 +#define MC_TASK_PRIORITY 1 + + +#define SW_READ 1 +#define SW_WRITE 2 +#define WRITE_FIFO_EMPTY 0x80 +#define READ_FIFO_EMPTY 0x0 +OS_EVENT *SWQ; +OS_EVENT *RS232Q; +INT8U err; + + +/* Error status */ +#define OK 0 + +/* Message queues */ +#define WAIT_FOREVER 0 + +// ==== INFRARED ==== + +/* Infrared message queue */ +#define IR_MAX_MESSAGES 4 +int ir_messages[IR_MAX_MESSAGES]; +OS_EVENT *ir_queue; + +/* Infrared messages */ +// Together these avoid passing 0 to the queue (which is not allowed since queue messages cannot be null) +// and invert pushbutton input (since the pushbutton returns 0 when it is pushed down). +#define IR_QUEUE_SEND_BASE 1 // Use: IR_QUEUE_SEND_BASE + IORD +#define IR_QUEUE_RECEIVE_BASE 2 // Use: IR_QUEUE_RECEIVE_BASE - OSQPend + + +MotorHandler *motor= new MotorHandler(); + + +// ==== mc + +#define mc_GUARD_TIME 1 + +void mc_task(void *pdata) +{ + printf("mc task\n"); + printf("MotorHandler [init"); + if (motor->init() == OK) { + printf("]\n\n"); + motor->left(); + } else { + printf( ", error]\n"); + } + while(1){ + motor->left(); + + } +} + + + +// ==== GENERAL + +void queue_init() { + ir_queue = OSQCreate((void**)&ir_messages, IR_MAX_MESSAGES); +} + +/* The main function creates the LCD task, registers the edge counter polling interrupt, + * and starts the OS. */ +int main(void) +{ + int status = OK; + // Initialize components. + queue_init(); + // Create the mc task. + OSTaskCreateExt(mc_task, + NULL, + &mc_task_stk[TASK_STACKSIZE - 1], + MC_TASK_PRIORITY, + MC_TASK_PRIORITY, + mc_task_stk, + TASK_STACKSIZE, + NULL, + 0); + + if (status == OK) { + OSStart(); + } + + return 0; +} + +/****************************************************************************** + * * + * License Agreement * + * * + * Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * + * All rights reserved. * + * * + * Permission is hereby granted, free of charge, to any person obtaining a * + * copy of this software and associated documentation files (the "Software"), * + * to deal in the Software without restriction, including without limitation * + * the rights to use, copy, modify, merge, publish, distribute, sublicense, * + * and/or sell copies of the Software, and to permit persons to whom the * + * Software is furnished to do so, subject to the following conditions: * + * * + * The above copyright notice and this permission notice shall be included in * + * all copies or substantial portions of the Software. * + * * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * + * DEALINGS IN THE SOFTWARE. * + * * + * This agreement shall be governed in all respects by the laws of the State * + * of California and by the laws of the United States of America. * + * Altera does not recommend, suggest or require that this reference design * + * file be used in conjunction or combination with any other product. * + ******************************************************************************/ diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/81/a0e1f59ea3ab001311f2ce252b4696cb b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/81/a0e1f59ea3ab001311f2ce252b4696cb new file mode 100644 index 00000000..b42867b8 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/81/a0e1f59ea3ab001311f2ce252b4696cb @@ -0,0 +1,146 @@ +/************************************************************************* + * ARCap + * Amshu Gongal, Kenan Kigunda + * February 18, 2014 + ************************************************************************** + * Description: * + * Prototype testing for infrared and mc. + **************************************************************************/ + +#include +#include "includes.h" +#include "altera_avalon_pio_regs.h" +#include "altera_avalon_uart_regs.h" +#include "sys/alt_irq.h" +#include "alt_types.h" +#include "altera_up_avalon_rs232.h" +#include "altera_up_avalon_rs232_regs.h" + +#include "MotorHandler.h" +#include "Status.h" + +/* Task stacks */ +#define TASK_STACKSIZE 2048 +OS_STK ir_task_stk[TASK_STACKSIZE]; +OS_STK mc_task_stk[TASK_STACKSIZE]; +/* Task priorities */ +#define IR_TASK_PRIORITY 2 +#define MC_TASK_PRIORITY 1 + + +#define SW_READ 1 +#define SW_WRITE 2 +#define WRITE_FIFO_EMPTY 0x80 +#define READ_FIFO_EMPTY 0x0 +OS_EVENT *SWQ; +OS_EVENT *RS232Q; +INT8U err; + + +/* Error status */ +#define OK 0 + +/* Message queues */ +#define WAIT_FOREVER 0 + +// ==== INFRARED ==== + +/* Infrared message queue */ +#define IR_MAX_MESSAGES 4 +int ir_messages[IR_MAX_MESSAGES]; +OS_EVENT *ir_queue; + +/* Infrared messages */ +// Together these avoid passing 0 to the queue (which is not allowed since queue messages cannot be null) +// and invert pushbutton input (since the pushbutton returns 0 when it is pushed down). +#define IR_QUEUE_SEND_BASE 1 // Use: IR_QUEUE_SEND_BASE + IORD +#define IR_QUEUE_RECEIVE_BASE 2 // Use: IR_QUEUE_RECEIVE_BASE - OSQPend + + +MotorHandler *motor= new MotorHandler(); + + +// ==== mc + +#define mc_GUARD_TIME 1 + +void mc_task(void *pdata) +{ + printf("mc task\n"); + printf("MotorHandler [init"); + if (motor->init() == OK) { + printf("]\n\n"); + motor->forward(); + } else { + printf( ", error]\n"); + } + while(1){ + motor->forward(); + OSTimeDlyHMSM(0, 0, 0, 100); + } +} + + + +// ==== GENERAL + +void queue_init() { + ir_queue = OSQCreate((void**)&ir_messages, IR_MAX_MESSAGES); +} + +/* The main function creates the LCD task, registers the edge counter polling interrupt, + * and starts the OS. */ +int main(void) +{ + int status = OK; + // Initialize components. + queue_init(); + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 1); + // Create the mc task. + OSTaskCreateExt(mc_task, + NULL, + &mc_task_stk[TASK_STACKSIZE - 1], + MC_TASK_PRIORITY, + MC_TASK_PRIORITY, + mc_task_stk, + TASK_STACKSIZE, + NULL, + 0); + + if (status == OK) { + OSStart(); + } + + return 0; +} + +/****************************************************************************** + * * + * License Agreement * + * * + * Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * + * All rights reserved. * + * * + * Permission is hereby granted, free of charge, to any person obtaining a * + * copy of this software and associated documentation files (the "Software"), * + * to deal in the Software without restriction, including without limitation * + * the rights to use, copy, modify, merge, publish, distribute, sublicense, * + * and/or sell copies of the Software, and to permit persons to whom the * + * Software is furnished to do so, subject to the following conditions: * + * * + * The above copyright notice and this permission notice shall be included in * + * all copies or substantial portions of the Software. * + * * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * + * DEALINGS IN THE SOFTWARE. * + * * + * This agreement shall be governed in all respects by the laws of the State * + * of California and by the laws of the United States of America. * + * Altera does not recommend, suggest or require that this reference design * + * file be used in conjunction or combination with any other product. * + ******************************************************************************/ diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/82/70fb55208db000131eb0f6c547a05c39 b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/82/70fb55208db000131eb0f6c547a05c39 new file mode 100644 index 00000000..62cd82f0 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/82/70fb55208db000131eb0f6c547a05c39 @@ -0,0 +1,146 @@ +/************************************************************************* + * ARCap + * Amshu Gongal, Kenan Kigunda + * February 18, 2014 + ************************************************************************** + * Description: * + * Prototype testing for infrared and mc. + **************************************************************************/ + +#include +#include "includes.h" +#include "altera_avalon_pio_regs.h" +#include "altera_avalon_uart_regs.h" +#include "sys/alt_irq.h" +#include "alt_types.h" +#include "altera_up_avalon_rs232.h" +#include "altera_up_avalon_rs232_regs.h" + +#include "MotorHandler.h" +#include "Status.h" + +/* Task stacks */ +#define TASK_STACKSIZE 2048 +OS_STK ir_task_stk[TASK_STACKSIZE]; +OS_STK mc_task_stk[TASK_STACKSIZE]; +/* Task priorities */ +#define IR_TASK_PRIORITY 2 +#define MC_TASK_PRIORITY 1 + + +#define SW_READ 1 +#define SW_WRITE 2 +#define WRITE_FIFO_EMPTY 0x80 +#define READ_FIFO_EMPTY 0x0 +OS_EVENT *SWQ; +OS_EVENT *RS232Q; +INT8U err; + + +/* Error status */ +#define OK 0 + +/* Message queues */ +#define WAIT_FOREVER 0 + +// ==== INFRARED ==== + +/* Infrared message queue */ +#define IR_MAX_MESSAGES 4 +int ir_messages[IR_MAX_MESSAGES]; +OS_EVENT *ir_queue; + +/* Infrared messages */ +// Together these avoid passing 0 to the queue (which is not allowed since queue messages cannot be null) +// and invert pushbutton input (since the pushbutton returns 0 when it is pushed down). +#define IR_QUEUE_SEND_BASE 1 // Use: IR_QUEUE_SEND_BASE + IORD +#define IR_QUEUE_RECEIVE_BASE 2 // Use: IR_QUEUE_RECEIVE_BASE - OSQPend + + +MotorHandler *motor= new MotorHandler(); + + +// ==== mc + +#define mc_GUARD_TIME 1 + +void mc_task(void *pdata) +{ + printf("mc task\n"); + printf("MotorHandler [init"); + if (motor->init() == OK) { + printf("]\n\n"); + } else { + printf( ", error]\n"); + } + while(1){ + motor->motorCommand("left", "forward", "120"); + OSTimeDlyHMSM(0, 0, 5, 0); + motor->motorCommand("left", "forward", "0"); + OSTimeDlyHMSM(0, 0, 5, 0); + } +} + + + +// ==== GENERAL + +void queue_init() { + ir_queue = OSQCreate((void**)&ir_messages, IR_MAX_MESSAGES); +} + +/* The main function creates the LCD task, registers the edge counter polling interrupt, + * and starts the OS. */ +int main(void) +{ + int status = OK; + // Initialize components. + queue_init(); + // Create the mc task. + OSTaskCreateExt(mc_task, + NULL, + &mc_task_stk[TASK_STACKSIZE - 1], + MC_TASK_PRIORITY, + MC_TASK_PRIORITY, + mc_task_stk, + TASK_STACKSIZE, + NULL, + 0); + + if (status == OK) { + OSStart(); + } + + return 0; +} + +/****************************************************************************** + * * + * License Agreement * + * * + * Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * + * All rights reserved. * + * * + * Permission is hereby granted, free of charge, to any person obtaining a * + * copy of this software and associated documentation files (the "Software"), * + * to deal in the Software without restriction, including without limitation * + * the rights to use, copy, modify, merge, publish, distribute, sublicense, * + * and/or sell copies of the Software, and to permit persons to whom the * + * Software is furnished to do so, subject to the following conditions: * + * * + * The above copyright notice and this permission notice shall be included in * + * all copies or substantial portions of the Software. * + * * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * + * DEALINGS IN THE SOFTWARE. * + * * + * This agreement shall be governed in all respects by the laws of the State * + * of California and by the laws of the United States of America. * + * Altera does not recommend, suggest or require that this reference design * + * file be used in conjunction or combination with any other product. * + ******************************************************************************/ diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/83/3000e79387b000131eb0f6c547a05c39 b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/83/3000e79387b000131eb0f6c547a05c39 new file mode 100644 index 00000000..24cf9826 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/83/3000e79387b000131eb0f6c547a05c39 @@ -0,0 +1,125 @@ +/* + * MotorHandler.cpp + * + * Created on: 2014-03-03 + * Author: Amshu Gongal + */ + + +#include + +#include "altera_avalon_pio_regs.h" +#include "includes.h" +#include "system.h" + +#include "MotorHandler.h" + +#define WRITE_FIFO_EMPTY 0x80 +#define MOTOR_ENABLE 1 +#define MOTOR_RESET 0 + +// ALLOCATION +MotorHandler::MotorHandler() {} +MotorHandler::~MotorHandler() {} + + +// INITIALIZATION + +/* + * Initializes this handler. + * @return OK if the handler was initialized without error + */ +Status MotorHandler::init() { + // Enable the motor controller. + reset(); + // Open the serial device to send commands to the motor controller. + motor_dev = alt_up_rs232_open_dev(RS232_MOTOR_NAME); + //printf("%d", motor_dev); + if (motor_dev == NULL) { + return ERR_MOTOR_OPEN; + } else { + return OK; + } +} + +void MotorHandler::configure(){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_CHANGE_CONFIGURATION, "change configuration"); + send(0X01, "2 MOTOR CONFIG"); + printf("\n"); +} + +//Command Interpreter +/* + * Interprets the command from the network handler and sends move commands + * @param motor The motor to move eg. Left or Right + * @param motorDirection The direction of the given motor to move + * @param speed The speed the motor is to move + */ +void MotorHandler::motorCommand(string motor, string motorDirection, string speed){ + char motorC = interpretMotor(motor); +} + +char MotorHandler::interpretMotor(string motor){ + if(motor.compare(MOTOR_LEFT) == 0){ + return MOTOR_LEFT_CHAR; + } + else + return MOTOR_RIGHT_CHAR; +} + +char MotorHandler::interpretDirection(string direction, int motor){ + +} + +// MOTOR CONTROL + +/*Moves the given motor in specified direction by Motor Direction with specified + * Speed + * @param MotorDirection Motor and direction to move + * @param Speed the speed to move at + * @param string description of motor movement + */ + +void MotorHandler::move(char MotorDirection,char Speed,char * Description){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_DEVICE_TYPE, "device"); + send(MotorDirection, Description); + send(Speed, "speed"); + printf("\n"); +} + +// MOTOR CONTROL HELPERS +/* + * Sends a byte-length message to the motor controller. + * @param message - the message to send + * @param description - the string description of the message, for debugging + */ +void MotorHandler::send(char message, char *description) { + alt_u32 write_space; + // Check for write space. + write_space = alt_up_rs232_get_available_space_in_write_FIFO(motor_dev); + if (write_space >= WRITE_FIFO_EMPTY) { + // If space, write. + int status = alt_up_rs232_write_data(motor_dev, message); + printf("MotorHandler [message: 0x%02x, description: %s", message, description); + // Log errors. + if (status == OK) { + printf("]\n"); + } else { + printf(", error: cannot write]\n"); + } + } else { + // If no space, wait and retry. + printf("MotorHandler [message: 0x%02x, description: %s, error: no write space; retrying]\n", message, description); + OSTimeDlyHMSM(0, 0, 0, 10); + send(message, description); + } +} + +void MotorHandler::reset(){ + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 0); + OSTimeDlyHMSM(0, 0, 0,200 ); + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 1); + OSTimeDlyHMSM(0, 0, 0, 200); +} diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/8b/60e18c37a5ab001311f2ce252b4696cb b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/8b/60e18c37a5ab001311f2ce252b4696cb new file mode 100644 index 00000000..c579c551 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/8b/60e18c37a5ab001311f2ce252b4696cb @@ -0,0 +1,153 @@ +/* + * MotorHandler.cpp + * + * Created on: 2014-03-03 + * Author: Amshu Gongal + */ + + +#include + +#include "altera_avalon_pio_regs.h" +#include "includes.h" +#include "system.h" + +#include "MotorHandler.h" + +#define WRITE_FIFO_EMPTY 0x80 +#define MOTOR_ENABLE 1 +#define MOTOR_RESET 0 + +// ALLOCATION +MotorHandler::MotorHandler() {} +MotorHandler::~MotorHandler() {} + +// INITIALIZATION + +/* + * Initializes this handler. + * @return OK if the handler was initialized without error + */ +Status MotorHandler::init() { + // Enable the motor controller. + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, MOTOR_ENABLE); + // Open the serial device to send commands to the motor controller. + motor_dev = alt_up_rs232_open_dev(RS232_MOTOR_NAME); + //printf("%d", motor_dev); + if (motor_dev == NULL) { + return ERR_MOTOR_OPEN; + } else { + return OK; + } +} + +void MotorHandler::configure(){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_CHANGE_CONFIGURATION, "change configuration"); + send(0X01, "2 MOTOR CONFIG"); + printf("\n"); +} +// TESTING + +void MotorHandler::test() { + send(MOTOR_START_BYTE, "test start"); +} + +// MOTOR CONTROL + +/* + * Move rover forward by activating both motors. + */ +void MotorHandler::forward() { + move(MOTOR_MOTOR1_FORWARD, "motor 1 forward"); + move(MOTOR_MOTOR2_FORWARD, "motor 2 forward"); +} + +/* + * Move rover backward by activating both motor backwards. + */ +void MotorHandler::backward() { + move(MOTOR_MOTOR1_BACKWARD, "motor 1 backward"); + move(MOTOR_MOTOR2_BACKWARD, "motor 2 backward"); +} + +/* + * Turn rover left. + */ +void MotorHandler::left() { + move(MOTOR_MOTOR2_FORWARD, "motor 1 forward"); +} + +/* + * Turn rover right. + */ +void MotorHandler::right() { + move(MOTOR_MOTOR2_FORWARD, "motor 2 forward"); +} + +/* + * Stop the rover. + */ +void MotorHandler::stop() { + move(MOTOR_MOTOR1_FORWARD, MOTOR_STOP_SPEED, "motor 1 stop"); + move(MOTOR_MOTOR2_FORWARD, MOTOR_STOP_SPEED, "motor 2 stop"); +} + +// MOTOR CONTROL HELPERS + +/* + * Moves in the given direction at constant speed. + * @param direction - the motor and direction to move in, e.g. MOTOR_MOTOR1_FORWARD + * @param description - the string description of the movement, for debugging + */ +void MotorHandler::move(char direction, char *description) { + move(direction, MOTOR_CONST_SPEED, description); +} + +/* + * Moves in the given direction and speed. + * @param direction - the motor and direction to move in, e.g. MOTOR_MOTOR1_FORWARD + * @param speed - the speed to move at, i.e. MOTOR_CONST_SPEED or MOTOR_STOP_SPEED + * @param description - the string description of the movement, for debugging + */ +void MotorHandler::move(char direction, char speed, char *description) { + send(MOTOR_START_BYTE, "start"); + send(MOTOR_DEVICE_TYPE, "device"); + send(direction, description); + send(speed, "speed"); + printf("\n"); +} + +/* + * Sends a byte-length message to the motor controller. + * @param message - the message to send + * @param description - the string description of the message, for debugging + */ +void MotorHandler::send(char message, char *description) { + alt_u32 write_space; + // Check for write space. + write_space = alt_up_rs232_get_available_space_in_write_FIFO(motor_dev); + if (write_space >= WRITE_FIFO_EMPTY) { + // If space, write. + int status = alt_up_rs232_write_data(motor_dev, message); + printf("MotorHandler [message: 0x%02x, description: %s", message, description); + // Log errors. + if (status == OK) { + printf("]\n"); + } else { + printf(", error: cannot write]\n"); + } + } else { + // If no space, wait and retry. + printf("MotorHandler [message: 0x%02x, description: %s, error: no write space; retrying]\n", message, description); + OSTimeDlyHMSM(0, 0, 0, 10); + send(message, description); + } +} + +void MotorHandler::reset(){ +// IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 0); +// OSTimeDlyHMSM(0, 0, 0, 100); + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 1); + OSTimeDlyHMSM(0, 0, 0, 100); +} diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/8b/c0a24436cdab001312eeeea4d67ccb1b b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/8b/c0a24436cdab001312eeeea4d67ccb1b new file mode 100644 index 00000000..962c427b --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/8b/c0a24436cdab001312eeeea4d67ccb1b @@ -0,0 +1,146 @@ +/************************************************************************* + * ARCap + * Amshu Gongal, Kenan Kigunda + * February 18, 2014 + ************************************************************************** + * Description: * + * Prototype testing for infrared and mc. + **************************************************************************/ + +#include +#include "includes.h" +#include "altera_avalon_pio_regs.h" +#include "altera_avalon_uart_regs.h" +#include "sys/alt_irq.h" +#include "alt_types.h" +#include "altera_up_avalon_rs232.h" +#include "altera_up_avalon_rs232_regs.h" + +#include "MotorHandler.h" +#include "Status.h" + +/* Task stacks */ +#define TASK_STACKSIZE 2048 +OS_STK ir_task_stk[TASK_STACKSIZE]; +OS_STK mc_task_stk[TASK_STACKSIZE]; +/* Task priorities */ +#define IR_TASK_PRIORITY 2 +#define MC_TASK_PRIORITY 1 + + +#define SW_READ 1 +#define SW_WRITE 2 +#define WRITE_FIFO_EMPTY 0x80 +#define READ_FIFO_EMPTY 0x0 +OS_EVENT *SWQ; +OS_EVENT *RS232Q; +INT8U err; + + +/* Error status */ +#define OK 0 + +/* Message queues */ +#define WAIT_FOREVER 0 + +// ==== INFRARED ==== + +/* Infrared message queue */ +#define IR_MAX_MESSAGES 4 +int ir_messages[IR_MAX_MESSAGES]; +OS_EVENT *ir_queue; + +/* Infrared messages */ +// Together these avoid passing 0 to the queue (which is not allowed since queue messages cannot be null) +// and invert pushbutton input (since the pushbutton returns 0 when it is pushed down). +#define IR_QUEUE_SEND_BASE 1 // Use: IR_QUEUE_SEND_BASE + IORD +#define IR_QUEUE_RECEIVE_BASE 2 // Use: IR_QUEUE_RECEIVE_BASE - OSQPend + + +MotorHandler *motor= new MotorHandler(); + + +// ==== mc + +#define mc_GUARD_TIME 1 + +void mc_task(void *pdata) +{ + printf("mc task\n"); + printf("MotorHandler [init"); + if (motor->init() == OK) { + printf("]\n\n"); + motor->forward(); + } else { + printf( ", error]\n"); + } + while(1){ + motor->forward(); + OSTimeDlyHMSM(0, 0, 0, 200); + + } +} + + + +// ==== GENERAL + +void queue_init() { + ir_queue = OSQCreate((void**)&ir_messages, IR_MAX_MESSAGES); +} + +/* The main function creates the LCD task, registers the edge counter polling interrupt, + * and starts the OS. */ +int main(void) +{ + int status = OK; + // Initialize components. + queue_init(); + // Create the mc task. + OSTaskCreateExt(mc_task, + NULL, + &mc_task_stk[TASK_STACKSIZE - 1], + MC_TASK_PRIORITY, + MC_TASK_PRIORITY, + mc_task_stk, + TASK_STACKSIZE, + NULL, + 0); + + if (status == OK) { + OSStart(); + } + + return 0; +} + +/****************************************************************************** + * * + * License Agreement * + * * + * Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * + * All rights reserved. * + * * + * Permission is hereby granted, free of charge, to any person obtaining a * + * copy of this software and associated documentation files (the "Software"), * + * to deal in the Software without restriction, including without limitation * + * the rights to use, copy, modify, merge, publish, distribute, sublicense, * + * and/or sell copies of the Software, and to permit persons to whom the * + * Software is furnished to do so, subject to the following conditions: * + * * + * The above copyright notice and this permission notice shall be included in * + * all copies or substantial portions of the Software. * + * * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * + * DEALINGS IN THE SOFTWARE. * + * * + * This agreement shall be governed in all respects by the laws of the State * + * of California and by the laws of the United States of America. * + * Altera does not recommend, suggest or require that this reference design * + * file be used in conjunction or combination with any other product. * + ******************************************************************************/ diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/8d/109cba1188b000131eb0f6c547a05c39 b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/8d/109cba1188b000131eb0f6c547a05c39 new file mode 100644 index 00000000..12502929 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/8d/109cba1188b000131eb0f6c547a05c39 @@ -0,0 +1,132 @@ +/* + * MotorHandler.cpp + * + * Created on: 2014-03-03 + * Author: Amshu Gongal + */ + + +#include + +#include "altera_avalon_pio_regs.h" +#include "includes.h" +#include "system.h" + +#include "MotorHandler.h" + +#define WRITE_FIFO_EMPTY 0x80 +#define MOTOR_ENABLE 1 +#define MOTOR_RESET 0 + +// ALLOCATION +MotorHandler::MotorHandler() {} +MotorHandler::~MotorHandler() {} + + +// INITIALIZATION + +/* + * Initializes this handler. + * @return OK if the handler was initialized without error + */ +Status MotorHandler::init() { + // Enable the motor controller. + reset(); + // Open the serial device to send commands to the motor controller. + motor_dev = alt_up_rs232_open_dev(RS232_MOTOR_NAME); + //printf("%d", motor_dev); + if (motor_dev == NULL) { + return ERR_MOTOR_OPEN; + } else { + return OK; + } +} + +void MotorHandler::configure(){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_CHANGE_CONFIGURATION, "change configuration"); + send(0X01, "2 MOTOR CONFIG"); + printf("\n"); +} + +//Command Interpreter +/* + * Interprets the command from the network handler and sends move commands + * @param motor The motor to move eg. Left or Right + * @param motorDirection The direction of the given motor to move + * @param speed The speed the motor is to move + */ +void MotorHandler::motorCommand(string motor, string motorDirection, string speed){ + char motorID = interpretMotor(motor); + char Direction = interpretDirection(motorDirection, int(motorID)); +} + +char MotorHandler::interpretMotor(string motor){ + if(motor.compare(MOTOR_LEFT) == 0){ + return MOTOR_LEFT_CHAR; + } + else{ + return MOTOR_RIGHT_CHAR; + } +} + +char MotorHandler::interpretDirection(string direction, int motor){ + if(direction.compare(MOTOR_FORWARD) == 0){ + return (char) (motor*2 + 1); + } + else + + +} + +// MOTOR CONTROL + +/*Moves the given motor in specified direction by Motor Direction with specified + * Speed + * @param MotorDirection Motor and direction to move + * @param Speed the speed to move at + * @param string description of motor movement + */ + +void MotorHandler::move(char MotorDirection,char Speed,char * Description){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_DEVICE_TYPE, "device"); + send(MotorDirection, Description); + send(Speed, "speed"); + printf("\n"); +} + +// MOTOR CONTROL HELPERS +/* + * Sends a byte-length message to the motor controller. + * @param message - the message to send + * @param description - the string description of the message, for debugging + */ +void MotorHandler::send(char message, char *description) { + alt_u32 write_space; + // Check for write space. + write_space = alt_up_rs232_get_available_space_in_write_FIFO(motor_dev); + if (write_space >= WRITE_FIFO_EMPTY) { + // If space, write. + int status = alt_up_rs232_write_data(motor_dev, message); + printf("MotorHandler [message: 0x%02x, description: %s", message, description); + // Log errors. + if (status == OK) { + printf("]\n"); + } else { + printf(", error: cannot write]\n"); + } + } else { + // If no space, wait and retry. + printf("MotorHandler [message: 0x%02x, description: %s, error: no write space; retrying]\n", message, description); + OSTimeDlyHMSM(0, 0, 0, 10); + send(message, description); + } +} + +void MotorHandler::reset(){ + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 0); + OSTimeDlyHMSM(0, 0, 0,200 ); + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 1); + OSTimeDlyHMSM(0, 0, 0, 200); +} diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/8d/a0b7c8788fab001311dbfe770f133bca b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/8d/a0b7c8788fab001311dbfe770f133bca new file mode 100644 index 00000000..5b1cc4c9 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/8d/a0b7c8788fab001311dbfe770f133bca @@ -0,0 +1,146 @@ +/************************************************************************* + * ARCap + * Amshu Gongal, Kenan Kigunda + * February 18, 2014 + ************************************************************************** + * Description: * + * Prototype testing for infrared and mc. + **************************************************************************/ + +#include +#include "includes.h" +#include "altera_avalon_pio_regs.h" +#include "altera_avalon_uart_regs.h" +#include "sys/alt_irq.h" +#include "alt_types.h" +#include "altera_up_avalon_rs232.h" +#include "altera_up_avalon_rs232_regs.h" + +#include "MotorHandler.h" +#include "Status.h" + +/* Task stacks */ +#define TASK_STACKSIZE 2048 +OS_STK ir_task_stk[TASK_STACKSIZE]; +OS_STK mc_task_stk[TASK_STACKSIZE]; +/* Task priorities */ +#define IR_TASK_PRIORITY 2 +#define MC_TASK_PRIORITY 1 + + +#define SW_READ 1 +#define SW_WRITE 2 +#define WRITE_FIFO_EMPTY 0x80 +#define READ_FIFO_EMPTY 0x0 +OS_EVENT *SWQ; +OS_EVENT *RS232Q; +INT8U err; + + +/* Error status */ +#define OK 0 + +/* Message queues */ +#define WAIT_FOREVER 0 + +// ==== INFRARED ==== + +/* Infrared message queue */ +#define IR_MAX_MESSAGES 4 +int ir_messages[IR_MAX_MESSAGES]; +OS_EVENT *ir_queue; + +/* Infrared messages */ +// Together these avoid passing 0 to the queue (which is not allowed since queue messages cannot be null) +// and invert pushbutton input (since the pushbutton returns 0 when it is pushed down). +#define IR_QUEUE_SEND_BASE 1 // Use: IR_QUEUE_SEND_BASE + IORD +#define IR_QUEUE_RECEIVE_BASE 2 // Use: IR_QUEUE_RECEIVE_BASE - OSQPend + + +MotorHandler *motor= new MotorHandler(); + + +// ==== mc + +#define mc_GUARD_TIME 1 + +void mc_task(void *pdata) +{ + printf("mc task\n"); + printf("MotorHandler [init"); + if (motor->init() == OK) { + printf("]\n\n"); + motor->forward(); + } else { + printf( ", error]\n"); + } + while(1){ + motor->forward(); + OSTimeDlyHMSM(0, 0, 0, 100); + } +} + + + +// ==== GENERAL + +void queue_init() { + ir_queue = OSQCreate((void**)&ir_messages, IR_MAX_MESSAGES); +} + +/* The main function creates the LCD task, registers the edge counter polling interrupt, + * and starts the OS. */ +int main(void) +{ + int status = OK; + // Initialize components. + queue_init(); + motor->reset(); + // Create the mc task. + OSTaskCreateExt(mc_task, + NULL, + &mc_task_stk[TASK_STACKSIZE - 1], + MC_TASK_PRIORITY, + MC_TASK_PRIORITY, + mc_task_stk, + TASK_STACKSIZE, + NULL, + 0); + + if (status == OK) { + OSStart(); + } + + return 0; +} + +/****************************************************************************** + * * + * License Agreement * + * * + * Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * + * All rights reserved. * + * * + * Permission is hereby granted, free of charge, to any person obtaining a * + * copy of this software and associated documentation files (the "Software"), * + * to deal in the Software without restriction, including without limitation * + * the rights to use, copy, modify, merge, publish, distribute, sublicense, * + * and/or sell copies of the Software, and to permit persons to whom the * + * Software is furnished to do so, subject to the following conditions: * + * * + * The above copyright notice and this permission notice shall be included in * + * all copies or substantial portions of the Software. * + * * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * + * DEALINGS IN THE SOFTWARE. * + * * + * This agreement shall be governed in all respects by the laws of the State * + * of California and by the laws of the United States of America. * + * Altera does not recommend, suggest or require that this reference design * + * file be used in conjunction or combination with any other product. * + ******************************************************************************/ diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/92/1092edfdccab001312eeeea4d67ccb1b b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/92/1092edfdccab001312eeeea4d67ccb1b new file mode 100644 index 00000000..61b14366 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/92/1092edfdccab001312eeeea4d67ccb1b @@ -0,0 +1,76 @@ +/* + * MotorHandler.h + * + * Created on: 2014-03-03 + * Author: Amshu Gongal + */ + +#ifndef MOTORHANDLER_H_ +#define MOTORHANDLER_H_ + +#include "altera_up_avalon_rs232.h" +#include "altera_up_avalon_rs232_regs.h" +#include +#include "Status.h" + +// Motor messages are LSB first +#define MOTOR_START_BYTE 0x80 +#define MOTOR_DEVICE_TYPE 0x00 +#define MOTOR_BOTH_FORWARD 0x01 // both motor forward +#define MOTOR_BOTH_BACKWARD 0x00 //both motor backward +#define MOTOR_MOTOR1_BACKWARD 0x40 // motor 1 backward +#define MOTOR_MOTOR2_BACKWARD 0x60 // motor 2 backward +#define MOTOR_MOTOR1_FORWARD 0x05 // motor 1 forward +#define MOTOR_MOTOR2_FORWARD 0x07 // motor 2 forward +#define MOTOR_CONST_SPEED 0x1F +#define MOTOR_STOP_SPEED 0x00 +#define MOTOR_CHANGE_CONFIGURATION 0X02 + +class MotorHandler { +public: + MotorHandler(); + virtual ~MotorHandler(); + + /* + * Initializes this handler. + * @return OK if the handler was initialized without error + */ + Status init(); + + void forward(); + void backward(); + void right(); + void left(); + void stop(); + void configure(); + void test(); + void reset(); + +private: + /* The device used to send serial commands to the motor controller. */ + alt_up_rs232_dev *motor_dev; + + /* + * Moves in the given direction at constant speed. + * @param direction - the motor and direction to move in, e.g. MOTOR_MOTOR1_FORWARD + * @param description - the string description of the movement, for debugging + */ + void move(char direction, char *description); + + /* + * Moves in the given direction and speed. + * @param direction - the motor and direction to move in, e.g. MOTOR_MOTOR1_FORWARD + * @param speed - the speed to move at, i.e. MOTOR_CONST_SPEED or MOTOR_STOP_SPEED + * @param description - the string description of the movement, for debugging + */ + void move(char direction, char speed, char *description); + + /* + * Sends a byte-length message to the motor controller. + * @param message - the message to send + * @param description - the string description of the message, for debugging + */ + void send(char message, char *description); +}; + +#endif /* MOTORHANDLER_H_ */ diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/94/208cd3228bab001311dbfe770f133bca b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/94/208cd3228bab001311dbfe770f133bca new file mode 100644 index 00000000..5c980acc --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/94/208cd3228bab001311dbfe770f133bca @@ -0,0 +1,153 @@ +/* + * MotorHandler.cpp + * + * Created on: 2014-03-03 + * Author: Amshu Gongal + */ + + +#include + +#include "altera_avalon_pio_regs.h" +#include "includes.h" +#include "system.h" + +#include "MotorHandler.h" + +#define WRITE_FIFO_EMPTY 0x80 +#define MOTOR_ENABLE 1 +#define MOTOR_RESET 0 + +// ALLOCATION +MotorHandler::MotorHandler() {} +MotorHandler::~MotorHandler() {} + +// INITIALIZATION + +/* + * Initializes this handler. + * @return OK if the handler was initialized without error + */ +Status MotorHandler::init() { + // Enable the motor controller. + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, MOTOR_ENABLE); + // Open the serial device to send commands to the motor controller. + motor_dev = alt_up_rs232_open_dev(RS232_MOTOR_NAME); + //printf("%d", motor_dev); + if (motor_dev == NULL) { + return ERR_MOTOR_OPEN; + } else { + return OK; + } +} + +void MotorHandler::configure(){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_CHANGE_CONFIGURATION, "change configuration"); + send(0X01, "2 MOTOR CONFIG"); + printf("\n"); +} +// TESTING + +void MotorHandler::test() { + send(MOTOR_START_BYTE, "test start"); +} + +// MOTOR CONTROL + +/* + * Move rover forward by activating both motors. + */ +void MotorHandler::forward() { + move(MOTOR_MOTOR1_FORWARD, "motor 1 forward"); + move(MOTOR_MOTOR2_FORWARD, "motor 2 forward"); +} + +/* + * Move rover backward by activating both motor backwards. + */ +void MotorHandler::backward() { + move(MOTOR_MOTOR1_BACKWARD, "motor 1 backward"); + move(MOTOR_MOTOR2_BACKWARD, "motor 2 backward"); +} + +/* + * Turn rover left. + */ +void MotorHandler::left() { + move(MOTOR_MOTOR2_FORWARD, "motor 1 forward"); +} + +/* + * Turn rover right. + */ +void MotorHandler::right() { + move(MOTOR_MOTOR2_FORWARD, "motor 2 forward"); +} + +/* + * Stop the rover. + */ +void MotorHandler::stop() { + move(MOTOR_MOTOR1_FORWARD, MOTOR_STOP_SPEED, "motor 1 stop"); + move(MOTOR_MOTOR2_FORWARD, MOTOR_STOP_SPEED, "motor 2 stop"); +} + +// MOTOR CONTROL HELPERS + +/* + * Moves in the given direction at constant speed. + * @param direction - the motor and direction to move in, e.g. MOTOR_MOTOR1_FORWARD + * @param description - the string description of the movement, for debugging + */ +void MotorHandler::move(char direction, char *description) { + move(direction, MOTOR_CONST_SPEED, description); +} + +/* + * Moves in the given direction and speed. + * @param direction - the motor and direction to move in, e.g. MOTOR_MOTOR1_FORWARD + * @param speed - the speed to move at, i.e. MOTOR_CONST_SPEED or MOTOR_STOP_SPEED + * @param description - the string description of the movement, for debugging + */ +void MotorHandler::move(char direction, char speed, char *description) { + send(MOTOR_START_BYTE, "start"); + send(MOTOR_DEVICE_TYPE, "device"); + send(direction, description); + send(speed, "speed"); + printf("\n"); +} + +/* + * Sends a byte-length message to the motor controller. + * @param message - the message to send + * @param description - the string description of the message, for debugging + */ +void MotorHandler::send(char message, char *description) { + alt_u32 write_space; + // Check for write space. + write_space = alt_up_rs232_get_available_space_in_write_FIFO(motor_dev); + if (write_space >= WRITE_FIFO_EMPTY) { + // If space, write. + int status = alt_up_rs232_write_data(motor_dev, message); + printf("MotorHandler [message: 0x%02x, description: %s", message, description); + // Log errors. + if (status == OK) { + printf("]\n"); + } else { + printf(", error: cannot write]\n"); + } + } else { + // If no space, wait and retry. + printf("MotorHandler [message: 0x%02x, description: %s, error: no write space; retrying]\n", message, description); + OSTimeDlyHMSM(0, 0, 0, 10); + send(message, description); + } +} + +void MotorHandler::reset(){ + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 0); + OSTimeDlyHMSM(0, 0, 0, 100); + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 1); + OSTimeDlyHMSM(0, 0, 0, 100); +} diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/97/60763cb286b000131eb0f6c547a05c39 b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/97/60763cb286b000131eb0f6c547a05c39 new file mode 100644 index 00000000..3fcbe078 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/97/60763cb286b000131eb0f6c547a05c39 @@ -0,0 +1,70 @@ +/* + * MotorHandler.h + * + * Created on: 2014-03-03 + * Author: Amshu Gongal + */ + +#ifndef MOTORHANDLER_H_ +#define MOTORHANDLER_H_ + +#include "altera_up_avalon_rs232.h" +#include "altera_up_avalon_rs232_regs.h" +#include +using namespace std; +#include +#include "Status.h" + +//Commands from network handler +#define MOTOR_LEFT "left" +#define MOTOR_RIGHT "right" +#define MOTOR_FORWARD "forward" +#define MOTOR_BACKWARD "backward" + + +// Motor messages are LSB first +#define MOTOR_START_BYTE 0x80 +#define MOTOR_DEVICE_TYPE 0x00 +#define MOTOR_LEFT_BACKWARD 0x04 // motor 1 backward +#define MOTOR_RIGHT_BACKWARD 0x06 // motor 2 backward +#define MOTOR_LEFT_FORWARD 0x05 // motor 1 forward +#define MOTOR_RIGHT_FORWARD 0x07 // motor 2 forward +#define MOTOR_CONST_SPEED 0x5F +#define MOTOR_STOP_SPEED 0x00 +#define MOTOR_CHANGE_CONFIGURATION 0X02 + +class MotorHandler { +public: + MotorHandler(); + virtual ~MotorHandler(); + + /* + * Initializes this handler. + * @return OK if the handler was initialized without error + */ + Status init(); + void reset(); + void configure(); + void motorCommand(string motor, string motorDirection, string speed); + +private: + /* The device used to send serial commands to the motor controller. */ + alt_up_rs232_dev *motor_dev; + + /* + * Moves in the given direction at constant speed. + * @param direction - the motor and direction to move in, e.g. MOTOR_MOTOR1_FORWARD + * @param speed speed of the motor + * @param description - the string description of the movement, for debugging + */ + void move(char direction, char speed, char *description); + + /* + * Sends a byte-length message to the motor controller. + * @param message - the message to send + * @param description - the string description of the message, for debugging + */ + void send(char message, char *description); +}; + +#endif /* MOTORHANDLER_H_ */ diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/9a/809283ee8fab001311dbfe770f133bca b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/9a/809283ee8fab001311dbfe770f133bca new file mode 100644 index 00000000..f938b4e0 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/9a/809283ee8fab001311dbfe770f133bca @@ -0,0 +1,148 @@ +/************************************************************************* + * ARCap + * Amshu Gongal, Kenan Kigunda + * February 18, 2014 + ************************************************************************** + * Description: * + * Prototype testing for infrared and mc. + **************************************************************************/ + +#include +#include "includes.h" +#include "altera_avalon_pio_regs.h" +#include "altera_avalon_uart_regs.h" +#include "sys/alt_irq.h" +#include "alt_types.h" +#include "altera_up_avalon_rs232.h" +#include "altera_up_avalon_rs232_regs.h" + +#include "MotorHandler.h" +#include "Status.h" + +/* Task stacks */ +#define TASK_STACKSIZE 2048 +OS_STK ir_task_stk[TASK_STACKSIZE]; +OS_STK mc_task_stk[TASK_STACKSIZE]; +/* Task priorities */ +#define IR_TASK_PRIORITY 2 +#define MC_TASK_PRIORITY 1 + + +#define SW_READ 1 +#define SW_WRITE 2 +#define WRITE_FIFO_EMPTY 0x80 +#define READ_FIFO_EMPTY 0x0 +OS_EVENT *SWQ; +OS_EVENT *RS232Q; +INT8U err; + + +/* Error status */ +#define OK 0 + +/* Message queues */ +#define WAIT_FOREVER 0 + +// ==== INFRARED ==== + +/* Infrared message queue */ +#define IR_MAX_MESSAGES 4 +int ir_messages[IR_MAX_MESSAGES]; +OS_EVENT *ir_queue; + +/* Infrared messages */ +// Together these avoid passing 0 to the queue (which is not allowed since queue messages cannot be null) +// and invert pushbutton input (since the pushbutton returns 0 when it is pushed down). +#define IR_QUEUE_SEND_BASE 1 // Use: IR_QUEUE_SEND_BASE + IORD +#define IR_QUEUE_RECEIVE_BASE 2 // Use: IR_QUEUE_RECEIVE_BASE - OSQPend + + +MotorHandler *motor= new MotorHandler(); + + +// ==== mc + +#define mc_GUARD_TIME 1 + +void mc_task(void *pdata) +{ + printf("mc task\n"); + printf("MotorHandler [init"); + if (motor->init() == OK) { + printf("]\n\n"); + motor->forward(); + } else { + printf( ", error]\n"); + } + while(1){ + motor->forward(); + OSTimeDlyHMSM(0, 0, 0, 100); + } +} + + + +// ==== GENERAL + +void queue_init() { + ir_queue = OSQCreate((void**)&ir_messages, IR_MAX_MESSAGES); +} + +/* The main function creates the LCD task, registers the edge counter polling interrupt, + * and starts the OS. */ +int main(void) +{ + int status = OK; + // Initialize components. + queue_init(); + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 1); + OSTimeDlyHMSM(0,0,0,100); + // Create the mc task. + OSTaskCreateExt(mc_task, + NULL, + &mc_task_stk[TASK_STACKSIZE - 1], + MC_TASK_PRIORITY, + MC_TASK_PRIORITY, + mc_task_stk, + TASK_STACKSIZE, + NULL, + 0); + + + if (status == OK) { + OSStart(); + } + + return 0; +} + +/****************************************************************************** + * * + * License Agreement * + * * + * Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * + * All rights reserved. * + * * + * Permission is hereby granted, free of charge, to any person obtaining a * + * copy of this software and associated documentation files (the "Software"), * + * to deal in the Software without restriction, including without limitation * + * the rights to use, copy, modify, merge, publish, distribute, sublicense, * + * and/or sell copies of the Software, and to permit persons to whom the * + * Software is furnished to do so, subject to the following conditions: * + * * + * The above copyright notice and this permission notice shall be included in * + * all copies or substantial portions of the Software. * + * * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * + * DEALINGS IN THE SOFTWARE. * + * * + * This agreement shall be governed in all respects by the laws of the State * + * of California and by the laws of the United States of America. * + * Altera does not recommend, suggest or require that this reference design * + * file be used in conjunction or combination with any other product. * + ******************************************************************************/ diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/9f/a0987b9e8fab001311dbfe770f133bca b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/9f/a0987b9e8fab001311dbfe770f133bca new file mode 100644 index 00000000..b42867b8 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/9f/a0987b9e8fab001311dbfe770f133bca @@ -0,0 +1,146 @@ +/************************************************************************* + * ARCap + * Amshu Gongal, Kenan Kigunda + * February 18, 2014 + ************************************************************************** + * Description: * + * Prototype testing for infrared and mc. + **************************************************************************/ + +#include +#include "includes.h" +#include "altera_avalon_pio_regs.h" +#include "altera_avalon_uart_regs.h" +#include "sys/alt_irq.h" +#include "alt_types.h" +#include "altera_up_avalon_rs232.h" +#include "altera_up_avalon_rs232_regs.h" + +#include "MotorHandler.h" +#include "Status.h" + +/* Task stacks */ +#define TASK_STACKSIZE 2048 +OS_STK ir_task_stk[TASK_STACKSIZE]; +OS_STK mc_task_stk[TASK_STACKSIZE]; +/* Task priorities */ +#define IR_TASK_PRIORITY 2 +#define MC_TASK_PRIORITY 1 + + +#define SW_READ 1 +#define SW_WRITE 2 +#define WRITE_FIFO_EMPTY 0x80 +#define READ_FIFO_EMPTY 0x0 +OS_EVENT *SWQ; +OS_EVENT *RS232Q; +INT8U err; + + +/* Error status */ +#define OK 0 + +/* Message queues */ +#define WAIT_FOREVER 0 + +// ==== INFRARED ==== + +/* Infrared message queue */ +#define IR_MAX_MESSAGES 4 +int ir_messages[IR_MAX_MESSAGES]; +OS_EVENT *ir_queue; + +/* Infrared messages */ +// Together these avoid passing 0 to the queue (which is not allowed since queue messages cannot be null) +// and invert pushbutton input (since the pushbutton returns 0 when it is pushed down). +#define IR_QUEUE_SEND_BASE 1 // Use: IR_QUEUE_SEND_BASE + IORD +#define IR_QUEUE_RECEIVE_BASE 2 // Use: IR_QUEUE_RECEIVE_BASE - OSQPend + + +MotorHandler *motor= new MotorHandler(); + + +// ==== mc + +#define mc_GUARD_TIME 1 + +void mc_task(void *pdata) +{ + printf("mc task\n"); + printf("MotorHandler [init"); + if (motor->init() == OK) { + printf("]\n\n"); + motor->forward(); + } else { + printf( ", error]\n"); + } + while(1){ + motor->forward(); + OSTimeDlyHMSM(0, 0, 0, 100); + } +} + + + +// ==== GENERAL + +void queue_init() { + ir_queue = OSQCreate((void**)&ir_messages, IR_MAX_MESSAGES); +} + +/* The main function creates the LCD task, registers the edge counter polling interrupt, + * and starts the OS. */ +int main(void) +{ + int status = OK; + // Initialize components. + queue_init(); + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 1); + // Create the mc task. + OSTaskCreateExt(mc_task, + NULL, + &mc_task_stk[TASK_STACKSIZE - 1], + MC_TASK_PRIORITY, + MC_TASK_PRIORITY, + mc_task_stk, + TASK_STACKSIZE, + NULL, + 0); + + if (status == OK) { + OSStart(); + } + + return 0; +} + +/****************************************************************************** + * * + * License Agreement * + * * + * Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * + * All rights reserved. * + * * + * Permission is hereby granted, free of charge, to any person obtaining a * + * copy of this software and associated documentation files (the "Software"), * + * to deal in the Software without restriction, including without limitation * + * the rights to use, copy, modify, merge, publish, distribute, sublicense, * + * and/or sell copies of the Software, and to permit persons to whom the * + * Software is furnished to do so, subject to the following conditions: * + * * + * The above copyright notice and this permission notice shall be included in * + * all copies or substantial portions of the Software. * + * * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * + * DEALINGS IN THE SOFTWARE. * + * * + * This agreement shall be governed in all respects by the laws of the State * + * of California and by the laws of the United States of America. * + * Altera does not recommend, suggest or require that this reference design * + * file be used in conjunction or combination with any other product. * + ******************************************************************************/ diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/a0/1067168480b000131eb0f6c547a05c39 b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/a0/1067168480b000131eb0f6c547a05c39 new file mode 100644 index 00000000..15822862 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/a0/1067168480b000131eb0f6c547a05c39 @@ -0,0 +1,147 @@ +/************************************************************************* + * ARCap + * Amshu Gongal, Kenan Kigunda + * February 18, 2014 + ************************************************************************** + * Description: * + * Prototype testing for infrared and mc. + **************************************************************************/ + +#include +#include "includes.h" +#include "altera_avalon_pio_regs.h" +#include "altera_avalon_uart_regs.h" +#include "sys/alt_irq.h" +#include "alt_types.h" +#include "altera_up_avalon_rs232.h" +#include "altera_up_avalon_rs232_regs.h" + +#include "MotorHandler.h" +#include "Status.h" + +/* Task stacks */ +#define TASK_STACKSIZE 2048 +OS_STK ir_task_stk[TASK_STACKSIZE]; +OS_STK mc_task_stk[TASK_STACKSIZE]; +/* Task priorities */ +#define IR_TASK_PRIORITY 2 +#define MC_TASK_PRIORITY 1 + + +#define SW_READ 1 +#define SW_WRITE 2 +#define WRITE_FIFO_EMPTY 0x80 +#define READ_FIFO_EMPTY 0x0 +OS_EVENT *SWQ; +OS_EVENT *RS232Q; +INT8U err; + + +/* Error status */ +#define OK 0 + +/* Message queues */ +#define WAIT_FOREVER 0 + +// ==== INFRARED ==== + +/* Infrared message queue */ +#define IR_MAX_MESSAGES 4 +int ir_messages[IR_MAX_MESSAGES]; +OS_EVENT *ir_queue; + +/* Infrared messages */ +// Together these avoid passing 0 to the queue (which is not allowed since queue messages cannot be null) +// and invert pushbutton input (since the pushbutton returns 0 when it is pushed down). +#define IR_QUEUE_SEND_BASE 1 // Use: IR_QUEUE_SEND_BASE + IORD +#define IR_QUEUE_RECEIVE_BASE 2 // Use: IR_QUEUE_RECEIVE_BASE - OSQPend + + +MotorHandler *motor= new MotorHandler(); + + +// ==== mc + +#define mc_GUARD_TIME 1 + +void mc_task(void *pdata) +{ + printf("mc task\n"); + printf("MotorHandler [init"); + if (motor->init() == OK) { + printf("]\n\n"); + } else { + printf( ", error]\n"); + } + while(1){ + motor->move(0x05, 0x6F, "Left Motor Forward"); + OSTimeDlyHMSM(0, 0, 5, 0); + motor->stop(); + OSTimeDlyHMSM(0, 0, 3,0); + + } +} + + + +// ==== GENERAL + +void queue_init() { + ir_queue = OSQCreate((void**)&ir_messages, IR_MAX_MESSAGES); +} + +/* The main function creates the LCD task, registers the edge counter polling interrupt, + * and starts the OS. */ +int main(void) +{ + int status = OK; + // Initialize components. + queue_init(); + // Create the mc task. + OSTaskCreateExt(mc_task, + NULL, + &mc_task_stk[TASK_STACKSIZE - 1], + MC_TASK_PRIORITY, + MC_TASK_PRIORITY, + mc_task_stk, + TASK_STACKSIZE, + NULL, + 0); + + if (status == OK) { + OSStart(); + } + + return 0; +} + +/****************************************************************************** + * * + * License Agreement * + * * + * Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * + * All rights reserved. * + * * + * Permission is hereby granted, free of charge, to any person obtaining a * + * copy of this software and associated documentation files (the "Software"), * + * to deal in the Software without restriction, including without limitation * + * the rights to use, copy, modify, merge, publish, distribute, sublicense, * + * and/or sell copies of the Software, and to permit persons to whom the * + * Software is furnished to do so, subject to the following conditions: * + * * + * The above copyright notice and this permission notice shall be included in * + * all copies or substantial portions of the Software. * + * * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * + * DEALINGS IN THE SOFTWARE. * + * * + * This agreement shall be governed in all respects by the laws of the State * + * of California and by the laws of the United States of America. * + * Altera does not recommend, suggest or require that this reference design * + * file be used in conjunction or combination with any other product. * + ******************************************************************************/ diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/a8/804380f08ab000131eb0f6c547a05c39 b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/a8/804380f08ab000131eb0f6c547a05c39 new file mode 100644 index 00000000..73c6d899 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/a8/804380f08ab000131eb0f6c547a05c39 @@ -0,0 +1,73 @@ +/* + * MotorHandler.h + * + * Created on: 2014-03-03 + * Author: Amshu Gongal + */ + +#ifndef MOTORHANDLER_H_ +#define MOTORHANDLER_H_ + +#include "altera_up_avalon_rs232.h" +#include "altera_up_avalon_rs232_regs.h" +#include +using namespace std; +#include +#include "Status.h" + +//Commands from network handler +#define MOTOR_LEFT "left" +#define MOTOR_RIGHT "right" +#define MOTOR_FORWARD "forward" +#define MOTOR_BACKWARD "backward" + + +// Motor messages are LSB first +#define MOTOR_START_BYTE 0x80 +#define MOTOR_DEVICE_TYPE 0x00 +#define MOTOR_LEFT_CHAR 0x02 // motor 1 backward +#define MOTOR_RIGHT_CHAR 0x03 // motor 2 backward +#define MOTOR_LEFT_FORWARD 0x05 // motor 1 forward +#define MOTOR_RIGHT_FORWARD 0x07 // motor 2 forward +#define MOTOR_CONST_SPEED 0x5F +#define MOTOR_STOP_SPEED 0x00 +#define MOTOR_CHANGE_CONFIGURATION 0X02 + +class MotorHandler { +public: + MotorHandler(); + virtual ~MotorHandler(); + + /* + * Initializes this handler. + * @return OK if the handler was initialized without error + */ + Status init(); + void reset(); + void configure(); + void motorCommand(string motor, string motorDirection, string speed); + +private: + /* The device used to send serial commands to the motor controller. */ + alt_up_rs232_dev *motor_dev; + + char interpretMotor(string motor); + char interpretDirection(string direction, int motor); + + /* + * Moves in the given direction at constant speed. + * @param direction - the motor and direction to move in, e.g. MOTOR_MOTOR1_FORWARD + * @param speed speed of the motor + * @param description - the string description of the movement, for debugging + */ + void move(char direction, char speed, char *description); + + /* + * Sends a byte-length message to the motor controller. + * @param message - the message to send + * @param description - the string description of the message, for debugging + */ + void send(char message, char *description); +}; + +#endif /* MOTORHANDLER_H_ */ diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/ab/9017dacba8ab001311f2ce252b4696cb b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/ab/9017dacba8ab001311f2ce252b4696cb new file mode 100644 index 00000000..321d9d5c --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/ab/9017dacba8ab001311f2ce252b4696cb @@ -0,0 +1,152 @@ +/************************************************************************* + * ARCap + * Amshu Gongal, Kenan Kigunda + * February 18, 2014 + ************************************************************************** + * Description: * + * Prototype testing for infrared and mc. + **************************************************************************/ + +#include +#include "includes.h" +#include "altera_avalon_pio_regs.h" +#include "altera_avalon_uart_regs.h" +#include "sys/alt_irq.h" +#include "alt_types.h" +#include "altera_up_avalon_rs232.h" +#include "altera_up_avalon_rs232_regs.h" + +#include "MotorHandler.h" +#include "Status.h" + +/* Task stacks */ +#define TASK_STACKSIZE 2048 +OS_STK ir_task_stk[TASK_STACKSIZE]; +OS_STK mc_task_stk[TASK_STACKSIZE]; +/* Task priorities */ +#define IR_TASK_PRIORITY 2 +#define MC_TASK_PRIORITY 1 + + +#define SW_READ 1 +#define SW_WRITE 2 +#define WRITE_FIFO_EMPTY 0x80 +#define READ_FIFO_EMPTY 0x0 +OS_EVENT *SWQ; +OS_EVENT *RS232Q; +INT8U err; + + +/* Error status */ +#define OK 0 + +/* Message queues */ +#define WAIT_FOREVER 0 + +// ==== INFRARED ==== + +/* Infrared message queue */ +#define IR_MAX_MESSAGES 4 +int ir_messages[IR_MAX_MESSAGES]; +OS_EVENT *ir_queue; + +/* Infrared messages */ +// Together these avoid passing 0 to the queue (which is not allowed since queue messages cannot be null) +// and invert pushbutton input (since the pushbutton returns 0 when it is pushed down). +#define IR_QUEUE_SEND_BASE 1 // Use: IR_QUEUE_SEND_BASE + IORD +#define IR_QUEUE_RECEIVE_BASE 2 // Use: IR_QUEUE_RECEIVE_BASE - OSQPend + + +MotorHandler *motor= new MotorHandler(); + + +// ==== mc + +#define mc_GUARD_TIME 1 + +void mc_task(void *pdata) +{ + printf("mc task\n"); + printf("MotorHandler [init"); + if (motor->init() == OK) { + printf("]\n\n"); + motor->forward(); + } else { + printf( ", error]\n"); + } + while(1){ + motor->forward(); + OSTimeDlyHMS(0,3,0); + motor->backward(); + OSTimeDlyHMS(0,3,0); + motor->left(); + OSTimeDlyHMS(0,3,0); + motor->right(); + OSTimeDlyHMS(0,3,0); + + } +} + + + +// ==== GENERAL + +void queue_init() { + ir_queue = OSQCreate((void**)&ir_messages, IR_MAX_MESSAGES); +} + +/* The main function creates the LCD task, registers the edge counter polling interrupt, + * and starts the OS. */ +int main(void) +{ + int status = OK; + // Initialize components. + queue_init(); + // Create the mc task. + OSTaskCreateExt(mc_task, + NULL, + &mc_task_stk[TASK_STACKSIZE - 1], + MC_TASK_PRIORITY, + MC_TASK_PRIORITY, + mc_task_stk, + TASK_STACKSIZE, + NULL, + 0); + + if (status == OK) { + OSStart(); + } + + return 0; +} + +/****************************************************************************** + * * + * License Agreement * + * * + * Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * + * All rights reserved. * + * * + * Permission is hereby granted, free of charge, to any person obtaining a * + * copy of this software and associated documentation files (the "Software"), * + * to deal in the Software without restriction, including without limitation * + * the rights to use, copy, modify, merge, publish, distribute, sublicense, * + * and/or sell copies of the Software, and to permit persons to whom the * + * Software is furnished to do so, subject to the following conditions: * + * * + * The above copyright notice and this permission notice shall be included in * + * all copies or substantial portions of the Software. * + * * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * + * DEALINGS IN THE SOFTWARE. * + * * + * This agreement shall be governed in all respects by the laws of the State * + * of California and by the laws of the United States of America. * + * Altera does not recommend, suggest or require that this reference design * + * file be used in conjunction or combination with any other product. * + ******************************************************************************/ diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/b0/80e0236dcdab001312eeeea4d67ccb1b b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/b0/80e0236dcdab001312eeeea4d67ccb1b new file mode 100644 index 00000000..3da071db --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/b0/80e0236dcdab001312eeeea4d67ccb1b @@ -0,0 +1,148 @@ +/************************************************************************* + * ARCap + * Amshu Gongal, Kenan Kigunda + * February 18, 2014 + ************************************************************************** + * Description: * + * Prototype testing for infrared and mc. + **************************************************************************/ + +#include +#include "includes.h" +#include "altera_avalon_pio_regs.h" +#include "altera_avalon_uart_regs.h" +#include "sys/alt_irq.h" +#include "alt_types.h" +#include "altera_up_avalon_rs232.h" +#include "altera_up_avalon_rs232_regs.h" + +#include "MotorHandler.h" +#include "Status.h" + +/* Task stacks */ +#define TASK_STACKSIZE 2048 +OS_STK ir_task_stk[TASK_STACKSIZE]; +OS_STK mc_task_stk[TASK_STACKSIZE]; +/* Task priorities */ +#define IR_TASK_PRIORITY 2 +#define MC_TASK_PRIORITY 1 + + +#define SW_READ 1 +#define SW_WRITE 2 +#define WRITE_FIFO_EMPTY 0x80 +#define READ_FIFO_EMPTY 0x0 +OS_EVENT *SWQ; +OS_EVENT *RS232Q; +INT8U err; + + +/* Error status */ +#define OK 0 + +/* Message queues */ +#define WAIT_FOREVER 0 + +// ==== INFRARED ==== + +/* Infrared message queue */ +#define IR_MAX_MESSAGES 4 +int ir_messages[IR_MAX_MESSAGES]; +OS_EVENT *ir_queue; + +/* Infrared messages */ +// Together these avoid passing 0 to the queue (which is not allowed since queue messages cannot be null) +// and invert pushbutton input (since the pushbutton returns 0 when it is pushed down). +#define IR_QUEUE_SEND_BASE 1 // Use: IR_QUEUE_SEND_BASE + IORD +#define IR_QUEUE_RECEIVE_BASE 2 // Use: IR_QUEUE_RECEIVE_BASE - OSQPend + + +MotorHandler *motor= new MotorHandler(); + + +// ==== mc + +#define mc_GUARD_TIME 1 + +void mc_task(void *pdata) +{ + printf("mc task\n"); + printf("MotorHandler [init"); + if (motor->init() == OK) { + printf("]\n\n"); + motor->forward(); + } else { + printf( ", error]\n"); + } + while(1){ + motor->forward(); + OSTimeDlyHMSM(0, 0, 2, 0); + motor->stop(); + OSTimeDlyHMSM(0, 0, 3,0); + + } +} + + + +// ==== GENERAL + +void queue_init() { + ir_queue = OSQCreate((void**)&ir_messages, IR_MAX_MESSAGES); +} + +/* The main function creates the LCD task, registers the edge counter polling interrupt, + * and starts the OS. */ +int main(void) +{ + int status = OK; + // Initialize components. + queue_init(); + // Create the mc task. + OSTaskCreateExt(mc_task, + NULL, + &mc_task_stk[TASK_STACKSIZE - 1], + MC_TASK_PRIORITY, + MC_TASK_PRIORITY, + mc_task_stk, + TASK_STACKSIZE, + NULL, + 0); + + if (status == OK) { + OSStart(); + } + + return 0; +} + +/****************************************************************************** + * * + * License Agreement * + * * + * Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * + * All rights reserved. * + * * + * Permission is hereby granted, free of charge, to any person obtaining a * + * copy of this software and associated documentation files (the "Software"), * + * to deal in the Software without restriction, including without limitation * + * the rights to use, copy, modify, merge, publish, distribute, sublicense, * + * and/or sell copies of the Software, and to permit persons to whom the * + * Software is furnished to do so, subject to the following conditions: * + * * + * The above copyright notice and this permission notice shall be included in * + * all copies or substantial portions of the Software. * + * * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * + * DEALINGS IN THE SOFTWARE. * + * * + * This agreement shall be governed in all respects by the laws of the State * + * of California and by the laws of the United States of America. * + * Altera does not recommend, suggest or require that this reference design * + * file be used in conjunction or combination with any other product. * + ******************************************************************************/ diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/b1/20df12738aab001311dbfe770f133bca b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/b1/20df12738aab001311dbfe770f133bca new file mode 100644 index 00000000..5c980acc --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/b1/20df12738aab001311dbfe770f133bca @@ -0,0 +1,153 @@ +/* + * MotorHandler.cpp + * + * Created on: 2014-03-03 + * Author: Amshu Gongal + */ + + +#include + +#include "altera_avalon_pio_regs.h" +#include "includes.h" +#include "system.h" + +#include "MotorHandler.h" + +#define WRITE_FIFO_EMPTY 0x80 +#define MOTOR_ENABLE 1 +#define MOTOR_RESET 0 + +// ALLOCATION +MotorHandler::MotorHandler() {} +MotorHandler::~MotorHandler() {} + +// INITIALIZATION + +/* + * Initializes this handler. + * @return OK if the handler was initialized without error + */ +Status MotorHandler::init() { + // Enable the motor controller. + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, MOTOR_ENABLE); + // Open the serial device to send commands to the motor controller. + motor_dev = alt_up_rs232_open_dev(RS232_MOTOR_NAME); + //printf("%d", motor_dev); + if (motor_dev == NULL) { + return ERR_MOTOR_OPEN; + } else { + return OK; + } +} + +void MotorHandler::configure(){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_CHANGE_CONFIGURATION, "change configuration"); + send(0X01, "2 MOTOR CONFIG"); + printf("\n"); +} +// TESTING + +void MotorHandler::test() { + send(MOTOR_START_BYTE, "test start"); +} + +// MOTOR CONTROL + +/* + * Move rover forward by activating both motors. + */ +void MotorHandler::forward() { + move(MOTOR_MOTOR1_FORWARD, "motor 1 forward"); + move(MOTOR_MOTOR2_FORWARD, "motor 2 forward"); +} + +/* + * Move rover backward by activating both motor backwards. + */ +void MotorHandler::backward() { + move(MOTOR_MOTOR1_BACKWARD, "motor 1 backward"); + move(MOTOR_MOTOR2_BACKWARD, "motor 2 backward"); +} + +/* + * Turn rover left. + */ +void MotorHandler::left() { + move(MOTOR_MOTOR2_FORWARD, "motor 1 forward"); +} + +/* + * Turn rover right. + */ +void MotorHandler::right() { + move(MOTOR_MOTOR2_FORWARD, "motor 2 forward"); +} + +/* + * Stop the rover. + */ +void MotorHandler::stop() { + move(MOTOR_MOTOR1_FORWARD, MOTOR_STOP_SPEED, "motor 1 stop"); + move(MOTOR_MOTOR2_FORWARD, MOTOR_STOP_SPEED, "motor 2 stop"); +} + +// MOTOR CONTROL HELPERS + +/* + * Moves in the given direction at constant speed. + * @param direction - the motor and direction to move in, e.g. MOTOR_MOTOR1_FORWARD + * @param description - the string description of the movement, for debugging + */ +void MotorHandler::move(char direction, char *description) { + move(direction, MOTOR_CONST_SPEED, description); +} + +/* + * Moves in the given direction and speed. + * @param direction - the motor and direction to move in, e.g. MOTOR_MOTOR1_FORWARD + * @param speed - the speed to move at, i.e. MOTOR_CONST_SPEED or MOTOR_STOP_SPEED + * @param description - the string description of the movement, for debugging + */ +void MotorHandler::move(char direction, char speed, char *description) { + send(MOTOR_START_BYTE, "start"); + send(MOTOR_DEVICE_TYPE, "device"); + send(direction, description); + send(speed, "speed"); + printf("\n"); +} + +/* + * Sends a byte-length message to the motor controller. + * @param message - the message to send + * @param description - the string description of the message, for debugging + */ +void MotorHandler::send(char message, char *description) { + alt_u32 write_space; + // Check for write space. + write_space = alt_up_rs232_get_available_space_in_write_FIFO(motor_dev); + if (write_space >= WRITE_FIFO_EMPTY) { + // If space, write. + int status = alt_up_rs232_write_data(motor_dev, message); + printf("MotorHandler [message: 0x%02x, description: %s", message, description); + // Log errors. + if (status == OK) { + printf("]\n"); + } else { + printf(", error: cannot write]\n"); + } + } else { + // If no space, wait and retry. + printf("MotorHandler [message: 0x%02x, description: %s, error: no write space; retrying]\n", message, description); + OSTimeDlyHMSM(0, 0, 0, 10); + send(message, description); + } +} + +void MotorHandler::reset(){ + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 0); + OSTimeDlyHMSM(0, 0, 0, 100); + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 1); + OSTimeDlyHMSM(0, 0, 0, 100); +} diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/b1/404259d289b000131eb0f6c547a05c39 b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/b1/404259d289b000131eb0f6c547a05c39 new file mode 100644 index 00000000..3142b74c --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/b1/404259d289b000131eb0f6c547a05c39 @@ -0,0 +1,134 @@ +/* + * MotorHandler.cpp + * + * Created on: 2014-03-03 + * Author: Amshu Gongal + */ + + +#include + +#include "altera_avalon_pio_regs.h" +#include "includes.h" +#include "system.h" + +#include "MotorHandler.h" + +#define WRITE_FIFO_EMPTY 0x80 +#define MOTOR_ENABLE 1 +#define MOTOR_RESET 0 + +// ALLOCATION +MotorHandler::MotorHandler() {} +MotorHandler::~MotorHandler() {} + + +// INITIALIZATION + +/* + * Initializes this handler. + * @return OK if the handler was initialized without error + */ +Status MotorHandler::init() { + // Enable the motor controller. + reset(); + // Open the serial device to send commands to the motor controller. + motor_dev = alt_up_rs232_open_dev(RS232_MOTOR_NAME); + //printf("%d", motor_dev); + if (motor_dev == NULL) { + return ERR_MOTOR_OPEN; + } else { + return OK; + } +} + +void MotorHandler::configure(){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_CHANGE_CONFIGURATION, "change configuration"); + send(0X01, "2 MOTOR CONFIG"); + printf("\n"); +} + +//Command Interpreter +/* + * Interprets the command from the network handler and sends move commands + * @param motor The motor to move eg. Left or Right + * @param motorDirection The direction of the given motor to move + * @param speed The speed the motor is to move + */ +void MotorHandler::motorCommand(string motor, string motorDirection, string speed){ + char motorID = interpretMotor(motor); + char directionByte = interpretDirection(motorDirection, int(motorID)); + int speedByte = strtol(speed.c_str()); + move(Direction, Speed, "Move Motor"); +} + +char MotorHandler::interpretMotor(string motor){ + if(motor.compare(MOTOR_LEFT) == 0){ + return MOTOR_LEFT_CHAR; + } + else{ + return MOTOR_RIGHT_CHAR; + } +} + +char MotorHandler::interpretDirection(string direction, int motor){ + if(direction.compare(MOTOR_FORWARD) == 0){ + return (char) (motor*2 + 1); + } + else{ + return (char) (motor*2); + } +} + +// MOTOR CONTROL + +/*Moves the given motor in specified direction by Motor Direction with specified + * Speed + * @param MotorDirection Motor and direction to move + * @param Speed the speed to move at + * @param string description of motor movement + */ + +void MotorHandler::move(char MotorDirection,char Speed,char * Description){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_DEVICE_TYPE, "device"); + send(MotorDirection, Description); + send(Speed, "speed"); + printf("\n"); +} + +// MOTOR CONTROL HELPERS +/* + * Sends a byte-length message to the motor controller. + * @param message - the message to send + * @param description - the string description of the message, for debugging + */ +void MotorHandler::send(char message, char *description) { + alt_u32 write_space; + // Check for write space. + write_space = alt_up_rs232_get_available_space_in_write_FIFO(motor_dev); + if (write_space >= WRITE_FIFO_EMPTY) { + // If space, write. + int status = alt_up_rs232_write_data(motor_dev, message); + printf("MotorHandler [message: 0x%02x, description: %s", message, description); + // Log errors. + if (status == OK) { + printf("]\n"); + } else { + printf(", error: cannot write]\n"); + } + } else { + // If no space, wait and retry. + printf("MotorHandler [message: 0x%02x, description: %s, error: no write space; retrying]\n", message, description); + OSTimeDlyHMSM(0, 0, 0, 10); + send(message, description); + } +} + +void MotorHandler::reset(){ + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 0); + OSTimeDlyHMSM(0, 0, 0,200 ); + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 1); + OSTimeDlyHMSM(0, 0, 0, 200); +} diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/b6/80476fca8bb000131eb0f6c547a05c39 b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/b6/80476fca8bb000131eb0f6c547a05c39 new file mode 100644 index 00000000..e3d177c2 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/b6/80476fca8bb000131eb0f6c547a05c39 @@ -0,0 +1,136 @@ +/* + * MotorHandler.cpp + * + * Created on: 2014-03-03 + * Author: Amshu Gongal + */ + + +#include +#include + +#include "altera_avalon_pio_regs.h" +#include "includes.h" +#include "system.h" + +#include "MotorHandler.h" + +#define WRITE_FIFO_EMPTY 0x80 +#define MOTOR_ENABLE 1 +#define MOTOR_RESET 0 + +// ALLOCATION +MotorHandler::MotorHandler() {} +MotorHandler::~MotorHandler() {} + + +// INITIALIZATION + +/* + * Initializes this handler. + * @return OK if the handler was initialized without error + */ +Status MotorHandler::init() { + // Enable the motor controller. + reset(); + // Open the serial device to send commands to the motor controller. + motor_dev = alt_up_rs232_open_dev(RS232_MOTOR_NAME); + //printf("%d", motor_dev); + if (motor_dev == NULL) { + return ERR_MOTOR_OPEN; + } else { + return OK; + } +} + +void MotorHandler::configure(){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_CHANGE_CONFIGURATION, "change configuration"); + send(0X01, "2 MOTOR CONFIG"); + printf("\n"); +} + +//Command Interpreter +/* + * Interprets the command from the network handler and sends move commands + * @param motor The motor to move eg. Left or Right + * @param motorDirection The direction of the given motor to move + * @param speed The speed the motor is to move + */ +void MotorHandler::motorCommand(string motor, string motorDirection, string speed){ + char motorID = interpretMotor(motor); + char directionByte = interpretDirection(motorDirection, int(motorID)); + int speedByte = strtol(speed.c_str(), NULL, 0); + move(directionByte, speedByte, (motor.append(motorDirection)).c_str()); +} + + +char MotorHandler::interpretMotor(string motor){ + if(motor.compare(MOTOR_LEFT) == 0){ + return MOTOR_LEFT_CHAR; + } + else{ + return MOTOR_RIGHT_CHAR; + } +} + +char MotorHandler::interpretDirection(string direction, int motor){ + if(direction.compare(MOTOR_FORWARD) == 0){ + return (char) (motor*2 + 1); + } + else{ + return (char) (motor*2); + } +} + +// MOTOR CONTROL + +/*Moves the given motor in specified direction by Motor Direction with specified + * Speed + * @param MotorDirection Motor and direction to move + * @param Speed the speed to move at + * @param string description of motor movement + */ + +void MotorHandler::move(char motorDirection, char speed,char *description){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_DEVICE_TYPE, "device"); + send(motorDirection, description); + send(speed, "speed"); + printf("\n"); +} + +// MOTOR CONTROL HELPERS +/* + * Sends a byte-length message to the motor controller. + * @param message - the message to send + * @param description - the string description of the message, for debugging + */ +void MotorHandler::send(char message, char *description) { + alt_u32 write_space; + // Check for write space. + write_space = alt_up_rs232_get_available_space_in_write_FIFO(motor_dev); + if (write_space >= WRITE_FIFO_EMPTY) { + // If space, write. + int status = alt_up_rs232_write_data(motor_dev, message); + printf("MotorHandler [message: 0x%02x, description: %s", message, description); + // Log errors. + if (status == OK) { + printf("]\n"); + } else { + printf(", error: cannot write]\n"); + } + } else { + // If no space, wait and retry. + printf("MotorHandler [message: 0x%02x, description: %s, error: no write space; retrying]\n", message, description); + OSTimeDlyHMSM(0, 0, 0, 10); + send(message, description); + } +} + +void MotorHandler::reset(){ + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 0); + OSTimeDlyHMSM(0, 0, 0,200 ); + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 1); + OSTimeDlyHMSM(0, 0, 0, 200); +} diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/b7/109197de89b000131eb0f6c547a05c39 b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/b7/109197de89b000131eb0f6c547a05c39 new file mode 100644 index 00000000..ac8966bc --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/b7/109197de89b000131eb0f6c547a05c39 @@ -0,0 +1,134 @@ +/* + * MotorHandler.cpp + * + * Created on: 2014-03-03 + * Author: Amshu Gongal + */ + + +#include + +#include "altera_avalon_pio_regs.h" +#include "includes.h" +#include "system.h" + +#include "MotorHandler.h" + +#define WRITE_FIFO_EMPTY 0x80 +#define MOTOR_ENABLE 1 +#define MOTOR_RESET 0 + +// ALLOCATION +MotorHandler::MotorHandler() {} +MotorHandler::~MotorHandler() {} + + +// INITIALIZATION + +/* + * Initializes this handler. + * @return OK if the handler was initialized without error + */ +Status MotorHandler::init() { + // Enable the motor controller. + reset(); + // Open the serial device to send commands to the motor controller. + motor_dev = alt_up_rs232_open_dev(RS232_MOTOR_NAME); + //printf("%d", motor_dev); + if (motor_dev == NULL) { + return ERR_MOTOR_OPEN; + } else { + return OK; + } +} + +void MotorHandler::configure(){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_CHANGE_CONFIGURATION, "change configuration"); + send(0X01, "2 MOTOR CONFIG"); + printf("\n"); +} + +//Command Interpreter +/* + * Interprets the command from the network handler and sends move commands + * @param motor The motor to move eg. Left or Right + * @param motorDirection The direction of the given motor to move + * @param speed The speed the motor is to move + */ +void MotorHandler::motorCommand(string motor, string motorDirection, string speed){ + char motorID = interpretMotor(motor); + char directionByte = interpretDirection(motorDirection, int(motorID)); + int speedByte = strtol(speed.c_str()); + move(directionByte, speedByte, "Move Motor"); +} + +char MotorHandler::interpretMotor(string motor){ + if(motor.compare(MOTOR_LEFT) == 0){ + return MOTOR_LEFT_CHAR; + } + else{ + return MOTOR_RIGHT_CHAR; + } +} + +char MotorHandler::interpretDirection(string direction, int motor){ + if(direction.compare(MOTOR_FORWARD) == 0){ + return (char) (motor*2 + 1); + } + else{ + return (char) (motor*2); + } +} + +// MOTOR CONTROL + +/*Moves the given motor in specified direction by Motor Direction with specified + * Speed + * @param MotorDirection Motor and direction to move + * @param Speed the speed to move at + * @param string description of motor movement + */ + +void MotorHandler::move(char MotorDirection,char Speed,char * Description){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_DEVICE_TYPE, "device"); + send(MotorDirection, Description); + send(Speed, "speed"); + printf("\n"); +} + +// MOTOR CONTROL HELPERS +/* + * Sends a byte-length message to the motor controller. + * @param message - the message to send + * @param description - the string description of the message, for debugging + */ +void MotorHandler::send(char message, char *description) { + alt_u32 write_space; + // Check for write space. + write_space = alt_up_rs232_get_available_space_in_write_FIFO(motor_dev); + if (write_space >= WRITE_FIFO_EMPTY) { + // If space, write. + int status = alt_up_rs232_write_data(motor_dev, message); + printf("MotorHandler [message: 0x%02x, description: %s", message, description); + // Log errors. + if (status == OK) { + printf("]\n"); + } else { + printf(", error: cannot write]\n"); + } + } else { + // If no space, wait and retry. + printf("MotorHandler [message: 0x%02x, description: %s, error: no write space; retrying]\n", message, description); + OSTimeDlyHMSM(0, 0, 0, 10); + send(message, description); + } +} + +void MotorHandler::reset(){ + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 0); + OSTimeDlyHMSM(0, 0, 0,200 ); + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 1); + OSTimeDlyHMSM(0, 0, 0, 200); +} diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/b7/80e834ca89b000131eb0f6c547a05c39 b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/b7/80e834ca89b000131eb0f6c547a05c39 new file mode 100644 index 00000000..37f9bffe --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/b7/80e834ca89b000131eb0f6c547a05c39 @@ -0,0 +1,134 @@ +/* + * MotorHandler.cpp + * + * Created on: 2014-03-03 + * Author: Amshu Gongal + */ + + +#include + +#include "altera_avalon_pio_regs.h" +#include "includes.h" +#include "system.h" + +#include "MotorHandler.h" + +#define WRITE_FIFO_EMPTY 0x80 +#define MOTOR_ENABLE 1 +#define MOTOR_RESET 0 + +// ALLOCATION +MotorHandler::MotorHandler() {} +MotorHandler::~MotorHandler() {} + + +// INITIALIZATION + +/* + * Initializes this handler. + * @return OK if the handler was initialized without error + */ +Status MotorHandler::init() { + // Enable the motor controller. + reset(); + // Open the serial device to send commands to the motor controller. + motor_dev = alt_up_rs232_open_dev(RS232_MOTOR_NAME); + //printf("%d", motor_dev); + if (motor_dev == NULL) { + return ERR_MOTOR_OPEN; + } else { + return OK; + } +} + +void MotorHandler::configure(){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_CHANGE_CONFIGURATION, "change configuration"); + send(0X01, "2 MOTOR CONFIG"); + printf("\n"); +} + +//Command Interpreter +/* + * Interprets the command from the network handler and sends move commands + * @param motor The motor to move eg. Left or Right + * @param motorDirection The direction of the given motor to move + * @param speed The speed the motor is to move + */ +void MotorHandler::motorCommand(string motor, string motorDirection, string speed){ + char motorID = interpretMotor(motor); + char Direction = interpretDirection(motorDirection, int(motorID)); + int Speed = strtol(speed.c_str()); + move(Direction, Speed, "Move Motor"); +} + +char MotorHandler::interpretMotor(string motor){ + if(motor.compare(MOTOR_LEFT) == 0){ + return MOTOR_LEFT_CHAR; + } + else{ + return MOTOR_RIGHT_CHAR; + } +} + +char MotorHandler::interpretDirection(string direction, int motor){ + if(direction.compare(MOTOR_FORWARD) == 0){ + return (char) (motor*2 + 1); + } + else{ + return (char) (motor*2); + } +} + +// MOTOR CONTROL + +/*Moves the given motor in specified direction by Motor Direction with specified + * Speed + * @param MotorDirection Motor and direction to move + * @param Speed the speed to move at + * @param string description of motor movement + */ + +void MotorHandler::move(char MotorDirection,char Speed,char * Description){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_DEVICE_TYPE, "device"); + send(MotorDirection, Description); + send(Speed, "speed"); + printf("\n"); +} + +// MOTOR CONTROL HELPERS +/* + * Sends a byte-length message to the motor controller. + * @param message - the message to send + * @param description - the string description of the message, for debugging + */ +void MotorHandler::send(char message, char *description) { + alt_u32 write_space; + // Check for write space. + write_space = alt_up_rs232_get_available_space_in_write_FIFO(motor_dev); + if (write_space >= WRITE_FIFO_EMPTY) { + // If space, write. + int status = alt_up_rs232_write_data(motor_dev, message); + printf("MotorHandler [message: 0x%02x, description: %s", message, description); + // Log errors. + if (status == OK) { + printf("]\n"); + } else { + printf(", error: cannot write]\n"); + } + } else { + // If no space, wait and retry. + printf("MotorHandler [message: 0x%02x, description: %s, error: no write space; retrying]\n", message, description); + OSTimeDlyHMSM(0, 0, 0, 10); + send(message, description); + } +} + +void MotorHandler::reset(){ + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 0); + OSTimeDlyHMSM(0, 0, 0,200 ); + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 1); + OSTimeDlyHMSM(0, 0, 0, 200); +} diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/b9/00b495f98ab000131eb0f6c547a05c39 b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/b9/00b495f98ab000131eb0f6c547a05c39 new file mode 100644 index 00000000..39c1d5eb --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/b9/00b495f98ab000131eb0f6c547a05c39 @@ -0,0 +1,136 @@ +/* + * MotorHandler.cpp + * + * Created on: 2014-03-03 + * Author: Amshu Gongal + */ + + +#include +#include + +#include "altera_avalon_pio_regs.h" +#include "includes.h" +#include "system.h" + +#include "MotorHandler.h" + +#define WRITE_FIFO_EMPTY 0x80 +#define MOTOR_ENABLE 1 +#define MOTOR_RESET 0 + +// ALLOCATION +MotorHandler::MotorHandler() {} +MotorHandler::~MotorHandler() {} + + +// INITIALIZATION + +/* + * Initializes this handler. + * @return OK if the handler was initialized without error + */ +Status MotorHandler::init() { + // Enable the motor controller. + reset(); + // Open the serial device to send commands to the motor controller. + motor_dev = alt_up_rs232_open_dev(RS232_MOTOR_NAME); + //printf("%d", motor_dev); + if (motor_dev == NULL) { + return ERR_MOTOR_OPEN; + } else { + return OK; + } +} + +void MotorHandler::configure(){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_CHANGE_CONFIGURATION, "change configuration"); + send(0X01, "2 MOTOR CONFIG"); + printf("\n"); +} + +//Command Interpreter +/* + * Interprets the command from the network handler and sends move commands + * @param motor The motor to move eg. Left or Right + * @param motorDirection The direction of the given motor to move + * @param speed The speed the motor is to move + */ +void MotorHandler::motorCommand(string motor, string motorDirection, string speed){ + char motorID = interpretMotor(motor); + char directionByte = interpretDirection(motorDirection, int(motorID)); + int speedByte = strtol(speed.c_str(), NULL, 0); + move(directionByte, speedByte, motor.append(motorDirection)); +} + + +char MotorHandler::interpretMotor(string motor){ + if(motor.compare(MOTOR_LEFT) == 0){ + return MOTOR_LEFT_CHAR; + } + else{ + return MOTOR_RIGHT_CHAR; + } +} + +char MotorHandler::interpretDirection(string direction, int motor){ + if(direction.compare(MOTOR_FORWARD) == 0){ + return (char) (motor*2 + 1); + } + else{ + return (char) (motor*2); + } +} + +// MOTOR CONTROL + +/*Moves the given motor in specified direction by Motor Direction with specified + * Speed + * @param MotorDirection Motor and direction to move + * @param Speed the speed to move at + * @param string description of motor movement + */ + +void MotorHandler::move(char motorDirection, char speed, string description){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_DEVICE_TYPE, "device"); + send(motorDirection, description); + send(speed, "speed"); + printf("\n"); +} + +// MOTOR CONTROL HELPERS +/* + * Sends a byte-length message to the motor controller. + * @param message - the message to send + * @param description - the string description of the message, for debugging + */ +void MotorHandler::send(char message, char *description) { + alt_u32 write_space; + // Check for write space. + write_space = alt_up_rs232_get_available_space_in_write_FIFO(motor_dev); + if (write_space >= WRITE_FIFO_EMPTY) { + // If space, write. + int status = alt_up_rs232_write_data(motor_dev, message); + printf("MotorHandler [message: 0x%02x, description: %s", message, description); + // Log errors. + if (status == OK) { + printf("]\n"); + } else { + printf(", error: cannot write]\n"); + } + } else { + // If no space, wait and retry. + printf("MotorHandler [message: 0x%02x, description: %s, error: no write space; retrying]\n", message, description); + OSTimeDlyHMSM(0, 0, 0, 10); + send(message, description); + } +} + +void MotorHandler::reset(){ + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 0); + OSTimeDlyHMSM(0, 0, 0,200 ); + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 1); + OSTimeDlyHMSM(0, 0, 0, 200); +} diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/bb/c06a659a8ab000131eb0f6c547a05c39 b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/bb/c06a659a8ab000131eb0f6c547a05c39 new file mode 100644 index 00000000..961579bb --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/bb/c06a659a8ab000131eb0f6c547a05c39 @@ -0,0 +1,136 @@ +/* + * MotorHandler.cpp + * + * Created on: 2014-03-03 + * Author: Amshu Gongal + */ + + +#include +#include + +#include "altera_avalon_pio_regs.h" +#include "includes.h" +#include "system.h" + +#include "MotorHandler.h" + +#define WRITE_FIFO_EMPTY 0x80 +#define MOTOR_ENABLE 1 +#define MOTOR_RESET 0 + +// ALLOCATION +MotorHandler::MotorHandler() {} +MotorHandler::~MotorHandler() {} + + +// INITIALIZATION + +/* + * Initializes this handler. + * @return OK if the handler was initialized without error + */ +Status MotorHandler::init() { + // Enable the motor controller. + reset(); + // Open the serial device to send commands to the motor controller. + motor_dev = alt_up_rs232_open_dev(RS232_MOTOR_NAME); + //printf("%d", motor_dev); + if (motor_dev == NULL) { + return ERR_MOTOR_OPEN; + } else { + return OK; + } +} + +void MotorHandler::configure(){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_CHANGE_CONFIGURATION, "change configuration"); + send(0X01, "2 MOTOR CONFIG"); + printf("\n"); +} + +//Command Interpreter +/* + * Interprets the command from the network handler and sends move commands + * @param motor The motor to move eg. Left or Right + * @param motorDirection The direction of the given motor to move + * @param speed The speed the motor is to move + */ +void MotorHandler::motorCommand(string motor, string motorDirection, string speed){ + char motorID = interpretMotor(motor); + char directionByte = interpretDirection(motorDirection, int(motorID)); + int speedByte = strtol(speed.c_str(), NULL, 0); + move(directionByte, speedByte, "Move Motor"); +} + + +char MotorHandler::interpretMotor(string motor){ + if(motor.compare(MOTOR_LEFT) == 0){ + return MOTOR_LEFT_CHAR; + } + else{ + return MOTOR_RIGHT_CHAR; + } +} + +char MotorHandler::interpretDirection(string direction, int motor){ + if(direction.compare(MOTOR_FORWARD) == 0){ + return (char) (motor*2 + 1); + } + else{ + return (char) (motor*2); + } +} + +// MOTOR CONTROL + +/*Moves the given motor in specified direction by Motor Direction with specified + * Speed + * @param MotorDirection Motor and direction to move + * @param Speed the speed to move at + * @param string description of motor movement + */ + +void MotorHandler::move(char motorDirection,char speed,char * Description){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_DEVICE_TYPE, "device"); + send(motorDirection, Description); + send(speed, "speed"); + printf("\n"); +} + +// MOTOR CONTROL HELPERS +/* + * Sends a byte-length message to the motor controller. + * @param message - the message to send + * @param description - the string description of the message, for debugging + */ +void MotorHandler::send(char message, char *description) { + alt_u32 write_space; + // Check for write space. + write_space = alt_up_rs232_get_available_space_in_write_FIFO(motor_dev); + if (write_space >= WRITE_FIFO_EMPTY) { + // If space, write. + int status = alt_up_rs232_write_data(motor_dev, message); + printf("MotorHandler [message: 0x%02x, description: %s", message, description); + // Log errors. + if (status == OK) { + printf("]\n"); + } else { + printf(", error: cannot write]\n"); + } + } else { + // If no space, wait and retry. + printf("MotorHandler [message: 0x%02x, description: %s, error: no write space; retrying]\n", message, description); + OSTimeDlyHMSM(0, 0, 0, 10); + send(message, description); + } +} + +void MotorHandler::reset(){ + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 0); + OSTimeDlyHMSM(0, 0, 0,200 ); + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 1); + OSTimeDlyHMSM(0, 0, 0, 200); +} diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/bb/d07b9920a5ab001311f2ce252b4696cb b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/bb/d07b9920a5ab001311f2ce252b4696cb new file mode 100644 index 00000000..1b1cc181 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/bb/d07b9920a5ab001311f2ce252b4696cb @@ -0,0 +1,146 @@ +/************************************************************************* + * ARCap + * Amshu Gongal, Kenan Kigunda + * February 18, 2014 + ************************************************************************** + * Description: * + * Prototype testing for infrared and mc. + **************************************************************************/ + +#include +#include "includes.h" +#include "altera_avalon_pio_regs.h" +#include "altera_avalon_uart_regs.h" +#include "sys/alt_irq.h" +#include "alt_types.h" +#include "altera_up_avalon_rs232.h" +#include "altera_up_avalon_rs232_regs.h" + +#include "MotorHandler.h" +#include "Status.h" + +/* Task stacks */ +#define TASK_STACKSIZE 2048 +OS_STK ir_task_stk[TASK_STACKSIZE]; +OS_STK mc_task_stk[TASK_STACKSIZE]; +/* Task priorities */ +#define IR_TASK_PRIORITY 2 +#define MC_TASK_PRIORITY 1 + + +#define SW_READ 1 +#define SW_WRITE 2 +#define WRITE_FIFO_EMPTY 0x80 +#define READ_FIFO_EMPTY 0x0 +OS_EVENT *SWQ; +OS_EVENT *RS232Q; +INT8U err; + + +/* Error status */ +#define OK 0 + +/* Message queues */ +#define WAIT_FOREVER 0 + +// ==== INFRARED ==== + +/* Infrared message queue */ +#define IR_MAX_MESSAGES 4 +int ir_messages[IR_MAX_MESSAGES]; +OS_EVENT *ir_queue; + +/* Infrared messages */ +// Together these avoid passing 0 to the queue (which is not allowed since queue messages cannot be null) +// and invert pushbutton input (since the pushbutton returns 0 when it is pushed down). +#define IR_QUEUE_SEND_BASE 1 // Use: IR_QUEUE_SEND_BASE + IORD +#define IR_QUEUE_RECEIVE_BASE 2 // Use: IR_QUEUE_RECEIVE_BASE - OSQPend + + +MotorHandler *motor= new MotorHandler(); + + +// ==== mc + +#define mc_GUARD_TIME 1 + +void mc_task(void *pdata) +{ + printf("mc task\n"); + printf("MotorHandler [init"); + if (motor->init() == OK) { + printf("]\n\n"); + motor->forward(); + } else { + printf( ", error]\n"); + } + while(1){ + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 1); + OSTimeDlyHMSM(0, 0, 2, 100); + } +} + + + +// ==== GENERAL + +void queue_init() { + ir_queue = OSQCreate((void**)&ir_messages, IR_MAX_MESSAGES); +} + +/* The main function creates the LCD task, registers the edge counter polling interrupt, + * and starts the OS. */ +int main(void) +{ + int status = OK; + // Initialize components. + queue_init(); + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 1); + // Create the mc task. + OSTaskCreateExt(mc_task, + NULL, + &mc_task_stk[TASK_STACKSIZE - 1], + MC_TASK_PRIORITY, + MC_TASK_PRIORITY, + mc_task_stk, + TASK_STACKSIZE, + NULL, + 0); + + if (status == OK) { + OSStart(); + } + + return 0; +} + +/****************************************************************************** + * * + * License Agreement * + * * + * Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * + * All rights reserved. * + * * + * Permission is hereby granted, free of charge, to any person obtaining a * + * copy of this software and associated documentation files (the "Software"), * + * to deal in the Software without restriction, including without limitation * + * the rights to use, copy, modify, merge, publish, distribute, sublicense, * + * and/or sell copies of the Software, and to permit persons to whom the * + * Software is furnished to do so, subject to the following conditions: * + * * + * The above copyright notice and this permission notice shall be included in * + * all copies or substantial portions of the Software. * + * * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * + * DEALINGS IN THE SOFTWARE. * + * * + * This agreement shall be governed in all respects by the laws of the State * + * of California and by the laws of the United States of America. * + * Altera does not recommend, suggest or require that this reference design * + * file be used in conjunction or combination with any other product. * + ******************************************************************************/ diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/c/30127d3ca5ab001311f2ce252b4696cb b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/c/30127d3ca5ab001311f2ce252b4696cb new file mode 100644 index 00000000..a4ca5f31 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/c/30127d3ca5ab001311f2ce252b4696cb @@ -0,0 +1,146 @@ +/************************************************************************* + * ARCap + * Amshu Gongal, Kenan Kigunda + * February 18, 2014 + ************************************************************************** + * Description: * + * Prototype testing for infrared and mc. + **************************************************************************/ + +#include +#include "includes.h" +#include "altera_avalon_pio_regs.h" +#include "altera_avalon_uart_regs.h" +#include "sys/alt_irq.h" +#include "alt_types.h" +#include "altera_up_avalon_rs232.h" +#include "altera_up_avalon_rs232_regs.h" + +#include "MotorHandler.h" +#include "Status.h" + +/* Task stacks */ +#define TASK_STACKSIZE 2048 +OS_STK ir_task_stk[TASK_STACKSIZE]; +OS_STK mc_task_stk[TASK_STACKSIZE]; +/* Task priorities */ +#define IR_TASK_PRIORITY 2 +#define MC_TASK_PRIORITY 1 + + +#define SW_READ 1 +#define SW_WRITE 2 +#define WRITE_FIFO_EMPTY 0x80 +#define READ_FIFO_EMPTY 0x0 +OS_EVENT *SWQ; +OS_EVENT *RS232Q; +INT8U err; + + +/* Error status */ +#define OK 0 + +/* Message queues */ +#define WAIT_FOREVER 0 + +// ==== INFRARED ==== + +/* Infrared message queue */ +#define IR_MAX_MESSAGES 4 +int ir_messages[IR_MAX_MESSAGES]; +OS_EVENT *ir_queue; + +/* Infrared messages */ +// Together these avoid passing 0 to the queue (which is not allowed since queue messages cannot be null) +// and invert pushbutton input (since the pushbutton returns 0 when it is pushed down). +#define IR_QUEUE_SEND_BASE 1 // Use: IR_QUEUE_SEND_BASE + IORD +#define IR_QUEUE_RECEIVE_BASE 2 // Use: IR_QUEUE_RECEIVE_BASE - OSQPend + + +MotorHandler *motor= new MotorHandler(); + + +// ==== mc + +#define mc_GUARD_TIME 1 + +void mc_task(void *pdata) +{ + printf("mc task\n"); + printf("MotorHandler [init"); + if (motor->init() == OK) { + printf("]\n\n"); + motor->forward(); + } else { + printf( ", error]\n"); + } + while(1){ + motor->reset(); + OSTimeDlyHMSM(0, 0, 2, 100); + } +} + + + +// ==== GENERAL + +void queue_init() { + ir_queue = OSQCreate((void**)&ir_messages, IR_MAX_MESSAGES); +} + +/* The main function creates the LCD task, registers the edge counter polling interrupt, + * and starts the OS. */ +int main(void) +{ + int status = OK; + // Initialize components. + queue_init(); + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 1); + // Create the mc task. + OSTaskCreateExt(mc_task, + NULL, + &mc_task_stk[TASK_STACKSIZE - 1], + MC_TASK_PRIORITY, + MC_TASK_PRIORITY, + mc_task_stk, + TASK_STACKSIZE, + NULL, + 0); + + if (status == OK) { + OSStart(); + } + + return 0; +} + +/****************************************************************************** + * * + * License Agreement * + * * + * Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * + * All rights reserved. * + * * + * Permission is hereby granted, free of charge, to any person obtaining a * + * copy of this software and associated documentation files (the "Software"), * + * to deal in the Software without restriction, including without limitation * + * the rights to use, copy, modify, merge, publish, distribute, sublicense, * + * and/or sell copies of the Software, and to permit persons to whom the * + * Software is furnished to do so, subject to the following conditions: * + * * + * The above copyright notice and this permission notice shall be included in * + * all copies or substantial portions of the Software. * + * * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * + * DEALINGS IN THE SOFTWARE. * + * * + * This agreement shall be governed in all respects by the laws of the State * + * of California and by the laws of the United States of America. * + * Altera does not recommend, suggest or require that this reference design * + * file be used in conjunction or combination with any other product. * + ******************************************************************************/ diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/c0/70a2a9c484b000131eb0f6c547a05c39 b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/c0/70a2a9c484b000131eb0f6c547a05c39 new file mode 100644 index 00000000..ce30a82f --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/c0/70a2a9c484b000131eb0f6c547a05c39 @@ -0,0 +1,63 @@ +/* + * MotorHandler.h + * + * Created on: 2014-03-03 + * Author: Amshu Gongal + */ + +#ifndef MOTORHANDLER_H_ +#define MOTORHANDLER_H_ + +#include "altera_up_avalon_rs232.h" +#include "altera_up_avalon_rs232_regs.h" +#include +using namespace std; +#include +#include "Status.h" + +// Motor messages are LSB first +#define MOTOR_START_BYTE 0x80 +#define MOTOR_DEVICE_TYPE 0x00 +#define MOTOR_LEFT_BACKWARD 0x04 // motor 1 backward +#define MOTOR_RIGHT_BACKWARD 0x06 // motor 2 backward +#define MOTOR_LEFT_FORWARD 0x05 // motor 1 forward +#define MOTOR_RIGHT_FORWARD 0x07 // motor 2 forward +#define MOTOR_CONST_SPEED 0x5F +#define MOTOR_STOP_SPEED 0x00 +#define MOTOR_CHANGE_CONFIGURATION 0X02 + +class MotorHandler { +public: + MotorHandler(); + virtual ~MotorHandler(); + + /* + * Initializes this handler. + * @return OK if the handler was initialized without error + */ + Status init(); + void reset(); + void configure(); + void motorCommand(string motor, string motorDirection, char); + +private: + /* The device used to send serial commands to the motor controller. */ + alt_up_rs232_dev *motor_dev; + + /* + * Moves in the given direction at constant speed. + * @param direction - the motor and direction to move in, e.g. MOTOR_MOTOR1_FORWARD + * @param speed speed of the motor + * @param description - the string description of the movement, for debugging + */ + void move(char direction, char speed, char *description); + + /* + * Sends a byte-length message to the motor controller. + * @param message - the message to send + * @param description - the string description of the message, for debugging + */ + void send(char message, char *description); +}; + +#endif /* MOTORHANDLER_H_ */ diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/c0/b04c73878bb000131eb0f6c547a05c39 b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/c0/b04c73878bb000131eb0f6c547a05c39 new file mode 100644 index 00000000..270fc7bd --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/c0/b04c73878bb000131eb0f6c547a05c39 @@ -0,0 +1,73 @@ +/* + * MotorHandler.h + * + * Created on: 2014-03-03 + * Author: Amshu Gongal + */ + +#ifndef MOTORHANDLER_H_ +#define MOTORHANDLER_H_ + +#include "altera_up_avalon_rs232.h" +#include "altera_up_avalon_rs232_regs.h" +#include +using namespace std; +#include +#include "Status.h" + +//Commands from network handler +#define MOTOR_LEFT "left" +#define MOTOR_RIGHT "right" +#define MOTOR_FORWARD "forward" +#define MOTOR_BACKWARD "backward" + + +// Motor messages are LSB first +#define MOTOR_START_BYTE 0x80 +#define MOTOR_DEVICE_TYPE 0x00 +#define MOTOR_LEFT_CHAR 0x02 // motor 1 backward +#define MOTOR_RIGHT_CHAR 0x03 // motor 2 backward +#define MOTOR_LEFT_FORWARD 0x05 // motor 1 forward +#define MOTOR_RIGHT_FORWARD 0x07 // motor 2 forward +#define MOTOR_CONST_SPEED 0x5F +#define MOTOR_STOP_SPEED 0x00 +#define MOTOR_CHANGE_CONFIGURATION 0X02 + +class MotorHandler { +public: + MotorHandler(); + virtual ~MotorHandler(); + + /* + * Initializes this handler. + * @return OK if the handler was initialized without error + */ + Status init(); + void reset(); + void configure(); + void motorCommand(string motor, string motorDirection, string speed); + +private: + /* The device used to send serial commands to the motor controller. */ + alt_up_rs232_dev *motor_dev; + + char interpretMotor(string motor); + char interpretDirection(string direction, int motor); + + /* + * Moves in the given direction at constant speed. + * @param direction - the motor and direction to move in, e.g. MOTOR_MOTOR1_FORWARD + * @param speed speed of the motor + * @param description - the string description of the movement, for debugging + */ + void move(char direction, char speed, string description); + + /* + * Sends a byte-length message to the motor controller. + * @param message - the message to send + * @param description - the string description of the message, for debugging + */ + void send(char message,string description); +}; + +#endif /* MOTORHANDLER_H_ */ diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/c3/30564cffb5ab00131274ac4b6fee418c b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/c3/30564cffb5ab00131274ac4b6fee418c new file mode 100644 index 00000000..6e88f939 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/c3/30564cffb5ab00131274ac4b6fee418c @@ -0,0 +1,153 @@ +/* + * MotorHandler.cpp + * + * Created on: 2014-03-03 + * Author: Amshu Gongal + */ + + +#include + +#include "altera_avalon_pio_regs.h" +#include "includes.h" +#include "system.h" + +#include "MotorHandler.h" + +#define WRITE_FIFO_EMPTY 0x80 +#define MOTOR_ENABLE 1 +#define MOTOR_RESET 0 + +// ALLOCATION +MotorHandler::MotorHandler() {} +MotorHandler::~MotorHandler() {} + +// INITIALIZATION + +/* + * Initializes this handler. + * @return OK if the handler was initialized without error + */ +Status MotorHandler::init() { + // Enable the motor controller. + reset(); + // Open the serial device to send commands to the motor controller. + motor_dev = alt_up_rs232_open_dev(RS232_MOTOR_NAME); + //printf("%d", motor_dev); + if (motor_dev == NULL) { + return ERR_MOTOR_OPEN; + } else { + return OK; + } +} + +void MotorHandler::configure(){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_CHANGE_CONFIGURATION, "change configuration"); + send(0X01, "2 MOTOR CONFIG"); + printf("\n"); +} +// TESTING + +void MotorHandler::test() { + send(MOTOR_START_BYTE, "test start"); +} + +// MOTOR CONTROL + +/* + * Move rover forward by activating both motors. + */ +void MotorHandler::forward() { + move(MOTOR_MOTOR1_FORWARD, "motor 1 forward"); + move(MOTOR_MOTOR2_FORWARD, "motor 2 forward"); +} + +/* + * Move rover backward by activating both motor backwards. + */ +void MotorHandler::backward() { + move(MOTOR_BOTH_BACKWARD, "both motors backward"); +// move(MOTOR_MOTOR2_BACKWARD, "motor 2 backward"); +} + +/* + * Turn rover left. + */ +void MotorHandler::left() { + move(MOTOR_MOTOR2_FORWARD, "motor 1 forward"); +} + +/* + * Turn rover right. + */ +void MotorHandler::right() { + move(MOTOR_MOTOR2_FORWARD, "motor 2 forward"); +} + +/* + * Stop the rover. + */ +void MotorHandler::stop() { + move(MOTOR_MOTOR1_FORWARD, MOTOR_STOP_SPEED, "motor 1 stop"); + move(MOTOR_MOTOR2_FORWARD, MOTOR_STOP_SPEED, "motor 2 stop"); +} + +// MOTOR CONTROL HELPERS + +/* + * Moves in the given direction at constant speed. + * @param direction - the motor and direction to move in, e.g. MOTOR_MOTOR1_FORWARD + * @param description - the string description of the movement, for debugging + */ +void MotorHandler::move(char direction, char *description) { + move(direction, MOTOR_CONST_SPEED, description); +} + +/* + * Moves in the given direction and speed. + * @param direction - the motor and direction to move in, e.g. MOTOR_MOTOR1_FORWARD + * @param speed - the speed to move at, i.e. MOTOR_CONST_SPEED or MOTOR_STOP_SPEED + * @param description - the string description of the movement, for debugging + */ +void MotorHandler::move(char direction, char speed, char *description) { + send(MOTOR_START_BYTE, "start"); + send(MOTOR_DEVICE_TYPE, "device"); + send(direction, description); + send(speed, "speed"); + printf("\n"); +} + +/* + * Sends a byte-length message to the motor controller. + * @param message - the message to send + * @param description - the string description of the message, for debugging + */ +void MotorHandler::send(char message, char *description) { + alt_u32 write_space; + // Check for write space. + write_space = alt_up_rs232_get_available_space_in_write_FIFO(motor_dev); + if (write_space >= WRITE_FIFO_EMPTY) { + // If space, write. + int status = alt_up_rs232_write_data(motor_dev, message); + printf("MotorHandler [message: 0x%02x, description: %s", message, description); + // Log errors. + if (status == OK) { + printf("]\n"); + } else { + printf(", error: cannot write]\n"); + } + } else { + // If no space, wait and retry. + printf("MotorHandler [message: 0x%02x, description: %s, error: no write space; retrying]\n", message, description); + OSTimeDlyHMSM(0, 0, 0, 10); + send(message, description); + } +} + +void MotorHandler::reset(){ + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 0); + OSTimeDlyHMSM(0, 0, 2,0 ); + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 1); + OSTimeDlyHMSM(0, 0, 2, 100); +} diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/c3/900852258cb000131eb0f6c547a05c39 b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/c3/900852258cb000131eb0f6c547a05c39 new file mode 100644 index 00000000..73ea65e7 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/c3/900852258cb000131eb0f6c547a05c39 @@ -0,0 +1,147 @@ +/************************************************************************* + * ARCap + * Amshu Gongal, Kenan Kigunda + * February 18, 2014 + ************************************************************************** + * Description: * + * Prototype testing for infrared and mc. + **************************************************************************/ + +#include +#include "includes.h" +#include "altera_avalon_pio_regs.h" +#include "altera_avalon_uart_regs.h" +#include "sys/alt_irq.h" +#include "alt_types.h" +#include "altera_up_avalon_rs232.h" +#include "altera_up_avalon_rs232_regs.h" + +#include "MotorHandler.h" +#include "Status.h" + +/* Task stacks */ +#define TASK_STACKSIZE 2048 +OS_STK ir_task_stk[TASK_STACKSIZE]; +OS_STK mc_task_stk[TASK_STACKSIZE]; +/* Task priorities */ +#define IR_TASK_PRIORITY 2 +#define MC_TASK_PRIORITY 1 + + +#define SW_READ 1 +#define SW_WRITE 2 +#define WRITE_FIFO_EMPTY 0x80 +#define READ_FIFO_EMPTY 0x0 +OS_EVENT *SWQ; +OS_EVENT *RS232Q; +INT8U err; + + +/* Error status */ +#define OK 0 + +/* Message queues */ +#define WAIT_FOREVER 0 + +// ==== INFRARED ==== + +/* Infrared message queue */ +#define IR_MAX_MESSAGES 4 +int ir_messages[IR_MAX_MESSAGES]; +OS_EVENT *ir_queue; + +/* Infrared messages */ +// Together these avoid passing 0 to the queue (which is not allowed since queue messages cannot be null) +// and invert pushbutton input (since the pushbutton returns 0 when it is pushed down). +#define IR_QUEUE_SEND_BASE 1 // Use: IR_QUEUE_SEND_BASE + IORD +#define IR_QUEUE_RECEIVE_BASE 2 // Use: IR_QUEUE_RECEIVE_BASE - OSQPend + + +MotorHandler *motor= new MotorHandler(); + + +// ==== mc + +#define mc_GUARD_TIME 1 + +void mc_task(void *pdata) +{ + printf("mc task\n"); + printf("MotorHandler [init"); + if (motor->init() == OK) { + printf("]\n\n"); + } else { + printf( ", error]\n"); + } + while(1){ + motor->motorCommand("left", "forward", "120"); + OSTimeDlyHMSM(0, 0, 5, 0); + motor->motorCommand("left", "forward", 0); + + + } +} + + + +// ==== GENERAL + +void queue_init() { + ir_queue = OSQCreate((void**)&ir_messages, IR_MAX_MESSAGES); +} + +/* The main function creates the LCD task, registers the edge counter polling interrupt, + * and starts the OS. */ +int main(void) +{ + int status = OK; + // Initialize components. + queue_init(); + // Create the mc task. + OSTaskCreateExt(mc_task, + NULL, + &mc_task_stk[TASK_STACKSIZE - 1], + MC_TASK_PRIORITY, + MC_TASK_PRIORITY, + mc_task_stk, + TASK_STACKSIZE, + NULL, + 0); + + if (status == OK) { + OSStart(); + } + + return 0; +} + +/****************************************************************************** + * * + * License Agreement * + * * + * Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * + * All rights reserved. * + * * + * Permission is hereby granted, free of charge, to any person obtaining a * + * copy of this software and associated documentation files (the "Software"), * + * to deal in the Software without restriction, including without limitation * + * the rights to use, copy, modify, merge, publish, distribute, sublicense, * + * and/or sell copies of the Software, and to permit persons to whom the * + * Software is furnished to do so, subject to the following conditions: * + * * + * The above copyright notice and this permission notice shall be included in * + * all copies or substantial portions of the Software. * + * * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * + * DEALINGS IN THE SOFTWARE. * + * * + * This agreement shall be governed in all respects by the laws of the State * + * of California and by the laws of the United States of America. * + * Altera does not recommend, suggest or require that this reference design * + * file be used in conjunction or combination with any other product. * + ******************************************************************************/ diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/c4/2008f7bf8ab000131eb0f6c547a05c39 b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/c4/2008f7bf8ab000131eb0f6c547a05c39 new file mode 100644 index 00000000..772ee589 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/c4/2008f7bf8ab000131eb0f6c547a05c39 @@ -0,0 +1,136 @@ +/* + * MotorHandler.cpp + * + * Created on: 2014-03-03 + * Author: Amshu Gongal + */ + + +#include +#include + +#include "altera_avalon_pio_regs.h" +#include "includes.h" +#include "system.h" + +#include "MotorHandler.h" + +#define WRITE_FIFO_EMPTY 0x80 +#define MOTOR_ENABLE 1 +#define MOTOR_RESET 0 + +// ALLOCATION +MotorHandler::MotorHandler() {} +MotorHandler::~MotorHandler() {} + + +// INITIALIZATION + +/* + * Initializes this handler. + * @return OK if the handler was initialized without error + */ +Status MotorHandler::init() { + // Enable the motor controller. + reset(); + // Open the serial device to send commands to the motor controller. + motor_dev = alt_up_rs232_open_dev(RS232_MOTOR_NAME); + //printf("%d", motor_dev); + if (motor_dev == NULL) { + return ERR_MOTOR_OPEN; + } else { + return OK; + } +} + +void MotorHandler::configure(){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_CHANGE_CONFIGURATION, "change configuration"); + send(0X01, "2 MOTOR CONFIG"); + printf("\n"); +} + +//Command Interpreter +/* + * Interprets the command from the network handler and sends move commands + * @param motor The motor to move eg. Left or Right + * @param motorDirection The direction of the given motor to move + * @param speed The speed the motor is to move + */ +void MotorHandler::motorCommand(string motor, string motorDirection, string speed){ + char motorID = interpretMotor(motor); + char directionByte = interpretDirection(motorDirection, int(motorID)); + int speedByte = strtol(speed.c_str(), NULL, 0); + move(directionByte, speedByte, "Move Motor"); +} + + +char MotorHandler::interpretMotor(string motor){ + if(motor.compare(MOTOR_LEFT) == 0){ + return MOTOR_LEFT_CHAR; + } + else{ + return MOTOR_RIGHT_CHAR; + } +} + +char MotorHandler::interpretDirection(string direction, int motor){ + if(direction.compare(MOTOR_FORWARD) == 0){ + return (char) (motor*2 + 1); + } + else{ + return (char) (motor*2); + } +} + +// MOTOR CONTROL + +/*Moves the given motor in specified direction by Motor Direction with specified + * Speed + * @param MotorDirection Motor and direction to move + * @param Speed the speed to move at + * @param string description of motor movement + */ + +void MotorHandler::move(char motorDirection, char speed, char *description){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_DEVICE_TYPE, "device"); + send(motorDirection, description); + send(speed, "speed"); + printf("\n"); +} + +// MOTOR CONTROL HELPERS +/* + * Sends a byte-length message to the motor controller. + * @param message - the message to send + * @param description - the string description of the message, for debugging + */ +void MotorHandler::send(char message, char *description) { + alt_u32 write_space; + // Check for write space. + write_space = alt_up_rs232_get_available_space_in_write_FIFO(motor_dev); + if (write_space >= WRITE_FIFO_EMPTY) { + // If space, write. + int status = alt_up_rs232_write_data(motor_dev, message); + printf("MotorHandler [message: 0x%02x, description: %s", message, description); + // Log errors. + if (status == OK) { + printf("]\n"); + } else { + printf(", error: cannot write]\n"); + } + } else { + // If no space, wait and retry. + printf("MotorHandler [message: 0x%02x, description: %s, error: no write space; retrying]\n", message, description); + OSTimeDlyHMSM(0, 0, 0, 10); + send(message, description); + } +} + +void MotorHandler::reset(){ + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 0); + OSTimeDlyHMSM(0, 0, 0,200 ); + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 1); + OSTimeDlyHMSM(0, 0, 0, 200); +} diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/c5/203f2dc487b000131eb0f6c547a05c39 b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/c5/203f2dc487b000131eb0f6c547a05c39 new file mode 100644 index 00000000..a3d1959a --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/c5/203f2dc487b000131eb0f6c547a05c39 @@ -0,0 +1,125 @@ +/* + * MotorHandler.cpp + * + * Created on: 2014-03-03 + * Author: Amshu Gongal + */ + + +#include + +#include "altera_avalon_pio_regs.h" +#include "includes.h" +#include "system.h" + +#include "MotorHandler.h" + +#define WRITE_FIFO_EMPTY 0x80 +#define MOTOR_ENABLE 1 +#define MOTOR_RESET 0 + +// ALLOCATION +MotorHandler::MotorHandler() {} +MotorHandler::~MotorHandler() {} + + +// INITIALIZATION + +/* + * Initializes this handler. + * @return OK if the handler was initialized without error + */ +Status MotorHandler::init() { + // Enable the motor controller. + reset(); + // Open the serial device to send commands to the motor controller. + motor_dev = alt_up_rs232_open_dev(RS232_MOTOR_NAME); + //printf("%d", motor_dev); + if (motor_dev == NULL) { + return ERR_MOTOR_OPEN; + } else { + return OK; + } +} + +void MotorHandler::configure(){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_CHANGE_CONFIGURATION, "change configuration"); + send(0X01, "2 MOTOR CONFIG"); + printf("\n"); +} + +//Command Interpreter +/* + * Interprets the command from the network handler and sends move commands + * @param motor The motor to move eg. Left or Right + * @param motorDirection The direction of the given motor to move + * @param speed The speed the motor is to move + */ +void MotorHandler::motorCommand(string motor, string motorDirection, string speed){ + char motorID = interpretMotor(motor); +} + +char MotorHandler::interpretMotor(string motor){ + if(motor.compare(MOTOR_LEFT) == 0){ + return MOTOR_LEFT_CHAR; + } + else + return MOTOR_RIGHT_CHAR; +} + +char MotorHandler::interpretDirection(string direction, int motor){ + +} + +// MOTOR CONTROL + +/*Moves the given motor in specified direction by Motor Direction with specified + * Speed + * @param MotorDirection Motor and direction to move + * @param Speed the speed to move at + * @param string description of motor movement + */ + +void MotorHandler::move(char MotorDirection,char Speed,char * Description){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_DEVICE_TYPE, "device"); + send(MotorDirection, Description); + send(Speed, "speed"); + printf("\n"); +} + +// MOTOR CONTROL HELPERS +/* + * Sends a byte-length message to the motor controller. + * @param message - the message to send + * @param description - the string description of the message, for debugging + */ +void MotorHandler::send(char message, char *description) { + alt_u32 write_space; + // Check for write space. + write_space = alt_up_rs232_get_available_space_in_write_FIFO(motor_dev); + if (write_space >= WRITE_FIFO_EMPTY) { + // If space, write. + int status = alt_up_rs232_write_data(motor_dev, message); + printf("MotorHandler [message: 0x%02x, description: %s", message, description); + // Log errors. + if (status == OK) { + printf("]\n"); + } else { + printf(", error: cannot write]\n"); + } + } else { + // If no space, wait and retry. + printf("MotorHandler [message: 0x%02x, description: %s, error: no write space; retrying]\n", message, description); + OSTimeDlyHMSM(0, 0, 0, 10); + send(message, description); + } +} + +void MotorHandler::reset(){ + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 0); + OSTimeDlyHMSM(0, 0, 0,200 ); + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 1); + OSTimeDlyHMSM(0, 0, 0, 200); +} diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/c7/d055eeff87b000131eb0f6c547a05c39 b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/c7/d055eeff87b000131eb0f6c547a05c39 new file mode 100644 index 00000000..598279b8 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/c7/d055eeff87b000131eb0f6c547a05c39 @@ -0,0 +1,132 @@ +/* + * MotorHandler.cpp + * + * Created on: 2014-03-03 + * Author: Amshu Gongal + */ + + +#include + +#include "altera_avalon_pio_regs.h" +#include "includes.h" +#include "system.h" + +#include "MotorHandler.h" + +#define WRITE_FIFO_EMPTY 0x80 +#define MOTOR_ENABLE 1 +#define MOTOR_RESET 0 + +// ALLOCATION +MotorHandler::MotorHandler() {} +MotorHandler::~MotorHandler() {} + + +// INITIALIZATION + +/* + * Initializes this handler. + * @return OK if the handler was initialized without error + */ +Status MotorHandler::init() { + // Enable the motor controller. + reset(); + // Open the serial device to send commands to the motor controller. + motor_dev = alt_up_rs232_open_dev(RS232_MOTOR_NAME); + //printf("%d", motor_dev); + if (motor_dev == NULL) { + return ERR_MOTOR_OPEN; + } else { + return OK; + } +} + +void MotorHandler::configure(){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_CHANGE_CONFIGURATION, "change configuration"); + send(0X01, "2 MOTOR CONFIG"); + printf("\n"); +} + +//Command Interpreter +/* + * Interprets the command from the network handler and sends move commands + * @param motor The motor to move eg. Left or Right + * @param motorDirection The direction of the given motor to move + * @param speed The speed the motor is to move + */ +void MotorHandler::motorCommand(string motor, string motorDirection, string speed){ + char motorID = interpretMotor(motor); + char Direction = interpretDirection(motorDirection, int(motorID)); +} + +char MotorHandler::interpretMotor(string motor){ + if(motor.compare(MOTOR_LEFT) == 0){ + return MOTOR_LEFT_CHAR; + } + else{ + return MOTOR_RIGHT_CHAR; + } +} + +char MotorHandler::interpretDirection(string direction, int motor){ + if(direction.compare(MOTOR_FORWARD) == 0){ + return (char) (motor*2 + 1) + } + else + + +} + +// MOTOR CONTROL + +/*Moves the given motor in specified direction by Motor Direction with specified + * Speed + * @param MotorDirection Motor and direction to move + * @param Speed the speed to move at + * @param string description of motor movement + */ + +void MotorHandler::move(char MotorDirection,char Speed,char * Description){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_DEVICE_TYPE, "device"); + send(MotorDirection, Description); + send(Speed, "speed"); + printf("\n"); +} + +// MOTOR CONTROL HELPERS +/* + * Sends a byte-length message to the motor controller. + * @param message - the message to send + * @param description - the string description of the message, for debugging + */ +void MotorHandler::send(char message, char *description) { + alt_u32 write_space; + // Check for write space. + write_space = alt_up_rs232_get_available_space_in_write_FIFO(motor_dev); + if (write_space >= WRITE_FIFO_EMPTY) { + // If space, write. + int status = alt_up_rs232_write_data(motor_dev, message); + printf("MotorHandler [message: 0x%02x, description: %s", message, description); + // Log errors. + if (status == OK) { + printf("]\n"); + } else { + printf(", error: cannot write]\n"); + } + } else { + // If no space, wait and retry. + printf("MotorHandler [message: 0x%02x, description: %s, error: no write space; retrying]\n", message, description); + OSTimeDlyHMSM(0, 0, 0, 10); + send(message, description); + } +} + +void MotorHandler::reset(){ + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 0); + OSTimeDlyHMSM(0, 0, 0,200 ); + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 1); + OSTimeDlyHMSM(0, 0, 0, 200); +} diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/c9/c04256a48aab001311dbfe770f133bca b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/c9/c04256a48aab001311dbfe770f133bca new file mode 100644 index 00000000..bd12fc02 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/c9/c04256a48aab001311dbfe770f133bca @@ -0,0 +1,143 @@ +/************************************************************************* + * ARCap + * Amshu Gongal, Kenan Kigunda + * February 18, 2014 + ************************************************************************** + * Description: * + * Prototype testing for infrared and mc. + **************************************************************************/ + +#include +#include "includes.h" +#include "altera_avalon_pio_regs.h" +#include "altera_avalon_uart_regs.h" +#include "sys/alt_irq.h" +#include "alt_types.h" +#include "altera_up_avalon_rs232.h" +#include "altera_up_avalon_rs232_regs.h" + +#include "MotorHandler.h" +#include "Status.h" + +/* Task stacks */ +#define TASK_STACKSIZE 2048 +OS_STK ir_task_stk[TASK_STACKSIZE]; +OS_STK mc_task_stk[TASK_STACKSIZE]; +/* Task priorities */ +#define IR_TASK_PRIORITY 2 +#define MC_TASK_PRIORITY 1 + + +#define SW_READ 1 +#define SW_WRITE 2 +#define WRITE_FIFO_EMPTY 0x80 +#define READ_FIFO_EMPTY 0x0 +OS_EVENT *SWQ; +OS_EVENT *RS232Q; +INT8U err; + + +/* Error status */ +#define OK 0 + +/* Message queues */ +#define WAIT_FOREVER 0 + +// ==== INFRARED ==== + +/* Infrared message queue */ +#define IR_MAX_MESSAGES 4 +int ir_messages[IR_MAX_MESSAGES]; +OS_EVENT *ir_queue; + +/* Infrared messages */ +// Together these avoid passing 0 to the queue (which is not allowed since queue messages cannot be null) +// and invert pushbutton input (since the pushbutton returns 0 when it is pushed down). +#define IR_QUEUE_SEND_BASE 1 // Use: IR_QUEUE_SEND_BASE + IORD +#define IR_QUEUE_RECEIVE_BASE 2 // Use: IR_QUEUE_RECEIVE_BASE - OSQPend + + +MotorHandler *motor= new MotorHandler(); + + +// ==== mc + +#define mc_GUARD_TIME 1 + +void mc_task(void *pdata) +{ + printf("mc task\n"); + printf("MotorHandler [init"); + if (motor->init() == OK) { + printf("]\n\n"); + motor->configure(); + } else { + printf( ", error]\n"); + } + motor->forward(); +} + + + +// ==== GENERAL + +void queue_init() { + ir_queue = OSQCreate((void**)&ir_messages, IR_MAX_MESSAGES); +} + +/* The main function creates the LCD task, registers the edge counter polling interrupt, + * and starts the OS. */ +int main(void) +{ + int status = OK; + // Initialize components. + queue_init(); + motor->reset(); + // Create the mc task. + OSTaskCreateExt(mc_task, + NULL, + &mc_task_stk[TASK_STACKSIZE - 1], + MC_TASK_PRIORITY, + MC_TASK_PRIORITY, + mc_task_stk, + TASK_STACKSIZE, + NULL, + 0); + + if (status == OK) { + OSStart(); + } + + return 0; +} + +/****************************************************************************** + * * + * License Agreement * + * * + * Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * + * All rights reserved. * + * * + * Permission is hereby granted, free of charge, to any person obtaining a * + * copy of this software and associated documentation files (the "Software"), * + * to deal in the Software without restriction, including without limitation * + * the rights to use, copy, modify, merge, publish, distribute, sublicense, * + * and/or sell copies of the Software, and to permit persons to whom the * + * Software is furnished to do so, subject to the following conditions: * + * * + * The above copyright notice and this permission notice shall be included in * + * all copies or substantial portions of the Software. * + * * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * + * DEALINGS IN THE SOFTWARE. * + * * + * This agreement shall be governed in all respects by the laws of the State * + * of California and by the laws of the United States of America. * + * Altera does not recommend, suggest or require that this reference design * + * file be used in conjunction or combination with any other product. * + ******************************************************************************/ diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/c9/c05bffb98fab001311dbfe770f133bca b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/c9/c05bffb98fab001311dbfe770f133bca new file mode 100644 index 00000000..03b7d997 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/c9/c05bffb98fab001311dbfe770f133bca @@ -0,0 +1,149 @@ +/************************************************************************* + * ARCap + * Amshu Gongal, Kenan Kigunda + * February 18, 2014 + ************************************************************************** + * Description: * + * Prototype testing for infrared and mc. + **************************************************************************/ + +#include +#include "includes.h" +#include "altera_avalon_pio_regs.h" +#include "altera_avalon_uart_regs.h" +#include "sys/alt_irq.h" +#include "alt_types.h" +#include "altera_up_avalon_rs232.h" +#include "altera_up_avalon_rs232_regs.h" + +#include "MotorHandler.h" +#include "Status.h" + +/* Task stacks */ +#define TASK_STACKSIZE 2048 +OS_STK ir_task_stk[TASK_STACKSIZE]; +OS_STK mc_task_stk[TASK_STACKSIZE]; +/* Task priorities */ +#define IR_TASK_PRIORITY 2 +#define MC_TASK_PRIORITY 1 + + +#define SW_READ 1 +#define SW_WRITE 2 +#define WRITE_FIFO_EMPTY 0x80 +#define READ_FIFO_EMPTY 0x0 +OS_EVENT *SWQ; +OS_EVENT *RS232Q; +INT8U err; + + +/* Error status */ +#define OK 0 + +/* Message queues */ +#define WAIT_FOREVER 0 + +// ==== INFRARED ==== + +/* Infrared message queue */ +#define IR_MAX_MESSAGES 4 +int ir_messages[IR_MAX_MESSAGES]; +OS_EVENT *ir_queue; + +/* Infrared messages */ +// Together these avoid passing 0 to the queue (which is not allowed since queue messages cannot be null) +// and invert pushbutton input (since the pushbutton returns 0 when it is pushed down). +#define IR_QUEUE_SEND_BASE 1 // Use: IR_QUEUE_SEND_BASE + IORD +#define IR_QUEUE_RECEIVE_BASE 2 // Use: IR_QUEUE_RECEIVE_BASE - OSQPend + + +MotorHandler *motor= new MotorHandler(); + + +// ==== mc + +#define mc_GUARD_TIME 1 + +void mc_task(void *pdata) +{ + printf("mc task\n"); + printf("MotorHandler [init"); + if (motor->init() == OK) { + printf("]\n\n"); + motor->forward(); + } else { + printf( ", error]\n"); + } + while(1){ + motor->forward(); + OSTimeDlyHMSM(0, 0, 0, 100); + } +} + + + +// ==== GENERAL + +void queue_init() { + ir_queue = OSQCreate((void**)&ir_messages, IR_MAX_MESSAGES); +} + +/* The main function creates the LCD task, registers the edge counter polling interrupt, + * and starts the OS. */ +int main(void) +{ + int status = OK; + // Initialize components. + queue_init(); + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 0); + OSTimeDlyHMSM(0,0,0,100); + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 1); + OSTimeDlyHMSM(0,0,0,100); + // Create the mc task. + OSTaskCreateExt(mc_task, + NULL, + &mc_task_stk[TASK_STACKSIZE - 1], + MC_TASK_PRIORITY, + MC_TASK_PRIORITY, + mc_task_stk, + TASK_STACKSIZE, + NULL, + 0); + + if (status == OK) { + OSStart(); + } + + return 0; +} + +/****************************************************************************** + * * + * License Agreement * + * * + * Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * + * All rights reserved. * + * * + * Permission is hereby granted, free of charge, to any person obtaining a * + * copy of this software and associated documentation files (the "Software"), * + * to deal in the Software without restriction, including without limitation * + * the rights to use, copy, modify, merge, publish, distribute, sublicense, * + * and/or sell copies of the Software, and to permit persons to whom the * + * Software is furnished to do so, subject to the following conditions: * + * * + * The above copyright notice and this permission notice shall be included in * + * all copies or substantial portions of the Software. * + * * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * + * DEALINGS IN THE SOFTWARE. * + * * + * This agreement shall be governed in all respects by the laws of the State * + * of California and by the laws of the United States of America. * + * Altera does not recommend, suggest or require that this reference design * + * file be used in conjunction or combination with any other product. * + ******************************************************************************/ diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/ce/20b52902cdab001312eeeea4d67ccb1b b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/ce/20b52902cdab001312eeeea4d67ccb1b new file mode 100644 index 00000000..c63be517 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/ce/20b52902cdab001312eeeea4d67ccb1b @@ -0,0 +1,145 @@ +/************************************************************************* + * ARCap + * Amshu Gongal, Kenan Kigunda + * February 18, 2014 + ************************************************************************** + * Description: * + * Prototype testing for infrared and mc. + **************************************************************************/ + +#include +#include "includes.h" +#include "altera_avalon_pio_regs.h" +#include "altera_avalon_uart_regs.h" +#include "sys/alt_irq.h" +#include "alt_types.h" +#include "altera_up_avalon_rs232.h" +#include "altera_up_avalon_rs232_regs.h" + +#include "MotorHandler.h" +#include "Status.h" + +/* Task stacks */ +#define TASK_STACKSIZE 2048 +OS_STK ir_task_stk[TASK_STACKSIZE]; +OS_STK mc_task_stk[TASK_STACKSIZE]; +/* Task priorities */ +#define IR_TASK_PRIORITY 2 +#define MC_TASK_PRIORITY 1 + + +#define SW_READ 1 +#define SW_WRITE 2 +#define WRITE_FIFO_EMPTY 0x80 +#define READ_FIFO_EMPTY 0x0 +OS_EVENT *SWQ; +OS_EVENT *RS232Q; +INT8U err; + + +/* Error status */ +#define OK 0 + +/* Message queues */ +#define WAIT_FOREVER 0 + +// ==== INFRARED ==== + +/* Infrared message queue */ +#define IR_MAX_MESSAGES 4 +int ir_messages[IR_MAX_MESSAGES]; +OS_EVENT *ir_queue; + +/* Infrared messages */ +// Together these avoid passing 0 to the queue (which is not allowed since queue messages cannot be null) +// and invert pushbutton input (since the pushbutton returns 0 when it is pushed down). +#define IR_QUEUE_SEND_BASE 1 // Use: IR_QUEUE_SEND_BASE + IORD +#define IR_QUEUE_RECEIVE_BASE 2 // Use: IR_QUEUE_RECEIVE_BASE - OSQPend + + +MotorHandler *motor= new MotorHandler(); + + +// ==== mc + +#define mc_GUARD_TIME 1 + +void mc_task(void *pdata) +{ + printf("mc task\n"); + printf("MotorHandler [init"); + if (motor->init() == OK) { + printf("]\n\n"); + motor->forward(); + } else { + printf( ", error]\n"); + } + while(1){ + motor->forward(); + + } +} + + + +// ==== GENERAL + +void queue_init() { + ir_queue = OSQCreate((void**)&ir_messages, IR_MAX_MESSAGES); +} + +/* The main function creates the LCD task, registers the edge counter polling interrupt, + * and starts the OS. */ +int main(void) +{ + int status = OK; + // Initialize components. + queue_init(); + // Create the mc task. + OSTaskCreateExt(mc_task, + NULL, + &mc_task_stk[TASK_STACKSIZE - 1], + MC_TASK_PRIORITY, + MC_TASK_PRIORITY, + mc_task_stk, + TASK_STACKSIZE, + NULL, + 0); + + if (status == OK) { + OSStart(); + } + + return 0; +} + +/****************************************************************************** + * * + * License Agreement * + * * + * Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * + * All rights reserved. * + * * + * Permission is hereby granted, free of charge, to any person obtaining a * + * copy of this software and associated documentation files (the "Software"), * + * to deal in the Software without restriction, including without limitation * + * the rights to use, copy, modify, merge, publish, distribute, sublicense, * + * and/or sell copies of the Software, and to permit persons to whom the * + * Software is furnished to do so, subject to the following conditions: * + * * + * The above copyright notice and this permission notice shall be included in * + * all copies or substantial portions of the Software. * + * * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * + * DEALINGS IN THE SOFTWARE. * + * * + * This agreement shall be governed in all respects by the laws of the State * + * of California and by the laws of the United States of America. * + * Altera does not recommend, suggest or require that this reference design * + * file be used in conjunction or combination with any other product. * + ******************************************************************************/ diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/ce/60ad733680b000131eb0f6c547a05c39 b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/ce/60ad733680b000131eb0f6c547a05c39 new file mode 100644 index 00000000..f8870e20 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/ce/60ad733680b000131eb0f6c547a05c39 @@ -0,0 +1,141 @@ +/* + * MotorHandler.cpp + * + * Created on: 2014-03-03 + * Author: Amshu Gongal + */ + + +#include + +#include "altera_avalon_pio_regs.h" +#include "includes.h" +#include "system.h" + +#include "MotorHandler.h" + +#define WRITE_FIFO_EMPTY 0x80 +#define MOTOR_ENABLE 1 +#define MOTOR_RESET 0 + +// ALLOCATION +MotorHandler::MotorHandler() {} +MotorHandler::~MotorHandler() {} + + + + +// INITIALIZATION + +/* + * Initializes this handler. + * @return OK if the handler was initialized without error + */ +Status MotorHandler::init() { + // Enable the motor controller. + reset(); + // Open the serial device to send commands to the motor controller. + motor_dev = alt_up_rs232_open_dev(RS232_MOTOR_NAME); + //printf("%d", motor_dev); + if (motor_dev == NULL) { + return ERR_MOTOR_OPEN; + } else { + return OK; + } +} + +void MotorHandler::configure(){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_CHANGE_CONFIGURATION, "change configuration"); + send(0X01, "2 MOTOR CONFIG"); + printf("\n"); +} +// TESTING + +void MotorHandler::test() { + send(MOTOR_START_BYTE, "test start"); +} + +// MOTOR CONTROL + +/* + * Move rover forward by activating both motors. + */ +void MotorHandler::forward() { + move(MOTOR_BOTH_FORWARD, "motor both forward"); + //move(MOTOR_MOTOR2_FORWARD, "motor 2 forward"); +} + +/* + * Move rover backward by activating both motor backwards. + */ +void MotorHandler::backward() { + move(MOTOR_BOTH_BACKWARD, "motor both backward"); + // move(MOTOR_MOTOR2_BACKWARD, "motor 2 backward"); +} + +/* + * Turn rover left. + */ +void MotorHandler::left() { + move(MOTOR_MOTOR1_FORWARD, "motor 1 forward"); +} + +/* + * Turn rover right. + */ +void MotorHandler::right() { + move(MOTOR_MOTOR2_FORWARD, "motor 2 forward"); +} + +/* + * Stop the rover. + */ +void MotorHandler::stop() { + move(MOTOR_MOTOR1_FORWARD, MOTOR_STOP_SPEED, "motor 1 stop"); + move(MOTOR_MOTOR2_FORWARD, MOTOR_STOP_SPEED, "motor 2 stop"); +} + +// MOTOR CONTROL HELPERS + + +void MotorHandler::move(char MotorDirection,char Speed,char * Description){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_DEVICE_TYPE, "device"); + send(MotorDirection, Description); + send(Speed, "speed"); + printf("\n"); +} +/* + * Sends a byte-length message to the motor controller. + * @param message - the message to send + * @param description - the string description of the message, for debugging + */ +void MotorHandler::send(char message, char *description) { + alt_u32 write_space; + // Check for write space. + write_space = alt_up_rs232_get_available_space_in_write_FIFO(motor_dev); + if (write_space >= WRITE_FIFO_EMPTY) { + // If space, write. + int status = alt_up_rs232_write_data(motor_dev, message); + printf("MotorHandler [message: 0x%02x, description: %s", message, description); + // Log errors. + if (status == OK) { + printf("]\n"); + } else { + printf(", error: cannot write]\n"); + } + } else { + // If no space, wait and retry. + printf("MotorHandler [message: 0x%02x, description: %s, error: no write space; retrying]\n", message, description); + OSTimeDlyHMSM(0, 0, 0, 10); + send(message, description); + } +} + +void MotorHandler::reset(){ + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 0); + OSTimeDlyHMSM(0, 0, 0,200 ); + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 1); + OSTimeDlyHMSM(0, 0, 0, 200); +} diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/d1/b0fae17387b000131eb0f6c547a05c39 b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/d1/b0fae17387b000131eb0f6c547a05c39 new file mode 100644 index 00000000..4b8fdaff --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/d1/b0fae17387b000131eb0f6c547a05c39 @@ -0,0 +1,123 @@ +/* + * MotorHandler.cpp + * + * Created on: 2014-03-03 + * Author: Amshu Gongal + */ + + +#include + +#include "altera_avalon_pio_regs.h" +#include "includes.h" +#include "system.h" + +#include "MotorHandler.h" + +#define WRITE_FIFO_EMPTY 0x80 +#define MOTOR_ENABLE 1 +#define MOTOR_RESET 0 + +// ALLOCATION +MotorHandler::MotorHandler() {} +MotorHandler::~MotorHandler() {} + + +// INITIALIZATION + +/* + * Initializes this handler. + * @return OK if the handler was initialized without error + */ +Status MotorHandler::init() { + // Enable the motor controller. + reset(); + // Open the serial device to send commands to the motor controller. + motor_dev = alt_up_rs232_open_dev(RS232_MOTOR_NAME); + //printf("%d", motor_dev); + if (motor_dev == NULL) { + return ERR_MOTOR_OPEN; + } else { + return OK; + } +} + +void MotorHandler::configure(){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_CHANGE_CONFIGURATION, "change configuration"); + send(0X01, "2 MOTOR CONFIG"); + printf("\n"); +} + +//Command Interpreter +/* + * Interprets the command from the network handler and sends move commands + * @param motor The motor to move eg. Left or Right + * @param motorDirection The direction of the given motor to move + * @param speed The speed the motor is to move + */ +void MotorHandler::motorCommand(string motor, string motorDirection, string speed){ + char motorC = interpretMotor(motor); +} + +char MotorHandler::interpretMotor(string motor){ + if(motor.compare(MOTOR_LEFT) == 0){ + return MOTOR_lEFT_CHAR; + } +} + +char MotorHandler::interpretDirection(string direction, int motor){ + +} + +// MOTOR CONTROL + +/*Moves the given motor in specified direction by Motor Direction with specified + * Speed + * @param MotorDirection Motor and direction to move + * @param Speed the speed to move at + * @param string description of motor movement + */ + +void MotorHandler::move(char MotorDirection,char Speed,char * Description){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_DEVICE_TYPE, "device"); + send(MotorDirection, Description); + send(Speed, "speed"); + printf("\n"); +} + +// MOTOR CONTROL HELPERS +/* + * Sends a byte-length message to the motor controller. + * @param message - the message to send + * @param description - the string description of the message, for debugging + */ +void MotorHandler::send(char message, char *description) { + alt_u32 write_space; + // Check for write space. + write_space = alt_up_rs232_get_available_space_in_write_FIFO(motor_dev); + if (write_space >= WRITE_FIFO_EMPTY) { + // If space, write. + int status = alt_up_rs232_write_data(motor_dev, message); + printf("MotorHandler [message: 0x%02x, description: %s", message, description); + // Log errors. + if (status == OK) { + printf("]\n"); + } else { + printf(", error: cannot write]\n"); + } + } else { + // If no space, wait and retry. + printf("MotorHandler [message: 0x%02x, description: %s, error: no write space; retrying]\n", message, description); + OSTimeDlyHMSM(0, 0, 0, 10); + send(message, description); + } +} + +void MotorHandler::reset(){ + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 0); + OSTimeDlyHMSM(0, 0, 0,200 ); + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 1); + OSTimeDlyHMSM(0, 0, 0, 200); +} diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/d3/6098c7748ab000131eb0f6c547a05c39 b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/d3/6098c7748ab000131eb0f6c547a05c39 new file mode 100644 index 00000000..16c8ec9a --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/d3/6098c7748ab000131eb0f6c547a05c39 @@ -0,0 +1,136 @@ +/* + * MotorHandler.cpp + * + * Created on: 2014-03-03 + * Author: Amshu Gongal + */ + + +#include +#include + +#include "altera_avalon_pio_regs.h" +#include "includes.h" +#include "system.h" + +#include "MotorHandler.h" + +#define WRITE_FIFO_EMPTY 0x80 +#define MOTOR_ENABLE 1 +#define MOTOR_RESET 0 + +// ALLOCATION +MotorHandler::MotorHandler() {} +MotorHandler::~MotorHandler() {} + + +// INITIALIZATION + +/* + * Initializes this handler. + * @return OK if the handler was initialized without error + */ +Status MotorHandler::init() { + // Enable the motor controller. + reset(); + // Open the serial device to send commands to the motor controller. + motor_dev = alt_up_rs232_open_dev(RS232_MOTOR_NAME); + //printf("%d", motor_dev); + if (motor_dev == NULL) { + return ERR_MOTOR_OPEN; + } else { + return OK; + } +} + +void MotorHandler::configure(){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_CHANGE_CONFIGURATION, "change configuration"); + send(0X01, "2 MOTOR CONFIG"); + printf("\n"); +} + +//Command Interpreter +/* + * Interprets the command from the network handler and sends move commands + * @param motor The motor to move eg. Left or Right + * @param motorDirection The direction of the given motor to move + * @param speed The speed the motor is to move + */ +void MotorHandler::motorCommand(string motor, string motorDirection, string speed){ + char motorID = interpretMotor(motor); + char directionByte = interpretDirection(motorDirection, int(motorID)); + int speedByte = strtol(speed.c_str(), NULL, 0); + move(directionByte, speedByte, "Move Motor"); +} + + +char MotorHandler::interpretMotor(string motor){ + if(motor.compare(MOTOR_LEFT) == 0){ + return MOTOR_LEFT_CHAR; + } + else{ + return MOTOR_RIGHT_CHAR; + } +} + +char MotorHandler::interpretDirection(string direction, int motor){ + if(direction.compare(MOTOR_FORWARD) == 0){ + return (char) (motor*2 + 1); + } + else{ + return (char) (motor*2); + } +} + +// MOTOR CONTROL + +/*Moves the given motor in specified direction by Motor Direction with specified + * Speed + * @param MotorDirection Motor and direction to move + * @param Speed the speed to move at + * @param string description of motor movement + */ + +void MotorHandler::move(char MotorDirection,char Speed,char * Description){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_DEVICE_TYPE, "device"); + send(MotorDirection, Description); + send(Speed, "speed"); + printf("\n"); +} + +// MOTOR CONTROL HELPERS +/* + * Sends a byte-length message to the motor controller. + * @param message - the message to send + * @param description - the string description of the message, for debugging + */ +void MotorHandler::send(char message, char *description) { + alt_u32 write_space; + // Check for write space. + write_space = alt_up_rs232_get_available_space_in_write_FIFO(motor_dev); + if (write_space >= WRITE_FIFO_EMPTY) { + // If space, write. + int status = alt_up_rs232_write_data(motor_dev, message); + printf("MotorHandler [message: 0x%02x, description: %s", message, description); + // Log errors. + if (status == OK) { + printf("]\n"); + } else { + printf(", error: cannot write]\n"); + } + } else { + // If no space, wait and retry. + printf("MotorHandler [message: 0x%02x, description: %s, error: no write space; retrying]\n", message, description); + OSTimeDlyHMSM(0, 0, 0, 10); + send(message, description); + } +} + +void MotorHandler::reset(){ + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 0); + OSTimeDlyHMSM(0, 0, 0,200 ); + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 1); + OSTimeDlyHMSM(0, 0, 0, 200); +} diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/d3/d06ecd3087b000131eb0f6c547a05c39 b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/d3/d06ecd3087b000131eb0f6c547a05c39 new file mode 100644 index 00000000..2d5e43f6 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/d3/d06ecd3087b000131eb0f6c547a05c39 @@ -0,0 +1,121 @@ +/* + * MotorHandler.cpp + * + * Created on: 2014-03-03 + * Author: Amshu Gongal + */ + + +#include + +#include "altera_avalon_pio_regs.h" +#include "includes.h" +#include "system.h" + +#include "MotorHandler.h" + +#define WRITE_FIFO_EMPTY 0x80 +#define MOTOR_ENABLE 1 +#define MOTOR_RESET 0 + +// ALLOCATION +MotorHandler::MotorHandler() {} +MotorHandler::~MotorHandler() {} + + +// INITIALIZATION + +/* + * Initializes this handler. + * @return OK if the handler was initialized without error + */ +Status MotorHandler::init() { + // Enable the motor controller. + reset(); + // Open the serial device to send commands to the motor controller. + motor_dev = alt_up_rs232_open_dev(RS232_MOTOR_NAME); + //printf("%d", motor_dev); + if (motor_dev == NULL) { + return ERR_MOTOR_OPEN; + } else { + return OK; + } +} + +void MotorHandler::configure(){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_CHANGE_CONFIGURATION, "change configuration"); + send(0X01, "2 MOTOR CONFIG"); + printf("\n"); +} + +//Command Interpreter +/* + * Interprets the command from the network handler and sends move commands + * @param motor The motor to move eg. Left or Right + * @param motorDirection The direction of the given motor to move + * @param speed The speed the motor is to move + */ +void MotorHandler::motorCommand(string motor, string motorDirection, string speed){ + char motor = interpretMotor(motor); +} + +char MotorHandler::interpretMotor(string motor){ + +} + +char MotorHandler::interpretDirection(string direction, int motor){ + +} + +// MOTOR CONTROL + +/*Moves the given motor in specified direction by Motor Direction with specified + * Speed + * @param MotorDirection Motor and direction to move + * @param Speed the speed to move at + * @param string description of motor movement + */ + +void MotorHandler::move(char MotorDirection,char Speed,char * Description){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_DEVICE_TYPE, "device"); + send(MotorDirection, Description); + send(Speed, "speed"); + printf("\n"); +} + +// MOTOR CONTROL HELPERS +/* + * Sends a byte-length message to the motor controller. + * @param message - the message to send + * @param description - the string description of the message, for debugging + */ +void MotorHandler::send(char message, char *description) { + alt_u32 write_space; + // Check for write space. + write_space = alt_up_rs232_get_available_space_in_write_FIFO(motor_dev); + if (write_space >= WRITE_FIFO_EMPTY) { + // If space, write. + int status = alt_up_rs232_write_data(motor_dev, message); + printf("MotorHandler [message: 0x%02x, description: %s", message, description); + // Log errors. + if (status == OK) { + printf("]\n"); + } else { + printf(", error: cannot write]\n"); + } + } else { + // If no space, wait and retry. + printf("MotorHandler [message: 0x%02x, description: %s, error: no write space; retrying]\n", message, description); + OSTimeDlyHMSM(0, 0, 0, 10); + send(message, description); + } +} + +void MotorHandler::reset(){ + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 0); + OSTimeDlyHMSM(0, 0, 0,200 ); + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 1); + OSTimeDlyHMSM(0, 0, 0, 200); +} diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/d4/20f0fd8ca6ab001311f2ce252b4696cb b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/d4/20f0fd8ca6ab001311f2ce252b4696cb new file mode 100644 index 00000000..ef421c9a --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/d4/20f0fd8ca6ab001311f2ce252b4696cb @@ -0,0 +1,144 @@ +/************************************************************************* + * ARCap + * Amshu Gongal, Kenan Kigunda + * February 18, 2014 + ************************************************************************** + * Description: * + * Prototype testing for infrared and mc. + **************************************************************************/ + +#include +#include "includes.h" +#include "altera_avalon_pio_regs.h" +#include "altera_avalon_uart_regs.h" +#include "sys/alt_irq.h" +#include "alt_types.h" +#include "altera_up_avalon_rs232.h" +#include "altera_up_avalon_rs232_regs.h" + +#include "MotorHandler.h" +#include "Status.h" + +/* Task stacks */ +#define TASK_STACKSIZE 2048 +OS_STK ir_task_stk[TASK_STACKSIZE]; +OS_STK mc_task_stk[TASK_STACKSIZE]; +/* Task priorities */ +#define IR_TASK_PRIORITY 2 +#define MC_TASK_PRIORITY 1 + + +#define SW_READ 1 +#define SW_WRITE 2 +#define WRITE_FIFO_EMPTY 0x80 +#define READ_FIFO_EMPTY 0x0 +OS_EVENT *SWQ; +OS_EVENT *RS232Q; +INT8U err; + + +/* Error status */ +#define OK 0 + +/* Message queues */ +#define WAIT_FOREVER 0 + +// ==== INFRARED ==== + +/* Infrared message queue */ +#define IR_MAX_MESSAGES 4 +int ir_messages[IR_MAX_MESSAGES]; +OS_EVENT *ir_queue; + +/* Infrared messages */ +// Together these avoid passing 0 to the queue (which is not allowed since queue messages cannot be null) +// and invert pushbutton input (since the pushbutton returns 0 when it is pushed down). +#define IR_QUEUE_SEND_BASE 1 // Use: IR_QUEUE_SEND_BASE + IORD +#define IR_QUEUE_RECEIVE_BASE 2 // Use: IR_QUEUE_RECEIVE_BASE - OSQPend + + +MotorHandler *motor= new MotorHandler(); + + +// ==== mc + +#define mc_GUARD_TIME 1 + +void mc_task(void *pdata) +{ + printf("mc task\n"); + printf("MotorHandler [init"); + if (motor->init() == OK) { + printf("]\n\n"); + motor->forward(); + } else { + printf( ", error]\n"); + } + while(1){ + motor->reset(); + } +} + + + +// ==== GENERAL + +void queue_init() { + ir_queue = OSQCreate((void**)&ir_messages, IR_MAX_MESSAGES); +} + +/* The main function creates the LCD task, registers the edge counter polling interrupt, + * and starts the OS. */ +int main(void) +{ + int status = OK; + // Initialize components. + queue_init(); + // Create the mc task. + OSTaskCreateExt(mc_task, + NULL, + &mc_task_stk[TASK_STACKSIZE - 1], + MC_TASK_PRIORITY, + MC_TASK_PRIORITY, + mc_task_stk, + TASK_STACKSIZE, + NULL, + 0); + + if (status == OK) { + OSStart(); + } + + return 0; +} + +/****************************************************************************** + * * + * License Agreement * + * * + * Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * + * All rights reserved. * + * * + * Permission is hereby granted, free of charge, to any person obtaining a * + * copy of this software and associated documentation files (the "Software"), * + * to deal in the Software without restriction, including without limitation * + * the rights to use, copy, modify, merge, publish, distribute, sublicense, * + * and/or sell copies of the Software, and to permit persons to whom the * + * Software is furnished to do so, subject to the following conditions: * + * * + * The above copyright notice and this permission notice shall be included in * + * all copies or substantial portions of the Software. * + * * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * + * DEALINGS IN THE SOFTWARE. * + * * + * This agreement shall be governed in all respects by the laws of the State * + * of California and by the laws of the United States of America. * + * Altera does not recommend, suggest or require that this reference design * + * file be used in conjunction or combination with any other product. * + ******************************************************************************/ diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/d6/70c7a90a83b000131eb0f6c547a05c39 b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/d6/70c7a90a83b000131eb0f6c547a05c39 new file mode 100644 index 00000000..3475db7e --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/d6/70c7a90a83b000131eb0f6c547a05c39 @@ -0,0 +1,147 @@ +/************************************************************************* + * ARCap + * Amshu Gongal, Kenan Kigunda + * February 18, 2014 + ************************************************************************** + * Description: * + * Prototype testing for infrared and mc. + **************************************************************************/ + +#include +#include "includes.h" +#include "altera_avalon_pio_regs.h" +#include "altera_avalon_uart_regs.h" +#include "sys/alt_irq.h" +#include "alt_types.h" +#include "altera_up_avalon_rs232.h" +#include "altera_up_avalon_rs232_regs.h" + +#include "MotorHandler.h" +#include "Status.h" + +/* Task stacks */ +#define TASK_STACKSIZE 2048 +OS_STK ir_task_stk[TASK_STACKSIZE]; +OS_STK mc_task_stk[TASK_STACKSIZE]; +/* Task priorities */ +#define IR_TASK_PRIORITY 2 +#define MC_TASK_PRIORITY 1 + + +#define SW_READ 1 +#define SW_WRITE 2 +#define WRITE_FIFO_EMPTY 0x80 +#define READ_FIFO_EMPTY 0x0 +OS_EVENT *SWQ; +OS_EVENT *RS232Q; +INT8U err; + + +/* Error status */ +#define OK 0 + +/* Message queues */ +#define WAIT_FOREVER 0 + +// ==== INFRARED ==== + +/* Infrared message queue */ +#define IR_MAX_MESSAGES 4 +int ir_messages[IR_MAX_MESSAGES]; +OS_EVENT *ir_queue; + +/* Infrared messages */ +// Together these avoid passing 0 to the queue (which is not allowed since queue messages cannot be null) +// and invert pushbutton input (since the pushbutton returns 0 when it is pushed down). +#define IR_QUEUE_SEND_BASE 1 // Use: IR_QUEUE_SEND_BASE + IORD +#define IR_QUEUE_RECEIVE_BASE 2 // Use: IR_QUEUE_RECEIVE_BASE - OSQPend + + +MotorHandler *motor= new MotorHandler(); + + +// ==== mc + +#define mc_GUARD_TIME 1 + +void mc_task(void *pdata) +{ + printf("mc task\n"); + printf("MotorHandler [init"); + if (motor->init() == OK) { + printf("]\n\n"); + } else { + printf( ", error]\n"); + } + while(1){ + motor->move(0x05, 0x6F, "Left Motor Forward"); + OSTimeDlyHMSM(0, 0, 5, 0); + motor->move(0x05,0x00, "Left Motor Stop"); + OSTimeDlyHMSM(0, 0, 3,0); + + } +} + + + +// ==== GENERAL + +void queue_init() { + ir_queue = OSQCreate((void**)&ir_messages, IR_MAX_MESSAGES); +} + +/* The main function creates the LCD task, registers the edge counter polling interrupt, + * and starts the OS. */ +int main(void) +{ + int status = OK; + // Initialize components. + queue_init(); + // Create the mc task. + OSTaskCreateExt(mc_task, + NULL, + &mc_task_stk[TASK_STACKSIZE - 1], + MC_TASK_PRIORITY, + MC_TASK_PRIORITY, + mc_task_stk, + TASK_STACKSIZE, + NULL, + 0); + + if (status == OK) { + OSStart(); + } + + return 0; +} + +/****************************************************************************** + * * + * License Agreement * + * * + * Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * + * All rights reserved. * + * * + * Permission is hereby granted, free of charge, to any person obtaining a * + * copy of this software and associated documentation files (the "Software"), * + * to deal in the Software without restriction, including without limitation * + * the rights to use, copy, modify, merge, publish, distribute, sublicense, * + * and/or sell copies of the Software, and to permit persons to whom the * + * Software is furnished to do so, subject to the following conditions: * + * * + * The above copyright notice and this permission notice shall be included in * + * all copies or substantial portions of the Software. * + * * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * + * DEALINGS IN THE SOFTWARE. * + * * + * This agreement shall be governed in all respects by the laws of the State * + * of California and by the laws of the United States of America. * + * Altera does not recommend, suggest or require that this reference design * + * file be used in conjunction or combination with any other product. * + ******************************************************************************/ diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/d7/d04964ca8fab001311dbfe770f133bca b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/d7/d04964ca8fab001311dbfe770f133bca new file mode 100644 index 00000000..240db666 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/d7/d04964ca8fab001311dbfe770f133bca @@ -0,0 +1,150 @@ +/************************************************************************* + * ARCap + * Amshu Gongal, Kenan Kigunda + * February 18, 2014 + ************************************************************************** + * Description: * + * Prototype testing for infrared and mc. + **************************************************************************/ + +#include +#include "includes.h" +#include "altera_avalon_pio_regs.h" +#include "altera_avalon_uart_regs.h" +#include "sys/alt_irq.h" +#include "alt_types.h" +#include "altera_up_avalon_rs232.h" +#include "altera_up_avalon_rs232_regs.h" + +#include "MotorHandler.h" +#include "Status.h" + +/* Task stacks */ +#define TASK_STACKSIZE 2048 +OS_STK ir_task_stk[TASK_STACKSIZE]; +OS_STK mc_task_stk[TASK_STACKSIZE]; +/* Task priorities */ +#define IR_TASK_PRIORITY 2 +#define MC_TASK_PRIORITY 1 + + +#define SW_READ 1 +#define SW_WRITE 2 +#define WRITE_FIFO_EMPTY 0x80 +#define READ_FIFO_EMPTY 0x0 +OS_EVENT *SWQ; +OS_EVENT *RS232Q; +INT8U err; + + +/* Error status */ +#define OK 0 + +/* Message queues */ +#define WAIT_FOREVER 0 + +// ==== INFRARED ==== + +/* Infrared message queue */ +#define IR_MAX_MESSAGES 4 +int ir_messages[IR_MAX_MESSAGES]; +OS_EVENT *ir_queue; + +/* Infrared messages */ +// Together these avoid passing 0 to the queue (which is not allowed since queue messages cannot be null) +// and invert pushbutton input (since the pushbutton returns 0 when it is pushed down). +#define IR_QUEUE_SEND_BASE 1 // Use: IR_QUEUE_SEND_BASE + IORD +#define IR_QUEUE_RECEIVE_BASE 2 // Use: IR_QUEUE_RECEIVE_BASE - OSQPend + + +MotorHandler *motor= new MotorHandler(); + + +// ==== mc + +#define mc_GUARD_TIME 1 + +void mc_task(void *pdata) +{ + printf("mc task\n"); + printf("MotorHandler [init"); + if (motor->init() == OK) { + printf("]\n\n"); + motor->forward(); + } else { + printf( ", error]\n"); + } + while(1){ + motor->forward(); + OSTimeDlyHMSM(0, 0, 0, 100); + } +} + + + +// ==== GENERAL + +void queue_init() { + ir_queue = OSQCreate((void**)&ir_messages, IR_MAX_MESSAGES); +} + +/* The main function creates the LCD task, registers the edge counter polling interrupt, + * and starts the OS. */ +int main(void) +{ + int status = OK; + // Initialize components. + queue_init(); + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 0); + OSTimeDlyHMSM(0,0,0,100); + + // Create the mc task. + OSTaskCreateExt(mc_task, + NULL, + &mc_task_stk[TASK_STACKSIZE - 1], + MC_TASK_PRIORITY, + MC_TASK_PRIORITY, + mc_task_stk, + TASK_STACKSIZE, + NULL, + 0); + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 1); + OSTimeDlyHMSM(0,0,0,100); + + if (status == OK) { + OSStart(); + } + + return 0; +} + +/****************************************************************************** + * * + * License Agreement * + * * + * Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * + * All rights reserved. * + * * + * Permission is hereby granted, free of charge, to any person obtaining a * + * copy of this software and associated documentation files (the "Software"), * + * to deal in the Software without restriction, including without limitation * + * the rights to use, copy, modify, merge, publish, distribute, sublicense, * + * and/or sell copies of the Software, and to permit persons to whom the * + * Software is furnished to do so, subject to the following conditions: * + * * + * The above copyright notice and this permission notice shall be included in * + * all copies or substantial portions of the Software. * + * * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * + * DEALINGS IN THE SOFTWARE. * + * * + * This agreement shall be governed in all respects by the laws of the State * + * of California and by the laws of the United States of America. * + * Altera does not recommend, suggest or require that this reference design * + * file be used in conjunction or combination with any other product. * + ******************************************************************************/ diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/d9/1065f39eadab001311f2ce252b4696cb b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/d9/1065f39eadab001311f2ce252b4696cb new file mode 100644 index 00000000..93286b07 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/d9/1065f39eadab001311f2ce252b4696cb @@ -0,0 +1,153 @@ +/* + * MotorHandler.cpp + * + * Created on: 2014-03-03 + * Author: Amshu Gongal + */ + + +#include + +#include "altera_avalon_pio_regs.h" +#include "includes.h" +#include "system.h" + +#include "MotorHandler.h" + +#define WRITE_FIFO_EMPTY 0x80 +#define MOTOR_ENABLE 1 +#define MOTOR_RESET 0 + +// ALLOCATION +MotorHandler::MotorHandler() {} +MotorHandler::~MotorHandler() {} + +// INITIALIZATION + +/* + * Initializes this handler. + * @return OK if the handler was initialized without error + */ +Status MotorHandler::init() { + // Enable the motor controller. + reset(); + // Open the serial device to send commands to the motor controller. + motor_dev = alt_up_rs232_open_dev(RS232_MOTOR_NAME); + //printf("%d", motor_dev); + if (motor_dev == NULL) { + return ERR_MOTOR_OPEN; + } else { + return OK; + } +} + +void MotorHandler::configure(){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_CHANGE_CONFIGURATION, "change configuration"); + send(0X01, "2 MOTOR CONFIG"); + printf("\n"); +} +// TESTING + +void MotorHandler::test() { + send(MOTOR_START_BYTE, "test start"); +} + +// MOTOR CONTROL + +/* + * Move rover forward by activating both motors. + */ +void MotorHandler::forward() { + move(MOTOR_MOTOR1_FORWARD, "both motors forward"); + move(MOTOR_MOTOR2_FORWARD, "motor 2 forward"); +} + +/* + * Move rover backward by activating both motor backwards. + */ +void MotorHandler::backward() { + move(MOTOR_BOTH_BACKWARD, "both motors backward"); +// move(MOTOR_MOTOR2_BACKWARD, "motor 2 backward"); +} + +/* + * Turn rover left. + */ +void MotorHandler::left() { + move(MOTOR_MOTOR2_FORWARD, "motor 1 forward"); +} + +/* + * Turn rover right. + */ +void MotorHandler::right() { + move(MOTOR_MOTOR2_FORWARD, "motor 2 forward"); +} + +/* + * Stop the rover. + */ +void MotorHandler::stop() { + move(MOTOR_MOTOR1_FORWARD, MOTOR_STOP_SPEED, "motor 1 stop"); + move(MOTOR_MOTOR2_FORWARD, MOTOR_STOP_SPEED, "motor 2 stop"); +} + +// MOTOR CONTROL HELPERS + +/* + * Moves in the given direction at constant speed. + * @param direction - the motor and direction to move in, e.g. MOTOR_MOTOR1_FORWARD + * @param description - the string description of the movement, for debugging + */ +void MotorHandler::move(char direction, char *description) { + move(direction, MOTOR_CONST_SPEED, description); +} + +/* + * Moves in the given direction and speed. + * @param direction - the motor and direction to move in, e.g. MOTOR_MOTOR1_FORWARD + * @param speed - the speed to move at, i.e. MOTOR_CONST_SPEED or MOTOR_STOP_SPEED + * @param description - the string description of the movement, for debugging + */ +void MotorHandler::move(char direction, char speed, char *description) { + send(MOTOR_START_BYTE, "start"); + send(MOTOR_DEVICE_TYPE, "device"); + send(direction, description); + send(speed, "speed"); + printf("\n"); +} + +/* + * Sends a byte-length message to the motor controller. + * @param message - the message to send + * @param description - the string description of the message, for debugging + */ +void MotorHandler::send(char message, char *description) { + alt_u32 write_space; + // Check for write space. + write_space = alt_up_rs232_get_available_space_in_write_FIFO(motor_dev); + if (write_space >= WRITE_FIFO_EMPTY) { + // If space, write. + int status = alt_up_rs232_write_data(motor_dev, message); + printf("MotorHandler [message: 0x%02x, description: %s", message, description); + // Log errors. + if (status == OK) { + printf("]\n"); + } else { + printf(", error: cannot write]\n"); + } + } else { + // If no space, wait and retry. + printf("MotorHandler [message: 0x%02x, description: %s, error: no write space; retrying]\n", message, description); + OSTimeDlyHMSM(0, 0, 0, 10); + send(message, description); + } +} + +void MotorHandler::reset(){ + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 0); + OSTimeDlyHMSM(0, 0, 2,0 ); + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 1); + OSTimeDlyHMSM(0, 0, 2, 100); +} diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/da/a00da7f68cb000131eb0f6c547a05c39 b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/da/a00da7f68cb000131eb0f6c547a05c39 new file mode 100644 index 00000000..4f4bde0d --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/da/a00da7f68cb000131eb0f6c547a05c39 @@ -0,0 +1,146 @@ +/************************************************************************* + * ARCap + * Amshu Gongal, Kenan Kigunda + * February 18, 2014 + ************************************************************************** + * Description: * + * Prototype testing for infrared and mc. + **************************************************************************/ + +#include +#include "includes.h" +#include "altera_avalon_pio_regs.h" +#include "altera_avalon_uart_regs.h" +#include "sys/alt_irq.h" +#include "alt_types.h" +#include "altera_up_avalon_rs232.h" +#include "altera_up_avalon_rs232_regs.h" + +#include "MotorHandler.h" +#include "Status.h" + +/* Task stacks */ +#define TASK_STACKSIZE 2048 +OS_STK ir_task_stk[TASK_STACKSIZE]; +OS_STK mc_task_stk[TASK_STACKSIZE]; +/* Task priorities */ +#define IR_TASK_PRIORITY 2 +#define MC_TASK_PRIORITY 1 + + +#define SW_READ 1 +#define SW_WRITE 2 +#define WRITE_FIFO_EMPTY 0x80 +#define READ_FIFO_EMPTY 0x0 +OS_EVENT *SWQ; +OS_EVENT *RS232Q; +INT8U err; + + +/* Error status */ +#define OK 0 + +/* Message queues */ +#define WAIT_FOREVER 0 + +// ==== INFRARED ==== + +/* Infrared message queue */ +#define IR_MAX_MESSAGES 4 +int ir_messages[IR_MAX_MESSAGES]; +OS_EVENT *ir_queue; + +/* Infrared messages */ +// Together these avoid passing 0 to the queue (which is not allowed since queue messages cannot be null) +// and invert pushbutton input (since the pushbutton returns 0 when it is pushed down). +#define IR_QUEUE_SEND_BASE 1 // Use: IR_QUEUE_SEND_BASE + IORD +#define IR_QUEUE_RECEIVE_BASE 2 // Use: IR_QUEUE_RECEIVE_BASE - OSQPend + + +MotorHandler *motor= new MotorHandler(); + + +// ==== mc + +#define mc_GUARD_TIME 1 + +void mc_task(void *pdata) +{ + printf("mc task\n"); + printf("MotorHandler [init"); + if (motor->init() == OK) { + printf("]\n\n"); + } else { + printf( ", error]\n"); + } + while(1){ + motor->motorCommand("left", "forward", "120"); + OSTimeDlyHMSM(0, 0, 5, 0); + motor->motorCommand("left", "forward", 0); + OSTimeDlyHMSM(0, 0, 5, 0); + } +} + + + +// ==== GENERAL + +void queue_init() { + ir_queue = OSQCreate((void**)&ir_messages, IR_MAX_MESSAGES); +} + +/* The main function creates the LCD task, registers the edge counter polling interrupt, + * and starts the OS. */ +int main(void) +{ + int status = OK; + // Initialize components. + queue_init(); + // Create the mc task. + OSTaskCreateExt(mc_task, + NULL, + &mc_task_stk[TASK_STACKSIZE - 1], + MC_TASK_PRIORITY, + MC_TASK_PRIORITY, + mc_task_stk, + TASK_STACKSIZE, + NULL, + 0); + + if (status == OK) { + OSStart(); + } + + return 0; +} + +/****************************************************************************** + * * + * License Agreement * + * * + * Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * + * All rights reserved. * + * * + * Permission is hereby granted, free of charge, to any person obtaining a * + * copy of this software and associated documentation files (the "Software"), * + * to deal in the Software without restriction, including without limitation * + * the rights to use, copy, modify, merge, publish, distribute, sublicense, * + * and/or sell copies of the Software, and to permit persons to whom the * + * Software is furnished to do so, subject to the following conditions: * + * * + * The above copyright notice and this permission notice shall be included in * + * all copies or substantial portions of the Software. * + * * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * + * DEALINGS IN THE SOFTWARE. * + * * + * This agreement shall be governed in all respects by the laws of the State * + * of California and by the laws of the United States of America. * + * Altera does not recommend, suggest or require that this reference design * + * file be used in conjunction or combination with any other product. * + ******************************************************************************/ diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/dc/a0c102178aab001311dbfe770f133bca b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/dc/a0c102178aab001311dbfe770f133bca new file mode 100644 index 00000000..9f1cb4dc --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/dc/a0c102178aab001311dbfe770f133bca @@ -0,0 +1,150 @@ +/* + * MotorHandler.cpp + * + * Created on: 2014-03-03 + * Author: Amshu Gongal + */ + + +#include + +#include "altera_avalon_pio_regs.h" +#include "includes.h" +#include "system.h" + +#include "MotorHandler.h" + +#define WRITE_FIFO_EMPTY 0x80 +#define MOTOR_ENABLE 1 +#define MOTOR_RESET 0 + +// ALLOCATION +MotorHandler::MotorHandler() {} +MotorHandler::~MotorHandler() {} + +// INITIALIZATION + +/* + * Initializes this handler. + * @return OK if the handler was initialized without error + */ +Status MotorHandler::init() { + // Enable the motor controller. + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, MOTOR_ENABLE); + // Open the serial device to send commands to the motor controller. + motor_dev = alt_up_rs232_open_dev(RS232_MOTOR_NAME); + //printf("%d", motor_dev); + if (motor_dev == NULL) { + return ERR_MOTOR_OPEN; + } else { + return OK; + } +} + +void MotorHandler::configure(){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_CHANGE_CONFIGURATION, "change configuration"); + send(0X01, "2 MOTOR CONFIG"); + printf("\n"); +} +// TESTING + +void MotorHandler::test() { + send(MOTOR_START_BYTE, "test start"); +} + +// MOTOR CONTROL + +/* + * Move rover forward by activating both motors. + */ +void MotorHandler::forward() { + move(MOTOR_MOTOR1_FORWARD, "motor 1 forward"); + move(MOTOR_MOTOR2_FORWARD, "motor 2 forward"); +} + +/* + * Move rover backward by activating both motor backwards. + */ +void MotorHandler::backward() { + move(MOTOR_MOTOR1_BACKWARD, "motor 1 backward"); + move(MOTOR_MOTOR2_BACKWARD, "motor 2 backward"); +} + +/* + * Turn rover left. + */ +void MotorHandler::left() { + move(MOTOR_MOTOR2_FORWARD, "motor 1 forward"); +} + +/* + * Turn rover right. + */ +void MotorHandler::right() { + move(MOTOR_MOTOR2_FORWARD, "motor 2 forward"); +} + +/* + * Stop the rover. + */ +void MotorHandler::stop() { + move(MOTOR_MOTOR1_FORWARD, MOTOR_STOP_SPEED, "motor 1 stop"); + move(MOTOR_MOTOR2_FORWARD, MOTOR_STOP_SPEED, "motor 2 stop"); +} + +// MOTOR CONTROL HELPERS + +/* + * Moves in the given direction at constant speed. + * @param direction - the motor and direction to move in, e.g. MOTOR_MOTOR1_FORWARD + * @param description - the string description of the movement, for debugging + */ +void MotorHandler::move(char direction, char *description) { + move(direction, MOTOR_CONST_SPEED, description); +} + +/* + * Moves in the given direction and speed. + * @param direction - the motor and direction to move in, e.g. MOTOR_MOTOR1_FORWARD + * @param speed - the speed to move at, i.e. MOTOR_CONST_SPEED or MOTOR_STOP_SPEED + * @param description - the string description of the movement, for debugging + */ +void MotorHandler::move(char direction, char speed, char *description) { + send(MOTOR_START_BYTE, "start"); + send(MOTOR_DEVICE_TYPE, "device"); + send(direction, description); + send(speed, "speed"); + printf("\n"); +} + +/* + * Sends a byte-length message to the motor controller. + * @param message - the message to send + * @param description - the string description of the message, for debugging + */ +void MotorHandler::send(char message, char *description) { + alt_u32 write_space; + // Check for write space. + write_space = alt_up_rs232_get_available_space_in_write_FIFO(motor_dev); + if (write_space >= WRITE_FIFO_EMPTY) { + // If space, write. + int status = alt_up_rs232_write_data(motor_dev, message); + printf("MotorHandler [message: 0x%02x, description: %s", message, description); + // Log errors. + if (status == OK) { + printf("]\n"); + } else { + printf(", error: cannot write]\n"); + } + } else { + // If no space, wait and retry. + printf("MotorHandler [message: 0x%02x, description: %s, error: no write space; retrying]\n", message, description); + OSTimeDlyHMSM(0, 0, 0, 10); + send(message, description); + } +} + +void MotorHandler::resetMC(){ + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 1); +} diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/e0/b04553c682b000131eb0f6c547a05c39 b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/e0/b04553c682b000131eb0f6c547a05c39 new file mode 100644 index 00000000..0410b154 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/e0/b04553c682b000131eb0f6c547a05c39 @@ -0,0 +1,66 @@ +/* + * MotorHandler.h + * + * Created on: 2014-03-03 + * Author: Amshu Gongal + */ + +#ifndef MOTORHANDLER_H_ +#define MOTORHANDLER_H_ + +#include "altera_up_avalon_rs232.h" +#include "altera_up_avalon_rs232_regs.h" +#include +#include "Status.h" + +// Motor messages are LSB first +#define MOTOR_START_BYTE 0x80 +#define MOTOR_DEVICE_TYPE 0x00 +#define MOTOR_LEFT_BACKWARD 0x04 // motor 1 backward +#define MOTOR_RIGHT_BACKWARD 0x06 // motor 2 backward +#define MOTOR_LEFT_FORWARD 0x05 // motor 1 forward +#define MOTOR_RIGHT_FORWARD 0x07 // motor 2 forward +#define MOTOR_CONST_SPEED 0x5F +#define MOTOR_STOP_SPEED 0x00 +#define MOTOR_CHANGE_CONFIGURATION 0X02 + +class MotorHandler { +public: + MotorHandler(); + virtual ~MotorHandler(); + + /* + * Initializes this handler. + * @return OK if the handler was initialized without error + */ + Status init(); + void move(char , char, char *); + void forward(); + void backward(); + void right(); + void left(); + void stop(); + void configure(); + void test(); + void reset(); + +private: + /* The device used to send serial commands to the motor controller. */ + alt_up_rs232_dev *motor_dev; + + /* + * Moves in the given direction at constant speed. + * @param direction - the motor and direction to move in, e.g. MOTOR_MOTOR1_FORWARD + * @param description - the string description of the movement, for debugging + */ + void move(char direction, char *description); + + /* + * Sends a byte-length message to the motor controller. + * @param message - the message to send + * @param description - the string description of the message, for debugging + */ + void send(char message, char *description); +}; + +#endif /* MOTORHANDLER_H_ */ diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/e2/908d7f8880b000131eb0f6c547a05c39 b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/e2/908d7f8880b000131eb0f6c547a05c39 new file mode 100644 index 00000000..85e0d5d5 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/e2/908d7f8880b000131eb0f6c547a05c39 @@ -0,0 +1,147 @@ +/************************************************************************* + * ARCap + * Amshu Gongal, Kenan Kigunda + * February 18, 2014 + ************************************************************************** + * Description: * + * Prototype testing for infrared and mc. + **************************************************************************/ + +#include +#include "includes.h" +#include "altera_avalon_pio_regs.h" +#include "altera_avalon_uart_regs.h" +#include "sys/alt_irq.h" +#include "alt_types.h" +#include "altera_up_avalon_rs232.h" +#include "altera_up_avalon_rs232_regs.h" + +#include "MotorHandler.h" +#include "Status.h" + +/* Task stacks */ +#define TASK_STACKSIZE 2048 +OS_STK ir_task_stk[TASK_STACKSIZE]; +OS_STK mc_task_stk[TASK_STACKSIZE]; +/* Task priorities */ +#define IR_TASK_PRIORITY 2 +#define MC_TASK_PRIORITY 1 + + +#define SW_READ 1 +#define SW_WRITE 2 +#define WRITE_FIFO_EMPTY 0x80 +#define READ_FIFO_EMPTY 0x0 +OS_EVENT *SWQ; +OS_EVENT *RS232Q; +INT8U err; + + +/* Error status */ +#define OK 0 + +/* Message queues */ +#define WAIT_FOREVER 0 + +// ==== INFRARED ==== + +/* Infrared message queue */ +#define IR_MAX_MESSAGES 4 +int ir_messages[IR_MAX_MESSAGES]; +OS_EVENT *ir_queue; + +/* Infrared messages */ +// Together these avoid passing 0 to the queue (which is not allowed since queue messages cannot be null) +// and invert pushbutton input (since the pushbutton returns 0 when it is pushed down). +#define IR_QUEUE_SEND_BASE 1 // Use: IR_QUEUE_SEND_BASE + IORD +#define IR_QUEUE_RECEIVE_BASE 2 // Use: IR_QUEUE_RECEIVE_BASE - OSQPend + + +MotorHandler *motor= new MotorHandler(); + + +// ==== mc + +#define mc_GUARD_TIME 1 + +void mc_task(void *pdata) +{ + printf("mc task\n"); + printf("MotorHandler [init"); + if (motor->init() == OK) { + printf("]\n\n"); + } else { + printf( ", error]\n"); + } + while(1){ + motor->move(0x05, 0x6F, "Left Motor Forward"); + OSTimeDlyHMSM(0, 0, 5, 0); + motor->move(00x05,0x00, "Left Motor Stop"); + OSTimeDlyHMSM(0, 0, 3,0); + + } +} + + + +// ==== GENERAL + +void queue_init() { + ir_queue = OSQCreate((void**)&ir_messages, IR_MAX_MESSAGES); +} + +/* The main function creates the LCD task, registers the edge counter polling interrupt, + * and starts the OS. */ +int main(void) +{ + int status = OK; + // Initialize components. + queue_init(); + // Create the mc task. + OSTaskCreateExt(mc_task, + NULL, + &mc_task_stk[TASK_STACKSIZE - 1], + MC_TASK_PRIORITY, + MC_TASK_PRIORITY, + mc_task_stk, + TASK_STACKSIZE, + NULL, + 0); + + if (status == OK) { + OSStart(); + } + + return 0; +} + +/****************************************************************************** + * * + * License Agreement * + * * + * Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * + * All rights reserved. * + * * + * Permission is hereby granted, free of charge, to any person obtaining a * + * copy of this software and associated documentation files (the "Software"), * + * to deal in the Software without restriction, including without limitation * + * the rights to use, copy, modify, merge, publish, distribute, sublicense, * + * and/or sell copies of the Software, and to permit persons to whom the * + * Software is furnished to do so, subject to the following conditions: * + * * + * The above copyright notice and this permission notice shall be included in * + * all copies or substantial portions of the Software. * + * * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * + * DEALINGS IN THE SOFTWARE. * + * * + * This agreement shall be governed in all respects by the laws of the State * + * of California and by the laws of the United States of America. * + * Altera does not recommend, suggest or require that this reference design * + * file be used in conjunction or combination with any other product. * + ******************************************************************************/ diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/e6/704940608db000131eb0f6c547a05c39 b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/e6/704940608db000131eb0f6c547a05c39 new file mode 100644 index 00000000..813192d0 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/e6/704940608db000131eb0f6c547a05c39 @@ -0,0 +1,147 @@ +/************************************************************************* + * ARCap + * Amshu Gongal, Kenan Kigunda + * February 18, 2014 + ************************************************************************** + * Description: * + * Prototype testing for infrared and mc. + **************************************************************************/ + +#include +#include "includes.h" +#include "altera_avalon_pio_regs.h" +#include "altera_avalon_uart_regs.h" +#include "sys/alt_irq.h" +#include "alt_types.h" +#include "altera_up_avalon_rs232.h" +#include "altera_up_avalon_rs232_regs.h" + +#include "MotorHandler.h" +#include "Status.h" + +/* Task stacks */ +#define TASK_STACKSIZE 2048 +OS_STK ir_task_stk[TASK_STACKSIZE]; +OS_STK mc_task_stk[TASK_STACKSIZE]; +/* Task priorities */ +#define IR_TASK_PRIORITY 2 +#define MC_TASK_PRIORITY 1 + + +#define SW_READ 1 +#define SW_WRITE 2 +#define WRITE_FIFO_EMPTY 0x80 +#define READ_FIFO_EMPTY 0x0 +OS_EVENT *SWQ; +OS_EVENT *RS232Q; +INT8U err; + + +/* Error status */ +#define OK 0 + +/* Message queues */ +#define WAIT_FOREVER 0 + +// ==== INFRARED ==== + +/* Infrared message queue */ +#define IR_MAX_MESSAGES 4 +int ir_messages[IR_MAX_MESSAGES]; +OS_EVENT *ir_queue; + +/* Infrared messages */ +// Together these avoid passing 0 to the queue (which is not allowed since queue messages cannot be null) +// and invert pushbutton input (since the pushbutton returns 0 when it is pushed down). +#define IR_QUEUE_SEND_BASE 1 // Use: IR_QUEUE_SEND_BASE + IORD +#define IR_QUEUE_RECEIVE_BASE 2 // Use: IR_QUEUE_RECEIVE_BASE - OSQPend + + +MotorHandler *motor= new MotorHandler(); + + +// ==== mc + +#define mc_GUARD_TIME 1 + +void mc_task(void *pdata) +{ + printf("mc task\n"); + printf("MotorHandler [init"); + if (motor->init() == OK) { + printf("]\n\n"); + } else { + printf( ", error]\n"); + } + while(1){ + motor->motorCommand("left", "forward", "120"); + motor->motorCommand("right","forward", "120"); + OSTimeDlyHMSM(0, 0, 5, 0); + motor->motorCommand("left", "forward", "0"); + OSTimeDlyHMSM(0, 0, 5, 0); + } +} + + + +// ==== GENERAL + +void queue_init() { + ir_queue = OSQCreate((void**)&ir_messages, IR_MAX_MESSAGES); +} + +/* The main function creates the LCD task, registers the edge counter polling interrupt, + * and starts the OS. */ +int main(void) +{ + int status = OK; + // Initialize components. + queue_init(); + // Create the mc task. + OSTaskCreateExt(mc_task, + NULL, + &mc_task_stk[TASK_STACKSIZE - 1], + MC_TASK_PRIORITY, + MC_TASK_PRIORITY, + mc_task_stk, + TASK_STACKSIZE, + NULL, + 0); + + if (status == OK) { + OSStart(); + } + + return 0; +} + +/****************************************************************************** + * * + * License Agreement * + * * + * Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * + * All rights reserved. * + * * + * Permission is hereby granted, free of charge, to any person obtaining a * + * copy of this software and associated documentation files (the "Software"), * + * to deal in the Software without restriction, including without limitation * + * the rights to use, copy, modify, merge, publish, distribute, sublicense, * + * and/or sell copies of the Software, and to permit persons to whom the * + * Software is furnished to do so, subject to the following conditions: * + * * + * The above copyright notice and this permission notice shall be included in * + * all copies or substantial portions of the Software. * + * * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * + * DEALINGS IN THE SOFTWARE. * + * * + * This agreement shall be governed in all respects by the laws of the State * + * of California and by the laws of the United States of America. * + * Altera does not recommend, suggest or require that this reference design * + * file be used in conjunction or combination with any other product. * + ******************************************************************************/ diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/e9/104d085ea6ab001311f2ce252b4696cb b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/e9/104d085ea6ab001311f2ce252b4696cb new file mode 100644 index 00000000..43a93c20 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/e9/104d085ea6ab001311f2ce252b4696cb @@ -0,0 +1,145 @@ +/************************************************************************* + * ARCap + * Amshu Gongal, Kenan Kigunda + * February 18, 2014 + ************************************************************************** + * Description: * + * Prototype testing for infrared and mc. + **************************************************************************/ + +#include +#include "includes.h" +#include "altera_avalon_pio_regs.h" +#include "altera_avalon_uart_regs.h" +#include "sys/alt_irq.h" +#include "alt_types.h" +#include "altera_up_avalon_rs232.h" +#include "altera_up_avalon_rs232_regs.h" + +#include "MotorHandler.h" +#include "Status.h" + +/* Task stacks */ +#define TASK_STACKSIZE 2048 +OS_STK ir_task_stk[TASK_STACKSIZE]; +OS_STK mc_task_stk[TASK_STACKSIZE]; +/* Task priorities */ +#define IR_TASK_PRIORITY 2 +#define MC_TASK_PRIORITY 1 + + +#define SW_READ 1 +#define SW_WRITE 2 +#define WRITE_FIFO_EMPTY 0x80 +#define READ_FIFO_EMPTY 0x0 +OS_EVENT *SWQ; +OS_EVENT *RS232Q; +INT8U err; + + +/* Error status */ +#define OK 0 + +/* Message queues */ +#define WAIT_FOREVER 0 + +// ==== INFRARED ==== + +/* Infrared message queue */ +#define IR_MAX_MESSAGES 4 +int ir_messages[IR_MAX_MESSAGES]; +OS_EVENT *ir_queue; + +/* Infrared messages */ +// Together these avoid passing 0 to the queue (which is not allowed since queue messages cannot be null) +// and invert pushbutton input (since the pushbutton returns 0 when it is pushed down). +#define IR_QUEUE_SEND_BASE 1 // Use: IR_QUEUE_SEND_BASE + IORD +#define IR_QUEUE_RECEIVE_BASE 2 // Use: IR_QUEUE_RECEIVE_BASE - OSQPend + + +MotorHandler *motor= new MotorHandler(); + + +// ==== mc + +#define mc_GUARD_TIME 1 + +void mc_task(void *pdata) +{ + printf("mc task\n"); + printf("MotorHandler [init"); + if (motor->init() == OK) { + printf("]\n\n"); + motor->forward(); + } else { + printf( ", error]\n"); + } + while(1){ + motor->reset(); + } +} + + + +// ==== GENERAL + +void queue_init() { + ir_queue = OSQCreate((void**)&ir_messages, IR_MAX_MESSAGES); +} + +/* The main function creates the LCD task, registers the edge counter polling interrupt, + * and starts the OS. */ +int main(void) +{ + int status = OK; + // Initialize components. + queue_init(); + motor->reset(); + // Create the mc task. + OSTaskCreateExt(mc_task, + NULL, + &mc_task_stk[TASK_STACKSIZE - 1], + MC_TASK_PRIORITY, + MC_TASK_PRIORITY, + mc_task_stk, + TASK_STACKSIZE, + NULL, + 0); + + if (status == OK) { + OSStart(); + } + + return 0; +} + +/****************************************************************************** + * * + * License Agreement * + * * + * Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * + * All rights reserved. * + * * + * Permission is hereby granted, free of charge, to any person obtaining a * + * copy of this software and associated documentation files (the "Software"), * + * to deal in the Software without restriction, including without limitation * + * the rights to use, copy, modify, merge, publish, distribute, sublicense, * + * and/or sell copies of the Software, and to permit persons to whom the * + * Software is furnished to do so, subject to the following conditions: * + * * + * The above copyright notice and this permission notice shall be included in * + * all copies or substantial portions of the Software. * + * * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * + * DEALINGS IN THE SOFTWARE. * + * * + * This agreement shall be governed in all respects by the laws of the State * + * of California and by the laws of the United States of America. * + * Altera does not recommend, suggest or require that this reference design * + * file be used in conjunction or combination with any other product. * + ******************************************************************************/ diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/e9/80459c918ab000131eb0f6c547a05c39 b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/e9/80459c918ab000131eb0f6c547a05c39 new file mode 100644 index 00000000..16c8ec9a --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/e9/80459c918ab000131eb0f6c547a05c39 @@ -0,0 +1,136 @@ +/* + * MotorHandler.cpp + * + * Created on: 2014-03-03 + * Author: Amshu Gongal + */ + + +#include +#include + +#include "altera_avalon_pio_regs.h" +#include "includes.h" +#include "system.h" + +#include "MotorHandler.h" + +#define WRITE_FIFO_EMPTY 0x80 +#define MOTOR_ENABLE 1 +#define MOTOR_RESET 0 + +// ALLOCATION +MotorHandler::MotorHandler() {} +MotorHandler::~MotorHandler() {} + + +// INITIALIZATION + +/* + * Initializes this handler. + * @return OK if the handler was initialized without error + */ +Status MotorHandler::init() { + // Enable the motor controller. + reset(); + // Open the serial device to send commands to the motor controller. + motor_dev = alt_up_rs232_open_dev(RS232_MOTOR_NAME); + //printf("%d", motor_dev); + if (motor_dev == NULL) { + return ERR_MOTOR_OPEN; + } else { + return OK; + } +} + +void MotorHandler::configure(){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_CHANGE_CONFIGURATION, "change configuration"); + send(0X01, "2 MOTOR CONFIG"); + printf("\n"); +} + +//Command Interpreter +/* + * Interprets the command from the network handler and sends move commands + * @param motor The motor to move eg. Left or Right + * @param motorDirection The direction of the given motor to move + * @param speed The speed the motor is to move + */ +void MotorHandler::motorCommand(string motor, string motorDirection, string speed){ + char motorID = interpretMotor(motor); + char directionByte = interpretDirection(motorDirection, int(motorID)); + int speedByte = strtol(speed.c_str(), NULL, 0); + move(directionByte, speedByte, "Move Motor"); +} + + +char MotorHandler::interpretMotor(string motor){ + if(motor.compare(MOTOR_LEFT) == 0){ + return MOTOR_LEFT_CHAR; + } + else{ + return MOTOR_RIGHT_CHAR; + } +} + +char MotorHandler::interpretDirection(string direction, int motor){ + if(direction.compare(MOTOR_FORWARD) == 0){ + return (char) (motor*2 + 1); + } + else{ + return (char) (motor*2); + } +} + +// MOTOR CONTROL + +/*Moves the given motor in specified direction by Motor Direction with specified + * Speed + * @param MotorDirection Motor and direction to move + * @param Speed the speed to move at + * @param string description of motor movement + */ + +void MotorHandler::move(char MotorDirection,char Speed,char * Description){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_DEVICE_TYPE, "device"); + send(MotorDirection, Description); + send(Speed, "speed"); + printf("\n"); +} + +// MOTOR CONTROL HELPERS +/* + * Sends a byte-length message to the motor controller. + * @param message - the message to send + * @param description - the string description of the message, for debugging + */ +void MotorHandler::send(char message, char *description) { + alt_u32 write_space; + // Check for write space. + write_space = alt_up_rs232_get_available_space_in_write_FIFO(motor_dev); + if (write_space >= WRITE_FIFO_EMPTY) { + // If space, write. + int status = alt_up_rs232_write_data(motor_dev, message); + printf("MotorHandler [message: 0x%02x, description: %s", message, description); + // Log errors. + if (status == OK) { + printf("]\n"); + } else { + printf(", error: cannot write]\n"); + } + } else { + // If no space, wait and retry. + printf("MotorHandler [message: 0x%02x, description: %s, error: no write space; retrying]\n", message, description); + OSTimeDlyHMSM(0, 0, 0, 10); + send(message, description); + } +} + +void MotorHandler::reset(){ + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 0); + OSTimeDlyHMSM(0, 0, 0,200 ); + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 1); + OSTimeDlyHMSM(0, 0, 0, 200); +} diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/eb/10550b8687b000131eb0f6c547a05c39 b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/eb/10550b8687b000131eb0f6c547a05c39 new file mode 100644 index 00000000..6af9709d --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/eb/10550b8687b000131eb0f6c547a05c39 @@ -0,0 +1,123 @@ +/* + * MotorHandler.cpp + * + * Created on: 2014-03-03 + * Author: Amshu Gongal + */ + + +#include + +#include "altera_avalon_pio_regs.h" +#include "includes.h" +#include "system.h" + +#include "MotorHandler.h" + +#define WRITE_FIFO_EMPTY 0x80 +#define MOTOR_ENABLE 1 +#define MOTOR_RESET 0 + +// ALLOCATION +MotorHandler::MotorHandler() {} +MotorHandler::~MotorHandler() {} + + +// INITIALIZATION + +/* + * Initializes this handler. + * @return OK if the handler was initialized without error + */ +Status MotorHandler::init() { + // Enable the motor controller. + reset(); + // Open the serial device to send commands to the motor controller. + motor_dev = alt_up_rs232_open_dev(RS232_MOTOR_NAME); + //printf("%d", motor_dev); + if (motor_dev == NULL) { + return ERR_MOTOR_OPEN; + } else { + return OK; + } +} + +void MotorHandler::configure(){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_CHANGE_CONFIGURATION, "change configuration"); + send(0X01, "2 MOTOR CONFIG"); + printf("\n"); +} + +//Command Interpreter +/* + * Interprets the command from the network handler and sends move commands + * @param motor The motor to move eg. Left or Right + * @param motorDirection The direction of the given motor to move + * @param speed The speed the motor is to move + */ +void MotorHandler::motorCommand(string motor, string motorDirection, string speed){ + char motorC = interpretMotor(motor); +} + +char MotorHandler::interpretMotor(string motor){ + if(motor.compare(MOTOR_LEFT) == 0){ + return MOTOR_LEFT_CHAR; + } +} + +char MotorHandler::interpretDirection(string direction, int motor){ + +} + +// MOTOR CONTROL + +/*Moves the given motor in specified direction by Motor Direction with specified + * Speed + * @param MotorDirection Motor and direction to move + * @param Speed the speed to move at + * @param string description of motor movement + */ + +void MotorHandler::move(char MotorDirection,char Speed,char * Description){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_DEVICE_TYPE, "device"); + send(MotorDirection, Description); + send(Speed, "speed"); + printf("\n"); +} + +// MOTOR CONTROL HELPERS +/* + * Sends a byte-length message to the motor controller. + * @param message - the message to send + * @param description - the string description of the message, for debugging + */ +void MotorHandler::send(char message, char *description) { + alt_u32 write_space; + // Check for write space. + write_space = alt_up_rs232_get_available_space_in_write_FIFO(motor_dev); + if (write_space >= WRITE_FIFO_EMPTY) { + // If space, write. + int status = alt_up_rs232_write_data(motor_dev, message); + printf("MotorHandler [message: 0x%02x, description: %s", message, description); + // Log errors. + if (status == OK) { + printf("]\n"); + } else { + printf(", error: cannot write]\n"); + } + } else { + // If no space, wait and retry. + printf("MotorHandler [message: 0x%02x, description: %s, error: no write space; retrying]\n", message, description); + OSTimeDlyHMSM(0, 0, 0, 10); + send(message, description); + } +} + +void MotorHandler::reset(){ + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 0); + OSTimeDlyHMSM(0, 0, 0,200 ); + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 1); + OSTimeDlyHMSM(0, 0, 0, 200); +} diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/eb/4076ad858ab000131eb0f6c547a05c39 b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/eb/4076ad858ab000131eb0f6c547a05c39 new file mode 100644 index 00000000..632e271b --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/eb/4076ad858ab000131eb0f6c547a05c39 @@ -0,0 +1,136 @@ +/* + * MotorHandler.cpp + * + * Created on: 2014-03-03 + * Author: Amshu Gongal + */ + + +#include +#include + +#include "altera_avalon_pio_regs.h" +#include "includes.h" +#include "system.h" + +#include "MotorHandler.h" + +#define WRITE_FIFO_EMPTY 0x80 +#define MOTOR_ENABLE 1 +#define MOTOR_RESET 0 + +// ALLOCATION +MotorHandler::MotorHandler() {} +MotorHandler::~MotorHandler() {} + + +// INITIALIZATION + +/* + * Initializes this handler. + * @return OK if the handler was initialized without error + */ +Status MotorHandler::init() { + // Enable the motor controller. + reset(); + // Open the serial device to send commands to the motor controller. + motor_dev = alt_up_rs232_open_dev(RS232_MOTOR_NAME); + //printf("%d", motor_dev); + if (motor_dev == NULL) { + return ERR_MOTOR_OPEN; + } else { + return OK; + } +} + +void MotorHandler::configure(){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_CHANGE_CONFIGURATION, "change configuration"); + send(0X01, "2 MOTOR CONFIG"); + printf("\n"); +} + +//Command Interpreter +/* + * Interprets the command from the network handler and sends move commands + * @param motor The motor to move eg. Left or Right + * @param motorDirection The direction of the given motor to move + * @param speed The speed the motor is to move + */ +void MotorHandler::motorCommand(string motor, string motorDirection, string speed){ + char motorID = interpretMotor(motor); + char directionByte = interpretDirection(motorDirection, int(motorID)); + char speedByte = (char)strtol(speed.c_str(), NULL, 0); + move(directionByte, speedByte, "Move Motor"); +} + + +char MotorHandler::interpretMotor(string motor){ + if(motor.compare(MOTOR_LEFT) == 0){ + return MOTOR_LEFT_CHAR; + } + else{ + return MOTOR_RIGHT_CHAR; + } +} + +char MotorHandler::interpretDirection(string direction, int motor){ + if(direction.compare(MOTOR_FORWARD) == 0){ + return (char) (motor*2 + 1); + } + else{ + return (char) (motor*2); + } +} + +// MOTOR CONTROL + +/*Moves the given motor in specified direction by Motor Direction with specified + * Speed + * @param MotorDirection Motor and direction to move + * @param Speed the speed to move at + * @param string description of motor movement + */ + +void MotorHandler::move(char MotorDirection,char Speed,char * Description){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_DEVICE_TYPE, "device"); + send(MotorDirection, Description); + send(Speed, "speed"); + printf("\n"); +} + +// MOTOR CONTROL HELPERS +/* + * Sends a byte-length message to the motor controller. + * @param message - the message to send + * @param description - the string description of the message, for debugging + */ +void MotorHandler::send(char message, char *description) { + alt_u32 write_space; + // Check for write space. + write_space = alt_up_rs232_get_available_space_in_write_FIFO(motor_dev); + if (write_space >= WRITE_FIFO_EMPTY) { + // If space, write. + int status = alt_up_rs232_write_data(motor_dev, message); + printf("MotorHandler [message: 0x%02x, description: %s", message, description); + // Log errors. + if (status == OK) { + printf("]\n"); + } else { + printf(", error: cannot write]\n"); + } + } else { + // If no space, wait and retry. + printf("MotorHandler [message: 0x%02x, description: %s, error: no write space; retrying]\n", message, description); + OSTimeDlyHMSM(0, 0, 0, 10); + send(message, description); + } +} + +void MotorHandler::reset(){ + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 0); + OSTimeDlyHMSM(0, 0, 0,200 ); + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 1); + OSTimeDlyHMSM(0, 0, 0, 200); +} diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/ec/a0a6123f86b000131eb0f6c547a05c39 b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/ec/a0a6123f86b000131eb0f6c547a05c39 new file mode 100644 index 00000000..abcf8bef --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/ec/a0a6123f86b000131eb0f6c547a05c39 @@ -0,0 +1,107 @@ +/* + * MotorHandler.cpp + * + * Created on: 2014-03-03 + * Author: Amshu Gongal + */ + + +#include + +#include "altera_avalon_pio_regs.h" +#include "includes.h" +#include "system.h" + +#include "MotorHandler.h" + +#define WRITE_FIFO_EMPTY 0x80 +#define MOTOR_ENABLE 1 +#define MOTOR_RESET 0 + +// ALLOCATION +MotorHandler::MotorHandler() {} +MotorHandler::~MotorHandler() {} + + +// INITIALIZATION + +/* + * Initializes this handler. + * @return OK if the handler was initialized without error + */ +Status MotorHandler::init() { + // Enable the motor controller. + reset(); + // Open the serial device to send commands to the motor controller. + motor_dev = alt_up_rs232_open_dev(RS232_MOTOR_NAME); + //printf("%d", motor_dev); + if (motor_dev == NULL) { + return ERR_MOTOR_OPEN; + } else { + return OK; + } +} + +void MotorHandler::configure(){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_CHANGE_CONFIGURATION, "change configuration"); + send(0X01, "2 MOTOR CONFIG"); + printf("\n"); +} + +//Command Interpreter +void MotorHandler::motorCommand(string motor, string motorDirection, char speed){ + +} + +// MOTOR CONTROL + +/*Moves the given motor in specified direction by Motor Direction with specified + * Speed + * @param MotorDirection Motor and direction to move + * @param Speed the speed to move at + * @param string description of motor movement + */ + +void MotorHandler::move(char MotorDirection,char Speed,char * Description){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_DEVICE_TYPE, "device"); + send(MotorDirection, Description); + send(Speed, "speed"); + printf("\n"); +} + +// MOTOR CONTROL HELPERS +/* + * Sends a byte-length message to the motor controller. + * @param message - the message to send + * @param description - the string description of the message, for debugging + */ +void MotorHandler::send(char message, char *description) { + alt_u32 write_space; + // Check for write space. + write_space = alt_up_rs232_get_available_space_in_write_FIFO(motor_dev); + if (write_space >= WRITE_FIFO_EMPTY) { + // If space, write. + int status = alt_up_rs232_write_data(motor_dev, message); + printf("MotorHandler [message: 0x%02x, description: %s", message, description); + // Log errors. + if (status == OK) { + printf("]\n"); + } else { + printf(", error: cannot write]\n"); + } + } else { + // If no space, wait and retry. + printf("MotorHandler [message: 0x%02x, description: %s, error: no write space; retrying]\n", message, description); + OSTimeDlyHMSM(0, 0, 0, 10); + send(message, description); + } +} + +void MotorHandler::reset(){ + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 0); + OSTimeDlyHMSM(0, 0, 0,200 ); + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 1); + OSTimeDlyHMSM(0, 0, 0, 200); +} diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/f0/d0cce1968bb000131eb0f6c547a05c39 b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/f0/d0cce1968bb000131eb0f6c547a05c39 new file mode 100644 index 00000000..a807feb7 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/f0/d0cce1968bb000131eb0f6c547a05c39 @@ -0,0 +1,136 @@ +/* + * MotorHandler.cpp + * + * Created on: 2014-03-03 + * Author: Amshu Gongal + */ + + +#include +#include + +#include "altera_avalon_pio_regs.h" +#include "includes.h" +#include "system.h" + +#include "MotorHandler.h" + +#define WRITE_FIFO_EMPTY 0x80 +#define MOTOR_ENABLE 1 +#define MOTOR_RESET 0 + +// ALLOCATION +MotorHandler::MotorHandler() {} +MotorHandler::~MotorHandler() {} + + +// INITIALIZATION + +/* + * Initializes this handler. + * @return OK if the handler was initialized without error + */ +Status MotorHandler::init() { + // Enable the motor controller. + reset(); + // Open the serial device to send commands to the motor controller. + motor_dev = alt_up_rs232_open_dev(RS232_MOTOR_NAME); + //printf("%d", motor_dev); + if (motor_dev == NULL) { + return ERR_MOTOR_OPEN; + } else { + return OK; + } +} + +void MotorHandler::configure(){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_CHANGE_CONFIGURATION, "change configuration"); + send(0X01, "2 MOTOR CONFIG"); + printf("\n"); +} + +//Command Interpreter +/* + * Interprets the command from the network handler and sends move commands + * @param motor The motor to move eg. Left or Right + * @param motorDirection The direction of the given motor to move + * @param speed The speed the motor is to move + */ +void MotorHandler::motorCommand(string motor, string motorDirection, string speed){ + char motorID = interpretMotor(motor); + char directionByte = interpretDirection(motorDirection, int(motorID)); + int speedByte = strtol(speed.c_str(), NULL, 0); + move(directionByte, speedByte, motor.append(motorDirection)); +} + + +char MotorHandler::interpretMotor(string motor){ + if(motor.compare(MOTOR_LEFT) == 0){ + return MOTOR_LEFT_CHAR; + } + else{ + return MOTOR_RIGHT_CHAR; + } +} + +char MotorHandler::interpretDirection(string direction, int motor){ + if(direction.compare(MOTOR_FORWARD) == 0){ + return (char) (motor*2 + 1); + } + else{ + return (char) (motor*2); + } +} + +// MOTOR CONTROL + +/*Moves the given motor in specified direction by Motor Direction with specified + * Speed + * @param MotorDirection Motor and direction to move + * @param Speed the speed to move at + * @param string description of motor movement + */ + +void MotorHandler::move(char motorDirection, char speed, string description){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_DEVICE_TYPE, "device"); + send(motorDirection, description); + send(speed, "speed"); + printf("\n"); +} + +// MOTOR CONTROL HELPERS +/* + * Sends a byte-length message to the motor controller. + * @param message - the message to send + * @param description - the string description of the message, for debugging + */ +void MotorHandler::send(char message, string description) { + alt_u32 write_space; + // Check for write space. + write_space = alt_up_rs232_get_available_space_in_write_FIFO(motor_dev); + if (write_space >= WRITE_FIFO_EMPTY) { + // If space, write. + int status = alt_up_rs232_write_data(motor_dev, message); + printf("MotorHandler [message: 0x%02x, description: %s", message, description); + // Log errors. + if (status == OK) { + printf("]\n"); + } else { + printf(", error: cannot write]\n"); + } + } else { + // If no space, wait and retry. + printf("MotorHandler [message: 0x%02x, description: %s, error: no write space; retrying]\n", message, description); + OSTimeDlyHMSM(0, 0, 0, 10); + send(message, description); + } +} + +void MotorHandler::reset(){ + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 0); + OSTimeDlyHMSM(0, 0, 0,200 ); + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 1); + OSTimeDlyHMSM(0, 0, 0, 200); +} diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/f1/80f527f289b000131eb0f6c547a05c39 b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/f1/80f527f289b000131eb0f6c547a05c39 new file mode 100644 index 00000000..d9304ba0 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/f1/80f527f289b000131eb0f6c547a05c39 @@ -0,0 +1,135 @@ +/* + * MotorHandler.cpp + * + * Created on: 2014-03-03 + * Author: Amshu Gongal + */ + + +#include +#include + +#include "altera_avalon_pio_regs.h" +#include "includes.h" +#include "system.h" + +#include "MotorHandler.h" + +#define WRITE_FIFO_EMPTY 0x80 +#define MOTOR_ENABLE 1 +#define MOTOR_RESET 0 + +// ALLOCATION +MotorHandler::MotorHandler() {} +MotorHandler::~MotorHandler() {} + + +// INITIALIZATION + +/* + * Initializes this handler. + * @return OK if the handler was initialized without error + */ +Status MotorHandler::init() { + // Enable the motor controller. + reset(); + // Open the serial device to send commands to the motor controller. + motor_dev = alt_up_rs232_open_dev(RS232_MOTOR_NAME); + //printf("%d", motor_dev); + if (motor_dev == NULL) { + return ERR_MOTOR_OPEN; + } else { + return OK; + } +} + +void MotorHandler::configure(){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_CHANGE_CONFIGURATION, "change configuration"); + send(0X01, "2 MOTOR CONFIG"); + printf("\n"); +} + +//Command Interpreter +/* + * Interprets the command from the network handler and sends move commands + * @param motor The motor to move eg. Left or Right + * @param motorDirection The direction of the given motor to move + * @param speed The speed the motor is to move + */ +void MotorHandler::motorCommand(string motor, string motorDirection, string speed){ + char motorID = interpretMotor(motor); + char directionByte = interpretDirection(motorDirection, int(motorID)); + int speedByte = speed.c_str() + move(directionByte, speedByte, "Move Motor"); +} + +char MotorHandler::interpretMotor(string motor){ + if(motor.compare(MOTOR_LEFT) == 0){ + return MOTOR_LEFT_CHAR; + } + else{ + return MOTOR_RIGHT_CHAR; + } +} + +char MotorHandler::interpretDirection(string direction, int motor){ + if(direction.compare(MOTOR_FORWARD) == 0){ + return (char) (motor*2 + 1); + } + else{ + return (char) (motor*2); + } +} + +// MOTOR CONTROL + +/*Moves the given motor in specified direction by Motor Direction with specified + * Speed + * @param MotorDirection Motor and direction to move + * @param Speed the speed to move at + * @param string description of motor movement + */ + +void MotorHandler::move(char MotorDirection,char Speed,char * Description){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_DEVICE_TYPE, "device"); + send(MotorDirection, Description); + send(Speed, "speed"); + printf("\n"); +} + +// MOTOR CONTROL HELPERS +/* + * Sends a byte-length message to the motor controller. + * @param message - the message to send + * @param description - the string description of the message, for debugging + */ +void MotorHandler::send(char message, char *description) { + alt_u32 write_space; + // Check for write space. + write_space = alt_up_rs232_get_available_space_in_write_FIFO(motor_dev); + if (write_space >= WRITE_FIFO_EMPTY) { + // If space, write. + int status = alt_up_rs232_write_data(motor_dev, message); + printf("MotorHandler [message: 0x%02x, description: %s", message, description); + // Log errors. + if (status == OK) { + printf("]\n"); + } else { + printf(", error: cannot write]\n"); + } + } else { + // If no space, wait and retry. + printf("MotorHandler [message: 0x%02x, description: %s, error: no write space; retrying]\n", message, description); + OSTimeDlyHMSM(0, 0, 0, 10); + send(message, description); + } +} + +void MotorHandler::reset(){ + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 0); + OSTimeDlyHMSM(0, 0, 0,200 ); + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 1); + OSTimeDlyHMSM(0, 0, 0, 200); +} diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/f3/c0fb870e90ab001311dbfe770f133bca b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/f3/c0fb870e90ab001311dbfe770f133bca new file mode 100644 index 00000000..7465a18a --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/f3/c0fb870e90ab001311dbfe770f133bca @@ -0,0 +1,147 @@ +/************************************************************************* + * ARCap + * Amshu Gongal, Kenan Kigunda + * February 18, 2014 + ************************************************************************** + * Description: * + * Prototype testing for infrared and mc. + **************************************************************************/ + +#include +#include "includes.h" +#include "altera_avalon_pio_regs.h" +#include "altera_avalon_uart_regs.h" +#include "sys/alt_irq.h" +#include "alt_types.h" +#include "altera_up_avalon_rs232.h" +#include "altera_up_avalon_rs232_regs.h" + +#include "MotorHandler.h" +#include "Status.h" + +/* Task stacks */ +#define TASK_STACKSIZE 2048 +OS_STK ir_task_stk[TASK_STACKSIZE]; +OS_STK mc_task_stk[TASK_STACKSIZE]; +/* Task priorities */ +#define IR_TASK_PRIORITY 2 +#define MC_TASK_PRIORITY 1 + + +#define SW_READ 1 +#define SW_WRITE 2 +#define WRITE_FIFO_EMPTY 0x80 +#define READ_FIFO_EMPTY 0x0 +OS_EVENT *SWQ; +OS_EVENT *RS232Q; +INT8U err; + + +/* Error status */ +#define OK 0 + +/* Message queues */ +#define WAIT_FOREVER 0 + +// ==== INFRARED ==== + +/* Infrared message queue */ +#define IR_MAX_MESSAGES 4 +int ir_messages[IR_MAX_MESSAGES]; +OS_EVENT *ir_queue; + +/* Infrared messages */ +// Together these avoid passing 0 to the queue (which is not allowed since queue messages cannot be null) +// and invert pushbutton input (since the pushbutton returns 0 when it is pushed down). +#define IR_QUEUE_SEND_BASE 1 // Use: IR_QUEUE_SEND_BASE + IORD +#define IR_QUEUE_RECEIVE_BASE 2 // Use: IR_QUEUE_RECEIVE_BASE - OSQPend + + +MotorHandler *motor= new MotorHandler(); + + +// ==== mc + +#define mc_GUARD_TIME 1 + +void mc_task(void *pdata) +{ + printf("mc task\n"); + printf("MotorHandler [init"); + if (motor->init() == OK) { + printf("]\n\n"); + motor->forward(); + } else { + printf( ", error]\n"); + } + while(1){ + motor->forward(); + OSTimeDlyHMSM(0, 0, 0, 100); + } +} + + + +// ==== GENERAL + +void queue_init() { + ir_queue = OSQCreate((void**)&ir_messages, IR_MAX_MESSAGES); +} + +/* The main function creates the LCD task, registers the edge counter polling interrupt, + * and starts the OS. */ +int main(void) +{ + int status = OK; + // Initialize components. + queue_init(); + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 1); + // Create the mc task. + OSTaskCreateExt(mc_task, + NULL, + &mc_task_stk[TASK_STACKSIZE - 1], + MC_TASK_PRIORITY, + MC_TASK_PRIORITY, + mc_task_stk, + TASK_STACKSIZE, + NULL, + 0); + + + if (status == OK) { + OSStart(); + } + + return 0; +} + +/****************************************************************************** + * * + * License Agreement * + * * + * Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * + * All rights reserved. * + * * + * Permission is hereby granted, free of charge, to any person obtaining a * + * copy of this software and associated documentation files (the "Software"), * + * to deal in the Software without restriction, including without limitation * + * the rights to use, copy, modify, merge, publish, distribute, sublicense, * + * and/or sell copies of the Software, and to permit persons to whom the * + * Software is furnished to do so, subject to the following conditions: * + * * + * The above copyright notice and this permission notice shall be included in * + * all copies or substantial portions of the Software. * + * * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * + * DEALINGS IN THE SOFTWARE. * + * * + * This agreement shall be governed in all respects by the laws of the State * + * of California and by the laws of the United States of America. * + * Altera does not recommend, suggest or require that this reference design * + * file be used in conjunction or combination with any other product. * + ******************************************************************************/ diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/f8/0094590289b000131eb0f6c547a05c39 b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/f8/0094590289b000131eb0f6c547a05c39 new file mode 100644 index 00000000..51807661 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/f8/0094590289b000131eb0f6c547a05c39 @@ -0,0 +1,134 @@ +/* + * MotorHandler.cpp + * + * Created on: 2014-03-03 + * Author: Amshu Gongal + */ + + +#include + +#include "altera_avalon_pio_regs.h" +#include "includes.h" +#include "system.h" + +#include "MotorHandler.h" + +#define WRITE_FIFO_EMPTY 0x80 +#define MOTOR_ENABLE 1 +#define MOTOR_RESET 0 + +// ALLOCATION +MotorHandler::MotorHandler() {} +MotorHandler::~MotorHandler() {} + + +// INITIALIZATION + +/* + * Initializes this handler. + * @return OK if the handler was initialized without error + */ +Status MotorHandler::init() { + // Enable the motor controller. + reset(); + // Open the serial device to send commands to the motor controller. + motor_dev = alt_up_rs232_open_dev(RS232_MOTOR_NAME); + //printf("%d", motor_dev); + if (motor_dev == NULL) { + return ERR_MOTOR_OPEN; + } else { + return OK; + } +} + +void MotorHandler::configure(){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_CHANGE_CONFIGURATION, "change configuration"); + send(0X01, "2 MOTOR CONFIG"); + printf("\n"); +} + +//Command Interpreter +/* + * Interprets the command from the network handler and sends move commands + * @param motor The motor to move eg. Left or Right + * @param motorDirection The direction of the given motor to move + * @param speed The speed the motor is to move + */ +void MotorHandler::motorCommand(string motor, string motorDirection, string speed){ + char motorID = interpretMotor(motor); + char Direction = interpretDirection(motorDirection, int(motorID)); + char Speed = (char) atol(speed); + move(Direction, speed, "Move Motor"); +} + +char MotorHandler::interpretMotor(string motor){ + if(motor.compare(MOTOR_LEFT) == 0){ + return MOTOR_LEFT_CHAR; + } + else{ + return MOTOR_RIGHT_CHAR; + } +} + +char MotorHandler::interpretDirection(string direction, int motor){ + if(direction.compare(MOTOR_FORWARD) == 0){ + return (char) (motor*2 + 1); + } + else{ + return (char) (motor*2); + } +} + +// MOTOR CONTROL + +/*Moves the given motor in specified direction by Motor Direction with specified + * Speed + * @param MotorDirection Motor and direction to move + * @param Speed the speed to move at + * @param string description of motor movement + */ + +void MotorHandler::move(char MotorDirection,char Speed,char * Description){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_DEVICE_TYPE, "device"); + send(MotorDirection, Description); + send(Speed, "speed"); + printf("\n"); +} + +// MOTOR CONTROL HELPERS +/* + * Sends a byte-length message to the motor controller. + * @param message - the message to send + * @param description - the string description of the message, for debugging + */ +void MotorHandler::send(char message, char *description) { + alt_u32 write_space; + // Check for write space. + write_space = alt_up_rs232_get_available_space_in_write_FIFO(motor_dev); + if (write_space >= WRITE_FIFO_EMPTY) { + // If space, write. + int status = alt_up_rs232_write_data(motor_dev, message); + printf("MotorHandler [message: 0x%02x, description: %s", message, description); + // Log errors. + if (status == OK) { + printf("]\n"); + } else { + printf(", error: cannot write]\n"); + } + } else { + // If no space, wait and retry. + printf("MotorHandler [message: 0x%02x, description: %s, error: no write space; retrying]\n", message, description); + OSTimeDlyHMSM(0, 0, 0, 10); + send(message, description); + } +} + +void MotorHandler::reset(){ + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 0); + OSTimeDlyHMSM(0, 0, 0,200 ); + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 1); + OSTimeDlyHMSM(0, 0, 0, 200); +} diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/f8/b087af2a8aab001311dbfe770f133bca b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/f8/b087af2a8aab001311dbfe770f133bca new file mode 100644 index 00000000..60e0dcab --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/f8/b087af2a8aab001311dbfe770f133bca @@ -0,0 +1,150 @@ +/* + * MotorHandler.cpp + * + * Created on: 2014-03-03 + * Author: Amshu Gongal + */ + + +#include + +#include "altera_avalon_pio_regs.h" +#include "includes.h" +#include "system.h" + +#include "MotorHandler.h" + +#define WRITE_FIFO_EMPTY 0x80 +#define MOTOR_ENABLE 1 +#define MOTOR_RESET 0 + +// ALLOCATION +MotorHandler::MotorHandler() {} +MotorHandler::~MotorHandler() {} + +// INITIALIZATION + +/* + * Initializes this handler. + * @return OK if the handler was initialized without error + */ +Status MotorHandler::init() { + // Enable the motor controller. + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, MOTOR_ENABLE); + // Open the serial device to send commands to the motor controller. + motor_dev = alt_up_rs232_open_dev(RS232_MOTOR_NAME); + //printf("%d", motor_dev); + if (motor_dev == NULL) { + return ERR_MOTOR_OPEN; + } else { + return OK; + } +} + +void MotorHandler::configure(){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_CHANGE_CONFIGURATION, "change configuration"); + send(0X01, "2 MOTOR CONFIG"); + printf("\n"); +} +// TESTING + +void MotorHandler::test() { + send(MOTOR_START_BYTE, "test start"); +} + +// MOTOR CONTROL + +/* + * Move rover forward by activating both motors. + */ +void MotorHandler::forward() { + move(MOTOR_MOTOR1_FORWARD, "motor 1 forward"); + move(MOTOR_MOTOR2_FORWARD, "motor 2 forward"); +} + +/* + * Move rover backward by activating both motor backwards. + */ +void MotorHandler::backward() { + move(MOTOR_MOTOR1_BACKWARD, "motor 1 backward"); + move(MOTOR_MOTOR2_BACKWARD, "motor 2 backward"); +} + +/* + * Turn rover left. + */ +void MotorHandler::left() { + move(MOTOR_MOTOR2_FORWARD, "motor 1 forward"); +} + +/* + * Turn rover right. + */ +void MotorHandler::right() { + move(MOTOR_MOTOR2_FORWARD, "motor 2 forward"); +} + +/* + * Stop the rover. + */ +void MotorHandler::stop() { + move(MOTOR_MOTOR1_FORWARD, MOTOR_STOP_SPEED, "motor 1 stop"); + move(MOTOR_MOTOR2_FORWARD, MOTOR_STOP_SPEED, "motor 2 stop"); +} + +// MOTOR CONTROL HELPERS + +/* + * Moves in the given direction at constant speed. + * @param direction - the motor and direction to move in, e.g. MOTOR_MOTOR1_FORWARD + * @param description - the string description of the movement, for debugging + */ +void MotorHandler::move(char direction, char *description) { + move(direction, MOTOR_CONST_SPEED, description); +} + +/* + * Moves in the given direction and speed. + * @param direction - the motor and direction to move in, e.g. MOTOR_MOTOR1_FORWARD + * @param speed - the speed to move at, i.e. MOTOR_CONST_SPEED or MOTOR_STOP_SPEED + * @param description - the string description of the movement, for debugging + */ +void MotorHandler::move(char direction, char speed, char *description) { + send(MOTOR_START_BYTE, "start"); + send(MOTOR_DEVICE_TYPE, "device"); + send(direction, description); + send(speed, "speed"); + printf("\n"); +} + +/* + * Sends a byte-length message to the motor controller. + * @param message - the message to send + * @param description - the string description of the message, for debugging + */ +void MotorHandler::send(char message, char *description) { + alt_u32 write_space; + // Check for write space. + write_space = alt_up_rs232_get_available_space_in_write_FIFO(motor_dev); + if (write_space >= WRITE_FIFO_EMPTY) { + // If space, write. + int status = alt_up_rs232_write_data(motor_dev, message); + printf("MotorHandler [message: 0x%02x, description: %s", message, description); + // Log errors. + if (status == OK) { + printf("]\n"); + } else { + printf(", error: cannot write]\n"); + } + } else { + // If no space, wait and retry. + printf("MotorHandler [message: 0x%02x, description: %s, error: no write space; retrying]\n", message, description); + OSTimeDlyHMSM(0, 0, 0, 10); + send(message, description); + } +} + +void MotorHandler::reset(){ + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 1); +} diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/f8/f07459e08faf0013110bf3236575307b b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/f8/f07459e08faf0013110bf3236575307b new file mode 100644 index 00000000..898881b9 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/f8/f07459e08faf0013110bf3236575307b @@ -0,0 +1,153 @@ +/* + * MotorHandler.cpp + * + * Created on: 2014-03-03 + * Author: Amshu Gongal + */ + + +#include + +#include "altera_avalon_pio_regs.h" +#include "includes.h" +#include "system.h" + +#include "MotorHandler.h" + +#define WRITE_FIFO_EMPTY 0x80 +#define MOTOR_ENABLE 1 +#define MOTOR_RESET 0 + +// ALLOCATION +MotorHandler::MotorHandler() {} +MotorHandler::~MotorHandler() {} + +// INITIALIZATION + +/* + * Initializes this handler. + * @return OK if the handler was initialized without error + */ +Status MotorHandler::init() { + // Enable the motor controller. + reset(); + // Open the serial device to send commands to the motor controller. + motor_dev = alt_up_rs232_open_dev(RS232_MOTOR_NAME); + //printf("%d", motor_dev); + if (motor_dev == NULL) { + return ERR_MOTOR_OPEN; + } else { + return OK; + } +} + +void MotorHandler::configure(){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_CHANGE_CONFIGURATION, "change configuration"); + send(0X01, "2 MOTOR CONFIG"); + printf("\n"); +} +// TESTING + +void MotorHandler::test() { + send(MOTOR_START_BYTE, "test start"); +} + +// MOTOR CONTROL + +/* + * Move rover forward by activating both motors. + */ +void MotorHandler::forward() { + move(MOTOR_MOTOR1_FORWARD, "motor 1 forward"); + move(MOTOR_MOTOR2_FORWARD, "motor 2 forward"); +} + +/* + * Move rover backward by activating both motor backwards. + */ +void MotorHandler::backward() { + move(MOTOR_MOTOR1_BACKWARD, "motor 1 backward"); + move(MOTOR_MOTOR2_BACKWARD, "motor 2 backward"); +} + +/* + * Turn rover left. + */ +void MotorHandler::left() { + move(MOTOR_MOTOR1_FORWARD, "motor 1 forward"); +} + +/* + * Turn rover right. + */ +void MotorHandler::right() { + move(MOTOR_MOTOR2_FORWARD, "motor 2 forward"); +} + +/* + * Stop the rover. + */ +void MotorHandler::stop() { + move(MOTOR_MOTOR1_FORWARD, MOTOR_STOP_SPEED, "motor 1 stop"); + move(MOTOR_MOTOR2_FORWARD, MOTOR_STOP_SPEED, "motor 2 stop"); +} + +// MOTOR CONTROL HELPERS + +/* + * Moves in the given direction at constant speed. + * @param direction - the motor and direction to move in, e.g. MOTOR_MOTOR1_FORWARD + * @param description - the string description of the movement, for debugging + */ +void MotorHandler::move(char direction, char *description) { + move(direction, MOTOR_CONST_SPEED, description); +} + +/* + * Moves in the given direction and speed. + * @param direction - the motor and direction to move in, e.g. MOTOR_MOTOR1_FORWARD + * @param speed - the speed to move at, i.e. MOTOR_CONST_SPEED or MOTOR_STOP_SPEED + * @param description - the string description of the movement, for debugging + */ +void MotorHandler::move(char direction, char speed, char *description) { + send(MOTOR_START_BYTE, "start"); + send(MOTOR_DEVICE_TYPE, "device"); + send(direction, description); + send(speed, "speed"); + printf("\n"); +} + +/* + * Sends a byte-length message to the motor controller. + * @param message - the message to send + * @param description - the string description of the message, for debugging + */ +void MotorHandler::send(char message, char *description) { + alt_u32 write_space; + // Check for write space. + write_space = alt_up_rs232_get_available_space_in_write_FIFO(motor_dev); + if (write_space >= WRITE_FIFO_EMPTY) { + // If space, write. + int status = alt_up_rs232_write_data(motor_dev, message); + printf("MotorHandler [message: 0x%02x, description: %s", message, description); + // Log errors. + if (status == OK) { + printf("]\n"); + } else { + printf(", error: cannot write]\n"); + } + } else { + // If no space, wait and retry. + printf("MotorHandler [message: 0x%02x, description: %s, error: no write space; retrying]\n", message, description); + OSTimeDlyHMSM(0, 0, 0, 10); + send(message, description); + } +} + +void MotorHandler::reset(){ + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 0); + OSTimeDlyHMSM(0, 0, 0,200 ); + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 1); + OSTimeDlyHMSM(0, 0, 0, 200); +} diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/fa/802150f28ab000131eb0f6c547a05c39 b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/fa/802150f28ab000131eb0f6c547a05c39 new file mode 100644 index 00000000..1a9492d7 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/fa/802150f28ab000131eb0f6c547a05c39 @@ -0,0 +1,136 @@ +/* + * MotorHandler.cpp + * + * Created on: 2014-03-03 + * Author: Amshu Gongal + */ + + +#include +#include + +#include "altera_avalon_pio_regs.h" +#include "includes.h" +#include "system.h" + +#include "MotorHandler.h" + +#define WRITE_FIFO_EMPTY 0x80 +#define MOTOR_ENABLE 1 +#define MOTOR_RESET 0 + +// ALLOCATION +MotorHandler::MotorHandler() {} +MotorHandler::~MotorHandler() {} + + +// INITIALIZATION + +/* + * Initializes this handler. + * @return OK if the handler was initialized without error + */ +Status MotorHandler::init() { + // Enable the motor controller. + reset(); + // Open the serial device to send commands to the motor controller. + motor_dev = alt_up_rs232_open_dev(RS232_MOTOR_NAME); + //printf("%d", motor_dev); + if (motor_dev == NULL) { + return ERR_MOTOR_OPEN; + } else { + return OK; + } +} + +void MotorHandler::configure(){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_CHANGE_CONFIGURATION, "change configuration"); + send(0X01, "2 MOTOR CONFIG"); + printf("\n"); +} + +//Command Interpreter +/* + * Interprets the command from the network handler and sends move commands + * @param motor The motor to move eg. Left or Right + * @param motorDirection The direction of the given motor to move + * @param speed The speed the motor is to move + */ +void MotorHandler::motorCommand(string motor, string motorDirection, string speed){ + char motorID = interpretMotor(motor); + char directionByte = interpretDirection(motorDirection, int(motorID)); + int speedByte = strtol(speed.c_str(), NULL, 0); + move(directionByte, speedByte, motor.append(motorDirection)); +} + + +char MotorHandler::interpretMotor(string motor){ + if(motor.compare(MOTOR_LEFT) == 0){ + return MOTOR_LEFT_CHAR; + } + else{ + return MOTOR_RIGHT_CHAR; + } +} + +char MotorHandler::interpretDirection(string direction, int motor){ + if(direction.compare(MOTOR_FORWARD) == 0){ + return (char) (motor*2 + 1); + } + else{ + return (char) (motor*2); + } +} + +// MOTOR CONTROL + +/*Moves the given motor in specified direction by Motor Direction with specified + * Speed + * @param MotorDirection Motor and direction to move + * @param Speed the speed to move at + * @param string description of motor movement + */ + +void MotorHandler::move(char motorDirection, char speed, char *description){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_DEVICE_TYPE, "device"); + send(motorDirection, description); + send(speed, "speed"); + printf("\n"); +} + +// MOTOR CONTROL HELPERS +/* + * Sends a byte-length message to the motor controller. + * @param message - the message to send + * @param description - the string description of the message, for debugging + */ +void MotorHandler::send(char message, char *description) { + alt_u32 write_space; + // Check for write space. + write_space = alt_up_rs232_get_available_space_in_write_FIFO(motor_dev); + if (write_space >= WRITE_FIFO_EMPTY) { + // If space, write. + int status = alt_up_rs232_write_data(motor_dev, message); + printf("MotorHandler [message: 0x%02x, description: %s", message, description); + // Log errors. + if (status == OK) { + printf("]\n"); + } else { + printf(", error: cannot write]\n"); + } + } else { + // If no space, wait and retry. + printf("MotorHandler [message: 0x%02x, description: %s, error: no write space; retrying]\n", message, description); + OSTimeDlyHMSM(0, 0, 0, 10); + send(message, description); + } +} + +void MotorHandler::reset(){ + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 0); + OSTimeDlyHMSM(0, 0, 0,200 ); + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 1); + OSTimeDlyHMSM(0, 0, 0, 200); +} diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/fb/30a25d7eb6ab00131274ac4b6fee418c b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/fb/30a25d7eb6ab00131274ac4b6fee418c new file mode 100644 index 00000000..c63be517 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/fb/30a25d7eb6ab00131274ac4b6fee418c @@ -0,0 +1,145 @@ +/************************************************************************* + * ARCap + * Amshu Gongal, Kenan Kigunda + * February 18, 2014 + ************************************************************************** + * Description: * + * Prototype testing for infrared and mc. + **************************************************************************/ + +#include +#include "includes.h" +#include "altera_avalon_pio_regs.h" +#include "altera_avalon_uart_regs.h" +#include "sys/alt_irq.h" +#include "alt_types.h" +#include "altera_up_avalon_rs232.h" +#include "altera_up_avalon_rs232_regs.h" + +#include "MotorHandler.h" +#include "Status.h" + +/* Task stacks */ +#define TASK_STACKSIZE 2048 +OS_STK ir_task_stk[TASK_STACKSIZE]; +OS_STK mc_task_stk[TASK_STACKSIZE]; +/* Task priorities */ +#define IR_TASK_PRIORITY 2 +#define MC_TASK_PRIORITY 1 + + +#define SW_READ 1 +#define SW_WRITE 2 +#define WRITE_FIFO_EMPTY 0x80 +#define READ_FIFO_EMPTY 0x0 +OS_EVENT *SWQ; +OS_EVENT *RS232Q; +INT8U err; + + +/* Error status */ +#define OK 0 + +/* Message queues */ +#define WAIT_FOREVER 0 + +// ==== INFRARED ==== + +/* Infrared message queue */ +#define IR_MAX_MESSAGES 4 +int ir_messages[IR_MAX_MESSAGES]; +OS_EVENT *ir_queue; + +/* Infrared messages */ +// Together these avoid passing 0 to the queue (which is not allowed since queue messages cannot be null) +// and invert pushbutton input (since the pushbutton returns 0 when it is pushed down). +#define IR_QUEUE_SEND_BASE 1 // Use: IR_QUEUE_SEND_BASE + IORD +#define IR_QUEUE_RECEIVE_BASE 2 // Use: IR_QUEUE_RECEIVE_BASE - OSQPend + + +MotorHandler *motor= new MotorHandler(); + + +// ==== mc + +#define mc_GUARD_TIME 1 + +void mc_task(void *pdata) +{ + printf("mc task\n"); + printf("MotorHandler [init"); + if (motor->init() == OK) { + printf("]\n\n"); + motor->forward(); + } else { + printf( ", error]\n"); + } + while(1){ + motor->forward(); + + } +} + + + +// ==== GENERAL + +void queue_init() { + ir_queue = OSQCreate((void**)&ir_messages, IR_MAX_MESSAGES); +} + +/* The main function creates the LCD task, registers the edge counter polling interrupt, + * and starts the OS. */ +int main(void) +{ + int status = OK; + // Initialize components. + queue_init(); + // Create the mc task. + OSTaskCreateExt(mc_task, + NULL, + &mc_task_stk[TASK_STACKSIZE - 1], + MC_TASK_PRIORITY, + MC_TASK_PRIORITY, + mc_task_stk, + TASK_STACKSIZE, + NULL, + 0); + + if (status == OK) { + OSStart(); + } + + return 0; +} + +/****************************************************************************** + * * + * License Agreement * + * * + * Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * + * All rights reserved. * + * * + * Permission is hereby granted, free of charge, to any person obtaining a * + * copy of this software and associated documentation files (the "Software"), * + * to deal in the Software without restriction, including without limitation * + * the rights to use, copy, modify, merge, publish, distribute, sublicense, * + * and/or sell copies of the Software, and to permit persons to whom the * + * Software is furnished to do so, subject to the following conditions: * + * * + * The above copyright notice and this permission notice shall be included in * + * all copies or substantial portions of the Software. * + * * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * + * DEALINGS IN THE SOFTWARE. * + * * + * This agreement shall be governed in all respects by the laws of the State * + * of California and by the laws of the United States of America. * + * Altera does not recommend, suggest or require that this reference design * + * file be used in conjunction or combination with any other product. * + ******************************************************************************/ diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/fd/80ecaa098aab001311dbfe770f133bca b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/fd/80ecaa098aab001311dbfe770f133bca new file mode 100644 index 00000000..b12b44c8 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/fd/80ecaa098aab001311dbfe770f133bca @@ -0,0 +1,143 @@ +/************************************************************************* + * ARCap + * Amshu Gongal, Kenan Kigunda + * February 18, 2014 + ************************************************************************** + * Description: * + * Prototype testing for infrared and mc. + **************************************************************************/ + +#include +#include "includes.h" +#include "altera_avalon_pio_regs.h" +#include "altera_avalon_uart_regs.h" +#include "sys/alt_irq.h" +#include "alt_types.h" +#include "altera_up_avalon_rs232.h" +#include "altera_up_avalon_rs232_regs.h" + +#include "MotorHandler.h" +#include "Status.h" + +/* Task stacks */ +#define TASK_STACKSIZE 2048 +OS_STK ir_task_stk[TASK_STACKSIZE]; +OS_STK mc_task_stk[TASK_STACKSIZE]; +/* Task priorities */ +#define IR_TASK_PRIORITY 2 +#define MC_TASK_PRIORITY 1 + + +#define SW_READ 1 +#define SW_WRITE 2 +#define WRITE_FIFO_EMPTY 0x80 +#define READ_FIFO_EMPTY 0x0 +OS_EVENT *SWQ; +OS_EVENT *RS232Q; +INT8U err; + + +/* Error status */ +#define OK 0 + +/* Message queues */ +#define WAIT_FOREVER 0 + +// ==== INFRARED ==== + +/* Infrared message queue */ +#define IR_MAX_MESSAGES 4 +int ir_messages[IR_MAX_MESSAGES]; +OS_EVENT *ir_queue; + +/* Infrared messages */ +// Together these avoid passing 0 to the queue (which is not allowed since queue messages cannot be null) +// and invert pushbutton input (since the pushbutton returns 0 when it is pushed down). +#define IR_QUEUE_SEND_BASE 1 // Use: IR_QUEUE_SEND_BASE + IORD +#define IR_QUEUE_RECEIVE_BASE 2 // Use: IR_QUEUE_RECEIVE_BASE - OSQPend + + +MotorHandler *motor= new MotorHandler(); + + +// ==== mc + +#define mc_GUARD_TIME 1 + +void mc_task(void *pdata) +{ + printf("mc task\n"); + printf("MotorHandler [init"); + if (motor->init() == OK) { + printf("]\n\n"); + motor->configure(); + } else { + printf( ", error]\n"); + } + motor->forward(); +} + + + +// ==== GENERAL + +void queue_init() { + ir_queue = OSQCreate((void**)&ir_messages, IR_MAX_MESSAGES); +} + +/* The main function creates the LCD task, registers the edge counter polling interrupt, + * and starts the OS. */ +int main(void) +{ + int status = OK; + // Initialize components. + queue_init(); + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 1); + // Create the mc task. + OSTaskCreateExt(mc_task, + NULL, + &mc_task_stk[TASK_STACKSIZE - 1], + MC_TASK_PRIORITY, + MC_TASK_PRIORITY, + mc_task_stk, + TASK_STACKSIZE, + NULL, + 0); + + if (status == OK) { + OSStart(); + } + + return 0; +} + +/****************************************************************************** + * * + * License Agreement * + * * + * Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * + * All rights reserved. * + * * + * Permission is hereby granted, free of charge, to any person obtaining a * + * copy of this software and associated documentation files (the "Software"), * + * to deal in the Software without restriction, including without limitation * + * the rights to use, copy, modify, merge, publish, distribute, sublicense, * + * and/or sell copies of the Software, and to permit persons to whom the * + * Software is furnished to do so, subject to the following conditions: * + * * + * The above copyright notice and this permission notice shall be included in * + * all copies or substantial portions of the Software. * + * * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * + * DEALINGS IN THE SOFTWARE. * + * * + * This agreement shall be governed in all respects by the laws of the State * + * of California and by the laws of the United States of America. * + * Altera does not recommend, suggest or require that this reference design * + * file be used in conjunction or combination with any other product. * + ******************************************************************************/ diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/ff/1016f66b87b000131eb0f6c547a05c39 b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/ff/1016f66b87b000131eb0f6c547a05c39 new file mode 100644 index 00000000..cc12705f --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/ff/1016f66b87b000131eb0f6c547a05c39 @@ -0,0 +1,73 @@ +/* + * MotorHandler.h + * + * Created on: 2014-03-03 + * Author: Amshu Gongal + */ + +#ifndef MOTORHANDLER_H_ +#define MOTORHANDLER_H_ + +#include "altera_up_avalon_rs232.h" +#include "altera_up_avalon_rs232_regs.h" +#include +using namespace std; +#include +#include "Status.h" + +//Commands from network handler +#define MOTOR_LEFT "left" +#define MOTOR_RIGHT "right" +#define MOTOR_FORWARD "forward" +#define MOTOR_BACKWARD "backward" + + +// Motor messages are LSB first +#define MOTOR_START_BYTE 0x80 +#define MOTOR_DEVICE_TYPE 0x00 +#define MOTOR_LEFT_BACKWARD 0x04 // motor 1 backward +#define MOTOR_RIGHT_BACKWARD 0x06 // motor 2 backward +#define MOTOR_LEFT_FORWARD 0x05 // motor 1 forward +#define MOTOR_RIGHT_FORWARD 0x07 // motor 2 forward +#define MOTOR_CONST_SPEED 0x5F +#define MOTOR_STOP_SPEED 0x00 +#define MOTOR_CHANGE_CONFIGURATION 0X02 + +class MotorHandler { +public: + MotorHandler(); + virtual ~MotorHandler(); + + /* + * Initializes this handler. + * @return OK if the handler was initialized without error + */ + Status init(); + void reset(); + void configure(); + void motorCommand(string motor, string motorDirection, string speed); + +private: + /* The device used to send serial commands to the motor controller. */ + alt_up_rs232_dev *motor_dev; + + char interpretMotor(string motor); + char interpretDirection(string direction, int motor); + + /* + * Moves in the given direction at constant speed. + * @param direction - the motor and direction to move in, e.g. MOTOR_MOTOR1_FORWARD + * @param speed speed of the motor + * @param description - the string description of the movement, for debugging + */ + void move(char direction, char speed, char *description); + + /* + * Sends a byte-length message to the motor controller. + * @param message - the message to send + * @param description - the string description of the message, for debugging + */ + void send(char message, char *description); +}; + +#endif /* MOTORHANDLER_H_ */ diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/ff/a0b2d6008bb000131eb0f6c547a05c39 b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/ff/a0b2d6008bb000131eb0f6c547a05c39 new file mode 100644 index 00000000..4289b2ef --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.history/ff/a0b2d6008bb000131eb0f6c547a05c39 @@ -0,0 +1,73 @@ +/* + * MotorHandler.h + * + * Created on: 2014-03-03 + * Author: Amshu Gongal + */ + +#ifndef MOTORHANDLER_H_ +#define MOTORHANDLER_H_ + +#include "altera_up_avalon_rs232.h" +#include "altera_up_avalon_rs232_regs.h" +#include +using namespace std; +#include +#include "Status.h" + +//Commands from network handler +#define MOTOR_LEFT "left" +#define MOTOR_RIGHT "right" +#define MOTOR_FORWARD "forward" +#define MOTOR_BACKWARD "backward" + + +// Motor messages are LSB first +#define MOTOR_START_BYTE 0x80 +#define MOTOR_DEVICE_TYPE 0x00 +#define MOTOR_LEFT_CHAR 0x02 // motor 1 backward +#define MOTOR_RIGHT_CHAR 0x03 // motor 2 backward +#define MOTOR_LEFT_FORWARD 0x05 // motor 1 forward +#define MOTOR_RIGHT_FORWARD 0x07 // motor 2 forward +#define MOTOR_CONST_SPEED 0x5F +#define MOTOR_STOP_SPEED 0x00 +#define MOTOR_CHANGE_CONFIGURATION 0X02 + +class MotorHandler { +public: + MotorHandler(); + virtual ~MotorHandler(); + + /* + * Initializes this handler. + * @return OK if the handler was initialized without error + */ + Status init(); + void reset(); + void configure(); + void motorCommand(string motor, string motorDirection, string speed); + +private: + /* The device used to send serial commands to the motor controller. */ + alt_up_rs232_dev *motor_dev; + + char interpretMotor(string motor); + char interpretDirection(string direction, int motor); + + /* + * Moves in the given direction at constant speed. + * @param direction - the motor and direction to move in, e.g. MOTOR_MOTOR1_FORWARD + * @param speed speed of the motor + * @param description - the string description of the movement, for debugging + */ + void move(char direction, char speed, string description); + + /* + * Sends a byte-length message to the motor controller. + * @param message - the message to send + * @param description - the string description of the message, for debugging + */ + void send(char message, char *description); +}; + +#endif /* MOTORHANDLER_H_ */ diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.projects/MCTest/.indexes/history.index b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.projects/MCTest/.indexes/history.index new file mode 100644 index 00000000..a7b8dcda Binary files /dev/null and b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.resources/.projects/MCTest/.indexes/history.index differ diff --git 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b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.runtime/.settings/com.altera.sbtgui.ui.prefs @@ -0,0 +1,4 @@ +eclipse.preferences.version=1 +newSoftwareExampleWizardPage.defaultLocation=C\:\\Users\\gongal\\Desktop\\MCTEST\\DE0-nano-HD\\software\\MCTest +newSoftwareExampleWizardPage.sopcinfoFile=C\:\\Users\\gongal\\Desktop\\MCTEST\\DE0-nano-HD\\system.sopcinfo +newSoftwareExampleWizardPage2.newBspLocation=C\:\\Users\\gongal\\Desktop\\MCTEST\\DE0-nano-HD\\software\\MCTest_bsp diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.codan.core.prefs b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.codan.core.prefs new file mode 100644 index 00000000..a4367a1a --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.codan.core.prefs @@ -0,0 +1,65 @@ +eclipse.preferences.version=1 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2014\\r\\nrebuildState\\\=true\\r\\n\r\naltera.nios2.mingw.gcc4.382324477\=\\\#\\r\\n\\\#Thu Mar 20 18\\\:11\\\:58 MDT 2014\\r\\nrebuildState\\\=false\\r\\n\r\ncdt.managedbuild.tool.gnu.c.compiler.cygwin.base.549290588\=\\\#\\r\\n\\\#Thu Mar 20 18\\\:11\\\:58 MDT 2014\\r\\nrebuildState\\\=false\\r\\n\r\n diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.mylyn.ui.prefs b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.mylyn.ui.prefs new file mode 100644 index 00000000..0451f542 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.mylyn.ui.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +org.eclipse.mylyn.cdt.ui.run.count.3_3_0=1 diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.ui.prefs b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.ui.prefs new file mode 100644 index 00000000..bd28f849 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.ui.prefs @@ -0,0 +1,6 @@ +content_assist_disabled_computers=org.eclipse.cdt.ui.parserProposalCategory\u0000org.eclipse.cdt.ui.textProposalCategory\u0000 +eclipse.preferences.version=1 +spelling_locale=en_GB +spelling_locale_initialized=true +useAnnotationsPrefPage=true +useQuickDiffPrefPage=true diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.core.resources.prefs b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.core.resources.prefs new file mode 100644 index 00000000..a7fb09f3 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.core.resources.prefs @@ -0,0 +1,3 @@ +description.autobuilding=false +eclipse.preferences.version=1 +version=1 diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.debug.core.prefs b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.debug.core.prefs new file mode 100644 index 00000000..2d3da00a --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.debug.core.prefs @@ -0,0 +1,7 @@ +//org.eclipse.debug.core.PREFERRED_DELEGATES/org.eclipse.cdt.launch.applicationLaunchType=org.eclipse.cdt.dsf.gdb.launch.localCLaunch,debug;org.eclipse.cdt.cdi.launch.localCLaunch,run +//org.eclipse.debug.core.PREFERRED_DELEGATES/org.eclipse.cdt.launch.attachLaunchType=org.eclipse.cdt.dsf.gdb.launch.attachCLaunch,debug +//org.eclipse.debug.core.PREFERRED_DELEGATES/org.eclipse.cdt.launch.postmortemLaunchType=org.eclipse.cdt.dsf.gdb.launch.coreCLaunch,debug +//org.eclipse.debug.core.PREFERRED_DELEGATES/org.eclipse.cdt.launch.remoteApplicationLaunchType=org.eclipse.rse.remotecdt.dsf.debug,debug +eclipse.preferences.version=1 +org.eclipse.debug.core.USE_STEP_FILTERS=false +prefWatchExpressions=\r\n\r\n diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.debug.ui.prefs b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.debug.ui.prefs new file mode 100644 index 00000000..0c71d7dc --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.debug.ui.prefs @@ -0,0 +1,5 @@ +eclipse.preferences.version=1 +org.eclipse.debug.ui.PREF_LAUNCH_PERSPECTIVES=\r\n\r\n +pref_state_memento.org.eclipse.debug.ui.DebugVieworg.eclipse.debug.ui.DebugView=\r\n +preferredDetailPanes=DefaultDetailPane\:DefaultDetailPane| +preferredTargets=org.eclipse.cdt.debug.ui.toggleCBreakpointTarget\:org.eclipse.cdt.debug.ui.toggleCBreakpointTarget| diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.epp.usagedata.recording.prefs b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.epp.usagedata.recording.prefs new file mode 100644 index 00000000..497e2e35 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.epp.usagedata.recording.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +org.eclipse.epp.usagedata.recording.last-upload=1395250897361 diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.mylyn.context.core.prefs b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.mylyn.context.core.prefs new file mode 100644 index 00000000..43e97e40 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.mylyn.context.core.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +mylyn.attention.migrated=true diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.mylyn.monitor.ui.prefs b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.mylyn.monitor.ui.prefs new file mode 100644 index 00000000..8d462a6c --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.mylyn.monitor.ui.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +org.eclipse.mylyn.monitor.activity.tracking.enabled.checked=true diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.team.cvs.ui.prefs b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.team.cvs.ui.prefs new file mode 100644 index 00000000..f9e585ba --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.team.cvs.ui.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +pref_first_startup=false diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.team.ui.prefs b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.team.ui.prefs new file mode 100644 index 00000000..56cd496f --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.team.ui.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +org.eclipse.team.ui.first_time=false diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.editors.prefs b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.editors.prefs new file mode 100644 index 00000000..61f3bb8b --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.editors.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +overviewRuler_migration=migrated_3.1 diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.ide.prefs b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.ide.prefs new file mode 100644 index 00000000..a9cf7bfe --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.ide.prefs @@ -0,0 +1,8 @@ +IMPORT_FILES_AND_FOLDERS_RELATIVE=true +IMPORT_FILES_AND_FOLDERS_TYPE=23,1 +PROBLEMS_FILTERS_MIGRATE=true +TASKS_FILTERS_MIGRATE=true +eclipse.preferences.version=1 +platformState=1370561326246 +quickStart=false +tipsAndTricks=true diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.prefs b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.prefs new file mode 100644 index 00000000..08076f23 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +showIntro=false diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.workbench.prefs b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.workbench.prefs new file mode 100644 index 00000000..dc1a5a0b --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.workbench.prefs @@ -0,0 +1,4 @@ +ENABLED_DECORATORS=com.altera.sbtgui.project.decorator.bsp\:true,com.altera.sbtgui.project.nios2builddecorator\:true,org.eclipse.cdt.ui.indexedFiles\:false,org.eclipse.cdt.managedbuilder.ui.excludedFile\:true,org.eclipse.egit.ui.internal.decorators.GitLightweightDecorator\:true,org.eclipse.mylyn.context.ui.decorator.interest\:true,org.eclipse.mylyn.tasks.ui.decorators.task\:true,org.eclipse.mylyn.team.ui.changeset.decorator\:true,org.eclipse.rse.core.virtualobject.decorator\:true,org.eclipse.rse.core.binary.executable.decorator\:true,org.eclipse.rse.core.script.executable.decorator\:true,org.eclipse.rse.core.java.executable.decorator\:true,org.eclipse.rse.core.library.decorator\:true,org.eclipse.rse.core.link.decorator\:true,org.eclipse.rse.subsystems.error.decorator\:true,org.eclipse.team.cvs.ui.decorator\:true,org.eclipse.ui.LinkedResourceDecorator\:true,org.eclipse.ui.VirtualResourceDecorator\:true,org.eclipse.ui.ContentTypeDecorator\:true,org.eclipse.ui.ResourceFilterDecorator\:false, +UIActivities.org.eclipse.cdt.debug.cdigdbActivity=true +UIActivities.org.eclipse.cdt.debug.dsfgdbActivity=true +eclipse.preferences.version=1 diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.debug.core/.launches/MCTest.elf.launch b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.debug.core/.launches/MCTest.elf.launch new file mode 100644 index 00000000..dd9e8254 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.debug.core/.launches/MCTest.elf.launch @@ -0,0 +1,17 @@ + + + + + + + + + + + + + + + + + diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.debug.core/.launches/New_configuration.launch b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.debug.core/.launches/New_configuration.launch new file mode 100644 index 00000000..5e057436 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.debug.core/.launches/New_configuration.launch @@ -0,0 +1,20 @@ + + + + + + + + + + + + + + + + + + + + diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.debug.ui/dialog_settings.xml b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.debug.ui/dialog_settings.xml new file mode 100644 index 00000000..eaa04965 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.debug.ui/dialog_settings.xml @@ -0,0 +1,11 @@ + +
+
+ + + + + + +
+
diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.debug.ui/launchConfigurationHistory.xml b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.debug.ui/launchConfigurationHistory.xml new file mode 100644 index 00000000..495ab682 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.debug.ui/launchConfigurationHistory.xml @@ -0,0 +1,25 @@ + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.epp.usagedata.recording/upload0.csv b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.epp.usagedata.recording/upload0.csv new file mode 100644 index 00000000..2842d3ea --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.epp.usagedata.recording/upload0.csv @@ -0,0 +1,276 @@ +what,kind,bundleId,bundleVersion,description,time +activated,perspective,com.altera.sbtgui.ui,,"com.altera.sbtgui.ui.cPerspective",1394125246935 +started,bundle,org.eclipse.osgi,3.7.2.v20120110-1415,"org.eclipse.osgi",1394125246936 +started,bundle,org.eclipse.equinox.simpleconfigurator,1.0.200.v20110815-1438,"org.eclipse.equinox.simpleconfigurator",1394125246936 +started,bundle,com.ibm.icu,4.4.2.v20110823,"com.ibm.icu",1394125246936 +started,bundle,org.eclipse.cdt.codan.checkers,1.0.1.201202111925,"org.eclipse.cdt.codan.checkers",1394125246937 +started,bundle,org.eclipse.cdt.codan.core,2.0.0.201202111925,"org.eclipse.cdt.codan.core",1394125246937 +started,bundle,org.eclipse.cdt.codan.core.cxx,1.0.0.201202111925,"org.eclipse.cdt.codan.core.cxx",1394125246937 +started,bundle,org.eclipse.cdt.codan.ui.cxx,2.0.0.201202111925,"org.eclipse.cdt.codan.ui.cxx",1394125246937 +started,bundle,org.eclipse.cdt.core,5.3.2.201202111925,"org.eclipse.cdt.core",1394125246938 +started,bundle,org.eclipse.cdt.make.core,7.1.2.201202111925,"org.eclipse.cdt.make.core",1394125246938 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+started,bundle,org.eclipse.core.net,1.2.100.I20110511-0800,"org.eclipse.core.net",1394125246943 +started,bundle,org.eclipse.core.resources,3.7.101.v20120125-1505,"org.eclipse.core.resources",1394125246943 +started,bundle,org.eclipse.core.runtime,3.7.0.v20110110,"org.eclipse.core.runtime",1394125246944 +started,bundle,org.eclipse.core.runtime.compatibility,3.2.100.v20100505,"org.eclipse.core.runtime.compatibility",1394125246944 +started,bundle,org.eclipse.core.runtime.compatibility.auth,3.2.200.v20110110,"org.eclipse.core.runtime.compatibility.auth",1394125246944 +started,bundle,org.eclipse.debug.core,3.7.1.v20111129-2031,"org.eclipse.debug.core",1394125246945 +started,bundle,org.eclipse.egit.core,1.3.0.201202151440-r,"org.eclipse.egit.core",1394125246945 +started,bundle,org.eclipse.egit.ui,1.3.0.201202151440-r,"org.eclipse.egit.ui",1394125246946 +started,bundle,org.eclipse.epp.mpc.ui,1.1.1.I20110907-0947,"org.eclipse.epp.mpc.ui",1394125246946 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+stopped,bundle,org.eclipse.cdt.msw.build,1.0.0.201202111925,"org.eclipse.cdt.msw.build",1395361764770 +stopped,bundle,org.eclipse.cdt.managedbuilder.core,8.0.2.201202111925,"org.eclipse.cdt.managedbuilder.core",1395361764770 +stopped,bundle,org.eclipse.cdt.make.core,7.1.2.201202111925,"org.eclipse.cdt.make.core",1395361764770 +stopped,bundle,org.eclipse.cdt.mylyn.ui,3.6.0.v20110608-1400,"org.eclipse.cdt.mylyn.ui",1395361764770 +stopped,bundle,org.eclipse.cdt.codan.ui,2.0.1.201202111925,"org.eclipse.cdt.codan.ui",1395361764770 diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/.workspace/2014/3/10/refactorings.history b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/.workspace/2014/3/10/refactorings.history new file mode 100644 index 00000000..30d6289e --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/.workspace/2014/3/10/refactorings.history @@ -0,0 +1,4 @@ + + + + \ No newline at end of file diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/.workspace/2014/3/10/refactorings.index b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/.workspace/2014/3/10/refactorings.index new file mode 100644 index 00000000..ea8a74ea --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/.workspace/2014/3/10/refactorings.index @@ -0,0 +1 @@ +1394125541216 Delete resource 'MCTest/hello_ucosii.c' diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/MCTest/2014/3/10/refactorings.history b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/MCTest/2014/3/10/refactorings.history new file mode 100644 index 00000000..a854c243 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/MCTest/2014/3/10/refactorings.history @@ -0,0 +1,4 @@ + + + + \ No newline at end of file diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/MCTest/2014/3/10/refactorings.index b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/MCTest/2014/3/10/refactorings.index new file mode 100644 index 00000000..19ec165a --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/MCTest/2014/3/10/refactorings.index @@ -0,0 +1 @@ +1394126340390 Rename resource 'main.c' diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.ltk.ui.refactoring/dialog_settings.xml b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.ltk.ui.refactoring/dialog_settings.xml new file mode 100644 index 00000000..27eb4040 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.ltk.ui.refactoring/dialog_settings.xml @@ -0,0 +1,7 @@ + +
+
+ + +
+
diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.search/dialog_settings.xml b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.search/dialog_settings.xml new file mode 100644 index 00000000..185c38cf --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.search/dialog_settings.xml @@ -0,0 +1,29 @@ + +
+
+ + + + + +
+
+ + + + + + + + + + + + + + +
+
+ +
+
diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.ui.editors/dialog_settings.xml b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.ui.editors/dialog_settings.xml new file mode 100644 index 00000000..50f1edb3 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.ui.editors/dialog_settings.xml @@ -0,0 +1,5 @@ + +
+
+
+
diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.ui.ide/dialog_settings.xml b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.ui.ide/dialog_settings.xml new file mode 100644 index 00000000..fd83f4c8 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.ui.ide/dialog_settings.xml @@ -0,0 +1,12 @@ + +
+
+ + + + + + + +
+
diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.ui.workbench.texteditor/dialog_settings.xml b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.ui.workbench.texteditor/dialog_settings.xml new file mode 100644 index 00000000..ff036516 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.ui.workbench.texteditor/dialog_settings.xml @@ -0,0 +1,24 @@ + +
+
+ + + + + +
+
+ + + + + + + + + + + + +
+
diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.ui.workbench/dialog_settings.xml b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.ui.workbench/dialog_settings.xml new file mode 100644 index 00000000..0aeff155 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.ui.workbench/dialog_settings.xml @@ -0,0 +1,14 @@ + +
+
+ + +
+
+ + + +
+
+
+
diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.ui.workbench/workbench.xml b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.ui.workbench/workbench.xml new file mode 100644 index 00000000..a9f126df --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/.plugins/org.eclipse.ui.workbench/workbench.xml @@ -0,0 +1,633 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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-0,0 +1,4 @@ + + + + \ No newline at end of file diff --git a/MCTEST/DE0-nano-HD/Software/.metadata/version.ini b/MCTEST/DE0-nano-HD/Software/.metadata/version.ini new file mode 100644 index 00000000..c51ff745 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/.metadata/version.ini @@ -0,0 +1 @@ +org.eclipse.core.runtime=1 \ No newline at end of file diff --git a/MCTEST/DE0-nano-HD/Software/MCTest/.cproject b/MCTEST/DE0-nano-HD/Software/MCTest/.cproject new file mode 100644 index 00000000..a8e07771 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/MCTest/.cproject @@ -0,0 +1,508 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + make + + mem_init_install + true + false + false + + + make + + mem_init_generate + true + false + false + + + make + + help + true + false + false + + + + diff --git a/MCTEST/DE0-nano-HD/Software/MCTest/.force_relink b/MCTEST/DE0-nano-HD/Software/MCTest/.force_relink new file mode 100644 index 00000000..e69de29b diff --git a/MCTEST/DE0-nano-HD/Software/MCTest/.project b/MCTEST/DE0-nano-HD/Software/MCTest/.project new file mode 100644 index 00000000..40854e92 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/MCTest/.project @@ -0,0 +1,96 @@ + + + MCTest + + + + + + com.altera.sbtgui.project.makefileBuilder + + + + + com.altera.sbtgui.project.makefileBuilder + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + + + + org.eclipse.cdt.make.core.buildCommand + make + + + org.eclipse.cdt.make.core.buildLocation + ${workspace_loc://MCTest} + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + org.eclipse.cdt.core.ccnature + com.altera.sbtgui.project.SBTGUINature + com.altera.sbtgui.project.SBTGUIAppNature + com.altera.sbtgui.project.SBTGUIManagedNature + + diff --git a/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf b/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf new file mode 100644 index 00000000..0751821a Binary files /dev/null and b/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.elf differ diff --git a/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.map b/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.map new file mode 100644 index 00000000..4b71647c --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.map @@ -0,0 +1,4687 @@ +Archive member included because of file (symbol) + +c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(allocator-inst.o) + obj/default/main.o (std::allocator::allocator()) +c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(string-inst.o) + obj/default/MotorHandler.o (std::string::c_str() const) +c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(atomicity.o) + c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(string-inst.o) (__gnu_cxx::__exchange_and_add(int volatile*, int)) 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(__cxxabiv1::__terminate_handler) +c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(eh_catch.o) + c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(eh_personality.o) (__cxa_end_catch) +c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(del_op.o) + obj/default/MotorHandler.o (operator delete(void*)) +c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(eh_throw.o) + c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(eh_personality.o) (__cxa_rethrow) +c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(si_class_type_info.o) + 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c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-makebuf.o) (_fstat_r) +c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-isattyr.o) + c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-makebuf.o) (_isatty_r) +c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-lseekr.o) + c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-stdio.o) (_lseek_r) +c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-readr.o) + c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-stdio.o) (_read_r) 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+c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_clz.o) + c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_udivdi3.o) (__clz_tab) +c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_clzsi2.o) + c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_si_to_df.o) (__clzsi2) +c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_pack_df.o) + c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_addsub_df.o) (__pack_d) +c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_unpack_df.o) + c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_addsub_df.o) (__unpack_d) +c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_fpcmp_parts_df.o) + c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_eq_df.o) (__fpcmp_parts_d) +../MCTest_bsp/\libucosii_bsp.a(alt_close.o) + c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-closer.o) (close) +../MCTest_bsp/\libucosii_bsp.a(alt_dev.o) + ../MCTest_bsp/\libucosii_bsp.a(alt_close.o) (alt_fd_list) +../MCTest_bsp/\libucosii_bsp.a(alt_errno.o) + ../MCTest_bsp/\libucosii_bsp.a(alt_close.o) (alt_errno) +../MCTest_bsp/\libucosii_bsp.a(alt_exit.o) + c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-abort.o) (_exit) +../MCTest_bsp/\libucosii_bsp.a(alt_fstat.o) + c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-fstatr.o) (fstat) +../MCTest_bsp/\libucosii_bsp.a(alt_getpid.o) + c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-signalr.o) (getpid) +../MCTest_bsp/\libucosii_bsp.a(alt_isatty.o) + c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-isattyr.o) (isatty) +../MCTest_bsp/\libucosii_bsp.a(alt_kill.o) + c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-signalr.o) (kill) +../MCTest_bsp/\libucosii_bsp.a(alt_load.o) + ../MCTest_bsp//obj/HAL/src/crt0.o (alt_load) +../MCTest_bsp/\libucosii_bsp.a(alt_lseek.o) + c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-lseekr.o) (lseek) +../MCTest_bsp/\libucosii_bsp.a(alt_main.o) + ../MCTest_bsp//obj/HAL/src/crt0.o (alt_main) +../MCTest_bsp/\libucosii_bsp.a(alt_read.o) + c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-readr.o) (read) +../MCTest_bsp/\libucosii_bsp.a(alt_release_fd.o) + ../MCTest_bsp/\libucosii_bsp.a(alt_close.o) (alt_release_fd) +../MCTest_bsp/\libucosii_bsp.a(alt_sbrk.o) + c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-sbrkr.o) (sbrk) +../MCTest_bsp/\libucosii_bsp.a(alt_write.o) + c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-writer.o) (write) +../MCTest_bsp/\libucosii_bsp.a(alt_env_lock.o) + ../MCTest_bsp/\libucosii_bsp.a(alt_main.o) (alt_envsem) +../MCTest_bsp/\libucosii_bsp.a(alt_malloc_lock.o) + c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-mallocr.o) (__malloc_lock) +../MCTest_bsp/\libucosii_bsp.a(os_core.o) + ../MCTest_bsp/\libucosii_bsp.a(alt_main.o) (OSInit) +../MCTest_bsp/\libucosii_bsp.a(os_dbg.o) + ../MCTest_bsp/\libucosii_bsp.a(os_core.o) (OSDebugInit) +../MCTest_bsp/\libucosii_bsp.a(os_flag.o) + ../MCTest_bsp/\libucosii_bsp.a(os_core.o) (OS_FlagInit) +../MCTest_bsp/\libucosii_bsp.a(os_mem.o) + ../MCTest_bsp/\libucosii_bsp.a(os_core.o) (OS_MemInit) +../MCTest_bsp/\libucosii_bsp.a(os_q.o) + obj/default/main.o (OSQCreate) +../MCTest_bsp/\libucosii_bsp.a(os_sem.o) + ../MCTest_bsp/\libucosii_bsp.a(alt_main.o) (OSSemCreate) +../MCTest_bsp/\libucosii_bsp.a(os_task.o) + obj/default/main.o (OSTaskCreateExt) +../MCTest_bsp/\libucosii_bsp.a(os_time.o) + ../MCTest_bsp/\libucosii_bsp.a(os_core.o) (OSTimeDly) +../MCTest_bsp/\libucosii_bsp.a(alt_sys_init.o) + ../MCTest_bsp/\libucosii_bsp.a(alt_main.o) (alt_irq_init) +../MCTest_bsp/\libucosii_bsp.a(altera_avalon_jtag_uart_fd.o) + ../MCTest_bsp/\libucosii_bsp.a(alt_sys_init.o) (altera_avalon_jtag_uart_read_fd) +../MCTest_bsp/\libucosii_bsp.a(altera_avalon_jtag_uart_init.o) + ../MCTest_bsp/\libucosii_bsp.a(alt_sys_init.o) (altera_avalon_jtag_uart_init) +../MCTest_bsp/\libucosii_bsp.a(altera_avalon_jtag_uart_ioctl.o) + ../MCTest_bsp/\libucosii_bsp.a(altera_avalon_jtag_uart_fd.o) (altera_avalon_jtag_uart_ioctl) +../MCTest_bsp/\libucosii_bsp.a(altera_avalon_jtag_uart_read.o) + ../MCTest_bsp/\libucosii_bsp.a(altera_avalon_jtag_uart_fd.o) (altera_avalon_jtag_uart_read) +../MCTest_bsp/\libucosii_bsp.a(altera_avalon_jtag_uart_write.o) + ../MCTest_bsp/\libucosii_bsp.a(altera_avalon_jtag_uart_fd.o) (altera_avalon_jtag_uart_write) +../MCTest_bsp/\libucosii_bsp.a(altera_avalon_timer_sc.o) + ../MCTest_bsp/\libucosii_bsp.a(alt_sys_init.o) (alt_avalon_timer_sc_init) +../MCTest_bsp/\libucosii_bsp.a(altera_avalon_uart_fd.o) + ../MCTest_bsp/\libucosii_bsp.a(alt_sys_init.o) (altera_avalon_uart_read_fd) +../MCTest_bsp/\libucosii_bsp.a(altera_avalon_uart_init.o) + ../MCTest_bsp/\libucosii_bsp.a(alt_sys_init.o) (altera_avalon_uart_init) +../MCTest_bsp/\libucosii_bsp.a(altera_avalon_uart_read.o) + ../MCTest_bsp/\libucosii_bsp.a(altera_avalon_uart_fd.o) (altera_avalon_uart_read) +../MCTest_bsp/\libucosii_bsp.a(altera_avalon_uart_write.o) + ../MCTest_bsp/\libucosii_bsp.a(altera_avalon_uart_fd.o) (altera_avalon_uart_write) +../MCTest_bsp/\libucosii_bsp.a(altera_up_avalon_rs232.o) + obj/default/MotorHandler.o (alt_up_rs232_get_available_space_in_write_FIFO) +../MCTest_bsp/\libucosii_bsp.a(alt_alarm_start.o) + ../MCTest_bsp/\libucosii_bsp.a(altera_avalon_jtag_uart_init.o) (alt_alarm_start) +../MCTest_bsp/\libucosii_bsp.a(alt_dcache_flush_all.o) + ../MCTest_bsp/\libucosii_bsp.a(alt_load.o) (alt_dcache_flush_all) +../MCTest_bsp/\libucosii_bsp.a(alt_dev_llist_insert.o) + ../MCTest_bsp/\libucosii_bsp.a(alt_sys_init.o) (alt_dev_llist_insert) +../MCTest_bsp/\libucosii_bsp.a(alt_do_ctors.o) + ../MCTest_bsp/\libucosii_bsp.a(alt_main.o) (_do_ctors) +../MCTest_bsp/\libucosii_bsp.a(alt_do_dtors.o) + ../MCTest_bsp/\libucosii_bsp.a(alt_main.o) (_do_dtors) +../MCTest_bsp/\libucosii_bsp.a(alt_find_dev.o) + ../MCTest_bsp/\libucosii_bsp.a(altera_up_avalon_rs232.o) (alt_find_dev) +../MCTest_bsp/\libucosii_bsp.a(alt_icache_flush_all.o) + ../MCTest_bsp/\libucosii_bsp.a(alt_load.o) (alt_icache_flush_all) +../MCTest_bsp/\libucosii_bsp.a(alt_io_redirect.o) + ../MCTest_bsp/\libucosii_bsp.a(alt_main.o) (alt_io_redirect) +../MCTest_bsp/\libucosii_bsp.a(alt_irq_register.o) + ../MCTest_bsp/\libucosii_bsp.a(altera_avalon_jtag_uart_init.o) (alt_irq_register) +../MCTest_bsp/\libucosii_bsp.a(alt_irq_vars.o) + ../MCTest_bsp/\libucosii_bsp.a(alt_irq_register.o) (alt_irq_active) +../MCTest_bsp/\libucosii_bsp.a(alt_open.o) + ../MCTest_bsp/\libucosii_bsp.a(alt_io_redirect.o) (open) +../MCTest_bsp/\libucosii_bsp.a(alt_tick.o) + ../MCTest_bsp/\libucosii_bsp.a(altera_avalon_jtag_uart_init.o) (_alt_tick_rate) +../MCTest_bsp/\libucosii_bsp.a(altera_nios2_qsys_irq.o) + ../MCTest_bsp/\libucosii_bsp.a(alt_sys_init.o) (altera_nios2_qsys_irq_init) +../MCTest_bsp/\libucosii_bsp.a(os_cpu_a.o) + ../MCTest_bsp/\libucosii_bsp.a(os_core.o) (OSIntCtxSw) +../MCTest_bsp/\libucosii_bsp.a(os_cpu_c.o) + ../MCTest_bsp/\libucosii_bsp.a(os_task.o) (OSTaskStkInit) +../MCTest_bsp/\libucosii_bsp.a(alt_find_file.o) + ../MCTest_bsp/\libucosii_bsp.a(alt_open.o) (alt_find_file) +../MCTest_bsp/\libucosii_bsp.a(alt_get_fd.o) + ../MCTest_bsp/\libucosii_bsp.a(alt_open.o) (alt_get_fd) +../MCTest_bsp/\libucosii_bsp.a(alt_icache_flush.o) + ../MCTest_bsp/\libucosii_bsp.a(alt_icache_flush_all.o) (alt_icache_flush) +../MCTest_bsp/\libucosii_bsp.a(alt_irq_entry.o) + ../MCTest_bsp/\libucosii_bsp.a(alt_irq_register.o) (alt_irq_entry) +../MCTest_bsp/\libucosii_bsp.a(alt_irq_handler.o) + ../MCTest_bsp/\libucosii_bsp.a(alt_irq_register.o) (alt_irq_handler) +../MCTest_bsp/\libucosii_bsp.a(alt_exception_entry.o) + ../MCTest_bsp/\libucosii_bsp.a(alt_irq_entry.o) (alt_exception) +c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-atexit.o) + ../MCTest_bsp/\libucosii_bsp.a(alt_main.o) (atexit) +c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-exit.o) + ../MCTest_bsp/\libucosii_bsp.a(alt_main.o) (exit) +c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-__atexit.o) + c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-atexit.o) (__register_exitproc) +c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-__call_atexit.o) + c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-exit.o) (__call_exitprocs) + +Allocating common symbols +Common symbol size file + +alt_irq 0x100 ../MCTest_bsp/\libucosii_bsp.a(alt_irq_handler.o) +OSLockNesting 0x1 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +OSRunning 0x1 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +OSIdleCtr 0x4 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +OSPrioHighRdy 0x1 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +errno 0x4 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-int_errno.o) +alt_heapsem 0x4 ../MCTest_bsp/\libucosii_bsp.a(alt_malloc_lock.o) +OSFlagTbl 0x370 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +OSPrioCur 0x1 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +OSTCBList 0x4 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +alt_fd_list_lock 0x4 ../MCTest_bsp/\libucosii_bsp.a(alt_dev.o) +OSMemTbl 0xc30 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +OSTickStepState 0x1 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +OSTaskStatStk 0x800 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +OSCtxSwCtr 0x4 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +OSIdleCtrMax 0x4 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +OSTCBFreeList 0x4 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +OSCPUUsage 0x1 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +OSTaskCtr 0x1 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +OSMemFreeList 0x4 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +OSQTbl 0x1e0 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +OSTCBHighRdy 0x4 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +OSQFreeList 0x4 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +OSRdyGrp 0x1 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +_atexit0 0x190 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-atexit.o) +OSRdyTbl 0x3 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +OSEventFreeList 0x4 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +OSIntNesting 0x1 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +OSTCBCur 0x4 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +OSTime 0x4 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +OSTaskIdleStk 0x800 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +OSEventTbl 0xb40 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +OSTCBTbl 0x510 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +OSFlagFreeList 0x4 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +OSStatRdy 0x1 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +OSTCBPrioTbl 0x54 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +alt_envsem 0x4 ../MCTest_bsp/\libucosii_bsp.a(alt_env_lock.o) +OSIdleCtrRun 0x4 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) + +Discarded input sections + + .group 0x00000000 0x8 obj/default/MotorHandler.o + .group 0x00000000 0x8 obj/default/MotorHandler.o + .group 0x00000000 0x8 obj/default/MotorHandler.o + .group 0x00000000 0x8 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(allocator-inst.o) + .group 0x00000000 0x8 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(allocator-inst.o) + .group 0x00000000 0x8 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(allocator-inst.o) + .group 0x00000000 0x8 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(allocator-inst.o) + .group 0x00000000 0x8 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(allocator-inst.o) + .group 0x00000000 0x8 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(allocator-inst.o) + .group 0x00000000 0x8 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(allocator-inst.o) + .group 0x00000000 0x8 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(allocator-inst.o) + .group 0x00000000 0x8 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c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(stdexcept.o) + .group 0x00000000 0x8 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(eh_exception.o) + .group 0x00000000 0x8 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(eh_exception.o) + .group 0x00000000 0x8 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(eh_exception.o) + .group 0x00000000 0x8 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(eh_exception.o) + .group 0x00000000 0x8 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(eh_exception.o) + .group 0x00000000 0x8 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(eh_exception.o) + .group 0x00000000 0x8 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(new_handler.o) + .group 0x00000000 0x8 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(new_handler.o) + .group 0x00000000 0x8 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(new_handler.o) + .group 0x00000000 0x8 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(bad_typeid.o) + .group 0x00000000 0x8 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(bad_typeid.o) + .group 0x00000000 0x8 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(bad_typeid.o) + .group 0x00000000 0x8 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(bad_cast.o) + .group 0x00000000 0x8 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(bad_cast.o) + .group 0x00000000 0x8 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(bad_cast.o) + +Memory Configuration + +Name Origin Length Attributes +reset 0x01000000 0x00000020 +sdram 0x01000020 0x00ffffe0 +*default* 0x00000000 0xffffffff + +Linker script and memory map + +LOAD ../MCTest_bsp//obj/HAL/src/crt0.o +LOAD obj/default/MotorHandler.o +LOAD obj/default/main.o +LOAD c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a +LOAD c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libm.a +LOAD c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a +START GROUP +LOAD c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a +LOAD c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a +LOAD ../MCTest_bsp/\libucosii_bsp.a +END GROUP +LOAD c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a + 0x01000000 __alt_mem_sdram = 0x1000000 + +.entry 0x01000000 0x20 + *(.entry) + .entry 0x01000000 0x20 ../MCTest_bsp//obj/HAL/src/crt0.o + 0x01000000 __reset + +.exceptions 0x01000020 0x1a0 + 0x01000020 PROVIDE (__ram_exceptions_start, ABSOLUTE (.)) + 0x01000020 . = ALIGN (0x20) + *(.irq) + *(.exceptions.entry.label) + .exceptions.entry.label + 0x01000020 0x0 ../MCTest_bsp/\libucosii_bsp.a(alt_irq_entry.o) + 0x01000020 alt_irq_entry + .exceptions.entry.label + 0x01000020 0x0 ../MCTest_bsp/\libucosii_bsp.a(alt_exception_entry.o) + 0x01000020 alt_exception + *(.exceptions.entry.user) + *(.exceptions.entry) + .exceptions.entry + 0x01000020 0x54 ../MCTest_bsp/\libucosii_bsp.a(alt_exception_entry.o) + *(.exceptions.irqtest.user) + *(.exceptions.irqtest) + .exceptions.irqtest + 0x01000074 0x10 ../MCTest_bsp/\libucosii_bsp.a(alt_irq_entry.o) + *(.exceptions.irqhandler.user) + *(.exceptions.irqhandler) + .exceptions.irqhandler + 0x01000084 0x4 ../MCTest_bsp/\libucosii_bsp.a(alt_irq_entry.o) + *(.exceptions.irqreturn.user) + *(.exceptions.irqreturn) + .exceptions.irqreturn + 0x01000088 0x4 ../MCTest_bsp/\libucosii_bsp.a(alt_irq_entry.o) + *(.exceptions.notirq.label) + .exceptions.notirq.label + 0x0100008c 0x0 ../MCTest_bsp/\libucosii_bsp.a(alt_irq_entry.o) + *(.exceptions.notirq.user) + *(.exceptions.notirq) + .exceptions.notirq + 0x0100008c 0x8 ../MCTest_bsp/\libucosii_bsp.a(alt_exception_entry.o) + *(.exceptions.soft.user) + *(.exceptions.soft) + *(.exceptions.unknown.user) + *(.exceptions.unknown) + .exceptions.unknown + 0x01000094 0x4 ../MCTest_bsp/\libucosii_bsp.a(alt_exception_entry.o) + *(.exceptions.exit.label) + .exceptions.exit.label + 0x01000098 0x0 ../MCTest_bsp/\libucosii_bsp.a(alt_irq_entry.o) + .exceptions.exit.label + 0x01000098 0x0 ../MCTest_bsp/\libucosii_bsp.a(alt_exception_entry.o) + *(.exceptions.exit.user) + *(.exceptions.exit) + .exceptions.exit + 0x01000098 0x54 ../MCTest_bsp/\libucosii_bsp.a(alt_exception_entry.o) + *(.exceptions) + .exceptions 0x010000ec 0xd4 ../MCTest_bsp/\libucosii_bsp.a(alt_irq_handler.o) + 0x010000ec alt_irq_handler + 0x010001c0 PROVIDE (__ram_exceptions_end, ABSOLUTE (.)) + 0x01000020 PROVIDE (__flash_exceptions_start, LOADADDR (.exceptions)) + +.text 0x010001c0 0x20c40 + 0x010001c0 PROVIDE (stext, ABSOLUTE (.)) + *(.interp) + *(.hash) + *(.dynsym) + *(.dynstr) + *(.gnu.version) + *(.gnu.version_d) + *(.gnu.version_r) + *(.rel.init) + *(.rela.init) + *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) + *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) + *(.rel.fini) + *(.rela.fini) + *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) + *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) + *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) + *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) + *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) + *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) + *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) + *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) + *(.rel.ctors) + *(.rela.ctors) + *(.rel.dtors) + *(.rela.dtors) + *(.rel.got) + *(.rela.got) + *(.rel.sdata .rel.sdata.* .rel.gnu.linkonce.s.*) + *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*) + *(.rel.sbss .rel.sbss.* .rel.gnu.linkonce.sb.*) + *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*) + *(.rel.sdata2 .rel.sdata2.* .rel.gnu.linkonce.s2.*) + *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*) + *(.rel.sbss2 .rel.sbss2.* .rel.gnu.linkonce.sb2.*) + *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*) + *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) + *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) + *(.rel.plt) + *(.rela.plt) + *(.rel.dyn) + *(.init) + *(.plt) + *(.text .stub .text.* .gnu.linkonce.t.*) + .text 0x010001c0 0x4c ../MCTest_bsp//obj/HAL/src/crt0.o + 0x010001c0 _start + .text 0x0100020c 0x6f4 obj/default/MotorHandler.o + 0x0100020c MotorHandler::MotorHandler() + 0x0100023c MotorHandler::MotorHandler() + 0x0100026c MotorHandler::reset() + 0x010002d8 MotorHandler::send(char, char const*) + 0x010003b4 MotorHandler::move(char, char, char const*) + 0x0100043c MotorHandler::configure() + 0x010004a8 MotorHandler::interpretDirection(std::string, int) + 0x01000534 MotorHandler::interpretMotor(std::string) + 0x01000598 MotorHandler::motorCommand(std::string, std::string, std::string) + 0x010007a4 MotorHandler::init() + 0x01000810 MotorHandler::~MotorHandler() + 0x01000860 MotorHandler::~MotorHandler() + 0x010008b0 MotorHandler::~MotorHandler() + .text 0x01000900 0x1988 obj/default/main.o + 0x01000a5c queue_init() + 0x01000a94 main + 0x01000b14 mc_task(void*) + .text 0x01002288 0x0 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(allocator-inst.o) + .text._ZNSaIcEC1Ev + 0x01002288 0x4 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(allocator-inst.o) + 0x01002288 std::allocator::allocator() + .text._ZNSaIcED2Ev + 0x0100228c 0x4 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(allocator-inst.o) + 0x0100228c std::allocator::~allocator() + .text._ZNSaIcEC2ERKS_ + 0x01002290 0x4 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(allocator-inst.o) + 0x01002290 std::allocator::allocator(std::allocator const&) + .text._ZNSaIwEC2Ev + 0x01002294 0x4 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(allocator-inst.o) + 0x01002294 std::allocator::allocator() + .text._ZNSaIwED1Ev + 0x01002298 0x4 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(allocator-inst.o) + 0x01002298 std::allocator::~allocator() + .text._ZNSaIwEC1ERKS_ + 0x0100229c 0x4 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(allocator-inst.o) + 0x0100229c std::allocator::allocator(std::allocator const&) + .text._ZNSaIwEC2ERKS_ + 0x010022a0 0x4 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(allocator-inst.o) + 0x010022a0 std::allocator::allocator(std::allocator const&) + .text._ZNSaIcEC1ERKS_ + 0x010022a4 0x4 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(allocator-inst.o) + 0x010022a4 std::allocator::allocator(std::allocator const&) + .text._ZNSaIwEC1Ev + 0x010022a8 0x4 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(allocator-inst.o) + 0x010022a8 std::allocator::allocator() + .text._ZNSaIwED2Ev + 0x010022ac 0x4 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(allocator-inst.o) + 0x010022ac std::allocator::~allocator() + .text._ZNSaIcEC2Ev + 0x010022b0 0x4 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c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(string-inst.o) + 0x01005184 std::string::insert(__gnu_cxx::__normal_iterator, char) + .text._ZNSs6insertEmmc + 0x010051e4 0x48 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(string-inst.o) + 0x010051e4 std::string::insert(unsigned long, unsigned long, char) + .text._ZNSs6assignEmc + 0x0100522c 0x38 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(string-inst.o) + 0x0100522c std::string::assign(unsigned long, char) + .text._ZNSsaSEc + 0x01005264 0x48 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(string-inst.o) + 0x01005264 std::string::operator=(char) + .text._ZNSs6insertEN9__gnu_cxx17__normal_iteratorIPcSsEEmc + 0x010052ac 0x38 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(string-inst.o) + 0x010052ac std::string::insert(__gnu_cxx::__normal_iterator, unsigned long, char) + .text._ZNSs5eraseEN9__gnu_cxx17__normal_iteratorIPcSsEES2_ + 0x010052e4 0x50 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(string-inst.o) + 0x010052e4 std::string::erase(__gnu_cxx::__normal_iterator, __gnu_cxx::__normal_iterator) + .text._ZNSs5eraseEN9__gnu_cxx17__normal_iteratorIPcSsEE + 0x01005334 0x50 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(string-inst.o) + 0x01005334 std::string::erase(__gnu_cxx::__normal_iterator) + .text._ZNSs5eraseEmm + 0x01005384 0x6c c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(string-inst.o) + 0x01005384 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std::string::rbegin() + .text._ZNSs6resizeEmc + 0x01005848 0x70 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(string-inst.o) + 0x01005848 std::string::resize(unsigned long, char) + .text._ZNSs6resizeEm + 0x010058b8 0x8 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(string-inst.o) + 0x010058b8 std::string::resize(unsigned long) + .text._ZStplIcSt11char_traitsIcESaIcEESbIT_T0_T1_EPKS3_RKS6_ + 0x010058c0 0x150 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(string-inst.o) + 0x010058c0 std::basic_string, std::allocator > std::operator+, std::allocator >(char const*, std::basic_string, std::allocator > const&) + .text._ZStplIcSt11char_traitsIcESaIcEESbIT_T0_T1_ERKS6_S8_ + 0x01005a10 0x114 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(string-inst.o) + 0x01005a10 std::basic_string, std::allocator > std::operator+, std::allocator >(std::basic_string, std::allocator > const&, std::basic_string, std::allocator > const&) + .text._ZNSs4swapERSs + 0x01005b24 0x34 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(string-inst.o) + 0x01005b24 std::string::swap(std::string&) + .text._ZStplIcSt11char_traitsIcESaIcEESbIT_T0_T1_ES3_RKS6_ + 0x01005b58 0x14c c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(string-inst.o) + 0x01005b58 std::basic_string, std::allocator > std::operator+, std::allocator >(char, std::basic_string, std::allocator > const&) + .text._ZNSs7replaceEmmPKcm + 0x01005ca4 0x2e0 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(string-inst.o) + 0x01005ca4 std::string::replace(unsigned long, unsigned long, char const*, unsigned long) + .text._ZNSs7replaceEN9__gnu_cxx17__normal_iteratorIPcSsEES2_NS0_IPKcSsEES5_ + 0x01005f84 0x1c c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(string-inst.o) + 0x01005f84 std::string::replace(__gnu_cxx::__normal_iterator, __gnu_cxx::__normal_iterator, __gnu_cxx::__normal_iterator, __gnu_cxx::__normal_iterator) + .text._ZNSs7replaceEN9__gnu_cxx17__normal_iteratorIPcSsEES2_S2_S2_ + 0x01005fa0 0x1c c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(string-inst.o) + 0x01005fa0 std::string::replace(__gnu_cxx::__normal_iterator, __gnu_cxx::__normal_iterator, __gnu_cxx::__normal_iterator, __gnu_cxx::__normal_iterator) + .text._ZNSs7replaceEN9__gnu_cxx17__normal_iteratorIPcSsEES2_PKcS4_ + 0x01005fbc 0x1c c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(string-inst.o) + 0x01005fbc std::string::replace(__gnu_cxx::__normal_iterator, __gnu_cxx::__normal_iterator, char const*, char const*) + .text._ZNSs7replaceEN9__gnu_cxx17__normal_iteratorIPcSsEES2_S1_S1_ + 0x01005fd8 0x1c c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(string-inst.o) + 0x01005fd8 std::string::replace(__gnu_cxx::__normal_iterator, __gnu_cxx::__normal_iterator, char*, char*) + .text._ZNSs7replaceEN9__gnu_cxx17__normal_iteratorIPcSsEES2_PKcm + 0x01005ff4 0x10 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(string-inst.o) + 0x01005ff4 std::string::replace(__gnu_cxx::__normal_iterator, __gnu_cxx::__normal_iterator, char const*, unsigned long) + .text._ZNSs7replaceEmmPKc + 0x01006004 0x64 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(string-inst.o) + 0x01006004 std::string::replace(unsigned long, unsigned long, char const*) + .text._ZNSs7replaceEmmRKSsmm + 0x01006068 0x5c c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(string-inst.o) + 0x01006068 std::string::replace(unsigned long, unsigned long, std::string const&, unsigned long, unsigned long) + .text._ZNSs7replaceEmmRKSs + 0x010060c4 0x24 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(string-inst.o) + 0x010060c4 std::string::replace(unsigned long, unsigned long, std::string const&) + .text._ZNSs7replaceEN9__gnu_cxx17__normal_iteratorIPcSsEES2_RKSs + 0x010060e8 0x30 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(string-inst.o) + 0x010060e8 std::string::replace(__gnu_cxx::__normal_iterator, __gnu_cxx::__normal_iterator, std::string const&) + .text._ZNSs7replaceEN9__gnu_cxx17__normal_iteratorIPcSsEES2_PKc + 0x01006118 0x64 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(string-inst.o) + 0x01006118 std::string::replace(__gnu_cxx::__normal_iterator, __gnu_cxx::__normal_iterator, char const*) + .text 0x0100617c 0x18 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(atomicity.o) + 0x0100617c __gnu_cxx::__exchange_and_add(int volatile*, int) + 0x01006190 __gnu_cxx::__atomic_add(int volatile*, int) + .text 0x01006194 0x1bc c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(class_type_info.o) + 0x01006194 __cxxabiv1::__class_type_info::__do_upcast(__cxxabiv1::__class_type_info const*, void**) const + 0x01006200 __cxxabiv1::__class_type_info::__do_find_public_src(long, void const*, __cxxabiv1::__class_type_info const*, void const*) const + 0x01006220 __cxxabiv1::__class_type_info::~__class_type_info() + 0x01006254 __cxxabiv1::__class_type_info::~__class_type_info() + 0x01006264 __cxxabiv1::__class_type_info::~__class_type_info() + 0x01006274 __cxxabiv1::__class_type_info::__do_catch(std::type_info const*, void**, unsigned int) const + 0x010062d4 __cxxabiv1::__class_type_info::__do_upcast(__cxxabiv1::__class_type_info const*, void const*, __cxxabiv1::__class_type_info::__upcast_result&) const + 0x01006304 __cxxabiv1::__class_type_info::__do_dyncast(long, __cxxabiv1::__class_type_info::__sub_kind, __cxxabiv1::__class_type_info const*, void const*, __cxxabiv1::__class_type_info const*, void const*, __cxxabiv1::__class_type_info::__dyncast_result&) const + .text 0x01006350 0xbec c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(eh_personality.o) + 0x010068dc __cxa_call_unexpected + 0x01006a5c __gxx_personality_sj0 + .text 0x01006f3c 0x10c c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(eh_terminate.o) + 0x01006f3c std::set_terminate(void (*)()) + 0x01006f50 std::set_unexpected(void (*)()) + 0x01006f64 __cxxabiv1::__terminate(void (*)()) + 0x01007008 std::terminate() + 0x01007020 __cxxabiv1::__unexpected(void (*)()) + 0x01007030 std::unexpected() + .text 0x01007048 0x0 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(eh_term_handler.o) + .text 0x01007048 0x1e4 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(eh_catch.o) + 0x01007048 __cxa_get_exception_ptr + 0x01007050 std::uncaught_exception() + 0x01007070 __cxa_end_catch + 0x01007114 __cxa_begin_catch + .text 0x0100722c 0xc c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(del_op.o) + 0x0100722c operator delete(void*) + .text 0x01007238 0x148 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(eh_throw.o) + 0x01007238 __cxa_rethrow + 0x010072ac __cxa_throw + .text 0x01007380 0x1c8 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(si_class_type_info.o) + 0x01007380 __cxxabiv1::__si_class_type_info::__do_upcast(__cxxabiv1::__class_type_info const*, void const*, __cxxabiv1::__class_type_info::__upcast_result&) const + 0x010073f8 __cxxabiv1::__si_class_type_info::~__si_class_type_info() + 0x0100742c __cxxabiv1::__si_class_type_info::~__si_class_type_info() + 0x0100743c __cxxabiv1::__si_class_type_info::~__si_class_type_info() + 0x0100744c __cxxabiv1::__si_class_type_info::__do_find_public_src(long, void const*, __cxxabiv1::__class_type_info const*, void const*) const + 0x01007480 __cxxabiv1::__si_class_type_info::__do_dyncast(long, __cxxabiv1::__class_type_info::__sub_kind, __cxxabiv1::__class_type_info const*, void const*, __cxxabiv1::__class_type_info const*, void const*, __cxxabiv1::__class_type_info::__dyncast_result&) const + .text 0x01007548 0x58 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(tinfo.o) + 0x01007548 std::type_info::__is_pointer_p() const + 0x01007550 std::type_info::__is_function_p() const + 0x01007558 std::type_info::__do_catch(std::type_info const*, void**, unsigned int) const + 0x01007568 std::type_info::__do_upcast(__cxxabiv1::__class_type_info const*, void**) const + 0x01007570 std::type_info::~type_info() + 0x01007580 std::type_info::~type_info() + 0x01007590 std::type_info::~type_info() + .text 0x010075a0 0x174 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(eh_alloc.o) + 0x010075a0 __cxa_free_exception + 0x010075e0 __cxa_allocate_exception + .text 0x01007714 0x100 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(new_op.o) + 0x01007714 operator new(unsigned long) + .text 0x01007814 0xfe8 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(functexcept.o) + 0x01007814 std::__throw_bad_typeid() + 0x01007848 std::__throw_bad_cast() + 0x0100787c std::__throw_bad_alloc() + 0x010078b0 std::__throw_bad_exception() + 0x010078e4 std::__throw_ios_failure(char const*) + 0x010079ec std::__throw_logic_error(char const*) + 0x01007b7c std::__throw_underflow_error(char const*) + 0x01007d0c std::__throw_overflow_error(char const*) + 0x01007e9c std::__throw_invalid_argument(char const*) + 0x0100802c std::__throw_domain_error(char const*) + 0x010081bc std::__throw_range_error(char const*) + 0x0100834c std::__throw_runtime_error(char const*) + 0x010084dc std::__throw_out_of_range(char const*) + 0x0100866c std::__throw_length_error(char const*) + .text._ZNSt15underflow_errorD0Ev + 0x010087fc 0x34 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(functexcept.o) + 0x010087fc std::underflow_error::~underflow_error() + .text._ZNSt15underflow_errorD1Ev + 0x01008830 0x10 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(functexcept.o) + 0x01008830 std::underflow_error::~underflow_error() + .text._ZNSt14overflow_errorD0Ev + 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c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(functexcept.o) + 0x010088c8 std::out_of_range::~out_of_range() + .text._ZNSt12out_of_rangeD1Ev + 0x010088fc 0x10 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(functexcept.o) + 0x010088fc std::out_of_range::~out_of_range() + .text._ZNSt12length_errorD0Ev + 0x0100890c 0x34 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(functexcept.o) + 0x0100890c std::length_error::~length_error() + .text._ZNSt12length_errorD1Ev + 0x01008940 0x10 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(functexcept.o) + 0x01008940 std::length_error::~length_error() + .text._ZNSt16invalid_argumentD0Ev + 0x01008950 0x34 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(functexcept.o) + 0x01008950 std::invalid_argument::~invalid_argument() + .text._ZNSt16invalid_argumentD1Ev + 0x01008984 0x10 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(functexcept.o) + 0x01008984 std::invalid_argument::~invalid_argument() + .text._ZNSt12domain_errorD0Ev + 0x01008994 0x34 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(functexcept.o) + 0x01008994 std::domain_error::~domain_error() + .text._ZNSt12domain_errorD1Ev + 0x010089c8 0x10 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(functexcept.o) + 0x010089c8 std::domain_error::~domain_error() + .text 0x010089d8 0x4bc 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std::overflow_error::overflow_error(std::string const&) + 0x01009110 std::range_error::range_error(std::string const&) + 0x01009140 std::range_error::range_error(std::string const&) + 0x01009170 std::logic_error::logic_error(std::string const&) + 0x01009220 std::logic_error::logic_error(std::string const&) + 0x010092d0 std::out_of_range::out_of_range(std::string const&) + 0x01009300 std::out_of_range::out_of_range(std::string const&) + 0x01009330 std::length_error::length_error(std::string const&) + 0x01009360 std::length_error::length_error(std::string const&) + 0x01009390 std::invalid_argument::invalid_argument(std::string const&) + 0x010093c0 std::invalid_argument::invalid_argument(std::string const&) + 0x010093f0 std::domain_error::domain_error(std::string const&) + 0x01009420 std::domain_error::domain_error(std::string const&) + 0x01009450 std::logic_error::what() const + 0x01009458 std::runtime_error::runtime_error(std::string const&) + 0x01009508 std::runtime_error::~runtime_error() + 0x0100960c std::runtime_error::~runtime_error() + 0x01009710 std::runtime_error::~runtime_error() + 0x0100981c std::logic_error::~logic_error() + 0x01009920 std::logic_error::~logic_error() + .text 0x01009a2c 0x94 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(eh_exception.o) + 0x01009a2c std::exception::what() const + 0x01009a3c std::exception::~exception() + 0x01009a4c std::exception::~exception() + 0x01009a5c std::exception::~exception() + 0x01009a6c std::bad_exception::~bad_exception() + 0x01009aa0 std::bad_exception::~bad_exception() + 0x01009ab0 std::bad_exception::~bad_exception() + .text 0x01009ac0 0x44 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(eh_call.o) + 0x01009ac0 __cxa_call_terminate + .text 0x01009b04 0x60 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c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-reallocr.o) + 0x01010ff4 _realloc_r + .text 0x010115e8 0x40 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-s_isinfd.o) + 0x010115e8 __isinfd + .text 0x01011628 0x30 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-s_isnand.o) + 0x01011628 __isnand + .text 0x01011658 0x14c c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-stdio.o) + 0x01011658 __sclose + 0x01011660 __sseek + 0x010116c8 __swrite + 0x01011744 __sread + .text 0x010117a4 0xbc c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-strcmp.o) + 0x010117a4 strcmp + .text 0x01011860 0x14c c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-wbuf.o) + 0x01011860 __swbuf_r + 0x01011990 __swbuf + .text 0x010119ac 0x78 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-writer.o) + 0x010119ac _write_r + .text 0x01011a24 0xb4 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-callocr.o) + 0x01011a24 _calloc_r + .text 0x01011ad8 0x70 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-closer.o) + 0x01011ad8 _close_r + .text 0x01011b48 0x124 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-fclose.o) + 0x01011b48 _fclose_r + 0x01011c58 fclose + .text 0x01011c6c 0x74 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-fstatr.o) + 0x01011c6c _fstat_r + .text 0x01011ce0 0x70 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-isattyr.o) + 0x01011ce0 _isatty_r + .text 0x01011d50 0x78 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-lseekr.o) + 0x01011d50 _lseek_r + .text 0x01011dc8 0x78 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-readr.o) + 0x01011dc8 _read_r + .text 0x01011e40 0x5dc c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_udivdi3.o) + 0x01011e40 __udivdi3 + .text 0x0101241c 0x5b0 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_umoddi3.o) + 0x0101241c __umoddi3 + .text 0x010129cc 0x504 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_addsub_df.o) + 0x01012ddc __subdf3 + 0x01012e5c __adddf3 + .text 0x01012ed0 0x3c4 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_mul_df.o) + 0x01012ed0 __muldf3 + .text 0x01013294 0x258 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_div_df.o) + 0x01013294 __divdf3 + .text 0x010134ec 0x88 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_eq_df.o) + 0x010134ec __eqdf2 + .text 0x01013574 0x88 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_ne_df.o) + 0x01013574 __nedf2 + .text 0x010135fc 0x88 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_gt_df.o) + 0x010135fc __gtdf2 + .text 0x01013684 0x88 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_ge_df.o) + 0x01013684 __gedf2 + .text 0x0101370c 0x88 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_lt_df.o) + 0x0101370c __ltdf2 + .text 0x01013794 0xf8 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_si_to_df.o) + 0x01013794 __floatsidf + .text 0x0101388c 0xd8 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_df_to_si.o) + 0x0101388c __fixdfsi + .text 0x01013964 0x0 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_thenan_df.o) + .text 0x01013964 0x194 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_usi_to_df.o) + 0x01013964 __floatunsidf + .text 0x01013af8 0x14c c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(lib2-divmod.o) + 0x01013b74 __divsi3 + 0x01013bd4 __modsi3 + 0x01013c34 __udivsi3 + 0x01013c3c __umodsi3 + .text 0x01013c44 0x98 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_muldi3.o) + 0x01013c44 __muldi3 + .text 0x01013cdc 0x0 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_clz.o) + .text 0x01013cdc 0x80 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_clzsi2.o) + 0x01013cdc __clzsi2 + .text 0x01013d5c 0x314 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_pack_df.o) + 0x01013d5c __pack_d + .text 0x01014070 0x138 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_unpack_df.o) + 0x01014070 __unpack_d + .text 0x010141a8 0xc8 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_fpcmp_parts_df.o) + 0x010141a8 __fpcmp_parts_d + .text 0x01014270 0x15c ../MCTest_bsp/\libucosii_bsp.a(alt_close.o) + 0x01014270 close + .text 0x010143cc 0x2c ../MCTest_bsp/\libucosii_bsp.a(alt_dev.o) + .text 0x010143f8 0x0 ../MCTest_bsp/\libucosii_bsp.a(alt_errno.o) + .text 0x010143f8 0x6c ../MCTest_bsp/\libucosii_bsp.a(alt_exit.o) + 0x01014438 _exit + .text 0x01014464 0x134 ../MCTest_bsp/\libucosii_bsp.a(alt_fstat.o) + 0x01014464 fstat + .text 0x01014598 0x20 ../MCTest_bsp/\libucosii_bsp.a(alt_getpid.o) + 0x01014598 getpid + .text 0x010145b8 0x120 ../MCTest_bsp/\libucosii_bsp.a(alt_isatty.o) + 0x010145b8 isatty + .text 0x010146d8 0x1a0 ../MCTest_bsp/\libucosii_bsp.a(alt_kill.o) + 0x010146d8 kill + .text 0x01014878 0xec ../MCTest_bsp/\libucosii_bsp.a(alt_load.o) + 0x01014878 alt_load + .text 0x01014964 0x150 ../MCTest_bsp/\libucosii_bsp.a(alt_lseek.o) + 0x01014964 lseek + .text 0x01014ab4 0xc8 ../MCTest_bsp/\libucosii_bsp.a(alt_main.o) + 0x01014ab4 alt_main + .text 0x01014b7c 0x180 ../MCTest_bsp/\libucosii_bsp.a(alt_read.o) + 0x01014b7c read + .text 0x01014cfc 0x60 ../MCTest_bsp/\libucosii_bsp.a(alt_release_fd.o) + 0x01014cfc alt_release_fd + .text 0x01014d5c 0xbc ../MCTest_bsp/\libucosii_bsp.a(alt_sbrk.o) + 0x01014d5c sbrk + .text 0x01014e18 0x180 ../MCTest_bsp/\libucosii_bsp.a(alt_write.o) + 0x01014e18 write + .text 0x01014f98 0x108 ../MCTest_bsp/\libucosii_bsp.a(alt_env_lock.o) + 0x01014f98 __env_lock + 0x01015044 __env_unlock + .text 0x010150a0 0x1d8 ../MCTest_bsp/\libucosii_bsp.a(alt_malloc_lock.o) + 0x010150a0 __malloc_lock + 0x010151a8 __malloc_unlock + .text 0x01015278 0x2128 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) + 0x01015278 OSEventNameGet + 0x010153a8 OSEventNameSet + 0x010154ec OSEventPendMulti + 0x01015ba0 OSInit + 0x01015bf4 OSIntEnter + 0x01015c70 OSIntExit + 0x01015d70 OSSchedLock + 0x01015dfc OSSchedUnlock + 0x01015ee0 OSStart + 0x01015f50 OSStatInit + 0x01015ffc OSTimeTick + 0x0101623c OSVersion + 0x0101625c OS_Dummy + 0x01016278 OS_EventTaskRdy + 0x0101640c OS_EventTaskWait + 0x0101651c OS_EventTaskWaitMulti + 0x01016670 OS_EventTaskRemove + 0x01016728 OS_EventTaskRemoveMulti + 0x0101682c OS_EventWaitListInit + 0x01016bf8 OS_MemClr + 0x01016c4c OS_MemCopy + 0x01016cb8 OS_Sched + 0x01016dfc OS_StrCopy + 0x01016e7c OS_StrLen + 0x01016ed4 OS_TaskIdle + 0x01016f30 OS_TaskStat + 0x01016ff8 OS_TaskStatStkChk + 0x010170c0 OS_TCBInit + .text 0x010173a0 0x18c ../MCTest_bsp/\libucosii_bsp.a(os_dbg.o) + 0x010173a0 OSDebugInit + .text 0x0101752c 0x193c ../MCTest_bsp/\libucosii_bsp.a(os_flag.o) + 0x0101752c OSFlagAccept + 0x01017860 OSFlagCreate + 0x0101799c OSFlagDel + 0x01017c44 OSFlagNameGet + 0x01017d88 OSFlagNameSet + 0x01017edc OSFlagPend + 0x01018520 OSFlagPendGetFlagsRdy + 0x01018588 OSFlagPost + 0x01018930 OSFlagQuery + 0x01018bc8 OS_FlagInit + 0x01018dbc OS_FlagUnlink + .text 0x01018e68 0x808 ../MCTest_bsp/\libucosii_bsp.a(os_mem.o) + 0x01018e68 OSMemCreate + 0x01019084 OSMemGet + 0x01019188 OSMemNameGet + 0x01019294 OSMemNameSet + 0x010193b4 OSMemPut + 0x010194a4 OSMemQuery + 0x010195a0 OS_MemInit + .text 0x01019670 0x1334 ../MCTest_bsp/\libucosii_bsp.a(os_q.o) + 0x01019670 OSQAccept + 0x010197c4 OSQCreate + 0x010199d8 OSQDel + 0x01019cd8 OSQFlush + 0x01019da0 OSQPend + 0x0101a0c0 OSQPendAbort + 0x0101a23c OSQPost + 0x0101a3bc OSQPostFront + 0x0101a544 OSQPostOpt + 0x0101a778 OSQQuery + 0x0101a8f8 OS_QInit + .text 0x0101a9a4 0xbc8 ../MCTest_bsp/\libucosii_bsp.a(os_sem.o) + 0x0101a9a4 OSSemAccept + 0x0101aa64 OSSemCreate + 0x0101ab78 OSSemDel + 0x0101ae18 OSSemPend + 0x0101b094 OSSemPendAbort + 0x0101b210 OSSemPost + 0x0101b338 OSSemQuery + 0x0101b468 OSSemSet + .text 0x0101b56c 0x1a40 ../MCTest_bsp/\libucosii_bsp.a(os_task.o) + 0x0101b56c OSTaskChangePrio + 0x0101bae0 OSTaskCreate + 0x0101bcb4 OSTaskCreateExt + 0x0101beb4 OSTaskDel + 0x0101c2c0 OSTaskDelReq + 0x0101c430 OSTaskNameGet + 0x0101c5e8 OSTaskNameSet + 0x0101c7ac OSTaskResume + 0x0101c9c4 OSTaskStkChk + 0x0101cbc0 OSTaskSuspend + 0x0101cdec OSTaskQuery + 0x0101cf30 OS_TaskStkClr + .text 0x0101cfac 0x598 ../MCTest_bsp/\libucosii_bsp.a(os_time.o) + 0x0101cfac OSTimeDly + 0x0101d0f8 OSTimeDlyHMSM + 0x0101d26c OSTimeDlyResume + 0x0101d47c OSTimeGet + 0x0101d4e0 OSTimeSet + .text 0x0101d544 0xf4 ../MCTest_bsp/\libucosii_bsp.a(alt_sys_init.o) + 0x0101d544 alt_irq_init + 0x0101d578 alt_sys_init + .text 0x0101d638 0x148 ../MCTest_bsp/\libucosii_bsp.a(altera_avalon_jtag_uart_fd.o) + 0x0101d638 altera_avalon_jtag_uart_read_fd + 0x0101d690 altera_avalon_jtag_uart_write_fd + 0x0101d6e8 altera_avalon_jtag_uart_close_fd + 0x0101d730 altera_avalon_jtag_uart_ioctl_fd + .text 0x0101d780 0x580 ../MCTest_bsp/\libucosii_bsp.a(altera_avalon_jtag_uart_init.o) + 0x0101d780 altera_avalon_jtag_uart_init + 0x0101dc8c altera_avalon_jtag_uart_close + .text 0x0101dd00 0xf4 ../MCTest_bsp/\libucosii_bsp.a(altera_avalon_jtag_uart_ioctl.o) + 0x0101dd00 altera_avalon_jtag_uart_ioctl + .text 0x0101ddf4 0x2c0 ../MCTest_bsp/\libucosii_bsp.a(altera_avalon_jtag_uart_read.o) + 0x0101ddf4 altera_avalon_jtag_uart_read + .text 0x0101e0b4 0x2dc ../MCTest_bsp/\libucosii_bsp.a(altera_avalon_jtag_uart_write.o) + 0x0101e0b4 altera_avalon_jtag_uart_write + .text 0x0101e390 0xfc ../MCTest_bsp/\libucosii_bsp.a(altera_avalon_timer_sc.o) + 0x0101e404 alt_avalon_timer_sc_init + .text 0x0101e48c 0xf8 ../MCTest_bsp/\libucosii_bsp.a(altera_avalon_uart_fd.o) + 0x0101e48c altera_avalon_uart_read_fd + 0x0101e4e4 altera_avalon_uart_write_fd + 0x0101e53c altera_avalon_uart_close_fd + .text 0x0101e584 0x578 ../MCTest_bsp/\libucosii_bsp.a(altera_avalon_uart_init.o) + 0x0101e584 altera_avalon_uart_init + 0x0101ea9c altera_avalon_uart_close + .text 0x0101eafc 0x310 ../MCTest_bsp/\libucosii_bsp.a(altera_avalon_uart_read.o) + 0x0101eafc altera_avalon_uart_read + .text 0x0101ee0c 0x2a8 ../MCTest_bsp/\libucosii_bsp.a(altera_avalon_uart_write.o) + 0x0101ee0c altera_avalon_uart_write + .text 0x0101f0b4 0x398 ../MCTest_bsp/\libucosii_bsp.a(altera_up_avalon_rs232.o) + 0x0101f0b4 alt_up_rs232_enable_read_interrupt + 0x0101f108 alt_up_rs232_disable_read_interrupt + 0x0101f160 alt_up_rs232_get_used_space_in_read_FIFO + 0x0101f19c alt_up_rs232_get_available_space_in_write_FIFO + 0x0101f1dc alt_up_rs232_check_parity + 0x0101f22c alt_up_rs232_write_data + 0x0101f274 alt_up_rs232_read_data + 0x0101f2e8 alt_up_rs232_read_fd + 0x0101f378 alt_up_rs232_write_fd + 0x0101f40c alt_up_rs232_open_dev + .text 0x0101f44c 0x154 ../MCTest_bsp/\libucosii_bsp.a(alt_alarm_start.o) + 0x0101f44c alt_alarm_start + .text 0x0101f5a0 0x44 ../MCTest_bsp/\libucosii_bsp.a(alt_dcache_flush_all.o) + 0x0101f5a0 alt_dcache_flush_all + .text 0x0101f5e4 0x114 ../MCTest_bsp/\libucosii_bsp.a(alt_dev_llist_insert.o) + 0x0101f5e4 alt_dev_llist_insert + .text 0x0101f6f8 0x64 ../MCTest_bsp/\libucosii_bsp.a(alt_do_ctors.o) + 0x0101f6f8 _do_ctors + .text 0x0101f75c 0x64 ../MCTest_bsp/\libucosii_bsp.a(alt_do_dtors.o) + 0x0101f75c _do_dtors + .text 0x0101f7c0 0x94 ../MCTest_bsp/\libucosii_bsp.a(alt_find_dev.o) + 0x0101f7c0 alt_find_dev + .text 0x0101f854 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c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_usi_to_df.o) + .debug_loc 0x00013b2d 0x1d2 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(lib2-divmod.o) + .debug_loc 0x00013cff 0xc4 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_muldi3.o) + .debug_loc 0x00013dc3 0x1e c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_clzsi2.o) + .debug_loc 0x00013de1 0x184 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_pack_df.o) + .debug_loc 0x00013f65 0xe5 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_unpack_df.o) + .debug_loc 0x0001404a 0x56 ../MCTest_bsp/\libucosii_bsp.a(alt_close.o) + .debug_loc 0x000140a0 0x2b ../MCTest_bsp/\libucosii_bsp.a(alt_dev.o) + .debug_loc 0x000140cb 0x56 ../MCTest_bsp/\libucosii_bsp.a(alt_exit.o) + .debug_loc 0x00014121 0x56 ../MCTest_bsp/\libucosii_bsp.a(alt_fstat.o) + .debug_loc 0x00014177 0x2b ../MCTest_bsp/\libucosii_bsp.a(alt_getpid.o) + .debug_loc 0x000141a2 0x57 ../MCTest_bsp/\libucosii_bsp.a(alt_isatty.o) + .debug_loc 0x000141f9 0x56 ../MCTest_bsp/\libucosii_bsp.a(alt_kill.o) + .debug_loc 0x0001424f 0x56 ../MCTest_bsp/\libucosii_bsp.a(alt_load.o) + .debug_loc 0x000142a5 0x56 ../MCTest_bsp/\libucosii_bsp.a(alt_lseek.o) + .debug_loc 0x000142fb 0x2b ../MCTest_bsp/\libucosii_bsp.a(alt_main.o) + .debug_loc 0x00014326 0x56 ../MCTest_bsp/\libucosii_bsp.a(alt_read.o) + .debug_loc 0x0001437c 0x2b ../MCTest_bsp/\libucosii_bsp.a(alt_release_fd.o) + .debug_loc 0x000143a7 0x2b ../MCTest_bsp/\libucosii_bsp.a(alt_sbrk.o) + .debug_loc 0x000143d2 0x56 ../MCTest_bsp/\libucosii_bsp.a(alt_write.o) + .debug_loc 0x00014428 0x57 ../MCTest_bsp/\libucosii_bsp.a(alt_env_lock.o) + .debug_loc 0x0001447f 0x57 ../MCTest_bsp/\libucosii_bsp.a(alt_malloc_lock.o) + .debug_loc 0x000144d6 0x5e2 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) + .debug_loc 0x00014ab8 0x2b ../MCTest_bsp/\libucosii_bsp.a(os_dbg.o) + .debug_loc 0x00014ae3 0x232 ../MCTest_bsp/\libucosii_bsp.a(os_flag.o) + .debug_loc 0x00014d15 0x12d ../MCTest_bsp/\libucosii_bsp.a(os_mem.o) + .debug_loc 0x00014e42 0x1da ../MCTest_bsp/\libucosii_bsp.a(os_q.o) + .debug_loc 0x0001501c 0x158 ../MCTest_bsp/\libucosii_bsp.a(os_sem.o) + .debug_loc 0x00015174 0x207 ../MCTest_bsp/\libucosii_bsp.a(os_task.o) + .debug_loc 0x0001537b 0xd7 ../MCTest_bsp/\libucosii_bsp.a(os_time.o) + .debug_loc 0x00015452 0x81 ../MCTest_bsp/\libucosii_bsp.a(alt_sys_init.o) + .debug_loc 0x000154d3 0xac ../MCTest_bsp/\libucosii_bsp.a(altera_avalon_jtag_uart_fd.o) + .debug_loc 0x0001557f 0xac ../MCTest_bsp/\libucosii_bsp.a(altera_avalon_jtag_uart_init.o) + .debug_loc 0x0001562b 0x2b ../MCTest_bsp/\libucosii_bsp.a(altera_avalon_jtag_uart_ioctl.o) + .debug_loc 0x00015656 0x2c ../MCTest_bsp/\libucosii_bsp.a(altera_avalon_jtag_uart_read.o) + .debug_loc 0x00015682 0x2c ../MCTest_bsp/\libucosii_bsp.a(altera_avalon_jtag_uart_write.o) + .debug_loc 0x000156ae 0x56 ../MCTest_bsp/\libucosii_bsp.a(altera_avalon_timer_sc.o) + .debug_loc 0x00015704 0x81 ../MCTest_bsp/\libucosii_bsp.a(altera_avalon_uart_fd.o) + .debug_loc 0x00015785 0xd8 ../MCTest_bsp/\libucosii_bsp.a(altera_avalon_uart_init.o) + .debug_loc 0x0001585d 0x57 ../MCTest_bsp/\libucosii_bsp.a(altera_avalon_uart_read.o) + .debug_loc 0x000158b4 0x57 ../MCTest_bsp/\libucosii_bsp.a(altera_avalon_uart_write.o) + .debug_loc 0x0001590b 0x1ae ../MCTest_bsp/\libucosii_bsp.a(altera_up_avalon_rs232.o) + .debug_loc 0x00015ab9 0x2b ../MCTest_bsp/\libucosii_bsp.a(alt_alarm_start.o) + .debug_loc 0x00015ae4 0x2b ../MCTest_bsp/\libucosii_bsp.a(alt_dcache_flush_all.o) + .debug_loc 0x00015b0f 0x56 ../MCTest_bsp/\libucosii_bsp.a(alt_dev_llist_insert.o) + .debug_loc 0x00015b65 0x2b ../MCTest_bsp/\libucosii_bsp.a(alt_do_ctors.o) + .debug_loc 0x00015b90 0x2b ../MCTest_bsp/\libucosii_bsp.a(alt_do_dtors.o) + .debug_loc 0x00015bbb 0x2b ../MCTest_bsp/\libucosii_bsp.a(alt_find_dev.o) + .debug_loc 0x00015be6 0x2b ../MCTest_bsp/\libucosii_bsp.a(alt_icache_flush_all.o) + .debug_loc 0x00015c11 0x56 ../MCTest_bsp/\libucosii_bsp.a(alt_io_redirect.o) + .debug_loc 0x00015c67 0x2c ../MCTest_bsp/\libucosii_bsp.a(alt_irq_register.o) + .debug_loc 0x00015c93 0x81 ../MCTest_bsp/\libucosii_bsp.a(alt_open.o) + .debug_loc 0x00015d14 0x56 ../MCTest_bsp/\libucosii_bsp.a(alt_tick.o) + .debug_loc 0x00015d6a 0x2b ../MCTest_bsp/\libucosii_bsp.a(altera_nios2_qsys_irq.o) + .debug_loc 0x00015d95 0x1ae ../MCTest_bsp/\libucosii_bsp.a(os_cpu_c.o) + .debug_loc 0x00015f43 0x2b ../MCTest_bsp/\libucosii_bsp.a(alt_find_file.o) + .debug_loc 0x00015f6e 0x2b ../MCTest_bsp/\libucosii_bsp.a(alt_get_fd.o) + .debug_loc 0x00015f99 0x2b ../MCTest_bsp/\libucosii_bsp.a(alt_icache_flush.o) + .debug_loc 0x00015fc4 0x2b ../MCTest_bsp/\libucosii_bsp.a(alt_irq_handler.o) + .debug_loc 0x00015fef 0x1e c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-atexit.o) + .debug_loc 0x0001600d 0x3d c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-exit.o) + .debug_loc 0x0001604a 0x120 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-__atexit.o) + .debug_loc 0x0001616a 0x1cb c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-__call_atexit.o) + +.debug_macinfo + *(.debug_macinfo) + +.debug_weaknames + *(.debug_weaknames) + +.debug_funcnames + *(.debug_funcnames) + +.debug_typenames + *(.debug_typenames) + +.debug_varnames + *(.debug_varnames) + +.debug_alt_sim_info + 0x00000000 0x30 + *(.debug_alt_sim_info) + .debug_alt_sim_info + 0x00000000 0x30 ../MCTest_bsp//obj/HAL/src/crt0.o + 0x02000000 __alt_data_end = 0x2000000 + 0x02000000 PROVIDE (__alt_stack_pointer, __alt_data_end) + 0x0102d1a8 PROVIDE (__alt_stack_limit, __alt_stack_base) + 0x0102d1a8 PROVIDE (__alt_heap_start, end) + 0x02000000 PROVIDE (__alt_heap_limit, 0x2000000) +OUTPUT(MCTest.elf elf32-littlenios2) + +.debug_ranges 0x00000000 0x32a8 + .debug_ranges 0x00000000 0x20 ../MCTest_bsp//obj/HAL/src/crt0.o + .debug_ranges 0x00000020 0x1d80 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(string-inst.o) + .debug_ranges 0x00001da0 0x18 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(class_type_info.o) + .debug_ranges 0x00001db8 0x80 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(eh_personality.o) + .debug_ranges 0x00001e38 0x18 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(eh_catch.o) + .debug_ranges 0x00001e50 0x30 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(eh_alloc.o) + .debug_ranges 0x00001e80 0x18 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(new_op.o) + .debug_ranges 0x00001e98 0x560 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(functexcept.o) + .debug_ranges 0x000023f8 0x138 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(ios_failure.o) + .debug_ranges 0x00002530 0x270 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(stdexcept.o) + .debug_ranges 0x000027a0 0x168 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(unwind-sjlj.o) + .debug_ranges 0x00002908 0x70 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-mallocr.o) + .debug_ranges 0x00002978 0x168 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-vfprintf.o) + .debug_ranges 0x00002ae0 0x20 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-fflush.o) + .debug_ranges 0x00002b00 0x28 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-fvwrite.o) + .debug_ranges 0x00002b28 0xa0 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-fwalk.o) + .debug_ranges 0x00002bc8 0x110 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-reallocr.o) + .debug_ranges 0x00002cd8 0x38 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-callocr.o) + .debug_ranges 0x00002d10 0x188 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_udivdi3.o) + .debug_ranges 0x00002e98 0x198 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_umoddi3.o) + .debug_ranges 0x00003030 0x30 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_addsub_df.o) + .debug_ranges 0x00003060 0x88 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_mul_df.o) + .debug_ranges 0x000030e8 0x50 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_div_df.o) + .debug_ranges 0x00003138 0x18 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_usi_to_df.o) + .debug_ranges 0x00003150 0x68 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_muldi3.o) + .debug_ranges 0x000031b8 0x28 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_clzsi2.o) + .debug_ranges 0x000031e0 0x28 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_pack_df.o) + .debug_ranges 0x00003208 0x18 ../MCTest_bsp/\libucosii_bsp.a(altera_avalon_jtag_uart_init.o) + .debug_ranges 0x00003220 0x18 ../MCTest_bsp/\libucosii_bsp.a(altera_avalon_uart_init.o) + .debug_ranges 0x00003238 0x28 ../MCTest_bsp/\libucosii_bsp.a(alt_irq_entry.o) + .debug_ranges 0x00003260 0x30 ../MCTest_bsp/\libucosii_bsp.a(alt_exception_entry.o) + .debug_ranges 0x00003290 0x18 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-__call_atexit.o) diff --git a/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.objdump b/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.objdump new file mode 100644 index 00000000..f3067dae --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/MCTest/MCTest.objdump @@ -0,0 +1,45398 @@ + +MCTest.elf: file format elf32-littlenios2 +MCTest.elf +architecture: nios2, flags 0x00000112: +EXEC_P, HAS_SYMS, D_PAGED +start address 0x010001c0 + +Program Header: + LOAD off 0x00001000 vaddr 0x01000000 paddr 0x01000000 align 2**12 + filesz 0x00000020 memsz 0x00000020 flags r-x + LOAD off 0x00001020 vaddr 0x01000020 paddr 0x01000020 align 2**12 + filesz 0x00021ba0 memsz 0x00021ba0 flags r-x + LOAD off 0x00022bc0 vaddr 0x01021bc0 paddr 0x010237d4 align 2**12 + filesz 0x00001c14 memsz 0x00001c14 flags rw- + LOAD off 0x000253e8 vaddr 0x010253e8 paddr 0x010253e8 align 2**12 + filesz 0x00000000 memsz 0x00007dc0 flags rw- + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .entry 00000020 01000000 01000000 00001000 2**5 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 1 .exceptions 000001a0 01000020 01000020 00001020 2**2 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 2 .text 00020c40 010001c0 010001c0 000011c0 2**2 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 3 .rodata 00000dc0 01020e00 01020e00 00021e00 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 4 .rwdata 00001c14 01021bc0 010237d4 00022bc0 2**2 + CONTENTS, ALLOC, LOAD, DATA, SMALL_DATA + 5 .bss 00007dc0 010253e8 010253e8 000253e8 2**2 + ALLOC, SMALL_DATA + 6 .comment 00000026 00000000 00000000 000247d4 2**0 + CONTENTS, READONLY + 7 .debug_aranges 00001920 00000000 00000000 00024800 2**3 + CONTENTS, READONLY, DEBUGGING + 8 .debug_pubnames 000079a8 00000000 00000000 00026120 2**0 + CONTENTS, READONLY, DEBUGGING + 9 .debug_info 00062f33 00000000 00000000 0002dac8 2**0 + CONTENTS, READONLY, DEBUGGING + 10 .debug_abbrev 0000ff06 00000000 00000000 000909fb 2**0 + CONTENTS, READONLY, DEBUGGING + 11 .debug_line 0002b262 00000000 00000000 000a0901 2**0 + CONTENTS, READONLY, DEBUGGING + 12 .debug_frame 00004b78 00000000 00000000 000cbb64 2**2 + CONTENTS, READONLY, DEBUGGING + 13 .debug_str 00009183 00000000 00000000 000d06dc 2**0 + CONTENTS, READONLY, DEBUGGING + 14 .debug_loc 00016335 00000000 00000000 000d985f 2**0 + CONTENTS, READONLY, DEBUGGING + 15 .debug_alt_sim_info 00000030 00000000 00000000 000efb94 2**2 + CONTENTS, READONLY, DEBUGGING + 16 .debug_ranges 000032a8 00000000 00000000 000efbc8 2**3 + CONTENTS, READONLY, DEBUGGING + 17 .thread_model 00000006 00000000 00000000 000fc68d 2**0 + CONTENTS, READONLY + 18 .cpu 00000003 00000000 00000000 000fc693 2**0 + CONTENTS, READONLY + 19 .qsys 00000001 00000000 00000000 000fc696 2**0 + CONTENTS, READONLY + 20 .simulation_enabled 00000001 00000000 00000000 000fc697 2**0 + CONTENTS, READONLY + 21 .sysid_hash 00000004 00000000 00000000 000fc698 2**0 + CONTENTS, READONLY + 22 .sysid_base 00000004 00000000 00000000 000fc69c 2**0 + CONTENTS, READONLY + 23 .sysid_time 00000004 00000000 00000000 000fc6a0 2**0 + CONTENTS, READONLY + 24 .stderr_dev 0000000b 00000000 00000000 000fc6a4 2**0 + CONTENTS, READONLY + 25 .stdin_dev 0000000b 00000000 00000000 000fc6af 2**0 + CONTENTS, READONLY + 26 .stdout_dev 0000000b 00000000 00000000 000fc6ba 2**0 + CONTENTS, READONLY + 27 .sopc_system_name 00000006 00000000 00000000 000fc6c5 2**0 + CONTENTS, READONLY + 28 .quartus_project_dir 0000002e 00000000 00000000 000fc6cb 2**0 + CONTENTS, READONLY + 29 .jdi 000046ad 00000000 00000000 000fc6f9 2**0 + CONTENTS, READONLY + 30 .sopcinfo 0004f74a 00000000 00000000 00100da6 2**0 + CONTENTS, READONLY +SYMBOL TABLE: +01000000 l d .entry 00000000 .entry +01000020 l d .exceptions 00000000 .exceptions +010001c0 l d .text 00000000 .text +01020e00 l d .rodata 00000000 .rodata +01021bc0 l d .rwdata 00000000 .rwdata +010253e8 l d .bss 00000000 .bss +00000000 l d .comment 00000000 .comment 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.text 00000100 __multadd +01006220 g F .text 00000034 _ZN10__cxxabiv117__class_type_infoD0Ev +0101cbc0 g F .text 0000022c OSTaskSuspend +0100fe14 g F .text 00000028 _Bfree +01004664 w F .text 0000010c _ZNSs6appendEPKcm +01016ed4 g F .text 0000005c OS_TaskIdle +01009458 g F .text 000000b0 _ZNSt13runtime_errorC1ERKSs +01003a68 w F .text 000000ec _ZNSsC1ERKSsmm +010237be g O .rwdata 00000002 OSTmrTblSize +0101a778 g F .text 00000180 OSQQuery + + + +Disassembly of section .entry: + +01000000 <__reset>: +#if NIOS2_ICACHE_SIZE > 0 && defined(ALT_ALLOW_CODE_AT_RESET) && !defined(ALT_SIM_OPTIMIZE) + /* Assume the instruction cache size is always a power of two. */ +#if NIOS2_ICACHE_SIZE > 0x8000 + movhi r2, %hi(NIOS2_ICACHE_SIZE) +#else + movui r2, NIOS2_ICACHE_SIZE + 1000000: 00880014 movui r2,8192 +#endif + +0: + initi r2 + 1000004: 1001483a initi r2 + addi r2, r2, -NIOS2_ICACHE_LINE_SIZE + 1000008: 10bff804 addi r2,r2,-32 + bgt r2, zero, 0b + 100000c: 00bffd16 blt zero,r2,1000004 <__reset+0x4> + * Jump to the _start entry point in the .text section if reset code + * is allowed or if optimizing for RTL simulation. + */ +#if defined(ALT_ALLOW_CODE_AT_RESET) || defined(ALT_SIM_OPTIMIZE) + /* Jump to the _start entry point in the .text section. */ + movhi r1, %hi(_start) + 1000010: 00404034 movhi at,256 + ori r1, r1, %lo(_start) + 1000014: 08407014 ori at,at,448 + jmp r1 + 1000018: 0800683a jmp at + 100001c: 00000000 call 0 + +Disassembly of section .exceptions: + +01000020 : + * Process an exception. For all exceptions we must preserve all + * caller saved registers on the stack (See the Nios2 ABI + * documentation for details). + */ + + addi sp, sp, -76 + 1000020: deffed04 addi sp,sp,-76 + +#endif + +#endif + + stw ra, 0(sp) + 1000024: dfc00015 stw ra,0(sp) + /* + * Leave a gap in the stack frame at 4(sp) for the muldiv handler to + * store zero into. + */ + + stw r1, 8(sp) + 1000028: d8400215 stw at,8(sp) + stw r2, 12(sp) + 100002c: d8800315 stw r2,12(sp) + stw r3, 16(sp) + 1000030: d8c00415 stw r3,16(sp) + stw r4, 20(sp) + 1000034: d9000515 stw r4,20(sp) + stw r5, 24(sp) + 1000038: d9400615 stw r5,24(sp) + stw r6, 28(sp) + 100003c: d9800715 stw r6,28(sp) + stw r7, 32(sp) + 1000040: d9c00815 stw r7,32(sp) + + rdctl r5, estatus + 1000044: 000b307a rdctl r5,estatus + + stw r8, 36(sp) + 1000048: da000915 stw r8,36(sp) + stw r9, 40(sp) + 100004c: da400a15 stw r9,40(sp) + stw r10, 44(sp) + 1000050: da800b15 stw r10,44(sp) + stw r11, 48(sp) + 1000054: dac00c15 stw r11,48(sp) + stw r12, 52(sp) + 1000058: db000d15 stw r12,52(sp) + stw r13, 56(sp) + 100005c: db400e15 stw r13,56(sp) + stw r14, 60(sp) + 1000060: db800f15 stw r14,60(sp) + stw r15, 64(sp) + 1000064: dbc01015 stw r15,64(sp) + /* + * ea-4 contains the address of the instruction being executed + * when the exception occured. For interrupt exceptions, we will + * will be re-issue the isntruction. Store it in 72(sp) + */ + stw r5, 68(sp) /* estatus */ + 1000068: d9401115 stw r5,68(sp) + addi r15, ea, -4 /* instruction that caused exception */ + 100006c: ebffff04 addi r15,ea,-4 + stw r15, 72(sp) + 1000070: dbc01215 stw r15,72(sp) +#else + /* + * Test to see if the exception was a software exception or caused + * by an external interrupt, and vector accordingly. + */ + rdctl r4, ipending + 1000074: 0009313a rdctl r4,ipending + andi r2, r5, 1 + 1000078: 2880004c andi r2,r5,1 + beq r2, zero, .Lnot_irq + 100007c: 10000326 beq r2,zero,100008c + beq r4, zero, .Lnot_irq + 1000080: 20000226 beq r4,zero,100008c + /* + * Now that all necessary registers have been preserved, call + * alt_irq_handler() to process the interrupts. + */ + + call alt_irq_handler + 1000084: 10000ec0 call 10000ec + + .section .exceptions.irqreturn, "xa" + + br .Lexception_exit + 1000088: 00000306 br 1000098 + * upon completion, so we write ea (address of instruction *after* + * the one where the exception occured) into 72(sp). The actual + * instruction that caused the exception is written in r2, which these + * handlers will utilize. + */ + stw ea, 72(sp) /* Don't re-issue */ + 100008c: df401215 stw ea,72(sp) + ldw r2, -4(ea) /* Instruction that caused exception */ + 1000090: e8bfff17 ldw r2,-4(ea) +#ifdef NIOS2_HAS_DEBUG_STUB + /* + * Either tell the user now (if there is a debugger attached) or go into + * the debug monitor which will loop until a debugger is attached. + */ + break + 1000094: 003da03a break 0 + /* + * Restore the saved registers, so that all general purpose registers + * have been restored to their state at the time the interrupt occured. + */ + + ldw r5, 68(sp) + 1000098: d9401117 ldw r5,68(sp) + ldw ea, 72(sp) /* This becomes the PC once eret is executed */ + 100009c: df401217 ldw ea,72(sp) + ldw ra, 0(sp) + 10000a0: dfc00017 ldw ra,0(sp) + + wrctl estatus, r5 + 10000a4: 2801707a wrctl estatus,r5 + + ldw r1, 8(sp) + 10000a8: d8400217 ldw at,8(sp) + ldw r2, 12(sp) + 10000ac: d8800317 ldw r2,12(sp) + ldw r3, 16(sp) + 10000b0: d8c00417 ldw r3,16(sp) + ldw r4, 20(sp) + 10000b4: d9000517 ldw r4,20(sp) + ldw r5, 24(sp) + 10000b8: d9400617 ldw r5,24(sp) + ldw r6, 28(sp) + 10000bc: d9800717 ldw r6,28(sp) + ldw r7, 32(sp) + 10000c0: d9c00817 ldw r7,32(sp) +#ifdef ALT_STACK_CHECK + ldw et, %gprel(alt_exception_old_stack_limit)(gp) +#endif +#endif + + ldw r8, 36(sp) + 10000c4: da000917 ldw r8,36(sp) + ldw r9, 40(sp) + 10000c8: da400a17 ldw r9,40(sp) + ldw r10, 44(sp) + 10000cc: da800b17 ldw r10,44(sp) + ldw r11, 48(sp) + 10000d0: dac00c17 ldw r11,48(sp) + ldw r12, 52(sp) + 10000d4: db000d17 ldw r12,52(sp) + ldw r13, 56(sp) + 10000d8: db400e17 ldw r13,56(sp) + ldw r14, 60(sp) + 10000dc: db800f17 ldw r14,60(sp) + ldw r15, 64(sp) + 10000e0: dbc01017 ldw r15,64(sp) +#endif + + ldw sp, 76(sp) + +#else + addi sp, sp, 76 + 10000e4: dec01304 addi sp,sp,76 + + /* + * Return to the interrupted instruction. + */ + + eret + 10000e8: ef80083a eret + +010000ec : + * instruction is present if the macro ALT_CI_INTERRUPT_VECTOR defined. + */ + +void alt_irq_handler (void) __attribute__ ((section (".exceptions"))); +void alt_irq_handler (void) +{ + 10000ec: defff904 addi sp,sp,-28 + 10000f0: dfc00615 stw ra,24(sp) + 10000f4: df000515 stw fp,20(sp) + 10000f8: df000504 addi fp,sp,20 + + /* + * Notify the operating system that we are at interrupt level. + */ + + ALT_OS_INT_ENTER(); + 10000fc: 1015bf40 call 1015bf4 +#ifndef NIOS2_EIC_PRESENT +static ALT_INLINE alt_u32 ALT_ALWAYS_INLINE alt_irq_pending (void) +{ + alt_u32 active; + + NIOS2_READ_IPENDING (active); + 1000100: 0005313a rdctl r2,ipending + 1000104: e0bffc15 stw r2,-16(fp) + + return active; + 1000108: e0bffc17 ldw r2,-16(fp) + * Consider the case where the high priority interupt is asserted during + * the interrupt entry sequence for a lower priority interrupt to see why + * this is the case. + */ + + active = alt_irq_pending (); + 100010c: e0bfff15 stw r2,-4(fp) + + do + { + i = 0; + 1000110: e03ffd15 stw zero,-12(fp) + mask = 1; + 1000114: 00800044 movi r2,1 + 1000118: e0bffe15 stw r2,-8(fp) + * called to clear the interrupt condition. + */ + + do + { + if (active & mask) + 100011c: e0ffff17 ldw r3,-4(fp) + 1000120: e0bffe17 ldw r2,-8(fp) + 1000124: 1884703a and r2,r3,r2 + 1000128: 1005003a cmpeq r2,r2,zero + 100012c: 1000171e bne r2,zero,100018c + { +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT + alt_irq[i].handler(alt_irq[i].context); +#else + alt_irq[i].handler(alt_irq[i].context, i); + 1000130: e0bffd17 ldw r2,-12(fp) + 1000134: 00c040f4 movhi r3,259 + 1000138: 18f3c604 addi r3,r3,-12520 + 100013c: 100490fa slli r2,r2,3 + 1000140: 10c5883a add r2,r2,r3 + 1000144: 11800017 ldw r6,0(r2) + 1000148: e0bffd17 ldw r2,-12(fp) + 100014c: 00c040f4 movhi r3,259 + 1000150: 18f3c604 addi r3,r3,-12520 + 1000154: 100490fa slli r2,r2,3 + 1000158: 10c5883a add r2,r2,r3 + 100015c: 10800104 addi r2,r2,4 + 1000160: 11000017 ldw r4,0(r2) + 1000164: e17ffd17 ldw r5,-12(fp) + 1000168: 303ee83a callr r6 +#ifndef NIOS2_EIC_PRESENT +static ALT_INLINE alt_u32 ALT_ALWAYS_INLINE alt_irq_pending (void) +{ + alt_u32 active; + + NIOS2_READ_IPENDING (active); + 100016c: 0005313a rdctl r2,ipending + 1000170: e0bffb15 stw r2,-20(fp) + + return active; + 1000174: e0bffb17 ldw r2,-20(fp) + mask <<= 1; + i++; + + } while (1); + + active = alt_irq_pending (); + 1000178: e0bfff15 stw r2,-4(fp) + + } while (active); + 100017c: e0bfff17 ldw r2,-4(fp) + 1000180: 1004c03a cmpne r2,r2,zero + 1000184: 103fe21e bne r2,zero,1000110 + 1000188: 00000706 br 10001a8 +#else + alt_irq[i].handler(alt_irq[i].context, i); +#endif + break; + } + mask <<= 1; + 100018c: e0bffe17 ldw r2,-8(fp) + 1000190: 1085883a add r2,r2,r2 + 1000194: e0bffe15 stw r2,-8(fp) + i++; + 1000198: e0bffd17 ldw r2,-12(fp) + 100019c: 10800044 addi r2,r2,1 + 10001a0: e0bffd15 stw r2,-12(fp) + + } while (1); + 10001a4: 003fdd06 br 100011c + + /* + * Notify the operating system that interrupt processing is complete. + */ + + ALT_OS_INT_EXIT(); + 10001a8: 1015c700 call 1015c70 +} + 10001ac: e037883a mov sp,fp + 10001b0: dfc00117 ldw ra,4(sp) + 10001b4: df000017 ldw fp,0(sp) + 10001b8: dec00204 addi sp,sp,8 + 10001bc: f800283a ret + +Disassembly of section .text: + +010001c0 <_start>: + + /* Assume the data cache size is always a power of two. */ +#if NIOS2_DCACHE_SIZE > 0x8000 + movhi r2, %hi(NIOS2_DCACHE_SIZE) +#else + movui r2, NIOS2_DCACHE_SIZE + 10001c0: 00840014 movui r2,4096 +#endif + +0: + initd 0(r2) + 10001c4: 10000033 initd 0(r2) + addi r2, r2, -NIOS2_DCACHE_LINE_SIZE + 10001c8: 10bff804 addi r2,r2,-32 + bgt r2, zero, 0b + 10001cc: 00bffd16 blt zero,r2,10001c4 <_start+0x4> +#if (NIOS2_NUM_OF_SHADOW_REG_SETS == 0) + /* + * Now that the caches are initialized, set up the stack pointer. + * The value provided by the linker is assumed to be correctly aligned. + */ + movhi sp, %hi(__alt_stack_pointer) + 10001d0: 06c08034 movhi sp,512 + ori sp, sp, %lo(__alt_stack_pointer) + 10001d4: dec00014 ori sp,sp,0 + + /* Set up the global pointer. */ + movhi gp, %hi(_gp) + 10001d8: 068040b4 movhi gp,258 + ori gp, gp, %lo(_gp) + 10001dc: d6adb914 ori gp,gp,46820 + */ +#ifndef ALT_SIM_OPTIMIZE + /* Log that the BSS is about to be cleared. */ + ALT_LOG_PUTS(alt_log_msg_bss) + + movhi r2, %hi(__bss_start) + 10001e0: 008040b4 movhi r2,258 + ori r2, r2, %lo(__bss_start) + 10001e4: 1094fa14 ori r2,r2,21480 + + movhi r3, %hi(__bss_end) + 10001e8: 00c040b4 movhi r3,258 + ori r3, r3, %lo(__bss_end) + 10001ec: 18f46a14 ori r3,r3,53672 + + beq r2, r3, 1f + 10001f0: 10c00326 beq r2,r3,1000200 <_start+0x40> + +0: + stw zero, (r2) + 10001f4: 10000015 stw zero,0(r2) + addi r2, r2, 4 + 10001f8: 10800104 addi r2,r2,4 + bltu r2, r3, 0b + 10001fc: 10fffd36 bltu r2,r3,10001f4 <_start+0x34> + * section aren't defined until alt_load() has been called). + */ + mov et, zero +#endif + + call alt_load + 1000200: 10148780 call 1014878 + + /* Log that alt_main is about to be called. */ + ALT_LOG_PUTS(alt_log_msg_alt_main) + + /* Call the C entry point. It should never return. */ + call alt_main + 1000204: 1014ab40 call 1014ab4 + +01000208 : + + /* Wait in infinite loop in case alt_main does return. */ +alt_after_alt_main: + br alt_after_alt_main + 1000208: 003fff06 br 1000208 + +0100020c <_ZN12MotorHandlerC2Ev>: +#define WRITE_FIFO_EMPTY 0x80 +#define MOTOR_ENABLE 1 +#define MOTOR_RESET 0 + +// ALLOCATION +MotorHandler::MotorHandler() {} + 100020c: defffe04 addi sp,sp,-8 + 1000210: df000115 stw fp,4(sp) + 1000214: df000104 addi fp,sp,4 + 1000218: e13fff15 stw r4,-4(fp) + 100021c: 00c040b4 movhi r3,258 + 1000220: 18c3c304 addi r3,r3,3852 + 1000224: e0bfff17 ldw r2,-4(fp) + 1000228: 10c00015 stw r3,0(r2) + 100022c: e037883a mov sp,fp + 1000230: df000017 ldw fp,0(sp) + 1000234: dec00104 addi sp,sp,4 + 1000238: f800283a ret + +0100023c <_ZN12MotorHandlerC1Ev>: + 100023c: defffe04 addi sp,sp,-8 + 1000240: df000115 stw fp,4(sp) + 1000244: df000104 addi fp,sp,4 + 1000248: e13fff15 stw r4,-4(fp) + 100024c: 00c040b4 movhi r3,258 + 1000250: 18c3c304 addi r3,r3,3852 + 1000254: e0bfff17 ldw r2,-4(fp) + 1000258: 10c00015 stw r3,0(r2) + 100025c: e037883a mov sp,fp + 1000260: df000017 ldw fp,0(sp) + 1000264: dec00104 addi sp,sp,4 + 1000268: f800283a ret + +0100026c <_ZN12MotorHandler5resetEv>: + OSTimeDlyHMSM(0, 0, 0, 10); + send(message, description); + } +} + +void MotorHandler::reset(){ + 100026c: defffd04 addi sp,sp,-12 + 1000270: dfc00215 stw ra,8(sp) + 1000274: df000115 stw fp,4(sp) + 1000278: df000104 addi fp,sp,4 + 100027c: e13fff15 stw r4,-4(fp) + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 0); + 1000280: 00808034 movhi r2,512 + 1000284: 10841804 addi r2,r2,4192 + 1000288: 10000035 stwio zero,0(r2) + OSTimeDlyHMSM(0, 0, 0,200 ); + 100028c: 0009883a mov r4,zero + 1000290: 000b883a mov r5,zero + 1000294: 000d883a mov r6,zero + 1000298: 01c03204 movi r7,200 + 100029c: 101d0f80 call 101d0f8 + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 1); + 10002a0: 00c08034 movhi r3,512 + 10002a4: 18c41804 addi r3,r3,4192 + 10002a8: 00800044 movi r2,1 + 10002ac: 18800035 stwio r2,0(r3) + OSTimeDlyHMSM(0, 0, 0, 200); + 10002b0: 0009883a mov r4,zero + 10002b4: 000b883a mov r5,zero + 10002b8: 000d883a mov r6,zero + 10002bc: 01c03204 movi r7,200 + 10002c0: 101d0f80 call 101d0f8 +} + 10002c4: e037883a mov sp,fp + 10002c8: dfc00117 ldw ra,4(sp) + 10002cc: df000017 ldw fp,0(sp) + 10002d0: dec00204 addi sp,sp,8 + 10002d4: f800283a ret + +010002d8 <_ZN12MotorHandler4sendEcPKc>: +/* + * Sends a byte-length message to the motor controller. + * @param message - the message to send + * @param description - the string description of the message, for debugging + */ +void MotorHandler::send(char message, const char *description) { + 10002d8: defff904 addi sp,sp,-28 + 10002dc: dfc00615 stw ra,24(sp) + 10002e0: df000515 stw fp,20(sp) + 10002e4: df000504 addi fp,sp,20 + 10002e8: e13ffd15 stw r4,-12(fp) + 10002ec: e1bfff15 stw r6,-4(fp) + 10002f0: e17ffe05 stb r5,-8(fp) + alt_u32 write_space; + // Check for write space. + write_space = alt_up_rs232_get_available_space_in_write_FIFO(motor_dev); + 10002f4: e0bffd17 ldw r2,-12(fp) + 10002f8: 11000117 ldw r4,4(r2) + 10002fc: 101f19c0 call 101f19c + 1000300: e0bffc15 stw r2,-16(fp) + if (write_space >= WRITE_FIFO_EMPTY) { + 1000304: e0bffc17 ldw r2,-16(fp) + 1000308: 10802030 cmpltui r2,r2,128 + 100030c: 1000161e bne r2,zero,1000368 <_ZN12MotorHandler4sendEcPKc+0x90> + // If space, write. + int status = alt_up_rs232_write_data(motor_dev, message); + 1000310: e0bffd17 ldw r2,-12(fp) + 1000314: 11000117 ldw r4,4(r2) + 1000318: e0bffe03 ldbu r2,-8(fp) + 100031c: 11403fcc andi r5,r2,255 + 1000320: 101f22c0 call 101f22c + 1000324: e0bffb15 stw r2,-20(fp) + printf("MotorHandler [message: 0x%02x, description: %s", message, description); + 1000328: e17ffe07 ldb r5,-8(fp) + 100032c: 010040b4 movhi r4,258 + 1000330: 21038004 addi r4,r4,3584 + 1000334: e1bfff17 ldw r6,-4(fp) + 1000338: 100ac540 call 100ac54 + // Log errors. + if (status == OK) { + 100033c: e0bffb17 ldw r2,-20(fp) + 1000340: 1004c03a cmpne r2,r2,zero + 1000344: 1000041e bne r2,zero,1000358 <_ZN12MotorHandler4sendEcPKc+0x80> + printf("]\n"); + 1000348: 010040b4 movhi r4,258 + 100034c: 21038c04 addi r4,r4,3632 + 1000350: 100ad900 call 100ad90 + 1000354: 00001206 br 10003a0 <_ZN12MotorHandler4sendEcPKc+0xc8> + } else { + printf(", error: cannot write]\n"); + 1000358: 010040b4 movhi r4,258 + 100035c: 21038d04 addi r4,r4,3636 + 1000360: 100ad900 call 100ad90 + 1000364: 00000e06 br 10003a0 <_ZN12MotorHandler4sendEcPKc+0xc8> + } + } else { + // If no space, wait and retry. + printf("MotorHandler [message: 0x%02x, description: %s, error: no write space; retrying]\n", message, description); + 1000368: e17ffe07 ldb r5,-8(fp) + 100036c: 010040b4 movhi r4,258 + 1000370: 21039304 addi r4,r4,3660 + 1000374: e1bfff17 ldw r6,-4(fp) + 1000378: 100ac540 call 100ac54 + OSTimeDlyHMSM(0, 0, 0, 10); + 100037c: 0009883a mov r4,zero + 1000380: 000b883a mov r5,zero + 1000384: 000d883a mov r6,zero + 1000388: 01c00284 movi r7,10 + 100038c: 101d0f80 call 101d0f8 + send(message, description); + 1000390: e17ffe07 ldb r5,-8(fp) + 1000394: e13ffd17 ldw r4,-12(fp) + 1000398: e1bfff17 ldw r6,-4(fp) + 100039c: 10002d80 call 10002d8 <_ZN12MotorHandler4sendEcPKc> + } +} + 10003a0: e037883a mov sp,fp + 10003a4: dfc00117 ldw ra,4(sp) + 10003a8: df000017 ldw fp,0(sp) + 10003ac: dec00204 addi sp,sp,8 + 10003b0: f800283a ret + +010003b4 <_ZN12MotorHandler4moveEccPKc>: + * @param MotorDirection Motor and direction to move + * @param Speed the speed to move at + * @param string description of motor movement + */ + +void MotorHandler::move(char motorDirection, char speed,const char *description){ + 10003b4: defffa04 addi sp,sp,-24 + 10003b8: dfc00515 stw ra,20(sp) + 10003bc: df000415 stw fp,16(sp) + 10003c0: df000404 addi fp,sp,16 + 10003c4: e13ffc15 stw r4,-16(fp) + 10003c8: e1ffff15 stw r7,-4(fp) + 10003cc: e17ffd05 stb r5,-12(fp) + 10003d0: e1bffe05 stb r6,-8(fp) + send(MOTOR_START_BYTE, "start"); + 10003d4: e13ffc17 ldw r4,-16(fp) + 10003d8: 017fe004 movi r5,-128 + 10003dc: 018040b4 movhi r6,258 + 10003e0: 3183a804 addi r6,r6,3744 + 10003e4: 10002d80 call 10002d8 <_ZN12MotorHandler4sendEcPKc> + send(MOTOR_DEVICE_TYPE, "device"); + 10003e8: e13ffc17 ldw r4,-16(fp) + 10003ec: 000b883a mov r5,zero + 10003f0: 018040b4 movhi r6,258 + 10003f4: 3183aa04 addi r6,r6,3752 + 10003f8: 10002d80 call 10002d8 <_ZN12MotorHandler4sendEcPKc> + send(motorDirection, description); + 10003fc: e17ffd07 ldb r5,-12(fp) + 1000400: e13ffc17 ldw r4,-16(fp) + 1000404: e1bfff17 ldw r6,-4(fp) + 1000408: 10002d80 call 10002d8 <_ZN12MotorHandler4sendEcPKc> + send(speed, "speed"); + 100040c: e17ffe07 ldb r5,-8(fp) + 1000410: e13ffc17 ldw r4,-16(fp) + 1000414: 018040b4 movhi r6,258 + 1000418: 3183ac04 addi r6,r6,3760 + 100041c: 10002d80 call 10002d8 <_ZN12MotorHandler4sendEcPKc> + printf("\n"); + 1000420: 01000284 movi r4,10 + 1000424: 100accc0 call 100accc +} + 1000428: e037883a mov sp,fp + 100042c: dfc00117 ldw ra,4(sp) + 1000430: df000017 ldw fp,0(sp) + 1000434: dec00204 addi sp,sp,8 + 1000438: f800283a ret + +0100043c <_ZN12MotorHandler9configureEv>: + } else { + return OK; + } +} + +void MotorHandler::configure(){ + 100043c: defffd04 addi sp,sp,-12 + 1000440: dfc00215 stw ra,8(sp) + 1000444: df000115 stw fp,4(sp) + 1000448: df000104 addi fp,sp,4 + 100044c: e13fff15 stw r4,-4(fp) + send(MOTOR_START_BYTE, "start"); + 1000450: e13fff17 ldw r4,-4(fp) + 1000454: 017fe004 movi r5,-128 + 1000458: 018040b4 movhi r6,258 + 100045c: 3183a804 addi r6,r6,3744 + 1000460: 10002d80 call 10002d8 <_ZN12MotorHandler4sendEcPKc> + send(MOTOR_CHANGE_CONFIGURATION, "change configuration"); + 1000464: e13fff17 ldw r4,-4(fp) + 1000468: 01400084 movi r5,2 + 100046c: 018040b4 movhi r6,258 + 1000470: 3183ae04 addi r6,r6,3768 + 1000474: 10002d80 call 10002d8 <_ZN12MotorHandler4sendEcPKc> + send(0X01, "2 MOTOR CONFIG"); + 1000478: e13fff17 ldw r4,-4(fp) + 100047c: 01400044 movi r5,1 + 1000480: 018040b4 movhi r6,258 + 1000484: 3183b404 addi r6,r6,3792 + 1000488: 10002d80 call 10002d8 <_ZN12MotorHandler4sendEcPKc> + printf("\n"); + 100048c: 01000284 movi r4,10 + 1000490: 100accc0 call 100accc +} + 1000494: e037883a mov sp,fp + 1000498: dfc00117 ldw ra,4(sp) + 100049c: df000017 ldw fp,0(sp) + 10004a0: dec00204 addi sp,sp,8 + 10004a4: f800283a ret + +010004a8 <_ZN12MotorHandler18interpretDirectionESsi>: + else{ + return MOTOR_RIGHT_CHAR; + } +} + +char MotorHandler::interpretDirection(string direction, int motor){ + 10004a8: defffa04 addi sp,sp,-24 + 10004ac: dfc00515 stw ra,20(sp) + 10004b0: df000415 stw fp,16(sp) + 10004b4: df000404 addi fp,sp,16 + 10004b8: e13ffc15 stw r4,-16(fp) + 10004bc: e17ffd15 stw r5,-12(fp) + 10004c0: e1bffe15 stw r6,-8(fp) + if(direction.compare(MOTOR_FORWARD) == 0){ + 10004c4: e13ffd17 ldw r4,-12(fp) + 10004c8: 014040b4 movhi r5,258 + 10004cc: 2943b804 addi r5,r5,3808 + 10004d0: 100300c0 call 100300c <_ZNKSs7compareEPKc> + 10004d4: 1005003a cmpeq r2,r2,zero + 10004d8: 10803fcc andi r2,r2,255 + 10004dc: 1005003a cmpeq r2,r2,zero + 10004e0: 1000081e bne r2,zero,1000504 <_ZN12MotorHandler18interpretDirectionESsi+0x5c> + return (char) (motor*2 + 1); + 10004e4: e0bffe17 ldw r2,-8(fp) + 10004e8: 1085883a add r2,r2,r2 + 10004ec: 10800044 addi r2,r2,1 + 10004f0: 10803fcc andi r2,r2,255 + 10004f4: 1080201c xori r2,r2,128 + 10004f8: 10bfe004 addi r2,r2,-128 + 10004fc: e0bfff15 stw r2,-4(fp) + 1000500: 00000606 br 100051c <_ZN12MotorHandler18interpretDirectionESsi+0x74> + } + else{ + return (char) (motor*2); + 1000504: e0bffe17 ldw r2,-8(fp) + 1000508: 1085883a add r2,r2,r2 + 100050c: 10803fcc andi r2,r2,255 + 1000510: 1080201c xori r2,r2,128 + 1000514: 10bfe004 addi r2,r2,-128 + 1000518: e0bfff15 stw r2,-4(fp) + 100051c: e0bfff17 ldw r2,-4(fp) + } +} + 1000520: e037883a mov sp,fp + 1000524: dfc00117 ldw ra,4(sp) + 1000528: df000017 ldw fp,0(sp) + 100052c: dec00204 addi sp,sp,8 + 1000530: f800283a ret + +01000534 <_ZN12MotorHandler14interpretMotorESs>: + int speedByte = strtol(speed.c_str(), NULL, 0); + move(directionByte, speedByte, (motor.append(motorDirection)).c_str()); +} + + +char MotorHandler::interpretMotor(string motor){ + 1000534: defffb04 addi sp,sp,-20 + 1000538: dfc00415 stw ra,16(sp) + 100053c: df000315 stw fp,12(sp) + 1000540: df000304 addi fp,sp,12 + 1000544: e13ffd15 stw r4,-12(fp) + 1000548: e17ffe15 stw r5,-8(fp) + if(motor.compare(MOTOR_LEFT) == 0){ + 100054c: e13ffe17 ldw r4,-8(fp) + 1000550: 014040b4 movhi r5,258 + 1000554: 2943ba04 addi r5,r5,3816 + 1000558: 100300c0 call 100300c <_ZNKSs7compareEPKc> + 100055c: 1005003a cmpeq r2,r2,zero + 1000560: 10803fcc andi r2,r2,255 + 1000564: 1005003a cmpeq r2,r2,zero + 1000568: 1000031e bne r2,zero,1000578 <_ZN12MotorHandler14interpretMotorESs+0x44> + return MOTOR_LEFT_CHAR; + 100056c: 00800084 movi r2,2 + 1000570: e0bfff15 stw r2,-4(fp) + 1000574: 00000206 br 1000580 <_ZN12MotorHandler14interpretMotorESs+0x4c> + } + else{ + return MOTOR_RIGHT_CHAR; + 1000578: 008000c4 movi r2,3 + 100057c: e0bfff15 stw r2,-4(fp) + 1000580: e0bfff17 ldw r2,-4(fp) + } +} + 1000584: e037883a mov sp,fp + 1000588: dfc00117 ldw ra,4(sp) + 100058c: df000017 ldw fp,0(sp) + 1000590: dec00204 addi sp,sp,8 + 1000594: f800283a ret + +01000598 <_ZN12MotorHandler12motorCommandESsSsSs>: + * Interprets the command from the network handler and sends move commands + * @param motor The motor to move eg. Left or Right + * @param motorDirection The direction of the given motor to move + * @param speed The speed the motor is to move + */ +void MotorHandler::motorCommand(string motor, string motorDirection, string speed){ + 1000598: deffdb04 addi sp,sp,-148 + 100059c: dfc02415 stw ra,144(sp) + 10005a0: df002315 stw fp,140(sp) + 10005a4: ddc02215 stw r23,136(sp) + 10005a8: dd802115 stw r22,132(sp) + 10005ac: dd402015 stw r21,128(sp) + 10005b0: dd001f15 stw r20,124(sp) + 10005b4: dcc01e15 stw r19,120(sp) + 10005b8: dc801d15 stw r18,116(sp) + 10005bc: dc401c15 stw r17,112(sp) + 10005c0: dc001b15 stw r16,108(sp) + 10005c4: df001b04 addi fp,sp,108 + 10005c8: e13fe915 stw r4,-92(fp) + 10005cc: e17fea15 stw r5,-88(fp) + 10005d0: e1bfeb15 stw r6,-84(fp) + 10005d4: e1ffec15 stw r7,-80(fp) + 10005d8: 00804034 movhi r2,256 + 10005dc: 109a9704 addi r2,r2,27228 + 10005e0: e0bff315 stw r2,-52(fp) + 10005e4: 008040b4 movhi r2,258 + 10005e8: 1082b304 addi r2,r2,2764 + 10005ec: e0bff415 stw r2,-48(fp) + 10005f0: e0bff504 addi r2,fp,-44 + 10005f4: e0ffe504 addi r3,fp,-108 + 10005f8: 10c00015 stw r3,0(r2) + 10005fc: 00c04034 movhi r3,256 + 1000600: 18c1c904 addi r3,r3,1828 + 1000604: 10c00115 stw r3,4(r2) + 1000608: 16c00215 stw sp,8(r2) + 100060c: e13fed04 addi r4,fp,-76 + 1000610: 1009c1c0 call 1009c1c <_Unwind_SjLj_Register> + char motorID = interpretMotor(motor); + 1000614: e13fe804 addi r4,fp,-96 + 1000618: 00bfffc4 movi r2,-1 + 100061c: e0bfee15 stw r2,-72(fp) + 1000620: e17fea17 ldw r5,-88(fp) + 1000624: 10040640 call 1004064 <_ZNSsC1ERKSs> + 1000628: e17fe804 addi r5,fp,-96 + 100062c: 00800084 movi r2,2 + 1000630: e0bfee15 stw r2,-72(fp) + 1000634: e13fe917 ldw r4,-92(fp) + 1000638: 10005340 call 1000534 <_ZN12MotorHandler14interpretMotorESs> + 100063c: e0bfe645 stb r2,-103(fp) + 1000640: e13fe804 addi r4,fp,-96 + 1000644: 00bfffc4 movi r2,-1 + 1000648: e0bfee15 stw r2,-72(fp) + 100064c: 1004a240 call 1004a24 <_ZNSsD1Ev> + char directionByte = interpretDirection(motorDirection, int(motorID)); + 1000650: e13fe704 addi r4,fp,-100 + 1000654: e17feb17 ldw r5,-84(fp) + 1000658: 10040640 call 1004064 <_ZNSsC1ERKSs> + 100065c: e1bfe647 ldb r6,-103(fp) + 1000660: e17fe704 addi r5,fp,-100 + 1000664: 00800044 movi r2,1 + 1000668: e0bfee15 stw r2,-72(fp) + 100066c: e13fe917 ldw r4,-92(fp) + 1000670: 10004a80 call 10004a8 <_ZN12MotorHandler18interpretDirectionESsi> + 1000674: e0bffe05 stb r2,-8(fp) + 1000678: 00000b06 br 10006a8 <_ZN12MotorHandler12motorCommandESsSsSs+0x110> + 100067c: e0bfff17 ldw r2,-4(fp) + 1000680: e0bffb15 stw r2,-20(fp) + * @param motor The motor to move eg. Left or Right + * @param motorDirection The direction of the given motor to move + * @param speed The speed the motor is to move + */ +void MotorHandler::motorCommand(string motor, string motorDirection, string speed){ + char motorID = interpretMotor(motor); + 1000684: e13fe804 addi r4,fp,-96 + 1000688: e03fee15 stw zero,-72(fp) + 100068c: 1004a240 call 1004a24 <_ZNSsD1Ev> + 1000690: e0fffb17 ldw r3,-20(fp) + 1000694: e0ffff15 stw r3,-4(fp) + 1000698: 00bfffc4 movi r2,-1 + 100069c: e0bfee15 stw r2,-72(fp) + 10006a0: e13fff17 ldw r4,-4(fp) + 10006a4: 1009ee80 call 1009ee8 <_Unwind_SjLj_Resume> + char directionByte = interpretDirection(motorDirection, int(motorID)); + 10006a8: e0bffe03 ldbu r2,-8(fp) + 10006ac: e0bfe605 stb r2,-104(fp) + 10006b0: e13fe704 addi r4,fp,-100 + 10006b4: 00bfffc4 movi r2,-1 + 10006b8: e0bfee15 stw r2,-72(fp) + 10006bc: 1004a240 call 1004a24 <_ZNSsD1Ev> + int speedByte = strtol(speed.c_str(), NULL, 0); + 10006c0: e13fec17 ldw r4,-80(fp) + 10006c4: 10026d80 call 10026d8 <_ZNKSs5c_strEv> + 10006c8: 1009883a mov r4,r2 + 10006cc: 000b883a mov r5,zero + 10006d0: 000d883a mov r6,zero + 10006d4: 100b41c0 call 100b41c + 10006d8: e0bfe515 stw r2,-108(fp) + move(directionByte, speedByte, (motor.append(motorDirection)).c_str()); + 10006dc: e0ffe607 ldb r3,-104(fp) + 10006e0: e0fffd15 stw r3,-12(fp) + 10006e4: e0bfe517 ldw r2,-108(fp) + 10006e8: 10803fcc andi r2,r2,255 + 10006ec: 1080201c xori r2,r2,128 + 10006f0: 10bfe004 addi r2,r2,-128 + 10006f4: e0bffc15 stw r2,-16(fp) + 10006f8: e13fea17 ldw r4,-88(fp) + 10006fc: e17feb17 ldw r5,-84(fp) + 1000700: 10048d80 call 10048d8 <_ZNSs6appendERKSs> + 1000704: 1009883a mov r4,r2 + 1000708: 10026d80 call 10026d8 <_ZNKSs5c_strEv> + 100070c: 100f883a mov r7,r2 + 1000710: e13fe917 ldw r4,-92(fp) + 1000714: e17ffd17 ldw r5,-12(fp) + 1000718: e1bffc17 ldw r6,-16(fp) + 100071c: 10003b40 call 10003b4 <_ZN12MotorHandler4moveEccPKc> +} + 1000720: 00001106 br 1000768 <_ZN12MotorHandler12motorCommandESsSsSs+0x1d0> + 1000724: e7001b04 addi fp,fp,108 + 1000728: e0bfee17 ldw r2,-72(fp) + 100072c: e0ffef17 ldw r3,-68(fp) + 1000730: e0ffff15 stw r3,-4(fp) + 1000734: 10800060 cmpeqi r2,r2,1 + 1000738: 103fd01e bne r2,zero,100067c <_ZN12MotorHandler12motorCommandESsSsSs+0xe4> + 100073c: e0bfff17 ldw r2,-4(fp) + 1000740: e0bffa15 stw r2,-24(fp) + * @param motorDirection The direction of the given motor to move + * @param speed The speed the motor is to move + */ +void MotorHandler::motorCommand(string motor, string motorDirection, string speed){ + char motorID = interpretMotor(motor); + char directionByte = interpretDirection(motorDirection, int(motorID)); + 1000744: e13fe704 addi r4,fp,-100 + 1000748: e03fee15 stw zero,-72(fp) + 100074c: 1004a240 call 1004a24 <_ZNSsD1Ev> + 1000750: e0fffa17 ldw r3,-24(fp) + 1000754: e0ffff15 stw r3,-4(fp) + 1000758: 00bfffc4 movi r2,-1 + 100075c: e0bfee15 stw r2,-72(fp) + 1000760: e13fff17 ldw r4,-4(fp) + 1000764: 1009ee80 call 1009ee8 <_Unwind_SjLj_Resume> + 1000768: e13fed04 addi r4,fp,-76 + 100076c: 1009c2c0 call 1009c2c <_Unwind_SjLj_Unregister> + int speedByte = strtol(speed.c_str(), NULL, 0); + move(directionByte, speedByte, (motor.append(motorDirection)).c_str()); +} + 1000770: e037883a mov sp,fp + 1000774: dfc00917 ldw ra,36(sp) + 1000778: df000817 ldw fp,32(sp) + 100077c: ddc00717 ldw r23,28(sp) + 1000780: dd800617 ldw r22,24(sp) + 1000784: dd400517 ldw r21,20(sp) + 1000788: dd000417 ldw r20,16(sp) + 100078c: dcc00317 ldw r19,12(sp) + 1000790: dc800217 ldw r18,8(sp) + 1000794: dc400117 ldw r17,4(sp) + 1000798: dc000017 ldw r16,0(sp) + 100079c: dec00a04 addi sp,sp,40 + 10007a0: f800283a ret + +010007a4 <_ZN12MotorHandler4initEv>: + +/* + * Initializes this handler. + * @return OK if the handler was initialized without error + */ +Status MotorHandler::init() { + 10007a4: defffc04 addi sp,sp,-16 + 10007a8: dfc00315 stw ra,12(sp) + 10007ac: df000215 stw fp,8(sp) + 10007b0: df000204 addi fp,sp,8 + 10007b4: e13ffe15 stw r4,-8(fp) + // Enable the motor controller. + reset(); + 10007b8: e13ffe17 ldw r4,-8(fp) + 10007bc: 100026c0 call 100026c <_ZN12MotorHandler5resetEv> + // Open the serial device to send commands to the motor controller. + motor_dev = alt_up_rs232_open_dev(RS232_MOTOR_NAME); + 10007c0: 010040b4 movhi r4,258 + 10007c4: 2103bc04 addi r4,r4,3824 + 10007c8: 101f40c0 call 101f40c + 10007cc: 1007883a mov r3,r2 + 10007d0: e0bffe17 ldw r2,-8(fp) + 10007d4: 10c00115 stw r3,4(r2) + //printf("%d", motor_dev); + if (motor_dev == NULL) { + 10007d8: e0bffe17 ldw r2,-8(fp) + 10007dc: 10800117 ldw r2,4(r2) + 10007e0: 1004c03a cmpne r2,r2,zero + 10007e4: 1000031e bne r2,zero,10007f4 <_ZN12MotorHandler4initEv+0x50> + return ERR_MOTOR_OPEN; + 10007e8: 00800044 movi r2,1 + 10007ec: e0bfff15 stw r2,-4(fp) + 10007f0: 00000106 br 10007f8 <_ZN12MotorHandler4initEv+0x54> + } else { + return OK; + 10007f4: e03fff15 stw zero,-4(fp) + 10007f8: e0bfff17 ldw r2,-4(fp) + } +} + 10007fc: e037883a mov sp,fp + 1000800: dfc00117 ldw ra,4(sp) + 1000804: df000017 ldw fp,0(sp) + 1000808: dec00204 addi sp,sp,8 + 100080c: f800283a ret + +01000810 <_ZN12MotorHandlerD0Ev>: +#define MOTOR_ENABLE 1 +#define MOTOR_RESET 0 + +// ALLOCATION +MotorHandler::MotorHandler() {} +MotorHandler::~MotorHandler() {} + 1000810: defffd04 addi sp,sp,-12 + 1000814: dfc00215 stw ra,8(sp) + 1000818: df000115 stw fp,4(sp) + 100081c: df000104 addi fp,sp,4 + 1000820: e13fff15 stw r4,-4(fp) + 1000824: 00c040b4 movhi r3,258 + 1000828: 18c3c304 addi r3,r3,3852 + 100082c: e0bfff17 ldw r2,-4(fp) + 1000830: 10c00015 stw r3,0(r2) + 1000834: 00800044 movi r2,1 + 1000838: 10803fcc andi r2,r2,255 + 100083c: 1005003a cmpeq r2,r2,zero + 1000840: 1000021e bne r2,zero,100084c <_ZN12MotorHandlerD0Ev+0x3c> + 1000844: e13fff17 ldw r4,-4(fp) + 1000848: 100722c0 call 100722c <_ZdlPv> + 100084c: e037883a mov sp,fp + 1000850: dfc00117 ldw ra,4(sp) + 1000854: df000017 ldw fp,0(sp) + 1000858: dec00204 addi sp,sp,8 + 100085c: f800283a ret + +01000860 <_ZN12MotorHandlerD1Ev>: + 1000860: defffd04 addi sp,sp,-12 + 1000864: dfc00215 stw ra,8(sp) + 1000868: df000115 stw fp,4(sp) + 100086c: df000104 addi fp,sp,4 + 1000870: e13fff15 stw r4,-4(fp) + 1000874: 00c040b4 movhi r3,258 + 1000878: 18c3c304 addi r3,r3,3852 + 100087c: e0bfff17 ldw r2,-4(fp) + 1000880: 10c00015 stw r3,0(r2) + 1000884: 0005883a mov r2,zero + 1000888: 10803fcc andi r2,r2,255 + 100088c: 1005003a cmpeq r2,r2,zero + 1000890: 1000021e bne r2,zero,100089c <_ZN12MotorHandlerD1Ev+0x3c> + 1000894: e13fff17 ldw r4,-4(fp) + 1000898: 100722c0 call 100722c <_ZdlPv> + 100089c: e037883a mov sp,fp + 10008a0: dfc00117 ldw ra,4(sp) + 10008a4: df000017 ldw fp,0(sp) + 10008a8: dec00204 addi sp,sp,8 + 10008ac: f800283a ret + +010008b0 <_ZN12MotorHandlerD2Ev>: + 10008b0: defffd04 addi sp,sp,-12 + 10008b4: dfc00215 stw ra,8(sp) + 10008b8: df000115 stw fp,4(sp) + 10008bc: df000104 addi fp,sp,4 + 10008c0: e13fff15 stw r4,-4(fp) + 10008c4: 00c040b4 movhi r3,258 + 10008c8: 18c3c304 addi r3,r3,3852 + 10008cc: e0bfff17 ldw r2,-4(fp) + 10008d0: 10c00015 stw r3,0(r2) + 10008d4: 0005883a mov r2,zero + 10008d8: 10803fcc andi r2,r2,255 + 10008dc: 1005003a cmpeq r2,r2,zero + 10008e0: 1000021e bne r2,zero,10008ec <_ZN12MotorHandlerD2Ev+0x3c> + 10008e4: e13fff17 ldw r4,-4(fp) + 10008e8: 100722c0 call 100722c <_ZdlPv> + 10008ec: e037883a mov sp,fp + 10008f0: dfc00117 ldw ra,4(sp) + 10008f4: df000017 ldw fp,0(sp) + 10008f8: dec00204 addi sp,sp,8 + 10008fc: f800283a ret + +01000900 <_Z41__static_initialization_and_destruction_0ii>: + if (status == OK) { + OSStart(); + } + + return 0; +} + 1000900: deffe404 addi sp,sp,-112 + 1000904: dfc01b15 stw ra,108(sp) + 1000908: df001a15 stw fp,104(sp) + 100090c: ddc01915 stw r23,100(sp) + 1000910: dd801815 stw r22,96(sp) + 1000914: dd401715 stw r21,92(sp) + 1000918: dd001615 stw r20,88(sp) + 100091c: dcc01515 stw r19,84(sp) + 1000920: dc801415 stw r18,80(sp) + 1000924: dc401315 stw r17,76(sp) + 1000928: dc001215 stw r16,72(sp) + 100092c: df001204 addi fp,sp,72 + 1000930: e13fee15 stw r4,-72(fp) + 1000934: e17fef15 stw r5,-68(fp) + 1000938: 00804034 movhi r2,256 + 100093c: 109a9704 addi r2,r2,27228 + 1000940: e0bff615 stw r2,-40(fp) + 1000944: 008040b4 movhi r2,258 + 1000948: 1082b504 addi r2,r2,2772 + 100094c: e0bff715 stw r2,-36(fp) + 1000950: e0bff804 addi r2,fp,-32 + 1000954: e0ffee04 addi r3,fp,-72 + 1000958: 10c00015 stw r3,0(r2) + 100095c: 00c04034 movhi r3,256 + 1000960: 18c26f04 addi r3,r3,2492 + 1000964: 10c00115 stw r3,4(r2) + 1000968: 16c00215 stw sp,8(r2) + 100096c: e13ff004 addi r4,fp,-64 + 1000970: 1009c1c0 call 1009c1c <_Unwind_SjLj_Register> + 1000974: e0bfee17 ldw r2,-72(fp) + 1000978: 10800058 cmpnei r2,r2,1 + 100097c: 10001c1e bne r2,zero,10009f0 <_Z41__static_initialization_and_destruction_0ii+0xf0> + 1000980: e0ffef17 ldw r3,-68(fp) + 1000984: 00bfffd4 movui r2,65535 + 1000988: 1880191e bne r3,r2,10009f0 <_Z41__static_initialization_and_destruction_0ii+0xf0> +// and invert pushbutton input (since the pushbutton returns 0 when it is pushed down). +#define IR_QUEUE_SEND_BASE 1 // Use: IR_QUEUE_SEND_BASE + IORD +#define IR_QUEUE_RECEIVE_BASE 2 // Use: IR_QUEUE_RECEIVE_BASE - OSQPend + + +MotorHandler *motor= new MotorHandler(); + 100098c: 00bfffc4 movi r2,-1 + 1000990: e0bff115 stw r2,-60(fp) + 1000994: 01000204 movi r4,8 + 1000998: 10077140 call 1007714 <_Znwm> + 100099c: e0bffe15 stw r2,-8(fp) + 10009a0: 00800044 movi r2,1 + 10009a4: e0bff115 stw r2,-60(fp) + 10009a8: e13ffe17 ldw r4,-8(fp) + 10009ac: 100023c0 call 100023c <_ZN12MotorHandlerC1Ev> + 10009b0: e0bffe17 ldw r2,-8(fp) + 10009b4: d0a74515 stw r2,-25324(gp) + 10009b8: 00000d06 br 10009f0 <_Z41__static_initialization_and_destruction_0ii+0xf0> + 10009bc: e7001204 addi fp,fp,72 + 10009c0: e0fff217 ldw r3,-56(fp) + 10009c4: e0ffff15 stw r3,-4(fp) + 10009c8: e0bfff17 ldw r2,-4(fp) + 10009cc: e0bffd15 stw r2,-12(fp) + 10009d0: e13ffe17 ldw r4,-8(fp) + 10009d4: 100722c0 call 100722c <_ZdlPv> + 10009d8: e0fffd17 ldw r3,-12(fp) + 10009dc: e0ffff15 stw r3,-4(fp) + 10009e0: 00bfffc4 movi r2,-1 + 10009e4: e0bff115 stw r2,-60(fp) + 10009e8: e13fff17 ldw r4,-4(fp) + 10009ec: 1009ee80 call 1009ee8 <_Unwind_SjLj_Resume> + 10009f0: e13ff004 addi r4,fp,-64 + 10009f4: 1009c2c0 call 1009c2c <_Unwind_SjLj_Unregister> + if (status == OK) { + OSStart(); + } + + return 0; +} + 10009f8: e037883a mov sp,fp + 10009fc: dfc00917 ldw ra,36(sp) + 1000a00: df000817 ldw fp,32(sp) + 1000a04: ddc00717 ldw r23,28(sp) + 1000a08: dd800617 ldw r22,24(sp) + 1000a0c: dd400517 ldw r21,20(sp) + 1000a10: dd000417 ldw r20,16(sp) + 1000a14: dcc00317 ldw r19,12(sp) + 1000a18: dc800217 ldw r18,8(sp) + 1000a1c: dc400117 ldw r17,4(sp) + 1000a20: dc000017 ldw r16,0(sp) + 1000a24: dec00a04 addi sp,sp,40 + 1000a28: f800283a ret + +01000a2c <_GLOBAL__I_ir_task_stk>: + + 1000a2c: defffe04 addi sp,sp,-8 + 1000a30: dfc00115 stw ra,4(sp) + 1000a34: df000015 stw fp,0(sp) + 1000a38: d839883a mov fp,sp + 1000a3c: 01000044 movi r4,1 + 1000a40: 017fffd4 movui r5,65535 + 1000a44: 10009000 call 1000900 <_Z41__static_initialization_and_destruction_0ii> + 1000a48: e037883a mov sp,fp + 1000a4c: dfc00117 ldw ra,4(sp) + 1000a50: df000017 ldw fp,0(sp) + 1000a54: dec00204 addi sp,sp,8 + 1000a58: f800283a ret + +01000a5c <_Z10queue_initv>: + + + +// ==== GENERAL + +void queue_init() { + 1000a5c: defffe04 addi sp,sp,-8 + 1000a60: dfc00115 stw ra,4(sp) + 1000a64: df000015 stw fp,0(sp) + 1000a68: d839883a mov fp,sp + ir_queue = OSQCreate((void**)&ir_messages, IR_MAX_MESSAGES); + 1000a6c: 010040f4 movhi r4,259 + 1000a70: 21252b04 addi r4,r4,-27476 + 1000a74: 01400104 movi r5,4 + 1000a78: 10197c40 call 10197c4 + 1000a7c: d0a74415 stw r2,-25328(gp) +} + 1000a80: e037883a mov sp,fp + 1000a84: dfc00117 ldw ra,4(sp) + 1000a88: df000017 ldw fp,0(sp) + 1000a8c: dec00204 addi sp,sp,8 + 1000a90: f800283a ret + +01000a94
: + +/* The main function creates the LCD task, registers the edge counter polling interrupt, + * and starts the OS. */ +int main(void) + 1000a94: defff804 addi sp,sp,-32 + 1000a98: dfc00715 stw ra,28(sp) + 1000a9c: df000615 stw fp,24(sp) + 1000aa0: df000604 addi fp,sp,24 +{ + int status = OK; + 1000aa4: e03fff15 stw zero,-4(fp) + // Initialize components. + queue_init(); + 1000aa8: 1000a5c0 call 1000a5c <_Z10queue_initv> + MC_TASK_PRIORITY, + MC_TASK_PRIORITY, + mc_task_stk, + TASK_STACKSIZE, + NULL, + 0); + 1000aac: 00800044 movi r2,1 + 1000ab0: d8800015 stw r2,0(sp) + 1000ab4: 008040b4 movhi r2,258 + 1000ab8: 109d2b04 addi r2,r2,29868 + 1000abc: d8800115 stw r2,4(sp) + 1000ac0: 00820004 movi r2,2048 + 1000ac4: d8800215 stw r2,8(sp) + 1000ac8: d8000315 stw zero,12(sp) + 1000acc: d8000415 stw zero,16(sp) + 1000ad0: 01004034 movhi r4,256 + 1000ad4: 2102c504 addi r4,r4,2836 + 1000ad8: 000b883a mov r5,zero + 1000adc: 018040f4 movhi r6,259 + 1000ae0: 31a52a04 addi r6,r6,-27480 + 1000ae4: 01c00044 movi r7,1 + 1000ae8: 101bcb40 call 101bcb4 + + if (status == OK) { + 1000aec: e0bfff17 ldw r2,-4(fp) + 1000af0: 1004c03a cmpne r2,r2,zero + 1000af4: 1000011e bne r2,zero,1000afc + OSStart(); + 1000af8: 1015ee00 call 1015ee0 + } + + return 0; + 1000afc: 0005883a mov r2,zero +} + 1000b00: e037883a mov sp,fp + 1000b04: dfc00117 ldw ra,4(sp) + 1000b08: df000017 ldw fp,0(sp) + 1000b0c: dec00204 addi sp,sp,8 + 1000b10: f800283a ret + +01000b14 <_Z7mc_taskPv>: + +// ==== mc + +#define mc_GUARD_TIME 1 + +void mc_task(void *pdata) + 1000b14: deff4a04 addi sp,sp,-728 + 1000b18: dfc0b515 stw ra,724(sp) + 1000b1c: df00b415 stw fp,720(sp) + 1000b20: ddc0b315 stw r23,716(sp) + 1000b24: dd80b215 stw r22,712(sp) + 1000b28: dd40b115 stw r21,708(sp) + 1000b2c: dd00b015 stw r20,704(sp) + 1000b30: dcc0af15 stw r19,700(sp) + 1000b34: dc80ae15 stw r18,696(sp) + 1000b38: dc40ad15 stw r17,692(sp) + 1000b3c: dc00ac15 stw r16,688(sp) + 1000b40: df00ac04 addi fp,sp,688 + 1000b44: e13f9c15 stw r4,-400(fp) + 1000b48: 00804034 movhi r2,256 + 1000b4c: 109a9704 addi r2,r2,27228 + 1000b50: e0bfa315 stw r2,-372(fp) + 1000b54: 008040b4 movhi r2,258 + 1000b58: 1082b684 addi r2,r2,2778 + 1000b5c: e0bfa415 stw r2,-368(fp) + 1000b60: e0bfa504 addi r2,fp,-364 + 1000b64: e0ff5404 addi r3,fp,-688 + 1000b68: 10c00015 stw r3,0(r2) + 1000b6c: 00c04034 movhi r3,256 + 1000b70: 18c7ca04 addi r3,r3,7976 + 1000b74: 10c00115 stw r3,4(r2) + 1000b78: 16c00215 stw sp,8(r2) + 1000b7c: e13f9d04 addi r4,fp,-396 + 1000b80: 1009c1c0 call 1009c1c <_Unwind_SjLj_Register> +{ + printf("mc task\n"); + 1000b84: 00bfffc4 movi r2,-1 + 1000b88: e0bf9e15 stw r2,-392(fp) + 1000b8c: 010040b4 movhi r4,258 + 1000b90: 2103c904 addi r4,r4,3876 + 1000b94: 100ad900 call 100ad90 + printf("MotorHandler [init"); + 1000b98: 010040b4 movhi r4,258 + 1000b9c: 2103cb04 addi r4,r4,3884 + 1000ba0: 100ac540 call 100ac54 + if (motor->init() == OK) { + 1000ba4: d1274517 ldw r4,-25324(gp) + 1000ba8: 10007a40 call 10007a4 <_ZN12MotorHandler4initEv> + 1000bac: 1005003a cmpeq r2,r2,zero + 1000bb0: 10803fcc andi r2,r2,255 + 1000bb4: 1005003a cmpeq r2,r2,zero + 1000bb8: 1000041e bne r2,zero,1000bcc <_Z7mc_taskPv+0xb8> + printf("]\n\n"); + 1000bbc: 010040b4 movhi r4,258 + 1000bc0: 2103d004 addi r4,r4,3904 + 1000bc4: 100ad900 call 100ad90 + 1000bc8: 00000506 br 1000be0 <_Z7mc_taskPv+0xcc> + } else { + printf( ", error]\n"); + 1000bcc: 00bfffc4 movi r2,-1 + 1000bd0: e0bf9e15 stw r2,-392(fp) + 1000bd4: 010040b4 movhi r4,258 + 1000bd8: 2103d104 addi r4,r4,3908 + 1000bdc: 100ad900 call 100ad90 + } + while(1){ + motor->motorCommand("left", "forward", "120"); + 1000be0: d0a74517 ldw r2,-25324(gp) + 1000be4: e0bffd15 stw r2,-12(fp) + 1000be8: e13f9a04 addi r4,fp,-408 + 1000bec: 10022880 call 1002288 <_ZNSaIcEC1Ev> + 1000bf0: e13f9b04 addi r4,fp,-404 + 1000bf4: e1bf9a04 addi r6,fp,-408 + 1000bf8: 00800c04 movi r2,48 + 1000bfc: e0bf9e15 stw r2,-392(fp) + 1000c00: 014040b4 movhi r5,258 + 1000c04: 2943d404 addi r5,r5,3920 + 1000c08: 1003e680 call 1003e68 <_ZNSsC1EPKcRKSaIcE> + 1000c0c: e13f9804 addi r4,fp,-416 + 1000c10: 10022880 call 1002288 <_ZNSaIcEC1Ev> + 1000c14: e13f9904 addi r4,fp,-412 + 1000c18: e1bf9804 addi r6,fp,-416 + 1000c1c: 00800bc4 movi r2,47 + 1000c20: e0bf9e15 stw r2,-392(fp) + 1000c24: 014040b4 movhi r5,258 + 1000c28: 2943d604 addi r5,r5,3928 + 1000c2c: 1003e680 call 1003e68 <_ZNSsC1EPKcRKSaIcE> + 1000c30: e13f9604 addi r4,fp,-424 + 1000c34: 10022880 call 1002288 <_ZNSaIcEC1Ev> + 1000c38: e13f9704 addi r4,fp,-420 + 1000c3c: e1bf9604 addi r6,fp,-424 + 1000c40: 00800b84 movi r2,46 + 1000c44: e0bf9e15 stw r2,-392(fp) + 1000c48: 014040b4 movhi r5,258 + 1000c4c: 2943d804 addi r5,r5,3936 + 1000c50: 1003e680 call 1003e68 <_ZNSsC1EPKcRKSaIcE> + 1000c54: e17f9b04 addi r5,fp,-404 + 1000c58: e1bf9904 addi r6,fp,-412 + 1000c5c: e1ff9704 addi r7,fp,-420 + 1000c60: 00800b44 movi r2,45 + 1000c64: e0bf9e15 stw r2,-392(fp) + 1000c68: e13ffd17 ldw r4,-12(fp) + 1000c6c: 10005980 call 1000598 <_ZN12MotorHandler12motorCommandESsSsSs> + 1000c70: e13f9704 addi r4,fp,-420 + 1000c74: 00800b84 movi r2,46 + 1000c78: e0bf9e15 stw r2,-392(fp) + 1000c7c: 1004a240 call 1004a24 <_ZNSsD1Ev> + 1000c80: 00000806 br 1000ca4 <_Z7mc_taskPv+0x190> + 1000c84: e0fffe17 ldw r3,-8(fp) + 1000c88: e0fff115 stw r3,-60(fp) + 1000c8c: e13f9704 addi r4,fp,-420 + 1000c90: e03f9e15 stw zero,-392(fp) + 1000c94: 1004a240 call 1004a24 <_ZNSsD1Ev> + 1000c98: e0bff117 ldw r2,-60(fp) + 1000c9c: e0bffe15 stw r2,-8(fp) + 1000ca0: 00000706 br 1000cc0 <_Z7mc_taskPv+0x1ac> + 1000ca4: e13f9604 addi r4,fp,-424 + 1000ca8: 10022b40 call 10022b4 <_ZNSaIcED1Ev> + 1000cac: e13f9904 addi r4,fp,-412 + 1000cb0: 00800bc4 movi r2,47 + 1000cb4: e0bf9e15 stw r2,-392(fp) + 1000cb8: 1004a240 call 1004a24 <_ZNSsD1Ev> + 1000cbc: 00000e06 br 1000cf8 <_Z7mc_taskPv+0x1e4> + 1000cc0: e0fffe17 ldw r3,-8(fp) + 1000cc4: e0fff015 stw r3,-64(fp) + 1000cc8: e13f9604 addi r4,fp,-424 + 1000ccc: 10022b40 call 10022b4 <_ZNSaIcED1Ev> + 1000cd0: e0bff017 ldw r2,-64(fp) + 1000cd4: e0bffe15 stw r2,-8(fp) + 1000cd8: e0fffe17 ldw r3,-8(fp) + 1000cdc: e0ffef15 stw r3,-68(fp) + 1000ce0: e13f9904 addi r4,fp,-412 + 1000ce4: e03f9e15 stw zero,-392(fp) + 1000ce8: 1004a240 call 1004a24 <_ZNSsD1Ev> + 1000cec: e0bfef17 ldw r2,-68(fp) + 1000cf0: e0bffe15 stw r2,-8(fp) + 1000cf4: 00000706 br 1000d14 <_Z7mc_taskPv+0x200> + 1000cf8: e13f9804 addi r4,fp,-416 + 1000cfc: 10022b40 call 10022b4 <_ZNSaIcED1Ev> + 1000d00: e13f9b04 addi r4,fp,-404 + 1000d04: 00800c04 movi r2,48 + 1000d08: e0bf9e15 stw r2,-392(fp) + 1000d0c: 1004a240 call 1004a24 <_ZNSsD1Ev> + 1000d10: 00000e06 br 1000d4c <_Z7mc_taskPv+0x238> + 1000d14: e0fffe17 ldw r3,-8(fp) + 1000d18: e0ffee15 stw r3,-72(fp) + 1000d1c: e13f9804 addi r4,fp,-416 + 1000d20: 10022b40 call 10022b4 <_ZNSaIcED1Ev> + 1000d24: e0bfee17 ldw r2,-72(fp) + 1000d28: e0bffe15 stw r2,-8(fp) + 1000d2c: e0fffe17 ldw r3,-8(fp) + 1000d30: e0ffed15 stw r3,-76(fp) + 1000d34: e13f9b04 addi r4,fp,-404 + 1000d38: e03f9e15 stw zero,-392(fp) + 1000d3c: 1004a240 call 1004a24 <_ZNSsD1Ev> + 1000d40: e0bfed17 ldw r2,-76(fp) + 1000d44: e0bffe15 stw r2,-8(fp) + 1000d48: 00000e06 br 1000d84 <_Z7mc_taskPv+0x270> + 1000d4c: e13f9a04 addi r4,fp,-408 + 1000d50: 10022b40 call 10022b4 <_ZNSaIcED1Ev> + motor->motorCommand("right","forward", "120"); + 1000d54: d0e74517 ldw r3,-25324(gp) + 1000d58: e0fffc15 stw r3,-16(fp) + 1000d5c: e13f9404 addi r4,fp,-432 + 1000d60: 10022880 call 1002288 <_ZNSaIcEC1Ev> + 1000d64: e13f9504 addi r4,fp,-428 + 1000d68: e1bf9404 addi r6,fp,-432 + 1000d6c: 00800b04 movi r2,44 + 1000d70: e0bf9e15 stw r2,-392(fp) + 1000d74: 014040b4 movhi r5,258 + 1000d78: 2943d904 addi r5,r5,3940 + 1000d7c: 1003e680 call 1003e68 <_ZNSsC1EPKcRKSaIcE> + 1000d80: 00000a06 br 1000dac <_Z7mc_taskPv+0x298> + 1000d84: e0bffe17 ldw r2,-8(fp) + 1000d88: e0bfec15 stw r2,-80(fp) + printf("]\n\n"); + } else { + printf( ", error]\n"); + } + while(1){ + motor->motorCommand("left", "forward", "120"); + 1000d8c: e13f9a04 addi r4,fp,-408 + 1000d90: 10022b40 call 10022b4 <_ZNSaIcED1Ev> + 1000d94: e0ffec17 ldw r3,-80(fp) + 1000d98: e0fffe15 stw r3,-8(fp) + 1000d9c: 00bfffc4 movi r2,-1 + 1000da0: e0bf9e15 stw r2,-392(fp) + 1000da4: e13ffe17 ldw r4,-8(fp) + 1000da8: 1009ee80 call 1009ee8 <_Unwind_SjLj_Resume> + motor->motorCommand("right","forward", "120"); + 1000dac: e13f9204 addi r4,fp,-440 + 1000db0: 10022880 call 1002288 <_ZNSaIcEC1Ev> + 1000db4: e13f9304 addi r4,fp,-436 + 1000db8: e1bf9204 addi r6,fp,-440 + 1000dbc: 00800ac4 movi r2,43 + 1000dc0: e0bf9e15 stw r2,-392(fp) + 1000dc4: 014040b4 movhi r5,258 + 1000dc8: 2943d604 addi r5,r5,3928 + 1000dcc: 1003e680 call 1003e68 <_ZNSsC1EPKcRKSaIcE> + 1000dd0: e13f9004 addi r4,fp,-448 + 1000dd4: 10022880 call 1002288 <_ZNSaIcEC1Ev> + 1000dd8: e13f9104 addi r4,fp,-444 + 1000ddc: e1bf9004 addi r6,fp,-448 + 1000de0: 00800a84 movi r2,42 + 1000de4: e0bf9e15 stw r2,-392(fp) + 1000de8: 014040b4 movhi r5,258 + 1000dec: 2943d804 addi r5,r5,3936 + 1000df0: 1003e680 call 1003e68 <_ZNSsC1EPKcRKSaIcE> + 1000df4: e17f9504 addi r5,fp,-428 + 1000df8: e1bf9304 addi r6,fp,-436 + 1000dfc: e1ff9104 addi r7,fp,-444 + 1000e00: 00800a44 movi r2,41 + 1000e04: e0bf9e15 stw r2,-392(fp) + 1000e08: e13ffc17 ldw r4,-16(fp) + 1000e0c: 10005980 call 1000598 <_ZN12MotorHandler12motorCommandESsSsSs> + 1000e10: e13f9104 addi r4,fp,-444 + 1000e14: 00800a84 movi r2,42 + 1000e18: e0bf9e15 stw r2,-392(fp) + 1000e1c: 1004a240 call 1004a24 <_ZNSsD1Ev> + 1000e20: 00000806 br 1000e44 <_Z7mc_taskPv+0x330> + 1000e24: e0bffe17 ldw r2,-8(fp) + 1000e28: e0bfeb15 stw r2,-84(fp) + 1000e2c: e13f9104 addi r4,fp,-444 + 1000e30: e03f9e15 stw zero,-392(fp) + 1000e34: 1004a240 call 1004a24 <_ZNSsD1Ev> + 1000e38: e0ffeb17 ldw r3,-84(fp) + 1000e3c: e0fffe15 stw r3,-8(fp) + 1000e40: 00000706 br 1000e60 <_Z7mc_taskPv+0x34c> + 1000e44: e13f9004 addi r4,fp,-448 + 1000e48: 10022b40 call 10022b4 <_ZNSaIcED1Ev> + 1000e4c: e13f9304 addi r4,fp,-436 + 1000e50: 00800ac4 movi r2,43 + 1000e54: e0bf9e15 stw r2,-392(fp) + 1000e58: 1004a240 call 1004a24 <_ZNSsD1Ev> + 1000e5c: 00000e06 br 1000e98 <_Z7mc_taskPv+0x384> + 1000e60: e0bffe17 ldw r2,-8(fp) + 1000e64: e0bfea15 stw r2,-88(fp) + 1000e68: e13f9004 addi r4,fp,-448 + 1000e6c: 10022b40 call 10022b4 <_ZNSaIcED1Ev> + 1000e70: e0ffea17 ldw r3,-88(fp) + 1000e74: e0fffe15 stw r3,-8(fp) + 1000e78: e0bffe17 ldw r2,-8(fp) + 1000e7c: e0bfe915 stw r2,-92(fp) + 1000e80: e13f9304 addi r4,fp,-436 + 1000e84: e03f9e15 stw zero,-392(fp) + 1000e88: 1004a240 call 1004a24 <_ZNSsD1Ev> + 1000e8c: e0ffe917 ldw r3,-92(fp) + 1000e90: e0fffe15 stw r3,-8(fp) + 1000e94: 00000706 br 1000eb4 <_Z7mc_taskPv+0x3a0> + 1000e98: e13f9204 addi r4,fp,-440 + 1000e9c: 10022b40 call 10022b4 <_ZNSaIcED1Ev> + 1000ea0: e13f9504 addi r4,fp,-428 + 1000ea4: 00800b04 movi r2,44 + 1000ea8: e0bf9e15 stw r2,-392(fp) + 1000eac: 1004a240 call 1004a24 <_ZNSsD1Ev> + 1000eb0: 00000e06 br 1000eec <_Z7mc_taskPv+0x3d8> + 1000eb4: e0bffe17 ldw r2,-8(fp) + 1000eb8: e0bfe815 stw r2,-96(fp) + 1000ebc: e13f9204 addi r4,fp,-440 + 1000ec0: 10022b40 call 10022b4 <_ZNSaIcED1Ev> + 1000ec4: e0ffe817 ldw r3,-96(fp) + 1000ec8: e0fffe15 stw r3,-8(fp) + 1000ecc: e0bffe17 ldw r2,-8(fp) + 1000ed0: e0bfe715 stw r2,-100(fp) + 1000ed4: e13f9504 addi r4,fp,-428 + 1000ed8: e03f9e15 stw zero,-392(fp) + 1000edc: 1004a240 call 1004a24 <_ZNSsD1Ev> + 1000ee0: e0ffe717 ldw r3,-100(fp) + 1000ee4: e0fffe15 stw r3,-8(fp) + 1000ee8: 00001506 br 1000f40 <_Z7mc_taskPv+0x42c> + 1000eec: e13f9404 addi r4,fp,-432 + 1000ef0: 10022b40 call 10022b4 <_ZNSaIcED1Ev> + OSTimeDlyHMSM(0, 0, 5, 0); + 1000ef4: 00bfffc4 movi r2,-1 + 1000ef8: e0bf9e15 stw r2,-392(fp) + 1000efc: 0009883a mov r4,zero + 1000f00: 000b883a mov r5,zero + 1000f04: 01800144 movi r6,5 + 1000f08: 000f883a mov r7,zero + 1000f0c: 101d0f80 call 101d0f8 + motor->motorCommand("left", "forward", "0"); + 1000f10: d0a74517 ldw r2,-25324(gp) + 1000f14: e0bffb15 stw r2,-20(fp) + 1000f18: e13f8e04 addi r4,fp,-456 + 1000f1c: 10022880 call 1002288 <_ZNSaIcEC1Ev> + 1000f20: e13f8f04 addi r4,fp,-452 + 1000f24: e1bf8e04 addi r6,fp,-456 + 1000f28: 00800a04 movi r2,40 + 1000f2c: e0bf9e15 stw r2,-392(fp) + 1000f30: 014040b4 movhi r5,258 + 1000f34: 2943d404 addi r5,r5,3920 + 1000f38: 1003e680 call 1003e68 <_ZNSsC1EPKcRKSaIcE> + 1000f3c: 00000a06 br 1000f68 <_Z7mc_taskPv+0x454> + 1000f40: e0fffe17 ldw r3,-8(fp) + 1000f44: e0ffe615 stw r3,-104(fp) + } else { + printf( ", error]\n"); + } + while(1){ + motor->motorCommand("left", "forward", "120"); + motor->motorCommand("right","forward", "120"); + 1000f48: e13f9404 addi r4,fp,-432 + 1000f4c: 10022b40 call 10022b4 <_ZNSaIcED1Ev> + 1000f50: e0bfe617 ldw r2,-104(fp) + 1000f54: e0bffe15 stw r2,-8(fp) + 1000f58: 00bfffc4 movi r2,-1 + 1000f5c: e0bf9e15 stw r2,-392(fp) + 1000f60: e13ffe17 ldw r4,-8(fp) + 1000f64: 1009ee80 call 1009ee8 <_Unwind_SjLj_Resume> + OSTimeDlyHMSM(0, 0, 5, 0); + motor->motorCommand("left", "forward", "0"); + 1000f68: e13f8c04 addi r4,fp,-464 + 1000f6c: 10022880 call 1002288 <_ZNSaIcEC1Ev> + 1000f70: e13f8d04 addi r4,fp,-460 + 1000f74: e1bf8c04 addi r6,fp,-464 + 1000f78: 008009c4 movi r2,39 + 1000f7c: e0bf9e15 stw r2,-392(fp) + 1000f80: 014040b4 movhi r5,258 + 1000f84: 2943d604 addi r5,r5,3928 + 1000f88: 1003e680 call 1003e68 <_ZNSsC1EPKcRKSaIcE> + 1000f8c: e13f8a04 addi r4,fp,-472 + 1000f90: 10022880 call 1002288 <_ZNSaIcEC1Ev> + 1000f94: e13f8b04 addi r4,fp,-468 + 1000f98: e1bf8a04 addi r6,fp,-472 + 1000f9c: 00800984 movi r2,38 + 1000fa0: e0bf9e15 stw r2,-392(fp) + 1000fa4: 014040b4 movhi r5,258 + 1000fa8: 2943db04 addi r5,r5,3948 + 1000fac: 1003e680 call 1003e68 <_ZNSsC1EPKcRKSaIcE> + 1000fb0: e17f8f04 addi r5,fp,-452 + 1000fb4: e1bf8d04 addi r6,fp,-460 + 1000fb8: e1ff8b04 addi r7,fp,-468 + 1000fbc: 00800944 movi r2,37 + 1000fc0: e0bf9e15 stw r2,-392(fp) + 1000fc4: e13ffb17 ldw r4,-20(fp) + 1000fc8: 10005980 call 1000598 <_ZN12MotorHandler12motorCommandESsSsSs> + 1000fcc: e13f8b04 addi r4,fp,-468 + 1000fd0: 00800984 movi r2,38 + 1000fd4: e0bf9e15 stw r2,-392(fp) + 1000fd8: 1004a240 call 1004a24 <_ZNSsD1Ev> + 1000fdc: 00000806 br 1001000 <_Z7mc_taskPv+0x4ec> + 1000fe0: e0fffe17 ldw r3,-8(fp) + 1000fe4: e0ffe515 stw r3,-108(fp) + 1000fe8: e13f8b04 addi r4,fp,-468 + 1000fec: e03f9e15 stw zero,-392(fp) + 1000ff0: 1004a240 call 1004a24 <_ZNSsD1Ev> + 1000ff4: e0bfe517 ldw r2,-108(fp) + 1000ff8: e0bffe15 stw r2,-8(fp) + 1000ffc: 00000706 br 100101c <_Z7mc_taskPv+0x508> + 1001000: e13f8a04 addi r4,fp,-472 + 1001004: 10022b40 call 10022b4 <_ZNSaIcED1Ev> + 1001008: e13f8d04 addi r4,fp,-460 + 100100c: 008009c4 movi r2,39 + 1001010: e0bf9e15 stw r2,-392(fp) + 1001014: 1004a240 call 1004a24 <_ZNSsD1Ev> + 1001018: 00000e06 br 1001054 <_Z7mc_taskPv+0x540> + 100101c: e0fffe17 ldw r3,-8(fp) + 1001020: e0ffe415 stw r3,-112(fp) + 1001024: e13f8a04 addi r4,fp,-472 + 1001028: 10022b40 call 10022b4 <_ZNSaIcED1Ev> + 100102c: e0bfe417 ldw r2,-112(fp) + 1001030: e0bffe15 stw r2,-8(fp) + 1001034: e0fffe17 ldw r3,-8(fp) + 1001038: e0ffe315 stw r3,-116(fp) + 100103c: e13f8d04 addi r4,fp,-460 + 1001040: e03f9e15 stw zero,-392(fp) + 1001044: 1004a240 call 1004a24 <_ZNSsD1Ev> + 1001048: e0bfe317 ldw r2,-116(fp) + 100104c: e0bffe15 stw r2,-8(fp) + 1001050: 00000706 br 1001070 <_Z7mc_taskPv+0x55c> + 1001054: e13f8c04 addi r4,fp,-464 + 1001058: 10022b40 call 10022b4 <_ZNSaIcED1Ev> + 100105c: e13f8f04 addi r4,fp,-452 + 1001060: 00800a04 movi r2,40 + 1001064: e0bf9e15 stw r2,-392(fp) + 1001068: 1004a240 call 1004a24 <_ZNSsD1Ev> + 100106c: 00000e06 br 10010a8 <_Z7mc_taskPv+0x594> + 1001070: e0fffe17 ldw r3,-8(fp) + 1001074: e0ffe215 stw r3,-120(fp) + 1001078: e13f8c04 addi r4,fp,-464 + 100107c: 10022b40 call 10022b4 <_ZNSaIcED1Ev> + 1001080: e0bfe217 ldw r2,-120(fp) + 1001084: e0bffe15 stw r2,-8(fp) + 1001088: e0fffe17 ldw r3,-8(fp) + 100108c: e0ffe115 stw r3,-124(fp) + 1001090: e13f8f04 addi r4,fp,-452 + 1001094: e03f9e15 stw zero,-392(fp) + 1001098: 1004a240 call 1004a24 <_ZNSsD1Ev> + 100109c: e0bfe117 ldw r2,-124(fp) + 10010a0: e0bffe15 stw r2,-8(fp) + 10010a4: 00000e06 br 10010e0 <_Z7mc_taskPv+0x5cc> + 10010a8: e13f8e04 addi r4,fp,-456 + 10010ac: 10022b40 call 10022b4 <_ZNSaIcED1Ev> + motor->motorCommand("right","forward", "0"); + 10010b0: d0e74517 ldw r3,-25324(gp) + 10010b4: e0fffa15 stw r3,-24(fp) + 10010b8: e13f8804 addi r4,fp,-480 + 10010bc: 10022880 call 1002288 <_ZNSaIcEC1Ev> + 10010c0: e13f8904 addi r4,fp,-476 + 10010c4: e1bf8804 addi r6,fp,-480 + 10010c8: 00800904 movi r2,36 + 10010cc: e0bf9e15 stw r2,-392(fp) + 10010d0: 014040b4 movhi r5,258 + 10010d4: 2943d904 addi r5,r5,3940 + 10010d8: 1003e680 call 1003e68 <_ZNSsC1EPKcRKSaIcE> + 10010dc: 00000a06 br 1001108 <_Z7mc_taskPv+0x5f4> + 10010e0: e0bffe17 ldw r2,-8(fp) + 10010e4: e0bfe015 stw r2,-128(fp) + } + while(1){ + motor->motorCommand("left", "forward", "120"); + motor->motorCommand("right","forward", "120"); + OSTimeDlyHMSM(0, 0, 5, 0); + motor->motorCommand("left", "forward", "0"); + 10010e8: e13f8e04 addi r4,fp,-456 + 10010ec: 10022b40 call 10022b4 <_ZNSaIcED1Ev> + 10010f0: e0ffe017 ldw r3,-128(fp) + 10010f4: e0fffe15 stw r3,-8(fp) + 10010f8: 00bfffc4 movi r2,-1 + 10010fc: e0bf9e15 stw r2,-392(fp) + 1001100: e13ffe17 ldw r4,-8(fp) + 1001104: 1009ee80 call 1009ee8 <_Unwind_SjLj_Resume> + motor->motorCommand("right","forward", "0"); + 1001108: e13f8604 addi r4,fp,-488 + 100110c: 10022880 call 1002288 <_ZNSaIcEC1Ev> + 1001110: e13f8704 addi r4,fp,-484 + 1001114: e1bf8604 addi r6,fp,-488 + 1001118: 008008c4 movi r2,35 + 100111c: e0bf9e15 stw r2,-392(fp) + 1001120: 014040b4 movhi r5,258 + 1001124: 2943d604 addi r5,r5,3928 + 1001128: 1003e680 call 1003e68 <_ZNSsC1EPKcRKSaIcE> + 100112c: e13f8404 addi r4,fp,-496 + 1001130: 10022880 call 1002288 <_ZNSaIcEC1Ev> + 1001134: e13f8504 addi r4,fp,-492 + 1001138: e1bf8404 addi r6,fp,-496 + 100113c: 00800884 movi r2,34 + 1001140: e0bf9e15 stw r2,-392(fp) + 1001144: 014040b4 movhi r5,258 + 1001148: 2943db04 addi r5,r5,3948 + 100114c: 1003e680 call 1003e68 <_ZNSsC1EPKcRKSaIcE> + 1001150: e17f8904 addi r5,fp,-476 + 1001154: e1bf8704 addi r6,fp,-484 + 1001158: e1ff8504 addi r7,fp,-492 + 100115c: 00800844 movi r2,33 + 1001160: e0bf9e15 stw r2,-392(fp) + 1001164: e13ffa17 ldw r4,-24(fp) + 1001168: 10005980 call 1000598 <_ZN12MotorHandler12motorCommandESsSsSs> + 100116c: e13f8504 addi r4,fp,-492 + 1001170: 00800884 movi r2,34 + 1001174: e0bf9e15 stw r2,-392(fp) + 1001178: 1004a240 call 1004a24 <_ZNSsD1Ev> + 100117c: 00000806 br 10011a0 <_Z7mc_taskPv+0x68c> + 1001180: e0bffe17 ldw r2,-8(fp) + 1001184: e0bfdf15 stw r2,-132(fp) + 1001188: e13f8504 addi r4,fp,-492 + 100118c: e03f9e15 stw zero,-392(fp) + 1001190: 1004a240 call 1004a24 <_ZNSsD1Ev> + 1001194: e0ffdf17 ldw r3,-132(fp) + 1001198: e0fffe15 stw r3,-8(fp) + 100119c: 00000706 br 10011bc <_Z7mc_taskPv+0x6a8> + 10011a0: e13f8404 addi r4,fp,-496 + 10011a4: 10022b40 call 10022b4 <_ZNSaIcED1Ev> + 10011a8: e13f8704 addi r4,fp,-484 + 10011ac: 008008c4 movi r2,35 + 10011b0: e0bf9e15 stw r2,-392(fp) + 10011b4: 1004a240 call 1004a24 <_ZNSsD1Ev> + 10011b8: 00000e06 br 10011f4 <_Z7mc_taskPv+0x6e0> + 10011bc: e0bffe17 ldw r2,-8(fp) + 10011c0: e0bfde15 stw r2,-136(fp) + 10011c4: e13f8404 addi r4,fp,-496 + 10011c8: 10022b40 call 10022b4 <_ZNSaIcED1Ev> + 10011cc: e0ffde17 ldw r3,-136(fp) + 10011d0: e0fffe15 stw r3,-8(fp) + 10011d4: e0bffe17 ldw r2,-8(fp) + 10011d8: e0bfdd15 stw r2,-140(fp) + 10011dc: e13f8704 addi r4,fp,-484 + 10011e0: e03f9e15 stw zero,-392(fp) + 10011e4: 1004a240 call 1004a24 <_ZNSsD1Ev> + 10011e8: e0ffdd17 ldw r3,-140(fp) + 10011ec: e0fffe15 stw r3,-8(fp) + 10011f0: 00000706 br 1001210 <_Z7mc_taskPv+0x6fc> + 10011f4: e13f8604 addi r4,fp,-488 + 10011f8: 10022b40 call 10022b4 <_ZNSaIcED1Ev> + 10011fc: e13f8904 addi r4,fp,-476 + 1001200: 00800904 movi r2,36 + 1001204: e0bf9e15 stw r2,-392(fp) + 1001208: 1004a240 call 1004a24 <_ZNSsD1Ev> + 100120c: 00000e06 br 1001248 <_Z7mc_taskPv+0x734> + 1001210: e0bffe17 ldw r2,-8(fp) + 1001214: e0bfdc15 stw r2,-144(fp) + 1001218: e13f8604 addi r4,fp,-488 + 100121c: 10022b40 call 10022b4 <_ZNSaIcED1Ev> + 1001220: e0ffdc17 ldw r3,-144(fp) + 1001224: e0fffe15 stw r3,-8(fp) + 1001228: e0bffe17 ldw r2,-8(fp) + 100122c: e0bfdb15 stw r2,-148(fp) + 1001230: e13f8904 addi r4,fp,-476 + 1001234: e03f9e15 stw zero,-392(fp) + 1001238: 1004a240 call 1004a24 <_ZNSsD1Ev> + 100123c: e0ffdb17 ldw r3,-148(fp) + 1001240: e0fffe15 stw r3,-8(fp) + 1001244: 00001506 br 100129c <_Z7mc_taskPv+0x788> + 1001248: e13f8804 addi r4,fp,-480 + 100124c: 10022b40 call 10022b4 <_ZNSaIcED1Ev> + OSTimeDlyHMSM(0, 0, 5, 0); + 1001250: 00bfffc4 movi r2,-1 + 1001254: e0bf9e15 stw r2,-392(fp) + 1001258: 0009883a mov r4,zero + 100125c: 000b883a mov r5,zero + 1001260: 01800144 movi r6,5 + 1001264: 000f883a mov r7,zero + 1001268: 101d0f80 call 101d0f8 + motor->motorCommand("left", "backward", "120"); + 100126c: d0a74517 ldw r2,-25324(gp) + 1001270: e0bff915 stw r2,-28(fp) + 1001274: e13f8204 addi r4,fp,-504 + 1001278: 10022880 call 1002288 <_ZNSaIcEC1Ev> + 100127c: e13f8304 addi r4,fp,-500 + 1001280: e1bf8204 addi r6,fp,-504 + 1001284: 00800804 movi r2,32 + 1001288: e0bf9e15 stw r2,-392(fp) + 100128c: 014040b4 movhi r5,258 + 1001290: 2943d404 addi r5,r5,3920 + 1001294: 1003e680 call 1003e68 <_ZNSsC1EPKcRKSaIcE> + 1001298: 00000a06 br 10012c4 <_Z7mc_taskPv+0x7b0> + 100129c: e0fffe17 ldw r3,-8(fp) + 10012a0: e0ffda15 stw r3,-152(fp) + while(1){ + motor->motorCommand("left", "forward", "120"); + motor->motorCommand("right","forward", "120"); + OSTimeDlyHMSM(0, 0, 5, 0); + motor->motorCommand("left", "forward", "0"); + motor->motorCommand("right","forward", "0"); + 10012a4: e13f8804 addi r4,fp,-480 + 10012a8: 10022b40 call 10022b4 <_ZNSaIcED1Ev> + 10012ac: e0bfda17 ldw r2,-152(fp) + 10012b0: e0bffe15 stw r2,-8(fp) + 10012b4: 00bfffc4 movi r2,-1 + 10012b8: e0bf9e15 stw r2,-392(fp) + 10012bc: e13ffe17 ldw r4,-8(fp) + 10012c0: 1009ee80 call 1009ee8 <_Unwind_SjLj_Resume> + OSTimeDlyHMSM(0, 0, 5, 0); + motor->motorCommand("left", "backward", "120"); + 10012c4: e13f8004 addi r4,fp,-512 + 10012c8: 10022880 call 1002288 <_ZNSaIcEC1Ev> + 10012cc: e13f8104 addi r4,fp,-508 + 10012d0: e1bf8004 addi r6,fp,-512 + 10012d4: 008007c4 movi r2,31 + 10012d8: e0bf9e15 stw r2,-392(fp) + 10012dc: 014040b4 movhi r5,258 + 10012e0: 2943dc04 addi r5,r5,3952 + 10012e4: 1003e680 call 1003e68 <_ZNSsC1EPKcRKSaIcE> + 10012e8: e13f7e04 addi r4,fp,-520 + 10012ec: 10022880 call 1002288 <_ZNSaIcEC1Ev> + 10012f0: e13f7f04 addi r4,fp,-516 + 10012f4: e1bf7e04 addi r6,fp,-520 + 10012f8: 00800784 movi r2,30 + 10012fc: e0bf9e15 stw r2,-392(fp) + 1001300: 014040b4 movhi r5,258 + 1001304: 2943d804 addi r5,r5,3936 + 1001308: 1003e680 call 1003e68 <_ZNSsC1EPKcRKSaIcE> + 100130c: e17f8304 addi r5,fp,-500 + 1001310: e1bf8104 addi r6,fp,-508 + 1001314: e1ff7f04 addi r7,fp,-516 + 1001318: 00800744 movi r2,29 + 100131c: e0bf9e15 stw r2,-392(fp) + 1001320: e13ff917 ldw r4,-28(fp) + 1001324: 10005980 call 1000598 <_ZN12MotorHandler12motorCommandESsSsSs> + 1001328: e13f7f04 addi r4,fp,-516 + 100132c: 00800784 movi r2,30 + 1001330: e0bf9e15 stw r2,-392(fp) + 1001334: 1004a240 call 1004a24 <_ZNSsD1Ev> + 1001338: 00000806 br 100135c <_Z7mc_taskPv+0x848> + 100133c: e0fffe17 ldw r3,-8(fp) + 1001340: e0ffd915 stw r3,-156(fp) + 1001344: e13f7f04 addi r4,fp,-516 + 1001348: e03f9e15 stw zero,-392(fp) + 100134c: 1004a240 call 1004a24 <_ZNSsD1Ev> + 1001350: e0bfd917 ldw r2,-156(fp) + 1001354: e0bffe15 stw r2,-8(fp) + 1001358: 00000706 br 1001378 <_Z7mc_taskPv+0x864> + 100135c: e13f7e04 addi r4,fp,-520 + 1001360: 10022b40 call 10022b4 <_ZNSaIcED1Ev> + 1001364: e13f8104 addi r4,fp,-508 + 1001368: 008007c4 movi r2,31 + 100136c: e0bf9e15 stw r2,-392(fp) + 1001370: 1004a240 call 1004a24 <_ZNSsD1Ev> + 1001374: 00000e06 br 10013b0 <_Z7mc_taskPv+0x89c> + 1001378: e0fffe17 ldw r3,-8(fp) + 100137c: e0ffd815 stw r3,-160(fp) + 1001380: e13f7e04 addi r4,fp,-520 + 1001384: 10022b40 call 10022b4 <_ZNSaIcED1Ev> + 1001388: e0bfd817 ldw r2,-160(fp) + 100138c: e0bffe15 stw r2,-8(fp) + 1001390: e0fffe17 ldw r3,-8(fp) + 1001394: e0ffd715 stw r3,-164(fp) + 1001398: e13f8104 addi r4,fp,-508 + 100139c: e03f9e15 stw zero,-392(fp) + 10013a0: 1004a240 call 1004a24 <_ZNSsD1Ev> + 10013a4: e0bfd717 ldw r2,-164(fp) + 10013a8: e0bffe15 stw r2,-8(fp) + 10013ac: 00000706 br 10013cc <_Z7mc_taskPv+0x8b8> + 10013b0: e13f8004 addi r4,fp,-512 + 10013b4: 10022b40 call 10022b4 <_ZNSaIcED1Ev> + 10013b8: e13f8304 addi r4,fp,-500 + 10013bc: 00800804 movi r2,32 + 10013c0: e0bf9e15 stw r2,-392(fp) + 10013c4: 1004a240 call 1004a24 <_ZNSsD1Ev> + 10013c8: 00000e06 br 1001404 <_Z7mc_taskPv+0x8f0> + 10013cc: e0fffe17 ldw r3,-8(fp) + 10013d0: e0ffd615 stw r3,-168(fp) + 10013d4: e13f8004 addi r4,fp,-512 + 10013d8: 10022b40 call 10022b4 <_ZNSaIcED1Ev> + 10013dc: e0bfd617 ldw r2,-168(fp) + 10013e0: e0bffe15 stw r2,-8(fp) + 10013e4: e0fffe17 ldw r3,-8(fp) + 10013e8: e0ffd515 stw r3,-172(fp) + 10013ec: e13f8304 addi r4,fp,-500 + 10013f0: e03f9e15 stw zero,-392(fp) + 10013f4: 1004a240 call 1004a24 <_ZNSsD1Ev> + 10013f8: e0bfd517 ldw r2,-172(fp) + 10013fc: e0bffe15 stw r2,-8(fp) + 1001400: 00000e06 br 100143c <_Z7mc_taskPv+0x928> + 1001404: e13f8204 addi r4,fp,-504 + 1001408: 10022b40 call 10022b4 <_ZNSaIcED1Ev> + motor->motorCommand("right","backward", "120"); + 100140c: d0e74517 ldw r3,-25324(gp) + 1001410: e0fff815 stw r3,-32(fp) + 1001414: e13f7c04 addi r4,fp,-528 + 1001418: 10022880 call 1002288 <_ZNSaIcEC1Ev> + 100141c: e13f7d04 addi r4,fp,-524 + 1001420: e1bf7c04 addi r6,fp,-528 + 1001424: 00800704 movi r2,28 + 1001428: e0bf9e15 stw r2,-392(fp) + 100142c: 014040b4 movhi r5,258 + 1001430: 2943d904 addi r5,r5,3940 + 1001434: 1003e680 call 1003e68 <_ZNSsC1EPKcRKSaIcE> + 1001438: 00000a06 br 1001464 <_Z7mc_taskPv+0x950> + 100143c: e0bffe17 ldw r2,-8(fp) + 1001440: e0bfd415 stw r2,-176(fp) + motor->motorCommand("right","forward", "120"); + OSTimeDlyHMSM(0, 0, 5, 0); + motor->motorCommand("left", "forward", "0"); + motor->motorCommand("right","forward", "0"); + OSTimeDlyHMSM(0, 0, 5, 0); + motor->motorCommand("left", "backward", "120"); + 1001444: e13f8204 addi r4,fp,-504 + 1001448: 10022b40 call 10022b4 <_ZNSaIcED1Ev> + 100144c: e0ffd417 ldw r3,-176(fp) + 1001450: e0fffe15 stw r3,-8(fp) + 1001454: 00bfffc4 movi r2,-1 + 1001458: e0bf9e15 stw r2,-392(fp) + 100145c: e13ffe17 ldw r4,-8(fp) + 1001460: 1009ee80 call 1009ee8 <_Unwind_SjLj_Resume> + motor->motorCommand("right","backward", "120"); + 1001464: e13f7a04 addi r4,fp,-536 + 1001468: 10022880 call 1002288 <_ZNSaIcEC1Ev> + 100146c: e13f7b04 addi r4,fp,-532 + 1001470: e1bf7a04 addi r6,fp,-536 + 1001474: 008006c4 movi r2,27 + 1001478: e0bf9e15 stw r2,-392(fp) + 100147c: 014040b4 movhi r5,258 + 1001480: 2943dc04 addi r5,r5,3952 + 1001484: 1003e680 call 1003e68 <_ZNSsC1EPKcRKSaIcE> + 1001488: e13f7804 addi r4,fp,-544 + 100148c: 10022880 call 1002288 <_ZNSaIcEC1Ev> + 1001490: e13f7904 addi r4,fp,-540 + 1001494: e1bf7804 addi r6,fp,-544 + 1001498: 00800684 movi r2,26 + 100149c: e0bf9e15 stw r2,-392(fp) + 10014a0: 014040b4 movhi r5,258 + 10014a4: 2943d804 addi r5,r5,3936 + 10014a8: 1003e680 call 1003e68 <_ZNSsC1EPKcRKSaIcE> + 10014ac: e17f7d04 addi r5,fp,-524 + 10014b0: e1bf7b04 addi r6,fp,-532 + 10014b4: e1ff7904 addi r7,fp,-540 + 10014b8: 00800644 movi r2,25 + 10014bc: e0bf9e15 stw r2,-392(fp) + 10014c0: e13ff817 ldw r4,-32(fp) + 10014c4: 10005980 call 1000598 <_ZN12MotorHandler12motorCommandESsSsSs> + 10014c8: e13f7904 addi r4,fp,-540 + 10014cc: 00800684 movi r2,26 + 10014d0: e0bf9e15 stw r2,-392(fp) + 10014d4: 1004a240 call 1004a24 <_ZNSsD1Ev> + 10014d8: 00000806 br 10014fc <_Z7mc_taskPv+0x9e8> + 10014dc: e0bffe17 ldw r2,-8(fp) + 10014e0: e0bfd315 stw r2,-180(fp) + 10014e4: e13f7904 addi r4,fp,-540 + 10014e8: e03f9e15 stw zero,-392(fp) + 10014ec: 1004a240 call 1004a24 <_ZNSsD1Ev> + 10014f0: e0ffd317 ldw r3,-180(fp) + 10014f4: e0fffe15 stw r3,-8(fp) + 10014f8: 00000706 br 1001518 <_Z7mc_taskPv+0xa04> + 10014fc: e13f7804 addi r4,fp,-544 + 1001500: 10022b40 call 10022b4 <_ZNSaIcED1Ev> + 1001504: e13f7b04 addi r4,fp,-532 + 1001508: 008006c4 movi r2,27 + 100150c: e0bf9e15 stw r2,-392(fp) + 1001510: 1004a240 call 1004a24 <_ZNSsD1Ev> + 1001514: 00000e06 br 1001550 <_Z7mc_taskPv+0xa3c> + 1001518: e0bffe17 ldw r2,-8(fp) + 100151c: e0bfd215 stw r2,-184(fp) + 1001520: e13f7804 addi r4,fp,-544 + 1001524: 10022b40 call 10022b4 <_ZNSaIcED1Ev> + 1001528: e0ffd217 ldw r3,-184(fp) + 100152c: e0fffe15 stw r3,-8(fp) + 1001530: e0bffe17 ldw r2,-8(fp) + 1001534: e0bfd115 stw r2,-188(fp) + 1001538: e13f7b04 addi r4,fp,-532 + 100153c: e03f9e15 stw zero,-392(fp) + 1001540: 1004a240 call 1004a24 <_ZNSsD1Ev> + 1001544: e0ffd117 ldw r3,-188(fp) + 1001548: e0fffe15 stw r3,-8(fp) + 100154c: 00000706 br 100156c <_Z7mc_taskPv+0xa58> + 1001550: e13f7a04 addi r4,fp,-536 + 1001554: 10022b40 call 10022b4 <_ZNSaIcED1Ev> + 1001558: e13f7d04 addi r4,fp,-524 + 100155c: 00800704 movi r2,28 + 1001560: e0bf9e15 stw r2,-392(fp) + 1001564: 1004a240 call 1004a24 <_ZNSsD1Ev> + 1001568: 00000e06 br 10015a4 <_Z7mc_taskPv+0xa90> + 100156c: e0bffe17 ldw r2,-8(fp) + 1001570: e0bfd015 stw r2,-192(fp) + 1001574: e13f7a04 addi r4,fp,-536 + 1001578: 10022b40 call 10022b4 <_ZNSaIcED1Ev> + 100157c: e0ffd017 ldw r3,-192(fp) + 1001580: e0fffe15 stw r3,-8(fp) + 1001584: e0bffe17 ldw r2,-8(fp) + 1001588: e0bfcf15 stw r2,-196(fp) + 100158c: e13f7d04 addi r4,fp,-524 + 1001590: e03f9e15 stw zero,-392(fp) + 1001594: 1004a240 call 1004a24 <_ZNSsD1Ev> + 1001598: e0ffcf17 ldw r3,-196(fp) + 100159c: e0fffe15 stw r3,-8(fp) + 10015a0: 00001506 br 10015f8 <_Z7mc_taskPv+0xae4> + 10015a4: e13f7c04 addi r4,fp,-528 + 10015a8: 10022b40 call 10022b4 <_ZNSaIcED1Ev> + OSTimeDlyHMSM(0, 0, 5, 0); + 10015ac: 00bfffc4 movi r2,-1 + 10015b0: e0bf9e15 stw r2,-392(fp) + 10015b4: 0009883a mov r4,zero + 10015b8: 000b883a mov r5,zero + 10015bc: 01800144 movi r6,5 + 10015c0: 000f883a mov r7,zero + 10015c4: 101d0f80 call 101d0f8 + motor->motorCommand("left", "forward", "0"); + 10015c8: d0a74517 ldw r2,-25324(gp) + 10015cc: e0bff715 stw r2,-36(fp) + 10015d0: e13f7604 addi r4,fp,-552 + 10015d4: 10022880 call 1002288 <_ZNSaIcEC1Ev> + 10015d8: e13f7704 addi r4,fp,-548 + 10015dc: e1bf7604 addi r6,fp,-552 + 10015e0: 00800604 movi r2,24 + 10015e4: e0bf9e15 stw r2,-392(fp) + 10015e8: 014040b4 movhi r5,258 + 10015ec: 2943d404 addi r5,r5,3920 + 10015f0: 1003e680 call 1003e68 <_ZNSsC1EPKcRKSaIcE> + 10015f4: 00000a06 br 1001620 <_Z7mc_taskPv+0xb0c> + 10015f8: e0fffe17 ldw r3,-8(fp) + 10015fc: e0ffce15 stw r3,-200(fp) + OSTimeDlyHMSM(0, 0, 5, 0); + motor->motorCommand("left", "forward", "0"); + motor->motorCommand("right","forward", "0"); + OSTimeDlyHMSM(0, 0, 5, 0); + motor->motorCommand("left", "backward", "120"); + motor->motorCommand("right","backward", "120"); + 1001600: e13f7c04 addi r4,fp,-528 + 1001604: 10022b40 call 10022b4 <_ZNSaIcED1Ev> + 1001608: e0bfce17 ldw r2,-200(fp) + 100160c: e0bffe15 stw r2,-8(fp) + 1001610: 00bfffc4 movi r2,-1 + 1001614: e0bf9e15 stw r2,-392(fp) + 1001618: e13ffe17 ldw r4,-8(fp) + 100161c: 1009ee80 call 1009ee8 <_Unwind_SjLj_Resume> + OSTimeDlyHMSM(0, 0, 5, 0); + motor->motorCommand("left", "forward", "0"); + 1001620: e13f7404 addi r4,fp,-560 + 1001624: 10022880 call 1002288 <_ZNSaIcEC1Ev> + 1001628: e13f7504 addi r4,fp,-556 + 100162c: e1bf7404 addi r6,fp,-560 + 1001630: 008005c4 movi r2,23 + 1001634: e0bf9e15 stw r2,-392(fp) + 1001638: 014040b4 movhi r5,258 + 100163c: 2943d604 addi r5,r5,3928 + 1001640: 1003e680 call 1003e68 <_ZNSsC1EPKcRKSaIcE> + 1001644: e13f7204 addi r4,fp,-568 + 1001648: 10022880 call 1002288 <_ZNSaIcEC1Ev> + 100164c: e13f7304 addi r4,fp,-564 + 1001650: e1bf7204 addi r6,fp,-568 + 1001654: 00800584 movi r2,22 + 1001658: e0bf9e15 stw r2,-392(fp) + 100165c: 014040b4 movhi r5,258 + 1001660: 2943db04 addi r5,r5,3948 + 1001664: 1003e680 call 1003e68 <_ZNSsC1EPKcRKSaIcE> + 1001668: e17f7704 addi r5,fp,-548 + 100166c: e1bf7504 addi r6,fp,-556 + 1001670: e1ff7304 addi r7,fp,-564 + 1001674: 00800544 movi r2,21 + 1001678: e0bf9e15 stw r2,-392(fp) + 100167c: e13ff717 ldw r4,-36(fp) + 1001680: 10005980 call 1000598 <_ZN12MotorHandler12motorCommandESsSsSs> + 1001684: e13f7304 addi r4,fp,-564 + 1001688: 00800584 movi r2,22 + 100168c: e0bf9e15 stw r2,-392(fp) + 1001690: 1004a240 call 1004a24 <_ZNSsD1Ev> + 1001694: 00000806 br 10016b8 <_Z7mc_taskPv+0xba4> + 1001698: e0fffe17 ldw r3,-8(fp) + 100169c: e0ffcd15 stw r3,-204(fp) + 10016a0: e13f7304 addi r4,fp,-564 + 10016a4: e03f9e15 stw zero,-392(fp) + 10016a8: 1004a240 call 1004a24 <_ZNSsD1Ev> + 10016ac: e0bfcd17 ldw r2,-204(fp) + 10016b0: e0bffe15 stw r2,-8(fp) + 10016b4: 00000706 br 10016d4 <_Z7mc_taskPv+0xbc0> + 10016b8: e13f7204 addi r4,fp,-568 + 10016bc: 10022b40 call 10022b4 <_ZNSaIcED1Ev> + 10016c0: e13f7504 addi r4,fp,-556 + 10016c4: 008005c4 movi r2,23 + 10016c8: e0bf9e15 stw r2,-392(fp) + 10016cc: 1004a240 call 1004a24 <_ZNSsD1Ev> + 10016d0: 00000e06 br 100170c <_Z7mc_taskPv+0xbf8> + 10016d4: e0fffe17 ldw r3,-8(fp) + 10016d8: e0ffcc15 stw r3,-208(fp) + 10016dc: e13f7204 addi r4,fp,-568 + 10016e0: 10022b40 call 10022b4 <_ZNSaIcED1Ev> + 10016e4: e0bfcc17 ldw r2,-208(fp) + 10016e8: e0bffe15 stw r2,-8(fp) + 10016ec: e0fffe17 ldw r3,-8(fp) + 10016f0: e0ffcb15 stw r3,-212(fp) + 10016f4: e13f7504 addi r4,fp,-556 + 10016f8: e03f9e15 stw zero,-392(fp) + 10016fc: 1004a240 call 1004a24 <_ZNSsD1Ev> + 1001700: e0bfcb17 ldw r2,-212(fp) + 1001704: e0bffe15 stw r2,-8(fp) + 1001708: 00000706 br 1001728 <_Z7mc_taskPv+0xc14> + 100170c: e13f7404 addi r4,fp,-560 + 1001710: 10022b40 call 10022b4 <_ZNSaIcED1Ev> + 1001714: e13f7704 addi r4,fp,-548 + 1001718: 00800604 movi r2,24 + 100171c: e0bf9e15 stw r2,-392(fp) + 1001720: 1004a240 call 1004a24 <_ZNSsD1Ev> + 1001724: 00000e06 br 1001760 <_Z7mc_taskPv+0xc4c> + 1001728: e0fffe17 ldw r3,-8(fp) + 100172c: e0ffca15 stw r3,-216(fp) + 1001730: e13f7404 addi r4,fp,-560 + 1001734: 10022b40 call 10022b4 <_ZNSaIcED1Ev> + 1001738: e0bfca17 ldw r2,-216(fp) + 100173c: e0bffe15 stw r2,-8(fp) + 1001740: e0fffe17 ldw r3,-8(fp) + 1001744: e0ffc915 stw r3,-220(fp) + 1001748: e13f7704 addi r4,fp,-548 + 100174c: e03f9e15 stw zero,-392(fp) + 1001750: 1004a240 call 1004a24 <_ZNSsD1Ev> + 1001754: e0bfc917 ldw r2,-220(fp) + 1001758: e0bffe15 stw r2,-8(fp) + 100175c: 00000e06 br 1001798 <_Z7mc_taskPv+0xc84> + 1001760: e13f7604 addi r4,fp,-552 + 1001764: 10022b40 call 10022b4 <_ZNSaIcED1Ev> + motor->motorCommand("right","forward", "0"); + 1001768: d0e74517 ldw r3,-25324(gp) + 100176c: e0fff615 stw r3,-40(fp) + 1001770: e13f7004 addi r4,fp,-576 + 1001774: 10022880 call 1002288 <_ZNSaIcEC1Ev> + 1001778: e13f7104 addi r4,fp,-572 + 100177c: e1bf7004 addi r6,fp,-576 + 1001780: 00800504 movi r2,20 + 1001784: e0bf9e15 stw r2,-392(fp) + 1001788: 014040b4 movhi r5,258 + 100178c: 2943d904 addi r5,r5,3940 + 1001790: 1003e680 call 1003e68 <_ZNSsC1EPKcRKSaIcE> + 1001794: 00000a06 br 10017c0 <_Z7mc_taskPv+0xcac> + 1001798: e0bffe17 ldw r2,-8(fp) + 100179c: e0bfc815 stw r2,-224(fp) + motor->motorCommand("right","forward", "0"); + OSTimeDlyHMSM(0, 0, 5, 0); + motor->motorCommand("left", "backward", "120"); + motor->motorCommand("right","backward", "120"); + OSTimeDlyHMSM(0, 0, 5, 0); + motor->motorCommand("left", "forward", "0"); + 10017a0: e13f7604 addi r4,fp,-552 + 10017a4: 10022b40 call 10022b4 <_ZNSaIcED1Ev> + 10017a8: e0ffc817 ldw r3,-224(fp) + 10017ac: e0fffe15 stw r3,-8(fp) + 10017b0: 00bfffc4 movi r2,-1 + 10017b4: e0bf9e15 stw r2,-392(fp) + 10017b8: e13ffe17 ldw r4,-8(fp) + 10017bc: 1009ee80 call 1009ee8 <_Unwind_SjLj_Resume> + motor->motorCommand("right","forward", "0"); + 10017c0: e13f6e04 addi r4,fp,-584 + 10017c4: 10022880 call 1002288 <_ZNSaIcEC1Ev> + 10017c8: e13f6f04 addi r4,fp,-580 + 10017cc: e1bf6e04 addi r6,fp,-584 + 10017d0: 008004c4 movi r2,19 + 10017d4: e0bf9e15 stw r2,-392(fp) + 10017d8: 014040b4 movhi r5,258 + 10017dc: 2943d604 addi r5,r5,3928 + 10017e0: 1003e680 call 1003e68 <_ZNSsC1EPKcRKSaIcE> + 10017e4: e13f6c04 addi r4,fp,-592 + 10017e8: 10022880 call 1002288 <_ZNSaIcEC1Ev> + 10017ec: e13f6d04 addi r4,fp,-588 + 10017f0: e1bf6c04 addi r6,fp,-592 + 10017f4: 00800484 movi r2,18 + 10017f8: e0bf9e15 stw r2,-392(fp) + 10017fc: 014040b4 movhi r5,258 + 1001800: 2943db04 addi r5,r5,3948 + 1001804: 1003e680 call 1003e68 <_ZNSsC1EPKcRKSaIcE> + 1001808: e17f7104 addi r5,fp,-572 + 100180c: e1bf6f04 addi r6,fp,-580 + 1001810: e1ff6d04 addi r7,fp,-588 + 1001814: 00800444 movi r2,17 + 1001818: e0bf9e15 stw r2,-392(fp) + 100181c: e13ff617 ldw r4,-40(fp) + 1001820: 10005980 call 1000598 <_ZN12MotorHandler12motorCommandESsSsSs> + 1001824: e13f6d04 addi r4,fp,-588 + 1001828: 00800484 movi r2,18 + 100182c: e0bf9e15 stw r2,-392(fp) + 1001830: 1004a240 call 1004a24 <_ZNSsD1Ev> + 1001834: 00000806 br 1001858 <_Z7mc_taskPv+0xd44> + 1001838: e0bffe17 ldw r2,-8(fp) + 100183c: e0bfc715 stw r2,-228(fp) + 1001840: e13f6d04 addi r4,fp,-588 + 1001844: e03f9e15 stw zero,-392(fp) + 1001848: 1004a240 call 1004a24 <_ZNSsD1Ev> + 100184c: e0ffc717 ldw r3,-228(fp) + 1001850: e0fffe15 stw r3,-8(fp) + 1001854: 00000706 br 1001874 <_Z7mc_taskPv+0xd60> + 1001858: e13f6c04 addi r4,fp,-592 + 100185c: 10022b40 call 10022b4 <_ZNSaIcED1Ev> + 1001860: e13f6f04 addi r4,fp,-580 + 1001864: 008004c4 movi r2,19 + 1001868: e0bf9e15 stw r2,-392(fp) + 100186c: 1004a240 call 1004a24 <_ZNSsD1Ev> + 1001870: 00000e06 br 10018ac <_Z7mc_taskPv+0xd98> + 1001874: e0bffe17 ldw r2,-8(fp) + 1001878: e0bfc615 stw r2,-232(fp) + 100187c: e13f6c04 addi r4,fp,-592 + 1001880: 10022b40 call 10022b4 <_ZNSaIcED1Ev> + 1001884: e0ffc617 ldw r3,-232(fp) + 1001888: e0fffe15 stw r3,-8(fp) + 100188c: e0bffe17 ldw r2,-8(fp) + 1001890: e0bfc515 stw r2,-236(fp) + 1001894: e13f6f04 addi r4,fp,-580 + 1001898: e03f9e15 stw zero,-392(fp) + 100189c: 1004a240 call 1004a24 <_ZNSsD1Ev> + 10018a0: e0ffc517 ldw r3,-236(fp) + 10018a4: e0fffe15 stw r3,-8(fp) + 10018a8: 00000706 br 10018c8 <_Z7mc_taskPv+0xdb4> + 10018ac: e13f6e04 addi r4,fp,-584 + 10018b0: 10022b40 call 10022b4 <_ZNSaIcED1Ev> + 10018b4: e13f7104 addi r4,fp,-572 + 10018b8: 00800504 movi r2,20 + 10018bc: e0bf9e15 stw r2,-392(fp) + 10018c0: 1004a240 call 1004a24 <_ZNSsD1Ev> + 10018c4: 00000e06 br 1001900 <_Z7mc_taskPv+0xdec> + 10018c8: e0bffe17 ldw r2,-8(fp) + 10018cc: e0bfc415 stw r2,-240(fp) + 10018d0: e13f6e04 addi r4,fp,-584 + 10018d4: 10022b40 call 10022b4 <_ZNSaIcED1Ev> + 10018d8: e0ffc417 ldw r3,-240(fp) + 10018dc: e0fffe15 stw r3,-8(fp) + 10018e0: e0bffe17 ldw r2,-8(fp) + 10018e4: e0bfc315 stw r2,-244(fp) + 10018e8: e13f7104 addi r4,fp,-572 + 10018ec: e03f9e15 stw zero,-392(fp) + 10018f0: 1004a240 call 1004a24 <_ZNSsD1Ev> + 10018f4: e0ffc317 ldw r3,-244(fp) + 10018f8: e0fffe15 stw r3,-8(fp) + 10018fc: 00001506 br 1001954 <_Z7mc_taskPv+0xe40> + 1001900: e13f7004 addi r4,fp,-576 + 1001904: 10022b40 call 10022b4 <_ZNSaIcED1Ev> + OSTimeDlyHMSM(0, 0, 5, 0); + 1001908: 00bfffc4 movi r2,-1 + 100190c: e0bf9e15 stw r2,-392(fp) + 1001910: 0009883a mov r4,zero + 1001914: 000b883a mov r5,zero + 1001918: 01800144 movi r6,5 + 100191c: 000f883a mov r7,zero + 1001920: 101d0f80 call 101d0f8 + motor->motorCommand("right","forward", "120"); + 1001924: d0a74517 ldw r2,-25324(gp) + 1001928: e0bff515 stw r2,-44(fp) + 100192c: e13f6a04 addi r4,fp,-600 + 1001930: 10022880 call 1002288 <_ZNSaIcEC1Ev> + 1001934: e13f6b04 addi r4,fp,-596 + 1001938: e1bf6a04 addi r6,fp,-600 + 100193c: 00800404 movi r2,16 + 1001940: e0bf9e15 stw r2,-392(fp) + 1001944: 014040b4 movhi r5,258 + 1001948: 2943d904 addi r5,r5,3940 + 100194c: 1003e680 call 1003e68 <_ZNSsC1EPKcRKSaIcE> + 1001950: 00000a06 br 100197c <_Z7mc_taskPv+0xe68> + 1001954: e0fffe17 ldw r3,-8(fp) + 1001958: e0ffc215 stw r3,-248(fp) + OSTimeDlyHMSM(0, 0, 5, 0); + motor->motorCommand("left", "backward", "120"); + motor->motorCommand("right","backward", "120"); + OSTimeDlyHMSM(0, 0, 5, 0); + motor->motorCommand("left", "forward", "0"); + motor->motorCommand("right","forward", "0"); + 100195c: e13f7004 addi r4,fp,-576 + 1001960: 10022b40 call 10022b4 <_ZNSaIcED1Ev> + 1001964: e0bfc217 ldw r2,-248(fp) + 1001968: e0bffe15 stw r2,-8(fp) + 100196c: 00bfffc4 movi r2,-1 + 1001970: e0bf9e15 stw r2,-392(fp) + 1001974: e13ffe17 ldw r4,-8(fp) + 1001978: 1009ee80 call 1009ee8 <_Unwind_SjLj_Resume> + OSTimeDlyHMSM(0, 0, 5, 0); + motor->motorCommand("right","forward", "120"); + 100197c: e13f6804 addi r4,fp,-608 + 1001980: 10022880 call 1002288 <_ZNSaIcEC1Ev> + 1001984: e13f6904 addi r4,fp,-604 + 1001988: e1bf6804 addi r6,fp,-608 + 100198c: 008003c4 movi r2,15 + 1001990: e0bf9e15 stw r2,-392(fp) + 1001994: 014040b4 movhi r5,258 + 1001998: 2943d604 addi r5,r5,3928 + 100199c: 1003e680 call 1003e68 <_ZNSsC1EPKcRKSaIcE> + 10019a0: e13f6604 addi r4,fp,-616 + 10019a4: 10022880 call 1002288 <_ZNSaIcEC1Ev> + 10019a8: e13f6704 addi r4,fp,-612 + 10019ac: e1bf6604 addi r6,fp,-616 + 10019b0: 00800384 movi r2,14 + 10019b4: e0bf9e15 stw r2,-392(fp) + 10019b8: 014040b4 movhi r5,258 + 10019bc: 2943d804 addi r5,r5,3936 + 10019c0: 1003e680 call 1003e68 <_ZNSsC1EPKcRKSaIcE> + 10019c4: e17f6b04 addi r5,fp,-596 + 10019c8: e1bf6904 addi r6,fp,-604 + 10019cc: e1ff6704 addi r7,fp,-612 + 10019d0: 00800344 movi r2,13 + 10019d4: e0bf9e15 stw r2,-392(fp) + 10019d8: e13ff517 ldw r4,-44(fp) + 10019dc: 10005980 call 1000598 <_ZN12MotorHandler12motorCommandESsSsSs> + 10019e0: e13f6704 addi r4,fp,-612 + 10019e4: 00800384 movi r2,14 + 10019e8: e0bf9e15 stw r2,-392(fp) + 10019ec: 1004a240 call 1004a24 <_ZNSsD1Ev> + 10019f0: 00000806 br 1001a14 <_Z7mc_taskPv+0xf00> + 10019f4: e0fffe17 ldw r3,-8(fp) + 10019f8: e0ffc115 stw r3,-252(fp) + 10019fc: e13f6704 addi r4,fp,-612 + 1001a00: e03f9e15 stw zero,-392(fp) + 1001a04: 1004a240 call 1004a24 <_ZNSsD1Ev> + 1001a08: e0bfc117 ldw r2,-252(fp) + 1001a0c: e0bffe15 stw r2,-8(fp) + 1001a10: 00000706 br 1001a30 <_Z7mc_taskPv+0xf1c> + 1001a14: e13f6604 addi r4,fp,-616 + 1001a18: 10022b40 call 10022b4 <_ZNSaIcED1Ev> + 1001a1c: e13f6904 addi r4,fp,-604 + 1001a20: 008003c4 movi r2,15 + 1001a24: e0bf9e15 stw r2,-392(fp) + 1001a28: 1004a240 call 1004a24 <_ZNSsD1Ev> + 1001a2c: 00000e06 br 1001a68 <_Z7mc_taskPv+0xf54> + 1001a30: e0fffe17 ldw r3,-8(fp) + 1001a34: e0ffc015 stw r3,-256(fp) + 1001a38: e13f6604 addi r4,fp,-616 + 1001a3c: 10022b40 call 10022b4 <_ZNSaIcED1Ev> + 1001a40: e0bfc017 ldw r2,-256(fp) + 1001a44: e0bffe15 stw r2,-8(fp) + 1001a48: e0fffe17 ldw r3,-8(fp) + 1001a4c: e0ffbf15 stw r3,-260(fp) + 1001a50: e13f6904 addi r4,fp,-604 + 1001a54: e03f9e15 stw zero,-392(fp) + 1001a58: 1004a240 call 1004a24 <_ZNSsD1Ev> + 1001a5c: e0bfbf17 ldw r2,-260(fp) + 1001a60: e0bffe15 stw r2,-8(fp) + 1001a64: 00000706 br 1001a84 <_Z7mc_taskPv+0xf70> + 1001a68: e13f6804 addi r4,fp,-608 + 1001a6c: 10022b40 call 10022b4 <_ZNSaIcED1Ev> + 1001a70: e13f6b04 addi r4,fp,-596 + 1001a74: 00800404 movi r2,16 + 1001a78: e0bf9e15 stw r2,-392(fp) + 1001a7c: 1004a240 call 1004a24 <_ZNSsD1Ev> + 1001a80: 00000e06 br 1001abc <_Z7mc_taskPv+0xfa8> + 1001a84: e0fffe17 ldw r3,-8(fp) + 1001a88: e0ffbe15 stw r3,-264(fp) + 1001a8c: e13f6804 addi r4,fp,-608 + 1001a90: 10022b40 call 10022b4 <_ZNSaIcED1Ev> + 1001a94: e0bfbe17 ldw r2,-264(fp) + 1001a98: e0bffe15 stw r2,-8(fp) + 1001a9c: e0fffe17 ldw r3,-8(fp) + 1001aa0: e0ffbd15 stw r3,-268(fp) + 1001aa4: e13f6b04 addi r4,fp,-596 + 1001aa8: e03f9e15 stw zero,-392(fp) + 1001aac: 1004a240 call 1004a24 <_ZNSsD1Ev> + 1001ab0: e0bfbd17 ldw r2,-268(fp) + 1001ab4: e0bffe15 stw r2,-8(fp) + 1001ab8: 00001506 br 1001b10 <_Z7mc_taskPv+0xffc> + 1001abc: e13f6a04 addi r4,fp,-600 + 1001ac0: 10022b40 call 10022b4 <_ZNSaIcED1Ev> + OSTimeDlyHMSM(0, 0, 5, 0); + 1001ac4: 00bfffc4 movi r2,-1 + 1001ac8: e0bf9e15 stw r2,-392(fp) + 1001acc: 0009883a mov r4,zero + 1001ad0: 000b883a mov r5,zero + 1001ad4: 01800144 movi r6,5 + 1001ad8: 000f883a mov r7,zero + 1001adc: 101d0f80 call 101d0f8 + motor->motorCommand("right","forward", "0"); + 1001ae0: d0e74517 ldw r3,-25324(gp) + 1001ae4: e0fff415 stw r3,-48(fp) + 1001ae8: e13f6404 addi r4,fp,-624 + 1001aec: 10022880 call 1002288 <_ZNSaIcEC1Ev> + 1001af0: e13f6504 addi r4,fp,-620 + 1001af4: e1bf6404 addi r6,fp,-624 + 1001af8: 00800304 movi r2,12 + 1001afc: e0bf9e15 stw r2,-392(fp) + 1001b00: 014040b4 movhi r5,258 + 1001b04: 2943d904 addi r5,r5,3940 + 1001b08: 1003e680 call 1003e68 <_ZNSsC1EPKcRKSaIcE> + 1001b0c: 00000a06 br 1001b38 <_Z7mc_taskPv+0x1024> + 1001b10: e0bffe17 ldw r2,-8(fp) + 1001b14: e0bfbc15 stw r2,-272(fp) + motor->motorCommand("right","backward", "120"); + OSTimeDlyHMSM(0, 0, 5, 0); + motor->motorCommand("left", "forward", "0"); + motor->motorCommand("right","forward", "0"); + OSTimeDlyHMSM(0, 0, 5, 0); + motor->motorCommand("right","forward", "120"); + 1001b18: e13f6a04 addi r4,fp,-600 + 1001b1c: 10022b40 call 10022b4 <_ZNSaIcED1Ev> + 1001b20: e0ffbc17 ldw r3,-272(fp) + 1001b24: e0fffe15 stw r3,-8(fp) + 1001b28: 00bfffc4 movi r2,-1 + 1001b2c: e0bf9e15 stw r2,-392(fp) + 1001b30: e13ffe17 ldw r4,-8(fp) + 1001b34: 1009ee80 call 1009ee8 <_Unwind_SjLj_Resume> + OSTimeDlyHMSM(0, 0, 5, 0); + motor->motorCommand("right","forward", "0"); + 1001b38: e13f6204 addi r4,fp,-632 + 1001b3c: 10022880 call 1002288 <_ZNSaIcEC1Ev> + 1001b40: e13f6304 addi r4,fp,-628 + 1001b44: e1bf6204 addi r6,fp,-632 + 1001b48: 008002c4 movi r2,11 + 1001b4c: e0bf9e15 stw r2,-392(fp) + 1001b50: 014040b4 movhi r5,258 + 1001b54: 2943d604 addi r5,r5,3928 + 1001b58: 1003e680 call 1003e68 <_ZNSsC1EPKcRKSaIcE> + 1001b5c: e13f6004 addi r4,fp,-640 + 1001b60: 10022880 call 1002288 <_ZNSaIcEC1Ev> + 1001b64: e13f6104 addi r4,fp,-636 + 1001b68: e1bf6004 addi r6,fp,-640 + 1001b6c: 00800284 movi r2,10 + 1001b70: e0bf9e15 stw r2,-392(fp) + 1001b74: 014040b4 movhi r5,258 + 1001b78: 2943db04 addi r5,r5,3948 + 1001b7c: 1003e680 call 1003e68 <_ZNSsC1EPKcRKSaIcE> + 1001b80: e17f6504 addi r5,fp,-620 + 1001b84: e1bf6304 addi r6,fp,-628 + 1001b88: e1ff6104 addi r7,fp,-636 + 1001b8c: 00800244 movi r2,9 + 1001b90: e0bf9e15 stw r2,-392(fp) + 1001b94: e13ff417 ldw r4,-48(fp) + 1001b98: 10005980 call 1000598 <_ZN12MotorHandler12motorCommandESsSsSs> + 1001b9c: e13f6104 addi r4,fp,-636 + 1001ba0: 00800284 movi r2,10 + 1001ba4: e0bf9e15 stw r2,-392(fp) + 1001ba8: 1004a240 call 1004a24 <_ZNSsD1Ev> + 1001bac: 00000806 br 1001bd0 <_Z7mc_taskPv+0x10bc> + 1001bb0: e0bffe17 ldw r2,-8(fp) + 1001bb4: e0bfbb15 stw r2,-276(fp) + 1001bb8: e13f6104 addi r4,fp,-636 + 1001bbc: e03f9e15 stw zero,-392(fp) + 1001bc0: 1004a240 call 1004a24 <_ZNSsD1Ev> + 1001bc4: e0ffbb17 ldw r3,-276(fp) + 1001bc8: e0fffe15 stw r3,-8(fp) + 1001bcc: 00000706 br 1001bec <_Z7mc_taskPv+0x10d8> + 1001bd0: e13f6004 addi r4,fp,-640 + 1001bd4: 10022b40 call 10022b4 <_ZNSaIcED1Ev> + 1001bd8: e13f6304 addi r4,fp,-628 + 1001bdc: 008002c4 movi r2,11 + 1001be0: e0bf9e15 stw r2,-392(fp) + 1001be4: 1004a240 call 1004a24 <_ZNSsD1Ev> + 1001be8: 00000e06 br 1001c24 <_Z7mc_taskPv+0x1110> + 1001bec: e0bffe17 ldw r2,-8(fp) + 1001bf0: e0bfba15 stw r2,-280(fp) + 1001bf4: e13f6004 addi r4,fp,-640 + 1001bf8: 10022b40 call 10022b4 <_ZNSaIcED1Ev> + 1001bfc: e0ffba17 ldw r3,-280(fp) + 1001c00: e0fffe15 stw r3,-8(fp) + 1001c04: e0bffe17 ldw r2,-8(fp) + 1001c08: e0bfb915 stw r2,-284(fp) + 1001c0c: e13f6304 addi r4,fp,-628 + 1001c10: e03f9e15 stw zero,-392(fp) + 1001c14: 1004a240 call 1004a24 <_ZNSsD1Ev> + 1001c18: e0ffb917 ldw r3,-284(fp) + 1001c1c: e0fffe15 stw r3,-8(fp) + 1001c20: 00000706 br 1001c40 <_Z7mc_taskPv+0x112c> + 1001c24: e13f6204 addi r4,fp,-632 + 1001c28: 10022b40 call 10022b4 <_ZNSaIcED1Ev> + 1001c2c: e13f6504 addi r4,fp,-620 + 1001c30: 00800304 movi r2,12 + 1001c34: e0bf9e15 stw r2,-392(fp) + 1001c38: 1004a240 call 1004a24 <_ZNSsD1Ev> + 1001c3c: 00000e06 br 1001c78 <_Z7mc_taskPv+0x1164> + 1001c40: e0bffe17 ldw r2,-8(fp) + 1001c44: e0bfb815 stw r2,-288(fp) + 1001c48: e13f6204 addi r4,fp,-632 + 1001c4c: 10022b40 call 10022b4 <_ZNSaIcED1Ev> + 1001c50: e0ffb817 ldw r3,-288(fp) + 1001c54: e0fffe15 stw r3,-8(fp) + 1001c58: e0bffe17 ldw r2,-8(fp) + 1001c5c: e0bfb715 stw r2,-292(fp) + 1001c60: e13f6504 addi r4,fp,-620 + 1001c64: e03f9e15 stw zero,-392(fp) + 1001c68: 1004a240 call 1004a24 <_ZNSsD1Ev> + 1001c6c: e0ffb717 ldw r3,-292(fp) + 1001c70: e0fffe15 stw r3,-8(fp) + 1001c74: 00001506 br 1001ccc <_Z7mc_taskPv+0x11b8> + 1001c78: e13f6404 addi r4,fp,-624 + 1001c7c: 10022b40 call 10022b4 <_ZNSaIcED1Ev> + OSTimeDlyHMSM(0, 0, 5, 0); + 1001c80: 00bfffc4 movi r2,-1 + 1001c84: e0bf9e15 stw r2,-392(fp) + 1001c88: 0009883a mov r4,zero + 1001c8c: 000b883a mov r5,zero + 1001c90: 01800144 movi r6,5 + 1001c94: 000f883a mov r7,zero + 1001c98: 101d0f80 call 101d0f8 + motor->motorCommand("left","forward", "120"); + 1001c9c: d0a74517 ldw r2,-25324(gp) + 1001ca0: e0bff315 stw r2,-52(fp) + 1001ca4: e13f5e04 addi r4,fp,-648 + 1001ca8: 10022880 call 1002288 <_ZNSaIcEC1Ev> + 1001cac: e13f5f04 addi r4,fp,-644 + 1001cb0: e1bf5e04 addi r6,fp,-648 + 1001cb4: 00800204 movi r2,8 + 1001cb8: e0bf9e15 stw r2,-392(fp) + 1001cbc: 014040b4 movhi r5,258 + 1001cc0: 2943d404 addi r5,r5,3920 + 1001cc4: 1003e680 call 1003e68 <_ZNSsC1EPKcRKSaIcE> + 1001cc8: 00000a06 br 1001cf4 <_Z7mc_taskPv+0x11e0> + 1001ccc: e0fffe17 ldw r3,-8(fp) + 1001cd0: e0ffb615 stw r3,-296(fp) + motor->motorCommand("left", "forward", "0"); + motor->motorCommand("right","forward", "0"); + OSTimeDlyHMSM(0, 0, 5, 0); + motor->motorCommand("right","forward", "120"); + OSTimeDlyHMSM(0, 0, 5, 0); + motor->motorCommand("right","forward", "0"); + 1001cd4: e13f6404 addi r4,fp,-624 + 1001cd8: 10022b40 call 10022b4 <_ZNSaIcED1Ev> + 1001cdc: e0bfb617 ldw r2,-296(fp) + 1001ce0: e0bffe15 stw r2,-8(fp) + 1001ce4: 00bfffc4 movi r2,-1 + 1001ce8: e0bf9e15 stw r2,-392(fp) + 1001cec: e13ffe17 ldw r4,-8(fp) + 1001cf0: 1009ee80 call 1009ee8 <_Unwind_SjLj_Resume> + OSTimeDlyHMSM(0, 0, 5, 0); + motor->motorCommand("left","forward", "120"); + 1001cf4: e13f5c04 addi r4,fp,-656 + 1001cf8: 10022880 call 1002288 <_ZNSaIcEC1Ev> + 1001cfc: e13f5d04 addi r4,fp,-652 + 1001d00: e1bf5c04 addi r6,fp,-656 + 1001d04: 008001c4 movi r2,7 + 1001d08: e0bf9e15 stw r2,-392(fp) + 1001d0c: 014040b4 movhi r5,258 + 1001d10: 2943d604 addi r5,r5,3928 + 1001d14: 1003e680 call 1003e68 <_ZNSsC1EPKcRKSaIcE> + 1001d18: e13f5a04 addi r4,fp,-664 + 1001d1c: 10022880 call 1002288 <_ZNSaIcEC1Ev> + 1001d20: e13f5b04 addi r4,fp,-660 + 1001d24: e1bf5a04 addi r6,fp,-664 + 1001d28: 00800184 movi r2,6 + 1001d2c: e0bf9e15 stw r2,-392(fp) + 1001d30: 014040b4 movhi r5,258 + 1001d34: 2943d804 addi r5,r5,3936 + 1001d38: 1003e680 call 1003e68 <_ZNSsC1EPKcRKSaIcE> + 1001d3c: e17f5f04 addi r5,fp,-644 + 1001d40: e1bf5d04 addi r6,fp,-652 + 1001d44: e1ff5b04 addi r7,fp,-660 + 1001d48: 00800144 movi r2,5 + 1001d4c: e0bf9e15 stw r2,-392(fp) + 1001d50: e13ff317 ldw r4,-52(fp) + 1001d54: 10005980 call 1000598 <_ZN12MotorHandler12motorCommandESsSsSs> + 1001d58: e13f5b04 addi r4,fp,-660 + 1001d5c: 00800184 movi r2,6 + 1001d60: e0bf9e15 stw r2,-392(fp) + 1001d64: 1004a240 call 1004a24 <_ZNSsD1Ev> + 1001d68: 00000806 br 1001d8c <_Z7mc_taskPv+0x1278> + 1001d6c: e0fffe17 ldw r3,-8(fp) + 1001d70: e0ffb515 stw r3,-300(fp) + 1001d74: e13f5b04 addi r4,fp,-660 + 1001d78: e03f9e15 stw zero,-392(fp) + 1001d7c: 1004a240 call 1004a24 <_ZNSsD1Ev> + 1001d80: e0bfb517 ldw r2,-300(fp) + 1001d84: e0bffe15 stw r2,-8(fp) + 1001d88: 00000706 br 1001da8 <_Z7mc_taskPv+0x1294> + 1001d8c: e13f5a04 addi r4,fp,-664 + 1001d90: 10022b40 call 10022b4 <_ZNSaIcED1Ev> + 1001d94: e13f5d04 addi r4,fp,-652 + 1001d98: 008001c4 movi r2,7 + 1001d9c: e0bf9e15 stw r2,-392(fp) + 1001da0: 1004a240 call 1004a24 <_ZNSsD1Ev> + 1001da4: 00000e06 br 1001de0 <_Z7mc_taskPv+0x12cc> + 1001da8: e0fffe17 ldw r3,-8(fp) + 1001dac: e0ffb415 stw r3,-304(fp) + 1001db0: e13f5a04 addi r4,fp,-664 + 1001db4: 10022b40 call 10022b4 <_ZNSaIcED1Ev> + 1001db8: e0bfb417 ldw r2,-304(fp) + 1001dbc: e0bffe15 stw r2,-8(fp) + 1001dc0: e0fffe17 ldw r3,-8(fp) + 1001dc4: e0ffb315 stw r3,-308(fp) + 1001dc8: e13f5d04 addi r4,fp,-652 + 1001dcc: e03f9e15 stw zero,-392(fp) + 1001dd0: 1004a240 call 1004a24 <_ZNSsD1Ev> + 1001dd4: e0bfb317 ldw r2,-308(fp) + 1001dd8: e0bffe15 stw r2,-8(fp) + 1001ddc: 00000706 br 1001dfc <_Z7mc_taskPv+0x12e8> + 1001de0: e13f5c04 addi r4,fp,-656 + 1001de4: 10022b40 call 10022b4 <_ZNSaIcED1Ev> + 1001de8: e13f5f04 addi r4,fp,-644 + 1001dec: 00800204 movi r2,8 + 1001df0: e0bf9e15 stw r2,-392(fp) + 1001df4: 1004a240 call 1004a24 <_ZNSsD1Ev> + 1001df8: 00000e06 br 1001e34 <_Z7mc_taskPv+0x1320> + 1001dfc: e0fffe17 ldw r3,-8(fp) + 1001e00: e0ffb215 stw r3,-312(fp) + 1001e04: e13f5c04 addi r4,fp,-656 + 1001e08: 10022b40 call 10022b4 <_ZNSaIcED1Ev> + 1001e0c: e0bfb217 ldw r2,-312(fp) + 1001e10: e0bffe15 stw r2,-8(fp) + 1001e14: e0fffe17 ldw r3,-8(fp) + 1001e18: e0ffb115 stw r3,-316(fp) + 1001e1c: e13f5f04 addi r4,fp,-644 + 1001e20: e03f9e15 stw zero,-392(fp) + 1001e24: 1004a240 call 1004a24 <_ZNSsD1Ev> + 1001e28: e0bfb117 ldw r2,-316(fp) + 1001e2c: e0bffe15 stw r2,-8(fp) + 1001e30: 00001506 br 1001e88 <_Z7mc_taskPv+0x1374> + 1001e34: e13f5e04 addi r4,fp,-648 + 1001e38: 10022b40 call 10022b4 <_ZNSaIcED1Ev> + OSTimeDlyHMSM(0, 0, 5, 0); + 1001e3c: 00bfffc4 movi r2,-1 + 1001e40: e0bf9e15 stw r2,-392(fp) + 1001e44: 0009883a mov r4,zero + 1001e48: 000b883a mov r5,zero + 1001e4c: 01800144 movi r6,5 + 1001e50: 000f883a mov r7,zero + 1001e54: 101d0f80 call 101d0f8 + motor->motorCommand("left","forward", "0"); + 1001e58: d0e74517 ldw r3,-25324(gp) + 1001e5c: e0fff215 stw r3,-56(fp) + 1001e60: e13f5804 addi r4,fp,-672 + 1001e64: 10022880 call 1002288 <_ZNSaIcEC1Ev> + 1001e68: e13f5904 addi r4,fp,-668 + 1001e6c: e1bf5804 addi r6,fp,-672 + 1001e70: 00800104 movi r2,4 + 1001e74: e0bf9e15 stw r2,-392(fp) + 1001e78: 014040b4 movhi r5,258 + 1001e7c: 2943d404 addi r5,r5,3920 + 1001e80: 1003e680 call 1003e68 <_ZNSsC1EPKcRKSaIcE> + 1001e84: 00000a06 br 1001eb0 <_Z7mc_taskPv+0x139c> + 1001e88: e0bffe17 ldw r2,-8(fp) + 1001e8c: e0bfb015 stw r2,-320(fp) + OSTimeDlyHMSM(0, 0, 5, 0); + motor->motorCommand("right","forward", "120"); + OSTimeDlyHMSM(0, 0, 5, 0); + motor->motorCommand("right","forward", "0"); + OSTimeDlyHMSM(0, 0, 5, 0); + motor->motorCommand("left","forward", "120"); + 1001e90: e13f5e04 addi r4,fp,-648 + 1001e94: 10022b40 call 10022b4 <_ZNSaIcED1Ev> + 1001e98: e0ffb017 ldw r3,-320(fp) + 1001e9c: e0fffe15 stw r3,-8(fp) + 1001ea0: 00bfffc4 movi r2,-1 + 1001ea4: e0bf9e15 stw r2,-392(fp) + 1001ea8: e13ffe17 ldw r4,-8(fp) + 1001eac: 1009ee80 call 1009ee8 <_Unwind_SjLj_Resume> + OSTimeDlyHMSM(0, 0, 5, 0); + motor->motorCommand("left","forward", "0"); + 1001eb0: e13f5604 addi r4,fp,-680 + 1001eb4: 10022880 call 1002288 <_ZNSaIcEC1Ev> + 1001eb8: e13f5704 addi r4,fp,-676 + 1001ebc: e1bf5604 addi r6,fp,-680 + 1001ec0: 008000c4 movi r2,3 + 1001ec4: e0bf9e15 stw r2,-392(fp) + 1001ec8: 014040b4 movhi r5,258 + 1001ecc: 2943d604 addi r5,r5,3928 + 1001ed0: 1003e680 call 1003e68 <_ZNSsC1EPKcRKSaIcE> + 1001ed4: e13f5404 addi r4,fp,-688 + 1001ed8: 10022880 call 1002288 <_ZNSaIcEC1Ev> + 1001edc: e13f5504 addi r4,fp,-684 + 1001ee0: 00800084 movi r2,2 + 1001ee4: e0bf9e15 stw r2,-392(fp) + 1001ee8: 014040b4 movhi r5,258 + 1001eec: 2943db04 addi r5,r5,3948 + 1001ef0: e1bf5404 addi r6,fp,-688 + 1001ef4: 1003e680 call 1003e68 <_ZNSsC1EPKcRKSaIcE> + 1001ef8: e17f5904 addi r5,fp,-668 + 1001efc: e1bf5704 addi r6,fp,-676 + 1001f00: e1ff5504 addi r7,fp,-684 + 1001f04: 00800044 movi r2,1 + 1001f08: e0bf9e15 stw r2,-392(fp) + 1001f0c: e13ff217 ldw r4,-56(fp) + 1001f10: 10005980 call 1000598 <_ZN12MotorHandler12motorCommandESsSsSs> + 1001f14: e13f5504 addi r4,fp,-684 + 1001f18: 00800084 movi r2,2 + 1001f1c: e0bf9e15 stw r2,-392(fp) + 1001f20: 1004a240 call 1004a24 <_ZNSsD1Ev> + 1001f24: 00009a06 br 1002190 <_Z7mc_taskPv+0x167c> + 1001f28: e700ac04 addi fp,fp,688 + 1001f2c: e0bf9e17 ldw r2,-392(fp) + 1001f30: e0bfff15 stw r2,-4(fp) + 1001f34: e0ff9f17 ldw r3,-388(fp) + 1001f38: e0fffe15 stw r3,-8(fp) + 1001f3c: e0ffff17 ldw r3,-4(fp) + 1001f40: 18800060 cmpeqi r2,r3,1 + 1001f44: 1000991e bne r2,zero,10021ac <_Z7mc_taskPv+0x1698> + 1001f48: e0ffff17 ldw r3,-4(fp) + 1001f4c: 188000a0 cmpeqi r2,r3,2 + 1001f50: 1000ab1e bne r2,zero,1002200 <_Z7mc_taskPv+0x16ec> + 1001f54: e0ffff17 ldw r3,-4(fp) + 1001f58: 188000e0 cmpeqi r2,r3,3 + 1001f5c: 1000c01e bne r2,zero,1002260 <_Z7mc_taskPv+0x174c> + 1001f60: e0ffff17 ldw r3,-4(fp) + 1001f64: 18800120 cmpeqi r2,r3,4 + 1001f68: 103f801e bne r2,zero,1001d6c <_Z7mc_taskPv+0x1258> + 1001f6c: e0ffff17 ldw r3,-4(fp) + 1001f70: 18800160 cmpeqi r2,r3,5 + 1001f74: 103f8c1e bne r2,zero,1001da8 <_Z7mc_taskPv+0x1294> + 1001f78: e0ffff17 ldw r3,-4(fp) + 1001f7c: 188001a0 cmpeqi r2,r3,6 + 1001f80: 103f9e1e bne r2,zero,1001dfc <_Z7mc_taskPv+0x12e8> + 1001f84: e0ffff17 ldw r3,-4(fp) + 1001f88: 188001e0 cmpeqi r2,r3,7 + 1001f8c: 103fbe1e bne r2,zero,1001e88 <_Z7mc_taskPv+0x1374> + 1001f90: e0ffff17 ldw r3,-4(fp) + 1001f94: 18800220 cmpeqi r2,r3,8 + 1001f98: 103f051e bne r2,zero,1001bb0 <_Z7mc_taskPv+0x109c> + 1001f9c: e0ffff17 ldw r3,-4(fp) + 1001fa0: 18800260 cmpeqi r2,r3,9 + 1001fa4: 103f111e bne r2,zero,1001bec <_Z7mc_taskPv+0x10d8> + 1001fa8: e0ffff17 ldw r3,-4(fp) + 1001fac: 188002a0 cmpeqi r2,r3,10 + 1001fb0: 103f231e bne r2,zero,1001c40 <_Z7mc_taskPv+0x112c> + 1001fb4: e0ffff17 ldw r3,-4(fp) + 1001fb8: 188002e0 cmpeqi r2,r3,11 + 1001fbc: 103f431e bne r2,zero,1001ccc <_Z7mc_taskPv+0x11b8> + 1001fc0: e0ffff17 ldw r3,-4(fp) + 1001fc4: 18800320 cmpeqi r2,r3,12 + 1001fc8: 103e8a1e bne r2,zero,10019f4 <_Z7mc_taskPv+0xee0> + 1001fcc: e0ffff17 ldw r3,-4(fp) + 1001fd0: 18800360 cmpeqi r2,r3,13 + 1001fd4: 103e961e bne r2,zero,1001a30 <_Z7mc_taskPv+0xf1c> + 1001fd8: e0ffff17 ldw r3,-4(fp) + 1001fdc: 188003a0 cmpeqi r2,r3,14 + 1001fe0: 103ea81e bne r2,zero,1001a84 <_Z7mc_taskPv+0xf70> + 1001fe4: e0ffff17 ldw r3,-4(fp) + 1001fe8: 188003e0 cmpeqi r2,r3,15 + 1001fec: 103ec81e bne r2,zero,1001b10 <_Z7mc_taskPv+0xffc> + 1001ff0: e0ffff17 ldw r3,-4(fp) + 1001ff4: 18800420 cmpeqi r2,r3,16 + 1001ff8: 103e0f1e bne r2,zero,1001838 <_Z7mc_taskPv+0xd24> + 1001ffc: e0ffff17 ldw r3,-4(fp) + 1002000: 18800460 cmpeqi r2,r3,17 + 1002004: 103e1b1e bne r2,zero,1001874 <_Z7mc_taskPv+0xd60> + 1002008: e0ffff17 ldw r3,-4(fp) + 100200c: 188004a0 cmpeqi r2,r3,18 + 1002010: 103e2d1e bne r2,zero,10018c8 <_Z7mc_taskPv+0xdb4> + 1002014: e0ffff17 ldw r3,-4(fp) + 1002018: 188004e0 cmpeqi r2,r3,19 + 100201c: 103e4d1e bne r2,zero,1001954 <_Z7mc_taskPv+0xe40> + 1002020: e0ffff17 ldw r3,-4(fp) + 1002024: 18800520 cmpeqi r2,r3,20 + 1002028: 103d9b1e bne r2,zero,1001698 <_Z7mc_taskPv+0xb84> + 100202c: e0ffff17 ldw r3,-4(fp) + 1002030: 18800560 cmpeqi r2,r3,21 + 1002034: 103da71e bne r2,zero,10016d4 <_Z7mc_taskPv+0xbc0> + 1002038: e0ffff17 ldw r3,-4(fp) + 100203c: 188005a0 cmpeqi r2,r3,22 + 1002040: 103db91e bne r2,zero,1001728 <_Z7mc_taskPv+0xc14> + 1002044: e0ffff17 ldw r3,-4(fp) + 1002048: 188005e0 cmpeqi r2,r3,23 + 100204c: 103dd21e bne r2,zero,1001798 <_Z7mc_taskPv+0xc84> + 1002050: e0ffff17 ldw r3,-4(fp) + 1002054: 18800620 cmpeqi r2,r3,24 + 1002058: 103d201e bne r2,zero,10014dc <_Z7mc_taskPv+0x9c8> + 100205c: e0ffff17 ldw r3,-4(fp) + 1002060: 18800660 cmpeqi r2,r3,25 + 1002064: 103d2c1e bne r2,zero,1001518 <_Z7mc_taskPv+0xa04> + 1002068: e0ffff17 ldw r3,-4(fp) + 100206c: 188006a0 cmpeqi r2,r3,26 + 1002070: 103d3e1e bne r2,zero,100156c <_Z7mc_taskPv+0xa58> + 1002074: e0ffff17 ldw r3,-4(fp) + 1002078: 188006e0 cmpeqi r2,r3,27 + 100207c: 103d5e1e bne r2,zero,10015f8 <_Z7mc_taskPv+0xae4> + 1002080: e0ffff17 ldw r3,-4(fp) + 1002084: 18800720 cmpeqi r2,r3,28 + 1002088: 103cac1e bne r2,zero,100133c <_Z7mc_taskPv+0x828> + 100208c: e0ffff17 ldw r3,-4(fp) + 1002090: 18800760 cmpeqi r2,r3,29 + 1002094: 103cb81e bne r2,zero,1001378 <_Z7mc_taskPv+0x864> + 1002098: e0ffff17 ldw r3,-4(fp) + 100209c: 188007a0 cmpeqi r2,r3,30 + 10020a0: 103cca1e bne r2,zero,10013cc <_Z7mc_taskPv+0x8b8> + 10020a4: e0ffff17 ldw r3,-4(fp) + 10020a8: 188007e0 cmpeqi r2,r3,31 + 10020ac: 103ce31e bne r2,zero,100143c <_Z7mc_taskPv+0x928> + 10020b0: e0ffff17 ldw r3,-4(fp) + 10020b4: 18800820 cmpeqi r2,r3,32 + 10020b8: 103c311e bne r2,zero,1001180 <_Z7mc_taskPv+0x66c> + 10020bc: e0ffff17 ldw r3,-4(fp) + 10020c0: 18800860 cmpeqi r2,r3,33 + 10020c4: 103c3d1e bne r2,zero,10011bc <_Z7mc_taskPv+0x6a8> + 10020c8: e0ffff17 ldw r3,-4(fp) + 10020cc: 188008a0 cmpeqi r2,r3,34 + 10020d0: 103c4f1e bne r2,zero,1001210 <_Z7mc_taskPv+0x6fc> + 10020d4: e0ffff17 ldw r3,-4(fp) + 10020d8: 188008e0 cmpeqi r2,r3,35 + 10020dc: 103c6f1e bne r2,zero,100129c <_Z7mc_taskPv+0x788> + 10020e0: e0ffff17 ldw r3,-4(fp) + 10020e4: 18800920 cmpeqi r2,r3,36 + 10020e8: 103bbd1e bne r2,zero,1000fe0 <_Z7mc_taskPv+0x4cc> + 10020ec: e0ffff17 ldw r3,-4(fp) + 10020f0: 18800960 cmpeqi r2,r3,37 + 10020f4: 103bc91e bne r2,zero,100101c <_Z7mc_taskPv+0x508> + 10020f8: e0ffff17 ldw r3,-4(fp) + 10020fc: 188009a0 cmpeqi r2,r3,38 + 1002100: 103bdb1e bne r2,zero,1001070 <_Z7mc_taskPv+0x55c> + 1002104: e0ffff17 ldw r3,-4(fp) + 1002108: 188009e0 cmpeqi r2,r3,39 + 100210c: 103bf41e bne r2,zero,10010e0 <_Z7mc_taskPv+0x5cc> + 1002110: e0ffff17 ldw r3,-4(fp) + 1002114: 18800a20 cmpeqi r2,r3,40 + 1002118: 103b421e bne r2,zero,1000e24 <_Z7mc_taskPv+0x310> + 100211c: e0ffff17 ldw r3,-4(fp) + 1002120: 18800a60 cmpeqi r2,r3,41 + 1002124: 103b4e1e bne r2,zero,1000e60 <_Z7mc_taskPv+0x34c> + 1002128: e0ffff17 ldw r3,-4(fp) + 100212c: 18800aa0 cmpeqi r2,r3,42 + 1002130: 103b601e bne r2,zero,1000eb4 <_Z7mc_taskPv+0x3a0> + 1002134: e0ffff17 ldw r3,-4(fp) + 1002138: 18800ae0 cmpeqi r2,r3,43 + 100213c: 103b801e bne r2,zero,1000f40 <_Z7mc_taskPv+0x42c> + 1002140: e0ffff17 ldw r3,-4(fp) + 1002144: 18800b20 cmpeqi r2,r3,44 + 1002148: 103ace1e bne r2,zero,1000c84 <_Z7mc_taskPv+0x170> + 100214c: e0ffff17 ldw r3,-4(fp) + 1002150: 18800b60 cmpeqi r2,r3,45 + 1002154: 103ada1e bne r2,zero,1000cc0 <_Z7mc_taskPv+0x1ac> + 1002158: e0ffff17 ldw r3,-4(fp) + 100215c: 18800ba0 cmpeqi r2,r3,46 + 1002160: 103aec1e bne r2,zero,1000d14 <_Z7mc_taskPv+0x200> + 1002164: e0ffff17 ldw r3,-4(fp) + 1002168: 18800be0 cmpeqi r2,r3,47 + 100216c: 103b051e bne r2,zero,1000d84 <_Z7mc_taskPv+0x270> + 1002170: e0bffe17 ldw r2,-8(fp) + 1002174: e0bfaf15 stw r2,-324(fp) + 1002178: e13f5504 addi r4,fp,-684 + 100217c: e03f9e15 stw zero,-392(fp) + 1002180: 1004a240 call 1004a24 <_ZNSsD1Ev> + 1002184: e0ffaf17 ldw r3,-324(fp) + 1002188: e0fffe15 stw r3,-8(fp) + 100218c: 00000706 br 10021ac <_Z7mc_taskPv+0x1698> + 1002190: e13f5404 addi r4,fp,-688 + 1002194: 10022b40 call 10022b4 <_ZNSaIcED1Ev> + 1002198: e13f5704 addi r4,fp,-676 + 100219c: 008000c4 movi r2,3 + 10021a0: e0bf9e15 stw r2,-392(fp) + 10021a4: 1004a240 call 1004a24 <_ZNSsD1Ev> + 10021a8: 00000e06 br 10021e4 <_Z7mc_taskPv+0x16d0> + 10021ac: e0bffe17 ldw r2,-8(fp) + 10021b0: e0bfae15 stw r2,-328(fp) + 10021b4: e13f5404 addi r4,fp,-688 + 10021b8: 10022b40 call 10022b4 <_ZNSaIcED1Ev> + 10021bc: e0ffae17 ldw r3,-328(fp) + 10021c0: e0fffe15 stw r3,-8(fp) + 10021c4: e0bffe17 ldw r2,-8(fp) + 10021c8: e0bfad15 stw r2,-332(fp) + 10021cc: e13f5704 addi r4,fp,-676 + 10021d0: e03f9e15 stw zero,-392(fp) + 10021d4: 1004a240 call 1004a24 <_ZNSsD1Ev> + 10021d8: e0ffad17 ldw r3,-332(fp) + 10021dc: e0fffe15 stw r3,-8(fp) + 10021e0: 00000706 br 1002200 <_Z7mc_taskPv+0x16ec> + 10021e4: e13f5604 addi r4,fp,-680 + 10021e8: 10022b40 call 10022b4 <_ZNSaIcED1Ev> + 10021ec: e13f5904 addi r4,fp,-668 + 10021f0: 00800104 movi r2,4 + 10021f4: e0bf9e15 stw r2,-392(fp) + 10021f8: 1004a240 call 1004a24 <_ZNSsD1Ev> + 10021fc: 00000e06 br 1002238 <_Z7mc_taskPv+0x1724> + 1002200: e0bffe17 ldw r2,-8(fp) + 1002204: e0bfac15 stw r2,-336(fp) + 1002208: e13f5604 addi r4,fp,-680 + 100220c: 10022b40 call 10022b4 <_ZNSaIcED1Ev> + 1002210: e0ffac17 ldw r3,-336(fp) + 1002214: e0fffe15 stw r3,-8(fp) + 1002218: e0bffe17 ldw r2,-8(fp) + 100221c: e0bfab15 stw r2,-340(fp) + 1002220: e13f5904 addi r4,fp,-668 + 1002224: e03f9e15 stw zero,-392(fp) + 1002228: 1004a240 call 1004a24 <_ZNSsD1Ev> + 100222c: e0ffab17 ldw r3,-340(fp) + 1002230: e0fffe15 stw r3,-8(fp) + 1002234: 00000a06 br 1002260 <_Z7mc_taskPv+0x174c> + 1002238: e13f5804 addi r4,fp,-672 + 100223c: 10022b40 call 10022b4 <_ZNSaIcED1Ev> + OSTimeDlyHMSM(0, 0, 5, 0); + 1002240: 00bfffc4 movi r2,-1 + 1002244: e0bf9e15 stw r2,-392(fp) + 1002248: 0009883a mov r4,zero + 100224c: 000b883a mov r5,zero + 1002250: 01800144 movi r6,5 + 1002254: 000f883a mov r7,zero + 1002258: 101d0f80 call 101d0f8 + if (motor->init() == OK) { + printf("]\n\n"); + } else { + printf( ", error]\n"); + } + while(1){ + 100225c: 003a6006 br 1000be0 <_Z7mc_taskPv+0xcc> + 1002260: e0bffe17 ldw r2,-8(fp) + 1002264: e0bfaa15 stw r2,-344(fp) + OSTimeDlyHMSM(0, 0, 5, 0); + motor->motorCommand("right","forward", "0"); + OSTimeDlyHMSM(0, 0, 5, 0); + motor->motorCommand("left","forward", "120"); + OSTimeDlyHMSM(0, 0, 5, 0); + motor->motorCommand("left","forward", "0"); + 1002268: e13f5804 addi r4,fp,-672 + 100226c: 10022b40 call 10022b4 <_ZNSaIcED1Ev> + 1002270: e0ffaa17 ldw r3,-344(fp) + 1002274: e0fffe15 stw r3,-8(fp) + 1002278: 00bfffc4 movi r2,-1 + 100227c: e0bf9e15 stw r2,-392(fp) + 1002280: e13ffe17 ldw r4,-8(fp) + 1002284: 1009ee80 call 1009ee8 <_Unwind_SjLj_Resume> + +01002288 <_ZNSaIcEC1Ev>: + 1002288: f800283a ret + +0100228c <_ZNSaIcED2Ev>: + 100228c: f800283a ret + +01002290 <_ZNSaIcEC2ERKS_>: + 1002290: f800283a ret + +01002294 <_ZNSaIwEC2Ev>: + 1002294: f800283a ret + +01002298 <_ZNSaIwED1Ev>: + 1002298: f800283a ret + +0100229c <_ZNSaIwEC1ERKS_>: + 100229c: f800283a ret + +010022a0 <_ZNSaIwEC2ERKS_>: + 10022a0: f800283a ret + +010022a4 <_ZNSaIcEC1ERKS_>: + 10022a4: f800283a ret + +010022a8 <_ZNSaIwEC1Ev>: + 10022a8: f800283a ret + +010022ac <_ZNSaIwED2Ev>: + 10022ac: f800283a ret + +010022b0 <_ZNSaIcEC2Ev>: + 10022b0: f800283a ret + +010022b4 <_ZNSaIcED1Ev>: + 10022b4: f800283a ret + +010022b8 <_ZNSt11char_traitsIcE2eqERKcS2_>: + 10022b8: 20c00007 ldb r3,0(r4) + 10022bc: 28800007 ldb r2,0(r5) + 10022c0: 1885003a cmpeq r2,r3,r2 + 10022c4: f800283a ret + +010022c8 <_ZNKSs7_M_dataEv>: + 10022c8: 20800017 ldw r2,0(r4) + 10022cc: f800283a ret + +010022d0 <_ZNSs7_M_dataEPc>: + 10022d0: 2805883a mov r2,r5 + 10022d4: 21400015 stw r5,0(r4) + 10022d8: f800283a ret + +010022dc <_ZNKSs6_M_repEv>: + 10022dc: 20800017 ldw r2,0(r4) + 10022e0: 10bffd04 addi r2,r2,-12 + 10022e4: f800283a ret + +010022e8 <_ZNKSs9_M_ibeginEv>: + 10022e8: 20800017 ldw r2,0(r4) + 10022ec: f800283a ret + +010022f0 <_ZNKSs7_M_iendEv>: + 10022f0: 20c00017 ldw r3,0(r4) + 10022f4: 18bffd17 ldw r2,-12(r3) + 10022f8: 1885883a add r2,r3,r2 + 10022fc: f800283a ret + +01002300 <_ZNKSs8_M_limitEmm>: + 1002300: 20c00017 ldw r3,0(r4) + 1002304: 18bffd17 ldw r2,-12(r3) + 1002308: 1145c83a sub r2,r2,r5 + 100230c: 3080012e bgeu r6,r2,1002314 <_ZNKSs8_M_limitEmm+0x14> + 1002310: 3005883a mov r2,r6 + 1002314: f800283a ret + +01002318 <_ZNKSs11_M_disjunctEPKc>: + 1002318: 21000017 ldw r4,0(r4) + 100231c: 00800044 movi r2,1 + 1002320: 29000336 bltu r5,r4,1002330 <_ZNKSs11_M_disjunctEPKc+0x18> + 1002324: 20bffd17 ldw r2,-12(r4) + 1002328: 2085883a add r2,r4,r2 + 100232c: 1145803a cmpltu r2,r2,r5 + 1002330: f800283a ret + +01002334 <_ZNSs12_S_empty_repEv>: + 1002334: 008040f4 movhi r2,259 + 1002338: 10a52f04 addi r2,r2,-27460 + 100233c: f800283a ret + +01002340 <_ZNSsC1Ev>: + 1002340: 008040f4 movhi r2,259 + 1002344: 10a53204 addi r2,r2,-27448 + 1002348: 20800015 stw r2,0(r4) + 100234c: f800283a ret + +01002350 <_ZNKSs5beginEv>: + 1002350: 20800017 ldw r2,0(r4) + 1002354: f800283a ret + +01002358 <_ZNKSs3endEv>: + 1002358: 20c00017 ldw r3,0(r4) + 100235c: 18bffd17 ldw r2,-12(r3) + 1002360: 1885883a add r2,r3,r2 + 1002364: f800283a ret + +01002368 <_ZNKSs4sizeEv>: + 1002368: 20c00017 ldw r3,0(r4) + 100236c: 18bffd17 ldw r2,-12(r3) + 1002370: f800283a ret + +01002374 <_ZNKSs8max_sizeEv>: + 1002374: 00900034 movhi r2,16384 + 1002378: 10bfff04 addi r2,r2,-4 + 100237c: f800283a ret + +01002380 <_ZNKSs8capacityEv>: + 1002380: 20c00017 ldw r3,0(r4) + 1002384: 18bffe17 ldw r2,-8(r3) + 1002388: f800283a ret + +0100238c <_ZNKSs4dataEv>: + 100238c: 20800017 ldw r2,0(r4) + 1002390: f800283a ret + +01002394 <_ZNKSs13get_allocatorEv>: + 1002394: 2005883a mov r2,r4 + 1002398: f800283a ret + +0100239c <_ZNSs12_Alloc_hiderC1EPcRKSaIcE>: + 100239c: 21400015 stw r5,0(r4) + 10023a0: f800283a ret + +010023a4 <_ZNSs4_Rep12_S_empty_repEv>: + 10023a4: 008040f4 movhi r2,259 + 10023a8: 10a52f04 addi r2,r2,-27460 + 10023ac: f800283a ret + +010023b0 <_ZNKSs4_Rep12_M_is_leakedEv>: + 10023b0: 20800217 ldw r2,8(r4) + 10023b4: 1004d7fa srli r2,r2,31 + 10023b8: f800283a ret + +010023bc <_ZNKSs4_Rep12_M_is_sharedEv>: + 10023bc: 20800217 ldw r2,8(r4) + 10023c0: 0084803a cmplt r2,zero,r2 + 10023c4: f800283a ret + +010023c8 <_ZNSs4_Rep13_M_set_leakedEv>: + 10023c8: 00bfffc4 movi r2,-1 + 10023cc: 20800215 stw r2,8(r4) + 10023d0: f800283a ret + +010023d4 <_ZNSs4_Rep15_M_set_sharableEv>: + 10023d4: 20000215 stw zero,8(r4) + 10023d8: f800283a ret + +010023dc <_ZNSs4_Rep26_M_set_length_and_sharableEm>: + 10023dc: 2145883a add r2,r4,r5 + 10023e0: 20000215 stw zero,8(r4) + 10023e4: 21400015 stw r5,0(r4) + 10023e8: 10000305 stb zero,12(r2) + 10023ec: f800283a ret + +010023f0 <_ZNSs4_Rep10_M_refdataEv>: + 10023f0: 20800304 addi r2,r4,12 + 10023f4: f800283a ret + +010023f8 <_ZSt6searchIPKcS1_PFbRS0_S2_EET_S5_S5_T0_S6_T1_>: + 10023f8: defff504 addi sp,sp,-44 + 10023fc: dd400615 stw r21,24(sp) + 1002400: dd000515 stw r20,20(sp) + 1002404: dcc00415 stw r19,16(sp) + 1002408: dc800315 stw r18,12(sp) + 100240c: dc400215 stw r17,8(sp) + 1002410: dfc00a15 stw ra,40(sp) + 1002414: df000915 stw fp,36(sp) + 1002418: ddc00815 stw r23,32(sp) + 100241c: dd800715 stw r22,28(sp) + 1002420: dc000115 stw r16,4(sp) + 1002424: 2025883a mov r18,r4 + 1002428: 2823883a mov r17,r5 + 100242c: 3027883a mov r19,r6 + 1002430: 382b883a mov r21,r7 + 1002434: dd000b17 ldw r20,44(sp) + 1002438: 21400d26 beq r4,r5,1002470 <_ZSt6searchIPKcS1_PFbRS0_S2_EET_S5_S5_T0_S6_T1_+0x78> + 100243c: 31c00c26 beq r6,r7,1002470 <_ZSt6searchIPKcS1_PFbRS0_S2_EET_S5_S5_T0_S6_T1_+0x78> + 1002440: 30800044 addi r2,r6,1 + 1002444: d8800015 stw r2,0(sp) + 1002448: 38803226 beq r7,r2,1002514 <_ZSt6searchIPKcS1_PFbRS0_S2_EET_S5_S5_T0_S6_T1_+0x11c> + 100244c: 9021883a mov r16,r18 + 1002450: 8009883a mov r4,r16 + 1002454: 980b883a mov r5,r19 + 1002458: a03ee83a callr r20 + 100245c: 10803fcc andi r2,r2,255 + 1002460: 1000101e bne r2,zero,10024a4 <_ZSt6searchIPKcS1_PFbRS0_S2_EET_S5_S5_T0_S6_T1_+0xac> + 1002464: 84000044 addi r16,r16,1 + 1002468: 847ff91e bne r16,r17,1002450 <_ZSt6searchIPKcS1_PFbRS0_S2_EET_S5_S5_T0_S6_T1_+0x58> + 100246c: 8825883a mov r18,r17 + 1002470: 9005883a mov r2,r18 + 1002474: dfc00a17 ldw ra,40(sp) + 1002478: df000917 ldw fp,36(sp) + 100247c: ddc00817 ldw r23,32(sp) + 1002480: dd800717 ldw r22,28(sp) + 1002484: dd400617 ldw r21,24(sp) + 1002488: dd000517 ldw r20,20(sp) + 100248c: dcc00417 ldw r19,16(sp) + 1002490: dc800317 ldw r18,12(sp) + 1002494: dc400217 ldw r17,8(sp) + 1002498: dc000117 ldw r16,4(sp) + 100249c: dec00b04 addi sp,sp,44 + 10024a0: f800283a ret + 10024a4: 8c3ff126 beq r17,r16,100246c <_ZSt6searchIPKcS1_PFbRS0_S2_EET_S5_S5_T0_S6_T1_+0x74> + 10024a8: 8825883a mov r18,r17 + 10024ac: 00000206 br 10024b8 <_ZSt6searchIPKcS1_PFbRS0_S2_EET_S5_S5_T0_S6_T1_+0xc0> + 10024b0: 84000044 addi r16,r16,1 + 10024b4: 84bfed26 beq r16,r18,100246c <_ZSt6searchIPKcS1_PFbRS0_S2_EET_S5_S5_T0_S6_T1_+0x74> + 10024b8: 8009883a mov r4,r16 + 10024bc: 980b883a mov r5,r19 + 10024c0: a03ee83a callr r20 + 10024c4: 10803fcc andi r2,r2,255 + 10024c8: 103ff926 beq r2,zero,10024b0 <_ZSt6searchIPKcS1_PFbRS0_S2_EET_S5_S5_T0_S6_T1_+0xb8> + 10024cc: 87000044 addi fp,r16,1 + 10024d0: 8f001a26 beq r17,fp,100253c <_ZSt6searchIPKcS1_PFbRS0_S2_EET_S5_S5_T0_S6_T1_+0x144> + 10024d4: dd800017 ldw r22,0(sp) + 10024d8: e02f883a mov r23,fp + 10024dc: b809883a mov r4,r23 + 10024e0: b00b883a mov r5,r22 + 10024e4: a03ee83a callr r20 + 10024e8: 8c07c83a sub r3,r17,r16 + 10024ec: 10803fcc andi r2,r2,255 + 10024f0: 98c7883a add r3,r19,r3 + 10024f4: b5800044 addi r22,r22,1 + 10024f8: bdc00044 addi r23,r23,1 + 10024fc: e025883a mov r18,fp + 1002500: 103fd226 beq r2,zero,100244c <_ZSt6searchIPKcS1_PFbRS0_S2_EET_S5_S5_T0_S6_T1_+0x54> + 1002504: ad800b26 beq r21,r22,1002534 <_ZSt6searchIPKcS1_PFbRS0_S2_EET_S5_S5_T0_S6_T1_+0x13c> + 1002508: b0fff41e bne r22,r3,10024dc <_ZSt6searchIPKcS1_PFbRS0_S2_EET_S5_S5_T0_S6_T1_+0xe4> + 100250c: b825883a mov r18,r23 + 1002510: 003fd706 br 1002470 <_ZSt6searchIPKcS1_PFbRS0_S2_EET_S5_S5_T0_S6_T1_+0x78> + 1002514: 2021883a mov r16,r4 + 1002518: 8009883a mov r4,r16 + 100251c: 980b883a mov r5,r19 + 1002520: a03ee83a callr r20 + 1002524: 10803fcc andi r2,r2,255 + 1002528: 1000021e bne r2,zero,1002534 <_ZSt6searchIPKcS1_PFbRS0_S2_EET_S5_S5_T0_S6_T1_+0x13c> + 100252c: 84000044 addi r16,r16,1 + 1002530: 8c3ff91e bne r17,r16,1002518 <_ZSt6searchIPKcS1_PFbRS0_S2_EET_S5_S5_T0_S6_T1_+0x120> + 1002534: 8025883a mov r18,r16 + 1002538: 003fcd06 br 1002470 <_ZSt6searchIPKcS1_PFbRS0_S2_EET_S5_S5_T0_S6_T1_+0x78> + 100253c: e025883a mov r18,fp + 1002540: 003fcb06 br 1002470 <_ZSt6searchIPKcS1_PFbRS0_S2_EET_S5_S5_T0_S6_T1_+0x78> + +01002544 <_ZN9__gnu_cxxeqIPcSsEEbRKNS_17__normal_iteratorIT_T0_EES7_>: + 1002544: 20c00017 ldw r3,0(r4) + 1002548: 28800017 ldw r2,0(r5) + 100254c: 1885003a cmpeq r2,r3,r2 + 1002550: f800283a ret + +01002554 <_ZNSs12_Alloc_hiderC2EPcRKSaIcE>: + 1002554: 21400015 stw r5,0(r4) + 1002558: f800283a ret + +0100255c <_ZNSs4_Rep10_M_refcopyEv>: + 100255c: deffee04 addi sp,sp,-72 + 1002560: 00804034 movhi r2,256 + 1002564: 109a9704 addi r2,r2,27228 + 1002568: 00c040b4 movhi r3,258 + 100256c: 18c2d004 addi r3,r3,2880 + 1002570: d8800615 stw r2,24(sp) + 1002574: d9000d15 stw r4,52(sp) + 1002578: 00804034 movhi r2,256 + 100257c: 10897d04 addi r2,r2,9716 + 1002580: d809883a mov r4,sp + 1002584: d8c00715 stw r3,28(sp) + 1002588: d8800915 stw r2,36(sp) + 100258c: dfc01115 stw ra,68(sp) + 1002590: df001015 stw fp,64(sp) + 1002594: ddc00f15 stw r23,60(sp) + 1002598: dec00815 stw sp,32(sp) + 100259c: dec00a15 stw sp,40(sp) + 10025a0: 1009c1c0 call 1009c1c <_Unwind_SjLj_Register> + 10025a4: d8c00d17 ldw r3,52(sp) + 10025a8: 008040f4 movhi r2,259 + 10025ac: 10a52f04 addi r2,r2,-27460 + 10025b0: 18800b1e bne r3,r2,10025e0 <_ZNSs4_Rep10_M_refcopyEv+0x84> + 10025b4: d8800d17 ldw r2,52(sp) + 10025b8: d809883a mov r4,sp + 10025bc: 10800304 addi r2,r2,12 + 10025c0: d8800e15 stw r2,56(sp) + 10025c4: 1009c2c0 call 1009c2c <_Unwind_SjLj_Unregister> + 10025c8: d8800e17 ldw r2,56(sp) + 10025cc: dfc01117 ldw ra,68(sp) + 10025d0: df001017 ldw fp,64(sp) + 10025d4: ddc00f17 ldw r23,60(sp) + 10025d8: dec01204 addi sp,sp,72 + 10025dc: f800283a ret + 10025e0: 01400044 movi r5,1 + 10025e4: d9400115 stw r5,4(sp) + 10025e8: 19000204 addi r4,r3,8 + 10025ec: 10061900 call 1006190 <_ZN9__gnu_cxx12__atomic_addEPVii> + 10025f0: 003ff006 br 10025b4 <_ZNSs4_Rep10_M_refcopyEv+0x58> + 10025f4: d8800317 ldw r2,12(sp) + 10025f8: 00ffffc4 movi r3,-1 + 10025fc: d9000217 ldw r4,8(sp) + 1002600: 10c00226 beq r2,r3,100260c <_ZNSs4_Rep10_M_refcopyEv+0xb0> + 1002604: d8c00115 stw r3,4(sp) + 1002608: 1009ee80 call 1009ee8 <_Unwind_SjLj_Resume> + 100260c: 00bfffc4 movi r2,-1 + 1002610: d8800115 stw r2,4(sp) + 1002614: 10068dc0 call 10068dc <__cxa_call_unexpected> + +01002618 <_ZNKSs15_M_check_lengthEmmPKc>: + 1002618: 20800017 ldw r2,0(r4) + 100261c: deffff04 addi sp,sp,-4 + 1002620: dfc00015 stw ra,0(sp) + 1002624: 10fffd17 ldw r3,-12(r2) + 1002628: 00900034 movhi r2,16384 + 100262c: 10bfff04 addi r2,r2,-4 + 1002630: 1947c83a sub r3,r3,r5 + 1002634: 10c5c83a sub r2,r2,r3 + 1002638: 11800336 bltu r2,r6,1002648 <_ZNKSs15_M_check_lengthEmmPKc+0x30> + 100263c: dfc00017 ldw ra,0(sp) + 1002640: dec00104 addi sp,sp,4 + 1002644: f800283a ret + 1002648: 3809883a mov r4,r7 + 100264c: 100866c0 call 100866c <_ZSt20__throw_length_errorPKc> + +01002650 <_ZNKSs8_M_checkEmPKc>: + 1002650: 20c00017 ldw r3,0(r4) + 1002654: deffff04 addi sp,sp,-4 + 1002658: dfc00015 stw ra,0(sp) + 100265c: 18bffd17 ldw r2,-12(r3) + 1002660: 11400436 bltu r2,r5,1002674 <_ZNKSs8_M_checkEmPKc+0x24> + 1002664: 2805883a mov r2,r5 + 1002668: dfc00017 ldw ra,0(sp) + 100266c: dec00104 addi sp,sp,4 + 1002670: f800283a ret + 1002674: 3009883a mov r4,r6 + 1002678: 10084dc0 call 10084dc <_ZSt20__throw_out_of_rangePKc> + +0100267c <_ZNSs9_M_assignEPcmc>: + 100267c: 3011883a mov r8,r6 + 1002680: 2807883a mov r3,r5 + 1002684: 280d883a mov r6,r5 + 1002688: 41403fcc andi r5,r8,255 + 100268c: 2940201c xori r5,r5,128 + 1002690: 01c00044 movi r7,1 + 1002694: 297fe004 addi r5,r5,-128 + 1002698: 19c00126 beq r3,r7,10026a0 <_ZNSs9_M_assignEPcmc+0x24> + 100269c: 100abbc1 jmpi 100abbc + 10026a0: 22000005 stb r8,0(r4) + 10026a4: f800283a ret + +010026a8 <_ZNSs7_M_moveEPcPKcm>: + 10026a8: 00800044 movi r2,1 + 10026ac: 30800126 beq r6,r2,10026b4 <_ZNSs7_M_moveEPcPKcm+0xc> + 10026b0: 100aadc1 jmpi 100aadc + 10026b4: 28800003 ldbu r2,0(r5) + 10026b8: 20800005 stb r2,0(r4) + 10026bc: f800283a ret + +010026c0 <_ZNSs7_M_copyEPcPKcm>: + 10026c0: 00800044 movi r2,1 + 10026c4: 30800126 beq r6,r2,10026cc <_ZNSs7_M_copyEPcPKcm+0xc> + 10026c8: 100aa3c1 jmpi 100aa3c + 10026cc: 28800003 ldbu r2,0(r5) + 10026d0: 20800005 stb r2,0(r4) + 10026d4: f800283a ret + +010026d8 <_ZNKSs5c_strEv>: + 10026d8: 20800017 ldw r2,0(r4) + 10026dc: f800283a ret + +010026e0 <_ZNKSsixEm>: + 10026e0: 20800017 ldw r2,0(r4) + 10026e4: 2885883a add r2,r5,r2 + 10026e8: f800283a ret + +010026ec <_ZNKSs17find_first_not_ofEPKcmm>: + 10026ec: 20c00017 ldw r3,0(r4) + 10026f0: defffb04 addi sp,sp,-20 + 10026f4: dcc00315 stw r19,12(sp) + 10026f8: 18bffd17 ldw r2,-12(r3) + 10026fc: dc800215 stw r18,8(sp) + 1002700: dc400115 stw r17,4(sp) + 1002704: dc000015 stw r16,0(sp) + 1002708: dfc00415 stw ra,16(sp) + 100270c: 2027883a mov r19,r4 + 1002710: 3021883a mov r16,r6 + 1002714: 2825883a mov r18,r5 + 1002718: 3823883a mov r17,r7 + 100271c: 30800536 bltu r6,r2,1002734 <_ZNKSs17find_first_not_ofEPKcmm+0x48> + 1002720: 00001206 br 100276c <_ZNKSs17find_first_not_ofEPKcmm+0x80> + 1002724: 98c00017 ldw r3,0(r19) + 1002728: 84000044 addi r16,r16,1 + 100272c: 18bffd17 ldw r2,-12(r3) + 1002730: 80800e2e bgeu r16,r2,100276c <_ZNKSs17find_first_not_ofEPKcmm+0x80> + 1002734: 1c05883a add r2,r3,r16 + 1002738: 11400007 ldb r5,0(r2) + 100273c: 9009883a mov r4,r18 + 1002740: 880d883a mov r6,r17 + 1002744: 100a8e40 call 100a8e4 + 1002748: 103ff61e bne r2,zero,1002724 <_ZNKSs17find_first_not_ofEPKcmm+0x38> + 100274c: 8005883a mov r2,r16 + 1002750: dfc00417 ldw ra,16(sp) + 1002754: dcc00317 ldw r19,12(sp) + 1002758: dc800217 ldw r18,8(sp) + 100275c: dc400117 ldw r17,4(sp) + 1002760: dc000017 ldw r16,0(sp) + 1002764: dec00504 addi sp,sp,20 + 1002768: f800283a ret + 100276c: 043fffc4 movi r16,-1 + 1002770: 8005883a mov r2,r16 + 1002774: dfc00417 ldw ra,16(sp) + 1002778: dcc00317 ldw r19,12(sp) + 100277c: dc800217 ldw r18,8(sp) + 1002780: dc400117 ldw r17,4(sp) + 1002784: dc000017 ldw r16,0(sp) + 1002788: dec00504 addi sp,sp,20 + 100278c: f800283a ret + +01002790 <_ZNKSs4findEPKcmm>: + 1002790: defffb04 addi sp,sp,-20 + 1002794: dc000115 stw r16,4(sp) + 1002798: 24000017 ldw r16,0(r4) + 100279c: 31c7883a add r3,r6,r7 + 10027a0: dc800315 stw r18,12(sp) + 10027a4: 823ffd17 ldw r8,-12(r16) + 10027a8: 8189883a add r4,r16,r6 + 10027ac: 280d883a mov r6,r5 + 10027b0: 8225883a add r18,r16,r8 + 10027b4: dc400215 stw r17,8(sp) + 10027b8: dfc00415 stw ra,16(sp) + 10027bc: 3823883a mov r17,r7 + 10027c0: 900b883a mov r5,r18 + 10027c4: 398f883a add r7,r7,r6 + 10027c8: 40c0082e bgeu r8,r3,10027ec <_ZNKSs4findEPKcmm+0x5c> + 10027cc: 00ffffc4 movi r3,-1 + 10027d0: 1805883a mov r2,r3 + 10027d4: dfc00417 ldw ra,16(sp) + 10027d8: dc800317 ldw r18,12(sp) + 10027dc: dc400217 ldw r17,8(sp) + 10027e0: dc000117 ldw r16,4(sp) + 10027e4: dec00504 addi sp,sp,20 + 10027e8: f800283a ret + 10027ec: 00804034 movhi r2,256 + 10027f0: 1088ae04 addi r2,r2,8888 + 10027f4: d8800015 stw r2,0(sp) + 10027f8: 10023f80 call 10023f8 <_ZSt6searchIPKcS1_PFbRS0_S2_EET_S5_S5_T0_S6_T1_> + 10027fc: 1407c83a sub r3,r2,r16 + 1002800: 90bff31e bne r18,r2,10027d0 <_ZNKSs4findEPKcmm+0x40> + 1002804: 883ff11e bne r17,zero,10027cc <_ZNKSs4findEPKcmm+0x3c> + 1002808: 1805883a mov r2,r3 + 100280c: dfc00417 ldw ra,16(sp) + 1002810: dc800317 ldw r18,12(sp) + 1002814: dc400217 ldw r17,8(sp) + 1002818: dc000117 ldw r16,4(sp) + 100281c: dec00504 addi sp,sp,20 + 1002820: f800283a ret + +01002824 <_ZNKSs2atEm>: + 1002824: 21000017 ldw r4,0(r4) + 1002828: deffff04 addi sp,sp,-4 + 100282c: dfc00015 stw ra,0(sp) + 1002830: 20bffd17 ldw r2,-12(r4) + 1002834: 2880042e bgeu r5,r2,1002848 <_ZNKSs2atEm+0x24> + 1002838: 2145883a add r2,r4,r5 + 100283c: dfc00017 ldw ra,0(sp) + 1002840: dec00104 addi sp,sp,4 + 1002844: f800283a ret + 1002848: 010040b4 movhi r4,258 + 100284c: 2103df04 addi r4,r4,3964 + 1002850: 10084dc0 call 10084dc <_ZSt20__throw_out_of_rangePKc> + +01002854 <_ZNKSs5emptyEv>: + 1002854: 20c00017 ldw r3,0(r4) + 1002858: 18bffd17 ldw r2,-12(r3) + 100285c: 1005003a cmpeq r2,r2,zero + 1002860: f800283a ret + +01002864 <_ZNKSs6lengthEv>: + 1002864: 20c00017 ldw r3,0(r4) + 1002868: 18bffd17 ldw r2,-12(r3) + 100286c: f800283a ret + +01002870 <_ZNKSs4findERKSsm>: + 1002870: 29400017 ldw r5,0(r5) + 1002874: 29fffd17 ldw r7,-12(r5) + 1002878: 10027901 jmpi 1002790 <_ZNKSs4findEPKcmm> + +0100287c <_ZNKSs17find_first_not_ofERKSsm>: + 100287c: 29400017 ldw r5,0(r5) + 1002880: 29fffd17 ldw r7,-12(r5) + 1002884: 10026ec1 jmpi 10026ec <_ZNKSs17find_first_not_ofEPKcmm> + +01002888 <_ZNKSs5rfindEPKcmm>: + 1002888: defff804 addi sp,sp,-32 + 100288c: dc800415 stw r18,16(sp) + 1002890: 24800017 ldw r18,0(r4) + 1002894: dcc00515 stw r19,20(sp) + 1002898: dc400315 stw r17,12(sp) + 100289c: 90bffd17 ldw r2,-12(r18) + 10028a0: dfc00715 stw ra,28(sp) + 10028a4: dd000615 stw r20,24(sp) + 10028a8: dc000215 stw r16,8(sp) + 10028ac: 3823883a mov r17,r7 + 10028b0: 2827883a mov r19,r5 + 10028b4: d9800115 stw r6,4(sp) + 10028b8: 11c01136 bltu r2,r7,1002900 <_ZNKSs5rfindEPKcmm+0x78> + 10028bc: 11c5c83a sub r2,r2,r7 + 10028c0: d8800015 stw r2,0(sp) + 10028c4: 3080182e bgeu r6,r2,1002928 <_ZNKSs5rfindEPKcmm+0xa0> + 10028c8: d8800104 addi r2,sp,4 + 10028cc: 10800017 ldw r2,0(r2) + 10028d0: 053fffc4 movi r20,-1 + 10028d4: d8800115 stw r2,4(sp) + 10028d8: 00000106 br 10028e0 <_ZNKSs5rfindEPKcmm+0x58> + 10028dc: d8c00115 stw r3,4(sp) + 10028e0: dc000117 ldw r16,4(sp) + 10028e4: 980b883a mov r5,r19 + 10028e8: 880d883a mov r6,r17 + 10028ec: 9409883a add r4,r18,r16 + 10028f0: 100a9c80 call 100a9c8 + 10028f4: 80ffffc4 addi r3,r16,-1 + 10028f8: 10000226 beq r2,zero,1002904 <_ZNKSs5rfindEPKcmm+0x7c> + 10028fc: 1d3ff71e bne r3,r20,10028dc <_ZNKSs5rfindEPKcmm+0x54> + 1002900: 043fffc4 movi r16,-1 + 1002904: 8005883a mov r2,r16 + 1002908: dfc00717 ldw ra,28(sp) + 100290c: dd000617 ldw r20,24(sp) + 1002910: dcc00517 ldw r19,20(sp) + 1002914: dc800417 ldw r18,16(sp) + 1002918: dc400317 ldw r17,12(sp) + 100291c: dc000217 ldw r16,8(sp) + 1002920: dec00804 addi sp,sp,32 + 1002924: f800283a ret + 1002928: d805883a mov r2,sp + 100292c: 003fe706 br 10028cc <_ZNKSs5rfindEPKcmm+0x44> + +01002930 <_ZNKSs5rfindEPKcm>: + 1002930: defffc04 addi sp,sp,-16 + 1002934: dd400215 stw r21,8(sp) + 1002938: dcc00115 stw r19,4(sp) + 100293c: dc400015 stw r17,0(sp) + 1002940: 2027883a mov r19,r4 + 1002944: dfc00315 stw ra,12(sp) + 1002948: 2809883a mov r4,r5 + 100294c: 2823883a mov r17,r5 + 1002950: 302b883a mov r21,r6 + 1002954: 100b1640 call 100b164 + 1002958: 880b883a mov r5,r17 + 100295c: 9809883a mov r4,r19 + 1002960: a80d883a mov r6,r21 + 1002964: 100f883a mov r7,r2 + 1002968: dfc00317 ldw ra,12(sp) + 100296c: dd400217 ldw r21,8(sp) + 1002970: dcc00117 ldw r19,4(sp) + 1002974: dc400017 ldw r17,0(sp) + 1002978: dec00404 addi sp,sp,16 + 100297c: 10028881 jmpi 1002888 <_ZNKSs5rfindEPKcmm> + +01002980 <_ZNKSs5rfindERKSsm>: + 1002980: 29400017 ldw r5,0(r5) + 1002984: 29fffd17 ldw r7,-12(r5) + 1002988: 10028881 jmpi 1002888 <_ZNKSs5rfindEPKcmm> + +0100298c <_ZNSsC2Ev>: + 100298c: 008040f4 movhi r2,259 + 1002990: 10a53204 addi r2,r2,-27448 + 1002994: 20800015 stw r2,0(r4) + 1002998: f800283a ret + +0100299c <_ZN9__gnu_cxxeqIPKcSsEEbRKNS_17__normal_iteratorIT_T0_EES8_>: + 100299c: 20c00017 ldw r3,0(r4) + 10029a0: 28800017 ldw r2,0(r5) + 10029a4: 1885003a cmpeq r2,r3,r2 + 10029a8: f800283a ret + +010029ac <_ZNKSs5rfindEcm>: + 10029ac: 21000017 ldw r4,0(r4) + 10029b0: 3007883a mov r3,r6 + 10029b4: 20bffd17 ldw r2,-12(r4) + 10029b8: 10001226 beq r2,zero,1002a04 <_ZNKSs5rfindEcm+0x58> + 10029bc: 11bfffc4 addi r6,r2,-1 + 10029c0: 19800e36 bltu r3,r6,10029fc <_ZNKSs5rfindEcm+0x50> + 10029c4: 29403fcc andi r5,r5,255 + 10029c8: 2940201c xori r5,r5,128 + 10029cc: 2189883a add r4,r4,r6 + 10029d0: 297fe004 addi r5,r5,-128 + 10029d4: 0007883a mov r3,zero + 10029d8: 32000044 addi r8,r6,1 + 10029dc: 30cfc83a sub r7,r6,r3 + 10029e0: 40c00826 beq r8,r3,1002a04 <_ZNKSs5rfindEcm+0x58> + 10029e4: 20800007 ldb r2,0(r4) + 10029e8: 18c00044 addi r3,r3,1 + 10029ec: 213fffc4 addi r4,r4,-1 + 10029f0: 117ffa1e bne r2,r5,10029dc <_ZNKSs5rfindEcm+0x30> + 10029f4: 3805883a mov r2,r7 + 10029f8: f800283a ret + 10029fc: 180d883a mov r6,r3 + 1002a00: 003ff006 br 10029c4 <_ZNKSs5rfindEcm+0x18> + 1002a04: 01ffffc4 movi r7,-1 + 1002a08: 3805883a mov r2,r7 + 1002a0c: f800283a ret + +01002a10 <_ZNKSs12find_last_ofEcm>: + 1002a10: 29403fcc andi r5,r5,255 + 1002a14: 2940201c xori r5,r5,128 + 1002a18: 297fe004 addi r5,r5,-128 + 1002a1c: 10029ac1 jmpi 10029ac <_ZNKSs5rfindEcm> + +01002a20 <_ZNKSs16find_last_not_ofEcm>: + 1002a20: 21000017 ldw r4,0(r4) + 1002a24: 20bffd17 ldw r2,-12(r4) + 1002a28: 10001026 beq r2,zero,1002a6c <_ZNKSs16find_last_not_ofEcm+0x4c> + 1002a2c: 10ffffc4 addi r3,r2,-1 + 1002a30: 30c00c36 bltu r6,r3,1002a64 <_ZNKSs16find_last_not_ofEcm+0x44> + 1002a34: 29403fcc andi r5,r5,255 + 1002a38: 2940201c xori r5,r5,128 + 1002a3c: 20c9883a add r4,r4,r3 + 1002a40: 297fe004 addi r5,r5,-128 + 1002a44: 01bfffc4 movi r6,-1 + 1002a48: 20800007 ldb r2,0(r4) + 1002a4c: 213fffc4 addi r4,r4,-1 + 1002a50: 1140021e bne r2,r5,1002a5c <_ZNKSs16find_last_not_ofEcm+0x3c> + 1002a54: 18ffffc4 addi r3,r3,-1 + 1002a58: 19bffb1e bne r3,r6,1002a48 <_ZNKSs16find_last_not_ofEcm+0x28> + 1002a5c: 1805883a mov r2,r3 + 1002a60: f800283a ret + 1002a64: 3007883a mov r3,r6 + 1002a68: 003ff206 br 1002a34 <_ZNKSs16find_last_not_ofEcm+0x14> + 1002a6c: 00ffffc4 movi r3,-1 + 1002a70: 1805883a mov r2,r3 + 1002a74: f800283a ret + +01002a78 <_ZNKSs17find_first_not_ofEcm>: + 1002a78: 21000017 ldw r4,0(r4) + 1002a7c: 3007883a mov r3,r6 + 1002a80: 21bffd17 ldw r6,-12(r4) + 1002a84: 19800f2e bgeu r3,r6,1002ac4 <_ZNKSs17find_first_not_ofEcm+0x4c> + 1002a88: 20c9883a add r4,r4,r3 + 1002a8c: 29403fcc andi r5,r5,255 + 1002a90: 20800007 ldb r2,0(r4) + 1002a94: 2940201c xori r5,r5,128 + 1002a98: 297fe004 addi r5,r5,-128 + 1002a9c: 28800a1e bne r5,r2,1002ac8 <_ZNKSs17find_first_not_ofEcm+0x50> + 1002aa0: 30cfc83a sub r7,r6,r3 + 1002aa4: 180d883a mov r6,r3 + 1002aa8: 00000306 br 1002ab8 <_ZNKSs17find_first_not_ofEcm+0x40> + 1002aac: 20800047 ldb r2,1(r4) + 1002ab0: 21000044 addi r4,r4,1 + 1002ab4: 1140061e bne r2,r5,1002ad0 <_ZNKSs17find_first_not_ofEcm+0x58> + 1002ab8: 31800044 addi r6,r6,1 + 1002abc: 19c5883a add r2,r3,r7 + 1002ac0: 11bffa1e bne r2,r6,1002aac <_ZNKSs17find_first_not_ofEcm+0x34> + 1002ac4: 00ffffc4 movi r3,-1 + 1002ac8: 1805883a mov r2,r3 + 1002acc: f800283a ret + 1002ad0: 3007883a mov r3,r6 + 1002ad4: 1805883a mov r2,r3 + 1002ad8: f800283a ret + +01002adc <_ZNSs4_Rep9_S_createEmmRKSaIcE>: + 1002adc: deffed04 addi sp,sp,-76 + 1002ae0: 00804034 movhi r2,256 + 1002ae4: 109a9704 addi r2,r2,27228 + 1002ae8: 00c040b4 movhi r3,258 + 1002aec: 18c2d344 addi r3,r3,2893 + 1002af0: d8800615 stw r2,24(sp) + 1002af4: d9000e15 stw r4,56(sp) + 1002af8: 00804034 movhi r2,256 + 1002afc: 108aff04 addi r2,r2,11260 + 1002b00: d809883a mov r4,sp + 1002b04: d8c00715 stw r3,28(sp) + 1002b08: d8800915 stw r2,36(sp) + 1002b0c: dfc01215 stw ra,72(sp) + 1002b10: df001115 stw fp,68(sp) + 1002b14: ddc01015 stw r23,64(sp) + 1002b18: dec00815 stw sp,32(sp) + 1002b1c: dec00a15 stw sp,40(sp) + 1002b20: d9400f15 stw r5,60(sp) + 1002b24: 1009c1c0 call 1009c1c <_Unwind_SjLj_Register> + 1002b28: d8c00e17 ldw r3,56(sp) + 1002b2c: 00900034 movhi r2,16384 + 1002b30: 10bfff04 addi r2,r2,-4 + 1002b34: 10c02c36 bltu r2,r3,1002be8 <_ZNSs4_Rep9_S_createEmmRKSaIcE+0x10c> + 1002b38: d9800f17 ldw r6,60(sp) + 1002b3c: d9c00e17 ldw r7,56(sp) + 1002b40: 31c0032e bgeu r6,r7,1002b50 <_ZNSs4_Rep9_S_createEmmRKSaIcE+0x74> + 1002b44: 3189883a add r4,r6,r6 + 1002b48: 3900012e bgeu r7,r4,1002b50 <_ZNSs4_Rep9_S_createEmmRKSaIcE+0x74> + 1002b4c: d9000e15 stw r4,56(sp) + 1002b50: d8800e17 ldw r2,56(sp) + 1002b54: 01400344 movi r5,13 + 1002b58: 00c40004 movi r3,4096 + 1002b5c: 1149883a add r4,r2,r5 + 1002b60: 20800404 addi r2,r4,16 + 1002b64: 18800f36 bltu r3,r2,1002ba4 <_ZNSs4_Rep9_S_createEmmRKSaIcE+0xc8> + 1002b68: 00800044 movi r2,1 + 1002b6c: d8800115 stw r2,4(sp) + 1002b70: 10077140 call 1007714 <_Znwm> + 1002b74: d8c00e17 ldw r3,56(sp) + 1002b78: 10000215 stw zero,8(r2) + 1002b7c: d809883a mov r4,sp + 1002b80: 10c00115 stw r3,4(r2) + 1002b84: d8800d15 stw r2,52(sp) + 1002b88: 1009c2c0 call 1009c2c <_Unwind_SjLj_Unregister> + 1002b8c: d8800d17 ldw r2,52(sp) + 1002b90: dfc01217 ldw ra,72(sp) + 1002b94: df001117 ldw fp,68(sp) + 1002b98: ddc01017 ldw r23,64(sp) + 1002b9c: dec01304 addi sp,sp,76 + 1002ba0: f800283a ret + 1002ba4: d9800f17 ldw r6,60(sp) + 1002ba8: d9c00e17 ldw r7,56(sp) + 1002bac: 31ffee2e bgeu r6,r7,1002b68 <_ZNSs4_Rep9_S_createEmmRKSaIcE+0x8c> + 1002bb0: 1083ffcc andi r2,r2,4095 + 1002bb4: 1885c83a sub r2,r3,r2 + 1002bb8: 388f883a add r7,r7,r2 + 1002bbc: 01100034 movhi r4,16384 + 1002bc0: 213fff04 addi r4,r4,-4 + 1002bc4: d9c00e15 stw r7,56(sp) + 1002bc8: 21c00336 bltu r4,r7,1002bd8 <_ZNSs4_Rep9_S_createEmmRKSaIcE+0xfc> + 1002bcc: d8800e17 ldw r2,56(sp) + 1002bd0: 1149883a add r4,r2,r5 + 1002bd4: 003fe406 br 1002b68 <_ZNSs4_Rep9_S_createEmmRKSaIcE+0x8c> + 1002bd8: d9000e15 stw r4,56(sp) + 1002bdc: d8800e17 ldw r2,56(sp) + 1002be0: 1149883a add r4,r2,r5 + 1002be4: 003fe006 br 1002b68 <_ZNSs4_Rep9_S_createEmmRKSaIcE+0x8c> + 1002be8: 00bfffc4 movi r2,-1 + 1002bec: 010040b4 movhi r4,258 + 1002bf0: 2103e404 addi r4,r4,3984 + 1002bf4: d8800115 stw r2,4(sp) + 1002bf8: 100866c0 call 100866c <_ZSt20__throw_length_errorPKc> + 1002bfc: d9000217 ldw r4,8(sp) + 1002c00: 00bfffc4 movi r2,-1 + 1002c04: d8800115 stw r2,4(sp) + 1002c08: 1009ee80 call 1009ee8 <_Unwind_SjLj_Resume> + +01002c0c <_ZNSs4_Rep10_M_destroyERKSaIcE>: + 1002c0c: 100722c1 jmpi 100722c <_ZdlPv> + +01002c10 <_ZNSs4_Rep10_M_disposeERKSaIcE>: + 1002c10: defffd04 addi sp,sp,-12 + 1002c14: dc000015 stw r16,0(sp) + 1002c18: 008040f4 movhi r2,259 + 1002c1c: 10a52f04 addi r2,r2,-27460 + 1002c20: 2021883a mov r16,r4 + 1002c24: dc400115 stw r17,4(sp) + 1002c28: dfc00215 stw ra,8(sp) + 1002c2c: 2823883a mov r17,r5 + 1002c30: 21000204 addi r4,r4,8 + 1002c34: 017fffc4 movi r5,-1 + 1002c38: 8080051e bne r16,r2,1002c50 <_ZNSs4_Rep10_M_disposeERKSaIcE+0x40> + 1002c3c: dfc00217 ldw ra,8(sp) + 1002c40: dc400117 ldw r17,4(sp) + 1002c44: dc000017 ldw r16,0(sp) + 1002c48: dec00304 addi sp,sp,12 + 1002c4c: f800283a ret + 1002c50: 100617c0 call 100617c <_ZN9__gnu_cxx18__exchange_and_addEPVii> + 1002c54: 8009883a mov r4,r16 + 1002c58: 880b883a mov r5,r17 + 1002c5c: 00bff716 blt zero,r2,1002c3c <_ZNSs4_Rep10_M_disposeERKSaIcE+0x2c> + 1002c60: dfc00217 ldw ra,8(sp) + 1002c64: dc400117 ldw r17,4(sp) + 1002c68: dc000017 ldw r16,0(sp) + 1002c6c: dec00304 addi sp,sp,12 + 1002c70: 1002c0c1 jmpi 1002c0c <_ZNSs4_Rep10_M_destroyERKSaIcE> + +01002c74 <_ZNKSs12find_last_ofEPKcmm>: + 1002c74: 20800017 ldw r2,0(r4) + 1002c78: defffb04 addi sp,sp,-20 + 1002c7c: dcc00315 stw r19,12(sp) + 1002c80: 10fffd17 ldw r3,-12(r2) + 1002c84: dc800215 stw r18,8(sp) + 1002c88: dc400115 stw r17,4(sp) + 1002c8c: dfc00415 stw ra,16(sp) + 1002c90: dc000015 stw r16,0(sp) + 1002c94: 2027883a mov r19,r4 + 1002c98: 2825883a mov r18,r5 + 1002c9c: 3823883a mov r17,r7 + 1002ca0: 18002426 beq r3,zero,1002d34 <_ZNKSs12find_last_ofEPKcmm+0xc0> + 1002ca4: 38002326 beq r7,zero,1002d34 <_ZNKSs12find_last_ofEPKcmm+0xc0> + 1002ca8: 1c3fffc4 addi r16,r3,-1 + 1002cac: 3400102e bgeu r6,r16,1002cf0 <_ZNKSs12find_last_ofEPKcmm+0x7c> + 1002cb0: 3021883a mov r16,r6 + 1002cb4: 1405883a add r2,r2,r16 + 1002cb8: 11400007 ldb r5,0(r2) + 1002cbc: 9009883a mov r4,r18 + 1002cc0: 880d883a mov r6,r17 + 1002cc4: 100a8e40 call 100a8e4 + 1002cc8: 10000f26 beq r2,zero,1002d08 <_ZNKSs12find_last_ofEPKcmm+0x94> + 1002ccc: 8005883a mov r2,r16 + 1002cd0: dfc00417 ldw ra,16(sp) + 1002cd4: dcc00317 ldw r19,12(sp) + 1002cd8: dc800217 ldw r18,8(sp) + 1002cdc: dc400117 ldw r17,4(sp) + 1002ce0: dc000017 ldw r16,0(sp) + 1002ce4: dec00504 addi sp,sp,20 + 1002ce8: f800283a ret + 1002cec: 98800017 ldw r2,0(r19) + 1002cf0: 1405883a add r2,r2,r16 + 1002cf4: 11400007 ldb r5,0(r2) + 1002cf8: 9009883a mov r4,r18 + 1002cfc: 880d883a mov r6,r17 + 1002d00: 100a8e40 call 100a8e4 + 1002d04: 103ff11e bne r2,zero,1002ccc <_ZNKSs12find_last_ofEPKcmm+0x58> + 1002d08: 843fffc4 addi r16,r16,-1 + 1002d0c: 00bfffc4 movi r2,-1 + 1002d10: 80bff61e bne r16,r2,1002cec <_ZNKSs12find_last_ofEPKcmm+0x78> + 1002d14: 8005883a mov r2,r16 + 1002d18: dfc00417 ldw ra,16(sp) + 1002d1c: dcc00317 ldw r19,12(sp) + 1002d20: dc800217 ldw r18,8(sp) + 1002d24: dc400117 ldw r17,4(sp) + 1002d28: dc000017 ldw r16,0(sp) + 1002d2c: dec00504 addi sp,sp,20 + 1002d30: f800283a ret + 1002d34: 043fffc4 movi r16,-1 + 1002d38: 8005883a mov r2,r16 + 1002d3c: dfc00417 ldw ra,16(sp) + 1002d40: dcc00317 ldw r19,12(sp) + 1002d44: dc800217 ldw r18,8(sp) + 1002d48: dc400117 ldw r17,4(sp) + 1002d4c: dc000017 ldw r16,0(sp) + 1002d50: dec00504 addi sp,sp,20 + 1002d54: f800283a ret + +01002d58 <_ZNKSs12find_last_ofERKSsm>: + 1002d58: 29400017 ldw r5,0(r5) + 1002d5c: 29fffd17 ldw r7,-12(r5) + 1002d60: 1002c741 jmpi 1002c74 <_ZNKSs12find_last_ofEPKcmm> + +01002d64 <_ZNKSs13find_first_ofEPKcmm>: + 1002d64: defffb04 addi sp,sp,-20 + 1002d68: dcc00315 stw r19,12(sp) + 1002d6c: dc800215 stw r18,8(sp) + 1002d70: dc400115 stw r17,4(sp) + 1002d74: dc000015 stw r16,0(sp) + 1002d78: dfc00415 stw ra,16(sp) + 1002d7c: 3823883a mov r17,r7 + 1002d80: 2027883a mov r19,r4 + 1002d84: 2825883a mov r18,r5 + 1002d88: 3021883a mov r16,r6 + 1002d8c: 3800091e bne r7,zero,1002db4 <_ZNKSs13find_first_ofEPKcmm+0x50> + 1002d90: 043fffc4 movi r16,-1 + 1002d94: 8005883a mov r2,r16 + 1002d98: dfc00417 ldw ra,16(sp) + 1002d9c: dcc00317 ldw r19,12(sp) + 1002da0: dc800217 ldw r18,8(sp) + 1002da4: dc400117 ldw r17,4(sp) + 1002da8: dc000017 ldw r16,0(sp) + 1002dac: dec00504 addi sp,sp,20 + 1002db0: f800283a ret + 1002db4: 20c00017 ldw r3,0(r4) + 1002db8: 18bffd17 ldw r2,-12(r3) + 1002dbc: 30bff42e bgeu r6,r2,1002d90 <_ZNKSs13find_first_ofEPKcmm+0x2c> + 1002dc0: 80c5883a add r2,r16,r3 + 1002dc4: 11400007 ldb r5,0(r2) + 1002dc8: 9009883a mov r4,r18 + 1002dcc: 880d883a mov r6,r17 + 1002dd0: 100a8e40 call 100a8e4 + 1002dd4: 103fef1e bne r2,zero,1002d94 <_ZNKSs13find_first_ofEPKcmm+0x30> + 1002dd8: 98c00017 ldw r3,0(r19) + 1002ddc: 84000044 addi r16,r16,1 + 1002de0: 18bffd17 ldw r2,-12(r3) + 1002de4: 80bff636 bltu r16,r2,1002dc0 <_ZNKSs13find_first_ofEPKcmm+0x5c> + 1002de8: 003fe906 br 1002d90 <_ZNKSs13find_first_ofEPKcmm+0x2c> + +01002dec <_ZNKSs13find_first_ofERKSsm>: + 1002dec: 29400017 ldw r5,0(r5) + 1002df0: 29fffd17 ldw r7,-12(r5) + 1002df4: 1002d641 jmpi 1002d64 <_ZNKSs13find_first_ofEPKcmm> + +01002df8 <_ZNKSs4findEcm>: + 1002df8: defffe04 addi sp,sp,-8 + 1002dfc: dc000015 stw r16,0(sp) + 1002e00: 24000017 ldw r16,0(r4) + 1002e04: 29403fcc andi r5,r5,255 + 1002e08: 3007883a mov r3,r6 + 1002e0c: 81fffd17 ldw r7,-12(r16) + 1002e10: 2940201c xori r5,r5,128 + 1002e14: 8189883a add r4,r16,r6 + 1002e18: dfc00115 stw ra,4(sp) + 1002e1c: 297fe004 addi r5,r5,-128 + 1002e20: 398dc83a sub r6,r7,r6 + 1002e24: 19c0082e bgeu r3,r7,1002e48 <_ZNKSs4findEcm+0x50> + 1002e28: 100a8e40 call 100a8e4 + 1002e2c: 1407c83a sub r3,r2,r16 + 1002e30: 10000526 beq r2,zero,1002e48 <_ZNKSs4findEcm+0x50> + 1002e34: 1805883a mov r2,r3 + 1002e38: dfc00117 ldw ra,4(sp) + 1002e3c: dc000017 ldw r16,0(sp) + 1002e40: dec00204 addi sp,sp,8 + 1002e44: f800283a ret + 1002e48: 00ffffc4 movi r3,-1 + 1002e4c: 1805883a mov r2,r3 + 1002e50: dfc00117 ldw ra,4(sp) + 1002e54: dc000017 ldw r16,0(sp) + 1002e58: dec00204 addi sp,sp,8 + 1002e5c: f800283a ret + +01002e60 <_ZNKSs13find_first_ofEcm>: + 1002e60: 29403fcc andi r5,r5,255 + 1002e64: 2940201c xori r5,r5,128 + 1002e68: 297fe004 addi r5,r5,-128 + 1002e6c: 1002df81 jmpi 1002df8 <_ZNKSs4findEcm> + +01002e70 <_ZNKSs16find_last_not_ofEPKcmm>: + 1002e70: 20800017 ldw r2,0(r4) + 1002e74: defffb04 addi sp,sp,-20 + 1002e78: dcc00315 stw r19,12(sp) + 1002e7c: 10fffd17 ldw r3,-12(r2) + 1002e80: dc800215 stw r18,8(sp) + 1002e84: dc400115 stw r17,4(sp) + 1002e88: dfc00415 stw ra,16(sp) + 1002e8c: dc000015 stw r16,0(sp) + 1002e90: 2027883a mov r19,r4 + 1002e94: 2825883a mov r18,r5 + 1002e98: 3823883a mov r17,r7 + 1002e9c: 18002326 beq r3,zero,1002f2c <_ZNKSs16find_last_not_ofEPKcmm+0xbc> + 1002ea0: 1c3fffc4 addi r16,r3,-1 + 1002ea4: 3400102e bgeu r6,r16,1002ee8 <_ZNKSs16find_last_not_ofEPKcmm+0x78> + 1002ea8: 3021883a mov r16,r6 + 1002eac: 1405883a add r2,r2,r16 + 1002eb0: 11400007 ldb r5,0(r2) + 1002eb4: 9009883a mov r4,r18 + 1002eb8: 880d883a mov r6,r17 + 1002ebc: 100a8e40 call 100a8e4 + 1002ec0: 10000f1e bne r2,zero,1002f00 <_ZNKSs16find_last_not_ofEPKcmm+0x90> + 1002ec4: 8005883a mov r2,r16 + 1002ec8: dfc00417 ldw ra,16(sp) + 1002ecc: dcc00317 ldw r19,12(sp) + 1002ed0: dc800217 ldw r18,8(sp) + 1002ed4: dc400117 ldw r17,4(sp) + 1002ed8: dc000017 ldw r16,0(sp) + 1002edc: dec00504 addi sp,sp,20 + 1002ee0: f800283a ret + 1002ee4: 98800017 ldw r2,0(r19) + 1002ee8: 1405883a add r2,r2,r16 + 1002eec: 11400007 ldb r5,0(r2) + 1002ef0: 9009883a mov r4,r18 + 1002ef4: 880d883a mov r6,r17 + 1002ef8: 100a8e40 call 100a8e4 + 1002efc: 103ff126 beq r2,zero,1002ec4 <_ZNKSs16find_last_not_ofEPKcmm+0x54> + 1002f00: 843fffc4 addi r16,r16,-1 + 1002f04: 00bfffc4 movi r2,-1 + 1002f08: 80bff61e bne r16,r2,1002ee4 <_ZNKSs16find_last_not_ofEPKcmm+0x74> + 1002f0c: 8005883a mov r2,r16 + 1002f10: dfc00417 ldw ra,16(sp) + 1002f14: dcc00317 ldw r19,12(sp) + 1002f18: dc800217 ldw r18,8(sp) + 1002f1c: dc400117 ldw r17,4(sp) + 1002f20: dc000017 ldw r16,0(sp) + 1002f24: dec00504 addi sp,sp,20 + 1002f28: f800283a ret + 1002f2c: 043fffc4 movi r16,-1 + 1002f30: 8005883a mov r2,r16 + 1002f34: dfc00417 ldw ra,16(sp) + 1002f38: dcc00317 ldw r19,12(sp) + 1002f3c: dc800217 ldw r18,8(sp) + 1002f40: dc400117 ldw r17,4(sp) + 1002f44: dc000017 ldw r16,0(sp) + 1002f48: dec00504 addi sp,sp,20 + 1002f4c: f800283a ret + +01002f50 <_ZNKSs16find_last_not_ofERKSsm>: + 1002f50: 29400017 ldw r5,0(r5) + 1002f54: 29fffd17 ldw r7,-12(r5) + 1002f58: 1002e701 jmpi 1002e70 <_ZNKSs16find_last_not_ofEPKcmm> + +01002f5c <_ZNKSs7compareERKSs>: + 1002f5c: 20800017 ldw r2,0(r4) + 1002f60: 28c00017 ldw r3,0(r5) + 1002f64: defffb04 addi sp,sp,-20 + 1002f68: dc400315 stw r17,12(sp) + 1002f6c: dc000215 stw r16,8(sp) + 1002f70: 147ffd17 ldw r17,-12(r2) + 1002f74: 1c3ffd17 ldw r16,-12(r3) + 1002f78: dfc00415 stw ra,16(sp) + 1002f7c: d80d883a mov r6,sp + 1002f80: dc400015 stw r17,0(sp) + 1002f84: dc000115 stw r16,4(sp) + 1002f88: 8440012e bgeu r16,r17,1002f90 <_ZNKSs7compareERKSs+0x34> + 1002f8c: d9800104 addi r6,sp,4 + 1002f90: 21000017 ldw r4,0(r4) + 1002f94: 29400017 ldw r5,0(r5) + 1002f98: 31800017 ldw r6,0(r6) + 1002f9c: 100a9c80 call 100a9c8 + 1002fa0: 1000011e bne r2,zero,1002fa8 <_ZNKSs7compareERKSs+0x4c> + 1002fa4: 8c05c83a sub r2,r17,r16 + 1002fa8: dfc00417 ldw ra,16(sp) + 1002fac: dc400317 ldw r17,12(sp) + 1002fb0: dc000217 ldw r16,8(sp) + 1002fb4: dec00504 addi sp,sp,20 + 1002fb8: f800283a ret + +01002fbc <_ZNKSs4findEPKcm>: + 1002fbc: defffc04 addi sp,sp,-16 + 1002fc0: dd400215 stw r21,8(sp) + 1002fc4: dcc00115 stw r19,4(sp) + 1002fc8: dc400015 stw r17,0(sp) + 1002fcc: 2027883a mov r19,r4 + 1002fd0: dfc00315 stw ra,12(sp) + 1002fd4: 2809883a mov r4,r5 + 1002fd8: 2823883a mov r17,r5 + 1002fdc: 302b883a mov r21,r6 + 1002fe0: 100b1640 call 100b164 + 1002fe4: 880b883a mov r5,r17 + 1002fe8: 9809883a mov r4,r19 + 1002fec: a80d883a mov r6,r21 + 1002ff0: 100f883a mov r7,r2 + 1002ff4: dfc00317 ldw ra,12(sp) + 1002ff8: dd400217 ldw r21,8(sp) + 1002ffc: dcc00117 ldw r19,4(sp) + 1003000: dc400017 ldw r17,0(sp) + 1003004: dec00404 addi sp,sp,16 + 1003008: 10027901 jmpi 1002790 <_ZNKSs4findEPKcmm> + +0100300c <_ZNKSs7compareEPKc>: + 100300c: 20800017 ldw r2,0(r4) + 1003010: defff904 addi sp,sp,-28 + 1003014: dc400315 stw r17,12(sp) + 1003018: 147ffd17 ldw r17,-12(r2) + 100301c: dcc00515 stw r19,20(sp) + 1003020: dc800415 stw r18,16(sp) + 1003024: dc000215 stw r16,8(sp) + 1003028: dfc00615 stw ra,24(sp) + 100302c: 2025883a mov r18,r4 + 1003030: dc400015 stw r17,0(sp) + 1003034: 2809883a mov r4,r5 + 1003038: 2827883a mov r19,r5 + 100303c: 100b1640 call 100b164 + 1003040: 1021883a mov r16,r2 + 1003044: d80d883a mov r6,sp + 1003048: d8800115 stw r2,4(sp) + 100304c: 1440012e bgeu r2,r17,1003054 <_ZNKSs7compareEPKc+0x48> + 1003050: d9800104 addi r6,sp,4 + 1003054: 91000017 ldw r4,0(r18) + 1003058: 31800017 ldw r6,0(r6) + 100305c: 980b883a mov r5,r19 + 1003060: 100a9c80 call 100a9c8 + 1003064: 1000011e bne r2,zero,100306c <_ZNKSs7compareEPKc+0x60> + 1003068: 8c05c83a sub r2,r17,r16 + 100306c: dfc00617 ldw ra,24(sp) + 1003070: dcc00517 ldw r19,20(sp) + 1003074: dc800417 ldw r18,16(sp) + 1003078: dc400317 ldw r17,12(sp) + 100307c: dc000217 ldw r16,8(sp) + 1003080: dec00704 addi sp,sp,28 + 1003084: f800283a ret + +01003088 <_ZNKSs16find_last_not_ofEPKcm>: + 1003088: defffc04 addi sp,sp,-16 + 100308c: dd400215 stw r21,8(sp) + 1003090: dcc00115 stw r19,4(sp) + 1003094: dc400015 stw r17,0(sp) + 1003098: 2027883a mov r19,r4 + 100309c: dfc00315 stw ra,12(sp) + 10030a0: 2809883a mov r4,r5 + 10030a4: 2823883a mov r17,r5 + 10030a8: 302b883a mov r21,r6 + 10030ac: 100b1640 call 100b164 + 10030b0: 880b883a mov r5,r17 + 10030b4: 9809883a mov r4,r19 + 10030b8: a80d883a mov r6,r21 + 10030bc: 100f883a mov r7,r2 + 10030c0: dfc00317 ldw ra,12(sp) + 10030c4: dd400217 ldw r21,8(sp) + 10030c8: dcc00117 ldw r19,4(sp) + 10030cc: dc400017 ldw r17,0(sp) + 10030d0: dec00404 addi sp,sp,16 + 10030d4: 1002e701 jmpi 1002e70 <_ZNKSs16find_last_not_ofEPKcmm> + +010030d8 <_ZNKSs17find_first_not_ofEPKcm>: + 10030d8: defffc04 addi sp,sp,-16 + 10030dc: dd400215 stw r21,8(sp) + 10030e0: dcc00115 stw r19,4(sp) + 10030e4: dc400015 stw r17,0(sp) + 10030e8: 2027883a mov r19,r4 + 10030ec: dfc00315 stw ra,12(sp) + 10030f0: 2809883a mov r4,r5 + 10030f4: 2823883a mov r17,r5 + 10030f8: 302b883a mov r21,r6 + 10030fc: 100b1640 call 100b164 + 1003100: 880b883a mov r5,r17 + 1003104: 9809883a mov r4,r19 + 1003108: a80d883a mov r6,r21 + 100310c: 100f883a mov r7,r2 + 1003110: dfc00317 ldw ra,12(sp) + 1003114: dd400217 ldw r21,8(sp) + 1003118: dcc00117 ldw r19,4(sp) + 100311c: dc400017 ldw r17,0(sp) + 1003120: dec00404 addi sp,sp,16 + 1003124: 10026ec1 jmpi 10026ec <_ZNKSs17find_first_not_ofEPKcmm> + +01003128 <_ZNKSs12find_last_ofEPKcm>: + 1003128: defffc04 addi sp,sp,-16 + 100312c: dd400215 stw r21,8(sp) + 1003130: dcc00115 stw r19,4(sp) + 1003134: dc400015 stw r17,0(sp) + 1003138: 2027883a mov r19,r4 + 100313c: dfc00315 stw ra,12(sp) + 1003140: 2809883a mov r4,r5 + 1003144: 2823883a mov r17,r5 + 1003148: 302b883a mov r21,r6 + 100314c: 100b1640 call 100b164 + 1003150: 880b883a mov r5,r17 + 1003154: 9809883a mov r4,r19 + 1003158: a80d883a mov r6,r21 + 100315c: 100f883a mov r7,r2 + 1003160: dfc00317 ldw ra,12(sp) + 1003164: dd400217 ldw r21,8(sp) + 1003168: dcc00117 ldw r19,4(sp) + 100316c: dc400017 ldw r17,0(sp) + 1003170: dec00404 addi sp,sp,16 + 1003174: 1002c741 jmpi 1002c74 <_ZNKSs12find_last_ofEPKcmm> + +01003178 <_ZNKSs13find_first_ofEPKcm>: + 1003178: defffc04 addi sp,sp,-16 + 100317c: dd400215 stw r21,8(sp) + 1003180: dcc00115 stw r19,4(sp) + 1003184: dc400015 stw r17,0(sp) + 1003188: 2027883a mov r19,r4 + 100318c: dfc00315 stw ra,12(sp) + 1003190: 2809883a mov r4,r5 + 1003194: 2823883a mov r17,r5 + 1003198: 302b883a mov r21,r6 + 100319c: 100b1640 call 100b164 + 10031a0: 880b883a mov r5,r17 + 10031a4: 9809883a mov r4,r19 + 10031a8: a80d883a mov r6,r21 + 10031ac: 100f883a mov r7,r2 + 10031b0: dfc00317 ldw ra,12(sp) + 10031b4: dd400217 ldw r21,8(sp) + 10031b8: dcc00117 ldw r19,4(sp) + 10031bc: dc400017 ldw r17,0(sp) + 10031c0: dec00404 addi sp,sp,16 + 10031c4: 1002d641 jmpi 1002d64 <_ZNKSs13find_first_ofEPKcmm> + +010031c8 <_ZNKSs4rendEv>: + 10031c8: 28c00017 ldw r3,0(r5) + 10031cc: 2005883a mov r2,r4 + 10031d0: 20c00015 stw r3,0(r4) + 10031d4: f800283a ret + +010031d8 <_ZNKSs6rbeginEv>: + 10031d8: 28c00017 ldw r3,0(r5) + 10031dc: 2005883a mov r2,r4 + 10031e0: 197ffd17 ldw r5,-12(r3) + 10031e4: 1947883a add r3,r3,r5 + 10031e8: 20c00015 stw r3,0(r4) + 10031ec: f800283a ret + +010031f0 <_ZNSs12_S_constructEmcRKSaIcE>: + 10031f0: defffb04 addi sp,sp,-20 + 10031f4: dcc00315 stw r19,12(sp) + 10031f8: dc400115 stw r17,4(sp) + 10031fc: dc000015 stw r16,0(sp) + 1003200: 2823883a mov r17,r5 + 1003204: dfc00415 stw ra,16(sp) + 1003208: dc800215 stw r18,8(sp) + 100320c: 2021883a mov r16,r4 + 1003210: 04c040f4 movhi r19,259 + 1003214: 9ce53204 addi r19,r19,-27448 + 1003218: 000b883a mov r5,zero + 100321c: 2000081e bne r4,zero,1003240 <_ZNSs12_S_constructEmcRKSaIcE+0x50> + 1003220: 9805883a mov r2,r19 + 1003224: dfc00417 ldw ra,16(sp) + 1003228: dcc00317 ldw r19,12(sp) + 100322c: dc800217 ldw r18,8(sp) + 1003230: dc400117 ldw r17,4(sp) + 1003234: dc000017 ldw r16,0(sp) + 1003238: dec00504 addi sp,sp,20 + 100323c: f800283a ret + 1003240: 1002adc0 call 1002adc <_ZNSs4_Rep9_S_createEmmRKSaIcE> + 1003244: 88c03fcc andi r3,r17,255 + 1003248: 18c0201c xori r3,r3,128 + 100324c: 18ffe004 addi r3,r3,-128 + 1003250: 19403fcc andi r5,r3,255 + 1003254: 14c00304 addi r19,r2,12 + 1003258: 1025883a mov r18,r2 + 100325c: 2940201c xori r5,r5,128 + 1003260: 00800044 movi r2,1 + 1003264: 800d883a mov r6,r16 + 1003268: 9809883a mov r4,r19 + 100326c: 297fe004 addi r5,r5,-128 + 1003270: 80800d26 beq r16,r2,10032a8 <_ZNSs12_S_constructEmcRKSaIcE+0xb8> + 1003274: 100abbc0 call 100abbc + 1003278: 84c5883a add r2,r16,r19 + 100327c: 94000015 stw r16,0(r18) + 1003280: 90000215 stw zero,8(r18) + 1003284: 10000005 stb zero,0(r2) + 1003288: 9805883a mov r2,r19 + 100328c: dfc00417 ldw ra,16(sp) + 1003290: dcc00317 ldw r19,12(sp) + 1003294: dc800217 ldw r18,8(sp) + 1003298: dc400117 ldw r17,4(sp) + 100329c: dc000017 ldw r16,0(sp) + 10032a0: dec00504 addi sp,sp,20 + 10032a4: f800283a ret + 10032a8: 98c00005 stb r3,0(r19) + 10032ac: 003ff206 br 1003278 <_ZNSs12_S_constructEmcRKSaIcE+0x88> + +010032b0 <_ZNSsC1EmcRKSaIcE>: + 10032b0: defffe04 addi sp,sp,-8 + 10032b4: dc400015 stw r17,0(sp) + 10032b8: 2023883a mov r17,r4 + 10032bc: 2809883a mov r4,r5 + 10032c0: 31403fcc andi r5,r6,255 + 10032c4: 2940201c xori r5,r5,128 + 10032c8: 297fe004 addi r5,r5,-128 + 10032cc: 380d883a mov r6,r7 + 10032d0: dfc00115 stw ra,4(sp) + 10032d4: 10031f00 call 10031f0 <_ZNSs12_S_constructEmcRKSaIcE> + 10032d8: 88800015 stw r2,0(r17) + 10032dc: dfc00117 ldw ra,4(sp) + 10032e0: dc400017 ldw r17,0(sp) + 10032e4: dec00204 addi sp,sp,8 + 10032e8: f800283a ret + +010032ec <_ZNSsC2EmcRKSaIcE>: + 10032ec: defffe04 addi sp,sp,-8 + 10032f0: dc400015 stw r17,0(sp) + 10032f4: 2023883a mov r17,r4 + 10032f8: 2809883a mov r4,r5 + 10032fc: 31403fcc andi r5,r6,255 + 1003300: 2940201c xori r5,r5,128 + 1003304: 297fe004 addi r5,r5,-128 + 1003308: 380d883a mov r6,r7 + 100330c: dfc00115 stw ra,4(sp) + 1003310: 10031f00 call 10031f0 <_ZNSs12_S_constructEmcRKSaIcE> + 1003314: 88800015 stw r2,0(r17) + 1003318: dfc00117 ldw ra,4(sp) + 100331c: dc400017 ldw r17,0(sp) + 1003320: dec00204 addi sp,sp,8 + 1003324: f800283a ret + +01003328 <_ZNSsC1ERKSaIcE>: + 1003328: defffe04 addi sp,sp,-8 + 100332c: dc400015 stw r17,0(sp) + 1003330: 280d883a mov r6,r5 + 1003334: 2023883a mov r17,r4 + 1003338: 000b883a mov r5,zero + 100333c: 0009883a mov r4,zero + 1003340: dfc00115 stw ra,4(sp) + 1003344: 10031f00 call 10031f0 <_ZNSs12_S_constructEmcRKSaIcE> + 1003348: 88800015 stw r2,0(r17) + 100334c: dfc00117 ldw ra,4(sp) + 1003350: dc400017 ldw r17,0(sp) + 1003354: dec00204 addi sp,sp,8 + 1003358: f800283a ret + +0100335c <_ZNSsC2ERKSaIcE>: + 100335c: defffe04 addi sp,sp,-8 + 1003360: dc400015 stw r17,0(sp) + 1003364: 280d883a mov r6,r5 + 1003368: 2023883a mov r17,r4 + 100336c: 000b883a mov r5,zero + 1003370: 0009883a mov r4,zero + 1003374: dfc00115 stw ra,4(sp) + 1003378: 10031f00 call 10031f0 <_ZNSs12_S_constructEmcRKSaIcE> + 100337c: 88800015 stw r2,0(r17) + 1003380: dfc00117 ldw ra,4(sp) + 1003384: dc400017 ldw r17,0(sp) + 1003388: dec00204 addi sp,sp,8 + 100338c: f800283a ret + +01003390 <_ZNKSs7compareEmmPKcm>: + 1003390: 21000017 ldw r4,0(r4) + 1003394: defffc04 addi sp,sp,-16 + 1003398: d9800015 stw r6,0(sp) + 100339c: 20bffd17 ldw r2,-12(r4) + 10033a0: dfc00315 stw ra,12(sp) + 10033a4: dc400215 stw r17,8(sp) + 10033a8: dc000115 stw r16,4(sp) + 10033ac: 11401936 bltu r2,r5,1003414 <_ZNKSs7compareEmmPKcm+0x84> + 10033b0: dc000017 ldw r16,0(sp) + 10033b4: 1145c83a sub r2,r2,r5 + 10033b8: 14001136 bltu r2,r16,1003400 <_ZNKSs7compareEmmPKcm+0x70> + 10033bc: dc400417 ldw r17,16(sp) + 10033c0: dc000015 stw r16,0(sp) + 10033c4: 8c000c36 bltu r17,r16,10033f8 <_ZNKSs7compareEmmPKcm+0x68> + 10033c8: d80d883a mov r6,sp + 10033cc: 31800017 ldw r6,0(r6) + 10033d0: 2149883a add r4,r4,r5 + 10033d4: 380b883a mov r5,r7 + 10033d8: 100a9c80 call 100a9c8 + 10033dc: 1000011e bne r2,zero,10033e4 <_ZNKSs7compareEmmPKcm+0x54> + 10033e0: 8445c83a sub r2,r16,r17 + 10033e4: dfc00317 ldw ra,12(sp) + 10033e8: dc400217 ldw r17,8(sp) + 10033ec: dc000117 ldw r16,4(sp) + 10033f0: dec00404 addi sp,sp,16 + 10033f4: f800283a ret + 10033f8: d9800404 addi r6,sp,16 + 10033fc: 003ff306 br 10033cc <_ZNKSs7compareEmmPKcm+0x3c> + 1003400: dc400417 ldw r17,16(sp) + 1003404: 1021883a mov r16,r2 + 1003408: dc000015 stw r16,0(sp) + 100340c: 8c3ffa36 bltu r17,r16,10033f8 <_ZNKSs7compareEmmPKcm+0x68> + 1003410: 003fed06 br 10033c8 <_ZNKSs7compareEmmPKcm+0x38> + 1003414: 010040b4 movhi r4,258 + 1003418: 2103ea04 addi r4,r4,4008 + 100341c: 10084dc0 call 10084dc <_ZSt20__throw_out_of_rangePKc> + +01003420 <_ZNKSs7compareEmmPKc>: + 1003420: defff804 addi sp,sp,-32 + 1003424: dd000615 stw r20,24(sp) + 1003428: 25000017 ldw r20,0(r4) + 100342c: d9800115 stw r6,4(sp) + 1003430: dcc00515 stw r19,20(sp) + 1003434: a0bffd17 ldw r2,-12(r20) + 1003438: dc800415 stw r18,16(sp) + 100343c: dfc00715 stw ra,28(sp) + 1003440: dc400315 stw r17,12(sp) + 1003444: dc000215 stw r16,8(sp) + 1003448: 2825883a mov r18,r5 + 100344c: 3827883a mov r19,r7 + 1003450: 11402236 bltu r2,r5,10034dc <_ZNKSs7compareEmmPKc+0xbc> + 1003454: 1145c83a sub r2,r2,r5 + 1003458: 3023883a mov r17,r6 + 100345c: 11801736 bltu r2,r6,10034bc <_ZNKSs7compareEmmPKc+0x9c> + 1003460: dc400115 stw r17,4(sp) + 1003464: 9809883a mov r4,r19 + 1003468: 100b1640 call 100b164 + 100346c: 1021883a mov r16,r2 + 1003470: d8800015 stw r2,0(sp) + 1003474: 14400f36 bltu r2,r17,10034b4 <_ZNKSs7compareEmmPKc+0x94> + 1003478: d9800104 addi r6,sp,4 + 100347c: 31800017 ldw r6,0(r6) + 1003480: a489883a add r4,r20,r18 + 1003484: 980b883a mov r5,r19 + 1003488: 100a9c80 call 100a9c8 + 100348c: 1000011e bne r2,zero,1003494 <_ZNKSs7compareEmmPKc+0x74> + 1003490: 8c05c83a sub r2,r17,r16 + 1003494: dfc00717 ldw ra,28(sp) + 1003498: dd000617 ldw r20,24(sp) + 100349c: dcc00517 ldw r19,20(sp) + 10034a0: dc800417 ldw r18,16(sp) + 10034a4: dc400317 ldw r17,12(sp) + 10034a8: dc000217 ldw r16,8(sp) + 10034ac: dec00804 addi sp,sp,32 + 10034b0: f800283a ret + 10034b4: d80d883a mov r6,sp + 10034b8: 003ff006 br 100347c <_ZNKSs7compareEmmPKc+0x5c> + 10034bc: 1023883a mov r17,r2 + 10034c0: dc400115 stw r17,4(sp) + 10034c4: 9809883a mov r4,r19 + 10034c8: 100b1640 call 100b164 + 10034cc: 1021883a mov r16,r2 + 10034d0: d8800015 stw r2,0(sp) + 10034d4: 147ff736 bltu r2,r17,10034b4 <_ZNKSs7compareEmmPKc+0x94> + 10034d8: 003fe706 br 1003478 <_ZNKSs7compareEmmPKc+0x58> + 10034dc: 010040b4 movhi r4,258 + 10034e0: 2103ea04 addi r4,r4,4008 + 10034e4: 10084dc0 call 10084dc <_ZSt20__throw_out_of_rangePKc> + +010034e8 <_ZNKSs7compareEmmRKSsmm>: + 10034e8: 21000017 ldw r4,0(r4) + 10034ec: defffc04 addi sp,sp,-16 + 10034f0: d9800015 stw r6,0(sp) + 10034f4: 20bffd17 ldw r2,-12(r4) + 10034f8: dfc00315 stw ra,12(sp) + 10034fc: dc400215 stw r17,8(sp) + 1003500: dc000115 stw r16,4(sp) + 1003504: da000417 ldw r8,16(sp) + 1003508: 11402436 bltu r2,r5,100359c <_ZNKSs7compareEmmRKSsmm+0xb4> + 100350c: 39c00017 ldw r7,0(r7) + 1003510: 38fffd17 ldw r3,-12(r7) + 1003514: 1a002136 bltu r3,r8,100359c <_ZNKSs7compareEmmRKSsmm+0xb4> + 1003518: dc400017 ldw r17,0(sp) + 100351c: 1145c83a sub r2,r2,r5 + 1003520: 14401836 bltu r2,r17,1003584 <_ZNKSs7compareEmmRKSsmm+0x9c> + 1003524: dc000517 ldw r16,20(sp) + 1003528: 1a05c83a sub r2,r3,r8 + 100352c: dc400015 stw r17,0(sp) + 1003530: 14001036 bltu r2,r16,1003574 <_ZNKSs7compareEmmRKSsmm+0x8c> + 1003534: dc000515 stw r16,20(sp) + 1003538: 84400c36 bltu r16,r17,100356c <_ZNKSs7compareEmmRKSsmm+0x84> + 100353c: d80d883a mov r6,sp + 1003540: 31800017 ldw r6,0(r6) + 1003544: 2149883a add r4,r4,r5 + 1003548: 3a0b883a add r5,r7,r8 + 100354c: 100a9c80 call 100a9c8 + 1003550: 1000011e bne r2,zero,1003558 <_ZNKSs7compareEmmRKSsmm+0x70> + 1003554: 8c05c83a sub r2,r17,r16 + 1003558: dfc00317 ldw ra,12(sp) + 100355c: dc400217 ldw r17,8(sp) + 1003560: dc000117 ldw r16,4(sp) + 1003564: dec00404 addi sp,sp,16 + 1003568: f800283a ret + 100356c: d9800504 addi r6,sp,20 + 1003570: 003ff306 br 1003540 <_ZNKSs7compareEmmRKSsmm+0x58> + 1003574: 1021883a mov r16,r2 + 1003578: dc000515 stw r16,20(sp) + 100357c: 847ffb36 bltu r16,r17,100356c <_ZNKSs7compareEmmRKSsmm+0x84> + 1003580: 003fee06 br 100353c <_ZNKSs7compareEmmRKSsmm+0x54> + 1003584: dc000517 ldw r16,20(sp) + 1003588: 1023883a mov r17,r2 + 100358c: 1a05c83a sub r2,r3,r8 + 1003590: dc400015 stw r17,0(sp) + 1003594: 143fe72e bgeu r2,r16,1003534 <_ZNKSs7compareEmmRKSsmm+0x4c> + 1003598: 003ff606 br 1003574 <_ZNKSs7compareEmmRKSsmm+0x8c> + 100359c: 010040b4 movhi r4,258 + 10035a0: 2103ea04 addi r4,r4,4008 + 10035a4: 10084dc0 call 10084dc <_ZSt20__throw_out_of_rangePKc> + +010035a8 <_ZNKSs7compareEmmRKSs>: + 10035a8: 21000017 ldw r4,0(r4) + 10035ac: defffb04 addi sp,sp,-20 + 10035b0: d9800115 stw r6,4(sp) + 10035b4: 20bffd17 ldw r2,-12(r4) + 10035b8: dfc00415 stw ra,16(sp) + 10035bc: dc400315 stw r17,12(sp) + 10035c0: dc000215 stw r16,8(sp) + 10035c4: 11401d36 bltu r2,r5,100363c <_ZNKSs7compareEmmRKSs+0x94> + 10035c8: 1145c83a sub r2,r2,r5 + 10035cc: 3021883a mov r16,r6 + 10035d0: 11801336 bltu r2,r6,1003620 <_ZNKSs7compareEmmRKSs+0x78> + 10035d4: 38800017 ldw r2,0(r7) + 10035d8: dc000115 stw r16,4(sp) + 10035dc: 147ffd17 ldw r17,-12(r2) + 10035e0: dc400015 stw r17,0(sp) + 10035e4: 8c000c36 bltu r17,r16,1003618 <_ZNKSs7compareEmmRKSs+0x70> + 10035e8: d9800104 addi r6,sp,4 + 10035ec: 31800017 ldw r6,0(r6) + 10035f0: 2149883a add r4,r4,r5 + 10035f4: 100b883a mov r5,r2 + 10035f8: 100a9c80 call 100a9c8 + 10035fc: 1000011e bne r2,zero,1003604 <_ZNKSs7compareEmmRKSs+0x5c> + 1003600: 8445c83a sub r2,r16,r17 + 1003604: dfc00417 ldw ra,16(sp) + 1003608: dc400317 ldw r17,12(sp) + 100360c: dc000217 ldw r16,8(sp) + 1003610: dec00504 addi sp,sp,20 + 1003614: f800283a ret + 1003618: d80d883a mov r6,sp + 100361c: 003ff306 br 10035ec <_ZNKSs7compareEmmRKSs+0x44> + 1003620: 1021883a mov r16,r2 + 1003624: 38800017 ldw r2,0(r7) + 1003628: dc000115 stw r16,4(sp) + 100362c: 147ffd17 ldw r17,-12(r2) + 1003630: dc400015 stw r17,0(sp) + 1003634: 8c3ff836 bltu r17,r16,1003618 <_ZNKSs7compareEmmRKSs+0x70> + 1003638: 003feb06 br 10035e8 <_ZNKSs7compareEmmRKSs+0x40> + 100363c: 010040b4 movhi r4,258 + 1003640: 2103ea04 addi r4,r4,4008 + 1003644: 10084dc0 call 10084dc <_ZSt20__throw_out_of_rangePKc> + +01003648 <_ZNSs4_Rep8_M_cloneERKSaIcEm>: + 1003648: defffc04 addi sp,sp,-16 + 100364c: dc000015 stw r16,0(sp) + 1003650: 2021883a mov r16,r4 + 1003654: 21000017 ldw r4,0(r4) + 1003658: 2807883a mov r3,r5 + 100365c: 81400117 ldw r5,4(r16) + 1003660: 3109883a add r4,r6,r4 + 1003664: 180d883a mov r6,r3 + 1003668: dc800215 stw r18,8(sp) + 100366c: dc400115 stw r17,4(sp) + 1003670: dfc00315 stw ra,12(sp) + 1003674: 1002adc0 call 1002adc <_ZNSs4_Rep9_S_createEmmRKSaIcE> + 1003678: 80c00017 ldw r3,0(r16) + 100367c: 1023883a mov r17,r2 + 1003680: 14800304 addi r18,r2,12 + 1003684: 18000826 beq r3,zero,10036a8 <_ZNSs4_Rep8_M_cloneERKSaIcEm+0x60> + 1003688: 14800304 addi r18,r2,12 + 100368c: 00800044 movi r2,1 + 1003690: 180d883a mov r6,r3 + 1003694: 9009883a mov r4,r18 + 1003698: 81400304 addi r5,r16,12 + 100369c: 18800d26 beq r3,r2,10036d4 <_ZNSs4_Rep8_M_cloneERKSaIcEm+0x8c> + 10036a0: 100aa3c0 call 100aa3c + 10036a4: 80c00017 ldw r3,0(r16) + 10036a8: 88c00015 stw r3,0(r17) + 10036ac: 88000215 stw zero,8(r17) + 10036b0: 1c87883a add r3,r3,r18 + 10036b4: 9005883a mov r2,r18 + 10036b8: 18000005 stb zero,0(r3) + 10036bc: dfc00317 ldw ra,12(sp) + 10036c0: dc800217 ldw r18,8(sp) + 10036c4: dc400117 ldw r17,4(sp) + 10036c8: dc000017 ldw r16,0(sp) + 10036cc: dec00404 addi sp,sp,16 + 10036d0: f800283a ret + 10036d4: 80800303 ldbu r2,12(r16) + 10036d8: 88800305 stb r2,12(r17) + 10036dc: 80c00017 ldw r3,0(r16) + 10036e0: 003ff106 br 10036a8 <_ZNSs4_Rep8_M_cloneERKSaIcEm+0x60> + +010036e4 <_ZNSs4_Rep7_M_grabERKSaIcES2_>: + 10036e4: deffed04 addi sp,sp,-76 + 10036e8: 00804034 movhi r2,256 + 10036ec: 109a9704 addi r2,r2,27228 + 10036f0: 00c040b4 movhi r3,258 + 10036f4: 18c2d504 addi r3,r3,2900 + 10036f8: d8800615 stw r2,24(sp) + 10036fc: d9000e15 stw r4,56(sp) + 1003700: 00804034 movhi r2,256 + 1003704: 108df104 addi r2,r2,14276 + 1003708: d809883a mov r4,sp + 100370c: d8c00715 stw r3,28(sp) + 1003710: d8800915 stw r2,36(sp) + 1003714: dfc01215 stw ra,72(sp) + 1003718: df001115 stw fp,68(sp) + 100371c: ddc01015 stw r23,64(sp) + 1003720: dec00815 stw sp,32(sp) + 1003724: dec00a15 stw sp,40(sp) + 1003728: d9400f15 stw r5,60(sp) + 100372c: 1009c1c0 call 1009c1c <_Unwind_SjLj_Register> + 1003730: d8c00e17 ldw r3,56(sp) + 1003734: 18800217 ldw r2,8(r3) + 1003738: 10000e16 blt r2,zero,1003774 <_ZNSs4_Rep7_M_grabERKSaIcES2_+0x90> + 100373c: 008040f4 movhi r2,259 + 1003740: 10a52f04 addi r2,r2,-27460 + 1003744: 18801a1e bne r3,r2,10037b0 <_ZNSs4_Rep7_M_grabERKSaIcES2_+0xcc> + 1003748: d8800e17 ldw r2,56(sp) + 100374c: d809883a mov r4,sp + 1003750: 10800304 addi r2,r2,12 + 1003754: d8800d15 stw r2,52(sp) + 1003758: 1009c2c0 call 1009c2c <_Unwind_SjLj_Unregister> + 100375c: d8800d17 ldw r2,52(sp) + 1003760: dfc01217 ldw ra,72(sp) + 1003764: df001117 ldw fp,68(sp) + 1003768: ddc01017 ldw r23,64(sp) + 100376c: dec01304 addi sp,sp,76 + 1003770: f800283a ret + 1003774: d9000e17 ldw r4,56(sp) + 1003778: d9400f17 ldw r5,60(sp) + 100377c: 000d883a mov r6,zero + 1003780: 00bfffc4 movi r2,-1 + 1003784: d8800115 stw r2,4(sp) + 1003788: 10036480 call 1003648 <_ZNSs4_Rep8_M_cloneERKSaIcEm> + 100378c: d809883a mov r4,sp + 1003790: d8800d15 stw r2,52(sp) + 1003794: 1009c2c0 call 1009c2c <_Unwind_SjLj_Unregister> + 1003798: d8800d17 ldw r2,52(sp) + 100379c: dfc01217 ldw ra,72(sp) + 10037a0: df001117 ldw fp,68(sp) + 10037a4: ddc01017 ldw r23,64(sp) + 10037a8: dec01304 addi sp,sp,76 + 10037ac: f800283a ret + 10037b0: 01400044 movi r5,1 + 10037b4: d9400115 stw r5,4(sp) + 10037b8: 19000204 addi r4,r3,8 + 10037bc: 10061900 call 1006190 <_ZN9__gnu_cxx12__atomic_addEPVii> + 10037c0: 003fe106 br 1003748 <_ZNSs4_Rep7_M_grabERKSaIcES2_+0x64> + 10037c4: d8800317 ldw r2,12(sp) + 10037c8: 00ffffc4 movi r3,-1 + 10037cc: d9000217 ldw r4,8(sp) + 10037d0: 10c00226 beq r2,r3,10037dc <_ZNSs4_Rep7_M_grabERKSaIcES2_+0xf8> + 10037d4: d8c00115 stw r3,4(sp) + 10037d8: 1009ee80 call 1009ee8 <_Unwind_SjLj_Resume> + 10037dc: 00bfffc4 movi r2,-1 + 10037e0: d8800115 stw r2,4(sp) + 10037e4: 10068dc0 call 10068dc <__cxa_call_unexpected> + +010037e8 <_ZNKSs4copyEPcmm>: + 10037e8: 21000017 ldw r4,0(r4) + 10037ec: defffe04 addi sp,sp,-8 + 10037f0: dfc00115 stw ra,4(sp) + 10037f4: 20fffd17 ldw r3,-12(r4) + 10037f8: dc000015 stw r16,0(sp) + 10037fc: 2811883a mov r8,r5 + 1003800: 19c01836 bltu r3,r7,1003864 <_ZNKSs4copyEPcmm+0x7c> + 1003804: 19c5c83a sub r2,r3,r7 + 1003808: 3021883a mov r16,r6 + 100380c: 11800c36 bltu r2,r6,1003840 <_ZNKSs4copyEPcmm+0x58> + 1003810: 80000626 beq r16,zero,100382c <_ZNKSs4copyEPcmm+0x44> + 1003814: 00800044 movi r2,1 + 1003818: 21cb883a add r5,r4,r7 + 100381c: 80800a26 beq r16,r2,1003848 <_ZNKSs4copyEPcmm+0x60> + 1003820: 4009883a mov r4,r8 + 1003824: 800d883a mov r6,r16 + 1003828: 100aa3c0 call 100aa3c + 100382c: 8005883a mov r2,r16 + 1003830: dfc00117 ldw ra,4(sp) + 1003834: dc000017 ldw r16,0(sp) + 1003838: dec00204 addi sp,sp,8 + 100383c: f800283a ret + 1003840: 1021883a mov r16,r2 + 1003844: 003ff206 br 1003810 <_ZNKSs4copyEPcmm+0x28> + 1003848: 28800003 ldbu r2,0(r5) + 100384c: 40800005 stb r2,0(r8) + 1003850: 8005883a mov r2,r16 + 1003854: dfc00117 ldw ra,4(sp) + 1003858: dc000017 ldw r16,0(sp) + 100385c: dec00204 addi sp,sp,8 + 1003860: f800283a ret + 1003864: 010040b4 movhi r4,258 + 1003868: 2103f004 addi r4,r4,4032 + 100386c: 10084dc0 call 10084dc <_ZSt20__throw_out_of_rangePKc> + +01003870 <_ZNSs13_S_copy_charsEPcPKcS1_>: + 1003870: 3147c83a sub r3,r6,r5 + 1003874: 00800044 movi r2,1 + 1003878: 180d883a mov r6,r3 + 100387c: 18800126 beq r3,r2,1003884 <_ZNSs13_S_copy_charsEPcPKcS1_+0x14> + 1003880: 100aa3c1 jmpi 100aa3c + 1003884: 28800003 ldbu r2,0(r5) + 1003888: 20800005 stb r2,0(r4) + 100388c: f800283a ret + +01003890 <_ZNSs13_S_copy_charsEPcS_S_>: + 1003890: 3147c83a sub r3,r6,r5 + 1003894: 00800044 movi r2,1 + 1003898: 180d883a mov r6,r3 + 100389c: 18800126 beq r3,r2,10038a4 <_ZNSs13_S_copy_charsEPcS_S_+0x14> + 10038a0: 100aa3c1 jmpi 100aa3c + 10038a4: 28800003 ldbu r2,0(r5) + 10038a8: 20800005 stb r2,0(r4) + 10038ac: f800283a ret + +010038b0 <_ZNSs12_S_constructIPcEES0_T_S1_RKSaIcESt20forward_iterator_tag>: + 10038b0: defffb04 addi sp,sp,-20 + 10038b4: dc000015 stw r16,0(sp) + 10038b8: dfc00415 stw ra,16(sp) + 10038bc: dcc00315 stw r19,12(sp) + 10038c0: dc800215 stw r18,8(sp) + 10038c4: dc400115 stw r17,4(sp) + 10038c8: 2021883a mov r16,r4 + 10038cc: 21401c26 beq r4,r5,1003940 <_ZNSs12_S_constructIPcEES0_T_S1_RKSaIcESt20forward_iterator_tag+0x90> + 10038d0: 20002526 beq r4,zero,1003968 <_ZNSs12_S_constructIPcEES0_T_S1_RKSaIcESt20forward_iterator_tag+0xb8> + 10038d4: 2c25c83a sub r18,r5,r16 + 10038d8: 9009883a mov r4,r18 + 10038dc: 000b883a mov r5,zero + 10038e0: 1002adc0 call 1002adc <_ZNSs4_Rep9_S_createEmmRKSaIcE> + 10038e4: 1023883a mov r17,r2 + 10038e8: 14c00304 addi r19,r2,12 + 10038ec: 00800044 movi r2,1 + 10038f0: 90801026 beq r18,r2,1003934 <_ZNSs12_S_constructIPcEES0_T_S1_RKSaIcESt20forward_iterator_tag+0x84> + 10038f4: 800b883a mov r5,r16 + 10038f8: 9809883a mov r4,r19 + 10038fc: 900d883a mov r6,r18 + 1003900: 100aa3c0 call 100aa3c + 1003904: 9c85883a add r2,r19,r18 + 1003908: 8c800015 stw r18,0(r17) + 100390c: 88000215 stw zero,8(r17) + 1003910: 10000005 stb zero,0(r2) + 1003914: 9805883a mov r2,r19 + 1003918: dfc00417 ldw ra,16(sp) + 100391c: dcc00317 ldw r19,12(sp) + 1003920: dc800217 ldw r18,8(sp) + 1003924: dc400117 ldw r17,4(sp) + 1003928: dc000017 ldw r16,0(sp) + 100392c: dec00504 addi sp,sp,20 + 1003930: f800283a ret + 1003934: 80800003 ldbu r2,0(r16) + 1003938: 88800305 stb r2,12(r17) + 100393c: 003ff106 br 1003904 <_ZNSs12_S_constructIPcEES0_T_S1_RKSaIcESt20forward_iterator_tag+0x54> + 1003940: 04c040f4 movhi r19,259 + 1003944: 9ce53204 addi r19,r19,-27448 + 1003948: 9805883a mov r2,r19 + 100394c: dfc00417 ldw ra,16(sp) + 1003950: dcc00317 ldw r19,12(sp) + 1003954: dc800217 ldw r18,8(sp) + 1003958: dc400117 ldw r17,4(sp) + 100395c: dc000017 ldw r16,0(sp) + 1003960: dec00504 addi sp,sp,20 + 1003964: f800283a ret + 1003968: 010040b4 movhi r4,258 + 100396c: 2103f504 addi r4,r4,4052 + 1003970: 10079ec0 call 10079ec <_ZSt19__throw_logic_errorPKc> + +01003974 <_ZNSsC2IPcEET_S1_RKSaIcE>: + 1003974: defffe04 addi sp,sp,-8 + 1003978: dc400015 stw r17,0(sp) + 100397c: 2023883a mov r17,r4 + 1003980: 2809883a mov r4,r5 + 1003984: 300b883a mov r5,r6 + 1003988: 380d883a mov r6,r7 + 100398c: dfc00115 stw ra,4(sp) + 1003990: 10038b00 call 10038b0 <_ZNSs12_S_constructIPcEES0_T_S1_RKSaIcESt20forward_iterator_tag> + 1003994: 88800015 stw r2,0(r17) + 1003998: dfc00117 ldw ra,4(sp) + 100399c: dc400017 ldw r17,0(sp) + 10039a0: dec00204 addi sp,sp,8 + 10039a4: f800283a ret + +010039a8 <_ZNSsC1ERKSsmmRKSaIcE>: + 10039a8: 29400017 ldw r5,0(r5) + 10039ac: defffe04 addi sp,sp,-8 + 10039b0: dc000015 stw r16,0(sp) + 10039b4: 28bffd17 ldw r2,-12(r5) + 10039b8: dfc00115 stw ra,4(sp) + 10039bc: 2021883a mov r16,r4 + 10039c0: 11800e36 bltu r2,r6,10039fc <_ZNSsC1ERKSsmmRKSaIcE+0x54> + 10039c4: 1185c83a sub r2,r2,r6 + 10039c8: 2989883a add r4,r5,r6 + 10039cc: 11c00936 bltu r2,r7,10039f4 <_ZNSsC1ERKSsmmRKSaIcE+0x4c> + 10039d0: 29cb883a add r5,r5,r7 + 10039d4: 314b883a add r5,r6,r5 + 10039d8: d9800217 ldw r6,8(sp) + 10039dc: 10038b00 call 10038b0 <_ZNSs12_S_constructIPcEES0_T_S1_RKSaIcESt20forward_iterator_tag> + 10039e0: 80800015 stw r2,0(r16) + 10039e4: dfc00117 ldw ra,4(sp) + 10039e8: dc000017 ldw r16,0(sp) + 10039ec: dec00204 addi sp,sp,8 + 10039f0: f800283a ret + 10039f4: 100f883a mov r7,r2 + 10039f8: 003ff506 br 10039d0 <_ZNSsC1ERKSsmmRKSaIcE+0x28> + 10039fc: 010040b4 movhi r4,258 + 1003a00: 21040004 addi r4,r4,4096 + 1003a04: 10084dc0 call 10084dc <_ZSt20__throw_out_of_rangePKc> + +01003a08 <_ZNSsC2ERKSsmmRKSaIcE>: + 1003a08: 29400017 ldw r5,0(r5) + 1003a0c: defffe04 addi sp,sp,-8 + 1003a10: dc000015 stw r16,0(sp) + 1003a14: 28bffd17 ldw r2,-12(r5) + 1003a18: dfc00115 stw ra,4(sp) + 1003a1c: 2021883a mov r16,r4 + 1003a20: 11800e36 bltu r2,r6,1003a5c <_ZNSsC2ERKSsmmRKSaIcE+0x54> + 1003a24: 1185c83a sub r2,r2,r6 + 1003a28: 2989883a add r4,r5,r6 + 1003a2c: 11c00936 bltu r2,r7,1003a54 <_ZNSsC2ERKSsmmRKSaIcE+0x4c> + 1003a30: 29cb883a add r5,r5,r7 + 1003a34: 314b883a add r5,r6,r5 + 1003a38: d9800217 ldw r6,8(sp) + 1003a3c: 10038b00 call 10038b0 <_ZNSs12_S_constructIPcEES0_T_S1_RKSaIcESt20forward_iterator_tag> + 1003a40: 80800015 stw r2,0(r16) + 1003a44: dfc00117 ldw ra,4(sp) + 1003a48: dc000017 ldw r16,0(sp) + 1003a4c: dec00204 addi sp,sp,8 + 1003a50: f800283a ret + 1003a54: 100f883a mov r7,r2 + 1003a58: 003ff506 br 1003a30 <_ZNSsC2ERKSsmmRKSaIcE+0x28> + 1003a5c: 010040b4 movhi r4,258 + 1003a60: 21040004 addi r4,r4,4096 + 1003a64: 10084dc0 call 10084dc <_ZSt20__throw_out_of_rangePKc> + +01003a68 <_ZNSsC1ERKSsmm>: + 1003a68: deffea04 addi sp,sp,-88 + 1003a6c: 00804034 movhi r2,256 + 1003a70: 109a9704 addi r2,r2,27228 + 1003a74: 00c040b4 movhi r3,258 + 1003a78: 18c2d844 addi r3,r3,2913 + 1003a7c: d8800715 stw r2,28(sp) + 1003a80: d9000f15 stw r4,60(sp) + 1003a84: 00804034 movhi r2,256 + 1003a88: 108ed104 addi r2,r2,15172 + 1003a8c: d9000104 addi r4,sp,4 + 1003a90: d8c00815 stw r3,32(sp) + 1003a94: d8800a15 stw r2,40(sp) + 1003a98: d9401015 stw r5,64(sp) + 1003a9c: dfc01515 stw ra,84(sp) + 1003aa0: df001415 stw fp,80(sp) + 1003aa4: ddc01315 stw r23,76(sp) + 1003aa8: dec00915 stw sp,36(sp) + 1003aac: dec00b15 stw sp,44(sp) + 1003ab0: d9801115 stw r6,68(sp) + 1003ab4: d9c01215 stw r7,72(sp) + 1003ab8: 1009c1c0 call 1009c1c <_Unwind_SjLj_Register> + 1003abc: d8801017 ldw r2,64(sp) + 1003ac0: d8c01117 ldw r3,68(sp) + 1003ac4: 11400017 ldw r5,0(r2) + 1003ac8: 28bffd17 ldw r2,-12(r5) + 1003acc: 10c01836 bltu r2,r3,1003b30 <_ZNSsC1ERKSsmm+0xc8> + 1003ad0: d8c01117 ldw r3,68(sp) + 1003ad4: d9c01217 ldw r7,72(sp) + 1003ad8: 10c5c83a sub r2,r2,r3 + 1003adc: 28c9883a add r4,r5,r3 + 1003ae0: 11c01136 bltu r2,r7,1003b28 <_ZNSsC1ERKSsmm+0xc0> + 1003ae4: 00800044 movi r2,1 + 1003ae8: d8800215 stw r2,8(sp) + 1003aec: d8801117 ldw r2,68(sp) + 1003af0: 29cb883a add r5,r5,r7 + 1003af4: d80d883a mov r6,sp + 1003af8: 114b883a add r5,r2,r5 + 1003afc: d9c00e03 ldbu r7,56(sp) + 1003b00: 10038b00 call 10038b0 <_ZNSs12_S_constructIPcEES0_T_S1_RKSaIcESt20forward_iterator_tag> + 1003b04: d8c00f17 ldw r3,60(sp) + 1003b08: d9000104 addi r4,sp,4 + 1003b0c: 18800015 stw r2,0(r3) + 1003b10: 1009c2c0 call 1009c2c <_Unwind_SjLj_Unregister> + 1003b14: dfc01517 ldw ra,84(sp) + 1003b18: df001417 ldw fp,80(sp) + 1003b1c: ddc01317 ldw r23,76(sp) + 1003b20: dec01604 addi sp,sp,88 + 1003b24: f800283a ret + 1003b28: 100f883a mov r7,r2 + 1003b2c: 003fed06 br 1003ae4 <_ZNSsC1ERKSsmm+0x7c> + 1003b30: 00bfffc4 movi r2,-1 + 1003b34: 010040b4 movhi r4,258 + 1003b38: 21040004 addi r4,r4,4096 + 1003b3c: d8800215 stw r2,8(sp) + 1003b40: 10084dc0 call 10084dc <_ZSt20__throw_out_of_rangePKc> + 1003b44: d9000317 ldw r4,12(sp) + 1003b48: 00bfffc4 movi r2,-1 + 1003b4c: d8800215 stw r2,8(sp) + 1003b50: 1009ee80 call 1009ee8 <_Unwind_SjLj_Resume> + +01003b54 <_ZNKSs6substrEmm>: + 1003b54: 28c00017 ldw r3,0(r5) + 1003b58: defffe04 addi sp,sp,-8 + 1003b5c: dc000015 stw r16,0(sp) + 1003b60: 18bffd17 ldw r2,-12(r3) + 1003b64: dfc00115 stw ra,4(sp) + 1003b68: 2021883a mov r16,r4 + 1003b6c: 11800636 bltu r2,r6,1003b88 <_ZNKSs6substrEmm+0x34> + 1003b70: 1003a680 call 1003a68 <_ZNSsC1ERKSsmm> + 1003b74: 8005883a mov r2,r16 + 1003b78: dfc00117 ldw ra,4(sp) + 1003b7c: dc000017 ldw r16,0(sp) + 1003b80: dec00204 addi sp,sp,8 + 1003b84: f800283a ret + 1003b88: 010040b4 movhi r4,258 + 1003b8c: 21040704 addi r4,r4,4124 + 1003b90: 10084dc0 call 10084dc <_ZSt20__throw_out_of_rangePKc> + +01003b94 <_ZNSsC2ERKSsmm>: + 1003b94: deffea04 addi sp,sp,-88 + 1003b98: 00804034 movhi r2,256 + 1003b9c: 109a9704 addi r2,r2,27228 + 1003ba0: 00c040b4 movhi r3,258 + 1003ba4: 18c2d9c4 addi r3,r3,2919 + 1003ba8: d8800715 stw r2,28(sp) + 1003bac: d9000f15 stw r4,60(sp) + 1003bb0: 00804034 movhi r2,256 + 1003bb4: 108f1c04 addi r2,r2,15472 + 1003bb8: d9000104 addi r4,sp,4 + 1003bbc: d8c00815 stw r3,32(sp) + 1003bc0: d8800a15 stw r2,40(sp) + 1003bc4: d9401015 stw r5,64(sp) + 1003bc8: dfc01515 stw ra,84(sp) + 1003bcc: df001415 stw fp,80(sp) + 1003bd0: ddc01315 stw r23,76(sp) + 1003bd4: dec00915 stw sp,36(sp) + 1003bd8: dec00b15 stw sp,44(sp) + 1003bdc: d9801115 stw r6,68(sp) + 1003be0: d9c01215 stw r7,72(sp) + 1003be4: 1009c1c0 call 1009c1c <_Unwind_SjLj_Register> + 1003be8: d8801017 ldw r2,64(sp) + 1003bec: d8c01117 ldw r3,68(sp) + 1003bf0: 11400017 ldw r5,0(r2) + 1003bf4: 28bffd17 ldw r2,-12(r5) + 1003bf8: 10c01836 bltu r2,r3,1003c5c <_ZNSsC2ERKSsmm+0xc8> + 1003bfc: d8c01117 ldw r3,68(sp) + 1003c00: d9c01217 ldw r7,72(sp) + 1003c04: 10c5c83a sub r2,r2,r3 + 1003c08: 28c9883a add r4,r5,r3 + 1003c0c: 11c01136 bltu r2,r7,1003c54 <_ZNSsC2ERKSsmm+0xc0> + 1003c10: 00800044 movi r2,1 + 1003c14: d8800215 stw r2,8(sp) + 1003c18: d8801117 ldw r2,68(sp) + 1003c1c: 29cb883a add r5,r5,r7 + 1003c20: d80d883a mov r6,sp + 1003c24: 114b883a add r5,r2,r5 + 1003c28: d9c00e03 ldbu r7,56(sp) + 1003c2c: 10038b00 call 10038b0 <_ZNSs12_S_constructIPcEES0_T_S1_RKSaIcESt20forward_iterator_tag> + 1003c30: d8c00f17 ldw r3,60(sp) + 1003c34: d9000104 addi r4,sp,4 + 1003c38: 18800015 stw r2,0(r3) + 1003c3c: 1009c2c0 call 1009c2c <_Unwind_SjLj_Unregister> + 1003c40: dfc01517 ldw ra,84(sp) + 1003c44: df001417 ldw fp,80(sp) + 1003c48: ddc01317 ldw r23,76(sp) + 1003c4c: dec01604 addi sp,sp,88 + 1003c50: f800283a ret + 1003c54: 100f883a mov r7,r2 + 1003c58: 003fed06 br 1003c10 <_ZNSsC2ERKSsmm+0x7c> + 1003c5c: 00bfffc4 movi r2,-1 + 1003c60: 010040b4 movhi r4,258 + 1003c64: 21040004 addi r4,r4,4096 + 1003c68: d8800215 stw r2,8(sp) + 1003c6c: 10084dc0 call 10084dc <_ZSt20__throw_out_of_rangePKc> + 1003c70: d9000317 ldw r4,12(sp) + 1003c74: 00bfffc4 movi r2,-1 + 1003c78: d8800215 stw r2,8(sp) + 1003c7c: 1009ee80 call 1009ee8 <_Unwind_SjLj_Resume> + +01003c80 <_ZNSsC1IPcEET_S1_RKSaIcE>: + 1003c80: defffe04 addi sp,sp,-8 + 1003c84: dc400015 stw r17,0(sp) + 1003c88: 2023883a mov r17,r4 + 1003c8c: 2809883a mov r4,r5 + 1003c90: 300b883a mov r5,r6 + 1003c94: 380d883a mov r6,r7 + 1003c98: dfc00115 stw ra,4(sp) + 1003c9c: 10038b00 call 10038b0 <_ZNSs12_S_constructIPcEES0_T_S1_RKSaIcESt20forward_iterator_tag> + 1003ca0: 88800015 stw r2,0(r17) + 1003ca4: dfc00117 ldw ra,4(sp) + 1003ca8: dc400017 ldw r17,0(sp) + 1003cac: dec00204 addi sp,sp,8 + 1003cb0: f800283a ret + +01003cb4 <_ZNSs13_S_copy_charsEPcN9__gnu_cxx17__normal_iteratorIS_SsEES2_>: + 1003cb4: 3147c83a sub r3,r6,r5 + 1003cb8: 00800044 movi r2,1 + 1003cbc: 180d883a mov r6,r3 + 1003cc0: 18800126 beq r3,r2,1003cc8 <_ZNSs13_S_copy_charsEPcN9__gnu_cxx17__normal_iteratorIS_SsEES2_+0x14> + 1003cc4: 100aa3c1 jmpi 100aa3c + 1003cc8: 28800003 ldbu r2,0(r5) + 1003ccc: 20800005 stb r2,0(r4) + 1003cd0: f800283a ret + +01003cd4 <_ZNSs12_S_constructIPKcEEPcT_S3_RKSaIcESt20forward_iterator_tag>: + 1003cd4: defffb04 addi sp,sp,-20 + 1003cd8: dc000015 stw r16,0(sp) + 1003cdc: dfc00415 stw ra,16(sp) + 1003ce0: dcc00315 stw r19,12(sp) + 1003ce4: dc800215 stw r18,8(sp) + 1003ce8: dc400115 stw r17,4(sp) + 1003cec: 2021883a mov r16,r4 + 1003cf0: 21401c26 beq r4,r5,1003d64 <_ZNSs12_S_constructIPKcEEPcT_S3_RKSaIcESt20forward_iterator_tag+0x90> + 1003cf4: 20002526 beq r4,zero,1003d8c <_ZNSs12_S_constructIPKcEEPcT_S3_RKSaIcESt20forward_iterator_tag+0xb8> + 1003cf8: 2c25c83a sub r18,r5,r16 + 1003cfc: 9009883a mov r4,r18 + 1003d00: 000b883a mov r5,zero + 1003d04: 1002adc0 call 1002adc <_ZNSs4_Rep9_S_createEmmRKSaIcE> + 1003d08: 1023883a mov r17,r2 + 1003d0c: 14c00304 addi r19,r2,12 + 1003d10: 00800044 movi r2,1 + 1003d14: 90801026 beq r18,r2,1003d58 <_ZNSs12_S_constructIPKcEEPcT_S3_RKSaIcESt20forward_iterator_tag+0x84> + 1003d18: 800b883a mov r5,r16 + 1003d1c: 9809883a mov r4,r19 + 1003d20: 900d883a mov r6,r18 + 1003d24: 100aa3c0 call 100aa3c + 1003d28: 9c85883a add r2,r19,r18 + 1003d2c: 8c800015 stw r18,0(r17) + 1003d30: 88000215 stw zero,8(r17) + 1003d34: 10000005 stb zero,0(r2) + 1003d38: 9805883a mov r2,r19 + 1003d3c: dfc00417 ldw ra,16(sp) + 1003d40: dcc00317 ldw r19,12(sp) + 1003d44: dc800217 ldw r18,8(sp) + 1003d48: dc400117 ldw r17,4(sp) + 1003d4c: dc000017 ldw r16,0(sp) + 1003d50: dec00504 addi sp,sp,20 + 1003d54: f800283a ret + 1003d58: 80800003 ldbu r2,0(r16) + 1003d5c: 88800305 stb r2,12(r17) + 1003d60: 003ff106 br 1003d28 <_ZNSs12_S_constructIPKcEEPcT_S3_RKSaIcESt20forward_iterator_tag+0x54> + 1003d64: 04c040f4 movhi r19,259 + 1003d68: 9ce53204 addi r19,r19,-27448 + 1003d6c: 9805883a mov r2,r19 + 1003d70: dfc00417 ldw ra,16(sp) + 1003d74: dcc00317 ldw r19,12(sp) + 1003d78: dc800217 ldw r18,8(sp) + 1003d7c: dc400117 ldw r17,4(sp) + 1003d80: dc000017 ldw r16,0(sp) + 1003d84: dec00504 addi sp,sp,20 + 1003d88: f800283a ret + 1003d8c: 010040b4 movhi r4,258 + 1003d90: 2103f504 addi r4,r4,4052 + 1003d94: 10079ec0 call 10079ec <_ZSt19__throw_logic_errorPKc> + +01003d98 <_ZNSsC2IPKcEET_S2_RKSaIcE>: + 1003d98: defffe04 addi sp,sp,-8 + 1003d9c: dc400015 stw r17,0(sp) + 1003da0: 2023883a mov r17,r4 + 1003da4: 2809883a mov r4,r5 + 1003da8: 300b883a mov r5,r6 + 1003dac: 380d883a mov r6,r7 + 1003db0: dfc00115 stw ra,4(sp) + 1003db4: 1003cd40 call 1003cd4 <_ZNSs12_S_constructIPKcEEPcT_S3_RKSaIcESt20forward_iterator_tag> + 1003db8: 88800015 stw r2,0(r17) + 1003dbc: dfc00117 ldw ra,4(sp) + 1003dc0: dc400017 ldw r17,0(sp) + 1003dc4: dec00204 addi sp,sp,8 + 1003dc8: f800283a ret + +01003dcc <_ZNSsC1EPKcmRKSaIcE>: + 1003dcc: defffe04 addi sp,sp,-8 + 1003dd0: dc400015 stw r17,0(sp) + 1003dd4: 2023883a mov r17,r4 + 1003dd8: 2809883a mov r4,r5 + 1003ddc: 314b883a add r5,r6,r5 + 1003de0: 380d883a mov r6,r7 + 1003de4: dfc00115 stw ra,4(sp) + 1003de8: 1003cd40 call 1003cd4 <_ZNSs12_S_constructIPKcEEPcT_S3_RKSaIcESt20forward_iterator_tag> + 1003dec: 88800015 stw r2,0(r17) + 1003df0: dfc00117 ldw ra,4(sp) + 1003df4: dc400017 ldw r17,0(sp) + 1003df8: dec00204 addi sp,sp,8 + 1003dfc: f800283a ret + +01003e00 <_ZNSsC2EPKcmRKSaIcE>: + 1003e00: defffe04 addi sp,sp,-8 + 1003e04: dc400015 stw r17,0(sp) + 1003e08: 2023883a mov r17,r4 + 1003e0c: 2809883a mov r4,r5 + 1003e10: 314b883a add r5,r6,r5 + 1003e14: 380d883a mov r6,r7 + 1003e18: dfc00115 stw ra,4(sp) + 1003e1c: 1003cd40 call 1003cd4 <_ZNSs12_S_constructIPKcEEPcT_S3_RKSaIcESt20forward_iterator_tag> + 1003e20: 88800015 stw r2,0(r17) + 1003e24: dfc00117 ldw ra,4(sp) + 1003e28: dc400017 ldw r17,0(sp) + 1003e2c: dec00204 addi sp,sp,8 + 1003e30: f800283a ret + +01003e34 <_ZNSsC1IPKcEET_S2_RKSaIcE>: + 1003e34: defffe04 addi sp,sp,-8 + 1003e38: dc400015 stw r17,0(sp) + 1003e3c: 2023883a mov r17,r4 + 1003e40: 2809883a mov r4,r5 + 1003e44: 300b883a mov r5,r6 + 1003e48: 380d883a mov r6,r7 + 1003e4c: dfc00115 stw ra,4(sp) + 1003e50: 1003cd40 call 1003cd4 <_ZNSs12_S_constructIPKcEEPcT_S3_RKSaIcESt20forward_iterator_tag> + 1003e54: 88800015 stw r2,0(r17) + 1003e58: dfc00117 ldw ra,4(sp) + 1003e5c: dc400017 ldw r17,0(sp) + 1003e60: dec00204 addi sp,sp,8 + 1003e64: f800283a ret + +01003e68 <_ZNSsC1EPKcRKSaIcE>: + 1003e68: defffc04 addi sp,sp,-16 + 1003e6c: dc400215 stw r17,8(sp) + 1003e70: dc000115 stw r16,4(sp) + 1003e74: 2023883a mov r17,r4 + 1003e78: dfc00315 stw ra,12(sp) + 1003e7c: 00bfffc4 movi r2,-1 + 1003e80: 2809883a mov r4,r5 + 1003e84: 3021883a mov r16,r6 + 1003e88: 28000426 beq r5,zero,1003e9c <_ZNSsC1EPKcRKSaIcE+0x34> + 1003e8c: d9400015 stw r5,0(sp) + 1003e90: 100b1640 call 100b164 + 1003e94: d9400017 ldw r5,0(sp) + 1003e98: 2885883a add r2,r5,r2 + 1003e9c: 2809883a mov r4,r5 + 1003ea0: 800d883a mov r6,r16 + 1003ea4: 100b883a mov r5,r2 + 1003ea8: 800f883a mov r7,r16 + 1003eac: 1003cd40 call 1003cd4 <_ZNSs12_S_constructIPKcEEPcT_S3_RKSaIcESt20forward_iterator_tag> + 1003eb0: 88800015 stw r2,0(r17) + 1003eb4: dfc00317 ldw ra,12(sp) + 1003eb8: dc400217 ldw r17,8(sp) + 1003ebc: dc000117 ldw r16,4(sp) + 1003ec0: dec00404 addi sp,sp,16 + 1003ec4: f800283a ret + +01003ec8 <_ZNSsC2EPKcRKSaIcE>: + 1003ec8: defffc04 addi sp,sp,-16 + 1003ecc: dc400215 stw r17,8(sp) + 1003ed0: dc000115 stw r16,4(sp) + 1003ed4: 2023883a mov r17,r4 + 1003ed8: dfc00315 stw ra,12(sp) + 1003edc: 00bfffc4 movi r2,-1 + 1003ee0: 2809883a mov r4,r5 + 1003ee4: 3021883a mov r16,r6 + 1003ee8: 28000426 beq r5,zero,1003efc <_ZNSsC2EPKcRKSaIcE+0x34> + 1003eec: d9400015 stw r5,0(sp) + 1003ef0: 100b1640 call 100b164 + 1003ef4: d9400017 ldw r5,0(sp) + 1003ef8: 2885883a add r2,r5,r2 + 1003efc: 2809883a mov r4,r5 + 1003f00: 800d883a mov r6,r16 + 1003f04: 100b883a mov r5,r2 + 1003f08: 800f883a mov r7,r16 + 1003f0c: 1003cd40 call 1003cd4 <_ZNSs12_S_constructIPKcEEPcT_S3_RKSaIcESt20forward_iterator_tag> + 1003f10: 88800015 stw r2,0(r17) + 1003f14: dfc00317 ldw ra,12(sp) + 1003f18: dc400217 ldw r17,8(sp) + 1003f1c: dc000117 ldw r16,4(sp) + 1003f20: dec00404 addi sp,sp,16 + 1003f24: f800283a ret + +01003f28 <_ZNSs13_S_copy_charsEPcN9__gnu_cxx17__normal_iteratorIPKcSsEES4_>: + 1003f28: 3147c83a sub r3,r6,r5 + 1003f2c: 00800044 movi r2,1 + 1003f30: 180d883a mov r6,r3 + 1003f34: 18800126 beq r3,r2,1003f3c <_ZNSs13_S_copy_charsEPcN9__gnu_cxx17__normal_iteratorIPKcSsEES4_+0x14> + 1003f38: 100aa3c1 jmpi 100aa3c + 1003f3c: 28800003 ldbu r2,0(r5) + 1003f40: 20800005 stb r2,0(r4) + 1003f44: f800283a ret + +01003f48 <_ZNSs12_S_constructIN9__gnu_cxx17__normal_iteratorIPcSsEEEES2_T_S4_RKSaIcESt20forward_iterator_tag>: + 1003f48: defffb04 addi sp,sp,-20 + 1003f4c: dc000015 stw r16,0(sp) + 1003f50: dfc00415 stw ra,16(sp) + 1003f54: dcc00315 stw r19,12(sp) + 1003f58: dc800215 stw r18,8(sp) + 1003f5c: dc400115 stw r17,4(sp) + 1003f60: 2021883a mov r16,r4 + 1003f64: 29000a1e bne r5,r4,1003f90 <_ZNSs12_S_constructIN9__gnu_cxx17__normal_iteratorIPcSsEEEES2_T_S4_RKSaIcESt20forward_iterator_tag+0x48> + 1003f68: 04c040f4 movhi r19,259 + 1003f6c: 9ce53204 addi r19,r19,-27448 + 1003f70: 9805883a mov r2,r19 + 1003f74: dfc00417 ldw ra,16(sp) + 1003f78: dcc00317 ldw r19,12(sp) + 1003f7c: dc800217 ldw r18,8(sp) + 1003f80: dc400117 ldw r17,4(sp) + 1003f84: dc000017 ldw r16,0(sp) + 1003f88: dec00504 addi sp,sp,20 + 1003f8c: f800283a ret + 1003f90: 2923c83a sub r17,r5,r4 + 1003f94: 8809883a mov r4,r17 + 1003f98: 000b883a mov r5,zero + 1003f9c: 1002adc0 call 1002adc <_ZNSs4_Rep9_S_createEmmRKSaIcE> + 1003fa0: 1025883a mov r18,r2 + 1003fa4: 14c00304 addi r19,r2,12 + 1003fa8: 00800044 movi r2,1 + 1003fac: 88801026 beq r17,r2,1003ff0 <_ZNSs12_S_constructIN9__gnu_cxx17__normal_iteratorIPcSsEEEES2_T_S4_RKSaIcESt20forward_iterator_tag+0xa8> + 1003fb0: 800b883a mov r5,r16 + 1003fb4: 9809883a mov r4,r19 + 1003fb8: 880d883a mov r6,r17 + 1003fbc: 100aa3c0 call 100aa3c + 1003fc0: 9c45883a add r2,r19,r17 + 1003fc4: 94400015 stw r17,0(r18) + 1003fc8: 90000215 stw zero,8(r18) + 1003fcc: 10000005 stb zero,0(r2) + 1003fd0: 9805883a mov r2,r19 + 1003fd4: dfc00417 ldw ra,16(sp) + 1003fd8: dcc00317 ldw r19,12(sp) + 1003fdc: dc800217 ldw r18,8(sp) + 1003fe0: dc400117 ldw r17,4(sp) + 1003fe4: dc000017 ldw r16,0(sp) + 1003fe8: dec00504 addi sp,sp,20 + 1003fec: f800283a ret + 1003ff0: 80800003 ldbu r2,0(r16) + 1003ff4: 98800005 stb r2,0(r19) + 1003ff8: 003ff106 br 1003fc0 <_ZNSs12_S_constructIN9__gnu_cxx17__normal_iteratorIPcSsEEEES2_T_S4_RKSaIcESt20forward_iterator_tag+0x78> + +01003ffc <_ZNSsC2IN9__gnu_cxx17__normal_iteratorIPcSsEEEET_S4_RKSaIcE>: + 1003ffc: defffe04 addi sp,sp,-8 + 1004000: dc400015 stw r17,0(sp) + 1004004: 2023883a mov r17,r4 + 1004008: 2809883a mov r4,r5 + 100400c: 300b883a mov r5,r6 + 1004010: 380d883a mov r6,r7 + 1004014: dfc00115 stw ra,4(sp) + 1004018: 1003f480 call 1003f48 <_ZNSs12_S_constructIN9__gnu_cxx17__normal_iteratorIPcSsEEEES2_T_S4_RKSaIcESt20forward_iterator_tag> + 100401c: 88800015 stw r2,0(r17) + 1004020: dfc00117 ldw ra,4(sp) + 1004024: dc400017 ldw r17,0(sp) + 1004028: dec00204 addi sp,sp,8 + 100402c: f800283a ret + +01004030 <_ZNSsC1IN9__gnu_cxx17__normal_iteratorIPcSsEEEET_S4_RKSaIcE>: + 1004030: defffe04 addi sp,sp,-8 + 1004034: dc400015 stw r17,0(sp) + 1004038: 2023883a mov r17,r4 + 100403c: 2809883a mov r4,r5 + 1004040: 300b883a mov r5,r6 + 1004044: 380d883a mov r6,r7 + 1004048: dfc00115 stw ra,4(sp) + 100404c: 1003f480 call 1003f48 <_ZNSs12_S_constructIN9__gnu_cxx17__normal_iteratorIPcSsEEEES2_T_S4_RKSaIcESt20forward_iterator_tag> + 1004050: 88800015 stw r2,0(r17) + 1004054: dfc00117 ldw ra,4(sp) + 1004058: dc400017 ldw r17,0(sp) + 100405c: dec00204 addi sp,sp,8 + 1004060: f800283a ret + +01004064 <_ZNSsC1ERKSs>: + 1004064: deffec04 addi sp,sp,-80 + 1004068: 00804034 movhi r2,256 + 100406c: 109a9704 addi r2,r2,27228 + 1004070: d8800715 stw r2,28(sp) + 1004074: 00c040b4 movhi r3,258 + 1004078: 18c2dc04 addi r3,r3,2928 + 100407c: 00804034 movhi r2,256 + 1004080: 10904a04 addi r2,r2,16680 + 1004084: d9000e15 stw r4,56(sp) + 1004088: d9000104 addi r4,sp,4 + 100408c: d8800a15 stw r2,40(sp) + 1004090: dfc01315 stw ra,76(sp) + 1004094: df001215 stw fp,72(sp) + 1004098: ddc01115 stw r23,68(sp) + 100409c: d8c00815 stw r3,32(sp) + 10040a0: d9400f15 stw r5,60(sp) + 10040a4: dec00915 stw sp,36(sp) + 10040a8: dec00b15 stw sp,44(sp) + 10040ac: 1009c1c0 call 1009c1c <_Unwind_SjLj_Register> + 10040b0: d8800f17 ldw r2,60(sp) + 10040b4: 10800017 ldw r2,0(r2) + 10040b8: 113ffd04 addi r4,r2,-12 + 10040bc: d8801015 stw r2,64(sp) + 10040c0: 20800217 ldw r2,8(r4) + 10040c4: 10000d16 blt r2,zero,10040fc <_ZNSsC1ERKSs+0x98> + 10040c8: 008040f4 movhi r2,259 + 10040cc: 10a52f04 addi r2,r2,-27460 + 10040d0: 2080101e bne r4,r2,1004114 <_ZNSsC1ERKSs+0xb0> + 10040d4: d8801017 ldw r2,64(sp) + 10040d8: d8c00e17 ldw r3,56(sp) + 10040dc: d9000104 addi r4,sp,4 + 10040e0: 18800015 stw r2,0(r3) + 10040e4: 1009c2c0 call 1009c2c <_Unwind_SjLj_Unregister> + 10040e8: dfc01317 ldw ra,76(sp) + 10040ec: df001217 ldw fp,72(sp) + 10040f0: ddc01117 ldw r23,68(sp) + 10040f4: dec01404 addi sp,sp,80 + 10040f8: f800283a ret + 10040fc: 00800084 movi r2,2 + 1004100: d8800215 stw r2,8(sp) + 1004104: d80b883a mov r5,sp + 1004108: 000d883a mov r6,zero + 100410c: 10036480 call 1003648 <_ZNSs4_Rep8_M_cloneERKSaIcEm> + 1004110: 003ff106 br 10040d8 <_ZNSsC1ERKSs+0x74> + 1004114: 01400044 movi r5,1 + 1004118: d9400215 stw r5,8(sp) + 100411c: 21000204 addi r4,r4,8 + 1004120: 10061900 call 1006190 <_ZN9__gnu_cxx12__atomic_addEPVii> + 1004124: 003feb06 br 10040d4 <_ZNSsC1ERKSs+0x70> + 1004128: d8c00217 ldw r3,8(sp) + 100412c: 00800044 movi r2,1 + 1004130: d9000317 ldw r4,12(sp) + 1004134: d9400417 ldw r5,16(sp) + 1004138: 18800426 beq r3,r2,100414c <_ZNSsC1ERKSs+0xe8> + 100413c: 00bfffc4 movi r2,-1 + 1004140: 28800426 beq r5,r2,1004154 <_ZNSsC1ERKSs+0xf0> + 1004144: d8800215 stw r2,8(sp) + 1004148: 1009ee80 call 1009ee8 <_Unwind_SjLj_Resume> + 100414c: 00bfffc4 movi r2,-1 + 1004150: 003ffc06 br 1004144 <_ZNSsC1ERKSs+0xe0> + 1004154: 00bfffc4 movi r2,-1 + 1004158: d8800215 stw r2,8(sp) + 100415c: 10068dc0 call 10068dc <__cxa_call_unexpected> + +01004160 <_ZNSsC2ERKSs>: + 1004160: deffec04 addi sp,sp,-80 + 1004164: 00804034 movhi r2,256 + 1004168: 109a9704 addi r2,r2,27228 + 100416c: d8800715 stw r2,28(sp) + 1004170: 00c040b4 movhi r3,258 + 1004174: 18c2e004 addi r3,r3,2944 + 1004178: 00804034 movhi r2,256 + 100417c: 10908904 addi r2,r2,16932 + 1004180: d9000e15 stw r4,56(sp) + 1004184: d9000104 addi r4,sp,4 + 1004188: d8800a15 stw r2,40(sp) + 100418c: dfc01315 stw ra,76(sp) + 1004190: df001215 stw fp,72(sp) + 1004194: ddc01115 stw r23,68(sp) + 1004198: d8c00815 stw r3,32(sp) + 100419c: d9400f15 stw r5,60(sp) + 10041a0: dec00915 stw sp,36(sp) + 10041a4: dec00b15 stw sp,44(sp) + 10041a8: 1009c1c0 call 1009c1c <_Unwind_SjLj_Register> + 10041ac: d8800f17 ldw r2,60(sp) + 10041b0: 10800017 ldw r2,0(r2) + 10041b4: 113ffd04 addi r4,r2,-12 + 10041b8: d8801015 stw r2,64(sp) + 10041bc: 20800217 ldw r2,8(r4) + 10041c0: 10000d16 blt r2,zero,10041f8 <_ZNSsC2ERKSs+0x98> + 10041c4: 008040f4 movhi r2,259 + 10041c8: 10a52f04 addi r2,r2,-27460 + 10041cc: 2080101e bne r4,r2,1004210 <_ZNSsC2ERKSs+0xb0> + 10041d0: d8801017 ldw r2,64(sp) + 10041d4: d8c00e17 ldw r3,56(sp) + 10041d8: d9000104 addi r4,sp,4 + 10041dc: 18800015 stw r2,0(r3) + 10041e0: 1009c2c0 call 1009c2c <_Unwind_SjLj_Unregister> + 10041e4: dfc01317 ldw ra,76(sp) + 10041e8: df001217 ldw fp,72(sp) + 10041ec: ddc01117 ldw r23,68(sp) + 10041f0: dec01404 addi sp,sp,80 + 10041f4: f800283a ret + 10041f8: 00800084 movi r2,2 + 10041fc: d8800215 stw r2,8(sp) + 1004200: d80b883a mov r5,sp + 1004204: 000d883a mov r6,zero + 1004208: 10036480 call 1003648 <_ZNSs4_Rep8_M_cloneERKSaIcEm> + 100420c: 003ff106 br 10041d4 <_ZNSsC2ERKSs+0x74> + 1004210: 01400044 movi r5,1 + 1004214: d9400215 stw r5,8(sp) + 1004218: 21000204 addi r4,r4,8 + 100421c: 10061900 call 1006190 <_ZN9__gnu_cxx12__atomic_addEPVii> + 1004220: 003feb06 br 10041d0 <_ZNSsC2ERKSs+0x70> + 1004224: d8c00217 ldw r3,8(sp) + 1004228: 00800044 movi r2,1 + 100422c: d9000317 ldw r4,12(sp) + 1004230: d9400417 ldw r5,16(sp) + 1004234: 18800426 beq r3,r2,1004248 <_ZNSsC2ERKSs+0xe8> + 1004238: 00bfffc4 movi r2,-1 + 100423c: 28800426 beq r5,r2,1004250 <_ZNSsC2ERKSs+0xf0> + 1004240: d8800215 stw r2,8(sp) + 1004244: 1009ee80 call 1009ee8 <_Unwind_SjLj_Resume> + 1004248: 00bfffc4 movi r2,-1 + 100424c: 003ffc06 br 1004240 <_ZNSsC2ERKSs+0xe0> + 1004250: 00bfffc4 movi r2,-1 + 1004254: d8800215 stw r2,8(sp) + 1004258: 10068dc0 call 10068dc <__cxa_call_unexpected> + +0100425c <_ZNSs6assignERKSs>: + 100425c: deffea04 addi sp,sp,-88 + 1004260: 00804034 movhi r2,256 + 1004264: 109a9704 addi r2,r2,27228 + 1004268: 00c040b4 movhi r3,258 + 100426c: 18c2e404 addi r3,r3,2960 + 1004270: d8800715 stw r2,28(sp) + 1004274: d9001015 stw r4,64(sp) + 1004278: 00804034 movhi r2,256 + 100427c: 1090e404 addi r2,r2,17296 + 1004280: d9000104 addi r4,sp,4 + 1004284: d8c00815 stw r3,32(sp) + 1004288: d8800a15 stw r2,40(sp) + 100428c: d9401115 stw r5,68(sp) + 1004290: dfc01515 stw ra,84(sp) + 1004294: df001415 stw fp,80(sp) + 1004298: ddc01315 stw r23,76(sp) + 100429c: dec00915 stw sp,36(sp) + 10042a0: dec00b15 stw sp,44(sp) + 10042a4: 1009c1c0 call 1009c1c <_Unwind_SjLj_Register> + 10042a8: d8801117 ldw r2,68(sp) + 10042ac: d8c01017 ldw r3,64(sp) + 10042b0: 10800017 ldw r2,0(r2) + 10042b4: d8801215 stw r2,72(sp) + 10042b8: d9401217 ldw r5,72(sp) + 10042bc: 18800017 ldw r2,0(r3) + 10042c0: 00fffd04 movi r3,-12 + 10042c4: 28c9883a add r4,r5,r3 + 10042c8: 10c5883a add r2,r2,r3 + 10042cc: 11001126 beq r2,r4,1004314 <_ZNSs6assignERKSs+0xb8> + 10042d0: 20800217 ldw r2,8(r4) + 10042d4: 10001716 blt r2,zero,1004334 <_ZNSs6assignERKSs+0xd8> + 10042d8: 008040f4 movhi r2,259 + 10042dc: 10a52f04 addi r2,r2,-27460 + 10042e0: 2080261e bne r4,r2,100437c <_ZNSs6assignERKSs+0x120> + 10042e4: d8c01217 ldw r3,72(sp) + 10042e8: d8c00f15 stw r3,60(sp) + 10042ec: d9401017 ldw r5,64(sp) + 10042f0: 00c040f4 movhi r3,259 + 10042f4: 18e52f04 addi r3,r3,-27460 + 10042f8: 28800017 ldw r2,0(r5) + 10042fc: 10bffd04 addi r2,r2,-12 + 1004300: d8800e15 stw r2,56(sp) + 1004304: 10c0121e bne r2,r3,1004350 <_ZNSs6assignERKSs+0xf4> + 1004308: d8c00f17 ldw r3,60(sp) + 100430c: d8801017 ldw r2,64(sp) + 1004310: 10c00015 stw r3,0(r2) + 1004314: d9000104 addi r4,sp,4 + 1004318: 1009c2c0 call 1009c2c <_Unwind_SjLj_Unregister> + 100431c: d8801017 ldw r2,64(sp) + 1004320: dfc01517 ldw ra,84(sp) + 1004324: df001417 ldw fp,80(sp) + 1004328: ddc01317 ldw r23,76(sp) + 100432c: dec01604 addi sp,sp,88 + 1004330: f800283a ret + 1004334: 00800084 movi r2,2 + 1004338: d8800215 stw r2,8(sp) + 100433c: d80b883a mov r5,sp + 1004340: 000d883a mov r6,zero + 1004344: 10036480 call 1003648 <_ZNSs4_Rep8_M_cloneERKSaIcEm> + 1004348: d8800f15 stw r2,60(sp) + 100434c: 003fe706 br 10042ec <_ZNSs6assignERKSs+0x90> + 1004350: d9400e17 ldw r5,56(sp) + 1004354: 008000c4 movi r2,3 + 1004358: d8800215 stw r2,8(sp) + 100435c: 29000204 addi r4,r5,8 + 1004360: 017fffc4 movi r5,-1 + 1004364: 100617c0 call 100617c <_ZN9__gnu_cxx18__exchange_and_addEPVii> + 1004368: 00bfe716 blt zero,r2,1004308 <_ZNSs6assignERKSs+0xac> + 100436c: d9000e17 ldw r4,56(sp) + 1004370: d80b883a mov r5,sp + 1004374: 1002c0c0 call 1002c0c <_ZNSs4_Rep10_M_destroyERKSaIcE> + 1004378: 003fe306 br 1004308 <_ZNSs6assignERKSs+0xac> + 100437c: 01400044 movi r5,1 + 1004380: d9400215 stw r5,8(sp) + 1004384: 21000204 addi r4,r4,8 + 1004388: 10061900 call 1006190 <_ZN9__gnu_cxx12__atomic_addEPVii> + 100438c: 003fd506 br 10042e4 <_ZNSs6assignERKSs+0x88> + 1004390: d8c00217 ldw r3,8(sp) + 1004394: 00800044 movi r2,1 + 1004398: d9000317 ldw r4,12(sp) + 100439c: d9400417 ldw r5,16(sp) + 10043a0: 18800626 beq r3,r2,10043bc <_ZNSs6assignERKSs+0x160> + 10043a4: 00800084 movi r2,2 + 10043a8: 18800426 beq r3,r2,10043bc <_ZNSs6assignERKSs+0x160> + 10043ac: 00bfffc4 movi r2,-1 + 10043b0: 28800426 beq r5,r2,10043c4 <_ZNSs6assignERKSs+0x168> + 10043b4: d8800215 stw r2,8(sp) + 10043b8: 1009ee80 call 1009ee8 <_Unwind_SjLj_Resume> + 10043bc: 00bfffc4 movi r2,-1 + 10043c0: 003ffc06 br 10043b4 <_ZNSs6assignERKSs+0x158> + 10043c4: 00bfffc4 movi r2,-1 + 10043c8: d8800215 stw r2,8(sp) + 10043cc: 10068dc0 call 10068dc <__cxa_call_unexpected> + +010043d0 <_ZNSsaSERKSs>: + 10043d0: 100425c1 jmpi 100425c <_ZNSs6assignERKSs> + +010043d4 <_ZNSs7reserveEm>: + 10043d4: deffeb04 addi sp,sp,-84 + 10043d8: 00804034 movhi r2,256 + 10043dc: 109a9704 addi r2,r2,27228 + 10043e0: 00c040b4 movhi r3,258 + 10043e4: 18c2e844 addi r3,r3,2977 + 10043e8: d8800715 stw r2,28(sp) + 10043ec: d9001015 stw r4,64(sp) + 10043f0: 00804034 movhi r2,256 + 10043f4: 10913b04 addi r2,r2,17644 + 10043f8: d9000104 addi r4,sp,4 + 10043fc: d8c00815 stw r3,32(sp) + 1004400: d8800a15 stw r2,40(sp) + 1004404: dfc01415 stw ra,80(sp) + 1004408: df001315 stw fp,76(sp) + 100440c: ddc01215 stw r23,72(sp) + 1004410: dec00915 stw sp,36(sp) + 1004414: dec00b15 stw sp,44(sp) + 1004418: d9401115 stw r5,68(sp) + 100441c: 1009c1c0 call 1009c1c <_Unwind_SjLj_Register> + 1004420: d8801017 ldw r2,64(sp) + 1004424: 10c00017 ldw r3,0(r2) + 1004428: 193ffd04 addi r4,r3,-12 + 100442c: 20800117 ldw r2,4(r4) + 1004430: d8c01117 ldw r3,68(sp) + 1004434: 10c01c26 beq r2,r3,10044a8 <_ZNSs7reserveEm+0xd4> + 1004438: 20c00017 ldw r3,0(r4) + 100443c: d9401117 ldw r5,68(sp) + 1004440: 28c01736 bltu r5,r3,10044a0 <_ZNSs7reserveEm+0xcc> + 1004444: 00800044 movi r2,1 + 1004448: 28cdc83a sub r6,r5,r3 + 100444c: d8800215 stw r2,8(sp) + 1004450: d80b883a mov r5,sp + 1004454: 10036480 call 1003648 <_ZNSs4_Rep8_M_cloneERKSaIcEm> + 1004458: d8c01017 ldw r3,64(sp) + 100445c: d8800f15 stw r2,60(sp) + 1004460: 18800017 ldw r2,0(r3) + 1004464: 00c040f4 movhi r3,259 + 1004468: 18e52f04 addi r3,r3,-27460 + 100446c: 10bffd04 addi r2,r2,-12 + 1004470: d8800e15 stw r2,56(sp) + 1004474: 10c0151e bne r2,r3,10044cc <_ZNSs7reserveEm+0xf8> + 1004478: d8c00f17 ldw r3,60(sp) + 100447c: d8801017 ldw r2,64(sp) + 1004480: d9000104 addi r4,sp,4 + 1004484: 10c00015 stw r3,0(r2) + 1004488: 1009c2c0 call 1009c2c <_Unwind_SjLj_Unregister> + 100448c: dfc01417 ldw ra,80(sp) + 1004490: df001317 ldw fp,76(sp) + 1004494: ddc01217 ldw r23,72(sp) + 1004498: dec01504 addi sp,sp,84 + 100449c: f800283a ret + 10044a0: 180b883a mov r5,r3 + 10044a4: 003fe706 br 1004444 <_ZNSs7reserveEm+0x70> + 10044a8: 20800217 ldw r2,8(r4) + 10044ac: 00bfe216 blt zero,r2,1004438 <_ZNSs7reserveEm+0x64> + 10044b0: d9000104 addi r4,sp,4 + 10044b4: 1009c2c0 call 1009c2c <_Unwind_SjLj_Unregister> + 10044b8: dfc01417 ldw ra,80(sp) + 10044bc: df001317 ldw fp,76(sp) + 10044c0: ddc01217 ldw r23,72(sp) + 10044c4: dec01504 addi sp,sp,84 + 10044c8: f800283a ret + 10044cc: 11000204 addi r4,r2,8 + 10044d0: 017fffc4 movi r5,-1 + 10044d4: 100617c0 call 100617c <_ZN9__gnu_cxx18__exchange_and_addEPVii> + 10044d8: 00bfe716 blt zero,r2,1004478 <_ZNSs7reserveEm+0xa4> + 10044dc: d9000e17 ldw r4,56(sp) + 10044e0: d80b883a mov r5,sp + 10044e4: 1002c0c0 call 1002c0c <_ZNSs4_Rep10_M_destroyERKSaIcE> + 10044e8: 003fe306 br 1004478 <_ZNSs7reserveEm+0xa4> + 10044ec: d9000317 ldw r4,12(sp) + 10044f0: 00bfffc4 movi r2,-1 + 10044f4: d8800215 stw r2,8(sp) + 10044f8: 1009ee80 call 1009ee8 <_Unwind_SjLj_Resume> + +010044fc <_ZNSs9push_backEc>: + 10044fc: 21800017 ldw r6,0(r4) + 1004500: defffc04 addi sp,sp,-16 + 1004504: dc000015 stw r16,0(sp) + 1004508: 30bffd17 ldw r2,-12(r6) + 100450c: 31fffd04 addi r7,r6,-12 + 1004510: 38c00117 ldw r3,4(r7) + 1004514: 14000044 addi r16,r2,1 + 1004518: dc800215 stw r18,8(sp) + 100451c: dc400115 stw r17,4(sp) + 1004520: 2825883a mov r18,r5 + 1004524: dfc00315 stw ra,12(sp) + 1004528: 2023883a mov r17,r4 + 100452c: 800b883a mov r5,r16 + 1004530: 1c001136 bltu r3,r16,1004578 <_ZNSs9push_backEc+0x7c> + 1004534: 38800217 ldw r2,8(r7) + 1004538: 00800f16 blt zero,r2,1004578 <_ZNSs9push_backEc+0x7c> + 100453c: 30bffd17 ldw r2,-12(r6) + 1004540: 3085883a add r2,r6,r2 + 1004544: 14800005 stb r18,0(r2) + 1004548: 88c00017 ldw r3,0(r17) + 100454c: 18bffd04 addi r2,r3,-12 + 1004550: 1c3ffd15 stw r16,-12(r3) + 1004554: 1409883a add r4,r2,r16 + 1004558: 10000215 stw zero,8(r2) + 100455c: 20000305 stb zero,12(r4) + 1004560: dfc00317 ldw ra,12(sp) + 1004564: dc800217 ldw r18,8(sp) + 1004568: dc400117 ldw r17,4(sp) + 100456c: dc000017 ldw r16,0(sp) + 1004570: dec00404 addi sp,sp,16 + 1004574: f800283a ret + 1004578: 10043d40 call 10043d4 <_ZNSs7reserveEm> + 100457c: 89800017 ldw r6,0(r17) + 1004580: 003fee06 br 100453c <_ZNSs9push_backEc+0x40> + +01004584 <_ZNSs6appendEmc>: + 1004584: defffb04 addi sp,sp,-20 + 1004588: dcc00315 stw r19,12(sp) + 100458c: dc800215 stw r18,8(sp) + 1004590: dc000015 stw r16,0(sp) + 1004594: dfc00415 stw ra,16(sp) + 1004598: dc400115 stw r17,4(sp) + 100459c: 2821883a mov r16,r5 + 10045a0: 3027883a mov r19,r6 + 10045a4: 2025883a mov r18,r4 + 10045a8: 28001d26 beq r5,zero,1004620 <_ZNSs6appendEmc+0x9c> + 10045ac: 20c00017 ldw r3,0(r4) + 10045b0: 00900034 movhi r2,16384 + 10045b4: 10bfff04 addi r2,r2,-4 + 10045b8: 197ffd17 ldw r5,-12(r3) + 10045bc: 19bffd04 addi r6,r3,-12 + 10045c0: 1145c83a sub r2,r2,r5 + 10045c4: 14002436 bltu r2,r16,1004658 <_ZNSs6appendEmc+0xd4> + 10045c8: 30800117 ldw r2,4(r6) + 10045cc: 8163883a add r17,r16,r5 + 10045d0: 14400236 bltu r2,r17,10045dc <_ZNSs6appendEmc+0x58> + 10045d4: 30800217 ldw r2,8(r6) + 10045d8: 0080030e bge zero,r2,10045e8 <_ZNSs6appendEmc+0x64> + 10045dc: 880b883a mov r5,r17 + 10045e0: 10043d40 call 10043d4 <_ZNSs7reserveEm> + 10045e4: 90c00017 ldw r3,0(r18) + 10045e8: 18bffd17 ldw r2,-12(r3) + 10045ec: 99803fcc andi r6,r19,255 + 10045f0: 3180201c xori r6,r6,128 + 10045f4: 1889883a add r4,r3,r2 + 10045f8: 00800044 movi r2,1 + 10045fc: 31bfe004 addi r6,r6,-128 + 1004600: 80800f1e bne r16,r2,1004640 <_ZNSs6appendEmc+0xbc> + 1004604: 21800005 stb r6,0(r4) + 1004608: 90800017 ldw r2,0(r18) + 100460c: 10fffd04 addi r3,r2,-12 + 1004610: 147ffd15 stw r17,-12(r2) + 1004614: 1c49883a add r4,r3,r17 + 1004618: 18000215 stw zero,8(r3) + 100461c: 20000305 stb zero,12(r4) + 1004620: 9005883a mov r2,r18 + 1004624: dfc00417 ldw ra,16(sp) + 1004628: dcc00317 ldw r19,12(sp) + 100462c: dc800217 ldw r18,8(sp) + 1004630: dc400117 ldw r17,4(sp) + 1004634: dc000017 ldw r16,0(sp) + 1004638: dec00504 addi sp,sp,20 + 100463c: f800283a ret + 1004640: 31403fcc andi r5,r6,255 + 1004644: 2940201c xori r5,r5,128 + 1004648: 297fe004 addi r5,r5,-128 + 100464c: 800d883a mov r6,r16 + 1004650: 100abbc0 call 100abbc + 1004654: 003fec06 br 1004608 <_ZNSs6appendEmc+0x84> + 1004658: 010040b4 movhi r4,258 + 100465c: 21040d04 addi r4,r4,4148 + 1004660: 100866c0 call 100866c <_ZSt20__throw_length_errorPKc> + +01004664 <_ZNSs6appendEPKcm>: + 1004664: defffa04 addi sp,sp,-24 + 1004668: dd000415 stw r20,16(sp) + 100466c: dcc00315 stw r19,12(sp) + 1004670: dc400115 stw r17,4(sp) + 1004674: dfc00515 stw ra,20(sp) + 1004678: dc800215 stw r18,8(sp) + 100467c: dc000015 stw r16,0(sp) + 1004680: 3023883a mov r17,r6 + 1004684: 2829883a mov r20,r5 + 1004688: 2027883a mov r19,r4 + 100468c: 30001c26 beq r6,zero,1004700 <_ZNSs6appendEPKcm+0x9c> + 1004690: 24000017 ldw r16,0(r4) + 1004694: 00900034 movhi r2,16384 + 1004698: 10bfff04 addi r2,r2,-4 + 100469c: 80fffd17 ldw r3,-12(r16) + 10046a0: 817ffd04 addi r5,r16,-12 + 10046a4: 10c5c83a sub r2,r2,r3 + 10046a8: 11802e36 bltu r2,r6,1004764 <_ZNSs6appendEPKcm+0x100> + 10046ac: 28800117 ldw r2,4(r5) + 10046b0: 30e5883a add r18,r6,r3 + 10046b4: 14801b2e bgeu r2,r18,1004724 <_ZNSs6appendEPKcm+0xc0> + 10046b8: a4000236 bltu r20,r16,10046c4 <_ZNSs6appendEPKcm+0x60> + 10046bc: 80c5883a add r2,r16,r3 + 10046c0: 1500222e bgeu r2,r20,100474c <_ZNSs6appendEPKcm+0xe8> + 10046c4: 900b883a mov r5,r18 + 10046c8: 10043d40 call 10043d4 <_ZNSs7reserveEm> + 10046cc: 9c000017 ldw r16,0(r19) + 10046d0: 80bffd17 ldw r2,-12(r16) + 10046d4: 00c00044 movi r3,1 + 10046d8: 8089883a add r4,r16,r2 + 10046dc: 88c0171e bne r17,r3,100473c <_ZNSs6appendEPKcm+0xd8> + 10046e0: a0800003 ldbu r2,0(r20) + 10046e4: 20800005 stb r2,0(r4) + 10046e8: 98800017 ldw r2,0(r19) + 10046ec: 10fffd04 addi r3,r2,-12 + 10046f0: 14bffd15 stw r18,-12(r2) + 10046f4: 1c89883a add r4,r3,r18 + 10046f8: 18000215 stw zero,8(r3) + 10046fc: 20000305 stb zero,12(r4) + 1004700: 9805883a mov r2,r19 + 1004704: dfc00517 ldw ra,20(sp) + 1004708: dd000417 ldw r20,16(sp) + 100470c: dcc00317 ldw r19,12(sp) + 1004710: dc800217 ldw r18,8(sp) + 1004714: dc400117 ldw r17,4(sp) + 1004718: dc000017 ldw r16,0(sp) + 100471c: dec00604 addi sp,sp,24 + 1004720: f800283a ret + 1004724: 28800217 ldw r2,8(r5) + 1004728: 00bfe316 blt zero,r2,10046b8 <_ZNSs6appendEPKcm+0x54> + 100472c: 80bffd17 ldw r2,-12(r16) + 1004730: 00c00044 movi r3,1 + 1004734: 8089883a add r4,r16,r2 + 1004738: 88ffe926 beq r17,r3,10046e0 <_ZNSs6appendEPKcm+0x7c> + 100473c: a00b883a mov r5,r20 + 1004740: 880d883a mov r6,r17 + 1004744: 100aa3c0 call 100aa3c + 1004748: 003fe706 br 10046e8 <_ZNSs6appendEPKcm+0x84> + 100474c: 900b883a mov r5,r18 + 1004750: 10043d40 call 10043d4 <_ZNSs7reserveEm> + 1004754: a405c83a sub r2,r20,r16 + 1004758: 9c000017 ldw r16,0(r19) + 100475c: 1429883a add r20,r2,r16 + 1004760: 003fdb06 br 10046d0 <_ZNSs6appendEPKcm+0x6c> + 1004764: 010040b4 movhi r4,258 + 1004768: 21040d04 addi r4,r4,4148 + 100476c: 100866c0 call 100866c <_ZSt20__throw_length_errorPKc> + +01004770 <_ZNSs6appendEPKc>: + 1004770: defffd04 addi sp,sp,-12 + 1004774: dcc00115 stw r19,4(sp) + 1004778: dc400015 stw r17,0(sp) + 100477c: dfc00215 stw ra,8(sp) + 1004780: 2023883a mov r17,r4 + 1004784: 2809883a mov r4,r5 + 1004788: 2827883a mov r19,r5 + 100478c: 100b1640 call 100b164 + 1004790: 980b883a mov r5,r19 + 1004794: 8809883a mov r4,r17 + 1004798: 100d883a mov r6,r2 + 100479c: dfc00217 ldw ra,8(sp) + 10047a0: dcc00117 ldw r19,4(sp) + 10047a4: dc400017 ldw r17,0(sp) + 10047a8: dec00304 addi sp,sp,12 + 10047ac: 10046641 jmpi 1004664 <_ZNSs6appendEPKcm> + +010047b0 <_ZNSspLEPKc>: + 10047b0: defffd04 addi sp,sp,-12 + 10047b4: dcc00115 stw r19,4(sp) + 10047b8: dc400015 stw r17,0(sp) + 10047bc: dfc00215 stw ra,8(sp) + 10047c0: 2023883a mov r17,r4 + 10047c4: 2809883a mov r4,r5 + 10047c8: 2827883a mov r19,r5 + 10047cc: 100b1640 call 100b164 + 10047d0: 980b883a mov r5,r19 + 10047d4: 8809883a mov r4,r17 + 10047d8: 100d883a mov r6,r2 + 10047dc: dfc00217 ldw ra,8(sp) + 10047e0: dcc00117 ldw r19,4(sp) + 10047e4: dc400017 ldw r17,0(sp) + 10047e8: dec00304 addi sp,sp,12 + 10047ec: 10046641 jmpi 1004664 <_ZNSs6appendEPKcm> + +010047f0 <_ZNSs6appendERKSsmm>: + 10047f0: defffa04 addi sp,sp,-24 + 10047f4: dcc00415 stw r19,16(sp) + 10047f8: 2827883a mov r19,r5 + 10047fc: 29400017 ldw r5,0(r5) + 1004800: dc800315 stw r18,12(sp) + 1004804: dc000115 stw r16,4(sp) + 1004808: 28bffd17 ldw r2,-12(r5) + 100480c: dfc00515 stw ra,20(sp) + 1004810: dc400215 stw r17,8(sp) + 1004814: 3021883a mov r16,r6 + 1004818: 2025883a mov r18,r4 + 100481c: 11802b36 bltu r2,r6,10048cc <_ZNSs6appendERKSsmm+0xdc> + 1004820: 118dc83a sub r6,r2,r6 + 1004824: 31c02436 bltu r6,r7,10048b8 <_ZNSs6appendERKSsmm+0xc8> + 1004828: 38001b26 beq r7,zero,1004898 <_ZNSs6appendERKSsmm+0xa8> + 100482c: 91800017 ldw r6,0(r18) + 1004830: 323ffd04 addi r8,r6,-12 + 1004834: 30bffd17 ldw r2,-12(r6) + 1004838: 40c00117 ldw r3,4(r8) + 100483c: 38a3883a add r17,r7,r2 + 1004840: 1c400236 bltu r3,r17,100484c <_ZNSs6appendERKSsmm+0x5c> + 1004844: 40800217 ldw r2,8(r8) + 1004848: 0080060e bge zero,r2,1004864 <_ZNSs6appendERKSsmm+0x74> + 100484c: 880b883a mov r5,r17 + 1004850: d9c00015 stw r7,0(sp) + 1004854: 10043d40 call 10043d4 <_ZNSs7reserveEm> + 1004858: 99400017 ldw r5,0(r19) + 100485c: 91800017 ldw r6,0(r18) + 1004860: d9c00017 ldw r7,0(sp) + 1004864: 30fffd17 ldw r3,-12(r6) + 1004868: 00800044 movi r2,1 + 100486c: 814b883a add r5,r16,r5 + 1004870: 30c9883a add r4,r6,r3 + 1004874: 3880121e bne r7,r2,10048c0 <_ZNSs6appendERKSsmm+0xd0> + 1004878: 28800003 ldbu r2,0(r5) + 100487c: 20800005 stb r2,0(r4) + 1004880: 90800017 ldw r2,0(r18) + 1004884: 10fffd04 addi r3,r2,-12 + 1004888: 147ffd15 stw r17,-12(r2) + 100488c: 1c49883a add r4,r3,r17 + 1004890: 18000215 stw zero,8(r3) + 1004894: 20000305 stb zero,12(r4) + 1004898: 9005883a mov r2,r18 + 100489c: dfc00517 ldw ra,20(sp) + 10048a0: dcc00417 ldw r19,16(sp) + 10048a4: dc800317 ldw r18,12(sp) + 10048a8: dc400217 ldw r17,8(sp) + 10048ac: dc000117 ldw r16,4(sp) + 10048b0: dec00604 addi sp,sp,24 + 10048b4: f800283a ret + 10048b8: 300f883a mov r7,r6 + 10048bc: 003fda06 br 1004828 <_ZNSs6appendERKSsmm+0x38> + 10048c0: 380d883a mov r6,r7 + 10048c4: 100aa3c0 call 100aa3c + 10048c8: 003fed06 br 1004880 <_ZNSs6appendERKSsmm+0x90> + 10048cc: 010040b4 movhi r4,258 + 10048d0: 21040d04 addi r4,r4,4148 + 10048d4: 10084dc0 call 10084dc <_ZSt20__throw_out_of_rangePKc> + +010048d8 <_ZNSs6appendERKSs>: + 10048d8: 2a000017 ldw r8,0(r5) + 10048dc: defffb04 addi sp,sp,-20 + 10048e0: dc000015 stw r16,0(sp) + 10048e4: 443ffd17 ldw r16,-12(r8) + 10048e8: dcc00315 stw r19,12(sp) + 10048ec: dc800215 stw r18,8(sp) + 10048f0: dfc00415 stw ra,16(sp) + 10048f4: dc400115 stw r17,4(sp) + 10048f8: 2827883a mov r19,r5 + 10048fc: 2025883a mov r18,r4 + 1004900: 80001a26 beq r16,zero,100496c <_ZNSs6appendERKSs+0x94> + 1004904: 21c00017 ldw r7,0(r4) + 1004908: 39bffd04 addi r6,r7,-12 + 100490c: 38bffd17 ldw r2,-12(r7) + 1004910: 30c00117 ldw r3,4(r6) + 1004914: 80a3883a add r17,r16,r2 + 1004918: 880b883a mov r5,r17 + 100491c: 1c400236 bltu r3,r17,1004928 <_ZNSs6appendERKSs+0x50> + 1004920: 30800217 ldw r2,8(r6) + 1004924: 0080030e bge zero,r2,1004934 <_ZNSs6appendERKSs+0x5c> + 1004928: 10043d40 call 10043d4 <_ZNSs7reserveEm> + 100492c: 9a000017 ldw r8,0(r19) + 1004930: 91c00017 ldw r7,0(r18) + 1004934: 38fffd17 ldw r3,-12(r7) + 1004938: 00800044 movi r2,1 + 100493c: 400b883a mov r5,r8 + 1004940: 800d883a mov r6,r16 + 1004944: 38c9883a add r4,r7,r3 + 1004948: 8080101e bne r16,r2,100498c <_ZNSs6appendERKSs+0xb4> + 100494c: 40800003 ldbu r2,0(r8) + 1004950: 20800005 stb r2,0(r4) + 1004954: 90800017 ldw r2,0(r18) + 1004958: 10fffd04 addi r3,r2,-12 + 100495c: 147ffd15 stw r17,-12(r2) + 1004960: 1c49883a add r4,r3,r17 + 1004964: 18000215 stw zero,8(r3) + 1004968: 20000305 stb zero,12(r4) + 100496c: 9005883a mov r2,r18 + 1004970: dfc00417 ldw ra,16(sp) + 1004974: dcc00317 ldw r19,12(sp) + 1004978: dc800217 ldw r18,8(sp) + 100497c: dc400117 ldw r17,4(sp) + 1004980: dc000017 ldw r16,0(sp) + 1004984: dec00504 addi sp,sp,20 + 1004988: f800283a ret + 100498c: 100aa3c0 call 100aa3c + 1004990: 003ff006 br 1004954 <_ZNSs6appendERKSs+0x7c> + +01004994 <_ZNSspLERKSs>: + 1004994: 10048d81 jmpi 10048d8 <_ZNSs6appendERKSs> + +01004998 <_ZNSspLEc>: + 1004998: 21800017 ldw r6,0(r4) + 100499c: defffc04 addi sp,sp,-16 + 10049a0: dc000015 stw r16,0(sp) + 10049a4: 30bffd17 ldw r2,-12(r6) + 10049a8: 31fffd04 addi r7,r6,-12 + 10049ac: 38c00117 ldw r3,4(r7) + 10049b0: 14000044 addi r16,r2,1 + 10049b4: dc800215 stw r18,8(sp) + 10049b8: dc400115 stw r17,4(sp) + 10049bc: 2825883a mov r18,r5 + 10049c0: dfc00315 stw ra,12(sp) + 10049c4: 2023883a mov r17,r4 + 10049c8: 800b883a mov r5,r16 + 10049cc: 1c001236 bltu r3,r16,1004a18 <_ZNSspLEc+0x80> + 10049d0: 38800217 ldw r2,8(r7) + 10049d4: 00801016 blt zero,r2,1004a18 <_ZNSspLEc+0x80> + 10049d8: 30fffd17 ldw r3,-12(r6) + 10049dc: 8805883a mov r2,r17 + 10049e0: 30c7883a add r3,r6,r3 + 10049e4: 1c800005 stb r18,0(r3) + 10049e8: 89000017 ldw r4,0(r17) + 10049ec: 20fffd04 addi r3,r4,-12 + 10049f0: 243ffd15 stw r16,-12(r4) + 10049f4: 1c0b883a add r5,r3,r16 + 10049f8: 18000215 stw zero,8(r3) + 10049fc: 28000305 stb zero,12(r5) + 1004a00: dfc00317 ldw ra,12(sp) + 1004a04: dc800217 ldw r18,8(sp) + 1004a08: dc400117 ldw r17,4(sp) + 1004a0c: dc000017 ldw r16,0(sp) + 1004a10: dec00404 addi sp,sp,16 + 1004a14: f800283a ret + 1004a18: 10043d40 call 10043d4 <_ZNSs7reserveEm> + 1004a1c: 89800017 ldw r6,0(r17) + 1004a20: 003fed06 br 10049d8 <_ZNSspLEc+0x40> + +01004a24 <_ZNSsD1Ev>: + 1004a24: deffed04 addi sp,sp,-76 + 1004a28: 00804034 movhi r2,256 + 1004a2c: 109a9704 addi r2,r2,27228 + 1004a30: 00c040b4 movhi r3,258 + 1004a34: 18c2e9c4 addi r3,r3,2983 + 1004a38: d8800715 stw r2,28(sp) + 1004a3c: d9000f15 stw r4,60(sp) + 1004a40: 00804034 movhi r2,256 + 1004a44: 1092b404 addi r2,r2,19152 + 1004a48: d9000104 addi r4,sp,4 + 1004a4c: d8c00815 stw r3,32(sp) + 1004a50: d8800a15 stw r2,40(sp) + 1004a54: dfc01215 stw ra,72(sp) + 1004a58: df001115 stw fp,68(sp) + 1004a5c: ddc01015 stw r23,64(sp) + 1004a60: dec00915 stw sp,36(sp) + 1004a64: dec00b15 stw sp,44(sp) + 1004a68: 1009c1c0 call 1009c1c <_Unwind_SjLj_Register> + 1004a6c: d8c00f17 ldw r3,60(sp) + 1004a70: 18800017 ldw r2,0(r3) + 1004a74: 00c040f4 movhi r3,259 + 1004a78: 18e52f04 addi r3,r3,-27460 + 1004a7c: 10bffd04 addi r2,r2,-12 + 1004a80: d8800e15 stw r2,56(sp) + 1004a84: 10c0071e bne r2,r3,1004aa4 <_ZNSsD1Ev+0x80> + 1004a88: d9000104 addi r4,sp,4 + 1004a8c: 1009c2c0 call 1009c2c <_Unwind_SjLj_Unregister> + 1004a90: dfc01217 ldw ra,72(sp) + 1004a94: df001117 ldw fp,68(sp) + 1004a98: ddc01017 ldw r23,64(sp) + 1004a9c: dec01304 addi sp,sp,76 + 1004aa0: f800283a ret + 1004aa4: 00800044 movi r2,1 + 1004aa8: d8800215 stw r2,8(sp) + 1004aac: d8800e17 ldw r2,56(sp) + 1004ab0: 017fffc4 movi r5,-1 + 1004ab4: 11000204 addi r4,r2,8 + 1004ab8: 100617c0 call 100617c <_ZN9__gnu_cxx18__exchange_and_addEPVii> + 1004abc: 00bff216 blt zero,r2,1004a88 <_ZNSsD1Ev+0x64> + 1004ac0: d9000e17 ldw r4,56(sp) + 1004ac4: d80b883a mov r5,sp + 1004ac8: 1002c0c0 call 1002c0c <_ZNSs4_Rep10_M_destroyERKSaIcE> + 1004acc: 003fee06 br 1004a88 <_ZNSsD1Ev+0x64> + 1004ad0: d9000317 ldw r4,12(sp) + 1004ad4: 00bfffc4 movi r2,-1 + 1004ad8: d8800215 stw r2,8(sp) + 1004adc: 1009ee80 call 1009ee8 <_Unwind_SjLj_Resume> + +01004ae0 <_ZNSsD2Ev>: + 1004ae0: deffed04 addi sp,sp,-76 + 1004ae4: 00804034 movhi r2,256 + 1004ae8: 109a9704 addi r2,r2,27228 + 1004aec: 00c040b4 movhi r3,258 + 1004af0: 18c2eb44 addi r3,r3,2989 + 1004af4: d8800715 stw r2,28(sp) + 1004af8: d9000f15 stw r4,60(sp) + 1004afc: 00804034 movhi r2,256 + 1004b00: 1092e304 addi r2,r2,19340 + 1004b04: d9000104 addi r4,sp,4 + 1004b08: d8c00815 stw r3,32(sp) + 1004b0c: d8800a15 stw r2,40(sp) + 1004b10: dfc01215 stw ra,72(sp) + 1004b14: df001115 stw fp,68(sp) + 1004b18: ddc01015 stw r23,64(sp) + 1004b1c: dec00915 stw sp,36(sp) + 1004b20: dec00b15 stw sp,44(sp) + 1004b24: 1009c1c0 call 1009c1c <_Unwind_SjLj_Register> + 1004b28: d8c00f17 ldw r3,60(sp) + 1004b2c: 18800017 ldw r2,0(r3) + 1004b30: 00c040f4 movhi r3,259 + 1004b34: 18e52f04 addi r3,r3,-27460 + 1004b38: 10bffd04 addi r2,r2,-12 + 1004b3c: d8800e15 stw r2,56(sp) + 1004b40: 10c0071e bne r2,r3,1004b60 <_ZNSsD2Ev+0x80> + 1004b44: d9000104 addi r4,sp,4 + 1004b48: 1009c2c0 call 1009c2c <_Unwind_SjLj_Unregister> + 1004b4c: dfc01217 ldw ra,72(sp) + 1004b50: df001117 ldw fp,68(sp) + 1004b54: ddc01017 ldw r23,64(sp) + 1004b58: dec01304 addi sp,sp,76 + 1004b5c: f800283a ret + 1004b60: 00800044 movi r2,1 + 1004b64: d8800215 stw r2,8(sp) + 1004b68: d8800e17 ldw r2,56(sp) + 1004b6c: 017fffc4 movi r5,-1 + 1004b70: 11000204 addi r4,r2,8 + 1004b74: 100617c0 call 100617c <_ZN9__gnu_cxx18__exchange_and_addEPVii> + 1004b78: 00bff216 blt zero,r2,1004b44 <_ZNSsD2Ev+0x64> + 1004b7c: d9000e17 ldw r4,56(sp) + 1004b80: d80b883a mov r5,sp + 1004b84: 1002c0c0 call 1002c0c <_ZNSs4_Rep10_M_destroyERKSaIcE> + 1004b88: 003fee06 br 1004b44 <_ZNSsD2Ev+0x64> + 1004b8c: d9000317 ldw r4,12(sp) + 1004b90: 00bfffc4 movi r2,-1 + 1004b94: d8800215 stw r2,8(sp) + 1004b98: 1009ee80 call 1009ee8 <_Unwind_SjLj_Resume> + +01004b9c <_ZNSs9_M_mutateEmmm>: + 1004b9c: deffe704 addi sp,sp,-100 + 1004ba0: 00804034 movhi r2,256 + 1004ba4: 109a9704 addi r2,r2,27228 + 1004ba8: 00c040b4 movhi r3,258 + 1004bac: 18c2ecc4 addi r3,r3,2995 + 1004bb0: d8800715 stw r2,28(sp) + 1004bb4: d9001215 stw r4,72(sp) + 1004bb8: 00804034 movhi r2,256 + 1004bbc: 10937104 addi r2,r2,19908 + 1004bc0: d9000104 addi r4,sp,4 + 1004bc4: d8c00815 stw r3,32(sp) + 1004bc8: d8800a15 stw r2,40(sp) + 1004bcc: d9801415 stw r6,80(sp) + 1004bd0: d9401315 stw r5,76(sp) + 1004bd4: d9c01515 stw r7,84(sp) + 1004bd8: dfc01815 stw ra,96(sp) + 1004bdc: df001715 stw fp,92(sp) + 1004be0: ddc01615 stw r23,88(sp) + 1004be4: dec00915 stw sp,36(sp) + 1004be8: dec00b15 stw sp,44(sp) + 1004bec: 1009c1c0 call 1009c1c <_Unwind_SjLj_Register> + 1004bf0: d8801217 ldw r2,72(sp) + 1004bf4: d9c01517 ldw r7,84(sp) + 1004bf8: 11800017 ldw r6,0(r2) + 1004bfc: 313ffd04 addi r4,r6,-12 + 1004c00: 20800017 ldw r2,0(r4) + 1004c04: 21400117 ldw r5,4(r4) + 1004c08: 11c7883a add r3,r2,r7 + 1004c0c: d9c01317 ldw r7,76(sp) + 1004c10: 11c5c83a sub r2,r2,r7 + 1004c14: d9c01417 ldw r7,80(sp) + 1004c18: 19c7c83a sub r3,r3,r7 + 1004c1c: 11c5c83a sub r2,r2,r7 + 1004c20: d8c01115 stw r3,68(sp) + 1004c24: d8801015 stw r2,64(sp) + 1004c28: 28c00236 bltu r5,r3,1004c34 <_ZNSs9_M_mutateEmmm+0x98> + 1004c2c: 20800217 ldw r2,8(r4) + 1004c30: 0080240e bge zero,r2,1004cc4 <_ZNSs9_M_mutateEmmm+0x128> + 1004c34: 00800044 movi r2,1 + 1004c38: d8800215 stw r2,8(sp) + 1004c3c: d9001117 ldw r4,68(sp) + 1004c40: d80d883a mov r6,sp + 1004c44: 1002adc0 call 1002adc <_ZNSs4_Rep9_S_createEmmRKSaIcE> + 1004c48: d8c01317 ldw r3,76(sp) + 1004c4c: d8800f15 stw r2,60(sp) + 1004c50: 18003c1e bne r3,zero,1004d44 <_ZNSs9_M_mutateEmmm+0x1a8> + 1004c54: d8c01017 ldw r3,64(sp) + 1004c58: 1800291e bne r3,zero,1004d00 <_ZNSs9_M_mutateEmmm+0x164> + 1004c5c: d8c01217 ldw r3,72(sp) + 1004c60: 18800017 ldw r2,0(r3) + 1004c64: 00c040f4 movhi r3,259 + 1004c68: 18e52f04 addi r3,r3,-27460 + 1004c6c: 10bffd04 addi r2,r2,-12 + 1004c70: d8800e15 stw r2,56(sp) + 1004c74: 10c0481e bne r2,r3,1004d98 <_ZNSs9_M_mutateEmmm+0x1fc> + 1004c78: d9c00f17 ldw r7,60(sp) + 1004c7c: d8c01217 ldw r3,72(sp) + 1004c80: 38800304 addi r2,r7,12 + 1004c84: 18800015 stw r2,0(r3) + 1004c88: d9401217 ldw r5,72(sp) + 1004c8c: d9c01117 ldw r7,68(sp) + 1004c90: d9000104 addi r4,sp,4 + 1004c94: 28800017 ldw r2,0(r5) + 1004c98: 10bffd04 addi r2,r2,-12 + 1004c9c: 11c7883a add r3,r2,r7 + 1004ca0: 10000215 stw zero,8(r2) + 1004ca4: 11c00015 stw r7,0(r2) + 1004ca8: 18000305 stb zero,12(r3) + 1004cac: 1009c2c0 call 1009c2c <_Unwind_SjLj_Unregister> + 1004cb0: dfc01817 ldw ra,96(sp) + 1004cb4: df001717 ldw fp,92(sp) + 1004cb8: ddc01617 ldw r23,88(sp) + 1004cbc: dec01904 addi sp,sp,100 + 1004cc0: f800283a ret + 1004cc4: d9001017 ldw r4,64(sp) + 1004cc8: 203fef26 beq r4,zero,1004c88 <_ZNSs9_M_mutateEmmm+0xec> + 1004ccc: d9001517 ldw r4,84(sp) + 1004cd0: d9401417 ldw r5,80(sp) + 1004cd4: 217fec26 beq r4,r5,1004c88 <_ZNSs9_M_mutateEmmm+0xec> + 1004cd8: d9c01317 ldw r7,76(sp) + 1004cdc: 00800044 movi r2,1 + 1004ce0: 31c7883a add r3,r6,r7 + 1004ce4: 194b883a add r5,r3,r5 + 1004ce8: 1909883a add r4,r3,r4 + 1004cec: d8c01017 ldw r3,64(sp) + 1004cf0: 1880261e bne r3,r2,1004d8c <_ZNSs9_M_mutateEmmm+0x1f0> + 1004cf4: 28800003 ldbu r2,0(r5) + 1004cf8: 20800005 stb r2,0(r4) + 1004cfc: 003fe206 br 1004c88 <_ZNSs9_M_mutateEmmm+0xec> + 1004d00: d9001217 ldw r4,72(sp) + 1004d04: d9400f17 ldw r5,60(sp) + 1004d08: d9c01317 ldw r7,76(sp) + 1004d0c: 20800017 ldw r2,0(r4) + 1004d10: 28c00304 addi r3,r5,12 + 1004d14: 19c7883a add r3,r3,r7 + 1004d18: 3885883a add r2,r7,r2 + 1004d1c: d9401517 ldw r5,84(sp) + 1004d20: d9c01417 ldw r7,80(sp) + 1004d24: 1949883a add r4,r3,r5 + 1004d28: 11cb883a add r5,r2,r7 + 1004d2c: d8801017 ldw r2,64(sp) + 1004d30: 00c00044 movi r3,1 + 1004d34: 10c00d26 beq r2,r3,1004d6c <_ZNSs9_M_mutateEmmm+0x1d0> + 1004d38: d9801017 ldw r6,64(sp) + 1004d3c: 100aa3c0 call 100aa3c + 1004d40: 003fc606 br 1004c5c <_ZNSs9_M_mutateEmmm+0xc0> + 1004d44: d9c01217 ldw r7,72(sp) + 1004d48: 11000304 addi r4,r2,12 + 1004d4c: 00800044 movi r2,1 + 1004d50: 39400017 ldw r5,0(r7) + 1004d54: 18800826 beq r3,r2,1004d78 <_ZNSs9_M_mutateEmmm+0x1dc> + 1004d58: d9801317 ldw r6,76(sp) + 1004d5c: 100aa3c0 call 100aa3c + 1004d60: d8c01017 ldw r3,64(sp) + 1004d64: 183fbd26 beq r3,zero,1004c5c <_ZNSs9_M_mutateEmmm+0xc0> + 1004d68: 003fe506 br 1004d00 <_ZNSs9_M_mutateEmmm+0x164> + 1004d6c: 28800003 ldbu r2,0(r5) + 1004d70: 20800005 stb r2,0(r4) + 1004d74: 003fb906 br 1004c5c <_ZNSs9_M_mutateEmmm+0xc0> + 1004d78: 28800003 ldbu r2,0(r5) + 1004d7c: 20800005 stb r2,0(r4) + 1004d80: d8c01017 ldw r3,64(sp) + 1004d84: 183fb526 beq r3,zero,1004c5c <_ZNSs9_M_mutateEmmm+0xc0> + 1004d88: 003fdd06 br 1004d00 <_ZNSs9_M_mutateEmmm+0x164> + 1004d8c: d9801017 ldw r6,64(sp) + 1004d90: 100aadc0 call 100aadc + 1004d94: 003fbc06 br 1004c88 <_ZNSs9_M_mutateEmmm+0xec> + 1004d98: d9400e17 ldw r5,56(sp) + 1004d9c: 00800044 movi r2,1 + 1004da0: d8800215 stw r2,8(sp) + 1004da4: 29000204 addi r4,r5,8 + 1004da8: 017fffc4 movi r5,-1 + 1004dac: 100617c0 call 100617c <_ZN9__gnu_cxx18__exchange_and_addEPVii> + 1004db0: 00bfb116 blt zero,r2,1004c78 <_ZNSs9_M_mutateEmmm+0xdc> + 1004db4: d9000e17 ldw r4,56(sp) + 1004db8: d80b883a mov r5,sp + 1004dbc: 1002c0c0 call 1002c0c <_ZNSs4_Rep10_M_destroyERKSaIcE> + 1004dc0: 003fad06 br 1004c78 <_ZNSs9_M_mutateEmmm+0xdc> + 1004dc4: d9000317 ldw r4,12(sp) + 1004dc8: 00bfffc4 movi r2,-1 + 1004dcc: d8800215 stw r2,8(sp) + 1004dd0: 1009ee80 call 1009ee8 <_Unwind_SjLj_Resume> + +01004dd4 <_ZNSs15_M_replace_safeEmmPKcm>: + 1004dd4: defffb04 addi sp,sp,-20 + 1004dd8: dc000015 stw r16,0(sp) + 1004ddc: dc000517 ldw r16,20(sp) + 1004de0: dcc00315 stw r19,12(sp) + 1004de4: 3827883a mov r19,r7 + 1004de8: 800f883a mov r7,r16 + 1004dec: dc800215 stw r18,8(sp) + 1004df0: dc400115 stw r17,4(sp) + 1004df4: dfc00415 stw ra,16(sp) + 1004df8: 2025883a mov r18,r4 + 1004dfc: 2823883a mov r17,r5 + 1004e00: 1004b9c0 call 1004b9c <_ZNSs9_M_mutateEmmm> + 1004e04: 80000826 beq r16,zero,1004e28 <_ZNSs15_M_replace_safeEmmPKcm+0x54> + 1004e08: 90800017 ldw r2,0(r18) + 1004e0c: 980b883a mov r5,r19 + 1004e10: 800d883a mov r6,r16 + 1004e14: 8887883a add r3,r17,r2 + 1004e18: 00800044 movi r2,1 + 1004e1c: 1809883a mov r4,r3 + 1004e20: 80800926 beq r16,r2,1004e48 <_ZNSs15_M_replace_safeEmmPKcm+0x74> + 1004e24: 100aa3c0 call 100aa3c + 1004e28: 9005883a mov r2,r18 + 1004e2c: dfc00417 ldw ra,16(sp) + 1004e30: dcc00317 ldw r19,12(sp) + 1004e34: dc800217 ldw r18,8(sp) + 1004e38: dc400117 ldw r17,4(sp) + 1004e3c: dc000017 ldw r16,0(sp) + 1004e40: dec00504 addi sp,sp,20 + 1004e44: f800283a ret + 1004e48: 98800003 ldbu r2,0(r19) + 1004e4c: 18800005 stb r2,0(r3) + 1004e50: 9005883a mov r2,r18 + 1004e54: dfc00417 ldw ra,16(sp) + 1004e58: dcc00317 ldw r19,12(sp) + 1004e5c: dc800217 ldw r18,8(sp) + 1004e60: dc400117 ldw r17,4(sp) + 1004e64: dc000017 ldw r16,0(sp) + 1004e68: dec00504 addi sp,sp,20 + 1004e6c: f800283a ret + +01004e70 <_ZNSs6assignEPKcm>: + 1004e70: defffc04 addi sp,sp,-16 + 1004e74: 00900034 movhi r2,16384 + 1004e78: 10bfff04 addi r2,r2,-4 + 1004e7c: dc400215 stw r17,8(sp) + 1004e80: dc000115 stw r16,4(sp) + 1004e84: dfc00315 stw ra,12(sp) + 1004e88: 3023883a mov r17,r6 + 1004e8c: 2021883a mov r16,r4 + 1004e90: 280f883a mov r7,r5 + 1004e94: 11803136 bltu r2,r6,1004f5c <_ZNSs6assignEPKcm+0xec> + 1004e98: 21000017 ldw r4,0(r4) + 1004e9c: 29000c2e bgeu r5,r4,1004ed0 <_ZNSs6assignEPKcm+0x60> + 1004ea0: 21bffd17 ldw r6,-12(r4) + 1004ea4: 000b883a mov r5,zero + 1004ea8: 8009883a mov r4,r16 + 1004eac: dc400015 stw r17,0(sp) + 1004eb0: 1004dd40 call 1004dd4 <_ZNSs15_M_replace_safeEmmPKcm> + 1004eb4: 1021883a mov r16,r2 + 1004eb8: 8005883a mov r2,r16 + 1004ebc: dfc00317 ldw ra,12(sp) + 1004ec0: dc400217 ldw r17,8(sp) + 1004ec4: dc000117 ldw r16,4(sp) + 1004ec8: dec00404 addi sp,sp,16 + 1004ecc: f800283a ret + 1004ed0: 20bffd17 ldw r2,-12(r4) + 1004ed4: 20fffd04 addi r3,r4,-12 + 1004ed8: 2085883a add r2,r4,r2 + 1004edc: 117ff036 bltu r2,r5,1004ea0 <_ZNSs6assignEPKcm+0x30> + 1004ee0: 18800217 ldw r2,8(r3) + 1004ee4: 00bfee16 blt zero,r2,1004ea0 <_ZNSs6assignEPKcm+0x30> + 1004ee8: 2905c83a sub r2,r5,r4 + 1004eec: 11800f36 bltu r2,r6,1004f2c <_ZNSs6assignEPKcm+0xbc> + 1004ef0: 00800044 movi r2,1 + 1004ef4: 88801526 beq r17,r2,1004f4c <_ZNSs6assignEPKcm+0xdc> + 1004ef8: 100aa3c0 call 100aa3c + 1004efc: 81000017 ldw r4,0(r16) + 1004f00: 20bffd04 addi r2,r4,-12 + 1004f04: 1447883a add r3,r2,r17 + 1004f08: 10000215 stw zero,8(r2) + 1004f0c: 247ffd15 stw r17,-12(r4) + 1004f10: 8005883a mov r2,r16 + 1004f14: 18000305 stb zero,12(r3) + 1004f18: dfc00317 ldw ra,12(sp) + 1004f1c: dc400217 ldw r17,8(sp) + 1004f20: dc000117 ldw r16,4(sp) + 1004f24: dec00404 addi sp,sp,16 + 1004f28: f800283a ret + 1004f2c: 103ff426 beq r2,zero,1004f00 <_ZNSs6assignEPKcm+0x90> + 1004f30: 00800044 movi r2,1 + 1004f34: 88800526 beq r17,r2,1004f4c <_ZNSs6assignEPKcm+0xdc> + 1004f38: 380b883a mov r5,r7 + 1004f3c: 880d883a mov r6,r17 + 1004f40: 100aadc0 call 100aadc + 1004f44: 81000017 ldw r4,0(r16) + 1004f48: 003fed06 br 1004f00 <_ZNSs6assignEPKcm+0x90> + 1004f4c: 38800003 ldbu r2,0(r7) + 1004f50: 20800005 stb r2,0(r4) + 1004f54: 81000017 ldw r4,0(r16) + 1004f58: 003fe906 br 1004f00 <_ZNSs6assignEPKcm+0x90> + 1004f5c: 010040b4 movhi r4,258 + 1004f60: 21041304 addi r4,r4,4172 + 1004f64: 100866c0 call 100866c <_ZSt20__throw_length_errorPKc> + +01004f68 <_ZNSs6assignEPKc>: + 1004f68: defffd04 addi sp,sp,-12 + 1004f6c: dcc00115 stw r19,4(sp) + 1004f70: dc400015 stw r17,0(sp) + 1004f74: dfc00215 stw ra,8(sp) + 1004f78: 2023883a mov r17,r4 + 1004f7c: 2809883a mov r4,r5 + 1004f80: 2827883a mov r19,r5 + 1004f84: 100b1640 call 100b164 + 1004f88: 980b883a mov r5,r19 + 1004f8c: 8809883a mov r4,r17 + 1004f90: 100d883a mov r6,r2 + 1004f94: dfc00217 ldw ra,8(sp) + 1004f98: dcc00117 ldw r19,4(sp) + 1004f9c: dc400017 ldw r17,0(sp) + 1004fa0: dec00304 addi sp,sp,12 + 1004fa4: 1004e701 jmpi 1004e70 <_ZNSs6assignEPKcm> + +01004fa8 <_ZNSs6assignERKSsmm>: + 1004fa8: 29400017 ldw r5,0(r5) + 1004fac: deffff04 addi sp,sp,-4 + 1004fb0: dfc00015 stw ra,0(sp) + 1004fb4: 28bffd17 ldw r2,-12(r5) + 1004fb8: 11800c36 bltu r2,r6,1004fec <_ZNSs6assignERKSsmm+0x44> + 1004fbc: 1185c83a sub r2,r2,r6 + 1004fc0: 298b883a add r5,r5,r6 + 1004fc4: 11c00436 bltu r2,r7,1004fd8 <_ZNSs6assignERKSsmm+0x30> + 1004fc8: 380d883a mov r6,r7 + 1004fcc: dfc00017 ldw ra,0(sp) + 1004fd0: dec00104 addi sp,sp,4 + 1004fd4: 1004e701 jmpi 1004e70 <_ZNSs6assignEPKcm> + 1004fd8: 100f883a mov r7,r2 + 1004fdc: 380d883a mov r6,r7 + 1004fe0: dfc00017 ldw ra,0(sp) + 1004fe4: dec00104 addi sp,sp,4 + 1004fe8: 1004e701 jmpi 1004e70 <_ZNSs6assignEPKcm> + 1004fec: 010040b4 movhi r4,258 + 1004ff0: 21041304 addi r4,r4,4172 + 1004ff4: 10084dc0 call 10084dc <_ZSt20__throw_out_of_rangePKc> + +01004ff8 <_ZNSsaSEPKc>: + 1004ff8: defffd04 addi sp,sp,-12 + 1004ffc: dcc00115 stw r19,4(sp) + 1005000: dc400015 stw r17,0(sp) + 1005004: dfc00215 stw ra,8(sp) + 1005008: 2023883a mov r17,r4 + 100500c: 2809883a mov r4,r5 + 1005010: 2827883a mov r19,r5 + 1005014: 100b1640 call 100b164 + 1005018: 980b883a mov r5,r19 + 100501c: 8809883a mov r4,r17 + 1005020: 100d883a mov r6,r2 + 1005024: dfc00217 ldw ra,8(sp) + 1005028: dcc00117 ldw r19,4(sp) + 100502c: dc400017 ldw r17,0(sp) + 1005030: dec00304 addi sp,sp,12 + 1005034: 1004e701 jmpi 1004e70 <_ZNSs6assignEPKcm> + +01005038 <_ZNSs14_M_replace_auxEmmmc>: + 1005038: 20800017 ldw r2,0(r4) + 100503c: defffb04 addi sp,sp,-20 + 1005040: dcc00315 stw r19,12(sp) + 1005044: 10fffd17 ldw r3,-12(r2) + 1005048: 00900034 movhi r2,16384 + 100504c: 10bfff04 addi r2,r2,-4 + 1005050: dc800215 stw r18,8(sp) + 1005054: 1987c83a sub r3,r3,r6 + 1005058: 10c5c83a sub r2,r2,r3 + 100505c: dc400115 stw r17,4(sp) + 1005060: dc000015 stw r16,0(sp) + 1005064: dfc00415 stw ra,16(sp) + 1005068: 2023883a mov r17,r4 + 100506c: 3821883a mov r16,r7 + 1005070: 2827883a mov r19,r5 + 1005074: dc800503 ldbu r18,20(sp) + 1005078: 11c01f36 bltu r2,r7,10050f8 <_ZNSs14_M_replace_auxEmmmc+0xc0> + 100507c: 1004b9c0 call 1004b9c <_ZNSs9_M_mutateEmmm> + 1005080: 80000c26 beq r16,zero,10050b4 <_ZNSs14_M_replace_auxEmmmc+0x7c> + 1005084: 88800017 ldw r2,0(r17) + 1005088: 90c03fcc andi r3,r18,255 + 100508c: 18c0201c xori r3,r3,128 + 1005090: 9889883a add r4,r19,r2 + 1005094: 00800044 movi r2,1 + 1005098: 18ffe004 addi r3,r3,-128 + 100509c: 80800d26 beq r16,r2,10050d4 <_ZNSs14_M_replace_auxEmmmc+0x9c> + 10050a0: 19403fcc andi r5,r3,255 + 10050a4: 2940201c xori r5,r5,128 + 10050a8: 297fe004 addi r5,r5,-128 + 10050ac: 800d883a mov r6,r16 + 10050b0: 100abbc0 call 100abbc + 10050b4: 8805883a mov r2,r17 + 10050b8: dfc00417 ldw ra,16(sp) + 10050bc: dcc00317 ldw r19,12(sp) + 10050c0: dc800217 ldw r18,8(sp) + 10050c4: dc400117 ldw r17,4(sp) + 10050c8: dc000017 ldw r16,0(sp) + 10050cc: dec00504 addi sp,sp,20 + 10050d0: f800283a ret + 10050d4: 8805883a mov r2,r17 + 10050d8: 20c00005 stb r3,0(r4) + 10050dc: dfc00417 ldw ra,16(sp) + 10050e0: dcc00317 ldw r19,12(sp) + 10050e4: dc800217 ldw r18,8(sp) + 10050e8: dc400117 ldw r17,4(sp) + 10050ec: dc000017 ldw r16,0(sp) + 10050f0: dec00504 addi sp,sp,20 + 10050f4: f800283a ret + 10050f8: 010040b4 movhi r4,258 + 10050fc: 21041904 addi r4,r4,4196 + 1005100: 100866c0 call 100866c <_ZSt20__throw_length_errorPKc> + +01005104 <_ZNSs7replaceEN9__gnu_cxx17__normal_iteratorIPcSsEES2_mc>: + 1005104: 20800017 ldw r2,0(r4) + 1005108: d8c00007 ldb r3,0(sp) + 100510c: 314dc83a sub r6,r6,r5 + 1005110: 288bc83a sub r5,r5,r2 + 1005114: d8c00015 stw r3,0(sp) + 1005118: 10050381 jmpi 1005038 <_ZNSs14_M_replace_auxEmmmc> + +0100511c <_ZNSs7replaceEmmmc>: + 100511c: 20800017 ldw r2,0(r4) + 1005120: deffff04 addi sp,sp,-4 + 1005124: dfc00015 stw ra,0(sp) + 1005128: 10fffd17 ldw r3,-12(r2) + 100512c: d8800103 ldbu r2,4(sp) + 1005130: 19401136 bltu r3,r5,1005178 <_ZNSs7replaceEmmmc+0x5c> + 1005134: 1947c83a sub r3,r3,r5 + 1005138: 19800736 bltu r3,r6,1005158 <_ZNSs7replaceEmmmc+0x3c> + 100513c: 10803fcc andi r2,r2,255 + 1005140: 1080201c xori r2,r2,128 + 1005144: 10bfe004 addi r2,r2,-128 + 1005148: d8800115 stw r2,4(sp) + 100514c: dfc00017 ldw ra,0(sp) + 1005150: dec00104 addi sp,sp,4 + 1005154: 10050381 jmpi 1005038 <_ZNSs14_M_replace_auxEmmmc> + 1005158: 10803fcc andi r2,r2,255 + 100515c: 1080201c xori r2,r2,128 + 1005160: 10bfe004 addi r2,r2,-128 + 1005164: 180d883a mov r6,r3 + 1005168: d8800115 stw r2,4(sp) + 100516c: dfc00017 ldw ra,0(sp) + 1005170: dec00104 addi sp,sp,4 + 1005174: 10050381 jmpi 1005038 <_ZNSs14_M_replace_auxEmmmc> + 1005178: 010040b4 movhi r4,258 + 100517c: 21042104 addi r4,r4,4228 + 1005180: 10084dc0 call 10084dc <_ZSt20__throw_out_of_rangePKc> + +01005184 <_ZNSs6insertEN9__gnu_cxx17__normal_iteratorIPcSsEEc>: + 1005184: 20800017 ldw r2,0(r4) + 1005188: defffc04 addi sp,sp,-16 + 100518c: 30c03fcc andi r3,r6,255 + 1005190: dc000115 stw r16,4(sp) + 1005194: 18c0201c xori r3,r3,128 + 1005198: 28a1c83a sub r16,r5,r2 + 100519c: dc400215 stw r17,8(sp) + 10051a0: 18ffe004 addi r3,r3,-128 + 10051a4: 2023883a mov r17,r4 + 10051a8: 01c00044 movi r7,1 + 10051ac: 800b883a mov r5,r16 + 10051b0: 000d883a mov r6,zero + 10051b4: d8c00015 stw r3,0(sp) + 10051b8: dfc00315 stw ra,12(sp) + 10051bc: 10050380 call 1005038 <_ZNSs14_M_replace_auxEmmmc> + 10051c0: 88800017 ldw r2,0(r17) + 10051c4: 00ffffc4 movi r3,-1 + 10051c8: 10ffff15 stw r3,-4(r2) + 10051cc: 1405883a add r2,r2,r16 + 10051d0: dfc00317 ldw ra,12(sp) + 10051d4: dc400217 ldw r17,8(sp) + 10051d8: dc000117 ldw r16,4(sp) + 10051dc: dec00404 addi sp,sp,16 + 10051e0: f800283a ret + +010051e4 <_ZNSs6insertEmmc>: + 10051e4: 20c00017 ldw r3,0(r4) + 10051e8: defffe04 addi sp,sp,-8 + 10051ec: dfc00115 stw ra,4(sp) + 10051f0: 18bffd17 ldw r2,-12(r3) + 10051f4: 11400a36 bltu r2,r5,1005220 <_ZNSs6insertEmmc+0x3c> + 10051f8: 38803fcc andi r2,r7,255 + 10051fc: 1080201c xori r2,r2,128 + 1005200: 300f883a mov r7,r6 + 1005204: 10bfe004 addi r2,r2,-128 + 1005208: 000d883a mov r6,zero + 100520c: d8800015 stw r2,0(sp) + 1005210: 10050380 call 1005038 <_ZNSs14_M_replace_auxEmmmc> + 1005214: dfc00117 ldw ra,4(sp) + 1005218: dec00204 addi sp,sp,8 + 100521c: f800283a ret + 1005220: 010040b4 movhi r4,258 + 1005224: 21042704 addi r4,r4,4252 + 1005228: 10084dc0 call 10084dc <_ZSt20__throw_out_of_rangePKc> + +0100522c <_ZNSs6assignEmc>: + 100522c: 20800017 ldw r2,0(r4) + 1005230: 30c03fcc andi r3,r6,255 + 1005234: 18c0201c xori r3,r3,128 + 1005238: 11bffd17 ldw r6,-12(r2) + 100523c: defffe04 addi sp,sp,-8 + 1005240: 280f883a mov r7,r5 + 1005244: 18ffe004 addi r3,r3,-128 + 1005248: 000b883a mov r5,zero + 100524c: dfc00115 stw ra,4(sp) + 1005250: d8c00015 stw r3,0(sp) + 1005254: 10050380 call 1005038 <_ZNSs14_M_replace_auxEmmmc> + 1005258: dfc00117 ldw ra,4(sp) + 100525c: dec00204 addi sp,sp,8 + 1005260: f800283a ret + +01005264 <_ZNSsaSEc>: + 1005264: 20800017 ldw r2,0(r4) + 1005268: 28c03fcc andi r3,r5,255 + 100526c: 18c0201c xori r3,r3,128 + 1005270: 11bffd17 ldw r6,-12(r2) + 1005274: defffd04 addi sp,sp,-12 + 1005278: 18ffe004 addi r3,r3,-128 + 100527c: 01c00044 movi r7,1 + 1005280: 000b883a mov r5,zero + 1005284: dc400115 stw r17,4(sp) + 1005288: dfc00215 stw ra,8(sp) + 100528c: 2023883a mov r17,r4 + 1005290: d8c00015 stw r3,0(sp) + 1005294: 10050380 call 1005038 <_ZNSs14_M_replace_auxEmmmc> + 1005298: 8805883a mov r2,r17 + 100529c: dfc00217 ldw ra,8(sp) + 10052a0: dc400117 ldw r17,4(sp) + 10052a4: dec00304 addi sp,sp,12 + 10052a8: f800283a ret + +010052ac <_ZNSs6insertEN9__gnu_cxx17__normal_iteratorIPcSsEEmc>: + 10052ac: 20800017 ldw r2,0(r4) + 10052b0: 3a003fcc andi r8,r7,255 + 10052b4: 4200201c xori r8,r8,128 + 10052b8: defffe04 addi sp,sp,-8 + 10052bc: 423fe004 addi r8,r8,-128 + 10052c0: 300f883a mov r7,r6 + 10052c4: 288bc83a sub r5,r5,r2 + 10052c8: 000d883a mov r6,zero + 10052cc: dfc00115 stw ra,4(sp) + 10052d0: da000015 stw r8,0(sp) + 10052d4: 10050380 call 1005038 <_ZNSs14_M_replace_auxEmmmc> + 10052d8: dfc00117 ldw ra,4(sp) + 10052dc: dec00204 addi sp,sp,8 + 10052e0: f800283a ret + +010052e4 <_ZNSs5eraseEN9__gnu_cxx17__normal_iteratorIPcSsEES2_>: + 10052e4: 20800017 ldw r2,0(r4) + 10052e8: defffd04 addi sp,sp,-12 + 10052ec: dc400015 stw r17,0(sp) + 10052f0: 28a3c83a sub r17,r5,r2 + 10052f4: dc800115 stw r18,4(sp) + 10052f8: 314dc83a sub r6,r6,r5 + 10052fc: 2025883a mov r18,r4 + 1005300: 880b883a mov r5,r17 + 1005304: 000f883a mov r7,zero + 1005308: dfc00215 stw ra,8(sp) + 100530c: 1004b9c0 call 1004b9c <_ZNSs9_M_mutateEmmm> + 1005310: 90800017 ldw r2,0(r18) + 1005314: 00ffffc4 movi r3,-1 + 1005318: 10ffff15 stw r3,-4(r2) + 100531c: 1445883a add r2,r2,r17 + 1005320: dfc00217 ldw ra,8(sp) + 1005324: dc800117 ldw r18,4(sp) + 1005328: dc400017 ldw r17,0(sp) + 100532c: dec00304 addi sp,sp,12 + 1005330: f800283a ret + +01005334 <_ZNSs5eraseEN9__gnu_cxx17__normal_iteratorIPcSsEE>: + 1005334: 20800017 ldw r2,0(r4) + 1005338: defffd04 addi sp,sp,-12 + 100533c: dc000015 stw r16,0(sp) + 1005340: 28a1c83a sub r16,r5,r2 + 1005344: dc400115 stw r17,4(sp) + 1005348: 01800044 movi r6,1 + 100534c: 2023883a mov r17,r4 + 1005350: 000f883a mov r7,zero + 1005354: 800b883a mov r5,r16 + 1005358: dfc00215 stw ra,8(sp) + 100535c: 1004b9c0 call 1004b9c <_ZNSs9_M_mutateEmmm> + 1005360: 88800017 ldw r2,0(r17) + 1005364: 00ffffc4 movi r3,-1 + 1005368: 10ffff15 stw r3,-4(r2) + 100536c: 1405883a add r2,r2,r16 + 1005370: dfc00217 ldw ra,8(sp) + 1005374: dc400117 ldw r17,4(sp) + 1005378: dc000017 ldw r16,0(sp) + 100537c: dec00304 addi sp,sp,12 + 1005380: f800283a ret + +01005384 <_ZNSs5eraseEmm>: + 1005384: 20800017 ldw r2,0(r4) + 1005388: defffe04 addi sp,sp,-8 + 100538c: dc000015 stw r16,0(sp) + 1005390: 10bffd17 ldw r2,-12(r2) + 1005394: dfc00115 stw ra,4(sp) + 1005398: 2021883a mov r16,r4 + 100539c: 11401136 bltu r2,r5,10053e4 <_ZNSs5eraseEmm+0x60> + 10053a0: 1145c83a sub r2,r2,r5 + 10053a4: 11800736 bltu r2,r6,10053c4 <_ZNSs5eraseEmm+0x40> + 10053a8: 000f883a mov r7,zero + 10053ac: 1004b9c0 call 1004b9c <_ZNSs9_M_mutateEmmm> + 10053b0: 8005883a mov r2,r16 + 10053b4: dfc00117 ldw ra,4(sp) + 10053b8: dc000017 ldw r16,0(sp) + 10053bc: dec00204 addi sp,sp,8 + 10053c0: f800283a ret + 10053c4: 100d883a mov r6,r2 + 10053c8: 000f883a mov r7,zero + 10053cc: 1004b9c0 call 1004b9c <_ZNSs9_M_mutateEmmm> + 10053d0: 8005883a mov r2,r16 + 10053d4: dfc00117 ldw ra,4(sp) + 10053d8: dc000017 ldw r16,0(sp) + 10053dc: dec00204 addi sp,sp,8 + 10053e0: f800283a ret + 10053e4: 010040b4 movhi r4,258 + 10053e8: 21042d04 addi r4,r4,4276 + 10053ec: 10084dc0 call 10084dc <_ZSt20__throw_out_of_rangePKc> + +010053f0 <_ZNSs6insertEmPKcm>: + 10053f0: defff904 addi sp,sp,-28 + 10053f4: dc000115 stw r16,4(sp) + 10053f8: 24000017 ldw r16,0(r4) + 10053fc: dd000515 stw r20,20(sp) + 1005400: dcc00415 stw r19,16(sp) + 1005404: 80fffd17 ldw r3,-12(r16) + 1005408: dc800315 stw r18,12(sp) + 100540c: dc400215 stw r17,8(sp) + 1005410: dfc00615 stw ra,24(sp) + 1005414: 3023883a mov r17,r6 + 1005418: 2029883a mov r20,r4 + 100541c: 2825883a mov r18,r5 + 1005420: 3827883a mov r19,r7 + 1005424: 81bffd04 addi r6,r16,-12 + 1005428: 19403d36 bltu r3,r5,1005520 <_ZNSs6insertEmPKcm+0x130> + 100542c: 00900034 movhi r2,16384 + 1005430: 10bfff04 addi r2,r2,-4 + 1005434: 10c5c83a sub r2,r2,r3 + 1005438: 11c03c36 bltu r2,r7,100552c <_ZNSs6insertEmPKcm+0x13c> + 100543c: 8c00102e bgeu r17,r16,1005480 <_ZNSs6insertEmPKcm+0x90> + 1005440: a009883a mov r4,r20 + 1005444: 900b883a mov r5,r18 + 1005448: 880f883a mov r7,r17 + 100544c: 000d883a mov r6,zero + 1005450: dcc00015 stw r19,0(sp) + 1005454: 1004dd40 call 1004dd4 <_ZNSs15_M_replace_safeEmmPKcm> + 1005458: 1029883a mov r20,r2 + 100545c: a005883a mov r2,r20 + 1005460: dfc00617 ldw ra,24(sp) + 1005464: dd000517 ldw r20,20(sp) + 1005468: dcc00417 ldw r19,16(sp) + 100546c: dc800317 ldw r18,12(sp) + 1005470: dc400217 ldw r17,8(sp) + 1005474: dc000117 ldw r16,4(sp) + 1005478: dec00704 addi sp,sp,28 + 100547c: f800283a ret + 1005480: 80c5883a add r2,r16,r3 + 1005484: 147fee36 bltu r2,r17,1005440 <_ZNSs6insertEmPKcm+0x50> + 1005488: 30800217 ldw r2,8(r6) + 100548c: 00bfec16 blt zero,r2,1005440 <_ZNSs6insertEmPKcm+0x50> + 1005490: 000d883a mov r6,zero + 1005494: 1004b9c0 call 1004b9c <_ZNSs9_M_mutateEmmm> + 1005498: a0c00017 ldw r3,0(r20) + 100549c: 8c05c83a sub r2,r17,r16 + 10054a0: 188b883a add r5,r3,r2 + 10054a4: 1ca1883a add r16,r3,r18 + 10054a8: 2cc7883a add r3,r5,r19 + 10054ac: 80c0062e bgeu r16,r3,10054c8 <_ZNSs6insertEmPKcm+0xd8> + 10054b0: 2c000e36 bltu r5,r16,10054ec <_ZNSs6insertEmPKcm+0xfc> + 10054b4: 00800044 movi r2,1 + 10054b8: 98801f1e bne r19,r2,1005538 <_ZNSs6insertEmPKcm+0x148> + 10054bc: 18800003 ldbu r2,0(r3) + 10054c0: 80800005 stb r2,0(r16) + 10054c4: 003fe506 br 100545c <_ZNSs6insertEmPKcm+0x6c> + 10054c8: 00800044 movi r2,1 + 10054cc: 9880031e bne r19,r2,10054dc <_ZNSs6insertEmPKcm+0xec> + 10054d0: 28800003 ldbu r2,0(r5) + 10054d4: 80800005 stb r2,0(r16) + 10054d8: 003fe006 br 100545c <_ZNSs6insertEmPKcm+0x6c> + 10054dc: 8009883a mov r4,r16 + 10054e0: 980d883a mov r6,r19 + 10054e4: 100aa3c0 call 100aa3c + 10054e8: 003fdc06 br 100545c <_ZNSs6insertEmPKcm+0x6c> + 10054ec: 8163c83a sub r17,r16,r5 + 10054f0: 00800044 movi r2,1 + 10054f4: 8880171e bne r17,r2,1005554 <_ZNSs6insertEmPKcm+0x164> + 10054f8: 28800003 ldbu r2,0(r5) + 10054fc: 80800005 stb r2,0(r16) + 1005500: 9c4dc83a sub r6,r19,r17 + 1005504: 00800044 movi r2,1 + 1005508: 84cb883a add r5,r16,r19 + 100550c: 8449883a add r4,r16,r17 + 1005510: 30800e1e bne r6,r2,100554c <_ZNSs6insertEmPKcm+0x15c> + 1005514: 28800003 ldbu r2,0(r5) + 1005518: 20800005 stb r2,0(r4) + 100551c: 003fcf06 br 100545c <_ZNSs6insertEmPKcm+0x6c> + 1005520: 010040b4 movhi r4,258 + 1005524: 21042704 addi r4,r4,4252 + 1005528: 10084dc0 call 10084dc <_ZSt20__throw_out_of_rangePKc> + 100552c: 010040b4 movhi r4,258 + 1005530: 21042704 addi r4,r4,4252 + 1005534: 100866c0 call 100866c <_ZSt20__throw_length_errorPKc> + 1005538: 8009883a mov r4,r16 + 100553c: 180b883a mov r5,r3 + 1005540: 980d883a mov r6,r19 + 1005544: 100aa3c0 call 100aa3c + 1005548: 003fc406 br 100545c <_ZNSs6insertEmPKcm+0x6c> + 100554c: 100aa3c0 call 100aa3c + 1005550: 003fc206 br 100545c <_ZNSs6insertEmPKcm+0x6c> + 1005554: 8009883a mov r4,r16 + 1005558: 880d883a mov r6,r17 + 100555c: 100aa3c0 call 100aa3c + 1005560: 003fe706 br 1005500 <_ZNSs6insertEmPKcm+0x110> + +01005564 <_ZNSs6insertEmPKc>: + 1005564: defffc04 addi sp,sp,-16 + 1005568: dd400215 stw r21,8(sp) + 100556c: dcc00115 stw r19,4(sp) + 1005570: dc400015 stw r17,0(sp) + 1005574: 2027883a mov r19,r4 + 1005578: dfc00315 stw ra,12(sp) + 100557c: 3009883a mov r4,r6 + 1005580: 3023883a mov r17,r6 + 1005584: 282b883a mov r21,r5 + 1005588: 100b1640 call 100b164 + 100558c: a80b883a mov r5,r21 + 1005590: 9809883a mov r4,r19 + 1005594: 880d883a mov r6,r17 + 1005598: 100f883a mov r7,r2 + 100559c: dfc00317 ldw ra,12(sp) + 10055a0: dd400217 ldw r21,8(sp) + 10055a4: dcc00117 ldw r19,4(sp) + 10055a8: dc400017 ldw r17,0(sp) + 10055ac: dec00404 addi sp,sp,16 + 10055b0: 10053f01 jmpi 10053f0 <_ZNSs6insertEmPKcm> + +010055b4 <_ZNSs6insertEmRKSsmm>: + 10055b4: 31800017 ldw r6,0(r6) + 10055b8: deffff04 addi sp,sp,-4 + 10055bc: 3805883a mov r2,r7 + 10055c0: 30fffd17 ldw r3,-12(r6) + 10055c4: dfc00015 stw ra,0(sp) + 10055c8: d9c00117 ldw r7,4(sp) + 10055cc: 18800a36 bltu r3,r2,10055f8 <_ZNSs6insertEmRKSsmm+0x44> + 10055d0: 1887c83a sub r3,r3,r2 + 10055d4: 308d883a add r6,r6,r2 + 10055d8: 19c00336 bltu r3,r7,10055e8 <_ZNSs6insertEmRKSsmm+0x34> + 10055dc: dfc00017 ldw ra,0(sp) + 10055e0: dec00104 addi sp,sp,4 + 10055e4: 10053f01 jmpi 10053f0 <_ZNSs6insertEmPKcm> + 10055e8: 180f883a mov r7,r3 + 10055ec: dfc00017 ldw ra,0(sp) + 10055f0: dec00104 addi sp,sp,4 + 10055f4: 10053f01 jmpi 10053f0 <_ZNSs6insertEmPKcm> + 10055f8: 010040b4 movhi r4,258 + 10055fc: 21042704 addi r4,r4,4252 + 1005600: 10084dc0 call 10084dc <_ZSt20__throw_out_of_rangePKc> + +01005604 <_ZNSs6insertEmRKSs>: + 1005604: 31800017 ldw r6,0(r6) + 1005608: 31fffd17 ldw r7,-12(r6) + 100560c: 10053f01 jmpi 10053f0 <_ZNSs6insertEmPKcm> + +01005610 <_ZNSs5clearEv>: + 1005610: 20800017 ldw r2,0(r4) + 1005614: 000b883a mov r5,zero + 1005618: 000f883a mov r7,zero + 100561c: 11bffd17 ldw r6,-12(r2) + 1005620: 1004b9c1 jmpi 1004b9c <_ZNSs9_M_mutateEmmm> + +01005624 <_ZNSs12_M_leak_hardEv>: + 1005624: 22000017 ldw r8,0(r4) + 1005628: defffe04 addi sp,sp,-8 + 100562c: 008040f4 movhi r2,259 + 1005630: 10a52f04 addi r2,r2,-27460 + 1005634: 40fffd04 addi r3,r8,-12 + 1005638: dc000015 stw r16,0(sp) + 100563c: dfc00115 stw ra,4(sp) + 1005640: 2021883a mov r16,r4 + 1005644: 18800726 beq r3,r2,1005664 <_ZNSs12_M_leak_hardEv+0x40> + 1005648: 18800217 ldw r2,8(r3) + 100564c: 000b883a mov r5,zero + 1005650: 000d883a mov r6,zero + 1005654: 000f883a mov r7,zero + 1005658: 00800616 blt zero,r2,1005674 <_ZNSs12_M_leak_hardEv+0x50> + 100565c: 00bfffc4 movi r2,-1 + 1005660: 40bfff15 stw r2,-4(r8) + 1005664: dfc00117 ldw ra,4(sp) + 1005668: dc000017 ldw r16,0(sp) + 100566c: dec00204 addi sp,sp,8 + 1005670: f800283a ret + 1005674: 1004b9c0 call 1004b9c <_ZNSs9_M_mutateEmmm> + 1005678: 82000017 ldw r8,0(r16) + 100567c: 003ff706 br 100565c <_ZNSs12_M_leak_hardEv+0x38> + +01005680 <_ZNSs7_M_leakEv>: + 1005680: 20800017 ldw r2,0(r4) + 1005684: 10ffff17 ldw r3,-4(r2) + 1005688: 1800010e bge r3,zero,1005690 <_ZNSs7_M_leakEv+0x10> + 100568c: f800283a ret + 1005690: 10056241 jmpi 1005624 <_ZNSs12_M_leak_hardEv> + +01005694 <_ZNSs2atEm>: + 1005694: 20c00017 ldw r3,0(r4) + 1005698: defffd04 addi sp,sp,-12 + 100569c: dc000015 stw r16,0(sp) + 10056a0: 18bffd17 ldw r2,-12(r3) + 10056a4: 2821883a mov r16,r5 + 10056a8: dc400115 stw r17,4(sp) + 10056ac: dfc00215 stw ra,8(sp) + 10056b0: 2023883a mov r17,r4 + 10056b4: 197ffd04 addi r5,r3,-12 + 10056b8: 80800a2e bgeu r16,r2,10056e4 <_ZNSs2atEm+0x50> + 10056bc: 28800217 ldw r2,8(r5) + 10056c0: 10000216 blt r2,zero,10056cc <_ZNSs2atEm+0x38> + 10056c4: 10056240 call 1005624 <_ZNSs12_M_leak_hardEv> + 10056c8: 88c00017 ldw r3,0(r17) + 10056cc: 80c5883a add r2,r16,r3 + 10056d0: dfc00217 ldw ra,8(sp) + 10056d4: dc400117 ldw r17,4(sp) + 10056d8: dc000017 ldw r16,0(sp) + 10056dc: dec00304 addi sp,sp,12 + 10056e0: f800283a ret + 10056e4: 010040b4 movhi r4,258 + 10056e8: 2103df04 addi r4,r4,3964 + 10056ec: 10084dc0 call 10084dc <_ZSt20__throw_out_of_rangePKc> + +010056f0 <_ZNSsixEm>: + 10056f0: 20c00017 ldw r3,0(r4) + 10056f4: defffd04 addi sp,sp,-12 + 10056f8: dc400115 stw r17,4(sp) + 10056fc: 18bfff17 ldw r2,-4(r3) + 1005700: dc000015 stw r16,0(sp) + 1005704: dfc00215 stw ra,8(sp) + 1005708: 2021883a mov r16,r4 + 100570c: 2823883a mov r17,r5 + 1005710: 10000216 blt r2,zero,100571c <_ZNSsixEm+0x2c> + 1005714: 10056240 call 1005624 <_ZNSs12_M_leak_hardEv> + 1005718: 80c00017 ldw r3,0(r16) + 100571c: 88c5883a add r2,r17,r3 + 1005720: dfc00217 ldw ra,8(sp) + 1005724: dc400117 ldw r17,4(sp) + 1005728: dc000017 ldw r16,0(sp) + 100572c: dec00304 addi sp,sp,12 + 1005730: f800283a ret + +01005734 <_ZNSs3endEv>: + 1005734: 20c00017 ldw r3,0(r4) + 1005738: defffe04 addi sp,sp,-8 + 100573c: dc000015 stw r16,0(sp) + 1005740: 18bfff17 ldw r2,-4(r3) + 1005744: dfc00115 stw ra,4(sp) + 1005748: 2021883a mov r16,r4 + 100574c: 10000216 blt r2,zero,1005758 <_ZNSs3endEv+0x24> + 1005750: 10056240 call 1005624 <_ZNSs12_M_leak_hardEv> + 1005754: 80c00017 ldw r3,0(r16) + 1005758: 18bffd17 ldw r2,-12(r3) + 100575c: 1885883a add r2,r3,r2 + 1005760: dfc00117 ldw ra,4(sp) + 1005764: dc000017 ldw r16,0(sp) + 1005768: dec00204 addi sp,sp,8 + 100576c: f800283a ret + +01005770 <_ZNSs5beginEv>: + 1005770: 20c00017 ldw r3,0(r4) + 1005774: defffe04 addi sp,sp,-8 + 1005778: dc000015 stw r16,0(sp) + 100577c: 18bfff17 ldw r2,-4(r3) + 1005780: dfc00115 stw ra,4(sp) + 1005784: 2021883a mov r16,r4 + 1005788: 10000216 blt r2,zero,1005794 <_ZNSs5beginEv+0x24> + 100578c: 10056240 call 1005624 <_ZNSs12_M_leak_hardEv> + 1005790: 80c00017 ldw r3,0(r16) + 1005794: 1805883a mov r2,r3 + 1005798: dfc00117 ldw ra,4(sp) + 100579c: dc000017 ldw r16,0(sp) + 10057a0: dec00204 addi sp,sp,8 + 10057a4: f800283a ret + +010057a8 <_ZNSs4rendEv>: + 10057a8: 28c00017 ldw r3,0(r5) + 10057ac: defffd04 addi sp,sp,-12 + 10057b0: dc400115 stw r17,4(sp) + 10057b4: 18bfff17 ldw r2,-4(r3) + 10057b8: dc000015 stw r16,0(sp) + 10057bc: 2023883a mov r17,r4 + 10057c0: dfc00215 stw ra,8(sp) + 10057c4: 2821883a mov r16,r5 + 10057c8: 2809883a mov r4,r5 + 10057cc: 10000216 blt r2,zero,10057d8 <_ZNSs4rendEv+0x30> + 10057d0: 10056240 call 1005624 <_ZNSs12_M_leak_hardEv> + 10057d4: 80c00017 ldw r3,0(r16) + 10057d8: 8805883a mov r2,r17 + 10057dc: 88c00015 stw r3,0(r17) + 10057e0: dfc00217 ldw ra,8(sp) + 10057e4: dc400117 ldw r17,4(sp) + 10057e8: dc000017 ldw r16,0(sp) + 10057ec: dec00304 addi sp,sp,12 + 10057f0: f800283a ret + +010057f4 <_ZNSs6rbeginEv>: + 10057f4: defffd04 addi sp,sp,-12 + 10057f8: dc000015 stw r16,0(sp) + 10057fc: 2821883a mov r16,r5 + 1005800: 29400017 ldw r5,0(r5) + 1005804: dc400115 stw r17,4(sp) + 1005808: dfc00215 stw ra,8(sp) + 100580c: 28bfff17 ldw r2,-4(r5) + 1005810: 2023883a mov r17,r4 + 1005814: 8009883a mov r4,r16 + 1005818: 10000216 blt r2,zero,1005824 <_ZNSs6rbeginEv+0x30> + 100581c: 10056240 call 1005624 <_ZNSs12_M_leak_hardEv> + 1005820: 81400017 ldw r5,0(r16) + 1005824: 28fffd17 ldw r3,-12(r5) + 1005828: 8805883a mov r2,r17 + 100582c: 28c7883a add r3,r5,r3 + 1005830: 88c00015 stw r3,0(r17) + 1005834: dfc00217 ldw ra,8(sp) + 1005838: dc400117 ldw r17,4(sp) + 100583c: dc000017 ldw r16,0(sp) + 1005840: dec00304 addi sp,sp,12 + 1005844: f800283a ret + +01005848 <_ZNSs6resizeEmc>: + 1005848: 20c00017 ldw r3,0(r4) + 100584c: deffff04 addi sp,sp,-4 + 1005850: 00900034 movhi r2,16384 + 1005854: 10bfff04 addi r2,r2,-4 + 1005858: 3011883a mov r8,r6 + 100585c: dfc00015 stw ra,0(sp) + 1005860: 19bffd17 ldw r6,-12(r3) + 1005864: 11401136 bltu r2,r5,10058ac <_ZNSs6resizeEmc+0x64> + 1005868: 31400936 bltu r6,r5,1005890 <_ZNSs6resizeEmc+0x48> + 100586c: 29800336 bltu r5,r6,100587c <_ZNSs6resizeEmc+0x34> + 1005870: dfc00017 ldw ra,0(sp) + 1005874: dec00104 addi sp,sp,4 + 1005878: f800283a ret + 100587c: 314dc83a sub r6,r6,r5 + 1005880: 000f883a mov r7,zero + 1005884: dfc00017 ldw ra,0(sp) + 1005888: dec00104 addi sp,sp,4 + 100588c: 1004b9c1 jmpi 1004b9c <_ZNSs9_M_mutateEmmm> + 1005890: 298bc83a sub r5,r5,r6 + 1005894: 41803fcc andi r6,r8,255 + 1005898: 3180201c xori r6,r6,128 + 100589c: 31bfe004 addi r6,r6,-128 + 10058a0: dfc00017 ldw ra,0(sp) + 10058a4: dec00104 addi sp,sp,4 + 10058a8: 10045841 jmpi 1004584 <_ZNSs6appendEmc> + 10058ac: 010040b4 movhi r4,258 + 10058b0: 21043204 addi r4,r4,4296 + 10058b4: 100866c0 call 100866c <_ZSt20__throw_length_errorPKc> + +010058b8 <_ZNSs6resizeEm>: + 10058b8: 000d883a mov r6,zero + 10058bc: 10058481 jmpi 1005848 <_ZNSs6resizeEmc> + +010058c0 <_ZStplIcSt11char_traitsIcESaIcEESbIT_T0_T1_EPKS3_RKS6_>: + 10058c0: deffe804 addi sp,sp,-96 + 10058c4: 00804034 movhi r2,256 + 10058c8: 109a9704 addi r2,r2,27228 + 10058cc: 00c040b4 movhi r3,258 + 10058d0: 18c2ee44 addi r3,r3,3001 + 10058d4: d8800715 stw r2,28(sp) + 10058d8: d9001115 stw r4,68(sp) + 10058dc: 00804034 movhi r2,256 + 10058e0: 10966604 addi r2,r2,22936 + 10058e4: d9000104 addi r4,sp,4 + 10058e8: d8c00815 stw r3,32(sp) + 10058ec: d9401215 stw r5,72(sp) + 10058f0: dfc01715 stw ra,92(sp) + 10058f4: d8800a15 stw r2,40(sp) + 10058f8: d9801315 stw r6,76(sp) + 10058fc: df001615 stw fp,88(sp) + 1005900: ddc01515 stw r23,84(sp) + 1005904: dec00915 stw sp,36(sp) + 1005908: dec00b15 stw sp,44(sp) + 100590c: 1009c1c0 call 1009c1c <_Unwind_SjLj_Register> + 1005910: d9001217 ldw r4,72(sp) + 1005914: 100b1640 call 100b164 + 1005918: 00c040f4 movhi r3,259 + 100591c: 18e52f04 addi r3,r3,-27460 + 1005920: d8801415 stw r2,80(sp) + 1005924: 18800304 addi r2,r3,12 + 1005928: d8c01117 ldw r3,68(sp) + 100592c: d9001117 ldw r4,68(sp) + 1005930: 18800015 stw r2,0(r3) + 1005934: d8801317 ldw r2,76(sp) + 1005938: 10c00017 ldw r3,0(r2) + 100593c: d8801117 ldw r2,68(sp) + 1005940: 197ffd17 ldw r5,-12(r3) + 1005944: d8c01417 ldw r3,80(sp) + 1005948: d8800f15 stw r2,60(sp) + 100594c: 00800084 movi r2,2 + 1005950: d8800215 stw r2,8(sp) + 1005954: 194b883a add r5,r3,r5 + 1005958: 10043d40 call 10043d4 <_ZNSs7reserveEm> + 100595c: d9001117 ldw r4,68(sp) + 1005960: d9401217 ldw r5,72(sp) + 1005964: d9801417 ldw r6,80(sp) + 1005968: 10046640 call 1004664 <_ZNSs6appendEPKcm> + 100596c: d9001117 ldw r4,68(sp) + 1005970: d9401317 ldw r5,76(sp) + 1005974: 10048d80 call 10048d8 <_ZNSs6appendERKSs> + 1005978: d9000104 addi r4,sp,4 + 100597c: 1009c2c0 call 1009c2c <_Unwind_SjLj_Unregister> + 1005980: d8801117 ldw r2,68(sp) + 1005984: dfc01717 ldw ra,92(sp) + 1005988: df001617 ldw fp,88(sp) + 100598c: ddc01517 ldw r23,84(sp) + 1005990: dec01804 addi sp,sp,96 + 1005994: f800283a ret + 1005998: d8c00217 ldw r3,8(sp) + 100599c: 00800044 movi r2,1 + 10059a0: d9000317 ldw r4,12(sp) + 10059a4: 18800326 beq r3,r2,10059b4 <_ZStplIcSt11char_traitsIcESaIcEESbIT_T0_T1_EPKS3_RKS6_+0xf4> + 10059a8: 00bfffc4 movi r2,-1 + 10059ac: d8800215 stw r2,8(sp) + 10059b0: 1009ee80 call 1009ee8 <_Unwind_SjLj_Resume> + 10059b4: d8c00f17 ldw r3,60(sp) + 10059b8: d9001015 stw r4,64(sp) + 10059bc: 18800017 ldw r2,0(r3) + 10059c0: 00c040f4 movhi r3,259 + 10059c4: 18e52f04 addi r3,r3,-27460 + 10059c8: 10bffd04 addi r2,r2,-12 + 10059cc: d8800e15 stw r2,56(sp) + 10059d0: 1880041e bne r3,r2,10059e4 <_ZStplIcSt11char_traitsIcESaIcEESbIT_T0_T1_EPKS3_RKS6_+0x124> + 10059d4: d9001017 ldw r4,64(sp) + 10059d8: 00bfffc4 movi r2,-1 + 10059dc: d8800215 stw r2,8(sp) + 10059e0: 1009ee80 call 1009ee8 <_Unwind_SjLj_Resume> + 10059e4: 00800044 movi r2,1 + 10059e8: d8800215 stw r2,8(sp) + 10059ec: d8800e17 ldw r2,56(sp) + 10059f0: 017fffc4 movi r5,-1 + 10059f4: 11000204 addi r4,r2,8 + 10059f8: 100617c0 call 100617c <_ZN9__gnu_cxx18__exchange_and_addEPVii> + 10059fc: 00bff516 blt zero,r2,10059d4 <_ZStplIcSt11char_traitsIcESaIcEESbIT_T0_T1_EPKS3_RKS6_+0x114> + 1005a00: d9000e17 ldw r4,56(sp) + 1005a04: d80b883a mov r5,sp + 1005a08: 1002c0c0 call 1002c0c <_ZNSs4_Rep10_M_destroyERKSaIcE> + 1005a0c: 003ff106 br 10059d4 <_ZStplIcSt11char_traitsIcESaIcEESbIT_T0_T1_EPKS3_RKS6_+0x114> + +01005a10 <_ZStplIcSt11char_traitsIcESaIcEESbIT_T0_T1_ERKS6_S8_>: + 1005a10: deffe904 addi sp,sp,-92 + 1005a14: 00804034 movhi r2,256 + 1005a18: 109a9704 addi r2,r2,27228 + 1005a1c: 00c040b4 movhi r3,258 + 1005a20: 18c2f044 addi r3,r3,3009 + 1005a24: d8800715 stw r2,28(sp) + 1005a28: d9001115 stw r4,68(sp) + 1005a2c: 00804034 movhi r2,256 + 1005a30: 1096ac04 addi r2,r2,23216 + 1005a34: d9000104 addi r4,sp,4 + 1005a38: dfc01615 stw ra,88(sp) + 1005a3c: d8c00815 stw r3,32(sp) + 1005a40: d8800a15 stw r2,40(sp) + 1005a44: d9801315 stw r6,76(sp) + 1005a48: d9401215 stw r5,72(sp) + 1005a4c: df001515 stw fp,84(sp) + 1005a50: ddc01415 stw r23,80(sp) + 1005a54: dec00915 stw sp,36(sp) + 1005a58: dec00b15 stw sp,44(sp) + 1005a5c: 1009c1c0 call 1009c1c <_Unwind_SjLj_Register> + 1005a60: d9401217 ldw r5,72(sp) + 1005a64: d9001117 ldw r4,68(sp) + 1005a68: 00bfffc4 movi r2,-1 + 1005a6c: d8800215 stw r2,8(sp) + 1005a70: 10040640 call 1004064 <_ZNSsC1ERKSs> + 1005a74: 00800084 movi r2,2 + 1005a78: d8800215 stw r2,8(sp) + 1005a7c: d8801117 ldw r2,68(sp) + 1005a80: d9401317 ldw r5,76(sp) + 1005a84: d8801015 stw r2,64(sp) + 1005a88: 1009883a mov r4,r2 + 1005a8c: 10048d80 call 10048d8 <_ZNSs6appendERKSs> + 1005a90: d9000104 addi r4,sp,4 + 1005a94: 1009c2c0 call 1009c2c <_Unwind_SjLj_Unregister> + 1005a98: d8801117 ldw r2,68(sp) + 1005a9c: dfc01617 ldw ra,88(sp) + 1005aa0: df001517 ldw fp,84(sp) + 1005aa4: ddc01417 ldw r23,80(sp) + 1005aa8: dec01704 addi sp,sp,92 + 1005aac: f800283a ret + 1005ab0: d8c00217 ldw r3,8(sp) + 1005ab4: 00800044 movi r2,1 + 1005ab8: d9000317 ldw r4,12(sp) + 1005abc: 18800326 beq r3,r2,1005acc <_ZStplIcSt11char_traitsIcESaIcEESbIT_T0_T1_ERKS6_S8_+0xbc> + 1005ac0: 00bfffc4 movi r2,-1 + 1005ac4: d8800215 stw r2,8(sp) + 1005ac8: 1009ee80 call 1009ee8 <_Unwind_SjLj_Resume> + 1005acc: d8801017 ldw r2,64(sp) + 1005ad0: d9000f15 stw r4,60(sp) + 1005ad4: 10c00017 ldw r3,0(r2) + 1005ad8: 008040f4 movhi r2,259 + 1005adc: 10a52f04 addi r2,r2,-27460 + 1005ae0: 18fffd04 addi r3,r3,-12 + 1005ae4: d8c00e15 stw r3,56(sp) + 1005ae8: 1880041e bne r3,r2,1005afc <_ZStplIcSt11char_traitsIcESaIcEESbIT_T0_T1_ERKS6_S8_+0xec> + 1005aec: d9000f17 ldw r4,60(sp) + 1005af0: 00bfffc4 movi r2,-1 + 1005af4: d8800215 stw r2,8(sp) + 1005af8: 1009ee80 call 1009ee8 <_Unwind_SjLj_Resume> + 1005afc: 00800044 movi r2,1 + 1005b00: d8800215 stw r2,8(sp) + 1005b04: 19000204 addi r4,r3,8 + 1005b08: 017fffc4 movi r5,-1 + 1005b0c: 100617c0 call 100617c <_ZN9__gnu_cxx18__exchange_and_addEPVii> + 1005b10: 00bff616 blt zero,r2,1005aec <_ZStplIcSt11char_traitsIcESaIcEESbIT_T0_T1_ERKS6_S8_+0xdc> + 1005b14: d9000e17 ldw r4,56(sp) + 1005b18: d80b883a mov r5,sp + 1005b1c: 1002c0c0 call 1002c0c <_ZNSs4_Rep10_M_destroyERKSaIcE> + 1005b20: 003ff206 br 1005aec <_ZStplIcSt11char_traitsIcESaIcEESbIT_T0_T1_ERKS6_S8_+0xdc> + +01005b24 <_ZNSs4swapERSs>: + 1005b24: 21c00017 ldw r7,0(r4) + 1005b28: 38fffd04 addi r3,r7,-12 + 1005b2c: 18800217 ldw r2,8(r3) + 1005b30: 1000010e bge r2,zero,1005b38 <_ZNSs4swapERSs+0x14> + 1005b34: 18000215 stw zero,8(r3) + 1005b38: 29800017 ldw r6,0(r5) + 1005b3c: 30fffd04 addi r3,r6,-12 + 1005b40: 18800217 ldw r2,8(r3) + 1005b44: 1000010e bge r2,zero,1005b4c <_ZNSs4swapERSs+0x28> + 1005b48: 18000215 stw zero,8(r3) + 1005b4c: 21800015 stw r6,0(r4) + 1005b50: 29c00015 stw r7,0(r5) + 1005b54: f800283a ret + +01005b58 <_ZStplIcSt11char_traitsIcESaIcEESbIT_T0_T1_ES3_RKS6_>: + 1005b58: deffe904 addi sp,sp,-92 + 1005b5c: 00804034 movhi r2,256 + 1005b60: 109a9704 addi r2,r2,27228 + 1005b64: 00c040b4 movhi r3,258 + 1005b68: 18c2f244 addi r3,r3,3017 + 1005b6c: d8800715 stw r2,28(sp) + 1005b70: d9001115 stw r4,68(sp) + 1005b74: 00804034 movhi r2,256 + 1005b78: 10970b04 addi r2,r2,23596 + 1005b7c: d9000104 addi r4,sp,4 + 1005b80: d8c00815 stw r3,32(sp) + 1005b84: d8800a15 stw r2,40(sp) + 1005b88: d9401205 stb r5,72(sp) + 1005b8c: dfc01615 stw ra,88(sp) + 1005b90: df001515 stw fp,84(sp) + 1005b94: ddc01415 stw r23,80(sp) + 1005b98: dec00915 stw sp,36(sp) + 1005b9c: dec00b15 stw sp,44(sp) + 1005ba0: d9801315 stw r6,76(sp) + 1005ba4: 1009c1c0 call 1009c1c <_Unwind_SjLj_Register> + 1005ba8: 00c040f4 movhi r3,259 + 1005bac: 18e52f04 addi r3,r3,-27460 + 1005bb0: 18800304 addi r2,r3,12 + 1005bb4: d8c01117 ldw r3,68(sp) + 1005bb8: 18800015 stw r2,0(r3) + 1005bbc: d8801317 ldw r2,76(sp) + 1005bc0: 10c00017 ldw r3,0(r2) + 1005bc4: 00800084 movi r2,2 + 1005bc8: 197ffd17 ldw r5,-12(r3) + 1005bcc: d8c01117 ldw r3,68(sp) + 1005bd0: d8800215 stw r2,8(sp) + 1005bd4: 29400044 addi r5,r5,1 + 1005bd8: d8c00f15 stw r3,60(sp) + 1005bdc: 1809883a mov r4,r3 + 1005be0: 10043d40 call 10043d4 <_ZNSs7reserveEm> + 1005be4: d8801203 ldbu r2,72(sp) + 1005be8: d9001117 ldw r4,68(sp) + 1005bec: 01400044 movi r5,1 + 1005bf0: 11803fcc andi r6,r2,255 + 1005bf4: 3180201c xori r6,r6,128 + 1005bf8: 31bfe004 addi r6,r6,-128 + 1005bfc: 10045840 call 1004584 <_ZNSs6appendEmc> + 1005c00: d9001117 ldw r4,68(sp) + 1005c04: d9401317 ldw r5,76(sp) + 1005c08: 10048d80 call 10048d8 <_ZNSs6appendERKSs> + 1005c0c: d9000104 addi r4,sp,4 + 1005c10: 1009c2c0 call 1009c2c <_Unwind_SjLj_Unregister> + 1005c14: d8801117 ldw r2,68(sp) + 1005c18: dfc01617 ldw ra,88(sp) + 1005c1c: df001517 ldw fp,84(sp) + 1005c20: ddc01417 ldw r23,80(sp) + 1005c24: dec01704 addi sp,sp,92 + 1005c28: f800283a ret + 1005c2c: d8c00217 ldw r3,8(sp) + 1005c30: 00800044 movi r2,1 + 1005c34: d9000317 ldw r4,12(sp) + 1005c38: 18800326 beq r3,r2,1005c48 <_ZStplIcSt11char_traitsIcESaIcEESbIT_T0_T1_ES3_RKS6_+0xf0> + 1005c3c: 00bfffc4 movi r2,-1 + 1005c40: d8800215 stw r2,8(sp) + 1005c44: 1009ee80 call 1009ee8 <_Unwind_SjLj_Resume> + 1005c48: d8c00f17 ldw r3,60(sp) + 1005c4c: d9001015 stw r4,64(sp) + 1005c50: 18800017 ldw r2,0(r3) + 1005c54: 00c040f4 movhi r3,259 + 1005c58: 18e52f04 addi r3,r3,-27460 + 1005c5c: 10bffd04 addi r2,r2,-12 + 1005c60: d8800e15 stw r2,56(sp) + 1005c64: 1880041e bne r3,r2,1005c78 <_ZStplIcSt11char_traitsIcESaIcEESbIT_T0_T1_ES3_RKS6_+0x120> + 1005c68: d9001017 ldw r4,64(sp) + 1005c6c: 00bfffc4 movi r2,-1 + 1005c70: d8800215 stw r2,8(sp) + 1005c74: 1009ee80 call 1009ee8 <_Unwind_SjLj_Resume> + 1005c78: 00800044 movi r2,1 + 1005c7c: d8800215 stw r2,8(sp) + 1005c80: d8800e17 ldw r2,56(sp) + 1005c84: 017fffc4 movi r5,-1 + 1005c88: 11000204 addi r4,r2,8 + 1005c8c: 100617c0 call 100617c <_ZN9__gnu_cxx18__exchange_and_addEPVii> + 1005c90: 00bff516 blt zero,r2,1005c68 <_ZStplIcSt11char_traitsIcESaIcEESbIT_T0_T1_ES3_RKS6_+0x110> + 1005c94: d9000e17 ldw r4,56(sp) + 1005c98: d80b883a mov r5,sp + 1005c9c: 1002c0c0 call 1002c0c <_ZNSs4_Rep10_M_destroyERKSaIcE> + 1005ca0: 003ff106 br 1005c68 <_ZStplIcSt11char_traitsIcESaIcEESbIT_T0_T1_ES3_RKS6_+0x110> + +01005ca4 <_ZNSs7replaceEmmPKcm>: + 1005ca4: deffe304 addi sp,sp,-116 + 1005ca8: 00804034 movhi r2,256 + 1005cac: 1097c204 addi r2,r2,24328 + 1005cb0: d8800c15 stw r2,48(sp) + 1005cb4: d8800104 addi r2,sp,4 + 1005cb8: 00c040b4 movhi r3,258 + 1005cbc: 18c2f444 addi r3,r3,3025 + 1005cc0: d9001615 stw r4,88(sp) + 1005cc4: d8800b15 stw r2,44(sp) + 1005cc8: d9000304 addi r4,sp,12 + 1005ccc: 00804034 movhi r2,256 + 1005cd0: 109a9704 addi r2,r2,27228 + 1005cd4: d8c00a15 stw r3,40(sp) + 1005cd8: d9401715 stw r5,92(sp) + 1005cdc: d9801815 stw r6,96(sp) + 1005ce0: d9c01915 stw r7,100(sp) + 1005ce4: dfc01c15 stw ra,112(sp) + 1005ce8: df001b15 stw fp,108(sp) + 1005cec: ddc01a15 stw r23,104(sp) + 1005cf0: dec00d15 stw sp,52(sp) + 1005cf4: d8800915 stw r2,36(sp) + 1005cf8: 1009c1c0 call 1009c1c <_Unwind_SjLj_Register> + 1005cfc: d8c01617 ldw r3,88(sp) + 1005d00: d9801717 ldw r6,92(sp) + 1005d04: 19400017 ldw r5,0(r3) + 1005d08: 29fffd04 addi r7,r5,-12 + 1005d0c: 39000017 ldw r4,0(r7) + 1005d10: 21807336 bltu r4,r6,1005ee0 <_ZNSs7replaceEmmPKcm+0x23c> + 1005d14: d8c01717 ldw r3,92(sp) + 1005d18: d8801817 ldw r2,96(sp) + 1005d1c: 20cdc83a sub r6,r4,r3 + 1005d20: d8801015 stw r2,64(sp) + 1005d24: 30801b36 bltu r6,r2,1005d94 <_ZNSs7replaceEmmPKcm+0xf0> + 1005d28: d9801017 ldw r6,64(sp) + 1005d2c: 00900034 movhi r2,16384 + 1005d30: 10bfff04 addi r2,r2,-4 + 1005d34: 2187c83a sub r3,r4,r6 + 1005d38: 10c5c83a sub r2,r2,r3 + 1005d3c: d8c01d17 ldw r3,116(sp) + 1005d40: 10c06c36 bltu r2,r3,1005ef4 <_ZNSs7replaceEmmPKcm+0x250> + 1005d44: d9801917 ldw r6,100(sp) + 1005d48: 3140142e bgeu r6,r5,1005d9c <_ZNSs7replaceEmmPKcm+0xf8> + 1005d4c: d8801d17 ldw r2,116(sp) + 1005d50: d9001617 ldw r4,88(sp) + 1005d54: d9401717 ldw r5,92(sp) + 1005d58: d9801017 ldw r6,64(sp) + 1005d5c: d9c01917 ldw r7,100(sp) + 1005d60: d8800015 stw r2,0(sp) + 1005d64: 00bfffc4 movi r2,-1 + 1005d68: d8800415 stw r2,16(sp) + 1005d6c: 1004dd40 call 1004dd4 <_ZNSs15_M_replace_safeEmmPKcm> + 1005d70: d8801615 stw r2,88(sp) + 1005d74: d9000304 addi r4,sp,12 + 1005d78: 1009c2c0 call 1009c2c <_Unwind_SjLj_Unregister> + 1005d7c: d8801617 ldw r2,88(sp) + 1005d80: dfc01c17 ldw ra,112(sp) + 1005d84: df001b17 ldw fp,108(sp) + 1005d88: ddc01a17 ldw r23,104(sp) + 1005d8c: dec01d04 addi sp,sp,116 + 1005d90: f800283a ret + 1005d94: d9801015 stw r6,64(sp) + 1005d98: 003fe306 br 1005d28 <_ZNSs7replaceEmmPKcm+0x84> + 1005d9c: 2905883a add r2,r5,r4 + 1005da0: 11bfea36 bltu r2,r6,1005d4c <_ZNSs7replaceEmmPKcm+0xa8> + 1005da4: 38800217 ldw r2,8(r7) + 1005da8: 00bfe816 blt zero,r2,1005d4c <_ZNSs7replaceEmmPKcm+0xa8> + 1005dac: d8801717 ldw r2,92(sp) + 1005db0: d9001917 ldw r4,100(sp) + 1005db4: d9801d17 ldw r6,116(sp) + 1005db8: d8801515 stw r2,84(sp) + 1005dbc: 2887883a add r3,r5,r2 + 1005dc0: 2185883a add r2,r4,r6 + 1005dc4: 18801636 bltu r3,r2,1005e20 <_ZNSs7replaceEmmPKcm+0x17c> + 1005dc8: d8c01917 ldw r3,100(sp) + 1005dcc: 194bc83a sub r5,r3,r5 + 1005dd0: d9401415 stw r5,80(sp) + 1005dd4: d9401717 ldw r5,92(sp) + 1005dd8: d9801017 ldw r6,64(sp) + 1005ddc: d9001617 ldw r4,88(sp) + 1005de0: d9c01d17 ldw r7,116(sp) + 1005de4: 00bfffc4 movi r2,-1 + 1005de8: d8800415 stw r2,16(sp) + 1005dec: 1004b9c0 call 1004b9c <_ZNSs9_M_mutateEmmm> + 1005df0: d9801617 ldw r6,88(sp) + 1005df4: d8801417 ldw r2,80(sp) + 1005df8: 30c00017 ldw r3,0(r6) + 1005dfc: d9801517 ldw r6,84(sp) + 1005e00: 188b883a add r5,r3,r2 + 1005e04: 30c9883a add r4,r6,r3 + 1005e08: d8c01d17 ldw r3,116(sp) + 1005e0c: 00800044 movi r2,1 + 1005e10: 18800d1e bne r3,r2,1005e48 <_ZNSs7replaceEmmPKcm+0x1a4> + 1005e14: 28800003 ldbu r2,0(r5) + 1005e18: 20800005 stb r2,0(r4) + 1005e1c: 003fd506 br 1005d74 <_ZNSs7replaceEmmPKcm+0xd0> + 1005e20: d9001017 ldw r4,64(sp) + 1005e24: d9801917 ldw r6,100(sp) + 1005e28: 1905883a add r2,r3,r4 + 1005e2c: 30800936 bltu r6,r2,1005e54 <_ZNSs7replaceEmmPKcm+0x1b0> + 1005e30: 3147c83a sub r3,r6,r5 + 1005e34: d9401d17 ldw r5,116(sp) + 1005e38: 2905c83a sub r2,r5,r4 + 1005e3c: 1887883a add r3,r3,r2 + 1005e40: d8c01415 stw r3,80(sp) + 1005e44: 003fe306 br 1005dd4 <_ZNSs7replaceEmmPKcm+0x130> + 1005e48: d9801d17 ldw r6,116(sp) + 1005e4c: 100aa3c0 call 100aa3c + 1005e50: 003fc806 br 1005d74 <_ZNSs7replaceEmmPKcm+0xd0> + 1005e54: 01000104 movi r4,4 + 1005e58: d905883a add r2,sp,r4 + 1005e5c: d9000415 stw r4,16(sp) + 1005e60: d9401917 ldw r5,100(sp) + 1005e64: 1109883a add r4,r2,r4 + 1005e68: d9801d17 ldw r6,116(sp) + 1005e6c: d9c00184 addi r7,sp,6 + 1005e70: 1003dcc0 call 1003dcc <_ZNSsC1EPKcmRKSaIcE> + 1005e74: d9001d17 ldw r4,116(sp) + 1005e78: 008000c4 movi r2,3 + 1005e7c: d9c00217 ldw r7,8(sp) + 1005e80: d9000015 stw r4,0(sp) + 1005e84: d8800415 stw r2,16(sp) + 1005e88: d9001617 ldw r4,88(sp) + 1005e8c: d9401717 ldw r5,92(sp) + 1005e90: d9801017 ldw r6,64(sp) + 1005e94: 1004dd40 call 1004dd4 <_ZNSs15_M_replace_safeEmmPKcm> + 1005e98: d8801615 stw r2,88(sp) + 1005e9c: d8800217 ldw r2,8(sp) + 1005ea0: 00c040f4 movhi r3,259 + 1005ea4: 18e52f04 addi r3,r3,-27460 + 1005ea8: 10bffd04 addi r2,r2,-12 + 1005eac: d8801215 stw r2,72(sp) + 1005eb0: 10ffb026 beq r2,r3,1005d74 <_ZNSs7replaceEmmPKcm+0xd0> + 1005eb4: d9401217 ldw r5,72(sp) + 1005eb8: 00800084 movi r2,2 + 1005ebc: d8800415 stw r2,16(sp) + 1005ec0: 29000204 addi r4,r5,8 + 1005ec4: 017fffc4 movi r5,-1 + 1005ec8: 100617c0 call 100617c <_ZN9__gnu_cxx18__exchange_and_addEPVii> + 1005ecc: 00bfa916 blt zero,r2,1005d74 <_ZNSs7replaceEmmPKcm+0xd0> + 1005ed0: d9001217 ldw r4,72(sp) + 1005ed4: d9400144 addi r5,sp,5 + 1005ed8: 1002c0c0 call 1002c0c <_ZNSs4_Rep10_M_destroyERKSaIcE> + 1005edc: 003fa506 br 1005d74 <_ZNSs7replaceEmmPKcm+0xd0> + 1005ee0: 00bfffc4 movi r2,-1 + 1005ee4: 010040b4 movhi r4,258 + 1005ee8: 21042104 addi r4,r4,4228 + 1005eec: d8800415 stw r2,16(sp) + 1005ef0: 10084dc0 call 10084dc <_ZSt20__throw_out_of_rangePKc> + 1005ef4: 00bfffc4 movi r2,-1 + 1005ef8: 010040b4 movhi r4,258 + 1005efc: 21042104 addi r4,r4,4228 + 1005f00: d8800415 stw r2,16(sp) + 1005f04: 100866c0 call 100866c <_ZSt20__throw_length_errorPKc> + 1005f08: d8c00417 ldw r3,16(sp) + 1005f0c: 00800044 movi r2,1 + 1005f10: d9000517 ldw r4,20(sp) + 1005f14: 18800226 beq r3,r2,1005f20 <_ZNSs7replaceEmmPKcm+0x27c> + 1005f18: 00800084 movi r2,2 + 1005f1c: 18800326 beq r3,r2,1005f2c <_ZNSs7replaceEmmPKcm+0x288> + 1005f20: 00bfffc4 movi r2,-1 + 1005f24: d8800415 stw r2,16(sp) + 1005f28: 1009ee80 call 1009ee8 <_Unwind_SjLj_Resume> + 1005f2c: d8800217 ldw r2,8(sp) + 1005f30: 00c040f4 movhi r3,259 + 1005f34: 18e52f04 addi r3,r3,-27460 + 1005f38: d9001315 stw r4,76(sp) + 1005f3c: 10bffd04 addi r2,r2,-12 + 1005f40: d8801115 stw r2,68(sp) + 1005f44: 10c0041e bne r2,r3,1005f58 <_ZNSs7replaceEmmPKcm+0x2b4> + 1005f48: d9001317 ldw r4,76(sp) + 1005f4c: 00bfffc4 movi r2,-1 + 1005f50: d8800415 stw r2,16(sp) + 1005f54: 1009ee80 call 1009ee8 <_Unwind_SjLj_Resume> + 1005f58: d9801117 ldw r6,68(sp) + 1005f5c: 00800044 movi r2,1 + 1005f60: d8800415 stw r2,16(sp) + 1005f64: 31000204 addi r4,r6,8 + 1005f68: 017fffc4 movi r5,-1 + 1005f6c: 100617c0 call 100617c <_ZN9__gnu_cxx18__exchange_and_addEPVii> + 1005f70: 00bff516 blt zero,r2,1005f48 <_ZNSs7replaceEmmPKcm+0x2a4> + 1005f74: d9001117 ldw r4,68(sp) + 1005f78: d9400104 addi r5,sp,4 + 1005f7c: 1002c0c0 call 1002c0c <_ZNSs4_Rep10_M_destroyERKSaIcE> + 1005f80: 003ff106 br 1005f48 <_ZNSs7replaceEmmPKcm+0x2a4> + +01005f84 <_ZNSs7replaceEN9__gnu_cxx17__normal_iteratorIPcSsEES2_NS0_IPKcSsEES5_>: + 1005f84: d8800017 ldw r2,0(sp) + 1005f88: 20c00017 ldw r3,0(r4) + 1005f8c: 314dc83a sub r6,r6,r5 + 1005f90: 11c5c83a sub r2,r2,r7 + 1005f94: 28cbc83a sub r5,r5,r3 + 1005f98: d8800015 stw r2,0(sp) + 1005f9c: 1005ca41 jmpi 1005ca4 <_ZNSs7replaceEmmPKcm> + +01005fa0 <_ZNSs7replaceEN9__gnu_cxx17__normal_iteratorIPcSsEES2_S2_S2_>: + 1005fa0: d8800017 ldw r2,0(sp) + 1005fa4: 20c00017 ldw r3,0(r4) + 1005fa8: 314dc83a sub r6,r6,r5 + 1005fac: 11c5c83a sub r2,r2,r7 + 1005fb0: 28cbc83a sub r5,r5,r3 + 1005fb4: d8800015 stw r2,0(sp) + 1005fb8: 1005ca41 jmpi 1005ca4 <_ZNSs7replaceEmmPKcm> + +01005fbc <_ZNSs7replaceEN9__gnu_cxx17__normal_iteratorIPcSsEES2_PKcS4_>: + 1005fbc: d8800017 ldw r2,0(sp) + 1005fc0: 20c00017 ldw r3,0(r4) + 1005fc4: 314dc83a sub r6,r6,r5 + 1005fc8: 11c5c83a sub r2,r2,r7 + 1005fcc: 28cbc83a sub r5,r5,r3 + 1005fd0: d8800015 stw r2,0(sp) + 1005fd4: 1005ca41 jmpi 1005ca4 <_ZNSs7replaceEmmPKcm> + +01005fd8 <_ZNSs7replaceEN9__gnu_cxx17__normal_iteratorIPcSsEES2_S1_S1_>: + 1005fd8: d8800017 ldw r2,0(sp) + 1005fdc: 20c00017 ldw r3,0(r4) + 1005fe0: 314dc83a sub r6,r6,r5 + 1005fe4: 11c5c83a sub r2,r2,r7 + 1005fe8: 28cbc83a sub r5,r5,r3 + 1005fec: d8800015 stw r2,0(sp) + 1005ff0: 1005ca41 jmpi 1005ca4 <_ZNSs7replaceEmmPKcm> + +01005ff4 <_ZNSs7replaceEN9__gnu_cxx17__normal_iteratorIPcSsEES2_PKcm>: + 1005ff4: 20800017 ldw r2,0(r4) + 1005ff8: 314dc83a sub r6,r6,r5 + 1005ffc: 288bc83a sub r5,r5,r2 + 1006000: 1005ca41 jmpi 1005ca4 <_ZNSs7replaceEmmPKcm> + +01006004 <_ZNSs7replaceEmmPKc>: + 1006004: defffa04 addi sp,sp,-24 + 1006008: dfc00515 stw ra,20(sp) + 100600c: ddc00415 stw r23,16(sp) + 1006010: dd400315 stw r21,12(sp) + 1006014: dcc00215 stw r19,8(sp) + 1006018: dc400115 stw r17,4(sp) + 100601c: 202f883a mov r23,r4 + 1006020: 3809883a mov r4,r7 + 1006024: 382b883a mov r21,r7 + 1006028: 2823883a mov r17,r5 + 100602c: 3027883a mov r19,r6 + 1006030: 100b1640 call 100b164 + 1006034: 880b883a mov r5,r17 + 1006038: b809883a mov r4,r23 + 100603c: 980d883a mov r6,r19 + 1006040: a80f883a mov r7,r21 + 1006044: d8800015 stw r2,0(sp) + 1006048: 1005ca40 call 1005ca4 <_ZNSs7replaceEmmPKcm> + 100604c: dfc00517 ldw ra,20(sp) + 1006050: ddc00417 ldw r23,16(sp) + 1006054: dd400317 ldw r21,12(sp) + 1006058: dcc00217 ldw r19,8(sp) + 100605c: dc400117 ldw r17,4(sp) + 1006060: dec00604 addi sp,sp,24 + 1006064: f800283a ret + +01006068 <_ZNSs7replaceEmmRKSsmm>: + 1006068: 3a400017 ldw r9,0(r7) + 100606c: deffff04 addi sp,sp,-4 + 1006070: d9c00117 ldw r7,4(sp) + 1006074: 48bffd17 ldw r2,-12(r9) + 1006078: dfc00015 stw ra,0(sp) + 100607c: da000217 ldw r8,8(sp) + 1006080: 11c00d36 bltu r2,r7,10060b8 <_ZNSs7replaceEmmRKSsmm+0x50> + 1006084: 11c7c83a sub r3,r2,r7 + 1006088: 4005883a mov r2,r8 + 100608c: 49cf883a add r7,r9,r7 + 1006090: 1a000436 bltu r3,r8,10060a4 <_ZNSs7replaceEmmRKSsmm+0x3c> + 1006094: d8800115 stw r2,4(sp) + 1006098: dfc00017 ldw ra,0(sp) + 100609c: dec00104 addi sp,sp,4 + 10060a0: 1005ca41 jmpi 1005ca4 <_ZNSs7replaceEmmPKcm> + 10060a4: 1805883a mov r2,r3 + 10060a8: d8800115 stw r2,4(sp) + 10060ac: dfc00017 ldw ra,0(sp) + 10060b0: dec00104 addi sp,sp,4 + 10060b4: 1005ca41 jmpi 1005ca4 <_ZNSs7replaceEmmPKcm> + 10060b8: 010040b4 movhi r4,258 + 10060bc: 21042104 addi r4,r4,4228 + 10060c0: 10084dc0 call 10084dc <_ZSt20__throw_out_of_rangePKc> + +010060c4 <_ZNSs7replaceEmmRKSs>: + 10060c4: 39c00017 ldw r7,0(r7) + 10060c8: defffe04 addi sp,sp,-8 + 10060cc: dfc00115 stw ra,4(sp) + 10060d0: 38bffd17 ldw r2,-12(r7) + 10060d4: d8800015 stw r2,0(sp) + 10060d8: 1005ca40 call 1005ca4 <_ZNSs7replaceEmmPKcm> + 10060dc: dfc00117 ldw ra,4(sp) + 10060e0: dec00204 addi sp,sp,8 + 10060e4: f800283a ret + +010060e8 <_ZNSs7replaceEN9__gnu_cxx17__normal_iteratorIPcSsEES2_RKSs>: + 10060e8: 39c00017 ldw r7,0(r7) + 10060ec: 20800017 ldw r2,0(r4) + 10060f0: defffe04 addi sp,sp,-8 + 10060f4: 38fffd17 ldw r3,-12(r7) + 10060f8: 314dc83a sub r6,r6,r5 + 10060fc: 288bc83a sub r5,r5,r2 + 1006100: dfc00115 stw ra,4(sp) + 1006104: d8c00015 stw r3,0(sp) + 1006108: 1005ca40 call 1005ca4 <_ZNSs7replaceEmmPKcm> + 100610c: dfc00117 ldw ra,4(sp) + 1006110: dec00204 addi sp,sp,8 + 1006114: f800283a ret + +01006118 <_ZNSs7replaceEN9__gnu_cxx17__normal_iteratorIPcSsEES2_PKc>: + 1006118: 20800017 ldw r2,0(r4) + 100611c: defffa04 addi sp,sp,-24 + 1006120: dc400215 stw r17,8(sp) + 1006124: 3163c83a sub r17,r6,r5 + 1006128: 288bc83a sub r5,r5,r2 + 100612c: dfc00515 stw ra,20(sp) + 1006130: dd400415 stw r21,16(sp) + 1006134: dcc00315 stw r19,12(sp) + 1006138: d9400115 stw r5,4(sp) + 100613c: 2027883a mov r19,r4 + 1006140: 3809883a mov r4,r7 + 1006144: 382b883a mov r21,r7 + 1006148: 100b1640 call 100b164 + 100614c: d9400117 ldw r5,4(sp) + 1006150: 9809883a mov r4,r19 + 1006154: 880d883a mov r6,r17 + 1006158: a80f883a mov r7,r21 + 100615c: d8800015 stw r2,0(sp) + 1006160: 1005ca40 call 1005ca4 <_ZNSs7replaceEmmPKcm> + 1006164: dfc00517 ldw ra,20(sp) + 1006168: dd400417 ldw r21,16(sp) + 100616c: dcc00317 ldw r19,12(sp) + 1006170: dc400217 ldw r17,8(sp) + 1006174: dec00604 addi sp,sp,24 + 1006178: f800283a ret + +0100617c <_ZN9__gnu_cxx18__exchange_and_addEPVii>: + 100617c: 20800017 ldw r2,0(r4) + 1006180: 20c00017 ldw r3,0(r4) + 1006184: 1947883a add r3,r3,r5 + 1006188: 20c00015 stw r3,0(r4) + 100618c: f800283a ret + +01006190 <_ZN9__gnu_cxx12__atomic_addEPVii>: + 1006190: 100617c1 jmpi 100617c <_ZN9__gnu_cxx18__exchange_and_addEPVii> + +01006194 <_ZNK10__cxxabiv117__class_type_info11__do_upcastEPKS0_PPv>: + 1006194: 20c00017 ldw r3,0(r4) + 1006198: defffa04 addi sp,sp,-24 + 100619c: dc000415 stw r16,16(sp) + 10061a0: 1a000617 ldw r8,24(r3) + 10061a4: 3021883a mov r16,r6 + 10061a8: 31800017 ldw r6,0(r6) + 10061ac: 00800404 movi r2,16 + 10061b0: dfc00515 stw ra,20(sp) + 10061b4: d8800215 stw r2,8(sp) + 10061b8: d8000015 stw zero,0(sp) + 10061bc: d8000115 stw zero,4(sp) + 10061c0: d8000315 stw zero,12(sp) + 10061c4: d80f883a mov r7,sp + 10061c8: 403ee83a callr r8 + 10061cc: d8800117 ldw r2,4(sp) + 10061d0: 00c00184 movi r3,6 + 10061d4: 0009883a mov r4,zero + 10061d8: 1080018c andi r2,r2,6 + 10061dc: 10c0031e bne r2,r3,10061ec <_ZNK10__cxxabiv117__class_type_info11__do_upcastEPKS0_PPv+0x58> + 10061e0: d8800017 ldw r2,0(sp) + 10061e4: 01000044 movi r4,1 + 10061e8: 80800015 stw r2,0(r16) + 10061ec: 2005883a mov r2,r4 + 10061f0: dfc00517 ldw ra,20(sp) + 10061f4: dc000417 ldw r16,16(sp) + 10061f8: dec00604 addi sp,sp,24 + 10061fc: f800283a ret + +01006200 <_ZNK10__cxxabiv117__class_type_info20__do_find_public_srcElPKvPKS0_S2_>: + 1006200: d8800017 ldw r2,0(sp) + 1006204: 00c00184 movi r3,6 + 1006208: 1180021e bne r2,r6,1006214 <_ZNK10__cxxabiv117__class_type_info20__do_find_public_srcElPKvPKS0_S2_+0x14> + 100620c: 1805883a mov r2,r3 + 1006210: f800283a ret + 1006214: 00c00044 movi r3,1 + 1006218: 1805883a mov r2,r3 + 100621c: f800283a ret + +01006220 <_ZN10__cxxabiv117__class_type_infoD0Ev>: + 1006220: defffe04 addi sp,sp,-8 + 1006224: 008040b4 movhi r2,258 + 1006228: 10843a04 addi r2,r2,4328 + 100622c: dc400015 stw r17,0(sp) + 1006230: 20800015 stw r2,0(r4) + 1006234: 2023883a mov r17,r4 + 1006238: dfc00115 stw ra,4(sp) + 100623c: 10075900 call 1007590 <_ZNSt9type_infoD2Ev> + 1006240: 8809883a mov r4,r17 + 1006244: dfc00117 ldw ra,4(sp) + 1006248: dc400017 ldw r17,0(sp) + 100624c: dec00204 addi sp,sp,8 + 1006250: 100722c1 jmpi 100722c <_ZdlPv> + +01006254 <_ZN10__cxxabiv117__class_type_infoD1Ev>: + 1006254: 008040b4 movhi r2,258 + 1006258: 10843a04 addi r2,r2,4328 + 100625c: 20800015 stw r2,0(r4) + 1006260: 10075901 jmpi 1007590 <_ZNSt9type_infoD2Ev> + +01006264 <_ZN10__cxxabiv117__class_type_infoD2Ev>: + 1006264: 008040b4 movhi r2,258 + 1006268: 10843a04 addi r2,r2,4328 + 100626c: 20800015 stw r2,0(r4) + 1006270: 10075901 jmpi 1007590 <_ZNSt9type_infoD2Ev> + +01006274 <_ZNK10__cxxabiv117__class_type_info10__do_catchEPKSt9type_infoPPvj>: + 1006274: 2811883a mov r8,r5 + 1006278: 20c00117 ldw r3,4(r4) + 100627c: 40800117 ldw r2,4(r8) + 1006280: deffff04 addi sp,sp,-4 + 1006284: dfc00015 stw ra,0(sp) + 1006288: 200b883a mov r5,r4 + 100628c: 02400044 movi r9,1 + 1006290: 18800426 beq r3,r2,10062a4 <_ZNK10__cxxabiv117__class_type_info10__do_catchEPKSt9type_infoPPvj+0x30> + 1006294: 008000c4 movi r2,3 + 1006298: 4009883a mov r4,r8 + 100629c: 0013883a mov r9,zero + 10062a0: 11c0042e bgeu r2,r7,10062b4 <_ZNK10__cxxabiv117__class_type_info10__do_catchEPKSt9type_infoPPvj+0x40> + 10062a4: 4805883a mov r2,r9 + 10062a8: dfc00017 ldw ra,0(sp) + 10062ac: dec00104 addi sp,sp,4 + 10062b0: f800283a ret + 10062b4: 40800017 ldw r2,0(r8) + 10062b8: 10c00517 ldw r3,20(r2) + 10062bc: 183ee83a callr r3 + 10062c0: 12403fcc andi r9,r2,255 + 10062c4: 4805883a mov r2,r9 + 10062c8: dfc00017 ldw ra,0(sp) + 10062cc: dec00104 addi sp,sp,4 + 10062d0: f800283a ret + +010062d4 <_ZNK10__cxxabiv117__class_type_info11__do_upcastEPKS0_PKvRNS0_15__upcast_resultE>: + 10062d4: 20c00117 ldw r3,4(r4) + 10062d8: 28800117 ldw r2,4(r5) + 10062dc: 0009883a mov r4,zero + 10062e0: 1880061e bne r3,r2,10062fc <_ZNK10__cxxabiv117__class_type_info11__do_upcastEPKS0_PKvRNS0_15__upcast_resultE+0x28> + 10062e4: 00800184 movi r2,6 + 10062e8: 38800115 stw r2,4(r7) + 10062ec: 00800204 movi r2,8 + 10062f0: 39800015 stw r6,0(r7) + 10062f4: 38800315 stw r2,12(r7) + 10062f8: 01000044 movi r4,1 + 10062fc: 2005883a mov r2,r4 + 1006300: f800283a ret + +01006304 <_ZNK10__cxxabiv117__class_type_info12__do_dyncastElNS0_10__sub_kindEPKS0_PKvS3_S5_RNS0_16__dyncast_resultE>: + 1006304: da000017 ldw r8,0(sp) + 1006308: d8800217 ldw r2,8(sp) + 100630c: d9400317 ldw r5,12(sp) + 1006310: 40800926 beq r8,r2,1006338 <_ZNK10__cxxabiv117__class_type_info12__do_dyncastElNS0_10__sub_kindEPKS0_PKvS3_S5_RNS0_16__dyncast_resultE+0x34> + 1006314: 21000117 ldw r4,4(r4) + 1006318: 38800117 ldw r2,4(r7) + 100631c: 2080041e bne r4,r2,1006330 <_ZNK10__cxxabiv117__class_type_info12__do_dyncastElNS0_10__sub_kindEPKS0_PKvS3_S5_RNS0_16__dyncast_resultE+0x2c> + 1006320: 00800044 movi r2,1 + 1006324: 28800315 stw r2,12(r5) + 1006328: 2a000015 stw r8,0(r5) + 100632c: 29800115 stw r6,4(r5) + 1006330: 0005883a mov r2,zero + 1006334: f800283a ret + 1006338: d8800117 ldw r2,4(sp) + 100633c: 21000117 ldw r4,4(r4) + 1006340: 10c00117 ldw r3,4(r2) + 1006344: 20fff41e bne r4,r3,1006318 <_ZNK10__cxxabiv117__class_type_info12__do_dyncastElNS0_10__sub_kindEPKS0_PKvS3_S5_RNS0_16__dyncast_resultE+0x14> + 1006348: 29800215 stw r6,8(r5) + 100634c: 003ff806 br 1006330 <_ZNK10__cxxabiv117__class_type_info12__do_dyncastElNS0_10__sub_kindEPKS0_PKvS3_S5_RNS0_16__dyncast_resultE+0x2c> + +01006350 <_Z12read_uleb128PKhPj>: + 1006350: 000d883a mov r6,zero + 1006354: 000f883a mov r7,zero + 1006358: 20c00007 ldb r3,0(r4) + 100635c: 21000044 addi r4,r4,1 + 1006360: 18801fcc andi r2,r3,127 + 1006364: 1184983a sll r2,r2,r6 + 1006368: 318001c4 addi r6,r6,7 + 100636c: 388eb03a or r7,r7,r2 + 1006370: 183ff916 blt r3,zero,1006358 <_Z12read_uleb128PKhPj+0x8> + 1006374: 2005883a mov r2,r4 + 1006378: 29c00015 stw r7,0(r5) + 100637c: f800283a ret + +01006380 <_Z12read_sleb128PKhPi>: + 1006380: 000f883a mov r7,zero + 1006384: 0011883a mov r8,zero + 1006388: 20c00007 ldb r3,0(r4) + 100638c: 21000044 addi r4,r4,1 + 1006390: 19803fcc andi r6,r3,255 + 1006394: 30801fcc andi r2,r6,127 + 1006398: 11c4983a sll r2,r2,r7 + 100639c: 39c001c4 addi r7,r7,7 + 10063a0: 4090b03a or r8,r8,r2 + 10063a4: 183ff816 blt r3,zero,1006388 <_Z12read_sleb128PKhPi+0x8> + 10063a8: 008007c4 movi r2,31 + 10063ac: 11c00636 bltu r2,r7,10063c8 <_Z12read_sleb128PKhPi+0x48> + 10063b0: 3080100c andi r2,r6,64 + 10063b4: 10000426 beq r2,zero,10063c8 <_Z12read_sleb128PKhPi+0x48> + 10063b8: 00800044 movi r2,1 + 10063bc: 11c4983a sll r2,r2,r7 + 10063c0: 0085c83a sub r2,zero,r2 + 10063c4: 4090b03a or r8,r8,r2 + 10063c8: 2005883a mov r2,r4 + 10063cc: 2a000015 stw r8,0(r5) + 10063d0: f800283a ret + +010063d4 <_Z16get_adjusted_ptrPKSt9type_infoS1_PPv>: + 10063d4: 28800017 ldw r2,0(r5) + 10063d8: defffb04 addi sp,sp,-20 + 10063dc: 30c00017 ldw r3,0(r6) + 10063e0: dc400215 stw r17,8(sp) + 10063e4: 2823883a mov r17,r5 + 10063e8: 11400217 ldw r5,8(r2) + 10063ec: dc800315 stw r18,12(sp) + 10063f0: dc000115 stw r16,4(sp) + 10063f4: dfc00415 stw ra,16(sp) + 10063f8: 2021883a mov r16,r4 + 10063fc: d8c00015 stw r3,0(sp) + 1006400: 8809883a mov r4,r17 + 1006404: 3025883a mov r18,r6 + 1006408: 283ee83a callr r5 + 100640c: 10803fcc andi r2,r2,255 + 1006410: 880b883a mov r5,r17 + 1006414: 8009883a mov r4,r16 + 1006418: d80d883a mov r6,sp + 100641c: 01c00044 movi r7,1 + 1006420: 10000326 beq r2,zero,1006430 <_Z16get_adjusted_ptrPKSt9type_infoS1_PPv+0x5c> + 1006424: d8800017 ldw r2,0(sp) + 1006428: 10c00017 ldw r3,0(r2) + 100642c: d8c00015 stw r3,0(sp) + 1006430: 80800017 ldw r2,0(r16) + 1006434: 10c00417 ldw r3,16(r2) + 1006438: 183ee83a callr r3 + 100643c: 10803fcc andi r2,r2,255 + 1006440: 0007883a mov r3,zero + 1006444: 10000326 beq r2,zero,1006454 <_Z16get_adjusted_ptrPKSt9type_infoS1_PPv+0x80> + 1006448: d8800017 ldw r2,0(sp) + 100644c: 00c00044 movi r3,1 + 1006450: 90800015 stw r2,0(r18) + 1006454: 1805883a mov r2,r3 + 1006458: dfc00417 ldw ra,16(sp) + 100645c: dc800317 ldw r18,12(sp) + 1006460: dc400217 ldw r17,8(sp) + 1006464: dc000117 ldw r16,4(sp) + 1006468: dec00504 addi sp,sp,20 + 100646c: f800283a ret + +01006470 <_Z28read_encoded_value_with_basehjPKhPj>: + 1006470: defff904 addi sp,sp,-28 + 1006474: dc400215 stw r17,8(sp) + 1006478: 00801404 movi r2,80 + 100647c: 24403fcc andi r17,r4,255 + 1006480: dd000515 stw r20,20(sp) + 1006484: dcc00415 stw r19,16(sp) + 1006488: dc800315 stw r18,12(sp) + 100648c: dc000115 stw r16,4(sp) + 1006490: dfc00615 stw ra,24(sp) + 1006494: 2025883a mov r18,r4 + 1006498: 2829883a mov r20,r5 + 100649c: 3021883a mov r16,r6 + 10064a0: 3827883a mov r19,r7 + 10064a4: 88801826 beq r17,r2,1006508 <_Z28read_encoded_value_with_basehjPKhPj+0x98> + 10064a8: 88c003cc andi r3,r17,15 + 10064ac: 00800304 movi r2,12 + 10064b0: 10c0012e bgeu r2,r3,10064b8 <_Z28read_encoded_value_with_basehjPKhPj+0x48> + 10064b4: 100a1640 call 100a164 + 10064b8: 18c5883a add r2,r3,r3 + 10064bc: 1085883a add r2,r2,r2 + 10064c0: 00c04034 movhi r3,256 + 10064c4: 18d93504 addi r3,r3,25812 + 10064c8: 10c5883a add r2,r2,r3 + 10064cc: 11000017 ldw r4,0(r2) + 10064d0: 2000683a jmp r4 + 10064d4: 01006544 movi r4,405 + 10064d8: 0100662c andhi r4,zero,408 + 10064dc: 010065d8 cmpnei r4,zero,407 + 10064e0: 01006544 movi r4,405 + 10064e4: 0100659c xori r4,zero,406 + 10064e8: 010064b4 movhi r4,402 + 10064ec: 010064b4 movhi r4,402 + 10064f0: 010064b4 movhi r4,402 + 10064f4: 010064b4 movhi r4,402 + 10064f8: 01006614 movui r4,408 + 10064fc: 010065f0 cmpltui r4,zero,407 + 1006500: 01006544 movi r4,405 + 1006504: 0100659c xori r4,zero,406 + 1006508: 308000c4 addi r2,r6,3 + 100650c: 00ffff04 movi r3,-4 + 1006510: 10c4703a and r2,r2,r3 + 1006514: 11000017 ldw r4,0(r2) + 1006518: 11400104 addi r5,r2,4 + 100651c: 2805883a mov r2,r5 + 1006520: 99000015 stw r4,0(r19) + 1006524: dfc00617 ldw ra,24(sp) + 1006528: dd000517 ldw r20,20(sp) + 100652c: dcc00417 ldw r19,16(sp) + 1006530: dc800317 ldw r18,12(sp) + 1006534: dc400217 ldw r17,8(sp) + 1006538: dc000117 ldw r16,4(sp) + 100653c: dec00704 addi sp,sp,28 + 1006540: f800283a ret + 1006544: 30800043 ldbu r2,1(r6) + 1006548: 30c00083 ldbu r3,2(r6) + 100654c: 310000c3 ldbu r4,3(r6) + 1006550: 31400003 ldbu r5,0(r6) + 1006554: 1004923a slli r2,r2,8 + 1006558: 1806943a slli r3,r3,16 + 100655c: 2008963a slli r4,r4,24 + 1006560: 1144b03a or r2,r2,r5 + 1006564: 1886b03a or r3,r3,r2 + 1006568: 20c8b03a or r4,r4,r3 + 100656c: 31400104 addi r5,r6,4 + 1006570: 203fea26 beq r4,zero,100651c <_Z28read_encoded_value_with_basehjPKhPj+0xac> + 1006574: 88c01c0c andi r3,r17,112 + 1006578: 00800404 movi r2,16 + 100657c: 18801426 beq r3,r2,10065d0 <_Z28read_encoded_value_with_basehjPKhPj+0x160> + 1006580: 90803fcc andi r2,r18,255 + 1006584: 1080201c xori r2,r2,128 + 1006588: 10bfe004 addi r2,r2,-128 + 100658c: 2509883a add r4,r4,r20 + 1006590: 103fe20e bge r2,zero,100651c <_Z28read_encoded_value_with_basehjPKhPj+0xac> + 1006594: 21000017 ldw r4,0(r4) + 1006598: 003fe006 br 100651c <_Z28read_encoded_value_with_basehjPKhPj+0xac> + 100659c: 30800043 ldbu r2,1(r6) + 10065a0: 31800083 ldbu r6,2(r6) + 10065a4: 820000c3 ldbu r8,3(r16) + 10065a8: 1004923a slli r2,r2,8 + 10065ac: 82400003 ldbu r9,0(r16) + 10065b0: 300c943a slli r6,r6,16 + 10065b4: 4010963a slli r8,r8,24 + 10065b8: 1244b03a or r2,r2,r9 + 10065bc: 308cb03a or r6,r6,r2 + 10065c0: 4184b03a or r2,r8,r6 + 10065c4: 1009883a mov r4,r2 + 10065c8: 81400204 addi r5,r16,8 + 10065cc: 003fe806 br 1006570 <_Z28read_encoded_value_with_basehjPKhPj+0x100> + 10065d0: 8029883a mov r20,r16 + 10065d4: 003fea06 br 1006580 <_Z28read_encoded_value_with_basehjPKhPj+0x110> + 10065d8: 30800043 ldbu r2,1(r6) + 10065dc: 30c00003 ldbu r3,0(r6) + 10065e0: 31400084 addi r5,r6,2 + 10065e4: 1004923a slli r2,r2,8 + 10065e8: 10c8b03a or r4,r2,r3 + 10065ec: 003fe006 br 1006570 <_Z28read_encoded_value_with_basehjPKhPj+0x100> + 10065f0: 30800043 ldbu r2,1(r6) + 10065f4: 30c00003 ldbu r3,0(r6) + 10065f8: 31400084 addi r5,r6,2 + 10065fc: 1004923a slli r2,r2,8 + 1006600: 10c4b03a or r2,r2,r3 + 1006604: 113fffcc andi r4,r2,65535 + 1006608: 2120001c xori r4,r4,32768 + 100660c: 21200004 addi r4,r4,-32768 + 1006610: 003fd706 br 1006570 <_Z28read_encoded_value_with_basehjPKhPj+0x100> + 1006614: 3009883a mov r4,r6 + 1006618: d80b883a mov r5,sp + 100661c: 10063800 call 1006380 <_Z12read_sleb128PKhPi> + 1006620: d9000017 ldw r4,0(sp) + 1006624: 100b883a mov r5,r2 + 1006628: 003fd106 br 1006570 <_Z28read_encoded_value_with_basehjPKhPj+0x100> + 100662c: 3009883a mov r4,r6 + 1006630: d80b883a mov r5,sp + 1006634: 10063500 call 1006350 <_Z12read_uleb128PKhPj> + 1006638: d9000017 ldw r4,0(sp) + 100663c: 100b883a mov r5,r2 + 1006640: 003fcb06 br 1006570 <_Z28read_encoded_value_with_basehjPKhPj+0x100> + +01006644 <_Z21base_of_encoded_valuehP15_Unwind_Context>: + 1006644: deffff04 addi sp,sp,-4 + 1006648: 21003fcc andi r4,r4,255 + 100664c: 00803fc4 movi r2,255 + 1006650: dfc00015 stw ra,0(sp) + 1006654: 20800c26 beq r4,r2,1006688 <_Z21base_of_encoded_valuehP15_Unwind_Context+0x44> + 1006658: 21001c0c andi r4,r4,112 + 100665c: 00800804 movi r2,32 + 1006660: 20800d26 beq r4,r2,1006698 <_Z21base_of_encoded_valuehP15_Unwind_Context+0x54> + 1006664: 1100070e bge r2,r4,1006684 <_Z21base_of_encoded_valuehP15_Unwind_Context+0x40> + 1006668: 00801004 movi r2,64 + 100666c: 20801126 beq r4,r2,10066b4 <_Z21base_of_encoded_valuehP15_Unwind_Context+0x70> + 1006670: 00801404 movi r2,80 + 1006674: 20800426 beq r4,r2,1006688 <_Z21base_of_encoded_valuehP15_Unwind_Context+0x44> + 1006678: 00800c04 movi r2,48 + 100667c: 20801126 beq r4,r2,10066c4 <_Z21base_of_encoded_valuehP15_Unwind_Context+0x80> + 1006680: 100a1640 call 100a164 + 1006684: 2000081e bne r4,zero,10066a8 <_Z21base_of_encoded_valuehP15_Unwind_Context+0x64> + 1006688: 0005883a mov r2,zero + 100668c: dfc00017 ldw ra,0(sp) + 1006690: dec00104 addi sp,sp,4 + 1006694: f800283a ret + 1006698: 2809883a mov r4,r5 + 100669c: dfc00017 ldw ra,0(sp) + 10066a0: dec00104 addi sp,sp,4 + 10066a4: 1009cd41 jmpi 1009cd4 <_Unwind_GetTextRelBase> + 10066a8: 00800404 movi r2,16 + 10066ac: 20bff626 beq r4,r2,1006688 <_Z21base_of_encoded_valuehP15_Unwind_Context+0x44> + 10066b0: 100a1640 call 100a164 + 10066b4: 2809883a mov r4,r5 + 10066b8: dfc00017 ldw ra,0(sp) + 10066bc: dec00104 addi sp,sp,4 + 10066c0: 1009cbc1 jmpi 1009cbc <_Unwind_GetRegionStart> + 10066c4: 2809883a mov r4,r5 + 10066c8: dfc00017 ldw ra,0(sp) + 10066cc: dec00104 addi sp,sp,4 + 10066d0: 1009ccc1 jmpi 1009ccc <_Unwind_GetDataRelBase> + +010066d4 <_Z17parse_lsda_headerP15_Unwind_ContextPKhP16lsda_header_info>: + 10066d4: defffa04 addi sp,sp,-24 + 10066d8: dc800415 stw r18,16(sp) + 10066dc: dc400315 stw r17,12(sp) + 10066e0: dc000215 stw r16,8(sp) + 10066e4: dfc00515 stw ra,20(sp) + 10066e8: 2021883a mov r16,r4 + 10066ec: 000f883a mov r7,zero + 10066f0: 3023883a mov r17,r6 + 10066f4: 2825883a mov r18,r5 + 10066f8: 20000226 beq r4,zero,1006704 <_Z17parse_lsda_headerP15_Unwind_ContextPKhP16lsda_header_info+0x30> + 10066fc: 1009cbc0 call 1009cbc <_Unwind_GetRegionStart> + 1006700: 100f883a mov r7,r2 + 1006704: 89c00015 stw r7,0(r17) + 1006708: 90c00003 ldbu r3,0(r18) + 100670c: 800b883a mov r5,r16 + 1006710: 00803fc4 movi r2,255 + 1006714: 1c003fcc andi r16,r3,255 + 1006718: 91800044 addi r6,r18,1 + 100671c: 8009883a mov r4,r16 + 1006720: 18802226 beq r3,r2,10067ac <_Z17parse_lsda_headerP15_Unwind_ContextPKhP16lsda_header_info+0xd8> + 1006724: d9800115 stw r6,4(sp) + 1006728: 10066440 call 1006644 <_Z21base_of_encoded_valuehP15_Unwind_Context> + 100672c: d9800117 ldw r6,4(sp) + 1006730: 8009883a mov r4,r16 + 1006734: 100b883a mov r5,r2 + 1006738: 89c00104 addi r7,r17,4 + 100673c: 10064700 call 1006470 <_Z28read_encoded_value_with_basehjPKhPj> + 1006740: 100d883a mov r6,r2 + 1006744: 30800003 ldbu r2,0(r6) + 1006748: 31c00044 addi r7,r6,1 + 100674c: 00c03fc4 movi r3,255 + 1006750: d80b883a mov r5,sp + 1006754: 3809883a mov r4,r7 + 1006758: 88800505 stb r2,20(r17) + 100675c: 10c01b26 beq r2,r3,10067cc <_Z17parse_lsda_headerP15_Unwind_ContextPKhP16lsda_header_info+0xf8> + 1006760: 10063500 call 1006350 <_Z12read_uleb128PKhPj> + 1006764: 100f883a mov r7,r2 + 1006768: d8800017 ldw r2,0(sp) + 100676c: 3885883a add r2,r7,r2 + 1006770: 88800315 stw r2,12(r17) + 1006774: 38800003 ldbu r2,0(r7) + 1006778: 39000044 addi r4,r7,1 + 100677c: d80b883a mov r5,sp + 1006780: 88800545 stb r2,21(r17) + 1006784: 10063500 call 1006350 <_Z12read_uleb128PKhPj> + 1006788: d8c00017 ldw r3,0(sp) + 100678c: 10c9883a add r4,r2,r3 + 1006790: 89000415 stw r4,16(r17) + 1006794: dfc00517 ldw ra,20(sp) + 1006798: dc800417 ldw r18,16(sp) + 100679c: dc400317 ldw r17,12(sp) + 10067a0: dc000217 ldw r16,8(sp) + 10067a4: dec00604 addi sp,sp,24 + 10067a8: f800283a ret + 10067ac: 89c00115 stw r7,4(r17) + 10067b0: 30800003 ldbu r2,0(r6) + 10067b4: 31c00044 addi r7,r6,1 + 10067b8: 00c03fc4 movi r3,255 + 10067bc: d80b883a mov r5,sp + 10067c0: 3809883a mov r4,r7 + 10067c4: 88800505 stb r2,20(r17) + 10067c8: 10ffe51e bne r2,r3,1006760 <_Z17parse_lsda_headerP15_Unwind_ContextPKhP16lsda_header_info+0x8c> + 10067cc: 88000315 stw zero,12(r17) + 10067d0: 003fe806 br 1006774 <_Z17parse_lsda_headerP15_Unwind_ContextPKhP16lsda_header_info+0xa0> + +010067d4 <_Z15get_ttype_entryP16lsda_header_infoj>: + 10067d4: defffe04 addi sp,sp,-8 + 10067d8: dfc00115 stw ra,4(sp) + 10067dc: 21c00503 ldbu r7,20(r4) + 10067e0: 00803fc4 movi r2,255 + 10067e4: 38801a26 beq r7,r2,1006850 <_Z15get_ttype_entryP16lsda_header_infoj+0x7c> + 10067e8: 38c001cc andi r3,r7,7 + 10067ec: 00800084 movi r2,2 + 10067f0: 18801326 beq r3,r2,1006840 <_Z15get_ttype_entryP16lsda_header_infoj+0x6c> + 10067f4: 10c0050e bge r2,r3,100680c <_Z15get_ttype_entryP16lsda_header_infoj+0x38> + 10067f8: 008000c4 movi r2,3 + 10067fc: 18800426 beq r3,r2,1006810 <_Z15get_ttype_entryP16lsda_header_infoj+0x3c> + 1006800: 00800104 movi r2,4 + 1006804: 18801026 beq r3,r2,1006848 <_Z15get_ttype_entryP16lsda_header_infoj+0x74> + 1006808: 100a1640 call 100a164 + 100680c: 183ffe1e bne r3,zero,1006808 <_Z15get_ttype_entryP16lsda_header_infoj+0x34> + 1006810: 2945883a add r2,r5,r5 + 1006814: 1085883a add r2,r2,r2 + 1006818: 21800317 ldw r6,12(r4) + 100681c: 21400217 ldw r5,8(r4) + 1006820: 3809883a mov r4,r7 + 1006824: 308dc83a sub r6,r6,r2 + 1006828: d80f883a mov r7,sp + 100682c: 10064700 call 1006470 <_Z28read_encoded_value_with_basehjPKhPj> + 1006830: d8800017 ldw r2,0(sp) + 1006834: dfc00117 ldw ra,4(sp) + 1006838: dec00204 addi sp,sp,8 + 100683c: f800283a ret + 1006840: 2945883a add r2,r5,r5 + 1006844: 003ff406 br 1006818 <_Z15get_ttype_entryP16lsda_header_infoj+0x44> + 1006848: 280490fa slli r2,r5,3 + 100684c: 003ff206 br 1006818 <_Z15get_ttype_entryP16lsda_header_infoj+0x44> + 1006850: 0005883a mov r2,zero + 1006854: 003ff006 br 1006818 <_Z15get_ttype_entryP16lsda_header_infoj+0x44> + +01006858 <_Z20check_exception_specP16lsda_header_infoPKSt9type_infoPvi>: + 1006858: 20800317 ldw r2,12(r4) + 100685c: defffa04 addi sp,sp,-24 + 1006860: dc800415 stw r18,16(sp) + 1006864: 11c5c83a sub r2,r2,r7 + 1006868: dc400315 stw r17,12(sp) + 100686c: dc000215 stw r16,8(sp) + 1006870: dfc00515 stw ra,20(sp) + 1006874: 2023883a mov r17,r4 + 1006878: d9800115 stw r6,4(sp) + 100687c: 2825883a mov r18,r5 + 1006880: 143fffc4 addi r16,r2,-1 + 1006884: 8009883a mov r4,r16 + 1006888: d80b883a mov r5,sp + 100688c: 10063500 call 1006350 <_Z12read_uleb128PKhPj> + 1006890: 1021883a mov r16,r2 + 1006894: d8800017 ldw r2,0(sp) + 1006898: 8809883a mov r4,r17 + 100689c: 100b883a mov r5,r2 + 10068a0: 10000826 beq r2,zero,10068c4 <_Z20check_exception_specP16lsda_header_infoPKSt9type_infoPvi+0x6c> + 10068a4: 10067d40 call 10067d4 <_Z15get_ttype_entryP16lsda_header_infoj> + 10068a8: 1009883a mov r4,r2 + 10068ac: 900b883a mov r5,r18 + 10068b0: d9800104 addi r6,sp,4 + 10068b4: 10063d40 call 10063d4 <_Z16get_adjusted_ptrPKSt9type_infoS1_PPv> + 10068b8: 10803fcc andi r2,r2,255 + 10068bc: 103ff126 beq r2,zero,1006884 <_Z20check_exception_specP16lsda_header_infoPKSt9type_infoPvi+0x2c> + 10068c0: 00800044 movi r2,1 + 10068c4: dfc00517 ldw ra,20(sp) + 10068c8: dc800417 ldw r18,16(sp) + 10068cc: dc400317 ldw r17,12(sp) + 10068d0: dc000217 ldw r16,8(sp) + 10068d4: dec00604 addi sp,sp,24 + 10068d8: f800283a ret + +010068dc <__cxa_call_unexpected>: + 10068dc: deffe204 addi sp,sp,-120 + 10068e0: 00804034 movhi r2,256 + 10068e4: 109a9704 addi r2,r2,27228 + 10068e8: 00c040b4 movhi r3,258 + 10068ec: 18c2f804 addi r3,r3,3040 + 10068f0: d8800c15 stw r2,48(sp) + 10068f4: d9001815 stw r4,96(sp) + 10068f8: 00804034 movhi r2,256 + 10068fc: 109a5904 addi r2,r2,26980 + 1006900: d9000604 addi r4,sp,24 + 1006904: d8c00d15 stw r3,52(sp) + 1006908: dfc01d15 stw ra,116(sp) + 100690c: d8800f15 stw r2,60(sp) + 1006910: df001c15 stw fp,112(sp) + 1006914: ddc01b15 stw r23,108(sp) + 1006918: dec00e15 stw sp,56(sp) + 100691c: dec01015 stw sp,64(sp) + 1006920: 1009c1c0 call 1009c1c <_Unwind_SjLj_Register> + 1006924: d9001817 ldw r4,96(sp) + 1006928: 10071140 call 1007114 <__cxa_begin_catch> + 100692c: d8801817 ldw r2,96(sp) + 1006930: 10fff504 addi r3,r2,-44 + 1006934: 18800917 ldw r2,36(r3) + 1006938: 19400617 ldw r5,24(r3) + 100693c: 19000217 ldw r4,8(r3) + 1006940: d8800215 stw r2,8(sp) + 1006944: 18800817 ldw r2,32(r3) + 1006948: 18c00317 ldw r3,12(r3) + 100694c: d9401615 stw r5,88(sp) + 1006950: d8801715 stw r2,92(sp) + 1006954: 00800084 movi r2,2 + 1006958: d8c01515 stw r3,84(sp) + 100695c: d8800715 stw r2,28(sp) + 1006960: 10070200 call 1007020 <_ZN10__cxxabiv112__unexpectedEPFvvE> + 1006964: d8800717 ldw r2,28(sp) + 1006968: d8c00817 ldw r3,32(sp) + 100696c: d8801a15 stw r2,104(sp) + 1006970: d9401a17 ldw r5,104(sp) + 1006974: 00800044 movi r2,1 + 1006978: d8c01915 stw r3,100(sp) + 100697c: 28800826 beq r5,r2,10069a0 <__cxa_call_unexpected+0xc4> + 1006980: d8000715 stw zero,28(sp) + 1006984: 10070700 call 1007070 <__cxa_end_catch> + 1006988: d8000715 stw zero,28(sp) + 100698c: 10070700 call 1007070 <__cxa_end_catch> + 1006990: d9001917 ldw r4,100(sp) + 1006994: 00bfffc4 movi r2,-1 + 1006998: d8800715 stw r2,28(sp) + 100699c: 1009ee80 call 1009ee8 <_Unwind_SjLj_Resume> + 10069a0: d9001917 ldw r4,100(sp) + 10069a4: 10071140 call 1007114 <__cxa_begin_catch> + 10069a8: 1009b640 call 1009b64 <__cxa_get_globals_fast> + 10069ac: 10800017 ldw r2,0(r2) + 10069b0: d8c01a17 ldw r3,104(sp) + 10069b4: 0009883a mov r4,zero + 10069b8: 11401004 addi r5,r2,64 + 10069bc: d9401315 stw r5,76(sp) + 10069c0: d8801415 stw r2,80(sp) + 10069c4: d8c00715 stw r3,28(sp) + 10069c8: d9401717 ldw r5,92(sp) + 10069cc: d80d883a mov r6,sp + 10069d0: 10066d40 call 10066d4 <_Z17parse_lsda_headerP15_Unwind_ContextPKhP16lsda_header_info> + 10069d4: d8801417 ldw r2,80(sp) + 10069d8: d809883a mov r4,sp + 10069dc: d9801317 ldw r6,76(sp) + 10069e0: 11400017 ldw r5,0(r2) + 10069e4: d9c01617 ldw r7,88(sp) + 10069e8: 10068580 call 1006858 <_Z20check_exception_specP16lsda_header_infoPKSt9type_infoPvi> + 10069ec: 10803fcc andi r2,r2,255 + 10069f0: 1000151e bne r2,zero,1006a48 <__cxa_call_unexpected+0x16c> + 10069f4: d8c01a17 ldw r3,104(sp) + 10069f8: d809883a mov r4,sp + 10069fc: 014040b4 movhi r5,258 + 1006a00: 29450404 addi r5,r5,5136 + 1006a04: d8c00715 stw r3,28(sp) + 1006a08: 000d883a mov r6,zero + 1006a0c: d9c01617 ldw r7,88(sp) + 1006a10: 10068580 call 1006858 <_Z20check_exception_specP16lsda_header_infoPKSt9type_infoPvi> + 1006a14: 10803fcc andi r2,r2,255 + 1006a18: 10000c26 beq r2,zero,1006a4c <__cxa_call_unexpected+0x170> + 1006a1c: 01000104 movi r4,4 + 1006a20: 10075e00 call 10075e0 <__cxa_allocate_exception> + 1006a24: 1009883a mov r4,r2 + 1006a28: 008040b4 movhi r2,258 + 1006a2c: 1084f704 addi r2,r2,5084 + 1006a30: 20800015 stw r2,0(r4) + 1006a34: 014040b4 movhi r5,258 + 1006a38: 29450404 addi r5,r5,5136 + 1006a3c: 01804074 movhi r6,257 + 1006a40: 31a6a804 addi r6,r6,-25952 + 1006a44: 10072ac0 call 10072ac <__cxa_throw> + 1006a48: 10072380 call 1007238 <__cxa_rethrow> + 1006a4c: d9401a17 ldw r5,104(sp) + 1006a50: d9001517 ldw r4,84(sp) + 1006a54: d9400715 stw r5,28(sp) + 1006a58: 1006f640 call 1006f64 <_ZN10__cxxabiv111__terminateEPFvvE> + +01006a5c <__gxx_personality_sj0>: + 1006a5c: deffd304 addi sp,sp,-180 + 1006a60: 00804034 movhi r2,256 + 1006a64: 109bbe04 addi r2,r2,28408 + 1006a68: 00c040b4 movhi r3,258 + 1006a6c: 18c2fc04 addi r3,r3,3056 + 1006a70: d8801315 stw r2,76(sp) + 1006a74: d9002315 stw r4,140(sp) + 1006a78: 00804034 movhi r2,256 + 1006a7c: 109a9704 addi r2,r2,27228 + 1006a80: d9000a04 addi r4,sp,40 + 1006a84: d8801015 stw r2,64(sp) + 1006a88: d8c01115 stw r3,68(sp) + 1006a8c: dfc02c15 stw ra,176(sp) + 1006a90: df002b15 stw fp,172(sp) + 1006a94: ddc02a15 stw r23,168(sp) + 1006a98: dec01215 stw sp,72(sp) + 1006a9c: dec01415 stw sp,80(sp) + 1006aa0: d9802515 stw r6,148(sp) + 1006aa4: d9402415 stw r5,144(sp) + 1006aa8: d9c02615 stw r7,152(sp) + 1006aac: 1009c1c0 call 1009c1c <_Unwind_SjLj_Register> + 1006ab0: d8c02317 ldw r3,140(sp) + 1006ab4: 00800044 movi r2,1 + 1006ab8: 18800a26 beq r3,r2,1006ae4 <__gxx_personality_sj0+0x88> + 1006abc: 010000c4 movi r4,3 + 1006ac0: d9002215 stw r4,136(sp) + 1006ac4: d9000a04 addi r4,sp,40 + 1006ac8: 1009c2c0 call 1009c2c <_Unwind_SjLj_Unregister> + 1006acc: d8802217 ldw r2,136(sp) + 1006ad0: dfc02c17 ldw ra,176(sp) + 1006ad4: df002b17 ldw fp,172(sp) + 1006ad8: ddc02a17 ldw r23,168(sp) + 1006adc: dec02d04 addi sp,sp,180 + 1006ae0: f800283a ret + 1006ae4: d9402d17 ldw r5,180(sp) + 1006ae8: d9002517 ldw r4,148(sp) + 1006aec: 0007883a mov r3,zero + 1006af0: 28800504 addi r2,r5,20 + 1006af4: d8800015 stw r2,0(sp) + 1006af8: 28bff504 addi r2,r5,-44 + 1006afc: d8801a15 stw r2,104(sp) + 1006b00: 0090caf4 movhi r2,17195 + 1006b04: 108ac004 addi r2,r2,11008 + 1006b08: 2080ad26 beq r4,r2,1006dc0 <__gxx_personality_sj0+0x364> + 1006b0c: d8c02105 stb r3,132(sp) + 1006b10: d8c02417 ldw r3,144(sp) + 1006b14: 00800184 movi r2,6 + 1006b18: 1880281e bne r3,r2,1006bbc <__gxx_personality_sj0+0x160> + 1006b1c: d8802103 ldbu r2,132(sp) + 1006b20: 10002626 beq r2,zero,1006bbc <__gxx_personality_sj0+0x160> + 1006b24: d9001a17 ldw r4,104(sp) + 1006b28: d9401a17 ldw r5,104(sp) + 1006b2c: d8801a17 ldw r2,104(sp) + 1006b30: 21000917 ldw r4,36(r4) + 1006b34: 29400617 ldw r5,24(r5) + 1006b38: 10800817 ldw r2,32(r2) + 1006b3c: d9001d15 stw r4,116(sp) + 1006b40: d9401b15 stw r5,108(sp) + 1006b44: d8802015 stw r2,128(sp) + 1006b48: 2000ad1e bne r4,zero,1006e00 <__gxx_personality_sj0+0x3a4> + 1006b4c: 01000044 movi r4,1 + 1006b50: 00800044 movi r2,1 + 1006b54: 2080e126 beq r4,r2,1006edc <__gxx_personality_sj0+0x480> + 1006b58: d8801b17 ldw r2,108(sp) + 1006b5c: 1000d316 blt r2,zero,1006eac <__gxx_personality_sj0+0x450> + 1006b60: d9802d17 ldw r6,180(sp) + 1006b64: d9002e17 ldw r4,184(sp) + 1006b68: 00bfffc4 movi r2,-1 + 1006b6c: 000b883a mov r5,zero + 1006b70: d8800b15 stw r2,44(sp) + 1006b74: 1009c640 call 1009c64 <_Unwind_SetGR> + 1006b78: d9801b17 ldw r6,108(sp) + 1006b7c: d9002e17 ldw r4,184(sp) + 1006b80: 01400044 movi r5,1 + 1006b84: 1009c640 call 1009c64 <_Unwind_SetGR> + 1006b88: d9002e17 ldw r4,184(sp) + 1006b8c: d9401d17 ldw r5,116(sp) + 1006b90: 1009ca00 call 1009ca0 <_Unwind_SetIP> + 1006b94: 010001c4 movi r4,7 + 1006b98: d9002215 stw r4,136(sp) + 1006b9c: d9000a04 addi r4,sp,40 + 1006ba0: 1009c2c0 call 1009c2c <_Unwind_SjLj_Unregister> + 1006ba4: d8802217 ldw r2,136(sp) + 1006ba8: dfc02c17 ldw ra,176(sp) + 1006bac: df002b17 ldw fp,172(sp) + 1006bb0: ddc02a17 ldw r23,168(sp) + 1006bb4: dec02d04 addi sp,sp,180 + 1006bb8: f800283a ret + 1006bbc: d9002e17 ldw r4,184(sp) + 1006bc0: 00ffffc4 movi r3,-1 + 1006bc4: d8c00b15 stw r3,44(sp) + 1006bc8: 1009cb00 call 1009cb0 <_Unwind_GetLanguageSpecificData> + 1006bcc: 10007226 beq r2,zero,1006d98 <__gxx_personality_sj0+0x33c> + 1006bd0: d9002e17 ldw r4,184(sp) + 1006bd4: d9800404 addi r6,sp,16 + 1006bd8: 100b883a mov r5,r2 + 1006bdc: d8802015 stw r2,128(sp) + 1006be0: 10066d40 call 10066d4 <_Z17parse_lsda_headerP15_Unwind_ContextPKhP16lsda_header_info> + 1006be4: d9000903 ldbu r4,36(sp) + 1006be8: d9402e17 ldw r5,184(sp) + 1006bec: d8801e15 stw r2,120(sp) + 1006bf0: 10066440 call 1006644 <_Z21base_of_encoded_valuehP15_Unwind_Context> + 1006bf4: d9002e17 ldw r4,184(sp) + 1006bf8: d8800615 stw r2,24(sp) + 1006bfc: 1009c7c0 call 1009c7c <_Unwind_GetIP> + 1006c00: 10bfffc4 addi r2,r2,-1 + 1006c04: d8801c15 stw r2,112(sp) + 1006c08: 10006316 blt r2,zero,1006d98 <__gxx_personality_sj0+0x33c> + 1006c0c: 10001b1e bne r2,zero,1006c7c <__gxx_personality_sj0+0x220> + 1006c10: 01000044 movi r4,1 + 1006c14: d8001f15 stw zero,124(sp) + 1006c18: d8001d15 stw zero,116(sp) + 1006c1c: d8001b15 stw zero,108(sp) + 1006c20: d9402417 ldw r5,144(sp) + 1006c24: 00c00044 movi r3,1 + 1006c28: 28c4703a and r2,r5,r3 + 1006c2c: 1005003a cmpeq r2,r2,zero + 1006c30: 10006a1e bne r2,zero,1006ddc <__gxx_personality_sj0+0x380> + 1006c34: 00800084 movi r2,2 + 1006c38: 20805726 beq r4,r2,1006d98 <__gxx_personality_sj0+0x33c> + 1006c3c: d8802103 ldbu r2,132(sp) + 1006c40: 10008626 beq r2,zero,1006e5c <__gxx_personality_sj0+0x400> + 1006c44: d9001a17 ldw r4,104(sp) + 1006c48: d9401d17 ldw r5,116(sp) + 1006c4c: d8801b17 ldw r2,108(sp) + 1006c50: 00c00184 movi r3,6 + 1006c54: d8c02215 stw r3,136(sp) + 1006c58: 21400915 stw r5,36(r4) + 1006c5c: 20800615 stw r2,24(r4) + 1006c60: d8c01f17 ldw r3,124(sp) + 1006c64: d9402017 ldw r5,128(sp) + 1006c68: d8800017 ldw r2,0(sp) + 1006c6c: 20c00715 stw r3,28(r4) + 1006c70: 21400815 stw r5,32(r4) + 1006c74: 20800a15 stw r2,40(r4) + 1006c78: 003f9206 br 1006ac4 <__gxx_personality_sj0+0x68> + 1006c7c: d9001e17 ldw r4,120(sp) + 1006c80: d9400204 addi r5,sp,8 + 1006c84: 10063500 call 1006350 <_Z12read_uleb128PKhPj> + 1006c88: d9401c17 ldw r5,112(sp) + 1006c8c: 1009883a mov r4,r2 + 1006c90: 297fffc4 addi r5,r5,-1 + 1006c94: d9401c15 stw r5,112(sp) + 1006c98: d9400104 addi r5,sp,4 + 1006c9c: 10063500 call 1006350 <_Z12read_uleb128PKhPj> + 1006ca0: d8801e15 stw r2,120(sp) + 1006ca4: d8801c17 ldw r2,112(sp) + 1006ca8: 103ff41e bne r2,zero,1006c7c <__gxx_personality_sj0+0x220> + 1006cac: d8800217 ldw r2,8(sp) + 1006cb0: d8c00117 ldw r3,4(sp) + 1006cb4: 01000044 movi r4,1 + 1006cb8: 1105883a add r2,r2,r4 + 1006cbc: d8801d15 stw r2,116(sp) + 1006cc0: 1800541e bne r3,zero,1006e14 <__gxx_personality_sj0+0x3b8> + 1006cc4: d8001f15 stw zero,124(sp) + 1006cc8: d8c01d17 ldw r3,116(sp) + 1006ccc: 18003226 beq r3,zero,1006d98 <__gxx_personality_sj0+0x33c> + 1006cd0: d9001f17 ldw r4,124(sp) + 1006cd4: 20007226 beq r4,zero,1006ea0 <__gxx_personality_sj0+0x444> + 1006cd8: d9402417 ldw r5,144(sp) + 1006cdc: 2880020c andi r2,r5,8 + 1006ce0: 10006a1e bne r2,zero,1006e8c <__gxx_personality_sj0+0x430> + 1006ce4: d8802103 ldbu r2,132(sp) + 1006ce8: 10006826 beq r2,zero,1006e8c <__gxx_personality_sj0+0x430> + 1006cec: d8801a17 ldw r2,104(sp) + 1006cf0: 10800017 ldw r2,0(r2) + 1006cf4: d8801915 stw r2,100(sp) + 1006cf8: d8c01917 ldw r3,100(sp) + 1006cfc: d8001805 stb zero,96(sp) + 1006d00: 1807003a cmpeq r3,r3,zero + 1006d04: d8c02715 stw r3,156(sp) + 1006d08: 00000706 br 1006d28 <__gxx_personality_sj0+0x2cc> + 1006d0c: 01000044 movi r4,1 + 1006d10: d9001805 stb r4,96(sp) + 1006d14: d8800217 ldw r2,8(sp) + 1006d18: 10005e26 beq r2,zero,1006e94 <__gxx_personality_sj0+0x438> + 1006d1c: d8c01717 ldw r3,92(sp) + 1006d20: 1885883a add r2,r3,r2 + 1006d24: d8801f15 stw r2,124(sp) + 1006d28: d9001f17 ldw r4,124(sp) + 1006d2c: d9400104 addi r5,sp,4 + 1006d30: 10063800 call 1006380 <_Z12read_sleb128PKhPi> + 1006d34: 1009883a mov r4,r2 + 1006d38: d9400204 addi r5,sp,8 + 1006d3c: d8801715 stw r2,92(sp) + 1006d40: 10063800 call 1006380 <_Z12read_sleb128PKhPi> + 1006d44: d8800117 ldw r2,4(sp) + 1006d48: 103ff026 beq r2,zero,1006d0c <__gxx_personality_sj0+0x2b0> + 1006d4c: 0080360e bge zero,r2,1006e28 <__gxx_personality_sj0+0x3cc> + 1006d50: 017fffc4 movi r5,-1 + 1006d54: d9400b15 stw r5,44(sp) + 1006d58: d9000404 addi r4,sp,16 + 1006d5c: 100b883a mov r5,r2 + 1006d60: 10067d40 call 10067d4 <_Z15get_ttype_entryP16lsda_header_infoj> + 1006d64: 10000826 beq r2,zero,1006d88 <__gxx_personality_sj0+0x32c> + 1006d68: d8c02717 ldw r3,156(sp) + 1006d6c: 183fe91e bne r3,zero,1006d14 <__gxx_personality_sj0+0x2b8> + 1006d70: d9401917 ldw r5,100(sp) + 1006d74: 1009883a mov r4,r2 + 1006d78: d80d883a mov r6,sp + 1006d7c: 10063d40 call 10063d4 <_Z16get_adjusted_ptrPKSt9type_infoS1_PPv> + 1006d80: 10803fcc andi r2,r2,255 + 1006d84: 103fe326 beq r2,zero,1006d14 <__gxx_personality_sj0+0x2b8> + 1006d88: d9000117 ldw r4,4(sp) + 1006d8c: d9001b15 stw r4,108(sp) + 1006d90: 010000c4 movi r4,3 + 1006d94: 003fa206 br 1006c20 <__gxx_personality_sj0+0x1c4> + 1006d98: 01400204 movi r5,8 + 1006d9c: d9000a04 addi r4,sp,40 + 1006da0: d9402215 stw r5,136(sp) + 1006da4: 1009c2c0 call 1009c2c <_Unwind_SjLj_Unregister> + 1006da8: d8802217 ldw r2,136(sp) + 1006dac: dfc02c17 ldw ra,176(sp) + 1006db0: df002b17 ldw fp,172(sp) + 1006db4: ddc02a17 ldw r23,168(sp) + 1006db8: dec02d04 addi sp,sp,180 + 1006dbc: f800283a ret + 1006dc0: d9402617 ldw r5,152(sp) + 1006dc4: 0091d3b4 movhi r2,18254 + 1006dc8: 109550c4 addi r2,r2,21827 + 1006dcc: 28bf4f1e bne r5,r2,1006b0c <__gxx_personality_sj0+0xb0> + 1006dd0: d8802317 ldw r2,140(sp) + 1006dd4: 1007883a mov r3,r2 + 1006dd8: 003f4c06 br 1006b0c <__gxx_personality_sj0+0xb0> + 1006ddc: d9402417 ldw r5,144(sp) + 1006de0: 2880020c andi r2,r5,8 + 1006de4: 10000826 beq r2,zero,1006e08 <__gxx_personality_sj0+0x3ac> + 1006de8: 20c04026 beq r4,r3,1006eec <__gxx_personality_sj0+0x490> + 1006dec: d8801b17 ldw r2,108(sp) + 1006df0: 103f5b0e bge r2,zero,1006b60 <__gxx_personality_sj0+0x104> + 1006df4: 00800084 movi r2,2 + 1006df8: d8800b15 stw r2,44(sp) + 1006dfc: 10070300 call 1007030 <_ZSt10unexpectedv> + 1006e00: 010000c4 movi r4,3 + 1006e04: 003f5206 br 1006b50 <__gxx_personality_sj0+0xf4> + 1006e08: d8802103 ldbu r2,132(sp) + 1006e0c: 103f501e bne r2,zero,1006b50 <__gxx_personality_sj0+0xf4> + 1006e10: 003ff506 br 1006de8 <__gxx_personality_sj0+0x38c> + 1006e14: d8800817 ldw r2,32(sp) + 1006e18: 1885883a add r2,r3,r2 + 1006e1c: 1105c83a sub r2,r2,r4 + 1006e20: d8801f15 stw r2,124(sp) + 1006e24: 003fa806 br 1006cc8 <__gxx_personality_sj0+0x26c> + 1006e28: d9002717 ldw r4,156(sp) + 1006e2c: 20000e1e bne r4,zero,1006e68 <__gxx_personality_sj0+0x40c> + 1006e30: 017fffc4 movi r5,-1 + 1006e34: d9400b15 stw r5,44(sp) + 1006e38: d9800017 ldw r6,0(sp) + 1006e3c: d9401917 ldw r5,100(sp) + 1006e40: 100f883a mov r7,r2 + 1006e44: d9000404 addi r4,sp,16 + 1006e48: 10068580 call 1006858 <_Z20check_exception_specP16lsda_header_infoPKSt9type_infoPvi> + 1006e4c: 1080005c xori r2,r2,1 + 1006e50: 10803fcc andi r2,r2,255 + 1006e54: 103faf26 beq r2,zero,1006d14 <__gxx_personality_sj0+0x2b8> + 1006e58: 003fcb06 br 1006d88 <__gxx_personality_sj0+0x32c> + 1006e5c: 00800184 movi r2,6 + 1006e60: d8802215 stw r2,136(sp) + 1006e64: 003f1706 br 1006ac4 <__gxx_personality_sj0+0x68> + 1006e68: d9000717 ldw r4,28(sp) + 1006e6c: d9400304 addi r5,sp,12 + 1006e70: 2089c83a sub r4,r4,r2 + 1006e74: 213fffc4 addi r4,r4,-1 + 1006e78: 10063500 call 1006350 <_Z12read_uleb128PKhPj> + 1006e7c: d8c00317 ldw r3,12(sp) + 1006e80: 1807003a cmpeq r3,r3,zero + 1006e84: 1805883a mov r2,r3 + 1006e88: 003ff106 br 1006e50 <__gxx_personality_sj0+0x3f4> + 1006e8c: d8001915 stw zero,100(sp) + 1006e90: 003f9906 br 1006cf8 <__gxx_personality_sj0+0x29c> + 1006e94: d8801803 ldbu r2,96(sp) + 1006e98: 1004c03a cmpne r2,r2,zero + 1006e9c: 103fbe26 beq r2,zero,1006d98 <__gxx_personality_sj0+0x33c> + 1006ea0: 01000084 movi r4,2 + 1006ea4: d8001b15 stw zero,108(sp) + 1006ea8: 003f5d06 br 1006c20 <__gxx_personality_sj0+0x1c4> + 1006eac: d9402017 ldw r5,128(sp) + 1006eb0: d9002e17 ldw r4,184(sp) + 1006eb4: 00bfffc4 movi r2,-1 + 1006eb8: d9800404 addi r6,sp,16 + 1006ebc: d8800b15 stw r2,44(sp) + 1006ec0: 10066d40 call 10066d4 <_Z17parse_lsda_headerP15_Unwind_ContextPKhP16lsda_header_info> + 1006ec4: d9000903 ldbu r4,36(sp) + 1006ec8: d9402e17 ldw r5,184(sp) + 1006ecc: 10066440 call 1006644 <_Z21base_of_encoded_valuehP15_Unwind_Context> + 1006ed0: d8c01a17 ldw r3,104(sp) + 1006ed4: 18800915 stw r2,36(r3) + 1006ed8: 003f2106 br 1006b60 <__gxx_personality_sj0+0x104> + 1006edc: d9002d17 ldw r4,180(sp) + 1006ee0: 00bfffc4 movi r2,-1 + 1006ee4: d8800b15 stw r2,44(sp) + 1006ee8: 1009ac00 call 1009ac0 <__cxa_call_terminate> + 1006eec: 00bfffc4 movi r2,-1 + 1006ef0: d8800b15 stw r2,44(sp) + 1006ef4: 10070080 call 1007008 <_ZSt9terminatev> + 1006ef8: d9000b17 ldw r4,44(sp) + 1006efc: d9400c17 ldw r5,48(sp) + 1006f00: 00800044 movi r2,1 + 1006f04: d9002915 stw r4,164(sp) + 1006f08: d9402815 stw r5,160(sp) + 1006f0c: 20800626 beq r4,r2,1006f28 <__gxx_personality_sj0+0x4cc> + 1006f10: d8000b15 stw zero,44(sp) + 1006f14: 10070700 call 1007070 <__cxa_end_catch> + 1006f18: d9002817 ldw r4,160(sp) + 1006f1c: 00bfffc4 movi r2,-1 + 1006f20: d8800b15 stw r2,44(sp) + 1006f24: 1009ee80 call 1009ee8 <_Unwind_SjLj_Resume> + 1006f28: d9002817 ldw r4,160(sp) + 1006f2c: 10071140 call 1007114 <__cxa_begin_catch> + 1006f30: d8c02917 ldw r3,164(sp) + 1006f34: d8c00b15 stw r3,44(sp) + 1006f38: 10070080 call 1007008 <_ZSt9terminatev> + +01006f3c <_ZSt13set_terminatePFvvE>: + 1006f3c: 00c040b4 movhi r3,258 + 1006f40: 18cdbe04 addi r3,r3,14072 + 1006f44: 18800017 ldw r2,0(r3) + 1006f48: 19000015 stw r4,0(r3) + 1006f4c: f800283a ret + +01006f50 <_ZSt14set_unexpectedPFvvE>: + 1006f50: 00c040b4 movhi r3,258 + 1006f54: 18cdc404 addi r3,r3,14096 + 1006f58: 18800017 ldw r2,0(r3) + 1006f5c: 19000015 stw r4,0(r3) + 1006f60: f800283a ret + +01006f64 <_ZN10__cxxabiv111__terminateEPFvvE>: + 1006f64: deffed04 addi sp,sp,-76 + 1006f68: 00804034 movhi r2,256 + 1006f6c: 109a9704 addi r2,r2,27228 + 1006f70: d8800615 stw r2,24(sp) + 1006f74: 00c040b4 movhi r3,258 + 1006f78: 18c30004 addi r3,r3,3072 + 1006f7c: 00804034 movhi r2,256 + 1006f80: 109bf004 addi r2,r2,28608 + 1006f84: d9000d15 stw r4,52(sp) + 1006f88: d809883a mov r4,sp + 1006f8c: d8800915 stw r2,36(sp) + 1006f90: dfc01215 stw ra,72(sp) + 1006f94: df001115 stw fp,68(sp) + 1006f98: ddc01015 stw r23,64(sp) + 1006f9c: d8c00715 stw r3,28(sp) + 1006fa0: dec00815 stw sp,32(sp) + 1006fa4: dec00a15 stw sp,40(sp) + 1006fa8: 1009c1c0 call 1009c1c <_Unwind_SjLj_Register> + 1006fac: 00800084 movi r2,2 + 1006fb0: d8800115 stw r2,4(sp) + 1006fb4: d8800d17 ldw r2,52(sp) + 1006fb8: 103ee83a callr r2 + 1006fbc: 100a1640 call 100a164 + 1006fc0: d8800117 ldw r2,4(sp) + 1006fc4: d8c00217 ldw r3,8(sp) + 1006fc8: d8800f15 stw r2,60(sp) + 1006fcc: d8c00e15 stw r3,56(sp) + 1006fd0: d8c00f17 ldw r3,60(sp) + 1006fd4: 00800044 movi r2,1 + 1006fd8: 18800626 beq r3,r2,1006ff4 <_ZN10__cxxabiv111__terminateEPFvvE+0x90> + 1006fdc: d8000115 stw zero,4(sp) + 1006fe0: 10070700 call 1007070 <__cxa_end_catch> + 1006fe4: d9000e17 ldw r4,56(sp) + 1006fe8: 00bfffc4 movi r2,-1 + 1006fec: d8800115 stw r2,4(sp) + 1006ff0: 1009ee80 call 1009ee8 <_Unwind_SjLj_Resume> + 1006ff4: d9000e17 ldw r4,56(sp) + 1006ff8: 10071140 call 1007114 <__cxa_begin_catch> + 1006ffc: d8c00f17 ldw r3,60(sp) + 1007000: d8c00115 stw r3,4(sp) + 1007004: 100a1640 call 100a164 + +01007008 <_ZSt9terminatev>: + 1007008: 008040b4 movhi r2,258 + 100700c: 108dbe04 addi r2,r2,14072 + 1007010: 11000017 ldw r4,0(r2) + 1007014: deffff04 addi sp,sp,-4 + 1007018: dfc00015 stw ra,0(sp) + 100701c: 1006f640 call 1006f64 <_ZN10__cxxabiv111__terminateEPFvvE> + +01007020 <_ZN10__cxxabiv112__unexpectedEPFvvE>: + 1007020: deffff04 addi sp,sp,-4 + 1007024: dfc00015 stw ra,0(sp) + 1007028: 203ee83a callr r4 + 100702c: 10070080 call 1007008 <_ZSt9terminatev> + +01007030 <_ZSt10unexpectedv>: + 1007030: 008040b4 movhi r2,258 + 1007034: 108dc404 addi r2,r2,14096 + 1007038: 11000017 ldw r4,0(r2) + 100703c: deffff04 addi sp,sp,-4 + 1007040: dfc00015 stw ra,0(sp) + 1007044: 10070200 call 1007020 <_ZN10__cxxabiv112__unexpectedEPFvvE> + +01007048 <__cxa_get_exception_ptr>: + 1007048: 20bfff17 ldw r2,-4(r4) + 100704c: f800283a ret + +01007050 <_ZSt18uncaught_exceptionv>: + 1007050: deffff04 addi sp,sp,-4 + 1007054: dfc00015 stw ra,0(sp) + 1007058: 1009b6c0 call 1009b6c <__cxa_get_globals> + 100705c: 10800117 ldw r2,4(r2) + 1007060: 1004c03a cmpne r2,r2,zero + 1007064: dfc00017 ldw ra,0(sp) + 1007068: dec00104 addi sp,sp,4 + 100706c: f800283a ret + +01007070 <__cxa_end_catch>: + 1007070: deffff04 addi sp,sp,-4 + 1007074: dfc00015 stw ra,0(sp) + 1007078: 1009b640 call 1009b64 <__cxa_get_globals_fast> + 100707c: 11000017 ldw r4,0(r2) + 1007080: 1007883a mov r3,r2 + 1007084: 20001326 beq r4,zero,10070d4 <__cxa_end_catch+0x64> + 1007088: 21400b17 ldw r5,44(r4) + 100708c: 0090caf4 movhi r2,17195 + 1007090: 108ac004 addi r2,r2,11008 + 1007094: 21800c17 ldw r6,48(r4) + 1007098: 28800526 beq r5,r2,10070b0 <__cxa_end_catch+0x40> + 100709c: 21000b04 addi r4,r4,44 + 10070a0: 18000015 stw zero,0(r3) + 10070a4: dfc00017 ldw ra,0(sp) + 10070a8: dec00104 addi sp,sp,4 + 10070ac: 1009ddc1 jmpi 1009ddc <_Unwind_DeleteException> + 10070b0: 0091d3b4 movhi r2,18254 + 10070b4: 109550c4 addi r2,r2,21827 + 10070b8: 30bff81e bne r6,r2,100709c <__cxa_end_catch+0x2c> + 10070bc: 20800517 ldw r2,20(r4) + 10070c0: 10000e16 blt r2,zero,10070fc <__cxa_end_catch+0x8c> + 10070c4: 117fffc4 addi r5,r2,-1 + 10070c8: 28000526 beq r5,zero,10070e0 <__cxa_end_catch+0x70> + 10070cc: 28000a16 blt r5,zero,10070f8 <__cxa_end_catch+0x88> + 10070d0: 21400515 stw r5,20(r4) + 10070d4: dfc00017 ldw ra,0(sp) + 10070d8: dec00104 addi sp,sp,4 + 10070dc: f800283a ret + 10070e0: 20800417 ldw r2,16(r4) + 10070e4: 21000b04 addi r4,r4,44 + 10070e8: 18800015 stw r2,0(r3) + 10070ec: dfc00017 ldw ra,0(sp) + 10070f0: dec00104 addi sp,sp,4 + 10070f4: 1009ddc1 jmpi 1009ddc <_Unwind_DeleteException> + 10070f8: 10070080 call 1007008 <_ZSt9terminatev> + 10070fc: 11400044 addi r5,r2,1 + 1007100: 283ff31e bne r5,zero,10070d0 <__cxa_end_catch+0x60> + 1007104: 20800417 ldw r2,16(r4) + 1007108: 21400515 stw r5,20(r4) + 100710c: 18800015 stw r2,0(r3) + 1007110: 003ff006 br 10070d4 <__cxa_end_catch+0x64> + +01007114 <__cxa_begin_catch>: + 1007114: deffee04 addi sp,sp,-72 + 1007118: 00804034 movhi r2,256 + 100711c: 109a9704 addi r2,r2,27228 + 1007120: 00c040b4 movhi r3,258 + 1007124: 18c30404 addi r3,r3,3088 + 1007128: d8800615 stw r2,24(sp) + 100712c: d9000e15 stw r4,56(sp) + 1007130: 00804034 movhi r2,256 + 1007134: 109c8204 addi r2,r2,29192 + 1007138: d809883a mov r4,sp + 100713c: d8c00715 stw r3,28(sp) + 1007140: dfc01115 stw ra,68(sp) + 1007144: d8800915 stw r2,36(sp) + 1007148: df001015 stw fp,64(sp) + 100714c: ddc00f15 stw r23,60(sp) + 1007150: dec00815 stw sp,32(sp) + 1007154: dec00a15 stw sp,40(sp) + 1007158: 1009c1c0 call 1009c1c <_Unwind_SjLj_Register> + 100715c: 1009b6c0 call 1009b6c <__cxa_get_globals> + 1007160: 100d883a mov r6,r2 + 1007164: d8800e17 ldw r2,56(sp) + 1007168: 31c00017 ldw r7,0(r6) + 100716c: 117ff504 addi r5,r2,-44 + 1007170: 28c00b17 ldw r3,44(r5) + 1007174: 0090caf4 movhi r2,17195 + 1007178: 108ac004 addi r2,r2,11008 + 100717c: 29000c17 ldw r4,48(r5) + 1007180: 18800b26 beq r3,r2,10071b0 <__cxa_begin_catch+0x9c> + 1007184: 38001d1e bne r7,zero,10071fc <__cxa_begin_catch+0xe8> + 1007188: d8000d15 stw zero,52(sp) + 100718c: 31400015 stw r5,0(r6) + 1007190: d809883a mov r4,sp + 1007194: 1009c2c0 call 1009c2c <_Unwind_SjLj_Unregister> + 1007198: d8800d17 ldw r2,52(sp) + 100719c: dfc01117 ldw ra,68(sp) + 10071a0: df001017 ldw fp,64(sp) + 10071a4: ddc00f17 ldw r23,60(sp) + 10071a8: dec01204 addi sp,sp,72 + 10071ac: f800283a ret + 10071b0: 0091d3b4 movhi r2,18254 + 10071b4: 109550c4 addi r2,r2,21827 + 10071b8: 20bff21e bne r4,r2,1007184 <__cxa_begin_catch+0x70> + 10071bc: 28c00517 ldw r3,20(r5) + 10071c0: 18000b16 blt r3,zero,10071f0 <__cxa_begin_catch+0xdc> + 10071c4: 18800044 addi r2,r3,1 + 10071c8: 28800515 stw r2,20(r5) + 10071cc: 30800117 ldw r2,4(r6) + 10071d0: 10bfffc4 addi r2,r2,-1 + 10071d4: 30800115 stw r2,4(r6) + 10071d8: 39400226 beq r7,r5,10071e4 <__cxa_begin_catch+0xd0> + 10071dc: 29c00415 stw r7,16(r5) + 10071e0: 31400015 stw r5,0(r6) + 10071e4: 29400a17 ldw r5,40(r5) + 10071e8: d9400d15 stw r5,52(sp) + 10071ec: 003fe806 br 1007190 <__cxa_begin_catch+0x7c> + 10071f0: 00800044 movi r2,1 + 10071f4: 10c5c83a sub r2,r2,r3 + 10071f8: 003ff306 br 10071c8 <__cxa_begin_catch+0xb4> + 10071fc: 00800044 movi r2,1 + 1007200: d8800115 stw r2,4(sp) + 1007204: 10070080 call 1007008 <_ZSt9terminatev> + 1007208: d8800317 ldw r2,12(sp) + 100720c: 00ffffc4 movi r3,-1 + 1007210: d9000217 ldw r4,8(sp) + 1007214: 10c00226 beq r2,r3,1007220 <__cxa_begin_catch+0x10c> + 1007218: d8c00115 stw r3,4(sp) + 100721c: 1009ee80 call 1009ee8 <_Unwind_SjLj_Resume> + 1007220: 00bfffc4 movi r2,-1 + 1007224: d8800115 stw r2,4(sp) + 1007228: 10068dc0 call 10068dc <__cxa_call_unexpected> + +0100722c <_ZdlPv>: + 100722c: 20000126 beq r4,zero,1007234 <_ZdlPv+0x8> + 1007230: 100a17c1 jmpi 100a17c + 1007234: f800283a ret + +01007238 <__cxa_rethrow>: + 1007238: defffe04 addi sp,sp,-8 + 100723c: dc400015 stw r17,0(sp) + 1007240: dfc00115 stw ra,4(sp) + 1007244: 1009b6c0 call 1009b6c <__cxa_get_globals> + 1007248: 100b883a mov r5,r2 + 100724c: 10800117 ldw r2,4(r2) + 1007250: 2c400017 ldw r17,0(r5) + 1007254: 10800044 addi r2,r2,1 + 1007258: 28800115 stw r2,4(r5) + 100725c: 88000b26 beq r17,zero,100728c <__cxa_rethrow+0x54> + 1007260: 88c00b17 ldw r3,44(r17) + 1007264: 0090caf4 movhi r2,17195 + 1007268: 108ac004 addi r2,r2,11008 + 100726c: 89000c17 ldw r4,48(r17) + 1007270: 18800726 beq r3,r2,1007290 <__cxa_rethrow+0x58> + 1007274: 28000015 stw zero,0(r5) + 1007278: 8c400b04 addi r17,r17,44 + 100727c: 8809883a mov r4,r17 + 1007280: 100a10c0 call 100a10c <_Unwind_SjLj_Resume_or_Rethrow> + 1007284: 8809883a mov r4,r17 + 1007288: 10071140 call 1007114 <__cxa_begin_catch> + 100728c: 10070080 call 1007008 <_ZSt9terminatev> + 1007290: 0091d3b4 movhi r2,18254 + 1007294: 109550c4 addi r2,r2,21827 + 1007298: 20bff61e bne r4,r2,1007274 <__cxa_rethrow+0x3c> + 100729c: 88800517 ldw r2,20(r17) + 10072a0: 0085c83a sub r2,zero,r2 + 10072a4: 88800515 stw r2,20(r17) + 10072a8: 003ff306 br 1007278 <__cxa_rethrow+0x40> + +010072ac <__cxa_throw>: + 10072ac: 008040b4 movhi r2,258 + 10072b0: 108dc404 addi r2,r2,14096 + 10072b4: 00c040b4 movhi r3,258 + 10072b8: 18cdbe04 addi r3,r3,14072 + 10072bc: 12000017 ldw r8,0(r2) + 10072c0: 19c00017 ldw r7,0(r3) + 10072c4: defffe04 addi sp,sp,-8 + 10072c8: 213ff004 addi r4,r4,-64 + 10072cc: dfc00115 stw ra,4(sp) + 10072d0: dc400015 stw r17,0(sp) + 10072d4: 0090caf4 movhi r2,17195 + 10072d8: 108ac004 addi r2,r2,11008 + 10072dc: 20800b15 stw r2,44(r4) + 10072e0: 00d1d3b4 movhi r3,18254 + 10072e4: 18d550c4 addi r3,r3,21827 + 10072e8: 24400b04 addi r17,r4,44 + 10072ec: 00804034 movhi r2,256 + 10072f0: 109cc804 addi r2,r2,29472 + 10072f4: 21400015 stw r5,0(r4) + 10072f8: 21800115 stw r6,4(r4) + 10072fc: 22000215 stw r8,8(r4) + 1007300: 21c00315 stw r7,12(r4) + 1007304: 20c00c15 stw r3,48(r4) + 1007308: 20800d15 stw r2,52(r4) + 100730c: 8809883a mov r4,r17 + 1007310: 1009f440 call 1009f44 <_Unwind_SjLj_RaiseException> + 1007314: 8809883a mov r4,r17 + 1007318: 10071140 call 1007114 <__cxa_begin_catch> + 100731c: 10070080 call 1007008 <_ZSt9terminatev> + +01007320 <_Z23__gxx_exception_cleanup19_Unwind_Reason_CodeP17_Unwind_Exception>: + 1007320: defffe04 addi sp,sp,-8 + 1007324: 00800044 movi r2,1 + 1007328: dfc00115 stw ra,4(sp) + 100732c: dc000015 stw r16,0(sp) + 1007330: 28fff504 addi r3,r5,-44 + 1007334: 11001036 bltu r2,r4,1007378 <_Z23__gxx_exception_cleanup19_Unwind_Reason_CodeP17_Unwind_Exception+0x58> + 1007338: 18800117 ldw r2,4(r3) + 100733c: 10000826 beq r2,zero,1007360 <_Z23__gxx_exception_cleanup19_Unwind_Reason_CodeP17_Unwind_Exception+0x40> + 1007340: 2c000504 addi r16,r5,20 + 1007344: 8009883a mov r4,r16 + 1007348: 103ee83a callr r2 + 100734c: 8009883a mov r4,r16 + 1007350: dfc00117 ldw ra,4(sp) + 1007354: dc000017 ldw r16,0(sp) + 1007358: dec00204 addi sp,sp,8 + 100735c: 10075a01 jmpi 10075a0 <__cxa_free_exception> + 1007360: 2c000504 addi r16,r5,20 + 1007364: 8009883a mov r4,r16 + 1007368: dfc00117 ldw ra,4(sp) + 100736c: dc000017 ldw r16,0(sp) + 1007370: dec00204 addi sp,sp,8 + 1007374: 10075a01 jmpi 10075a0 <__cxa_free_exception> + 1007378: 19000317 ldw r4,12(r3) + 100737c: 1006f640 call 1006f64 <_ZN10__cxxabiv111__terminateEPFvvE> + +01007380 <_ZNK10__cxxabiv120__si_class_type_info11__do_upcastEPKNS_17__class_type_infoEPKvRNS1_15__upcast_resultE>: + 1007380: defffb04 addi sp,sp,-20 + 1007384: dd400315 stw r21,12(sp) + 1007388: dcc00215 stw r19,8(sp) + 100738c: dc400115 stw r17,4(sp) + 1007390: dc000015 stw r16,0(sp) + 1007394: 2823883a mov r17,r5 + 1007398: 3027883a mov r19,r6 + 100739c: 382b883a mov r21,r7 + 10073a0: dfc00415 stw ra,16(sp) + 10073a4: 2021883a mov r16,r4 + 10073a8: 10062d40 call 10062d4 <_ZNK10__cxxabiv117__class_type_info11__do_upcastEPKS0_PKvRNS0_15__upcast_resultE> + 10073ac: 10803fcc andi r2,r2,255 + 10073b0: 880b883a mov r5,r17 + 10073b4: 980d883a mov r6,r19 + 10073b8: a80f883a mov r7,r21 + 10073bc: 00c00044 movi r3,1 + 10073c0: 1000051e bne r2,zero,10073d8 <_ZNK10__cxxabiv120__si_class_type_info11__do_upcastEPKNS_17__class_type_infoEPKvRNS1_15__upcast_resultE+0x58> + 10073c4: 81000217 ldw r4,8(r16) + 10073c8: 20800017 ldw r2,0(r4) + 10073cc: 10c00617 ldw r3,24(r2) + 10073d0: 183ee83a callr r3 + 10073d4: 10c03fcc andi r3,r2,255 + 10073d8: 1805883a mov r2,r3 + 10073dc: dfc00417 ldw ra,16(sp) + 10073e0: dd400317 ldw r21,12(sp) + 10073e4: dcc00217 ldw r19,8(sp) + 10073e8: dc400117 ldw r17,4(sp) + 10073ec: dc000017 ldw r16,0(sp) + 10073f0: dec00504 addi sp,sp,20 + 10073f4: f800283a ret + +010073f8 <_ZN10__cxxabiv120__si_class_type_infoD0Ev>: + 10073f8: defffe04 addi sp,sp,-8 + 10073fc: 008040b4 movhi r2,258 + 1007400: 10845104 addi r2,r2,4420 + 1007404: dc400015 stw r17,0(sp) + 1007408: 20800015 stw r2,0(r4) + 100740c: 2023883a mov r17,r4 + 1007410: dfc00115 stw ra,4(sp) + 1007414: 10062640 call 1006264 <_ZN10__cxxabiv117__class_type_infoD2Ev> + 1007418: 8809883a mov r4,r17 + 100741c: dfc00117 ldw ra,4(sp) + 1007420: dc400017 ldw r17,0(sp) + 1007424: dec00204 addi sp,sp,8 + 1007428: 100722c1 jmpi 100722c <_ZdlPv> + +0100742c <_ZN10__cxxabiv120__si_class_type_infoD1Ev>: + 100742c: 008040b4 movhi r2,258 + 1007430: 10845104 addi r2,r2,4420 + 1007434: 20800015 stw r2,0(r4) + 1007438: 10062641 jmpi 1006264 <_ZN10__cxxabiv117__class_type_infoD2Ev> + +0100743c <_ZN10__cxxabiv120__si_class_type_infoD2Ev>: + 100743c: 008040b4 movhi r2,258 + 1007440: 10845104 addi r2,r2,4420 + 1007444: 20800015 stw r2,0(r4) + 1007448: 10062641 jmpi 1006264 <_ZN10__cxxabiv117__class_type_infoD2Ev> + +0100744c <_ZNK10__cxxabiv120__si_class_type_info20__do_find_public_srcElPKvPKNS_17__class_type_infoES2_>: + 100744c: da400017 ldw r9,0(sp) + 1007450: 2011883a mov r8,r4 + 1007454: 49800526 beq r9,r6,100746c <_ZNK10__cxxabiv120__si_class_type_info20__do_find_public_srcElPKvPKNS_17__class_type_infoES2_+0x20> + 1007458: 41000217 ldw r4,8(r8) + 100745c: 20800017 ldw r2,0(r4) + 1007460: da400015 stw r9,0(sp) + 1007464: 10c00817 ldw r3,32(r2) + 1007468: 1800683a jmp r3 + 100746c: 39000117 ldw r4,4(r7) + 1007470: 40c00117 ldw r3,4(r8) + 1007474: 00800184 movi r2,6 + 1007478: 193ff71e bne r3,r4,1007458 <_ZNK10__cxxabiv120__si_class_type_info20__do_find_public_srcElPKvPKNS_17__class_type_infoES2_+0xc> + 100747c: f800283a ret + +01007480 <_ZNK10__cxxabiv120__si_class_type_info12__do_dyncastElNS_17__class_type_info10__sub_kindEPKS1_PKvS4_S6_RNS1_16__dyncast_resultE>: + 1007480: 20c00117 ldw r3,4(r4) + 1007484: 38800117 ldw r2,4(r7) + 1007488: defffb04 addi sp,sp,-20 + 100748c: dfc00415 stw ra,16(sp) + 1007490: da000517 ldw r8,20(sp) + 1007494: dac00617 ldw r11,24(sp) + 1007498: da400717 ldw r9,28(sp) + 100749c: da800817 ldw r10,32(sp) + 10074a0: 18800c1e bne r3,r2,10074d4 <_ZNK10__cxxabiv120__si_class_type_info12__do_dyncastElNS_17__class_type_info10__sub_kindEPKS1_PKvS4_S6_RNS1_16__dyncast_resultE+0x54> + 10074a4: 51800115 stw r6,4(r10) + 10074a8: 52000015 stw r8,0(r10) + 10074ac: 28001c16 blt r5,zero,1007520 <_ZNK10__cxxabiv120__si_class_type_info12__do_dyncastElNS_17__class_type_info10__sub_kindEPKS1_PKvS4_S6_RNS1_16__dyncast_resultE+0xa0> + 10074b0: 4145883a add r2,r8,r5 + 10074b4: 48801e26 beq r9,r2,1007530 <_ZNK10__cxxabiv120__si_class_type_info12__do_dyncastElNS_17__class_type_info10__sub_kindEPKS1_PKvS4_S6_RNS1_16__dyncast_resultE+0xb0> + 10074b8: 00800044 movi r2,1 + 10074bc: 0007883a mov r3,zero + 10074c0: 50800315 stw r2,12(r10) + 10074c4: 1805883a mov r2,r3 + 10074c8: dfc00417 ldw ra,16(sp) + 10074cc: dec00504 addi sp,sp,20 + 10074d0: f800283a ret + 10074d4: 42400d26 beq r8,r9,100750c <_ZNK10__cxxabiv120__si_class_type_info12__do_dyncastElNS_17__class_type_info10__sub_kindEPKS1_PKvS4_S6_RNS1_16__dyncast_resultE+0x8c> + 10074d8: 21000217 ldw r4,8(r4) + 10074dc: 20800017 ldw r2,0(r4) + 10074e0: da000015 stw r8,0(sp) + 10074e4: dac00115 stw r11,4(sp) + 10074e8: da400215 stw r9,8(sp) + 10074ec: da800315 stw r10,12(sp) + 10074f0: 10c00717 ldw r3,28(r2) + 10074f4: 183ee83a callr r3 + 10074f8: 10c03fcc andi r3,r2,255 + 10074fc: 1805883a mov r2,r3 + 1007500: dfc00417 ldw ra,16(sp) + 1007504: dec00504 addi sp,sp,20 + 1007508: f800283a ret + 100750c: 58800117 ldw r2,4(r11) + 1007510: 18bff11e bne r3,r2,10074d8 <_ZNK10__cxxabiv120__si_class_type_info12__do_dyncastElNS_17__class_type_info10__sub_kindEPKS1_PKvS4_S6_RNS1_16__dyncast_resultE+0x58> + 1007514: 0007883a mov r3,zero + 1007518: 51800215 stw r6,8(r10) + 100751c: 003fe906 br 10074c4 <_ZNK10__cxxabiv120__si_class_type_info12__do_dyncastElNS_17__class_type_info10__sub_kindEPKS1_PKvS4_S6_RNS1_16__dyncast_resultE+0x44> + 1007520: 00bfff84 movi r2,-2 + 1007524: 28800426 beq r5,r2,1007538 <_ZNK10__cxxabiv120__si_class_type_info12__do_dyncastElNS_17__class_type_info10__sub_kindEPKS1_PKvS4_S6_RNS1_16__dyncast_resultE+0xb8> + 1007528: 0007883a mov r3,zero + 100752c: 003fe506 br 10074c4 <_ZNK10__cxxabiv120__si_class_type_info12__do_dyncastElNS_17__class_type_info10__sub_kindEPKS1_PKvS4_S6_RNS1_16__dyncast_resultE+0x44> + 1007530: 00800184 movi r2,6 + 1007534: 003fe106 br 10074bc <_ZNK10__cxxabiv120__si_class_type_info12__do_dyncastElNS_17__class_type_info10__sub_kindEPKS1_PKvS4_S6_RNS1_16__dyncast_resultE+0x3c> + 1007538: 00800044 movi r2,1 + 100753c: 0007883a mov r3,zero + 1007540: 50800315 stw r2,12(r10) + 1007544: 003fdf06 br 10074c4 <_ZNK10__cxxabiv120__si_class_type_info12__do_dyncastElNS_17__class_type_info10__sub_kindEPKS1_PKvS4_S6_RNS1_16__dyncast_resultE+0x44> + +01007548 <_ZNKSt9type_info14__is_pointer_pEv>: + 1007548: 0005883a mov r2,zero + 100754c: f800283a ret + +01007550 <_ZNKSt9type_info15__is_function_pEv>: + 1007550: 0005883a mov r2,zero + 1007554: f800283a ret + +01007558 <_ZNKSt9type_info10__do_catchEPKS_PPvj>: + 1007558: 20c00117 ldw r3,4(r4) + 100755c: 28800117 ldw r2,4(r5) + 1007560: 1885003a cmpeq r2,r3,r2 + 1007564: f800283a ret + +01007568 <_ZNKSt9type_info11__do_upcastEPKN10__cxxabiv117__class_type_infoEPPv>: + 1007568: 0005883a mov r2,zero + 100756c: f800283a ret + +01007570 <_ZNSt9type_infoD0Ev>: + 1007570: 008040b4 movhi r2,258 + 1007574: 10846904 addi r2,r2,4516 + 1007578: 20800015 stw r2,0(r4) + 100757c: 100722c1 jmpi 100722c <_ZdlPv> + +01007580 <_ZNSt9type_infoD1Ev>: + 1007580: 008040b4 movhi r2,258 + 1007584: 10846904 addi r2,r2,4516 + 1007588: 20800015 stw r2,0(r4) + 100758c: f800283a ret + +01007590 <_ZNSt9type_infoD2Ev>: + 1007590: 008040b4 movhi r2,258 + 1007594: 10846904 addi r2,r2,4516 + 1007598: 20800015 stw r2,0(r4) + 100759c: f800283a ret + +010075a0 <__cxa_free_exception>: + 10075a0: 2007883a mov r3,r4 + 10075a4: 008040f4 movhi r2,259 + 10075a8: 10a53304 addi r2,r2,-27444 + 10075ac: 213ff004 addi r4,r4,-64 + 10075b0: 11420004 addi r5,r2,2048 + 10075b4: 18800336 bltu r3,r2,10075c4 <__cxa_free_exception+0x24> + 10075b8: 1885c83a sub r2,r3,r2 + 10075bc: 1004d27a srli r2,r2,9 + 10075c0: 19400136 bltu r3,r5,10075c8 <__cxa_free_exception+0x28> + 10075c4: 100a17c1 jmpi 100a17c + 10075c8: 00ffff84 movi r3,-2 + 10075cc: 1886183a rol r3,r3,r2 + 10075d0: d0a74717 ldw r2,-25316(gp) + 10075d4: 10c4703a and r2,r2,r3 + 10075d8: d0a74715 stw r2,-25316(gp) + 10075dc: f800283a ret + +010075e0 <__cxa_allocate_exception>: + 10075e0: deffed04 addi sp,sp,-76 + 10075e4: 00804034 movhi r2,256 + 10075e8: 109a9704 addi r2,r2,27228 + 10075ec: 21001004 addi r4,r4,64 + 10075f0: 00c040b4 movhi r3,258 + 10075f4: 18c30804 addi r3,r3,3104 + 10075f8: d8800615 stw r2,24(sp) + 10075fc: d9000d15 stw r4,52(sp) + 1007600: 00804034 movhi r2,256 + 1007604: 109dbc04 addi r2,r2,30448 + 1007608: d809883a mov r4,sp + 100760c: dfc01215 stw ra,72(sp) + 1007610: d8c00715 stw r3,28(sp) + 1007614: d8800915 stw r2,36(sp) + 1007618: df001115 stw fp,68(sp) + 100761c: ddc01015 stw r23,64(sp) + 1007620: dec00815 stw sp,32(sp) + 1007624: dec00a15 stw sp,40(sp) + 1007628: 1009c1c0 call 1009c1c <_Unwind_SjLj_Register> + 100762c: d9000d17 ldw r4,52(sp) + 1007630: 100a1900 call 100a190 + 1007634: d8800e15 stw r2,56(sp) + 1007638: 1000171e bne r2,zero,1007698 <__cxa_allocate_exception+0xb8> + 100763c: d8c00d17 ldw r3,52(sp) + 1007640: 00808004 movi r2,512 + 1007644: d1e74717 ldw r7,-25316(gp) + 1007648: 10c02636 bltu r2,r3,10076e4 <__cxa_allocate_exception+0x104> + 100764c: 3807883a mov r3,r7 + 1007650: 01400044 movi r5,1 + 1007654: 1944703a and r2,r3,r5 + 1007658: 0009883a mov r4,zero + 100765c: 01800104 movi r6,4 + 1007660: 10000526 beq r2,zero,1007678 <__cxa_allocate_exception+0x98> + 1007664: 2149883a add r4,r4,r5 + 1007668: 21801e26 beq r4,r6,10076e4 <__cxa_allocate_exception+0x104> + 100766c: 1806d07a srli r3,r3,1 + 1007670: 1944703a and r2,r3,r5 + 1007674: 103ffb1e bne r2,zero,1007664 <__cxa_allocate_exception+0x84> + 1007678: 2904983a sll r2,r5,r4 + 100767c: 2008927a slli r4,r4,9 + 1007680: 00c040f4 movhi r3,259 + 1007684: 18e53304 addi r3,r3,-27444 + 1007688: 3884b03a or r2,r7,r2 + 100768c: 20c9883a add r4,r4,r3 + 1007690: d9000e15 stw r4,56(sp) + 1007694: d0a74715 stw r2,-25316(gp) + 1007698: 1009b6c0 call 1009b6c <__cxa_get_globals> + 100769c: 10c00117 ldw r3,4(r2) + 10076a0: d9000e17 ldw r4,56(sp) + 10076a4: 000b883a mov r5,zero + 10076a8: 18c00044 addi r3,r3,1 + 10076ac: 10c00115 stw r3,4(r2) + 10076b0: 01801004 movi r6,64 + 10076b4: 100abbc0 call 100abbc + 10076b8: d8800e17 ldw r2,56(sp) + 10076bc: d809883a mov r4,sp + 10076c0: 10801004 addi r2,r2,64 + 10076c4: d8800f15 stw r2,60(sp) + 10076c8: 1009c2c0 call 1009c2c <_Unwind_SjLj_Unregister> + 10076cc: d8800f17 ldw r2,60(sp) + 10076d0: dfc01217 ldw ra,72(sp) + 10076d4: df001117 ldw fp,68(sp) + 10076d8: ddc01017 ldw r23,64(sp) + 10076dc: dec01304 addi sp,sp,76 + 10076e0: f800283a ret + 10076e4: 00800044 movi r2,1 + 10076e8: d8800115 stw r2,4(sp) + 10076ec: 10070080 call 1007008 <_ZSt9terminatev> + 10076f0: d8800317 ldw r2,12(sp) + 10076f4: 00ffffc4 movi r3,-1 + 10076f8: d9000217 ldw r4,8(sp) + 10076fc: 10c00226 beq r2,r3,1007708 <__cxa_allocate_exception+0x128> + 1007700: d8c00115 stw r3,4(sp) + 1007704: 1009ee80 call 1009ee8 <_Unwind_SjLj_Resume> + 1007708: 00bfffc4 movi r2,-1 + 100770c: d8800115 stw r2,4(sp) + 1007710: 10068dc0 call 10068dc <__cxa_call_unexpected> + +01007714 <_Znwm>: + 1007714: deffee04 addi sp,sp,-72 + 1007718: 00804034 movhi r2,256 + 100771c: 109a9704 addi r2,r2,27228 + 1007720: d8800615 stw r2,24(sp) + 1007724: 00c040b4 movhi r3,258 + 1007728: 18c30c04 addi r3,r3,3120 + 100772c: 00804034 movhi r2,256 + 1007730: 109dfc04 addi r2,r2,30704 + 1007734: d9000e15 stw r4,56(sp) + 1007738: d809883a mov r4,sp + 100773c: d8800915 stw r2,36(sp) + 1007740: dfc01115 stw ra,68(sp) + 1007744: df001015 stw fp,64(sp) + 1007748: ddc00f15 stw r23,60(sp) + 100774c: d8c00715 stw r3,28(sp) + 1007750: dec00815 stw sp,32(sp) + 1007754: dec00a15 stw sp,40(sp) + 1007758: 1009c1c0 call 1009c1c <_Unwind_SjLj_Register> + 100775c: d8800e17 ldw r2,56(sp) + 1007760: 10000a1e bne r2,zero,100778c <_Znwm+0x78> + 1007764: 00800044 movi r2,1 + 1007768: d8800e15 stw r2,56(sp) + 100776c: 00000706 br 100778c <_Znwm+0x78> + 1007770: 008040b4 movhi r2,258 + 1007774: 10950104 addi r2,r2,21508 + 1007778: 10c00017 ldw r3,0(r2) + 100777c: 18000f26 beq r3,zero,10077bc <_Znwm+0xa8> + 1007780: 00800044 movi r2,1 + 1007784: d8800115 stw r2,4(sp) + 1007788: 183ee83a callr r3 + 100778c: d9000e17 ldw r4,56(sp) + 1007790: 100a1900 call 100a190 + 1007794: d8800d15 stw r2,52(sp) + 1007798: 103ff526 beq r2,zero,1007770 <_Znwm+0x5c> + 100779c: d809883a mov r4,sp + 10077a0: 1009c2c0 call 1009c2c <_Unwind_SjLj_Unregister> + 10077a4: d8800d17 ldw r2,52(sp) + 10077a8: dfc01117 ldw ra,68(sp) + 10077ac: df001017 ldw fp,64(sp) + 10077b0: ddc00f17 ldw r23,60(sp) + 10077b4: dec01204 addi sp,sp,72 + 10077b8: f800283a ret + 10077bc: 01000104 movi r4,4 + 10077c0: 10075e00 call 10075e0 <__cxa_allocate_exception> + 10077c4: 1009883a mov r4,r2 + 10077c8: 008040b4 movhi r2,258 + 10077cc: 10850d04 addi r2,r2,5172 + 10077d0: 20800015 stw r2,0(r4) + 10077d4: 00c00044 movi r3,1 + 10077d8: d8c00115 stw r3,4(sp) + 10077dc: 014040b4 movhi r5,258 + 10077e0: 29451404 addi r5,r5,5200 + 10077e4: 01804074 movhi r6,257 + 10077e8: 31a6d104 addi r6,r6,-25788 + 10077ec: 10072ac0 call 10072ac <__cxa_throw> + 10077f0: d8800317 ldw r2,12(sp) + 10077f4: 00ffffc4 movi r3,-1 + 10077f8: d9000217 ldw r4,8(sp) + 10077fc: 10c00226 beq r2,r3,1007808 <_Znwm+0xf4> + 1007800: d8c00115 stw r3,4(sp) + 1007804: 1009ee80 call 1009ee8 <_Unwind_SjLj_Resume> + 1007808: 00bfffc4 movi r2,-1 + 100780c: d8800115 stw r2,4(sp) + 1007810: 10068dc0 call 10068dc <__cxa_call_unexpected> + +01007814 <_ZSt18__throw_bad_typeidv>: + 1007814: deffff04 addi sp,sp,-4 + 1007818: 01000104 movi r4,4 + 100781c: dfc00015 stw ra,0(sp) + 1007820: 10075e00 call 10075e0 <__cxa_allocate_exception> + 1007824: 1009883a mov r4,r2 + 1007828: 008040b4 movhi r2,258 + 100782c: 10851904 addi r2,r2,5220 + 1007830: 20800015 stw r2,0(r4) + 1007834: 014040b4 movhi r5,258 + 1007838: 29452004 addi r5,r5,5248 + 100783c: 01804074 movhi r6,257 + 1007840: 31a6ea04 addi r6,r6,-25688 + 1007844: 10072ac0 call 10072ac <__cxa_throw> + +01007848 <_ZSt16__throw_bad_castv>: + 1007848: deffff04 addi sp,sp,-4 + 100784c: 01000104 movi r4,4 + 1007850: dfc00015 stw ra,0(sp) + 1007854: 10075e00 call 10075e0 <__cxa_allocate_exception> + 1007858: 1009883a mov r4,r2 + 100785c: 008040b4 movhi r2,258 + 1007860: 10852504 addi r2,r2,5268 + 1007864: 20800015 stw r2,0(r4) + 1007868: 014040b4 movhi r5,258 + 100786c: 29452b04 addi r5,r5,5292 + 1007870: 01804074 movhi r6,257 + 1007874: 31a6ff04 addi r6,r6,-25604 + 1007878: 10072ac0 call 10072ac <__cxa_throw> + +0100787c <_ZSt17__throw_bad_allocv>: + 100787c: deffff04 addi sp,sp,-4 + 1007880: 01000104 movi r4,4 + 1007884: dfc00015 stw ra,0(sp) + 1007888: 10075e00 call 10075e0 <__cxa_allocate_exception> + 100788c: 1009883a mov r4,r2 + 1007890: 008040b4 movhi r2,258 + 1007894: 10850d04 addi r2,r2,5172 + 1007898: 20800015 stw r2,0(r4) + 100789c: 014040b4 movhi r5,258 + 10078a0: 29451404 addi r5,r5,5200 + 10078a4: 01804074 movhi r6,257 + 10078a8: 31a6d104 addi r6,r6,-25788 + 10078ac: 10072ac0 call 10072ac <__cxa_throw> + +010078b0 <_ZSt21__throw_bad_exceptionv>: + 10078b0: deffff04 addi sp,sp,-4 + 10078b4: 01000104 movi r4,4 + 10078b8: dfc00015 stw ra,0(sp) + 10078bc: 10075e00 call 10075e0 <__cxa_allocate_exception> + 10078c0: 1009883a mov r4,r2 + 10078c4: 008040b4 movhi r2,258 + 10078c8: 1084f704 addi r2,r2,5084 + 10078cc: 20800015 stw r2,0(r4) + 10078d0: 014040b4 movhi r5,258 + 10078d4: 29450404 addi r5,r5,5136 + 10078d8: 01804074 movhi r6,257 + 10078dc: 31a6a804 addi r6,r6,-25952 + 10078e0: 10072ac0 call 10072ac <__cxa_throw> + +010078e4 <_ZSt19__throw_ios_failurePKc>: + 10078e4: deffeb04 addi sp,sp,-84 + 10078e8: 00804034 movhi r2,256 + 10078ec: 109a9704 addi r2,r2,27228 + 10078f0: d8800815 stw r2,32(sp) + 10078f4: 00c040b4 movhi r3,258 + 10078f8: 18c31104 addi r3,r3,3140 + 10078fc: 00804034 movhi r2,256 + 1007900: 109e7004 addi r2,r2,31168 + 1007904: d9001115 stw r4,68(sp) + 1007908: d9000204 addi r4,sp,8 + 100790c: d8800b15 stw r2,44(sp) + 1007910: dfc01415 stw ra,80(sp) + 1007914: df001315 stw fp,76(sp) + 1007918: ddc01215 stw r23,72(sp) + 100791c: d8c00915 stw r3,36(sp) + 1007920: dec00a15 stw sp,40(sp) + 1007924: dec00c15 stw sp,48(sp) + 1007928: 1009c1c0 call 1009c1c <_Unwind_SjLj_Register> + 100792c: 00800084 movi r2,2 + 1007930: d8800315 stw r2,12(sp) + 1007934: d9401117 ldw r5,68(sp) + 1007938: d9000104 addi r4,sp,4 + 100793c: d9800044 addi r6,sp,1 + 1007940: 1003e680 call 1003e68 <_ZNSsC1EPKcRKSaIcE> + 1007944: 01000204 movi r4,8 + 1007948: 10075e00 call 10075e0 <__cxa_allocate_exception> + 100794c: 1009883a mov r4,r2 + 1007950: d9400104 addi r5,sp,4 + 1007954: d8801015 stw r2,64(sp) + 1007958: 1008ae40 call 1008ae4 <_ZNSt8ios_base7failureC1ERKSs> + 100795c: d8800117 ldw r2,4(sp) + 1007960: 00c040f4 movhi r3,259 + 1007964: 18e52f04 addi r3,r3,-27460 + 1007968: 10bffd04 addi r2,r2,-12 + 100796c: d8800f15 stw r2,60(sp) + 1007970: 10c0081e bne r2,r3,1007994 <_ZSt19__throw_ios_failurePKc+0xb0> + 1007974: d9001017 ldw r4,64(sp) + 1007978: 00bfffc4 movi r2,-1 + 100797c: 014040b4 movhi r5,258 + 1007980: 2944d904 addi r5,r5,4964 + 1007984: 01804074 movhi r6,257 + 1007988: 31a27804 addi r6,r6,-30240 + 100798c: d8800315 stw r2,12(sp) + 1007990: 10072ac0 call 10072ac <__cxa_throw> + 1007994: 00800044 movi r2,1 + 1007998: d8800315 stw r2,12(sp) + 100799c: d8800f17 ldw r2,60(sp) + 10079a0: 017fffc4 movi r5,-1 + 10079a4: 11000204 addi r4,r2,8 + 10079a8: 100617c0 call 100617c <_ZN9__gnu_cxx18__exchange_and_addEPVii> + 10079ac: 00bff116 blt zero,r2,1007974 <_ZSt19__throw_ios_failurePKc+0x90> + 10079b0: d9000f17 ldw r4,60(sp) + 10079b4: d80b883a mov r5,sp + 10079b8: 1002c0c0 call 1002c0c <_ZNSs4_Rep10_M_destroyERKSaIcE> + 10079bc: 003fed06 br 1007974 <_ZSt19__throw_ios_failurePKc+0x90> + 10079c0: d8c00317 ldw r3,12(sp) + 10079c4: 00800044 movi r2,1 + 10079c8: d9000417 ldw r4,16(sp) + 10079cc: d9400517 ldw r5,20(sp) + 10079d0: 18800226 beq r3,r2,10079dc <_ZSt19__throw_ios_failurePKc+0xf8> + 10079d4: 00bfffc4 movi r2,-1 + 10079d8: 28800326 beq r5,r2,10079e8 <_ZSt19__throw_ios_failurePKc+0x104> + 10079dc: 00bfffc4 movi r2,-1 + 10079e0: d8800315 stw r2,12(sp) + 10079e4: 1009ee80 call 1009ee8 <_Unwind_SjLj_Resume> + 10079e8: 10070080 call 1007008 <_ZSt9terminatev> + +010079ec <_ZSt19__throw_logic_errorPKc>: + 10079ec: deffe704 addi sp,sp,-100 + 10079f0: 00804034 movhi r2,256 + 10079f4: 109a9704 addi r2,r2,27228 + 10079f8: d8800815 stw r2,32(sp) + 10079fc: 00c040b4 movhi r3,258 + 1007a00: 18c31604 addi r3,r3,3160 + 1007a04: 00804034 movhi r2,256 + 1007a08: 109eb604 addi r2,r2,31448 + 1007a0c: d9001315 stw r4,76(sp) + 1007a10: d9000204 addi r4,sp,8 + 1007a14: d8800b15 stw r2,44(sp) + 1007a18: dfc01815 stw ra,96(sp) + 1007a1c: df001715 stw fp,92(sp) + 1007a20: ddc01615 stw r23,88(sp) + 1007a24: d8c00915 stw r3,36(sp) + 1007a28: dec00a15 stw sp,40(sp) + 1007a2c: dec00c15 stw sp,48(sp) + 1007a30: 1009c1c0 call 1009c1c <_Unwind_SjLj_Register> + 1007a34: 00800104 movi r2,4 + 1007a38: d8800315 stw r2,12(sp) + 1007a3c: d885883a add r2,sp,r2 + 1007a40: d8801415 stw r2,80(sp) + 1007a44: d9401317 ldw r5,76(sp) + 1007a48: 1009883a mov r4,r2 + 1007a4c: d9800084 addi r6,sp,2 + 1007a50: 1003e680 call 1003e68 <_ZNSsC1EPKcRKSaIcE> + 1007a54: 01000204 movi r4,8 + 1007a58: 10075e00 call 10075e0 <__cxa_allocate_exception> + 1007a5c: d8801215 stw r2,72(sp) + 1007a60: 008000c4 movi r2,3 + 1007a64: d8800315 stw r2,12(sp) + 1007a68: d9401417 ldw r5,80(sp) + 1007a6c: d9001217 ldw r4,72(sp) + 1007a70: 10091700 call 1009170 <_ZNSt11logic_errorC1ERKSs> + 1007a74: d8800117 ldw r2,4(sp) + 1007a78: 00c040f4 movhi r3,259 + 1007a7c: 18e52f04 addi r3,r3,-27460 + 1007a80: 10bffd04 addi r2,r2,-12 + 1007a84: d8800f15 stw r2,60(sp) + 1007a88: 10c0081e bne r2,r3,1007aac <_ZSt19__throw_logic_errorPKc+0xc0> + 1007a8c: d9001217 ldw r4,72(sp) + 1007a90: 00bfffc4 movi r2,-1 + 1007a94: 014040b4 movhi r5,258 + 1007a98: 2944f204 addi r5,r5,5064 + 1007a9c: 01804074 movhi r6,257 + 1007aa0: 31a3a704 addi r6,r6,-29028 + 1007aa4: d8800315 stw r2,12(sp) + 1007aa8: 10072ac0 call 10072ac <__cxa_throw> + 1007aac: 00800044 movi r2,1 + 1007ab0: d8800315 stw r2,12(sp) + 1007ab4: d8800f17 ldw r2,60(sp) + 1007ab8: 017fffc4 movi r5,-1 + 1007abc: 11000204 addi r4,r2,8 + 1007ac0: 100617c0 call 100617c <_ZN9__gnu_cxx18__exchange_and_addEPVii> + 1007ac4: 00bff116 blt zero,r2,1007a8c <_ZSt19__throw_logic_errorPKc+0xa0> + 1007ac8: d9000f17 ldw r4,60(sp) + 1007acc: d80b883a mov r5,sp + 1007ad0: 1002c0c0 call 1002c0c <_ZNSs4_Rep10_M_destroyERKSaIcE> + 1007ad4: 003fed06 br 1007a8c <_ZSt19__throw_logic_errorPKc+0xa0> + 1007ad8: d8800417 ldw r2,16(sp) + 1007adc: d8c00317 ldw r3,12(sp) + 1007ae0: d9000517 ldw r4,20(sp) + 1007ae4: d8801515 stw r2,84(sp) + 1007ae8: 00800044 movi r2,1 + 1007aec: 18800426 beq r3,r2,1007b00 <_ZSt19__throw_logic_errorPKc+0x114> + 1007af0: 00800084 movi r2,2 + 1007af4: 18800826 beq r3,r2,1007b18 <_ZSt19__throw_logic_errorPKc+0x12c> + 1007af8: 008000c4 movi r2,3 + 1007afc: 18800226 beq r3,r2,1007b08 <_ZSt19__throw_logic_errorPKc+0x11c> + 1007b00: 00bfffc4 movi r2,-1 + 1007b04: 20801126 beq r4,r2,1007b4c <_ZSt19__throw_logic_errorPKc+0x160> + 1007b08: d9001517 ldw r4,84(sp) + 1007b0c: 00bfffc4 movi r2,-1 + 1007b10: d8800315 stw r2,12(sp) + 1007b14: 1009ee80 call 1009ee8 <_Unwind_SjLj_Resume> + 1007b18: d9001217 ldw r4,72(sp) + 1007b1c: 10075a00 call 10075a0 <__cxa_free_exception> + 1007b20: d8801517 ldw r2,84(sp) + 1007b24: 00c040f4 movhi r3,259 + 1007b28: 18e52f04 addi r3,r3,-27460 + 1007b2c: d8801115 stw r2,68(sp) + 1007b30: d8800117 ldw r2,4(sp) + 1007b34: 10bffd04 addi r2,r2,-12 + 1007b38: d8801015 stw r2,64(sp) + 1007b3c: 10c0041e bne r2,r3,1007b50 <_ZSt19__throw_logic_errorPKc+0x164> + 1007b40: d8801117 ldw r2,68(sp) + 1007b44: d8801515 stw r2,84(sp) + 1007b48: 003fef06 br 1007b08 <_ZSt19__throw_logic_errorPKc+0x11c> + 1007b4c: 10070080 call 1007008 <_ZSt9terminatev> + 1007b50: 00800084 movi r2,2 + 1007b54: d8800315 stw r2,12(sp) + 1007b58: d8801017 ldw r2,64(sp) + 1007b5c: 017fffc4 movi r5,-1 + 1007b60: 11000204 addi r4,r2,8 + 1007b64: 100617c0 call 100617c <_ZN9__gnu_cxx18__exchange_and_addEPVii> + 1007b68: 00bff516 blt zero,r2,1007b40 <_ZSt19__throw_logic_errorPKc+0x154> + 1007b6c: d9001017 ldw r4,64(sp) + 1007b70: d9400044 addi r5,sp,1 + 1007b74: 1002c0c0 call 1002c0c <_ZNSs4_Rep10_M_destroyERKSaIcE> + 1007b78: 003ff106 br 1007b40 <_ZSt19__throw_logic_errorPKc+0x154> + +01007b7c <_ZSt23__throw_underflow_errorPKc>: + 1007b7c: deffe704 addi sp,sp,-100 + 1007b80: 00804034 movhi r2,256 + 1007b84: 109a9704 addi r2,r2,27228 + 1007b88: d8800815 stw r2,32(sp) + 1007b8c: 00c040b4 movhi r3,258 + 1007b90: 18c31c04 addi r3,r3,3184 + 1007b94: 00804034 movhi r2,256 + 1007b98: 109f1a04 addi r2,r2,31848 + 1007b9c: d9001315 stw r4,76(sp) + 1007ba0: d9000204 addi r4,sp,8 + 1007ba4: d8800b15 stw r2,44(sp) + 1007ba8: dfc01815 stw ra,96(sp) + 1007bac: df001715 stw fp,92(sp) + 1007bb0: ddc01615 stw r23,88(sp) + 1007bb4: d8c00915 stw r3,36(sp) + 1007bb8: dec00a15 stw sp,40(sp) + 1007bbc: dec00c15 stw sp,48(sp) + 1007bc0: 1009c1c0 call 1009c1c <_Unwind_SjLj_Register> + 1007bc4: 00800104 movi r2,4 + 1007bc8: d8800315 stw r2,12(sp) + 1007bcc: d885883a add r2,sp,r2 + 1007bd0: d8801415 stw r2,80(sp) + 1007bd4: d9401317 ldw r5,76(sp) + 1007bd8: 1009883a mov r4,r2 + 1007bdc: d9800084 addi r6,sp,2 + 1007be0: 1003e680 call 1003e68 <_ZNSsC1EPKcRKSaIcE> + 1007be4: 01000204 movi r4,8 + 1007be8: 10075e00 call 10075e0 <__cxa_allocate_exception> + 1007bec: d8801215 stw r2,72(sp) + 1007bf0: 008000c4 movi r2,3 + 1007bf4: d8800315 stw r2,12(sp) + 1007bf8: d9401417 ldw r5,80(sp) + 1007bfc: d9001217 ldw r4,72(sp) + 1007c00: 10090500 call 1009050 <_ZNSt15underflow_errorC1ERKSs> + 1007c04: d8800117 ldw r2,4(sp) + 1007c08: 00c040f4 movhi r3,259 + 1007c0c: 18e52f04 addi r3,r3,-27460 + 1007c10: 10bffd04 addi r2,r2,-12 + 1007c14: d8800f15 stw r2,60(sp) + 1007c18: 10c0081e bne r2,r3,1007c3c <_ZSt23__throw_underflow_errorPKc+0xc0> + 1007c1c: d9001217 ldw r4,72(sp) + 1007c20: 00bfffc4 movi r2,-1 + 1007c24: 014040b4 movhi r5,258 + 1007c28: 29447304 addi r5,r5,4556 + 1007c2c: 01804074 movhi r6,257 + 1007c30: 31a20c04 addi r6,r6,-30672 + 1007c34: d8800315 stw r2,12(sp) + 1007c38: 10072ac0 call 10072ac <__cxa_throw> + 1007c3c: 00800044 movi r2,1 + 1007c40: d8800315 stw r2,12(sp) + 1007c44: d8800f17 ldw r2,60(sp) + 1007c48: 017fffc4 movi r5,-1 + 1007c4c: 11000204 addi r4,r2,8 + 1007c50: 100617c0 call 100617c <_ZN9__gnu_cxx18__exchange_and_addEPVii> + 1007c54: 00bff116 blt zero,r2,1007c1c <_ZSt23__throw_underflow_errorPKc+0xa0> + 1007c58: d9000f17 ldw r4,60(sp) + 1007c5c: d80b883a mov r5,sp + 1007c60: 1002c0c0 call 1002c0c <_ZNSs4_Rep10_M_destroyERKSaIcE> + 1007c64: 003fed06 br 1007c1c <_ZSt23__throw_underflow_errorPKc+0xa0> + 1007c68: d8800417 ldw r2,16(sp) + 1007c6c: d8c00317 ldw r3,12(sp) + 1007c70: d9000517 ldw r4,20(sp) + 1007c74: d8801515 stw r2,84(sp) + 1007c78: 00800044 movi r2,1 + 1007c7c: 18800426 beq r3,r2,1007c90 <_ZSt23__throw_underflow_errorPKc+0x114> + 1007c80: 00800084 movi r2,2 + 1007c84: 18800826 beq r3,r2,1007ca8 <_ZSt23__throw_underflow_errorPKc+0x12c> + 1007c88: 008000c4 movi r2,3 + 1007c8c: 18800226 beq r3,r2,1007c98 <_ZSt23__throw_underflow_errorPKc+0x11c> + 1007c90: 00bfffc4 movi r2,-1 + 1007c94: 20801126 beq r4,r2,1007cdc <_ZSt23__throw_underflow_errorPKc+0x160> + 1007c98: d9001517 ldw r4,84(sp) + 1007c9c: 00bfffc4 movi r2,-1 + 1007ca0: d8800315 stw r2,12(sp) + 1007ca4: 1009ee80 call 1009ee8 <_Unwind_SjLj_Resume> + 1007ca8: d9001217 ldw r4,72(sp) + 1007cac: 10075a00 call 10075a0 <__cxa_free_exception> + 1007cb0: d8801517 ldw r2,84(sp) + 1007cb4: 00c040f4 movhi r3,259 + 1007cb8: 18e52f04 addi r3,r3,-27460 + 1007cbc: d8801115 stw r2,68(sp) + 1007cc0: d8800117 ldw r2,4(sp) + 1007cc4: 10bffd04 addi r2,r2,-12 + 1007cc8: d8801015 stw r2,64(sp) + 1007ccc: 10c0041e bne r2,r3,1007ce0 <_ZSt23__throw_underflow_errorPKc+0x164> + 1007cd0: d8801117 ldw r2,68(sp) + 1007cd4: d8801515 stw r2,84(sp) + 1007cd8: 003fef06 br 1007c98 <_ZSt23__throw_underflow_errorPKc+0x11c> + 1007cdc: 10070080 call 1007008 <_ZSt9terminatev> + 1007ce0: 00800084 movi r2,2 + 1007ce4: d8800315 stw r2,12(sp) + 1007ce8: d8801017 ldw r2,64(sp) + 1007cec: 017fffc4 movi r5,-1 + 1007cf0: 11000204 addi r4,r2,8 + 1007cf4: 100617c0 call 100617c <_ZN9__gnu_cxx18__exchange_and_addEPVii> + 1007cf8: 00bff516 blt zero,r2,1007cd0 <_ZSt23__throw_underflow_errorPKc+0x154> + 1007cfc: d9001017 ldw r4,64(sp) + 1007d00: d9400044 addi r5,sp,1 + 1007d04: 1002c0c0 call 1002c0c <_ZNSs4_Rep10_M_destroyERKSaIcE> + 1007d08: 003ff106 br 1007cd0 <_ZSt23__throw_underflow_errorPKc+0x154> + +01007d0c <_ZSt22__throw_overflow_errorPKc>: + 1007d0c: deffe704 addi sp,sp,-100 + 1007d10: 00804034 movhi r2,256 + 1007d14: 109a9704 addi r2,r2,27228 + 1007d18: d8800815 stw r2,32(sp) + 1007d1c: 00c040b4 movhi r3,258 + 1007d20: 18c32204 addi r3,r3,3208 + 1007d24: 00804034 movhi r2,256 + 1007d28: 109f7e04 addi r2,r2,32248 + 1007d2c: d9001315 stw r4,76(sp) + 1007d30: d9000204 addi r4,sp,8 + 1007d34: d8800b15 stw r2,44(sp) + 1007d38: dfc01815 stw ra,96(sp) + 1007d3c: df001715 stw fp,92(sp) + 1007d40: ddc01615 stw r23,88(sp) + 1007d44: d8c00915 stw r3,36(sp) + 1007d48: dec00a15 stw sp,40(sp) + 1007d4c: dec00c15 stw sp,48(sp) + 1007d50: 1009c1c0 call 1009c1c <_Unwind_SjLj_Register> + 1007d54: 00800104 movi r2,4 + 1007d58: d8800315 stw r2,12(sp) + 1007d5c: d885883a add r2,sp,r2 + 1007d60: d8801415 stw r2,80(sp) + 1007d64: d9401317 ldw r5,76(sp) + 1007d68: 1009883a mov r4,r2 + 1007d6c: d9800084 addi r6,sp,2 + 1007d70: 1003e680 call 1003e68 <_ZNSsC1EPKcRKSaIcE> + 1007d74: 01000204 movi r4,8 + 1007d78: 10075e00 call 10075e0 <__cxa_allocate_exception> + 1007d7c: d8801215 stw r2,72(sp) + 1007d80: 008000c4 movi r2,3 + 1007d84: d8800315 stw r2,12(sp) + 1007d88: d9401417 ldw r5,80(sp) + 1007d8c: d9001217 ldw r4,72(sp) + 1007d90: 10090b00 call 10090b0 <_ZNSt14overflow_errorC1ERKSs> + 1007d94: d8800117 ldw r2,4(sp) + 1007d98: 00c040f4 movhi r3,259 + 1007d9c: 18e52f04 addi r3,r3,-27460 + 1007da0: 10bffd04 addi r2,r2,-12 + 1007da4: d8800f15 stw r2,60(sp) + 1007da8: 10c0081e bne r2,r3,1007dcc <_ZSt22__throw_overflow_errorPKc+0xc0> + 1007dac: d9001217 ldw r4,72(sp) + 1007db0: 00bfffc4 movi r2,-1 + 1007db4: 014040b4 movhi r5,258 + 1007db8: 29448004 addi r5,r5,4608 + 1007dbc: 01804074 movhi r6,257 + 1007dc0: 31a21d04 addi r6,r6,-30604 + 1007dc4: d8800315 stw r2,12(sp) + 1007dc8: 10072ac0 call 10072ac <__cxa_throw> + 1007dcc: 00800044 movi r2,1 + 1007dd0: d8800315 stw r2,12(sp) + 1007dd4: d8800f17 ldw r2,60(sp) + 1007dd8: 017fffc4 movi r5,-1 + 1007ddc: 11000204 addi r4,r2,8 + 1007de0: 100617c0 call 100617c <_ZN9__gnu_cxx18__exchange_and_addEPVii> + 1007de4: 00bff116 blt zero,r2,1007dac <_ZSt22__throw_overflow_errorPKc+0xa0> + 1007de8: d9000f17 ldw r4,60(sp) + 1007dec: d80b883a mov r5,sp + 1007df0: 1002c0c0 call 1002c0c <_ZNSs4_Rep10_M_destroyERKSaIcE> + 1007df4: 003fed06 br 1007dac <_ZSt22__throw_overflow_errorPKc+0xa0> + 1007df8: d8800417 ldw r2,16(sp) + 1007dfc: d8c00317 ldw r3,12(sp) + 1007e00: d9000517 ldw r4,20(sp) + 1007e04: d8801515 stw r2,84(sp) + 1007e08: 00800044 movi r2,1 + 1007e0c: 18800426 beq r3,r2,1007e20 <_ZSt22__throw_overflow_errorPKc+0x114> + 1007e10: 00800084 movi r2,2 + 1007e14: 18800826 beq r3,r2,1007e38 <_ZSt22__throw_overflow_errorPKc+0x12c> + 1007e18: 008000c4 movi r2,3 + 1007e1c: 18800226 beq r3,r2,1007e28 <_ZSt22__throw_overflow_errorPKc+0x11c> + 1007e20: 00bfffc4 movi r2,-1 + 1007e24: 20801126 beq r4,r2,1007e6c <_ZSt22__throw_overflow_errorPKc+0x160> + 1007e28: d9001517 ldw r4,84(sp) + 1007e2c: 00bfffc4 movi r2,-1 + 1007e30: d8800315 stw r2,12(sp) + 1007e34: 1009ee80 call 1009ee8 <_Unwind_SjLj_Resume> + 1007e38: d9001217 ldw r4,72(sp) + 1007e3c: 10075a00 call 10075a0 <__cxa_free_exception> + 1007e40: d8801517 ldw r2,84(sp) + 1007e44: 00c040f4 movhi r3,259 + 1007e48: 18e52f04 addi r3,r3,-27460 + 1007e4c: d8801115 stw r2,68(sp) + 1007e50: d8800117 ldw r2,4(sp) + 1007e54: 10bffd04 addi r2,r2,-12 + 1007e58: d8801015 stw r2,64(sp) + 1007e5c: 10c0041e bne r2,r3,1007e70 <_ZSt22__throw_overflow_errorPKc+0x164> + 1007e60: d8801117 ldw r2,68(sp) + 1007e64: d8801515 stw r2,84(sp) + 1007e68: 003fef06 br 1007e28 <_ZSt22__throw_overflow_errorPKc+0x11c> + 1007e6c: 10070080 call 1007008 <_ZSt9terminatev> + 1007e70: 00800084 movi r2,2 + 1007e74: d8800315 stw r2,12(sp) + 1007e78: d8801017 ldw r2,64(sp) + 1007e7c: 017fffc4 movi r5,-1 + 1007e80: 11000204 addi r4,r2,8 + 1007e84: 100617c0 call 100617c <_ZN9__gnu_cxx18__exchange_and_addEPVii> + 1007e88: 00bff516 blt zero,r2,1007e60 <_ZSt22__throw_overflow_errorPKc+0x154> + 1007e8c: d9001017 ldw r4,64(sp) + 1007e90: d9400044 addi r5,sp,1 + 1007e94: 1002c0c0 call 1002c0c <_ZNSs4_Rep10_M_destroyERKSaIcE> + 1007e98: 003ff106 br 1007e60 <_ZSt22__throw_overflow_errorPKc+0x154> + +01007e9c <_ZSt24__throw_invalid_argumentPKc>: + 1007e9c: deffe704 addi sp,sp,-100 + 1007ea0: 00804034 movhi r2,256 + 1007ea4: 109a9704 addi r2,r2,27228 + 1007ea8: d8800815 stw r2,32(sp) + 1007eac: 00c040b4 movhi r3,258 + 1007eb0: 18c32804 addi r3,r3,3232 + 1007eb4: 00804034 movhi r2,256 + 1007eb8: 109fe204 addi r2,r2,32648 + 1007ebc: d9001315 stw r4,76(sp) + 1007ec0: d9000204 addi r4,sp,8 + 1007ec4: d8800b15 stw r2,44(sp) + 1007ec8: dfc01815 stw ra,96(sp) + 1007ecc: df001715 stw fp,92(sp) + 1007ed0: ddc01615 stw r23,88(sp) + 1007ed4: d8c00915 stw r3,36(sp) + 1007ed8: dec00a15 stw sp,40(sp) + 1007edc: dec00c15 stw sp,48(sp) + 1007ee0: 1009c1c0 call 1009c1c <_Unwind_SjLj_Register> + 1007ee4: 00800104 movi r2,4 + 1007ee8: d8800315 stw r2,12(sp) + 1007eec: d885883a add r2,sp,r2 + 1007ef0: d8801415 stw r2,80(sp) + 1007ef4: d9401317 ldw r5,76(sp) + 1007ef8: 1009883a mov r4,r2 + 1007efc: d9800084 addi r6,sp,2 + 1007f00: 1003e680 call 1003e68 <_ZNSsC1EPKcRKSaIcE> + 1007f04: 01000204 movi r4,8 + 1007f08: 10075e00 call 10075e0 <__cxa_allocate_exception> + 1007f0c: d8801215 stw r2,72(sp) + 1007f10: 008000c4 movi r2,3 + 1007f14: d8800315 stw r2,12(sp) + 1007f18: d9401417 ldw r5,80(sp) + 1007f1c: d9001217 ldw r4,72(sp) + 1007f20: 10093900 call 1009390 <_ZNSt16invalid_argumentC1ERKSs> + 1007f24: d8800117 ldw r2,4(sp) + 1007f28: 00c040f4 movhi r3,259 + 1007f2c: 18e52f04 addi r3,r3,-27460 + 1007f30: 10bffd04 addi r2,r2,-12 + 1007f34: d8800f15 stw r2,60(sp) + 1007f38: 10c0081e bne r2,r3,1007f5c <_ZSt24__throw_invalid_argumentPKc+0xc0> + 1007f3c: d9001217 ldw r4,72(sp) + 1007f40: 00bfffc4 movi r2,-1 + 1007f44: 014040b4 movhi r5,258 + 1007f48: 2944b304 addi r5,r5,4812 + 1007f4c: 01804074 movhi r6,257 + 1007f50: 31a26104 addi r6,r6,-30332 + 1007f54: d8800315 stw r2,12(sp) + 1007f58: 10072ac0 call 10072ac <__cxa_throw> + 1007f5c: 00800044 movi r2,1 + 1007f60: d8800315 stw r2,12(sp) + 1007f64: d8800f17 ldw r2,60(sp) + 1007f68: 017fffc4 movi r5,-1 + 1007f6c: 11000204 addi r4,r2,8 + 1007f70: 100617c0 call 100617c <_ZN9__gnu_cxx18__exchange_and_addEPVii> + 1007f74: 00bff116 blt zero,r2,1007f3c <_ZSt24__throw_invalid_argumentPKc+0xa0> + 1007f78: d9000f17 ldw r4,60(sp) + 1007f7c: d80b883a mov r5,sp + 1007f80: 1002c0c0 call 1002c0c <_ZNSs4_Rep10_M_destroyERKSaIcE> + 1007f84: 003fed06 br 1007f3c <_ZSt24__throw_invalid_argumentPKc+0xa0> + 1007f88: d8800417 ldw r2,16(sp) + 1007f8c: d8c00317 ldw r3,12(sp) + 1007f90: d9000517 ldw r4,20(sp) + 1007f94: d8801515 stw r2,84(sp) + 1007f98: 00800044 movi r2,1 + 1007f9c: 18800426 beq r3,r2,1007fb0 <_ZSt24__throw_invalid_argumentPKc+0x114> + 1007fa0: 00800084 movi r2,2 + 1007fa4: 18800826 beq r3,r2,1007fc8 <_ZSt24__throw_invalid_argumentPKc+0x12c> + 1007fa8: 008000c4 movi r2,3 + 1007fac: 18800226 beq r3,r2,1007fb8 <_ZSt24__throw_invalid_argumentPKc+0x11c> + 1007fb0: 00bfffc4 movi r2,-1 + 1007fb4: 20801126 beq r4,r2,1007ffc <_ZSt24__throw_invalid_argumentPKc+0x160> + 1007fb8: d9001517 ldw r4,84(sp) + 1007fbc: 00bfffc4 movi r2,-1 + 1007fc0: d8800315 stw r2,12(sp) + 1007fc4: 1009ee80 call 1009ee8 <_Unwind_SjLj_Resume> + 1007fc8: d9001217 ldw r4,72(sp) + 1007fcc: 10075a00 call 10075a0 <__cxa_free_exception> + 1007fd0: d8801517 ldw r2,84(sp) + 1007fd4: 00c040f4 movhi r3,259 + 1007fd8: 18e52f04 addi r3,r3,-27460 + 1007fdc: d8801115 stw r2,68(sp) + 1007fe0: d8800117 ldw r2,4(sp) + 1007fe4: 10bffd04 addi r2,r2,-12 + 1007fe8: d8801015 stw r2,64(sp) + 1007fec: 10c0041e bne r2,r3,1008000 <_ZSt24__throw_invalid_argumentPKc+0x164> + 1007ff0: d8801117 ldw r2,68(sp) + 1007ff4: d8801515 stw r2,84(sp) + 1007ff8: 003fef06 br 1007fb8 <_ZSt24__throw_invalid_argumentPKc+0x11c> + 1007ffc: 10070080 call 1007008 <_ZSt9terminatev> + 1008000: 00800084 movi r2,2 + 1008004: d8800315 stw r2,12(sp) + 1008008: d8801017 ldw r2,64(sp) + 100800c: 017fffc4 movi r5,-1 + 1008010: 11000204 addi r4,r2,8 + 1008014: 100617c0 call 100617c <_ZN9__gnu_cxx18__exchange_and_addEPVii> + 1008018: 00bff516 blt zero,r2,1007ff0 <_ZSt24__throw_invalid_argumentPKc+0x154> + 100801c: d9001017 ldw r4,64(sp) + 1008020: d9400044 addi r5,sp,1 + 1008024: 1002c0c0 call 1002c0c <_ZNSs4_Rep10_M_destroyERKSaIcE> + 1008028: 003ff106 br 1007ff0 <_ZSt24__throw_invalid_argumentPKc+0x154> + +0100802c <_ZSt20__throw_domain_errorPKc>: + 100802c: deffe704 addi sp,sp,-100 + 1008030: 00804034 movhi r2,256 + 1008034: 109a9704 addi r2,r2,27228 + 1008038: d8800815 stw r2,32(sp) + 100803c: 00c040b4 movhi r3,258 + 1008040: 18c32e04 addi r3,r3,3256 + 1008044: 00804074 movhi r2,257 + 1008048: 10a04604 addi r2,r2,-32488 + 100804c: d9001315 stw r4,76(sp) + 1008050: d9000204 addi r4,sp,8 + 1008054: d8800b15 stw r2,44(sp) + 1008058: dfc01815 stw ra,96(sp) + 100805c: df001715 stw fp,92(sp) + 1008060: ddc01615 stw r23,88(sp) + 1008064: d8c00915 stw r3,36(sp) + 1008068: dec00a15 stw sp,40(sp) + 100806c: dec00c15 stw sp,48(sp) + 1008070: 1009c1c0 call 1009c1c <_Unwind_SjLj_Register> + 1008074: 00800104 movi r2,4 + 1008078: d8800315 stw r2,12(sp) + 100807c: d885883a add r2,sp,r2 + 1008080: d8801415 stw r2,80(sp) + 1008084: d9401317 ldw r5,76(sp) + 1008088: 1009883a mov r4,r2 + 100808c: d9800084 addi r6,sp,2 + 1008090: 1003e680 call 1003e68 <_ZNSsC1EPKcRKSaIcE> + 1008094: 01000204 movi r4,8 + 1008098: 10075e00 call 10075e0 <__cxa_allocate_exception> + 100809c: d8801215 stw r2,72(sp) + 10080a0: 008000c4 movi r2,3 + 10080a4: d8800315 stw r2,12(sp) + 10080a8: d9401417 ldw r5,80(sp) + 10080ac: d9001217 ldw r4,72(sp) + 10080b0: 10093f00 call 10093f0 <_ZNSt12domain_errorC1ERKSs> + 10080b4: d8800117 ldw r2,4(sp) + 10080b8: 00c040f4 movhi r3,259 + 10080bc: 18e52f04 addi r3,r3,-27460 + 10080c0: 10bffd04 addi r2,r2,-12 + 10080c4: d8800f15 stw r2,60(sp) + 10080c8: 10c0081e bne r2,r3,10080ec <_ZSt20__throw_domain_errorPKc+0xc0> + 10080cc: d9001217 ldw r4,72(sp) + 10080d0: 00bfffc4 movi r2,-1 + 10080d4: 014040b4 movhi r5,258 + 10080d8: 2944c104 addi r5,r5,4868 + 10080dc: 01804074 movhi r6,257 + 10080e0: 31a27204 addi r6,r6,-30264 + 10080e4: d8800315 stw r2,12(sp) + 10080e8: 10072ac0 call 10072ac <__cxa_throw> + 10080ec: 00800044 movi r2,1 + 10080f0: d8800315 stw r2,12(sp) + 10080f4: d8800f17 ldw r2,60(sp) + 10080f8: 017fffc4 movi r5,-1 + 10080fc: 11000204 addi r4,r2,8 + 1008100: 100617c0 call 100617c <_ZN9__gnu_cxx18__exchange_and_addEPVii> + 1008104: 00bff116 blt zero,r2,10080cc <_ZSt20__throw_domain_errorPKc+0xa0> + 1008108: d9000f17 ldw r4,60(sp) + 100810c: d80b883a mov r5,sp + 1008110: 1002c0c0 call 1002c0c <_ZNSs4_Rep10_M_destroyERKSaIcE> + 1008114: 003fed06 br 10080cc <_ZSt20__throw_domain_errorPKc+0xa0> + 1008118: d8800417 ldw r2,16(sp) + 100811c: d8c00317 ldw r3,12(sp) + 1008120: d9000517 ldw r4,20(sp) + 1008124: d8801515 stw r2,84(sp) + 1008128: 00800044 movi r2,1 + 100812c: 18800426 beq r3,r2,1008140 <_ZSt20__throw_domain_errorPKc+0x114> + 1008130: 00800084 movi r2,2 + 1008134: 18800826 beq r3,r2,1008158 <_ZSt20__throw_domain_errorPKc+0x12c> + 1008138: 008000c4 movi r2,3 + 100813c: 18800226 beq r3,r2,1008148 <_ZSt20__throw_domain_errorPKc+0x11c> + 1008140: 00bfffc4 movi r2,-1 + 1008144: 20801126 beq r4,r2,100818c <_ZSt20__throw_domain_errorPKc+0x160> + 1008148: d9001517 ldw r4,84(sp) + 100814c: 00bfffc4 movi r2,-1 + 1008150: d8800315 stw r2,12(sp) + 1008154: 1009ee80 call 1009ee8 <_Unwind_SjLj_Resume> + 1008158: d9001217 ldw r4,72(sp) + 100815c: 10075a00 call 10075a0 <__cxa_free_exception> + 1008160: d8801517 ldw r2,84(sp) + 1008164: 00c040f4 movhi r3,259 + 1008168: 18e52f04 addi r3,r3,-27460 + 100816c: d8801115 stw r2,68(sp) + 1008170: d8800117 ldw r2,4(sp) + 1008174: 10bffd04 addi r2,r2,-12 + 1008178: d8801015 stw r2,64(sp) + 100817c: 10c0041e bne r2,r3,1008190 <_ZSt20__throw_domain_errorPKc+0x164> + 1008180: d8801117 ldw r2,68(sp) + 1008184: d8801515 stw r2,84(sp) + 1008188: 003fef06 br 1008148 <_ZSt20__throw_domain_errorPKc+0x11c> + 100818c: 10070080 call 1007008 <_ZSt9terminatev> + 1008190: 00800084 movi r2,2 + 1008194: d8800315 stw r2,12(sp) + 1008198: d8801017 ldw r2,64(sp) + 100819c: 017fffc4 movi r5,-1 + 10081a0: 11000204 addi r4,r2,8 + 10081a4: 100617c0 call 100617c <_ZN9__gnu_cxx18__exchange_and_addEPVii> + 10081a8: 00bff516 blt zero,r2,1008180 <_ZSt20__throw_domain_errorPKc+0x154> + 10081ac: d9001017 ldw r4,64(sp) + 10081b0: d9400044 addi r5,sp,1 + 10081b4: 1002c0c0 call 1002c0c <_ZNSs4_Rep10_M_destroyERKSaIcE> + 10081b8: 003ff106 br 1008180 <_ZSt20__throw_domain_errorPKc+0x154> + +010081bc <_ZSt19__throw_range_errorPKc>: + 10081bc: deffe704 addi sp,sp,-100 + 10081c0: 00804034 movhi r2,256 + 10081c4: 109a9704 addi r2,r2,27228 + 10081c8: d8800815 stw r2,32(sp) + 10081cc: 00c040b4 movhi r3,258 + 10081d0: 18c33404 addi r3,r3,3280 + 10081d4: 00804074 movhi r2,257 + 10081d8: 10a0aa04 addi r2,r2,-32088 + 10081dc: d9001315 stw r4,76(sp) + 10081e0: d9000204 addi r4,sp,8 + 10081e4: d8800b15 stw r2,44(sp) + 10081e8: dfc01815 stw ra,96(sp) + 10081ec: df001715 stw fp,92(sp) + 10081f0: ddc01615 stw r23,88(sp) + 10081f4: d8c00915 stw r3,36(sp) + 10081f8: dec00a15 stw sp,40(sp) + 10081fc: dec00c15 stw sp,48(sp) + 1008200: 1009c1c0 call 1009c1c <_Unwind_SjLj_Register> + 1008204: 00800104 movi r2,4 + 1008208: d8800315 stw r2,12(sp) + 100820c: d885883a add r2,sp,r2 + 1008210: d8801415 stw r2,80(sp) + 1008214: d9401317 ldw r5,76(sp) + 1008218: 1009883a mov r4,r2 + 100821c: d9800084 addi r6,sp,2 + 1008220: 1003e680 call 1003e68 <_ZNSsC1EPKcRKSaIcE> + 1008224: 01000204 movi r4,8 + 1008228: 10075e00 call 10075e0 <__cxa_allocate_exception> + 100822c: d8801215 stw r2,72(sp) + 1008230: 008000c4 movi r2,3 + 1008234: d8800315 stw r2,12(sp) + 1008238: d9401417 ldw r5,80(sp) + 100823c: d9001217 ldw r4,72(sp) + 1008240: 10091100 call 1009110 <_ZNSt11range_errorC1ERKSs> + 1008244: d8800117 ldw r2,4(sp) + 1008248: 00c040f4 movhi r3,259 + 100824c: 18e52f04 addi r3,r3,-27460 + 1008250: 10bffd04 addi r2,r2,-12 + 1008254: d8800f15 stw r2,60(sp) + 1008258: 10c0081e bne r2,r3,100827c <_ZSt19__throw_range_errorPKc+0xc0> + 100825c: d9001217 ldw r4,72(sp) + 1008260: 00bfffc4 movi r2,-1 + 1008264: 014040b4 movhi r5,258 + 1008268: 29448d04 addi r5,r5,4660 + 100826c: 01804074 movhi r6,257 + 1008270: 31a22e04 addi r6,r6,-30536 + 1008274: d8800315 stw r2,12(sp) + 1008278: 10072ac0 call 10072ac <__cxa_throw> + 100827c: 00800044 movi r2,1 + 1008280: d8800315 stw r2,12(sp) + 1008284: d8800f17 ldw r2,60(sp) + 1008288: 017fffc4 movi r5,-1 + 100828c: 11000204 addi r4,r2,8 + 1008290: 100617c0 call 100617c <_ZN9__gnu_cxx18__exchange_and_addEPVii> + 1008294: 00bff116 blt zero,r2,100825c <_ZSt19__throw_range_errorPKc+0xa0> + 1008298: d9000f17 ldw r4,60(sp) + 100829c: d80b883a mov r5,sp + 10082a0: 1002c0c0 call 1002c0c <_ZNSs4_Rep10_M_destroyERKSaIcE> + 10082a4: 003fed06 br 100825c <_ZSt19__throw_range_errorPKc+0xa0> + 10082a8: d8800417 ldw r2,16(sp) + 10082ac: d8c00317 ldw r3,12(sp) + 10082b0: d9000517 ldw r4,20(sp) + 10082b4: d8801515 stw r2,84(sp) + 10082b8: 00800044 movi r2,1 + 10082bc: 18800426 beq r3,r2,10082d0 <_ZSt19__throw_range_errorPKc+0x114> + 10082c0: 00800084 movi r2,2 + 10082c4: 18800826 beq r3,r2,10082e8 <_ZSt19__throw_range_errorPKc+0x12c> + 10082c8: 008000c4 movi r2,3 + 10082cc: 18800226 beq r3,r2,10082d8 <_ZSt19__throw_range_errorPKc+0x11c> + 10082d0: 00bfffc4 movi r2,-1 + 10082d4: 20801126 beq r4,r2,100831c <_ZSt19__throw_range_errorPKc+0x160> + 10082d8: d9001517 ldw r4,84(sp) + 10082dc: 00bfffc4 movi r2,-1 + 10082e0: d8800315 stw r2,12(sp) + 10082e4: 1009ee80 call 1009ee8 <_Unwind_SjLj_Resume> + 10082e8: d9001217 ldw r4,72(sp) + 10082ec: 10075a00 call 10075a0 <__cxa_free_exception> + 10082f0: d8801517 ldw r2,84(sp) + 10082f4: 00c040f4 movhi r3,259 + 10082f8: 18e52f04 addi r3,r3,-27460 + 10082fc: d8801115 stw r2,68(sp) + 1008300: d8800117 ldw r2,4(sp) + 1008304: 10bffd04 addi r2,r2,-12 + 1008308: d8801015 stw r2,64(sp) + 100830c: 10c0041e bne r2,r3,1008320 <_ZSt19__throw_range_errorPKc+0x164> + 1008310: d8801117 ldw r2,68(sp) + 1008314: d8801515 stw r2,84(sp) + 1008318: 003fef06 br 10082d8 <_ZSt19__throw_range_errorPKc+0x11c> + 100831c: 10070080 call 1007008 <_ZSt9terminatev> + 1008320: 00800084 movi r2,2 + 1008324: d8800315 stw r2,12(sp) + 1008328: d8801017 ldw r2,64(sp) + 100832c: 017fffc4 movi r5,-1 + 1008330: 11000204 addi r4,r2,8 + 1008334: 100617c0 call 100617c <_ZN9__gnu_cxx18__exchange_and_addEPVii> + 1008338: 00bff516 blt zero,r2,1008310 <_ZSt19__throw_range_errorPKc+0x154> + 100833c: d9001017 ldw r4,64(sp) + 1008340: d9400044 addi r5,sp,1 + 1008344: 1002c0c0 call 1002c0c <_ZNSs4_Rep10_M_destroyERKSaIcE> + 1008348: 003ff106 br 1008310 <_ZSt19__throw_range_errorPKc+0x154> + +0100834c <_ZSt21__throw_runtime_errorPKc>: + 100834c: deffe704 addi sp,sp,-100 + 1008350: 00804034 movhi r2,256 + 1008354: 109a9704 addi r2,r2,27228 + 1008358: d8800815 stw r2,32(sp) + 100835c: 00c040b4 movhi r3,258 + 1008360: 18c33a04 addi r3,r3,3304 + 1008364: 00804074 movhi r2,257 + 1008368: 10a10e04 addi r2,r2,-31688 + 100836c: d9001315 stw r4,76(sp) + 1008370: d9000204 addi r4,sp,8 + 1008374: d8800b15 stw r2,44(sp) + 1008378: dfc01815 stw ra,96(sp) + 100837c: df001715 stw fp,92(sp) + 1008380: ddc01615 stw r23,88(sp) + 1008384: d8c00915 stw r3,36(sp) + 1008388: dec00a15 stw sp,40(sp) + 100838c: dec00c15 stw sp,48(sp) + 1008390: 1009c1c0 call 1009c1c <_Unwind_SjLj_Register> + 1008394: 00800104 movi r2,4 + 1008398: d8800315 stw r2,12(sp) + 100839c: d885883a add r2,sp,r2 + 10083a0: d8801415 stw r2,80(sp) + 10083a4: d9401317 ldw r5,76(sp) + 10083a8: 1009883a mov r4,r2 + 10083ac: d9800084 addi r6,sp,2 + 10083b0: 1003e680 call 1003e68 <_ZNSsC1EPKcRKSaIcE> + 10083b4: 01000204 movi r4,8 + 10083b8: 10075e00 call 10075e0 <__cxa_allocate_exception> + 10083bc: d8801215 stw r2,72(sp) + 10083c0: 008000c4 movi r2,3 + 10083c4: d8800315 stw r2,12(sp) + 10083c8: d9401417 ldw r5,80(sp) + 10083cc: d9001217 ldw r4,72(sp) + 10083d0: 10094580 call 1009458 <_ZNSt13runtime_errorC1ERKSs> + 10083d4: d8800117 ldw r2,4(sp) + 10083d8: 00c040f4 movhi r3,259 + 10083dc: 18e52f04 addi r3,r3,-27460 + 10083e0: 10bffd04 addi r2,r2,-12 + 10083e4: d8800f15 stw r2,60(sp) + 10083e8: 10c0081e bne r2,r3,100840c <_ZSt21__throw_runtime_errorPKc+0xc0> + 10083ec: d9001217 ldw r4,72(sp) + 10083f0: 00bfffc4 movi r2,-1 + 10083f4: 014040b4 movhi r5,258 + 10083f8: 2944eb04 addi r5,r5,5036 + 10083fc: 01804074 movhi r6,257 + 1008400: 31a54204 addi r6,r6,-27384 + 1008404: d8800315 stw r2,12(sp) + 1008408: 10072ac0 call 10072ac <__cxa_throw> + 100840c: 00800044 movi r2,1 + 1008410: d8800315 stw r2,12(sp) + 1008414: d8800f17 ldw r2,60(sp) + 1008418: 017fffc4 movi r5,-1 + 100841c: 11000204 addi r4,r2,8 + 1008420: 100617c0 call 100617c <_ZN9__gnu_cxx18__exchange_and_addEPVii> + 1008424: 00bff116 blt zero,r2,10083ec <_ZSt21__throw_runtime_errorPKc+0xa0> + 1008428: d9000f17 ldw r4,60(sp) + 100842c: d80b883a mov r5,sp + 1008430: 1002c0c0 call 1002c0c <_ZNSs4_Rep10_M_destroyERKSaIcE> + 1008434: 003fed06 br 10083ec <_ZSt21__throw_runtime_errorPKc+0xa0> + 1008438: d8800417 ldw r2,16(sp) + 100843c: d8c00317 ldw r3,12(sp) + 1008440: d9000517 ldw r4,20(sp) + 1008444: d8801515 stw r2,84(sp) + 1008448: 00800044 movi r2,1 + 100844c: 18800426 beq r3,r2,1008460 <_ZSt21__throw_runtime_errorPKc+0x114> + 1008450: 00800084 movi r2,2 + 1008454: 18800826 beq r3,r2,1008478 <_ZSt21__throw_runtime_errorPKc+0x12c> + 1008458: 008000c4 movi r2,3 + 100845c: 18800226 beq r3,r2,1008468 <_ZSt21__throw_runtime_errorPKc+0x11c> + 1008460: 00bfffc4 movi r2,-1 + 1008464: 20801126 beq r4,r2,10084ac <_ZSt21__throw_runtime_errorPKc+0x160> + 1008468: d9001517 ldw r4,84(sp) + 100846c: 00bfffc4 movi r2,-1 + 1008470: d8800315 stw r2,12(sp) + 1008474: 1009ee80 call 1009ee8 <_Unwind_SjLj_Resume> + 1008478: d9001217 ldw r4,72(sp) + 100847c: 10075a00 call 10075a0 <__cxa_free_exception> + 1008480: d8801517 ldw r2,84(sp) + 1008484: 00c040f4 movhi r3,259 + 1008488: 18e52f04 addi r3,r3,-27460 + 100848c: d8801115 stw r2,68(sp) + 1008490: d8800117 ldw r2,4(sp) + 1008494: 10bffd04 addi r2,r2,-12 + 1008498: d8801015 stw r2,64(sp) + 100849c: 10c0041e bne r2,r3,10084b0 <_ZSt21__throw_runtime_errorPKc+0x164> + 10084a0: d8801117 ldw r2,68(sp) + 10084a4: d8801515 stw r2,84(sp) + 10084a8: 003fef06 br 1008468 <_ZSt21__throw_runtime_errorPKc+0x11c> + 10084ac: 10070080 call 1007008 <_ZSt9terminatev> + 10084b0: 00800084 movi r2,2 + 10084b4: d8800315 stw r2,12(sp) + 10084b8: d8801017 ldw r2,64(sp) + 10084bc: 017fffc4 movi r5,-1 + 10084c0: 11000204 addi r4,r2,8 + 10084c4: 100617c0 call 100617c <_ZN9__gnu_cxx18__exchange_and_addEPVii> + 10084c8: 00bff516 blt zero,r2,10084a0 <_ZSt21__throw_runtime_errorPKc+0x154> + 10084cc: d9001017 ldw r4,64(sp) + 10084d0: d9400044 addi r5,sp,1 + 10084d4: 1002c0c0 call 1002c0c <_ZNSs4_Rep10_M_destroyERKSaIcE> + 10084d8: 003ff106 br 10084a0 <_ZSt21__throw_runtime_errorPKc+0x154> + +010084dc <_ZSt20__throw_out_of_rangePKc>: + 10084dc: deffe704 addi sp,sp,-100 + 10084e0: 00804034 movhi r2,256 + 10084e4: 109a9704 addi r2,r2,27228 + 10084e8: d8800815 stw r2,32(sp) + 10084ec: 00c040b4 movhi r3,258 + 10084f0: 18c34004 addi r3,r3,3328 + 10084f4: 00804074 movhi r2,257 + 10084f8: 10a17204 addi r2,r2,-31288 + 10084fc: d9001315 stw r4,76(sp) + 1008500: d9000204 addi r4,sp,8 + 1008504: d8800b15 stw r2,44(sp) + 1008508: dfc01815 stw ra,96(sp) + 100850c: df001715 stw fp,92(sp) + 1008510: ddc01615 stw r23,88(sp) + 1008514: d8c00915 stw r3,36(sp) + 1008518: dec00a15 stw sp,40(sp) + 100851c: dec00c15 stw sp,48(sp) + 1008520: 1009c1c0 call 1009c1c <_Unwind_SjLj_Register> + 1008524: 00800104 movi r2,4 + 1008528: d8800315 stw r2,12(sp) + 100852c: d885883a add r2,sp,r2 + 1008530: d8801415 stw r2,80(sp) + 1008534: d9401317 ldw r5,76(sp) + 1008538: 1009883a mov r4,r2 + 100853c: d9800084 addi r6,sp,2 + 1008540: 1003e680 call 1003e68 <_ZNSsC1EPKcRKSaIcE> + 1008544: 01000204 movi r4,8 + 1008548: 10075e00 call 10075e0 <__cxa_allocate_exception> + 100854c: d8801215 stw r2,72(sp) + 1008550: 008000c4 movi r2,3 + 1008554: d8800315 stw r2,12(sp) + 1008558: d9401417 ldw r5,80(sp) + 100855c: d9001217 ldw r4,72(sp) + 1008560: 10092d00 call 10092d0 <_ZNSt12out_of_rangeC1ERKSs> + 1008564: d8800117 ldw r2,4(sp) + 1008568: 00c040f4 movhi r3,259 + 100856c: 18e52f04 addi r3,r3,-27460 + 1008570: 10bffd04 addi r2,r2,-12 + 1008574: d8800f15 stw r2,60(sp) + 1008578: 10c0081e bne r2,r3,100859c <_ZSt20__throw_out_of_rangePKc+0xc0> + 100857c: d9001217 ldw r4,72(sp) + 1008580: 00bfffc4 movi r2,-1 + 1008584: 014040b4 movhi r5,258 + 1008588: 29449904 addi r5,r5,4708 + 100858c: 01804074 movhi r6,257 + 1008590: 31a23f04 addi r6,r6,-30468 + 1008594: d8800315 stw r2,12(sp) + 1008598: 10072ac0 call 10072ac <__cxa_throw> + 100859c: 00800044 movi r2,1 + 10085a0: d8800315 stw r2,12(sp) + 10085a4: d8800f17 ldw r2,60(sp) + 10085a8: 017fffc4 movi r5,-1 + 10085ac: 11000204 addi r4,r2,8 + 10085b0: 100617c0 call 100617c <_ZN9__gnu_cxx18__exchange_and_addEPVii> + 10085b4: 00bff116 blt zero,r2,100857c <_ZSt20__throw_out_of_rangePKc+0xa0> + 10085b8: d9000f17 ldw r4,60(sp) + 10085bc: d80b883a mov r5,sp + 10085c0: 1002c0c0 call 1002c0c <_ZNSs4_Rep10_M_destroyERKSaIcE> + 10085c4: 003fed06 br 100857c <_ZSt20__throw_out_of_rangePKc+0xa0> + 10085c8: d8800417 ldw r2,16(sp) + 10085cc: d8c00317 ldw r3,12(sp) + 10085d0: d9000517 ldw r4,20(sp) + 10085d4: d8801515 stw r2,84(sp) + 10085d8: 00800044 movi r2,1 + 10085dc: 18800426 beq r3,r2,10085f0 <_ZSt20__throw_out_of_rangePKc+0x114> + 10085e0: 00800084 movi r2,2 + 10085e4: 18800826 beq r3,r2,1008608 <_ZSt20__throw_out_of_rangePKc+0x12c> + 10085e8: 008000c4 movi r2,3 + 10085ec: 18800226 beq r3,r2,10085f8 <_ZSt20__throw_out_of_rangePKc+0x11c> + 10085f0: 00bfffc4 movi r2,-1 + 10085f4: 20801126 beq r4,r2,100863c <_ZSt20__throw_out_of_rangePKc+0x160> + 10085f8: d9001517 ldw r4,84(sp) + 10085fc: 00bfffc4 movi r2,-1 + 1008600: d8800315 stw r2,12(sp) + 1008604: 1009ee80 call 1009ee8 <_Unwind_SjLj_Resume> + 1008608: d9001217 ldw r4,72(sp) + 100860c: 10075a00 call 10075a0 <__cxa_free_exception> + 1008610: d8801517 ldw r2,84(sp) + 1008614: 00c040f4 movhi r3,259 + 1008618: 18e52f04 addi r3,r3,-27460 + 100861c: d8801115 stw r2,68(sp) + 1008620: d8800117 ldw r2,4(sp) + 1008624: 10bffd04 addi r2,r2,-12 + 1008628: d8801015 stw r2,64(sp) + 100862c: 10c0041e bne r2,r3,1008640 <_ZSt20__throw_out_of_rangePKc+0x164> + 1008630: d8801117 ldw r2,68(sp) + 1008634: d8801515 stw r2,84(sp) + 1008638: 003fef06 br 10085f8 <_ZSt20__throw_out_of_rangePKc+0x11c> + 100863c: 10070080 call 1007008 <_ZSt9terminatev> + 1008640: 00800084 movi r2,2 + 1008644: d8800315 stw r2,12(sp) + 1008648: d8801017 ldw r2,64(sp) + 100864c: 017fffc4 movi r5,-1 + 1008650: 11000204 addi r4,r2,8 + 1008654: 100617c0 call 100617c <_ZN9__gnu_cxx18__exchange_and_addEPVii> + 1008658: 00bff516 blt zero,r2,1008630 <_ZSt20__throw_out_of_rangePKc+0x154> + 100865c: d9001017 ldw r4,64(sp) + 1008660: d9400044 addi r5,sp,1 + 1008664: 1002c0c0 call 1002c0c <_ZNSs4_Rep10_M_destroyERKSaIcE> + 1008668: 003ff106 br 1008630 <_ZSt20__throw_out_of_rangePKc+0x154> + +0100866c <_ZSt20__throw_length_errorPKc>: + 100866c: deffe704 addi sp,sp,-100 + 1008670: 00804034 movhi r2,256 + 1008674: 109a9704 addi r2,r2,27228 + 1008678: d8800815 stw r2,32(sp) + 100867c: 00c040b4 movhi r3,258 + 1008680: 18c34604 addi r3,r3,3352 + 1008684: 00804074 movhi r2,257 + 1008688: 10a1d604 addi r2,r2,-30888 + 100868c: d9001315 stw r4,76(sp) + 1008690: d9000204 addi r4,sp,8 + 1008694: d8800b15 stw r2,44(sp) + 1008698: dfc01815 stw ra,96(sp) + 100869c: df001715 stw fp,92(sp) + 10086a0: ddc01615 stw r23,88(sp) + 10086a4: d8c00915 stw r3,36(sp) + 10086a8: dec00a15 stw sp,40(sp) + 10086ac: dec00c15 stw sp,48(sp) + 10086b0: 1009c1c0 call 1009c1c <_Unwind_SjLj_Register> + 10086b4: 00800104 movi r2,4 + 10086b8: d8800315 stw r2,12(sp) + 10086bc: d885883a add r2,sp,r2 + 10086c0: d8801415 stw r2,80(sp) + 10086c4: d9401317 ldw r5,76(sp) + 10086c8: 1009883a mov r4,r2 + 10086cc: d9800084 addi r6,sp,2 + 10086d0: 1003e680 call 1003e68 <_ZNSsC1EPKcRKSaIcE> + 10086d4: 01000204 movi r4,8 + 10086d8: 10075e00 call 10075e0 <__cxa_allocate_exception> + 10086dc: d8801215 stw r2,72(sp) + 10086e0: 008000c4 movi r2,3 + 10086e4: d8800315 stw r2,12(sp) + 10086e8: d9401417 ldw r5,80(sp) + 10086ec: d9001217 ldw r4,72(sp) + 10086f0: 10093300 call 1009330 <_ZNSt12length_errorC1ERKSs> + 10086f4: d8800117 ldw r2,4(sp) + 10086f8: 00c040f4 movhi r3,259 + 10086fc: 18e52f04 addi r3,r3,-27460 + 1008700: 10bffd04 addi r2,r2,-12 + 1008704: d8800f15 stw r2,60(sp) + 1008708: 10c0081e bne r2,r3,100872c <_ZSt20__throw_length_errorPKc+0xc0> + 100870c: d9001217 ldw r4,72(sp) + 1008710: 00bfffc4 movi r2,-1 + 1008714: 014040b4 movhi r5,258 + 1008718: 2944a604 addi r5,r5,4760 + 100871c: 01804074 movhi r6,257 + 1008720: 31a25004 addi r6,r6,-30400 + 1008724: d8800315 stw r2,12(sp) + 1008728: 10072ac0 call 10072ac <__cxa_throw> + 100872c: 00800044 movi r2,1 + 1008730: d8800315 stw r2,12(sp) + 1008734: d8800f17 ldw r2,60(sp) + 1008738: 017fffc4 movi r5,-1 + 100873c: 11000204 addi r4,r2,8 + 1008740: 100617c0 call 100617c <_ZN9__gnu_cxx18__exchange_and_addEPVii> + 1008744: 00bff116 blt zero,r2,100870c <_ZSt20__throw_length_errorPKc+0xa0> + 1008748: d9000f17 ldw r4,60(sp) + 100874c: d80b883a mov r5,sp + 1008750: 1002c0c0 call 1002c0c <_ZNSs4_Rep10_M_destroyERKSaIcE> + 1008754: 003fed06 br 100870c <_ZSt20__throw_length_errorPKc+0xa0> + 1008758: d8800417 ldw r2,16(sp) + 100875c: d8c00317 ldw r3,12(sp) + 1008760: d9000517 ldw r4,20(sp) + 1008764: d8801515 stw r2,84(sp) + 1008768: 00800044 movi r2,1 + 100876c: 18800426 beq r3,r2,1008780 <_ZSt20__throw_length_errorPKc+0x114> + 1008770: 00800084 movi r2,2 + 1008774: 18800826 beq r3,r2,1008798 <_ZSt20__throw_length_errorPKc+0x12c> + 1008778: 008000c4 movi r2,3 + 100877c: 18800226 beq r3,r2,1008788 <_ZSt20__throw_length_errorPKc+0x11c> + 1008780: 00bfffc4 movi r2,-1 + 1008784: 20801126 beq r4,r2,10087cc <_ZSt20__throw_length_errorPKc+0x160> + 1008788: d9001517 ldw r4,84(sp) + 100878c: 00bfffc4 movi r2,-1 + 1008790: d8800315 stw r2,12(sp) + 1008794: 1009ee80 call 1009ee8 <_Unwind_SjLj_Resume> + 1008798: d9001217 ldw r4,72(sp) + 100879c: 10075a00 call 10075a0 <__cxa_free_exception> + 10087a0: d8801517 ldw r2,84(sp) + 10087a4: 00c040f4 movhi r3,259 + 10087a8: 18e52f04 addi r3,r3,-27460 + 10087ac: d8801115 stw r2,68(sp) + 10087b0: d8800117 ldw r2,4(sp) + 10087b4: 10bffd04 addi r2,r2,-12 + 10087b8: d8801015 stw r2,64(sp) + 10087bc: 10c0041e bne r2,r3,10087d0 <_ZSt20__throw_length_errorPKc+0x164> + 10087c0: d8801117 ldw r2,68(sp) + 10087c4: d8801515 stw r2,84(sp) + 10087c8: 003fef06 br 1008788 <_ZSt20__throw_length_errorPKc+0x11c> + 10087cc: 10070080 call 1007008 <_ZSt9terminatev> + 10087d0: 00800084 movi r2,2 + 10087d4: d8800315 stw r2,12(sp) + 10087d8: d8801017 ldw r2,64(sp) + 10087dc: 017fffc4 movi r5,-1 + 10087e0: 11000204 addi r4,r2,8 + 10087e4: 100617c0 call 100617c <_ZN9__gnu_cxx18__exchange_and_addEPVii> + 10087e8: 00bff516 blt zero,r2,10087c0 <_ZSt20__throw_length_errorPKc+0x154> + 10087ec: d9001017 ldw r4,64(sp) + 10087f0: d9400044 addi r5,sp,1 + 10087f4: 1002c0c0 call 1002c0c <_ZNSs4_Rep10_M_destroyERKSaIcE> + 10087f8: 003ff106 br 10087c0 <_ZSt20__throw_length_errorPKc+0x154> + +010087fc <_ZNSt15underflow_errorD0Ev>: + 10087fc: defffe04 addi sp,sp,-8 + 1008800: 008040b4 movhi r2,258 + 1008804: 10847d04 addi r2,r2,4596 + 1008808: dc400015 stw r17,0(sp) + 100880c: 20800015 stw r2,0(r4) + 1008810: 2023883a mov r17,r4 + 1008814: dfc00115 stw ra,4(sp) + 1008818: 100960c0 call 100960c <_ZNSt13runtime_errorD2Ev> + 100881c: 8809883a mov r4,r17 + 1008820: dfc00117 ldw ra,4(sp) + 1008824: dc400017 ldw r17,0(sp) + 1008828: dec00204 addi sp,sp,8 + 100882c: 100722c1 jmpi 100722c <_ZdlPv> + +01008830 <_ZNSt15underflow_errorD1Ev>: + 1008830: 008040b4 movhi r2,258 + 1008834: 10847d04 addi r2,r2,4596 + 1008838: 20800015 stw r2,0(r4) + 100883c: 100960c1 jmpi 100960c <_ZNSt13runtime_errorD2Ev> + +01008840 <_ZNSt14overflow_errorD0Ev>: + 1008840: defffe04 addi sp,sp,-8 + 1008844: 008040b4 movhi r2,258 + 1008848: 10848a04 addi r2,r2,4648 + 100884c: dc400015 stw r17,0(sp) + 1008850: 20800015 stw r2,0(r4) + 1008854: 2023883a mov r17,r4 + 1008858: dfc00115 stw ra,4(sp) + 100885c: 100960c0 call 100960c <_ZNSt13runtime_errorD2Ev> + 1008860: 8809883a mov r4,r17 + 1008864: dfc00117 ldw ra,4(sp) + 1008868: dc400017 ldw r17,0(sp) + 100886c: dec00204 addi sp,sp,8 + 1008870: 100722c1 jmpi 100722c <_ZdlPv> + +01008874 <_ZNSt14overflow_errorD1Ev>: + 1008874: 008040b4 movhi r2,258 + 1008878: 10848a04 addi r2,r2,4648 + 100887c: 20800015 stw r2,0(r4) + 1008880: 100960c1 jmpi 100960c <_ZNSt13runtime_errorD2Ev> + +01008884 <_ZNSt11range_errorD0Ev>: + 1008884: defffe04 addi sp,sp,-8 + 1008888: 008040b4 movhi r2,258 + 100888c: 10849604 addi r2,r2,4696 + 1008890: dc400015 stw r17,0(sp) + 1008894: 20800015 stw r2,0(r4) + 1008898: 2023883a mov r17,r4 + 100889c: dfc00115 stw ra,4(sp) + 10088a0: 100960c0 call 100960c <_ZNSt13runtime_errorD2Ev> + 10088a4: 8809883a mov r4,r17 + 10088a8: dfc00117 ldw ra,4(sp) + 10088ac: dc400017 ldw r17,0(sp) + 10088b0: dec00204 addi sp,sp,8 + 10088b4: 100722c1 jmpi 100722c <_ZdlPv> + +010088b8 <_ZNSt11range_errorD1Ev>: + 10088b8: 008040b4 movhi r2,258 + 10088bc: 10849604 addi r2,r2,4696 + 10088c0: 20800015 stw r2,0(r4) + 10088c4: 100960c1 jmpi 100960c <_ZNSt13runtime_errorD2Ev> + +010088c8 <_ZNSt12out_of_rangeD0Ev>: + 10088c8: defffe04 addi sp,sp,-8 + 10088cc: 008040b4 movhi r2,258 + 10088d0: 1084a304 addi r2,r2,4748 + 10088d4: dc400015 stw r17,0(sp) + 10088d8: 20800015 stw r2,0(r4) + 10088dc: 2023883a mov r17,r4 + 10088e0: dfc00115 stw ra,4(sp) + 10088e4: 100981c0 call 100981c <_ZNSt11logic_errorD2Ev> + 10088e8: 8809883a mov r4,r17 + 10088ec: dfc00117 ldw ra,4(sp) + 10088f0: dc400017 ldw r17,0(sp) + 10088f4: dec00204 addi sp,sp,8 + 10088f8: 100722c1 jmpi 100722c <_ZdlPv> + +010088fc <_ZNSt12out_of_rangeD1Ev>: + 10088fc: 008040b4 movhi r2,258 + 1008900: 1084a304 addi r2,r2,4748 + 1008904: 20800015 stw r2,0(r4) + 1008908: 100981c1 jmpi 100981c <_ZNSt11logic_errorD2Ev> + +0100890c <_ZNSt12length_errorD0Ev>: + 100890c: defffe04 addi sp,sp,-8 + 1008910: 008040b4 movhi r2,258 + 1008914: 1084b004 addi r2,r2,4800 + 1008918: dc400015 stw r17,0(sp) + 100891c: 20800015 stw r2,0(r4) + 1008920: 2023883a mov r17,r4 + 1008924: dfc00115 stw ra,4(sp) + 1008928: 100981c0 call 100981c <_ZNSt11logic_errorD2Ev> + 100892c: 8809883a mov r4,r17 + 1008930: dfc00117 ldw ra,4(sp) + 1008934: dc400017 ldw r17,0(sp) + 1008938: dec00204 addi sp,sp,8 + 100893c: 100722c1 jmpi 100722c <_ZdlPv> + +01008940 <_ZNSt12length_errorD1Ev>: + 1008940: 008040b4 movhi r2,258 + 1008944: 1084b004 addi r2,r2,4800 + 1008948: 20800015 stw r2,0(r4) + 100894c: 100981c1 jmpi 100981c <_ZNSt11logic_errorD2Ev> + +01008950 <_ZNSt16invalid_argumentD0Ev>: + 1008950: defffe04 addi sp,sp,-8 + 1008954: 008040b4 movhi r2,258 + 1008958: 1084be04 addi r2,r2,4856 + 100895c: dc400015 stw r17,0(sp) + 1008960: 20800015 stw r2,0(r4) + 1008964: 2023883a mov r17,r4 + 1008968: dfc00115 stw ra,4(sp) + 100896c: 100981c0 call 100981c <_ZNSt11logic_errorD2Ev> + 1008970: 8809883a mov r4,r17 + 1008974: dfc00117 ldw ra,4(sp) + 1008978: dc400017 ldw r17,0(sp) + 100897c: dec00204 addi sp,sp,8 + 1008980: 100722c1 jmpi 100722c <_ZdlPv> + +01008984 <_ZNSt16invalid_argumentD1Ev>: + 1008984: 008040b4 movhi r2,258 + 1008988: 1084be04 addi r2,r2,4856 + 100898c: 20800015 stw r2,0(r4) + 1008990: 100981c1 jmpi 100981c <_ZNSt11logic_errorD2Ev> + +01008994 <_ZNSt12domain_errorD0Ev>: + 1008994: defffe04 addi sp,sp,-8 + 1008998: 008040b4 movhi r2,258 + 100899c: 1084cb04 addi r2,r2,4908 + 10089a0: dc400015 stw r17,0(sp) + 10089a4: 20800015 stw r2,0(r4) + 10089a8: 2023883a mov r17,r4 + 10089ac: dfc00115 stw ra,4(sp) + 10089b0: 100981c0 call 100981c <_ZNSt11logic_errorD2Ev> + 10089b4: 8809883a mov r4,r17 + 10089b8: dfc00117 ldw ra,4(sp) + 10089bc: dc400017 ldw r17,0(sp) + 10089c0: dec00204 addi sp,sp,8 + 10089c4: 100722c1 jmpi 100722c <_ZdlPv> + +010089c8 <_ZNSt12domain_errorD1Ev>: + 10089c8: 008040b4 movhi r2,258 + 10089cc: 1084cb04 addi r2,r2,4908 + 10089d0: 20800015 stw r2,0(r4) + 10089d4: 100981c1 jmpi 100981c <_ZNSt11logic_errorD2Ev> + +010089d8 <_ZNKSt8ios_base7failure4whatEv>: + 10089d8: 20800117 ldw r2,4(r4) + 10089dc: f800283a ret + +010089e0 <_ZNSt8ios_base7failureD1Ev>: + 10089e0: deffeb04 addi sp,sp,-84 + 10089e4: 00804034 movhi r2,256 + 10089e8: 109a9704 addi r2,r2,27228 + 10089ec: 00c040b4 movhi r3,258 + 10089f0: 18c34c04 addi r3,r3,3376 + 10089f4: d8800715 stw r2,28(sp) + 10089f8: d9001015 stw r4,64(sp) + 10089fc: 00804074 movhi r2,257 + 1008a00: 10a2a904 addi r2,r2,-30044 + 1008a04: d9000104 addi r4,sp,4 + 1008a08: d8c00815 stw r3,32(sp) + 1008a0c: d8800a15 stw r2,40(sp) + 1008a10: dfc01415 stw ra,80(sp) + 1008a14: df001315 stw fp,76(sp) + 1008a18: ddc01215 stw r23,72(sp) + 1008a1c: dec00915 stw sp,36(sp) + 1008a20: dec00b15 stw sp,44(sp) + 1008a24: 1009c1c0 call 1009c1c <_Unwind_SjLj_Register> + 1008a28: d8c01017 ldw r3,64(sp) + 1008a2c: 18800117 ldw r2,4(r3) + 1008a30: 00c040b4 movhi r3,258 + 1008a34: 18c4d004 addi r3,r3,4928 + 1008a38: 10bffd04 addi r2,r2,-12 + 1008a3c: d8800e15 stw r2,56(sp) + 1008a40: d8801017 ldw r2,64(sp) + 1008a44: 10c00015 stw r3,0(r2) + 1008a48: d8c00e17 ldw r3,56(sp) + 1008a4c: 008040f4 movhi r2,259 + 1008a50: 10a52f04 addi r2,r2,-27460 + 1008a54: 1880091e bne r3,r2,1008a7c <_ZNSt8ios_base7failureD1Ev+0x9c> + 1008a58: d9001017 ldw r4,64(sp) + 1008a5c: 1009a5c0 call 1009a5c <_ZNSt9exceptionD2Ev> + 1008a60: d9000104 addi r4,sp,4 + 1008a64: 1009c2c0 call 1009c2c <_Unwind_SjLj_Unregister> + 1008a68: dfc01417 ldw ra,80(sp) + 1008a6c: df001317 ldw fp,76(sp) + 1008a70: ddc01217 ldw r23,72(sp) + 1008a74: dec01504 addi sp,sp,84 + 1008a78: f800283a ret + 1008a7c: 00800044 movi r2,1 + 1008a80: d8800215 stw r2,8(sp) + 1008a84: 19000204 addi r4,r3,8 + 1008a88: 017fffc4 movi r5,-1 + 1008a8c: 100617c0 call 100617c <_ZN9__gnu_cxx18__exchange_and_addEPVii> + 1008a90: 00bff116 blt zero,r2,1008a58 <_ZNSt8ios_base7failureD1Ev+0x78> + 1008a94: d9000e17 ldw r4,56(sp) + 1008a98: d80b883a mov r5,sp + 1008a9c: 1002c0c0 call 1002c0c <_ZNSs4_Rep10_M_destroyERKSaIcE> + 1008aa0: 003fed06 br 1008a58 <_ZNSt8ios_base7failureD1Ev+0x78> + 1008aa4: d8800417 ldw r2,16(sp) + 1008aa8: d8c00317 ldw r3,12(sp) + 1008aac: d9001017 ldw r4,64(sp) + 1008ab0: d8800f15 stw r2,60(sp) + 1008ab4: d8c01115 stw r3,68(sp) + 1008ab8: 1009a5c0 call 1009a5c <_ZNSt9exceptionD2Ev> + 1008abc: d8c00f17 ldw r3,60(sp) + 1008ac0: 00bfffc4 movi r2,-1 + 1008ac4: 18800326 beq r3,r2,1008ad4 <_ZNSt8ios_base7failureD1Ev+0xf4> + 1008ac8: d9001117 ldw r4,68(sp) + 1008acc: d8800215 stw r2,8(sp) + 1008ad0: 1009ee80 call 1009ee8 <_Unwind_SjLj_Resume> + 1008ad4: d9001117 ldw r4,68(sp) + 1008ad8: 00bfffc4 movi r2,-1 + 1008adc: d8800215 stw r2,8(sp) + 1008ae0: 10068dc0 call 10068dc <__cxa_call_unexpected> + +01008ae4 <_ZNSt8ios_base7failureC1ERKSs>: + 1008ae4: deffec04 addi sp,sp,-80 + 1008ae8: 00804034 movhi r2,256 + 1008aec: 109a9704 addi r2,r2,27228 + 1008af0: 00c040b4 movhi r3,258 + 1008af4: 18c35004 addi r3,r3,3392 + 1008af8: d8800615 stw r2,24(sp) + 1008afc: d9000d15 stw r4,52(sp) + 1008b00: 00804074 movhi r2,257 + 1008b04: 10a2dd04 addi r2,r2,-29836 + 1008b08: d809883a mov r4,sp + 1008b0c: d8c00715 stw r3,28(sp) + 1008b10: d8800915 stw r2,36(sp) + 1008b14: d9400e15 stw r5,56(sp) + 1008b18: dfc01315 stw ra,76(sp) + 1008b1c: df001215 stw fp,72(sp) + 1008b20: ddc01115 stw r23,68(sp) + 1008b24: dec00815 stw sp,32(sp) + 1008b28: dec00a15 stw sp,40(sp) + 1008b2c: 1009c1c0 call 1009c1c <_Unwind_SjLj_Register> + 1008b30: d8c00d17 ldw r3,52(sp) + 1008b34: 008040b4 movhi r2,258 + 1008b38: 1084d004 addi r2,r2,4928 + 1008b3c: d9400e17 ldw r5,56(sp) + 1008b40: 18800015 stw r2,0(r3) + 1008b44: d8800d17 ldw r2,52(sp) + 1008b48: 00c00044 movi r3,1 + 1008b4c: d8c00115 stw r3,4(sp) + 1008b50: 11000104 addi r4,r2,4 + 1008b54: 10040640 call 1004064 <_ZNSsC1ERKSs> + 1008b58: d809883a mov r4,sp + 1008b5c: 1009c2c0 call 1009c2c <_Unwind_SjLj_Unregister> + 1008b60: dfc01317 ldw ra,76(sp) + 1008b64: df001217 ldw fp,72(sp) + 1008b68: ddc01117 ldw r23,68(sp) + 1008b6c: dec01404 addi sp,sp,80 + 1008b70: f800283a ret + 1008b74: d8c00317 ldw r3,12(sp) + 1008b78: d8800217 ldw r2,8(sp) + 1008b7c: d9000d17 ldw r4,52(sp) + 1008b80: d8c00f15 stw r3,60(sp) + 1008b84: d8801015 stw r2,64(sp) + 1008b88: 1009a5c0 call 1009a5c <_ZNSt9exceptionD2Ev> + 1008b8c: d8c00f17 ldw r3,60(sp) + 1008b90: 00bfffc4 movi r2,-1 + 1008b94: 18800326 beq r3,r2,1008ba4 <_ZNSt8ios_base7failureC1ERKSs+0xc0> + 1008b98: d9001017 ldw r4,64(sp) + 1008b9c: d8800115 stw r2,4(sp) + 1008ba0: 1009ee80 call 1009ee8 <_Unwind_SjLj_Resume> + 1008ba4: d9001017 ldw r4,64(sp) + 1008ba8: 00bfffc4 movi r2,-1 + 1008bac: d8800115 stw r2,4(sp) + 1008bb0: 10068dc0 call 10068dc <__cxa_call_unexpected> + +01008bb4 <_ZNSt8ios_base7failureC2ERKSs>: + 1008bb4: deffec04 addi sp,sp,-80 + 1008bb8: 00804034 movhi r2,256 + 1008bbc: 109a9704 addi r2,r2,27228 + 1008bc0: 00c040b4 movhi r3,258 + 1008bc4: 18c35404 addi r3,r3,3408 + 1008bc8: d8800615 stw r2,24(sp) + 1008bcc: d9000d15 stw r4,52(sp) + 1008bd0: 00804074 movhi r2,257 + 1008bd4: 10a31104 addi r2,r2,-29628 + 1008bd8: d809883a mov r4,sp + 1008bdc: d8c00715 stw r3,28(sp) + 1008be0: d8800915 stw r2,36(sp) + 1008be4: d9400e15 stw r5,56(sp) + 1008be8: dfc01315 stw ra,76(sp) + 1008bec: df001215 stw fp,72(sp) + 1008bf0: ddc01115 stw r23,68(sp) + 1008bf4: dec00815 stw sp,32(sp) + 1008bf8: dec00a15 stw sp,40(sp) + 1008bfc: 1009c1c0 call 1009c1c <_Unwind_SjLj_Register> + 1008c00: d8c00d17 ldw r3,52(sp) + 1008c04: 008040b4 movhi r2,258 + 1008c08: 1084d004 addi r2,r2,4928 + 1008c0c: d9400e17 ldw r5,56(sp) + 1008c10: 18800015 stw r2,0(r3) + 1008c14: d8800d17 ldw r2,52(sp) + 1008c18: 00c00044 movi r3,1 + 1008c1c: d8c00115 stw r3,4(sp) + 1008c20: 11000104 addi r4,r2,4 + 1008c24: 10040640 call 1004064 <_ZNSsC1ERKSs> + 1008c28: d809883a mov r4,sp + 1008c2c: 1009c2c0 call 1009c2c <_Unwind_SjLj_Unregister> + 1008c30: dfc01317 ldw ra,76(sp) + 1008c34: df001217 ldw fp,72(sp) + 1008c38: ddc01117 ldw r23,68(sp) + 1008c3c: dec01404 addi sp,sp,80 + 1008c40: f800283a ret + 1008c44: d8c00317 ldw r3,12(sp) + 1008c48: d8800217 ldw r2,8(sp) + 1008c4c: d9000d17 ldw r4,52(sp) + 1008c50: d8c00f15 stw r3,60(sp) + 1008c54: d8801015 stw r2,64(sp) + 1008c58: 1009a5c0 call 1009a5c <_ZNSt9exceptionD2Ev> + 1008c5c: d8c00f17 ldw r3,60(sp) + 1008c60: 00bfffc4 movi r2,-1 + 1008c64: 18800326 beq r3,r2,1008c74 <_ZNSt8ios_base7failureC2ERKSs+0xc0> + 1008c68: d9001017 ldw r4,64(sp) + 1008c6c: d8800115 stw r2,4(sp) + 1008c70: 1009ee80 call 1009ee8 <_Unwind_SjLj_Resume> + 1008c74: d9001017 ldw r4,64(sp) + 1008c78: 00bfffc4 movi r2,-1 + 1008c7c: d8800115 stw r2,4(sp) + 1008c80: 10068dc0 call 10068dc <__cxa_call_unexpected> + +01008c84 <_ZNSt8ios_base7failureD2Ev>: + 1008c84: deffeb04 addi sp,sp,-84 + 1008c88: 00804034 movhi r2,256 + 1008c8c: 109a9704 addi r2,r2,27228 + 1008c90: 00c040b4 movhi r3,258 + 1008c94: 18c35804 addi r3,r3,3424 + 1008c98: d8800715 stw r2,28(sp) + 1008c9c: d9001015 stw r4,64(sp) + 1008ca0: 00804074 movhi r2,257 + 1008ca4: 10a35204 addi r2,r2,-29368 + 1008ca8: d9000104 addi r4,sp,4 + 1008cac: d8c00815 stw r3,32(sp) + 1008cb0: d8800a15 stw r2,40(sp) + 1008cb4: dfc01415 stw ra,80(sp) + 1008cb8: df001315 stw fp,76(sp) + 1008cbc: ddc01215 stw r23,72(sp) + 1008cc0: dec00915 stw sp,36(sp) + 1008cc4: dec00b15 stw sp,44(sp) + 1008cc8: 1009c1c0 call 1009c1c <_Unwind_SjLj_Register> + 1008ccc: d8c01017 ldw r3,64(sp) + 1008cd0: 18800117 ldw r2,4(r3) + 1008cd4: 00c040b4 movhi r3,258 + 1008cd8: 18c4d004 addi r3,r3,4928 + 1008cdc: 10bffd04 addi r2,r2,-12 + 1008ce0: d8800e15 stw r2,56(sp) + 1008ce4: d8801017 ldw r2,64(sp) + 1008ce8: 10c00015 stw r3,0(r2) + 1008cec: d8c00e17 ldw r3,56(sp) + 1008cf0: 008040f4 movhi r2,259 + 1008cf4: 10a52f04 addi r2,r2,-27460 + 1008cf8: 1880091e bne r3,r2,1008d20 <_ZNSt8ios_base7failureD2Ev+0x9c> + 1008cfc: d9001017 ldw r4,64(sp) + 1008d00: 1009a5c0 call 1009a5c <_ZNSt9exceptionD2Ev> + 1008d04: d9000104 addi r4,sp,4 + 1008d08: 1009c2c0 call 1009c2c <_Unwind_SjLj_Unregister> + 1008d0c: dfc01417 ldw ra,80(sp) + 1008d10: df001317 ldw fp,76(sp) + 1008d14: ddc01217 ldw r23,72(sp) + 1008d18: dec01504 addi sp,sp,84 + 1008d1c: f800283a ret + 1008d20: 00800044 movi r2,1 + 1008d24: d8800215 stw r2,8(sp) + 1008d28: 19000204 addi r4,r3,8 + 1008d2c: 017fffc4 movi r5,-1 + 1008d30: 100617c0 call 100617c <_ZN9__gnu_cxx18__exchange_and_addEPVii> + 1008d34: 00bff116 blt zero,r2,1008cfc <_ZNSt8ios_base7failureD2Ev+0x78> + 1008d38: d9000e17 ldw r4,56(sp) + 1008d3c: d80b883a mov r5,sp + 1008d40: 1002c0c0 call 1002c0c <_ZNSs4_Rep10_M_destroyERKSaIcE> + 1008d44: 003fed06 br 1008cfc <_ZNSt8ios_base7failureD2Ev+0x78> + 1008d48: d8800417 ldw r2,16(sp) + 1008d4c: d8c00317 ldw r3,12(sp) + 1008d50: d9001017 ldw r4,64(sp) + 1008d54: d8800f15 stw r2,60(sp) + 1008d58: d8c01115 stw r3,68(sp) + 1008d5c: 1009a5c0 call 1009a5c <_ZNSt9exceptionD2Ev> + 1008d60: d8c00f17 ldw r3,60(sp) + 1008d64: 00bfffc4 movi r2,-1 + 1008d68: 18800326 beq r3,r2,1008d78 <_ZNSt8ios_base7failureD2Ev+0xf4> + 1008d6c: d9001117 ldw r4,68(sp) + 1008d70: d8800215 stw r2,8(sp) + 1008d74: 1009ee80 call 1009ee8 <_Unwind_SjLj_Resume> + 1008d78: d9001117 ldw r4,68(sp) + 1008d7c: 00bfffc4 movi r2,-1 + 1008d80: d8800215 stw r2,8(sp) + 1008d84: 10068dc0 call 10068dc <__cxa_call_unexpected> + +01008d88 <_ZNSt8ios_base7failureD0Ev>: + 1008d88: deffeb04 addi sp,sp,-84 + 1008d8c: 00804034 movhi r2,256 + 1008d90: 109a9704 addi r2,r2,27228 + 1008d94: 00c040b4 movhi r3,258 + 1008d98: 18c35c04 addi r3,r3,3440 + 1008d9c: d8800715 stw r2,28(sp) + 1008da0: d9001015 stw r4,64(sp) + 1008da4: 00804074 movhi r2,257 + 1008da8: 10a39504 addi r2,r2,-29100 + 1008dac: d9000104 addi r4,sp,4 + 1008db0: d8c00815 stw r3,32(sp) + 1008db4: d8800a15 stw r2,40(sp) + 1008db8: dfc01415 stw ra,80(sp) + 1008dbc: df001315 stw fp,76(sp) + 1008dc0: ddc01215 stw r23,72(sp) + 1008dc4: dec00915 stw sp,36(sp) + 1008dc8: dec00b15 stw sp,44(sp) + 1008dcc: 1009c1c0 call 1009c1c <_Unwind_SjLj_Register> + 1008dd0: d8c01017 ldw r3,64(sp) + 1008dd4: 18800117 ldw r2,4(r3) + 1008dd8: 00c040b4 movhi r3,258 + 1008ddc: 18c4d004 addi r3,r3,4928 + 1008de0: 10bffd04 addi r2,r2,-12 + 1008de4: d8800e15 stw r2,56(sp) + 1008de8: d8801017 ldw r2,64(sp) + 1008dec: 10c00015 stw r3,0(r2) + 1008df0: d8c00e17 ldw r3,56(sp) + 1008df4: 008040f4 movhi r2,259 + 1008df8: 10a52f04 addi r2,r2,-27460 + 1008dfc: 18800b1e bne r3,r2,1008e2c <_ZNSt8ios_base7failureD0Ev+0xa4> + 1008e00: d9001017 ldw r4,64(sp) + 1008e04: 1009a5c0 call 1009a5c <_ZNSt9exceptionD2Ev> + 1008e08: d9001017 ldw r4,64(sp) + 1008e0c: 100722c0 call 100722c <_ZdlPv> + 1008e10: d9000104 addi r4,sp,4 + 1008e14: 1009c2c0 call 1009c2c <_Unwind_SjLj_Unregister> + 1008e18: dfc01417 ldw ra,80(sp) + 1008e1c: df001317 ldw fp,76(sp) + 1008e20: ddc01217 ldw r23,72(sp) + 1008e24: dec01504 addi sp,sp,84 + 1008e28: f800283a ret + 1008e2c: 00800044 movi r2,1 + 1008e30: d8800215 stw r2,8(sp) + 1008e34: 19000204 addi r4,r3,8 + 1008e38: 017fffc4 movi r5,-1 + 1008e3c: 100617c0 call 100617c <_ZN9__gnu_cxx18__exchange_and_addEPVii> + 1008e40: 00bfef16 blt zero,r2,1008e00 <_ZNSt8ios_base7failureD0Ev+0x78> + 1008e44: d9000e17 ldw r4,56(sp) + 1008e48: d80b883a mov r5,sp + 1008e4c: 1002c0c0 call 1002c0c <_ZNSs4_Rep10_M_destroyERKSaIcE> + 1008e50: 003feb06 br 1008e00 <_ZNSt8ios_base7failureD0Ev+0x78> + 1008e54: d8800417 ldw r2,16(sp) + 1008e58: d8c00317 ldw r3,12(sp) + 1008e5c: d9001017 ldw r4,64(sp) + 1008e60: d8800f15 stw r2,60(sp) + 1008e64: d8c01115 stw r3,68(sp) + 1008e68: 1009a5c0 call 1009a5c <_ZNSt9exceptionD2Ev> + 1008e6c: d8c00f17 ldw r3,60(sp) + 1008e70: 00bfffc4 movi r2,-1 + 1008e74: 18800326 beq r3,r2,1008e84 <_ZNSt8ios_base7failureD0Ev+0xfc> + 1008e78: d9001117 ldw r4,68(sp) + 1008e7c: d8800215 stw r2,8(sp) + 1008e80: 1009ee80 call 1009ee8 <_Unwind_SjLj_Resume> + 1008e84: d9001117 ldw r4,68(sp) + 1008e88: 00bfffc4 movi r2,-1 + 1008e8c: d8800215 stw r2,8(sp) + 1008e90: 10068dc0 call 10068dc <__cxa_call_unexpected> + +01008e94 <_ZNKSt13runtime_error4whatEv>: + 1008e94: 20800117 ldw r2,4(r4) + 1008e98: f800283a ret + +01008e9c <_ZNSt11logic_errorD1Ev>: + 1008e9c: deffeb04 addi sp,sp,-84 + 1008ea0: 00804034 movhi r2,256 + 1008ea4: 109a9704 addi r2,r2,27228 + 1008ea8: 00c040b4 movhi r3,258 + 1008eac: 18c36004 addi r3,r3,3456 + 1008eb0: d8800715 stw r2,28(sp) + 1008eb4: d9001015 stw r4,64(sp) + 1008eb8: 00804074 movhi r2,257 + 1008ebc: 10a3d804 addi r2,r2,-28832 + 1008ec0: d9000104 addi r4,sp,4 + 1008ec4: d8c00815 stw r3,32(sp) + 1008ec8: d8800a15 stw r2,40(sp) + 1008ecc: dfc01415 stw ra,80(sp) + 1008ed0: df001315 stw fp,76(sp) + 1008ed4: ddc01215 stw r23,72(sp) + 1008ed8: dec00915 stw sp,36(sp) + 1008edc: dec00b15 stw sp,44(sp) + 1008ee0: 1009c1c0 call 1009c1c <_Unwind_SjLj_Register> + 1008ee4: d8c01017 ldw r3,64(sp) + 1008ee8: 18800117 ldw r2,4(r3) + 1008eec: 00c040b4 movhi r3,258 + 1008ef0: 18c4e304 addi r3,r3,5004 + 1008ef4: 10bffd04 addi r2,r2,-12 + 1008ef8: d8800e15 stw r2,56(sp) + 1008efc: d8801017 ldw r2,64(sp) + 1008f00: 10c00015 stw r3,0(r2) + 1008f04: d8c00e17 ldw r3,56(sp) + 1008f08: 008040f4 movhi r2,259 + 1008f0c: 10a52f04 addi r2,r2,-27460 + 1008f10: 1880091e bne r3,r2,1008f38 <_ZNSt11logic_errorD1Ev+0x9c> + 1008f14: d9001017 ldw r4,64(sp) + 1008f18: 1009a5c0 call 1009a5c <_ZNSt9exceptionD2Ev> + 1008f1c: d9000104 addi r4,sp,4 + 1008f20: 1009c2c0 call 1009c2c <_Unwind_SjLj_Unregister> + 1008f24: dfc01417 ldw ra,80(sp) + 1008f28: df001317 ldw fp,76(sp) + 1008f2c: ddc01217 ldw r23,72(sp) + 1008f30: dec01504 addi sp,sp,84 + 1008f34: f800283a ret + 1008f38: 00800044 movi r2,1 + 1008f3c: d8800215 stw r2,8(sp) + 1008f40: 19000204 addi r4,r3,8 + 1008f44: 017fffc4 movi r5,-1 + 1008f48: 100617c0 call 100617c <_ZN9__gnu_cxx18__exchange_and_addEPVii> + 1008f4c: 00bff116 blt zero,r2,1008f14 <_ZNSt11logic_errorD1Ev+0x78> + 1008f50: d9000e17 ldw r4,56(sp) + 1008f54: d80b883a mov r5,sp + 1008f58: 1002c0c0 call 1002c0c <_ZNSs4_Rep10_M_destroyERKSaIcE> + 1008f5c: 003fed06 br 1008f14 <_ZNSt11logic_errorD1Ev+0x78> + 1008f60: d8800417 ldw r2,16(sp) + 1008f64: d8c00317 ldw r3,12(sp) + 1008f68: d9001017 ldw r4,64(sp) + 1008f6c: d8800f15 stw r2,60(sp) + 1008f70: d8c01115 stw r3,68(sp) + 1008f74: 1009a5c0 call 1009a5c <_ZNSt9exceptionD2Ev> + 1008f78: d8c00f17 ldw r3,60(sp) + 1008f7c: 00bfffc4 movi r2,-1 + 1008f80: 18800326 beq r3,r2,1008f90 <_ZNSt11logic_errorD1Ev+0xf4> + 1008f84: d9001117 ldw r4,68(sp) + 1008f88: d8800215 stw r2,8(sp) + 1008f8c: 1009ee80 call 1009ee8 <_Unwind_SjLj_Resume> + 1008f90: d9001117 ldw r4,68(sp) + 1008f94: 00bfffc4 movi r2,-1 + 1008f98: d8800215 stw r2,8(sp) + 1008f9c: 10068dc0 call 10068dc <__cxa_call_unexpected> + +01008fa0 <_ZNSt13runtime_errorC2ERKSs>: + 1008fa0: deffed04 addi sp,sp,-76 + 1008fa4: 00804034 movhi r2,256 + 1008fa8: 109a9704 addi r2,r2,27228 + 1008fac: 00c040b4 movhi r3,258 + 1008fb0: 18c36344 addi r3,r3,3469 + 1008fb4: d8800615 stw r2,24(sp) + 1008fb8: d9000d15 stw r4,52(sp) + 1008fbc: 00804074 movhi r2,257 + 1008fc0: 10a40c04 addi r2,r2,-28624 + 1008fc4: d809883a mov r4,sp + 1008fc8: d8c00715 stw r3,28(sp) + 1008fcc: d8800915 stw r2,36(sp) + 1008fd0: d9400e15 stw r5,56(sp) + 1008fd4: dfc01215 stw ra,72(sp) + 1008fd8: df001115 stw fp,68(sp) + 1008fdc: ddc01015 stw r23,64(sp) + 1008fe0: dec00815 stw sp,32(sp) + 1008fe4: dec00a15 stw sp,40(sp) + 1008fe8: 1009c1c0 call 1009c1c <_Unwind_SjLj_Register> + 1008fec: d8c00d17 ldw r3,52(sp) + 1008ff0: 008040b4 movhi r2,258 + 1008ff4: 1084de04 addi r2,r2,4984 + 1008ff8: d9400e17 ldw r5,56(sp) + 1008ffc: 18800015 stw r2,0(r3) + 1009000: d8800d17 ldw r2,52(sp) + 1009004: 00c00044 movi r3,1 + 1009008: d8c00115 stw r3,4(sp) + 100900c: 11000104 addi r4,r2,4 + 1009010: 10040640 call 1004064 <_ZNSsC1ERKSs> + 1009014: d809883a mov r4,sp + 1009018: 1009c2c0 call 1009c2c <_Unwind_SjLj_Unregister> + 100901c: dfc01217 ldw ra,72(sp) + 1009020: df001117 ldw fp,68(sp) + 1009024: ddc01017 ldw r23,64(sp) + 1009028: dec01304 addi sp,sp,76 + 100902c: f800283a ret + 1009030: d8c00217 ldw r3,8(sp) + 1009034: d9000d17 ldw r4,52(sp) + 1009038: d8c00f15 stw r3,60(sp) + 100903c: 1009a5c0 call 1009a5c <_ZNSt9exceptionD2Ev> + 1009040: d9000f17 ldw r4,60(sp) + 1009044: 00bfffc4 movi r2,-1 + 1009048: d8800115 stw r2,4(sp) + 100904c: 1009ee80 call 1009ee8 <_Unwind_SjLj_Resume> + +01009050 <_ZNSt15underflow_errorC1ERKSs>: + 1009050: defffe04 addi sp,sp,-8 + 1009054: dc000015 stw r16,0(sp) + 1009058: dfc00115 stw ra,4(sp) + 100905c: 2021883a mov r16,r4 + 1009060: 1008fa00 call 1008fa0 <_ZNSt13runtime_errorC2ERKSs> + 1009064: 008040b4 movhi r2,258 + 1009068: 10847d04 addi r2,r2,4596 + 100906c: 80800015 stw r2,0(r16) + 1009070: dfc00117 ldw ra,4(sp) + 1009074: dc000017 ldw r16,0(sp) + 1009078: dec00204 addi sp,sp,8 + 100907c: f800283a ret + +01009080 <_ZNSt15underflow_errorC2ERKSs>: + 1009080: defffe04 addi sp,sp,-8 + 1009084: dc000015 stw r16,0(sp) + 1009088: dfc00115 stw ra,4(sp) + 100908c: 2021883a mov r16,r4 + 1009090: 1008fa00 call 1008fa0 <_ZNSt13runtime_errorC2ERKSs> + 1009094: 008040b4 movhi r2,258 + 1009098: 10847d04 addi r2,r2,4596 + 100909c: 80800015 stw r2,0(r16) + 10090a0: dfc00117 ldw ra,4(sp) + 10090a4: dc000017 ldw r16,0(sp) + 10090a8: dec00204 addi sp,sp,8 + 10090ac: f800283a ret + +010090b0 <_ZNSt14overflow_errorC1ERKSs>: + 10090b0: defffe04 addi sp,sp,-8 + 10090b4: dc000015 stw r16,0(sp) + 10090b8: dfc00115 stw ra,4(sp) + 10090bc: 2021883a mov r16,r4 + 10090c0: 1008fa00 call 1008fa0 <_ZNSt13runtime_errorC2ERKSs> + 10090c4: 008040b4 movhi r2,258 + 10090c8: 10848a04 addi r2,r2,4648 + 10090cc: 80800015 stw r2,0(r16) + 10090d0: dfc00117 ldw ra,4(sp) + 10090d4: dc000017 ldw r16,0(sp) + 10090d8: dec00204 addi sp,sp,8 + 10090dc: f800283a ret + +010090e0 <_ZNSt14overflow_errorC2ERKSs>: + 10090e0: defffe04 addi sp,sp,-8 + 10090e4: dc000015 stw r16,0(sp) + 10090e8: dfc00115 stw ra,4(sp) + 10090ec: 2021883a mov r16,r4 + 10090f0: 1008fa00 call 1008fa0 <_ZNSt13runtime_errorC2ERKSs> + 10090f4: 008040b4 movhi r2,258 + 10090f8: 10848a04 addi r2,r2,4648 + 10090fc: 80800015 stw r2,0(r16) + 1009100: dfc00117 ldw ra,4(sp) + 1009104: dc000017 ldw r16,0(sp) + 1009108: dec00204 addi sp,sp,8 + 100910c: f800283a ret + +01009110 <_ZNSt11range_errorC1ERKSs>: + 1009110: defffe04 addi sp,sp,-8 + 1009114: dc000015 stw r16,0(sp) + 1009118: dfc00115 stw ra,4(sp) + 100911c: 2021883a mov r16,r4 + 1009120: 1008fa00 call 1008fa0 <_ZNSt13runtime_errorC2ERKSs> + 1009124: 008040b4 movhi r2,258 + 1009128: 10849604 addi r2,r2,4696 + 100912c: 80800015 stw r2,0(r16) + 1009130: dfc00117 ldw ra,4(sp) + 1009134: dc000017 ldw r16,0(sp) + 1009138: dec00204 addi sp,sp,8 + 100913c: f800283a ret + +01009140 <_ZNSt11range_errorC2ERKSs>: + 1009140: defffe04 addi sp,sp,-8 + 1009144: dc000015 stw r16,0(sp) + 1009148: dfc00115 stw ra,4(sp) + 100914c: 2021883a mov r16,r4 + 1009150: 1008fa00 call 1008fa0 <_ZNSt13runtime_errorC2ERKSs> + 1009154: 008040b4 movhi r2,258 + 1009158: 10849604 addi r2,r2,4696 + 100915c: 80800015 stw r2,0(r16) + 1009160: dfc00117 ldw ra,4(sp) + 1009164: dc000017 ldw r16,0(sp) + 1009168: dec00204 addi sp,sp,8 + 100916c: f800283a ret + +01009170 <_ZNSt11logic_errorC1ERKSs>: + 1009170: deffed04 addi sp,sp,-76 + 1009174: 00804034 movhi r2,256 + 1009178: 109a9704 addi r2,r2,27228 + 100917c: 00c040b4 movhi r3,258 + 1009180: 18c364c4 addi r3,r3,3475 + 1009184: d8800615 stw r2,24(sp) + 1009188: d9000d15 stw r4,52(sp) + 100918c: 00804074 movhi r2,257 + 1009190: 10a48004 addi r2,r2,-28160 + 1009194: d809883a mov r4,sp + 1009198: d8c00715 stw r3,28(sp) + 100919c: d8800915 stw r2,36(sp) + 10091a0: d9400e15 stw r5,56(sp) + 10091a4: dfc01215 stw ra,72(sp) + 10091a8: df001115 stw fp,68(sp) + 10091ac: ddc01015 stw r23,64(sp) + 10091b0: dec00815 stw sp,32(sp) + 10091b4: dec00a15 stw sp,40(sp) + 10091b8: 1009c1c0 call 1009c1c <_Unwind_SjLj_Register> + 10091bc: d8c00d17 ldw r3,52(sp) + 10091c0: 008040b4 movhi r2,258 + 10091c4: 1084e304 addi r2,r2,5004 + 10091c8: d9400e17 ldw r5,56(sp) + 10091cc: 18800015 stw r2,0(r3) + 10091d0: d8800d17 ldw r2,52(sp) + 10091d4: 00c00044 movi r3,1 + 10091d8: d8c00115 stw r3,4(sp) + 10091dc: 11000104 addi r4,r2,4 + 10091e0: 10040640 call 1004064 <_ZNSsC1ERKSs> + 10091e4: d809883a mov r4,sp + 10091e8: 1009c2c0 call 1009c2c <_Unwind_SjLj_Unregister> + 10091ec: dfc01217 ldw ra,72(sp) + 10091f0: df001117 ldw fp,68(sp) + 10091f4: ddc01017 ldw r23,64(sp) + 10091f8: dec01304 addi sp,sp,76 + 10091fc: f800283a ret + 1009200: d8c00217 ldw r3,8(sp) + 1009204: d9000d17 ldw r4,52(sp) + 1009208: d8c00f15 stw r3,60(sp) + 100920c: 1009a5c0 call 1009a5c <_ZNSt9exceptionD2Ev> + 1009210: d9000f17 ldw r4,60(sp) + 1009214: 00bfffc4 movi r2,-1 + 1009218: d8800115 stw r2,4(sp) + 100921c: 1009ee80 call 1009ee8 <_Unwind_SjLj_Resume> + +01009220 <_ZNSt11logic_errorC2ERKSs>: + 1009220: deffed04 addi sp,sp,-76 + 1009224: 00804034 movhi r2,256 + 1009228: 109a9704 addi r2,r2,27228 + 100922c: 00c040b4 movhi r3,258 + 1009230: 18c36644 addi r3,r3,3481 + 1009234: d8800615 stw r2,24(sp) + 1009238: d9000d15 stw r4,52(sp) + 100923c: 00804074 movhi r2,257 + 1009240: 10a4ac04 addi r2,r2,-27984 + 1009244: d809883a mov r4,sp + 1009248: d8c00715 stw r3,28(sp) + 100924c: d8800915 stw r2,36(sp) + 1009250: d9400e15 stw r5,56(sp) + 1009254: dfc01215 stw ra,72(sp) + 1009258: df001115 stw fp,68(sp) + 100925c: ddc01015 stw r23,64(sp) + 1009260: dec00815 stw sp,32(sp) + 1009264: dec00a15 stw sp,40(sp) + 1009268: 1009c1c0 call 1009c1c <_Unwind_SjLj_Register> + 100926c: d8c00d17 ldw r3,52(sp) + 1009270: 008040b4 movhi r2,258 + 1009274: 1084e304 addi r2,r2,5004 + 1009278: d9400e17 ldw r5,56(sp) + 100927c: 18800015 stw r2,0(r3) + 1009280: d8800d17 ldw r2,52(sp) + 1009284: 00c00044 movi r3,1 + 1009288: d8c00115 stw r3,4(sp) + 100928c: 11000104 addi r4,r2,4 + 1009290: 10040640 call 1004064 <_ZNSsC1ERKSs> + 1009294: d809883a mov r4,sp + 1009298: 1009c2c0 call 1009c2c <_Unwind_SjLj_Unregister> + 100929c: dfc01217 ldw ra,72(sp) + 10092a0: df001117 ldw fp,68(sp) + 10092a4: ddc01017 ldw r23,64(sp) + 10092a8: dec01304 addi sp,sp,76 + 10092ac: f800283a ret + 10092b0: d8c00217 ldw r3,8(sp) + 10092b4: d9000d17 ldw r4,52(sp) + 10092b8: d8c00f15 stw r3,60(sp) + 10092bc: 1009a5c0 call 1009a5c <_ZNSt9exceptionD2Ev> + 10092c0: d9000f17 ldw r4,60(sp) + 10092c4: 00bfffc4 movi r2,-1 + 10092c8: d8800115 stw r2,4(sp) + 10092cc: 1009ee80 call 1009ee8 <_Unwind_SjLj_Resume> + +010092d0 <_ZNSt12out_of_rangeC1ERKSs>: + 10092d0: defffe04 addi sp,sp,-8 + 10092d4: dc000015 stw r16,0(sp) + 10092d8: dfc00115 stw ra,4(sp) + 10092dc: 2021883a mov r16,r4 + 10092e0: 10092200 call 1009220 <_ZNSt11logic_errorC2ERKSs> + 10092e4: 008040b4 movhi r2,258 + 10092e8: 1084a304 addi r2,r2,4748 + 10092ec: 80800015 stw r2,0(r16) + 10092f0: dfc00117 ldw ra,4(sp) + 10092f4: dc000017 ldw r16,0(sp) + 10092f8: dec00204 addi sp,sp,8 + 10092fc: f800283a ret + +01009300 <_ZNSt12out_of_rangeC2ERKSs>: + 1009300: defffe04 addi sp,sp,-8 + 1009304: dc000015 stw r16,0(sp) + 1009308: dfc00115 stw ra,4(sp) + 100930c: 2021883a mov r16,r4 + 1009310: 10092200 call 1009220 <_ZNSt11logic_errorC2ERKSs> + 1009314: 008040b4 movhi r2,258 + 1009318: 1084a304 addi r2,r2,4748 + 100931c: 80800015 stw r2,0(r16) + 1009320: dfc00117 ldw ra,4(sp) + 1009324: dc000017 ldw r16,0(sp) + 1009328: dec00204 addi sp,sp,8 + 100932c: f800283a ret + +01009330 <_ZNSt12length_errorC1ERKSs>: + 1009330: defffe04 addi sp,sp,-8 + 1009334: dc000015 stw r16,0(sp) + 1009338: dfc00115 stw ra,4(sp) + 100933c: 2021883a mov r16,r4 + 1009340: 10092200 call 1009220 <_ZNSt11logic_errorC2ERKSs> + 1009344: 008040b4 movhi r2,258 + 1009348: 1084b004 addi r2,r2,4800 + 100934c: 80800015 stw r2,0(r16) + 1009350: dfc00117 ldw ra,4(sp) + 1009354: dc000017 ldw r16,0(sp) + 1009358: dec00204 addi sp,sp,8 + 100935c: f800283a ret + +01009360 <_ZNSt12length_errorC2ERKSs>: + 1009360: defffe04 addi sp,sp,-8 + 1009364: dc000015 stw r16,0(sp) + 1009368: dfc00115 stw ra,4(sp) + 100936c: 2021883a mov r16,r4 + 1009370: 10092200 call 1009220 <_ZNSt11logic_errorC2ERKSs> + 1009374: 008040b4 movhi r2,258 + 1009378: 1084b004 addi r2,r2,4800 + 100937c: 80800015 stw r2,0(r16) + 1009380: dfc00117 ldw ra,4(sp) + 1009384: dc000017 ldw r16,0(sp) + 1009388: dec00204 addi sp,sp,8 + 100938c: f800283a ret + +01009390 <_ZNSt16invalid_argumentC1ERKSs>: + 1009390: defffe04 addi sp,sp,-8 + 1009394: dc000015 stw r16,0(sp) + 1009398: dfc00115 stw ra,4(sp) + 100939c: 2021883a mov r16,r4 + 10093a0: 10092200 call 1009220 <_ZNSt11logic_errorC2ERKSs> + 10093a4: 008040b4 movhi r2,258 + 10093a8: 1084be04 addi r2,r2,4856 + 10093ac: 80800015 stw r2,0(r16) + 10093b0: dfc00117 ldw ra,4(sp) + 10093b4: dc000017 ldw r16,0(sp) + 10093b8: dec00204 addi sp,sp,8 + 10093bc: f800283a ret + +010093c0 <_ZNSt16invalid_argumentC2ERKSs>: + 10093c0: defffe04 addi sp,sp,-8 + 10093c4: dc000015 stw r16,0(sp) + 10093c8: dfc00115 stw ra,4(sp) + 10093cc: 2021883a mov r16,r4 + 10093d0: 10092200 call 1009220 <_ZNSt11logic_errorC2ERKSs> + 10093d4: 008040b4 movhi r2,258 + 10093d8: 1084be04 addi r2,r2,4856 + 10093dc: 80800015 stw r2,0(r16) + 10093e0: dfc00117 ldw ra,4(sp) + 10093e4: dc000017 ldw r16,0(sp) + 10093e8: dec00204 addi sp,sp,8 + 10093ec: f800283a ret + +010093f0 <_ZNSt12domain_errorC1ERKSs>: + 10093f0: defffe04 addi sp,sp,-8 + 10093f4: dc000015 stw r16,0(sp) + 10093f8: dfc00115 stw ra,4(sp) + 10093fc: 2021883a mov r16,r4 + 1009400: 10092200 call 1009220 <_ZNSt11logic_errorC2ERKSs> + 1009404: 008040b4 movhi r2,258 + 1009408: 1084cb04 addi r2,r2,4908 + 100940c: 80800015 stw r2,0(r16) + 1009410: dfc00117 ldw ra,4(sp) + 1009414: dc000017 ldw r16,0(sp) + 1009418: dec00204 addi sp,sp,8 + 100941c: f800283a ret + +01009420 <_ZNSt12domain_errorC2ERKSs>: + 1009420: defffe04 addi sp,sp,-8 + 1009424: dc000015 stw r16,0(sp) + 1009428: dfc00115 stw ra,4(sp) + 100942c: 2021883a mov r16,r4 + 1009430: 10092200 call 1009220 <_ZNSt11logic_errorC2ERKSs> + 1009434: 008040b4 movhi r2,258 + 1009438: 1084cb04 addi r2,r2,4908 + 100943c: 80800015 stw r2,0(r16) + 1009440: dfc00117 ldw ra,4(sp) + 1009444: dc000017 ldw r16,0(sp) + 1009448: dec00204 addi sp,sp,8 + 100944c: f800283a ret + +01009450 <_ZNKSt11logic_error4whatEv>: + 1009450: 20800117 ldw r2,4(r4) + 1009454: f800283a ret + +01009458 <_ZNSt13runtime_errorC1ERKSs>: + 1009458: deffed04 addi sp,sp,-76 + 100945c: 00804034 movhi r2,256 + 1009460: 109a9704 addi r2,r2,27228 + 1009464: 00c040b4 movhi r3,258 + 1009468: 18c367c4 addi r3,r3,3487 + 100946c: d8800615 stw r2,24(sp) + 1009470: d9000d15 stw r4,52(sp) + 1009474: 00804074 movhi r2,257 + 1009478: 10a53a04 addi r2,r2,-27416 + 100947c: d809883a mov r4,sp + 1009480: d8c00715 stw r3,28(sp) + 1009484: d8800915 stw r2,36(sp) + 1009488: d9400e15 stw r5,56(sp) + 100948c: dfc01215 stw ra,72(sp) + 1009490: df001115 stw fp,68(sp) + 1009494: ddc01015 stw r23,64(sp) + 1009498: dec00815 stw sp,32(sp) + 100949c: dec00a15 stw sp,40(sp) + 10094a0: 1009c1c0 call 1009c1c <_Unwind_SjLj_Register> + 10094a4: d8c00d17 ldw r3,52(sp) + 10094a8: 008040b4 movhi r2,258 + 10094ac: 1084de04 addi r2,r2,4984 + 10094b0: d9400e17 ldw r5,56(sp) + 10094b4: 18800015 stw r2,0(r3) + 10094b8: d8800d17 ldw r2,52(sp) + 10094bc: 00c00044 movi r3,1 + 10094c0: d8c00115 stw r3,4(sp) + 10094c4: 11000104 addi r4,r2,4 + 10094c8: 10040640 call 1004064 <_ZNSsC1ERKSs> + 10094cc: d809883a mov r4,sp + 10094d0: 1009c2c0 call 1009c2c <_Unwind_SjLj_Unregister> + 10094d4: dfc01217 ldw ra,72(sp) + 10094d8: df001117 ldw fp,68(sp) + 10094dc: ddc01017 ldw r23,64(sp) + 10094e0: dec01304 addi sp,sp,76 + 10094e4: f800283a ret + 10094e8: d8c00217 ldw r3,8(sp) + 10094ec: d9000d17 ldw r4,52(sp) + 10094f0: d8c00f15 stw r3,60(sp) + 10094f4: 1009a5c0 call 1009a5c <_ZNSt9exceptionD2Ev> + 10094f8: d9000f17 ldw r4,60(sp) + 10094fc: 00bfffc4 movi r2,-1 + 1009500: d8800115 stw r2,4(sp) + 1009504: 1009ee80 call 1009ee8 <_Unwind_SjLj_Resume> + +01009508 <_ZNSt13runtime_errorD1Ev>: + 1009508: deffeb04 addi sp,sp,-84 + 100950c: 00804034 movhi r2,256 + 1009510: 109a9704 addi r2,r2,27228 + 1009514: 00c040b4 movhi r3,258 + 1009518: 18c36a04 addi r3,r3,3496 + 100951c: d8800715 stw r2,28(sp) + 1009520: d9001015 stw r4,64(sp) + 1009524: 00804074 movhi r2,257 + 1009528: 10a57304 addi r2,r2,-27188 + 100952c: d9000104 addi r4,sp,4 + 1009530: d8c00815 stw r3,32(sp) + 1009534: d8800a15 stw r2,40(sp) + 1009538: dfc01415 stw ra,80(sp) + 100953c: df001315 stw fp,76(sp) + 1009540: ddc01215 stw r23,72(sp) + 1009544: dec00915 stw sp,36(sp) + 1009548: dec00b15 stw sp,44(sp) + 100954c: 1009c1c0 call 1009c1c <_Unwind_SjLj_Register> + 1009550: d8c01017 ldw r3,64(sp) + 1009554: 18800117 ldw r2,4(r3) + 1009558: 00c040b4 movhi r3,258 + 100955c: 18c4de04 addi r3,r3,4984 + 1009560: 10bffd04 addi r2,r2,-12 + 1009564: d8800e15 stw r2,56(sp) + 1009568: d8801017 ldw r2,64(sp) + 100956c: 10c00015 stw r3,0(r2) + 1009570: d8c00e17 ldw r3,56(sp) + 1009574: 008040f4 movhi r2,259 + 1009578: 10a52f04 addi r2,r2,-27460 + 100957c: 1880091e bne r3,r2,10095a4 <_ZNSt13runtime_errorD1Ev+0x9c> + 1009580: d9001017 ldw r4,64(sp) + 1009584: 1009a5c0 call 1009a5c <_ZNSt9exceptionD2Ev> + 1009588: d9000104 addi r4,sp,4 + 100958c: 1009c2c0 call 1009c2c <_Unwind_SjLj_Unregister> + 1009590: dfc01417 ldw ra,80(sp) + 1009594: df001317 ldw fp,76(sp) + 1009598: ddc01217 ldw r23,72(sp) + 100959c: dec01504 addi sp,sp,84 + 10095a0: f800283a ret + 10095a4: 00800044 movi r2,1 + 10095a8: d8800215 stw r2,8(sp) + 10095ac: 19000204 addi r4,r3,8 + 10095b0: 017fffc4 movi r5,-1 + 10095b4: 100617c0 call 100617c <_ZN9__gnu_cxx18__exchange_and_addEPVii> + 10095b8: 00bff116 blt zero,r2,1009580 <_ZNSt13runtime_errorD1Ev+0x78> + 10095bc: d9000e17 ldw r4,56(sp) + 10095c0: d80b883a mov r5,sp + 10095c4: 1002c0c0 call 1002c0c <_ZNSs4_Rep10_M_destroyERKSaIcE> + 10095c8: 003fed06 br 1009580 <_ZNSt13runtime_errorD1Ev+0x78> + 10095cc: d8800417 ldw r2,16(sp) + 10095d0: d8c00317 ldw r3,12(sp) + 10095d4: d9001017 ldw r4,64(sp) + 10095d8: d8800f15 stw r2,60(sp) + 10095dc: d8c01115 stw r3,68(sp) + 10095e0: 1009a5c0 call 1009a5c <_ZNSt9exceptionD2Ev> + 10095e4: d8c00f17 ldw r3,60(sp) + 10095e8: 00bfffc4 movi r2,-1 + 10095ec: 18800326 beq r3,r2,10095fc <_ZNSt13runtime_errorD1Ev+0xf4> + 10095f0: d9001117 ldw r4,68(sp) + 10095f4: d8800215 stw r2,8(sp) + 10095f8: 1009ee80 call 1009ee8 <_Unwind_SjLj_Resume> + 10095fc: d9001117 ldw r4,68(sp) + 1009600: 00bfffc4 movi r2,-1 + 1009604: d8800215 stw r2,8(sp) + 1009608: 10068dc0 call 10068dc <__cxa_call_unexpected> + +0100960c <_ZNSt13runtime_errorD2Ev>: + 100960c: deffeb04 addi sp,sp,-84 + 1009610: 00804034 movhi r2,256 + 1009614: 109a9704 addi r2,r2,27228 + 1009618: 00c040b4 movhi r3,258 + 100961c: 18c36e04 addi r3,r3,3512 + 1009620: d8800715 stw r2,28(sp) + 1009624: d9001015 stw r4,64(sp) + 1009628: 00804074 movhi r2,257 + 100962c: 10a5b404 addi r2,r2,-26928 + 1009630: d9000104 addi r4,sp,4 + 1009634: d8c00815 stw r3,32(sp) + 1009638: d8800a15 stw r2,40(sp) + 100963c: dfc01415 stw ra,80(sp) + 1009640: df001315 stw fp,76(sp) + 1009644: ddc01215 stw r23,72(sp) + 1009648: dec00915 stw sp,36(sp) + 100964c: dec00b15 stw sp,44(sp) + 1009650: 1009c1c0 call 1009c1c <_Unwind_SjLj_Register> + 1009654: d8c01017 ldw r3,64(sp) + 1009658: 18800117 ldw r2,4(r3) + 100965c: 00c040b4 movhi r3,258 + 1009660: 18c4de04 addi r3,r3,4984 + 1009664: 10bffd04 addi r2,r2,-12 + 1009668: d8800e15 stw r2,56(sp) + 100966c: d8801017 ldw r2,64(sp) + 1009670: 10c00015 stw r3,0(r2) + 1009674: d8c00e17 ldw r3,56(sp) + 1009678: 008040f4 movhi r2,259 + 100967c: 10a52f04 addi r2,r2,-27460 + 1009680: 1880091e bne r3,r2,10096a8 <_ZNSt13runtime_errorD2Ev+0x9c> + 1009684: d9001017 ldw r4,64(sp) + 1009688: 1009a5c0 call 1009a5c <_ZNSt9exceptionD2Ev> + 100968c: d9000104 addi r4,sp,4 + 1009690: 1009c2c0 call 1009c2c <_Unwind_SjLj_Unregister> + 1009694: dfc01417 ldw ra,80(sp) + 1009698: df001317 ldw fp,76(sp) + 100969c: ddc01217 ldw r23,72(sp) + 10096a0: dec01504 addi sp,sp,84 + 10096a4: f800283a ret + 10096a8: 00800044 movi r2,1 + 10096ac: d8800215 stw r2,8(sp) + 10096b0: 19000204 addi r4,r3,8 + 10096b4: 017fffc4 movi r5,-1 + 10096b8: 100617c0 call 100617c <_ZN9__gnu_cxx18__exchange_and_addEPVii> + 10096bc: 00bff116 blt zero,r2,1009684 <_ZNSt13runtime_errorD2Ev+0x78> + 10096c0: d9000e17 ldw r4,56(sp) + 10096c4: d80b883a mov r5,sp + 10096c8: 1002c0c0 call 1002c0c <_ZNSs4_Rep10_M_destroyERKSaIcE> + 10096cc: 003fed06 br 1009684 <_ZNSt13runtime_errorD2Ev+0x78> + 10096d0: d8800417 ldw r2,16(sp) + 10096d4: d8c00317 ldw r3,12(sp) + 10096d8: d9001017 ldw r4,64(sp) + 10096dc: d8800f15 stw r2,60(sp) + 10096e0: d8c01115 stw r3,68(sp) + 10096e4: 1009a5c0 call 1009a5c <_ZNSt9exceptionD2Ev> + 10096e8: d8c00f17 ldw r3,60(sp) + 10096ec: 00bfffc4 movi r2,-1 + 10096f0: 18800326 beq r3,r2,1009700 <_ZNSt13runtime_errorD2Ev+0xf4> + 10096f4: d9001117 ldw r4,68(sp) + 10096f8: d8800215 stw r2,8(sp) + 10096fc: 1009ee80 call 1009ee8 <_Unwind_SjLj_Resume> + 1009700: d9001117 ldw r4,68(sp) + 1009704: 00bfffc4 movi r2,-1 + 1009708: d8800215 stw r2,8(sp) + 100970c: 10068dc0 call 10068dc <__cxa_call_unexpected> + +01009710 <_ZNSt13runtime_errorD0Ev>: + 1009710: deffeb04 addi sp,sp,-84 + 1009714: 00804034 movhi r2,256 + 1009718: 109a9704 addi r2,r2,27228 + 100971c: 00c040b4 movhi r3,258 + 1009720: 18c37204 addi r3,r3,3528 + 1009724: d8800715 stw r2,28(sp) + 1009728: d9001015 stw r4,64(sp) + 100972c: 00804074 movhi r2,257 + 1009730: 10a5f704 addi r2,r2,-26660 + 1009734: d9000104 addi r4,sp,4 + 1009738: d8c00815 stw r3,32(sp) + 100973c: d8800a15 stw r2,40(sp) + 1009740: dfc01415 stw ra,80(sp) + 1009744: df001315 stw fp,76(sp) + 1009748: ddc01215 stw r23,72(sp) + 100974c: dec00915 stw sp,36(sp) + 1009750: dec00b15 stw sp,44(sp) + 1009754: 1009c1c0 call 1009c1c <_Unwind_SjLj_Register> + 1009758: d8c01017 ldw r3,64(sp) + 100975c: 18800117 ldw r2,4(r3) + 1009760: 00c040b4 movhi r3,258 + 1009764: 18c4de04 addi r3,r3,4984 + 1009768: 10bffd04 addi r2,r2,-12 + 100976c: d8800e15 stw r2,56(sp) + 1009770: d8801017 ldw r2,64(sp) + 1009774: 10c00015 stw r3,0(r2) + 1009778: d8c00e17 ldw r3,56(sp) + 100977c: 008040f4 movhi r2,259 + 1009780: 10a52f04 addi r2,r2,-27460 + 1009784: 18800b1e bne r3,r2,10097b4 <_ZNSt13runtime_errorD0Ev+0xa4> + 1009788: d9001017 ldw r4,64(sp) + 100978c: 1009a5c0 call 1009a5c <_ZNSt9exceptionD2Ev> + 1009790: d9001017 ldw r4,64(sp) + 1009794: 100722c0 call 100722c <_ZdlPv> + 1009798: d9000104 addi r4,sp,4 + 100979c: 1009c2c0 call 1009c2c <_Unwind_SjLj_Unregister> + 10097a0: dfc01417 ldw ra,80(sp) + 10097a4: df001317 ldw fp,76(sp) + 10097a8: ddc01217 ldw r23,72(sp) + 10097ac: dec01504 addi sp,sp,84 + 10097b0: f800283a ret + 10097b4: 00800044 movi r2,1 + 10097b8: d8800215 stw r2,8(sp) + 10097bc: 19000204 addi r4,r3,8 + 10097c0: 017fffc4 movi r5,-1 + 10097c4: 100617c0 call 100617c <_ZN9__gnu_cxx18__exchange_and_addEPVii> + 10097c8: 00bfef16 blt zero,r2,1009788 <_ZNSt13runtime_errorD0Ev+0x78> + 10097cc: d9000e17 ldw r4,56(sp) + 10097d0: d80b883a mov r5,sp + 10097d4: 1002c0c0 call 1002c0c <_ZNSs4_Rep10_M_destroyERKSaIcE> + 10097d8: 003feb06 br 1009788 <_ZNSt13runtime_errorD0Ev+0x78> + 10097dc: d8800417 ldw r2,16(sp) + 10097e0: d8c00317 ldw r3,12(sp) + 10097e4: d9001017 ldw r4,64(sp) + 10097e8: d8800f15 stw r2,60(sp) + 10097ec: d8c01115 stw r3,68(sp) + 10097f0: 1009a5c0 call 1009a5c <_ZNSt9exceptionD2Ev> + 10097f4: d8c00f17 ldw r3,60(sp) + 10097f8: 00bfffc4 movi r2,-1 + 10097fc: 18800326 beq r3,r2,100980c <_ZNSt13runtime_errorD0Ev+0xfc> + 1009800: d9001117 ldw r4,68(sp) + 1009804: d8800215 stw r2,8(sp) + 1009808: 1009ee80 call 1009ee8 <_Unwind_SjLj_Resume> + 100980c: d9001117 ldw r4,68(sp) + 1009810: 00bfffc4 movi r2,-1 + 1009814: d8800215 stw r2,8(sp) + 1009818: 10068dc0 call 10068dc <__cxa_call_unexpected> + +0100981c <_ZNSt11logic_errorD2Ev>: + 100981c: deffeb04 addi sp,sp,-84 + 1009820: 00804034 movhi r2,256 + 1009824: 109a9704 addi r2,r2,27228 + 1009828: 00c040b4 movhi r3,258 + 100982c: 18c37604 addi r3,r3,3544 + 1009830: d8800715 stw r2,28(sp) + 1009834: d9001015 stw r4,64(sp) + 1009838: 00804074 movhi r2,257 + 100983c: 10a63804 addi r2,r2,-26400 + 1009840: d9000104 addi r4,sp,4 + 1009844: d8c00815 stw r3,32(sp) + 1009848: d8800a15 stw r2,40(sp) + 100984c: dfc01415 stw ra,80(sp) + 1009850: df001315 stw fp,76(sp) + 1009854: ddc01215 stw r23,72(sp) + 1009858: dec00915 stw sp,36(sp) + 100985c: dec00b15 stw sp,44(sp) + 1009860: 1009c1c0 call 1009c1c <_Unwind_SjLj_Register> + 1009864: d8c01017 ldw r3,64(sp) + 1009868: 18800117 ldw r2,4(r3) + 100986c: 00c040b4 movhi r3,258 + 1009870: 18c4e304 addi r3,r3,5004 + 1009874: 10bffd04 addi r2,r2,-12 + 1009878: d8800e15 stw r2,56(sp) + 100987c: d8801017 ldw r2,64(sp) + 1009880: 10c00015 stw r3,0(r2) + 1009884: d8c00e17 ldw r3,56(sp) + 1009888: 008040f4 movhi r2,259 + 100988c: 10a52f04 addi r2,r2,-27460 + 1009890: 1880091e bne r3,r2,10098b8 <_ZNSt11logic_errorD2Ev+0x9c> + 1009894: d9001017 ldw r4,64(sp) + 1009898: 1009a5c0 call 1009a5c <_ZNSt9exceptionD2Ev> + 100989c: d9000104 addi r4,sp,4 + 10098a0: 1009c2c0 call 1009c2c <_Unwind_SjLj_Unregister> + 10098a4: dfc01417 ldw ra,80(sp) + 10098a8: df001317 ldw fp,76(sp) + 10098ac: ddc01217 ldw r23,72(sp) + 10098b0: dec01504 addi sp,sp,84 + 10098b4: f800283a ret + 10098b8: 00800044 movi r2,1 + 10098bc: d8800215 stw r2,8(sp) + 10098c0: 19000204 addi r4,r3,8 + 10098c4: 017fffc4 movi r5,-1 + 10098c8: 100617c0 call 100617c <_ZN9__gnu_cxx18__exchange_and_addEPVii> + 10098cc: 00bff116 blt zero,r2,1009894 <_ZNSt11logic_errorD2Ev+0x78> + 10098d0: d9000e17 ldw r4,56(sp) + 10098d4: d80b883a mov r5,sp + 10098d8: 1002c0c0 call 1002c0c <_ZNSs4_Rep10_M_destroyERKSaIcE> + 10098dc: 003fed06 br 1009894 <_ZNSt11logic_errorD2Ev+0x78> + 10098e0: d8800417 ldw r2,16(sp) + 10098e4: d8c00317 ldw r3,12(sp) + 10098e8: d9001017 ldw r4,64(sp) + 10098ec: d8800f15 stw r2,60(sp) + 10098f0: d8c01115 stw r3,68(sp) + 10098f4: 1009a5c0 call 1009a5c <_ZNSt9exceptionD2Ev> + 10098f8: d8c00f17 ldw r3,60(sp) + 10098fc: 00bfffc4 movi r2,-1 + 1009900: 18800326 beq r3,r2,1009910 <_ZNSt11logic_errorD2Ev+0xf4> + 1009904: d9001117 ldw r4,68(sp) + 1009908: d8800215 stw r2,8(sp) + 100990c: 1009ee80 call 1009ee8 <_Unwind_SjLj_Resume> + 1009910: d9001117 ldw r4,68(sp) + 1009914: 00bfffc4 movi r2,-1 + 1009918: d8800215 stw r2,8(sp) + 100991c: 10068dc0 call 10068dc <__cxa_call_unexpected> + +01009920 <_ZNSt11logic_errorD0Ev>: + 1009920: deffeb04 addi sp,sp,-84 + 1009924: 00804034 movhi r2,256 + 1009928: 109a9704 addi r2,r2,27228 + 100992c: 00c040b4 movhi r3,258 + 1009930: 18c37a04 addi r3,r3,3560 + 1009934: d8800715 stw r2,28(sp) + 1009938: d9001015 stw r4,64(sp) + 100993c: 00804074 movhi r2,257 + 1009940: 10a67b04 addi r2,r2,-26132 + 1009944: d9000104 addi r4,sp,4 + 1009948: d8c00815 stw r3,32(sp) + 100994c: d8800a15 stw r2,40(sp) + 1009950: dfc01415 stw ra,80(sp) + 1009954: df001315 stw fp,76(sp) + 1009958: ddc01215 stw r23,72(sp) + 100995c: dec00915 stw sp,36(sp) + 1009960: dec00b15 stw sp,44(sp) + 1009964: 1009c1c0 call 1009c1c <_Unwind_SjLj_Register> + 1009968: d8c01017 ldw r3,64(sp) + 100996c: 18800117 ldw r2,4(r3) + 1009970: 00c040b4 movhi r3,258 + 1009974: 18c4e304 addi r3,r3,5004 + 1009978: 10bffd04 addi r2,r2,-12 + 100997c: d8800e15 stw r2,56(sp) + 1009980: d8801017 ldw r2,64(sp) + 1009984: 10c00015 stw r3,0(r2) + 1009988: d8c00e17 ldw r3,56(sp) + 100998c: 008040f4 movhi r2,259 + 1009990: 10a52f04 addi r2,r2,-27460 + 1009994: 18800b1e bne r3,r2,10099c4 <_ZNSt11logic_errorD0Ev+0xa4> + 1009998: d9001017 ldw r4,64(sp) + 100999c: 1009a5c0 call 1009a5c <_ZNSt9exceptionD2Ev> + 10099a0: d9001017 ldw r4,64(sp) + 10099a4: 100722c0 call 100722c <_ZdlPv> + 10099a8: d9000104 addi r4,sp,4 + 10099ac: 1009c2c0 call 1009c2c <_Unwind_SjLj_Unregister> + 10099b0: dfc01417 ldw ra,80(sp) + 10099b4: df001317 ldw fp,76(sp) + 10099b8: ddc01217 ldw r23,72(sp) + 10099bc: dec01504 addi sp,sp,84 + 10099c0: f800283a ret + 10099c4: 00800044 movi r2,1 + 10099c8: d8800215 stw r2,8(sp) + 10099cc: 19000204 addi r4,r3,8 + 10099d0: 017fffc4 movi r5,-1 + 10099d4: 100617c0 call 100617c <_ZN9__gnu_cxx18__exchange_and_addEPVii> + 10099d8: 00bfef16 blt zero,r2,1009998 <_ZNSt11logic_errorD0Ev+0x78> + 10099dc: d9000e17 ldw r4,56(sp) + 10099e0: d80b883a mov r5,sp + 10099e4: 1002c0c0 call 1002c0c <_ZNSs4_Rep10_M_destroyERKSaIcE> + 10099e8: 003feb06 br 1009998 <_ZNSt11logic_errorD0Ev+0x78> + 10099ec: d8800417 ldw r2,16(sp) + 10099f0: d8c00317 ldw r3,12(sp) + 10099f4: d9001017 ldw r4,64(sp) + 10099f8: d8800f15 stw r2,60(sp) + 10099fc: d8c01115 stw r3,68(sp) + 1009a00: 1009a5c0 call 1009a5c <_ZNSt9exceptionD2Ev> + 1009a04: d8c00f17 ldw r3,60(sp) + 1009a08: 00bfffc4 movi r2,-1 + 1009a0c: 18800326 beq r3,r2,1009a1c <_ZNSt11logic_errorD0Ev+0xfc> + 1009a10: d9001117 ldw r4,68(sp) + 1009a14: d8800215 stw r2,8(sp) + 1009a18: 1009ee80 call 1009ee8 <_Unwind_SjLj_Resume> + 1009a1c: d9001117 ldw r4,68(sp) + 1009a20: 00bfffc4 movi r2,-1 + 1009a24: d8800215 stw r2,8(sp) + 1009a28: 10068dc0 call 10068dc <__cxa_call_unexpected> + +01009a2c <_ZNKSt9exception4whatEv>: + 1009a2c: 20800017 ldw r2,0(r4) + 1009a30: 10ffff17 ldw r3,-4(r2) + 1009a34: 18800117 ldw r2,4(r3) + 1009a38: f800283a ret + +01009a3c <_ZNSt9exceptionD0Ev>: + 1009a3c: 008040b4 movhi r2,258 + 1009a40: 1084fc04 addi r2,r2,5104 + 1009a44: 20800015 stw r2,0(r4) + 1009a48: 100722c1 jmpi 100722c <_ZdlPv> + +01009a4c <_ZNSt9exceptionD1Ev>: + 1009a4c: 008040b4 movhi r2,258 + 1009a50: 1084fc04 addi r2,r2,5104 + 1009a54: 20800015 stw r2,0(r4) + 1009a58: f800283a ret + +01009a5c <_ZNSt9exceptionD2Ev>: + 1009a5c: 008040b4 movhi r2,258 + 1009a60: 1084fc04 addi r2,r2,5104 + 1009a64: 20800015 stw r2,0(r4) + 1009a68: f800283a ret + +01009a6c <_ZNSt13bad_exceptionD0Ev>: + 1009a6c: defffe04 addi sp,sp,-8 + 1009a70: 008040b4 movhi r2,258 + 1009a74: 1084f704 addi r2,r2,5084 + 1009a78: dc400015 stw r17,0(sp) + 1009a7c: 20800015 stw r2,0(r4) + 1009a80: 2023883a mov r17,r4 + 1009a84: dfc00115 stw ra,4(sp) + 1009a88: 1009a5c0 call 1009a5c <_ZNSt9exceptionD2Ev> + 1009a8c: 8809883a mov r4,r17 + 1009a90: dfc00117 ldw ra,4(sp) + 1009a94: dc400017 ldw r17,0(sp) + 1009a98: dec00204 addi sp,sp,8 + 1009a9c: 100722c1 jmpi 100722c <_ZdlPv> + +01009aa0 <_ZNSt13bad_exceptionD1Ev>: + 1009aa0: 008040b4 movhi r2,258 + 1009aa4: 1084f704 addi r2,r2,5084 + 1009aa8: 20800015 stw r2,0(r4) + 1009aac: 1009a5c1 jmpi 1009a5c <_ZNSt9exceptionD2Ev> + +01009ab0 <_ZNSt13bad_exceptionD2Ev>: + 1009ab0: 008040b4 movhi r2,258 + 1009ab4: 1084f704 addi r2,r2,5084 + 1009ab8: 20800015 stw r2,0(r4) + 1009abc: 1009a5c1 jmpi 1009a5c <_ZNSt9exceptionD2Ev> + +01009ac0 <__cxa_call_terminate>: + 1009ac0: defffe04 addi sp,sp,-8 + 1009ac4: dc000015 stw r16,0(sp) + 1009ac8: dfc00115 stw ra,4(sp) + 1009acc: 2021883a mov r16,r4 + 1009ad0: 20000626 beq r4,zero,1009aec <__cxa_call_terminate+0x2c> + 1009ad4: 10071140 call 1007114 <__cxa_begin_catch> + 1009ad8: 80c00017 ldw r3,0(r16) + 1009adc: 0090caf4 movhi r2,17195 + 1009ae0: 108ac004 addi r2,r2,11008 + 1009ae4: 81000117 ldw r4,4(r16) + 1009ae8: 18800126 beq r3,r2,1009af0 <__cxa_call_terminate+0x30> + 1009aec: 10070080 call 1007008 <_ZSt9terminatev> + 1009af0: 0091d3b4 movhi r2,18254 + 1009af4: 109550c4 addi r2,r2,21827 + 1009af8: 20bffc1e bne r4,r2,1009aec <__cxa_call_terminate+0x2c> + 1009afc: 813ff817 ldw r4,-32(r16) + 1009b00: 1006f640 call 1006f64 <_ZN10__cxxabiv111__terminateEPFvvE> + +01009b04 <_ZSt15set_new_handlerPFvvE>: + 1009b04: d0a74817 ldw r2,-25312(gp) + 1009b08: d1274815 stw r4,-25312(gp) + 1009b0c: f800283a ret + +01009b10 <_ZNSt9bad_allocD0Ev>: + 1009b10: defffe04 addi sp,sp,-8 + 1009b14: 008040b4 movhi r2,258 + 1009b18: 10850d04 addi r2,r2,5172 + 1009b1c: dc400015 stw r17,0(sp) + 1009b20: 20800015 stw r2,0(r4) + 1009b24: 2023883a mov r17,r4 + 1009b28: dfc00115 stw ra,4(sp) + 1009b2c: 1009a5c0 call 1009a5c <_ZNSt9exceptionD2Ev> + 1009b30: 8809883a mov r4,r17 + 1009b34: dfc00117 ldw ra,4(sp) + 1009b38: dc400017 ldw r17,0(sp) + 1009b3c: dec00204 addi sp,sp,8 + 1009b40: 100722c1 jmpi 100722c <_ZdlPv> + +01009b44 <_ZNSt9bad_allocD1Ev>: + 1009b44: 008040b4 movhi r2,258 + 1009b48: 10850d04 addi r2,r2,5172 + 1009b4c: 20800015 stw r2,0(r4) + 1009b50: 1009a5c1 jmpi 1009a5c <_ZNSt9exceptionD2Ev> + +01009b54 <_ZNSt9bad_allocD2Ev>: + 1009b54: 008040b4 movhi r2,258 + 1009b58: 10850d04 addi r2,r2,5172 + 1009b5c: 20800015 stw r2,0(r4) + 1009b60: 1009a5c1 jmpi 1009a5c <_ZNSt9exceptionD2Ev> + +01009b64 <__cxa_get_globals_fast>: + 1009b64: d0a74904 addi r2,gp,-25308 + 1009b68: f800283a ret + +01009b6c <__cxa_get_globals>: + 1009b6c: d0a74904 addi r2,gp,-25308 + 1009b70: f800283a ret + +01009b74 <_ZNSt10bad_typeidD0Ev>: + 1009b74: defffe04 addi sp,sp,-8 + 1009b78: 008040b4 movhi r2,258 + 1009b7c: 10851904 addi r2,r2,5220 + 1009b80: dc400015 stw r17,0(sp) + 1009b84: 20800015 stw r2,0(r4) + 1009b88: 2023883a mov r17,r4 + 1009b8c: dfc00115 stw ra,4(sp) + 1009b90: 1009a5c0 call 1009a5c <_ZNSt9exceptionD2Ev> + 1009b94: 8809883a mov r4,r17 + 1009b98: dfc00117 ldw ra,4(sp) + 1009b9c: dc400017 ldw r17,0(sp) + 1009ba0: dec00204 addi sp,sp,8 + 1009ba4: 100722c1 jmpi 100722c <_ZdlPv> + +01009ba8 <_ZNSt10bad_typeidD1Ev>: + 1009ba8: 008040b4 movhi r2,258 + 1009bac: 10851904 addi r2,r2,5220 + 1009bb0: 20800015 stw r2,0(r4) + 1009bb4: 1009a5c1 jmpi 1009a5c <_ZNSt9exceptionD2Ev> + +01009bb8 <_ZNSt10bad_typeidD2Ev>: + 1009bb8: 008040b4 movhi r2,258 + 1009bbc: 10851904 addi r2,r2,5220 + 1009bc0: 20800015 stw r2,0(r4) + 1009bc4: 1009a5c1 jmpi 1009a5c <_ZNSt9exceptionD2Ev> + +01009bc8 <_ZNSt8bad_castD0Ev>: + 1009bc8: defffe04 addi sp,sp,-8 + 1009bcc: 008040b4 movhi r2,258 + 1009bd0: 10852504 addi r2,r2,5268 + 1009bd4: dc400015 stw r17,0(sp) + 1009bd8: 20800015 stw r2,0(r4) + 1009bdc: 2023883a mov r17,r4 + 1009be0: dfc00115 stw ra,4(sp) + 1009be4: 1009a5c0 call 1009a5c <_ZNSt9exceptionD2Ev> + 1009be8: 8809883a mov r4,r17 + 1009bec: dfc00117 ldw ra,4(sp) + 1009bf0: dc400017 ldw r17,0(sp) + 1009bf4: dec00204 addi sp,sp,8 + 1009bf8: 100722c1 jmpi 100722c <_ZdlPv> + +01009bfc <_ZNSt8bad_castD1Ev>: + 1009bfc: 008040b4 movhi r2,258 + 1009c00: 10852504 addi r2,r2,5268 + 1009c04: 20800015 stw r2,0(r4) + 1009c08: 1009a5c1 jmpi 1009a5c <_ZNSt9exceptionD2Ev> + +01009c0c <_ZNSt8bad_castD2Ev>: + 1009c0c: 008040b4 movhi r2,258 + 1009c10: 10852504 addi r2,r2,5268 + 1009c14: 20800015 stw r2,0(r4) + 1009c18: 1009a5c1 jmpi 1009a5c <_ZNSt9exceptionD2Ev> + +01009c1c <_Unwind_SjLj_Register>: + 1009c1c: d0a74b17 ldw r2,-25300(gp) + 1009c20: 20800015 stw r2,0(r4) + 1009c24: d1274b15 stw r4,-25300(gp) + 1009c28: f800283a ret + +01009c2c <_Unwind_SjLj_Unregister>: + 1009c2c: 20800017 ldw r2,0(r4) + 1009c30: d0a74b15 stw r2,-25300(gp) + 1009c34: f800283a ret + +01009c38 <_Unwind_GetGR>: + 1009c38: 20800017 ldw r2,0(r4) + 1009c3c: 294b883a add r5,r5,r5 + 1009c40: 294b883a add r5,r5,r5 + 1009c44: 288b883a add r5,r5,r2 + 1009c48: 28800217 ldw r2,8(r5) + 1009c4c: f800283a ret + +01009c50 <_Unwind_GetCFA>: + 1009c50: 21000017 ldw r4,0(r4) + 1009c54: 0005883a mov r2,zero + 1009c58: 20000126 beq r4,zero,1009c60 <_Unwind_GetCFA+0x10> + 1009c5c: 20800a17 ldw r2,40(r4) + 1009c60: f800283a ret + +01009c64 <_Unwind_SetGR>: + 1009c64: 20800017 ldw r2,0(r4) + 1009c68: 294b883a add r5,r5,r5 + 1009c6c: 294b883a add r5,r5,r5 + 1009c70: 288b883a add r5,r5,r2 + 1009c74: 29800215 stw r6,8(r5) + 1009c78: f800283a ret + +01009c7c <_Unwind_GetIP>: + 1009c7c: 20c00017 ldw r3,0(r4) + 1009c80: 18800117 ldw r2,4(r3) + 1009c84: 10800044 addi r2,r2,1 + 1009c88: f800283a ret + +01009c8c <_Unwind_GetIPInfo>: + 1009c8c: 20c00017 ldw r3,0(r4) + 1009c90: 28000015 stw zero,0(r5) + 1009c94: 18800117 ldw r2,4(r3) + 1009c98: 10800044 addi r2,r2,1 + 1009c9c: f800283a ret + +01009ca0 <_Unwind_SetIP>: + 1009ca0: 20800017 ldw r2,0(r4) + 1009ca4: 297fffc4 addi r5,r5,-1 + 1009ca8: 11400115 stw r5,4(r2) + 1009cac: f800283a ret + +01009cb0 <_Unwind_GetLanguageSpecificData>: + 1009cb0: 20c00017 ldw r3,0(r4) + 1009cb4: 18800717 ldw r2,28(r3) + 1009cb8: f800283a ret + +01009cbc <_Unwind_GetRegionStart>: + 1009cbc: 0005883a mov r2,zero + 1009cc0: f800283a ret + +01009cc4 <_Unwind_FindEnclosingFunction>: + 1009cc4: 0005883a mov r2,zero + 1009cc8: f800283a ret + +01009ccc <_Unwind_GetDataRelBase>: + 1009ccc: 0005883a mov r2,zero + 1009cd0: f800283a ret + +01009cd4 <_Unwind_GetTextRelBase>: + 1009cd4: 0005883a mov r2,zero + 1009cd8: f800283a ret + +01009cdc <_Unwind_ForcedUnwind_Phase2>: + 1009cdc: defff604 addi sp,sp,-40 + 1009ce0: dd400815 stw r21,32(sp) + 1009ce4: dd000715 stw r20,28(sp) + 1009ce8: 25400317 ldw r21,12(r4) + 1009cec: 25000417 ldw r20,16(r4) + 1009cf0: 28800017 ldw r2,0(r5) + 1009cf4: dc800515 stw r18,20(sp) + 1009cf8: dc000315 stw r16,12(sp) + 1009cfc: 2825883a mov r18,r5 + 1009d00: 2021883a mov r16,r4 + 1009d04: dfc00915 stw ra,36(sp) + 1009d08: dcc00615 stw r19,24(sp) + 1009d0c: dc400415 stw r17,16(sp) + 1009d10: 00001406 br 1009d64 <_Unwind_ForcedUnwind_Phase2+0x88> + 1009d14: 00800144 movi r2,5 + 1009d18: 88802626 beq r17,r2,1009db4 <_Unwind_ForcedUnwind_Phase2+0xd8> + 1009d1c: 98000c26 beq r19,zero,1009d50 <_Unwind_ForcedUnwind_Phase2+0x74> + 1009d20: 82000017 ldw r8,0(r16) + 1009d24: dc000015 stw r16,0(sp) + 1009d28: dc800115 stw r18,4(sp) + 1009d2c: 82400117 ldw r9,4(r16) + 1009d30: 400d883a mov r6,r8 + 1009d34: 480f883a mov r7,r9 + 1009d38: 983ee83a callr r19 + 1009d3c: 1023883a mov r17,r2 + 1009d40: 008001c4 movi r2,7 + 1009d44: 88801b26 beq r17,r2,1009db4 <_Unwind_ForcedUnwind_Phase2+0xd8> + 1009d48: 00800204 movi r2,8 + 1009d4c: 8880181e bne r17,r2,1009db0 <_Unwind_ForcedUnwind_Phase2+0xd4> + 1009d50: 91000017 ldw r4,0(r18) + 1009d54: 1009c2c0 call 1009c2c <_Unwind_SjLj_Unregister> + 1009d58: 90800017 ldw r2,0(r18) + 1009d5c: 10800017 ldw r2,0(r2) + 1009d60: 90800015 stw r2,0(r18) + 1009d64: 01400684 movi r5,26 + 1009d68: 04400144 movi r17,5 + 1009d6c: 0027883a mov r19,zero + 1009d70: 10000326 beq r2,zero,1009d80 <_Unwind_ForcedUnwind_Phase2+0xa4> + 1009d74: 14c00617 ldw r19,24(r2) + 1009d78: 0023883a mov r17,zero + 1009d7c: 01400284 movi r5,10 + 1009d80: dc000015 stw r16,0(sp) + 1009d84: dc800115 stw r18,4(sp) + 1009d88: 80800017 ldw r2,0(r16) + 1009d8c: dd000215 stw r20,8(sp) + 1009d90: 80c00117 ldw r3,4(r16) + 1009d94: 01000044 movi r4,1 + 1009d98: 100d883a mov r6,r2 + 1009d9c: 180f883a mov r7,r3 + 1009da0: a83ee83a callr r21 + 1009da4: 01400284 movi r5,10 + 1009da8: 01000044 movi r4,1 + 1009dac: 103fd926 beq r2,zero,1009d14 <_Unwind_ForcedUnwind_Phase2+0x38> + 1009db0: 04400084 movi r17,2 + 1009db4: 8805883a mov r2,r17 + 1009db8: dfc00917 ldw ra,36(sp) + 1009dbc: dd400817 ldw r21,32(sp) + 1009dc0: dd000717 ldw r20,28(sp) + 1009dc4: dcc00617 ldw r19,24(sp) + 1009dc8: dc800517 ldw r18,20(sp) + 1009dcc: dc400417 ldw r17,16(sp) + 1009dd0: dc000317 ldw r16,12(sp) + 1009dd4: dec00a04 addi sp,sp,40 + 1009dd8: f800283a ret + +01009ddc <_Unwind_DeleteException>: + 1009ddc: 20800217 ldw r2,8(r4) + 1009de0: 200b883a mov r5,r4 + 1009de4: 01000044 movi r4,1 + 1009de8: 10000126 beq r2,zero,1009df0 <_Unwind_DeleteException+0x14> + 1009dec: 1000683a jmp r2 + 1009df0: f800283a ret + +01009df4 <_Unwind_RaiseException_Phase2>: + 1009df4: defffa04 addi sp,sp,-24 + 1009df8: dc800415 stw r18,16(sp) + 1009dfc: 2825883a mov r18,r5 + 1009e00: 29400017 ldw r5,0(r5) + 1009e04: dc400315 stw r17,12(sp) + 1009e08: dfc00515 stw ra,20(sp) + 1009e0c: dc000215 stw r16,8(sp) + 1009e10: 2023883a mov r17,r4 + 1009e14: 28001b26 beq r5,zero,1009e84 <_Unwind_RaiseException_Phase2+0x90> + 1009e18: 88800417 ldw r2,16(r17) + 1009e1c: 0007883a mov r3,zero + 1009e20: 2a000617 ldw r8,24(r5) + 1009e24: 28a1003a cmpeq r16,r5,r2 + 1009e28: 802090ba slli r16,r16,2 + 1009e2c: 18001b1e bne r3,zero,1009e9c <_Unwind_RaiseException_Phase2+0xa8> + 1009e30: 40000e26 beq r8,zero,1009e6c <_Unwind_RaiseException_Phase2+0x78> + 1009e34: 88800017 ldw r2,0(r17) + 1009e38: dc400015 stw r17,0(sp) + 1009e3c: dc800115 stw r18,4(sp) + 1009e40: 88c00117 ldw r3,4(r17) + 1009e44: 01000044 movi r4,1 + 1009e48: 81400094 ori r5,r16,2 + 1009e4c: 180f883a mov r7,r3 + 1009e50: 100d883a mov r6,r2 + 1009e54: 403ee83a callr r8 + 1009e58: 1007883a mov r3,r2 + 1009e5c: 008001c4 movi r2,7 + 1009e60: 18800f26 beq r3,r2,1009ea0 <_Unwind_RaiseException_Phase2+0xac> + 1009e64: 00800204 movi r2,8 + 1009e68: 18800c1e bne r3,r2,1009e9c <_Unwind_RaiseException_Phase2+0xa8> + 1009e6c: 8000131e bne r16,zero,1009ebc <_Unwind_RaiseException_Phase2+0xc8> + 1009e70: 91400017 ldw r5,0(r18) + 1009e74: 28800017 ldw r2,0(r5) + 1009e78: 100b883a mov r5,r2 + 1009e7c: 90800015 stw r2,0(r18) + 1009e80: 283fe51e bne r5,zero,1009e18 <_Unwind_RaiseException_Phase2+0x24> + 1009e84: 88800417 ldw r2,16(r17) + 1009e88: 00c00144 movi r3,5 + 1009e8c: 0011883a mov r8,zero + 1009e90: 28a1003a cmpeq r16,r5,r2 + 1009e94: 802090ba slli r16,r16,2 + 1009e98: 183fe526 beq r3,zero,1009e30 <_Unwind_RaiseException_Phase2+0x3c> + 1009e9c: 00c00084 movi r3,2 + 1009ea0: 1805883a mov r2,r3 + 1009ea4: dfc00517 ldw ra,20(sp) + 1009ea8: dc800417 ldw r18,16(sp) + 1009eac: dc400317 ldw r17,12(sp) + 1009eb0: dc000217 ldw r16,8(sp) + 1009eb4: dec00604 addi sp,sp,24 + 1009eb8: f800283a ret + 1009ebc: 100a1640 call 100a164 + +01009ec0 : + 1009ec0: 28800017 ldw r2,0(r5) + 1009ec4: deffff04 addi sp,sp,-4 + 1009ec8: df000015 stw fp,0(sp) + 1009ecc: 10c00804 addi r3,r2,32 + 1009ed0: d839883a mov fp,sp + 1009ed4: d0a74b15 stw r2,-25300(gp) + 1009ed8: 19000117 ldw r4,4(r3) + 1009edc: 1f000017 ldw fp,0(r3) + 1009ee0: 1ec00217 ldw sp,8(r3) + 1009ee4: 2000683a jmp r4 + +01009ee8 <_Unwind_SjLj_Resume>: + 1009ee8: d0e74b17 ldw r3,-25300(gp) + 1009eec: 20800317 ldw r2,12(r4) + 1009ef0: defffc04 addi sp,sp,-16 + 1009ef4: dfc00315 stw ra,12(sp) + 1009ef8: dc000215 stw r16,8(sp) + 1009efc: d8c00015 stw r3,0(sp) + 1009f00: d8c00115 stw r3,4(sp) + 1009f04: 1000071e bne r2,zero,1009f24 <_Unwind_SjLj_Resume+0x3c> + 1009f08: dc000104 addi r16,sp,4 + 1009f0c: 800b883a mov r5,r16 + 1009f10: 1009df40 call 1009df4 <_Unwind_RaiseException_Phase2> + 1009f14: 1007883a mov r3,r2 + 1009f18: 008001c4 movi r2,7 + 1009f1c: 18800626 beq r3,r2,1009f38 <_Unwind_SjLj_Resume+0x50> + 1009f20: 100a1640 call 100a164 + 1009f24: dc000104 addi r16,sp,4 + 1009f28: 800b883a mov r5,r16 + 1009f2c: 1009cdc0 call 1009cdc <_Unwind_ForcedUnwind_Phase2> + 1009f30: 1007883a mov r3,r2 + 1009f34: 003ff806 br 1009f18 <_Unwind_SjLj_Resume+0x30> + 1009f38: 800b883a mov r5,r16 + 1009f3c: d809883a mov r4,sp + 1009f40: 1009ec00 call 1009ec0 + +01009f44 <_Unwind_SjLj_RaiseException>: + 1009f44: d0a74b17 ldw r2,-25300(gp) + 1009f48: defff804 addi sp,sp,-32 + 1009f4c: dc000415 stw r16,16(sp) + 1009f50: dfc00715 stw ra,28(sp) + 1009f54: dc800615 stw r18,24(sp) + 1009f58: dc400515 stw r17,20(sp) + 1009f5c: 2021883a mov r16,r4 + 1009f60: d8800215 stw r2,8(sp) + 1009f64: d8800315 stw r2,12(sp) + 1009f68: 10001626 beq r2,zero,1009fc4 <_Unwind_SjLj_RaiseException+0x80> + 1009f6c: dc400304 addi r17,sp,12 + 1009f70: 04800184 movi r18,6 + 1009f74: 00000106 br 1009f7c <_Unwind_SjLj_RaiseException+0x38> + 1009f78: d8800315 stw r2,12(sp) + 1009f7c: 12000617 ldw r8,24(r2) + 1009f80: 40000d26 beq r8,zero,1009fb8 <_Unwind_SjLj_RaiseException+0x74> + 1009f84: 80800017 ldw r2,0(r16) + 1009f88: dc000015 stw r16,0(sp) + 1009f8c: 80c00117 ldw r3,4(r16) + 1009f90: 01000044 movi r4,1 + 1009f94: dc400115 stw r17,4(sp) + 1009f98: 180f883a mov r7,r3 + 1009f9c: 200b883a mov r5,r4 + 1009fa0: 100d883a mov r6,r2 + 1009fa4: 403ee83a callr r8 + 1009fa8: 1007883a mov r3,r2 + 1009fac: 14800d26 beq r2,r18,1009fe4 <_Unwind_SjLj_RaiseException+0xa0> + 1009fb0: 00800204 movi r2,8 + 1009fb4: 1880191e bne r3,r2,100a01c <_Unwind_SjLj_RaiseException+0xd8> + 1009fb8: d8800317 ldw r2,12(sp) + 1009fbc: 10800017 ldw r2,0(r2) + 1009fc0: 103fed1e bne r2,zero,1009f78 <_Unwind_SjLj_RaiseException+0x34> + 1009fc4: 00c00144 movi r3,5 + 1009fc8: 1805883a mov r2,r3 + 1009fcc: dfc00717 ldw ra,28(sp) + 1009fd0: dc800617 ldw r18,24(sp) + 1009fd4: dc400517 ldw r17,20(sp) + 1009fd8: dc000417 ldw r16,16(sp) + 1009fdc: dec00804 addi sp,sp,32 + 1009fe0: f800283a ret + 1009fe4: d8800317 ldw r2,12(sp) + 1009fe8: 80000315 stw zero,12(r16) + 1009fec: 8009883a mov r4,r16 + 1009ff0: 80800415 stw r2,16(r16) + 1009ff4: d8800217 ldw r2,8(sp) + 1009ff8: 880b883a mov r5,r17 + 1009ffc: d8800315 stw r2,12(sp) + 100a000: 1009df40 call 1009df4 <_Unwind_RaiseException_Phase2> + 100a004: 1007883a mov r3,r2 + 100a008: 008001c4 movi r2,7 + 100a00c: 18bfee1e bne r3,r2,1009fc8 <_Unwind_SjLj_RaiseException+0x84> + 100a010: 880b883a mov r5,r17 + 100a014: d9000204 addi r4,sp,8 + 100a018: 1009ec00 call 1009ec0 + 100a01c: 00c000c4 movi r3,3 + 100a020: 1805883a mov r2,r3 + 100a024: dfc00717 ldw ra,28(sp) + 100a028: dc800617 ldw r18,24(sp) + 100a02c: dc400517 ldw r17,20(sp) + 100a030: dc000417 ldw r16,16(sp) + 100a034: dec00804 addi sp,sp,32 + 100a038: f800283a ret + +0100a03c <_Unwind_SjLj_ForcedUnwind>: + 100a03c: defffc04 addi sp,sp,-16 + 100a040: d0a74b17 ldw r2,-25300(gp) + 100a044: dc000215 stw r16,8(sp) + 100a048: dc000104 addi r16,sp,4 + 100a04c: 21400315 stw r5,12(r4) + 100a050: 21800415 stw r6,16(r4) + 100a054: 800b883a mov r5,r16 + 100a058: dfc00315 stw ra,12(sp) + 100a05c: d8800015 stw r2,0(sp) + 100a060: d8800115 stw r2,4(sp) + 100a064: 1009cdc0 call 1009cdc <_Unwind_ForcedUnwind_Phase2> + 100a068: 00c001c4 movi r3,7 + 100a06c: 10c00426 beq r2,r3,100a080 <_Unwind_SjLj_ForcedUnwind+0x44> + 100a070: dfc00317 ldw ra,12(sp) + 100a074: dc000217 ldw r16,8(sp) + 100a078: dec00404 addi sp,sp,16 + 100a07c: f800283a ret + 100a080: 800b883a mov r5,r16 + 100a084: d809883a mov r4,sp + 100a088: 1009ec00 call 1009ec0 + +0100a08c <_Unwind_Backtrace>: + 100a08c: d0a74b17 ldw r2,-25300(gp) + 100a090: defffa04 addi sp,sp,-24 + 100a094: dcc00415 stw r19,16(sp) + 100a098: dc800315 stw r18,12(sp) + 100a09c: dc400215 stw r17,8(sp) + 100a0a0: 2025883a mov r18,r4 + 100a0a4: 2823883a mov r17,r5 + 100a0a8: 04c00144 movi r19,5 + 100a0ac: dfc00515 stw ra,20(sp) + 100a0b0: dc000115 stw r16,4(sp) + 100a0b4: d8800015 stw r2,0(sp) + 100a0b8: 00000406 br 100a0cc <_Unwind_Backtrace+0x40> + 100a0bc: 84c00b26 beq r16,r19,100a0ec <_Unwind_Backtrace+0x60> + 100a0c0: d8800017 ldw r2,0(sp) + 100a0c4: 10800017 ldw r2,0(r2) + 100a0c8: d8800015 stw r2,0(sp) + 100a0cc: 04000144 movi r16,5 + 100a0d0: 10000126 beq r2,zero,100a0d8 <_Unwind_Backtrace+0x4c> + 100a0d4: 0021883a mov r16,zero + 100a0d8: d809883a mov r4,sp + 100a0dc: 880b883a mov r5,r17 + 100a0e0: 903ee83a callr r18 + 100a0e4: 103ff526 beq r2,zero,100a0bc <_Unwind_Backtrace+0x30> + 100a0e8: 040000c4 movi r16,3 + 100a0ec: 8005883a mov r2,r16 + 100a0f0: dfc00517 ldw ra,20(sp) + 100a0f4: dcc00417 ldw r19,16(sp) + 100a0f8: dc800317 ldw r18,12(sp) + 100a0fc: dc400217 ldw r17,8(sp) + 100a100: dc000117 ldw r16,4(sp) + 100a104: dec00604 addi sp,sp,24 + 100a108: f800283a ret + +0100a10c <_Unwind_SjLj_Resume_or_Rethrow>: + 100a10c: 20800317 ldw r2,12(r4) + 100a110: defffc04 addi sp,sp,-16 + 100a114: dfc00315 stw ra,12(sp) + 100a118: dc000215 stw r16,8(sp) + 100a11c: 10000926 beq r2,zero,100a144 <_Unwind_SjLj_Resume_or_Rethrow+0x38> + 100a120: d0a74b17 ldw r2,-25300(gp) + 100a124: dc000104 addi r16,sp,4 + 100a128: 800b883a mov r5,r16 + 100a12c: d8800015 stw r2,0(sp) + 100a130: d8800115 stw r2,4(sp) + 100a134: 1009cdc0 call 1009cdc <_Unwind_ForcedUnwind_Phase2> + 100a138: 00c001c4 movi r3,7 + 100a13c: 10c00626 beq r2,r3,100a158 <_Unwind_SjLj_Resume_or_Rethrow+0x4c> + 100a140: 100a1640 call 100a164 + 100a144: 1009f440 call 1009f44 <_Unwind_SjLj_RaiseException> + 100a148: dfc00317 ldw ra,12(sp) + 100a14c: dc000217 ldw r16,8(sp) + 100a150: dec00404 addi sp,sp,16 + 100a154: f800283a ret + 100a158: 800b883a mov r5,r16 + 100a15c: d809883a mov r4,sp + 100a160: 1009ec00 call 1009ec0 + +0100a164 : + 100a164: deffff04 addi sp,sp,-4 + 100a168: 01000184 movi r4,6 + 100a16c: dfc00015 stw ra,0(sp) + 100a170: 100aee00 call 100aee0 + 100a174: 01000044 movi r4,1 + 100a178: 10144380 call 1014438 <_exit> + +0100a17c : + 100a17c: 008040b4 movhi r2,258 + 100a180: 108dc804 addi r2,r2,14112 + 100a184: 200b883a mov r5,r4 + 100a188: 11000017 ldw r4,0(r2) + 100a18c: 100f28c1 jmpi 100f28c <_free_r> + +0100a190 : + 100a190: 008040b4 movhi r2,258 + 100a194: 108dc804 addi r2,r2,14112 + 100a198: 200b883a mov r5,r4 + 100a19c: 11000017 ldw r4,0(r2) + 100a1a0: 100a1a41 jmpi 100a1a4 <_malloc_r> + +0100a1a4 <_malloc_r>: + 100a1a4: defff604 addi sp,sp,-40 + 100a1a8: 28c002c4 addi r3,r5,11 + 100a1ac: 00800584 movi r2,22 + 100a1b0: dc800215 stw r18,8(sp) + 100a1b4: dfc00915 stw ra,36(sp) + 100a1b8: df000815 stw fp,32(sp) + 100a1bc: ddc00715 stw r23,28(sp) + 100a1c0: dd800615 stw r22,24(sp) + 100a1c4: dd400515 stw r21,20(sp) + 100a1c8: dd000415 stw r20,16(sp) + 100a1cc: dcc00315 stw r19,12(sp) + 100a1d0: dc400115 stw r17,4(sp) + 100a1d4: dc000015 stw r16,0(sp) + 100a1d8: 2025883a mov r18,r4 + 100a1dc: 10c01236 bltu r2,r3,100a228 <_malloc_r+0x84> + 100a1e0: 04400404 movi r17,16 + 100a1e4: 8940142e bgeu r17,r5,100a238 <_malloc_r+0x94> + 100a1e8: 00800304 movi r2,12 + 100a1ec: 0007883a mov r3,zero + 100a1f0: 90800015 stw r2,0(r18) + 100a1f4: 1805883a mov r2,r3 + 100a1f8: dfc00917 ldw ra,36(sp) + 100a1fc: df000817 ldw fp,32(sp) + 100a200: ddc00717 ldw r23,28(sp) + 100a204: dd800617 ldw r22,24(sp) + 100a208: dd400517 ldw r21,20(sp) + 100a20c: dd000417 ldw r20,16(sp) + 100a210: dcc00317 ldw r19,12(sp) + 100a214: dc800217 ldw r18,8(sp) + 100a218: dc400117 ldw r17,4(sp) + 100a21c: dc000017 ldw r16,0(sp) + 100a220: dec00a04 addi sp,sp,40 + 100a224: f800283a ret + 100a228: 00bffe04 movi r2,-8 + 100a22c: 18a2703a and r17,r3,r2 + 100a230: 883fed16 blt r17,zero,100a1e8 <_malloc_r+0x44> + 100a234: 897fec36 bltu r17,r5,100a1e8 <_malloc_r+0x44> + 100a238: 9009883a mov r4,r18 + 100a23c: 10150a00 call 10150a0 <__malloc_lock> + 100a240: 00807dc4 movi r2,503 + 100a244: 14402b2e bgeu r2,r17,100a2f4 <_malloc_r+0x150> + 100a248: 8806d27a srli r3,r17,9 + 100a24c: 18003f1e bne r3,zero,100a34c <_malloc_r+0x1a8> + 100a250: 880cd0fa srli r6,r17,3 + 100a254: 300490fa slli r2,r6,3 + 100a258: 02c040b4 movhi r11,258 + 100a25c: 5ac6f004 addi r11,r11,7104 + 100a260: 12cb883a add r5,r2,r11 + 100a264: 2c000317 ldw r16,12(r5) + 100a268: 580f883a mov r7,r11 + 100a26c: 2c00041e bne r5,r16,100a280 <_malloc_r+0xdc> + 100a270: 00000a06 br 100a29c <_malloc_r+0xf8> + 100a274: 1800860e bge r3,zero,100a490 <_malloc_r+0x2ec> + 100a278: 84000317 ldw r16,12(r16) + 100a27c: 2c000726 beq r5,r16,100a29c <_malloc_r+0xf8> + 100a280: 80800117 ldw r2,4(r16) + 100a284: 00ffff04 movi r3,-4 + 100a288: 10c8703a and r4,r2,r3 + 100a28c: 2447c83a sub r3,r4,r17 + 100a290: 008003c4 movi r2,15 + 100a294: 10fff70e bge r2,r3,100a274 <_malloc_r+0xd0> + 100a298: 31bfffc4 addi r6,r6,-1 + 100a29c: 32400044 addi r9,r6,1 + 100a2a0: 028040b4 movhi r10,258 + 100a2a4: 5286f204 addi r10,r10,7112 + 100a2a8: 54000217 ldw r16,8(r10) + 100a2ac: 8280a026 beq r16,r10,100a530 <_malloc_r+0x38c> + 100a2b0: 80800117 ldw r2,4(r16) + 100a2b4: 00ffff04 movi r3,-4 + 100a2b8: 10ca703a and r5,r2,r3 + 100a2bc: 2c4dc83a sub r6,r5,r17 + 100a2c0: 008003c4 movi r2,15 + 100a2c4: 11808316 blt r2,r6,100a4d4 <_malloc_r+0x330> + 100a2c8: 52800315 stw r10,12(r10) + 100a2cc: 52800215 stw r10,8(r10) + 100a2d0: 30002916 blt r6,zero,100a378 <_malloc_r+0x1d4> + 100a2d4: 8147883a add r3,r16,r5 + 100a2d8: 18800117 ldw r2,4(r3) + 100a2dc: 9009883a mov r4,r18 + 100a2e0: 10800054 ori r2,r2,1 + 100a2e4: 18800115 stw r2,4(r3) + 100a2e8: 10151a80 call 10151a8 <__malloc_unlock> + 100a2ec: 80c00204 addi r3,r16,8 + 100a2f0: 003fc006 br 100a1f4 <_malloc_r+0x50> + 100a2f4: 02c040b4 movhi r11,258 + 100a2f8: 5ac6f004 addi r11,r11,7104 + 100a2fc: 8ac5883a add r2,r17,r11 + 100a300: 14000317 ldw r16,12(r2) + 100a304: 580f883a mov r7,r11 + 100a308: 8806d0fa srli r3,r17,3 + 100a30c: 14006c26 beq r2,r16,100a4c0 <_malloc_r+0x31c> + 100a310: 80c00117 ldw r3,4(r16) + 100a314: 00bfff04 movi r2,-4 + 100a318: 81800317 ldw r6,12(r16) + 100a31c: 1886703a and r3,r3,r2 + 100a320: 80c7883a add r3,r16,r3 + 100a324: 18800117 ldw r2,4(r3) + 100a328: 81400217 ldw r5,8(r16) + 100a32c: 9009883a mov r4,r18 + 100a330: 10800054 ori r2,r2,1 + 100a334: 18800115 stw r2,4(r3) + 100a338: 31400215 stw r5,8(r6) + 100a33c: 29800315 stw r6,12(r5) + 100a340: 10151a80 call 10151a8 <__malloc_unlock> + 100a344: 80c00204 addi r3,r16,8 + 100a348: 003faa06 br 100a1f4 <_malloc_r+0x50> + 100a34c: 00800104 movi r2,4 + 100a350: 10c0052e bgeu r2,r3,100a368 <_malloc_r+0x1c4> + 100a354: 00800504 movi r2,20 + 100a358: 10c07836 bltu r2,r3,100a53c <_malloc_r+0x398> + 100a35c: 198016c4 addi r6,r3,91 + 100a360: 300490fa slli r2,r6,3 + 100a364: 003fbc06 br 100a258 <_malloc_r+0xb4> + 100a368: 8804d1ba srli r2,r17,6 + 100a36c: 11800e04 addi r6,r2,56 + 100a370: 300490fa slli r2,r6,3 + 100a374: 003fb806 br 100a258 <_malloc_r+0xb4> + 100a378: 00807fc4 movi r2,511 + 100a37c: 1140bb36 bltu r2,r5,100a66c <_malloc_r+0x4c8> + 100a380: 2806d0fa srli r3,r5,3 + 100a384: 573ffe04 addi fp,r10,-8 + 100a388: 00800044 movi r2,1 + 100a38c: 180890fa slli r4,r3,3 + 100a390: 1807d0ba srai r3,r3,2 + 100a394: e1c00117 ldw r7,4(fp) + 100a398: 5909883a add r4,r11,r4 + 100a39c: 21400217 ldw r5,8(r4) + 100a3a0: 10c4983a sll r2,r2,r3 + 100a3a4: 81000315 stw r4,12(r16) + 100a3a8: 81400215 stw r5,8(r16) + 100a3ac: 388eb03a or r7,r7,r2 + 100a3b0: 2c000315 stw r16,12(r5) + 100a3b4: 24000215 stw r16,8(r4) + 100a3b8: e1c00115 stw r7,4(fp) + 100a3bc: 4807883a mov r3,r9 + 100a3c0: 4800cd16 blt r9,zero,100a6f8 <_malloc_r+0x554> + 100a3c4: 1807d0ba srai r3,r3,2 + 100a3c8: 00800044 movi r2,1 + 100a3cc: 10c8983a sll r4,r2,r3 + 100a3d0: 39004436 bltu r7,r4,100a4e4 <_malloc_r+0x340> + 100a3d4: 21c4703a and r2,r4,r7 + 100a3d8: 10000a1e bne r2,zero,100a404 <_malloc_r+0x260> + 100a3dc: 2109883a add r4,r4,r4 + 100a3e0: 00bfff04 movi r2,-4 + 100a3e4: 4884703a and r2,r9,r2 + 100a3e8: 3906703a and r3,r7,r4 + 100a3ec: 12400104 addi r9,r2,4 + 100a3f0: 1800041e bne r3,zero,100a404 <_malloc_r+0x260> + 100a3f4: 2109883a add r4,r4,r4 + 100a3f8: 3904703a and r2,r7,r4 + 100a3fc: 4a400104 addi r9,r9,4 + 100a400: 103ffc26 beq r2,zero,100a3f4 <_malloc_r+0x250> + 100a404: 480490fa slli r2,r9,3 + 100a408: 4819883a mov r12,r9 + 100a40c: 023fff04 movi r8,-4 + 100a410: 589b883a add r13,r11,r2 + 100a414: 6807883a mov r3,r13 + 100a418: 014003c4 movi r5,15 + 100a41c: 1c000317 ldw r16,12(r3) + 100a420: 1c00041e bne r3,r16,100a434 <_malloc_r+0x290> + 100a424: 0000a706 br 100a6c4 <_malloc_r+0x520> + 100a428: 3000ab0e bge r6,zero,100a6d8 <_malloc_r+0x534> + 100a42c: 84000317 ldw r16,12(r16) + 100a430: 1c00a426 beq r3,r16,100a6c4 <_malloc_r+0x520> + 100a434: 80800117 ldw r2,4(r16) + 100a438: 1204703a and r2,r2,r8 + 100a43c: 144dc83a sub r6,r2,r17 + 100a440: 29bff90e bge r5,r6,100a428 <_malloc_r+0x284> + 100a444: 81000317 ldw r4,12(r16) + 100a448: 80c00217 ldw r3,8(r16) + 100a44c: 89400054 ori r5,r17,1 + 100a450: 8445883a add r2,r16,r17 + 100a454: 20c00215 stw r3,8(r4) + 100a458: 19000315 stw r4,12(r3) + 100a45c: 81400115 stw r5,4(r16) + 100a460: 1187883a add r3,r2,r6 + 100a464: 31000054 ori r4,r6,1 + 100a468: 50800315 stw r2,12(r10) + 100a46c: 50800215 stw r2,8(r10) + 100a470: 19800015 stw r6,0(r3) + 100a474: 11000115 stw r4,4(r2) + 100a478: 12800215 stw r10,8(r2) + 100a47c: 12800315 stw r10,12(r2) + 100a480: 9009883a mov r4,r18 + 100a484: 10151a80 call 10151a8 <__malloc_unlock> + 100a488: 80c00204 addi r3,r16,8 + 100a48c: 003f5906 br 100a1f4 <_malloc_r+0x50> + 100a490: 8109883a add r4,r16,r4 + 100a494: 20800117 ldw r2,4(r4) + 100a498: 80c00217 ldw r3,8(r16) + 100a49c: 81400317 ldw r5,12(r16) + 100a4a0: 10800054 ori r2,r2,1 + 100a4a4: 20800115 stw r2,4(r4) + 100a4a8: 28c00215 stw r3,8(r5) + 100a4ac: 19400315 stw r5,12(r3) + 100a4b0: 9009883a mov r4,r18 + 100a4b4: 10151a80 call 10151a8 <__malloc_unlock> + 100a4b8: 80c00204 addi r3,r16,8 + 100a4bc: 003f4d06 br 100a1f4 <_malloc_r+0x50> + 100a4c0: 80800204 addi r2,r16,8 + 100a4c4: 14000317 ldw r16,12(r2) + 100a4c8: 143f911e bne r2,r16,100a310 <_malloc_r+0x16c> + 100a4cc: 1a400084 addi r9,r3,2 + 100a4d0: 003f7306 br 100a2a0 <_malloc_r+0xfc> + 100a4d4: 88c00054 ori r3,r17,1 + 100a4d8: 8445883a add r2,r16,r17 + 100a4dc: 80c00115 stw r3,4(r16) + 100a4e0: 003fdf06 br 100a460 <_malloc_r+0x2bc> + 100a4e4: e4000217 ldw r16,8(fp) + 100a4e8: 00bfff04 movi r2,-4 + 100a4ec: 80c00117 ldw r3,4(r16) + 100a4f0: 802d883a mov r22,r16 + 100a4f4: 18aa703a and r21,r3,r2 + 100a4f8: ac401636 bltu r21,r17,100a554 <_malloc_r+0x3b0> + 100a4fc: ac49c83a sub r4,r21,r17 + 100a500: 008003c4 movi r2,15 + 100a504: 1100130e bge r2,r4,100a554 <_malloc_r+0x3b0> + 100a508: 88800054 ori r2,r17,1 + 100a50c: 8447883a add r3,r16,r17 + 100a510: 80800115 stw r2,4(r16) + 100a514: 20800054 ori r2,r4,1 + 100a518: 18800115 stw r2,4(r3) + 100a51c: e0c00215 stw r3,8(fp) + 100a520: 9009883a mov r4,r18 + 100a524: 10151a80 call 10151a8 <__malloc_unlock> + 100a528: 80c00204 addi r3,r16,8 + 100a52c: 003f3106 br 100a1f4 <_malloc_r+0x50> + 100a530: 39c00117 ldw r7,4(r7) + 100a534: 573ffe04 addi fp,r10,-8 + 100a538: 003fa006 br 100a3bc <_malloc_r+0x218> + 100a53c: 00801504 movi r2,84 + 100a540: 10c06736 bltu r2,r3,100a6e0 <_malloc_r+0x53c> + 100a544: 8804d33a srli r2,r17,12 + 100a548: 11801b84 addi r6,r2,110 + 100a54c: 300490fa slli r2,r6,3 + 100a550: 003f4106 br 100a258 <_malloc_r+0xb4> + 100a554: d0a74c17 ldw r2,-25296(gp) + 100a558: d0e00d17 ldw r3,-32716(gp) + 100a55c: 053fffc4 movi r20,-1 + 100a560: 10800404 addi r2,r2,16 + 100a564: 88a7883a add r19,r17,r2 + 100a568: 1d000326 beq r3,r20,100a578 <_malloc_r+0x3d4> + 100a56c: 98c3ffc4 addi r3,r19,4095 + 100a570: 00bc0004 movi r2,-4096 + 100a574: 18a6703a and r19,r3,r2 + 100a578: 9009883a mov r4,r18 + 100a57c: 980b883a mov r5,r19 + 100a580: 100ada40 call 100ada4 <_sbrk_r> + 100a584: 1009883a mov r4,r2 + 100a588: 15000426 beq r2,r20,100a59c <_malloc_r+0x3f8> + 100a58c: 854b883a add r5,r16,r21 + 100a590: 1029883a mov r20,r2 + 100a594: 11405a2e bgeu r2,r5,100a700 <_malloc_r+0x55c> + 100a598: 87000c26 beq r16,fp,100a5cc <_malloc_r+0x428> + 100a59c: e4000217 ldw r16,8(fp) + 100a5a0: 80c00117 ldw r3,4(r16) + 100a5a4: 00bfff04 movi r2,-4 + 100a5a8: 1884703a and r2,r3,r2 + 100a5ac: 14400336 bltu r2,r17,100a5bc <_malloc_r+0x418> + 100a5b0: 1449c83a sub r4,r2,r17 + 100a5b4: 008003c4 movi r2,15 + 100a5b8: 113fd316 blt r2,r4,100a508 <_malloc_r+0x364> + 100a5bc: 9009883a mov r4,r18 + 100a5c0: 10151a80 call 10151a8 <__malloc_unlock> + 100a5c4: 0007883a mov r3,zero + 100a5c8: 003f0a06 br 100a1f4 <_malloc_r+0x50> + 100a5cc: 05c040f4 movhi r23,259 + 100a5d0: bde73304 addi r23,r23,-25396 + 100a5d4: b8800017 ldw r2,0(r23) + 100a5d8: 988d883a add r6,r19,r2 + 100a5dc: b9800015 stw r6,0(r23) + 100a5e0: d0e00d17 ldw r3,-32716(gp) + 100a5e4: 00bfffc4 movi r2,-1 + 100a5e8: 18808e26 beq r3,r2,100a824 <_malloc_r+0x680> + 100a5ec: 2145c83a sub r2,r4,r5 + 100a5f0: 3085883a add r2,r6,r2 + 100a5f4: b8800015 stw r2,0(r23) + 100a5f8: 20c001cc andi r3,r4,7 + 100a5fc: 18005f1e bne r3,zero,100a77c <_malloc_r+0x5d8> + 100a600: 000b883a mov r5,zero + 100a604: a4c5883a add r2,r20,r19 + 100a608: 1083ffcc andi r2,r2,4095 + 100a60c: 00c40004 movi r3,4096 + 100a610: 1887c83a sub r3,r3,r2 + 100a614: 28e7883a add r19,r5,r3 + 100a618: 9009883a mov r4,r18 + 100a61c: 980b883a mov r5,r19 + 100a620: 100ada40 call 100ada4 <_sbrk_r> + 100a624: 1007883a mov r3,r2 + 100a628: 00bfffc4 movi r2,-1 + 100a62c: 18807a26 beq r3,r2,100a818 <_malloc_r+0x674> + 100a630: 1d05c83a sub r2,r3,r20 + 100a634: 9885883a add r2,r19,r2 + 100a638: 10c00054 ori r3,r2,1 + 100a63c: b8800017 ldw r2,0(r23) + 100a640: a021883a mov r16,r20 + 100a644: a0c00115 stw r3,4(r20) + 100a648: 9885883a add r2,r19,r2 + 100a64c: b8800015 stw r2,0(r23) + 100a650: e5000215 stw r20,8(fp) + 100a654: b7003626 beq r22,fp,100a730 <_malloc_r+0x58c> + 100a658: 018003c4 movi r6,15 + 100a65c: 35404b36 bltu r6,r21,100a78c <_malloc_r+0x5e8> + 100a660: 00800044 movi r2,1 + 100a664: a0800115 stw r2,4(r20) + 100a668: 003fcd06 br 100a5a0 <_malloc_r+0x3fc> + 100a66c: 2808d27a srli r4,r5,9 + 100a670: 2000371e bne r4,zero,100a750 <_malloc_r+0x5ac> + 100a674: 2808d0fa srli r4,r5,3 + 100a678: 200690fa slli r3,r4,3 + 100a67c: 1ad1883a add r8,r3,r11 + 100a680: 41800217 ldw r6,8(r8) + 100a684: 41805b26 beq r8,r6,100a7f4 <_malloc_r+0x650> + 100a688: 30800117 ldw r2,4(r6) + 100a68c: 00ffff04 movi r3,-4 + 100a690: 10c4703a and r2,r2,r3 + 100a694: 2880022e bgeu r5,r2,100a6a0 <_malloc_r+0x4fc> + 100a698: 31800217 ldw r6,8(r6) + 100a69c: 41bffa1e bne r8,r6,100a688 <_malloc_r+0x4e4> + 100a6a0: 32000317 ldw r8,12(r6) + 100a6a4: 39c00117 ldw r7,4(r7) + 100a6a8: 82000315 stw r8,12(r16) + 100a6ac: 81800215 stw r6,8(r16) + 100a6b0: 070040b4 movhi fp,258 + 100a6b4: e706f004 addi fp,fp,7104 + 100a6b8: 34000315 stw r16,12(r6) + 100a6bc: 44000215 stw r16,8(r8) + 100a6c0: 003f3e06 br 100a3bc <_malloc_r+0x218> + 100a6c4: 63000044 addi r12,r12,1 + 100a6c8: 608000cc andi r2,r12,3 + 100a6cc: 10005d26 beq r2,zero,100a844 <_malloc_r+0x6a0> + 100a6d0: 18c00204 addi r3,r3,8 + 100a6d4: 003f5106 br 100a41c <_malloc_r+0x278> + 100a6d8: 8089883a add r4,r16,r2 + 100a6dc: 003f6d06 br 100a494 <_malloc_r+0x2f0> + 100a6e0: 00805504 movi r2,340 + 100a6e4: 10c02036 bltu r2,r3,100a768 <_malloc_r+0x5c4> + 100a6e8: 8804d3fa srli r2,r17,15 + 100a6ec: 11801dc4 addi r6,r2,119 + 100a6f0: 300490fa slli r2,r6,3 + 100a6f4: 003ed806 br 100a258 <_malloc_r+0xb4> + 100a6f8: 48c000c4 addi r3,r9,3 + 100a6fc: 003f3106 br 100a3c4 <_malloc_r+0x220> + 100a700: 05c040f4 movhi r23,259 + 100a704: bde73304 addi r23,r23,-25396 + 100a708: b8800017 ldw r2,0(r23) + 100a70c: 988d883a add r6,r19,r2 + 100a710: b9800015 stw r6,0(r23) + 100a714: 293fb21e bne r5,r4,100a5e0 <_malloc_r+0x43c> + 100a718: 2083ffcc andi r2,r4,4095 + 100a71c: 103fb01e bne r2,zero,100a5e0 <_malloc_r+0x43c> + 100a720: e4000217 ldw r16,8(fp) + 100a724: 9d45883a add r2,r19,r21 + 100a728: 10800054 ori r2,r2,1 + 100a72c: 80800115 stw r2,4(r16) + 100a730: b8c00017 ldw r3,0(r23) + 100a734: d0a74d17 ldw r2,-25292(gp) + 100a738: 10c0012e bgeu r2,r3,100a740 <_malloc_r+0x59c> + 100a73c: d0e74d15 stw r3,-25292(gp) + 100a740: d0a74e17 ldw r2,-25288(gp) + 100a744: 10ff962e bgeu r2,r3,100a5a0 <_malloc_r+0x3fc> + 100a748: d0e74e15 stw r3,-25288(gp) + 100a74c: 003f9406 br 100a5a0 <_malloc_r+0x3fc> + 100a750: 00800104 movi r2,4 + 100a754: 11001e36 bltu r2,r4,100a7d0 <_malloc_r+0x62c> + 100a758: 2804d1ba srli r2,r5,6 + 100a75c: 11000e04 addi r4,r2,56 + 100a760: 200690fa slli r3,r4,3 + 100a764: 003fc506 br 100a67c <_malloc_r+0x4d8> + 100a768: 00815504 movi r2,1364 + 100a76c: 10c01d2e bgeu r2,r3,100a7e4 <_malloc_r+0x640> + 100a770: 01801f84 movi r6,126 + 100a774: 0080fc04 movi r2,1008 + 100a778: 003eb706 br 100a258 <_malloc_r+0xb4> + 100a77c: 00800204 movi r2,8 + 100a780: 10cbc83a sub r5,r2,r3 + 100a784: 2169883a add r20,r4,r5 + 100a788: 003f9e06 br 100a604 <_malloc_r+0x460> + 100a78c: 00bffe04 movi r2,-8 + 100a790: a93ffd04 addi r4,r21,-12 + 100a794: 2088703a and r4,r4,r2 + 100a798: b10b883a add r5,r22,r4 + 100a79c: 00c00144 movi r3,5 + 100a7a0: 28c00215 stw r3,8(r5) + 100a7a4: 28c00115 stw r3,4(r5) + 100a7a8: b0800117 ldw r2,4(r22) + 100a7ac: 1080004c andi r2,r2,1 + 100a7b0: 2084b03a or r2,r4,r2 + 100a7b4: b0800115 stw r2,4(r22) + 100a7b8: 313fdd2e bgeu r6,r4,100a730 <_malloc_r+0x58c> + 100a7bc: b1400204 addi r5,r22,8 + 100a7c0: 9009883a mov r4,r18 + 100a7c4: 100f28c0 call 100f28c <_free_r> + 100a7c8: e4000217 ldw r16,8(fp) + 100a7cc: 003fd806 br 100a730 <_malloc_r+0x58c> + 100a7d0: 00800504 movi r2,20 + 100a7d4: 11001536 bltu r2,r4,100a82c <_malloc_r+0x688> + 100a7d8: 210016c4 addi r4,r4,91 + 100a7dc: 200690fa slli r3,r4,3 + 100a7e0: 003fa606 br 100a67c <_malloc_r+0x4d8> + 100a7e4: 8804d4ba srli r2,r17,18 + 100a7e8: 11801f04 addi r6,r2,124 + 100a7ec: 300490fa slli r2,r6,3 + 100a7f0: 003e9906 br 100a258 <_malloc_r+0xb4> + 100a7f4: 2009d0ba srai r4,r4,2 + 100a7f8: 014040b4 movhi r5,258 + 100a7fc: 2946f004 addi r5,r5,7104 + 100a800: 00c00044 movi r3,1 + 100a804: 28800117 ldw r2,4(r5) + 100a808: 1906983a sll r3,r3,r4 + 100a80c: 10c4b03a or r2,r2,r3 + 100a810: 28800115 stw r2,4(r5) + 100a814: 003fa306 br 100a6a4 <_malloc_r+0x500> + 100a818: 0027883a mov r19,zero + 100a81c: 00c00044 movi r3,1 + 100a820: 003f8606 br 100a63c <_malloc_r+0x498> + 100a824: d1200d15 stw r4,-32716(gp) + 100a828: 003f7306 br 100a5f8 <_malloc_r+0x454> + 100a82c: 00801504 movi r2,84 + 100a830: 11001936 bltu r2,r4,100a898 <_malloc_r+0x6f4> + 100a834: 2804d33a srli r2,r5,12 + 100a838: 11001b84 addi r4,r2,110 + 100a83c: 200690fa slli r3,r4,3 + 100a840: 003f8e06 br 100a67c <_malloc_r+0x4d8> + 100a844: 480b883a mov r5,r9 + 100a848: 6807883a mov r3,r13 + 100a84c: 288000cc andi r2,r5,3 + 100a850: 18fffe04 addi r3,r3,-8 + 100a854: 297fffc4 addi r5,r5,-1 + 100a858: 10001526 beq r2,zero,100a8b0 <_malloc_r+0x70c> + 100a85c: 18800217 ldw r2,8(r3) + 100a860: 10fffa26 beq r2,r3,100a84c <_malloc_r+0x6a8> + 100a864: 2109883a add r4,r4,r4 + 100a868: 393f1e36 bltu r7,r4,100a4e4 <_malloc_r+0x340> + 100a86c: 203f1d26 beq r4,zero,100a4e4 <_malloc_r+0x340> + 100a870: 21c4703a and r2,r4,r7 + 100a874: 10000226 beq r2,zero,100a880 <_malloc_r+0x6dc> + 100a878: 6013883a mov r9,r12 + 100a87c: 003ee106 br 100a404 <_malloc_r+0x260> + 100a880: 2109883a add r4,r4,r4 + 100a884: 3904703a and r2,r7,r4 + 100a888: 63000104 addi r12,r12,4 + 100a88c: 103ffc26 beq r2,zero,100a880 <_malloc_r+0x6dc> + 100a890: 6013883a mov r9,r12 + 100a894: 003edb06 br 100a404 <_malloc_r+0x260> + 100a898: 00805504 movi r2,340 + 100a89c: 11000836 bltu r2,r4,100a8c0 <_malloc_r+0x71c> + 100a8a0: 2804d3fa srli r2,r5,15 + 100a8a4: 11001dc4 addi r4,r2,119 + 100a8a8: 200690fa slli r3,r4,3 + 100a8ac: 003f7306 br 100a67c <_malloc_r+0x4d8> + 100a8b0: 0104303a nor r2,zero,r4 + 100a8b4: 388e703a and r7,r7,r2 + 100a8b8: e1c00115 stw r7,4(fp) + 100a8bc: 003fe906 br 100a864 <_malloc_r+0x6c0> + 100a8c0: 00815504 movi r2,1364 + 100a8c4: 1100032e bgeu r2,r4,100a8d4 <_malloc_r+0x730> + 100a8c8: 01001f84 movi r4,126 + 100a8cc: 00c0fc04 movi r3,1008 + 100a8d0: 003f6a06 br 100a67c <_malloc_r+0x4d8> + 100a8d4: 2804d4ba srli r2,r5,18 + 100a8d8: 11001f04 addi r4,r2,124 + 100a8dc: 200690fa slli r3,r4,3 + 100a8e0: 003f6606 br 100a67c <_malloc_r+0x4d8> + +0100a8e4 : + 100a8e4: 008000c4 movi r2,3 + 100a8e8: 29403fcc andi r5,r5,255 + 100a8ec: 2007883a mov r3,r4 + 100a8f0: 1180022e bgeu r2,r6,100a8fc + 100a8f4: 2084703a and r2,r4,r2 + 100a8f8: 10000b26 beq r2,zero,100a928 + 100a8fc: 313fffc4 addi r4,r6,-1 + 100a900: 3000051e bne r6,zero,100a918 + 100a904: 00002c06 br 100a9b8 + 100a908: 213fffc4 addi r4,r4,-1 + 100a90c: 00bfffc4 movi r2,-1 + 100a910: 18c00044 addi r3,r3,1 + 100a914: 20802826 beq r4,r2,100a9b8 + 100a918: 18800003 ldbu r2,0(r3) + 100a91c: 28bffa1e bne r5,r2,100a908 + 100a920: 1805883a mov r2,r3 + 100a924: f800283a ret + 100a928: 0011883a mov r8,zero + 100a92c: 0007883a mov r3,zero + 100a930: 01c00104 movi r7,4 + 100a934: 4004923a slli r2,r8,8 + 100a938: 18c00044 addi r3,r3,1 + 100a93c: 1151883a add r8,r2,r5 + 100a940: 19fffc1e bne r3,r7,100a934 + 100a944: 02bfbff4 movhi r10,65279 + 100a948: 52bfbfc4 addi r10,r10,-257 + 100a94c: 02602074 movhi r9,32897 + 100a950: 4a602004 addi r9,r9,-32640 + 100a954: 02c000c4 movi r11,3 + 100a958: 20800017 ldw r2,0(r4) + 100a95c: 31bfff04 addi r6,r6,-4 + 100a960: 200f883a mov r7,r4 + 100a964: 1204f03a xor r2,r2,r8 + 100a968: 1287883a add r3,r2,r10 + 100a96c: 1a46703a and r3,r3,r9 + 100a970: 0084303a nor r2,zero,r2 + 100a974: 10c4703a and r2,r2,r3 + 100a978: 10000b26 beq r2,zero,100a9a8 + 100a97c: 20800003 ldbu r2,0(r4) + 100a980: 28800f26 beq r5,r2,100a9c0 + 100a984: 20800043 ldbu r2,1(r4) + 100a988: 21c00044 addi r7,r4,1 + 100a98c: 28800c26 beq r5,r2,100a9c0 + 100a990: 20800083 ldbu r2,2(r4) + 100a994: 21c00084 addi r7,r4,2 + 100a998: 28800926 beq r5,r2,100a9c0 + 100a99c: 208000c3 ldbu r2,3(r4) + 100a9a0: 21c000c4 addi r7,r4,3 + 100a9a4: 28800626 beq r5,r2,100a9c0 + 100a9a8: 21000104 addi r4,r4,4 + 100a9ac: 59bfea36 bltu r11,r6,100a958 + 100a9b0: 2007883a mov r3,r4 + 100a9b4: 003fd106 br 100a8fc + 100a9b8: 0005883a mov r2,zero + 100a9bc: f800283a ret + 100a9c0: 3805883a mov r2,r7 + 100a9c4: f800283a ret + +0100a9c8 : + 100a9c8: 00c000c4 movi r3,3 + 100a9cc: 1980032e bgeu r3,r6,100a9dc + 100a9d0: 2144b03a or r2,r4,r5 + 100a9d4: 10c4703a and r2,r2,r3 + 100a9d8: 10000f26 beq r2,zero,100aa18 + 100a9dc: 31ffffc4 addi r7,r6,-1 + 100a9e0: 3000061e bne r6,zero,100a9fc + 100a9e4: 00000a06 br 100aa10 + 100a9e8: 39ffffc4 addi r7,r7,-1 + 100a9ec: 00bfffc4 movi r2,-1 + 100a9f0: 21000044 addi r4,r4,1 + 100a9f4: 29400044 addi r5,r5,1 + 100a9f8: 38800526 beq r7,r2,100aa10 + 100a9fc: 20c00003 ldbu r3,0(r4) + 100aa00: 28800003 ldbu r2,0(r5) + 100aa04: 18bff826 beq r3,r2,100a9e8 + 100aa08: 1885c83a sub r2,r3,r2 + 100aa0c: f800283a ret + 100aa10: 0005883a mov r2,zero + 100aa14: f800283a ret + 100aa18: 180f883a mov r7,r3 + 100aa1c: 20c00017 ldw r3,0(r4) + 100aa20: 28800017 ldw r2,0(r5) + 100aa24: 18bfed1e bne r3,r2,100a9dc + 100aa28: 31bfff04 addi r6,r6,-4 + 100aa2c: 21000104 addi r4,r4,4 + 100aa30: 29400104 addi r5,r5,4 + 100aa34: 39bff936 bltu r7,r6,100aa1c + 100aa38: 003fe806 br 100a9dc + +0100aa3c : + 100aa3c: 01c003c4 movi r7,15 + 100aa40: 2007883a mov r3,r4 + 100aa44: 3980032e bgeu r7,r6,100aa54 + 100aa48: 2904b03a or r2,r5,r4 + 100aa4c: 108000cc andi r2,r2,3 + 100aa50: 10000926 beq r2,zero,100aa78 + 100aa54: 30000626 beq r6,zero,100aa70 + 100aa58: 30cd883a add r6,r6,r3 + 100aa5c: 28800003 ldbu r2,0(r5) + 100aa60: 29400044 addi r5,r5,1 + 100aa64: 18800005 stb r2,0(r3) + 100aa68: 18c00044 addi r3,r3,1 + 100aa6c: 30fffb1e bne r6,r3,100aa5c + 100aa70: 2005883a mov r2,r4 + 100aa74: f800283a ret + 100aa78: 3811883a mov r8,r7 + 100aa7c: 200f883a mov r7,r4 + 100aa80: 28c00017 ldw r3,0(r5) + 100aa84: 31bffc04 addi r6,r6,-16 + 100aa88: 38c00015 stw r3,0(r7) + 100aa8c: 28800117 ldw r2,4(r5) + 100aa90: 38800115 stw r2,4(r7) + 100aa94: 28c00217 ldw r3,8(r5) + 100aa98: 38c00215 stw r3,8(r7) + 100aa9c: 28800317 ldw r2,12(r5) + 100aaa0: 29400404 addi r5,r5,16 + 100aaa4: 38800315 stw r2,12(r7) + 100aaa8: 39c00404 addi r7,r7,16 + 100aaac: 41bff436 bltu r8,r6,100aa80 + 100aab0: 008000c4 movi r2,3 + 100aab4: 1180072e bgeu r2,r6,100aad4 + 100aab8: 1007883a mov r3,r2 + 100aabc: 28800017 ldw r2,0(r5) + 100aac0: 31bfff04 addi r6,r6,-4 + 100aac4: 29400104 addi r5,r5,4 + 100aac8: 38800015 stw r2,0(r7) + 100aacc: 39c00104 addi r7,r7,4 + 100aad0: 19bffa36 bltu r3,r6,100aabc + 100aad4: 3807883a mov r3,r7 + 100aad8: 003fde06 br 100aa54 + +0100aadc : + 100aadc: 2807883a mov r3,r5 + 100aae0: 2011883a mov r8,r4 + 100aae4: 29000c2e bgeu r5,r4,100ab18 + 100aae8: 298f883a add r7,r5,r6 + 100aaec: 21c00a2e bgeu r4,r7,100ab18 + 100aaf0: 30000726 beq r6,zero,100ab10 + 100aaf4: 2187883a add r3,r4,r6 + 100aaf8: 198dc83a sub r6,r3,r6 + 100aafc: 39ffffc4 addi r7,r7,-1 + 100ab00: 38800003 ldbu r2,0(r7) + 100ab04: 18ffffc4 addi r3,r3,-1 + 100ab08: 18800005 stb r2,0(r3) + 100ab0c: 19bffb1e bne r3,r6,100aafc + 100ab10: 2005883a mov r2,r4 + 100ab14: f800283a ret + 100ab18: 01c003c4 movi r7,15 + 100ab1c: 39800a36 bltu r7,r6,100ab48 + 100ab20: 303ffb26 beq r6,zero,100ab10 + 100ab24: 400f883a mov r7,r8 + 100ab28: 320d883a add r6,r6,r8 + 100ab2c: 28800003 ldbu r2,0(r5) + 100ab30: 29400044 addi r5,r5,1 + 100ab34: 38800005 stb r2,0(r7) + 100ab38: 39c00044 addi r7,r7,1 + 100ab3c: 39bffb1e bne r7,r6,100ab2c + 100ab40: 2005883a mov r2,r4 + 100ab44: f800283a ret + 100ab48: 1904b03a or r2,r3,r4 + 100ab4c: 108000cc andi r2,r2,3 + 100ab50: 103ff31e bne r2,zero,100ab20 + 100ab54: 3811883a mov r8,r7 + 100ab58: 180b883a mov r5,r3 + 100ab5c: 200f883a mov r7,r4 + 100ab60: 28c00017 ldw r3,0(r5) + 100ab64: 31bffc04 addi r6,r6,-16 + 100ab68: 38c00015 stw r3,0(r7) + 100ab6c: 28800117 ldw r2,4(r5) + 100ab70: 38800115 stw r2,4(r7) + 100ab74: 28c00217 ldw r3,8(r5) + 100ab78: 38c00215 stw r3,8(r7) + 100ab7c: 28800317 ldw r2,12(r5) + 100ab80: 29400404 addi r5,r5,16 + 100ab84: 38800315 stw r2,12(r7) + 100ab88: 39c00404 addi r7,r7,16 + 100ab8c: 41bff436 bltu r8,r6,100ab60 + 100ab90: 008000c4 movi r2,3 + 100ab94: 1180072e bgeu r2,r6,100abb4 + 100ab98: 1007883a mov r3,r2 + 100ab9c: 28800017 ldw r2,0(r5) + 100aba0: 31bfff04 addi r6,r6,-4 + 100aba4: 29400104 addi r5,r5,4 + 100aba8: 38800015 stw r2,0(r7) + 100abac: 39c00104 addi r7,r7,4 + 100abb0: 19bffa36 bltu r3,r6,100ab9c + 100abb4: 3811883a mov r8,r7 + 100abb8: 003fd906 br 100ab20 + +0100abbc : + 100abbc: 008000c4 movi r2,3 + 100abc0: 29403fcc andi r5,r5,255 + 100abc4: 2007883a mov r3,r4 + 100abc8: 1180022e bgeu r2,r6,100abd4 + 100abcc: 2084703a and r2,r4,r2 + 100abd0: 10000826 beq r2,zero,100abf4 + 100abd4: 30000526 beq r6,zero,100abec + 100abd8: 2805883a mov r2,r5 + 100abdc: 30cd883a add r6,r6,r3 + 100abe0: 18800005 stb r2,0(r3) + 100abe4: 18c00044 addi r3,r3,1 + 100abe8: 19bffd1e bne r3,r6,100abe0 + 100abec: 2005883a mov r2,r4 + 100abf0: f800283a ret + 100abf4: 2804923a slli r2,r5,8 + 100abf8: 020003c4 movi r8,15 + 100abfc: 200f883a mov r7,r4 + 100ac00: 2884b03a or r2,r5,r2 + 100ac04: 1006943a slli r3,r2,16 + 100ac08: 10c6b03a or r3,r2,r3 + 100ac0c: 41800a2e bgeu r8,r6,100ac38 + 100ac10: 4005883a mov r2,r8 + 100ac14: 31bffc04 addi r6,r6,-16 + 100ac18: 38c00015 stw r3,0(r7) + 100ac1c: 38c00115 stw r3,4(r7) + 100ac20: 38c00215 stw r3,8(r7) + 100ac24: 38c00315 stw r3,12(r7) + 100ac28: 39c00404 addi r7,r7,16 + 100ac2c: 11bff936 bltu r2,r6,100ac14 + 100ac30: 008000c4 movi r2,3 + 100ac34: 1180052e bgeu r2,r6,100ac4c + 100ac38: 31bfff04 addi r6,r6,-4 + 100ac3c: 008000c4 movi r2,3 + 100ac40: 38c00015 stw r3,0(r7) + 100ac44: 39c00104 addi r7,r7,4 + 100ac48: 11bffb36 bltu r2,r6,100ac38 + 100ac4c: 3807883a mov r3,r7 + 100ac50: 003fe006 br 100abd4 + +0100ac54 : + 100ac54: defffb04 addi sp,sp,-20 + 100ac58: dfc00115 stw ra,4(sp) + 100ac5c: d9400215 stw r5,8(sp) + 100ac60: d9800315 stw r6,12(sp) + 100ac64: d9c00415 stw r7,16(sp) + 100ac68: 008040b4 movhi r2,258 + 100ac6c: 108dc804 addi r2,r2,14112 + 100ac70: 10c00017 ldw r3,0(r2) + 100ac74: 200b883a mov r5,r4 + 100ac78: d8800204 addi r2,sp,8 + 100ac7c: 19000217 ldw r4,8(r3) + 100ac80: 100d883a mov r6,r2 + 100ac84: d8800015 stw r2,0(sp) + 100ac88: 100d3440 call 100d344 <__vfprintf_internal> + 100ac8c: dfc00117 ldw ra,4(sp) + 100ac90: dec00504 addi sp,sp,20 + 100ac94: f800283a ret + +0100ac98 <_printf_r>: + 100ac98: defffc04 addi sp,sp,-16 + 100ac9c: dfc00115 stw ra,4(sp) + 100aca0: d9800215 stw r6,8(sp) + 100aca4: d9c00315 stw r7,12(sp) + 100aca8: 280d883a mov r6,r5 + 100acac: 21400217 ldw r5,8(r4) + 100acb0: d8c00204 addi r3,sp,8 + 100acb4: 180f883a mov r7,r3 + 100acb8: d8c00015 stw r3,0(sp) + 100acbc: 100b4980 call 100b498 <___vfprintf_internal_r> + 100acc0: dfc00117 ldw ra,4(sp) + 100acc4: dec00404 addi sp,sp,16 + 100acc8: f800283a ret + +0100accc : + 100accc: 008040b4 movhi r2,258 + 100acd0: 108dc804 addi r2,r2,14112 + 100acd4: 11800017 ldw r6,0(r2) + 100acd8: 200b883a mov r5,r4 + 100acdc: 3009883a mov r4,r6 + 100ace0: 31800217 ldw r6,8(r6) + 100ace4: 1010f0c1 jmpi 1010f0c <_putc_r> + +0100ace8 <_putchar_r>: + 100ace8: 21800217 ldw r6,8(r4) + 100acec: 1010f0c1 jmpi 1010f0c <_putc_r> + +0100acf0 <_puts_r>: + 100acf0: defff604 addi sp,sp,-40 + 100acf4: dc400715 stw r17,28(sp) + 100acf8: 2023883a mov r17,r4 + 100acfc: 2809883a mov r4,r5 + 100ad00: dfc00915 stw ra,36(sp) + 100ad04: dcc00815 stw r19,32(sp) + 100ad08: 2827883a mov r19,r5 + 100ad0c: 100b1640 call 100b164 + 100ad10: 89400217 ldw r5,8(r17) + 100ad14: 00c040b4 movhi r3,258 + 100ad18: 18c52e04 addi r3,r3,5304 + 100ad1c: 01c00044 movi r7,1 + 100ad20: 12000044 addi r8,r2,1 + 100ad24: d8c00515 stw r3,20(sp) + 100ad28: d9c00615 stw r7,24(sp) + 100ad2c: d8c00304 addi r3,sp,12 + 100ad30: 01c00084 movi r7,2 + 100ad34: 8809883a mov r4,r17 + 100ad38: d80d883a mov r6,sp + 100ad3c: d8c00015 stw r3,0(sp) + 100ad40: dcc00315 stw r19,12(sp) + 100ad44: da000215 stw r8,8(sp) + 100ad48: d9c00115 stw r7,4(sp) + 100ad4c: d8800415 stw r2,16(sp) + 100ad50: 100f5a00 call 100f5a0 <__sfvwrite_r> + 100ad54: 00ffffc4 movi r3,-1 + 100ad58: 10000626 beq r2,zero,100ad74 <_puts_r+0x84> + 100ad5c: 1805883a mov r2,r3 + 100ad60: dfc00917 ldw ra,36(sp) + 100ad64: dcc00817 ldw r19,32(sp) + 100ad68: dc400717 ldw r17,28(sp) + 100ad6c: dec00a04 addi sp,sp,40 + 100ad70: f800283a ret + 100ad74: 00c00284 movi r3,10 + 100ad78: 1805883a mov r2,r3 + 100ad7c: dfc00917 ldw ra,36(sp) + 100ad80: dcc00817 ldw r19,32(sp) + 100ad84: dc400717 ldw r17,28(sp) + 100ad88: dec00a04 addi sp,sp,40 + 100ad8c: f800283a ret + +0100ad90 : + 100ad90: 008040b4 movhi r2,258 + 100ad94: 108dc804 addi r2,r2,14112 + 100ad98: 200b883a mov r5,r4 + 100ad9c: 11000017 ldw r4,0(r2) + 100ada0: 100acf01 jmpi 100acf0 <_puts_r> + +0100ada4 <_sbrk_r>: + 100ada4: defffd04 addi sp,sp,-12 + 100ada8: dc000015 stw r16,0(sp) + 100adac: 040040b4 movhi r16,258 + 100adb0: 84150804 addi r16,r16,21536 + 100adb4: dc400115 stw r17,4(sp) + 100adb8: 80000015 stw zero,0(r16) + 100adbc: 2023883a mov r17,r4 + 100adc0: 2809883a mov r4,r5 + 100adc4: dfc00215 stw ra,8(sp) + 100adc8: 1014d5c0 call 1014d5c + 100adcc: 1007883a mov r3,r2 + 100add0: 00bfffc4 movi r2,-1 + 100add4: 18800626 beq r3,r2,100adf0 <_sbrk_r+0x4c> + 100add8: 1805883a mov r2,r3 + 100addc: dfc00217 ldw ra,8(sp) + 100ade0: dc400117 ldw r17,4(sp) + 100ade4: dc000017 ldw r16,0(sp) + 100ade8: dec00304 addi sp,sp,12 + 100adec: f800283a ret + 100adf0: 80800017 ldw r2,0(r16) + 100adf4: 103ff826 beq r2,zero,100add8 <_sbrk_r+0x34> + 100adf8: 88800015 stw r2,0(r17) + 100adfc: 1805883a mov r2,r3 + 100ae00: dfc00217 ldw ra,8(sp) + 100ae04: dc400117 ldw r17,4(sp) + 100ae08: dc000017 ldw r16,0(sp) + 100ae0c: dec00304 addi sp,sp,12 + 100ae10: f800283a ret + +0100ae14 <_raise_r>: + 100ae14: defffd04 addi sp,sp,-12 + 100ae18: 008007c4 movi r2,31 + 100ae1c: dc400115 stw r17,4(sp) + 100ae20: dc000015 stw r16,0(sp) + 100ae24: dfc00215 stw ra,8(sp) + 100ae28: 2821883a mov r16,r5 + 100ae2c: 2023883a mov r17,r4 + 100ae30: 11402736 bltu r2,r5,100aed0 <_raise_r+0xbc> + 100ae34: 20c0b717 ldw r3,732(r4) + 100ae38: 18001326 beq r3,zero,100ae88 <_raise_r+0x74> + 100ae3c: 2945883a add r2,r5,r5 + 100ae40: 1085883a add r2,r2,r2 + 100ae44: 188b883a add r5,r3,r2 + 100ae48: 28c00017 ldw r3,0(r5) + 100ae4c: 18000e26 beq r3,zero,100ae88 <_raise_r+0x74> + 100ae50: 01000044 movi r4,1 + 100ae54: 19000526 beq r3,r4,100ae6c <_raise_r+0x58> + 100ae58: 00bfffc4 movi r2,-1 + 100ae5c: 18801326 beq r3,r2,100aeac <_raise_r+0x98> + 100ae60: 28000015 stw zero,0(r5) + 100ae64: 8009883a mov r4,r16 + 100ae68: 183ee83a callr r3 + 100ae6c: 0007883a mov r3,zero + 100ae70: 1805883a mov r2,r3 + 100ae74: dfc00217 ldw ra,8(sp) + 100ae78: dc400117 ldw r17,4(sp) + 100ae7c: dc000017 ldw r16,0(sp) + 100ae80: dec00304 addi sp,sp,12 + 100ae84: f800283a ret + 100ae88: 100b0ec0 call 100b0ec <_getpid_r> + 100ae8c: 100b883a mov r5,r2 + 100ae90: 8809883a mov r4,r17 + 100ae94: 800d883a mov r6,r16 + 100ae98: dfc00217 ldw ra,8(sp) + 100ae9c: dc400117 ldw r17,4(sp) + 100aea0: dc000017 ldw r16,0(sp) + 100aea4: dec00304 addi sp,sp,12 + 100aea8: 100b0f01 jmpi 100b0f0 <_kill_r> + 100aeac: 2007883a mov r3,r4 + 100aeb0: 00800584 movi r2,22 + 100aeb4: 88800015 stw r2,0(r17) + 100aeb8: 1805883a mov r2,r3 + 100aebc: dfc00217 ldw ra,8(sp) + 100aec0: dc400117 ldw r17,4(sp) + 100aec4: dc000017 ldw r16,0(sp) + 100aec8: dec00304 addi sp,sp,12 + 100aecc: f800283a ret + 100aed0: 00800584 movi r2,22 + 100aed4: 00ffffc4 movi r3,-1 + 100aed8: 20800015 stw r2,0(r4) + 100aedc: 003fe406 br 100ae70 <_raise_r+0x5c> + +0100aee0 : + 100aee0: 008040b4 movhi r2,258 + 100aee4: 108dc804 addi r2,r2,14112 + 100aee8: 200b883a mov r5,r4 + 100aeec: 11000017 ldw r4,0(r2) + 100aef0: 100ae141 jmpi 100ae14 <_raise_r> + +0100aef4 <_init_signal_r>: + 100aef4: 2080b717 ldw r2,732(r4) + 100aef8: defffe04 addi sp,sp,-8 + 100aefc: dc000015 stw r16,0(sp) + 100af00: dfc00115 stw ra,4(sp) + 100af04: 2021883a mov r16,r4 + 100af08: 10000526 beq r2,zero,100af20 <_init_signal_r+0x2c> + 100af0c: 0005883a mov r2,zero + 100af10: dfc00117 ldw ra,4(sp) + 100af14: dc000017 ldw r16,0(sp) + 100af18: dec00204 addi sp,sp,8 + 100af1c: f800283a ret + 100af20: 01402004 movi r5,128 + 100af24: 100a1a40 call 100a1a4 <_malloc_r> + 100af28: 1009883a mov r4,r2 + 100af2c: 8080b715 stw r2,732(r16) + 100af30: 10000726 beq r2,zero,100af50 <_init_signal_r+0x5c> + 100af34: 0007883a mov r3,zero + 100af38: 01402004 movi r5,128 + 100af3c: 20c5883a add r2,r4,r3 + 100af40: 18c00104 addi r3,r3,4 + 100af44: 10000015 stw zero,0(r2) + 100af48: 197ffc1e bne r3,r5,100af3c <_init_signal_r+0x48> + 100af4c: 003fef06 br 100af0c <_init_signal_r+0x18> + 100af50: 00bfffc4 movi r2,-1 + 100af54: 003fee06 br 100af10 <_init_signal_r+0x1c> + +0100af58 <_init_signal>: + 100af58: 008040b4 movhi r2,258 + 100af5c: 108dc804 addi r2,r2,14112 + 100af60: 11000017 ldw r4,0(r2) + 100af64: 100aef41 jmpi 100aef4 <_init_signal_r> + +0100af68 <__sigtramp_r>: + 100af68: defffd04 addi sp,sp,-12 + 100af6c: 008007c4 movi r2,31 + 100af70: dc000115 stw r16,4(sp) + 100af74: dfc00215 stw ra,8(sp) + 100af78: 2021883a mov r16,r4 + 100af7c: 11401336 bltu r2,r5,100afcc <__sigtramp_r+0x64> + 100af80: 20c0b717 ldw r3,732(r4) + 100af84: 18001f26 beq r3,zero,100b004 <__sigtramp_r+0x9c> + 100af88: 2945883a add r2,r5,r5 + 100af8c: 1085883a add r2,r2,r2 + 100af90: 10c9883a add r4,r2,r3 + 100af94: 20c00017 ldw r3,0(r4) + 100af98: 18001626 beq r3,zero,100aff4 <__sigtramp_r+0x8c> + 100af9c: 00bfffc4 movi r2,-1 + 100afa0: 18801626 beq r3,r2,100affc <__sigtramp_r+0x94> + 100afa4: 00800044 movi r2,1 + 100afa8: 18800d26 beq r3,r2,100afe0 <__sigtramp_r+0x78> + 100afac: 20000015 stw zero,0(r4) + 100afb0: 2809883a mov r4,r5 + 100afb4: 183ee83a callr r3 + 100afb8: 0005883a mov r2,zero + 100afbc: dfc00217 ldw ra,8(sp) + 100afc0: dc000117 ldw r16,4(sp) + 100afc4: dec00304 addi sp,sp,12 + 100afc8: f800283a ret + 100afcc: 00bfffc4 movi r2,-1 + 100afd0: dfc00217 ldw ra,8(sp) + 100afd4: dc000117 ldw r16,4(sp) + 100afd8: dec00304 addi sp,sp,12 + 100afdc: f800283a ret + 100afe0: 008000c4 movi r2,3 + 100afe4: dfc00217 ldw ra,8(sp) + 100afe8: dc000117 ldw r16,4(sp) + 100afec: dec00304 addi sp,sp,12 + 100aff0: f800283a ret + 100aff4: 00800044 movi r2,1 + 100aff8: 003ff006 br 100afbc <__sigtramp_r+0x54> + 100affc: 00800084 movi r2,2 + 100b000: 003fee06 br 100afbc <__sigtramp_r+0x54> + 100b004: d9400015 stw r5,0(sp) + 100b008: 100aef40 call 100aef4 <_init_signal_r> + 100b00c: d9400017 ldw r5,0(sp) + 100b010: 103fee1e bne r2,zero,100afcc <__sigtramp_r+0x64> + 100b014: 80c0b717 ldw r3,732(r16) + 100b018: 003fdb06 br 100af88 <__sigtramp_r+0x20> + +0100b01c <__sigtramp>: + 100b01c: 008040b4 movhi r2,258 + 100b020: 108dc804 addi r2,r2,14112 + 100b024: 200b883a mov r5,r4 + 100b028: 11000017 ldw r4,0(r2) + 100b02c: 100af681 jmpi 100af68 <__sigtramp_r> + +0100b030 <_signal_r>: + 100b030: defffc04 addi sp,sp,-16 + 100b034: 008007c4 movi r2,31 + 100b038: dc800215 stw r18,8(sp) + 100b03c: dc400115 stw r17,4(sp) + 100b040: dc000015 stw r16,0(sp) + 100b044: dfc00315 stw ra,12(sp) + 100b048: 2823883a mov r17,r5 + 100b04c: 00ffffc4 movi r3,-1 + 100b050: 3025883a mov r18,r6 + 100b054: 2021883a mov r16,r4 + 100b058: 1140092e bgeu r2,r5,100b080 <_signal_r+0x50> + 100b05c: 00800584 movi r2,22 + 100b060: 20800015 stw r2,0(r4) + 100b064: 1805883a mov r2,r3 + 100b068: dfc00317 ldw ra,12(sp) + 100b06c: dc800217 ldw r18,8(sp) + 100b070: dc400117 ldw r17,4(sp) + 100b074: dc000017 ldw r16,0(sp) + 100b078: dec00404 addi sp,sp,16 + 100b07c: f800283a ret + 100b080: 2140b717 ldw r5,732(r4) + 100b084: 28000c26 beq r5,zero,100b0b8 <_signal_r+0x88> + 100b088: 8c45883a add r2,r17,r17 + 100b08c: 1085883a add r2,r2,r2 + 100b090: 1145883a add r2,r2,r5 + 100b094: 10c00017 ldw r3,0(r2) + 100b098: 14800015 stw r18,0(r2) + 100b09c: 1805883a mov r2,r3 + 100b0a0: dfc00317 ldw ra,12(sp) + 100b0a4: dc800217 ldw r18,8(sp) + 100b0a8: dc400117 ldw r17,4(sp) + 100b0ac: dc000017 ldw r16,0(sp) + 100b0b0: dec00404 addi sp,sp,16 + 100b0b4: f800283a ret + 100b0b8: 100aef40 call 100aef4 <_init_signal_r> + 100b0bc: 1000021e bne r2,zero,100b0c8 <_signal_r+0x98> + 100b0c0: 8140b717 ldw r5,732(r16) + 100b0c4: 003ff006 br 100b088 <_signal_r+0x58> + 100b0c8: 00ffffc4 movi r3,-1 + 100b0cc: 003fe506 br 100b064 <_signal_r+0x34> + +0100b0d0 : + 100b0d0: 018040b4 movhi r6,258 + 100b0d4: 318dc804 addi r6,r6,14112 + 100b0d8: 2007883a mov r3,r4 + 100b0dc: 31000017 ldw r4,0(r6) + 100b0e0: 280d883a mov r6,r5 + 100b0e4: 180b883a mov r5,r3 + 100b0e8: 100b0301 jmpi 100b030 <_signal_r> + +0100b0ec <_getpid_r>: + 100b0ec: 10145981 jmpi 1014598 + +0100b0f0 <_kill_r>: + 100b0f0: defffd04 addi sp,sp,-12 + 100b0f4: dc000015 stw r16,0(sp) + 100b0f8: 040040b4 movhi r16,258 + 100b0fc: 84150804 addi r16,r16,21536 + 100b100: dc400115 stw r17,4(sp) + 100b104: 80000015 stw zero,0(r16) + 100b108: 2023883a mov r17,r4 + 100b10c: 2809883a mov r4,r5 + 100b110: 300b883a mov r5,r6 + 100b114: dfc00215 stw ra,8(sp) + 100b118: 10146d80 call 10146d8 + 100b11c: 1007883a mov r3,r2 + 100b120: 00bfffc4 movi r2,-1 + 100b124: 18800626 beq r3,r2,100b140 <_kill_r+0x50> + 100b128: 1805883a mov r2,r3 + 100b12c: dfc00217 ldw ra,8(sp) + 100b130: dc400117 ldw r17,4(sp) + 100b134: dc000017 ldw r16,0(sp) + 100b138: dec00304 addi sp,sp,12 + 100b13c: f800283a ret + 100b140: 80800017 ldw r2,0(r16) + 100b144: 103ff826 beq r2,zero,100b128 <_kill_r+0x38> + 100b148: 88800015 stw r2,0(r17) + 100b14c: 1805883a mov r2,r3 + 100b150: dfc00217 ldw ra,8(sp) + 100b154: dc400117 ldw r17,4(sp) + 100b158: dc000017 ldw r16,0(sp) + 100b15c: dec00304 addi sp,sp,12 + 100b160: f800283a ret + +0100b164 : + 100b164: 208000cc andi r2,r4,3 + 100b168: 2011883a mov r8,r4 + 100b16c: 1000161e bne r2,zero,100b1c8 + 100b170: 20c00017 ldw r3,0(r4) + 100b174: 017fbff4 movhi r5,65279 + 100b178: 297fbfc4 addi r5,r5,-257 + 100b17c: 01e02074 movhi r7,32897 + 100b180: 39e02004 addi r7,r7,-32640 + 100b184: 1945883a add r2,r3,r5 + 100b188: 11c4703a and r2,r2,r7 + 100b18c: 00c6303a nor r3,zero,r3 + 100b190: 1886703a and r3,r3,r2 + 100b194: 18000c1e bne r3,zero,100b1c8 + 100b198: 280d883a mov r6,r5 + 100b19c: 380b883a mov r5,r7 + 100b1a0: 21000104 addi r4,r4,4 + 100b1a4: 20800017 ldw r2,0(r4) + 100b1a8: 1187883a add r3,r2,r6 + 100b1ac: 1946703a and r3,r3,r5 + 100b1b0: 0084303a nor r2,zero,r2 + 100b1b4: 10c4703a and r2,r2,r3 + 100b1b8: 103ff926 beq r2,zero,100b1a0 + 100b1bc: 20800007 ldb r2,0(r4) + 100b1c0: 10000326 beq r2,zero,100b1d0 + 100b1c4: 21000044 addi r4,r4,1 + 100b1c8: 20800007 ldb r2,0(r4) + 100b1cc: 103ffd1e bne r2,zero,100b1c4 + 100b1d0: 2205c83a sub r2,r4,r8 + 100b1d4: f800283a ret + +0100b1d8 <_strtol_r>: + 100b1d8: defff304 addi sp,sp,-52 + 100b1dc: 008040b4 movhi r2,258 + 100b1e0: 108dc704 addi r2,r2,14108 + 100b1e4: dcc00615 stw r19,24(sp) + 100b1e8: 14c00017 ldw r19,0(r2) + 100b1ec: ddc00a15 stw r23,40(sp) + 100b1f0: dc000315 stw r16,12(sp) + 100b1f4: dfc00c15 stw ra,48(sp) + 100b1f8: df000b15 stw fp,44(sp) + 100b1fc: dd800915 stw r22,36(sp) + 100b200: dd400815 stw r21,32(sp) + 100b204: dd000715 stw r20,28(sp) + 100b208: dc800515 stw r18,20(sp) + 100b20c: dc400415 stw r17,16(sp) + 100b210: 282f883a mov r23,r5 + 100b214: d9000015 stw r4,0(sp) + 100b218: d9800115 stw r6,4(sp) + 100b21c: 2821883a mov r16,r5 + 100b220: 84400007 ldb r17,0(r16) + 100b224: 84000044 addi r16,r16,1 + 100b228: 9c47883a add r3,r19,r17 + 100b22c: 18800003 ldbu r2,0(r3) + 100b230: 1080020c andi r2,r2,8 + 100b234: 103ffa1e bne r2,zero,100b220 <_strtol_r+0x48> + 100b238: 00800b44 movi r2,45 + 100b23c: 88805c26 beq r17,r2,100b3b0 <_strtol_r+0x1d8> + 100b240: 00800ac4 movi r2,43 + 100b244: 88805726 beq r17,r2,100b3a4 <_strtol_r+0x1cc> + 100b248: 0039883a mov fp,zero + 100b24c: 3807003a cmpeq r3,r7,zero + 100b250: 1800431e bne r3,zero,100b360 <_strtol_r+0x188> + 100b254: 00800404 movi r2,16 + 100b258: 38804126 beq r7,r2,100b360 <_strtol_r+0x188> + 100b25c: 3829883a mov r20,r7 + 100b260: e02cc03a cmpne r22,fp,zero + 100b264: b0004b1e bne r22,zero,100b394 <_strtol_r+0x1bc> + 100b268: 04a00034 movhi r18,32768 + 100b26c: 94bfffc4 addi r18,r18,-1 + 100b270: 9009883a mov r4,r18 + 100b274: a00b883a mov r5,r20 + 100b278: d9c00215 stw r7,8(sp) + 100b27c: 1013c3c0 call 1013c3c <__umodsi3> + 100b280: 9009883a mov r4,r18 + 100b284: a00b883a mov r5,r20 + 100b288: 102b883a mov r21,r2 + 100b28c: 1013c340 call 1013c34 <__udivsi3> + 100b290: 1011883a mov r8,r2 + 100b294: 9c45883a add r2,r19,r17 + 100b298: 11000003 ldbu r4,0(r2) + 100b29c: 000b883a mov r5,zero + 100b2a0: 000d883a mov r6,zero + 100b2a4: 20c0010c andi r3,r4,4 + 100b2a8: d9c00217 ldw r7,8(sp) + 100b2ac: 18000e26 beq r3,zero,100b2e8 <_strtol_r+0x110> + 100b2b0: 88fff404 addi r3,r17,-48 + 100b2b4: 19c0140e bge r3,r7,100b308 <_strtol_r+0x130> + 100b2b8: 30003116 blt r6,zero,100b380 <_strtol_r+0x1a8> + 100b2bc: 41403036 bltu r8,r5,100b380 <_strtol_r+0x1a8> + 100b2c0: 2a002e26 beq r5,r8,100b37c <_strtol_r+0x1a4> + 100b2c4: 2d05383a mul r2,r5,r20 + 100b2c8: 01800044 movi r6,1 + 100b2cc: 10cb883a add r5,r2,r3 + 100b2d0: 84400007 ldb r17,0(r16) + 100b2d4: 84000044 addi r16,r16,1 + 100b2d8: 9c45883a add r2,r19,r17 + 100b2dc: 11000003 ldbu r4,0(r2) + 100b2e0: 20c0010c andi r3,r4,4 + 100b2e4: 183ff21e bne r3,zero,100b2b0 <_strtol_r+0xd8> + 100b2e8: 208000cc andi r2,r4,3 + 100b2ec: 10000626 beq r2,zero,100b308 <_strtol_r+0x130> + 100b2f0: 2080004c andi r2,r4,1 + 100b2f4: 1005003a cmpeq r2,r2,zero + 100b2f8: 1000231e bne r2,zero,100b388 <_strtol_r+0x1b0> + 100b2fc: 00800dc4 movi r2,55 + 100b300: 8887c83a sub r3,r17,r2 + 100b304: 19ffec16 blt r3,r7,100b2b8 <_strtol_r+0xe0> + 100b308: 30002d16 blt r6,zero,100b3c0 <_strtol_r+0x1e8> + 100b30c: b000231e bne r22,zero,100b39c <_strtol_r+0x1c4> + 100b310: 2807883a mov r3,r5 + 100b314: d8800117 ldw r2,4(sp) + 100b318: 10000426 beq r2,zero,100b32c <_strtol_r+0x154> + 100b31c: 30000126 beq r6,zero,100b324 <_strtol_r+0x14c> + 100b320: 85ffffc4 addi r23,r16,-1 + 100b324: d9000117 ldw r4,4(sp) + 100b328: 25c00015 stw r23,0(r4) + 100b32c: 1805883a mov r2,r3 + 100b330: dfc00c17 ldw ra,48(sp) + 100b334: df000b17 ldw fp,44(sp) + 100b338: ddc00a17 ldw r23,40(sp) + 100b33c: dd800917 ldw r22,36(sp) + 100b340: dd400817 ldw r21,32(sp) + 100b344: dd000717 ldw r20,28(sp) + 100b348: dcc00617 ldw r19,24(sp) + 100b34c: dc800517 ldw r18,20(sp) + 100b350: dc400417 ldw r17,16(sp) + 100b354: dc000317 ldw r16,12(sp) + 100b358: dec00d04 addi sp,sp,52 + 100b35c: f800283a ret + 100b360: 00800c04 movi r2,48 + 100b364: 88801d26 beq r17,r2,100b3dc <_strtol_r+0x204> + 100b368: 183fbc26 beq r3,zero,100b25c <_strtol_r+0x84> + 100b36c: 00800c04 movi r2,48 + 100b370: 88802726 beq r17,r2,100b410 <_strtol_r+0x238> + 100b374: 01c00284 movi r7,10 + 100b378: 003fb806 br 100b25c <_strtol_r+0x84> + 100b37c: a8ffd10e bge r21,r3,100b2c4 <_strtol_r+0xec> + 100b380: 01bfffc4 movi r6,-1 + 100b384: 003fd206 br 100b2d0 <_strtol_r+0xf8> + 100b388: 008015c4 movi r2,87 + 100b38c: 8887c83a sub r3,r17,r2 + 100b390: 003fdc06 br 100b304 <_strtol_r+0x12c> + 100b394: 04a00034 movhi r18,32768 + 100b398: 003fb506 br 100b270 <_strtol_r+0x98> + 100b39c: 0147c83a sub r3,zero,r5 + 100b3a0: 003fdc06 br 100b314 <_strtol_r+0x13c> + 100b3a4: 84400007 ldb r17,0(r16) + 100b3a8: 84000044 addi r16,r16,1 + 100b3ac: 003fa606 br 100b248 <_strtol_r+0x70> + 100b3b0: 84400007 ldb r17,0(r16) + 100b3b4: 07000044 movi fp,1 + 100b3b8: 84000044 addi r16,r16,1 + 100b3bc: 003fa306 br 100b24c <_strtol_r+0x74> + 100b3c0: e005003a cmpeq r2,fp,zero + 100b3c4: 10000f1e bne r2,zero,100b404 <_strtol_r+0x22c> + 100b3c8: 00e00034 movhi r3,32768 + 100b3cc: d9000017 ldw r4,0(sp) + 100b3d0: 00800884 movi r2,34 + 100b3d4: 20800015 stw r2,0(r4) + 100b3d8: 003fce06 br 100b314 <_strtol_r+0x13c> + 100b3dc: 81000007 ldb r4,0(r16) + 100b3e0: 00801e04 movi r2,120 + 100b3e4: 20800226 beq r4,r2,100b3f0 <_strtol_r+0x218> + 100b3e8: 00801604 movi r2,88 + 100b3ec: 20bfde1e bne r4,r2,100b368 <_strtol_r+0x190> + 100b3f0: 84400047 ldb r17,1(r16) + 100b3f4: 01c00404 movi r7,16 + 100b3f8: 84000084 addi r16,r16,2 + 100b3fc: 3829883a mov r20,r7 + 100b400: 003f9706 br 100b260 <_strtol_r+0x88> + 100b404: 00e00034 movhi r3,32768 + 100b408: 18ffffc4 addi r3,r3,-1 + 100b40c: 003fef06 br 100b3cc <_strtol_r+0x1f4> + 100b410: 01c00204 movi r7,8 + 100b414: 3829883a mov r20,r7 + 100b418: 003f9106 br 100b260 <_strtol_r+0x88> + +0100b41c : + 100b41c: 008040b4 movhi r2,258 + 100b420: 108dc804 addi r2,r2,14112 + 100b424: 2013883a mov r9,r4 + 100b428: 11000017 ldw r4,0(r2) + 100b42c: 2805883a mov r2,r5 + 100b430: 300f883a mov r7,r6 + 100b434: 480b883a mov r5,r9 + 100b438: 100d883a mov r6,r2 + 100b43c: 100b1d81 jmpi 100b1d8 <_strtol_r> + +0100b440 <__sprint_r>: + 100b440: 30800217 ldw r2,8(r6) + 100b444: defffe04 addi sp,sp,-8 + 100b448: dc000015 stw r16,0(sp) + 100b44c: dfc00115 stw ra,4(sp) + 100b450: 3021883a mov r16,r6 + 100b454: 0007883a mov r3,zero + 100b458: 1000061e bne r2,zero,100b474 <__sprint_r+0x34> + 100b45c: 1805883a mov r2,r3 + 100b460: 30000115 stw zero,4(r6) + 100b464: dfc00117 ldw ra,4(sp) + 100b468: dc000017 ldw r16,0(sp) + 100b46c: dec00204 addi sp,sp,8 + 100b470: f800283a ret + 100b474: 100f5a00 call 100f5a0 <__sfvwrite_r> + 100b478: 1007883a mov r3,r2 + 100b47c: 1805883a mov r2,r3 + 100b480: 80000115 stw zero,4(r16) + 100b484: 80000215 stw zero,8(r16) + 100b488: dfc00117 ldw ra,4(sp) + 100b48c: dc000017 ldw r16,0(sp) + 100b490: dec00204 addi sp,sp,8 + 100b494: f800283a ret + +0100b498 <___vfprintf_internal_r>: + 100b498: defea404 addi sp,sp,-1392 + 100b49c: dd815815 stw r22,1376(sp) + 100b4a0: dc015215 stw r16,1352(sp) + 100b4a4: d9c15115 stw r7,1348(sp) + 100b4a8: dfc15b15 stw ra,1388(sp) + 100b4ac: df015a15 stw fp,1384(sp) + 100b4b0: ddc15915 stw r23,1380(sp) + 100b4b4: dd415715 stw r21,1372(sp) + 100b4b8: dd015615 stw r20,1368(sp) + 100b4bc: dcc15515 stw r19,1364(sp) + 100b4c0: dc815415 stw r18,1360(sp) + 100b4c4: dc415315 stw r17,1356(sp) + 100b4c8: 282d883a mov r22,r5 + 100b4cc: 3021883a mov r16,r6 + 100b4d0: d9014f15 stw r4,1340(sp) + 100b4d4: 100fbc40 call 100fbc4 <_localeconv_r> + 100b4d8: 10800017 ldw r2,0(r2) + 100b4dc: d9c15117 ldw r7,1348(sp) + 100b4e0: d8814915 stw r2,1316(sp) + 100b4e4: d8814f17 ldw r2,1340(sp) + 100b4e8: 10000226 beq r2,zero,100b4f4 <___vfprintf_internal_r+0x5c> + 100b4ec: 10800e17 ldw r2,56(r2) + 100b4f0: 10020d26 beq r2,zero,100bd28 <___vfprintf_internal_r+0x890> + 100b4f4: b080030b ldhu r2,12(r22) + 100b4f8: 1080020c andi r2,r2,8 + 100b4fc: 10020e26 beq r2,zero,100bd38 <___vfprintf_internal_r+0x8a0> + 100b500: b0800417 ldw r2,16(r22) + 100b504: 10020c26 beq r2,zero,100bd38 <___vfprintf_internal_r+0x8a0> + 100b508: b200030b ldhu r8,12(r22) + 100b50c: 00800284 movi r2,10 + 100b510: 40c0068c andi r3,r8,26 + 100b514: 18802f1e bne r3,r2,100b5d4 <___vfprintf_internal_r+0x13c> + 100b518: b080038f ldh r2,14(r22) + 100b51c: 10002d16 blt r2,zero,100b5d4 <___vfprintf_internal_r+0x13c> + 100b520: b240038b ldhu r9,14(r22) + 100b524: b2800717 ldw r10,28(r22) + 100b528: b2c00917 ldw r11,36(r22) + 100b52c: d9014f17 ldw r4,1340(sp) + 100b530: dc402904 addi r17,sp,164 + 100b534: d8804004 addi r2,sp,256 + 100b538: 00c10004 movi r3,1024 + 100b53c: 423fff4c andi r8,r8,65533 + 100b540: 800d883a mov r6,r16 + 100b544: 880b883a mov r5,r17 + 100b548: da002c0d sth r8,176(sp) + 100b54c: da402c8d sth r9,178(sp) + 100b550: da803015 stw r10,192(sp) + 100b554: dac03215 stw r11,200(sp) + 100b558: d8802d15 stw r2,180(sp) + 100b55c: d8c02e15 stw r3,184(sp) + 100b560: d8802915 stw r2,164(sp) + 100b564: d8c02b15 stw r3,172(sp) + 100b568: d8002f15 stw zero,188(sp) + 100b56c: 100b4980 call 100b498 <___vfprintf_internal_r> + 100b570: d8814b15 stw r2,1324(sp) + 100b574: 10000416 blt r2,zero,100b588 <___vfprintf_internal_r+0xf0> + 100b578: d9014f17 ldw r4,1340(sp) + 100b57c: 880b883a mov r5,r17 + 100b580: 100ec700 call 100ec70 <_fflush_r> + 100b584: 1002321e bne r2,zero,100be50 <___vfprintf_internal_r+0x9b8> + 100b588: d8802c0b ldhu r2,176(sp) + 100b58c: 1080100c andi r2,r2,64 + 100b590: 10000326 beq r2,zero,100b5a0 <___vfprintf_internal_r+0x108> + 100b594: b080030b ldhu r2,12(r22) + 100b598: 10801014 ori r2,r2,64 + 100b59c: b080030d sth r2,12(r22) + 100b5a0: d8814b17 ldw r2,1324(sp) + 100b5a4: dfc15b17 ldw ra,1388(sp) + 100b5a8: df015a17 ldw fp,1384(sp) + 100b5ac: ddc15917 ldw r23,1380(sp) + 100b5b0: dd815817 ldw r22,1376(sp) + 100b5b4: dd415717 ldw r21,1372(sp) + 100b5b8: dd015617 ldw r20,1368(sp) + 100b5bc: dcc15517 ldw r19,1364(sp) + 100b5c0: dc815417 ldw r18,1360(sp) + 100b5c4: dc415317 ldw r17,1356(sp) + 100b5c8: dc015217 ldw r16,1352(sp) + 100b5cc: dec15c04 addi sp,sp,1392 + 100b5d0: f800283a ret + 100b5d4: 0005883a mov r2,zero + 100b5d8: 0007883a mov r3,zero + 100b5dc: dd401904 addi r21,sp,100 + 100b5e0: d8814215 stw r2,1288(sp) + 100b5e4: 802f883a mov r23,r16 + 100b5e8: d8c14315 stw r3,1292(sp) + 100b5ec: d8014b15 stw zero,1324(sp) + 100b5f0: d8014815 stw zero,1312(sp) + 100b5f4: d8014415 stw zero,1296(sp) + 100b5f8: d8014715 stw zero,1308(sp) + 100b5fc: dd400c15 stw r21,48(sp) + 100b600: d8000e15 stw zero,56(sp) + 100b604: d8000d15 stw zero,52(sp) + 100b608: b8800007 ldb r2,0(r23) + 100b60c: 10001926 beq r2,zero,100b674 <___vfprintf_internal_r+0x1dc> + 100b610: 00c00944 movi r3,37 + 100b614: 10c01726 beq r2,r3,100b674 <___vfprintf_internal_r+0x1dc> + 100b618: b821883a mov r16,r23 + 100b61c: 00000106 br 100b624 <___vfprintf_internal_r+0x18c> + 100b620: 10c00326 beq r2,r3,100b630 <___vfprintf_internal_r+0x198> + 100b624: 84000044 addi r16,r16,1 + 100b628: 80800007 ldb r2,0(r16) + 100b62c: 103ffc1e bne r2,zero,100b620 <___vfprintf_internal_r+0x188> + 100b630: 85e7c83a sub r19,r16,r23 + 100b634: 98000e26 beq r19,zero,100b670 <___vfprintf_internal_r+0x1d8> + 100b638: dc800e17 ldw r18,56(sp) + 100b63c: dc400d17 ldw r17,52(sp) + 100b640: 008001c4 movi r2,7 + 100b644: 94e5883a add r18,r18,r19 + 100b648: 8c400044 addi r17,r17,1 + 100b64c: adc00015 stw r23,0(r21) + 100b650: dc800e15 stw r18,56(sp) + 100b654: acc00115 stw r19,4(r21) + 100b658: dc400d15 stw r17,52(sp) + 100b65c: 14428b16 blt r2,r17,100c08c <___vfprintf_internal_r+0xbf4> + 100b660: ad400204 addi r21,r21,8 + 100b664: d9014b17 ldw r4,1324(sp) + 100b668: 24c9883a add r4,r4,r19 + 100b66c: d9014b15 stw r4,1324(sp) + 100b670: 802f883a mov r23,r16 + 100b674: b8800007 ldb r2,0(r23) + 100b678: 10013c26 beq r2,zero,100bb6c <___vfprintf_internal_r+0x6d4> + 100b67c: bdc00044 addi r23,r23,1 + 100b680: d8000405 stb zero,16(sp) + 100b684: b8c00007 ldb r3,0(r23) + 100b688: 04ffffc4 movi r19,-1 + 100b68c: d8014c15 stw zero,1328(sp) + 100b690: d8014a15 stw zero,1320(sp) + 100b694: d8c14d15 stw r3,1332(sp) + 100b698: bdc00044 addi r23,r23,1 + 100b69c: d9414d17 ldw r5,1332(sp) + 100b6a0: 00801604 movi r2,88 + 100b6a4: 28fff804 addi r3,r5,-32 + 100b6a8: 10c06036 bltu r2,r3,100b82c <___vfprintf_internal_r+0x394> + 100b6ac: 18c5883a add r2,r3,r3 + 100b6b0: 1085883a add r2,r2,r2 + 100b6b4: 00c04074 movhi r3,257 + 100b6b8: 18edb204 addi r3,r3,-18744 + 100b6bc: 10c5883a add r2,r2,r3 + 100b6c0: 11000017 ldw r4,0(r2) + 100b6c4: 2000683a jmp r4 + 100b6c8: 0100c63c xorhi r4,zero,792 + 100b6cc: 0100b82c andhi r4,zero,736 + 100b6d0: 0100b82c andhi r4,zero,736 + 100b6d4: 0100c628 cmpgeui r4,zero,792 + 100b6d8: 0100b82c andhi r4,zero,736 + 100b6dc: 0100b82c andhi r4,zero,736 + 100b6e0: 0100b82c andhi r4,zero,736 + 100b6e4: 0100b82c andhi r4,zero,736 + 100b6e8: 0100b82c andhi r4,zero,736 + 100b6ec: 0100b82c andhi r4,zero,736 + 100b6f0: 0100c408 cmpgei r4,zero,784 + 100b6f4: 0100c618 cmpnei r4,zero,792 + 100b6f8: 0100b82c andhi r4,zero,736 + 100b6fc: 0100c420 cmpeqi r4,zero,784 + 100b700: 0100c6b4 movhi r4,794 + 100b704: 0100b82c andhi r4,zero,736 + 100b708: 0100c6a0 cmpeqi r4,zero,794 + 100b70c: 0100c668 cmpgeui r4,zero,793 + 100b710: 0100c668 cmpgeui r4,zero,793 + 100b714: 0100c668 cmpgeui r4,zero,793 + 100b718: 0100c668 cmpgeui r4,zero,793 + 100b71c: 0100c668 cmpgeui r4,zero,793 + 100b720: 0100c668 cmpgeui r4,zero,793 + 100b724: 0100c668 cmpgeui r4,zero,793 + 100b728: 0100c668 cmpgeui r4,zero,793 + 100b72c: 0100c668 cmpgeui r4,zero,793 + 100b730: 0100b82c andhi r4,zero,736 + 100b734: 0100b82c andhi r4,zero,736 + 100b738: 0100b82c andhi r4,zero,736 + 100b73c: 0100b82c andhi r4,zero,736 + 100b740: 0100b82c andhi r4,zero,736 + 100b744: 0100b82c andhi r4,zero,736 + 100b748: 0100b82c andhi r4,zero,736 + 100b74c: 0100b82c andhi r4,zero,736 + 100b750: 0100b82c andhi r4,zero,736 + 100b754: 0100b82c andhi r4,zero,736 + 100b758: 0100be84 movi r4,762 + 100b75c: 0100c4f0 cmpltui r4,zero,787 + 100b760: 0100b82c andhi r4,zero,736 + 100b764: 0100c4f0 cmpltui r4,zero,787 + 100b768: 0100b82c andhi r4,zero,736 + 100b76c: 0100b82c andhi r4,zero,736 + 100b770: 0100b82c andhi r4,zero,736 + 100b774: 0100b82c andhi r4,zero,736 + 100b778: 0100c654 movui r4,793 + 100b77c: 0100b82c andhi r4,zero,736 + 100b780: 0100b82c andhi r4,zero,736 + 100b784: 0100bf38 rdprs r4,zero,764 + 100b788: 0100b82c andhi r4,zero,736 + 100b78c: 0100b82c andhi r4,zero,736 + 100b790: 0100b82c andhi r4,zero,736 + 100b794: 0100b82c andhi r4,zero,736 + 100b798: 0100b82c andhi r4,zero,736 + 100b79c: 0100bf84 movi r4,766 + 100b7a0: 0100b82c andhi r4,zero,736 + 100b7a4: 0100b82c andhi r4,zero,736 + 100b7a8: 0100c5a4 muli r4,zero,790 + 100b7ac: 0100b82c andhi r4,zero,736 + 100b7b0: 0100b82c andhi r4,zero,736 + 100b7b4: 0100b82c andhi r4,zero,736 + 100b7b8: 0100b82c andhi r4,zero,736 + 100b7bc: 0100b82c andhi r4,zero,736 + 100b7c0: 0100b82c andhi r4,zero,736 + 100b7c4: 0100b82c andhi r4,zero,736 + 100b7c8: 0100b82c andhi r4,zero,736 + 100b7cc: 0100b82c andhi r4,zero,736 + 100b7d0: 0100b82c andhi r4,zero,736 + 100b7d4: 0100c578 rdprs r4,zero,789 + 100b7d8: 0100be90 cmplti r4,zero,762 + 100b7dc: 0100c4f0 cmpltui r4,zero,787 + 100b7e0: 0100c4f0 cmpltui r4,zero,787 + 100b7e4: 0100c4f0 cmpltui r4,zero,787 + 100b7e8: 0100c4dc xori r4,zero,787 + 100b7ec: 0100be90 cmplti r4,zero,762 + 100b7f0: 0100b82c andhi r4,zero,736 + 100b7f4: 0100b82c andhi r4,zero,736 + 100b7f8: 0100c464 muli r4,zero,785 + 100b7fc: 0100b82c andhi r4,zero,736 + 100b800: 0100c434 movhi r4,784 + 100b804: 0100bf44 movi r4,765 + 100b808: 0100c494 movui r4,786 + 100b80c: 0100c480 call 100c48 + 100b810: 0100b82c andhi r4,zero,736 + 100b814: 0100c710 cmplti r4,zero,796 + 100b818: 0100b82c andhi r4,zero,736 + 100b81c: 0100bf90 cmplti r4,zero,766 + 100b820: 0100b82c andhi r4,zero,736 + 100b824: 0100b82c andhi r4,zero,736 + 100b828: 0100c608 cmpgei r4,zero,792 + 100b82c: d9014d17 ldw r4,1332(sp) + 100b830: 2000ce26 beq r4,zero,100bb6c <___vfprintf_internal_r+0x6d4> + 100b834: 01400044 movi r5,1 + 100b838: d9800f04 addi r6,sp,60 + 100b83c: d9c14015 stw r7,1280(sp) + 100b840: d9414515 stw r5,1300(sp) + 100b844: d9814115 stw r6,1284(sp) + 100b848: 280f883a mov r7,r5 + 100b84c: d9000f05 stb r4,60(sp) + 100b850: d8000405 stb zero,16(sp) + 100b854: d8014615 stw zero,1304(sp) + 100b858: d8c14c17 ldw r3,1328(sp) + 100b85c: 1880008c andi r2,r3,2 + 100b860: 1005003a cmpeq r2,r2,zero + 100b864: d8815015 stw r2,1344(sp) + 100b868: 1000031e bne r2,zero,100b878 <___vfprintf_internal_r+0x3e0> + 100b86c: d9014517 ldw r4,1300(sp) + 100b870: 21000084 addi r4,r4,2 + 100b874: d9014515 stw r4,1300(sp) + 100b878: d9414c17 ldw r5,1328(sp) + 100b87c: 2940210c andi r5,r5,132 + 100b880: d9414e15 stw r5,1336(sp) + 100b884: 28002d1e bne r5,zero,100b93c <___vfprintf_internal_r+0x4a4> + 100b888: d9814a17 ldw r6,1320(sp) + 100b88c: d8814517 ldw r2,1300(sp) + 100b890: 30a1c83a sub r16,r6,r2 + 100b894: 0400290e bge zero,r16,100b93c <___vfprintf_internal_r+0x4a4> + 100b898: 00800404 movi r2,16 + 100b89c: 1404580e bge r2,r16,100ca00 <___vfprintf_internal_r+0x1568> + 100b8a0: dc800e17 ldw r18,56(sp) + 100b8a4: dc400d17 ldw r17,52(sp) + 100b8a8: 1027883a mov r19,r2 + 100b8ac: 070040b4 movhi fp,258 + 100b8b0: e7054a84 addi fp,fp,5418 + 100b8b4: 050001c4 movi r20,7 + 100b8b8: 00000306 br 100b8c8 <___vfprintf_internal_r+0x430> + 100b8bc: 843ffc04 addi r16,r16,-16 + 100b8c0: ad400204 addi r21,r21,8 + 100b8c4: 9c00130e bge r19,r16,100b914 <___vfprintf_internal_r+0x47c> + 100b8c8: 94800404 addi r18,r18,16 + 100b8cc: 8c400044 addi r17,r17,1 + 100b8d0: af000015 stw fp,0(r21) + 100b8d4: acc00115 stw r19,4(r21) + 100b8d8: dc800e15 stw r18,56(sp) + 100b8dc: dc400d15 stw r17,52(sp) + 100b8e0: a47ff60e bge r20,r17,100b8bc <___vfprintf_internal_r+0x424> + 100b8e4: d9014f17 ldw r4,1340(sp) + 100b8e8: b00b883a mov r5,r22 + 100b8ec: d9800c04 addi r6,sp,48 + 100b8f0: d9c15115 stw r7,1348(sp) + 100b8f4: 100b4400 call 100b440 <__sprint_r> + 100b8f8: d9c15117 ldw r7,1348(sp) + 100b8fc: 10009e1e bne r2,zero,100bb78 <___vfprintf_internal_r+0x6e0> + 100b900: 843ffc04 addi r16,r16,-16 + 100b904: dc800e17 ldw r18,56(sp) + 100b908: dc400d17 ldw r17,52(sp) + 100b90c: dd401904 addi r21,sp,100 + 100b910: 9c3fed16 blt r19,r16,100b8c8 <___vfprintf_internal_r+0x430> + 100b914: 9425883a add r18,r18,r16 + 100b918: 8c400044 addi r17,r17,1 + 100b91c: 008001c4 movi r2,7 + 100b920: af000015 stw fp,0(r21) + 100b924: ac000115 stw r16,4(r21) + 100b928: dc800e15 stw r18,56(sp) + 100b92c: dc400d15 stw r17,52(sp) + 100b930: 1441f516 blt r2,r17,100c108 <___vfprintf_internal_r+0xc70> + 100b934: ad400204 addi r21,r21,8 + 100b938: 00000206 br 100b944 <___vfprintf_internal_r+0x4ac> + 100b93c: dc800e17 ldw r18,56(sp) + 100b940: dc400d17 ldw r17,52(sp) + 100b944: d8800407 ldb r2,16(sp) + 100b948: 10000b26 beq r2,zero,100b978 <___vfprintf_internal_r+0x4e0> + 100b94c: 00800044 movi r2,1 + 100b950: 94800044 addi r18,r18,1 + 100b954: 8c400044 addi r17,r17,1 + 100b958: a8800115 stw r2,4(r21) + 100b95c: d8c00404 addi r3,sp,16 + 100b960: 008001c4 movi r2,7 + 100b964: a8c00015 stw r3,0(r21) + 100b968: dc800e15 stw r18,56(sp) + 100b96c: dc400d15 stw r17,52(sp) + 100b970: 1441da16 blt r2,r17,100c0dc <___vfprintf_internal_r+0xc44> + 100b974: ad400204 addi r21,r21,8 + 100b978: d9015017 ldw r4,1344(sp) + 100b97c: 20000b1e bne r4,zero,100b9ac <___vfprintf_internal_r+0x514> + 100b980: d8800444 addi r2,sp,17 + 100b984: 94800084 addi r18,r18,2 + 100b988: 8c400044 addi r17,r17,1 + 100b98c: a8800015 stw r2,0(r21) + 100b990: 00c00084 movi r3,2 + 100b994: 008001c4 movi r2,7 + 100b998: a8c00115 stw r3,4(r21) + 100b99c: dc800e15 stw r18,56(sp) + 100b9a0: dc400d15 stw r17,52(sp) + 100b9a4: 1441c216 blt r2,r17,100c0b0 <___vfprintf_internal_r+0xc18> + 100b9a8: ad400204 addi r21,r21,8 + 100b9ac: d9414e17 ldw r5,1336(sp) + 100b9b0: 00802004 movi r2,128 + 100b9b4: 2880b126 beq r5,r2,100bc7c <___vfprintf_internal_r+0x7e4> + 100b9b8: d8c14617 ldw r3,1304(sp) + 100b9bc: 19e1c83a sub r16,r3,r7 + 100b9c0: 0400260e bge zero,r16,100ba5c <___vfprintf_internal_r+0x5c4> + 100b9c4: 00800404 movi r2,16 + 100b9c8: 1403c90e bge r2,r16,100c8f0 <___vfprintf_internal_r+0x1458> + 100b9cc: 1027883a mov r19,r2 + 100b9d0: 070040b4 movhi fp,258 + 100b9d4: e7054684 addi fp,fp,5402 + 100b9d8: 050001c4 movi r20,7 + 100b9dc: 00000306 br 100b9ec <___vfprintf_internal_r+0x554> + 100b9e0: 843ffc04 addi r16,r16,-16 + 100b9e4: ad400204 addi r21,r21,8 + 100b9e8: 9c00130e bge r19,r16,100ba38 <___vfprintf_internal_r+0x5a0> + 100b9ec: 94800404 addi r18,r18,16 + 100b9f0: 8c400044 addi r17,r17,1 + 100b9f4: af000015 stw fp,0(r21) + 100b9f8: acc00115 stw r19,4(r21) + 100b9fc: dc800e15 stw r18,56(sp) + 100ba00: dc400d15 stw r17,52(sp) + 100ba04: a47ff60e bge r20,r17,100b9e0 <___vfprintf_internal_r+0x548> + 100ba08: d9014f17 ldw r4,1340(sp) + 100ba0c: b00b883a mov r5,r22 + 100ba10: d9800c04 addi r6,sp,48 + 100ba14: d9c15115 stw r7,1348(sp) + 100ba18: 100b4400 call 100b440 <__sprint_r> + 100ba1c: d9c15117 ldw r7,1348(sp) + 100ba20: 1000551e bne r2,zero,100bb78 <___vfprintf_internal_r+0x6e0> + 100ba24: 843ffc04 addi r16,r16,-16 + 100ba28: dc800e17 ldw r18,56(sp) + 100ba2c: dc400d17 ldw r17,52(sp) + 100ba30: dd401904 addi r21,sp,100 + 100ba34: 9c3fed16 blt r19,r16,100b9ec <___vfprintf_internal_r+0x554> + 100ba38: 9425883a add r18,r18,r16 + 100ba3c: 8c400044 addi r17,r17,1 + 100ba40: 008001c4 movi r2,7 + 100ba44: af000015 stw fp,0(r21) + 100ba48: ac000115 stw r16,4(r21) + 100ba4c: dc800e15 stw r18,56(sp) + 100ba50: dc400d15 stw r17,52(sp) + 100ba54: 14418216 blt r2,r17,100c060 <___vfprintf_internal_r+0xbc8> + 100ba58: ad400204 addi r21,r21,8 + 100ba5c: d9014c17 ldw r4,1328(sp) + 100ba60: 2080400c andi r2,r4,256 + 100ba64: 10004a1e bne r2,zero,100bb90 <___vfprintf_internal_r+0x6f8> + 100ba68: d9414117 ldw r5,1284(sp) + 100ba6c: 91e5883a add r18,r18,r7 + 100ba70: 8c400044 addi r17,r17,1 + 100ba74: 008001c4 movi r2,7 + 100ba78: a9400015 stw r5,0(r21) + 100ba7c: a9c00115 stw r7,4(r21) + 100ba80: dc800e15 stw r18,56(sp) + 100ba84: dc400d15 stw r17,52(sp) + 100ba88: 14416716 blt r2,r17,100c028 <___vfprintf_internal_r+0xb90> + 100ba8c: a8c00204 addi r3,r21,8 + 100ba90: d9814c17 ldw r6,1328(sp) + 100ba94: 3080010c andi r2,r6,4 + 100ba98: 10002826 beq r2,zero,100bb3c <___vfprintf_internal_r+0x6a4> + 100ba9c: d8814a17 ldw r2,1320(sp) + 100baa0: d9014517 ldw r4,1300(sp) + 100baa4: 1121c83a sub r16,r2,r4 + 100baa8: 0400240e bge zero,r16,100bb3c <___vfprintf_internal_r+0x6a4> + 100baac: 00800404 movi r2,16 + 100bab0: 14044f0e bge r2,r16,100cbf0 <___vfprintf_internal_r+0x1758> + 100bab4: dc400d17 ldw r17,52(sp) + 100bab8: 1027883a mov r19,r2 + 100babc: 070040b4 movhi fp,258 + 100bac0: e7054a84 addi fp,fp,5418 + 100bac4: 050001c4 movi r20,7 + 100bac8: 00000306 br 100bad8 <___vfprintf_internal_r+0x640> + 100bacc: 843ffc04 addi r16,r16,-16 + 100bad0: 18c00204 addi r3,r3,8 + 100bad4: 9c00110e bge r19,r16,100bb1c <___vfprintf_internal_r+0x684> + 100bad8: 94800404 addi r18,r18,16 + 100badc: 8c400044 addi r17,r17,1 + 100bae0: 1f000015 stw fp,0(r3) + 100bae4: 1cc00115 stw r19,4(r3) + 100bae8: dc800e15 stw r18,56(sp) + 100baec: dc400d15 stw r17,52(sp) + 100baf0: a47ff60e bge r20,r17,100bacc <___vfprintf_internal_r+0x634> + 100baf4: d9014f17 ldw r4,1340(sp) + 100baf8: b00b883a mov r5,r22 + 100bafc: d9800c04 addi r6,sp,48 + 100bb00: 100b4400 call 100b440 <__sprint_r> + 100bb04: 10001c1e bne r2,zero,100bb78 <___vfprintf_internal_r+0x6e0> + 100bb08: 843ffc04 addi r16,r16,-16 + 100bb0c: dc800e17 ldw r18,56(sp) + 100bb10: dc400d17 ldw r17,52(sp) + 100bb14: d8c01904 addi r3,sp,100 + 100bb18: 9c3fef16 blt r19,r16,100bad8 <___vfprintf_internal_r+0x640> + 100bb1c: 9425883a add r18,r18,r16 + 100bb20: 8c400044 addi r17,r17,1 + 100bb24: 008001c4 movi r2,7 + 100bb28: 1f000015 stw fp,0(r3) + 100bb2c: 1c000115 stw r16,4(r3) + 100bb30: dc800e15 stw r18,56(sp) + 100bb34: dc400d15 stw r17,52(sp) + 100bb38: 1440cb16 blt r2,r17,100be68 <___vfprintf_internal_r+0x9d0> + 100bb3c: d8814a17 ldw r2,1320(sp) + 100bb40: d9414517 ldw r5,1300(sp) + 100bb44: 1140010e bge r2,r5,100bb4c <___vfprintf_internal_r+0x6b4> + 100bb48: 2805883a mov r2,r5 + 100bb4c: d9814b17 ldw r6,1324(sp) + 100bb50: 308d883a add r6,r6,r2 + 100bb54: d9814b15 stw r6,1324(sp) + 100bb58: 90013b1e bne r18,zero,100c048 <___vfprintf_internal_r+0xbb0> + 100bb5c: d9c14017 ldw r7,1280(sp) + 100bb60: dd401904 addi r21,sp,100 + 100bb64: d8000d15 stw zero,52(sp) + 100bb68: 003ea706 br 100b608 <___vfprintf_internal_r+0x170> + 100bb6c: d8800e17 ldw r2,56(sp) + 100bb70: 10053f1e bne r2,zero,100d070 <___vfprintf_internal_r+0x1bd8> + 100bb74: d8000d15 stw zero,52(sp) + 100bb78: b080030b ldhu r2,12(r22) + 100bb7c: 1080100c andi r2,r2,64 + 100bb80: 103e8726 beq r2,zero,100b5a0 <___vfprintf_internal_r+0x108> + 100bb84: 00bfffc4 movi r2,-1 + 100bb88: d8814b15 stw r2,1324(sp) + 100bb8c: 003e8406 br 100b5a0 <___vfprintf_internal_r+0x108> + 100bb90: d9814d17 ldw r6,1332(sp) + 100bb94: 00801944 movi r2,101 + 100bb98: 11806e16 blt r2,r6,100bd54 <___vfprintf_internal_r+0x8bc> + 100bb9c: d9414717 ldw r5,1308(sp) + 100bba0: 00c00044 movi r3,1 + 100bba4: 1943430e bge r3,r5,100c8b4 <___vfprintf_internal_r+0x141c> + 100bba8: d8814117 ldw r2,1284(sp) + 100bbac: 94800044 addi r18,r18,1 + 100bbb0: 8c400044 addi r17,r17,1 + 100bbb4: a8800015 stw r2,0(r21) + 100bbb8: 008001c4 movi r2,7 + 100bbbc: a8c00115 stw r3,4(r21) + 100bbc0: dc800e15 stw r18,56(sp) + 100bbc4: dc400d15 stw r17,52(sp) + 100bbc8: 1441ca16 blt r2,r17,100c2f4 <___vfprintf_internal_r+0xe5c> + 100bbcc: a8c00204 addi r3,r21,8 + 100bbd0: d9014917 ldw r4,1316(sp) + 100bbd4: 00800044 movi r2,1 + 100bbd8: 94800044 addi r18,r18,1 + 100bbdc: 8c400044 addi r17,r17,1 + 100bbe0: 18800115 stw r2,4(r3) + 100bbe4: 008001c4 movi r2,7 + 100bbe8: 19000015 stw r4,0(r3) + 100bbec: dc800e15 stw r18,56(sp) + 100bbf0: dc400d15 stw r17,52(sp) + 100bbf4: 1441b616 blt r2,r17,100c2d0 <___vfprintf_internal_r+0xe38> + 100bbf8: 1cc00204 addi r19,r3,8 + 100bbfc: d9014217 ldw r4,1288(sp) + 100bc00: d9414317 ldw r5,1292(sp) + 100bc04: 000d883a mov r6,zero + 100bc08: 000f883a mov r7,zero + 100bc0c: 10135740 call 1013574 <__nedf2> + 100bc10: 10017426 beq r2,zero,100c1e4 <___vfprintf_internal_r+0xd4c> + 100bc14: d9414717 ldw r5,1308(sp) + 100bc18: d9814117 ldw r6,1284(sp) + 100bc1c: 8c400044 addi r17,r17,1 + 100bc20: 2c85883a add r2,r5,r18 + 100bc24: 14bfffc4 addi r18,r2,-1 + 100bc28: 28bfffc4 addi r2,r5,-1 + 100bc2c: 30c00044 addi r3,r6,1 + 100bc30: 98800115 stw r2,4(r19) + 100bc34: 008001c4 movi r2,7 + 100bc38: 98c00015 stw r3,0(r19) + 100bc3c: dc800e15 stw r18,56(sp) + 100bc40: dc400d15 stw r17,52(sp) + 100bc44: 14418e16 blt r2,r17,100c280 <___vfprintf_internal_r+0xde8> + 100bc48: 9cc00204 addi r19,r19,8 + 100bc4c: d9414817 ldw r5,1312(sp) + 100bc50: d8800804 addi r2,sp,32 + 100bc54: 8c400044 addi r17,r17,1 + 100bc58: 9165883a add r18,r18,r5 + 100bc5c: 98800015 stw r2,0(r19) + 100bc60: 008001c4 movi r2,7 + 100bc64: 99400115 stw r5,4(r19) + 100bc68: dc800e15 stw r18,56(sp) + 100bc6c: dc400d15 stw r17,52(sp) + 100bc70: 1440ed16 blt r2,r17,100c028 <___vfprintf_internal_r+0xb90> + 100bc74: 98c00204 addi r3,r19,8 + 100bc78: 003f8506 br 100ba90 <___vfprintf_internal_r+0x5f8> + 100bc7c: d9814a17 ldw r6,1320(sp) + 100bc80: d8814517 ldw r2,1300(sp) + 100bc84: 30a1c83a sub r16,r6,r2 + 100bc88: 043f4b0e bge zero,r16,100b9b8 <___vfprintf_internal_r+0x520> + 100bc8c: 00800404 movi r2,16 + 100bc90: 1404340e bge r2,r16,100cd64 <___vfprintf_internal_r+0x18cc> + 100bc94: 1027883a mov r19,r2 + 100bc98: 070040b4 movhi fp,258 + 100bc9c: e7054684 addi fp,fp,5402 + 100bca0: 050001c4 movi r20,7 + 100bca4: 00000306 br 100bcb4 <___vfprintf_internal_r+0x81c> + 100bca8: 843ffc04 addi r16,r16,-16 + 100bcac: ad400204 addi r21,r21,8 + 100bcb0: 9c00130e bge r19,r16,100bd00 <___vfprintf_internal_r+0x868> + 100bcb4: 94800404 addi r18,r18,16 + 100bcb8: 8c400044 addi r17,r17,1 + 100bcbc: af000015 stw fp,0(r21) + 100bcc0: acc00115 stw r19,4(r21) + 100bcc4: dc800e15 stw r18,56(sp) + 100bcc8: dc400d15 stw r17,52(sp) + 100bccc: a47ff60e bge r20,r17,100bca8 <___vfprintf_internal_r+0x810> + 100bcd0: d9014f17 ldw r4,1340(sp) + 100bcd4: b00b883a mov r5,r22 + 100bcd8: d9800c04 addi r6,sp,48 + 100bcdc: d9c15115 stw r7,1348(sp) + 100bce0: 100b4400 call 100b440 <__sprint_r> + 100bce4: d9c15117 ldw r7,1348(sp) + 100bce8: 103fa31e bne r2,zero,100bb78 <___vfprintf_internal_r+0x6e0> + 100bcec: 843ffc04 addi r16,r16,-16 + 100bcf0: dc800e17 ldw r18,56(sp) + 100bcf4: dc400d17 ldw r17,52(sp) + 100bcf8: dd401904 addi r21,sp,100 + 100bcfc: 9c3fed16 blt r19,r16,100bcb4 <___vfprintf_internal_r+0x81c> + 100bd00: 9425883a add r18,r18,r16 + 100bd04: 8c400044 addi r17,r17,1 + 100bd08: 008001c4 movi r2,7 + 100bd0c: af000015 stw fp,0(r21) + 100bd10: ac000115 stw r16,4(r21) + 100bd14: dc800e15 stw r18,56(sp) + 100bd18: dc400d15 stw r17,52(sp) + 100bd1c: 14416116 blt r2,r17,100c2a4 <___vfprintf_internal_r+0xe0c> + 100bd20: ad400204 addi r21,r21,8 + 100bd24: 003f2406 br 100b9b8 <___vfprintf_internal_r+0x520> + 100bd28: d9014f17 ldw r4,1340(sp) + 100bd2c: 100ef080 call 100ef08 <__sinit> + 100bd30: d9c15117 ldw r7,1348(sp) + 100bd34: 003def06 br 100b4f4 <___vfprintf_internal_r+0x5c> + 100bd38: d9014f17 ldw r4,1340(sp) + 100bd3c: b00b883a mov r5,r22 + 100bd40: d9c15115 stw r7,1348(sp) + 100bd44: 100d3680 call 100d368 <__swsetup_r> + 100bd48: d9c15117 ldw r7,1348(sp) + 100bd4c: 103dee26 beq r2,zero,100b508 <___vfprintf_internal_r+0x70> + 100bd50: 003f8c06 br 100bb84 <___vfprintf_internal_r+0x6ec> + 100bd54: d9014217 ldw r4,1288(sp) + 100bd58: d9414317 ldw r5,1292(sp) + 100bd5c: 000d883a mov r6,zero + 100bd60: 000f883a mov r7,zero + 100bd64: 10134ec0 call 10134ec <__eqdf2> + 100bd68: 1000f21e bne r2,zero,100c134 <___vfprintf_internal_r+0xc9c> + 100bd6c: 008040b4 movhi r2,258 + 100bd70: 10854604 addi r2,r2,5400 + 100bd74: 94800044 addi r18,r18,1 + 100bd78: 8c400044 addi r17,r17,1 + 100bd7c: a8800015 stw r2,0(r21) + 100bd80: 00c00044 movi r3,1 + 100bd84: 008001c4 movi r2,7 + 100bd88: a8c00115 stw r3,4(r21) + 100bd8c: dc800e15 stw r18,56(sp) + 100bd90: dc400d15 stw r17,52(sp) + 100bd94: 1442fa16 blt r2,r17,100c980 <___vfprintf_internal_r+0x14e8> + 100bd98: a8c00204 addi r3,r21,8 + 100bd9c: d8800517 ldw r2,20(sp) + 100bda0: d9014717 ldw r4,1308(sp) + 100bda4: 11015c0e bge r2,r4,100c318 <___vfprintf_internal_r+0xe80> + 100bda8: dc400d17 ldw r17,52(sp) + 100bdac: d9814917 ldw r6,1316(sp) + 100bdb0: 00800044 movi r2,1 + 100bdb4: 94800044 addi r18,r18,1 + 100bdb8: 8c400044 addi r17,r17,1 + 100bdbc: 18800115 stw r2,4(r3) + 100bdc0: 008001c4 movi r2,7 + 100bdc4: 19800015 stw r6,0(r3) + 100bdc8: dc800e15 stw r18,56(sp) + 100bdcc: dc400d15 stw r17,52(sp) + 100bdd0: 14431016 blt r2,r17,100ca14 <___vfprintf_internal_r+0x157c> + 100bdd4: 18c00204 addi r3,r3,8 + 100bdd8: d8814717 ldw r2,1308(sp) + 100bddc: 143fffc4 addi r16,r2,-1 + 100bde0: 043f2b0e bge zero,r16,100ba90 <___vfprintf_internal_r+0x5f8> + 100bde4: 00800404 movi r2,16 + 100bde8: 1402a20e bge r2,r16,100c874 <___vfprintf_internal_r+0x13dc> + 100bdec: dc400d17 ldw r17,52(sp) + 100bdf0: 1027883a mov r19,r2 + 100bdf4: 070040b4 movhi fp,258 + 100bdf8: e7054684 addi fp,fp,5402 + 100bdfc: 050001c4 movi r20,7 + 100be00: 00000306 br 100be10 <___vfprintf_internal_r+0x978> + 100be04: 18c00204 addi r3,r3,8 + 100be08: 843ffc04 addi r16,r16,-16 + 100be0c: 9c029c0e bge r19,r16,100c880 <___vfprintf_internal_r+0x13e8> + 100be10: 94800404 addi r18,r18,16 + 100be14: 8c400044 addi r17,r17,1 + 100be18: 1f000015 stw fp,0(r3) + 100be1c: 1cc00115 stw r19,4(r3) + 100be20: dc800e15 stw r18,56(sp) + 100be24: dc400d15 stw r17,52(sp) + 100be28: a47ff60e bge r20,r17,100be04 <___vfprintf_internal_r+0x96c> + 100be2c: d9014f17 ldw r4,1340(sp) + 100be30: b00b883a mov r5,r22 + 100be34: d9800c04 addi r6,sp,48 + 100be38: 100b4400 call 100b440 <__sprint_r> + 100be3c: 103f4e1e bne r2,zero,100bb78 <___vfprintf_internal_r+0x6e0> + 100be40: dc800e17 ldw r18,56(sp) + 100be44: dc400d17 ldw r17,52(sp) + 100be48: d8c01904 addi r3,sp,100 + 100be4c: 003fee06 br 100be08 <___vfprintf_internal_r+0x970> + 100be50: d8802c0b ldhu r2,176(sp) + 100be54: 00ffffc4 movi r3,-1 + 100be58: d8c14b15 stw r3,1324(sp) + 100be5c: 1080100c andi r2,r2,64 + 100be60: 103dcc1e bne r2,zero,100b594 <___vfprintf_internal_r+0xfc> + 100be64: 003dce06 br 100b5a0 <___vfprintf_internal_r+0x108> + 100be68: d9014f17 ldw r4,1340(sp) + 100be6c: b00b883a mov r5,r22 + 100be70: d9800c04 addi r6,sp,48 + 100be74: 100b4400 call 100b440 <__sprint_r> + 100be78: 103f3f1e bne r2,zero,100bb78 <___vfprintf_internal_r+0x6e0> + 100be7c: dc800e17 ldw r18,56(sp) + 100be80: 003f2e06 br 100bb3c <___vfprintf_internal_r+0x6a4> + 100be84: d9414c17 ldw r5,1328(sp) + 100be88: 29400414 ori r5,r5,16 + 100be8c: d9414c15 stw r5,1328(sp) + 100be90: d9814c17 ldw r6,1328(sp) + 100be94: 3080080c andi r2,r6,32 + 100be98: 10014f1e bne r2,zero,100c3d8 <___vfprintf_internal_r+0xf40> + 100be9c: d8c14c17 ldw r3,1328(sp) + 100bea0: 1880040c andi r2,r3,16 + 100bea4: 1002ea1e bne r2,zero,100ca50 <___vfprintf_internal_r+0x15b8> + 100bea8: d9014c17 ldw r4,1328(sp) + 100beac: 2080100c andi r2,r4,64 + 100beb0: 1002e726 beq r2,zero,100ca50 <___vfprintf_internal_r+0x15b8> + 100beb4: 3880000f ldh r2,0(r7) + 100beb8: 39c00104 addi r7,r7,4 + 100bebc: d9c14015 stw r7,1280(sp) + 100bec0: 1023d7fa srai r17,r2,31 + 100bec4: 1021883a mov r16,r2 + 100bec8: 88037216 blt r17,zero,100cc94 <___vfprintf_internal_r+0x17fc> + 100becc: 01000044 movi r4,1 + 100bed0: 98000416 blt r19,zero,100bee4 <___vfprintf_internal_r+0xa4c> + 100bed4: d8c14c17 ldw r3,1328(sp) + 100bed8: 00bfdfc4 movi r2,-129 + 100bedc: 1886703a and r3,r3,r2 + 100bee0: d8c14c15 stw r3,1328(sp) + 100bee4: 8444b03a or r2,r16,r17 + 100bee8: 1002261e bne r2,zero,100c784 <___vfprintf_internal_r+0x12ec> + 100beec: 9802251e bne r19,zero,100c784 <___vfprintf_internal_r+0x12ec> + 100bef0: 20803fcc andi r2,r4,255 + 100bef4: 10029b26 beq r2,zero,100c964 <___vfprintf_internal_r+0x14cc> + 100bef8: d8c01904 addi r3,sp,100 + 100befc: dd000f04 addi r20,sp,60 + 100bf00: d8c14115 stw r3,1284(sp) + 100bf04: d8c14117 ldw r3,1284(sp) + 100bf08: dcc14515 stw r19,1300(sp) + 100bf0c: a0c5c83a sub r2,r20,r3 + 100bf10: 11c00a04 addi r7,r2,40 + 100bf14: 99c0010e bge r19,r7,100bf1c <___vfprintf_internal_r+0xa84> + 100bf18: d9c14515 stw r7,1300(sp) + 100bf1c: dcc14615 stw r19,1304(sp) + 100bf20: d8800407 ldb r2,16(sp) + 100bf24: 103e4c26 beq r2,zero,100b858 <___vfprintf_internal_r+0x3c0> + 100bf28: d8814517 ldw r2,1300(sp) + 100bf2c: 10800044 addi r2,r2,1 + 100bf30: d8814515 stw r2,1300(sp) + 100bf34: 003e4806 br 100b858 <___vfprintf_internal_r+0x3c0> + 100bf38: d9814c17 ldw r6,1328(sp) + 100bf3c: 31800414 ori r6,r6,16 + 100bf40: d9814c15 stw r6,1328(sp) + 100bf44: d8c14c17 ldw r3,1328(sp) + 100bf48: 1880080c andi r2,r3,32 + 100bf4c: 1001271e bne r2,zero,100c3ec <___vfprintf_internal_r+0xf54> + 100bf50: d9414c17 ldw r5,1328(sp) + 100bf54: 2880040c andi r2,r5,16 + 100bf58: 1002b61e bne r2,zero,100ca34 <___vfprintf_internal_r+0x159c> + 100bf5c: d9814c17 ldw r6,1328(sp) + 100bf60: 3080100c andi r2,r6,64 + 100bf64: 1002b326 beq r2,zero,100ca34 <___vfprintf_internal_r+0x159c> + 100bf68: 3c00000b ldhu r16,0(r7) + 100bf6c: 0009883a mov r4,zero + 100bf70: 39c00104 addi r7,r7,4 + 100bf74: 0023883a mov r17,zero + 100bf78: d9c14015 stw r7,1280(sp) + 100bf7c: d8000405 stb zero,16(sp) + 100bf80: 003fd306 br 100bed0 <___vfprintf_internal_r+0xa38> + 100bf84: d9014c17 ldw r4,1328(sp) + 100bf88: 21000414 ori r4,r4,16 + 100bf8c: d9014c15 stw r4,1328(sp) + 100bf90: d9414c17 ldw r5,1328(sp) + 100bf94: 2880080c andi r2,r5,32 + 100bf98: 1001081e bne r2,zero,100c3bc <___vfprintf_internal_r+0xf24> + 100bf9c: d8c14c17 ldw r3,1328(sp) + 100bfa0: 1880040c andi r2,r3,16 + 100bfa4: 1002b01e bne r2,zero,100ca68 <___vfprintf_internal_r+0x15d0> + 100bfa8: d9014c17 ldw r4,1328(sp) + 100bfac: 2080100c andi r2,r4,64 + 100bfb0: 1002ad26 beq r2,zero,100ca68 <___vfprintf_internal_r+0x15d0> + 100bfb4: 3c00000b ldhu r16,0(r7) + 100bfb8: 01000044 movi r4,1 + 100bfbc: 39c00104 addi r7,r7,4 + 100bfc0: 0023883a mov r17,zero + 100bfc4: d9c14015 stw r7,1280(sp) + 100bfc8: d8000405 stb zero,16(sp) + 100bfcc: 003fc006 br 100bed0 <___vfprintf_internal_r+0xa38> + 100bfd0: d9014f17 ldw r4,1340(sp) + 100bfd4: b00b883a mov r5,r22 + 100bfd8: d9800c04 addi r6,sp,48 + 100bfdc: 100b4400 call 100b440 <__sprint_r> + 100bfe0: 103ee51e bne r2,zero,100bb78 <___vfprintf_internal_r+0x6e0> + 100bfe4: dc800e17 ldw r18,56(sp) + 100bfe8: d8c01904 addi r3,sp,100 + 100bfec: d9814c17 ldw r6,1328(sp) + 100bff0: 3080004c andi r2,r6,1 + 100bff4: 1005003a cmpeq r2,r2,zero + 100bff8: 103ea51e bne r2,zero,100ba90 <___vfprintf_internal_r+0x5f8> + 100bffc: 00800044 movi r2,1 + 100c000: dc400d17 ldw r17,52(sp) + 100c004: 18800115 stw r2,4(r3) + 100c008: d8814917 ldw r2,1316(sp) + 100c00c: 94800044 addi r18,r18,1 + 100c010: 8c400044 addi r17,r17,1 + 100c014: 18800015 stw r2,0(r3) + 100c018: 008001c4 movi r2,7 + 100c01c: dc800e15 stw r18,56(sp) + 100c020: dc400d15 stw r17,52(sp) + 100c024: 14421e0e bge r2,r17,100c8a0 <___vfprintf_internal_r+0x1408> + 100c028: d9014f17 ldw r4,1340(sp) + 100c02c: b00b883a mov r5,r22 + 100c030: d9800c04 addi r6,sp,48 + 100c034: 100b4400 call 100b440 <__sprint_r> + 100c038: 103ecf1e bne r2,zero,100bb78 <___vfprintf_internal_r+0x6e0> + 100c03c: dc800e17 ldw r18,56(sp) + 100c040: d8c01904 addi r3,sp,100 + 100c044: 003e9206 br 100ba90 <___vfprintf_internal_r+0x5f8> + 100c048: d9014f17 ldw r4,1340(sp) + 100c04c: b00b883a mov r5,r22 + 100c050: d9800c04 addi r6,sp,48 + 100c054: 100b4400 call 100b440 <__sprint_r> + 100c058: 103ec026 beq r2,zero,100bb5c <___vfprintf_internal_r+0x6c4> + 100c05c: 003ec606 br 100bb78 <___vfprintf_internal_r+0x6e0> + 100c060: d9014f17 ldw r4,1340(sp) + 100c064: b00b883a mov r5,r22 + 100c068: d9800c04 addi r6,sp,48 + 100c06c: d9c15115 stw r7,1348(sp) + 100c070: 100b4400 call 100b440 <__sprint_r> + 100c074: d9c15117 ldw r7,1348(sp) + 100c078: 103ebf1e bne r2,zero,100bb78 <___vfprintf_internal_r+0x6e0> + 100c07c: dc800e17 ldw r18,56(sp) + 100c080: dc400d17 ldw r17,52(sp) + 100c084: dd401904 addi r21,sp,100 + 100c088: 003e7406 br 100ba5c <___vfprintf_internal_r+0x5c4> + 100c08c: d9014f17 ldw r4,1340(sp) + 100c090: b00b883a mov r5,r22 + 100c094: d9800c04 addi r6,sp,48 + 100c098: d9c15115 stw r7,1348(sp) + 100c09c: 100b4400 call 100b440 <__sprint_r> + 100c0a0: d9c15117 ldw r7,1348(sp) + 100c0a4: 103eb41e bne r2,zero,100bb78 <___vfprintf_internal_r+0x6e0> + 100c0a8: dd401904 addi r21,sp,100 + 100c0ac: 003d6d06 br 100b664 <___vfprintf_internal_r+0x1cc> + 100c0b0: d9014f17 ldw r4,1340(sp) + 100c0b4: b00b883a mov r5,r22 + 100c0b8: d9800c04 addi r6,sp,48 + 100c0bc: d9c15115 stw r7,1348(sp) + 100c0c0: 100b4400 call 100b440 <__sprint_r> + 100c0c4: d9c15117 ldw r7,1348(sp) + 100c0c8: 103eab1e bne r2,zero,100bb78 <___vfprintf_internal_r+0x6e0> + 100c0cc: dc800e17 ldw r18,56(sp) + 100c0d0: dc400d17 ldw r17,52(sp) + 100c0d4: dd401904 addi r21,sp,100 + 100c0d8: 003e3406 br 100b9ac <___vfprintf_internal_r+0x514> + 100c0dc: d9014f17 ldw r4,1340(sp) + 100c0e0: b00b883a mov r5,r22 + 100c0e4: d9800c04 addi r6,sp,48 + 100c0e8: d9c15115 stw r7,1348(sp) + 100c0ec: 100b4400 call 100b440 <__sprint_r> + 100c0f0: d9c15117 ldw r7,1348(sp) + 100c0f4: 103ea01e bne r2,zero,100bb78 <___vfprintf_internal_r+0x6e0> + 100c0f8: dc800e17 ldw r18,56(sp) + 100c0fc: dc400d17 ldw r17,52(sp) + 100c100: dd401904 addi r21,sp,100 + 100c104: 003e1c06 br 100b978 <___vfprintf_internal_r+0x4e0> + 100c108: d9014f17 ldw r4,1340(sp) + 100c10c: b00b883a mov r5,r22 + 100c110: d9800c04 addi r6,sp,48 + 100c114: d9c15115 stw r7,1348(sp) + 100c118: 100b4400 call 100b440 <__sprint_r> + 100c11c: d9c15117 ldw r7,1348(sp) + 100c120: 103e951e bne r2,zero,100bb78 <___vfprintf_internal_r+0x6e0> + 100c124: dc800e17 ldw r18,56(sp) + 100c128: dc400d17 ldw r17,52(sp) + 100c12c: dd401904 addi r21,sp,100 + 100c130: 003e0406 br 100b944 <___vfprintf_internal_r+0x4ac> + 100c134: d9000517 ldw r4,20(sp) + 100c138: 0102520e bge zero,r4,100ca84 <___vfprintf_internal_r+0x15ec> + 100c13c: d9814717 ldw r6,1308(sp) + 100c140: 21807a16 blt r4,r6,100c32c <___vfprintf_internal_r+0xe94> + 100c144: d8814117 ldw r2,1284(sp) + 100c148: 91a5883a add r18,r18,r6 + 100c14c: 8c400044 addi r17,r17,1 + 100c150: a8800015 stw r2,0(r21) + 100c154: 008001c4 movi r2,7 + 100c158: a9800115 stw r6,4(r21) + 100c15c: dc800e15 stw r18,56(sp) + 100c160: dc400d15 stw r17,52(sp) + 100c164: 1442f616 blt r2,r17,100cd40 <___vfprintf_internal_r+0x18a8> + 100c168: a8c00204 addi r3,r21,8 + 100c16c: d9414717 ldw r5,1308(sp) + 100c170: 2161c83a sub r16,r4,r5 + 100c174: 043f9d0e bge zero,r16,100bfec <___vfprintf_internal_r+0xb54> + 100c178: 00800404 movi r2,16 + 100c17c: 1402130e bge r2,r16,100c9cc <___vfprintf_internal_r+0x1534> + 100c180: dc400d17 ldw r17,52(sp) + 100c184: 1027883a mov r19,r2 + 100c188: 070040b4 movhi fp,258 + 100c18c: e7054684 addi fp,fp,5402 + 100c190: 050001c4 movi r20,7 + 100c194: 00000306 br 100c1a4 <___vfprintf_internal_r+0xd0c> + 100c198: 18c00204 addi r3,r3,8 + 100c19c: 843ffc04 addi r16,r16,-16 + 100c1a0: 9c020d0e bge r19,r16,100c9d8 <___vfprintf_internal_r+0x1540> + 100c1a4: 94800404 addi r18,r18,16 + 100c1a8: 8c400044 addi r17,r17,1 + 100c1ac: 1f000015 stw fp,0(r3) + 100c1b0: 1cc00115 stw r19,4(r3) + 100c1b4: dc800e15 stw r18,56(sp) + 100c1b8: dc400d15 stw r17,52(sp) + 100c1bc: a47ff60e bge r20,r17,100c198 <___vfprintf_internal_r+0xd00> + 100c1c0: d9014f17 ldw r4,1340(sp) + 100c1c4: b00b883a mov r5,r22 + 100c1c8: d9800c04 addi r6,sp,48 + 100c1cc: 100b4400 call 100b440 <__sprint_r> + 100c1d0: 103e691e bne r2,zero,100bb78 <___vfprintf_internal_r+0x6e0> + 100c1d4: dc800e17 ldw r18,56(sp) + 100c1d8: dc400d17 ldw r17,52(sp) + 100c1dc: d8c01904 addi r3,sp,100 + 100c1e0: 003fee06 br 100c19c <___vfprintf_internal_r+0xd04> + 100c1e4: d8814717 ldw r2,1308(sp) + 100c1e8: 143fffc4 addi r16,r2,-1 + 100c1ec: 043e970e bge zero,r16,100bc4c <___vfprintf_internal_r+0x7b4> + 100c1f0: 00800404 movi r2,16 + 100c1f4: 1400180e bge r2,r16,100c258 <___vfprintf_internal_r+0xdc0> + 100c1f8: 1029883a mov r20,r2 + 100c1fc: 070040b4 movhi fp,258 + 100c200: e7054684 addi fp,fp,5402 + 100c204: 054001c4 movi r21,7 + 100c208: 00000306 br 100c218 <___vfprintf_internal_r+0xd80> + 100c20c: 9cc00204 addi r19,r19,8 + 100c210: 843ffc04 addi r16,r16,-16 + 100c214: a400120e bge r20,r16,100c260 <___vfprintf_internal_r+0xdc8> + 100c218: 94800404 addi r18,r18,16 + 100c21c: 8c400044 addi r17,r17,1 + 100c220: 9f000015 stw fp,0(r19) + 100c224: 9d000115 stw r20,4(r19) + 100c228: dc800e15 stw r18,56(sp) + 100c22c: dc400d15 stw r17,52(sp) + 100c230: ac7ff60e bge r21,r17,100c20c <___vfprintf_internal_r+0xd74> + 100c234: d9014f17 ldw r4,1340(sp) + 100c238: b00b883a mov r5,r22 + 100c23c: d9800c04 addi r6,sp,48 + 100c240: 100b4400 call 100b440 <__sprint_r> + 100c244: 103e4c1e bne r2,zero,100bb78 <___vfprintf_internal_r+0x6e0> + 100c248: dc800e17 ldw r18,56(sp) + 100c24c: dc400d17 ldw r17,52(sp) + 100c250: dcc01904 addi r19,sp,100 + 100c254: 003fee06 br 100c210 <___vfprintf_internal_r+0xd78> + 100c258: 070040b4 movhi fp,258 + 100c25c: e7054684 addi fp,fp,5402 + 100c260: 9425883a add r18,r18,r16 + 100c264: 8c400044 addi r17,r17,1 + 100c268: 008001c4 movi r2,7 + 100c26c: 9f000015 stw fp,0(r19) + 100c270: 9c000115 stw r16,4(r19) + 100c274: dc800e15 stw r18,56(sp) + 100c278: dc400d15 stw r17,52(sp) + 100c27c: 147e720e bge r2,r17,100bc48 <___vfprintf_internal_r+0x7b0> + 100c280: d9014f17 ldw r4,1340(sp) + 100c284: b00b883a mov r5,r22 + 100c288: d9800c04 addi r6,sp,48 + 100c28c: 100b4400 call 100b440 <__sprint_r> + 100c290: 103e391e bne r2,zero,100bb78 <___vfprintf_internal_r+0x6e0> + 100c294: dc800e17 ldw r18,56(sp) + 100c298: dc400d17 ldw r17,52(sp) + 100c29c: dcc01904 addi r19,sp,100 + 100c2a0: 003e6a06 br 100bc4c <___vfprintf_internal_r+0x7b4> + 100c2a4: d9014f17 ldw r4,1340(sp) + 100c2a8: b00b883a mov r5,r22 + 100c2ac: d9800c04 addi r6,sp,48 + 100c2b0: d9c15115 stw r7,1348(sp) + 100c2b4: 100b4400 call 100b440 <__sprint_r> + 100c2b8: d9c15117 ldw r7,1348(sp) + 100c2bc: 103e2e1e bne r2,zero,100bb78 <___vfprintf_internal_r+0x6e0> + 100c2c0: dc800e17 ldw r18,56(sp) + 100c2c4: dc400d17 ldw r17,52(sp) + 100c2c8: dd401904 addi r21,sp,100 + 100c2cc: 003dba06 br 100b9b8 <___vfprintf_internal_r+0x520> + 100c2d0: d9014f17 ldw r4,1340(sp) + 100c2d4: b00b883a mov r5,r22 + 100c2d8: d9800c04 addi r6,sp,48 + 100c2dc: 100b4400 call 100b440 <__sprint_r> + 100c2e0: 103e251e bne r2,zero,100bb78 <___vfprintf_internal_r+0x6e0> + 100c2e4: dc800e17 ldw r18,56(sp) + 100c2e8: dc400d17 ldw r17,52(sp) + 100c2ec: dcc01904 addi r19,sp,100 + 100c2f0: 003e4206 br 100bbfc <___vfprintf_internal_r+0x764> + 100c2f4: d9014f17 ldw r4,1340(sp) + 100c2f8: b00b883a mov r5,r22 + 100c2fc: d9800c04 addi r6,sp,48 + 100c300: 100b4400 call 100b440 <__sprint_r> + 100c304: 103e1c1e bne r2,zero,100bb78 <___vfprintf_internal_r+0x6e0> + 100c308: dc800e17 ldw r18,56(sp) + 100c30c: dc400d17 ldw r17,52(sp) + 100c310: d8c01904 addi r3,sp,100 + 100c314: 003e2e06 br 100bbd0 <___vfprintf_internal_r+0x738> + 100c318: d9414c17 ldw r5,1328(sp) + 100c31c: 2880004c andi r2,r5,1 + 100c320: 1005003a cmpeq r2,r2,zero + 100c324: 103dda1e bne r2,zero,100ba90 <___vfprintf_internal_r+0x5f8> + 100c328: 003e9f06 br 100bda8 <___vfprintf_internal_r+0x910> + 100c32c: d8c14117 ldw r3,1284(sp) + 100c330: 9125883a add r18,r18,r4 + 100c334: 8c400044 addi r17,r17,1 + 100c338: 008001c4 movi r2,7 + 100c33c: a8c00015 stw r3,0(r21) + 100c340: a9000115 stw r4,4(r21) + 100c344: dc800e15 stw r18,56(sp) + 100c348: dc400d15 stw r17,52(sp) + 100c34c: 14426616 blt r2,r17,100cce8 <___vfprintf_internal_r+0x1850> + 100c350: a8c00204 addi r3,r21,8 + 100c354: d9414917 ldw r5,1316(sp) + 100c358: 00800044 movi r2,1 + 100c35c: 94800044 addi r18,r18,1 + 100c360: 8c400044 addi r17,r17,1 + 100c364: 18800115 stw r2,4(r3) + 100c368: 008001c4 movi r2,7 + 100c36c: 19400015 stw r5,0(r3) + 100c370: dc800e15 stw r18,56(sp) + 100c374: dc400d15 stw r17,52(sp) + 100c378: 2021883a mov r16,r4 + 100c37c: 14425016 blt r2,r17,100ccc0 <___vfprintf_internal_r+0x1828> + 100c380: 19400204 addi r5,r3,8 + 100c384: d9814717 ldw r6,1308(sp) + 100c388: 8c400044 addi r17,r17,1 + 100c38c: dc400d15 stw r17,52(sp) + 100c390: 3107c83a sub r3,r6,r4 + 100c394: d9014117 ldw r4,1284(sp) + 100c398: 90e5883a add r18,r18,r3 + 100c39c: 28c00115 stw r3,4(r5) + 100c3a0: 8105883a add r2,r16,r4 + 100c3a4: 28800015 stw r2,0(r5) + 100c3a8: 008001c4 movi r2,7 + 100c3ac: dc800e15 stw r18,56(sp) + 100c3b0: 147f1d16 blt r2,r17,100c028 <___vfprintf_internal_r+0xb90> + 100c3b4: 28c00204 addi r3,r5,8 + 100c3b8: 003db506 br 100ba90 <___vfprintf_internal_r+0x5f8> + 100c3bc: 3c000017 ldw r16,0(r7) + 100c3c0: 3c400117 ldw r17,4(r7) + 100c3c4: 39800204 addi r6,r7,8 + 100c3c8: 01000044 movi r4,1 + 100c3cc: d9814015 stw r6,1280(sp) + 100c3d0: d8000405 stb zero,16(sp) + 100c3d4: 003ebe06 br 100bed0 <___vfprintf_internal_r+0xa38> + 100c3d8: 3c000017 ldw r16,0(r7) + 100c3dc: 3c400117 ldw r17,4(r7) + 100c3e0: 38800204 addi r2,r7,8 + 100c3e4: d8814015 stw r2,1280(sp) + 100c3e8: 003eb706 br 100bec8 <___vfprintf_internal_r+0xa30> + 100c3ec: 3c000017 ldw r16,0(r7) + 100c3f0: 3c400117 ldw r17,4(r7) + 100c3f4: 39000204 addi r4,r7,8 + 100c3f8: d9014015 stw r4,1280(sp) + 100c3fc: 0009883a mov r4,zero + 100c400: d8000405 stb zero,16(sp) + 100c404: 003eb206 br 100bed0 <___vfprintf_internal_r+0xa38> + 100c408: 38c00017 ldw r3,0(r7) + 100c40c: 39c00104 addi r7,r7,4 + 100c410: d8c14a15 stw r3,1320(sp) + 100c414: 1800d10e bge r3,zero,100c75c <___vfprintf_internal_r+0x12c4> + 100c418: 00c7c83a sub r3,zero,r3 + 100c41c: d8c14a15 stw r3,1320(sp) + 100c420: d9014c17 ldw r4,1328(sp) + 100c424: b8c00007 ldb r3,0(r23) + 100c428: 21000114 ori r4,r4,4 + 100c42c: d9014c15 stw r4,1328(sp) + 100c430: 003c9806 br 100b694 <___vfprintf_internal_r+0x1fc> + 100c434: d9814c17 ldw r6,1328(sp) + 100c438: 3080080c andi r2,r6,32 + 100c43c: 1001f026 beq r2,zero,100cc00 <___vfprintf_internal_r+0x1768> + 100c440: d9014b17 ldw r4,1324(sp) + 100c444: 38800017 ldw r2,0(r7) + 100c448: 39c00104 addi r7,r7,4 + 100c44c: d9c14015 stw r7,1280(sp) + 100c450: 2007d7fa srai r3,r4,31 + 100c454: d9c14017 ldw r7,1280(sp) + 100c458: 11000015 stw r4,0(r2) + 100c45c: 10c00115 stw r3,4(r2) + 100c460: 003c6906 br 100b608 <___vfprintf_internal_r+0x170> + 100c464: b8c00007 ldb r3,0(r23) + 100c468: 00801b04 movi r2,108 + 100c46c: 18824f26 beq r3,r2,100cdac <___vfprintf_internal_r+0x1914> + 100c470: d9414c17 ldw r5,1328(sp) + 100c474: 29400414 ori r5,r5,16 + 100c478: d9414c15 stw r5,1328(sp) + 100c47c: 003c8506 br 100b694 <___vfprintf_internal_r+0x1fc> + 100c480: d9814c17 ldw r6,1328(sp) + 100c484: b8c00007 ldb r3,0(r23) + 100c488: 31800814 ori r6,r6,32 + 100c48c: d9814c15 stw r6,1328(sp) + 100c490: 003c8006 br 100b694 <___vfprintf_internal_r+0x1fc> + 100c494: d8814c17 ldw r2,1328(sp) + 100c498: 3c000017 ldw r16,0(r7) + 100c49c: 00c01e04 movi r3,120 + 100c4a0: 10800094 ori r2,r2,2 + 100c4a4: d8814c15 stw r2,1328(sp) + 100c4a8: 39c00104 addi r7,r7,4 + 100c4ac: 014040b4 movhi r5,258 + 100c4b0: 29452f04 addi r5,r5,5308 + 100c4b4: 00800c04 movi r2,48 + 100c4b8: 0023883a mov r17,zero + 100c4bc: 01000084 movi r4,2 + 100c4c0: d9c14015 stw r7,1280(sp) + 100c4c4: d8c14d15 stw r3,1332(sp) + 100c4c8: d9414415 stw r5,1296(sp) + 100c4cc: d8800445 stb r2,17(sp) + 100c4d0: d8c00485 stb r3,18(sp) + 100c4d4: d8000405 stb zero,16(sp) + 100c4d8: 003e7d06 br 100bed0 <___vfprintf_internal_r+0xa38> + 100c4dc: d8814c17 ldw r2,1328(sp) + 100c4e0: b8c00007 ldb r3,0(r23) + 100c4e4: 10801014 ori r2,r2,64 + 100c4e8: d8814c15 stw r2,1328(sp) + 100c4ec: 003c6906 br 100b694 <___vfprintf_internal_r+0x1fc> + 100c4f0: d9414c17 ldw r5,1328(sp) + 100c4f4: 2880020c andi r2,r5,8 + 100c4f8: 1001df26 beq r2,zero,100cc78 <___vfprintf_internal_r+0x17e0> + 100c4fc: 39800017 ldw r6,0(r7) + 100c500: 38800204 addi r2,r7,8 + 100c504: d8814015 stw r2,1280(sp) + 100c508: d9814215 stw r6,1288(sp) + 100c50c: 39c00117 ldw r7,4(r7) + 100c510: d9c14315 stw r7,1292(sp) + 100c514: d9014217 ldw r4,1288(sp) + 100c518: d9414317 ldw r5,1292(sp) + 100c51c: 10115e80 call 10115e8 <__isinfd> + 100c520: 10021726 beq r2,zero,100cd80 <___vfprintf_internal_r+0x18e8> + 100c524: d9014217 ldw r4,1288(sp) + 100c528: d9414317 ldw r5,1292(sp) + 100c52c: 000d883a mov r6,zero + 100c530: 000f883a mov r7,zero + 100c534: 101370c0 call 101370c <__ltdf2> + 100c538: 1002ca16 blt r2,zero,100d064 <___vfprintf_internal_r+0x1bcc> + 100c53c: d9414d17 ldw r5,1332(sp) + 100c540: 008011c4 movi r2,71 + 100c544: 11420a16 blt r2,r5,100cd70 <___vfprintf_internal_r+0x18d8> + 100c548: 018040b4 movhi r6,258 + 100c54c: 31853404 addi r6,r6,5328 + 100c550: d9814115 stw r6,1284(sp) + 100c554: d9014c17 ldw r4,1328(sp) + 100c558: 00c000c4 movi r3,3 + 100c55c: 00bfdfc4 movi r2,-129 + 100c560: 2088703a and r4,r4,r2 + 100c564: 180f883a mov r7,r3 + 100c568: d8c14515 stw r3,1300(sp) + 100c56c: d9014c15 stw r4,1328(sp) + 100c570: d8014615 stw zero,1304(sp) + 100c574: 003e6a06 br 100bf20 <___vfprintf_internal_r+0xa88> + 100c578: 38800017 ldw r2,0(r7) + 100c57c: 00c00044 movi r3,1 + 100c580: 39c00104 addi r7,r7,4 + 100c584: d9c14015 stw r7,1280(sp) + 100c588: d9000f04 addi r4,sp,60 + 100c58c: 180f883a mov r7,r3 + 100c590: d8c14515 stw r3,1300(sp) + 100c594: d9014115 stw r4,1284(sp) + 100c598: d8800f05 stb r2,60(sp) + 100c59c: d8000405 stb zero,16(sp) + 100c5a0: 003cac06 br 100b854 <___vfprintf_internal_r+0x3bc> + 100c5a4: 014040b4 movhi r5,258 + 100c5a8: 29453a04 addi r5,r5,5352 + 100c5ac: d9414415 stw r5,1296(sp) + 100c5b0: d9814c17 ldw r6,1328(sp) + 100c5b4: 3080080c andi r2,r6,32 + 100c5b8: 1000f926 beq r2,zero,100c9a0 <___vfprintf_internal_r+0x1508> + 100c5bc: 3c000017 ldw r16,0(r7) + 100c5c0: 3c400117 ldw r17,4(r7) + 100c5c4: 38800204 addi r2,r7,8 + 100c5c8: d8814015 stw r2,1280(sp) + 100c5cc: d9414c17 ldw r5,1328(sp) + 100c5d0: 2880004c andi r2,r5,1 + 100c5d4: 1005003a cmpeq r2,r2,zero + 100c5d8: 1000b31e bne r2,zero,100c8a8 <___vfprintf_internal_r+0x1410> + 100c5dc: 8444b03a or r2,r16,r17 + 100c5e0: 1000b126 beq r2,zero,100c8a8 <___vfprintf_internal_r+0x1410> + 100c5e4: d9814d17 ldw r6,1332(sp) + 100c5e8: 29400094 ori r5,r5,2 + 100c5ec: 00800c04 movi r2,48 + 100c5f0: 01000084 movi r4,2 + 100c5f4: d9414c15 stw r5,1328(sp) + 100c5f8: d8800445 stb r2,17(sp) + 100c5fc: d9800485 stb r6,18(sp) + 100c600: d8000405 stb zero,16(sp) + 100c604: 003e3206 br 100bed0 <___vfprintf_internal_r+0xa38> + 100c608: 018040b4 movhi r6,258 + 100c60c: 31852f04 addi r6,r6,5308 + 100c610: d9814415 stw r6,1296(sp) + 100c614: 003fe606 br 100c5b0 <___vfprintf_internal_r+0x1118> + 100c618: 00800ac4 movi r2,43 + 100c61c: d8800405 stb r2,16(sp) + 100c620: b8c00007 ldb r3,0(r23) + 100c624: 003c1b06 br 100b694 <___vfprintf_internal_r+0x1fc> + 100c628: d8814c17 ldw r2,1328(sp) + 100c62c: b8c00007 ldb r3,0(r23) + 100c630: 10800054 ori r2,r2,1 + 100c634: d8814c15 stw r2,1328(sp) + 100c638: 003c1606 br 100b694 <___vfprintf_internal_r+0x1fc> + 100c63c: d8800407 ldb r2,16(sp) + 100c640: 1000461e bne r2,zero,100c75c <___vfprintf_internal_r+0x12c4> + 100c644: 00800804 movi r2,32 + 100c648: d8800405 stb r2,16(sp) + 100c64c: b8c00007 ldb r3,0(r23) + 100c650: 003c1006 br 100b694 <___vfprintf_internal_r+0x1fc> + 100c654: d9814c17 ldw r6,1328(sp) + 100c658: b8c00007 ldb r3,0(r23) + 100c65c: 31800214 ori r6,r6,8 + 100c660: d9814c15 stw r6,1328(sp) + 100c664: 003c0b06 br 100b694 <___vfprintf_internal_r+0x1fc> + 100c668: 0007883a mov r3,zero + 100c66c: 01000244 movi r4,9 + 100c670: 188002a4 muli r2,r3,10 + 100c674: b8c00007 ldb r3,0(r23) + 100c678: d9814d17 ldw r6,1332(sp) + 100c67c: bdc00044 addi r23,r23,1 + 100c680: d8c14d15 stw r3,1332(sp) + 100c684: d9414d17 ldw r5,1332(sp) + 100c688: 3085883a add r2,r6,r2 + 100c68c: 10fff404 addi r3,r2,-48 + 100c690: 28bff404 addi r2,r5,-48 + 100c694: 20bff62e bgeu r4,r2,100c670 <___vfprintf_internal_r+0x11d8> + 100c698: d8c14a15 stw r3,1320(sp) + 100c69c: 003bff06 br 100b69c <___vfprintf_internal_r+0x204> + 100c6a0: d9414c17 ldw r5,1328(sp) + 100c6a4: b8c00007 ldb r3,0(r23) + 100c6a8: 29402014 ori r5,r5,128 + 100c6ac: d9414c15 stw r5,1328(sp) + 100c6b0: 003bf806 br 100b694 <___vfprintf_internal_r+0x1fc> + 100c6b4: b8c00007 ldb r3,0(r23) + 100c6b8: 00800a84 movi r2,42 + 100c6bc: bdc00044 addi r23,r23,1 + 100c6c0: 18831526 beq r3,r2,100d318 <___vfprintf_internal_r+0x1e80> + 100c6c4: d8c14d15 stw r3,1332(sp) + 100c6c8: 18bff404 addi r2,r3,-48 + 100c6cc: 00c00244 movi r3,9 + 100c6d0: 18827836 bltu r3,r2,100d0b4 <___vfprintf_internal_r+0x1c1c> + 100c6d4: 000d883a mov r6,zero + 100c6d8: 308002a4 muli r2,r6,10 + 100c6dc: b9800007 ldb r6,0(r23) + 100c6e0: d9414d17 ldw r5,1332(sp) + 100c6e4: bdc00044 addi r23,r23,1 + 100c6e8: d9814d15 stw r6,1332(sp) + 100c6ec: d9014d17 ldw r4,1332(sp) + 100c6f0: 1145883a add r2,r2,r5 + 100c6f4: 11bff404 addi r6,r2,-48 + 100c6f8: 20bff404 addi r2,r4,-48 + 100c6fc: 18bff62e bgeu r3,r2,100c6d8 <___vfprintf_internal_r+0x1240> + 100c700: 3027883a mov r19,r6 + 100c704: 303be50e bge r6,zero,100b69c <___vfprintf_internal_r+0x204> + 100c708: 04ffffc4 movi r19,-1 + 100c70c: 003be306 br 100b69c <___vfprintf_internal_r+0x204> + 100c710: d8000405 stb zero,16(sp) + 100c714: 39800017 ldw r6,0(r7) + 100c718: 39c00104 addi r7,r7,4 + 100c71c: d9c14015 stw r7,1280(sp) + 100c720: d9814115 stw r6,1284(sp) + 100c724: 3001c926 beq r6,zero,100ce4c <___vfprintf_internal_r+0x19b4> + 100c728: 98000e16 blt r19,zero,100c764 <___vfprintf_internal_r+0x12cc> + 100c72c: d9014117 ldw r4,1284(sp) + 100c730: 000b883a mov r5,zero + 100c734: 980d883a mov r6,r19 + 100c738: 100a8e40 call 100a8e4 + 100c73c: 10025926 beq r2,zero,100d0a4 <___vfprintf_internal_r+0x1c0c> + 100c740: d8c14117 ldw r3,1284(sp) + 100c744: 10cfc83a sub r7,r2,r3 + 100c748: 99c19e16 blt r19,r7,100cdc4 <___vfprintf_internal_r+0x192c> + 100c74c: d9c14515 stw r7,1300(sp) + 100c750: 38000916 blt r7,zero,100c778 <___vfprintf_internal_r+0x12e0> + 100c754: d8014615 stw zero,1304(sp) + 100c758: 003df106 br 100bf20 <___vfprintf_internal_r+0xa88> + 100c75c: b8c00007 ldb r3,0(r23) + 100c760: 003bcc06 br 100b694 <___vfprintf_internal_r+0x1fc> + 100c764: d9014117 ldw r4,1284(sp) + 100c768: 100b1640 call 100b164 + 100c76c: d8814515 stw r2,1300(sp) + 100c770: 100f883a mov r7,r2 + 100c774: 103ff70e bge r2,zero,100c754 <___vfprintf_internal_r+0x12bc> + 100c778: d8014515 stw zero,1300(sp) + 100c77c: d8014615 stw zero,1304(sp) + 100c780: 003de706 br 100bf20 <___vfprintf_internal_r+0xa88> + 100c784: 20c03fcc andi r3,r4,255 + 100c788: 00800044 movi r2,1 + 100c78c: 18802d26 beq r3,r2,100c844 <___vfprintf_internal_r+0x13ac> + 100c790: 18800e36 bltu r3,r2,100c7cc <___vfprintf_internal_r+0x1334> + 100c794: 00800084 movi r2,2 + 100c798: 1880fa26 beq r3,r2,100cb84 <___vfprintf_internal_r+0x16ec> + 100c79c: 010040b4 movhi r4,258 + 100c7a0: 21053f04 addi r4,r4,5372 + 100c7a4: 100b1640 call 100b164 + 100c7a8: 100f883a mov r7,r2 + 100c7ac: dcc14515 stw r19,1300(sp) + 100c7b0: 9880010e bge r19,r2,100c7b8 <___vfprintf_internal_r+0x1320> + 100c7b4: d8814515 stw r2,1300(sp) + 100c7b8: 008040b4 movhi r2,258 + 100c7bc: 10853f04 addi r2,r2,5372 + 100c7c0: dcc14615 stw r19,1304(sp) + 100c7c4: d8814115 stw r2,1284(sp) + 100c7c8: 003dd506 br 100bf20 <___vfprintf_internal_r+0xa88> + 100c7cc: d9401904 addi r5,sp,100 + 100c7d0: dd000f04 addi r20,sp,60 + 100c7d4: d9414115 stw r5,1284(sp) + 100c7d8: 880a977a slli r5,r17,29 + 100c7dc: d9814117 ldw r6,1284(sp) + 100c7e0: 8004d0fa srli r2,r16,3 + 100c7e4: 8806d0fa srli r3,r17,3 + 100c7e8: 810001cc andi r4,r16,7 + 100c7ec: 2884b03a or r2,r5,r2 + 100c7f0: 31bfffc4 addi r6,r6,-1 + 100c7f4: 21000c04 addi r4,r4,48 + 100c7f8: d9814115 stw r6,1284(sp) + 100c7fc: 10cab03a or r5,r2,r3 + 100c800: 31000005 stb r4,0(r6) + 100c804: 1021883a mov r16,r2 + 100c808: 1823883a mov r17,r3 + 100c80c: 283ff21e bne r5,zero,100c7d8 <___vfprintf_internal_r+0x1340> + 100c810: d8c14c17 ldw r3,1328(sp) + 100c814: 1880004c andi r2,r3,1 + 100c818: 1005003a cmpeq r2,r2,zero + 100c81c: 103db91e bne r2,zero,100bf04 <___vfprintf_internal_r+0xa6c> + 100c820: 20803fcc andi r2,r4,255 + 100c824: 1080201c xori r2,r2,128 + 100c828: 10bfe004 addi r2,r2,-128 + 100c82c: 00c00c04 movi r3,48 + 100c830: 10fdb426 beq r2,r3,100bf04 <___vfprintf_internal_r+0xa6c> + 100c834: 31bfffc4 addi r6,r6,-1 + 100c838: d9814115 stw r6,1284(sp) + 100c83c: 30c00005 stb r3,0(r6) + 100c840: 003db006 br 100bf04 <___vfprintf_internal_r+0xa6c> + 100c844: 88800068 cmpgeui r2,r17,1 + 100c848: 10002c1e bne r2,zero,100c8fc <___vfprintf_internal_r+0x1464> + 100c84c: 8800021e bne r17,zero,100c858 <___vfprintf_internal_r+0x13c0> + 100c850: 00800244 movi r2,9 + 100c854: 14002936 bltu r2,r16,100c8fc <___vfprintf_internal_r+0x1464> + 100c858: d90018c4 addi r4,sp,99 + 100c85c: dd000f04 addi r20,sp,60 + 100c860: d9014115 stw r4,1284(sp) + 100c864: d9014117 ldw r4,1284(sp) + 100c868: 80800c04 addi r2,r16,48 + 100c86c: 20800005 stb r2,0(r4) + 100c870: 003da406 br 100bf04 <___vfprintf_internal_r+0xa6c> + 100c874: dc400d17 ldw r17,52(sp) + 100c878: 070040b4 movhi fp,258 + 100c87c: e7054684 addi fp,fp,5402 + 100c880: 9425883a add r18,r18,r16 + 100c884: 8c400044 addi r17,r17,1 + 100c888: 008001c4 movi r2,7 + 100c88c: 1f000015 stw fp,0(r3) + 100c890: 1c000115 stw r16,4(r3) + 100c894: dc800e15 stw r18,56(sp) + 100c898: dc400d15 stw r17,52(sp) + 100c89c: 147de216 blt r2,r17,100c028 <___vfprintf_internal_r+0xb90> + 100c8a0: 18c00204 addi r3,r3,8 + 100c8a4: 003c7a06 br 100ba90 <___vfprintf_internal_r+0x5f8> + 100c8a8: 01000084 movi r4,2 + 100c8ac: d8000405 stb zero,16(sp) + 100c8b0: 003d8706 br 100bed0 <___vfprintf_internal_r+0xa38> + 100c8b4: d9814c17 ldw r6,1328(sp) + 100c8b8: 30c4703a and r2,r6,r3 + 100c8bc: 1005003a cmpeq r2,r2,zero + 100c8c0: 103cb926 beq r2,zero,100bba8 <___vfprintf_internal_r+0x710> + 100c8c4: d9014117 ldw r4,1284(sp) + 100c8c8: 94800044 addi r18,r18,1 + 100c8cc: 8c400044 addi r17,r17,1 + 100c8d0: 008001c4 movi r2,7 + 100c8d4: a9000015 stw r4,0(r21) + 100c8d8: a8c00115 stw r3,4(r21) + 100c8dc: dc800e15 stw r18,56(sp) + 100c8e0: dc400d15 stw r17,52(sp) + 100c8e4: 147e6616 blt r2,r17,100c280 <___vfprintf_internal_r+0xde8> + 100c8e8: acc00204 addi r19,r21,8 + 100c8ec: 003cd706 br 100bc4c <___vfprintf_internal_r+0x7b4> + 100c8f0: 070040b4 movhi fp,258 + 100c8f4: e7054684 addi fp,fp,5402 + 100c8f8: 003c4f06 br 100ba38 <___vfprintf_internal_r+0x5a0> + 100c8fc: dd000f04 addi r20,sp,60 + 100c900: dc801904 addi r18,sp,100 + 100c904: 8009883a mov r4,r16 + 100c908: 880b883a mov r5,r17 + 100c90c: 01800284 movi r6,10 + 100c910: 000f883a mov r7,zero + 100c914: 101241c0 call 101241c <__umoddi3> + 100c918: 12000c04 addi r8,r2,48 + 100c91c: 94bfffc4 addi r18,r18,-1 + 100c920: 8009883a mov r4,r16 + 100c924: 880b883a mov r5,r17 + 100c928: 01800284 movi r6,10 + 100c92c: 000f883a mov r7,zero + 100c930: 92000005 stb r8,0(r18) + 100c934: 1011e400 call 1011e40 <__udivdi3> + 100c938: 1009883a mov r4,r2 + 100c93c: 1021883a mov r16,r2 + 100c940: 18800068 cmpgeui r2,r3,1 + 100c944: 1823883a mov r17,r3 + 100c948: 103fee1e bne r2,zero,100c904 <___vfprintf_internal_r+0x146c> + 100c94c: 1800021e bne r3,zero,100c958 <___vfprintf_internal_r+0x14c0> + 100c950: 00800244 movi r2,9 + 100c954: 113feb36 bltu r2,r4,100c904 <___vfprintf_internal_r+0x146c> + 100c958: 94bfffc4 addi r18,r18,-1 + 100c95c: dc814115 stw r18,1284(sp) + 100c960: 003fc006 br 100c864 <___vfprintf_internal_r+0x13cc> + 100c964: d9014c17 ldw r4,1328(sp) + 100c968: 2080004c andi r2,r4,1 + 100c96c: 10009a1e bne r2,zero,100cbd8 <___vfprintf_internal_r+0x1740> + 100c970: d9401904 addi r5,sp,100 + 100c974: dd000f04 addi r20,sp,60 + 100c978: d9414115 stw r5,1284(sp) + 100c97c: 003d6106 br 100bf04 <___vfprintf_internal_r+0xa6c> + 100c980: d9014f17 ldw r4,1340(sp) + 100c984: b00b883a mov r5,r22 + 100c988: d9800c04 addi r6,sp,48 + 100c98c: 100b4400 call 100b440 <__sprint_r> + 100c990: 103c791e bne r2,zero,100bb78 <___vfprintf_internal_r+0x6e0> + 100c994: dc800e17 ldw r18,56(sp) + 100c998: d8c01904 addi r3,sp,100 + 100c99c: 003cff06 br 100bd9c <___vfprintf_internal_r+0x904> + 100c9a0: d8c14c17 ldw r3,1328(sp) + 100c9a4: 1880040c andi r2,r3,16 + 100c9a8: 1000711e bne r2,zero,100cb70 <___vfprintf_internal_r+0x16d8> + 100c9ac: d9014c17 ldw r4,1328(sp) + 100c9b0: 2080100c andi r2,r4,64 + 100c9b4: 10006e26 beq r2,zero,100cb70 <___vfprintf_internal_r+0x16d8> + 100c9b8: 3c00000b ldhu r16,0(r7) + 100c9bc: 0023883a mov r17,zero + 100c9c0: 39c00104 addi r7,r7,4 + 100c9c4: d9c14015 stw r7,1280(sp) + 100c9c8: 003f0006 br 100c5cc <___vfprintf_internal_r+0x1134> + 100c9cc: dc400d17 ldw r17,52(sp) + 100c9d0: 070040b4 movhi fp,258 + 100c9d4: e7054684 addi fp,fp,5402 + 100c9d8: 9425883a add r18,r18,r16 + 100c9dc: 8c400044 addi r17,r17,1 + 100c9e0: 008001c4 movi r2,7 + 100c9e4: 1f000015 stw fp,0(r3) + 100c9e8: 1c000115 stw r16,4(r3) + 100c9ec: dc800e15 stw r18,56(sp) + 100c9f0: dc400d15 stw r17,52(sp) + 100c9f4: 147d7616 blt r2,r17,100bfd0 <___vfprintf_internal_r+0xb38> + 100c9f8: 18c00204 addi r3,r3,8 + 100c9fc: 003d7b06 br 100bfec <___vfprintf_internal_r+0xb54> + 100ca00: dc800e17 ldw r18,56(sp) + 100ca04: dc400d17 ldw r17,52(sp) + 100ca08: 070040b4 movhi fp,258 + 100ca0c: e7054a84 addi fp,fp,5418 + 100ca10: 003bc006 br 100b914 <___vfprintf_internal_r+0x47c> + 100ca14: d9014f17 ldw r4,1340(sp) + 100ca18: b00b883a mov r5,r22 + 100ca1c: d9800c04 addi r6,sp,48 + 100ca20: 100b4400 call 100b440 <__sprint_r> + 100ca24: 103c541e bne r2,zero,100bb78 <___vfprintf_internal_r+0x6e0> + 100ca28: dc800e17 ldw r18,56(sp) + 100ca2c: d8c01904 addi r3,sp,100 + 100ca30: 003ce906 br 100bdd8 <___vfprintf_internal_r+0x940> + 100ca34: 3c000017 ldw r16,0(r7) + 100ca38: 0009883a mov r4,zero + 100ca3c: 39c00104 addi r7,r7,4 + 100ca40: 0023883a mov r17,zero + 100ca44: d9c14015 stw r7,1280(sp) + 100ca48: d8000405 stb zero,16(sp) + 100ca4c: 003d2006 br 100bed0 <___vfprintf_internal_r+0xa38> + 100ca50: 38800017 ldw r2,0(r7) + 100ca54: 39c00104 addi r7,r7,4 + 100ca58: d9c14015 stw r7,1280(sp) + 100ca5c: 1023d7fa srai r17,r2,31 + 100ca60: 1021883a mov r16,r2 + 100ca64: 003d1806 br 100bec8 <___vfprintf_internal_r+0xa30> + 100ca68: 3c000017 ldw r16,0(r7) + 100ca6c: 01000044 movi r4,1 + 100ca70: 39c00104 addi r7,r7,4 + 100ca74: 0023883a mov r17,zero + 100ca78: d9c14015 stw r7,1280(sp) + 100ca7c: d8000405 stb zero,16(sp) + 100ca80: 003d1306 br 100bed0 <___vfprintf_internal_r+0xa38> + 100ca84: 008040b4 movhi r2,258 + 100ca88: 10854604 addi r2,r2,5400 + 100ca8c: 94800044 addi r18,r18,1 + 100ca90: 8c400044 addi r17,r17,1 + 100ca94: a8800015 stw r2,0(r21) + 100ca98: 00c00044 movi r3,1 + 100ca9c: 008001c4 movi r2,7 + 100caa0: a8c00115 stw r3,4(r21) + 100caa4: dc800e15 stw r18,56(sp) + 100caa8: dc400d15 stw r17,52(sp) + 100caac: 1440ca16 blt r2,r17,100cdd8 <___vfprintf_internal_r+0x1940> + 100cab0: a8c00204 addi r3,r21,8 + 100cab4: 2000061e bne r4,zero,100cad0 <___vfprintf_internal_r+0x1638> + 100cab8: d9414717 ldw r5,1308(sp) + 100cabc: 2800041e bne r5,zero,100cad0 <___vfprintf_internal_r+0x1638> + 100cac0: d9814c17 ldw r6,1328(sp) + 100cac4: 3080004c andi r2,r6,1 + 100cac8: 1005003a cmpeq r2,r2,zero + 100cacc: 103bf01e bne r2,zero,100ba90 <___vfprintf_internal_r+0x5f8> + 100cad0: 00800044 movi r2,1 + 100cad4: dc400d17 ldw r17,52(sp) + 100cad8: 18800115 stw r2,4(r3) + 100cadc: d8814917 ldw r2,1316(sp) + 100cae0: 94800044 addi r18,r18,1 + 100cae4: 8c400044 addi r17,r17,1 + 100cae8: 18800015 stw r2,0(r3) + 100caec: 008001c4 movi r2,7 + 100caf0: dc800e15 stw r18,56(sp) + 100caf4: dc400d15 stw r17,52(sp) + 100caf8: 1440ca16 blt r2,r17,100ce24 <___vfprintf_internal_r+0x198c> + 100cafc: 18c00204 addi r3,r3,8 + 100cb00: 0121c83a sub r16,zero,r4 + 100cb04: 0400500e bge zero,r16,100cc48 <___vfprintf_internal_r+0x17b0> + 100cb08: 00800404 movi r2,16 + 100cb0c: 1400800e bge r2,r16,100cd10 <___vfprintf_internal_r+0x1878> + 100cb10: 1027883a mov r19,r2 + 100cb14: 070040b4 movhi fp,258 + 100cb18: e7054684 addi fp,fp,5402 + 100cb1c: 050001c4 movi r20,7 + 100cb20: 00000306 br 100cb30 <___vfprintf_internal_r+0x1698> + 100cb24: 18c00204 addi r3,r3,8 + 100cb28: 843ffc04 addi r16,r16,-16 + 100cb2c: 9c007a0e bge r19,r16,100cd18 <___vfprintf_internal_r+0x1880> + 100cb30: 94800404 addi r18,r18,16 + 100cb34: 8c400044 addi r17,r17,1 + 100cb38: 1f000015 stw fp,0(r3) + 100cb3c: 1cc00115 stw r19,4(r3) + 100cb40: dc800e15 stw r18,56(sp) + 100cb44: dc400d15 stw r17,52(sp) + 100cb48: a47ff60e bge r20,r17,100cb24 <___vfprintf_internal_r+0x168c> + 100cb4c: d9014f17 ldw r4,1340(sp) + 100cb50: b00b883a mov r5,r22 + 100cb54: d9800c04 addi r6,sp,48 + 100cb58: 100b4400 call 100b440 <__sprint_r> + 100cb5c: 103c061e bne r2,zero,100bb78 <___vfprintf_internal_r+0x6e0> + 100cb60: dc800e17 ldw r18,56(sp) + 100cb64: dc400d17 ldw r17,52(sp) + 100cb68: d8c01904 addi r3,sp,100 + 100cb6c: 003fee06 br 100cb28 <___vfprintf_internal_r+0x1690> + 100cb70: 3c000017 ldw r16,0(r7) + 100cb74: 0023883a mov r17,zero + 100cb78: 39c00104 addi r7,r7,4 + 100cb7c: d9c14015 stw r7,1280(sp) + 100cb80: 003e9206 br 100c5cc <___vfprintf_internal_r+0x1134> + 100cb84: d9401904 addi r5,sp,100 + 100cb88: dd000f04 addi r20,sp,60 + 100cb8c: d9414115 stw r5,1284(sp) + 100cb90: d9814417 ldw r6,1296(sp) + 100cb94: 880a973a slli r5,r17,28 + 100cb98: 8004d13a srli r2,r16,4 + 100cb9c: 810003cc andi r4,r16,15 + 100cba0: 3109883a add r4,r6,r4 + 100cba4: 2884b03a or r2,r5,r2 + 100cba8: 21400003 ldbu r5,0(r4) + 100cbac: d9014117 ldw r4,1284(sp) + 100cbb0: 8806d13a srli r3,r17,4 + 100cbb4: 1021883a mov r16,r2 + 100cbb8: 213fffc4 addi r4,r4,-1 + 100cbbc: d9014115 stw r4,1284(sp) + 100cbc0: d9814117 ldw r6,1284(sp) + 100cbc4: 10c8b03a or r4,r2,r3 + 100cbc8: 1823883a mov r17,r3 + 100cbcc: 31400005 stb r5,0(r6) + 100cbd0: 203fef1e bne r4,zero,100cb90 <___vfprintf_internal_r+0x16f8> + 100cbd4: 003ccb06 br 100bf04 <___vfprintf_internal_r+0xa6c> + 100cbd8: 00800c04 movi r2,48 + 100cbdc: d98018c4 addi r6,sp,99 + 100cbe0: dd000f04 addi r20,sp,60 + 100cbe4: d88018c5 stb r2,99(sp) + 100cbe8: d9814115 stw r6,1284(sp) + 100cbec: 003cc506 br 100bf04 <___vfprintf_internal_r+0xa6c> + 100cbf0: dc400d17 ldw r17,52(sp) + 100cbf4: 070040b4 movhi fp,258 + 100cbf8: e7054a84 addi fp,fp,5418 + 100cbfc: 003bc706 br 100bb1c <___vfprintf_internal_r+0x684> + 100cc00: d9414c17 ldw r5,1328(sp) + 100cc04: 2880040c andi r2,r5,16 + 100cc08: 10007c26 beq r2,zero,100cdfc <___vfprintf_internal_r+0x1964> + 100cc0c: 38800017 ldw r2,0(r7) + 100cc10: 39c00104 addi r7,r7,4 + 100cc14: d9c14015 stw r7,1280(sp) + 100cc18: d9814b17 ldw r6,1324(sp) + 100cc1c: d9c14017 ldw r7,1280(sp) + 100cc20: 11800015 stw r6,0(r2) + 100cc24: 003a7806 br 100b608 <___vfprintf_internal_r+0x170> + 100cc28: d9014f17 ldw r4,1340(sp) + 100cc2c: b00b883a mov r5,r22 + 100cc30: d9800c04 addi r6,sp,48 + 100cc34: 100b4400 call 100b440 <__sprint_r> + 100cc38: 103bcf1e bne r2,zero,100bb78 <___vfprintf_internal_r+0x6e0> + 100cc3c: dc800e17 ldw r18,56(sp) + 100cc40: dc400d17 ldw r17,52(sp) + 100cc44: d8c01904 addi r3,sp,100 + 100cc48: d9014717 ldw r4,1308(sp) + 100cc4c: d9414117 ldw r5,1284(sp) + 100cc50: 8c400044 addi r17,r17,1 + 100cc54: 9125883a add r18,r18,r4 + 100cc58: 008001c4 movi r2,7 + 100cc5c: 19400015 stw r5,0(r3) + 100cc60: 19000115 stw r4,4(r3) + 100cc64: dc800e15 stw r18,56(sp) + 100cc68: dc400d15 stw r17,52(sp) + 100cc6c: 147cee16 blt r2,r17,100c028 <___vfprintf_internal_r+0xb90> + 100cc70: 18c00204 addi r3,r3,8 + 100cc74: 003b8606 br 100ba90 <___vfprintf_internal_r+0x5f8> + 100cc78: 38c00017 ldw r3,0(r7) + 100cc7c: 39000204 addi r4,r7,8 + 100cc80: d9014015 stw r4,1280(sp) + 100cc84: d8c14215 stw r3,1288(sp) + 100cc88: 39c00117 ldw r7,4(r7) + 100cc8c: d9c14315 stw r7,1292(sp) + 100cc90: 003e2006 br 100c514 <___vfprintf_internal_r+0x107c> + 100cc94: 0005883a mov r2,zero + 100cc98: 1409c83a sub r4,r2,r16 + 100cc9c: 1105803a cmpltu r2,r2,r4 + 100cca0: 044bc83a sub r5,zero,r17 + 100cca4: 2885c83a sub r2,r5,r2 + 100cca8: 2021883a mov r16,r4 + 100ccac: 1023883a mov r17,r2 + 100ccb0: 01000044 movi r4,1 + 100ccb4: 00800b44 movi r2,45 + 100ccb8: d8800405 stb r2,16(sp) + 100ccbc: 003c8406 br 100bed0 <___vfprintf_internal_r+0xa38> + 100ccc0: d9014f17 ldw r4,1340(sp) + 100ccc4: b00b883a mov r5,r22 + 100ccc8: d9800c04 addi r6,sp,48 + 100cccc: 100b4400 call 100b440 <__sprint_r> + 100ccd0: 103ba91e bne r2,zero,100bb78 <___vfprintf_internal_r+0x6e0> + 100ccd4: dc800e17 ldw r18,56(sp) + 100ccd8: dc400d17 ldw r17,52(sp) + 100ccdc: d9000517 ldw r4,20(sp) + 100cce0: d9401904 addi r5,sp,100 + 100cce4: 003da706 br 100c384 <___vfprintf_internal_r+0xeec> + 100cce8: d9014f17 ldw r4,1340(sp) + 100ccec: b00b883a mov r5,r22 + 100ccf0: d9800c04 addi r6,sp,48 + 100ccf4: 100b4400 call 100b440 <__sprint_r> + 100ccf8: 103b9f1e bne r2,zero,100bb78 <___vfprintf_internal_r+0x6e0> + 100ccfc: dc800e17 ldw r18,56(sp) + 100cd00: dc400d17 ldw r17,52(sp) + 100cd04: d9000517 ldw r4,20(sp) + 100cd08: d8c01904 addi r3,sp,100 + 100cd0c: 003d9106 br 100c354 <___vfprintf_internal_r+0xebc> + 100cd10: 070040b4 movhi fp,258 + 100cd14: e7054684 addi fp,fp,5402 + 100cd18: 9425883a add r18,r18,r16 + 100cd1c: 8c400044 addi r17,r17,1 + 100cd20: 008001c4 movi r2,7 + 100cd24: 1f000015 stw fp,0(r3) + 100cd28: 1c000115 stw r16,4(r3) + 100cd2c: dc800e15 stw r18,56(sp) + 100cd30: dc400d15 stw r17,52(sp) + 100cd34: 147fbc16 blt r2,r17,100cc28 <___vfprintf_internal_r+0x1790> + 100cd38: 18c00204 addi r3,r3,8 + 100cd3c: 003fc206 br 100cc48 <___vfprintf_internal_r+0x17b0> + 100cd40: d9014f17 ldw r4,1340(sp) + 100cd44: b00b883a mov r5,r22 + 100cd48: d9800c04 addi r6,sp,48 + 100cd4c: 100b4400 call 100b440 <__sprint_r> + 100cd50: 103b891e bne r2,zero,100bb78 <___vfprintf_internal_r+0x6e0> + 100cd54: dc800e17 ldw r18,56(sp) + 100cd58: d9000517 ldw r4,20(sp) + 100cd5c: d8c01904 addi r3,sp,100 + 100cd60: 003d0206 br 100c16c <___vfprintf_internal_r+0xcd4> + 100cd64: 070040b4 movhi fp,258 + 100cd68: e7054684 addi fp,fp,5402 + 100cd6c: 003be406 br 100bd00 <___vfprintf_internal_r+0x868> + 100cd70: 008040b4 movhi r2,258 + 100cd74: 10853504 addi r2,r2,5332 + 100cd78: d8814115 stw r2,1284(sp) + 100cd7c: 003df506 br 100c554 <___vfprintf_internal_r+0x10bc> + 100cd80: d9014217 ldw r4,1288(sp) + 100cd84: d9414317 ldw r5,1292(sp) + 100cd88: 10116280 call 1011628 <__isnand> + 100cd8c: 10003926 beq r2,zero,100ce74 <___vfprintf_internal_r+0x19dc> + 100cd90: d9414d17 ldw r5,1332(sp) + 100cd94: 008011c4 movi r2,71 + 100cd98: 1140ce16 blt r2,r5,100d0d4 <___vfprintf_internal_r+0x1c3c> + 100cd9c: 018040b4 movhi r6,258 + 100cda0: 31853604 addi r6,r6,5336 + 100cda4: d9814115 stw r6,1284(sp) + 100cda8: 003dea06 br 100c554 <___vfprintf_internal_r+0x10bc> + 100cdac: d9014c17 ldw r4,1328(sp) + 100cdb0: bdc00044 addi r23,r23,1 + 100cdb4: b8c00007 ldb r3,0(r23) + 100cdb8: 21000814 ori r4,r4,32 + 100cdbc: d9014c15 stw r4,1328(sp) + 100cdc0: 003a3406 br 100b694 <___vfprintf_internal_r+0x1fc> + 100cdc4: dcc14515 stw r19,1300(sp) + 100cdc8: 98011016 blt r19,zero,100d20c <___vfprintf_internal_r+0x1d74> + 100cdcc: 980f883a mov r7,r19 + 100cdd0: d8014615 stw zero,1304(sp) + 100cdd4: 003c5206 br 100bf20 <___vfprintf_internal_r+0xa88> + 100cdd8: d9014f17 ldw r4,1340(sp) + 100cddc: b00b883a mov r5,r22 + 100cde0: d9800c04 addi r6,sp,48 + 100cde4: 100b4400 call 100b440 <__sprint_r> + 100cde8: 103b631e bne r2,zero,100bb78 <___vfprintf_internal_r+0x6e0> + 100cdec: dc800e17 ldw r18,56(sp) + 100cdf0: d9000517 ldw r4,20(sp) + 100cdf4: d8c01904 addi r3,sp,100 + 100cdf8: 003f2e06 br 100cab4 <___vfprintf_internal_r+0x161c> + 100cdfc: d8c14c17 ldw r3,1328(sp) + 100ce00: 1880100c andi r2,r3,64 + 100ce04: 1000a026 beq r2,zero,100d088 <___vfprintf_internal_r+0x1bf0> + 100ce08: 38800017 ldw r2,0(r7) + 100ce0c: 39c00104 addi r7,r7,4 + 100ce10: d9c14015 stw r7,1280(sp) + 100ce14: d9014b17 ldw r4,1324(sp) + 100ce18: d9c14017 ldw r7,1280(sp) + 100ce1c: 1100000d sth r4,0(r2) + 100ce20: 0039f906 br 100b608 <___vfprintf_internal_r+0x170> + 100ce24: d9014f17 ldw r4,1340(sp) + 100ce28: b00b883a mov r5,r22 + 100ce2c: d9800c04 addi r6,sp,48 + 100ce30: 100b4400 call 100b440 <__sprint_r> + 100ce34: 103b501e bne r2,zero,100bb78 <___vfprintf_internal_r+0x6e0> + 100ce38: dc800e17 ldw r18,56(sp) + 100ce3c: dc400d17 ldw r17,52(sp) + 100ce40: d9000517 ldw r4,20(sp) + 100ce44: d8c01904 addi r3,sp,100 + 100ce48: 003f2d06 br 100cb00 <___vfprintf_internal_r+0x1668> + 100ce4c: 00800184 movi r2,6 + 100ce50: 14c09a36 bltu r2,r19,100d0bc <___vfprintf_internal_r+0x1c24> + 100ce54: dcc14515 stw r19,1300(sp) + 100ce58: 9800010e bge r19,zero,100ce60 <___vfprintf_internal_r+0x19c8> + 100ce5c: d8014515 stw zero,1300(sp) + 100ce60: 008040b4 movhi r2,258 + 100ce64: 10853804 addi r2,r2,5344 + 100ce68: 980f883a mov r7,r19 + 100ce6c: d8814115 stw r2,1284(sp) + 100ce70: 003a7806 br 100b854 <___vfprintf_internal_r+0x3bc> + 100ce74: 00bfffc4 movi r2,-1 + 100ce78: 9880e226 beq r19,r2,100d204 <___vfprintf_internal_r+0x1d6c> + 100ce7c: d9414d17 ldw r5,1332(sp) + 100ce80: 008019c4 movi r2,103 + 100ce84: 2880dc26 beq r5,r2,100d1f8 <___vfprintf_internal_r+0x1d60> + 100ce88: 008011c4 movi r2,71 + 100ce8c: 2880da26 beq r5,r2,100d1f8 <___vfprintf_internal_r+0x1d60> + 100ce90: d9414c17 ldw r5,1328(sp) + 100ce94: d9014317 ldw r4,1292(sp) + 100ce98: d9814217 ldw r6,1288(sp) + 100ce9c: 29404014 ori r5,r5,256 + 100cea0: d9414c15 stw r5,1328(sp) + 100cea4: 2000cc16 blt r4,zero,100d1d8 <___vfprintf_internal_r+0x1d40> + 100cea8: 3021883a mov r16,r6 + 100ceac: 2023883a mov r17,r4 + 100ceb0: 0039883a mov fp,zero + 100ceb4: d9414d17 ldw r5,1332(sp) + 100ceb8: 00801984 movi r2,102 + 100cebc: 2880b726 beq r5,r2,100d19c <___vfprintf_internal_r+0x1d04> + 100cec0: 00801184 movi r2,70 + 100cec4: 2880b526 beq r5,r2,100d19c <___vfprintf_internal_r+0x1d04> + 100cec8: 00801944 movi r2,101 + 100cecc: 2880c826 beq r5,r2,100d1f0 <___vfprintf_internal_r+0x1d58> + 100ced0: 00801144 movi r2,69 + 100ced4: 2880c626 beq r5,r2,100d1f0 <___vfprintf_internal_r+0x1d58> + 100ced8: 9829883a mov r20,r19 + 100cedc: d9014f17 ldw r4,1340(sp) + 100cee0: d8800504 addi r2,sp,20 + 100cee4: 880d883a mov r6,r17 + 100cee8: d8800115 stw r2,4(sp) + 100ceec: d8c00604 addi r3,sp,24 + 100cef0: d8800704 addi r2,sp,28 + 100cef4: 800b883a mov r5,r16 + 100cef8: 01c00084 movi r7,2 + 100cefc: d8c00215 stw r3,8(sp) + 100cf00: d8800315 stw r2,12(sp) + 100cf04: dd000015 stw r20,0(sp) + 100cf08: 100d6bc0 call 100d6bc <_dtoa_r> + 100cf0c: d9814d17 ldw r6,1332(sp) + 100cf10: d8814115 stw r2,1284(sp) + 100cf14: 008019c4 movi r2,103 + 100cf18: 30809526 beq r6,r2,100d170 <___vfprintf_internal_r+0x1cd8> + 100cf1c: d8c14d17 ldw r3,1332(sp) + 100cf20: 008011c4 movi r2,71 + 100cf24: 18809226 beq r3,r2,100d170 <___vfprintf_internal_r+0x1cd8> + 100cf28: d9414117 ldw r5,1284(sp) + 100cf2c: d9814d17 ldw r6,1332(sp) + 100cf30: 00801984 movi r2,102 + 100cf34: 2d25883a add r18,r5,r20 + 100cf38: 30808626 beq r6,r2,100d154 <___vfprintf_internal_r+0x1cbc> + 100cf3c: 00801184 movi r2,70 + 100cf40: 30808426 beq r6,r2,100d154 <___vfprintf_internal_r+0x1cbc> + 100cf44: 000d883a mov r6,zero + 100cf48: 000f883a mov r7,zero + 100cf4c: 880b883a mov r5,r17 + 100cf50: 8009883a mov r4,r16 + 100cf54: 10134ec0 call 10134ec <__eqdf2> + 100cf58: 1000751e bne r2,zero,100d130 <___vfprintf_internal_r+0x1c98> + 100cf5c: 9005883a mov r2,r18 + 100cf60: dc800715 stw r18,28(sp) + 100cf64: d9014117 ldw r4,1284(sp) + 100cf68: d9414d17 ldw r5,1332(sp) + 100cf6c: 00c019c4 movi r3,103 + 100cf70: 1125c83a sub r18,r2,r4 + 100cf74: 28c06826 beq r5,r3,100d118 <___vfprintf_internal_r+0x1c80> + 100cf78: 008011c4 movi r2,71 + 100cf7c: 28806626 beq r5,r2,100d118 <___vfprintf_internal_r+0x1c80> + 100cf80: d9000517 ldw r4,20(sp) + 100cf84: d8c14d17 ldw r3,1332(sp) + 100cf88: 00801944 movi r2,101 + 100cf8c: 10c05516 blt r2,r3,100d0e4 <___vfprintf_internal_r+0x1c4c> + 100cf90: 213fffc4 addi r4,r4,-1 + 100cf94: d9000515 stw r4,20(sp) + 100cf98: d8c00805 stb r3,32(sp) + 100cf9c: 2021883a mov r16,r4 + 100cfa0: 2000c116 blt r4,zero,100d2a8 <___vfprintf_internal_r+0x1e10> + 100cfa4: 00800ac4 movi r2,43 + 100cfa8: d8800845 stb r2,33(sp) + 100cfac: 00800244 movi r2,9 + 100cfb0: 1400af0e bge r2,r16,100d270 <___vfprintf_internal_r+0x1dd8> + 100cfb4: 1027883a mov r19,r2 + 100cfb8: dc400b84 addi r17,sp,46 + 100cfbc: 8009883a mov r4,r16 + 100cfc0: 01400284 movi r5,10 + 100cfc4: 1013bd40 call 1013bd4 <__modsi3> + 100cfc8: 10800c04 addi r2,r2,48 + 100cfcc: 8c7fffc4 addi r17,r17,-1 + 100cfd0: 8009883a mov r4,r16 + 100cfd4: 01400284 movi r5,10 + 100cfd8: 88800005 stb r2,0(r17) + 100cfdc: 1013b740 call 1013b74 <__divsi3> + 100cfe0: 1021883a mov r16,r2 + 100cfe4: 98bff516 blt r19,r2,100cfbc <___vfprintf_internal_r+0x1b24> + 100cfe8: 10c00c04 addi r3,r2,48 + 100cfec: d88009c4 addi r2,sp,39 + 100cff0: 108001c4 addi r2,r2,7 + 100cff4: 897fffc4 addi r5,r17,-1 + 100cff8: 88ffffc5 stb r3,-1(r17) + 100cffc: 2880a72e bgeu r5,r2,100d29c <___vfprintf_internal_r+0x1e04> + 100d000: 1009883a mov r4,r2 + 100d004: d9800804 addi r6,sp,32 + 100d008: d8c00884 addi r3,sp,34 + 100d00c: 28800003 ldbu r2,0(r5) + 100d010: 29400044 addi r5,r5,1 + 100d014: 18800005 stb r2,0(r3) + 100d018: 18c00044 addi r3,r3,1 + 100d01c: 293ffb36 bltu r5,r4,100d00c <___vfprintf_internal_r+0x1b74> + 100d020: 1987c83a sub r3,r3,r6 + 100d024: 00800044 movi r2,1 + 100d028: d8c14815 stw r3,1312(sp) + 100d02c: 90cf883a add r7,r18,r3 + 100d030: 1480960e bge r2,r18,100d28c <___vfprintf_internal_r+0x1df4> + 100d034: 39c00044 addi r7,r7,1 + 100d038: d9c14515 stw r7,1300(sp) + 100d03c: 38003416 blt r7,zero,100d110 <___vfprintf_internal_r+0x1c78> + 100d040: e0803fcc andi r2,fp,255 + 100d044: 1080201c xori r2,r2,128 + 100d048: 10bfe004 addi r2,r2,-128 + 100d04c: 10004e26 beq r2,zero,100d188 <___vfprintf_internal_r+0x1cf0> + 100d050: 00800b44 movi r2,45 + 100d054: dc814715 stw r18,1308(sp) + 100d058: d8014615 stw zero,1304(sp) + 100d05c: d8800405 stb r2,16(sp) + 100d060: 003bb106 br 100bf28 <___vfprintf_internal_r+0xa90> + 100d064: 00800b44 movi r2,45 + 100d068: d8800405 stb r2,16(sp) + 100d06c: 003d3306 br 100c53c <___vfprintf_internal_r+0x10a4> + 100d070: d9014f17 ldw r4,1340(sp) + 100d074: b00b883a mov r5,r22 + 100d078: d9800c04 addi r6,sp,48 + 100d07c: 100b4400 call 100b440 <__sprint_r> + 100d080: 103abd1e bne r2,zero,100bb78 <___vfprintf_internal_r+0x6e0> + 100d084: 003abb06 br 100bb74 <___vfprintf_internal_r+0x6dc> + 100d088: 38800017 ldw r2,0(r7) + 100d08c: 39c00104 addi r7,r7,4 + 100d090: d9c14015 stw r7,1280(sp) + 100d094: d9414b17 ldw r5,1324(sp) + 100d098: d9c14017 ldw r7,1280(sp) + 100d09c: 11400015 stw r5,0(r2) + 100d0a0: 00395906 br 100b608 <___vfprintf_internal_r+0x170> + 100d0a4: 980f883a mov r7,r19 + 100d0a8: dcc14515 stw r19,1300(sp) + 100d0ac: d8014615 stw zero,1304(sp) + 100d0b0: 003b9b06 br 100bf20 <___vfprintf_internal_r+0xa88> + 100d0b4: 0027883a mov r19,zero + 100d0b8: 00397806 br 100b69c <___vfprintf_internal_r+0x204> + 100d0bc: 00c040b4 movhi r3,258 + 100d0c0: 18c53804 addi r3,r3,5344 + 100d0c4: 100f883a mov r7,r2 + 100d0c8: d8814515 stw r2,1300(sp) + 100d0cc: d8c14115 stw r3,1284(sp) + 100d0d0: 0039e006 br 100b854 <___vfprintf_internal_r+0x3bc> + 100d0d4: 008040b4 movhi r2,258 + 100d0d8: 10853704 addi r2,r2,5340 + 100d0dc: d8814115 stw r2,1284(sp) + 100d0e0: 003d1c06 br 100c554 <___vfprintf_internal_r+0x10bc> + 100d0e4: d9414d17 ldw r5,1332(sp) + 100d0e8: 00801984 movi r2,102 + 100d0ec: 28804926 beq r5,r2,100d214 <___vfprintf_internal_r+0x1d7c> + 100d0f0: 200f883a mov r7,r4 + 100d0f4: 24805716 blt r4,r18,100d254 <___vfprintf_internal_r+0x1dbc> + 100d0f8: d9414c17 ldw r5,1328(sp) + 100d0fc: 2880004c andi r2,r5,1 + 100d100: 10000126 beq r2,zero,100d108 <___vfprintf_internal_r+0x1c70> + 100d104: 21c00044 addi r7,r4,1 + 100d108: d9c14515 stw r7,1300(sp) + 100d10c: 383fcc0e bge r7,zero,100d040 <___vfprintf_internal_r+0x1ba8> + 100d110: d8014515 stw zero,1300(sp) + 100d114: 003fca06 br 100d040 <___vfprintf_internal_r+0x1ba8> + 100d118: d9000517 ldw r4,20(sp) + 100d11c: 00bfff04 movi r2,-4 + 100d120: 1100480e bge r2,r4,100d244 <___vfprintf_internal_r+0x1dac> + 100d124: 99004716 blt r19,r4,100d244 <___vfprintf_internal_r+0x1dac> + 100d128: d8c14d15 stw r3,1332(sp) + 100d12c: 003ff006 br 100d0f0 <___vfprintf_internal_r+0x1c58> + 100d130: d8800717 ldw r2,28(sp) + 100d134: 14bf8b2e bgeu r2,r18,100cf64 <___vfprintf_internal_r+0x1acc> + 100d138: 9007883a mov r3,r18 + 100d13c: 01000c04 movi r4,48 + 100d140: 11000005 stb r4,0(r2) + 100d144: 10800044 addi r2,r2,1 + 100d148: d8800715 stw r2,28(sp) + 100d14c: 18bffc1e bne r3,r2,100d140 <___vfprintf_internal_r+0x1ca8> + 100d150: 003f8406 br 100cf64 <___vfprintf_internal_r+0x1acc> + 100d154: d8814117 ldw r2,1284(sp) + 100d158: 10c00007 ldb r3,0(r2) + 100d15c: 00800c04 movi r2,48 + 100d160: 18805b26 beq r3,r2,100d2d0 <___vfprintf_internal_r+0x1e38> + 100d164: d9000517 ldw r4,20(sp) + 100d168: 9125883a add r18,r18,r4 + 100d16c: 003f7506 br 100cf44 <___vfprintf_internal_r+0x1aac> + 100d170: d9014c17 ldw r4,1328(sp) + 100d174: 2080004c andi r2,r4,1 + 100d178: 1005003a cmpeq r2,r2,zero + 100d17c: 103f6a26 beq r2,zero,100cf28 <___vfprintf_internal_r+0x1a90> + 100d180: d8800717 ldw r2,28(sp) + 100d184: 003f7706 br 100cf64 <___vfprintf_internal_r+0x1acc> + 100d188: d9c14515 stw r7,1300(sp) + 100d18c: 38004d16 blt r7,zero,100d2c4 <___vfprintf_internal_r+0x1e2c> + 100d190: dc814715 stw r18,1308(sp) + 100d194: d8014615 stw zero,1304(sp) + 100d198: 003b6106 br 100bf20 <___vfprintf_internal_r+0xa88> + 100d19c: d9014f17 ldw r4,1340(sp) + 100d1a0: d8800504 addi r2,sp,20 + 100d1a4: d8800115 stw r2,4(sp) + 100d1a8: d8c00604 addi r3,sp,24 + 100d1ac: d8800704 addi r2,sp,28 + 100d1b0: 800b883a mov r5,r16 + 100d1b4: 880d883a mov r6,r17 + 100d1b8: 01c000c4 movi r7,3 + 100d1bc: d8c00215 stw r3,8(sp) + 100d1c0: d8800315 stw r2,12(sp) + 100d1c4: dcc00015 stw r19,0(sp) + 100d1c8: 9829883a mov r20,r19 + 100d1cc: 100d6bc0 call 100d6bc <_dtoa_r> + 100d1d0: d8814115 stw r2,1284(sp) + 100d1d4: 003f5106 br 100cf1c <___vfprintf_internal_r+0x1a84> + 100d1d8: d8c14217 ldw r3,1288(sp) + 100d1dc: d9014317 ldw r4,1292(sp) + 100d1e0: 07000b44 movi fp,45 + 100d1e4: 1821883a mov r16,r3 + 100d1e8: 2460003c xorhi r17,r4,32768 + 100d1ec: 003f3106 br 100ceb4 <___vfprintf_internal_r+0x1a1c> + 100d1f0: 9d000044 addi r20,r19,1 + 100d1f4: 003f3906 br 100cedc <___vfprintf_internal_r+0x1a44> + 100d1f8: 983f251e bne r19,zero,100ce90 <___vfprintf_internal_r+0x19f8> + 100d1fc: 04c00044 movi r19,1 + 100d200: 003f2306 br 100ce90 <___vfprintf_internal_r+0x19f8> + 100d204: 04c00184 movi r19,6 + 100d208: 003f2106 br 100ce90 <___vfprintf_internal_r+0x19f8> + 100d20c: d8014515 stw zero,1300(sp) + 100d210: 003eee06 br 100cdcc <___vfprintf_internal_r+0x1934> + 100d214: 200f883a mov r7,r4 + 100d218: 0100370e bge zero,r4,100d2f8 <___vfprintf_internal_r+0x1e60> + 100d21c: 9800031e bne r19,zero,100d22c <___vfprintf_internal_r+0x1d94> + 100d220: d9814c17 ldw r6,1328(sp) + 100d224: 3080004c andi r2,r6,1 + 100d228: 103fb726 beq r2,zero,100d108 <___vfprintf_internal_r+0x1c70> + 100d22c: 20800044 addi r2,r4,1 + 100d230: 98a7883a add r19,r19,r2 + 100d234: dcc14515 stw r19,1300(sp) + 100d238: 980f883a mov r7,r19 + 100d23c: 983f800e bge r19,zero,100d040 <___vfprintf_internal_r+0x1ba8> + 100d240: 003fb306 br 100d110 <___vfprintf_internal_r+0x1c78> + 100d244: d9814d17 ldw r6,1332(sp) + 100d248: 31bfff84 addi r6,r6,-2 + 100d24c: d9814d15 stw r6,1332(sp) + 100d250: 003f4c06 br 100cf84 <___vfprintf_internal_r+0x1aec> + 100d254: 0100180e bge zero,r4,100d2b8 <___vfprintf_internal_r+0x1e20> + 100d258: 00800044 movi r2,1 + 100d25c: 1485883a add r2,r2,r18 + 100d260: d8814515 stw r2,1300(sp) + 100d264: 100f883a mov r7,r2 + 100d268: 103f750e bge r2,zero,100d040 <___vfprintf_internal_r+0x1ba8> + 100d26c: 003fa806 br 100d110 <___vfprintf_internal_r+0x1c78> + 100d270: 80c00c04 addi r3,r16,48 + 100d274: 00800c04 movi r2,48 + 100d278: d8c008c5 stb r3,35(sp) + 100d27c: d9800804 addi r6,sp,32 + 100d280: d8c00904 addi r3,sp,36 + 100d284: d8800885 stb r2,34(sp) + 100d288: 003f6506 br 100d020 <___vfprintf_internal_r+0x1b88> + 100d28c: d9014c17 ldw r4,1328(sp) + 100d290: 2084703a and r2,r4,r2 + 100d294: 103f9c26 beq r2,zero,100d108 <___vfprintf_internal_r+0x1c70> + 100d298: 003f6606 br 100d034 <___vfprintf_internal_r+0x1b9c> + 100d29c: d9800804 addi r6,sp,32 + 100d2a0: d8c00884 addi r3,sp,34 + 100d2a4: 003f5e06 br 100d020 <___vfprintf_internal_r+0x1b88> + 100d2a8: 00800b44 movi r2,45 + 100d2ac: 0121c83a sub r16,zero,r4 + 100d2b0: d8800845 stb r2,33(sp) + 100d2b4: 003f3d06 br 100cfac <___vfprintf_internal_r+0x1b14> + 100d2b8: 00800084 movi r2,2 + 100d2bc: 1105c83a sub r2,r2,r4 + 100d2c0: 003fe606 br 100d25c <___vfprintf_internal_r+0x1dc4> + 100d2c4: d8014515 stw zero,1300(sp) + 100d2c8: dc814715 stw r18,1308(sp) + 100d2cc: 003fb106 br 100d194 <___vfprintf_internal_r+0x1cfc> + 100d2d0: 000d883a mov r6,zero + 100d2d4: 000f883a mov r7,zero + 100d2d8: 8009883a mov r4,r16 + 100d2dc: 880b883a mov r5,r17 + 100d2e0: 10135740 call 1013574 <__nedf2> + 100d2e4: 103f9f26 beq r2,zero,100d164 <___vfprintf_internal_r+0x1ccc> + 100d2e8: 00800044 movi r2,1 + 100d2ec: 1509c83a sub r4,r2,r20 + 100d2f0: d9000515 stw r4,20(sp) + 100d2f4: 003f9b06 br 100d164 <___vfprintf_internal_r+0x1ccc> + 100d2f8: 98000d1e bne r19,zero,100d330 <___vfprintf_internal_r+0x1e98> + 100d2fc: d8c14c17 ldw r3,1328(sp) + 100d300: 1880004c andi r2,r3,1 + 100d304: 10000a1e bne r2,zero,100d330 <___vfprintf_internal_r+0x1e98> + 100d308: 01000044 movi r4,1 + 100d30c: 200f883a mov r7,r4 + 100d310: d9014515 stw r4,1300(sp) + 100d314: 003f4a06 br 100d040 <___vfprintf_internal_r+0x1ba8> + 100d318: 3cc00017 ldw r19,0(r7) + 100d31c: 39c00104 addi r7,r7,4 + 100d320: 983d0e0e bge r19,zero,100c75c <___vfprintf_internal_r+0x12c4> + 100d324: b8c00007 ldb r3,0(r23) + 100d328: 04ffffc4 movi r19,-1 + 100d32c: 0038d906 br 100b694 <___vfprintf_internal_r+0x1fc> + 100d330: 9cc00084 addi r19,r19,2 + 100d334: dcc14515 stw r19,1300(sp) + 100d338: 980f883a mov r7,r19 + 100d33c: 983f400e bge r19,zero,100d040 <___vfprintf_internal_r+0x1ba8> + 100d340: 003f7306 br 100d110 <___vfprintf_internal_r+0x1c78> + +0100d344 <__vfprintf_internal>: + 100d344: 008040b4 movhi r2,258 + 100d348: 108dc804 addi r2,r2,14112 + 100d34c: 2013883a mov r9,r4 + 100d350: 11000017 ldw r4,0(r2) + 100d354: 2805883a mov r2,r5 + 100d358: 300f883a mov r7,r6 + 100d35c: 480b883a mov r5,r9 + 100d360: 100d883a mov r6,r2 + 100d364: 100b4981 jmpi 100b498 <___vfprintf_internal_r> + +0100d368 <__swsetup_r>: + 100d368: 008040b4 movhi r2,258 + 100d36c: 108dc804 addi r2,r2,14112 + 100d370: 10c00017 ldw r3,0(r2) + 100d374: defffd04 addi sp,sp,-12 + 100d378: dc400115 stw r17,4(sp) + 100d37c: dc000015 stw r16,0(sp) + 100d380: dfc00215 stw ra,8(sp) + 100d384: 2023883a mov r17,r4 + 100d388: 2821883a mov r16,r5 + 100d38c: 18000226 beq r3,zero,100d398 <__swsetup_r+0x30> + 100d390: 18800e17 ldw r2,56(r3) + 100d394: 10001f26 beq r2,zero,100d414 <__swsetup_r+0xac> + 100d398: 8100030b ldhu r4,12(r16) + 100d39c: 2080020c andi r2,r4,8 + 100d3a0: 10002826 beq r2,zero,100d444 <__swsetup_r+0xdc> + 100d3a4: 81400417 ldw r5,16(r16) + 100d3a8: 28001d26 beq r5,zero,100d420 <__swsetup_r+0xb8> + 100d3ac: 2080004c andi r2,r4,1 + 100d3b0: 1005003a cmpeq r2,r2,zero + 100d3b4: 10000b26 beq r2,zero,100d3e4 <__swsetup_r+0x7c> + 100d3b8: 2080008c andi r2,r4,2 + 100d3bc: 10001226 beq r2,zero,100d408 <__swsetup_r+0xa0> + 100d3c0: 0005883a mov r2,zero + 100d3c4: 80800215 stw r2,8(r16) + 100d3c8: 28000b26 beq r5,zero,100d3f8 <__swsetup_r+0x90> + 100d3cc: 0005883a mov r2,zero + 100d3d0: dfc00217 ldw ra,8(sp) + 100d3d4: dc400117 ldw r17,4(sp) + 100d3d8: dc000017 ldw r16,0(sp) + 100d3dc: dec00304 addi sp,sp,12 + 100d3e0: f800283a ret + 100d3e4: 80800517 ldw r2,20(r16) + 100d3e8: 80000215 stw zero,8(r16) + 100d3ec: 0085c83a sub r2,zero,r2 + 100d3f0: 80800615 stw r2,24(r16) + 100d3f4: 283ff51e bne r5,zero,100d3cc <__swsetup_r+0x64> + 100d3f8: 2080200c andi r2,r4,128 + 100d3fc: 103ff326 beq r2,zero,100d3cc <__swsetup_r+0x64> + 100d400: 00bfffc4 movi r2,-1 + 100d404: 003ff206 br 100d3d0 <__swsetup_r+0x68> + 100d408: 80800517 ldw r2,20(r16) + 100d40c: 80800215 stw r2,8(r16) + 100d410: 003fed06 br 100d3c8 <__swsetup_r+0x60> + 100d414: 1809883a mov r4,r3 + 100d418: 100ef080 call 100ef08 <__sinit> + 100d41c: 003fde06 br 100d398 <__swsetup_r+0x30> + 100d420: 20c0a00c andi r3,r4,640 + 100d424: 00808004 movi r2,512 + 100d428: 18bfe026 beq r3,r2,100d3ac <__swsetup_r+0x44> + 100d42c: 8809883a mov r4,r17 + 100d430: 800b883a mov r5,r16 + 100d434: 100fc800 call 100fc80 <__smakebuf_r> + 100d438: 8100030b ldhu r4,12(r16) + 100d43c: 81400417 ldw r5,16(r16) + 100d440: 003fda06 br 100d3ac <__swsetup_r+0x44> + 100d444: 2080040c andi r2,r4,16 + 100d448: 103fed26 beq r2,zero,100d400 <__swsetup_r+0x98> + 100d44c: 2080010c andi r2,r4,4 + 100d450: 10001226 beq r2,zero,100d49c <__swsetup_r+0x134> + 100d454: 81400c17 ldw r5,48(r16) + 100d458: 28000526 beq r5,zero,100d470 <__swsetup_r+0x108> + 100d45c: 80801004 addi r2,r16,64 + 100d460: 28800226 beq r5,r2,100d46c <__swsetup_r+0x104> + 100d464: 8809883a mov r4,r17 + 100d468: 100f28c0 call 100f28c <_free_r> + 100d46c: 80000c15 stw zero,48(r16) + 100d470: 8080030b ldhu r2,12(r16) + 100d474: 81400417 ldw r5,16(r16) + 100d478: 80000115 stw zero,4(r16) + 100d47c: 10bff6cc andi r2,r2,65499 + 100d480: 8080030d sth r2,12(r16) + 100d484: 81400015 stw r5,0(r16) + 100d488: 8080030b ldhu r2,12(r16) + 100d48c: 10800214 ori r2,r2,8 + 100d490: 113fffcc andi r4,r2,65535 + 100d494: 8080030d sth r2,12(r16) + 100d498: 003fc306 br 100d3a8 <__swsetup_r+0x40> + 100d49c: 81400417 ldw r5,16(r16) + 100d4a0: 003ff906 br 100d488 <__swsetup_r+0x120> + +0100d4a4 : + 100d4a4: 28c00417 ldw r3,16(r5) + 100d4a8: 20800417 ldw r2,16(r4) + 100d4ac: defff604 addi sp,sp,-40 + 100d4b0: ddc00715 stw r23,28(sp) + 100d4b4: dd400515 stw r21,20(sp) + 100d4b8: dfc00915 stw ra,36(sp) + 100d4bc: df000815 stw fp,32(sp) + 100d4c0: dd800615 stw r22,24(sp) + 100d4c4: dd000415 stw r20,16(sp) + 100d4c8: dcc00315 stw r19,12(sp) + 100d4cc: dc800215 stw r18,8(sp) + 100d4d0: dc400115 stw r17,4(sp) + 100d4d4: dc000015 stw r16,0(sp) + 100d4d8: 202f883a mov r23,r4 + 100d4dc: 282b883a mov r21,r5 + 100d4e0: 10c07416 blt r2,r3,100d6b4 + 100d4e4: 1c7fffc4 addi r17,r3,-1 + 100d4e8: 8c45883a add r2,r17,r17 + 100d4ec: 1085883a add r2,r2,r2 + 100d4f0: 2c000504 addi r16,r5,20 + 100d4f4: 24c00504 addi r19,r4,20 + 100d4f8: 14ed883a add r22,r2,r19 + 100d4fc: 80a5883a add r18,r16,r2 + 100d500: b7000017 ldw fp,0(r22) + 100d504: 91400017 ldw r5,0(r18) + 100d508: e009883a mov r4,fp + 100d50c: 29400044 addi r5,r5,1 + 100d510: 1013c340 call 1013c34 <__udivsi3> + 100d514: 1029883a mov r20,r2 + 100d518: 10003c1e bne r2,zero,100d60c + 100d51c: a80b883a mov r5,r21 + 100d520: b809883a mov r4,r23 + 100d524: 100ff700 call 100ff70 <__mcmp> + 100d528: 10002b16 blt r2,zero,100d5d8 + 100d52c: a5000044 addi r20,r20,1 + 100d530: 980f883a mov r7,r19 + 100d534: 0011883a mov r8,zero + 100d538: 0009883a mov r4,zero + 100d53c: 81400017 ldw r5,0(r16) + 100d540: 38c00017 ldw r3,0(r7) + 100d544: 84000104 addi r16,r16,4 + 100d548: 28bfffcc andi r2,r5,65535 + 100d54c: 2085883a add r2,r4,r2 + 100d550: 11bfffcc andi r6,r2,65535 + 100d554: 193fffcc andi r4,r3,65535 + 100d558: 1004d43a srli r2,r2,16 + 100d55c: 280ad43a srli r5,r5,16 + 100d560: 2189c83a sub r4,r4,r6 + 100d564: 2209883a add r4,r4,r8 + 100d568: 1806d43a srli r3,r3,16 + 100d56c: 288b883a add r5,r5,r2 + 100d570: 200dd43a srai r6,r4,16 + 100d574: 28bfffcc andi r2,r5,65535 + 100d578: 1887c83a sub r3,r3,r2 + 100d57c: 1987883a add r3,r3,r6 + 100d580: 3900000d sth r4,0(r7) + 100d584: 38c0008d sth r3,2(r7) + 100d588: 2808d43a srli r4,r5,16 + 100d58c: 39c00104 addi r7,r7,4 + 100d590: 1811d43a srai r8,r3,16 + 100d594: 943fe92e bgeu r18,r16,100d53c + 100d598: 8c45883a add r2,r17,r17 + 100d59c: 1085883a add r2,r2,r2 + 100d5a0: 9885883a add r2,r19,r2 + 100d5a4: 10c00017 ldw r3,0(r2) + 100d5a8: 18000b1e bne r3,zero,100d5d8 + 100d5ac: 113fff04 addi r4,r2,-4 + 100d5b0: 9900082e bgeu r19,r4,100d5d4 + 100d5b4: 10bfff17 ldw r2,-4(r2) + 100d5b8: 10000326 beq r2,zero,100d5c8 + 100d5bc: 00000506 br 100d5d4 + 100d5c0: 20800017 ldw r2,0(r4) + 100d5c4: 1000031e bne r2,zero,100d5d4 + 100d5c8: 213fff04 addi r4,r4,-4 + 100d5cc: 8c7fffc4 addi r17,r17,-1 + 100d5d0: 993ffb36 bltu r19,r4,100d5c0 + 100d5d4: bc400415 stw r17,16(r23) + 100d5d8: a005883a mov r2,r20 + 100d5dc: dfc00917 ldw ra,36(sp) + 100d5e0: df000817 ldw fp,32(sp) + 100d5e4: ddc00717 ldw r23,28(sp) + 100d5e8: dd800617 ldw r22,24(sp) + 100d5ec: dd400517 ldw r21,20(sp) + 100d5f0: dd000417 ldw r20,16(sp) + 100d5f4: dcc00317 ldw r19,12(sp) + 100d5f8: dc800217 ldw r18,8(sp) + 100d5fc: dc400117 ldw r17,4(sp) + 100d600: dc000017 ldw r16,0(sp) + 100d604: dec00a04 addi sp,sp,40 + 100d608: f800283a ret + 100d60c: 980f883a mov r7,r19 + 100d610: 8011883a mov r8,r16 + 100d614: 0013883a mov r9,zero + 100d618: 000d883a mov r6,zero + 100d61c: 40c00017 ldw r3,0(r8) + 100d620: 39000017 ldw r4,0(r7) + 100d624: 42000104 addi r8,r8,4 + 100d628: 18bfffcc andi r2,r3,65535 + 100d62c: a085383a mul r2,r20,r2 + 100d630: 1806d43a srli r3,r3,16 + 100d634: 217fffcc andi r5,r4,65535 + 100d638: 3085883a add r2,r6,r2 + 100d63c: 11bfffcc andi r6,r2,65535 + 100d640: a0c7383a mul r3,r20,r3 + 100d644: 1004d43a srli r2,r2,16 + 100d648: 298bc83a sub r5,r5,r6 + 100d64c: 2a4b883a add r5,r5,r9 + 100d650: 2008d43a srli r4,r4,16 + 100d654: 1887883a add r3,r3,r2 + 100d658: 280dd43a srai r6,r5,16 + 100d65c: 18bfffcc andi r2,r3,65535 + 100d660: 2089c83a sub r4,r4,r2 + 100d664: 2189883a add r4,r4,r6 + 100d668: 3900008d sth r4,2(r7) + 100d66c: 3940000d sth r5,0(r7) + 100d670: 180cd43a srli r6,r3,16 + 100d674: 39c00104 addi r7,r7,4 + 100d678: 2013d43a srai r9,r4,16 + 100d67c: 923fe72e bgeu r18,r8,100d61c + 100d680: e03fa61e bne fp,zero,100d51c + 100d684: b0ffff04 addi r3,r22,-4 + 100d688: 98c0082e bgeu r19,r3,100d6ac + 100d68c: b0bfff17 ldw r2,-4(r22) + 100d690: 10000326 beq r2,zero,100d6a0 + 100d694: 00000506 br 100d6ac + 100d698: 18800017 ldw r2,0(r3) + 100d69c: 1000031e bne r2,zero,100d6ac + 100d6a0: 18ffff04 addi r3,r3,-4 + 100d6a4: 8c7fffc4 addi r17,r17,-1 + 100d6a8: 98fffb36 bltu r19,r3,100d698 + 100d6ac: bc400415 stw r17,16(r23) + 100d6b0: 003f9a06 br 100d51c + 100d6b4: 0005883a mov r2,zero + 100d6b8: 003fc806 br 100d5dc + +0100d6bc <_dtoa_r>: + 100d6bc: 22001017 ldw r8,64(r4) + 100d6c0: deffda04 addi sp,sp,-152 + 100d6c4: dd402115 stw r21,132(sp) + 100d6c8: dd002015 stw r20,128(sp) + 100d6cc: dc801e15 stw r18,120(sp) + 100d6d0: dc401d15 stw r17,116(sp) + 100d6d4: dfc02515 stw ra,148(sp) + 100d6d8: df002415 stw fp,144(sp) + 100d6dc: ddc02315 stw r23,140(sp) + 100d6e0: dd802215 stw r22,136(sp) + 100d6e4: dcc01f15 stw r19,124(sp) + 100d6e8: dc001c15 stw r16,112(sp) + 100d6ec: d9001615 stw r4,88(sp) + 100d6f0: 3023883a mov r17,r6 + 100d6f4: 2829883a mov r20,r5 + 100d6f8: d9c01715 stw r7,92(sp) + 100d6fc: dc802817 ldw r18,160(sp) + 100d700: 302b883a mov r21,r6 + 100d704: 40000a26 beq r8,zero,100d730 <_dtoa_r+0x74> + 100d708: 20801117 ldw r2,68(r4) + 100d70c: 400b883a mov r5,r8 + 100d710: 40800115 stw r2,4(r8) + 100d714: 20c01117 ldw r3,68(r4) + 100d718: 00800044 movi r2,1 + 100d71c: 10c4983a sll r2,r2,r3 + 100d720: 40800215 stw r2,8(r8) + 100d724: 100fe140 call 100fe14 <_Bfree> + 100d728: d8c01617 ldw r3,88(sp) + 100d72c: 18001015 stw zero,64(r3) + 100d730: 8800a316 blt r17,zero,100d9c0 <_dtoa_r+0x304> + 100d734: 90000015 stw zero,0(r18) + 100d738: a8dffc2c andhi r3,r21,32752 + 100d73c: 009ffc34 movhi r2,32752 + 100d740: 18809126 beq r3,r2,100d988 <_dtoa_r+0x2cc> + 100d744: 000d883a mov r6,zero + 100d748: 000f883a mov r7,zero + 100d74c: a009883a mov r4,r20 + 100d750: a80b883a mov r5,r21 + 100d754: dd001215 stw r20,72(sp) + 100d758: dd401315 stw r21,76(sp) + 100d75c: 10135740 call 1013574 <__nedf2> + 100d760: 1000171e bne r2,zero,100d7c0 <_dtoa_r+0x104> + 100d764: d9802717 ldw r6,156(sp) + 100d768: 00800044 movi r2,1 + 100d76c: 30800015 stw r2,0(r6) + 100d770: d8802917 ldw r2,164(sp) + 100d774: 10029b26 beq r2,zero,100e1e4 <_dtoa_r+0xb28> + 100d778: d9002917 ldw r4,164(sp) + 100d77c: 008040b4 movhi r2,258 + 100d780: 10854644 addi r2,r2,5401 + 100d784: 10ffffc4 addi r3,r2,-1 + 100d788: 20800015 stw r2,0(r4) + 100d78c: 1805883a mov r2,r3 + 100d790: dfc02517 ldw ra,148(sp) + 100d794: df002417 ldw fp,144(sp) + 100d798: ddc02317 ldw r23,140(sp) + 100d79c: dd802217 ldw r22,136(sp) + 100d7a0: dd402117 ldw r21,132(sp) + 100d7a4: dd002017 ldw r20,128(sp) + 100d7a8: dcc01f17 ldw r19,124(sp) + 100d7ac: dc801e17 ldw r18,120(sp) + 100d7b0: dc401d17 ldw r17,116(sp) + 100d7b4: dc001c17 ldw r16,112(sp) + 100d7b8: dec02604 addi sp,sp,152 + 100d7bc: f800283a ret + 100d7c0: d9001617 ldw r4,88(sp) + 100d7c4: d9401217 ldw r5,72(sp) + 100d7c8: d8800104 addi r2,sp,4 + 100d7cc: a80d883a mov r6,r21 + 100d7d0: d9c00204 addi r7,sp,8 + 100d7d4: d8800015 stw r2,0(sp) + 100d7d8: 10104500 call 1010450 <__d2b> + 100d7dc: d8800715 stw r2,28(sp) + 100d7e0: a804d53a srli r2,r21,20 + 100d7e4: 1101ffcc andi r4,r2,2047 + 100d7e8: 20008626 beq r4,zero,100da04 <_dtoa_r+0x348> + 100d7ec: d8c01217 ldw r3,72(sp) + 100d7f0: 00800434 movhi r2,16 + 100d7f4: 10bfffc4 addi r2,r2,-1 + 100d7f8: ddc00117 ldw r23,4(sp) + 100d7fc: a884703a and r2,r21,r2 + 100d800: 1811883a mov r8,r3 + 100d804: 124ffc34 orhi r9,r2,16368 + 100d808: 25bf0044 addi r22,r4,-1023 + 100d80c: d8000815 stw zero,32(sp) + 100d810: 0005883a mov r2,zero + 100d814: 00cffe34 movhi r3,16376 + 100d818: 480b883a mov r5,r9 + 100d81c: 4009883a mov r4,r8 + 100d820: 180f883a mov r7,r3 + 100d824: 100d883a mov r6,r2 + 100d828: 1012ddc0 call 1012ddc <__subdf3> + 100d82c: 0218dbf4 movhi r8,25455 + 100d830: 4210d844 addi r8,r8,17249 + 100d834: 024ff4f4 movhi r9,16339 + 100d838: 4a61e9c4 addi r9,r9,-30809 + 100d83c: 480f883a mov r7,r9 + 100d840: 400d883a mov r6,r8 + 100d844: 180b883a mov r5,r3 + 100d848: 1009883a mov r4,r2 + 100d84c: 1012ed00 call 1012ed0 <__muldf3> + 100d850: 0222d874 movhi r8,35681 + 100d854: 42322cc4 addi r8,r8,-14157 + 100d858: 024ff1f4 movhi r9,16327 + 100d85c: 4a628a04 addi r9,r9,-30168 + 100d860: 480f883a mov r7,r9 + 100d864: 400d883a mov r6,r8 + 100d868: 180b883a mov r5,r3 + 100d86c: 1009883a mov r4,r2 + 100d870: 1012e5c0 call 1012e5c <__adddf3> + 100d874: b009883a mov r4,r22 + 100d878: 1021883a mov r16,r2 + 100d87c: 1823883a mov r17,r3 + 100d880: 10137940 call 1013794 <__floatsidf> + 100d884: 021427f4 movhi r8,20639 + 100d888: 421e7ec4 addi r8,r8,31227 + 100d88c: 024ff4f4 movhi r9,16339 + 100d890: 4a5104c4 addi r9,r9,17427 + 100d894: 480f883a mov r7,r9 + 100d898: 400d883a mov r6,r8 + 100d89c: 180b883a mov r5,r3 + 100d8a0: 1009883a mov r4,r2 + 100d8a4: 1012ed00 call 1012ed0 <__muldf3> + 100d8a8: 180f883a mov r7,r3 + 100d8ac: 880b883a mov r5,r17 + 100d8b0: 100d883a mov r6,r2 + 100d8b4: 8009883a mov r4,r16 + 100d8b8: 1012e5c0 call 1012e5c <__adddf3> + 100d8bc: 1009883a mov r4,r2 + 100d8c0: 180b883a mov r5,r3 + 100d8c4: 1021883a mov r16,r2 + 100d8c8: 1823883a mov r17,r3 + 100d8cc: 101388c0 call 101388c <__fixdfsi> + 100d8d0: 000d883a mov r6,zero + 100d8d4: 000f883a mov r7,zero + 100d8d8: 8009883a mov r4,r16 + 100d8dc: 880b883a mov r5,r17 + 100d8e0: d8800d15 stw r2,52(sp) + 100d8e4: 101370c0 call 101370c <__ltdf2> + 100d8e8: 10031716 blt r2,zero,100e548 <_dtoa_r+0xe8c> + 100d8ec: d8c00d17 ldw r3,52(sp) + 100d8f0: 00800584 movi r2,22 + 100d8f4: 10c1482e bgeu r2,r3,100de18 <_dtoa_r+0x75c> + 100d8f8: 01000044 movi r4,1 + 100d8fc: d9000c15 stw r4,48(sp) + 100d900: bd85c83a sub r2,r23,r22 + 100d904: 11bfffc4 addi r6,r2,-1 + 100d908: 30030b16 blt r6,zero,100e538 <_dtoa_r+0xe7c> + 100d90c: d9800a15 stw r6,40(sp) + 100d910: d8001115 stw zero,68(sp) + 100d914: d8c00d17 ldw r3,52(sp) + 100d918: 1802ff16 blt r3,zero,100e518 <_dtoa_r+0xe5c> + 100d91c: d9000a17 ldw r4,40(sp) + 100d920: d8c00915 stw r3,36(sp) + 100d924: d8001015 stw zero,64(sp) + 100d928: 20c9883a add r4,r4,r3 + 100d92c: d9000a15 stw r4,40(sp) + 100d930: d9001717 ldw r4,92(sp) + 100d934: 00800244 movi r2,9 + 100d938: 11004636 bltu r2,r4,100da54 <_dtoa_r+0x398> + 100d93c: 00800144 movi r2,5 + 100d940: 11020416 blt r2,r4,100e154 <_dtoa_r+0xa98> + 100d944: 04400044 movi r17,1 + 100d948: d8c01717 ldw r3,92(sp) + 100d94c: 00800144 movi r2,5 + 100d950: 10c1ed36 bltu r2,r3,100e108 <_dtoa_r+0xa4c> + 100d954: 18c5883a add r2,r3,r3 + 100d958: 1085883a add r2,r2,r2 + 100d95c: 00c04074 movhi r3,257 + 100d960: 18f65c04 addi r3,r3,-9872 + 100d964: 10c5883a add r2,r2,r3 + 100d968: 11000017 ldw r4,0(r2) + 100d96c: 2000683a jmp r4 + 100d970: 0100da5c xori r4,zero,873 + 100d974: 0100da5c xori r4,zero,873 + 100d978: 0100e45c xori r4,zero,913 + 100d97c: 0100e434 movhi r4,912 + 100d980: 0100e478 rdprs r4,zero,913 + 100d984: 0100e484 movi r4,914 + 100d988: d9002717 ldw r4,156(sp) + 100d98c: 0089c3c4 movi r2,9999 + 100d990: 20800015 stw r2,0(r4) + 100d994: a0001026 beq r20,zero,100d9d8 <_dtoa_r+0x31c> + 100d998: 00c040b4 movhi r3,258 + 100d99c: 18c5f204 addi r3,r3,6088 + 100d9a0: d9802917 ldw r6,164(sp) + 100d9a4: 303f7926 beq r6,zero,100d78c <_dtoa_r+0xd0> + 100d9a8: 188000c7 ldb r2,3(r3) + 100d9ac: 190000c4 addi r4,r3,3 + 100d9b0: 1000101e bne r2,zero,100d9f4 <_dtoa_r+0x338> + 100d9b4: d8802917 ldw r2,164(sp) + 100d9b8: 11000015 stw r4,0(r2) + 100d9bc: 003f7306 br 100d78c <_dtoa_r+0xd0> + 100d9c0: 00a00034 movhi r2,32768 + 100d9c4: 10bfffc4 addi r2,r2,-1 + 100d9c8: 00c00044 movi r3,1 + 100d9cc: 88aa703a and r21,r17,r2 + 100d9d0: 90c00015 stw r3,0(r18) + 100d9d4: 003f5806 br 100d738 <_dtoa_r+0x7c> + 100d9d8: 00800434 movhi r2,16 + 100d9dc: 10bfffc4 addi r2,r2,-1 + 100d9e0: a884703a and r2,r21,r2 + 100d9e4: 103fec1e bne r2,zero,100d998 <_dtoa_r+0x2dc> + 100d9e8: 00c040b4 movhi r3,258 + 100d9ec: 18c5ef04 addi r3,r3,6076 + 100d9f0: 003feb06 br 100d9a0 <_dtoa_r+0x2e4> + 100d9f4: d8802917 ldw r2,164(sp) + 100d9f8: 19000204 addi r4,r3,8 + 100d9fc: 11000015 stw r4,0(r2) + 100da00: 003f6206 br 100d78c <_dtoa_r+0xd0> + 100da04: ddc00117 ldw r23,4(sp) + 100da08: d8800217 ldw r2,8(sp) + 100da0c: 01000804 movi r4,32 + 100da10: b8c10c84 addi r3,r23,1074 + 100da14: 18a3883a add r17,r3,r2 + 100da18: 2441b80e bge r4,r17,100e0fc <_dtoa_r+0xa40> + 100da1c: 00c01004 movi r3,64 + 100da20: 1c47c83a sub r3,r3,r17 + 100da24: 88bff804 addi r2,r17,-32 + 100da28: a8c6983a sll r3,r21,r3 + 100da2c: a084d83a srl r2,r20,r2 + 100da30: 1888b03a or r4,r3,r2 + 100da34: 10139640 call 1013964 <__floatunsidf> + 100da38: 1011883a mov r8,r2 + 100da3c: 00bf8434 movhi r2,65040 + 100da40: 01000044 movi r4,1 + 100da44: 10d3883a add r9,r2,r3 + 100da48: 8dbef344 addi r22,r17,-1075 + 100da4c: d9000815 stw r4,32(sp) + 100da50: 003f6f06 br 100d810 <_dtoa_r+0x154> + 100da54: d8001715 stw zero,92(sp) + 100da58: 04400044 movi r17,1 + 100da5c: 00bfffc4 movi r2,-1 + 100da60: 00c00044 movi r3,1 + 100da64: d8800e15 stw r2,56(sp) + 100da68: d8002615 stw zero,152(sp) + 100da6c: d8800f15 stw r2,60(sp) + 100da70: d8c00b15 stw r3,44(sp) + 100da74: 1021883a mov r16,r2 + 100da78: d8801617 ldw r2,88(sp) + 100da7c: 10001115 stw zero,68(r2) + 100da80: d8801617 ldw r2,88(sp) + 100da84: 11401117 ldw r5,68(r2) + 100da88: 1009883a mov r4,r2 + 100da8c: 10103940 call 1010394 <_Balloc> + 100da90: d8c01617 ldw r3,88(sp) + 100da94: d8800515 stw r2,20(sp) + 100da98: 18801015 stw r2,64(r3) + 100da9c: 00800384 movi r2,14 + 100daa0: 14006836 bltu r2,r16,100dc44 <_dtoa_r+0x588> + 100daa4: 8805003a cmpeq r2,r17,zero + 100daa8: 1000661e bne r2,zero,100dc44 <_dtoa_r+0x588> + 100daac: d9000d17 ldw r4,52(sp) + 100dab0: 0102300e bge zero,r4,100e374 <_dtoa_r+0xcb8> + 100dab4: 208003cc andi r2,r4,15 + 100dab8: 100490fa slli r2,r2,3 + 100dabc: 2025d13a srai r18,r4,4 + 100dac0: 00c040b4 movhi r3,258 + 100dac4: 18c60404 addi r3,r3,6160 + 100dac8: 10c5883a add r2,r2,r3 + 100dacc: 90c0040c andi r3,r18,16 + 100dad0: 14000017 ldw r16,0(r2) + 100dad4: 14400117 ldw r17,4(r2) + 100dad8: 18036a1e bne r3,zero,100e884 <_dtoa_r+0x11c8> + 100dadc: 05800084 movi r22,2 + 100dae0: 90001026 beq r18,zero,100db24 <_dtoa_r+0x468> + 100dae4: 04c040b4 movhi r19,258 + 100dae8: 9cc63604 addi r19,r19,6360 + 100daec: 9080004c andi r2,r18,1 + 100daf0: 1005003a cmpeq r2,r2,zero + 100daf4: 1000081e bne r2,zero,100db18 <_dtoa_r+0x45c> + 100daf8: 99800017 ldw r6,0(r19) + 100dafc: 99c00117 ldw r7,4(r19) + 100db00: 880b883a mov r5,r17 + 100db04: 8009883a mov r4,r16 + 100db08: 1012ed00 call 1012ed0 <__muldf3> + 100db0c: 1021883a mov r16,r2 + 100db10: b5800044 addi r22,r22,1 + 100db14: 1823883a mov r17,r3 + 100db18: 9025d07a srai r18,r18,1 + 100db1c: 9cc00204 addi r19,r19,8 + 100db20: 903ff21e bne r18,zero,100daec <_dtoa_r+0x430> + 100db24: a80b883a mov r5,r21 + 100db28: a009883a mov r4,r20 + 100db2c: 880f883a mov r7,r17 + 100db30: 800d883a mov r6,r16 + 100db34: 10132940 call 1013294 <__divdf3> + 100db38: 1029883a mov r20,r2 + 100db3c: 182b883a mov r21,r3 + 100db40: d8c00c17 ldw r3,48(sp) + 100db44: 1805003a cmpeq r2,r3,zero + 100db48: 1000081e bne r2,zero,100db6c <_dtoa_r+0x4b0> + 100db4c: 0005883a mov r2,zero + 100db50: 00cffc34 movhi r3,16368 + 100db54: 180f883a mov r7,r3 + 100db58: a009883a mov r4,r20 + 100db5c: a80b883a mov r5,r21 + 100db60: 100d883a mov r6,r2 + 100db64: 101370c0 call 101370c <__ltdf2> + 100db68: 1003fe16 blt r2,zero,100eb64 <_dtoa_r+0x14a8> + 100db6c: b009883a mov r4,r22 + 100db70: 10137940 call 1013794 <__floatsidf> + 100db74: 180b883a mov r5,r3 + 100db78: 1009883a mov r4,r2 + 100db7c: a00d883a mov r6,r20 + 100db80: a80f883a mov r7,r21 + 100db84: 1012ed00 call 1012ed0 <__muldf3> + 100db88: 0011883a mov r8,zero + 100db8c: 02500734 movhi r9,16412 + 100db90: 1009883a mov r4,r2 + 100db94: 180b883a mov r5,r3 + 100db98: 480f883a mov r7,r9 + 100db9c: 400d883a mov r6,r8 + 100dba0: 1012e5c0 call 1012e5c <__adddf3> + 100dba4: d9000f17 ldw r4,60(sp) + 100dba8: 102d883a mov r22,r2 + 100dbac: 00bf3034 movhi r2,64704 + 100dbb0: 18b9883a add fp,r3,r2 + 100dbb4: e02f883a mov r23,fp + 100dbb8: 20028f1e bne r4,zero,100e5f8 <_dtoa_r+0xf3c> + 100dbbc: 0005883a mov r2,zero + 100dbc0: 00d00534 movhi r3,16404 + 100dbc4: a009883a mov r4,r20 + 100dbc8: a80b883a mov r5,r21 + 100dbcc: 180f883a mov r7,r3 + 100dbd0: 100d883a mov r6,r2 + 100dbd4: 1012ddc0 call 1012ddc <__subdf3> + 100dbd8: 1009883a mov r4,r2 + 100dbdc: e00f883a mov r7,fp + 100dbe0: 180b883a mov r5,r3 + 100dbe4: b00d883a mov r6,r22 + 100dbe8: 1025883a mov r18,r2 + 100dbec: 1827883a mov r19,r3 + 100dbf0: 10135fc0 call 10135fc <__gtdf2> + 100dbf4: 00834f16 blt zero,r2,100e934 <_dtoa_r+0x1278> + 100dbf8: e0e0003c xorhi r3,fp,32768 + 100dbfc: 9009883a mov r4,r18 + 100dc00: 980b883a mov r5,r19 + 100dc04: 180f883a mov r7,r3 + 100dc08: b00d883a mov r6,r22 + 100dc0c: 101370c0 call 101370c <__ltdf2> + 100dc10: 1000080e bge r2,zero,100dc34 <_dtoa_r+0x578> + 100dc14: 0027883a mov r19,zero + 100dc18: 0025883a mov r18,zero + 100dc1c: d8802617 ldw r2,152(sp) + 100dc20: df000517 ldw fp,20(sp) + 100dc24: d8000615 stw zero,24(sp) + 100dc28: 0084303a nor r2,zero,r2 + 100dc2c: d8800d15 stw r2,52(sp) + 100dc30: 00019b06 br 100e2a0 <_dtoa_r+0xbe4> + 100dc34: d9801217 ldw r6,72(sp) + 100dc38: d8801317 ldw r2,76(sp) + 100dc3c: 3029883a mov r20,r6 + 100dc40: 102b883a mov r21,r2 + 100dc44: d8c00217 ldw r3,8(sp) + 100dc48: 18008516 blt r3,zero,100de60 <_dtoa_r+0x7a4> + 100dc4c: d9000d17 ldw r4,52(sp) + 100dc50: 00800384 movi r2,14 + 100dc54: 11008216 blt r2,r4,100de60 <_dtoa_r+0x7a4> + 100dc58: 200490fa slli r2,r4,3 + 100dc5c: d9802617 ldw r6,152(sp) + 100dc60: 00c040b4 movhi r3,258 + 100dc64: 18c60404 addi r3,r3,6160 + 100dc68: 10c5883a add r2,r2,r3 + 100dc6c: 14800017 ldw r18,0(r2) + 100dc70: 14c00117 ldw r19,4(r2) + 100dc74: 30031e16 blt r6,zero,100e8f0 <_dtoa_r+0x1234> + 100dc78: d9000517 ldw r4,20(sp) + 100dc7c: d8c00f17 ldw r3,60(sp) + 100dc80: a823883a mov r17,r21 + 100dc84: a021883a mov r16,r20 + 100dc88: 192b883a add r21,r3,r4 + 100dc8c: 2039883a mov fp,r4 + 100dc90: 00000f06 br 100dcd0 <_dtoa_r+0x614> + 100dc94: 0005883a mov r2,zero + 100dc98: 00d00934 movhi r3,16420 + 100dc9c: 5009883a mov r4,r10 + 100dca0: 580b883a mov r5,r11 + 100dca4: 180f883a mov r7,r3 + 100dca8: 100d883a mov r6,r2 + 100dcac: 1012ed00 call 1012ed0 <__muldf3> + 100dcb0: 180b883a mov r5,r3 + 100dcb4: 000d883a mov r6,zero + 100dcb8: 000f883a mov r7,zero + 100dcbc: 1009883a mov r4,r2 + 100dcc0: 1021883a mov r16,r2 + 100dcc4: 1823883a mov r17,r3 + 100dcc8: 10135740 call 1013574 <__nedf2> + 100dccc: 10004526 beq r2,zero,100dde4 <_dtoa_r+0x728> + 100dcd0: 900d883a mov r6,r18 + 100dcd4: 980f883a mov r7,r19 + 100dcd8: 8009883a mov r4,r16 + 100dcdc: 880b883a mov r5,r17 + 100dce0: 10132940 call 1013294 <__divdf3> + 100dce4: 180b883a mov r5,r3 + 100dce8: 1009883a mov r4,r2 + 100dcec: 101388c0 call 101388c <__fixdfsi> + 100dcf0: 1009883a mov r4,r2 + 100dcf4: 1029883a mov r20,r2 + 100dcf8: 10137940 call 1013794 <__floatsidf> + 100dcfc: 180f883a mov r7,r3 + 100dd00: 9009883a mov r4,r18 + 100dd04: 980b883a mov r5,r19 + 100dd08: 100d883a mov r6,r2 + 100dd0c: 1012ed00 call 1012ed0 <__muldf3> + 100dd10: 180f883a mov r7,r3 + 100dd14: 880b883a mov r5,r17 + 100dd18: 8009883a mov r4,r16 + 100dd1c: 100d883a mov r6,r2 + 100dd20: 1012ddc0 call 1012ddc <__subdf3> + 100dd24: 1015883a mov r10,r2 + 100dd28: a0800c04 addi r2,r20,48 + 100dd2c: e0800005 stb r2,0(fp) + 100dd30: e7000044 addi fp,fp,1 + 100dd34: 1817883a mov r11,r3 + 100dd38: e57fd61e bne fp,r21,100dc94 <_dtoa_r+0x5d8> + 100dd3c: 500d883a mov r6,r10 + 100dd40: 180f883a mov r7,r3 + 100dd44: 5009883a mov r4,r10 + 100dd48: 180b883a mov r5,r3 + 100dd4c: 1012e5c0 call 1012e5c <__adddf3> + 100dd50: 100d883a mov r6,r2 + 100dd54: 9009883a mov r4,r18 + 100dd58: 980b883a mov r5,r19 + 100dd5c: 180f883a mov r7,r3 + 100dd60: 1021883a mov r16,r2 + 100dd64: 1823883a mov r17,r3 + 100dd68: 101370c0 call 101370c <__ltdf2> + 100dd6c: 10000816 blt r2,zero,100dd90 <_dtoa_r+0x6d4> + 100dd70: 980b883a mov r5,r19 + 100dd74: 800d883a mov r6,r16 + 100dd78: 880f883a mov r7,r17 + 100dd7c: 9009883a mov r4,r18 + 100dd80: 10134ec0 call 10134ec <__eqdf2> + 100dd84: 1000171e bne r2,zero,100dde4 <_dtoa_r+0x728> + 100dd88: a080004c andi r2,r20,1 + 100dd8c: 10001526 beq r2,zero,100dde4 <_dtoa_r+0x728> + 100dd90: d8800d17 ldw r2,52(sp) + 100dd94: d8800415 stw r2,16(sp) + 100dd98: e009883a mov r4,fp + 100dd9c: 213fffc4 addi r4,r4,-1 + 100dda0: 20c00007 ldb r3,0(r4) + 100dda4: 00800e44 movi r2,57 + 100dda8: 1880081e bne r3,r2,100ddcc <_dtoa_r+0x710> + 100ddac: d8800517 ldw r2,20(sp) + 100ddb0: 113ffa1e bne r2,r4,100dd9c <_dtoa_r+0x6e0> + 100ddb4: d8c00417 ldw r3,16(sp) + 100ddb8: d9800517 ldw r6,20(sp) + 100ddbc: 00800c04 movi r2,48 + 100ddc0: 18c00044 addi r3,r3,1 + 100ddc4: d8c00415 stw r3,16(sp) + 100ddc8: 30800005 stb r2,0(r6) + 100ddcc: 20800003 ldbu r2,0(r4) + 100ddd0: d8c00417 ldw r3,16(sp) + 100ddd4: 27000044 addi fp,r4,1 + 100ddd8: 10800044 addi r2,r2,1 + 100dddc: d8c00d15 stw r3,52(sp) + 100dde0: 20800005 stb r2,0(r4) + 100dde4: d9001617 ldw r4,88(sp) + 100dde8: d9400717 ldw r5,28(sp) + 100ddec: 100fe140 call 100fe14 <_Bfree> + 100ddf0: e0000005 stb zero,0(fp) + 100ddf4: d9800d17 ldw r6,52(sp) + 100ddf8: d8c02717 ldw r3,156(sp) + 100ddfc: d9002917 ldw r4,164(sp) + 100de00: 30800044 addi r2,r6,1 + 100de04: 18800015 stw r2,0(r3) + 100de08: 20029c26 beq r4,zero,100e87c <_dtoa_r+0x11c0> + 100de0c: d8c00517 ldw r3,20(sp) + 100de10: 27000015 stw fp,0(r4) + 100de14: 003e5d06 br 100d78c <_dtoa_r+0xd0> + 100de18: d9800d17 ldw r6,52(sp) + 100de1c: 00c040b4 movhi r3,258 + 100de20: 18c60404 addi r3,r3,6160 + 100de24: d9001217 ldw r4,72(sp) + 100de28: 300490fa slli r2,r6,3 + 100de2c: d9401317 ldw r5,76(sp) + 100de30: 10c5883a add r2,r2,r3 + 100de34: 12000017 ldw r8,0(r2) + 100de38: 12400117 ldw r9,4(r2) + 100de3c: 400d883a mov r6,r8 + 100de40: 480f883a mov r7,r9 + 100de44: 101370c0 call 101370c <__ltdf2> + 100de48: 1000030e bge r2,zero,100de58 <_dtoa_r+0x79c> + 100de4c: d8800d17 ldw r2,52(sp) + 100de50: 10bfffc4 addi r2,r2,-1 + 100de54: d8800d15 stw r2,52(sp) + 100de58: d8000c15 stw zero,48(sp) + 100de5c: 003ea806 br 100d900 <_dtoa_r+0x244> + 100de60: d9000b17 ldw r4,44(sp) + 100de64: 202cc03a cmpne r22,r4,zero + 100de68: b000c71e bne r22,zero,100e188 <_dtoa_r+0xacc> + 100de6c: dc001117 ldw r16,68(sp) + 100de70: dc801017 ldw r18,64(sp) + 100de74: 0027883a mov r19,zero + 100de78: 04000b0e bge zero,r16,100dea8 <_dtoa_r+0x7ec> + 100de7c: d8c00a17 ldw r3,40(sp) + 100de80: 00c0090e bge zero,r3,100dea8 <_dtoa_r+0x7ec> + 100de84: 8005883a mov r2,r16 + 100de88: 1c011316 blt r3,r16,100e2d8 <_dtoa_r+0xc1c> + 100de8c: d9000a17 ldw r4,40(sp) + 100de90: d9801117 ldw r6,68(sp) + 100de94: 80a1c83a sub r16,r16,r2 + 100de98: 2089c83a sub r4,r4,r2 + 100de9c: 308dc83a sub r6,r6,r2 + 100dea0: d9000a15 stw r4,40(sp) + 100dea4: d9801115 stw r6,68(sp) + 100dea8: d8801017 ldw r2,64(sp) + 100deac: 0080150e bge zero,r2,100df04 <_dtoa_r+0x848> + 100deb0: d8c00b17 ldw r3,44(sp) + 100deb4: 1805003a cmpeq r2,r3,zero + 100deb8: 1001c91e bne r2,zero,100e5e0 <_dtoa_r+0xf24> + 100debc: 04800e0e bge zero,r18,100def8 <_dtoa_r+0x83c> + 100dec0: d9001617 ldw r4,88(sp) + 100dec4: 980b883a mov r5,r19 + 100dec8: 900d883a mov r6,r18 + 100decc: 1010bc80 call 1010bc8 <__pow5mult> + 100ded0: d9001617 ldw r4,88(sp) + 100ded4: d9800717 ldw r6,28(sp) + 100ded8: 100b883a mov r5,r2 + 100dedc: 1027883a mov r19,r2 + 100dee0: 10108a40 call 10108a4 <__multiply> + 100dee4: d9001617 ldw r4,88(sp) + 100dee8: d9400717 ldw r5,28(sp) + 100deec: 1023883a mov r17,r2 + 100def0: 100fe140 call 100fe14 <_Bfree> + 100def4: dc400715 stw r17,28(sp) + 100def8: d9001017 ldw r4,64(sp) + 100defc: 248dc83a sub r6,r4,r18 + 100df00: 30010e1e bne r6,zero,100e33c <_dtoa_r+0xc80> + 100df04: d9001617 ldw r4,88(sp) + 100df08: 04400044 movi r17,1 + 100df0c: 880b883a mov r5,r17 + 100df10: 1010a8c0 call 1010a8c <__i2b> + 100df14: d9800917 ldw r6,36(sp) + 100df18: 1025883a mov r18,r2 + 100df1c: 0180040e bge zero,r6,100df30 <_dtoa_r+0x874> + 100df20: d9001617 ldw r4,88(sp) + 100df24: 100b883a mov r5,r2 + 100df28: 1010bc80 call 1010bc8 <__pow5mult> + 100df2c: 1025883a mov r18,r2 + 100df30: d8801717 ldw r2,92(sp) + 100df34: 8880f30e bge r17,r2,100e304 <_dtoa_r+0xc48> + 100df38: 0023883a mov r17,zero + 100df3c: d9800917 ldw r6,36(sp) + 100df40: 30019e1e bne r6,zero,100e5bc <_dtoa_r+0xf00> + 100df44: 00c00044 movi r3,1 + 100df48: d9000a17 ldw r4,40(sp) + 100df4c: 20c5883a add r2,r4,r3 + 100df50: 10c007cc andi r3,r2,31 + 100df54: 1800841e bne r3,zero,100e168 <_dtoa_r+0xaac> + 100df58: 00800704 movi r2,28 + 100df5c: d9000a17 ldw r4,40(sp) + 100df60: d9801117 ldw r6,68(sp) + 100df64: 80a1883a add r16,r16,r2 + 100df68: 2089883a add r4,r4,r2 + 100df6c: 308d883a add r6,r6,r2 + 100df70: d9000a15 stw r4,40(sp) + 100df74: d9801115 stw r6,68(sp) + 100df78: d8801117 ldw r2,68(sp) + 100df7c: 0080050e bge zero,r2,100df94 <_dtoa_r+0x8d8> + 100df80: d9400717 ldw r5,28(sp) + 100df84: d9001617 ldw r4,88(sp) + 100df88: 100d883a mov r6,r2 + 100df8c: 10107580 call 1010758 <__lshift> + 100df90: d8800715 stw r2,28(sp) + 100df94: d8c00a17 ldw r3,40(sp) + 100df98: 00c0050e bge zero,r3,100dfb0 <_dtoa_r+0x8f4> + 100df9c: d9001617 ldw r4,88(sp) + 100dfa0: 900b883a mov r5,r18 + 100dfa4: 180d883a mov r6,r3 + 100dfa8: 10107580 call 1010758 <__lshift> + 100dfac: 1025883a mov r18,r2 + 100dfb0: d9000c17 ldw r4,48(sp) + 100dfb4: 2005003a cmpeq r2,r4,zero + 100dfb8: 10016f26 beq r2,zero,100e578 <_dtoa_r+0xebc> + 100dfbc: d9000f17 ldw r4,60(sp) + 100dfc0: 0102170e bge zero,r4,100e820 <_dtoa_r+0x1164> + 100dfc4: d9800b17 ldw r6,44(sp) + 100dfc8: 3005003a cmpeq r2,r6,zero + 100dfcc: 1000881e bne r2,zero,100e1f0 <_dtoa_r+0xb34> + 100dfd0: 0400050e bge zero,r16,100dfe8 <_dtoa_r+0x92c> + 100dfd4: d9001617 ldw r4,88(sp) + 100dfd8: 980b883a mov r5,r19 + 100dfdc: 800d883a mov r6,r16 + 100dfe0: 10107580 call 1010758 <__lshift> + 100dfe4: 1027883a mov r19,r2 + 100dfe8: 8804c03a cmpne r2,r17,zero + 100dfec: 1002541e bne r2,zero,100e940 <_dtoa_r+0x1284> + 100dff0: 980b883a mov r5,r19 + 100dff4: dd800517 ldw r22,20(sp) + 100dff8: dcc00615 stw r19,24(sp) + 100dffc: a700004c andi fp,r20,1 + 100e000: 2827883a mov r19,r5 + 100e004: d9000717 ldw r4,28(sp) + 100e008: 900b883a mov r5,r18 + 100e00c: 100d4a40 call 100d4a4 + 100e010: d9000717 ldw r4,28(sp) + 100e014: d9400617 ldw r5,24(sp) + 100e018: 1023883a mov r17,r2 + 100e01c: 8dc00c04 addi r23,r17,48 + 100e020: 100ff700 call 100ff70 <__mcmp> + 100e024: d9001617 ldw r4,88(sp) + 100e028: 900b883a mov r5,r18 + 100e02c: 980d883a mov r6,r19 + 100e030: 1029883a mov r20,r2 + 100e034: 10105cc0 call 10105cc <__mdiff> + 100e038: 102b883a mov r21,r2 + 100e03c: 10800317 ldw r2,12(r2) + 100e040: 1001281e bne r2,zero,100e4e4 <_dtoa_r+0xe28> + 100e044: d9000717 ldw r4,28(sp) + 100e048: a80b883a mov r5,r21 + 100e04c: 100ff700 call 100ff70 <__mcmp> + 100e050: d9001617 ldw r4,88(sp) + 100e054: 1021883a mov r16,r2 + 100e058: a80b883a mov r5,r21 + 100e05c: 100fe140 call 100fe14 <_Bfree> + 100e060: 8000041e bne r16,zero,100e074 <_dtoa_r+0x9b8> + 100e064: d8801717 ldw r2,92(sp) + 100e068: 1000021e bne r2,zero,100e074 <_dtoa_r+0x9b8> + 100e06c: e004c03a cmpne r2,fp,zero + 100e070: 10011726 beq r2,zero,100e4d0 <_dtoa_r+0xe14> + 100e074: a0010616 blt r20,zero,100e490 <_dtoa_r+0xdd4> + 100e078: a000041e bne r20,zero,100e08c <_dtoa_r+0x9d0> + 100e07c: d8c01717 ldw r3,92(sp) + 100e080: 1800021e bne r3,zero,100e08c <_dtoa_r+0x9d0> + 100e084: e004c03a cmpne r2,fp,zero + 100e088: 10010126 beq r2,zero,100e490 <_dtoa_r+0xdd4> + 100e08c: 04023d16 blt zero,r16,100e984 <_dtoa_r+0x12c8> + 100e090: b5c00005 stb r23,0(r22) + 100e094: d9800517 ldw r6,20(sp) + 100e098: d9000f17 ldw r4,60(sp) + 100e09c: b5800044 addi r22,r22,1 + 100e0a0: 3105883a add r2,r6,r4 + 100e0a4: b0806526 beq r22,r2,100e23c <_dtoa_r+0xb80> + 100e0a8: d9400717 ldw r5,28(sp) + 100e0ac: d9001617 ldw r4,88(sp) + 100e0b0: 01800284 movi r6,10 + 100e0b4: 000f883a mov r7,zero + 100e0b8: 1010ac80 call 1010ac8 <__multadd> + 100e0bc: d8800715 stw r2,28(sp) + 100e0c0: d8800617 ldw r2,24(sp) + 100e0c4: 14c10c26 beq r2,r19,100e4f8 <_dtoa_r+0xe3c> + 100e0c8: d9400617 ldw r5,24(sp) + 100e0cc: d9001617 ldw r4,88(sp) + 100e0d0: 01800284 movi r6,10 + 100e0d4: 000f883a mov r7,zero + 100e0d8: 1010ac80 call 1010ac8 <__multadd> + 100e0dc: d9001617 ldw r4,88(sp) + 100e0e0: 980b883a mov r5,r19 + 100e0e4: 01800284 movi r6,10 + 100e0e8: 000f883a mov r7,zero + 100e0ec: d8800615 stw r2,24(sp) + 100e0f0: 1010ac80 call 1010ac8 <__multadd> + 100e0f4: 1027883a mov r19,r2 + 100e0f8: 003fc206 br 100e004 <_dtoa_r+0x948> + 100e0fc: 2445c83a sub r2,r4,r17 + 100e100: a088983a sll r4,r20,r2 + 100e104: 003e4b06 br 100da34 <_dtoa_r+0x378> + 100e108: 01bfffc4 movi r6,-1 + 100e10c: 00800044 movi r2,1 + 100e110: d9800e15 stw r6,56(sp) + 100e114: d9800f15 stw r6,60(sp) + 100e118: d8800b15 stw r2,44(sp) + 100e11c: d8c01617 ldw r3,88(sp) + 100e120: 008005c4 movi r2,23 + 100e124: 18001115 stw zero,68(r3) + 100e128: 1580082e bgeu r2,r22,100e14c <_dtoa_r+0xa90> + 100e12c: 00c00104 movi r3,4 + 100e130: 0009883a mov r4,zero + 100e134: 18c7883a add r3,r3,r3 + 100e138: 18800504 addi r2,r3,20 + 100e13c: 21000044 addi r4,r4,1 + 100e140: b0bffc2e bgeu r22,r2,100e134 <_dtoa_r+0xa78> + 100e144: d9801617 ldw r6,88(sp) + 100e148: 31001115 stw r4,68(r6) + 100e14c: dc000f17 ldw r16,60(sp) + 100e150: 003e4b06 br 100da80 <_dtoa_r+0x3c4> + 100e154: d9801717 ldw r6,92(sp) + 100e158: 0023883a mov r17,zero + 100e15c: 31bfff04 addi r6,r6,-4 + 100e160: d9801715 stw r6,92(sp) + 100e164: 003df806 br 100d948 <_dtoa_r+0x28c> + 100e168: 00800804 movi r2,32 + 100e16c: 10c9c83a sub r4,r2,r3 + 100e170: 00c00104 movi r3,4 + 100e174: 19005a16 blt r3,r4,100e2e0 <_dtoa_r+0xc24> + 100e178: 008000c4 movi r2,3 + 100e17c: 113f7e16 blt r2,r4,100df78 <_dtoa_r+0x8bc> + 100e180: 20800704 addi r2,r4,28 + 100e184: 003f7506 br 100df5c <_dtoa_r+0x8a0> + 100e188: d9801717 ldw r6,92(sp) + 100e18c: 00800044 movi r2,1 + 100e190: 1180a10e bge r2,r6,100e418 <_dtoa_r+0xd5c> + 100e194: d9800f17 ldw r6,60(sp) + 100e198: d8c01017 ldw r3,64(sp) + 100e19c: 30bfffc4 addi r2,r6,-1 + 100e1a0: 1881c616 blt r3,r2,100e8bc <_dtoa_r+0x1200> + 100e1a4: 18a5c83a sub r18,r3,r2 + 100e1a8: d8800f17 ldw r2,60(sp) + 100e1ac: 10026216 blt r2,zero,100eb38 <_dtoa_r+0x147c> + 100e1b0: dc001117 ldw r16,68(sp) + 100e1b4: 1007883a mov r3,r2 + 100e1b8: d9800a17 ldw r6,40(sp) + 100e1bc: d8801117 ldw r2,68(sp) + 100e1c0: d9001617 ldw r4,88(sp) + 100e1c4: 30cd883a add r6,r6,r3 + 100e1c8: 10c5883a add r2,r2,r3 + 100e1cc: 01400044 movi r5,1 + 100e1d0: d9800a15 stw r6,40(sp) + 100e1d4: d8801115 stw r2,68(sp) + 100e1d8: 1010a8c0 call 1010a8c <__i2b> + 100e1dc: 1027883a mov r19,r2 + 100e1e0: 003f2506 br 100de78 <_dtoa_r+0x7bc> + 100e1e4: 00c040b4 movhi r3,258 + 100e1e8: 18c54604 addi r3,r3,5400 + 100e1ec: 003d6706 br 100d78c <_dtoa_r+0xd0> + 100e1f0: dd800517 ldw r22,20(sp) + 100e1f4: 04000044 movi r16,1 + 100e1f8: 00000706 br 100e218 <_dtoa_r+0xb5c> + 100e1fc: d9400717 ldw r5,28(sp) + 100e200: d9001617 ldw r4,88(sp) + 100e204: 01800284 movi r6,10 + 100e208: 000f883a mov r7,zero + 100e20c: 1010ac80 call 1010ac8 <__multadd> + 100e210: d8800715 stw r2,28(sp) + 100e214: 84000044 addi r16,r16,1 + 100e218: d9000717 ldw r4,28(sp) + 100e21c: 900b883a mov r5,r18 + 100e220: 100d4a40 call 100d4a4 + 100e224: 15c00c04 addi r23,r2,48 + 100e228: b5c00005 stb r23,0(r22) + 100e22c: d8c00f17 ldw r3,60(sp) + 100e230: b5800044 addi r22,r22,1 + 100e234: 80fff116 blt r16,r3,100e1fc <_dtoa_r+0xb40> + 100e238: d8000615 stw zero,24(sp) + 100e23c: d9400717 ldw r5,28(sp) + 100e240: d9001617 ldw r4,88(sp) + 100e244: 01800044 movi r6,1 + 100e248: 10107580 call 1010758 <__lshift> + 100e24c: 1009883a mov r4,r2 + 100e250: 900b883a mov r5,r18 + 100e254: d8800715 stw r2,28(sp) + 100e258: 100ff700 call 100ff70 <__mcmp> + 100e25c: 00803c0e bge zero,r2,100e350 <_dtoa_r+0xc94> + 100e260: b009883a mov r4,r22 + 100e264: 213fffc4 addi r4,r4,-1 + 100e268: 21400003 ldbu r5,0(r4) + 100e26c: 00800e44 movi r2,57 + 100e270: 28c03fcc andi r3,r5,255 + 100e274: 18c0201c xori r3,r3,128 + 100e278: 18ffe004 addi r3,r3,-128 + 100e27c: 1881981e bne r3,r2,100e8e0 <_dtoa_r+0x1224> + 100e280: d9800517 ldw r6,20(sp) + 100e284: 21bff71e bne r4,r6,100e264 <_dtoa_r+0xba8> + 100e288: d8800d17 ldw r2,52(sp) + 100e28c: 37000044 addi fp,r6,1 + 100e290: 10800044 addi r2,r2,1 + 100e294: d8800d15 stw r2,52(sp) + 100e298: 00800c44 movi r2,49 + 100e29c: 30800005 stb r2,0(r6) + 100e2a0: d9001617 ldw r4,88(sp) + 100e2a4: 900b883a mov r5,r18 + 100e2a8: 100fe140 call 100fe14 <_Bfree> + 100e2ac: 983ecd26 beq r19,zero,100dde4 <_dtoa_r+0x728> + 100e2b0: d8c00617 ldw r3,24(sp) + 100e2b4: 18000426 beq r3,zero,100e2c8 <_dtoa_r+0xc0c> + 100e2b8: 1cc00326 beq r3,r19,100e2c8 <_dtoa_r+0xc0c> + 100e2bc: d9001617 ldw r4,88(sp) + 100e2c0: 180b883a mov r5,r3 + 100e2c4: 100fe140 call 100fe14 <_Bfree> + 100e2c8: d9001617 ldw r4,88(sp) + 100e2cc: 980b883a mov r5,r19 + 100e2d0: 100fe140 call 100fe14 <_Bfree> + 100e2d4: 003ec306 br 100dde4 <_dtoa_r+0x728> + 100e2d8: 1805883a mov r2,r3 + 100e2dc: 003eeb06 br 100de8c <_dtoa_r+0x7d0> + 100e2e0: d9800a17 ldw r6,40(sp) + 100e2e4: d8c01117 ldw r3,68(sp) + 100e2e8: 20bfff04 addi r2,r4,-4 + 100e2ec: 308d883a add r6,r6,r2 + 100e2f0: 1887883a add r3,r3,r2 + 100e2f4: 80a1883a add r16,r16,r2 + 100e2f8: d9800a15 stw r6,40(sp) + 100e2fc: d8c01115 stw r3,68(sp) + 100e300: 003f1d06 br 100df78 <_dtoa_r+0x8bc> + 100e304: a03f0c1e bne r20,zero,100df38 <_dtoa_r+0x87c> + 100e308: 00800434 movhi r2,16 + 100e30c: 10bfffc4 addi r2,r2,-1 + 100e310: a884703a and r2,r21,r2 + 100e314: 103f081e bne r2,zero,100df38 <_dtoa_r+0x87c> + 100e318: a89ffc2c andhi r2,r21,32752 + 100e31c: 103f0626 beq r2,zero,100df38 <_dtoa_r+0x87c> + 100e320: d8c01117 ldw r3,68(sp) + 100e324: d9000a17 ldw r4,40(sp) + 100e328: 18c00044 addi r3,r3,1 + 100e32c: 21000044 addi r4,r4,1 + 100e330: d8c01115 stw r3,68(sp) + 100e334: d9000a15 stw r4,40(sp) + 100e338: 003f0006 br 100df3c <_dtoa_r+0x880> + 100e33c: d9400717 ldw r5,28(sp) + 100e340: d9001617 ldw r4,88(sp) + 100e344: 1010bc80 call 1010bc8 <__pow5mult> + 100e348: d8800715 stw r2,28(sp) + 100e34c: 003eed06 br 100df04 <_dtoa_r+0x848> + 100e350: 1000021e bne r2,zero,100e35c <_dtoa_r+0xca0> + 100e354: b880004c andi r2,r23,1 + 100e358: 103fc11e bne r2,zero,100e260 <_dtoa_r+0xba4> + 100e35c: b5bfffc4 addi r22,r22,-1 + 100e360: b0c00007 ldb r3,0(r22) + 100e364: 00800c04 movi r2,48 + 100e368: 18bffc26 beq r3,r2,100e35c <_dtoa_r+0xca0> + 100e36c: b7000044 addi fp,r22,1 + 100e370: 003fcb06 br 100e2a0 <_dtoa_r+0xbe4> + 100e374: d9800d17 ldw r6,52(sp) + 100e378: 018fc83a sub r7,zero,r6 + 100e37c: 3801f726 beq r7,zero,100eb5c <_dtoa_r+0x14a0> + 100e380: 398003cc andi r6,r7,15 + 100e384: 300c90fa slli r6,r6,3 + 100e388: 014040b4 movhi r5,258 + 100e38c: 29460404 addi r5,r5,6160 + 100e390: d9001217 ldw r4,72(sp) + 100e394: 314d883a add r6,r6,r5 + 100e398: 30c00117 ldw r3,4(r6) + 100e39c: 30800017 ldw r2,0(r6) + 100e3a0: d9401317 ldw r5,76(sp) + 100e3a4: 3821d13a srai r16,r7,4 + 100e3a8: 100d883a mov r6,r2 + 100e3ac: 180f883a mov r7,r3 + 100e3b0: 1012ed00 call 1012ed0 <__muldf3> + 100e3b4: 1011883a mov r8,r2 + 100e3b8: 1813883a mov r9,r3 + 100e3bc: 1029883a mov r20,r2 + 100e3c0: 182b883a mov r21,r3 + 100e3c4: 8001e526 beq r16,zero,100eb5c <_dtoa_r+0x14a0> + 100e3c8: 05800084 movi r22,2 + 100e3cc: 044040b4 movhi r17,258 + 100e3d0: 8c463604 addi r17,r17,6360 + 100e3d4: 8080004c andi r2,r16,1 + 100e3d8: 1005003a cmpeq r2,r2,zero + 100e3dc: 1000081e bne r2,zero,100e400 <_dtoa_r+0xd44> + 100e3e0: 89800017 ldw r6,0(r17) + 100e3e4: 89c00117 ldw r7,4(r17) + 100e3e8: 480b883a mov r5,r9 + 100e3ec: 4009883a mov r4,r8 + 100e3f0: 1012ed00 call 1012ed0 <__muldf3> + 100e3f4: 1011883a mov r8,r2 + 100e3f8: b5800044 addi r22,r22,1 + 100e3fc: 1813883a mov r9,r3 + 100e400: 8021d07a srai r16,r16,1 + 100e404: 8c400204 addi r17,r17,8 + 100e408: 803ff21e bne r16,zero,100e3d4 <_dtoa_r+0xd18> + 100e40c: 4029883a mov r20,r8 + 100e410: 482b883a mov r21,r9 + 100e414: 003dca06 br 100db40 <_dtoa_r+0x484> + 100e418: d9000817 ldw r4,32(sp) + 100e41c: 2005003a cmpeq r2,r4,zero + 100e420: 1001f61e bne r2,zero,100ebfc <_dtoa_r+0x1540> + 100e424: dc001117 ldw r16,68(sp) + 100e428: dc801017 ldw r18,64(sp) + 100e42c: 18c10cc4 addi r3,r3,1075 + 100e430: 003f6106 br 100e1b8 <_dtoa_r+0xafc> + 100e434: d8000b15 stw zero,44(sp) + 100e438: d9802617 ldw r6,152(sp) + 100e43c: d8c00d17 ldw r3,52(sp) + 100e440: 30800044 addi r2,r6,1 + 100e444: 18ad883a add r22,r3,r2 + 100e448: b13fffc4 addi r4,r22,-1 + 100e44c: d9000e15 stw r4,56(sp) + 100e450: 0581f60e bge zero,r22,100ec2c <_dtoa_r+0x1570> + 100e454: dd800f15 stw r22,60(sp) + 100e458: 003f3006 br 100e11c <_dtoa_r+0xa60> + 100e45c: d8000b15 stw zero,44(sp) + 100e460: d9002617 ldw r4,152(sp) + 100e464: 0101eb0e bge zero,r4,100ec14 <_dtoa_r+0x1558> + 100e468: 202d883a mov r22,r4 + 100e46c: d9000e15 stw r4,56(sp) + 100e470: d9000f15 stw r4,60(sp) + 100e474: 003f2906 br 100e11c <_dtoa_r+0xa60> + 100e478: 01800044 movi r6,1 + 100e47c: d9800b15 stw r6,44(sp) + 100e480: 003ff706 br 100e460 <_dtoa_r+0xda4> + 100e484: 01000044 movi r4,1 + 100e488: d9000b15 stw r4,44(sp) + 100e48c: 003fea06 br 100e438 <_dtoa_r+0xd7c> + 100e490: 04000c0e bge zero,r16,100e4c4 <_dtoa_r+0xe08> + 100e494: d9400717 ldw r5,28(sp) + 100e498: d9001617 ldw r4,88(sp) + 100e49c: 01800044 movi r6,1 + 100e4a0: 10107580 call 1010758 <__lshift> + 100e4a4: 1009883a mov r4,r2 + 100e4a8: 900b883a mov r5,r18 + 100e4ac: d8800715 stw r2,28(sp) + 100e4b0: 100ff700 call 100ff70 <__mcmp> + 100e4b4: 0081e00e bge zero,r2,100ec38 <_dtoa_r+0x157c> + 100e4b8: bdc00044 addi r23,r23,1 + 100e4bc: 00800e84 movi r2,58 + 100e4c0: b881a226 beq r23,r2,100eb4c <_dtoa_r+0x1490> + 100e4c4: b7000044 addi fp,r22,1 + 100e4c8: b5c00005 stb r23,0(r22) + 100e4cc: 003f7406 br 100e2a0 <_dtoa_r+0xbe4> + 100e4d0: 00800e44 movi r2,57 + 100e4d4: b8819d26 beq r23,r2,100eb4c <_dtoa_r+0x1490> + 100e4d8: 053ffa0e bge zero,r20,100e4c4 <_dtoa_r+0xe08> + 100e4dc: 8dc00c44 addi r23,r17,49 + 100e4e0: 003ff806 br 100e4c4 <_dtoa_r+0xe08> + 100e4e4: d9001617 ldw r4,88(sp) + 100e4e8: a80b883a mov r5,r21 + 100e4ec: 04000044 movi r16,1 + 100e4f0: 100fe140 call 100fe14 <_Bfree> + 100e4f4: 003edf06 br 100e074 <_dtoa_r+0x9b8> + 100e4f8: d9001617 ldw r4,88(sp) + 100e4fc: 980b883a mov r5,r19 + 100e500: 01800284 movi r6,10 + 100e504: 000f883a mov r7,zero + 100e508: 1010ac80 call 1010ac8 <__multadd> + 100e50c: 1027883a mov r19,r2 + 100e510: d8800615 stw r2,24(sp) + 100e514: 003ebb06 br 100e004 <_dtoa_r+0x948> + 100e518: d9801117 ldw r6,68(sp) + 100e51c: d8800d17 ldw r2,52(sp) + 100e520: d8000915 stw zero,36(sp) + 100e524: 308dc83a sub r6,r6,r2 + 100e528: 0087c83a sub r3,zero,r2 + 100e52c: d9801115 stw r6,68(sp) + 100e530: d8c01015 stw r3,64(sp) + 100e534: 003cfe06 br 100d930 <_dtoa_r+0x274> + 100e538: 018dc83a sub r6,zero,r6 + 100e53c: d9801115 stw r6,68(sp) + 100e540: d8000a15 stw zero,40(sp) + 100e544: 003cf306 br 100d914 <_dtoa_r+0x258> + 100e548: d9000d17 ldw r4,52(sp) + 100e54c: 10137940 call 1013794 <__floatsidf> + 100e550: 880b883a mov r5,r17 + 100e554: 8009883a mov r4,r16 + 100e558: 180f883a mov r7,r3 + 100e55c: 100d883a mov r6,r2 + 100e560: 10135740 call 1013574 <__nedf2> + 100e564: 103ce126 beq r2,zero,100d8ec <_dtoa_r+0x230> + 100e568: d9800d17 ldw r6,52(sp) + 100e56c: 31bfffc4 addi r6,r6,-1 + 100e570: d9800d15 stw r6,52(sp) + 100e574: 003cdd06 br 100d8ec <_dtoa_r+0x230> + 100e578: d9000717 ldw r4,28(sp) + 100e57c: 900b883a mov r5,r18 + 100e580: 100ff700 call 100ff70 <__mcmp> + 100e584: 103e8d0e bge r2,zero,100dfbc <_dtoa_r+0x900> + 100e588: d9400717 ldw r5,28(sp) + 100e58c: d9001617 ldw r4,88(sp) + 100e590: 01800284 movi r6,10 + 100e594: 000f883a mov r7,zero + 100e598: 1010ac80 call 1010ac8 <__multadd> + 100e59c: d9800d17 ldw r6,52(sp) + 100e5a0: d8800715 stw r2,28(sp) + 100e5a4: 31bfffc4 addi r6,r6,-1 + 100e5a8: d9800d15 stw r6,52(sp) + 100e5ac: b001a71e bne r22,zero,100ec4c <_dtoa_r+0x1590> + 100e5b0: d8800e17 ldw r2,56(sp) + 100e5b4: d8800f15 stw r2,60(sp) + 100e5b8: 003e8006 br 100dfbc <_dtoa_r+0x900> + 100e5bc: 90800417 ldw r2,16(r18) + 100e5c0: 1085883a add r2,r2,r2 + 100e5c4: 1085883a add r2,r2,r2 + 100e5c8: 1485883a add r2,r2,r18 + 100e5cc: 11000417 ldw r4,16(r2) + 100e5d0: 100fe3c0 call 100fe3c <__hi0bits> + 100e5d4: 00c00804 movi r3,32 + 100e5d8: 1887c83a sub r3,r3,r2 + 100e5dc: 003e5a06 br 100df48 <_dtoa_r+0x88c> + 100e5e0: d9400717 ldw r5,28(sp) + 100e5e4: d9801017 ldw r6,64(sp) + 100e5e8: d9001617 ldw r4,88(sp) + 100e5ec: 1010bc80 call 1010bc8 <__pow5mult> + 100e5f0: d8800715 stw r2,28(sp) + 100e5f4: 003e4306 br 100df04 <_dtoa_r+0x848> + 100e5f8: d9800f17 ldw r6,60(sp) + 100e5fc: d8800d17 ldw r2,52(sp) + 100e600: d9800315 stw r6,12(sp) + 100e604: d8800415 stw r2,16(sp) + 100e608: d8c00b17 ldw r3,44(sp) + 100e60c: 1805003a cmpeq r2,r3,zero + 100e610: 1000e21e bne r2,zero,100e99c <_dtoa_r+0x12e0> + 100e614: d9000317 ldw r4,12(sp) + 100e618: 0005883a mov r2,zero + 100e61c: 00cff834 movhi r3,16352 + 100e620: 200c90fa slli r6,r4,3 + 100e624: 010040b4 movhi r4,258 + 100e628: 21060404 addi r4,r4,6160 + 100e62c: 180b883a mov r5,r3 + 100e630: 310d883a add r6,r6,r4 + 100e634: 327fff17 ldw r9,-4(r6) + 100e638: 323ffe17 ldw r8,-8(r6) + 100e63c: 1009883a mov r4,r2 + 100e640: 480f883a mov r7,r9 + 100e644: 400d883a mov r6,r8 + 100e648: 10132940 call 1013294 <__divdf3> + 100e64c: 180b883a mov r5,r3 + 100e650: b00d883a mov r6,r22 + 100e654: b80f883a mov r7,r23 + 100e658: 1009883a mov r4,r2 + 100e65c: 1012ddc0 call 1012ddc <__subdf3> + 100e660: a80b883a mov r5,r21 + 100e664: a009883a mov r4,r20 + 100e668: d8c01915 stw r3,100(sp) + 100e66c: d8801815 stw r2,96(sp) + 100e670: 101388c0 call 101388c <__fixdfsi> + 100e674: 1009883a mov r4,r2 + 100e678: 1027883a mov r19,r2 + 100e67c: 10137940 call 1013794 <__floatsidf> + 100e680: a80b883a mov r5,r21 + 100e684: a009883a mov r4,r20 + 100e688: 180f883a mov r7,r3 + 100e68c: 100d883a mov r6,r2 + 100e690: 1012ddc0 call 1012ddc <__subdf3> + 100e694: d9801817 ldw r6,96(sp) + 100e698: 1823883a mov r17,r3 + 100e69c: d8801415 stw r2,80(sp) + 100e6a0: 302d883a mov r22,r6 + 100e6a4: d9800517 ldw r6,20(sp) + 100e6a8: 9cc00c04 addi r19,r19,48 + 100e6ac: dc401515 stw r17,84(sp) + 100e6b0: d8c01917 ldw r3,100(sp) + 100e6b4: 34c00005 stb r19,0(r6) + 100e6b8: d8800517 ldw r2,20(sp) + 100e6bc: d9401917 ldw r5,100(sp) + 100e6c0: d9801417 ldw r6,80(sp) + 100e6c4: b009883a mov r4,r22 + 100e6c8: 880f883a mov r7,r17 + 100e6cc: 182f883a mov r23,r3 + 100e6d0: 17000044 addi fp,r2,1 + 100e6d4: 10135fc0 call 10135fc <__gtdf2> + 100e6d8: 00804e16 blt zero,r2,100e814 <_dtoa_r+0x1158> + 100e6dc: d9801417 ldw r6,80(sp) + 100e6e0: 0005883a mov r2,zero + 100e6e4: 00cffc34 movhi r3,16368 + 100e6e8: 180b883a mov r5,r3 + 100e6ec: 880f883a mov r7,r17 + 100e6f0: 1009883a mov r4,r2 + 100e6f4: 1012ddc0 call 1012ddc <__subdf3> + 100e6f8: d9401917 ldw r5,100(sp) + 100e6fc: 180f883a mov r7,r3 + 100e700: b009883a mov r4,r22 + 100e704: 100d883a mov r6,r2 + 100e708: 10135fc0 call 10135fc <__gtdf2> + 100e70c: 00bda216 blt zero,r2,100dd98 <_dtoa_r+0x6dc> + 100e710: d8c00317 ldw r3,12(sp) + 100e714: 00800044 movi r2,1 + 100e718: 10c01216 blt r2,r3,100e764 <_dtoa_r+0x10a8> + 100e71c: 003d4506 br 100dc34 <_dtoa_r+0x578> + 100e720: d9801417 ldw r6,80(sp) + 100e724: 0005883a mov r2,zero + 100e728: 00cffc34 movhi r3,16368 + 100e72c: 180b883a mov r5,r3 + 100e730: 880f883a mov r7,r17 + 100e734: 1009883a mov r4,r2 + 100e738: 1012ddc0 call 1012ddc <__subdf3> + 100e73c: d9c01b17 ldw r7,108(sp) + 100e740: 180b883a mov r5,r3 + 100e744: 1009883a mov r4,r2 + 100e748: b00d883a mov r6,r22 + 100e74c: 101370c0 call 101370c <__ltdf2> + 100e750: 103d9116 blt r2,zero,100dd98 <_dtoa_r+0x6dc> + 100e754: d9800517 ldw r6,20(sp) + 100e758: d9000317 ldw r4,12(sp) + 100e75c: 3105883a add r2,r6,r4 + 100e760: e0bd3426 beq fp,r2,100dc34 <_dtoa_r+0x578> + 100e764: 04500934 movhi r17,16420 + 100e768: 0021883a mov r16,zero + 100e76c: b80b883a mov r5,r23 + 100e770: b009883a mov r4,r22 + 100e774: 800d883a mov r6,r16 + 100e778: 880f883a mov r7,r17 + 100e77c: 1012ed00 call 1012ed0 <__muldf3> + 100e780: d9401517 ldw r5,84(sp) + 100e784: d9001417 ldw r4,80(sp) + 100e788: 880f883a mov r7,r17 + 100e78c: 000d883a mov r6,zero + 100e790: d8801a15 stw r2,104(sp) + 100e794: d8c01b15 stw r3,108(sp) + 100e798: 1012ed00 call 1012ed0 <__muldf3> + 100e79c: 180b883a mov r5,r3 + 100e7a0: 1009883a mov r4,r2 + 100e7a4: 1823883a mov r17,r3 + 100e7a8: 1021883a mov r16,r2 + 100e7ac: 101388c0 call 101388c <__fixdfsi> + 100e7b0: 1009883a mov r4,r2 + 100e7b4: 102b883a mov r21,r2 + 100e7b8: 10137940 call 1013794 <__floatsidf> + 100e7bc: 880b883a mov r5,r17 + 100e7c0: 8009883a mov r4,r16 + 100e7c4: 180f883a mov r7,r3 + 100e7c8: 100d883a mov r6,r2 + 100e7cc: 1012ddc0 call 1012ddc <__subdf3> + 100e7d0: 1021883a mov r16,r2 + 100e7d4: d9001b17 ldw r4,108(sp) + 100e7d8: 1823883a mov r17,r3 + 100e7dc: dc001415 stw r16,80(sp) + 100e7e0: ad400c04 addi r21,r21,48 + 100e7e4: dc401515 stw r17,84(sp) + 100e7e8: d8801a17 ldw r2,104(sp) + 100e7ec: e5400005 stb r21,0(fp) + 100e7f0: 202f883a mov r23,r4 + 100e7f4: d9c01b17 ldw r7,108(sp) + 100e7f8: d9001417 ldw r4,80(sp) + 100e7fc: 880b883a mov r5,r17 + 100e800: 100d883a mov r6,r2 + 100e804: 102d883a mov r22,r2 + 100e808: e7000044 addi fp,fp,1 + 100e80c: 101370c0 call 101370c <__ltdf2> + 100e810: 103fc30e bge r2,zero,100e720 <_dtoa_r+0x1064> + 100e814: d9000417 ldw r4,16(sp) + 100e818: d9000d15 stw r4,52(sp) + 100e81c: 003d7106 br 100dde4 <_dtoa_r+0x728> + 100e820: d9801717 ldw r6,92(sp) + 100e824: 00800084 movi r2,2 + 100e828: 11bde60e bge r2,r6,100dfc4 <_dtoa_r+0x908> + 100e82c: 203cfb1e bne r4,zero,100dc1c <_dtoa_r+0x560> + 100e830: d9001617 ldw r4,88(sp) + 100e834: 900b883a mov r5,r18 + 100e838: 01800144 movi r6,5 + 100e83c: 000f883a mov r7,zero + 100e840: 1010ac80 call 1010ac8 <__multadd> + 100e844: d9000717 ldw r4,28(sp) + 100e848: 100b883a mov r5,r2 + 100e84c: 1025883a mov r18,r2 + 100e850: 100ff700 call 100ff70 <__mcmp> + 100e854: 00bcf10e bge zero,r2,100dc1c <_dtoa_r+0x560> + 100e858: d8c00d17 ldw r3,52(sp) + 100e85c: d9000517 ldw r4,20(sp) + 100e860: d8000615 stw zero,24(sp) + 100e864: 18c00044 addi r3,r3,1 + 100e868: d8c00d15 stw r3,52(sp) + 100e86c: 00800c44 movi r2,49 + 100e870: 27000044 addi fp,r4,1 + 100e874: 20800005 stb r2,0(r4) + 100e878: 003e8906 br 100e2a0 <_dtoa_r+0xbe4> + 100e87c: d8c00517 ldw r3,20(sp) + 100e880: 003bc206 br 100d78c <_dtoa_r+0xd0> + 100e884: 018040b4 movhi r6,258 + 100e888: 31863604 addi r6,r6,6360 + 100e88c: 30c00917 ldw r3,36(r6) + 100e890: 30800817 ldw r2,32(r6) + 100e894: d9001217 ldw r4,72(sp) + 100e898: d9401317 ldw r5,76(sp) + 100e89c: 180f883a mov r7,r3 + 100e8a0: 100d883a mov r6,r2 + 100e8a4: 10132940 call 1013294 <__divdf3> + 100e8a8: 948003cc andi r18,r18,15 + 100e8ac: 058000c4 movi r22,3 + 100e8b0: 1029883a mov r20,r2 + 100e8b4: 182b883a mov r21,r3 + 100e8b8: 003c8906 br 100dae0 <_dtoa_r+0x424> + 100e8bc: d9001017 ldw r4,64(sp) + 100e8c0: d9800917 ldw r6,36(sp) + 100e8c4: 0025883a mov r18,zero + 100e8c8: 1105c83a sub r2,r2,r4 + 100e8cc: 2089883a add r4,r4,r2 + 100e8d0: 308d883a add r6,r6,r2 + 100e8d4: d9001015 stw r4,64(sp) + 100e8d8: d9800915 stw r6,36(sp) + 100e8dc: 003e3206 br 100e1a8 <_dtoa_r+0xaec> + 100e8e0: 28800044 addi r2,r5,1 + 100e8e4: 27000044 addi fp,r4,1 + 100e8e8: 20800005 stb r2,0(r4) + 100e8ec: 003e6c06 br 100e2a0 <_dtoa_r+0xbe4> + 100e8f0: d8800f17 ldw r2,60(sp) + 100e8f4: 00bce016 blt zero,r2,100dc78 <_dtoa_r+0x5bc> + 100e8f8: d9800f17 ldw r6,60(sp) + 100e8fc: 303cc51e bne r6,zero,100dc14 <_dtoa_r+0x558> + 100e900: 0005883a mov r2,zero + 100e904: 00d00534 movhi r3,16404 + 100e908: 980b883a mov r5,r19 + 100e90c: 180f883a mov r7,r3 + 100e910: 9009883a mov r4,r18 + 100e914: 100d883a mov r6,r2 + 100e918: 1012ed00 call 1012ed0 <__muldf3> + 100e91c: 180b883a mov r5,r3 + 100e920: a80f883a mov r7,r21 + 100e924: 1009883a mov r4,r2 + 100e928: a00d883a mov r6,r20 + 100e92c: 10136840 call 1013684 <__gedf2> + 100e930: 103cb80e bge r2,zero,100dc14 <_dtoa_r+0x558> + 100e934: 0027883a mov r19,zero + 100e938: 0025883a mov r18,zero + 100e93c: 003fc606 br 100e858 <_dtoa_r+0x119c> + 100e940: 99400117 ldw r5,4(r19) + 100e944: d9001617 ldw r4,88(sp) + 100e948: 10103940 call 1010394 <_Balloc> + 100e94c: 99800417 ldw r6,16(r19) + 100e950: 11000304 addi r4,r2,12 + 100e954: 99400304 addi r5,r19,12 + 100e958: 318d883a add r6,r6,r6 + 100e95c: 318d883a add r6,r6,r6 + 100e960: 31800204 addi r6,r6,8 + 100e964: 1023883a mov r17,r2 + 100e968: 100aa3c0 call 100aa3c + 100e96c: d9001617 ldw r4,88(sp) + 100e970: 880b883a mov r5,r17 + 100e974: 01800044 movi r6,1 + 100e978: 10107580 call 1010758 <__lshift> + 100e97c: 100b883a mov r5,r2 + 100e980: 003d9c06 br 100dff4 <_dtoa_r+0x938> + 100e984: 00800e44 movi r2,57 + 100e988: b8807026 beq r23,r2,100eb4c <_dtoa_r+0x1490> + 100e98c: b8800044 addi r2,r23,1 + 100e990: b7000044 addi fp,r22,1 + 100e994: b0800005 stb r2,0(r22) + 100e998: 003e4106 br 100e2a0 <_dtoa_r+0xbe4> + 100e99c: d8800317 ldw r2,12(sp) + 100e9a0: 018040b4 movhi r6,258 + 100e9a4: 31860404 addi r6,r6,6160 + 100e9a8: b009883a mov r4,r22 + 100e9ac: 100e90fa slli r7,r2,3 + 100e9b0: b80b883a mov r5,r23 + 100e9b4: 398f883a add r7,r7,r6 + 100e9b8: 38bffe17 ldw r2,-8(r7) + 100e9bc: d9800517 ldw r6,20(sp) + 100e9c0: 38ffff17 ldw r3,-4(r7) + 100e9c4: 37000044 addi fp,r6,1 + 100e9c8: 180f883a mov r7,r3 + 100e9cc: 100d883a mov r6,r2 + 100e9d0: 1012ed00 call 1012ed0 <__muldf3> + 100e9d4: a80b883a mov r5,r21 + 100e9d8: a009883a mov r4,r20 + 100e9dc: 182f883a mov r23,r3 + 100e9e0: 102d883a mov r22,r2 + 100e9e4: 101388c0 call 101388c <__fixdfsi> + 100e9e8: 1009883a mov r4,r2 + 100e9ec: 1027883a mov r19,r2 + 100e9f0: 10137940 call 1013794 <__floatsidf> + 100e9f4: a80b883a mov r5,r21 + 100e9f8: a009883a mov r4,r20 + 100e9fc: 180f883a mov r7,r3 + 100ea00: 100d883a mov r6,r2 + 100ea04: 1012ddc0 call 1012ddc <__subdf3> + 100ea08: 180b883a mov r5,r3 + 100ea0c: d8c00517 ldw r3,20(sp) + 100ea10: 9cc00c04 addi r19,r19,48 + 100ea14: 1009883a mov r4,r2 + 100ea18: 1cc00005 stb r19,0(r3) + 100ea1c: 2021883a mov r16,r4 + 100ea20: d9000317 ldw r4,12(sp) + 100ea24: 00800044 movi r2,1 + 100ea28: 2823883a mov r17,r5 + 100ea2c: 20802226 beq r4,r2,100eab8 <_dtoa_r+0x13fc> + 100ea30: 1029883a mov r20,r2 + 100ea34: 0005883a mov r2,zero + 100ea38: 00d00934 movhi r3,16420 + 100ea3c: 180f883a mov r7,r3 + 100ea40: 100d883a mov r6,r2 + 100ea44: 880b883a mov r5,r17 + 100ea48: 8009883a mov r4,r16 + 100ea4c: 1012ed00 call 1012ed0 <__muldf3> + 100ea50: 180b883a mov r5,r3 + 100ea54: 1009883a mov r4,r2 + 100ea58: 1823883a mov r17,r3 + 100ea5c: 1021883a mov r16,r2 + 100ea60: 101388c0 call 101388c <__fixdfsi> + 100ea64: 1009883a mov r4,r2 + 100ea68: 102b883a mov r21,r2 + 100ea6c: 10137940 call 1013794 <__floatsidf> + 100ea70: 880b883a mov r5,r17 + 100ea74: 8009883a mov r4,r16 + 100ea78: 180f883a mov r7,r3 + 100ea7c: 100d883a mov r6,r2 + 100ea80: 1012ddc0 call 1012ddc <__subdf3> + 100ea84: 180b883a mov r5,r3 + 100ea88: d8c00517 ldw r3,20(sp) + 100ea8c: 1009883a mov r4,r2 + 100ea90: ad400c04 addi r21,r21,48 + 100ea94: 1d05883a add r2,r3,r20 + 100ea98: 15400005 stb r21,0(r2) + 100ea9c: 2021883a mov r16,r4 + 100eaa0: d9000317 ldw r4,12(sp) + 100eaa4: a5000044 addi r20,r20,1 + 100eaa8: 2823883a mov r17,r5 + 100eaac: a13fe11e bne r20,r4,100ea34 <_dtoa_r+0x1378> + 100eab0: e505883a add r2,fp,r20 + 100eab4: 173fffc4 addi fp,r2,-1 + 100eab8: 0025883a mov r18,zero + 100eabc: 04cff834 movhi r19,16352 + 100eac0: b009883a mov r4,r22 + 100eac4: b80b883a mov r5,r23 + 100eac8: 900d883a mov r6,r18 + 100eacc: 980f883a mov r7,r19 + 100ead0: 1012e5c0 call 1012e5c <__adddf3> + 100ead4: 180b883a mov r5,r3 + 100ead8: 1009883a mov r4,r2 + 100eadc: 800d883a mov r6,r16 + 100eae0: 880f883a mov r7,r17 + 100eae4: 101370c0 call 101370c <__ltdf2> + 100eae8: 103cab16 blt r2,zero,100dd98 <_dtoa_r+0x6dc> + 100eaec: 0009883a mov r4,zero + 100eaf0: 980b883a mov r5,r19 + 100eaf4: b80f883a mov r7,r23 + 100eaf8: b00d883a mov r6,r22 + 100eafc: 1012ddc0 call 1012ddc <__subdf3> + 100eb00: 180b883a mov r5,r3 + 100eb04: 880f883a mov r7,r17 + 100eb08: 1009883a mov r4,r2 + 100eb0c: 800d883a mov r6,r16 + 100eb10: 10135fc0 call 10135fc <__gtdf2> + 100eb14: 00bc470e bge zero,r2,100dc34 <_dtoa_r+0x578> + 100eb18: 00c00c04 movi r3,48 + 100eb1c: e73fffc4 addi fp,fp,-1 + 100eb20: e0800007 ldb r2,0(fp) + 100eb24: 10fffd26 beq r2,r3,100eb1c <_dtoa_r+0x1460> + 100eb28: d9800417 ldw r6,16(sp) + 100eb2c: e7000044 addi fp,fp,1 + 100eb30: d9800d15 stw r6,52(sp) + 100eb34: 003cab06 br 100dde4 <_dtoa_r+0x728> + 100eb38: d8c00f17 ldw r3,60(sp) + 100eb3c: d9001117 ldw r4,68(sp) + 100eb40: 20e1c83a sub r16,r4,r3 + 100eb44: 0007883a mov r3,zero + 100eb48: 003d9b06 br 100e1b8 <_dtoa_r+0xafc> + 100eb4c: 00800e44 movi r2,57 + 100eb50: b0800005 stb r2,0(r22) + 100eb54: b5800044 addi r22,r22,1 + 100eb58: 003dc106 br 100e260 <_dtoa_r+0xba4> + 100eb5c: 05800084 movi r22,2 + 100eb60: 003bf706 br 100db40 <_dtoa_r+0x484> + 100eb64: d9000f17 ldw r4,60(sp) + 100eb68: 013c000e bge zero,r4,100db6c <_dtoa_r+0x4b0> + 100eb6c: d9800e17 ldw r6,56(sp) + 100eb70: 01bc300e bge zero,r6,100dc34 <_dtoa_r+0x578> + 100eb74: 0005883a mov r2,zero + 100eb78: 00d00934 movhi r3,16420 + 100eb7c: a80b883a mov r5,r21 + 100eb80: 180f883a mov r7,r3 + 100eb84: a009883a mov r4,r20 + 100eb88: 100d883a mov r6,r2 + 100eb8c: 1012ed00 call 1012ed0 <__muldf3> + 100eb90: b1000044 addi r4,r22,1 + 100eb94: 1021883a mov r16,r2 + 100eb98: 1823883a mov r17,r3 + 100eb9c: 10137940 call 1013794 <__floatsidf> + 100eba0: 880b883a mov r5,r17 + 100eba4: 8009883a mov r4,r16 + 100eba8: 180f883a mov r7,r3 + 100ebac: 100d883a mov r6,r2 + 100ebb0: 1012ed00 call 1012ed0 <__muldf3> + 100ebb4: 0011883a mov r8,zero + 100ebb8: 02500734 movhi r9,16412 + 100ebbc: 180b883a mov r5,r3 + 100ebc0: 480f883a mov r7,r9 + 100ebc4: 1009883a mov r4,r2 + 100ebc8: 400d883a mov r6,r8 + 100ebcc: 1012e5c0 call 1012e5c <__adddf3> + 100ebd0: 102d883a mov r22,r2 + 100ebd4: 00bf3034 movhi r2,64704 + 100ebd8: 10ef883a add r23,r2,r3 + 100ebdc: d8800d17 ldw r2,52(sp) + 100ebe0: d8c00e17 ldw r3,56(sp) + 100ebe4: 8029883a mov r20,r16 + 100ebe8: 10bfffc4 addi r2,r2,-1 + 100ebec: 882b883a mov r21,r17 + 100ebf0: d8800415 stw r2,16(sp) + 100ebf4: d8c00315 stw r3,12(sp) + 100ebf8: 003e8306 br 100e608 <_dtoa_r+0xf4c> + 100ebfc: d8800117 ldw r2,4(sp) + 100ec00: dc001117 ldw r16,68(sp) + 100ec04: dc801017 ldw r18,64(sp) + 100ec08: 00c00d84 movi r3,54 + 100ec0c: 1887c83a sub r3,r3,r2 + 100ec10: 003d6906 br 100e1b8 <_dtoa_r+0xafc> + 100ec14: 01800044 movi r6,1 + 100ec18: 3021883a mov r16,r6 + 100ec1c: d9800f15 stw r6,60(sp) + 100ec20: d9802615 stw r6,152(sp) + 100ec24: d9800e15 stw r6,56(sp) + 100ec28: 003b9306 br 100da78 <_dtoa_r+0x3bc> + 100ec2c: b021883a mov r16,r22 + 100ec30: dd800f15 stw r22,60(sp) + 100ec34: 003b9006 br 100da78 <_dtoa_r+0x3bc> + 100ec38: 103e221e bne r2,zero,100e4c4 <_dtoa_r+0xe08> + 100ec3c: b880004c andi r2,r23,1 + 100ec40: 1005003a cmpeq r2,r2,zero + 100ec44: 103e1f1e bne r2,zero,100e4c4 <_dtoa_r+0xe08> + 100ec48: 003e1b06 br 100e4b8 <_dtoa_r+0xdfc> + 100ec4c: d9001617 ldw r4,88(sp) + 100ec50: 980b883a mov r5,r19 + 100ec54: 01800284 movi r6,10 + 100ec58: 000f883a mov r7,zero + 100ec5c: 1010ac80 call 1010ac8 <__multadd> + 100ec60: d8c00e17 ldw r3,56(sp) + 100ec64: 1027883a mov r19,r2 + 100ec68: d8c00f15 stw r3,60(sp) + 100ec6c: 003cd306 br 100dfbc <_dtoa_r+0x900> + +0100ec70 <_fflush_r>: + 100ec70: defffb04 addi sp,sp,-20 + 100ec74: dcc00315 stw r19,12(sp) + 100ec78: dc800215 stw r18,8(sp) + 100ec7c: dfc00415 stw ra,16(sp) + 100ec80: dc400115 stw r17,4(sp) + 100ec84: dc000015 stw r16,0(sp) + 100ec88: 2027883a mov r19,r4 + 100ec8c: 2825883a mov r18,r5 + 100ec90: 20000226 beq r4,zero,100ec9c <_fflush_r+0x2c> + 100ec94: 20800e17 ldw r2,56(r4) + 100ec98: 10005626 beq r2,zero,100edf4 <_fflush_r+0x184> + 100ec9c: 9100030b ldhu r4,12(r18) + 100eca0: 20ffffcc andi r3,r4,65535 + 100eca4: 18e0001c xori r3,r3,32768 + 100eca8: 18e00004 addi r3,r3,-32768 + 100ecac: 1880020c andi r2,r3,8 + 100ecb0: 1000261e bne r2,zero,100ed4c <_fflush_r+0xdc> + 100ecb4: 90c00117 ldw r3,4(r18) + 100ecb8: 20820014 ori r2,r4,2048 + 100ecbc: 9080030d sth r2,12(r18) + 100ecc0: 1009883a mov r4,r2 + 100ecc4: 00c0400e bge zero,r3,100edc8 <_fflush_r+0x158> + 100ecc8: 92000a17 ldw r8,40(r18) + 100eccc: 40004026 beq r8,zero,100edd0 <_fflush_r+0x160> + 100ecd0: 2084000c andi r2,r4,4096 + 100ecd4: 10005326 beq r2,zero,100ee24 <_fflush_r+0x1b4> + 100ecd8: 94001417 ldw r16,80(r18) + 100ecdc: 9080030b ldhu r2,12(r18) + 100ece0: 1080010c andi r2,r2,4 + 100ece4: 1000481e bne r2,zero,100ee08 <_fflush_r+0x198> + 100ece8: 91400717 ldw r5,28(r18) + 100ecec: 9809883a mov r4,r19 + 100ecf0: 800d883a mov r6,r16 + 100ecf4: 000f883a mov r7,zero + 100ecf8: 403ee83a callr r8 + 100ecfc: 8080261e bne r16,r2,100ed98 <_fflush_r+0x128> + 100ed00: 9080030b ldhu r2,12(r18) + 100ed04: 91000417 ldw r4,16(r18) + 100ed08: 90000115 stw zero,4(r18) + 100ed0c: 10bdffcc andi r2,r2,63487 + 100ed10: 10ffffcc andi r3,r2,65535 + 100ed14: 18c4000c andi r3,r3,4096 + 100ed18: 9080030d sth r2,12(r18) + 100ed1c: 91000015 stw r4,0(r18) + 100ed20: 18002b26 beq r3,zero,100edd0 <_fflush_r+0x160> + 100ed24: 0007883a mov r3,zero + 100ed28: 1805883a mov r2,r3 + 100ed2c: 94001415 stw r16,80(r18) + 100ed30: dfc00417 ldw ra,16(sp) + 100ed34: dcc00317 ldw r19,12(sp) + 100ed38: dc800217 ldw r18,8(sp) + 100ed3c: dc400117 ldw r17,4(sp) + 100ed40: dc000017 ldw r16,0(sp) + 100ed44: dec00504 addi sp,sp,20 + 100ed48: f800283a ret + 100ed4c: 94400417 ldw r17,16(r18) + 100ed50: 88001f26 beq r17,zero,100edd0 <_fflush_r+0x160> + 100ed54: 90800017 ldw r2,0(r18) + 100ed58: 18c000cc andi r3,r3,3 + 100ed5c: 94400015 stw r17,0(r18) + 100ed60: 1461c83a sub r16,r2,r17 + 100ed64: 18002526 beq r3,zero,100edfc <_fflush_r+0x18c> + 100ed68: 0005883a mov r2,zero + 100ed6c: 90800215 stw r2,8(r18) + 100ed70: 0400170e bge zero,r16,100edd0 <_fflush_r+0x160> + 100ed74: 90c00917 ldw r3,36(r18) + 100ed78: 91400717 ldw r5,28(r18) + 100ed7c: 880d883a mov r6,r17 + 100ed80: 800f883a mov r7,r16 + 100ed84: 9809883a mov r4,r19 + 100ed88: 183ee83a callr r3 + 100ed8c: 88a3883a add r17,r17,r2 + 100ed90: 80a1c83a sub r16,r16,r2 + 100ed94: 00bff616 blt zero,r2,100ed70 <_fflush_r+0x100> + 100ed98: 9080030b ldhu r2,12(r18) + 100ed9c: 00ffffc4 movi r3,-1 + 100eda0: 10801014 ori r2,r2,64 + 100eda4: 9080030d sth r2,12(r18) + 100eda8: 1805883a mov r2,r3 + 100edac: dfc00417 ldw ra,16(sp) + 100edb0: dcc00317 ldw r19,12(sp) + 100edb4: dc800217 ldw r18,8(sp) + 100edb8: dc400117 ldw r17,4(sp) + 100edbc: dc000017 ldw r16,0(sp) + 100edc0: dec00504 addi sp,sp,20 + 100edc4: f800283a ret + 100edc8: 90800f17 ldw r2,60(r18) + 100edcc: 00bfbe16 blt zero,r2,100ecc8 <_fflush_r+0x58> + 100edd0: 0007883a mov r3,zero + 100edd4: 1805883a mov r2,r3 + 100edd8: dfc00417 ldw ra,16(sp) + 100eddc: dcc00317 ldw r19,12(sp) + 100ede0: dc800217 ldw r18,8(sp) + 100ede4: dc400117 ldw r17,4(sp) + 100ede8: dc000017 ldw r16,0(sp) + 100edec: dec00504 addi sp,sp,20 + 100edf0: f800283a ret + 100edf4: 100ef080 call 100ef08 <__sinit> + 100edf8: 003fa806 br 100ec9c <_fflush_r+0x2c> + 100edfc: 90800517 ldw r2,20(r18) + 100ee00: 90800215 stw r2,8(r18) + 100ee04: 003fda06 br 100ed70 <_fflush_r+0x100> + 100ee08: 90800117 ldw r2,4(r18) + 100ee0c: 90c00c17 ldw r3,48(r18) + 100ee10: 80a1c83a sub r16,r16,r2 + 100ee14: 183fb426 beq r3,zero,100ece8 <_fflush_r+0x78> + 100ee18: 90800f17 ldw r2,60(r18) + 100ee1c: 80a1c83a sub r16,r16,r2 + 100ee20: 003fb106 br 100ece8 <_fflush_r+0x78> + 100ee24: 91400717 ldw r5,28(r18) + 100ee28: 9809883a mov r4,r19 + 100ee2c: 000d883a mov r6,zero + 100ee30: 01c00044 movi r7,1 + 100ee34: 403ee83a callr r8 + 100ee38: 1021883a mov r16,r2 + 100ee3c: 00bfffc4 movi r2,-1 + 100ee40: 80800226 beq r16,r2,100ee4c <_fflush_r+0x1dc> + 100ee44: 92000a17 ldw r8,40(r18) + 100ee48: 003fa406 br 100ecdc <_fflush_r+0x6c> + 100ee4c: 98c00017 ldw r3,0(r19) + 100ee50: 00800744 movi r2,29 + 100ee54: 18bfde26 beq r3,r2,100edd0 <_fflush_r+0x160> + 100ee58: 9080030b ldhu r2,12(r18) + 100ee5c: 8007883a mov r3,r16 + 100ee60: 10801014 ori r2,r2,64 + 100ee64: 9080030d sth r2,12(r18) + 100ee68: 003fcf06 br 100eda8 <_fflush_r+0x138> + +0100ee6c : + 100ee6c: 01404074 movhi r5,257 + 100ee70: 297b1c04 addi r5,r5,-5008 + 100ee74: 2007883a mov r3,r4 + 100ee78: 20000526 beq r4,zero,100ee90 + 100ee7c: 008040b4 movhi r2,258 + 100ee80: 108dc804 addi r2,r2,14112 + 100ee84: 11000017 ldw r4,0(r2) + 100ee88: 180b883a mov r5,r3 + 100ee8c: 100ec701 jmpi 100ec70 <_fflush_r> + 100ee90: 008040b4 movhi r2,258 + 100ee94: 108dc904 addi r2,r2,14116 + 100ee98: 11000017 ldw r4,0(r2) + 100ee9c: 100fa3c1 jmpi 100fa3c <_fwalk_reent> + +0100eea0 : + 100eea0: 00804074 movhi r2,257 + 100eea4: 10859604 addi r2,r2,5720 + 100eea8: 20800b15 stw r2,44(r4) + 100eeac: 00804074 movhi r2,257 + 100eeb0: 1085d104 addi r2,r2,5956 + 100eeb4: 20800815 stw r2,32(r4) + 100eeb8: 00c04074 movhi r3,257 + 100eebc: 18c5b204 addi r3,r3,5832 + 100eec0: 00804074 movhi r2,257 + 100eec4: 10859804 addi r2,r2,5728 + 100eec8: 2140030d sth r5,12(r4) + 100eecc: 2180038d sth r6,14(r4) + 100eed0: 20c00915 stw r3,36(r4) + 100eed4: 20800a15 stw r2,40(r4) + 100eed8: 20000015 stw zero,0(r4) + 100eedc: 20000115 stw zero,4(r4) + 100eee0: 20000215 stw zero,8(r4) + 100eee4: 20000415 stw zero,16(r4) + 100eee8: 20000515 stw zero,20(r4) + 100eeec: 20000615 stw zero,24(r4) + 100eef0: 21000715 stw r4,28(r4) + 100eef4: f800283a ret + +0100eef8 <__sfp_lock_acquire>: + 100eef8: f800283a ret + +0100eefc <__sfp_lock_release>: + 100eefc: f800283a ret + +0100ef00 <__sinit_lock_acquire>: + 100ef00: f800283a ret + +0100ef04 <__sinit_lock_release>: + 100ef04: f800283a ret + +0100ef08 <__sinit>: + 100ef08: 20800e17 ldw r2,56(r4) + 100ef0c: defffd04 addi sp,sp,-12 + 100ef10: dc400115 stw r17,4(sp) + 100ef14: dc000015 stw r16,0(sp) + 100ef18: dfc00215 stw ra,8(sp) + 100ef1c: 04400044 movi r17,1 + 100ef20: 01400104 movi r5,4 + 100ef24: 000d883a mov r6,zero + 100ef28: 2021883a mov r16,r4 + 100ef2c: 2200bb04 addi r8,r4,748 + 100ef30: 200f883a mov r7,r4 + 100ef34: 10000526 beq r2,zero,100ef4c <__sinit+0x44> + 100ef38: dfc00217 ldw ra,8(sp) + 100ef3c: dc400117 ldw r17,4(sp) + 100ef40: dc000017 ldw r16,0(sp) + 100ef44: dec00304 addi sp,sp,12 + 100ef48: f800283a ret + 100ef4c: 21000117 ldw r4,4(r4) + 100ef50: 00804074 movhi r2,257 + 100ef54: 10bbfb04 addi r2,r2,-4116 + 100ef58: 00c000c4 movi r3,3 + 100ef5c: 80800f15 stw r2,60(r16) + 100ef60: 80c0b915 stw r3,740(r16) + 100ef64: 8200ba15 stw r8,744(r16) + 100ef68: 84400e15 stw r17,56(r16) + 100ef6c: 8000b815 stw zero,736(r16) + 100ef70: 100eea00 call 100eea0 + 100ef74: 81000217 ldw r4,8(r16) + 100ef78: 880d883a mov r6,r17 + 100ef7c: 800f883a mov r7,r16 + 100ef80: 01400284 movi r5,10 + 100ef84: 100eea00 call 100eea0 + 100ef88: 81000317 ldw r4,12(r16) + 100ef8c: 800f883a mov r7,r16 + 100ef90: 01400484 movi r5,18 + 100ef94: 01800084 movi r6,2 + 100ef98: dfc00217 ldw ra,8(sp) + 100ef9c: dc400117 ldw r17,4(sp) + 100efa0: dc000017 ldw r16,0(sp) + 100efa4: dec00304 addi sp,sp,12 + 100efa8: 100eea01 jmpi 100eea0 + +0100efac <__fp_lock>: + 100efac: 0005883a mov r2,zero + 100efb0: f800283a ret + +0100efb4 <__fp_unlock>: + 100efb4: 0005883a mov r2,zero + 100efb8: f800283a ret + +0100efbc <__fp_unlock_all>: + 100efbc: 008040b4 movhi r2,258 + 100efc0: 108dc804 addi r2,r2,14112 + 100efc4: 11000017 ldw r4,0(r2) + 100efc8: 01404074 movhi r5,257 + 100efcc: 297bed04 addi r5,r5,-4172 + 100efd0: 100fb041 jmpi 100fb04 <_fwalk> + +0100efd4 <__fp_lock_all>: + 100efd4: 008040b4 movhi r2,258 + 100efd8: 108dc804 addi r2,r2,14112 + 100efdc: 11000017 ldw r4,0(r2) + 100efe0: 01404074 movhi r5,257 + 100efe4: 297beb04 addi r5,r5,-4180 + 100efe8: 100fb041 jmpi 100fb04 <_fwalk> + +0100efec <_cleanup_r>: + 100efec: 01404074 movhi r5,257 + 100eff0: 29471604 addi r5,r5,7256 + 100eff4: 100fb041 jmpi 100fb04 <_fwalk> + +0100eff8 <_cleanup>: + 100eff8: 008040b4 movhi r2,258 + 100effc: 108dc904 addi r2,r2,14116 + 100f000: 11000017 ldw r4,0(r2) + 100f004: 100efec1 jmpi 100efec <_cleanup_r> + +0100f008 <__sfmoreglue>: + 100f008: defffc04 addi sp,sp,-16 + 100f00c: dc400115 stw r17,4(sp) + 100f010: 2c401724 muli r17,r5,92 + 100f014: dc800215 stw r18,8(sp) + 100f018: 2825883a mov r18,r5 + 100f01c: 89400304 addi r5,r17,12 + 100f020: dc000015 stw r16,0(sp) + 100f024: dfc00315 stw ra,12(sp) + 100f028: 100a1a40 call 100a1a4 <_malloc_r> + 100f02c: 0021883a mov r16,zero + 100f030: 880d883a mov r6,r17 + 100f034: 000b883a mov r5,zero + 100f038: 10000626 beq r2,zero,100f054 <__sfmoreglue+0x4c> + 100f03c: 11000304 addi r4,r2,12 + 100f040: 14800115 stw r18,4(r2) + 100f044: 10000015 stw zero,0(r2) + 100f048: 11000215 stw r4,8(r2) + 100f04c: 1021883a mov r16,r2 + 100f050: 100abbc0 call 100abbc + 100f054: 8005883a mov r2,r16 + 100f058: dfc00317 ldw ra,12(sp) + 100f05c: dc800217 ldw r18,8(sp) + 100f060: dc400117 ldw r17,4(sp) + 100f064: dc000017 ldw r16,0(sp) + 100f068: dec00404 addi sp,sp,16 + 100f06c: f800283a ret + +0100f070 <__sfp>: + 100f070: defffd04 addi sp,sp,-12 + 100f074: 008040b4 movhi r2,258 + 100f078: 108dc904 addi r2,r2,14116 + 100f07c: dc000015 stw r16,0(sp) + 100f080: 14000017 ldw r16,0(r2) + 100f084: dc400115 stw r17,4(sp) + 100f088: dfc00215 stw ra,8(sp) + 100f08c: 80800e17 ldw r2,56(r16) + 100f090: 2023883a mov r17,r4 + 100f094: 10002626 beq r2,zero,100f130 <__sfp+0xc0> + 100f098: 8400b804 addi r16,r16,736 + 100f09c: 80800117 ldw r2,4(r16) + 100f0a0: 81000217 ldw r4,8(r16) + 100f0a4: 10ffffc4 addi r3,r2,-1 + 100f0a8: 18000916 blt r3,zero,100f0d0 <__sfp+0x60> + 100f0ac: 2080030f ldh r2,12(r4) + 100f0b0: 10000b26 beq r2,zero,100f0e0 <__sfp+0x70> + 100f0b4: 017fffc4 movi r5,-1 + 100f0b8: 00000206 br 100f0c4 <__sfp+0x54> + 100f0bc: 2080030f ldh r2,12(r4) + 100f0c0: 10000726 beq r2,zero,100f0e0 <__sfp+0x70> + 100f0c4: 18ffffc4 addi r3,r3,-1 + 100f0c8: 21001704 addi r4,r4,92 + 100f0cc: 197ffb1e bne r3,r5,100f0bc <__sfp+0x4c> + 100f0d0: 80800017 ldw r2,0(r16) + 100f0d4: 10001926 beq r2,zero,100f13c <__sfp+0xcc> + 100f0d8: 1021883a mov r16,r2 + 100f0dc: 003fef06 br 100f09c <__sfp+0x2c> + 100f0e0: 00bfffc4 movi r2,-1 + 100f0e4: 00c00044 movi r3,1 + 100f0e8: 2080038d sth r2,14(r4) + 100f0ec: 20c0030d sth r3,12(r4) + 100f0f0: 20000015 stw zero,0(r4) + 100f0f4: 20000215 stw zero,8(r4) + 100f0f8: 20000115 stw zero,4(r4) + 100f0fc: 20000415 stw zero,16(r4) + 100f100: 20000515 stw zero,20(r4) + 100f104: 20000615 stw zero,24(r4) + 100f108: 20000c15 stw zero,48(r4) + 100f10c: 20000d15 stw zero,52(r4) + 100f110: 20001115 stw zero,68(r4) + 100f114: 20001215 stw zero,72(r4) + 100f118: 2005883a mov r2,r4 + 100f11c: dfc00217 ldw ra,8(sp) + 100f120: dc400117 ldw r17,4(sp) + 100f124: dc000017 ldw r16,0(sp) + 100f128: dec00304 addi sp,sp,12 + 100f12c: f800283a ret + 100f130: 8009883a mov r4,r16 + 100f134: 100ef080 call 100ef08 <__sinit> + 100f138: 003fd706 br 100f098 <__sfp+0x28> + 100f13c: 8809883a mov r4,r17 + 100f140: 01400104 movi r5,4 + 100f144: 100f0080 call 100f008 <__sfmoreglue> + 100f148: 80800015 stw r2,0(r16) + 100f14c: 103fe21e bne r2,zero,100f0d8 <__sfp+0x68> + 100f150: 00800304 movi r2,12 + 100f154: 0009883a mov r4,zero + 100f158: 88800015 stw r2,0(r17) + 100f15c: 003fee06 br 100f118 <__sfp+0xa8> + +0100f160 <_malloc_trim_r>: + 100f160: defffb04 addi sp,sp,-20 + 100f164: dcc00315 stw r19,12(sp) + 100f168: 04c040b4 movhi r19,258 + 100f16c: 9cc6f004 addi r19,r19,7104 + 100f170: dc800215 stw r18,8(sp) + 100f174: dc400115 stw r17,4(sp) + 100f178: dc000015 stw r16,0(sp) + 100f17c: 2823883a mov r17,r5 + 100f180: 2025883a mov r18,r4 + 100f184: dfc00415 stw ra,16(sp) + 100f188: 10150a00 call 10150a0 <__malloc_lock> + 100f18c: 98800217 ldw r2,8(r19) + 100f190: 9009883a mov r4,r18 + 100f194: 000b883a mov r5,zero + 100f198: 10c00117 ldw r3,4(r2) + 100f19c: 00bfff04 movi r2,-4 + 100f1a0: 18a0703a and r16,r3,r2 + 100f1a4: 8463c83a sub r17,r16,r17 + 100f1a8: 8c43fbc4 addi r17,r17,4079 + 100f1ac: 8822d33a srli r17,r17,12 + 100f1b0: 0083ffc4 movi r2,4095 + 100f1b4: 8c7fffc4 addi r17,r17,-1 + 100f1b8: 8822933a slli r17,r17,12 + 100f1bc: 1440060e bge r2,r17,100f1d8 <_malloc_trim_r+0x78> + 100f1c0: 100ada40 call 100ada4 <_sbrk_r> + 100f1c4: 98c00217 ldw r3,8(r19) + 100f1c8: 9009883a mov r4,r18 + 100f1cc: 044bc83a sub r5,zero,r17 + 100f1d0: 80c7883a add r3,r16,r3 + 100f1d4: 10c00926 beq r2,r3,100f1fc <_malloc_trim_r+0x9c> + 100f1d8: 10151a80 call 10151a8 <__malloc_unlock> + 100f1dc: 0005883a mov r2,zero + 100f1e0: dfc00417 ldw ra,16(sp) + 100f1e4: dcc00317 ldw r19,12(sp) + 100f1e8: dc800217 ldw r18,8(sp) + 100f1ec: dc400117 ldw r17,4(sp) + 100f1f0: dc000017 ldw r16,0(sp) + 100f1f4: dec00504 addi sp,sp,20 + 100f1f8: f800283a ret + 100f1fc: 9009883a mov r4,r18 + 100f200: 100ada40 call 100ada4 <_sbrk_r> + 100f204: 844dc83a sub r6,r16,r17 + 100f208: 00ffffc4 movi r3,-1 + 100f20c: 9009883a mov r4,r18 + 100f210: 000b883a mov r5,zero + 100f214: 01c040f4 movhi r7,259 + 100f218: 39e73304 addi r7,r7,-25396 + 100f21c: 31800054 ori r6,r6,1 + 100f220: 10c00926 beq r2,r3,100f248 <_malloc_trim_r+0xe8> + 100f224: 38800017 ldw r2,0(r7) + 100f228: 98c00217 ldw r3,8(r19) + 100f22c: 9009883a mov r4,r18 + 100f230: 1445c83a sub r2,r2,r17 + 100f234: 38800015 stw r2,0(r7) + 100f238: 19800115 stw r6,4(r3) + 100f23c: 10151a80 call 10151a8 <__malloc_unlock> + 100f240: 00800044 movi r2,1 + 100f244: 003fe606 br 100f1e0 <_malloc_trim_r+0x80> + 100f248: 100ada40 call 100ada4 <_sbrk_r> + 100f24c: 99800217 ldw r6,8(r19) + 100f250: 100f883a mov r7,r2 + 100f254: 9009883a mov r4,r18 + 100f258: 1187c83a sub r3,r2,r6 + 100f25c: 008003c4 movi r2,15 + 100f260: 19400054 ori r5,r3,1 + 100f264: 10ffdc0e bge r2,r3,100f1d8 <_malloc_trim_r+0x78> + 100f268: 008040b4 movhi r2,258 + 100f26c: 108dc604 addi r2,r2,14104 + 100f270: 10c00017 ldw r3,0(r2) + 100f274: 008040f4 movhi r2,259 + 100f278: 10a73304 addi r2,r2,-25396 + 100f27c: 31400115 stw r5,4(r6) + 100f280: 38c7c83a sub r3,r7,r3 + 100f284: 10c00015 stw r3,0(r2) + 100f288: 003fd306 br 100f1d8 <_malloc_trim_r+0x78> + +0100f28c <_free_r>: + 100f28c: defffd04 addi sp,sp,-12 + 100f290: dc400115 stw r17,4(sp) + 100f294: dc000015 stw r16,0(sp) + 100f298: dfc00215 stw ra,8(sp) + 100f29c: 2821883a mov r16,r5 + 100f2a0: 2023883a mov r17,r4 + 100f2a4: 28005a26 beq r5,zero,100f410 <_free_r+0x184> + 100f2a8: 10150a00 call 10150a0 <__malloc_lock> + 100f2ac: 823ffe04 addi r8,r16,-8 + 100f2b0: 41400117 ldw r5,4(r8) + 100f2b4: 00bfff84 movi r2,-2 + 100f2b8: 028040b4 movhi r10,258 + 100f2bc: 5286f004 addi r10,r10,7104 + 100f2c0: 288e703a and r7,r5,r2 + 100f2c4: 41cd883a add r6,r8,r7 + 100f2c8: 30c00117 ldw r3,4(r6) + 100f2cc: 51000217 ldw r4,8(r10) + 100f2d0: 00bfff04 movi r2,-4 + 100f2d4: 1892703a and r9,r3,r2 + 100f2d8: 5017883a mov r11,r10 + 100f2dc: 31006726 beq r6,r4,100f47c <_free_r+0x1f0> + 100f2e0: 2880004c andi r2,r5,1 + 100f2e4: 1005003a cmpeq r2,r2,zero + 100f2e8: 32400115 stw r9,4(r6) + 100f2ec: 10001a1e bne r2,zero,100f358 <_free_r+0xcc> + 100f2f0: 000b883a mov r5,zero + 100f2f4: 3247883a add r3,r6,r9 + 100f2f8: 18800117 ldw r2,4(r3) + 100f2fc: 1080004c andi r2,r2,1 + 100f300: 1000231e bne r2,zero,100f390 <_free_r+0x104> + 100f304: 280ac03a cmpne r5,r5,zero + 100f308: 3a4f883a add r7,r7,r9 + 100f30c: 2800451e bne r5,zero,100f424 <_free_r+0x198> + 100f310: 31000217 ldw r4,8(r6) + 100f314: 008040b4 movhi r2,258 + 100f318: 1086f204 addi r2,r2,7112 + 100f31c: 20807b26 beq r4,r2,100f50c <_free_r+0x280> + 100f320: 30800317 ldw r2,12(r6) + 100f324: 3a07883a add r3,r7,r8 + 100f328: 19c00015 stw r7,0(r3) + 100f32c: 11000215 stw r4,8(r2) + 100f330: 20800315 stw r2,12(r4) + 100f334: 38800054 ori r2,r7,1 + 100f338: 40800115 stw r2,4(r8) + 100f33c: 28001a26 beq r5,zero,100f3a8 <_free_r+0x11c> + 100f340: 8809883a mov r4,r17 + 100f344: dfc00217 ldw ra,8(sp) + 100f348: dc400117 ldw r17,4(sp) + 100f34c: dc000017 ldw r16,0(sp) + 100f350: dec00304 addi sp,sp,12 + 100f354: 10151a81 jmpi 10151a8 <__malloc_unlock> + 100f358: 80bffe17 ldw r2,-8(r16) + 100f35c: 50c00204 addi r3,r10,8 + 100f360: 4091c83a sub r8,r8,r2 + 100f364: 41000217 ldw r4,8(r8) + 100f368: 388f883a add r7,r7,r2 + 100f36c: 20c06126 beq r4,r3,100f4f4 <_free_r+0x268> + 100f370: 40800317 ldw r2,12(r8) + 100f374: 3247883a add r3,r6,r9 + 100f378: 000b883a mov r5,zero + 100f37c: 11000215 stw r4,8(r2) + 100f380: 20800315 stw r2,12(r4) + 100f384: 18800117 ldw r2,4(r3) + 100f388: 1080004c andi r2,r2,1 + 100f38c: 103fdd26 beq r2,zero,100f304 <_free_r+0x78> + 100f390: 38800054 ori r2,r7,1 + 100f394: 3a07883a add r3,r7,r8 + 100f398: 280ac03a cmpne r5,r5,zero + 100f39c: 40800115 stw r2,4(r8) + 100f3a0: 19c00015 stw r7,0(r3) + 100f3a4: 283fe61e bne r5,zero,100f340 <_free_r+0xb4> + 100f3a8: 00807fc4 movi r2,511 + 100f3ac: 11c01f2e bgeu r2,r7,100f42c <_free_r+0x1a0> + 100f3b0: 3806d27a srli r3,r7,9 + 100f3b4: 1800481e bne r3,zero,100f4d8 <_free_r+0x24c> + 100f3b8: 3804d0fa srli r2,r7,3 + 100f3bc: 100690fa slli r3,r2,3 + 100f3c0: 1acd883a add r6,r3,r11 + 100f3c4: 31400217 ldw r5,8(r6) + 100f3c8: 31405926 beq r6,r5,100f530 <_free_r+0x2a4> + 100f3cc: 28800117 ldw r2,4(r5) + 100f3d0: 00ffff04 movi r3,-4 + 100f3d4: 10c4703a and r2,r2,r3 + 100f3d8: 3880022e bgeu r7,r2,100f3e4 <_free_r+0x158> + 100f3dc: 29400217 ldw r5,8(r5) + 100f3e0: 317ffa1e bne r6,r5,100f3cc <_free_r+0x140> + 100f3e4: 29800317 ldw r6,12(r5) + 100f3e8: 41800315 stw r6,12(r8) + 100f3ec: 41400215 stw r5,8(r8) + 100f3f0: 8809883a mov r4,r17 + 100f3f4: 2a000315 stw r8,12(r5) + 100f3f8: 32000215 stw r8,8(r6) + 100f3fc: dfc00217 ldw ra,8(sp) + 100f400: dc400117 ldw r17,4(sp) + 100f404: dc000017 ldw r16,0(sp) + 100f408: dec00304 addi sp,sp,12 + 100f40c: 10151a81 jmpi 10151a8 <__malloc_unlock> + 100f410: dfc00217 ldw ra,8(sp) + 100f414: dc400117 ldw r17,4(sp) + 100f418: dc000017 ldw r16,0(sp) + 100f41c: dec00304 addi sp,sp,12 + 100f420: f800283a ret + 100f424: 31000217 ldw r4,8(r6) + 100f428: 003fbd06 br 100f320 <_free_r+0x94> + 100f42c: 3806d0fa srli r3,r7,3 + 100f430: 00800044 movi r2,1 + 100f434: 51400117 ldw r5,4(r10) + 100f438: 180890fa slli r4,r3,3 + 100f43c: 1807d0ba srai r3,r3,2 + 100f440: 22c9883a add r4,r4,r11 + 100f444: 21800217 ldw r6,8(r4) + 100f448: 10c4983a sll r2,r2,r3 + 100f44c: 41000315 stw r4,12(r8) + 100f450: 41800215 stw r6,8(r8) + 100f454: 288ab03a or r5,r5,r2 + 100f458: 22000215 stw r8,8(r4) + 100f45c: 8809883a mov r4,r17 + 100f460: 51400115 stw r5,4(r10) + 100f464: 32000315 stw r8,12(r6) + 100f468: dfc00217 ldw ra,8(sp) + 100f46c: dc400117 ldw r17,4(sp) + 100f470: dc000017 ldw r16,0(sp) + 100f474: dec00304 addi sp,sp,12 + 100f478: 10151a81 jmpi 10151a8 <__malloc_unlock> + 100f47c: 2880004c andi r2,r5,1 + 100f480: 3a4d883a add r6,r7,r9 + 100f484: 1000071e bne r2,zero,100f4a4 <_free_r+0x218> + 100f488: 80bffe17 ldw r2,-8(r16) + 100f48c: 4091c83a sub r8,r8,r2 + 100f490: 41000317 ldw r4,12(r8) + 100f494: 40c00217 ldw r3,8(r8) + 100f498: 308d883a add r6,r6,r2 + 100f49c: 20c00215 stw r3,8(r4) + 100f4a0: 19000315 stw r4,12(r3) + 100f4a4: 008040b4 movhi r2,258 + 100f4a8: 108dc504 addi r2,r2,14100 + 100f4ac: 11000017 ldw r4,0(r2) + 100f4b0: 30c00054 ori r3,r6,1 + 100f4b4: 52000215 stw r8,8(r10) + 100f4b8: 40c00115 stw r3,4(r8) + 100f4bc: 313fa036 bltu r6,r4,100f340 <_free_r+0xb4> + 100f4c0: 008040b4 movhi r2,258 + 100f4c4: 10950504 addi r2,r2,21524 + 100f4c8: 11400017 ldw r5,0(r2) + 100f4cc: 8809883a mov r4,r17 + 100f4d0: 100f1600 call 100f160 <_malloc_trim_r> + 100f4d4: 003f9a06 br 100f340 <_free_r+0xb4> + 100f4d8: 00800104 movi r2,4 + 100f4dc: 10c0072e bgeu r2,r3,100f4fc <_free_r+0x270> + 100f4e0: 00800504 movi r2,20 + 100f4e4: 10c01936 bltu r2,r3,100f54c <_free_r+0x2c0> + 100f4e8: 188016c4 addi r2,r3,91 + 100f4ec: 100690fa slli r3,r2,3 + 100f4f0: 003fb306 br 100f3c0 <_free_r+0x134> + 100f4f4: 01400044 movi r5,1 + 100f4f8: 003f7e06 br 100f2f4 <_free_r+0x68> + 100f4fc: 3804d1ba srli r2,r7,6 + 100f500: 10800e04 addi r2,r2,56 + 100f504: 100690fa slli r3,r2,3 + 100f508: 003fad06 br 100f3c0 <_free_r+0x134> + 100f50c: 22000315 stw r8,12(r4) + 100f510: 22000215 stw r8,8(r4) + 100f514: 3a05883a add r2,r7,r8 + 100f518: 38c00054 ori r3,r7,1 + 100f51c: 11c00015 stw r7,0(r2) + 100f520: 41000215 stw r4,8(r8) + 100f524: 40c00115 stw r3,4(r8) + 100f528: 41000315 stw r4,12(r8) + 100f52c: 003f8406 br 100f340 <_free_r+0xb4> + 100f530: 1005d0ba srai r2,r2,2 + 100f534: 00c00044 movi r3,1 + 100f538: 51000117 ldw r4,4(r10) + 100f53c: 1886983a sll r3,r3,r2 + 100f540: 20c8b03a or r4,r4,r3 + 100f544: 51000115 stw r4,4(r10) + 100f548: 003fa706 br 100f3e8 <_free_r+0x15c> + 100f54c: 00801504 movi r2,84 + 100f550: 10c00436 bltu r2,r3,100f564 <_free_r+0x2d8> + 100f554: 3804d33a srli r2,r7,12 + 100f558: 10801b84 addi r2,r2,110 + 100f55c: 100690fa slli r3,r2,3 + 100f560: 003f9706 br 100f3c0 <_free_r+0x134> + 100f564: 00805504 movi r2,340 + 100f568: 10c00436 bltu r2,r3,100f57c <_free_r+0x2f0> + 100f56c: 3804d3fa srli r2,r7,15 + 100f570: 10801dc4 addi r2,r2,119 + 100f574: 100690fa slli r3,r2,3 + 100f578: 003f9106 br 100f3c0 <_free_r+0x134> + 100f57c: 00815504 movi r2,1364 + 100f580: 10c0032e bgeu r2,r3,100f590 <_free_r+0x304> + 100f584: 00801f84 movi r2,126 + 100f588: 00c0fc04 movi r3,1008 + 100f58c: 003f8c06 br 100f3c0 <_free_r+0x134> + 100f590: 3804d4ba srli r2,r7,18 + 100f594: 10801f04 addi r2,r2,124 + 100f598: 100690fa slli r3,r2,3 + 100f59c: 003f8806 br 100f3c0 <_free_r+0x134> + +0100f5a0 <__sfvwrite_r>: + 100f5a0: 30800217 ldw r2,8(r6) + 100f5a4: defff504 addi sp,sp,-44 + 100f5a8: df000915 stw fp,36(sp) + 100f5ac: dd800715 stw r22,28(sp) + 100f5b0: dc800315 stw r18,12(sp) + 100f5b4: dfc00a15 stw ra,40(sp) + 100f5b8: ddc00815 stw r23,32(sp) + 100f5bc: dd400615 stw r21,24(sp) + 100f5c0: dd000515 stw r20,20(sp) + 100f5c4: dcc00415 stw r19,16(sp) + 100f5c8: dc400215 stw r17,8(sp) + 100f5cc: dc000115 stw r16,4(sp) + 100f5d0: 302d883a mov r22,r6 + 100f5d4: 2039883a mov fp,r4 + 100f5d8: 2825883a mov r18,r5 + 100f5dc: 10001c26 beq r2,zero,100f650 <__sfvwrite_r+0xb0> + 100f5e0: 29c0030b ldhu r7,12(r5) + 100f5e4: 3880020c andi r2,r7,8 + 100f5e8: 10002726 beq r2,zero,100f688 <__sfvwrite_r+0xe8> + 100f5ec: 28800417 ldw r2,16(r5) + 100f5f0: 10002526 beq r2,zero,100f688 <__sfvwrite_r+0xe8> + 100f5f4: 3880008c andi r2,r7,2 + 100f5f8: b5400017 ldw r21,0(r22) + 100f5fc: 10002826 beq r2,zero,100f6a0 <__sfvwrite_r+0x100> + 100f600: 0021883a mov r16,zero + 100f604: 0023883a mov r17,zero + 100f608: 880d883a mov r6,r17 + 100f60c: e009883a mov r4,fp + 100f610: 00810004 movi r2,1024 + 100f614: 80006e26 beq r16,zero,100f7d0 <__sfvwrite_r+0x230> + 100f618: 800f883a mov r7,r16 + 100f61c: 91400717 ldw r5,28(r18) + 100f620: 1400012e bgeu r2,r16,100f628 <__sfvwrite_r+0x88> + 100f624: 100f883a mov r7,r2 + 100f628: 90c00917 ldw r3,36(r18) + 100f62c: 183ee83a callr r3 + 100f630: 1007883a mov r3,r2 + 100f634: 80a1c83a sub r16,r16,r2 + 100f638: 88a3883a add r17,r17,r2 + 100f63c: 00806d0e bge zero,r2,100f7f4 <__sfvwrite_r+0x254> + 100f640: b0800217 ldw r2,8(r22) + 100f644: 10c5c83a sub r2,r2,r3 + 100f648: b0800215 stw r2,8(r22) + 100f64c: 103fee1e bne r2,zero,100f608 <__sfvwrite_r+0x68> + 100f650: 0009883a mov r4,zero + 100f654: 2005883a mov r2,r4 + 100f658: dfc00a17 ldw ra,40(sp) + 100f65c: df000917 ldw fp,36(sp) + 100f660: ddc00817 ldw r23,32(sp) + 100f664: dd800717 ldw r22,28(sp) + 100f668: dd400617 ldw r21,24(sp) + 100f66c: dd000517 ldw r20,20(sp) + 100f670: dcc00417 ldw r19,16(sp) + 100f674: dc800317 ldw r18,12(sp) + 100f678: dc400217 ldw r17,8(sp) + 100f67c: dc000117 ldw r16,4(sp) + 100f680: dec00b04 addi sp,sp,44 + 100f684: f800283a ret + 100f688: 100d3680 call 100d368 <__swsetup_r> + 100f68c: 1000e41e bne r2,zero,100fa20 <__sfvwrite_r+0x480> + 100f690: 91c0030b ldhu r7,12(r18) + 100f694: b5400017 ldw r21,0(r22) + 100f698: 3880008c andi r2,r7,2 + 100f69c: 103fd81e bne r2,zero,100f600 <__sfvwrite_r+0x60> + 100f6a0: 3880004c andi r2,r7,1 + 100f6a4: 1005003a cmpeq r2,r2,zero + 100f6a8: 10005726 beq r2,zero,100f808 <__sfvwrite_r+0x268> + 100f6ac: 0029883a mov r20,zero + 100f6b0: 002f883a mov r23,zero + 100f6b4: a0004226 beq r20,zero,100f7c0 <__sfvwrite_r+0x220> + 100f6b8: 3880800c andi r2,r7,512 + 100f6bc: 94000217 ldw r16,8(r18) + 100f6c0: 10008b26 beq r2,zero,100f8f0 <__sfvwrite_r+0x350> + 100f6c4: 800d883a mov r6,r16 + 100f6c8: a400a536 bltu r20,r16,100f960 <__sfvwrite_r+0x3c0> + 100f6cc: 3881200c andi r2,r7,1152 + 100f6d0: 10002726 beq r2,zero,100f770 <__sfvwrite_r+0x1d0> + 100f6d4: 90800517 ldw r2,20(r18) + 100f6d8: 92000417 ldw r8,16(r18) + 100f6dc: 91400017 ldw r5,0(r18) + 100f6e0: 1087883a add r3,r2,r2 + 100f6e4: 1887883a add r3,r3,r2 + 100f6e8: 1808d7fa srli r4,r3,31 + 100f6ec: 2a21c83a sub r16,r5,r8 + 100f6f0: 80800044 addi r2,r16,1 + 100f6f4: 20c9883a add r4,r4,r3 + 100f6f8: 2027d07a srai r19,r4,1 + 100f6fc: a085883a add r2,r20,r2 + 100f700: 980d883a mov r6,r19 + 100f704: 9880022e bgeu r19,r2,100f710 <__sfvwrite_r+0x170> + 100f708: 1027883a mov r19,r2 + 100f70c: 100d883a mov r6,r2 + 100f710: 3881000c andi r2,r7,1024 + 100f714: 1000b826 beq r2,zero,100f9f8 <__sfvwrite_r+0x458> + 100f718: 300b883a mov r5,r6 + 100f71c: e009883a mov r4,fp + 100f720: 100a1a40 call 100a1a4 <_malloc_r> + 100f724: 10003126 beq r2,zero,100f7ec <__sfvwrite_r+0x24c> + 100f728: 91400417 ldw r5,16(r18) + 100f72c: 1009883a mov r4,r2 + 100f730: 800d883a mov r6,r16 + 100f734: 1023883a mov r17,r2 + 100f738: 100aa3c0 call 100aa3c + 100f73c: 90c0030b ldhu r3,12(r18) + 100f740: 00beffc4 movi r2,-1025 + 100f744: 1886703a and r3,r3,r2 + 100f748: 18c02014 ori r3,r3,128 + 100f74c: 90c0030d sth r3,12(r18) + 100f750: 9c07c83a sub r3,r19,r16 + 100f754: 8c05883a add r2,r17,r16 + 100f758: a00d883a mov r6,r20 + 100f75c: a021883a mov r16,r20 + 100f760: 90800015 stw r2,0(r18) + 100f764: 90c00215 stw r3,8(r18) + 100f768: 94400415 stw r17,16(r18) + 100f76c: 94c00515 stw r19,20(r18) + 100f770: 91000017 ldw r4,0(r18) + 100f774: b80b883a mov r5,r23 + 100f778: a023883a mov r17,r20 + 100f77c: 100aadc0 call 100aadc + 100f780: 90c00217 ldw r3,8(r18) + 100f784: 90800017 ldw r2,0(r18) + 100f788: a027883a mov r19,r20 + 100f78c: 1c07c83a sub r3,r3,r16 + 100f790: 1405883a add r2,r2,r16 + 100f794: 90c00215 stw r3,8(r18) + 100f798: a021883a mov r16,r20 + 100f79c: 90800015 stw r2,0(r18) + 100f7a0: b0800217 ldw r2,8(r22) + 100f7a4: 1405c83a sub r2,r2,r16 + 100f7a8: b0800215 stw r2,8(r22) + 100f7ac: 103fa826 beq r2,zero,100f650 <__sfvwrite_r+0xb0> + 100f7b0: a469c83a sub r20,r20,r17 + 100f7b4: 91c0030b ldhu r7,12(r18) + 100f7b8: bcef883a add r23,r23,r19 + 100f7bc: a03fbe1e bne r20,zero,100f6b8 <__sfvwrite_r+0x118> + 100f7c0: adc00017 ldw r23,0(r21) + 100f7c4: ad000117 ldw r20,4(r21) + 100f7c8: ad400204 addi r21,r21,8 + 100f7cc: 003fb906 br 100f6b4 <__sfvwrite_r+0x114> + 100f7d0: ac400017 ldw r17,0(r21) + 100f7d4: ac000117 ldw r16,4(r21) + 100f7d8: ad400204 addi r21,r21,8 + 100f7dc: 003f8a06 br 100f608 <__sfvwrite_r+0x68> + 100f7e0: 91400417 ldw r5,16(r18) + 100f7e4: e009883a mov r4,fp + 100f7e8: 100f28c0 call 100f28c <_free_r> + 100f7ec: 00800304 movi r2,12 + 100f7f0: e0800015 stw r2,0(fp) + 100f7f4: 9080030b ldhu r2,12(r18) + 100f7f8: 013fffc4 movi r4,-1 + 100f7fc: 10801014 ori r2,r2,64 + 100f800: 9080030d sth r2,12(r18) + 100f804: 003f9306 br 100f654 <__sfvwrite_r+0xb4> + 100f808: 0027883a mov r19,zero + 100f80c: 002f883a mov r23,zero + 100f810: d8000015 stw zero,0(sp) + 100f814: 0029883a mov r20,zero + 100f818: 98001e26 beq r19,zero,100f894 <__sfvwrite_r+0x2f4> + 100f81c: d8c00017 ldw r3,0(sp) + 100f820: 1804c03a cmpne r2,r3,zero + 100f824: 10005e26 beq r2,zero,100f9a0 <__sfvwrite_r+0x400> + 100f828: 9821883a mov r16,r19 + 100f82c: a4c0012e bgeu r20,r19,100f834 <__sfvwrite_r+0x294> + 100f830: a021883a mov r16,r20 + 100f834: 91000017 ldw r4,0(r18) + 100f838: 90800417 ldw r2,16(r18) + 100f83c: 91800217 ldw r6,8(r18) + 100f840: 91c00517 ldw r7,20(r18) + 100f844: 1100022e bgeu r2,r4,100f850 <__sfvwrite_r+0x2b0> + 100f848: 31e3883a add r17,r6,r7 + 100f84c: 8c001616 blt r17,r16,100f8a8 <__sfvwrite_r+0x308> + 100f850: 81c03816 blt r16,r7,100f934 <__sfvwrite_r+0x394> + 100f854: 90c00917 ldw r3,36(r18) + 100f858: 91400717 ldw r5,28(r18) + 100f85c: e009883a mov r4,fp + 100f860: b80d883a mov r6,r23 + 100f864: 183ee83a callr r3 + 100f868: 1023883a mov r17,r2 + 100f86c: 00bfe10e bge zero,r2,100f7f4 <__sfvwrite_r+0x254> + 100f870: a469c83a sub r20,r20,r17 + 100f874: a0001826 beq r20,zero,100f8d8 <__sfvwrite_r+0x338> + 100f878: b0800217 ldw r2,8(r22) + 100f87c: 1445c83a sub r2,r2,r17 + 100f880: b0800215 stw r2,8(r22) + 100f884: 103f7226 beq r2,zero,100f650 <__sfvwrite_r+0xb0> + 100f888: 9c67c83a sub r19,r19,r17 + 100f88c: bc6f883a add r23,r23,r17 + 100f890: 983fe21e bne r19,zero,100f81c <__sfvwrite_r+0x27c> + 100f894: adc00017 ldw r23,0(r21) + 100f898: acc00117 ldw r19,4(r21) + 100f89c: ad400204 addi r21,r21,8 + 100f8a0: d8000015 stw zero,0(sp) + 100f8a4: 003fdc06 br 100f818 <__sfvwrite_r+0x278> + 100f8a8: b80b883a mov r5,r23 + 100f8ac: 880d883a mov r6,r17 + 100f8b0: 100aadc0 call 100aadc + 100f8b4: 90c00017 ldw r3,0(r18) + 100f8b8: e009883a mov r4,fp + 100f8bc: 900b883a mov r5,r18 + 100f8c0: 1c47883a add r3,r3,r17 + 100f8c4: 90c00015 stw r3,0(r18) + 100f8c8: 100ec700 call 100ec70 <_fflush_r> + 100f8cc: 103fc91e bne r2,zero,100f7f4 <__sfvwrite_r+0x254> + 100f8d0: a469c83a sub r20,r20,r17 + 100f8d4: a03fe81e bne r20,zero,100f878 <__sfvwrite_r+0x2d8> + 100f8d8: e009883a mov r4,fp + 100f8dc: 900b883a mov r5,r18 + 100f8e0: 100ec700 call 100ec70 <_fflush_r> + 100f8e4: 103fc31e bne r2,zero,100f7f4 <__sfvwrite_r+0x254> + 100f8e8: d8000015 stw zero,0(sp) + 100f8ec: 003fe206 br 100f878 <__sfvwrite_r+0x2d8> + 100f8f0: 91000017 ldw r4,0(r18) + 100f8f4: 90800417 ldw r2,16(r18) + 100f8f8: 1100022e bgeu r2,r4,100f904 <__sfvwrite_r+0x364> + 100f8fc: 8023883a mov r17,r16 + 100f900: 85003136 bltu r16,r20,100f9c8 <__sfvwrite_r+0x428> + 100f904: 91c00517 ldw r7,20(r18) + 100f908: a1c01836 bltu r20,r7,100f96c <__sfvwrite_r+0x3cc> + 100f90c: 90c00917 ldw r3,36(r18) + 100f910: 91400717 ldw r5,28(r18) + 100f914: e009883a mov r4,fp + 100f918: b80d883a mov r6,r23 + 100f91c: 183ee83a callr r3 + 100f920: 1021883a mov r16,r2 + 100f924: 00bfb30e bge zero,r2,100f7f4 <__sfvwrite_r+0x254> + 100f928: 1023883a mov r17,r2 + 100f92c: 1027883a mov r19,r2 + 100f930: 003f9b06 br 100f7a0 <__sfvwrite_r+0x200> + 100f934: b80b883a mov r5,r23 + 100f938: 800d883a mov r6,r16 + 100f93c: 100aadc0 call 100aadc + 100f940: 90c00217 ldw r3,8(r18) + 100f944: 90800017 ldw r2,0(r18) + 100f948: 8023883a mov r17,r16 + 100f94c: 1c07c83a sub r3,r3,r16 + 100f950: 1405883a add r2,r2,r16 + 100f954: 90c00215 stw r3,8(r18) + 100f958: 90800015 stw r2,0(r18) + 100f95c: 003fc406 br 100f870 <__sfvwrite_r+0x2d0> + 100f960: a00d883a mov r6,r20 + 100f964: a021883a mov r16,r20 + 100f968: 003f8106 br 100f770 <__sfvwrite_r+0x1d0> + 100f96c: b80b883a mov r5,r23 + 100f970: a00d883a mov r6,r20 + 100f974: 100aadc0 call 100aadc + 100f978: 90c00217 ldw r3,8(r18) + 100f97c: 90800017 ldw r2,0(r18) + 100f980: a021883a mov r16,r20 + 100f984: 1d07c83a sub r3,r3,r20 + 100f988: 1505883a add r2,r2,r20 + 100f98c: a023883a mov r17,r20 + 100f990: a027883a mov r19,r20 + 100f994: 90c00215 stw r3,8(r18) + 100f998: 90800015 stw r2,0(r18) + 100f99c: 003f8006 br 100f7a0 <__sfvwrite_r+0x200> + 100f9a0: b809883a mov r4,r23 + 100f9a4: 01400284 movi r5,10 + 100f9a8: 980d883a mov r6,r19 + 100f9ac: 100a8e40 call 100a8e4 + 100f9b0: 10001726 beq r2,zero,100fa10 <__sfvwrite_r+0x470> + 100f9b4: 15c5c83a sub r2,r2,r23 + 100f9b8: 15000044 addi r20,r2,1 + 100f9bc: 00800044 movi r2,1 + 100f9c0: d8800015 stw r2,0(sp) + 100f9c4: 003f9806 br 100f828 <__sfvwrite_r+0x288> + 100f9c8: b80b883a mov r5,r23 + 100f9cc: 800d883a mov r6,r16 + 100f9d0: 100aadc0 call 100aadc + 100f9d4: 90c00017 ldw r3,0(r18) + 100f9d8: e009883a mov r4,fp + 100f9dc: 900b883a mov r5,r18 + 100f9e0: 1c07883a add r3,r3,r16 + 100f9e4: 90c00015 stw r3,0(r18) + 100f9e8: 8027883a mov r19,r16 + 100f9ec: 100ec700 call 100ec70 <_fflush_r> + 100f9f0: 103f6b26 beq r2,zero,100f7a0 <__sfvwrite_r+0x200> + 100f9f4: 003f7f06 br 100f7f4 <__sfvwrite_r+0x254> + 100f9f8: 400b883a mov r5,r8 + 100f9fc: e009883a mov r4,fp + 100fa00: 1010ff40 call 1010ff4 <_realloc_r> + 100fa04: 103f7626 beq r2,zero,100f7e0 <__sfvwrite_r+0x240> + 100fa08: 1023883a mov r17,r2 + 100fa0c: 003f5006 br 100f750 <__sfvwrite_r+0x1b0> + 100fa10: 00c00044 movi r3,1 + 100fa14: 9d000044 addi r20,r19,1 + 100fa18: d8c00015 stw r3,0(sp) + 100fa1c: 003f8206 br 100f828 <__sfvwrite_r+0x288> + 100fa20: 9080030b ldhu r2,12(r18) + 100fa24: 00c00244 movi r3,9 + 100fa28: 013fffc4 movi r4,-1 + 100fa2c: 10801014 ori r2,r2,64 + 100fa30: 9080030d sth r2,12(r18) + 100fa34: e0c00015 stw r3,0(fp) + 100fa38: 003f0606 br 100f654 <__sfvwrite_r+0xb4> + +0100fa3c <_fwalk_reent>: + 100fa3c: defff704 addi sp,sp,-36 + 100fa40: dcc00315 stw r19,12(sp) + 100fa44: 24c0b804 addi r19,r4,736 + 100fa48: dd800615 stw r22,24(sp) + 100fa4c: dd400515 stw r21,20(sp) + 100fa50: dfc00815 stw ra,32(sp) + 100fa54: ddc00715 stw r23,28(sp) + 100fa58: dd000415 stw r20,16(sp) + 100fa5c: dc800215 stw r18,8(sp) + 100fa60: dc400115 stw r17,4(sp) + 100fa64: dc000015 stw r16,0(sp) + 100fa68: 202b883a mov r21,r4 + 100fa6c: 282d883a mov r22,r5 + 100fa70: 100eef80 call 100eef8 <__sfp_lock_acquire> + 100fa74: 98002126 beq r19,zero,100fafc <_fwalk_reent+0xc0> + 100fa78: 002f883a mov r23,zero + 100fa7c: 9c800117 ldw r18,4(r19) + 100fa80: 9c000217 ldw r16,8(r19) + 100fa84: 90bfffc4 addi r2,r18,-1 + 100fa88: 10000d16 blt r2,zero,100fac0 <_fwalk_reent+0x84> + 100fa8c: 0023883a mov r17,zero + 100fa90: 053fffc4 movi r20,-1 + 100fa94: 8080030f ldh r2,12(r16) + 100fa98: 8c400044 addi r17,r17,1 + 100fa9c: 10000626 beq r2,zero,100fab8 <_fwalk_reent+0x7c> + 100faa0: 8080038f ldh r2,14(r16) + 100faa4: 800b883a mov r5,r16 + 100faa8: a809883a mov r4,r21 + 100faac: 15000226 beq r2,r20,100fab8 <_fwalk_reent+0x7c> + 100fab0: b03ee83a callr r22 + 100fab4: b8aeb03a or r23,r23,r2 + 100fab8: 84001704 addi r16,r16,92 + 100fabc: 947ff51e bne r18,r17,100fa94 <_fwalk_reent+0x58> + 100fac0: 9cc00017 ldw r19,0(r19) + 100fac4: 983fed1e bne r19,zero,100fa7c <_fwalk_reent+0x40> + 100fac8: 100eefc0 call 100eefc <__sfp_lock_release> + 100facc: b805883a mov r2,r23 + 100fad0: dfc00817 ldw ra,32(sp) + 100fad4: ddc00717 ldw r23,28(sp) + 100fad8: dd800617 ldw r22,24(sp) + 100fadc: dd400517 ldw r21,20(sp) + 100fae0: dd000417 ldw r20,16(sp) + 100fae4: dcc00317 ldw r19,12(sp) + 100fae8: dc800217 ldw r18,8(sp) + 100faec: dc400117 ldw r17,4(sp) + 100faf0: dc000017 ldw r16,0(sp) + 100faf4: dec00904 addi sp,sp,36 + 100faf8: f800283a ret + 100fafc: 002f883a mov r23,zero + 100fb00: 003ff106 br 100fac8 <_fwalk_reent+0x8c> + +0100fb04 <_fwalk>: + 100fb04: defff804 addi sp,sp,-32 + 100fb08: dcc00315 stw r19,12(sp) + 100fb0c: 24c0b804 addi r19,r4,736 + 100fb10: dd400515 stw r21,20(sp) + 100fb14: dfc00715 stw ra,28(sp) + 100fb18: dd800615 stw r22,24(sp) + 100fb1c: dd000415 stw r20,16(sp) + 100fb20: dc800215 stw r18,8(sp) + 100fb24: dc400115 stw r17,4(sp) + 100fb28: dc000015 stw r16,0(sp) + 100fb2c: 282b883a mov r21,r5 + 100fb30: 100eef80 call 100eef8 <__sfp_lock_acquire> + 100fb34: 98001f26 beq r19,zero,100fbb4 <_fwalk+0xb0> + 100fb38: 002d883a mov r22,zero + 100fb3c: 9c800117 ldw r18,4(r19) + 100fb40: 9c000217 ldw r16,8(r19) + 100fb44: 90bfffc4 addi r2,r18,-1 + 100fb48: 10000c16 blt r2,zero,100fb7c <_fwalk+0x78> + 100fb4c: 0023883a mov r17,zero + 100fb50: 053fffc4 movi r20,-1 + 100fb54: 8080030f ldh r2,12(r16) + 100fb58: 8c400044 addi r17,r17,1 + 100fb5c: 10000526 beq r2,zero,100fb74 <_fwalk+0x70> + 100fb60: 8080038f ldh r2,14(r16) + 100fb64: 8009883a mov r4,r16 + 100fb68: 15000226 beq r2,r20,100fb74 <_fwalk+0x70> + 100fb6c: a83ee83a callr r21 + 100fb70: b0acb03a or r22,r22,r2 + 100fb74: 84001704 addi r16,r16,92 + 100fb78: 947ff61e bne r18,r17,100fb54 <_fwalk+0x50> + 100fb7c: 9cc00017 ldw r19,0(r19) + 100fb80: 983fee1e bne r19,zero,100fb3c <_fwalk+0x38> + 100fb84: 100eefc0 call 100eefc <__sfp_lock_release> + 100fb88: b005883a mov r2,r22 + 100fb8c: dfc00717 ldw ra,28(sp) + 100fb90: dd800617 ldw r22,24(sp) + 100fb94: dd400517 ldw r21,20(sp) + 100fb98: dd000417 ldw r20,16(sp) + 100fb9c: dcc00317 ldw r19,12(sp) + 100fba0: dc800217 ldw r18,8(sp) + 100fba4: dc400117 ldw r17,4(sp) + 100fba8: dc000017 ldw r16,0(sp) + 100fbac: dec00804 addi sp,sp,32 + 100fbb0: f800283a ret + 100fbb4: 002d883a mov r22,zero + 100fbb8: 003ff206 br 100fb84 <_fwalk+0x80> + +0100fbbc <__locale_charset>: + 100fbbc: d0a01217 ldw r2,-32696(gp) + 100fbc0: f800283a ret + +0100fbc4 <_localeconv_r>: + 100fbc4: 008040b4 movhi r2,258 + 100fbc8: 1085f804 addi r2,r2,6112 + 100fbcc: f800283a ret + +0100fbd0 : + 100fbd0: 008040b4 movhi r2,258 + 100fbd4: 108dc804 addi r2,r2,14112 + 100fbd8: 11000017 ldw r4,0(r2) + 100fbdc: 100fbc41 jmpi 100fbc4 <_localeconv_r> + +0100fbe0 <_setlocale_r>: + 100fbe0: defffc04 addi sp,sp,-16 + 100fbe4: 00c040b4 movhi r3,258 + 100fbe8: 18c5f304 addi r3,r3,6092 + 100fbec: dc800215 stw r18,8(sp) + 100fbf0: dc400115 stw r17,4(sp) + 100fbf4: dc000015 stw r16,0(sp) + 100fbf8: 2023883a mov r17,r4 + 100fbfc: 2825883a mov r18,r5 + 100fc00: dfc00315 stw ra,12(sp) + 100fc04: 3021883a mov r16,r6 + 100fc08: 3009883a mov r4,r6 + 100fc0c: 180b883a mov r5,r3 + 100fc10: 30000926 beq r6,zero,100fc38 <_setlocale_r+0x58> + 100fc14: 10117a40 call 10117a4 + 100fc18: 8009883a mov r4,r16 + 100fc1c: 014040b4 movhi r5,258 + 100fc20: 29453e04 addi r5,r5,5368 + 100fc24: 10000b1e bne r2,zero,100fc54 <_setlocale_r+0x74> + 100fc28: 8c000d15 stw r16,52(r17) + 100fc2c: 8c800c15 stw r18,48(r17) + 100fc30: 00c040b4 movhi r3,258 + 100fc34: 18c5f304 addi r3,r3,6092 + 100fc38: 1805883a mov r2,r3 + 100fc3c: dfc00317 ldw ra,12(sp) + 100fc40: dc800217 ldw r18,8(sp) + 100fc44: dc400117 ldw r17,4(sp) + 100fc48: dc000017 ldw r16,0(sp) + 100fc4c: dec00404 addi sp,sp,16 + 100fc50: f800283a ret + 100fc54: 10117a40 call 10117a4 + 100fc58: 0007883a mov r3,zero + 100fc5c: 103ff226 beq r2,zero,100fc28 <_setlocale_r+0x48> + 100fc60: 003ff506 br 100fc38 <_setlocale_r+0x58> + +0100fc64 : + 100fc64: 018040b4 movhi r6,258 + 100fc68: 318dc804 addi r6,r6,14112 + 100fc6c: 2007883a mov r3,r4 + 100fc70: 31000017 ldw r4,0(r6) + 100fc74: 280d883a mov r6,r5 + 100fc78: 180b883a mov r5,r3 + 100fc7c: 100fbe01 jmpi 100fbe0 <_setlocale_r> + +0100fc80 <__smakebuf_r>: + 100fc80: 2880030b ldhu r2,12(r5) + 100fc84: deffed04 addi sp,sp,-76 + 100fc88: dc401015 stw r17,64(sp) + 100fc8c: 1080008c andi r2,r2,2 + 100fc90: dc000f15 stw r16,60(sp) + 100fc94: dfc01215 stw ra,72(sp) + 100fc98: dc801115 stw r18,68(sp) + 100fc9c: 2821883a mov r16,r5 + 100fca0: 2023883a mov r17,r4 + 100fca4: 10000b26 beq r2,zero,100fcd4 <__smakebuf_r+0x54> + 100fca8: 28c010c4 addi r3,r5,67 + 100fcac: 00800044 movi r2,1 + 100fcb0: 28800515 stw r2,20(r5) + 100fcb4: 28c00415 stw r3,16(r5) + 100fcb8: 28c00015 stw r3,0(r5) + 100fcbc: dfc01217 ldw ra,72(sp) + 100fcc0: dc801117 ldw r18,68(sp) + 100fcc4: dc401017 ldw r17,64(sp) + 100fcc8: dc000f17 ldw r16,60(sp) + 100fccc: dec01304 addi sp,sp,76 + 100fcd0: f800283a ret + 100fcd4: 2940038f ldh r5,14(r5) + 100fcd8: 28002116 blt r5,zero,100fd60 <__smakebuf_r+0xe0> + 100fcdc: d80d883a mov r6,sp + 100fce0: 1011c6c0 call 1011c6c <_fstat_r> + 100fce4: 10001e16 blt r2,zero,100fd60 <__smakebuf_r+0xe0> + 100fce8: d8800117 ldw r2,4(sp) + 100fcec: 00e00014 movui r3,32768 + 100fcf0: 113c000c andi r4,r2,61440 + 100fcf4: 20c03126 beq r4,r3,100fdbc <__smakebuf_r+0x13c> + 100fcf8: 8080030b ldhu r2,12(r16) + 100fcfc: 00c80004 movi r3,8192 + 100fd00: 10820014 ori r2,r2,2048 + 100fd04: 8080030d sth r2,12(r16) + 100fd08: 20c01e26 beq r4,r3,100fd84 <__smakebuf_r+0x104> + 100fd0c: 04810004 movi r18,1024 + 100fd10: 8809883a mov r4,r17 + 100fd14: 900b883a mov r5,r18 + 100fd18: 100a1a40 call 100a1a4 <_malloc_r> + 100fd1c: 1009883a mov r4,r2 + 100fd20: 10003126 beq r2,zero,100fde8 <__smakebuf_r+0x168> + 100fd24: 80c0030b ldhu r3,12(r16) + 100fd28: 00804074 movhi r2,257 + 100fd2c: 10bbfb04 addi r2,r2,-4116 + 100fd30: 88800f15 stw r2,60(r17) + 100fd34: 18c02014 ori r3,r3,128 + 100fd38: 84800515 stw r18,20(r16) + 100fd3c: 80c0030d sth r3,12(r16) + 100fd40: 81000415 stw r4,16(r16) + 100fd44: 81000015 stw r4,0(r16) + 100fd48: dfc01217 ldw ra,72(sp) + 100fd4c: dc801117 ldw r18,68(sp) + 100fd50: dc401017 ldw r17,64(sp) + 100fd54: dc000f17 ldw r16,60(sp) + 100fd58: dec01304 addi sp,sp,76 + 100fd5c: f800283a ret + 100fd60: 80c0030b ldhu r3,12(r16) + 100fd64: 1880200c andi r2,r3,128 + 100fd68: 10000426 beq r2,zero,100fd7c <__smakebuf_r+0xfc> + 100fd6c: 04801004 movi r18,64 + 100fd70: 18820014 ori r2,r3,2048 + 100fd74: 8080030d sth r2,12(r16) + 100fd78: 003fe506 br 100fd10 <__smakebuf_r+0x90> + 100fd7c: 04810004 movi r18,1024 + 100fd80: 003ffb06 br 100fd70 <__smakebuf_r+0xf0> + 100fd84: 8140038f ldh r5,14(r16) + 100fd88: 8809883a mov r4,r17 + 100fd8c: 1011ce00 call 1011ce0 <_isatty_r> + 100fd90: 103fde26 beq r2,zero,100fd0c <__smakebuf_r+0x8c> + 100fd94: 8080030b ldhu r2,12(r16) + 100fd98: 80c010c4 addi r3,r16,67 + 100fd9c: 04810004 movi r18,1024 + 100fda0: 10800054 ori r2,r2,1 + 100fda4: 8080030d sth r2,12(r16) + 100fda8: 00800044 movi r2,1 + 100fdac: 80c00415 stw r3,16(r16) + 100fdb0: 80800515 stw r2,20(r16) + 100fdb4: 80c00015 stw r3,0(r16) + 100fdb8: 003fd506 br 100fd10 <__smakebuf_r+0x90> + 100fdbc: 80c00a17 ldw r3,40(r16) + 100fdc0: 00804074 movhi r2,257 + 100fdc4: 10859804 addi r2,r2,5728 + 100fdc8: 18bfcb1e bne r3,r2,100fcf8 <__smakebuf_r+0x78> + 100fdcc: 8080030b ldhu r2,12(r16) + 100fdd0: 00c10004 movi r3,1024 + 100fdd4: 1825883a mov r18,r3 + 100fdd8: 10c4b03a or r2,r2,r3 + 100fddc: 8080030d sth r2,12(r16) + 100fde0: 80c01315 stw r3,76(r16) + 100fde4: 003fca06 br 100fd10 <__smakebuf_r+0x90> + 100fde8: 8100030b ldhu r4,12(r16) + 100fdec: 2080800c andi r2,r4,512 + 100fdf0: 103fb21e bne r2,zero,100fcbc <__smakebuf_r+0x3c> + 100fdf4: 80c010c4 addi r3,r16,67 + 100fdf8: 21000094 ori r4,r4,2 + 100fdfc: 00800044 movi r2,1 + 100fe00: 80800515 stw r2,20(r16) + 100fe04: 8100030d sth r4,12(r16) + 100fe08: 80c00415 stw r3,16(r16) + 100fe0c: 80c00015 stw r3,0(r16) + 100fe10: 003faa06 br 100fcbc <__smakebuf_r+0x3c> + +0100fe14 <_Bfree>: + 100fe14: 28000826 beq r5,zero,100fe38 <_Bfree+0x24> + 100fe18: 28800117 ldw r2,4(r5) + 100fe1c: 21001317 ldw r4,76(r4) + 100fe20: 1085883a add r2,r2,r2 + 100fe24: 1085883a add r2,r2,r2 + 100fe28: 1105883a add r2,r2,r4 + 100fe2c: 10c00017 ldw r3,0(r2) + 100fe30: 28c00015 stw r3,0(r5) + 100fe34: 11400015 stw r5,0(r2) + 100fe38: f800283a ret + +0100fe3c <__hi0bits>: + 100fe3c: 20bfffec andhi r2,r4,65535 + 100fe40: 10001426 beq r2,zero,100fe94 <__hi0bits+0x58> + 100fe44: 0007883a mov r3,zero + 100fe48: 20bfc02c andhi r2,r4,65280 + 100fe4c: 1000021e bne r2,zero,100fe58 <__hi0bits+0x1c> + 100fe50: 2008923a slli r4,r4,8 + 100fe54: 18c00204 addi r3,r3,8 + 100fe58: 20bc002c andhi r2,r4,61440 + 100fe5c: 1000021e bne r2,zero,100fe68 <__hi0bits+0x2c> + 100fe60: 2008913a slli r4,r4,4 + 100fe64: 18c00104 addi r3,r3,4 + 100fe68: 20b0002c andhi r2,r4,49152 + 100fe6c: 1000031e bne r2,zero,100fe7c <__hi0bits+0x40> + 100fe70: 2105883a add r2,r4,r4 + 100fe74: 18c00084 addi r3,r3,2 + 100fe78: 1089883a add r4,r2,r2 + 100fe7c: 20000316 blt r4,zero,100fe8c <__hi0bits+0x50> + 100fe80: 2090002c andhi r2,r4,16384 + 100fe84: 10000626 beq r2,zero,100fea0 <__hi0bits+0x64> + 100fe88: 18c00044 addi r3,r3,1 + 100fe8c: 1805883a mov r2,r3 + 100fe90: f800283a ret + 100fe94: 2008943a slli r4,r4,16 + 100fe98: 00c00404 movi r3,16 + 100fe9c: 003fea06 br 100fe48 <__hi0bits+0xc> + 100fea0: 00c00804 movi r3,32 + 100fea4: 1805883a mov r2,r3 + 100fea8: f800283a ret + +0100feac <__lo0bits>: + 100feac: 20c00017 ldw r3,0(r4) + 100feb0: 188001cc andi r2,r3,7 + 100feb4: 10000a26 beq r2,zero,100fee0 <__lo0bits+0x34> + 100feb8: 1880004c andi r2,r3,1 + 100febc: 1005003a cmpeq r2,r2,zero + 100fec0: 10002126 beq r2,zero,100ff48 <__lo0bits+0x9c> + 100fec4: 1880008c andi r2,r3,2 + 100fec8: 1000251e bne r2,zero,100ff60 <__lo0bits+0xb4> + 100fecc: 1804d0ba srli r2,r3,2 + 100fed0: 01400084 movi r5,2 + 100fed4: 20800015 stw r2,0(r4) + 100fed8: 2805883a mov r2,r5 + 100fedc: f800283a ret + 100fee0: 18bfffcc andi r2,r3,65535 + 100fee4: 10001526 beq r2,zero,100ff3c <__lo0bits+0x90> + 100fee8: 000b883a mov r5,zero + 100feec: 18803fcc andi r2,r3,255 + 100fef0: 1000021e bne r2,zero,100fefc <__lo0bits+0x50> + 100fef4: 1806d23a srli r3,r3,8 + 100fef8: 29400204 addi r5,r5,8 + 100fefc: 188003cc andi r2,r3,15 + 100ff00: 1000021e bne r2,zero,100ff0c <__lo0bits+0x60> + 100ff04: 1806d13a srli r3,r3,4 + 100ff08: 29400104 addi r5,r5,4 + 100ff0c: 188000cc andi r2,r3,3 + 100ff10: 1000021e bne r2,zero,100ff1c <__lo0bits+0x70> + 100ff14: 1806d0ba srli r3,r3,2 + 100ff18: 29400084 addi r5,r5,2 + 100ff1c: 1880004c andi r2,r3,1 + 100ff20: 1000031e bne r2,zero,100ff30 <__lo0bits+0x84> + 100ff24: 1806d07a srli r3,r3,1 + 100ff28: 18000a26 beq r3,zero,100ff54 <__lo0bits+0xa8> + 100ff2c: 29400044 addi r5,r5,1 + 100ff30: 2805883a mov r2,r5 + 100ff34: 20c00015 stw r3,0(r4) + 100ff38: f800283a ret + 100ff3c: 1806d43a srli r3,r3,16 + 100ff40: 01400404 movi r5,16 + 100ff44: 003fe906 br 100feec <__lo0bits+0x40> + 100ff48: 000b883a mov r5,zero + 100ff4c: 2805883a mov r2,r5 + 100ff50: f800283a ret + 100ff54: 01400804 movi r5,32 + 100ff58: 2805883a mov r2,r5 + 100ff5c: f800283a ret + 100ff60: 1804d07a srli r2,r3,1 + 100ff64: 01400044 movi r5,1 + 100ff68: 20800015 stw r2,0(r4) + 100ff6c: 003fda06 br 100fed8 <__lo0bits+0x2c> + +0100ff70 <__mcmp>: + 100ff70: 20800417 ldw r2,16(r4) + 100ff74: 28c00417 ldw r3,16(r5) + 100ff78: 10cfc83a sub r7,r2,r3 + 100ff7c: 38000c1e bne r7,zero,100ffb0 <__mcmp+0x40> + 100ff80: 18c5883a add r2,r3,r3 + 100ff84: 1085883a add r2,r2,r2 + 100ff88: 10c00504 addi r3,r2,20 + 100ff8c: 21000504 addi r4,r4,20 + 100ff90: 28cb883a add r5,r5,r3 + 100ff94: 2085883a add r2,r4,r2 + 100ff98: 10bfff04 addi r2,r2,-4 + 100ff9c: 297fff04 addi r5,r5,-4 + 100ffa0: 11800017 ldw r6,0(r2) + 100ffa4: 28c00017 ldw r3,0(r5) + 100ffa8: 30c0031e bne r6,r3,100ffb8 <__mcmp+0x48> + 100ffac: 20bffa36 bltu r4,r2,100ff98 <__mcmp+0x28> + 100ffb0: 3805883a mov r2,r7 + 100ffb4: f800283a ret + 100ffb8: 30c00336 bltu r6,r3,100ffc8 <__mcmp+0x58> + 100ffbc: 01c00044 movi r7,1 + 100ffc0: 3805883a mov r2,r7 + 100ffc4: f800283a ret + 100ffc8: 01ffffc4 movi r7,-1 + 100ffcc: 003ff806 br 100ffb0 <__mcmp+0x40> + +0100ffd0 <__ulp>: + 100ffd0: 295ffc2c andhi r5,r5,32752 + 100ffd4: 013f3034 movhi r4,64704 + 100ffd8: 290b883a add r5,r5,r4 + 100ffdc: 0145c83a sub r2,zero,r5 + 100ffe0: 1007d53a srai r3,r2,20 + 100ffe4: 000d883a mov r6,zero + 100ffe8: 0140040e bge zero,r5,100fffc <__ulp+0x2c> + 100ffec: 280f883a mov r7,r5 + 100fff0: 3807883a mov r3,r7 + 100fff4: 3005883a mov r2,r6 + 100fff8: f800283a ret + 100fffc: 008004c4 movi r2,19 + 1010000: 193ffb04 addi r4,r3,-20 + 1010004: 10c00c0e bge r2,r3,1010038 <__ulp+0x68> + 1010008: 008007c4 movi r2,31 + 101000c: 1107c83a sub r3,r2,r4 + 1010010: 00800784 movi r2,30 + 1010014: 01400044 movi r5,1 + 1010018: 11000216 blt r2,r4,1010024 <__ulp+0x54> + 101001c: 00800044 movi r2,1 + 1010020: 10ca983a sll r5,r2,r3 + 1010024: 000f883a mov r7,zero + 1010028: 280d883a mov r6,r5 + 101002c: 3807883a mov r3,r7 + 1010030: 3005883a mov r2,r6 + 1010034: f800283a ret + 1010038: 00800234 movhi r2,8 + 101003c: 10cfd83a sra r7,r2,r3 + 1010040: 000d883a mov r6,zero + 1010044: 3005883a mov r2,r6 + 1010048: 3807883a mov r3,r7 + 101004c: f800283a ret + +01010050 <__b2d>: + 1010050: 20800417 ldw r2,16(r4) + 1010054: defff904 addi sp,sp,-28 + 1010058: dd000415 stw r20,16(sp) + 101005c: 1085883a add r2,r2,r2 + 1010060: 25000504 addi r20,r4,20 + 1010064: 1085883a add r2,r2,r2 + 1010068: dc000015 stw r16,0(sp) + 101006c: a0a1883a add r16,r20,r2 + 1010070: dd400515 stw r21,20(sp) + 1010074: 857fff17 ldw r21,-4(r16) + 1010078: dc400115 stw r17,4(sp) + 101007c: dfc00615 stw ra,24(sp) + 1010080: a809883a mov r4,r21 + 1010084: 2823883a mov r17,r5 + 1010088: dcc00315 stw r19,12(sp) + 101008c: dc800215 stw r18,8(sp) + 1010090: 100fe3c0 call 100fe3c <__hi0bits> + 1010094: 100b883a mov r5,r2 + 1010098: 00800804 movi r2,32 + 101009c: 1145c83a sub r2,r2,r5 + 10100a0: 88800015 stw r2,0(r17) + 10100a4: 00800284 movi r2,10 + 10100a8: 80ffff04 addi r3,r16,-4 + 10100ac: 11401416 blt r2,r5,1010100 <__b2d+0xb0> + 10100b0: 008002c4 movi r2,11 + 10100b4: 1149c83a sub r4,r2,r5 + 10100b8: a0c02736 bltu r20,r3,1010158 <__b2d+0x108> + 10100bc: 000d883a mov r6,zero + 10100c0: 28800544 addi r2,r5,21 + 10100c4: a906d83a srl r3,r21,r4 + 10100c8: a884983a sll r2,r21,r2 + 10100cc: 1ccffc34 orhi r19,r3,16368 + 10100d0: 11a4b03a or r18,r2,r6 + 10100d4: 9005883a mov r2,r18 + 10100d8: 9807883a mov r3,r19 + 10100dc: dfc00617 ldw ra,24(sp) + 10100e0: dd400517 ldw r21,20(sp) + 10100e4: dd000417 ldw r20,16(sp) + 10100e8: dcc00317 ldw r19,12(sp) + 10100ec: dc800217 ldw r18,8(sp) + 10100f0: dc400117 ldw r17,4(sp) + 10100f4: dc000017 ldw r16,0(sp) + 10100f8: dec00704 addi sp,sp,28 + 10100fc: f800283a ret + 1010100: a0c00e36 bltu r20,r3,101013c <__b2d+0xec> + 1010104: 293ffd44 addi r4,r5,-11 + 1010108: 000d883a mov r6,zero + 101010c: 20000f26 beq r4,zero,101014c <__b2d+0xfc> + 1010110: 00800804 movi r2,32 + 1010114: 110bc83a sub r5,r2,r4 + 1010118: a0c01236 bltu r20,r3,1010164 <__b2d+0x114> + 101011c: 000f883a mov r7,zero + 1010120: a904983a sll r2,r21,r4 + 1010124: 3146d83a srl r3,r6,r5 + 1010128: 3108983a sll r4,r6,r4 + 101012c: 108ffc34 orhi r2,r2,16368 + 1010130: 18a6b03a or r19,r3,r2 + 1010134: 3924b03a or r18,r7,r4 + 1010138: 003fe606 br 10100d4 <__b2d+0x84> + 101013c: 293ffd44 addi r4,r5,-11 + 1010140: 81bffe17 ldw r6,-8(r16) + 1010144: 80fffe04 addi r3,r16,-8 + 1010148: 203ff11e bne r4,zero,1010110 <__b2d+0xc0> + 101014c: accffc34 orhi r19,r21,16368 + 1010150: 3025883a mov r18,r6 + 1010154: 003fdf06 br 10100d4 <__b2d+0x84> + 1010158: 18bfff17 ldw r2,-4(r3) + 101015c: 110cd83a srl r6,r2,r4 + 1010160: 003fd706 br 10100c0 <__b2d+0x70> + 1010164: 18bfff17 ldw r2,-4(r3) + 1010168: 114ed83a srl r7,r2,r5 + 101016c: 003fec06 br 1010120 <__b2d+0xd0> + +01010170 <__ratio>: + 1010170: defff904 addi sp,sp,-28 + 1010174: dc400215 stw r17,8(sp) + 1010178: 2823883a mov r17,r5 + 101017c: d80b883a mov r5,sp + 1010180: dfc00615 stw ra,24(sp) + 1010184: dd000515 stw r20,20(sp) + 1010188: dcc00415 stw r19,16(sp) + 101018c: dc800315 stw r18,12(sp) + 1010190: 2025883a mov r18,r4 + 1010194: 10100500 call 1010050 <__b2d> + 1010198: 8809883a mov r4,r17 + 101019c: d9400104 addi r5,sp,4 + 10101a0: 1027883a mov r19,r2 + 10101a4: 1829883a mov r20,r3 + 10101a8: 10100500 call 1010050 <__b2d> + 10101ac: 89000417 ldw r4,16(r17) + 10101b0: 91c00417 ldw r7,16(r18) + 10101b4: d9800117 ldw r6,4(sp) + 10101b8: 180b883a mov r5,r3 + 10101bc: 390fc83a sub r7,r7,r4 + 10101c0: 1009883a mov r4,r2 + 10101c4: d8800017 ldw r2,0(sp) + 10101c8: 380e917a slli r7,r7,5 + 10101cc: 2011883a mov r8,r4 + 10101d0: 1185c83a sub r2,r2,r6 + 10101d4: 11c5883a add r2,r2,r7 + 10101d8: 1006953a slli r3,r2,20 + 10101dc: 2813883a mov r9,r5 + 10101e0: 00800d0e bge zero,r2,1010218 <__ratio+0xa8> + 10101e4: 1d29883a add r20,r3,r20 + 10101e8: a00b883a mov r5,r20 + 10101ec: 480f883a mov r7,r9 + 10101f0: 9809883a mov r4,r19 + 10101f4: 400d883a mov r6,r8 + 10101f8: 10132940 call 1013294 <__divdf3> + 10101fc: dfc00617 ldw ra,24(sp) + 1010200: dd000517 ldw r20,20(sp) + 1010204: dcc00417 ldw r19,16(sp) + 1010208: dc800317 ldw r18,12(sp) + 101020c: dc400217 ldw r17,8(sp) + 1010210: dec00704 addi sp,sp,28 + 1010214: f800283a ret + 1010218: 28d3c83a sub r9,r5,r3 + 101021c: 003ff206 br 10101e8 <__ratio+0x78> + +01010220 <_mprec_log10>: + 1010220: defffe04 addi sp,sp,-8 + 1010224: 008005c4 movi r2,23 + 1010228: dc000015 stw r16,0(sp) + 101022c: dfc00115 stw ra,4(sp) + 1010230: 2021883a mov r16,r4 + 1010234: 11000c16 blt r2,r4,1010268 <_mprec_log10+0x48> + 1010238: 200490fa slli r2,r4,3 + 101023c: 00c040b4 movhi r3,258 + 1010240: 18c60404 addi r3,r3,6160 + 1010244: 10c5883a add r2,r2,r3 + 1010248: 12400117 ldw r9,4(r2) + 101024c: 12000017 ldw r8,0(r2) + 1010250: 4807883a mov r3,r9 + 1010254: 4005883a mov r2,r8 + 1010258: dfc00117 ldw ra,4(sp) + 101025c: dc000017 ldw r16,0(sp) + 1010260: dec00204 addi sp,sp,8 + 1010264: f800283a ret + 1010268: 0011883a mov r8,zero + 101026c: 024ffc34 movhi r9,16368 + 1010270: 0005883a mov r2,zero + 1010274: 00d00934 movhi r3,16420 + 1010278: 480b883a mov r5,r9 + 101027c: 4009883a mov r4,r8 + 1010280: 180f883a mov r7,r3 + 1010284: 100d883a mov r6,r2 + 1010288: 1012ed00 call 1012ed0 <__muldf3> + 101028c: 843fffc4 addi r16,r16,-1 + 1010290: 1011883a mov r8,r2 + 1010294: 1813883a mov r9,r3 + 1010298: 803ff51e bne r16,zero,1010270 <_mprec_log10+0x50> + 101029c: 4005883a mov r2,r8 + 10102a0: 4807883a mov r3,r9 + 10102a4: dfc00117 ldw ra,4(sp) + 10102a8: dc000017 ldw r16,0(sp) + 10102ac: dec00204 addi sp,sp,8 + 10102b0: f800283a ret + +010102b4 <__copybits>: + 10102b4: 297fffc4 addi r5,r5,-1 + 10102b8: 30800417 ldw r2,16(r6) + 10102bc: 280bd17a srai r5,r5,5 + 10102c0: 31800504 addi r6,r6,20 + 10102c4: 1085883a add r2,r2,r2 + 10102c8: 294b883a add r5,r5,r5 + 10102cc: 294b883a add r5,r5,r5 + 10102d0: 1085883a add r2,r2,r2 + 10102d4: 290b883a add r5,r5,r4 + 10102d8: 3087883a add r3,r6,r2 + 10102dc: 29400104 addi r5,r5,4 + 10102e0: 30c0052e bgeu r6,r3,10102f8 <__copybits+0x44> + 10102e4: 30800017 ldw r2,0(r6) + 10102e8: 31800104 addi r6,r6,4 + 10102ec: 20800015 stw r2,0(r4) + 10102f0: 21000104 addi r4,r4,4 + 10102f4: 30fffb36 bltu r6,r3,10102e4 <__copybits+0x30> + 10102f8: 2140032e bgeu r4,r5,1010308 <__copybits+0x54> + 10102fc: 20000015 stw zero,0(r4) + 1010300: 21000104 addi r4,r4,4 + 1010304: 217ffd36 bltu r4,r5,10102fc <__copybits+0x48> + 1010308: f800283a ret + +0101030c <__any_on>: + 101030c: 20800417 ldw r2,16(r4) + 1010310: 2807d17a srai r3,r5,5 + 1010314: 21000504 addi r4,r4,20 + 1010318: 10c00d0e bge r2,r3,1010350 <__any_on+0x44> + 101031c: 1085883a add r2,r2,r2 + 1010320: 1085883a add r2,r2,r2 + 1010324: 208d883a add r6,r4,r2 + 1010328: 2180182e bgeu r4,r6,101038c <__any_on+0x80> + 101032c: 30bfff17 ldw r2,-4(r6) + 1010330: 30ffff04 addi r3,r6,-4 + 1010334: 1000041e bne r2,zero,1010348 <__any_on+0x3c> + 1010338: 20c0142e bgeu r4,r3,101038c <__any_on+0x80> + 101033c: 18ffff04 addi r3,r3,-4 + 1010340: 18800017 ldw r2,0(r3) + 1010344: 103ffc26 beq r2,zero,1010338 <__any_on+0x2c> + 1010348: 00800044 movi r2,1 + 101034c: f800283a ret + 1010350: 18800a0e bge r3,r2,101037c <__any_on+0x70> + 1010354: 294007cc andi r5,r5,31 + 1010358: 28000826 beq r5,zero,101037c <__any_on+0x70> + 101035c: 18c5883a add r2,r3,r3 + 1010360: 1085883a add r2,r2,r2 + 1010364: 208d883a add r6,r4,r2 + 1010368: 30c00017 ldw r3,0(r6) + 101036c: 1944d83a srl r2,r3,r5 + 1010370: 1144983a sll r2,r2,r5 + 1010374: 18bff41e bne r3,r2,1010348 <__any_on+0x3c> + 1010378: 003feb06 br 1010328 <__any_on+0x1c> + 101037c: 18c5883a add r2,r3,r3 + 1010380: 1085883a add r2,r2,r2 + 1010384: 208d883a add r6,r4,r2 + 1010388: 003fe706 br 1010328 <__any_on+0x1c> + 101038c: 0005883a mov r2,zero + 1010390: f800283a ret + +01010394 <_Balloc>: + 1010394: 20c01317 ldw r3,76(r4) + 1010398: defffb04 addi sp,sp,-20 + 101039c: dcc00315 stw r19,12(sp) + 10103a0: dc800215 stw r18,8(sp) + 10103a4: dfc00415 stw ra,16(sp) + 10103a8: 2825883a mov r18,r5 + 10103ac: dc400115 stw r17,4(sp) + 10103b0: dc000015 stw r16,0(sp) + 10103b4: 2027883a mov r19,r4 + 10103b8: 01800404 movi r6,16 + 10103bc: 01400104 movi r5,4 + 10103c0: 18001726 beq r3,zero,1010420 <_Balloc+0x8c> + 10103c4: 01400044 movi r5,1 + 10103c8: 9485883a add r2,r18,r18 + 10103cc: 2ca2983a sll r17,r5,r18 + 10103d0: 1085883a add r2,r2,r2 + 10103d4: 10c7883a add r3,r2,r3 + 10103d8: 1c000017 ldw r16,0(r3) + 10103dc: 8c4d883a add r6,r17,r17 + 10103e0: 318d883a add r6,r6,r6 + 10103e4: 9809883a mov r4,r19 + 10103e8: 31800504 addi r6,r6,20 + 10103ec: 80001226 beq r16,zero,1010438 <_Balloc+0xa4> + 10103f0: 80800017 ldw r2,0(r16) + 10103f4: 18800015 stw r2,0(r3) + 10103f8: 80000415 stw zero,16(r16) + 10103fc: 80000315 stw zero,12(r16) + 1010400: 8005883a mov r2,r16 + 1010404: dfc00417 ldw ra,16(sp) + 1010408: dcc00317 ldw r19,12(sp) + 101040c: dc800217 ldw r18,8(sp) + 1010410: dc400117 ldw r17,4(sp) + 1010414: dc000017 ldw r16,0(sp) + 1010418: dec00504 addi sp,sp,20 + 101041c: f800283a ret + 1010420: 1011a240 call 1011a24 <_calloc_r> + 1010424: 1007883a mov r3,r2 + 1010428: 0021883a mov r16,zero + 101042c: 98801315 stw r2,76(r19) + 1010430: 103fe41e bne r2,zero,10103c4 <_Balloc+0x30> + 1010434: 003ff206 br 1010400 <_Balloc+0x6c> + 1010438: 1011a240 call 1011a24 <_calloc_r> + 101043c: 103ff026 beq r2,zero,1010400 <_Balloc+0x6c> + 1010440: 1021883a mov r16,r2 + 1010444: 14800115 stw r18,4(r2) + 1010448: 14400215 stw r17,8(r2) + 101044c: 003fea06 br 10103f8 <_Balloc+0x64> + +01010450 <__d2b>: + 1010450: defff504 addi sp,sp,-44 + 1010454: dcc00515 stw r19,20(sp) + 1010458: 04c00044 movi r19,1 + 101045c: dc000215 stw r16,8(sp) + 1010460: 2821883a mov r16,r5 + 1010464: 980b883a mov r5,r19 + 1010468: ddc00915 stw r23,36(sp) + 101046c: dd800815 stw r22,32(sp) + 1010470: dd400715 stw r21,28(sp) + 1010474: dd000615 stw r20,24(sp) + 1010478: dc800415 stw r18,16(sp) + 101047c: dc400315 stw r17,12(sp) + 1010480: dfc00a15 stw ra,40(sp) + 1010484: 3023883a mov r17,r6 + 1010488: 382d883a mov r22,r7 + 101048c: ddc00b17 ldw r23,44(sp) + 1010490: 10103940 call 1010394 <_Balloc> + 1010494: 1025883a mov r18,r2 + 1010498: 00a00034 movhi r2,32768 + 101049c: 10bfffc4 addi r2,r2,-1 + 10104a0: 8888703a and r4,r17,r2 + 10104a4: 202ad53a srli r21,r4,20 + 10104a8: 00800434 movhi r2,16 + 10104ac: 10bfffc4 addi r2,r2,-1 + 10104b0: 8886703a and r3,r17,r2 + 10104b4: a829003a cmpeq r20,r21,zero + 10104b8: 800b883a mov r5,r16 + 10104bc: d8c00115 stw r3,4(sp) + 10104c0: 94000504 addi r16,r18,20 + 10104c4: a000021e bne r20,zero,10104d0 <__d2b+0x80> + 10104c8: 18c00434 orhi r3,r3,16 + 10104cc: d8c00115 stw r3,4(sp) + 10104d0: 28002726 beq r5,zero,1010570 <__d2b+0x120> + 10104d4: d809883a mov r4,sp + 10104d8: d9400015 stw r5,0(sp) + 10104dc: 100feac0 call 100feac <__lo0bits> + 10104e0: 100d883a mov r6,r2 + 10104e4: 10003526 beq r2,zero,10105bc <__d2b+0x16c> + 10104e8: d8c00117 ldw r3,4(sp) + 10104ec: 00800804 movi r2,32 + 10104f0: 1185c83a sub r2,r2,r6 + 10104f4: d9000017 ldw r4,0(sp) + 10104f8: 1886983a sll r3,r3,r2 + 10104fc: 1906b03a or r3,r3,r4 + 1010500: 90c00515 stw r3,20(r18) + 1010504: d8c00117 ldw r3,4(sp) + 1010508: 1986d83a srl r3,r3,r6 + 101050c: d8c00115 stw r3,4(sp) + 1010510: 180b003a cmpeq r5,r3,zero + 1010514: 00800084 movi r2,2 + 1010518: 114bc83a sub r5,r2,r5 + 101051c: 80c00115 stw r3,4(r16) + 1010520: 91400415 stw r5,16(r18) + 1010524: a0001a1e bne r20,zero,1010590 <__d2b+0x140> + 1010528: 3545883a add r2,r6,r21 + 101052c: 10bef344 addi r2,r2,-1075 + 1010530: 00c00d44 movi r3,53 + 1010534: b0800015 stw r2,0(r22) + 1010538: 1987c83a sub r3,r3,r6 + 101053c: b8c00015 stw r3,0(r23) + 1010540: 9005883a mov r2,r18 + 1010544: dfc00a17 ldw ra,40(sp) + 1010548: ddc00917 ldw r23,36(sp) + 101054c: dd800817 ldw r22,32(sp) + 1010550: dd400717 ldw r21,28(sp) + 1010554: dd000617 ldw r20,24(sp) + 1010558: dcc00517 ldw r19,20(sp) + 101055c: dc800417 ldw r18,16(sp) + 1010560: dc400317 ldw r17,12(sp) + 1010564: dc000217 ldw r16,8(sp) + 1010568: dec00b04 addi sp,sp,44 + 101056c: f800283a ret + 1010570: d9000104 addi r4,sp,4 + 1010574: 100feac0 call 100feac <__lo0bits> + 1010578: 11800804 addi r6,r2,32 + 101057c: d8800117 ldw r2,4(sp) + 1010580: 94c00415 stw r19,16(r18) + 1010584: 980b883a mov r5,r19 + 1010588: 90800515 stw r2,20(r18) + 101058c: a03fe626 beq r20,zero,1010528 <__d2b+0xd8> + 1010590: 2945883a add r2,r5,r5 + 1010594: 1085883a add r2,r2,r2 + 1010598: 1405883a add r2,r2,r16 + 101059c: 113fff17 ldw r4,-4(r2) + 10105a0: 30fef384 addi r3,r6,-1074 + 10105a4: 2820917a slli r16,r5,5 + 10105a8: b0c00015 stw r3,0(r22) + 10105ac: 100fe3c0 call 100fe3c <__hi0bits> + 10105b0: 80a1c83a sub r16,r16,r2 + 10105b4: bc000015 stw r16,0(r23) + 10105b8: 003fe106 br 1010540 <__d2b+0xf0> + 10105bc: d8800017 ldw r2,0(sp) + 10105c0: 90800515 stw r2,20(r18) + 10105c4: d8c00117 ldw r3,4(sp) + 10105c8: 003fd106 br 1010510 <__d2b+0xc0> + +010105cc <__mdiff>: + 10105cc: defffb04 addi sp,sp,-20 + 10105d0: dc000015 stw r16,0(sp) + 10105d4: 2821883a mov r16,r5 + 10105d8: dc800215 stw r18,8(sp) + 10105dc: 300b883a mov r5,r6 + 10105e0: 2025883a mov r18,r4 + 10105e4: 8009883a mov r4,r16 + 10105e8: dc400115 stw r17,4(sp) + 10105ec: dfc00415 stw ra,16(sp) + 10105f0: dcc00315 stw r19,12(sp) + 10105f4: 3023883a mov r17,r6 + 10105f8: 100ff700 call 100ff70 <__mcmp> + 10105fc: 10004226 beq r2,zero,1010708 <__mdiff+0x13c> + 1010600: 10005016 blt r2,zero,1010744 <__mdiff+0x178> + 1010604: 0027883a mov r19,zero + 1010608: 81400117 ldw r5,4(r16) + 101060c: 9009883a mov r4,r18 + 1010610: 10103940 call 1010394 <_Balloc> + 1010614: 1019883a mov r12,r2 + 1010618: 82800417 ldw r10,16(r16) + 101061c: 88800417 ldw r2,16(r17) + 1010620: 81800504 addi r6,r16,20 + 1010624: 5287883a add r3,r10,r10 + 1010628: 1085883a add r2,r2,r2 + 101062c: 18c7883a add r3,r3,r3 + 1010630: 1085883a add r2,r2,r2 + 1010634: 8a000504 addi r8,r17,20 + 1010638: 64c00315 stw r19,12(r12) + 101063c: 30db883a add r13,r6,r3 + 1010640: 4097883a add r11,r8,r2 + 1010644: 61c00504 addi r7,r12,20 + 1010648: 0013883a mov r9,zero + 101064c: 31000017 ldw r4,0(r6) + 1010650: 41400017 ldw r5,0(r8) + 1010654: 42000104 addi r8,r8,4 + 1010658: 20bfffcc andi r2,r4,65535 + 101065c: 28ffffcc andi r3,r5,65535 + 1010660: 10c5c83a sub r2,r2,r3 + 1010664: 1245883a add r2,r2,r9 + 1010668: 2008d43a srli r4,r4,16 + 101066c: 280ad43a srli r5,r5,16 + 1010670: 1007d43a srai r3,r2,16 + 1010674: 3880000d sth r2,0(r7) + 1010678: 2149c83a sub r4,r4,r5 + 101067c: 20c9883a add r4,r4,r3 + 1010680: 3900008d sth r4,2(r7) + 1010684: 31800104 addi r6,r6,4 + 1010688: 39c00104 addi r7,r7,4 + 101068c: 2013d43a srai r9,r4,16 + 1010690: 42ffee36 bltu r8,r11,101064c <__mdiff+0x80> + 1010694: 33400c2e bgeu r6,r13,10106c8 <__mdiff+0xfc> + 1010698: 30800017 ldw r2,0(r6) + 101069c: 31800104 addi r6,r6,4 + 10106a0: 10ffffcc andi r3,r2,65535 + 10106a4: 1a47883a add r3,r3,r9 + 10106a8: 1004d43a srli r2,r2,16 + 10106ac: 1809d43a srai r4,r3,16 + 10106b0: 38c0000d sth r3,0(r7) + 10106b4: 1105883a add r2,r2,r4 + 10106b8: 3880008d sth r2,2(r7) + 10106bc: 1013d43a srai r9,r2,16 + 10106c0: 39c00104 addi r7,r7,4 + 10106c4: 337ff436 bltu r6,r13,1010698 <__mdiff+0xcc> + 10106c8: 38bfff17 ldw r2,-4(r7) + 10106cc: 38ffff04 addi r3,r7,-4 + 10106d0: 1000041e bne r2,zero,10106e4 <__mdiff+0x118> + 10106d4: 18ffff04 addi r3,r3,-4 + 10106d8: 18800017 ldw r2,0(r3) + 10106dc: 52bfffc4 addi r10,r10,-1 + 10106e0: 103ffc26 beq r2,zero,10106d4 <__mdiff+0x108> + 10106e4: 6005883a mov r2,r12 + 10106e8: 62800415 stw r10,16(r12) + 10106ec: dfc00417 ldw ra,16(sp) + 10106f0: dcc00317 ldw r19,12(sp) + 10106f4: dc800217 ldw r18,8(sp) + 10106f8: dc400117 ldw r17,4(sp) + 10106fc: dc000017 ldw r16,0(sp) + 1010700: dec00504 addi sp,sp,20 + 1010704: f800283a ret + 1010708: 9009883a mov r4,r18 + 101070c: 000b883a mov r5,zero + 1010710: 10103940 call 1010394 <_Balloc> + 1010714: 1019883a mov r12,r2 + 1010718: 00800044 movi r2,1 + 101071c: 60800415 stw r2,16(r12) + 1010720: 6005883a mov r2,r12 + 1010724: 60000515 stw zero,20(r12) + 1010728: dfc00417 ldw ra,16(sp) + 101072c: dcc00317 ldw r19,12(sp) + 1010730: dc800217 ldw r18,8(sp) + 1010734: dc400117 ldw r17,4(sp) + 1010738: dc000017 ldw r16,0(sp) + 101073c: dec00504 addi sp,sp,20 + 1010740: f800283a ret + 1010744: 880d883a mov r6,r17 + 1010748: 04c00044 movi r19,1 + 101074c: 8023883a mov r17,r16 + 1010750: 3021883a mov r16,r6 + 1010754: 003fac06 br 1010608 <__mdiff+0x3c> + +01010758 <__lshift>: + 1010758: defff904 addi sp,sp,-28 + 101075c: 28800417 ldw r2,16(r5) + 1010760: dc000015 stw r16,0(sp) + 1010764: 3021d17a srai r16,r6,5 + 1010768: 28c00217 ldw r3,8(r5) + 101076c: 10800044 addi r2,r2,1 + 1010770: dc400115 stw r17,4(sp) + 1010774: 80a3883a add r17,r16,r2 + 1010778: dd400515 stw r21,20(sp) + 101077c: dd000415 stw r20,16(sp) + 1010780: dc800215 stw r18,8(sp) + 1010784: dfc00615 stw ra,24(sp) + 1010788: 2825883a mov r18,r5 + 101078c: dcc00315 stw r19,12(sp) + 1010790: 3029883a mov r20,r6 + 1010794: 202b883a mov r21,r4 + 1010798: 29400117 ldw r5,4(r5) + 101079c: 1c40030e bge r3,r17,10107ac <__lshift+0x54> + 10107a0: 18c7883a add r3,r3,r3 + 10107a4: 29400044 addi r5,r5,1 + 10107a8: 1c7ffd16 blt r3,r17,10107a0 <__lshift+0x48> + 10107ac: a809883a mov r4,r21 + 10107b0: 10103940 call 1010394 <_Balloc> + 10107b4: 1027883a mov r19,r2 + 10107b8: 11400504 addi r5,r2,20 + 10107bc: 0400090e bge zero,r16,10107e4 <__lshift+0x8c> + 10107c0: 2805883a mov r2,r5 + 10107c4: 0007883a mov r3,zero + 10107c8: 18c00044 addi r3,r3,1 + 10107cc: 10000015 stw zero,0(r2) + 10107d0: 10800104 addi r2,r2,4 + 10107d4: 80fffc1e bne r16,r3,10107c8 <__lshift+0x70> + 10107d8: 8405883a add r2,r16,r16 + 10107dc: 1085883a add r2,r2,r2 + 10107e0: 288b883a add r5,r5,r2 + 10107e4: 90800417 ldw r2,16(r18) + 10107e8: 91000504 addi r4,r18,20 + 10107ec: a18007cc andi r6,r20,31 + 10107f0: 1085883a add r2,r2,r2 + 10107f4: 1085883a add r2,r2,r2 + 10107f8: 208f883a add r7,r4,r2 + 10107fc: 30001e26 beq r6,zero,1010878 <__lshift+0x120> + 1010800: 00800804 movi r2,32 + 1010804: 1191c83a sub r8,r2,r6 + 1010808: 0007883a mov r3,zero + 101080c: 20800017 ldw r2,0(r4) + 1010810: 1184983a sll r2,r2,r6 + 1010814: 1884b03a or r2,r3,r2 + 1010818: 28800015 stw r2,0(r5) + 101081c: 20c00017 ldw r3,0(r4) + 1010820: 21000104 addi r4,r4,4 + 1010824: 29400104 addi r5,r5,4 + 1010828: 1a06d83a srl r3,r3,r8 + 101082c: 21fff736 bltu r4,r7,101080c <__lshift+0xb4> + 1010830: 28c00015 stw r3,0(r5) + 1010834: 18000126 beq r3,zero,101083c <__lshift+0xe4> + 1010838: 8c400044 addi r17,r17,1 + 101083c: 88bfffc4 addi r2,r17,-1 + 1010840: 98800415 stw r2,16(r19) + 1010844: a809883a mov r4,r21 + 1010848: 900b883a mov r5,r18 + 101084c: 100fe140 call 100fe14 <_Bfree> + 1010850: 9805883a mov r2,r19 + 1010854: dfc00617 ldw ra,24(sp) + 1010858: dd400517 ldw r21,20(sp) + 101085c: dd000417 ldw r20,16(sp) + 1010860: dcc00317 ldw r19,12(sp) + 1010864: dc800217 ldw r18,8(sp) + 1010868: dc400117 ldw r17,4(sp) + 101086c: dc000017 ldw r16,0(sp) + 1010870: dec00704 addi sp,sp,28 + 1010874: f800283a ret + 1010878: 20800017 ldw r2,0(r4) + 101087c: 21000104 addi r4,r4,4 + 1010880: 28800015 stw r2,0(r5) + 1010884: 29400104 addi r5,r5,4 + 1010888: 21ffec2e bgeu r4,r7,101083c <__lshift+0xe4> + 101088c: 20800017 ldw r2,0(r4) + 1010890: 21000104 addi r4,r4,4 + 1010894: 28800015 stw r2,0(r5) + 1010898: 29400104 addi r5,r5,4 + 101089c: 21fff636 bltu r4,r7,1010878 <__lshift+0x120> + 10108a0: 003fe606 br 101083c <__lshift+0xe4> + +010108a4 <__multiply>: + 10108a4: defff904 addi sp,sp,-28 + 10108a8: dcc00315 stw r19,12(sp) + 10108ac: dc800215 stw r18,8(sp) + 10108b0: 2cc00417 ldw r19,16(r5) + 10108b4: 34800417 ldw r18,16(r6) + 10108b8: dd000415 stw r20,16(sp) + 10108bc: dc400115 stw r17,4(sp) + 10108c0: dfc00615 stw ra,24(sp) + 10108c4: dd400515 stw r21,20(sp) + 10108c8: dc000015 stw r16,0(sp) + 10108cc: 2823883a mov r17,r5 + 10108d0: 3029883a mov r20,r6 + 10108d4: 9c80040e bge r19,r18,10108e8 <__multiply+0x44> + 10108d8: 9027883a mov r19,r18 + 10108dc: 2c800417 ldw r18,16(r5) + 10108e0: 2829883a mov r20,r5 + 10108e4: 3023883a mov r17,r6 + 10108e8: 88800217 ldw r2,8(r17) + 10108ec: 9ca1883a add r16,r19,r18 + 10108f0: 89400117 ldw r5,4(r17) + 10108f4: 1400010e bge r2,r16,10108fc <__multiply+0x58> + 10108f8: 29400044 addi r5,r5,1 + 10108fc: 10103940 call 1010394 <_Balloc> + 1010900: 102b883a mov r21,r2 + 1010904: 8405883a add r2,r16,r16 + 1010908: 1085883a add r2,r2,r2 + 101090c: a9000504 addi r4,r21,20 + 1010910: 209d883a add r14,r4,r2 + 1010914: 2380042e bgeu r4,r14,1010928 <__multiply+0x84> + 1010918: 2005883a mov r2,r4 + 101091c: 10000015 stw zero,0(r2) + 1010920: 10800104 addi r2,r2,4 + 1010924: 13bffd36 bltu r2,r14,101091c <__multiply+0x78> + 1010928: 9485883a add r2,r18,r18 + 101092c: 9cc7883a add r3,r19,r19 + 1010930: a1800504 addi r6,r20,20 + 1010934: 1085883a add r2,r2,r2 + 1010938: 8b400504 addi r13,r17,20 + 101093c: 18c7883a add r3,r3,r3 + 1010940: 309f883a add r15,r6,r2 + 1010944: 68d7883a add r11,r13,r3 + 1010948: 33c03b2e bgeu r6,r15,1010a38 <__multiply+0x194> + 101094c: 2019883a mov r12,r4 + 1010950: 30800017 ldw r2,0(r6) + 1010954: 127fffcc andi r9,r2,65535 + 1010958: 48001826 beq r9,zero,10109bc <__multiply+0x118> + 101095c: 6811883a mov r8,r13 + 1010960: 600f883a mov r7,r12 + 1010964: 0015883a mov r10,zero + 1010968: 40c00017 ldw r3,0(r8) + 101096c: 39400017 ldw r5,0(r7) + 1010970: 42000104 addi r8,r8,4 + 1010974: 193fffcc andi r4,r3,65535 + 1010978: 4909383a mul r4,r9,r4 + 101097c: 1806d43a srli r3,r3,16 + 1010980: 28bfffcc andi r2,r5,65535 + 1010984: 5085883a add r2,r10,r2 + 1010988: 2089883a add r4,r4,r2 + 101098c: 48c7383a mul r3,r9,r3 + 1010990: 280ad43a srli r5,r5,16 + 1010994: 2004d43a srli r2,r4,16 + 1010998: 3900000d sth r4,0(r7) + 101099c: 1947883a add r3,r3,r5 + 10109a0: 10c5883a add r2,r2,r3 + 10109a4: 3880008d sth r2,2(r7) + 10109a8: 1014d43a srli r10,r2,16 + 10109ac: 39c00104 addi r7,r7,4 + 10109b0: 42ffed36 bltu r8,r11,1010968 <__multiply+0xc4> + 10109b4: 3a800015 stw r10,0(r7) + 10109b8: 30800017 ldw r2,0(r6) + 10109bc: 1012d43a srli r9,r2,16 + 10109c0: 48001926 beq r9,zero,1010a28 <__multiply+0x184> + 10109c4: 60800017 ldw r2,0(r12) + 10109c8: 6811883a mov r8,r13 + 10109cc: 600f883a mov r7,r12 + 10109d0: 0015883a mov r10,zero + 10109d4: 100b883a mov r5,r2 + 10109d8: 41000017 ldw r4,0(r8) + 10109dc: 2806d43a srli r3,r5,16 + 10109e0: 3880000d sth r2,0(r7) + 10109e4: 20bfffcc andi r2,r4,65535 + 10109e8: 4885383a mul r2,r9,r2 + 10109ec: 50c7883a add r3,r10,r3 + 10109f0: 2008d43a srli r4,r4,16 + 10109f4: 10c5883a add r2,r2,r3 + 10109f8: 3880008d sth r2,2(r7) + 10109fc: 39c00104 addi r7,r7,4 + 1010a00: 39400017 ldw r5,0(r7) + 1010a04: 4909383a mul r4,r9,r4 + 1010a08: 1004d43a srli r2,r2,16 + 1010a0c: 28ffffcc andi r3,r5,65535 + 1010a10: 20c9883a add r4,r4,r3 + 1010a14: 1105883a add r2,r2,r4 + 1010a18: 42000104 addi r8,r8,4 + 1010a1c: 1014d43a srli r10,r2,16 + 1010a20: 42ffed36 bltu r8,r11,10109d8 <__multiply+0x134> + 1010a24: 38800015 stw r2,0(r7) + 1010a28: 31800104 addi r6,r6,4 + 1010a2c: 33c0022e bgeu r6,r15,1010a38 <__multiply+0x194> + 1010a30: 63000104 addi r12,r12,4 + 1010a34: 003fc606 br 1010950 <__multiply+0xac> + 1010a38: 0400090e bge zero,r16,1010a60 <__multiply+0x1bc> + 1010a3c: 70bfff17 ldw r2,-4(r14) + 1010a40: 70ffff04 addi r3,r14,-4 + 1010a44: 10000326 beq r2,zero,1010a54 <__multiply+0x1b0> + 1010a48: 00000506 br 1010a60 <__multiply+0x1bc> + 1010a4c: 18800017 ldw r2,0(r3) + 1010a50: 1000031e bne r2,zero,1010a60 <__multiply+0x1bc> + 1010a54: 843fffc4 addi r16,r16,-1 + 1010a58: 18ffff04 addi r3,r3,-4 + 1010a5c: 803ffb1e bne r16,zero,1010a4c <__multiply+0x1a8> + 1010a60: a805883a mov r2,r21 + 1010a64: ac000415 stw r16,16(r21) + 1010a68: dfc00617 ldw ra,24(sp) + 1010a6c: dd400517 ldw r21,20(sp) + 1010a70: dd000417 ldw r20,16(sp) + 1010a74: dcc00317 ldw r19,12(sp) + 1010a78: dc800217 ldw r18,8(sp) + 1010a7c: dc400117 ldw r17,4(sp) + 1010a80: dc000017 ldw r16,0(sp) + 1010a84: dec00704 addi sp,sp,28 + 1010a88: f800283a ret + +01010a8c <__i2b>: + 1010a8c: defffd04 addi sp,sp,-12 + 1010a90: dc000015 stw r16,0(sp) + 1010a94: 04000044 movi r16,1 + 1010a98: dc800115 stw r18,4(sp) + 1010a9c: 2825883a mov r18,r5 + 1010aa0: 800b883a mov r5,r16 + 1010aa4: dfc00215 stw ra,8(sp) + 1010aa8: 10103940 call 1010394 <_Balloc> + 1010aac: 14000415 stw r16,16(r2) + 1010ab0: 14800515 stw r18,20(r2) + 1010ab4: dfc00217 ldw ra,8(sp) + 1010ab8: dc800117 ldw r18,4(sp) + 1010abc: dc000017 ldw r16,0(sp) + 1010ac0: dec00304 addi sp,sp,12 + 1010ac4: f800283a ret + +01010ac8 <__multadd>: + 1010ac8: defffa04 addi sp,sp,-24 + 1010acc: dc800215 stw r18,8(sp) + 1010ad0: 2c800417 ldw r18,16(r5) + 1010ad4: dd000415 stw r20,16(sp) + 1010ad8: dcc00315 stw r19,12(sp) + 1010adc: dc000015 stw r16,0(sp) + 1010ae0: dfc00515 stw ra,20(sp) + 1010ae4: 3821883a mov r16,r7 + 1010ae8: dc400115 stw r17,4(sp) + 1010aec: 2827883a mov r19,r5 + 1010af0: 2029883a mov r20,r4 + 1010af4: 2a000504 addi r8,r5,20 + 1010af8: 000f883a mov r7,zero + 1010afc: 40800017 ldw r2,0(r8) + 1010b00: 39c00044 addi r7,r7,1 + 1010b04: 10ffffcc andi r3,r2,65535 + 1010b08: 1987383a mul r3,r3,r6 + 1010b0c: 1004d43a srli r2,r2,16 + 1010b10: 1c07883a add r3,r3,r16 + 1010b14: 180ad43a srli r5,r3,16 + 1010b18: 1185383a mul r2,r2,r6 + 1010b1c: 18ffffcc andi r3,r3,65535 + 1010b20: 1145883a add r2,r2,r5 + 1010b24: 1008943a slli r4,r2,16 + 1010b28: 1020d43a srli r16,r2,16 + 1010b2c: 20c9883a add r4,r4,r3 + 1010b30: 41000015 stw r4,0(r8) + 1010b34: 42000104 addi r8,r8,4 + 1010b38: 3cbff016 blt r7,r18,1010afc <__multadd+0x34> + 1010b3c: 80000826 beq r16,zero,1010b60 <__multadd+0x98> + 1010b40: 98800217 ldw r2,8(r19) + 1010b44: 90800f0e bge r18,r2,1010b84 <__multadd+0xbc> + 1010b48: 9485883a add r2,r18,r18 + 1010b4c: 1085883a add r2,r2,r2 + 1010b50: 14c5883a add r2,r2,r19 + 1010b54: 90c00044 addi r3,r18,1 + 1010b58: 14000515 stw r16,20(r2) + 1010b5c: 98c00415 stw r3,16(r19) + 1010b60: 9805883a mov r2,r19 + 1010b64: dfc00517 ldw ra,20(sp) + 1010b68: dd000417 ldw r20,16(sp) + 1010b6c: dcc00317 ldw r19,12(sp) + 1010b70: dc800217 ldw r18,8(sp) + 1010b74: dc400117 ldw r17,4(sp) + 1010b78: dc000017 ldw r16,0(sp) + 1010b7c: dec00604 addi sp,sp,24 + 1010b80: f800283a ret + 1010b84: 99400117 ldw r5,4(r19) + 1010b88: a009883a mov r4,r20 + 1010b8c: 29400044 addi r5,r5,1 + 1010b90: 10103940 call 1010394 <_Balloc> + 1010b94: 99800417 ldw r6,16(r19) + 1010b98: 99400304 addi r5,r19,12 + 1010b9c: 11000304 addi r4,r2,12 + 1010ba0: 318d883a add r6,r6,r6 + 1010ba4: 318d883a add r6,r6,r6 + 1010ba8: 31800204 addi r6,r6,8 + 1010bac: 1023883a mov r17,r2 + 1010bb0: 100aa3c0 call 100aa3c + 1010bb4: 980b883a mov r5,r19 + 1010bb8: a009883a mov r4,r20 + 1010bbc: 100fe140 call 100fe14 <_Bfree> + 1010bc0: 8827883a mov r19,r17 + 1010bc4: 003fe006 br 1010b48 <__multadd+0x80> + +01010bc8 <__pow5mult>: + 1010bc8: defffa04 addi sp,sp,-24 + 1010bcc: 308000cc andi r2,r6,3 + 1010bd0: dd000415 stw r20,16(sp) + 1010bd4: dcc00315 stw r19,12(sp) + 1010bd8: dc000015 stw r16,0(sp) + 1010bdc: dfc00515 stw ra,20(sp) + 1010be0: dc800215 stw r18,8(sp) + 1010be4: dc400115 stw r17,4(sp) + 1010be8: 3021883a mov r16,r6 + 1010bec: 2027883a mov r19,r4 + 1010bf0: 2829883a mov r20,r5 + 1010bf4: 10002b1e bne r2,zero,1010ca4 <__pow5mult+0xdc> + 1010bf8: 8025d0ba srai r18,r16,2 + 1010bfc: 90001b26 beq r18,zero,1010c6c <__pow5mult+0xa4> + 1010c00: 9c001217 ldw r16,72(r19) + 1010c04: 8000081e bne r16,zero,1010c28 <__pow5mult+0x60> + 1010c08: 00003006 br 1010ccc <__pow5mult+0x104> + 1010c0c: 800b883a mov r5,r16 + 1010c10: 800d883a mov r6,r16 + 1010c14: 9809883a mov r4,r19 + 1010c18: 90001426 beq r18,zero,1010c6c <__pow5mult+0xa4> + 1010c1c: 80800017 ldw r2,0(r16) + 1010c20: 10001b26 beq r2,zero,1010c90 <__pow5mult+0xc8> + 1010c24: 1021883a mov r16,r2 + 1010c28: 9080004c andi r2,r18,1 + 1010c2c: 1005003a cmpeq r2,r2,zero + 1010c30: 9025d07a srai r18,r18,1 + 1010c34: 800d883a mov r6,r16 + 1010c38: 9809883a mov r4,r19 + 1010c3c: a00b883a mov r5,r20 + 1010c40: 103ff21e bne r2,zero,1010c0c <__pow5mult+0x44> + 1010c44: 10108a40 call 10108a4 <__multiply> + 1010c48: a00b883a mov r5,r20 + 1010c4c: 9809883a mov r4,r19 + 1010c50: 1023883a mov r17,r2 + 1010c54: 100fe140 call 100fe14 <_Bfree> + 1010c58: 8829883a mov r20,r17 + 1010c5c: 800b883a mov r5,r16 + 1010c60: 800d883a mov r6,r16 + 1010c64: 9809883a mov r4,r19 + 1010c68: 903fec1e bne r18,zero,1010c1c <__pow5mult+0x54> + 1010c6c: a005883a mov r2,r20 + 1010c70: dfc00517 ldw ra,20(sp) + 1010c74: dd000417 ldw r20,16(sp) + 1010c78: dcc00317 ldw r19,12(sp) + 1010c7c: dc800217 ldw r18,8(sp) + 1010c80: dc400117 ldw r17,4(sp) + 1010c84: dc000017 ldw r16,0(sp) + 1010c88: dec00604 addi sp,sp,24 + 1010c8c: f800283a ret + 1010c90: 10108a40 call 10108a4 <__multiply> + 1010c94: 80800015 stw r2,0(r16) + 1010c98: 1021883a mov r16,r2 + 1010c9c: 10000015 stw zero,0(r2) + 1010ca0: 003fe106 br 1010c28 <__pow5mult+0x60> + 1010ca4: 1085883a add r2,r2,r2 + 1010ca8: 00c040b4 movhi r3,258 + 1010cac: 18c64a04 addi r3,r3,6440 + 1010cb0: 1085883a add r2,r2,r2 + 1010cb4: 10c5883a add r2,r2,r3 + 1010cb8: 11bfff17 ldw r6,-4(r2) + 1010cbc: 000f883a mov r7,zero + 1010cc0: 1010ac80 call 1010ac8 <__multadd> + 1010cc4: 1029883a mov r20,r2 + 1010cc8: 003fcb06 br 1010bf8 <__pow5mult+0x30> + 1010ccc: 9809883a mov r4,r19 + 1010cd0: 01409c44 movi r5,625 + 1010cd4: 1010a8c0 call 1010a8c <__i2b> + 1010cd8: 98801215 stw r2,72(r19) + 1010cdc: 1021883a mov r16,r2 + 1010ce0: 10000015 stw zero,0(r2) + 1010ce4: 003fd006 br 1010c28 <__pow5mult+0x60> + +01010ce8 <__s2b>: + 1010ce8: defff904 addi sp,sp,-28 + 1010cec: dcc00315 stw r19,12(sp) + 1010cf0: dc800215 stw r18,8(sp) + 1010cf4: 2827883a mov r19,r5 + 1010cf8: 2025883a mov r18,r4 + 1010cfc: 01400244 movi r5,9 + 1010d00: 39000204 addi r4,r7,8 + 1010d04: dd000415 stw r20,16(sp) + 1010d08: dc400115 stw r17,4(sp) + 1010d0c: dfc00615 stw ra,24(sp) + 1010d10: dd400515 stw r21,20(sp) + 1010d14: dc000015 stw r16,0(sp) + 1010d18: 3829883a mov r20,r7 + 1010d1c: 3023883a mov r17,r6 + 1010d20: 1013b740 call 1013b74 <__divsi3> + 1010d24: 00c00044 movi r3,1 + 1010d28: 1880350e bge r3,r2,1010e00 <__s2b+0x118> + 1010d2c: 000b883a mov r5,zero + 1010d30: 18c7883a add r3,r3,r3 + 1010d34: 29400044 addi r5,r5,1 + 1010d38: 18bffd16 blt r3,r2,1010d30 <__s2b+0x48> + 1010d3c: 9009883a mov r4,r18 + 1010d40: 10103940 call 1010394 <_Balloc> + 1010d44: 1011883a mov r8,r2 + 1010d48: d8800717 ldw r2,28(sp) + 1010d4c: 00c00044 movi r3,1 + 1010d50: 01800244 movi r6,9 + 1010d54: 40800515 stw r2,20(r8) + 1010d58: 40c00415 stw r3,16(r8) + 1010d5c: 3440260e bge r6,r17,1010df8 <__s2b+0x110> + 1010d60: 3021883a mov r16,r6 + 1010d64: 99ab883a add r21,r19,r6 + 1010d68: 9c05883a add r2,r19,r16 + 1010d6c: 11c00007 ldb r7,0(r2) + 1010d70: 400b883a mov r5,r8 + 1010d74: 9009883a mov r4,r18 + 1010d78: 39fff404 addi r7,r7,-48 + 1010d7c: 01800284 movi r6,10 + 1010d80: 1010ac80 call 1010ac8 <__multadd> + 1010d84: 84000044 addi r16,r16,1 + 1010d88: 1011883a mov r8,r2 + 1010d8c: 8c3ff61e bne r17,r16,1010d68 <__s2b+0x80> + 1010d90: ac45883a add r2,r21,r17 + 1010d94: 117ffe04 addi r5,r2,-8 + 1010d98: 880d883a mov r6,r17 + 1010d9c: 35000c0e bge r6,r20,1010dd0 <__s2b+0xe8> + 1010da0: a185c83a sub r2,r20,r6 + 1010da4: 2821883a mov r16,r5 + 1010da8: 28a3883a add r17,r5,r2 + 1010dac: 81c00007 ldb r7,0(r16) + 1010db0: 400b883a mov r5,r8 + 1010db4: 9009883a mov r4,r18 + 1010db8: 39fff404 addi r7,r7,-48 + 1010dbc: 01800284 movi r6,10 + 1010dc0: 1010ac80 call 1010ac8 <__multadd> + 1010dc4: 84000044 addi r16,r16,1 + 1010dc8: 1011883a mov r8,r2 + 1010dcc: 847ff71e bne r16,r17,1010dac <__s2b+0xc4> + 1010dd0: 4005883a mov r2,r8 + 1010dd4: dfc00617 ldw ra,24(sp) + 1010dd8: dd400517 ldw r21,20(sp) + 1010ddc: dd000417 ldw r20,16(sp) + 1010de0: dcc00317 ldw r19,12(sp) + 1010de4: dc800217 ldw r18,8(sp) + 1010de8: dc400117 ldw r17,4(sp) + 1010dec: dc000017 ldw r16,0(sp) + 1010df0: dec00704 addi sp,sp,28 + 1010df4: f800283a ret + 1010df8: 99400284 addi r5,r19,10 + 1010dfc: 003fe706 br 1010d9c <__s2b+0xb4> + 1010e00: 000b883a mov r5,zero + 1010e04: 003fcd06 br 1010d3c <__s2b+0x54> + +01010e08 : + 1010e08: defffc04 addi sp,sp,-16 + 1010e0c: dc800215 stw r18,8(sp) + 1010e10: 048040b4 movhi r18,258 + 1010e14: 948dc804 addi r18,r18,14112 + 1010e18: 90c00017 ldw r3,0(r18) + 1010e1c: dc400115 stw r17,4(sp) + 1010e20: dc000015 stw r16,0(sp) + 1010e24: dfc00315 stw ra,12(sp) + 1010e28: 2023883a mov r17,r4 + 1010e2c: 2821883a mov r16,r5 + 1010e30: 18000226 beq r3,zero,1010e3c + 1010e34: 18800e17 ldw r2,56(r3) + 1010e38: 10001126 beq r2,zero,1010e80 + 1010e3c: 80800217 ldw r2,8(r16) + 1010e40: 10ffffc4 addi r3,r2,-1 + 1010e44: 80c00215 stw r3,8(r16) + 1010e48: 18001316 blt r3,zero,1010e98 + 1010e4c: 80800017 ldw r2,0(r16) + 1010e50: 14400005 stb r17,0(r2) + 1010e54: 80c00017 ldw r3,0(r16) + 1010e58: 18800044 addi r2,r3,1 + 1010e5c: 18c00003 ldbu r3,0(r3) + 1010e60: 80800015 stw r2,0(r16) + 1010e64: 1805883a mov r2,r3 + 1010e68: dfc00317 ldw ra,12(sp) + 1010e6c: dc800217 ldw r18,8(sp) + 1010e70: dc400117 ldw r17,4(sp) + 1010e74: dc000017 ldw r16,0(sp) + 1010e78: dec00404 addi sp,sp,16 + 1010e7c: f800283a ret + 1010e80: 1809883a mov r4,r3 + 1010e84: 100ef080 call 100ef08 <__sinit> + 1010e88: 80800217 ldw r2,8(r16) + 1010e8c: 10ffffc4 addi r3,r2,-1 + 1010e90: 80c00215 stw r3,8(r16) + 1010e94: 183fed0e bge r3,zero,1010e4c + 1010e98: 80800617 ldw r2,24(r16) + 1010e9c: 18800f16 blt r3,r2,1010edc + 1010ea0: 80800017 ldw r2,0(r16) + 1010ea4: 14400005 stb r17,0(r2) + 1010ea8: 81000017 ldw r4,0(r16) + 1010eac: 00800284 movi r2,10 + 1010eb0: 20c00003 ldbu r3,0(r4) + 1010eb4: 18801226 beq r3,r2,1010f00 + 1010eb8: 20800044 addi r2,r4,1 + 1010ebc: 80800015 stw r2,0(r16) + 1010ec0: 1805883a mov r2,r3 + 1010ec4: dfc00317 ldw ra,12(sp) + 1010ec8: dc800217 ldw r18,8(sp) + 1010ecc: dc400117 ldw r17,4(sp) + 1010ed0: dc000017 ldw r16,0(sp) + 1010ed4: dec00404 addi sp,sp,16 + 1010ed8: f800283a ret + 1010edc: 91000017 ldw r4,0(r18) + 1010ee0: 880b883a mov r5,r17 + 1010ee4: 800d883a mov r6,r16 + 1010ee8: dfc00317 ldw ra,12(sp) + 1010eec: dc800217 ldw r18,8(sp) + 1010ef0: dc400117 ldw r17,4(sp) + 1010ef4: dc000017 ldw r16,0(sp) + 1010ef8: dec00404 addi sp,sp,16 + 1010efc: 10118601 jmpi 1011860 <__swbuf_r> + 1010f00: 91000017 ldw r4,0(r18) + 1010f04: 180b883a mov r5,r3 + 1010f08: 003ff606 br 1010ee4 + +01010f0c <_putc_r>: + 1010f0c: defffc04 addi sp,sp,-16 + 1010f10: dc400215 stw r17,8(sp) + 1010f14: dc000115 stw r16,4(sp) + 1010f18: dfc00315 stw ra,12(sp) + 1010f1c: 2021883a mov r16,r4 + 1010f20: 2823883a mov r17,r5 + 1010f24: 20000226 beq r4,zero,1010f30 <_putc_r+0x24> + 1010f28: 20800e17 ldw r2,56(r4) + 1010f2c: 10001026 beq r2,zero,1010f70 <_putc_r+0x64> + 1010f30: 30800217 ldw r2,8(r6) + 1010f34: 10ffffc4 addi r3,r2,-1 + 1010f38: 30c00215 stw r3,8(r6) + 1010f3c: 18001316 blt r3,zero,1010f8c <_putc_r+0x80> + 1010f40: 30800017 ldw r2,0(r6) + 1010f44: 14400005 stb r17,0(r2) + 1010f48: 30c00017 ldw r3,0(r6) + 1010f4c: 18800044 addi r2,r3,1 + 1010f50: 18c00003 ldbu r3,0(r3) + 1010f54: 30800015 stw r2,0(r6) + 1010f58: 1805883a mov r2,r3 + 1010f5c: dfc00317 ldw ra,12(sp) + 1010f60: dc400217 ldw r17,8(sp) + 1010f64: dc000117 ldw r16,4(sp) + 1010f68: dec00404 addi sp,sp,16 + 1010f6c: f800283a ret + 1010f70: d9800015 stw r6,0(sp) + 1010f74: 100ef080 call 100ef08 <__sinit> + 1010f78: d9800017 ldw r6,0(sp) + 1010f7c: 30800217 ldw r2,8(r6) + 1010f80: 10ffffc4 addi r3,r2,-1 + 1010f84: 30c00215 stw r3,8(r6) + 1010f88: 183fed0e bge r3,zero,1010f40 <_putc_r+0x34> + 1010f8c: 30800617 ldw r2,24(r6) + 1010f90: 18800e16 blt r3,r2,1010fcc <_putc_r+0xc0> + 1010f94: 30800017 ldw r2,0(r6) + 1010f98: 14400005 stb r17,0(r2) + 1010f9c: 31000017 ldw r4,0(r6) + 1010fa0: 00800284 movi r2,10 + 1010fa4: 20c00003 ldbu r3,0(r4) + 1010fa8: 18800f26 beq r3,r2,1010fe8 <_putc_r+0xdc> + 1010fac: 20800044 addi r2,r4,1 + 1010fb0: 30800015 stw r2,0(r6) + 1010fb4: 1805883a mov r2,r3 + 1010fb8: dfc00317 ldw ra,12(sp) + 1010fbc: dc400217 ldw r17,8(sp) + 1010fc0: dc000117 ldw r16,4(sp) + 1010fc4: dec00404 addi sp,sp,16 + 1010fc8: f800283a ret + 1010fcc: 8009883a mov r4,r16 + 1010fd0: 880b883a mov r5,r17 + 1010fd4: dfc00317 ldw ra,12(sp) + 1010fd8: dc400217 ldw r17,8(sp) + 1010fdc: dc000117 ldw r16,4(sp) + 1010fe0: dec00404 addi sp,sp,16 + 1010fe4: 10118601 jmpi 1011860 <__swbuf_r> + 1010fe8: 8009883a mov r4,r16 + 1010fec: 180b883a mov r5,r3 + 1010ff0: 003ff806 br 1010fd4 <_putc_r+0xc8> + +01010ff4 <_realloc_r>: + 1010ff4: defff404 addi sp,sp,-48 + 1010ff8: dd800815 stw r22,32(sp) + 1010ffc: dc800415 stw r18,16(sp) + 1011000: dc400315 stw r17,12(sp) + 1011004: dfc00b15 stw ra,44(sp) + 1011008: df000a15 stw fp,40(sp) + 101100c: ddc00915 stw r23,36(sp) + 1011010: dd400715 stw r21,28(sp) + 1011014: dd000615 stw r20,24(sp) + 1011018: dcc00515 stw r19,20(sp) + 101101c: dc000215 stw r16,8(sp) + 1011020: 2825883a mov r18,r5 + 1011024: 3023883a mov r17,r6 + 1011028: 202d883a mov r22,r4 + 101102c: 2800c926 beq r5,zero,1011354 <_realloc_r+0x360> + 1011030: 10150a00 call 10150a0 <__malloc_lock> + 1011034: 943ffe04 addi r16,r18,-8 + 1011038: 88c002c4 addi r3,r17,11 + 101103c: 00800584 movi r2,22 + 1011040: 82000117 ldw r8,4(r16) + 1011044: 10c01b2e bgeu r2,r3,10110b4 <_realloc_r+0xc0> + 1011048: 00bffe04 movi r2,-8 + 101104c: 188e703a and r7,r3,r2 + 1011050: 3839883a mov fp,r7 + 1011054: 38001a16 blt r7,zero,10110c0 <_realloc_r+0xcc> + 1011058: e4401936 bltu fp,r17,10110c0 <_realloc_r+0xcc> + 101105c: 013fff04 movi r4,-4 + 1011060: 4126703a and r19,r8,r4 + 1011064: 99c02616 blt r19,r7,1011100 <_realloc_r+0x10c> + 1011068: 802b883a mov r21,r16 + 101106c: 9829883a mov r20,r19 + 1011070: 84000204 addi r16,r16,8 + 1011074: a80f883a mov r7,r21 + 1011078: a70dc83a sub r6,r20,fp + 101107c: 008003c4 movi r2,15 + 1011080: 1180c136 bltu r2,r6,1011388 <_realloc_r+0x394> + 1011084: 38800117 ldw r2,4(r7) + 1011088: a549883a add r4,r20,r21 + 101108c: 1080004c andi r2,r2,1 + 1011090: a084b03a or r2,r20,r2 + 1011094: 38800115 stw r2,4(r7) + 1011098: 20c00117 ldw r3,4(r4) + 101109c: 18c00054 ori r3,r3,1 + 10110a0: 20c00115 stw r3,4(r4) + 10110a4: b009883a mov r4,r22 + 10110a8: 10151a80 call 10151a8 <__malloc_unlock> + 10110ac: 8023883a mov r17,r16 + 10110b0: 00000606 br 10110cc <_realloc_r+0xd8> + 10110b4: 01c00404 movi r7,16 + 10110b8: 3839883a mov fp,r7 + 10110bc: e47fe72e bgeu fp,r17,101105c <_realloc_r+0x68> + 10110c0: 00800304 movi r2,12 + 10110c4: 0023883a mov r17,zero + 10110c8: b0800015 stw r2,0(r22) + 10110cc: 8805883a mov r2,r17 + 10110d0: dfc00b17 ldw ra,44(sp) + 10110d4: df000a17 ldw fp,40(sp) + 10110d8: ddc00917 ldw r23,36(sp) + 10110dc: dd800817 ldw r22,32(sp) + 10110e0: dd400717 ldw r21,28(sp) + 10110e4: dd000617 ldw r20,24(sp) + 10110e8: dcc00517 ldw r19,20(sp) + 10110ec: dc800417 ldw r18,16(sp) + 10110f0: dc400317 ldw r17,12(sp) + 10110f4: dc000217 ldw r16,8(sp) + 10110f8: dec00c04 addi sp,sp,48 + 10110fc: f800283a ret + 1011100: 008040b4 movhi r2,258 + 1011104: 1086f004 addi r2,r2,7104 + 1011108: 12400217 ldw r9,8(r2) + 101110c: 84cd883a add r6,r16,r19 + 1011110: 802b883a mov r21,r16 + 1011114: 3240b926 beq r6,r9,10113fc <_realloc_r+0x408> + 1011118: 31400117 ldw r5,4(r6) + 101111c: 00bfff84 movi r2,-2 + 1011120: 2884703a and r2,r5,r2 + 1011124: 1185883a add r2,r2,r6 + 1011128: 10c00117 ldw r3,4(r2) + 101112c: 18c0004c andi r3,r3,1 + 1011130: 1807003a cmpeq r3,r3,zero + 1011134: 1800a326 beq r3,zero,10113c4 <_realloc_r+0x3d0> + 1011138: 2908703a and r4,r5,r4 + 101113c: 9929883a add r20,r19,r4 + 1011140: a1c0a30e bge r20,r7,10113d0 <_realloc_r+0x3dc> + 1011144: 4080004c andi r2,r8,1 + 1011148: 1000551e bne r2,zero,10112a0 <_realloc_r+0x2ac> + 101114c: 80800017 ldw r2,0(r16) + 1011150: 80afc83a sub r23,r16,r2 + 1011154: b8c00117 ldw r3,4(r23) + 1011158: 00bfff04 movi r2,-4 + 101115c: 1884703a and r2,r3,r2 + 1011160: 30002e26 beq r6,zero,101121c <_realloc_r+0x228> + 1011164: 3240b926 beq r6,r9,101144c <_realloc_r+0x458> + 1011168: 98a9883a add r20,r19,r2 + 101116c: 2509883a add r4,r4,r20 + 1011170: d9000015 stw r4,0(sp) + 1011174: 21c02a16 blt r4,r7,1011220 <_realloc_r+0x22c> + 1011178: 30800317 ldw r2,12(r6) + 101117c: 30c00217 ldw r3,8(r6) + 1011180: 01400904 movi r5,36 + 1011184: 99bfff04 addi r6,r19,-4 + 1011188: 18800315 stw r2,12(r3) + 101118c: 10c00215 stw r3,8(r2) + 1011190: b9000317 ldw r4,12(r23) + 1011194: b8800217 ldw r2,8(r23) + 1011198: b82b883a mov r21,r23 + 101119c: bc000204 addi r16,r23,8 + 10111a0: 20800215 stw r2,8(r4) + 10111a4: 11000315 stw r4,12(r2) + 10111a8: 2980e436 bltu r5,r6,101153c <_realloc_r+0x548> + 10111ac: 008004c4 movi r2,19 + 10111b0: 9009883a mov r4,r18 + 10111b4: 8011883a mov r8,r16 + 10111b8: 11800f2e bgeu r2,r6,10111f8 <_realloc_r+0x204> + 10111bc: 90800017 ldw r2,0(r18) + 10111c0: ba000404 addi r8,r23,16 + 10111c4: 91000204 addi r4,r18,8 + 10111c8: b8800215 stw r2,8(r23) + 10111cc: 90c00117 ldw r3,4(r18) + 10111d0: 008006c4 movi r2,27 + 10111d4: b8c00315 stw r3,12(r23) + 10111d8: 1180072e bgeu r2,r6,10111f8 <_realloc_r+0x204> + 10111dc: 90c00217 ldw r3,8(r18) + 10111e0: ba000604 addi r8,r23,24 + 10111e4: 91000404 addi r4,r18,16 + 10111e8: b8c00415 stw r3,16(r23) + 10111ec: 90800317 ldw r2,12(r18) + 10111f0: b8800515 stw r2,20(r23) + 10111f4: 3140e726 beq r6,r5,1011594 <_realloc_r+0x5a0> + 10111f8: 20800017 ldw r2,0(r4) + 10111fc: dd000017 ldw r20,0(sp) + 1011200: b80f883a mov r7,r23 + 1011204: 40800015 stw r2,0(r8) + 1011208: 20c00117 ldw r3,4(r4) + 101120c: 40c00115 stw r3,4(r8) + 1011210: 20800217 ldw r2,8(r4) + 1011214: 40800215 stw r2,8(r8) + 1011218: 003f9706 br 1011078 <_realloc_r+0x84> + 101121c: 98a9883a add r20,r19,r2 + 1011220: a1c01f16 blt r20,r7,10112a0 <_realloc_r+0x2ac> + 1011224: b8c00317 ldw r3,12(r23) + 1011228: b8800217 ldw r2,8(r23) + 101122c: 99bfff04 addi r6,r19,-4 + 1011230: 01400904 movi r5,36 + 1011234: b82b883a mov r21,r23 + 1011238: 18800215 stw r2,8(r3) + 101123c: 10c00315 stw r3,12(r2) + 1011240: bc000204 addi r16,r23,8 + 1011244: 2980c336 bltu r5,r6,1011554 <_realloc_r+0x560> + 1011248: 008004c4 movi r2,19 + 101124c: 9009883a mov r4,r18 + 1011250: 8011883a mov r8,r16 + 1011254: 11800f2e bgeu r2,r6,1011294 <_realloc_r+0x2a0> + 1011258: 90800017 ldw r2,0(r18) + 101125c: ba000404 addi r8,r23,16 + 1011260: 91000204 addi r4,r18,8 + 1011264: b8800215 stw r2,8(r23) + 1011268: 90c00117 ldw r3,4(r18) + 101126c: 008006c4 movi r2,27 + 1011270: b8c00315 stw r3,12(r23) + 1011274: 1180072e bgeu r2,r6,1011294 <_realloc_r+0x2a0> + 1011278: 90c00217 ldw r3,8(r18) + 101127c: ba000604 addi r8,r23,24 + 1011280: 91000404 addi r4,r18,16 + 1011284: b8c00415 stw r3,16(r23) + 1011288: 90800317 ldw r2,12(r18) + 101128c: b8800515 stw r2,20(r23) + 1011290: 3140c726 beq r6,r5,10115b0 <_realloc_r+0x5bc> + 1011294: 20800017 ldw r2,0(r4) + 1011298: b80f883a mov r7,r23 + 101129c: 003fd906 br 1011204 <_realloc_r+0x210> + 10112a0: 880b883a mov r5,r17 + 10112a4: b009883a mov r4,r22 + 10112a8: 100a1a40 call 100a1a4 <_malloc_r> + 10112ac: 1023883a mov r17,r2 + 10112b0: 10002526 beq r2,zero,1011348 <_realloc_r+0x354> + 10112b4: 80800117 ldw r2,4(r16) + 10112b8: 00ffff84 movi r3,-2 + 10112bc: 893ffe04 addi r4,r17,-8 + 10112c0: 10c4703a and r2,r2,r3 + 10112c4: 8085883a add r2,r16,r2 + 10112c8: 20809526 beq r4,r2,1011520 <_realloc_r+0x52c> + 10112cc: 99bfff04 addi r6,r19,-4 + 10112d0: 01c00904 movi r7,36 + 10112d4: 39804536 bltu r7,r6,10113ec <_realloc_r+0x3f8> + 10112d8: 008004c4 movi r2,19 + 10112dc: 9009883a mov r4,r18 + 10112e0: 880b883a mov r5,r17 + 10112e4: 11800f2e bgeu r2,r6,1011324 <_realloc_r+0x330> + 10112e8: 90800017 ldw r2,0(r18) + 10112ec: 89400204 addi r5,r17,8 + 10112f0: 91000204 addi r4,r18,8 + 10112f4: 88800015 stw r2,0(r17) + 10112f8: 90c00117 ldw r3,4(r18) + 10112fc: 008006c4 movi r2,27 + 1011300: 88c00115 stw r3,4(r17) + 1011304: 1180072e bgeu r2,r6,1011324 <_realloc_r+0x330> + 1011308: 90c00217 ldw r3,8(r18) + 101130c: 89400404 addi r5,r17,16 + 1011310: 91000404 addi r4,r18,16 + 1011314: 88c00215 stw r3,8(r17) + 1011318: 90800317 ldw r2,12(r18) + 101131c: 88800315 stw r2,12(r17) + 1011320: 31c09126 beq r6,r7,1011568 <_realloc_r+0x574> + 1011324: 20800017 ldw r2,0(r4) + 1011328: 28800015 stw r2,0(r5) + 101132c: 20c00117 ldw r3,4(r4) + 1011330: 28c00115 stw r3,4(r5) + 1011334: 20800217 ldw r2,8(r4) + 1011338: 28800215 stw r2,8(r5) + 101133c: 900b883a mov r5,r18 + 1011340: b009883a mov r4,r22 + 1011344: 100f28c0 call 100f28c <_free_r> + 1011348: b009883a mov r4,r22 + 101134c: 10151a80 call 10151a8 <__malloc_unlock> + 1011350: 003f5e06 br 10110cc <_realloc_r+0xd8> + 1011354: 300b883a mov r5,r6 + 1011358: dfc00b17 ldw ra,44(sp) + 101135c: df000a17 ldw fp,40(sp) + 1011360: ddc00917 ldw r23,36(sp) + 1011364: dd800817 ldw r22,32(sp) + 1011368: dd400717 ldw r21,28(sp) + 101136c: dd000617 ldw r20,24(sp) + 1011370: dcc00517 ldw r19,20(sp) + 1011374: dc800417 ldw r18,16(sp) + 1011378: dc400317 ldw r17,12(sp) + 101137c: dc000217 ldw r16,8(sp) + 1011380: dec00c04 addi sp,sp,48 + 1011384: 100a1a41 jmpi 100a1a4 <_malloc_r> + 1011388: 38800117 ldw r2,4(r7) + 101138c: e54b883a add r5,fp,r21 + 1011390: 31000054 ori r4,r6,1 + 1011394: 1080004c andi r2,r2,1 + 1011398: 1704b03a or r2,r2,fp + 101139c: 38800115 stw r2,4(r7) + 10113a0: 29000115 stw r4,4(r5) + 10113a4: 2987883a add r3,r5,r6 + 10113a8: 18800117 ldw r2,4(r3) + 10113ac: 29400204 addi r5,r5,8 + 10113b0: b009883a mov r4,r22 + 10113b4: 10800054 ori r2,r2,1 + 10113b8: 18800115 stw r2,4(r3) + 10113bc: 100f28c0 call 100f28c <_free_r> + 10113c0: 003f3806 br 10110a4 <_realloc_r+0xb0> + 10113c4: 000d883a mov r6,zero + 10113c8: 0009883a mov r4,zero + 10113cc: 003f5d06 br 1011144 <_realloc_r+0x150> + 10113d0: 30c00217 ldw r3,8(r6) + 10113d4: 30800317 ldw r2,12(r6) + 10113d8: 800f883a mov r7,r16 + 10113dc: 84000204 addi r16,r16,8 + 10113e0: 10c00215 stw r3,8(r2) + 10113e4: 18800315 stw r2,12(r3) + 10113e8: 003f2306 br 1011078 <_realloc_r+0x84> + 10113ec: 8809883a mov r4,r17 + 10113f0: 900b883a mov r5,r18 + 10113f4: 100aadc0 call 100aadc + 10113f8: 003fd006 br 101133c <_realloc_r+0x348> + 10113fc: 30800117 ldw r2,4(r6) + 1011400: e0c00404 addi r3,fp,16 + 1011404: 1108703a and r4,r2,r4 + 1011408: 9905883a add r2,r19,r4 + 101140c: 10ff4d16 blt r2,r3,1011144 <_realloc_r+0x150> + 1011410: 1705c83a sub r2,r2,fp + 1011414: 870b883a add r5,r16,fp + 1011418: 10800054 ori r2,r2,1 + 101141c: 28800115 stw r2,4(r5) + 1011420: 80c00117 ldw r3,4(r16) + 1011424: 008040b4 movhi r2,258 + 1011428: 1086f004 addi r2,r2,7104 + 101142c: b009883a mov r4,r22 + 1011430: 18c0004c andi r3,r3,1 + 1011434: e0c6b03a or r3,fp,r3 + 1011438: 11400215 stw r5,8(r2) + 101143c: 80c00115 stw r3,4(r16) + 1011440: 10151a80 call 10151a8 <__malloc_unlock> + 1011444: 84400204 addi r17,r16,8 + 1011448: 003f2006 br 10110cc <_realloc_r+0xd8> + 101144c: 98a9883a add r20,r19,r2 + 1011450: 2509883a add r4,r4,r20 + 1011454: e0800404 addi r2,fp,16 + 1011458: d9000115 stw r4,4(sp) + 101145c: 20bf7016 blt r4,r2,1011220 <_realloc_r+0x22c> + 1011460: b8c00317 ldw r3,12(r23) + 1011464: b8800217 ldw r2,8(r23) + 1011468: 99bfff04 addi r6,r19,-4 + 101146c: 01400904 movi r5,36 + 1011470: 18800215 stw r2,8(r3) + 1011474: 10c00315 stw r3,12(r2) + 1011478: bc400204 addi r17,r23,8 + 101147c: 29804136 bltu r5,r6,1011584 <_realloc_r+0x590> + 1011480: 008004c4 movi r2,19 + 1011484: 9009883a mov r4,r18 + 1011488: 880f883a mov r7,r17 + 101148c: 11800f2e bgeu r2,r6,10114cc <_realloc_r+0x4d8> + 1011490: 90800017 ldw r2,0(r18) + 1011494: b9c00404 addi r7,r23,16 + 1011498: 91000204 addi r4,r18,8 + 101149c: b8800215 stw r2,8(r23) + 10114a0: 90c00117 ldw r3,4(r18) + 10114a4: 008006c4 movi r2,27 + 10114a8: b8c00315 stw r3,12(r23) + 10114ac: 1180072e bgeu r2,r6,10114cc <_realloc_r+0x4d8> + 10114b0: 90c00217 ldw r3,8(r18) + 10114b4: b9c00604 addi r7,r23,24 + 10114b8: 91000404 addi r4,r18,16 + 10114bc: b8c00415 stw r3,16(r23) + 10114c0: 90800317 ldw r2,12(r18) + 10114c4: b8800515 stw r2,20(r23) + 10114c8: 31404026 beq r6,r5,10115cc <_realloc_r+0x5d8> + 10114cc: 20800017 ldw r2,0(r4) + 10114d0: 38800015 stw r2,0(r7) + 10114d4: 20c00117 ldw r3,4(r4) + 10114d8: 38c00115 stw r3,4(r7) + 10114dc: 20800217 ldw r2,8(r4) + 10114e0: 38800215 stw r2,8(r7) + 10114e4: d8c00117 ldw r3,4(sp) + 10114e8: bf0b883a add r5,r23,fp + 10114ec: b009883a mov r4,r22 + 10114f0: 1f05c83a sub r2,r3,fp + 10114f4: 10800054 ori r2,r2,1 + 10114f8: 28800115 stw r2,4(r5) + 10114fc: b8c00117 ldw r3,4(r23) + 1011500: 008040b4 movhi r2,258 + 1011504: 1086f004 addi r2,r2,7104 + 1011508: 11400215 stw r5,8(r2) + 101150c: 18c0004c andi r3,r3,1 + 1011510: e0c6b03a or r3,fp,r3 + 1011514: b8c00115 stw r3,4(r23) + 1011518: 10151a80 call 10151a8 <__malloc_unlock> + 101151c: 003eeb06 br 10110cc <_realloc_r+0xd8> + 1011520: 20800117 ldw r2,4(r4) + 1011524: 00ffff04 movi r3,-4 + 1011528: 800f883a mov r7,r16 + 101152c: 10c4703a and r2,r2,r3 + 1011530: 98a9883a add r20,r19,r2 + 1011534: 84000204 addi r16,r16,8 + 1011538: 003ecf06 br 1011078 <_realloc_r+0x84> + 101153c: 900b883a mov r5,r18 + 1011540: 8009883a mov r4,r16 + 1011544: 100aadc0 call 100aadc + 1011548: dd000017 ldw r20,0(sp) + 101154c: b80f883a mov r7,r23 + 1011550: 003ec906 br 1011078 <_realloc_r+0x84> + 1011554: 900b883a mov r5,r18 + 1011558: 8009883a mov r4,r16 + 101155c: 100aadc0 call 100aadc + 1011560: b80f883a mov r7,r23 + 1011564: 003ec406 br 1011078 <_realloc_r+0x84> + 1011568: 90c00417 ldw r3,16(r18) + 101156c: 89400604 addi r5,r17,24 + 1011570: 91000604 addi r4,r18,24 + 1011574: 88c00415 stw r3,16(r17) + 1011578: 90800517 ldw r2,20(r18) + 101157c: 88800515 stw r2,20(r17) + 1011580: 003f6806 br 1011324 <_realloc_r+0x330> + 1011584: 900b883a mov r5,r18 + 1011588: 8809883a mov r4,r17 + 101158c: 100aadc0 call 100aadc + 1011590: 003fd406 br 10114e4 <_realloc_r+0x4f0> + 1011594: 90c00417 ldw r3,16(r18) + 1011598: 91000604 addi r4,r18,24 + 101159c: ba000804 addi r8,r23,32 + 10115a0: b8c00615 stw r3,24(r23) + 10115a4: 90800517 ldw r2,20(r18) + 10115a8: b8800715 stw r2,28(r23) + 10115ac: 003f1206 br 10111f8 <_realloc_r+0x204> + 10115b0: 90c00417 ldw r3,16(r18) + 10115b4: 91000604 addi r4,r18,24 + 10115b8: ba000804 addi r8,r23,32 + 10115bc: b8c00615 stw r3,24(r23) + 10115c0: 90800517 ldw r2,20(r18) + 10115c4: b8800715 stw r2,28(r23) + 10115c8: 003f3206 br 1011294 <_realloc_r+0x2a0> + 10115cc: 90c00417 ldw r3,16(r18) + 10115d0: 91000604 addi r4,r18,24 + 10115d4: b9c00804 addi r7,r23,32 + 10115d8: b8c00615 stw r3,24(r23) + 10115dc: 90800517 ldw r2,20(r18) + 10115e0: b8800715 stw r2,28(r23) + 10115e4: 003fb906 br 10114cc <_realloc_r+0x4d8> + +010115e8 <__isinfd>: + 10115e8: 200d883a mov r6,r4 + 10115ec: 0109c83a sub r4,zero,r4 + 10115f0: 2188b03a or r4,r4,r6 + 10115f4: 2008d7fa srli r4,r4,31 + 10115f8: 00a00034 movhi r2,32768 + 10115fc: 10bfffc4 addi r2,r2,-1 + 1011600: 1144703a and r2,r2,r5 + 1011604: 2088b03a or r4,r4,r2 + 1011608: 009ffc34 movhi r2,32752 + 101160c: 1105c83a sub r2,r2,r4 + 1011610: 0087c83a sub r3,zero,r2 + 1011614: 10c4b03a or r2,r2,r3 + 1011618: 1004d7fa srli r2,r2,31 + 101161c: 00c00044 movi r3,1 + 1011620: 1885c83a sub r2,r3,r2 + 1011624: f800283a ret + +01011628 <__isnand>: + 1011628: 200d883a mov r6,r4 + 101162c: 0109c83a sub r4,zero,r4 + 1011630: 2188b03a or r4,r4,r6 + 1011634: 2008d7fa srli r4,r4,31 + 1011638: 00a00034 movhi r2,32768 + 101163c: 10bfffc4 addi r2,r2,-1 + 1011640: 1144703a and r2,r2,r5 + 1011644: 2088b03a or r4,r4,r2 + 1011648: 009ffc34 movhi r2,32752 + 101164c: 1105c83a sub r2,r2,r4 + 1011650: 1004d7fa srli r2,r2,31 + 1011654: f800283a ret + +01011658 <__sclose>: + 1011658: 2940038f ldh r5,14(r5) + 101165c: 1011ad81 jmpi 1011ad8 <_close_r> + +01011660 <__sseek>: + 1011660: defffe04 addi sp,sp,-8 + 1011664: dc000015 stw r16,0(sp) + 1011668: 2821883a mov r16,r5 + 101166c: 2940038f ldh r5,14(r5) + 1011670: dfc00115 stw ra,4(sp) + 1011674: 1011d500 call 1011d50 <_lseek_r> + 1011678: 1007883a mov r3,r2 + 101167c: 00bfffc4 movi r2,-1 + 1011680: 18800926 beq r3,r2,10116a8 <__sseek+0x48> + 1011684: 8080030b ldhu r2,12(r16) + 1011688: 80c01415 stw r3,80(r16) + 101168c: 10840014 ori r2,r2,4096 + 1011690: 8080030d sth r2,12(r16) + 1011694: 1805883a mov r2,r3 + 1011698: dfc00117 ldw ra,4(sp) + 101169c: dc000017 ldw r16,0(sp) + 10116a0: dec00204 addi sp,sp,8 + 10116a4: f800283a ret + 10116a8: 8080030b ldhu r2,12(r16) + 10116ac: 10bbffcc andi r2,r2,61439 + 10116b0: 8080030d sth r2,12(r16) + 10116b4: 1805883a mov r2,r3 + 10116b8: dfc00117 ldw ra,4(sp) + 10116bc: dc000017 ldw r16,0(sp) + 10116c0: dec00204 addi sp,sp,8 + 10116c4: f800283a ret + +010116c8 <__swrite>: + 10116c8: 2880030b ldhu r2,12(r5) + 10116cc: defffb04 addi sp,sp,-20 + 10116d0: dcc00315 stw r19,12(sp) + 10116d4: 1080400c andi r2,r2,256 + 10116d8: dc800215 stw r18,8(sp) + 10116dc: dc400115 stw r17,4(sp) + 10116e0: dc000015 stw r16,0(sp) + 10116e4: 3027883a mov r19,r6 + 10116e8: 3825883a mov r18,r7 + 10116ec: dfc00415 stw ra,16(sp) + 10116f0: 2821883a mov r16,r5 + 10116f4: 000d883a mov r6,zero + 10116f8: 01c00084 movi r7,2 + 10116fc: 2023883a mov r17,r4 + 1011700: 10000226 beq r2,zero,101170c <__swrite+0x44> + 1011704: 2940038f ldh r5,14(r5) + 1011708: 1011d500 call 1011d50 <_lseek_r> + 101170c: 8080030b ldhu r2,12(r16) + 1011710: 8140038f ldh r5,14(r16) + 1011714: 8809883a mov r4,r17 + 1011718: 10bbffcc andi r2,r2,61439 + 101171c: 980d883a mov r6,r19 + 1011720: 900f883a mov r7,r18 + 1011724: 8080030d sth r2,12(r16) + 1011728: dfc00417 ldw ra,16(sp) + 101172c: dcc00317 ldw r19,12(sp) + 1011730: dc800217 ldw r18,8(sp) + 1011734: dc400117 ldw r17,4(sp) + 1011738: dc000017 ldw r16,0(sp) + 101173c: dec00504 addi sp,sp,20 + 1011740: 10119ac1 jmpi 10119ac <_write_r> + +01011744 <__sread>: + 1011744: defffe04 addi sp,sp,-8 + 1011748: dc000015 stw r16,0(sp) + 101174c: 2821883a mov r16,r5 + 1011750: 2940038f ldh r5,14(r5) + 1011754: dfc00115 stw ra,4(sp) + 1011758: 1011dc80 call 1011dc8 <_read_r> + 101175c: 1007883a mov r3,r2 + 1011760: 10000816 blt r2,zero,1011784 <__sread+0x40> + 1011764: 80801417 ldw r2,80(r16) + 1011768: 10c5883a add r2,r2,r3 + 101176c: 80801415 stw r2,80(r16) + 1011770: 1805883a mov r2,r3 + 1011774: dfc00117 ldw ra,4(sp) + 1011778: dc000017 ldw r16,0(sp) + 101177c: dec00204 addi sp,sp,8 + 1011780: f800283a ret + 1011784: 8080030b ldhu r2,12(r16) + 1011788: 10bbffcc andi r2,r2,61439 + 101178c: 8080030d sth r2,12(r16) + 1011790: 1805883a mov r2,r3 + 1011794: dfc00117 ldw ra,4(sp) + 1011798: dc000017 ldw r16,0(sp) + 101179c: dec00204 addi sp,sp,8 + 10117a0: f800283a ret + +010117a4 : + 10117a4: 2144b03a or r2,r4,r5 + 10117a8: 108000cc andi r2,r2,3 + 10117ac: 10001d1e bne r2,zero,1011824 + 10117b0: 200f883a mov r7,r4 + 10117b4: 28800017 ldw r2,0(r5) + 10117b8: 21000017 ldw r4,0(r4) + 10117bc: 280d883a mov r6,r5 + 10117c0: 2080161e bne r4,r2,101181c + 10117c4: 023fbff4 movhi r8,65279 + 10117c8: 423fbfc4 addi r8,r8,-257 + 10117cc: 2207883a add r3,r4,r8 + 10117d0: 01602074 movhi r5,32897 + 10117d4: 29602004 addi r5,r5,-32640 + 10117d8: 1946703a and r3,r3,r5 + 10117dc: 0104303a nor r2,zero,r4 + 10117e0: 10c4703a and r2,r2,r3 + 10117e4: 10001c1e bne r2,zero,1011858 + 10117e8: 4013883a mov r9,r8 + 10117ec: 2811883a mov r8,r5 + 10117f0: 00000106 br 10117f8 + 10117f4: 1800181e bne r3,zero,1011858 + 10117f8: 39c00104 addi r7,r7,4 + 10117fc: 39000017 ldw r4,0(r7) + 1011800: 31800104 addi r6,r6,4 + 1011804: 31400017 ldw r5,0(r6) + 1011808: 2245883a add r2,r4,r9 + 101180c: 1204703a and r2,r2,r8 + 1011810: 0106303a nor r3,zero,r4 + 1011814: 1886703a and r3,r3,r2 + 1011818: 217ff626 beq r4,r5,10117f4 + 101181c: 3809883a mov r4,r7 + 1011820: 300b883a mov r5,r6 + 1011824: 20c00007 ldb r3,0(r4) + 1011828: 1800051e bne r3,zero,1011840 + 101182c: 00000606 br 1011848 + 1011830: 21000044 addi r4,r4,1 + 1011834: 20c00007 ldb r3,0(r4) + 1011838: 29400044 addi r5,r5,1 + 101183c: 18000226 beq r3,zero,1011848 + 1011840: 28800007 ldb r2,0(r5) + 1011844: 18bffa26 beq r3,r2,1011830 + 1011848: 20c00003 ldbu r3,0(r4) + 101184c: 28800003 ldbu r2,0(r5) + 1011850: 1885c83a sub r2,r3,r2 + 1011854: f800283a ret + 1011858: 0005883a mov r2,zero + 101185c: f800283a ret + +01011860 <__swbuf_r>: + 1011860: defffc04 addi sp,sp,-16 + 1011864: dc400215 stw r17,8(sp) + 1011868: dc000115 stw r16,4(sp) + 101186c: dfc00315 stw ra,12(sp) + 1011870: 2023883a mov r17,r4 + 1011874: 2821883a mov r16,r5 + 1011878: 20000226 beq r4,zero,1011884 <__swbuf_r+0x24> + 101187c: 20800e17 ldw r2,56(r4) + 1011880: 10002f26 beq r2,zero,1011940 <__swbuf_r+0xe0> + 1011884: 3080030b ldhu r2,12(r6) + 1011888: 30c00617 ldw r3,24(r6) + 101188c: 1080020c andi r2,r2,8 + 1011890: 30c00215 stw r3,8(r6) + 1011894: 10002226 beq r2,zero,1011920 <__swbuf_r+0xc0> + 1011898: 30c00417 ldw r3,16(r6) + 101189c: 18002026 beq r3,zero,1011920 <__swbuf_r+0xc0> + 10118a0: 31000017 ldw r4,0(r6) + 10118a4: 30800517 ldw r2,20(r6) + 10118a8: 20c7c83a sub r3,r4,r3 + 10118ac: 18802f0e bge r3,r2,101196c <__swbuf_r+0x10c> + 10118b0: 19400044 addi r5,r3,1 + 10118b4: 30800217 ldw r2,8(r6) + 10118b8: 84003fcc andi r16,r16,255 + 10118bc: 20c00044 addi r3,r4,1 + 10118c0: 10bfffc4 addi r2,r2,-1 + 10118c4: 30800215 stw r2,8(r6) + 10118c8: 24000005 stb r16,0(r4) + 10118cc: 30800517 ldw r2,20(r6) + 10118d0: 30c00015 stw r3,0(r6) + 10118d4: 11400c26 beq r2,r5,1011908 <__swbuf_r+0xa8> + 10118d8: 3080030b ldhu r2,12(r6) + 10118dc: 1080004c andi r2,r2,1 + 10118e0: 1005003a cmpeq r2,r2,zero + 10118e4: 10000626 beq r2,zero,1011900 <__swbuf_r+0xa0> + 10118e8: 8005883a mov r2,r16 + 10118ec: dfc00317 ldw ra,12(sp) + 10118f0: dc400217 ldw r17,8(sp) + 10118f4: dc000117 ldw r16,4(sp) + 10118f8: dec00404 addi sp,sp,16 + 10118fc: f800283a ret + 1011900: 00800284 movi r2,10 + 1011904: 80bff81e bne r16,r2,10118e8 <__swbuf_r+0x88> + 1011908: 8809883a mov r4,r17 + 101190c: 300b883a mov r5,r6 + 1011910: 100ec700 call 100ec70 <_fflush_r> + 1011914: 103ff426 beq r2,zero,10118e8 <__swbuf_r+0x88> + 1011918: 043fffc4 movi r16,-1 + 101191c: 003ff206 br 10118e8 <__swbuf_r+0x88> + 1011920: 300b883a mov r5,r6 + 1011924: 8809883a mov r4,r17 + 1011928: d9800015 stw r6,0(sp) + 101192c: 100d3680 call 100d368 <__swsetup_r> + 1011930: d9800017 ldw r6,0(sp) + 1011934: 1000061e bne r2,zero,1011950 <__swbuf_r+0xf0> + 1011938: 30c00417 ldw r3,16(r6) + 101193c: 003fd806 br 10118a0 <__swbuf_r+0x40> + 1011940: d9800015 stw r6,0(sp) + 1011944: 100ef080 call 100ef08 <__sinit> + 1011948: d9800017 ldw r6,0(sp) + 101194c: 003fcd06 br 1011884 <__swbuf_r+0x24> + 1011950: 3080030b ldhu r2,12(r6) + 1011954: 00c00244 movi r3,9 + 1011958: 043fffc4 movi r16,-1 + 101195c: 10801014 ori r2,r2,64 + 1011960: 3080030d sth r2,12(r6) + 1011964: 88c00015 stw r3,0(r17) + 1011968: 003fdf06 br 10118e8 <__swbuf_r+0x88> + 101196c: 300b883a mov r5,r6 + 1011970: 8809883a mov r4,r17 + 1011974: d9800015 stw r6,0(sp) + 1011978: 100ec700 call 100ec70 <_fflush_r> + 101197c: d9800017 ldw r6,0(sp) + 1011980: 103fe51e bne r2,zero,1011918 <__swbuf_r+0xb8> + 1011984: 31000017 ldw r4,0(r6) + 1011988: 01400044 movi r5,1 + 101198c: 003fc906 br 10118b4 <__swbuf_r+0x54> + +01011990 <__swbuf>: + 1011990: 018040b4 movhi r6,258 + 1011994: 318dc804 addi r6,r6,14112 + 1011998: 2007883a mov r3,r4 + 101199c: 31000017 ldw r4,0(r6) + 10119a0: 280d883a mov r6,r5 + 10119a4: 180b883a mov r5,r3 + 10119a8: 10118601 jmpi 1011860 <__swbuf_r> + +010119ac <_write_r>: + 10119ac: defffd04 addi sp,sp,-12 + 10119b0: dc000015 stw r16,0(sp) + 10119b4: 040040b4 movhi r16,258 + 10119b8: 84150804 addi r16,r16,21536 + 10119bc: dc400115 stw r17,4(sp) + 10119c0: 80000015 stw zero,0(r16) + 10119c4: 2023883a mov r17,r4 + 10119c8: 2809883a mov r4,r5 + 10119cc: 300b883a mov r5,r6 + 10119d0: 380d883a mov r6,r7 + 10119d4: dfc00215 stw ra,8(sp) + 10119d8: 1014e180 call 1014e18 + 10119dc: 1007883a mov r3,r2 + 10119e0: 00bfffc4 movi r2,-1 + 10119e4: 18800626 beq r3,r2,1011a00 <_write_r+0x54> + 10119e8: 1805883a mov r2,r3 + 10119ec: dfc00217 ldw ra,8(sp) + 10119f0: dc400117 ldw r17,4(sp) + 10119f4: dc000017 ldw r16,0(sp) + 10119f8: dec00304 addi sp,sp,12 + 10119fc: f800283a ret + 1011a00: 80800017 ldw r2,0(r16) + 1011a04: 103ff826 beq r2,zero,10119e8 <_write_r+0x3c> + 1011a08: 88800015 stw r2,0(r17) + 1011a0c: 1805883a mov r2,r3 + 1011a10: dfc00217 ldw ra,8(sp) + 1011a14: dc400117 ldw r17,4(sp) + 1011a18: dc000017 ldw r16,0(sp) + 1011a1c: dec00304 addi sp,sp,12 + 1011a20: f800283a ret + +01011a24 <_calloc_r>: + 1011a24: 298b383a mul r5,r5,r6 + 1011a28: defffe04 addi sp,sp,-8 + 1011a2c: dc000015 stw r16,0(sp) + 1011a30: dfc00115 stw ra,4(sp) + 1011a34: 100a1a40 call 100a1a4 <_malloc_r> + 1011a38: 1021883a mov r16,r2 + 1011a3c: 01c00904 movi r7,36 + 1011a40: 10000d26 beq r2,zero,1011a78 <_calloc_r+0x54> + 1011a44: 10ffff17 ldw r3,-4(r2) + 1011a48: 1009883a mov r4,r2 + 1011a4c: 00bfff04 movi r2,-4 + 1011a50: 1886703a and r3,r3,r2 + 1011a54: 1887883a add r3,r3,r2 + 1011a58: 180d883a mov r6,r3 + 1011a5c: 000b883a mov r5,zero + 1011a60: 38c01736 bltu r7,r3,1011ac0 <_calloc_r+0x9c> + 1011a64: 008004c4 movi r2,19 + 1011a68: 10c00836 bltu r2,r3,1011a8c <_calloc_r+0x68> + 1011a6c: 20000215 stw zero,8(r4) + 1011a70: 20000015 stw zero,0(r4) + 1011a74: 20000115 stw zero,4(r4) + 1011a78: 8005883a mov r2,r16 + 1011a7c: dfc00117 ldw ra,4(sp) + 1011a80: dc000017 ldw r16,0(sp) + 1011a84: dec00204 addi sp,sp,8 + 1011a88: f800283a ret + 1011a8c: 008006c4 movi r2,27 + 1011a90: 80000015 stw zero,0(r16) + 1011a94: 80000115 stw zero,4(r16) + 1011a98: 81000204 addi r4,r16,8 + 1011a9c: 10fff32e bgeu r2,r3,1011a6c <_calloc_r+0x48> + 1011aa0: 80000215 stw zero,8(r16) + 1011aa4: 80000315 stw zero,12(r16) + 1011aa8: 81000404 addi r4,r16,16 + 1011aac: 19ffef1e bne r3,r7,1011a6c <_calloc_r+0x48> + 1011ab0: 81000604 addi r4,r16,24 + 1011ab4: 80000415 stw zero,16(r16) + 1011ab8: 80000515 stw zero,20(r16) + 1011abc: 003feb06 br 1011a6c <_calloc_r+0x48> + 1011ac0: 100abbc0 call 100abbc + 1011ac4: 8005883a mov r2,r16 + 1011ac8: dfc00117 ldw ra,4(sp) + 1011acc: dc000017 ldw r16,0(sp) + 1011ad0: dec00204 addi sp,sp,8 + 1011ad4: f800283a ret + +01011ad8 <_close_r>: + 1011ad8: defffd04 addi sp,sp,-12 + 1011adc: dc000015 stw r16,0(sp) + 1011ae0: 040040b4 movhi r16,258 + 1011ae4: 84150804 addi r16,r16,21536 + 1011ae8: dc400115 stw r17,4(sp) + 1011aec: 80000015 stw zero,0(r16) + 1011af0: 2023883a mov r17,r4 + 1011af4: 2809883a mov r4,r5 + 1011af8: dfc00215 stw ra,8(sp) + 1011afc: 10142700 call 1014270 + 1011b00: 1007883a mov r3,r2 + 1011b04: 00bfffc4 movi r2,-1 + 1011b08: 18800626 beq r3,r2,1011b24 <_close_r+0x4c> + 1011b0c: 1805883a mov r2,r3 + 1011b10: dfc00217 ldw ra,8(sp) + 1011b14: dc400117 ldw r17,4(sp) + 1011b18: dc000017 ldw r16,0(sp) + 1011b1c: dec00304 addi sp,sp,12 + 1011b20: f800283a ret + 1011b24: 80800017 ldw r2,0(r16) + 1011b28: 103ff826 beq r2,zero,1011b0c <_close_r+0x34> + 1011b2c: 88800015 stw r2,0(r17) + 1011b30: 1805883a mov r2,r3 + 1011b34: dfc00217 ldw ra,8(sp) + 1011b38: dc400117 ldw r17,4(sp) + 1011b3c: dc000017 ldw r16,0(sp) + 1011b40: dec00304 addi sp,sp,12 + 1011b44: f800283a ret + +01011b48 <_fclose_r>: + 1011b48: defffc04 addi sp,sp,-16 + 1011b4c: dc400115 stw r17,4(sp) + 1011b50: dc000015 stw r16,0(sp) + 1011b54: dfc00315 stw ra,12(sp) + 1011b58: dc800215 stw r18,8(sp) + 1011b5c: 2821883a mov r16,r5 + 1011b60: 2023883a mov r17,r4 + 1011b64: 28002926 beq r5,zero,1011c0c <_fclose_r+0xc4> + 1011b68: 100eef80 call 100eef8 <__sfp_lock_acquire> + 1011b6c: 88000226 beq r17,zero,1011b78 <_fclose_r+0x30> + 1011b70: 88800e17 ldw r2,56(r17) + 1011b74: 10002d26 beq r2,zero,1011c2c <_fclose_r+0xe4> + 1011b78: 8080030f ldh r2,12(r16) + 1011b7c: 10002226 beq r2,zero,1011c08 <_fclose_r+0xc0> + 1011b80: 8809883a mov r4,r17 + 1011b84: 800b883a mov r5,r16 + 1011b88: 100ec700 call 100ec70 <_fflush_r> + 1011b8c: 1025883a mov r18,r2 + 1011b90: 80800b17 ldw r2,44(r16) + 1011b94: 10000426 beq r2,zero,1011ba8 <_fclose_r+0x60> + 1011b98: 81400717 ldw r5,28(r16) + 1011b9c: 8809883a mov r4,r17 + 1011ba0: 103ee83a callr r2 + 1011ba4: 10002a16 blt r2,zero,1011c50 <_fclose_r+0x108> + 1011ba8: 8080030b ldhu r2,12(r16) + 1011bac: 1080200c andi r2,r2,128 + 1011bb0: 1000231e bne r2,zero,1011c40 <_fclose_r+0xf8> + 1011bb4: 81400c17 ldw r5,48(r16) + 1011bb8: 28000526 beq r5,zero,1011bd0 <_fclose_r+0x88> + 1011bbc: 80801004 addi r2,r16,64 + 1011bc0: 28800226 beq r5,r2,1011bcc <_fclose_r+0x84> + 1011bc4: 8809883a mov r4,r17 + 1011bc8: 100f28c0 call 100f28c <_free_r> + 1011bcc: 80000c15 stw zero,48(r16) + 1011bd0: 81401117 ldw r5,68(r16) + 1011bd4: 28000326 beq r5,zero,1011be4 <_fclose_r+0x9c> + 1011bd8: 8809883a mov r4,r17 + 1011bdc: 100f28c0 call 100f28c <_free_r> + 1011be0: 80001115 stw zero,68(r16) + 1011be4: 8000030d sth zero,12(r16) + 1011be8: 100eefc0 call 100eefc <__sfp_lock_release> + 1011bec: 9005883a mov r2,r18 + 1011bf0: dfc00317 ldw ra,12(sp) + 1011bf4: dc800217 ldw r18,8(sp) + 1011bf8: dc400117 ldw r17,4(sp) + 1011bfc: dc000017 ldw r16,0(sp) + 1011c00: dec00404 addi sp,sp,16 + 1011c04: f800283a ret + 1011c08: 100eefc0 call 100eefc <__sfp_lock_release> + 1011c0c: 0025883a mov r18,zero + 1011c10: 9005883a mov r2,r18 + 1011c14: dfc00317 ldw ra,12(sp) + 1011c18: dc800217 ldw r18,8(sp) + 1011c1c: dc400117 ldw r17,4(sp) + 1011c20: dc000017 ldw r16,0(sp) + 1011c24: dec00404 addi sp,sp,16 + 1011c28: f800283a ret + 1011c2c: 8809883a mov r4,r17 + 1011c30: 100ef080 call 100ef08 <__sinit> + 1011c34: 8080030f ldh r2,12(r16) + 1011c38: 103fd11e bne r2,zero,1011b80 <_fclose_r+0x38> + 1011c3c: 003ff206 br 1011c08 <_fclose_r+0xc0> + 1011c40: 81400417 ldw r5,16(r16) + 1011c44: 8809883a mov r4,r17 + 1011c48: 100f28c0 call 100f28c <_free_r> + 1011c4c: 003fd906 br 1011bb4 <_fclose_r+0x6c> + 1011c50: 04bfffc4 movi r18,-1 + 1011c54: 003fd406 br 1011ba8 <_fclose_r+0x60> + +01011c58 : + 1011c58: 008040b4 movhi r2,258 + 1011c5c: 108dc804 addi r2,r2,14112 + 1011c60: 200b883a mov r5,r4 + 1011c64: 11000017 ldw r4,0(r2) + 1011c68: 1011b481 jmpi 1011b48 <_fclose_r> + +01011c6c <_fstat_r>: + 1011c6c: defffd04 addi sp,sp,-12 + 1011c70: dc000015 stw r16,0(sp) + 1011c74: 040040b4 movhi r16,258 + 1011c78: 84150804 addi r16,r16,21536 + 1011c7c: dc400115 stw r17,4(sp) + 1011c80: 80000015 stw zero,0(r16) + 1011c84: 2023883a mov r17,r4 + 1011c88: 2809883a mov r4,r5 + 1011c8c: 300b883a mov r5,r6 + 1011c90: dfc00215 stw ra,8(sp) + 1011c94: 10144640 call 1014464 + 1011c98: 1007883a mov r3,r2 + 1011c9c: 00bfffc4 movi r2,-1 + 1011ca0: 18800626 beq r3,r2,1011cbc <_fstat_r+0x50> + 1011ca4: 1805883a mov r2,r3 + 1011ca8: dfc00217 ldw ra,8(sp) + 1011cac: dc400117 ldw r17,4(sp) + 1011cb0: dc000017 ldw r16,0(sp) + 1011cb4: dec00304 addi sp,sp,12 + 1011cb8: f800283a ret + 1011cbc: 80800017 ldw r2,0(r16) + 1011cc0: 103ff826 beq r2,zero,1011ca4 <_fstat_r+0x38> + 1011cc4: 88800015 stw r2,0(r17) + 1011cc8: 1805883a mov r2,r3 + 1011ccc: dfc00217 ldw ra,8(sp) + 1011cd0: dc400117 ldw r17,4(sp) + 1011cd4: dc000017 ldw r16,0(sp) + 1011cd8: dec00304 addi sp,sp,12 + 1011cdc: f800283a ret + +01011ce0 <_isatty_r>: + 1011ce0: defffd04 addi sp,sp,-12 + 1011ce4: dc000015 stw r16,0(sp) + 1011ce8: 040040b4 movhi r16,258 + 1011cec: 84150804 addi r16,r16,21536 + 1011cf0: dc400115 stw r17,4(sp) + 1011cf4: 80000015 stw zero,0(r16) + 1011cf8: 2023883a mov r17,r4 + 1011cfc: 2809883a mov r4,r5 + 1011d00: dfc00215 stw ra,8(sp) + 1011d04: 10145b80 call 10145b8 + 1011d08: 1007883a mov r3,r2 + 1011d0c: 00bfffc4 movi r2,-1 + 1011d10: 18800626 beq r3,r2,1011d2c <_isatty_r+0x4c> + 1011d14: 1805883a mov r2,r3 + 1011d18: dfc00217 ldw ra,8(sp) + 1011d1c: dc400117 ldw r17,4(sp) + 1011d20: dc000017 ldw r16,0(sp) + 1011d24: dec00304 addi sp,sp,12 + 1011d28: f800283a ret + 1011d2c: 80800017 ldw r2,0(r16) + 1011d30: 103ff826 beq r2,zero,1011d14 <_isatty_r+0x34> + 1011d34: 88800015 stw r2,0(r17) + 1011d38: 1805883a mov r2,r3 + 1011d3c: dfc00217 ldw ra,8(sp) + 1011d40: dc400117 ldw r17,4(sp) + 1011d44: dc000017 ldw r16,0(sp) + 1011d48: dec00304 addi sp,sp,12 + 1011d4c: f800283a ret + +01011d50 <_lseek_r>: + 1011d50: defffd04 addi sp,sp,-12 + 1011d54: dc000015 stw r16,0(sp) + 1011d58: 040040b4 movhi r16,258 + 1011d5c: 84150804 addi r16,r16,21536 + 1011d60: dc400115 stw r17,4(sp) + 1011d64: 80000015 stw zero,0(r16) + 1011d68: 2023883a mov r17,r4 + 1011d6c: 2809883a mov r4,r5 + 1011d70: 300b883a mov r5,r6 + 1011d74: 380d883a mov r6,r7 + 1011d78: dfc00215 stw ra,8(sp) + 1011d7c: 10149640 call 1014964 + 1011d80: 1007883a mov r3,r2 + 1011d84: 00bfffc4 movi r2,-1 + 1011d88: 18800626 beq r3,r2,1011da4 <_lseek_r+0x54> + 1011d8c: 1805883a mov r2,r3 + 1011d90: dfc00217 ldw ra,8(sp) + 1011d94: dc400117 ldw r17,4(sp) + 1011d98: dc000017 ldw r16,0(sp) + 1011d9c: dec00304 addi sp,sp,12 + 1011da0: f800283a ret + 1011da4: 80800017 ldw r2,0(r16) + 1011da8: 103ff826 beq r2,zero,1011d8c <_lseek_r+0x3c> + 1011dac: 88800015 stw r2,0(r17) + 1011db0: 1805883a mov r2,r3 + 1011db4: dfc00217 ldw ra,8(sp) + 1011db8: dc400117 ldw r17,4(sp) + 1011dbc: dc000017 ldw r16,0(sp) + 1011dc0: dec00304 addi sp,sp,12 + 1011dc4: f800283a ret + +01011dc8 <_read_r>: + 1011dc8: defffd04 addi sp,sp,-12 + 1011dcc: dc000015 stw r16,0(sp) + 1011dd0: 040040b4 movhi r16,258 + 1011dd4: 84150804 addi r16,r16,21536 + 1011dd8: dc400115 stw r17,4(sp) + 1011ddc: 80000015 stw zero,0(r16) + 1011de0: 2023883a mov r17,r4 + 1011de4: 2809883a mov r4,r5 + 1011de8: 300b883a mov r5,r6 + 1011dec: 380d883a mov r6,r7 + 1011df0: dfc00215 stw ra,8(sp) + 1011df4: 1014b7c0 call 1014b7c + 1011df8: 1007883a mov r3,r2 + 1011dfc: 00bfffc4 movi r2,-1 + 1011e00: 18800626 beq r3,r2,1011e1c <_read_r+0x54> + 1011e04: 1805883a mov r2,r3 + 1011e08: dfc00217 ldw ra,8(sp) + 1011e0c: dc400117 ldw r17,4(sp) + 1011e10: dc000017 ldw r16,0(sp) + 1011e14: dec00304 addi sp,sp,12 + 1011e18: f800283a ret + 1011e1c: 80800017 ldw r2,0(r16) + 1011e20: 103ff826 beq r2,zero,1011e04 <_read_r+0x3c> + 1011e24: 88800015 stw r2,0(r17) + 1011e28: 1805883a mov r2,r3 + 1011e2c: dfc00217 ldw ra,8(sp) + 1011e30: dc400117 ldw r17,4(sp) + 1011e34: dc000017 ldw r16,0(sp) + 1011e38: dec00304 addi sp,sp,12 + 1011e3c: f800283a ret + +01011e40 <__udivdi3>: + 1011e40: defff004 addi sp,sp,-64 + 1011e44: 2005883a mov r2,r4 + 1011e48: 3011883a mov r8,r6 + 1011e4c: df000e15 stw fp,56(sp) + 1011e50: dd000a15 stw r20,40(sp) + 1011e54: dc000615 stw r16,24(sp) + 1011e58: dfc00f15 stw ra,60(sp) + 1011e5c: ddc00d15 stw r23,52(sp) + 1011e60: dd800c15 stw r22,48(sp) + 1011e64: dd400b15 stw r21,44(sp) + 1011e68: dcc00915 stw r19,36(sp) + 1011e6c: dc800815 stw r18,32(sp) + 1011e70: dc400715 stw r17,28(sp) + 1011e74: 4021883a mov r16,r8 + 1011e78: 1039883a mov fp,r2 + 1011e7c: 2829883a mov r20,r5 + 1011e80: 38003b1e bne r7,zero,1011f70 <__udivdi3+0x130> + 1011e84: 2a005c36 bltu r5,r8,1011ff8 <__udivdi3+0x1b8> + 1011e88: 4000a626 beq r8,zero,1012124 <__udivdi3+0x2e4> + 1011e8c: 00bfffd4 movui r2,65535 + 1011e90: 14009e36 bltu r2,r16,101210c <__udivdi3+0x2cc> + 1011e94: 00803fc4 movi r2,255 + 1011e98: 14013d36 bltu r2,r16,1012390 <__udivdi3+0x550> + 1011e9c: 000b883a mov r5,zero + 1011ea0: 0005883a mov r2,zero + 1011ea4: 8084d83a srl r2,r16,r2 + 1011ea8: 010040b4 movhi r4,258 + 1011eac: 21065204 addi r4,r4,6472 + 1011eb0: 01800804 movi r6,32 + 1011eb4: 1105883a add r2,r2,r4 + 1011eb8: 10c00003 ldbu r3,0(r2) + 1011ebc: 28c7883a add r3,r5,r3 + 1011ec0: 30edc83a sub r22,r6,r3 + 1011ec4: b000ee1e bne r22,zero,1012280 <__udivdi3+0x440> + 1011ec8: 802ad43a srli r21,r16,16 + 1011ecc: 00800044 movi r2,1 + 1011ed0: a423c83a sub r17,r20,r16 + 1011ed4: 85ffffcc andi r23,r16,65535 + 1011ed8: d8800315 stw r2,12(sp) + 1011edc: 8809883a mov r4,r17 + 1011ee0: a80b883a mov r5,r21 + 1011ee4: 1013c340 call 1013c34 <__udivsi3> + 1011ee8: 8809883a mov r4,r17 + 1011eec: a80b883a mov r5,r21 + 1011ef0: 102d883a mov r22,r2 + 1011ef4: 1013c3c0 call 1013c3c <__umodsi3> + 1011ef8: 1004943a slli r2,r2,16 + 1011efc: e006d43a srli r3,fp,16 + 1011f00: bda3383a mul r17,r23,r22 + 1011f04: 10c4b03a or r2,r2,r3 + 1011f08: 1440042e bgeu r2,r17,1011f1c <__udivdi3+0xdc> + 1011f0c: 1405883a add r2,r2,r16 + 1011f10: b5bfffc4 addi r22,r22,-1 + 1011f14: 14000136 bltu r2,r16,1011f1c <__udivdi3+0xdc> + 1011f18: 14413d36 bltu r2,r17,1012410 <__udivdi3+0x5d0> + 1011f1c: 1463c83a sub r17,r2,r17 + 1011f20: 8809883a mov r4,r17 + 1011f24: a80b883a mov r5,r21 + 1011f28: 1013c340 call 1013c34 <__udivsi3> + 1011f2c: 8809883a mov r4,r17 + 1011f30: a80b883a mov r5,r21 + 1011f34: 1029883a mov r20,r2 + 1011f38: 1013c3c0 call 1013c3c <__umodsi3> + 1011f3c: 1004943a slli r2,r2,16 + 1011f40: bd09383a mul r4,r23,r20 + 1011f44: e0ffffcc andi r3,fp,65535 + 1011f48: 10c4b03a or r2,r2,r3 + 1011f4c: 1100042e bgeu r2,r4,1011f60 <__udivdi3+0x120> + 1011f50: 8085883a add r2,r16,r2 + 1011f54: a53fffc4 addi r20,r20,-1 + 1011f58: 14000136 bltu r2,r16,1011f60 <__udivdi3+0x120> + 1011f5c: 11012036 bltu r2,r4,10123e0 <__udivdi3+0x5a0> + 1011f60: b004943a slli r2,r22,16 + 1011f64: d9000317 ldw r4,12(sp) + 1011f68: a084b03a or r2,r20,r2 + 1011f6c: 00001506 br 1011fc4 <__udivdi3+0x184> + 1011f70: 380d883a mov r6,r7 + 1011f74: 29c06236 bltu r5,r7,1012100 <__udivdi3+0x2c0> + 1011f78: 00bfffd4 movui r2,65535 + 1011f7c: 11c05a36 bltu r2,r7,10120e8 <__udivdi3+0x2a8> + 1011f80: 00803fc4 movi r2,255 + 1011f84: 11c0fc36 bltu r2,r7,1012378 <__udivdi3+0x538> + 1011f88: 000b883a mov r5,zero + 1011f8c: 0005883a mov r2,zero + 1011f90: 3084d83a srl r2,r6,r2 + 1011f94: 010040b4 movhi r4,258 + 1011f98: 21065204 addi r4,r4,6472 + 1011f9c: 01c00804 movi r7,32 + 1011fa0: 1105883a add r2,r2,r4 + 1011fa4: 10c00003 ldbu r3,0(r2) + 1011fa8: 28c7883a add r3,r5,r3 + 1011fac: 38efc83a sub r23,r7,r3 + 1011fb0: b800691e bne r23,zero,1012158 <__udivdi3+0x318> + 1011fb4: 35000136 bltu r6,r20,1011fbc <__udivdi3+0x17c> + 1011fb8: e4005136 bltu fp,r16,1012100 <__udivdi3+0x2c0> + 1011fbc: 00800044 movi r2,1 + 1011fc0: 0009883a mov r4,zero + 1011fc4: 2007883a mov r3,r4 + 1011fc8: dfc00f17 ldw ra,60(sp) + 1011fcc: df000e17 ldw fp,56(sp) + 1011fd0: ddc00d17 ldw r23,52(sp) + 1011fd4: dd800c17 ldw r22,48(sp) + 1011fd8: dd400b17 ldw r21,44(sp) + 1011fdc: dd000a17 ldw r20,40(sp) + 1011fe0: dcc00917 ldw r19,36(sp) + 1011fe4: dc800817 ldw r18,32(sp) + 1011fe8: dc400717 ldw r17,28(sp) + 1011fec: dc000617 ldw r16,24(sp) + 1011ff0: dec01004 addi sp,sp,64 + 1011ff4: f800283a ret + 1011ff8: 00bfffd4 movui r2,65535 + 1011ffc: 12005036 bltu r2,r8,1012140 <__udivdi3+0x300> + 1012000: 00803fc4 movi r2,255 + 1012004: 1200e836 bltu r2,r8,10123a8 <__udivdi3+0x568> + 1012008: 000b883a mov r5,zero + 101200c: 0005883a mov r2,zero + 1012010: 8084d83a srl r2,r16,r2 + 1012014: 010040b4 movhi r4,258 + 1012018: 21065204 addi r4,r4,6472 + 101201c: 01800804 movi r6,32 + 1012020: 1105883a add r2,r2,r4 + 1012024: 10c00003 ldbu r3,0(r2) + 1012028: 28c7883a add r3,r5,r3 + 101202c: 30cbc83a sub r5,r6,r3 + 1012030: 28000626 beq r5,zero,101204c <__udivdi3+0x20c> + 1012034: 3145c83a sub r2,r6,r5 + 1012038: e084d83a srl r2,fp,r2 + 101203c: a146983a sll r3,r20,r5 + 1012040: e178983a sll fp,fp,r5 + 1012044: 8160983a sll r16,r16,r5 + 1012048: 18a8b03a or r20,r3,r2 + 101204c: 802ad43a srli r21,r16,16 + 1012050: a009883a mov r4,r20 + 1012054: 85ffffcc andi r23,r16,65535 + 1012058: a80b883a mov r5,r21 + 101205c: 1013c340 call 1013c34 <__udivsi3> + 1012060: a009883a mov r4,r20 + 1012064: a80b883a mov r5,r21 + 1012068: 102d883a mov r22,r2 + 101206c: 1013c3c0 call 1013c3c <__umodsi3> + 1012070: 1004943a slli r2,r2,16 + 1012074: e006d43a srli r3,fp,16 + 1012078: bda3383a mul r17,r23,r22 + 101207c: 10c4b03a or r2,r2,r3 + 1012080: 1440042e bgeu r2,r17,1012094 <__udivdi3+0x254> + 1012084: 1405883a add r2,r2,r16 + 1012088: b5bfffc4 addi r22,r22,-1 + 101208c: 14000136 bltu r2,r16,1012094 <__udivdi3+0x254> + 1012090: 1440d536 bltu r2,r17,10123e8 <__udivdi3+0x5a8> + 1012094: 1463c83a sub r17,r2,r17 + 1012098: 8809883a mov r4,r17 + 101209c: a80b883a mov r5,r21 + 10120a0: 1013c340 call 1013c34 <__udivsi3> + 10120a4: 8809883a mov r4,r17 + 10120a8: a80b883a mov r5,r21 + 10120ac: 1029883a mov r20,r2 + 10120b0: 1013c3c0 call 1013c3c <__umodsi3> + 10120b4: 1004943a slli r2,r2,16 + 10120b8: bd09383a mul r4,r23,r20 + 10120bc: e0ffffcc andi r3,fp,65535 + 10120c0: 10c4b03a or r2,r2,r3 + 10120c4: 1100042e bgeu r2,r4,10120d8 <__udivdi3+0x298> + 10120c8: 8085883a add r2,r16,r2 + 10120cc: a53fffc4 addi r20,r20,-1 + 10120d0: 14000136 bltu r2,r16,10120d8 <__udivdi3+0x298> + 10120d4: 1100c736 bltu r2,r4,10123f4 <__udivdi3+0x5b4> + 10120d8: b004943a slli r2,r22,16 + 10120dc: 0009883a mov r4,zero + 10120e0: a084b03a or r2,r20,r2 + 10120e4: 003fb706 br 1011fc4 <__udivdi3+0x184> + 10120e8: 00804034 movhi r2,256 + 10120ec: 10bfffc4 addi r2,r2,-1 + 10120f0: 11c0a436 bltu r2,r7,1012384 <__udivdi3+0x544> + 10120f4: 01400404 movi r5,16 + 10120f8: 2805883a mov r2,r5 + 10120fc: 003fa406 br 1011f90 <__udivdi3+0x150> + 1012100: 0005883a mov r2,zero + 1012104: 0009883a mov r4,zero + 1012108: 003fae06 br 1011fc4 <__udivdi3+0x184> + 101210c: 00804034 movhi r2,256 + 1012110: 10bfffc4 addi r2,r2,-1 + 1012114: 1400a136 bltu r2,r16,101239c <__udivdi3+0x55c> + 1012118: 01400404 movi r5,16 + 101211c: 2805883a mov r2,r5 + 1012120: 003f6006 br 1011ea4 <__udivdi3+0x64> + 1012124: 01000044 movi r4,1 + 1012128: 000b883a mov r5,zero + 101212c: 1013c340 call 1013c34 <__udivsi3> + 1012130: 1021883a mov r16,r2 + 1012134: 00bfffd4 movui r2,65535 + 1012138: 143ff436 bltu r2,r16,101210c <__udivdi3+0x2cc> + 101213c: 003f5506 br 1011e94 <__udivdi3+0x54> + 1012140: 00804034 movhi r2,256 + 1012144: 10bfffc4 addi r2,r2,-1 + 1012148: 12009a36 bltu r2,r8,10123b4 <__udivdi3+0x574> + 101214c: 01400404 movi r5,16 + 1012150: 2805883a mov r2,r5 + 1012154: 003fae06 br 1012010 <__udivdi3+0x1d0> + 1012158: 3dc5c83a sub r2,r7,r23 + 101215c: 35c8983a sll r4,r6,r23 + 1012160: 8086d83a srl r3,r16,r2 + 1012164: a0a2d83a srl r17,r20,r2 + 1012168: e084d83a srl r2,fp,r2 + 101216c: 20eab03a or r21,r4,r3 + 1012170: a82cd43a srli r22,r21,16 + 1012174: a5c6983a sll r3,r20,r23 + 1012178: 8809883a mov r4,r17 + 101217c: b00b883a mov r5,r22 + 1012180: 1886b03a or r3,r3,r2 + 1012184: d8c00215 stw r3,8(sp) + 1012188: 1013c340 call 1013c34 <__udivsi3> + 101218c: 8809883a mov r4,r17 + 1012190: b00b883a mov r5,r22 + 1012194: 1029883a mov r20,r2 + 1012198: 1013c3c0 call 1013c3c <__umodsi3> + 101219c: a8ffffcc andi r3,r21,65535 + 10121a0: d8c00515 stw r3,20(sp) + 10121a4: d9000217 ldw r4,8(sp) + 10121a8: d9400517 ldw r5,20(sp) + 10121ac: 1004943a slli r2,r2,16 + 10121b0: 2006d43a srli r3,r4,16 + 10121b4: 85e0983a sll r16,r16,r23 + 10121b8: 2d23383a mul r17,r5,r20 + 10121bc: 10c4b03a or r2,r2,r3 + 10121c0: dc000015 stw r16,0(sp) + 10121c4: 1440032e bgeu r2,r17,10121d4 <__udivdi3+0x394> + 10121c8: 1545883a add r2,r2,r21 + 10121cc: a53fffc4 addi r20,r20,-1 + 10121d0: 15407f2e bgeu r2,r21,10123d0 <__udivdi3+0x590> + 10121d4: 1463c83a sub r17,r2,r17 + 10121d8: 8809883a mov r4,r17 + 10121dc: b00b883a mov r5,r22 + 10121e0: 1013c340 call 1013c34 <__udivsi3> + 10121e4: 8809883a mov r4,r17 + 10121e8: b00b883a mov r5,r22 + 10121ec: 1021883a mov r16,r2 + 10121f0: 1013c3c0 call 1013c3c <__umodsi3> + 10121f4: d8c00517 ldw r3,20(sp) + 10121f8: d9000217 ldw r4,8(sp) + 10121fc: 1004943a slli r2,r2,16 + 1012200: 1c0f383a mul r7,r3,r16 + 1012204: 20ffffcc andi r3,r4,65535 + 1012208: 10e2b03a or r17,r2,r3 + 101220c: 89c0032e bgeu r17,r7,101221c <__udivdi3+0x3dc> + 1012210: 8d63883a add r17,r17,r21 + 1012214: 843fffc4 addi r16,r16,-1 + 1012218: 8d40692e bgeu r17,r21,10123c0 <__udivdi3+0x580> + 101221c: a008943a slli r4,r20,16 + 1012220: d9400017 ldw r5,0(sp) + 1012224: 89e3c83a sub r17,r17,r7 + 1012228: 8110b03a or r8,r16,r4 + 101222c: 280cd43a srli r6,r5,16 + 1012230: 28ffffcc andi r3,r5,65535 + 1012234: 40bfffcc andi r2,r8,65535 + 1012238: 400ad43a srli r5,r8,16 + 101223c: 10d3383a mul r9,r2,r3 + 1012240: 1185383a mul r2,r2,r6 + 1012244: 28c7383a mul r3,r5,r3 + 1012248: 4808d43a srli r4,r9,16 + 101224c: 298b383a mul r5,r5,r6 + 1012250: 10c5883a add r2,r2,r3 + 1012254: 2089883a add r4,r4,r2 + 1012258: 20c0022e bgeu r4,r3,1012264 <__udivdi3+0x424> + 101225c: 00800074 movhi r2,1 + 1012260: 288b883a add r5,r5,r2 + 1012264: 2004d43a srli r2,r4,16 + 1012268: 288b883a add r5,r5,r2 + 101226c: 89403f36 bltu r17,r5,101236c <__udivdi3+0x52c> + 1012270: 89403926 beq r17,r5,1012358 <__udivdi3+0x518> + 1012274: 4005883a mov r2,r8 + 1012278: 0009883a mov r4,zero + 101227c: 003f5106 br 1011fc4 <__udivdi3+0x184> + 1012280: 85a0983a sll r16,r16,r22 + 1012284: 3585c83a sub r2,r6,r22 + 1012288: a0a2d83a srl r17,r20,r2 + 101228c: 802ad43a srli r21,r16,16 + 1012290: e084d83a srl r2,fp,r2 + 1012294: a586983a sll r3,r20,r22 + 1012298: 8809883a mov r4,r17 + 101229c: a80b883a mov r5,r21 + 10122a0: 1886b03a or r3,r3,r2 + 10122a4: d8c00115 stw r3,4(sp) + 10122a8: 1013c340 call 1013c34 <__udivsi3> + 10122ac: 8809883a mov r4,r17 + 10122b0: a80b883a mov r5,r21 + 10122b4: d8800415 stw r2,16(sp) + 10122b8: 1013c3c0 call 1013c3c <__umodsi3> + 10122bc: d9000117 ldw r4,4(sp) + 10122c0: d9400417 ldw r5,16(sp) + 10122c4: 1004943a slli r2,r2,16 + 10122c8: 85ffffcc andi r23,r16,65535 + 10122cc: 2006d43a srli r3,r4,16 + 10122d0: b963383a mul r17,r23,r5 + 10122d4: 10c4b03a or r2,r2,r3 + 10122d8: 1440042e bgeu r2,r17,10122ec <__udivdi3+0x4ac> + 10122dc: 297fffc4 addi r5,r5,-1 + 10122e0: 1405883a add r2,r2,r16 + 10122e4: d9400415 stw r5,16(sp) + 10122e8: 1400442e bgeu r2,r16,10123fc <__udivdi3+0x5bc> + 10122ec: 1463c83a sub r17,r2,r17 + 10122f0: 8809883a mov r4,r17 + 10122f4: a80b883a mov r5,r21 + 10122f8: 1013c340 call 1013c34 <__udivsi3> + 10122fc: 8809883a mov r4,r17 + 1012300: a80b883a mov r5,r21 + 1012304: 1029883a mov r20,r2 + 1012308: 1013c3c0 call 1013c3c <__umodsi3> + 101230c: d9400117 ldw r5,4(sp) + 1012310: 1004943a slli r2,r2,16 + 1012314: bd09383a mul r4,r23,r20 + 1012318: 28ffffcc andi r3,r5,65535 + 101231c: 10c6b03a or r3,r2,r3 + 1012320: 1900062e bgeu r3,r4,101233c <__udivdi3+0x4fc> + 1012324: 1c07883a add r3,r3,r16 + 1012328: a53fffc4 addi r20,r20,-1 + 101232c: 1c000336 bltu r3,r16,101233c <__udivdi3+0x4fc> + 1012330: 1900022e bgeu r3,r4,101233c <__udivdi3+0x4fc> + 1012334: a53fffc4 addi r20,r20,-1 + 1012338: 1c07883a add r3,r3,r16 + 101233c: d9400417 ldw r5,16(sp) + 1012340: e5b8983a sll fp,fp,r22 + 1012344: 1923c83a sub r17,r3,r4 + 1012348: 2804943a slli r2,r5,16 + 101234c: a0a8b03a or r20,r20,r2 + 1012350: dd000315 stw r20,12(sp) + 1012354: 003ee106 br 1011edc <__udivdi3+0x9c> + 1012358: 2004943a slli r2,r4,16 + 101235c: e5c8983a sll r4,fp,r23 + 1012360: 48ffffcc andi r3,r9,65535 + 1012364: 10c5883a add r2,r2,r3 + 1012368: 20bfc22e bgeu r4,r2,1012274 <__udivdi3+0x434> + 101236c: 40bfffc4 addi r2,r8,-1 + 1012370: 0009883a mov r4,zero + 1012374: 003f1306 br 1011fc4 <__udivdi3+0x184> + 1012378: 01400204 movi r5,8 + 101237c: 2805883a mov r2,r5 + 1012380: 003f0306 br 1011f90 <__udivdi3+0x150> + 1012384: 01400604 movi r5,24 + 1012388: 2805883a mov r2,r5 + 101238c: 003f0006 br 1011f90 <__udivdi3+0x150> + 1012390: 01400204 movi r5,8 + 1012394: 2805883a mov r2,r5 + 1012398: 003ec206 br 1011ea4 <__udivdi3+0x64> + 101239c: 01400604 movi r5,24 + 10123a0: 2805883a mov r2,r5 + 10123a4: 003ebf06 br 1011ea4 <__udivdi3+0x64> + 10123a8: 01400204 movi r5,8 + 10123ac: 2805883a mov r2,r5 + 10123b0: 003f1706 br 1012010 <__udivdi3+0x1d0> + 10123b4: 01400604 movi r5,24 + 10123b8: 2805883a mov r2,r5 + 10123bc: 003f1406 br 1012010 <__udivdi3+0x1d0> + 10123c0: 89ff962e bgeu r17,r7,101221c <__udivdi3+0x3dc> + 10123c4: 8d63883a add r17,r17,r21 + 10123c8: 843fffc4 addi r16,r16,-1 + 10123cc: 003f9306 br 101221c <__udivdi3+0x3dc> + 10123d0: 147f802e bgeu r2,r17,10121d4 <__udivdi3+0x394> + 10123d4: a53fffc4 addi r20,r20,-1 + 10123d8: 1545883a add r2,r2,r21 + 10123dc: 003f7d06 br 10121d4 <__udivdi3+0x394> + 10123e0: a53fffc4 addi r20,r20,-1 + 10123e4: 003ede06 br 1011f60 <__udivdi3+0x120> + 10123e8: b5bfffc4 addi r22,r22,-1 + 10123ec: 1405883a add r2,r2,r16 + 10123f0: 003f2806 br 1012094 <__udivdi3+0x254> + 10123f4: a53fffc4 addi r20,r20,-1 + 10123f8: 003f3706 br 10120d8 <__udivdi3+0x298> + 10123fc: 147fbb2e bgeu r2,r17,10122ec <__udivdi3+0x4ac> + 1012400: 297fffc4 addi r5,r5,-1 + 1012404: 1405883a add r2,r2,r16 + 1012408: d9400415 stw r5,16(sp) + 101240c: 003fb706 br 10122ec <__udivdi3+0x4ac> + 1012410: b5bfffc4 addi r22,r22,-1 + 1012414: 1405883a add r2,r2,r16 + 1012418: 003ec006 br 1011f1c <__udivdi3+0xdc> + +0101241c <__umoddi3>: + 101241c: defff104 addi sp,sp,-60 + 1012420: dd800b15 stw r22,44(sp) + 1012424: dd000915 stw r20,36(sp) + 1012428: dc000515 stw r16,20(sp) + 101242c: dfc00e15 stw ra,56(sp) + 1012430: df000d15 stw fp,52(sp) + 1012434: ddc00c15 stw r23,48(sp) + 1012438: dd400a15 stw r21,40(sp) + 101243c: dcc00815 stw r19,32(sp) + 1012440: dc800715 stw r18,28(sp) + 1012444: dc400615 stw r17,24(sp) + 1012448: 3021883a mov r16,r6 + 101244c: 202d883a mov r22,r4 + 1012450: 2829883a mov r20,r5 + 1012454: 38002b1e bne r7,zero,1012504 <__umoddi3+0xe8> + 1012458: 29805036 bltu r5,r6,101259c <__umoddi3+0x180> + 101245c: 30008a26 beq r6,zero,1012688 <__umoddi3+0x26c> + 1012460: 00bfffd4 movui r2,65535 + 1012464: 14008236 bltu r2,r16,1012670 <__umoddi3+0x254> + 1012468: 00803fc4 movi r2,255 + 101246c: 14013636 bltu r2,r16,1012948 <__umoddi3+0x52c> + 1012470: 000b883a mov r5,zero + 1012474: 0005883a mov r2,zero + 1012478: 8084d83a srl r2,r16,r2 + 101247c: 010040b4 movhi r4,258 + 1012480: 21065204 addi r4,r4,6472 + 1012484: 01800804 movi r6,32 + 1012488: 1105883a add r2,r2,r4 + 101248c: 10c00003 ldbu r3,0(r2) + 1012490: 28c7883a add r3,r5,r3 + 1012494: 30efc83a sub r23,r6,r3 + 1012498: b800941e bne r23,zero,10126ec <__umoddi3+0x2d0> + 101249c: 802ad43a srli r21,r16,16 + 10124a0: a423c83a sub r17,r20,r16 + 10124a4: 0039883a mov fp,zero + 10124a8: 853fffcc andi r20,r16,65535 + 10124ac: 8809883a mov r4,r17 + 10124b0: a80b883a mov r5,r21 + 10124b4: 1013c340 call 1013c34 <__udivsi3> + 10124b8: 8809883a mov r4,r17 + 10124bc: a80b883a mov r5,r21 + 10124c0: a0a3383a mul r17,r20,r2 + 10124c4: 1013c3c0 call 1013c3c <__umodsi3> + 10124c8: 1004943a slli r2,r2,16 + 10124cc: b006d43a srli r3,r22,16 + 10124d0: 10c4b03a or r2,r2,r3 + 10124d4: 1440032e bgeu r2,r17,10124e4 <__umoddi3+0xc8> + 10124d8: 1405883a add r2,r2,r16 + 10124dc: 14000136 bltu r2,r16,10124e4 <__umoddi3+0xc8> + 10124e0: 14413536 bltu r2,r17,10129b8 <__umoddi3+0x59c> + 10124e4: 1463c83a sub r17,r2,r17 + 10124e8: 8809883a mov r4,r17 + 10124ec: a80b883a mov r5,r21 + 10124f0: 1013c340 call 1013c34 <__udivsi3> + 10124f4: 8809883a mov r4,r17 + 10124f8: a0a3383a mul r17,r20,r2 + 10124fc: a80b883a mov r5,r21 + 1012500: 00004d06 br 1012638 <__umoddi3+0x21c> + 1012504: 380d883a mov r6,r7 + 1012508: 29c0102e bgeu r5,r7,101254c <__umoddi3+0x130> + 101250c: 2011883a mov r8,r4 + 1012510: 2813883a mov r9,r5 + 1012514: 4005883a mov r2,r8 + 1012518: 4807883a mov r3,r9 + 101251c: dfc00e17 ldw ra,56(sp) + 1012520: df000d17 ldw fp,52(sp) + 1012524: ddc00c17 ldw r23,48(sp) + 1012528: dd800b17 ldw r22,44(sp) + 101252c: dd400a17 ldw r21,40(sp) + 1012530: dd000917 ldw r20,36(sp) + 1012534: dcc00817 ldw r19,32(sp) + 1012538: dc800717 ldw r18,28(sp) + 101253c: dc400617 ldw r17,24(sp) + 1012540: dc000517 ldw r16,20(sp) + 1012544: dec00f04 addi sp,sp,60 + 1012548: f800283a ret + 101254c: 00bfffd4 movui r2,65535 + 1012550: 11c05a36 bltu r2,r7,10126bc <__umoddi3+0x2a0> + 1012554: 00803fc4 movi r2,255 + 1012558: 11c0fe36 bltu r2,r7,1012954 <__umoddi3+0x538> + 101255c: 000b883a mov r5,zero + 1012560: 0005883a mov r2,zero + 1012564: 3084d83a srl r2,r6,r2 + 1012568: 010040b4 movhi r4,258 + 101256c: 21065204 addi r4,r4,6472 + 1012570: 01c00804 movi r7,32 + 1012574: 1105883a add r2,r2,r4 + 1012578: 10c00003 ldbu r3,0(r2) + 101257c: 28c7883a add r3,r5,r3 + 1012580: 38ebc83a sub r21,r7,r3 + 1012584: a800851e bne r21,zero,101279c <__umoddi3+0x380> + 1012588: 35005236 bltu r6,r20,10126d4 <__umoddi3+0x2b8> + 101258c: b400512e bgeu r22,r16,10126d4 <__umoddi3+0x2b8> + 1012590: b011883a mov r8,r22 + 1012594: a013883a mov r9,r20 + 1012598: 003fde06 br 1012514 <__umoddi3+0xf8> + 101259c: 00bfffd4 movui r2,65535 + 10125a0: 11804036 bltu r2,r6,10126a4 <__umoddi3+0x288> + 10125a4: 00803fc4 movi r2,255 + 10125a8: 1180ed36 bltu r2,r6,1012960 <__umoddi3+0x544> + 10125ac: 000b883a mov r5,zero + 10125b0: 0005883a mov r2,zero + 10125b4: 8084d83a srl r2,r16,r2 + 10125b8: 010040b4 movhi r4,258 + 10125bc: 21065204 addi r4,r4,6472 + 10125c0: 01800804 movi r6,32 + 10125c4: 1105883a add r2,r2,r4 + 10125c8: 10c00003 ldbu r3,0(r2) + 10125cc: 28c7883a add r3,r5,r3 + 10125d0: 30c7c83a sub r3,r6,r3 + 10125d4: 1800bf1e bne r3,zero,10128d4 <__umoddi3+0x4b8> + 10125d8: 0039883a mov fp,zero + 10125dc: 802ad43a srli r21,r16,16 + 10125e0: a009883a mov r4,r20 + 10125e4: 85ffffcc andi r23,r16,65535 + 10125e8: a80b883a mov r5,r21 + 10125ec: 1013c340 call 1013c34 <__udivsi3> + 10125f0: a009883a mov r4,r20 + 10125f4: a80b883a mov r5,r21 + 10125f8: b8a3383a mul r17,r23,r2 + 10125fc: 1013c3c0 call 1013c3c <__umodsi3> + 1012600: 1004943a slli r2,r2,16 + 1012604: b006d43a srli r3,r22,16 + 1012608: 10c4b03a or r2,r2,r3 + 101260c: 1440032e bgeu r2,r17,101261c <__umoddi3+0x200> + 1012610: 1405883a add r2,r2,r16 + 1012614: 14000136 bltu r2,r16,101261c <__umoddi3+0x200> + 1012618: 1440e536 bltu r2,r17,10129b0 <__umoddi3+0x594> + 101261c: 1463c83a sub r17,r2,r17 + 1012620: 8809883a mov r4,r17 + 1012624: a80b883a mov r5,r21 + 1012628: 1013c340 call 1013c34 <__udivsi3> + 101262c: 8809883a mov r4,r17 + 1012630: b8a3383a mul r17,r23,r2 + 1012634: a80b883a mov r5,r21 + 1012638: 1013c3c0 call 1013c3c <__umodsi3> + 101263c: 1004943a slli r2,r2,16 + 1012640: b0ffffcc andi r3,r22,65535 + 1012644: 10c4b03a or r2,r2,r3 + 1012648: 1440042e bgeu r2,r17,101265c <__umoddi3+0x240> + 101264c: 1405883a add r2,r2,r16 + 1012650: 14000236 bltu r2,r16,101265c <__umoddi3+0x240> + 1012654: 1440012e bgeu r2,r17,101265c <__umoddi3+0x240> + 1012658: 1405883a add r2,r2,r16 + 101265c: 1445c83a sub r2,r2,r17 + 1012660: 1724d83a srl r18,r2,fp + 1012664: 0013883a mov r9,zero + 1012668: 9011883a mov r8,r18 + 101266c: 003fa906 br 1012514 <__umoddi3+0xf8> + 1012670: 00804034 movhi r2,256 + 1012674: 10bfffc4 addi r2,r2,-1 + 1012678: 1400b036 bltu r2,r16,101293c <__umoddi3+0x520> + 101267c: 01400404 movi r5,16 + 1012680: 2805883a mov r2,r5 + 1012684: 003f7c06 br 1012478 <__umoddi3+0x5c> + 1012688: 01000044 movi r4,1 + 101268c: 000b883a mov r5,zero + 1012690: 1013c340 call 1013c34 <__udivsi3> + 1012694: 1021883a mov r16,r2 + 1012698: 00bfffd4 movui r2,65535 + 101269c: 143ff436 bltu r2,r16,1012670 <__umoddi3+0x254> + 10126a0: 003f7106 br 1012468 <__umoddi3+0x4c> + 10126a4: 00804034 movhi r2,256 + 10126a8: 10bfffc4 addi r2,r2,-1 + 10126ac: 1180af36 bltu r2,r6,101296c <__umoddi3+0x550> + 10126b0: 01400404 movi r5,16 + 10126b4: 2805883a mov r2,r5 + 10126b8: 003fbe06 br 10125b4 <__umoddi3+0x198> + 10126bc: 00804034 movhi r2,256 + 10126c0: 10bfffc4 addi r2,r2,-1 + 10126c4: 11c0ac36 bltu r2,r7,1012978 <__umoddi3+0x55c> + 10126c8: 01400404 movi r5,16 + 10126cc: 2805883a mov r2,r5 + 10126d0: 003fa406 br 1012564 <__umoddi3+0x148> + 10126d4: b409c83a sub r4,r22,r16 + 10126d8: b105803a cmpltu r2,r22,r4 + 10126dc: a187c83a sub r3,r20,r6 + 10126e0: 18a9c83a sub r20,r3,r2 + 10126e4: 202d883a mov r22,r4 + 10126e8: 003fa906 br 1012590 <__umoddi3+0x174> + 10126ec: 85e0983a sll r16,r16,r23 + 10126f0: 35c5c83a sub r2,r6,r23 + 10126f4: a0a2d83a srl r17,r20,r2 + 10126f8: 802ad43a srli r21,r16,16 + 10126fc: b084d83a srl r2,r22,r2 + 1012700: a5c6983a sll r3,r20,r23 + 1012704: 8809883a mov r4,r17 + 1012708: a80b883a mov r5,r21 + 101270c: 1886b03a or r3,r3,r2 + 1012710: d8c00115 stw r3,4(sp) + 1012714: 853fffcc andi r20,r16,65535 + 1012718: 1013c340 call 1013c34 <__udivsi3> + 101271c: 8809883a mov r4,r17 + 1012720: a80b883a mov r5,r21 + 1012724: a0a3383a mul r17,r20,r2 + 1012728: 1013c3c0 call 1013c3c <__umodsi3> + 101272c: d9000117 ldw r4,4(sp) + 1012730: 1004943a slli r2,r2,16 + 1012734: b839883a mov fp,r23 + 1012738: 2006d43a srli r3,r4,16 + 101273c: 10c4b03a or r2,r2,r3 + 1012740: 1440022e bgeu r2,r17,101274c <__umoddi3+0x330> + 1012744: 1405883a add r2,r2,r16 + 1012748: 1400962e bgeu r2,r16,10129a4 <__umoddi3+0x588> + 101274c: 1463c83a sub r17,r2,r17 + 1012750: 8809883a mov r4,r17 + 1012754: a80b883a mov r5,r21 + 1012758: 1013c340 call 1013c34 <__udivsi3> + 101275c: 8809883a mov r4,r17 + 1012760: a80b883a mov r5,r21 + 1012764: a0a3383a mul r17,r20,r2 + 1012768: 1013c3c0 call 1013c3c <__umodsi3> + 101276c: d9400117 ldw r5,4(sp) + 1012770: 1004943a slli r2,r2,16 + 1012774: 28ffffcc andi r3,r5,65535 + 1012778: 10c4b03a or r2,r2,r3 + 101277c: 1440042e bgeu r2,r17,1012790 <__umoddi3+0x374> + 1012780: 1405883a add r2,r2,r16 + 1012784: 14000236 bltu r2,r16,1012790 <__umoddi3+0x374> + 1012788: 1440012e bgeu r2,r17,1012790 <__umoddi3+0x374> + 101278c: 1405883a add r2,r2,r16 + 1012790: b5ec983a sll r22,r22,r23 + 1012794: 1463c83a sub r17,r2,r17 + 1012798: 003f4406 br 10124ac <__umoddi3+0x90> + 101279c: 3d4fc83a sub r7,r7,r21 + 10127a0: 3546983a sll r3,r6,r21 + 10127a4: 81c4d83a srl r2,r16,r7 + 10127a8: a1e2d83a srl r17,r20,r7 + 10127ac: a54c983a sll r6,r20,r21 + 10127b0: 18aeb03a or r23,r3,r2 + 10127b4: b828d43a srli r20,r23,16 + 10127b8: b1c4d83a srl r2,r22,r7 + 10127bc: 8809883a mov r4,r17 + 10127c0: a00b883a mov r5,r20 + 10127c4: 308cb03a or r6,r6,r2 + 10127c8: d9c00315 stw r7,12(sp) + 10127cc: d9800215 stw r6,8(sp) + 10127d0: 1013c340 call 1013c34 <__udivsi3> + 10127d4: 8809883a mov r4,r17 + 10127d8: a00b883a mov r5,r20 + 10127dc: 1039883a mov fp,r2 + 10127e0: 1013c3c0 call 1013c3c <__umodsi3> + 10127e4: b8ffffcc andi r3,r23,65535 + 10127e8: d8c00415 stw r3,16(sp) + 10127ec: d9000217 ldw r4,8(sp) + 10127f0: d9400417 ldw r5,16(sp) + 10127f4: 1004943a slli r2,r2,16 + 10127f8: 2006d43a srli r3,r4,16 + 10127fc: 8560983a sll r16,r16,r21 + 1012800: 2f23383a mul r17,r5,fp + 1012804: 10c4b03a or r2,r2,r3 + 1012808: dc000015 stw r16,0(sp) + 101280c: b56c983a sll r22,r22,r21 + 1012810: 1440032e bgeu r2,r17,1012820 <__umoddi3+0x404> + 1012814: 15c5883a add r2,r2,r23 + 1012818: e73fffc4 addi fp,fp,-1 + 101281c: 15c05d2e bgeu r2,r23,1012994 <__umoddi3+0x578> + 1012820: 1463c83a sub r17,r2,r17 + 1012824: 8809883a mov r4,r17 + 1012828: a00b883a mov r5,r20 + 101282c: 1013c340 call 1013c34 <__udivsi3> + 1012830: 8809883a mov r4,r17 + 1012834: a00b883a mov r5,r20 + 1012838: 1021883a mov r16,r2 + 101283c: 1013c3c0 call 1013c3c <__umodsi3> + 1012840: d8c00417 ldw r3,16(sp) + 1012844: d9000217 ldw r4,8(sp) + 1012848: 1004943a slli r2,r2,16 + 101284c: 1c23383a mul r17,r3,r16 + 1012850: 20ffffcc andi r3,r4,65535 + 1012854: 10ceb03a or r7,r2,r3 + 1012858: 3c40032e bgeu r7,r17,1012868 <__umoddi3+0x44c> + 101285c: 3dcf883a add r7,r7,r23 + 1012860: 843fffc4 addi r16,r16,-1 + 1012864: 3dc0472e bgeu r7,r23,1012984 <__umoddi3+0x568> + 1012868: e004943a slli r2,fp,16 + 101286c: d9400017 ldw r5,0(sp) + 1012870: 3c4fc83a sub r7,r7,r17 + 1012874: 8084b03a or r2,r16,r2 + 1012878: 28ffffcc andi r3,r5,65535 + 101287c: 280cd43a srli r6,r5,16 + 1012880: 100ad43a srli r5,r2,16 + 1012884: 10bfffcc andi r2,r2,65535 + 1012888: 10d1383a mul r8,r2,r3 + 101288c: 28c7383a mul r3,r5,r3 + 1012890: 1185383a mul r2,r2,r6 + 1012894: 4008d43a srli r4,r8,16 + 1012898: 298b383a mul r5,r5,r6 + 101289c: 10c5883a add r2,r2,r3 + 10128a0: 2089883a add r4,r4,r2 + 10128a4: 20c0022e bgeu r4,r3,10128b0 <__umoddi3+0x494> + 10128a8: 00800074 movhi r2,1 + 10128ac: 288b883a add r5,r5,r2 + 10128b0: 2004d43a srli r2,r4,16 + 10128b4: 2008943a slli r4,r4,16 + 10128b8: 40ffffcc andi r3,r8,65535 + 10128bc: 288b883a add r5,r5,r2 + 10128c0: 20c9883a add r4,r4,r3 + 10128c4: 39400b36 bltu r7,r5,10128f4 <__umoddi3+0x4d8> + 10128c8: 39403d26 beq r7,r5,10129c0 <__umoddi3+0x5a4> + 10128cc: 394bc83a sub r5,r7,r5 + 10128d0: 00000f06 br 1012910 <__umoddi3+0x4f4> + 10128d4: 30c5c83a sub r2,r6,r3 + 10128d8: 1839883a mov fp,r3 + 10128dc: b084d83a srl r2,r22,r2 + 10128e0: a0c6983a sll r3,r20,r3 + 10128e4: 8720983a sll r16,r16,fp + 10128e8: b72c983a sll r22,r22,fp + 10128ec: 18a8b03a or r20,r3,r2 + 10128f0: 003f3a06 br 10125dc <__umoddi3+0x1c0> + 10128f4: d8c00017 ldw r3,0(sp) + 10128f8: 20c5c83a sub r2,r4,r3 + 10128fc: 2089803a cmpltu r4,r4,r2 + 1012900: 2dc7c83a sub r3,r5,r23 + 1012904: 1907c83a sub r3,r3,r4 + 1012908: 38cbc83a sub r5,r7,r3 + 101290c: 1009883a mov r4,r2 + 1012910: b105c83a sub r2,r22,r4 + 1012914: b087803a cmpltu r3,r22,r2 + 1012918: 28c7c83a sub r3,r5,r3 + 101291c: d9400317 ldw r5,12(sp) + 1012920: 1544d83a srl r2,r2,r21 + 1012924: 1948983a sll r4,r3,r5 + 1012928: 1d46d83a srl r3,r3,r21 + 101292c: 20a4b03a or r18,r4,r2 + 1012930: 9011883a mov r8,r18 + 1012934: 1813883a mov r9,r3 + 1012938: 003ef606 br 1012514 <__umoddi3+0xf8> + 101293c: 01400604 movi r5,24 + 1012940: 2805883a mov r2,r5 + 1012944: 003ecc06 br 1012478 <__umoddi3+0x5c> + 1012948: 01400204 movi r5,8 + 101294c: 2805883a mov r2,r5 + 1012950: 003ec906 br 1012478 <__umoddi3+0x5c> + 1012954: 01400204 movi r5,8 + 1012958: 2805883a mov r2,r5 + 101295c: 003f0106 br 1012564 <__umoddi3+0x148> + 1012960: 01400204 movi r5,8 + 1012964: 2805883a mov r2,r5 + 1012968: 003f1206 br 10125b4 <__umoddi3+0x198> + 101296c: 01400604 movi r5,24 + 1012970: 2805883a mov r2,r5 + 1012974: 003f0f06 br 10125b4 <__umoddi3+0x198> + 1012978: 01400604 movi r5,24 + 101297c: 2805883a mov r2,r5 + 1012980: 003ef806 br 1012564 <__umoddi3+0x148> + 1012984: 3c7fb82e bgeu r7,r17,1012868 <__umoddi3+0x44c> + 1012988: 843fffc4 addi r16,r16,-1 + 101298c: 3dcf883a add r7,r7,r23 + 1012990: 003fb506 br 1012868 <__umoddi3+0x44c> + 1012994: 147fa22e bgeu r2,r17,1012820 <__umoddi3+0x404> + 1012998: e73fffc4 addi fp,fp,-1 + 101299c: 15c5883a add r2,r2,r23 + 10129a0: 003f9f06 br 1012820 <__umoddi3+0x404> + 10129a4: 147f692e bgeu r2,r17,101274c <__umoddi3+0x330> + 10129a8: 1405883a add r2,r2,r16 + 10129ac: 003f6706 br 101274c <__umoddi3+0x330> + 10129b0: 1405883a add r2,r2,r16 + 10129b4: 003f1906 br 101261c <__umoddi3+0x200> + 10129b8: 1405883a add r2,r2,r16 + 10129bc: 003ec906 br 10124e4 <__umoddi3+0xc8> + 10129c0: b13fcc36 bltu r22,r4,10128f4 <__umoddi3+0x4d8> + 10129c4: 000b883a mov r5,zero + 10129c8: 003fd106 br 1012910 <__umoddi3+0x4f4> + +010129cc <_fpadd_parts>: + 10129cc: defff804 addi sp,sp,-32 + 10129d0: dcc00315 stw r19,12(sp) + 10129d4: 2027883a mov r19,r4 + 10129d8: 21000017 ldw r4,0(r4) + 10129dc: 00c00044 movi r3,1 + 10129e0: dd400515 stw r21,20(sp) + 10129e4: dd000415 stw r20,16(sp) + 10129e8: ddc00715 stw r23,28(sp) + 10129ec: dd800615 stw r22,24(sp) + 10129f0: dc800215 stw r18,8(sp) + 10129f4: dc400115 stw r17,4(sp) + 10129f8: dc000015 stw r16,0(sp) + 10129fc: 282b883a mov r21,r5 + 1012a00: 3029883a mov r20,r6 + 1012a04: 1900632e bgeu r3,r4,1012b94 <_fpadd_parts+0x1c8> + 1012a08: 28800017 ldw r2,0(r5) + 1012a0c: 1880812e bgeu r3,r2,1012c14 <_fpadd_parts+0x248> + 1012a10: 00c00104 movi r3,4 + 1012a14: 20c0dc26 beq r4,r3,1012d88 <_fpadd_parts+0x3bc> + 1012a18: 10c07e26 beq r2,r3,1012c14 <_fpadd_parts+0x248> + 1012a1c: 00c00084 movi r3,2 + 1012a20: 10c06726 beq r2,r3,1012bc0 <_fpadd_parts+0x1f4> + 1012a24: 20c07b26 beq r4,r3,1012c14 <_fpadd_parts+0x248> + 1012a28: 9dc00217 ldw r23,8(r19) + 1012a2c: 28c00217 ldw r3,8(r5) + 1012a30: 9c400317 ldw r17,12(r19) + 1012a34: 2bc00317 ldw r15,12(r5) + 1012a38: b8cdc83a sub r6,r23,r3 + 1012a3c: 9c800417 ldw r18,16(r19) + 1012a40: 2c000417 ldw r16,16(r5) + 1012a44: 3009883a mov r4,r6 + 1012a48: 30009716 blt r6,zero,1012ca8 <_fpadd_parts+0x2dc> + 1012a4c: 00800fc4 movi r2,63 + 1012a50: 11806b16 blt r2,r6,1012c00 <_fpadd_parts+0x234> + 1012a54: 0100a40e bge zero,r4,1012ce8 <_fpadd_parts+0x31c> + 1012a58: 35bff804 addi r22,r6,-32 + 1012a5c: b000bc16 blt r22,zero,1012d50 <_fpadd_parts+0x384> + 1012a60: 8596d83a srl r11,r16,r22 + 1012a64: 0019883a mov r12,zero + 1012a68: 0013883a mov r9,zero + 1012a6c: 01000044 movi r4,1 + 1012a70: 0015883a mov r10,zero + 1012a74: b000be16 blt r22,zero,1012d70 <_fpadd_parts+0x3a4> + 1012a78: 2590983a sll r8,r4,r22 + 1012a7c: 000f883a mov r7,zero + 1012a80: 00bfffc4 movi r2,-1 + 1012a84: 3889883a add r4,r7,r2 + 1012a88: 408b883a add r5,r8,r2 + 1012a8c: 21cd803a cmpltu r6,r4,r7 + 1012a90: 314b883a add r5,r6,r5 + 1012a94: 7904703a and r2,r15,r4 + 1012a98: 8146703a and r3,r16,r5 + 1012a9c: 10c4b03a or r2,r2,r3 + 1012aa0: 10000226 beq r2,zero,1012aac <_fpadd_parts+0xe0> + 1012aa4: 02400044 movi r9,1 + 1012aa8: 0015883a mov r10,zero + 1012aac: 5a5eb03a or r15,r11,r9 + 1012ab0: 62a0b03a or r16,r12,r10 + 1012ab4: 99400117 ldw r5,4(r19) + 1012ab8: a8800117 ldw r2,4(r21) + 1012abc: 28806e26 beq r5,r2,1012c78 <_fpadd_parts+0x2ac> + 1012ac0: 28006626 beq r5,zero,1012c5c <_fpadd_parts+0x290> + 1012ac4: 7c45c83a sub r2,r15,r17 + 1012ac8: 7889803a cmpltu r4,r15,r2 + 1012acc: 8487c83a sub r3,r16,r18 + 1012ad0: 1909c83a sub r4,r3,r4 + 1012ad4: 100d883a mov r6,r2 + 1012ad8: 200f883a mov r7,r4 + 1012adc: 38007716 blt r7,zero,1012cbc <_fpadd_parts+0x2f0> + 1012ae0: a5c00215 stw r23,8(r20) + 1012ae4: a1c00415 stw r7,16(r20) + 1012ae8: a0000115 stw zero,4(r20) + 1012aec: a1800315 stw r6,12(r20) + 1012af0: a2000317 ldw r8,12(r20) + 1012af4: a2400417 ldw r9,16(r20) + 1012af8: 00bfffc4 movi r2,-1 + 1012afc: 408b883a add r5,r8,r2 + 1012b00: 2a09803a cmpltu r4,r5,r8 + 1012b04: 488d883a add r6,r9,r2 + 1012b08: 01c40034 movhi r7,4096 + 1012b0c: 39ffffc4 addi r7,r7,-1 + 1012b10: 218d883a add r6,r4,r6 + 1012b14: 39801736 bltu r7,r6,1012b74 <_fpadd_parts+0x1a8> + 1012b18: 31c06526 beq r6,r7,1012cb0 <_fpadd_parts+0x2e4> + 1012b1c: a3000217 ldw r12,8(r20) + 1012b20: 4209883a add r4,r8,r8 + 1012b24: 00bfffc4 movi r2,-1 + 1012b28: 220f803a cmpltu r7,r4,r8 + 1012b2c: 4a4b883a add r5,r9,r9 + 1012b30: 394f883a add r7,r7,r5 + 1012b34: 2095883a add r10,r4,r2 + 1012b38: 3897883a add r11,r7,r2 + 1012b3c: 510d803a cmpltu r6,r10,r4 + 1012b40: 6099883a add r12,r12,r2 + 1012b44: 32d7883a add r11,r6,r11 + 1012b48: 00840034 movhi r2,4096 + 1012b4c: 10bfffc4 addi r2,r2,-1 + 1012b50: 2011883a mov r8,r4 + 1012b54: 3813883a mov r9,r7 + 1012b58: a1000315 stw r4,12(r20) + 1012b5c: a1c00415 stw r7,16(r20) + 1012b60: a3000215 stw r12,8(r20) + 1012b64: 12c00336 bltu r2,r11,1012b74 <_fpadd_parts+0x1a8> + 1012b68: 58bfed1e bne r11,r2,1012b20 <_fpadd_parts+0x154> + 1012b6c: 00bfff84 movi r2,-2 + 1012b70: 12bfeb2e bgeu r2,r10,1012b20 <_fpadd_parts+0x154> + 1012b74: a2800417 ldw r10,16(r20) + 1012b78: 008000c4 movi r2,3 + 1012b7c: 00c80034 movhi r3,8192 + 1012b80: 18ffffc4 addi r3,r3,-1 + 1012b84: a2400317 ldw r9,12(r20) + 1012b88: a0800015 stw r2,0(r20) + 1012b8c: 1a802336 bltu r3,r10,1012c1c <_fpadd_parts+0x250> + 1012b90: a027883a mov r19,r20 + 1012b94: 9805883a mov r2,r19 + 1012b98: ddc00717 ldw r23,28(sp) + 1012b9c: dd800617 ldw r22,24(sp) + 1012ba0: dd400517 ldw r21,20(sp) + 1012ba4: dd000417 ldw r20,16(sp) + 1012ba8: dcc00317 ldw r19,12(sp) + 1012bac: dc800217 ldw r18,8(sp) + 1012bb0: dc400117 ldw r17,4(sp) + 1012bb4: dc000017 ldw r16,0(sp) + 1012bb8: dec00804 addi sp,sp,32 + 1012bbc: f800283a ret + 1012bc0: 20fff41e bne r4,r3,1012b94 <_fpadd_parts+0x1c8> + 1012bc4: 31000015 stw r4,0(r6) + 1012bc8: 98800117 ldw r2,4(r19) + 1012bcc: 30800115 stw r2,4(r6) + 1012bd0: 98c00217 ldw r3,8(r19) + 1012bd4: 30c00215 stw r3,8(r6) + 1012bd8: 98800317 ldw r2,12(r19) + 1012bdc: 30800315 stw r2,12(r6) + 1012be0: 98c00417 ldw r3,16(r19) + 1012be4: 30c00415 stw r3,16(r6) + 1012be8: 98800117 ldw r2,4(r19) + 1012bec: 28c00117 ldw r3,4(r5) + 1012bf0: 3027883a mov r19,r6 + 1012bf4: 10c4703a and r2,r2,r3 + 1012bf8: 30800115 stw r2,4(r6) + 1012bfc: 003fe506 br 1012b94 <_fpadd_parts+0x1c8> + 1012c00: 1dc02616 blt r3,r23,1012c9c <_fpadd_parts+0x2d0> + 1012c04: 0023883a mov r17,zero + 1012c08: 182f883a mov r23,r3 + 1012c0c: 0025883a mov r18,zero + 1012c10: 003fa806 br 1012ab4 <_fpadd_parts+0xe8> + 1012c14: a827883a mov r19,r21 + 1012c18: 003fde06 br 1012b94 <_fpadd_parts+0x1c8> + 1012c1c: 01800044 movi r6,1 + 1012c20: 500497fa slli r2,r10,31 + 1012c24: 4808d07a srli r4,r9,1 + 1012c28: 518ad83a srl r5,r10,r6 + 1012c2c: a2000217 ldw r8,8(r20) + 1012c30: 1108b03a or r4,r2,r4 + 1012c34: 0007883a mov r3,zero + 1012c38: 4984703a and r2,r9,r6 + 1012c3c: 208cb03a or r6,r4,r2 + 1012c40: 28ceb03a or r7,r5,r3 + 1012c44: 42000044 addi r8,r8,1 + 1012c48: a027883a mov r19,r20 + 1012c4c: a1c00415 stw r7,16(r20) + 1012c50: a2000215 stw r8,8(r20) + 1012c54: a1800315 stw r6,12(r20) + 1012c58: 003fce06 br 1012b94 <_fpadd_parts+0x1c8> + 1012c5c: 8bc5c83a sub r2,r17,r15 + 1012c60: 8889803a cmpltu r4,r17,r2 + 1012c64: 9407c83a sub r3,r18,r16 + 1012c68: 1909c83a sub r4,r3,r4 + 1012c6c: 100d883a mov r6,r2 + 1012c70: 200f883a mov r7,r4 + 1012c74: 003f9906 br 1012adc <_fpadd_parts+0x110> + 1012c78: 7c45883a add r2,r15,r17 + 1012c7c: 13c9803a cmpltu r4,r2,r15 + 1012c80: 8487883a add r3,r16,r18 + 1012c84: 20c9883a add r4,r4,r3 + 1012c88: a1400115 stw r5,4(r20) + 1012c8c: a5c00215 stw r23,8(r20) + 1012c90: a0800315 stw r2,12(r20) + 1012c94: a1000415 stw r4,16(r20) + 1012c98: 003fb606 br 1012b74 <_fpadd_parts+0x1a8> + 1012c9c: 001f883a mov r15,zero + 1012ca0: 0021883a mov r16,zero + 1012ca4: 003f8306 br 1012ab4 <_fpadd_parts+0xe8> + 1012ca8: 018dc83a sub r6,zero,r6 + 1012cac: 003f6706 br 1012a4c <_fpadd_parts+0x80> + 1012cb0: 00bfff84 movi r2,-2 + 1012cb4: 117faf36 bltu r2,r5,1012b74 <_fpadd_parts+0x1a8> + 1012cb8: 003f9806 br 1012b1c <_fpadd_parts+0x150> + 1012cbc: 0005883a mov r2,zero + 1012cc0: 1189c83a sub r4,r2,r6 + 1012cc4: 1105803a cmpltu r2,r2,r4 + 1012cc8: 01cbc83a sub r5,zero,r7 + 1012ccc: 2885c83a sub r2,r5,r2 + 1012cd0: 01800044 movi r6,1 + 1012cd4: a1800115 stw r6,4(r20) + 1012cd8: a5c00215 stw r23,8(r20) + 1012cdc: a1000315 stw r4,12(r20) + 1012ce0: a0800415 stw r2,16(r20) + 1012ce4: 003f8206 br 1012af0 <_fpadd_parts+0x124> + 1012ce8: 203f7226 beq r4,zero,1012ab4 <_fpadd_parts+0xe8> + 1012cec: 35bff804 addi r22,r6,-32 + 1012cf0: b9af883a add r23,r23,r6 + 1012cf4: b0003116 blt r22,zero,1012dbc <_fpadd_parts+0x3f0> + 1012cf8: 959ad83a srl r13,r18,r22 + 1012cfc: 001d883a mov r14,zero + 1012d00: 000f883a mov r7,zero + 1012d04: 01000044 movi r4,1 + 1012d08: 0011883a mov r8,zero + 1012d0c: b0002516 blt r22,zero,1012da4 <_fpadd_parts+0x3d8> + 1012d10: 2594983a sll r10,r4,r22 + 1012d14: 0013883a mov r9,zero + 1012d18: 00bfffc4 movi r2,-1 + 1012d1c: 4889883a add r4,r9,r2 + 1012d20: 508b883a add r5,r10,r2 + 1012d24: 224d803a cmpltu r6,r4,r9 + 1012d28: 314b883a add r5,r6,r5 + 1012d2c: 8904703a and r2,r17,r4 + 1012d30: 9146703a and r3,r18,r5 + 1012d34: 10c4b03a or r2,r2,r3 + 1012d38: 10000226 beq r2,zero,1012d44 <_fpadd_parts+0x378> + 1012d3c: 01c00044 movi r7,1 + 1012d40: 0011883a mov r8,zero + 1012d44: 69e2b03a or r17,r13,r7 + 1012d48: 7224b03a or r18,r14,r8 + 1012d4c: 003f5906 br 1012ab4 <_fpadd_parts+0xe8> + 1012d50: 8407883a add r3,r16,r16 + 1012d54: 008007c4 movi r2,31 + 1012d58: 1185c83a sub r2,r2,r6 + 1012d5c: 1886983a sll r3,r3,r2 + 1012d60: 7996d83a srl r11,r15,r6 + 1012d64: 8198d83a srl r12,r16,r6 + 1012d68: 1ad6b03a or r11,r3,r11 + 1012d6c: 003f3e06 br 1012a68 <_fpadd_parts+0x9c> + 1012d70: 2006d07a srli r3,r4,1 + 1012d74: 008007c4 movi r2,31 + 1012d78: 1185c83a sub r2,r2,r6 + 1012d7c: 1890d83a srl r8,r3,r2 + 1012d80: 218e983a sll r7,r4,r6 + 1012d84: 003f3e06 br 1012a80 <_fpadd_parts+0xb4> + 1012d88: 113f821e bne r2,r4,1012b94 <_fpadd_parts+0x1c8> + 1012d8c: 28c00117 ldw r3,4(r5) + 1012d90: 98800117 ldw r2,4(r19) + 1012d94: 10ff7f26 beq r2,r3,1012b94 <_fpadd_parts+0x1c8> + 1012d98: 04c040b4 movhi r19,258 + 1012d9c: 9cc64d04 addi r19,r19,6452 + 1012da0: 003f7c06 br 1012b94 <_fpadd_parts+0x1c8> + 1012da4: 2006d07a srli r3,r4,1 + 1012da8: 008007c4 movi r2,31 + 1012dac: 1185c83a sub r2,r2,r6 + 1012db0: 1894d83a srl r10,r3,r2 + 1012db4: 2192983a sll r9,r4,r6 + 1012db8: 003fd706 br 1012d18 <_fpadd_parts+0x34c> + 1012dbc: 9487883a add r3,r18,r18 + 1012dc0: 008007c4 movi r2,31 + 1012dc4: 1185c83a sub r2,r2,r6 + 1012dc8: 1886983a sll r3,r3,r2 + 1012dcc: 899ad83a srl r13,r17,r6 + 1012dd0: 919cd83a srl r14,r18,r6 + 1012dd4: 1b5ab03a or r13,r3,r13 + 1012dd8: 003fc906 br 1012d00 <_fpadd_parts+0x334> + +01012ddc <__subdf3>: + 1012ddc: deffea04 addi sp,sp,-88 + 1012de0: dcc01415 stw r19,80(sp) + 1012de4: dcc00404 addi r19,sp,16 + 1012de8: 2011883a mov r8,r4 + 1012dec: 2813883a mov r9,r5 + 1012df0: dc401315 stw r17,76(sp) + 1012df4: d809883a mov r4,sp + 1012df8: 980b883a mov r5,r19 + 1012dfc: dc400904 addi r17,sp,36 + 1012e00: dfc01515 stw ra,84(sp) + 1012e04: da400115 stw r9,4(sp) + 1012e08: d9c00315 stw r7,12(sp) + 1012e0c: da000015 stw r8,0(sp) + 1012e10: d9800215 stw r6,8(sp) + 1012e14: 10140700 call 1014070 <__unpack_d> + 1012e18: d9000204 addi r4,sp,8 + 1012e1c: 880b883a mov r5,r17 + 1012e20: 10140700 call 1014070 <__unpack_d> + 1012e24: d8800a17 ldw r2,40(sp) + 1012e28: 880b883a mov r5,r17 + 1012e2c: 9809883a mov r4,r19 + 1012e30: d9800e04 addi r6,sp,56 + 1012e34: 1080005c xori r2,r2,1 + 1012e38: d8800a15 stw r2,40(sp) + 1012e3c: 10129cc0 call 10129cc <_fpadd_parts> + 1012e40: 1009883a mov r4,r2 + 1012e44: 1013d5c0 call 1013d5c <__pack_d> + 1012e48: dfc01517 ldw ra,84(sp) + 1012e4c: dcc01417 ldw r19,80(sp) + 1012e50: dc401317 ldw r17,76(sp) + 1012e54: dec01604 addi sp,sp,88 + 1012e58: f800283a ret + +01012e5c <__adddf3>: + 1012e5c: deffea04 addi sp,sp,-88 + 1012e60: dcc01415 stw r19,80(sp) + 1012e64: dcc00404 addi r19,sp,16 + 1012e68: 2011883a mov r8,r4 + 1012e6c: 2813883a mov r9,r5 + 1012e70: dc401315 stw r17,76(sp) + 1012e74: d809883a mov r4,sp + 1012e78: 980b883a mov r5,r19 + 1012e7c: dc400904 addi r17,sp,36 + 1012e80: dfc01515 stw ra,84(sp) + 1012e84: da400115 stw r9,4(sp) + 1012e88: d9c00315 stw r7,12(sp) + 1012e8c: da000015 stw r8,0(sp) + 1012e90: d9800215 stw r6,8(sp) + 1012e94: 10140700 call 1014070 <__unpack_d> + 1012e98: d9000204 addi r4,sp,8 + 1012e9c: 880b883a mov r5,r17 + 1012ea0: 10140700 call 1014070 <__unpack_d> + 1012ea4: d9800e04 addi r6,sp,56 + 1012ea8: 9809883a mov r4,r19 + 1012eac: 880b883a mov r5,r17 + 1012eb0: 10129cc0 call 10129cc <_fpadd_parts> + 1012eb4: 1009883a mov r4,r2 + 1012eb8: 1013d5c0 call 1013d5c <__pack_d> + 1012ebc: dfc01517 ldw ra,84(sp) + 1012ec0: dcc01417 ldw r19,80(sp) + 1012ec4: dc401317 ldw r17,76(sp) + 1012ec8: dec01604 addi sp,sp,88 + 1012ecc: f800283a ret + +01012ed0 <__muldf3>: + 1012ed0: deffe004 addi sp,sp,-128 + 1012ed4: dc401815 stw r17,96(sp) + 1012ed8: dc400404 addi r17,sp,16 + 1012edc: 2011883a mov r8,r4 + 1012ee0: 2813883a mov r9,r5 + 1012ee4: dc001715 stw r16,92(sp) + 1012ee8: d809883a mov r4,sp + 1012eec: 880b883a mov r5,r17 + 1012ef0: dc000904 addi r16,sp,36 + 1012ef4: dfc01f15 stw ra,124(sp) + 1012ef8: da400115 stw r9,4(sp) + 1012efc: d9c00315 stw r7,12(sp) + 1012f00: da000015 stw r8,0(sp) + 1012f04: d9800215 stw r6,8(sp) + 1012f08: ddc01e15 stw r23,120(sp) + 1012f0c: dd801d15 stw r22,116(sp) + 1012f10: dd401c15 stw r21,112(sp) + 1012f14: dd001b15 stw r20,108(sp) + 1012f18: dcc01a15 stw r19,104(sp) + 1012f1c: dc801915 stw r18,100(sp) + 1012f20: 10140700 call 1014070 <__unpack_d> + 1012f24: d9000204 addi r4,sp,8 + 1012f28: 800b883a mov r5,r16 + 1012f2c: 10140700 call 1014070 <__unpack_d> + 1012f30: d9000417 ldw r4,16(sp) + 1012f34: 00800044 movi r2,1 + 1012f38: 1100102e bgeu r2,r4,1012f7c <__muldf3+0xac> + 1012f3c: d8c00917 ldw r3,36(sp) + 1012f40: 10c0062e bgeu r2,r3,1012f5c <__muldf3+0x8c> + 1012f44: 00800104 movi r2,4 + 1012f48: 20800a26 beq r4,r2,1012f74 <__muldf3+0xa4> + 1012f4c: 1880cc26 beq r3,r2,1013280 <__muldf3+0x3b0> + 1012f50: 00800084 movi r2,2 + 1012f54: 20800926 beq r4,r2,1012f7c <__muldf3+0xac> + 1012f58: 1880191e bne r3,r2,1012fc0 <__muldf3+0xf0> + 1012f5c: d8c00a17 ldw r3,40(sp) + 1012f60: d8800517 ldw r2,20(sp) + 1012f64: 8009883a mov r4,r16 + 1012f68: 10c4c03a cmpne r2,r2,r3 + 1012f6c: d8800a15 stw r2,40(sp) + 1012f70: 00000706 br 1012f90 <__muldf3+0xc0> + 1012f74: 00800084 movi r2,2 + 1012f78: 1880c326 beq r3,r2,1013288 <__muldf3+0x3b8> + 1012f7c: d8800517 ldw r2,20(sp) + 1012f80: d8c00a17 ldw r3,40(sp) + 1012f84: 8809883a mov r4,r17 + 1012f88: 10c4c03a cmpne r2,r2,r3 + 1012f8c: d8800515 stw r2,20(sp) + 1012f90: 1013d5c0 call 1013d5c <__pack_d> + 1012f94: dfc01f17 ldw ra,124(sp) + 1012f98: ddc01e17 ldw r23,120(sp) + 1012f9c: dd801d17 ldw r22,116(sp) + 1012fa0: dd401c17 ldw r21,112(sp) + 1012fa4: dd001b17 ldw r20,108(sp) + 1012fa8: dcc01a17 ldw r19,104(sp) + 1012fac: dc801917 ldw r18,100(sp) + 1012fb0: dc401817 ldw r17,96(sp) + 1012fb4: dc001717 ldw r16,92(sp) + 1012fb8: dec02004 addi sp,sp,128 + 1012fbc: f800283a ret + 1012fc0: dd800717 ldw r22,28(sp) + 1012fc4: dc800c17 ldw r18,48(sp) + 1012fc8: 002b883a mov r21,zero + 1012fcc: 0023883a mov r17,zero + 1012fd0: a80b883a mov r5,r21 + 1012fd4: b00d883a mov r6,r22 + 1012fd8: 880f883a mov r7,r17 + 1012fdc: ddc00817 ldw r23,32(sp) + 1012fe0: dcc00d17 ldw r19,52(sp) + 1012fe4: 9009883a mov r4,r18 + 1012fe8: 1013c440 call 1013c44 <__muldi3> + 1012fec: 001b883a mov r13,zero + 1012ff0: 680f883a mov r7,r13 + 1012ff4: b009883a mov r4,r22 + 1012ff8: 000b883a mov r5,zero + 1012ffc: 980d883a mov r6,r19 + 1013000: b82d883a mov r22,r23 + 1013004: 002f883a mov r23,zero + 1013008: db401615 stw r13,88(sp) + 101300c: d8801315 stw r2,76(sp) + 1013010: d8c01415 stw r3,80(sp) + 1013014: dcc01515 stw r19,84(sp) + 1013018: 1013c440 call 1013c44 <__muldi3> + 101301c: b00d883a mov r6,r22 + 1013020: 000b883a mov r5,zero + 1013024: 9009883a mov r4,r18 + 1013028: b80f883a mov r7,r23 + 101302c: 1021883a mov r16,r2 + 1013030: 1823883a mov r17,r3 + 1013034: 1013c440 call 1013c44 <__muldi3> + 1013038: 8085883a add r2,r16,r2 + 101303c: 140d803a cmpltu r6,r2,r16 + 1013040: 88c7883a add r3,r17,r3 + 1013044: 30cd883a add r6,r6,r3 + 1013048: 1029883a mov r20,r2 + 101304c: 302b883a mov r21,r6 + 1013050: da801317 ldw r10,76(sp) + 1013054: dac01417 ldw r11,80(sp) + 1013058: db001517 ldw r12,84(sp) + 101305c: db401617 ldw r13,88(sp) + 1013060: 3440612e bgeu r6,r17,10131e8 <__muldf3+0x318> + 1013064: 0009883a mov r4,zero + 1013068: 5105883a add r2,r10,r4 + 101306c: 128d803a cmpltu r6,r2,r10 + 1013070: 5d07883a add r3,r11,r20 + 1013074: 30cd883a add r6,r6,r3 + 1013078: 0021883a mov r16,zero + 101307c: 04400044 movi r17,1 + 1013080: 1025883a mov r18,r2 + 1013084: 3027883a mov r19,r6 + 1013088: 32c06236 bltu r6,r11,1013214 <__muldf3+0x344> + 101308c: 59807a26 beq r11,r6,1013278 <__muldf3+0x3a8> + 1013090: 680b883a mov r5,r13 + 1013094: b80f883a mov r7,r23 + 1013098: 6009883a mov r4,r12 + 101309c: b00d883a mov r6,r22 + 10130a0: 1013c440 call 1013c44 <__muldi3> + 10130a4: 1009883a mov r4,r2 + 10130a8: 000f883a mov r7,zero + 10130ac: 1545883a add r2,r2,r21 + 10130b0: 1111803a cmpltu r8,r2,r4 + 10130b4: 19c7883a add r3,r3,r7 + 10130b8: 40c7883a add r3,r8,r3 + 10130bc: 88cb883a add r5,r17,r3 + 10130c0: d8c00617 ldw r3,24(sp) + 10130c4: 8089883a add r4,r16,r2 + 10130c8: d8800b17 ldw r2,44(sp) + 10130cc: 18c00104 addi r3,r3,4 + 10130d0: 240d803a cmpltu r6,r4,r16 + 10130d4: 10c7883a add r3,r2,r3 + 10130d8: 2013883a mov r9,r4 + 10130dc: d8800a17 ldw r2,40(sp) + 10130e0: d9000517 ldw r4,20(sp) + 10130e4: 314d883a add r6,r6,r5 + 10130e8: 3015883a mov r10,r6 + 10130ec: 2088c03a cmpne r4,r4,r2 + 10130f0: 00880034 movhi r2,8192 + 10130f4: 10bfffc4 addi r2,r2,-1 + 10130f8: d9000f15 stw r4,60(sp) + 10130fc: d8c01015 stw r3,64(sp) + 1013100: 1180162e bgeu r2,r6,101315c <__muldf3+0x28c> + 1013104: 1811883a mov r8,r3 + 1013108: 101f883a mov r15,r2 + 101310c: 980497fa slli r2,r19,31 + 1013110: 9016d07a srli r11,r18,1 + 1013114: 500697fa slli r3,r10,31 + 1013118: 480cd07a srli r6,r9,1 + 101311c: 500ed07a srli r7,r10,1 + 1013120: 12d6b03a or r11,r2,r11 + 1013124: 00800044 movi r2,1 + 1013128: 198cb03a or r6,r3,r6 + 101312c: 4888703a and r4,r9,r2 + 1013130: 9818d07a srli r12,r19,1 + 1013134: 001b883a mov r13,zero + 1013138: 03a00034 movhi r14,32768 + 101313c: 3013883a mov r9,r6 + 1013140: 3815883a mov r10,r7 + 1013144: 4091883a add r8,r8,r2 + 1013148: 20000226 beq r4,zero,1013154 <__muldf3+0x284> + 101314c: 5b64b03a or r18,r11,r13 + 1013150: 63a6b03a or r19,r12,r14 + 1013154: 7abfed36 bltu r15,r10,101310c <__muldf3+0x23c> + 1013158: da001015 stw r8,64(sp) + 101315c: 00840034 movhi r2,4096 + 1013160: 10bfffc4 addi r2,r2,-1 + 1013164: 12801436 bltu r2,r10,10131b8 <__muldf3+0x2e8> + 1013168: da001017 ldw r8,64(sp) + 101316c: 101f883a mov r15,r2 + 1013170: 4a45883a add r2,r9,r9 + 1013174: 124d803a cmpltu r6,r2,r9 + 1013178: 5287883a add r3,r10,r10 + 101317c: 9497883a add r11,r18,r18 + 1013180: 5c8f803a cmpltu r7,r11,r18 + 1013184: 9cd9883a add r12,r19,r19 + 1013188: 01000044 movi r4,1 + 101318c: 30cd883a add r6,r6,r3 + 1013190: 3b0f883a add r7,r7,r12 + 1013194: 423fffc4 addi r8,r8,-1 + 1013198: 1013883a mov r9,r2 + 101319c: 3015883a mov r10,r6 + 10131a0: 111ab03a or r13,r2,r4 + 10131a4: 98003016 blt r19,zero,1013268 <__muldf3+0x398> + 10131a8: 5825883a mov r18,r11 + 10131ac: 3827883a mov r19,r7 + 10131b0: 7abfef2e bgeu r15,r10,1013170 <__muldf3+0x2a0> + 10131b4: da001015 stw r8,64(sp) + 10131b8: 00803fc4 movi r2,255 + 10131bc: 488e703a and r7,r9,r2 + 10131c0: 00802004 movi r2,128 + 10131c4: 0007883a mov r3,zero + 10131c8: 0011883a mov r8,zero + 10131cc: 38801826 beq r7,r2,1013230 <__muldf3+0x360> + 10131d0: 008000c4 movi r2,3 + 10131d4: d9000e04 addi r4,sp,56 + 10131d8: da801215 stw r10,72(sp) + 10131dc: d8800e15 stw r2,56(sp) + 10131e0: da401115 stw r9,68(sp) + 10131e4: 003f6a06 br 1012f90 <__muldf3+0xc0> + 10131e8: 89802126 beq r17,r6,1013270 <__muldf3+0x3a0> + 10131ec: 0009883a mov r4,zero + 10131f0: 5105883a add r2,r10,r4 + 10131f4: 128d803a cmpltu r6,r2,r10 + 10131f8: 5d07883a add r3,r11,r20 + 10131fc: 30cd883a add r6,r6,r3 + 1013200: 0021883a mov r16,zero + 1013204: 0023883a mov r17,zero + 1013208: 1025883a mov r18,r2 + 101320c: 3027883a mov r19,r6 + 1013210: 32ff9e2e bgeu r6,r11,101308c <__muldf3+0x1bc> + 1013214: 00800044 movi r2,1 + 1013218: 8089883a add r4,r16,r2 + 101321c: 240d803a cmpltu r6,r4,r16 + 1013220: 344d883a add r6,r6,r17 + 1013224: 2021883a mov r16,r4 + 1013228: 3023883a mov r17,r6 + 101322c: 003f9806 br 1013090 <__muldf3+0x1c0> + 1013230: 403fe71e bne r8,zero,10131d0 <__muldf3+0x300> + 1013234: 01004004 movi r4,256 + 1013238: 4904703a and r2,r9,r4 + 101323c: 10c4b03a or r2,r2,r3 + 1013240: 103fe31e bne r2,zero,10131d0 <__muldf3+0x300> + 1013244: 94c4b03a or r2,r18,r19 + 1013248: 103fe126 beq r2,zero,10131d0 <__muldf3+0x300> + 101324c: 49c5883a add r2,r9,r7 + 1013250: 1251803a cmpltu r8,r2,r9 + 1013254: 4291883a add r8,r8,r10 + 1013258: 013fc004 movi r4,-256 + 101325c: 1112703a and r9,r2,r4 + 1013260: 4015883a mov r10,r8 + 1013264: 003fda06 br 10131d0 <__muldf3+0x300> + 1013268: 6813883a mov r9,r13 + 101326c: 003fce06 br 10131a8 <__muldf3+0x2d8> + 1013270: 143f7c36 bltu r2,r16,1013064 <__muldf3+0x194> + 1013274: 003fdd06 br 10131ec <__muldf3+0x31c> + 1013278: 12bf852e bgeu r2,r10,1013090 <__muldf3+0x1c0> + 101327c: 003fe506 br 1013214 <__muldf3+0x344> + 1013280: 00800084 movi r2,2 + 1013284: 20bf351e bne r4,r2,1012f5c <__muldf3+0x8c> + 1013288: 010040b4 movhi r4,258 + 101328c: 21064d04 addi r4,r4,6452 + 1013290: 003f3f06 br 1012f90 <__muldf3+0xc0> + +01013294 <__divdf3>: + 1013294: deffed04 addi sp,sp,-76 + 1013298: dcc01115 stw r19,68(sp) + 101329c: dcc00404 addi r19,sp,16 + 10132a0: 2011883a mov r8,r4 + 10132a4: 2813883a mov r9,r5 + 10132a8: dc000e15 stw r16,56(sp) + 10132ac: d809883a mov r4,sp + 10132b0: 980b883a mov r5,r19 + 10132b4: dc000904 addi r16,sp,36 + 10132b8: dfc01215 stw ra,72(sp) + 10132bc: da400115 stw r9,4(sp) + 10132c0: d9c00315 stw r7,12(sp) + 10132c4: da000015 stw r8,0(sp) + 10132c8: d9800215 stw r6,8(sp) + 10132cc: dc801015 stw r18,64(sp) + 10132d0: dc400f15 stw r17,60(sp) + 10132d4: 10140700 call 1014070 <__unpack_d> + 10132d8: d9000204 addi r4,sp,8 + 10132dc: 800b883a mov r5,r16 + 10132e0: 10140700 call 1014070 <__unpack_d> + 10132e4: d9000417 ldw r4,16(sp) + 10132e8: 00800044 movi r2,1 + 10132ec: 11000b2e bgeu r2,r4,101331c <__divdf3+0x88> + 10132f0: d9400917 ldw r5,36(sp) + 10132f4: 1140762e bgeu r2,r5,10134d0 <__divdf3+0x23c> + 10132f8: d8800517 ldw r2,20(sp) + 10132fc: d8c00a17 ldw r3,40(sp) + 1013300: 01800104 movi r6,4 + 1013304: 10c4f03a xor r2,r2,r3 + 1013308: d8800515 stw r2,20(sp) + 101330c: 21800226 beq r4,r6,1013318 <__divdf3+0x84> + 1013310: 00800084 movi r2,2 + 1013314: 2080141e bne r4,r2,1013368 <__divdf3+0xd4> + 1013318: 29000926 beq r5,r4,1013340 <__divdf3+0xac> + 101331c: 9809883a mov r4,r19 + 1013320: 1013d5c0 call 1013d5c <__pack_d> + 1013324: dfc01217 ldw ra,72(sp) + 1013328: dcc01117 ldw r19,68(sp) + 101332c: dc801017 ldw r18,64(sp) + 1013330: dc400f17 ldw r17,60(sp) + 1013334: dc000e17 ldw r16,56(sp) + 1013338: dec01304 addi sp,sp,76 + 101333c: f800283a ret + 1013340: 010040b4 movhi r4,258 + 1013344: 21064d04 addi r4,r4,6452 + 1013348: 1013d5c0 call 1013d5c <__pack_d> + 101334c: dfc01217 ldw ra,72(sp) + 1013350: dcc01117 ldw r19,68(sp) + 1013354: dc801017 ldw r18,64(sp) + 1013358: dc400f17 ldw r17,60(sp) + 101335c: dc000e17 ldw r16,56(sp) + 1013360: dec01304 addi sp,sp,76 + 1013364: f800283a ret + 1013368: 29805b26 beq r5,r6,10134d8 <__divdf3+0x244> + 101336c: 28802d26 beq r5,r2,1013424 <__divdf3+0x190> + 1013370: d8c00617 ldw r3,24(sp) + 1013374: d8800b17 ldw r2,44(sp) + 1013378: d9c00817 ldw r7,32(sp) + 101337c: dc400d17 ldw r17,52(sp) + 1013380: 188bc83a sub r5,r3,r2 + 1013384: d9800717 ldw r6,28(sp) + 1013388: dc000c17 ldw r16,48(sp) + 101338c: d9400615 stw r5,24(sp) + 1013390: 3c403836 bltu r7,r17,1013474 <__divdf3+0x1e0> + 1013394: 89c03626 beq r17,r7,1013470 <__divdf3+0x1dc> + 1013398: 0015883a mov r10,zero + 101339c: 001d883a mov r14,zero + 10133a0: 02c40034 movhi r11,4096 + 10133a4: 001f883a mov r15,zero + 10133a8: 003f883a mov ra,zero + 10133ac: 04800f44 movi r18,61 + 10133b0: 00000f06 br 10133f0 <__divdf3+0x15c> + 10133b4: 601d883a mov r14,r12 + 10133b8: 681f883a mov r15,r13 + 10133bc: 400d883a mov r6,r8 + 10133c0: 100f883a mov r7,r2 + 10133c4: 3191883a add r8,r6,r6 + 10133c8: 5808d07a srli r4,r11,1 + 10133cc: 4185803a cmpltu r2,r8,r6 + 10133d0: 39d3883a add r9,r7,r7 + 10133d4: 28c6b03a or r3,r5,r3 + 10133d8: 1245883a add r2,r2,r9 + 10133dc: 1815883a mov r10,r3 + 10133e0: 2017883a mov r11,r4 + 10133e4: 400d883a mov r6,r8 + 10133e8: 100f883a mov r7,r2 + 10133ec: fc801726 beq ra,r18,101344c <__divdf3+0x1b8> + 10133f0: 580a97fa slli r5,r11,31 + 10133f4: 5006d07a srli r3,r10,1 + 10133f8: ffc00044 addi ra,ra,1 + 10133fc: 3c7ff136 bltu r7,r17,10133c4 <__divdf3+0x130> + 1013400: 3411c83a sub r8,r6,r16 + 1013404: 3205803a cmpltu r2,r6,r8 + 1013408: 3c53c83a sub r9,r7,r17 + 101340c: 7298b03a or r12,r14,r10 + 1013410: 7adab03a or r13,r15,r11 + 1013414: 4885c83a sub r2,r9,r2 + 1013418: 89ffe61e bne r17,r7,10133b4 <__divdf3+0x120> + 101341c: 343fe936 bltu r6,r16,10133c4 <__divdf3+0x130> + 1013420: 003fe406 br 10133b4 <__divdf3+0x120> + 1013424: 9809883a mov r4,r19 + 1013428: d9800415 stw r6,16(sp) + 101342c: 1013d5c0 call 1013d5c <__pack_d> + 1013430: dfc01217 ldw ra,72(sp) + 1013434: dcc01117 ldw r19,68(sp) + 1013438: dc801017 ldw r18,64(sp) + 101343c: dc400f17 ldw r17,60(sp) + 1013440: dc000e17 ldw r16,56(sp) + 1013444: dec01304 addi sp,sp,76 + 1013448: f800283a ret + 101344c: 00803fc4 movi r2,255 + 1013450: 7090703a and r8,r14,r2 + 1013454: 00802004 movi r2,128 + 1013458: 0007883a mov r3,zero + 101345c: 0013883a mov r9,zero + 1013460: 40800d26 beq r8,r2,1013498 <__divdf3+0x204> + 1013464: dbc00815 stw r15,32(sp) + 1013468: db800715 stw r14,28(sp) + 101346c: 003fab06 br 101331c <__divdf3+0x88> + 1013470: 343fc92e bgeu r6,r16,1013398 <__divdf3+0x104> + 1013474: 3185883a add r2,r6,r6 + 1013478: 1189803a cmpltu r4,r2,r6 + 101347c: 39c7883a add r3,r7,r7 + 1013480: 20c9883a add r4,r4,r3 + 1013484: 297fffc4 addi r5,r5,-1 + 1013488: 100d883a mov r6,r2 + 101348c: 200f883a mov r7,r4 + 1013490: d9400615 stw r5,24(sp) + 1013494: 003fc006 br 1013398 <__divdf3+0x104> + 1013498: 483ff21e bne r9,zero,1013464 <__divdf3+0x1d0> + 101349c: 01004004 movi r4,256 + 10134a0: 7104703a and r2,r14,r4 + 10134a4: 10c4b03a or r2,r2,r3 + 10134a8: 103fee1e bne r2,zero,1013464 <__divdf3+0x1d0> + 10134ac: 31c4b03a or r2,r6,r7 + 10134b0: 103fec26 beq r2,zero,1013464 <__divdf3+0x1d0> + 10134b4: 7205883a add r2,r14,r8 + 10134b8: 1391803a cmpltu r8,r2,r14 + 10134bc: 43d1883a add r8,r8,r15 + 10134c0: 013fc004 movi r4,-256 + 10134c4: 111c703a and r14,r2,r4 + 10134c8: 401f883a mov r15,r8 + 10134cc: 003fe506 br 1013464 <__divdf3+0x1d0> + 10134d0: 8009883a mov r4,r16 + 10134d4: 003f9206 br 1013320 <__divdf3+0x8c> + 10134d8: 9809883a mov r4,r19 + 10134dc: d8000715 stw zero,28(sp) + 10134e0: d8000815 stw zero,32(sp) + 10134e4: d8000615 stw zero,24(sp) + 10134e8: 003f8d06 br 1013320 <__divdf3+0x8c> + +010134ec <__eqdf2>: + 10134ec: deffef04 addi sp,sp,-68 + 10134f0: dc400f15 stw r17,60(sp) + 10134f4: dc400404 addi r17,sp,16 + 10134f8: 2005883a mov r2,r4 + 10134fc: 2807883a mov r3,r5 + 1013500: dc000e15 stw r16,56(sp) + 1013504: d809883a mov r4,sp + 1013508: 880b883a mov r5,r17 + 101350c: dc000904 addi r16,sp,36 + 1013510: d8c00115 stw r3,4(sp) + 1013514: d8800015 stw r2,0(sp) + 1013518: d9800215 stw r6,8(sp) + 101351c: dfc01015 stw ra,64(sp) + 1013520: d9c00315 stw r7,12(sp) + 1013524: 10140700 call 1014070 <__unpack_d> + 1013528: d9000204 addi r4,sp,8 + 101352c: 800b883a mov r5,r16 + 1013530: 10140700 call 1014070 <__unpack_d> + 1013534: d8800417 ldw r2,16(sp) + 1013538: 00c00044 movi r3,1 + 101353c: 180d883a mov r6,r3 + 1013540: 1880062e bgeu r3,r2,101355c <__eqdf2+0x70> + 1013544: d8800917 ldw r2,36(sp) + 1013548: 8809883a mov r4,r17 + 101354c: 800b883a mov r5,r16 + 1013550: 1880022e bgeu r3,r2,101355c <__eqdf2+0x70> + 1013554: 10141a80 call 10141a8 <__fpcmp_parts_d> + 1013558: 100d883a mov r6,r2 + 101355c: 3005883a mov r2,r6 + 1013560: dfc01017 ldw ra,64(sp) + 1013564: dc400f17 ldw r17,60(sp) + 1013568: dc000e17 ldw r16,56(sp) + 101356c: dec01104 addi sp,sp,68 + 1013570: f800283a ret + +01013574 <__nedf2>: + 1013574: deffef04 addi sp,sp,-68 + 1013578: dc400f15 stw r17,60(sp) + 101357c: dc400404 addi r17,sp,16 + 1013580: 2005883a mov r2,r4 + 1013584: 2807883a mov r3,r5 + 1013588: dc000e15 stw r16,56(sp) + 101358c: d809883a mov r4,sp + 1013590: 880b883a mov r5,r17 + 1013594: dc000904 addi r16,sp,36 + 1013598: d8c00115 stw r3,4(sp) + 101359c: d8800015 stw r2,0(sp) + 10135a0: d9800215 stw r6,8(sp) + 10135a4: dfc01015 stw ra,64(sp) + 10135a8: d9c00315 stw r7,12(sp) + 10135ac: 10140700 call 1014070 <__unpack_d> + 10135b0: d9000204 addi r4,sp,8 + 10135b4: 800b883a mov r5,r16 + 10135b8: 10140700 call 1014070 <__unpack_d> + 10135bc: d8800417 ldw r2,16(sp) + 10135c0: 00c00044 movi r3,1 + 10135c4: 180d883a mov r6,r3 + 10135c8: 1880062e bgeu r3,r2,10135e4 <__nedf2+0x70> + 10135cc: d8800917 ldw r2,36(sp) + 10135d0: 8809883a mov r4,r17 + 10135d4: 800b883a mov r5,r16 + 10135d8: 1880022e bgeu r3,r2,10135e4 <__nedf2+0x70> + 10135dc: 10141a80 call 10141a8 <__fpcmp_parts_d> + 10135e0: 100d883a mov r6,r2 + 10135e4: 3005883a mov r2,r6 + 10135e8: dfc01017 ldw ra,64(sp) + 10135ec: dc400f17 ldw r17,60(sp) + 10135f0: dc000e17 ldw r16,56(sp) + 10135f4: dec01104 addi sp,sp,68 + 10135f8: f800283a ret + +010135fc <__gtdf2>: + 10135fc: deffef04 addi sp,sp,-68 + 1013600: dc400f15 stw r17,60(sp) + 1013604: dc400404 addi r17,sp,16 + 1013608: 2005883a mov r2,r4 + 101360c: 2807883a mov r3,r5 + 1013610: dc000e15 stw r16,56(sp) + 1013614: d809883a mov r4,sp + 1013618: 880b883a mov r5,r17 + 101361c: dc000904 addi r16,sp,36 + 1013620: d8c00115 stw r3,4(sp) + 1013624: d8800015 stw r2,0(sp) + 1013628: d9800215 stw r6,8(sp) + 101362c: dfc01015 stw ra,64(sp) + 1013630: d9c00315 stw r7,12(sp) + 1013634: 10140700 call 1014070 <__unpack_d> + 1013638: d9000204 addi r4,sp,8 + 101363c: 800b883a mov r5,r16 + 1013640: 10140700 call 1014070 <__unpack_d> + 1013644: d8800417 ldw r2,16(sp) + 1013648: 00c00044 movi r3,1 + 101364c: 01bfffc4 movi r6,-1 + 1013650: 1880062e bgeu r3,r2,101366c <__gtdf2+0x70> + 1013654: d8800917 ldw r2,36(sp) + 1013658: 8809883a mov r4,r17 + 101365c: 800b883a mov r5,r16 + 1013660: 1880022e bgeu r3,r2,101366c <__gtdf2+0x70> + 1013664: 10141a80 call 10141a8 <__fpcmp_parts_d> + 1013668: 100d883a mov r6,r2 + 101366c: 3005883a mov r2,r6 + 1013670: dfc01017 ldw ra,64(sp) + 1013674: dc400f17 ldw r17,60(sp) + 1013678: dc000e17 ldw r16,56(sp) + 101367c: dec01104 addi sp,sp,68 + 1013680: f800283a ret + +01013684 <__gedf2>: + 1013684: deffef04 addi sp,sp,-68 + 1013688: dc400f15 stw r17,60(sp) + 101368c: dc400404 addi r17,sp,16 + 1013690: 2005883a mov r2,r4 + 1013694: 2807883a mov r3,r5 + 1013698: dc000e15 stw r16,56(sp) + 101369c: d809883a mov r4,sp + 10136a0: 880b883a mov r5,r17 + 10136a4: dc000904 addi r16,sp,36 + 10136a8: d8c00115 stw r3,4(sp) + 10136ac: d8800015 stw r2,0(sp) + 10136b0: d9800215 stw r6,8(sp) + 10136b4: dfc01015 stw ra,64(sp) + 10136b8: d9c00315 stw r7,12(sp) + 10136bc: 10140700 call 1014070 <__unpack_d> + 10136c0: d9000204 addi r4,sp,8 + 10136c4: 800b883a mov r5,r16 + 10136c8: 10140700 call 1014070 <__unpack_d> + 10136cc: d8800417 ldw r2,16(sp) + 10136d0: 00c00044 movi r3,1 + 10136d4: 01bfffc4 movi r6,-1 + 10136d8: 1880062e bgeu r3,r2,10136f4 <__gedf2+0x70> + 10136dc: d8800917 ldw r2,36(sp) + 10136e0: 8809883a mov r4,r17 + 10136e4: 800b883a mov r5,r16 + 10136e8: 1880022e bgeu r3,r2,10136f4 <__gedf2+0x70> + 10136ec: 10141a80 call 10141a8 <__fpcmp_parts_d> + 10136f0: 100d883a mov r6,r2 + 10136f4: 3005883a mov r2,r6 + 10136f8: dfc01017 ldw ra,64(sp) + 10136fc: dc400f17 ldw r17,60(sp) + 1013700: dc000e17 ldw r16,56(sp) + 1013704: dec01104 addi sp,sp,68 + 1013708: f800283a ret + +0101370c <__ltdf2>: + 101370c: deffef04 addi sp,sp,-68 + 1013710: dc400f15 stw r17,60(sp) + 1013714: dc400404 addi r17,sp,16 + 1013718: 2005883a mov r2,r4 + 101371c: 2807883a mov r3,r5 + 1013720: dc000e15 stw r16,56(sp) + 1013724: d809883a mov r4,sp + 1013728: 880b883a mov r5,r17 + 101372c: dc000904 addi r16,sp,36 + 1013730: d8c00115 stw r3,4(sp) + 1013734: d8800015 stw r2,0(sp) + 1013738: d9800215 stw r6,8(sp) + 101373c: dfc01015 stw ra,64(sp) + 1013740: d9c00315 stw r7,12(sp) + 1013744: 10140700 call 1014070 <__unpack_d> + 1013748: d9000204 addi r4,sp,8 + 101374c: 800b883a mov r5,r16 + 1013750: 10140700 call 1014070 <__unpack_d> + 1013754: d8800417 ldw r2,16(sp) + 1013758: 00c00044 movi r3,1 + 101375c: 180d883a mov r6,r3 + 1013760: 1880062e bgeu r3,r2,101377c <__ltdf2+0x70> + 1013764: d8800917 ldw r2,36(sp) + 1013768: 8809883a mov r4,r17 + 101376c: 800b883a mov r5,r16 + 1013770: 1880022e bgeu r3,r2,101377c <__ltdf2+0x70> + 1013774: 10141a80 call 10141a8 <__fpcmp_parts_d> + 1013778: 100d883a mov r6,r2 + 101377c: 3005883a mov r2,r6 + 1013780: dfc01017 ldw ra,64(sp) + 1013784: dc400f17 ldw r17,60(sp) + 1013788: dc000e17 ldw r16,56(sp) + 101378c: dec01104 addi sp,sp,68 + 1013790: f800283a ret + +01013794 <__floatsidf>: + 1013794: 2006d7fa srli r3,r4,31 + 1013798: defff604 addi sp,sp,-40 + 101379c: 008000c4 movi r2,3 + 10137a0: dfc00915 stw ra,36(sp) + 10137a4: dcc00815 stw r19,32(sp) + 10137a8: dc800715 stw r18,28(sp) + 10137ac: dc400615 stw r17,24(sp) + 10137b0: dc000515 stw r16,20(sp) + 10137b4: d8800015 stw r2,0(sp) + 10137b8: d8c00115 stw r3,4(sp) + 10137bc: 20000f1e bne r4,zero,10137fc <__floatsidf+0x68> + 10137c0: 00800084 movi r2,2 + 10137c4: d8800015 stw r2,0(sp) + 10137c8: d809883a mov r4,sp + 10137cc: 1013d5c0 call 1013d5c <__pack_d> + 10137d0: 1009883a mov r4,r2 + 10137d4: 180b883a mov r5,r3 + 10137d8: 2005883a mov r2,r4 + 10137dc: 2807883a mov r3,r5 + 10137e0: dfc00917 ldw ra,36(sp) + 10137e4: dcc00817 ldw r19,32(sp) + 10137e8: dc800717 ldw r18,28(sp) + 10137ec: dc400617 ldw r17,24(sp) + 10137f0: dc000517 ldw r16,20(sp) + 10137f4: dec00a04 addi sp,sp,40 + 10137f8: f800283a ret + 10137fc: 00800f04 movi r2,60 + 1013800: 1807003a cmpeq r3,r3,zero + 1013804: d8800215 stw r2,8(sp) + 1013808: 18001126 beq r3,zero,1013850 <__floatsidf+0xbc> + 101380c: 0027883a mov r19,zero + 1013810: 2025883a mov r18,r4 + 1013814: d9000315 stw r4,12(sp) + 1013818: dcc00415 stw r19,16(sp) + 101381c: 1013cdc0 call 1013cdc <__clzsi2> + 1013820: 11000744 addi r4,r2,29 + 1013824: 013fe80e bge zero,r4,10137c8 <__floatsidf+0x34> + 1013828: 10bfff44 addi r2,r2,-3 + 101382c: 10000c16 blt r2,zero,1013860 <__floatsidf+0xcc> + 1013830: 90a2983a sll r17,r18,r2 + 1013834: 0021883a mov r16,zero + 1013838: d8800217 ldw r2,8(sp) + 101383c: dc400415 stw r17,16(sp) + 1013840: dc000315 stw r16,12(sp) + 1013844: 1105c83a sub r2,r2,r4 + 1013848: d8800215 stw r2,8(sp) + 101384c: 003fde06 br 10137c8 <__floatsidf+0x34> + 1013850: 00a00034 movhi r2,32768 + 1013854: 20800a26 beq r4,r2,1013880 <__floatsidf+0xec> + 1013858: 0109c83a sub r4,zero,r4 + 101385c: 003feb06 br 101380c <__floatsidf+0x78> + 1013860: 9006d07a srli r3,r18,1 + 1013864: 008007c4 movi r2,31 + 1013868: 1105c83a sub r2,r2,r4 + 101386c: 1886d83a srl r3,r3,r2 + 1013870: 9922983a sll r17,r19,r4 + 1013874: 9120983a sll r16,r18,r4 + 1013878: 1c62b03a or r17,r3,r17 + 101387c: 003fee06 br 1013838 <__floatsidf+0xa4> + 1013880: 0009883a mov r4,zero + 1013884: 01707834 movhi r5,49632 + 1013888: 003fd306 br 10137d8 <__floatsidf+0x44> + +0101388c <__fixdfsi>: + 101388c: defff804 addi sp,sp,-32 + 1013890: 2005883a mov r2,r4 + 1013894: 2807883a mov r3,r5 + 1013898: d809883a mov r4,sp + 101389c: d9400204 addi r5,sp,8 + 10138a0: d8c00115 stw r3,4(sp) + 10138a4: d8800015 stw r2,0(sp) + 10138a8: dfc00715 stw ra,28(sp) + 10138ac: 10140700 call 1014070 <__unpack_d> + 10138b0: d8c00217 ldw r3,8(sp) + 10138b4: 00800084 movi r2,2 + 10138b8: 1880051e bne r3,r2,10138d0 <__fixdfsi+0x44> + 10138bc: 0007883a mov r3,zero + 10138c0: 1805883a mov r2,r3 + 10138c4: dfc00717 ldw ra,28(sp) + 10138c8: dec00804 addi sp,sp,32 + 10138cc: f800283a ret + 10138d0: 00800044 movi r2,1 + 10138d4: 10fff92e bgeu r2,r3,10138bc <__fixdfsi+0x30> + 10138d8: 00800104 movi r2,4 + 10138dc: 18800426 beq r3,r2,10138f0 <__fixdfsi+0x64> + 10138e0: d8c00417 ldw r3,16(sp) + 10138e4: 183ff516 blt r3,zero,10138bc <__fixdfsi+0x30> + 10138e8: 00800784 movi r2,30 + 10138ec: 10c0080e bge r2,r3,1013910 <__fixdfsi+0x84> + 10138f0: d8800317 ldw r2,12(sp) + 10138f4: 1000121e bne r2,zero,1013940 <__fixdfsi+0xb4> + 10138f8: 00e00034 movhi r3,32768 + 10138fc: 18ffffc4 addi r3,r3,-1 + 1013900: 1805883a mov r2,r3 + 1013904: dfc00717 ldw ra,28(sp) + 1013908: dec00804 addi sp,sp,32 + 101390c: f800283a ret + 1013910: 00800f04 movi r2,60 + 1013914: 10d1c83a sub r8,r2,r3 + 1013918: 40bff804 addi r2,r8,-32 + 101391c: d9800517 ldw r6,20(sp) + 1013920: d9c00617 ldw r7,24(sp) + 1013924: 10000816 blt r2,zero,1013948 <__fixdfsi+0xbc> + 1013928: 3888d83a srl r4,r7,r2 + 101392c: d8800317 ldw r2,12(sp) + 1013930: 2007883a mov r3,r4 + 1013934: 103fe226 beq r2,zero,10138c0 <__fixdfsi+0x34> + 1013938: 0107c83a sub r3,zero,r4 + 101393c: 003fe006 br 10138c0 <__fixdfsi+0x34> + 1013940: 00e00034 movhi r3,32768 + 1013944: 003fde06 br 10138c0 <__fixdfsi+0x34> + 1013948: 39c7883a add r3,r7,r7 + 101394c: 008007c4 movi r2,31 + 1013950: 1205c83a sub r2,r2,r8 + 1013954: 1886983a sll r3,r3,r2 + 1013958: 3208d83a srl r4,r6,r8 + 101395c: 1908b03a or r4,r3,r4 + 1013960: 003ff206 br 101392c <__fixdfsi+0xa0> + +01013964 <__floatunsidf>: + 1013964: defff204 addi sp,sp,-56 + 1013968: dfc00d15 stw ra,52(sp) + 101396c: ddc00c15 stw r23,48(sp) + 1013970: dd800b15 stw r22,44(sp) + 1013974: dd400a15 stw r21,40(sp) + 1013978: dd000915 stw r20,36(sp) + 101397c: dcc00815 stw r19,32(sp) + 1013980: dc800715 stw r18,28(sp) + 1013984: dc400615 stw r17,24(sp) + 1013988: dc000515 stw r16,20(sp) + 101398c: d8000115 stw zero,4(sp) + 1013990: 20000f1e bne r4,zero,10139d0 <__floatunsidf+0x6c> + 1013994: 00800084 movi r2,2 + 1013998: d8800015 stw r2,0(sp) + 101399c: d809883a mov r4,sp + 10139a0: 1013d5c0 call 1013d5c <__pack_d> + 10139a4: dfc00d17 ldw ra,52(sp) + 10139a8: ddc00c17 ldw r23,48(sp) + 10139ac: dd800b17 ldw r22,44(sp) + 10139b0: dd400a17 ldw r21,40(sp) + 10139b4: dd000917 ldw r20,36(sp) + 10139b8: dcc00817 ldw r19,32(sp) + 10139bc: dc800717 ldw r18,28(sp) + 10139c0: dc400617 ldw r17,24(sp) + 10139c4: dc000517 ldw r16,20(sp) + 10139c8: dec00e04 addi sp,sp,56 + 10139cc: f800283a ret + 10139d0: 008000c4 movi r2,3 + 10139d4: 00c00f04 movi r3,60 + 10139d8: 002f883a mov r23,zero + 10139dc: 202d883a mov r22,r4 + 10139e0: d8800015 stw r2,0(sp) + 10139e4: d8c00215 stw r3,8(sp) + 10139e8: d9000315 stw r4,12(sp) + 10139ec: ddc00415 stw r23,16(sp) + 10139f0: 1013cdc0 call 1013cdc <__clzsi2> + 10139f4: 12400744 addi r9,r2,29 + 10139f8: 48000b16 blt r9,zero,1013a28 <__floatunsidf+0xc4> + 10139fc: 483fe726 beq r9,zero,101399c <__floatunsidf+0x38> + 1013a00: 10bfff44 addi r2,r2,-3 + 1013a04: 10002e16 blt r2,zero,1013ac0 <__floatunsidf+0x15c> + 1013a08: b0a2983a sll r17,r22,r2 + 1013a0c: 0021883a mov r16,zero + 1013a10: d8800217 ldw r2,8(sp) + 1013a14: dc400415 stw r17,16(sp) + 1013a18: dc000315 stw r16,12(sp) + 1013a1c: 1245c83a sub r2,r2,r9 + 1013a20: d8800215 stw r2,8(sp) + 1013a24: 003fdd06 br 101399c <__floatunsidf+0x38> + 1013a28: 0255c83a sub r10,zero,r9 + 1013a2c: 51bff804 addi r6,r10,-32 + 1013a30: 30001b16 blt r6,zero,1013aa0 <__floatunsidf+0x13c> + 1013a34: b9a8d83a srl r20,r23,r6 + 1013a38: 002b883a mov r21,zero + 1013a3c: 000f883a mov r7,zero + 1013a40: 01000044 movi r4,1 + 1013a44: 0011883a mov r8,zero + 1013a48: 30002516 blt r6,zero,1013ae0 <__floatunsidf+0x17c> + 1013a4c: 21a6983a sll r19,r4,r6 + 1013a50: 0025883a mov r18,zero + 1013a54: 00bfffc4 movi r2,-1 + 1013a58: 9089883a add r4,r18,r2 + 1013a5c: 988b883a add r5,r19,r2 + 1013a60: 248d803a cmpltu r6,r4,r18 + 1013a64: 314b883a add r5,r6,r5 + 1013a68: b104703a and r2,r22,r4 + 1013a6c: b946703a and r3,r23,r5 + 1013a70: 10c4b03a or r2,r2,r3 + 1013a74: 10000226 beq r2,zero,1013a80 <__floatunsidf+0x11c> + 1013a78: 01c00044 movi r7,1 + 1013a7c: 0011883a mov r8,zero + 1013a80: d9000217 ldw r4,8(sp) + 1013a84: a1c4b03a or r2,r20,r7 + 1013a88: aa06b03a or r3,r21,r8 + 1013a8c: 2249c83a sub r4,r4,r9 + 1013a90: d8c00415 stw r3,16(sp) + 1013a94: d9000215 stw r4,8(sp) + 1013a98: d8800315 stw r2,12(sp) + 1013a9c: 003fbf06 br 101399c <__floatunsidf+0x38> + 1013aa0: bdc7883a add r3,r23,r23 + 1013aa4: 008007c4 movi r2,31 + 1013aa8: 1285c83a sub r2,r2,r10 + 1013aac: 1886983a sll r3,r3,r2 + 1013ab0: b2a8d83a srl r20,r22,r10 + 1013ab4: baaad83a srl r21,r23,r10 + 1013ab8: 1d28b03a or r20,r3,r20 + 1013abc: 003fdf06 br 1013a3c <__floatunsidf+0xd8> + 1013ac0: b006d07a srli r3,r22,1 + 1013ac4: 008007c4 movi r2,31 + 1013ac8: 1245c83a sub r2,r2,r9 + 1013acc: 1886d83a srl r3,r3,r2 + 1013ad0: ba62983a sll r17,r23,r9 + 1013ad4: b260983a sll r16,r22,r9 + 1013ad8: 1c62b03a or r17,r3,r17 + 1013adc: 003fcc06 br 1013a10 <__floatunsidf+0xac> + 1013ae0: 2006d07a srli r3,r4,1 + 1013ae4: 008007c4 movi r2,31 + 1013ae8: 1285c83a sub r2,r2,r10 + 1013aec: 18a6d83a srl r19,r3,r2 + 1013af0: 22a4983a sll r18,r4,r10 + 1013af4: 003fd706 br 1013a54 <__floatunsidf+0xf0> + +01013af8 : + 1013af8: 29001b2e bgeu r5,r4,1013b68 + 1013afc: 28001a16 blt r5,zero,1013b68 + 1013b00: 00800044 movi r2,1 + 1013b04: 0007883a mov r3,zero + 1013b08: 01c007c4 movi r7,31 + 1013b0c: 00000306 br 1013b1c + 1013b10: 19c01326 beq r3,r7,1013b60 + 1013b14: 18c00044 addi r3,r3,1 + 1013b18: 28000416 blt r5,zero,1013b2c + 1013b1c: 294b883a add r5,r5,r5 + 1013b20: 1085883a add r2,r2,r2 + 1013b24: 293ffa36 bltu r5,r4,1013b10 + 1013b28: 10000d26 beq r2,zero,1013b60 + 1013b2c: 0007883a mov r3,zero + 1013b30: 21400236 bltu r4,r5,1013b3c + 1013b34: 2149c83a sub r4,r4,r5 + 1013b38: 1886b03a or r3,r3,r2 + 1013b3c: 1004d07a srli r2,r2,1 + 1013b40: 280ad07a srli r5,r5,1 + 1013b44: 103ffa1e bne r2,zero,1013b30 + 1013b48: 30000226 beq r6,zero,1013b54 + 1013b4c: 2005883a mov r2,r4 + 1013b50: f800283a ret + 1013b54: 1809883a mov r4,r3 + 1013b58: 2005883a mov r2,r4 + 1013b5c: f800283a ret + 1013b60: 0007883a mov r3,zero + 1013b64: 003ff806 br 1013b48 + 1013b68: 00800044 movi r2,1 + 1013b6c: 0007883a mov r3,zero + 1013b70: 003fef06 br 1013b30 + +01013b74 <__divsi3>: + 1013b74: defffe04 addi sp,sp,-8 + 1013b78: dc000015 stw r16,0(sp) + 1013b7c: dfc00115 stw ra,4(sp) + 1013b80: 0021883a mov r16,zero + 1013b84: 20000c16 blt r4,zero,1013bb8 <__divsi3+0x44> + 1013b88: 000d883a mov r6,zero + 1013b8c: 28000e16 blt r5,zero,1013bc8 <__divsi3+0x54> + 1013b90: 1013af80 call 1013af8 + 1013b94: 1007883a mov r3,r2 + 1013b98: 8005003a cmpeq r2,r16,zero + 1013b9c: 1000011e bne r2,zero,1013ba4 <__divsi3+0x30> + 1013ba0: 00c7c83a sub r3,zero,r3 + 1013ba4: 1805883a mov r2,r3 + 1013ba8: dfc00117 ldw ra,4(sp) + 1013bac: dc000017 ldw r16,0(sp) + 1013bb0: dec00204 addi sp,sp,8 + 1013bb4: f800283a ret + 1013bb8: 0109c83a sub r4,zero,r4 + 1013bbc: 04000044 movi r16,1 + 1013bc0: 000d883a mov r6,zero + 1013bc4: 283ff20e bge r5,zero,1013b90 <__divsi3+0x1c> + 1013bc8: 014bc83a sub r5,zero,r5 + 1013bcc: 8021003a cmpeq r16,r16,zero + 1013bd0: 003fef06 br 1013b90 <__divsi3+0x1c> + +01013bd4 <__modsi3>: + 1013bd4: deffff04 addi sp,sp,-4 + 1013bd8: dfc00015 stw ra,0(sp) + 1013bdc: 01800044 movi r6,1 + 1013be0: 2807883a mov r3,r5 + 1013be4: 20000416 blt r4,zero,1013bf8 <__modsi3+0x24> + 1013be8: 28000c16 blt r5,zero,1013c1c <__modsi3+0x48> + 1013bec: dfc00017 ldw ra,0(sp) + 1013bf0: dec00104 addi sp,sp,4 + 1013bf4: 1013af81 jmpi 1013af8 + 1013bf8: 0109c83a sub r4,zero,r4 + 1013bfc: 28000b16 blt r5,zero,1013c2c <__modsi3+0x58> + 1013c00: 180b883a mov r5,r3 + 1013c04: 01800044 movi r6,1 + 1013c08: 1013af80 call 1013af8 + 1013c0c: 0085c83a sub r2,zero,r2 + 1013c10: dfc00017 ldw ra,0(sp) + 1013c14: dec00104 addi sp,sp,4 + 1013c18: f800283a ret + 1013c1c: 014bc83a sub r5,zero,r5 + 1013c20: dfc00017 ldw ra,0(sp) + 1013c24: dec00104 addi sp,sp,4 + 1013c28: 1013af81 jmpi 1013af8 + 1013c2c: 0147c83a sub r3,zero,r5 + 1013c30: 003ff306 br 1013c00 <__modsi3+0x2c> + +01013c34 <__udivsi3>: + 1013c34: 000d883a mov r6,zero + 1013c38: 1013af81 jmpi 1013af8 + +01013c3c <__umodsi3>: + 1013c3c: 01800044 movi r6,1 + 1013c40: 1013af81 jmpi 1013af8 + +01013c44 <__muldi3>: + 1013c44: 2011883a mov r8,r4 + 1013c48: 427fffcc andi r9,r8,65535 + 1013c4c: 4018d43a srli r12,r8,16 + 1013c50: 32bfffcc andi r10,r6,65535 + 1013c54: 3016d43a srli r11,r6,16 + 1013c58: 4a85383a mul r2,r9,r10 + 1013c5c: 6295383a mul r10,r12,r10 + 1013c60: 4ad3383a mul r9,r9,r11 + 1013c64: 113fffcc andi r4,r2,65535 + 1013c68: 1004d43a srli r2,r2,16 + 1013c6c: 4a93883a add r9,r9,r10 + 1013c70: 3807883a mov r3,r7 + 1013c74: 1245883a add r2,r2,r9 + 1013c78: 280f883a mov r7,r5 + 1013c7c: 180b883a mov r5,r3 + 1013c80: 1006943a slli r3,r2,16 + 1013c84: defffd04 addi sp,sp,-12 + 1013c88: dc800215 stw r18,8(sp) + 1013c8c: 1907883a add r3,r3,r4 + 1013c90: dc400115 stw r17,4(sp) + 1013c94: dc000015 stw r16,0(sp) + 1013c98: 4165383a mul r18,r8,r5 + 1013c9c: 31e3383a mul r17,r6,r7 + 1013ca0: 1012d43a srli r9,r2,16 + 1013ca4: 62d9383a mul r12,r12,r11 + 1013ca8: 181f883a mov r15,r3 + 1013cac: 1280022e bgeu r2,r10,1013cb8 <__muldi3+0x74> + 1013cb0: 00800074 movhi r2,1 + 1013cb4: 6099883a add r12,r12,r2 + 1013cb8: 624d883a add r6,r12,r9 + 1013cbc: 9187883a add r3,r18,r6 + 1013cc0: 88c7883a add r3,r17,r3 + 1013cc4: 7805883a mov r2,r15 + 1013cc8: dc800217 ldw r18,8(sp) + 1013ccc: dc400117 ldw r17,4(sp) + 1013cd0: dc000017 ldw r16,0(sp) + 1013cd4: dec00304 addi sp,sp,12 + 1013cd8: f800283a ret + +01013cdc <__clzsi2>: + 1013cdc: 00bfffd4 movui r2,65535 + 1013ce0: 11000e36 bltu r2,r4,1013d1c <__clzsi2+0x40> + 1013ce4: 00803fc4 movi r2,255 + 1013ce8: 01400204 movi r5,8 + 1013cec: 0007883a mov r3,zero + 1013cf0: 11001036 bltu r2,r4,1013d34 <__clzsi2+0x58> + 1013cf4: 000b883a mov r5,zero + 1013cf8: 20c6d83a srl r3,r4,r3 + 1013cfc: 008040b4 movhi r2,258 + 1013d00: 10865204 addi r2,r2,6472 + 1013d04: 1887883a add r3,r3,r2 + 1013d08: 18800003 ldbu r2,0(r3) + 1013d0c: 00c00804 movi r3,32 + 1013d10: 2885883a add r2,r5,r2 + 1013d14: 1885c83a sub r2,r3,r2 + 1013d18: f800283a ret + 1013d1c: 01400404 movi r5,16 + 1013d20: 00804034 movhi r2,256 + 1013d24: 10bfffc4 addi r2,r2,-1 + 1013d28: 2807883a mov r3,r5 + 1013d2c: 113ff22e bgeu r2,r4,1013cf8 <__clzsi2+0x1c> + 1013d30: 01400604 movi r5,24 + 1013d34: 2807883a mov r3,r5 + 1013d38: 20c6d83a srl r3,r4,r3 + 1013d3c: 008040b4 movhi r2,258 + 1013d40: 10865204 addi r2,r2,6472 + 1013d44: 1887883a add r3,r3,r2 + 1013d48: 18800003 ldbu r2,0(r3) + 1013d4c: 00c00804 movi r3,32 + 1013d50: 2885883a add r2,r5,r2 + 1013d54: 1885c83a sub r2,r3,r2 + 1013d58: f800283a ret + +01013d5c <__pack_d>: + 1013d5c: 20c00017 ldw r3,0(r4) + 1013d60: defffd04 addi sp,sp,-12 + 1013d64: dc000015 stw r16,0(sp) + 1013d68: dc800215 stw r18,8(sp) + 1013d6c: dc400115 stw r17,4(sp) + 1013d70: 00800044 movi r2,1 + 1013d74: 22000317 ldw r8,12(r4) + 1013d78: 001f883a mov r15,zero + 1013d7c: 22400417 ldw r9,16(r4) + 1013d80: 24000117 ldw r16,4(r4) + 1013d84: 10c0552e bgeu r2,r3,1013edc <__pack_d+0x180> + 1013d88: 00800104 movi r2,4 + 1013d8c: 18804f26 beq r3,r2,1013ecc <__pack_d+0x170> + 1013d90: 00800084 movi r2,2 + 1013d94: 18800226 beq r3,r2,1013da0 <__pack_d+0x44> + 1013d98: 4244b03a or r2,r8,r9 + 1013d9c: 10001a1e bne r2,zero,1013e08 <__pack_d+0xac> + 1013da0: 000d883a mov r6,zero + 1013da4: 000f883a mov r7,zero + 1013da8: 0011883a mov r8,zero + 1013dac: 00800434 movhi r2,16 + 1013db0: 10bfffc4 addi r2,r2,-1 + 1013db4: 301d883a mov r14,r6 + 1013db8: 3884703a and r2,r7,r2 + 1013dbc: 400a953a slli r5,r8,20 + 1013dc0: 79bffc2c andhi r6,r15,65520 + 1013dc4: 308cb03a or r6,r6,r2 + 1013dc8: 00e00434 movhi r3,32784 + 1013dcc: 18ffffc4 addi r3,r3,-1 + 1013dd0: 800497fa slli r2,r16,31 + 1013dd4: 30c6703a and r3,r6,r3 + 1013dd8: 1946b03a or r3,r3,r5 + 1013ddc: 01600034 movhi r5,32768 + 1013de0: 297fffc4 addi r5,r5,-1 + 1013de4: 194a703a and r5,r3,r5 + 1013de8: 288ab03a or r5,r5,r2 + 1013dec: 2807883a mov r3,r5 + 1013df0: 7005883a mov r2,r14 + 1013df4: dc800217 ldw r18,8(sp) + 1013df8: dc400117 ldw r17,4(sp) + 1013dfc: dc000017 ldw r16,0(sp) + 1013e00: dec00304 addi sp,sp,12 + 1013e04: f800283a ret + 1013e08: 21000217 ldw r4,8(r4) + 1013e0c: 00bf0084 movi r2,-1022 + 1013e10: 20803f16 blt r4,r2,1013f10 <__pack_d+0x1b4> + 1013e14: 0080ffc4 movi r2,1023 + 1013e18: 11002c16 blt r2,r4,1013ecc <__pack_d+0x170> + 1013e1c: 00803fc4 movi r2,255 + 1013e20: 408c703a and r6,r8,r2 + 1013e24: 00802004 movi r2,128 + 1013e28: 0007883a mov r3,zero + 1013e2c: 000f883a mov r7,zero + 1013e30: 2280ffc4 addi r10,r4,1023 + 1013e34: 30801e26 beq r6,r2,1013eb0 <__pack_d+0x154> + 1013e38: 00801fc4 movi r2,127 + 1013e3c: 4089883a add r4,r8,r2 + 1013e40: 220d803a cmpltu r6,r4,r8 + 1013e44: 324d883a add r6,r6,r9 + 1013e48: 2011883a mov r8,r4 + 1013e4c: 3013883a mov r9,r6 + 1013e50: 00880034 movhi r2,8192 + 1013e54: 10bfffc4 addi r2,r2,-1 + 1013e58: 12400d36 bltu r2,r9,1013e90 <__pack_d+0x134> + 1013e5c: 4804963a slli r2,r9,24 + 1013e60: 400cd23a srli r6,r8,8 + 1013e64: 480ed23a srli r7,r9,8 + 1013e68: 013fffc4 movi r4,-1 + 1013e6c: 118cb03a or r6,r2,r6 + 1013e70: 01400434 movhi r5,16 + 1013e74: 297fffc4 addi r5,r5,-1 + 1013e78: 3104703a and r2,r6,r4 + 1013e7c: 3946703a and r3,r7,r5 + 1013e80: 5201ffcc andi r8,r10,2047 + 1013e84: 100d883a mov r6,r2 + 1013e88: 180f883a mov r7,r3 + 1013e8c: 003fc706 br 1013dac <__pack_d+0x50> + 1013e90: 480897fa slli r4,r9,31 + 1013e94: 4004d07a srli r2,r8,1 + 1013e98: 4806d07a srli r3,r9,1 + 1013e9c: 52800044 addi r10,r10,1 + 1013ea0: 2084b03a or r2,r4,r2 + 1013ea4: 1011883a mov r8,r2 + 1013ea8: 1813883a mov r9,r3 + 1013eac: 003feb06 br 1013e5c <__pack_d+0x100> + 1013eb0: 383fe11e bne r7,zero,1013e38 <__pack_d+0xdc> + 1013eb4: 01004004 movi r4,256 + 1013eb8: 4104703a and r2,r8,r4 + 1013ebc: 10c4b03a or r2,r2,r3 + 1013ec0: 103fe326 beq r2,zero,1013e50 <__pack_d+0xf4> + 1013ec4: 3005883a mov r2,r6 + 1013ec8: 003fdc06 br 1013e3c <__pack_d+0xe0> + 1013ecc: 000d883a mov r6,zero + 1013ed0: 000f883a mov r7,zero + 1013ed4: 0201ffc4 movi r8,2047 + 1013ed8: 003fb406 br 1013dac <__pack_d+0x50> + 1013edc: 0005883a mov r2,zero + 1013ee0: 00c00234 movhi r3,8 + 1013ee4: 408cb03a or r6,r8,r2 + 1013ee8: 48ceb03a or r7,r9,r3 + 1013eec: 013fffc4 movi r4,-1 + 1013ef0: 01400434 movhi r5,16 + 1013ef4: 297fffc4 addi r5,r5,-1 + 1013ef8: 3104703a and r2,r6,r4 + 1013efc: 3946703a and r3,r7,r5 + 1013f00: 100d883a mov r6,r2 + 1013f04: 180f883a mov r7,r3 + 1013f08: 0201ffc4 movi r8,2047 + 1013f0c: 003fa706 br 1013dac <__pack_d+0x50> + 1013f10: 1109c83a sub r4,r2,r4 + 1013f14: 00800e04 movi r2,56 + 1013f18: 11004316 blt r2,r4,1014028 <__pack_d+0x2cc> + 1013f1c: 21fff804 addi r7,r4,-32 + 1013f20: 38004516 blt r7,zero,1014038 <__pack_d+0x2dc> + 1013f24: 49d8d83a srl r12,r9,r7 + 1013f28: 001b883a mov r13,zero + 1013f2c: 0023883a mov r17,zero + 1013f30: 01400044 movi r5,1 + 1013f34: 0025883a mov r18,zero + 1013f38: 38004716 blt r7,zero,1014058 <__pack_d+0x2fc> + 1013f3c: 29d6983a sll r11,r5,r7 + 1013f40: 0015883a mov r10,zero + 1013f44: 00bfffc4 movi r2,-1 + 1013f48: 5089883a add r4,r10,r2 + 1013f4c: 588b883a add r5,r11,r2 + 1013f50: 228d803a cmpltu r6,r4,r10 + 1013f54: 314b883a add r5,r6,r5 + 1013f58: 4104703a and r2,r8,r4 + 1013f5c: 4946703a and r3,r9,r5 + 1013f60: 10c4b03a or r2,r2,r3 + 1013f64: 10000226 beq r2,zero,1013f70 <__pack_d+0x214> + 1013f68: 04400044 movi r17,1 + 1013f6c: 0025883a mov r18,zero + 1013f70: 00803fc4 movi r2,255 + 1013f74: 644eb03a or r7,r12,r17 + 1013f78: 3892703a and r9,r7,r2 + 1013f7c: 00802004 movi r2,128 + 1013f80: 6c90b03a or r8,r13,r18 + 1013f84: 0015883a mov r10,zero + 1013f88: 48801626 beq r9,r2,1013fe4 <__pack_d+0x288> + 1013f8c: 01001fc4 movi r4,127 + 1013f90: 3905883a add r2,r7,r4 + 1013f94: 11cd803a cmpltu r6,r2,r7 + 1013f98: 320d883a add r6,r6,r8 + 1013f9c: 100f883a mov r7,r2 + 1013fa0: 00840034 movhi r2,4096 + 1013fa4: 10bfffc4 addi r2,r2,-1 + 1013fa8: 3011883a mov r8,r6 + 1013fac: 0007883a mov r3,zero + 1013fb0: 11801b36 bltu r2,r6,1014020 <__pack_d+0x2c4> + 1013fb4: 4004963a slli r2,r8,24 + 1013fb8: 3808d23a srli r4,r7,8 + 1013fbc: 400ad23a srli r5,r8,8 + 1013fc0: 1813883a mov r9,r3 + 1013fc4: 1108b03a or r4,r2,r4 + 1013fc8: 00bfffc4 movi r2,-1 + 1013fcc: 00c00434 movhi r3,16 + 1013fd0: 18ffffc4 addi r3,r3,-1 + 1013fd4: 208c703a and r6,r4,r2 + 1013fd8: 28ce703a and r7,r5,r3 + 1013fdc: 4a01ffcc andi r8,r9,2047 + 1013fe0: 003f7206 br 1013dac <__pack_d+0x50> + 1013fe4: 503fe91e bne r10,zero,1013f8c <__pack_d+0x230> + 1013fe8: 01004004 movi r4,256 + 1013fec: 3904703a and r2,r7,r4 + 1013ff0: 0007883a mov r3,zero + 1013ff4: 10c4b03a or r2,r2,r3 + 1013ff8: 10000626 beq r2,zero,1014014 <__pack_d+0x2b8> + 1013ffc: 3a45883a add r2,r7,r9 + 1014000: 11cd803a cmpltu r6,r2,r7 + 1014004: 320d883a add r6,r6,r8 + 1014008: 100f883a mov r7,r2 + 101400c: 3011883a mov r8,r6 + 1014010: 0007883a mov r3,zero + 1014014: 00840034 movhi r2,4096 + 1014018: 10bfffc4 addi r2,r2,-1 + 101401c: 123fe52e bgeu r2,r8,1013fb4 <__pack_d+0x258> + 1014020: 00c00044 movi r3,1 + 1014024: 003fe306 br 1013fb4 <__pack_d+0x258> + 1014028: 0009883a mov r4,zero + 101402c: 0013883a mov r9,zero + 1014030: 000b883a mov r5,zero + 1014034: 003fe406 br 1013fc8 <__pack_d+0x26c> + 1014038: 4a47883a add r3,r9,r9 + 101403c: 008007c4 movi r2,31 + 1014040: 1105c83a sub r2,r2,r4 + 1014044: 1886983a sll r3,r3,r2 + 1014048: 4118d83a srl r12,r8,r4 + 101404c: 491ad83a srl r13,r9,r4 + 1014050: 1b18b03a or r12,r3,r12 + 1014054: 003fb506 br 1013f2c <__pack_d+0x1d0> + 1014058: 2806d07a srli r3,r5,1 + 101405c: 008007c4 movi r2,31 + 1014060: 1105c83a sub r2,r2,r4 + 1014064: 1896d83a srl r11,r3,r2 + 1014068: 2914983a sll r10,r5,r4 + 101406c: 003fb506 br 1013f44 <__pack_d+0x1e8> + +01014070 <__unpack_d>: + 1014070: 20c00117 ldw r3,4(r4) + 1014074: 22400017 ldw r9,0(r4) + 1014078: 00800434 movhi r2,16 + 101407c: 10bfffc4 addi r2,r2,-1 + 1014080: 1808d53a srli r4,r3,20 + 1014084: 180cd7fa srli r6,r3,31 + 1014088: 1894703a and r10,r3,r2 + 101408c: 2201ffcc andi r8,r4,2047 + 1014090: 281b883a mov r13,r5 + 1014094: 4817883a mov r11,r9 + 1014098: 29800115 stw r6,4(r5) + 101409c: 5019883a mov r12,r10 + 10140a0: 40001e1e bne r8,zero,101411c <__unpack_d+0xac> + 10140a4: 4a84b03a or r2,r9,r10 + 10140a8: 10001926 beq r2,zero,1014110 <__unpack_d+0xa0> + 10140ac: 4804d63a srli r2,r9,24 + 10140b0: 500c923a slli r6,r10,8 + 10140b4: 013f0084 movi r4,-1022 + 10140b8: 00c40034 movhi r3,4096 + 10140bc: 18ffffc4 addi r3,r3,-1 + 10140c0: 118cb03a or r6,r2,r6 + 10140c4: 008000c4 movi r2,3 + 10140c8: 480a923a slli r5,r9,8 + 10140cc: 68800015 stw r2,0(r13) + 10140d0: 69000215 stw r4,8(r13) + 10140d4: 19800b36 bltu r3,r6,1014104 <__unpack_d+0x94> + 10140d8: 200f883a mov r7,r4 + 10140dc: 1811883a mov r8,r3 + 10140e0: 2945883a add r2,r5,r5 + 10140e4: 1149803a cmpltu r4,r2,r5 + 10140e8: 3187883a add r3,r6,r6 + 10140ec: 20c9883a add r4,r4,r3 + 10140f0: 100b883a mov r5,r2 + 10140f4: 200d883a mov r6,r4 + 10140f8: 39ffffc4 addi r7,r7,-1 + 10140fc: 413ff82e bgeu r8,r4,10140e0 <__unpack_d+0x70> + 1014100: 69c00215 stw r7,8(r13) + 1014104: 69800415 stw r6,16(r13) + 1014108: 69400315 stw r5,12(r13) + 101410c: f800283a ret + 1014110: 00800084 movi r2,2 + 1014114: 28800015 stw r2,0(r5) + 1014118: f800283a ret + 101411c: 0081ffc4 movi r2,2047 + 1014120: 40800f26 beq r8,r2,1014160 <__unpack_d+0xf0> + 1014124: 480cd63a srli r6,r9,24 + 1014128: 5006923a slli r3,r10,8 + 101412c: 4804923a slli r2,r9,8 + 1014130: 0009883a mov r4,zero + 1014134: 30c6b03a or r3,r6,r3 + 1014138: 01440034 movhi r5,4096 + 101413c: 110cb03a or r6,r2,r4 + 1014140: 423f0044 addi r8,r8,-1023 + 1014144: 194eb03a or r7,r3,r5 + 1014148: 008000c4 movi r2,3 + 101414c: 69c00415 stw r7,16(r13) + 1014150: 6a000215 stw r8,8(r13) + 1014154: 68800015 stw r2,0(r13) + 1014158: 69800315 stw r6,12(r13) + 101415c: f800283a ret + 1014160: 4a84b03a or r2,r9,r10 + 1014164: 1000031e bne r2,zero,1014174 <__unpack_d+0x104> + 1014168: 00800104 movi r2,4 + 101416c: 28800015 stw r2,0(r5) + 1014170: f800283a ret + 1014174: 0009883a mov r4,zero + 1014178: 01400234 movhi r5,8 + 101417c: 4904703a and r2,r9,r4 + 1014180: 5146703a and r3,r10,r5 + 1014184: 10c4b03a or r2,r2,r3 + 1014188: 10000526 beq r2,zero,10141a0 <__unpack_d+0x130> + 101418c: 00800044 movi r2,1 + 1014190: 68800015 stw r2,0(r13) + 1014194: 6b000415 stw r12,16(r13) + 1014198: 6ac00315 stw r11,12(r13) + 101419c: f800283a ret + 10141a0: 68000015 stw zero,0(r13) + 10141a4: 003ffb06 br 1014194 <__unpack_d+0x124> + +010141a8 <__fpcmp_parts_d>: + 10141a8: 21800017 ldw r6,0(r4) + 10141ac: 00c00044 movi r3,1 + 10141b0: 19800a2e bgeu r3,r6,10141dc <__fpcmp_parts_d+0x34> + 10141b4: 28800017 ldw r2,0(r5) + 10141b8: 1880082e bgeu r3,r2,10141dc <__fpcmp_parts_d+0x34> + 10141bc: 00c00104 movi r3,4 + 10141c0: 30c02626 beq r6,r3,101425c <__fpcmp_parts_d+0xb4> + 10141c4: 10c02226 beq r2,r3,1014250 <__fpcmp_parts_d+0xa8> + 10141c8: 00c00084 movi r3,2 + 10141cc: 30c00526 beq r6,r3,10141e4 <__fpcmp_parts_d+0x3c> + 10141d0: 10c0071e bne r2,r3,10141f0 <__fpcmp_parts_d+0x48> + 10141d4: 20800117 ldw r2,4(r4) + 10141d8: 1000091e bne r2,zero,1014200 <__fpcmp_parts_d+0x58> + 10141dc: 00800044 movi r2,1 + 10141e0: f800283a ret + 10141e4: 10c01a1e bne r2,r3,1014250 <__fpcmp_parts_d+0xa8> + 10141e8: 0005883a mov r2,zero + 10141ec: f800283a ret + 10141f0: 22000117 ldw r8,4(r4) + 10141f4: 28800117 ldw r2,4(r5) + 10141f8: 40800326 beq r8,r2,1014208 <__fpcmp_parts_d+0x60> + 10141fc: 403ff726 beq r8,zero,10141dc <__fpcmp_parts_d+0x34> + 1014200: 00bfffc4 movi r2,-1 + 1014204: f800283a ret + 1014208: 20c00217 ldw r3,8(r4) + 101420c: 28800217 ldw r2,8(r5) + 1014210: 10fffa16 blt r2,r3,10141fc <__fpcmp_parts_d+0x54> + 1014214: 18800916 blt r3,r2,101423c <__fpcmp_parts_d+0x94> + 1014218: 21c00417 ldw r7,16(r4) + 101421c: 28c00417 ldw r3,16(r5) + 1014220: 21800317 ldw r6,12(r4) + 1014224: 28800317 ldw r2,12(r5) + 1014228: 19fff436 bltu r3,r7,10141fc <__fpcmp_parts_d+0x54> + 101422c: 38c00526 beq r7,r3,1014244 <__fpcmp_parts_d+0x9c> + 1014230: 38c00236 bltu r7,r3,101423c <__fpcmp_parts_d+0x94> + 1014234: 19ffec1e bne r3,r7,10141e8 <__fpcmp_parts_d+0x40> + 1014238: 30bfeb2e bgeu r6,r2,10141e8 <__fpcmp_parts_d+0x40> + 101423c: 403fe71e bne r8,zero,10141dc <__fpcmp_parts_d+0x34> + 1014240: 003fef06 br 1014200 <__fpcmp_parts_d+0x58> + 1014244: 11bffa2e bgeu r2,r6,1014230 <__fpcmp_parts_d+0x88> + 1014248: 403fe426 beq r8,zero,10141dc <__fpcmp_parts_d+0x34> + 101424c: 003fec06 br 1014200 <__fpcmp_parts_d+0x58> + 1014250: 28800117 ldw r2,4(r5) + 1014254: 103fe11e bne r2,zero,10141dc <__fpcmp_parts_d+0x34> + 1014258: 003fe906 br 1014200 <__fpcmp_parts_d+0x58> + 101425c: 11bfdd1e bne r2,r6,10141d4 <__fpcmp_parts_d+0x2c> + 1014260: 28c00117 ldw r3,4(r5) + 1014264: 20800117 ldw r2,4(r4) + 1014268: 1885c83a sub r2,r3,r2 + 101426c: f800283a ret + +01014270 : + * + * ALT_CLOSE is mapped onto the close() system call in alt_syscall.h + */ + +int ALT_CLOSE (int fildes) +{ + 1014270: defff804 addi sp,sp,-32 + 1014274: dfc00715 stw ra,28(sp) + 1014278: df000615 stw fp,24(sp) + 101427c: df000604 addi fp,sp,24 + 1014280: e13ffc15 stw r4,-16(fp) + * A common error case is that when the file descriptor was created, the call + * to open() failed resulting in a negative file descriptor. This is trapped + * below so that we don't try and process an invalid file descriptor. + */ + + fd = (fildes < 0) ? NULL : &alt_fd_list[fildes]; + 1014284: e0bffc17 ldw r2,-16(fp) + 1014288: 1004803a cmplt r2,r2,zero + 101428c: 1000081e bne r2,zero,10142b0 + 1014290: e0bffc17 ldw r2,-16(fp) + 1014294: 10800324 muli r2,r2,12 + 1014298: 1007883a mov r3,r2 + 101429c: 008040b4 movhi r2,258 + 10142a0: 1088ff04 addi r2,r2,9212 + 10142a4: 1887883a add r3,r3,r2 + 10142a8: e0ffff15 stw r3,-4(fp) + 10142ac: 00000106 br 10142b4 + 10142b0: e03fff15 stw zero,-4(fp) + 10142b4: e0bfff17 ldw r2,-4(fp) + 10142b8: e0bffb15 stw r2,-20(fp) + + if (fd) + 10142bc: e0bffb17 ldw r2,-20(fp) + 10142c0: 1005003a cmpeq r2,r2,zero + 10142c4: 10001d1e bne r2,zero,101433c + /* + * If the associated file system/device has a close function, call it so + * that any necessary cleanup code can run. + */ + + rval = (fd->dev->close) ? fd->dev->close(fd) : 0; + 10142c8: e0bffb17 ldw r2,-20(fp) + 10142cc: 10800017 ldw r2,0(r2) + 10142d0: 10800417 ldw r2,16(r2) + 10142d4: 1005003a cmpeq r2,r2,zero + 10142d8: 1000071e bne r2,zero,10142f8 + 10142dc: e0bffb17 ldw r2,-20(fp) + 10142e0: 10800017 ldw r2,0(r2) + 10142e4: 10800417 ldw r2,16(r2) + 10142e8: e13ffb17 ldw r4,-20(fp) + 10142ec: 103ee83a callr r2 + 10142f0: e0bffe15 stw r2,-8(fp) + 10142f4: 00000106 br 10142fc + 10142f8: e03ffe15 stw zero,-8(fp) + 10142fc: e0bffe17 ldw r2,-8(fp) + 1014300: e0bffa15 stw r2,-24(fp) + + /* Free the file descriptor structure and return. */ + + alt_release_fd (fildes); + 1014304: e13ffc17 ldw r4,-16(fp) + 1014308: 1014cfc0 call 1014cfc + if (rval < 0) + 101430c: e0bffa17 ldw r2,-24(fp) + 1014310: 1004403a cmpge r2,r2,zero + 1014314: 1000071e bne r2,zero,1014334 + { + ALT_ERRNO = -rval; + 1014318: 101436c0 call 101436c + 101431c: e0fffa17 ldw r3,-24(fp) + 1014320: 00c7c83a sub r3,zero,r3 + 1014324: 10c00015 stw r3,0(r2) + return -1; + 1014328: 00bfffc4 movi r2,-1 + 101432c: e0bffd15 stw r2,-12(fp) + 1014330: 00000806 br 1014354 + } + return 0; + 1014334: e03ffd15 stw zero,-12(fp) + 1014338: 00000606 br 1014354 + } + else + { + ALT_ERRNO = EBADFD; + 101433c: 101436c0 call 101436c + 1014340: 1007883a mov r3,r2 + 1014344: 00801444 movi r2,81 + 1014348: 18800015 stw r2,0(r3) + return -1; + 101434c: 00bfffc4 movi r2,-1 + 1014350: e0bffd15 stw r2,-12(fp) + 1014354: e0bffd17 ldw r2,-12(fp) + } +} + 1014358: e037883a mov sp,fp + 101435c: dfc00117 ldw ra,4(sp) + 1014360: df000017 ldw fp,0(sp) + 1014364: dec00204 addi sp,sp,8 + 1014368: f800283a ret + +0101436c : +#undef errno + +extern int errno; + +static ALT_INLINE int* alt_get_errno(void) +{ + 101436c: defffd04 addi sp,sp,-12 + 1014370: dfc00215 stw ra,8(sp) + 1014374: df000115 stw fp,4(sp) + 1014378: df000104 addi fp,sp,4 + return ((alt_errno) ? alt_errno() : &errno); + 101437c: 008040b4 movhi r2,258 + 1014380: 108dd104 addi r2,r2,14148 + 1014384: 10800017 ldw r2,0(r2) + 1014388: 1005003a cmpeq r2,r2,zero + 101438c: 1000061e bne r2,zero,10143a8 + 1014390: 008040b4 movhi r2,258 + 1014394: 108dd104 addi r2,r2,14148 + 1014398: 10800017 ldw r2,0(r2) + 101439c: 103ee83a callr r2 + 10143a0: e0bfff15 stw r2,-4(fp) + 10143a4: 00000306 br 10143b4 + 10143a8: 008040b4 movhi r2,258 + 10143ac: 10950804 addi r2,r2,21536 + 10143b0: e0bfff15 stw r2,-4(fp) + 10143b4: e0bfff17 ldw r2,-4(fp) +} + 10143b8: e037883a mov sp,fp + 10143bc: dfc00117 ldw ra,4(sp) + 10143c0: df000017 ldw fp,0(sp) + 10143c4: dec00204 addi sp,sp,8 + 10143c8: f800283a ret + +010143cc : + * by the alt_dev_null device. It simple discards all data passed to it, and + * indicates that the data has been successfully transmitted. + */ + +static int alt_dev_null_write (alt_fd* fd, const char* ptr, int len) +{ + 10143cc: defffc04 addi sp,sp,-16 + 10143d0: df000315 stw fp,12(sp) + 10143d4: df000304 addi fp,sp,12 + 10143d8: e13ffd15 stw r4,-12(fp) + 10143dc: e17ffe15 stw r5,-8(fp) + 10143e0: e1bfff15 stw r6,-4(fp) + return len; + 10143e4: e0bfff17 ldw r2,-4(fp) +} + 10143e8: e037883a mov sp,fp + 10143ec: df000017 ldw fp,0(sp) + 10143f0: dec00104 addi sp,sp,4 + 10143f4: f800283a ret + +010143f8 : + +/* + * Routine called on exit. + */ +static ALT_ALWAYS_INLINE void alt_sim_halt(int exit_code) +{ + 10143f8: defffd04 addi sp,sp,-12 + 10143fc: df000215 stw fp,8(sp) + 1014400: df000204 addi fp,sp,8 + 1014404: e13fff15 stw r4,-4(fp) + int r2 = exit_code; + 1014408: e0bfff17 ldw r2,-4(fp) + 101440c: e0bffe15 stw r2,-8(fp) + __asm__ volatile ("\n0:\n\taddi %0,%0, -1\n\tbgt %0,zero,0b" : : "r" (ALT_CPU_FREQ/100) ); /* Delay for >30ms */ + + __asm__ volatile ("break 2" : : "D02"(r2), "D03"(r3) ALT_GMON_DATA ); + +#else /* !DEBUG_STUB */ + if (r2) { + 1014410: e0bffe17 ldw r2,-8(fp) + 1014414: 1005003a cmpeq r2,r2,zero + 1014418: 1000021e bne r2,zero,1014424 + ALT_SIM_FAIL(); + 101441c: 002af070 cmpltui zero,zero,43969 + 1014420: 00000106 br 1014428 + } else { + ALT_SIM_PASS(); + 1014424: 002af0b0 cmpltui zero,zero,43970 + } +#endif /* DEBUG_STUB */ +} + 1014428: e037883a mov sp,fp + 101442c: df000017 ldw fp,0(sp) + 1014430: dec00104 addi sp,sp,4 + 1014434: f800283a ret + +01014438 <_exit>: + * + * ALT_EXIT is mapped onto the _exit() system call in alt_syscall.h + */ + +void ALT_EXIT (int exit_code) +{ + 1014438: defffd04 addi sp,sp,-12 + 101443c: dfc00215 stw ra,8(sp) + 1014440: df000115 stw fp,4(sp) + 1014444: df000104 addi fp,sp,4 + 1014448: e13fff15 stw r4,-4(fp) + ALT_LOG_PRINT_BOOT("[alt_exit.c] Entering _exit() function.\r\n"); + ALT_LOG_PRINT_BOOT("[alt_exit.c] Exit code from main was %d.\r\n",exit_code); + /* Stop all other threads */ + + ALT_LOG_PRINT_BOOT("[alt_exit.c] Calling ALT_OS_STOP().\r\n"); + ALT_OS_STOP(); + 101444c: 008040b4 movhi r2,258 + 1014450: 10951444 addi r2,r2,21585 + 1014454: 10000005 stb zero,0(r2) + + /* Provide notification to the simulator that we've stopped */ + + ALT_LOG_PRINT_BOOT("[alt_exit.c] Calling ALT_SIM_HALT().\r\n"); + ALT_SIM_HALT(exit_code); + 1014458: e13fff17 ldw r4,-4(fp) + 101445c: 10143f80 call 10143f8 + + /* spin forever, since there's no where to go back to */ + + ALT_LOG_PRINT_BOOT("[alt_exit.c] Spinning forever.\r\n"); + while (1); + 1014460: 003fff06 br 1014460 <_exit+0x28> + +01014464 : +} + +#else /* !ALT_USE_DIRECT_DRIVERS */ + +int ALT_FSTAT (int file, struct stat *st) +{ + 1014464: defff904 addi sp,sp,-28 + 1014468: dfc00615 stw ra,24(sp) + 101446c: df000515 stw fp,20(sp) + 1014470: df000504 addi fp,sp,20 + 1014474: e13ffc15 stw r4,-16(fp) + 1014478: e17ffd15 stw r5,-12(fp) + * A common error case is that when the file descriptor was created, the call + * to open() failed resulting in a negative file descriptor. This is trapped + * below so that we don't try and process an invalid file descriptor. + */ + + fd = (file < 0) ? NULL : &alt_fd_list[file]; + 101447c: e0bffc17 ldw r2,-16(fp) + 1014480: 1004803a cmplt r2,r2,zero + 1014484: 1000081e bne r2,zero,10144a8 + 1014488: e0bffc17 ldw r2,-16(fp) + 101448c: 10800324 muli r2,r2,12 + 1014490: 1007883a mov r3,r2 + 1014494: 008040b4 movhi r2,258 + 1014498: 1088ff04 addi r2,r2,9212 + 101449c: 1887883a add r3,r3,r2 + 10144a0: e0ffff15 stw r3,-4(fp) + 10144a4: 00000106 br 10144ac + 10144a8: e03fff15 stw zero,-4(fp) + 10144ac: e0bfff17 ldw r2,-4(fp) + 10144b0: e0bffb15 stw r2,-20(fp) + + if (fd) + 10144b4: e0bffb17 ldw r2,-20(fp) + 10144b8: 1005003a cmpeq r2,r2,zero + 10144bc: 1000121e bne r2,zero,1014508 + { + /* Call the drivers fstat() function to fill out the "st" structure. */ + + if (fd->dev->fstat) + 10144c0: e0bffb17 ldw r2,-20(fp) + 10144c4: 10800017 ldw r2,0(r2) + 10144c8: 10800817 ldw r2,32(r2) + 10144cc: 1005003a cmpeq r2,r2,zero + 10144d0: 1000081e bne r2,zero,10144f4 + { + return fd->dev->fstat(fd, st); + 10144d4: e0bffb17 ldw r2,-20(fp) + 10144d8: 10800017 ldw r2,0(r2) + 10144dc: 10800817 ldw r2,32(r2) + 10144e0: e13ffb17 ldw r4,-20(fp) + 10144e4: e17ffd17 ldw r5,-12(fp) + 10144e8: 103ee83a callr r2 + 10144ec: e0bffe15 stw r2,-8(fp) + 10144f0: 00000b06 br 1014520 + * device. + */ + + else + { + st->st_mode = _IFCHR; + 10144f4: e0fffd17 ldw r3,-12(fp) + 10144f8: 00880004 movi r2,8192 + 10144fc: 18800115 stw r2,4(r3) + return 0; + 1014500: e03ffe15 stw zero,-8(fp) + 1014504: 00000606 br 1014520 + } + } + else + { + ALT_ERRNO = EBADFD; + 1014508: 10145380 call 1014538 + 101450c: 1007883a mov r3,r2 + 1014510: 00801444 movi r2,81 + 1014514: 18800015 stw r2,0(r3) + return -1; + 1014518: 00bfffc4 movi r2,-1 + 101451c: e0bffe15 stw r2,-8(fp) + 1014520: e0bffe17 ldw r2,-8(fp) + } +} + 1014524: e037883a mov sp,fp + 1014528: dfc00117 ldw ra,4(sp) + 101452c: df000017 ldw fp,0(sp) + 1014530: dec00204 addi sp,sp,8 + 1014534: f800283a ret + +01014538 : +#undef errno + +extern int errno; + +static ALT_INLINE int* alt_get_errno(void) +{ + 1014538: defffd04 addi sp,sp,-12 + 101453c: dfc00215 stw ra,8(sp) + 1014540: df000115 stw fp,4(sp) + 1014544: df000104 addi fp,sp,4 + return ((alt_errno) ? alt_errno() : &errno); + 1014548: 008040b4 movhi r2,258 + 101454c: 108dd104 addi r2,r2,14148 + 1014550: 10800017 ldw r2,0(r2) + 1014554: 1005003a cmpeq r2,r2,zero + 1014558: 1000061e bne r2,zero,1014574 + 101455c: 008040b4 movhi r2,258 + 1014560: 108dd104 addi r2,r2,14148 + 1014564: 10800017 ldw r2,0(r2) + 1014568: 103ee83a callr r2 + 101456c: e0bfff15 stw r2,-4(fp) + 1014570: 00000306 br 1014580 + 1014574: 008040b4 movhi r2,258 + 1014578: 10950804 addi r2,r2,21536 + 101457c: e0bfff15 stw r2,-4(fp) + 1014580: e0bfff17 ldw r2,-4(fp) +} + 1014584: e037883a mov sp,fp + 1014588: dfc00117 ldw ra,4(sp) + 101458c: df000017 ldw fp,0(sp) + 1014590: dec00204 addi sp,sp,8 + 1014594: f800283a ret + +01014598 : + * + * ALT_GETPID is mapped onto the getpid() system call in alt_syscall.h + */ + +int ALT_GETPID (void) +{ + 1014598: deffff04 addi sp,sp,-4 + 101459c: df000015 stw fp,0(sp) + 10145a0: d839883a mov fp,sp + return 0; + 10145a4: 0005883a mov r2,zero +} + 10145a8: e037883a mov sp,fp + 10145ac: df000017 ldw fp,0(sp) + 10145b0: dec00104 addi sp,sp,4 + 10145b4: f800283a ret + +010145b8 : + * + * ALT_ISATTY is mapped onto the isatty() system call in alt_syscall.h + */ + +int ALT_ISATTY (int file) +{ + 10145b8: deffeb04 addi sp,sp,-84 + 10145bc: dfc01415 stw ra,80(sp) + 10145c0: df001315 stw fp,76(sp) + 10145c4: df001304 addi fp,sp,76 + 10145c8: e13ffd15 stw r4,-12(fp) + * A common error case is that when the file descriptor was created, the call + * to open() failed resulting in a negative file descriptor. This is trapped + * below so that we don't try and process an invalid file descriptor. + */ + + fd = (file < 0) ? NULL : &alt_fd_list[file]; + 10145cc: e0bffd17 ldw r2,-12(fp) + 10145d0: 1004803a cmplt r2,r2,zero + 10145d4: 1000081e bne r2,zero,10145f8 + 10145d8: e0bffd17 ldw r2,-12(fp) + 10145dc: 10800324 muli r2,r2,12 + 10145e0: 1007883a mov r3,r2 + 10145e4: 008040b4 movhi r2,258 + 10145e8: 1088ff04 addi r2,r2,9212 + 10145ec: 1887883a add r3,r3,r2 + 10145f0: e0ffff15 stw r3,-4(fp) + 10145f4: 00000106 br 10145fc + 10145f8: e03fff15 stw zero,-4(fp) + 10145fc: e0bfff17 ldw r2,-4(fp) + 1014600: e0bfed15 stw r2,-76(fp) + + if (fd) + 1014604: e0bfed17 ldw r2,-76(fp) + 1014608: 1005003a cmpeq r2,r2,zero + 101460c: 10000f1e bne r2,zero,101464c + /* + * If a device driver does not provide an fstat() function, then it is + * treated as a terminal device by default. + */ + + if (!fd->dev->fstat) + 1014610: e0bfed17 ldw r2,-76(fp) + 1014614: 10800017 ldw r2,0(r2) + 1014618: 10800817 ldw r2,32(r2) + 101461c: 1004c03a cmpne r2,r2,zero + 1014620: 1000031e bne r2,zero,1014630 + { + return 1; + 1014624: 00800044 movi r2,1 + 1014628: e0bffe15 stw r2,-8(fp) + 101462c: 00000c06 br 1014660 + * this is called so that the device can identify itself. + */ + + else + { + fstat (file, &stat); + 1014630: e17fee04 addi r5,fp,-72 + 1014634: e13ffd17 ldw r4,-12(fp) + 1014638: 10144640 call 1014464 + return (stat.st_mode == _IFCHR) ? 1 : 0; + 101463c: e0bfef17 ldw r2,-68(fp) + 1014640: 10880020 cmpeqi r2,r2,8192 + 1014644: e0bffe15 stw r2,-8(fp) + 1014648: 00000506 br 1014660 + } + } + else + { + ALT_ERRNO = EBADFD; + 101464c: 10146780 call 1014678 + 1014650: 1007883a mov r3,r2 + 1014654: 00801444 movi r2,81 + 1014658: 18800015 stw r2,0(r3) + return 0; + 101465c: e03ffe15 stw zero,-8(fp) + 1014660: e0bffe17 ldw r2,-8(fp) + } +} + 1014664: e037883a mov sp,fp + 1014668: dfc00117 ldw ra,4(sp) + 101466c: df000017 ldw fp,0(sp) + 1014670: dec00204 addi sp,sp,8 + 1014674: f800283a ret + +01014678 : +#undef errno + +extern int errno; + +static ALT_INLINE int* alt_get_errno(void) +{ + 1014678: defffd04 addi sp,sp,-12 + 101467c: dfc00215 stw ra,8(sp) + 1014680: df000115 stw fp,4(sp) + 1014684: df000104 addi fp,sp,4 + return ((alt_errno) ? alt_errno() : &errno); + 1014688: 008040b4 movhi r2,258 + 101468c: 108dd104 addi r2,r2,14148 + 1014690: 10800017 ldw r2,0(r2) + 1014694: 1005003a cmpeq r2,r2,zero + 1014698: 1000061e bne r2,zero,10146b4 + 101469c: 008040b4 movhi r2,258 + 10146a0: 108dd104 addi r2,r2,14148 + 10146a4: 10800017 ldw r2,0(r2) + 10146a8: 103ee83a callr r2 + 10146ac: e0bfff15 stw r2,-4(fp) + 10146b0: 00000306 br 10146c0 + 10146b4: 008040b4 movhi r2,258 + 10146b8: 10950804 addi r2,r2,21536 + 10146bc: e0bfff15 stw r2,-4(fp) + 10146c0: e0bfff17 ldw r2,-4(fp) +} + 10146c4: e037883a mov sp,fp + 10146c8: dfc00117 ldw ra,4(sp) + 10146cc: df000017 ldw fp,0(sp) + 10146d0: dec00204 addi sp,sp,8 + 10146d4: f800283a ret + +010146d8 : + * + * ALT_KILL is mapped onto the kill() system call in alt_syscall.h + */ + +int ALT_KILL (int pid, int sig) +{ + 10146d8: defffa04 addi sp,sp,-24 + 10146dc: dfc00515 stw ra,20(sp) + 10146e0: df000415 stw fp,16(sp) + 10146e4: df000404 addi fp,sp,16 + 10146e8: e13ffd15 stw r4,-12(fp) + 10146ec: e17ffe15 stw r5,-8(fp) + int status = 0; + 10146f0: e03ffc15 stw zero,-16(fp) + + if (pid <= 0) + 10146f4: e0bffd17 ldw r2,-12(fp) + 10146f8: 10800048 cmpgei r2,r2,1 + 10146fc: 1000301e bne r2,zero,10147c0 + { + switch (sig) + 1014700: e0bffe17 ldw r2,-8(fp) + 1014704: 10800828 cmpgeui r2,r2,32 + 1014708: 10002a1e bne r2,zero,10147b4 + 101470c: e0bffe17 ldw r2,-8(fp) + 1014710: 1085883a add r2,r2,r2 + 1014714: 1087883a add r3,r2,r2 + 1014718: 00804074 movhi r2,257 + 101471c: 1091cb04 addi r2,r2,18220 + 1014720: 1885883a add r2,r3,r2 + 1014724: 10800017 ldw r2,0(r2) + 1014728: 1000683a jmp r2 + 101472c: 010147d4 movui r4,1311 + 1014730: 010147b4 movhi r4,1310 + 1014734: 010147b4 movhi r4,1310 + 1014738: 010147ac andhi r4,zero,1310 + 101473c: 010147ac andhi r4,zero,1310 + 1014740: 010147ac andhi r4,zero,1310 + 1014744: 010147ac andhi r4,zero,1310 + 1014748: 010147b4 movhi r4,1310 + 101474c: 010147ac andhi r4,zero,1310 + 1014750: 010147ac andhi r4,zero,1310 + 1014754: 010147ac andhi r4,zero,1310 + 1014758: 010147ac andhi r4,zero,1310 + 101475c: 010147ac andhi r4,zero,1310 + 1014760: 010147ac andhi r4,zero,1310 + 1014764: 010147ac andhi r4,zero,1310 + 1014768: 010147ac andhi r4,zero,1310 + 101476c: 010147d4 movui r4,1311 + 1014770: 010147b4 movhi r4,1310 + 1014774: 010147b4 movhi r4,1310 + 1014778: 010147b4 movhi r4,1310 + 101477c: 010147d4 movui r4,1311 + 1014780: 010147b4 movhi r4,1310 + 1014784: 010147b4 movhi r4,1310 + 1014788: 010147ac andhi r4,zero,1310 + 101478c: 010147ac andhi r4,zero,1310 + 1014790: 010147ac andhi r4,zero,1310 + 1014794: 010147ac andhi r4,zero,1310 + 1014798: 010147ac andhi r4,zero,1310 + 101479c: 010147b4 movhi r4,1310 + 10147a0: 010147b4 movhi r4,1310 + 10147a4: 010147ac andhi r4,zero,1310 + 10147a8: 010147ac andhi r4,zero,1310 + * The Posix standard defines the default behaviour for all these signals + * as being eqivalent to a call to _exit(). No mechanism is provided to + * change this behaviour. + */ + + _exit(0); + 10147ac: 0009883a mov r4,zero + 10147b0: 10144380 call 1014438 <_exit> + break; + default: + + /* Tried to send an unsupported signal */ + + status = EINVAL; + 10147b4: 00800584 movi r2,22 + 10147b8: e0bffc15 stw r2,-16(fp) + 10147bc: 00000506 br 10147d4 + } + } + + else if (pid > 0) + 10147c0: e0bffd17 ldw r2,-12(fp) + 10147c4: 10800050 cmplti r2,r2,1 + 10147c8: 1000021e bne r2,zero,10147d4 + { + /* Attempted to signal a non-existant process */ + + status = ESRCH; + 10147cc: 008000c4 movi r2,3 + 10147d0: e0bffc15 stw r2,-16(fp) + } + + if (status) + 10147d4: e0bffc17 ldw r2,-16(fp) + 10147d8: 1005003a cmpeq r2,r2,zero + 10147dc: 1000071e bne r2,zero,10147fc + { + ALT_ERRNO = status; + 10147e0: 10148180 call 1014818 + 10147e4: 1007883a mov r3,r2 + 10147e8: e0bffc17 ldw r2,-16(fp) + 10147ec: 18800015 stw r2,0(r3) + return -1; + 10147f0: 00bfffc4 movi r2,-1 + 10147f4: e0bfff15 stw r2,-4(fp) + 10147f8: 00000106 br 1014800 + } + + return 0; + 10147fc: e03fff15 stw zero,-4(fp) + 1014800: e0bfff17 ldw r2,-4(fp) +} + 1014804: e037883a mov sp,fp + 1014808: dfc00117 ldw ra,4(sp) + 101480c: df000017 ldw fp,0(sp) + 1014810: dec00204 addi sp,sp,8 + 1014814: f800283a ret + +01014818 : +#undef errno + +extern int errno; + +static ALT_INLINE int* alt_get_errno(void) +{ + 1014818: defffd04 addi sp,sp,-12 + 101481c: dfc00215 stw ra,8(sp) + 1014820: df000115 stw fp,4(sp) + 1014824: df000104 addi fp,sp,4 + return ((alt_errno) ? alt_errno() : &errno); + 1014828: 008040b4 movhi r2,258 + 101482c: 108dd104 addi r2,r2,14148 + 1014830: 10800017 ldw r2,0(r2) + 1014834: 1005003a cmpeq r2,r2,zero + 1014838: 1000061e bne r2,zero,1014854 + 101483c: 008040b4 movhi r2,258 + 1014840: 108dd104 addi r2,r2,14148 + 1014844: 10800017 ldw r2,0(r2) + 1014848: 103ee83a callr r2 + 101484c: e0bfff15 stw r2,-4(fp) + 1014850: 00000306 br 1014860 + 1014854: 008040b4 movhi r2,258 + 1014858: 10950804 addi r2,r2,21536 + 101485c: e0bfff15 stw r2,-4(fp) + 1014860: e0bfff17 ldw r2,-4(fp) +} + 1014864: e037883a mov sp,fp + 1014868: dfc00117 ldw ra,4(sp) + 101486c: df000017 ldw fp,0(sp) + 1014870: dec00204 addi sp,sp,8 + 1014874: f800283a ret + +01014878 : + * there is no bootloader, so this application is responsible for loading to + * RAM any sections that are required. + */ + +void alt_load (void) +{ + 1014878: defffe04 addi sp,sp,-8 + 101487c: dfc00115 stw ra,4(sp) + 1014880: df000015 stw fp,0(sp) + 1014884: d839883a mov fp,sp + /* + * Copy the .rwdata section. + */ + + alt_load_section (&__flash_rwdata_start, + 1014888: 010040b4 movhi r4,258 + 101488c: 210df504 addi r4,r4,14292 + 1014890: 014040b4 movhi r5,258 + 1014894: 2946f004 addi r5,r5,7104 + 1014898: 018040b4 movhi r6,258 + 101489c: 318df504 addi r6,r6,14292 + 10148a0: 10148f80 call 10148f8 + + /* + * Copy the exception handler. + */ + + alt_load_section (&__flash_exceptions_start, + 10148a4: 01004034 movhi r4,256 + 10148a8: 21000804 addi r4,r4,32 + 10148ac: 01404034 movhi r5,256 + 10148b0: 29400804 addi r5,r5,32 + 10148b4: 01804034 movhi r6,256 + 10148b8: 31807004 addi r6,r6,448 + 10148bc: 10148f80 call 10148f8 + + /* + * Copy the .rodata section. + */ + + alt_load_section (&__flash_rodata_start, + 10148c0: 010040b4 movhi r4,258 + 10148c4: 21038004 addi r4,r4,3584 + 10148c8: 014040b4 movhi r5,258 + 10148cc: 29438004 addi r5,r5,3584 + 10148d0: 018040b4 movhi r6,258 + 10148d4: 3186f004 addi r6,r6,7104 + 10148d8: 10148f80 call 10148f8 + + /* + * Now ensure that the caches are in synch. + */ + + alt_dcache_flush_all(); + 10148dc: 101f5a00 call 101f5a0 + alt_icache_flush_all(); + 10148e0: 101f8540 call 101f854 +} + 10148e4: e037883a mov sp,fp + 10148e8: dfc00117 ldw ra,4(sp) + 10148ec: df000017 ldw fp,0(sp) + 10148f0: dec00204 addi sp,sp,8 + 10148f4: f800283a ret + +010148f8 : + */ + +static void ALT_INLINE alt_load_section (alt_u32* from, + alt_u32* to, + alt_u32* end) +{ + 10148f8: defffc04 addi sp,sp,-16 + 10148fc: df000315 stw fp,12(sp) + 1014900: df000304 addi fp,sp,12 + 1014904: e13ffd15 stw r4,-12(fp) + 1014908: e17ffe15 stw r5,-8(fp) + 101490c: e1bfff15 stw r6,-4(fp) + if (to != from) + 1014910: e0fffe17 ldw r3,-8(fp) + 1014914: e0bffd17 ldw r2,-12(fp) + 1014918: 18800e26 beq r3,r2,1014954 + { + while( to != end ) + 101491c: 00000a06 br 1014948 + { + *to++ = *from++; + 1014920: e0bffd17 ldw r2,-12(fp) + 1014924: 10c00017 ldw r3,0(r2) + 1014928: e0bffe17 ldw r2,-8(fp) + 101492c: 10c00015 stw r3,0(r2) + 1014930: e0bffe17 ldw r2,-8(fp) + 1014934: 10800104 addi r2,r2,4 + 1014938: e0bffe15 stw r2,-8(fp) + 101493c: e0bffd17 ldw r2,-12(fp) + 1014940: 10800104 addi r2,r2,4 + 1014944: e0bffd15 stw r2,-12(fp) + alt_u32* to, + alt_u32* end) +{ + if (to != from) + { + while( to != end ) + 1014948: e0fffe17 ldw r3,-8(fp) + 101494c: e0bfff17 ldw r2,-4(fp) + 1014950: 18bff31e bne r3,r2,1014920 + { + *to++ = *from++; + } + } +} + 1014954: e037883a mov sp,fp + 1014958: df000017 ldw fp,0(sp) + 101495c: dec00104 addi sp,sp,4 + 1014960: f800283a ret + +01014964 : + * ALT_LSEEK is mapped onto the lseek() system call in alt_syscall.h + * + */ + +off_t ALT_LSEEK (int file, off_t ptr, int dir) +{ + 1014964: defff804 addi sp,sp,-32 + 1014968: dfc00715 stw ra,28(sp) + 101496c: df000615 stw fp,24(sp) + 1014970: df000604 addi fp,sp,24 + 1014974: e13ffc15 stw r4,-16(fp) + 1014978: e17ffd15 stw r5,-12(fp) + 101497c: e1bffe15 stw r6,-8(fp) + alt_fd* fd; + off_t rc = 0; + 1014980: e03ffa15 stw zero,-24(fp) + * A common error case is that when the file descriptor was created, the call + * to open() failed resulting in a negative file descriptor. This is trapped + * below so that we don't try and process an invalid file descriptor. + */ + + fd = (file < 0) ? NULL : &alt_fd_list[file]; + 1014984: e0bffc17 ldw r2,-16(fp) + 1014988: 1004803a cmplt r2,r2,zero + 101498c: 1000081e bne r2,zero,10149b0 + 1014990: e0bffc17 ldw r2,-16(fp) + 1014994: 10800324 muli r2,r2,12 + 1014998: 1007883a mov r3,r2 + 101499c: 008040b4 movhi r2,258 + 10149a0: 1088ff04 addi r2,r2,9212 + 10149a4: 1887883a add r3,r3,r2 + 10149a8: e0ffff15 stw r3,-4(fp) + 10149ac: 00000106 br 10149b4 + 10149b0: e03fff15 stw zero,-4(fp) + 10149b4: e0bfff17 ldw r2,-4(fp) + 10149b8: e0bffb15 stw r2,-20(fp) + + if (fd) + 10149bc: e0bffb17 ldw r2,-20(fp) + 10149c0: 1005003a cmpeq r2,r2,zero + 10149c4: 1000111e bne r2,zero,1014a0c + /* + * If the device driver provides an implementation of the lseek() function, + * then call that to process the request. + */ + + if (fd->dev->lseek) + 10149c8: e0bffb17 ldw r2,-20(fp) + 10149cc: 10800017 ldw r2,0(r2) + 10149d0: 10800717 ldw r2,28(r2) + 10149d4: 1005003a cmpeq r2,r2,zero + 10149d8: 1000091e bne r2,zero,1014a00 + { + rc = fd->dev->lseek(fd, ptr, dir); + 10149dc: e0bffb17 ldw r2,-20(fp) + 10149e0: 10800017 ldw r2,0(r2) + 10149e4: 10800717 ldw r2,28(r2) + 10149e8: e13ffb17 ldw r4,-20(fp) + 10149ec: e17ffd17 ldw r5,-12(fp) + 10149f0: e1bffe17 ldw r6,-8(fp) + 10149f4: 103ee83a callr r2 + 10149f8: e0bffa15 stw r2,-24(fp) + 10149fc: 00000506 br 1014a14 + * Otherwise return an error. + */ + + else + { + rc = -ENOTSUP; + 1014a00: 00bfde84 movi r2,-134 + 1014a04: e0bffa15 stw r2,-24(fp) + 1014a08: 00000206 br 1014a14 + } + } + else + { + rc = -EBADFD; + 1014a0c: 00bfebc4 movi r2,-81 + 1014a10: e0bffa15 stw r2,-24(fp) + } + + if (rc < 0) + 1014a14: e0bffa17 ldw r2,-24(fp) + 1014a18: 1004403a cmpge r2,r2,zero + 1014a1c: 1000071e bne r2,zero,1014a3c + { + ALT_ERRNO = -rc; + 1014a20: 1014a540 call 1014a54 + 1014a24: 1007883a mov r3,r2 + 1014a28: e0bffa17 ldw r2,-24(fp) + 1014a2c: 0085c83a sub r2,zero,r2 + 1014a30: 18800015 stw r2,0(r3) + rc = -1; + 1014a34: 00bfffc4 movi r2,-1 + 1014a38: e0bffa15 stw r2,-24(fp) + } + + return rc; + 1014a3c: e0bffa17 ldw r2,-24(fp) +} + 1014a40: e037883a mov sp,fp + 1014a44: dfc00117 ldw ra,4(sp) + 1014a48: df000017 ldw fp,0(sp) + 1014a4c: dec00204 addi sp,sp,8 + 1014a50: f800283a ret + +01014a54 : +#undef errno + +extern int errno; + +static ALT_INLINE int* alt_get_errno(void) +{ + 1014a54: defffd04 addi sp,sp,-12 + 1014a58: dfc00215 stw ra,8(sp) + 1014a5c: df000115 stw fp,4(sp) + 1014a60: df000104 addi fp,sp,4 + return ((alt_errno) ? alt_errno() : &errno); + 1014a64: 008040b4 movhi r2,258 + 1014a68: 108dd104 addi r2,r2,14148 + 1014a6c: 10800017 ldw r2,0(r2) + 1014a70: 1005003a cmpeq r2,r2,zero + 1014a74: 1000061e bne r2,zero,1014a90 + 1014a78: 008040b4 movhi r2,258 + 1014a7c: 108dd104 addi r2,r2,14148 + 1014a80: 10800017 ldw r2,0(r2) + 1014a84: 103ee83a callr r2 + 1014a88: e0bfff15 stw r2,-4(fp) + 1014a8c: 00000306 br 1014a9c + 1014a90: 008040b4 movhi r2,258 + 1014a94: 10950804 addi r2,r2,21536 + 1014a98: e0bfff15 stw r2,-4(fp) + 1014a9c: e0bfff17 ldw r2,-4(fp) +} + 1014aa0: e037883a mov sp,fp + 1014aa4: dfc00117 ldw ra,4(sp) + 1014aa8: df000017 ldw fp,0(sp) + 1014aac: dec00204 addi sp,sp,8 + 1014ab0: f800283a ret + +01014ab4 : + * devices/filesystems/components in the system; and call the entry point for + * the users application, i.e. main(). + */ + +void alt_main (void) +{ + 1014ab4: defffb04 addi sp,sp,-20 + 1014ab8: dfc00415 stw ra,16(sp) + 1014abc: df000315 stw fp,12(sp) + 1014ac0: df000304 addi fp,sp,12 +#endif + + /* ALT LOG - please see HAL/sys/alt_log_printf.h for details */ + ALT_LOG_PRINT_BOOT("[alt_main.c] Entering alt_main, calling alt_irq_init.\r\n"); + /* Initialize the interrupt controller. */ + alt_irq_init (NULL); + 1014ac4: 0009883a mov r4,zero + 1014ac8: 101d5440 call 101d544 + + /* Initialize the operating system */ + ALT_LOG_PRINT_BOOT("[alt_main.c] Done alt_irq_init, calling alt_os_init.\r\n"); + ALT_OS_INIT(); + 1014acc: 1015ba00 call 1015ba0 + 1014ad0: 01000044 movi r4,1 + 1014ad4: 101aa640 call 101aa64 + 1014ad8: 1007883a mov r3,r2 + 1014adc: 008040b4 movhi r2,258 + 1014ae0: 10951104 addi r2,r2,21572 + 1014ae4: 10c00015 stw r3,0(r2) + 1014ae8: 01000044 movi r4,1 + 1014aec: 101aa640 call 101aa64 + 1014af0: 1007883a mov r3,r2 + 1014af4: 008040b4 movhi r2,258 + 1014af8: 10951304 addi r2,r2,21580 + 1014afc: 10c00015 stw r3,0(r2) + 1014b00: 008040b4 movhi r2,258 + 1014b04: 10950c04 addi r2,r2,21552 + 1014b08: e0bffd15 stw r2,-12(fp) + 1014b0c: 00800044 movi r2,1 + 1014b10: e0bffe0d sth r2,-8(fp) + */ + +static ALT_INLINE int ALT_ALWAYS_INLINE alt_sem_create (OS_EVENT** sem, + INT16U value) +{ + *sem = OSSemCreate (value); + 1014b14: e13ffe0b ldhu r4,-8(fp) + 1014b18: 101aa640 call 101aa64 + 1014b1c: 1007883a mov r3,r2 + 1014b20: e0bffd17 ldw r2,-12(fp) + 1014b24: 10c00015 stw r3,0(r2) + ALT_LOG_PRINT_BOOT("[alt_main.c] Done OS Init, calling alt_sem_create.\r\n"); + ALT_SEM_CREATE (&alt_fd_list_lock, 1); + + /* Initialize the device drivers/software components. */ + ALT_LOG_PRINT_BOOT("[alt_main.c] Calling alt_sys_init.\r\n"); + alt_sys_init(); + 1014b28: 101d5780 call 101d578 + * devices be present (not equal to /dev/null) and if direct drivers + * aren't being used. + */ + + ALT_LOG_PRINT_BOOT("[alt_main.c] Redirecting IO.\r\n"); + alt_io_redirect(ALT_STDOUT, ALT_STDIN, ALT_STDERR); + 1014b2c: 010040b4 movhi r4,258 + 1014b30: 21069504 addi r4,r4,6740 + 1014b34: 014040b4 movhi r5,258 + 1014b38: 29469504 addi r5,r5,6740 + 1014b3c: 018040b4 movhi r6,258 + 1014b40: 31869504 addi r6,r6,6740 + 1014b44: 101f9480 call 101f948 + /* + * Call the C++ constructors + */ + + ALT_LOG_PRINT_BOOT("[alt_main.c] Calling C++ constructors.\r\n"); + _do_ctors (); + 1014b48: 101f6f80 call 101f6f8 <_do_ctors> + * redefined as _exit()). This is in the interest of reducing code footprint, + * in that the atexit() overhead is removed when it's not needed. + */ + + ALT_LOG_PRINT_BOOT("[alt_main.c] Calling atexit.\r\n"); + atexit (_do_dtors); + 1014b4c: 010040b4 movhi r4,258 + 1014b50: 213dd704 addi r4,r4,-2212 + 1014b54: 10207980 call 1020798 + ALT_LOG_PRINT_BOOT("[alt_main.c] Calling main.\r\n"); + +#ifdef ALT_NO_EXIT + main (alt_argc, alt_argv, alt_envp); +#else + result = main (alt_argc, alt_argv, alt_envp); + 1014b58: d1275417 ldw r4,-25264(gp) + 1014b5c: d1675517 ldw r5,-25260(gp) + 1014b60: d1a75617 ldw r6,-25256(gp) + 1014b64: 1000a940 call 1000a94
+ 1014b68: e0bfff15 stw r2,-4(fp) + close(STDOUT_FILENO); + 1014b6c: 01000044 movi r4,1 + 1014b70: 10142700 call 1014270 + exit (result); + 1014b74: e13fff17 ldw r4,-4(fp) + 1014b78: 10207ac0 call 10207ac + +01014b7c : +} + +#else /* !ALT_USE_DIRECT_DRIVERS */ + +int ALT_READ (int file, void *ptr, size_t len) +{ + 1014b7c: defff704 addi sp,sp,-36 + 1014b80: dfc00815 stw ra,32(sp) + 1014b84: df000715 stw fp,28(sp) + 1014b88: df000704 addi fp,sp,28 + 1014b8c: e13ffb15 stw r4,-20(fp) + 1014b90: e17ffc15 stw r5,-16(fp) + 1014b94: e1bffd15 stw r6,-12(fp) + * A common error case is that when the file descriptor was created, the call + * to open() failed resulting in a negative file descriptor. This is trapped + * below so that we don't try and process an invalid file descriptor. + */ + + fd = (file < 0) ? NULL : &alt_fd_list[file]; + 1014b98: e0bffb17 ldw r2,-20(fp) + 1014b9c: 1004803a cmplt r2,r2,zero + 1014ba0: 1000081e bne r2,zero,1014bc4 + 1014ba4: e0bffb17 ldw r2,-20(fp) + 1014ba8: 10800324 muli r2,r2,12 + 1014bac: 1007883a mov r3,r2 + 1014bb0: 008040b4 movhi r2,258 + 1014bb4: 1088ff04 addi r2,r2,9212 + 1014bb8: 1887883a add r3,r3,r2 + 1014bbc: e0ffff15 stw r3,-4(fp) + 1014bc0: 00000106 br 1014bc8 + 1014bc4: e03fff15 stw zero,-4(fp) + 1014bc8: e0bfff17 ldw r2,-4(fp) + 1014bcc: e0bffa15 stw r2,-24(fp) + + if (fd) + 1014bd0: e0bffa17 ldw r2,-24(fp) + 1014bd4: 1005003a cmpeq r2,r2,zero + 1014bd8: 1000241e bne r2,zero,1014c6c + * If the file has not been opened with read access, or if the driver does + * not provide an implementation of read(), generate an error. Otherwise + * call the drivers read() function to process the request. + */ + + if (((fd->fd_flags & O_ACCMODE) != O_WRONLY) && + 1014bdc: e0bffa17 ldw r2,-24(fp) + 1014be0: 10800217 ldw r2,8(r2) + 1014be4: 108000cc andi r2,r2,3 + 1014be8: 10800060 cmpeqi r2,r2,1 + 1014bec: 10001a1e bne r2,zero,1014c58 + 1014bf0: e0bffa17 ldw r2,-24(fp) + 1014bf4: 10800017 ldw r2,0(r2) + 1014bf8: 10800517 ldw r2,20(r2) + 1014bfc: 1005003a cmpeq r2,r2,zero + 1014c00: 1000151e bne r2,zero,1014c58 + (fd->dev->read)) + { + if ((rval = fd->dev->read(fd, ptr, len)) < 0) + 1014c04: e0bffa17 ldw r2,-24(fp) + 1014c08: 10800017 ldw r2,0(r2) + 1014c0c: 10800517 ldw r2,20(r2) + 1014c10: e17ffc17 ldw r5,-16(fp) + 1014c14: e1bffd17 ldw r6,-12(fp) + 1014c18: e13ffa17 ldw r4,-24(fp) + 1014c1c: 103ee83a callr r2 + 1014c20: e0bff915 stw r2,-28(fp) + 1014c24: e0bff917 ldw r2,-28(fp) + 1014c28: 1004403a cmpge r2,r2,zero + 1014c2c: 1000071e bne r2,zero,1014c4c + { + ALT_ERRNO = -rval; + 1014c30: 1014c9c0 call 1014c9c + 1014c34: e0fff917 ldw r3,-28(fp) + 1014c38: 00c7c83a sub r3,zero,r3 + 1014c3c: 10c00015 stw r3,0(r2) + return -1; + 1014c40: 00bfffc4 movi r2,-1 + 1014c44: e0bffe15 stw r2,-8(fp) + 1014c48: 00000e06 br 1014c84 + } + return rval; + 1014c4c: e0bff917 ldw r2,-28(fp) + 1014c50: e0bffe15 stw r2,-8(fp) + 1014c54: 00000b06 br 1014c84 + } + else + { + ALT_ERRNO = EACCES; + 1014c58: 1014c9c0 call 1014c9c + 1014c5c: 1007883a mov r3,r2 + 1014c60: 00800344 movi r2,13 + 1014c64: 18800015 stw r2,0(r3) + 1014c68: 00000406 br 1014c7c + } + } + else + { + ALT_ERRNO = EBADFD; + 1014c6c: 1014c9c0 call 1014c9c + 1014c70: 1007883a mov r3,r2 + 1014c74: 00801444 movi r2,81 + 1014c78: 18800015 stw r2,0(r3) + } + return -1; + 1014c7c: 00bfffc4 movi r2,-1 + 1014c80: e0bffe15 stw r2,-8(fp) + 1014c84: e0bffe17 ldw r2,-8(fp) +} + 1014c88: e037883a mov sp,fp + 1014c8c: dfc00117 ldw ra,4(sp) + 1014c90: df000017 ldw fp,0(sp) + 1014c94: dec00204 addi sp,sp,8 + 1014c98: f800283a ret + +01014c9c : +#undef errno + +extern int errno; + +static ALT_INLINE int* alt_get_errno(void) +{ + 1014c9c: defffd04 addi sp,sp,-12 + 1014ca0: dfc00215 stw ra,8(sp) + 1014ca4: df000115 stw fp,4(sp) + 1014ca8: df000104 addi fp,sp,4 + return ((alt_errno) ? alt_errno() : &errno); + 1014cac: 008040b4 movhi r2,258 + 1014cb0: 108dd104 addi r2,r2,14148 + 1014cb4: 10800017 ldw r2,0(r2) + 1014cb8: 1005003a cmpeq r2,r2,zero + 1014cbc: 1000061e bne r2,zero,1014cd8 + 1014cc0: 008040b4 movhi r2,258 + 1014cc4: 108dd104 addi r2,r2,14148 + 1014cc8: 10800017 ldw r2,0(r2) + 1014ccc: 103ee83a callr r2 + 1014cd0: e0bfff15 stw r2,-4(fp) + 1014cd4: 00000306 br 1014ce4 + 1014cd8: 008040b4 movhi r2,258 + 1014cdc: 10950804 addi r2,r2,21536 + 1014ce0: e0bfff15 stw r2,-4(fp) + 1014ce4: e0bfff17 ldw r2,-4(fp) +} + 1014ce8: e037883a mov sp,fp + 1014cec: dfc00117 ldw ra,4(sp) + 1014cf0: df000017 ldw fp,0(sp) + 1014cf4: dec00204 addi sp,sp,8 + 1014cf8: f800283a ret + +01014cfc : + * File descriptors correcponding to standard in, standard out and standard + * error cannont be released backed to the pool. They are always reserved. + */ + +void alt_release_fd (int fd) +{ + 1014cfc: defffe04 addi sp,sp,-8 + 1014d00: df000115 stw fp,4(sp) + 1014d04: df000104 addi fp,sp,4 + 1014d08: e13fff15 stw r4,-4(fp) + if (fd > 2) + 1014d0c: e0bfff17 ldw r2,-4(fp) + 1014d10: 108000d0 cmplti r2,r2,3 + 1014d14: 10000d1e bne r2,zero,1014d4c + { + alt_fd_list[fd].fd_flags = 0; + 1014d18: e0bfff17 ldw r2,-4(fp) + 1014d1c: 00c040b4 movhi r3,258 + 1014d20: 18c8ff04 addi r3,r3,9212 + 1014d24: 10800324 muli r2,r2,12 + 1014d28: 10c5883a add r2,r2,r3 + 1014d2c: 10800204 addi r2,r2,8 + 1014d30: 10000015 stw zero,0(r2) + alt_fd_list[fd].dev = 0; + 1014d34: e0bfff17 ldw r2,-4(fp) + 1014d38: 00c040b4 movhi r3,258 + 1014d3c: 18c8ff04 addi r3,r3,9212 + 1014d40: 10800324 muli r2,r2,12 + 1014d44: 10c5883a add r2,r2,r3 + 1014d48: 10000015 stw zero,0(r2) + } +} + 1014d4c: e037883a mov sp,fp + 1014d50: df000017 ldw fp,0(sp) + 1014d54: dec00104 addi sp,sp,4 + 1014d58: f800283a ret + +01014d5c : +#endif + +caddr_t ALT_SBRK (int incr) __attribute__ ((no_instrument_function )); + +caddr_t ALT_SBRK (int incr) +{ + 1014d5c: defff804 addi sp,sp,-32 + 1014d60: df000715 stw fp,28(sp) + 1014d64: df000704 addi fp,sp,28 + 1014d68: e13ffe15 stw r4,-8(fp) +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1014d6c: 0005303a rdctl r2,status + 1014d70: e0bffb15 stw r2,-20(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1014d74: e0fffb17 ldw r3,-20(fp) + 1014d78: 00bfff84 movi r2,-2 + 1014d7c: 1884703a and r2,r3,r2 + 1014d80: 1001703a wrctl status,r2 + + return context; + 1014d84: e0bffb17 ldw r2,-20(fp) + alt_irq_context context; + char *prev_heap_end; + + context = alt_irq_disable_all(); + 1014d88: e0bffd15 stw r2,-12(fp) + + /* Always return data aligned on a word boundary */ + heap_end = (char *)(((unsigned int)heap_end + 3) & ~3); + 1014d8c: d0a01917 ldw r2,-32668(gp) + 1014d90: 10c000c4 addi r3,r2,3 + 1014d94: 00bfff04 movi r2,-4 + 1014d98: 1884703a and r2,r3,r2 + 1014d9c: d0a01915 stw r2,-32668(gp) + if (((heap_end + incr) - __alt_heap_start) > ALT_MAX_HEAP_BYTES) { + alt_irq_enable_all(context); + return (caddr_t)-1; + } +#else + if ((heap_end + incr) > __alt_heap_limit) { + 1014da0: d0e01917 ldw r3,-32668(gp) + 1014da4: e0bffe17 ldw r2,-8(fp) + 1014da8: 1887883a add r3,r3,r2 + 1014dac: 00808034 movhi r2,512 + 1014db0: 10800004 addi r2,r2,0 + 1014db4: 10c0072e bgeu r2,r3,1014dd4 + 1014db8: e0bffd17 ldw r2,-12(fp) + 1014dbc: e0bffa15 stw r2,-24(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1014dc0: e0bffa17 ldw r2,-24(fp) + 1014dc4: 1001703a wrctl status,r2 + alt_irq_enable_all(context); + return (caddr_t)-1; + 1014dc8: 00bfffc4 movi r2,-1 + 1014dcc: e0bfff15 stw r2,-4(fp) + 1014dd0: 00000c06 br 1014e04 + } +#endif + + prev_heap_end = heap_end; + 1014dd4: d0a01917 ldw r2,-32668(gp) + 1014dd8: e0bffc15 stw r2,-16(fp) + heap_end += incr; + 1014ddc: d0e01917 ldw r3,-32668(gp) + 1014de0: e0bffe17 ldw r2,-8(fp) + 1014de4: 1885883a add r2,r3,r2 + 1014de8: d0a01915 stw r2,-32668(gp) + 1014dec: e0bffd17 ldw r2,-12(fp) + 1014df0: e0bff915 stw r2,-28(fp) + 1014df4: e0bff917 ldw r2,-28(fp) + 1014df8: 1001703a wrctl status,r2 + +#endif + + alt_irq_enable_all(context); + + return (caddr_t) prev_heap_end; + 1014dfc: e0bffc17 ldw r2,-16(fp) + 1014e00: e0bfff15 stw r2,-4(fp) + 1014e04: e0bfff17 ldw r2,-4(fp) +} + 1014e08: e037883a mov sp,fp + 1014e0c: df000017 ldw fp,0(sp) + 1014e10: dec00104 addi sp,sp,4 + 1014e14: f800283a ret + +01014e18 : +} + +#else /* !ALT_USE_DIRECT_DRIVERS */ + +int ALT_WRITE (int file, const void *ptr, size_t len) +{ + 1014e18: defff704 addi sp,sp,-36 + 1014e1c: dfc00815 stw ra,32(sp) + 1014e20: df000715 stw fp,28(sp) + 1014e24: df000704 addi fp,sp,28 + 1014e28: e13ffb15 stw r4,-20(fp) + 1014e2c: e17ffc15 stw r5,-16(fp) + 1014e30: e1bffd15 stw r6,-12(fp) + * A common error case is that when the file descriptor was created, the call + * to open() failed resulting in a negative file descriptor. This is trapped + * below so that we don't try and process an invalid file descriptor. + */ + + fd = (file < 0) ? NULL : &alt_fd_list[file]; + 1014e34: e0bffb17 ldw r2,-20(fp) + 1014e38: 1004803a cmplt r2,r2,zero + 1014e3c: 1000081e bne r2,zero,1014e60 + 1014e40: e0bffb17 ldw r2,-20(fp) + 1014e44: 10800324 muli r2,r2,12 + 1014e48: 1007883a mov r3,r2 + 1014e4c: 008040b4 movhi r2,258 + 1014e50: 1088ff04 addi r2,r2,9212 + 1014e54: 1887883a add r3,r3,r2 + 1014e58: e0ffff15 stw r3,-4(fp) + 1014e5c: 00000106 br 1014e64 + 1014e60: e03fff15 stw zero,-4(fp) + 1014e64: e0bfff17 ldw r2,-4(fp) + 1014e68: e0bffa15 stw r2,-24(fp) + + if (fd) + 1014e6c: e0bffa17 ldw r2,-24(fp) + 1014e70: 1005003a cmpeq r2,r2,zero + 1014e74: 1000241e bne r2,zero,1014f08 + * If the file has not been opened with write access, or if the driver does + * not provide an implementation of write(), generate an error. Otherwise + * call the drivers write() function to process the request. + */ + + if (((fd->fd_flags & O_ACCMODE) != O_RDONLY) && fd->dev->write) + 1014e78: e0bffa17 ldw r2,-24(fp) + 1014e7c: 10800217 ldw r2,8(r2) + 1014e80: 108000cc andi r2,r2,3 + 1014e84: 1005003a cmpeq r2,r2,zero + 1014e88: 10001a1e bne r2,zero,1014ef4 + 1014e8c: e0bffa17 ldw r2,-24(fp) + 1014e90: 10800017 ldw r2,0(r2) + 1014e94: 10800617 ldw r2,24(r2) + 1014e98: 1005003a cmpeq r2,r2,zero + 1014e9c: 1000151e bne r2,zero,1014ef4 + { + + /* ALT_LOG - see altera_hal/HAL/inc/sys/alt_log_printf.h */ + ALT_LOG_WRITE_FUNCTION(ptr,len); + + if ((rval = fd->dev->write(fd, ptr, len)) < 0) + 1014ea0: e0bffa17 ldw r2,-24(fp) + 1014ea4: 10800017 ldw r2,0(r2) + 1014ea8: 10800617 ldw r2,24(r2) + 1014eac: e17ffc17 ldw r5,-16(fp) + 1014eb0: e1bffd17 ldw r6,-12(fp) + 1014eb4: e13ffa17 ldw r4,-24(fp) + 1014eb8: 103ee83a callr r2 + 1014ebc: e0bff915 stw r2,-28(fp) + 1014ec0: e0bff917 ldw r2,-28(fp) + 1014ec4: 1004403a cmpge r2,r2,zero + 1014ec8: 1000071e bne r2,zero,1014ee8 + { + ALT_ERRNO = -rval; + 1014ecc: 1014f380 call 1014f38 + 1014ed0: e0fff917 ldw r3,-28(fp) + 1014ed4: 00c7c83a sub r3,zero,r3 + 1014ed8: 10c00015 stw r3,0(r2) + return -1; + 1014edc: 00bfffc4 movi r2,-1 + 1014ee0: e0bffe15 stw r2,-8(fp) + 1014ee4: 00000e06 br 1014f20 + } + return rval; + 1014ee8: e0bff917 ldw r2,-28(fp) + 1014eec: e0bffe15 stw r2,-8(fp) + 1014ef0: 00000b06 br 1014f20 + } + else + { + ALT_ERRNO = EACCES; + 1014ef4: 1014f380 call 1014f38 + 1014ef8: 1007883a mov r3,r2 + 1014efc: 00800344 movi r2,13 + 1014f00: 18800015 stw r2,0(r3) + 1014f04: 00000406 br 1014f18 + } + } + else + { + ALT_ERRNO = EBADFD; + 1014f08: 1014f380 call 1014f38 + 1014f0c: 1007883a mov r3,r2 + 1014f10: 00801444 movi r2,81 + 1014f14: 18800015 stw r2,0(r3) + } + return -1; + 1014f18: 00bfffc4 movi r2,-1 + 1014f1c: e0bffe15 stw r2,-8(fp) + 1014f20: e0bffe17 ldw r2,-8(fp) +} + 1014f24: e037883a mov sp,fp + 1014f28: dfc00117 ldw ra,4(sp) + 1014f2c: df000017 ldw fp,0(sp) + 1014f30: dec00204 addi sp,sp,8 + 1014f34: f800283a ret + +01014f38 : +#undef errno + +extern int errno; + +static ALT_INLINE int* alt_get_errno(void) +{ + 1014f38: defffd04 addi sp,sp,-12 + 1014f3c: dfc00215 stw ra,8(sp) + 1014f40: df000115 stw fp,4(sp) + 1014f44: df000104 addi fp,sp,4 + return ((alt_errno) ? alt_errno() : &errno); + 1014f48: 008040b4 movhi r2,258 + 1014f4c: 108dd104 addi r2,r2,14148 + 1014f50: 10800017 ldw r2,0(r2) + 1014f54: 1005003a cmpeq r2,r2,zero + 1014f58: 1000061e bne r2,zero,1014f74 + 1014f5c: 008040b4 movhi r2,258 + 1014f60: 108dd104 addi r2,r2,14148 + 1014f64: 10800017 ldw r2,0(r2) + 1014f68: 103ee83a callr r2 + 1014f6c: e0bfff15 stw r2,-4(fp) + 1014f70: 00000306 br 1014f80 + 1014f74: 008040b4 movhi r2,258 + 1014f78: 10950804 addi r2,r2,21536 + 1014f7c: e0bfff15 stw r2,-4(fp) + 1014f80: e0bfff17 ldw r2,-4(fp) +} + 1014f84: e037883a mov sp,fp + 1014f88: dfc00117 ldw ra,4(sp) + 1014f8c: df000017 ldw fp,0(sp) + 1014f90: dec00204 addi sp,sp,8 + 1014f94: f800283a ret + +01014f98 <__env_lock>: +/* + * + */ + +void __env_lock ( struct _reent *_r ) +{ + 1014f98: deffdf04 addi sp,sp,-132 + 1014f9c: dfc02015 stw ra,128(sp) + 1014fa0: df001f15 stw fp,124(sp) + 1014fa4: df001f04 addi fp,sp,124 + 1014fa8: e13fff15 stw r4,-4(fp) + INT8U err; + int id; + + /* use our priority as a task id */ + + err = OSTaskQuery( OS_PRIO_SELF, &tcb ); + 1014fac: e17fe204 addi r5,fp,-120 + 1014fb0: 01003fc4 movi r4,255 + 1014fb4: 101cdec0 call 101cdec + 1014fb8: e0bffe85 stb r2,-6(fp) + if (err != OS_NO_ERR) + 1014fbc: e0bffe83 ldbu r2,-6(fp) + 1014fc0: 10803fcc andi r2,r2,255 + 1014fc4: 1004c03a cmpne r2,r2,zero + 1014fc8: 1000191e bne r2,zero,1015030 <__env_lock+0x98> + return; + + id = tcb.OSTCBPrio; + 1014fcc: e0bfee83 ldbu r2,-70(fp) + 1014fd0: 10803fcc andi r2,r2,255 + 1014fd4: e0bfe115 stw r2,-124(fp) + + /* see if we own the environment already */ + + OSSemQuery( alt_envsem, &semdata ); + 1014fd8: d1275817 ldw r4,-25248(gp) + 1014fdc: e17ffd04 addi r5,fp,-12 + 1014fe0: 101b3380 call 101b338 + if( semdata.OSEventGrp && id == lockid ) + 1014fe4: e0bffe43 ldbu r2,-7(fp) + 1014fe8: 10803fcc andi r2,r2,255 + 1014fec: 1005003a cmpeq r2,r2,zero + 1014ff0: 1000071e bne r2,zero,1015010 <__env_lock+0x78> + 1014ff4: d0e01a17 ldw r3,-32664(gp) + 1014ff8: e0bfe117 ldw r2,-124(fp) + 1014ffc: 10c0041e bne r2,r3,1015010 <__env_lock+0x78> + { + /* we do; just count the recursion */ + + locks++; + 1015000: d0a75717 ldw r2,-25252(gp) + 1015004: 10800044 addi r2,r2,1 + 1015008: d0a75715 stw r2,-25252(gp) + id = tcb.OSTCBPrio; + + /* see if we own the environment already */ + + OSSemQuery( alt_envsem, &semdata ); + if( semdata.OSEventGrp && id == lockid ) + 101500c: 00000806 br 1015030 <__env_lock+0x98> + } + else + { + /* wait on the other task to yield, then claim ownership */ + + OSSemPend( alt_envsem, 0, &err ); + 1015010: d1275817 ldw r4,-25248(gp) + 1015014: e1bffe84 addi r6,fp,-6 + 1015018: 000b883a mov r5,zero + 101501c: 101ae180 call 101ae18 + locks = 1; + 1015020: 00800044 movi r2,1 + 1015024: d0a75715 stw r2,-25252(gp) + lockid = id; + 1015028: e0bfe117 ldw r2,-124(fp) + 101502c: d0a01a15 stw r2,-32664(gp) + } + +#endif /* OS_THREAD_SAFE_NEWLIB */ + return; +} + 1015030: e037883a mov sp,fp + 1015034: dfc00117 ldw ra,4(sp) + 1015038: df000017 ldw fp,0(sp) + 101503c: dec00204 addi sp,sp,8 + 1015040: f800283a ret + +01015044 <__env_unlock>: +/* + * + */ + +void __env_unlock ( struct _reent *_r ) +{ + 1015044: defffd04 addi sp,sp,-12 + 1015048: dfc00215 stw ra,8(sp) + 101504c: df000115 stw fp,4(sp) + 1015050: df000104 addi fp,sp,4 + 1015054: e13fff15 stw r4,-4(fp) +#if OS_THREAD_SAFE_NEWLIB + if (locks == 0) + 1015058: d0a75717 ldw r2,-25252(gp) + 101505c: 1005003a cmpeq r2,r2,zero + 1015060: 10000a1e bne r2,zero,101508c <__env_unlock+0x48> + /* + * release the environment once the number of locks == the number + * of unlocks + */ + + if( (--locks) == 0 ) + 1015064: d0a75717 ldw r2,-25252(gp) + 1015068: 10bfffc4 addi r2,r2,-1 + 101506c: d0a75715 stw r2,-25252(gp) + 1015070: d0a75717 ldw r2,-25252(gp) + 1015074: 1004c03a cmpne r2,r2,zero + 1015078: 1000041e bne r2,zero,101508c <__env_unlock+0x48> + { + lockid = -1; + 101507c: 00bfffc4 movi r2,-1 + 1015080: d0a01a15 stw r2,-32664(gp) + OSSemPost( alt_envsem ); + 1015084: d1275817 ldw r4,-25248(gp) + 1015088: 101b2100 call 101b210 + } +#endif /* OS_THREAD_SAFE_NEWLIB */ +} + 101508c: e037883a mov sp,fp + 1015090: dfc00117 ldw ra,4(sp) + 1015094: df000017 ldw fp,0(sp) + 1015098: dec00204 addi sp,sp,8 + 101509c: f800283a ret + +010150a0 <__malloc_lock>: +/* + * + */ + +void __malloc_lock ( struct _reent *_r ) +{ + 10150a0: deffdb04 addi sp,sp,-148 + 10150a4: dfc02415 stw ra,144(sp) + 10150a8: df002315 stw fp,140(sp) + 10150ac: df002304 addi fp,sp,140 + 10150b0: e13fff15 stw r4,-4(fp) + OS_TCB tcb; + OS_SEM_DATA semdata; + INT8U err; + int id; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 10150b4: e03fe015 stw zero,-128(fp) +#endif + + if (OSRunning != OS_TRUE) + 10150b8: 008040b4 movhi r2,258 + 10150bc: 10951444 addi r2,r2,21585 + 10150c0: 10800003 ldbu r2,0(r2) + 10150c4: 10803fcc andi r2,r2,255 + 10150c8: 10800058 cmpnei r2,r2,1 + 10150cc: 1000311e bne r2,zero,1015194 <__malloc_lock+0xf4> + return; + + /* use our priority as a task id */ + + err = OSTaskQuery( OS_PRIO_SELF, &tcb ); + 10150d0: e17fe204 addi r5,fp,-120 + 10150d4: 01003fc4 movi r4,255 + 10150d8: 101cdec0 call 101cdec + 10150dc: e0bffe85 stb r2,-6(fp) + if (err != OS_NO_ERR) + 10150e0: e0bffe83 ldbu r2,-6(fp) + 10150e4: 10803fcc andi r2,r2,255 + 10150e8: 1004c03a cmpne r2,r2,zero + 10150ec: 1000291e bne r2,zero,1015194 <__malloc_lock+0xf4> + return; + + id = tcb.OSTCBPrio; + 10150f0: e0bfee83 ldbu r2,-70(fp) + 10150f4: 10803fcc andi r2,r2,255 + 10150f8: e0bfe115 stw r2,-124(fp) + + /* see if we own the heap already */ + + OSSemQuery( alt_heapsem, &semdata ); + 10150fc: d1275a17 ldw r4,-25240(gp) + 1015100: e17ffd04 addi r5,fp,-12 + 1015104: 101b3380 call 101b338 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1015108: 0005303a rdctl r2,status + 101510c: e0bfdf15 stw r2,-132(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1015110: e0ffdf17 ldw r3,-132(fp) + 1015114: 00bfff84 movi r2,-2 + 1015118: 1884703a and r2,r3,r2 + 101511c: 1001703a wrctl status,r2 + + return context; + 1015120: e0bfdf17 ldw r2,-132(fp) + + OS_ENTER_CRITICAL(); + 1015124: e0bfe015 stw r2,-128(fp) + + if( !semdata.OSCnt && id == lockid ) + 1015128: e0bffd0b ldhu r2,-12(fp) + 101512c: 10bfffcc andi r2,r2,65535 + 1015130: 1004c03a cmpne r2,r2,zero + 1015134: 10000b1e bne r2,zero,1015164 <__malloc_lock+0xc4> + 1015138: d0e01b17 ldw r3,-32660(gp) + 101513c: e0bfe117 ldw r2,-124(fp) + 1015140: 10c0081e bne r2,r3,1015164 <__malloc_lock+0xc4> + { + /* we do; just count the recursion */ + locks++; + 1015144: d0a75917 ldw r2,-25244(gp) + 1015148: 10800044 addi r2,r2,1 + 101514c: d0a75915 stw r2,-25244(gp) + 1015150: e0bfe017 ldw r2,-128(fp) + 1015154: e0bfde15 stw r2,-136(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1015158: e0bfde17 ldw r2,-136(fp) + 101515c: 1001703a wrctl status,r2 + + OSSemQuery( alt_heapsem, &semdata ); + + OS_ENTER_CRITICAL(); + + if( !semdata.OSCnt && id == lockid ) + 1015160: 00000c06 br 1015194 <__malloc_lock+0xf4> + 1015164: e0bfe017 ldw r2,-128(fp) + 1015168: e0bfdd15 stw r2,-140(fp) + 101516c: e0bfdd17 ldw r2,-140(fp) + 1015170: 1001703a wrctl status,r2 + else + { + /* wait on the other task to yield the heap, then claim ownership of it */ + OS_EXIT_CRITICAL(); + + OSSemPend( alt_heapsem, 0, &err ); + 1015174: d1275a17 ldw r4,-25240(gp) + 1015178: e1bffe84 addi r6,fp,-6 + 101517c: 000b883a mov r5,zero + 1015180: 101ae180 call 101ae18 + locks = 1; + 1015184: 00800044 movi r2,1 + 1015188: d0a75915 stw r2,-25244(gp) + lockid = id; + 101518c: e0bfe117 ldw r2,-124(fp) + 1015190: d0a01b15 stw r2,-32660(gp) + } + +#endif /* OS_THREAD_SAFE_NEWLIB */ + return; +} + 1015194: e037883a mov sp,fp + 1015198: dfc00117 ldw ra,4(sp) + 101519c: df000017 ldw fp,0(sp) + 10151a0: dec00204 addi sp,sp,8 + 10151a4: f800283a ret + +010151a8 <__malloc_unlock>: +/* + * + */ + +void __malloc_unlock ( struct _reent *_r ) +{ + 10151a8: defff804 addi sp,sp,-32 + 10151ac: dfc00715 stw ra,28(sp) + 10151b0: df000615 stw fp,24(sp) + 10151b4: df000604 addi fp,sp,24 + 10151b8: e13fff15 stw r4,-4(fp) +#if OS_THREAD_SAFE_NEWLIB + +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 10151bc: e03ffe15 stw zero,-8(fp) +#endif + + if (OSRunning != OS_TRUE) + 10151c0: 008040b4 movhi r2,258 + 10151c4: 10951444 addi r2,r2,21585 + 10151c8: 10800003 ldbu r2,0(r2) + 10151cc: 10803fcc andi r2,r2,255 + 10151d0: 10800058 cmpnei r2,r2,1 + 10151d4: 1000231e bne r2,zero,1015264 <__malloc_unlock+0xbc> +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 10151d8: 0005303a rdctl r2,status + 10151dc: e0bffd15 stw r2,-12(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 10151e0: e0fffd17 ldw r3,-12(fp) + 10151e4: 00bfff84 movi r2,-2 + 10151e8: 1884703a and r2,r3,r2 + 10151ec: 1001703a wrctl status,r2 + + return context; + 10151f0: e0bffd17 ldw r2,-12(fp) + return; + + OS_ENTER_CRITICAL(); + 10151f4: e0bffe15 stw r2,-8(fp) + if (locks == 0) + 10151f8: d0a75917 ldw r2,-25244(gp) + 10151fc: 1004c03a cmpne r2,r2,zero + 1015200: 1000051e bne r2,zero,1015218 <__malloc_unlock+0x70> + 1015204: e0bffe17 ldw r2,-8(fp) + 1015208: e0bffc15 stw r2,-16(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 101520c: e0bffc17 ldw r2,-16(fp) + 1015210: 1001703a wrctl status,r2 + { + OS_EXIT_CRITICAL(); + return; + 1015214: 00001306 br 1015264 <__malloc_unlock+0xbc> + } + + /* release the heap once the number of locks == the number of unlocks */ + if( (--locks) == 0 ) + 1015218: d0a75917 ldw r2,-25244(gp) + 101521c: 10bfffc4 addi r2,r2,-1 + 1015220: d0a75915 stw r2,-25244(gp) + 1015224: d0a75917 ldw r2,-25244(gp) + 1015228: 1004c03a cmpne r2,r2,zero + 101522c: 1000091e bne r2,zero,1015254 <__malloc_unlock+0xac> + { + lockid = -1; + 1015230: 00bfffc4 movi r2,-1 + 1015234: d0a01b15 stw r2,-32660(gp) + 1015238: e0bffe17 ldw r2,-8(fp) + 101523c: e0bffb15 stw r2,-20(fp) + 1015240: e0bffb17 ldw r2,-20(fp) + 1015244: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + OSSemPost( alt_heapsem ); + 1015248: d1275a17 ldw r4,-25240(gp) + 101524c: 101b2100 call 101b210 + 1015250: 00000406 br 1015264 <__malloc_unlock+0xbc> + 1015254: e0bffe17 ldw r2,-8(fp) + 1015258: e0bffa15 stw r2,-24(fp) + 101525c: e0bffa17 ldw r2,-24(fp) + 1015260: 1001703a wrctl status,r2 + { + OS_EXIT_CRITICAL(); + } + +#endif /* OS_THREAD_SAFE_NEWLIB */ +} + 1015264: e037883a mov sp,fp + 1015268: dfc00117 ldw ra,4(sp) + 101526c: df000017 ldw fp,0(sp) + 1015270: dec00204 addi sp,sp,8 + 1015274: f800283a ret + +01015278 : +********************************************************************************************************* +*/ + +#if (OS_EVENT_EN) && (OS_EVENT_NAME_SIZE > 1) +INT8U OSEventNameGet (OS_EVENT *pevent, INT8U *pname, INT8U *perr) +{ + 1015278: defff604 addi sp,sp,-40 + 101527c: dfc00915 stw ra,36(sp) + 1015280: df000815 stw fp,32(sp) + 1015284: df000804 addi fp,sp,32 + 1015288: e13ffc15 stw r4,-16(fp) + 101528c: e17ffd15 stw r5,-12(fp) + 1015290: e1bffe15 stw r6,-8(fp) + INT8U len; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 1015294: e03ffa15 stw zero,-24(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + 1015298: e0bffe17 ldw r2,-8(fp) + 101529c: 1004c03a cmpne r2,r2,zero + 10152a0: 1000021e bne r2,zero,10152ac + return (0); + 10152a4: e03fff15 stw zero,-4(fp) + 10152a8: 00003906 br 1015390 + } + if (pevent == (OS_EVENT *)0) { /* Is 'pevent' a NULL pointer? */ + 10152ac: e0bffc17 ldw r2,-16(fp) + 10152b0: 1004c03a cmpne r2,r2,zero + 10152b4: 1000051e bne r2,zero,10152cc + *perr = OS_ERR_PEVENT_NULL; + 10152b8: e0fffe17 ldw r3,-8(fp) + 10152bc: 00800104 movi r2,4 + 10152c0: 18800005 stb r2,0(r3) + return (0); + 10152c4: e03fff15 stw zero,-4(fp) + 10152c8: 00003106 br 1015390 + } + if (pname == (INT8U *)0) { /* Is 'pname' a NULL pointer? */ + 10152cc: e0bffd17 ldw r2,-12(fp) + 10152d0: 1004c03a cmpne r2,r2,zero + 10152d4: 1000051e bne r2,zero,10152ec + *perr = OS_ERR_PNAME_NULL; + 10152d8: e0fffe17 ldw r3,-8(fp) + 10152dc: 00800304 movi r2,12 + 10152e0: 18800005 stb r2,0(r3) + return (0); + 10152e4: e03fff15 stw zero,-4(fp) + 10152e8: 00002906 br 1015390 + } +#endif + if (OSIntNesting > 0) { /* See if trying to call from an ISR */ + 10152ec: d0a76903 ldbu r2,-25180(gp) + 10152f0: 10803fcc andi r2,r2,255 + 10152f4: 1005003a cmpeq r2,r2,zero + 10152f8: 1000051e bne r2,zero,1015310 + *perr = OS_ERR_NAME_GET_ISR; + 10152fc: e0fffe17 ldw r3,-8(fp) + 1015300: 00800444 movi r2,17 + 1015304: 18800005 stb r2,0(r3) + return (0); + 1015308: e03fff15 stw zero,-4(fp) + 101530c: 00002006 br 1015390 + } + switch (pevent->OSEventType) { + 1015310: e0bffc17 ldw r2,-16(fp) + 1015314: 10800003 ldbu r2,0(r2) + 1015318: 10803fcc andi r2,r2,255 + 101531c: 10bfffc4 addi r2,r2,-1 + 1015320: 10800128 cmpgeui r2,r2,4 + 1015324: 1000161e bne r2,zero,1015380 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1015328: 0005303a rdctl r2,status + 101532c: e0bff915 stw r2,-28(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1015330: e0fff917 ldw r3,-28(fp) + 1015334: 00bfff84 movi r2,-2 + 1015338: 1884703a and r2,r3,r2 + 101533c: 1001703a wrctl status,r2 + + return context; + 1015340: e0bff917 ldw r2,-28(fp) + + default: + *perr = OS_ERR_EVENT_TYPE; + return (0); + } + OS_ENTER_CRITICAL(); + 1015344: e0bffa15 stw r2,-24(fp) + len = OS_StrCopy(pname, pevent->OSEventName); /* Copy name from OS_EVENT */ + 1015348: e0bffc17 ldw r2,-16(fp) + 101534c: 11400384 addi r5,r2,14 + 1015350: e13ffd17 ldw r4,-12(fp) + 1015354: 1016dfc0 call 1016dfc + 1015358: e0bffb05 stb r2,-20(fp) + 101535c: e0bffa17 ldw r2,-24(fp) + 1015360: e0bff815 stw r2,-32(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1015364: e0bff817 ldw r2,-32(fp) + 1015368: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + 101536c: e0bffe17 ldw r2,-8(fp) + 1015370: 10000005 stb zero,0(r2) + return (len); + 1015374: e0bffb03 ldbu r2,-20(fp) + 1015378: e0bfff15 stw r2,-4(fp) + 101537c: 00000406 br 1015390 + case OS_EVENT_TYPE_MBOX: + case OS_EVENT_TYPE_Q: + break; + + default: + *perr = OS_ERR_EVENT_TYPE; + 1015380: e0fffe17 ldw r3,-8(fp) + 1015384: 00800044 movi r2,1 + 1015388: 18800005 stb r2,0(r3) + return (0); + 101538c: e03fff15 stw zero,-4(fp) + 1015390: e0bfff17 ldw r2,-4(fp) + OS_ENTER_CRITICAL(); + len = OS_StrCopy(pname, pevent->OSEventName); /* Copy name from OS_EVENT */ + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + return (len); +} + 1015394: e037883a mov sp,fp + 1015398: dfc00117 ldw ra,4(sp) + 101539c: df000017 ldw fp,0(sp) + 10153a0: dec00204 addi sp,sp,8 + 10153a4: f800283a ret + +010153a8 : +********************************************************************************************************* +*/ + +#if (OS_EVENT_EN) && (OS_EVENT_NAME_SIZE > 1) +void OSEventNameSet (OS_EVENT *pevent, INT8U *pname, INT8U *perr) +{ + 10153a8: defff604 addi sp,sp,-40 + 10153ac: dfc00915 stw ra,36(sp) + 10153b0: df000815 stw fp,32(sp) + 10153b4: df000804 addi fp,sp,32 + 10153b8: e13ffd15 stw r4,-12(fp) + 10153bc: e17ffe15 stw r5,-8(fp) + 10153c0: e1bfff15 stw r6,-4(fp) + INT8U len; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 10153c4: e03ffb15 stw zero,-20(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + 10153c8: e0bfff17 ldw r2,-4(fp) + 10153cc: 1005003a cmpeq r2,r2,zero + 10153d0: 1000411e bne r2,zero,10154d8 + return; + } + if (pevent == (OS_EVENT *)0) { /* Is 'pevent' a NULL pointer? */ + 10153d4: e0bffd17 ldw r2,-12(fp) + 10153d8: 1004c03a cmpne r2,r2,zero + 10153dc: 1000041e bne r2,zero,10153f0 + *perr = OS_ERR_PEVENT_NULL; + 10153e0: e0ffff17 ldw r3,-4(fp) + 10153e4: 00800104 movi r2,4 + 10153e8: 18800005 stb r2,0(r3) + return; + 10153ec: 00003a06 br 10154d8 + } + if (pname == (INT8U *)0) { /* Is 'pname' a NULL pointer? */ + 10153f0: e0bffe17 ldw r2,-8(fp) + 10153f4: 1004c03a cmpne r2,r2,zero + 10153f8: 1000041e bne r2,zero,101540c + *perr = OS_ERR_PNAME_NULL; + 10153fc: e0ffff17 ldw r3,-4(fp) + 1015400: 00800304 movi r2,12 + 1015404: 18800005 stb r2,0(r3) + return; + 1015408: 00003306 br 10154d8 + } +#endif + if (OSIntNesting > 0) { /* See if trying to call from an ISR */ + 101540c: d0a76903 ldbu r2,-25180(gp) + 1015410: 10803fcc andi r2,r2,255 + 1015414: 1005003a cmpeq r2,r2,zero + 1015418: 1000041e bne r2,zero,101542c + *perr = OS_ERR_NAME_SET_ISR; + 101541c: e0ffff17 ldw r3,-4(fp) + 1015420: 00800484 movi r2,18 + 1015424: 18800005 stb r2,0(r3) + return; + 1015428: 00002b06 br 10154d8 + } + switch (pevent->OSEventType) { + 101542c: e0bffd17 ldw r2,-12(fp) + 1015430: 10800003 ldbu r2,0(r2) + 1015434: 10803fcc andi r2,r2,255 + 1015438: 10bfffc4 addi r2,r2,-1 + 101543c: 10800128 cmpgeui r2,r2,4 + 1015440: 10000f1e bne r2,zero,1015480 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1015444: 0005303a rdctl r2,status + 1015448: e0bffa15 stw r2,-24(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 101544c: e0fffa17 ldw r3,-24(fp) + 1015450: 00bfff84 movi r2,-2 + 1015454: 1884703a and r2,r3,r2 + 1015458: 1001703a wrctl status,r2 + + return context; + 101545c: e0bffa17 ldw r2,-24(fp) + + default: + *perr = OS_ERR_EVENT_TYPE; + return; + } + OS_ENTER_CRITICAL(); + 1015460: e0bffb15 stw r2,-20(fp) + len = OS_StrLen(pname); /* Can we fit the string in the storage area? */ + 1015464: e13ffe17 ldw r4,-8(fp) + 1015468: 1016e7c0 call 1016e7c + 101546c: e0bffc05 stb r2,-16(fp) + if (len > (OS_EVENT_NAME_SIZE - 1)) { /* No */ + 1015470: e0bffc03 ldbu r2,-16(fp) + 1015474: 10800828 cmpgeui r2,r2,32 + 1015478: 1000051e bne r2,zero,1015490 + 101547c: 00000c06 br 10154b0 + case OS_EVENT_TYPE_MBOX: + case OS_EVENT_TYPE_Q: + break; + + default: + *perr = OS_ERR_EVENT_TYPE; + 1015480: e0ffff17 ldw r3,-4(fp) + 1015484: 00800044 movi r2,1 + 1015488: 18800005 stb r2,0(r3) + return; + 101548c: 00001206 br 10154d8 + 1015490: e0bffb17 ldw r2,-20(fp) + 1015494: e0bff915 stw r2,-28(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1015498: e0bff917 ldw r2,-28(fp) + 101549c: 1001703a wrctl status,r2 + } + OS_ENTER_CRITICAL(); + len = OS_StrLen(pname); /* Can we fit the string in the storage area? */ + if (len > (OS_EVENT_NAME_SIZE - 1)) { /* No */ + OS_EXIT_CRITICAL(); + *perr = OS_ERR_EVENT_NAME_TOO_LONG; + 10154a0: e0ffff17 ldw r3,-4(fp) + 10154a4: 008002c4 movi r2,11 + 10154a8: 18800005 stb r2,0(r3) + return; + 10154ac: 00000a06 br 10154d8 + } + (void)OS_StrCopy(pevent->OSEventName, pname); /* Yes, copy name to the event control block */ + 10154b0: e0bffd17 ldw r2,-12(fp) + 10154b4: 11000384 addi r4,r2,14 + 10154b8: e17ffe17 ldw r5,-8(fp) + 10154bc: 1016dfc0 call 1016dfc + 10154c0: e0bffb17 ldw r2,-20(fp) + 10154c4: e0bff815 stw r2,-32(fp) + 10154c8: e0bff817 ldw r2,-32(fp) + 10154cc: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + 10154d0: e0bfff17 ldw r2,-4(fp) + 10154d4: 10000005 stb zero,0(r2) +} + 10154d8: e037883a mov sp,fp + 10154dc: dfc00117 ldw ra,4(sp) + 10154e0: df000017 ldw fp,0(sp) + 10154e4: dec00204 addi sp,sp,8 + 10154e8: f800283a ret + +010154ec : +********************************************************************************************************* +*/ +/*$PAGE*/ +#if ((OS_EVENT_EN) && (OS_EVENT_MULTI_EN > 0)) +INT16U OSEventPendMulti (OS_EVENT **pevents_pend, OS_EVENT **pevents_rdy, void **pmsgs_rdy, INT16U timeout, INT8U *perr) +{ + 10154ec: deffe704 addi sp,sp,-100 + 10154f0: dfc01815 stw ra,96(sp) + 10154f4: df001715 stw fp,92(sp) + 10154f8: df001704 addi fp,sp,92 + 10154fc: e13ff615 stw r4,-40(fp) + 1015500: e17ff715 stw r5,-36(fp) + 1015504: e1bff815 stw r6,-32(fp) + 1015508: e1fff90d sth r7,-28(fp) +#endif + BOOLEAN events_rdy; + INT16U events_rdy_nbr; + INT8U events_stat; +#if (OS_CRITICAL_METHOD == 3) /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 101550c: e03ff015 stw zero,-64(fp) +#endif + + + +#if (OS_ARG_CHK_EN > 0) + if (perr == (INT8U *)0) { /* Validate 'perr' */ + 1015510: e0800217 ldw r2,8(fp) + 1015514: 1004c03a cmpne r2,r2,zero + 1015518: 1000021e bne r2,zero,1015524 + return (0); + 101551c: e03fff15 stw zero,-4(fp) + 1015520: 00019906 br 1015b88 + } + if (pevents_pend == (OS_EVENT **)0) { /* Validate 'pevents_pend' */ + 1015524: e0bff617 ldw r2,-40(fp) + 1015528: 1004c03a cmpne r2,r2,zero + 101552c: 1000051e bne r2,zero,1015544 + *perr = OS_ERR_PEVENT_NULL; + 1015530: e0c00217 ldw r3,8(fp) + 1015534: 00800104 movi r2,4 + 1015538: 18800005 stb r2,0(r3) + return (0); + 101553c: e03fff15 stw zero,-4(fp) + 1015540: 00019106 br 1015b88 + } + if (pevents_rdy == (OS_EVENT **)0) { /* Validate 'pevents_rdy' */ + 1015544: e0bff717 ldw r2,-36(fp) + 1015548: 1004c03a cmpne r2,r2,zero + 101554c: 1000051e bne r2,zero,1015564 + *perr = OS_ERR_PEVENT_NULL; + 1015550: e0c00217 ldw r3,8(fp) + 1015554: 00800104 movi r2,4 + 1015558: 18800005 stb r2,0(r3) + return (0); + 101555c: e03fff15 stw zero,-4(fp) + 1015560: 00018906 br 1015b88 + } + if (pmsgs_rdy == (void **)0) { /* Validate 'pmsgs_rdy' */ + 1015564: e0bff817 ldw r2,-32(fp) + 1015568: 1004c03a cmpne r2,r2,zero + 101556c: 1000051e bne r2,zero,1015584 + *perr = OS_ERR_PEVENT_NULL; + 1015570: e0c00217 ldw r3,8(fp) + 1015574: 00800104 movi r2,4 + 1015578: 18800005 stb r2,0(r3) + return (0); + 101557c: e03fff15 stw zero,-4(fp) + 1015580: 00018106 br 1015b88 + } +#endif + + *pevents_rdy = (OS_EVENT *)0; /* Init array to NULL in case of errors */ + 1015584: e0bff717 ldw r2,-36(fp) + 1015588: 10000015 stw zero,0(r2) + + pevents = pevents_pend; + 101558c: e0bff617 ldw r2,-40(fp) + 1015590: e0bff515 stw r2,-44(fp) + pevent = *pevents; + 1015594: e0bff517 ldw r2,-44(fp) + 1015598: 10800017 ldw r2,0(r2) + 101559c: e0bff415 stw r2,-48(fp) + while (pevent != (OS_EVENT *)0) { + 10155a0: 00001806 br 1015604 + switch (pevent->OSEventType) { /* Validate event block types */ + 10155a4: e0bff417 ldw r2,-48(fp) + 10155a8: 10800003 ldbu r2,0(r2) + 10155ac: 10803fcc andi r2,r2,255 + 10155b0: e0bffe15 stw r2,-8(fp) + 10155b4: e0fffe17 ldw r3,-8(fp) + 10155b8: 188000a0 cmpeqi r2,r3,2 + 10155bc: 10000b1e bne r2,zero,10155ec + 10155c0: e0fffe17 ldw r3,-8(fp) + 10155c4: 188000e0 cmpeqi r2,r3,3 + 10155c8: 1000081e bne r2,zero,10155ec + 10155cc: e0fffe17 ldw r3,-8(fp) + 10155d0: 18800060 cmpeqi r2,r3,1 + 10155d4: 1000051e bne r2,zero,10155ec +#endif + + case OS_EVENT_TYPE_MUTEX: + case OS_EVENT_TYPE_FLAG: + default: + *perr = OS_ERR_EVENT_TYPE; + 10155d8: e0c00217 ldw r3,8(fp) + 10155dc: 00800044 movi r2,1 + 10155e0: 18800005 stb r2,0(r3) + return (0); + 10155e4: e03fff15 stw zero,-4(fp) + 10155e8: 00016706 br 1015b88 + } + pevents++; + 10155ec: e0bff517 ldw r2,-44(fp) + 10155f0: 10800104 addi r2,r2,4 + 10155f4: e0bff515 stw r2,-44(fp) + pevent = *pevents; + 10155f8: e0bff517 ldw r2,-44(fp) + 10155fc: 10800017 ldw r2,0(r2) + 1015600: e0bff415 stw r2,-48(fp) + + *pevents_rdy = (OS_EVENT *)0; /* Init array to NULL in case of errors */ + + pevents = pevents_pend; + pevent = *pevents; + while (pevent != (OS_EVENT *)0) { + 1015604: e0bff417 ldw r2,-48(fp) + 1015608: 1004c03a cmpne r2,r2,zero + 101560c: 103fe51e bne r2,zero,10155a4 + } + pevents++; + pevent = *pevents; + } + + if (OSIntNesting > 0) { /* See if called from ISR ... */ + 1015610: d0a76903 ldbu r2,-25180(gp) + 1015614: 10803fcc andi r2,r2,255 + 1015618: 1005003a cmpeq r2,r2,zero + 101561c: 1000051e bne r2,zero,1015634 + *perr = OS_ERR_PEND_ISR; /* ... can't PEND from an ISR */ + 1015620: e0c00217 ldw r3,8(fp) + 1015624: 00800084 movi r2,2 + 1015628: 18800005 stb r2,0(r3) + return (0); + 101562c: e03fff15 stw zero,-4(fp) + 1015630: 00015506 br 1015b88 + } + if (OSLockNesting > 0) { /* See if called with scheduler locked ... */ + 1015634: d0a75b03 ldbu r2,-25236(gp) + 1015638: 10803fcc andi r2,r2,255 + 101563c: 1005003a cmpeq r2,r2,zero + 1015640: 1000051e bne r2,zero,1015658 + *perr = OS_ERR_PEND_LOCKED; /* ... can't PEND when locked */ + 1015644: e0c00217 ldw r3,8(fp) + 1015648: 00800344 movi r2,13 + 101564c: 18800005 stb r2,0(r3) + return (0); + 1015650: e03fff15 stw zero,-4(fp) + 1015654: 00014c06 br 1015b88 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1015658: 0005303a rdctl r2,status + 101565c: e0bfef15 stw r2,-68(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1015660: e0ffef17 ldw r3,-68(fp) + 1015664: 00bfff84 movi r2,-2 + 1015668: 1884703a and r2,r3,r2 + 101566c: 1001703a wrctl status,r2 + + return context; + 1015670: e0bfef17 ldw r2,-68(fp) + } + +/*$PAGE*/ + OS_ENTER_CRITICAL(); + 1015674: e0bff015 stw r2,-64(fp) + events_rdy = OS_FALSE; + 1015678: e03ff205 stb zero,-56(fp) + events_rdy_nbr = 0; + 101567c: e03ff18d sth zero,-58(fp) + events_stat = OS_STAT_RDY; + 1015680: e03ff105 stb zero,-60(fp) + pevents = pevents_pend; + 1015684: e0bff617 ldw r2,-40(fp) + 1015688: e0bff515 stw r2,-44(fp) + pevent = *pevents; + 101568c: e0bff517 ldw r2,-44(fp) + 1015690: 10800017 ldw r2,0(r2) + 1015694: e0bff415 stw r2,-48(fp) + while (pevent != (OS_EVENT *)0) { /* See if any events already available */ + 1015698: 00008f06 br 10158d8 + switch (pevent->OSEventType) { + 101569c: e0bff417 ldw r2,-48(fp) + 10156a0: 10800003 ldbu r2,0(r2) + 10156a4: 10803fcc andi r2,r2,255 + 10156a8: e0bffd15 stw r2,-12(fp) + 10156ac: e0fffd17 ldw r3,-12(fp) + 10156b0: 188000a0 cmpeqi r2,r3,2 + 10156b4: 1000441e bne r2,zero,10157c8 + 10156b8: e0fffd17 ldw r3,-12(fp) + 10156bc: 188000e0 cmpeqi r2,r3,3 + 10156c0: 1000041e bne r2,zero,10156d4 + 10156c4: e0fffd17 ldw r3,-12(fp) + 10156c8: 18800060 cmpeqi r2,r3,1 + 10156cc: 1000211e bne r2,zero,1015754 + 10156d0: 00006f06 br 1015890 +#if (OS_SEM_EN > 0) + case OS_EVENT_TYPE_SEM: + if (pevent->OSEventCnt > 0) { /* If semaphore count > 0, resource available; */ + 10156d4: e0bff417 ldw r2,-48(fp) + 10156d8: 1080020b ldhu r2,8(r2) + 10156dc: 10bfffcc andi r2,r2,65535 + 10156e0: 1005003a cmpeq r2,r2,zero + 10156e4: 1000171e bne r2,zero,1015744 + pevent->OSEventCnt--; /* ... decrement semaphore, ... */ + 10156e8: e0bff417 ldw r2,-48(fp) + 10156ec: 1080020b ldhu r2,8(r2) + 10156f0: 10bfffc4 addi r2,r2,-1 + 10156f4: 1007883a mov r3,r2 + 10156f8: e0bff417 ldw r2,-48(fp) + 10156fc: 10c0020d sth r3,8(r2) + *pevents_rdy++ = pevent; /* ... and return available semaphore event */ + 1015700: e0fff717 ldw r3,-36(fp) + 1015704: e0bff417 ldw r2,-48(fp) + 1015708: 18800015 stw r2,0(r3) + 101570c: e0bff717 ldw r2,-36(fp) + 1015710: 10800104 addi r2,r2,4 + 1015714: e0bff715 stw r2,-36(fp) + events_rdy = OS_TRUE; + 1015718: 00800044 movi r2,1 + 101571c: e0bff205 stb r2,-56(fp) + *pmsgs_rdy++ = (void *)0; /* NO message returned for semaphores */ + 1015720: e0bff817 ldw r2,-32(fp) + 1015724: 10000015 stw zero,0(r2) + 1015728: e0bff817 ldw r2,-32(fp) + 101572c: 10800104 addi r2,r2,4 + 1015730: e0bff815 stw r2,-32(fp) + events_rdy_nbr++; + 1015734: e0bff18b ldhu r2,-58(fp) + 1015738: 10800044 addi r2,r2,1 + 101573c: e0bff18d sth r2,-58(fp) + 1015740: 00005f06 br 10158c0 + + } else { + events_stat |= OS_STAT_SEM; /* Configure multi-pend for semaphore events */ + 1015744: e0bff103 ldbu r2,-60(fp) + 1015748: 10800054 ori r2,r2,1 + 101574c: e0bff105 stb r2,-60(fp) + } + break; + 1015750: 00005b06 br 10158c0 +#endif + +#if (OS_MBOX_EN > 0) + case OS_EVENT_TYPE_MBOX: + if (pevent->OSEventPtr != (void *)0) { /* If mailbox NOT empty; ... */ + 1015754: e0bff417 ldw r2,-48(fp) + 1015758: 10800117 ldw r2,4(r2) + 101575c: 1005003a cmpeq r2,r2,zero + 1015760: 1000151e bne r2,zero,10157b8 + /* ... return available message, ... */ + *pmsgs_rdy++ = (void *)pevent->OSEventPtr; + 1015764: e0bff417 ldw r2,-48(fp) + 1015768: 10c00117 ldw r3,4(r2) + 101576c: e0bff817 ldw r2,-32(fp) + 1015770: 10c00015 stw r3,0(r2) + 1015774: e0bff817 ldw r2,-32(fp) + 1015778: 10800104 addi r2,r2,4 + 101577c: e0bff815 stw r2,-32(fp) + pevent->OSEventPtr = (void *)0; + 1015780: e0bff417 ldw r2,-48(fp) + 1015784: 10000115 stw zero,4(r2) + *pevents_rdy++ = pevent; /* ... and return available mailbox event */ + 1015788: e0fff717 ldw r3,-36(fp) + 101578c: e0bff417 ldw r2,-48(fp) + 1015790: 18800015 stw r2,0(r3) + 1015794: e0bff717 ldw r2,-36(fp) + 1015798: 10800104 addi r2,r2,4 + 101579c: e0bff715 stw r2,-36(fp) + events_rdy = OS_TRUE; + 10157a0: 00800044 movi r2,1 + 10157a4: e0bff205 stb r2,-56(fp) + events_rdy_nbr++; + 10157a8: e0bff18b ldhu r2,-58(fp) + 10157ac: 10800044 addi r2,r2,1 + 10157b0: e0bff18d sth r2,-58(fp) + 10157b4: 00004206 br 10158c0 + + } else { + events_stat |= OS_STAT_MBOX; /* Configure multi-pend for mailbox events */ + 10157b8: e0bff103 ldbu r2,-60(fp) + 10157bc: 10800094 ori r2,r2,2 + 10157c0: e0bff105 stb r2,-60(fp) + } + break; + 10157c4: 00003e06 br 10158c0 +#endif + +#if ((OS_Q_EN > 0) && (OS_MAX_QS > 0)) + case OS_EVENT_TYPE_Q: + pq = (OS_Q *)pevent->OSEventPtr; + 10157c8: e0bff417 ldw r2,-48(fp) + 10157cc: 10800117 ldw r2,4(r2) + 10157d0: e0bff315 stw r2,-52(fp) + if (pq->OSQEntries > 0) { /* If queue NOT empty; ... */ + 10157d4: e0bff317 ldw r2,-52(fp) + 10157d8: 1080058b ldhu r2,22(r2) + 10157dc: 10bfffcc andi r2,r2,65535 + 10157e0: 1005003a cmpeq r2,r2,zero + 10157e4: 1000261e bne r2,zero,1015880 + /* ... return available message, ... */ + *pmsgs_rdy++ = (void *)*pq->OSQOut++; + 10157e8: e0bff317 ldw r2,-52(fp) + 10157ec: 11000417 ldw r4,16(r2) + 10157f0: 20c00017 ldw r3,0(r4) + 10157f4: e0bff817 ldw r2,-32(fp) + 10157f8: 10c00015 stw r3,0(r2) + 10157fc: e0bff817 ldw r2,-32(fp) + 1015800: 10800104 addi r2,r2,4 + 1015804: e0bff815 stw r2,-32(fp) + 1015808: 20c00104 addi r3,r4,4 + 101580c: e0bff317 ldw r2,-52(fp) + 1015810: 10c00415 stw r3,16(r2) + if (pq->OSQOut == pq->OSQEnd) { /* If OUT ptr at queue end, ... */ + 1015814: e0bff317 ldw r2,-52(fp) + 1015818: 10c00417 ldw r3,16(r2) + 101581c: e0bff317 ldw r2,-52(fp) + 1015820: 10800217 ldw r2,8(r2) + 1015824: 1880041e bne r3,r2,1015838 + pq->OSQOut = pq->OSQStart; /* ... wrap to queue start */ + 1015828: e0bff317 ldw r2,-52(fp) + 101582c: 10c00117 ldw r3,4(r2) + 1015830: e0bff317 ldw r2,-52(fp) + 1015834: 10c00415 stw r3,16(r2) + } + pq->OSQEntries--; /* Update number of queue entries */ + 1015838: e0bff317 ldw r2,-52(fp) + 101583c: 1080058b ldhu r2,22(r2) + 1015840: 10bfffc4 addi r2,r2,-1 + 1015844: 1007883a mov r3,r2 + 1015848: e0bff317 ldw r2,-52(fp) + 101584c: 10c0058d sth r3,22(r2) + *pevents_rdy++ = pevent; /* ... and return available queue event */ + 1015850: e0fff717 ldw r3,-36(fp) + 1015854: e0bff417 ldw r2,-48(fp) + 1015858: 18800015 stw r2,0(r3) + 101585c: e0bff717 ldw r2,-36(fp) + 1015860: 10800104 addi r2,r2,4 + 1015864: e0bff715 stw r2,-36(fp) + events_rdy = OS_TRUE; + 1015868: 00800044 movi r2,1 + 101586c: e0bff205 stb r2,-56(fp) + events_rdy_nbr++; + 1015870: e0bff18b ldhu r2,-58(fp) + 1015874: 10800044 addi r2,r2,1 + 1015878: e0bff18d sth r2,-58(fp) + 101587c: 00001006 br 10158c0 + + } else { + events_stat |= OS_STAT_Q; /* Configure multi-pend for queue events */ + 1015880: e0bff103 ldbu r2,-60(fp) + 1015884: 10800114 ori r2,r2,4 + 1015888: e0bff105 stb r2,-60(fp) + } + break; + 101588c: 00000c06 br 10158c0 + 1015890: e0bff017 ldw r2,-64(fp) + 1015894: e0bfee15 stw r2,-72(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1015898: e0bfee17 ldw r2,-72(fp) + 101589c: 1001703a wrctl status,r2 + + case OS_EVENT_TYPE_MUTEX: + case OS_EVENT_TYPE_FLAG: + default: + OS_EXIT_CRITICAL(); + *pevents_rdy = (OS_EVENT *)0; /* NULL terminate return event array */ + 10158a0: e0bff717 ldw r2,-36(fp) + 10158a4: 10000015 stw zero,0(r2) + *perr = OS_ERR_EVENT_TYPE; + 10158a8: e0c00217 ldw r3,8(fp) + 10158ac: 00800044 movi r2,1 + 10158b0: 18800005 stb r2,0(r3) + return (events_rdy_nbr); + 10158b4: e0bff18b ldhu r2,-58(fp) + 10158b8: e0bfff15 stw r2,-4(fp) + 10158bc: 0000b206 br 1015b88 + } + pevents++; + 10158c0: e0bff517 ldw r2,-44(fp) + 10158c4: 10800104 addi r2,r2,4 + 10158c8: e0bff515 stw r2,-44(fp) + pevent = *pevents; + 10158cc: e0bff517 ldw r2,-44(fp) + 10158d0: 10800017 ldw r2,0(r2) + 10158d4: e0bff415 stw r2,-48(fp) + events_rdy = OS_FALSE; + events_rdy_nbr = 0; + events_stat = OS_STAT_RDY; + pevents = pevents_pend; + pevent = *pevents; + while (pevent != (OS_EVENT *)0) { /* See if any events already available */ + 10158d8: e0bff417 ldw r2,-48(fp) + 10158dc: 1004c03a cmpne r2,r2,zero + 10158e0: 103f6e1e bne r2,zero,101569c + } + pevents++; + pevent = *pevents; + } + + if ( events_rdy == OS_TRUE) { /* Return any events already available */ + 10158e4: e0bff203 ldbu r2,-56(fp) + 10158e8: 10800058 cmpnei r2,r2,1 + 10158ec: 10000b1e bne r2,zero,101591c + *pevents_rdy = (OS_EVENT *)0; /* NULL terminate return event array */ + 10158f0: e0bff717 ldw r2,-36(fp) + 10158f4: 10000015 stw zero,0(r2) + 10158f8: e0bff017 ldw r2,-64(fp) + 10158fc: e0bfed15 stw r2,-76(fp) + 1015900: e0bfed17 ldw r2,-76(fp) + 1015904: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + 1015908: e0800217 ldw r2,8(fp) + 101590c: 10000005 stb zero,0(r2) + return (events_rdy_nbr); + 1015910: e0fff18b ldhu r3,-58(fp) + 1015914: e0ffff15 stw r3,-4(fp) + 1015918: 00009b06 br 1015b88 + } +/*$PAGE*/ + /* Otherwise, must wait until any event occurs */ + OSTCBCur->OSTCBStat |= events_stat | /* Resource not available, ... */ + 101591c: d1276a17 ldw r4,-25176(gp) + 1015920: d0a76a17 ldw r2,-25176(gp) + 1015924: 10c00c03 ldbu r3,48(r2) + 1015928: e0bff103 ldbu r2,-60(fp) + 101592c: 1884b03a or r2,r3,r2 + 1015930: 1007883a mov r3,r2 + 1015934: 00bfe004 movi r2,-128 + 1015938: 1884b03a or r2,r3,r2 + 101593c: 20800c05 stb r2,48(r4) + OS_STAT_MULTI; /* ... pend on multiple events */ + OSTCBCur->OSTCBStatPend = OS_STAT_PEND_OK; + 1015940: d0a76a17 ldw r2,-25176(gp) + 1015944: 10000c45 stb zero,49(r2) + OSTCBCur->OSTCBDly = timeout; /* Store pend timeout in TCB */ + 1015948: d0e76a17 ldw r3,-25176(gp) + 101594c: e0bff90b ldhu r2,-28(fp) + 1015950: 18800b8d sth r2,46(r3) + OS_EventTaskWaitMulti(pevents_pend); /* Suspend task until events or timeout occurs */ + 1015954: e13ff617 ldw r4,-40(fp) + 1015958: 101651c0 call 101651c + 101595c: e0bff017 ldw r2,-64(fp) + 1015960: e0bfec15 stw r2,-80(fp) + 1015964: e0bfec17 ldw r2,-80(fp) + 1015968: 1001703a wrctl status,r2 + + OS_EXIT_CRITICAL(); + OS_Sched(); /* Find next highest priority task ready */ + 101596c: 1016cb80 call 1016cb8 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1015970: 0005303a rdctl r2,status + 1015974: e0bfeb15 stw r2,-84(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1015978: e0ffeb17 ldw r3,-84(fp) + 101597c: 00bfff84 movi r2,-2 + 1015980: 1884703a and r2,r3,r2 + 1015984: 1001703a wrctl status,r2 + + return context; + 1015988: e0bfeb17 ldw r2,-84(fp) + OS_ENTER_CRITICAL(); + 101598c: e0bff015 stw r2,-64(fp) + + switch (OSTCBCur->OSTCBStatPend) { /* Handle event posted, aborted, or timed-out */ + 1015990: d0a76a17 ldw r2,-25176(gp) + 1015994: 10800c43 ldbu r2,49(r2) + 1015998: 10803fcc andi r2,r2,255 + 101599c: e0bffc15 stw r2,-16(fp) + 10159a0: e0fffc17 ldw r3,-16(fp) + 10159a4: 1805003a cmpeq r2,r3,zero + 10159a8: 1000041e bne r2,zero,10159bc + 10159ac: e0fffc17 ldw r3,-16(fp) + 10159b0: 188000a0 cmpeqi r2,r3,2 + 10159b4: 1000011e bne r2,zero,10159bc + 10159b8: 00001906 br 1015a20 + case OS_STAT_PEND_OK: + case OS_STAT_PEND_ABORT: + pevent = OSTCBCur->OSTCBEventPtr; + 10159bc: d0a76a17 ldw r2,-25176(gp) + 10159c0: 10800717 ldw r2,28(r2) + 10159c4: e0bff415 stw r2,-48(fp) + if (pevent != (OS_EVENT *)0) { /* If task event ptr != NULL, ... */ + 10159c8: e0bff417 ldw r2,-48(fp) + 10159cc: 1005003a cmpeq r2,r2,zero + 10159d0: 10000c1e bne r2,zero,1015a04 + *pevents_rdy++ = pevent; /* ... return available event ... */ + 10159d4: e0fff717 ldw r3,-36(fp) + 10159d8: e0bff417 ldw r2,-48(fp) + 10159dc: 18800015 stw r2,0(r3) + 10159e0: e0bff717 ldw r2,-36(fp) + 10159e4: 10800104 addi r2,r2,4 + 10159e8: e0bff715 stw r2,-36(fp) + *pevents_rdy = (OS_EVENT *)0; /* ... & NULL terminate return event array */ + 10159ec: e0bff717 ldw r2,-36(fp) + 10159f0: 10000015 stw zero,0(r2) + events_rdy_nbr++; + 10159f4: e0bff18b ldhu r2,-58(fp) + 10159f8: 10800044 addi r2,r2,1 + 10159fc: e0bff18d sth r2,-58(fp) + 1015a00: 00000a06 br 1015a2c + + } else { /* Else NO event available, handle as timeout */ + OSTCBCur->OSTCBStatPend = OS_STAT_PEND_TO; + 1015a04: d0a76a17 ldw r2,-25176(gp) + 1015a08: 00c00044 movi r3,1 + 1015a0c: 10c00c45 stb r3,49(r2) + OS_EventTaskRemoveMulti(OSTCBCur, pevents_pend); + 1015a10: d1276a17 ldw r4,-25176(gp) + 1015a14: e17ff617 ldw r5,-40(fp) + 1015a18: 10167280 call 1016728 + } + break; + 1015a1c: 00000306 br 1015a2c + + case OS_STAT_PEND_TO: + default: /* ... remove task from events' wait lists */ + OS_EventTaskRemoveMulti(OSTCBCur, pevents_pend); + 1015a20: d1276a17 ldw r4,-25176(gp) + 1015a24: e17ff617 ldw r5,-40(fp) + 1015a28: 10167280 call 1016728 + break; + } + + switch (OSTCBCur->OSTCBStatPend) { + 1015a2c: d0a76a17 ldw r2,-25176(gp) + 1015a30: 10800c43 ldbu r2,49(r2) + 1015a34: 10803fcc andi r2,r2,255 + 1015a38: e0bffb15 stw r2,-20(fp) + 1015a3c: e0fffb17 ldw r3,-20(fp) + 1015a40: 1805003a cmpeq r2,r3,zero + 1015a44: 1000041e bne r2,zero,1015a58 + 1015a48: e0fffb17 ldw r3,-20(fp) + 1015a4c: 188000a0 cmpeqi r2,r3,2 + 1015a50: 10002c1e bne r2,zero,1015b04 + 1015a54: 00003406 br 1015b28 + case OS_STAT_PEND_OK: + switch (pevent->OSEventType) { /* Return event's message */ + 1015a58: e0bff417 ldw r2,-48(fp) + 1015a5c: 10800003 ldbu r2,0(r2) + 1015a60: 10803fcc andi r2,r2,255 + 1015a64: e0bffa15 stw r2,-24(fp) + 1015a68: e0fffa17 ldw r3,-24(fp) + 1015a6c: 18800050 cmplti r2,r3,1 + 1015a70: 1000151e bne r2,zero,1015ac8 + 1015a74: e0fffa17 ldw r3,-24(fp) + 1015a78: 188000d0 cmplti r2,r3,3 + 1015a7c: 10000a1e bne r2,zero,1015aa8 + 1015a80: e0fffa17 ldw r3,-24(fp) + 1015a84: 188000e0 cmpeqi r2,r3,3 + 1015a88: 1000011e bne r2,zero,1015a90 + 1015a8c: 00000e06 br 1015ac8 +#if (OS_SEM_EN > 0) + case OS_EVENT_TYPE_SEM: + *pmsgs_rdy++ = (void *)0; /* NO message returned for semaphores */ + 1015a90: e0bff817 ldw r2,-32(fp) + 1015a94: 10000015 stw zero,0(r2) + 1015a98: e0bff817 ldw r2,-32(fp) + 1015a9c: 10800104 addi r2,r2,4 + 1015aa0: e0bff815 stw r2,-32(fp) + break; + 1015aa4: 00001406 br 1015af8 + +#if ((OS_MBOX_EN > 0) || \ + ((OS_Q_EN > 0) && (OS_MAX_QS > 0))) + case OS_EVENT_TYPE_MBOX: + case OS_EVENT_TYPE_Q: + *pmsgs_rdy++ = (void *)OSTCBCur->OSTCBMsg; /* Return received message */ + 1015aa8: d0a76a17 ldw r2,-25176(gp) + 1015aac: 10c00917 ldw r3,36(r2) + 1015ab0: e0bff817 ldw r2,-32(fp) + 1015ab4: 10c00015 stw r3,0(r2) + 1015ab8: e0bff817 ldw r2,-32(fp) + 1015abc: 10800104 addi r2,r2,4 + 1015ac0: e0bff815 stw r2,-32(fp) + break; + 1015ac4: 00000c06 br 1015af8 + 1015ac8: e0bff017 ldw r2,-64(fp) + 1015acc: e0bfea15 stw r2,-88(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1015ad0: e0bfea17 ldw r2,-88(fp) + 1015ad4: 1001703a wrctl status,r2 + + case OS_EVENT_TYPE_MUTEX: + case OS_EVENT_TYPE_FLAG: + default: + OS_EXIT_CRITICAL(); + *pevents_rdy = (OS_EVENT *)0; /* NULL terminate return event array */ + 1015ad8: e0bff717 ldw r2,-36(fp) + 1015adc: 10000015 stw zero,0(r2) + *perr = OS_ERR_EVENT_TYPE; + 1015ae0: e0c00217 ldw r3,8(fp) + 1015ae4: 00800044 movi r2,1 + 1015ae8: 18800005 stb r2,0(r3) + return (events_rdy_nbr); + 1015aec: e0bff18b ldhu r2,-58(fp) + 1015af0: e0bfff15 stw r2,-4(fp) + 1015af4: 00002406 br 1015b88 + } + *perr = OS_ERR_NONE; + 1015af8: e0800217 ldw r2,8(fp) + 1015afc: 10000005 stb zero,0(r2) + break; + 1015b00: 00001106 br 1015b48 + + case OS_STAT_PEND_ABORT: + *pmsgs_rdy++ = (void *)0; /* NO message returned for abort */ + 1015b04: e0bff817 ldw r2,-32(fp) + 1015b08: 10000015 stw zero,0(r2) + 1015b0c: e0bff817 ldw r2,-32(fp) + 1015b10: 10800104 addi r2,r2,4 + 1015b14: e0bff815 stw r2,-32(fp) + *perr = OS_ERR_PEND_ABORT; /* Indicate that event aborted */ + 1015b18: e0c00217 ldw r3,8(fp) + 1015b1c: 00800384 movi r2,14 + 1015b20: 18800005 stb r2,0(r3) + break; + 1015b24: 00000806 br 1015b48 + + case OS_STAT_PEND_TO: + default: + *pmsgs_rdy++ = (void *)0; /* NO message returned for timeout */ + 1015b28: e0bff817 ldw r2,-32(fp) + 1015b2c: 10000015 stw zero,0(r2) + 1015b30: e0bff817 ldw r2,-32(fp) + 1015b34: 10800104 addi r2,r2,4 + 1015b38: e0bff815 stw r2,-32(fp) + *perr = OS_ERR_TIMEOUT; /* Indicate that events timed out */ + 1015b3c: e0c00217 ldw r3,8(fp) + 1015b40: 00800284 movi r2,10 + 1015b44: 18800005 stb r2,0(r3) + break; + } + + OSTCBCur->OSTCBStat = OS_STAT_RDY; /* Set task status to ready */ + 1015b48: d0a76a17 ldw r2,-25176(gp) + 1015b4c: 10000c05 stb zero,48(r2) + OSTCBCur->OSTCBStatPend = OS_STAT_PEND_OK; /* Clear pend status */ + 1015b50: d0a76a17 ldw r2,-25176(gp) + 1015b54: 10000c45 stb zero,49(r2) + OSTCBCur->OSTCBEventPtr = (OS_EVENT *)0; /* Clear event pointers */ + 1015b58: d0a76a17 ldw r2,-25176(gp) + 1015b5c: 10000715 stw zero,28(r2) + OSTCBCur->OSTCBEventMultiPtr = (OS_EVENT **)0; + 1015b60: d0a76a17 ldw r2,-25176(gp) + 1015b64: 10000815 stw zero,32(r2) + OSTCBCur->OSTCBMsg = (void *)0; /* Clear task message */ + 1015b68: d0a76a17 ldw r2,-25176(gp) + 1015b6c: 10000915 stw zero,36(r2) + 1015b70: e0bff017 ldw r2,-64(fp) + 1015b74: e0bfe915 stw r2,-92(fp) + 1015b78: e0bfe917 ldw r2,-92(fp) + 1015b7c: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + + return (events_rdy_nbr); + 1015b80: e0fff18b ldhu r3,-58(fp) + 1015b84: e0ffff15 stw r3,-4(fp) + 1015b88: e0bfff17 ldw r2,-4(fp) +} + 1015b8c: e037883a mov sp,fp + 1015b90: dfc00117 ldw ra,4(sp) + 1015b94: df000017 ldw fp,0(sp) + 1015b98: dec00204 addi sp,sp,8 + 1015b9c: f800283a ret + +01015ba0 : +* Returns : none +********************************************************************************************************* +*/ + +void OSInit (void) +{ + 1015ba0: defffe04 addi sp,sp,-8 + 1015ba4: dfc00115 stw ra,4(sp) + 1015ba8: df000015 stw fp,0(sp) + 1015bac: d839883a mov fp,sp + OSInitHookBegin(); /* Call port specific initialization code */ + 1015bb0: 10204800 call 1020480 + + OS_InitMisc(); /* Initialize miscellaneous variables */ + 1015bb4: 10169700 call 1016970 + + OS_InitRdyList(); /* Initialize the Ready List */ + 1015bb8: 10169b40 call 10169b4 + + OS_InitTCBList(); /* Initialize the free list of OS_TCBs */ + 1015bbc: 1016b180 call 1016b18 + + OS_InitEventList(); /* Initialize the free list of OS_EVENTs */ + 1015bc0: 10168940 call 1016894 + +#if (OS_FLAG_EN > 0) && (OS_MAX_FLAGS > 0) + OS_FlagInit(); /* Initialize the event flag structures */ + 1015bc4: 1018bc80 call 1018bc8 +#endif + +#if (OS_MEM_EN > 0) && (OS_MAX_MEM_PART > 0) + OS_MemInit(); /* Initialize the memory manager */ + 1015bc8: 10195a00 call 10195a0 +#endif + +#if (OS_Q_EN > 0) && (OS_MAX_QS > 0) + OS_QInit(); /* Initialize the message queue structures */ + 1015bcc: 101a8f80 call 101a8f8 +#endif + + OS_InitTaskIdle(); /* Create the Idle Task */ + 1015bd0: 1016a200 call 1016a20 +#if OS_TASK_STAT_EN > 0 + OS_InitTaskStat(); /* Create the Statistic Task */ + 1015bd4: 1016a9c0 call 1016a9c + +#if OS_TMR_EN > 0 + OSTmr_Init(); /* Initialize the Timer Manager */ +#endif + + OSInitHookEnd(); /* Call port specific init. code */ + 1015bd8: 102049c0 call 102049c + +#if OS_DEBUG_EN > 0 + OSDebugInit(); + 1015bdc: 10173a00 call 10173a0 +#endif +} + 1015be0: e037883a mov sp,fp + 1015be4: dfc00117 ldw ra,4(sp) + 1015be8: df000017 ldw fp,0(sp) + 1015bec: dec00204 addi sp,sp,8 + 1015bf0: f800283a ret + +01015bf4 : +* 5) You are allowed to nest interrupts up to 255 levels deep. +********************************************************************************************************* +*/ + +void OSIntEnter (void) +{ + 1015bf4: defffc04 addi sp,sp,-16 + 1015bf8: df000315 stw fp,12(sp) + 1015bfc: df000304 addi fp,sp,12 +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 1015c00: e03fff15 stw zero,-4(fp) +#endif + + if (OSRunning == OS_TRUE) { + 1015c04: d0a75b43 ldbu r2,-25235(gp) + 1015c08: 10803fcc andi r2,r2,255 + 1015c0c: 10800058 cmpnei r2,r2,1 + 1015c10: 1000131e bne r2,zero,1015c60 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1015c14: 0005303a rdctl r2,status + 1015c18: e0bffe15 stw r2,-8(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1015c1c: e0fffe17 ldw r3,-8(fp) + 1015c20: 00bfff84 movi r2,-2 + 1015c24: 1884703a and r2,r3,r2 + 1015c28: 1001703a wrctl status,r2 + + return context; + 1015c2c: e0bffe17 ldw r2,-8(fp) + OS_ENTER_CRITICAL(); + 1015c30: e0bfff15 stw r2,-4(fp) + if (OSIntNesting < 255u) { + 1015c34: d0a76903 ldbu r2,-25180(gp) + 1015c38: 10803fcc andi r2,r2,255 + 1015c3c: 10803fe0 cmpeqi r2,r2,255 + 1015c40: 1000031e bne r2,zero,1015c50 + OSIntNesting++; /* Increment ISR nesting level */ + 1015c44: d0a76903 ldbu r2,-25180(gp) + 1015c48: 10800044 addi r2,r2,1 + 1015c4c: d0a76905 stb r2,-25180(gp) + 1015c50: e0bfff17 ldw r2,-4(fp) + 1015c54: e0bffd15 stw r2,-12(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1015c58: e0bffd17 ldw r2,-12(fp) + 1015c5c: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); + } +} + 1015c60: e037883a mov sp,fp + 1015c64: df000017 ldw fp,0(sp) + 1015c68: dec00104 addi sp,sp,4 + 1015c6c: f800283a ret + +01015c70 : +* 2) Rescheduling is prevented when the scheduler is locked (see OS_SchedLock()) +********************************************************************************************************* +*/ + +void OSIntExit (void) +{ + 1015c70: defffb04 addi sp,sp,-20 + 1015c74: dfc00415 stw ra,16(sp) + 1015c78: df000315 stw fp,12(sp) + 1015c7c: df000304 addi fp,sp,12 +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 1015c80: e03fff15 stw zero,-4(fp) +#endif + + + + if (OSRunning == OS_TRUE) { + 1015c84: d0a75b43 ldbu r2,-25235(gp) + 1015c88: 10803fcc andi r2,r2,255 + 1015c8c: 10800058 cmpnei r2,r2,1 + 1015c90: 1000321e bne r2,zero,1015d5c +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1015c94: 0005303a rdctl r2,status + 1015c98: e0bffe15 stw r2,-8(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1015c9c: e0fffe17 ldw r3,-8(fp) + 1015ca0: 00bfff84 movi r2,-2 + 1015ca4: 1884703a and r2,r3,r2 + 1015ca8: 1001703a wrctl status,r2 + + return context; + 1015cac: e0bffe17 ldw r2,-8(fp) + OS_ENTER_CRITICAL(); + 1015cb0: e0bfff15 stw r2,-4(fp) + if (OSIntNesting > 0) { /* Prevent OSIntNesting from wrapping */ + 1015cb4: d0a76903 ldbu r2,-25180(gp) + 1015cb8: 10803fcc andi r2,r2,255 + 1015cbc: 1005003a cmpeq r2,r2,zero + 1015cc0: 1000031e bne r2,zero,1015cd0 + OSIntNesting--; + 1015cc4: d0a76903 ldbu r2,-25180(gp) + 1015cc8: 10bfffc4 addi r2,r2,-1 + 1015ccc: d0a76905 stb r2,-25180(gp) + } + if (OSIntNesting == 0) { /* Reschedule only if all ISRs complete ... */ + 1015cd0: d0a76903 ldbu r2,-25180(gp) + 1015cd4: 10803fcc andi r2,r2,255 + 1015cd8: 1004c03a cmpne r2,r2,zero + 1015cdc: 10001b1e bne r2,zero,1015d4c + if (OSLockNesting == 0) { /* ... and not locked. */ + 1015ce0: d0a75b03 ldbu r2,-25236(gp) + 1015ce4: 10803fcc andi r2,r2,255 + 1015ce8: 1004c03a cmpne r2,r2,zero + 1015cec: 1000171e bne r2,zero,1015d4c + OS_SchedNew(); + 1015cf0: 1016d8c0 call 1016d8c + if (OSPrioHighRdy != OSPrioCur) { /* No Ctx Sw if current task is highest rdy */ + 1015cf4: d0a75d03 ldbu r2,-25228(gp) + 1015cf8: d0e75d43 ldbu r3,-25227(gp) + 1015cfc: 11003fcc andi r4,r2,255 + 1015d00: 18803fcc andi r2,r3,255 + 1015d04: 20801126 beq r4,r2,1015d4c + OSTCBHighRdy = OSTCBPrioTbl[OSPrioHighRdy]; + 1015d08: d0a75d03 ldbu r2,-25228(gp) + 1015d0c: 10803fcc andi r2,r2,255 + 1015d10: 00c040f4 movhi r3,259 + 1015d14: 18f3b104 addi r3,r3,-12604 + 1015d18: 1085883a add r2,r2,r2 + 1015d1c: 1085883a add r2,r2,r2 + 1015d20: 10c5883a add r2,r2,r3 + 1015d24: 10800017 ldw r2,0(r2) + 1015d28: d0a76515 stw r2,-25196(gp) +#if OS_TASK_PROFILE_EN > 0 + OSTCBHighRdy->OSTCBCtxSwCtr++; /* Inc. # of context switches to this task */ + 1015d2c: d0e76517 ldw r3,-25196(gp) + 1015d30: 18800e17 ldw r2,56(r3) + 1015d34: 10800044 addi r2,r2,1 + 1015d38: 18800e15 stw r2,56(r3) +#endif + OSCtxSwCtr++; /* Keep track of the number of ctx switches */ + 1015d3c: d0a76017 ldw r2,-25216(gp) + 1015d40: 10800044 addi r2,r2,1 + 1015d44: d0a76015 stw r2,-25216(gp) + OSIntCtxSw(); /* Perform interrupt level ctx switch */ + 1015d48: 102000c0 call 102000c + 1015d4c: e0bfff17 ldw r2,-4(fp) + 1015d50: e0bffd15 stw r2,-12(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1015d54: e0bffd17 ldw r2,-12(fp) + 1015d58: 1001703a wrctl status,r2 + } + } + } + OS_EXIT_CRITICAL(); + } +} + 1015d5c: e037883a mov sp,fp + 1015d60: dfc00117 ldw ra,4(sp) + 1015d64: df000017 ldw fp,0(sp) + 1015d68: dec00204 addi sp,sp,8 + 1015d6c: f800283a ret + +01015d70 : +********************************************************************************************************* +*/ + +#if OS_SCHED_LOCK_EN > 0 +void OSSchedLock (void) +{ + 1015d70: defffc04 addi sp,sp,-16 + 1015d74: df000315 stw fp,12(sp) + 1015d78: df000304 addi fp,sp,12 +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 1015d7c: e03fff15 stw zero,-4(fp) +#endif + + + + if (OSRunning == OS_TRUE) { /* Make sure multitasking is running */ + 1015d80: d0a75b43 ldbu r2,-25235(gp) + 1015d84: 10803fcc andi r2,r2,255 + 1015d88: 10800058 cmpnei r2,r2,1 + 1015d8c: 1000171e bne r2,zero,1015dec +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1015d90: 0005303a rdctl r2,status + 1015d94: e0bffe15 stw r2,-8(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1015d98: e0fffe17 ldw r3,-8(fp) + 1015d9c: 00bfff84 movi r2,-2 + 1015da0: 1884703a and r2,r3,r2 + 1015da4: 1001703a wrctl status,r2 + + return context; + 1015da8: e0bffe17 ldw r2,-8(fp) + OS_ENTER_CRITICAL(); + 1015dac: e0bfff15 stw r2,-4(fp) + if (OSIntNesting == 0) { /* Can't call from an ISR */ + 1015db0: d0a76903 ldbu r2,-25180(gp) + 1015db4: 10803fcc andi r2,r2,255 + 1015db8: 1004c03a cmpne r2,r2,zero + 1015dbc: 1000071e bne r2,zero,1015ddc + if (OSLockNesting < 255u) { /* Prevent OSLockNesting from wrapping back to 0 */ + 1015dc0: d0a75b03 ldbu r2,-25236(gp) + 1015dc4: 10803fcc andi r2,r2,255 + 1015dc8: 10803fe0 cmpeqi r2,r2,255 + 1015dcc: 1000031e bne r2,zero,1015ddc + OSLockNesting++; /* Increment lock nesting level */ + 1015dd0: d0a75b03 ldbu r2,-25236(gp) + 1015dd4: 10800044 addi r2,r2,1 + 1015dd8: d0a75b05 stb r2,-25236(gp) + 1015ddc: e0bfff17 ldw r2,-4(fp) + 1015de0: e0bffd15 stw r2,-12(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1015de4: e0bffd17 ldw r2,-12(fp) + 1015de8: 1001703a wrctl status,r2 + } + } + OS_EXIT_CRITICAL(); + } +} + 1015dec: e037883a mov sp,fp + 1015df0: df000017 ldw fp,0(sp) + 1015df4: dec00104 addi sp,sp,4 + 1015df8: f800283a ret + +01015dfc : +********************************************************************************************************* +*/ + +#if OS_SCHED_LOCK_EN > 0 +void OSSchedUnlock (void) +{ + 1015dfc: defff804 addi sp,sp,-32 + 1015e00: dfc00715 stw ra,28(sp) + 1015e04: df000615 stw fp,24(sp) + 1015e08: df000604 addi fp,sp,24 +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 1015e0c: e03fff15 stw zero,-4(fp) +#endif + + + + if (OSRunning == OS_TRUE) { /* Make sure multitasking is running */ + 1015e10: d0a75b43 ldbu r2,-25235(gp) + 1015e14: 10803fcc andi r2,r2,255 + 1015e18: 10800058 cmpnei r2,r2,1 + 1015e1c: 10002b1e bne r2,zero,1015ecc +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1015e20: 0005303a rdctl r2,status + 1015e24: e0bffe15 stw r2,-8(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1015e28: e0fffe17 ldw r3,-8(fp) + 1015e2c: 00bfff84 movi r2,-2 + 1015e30: 1884703a and r2,r3,r2 + 1015e34: 1001703a wrctl status,r2 + + return context; + 1015e38: e0bffe17 ldw r2,-8(fp) + OS_ENTER_CRITICAL(); + 1015e3c: e0bfff15 stw r2,-4(fp) + if (OSLockNesting > 0) { /* Do not decrement if already 0 */ + 1015e40: d0a75b03 ldbu r2,-25236(gp) + 1015e44: 10803fcc andi r2,r2,255 + 1015e48: 1005003a cmpeq r2,r2,zero + 1015e4c: 10001b1e bne r2,zero,1015ebc + OSLockNesting--; /* Decrement lock nesting level */ + 1015e50: d0a75b03 ldbu r2,-25236(gp) + 1015e54: 10bfffc4 addi r2,r2,-1 + 1015e58: d0a75b05 stb r2,-25236(gp) + if (OSLockNesting == 0) { /* See if scheduler is enabled and ... */ + 1015e5c: d0a75b03 ldbu r2,-25236(gp) + 1015e60: 10803fcc andi r2,r2,255 + 1015e64: 1004c03a cmpne r2,r2,zero + 1015e68: 10000f1e bne r2,zero,1015ea8 + if (OSIntNesting == 0) { /* ... not in an ISR */ + 1015e6c: d0a76903 ldbu r2,-25180(gp) + 1015e70: 10803fcc andi r2,r2,255 + 1015e74: 1004c03a cmpne r2,r2,zero + 1015e78: 1000061e bne r2,zero,1015e94 + 1015e7c: e0bfff17 ldw r2,-4(fp) + 1015e80: e0bffd15 stw r2,-12(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1015e84: e0bffd17 ldw r2,-12(fp) + 1015e88: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + OS_Sched(); /* See if a HPT is ready */ + 1015e8c: 1016cb80 call 1016cb8 + 1015e90: 00000e06 br 1015ecc + 1015e94: e0bfff17 ldw r2,-4(fp) + 1015e98: e0bffc15 stw r2,-16(fp) + 1015e9c: e0bffc17 ldw r2,-16(fp) + 1015ea0: 1001703a wrctl status,r2 + 1015ea4: 00000906 br 1015ecc + 1015ea8: e0bfff17 ldw r2,-4(fp) + 1015eac: e0bffb15 stw r2,-20(fp) + 1015eb0: e0bffb17 ldw r2,-20(fp) + 1015eb4: 1001703a wrctl status,r2 + 1015eb8: 00000406 br 1015ecc + 1015ebc: e0bfff17 ldw r2,-4(fp) + 1015ec0: e0bffa15 stw r2,-24(fp) + 1015ec4: e0bffa17 ldw r2,-24(fp) + 1015ec8: 1001703a wrctl status,r2 + } + } else { + OS_EXIT_CRITICAL(); + } + } +} + 1015ecc: e037883a mov sp,fp + 1015ed0: dfc00117 ldw ra,4(sp) + 1015ed4: df000017 ldw fp,0(sp) + 1015ed8: dec00204 addi sp,sp,8 + 1015edc: f800283a ret + +01015ee0 : +* d_ Execute the task. +********************************************************************************************************* +*/ + +void OSStart (void) +{ + 1015ee0: defffe04 addi sp,sp,-8 + 1015ee4: dfc00115 stw ra,4(sp) + 1015ee8: df000015 stw fp,0(sp) + 1015eec: d839883a mov fp,sp + if (OSRunning == OS_FALSE) { + 1015ef0: d0a75b43 ldbu r2,-25235(gp) + 1015ef4: 10803fcc andi r2,r2,255 + 1015ef8: 1004c03a cmpne r2,r2,zero + 1015efc: 10000f1e bne r2,zero,1015f3c + OS_SchedNew(); /* Find highest priority's task priority number */ + 1015f00: 1016d8c0 call 1016d8c + OSPrioCur = OSPrioHighRdy; + 1015f04: d0a75d03 ldbu r2,-25228(gp) + 1015f08: d0a75d45 stb r2,-25227(gp) + OSTCBHighRdy = OSTCBPrioTbl[OSPrioHighRdy]; /* Point to highest priority task ready to run */ + 1015f0c: d0a75d03 ldbu r2,-25228(gp) + 1015f10: 10803fcc andi r2,r2,255 + 1015f14: 00c040f4 movhi r3,259 + 1015f18: 18f3b104 addi r3,r3,-12604 + 1015f1c: 1085883a add r2,r2,r2 + 1015f20: 1085883a add r2,r2,r2 + 1015f24: 10c5883a add r2,r2,r3 + 1015f28: 10800017 ldw r2,0(r2) + 1015f2c: d0a76515 stw r2,-25196(gp) + OSTCBCur = OSTCBHighRdy; + 1015f30: d0a76517 ldw r2,-25196(gp) + 1015f34: d0a76a15 stw r2,-25176(gp) + OSStartHighRdy(); /* Execute target specific code to start task */ + 1015f38: 10200980 call 1020098 + } +} + 1015f3c: e037883a mov sp,fp + 1015f40: dfc00117 ldw ra,4(sp) + 1015f44: df000017 ldw fp,0(sp) + 1015f48: dec00204 addi sp,sp,8 + 1015f4c: f800283a ret + +01015f50 : +********************************************************************************************************* +*/ + +#if OS_TASK_STAT_EN > 0 +void OSStatInit (void) +{ + 1015f50: defff904 addi sp,sp,-28 + 1015f54: dfc00615 stw ra,24(sp) + 1015f58: df000515 stw fp,20(sp) + 1015f5c: df000504 addi fp,sp,20 +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 1015f60: e03fff15 stw zero,-4(fp) +#endif + + + + OSTimeDly(2); /* Synchronize with clock tick */ + 1015f64: 01000084 movi r4,2 + 1015f68: 101cfac0 call 101cfac +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1015f6c: 0005303a rdctl r2,status + 1015f70: e0bffe15 stw r2,-8(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1015f74: e0fffe17 ldw r3,-8(fp) + 1015f78: 00bfff84 movi r2,-2 + 1015f7c: 1884703a and r2,r3,r2 + 1015f80: 1001703a wrctl status,r2 + + return context; + 1015f84: e0bffe17 ldw r2,-8(fp) + OS_ENTER_CRITICAL(); + 1015f88: e0bfff15 stw r2,-4(fp) + OSIdleCtr = 0L; /* Clear idle counter */ + 1015f8c: d0275c15 stw zero,-25232(gp) + 1015f90: e0bfff17 ldw r2,-4(fp) + 1015f94: e0bffd15 stw r2,-12(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1015f98: e0bffd17 ldw r2,-12(fp) + 1015f9c: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + OSTimeDly(OS_TICKS_PER_SEC / 10); /* Determine MAX. idle counter value for 1/10 second */ + 1015fa0: 01001904 movi r4,100 + 1015fa4: 101cfac0 call 101cfac +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1015fa8: 0005303a rdctl r2,status + 1015fac: e0bffc15 stw r2,-16(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1015fb0: e0fffc17 ldw r3,-16(fp) + 1015fb4: 00bfff84 movi r2,-2 + 1015fb8: 1884703a and r2,r3,r2 + 1015fbc: 1001703a wrctl status,r2 + + return context; + 1015fc0: e0bffc17 ldw r2,-16(fp) + OS_ENTER_CRITICAL(); + 1015fc4: e0bfff15 stw r2,-4(fp) + OSIdleCtrMax = OSIdleCtr; /* Store maximum idle counter count in 1/10 second */ + 1015fc8: d0a75c17 ldw r2,-25232(gp) + 1015fcc: d0a76115 stw r2,-25212(gp) + OSStatRdy = OS_TRUE; + 1015fd0: 00800044 movi r2,1 + 1015fd4: d0a76d05 stb r2,-25164(gp) + 1015fd8: e0bfff17 ldw r2,-4(fp) + 1015fdc: e0bffb15 stw r2,-20(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1015fe0: e0bffb17 ldw r2,-20(fp) + 1015fe4: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); +} + 1015fe8: e037883a mov sp,fp + 1015fec: dfc00117 ldw ra,4(sp) + 1015ff0: df000017 ldw fp,0(sp) + 1015ff4: dec00204 addi sp,sp,8 + 1015ff8: f800283a ret + +01015ffc : +* Returns : none +********************************************************************************************************* +*/ + +void OSTimeTick (void) +{ + 1015ffc: defff604 addi sp,sp,-40 + 1016000: dfc00915 stw ra,36(sp) + 1016004: df000815 stw fp,32(sp) + 1016008: df000804 addi fp,sp,32 + OS_TCB *ptcb; +#if OS_TICK_STEP_EN > 0 + BOOLEAN step; +#endif +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 101600c: e03ffc15 stw zero,-16(fp) +#endif + + + +#if OS_TIME_TICK_HOOK_EN > 0 + OSTimeTickHook(); /* Call user definable hook */ + 1016010: 10204640 call 1020464 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1016014: 0005303a rdctl r2,status + 1016018: e0bffb15 stw r2,-20(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 101601c: e0fffb17 ldw r3,-20(fp) + 1016020: 00bfff84 movi r2,-2 + 1016024: 1884703a and r2,r3,r2 + 1016028: 1001703a wrctl status,r2 + + return context; + 101602c: e0bffb17 ldw r2,-20(fp) +#endif +#if OS_TIME_GET_SET_EN > 0 + OS_ENTER_CRITICAL(); /* Update the 32-bit tick counter */ + 1016030: e0bffc15 stw r2,-16(fp) + OSTime++; + 1016034: d0a76b17 ldw r2,-25172(gp) + 1016038: 10800044 addi r2,r2,1 + 101603c: d0a76b15 stw r2,-25172(gp) + 1016040: e0bffc17 ldw r2,-16(fp) + 1016044: e0bffa15 stw r2,-24(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1016048: e0bffa17 ldw r2,-24(fp) + 101604c: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); +#endif + if (OSRunning == OS_TRUE) { + 1016050: d0a75b43 ldbu r2,-25235(gp) + 1016054: 10803fcc andi r2,r2,255 + 1016058: 10800058 cmpnei r2,r2,1 + 101605c: 1000721e bne r2,zero,1016228 +#if OS_TICK_STEP_EN > 0 + switch (OSTickStepState) { /* Determine whether we need to process a tick */ + 1016060: d0a75f03 ldbu r2,-25220(gp) + 1016064: 10803fcc andi r2,r2,255 + 1016068: e0bfff15 stw r2,-4(fp) + 101606c: e0ffff17 ldw r3,-4(fp) + 1016070: 18800060 cmpeqi r2,r3,1 + 1016074: 10000a1e bne r2,zero,10160a0 + 1016078: e0ffff17 ldw r3,-4(fp) + 101607c: 188000a0 cmpeqi r2,r3,2 + 1016080: 1000091e bne r2,zero,10160a8 + 1016084: e0ffff17 ldw r3,-4(fp) + 1016088: 1805003a cmpeq r2,r3,zero + 101608c: 1000011e bne r2,zero,1016094 + 1016090: 00000a06 br 10160bc + case OS_TICK_STEP_DIS: /* Yes, stepping is disabled */ + step = OS_TRUE; + 1016094: 00800044 movi r2,1 + 1016098: e0bffd05 stb r2,-12(fp) + break; + 101609c: 00000a06 br 10160c8 + + case OS_TICK_STEP_WAIT: /* No, waiting for uC/OS-View to set ... */ + step = OS_FALSE; /* .. OSTickStepState to OS_TICK_STEP_ONCE */ + 10160a0: e03ffd05 stb zero,-12(fp) + break; + 10160a4: 00000806 br 10160c8 + + case OS_TICK_STEP_ONCE: /* Yes, process tick once and wait for next ... */ + step = OS_TRUE; /* ... step command from uC/OS-View */ + 10160a8: 00800044 movi r2,1 + 10160ac: e0bffd05 stb r2,-12(fp) + OSTickStepState = OS_TICK_STEP_WAIT; + 10160b0: 00800044 movi r2,1 + 10160b4: d0a75f05 stb r2,-25220(gp) + break; + 10160b8: 00000306 br 10160c8 + + default: /* Invalid case, correct situation */ + step = OS_TRUE; + 10160bc: 00800044 movi r2,1 + 10160c0: e0bffd05 stb r2,-12(fp) + OSTickStepState = OS_TICK_STEP_DIS; + 10160c4: d0275f05 stb zero,-25220(gp) + break; + } + if (step == OS_FALSE) { /* Return if waiting for step command */ + 10160c8: e0bffd03 ldbu r2,-12(fp) + 10160cc: 1005003a cmpeq r2,r2,zero + 10160d0: 1000551e bne r2,zero,1016228 + return; + } +#endif + ptcb = OSTCBList; /* Point at first TCB in TCB list */ + 10160d4: d0a75e17 ldw r2,-25224(gp) + 10160d8: e0bffe15 stw r2,-8(fp) + while (ptcb->OSTCBPrio != OS_TASK_IDLE_PRIO) { /* Go through all TCBs in TCB list */ + 10160dc: 00004d06 br 1016214 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 10160e0: 0005303a rdctl r2,status + 10160e4: e0bff915 stw r2,-28(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 10160e8: e0fff917 ldw r3,-28(fp) + 10160ec: 00bfff84 movi r2,-2 + 10160f0: 1884703a and r2,r3,r2 + 10160f4: 1001703a wrctl status,r2 + + return context; + 10160f8: e0bff917 ldw r2,-28(fp) + OS_ENTER_CRITICAL(); + 10160fc: e0bffc15 stw r2,-16(fp) + if (ptcb->OSTCBDly != 0) { /* No, Delayed or waiting for event with TO */ + 1016100: e0bffe17 ldw r2,-8(fp) + 1016104: 10800b8b ldhu r2,46(r2) + 1016108: 10bfffcc andi r2,r2,65535 + 101610c: 1005003a cmpeq r2,r2,zero + 1016110: 1000391e bne r2,zero,10161f8 + if (--ptcb->OSTCBDly == 0) { /* Decrement nbr of ticks to end of delay */ + 1016114: e0bffe17 ldw r2,-8(fp) + 1016118: 10800b8b ldhu r2,46(r2) + 101611c: 10bfffc4 addi r2,r2,-1 + 1016120: 1007883a mov r3,r2 + 1016124: e0bffe17 ldw r2,-8(fp) + 1016128: 10c00b8d sth r3,46(r2) + 101612c: e0bffe17 ldw r2,-8(fp) + 1016130: 10800b8b ldhu r2,46(r2) + 1016134: 10bfffcc andi r2,r2,65535 + 1016138: 1004c03a cmpne r2,r2,zero + 101613c: 10002e1e bne r2,zero,10161f8 + /* Check for timeout */ + if ((ptcb->OSTCBStat & OS_STAT_PEND_ANY) != OS_STAT_RDY) { + 1016140: e0bffe17 ldw r2,-8(fp) + 1016144: 10800c03 ldbu r2,48(r2) + 1016148: 10803fcc andi r2,r2,255 + 101614c: 10800dcc andi r2,r2,55 + 1016150: 1005003a cmpeq r2,r2,zero + 1016154: 10000b1e bne r2,zero,1016184 + ptcb->OSTCBStat &= ~(INT8U)OS_STAT_PEND_ANY; /* Yes, Clear status flag */ + 1016158: e0bffe17 ldw r2,-8(fp) + 101615c: 10c00c03 ldbu r3,48(r2) + 1016160: 00bff204 movi r2,-56 + 1016164: 1884703a and r2,r3,r2 + 1016168: 1007883a mov r3,r2 + 101616c: e0bffe17 ldw r2,-8(fp) + 1016170: 10c00c05 stb r3,48(r2) + ptcb->OSTCBStatPend = OS_STAT_PEND_TO; /* Indicate PEND timeout */ + 1016174: e0fffe17 ldw r3,-8(fp) + 1016178: 00800044 movi r2,1 + 101617c: 18800c45 stb r2,49(r3) + 1016180: 00000206 br 101618c + } else { + ptcb->OSTCBStatPend = OS_STAT_PEND_OK; + 1016184: e0bffe17 ldw r2,-8(fp) + 1016188: 10000c45 stb zero,49(r2) + } + + if ((ptcb->OSTCBStat & OS_STAT_SUSPEND) == OS_STAT_RDY) { /* Is task suspended? */ + 101618c: e0bffe17 ldw r2,-8(fp) + 1016190: 10800c03 ldbu r2,48(r2) + 1016194: 10803fcc andi r2,r2,255 + 1016198: 1080020c andi r2,r2,8 + 101619c: 1004c03a cmpne r2,r2,zero + 10161a0: 1000151e bne r2,zero,10161f8 + OSRdyGrp |= ptcb->OSTCBBitY; /* No, Make ready */ + 10161a4: e0bffe17 ldw r2,-8(fp) + 10161a8: 10c00d83 ldbu r3,54(r2) + 10161ac: d0a76703 ldbu r2,-25188(gp) + 10161b0: 1884b03a or r2,r3,r2 + 10161b4: d0a76705 stb r2,-25188(gp) + OSRdyTbl[ptcb->OSTCBY] |= ptcb->OSTCBBitX; + 10161b8: e0bffe17 ldw r2,-8(fp) + 10161bc: 10800d03 ldbu r2,52(r2) + 10161c0: 11003fcc andi r4,r2,255 + 10161c4: e0bffe17 ldw r2,-8(fp) + 10161c8: 10800d03 ldbu r2,52(r2) + 10161cc: 10c03fcc andi r3,r2,255 + 10161d0: d0a76744 addi r2,gp,-25187 + 10161d4: 1885883a add r2,r3,r2 + 10161d8: 10c00003 ldbu r3,0(r2) + 10161dc: e0bffe17 ldw r2,-8(fp) + 10161e0: 10800d43 ldbu r2,53(r2) + 10161e4: 1884b03a or r2,r3,r2 + 10161e8: 1007883a mov r3,r2 + 10161ec: d0a76744 addi r2,gp,-25187 + 10161f0: 2085883a add r2,r4,r2 + 10161f4: 10c00005 stb r3,0(r2) + } + } + } + ptcb = ptcb->OSTCBNext; /* Point at next TCB in TCB list */ + 10161f8: e0bffe17 ldw r2,-8(fp) + 10161fc: 10800517 ldw r2,20(r2) + 1016200: e0bffe15 stw r2,-8(fp) + 1016204: e0bffc17 ldw r2,-16(fp) + 1016208: e0bff815 stw r2,-32(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 101620c: e0bff817 ldw r2,-32(fp) + 1016210: 1001703a wrctl status,r2 + if (step == OS_FALSE) { /* Return if waiting for step command */ + return; + } +#endif + ptcb = OSTCBList; /* Point at first TCB in TCB list */ + while (ptcb->OSTCBPrio != OS_TASK_IDLE_PRIO) { /* Go through all TCBs in TCB list */ + 1016214: e0bffe17 ldw r2,-8(fp) + 1016218: 10800c83 ldbu r2,50(r2) + 101621c: 10803fcc andi r2,r2,255 + 1016220: 10800518 cmpnei r2,r2,20 + 1016224: 103fae1e bne r2,zero,10160e0 + } + ptcb = ptcb->OSTCBNext; /* Point at next TCB in TCB list */ + OS_EXIT_CRITICAL(); + } + } +} + 1016228: e037883a mov sp,fp + 101622c: dfc00117 ldw ra,4(sp) + 1016230: df000017 ldw fp,0(sp) + 1016234: dec00204 addi sp,sp,8 + 1016238: f800283a ret + +0101623c : +* Returns : the version number of uC/OS-II multiplied by 100. +********************************************************************************************************* +*/ + +INT16U OSVersion (void) +{ + 101623c: deffff04 addi sp,sp,-4 + 1016240: df000015 stw fp,0(sp) + 1016244: d839883a mov fp,sp + return (OS_VERSION); + 1016248: 00804784 movi r2,286 +} + 101624c: e037883a mov sp,fp + 1016250: df000017 ldw fp,0(sp) + 1016254: dec00104 addi sp,sp,4 + 1016258: f800283a ret + +0101625c : +********************************************************************************************************* +*/ + +#if OS_TASK_DEL_EN > 0 +void OS_Dummy (void) +{ + 101625c: deffff04 addi sp,sp,-4 + 1016260: df000015 stw fp,0(sp) + 1016264: d839883a mov fp,sp +} + 1016268: e037883a mov sp,fp + 101626c: df000017 ldw fp,0(sp) + 1016270: dec00104 addi sp,sp,4 + 1016274: f800283a ret + +01016278 : +* Note : This function is INTERNAL to uC/OS-II and your application should not call it. +********************************************************************************************************* +*/ +#if (OS_EVENT_EN) +INT8U OS_EventTaskRdy (OS_EVENT *pevent, void *pmsg, INT8U msk, INT8U pend_stat) +{ + 1016278: defff804 addi sp,sp,-32 + 101627c: dfc00715 stw ra,28(sp) + 1016280: df000615 stw fp,24(sp) + 1016284: df000604 addi fp,sp,24 + 1016288: e13ffc15 stw r4,-16(fp) + 101628c: e17ffd15 stw r5,-12(fp) + 1016290: e1bffe05 stb r6,-8(fp) + 1016294: e1ffff05 stb r7,-4(fp) + INT16U *ptbl; +#endif + + +#if OS_LOWEST_PRIO <= 63 + y = OSUnMapTbl[pevent->OSEventGrp]; /* Find HPT waiting for message */ + 1016298: e0bffc17 ldw r2,-16(fp) + 101629c: 10800283 ldbu r2,10(r2) + 10162a0: 10c03fcc andi r3,r2,255 + 10162a4: 008040b4 movhi r2,258 + 10162a8: 10869a04 addi r2,r2,6760 + 10162ac: 10c5883a add r2,r2,r3 + 10162b0: 10800003 ldbu r2,0(r2) + 10162b4: e0bffa85 stb r2,-22(fp) + x = OSUnMapTbl[pevent->OSEventTbl[y]]; + 10162b8: e0fffa83 ldbu r3,-22(fp) + 10162bc: e0bffc17 ldw r2,-16(fp) + 10162c0: 1885883a add r2,r3,r2 + 10162c4: 10800204 addi r2,r2,8 + 10162c8: 108000c3 ldbu r2,3(r2) + 10162cc: 10c03fcc andi r3,r2,255 + 10162d0: 008040b4 movhi r2,258 + 10162d4: 10869a04 addi r2,r2,6760 + 10162d8: 10c5883a add r2,r2,r3 + 10162dc: 10800003 ldbu r2,0(r2) + 10162e0: e0bffa45 stb r2,-23(fp) + prio = (INT8U)((y << 3) + x); /* Find priority of task getting the msg */ + 10162e4: e0bffa83 ldbu r2,-22(fp) + 10162e8: 100490fa slli r2,r2,3 + 10162ec: 1007883a mov r3,r2 + 10162f0: e0bffa43 ldbu r2,-23(fp) + 10162f4: 1885883a add r2,r3,r2 + 10162f8: e0bffa05 stb r2,-24(fp) + x = OSUnMapTbl[(*ptbl >> 8) & 0xFF] + 8; + } + prio = (INT8U)((y << 4) + x); /* Find priority of task getting the msg */ +#endif + + ptcb = OSTCBPrioTbl[prio]; /* Point to this task's OS_TCB */ + 10162fc: e0bffa03 ldbu r2,-24(fp) + 1016300: 00c040f4 movhi r3,259 + 1016304: 18f3b104 addi r3,r3,-12604 + 1016308: 1085883a add r2,r2,r2 + 101630c: 1085883a add r2,r2,r2 + 1016310: 10c5883a add r2,r2,r3 + 1016314: 10800017 ldw r2,0(r2) + 1016318: e0bffb15 stw r2,-20(fp) + ptcb->OSTCBDly = 0; /* Prevent OSTimeTick() from readying task */ + 101631c: e0bffb17 ldw r2,-20(fp) + 1016320: 10000b8d sth zero,46(r2) +#if ((OS_Q_EN > 0) && (OS_MAX_QS > 0)) || (OS_MBOX_EN > 0) + ptcb->OSTCBMsg = pmsg; /* Send message directly to waiting task */ + 1016324: e0fffb17 ldw r3,-20(fp) + 1016328: e0bffd17 ldw r2,-12(fp) + 101632c: 18800915 stw r2,36(r3) +#else + pmsg = pmsg; /* Prevent compiler warning if not used */ +#endif + ptcb->OSTCBStat &= ~msk; /* Clear bit associated with event type */ + 1016330: e0bffb17 ldw r2,-20(fp) + 1016334: 10800c03 ldbu r2,48(r2) + 1016338: 1007883a mov r3,r2 + 101633c: e0bffe03 ldbu r2,-8(fp) + 1016340: 0084303a nor r2,zero,r2 + 1016344: 1884703a and r2,r3,r2 + 1016348: 1007883a mov r3,r2 + 101634c: e0bffb17 ldw r2,-20(fp) + 1016350: 10c00c05 stb r3,48(r2) + ptcb->OSTCBStatPend = pend_stat; /* Set pend status of post or abort */ + 1016354: e0fffb17 ldw r3,-20(fp) + 1016358: e0bfff03 ldbu r2,-4(fp) + 101635c: 18800c45 stb r2,49(r3) + /* See if task is ready (could be susp'd) */ + if ((ptcb->OSTCBStat & OS_STAT_SUSPEND) == OS_STAT_RDY) { + 1016360: e0bffb17 ldw r2,-20(fp) + 1016364: 10800c03 ldbu r2,48(r2) + 1016368: 10803fcc andi r2,r2,255 + 101636c: 1080020c andi r2,r2,8 + 1016370: 1004c03a cmpne r2,r2,zero + 1016374: 1000111e bne r2,zero,10163bc + OSRdyGrp |= ptcb->OSTCBBitY; /* Put task in the ready to run list */ + 1016378: e0bffb17 ldw r2,-20(fp) + 101637c: 10c00d83 ldbu r3,54(r2) + 1016380: d0a76703 ldbu r2,-25188(gp) + 1016384: 1884b03a or r2,r3,r2 + 1016388: d0a76705 stb r2,-25188(gp) + OSRdyTbl[y] |= ptcb->OSTCBBitX; + 101638c: e13ffa83 ldbu r4,-22(fp) + 1016390: e0fffa83 ldbu r3,-22(fp) + 1016394: d0a76744 addi r2,gp,-25187 + 1016398: 1885883a add r2,r3,r2 + 101639c: 10c00003 ldbu r3,0(r2) + 10163a0: e0bffb17 ldw r2,-20(fp) + 10163a4: 10800d43 ldbu r2,53(r2) + 10163a8: 1884b03a or r2,r3,r2 + 10163ac: 1007883a mov r3,r2 + 10163b0: d0a76744 addi r2,gp,-25187 + 10163b4: 2085883a add r2,r4,r2 + 10163b8: 10c00005 stb r3,0(r2) + } + + OS_EventTaskRemove(ptcb, pevent); /* Remove this task from event wait list */ + 10163bc: e13ffb17 ldw r4,-20(fp) + 10163c0: e17ffc17 ldw r5,-16(fp) + 10163c4: 10166700 call 1016670 +#if (OS_EVENT_MULTI_EN > 0) + if (ptcb->OSTCBEventMultiPtr != (OS_EVENT **)0) { /* Remove this task from events' wait lists */ + 10163c8: e0bffb17 ldw r2,-20(fp) + 10163cc: 10800817 ldw r2,32(r2) + 10163d0: 1005003a cmpeq r2,r2,zero + 10163d4: 1000071e bne r2,zero,10163f4 + OS_EventTaskRemoveMulti(ptcb, ptcb->OSTCBEventMultiPtr); + 10163d8: e0bffb17 ldw r2,-20(fp) + 10163dc: 11400817 ldw r5,32(r2) + 10163e0: e13ffb17 ldw r4,-20(fp) + 10163e4: 10167280 call 1016728 + ptcb->OSTCBEventPtr = (OS_EVENT *)pevent;/* Return event as first multi-pend event ready*/ + 10163e8: e0fffb17 ldw r3,-20(fp) + 10163ec: e0bffc17 ldw r2,-16(fp) + 10163f0: 18800715 stw r2,28(r3) + } +#endif + + return (prio); + 10163f4: e0bffa03 ldbu r2,-24(fp) +} + 10163f8: e037883a mov sp,fp + 10163fc: dfc00117 ldw ra,4(sp) + 1016400: df000017 ldw fp,0(sp) + 1016404: dec00204 addi sp,sp,8 + 1016408: f800283a ret + +0101640c : +* Note : This function is INTERNAL to uC/OS-II and your application should not call it. +********************************************************************************************************* +*/ +#if (OS_EVENT_EN) +void OS_EventTaskWait (OS_EVENT *pevent) +{ + 101640c: defffd04 addi sp,sp,-12 + 1016410: df000215 stw fp,8(sp) + 1016414: df000204 addi fp,sp,8 + 1016418: e13fff15 stw r4,-4(fp) + INT8U y; + + + OSTCBCur->OSTCBEventPtr = pevent; /* Store ptr to ECB in TCB */ + 101641c: d0e76a17 ldw r3,-25176(gp) + 1016420: e0bfff17 ldw r2,-4(fp) + 1016424: 18800715 stw r2,28(r3) + + pevent->OSEventTbl[OSTCBCur->OSTCBY] |= OSTCBCur->OSTCBBitX; /* Put task in waiting list */ + 1016428: d0a76a17 ldw r2,-25176(gp) + 101642c: 10800d03 ldbu r2,52(r2) + 1016430: 11003fcc andi r4,r2,255 + 1016434: d0a76a17 ldw r2,-25176(gp) + 1016438: 10800d03 ldbu r2,52(r2) + 101643c: 10c03fcc andi r3,r2,255 + 1016440: e0bfff17 ldw r2,-4(fp) + 1016444: 1885883a add r2,r3,r2 + 1016448: 10800204 addi r2,r2,8 + 101644c: 10c000c3 ldbu r3,3(r2) + 1016450: d0a76a17 ldw r2,-25176(gp) + 1016454: 10800d43 ldbu r2,53(r2) + 1016458: 1884b03a or r2,r3,r2 + 101645c: 1007883a mov r3,r2 + 1016460: e0bfff17 ldw r2,-4(fp) + 1016464: 2085883a add r2,r4,r2 + 1016468: 10800204 addi r2,r2,8 + 101646c: 10c000c5 stb r3,3(r2) + pevent->OSEventGrp |= OSTCBCur->OSTCBBitY; + 1016470: e0bfff17 ldw r2,-4(fp) + 1016474: 10c00283 ldbu r3,10(r2) + 1016478: d0a76a17 ldw r2,-25176(gp) + 101647c: 10800d83 ldbu r2,54(r2) + 1016480: 1884b03a or r2,r3,r2 + 1016484: 1007883a mov r3,r2 + 1016488: e0bfff17 ldw r2,-4(fp) + 101648c: 10c00285 stb r3,10(r2) + + y = OSTCBCur->OSTCBY; /* Task no longer ready */ + 1016490: d0a76a17 ldw r2,-25176(gp) + 1016494: 10800d03 ldbu r2,52(r2) + 1016498: e0bffe05 stb r2,-8(fp) + OSRdyTbl[y] &= ~OSTCBCur->OSTCBBitX; + 101649c: e13ffe03 ldbu r4,-8(fp) + 10164a0: e0fffe03 ldbu r3,-8(fp) + 10164a4: d0a76744 addi r2,gp,-25187 + 10164a8: 1885883a add r2,r3,r2 + 10164ac: 10800003 ldbu r2,0(r2) + 10164b0: 1007883a mov r3,r2 + 10164b4: d0a76a17 ldw r2,-25176(gp) + 10164b8: 10800d43 ldbu r2,53(r2) + 10164bc: 0084303a nor r2,zero,r2 + 10164c0: 1884703a and r2,r3,r2 + 10164c4: 1007883a mov r3,r2 + 10164c8: d0a76744 addi r2,gp,-25187 + 10164cc: 2085883a add r2,r4,r2 + 10164d0: 10c00005 stb r3,0(r2) + if (OSRdyTbl[y] == 0) { + 10164d4: e0fffe03 ldbu r3,-8(fp) + 10164d8: d0a76744 addi r2,gp,-25187 + 10164dc: 1885883a add r2,r3,r2 + 10164e0: 10800003 ldbu r2,0(r2) + 10164e4: 10803fcc andi r2,r2,255 + 10164e8: 1004c03a cmpne r2,r2,zero + 10164ec: 1000071e bne r2,zero,101650c + OSRdyGrp &= ~OSTCBCur->OSTCBBitY; /* Clear event grp bit if this was only task pending */ + 10164f0: d0a76a17 ldw r2,-25176(gp) + 10164f4: 10800d83 ldbu r2,54(r2) + 10164f8: 0084303a nor r2,zero,r2 + 10164fc: 1007883a mov r3,r2 + 1016500: d0a76703 ldbu r2,-25188(gp) + 1016504: 1884703a and r2,r3,r2 + 1016508: d0a76705 stb r2,-25188(gp) + } +} + 101650c: e037883a mov sp,fp + 1016510: df000017 ldw fp,0(sp) + 1016514: dec00104 addi sp,sp,4 + 1016518: f800283a ret + +0101651c : +* Note : This function is INTERNAL to uC/OS-II and your application should not call it. +********************************************************************************************************* +*/ +#if ((OS_EVENT_EN) && (OS_EVENT_MULTI_EN > 0)) +void OS_EventTaskWaitMulti (OS_EVENT **pevents_wait) +{ + 101651c: defffb04 addi sp,sp,-20 + 1016520: df000415 stw fp,16(sp) + 1016524: df000404 addi fp,sp,16 + 1016528: e13fff15 stw r4,-4(fp) + OS_EVENT **pevents; + OS_EVENT *pevent; + INT8U y; + + + OSTCBCur->OSTCBEventPtr = (OS_EVENT *)0; + 101652c: d0a76a17 ldw r2,-25176(gp) + 1016530: 10000715 stw zero,28(r2) + OSTCBCur->OSTCBEventMultiPtr = (OS_EVENT **)pevents_wait; /* Store ptr to ECBs in TCB */ + 1016534: d0e76a17 ldw r3,-25176(gp) + 1016538: e0bfff17 ldw r2,-4(fp) + 101653c: 18800815 stw r2,32(r3) + + pevents = pevents_wait; + 1016540: e0bfff17 ldw r2,-4(fp) + 1016544: e0bffe15 stw r2,-8(fp) + pevent = *pevents; + 1016548: e0bffe17 ldw r2,-8(fp) + 101654c: 10800017 ldw r2,0(r2) + 1016550: e0bffd15 stw r2,-12(fp) + while (pevent != (OS_EVENT *)0) { /* Put task in waiting lists */ + 1016554: 00002006 br 10165d8 + pevent->OSEventTbl[OSTCBCur->OSTCBY] |= OSTCBCur->OSTCBBitX; + 1016558: d0a76a17 ldw r2,-25176(gp) + 101655c: 10800d03 ldbu r2,52(r2) + 1016560: 11003fcc andi r4,r2,255 + 1016564: d0a76a17 ldw r2,-25176(gp) + 1016568: 10800d03 ldbu r2,52(r2) + 101656c: 10c03fcc andi r3,r2,255 + 1016570: e0bffd17 ldw r2,-12(fp) + 1016574: 1885883a add r2,r3,r2 + 1016578: 10800204 addi r2,r2,8 + 101657c: 10c000c3 ldbu r3,3(r2) + 1016580: d0a76a17 ldw r2,-25176(gp) + 1016584: 10800d43 ldbu r2,53(r2) + 1016588: 1884b03a or r2,r3,r2 + 101658c: 1007883a mov r3,r2 + 1016590: e0bffd17 ldw r2,-12(fp) + 1016594: 2085883a add r2,r4,r2 + 1016598: 10800204 addi r2,r2,8 + 101659c: 10c000c5 stb r3,3(r2) + pevent->OSEventGrp |= OSTCBCur->OSTCBBitY; + 10165a0: e0bffd17 ldw r2,-12(fp) + 10165a4: 10c00283 ldbu r3,10(r2) + 10165a8: d0a76a17 ldw r2,-25176(gp) + 10165ac: 10800d83 ldbu r2,54(r2) + 10165b0: 1884b03a or r2,r3,r2 + 10165b4: 1007883a mov r3,r2 + 10165b8: e0bffd17 ldw r2,-12(fp) + 10165bc: 10c00285 stb r3,10(r2) + pevents++; + 10165c0: e0bffe17 ldw r2,-8(fp) + 10165c4: 10800104 addi r2,r2,4 + 10165c8: e0bffe15 stw r2,-8(fp) + pevent = *pevents; + 10165cc: e0bffe17 ldw r2,-8(fp) + 10165d0: 10800017 ldw r2,0(r2) + 10165d4: e0bffd15 stw r2,-12(fp) + OSTCBCur->OSTCBEventPtr = (OS_EVENT *)0; + OSTCBCur->OSTCBEventMultiPtr = (OS_EVENT **)pevents_wait; /* Store ptr to ECBs in TCB */ + + pevents = pevents_wait; + pevent = *pevents; + while (pevent != (OS_EVENT *)0) { /* Put task in waiting lists */ + 10165d8: e0bffd17 ldw r2,-12(fp) + 10165dc: 1004c03a cmpne r2,r2,zero + 10165e0: 103fdd1e bne r2,zero,1016558 + pevent->OSEventGrp |= OSTCBCur->OSTCBBitY; + pevents++; + pevent = *pevents; + } + + y = OSTCBCur->OSTCBY; /* Task no longer ready */ + 10165e4: d0a76a17 ldw r2,-25176(gp) + 10165e8: 10800d03 ldbu r2,52(r2) + 10165ec: e0bffc05 stb r2,-16(fp) + OSRdyTbl[y] &= ~OSTCBCur->OSTCBBitX; + 10165f0: e13ffc03 ldbu r4,-16(fp) + 10165f4: e0fffc03 ldbu r3,-16(fp) + 10165f8: d0a76744 addi r2,gp,-25187 + 10165fc: 1885883a add r2,r3,r2 + 1016600: 10800003 ldbu r2,0(r2) + 1016604: 1007883a mov r3,r2 + 1016608: d0a76a17 ldw r2,-25176(gp) + 101660c: 10800d43 ldbu r2,53(r2) + 1016610: 0084303a nor r2,zero,r2 + 1016614: 1884703a and r2,r3,r2 + 1016618: 1007883a mov r3,r2 + 101661c: d0a76744 addi r2,gp,-25187 + 1016620: 2085883a add r2,r4,r2 + 1016624: 10c00005 stb r3,0(r2) + if (OSRdyTbl[y] == 0) { + 1016628: e0fffc03 ldbu r3,-16(fp) + 101662c: d0a76744 addi r2,gp,-25187 + 1016630: 1885883a add r2,r3,r2 + 1016634: 10800003 ldbu r2,0(r2) + 1016638: 10803fcc andi r2,r2,255 + 101663c: 1004c03a cmpne r2,r2,zero + 1016640: 1000071e bne r2,zero,1016660 + OSRdyGrp &= ~OSTCBCur->OSTCBBitY; /* Clear event grp bit if this was only task pending */ + 1016644: d0a76a17 ldw r2,-25176(gp) + 1016648: 10800d83 ldbu r2,54(r2) + 101664c: 0084303a nor r2,zero,r2 + 1016650: 1007883a mov r3,r2 + 1016654: d0a76703 ldbu r2,-25188(gp) + 1016658: 1884703a and r2,r3,r2 + 101665c: d0a76705 stb r2,-25188(gp) + } +} + 1016660: e037883a mov sp,fp + 1016664: df000017 ldw fp,0(sp) + 1016668: dec00104 addi sp,sp,4 + 101666c: f800283a ret + +01016670 : +********************************************************************************************************* +*/ +#if (OS_EVENT_EN) +void OS_EventTaskRemove (OS_TCB *ptcb, + OS_EVENT *pevent) +{ + 1016670: defffc04 addi sp,sp,-16 + 1016674: df000315 stw fp,12(sp) + 1016678: df000304 addi fp,sp,12 + 101667c: e13ffe15 stw r4,-8(fp) + 1016680: e17fff15 stw r5,-4(fp) + INT8U y; + + + y = ptcb->OSTCBY; + 1016684: e0bffe17 ldw r2,-8(fp) + 1016688: 10800d03 ldbu r2,52(r2) + 101668c: e0bffd05 stb r2,-12(fp) + pevent->OSEventTbl[y] &= ~ptcb->OSTCBBitX; /* Remove task from wait list */ + 1016690: e13ffd03 ldbu r4,-12(fp) + 1016694: e0fffd03 ldbu r3,-12(fp) + 1016698: e0bfff17 ldw r2,-4(fp) + 101669c: 1885883a add r2,r3,r2 + 10166a0: 10800204 addi r2,r2,8 + 10166a4: 108000c3 ldbu r2,3(r2) + 10166a8: 1007883a mov r3,r2 + 10166ac: e0bffe17 ldw r2,-8(fp) + 10166b0: 10800d43 ldbu r2,53(r2) + 10166b4: 0084303a nor r2,zero,r2 + 10166b8: 1884703a and r2,r3,r2 + 10166bc: 1007883a mov r3,r2 + 10166c0: e0bfff17 ldw r2,-4(fp) + 10166c4: 2085883a add r2,r4,r2 + 10166c8: 10800204 addi r2,r2,8 + 10166cc: 10c000c5 stb r3,3(r2) + if (pevent->OSEventTbl[y] == 0) { + 10166d0: e0fffd03 ldbu r3,-12(fp) + 10166d4: e0bfff17 ldw r2,-4(fp) + 10166d8: 1885883a add r2,r3,r2 + 10166dc: 10800204 addi r2,r2,8 + 10166e0: 108000c3 ldbu r2,3(r2) + 10166e4: 10803fcc andi r2,r2,255 + 10166e8: 1004c03a cmpne r2,r2,zero + 10166ec: 10000a1e bne r2,zero,1016718 + pevent->OSEventGrp &= ~ptcb->OSTCBBitY; + 10166f0: e0bfff17 ldw r2,-4(fp) + 10166f4: 10800283 ldbu r2,10(r2) + 10166f8: 1007883a mov r3,r2 + 10166fc: e0bffe17 ldw r2,-8(fp) + 1016700: 10800d83 ldbu r2,54(r2) + 1016704: 0084303a nor r2,zero,r2 + 1016708: 1884703a and r2,r3,r2 + 101670c: 1007883a mov r3,r2 + 1016710: e0bfff17 ldw r2,-4(fp) + 1016714: 10c00285 stb r3,10(r2) + } +} + 1016718: e037883a mov sp,fp + 101671c: df000017 ldw fp,0(sp) + 1016720: dec00104 addi sp,sp,4 + 1016724: f800283a ret + +01016728 : +********************************************************************************************************* +*/ +#if ((OS_EVENT_EN) && (OS_EVENT_MULTI_EN > 0)) +void OS_EventTaskRemoveMulti (OS_TCB *ptcb, + OS_EVENT **pevents_multi) +{ + 1016728: defffa04 addi sp,sp,-24 + 101672c: df000515 stw fp,20(sp) + 1016730: df000504 addi fp,sp,20 + 1016734: e13ffe15 stw r4,-8(fp) + 1016738: e17fff15 stw r5,-4(fp) + INT16U bity; + INT16U bitx; +#endif + + + y = ptcb->OSTCBY; + 101673c: e0bffe17 ldw r2,-8(fp) + 1016740: 10800d03 ldbu r2,52(r2) + 1016744: e0bffb85 stb r2,-18(fp) + bity = ptcb->OSTCBBitY; + 1016748: e0bffe17 ldw r2,-8(fp) + 101674c: 10800d83 ldbu r2,54(r2) + 1016750: e0bffb45 stb r2,-19(fp) + bitx = ptcb->OSTCBBitX; + 1016754: e0bffe17 ldw r2,-8(fp) + 1016758: 10800d43 ldbu r2,53(r2) + 101675c: e0bffb05 stb r2,-20(fp) + pevents = pevents_multi; + 1016760: e0bfff17 ldw r2,-4(fp) + 1016764: e0bffd15 stw r2,-12(fp) + pevent = *pevents; + 1016768: e0bffd17 ldw r2,-12(fp) + 101676c: 10800017 ldw r2,0(r2) + 1016770: e0bffc15 stw r2,-16(fp) + while (pevent != (OS_EVENT *)0) { /* Remove task from all events' wait lists */ + 1016774: 00002606 br 1016810 + pevent->OSEventTbl[y] &= ~bitx; + 1016778: e13ffb83 ldbu r4,-18(fp) + 101677c: e0fffb83 ldbu r3,-18(fp) + 1016780: e0bffc17 ldw r2,-16(fp) + 1016784: 1885883a add r2,r3,r2 + 1016788: 10800204 addi r2,r2,8 + 101678c: 108000c3 ldbu r2,3(r2) + 1016790: 1007883a mov r3,r2 + 1016794: e0bffb03 ldbu r2,-20(fp) + 1016798: 0084303a nor r2,zero,r2 + 101679c: 1884703a and r2,r3,r2 + 10167a0: 1007883a mov r3,r2 + 10167a4: e0bffc17 ldw r2,-16(fp) + 10167a8: 2085883a add r2,r4,r2 + 10167ac: 10800204 addi r2,r2,8 + 10167b0: 10c000c5 stb r3,3(r2) + if (pevent->OSEventTbl[y] == 0) { + 10167b4: e0fffb83 ldbu r3,-18(fp) + 10167b8: e0bffc17 ldw r2,-16(fp) + 10167bc: 1885883a add r2,r3,r2 + 10167c0: 10800204 addi r2,r2,8 + 10167c4: 108000c3 ldbu r2,3(r2) + 10167c8: 10803fcc andi r2,r2,255 + 10167cc: 1004c03a cmpne r2,r2,zero + 10167d0: 1000091e bne r2,zero,10167f8 + pevent->OSEventGrp &= ~bity; + 10167d4: e0bffc17 ldw r2,-16(fp) + 10167d8: 10800283 ldbu r2,10(r2) + 10167dc: 1007883a mov r3,r2 + 10167e0: e0bffb43 ldbu r2,-19(fp) + 10167e4: 0084303a nor r2,zero,r2 + 10167e8: 1884703a and r2,r3,r2 + 10167ec: 1007883a mov r3,r2 + 10167f0: e0bffc17 ldw r2,-16(fp) + 10167f4: 10c00285 stb r3,10(r2) + } + pevents++; + 10167f8: e0bffd17 ldw r2,-12(fp) + 10167fc: 10800104 addi r2,r2,4 + 1016800: e0bffd15 stw r2,-12(fp) + pevent = *pevents; + 1016804: e0bffd17 ldw r2,-12(fp) + 1016808: 10800017 ldw r2,0(r2) + 101680c: e0bffc15 stw r2,-16(fp) + y = ptcb->OSTCBY; + bity = ptcb->OSTCBBitY; + bitx = ptcb->OSTCBBitX; + pevents = pevents_multi; + pevent = *pevents; + while (pevent != (OS_EVENT *)0) { /* Remove task from all events' wait lists */ + 1016810: e0bffc17 ldw r2,-16(fp) + 1016814: 1004c03a cmpne r2,r2,zero + 1016818: 103fd71e bne r2,zero,1016778 + pevent->OSEventGrp &= ~bity; + } + pevents++; + pevent = *pevents; + } +} + 101681c: e037883a mov sp,fp + 1016820: df000017 ldw fp,0(sp) + 1016824: dec00104 addi sp,sp,4 + 1016828: f800283a ret + +0101682c : +* Note : This function is INTERNAL to uC/OS-II and your application should not call it. +********************************************************************************************************* +*/ +#if (OS_EVENT_EN) +void OS_EventWaitListInit (OS_EVENT *pevent) +{ + 101682c: defffc04 addi sp,sp,-16 + 1016830: df000315 stw fp,12(sp) + 1016834: df000304 addi fp,sp,12 + 1016838: e13fff15 stw r4,-4(fp) + INT16U *ptbl; +#endif + INT8U i; + + + pevent->OSEventGrp = 0; /* No task waiting on event */ + 101683c: e0bfff17 ldw r2,-4(fp) + 1016840: 10000285 stb zero,10(r2) + ptbl = &pevent->OSEventTbl[0]; + 1016844: e0bfff17 ldw r2,-4(fp) + 1016848: 108002c4 addi r2,r2,11 + 101684c: e0bffe15 stw r2,-8(fp) + + for (i = 0; i < OS_EVENT_TBL_SIZE; i++) { + 1016850: e03ffd05 stb zero,-12(fp) + 1016854: 00000806 br 1016878 + *ptbl++ = 0; + 1016858: e0bffe17 ldw r2,-8(fp) + 101685c: 10000005 stb zero,0(r2) + 1016860: e0bffe17 ldw r2,-8(fp) + 1016864: 10800044 addi r2,r2,1 + 1016868: e0bffe15 stw r2,-8(fp) + + + pevent->OSEventGrp = 0; /* No task waiting on event */ + ptbl = &pevent->OSEventTbl[0]; + + for (i = 0; i < OS_EVENT_TBL_SIZE; i++) { + 101686c: e0bffd03 ldbu r2,-12(fp) + 1016870: 10800044 addi r2,r2,1 + 1016874: e0bffd05 stb r2,-12(fp) + 1016878: e0bffd03 ldbu r2,-12(fp) + 101687c: 108000f0 cmpltui r2,r2,3 + 1016880: 103ff51e bne r2,zero,1016858 + *ptbl++ = 0; + } +} + 1016884: e037883a mov sp,fp + 1016888: df000017 ldw fp,0(sp) + 101688c: dec00104 addi sp,sp,4 + 1016890: f800283a ret + +01016894 : +* Returns : none +********************************************************************************************************* +*/ + +static void OS_InitEventList (void) +{ + 1016894: defffb04 addi sp,sp,-20 + 1016898: dfc00415 stw ra,16(sp) + 101689c: df000315 stw fp,12(sp) + 10168a0: df000304 addi fp,sp,12 + INT16U i; + OS_EVENT *pevent1; + OS_EVENT *pevent2; + + + OS_MemClr((INT8U *)&OSEventTbl[0], sizeof(OSEventTbl)); /* Clear the event table */ + 10168a4: 010040f4 movhi r4,259 + 10168a8: 212f9d04 addi r4,r4,-16780 + 10168ac: 0142d004 movi r5,2880 + 10168b0: 1016bf80 call 1016bf8 + pevent1 = &OSEventTbl[0]; + 10168b4: 008040f4 movhi r2,259 + 10168b8: 10af9d04 addi r2,r2,-16780 + 10168bc: e0bffe15 stw r2,-8(fp) + pevent2 = &OSEventTbl[1]; + 10168c0: 008040f4 movhi r2,259 + 10168c4: 10afa904 addi r2,r2,-16732 + 10168c8: e0bffd15 stw r2,-12(fp) + for (i = 0; i < (OS_MAX_EVENTS - 1); i++) { /* Init. list of free EVENT control blocks */ + 10168cc: e03fff0d sth zero,-4(fp) + 10168d0: 00001306 br 1016920 + pevent1->OSEventType = OS_EVENT_TYPE_UNUSED; + 10168d4: e0bffe17 ldw r2,-8(fp) + 10168d8: 10000005 stb zero,0(r2) + pevent1->OSEventPtr = pevent2; + 10168dc: e0fffe17 ldw r3,-8(fp) + 10168e0: e0bffd17 ldw r2,-12(fp) + 10168e4: 18800115 stw r2,4(r3) +#if OS_EVENT_NAME_SIZE > 1 + pevent1->OSEventName[0] = '?'; /* Unknown name */ + 10168e8: e0fffe17 ldw r3,-8(fp) + 10168ec: 00800fc4 movi r2,63 + 10168f0: 18800385 stb r2,14(r3) + pevent1->OSEventName[1] = OS_ASCII_NUL; + 10168f4: e0bffe17 ldw r2,-8(fp) + 10168f8: 100003c5 stb zero,15(r2) +#endif + pevent1++; + 10168fc: e0bffe17 ldw r2,-8(fp) + 1016900: 10800c04 addi r2,r2,48 + 1016904: e0bffe15 stw r2,-8(fp) + pevent2++; + 1016908: e0bffd17 ldw r2,-12(fp) + 101690c: 10800c04 addi r2,r2,48 + 1016910: e0bffd15 stw r2,-12(fp) + + + OS_MemClr((INT8U *)&OSEventTbl[0], sizeof(OSEventTbl)); /* Clear the event table */ + pevent1 = &OSEventTbl[0]; + pevent2 = &OSEventTbl[1]; + for (i = 0; i < (OS_MAX_EVENTS - 1); i++) { /* Init. list of free EVENT control blocks */ + 1016914: e0bfff0b ldhu r2,-4(fp) + 1016918: 10800044 addi r2,r2,1 + 101691c: e0bfff0d sth r2,-4(fp) + 1016920: e0bfff0b ldhu r2,-4(fp) + 1016924: 10800ef0 cmpltui r2,r2,59 + 1016928: 103fea1e bne r2,zero,10168d4 + pevent1->OSEventName[1] = OS_ASCII_NUL; +#endif + pevent1++; + pevent2++; + } + pevent1->OSEventType = OS_EVENT_TYPE_UNUSED; + 101692c: e0bffe17 ldw r2,-8(fp) + 1016930: 10000005 stb zero,0(r2) + pevent1->OSEventPtr = (OS_EVENT *)0; + 1016934: e0bffe17 ldw r2,-8(fp) + 1016938: 10000115 stw zero,4(r2) +#if OS_EVENT_NAME_SIZE > 1 + pevent1->OSEventName[0] = '?'; + 101693c: e0fffe17 ldw r3,-8(fp) + 1016940: 00800fc4 movi r2,63 + 1016944: 18800385 stb r2,14(r3) + pevent1->OSEventName[1] = OS_ASCII_NUL; + 1016948: e0bffe17 ldw r2,-8(fp) + 101694c: 100003c5 stb zero,15(r2) +#endif + OSEventFreeList = &OSEventTbl[0]; + 1016950: 008040f4 movhi r2,259 + 1016954: 10af9d04 addi r2,r2,-16780 + 1016958: d0a76815 stw r2,-25184(gp) + OSEventFreeList->OSEventName[0] = '?'; /* Unknown name */ + OSEventFreeList->OSEventName[1] = OS_ASCII_NUL; +#endif +#endif +#endif +} + 101695c: e037883a mov sp,fp + 1016960: dfc00117 ldw ra,4(sp) + 1016964: df000017 ldw fp,0(sp) + 1016968: dec00204 addi sp,sp,8 + 101696c: f800283a ret + +01016970 : +* Returns : none +********************************************************************************************************* +*/ + +static void OS_InitMisc (void) +{ + 1016970: deffff04 addi sp,sp,-4 + 1016974: df000015 stw fp,0(sp) + 1016978: d839883a mov fp,sp +#if OS_TIME_GET_SET_EN > 0 + OSTime = 0L; /* Clear the 32-bit system clock */ + 101697c: d0276b15 stw zero,-25172(gp) +#endif + + OSIntNesting = 0; /* Clear the interrupt nesting counter */ + 1016980: d0276905 stb zero,-25180(gp) + OSLockNesting = 0; /* Clear the scheduling lock counter */ + 1016984: d0275b05 stb zero,-25236(gp) + + OSTaskCtr = 0; /* Clear the number of tasks */ + 1016988: d0276345 stb zero,-25203(gp) + + OSRunning = OS_FALSE; /* Indicate that multitasking not started */ + 101698c: d0275b45 stb zero,-25235(gp) + + OSCtxSwCtr = 0; /* Clear the context switch counter */ + 1016990: d0276015 stw zero,-25216(gp) + OSIdleCtr = 0L; /* Clear the 32-bit idle counter */ + 1016994: d0275c15 stw zero,-25232(gp) + +#if OS_TASK_STAT_EN > 0 + OSIdleCtrRun = 0L; + 1016998: d0276e15 stw zero,-25160(gp) + OSIdleCtrMax = 0L; + 101699c: d0276115 stw zero,-25212(gp) + OSStatRdy = OS_FALSE; /* Statistic task is not ready */ + 10169a0: d0276d05 stb zero,-25164(gp) +#endif +} + 10169a4: e037883a mov sp,fp + 10169a8: df000017 ldw fp,0(sp) + 10169ac: dec00104 addi sp,sp,4 + 10169b0: f800283a ret + +010169b4 : +* Returns : none +********************************************************************************************************* +*/ + +static void OS_InitRdyList (void) +{ + 10169b4: defffd04 addi sp,sp,-12 + 10169b8: df000215 stw fp,8(sp) + 10169bc: df000204 addi fp,sp,8 +#else + INT16U *prdytbl; +#endif + + + OSRdyGrp = 0; /* Clear the ready list */ + 10169c0: d0276705 stb zero,-25188(gp) + prdytbl = &OSRdyTbl[0]; + 10169c4: d0a76744 addi r2,gp,-25187 + 10169c8: e0bffe15 stw r2,-8(fp) + for (i = 0; i < OS_RDY_TBL_SIZE; i++) { + 10169cc: e03fff05 stb zero,-4(fp) + 10169d0: 00000806 br 10169f4 + *prdytbl++ = 0; + 10169d4: e0bffe17 ldw r2,-8(fp) + 10169d8: 10000005 stb zero,0(r2) + 10169dc: e0bffe17 ldw r2,-8(fp) + 10169e0: 10800044 addi r2,r2,1 + 10169e4: e0bffe15 stw r2,-8(fp) +#endif + + + OSRdyGrp = 0; /* Clear the ready list */ + prdytbl = &OSRdyTbl[0]; + for (i = 0; i < OS_RDY_TBL_SIZE; i++) { + 10169e8: e0bfff03 ldbu r2,-4(fp) + 10169ec: 10800044 addi r2,r2,1 + 10169f0: e0bfff05 stb r2,-4(fp) + 10169f4: e0bfff03 ldbu r2,-4(fp) + 10169f8: 108000f0 cmpltui r2,r2,3 + 10169fc: 103ff51e bne r2,zero,10169d4 + *prdytbl++ = 0; + } + + OSPrioCur = 0; + 1016a00: d0275d45 stb zero,-25227(gp) + OSPrioHighRdy = 0; + 1016a04: d0275d05 stb zero,-25228(gp) + + OSTCBHighRdy = (OS_TCB *)0; + 1016a08: d0276515 stw zero,-25196(gp) + OSTCBCur = (OS_TCB *)0; + 1016a0c: d0276a15 stw zero,-25176(gp) +} + 1016a10: e037883a mov sp,fp + 1016a14: df000017 ldw fp,0(sp) + 1016a18: dec00104 addi sp,sp,4 + 1016a1c: f800283a ret + +01016a20 : +* Returns : none +********************************************************************************************************* +*/ + +static void OS_InitTaskIdle (void) +{ + 1016a20: defff804 addi sp,sp,-32 + 1016a24: dfc00715 stw ra,28(sp) + 1016a28: df000615 stw fp,24(sp) + 1016a2c: df000604 addi fp,sp,24 +#endif + + +#if OS_TASK_CREATE_EXT_EN > 0 + #if OS_STK_GROWTH == 1 + (void)OSTaskCreateExt(OS_TaskIdle, + 1016a30: 018040f4 movhi r6,259 + 1016a34: 31af9c04 addi r6,r6,-16784 + 1016a38: 00bfffd4 movui r2,65535 + 1016a3c: d8800015 stw r2,0(sp) + 1016a40: 008040f4 movhi r2,259 + 1016a44: 10ad9d04 addi r2,r2,-18828 + 1016a48: d8800115 stw r2,4(sp) + 1016a4c: 00808004 movi r2,512 + 1016a50: d8800215 stw r2,8(sp) + 1016a54: d8000315 stw zero,12(sp) + 1016a58: 008000c4 movi r2,3 + 1016a5c: d8800415 stw r2,16(sp) + 1016a60: 01004074 movhi r4,257 + 1016a64: 211bb504 addi r4,r4,28372 + 1016a68: 000b883a mov r5,zero + 1016a6c: 01c00504 movi r7,20 + 1016a70: 101bcb40 call 101bcb4 + OS_TASK_IDLE_PRIO); + #endif +#endif + +#if OS_TASK_NAME_SIZE > 14 + OSTaskNameSet(OS_TASK_IDLE_PRIO, (INT8U *)"uC/OS-II Idle", &err); + 1016a74: 014040b4 movhi r5,258 + 1016a78: 2946da04 addi r5,r5,7016 + 1016a7c: 01000504 movi r4,20 + 1016a80: e1bfff04 addi r6,fp,-4 + 1016a84: 101c5e80 call 101c5e8 +#else +#if OS_TASK_NAME_SIZE > 7 + OSTaskNameSet(OS_TASK_IDLE_PRIO, (INT8U *)"OS-Idle", &err); +#endif +#endif +} + 1016a88: e037883a mov sp,fp + 1016a8c: dfc00117 ldw ra,4(sp) + 1016a90: df000017 ldw fp,0(sp) + 1016a94: dec00204 addi sp,sp,8 + 1016a98: f800283a ret + +01016a9c : +********************************************************************************************************* +*/ + +#if OS_TASK_STAT_EN > 0 +static void OS_InitTaskStat (void) +{ + 1016a9c: defff804 addi sp,sp,-32 + 1016aa0: dfc00715 stw ra,28(sp) + 1016aa4: df000615 stw fp,24(sp) + 1016aa8: df000604 addi fp,sp,24 +#endif + + +#if OS_TASK_CREATE_EXT_EN > 0 + #if OS_STK_GROWTH == 1 + (void)OSTaskCreateExt(OS_TaskStat, + 1016aac: 018040f4 movhi r6,259 + 1016ab0: 31ad2404 addi r6,r6,-19312 + 1016ab4: 00bfff94 movui r2,65534 + 1016ab8: d8800015 stw r2,0(sp) + 1016abc: 008040f4 movhi r2,259 + 1016ac0: 10ab2504 addi r2,r2,-21356 + 1016ac4: d8800115 stw r2,4(sp) + 1016ac8: 00808004 movi r2,512 + 1016acc: d8800215 stw r2,8(sp) + 1016ad0: d8000315 stw zero,12(sp) + 1016ad4: 008000c4 movi r2,3 + 1016ad8: d8800415 stw r2,16(sp) + 1016adc: 01004074 movhi r4,257 + 1016ae0: 211bcc04 addi r4,r4,28464 + 1016ae4: 000b883a mov r5,zero + 1016ae8: 01c004c4 movi r7,19 + 1016aec: 101bcb40 call 101bcb4 + OS_TASK_STAT_PRIO); /* One higher than the idle task */ + #endif +#endif + +#if OS_TASK_NAME_SIZE > 14 + OSTaskNameSet(OS_TASK_STAT_PRIO, (INT8U *)"uC/OS-II Stat", &err); + 1016af0: 014040b4 movhi r5,258 + 1016af4: 2946de04 addi r5,r5,7032 + 1016af8: 010004c4 movi r4,19 + 1016afc: e1bfff04 addi r6,fp,-4 + 1016b00: 101c5e80 call 101c5e8 +#else +#if OS_TASK_NAME_SIZE > 7 + OSTaskNameSet(OS_TASK_STAT_PRIO, (INT8U *)"OS-Stat", &err); +#endif +#endif +} + 1016b04: e037883a mov sp,fp + 1016b08: dfc00117 ldw ra,4(sp) + 1016b0c: df000017 ldw fp,0(sp) + 1016b10: dec00204 addi sp,sp,8 + 1016b14: f800283a ret + +01016b18 : +* Returns : none +********************************************************************************************************* +*/ + +static void OS_InitTCBList (void) +{ + 1016b18: defffb04 addi sp,sp,-20 + 1016b1c: dfc00415 stw ra,16(sp) + 1016b20: df000315 stw fp,12(sp) + 1016b24: df000304 addi fp,sp,12 + INT8U i; + OS_TCB *ptcb1; + OS_TCB *ptcb2; + + + OS_MemClr((INT8U *)&OSTCBTbl[0], sizeof(OSTCBTbl)); /* Clear all the TCBs */ + 1016b28: 010040f4 movhi r4,259 + 1016b2c: 21326d04 addi r4,r4,-13900 + 1016b30: 01414404 movi r5,1296 + 1016b34: 1016bf80 call 1016bf8 + OS_MemClr((INT8U *)&OSTCBPrioTbl[0], sizeof(OSTCBPrioTbl)); /* Clear the priority table */ + 1016b38: 010040f4 movhi r4,259 + 1016b3c: 2133b104 addi r4,r4,-12604 + 1016b40: 01401504 movi r5,84 + 1016b44: 1016bf80 call 1016bf8 + ptcb1 = &OSTCBTbl[0]; + 1016b48: 008040f4 movhi r2,259 + 1016b4c: 10b26d04 addi r2,r2,-13900 + 1016b50: e0bffe15 stw r2,-8(fp) + ptcb2 = &OSTCBTbl[1]; + 1016b54: 008040f4 movhi r2,259 + 1016b58: 10b28804 addi r2,r2,-13792 + 1016b5c: e0bffd15 stw r2,-12(fp) + for (i = 0; i < (OS_MAX_TASKS + OS_N_SYS_TASKS - 1); i++) { /* Init. list of free TCBs */ + 1016b60: e03fff05 stb zero,-4(fp) + 1016b64: 00001106 br 1016bac + ptcb1->OSTCBNext = ptcb2; + 1016b68: e0fffe17 ldw r3,-8(fp) + 1016b6c: e0bffd17 ldw r2,-12(fp) + 1016b70: 18800515 stw r2,20(r3) +#if OS_TASK_NAME_SIZE > 1 + ptcb1->OSTCBTaskName[0] = '?'; /* Unknown name */ + 1016b74: e0fffe17 ldw r3,-8(fp) + 1016b78: 00800fc4 movi r2,63 + 1016b7c: 18801305 stb r2,76(r3) + ptcb1->OSTCBTaskName[1] = OS_ASCII_NUL; + 1016b80: e0bffe17 ldw r2,-8(fp) + 1016b84: 10001345 stb zero,77(r2) +#endif + ptcb1++; + 1016b88: e0bffe17 ldw r2,-8(fp) + 1016b8c: 10801b04 addi r2,r2,108 + 1016b90: e0bffe15 stw r2,-8(fp) + ptcb2++; + 1016b94: e0bffd17 ldw r2,-12(fp) + 1016b98: 10801b04 addi r2,r2,108 + 1016b9c: e0bffd15 stw r2,-12(fp) + + OS_MemClr((INT8U *)&OSTCBTbl[0], sizeof(OSTCBTbl)); /* Clear all the TCBs */ + OS_MemClr((INT8U *)&OSTCBPrioTbl[0], sizeof(OSTCBPrioTbl)); /* Clear the priority table */ + ptcb1 = &OSTCBTbl[0]; + ptcb2 = &OSTCBTbl[1]; + for (i = 0; i < (OS_MAX_TASKS + OS_N_SYS_TASKS - 1); i++) { /* Init. list of free TCBs */ + 1016ba0: e0bfff03 ldbu r2,-4(fp) + 1016ba4: 10800044 addi r2,r2,1 + 1016ba8: e0bfff05 stb r2,-4(fp) + 1016bac: e0bfff03 ldbu r2,-4(fp) + 1016bb0: 108002f0 cmpltui r2,r2,11 + 1016bb4: 103fec1e bne r2,zero,1016b68 + ptcb1->OSTCBTaskName[1] = OS_ASCII_NUL; +#endif + ptcb1++; + ptcb2++; + } + ptcb1->OSTCBNext = (OS_TCB *)0; /* Last OS_TCB */ + 1016bb8: e0bffe17 ldw r2,-8(fp) + 1016bbc: 10000515 stw zero,20(r2) +#if OS_TASK_NAME_SIZE > 1 + ptcb1->OSTCBTaskName[0] = '?'; /* Unknown name */ + 1016bc0: e0fffe17 ldw r3,-8(fp) + 1016bc4: 00800fc4 movi r2,63 + 1016bc8: 18801305 stb r2,76(r3) + ptcb1->OSTCBTaskName[1] = OS_ASCII_NUL; + 1016bcc: e0bffe17 ldw r2,-8(fp) + 1016bd0: 10001345 stb zero,77(r2) +#endif + OSTCBList = (OS_TCB *)0; /* TCB lists initializations */ + 1016bd4: d0275e15 stw zero,-25224(gp) + OSTCBFreeList = &OSTCBTbl[0]; + 1016bd8: 008040f4 movhi r2,259 + 1016bdc: 10b26d04 addi r2,r2,-13900 + 1016be0: d0a76215 stw r2,-25208(gp) +} + 1016be4: e037883a mov sp,fp + 1016be8: dfc00117 ldw ra,4(sp) + 1016bec: df000017 ldw fp,0(sp) + 1016bf0: dec00204 addi sp,sp,8 + 1016bf4: f800283a ret + +01016bf8 : +* of the alignment of the destination. +********************************************************************************************************* +*/ + +void OS_MemClr (INT8U *pdest, INT16U size) +{ + 1016bf8: defffd04 addi sp,sp,-12 + 1016bfc: df000215 stw fp,8(sp) + 1016c00: df000204 addi fp,sp,8 + 1016c04: e13ffe15 stw r4,-8(fp) + 1016c08: e17fff0d sth r5,-4(fp) + while (size > 0) { + 1016c0c: 00000806 br 1016c30 + *pdest++ = (INT8U)0; + 1016c10: e0bffe17 ldw r2,-8(fp) + 1016c14: 10000005 stb zero,0(r2) + 1016c18: e0bffe17 ldw r2,-8(fp) + 1016c1c: 10800044 addi r2,r2,1 + 1016c20: e0bffe15 stw r2,-8(fp) + size--; + 1016c24: e0bfff0b ldhu r2,-4(fp) + 1016c28: 10bfffc4 addi r2,r2,-1 + 1016c2c: e0bfff0d sth r2,-4(fp) +********************************************************************************************************* +*/ + +void OS_MemClr (INT8U *pdest, INT16U size) +{ + while (size > 0) { + 1016c30: e0bfff0b ldhu r2,-4(fp) + 1016c34: 1004c03a cmpne r2,r2,zero + 1016c38: 103ff51e bne r2,zero,1016c10 + *pdest++ = (INT8U)0; + size--; + } +} + 1016c3c: e037883a mov sp,fp + 1016c40: df000017 ldw fp,0(sp) + 1016c44: dec00104 addi sp,sp,4 + 1016c48: f800283a ret + +01016c4c : +* of the alignment of the source and destination. +********************************************************************************************************* +*/ + +void OS_MemCopy (INT8U *pdest, INT8U *psrc, INT16U size) +{ + 1016c4c: defffc04 addi sp,sp,-16 + 1016c50: df000315 stw fp,12(sp) + 1016c54: df000304 addi fp,sp,12 + 1016c58: e13ffd15 stw r4,-12(fp) + 1016c5c: e17ffe15 stw r5,-8(fp) + 1016c60: e1bfff0d sth r6,-4(fp) + while (size > 0) { + 1016c64: 00000d06 br 1016c9c + *pdest++ = *psrc++; + 1016c68: e0bffe17 ldw r2,-8(fp) + 1016c6c: 10c00003 ldbu r3,0(r2) + 1016c70: e0bffd17 ldw r2,-12(fp) + 1016c74: 10c00005 stb r3,0(r2) + 1016c78: e0bffd17 ldw r2,-12(fp) + 1016c7c: 10800044 addi r2,r2,1 + 1016c80: e0bffd15 stw r2,-12(fp) + 1016c84: e0bffe17 ldw r2,-8(fp) + 1016c88: 10800044 addi r2,r2,1 + 1016c8c: e0bffe15 stw r2,-8(fp) + size--; + 1016c90: e0bfff0b ldhu r2,-4(fp) + 1016c94: 10bfffc4 addi r2,r2,-1 + 1016c98: e0bfff0d sth r2,-4(fp) +********************************************************************************************************* +*/ + +void OS_MemCopy (INT8U *pdest, INT8U *psrc, INT16U size) +{ + while (size > 0) { + 1016c9c: e0bfff0b ldhu r2,-4(fp) + 1016ca0: 1004c03a cmpne r2,r2,zero + 1016ca4: 103ff01e bne r2,zero,1016c68 + *pdest++ = *psrc++; + size--; + } +} + 1016ca8: e037883a mov sp,fp + 1016cac: df000017 ldw fp,0(sp) + 1016cb0: dec00104 addi sp,sp,4 + 1016cb4: f800283a ret + +01016cb8 : +* 2) Rescheduling is prevented when the scheduler is locked (see OS_SchedLock()) +********************************************************************************************************* +*/ + +void OS_Sched (void) +{ + 1016cb8: defffb04 addi sp,sp,-20 + 1016cbc: dfc00415 stw ra,16(sp) + 1016cc0: df000315 stw fp,12(sp) + 1016cc4: df000304 addi fp,sp,12 +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 1016cc8: e03fff15 stw zero,-4(fp) +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1016ccc: 0005303a rdctl r2,status + 1016cd0: e0bffe15 stw r2,-8(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1016cd4: e0fffe17 ldw r3,-8(fp) + 1016cd8: 00bfff84 movi r2,-2 + 1016cdc: 1884703a and r2,r3,r2 + 1016ce0: 1001703a wrctl status,r2 + + return context; + 1016ce4: e0bffe17 ldw r2,-8(fp) +#endif + + + + OS_ENTER_CRITICAL(); + 1016ce8: e0bfff15 stw r2,-4(fp) + if (OSIntNesting == 0) { /* Schedule only if all ISRs done and ... */ + 1016cec: d0a76903 ldbu r2,-25180(gp) + 1016cf0: 10803fcc andi r2,r2,255 + 1016cf4: 1004c03a cmpne r2,r2,zero + 1016cf8: 10001b1e bne r2,zero,1016d68 + if (OSLockNesting == 0) { /* ... scheduler is not locked */ + 1016cfc: d0a75b03 ldbu r2,-25236(gp) + 1016d00: 10803fcc andi r2,r2,255 + 1016d04: 1004c03a cmpne r2,r2,zero + 1016d08: 1000171e bne r2,zero,1016d68 + OS_SchedNew(); + 1016d0c: 1016d8c0 call 1016d8c + if (OSPrioHighRdy != OSPrioCur) { /* No Ctx Sw if current task is highest rdy */ + 1016d10: d0a75d03 ldbu r2,-25228(gp) + 1016d14: d0e75d43 ldbu r3,-25227(gp) + 1016d18: 11003fcc andi r4,r2,255 + 1016d1c: 18803fcc andi r2,r3,255 + 1016d20: 20801126 beq r4,r2,1016d68 + OSTCBHighRdy = OSTCBPrioTbl[OSPrioHighRdy]; + 1016d24: d0a75d03 ldbu r2,-25228(gp) + 1016d28: 10803fcc andi r2,r2,255 + 1016d2c: 00c040f4 movhi r3,259 + 1016d30: 18f3b104 addi r3,r3,-12604 + 1016d34: 1085883a add r2,r2,r2 + 1016d38: 1085883a add r2,r2,r2 + 1016d3c: 10c5883a add r2,r2,r3 + 1016d40: 10800017 ldw r2,0(r2) + 1016d44: d0a76515 stw r2,-25196(gp) +#if OS_TASK_PROFILE_EN > 0 + OSTCBHighRdy->OSTCBCtxSwCtr++; /* Inc. # of context switches to this task */ + 1016d48: d0e76517 ldw r3,-25196(gp) + 1016d4c: 18800e17 ldw r2,56(r3) + 1016d50: 10800044 addi r2,r2,1 + 1016d54: 18800e15 stw r2,56(r3) +#endif + OSCtxSwCtr++; /* Increment context switch counter */ + 1016d58: d0a76017 ldw r2,-25216(gp) + 1016d5c: 10800044 addi r2,r2,1 + 1016d60: d0a76015 stw r2,-25216(gp) + OS_TASK_SW(); /* Perform a context switch */ + 1016d64: 102000c0 call 102000c + 1016d68: e0bfff17 ldw r2,-4(fp) + 1016d6c: e0bffd15 stw r2,-12(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1016d70: e0bffd17 ldw r2,-12(fp) + 1016d74: 1001703a wrctl status,r2 + } + } + } + OS_EXIT_CRITICAL(); +} + 1016d78: e037883a mov sp,fp + 1016d7c: dfc00117 ldw ra,4(sp) + 1016d80: df000017 ldw fp,0(sp) + 1016d84: dec00204 addi sp,sp,8 + 1016d88: f800283a ret + +01016d8c : +* 2) Interrupts are assumed to be disabled when this function is called. +********************************************************************************************************* +*/ + +static void OS_SchedNew (void) +{ + 1016d8c: defffe04 addi sp,sp,-8 + 1016d90: df000115 stw fp,4(sp) + 1016d94: df000104 addi fp,sp,4 +#if OS_LOWEST_PRIO <= 63 /* See if we support up to 64 tasks */ + INT8U y; + + + y = OSUnMapTbl[OSRdyGrp]; + 1016d98: d0a76703 ldbu r2,-25188(gp) + 1016d9c: 10c03fcc andi r3,r2,255 + 1016da0: 008040b4 movhi r2,258 + 1016da4: 10869a04 addi r2,r2,6760 + 1016da8: 10c5883a add r2,r2,r3 + 1016dac: 10800003 ldbu r2,0(r2) + 1016db0: e0bfff05 stb r2,-4(fp) + OSPrioHighRdy = (INT8U)((y << 3) + OSUnMapTbl[OSRdyTbl[y]]); + 1016db4: e0bfff03 ldbu r2,-4(fp) + 1016db8: 100490fa slli r2,r2,3 + 1016dbc: 1009883a mov r4,r2 + 1016dc0: e0ffff03 ldbu r3,-4(fp) + 1016dc4: d0a76744 addi r2,gp,-25187 + 1016dc8: 1885883a add r2,r3,r2 + 1016dcc: 10800003 ldbu r2,0(r2) + 1016dd0: 10c03fcc andi r3,r2,255 + 1016dd4: 008040b4 movhi r2,258 + 1016dd8: 10869a04 addi r2,r2,6760 + 1016ddc: 10c5883a add r2,r2,r3 + 1016de0: 10800003 ldbu r2,0(r2) + 1016de4: 2085883a add r2,r4,r2 + 1016de8: d0a75d05 stb r2,-25228(gp) + OSPrioHighRdy = (INT8U)((y << 4) + OSUnMapTbl[(*ptbl & 0xFF)]); + } else { + OSPrioHighRdy = (INT8U)((y << 4) + OSUnMapTbl[(*ptbl >> 8) & 0xFF] + 8); + } +#endif +} + 1016dec: e037883a mov sp,fp + 1016df0: df000017 ldw fp,0(sp) + 1016df4: dec00104 addi sp,sp,4 + 1016df8: f800283a ret + +01016dfc : +********************************************************************************************************* +*/ + +#if (OS_EVENT_NAME_SIZE > 1) || (OS_FLAG_NAME_SIZE > 1) || (OS_MEM_NAME_SIZE > 1) || (OS_TASK_NAME_SIZE > 1) || (OS_TMR_CFG_NAME_SIZE > 1) +INT8U OS_StrCopy (INT8U *pdest, INT8U *psrc) +{ + 1016dfc: defffc04 addi sp,sp,-16 + 1016e00: df000315 stw fp,12(sp) + 1016e04: df000304 addi fp,sp,12 + 1016e08: e13ffe15 stw r4,-8(fp) + 1016e0c: e17fff15 stw r5,-4(fp) + INT8U len; + + + len = 0; + 1016e10: e03ffd05 stb zero,-12(fp) + while (*psrc != OS_ASCII_NUL) { + 1016e14: 00000d06 br 1016e4c + *pdest++ = *psrc++; + 1016e18: e0bfff17 ldw r2,-4(fp) + 1016e1c: 10c00003 ldbu r3,0(r2) + 1016e20: e0bffe17 ldw r2,-8(fp) + 1016e24: 10c00005 stb r3,0(r2) + 1016e28: e0bffe17 ldw r2,-8(fp) + 1016e2c: 10800044 addi r2,r2,1 + 1016e30: e0bffe15 stw r2,-8(fp) + 1016e34: e0bfff17 ldw r2,-4(fp) + 1016e38: 10800044 addi r2,r2,1 + 1016e3c: e0bfff15 stw r2,-4(fp) + len++; + 1016e40: e0bffd03 ldbu r2,-12(fp) + 1016e44: 10800044 addi r2,r2,1 + 1016e48: e0bffd05 stb r2,-12(fp) +{ + INT8U len; + + + len = 0; + while (*psrc != OS_ASCII_NUL) { + 1016e4c: e0bfff17 ldw r2,-4(fp) + 1016e50: 10800003 ldbu r2,0(r2) + 1016e54: 10803fcc andi r2,r2,255 + 1016e58: 1004c03a cmpne r2,r2,zero + 1016e5c: 103fee1e bne r2,zero,1016e18 + *pdest++ = *psrc++; + len++; + } + *pdest = OS_ASCII_NUL; + 1016e60: e0bffe17 ldw r2,-8(fp) + 1016e64: 10000005 stb zero,0(r2) + return (len); + 1016e68: e0bffd03 ldbu r2,-12(fp) +} + 1016e6c: e037883a mov sp,fp + 1016e70: df000017 ldw fp,0(sp) + 1016e74: dec00104 addi sp,sp,4 + 1016e78: f800283a ret + +01016e7c : +********************************************************************************************************* +*/ + +#if (OS_EVENT_NAME_SIZE > 1) || (OS_FLAG_NAME_SIZE > 1) || (OS_MEM_NAME_SIZE > 1) || (OS_TASK_NAME_SIZE > 1) || (OS_TMR_CFG_NAME_SIZE > 1) +INT8U OS_StrLen (INT8U *psrc) +{ + 1016e7c: defffd04 addi sp,sp,-12 + 1016e80: df000215 stw fp,8(sp) + 1016e84: df000204 addi fp,sp,8 + 1016e88: e13fff15 stw r4,-4(fp) + INT8U len; + + + len = 0; + 1016e8c: e03ffe05 stb zero,-8(fp) + while (*psrc != OS_ASCII_NUL) { + 1016e90: 00000606 br 1016eac + psrc++; + 1016e94: e0bfff17 ldw r2,-4(fp) + 1016e98: 10800044 addi r2,r2,1 + 1016e9c: e0bfff15 stw r2,-4(fp) + len++; + 1016ea0: e0bffe03 ldbu r2,-8(fp) + 1016ea4: 10800044 addi r2,r2,1 + 1016ea8: e0bffe05 stb r2,-8(fp) +{ + INT8U len; + + + len = 0; + while (*psrc != OS_ASCII_NUL) { + 1016eac: e0bfff17 ldw r2,-4(fp) + 1016eb0: 10800003 ldbu r2,0(r2) + 1016eb4: 10803fcc andi r2,r2,255 + 1016eb8: 1004c03a cmpne r2,r2,zero + 1016ebc: 103ff51e bne r2,zero,1016e94 + psrc++; + len++; + } + return (len); + 1016ec0: e0bffe03 ldbu r2,-8(fp) +} + 1016ec4: e037883a mov sp,fp + 1016ec8: df000017 ldw fp,0(sp) + 1016ecc: dec00104 addi sp,sp,4 + 1016ed0: f800283a ret + +01016ed4 : +* power. +********************************************************************************************************* +*/ + +void OS_TaskIdle (void *p_arg) +{ + 1016ed4: defffa04 addi sp,sp,-24 + 1016ed8: dfc00515 stw ra,20(sp) + 1016edc: df000415 stw fp,16(sp) + 1016ee0: df000404 addi fp,sp,16 + 1016ee4: e13fff15 stw r4,-4(fp) +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 1016ee8: e03ffe15 stw zero,-8(fp) +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1016eec: 0005303a rdctl r2,status + 1016ef0: e0bffd15 stw r2,-12(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1016ef4: e0fffd17 ldw r3,-12(fp) + 1016ef8: 00bfff84 movi r2,-2 + 1016efc: 1884703a and r2,r3,r2 + 1016f00: 1001703a wrctl status,r2 + + return context; + 1016f04: e0bffd17 ldw r2,-12(fp) + + + + (void)p_arg; /* Prevent compiler warning for not using 'p_arg' */ + for (;;) { + OS_ENTER_CRITICAL(); + 1016f08: e0bffe15 stw r2,-8(fp) + OSIdleCtr++; + 1016f0c: d0a75c17 ldw r2,-25232(gp) + 1016f10: 10800044 addi r2,r2,1 + 1016f14: d0a75c15 stw r2,-25232(gp) + 1016f18: e0bffe17 ldw r2,-8(fp) + 1016f1c: e0bffc15 stw r2,-16(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1016f20: e0bffc17 ldw r2,-16(fp) + 1016f24: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + OSTaskIdleHook(); /* Call user definable HOOK */ + 1016f28: 10204b80 call 10204b8 + } + 1016f2c: 003fef06 br 1016eec + +01016f30 : +********************************************************************************************************* +*/ + +#if OS_TASK_STAT_EN > 0 +void OS_TaskStat (void *p_arg) +{ + 1016f30: defffa04 addi sp,sp,-24 + 1016f34: dfc00515 stw ra,20(sp) + 1016f38: df000415 stw fp,16(sp) + 1016f3c: df000404 addi fp,sp,16 + 1016f40: e13fff15 stw r4,-4(fp) +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 1016f44: e03ffe15 stw zero,-8(fp) +#endif + + + + (void)p_arg; /* Prevent compiler warning for not using 'p_arg' */ + while (OSStatRdy == OS_FALSE) { + 1016f48: 00000206 br 1016f54 + OSTimeDly(2 * OS_TICKS_PER_SEC / 10); /* Wait until statistic task is ready */ + 1016f4c: 01003204 movi r4,200 + 1016f50: 101cfac0 call 101cfac +#endif + + + + (void)p_arg; /* Prevent compiler warning for not using 'p_arg' */ + while (OSStatRdy == OS_FALSE) { + 1016f54: d0a76d03 ldbu r2,-25164(gp) + 1016f58: 10803fcc andi r2,r2,255 + 1016f5c: 1005003a cmpeq r2,r2,zero + 1016f60: 103ffa1e bne r2,zero,1016f4c + OSTimeDly(2 * OS_TICKS_PER_SEC / 10); /* Wait until statistic task is ready */ + } + OSIdleCtrMax /= 100L; + 1016f64: d1276117 ldw r4,-25212(gp) + 1016f68: 01401904 movi r5,100 + 1016f6c: 1013c340 call 1013c34 <__udivsi3> + 1016f70: d0a76115 stw r2,-25212(gp) + if (OSIdleCtrMax == 0L) { + 1016f74: d0a76117 ldw r2,-25212(gp) + 1016f78: 1004c03a cmpne r2,r2,zero + 1016f7c: 1000031e bne r2,zero,1016f8c + OSCPUUsage = 0; + 1016f80: d0276305 stb zero,-25204(gp) + (void)OSTaskSuspend(OS_PRIO_SELF); + 1016f84: 01003fc4 movi r4,255 + 1016f88: 101cbc00 call 101cbc0 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1016f8c: 0005303a rdctl r2,status + 1016f90: e0bffd15 stw r2,-12(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1016f94: e0fffd17 ldw r3,-12(fp) + 1016f98: 00bfff84 movi r2,-2 + 1016f9c: 1884703a and r2,r3,r2 + 1016fa0: 1001703a wrctl status,r2 + + return context; + 1016fa4: e0bffd17 ldw r2,-12(fp) + } + for (;;) { + OS_ENTER_CRITICAL(); + 1016fa8: e0bffe15 stw r2,-8(fp) + OSIdleCtrRun = OSIdleCtr; /* Obtain the of the idle counter for the past second */ + 1016fac: d0a75c17 ldw r2,-25232(gp) + 1016fb0: d0a76e15 stw r2,-25160(gp) + OSIdleCtr = 0L; /* Reset the idle counter for the next second */ + 1016fb4: d0275c15 stw zero,-25232(gp) + 1016fb8: e0bffe17 ldw r2,-8(fp) + 1016fbc: e0bffc15 stw r2,-16(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1016fc0: e0bffc17 ldw r2,-16(fp) + 1016fc4: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + OSCPUUsage = (INT8U)(100L - OSIdleCtrRun / OSIdleCtrMax); + 1016fc8: d1276e17 ldw r4,-25160(gp) + 1016fcc: d1676117 ldw r5,-25212(gp) + 1016fd0: 1013c340 call 1013c34 <__udivsi3> + 1016fd4: 1007883a mov r3,r2 + 1016fd8: 00801904 movi r2,100 + 1016fdc: 10c5c83a sub r2,r2,r3 + 1016fe0: d0a76305 stb r2,-25204(gp) + OSTaskStatHook(); /* Invoke user definable hook */ + 1016fe4: 10204480 call 1020448 +#if (OS_TASK_STAT_STK_CHK_EN > 0) && (OS_TASK_CREATE_EXT_EN > 0) + OS_TaskStatStkChk(); /* Check the stacks for each task */ + 1016fe8: 1016ff80 call 1016ff8 +#endif + OSTimeDly(OS_TICKS_PER_SEC / 10); /* Accumulate OSIdleCtr for the next 1/10 second */ + 1016fec: 01001904 movi r4,100 + 1016ff0: 101cfac0 call 101cfac + } + 1016ff4: 003fe506 br 1016f8c + +01016ff8 : +********************************************************************************************************* +*/ + +#if (OS_TASK_STAT_STK_CHK_EN > 0) && (OS_TASK_CREATE_EXT_EN > 0) +void OS_TaskStatStkChk (void) +{ + 1016ff8: defffa04 addi sp,sp,-24 + 1016ffc: dfc00515 stw ra,20(sp) + 1017000: df000415 stw fp,16(sp) + 1017004: df000404 addi fp,sp,16 + OS_STK_DATA stk_data; + INT8U err; + INT8U prio; + + + for (prio = 0; prio <= OS_TASK_IDLE_PRIO; prio++) { + 1017008: e03ffc05 stb zero,-16(fp) + 101700c: 00002406 br 10170a0 + err = OSTaskStkChk(prio, &stk_data); + 1017010: e13ffc03 ldbu r4,-16(fp) + 1017014: e17ffe04 addi r5,fp,-8 + 1017018: 101c9c40 call 101c9c4 + 101701c: e0bffc45 stb r2,-15(fp) + if (err == OS_ERR_NONE) { + 1017020: e0bffc43 ldbu r2,-15(fp) + 1017024: 1004c03a cmpne r2,r2,zero + 1017028: 10001a1e bne r2,zero,1017094 + ptcb = OSTCBPrioTbl[prio]; + 101702c: e0bffc03 ldbu r2,-16(fp) + 1017030: 00c040f4 movhi r3,259 + 1017034: 18f3b104 addi r3,r3,-12604 + 1017038: 1085883a add r2,r2,r2 + 101703c: 1085883a add r2,r2,r2 + 1017040: 10c5883a add r2,r2,r3 + 1017044: 10800017 ldw r2,0(r2) + 1017048: e0bffd15 stw r2,-12(fp) + if (ptcb != (OS_TCB *)0) { /* Make sure task 'ptcb' is ... */ + 101704c: e0bffd17 ldw r2,-12(fp) + 1017050: 1005003a cmpeq r2,r2,zero + 1017054: 10000f1e bne r2,zero,1017094 + if (ptcb != OS_TCB_RESERVED) { /* ... still valid. */ + 1017058: e0bffd17 ldw r2,-12(fp) + 101705c: 10800060 cmpeqi r2,r2,1 + 1017060: 10000c1e bne r2,zero,1017094 +#if OS_TASK_PROFILE_EN > 0 + #if OS_STK_GROWTH == 1 + ptcb->OSTCBStkBase = ptcb->OSTCBStkBottom + ptcb->OSTCBStkSize; + 1017064: e0bffd17 ldw r2,-12(fp) + 1017068: 10c00217 ldw r3,8(r2) + 101706c: e0bffd17 ldw r2,-12(fp) + 1017070: 10800317 ldw r2,12(r2) + 1017074: 1085883a add r2,r2,r2 + 1017078: 1085883a add r2,r2,r2 + 101707c: 1887883a add r3,r3,r2 + 1017080: e0bffd17 ldw r2,-12(fp) + 1017084: 10c01115 stw r3,68(r2) + #else + ptcb->OSTCBStkBase = ptcb->OSTCBStkBottom - ptcb->OSTCBStkSize; + #endif + ptcb->OSTCBStkUsed = stk_data.OSUsed; /* Store the number of bytes used */ + 1017088: e0ffff17 ldw r3,-4(fp) + 101708c: e0bffd17 ldw r2,-12(fp) + 1017090: 10c01215 stw r3,72(r2) + OS_STK_DATA stk_data; + INT8U err; + INT8U prio; + + + for (prio = 0; prio <= OS_TASK_IDLE_PRIO; prio++) { + 1017094: e0bffc03 ldbu r2,-16(fp) + 1017098: 10800044 addi r2,r2,1 + 101709c: e0bffc05 stb r2,-16(fp) + 10170a0: e0bffc03 ldbu r2,-16(fp) + 10170a4: 10800570 cmpltui r2,r2,21 + 10170a8: 103fd91e bne r2,zero,1017010 +#endif + } + } + } + } +} + 10170ac: e037883a mov sp,fp + 10170b0: dfc00117 ldw ra,4(sp) + 10170b4: df000017 ldw fp,0(sp) + 10170b8: dec00204 addi sp,sp,8 + 10170bc: f800283a ret + +010170c0 : +* Note : This function is INTERNAL to uC/OS-II and your application should not call it. +********************************************************************************************************* +*/ + +INT8U OS_TCBInit (INT8U prio, OS_STK *ptos, OS_STK *pbos, INT16U id, INT32U stk_size, void *pext, INT16U opt) +{ + 10170c0: defff104 addi sp,sp,-60 + 10170c4: dfc00e15 stw ra,56(sp) + 10170c8: df000d15 stw fp,52(sp) + 10170cc: df000d04 addi fp,sp,52 + 10170d0: e17ffb15 stw r5,-20(fp) + 10170d4: e1bffc15 stw r6,-16(fp) + 10170d8: e0800417 ldw r2,16(fp) + 10170dc: e13ffa05 stb r4,-24(fp) + 10170e0: e1fffd0d sth r7,-12(fp) + 10170e4: e0bffe0d sth r2,-8(fp) + OS_TCB *ptcb; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 10170e8: e03ff815 stw zero,-32(fp) +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 10170ec: 0005303a rdctl r2,status + 10170f0: e0bff715 stw r2,-36(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 10170f4: e0fff717 ldw r3,-36(fp) + 10170f8: 00bfff84 movi r2,-2 + 10170fc: 1884703a and r2,r3,r2 + 1017100: 1001703a wrctl status,r2 + + return context; + 1017104: e0bff717 ldw r2,-36(fp) +#endif + + + + OS_ENTER_CRITICAL(); + 1017108: e0bff815 stw r2,-32(fp) + ptcb = OSTCBFreeList; /* Get a free TCB from the free TCB list */ + 101710c: d0a76217 ldw r2,-25208(gp) + 1017110: e0bff915 stw r2,-28(fp) + if (ptcb != (OS_TCB *)0) { + 1017114: e0bff917 ldw r2,-28(fp) + 1017118: 1005003a cmpeq r2,r2,zero + 101711c: 1000941e bne r2,zero,1017370 + OSTCBFreeList = ptcb->OSTCBNext; /* Update pointer to free TCB list */ + 1017120: e0bff917 ldw r2,-28(fp) + 1017124: 10800517 ldw r2,20(r2) + 1017128: d0a76215 stw r2,-25208(gp) + 101712c: e0bff817 ldw r2,-32(fp) + 1017130: e0bff615 stw r2,-40(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1017134: e0bff617 ldw r2,-40(fp) + 1017138: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + ptcb->OSTCBStkPtr = ptos; /* Load Stack pointer in TCB */ + 101713c: e0fff917 ldw r3,-28(fp) + 1017140: e0bffb17 ldw r2,-20(fp) + 1017144: 18800015 stw r2,0(r3) + ptcb->OSTCBPrio = prio; /* Load task priority into TCB */ + 1017148: e0fff917 ldw r3,-28(fp) + 101714c: e0bffa03 ldbu r2,-24(fp) + 1017150: 18800c85 stb r2,50(r3) + ptcb->OSTCBStat = OS_STAT_RDY; /* Task is ready to run */ + 1017154: e0bff917 ldw r2,-28(fp) + 1017158: 10000c05 stb zero,48(r2) + ptcb->OSTCBStatPend = OS_STAT_PEND_OK; /* Clear pend status */ + 101715c: e0bff917 ldw r2,-28(fp) + 1017160: 10000c45 stb zero,49(r2) + ptcb->OSTCBDly = 0; /* Task is not delayed */ + 1017164: e0bff917 ldw r2,-28(fp) + 1017168: 10000b8d sth zero,46(r2) + +#if OS_TASK_CREATE_EXT_EN > 0 + ptcb->OSTCBExtPtr = pext; /* Store pointer to TCB extension */ + 101716c: e0fff917 ldw r3,-28(fp) + 1017170: e0800317 ldw r2,12(fp) + 1017174: 18800115 stw r2,4(r3) + ptcb->OSTCBStkSize = stk_size; /* Store stack size */ + 1017178: e0fff917 ldw r3,-28(fp) + 101717c: e0800217 ldw r2,8(fp) + 1017180: 18800315 stw r2,12(r3) + ptcb->OSTCBStkBottom = pbos; /* Store pointer to bottom of stack */ + 1017184: e0fff917 ldw r3,-28(fp) + 1017188: e0bffc17 ldw r2,-16(fp) + 101718c: 18800215 stw r2,8(r3) + ptcb->OSTCBOpt = opt; /* Store task options */ + 1017190: e0fff917 ldw r3,-28(fp) + 1017194: e0bffe0b ldhu r2,-8(fp) + 1017198: 1880040d sth r2,16(r3) + ptcb->OSTCBId = id; /* Store task ID */ + 101719c: e0fff917 ldw r3,-28(fp) + 10171a0: e0bffd0b ldhu r2,-12(fp) + 10171a4: 1880048d sth r2,18(r3) + opt = opt; + id = id; +#endif + +#if OS_TASK_DEL_EN > 0 + ptcb->OSTCBDelReq = OS_ERR_NONE; + 10171a8: e0bff917 ldw r2,-28(fp) + 10171ac: 10000dc5 stb zero,55(r2) +#endif + +#if OS_LOWEST_PRIO <= 63 + ptcb->OSTCBY = (INT8U)(prio >> 3); /* Pre-compute X, Y, BitX and BitY */ + 10171b0: e0bffa03 ldbu r2,-24(fp) + 10171b4: 1004d0fa srli r2,r2,3 + 10171b8: 1007883a mov r3,r2 + 10171bc: e0bff917 ldw r2,-28(fp) + 10171c0: 10c00d05 stb r3,52(r2) + ptcb->OSTCBX = (INT8U)(prio & 0x07); + 10171c4: e0bffa03 ldbu r2,-24(fp) + 10171c8: 108001cc andi r2,r2,7 + 10171cc: 1007883a mov r3,r2 + 10171d0: e0bff917 ldw r2,-28(fp) + 10171d4: 10c00cc5 stb r3,51(r2) + ptcb->OSTCBBitY = (INT8U)(1 << ptcb->OSTCBY); + 10171d8: e0bff917 ldw r2,-28(fp) + 10171dc: 10800d03 ldbu r2,52(r2) + 10171e0: 10c03fcc andi r3,r2,255 + 10171e4: 00800044 movi r2,1 + 10171e8: 10c4983a sll r2,r2,r3 + 10171ec: 1007883a mov r3,r2 + 10171f0: e0bff917 ldw r2,-28(fp) + 10171f4: 10c00d85 stb r3,54(r2) + ptcb->OSTCBBitX = (INT8U)(1 << ptcb->OSTCBX); + 10171f8: e0bff917 ldw r2,-28(fp) + 10171fc: 10800cc3 ldbu r2,51(r2) + 1017200: 10c03fcc andi r3,r2,255 + 1017204: 00800044 movi r2,1 + 1017208: 10c4983a sll r2,r2,r3 + 101720c: 1007883a mov r3,r2 + 1017210: e0bff917 ldw r2,-28(fp) + 1017214: 10c00d45 stb r3,53(r2) + ptcb->OSTCBBitY = (INT16U)(1 << ptcb->OSTCBY); + ptcb->OSTCBBitX = (INT16U)(1 << ptcb->OSTCBX); +#endif + +#if (OS_EVENT_EN) + ptcb->OSTCBEventPtr = (OS_EVENT *)0; /* Task is not pending on an event */ + 1017218: e0bff917 ldw r2,-28(fp) + 101721c: 10000715 stw zero,28(r2) +#if (OS_EVENT_MULTI_EN > 0) + ptcb->OSTCBEventMultiPtr = (OS_EVENT **)0; /* Task is not pending on any events */ + 1017220: e0bff917 ldw r2,-28(fp) + 1017224: 10000815 stw zero,32(r2) +#endif +#endif + +#if (OS_FLAG_EN > 0) && (OS_MAX_FLAGS > 0) && (OS_TASK_DEL_EN > 0) + ptcb->OSTCBFlagNode = (OS_FLAG_NODE *)0; /* Task is not pending on an event flag */ + 1017228: e0bff917 ldw r2,-28(fp) + 101722c: 10000a15 stw zero,40(r2) +#endif + +#if (OS_MBOX_EN > 0) || ((OS_Q_EN > 0) && (OS_MAX_QS > 0)) + ptcb->OSTCBMsg = (void *)0; /* No message received */ + 1017230: e0bff917 ldw r2,-28(fp) + 1017234: 10000915 stw zero,36(r2) +#endif + +#if OS_TASK_PROFILE_EN > 0 + ptcb->OSTCBCtxSwCtr = 0L; /* Initialize profiling variables */ + 1017238: e0bff917 ldw r2,-28(fp) + 101723c: 10000e15 stw zero,56(r2) + ptcb->OSTCBCyclesStart = 0L; + 1017240: e0bff917 ldw r2,-28(fp) + 1017244: 10001015 stw zero,64(r2) + ptcb->OSTCBCyclesTot = 0L; + 1017248: e0bff917 ldw r2,-28(fp) + 101724c: 10000f15 stw zero,60(r2) + ptcb->OSTCBStkBase = (OS_STK *)0; + 1017250: e0bff917 ldw r2,-28(fp) + 1017254: 10001115 stw zero,68(r2) + ptcb->OSTCBStkUsed = 0L; + 1017258: e0bff917 ldw r2,-28(fp) + 101725c: 10001215 stw zero,72(r2) +#endif + +#if OS_TASK_NAME_SIZE > 1 + ptcb->OSTCBTaskName[0] = '?'; /* Unknown name at task creation */ + 1017260: e0fff917 ldw r3,-28(fp) + 1017264: 00800fc4 movi r2,63 + 1017268: 18801305 stb r2,76(r3) + ptcb->OSTCBTaskName[1] = OS_ASCII_NUL; + 101726c: e0bff917 ldw r2,-28(fp) + 1017270: 10001345 stb zero,77(r2) +#endif + + OSTCBInitHook(ptcb); + 1017274: e13ff917 ldw r4,-28(fp) + 1017278: 10204d40 call 10204d4 + + OSTaskCreateHook(ptcb); /* Call user defined hook */ + 101727c: e13ff917 ldw r4,-28(fp) + 1017280: 10203ec0 call 10203ec +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1017284: 0005303a rdctl r2,status + 1017288: e0bff515 stw r2,-44(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 101728c: e0fff517 ldw r3,-44(fp) + 1017290: 00bfff84 movi r2,-2 + 1017294: 1884703a and r2,r3,r2 + 1017298: 1001703a wrctl status,r2 + + return context; + 101729c: e0bff517 ldw r2,-44(fp) + + OS_ENTER_CRITICAL(); + 10172a0: e0bff815 stw r2,-32(fp) + OSTCBPrioTbl[prio] = ptcb; + 10172a4: e0bffa03 ldbu r2,-24(fp) + 10172a8: 00c040f4 movhi r3,259 + 10172ac: 18f3b104 addi r3,r3,-12604 + 10172b0: 1085883a add r2,r2,r2 + 10172b4: 1085883a add r2,r2,r2 + 10172b8: 10c7883a add r3,r2,r3 + 10172bc: e0bff917 ldw r2,-28(fp) + 10172c0: 18800015 stw r2,0(r3) + ptcb->OSTCBNext = OSTCBList; /* Link into TCB chain */ + 10172c4: d0e75e17 ldw r3,-25224(gp) + 10172c8: e0bff917 ldw r2,-28(fp) + 10172cc: 10c00515 stw r3,20(r2) + ptcb->OSTCBPrev = (OS_TCB *)0; + 10172d0: e0bff917 ldw r2,-28(fp) + 10172d4: 10000615 stw zero,24(r2) + if (OSTCBList != (OS_TCB *)0) { + 10172d8: d0a75e17 ldw r2,-25224(gp) + 10172dc: 1005003a cmpeq r2,r2,zero + 10172e0: 1000031e bne r2,zero,10172f0 + OSTCBList->OSTCBPrev = ptcb; + 10172e4: d0e75e17 ldw r3,-25224(gp) + 10172e8: e0bff917 ldw r2,-28(fp) + 10172ec: 18800615 stw r2,24(r3) + } + OSTCBList = ptcb; + 10172f0: e0bff917 ldw r2,-28(fp) + 10172f4: d0a75e15 stw r2,-25224(gp) + OSRdyGrp |= ptcb->OSTCBBitY; /* Make task ready to run */ + 10172f8: e0bff917 ldw r2,-28(fp) + 10172fc: 10c00d83 ldbu r3,54(r2) + 1017300: d0a76703 ldbu r2,-25188(gp) + 1017304: 1884b03a or r2,r3,r2 + 1017308: d0a76705 stb r2,-25188(gp) + OSRdyTbl[ptcb->OSTCBY] |= ptcb->OSTCBBitX; + 101730c: e0bff917 ldw r2,-28(fp) + 1017310: 10800d03 ldbu r2,52(r2) + 1017314: 11003fcc andi r4,r2,255 + 1017318: e0bff917 ldw r2,-28(fp) + 101731c: 10800d03 ldbu r2,52(r2) + 1017320: 10c03fcc andi r3,r2,255 + 1017324: d0a76744 addi r2,gp,-25187 + 1017328: 1885883a add r2,r3,r2 + 101732c: 10c00003 ldbu r3,0(r2) + 1017330: e0bff917 ldw r2,-28(fp) + 1017334: 10800d43 ldbu r2,53(r2) + 1017338: 1884b03a or r2,r3,r2 + 101733c: 1007883a mov r3,r2 + 1017340: d0a76744 addi r2,gp,-25187 + 1017344: 2085883a add r2,r4,r2 + 1017348: 10c00005 stb r3,0(r2) + OSTaskCtr++; /* Increment the #tasks counter */ + 101734c: d0a76343 ldbu r2,-25203(gp) + 1017350: 10800044 addi r2,r2,1 + 1017354: d0a76345 stb r2,-25203(gp) + 1017358: e0bff817 ldw r2,-32(fp) + 101735c: e0bff415 stw r2,-48(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1017360: e0bff417 ldw r2,-48(fp) + 1017364: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_NONE); + 1017368: e03fff15 stw zero,-4(fp) + 101736c: 00000606 br 1017388 + 1017370: e0bff817 ldw r2,-32(fp) + 1017374: e0bff315 stw r2,-52(fp) + 1017378: e0bff317 ldw r2,-52(fp) + 101737c: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_NO_MORE_TCB); + 1017380: 00801084 movi r2,66 + 1017384: e0bfff15 stw r2,-4(fp) + 1017388: e0bfff17 ldw r2,-4(fp) +} + 101738c: e037883a mov sp,fp + 1017390: dfc00117 ldw ra,4(sp) + 1017394: df000017 ldw fp,0(sp) + 1017398: dec00204 addi sp,sp,8 + 101739c: f800283a ret + +010173a0 : +********************************************************************************************************* +*/ + +#if OS_DEBUG_EN > 0 +void OSDebugInit (void) +{ + 10173a0: defffe04 addi sp,sp,-8 + 10173a4: df000115 stw fp,4(sp) + 10173a8: df000104 addi fp,sp,4 + void *ptemp; + + + ptemp = (void *)&OSDebugEn; + 10173ac: d0a01c04 addi r2,gp,-32656 + 10173b0: e0bfff15 stw r2,-4(fp) + + ptemp = (void *)&OSEndiannessTest; + 10173b4: d0a01d04 addi r2,gp,-32652 + 10173b8: e0bfff15 stw r2,-4(fp) + + ptemp = (void *)&OSEventMax; + 10173bc: d0a01e84 addi r2,gp,-32646 + 10173c0: e0bfff15 stw r2,-4(fp) + ptemp = (void *)&OSEventNameSize; + 10173c4: d0a01f04 addi r2,gp,-32644 + 10173c8: e0bfff15 stw r2,-4(fp) + ptemp = (void *)&OSEventEn; + 10173cc: d0a01e04 addi r2,gp,-32648 + 10173d0: e0bfff15 stw r2,-4(fp) + ptemp = (void *)&OSEventSize; + 10173d4: d0a01f84 addi r2,gp,-32642 + 10173d8: e0bfff15 stw r2,-4(fp) + ptemp = (void *)&OSEventTblSize; + 10173dc: d0a02004 addi r2,gp,-32640 + 10173e0: e0bfff15 stw r2,-4(fp) + ptemp = (void *)&OSEventMultiEn; + 10173e4: d0a02084 addi r2,gp,-32638 + 10173e8: e0bfff15 stw r2,-4(fp) + + ptemp = (void *)&OSFlagEn; + 10173ec: d0a02104 addi r2,gp,-32636 + 10173f0: e0bfff15 stw r2,-4(fp) + ptemp = (void *)&OSFlagGrpSize; + 10173f4: d0a02184 addi r2,gp,-32634 + 10173f8: e0bfff15 stw r2,-4(fp) + ptemp = (void *)&OSFlagNodeSize; + 10173fc: d0a02204 addi r2,gp,-32632 + 1017400: e0bfff15 stw r2,-4(fp) + ptemp = (void *)&OSFlagWidth; + 1017404: d0a02284 addi r2,gp,-32630 + 1017408: e0bfff15 stw r2,-4(fp) + ptemp = (void *)&OSFlagMax; + 101740c: d0a02304 addi r2,gp,-32628 + 1017410: e0bfff15 stw r2,-4(fp) + ptemp = (void *)&OSFlagNameSize; + 1017414: d0a02384 addi r2,gp,-32626 + 1017418: e0bfff15 stw r2,-4(fp) + + ptemp = (void *)&OSLowestPrio; + 101741c: d0a02404 addi r2,gp,-32624 + 1017420: e0bfff15 stw r2,-4(fp) + + ptemp = (void *)&OSMboxEn; + 1017424: d0a02484 addi r2,gp,-32622 + 1017428: e0bfff15 stw r2,-4(fp) + + ptemp = (void *)&OSMemEn; + 101742c: d0a02504 addi r2,gp,-32620 + 1017430: e0bfff15 stw r2,-4(fp) + ptemp = (void *)&OSMemMax; + 1017434: d0a02584 addi r2,gp,-32618 + 1017438: e0bfff15 stw r2,-4(fp) + ptemp = (void *)&OSMemNameSize; + 101743c: d0a02604 addi r2,gp,-32616 + 1017440: e0bfff15 stw r2,-4(fp) + ptemp = (void *)&OSMemSize; + 1017444: d0a02684 addi r2,gp,-32614 + 1017448: e0bfff15 stw r2,-4(fp) + ptemp = (void *)&OSMemTblSize; + 101744c: d0a02704 addi r2,gp,-32612 + 1017450: e0bfff15 stw r2,-4(fp) + + ptemp = (void *)&OSMutexEn; + 1017454: d0a02784 addi r2,gp,-32610 + 1017458: e0bfff15 stw r2,-4(fp) + + ptemp = (void *)&OSPtrSize; + 101745c: d0a02804 addi r2,gp,-32608 + 1017460: e0bfff15 stw r2,-4(fp) + + ptemp = (void *)&OSQEn; + 1017464: d0a02884 addi r2,gp,-32606 + 1017468: e0bfff15 stw r2,-4(fp) + ptemp = (void *)&OSQMax; + 101746c: d0a02904 addi r2,gp,-32604 + 1017470: e0bfff15 stw r2,-4(fp) + ptemp = (void *)&OSQSize; + 1017474: d0a02984 addi r2,gp,-32602 + 1017478: e0bfff15 stw r2,-4(fp) + + ptemp = (void *)&OSRdyTblSize; + 101747c: d0a02a04 addi r2,gp,-32600 + 1017480: e0bfff15 stw r2,-4(fp) + + ptemp = (void *)&OSSemEn; + 1017484: d0a02a84 addi r2,gp,-32598 + 1017488: e0bfff15 stw r2,-4(fp) + + ptemp = (void *)&OSStkWidth; + 101748c: d0a02b04 addi r2,gp,-32596 + 1017490: e0bfff15 stw r2,-4(fp) + + ptemp = (void *)&OSTaskCreateEn; + 1017494: d0a02b84 addi r2,gp,-32594 + 1017498: e0bfff15 stw r2,-4(fp) + ptemp = (void *)&OSTaskCreateExtEn; + 101749c: d0a02c04 addi r2,gp,-32592 + 10174a0: e0bfff15 stw r2,-4(fp) + ptemp = (void *)&OSTaskDelEn; + 10174a4: d0a02c84 addi r2,gp,-32590 + 10174a8: e0bfff15 stw r2,-4(fp) + ptemp = (void *)&OSTaskIdleStkSize; + 10174ac: d0a02d04 addi r2,gp,-32588 + 10174b0: e0bfff15 stw r2,-4(fp) + ptemp = (void *)&OSTaskProfileEn; + 10174b4: d0a02d84 addi r2,gp,-32586 + 10174b8: e0bfff15 stw r2,-4(fp) + ptemp = (void *)&OSTaskMax; + 10174bc: d0a02e04 addi r2,gp,-32584 + 10174c0: e0bfff15 stw r2,-4(fp) + ptemp = (void *)&OSTaskNameSize; + 10174c4: d0a02e84 addi r2,gp,-32582 + 10174c8: e0bfff15 stw r2,-4(fp) + ptemp = (void *)&OSTaskStatEn; + 10174cc: d0a02f04 addi r2,gp,-32580 + 10174d0: e0bfff15 stw r2,-4(fp) + ptemp = (void *)&OSTaskStatStkSize; + 10174d4: d0a02f84 addi r2,gp,-32578 + 10174d8: e0bfff15 stw r2,-4(fp) + ptemp = (void *)&OSTaskStatStkChkEn; + 10174dc: d0a03004 addi r2,gp,-32576 + 10174e0: e0bfff15 stw r2,-4(fp) + ptemp = (void *)&OSTaskSwHookEn; + 10174e4: d0a03084 addi r2,gp,-32574 + 10174e8: e0bfff15 stw r2,-4(fp) + + ptemp = (void *)&OSTCBPrioTblMax; + 10174ec: d0a03104 addi r2,gp,-32572 + 10174f0: e0bfff15 stw r2,-4(fp) + ptemp = (void *)&OSTCBSize; + 10174f4: d0a03184 addi r2,gp,-32570 + 10174f8: e0bfff15 stw r2,-4(fp) + + ptemp = (void *)&OSTicksPerSec; + 10174fc: d0a03204 addi r2,gp,-32568 + 1017500: e0bfff15 stw r2,-4(fp) + ptemp = (void *)&OSTimeTickHookEn; + 1017504: d0a03284 addi r2,gp,-32566 + 1017508: e0bfff15 stw r2,-4(fp) + + ptemp = (void *)&OSTmrWheelSize; + ptemp = (void *)&OSTmrWheelTblSize; +#endif + + ptemp = (void *)&OSVersionNbr; + 101750c: d0a03304 addi r2,gp,-32564 + 1017510: e0bfff15 stw r2,-4(fp) + + ptemp = (void *)&OSDataSize; + 1017514: d0a03804 addi r2,gp,-32544 + 1017518: e0bfff15 stw r2,-4(fp) + + ptemp = ptemp; /* Prevent compiler warning for 'ptemp' not being used! */ +} + 101751c: e037883a mov sp,fp + 1017520: df000017 ldw fp,0(sp) + 1017524: dec00104 addi sp,sp,4 + 1017528: f800283a ret + +0101752c : +********************************************************************************************************* +*/ + +#if OS_FLAG_ACCEPT_EN > 0 +OS_FLAGS OSFlagAccept (OS_FLAG_GRP *pgrp, OS_FLAGS flags, INT8U wait_type, INT8U *perr) +{ + 101752c: defff104 addi sp,sp,-60 + 1017530: df000e15 stw fp,56(sp) + 1017534: df000e04 addi fp,sp,56 + 1017538: e13ffa15 stw r4,-24(fp) + 101753c: e1fffd15 stw r7,-12(fp) + 1017540: e17ffb0d sth r5,-20(fp) + 1017544: e1bffc05 stb r6,-16(fp) + OS_FLAGS flags_rdy; + INT8U result; + BOOLEAN consume; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 1017548: e03ff815 stw zero,-32(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + 101754c: e0bffd17 ldw r2,-12(fp) + 1017550: 1004c03a cmpne r2,r2,zero + 1017554: 1000021e bne r2,zero,1017560 + return ((OS_FLAGS)0); + 1017558: e03fff15 stw zero,-4(fp) + 101755c: 0000bb06 br 101784c + } + if (pgrp == (OS_FLAG_GRP *)0) { /* Validate 'pgrp' */ + 1017560: e0bffa17 ldw r2,-24(fp) + 1017564: 1004c03a cmpne r2,r2,zero + 1017568: 1000051e bne r2,zero,1017580 + *perr = OS_ERR_FLAG_INVALID_PGRP; + 101756c: e0fffd17 ldw r3,-12(fp) + 1017570: 00801b84 movi r2,110 + 1017574: 18800005 stb r2,0(r3) + return ((OS_FLAGS)0); + 1017578: e03fff15 stw zero,-4(fp) + 101757c: 0000b306 br 101784c + } +#endif + if (pgrp->OSFlagType != OS_EVENT_TYPE_FLAG) { /* Validate event block type */ + 1017580: e0bffa17 ldw r2,-24(fp) + 1017584: 10800003 ldbu r2,0(r2) + 1017588: 10803fcc andi r2,r2,255 + 101758c: 10800160 cmpeqi r2,r2,5 + 1017590: 1000051e bne r2,zero,10175a8 + *perr = OS_ERR_EVENT_TYPE; + 1017594: e0fffd17 ldw r3,-12(fp) + 1017598: 00800044 movi r2,1 + 101759c: 18800005 stb r2,0(r3) + return ((OS_FLAGS)0); + 10175a0: e03fff15 stw zero,-4(fp) + 10175a4: 0000a906 br 101784c + } + result = (INT8U)(wait_type & OS_FLAG_CONSUME); + 10175a8: e0fffc03 ldbu r3,-16(fp) + 10175ac: 00bfe004 movi r2,-128 + 10175b0: 1884703a and r2,r3,r2 + 10175b4: e0bff945 stb r2,-27(fp) + if (result != (INT8U)0) { /* See if we need to consume the flags */ + 10175b8: e0bff943 ldbu r2,-27(fp) + 10175bc: 1005003a cmpeq r2,r2,zero + 10175c0: 1000061e bne r2,zero,10175dc + wait_type &= ~OS_FLAG_CONSUME; + 10175c4: e0bffc03 ldbu r2,-16(fp) + 10175c8: 10801fcc andi r2,r2,127 + 10175cc: e0bffc05 stb r2,-16(fp) + consume = OS_TRUE; + 10175d0: 00800044 movi r2,1 + 10175d4: e0bff905 stb r2,-28(fp) + 10175d8: 00000106 br 10175e0 + } else { + consume = OS_FALSE; + 10175dc: e03ff905 stb zero,-28(fp) + } +/*$PAGE*/ + *perr = OS_ERR_NONE; /* Assume NO error until proven otherwise. */ + 10175e0: e0bffd17 ldw r2,-12(fp) + 10175e4: 10000005 stb zero,0(r2) +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 10175e8: 0005303a rdctl r2,status + 10175ec: e0bff715 stw r2,-36(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 10175f0: e0fff717 ldw r3,-36(fp) + 10175f4: 00bfff84 movi r2,-2 + 10175f8: 1884703a and r2,r3,r2 + 10175fc: 1001703a wrctl status,r2 + + return context; + 1017600: e0bff717 ldw r2,-36(fp) + OS_ENTER_CRITICAL(); + 1017604: e0bff815 stw r2,-32(fp) + switch (wait_type) { + 1017608: e0bffc03 ldbu r2,-16(fp) + 101760c: e0bffe15 stw r2,-8(fp) + 1017610: e0fffe17 ldw r3,-8(fp) + 1017614: 18800060 cmpeqi r2,r3,1 + 1017618: 1000651e bne r2,zero,10177b0 + 101761c: e0fffe17 ldw r3,-8(fp) + 1017620: 18800088 cmpgei r2,r3,2 + 1017624: 1000041e bne r2,zero,1017638 + 1017628: e0fffe17 ldw r3,-8(fp) + 101762c: 1805003a cmpeq r2,r3,zero + 1017630: 1000421e bne r2,zero,101773c + 1017634: 00007b06 br 1017824 + 1017638: e0fffe17 ldw r3,-8(fp) + 101763c: 188000a0 cmpeqi r2,r3,2 + 1017640: 1000041e bne r2,zero,1017654 + 1017644: e0fffe17 ldw r3,-8(fp) + 1017648: 188000e0 cmpeqi r2,r3,3 + 101764c: 10001e1e bne r2,zero,10176c8 + 1017650: 00007406 br 1017824 + case OS_FLAG_WAIT_SET_ALL: /* See if all required flags are set */ + flags_rdy = (OS_FLAGS)(pgrp->OSFlagFlags & flags); /* Extract only the bits we want */ + 1017654: e0bffa17 ldw r2,-24(fp) + 1017658: 10c0020b ldhu r3,8(r2) + 101765c: e0bffb0b ldhu r2,-20(fp) + 1017660: 1884703a and r2,r3,r2 + 1017664: e0bff98d sth r2,-26(fp) + if (flags_rdy == flags) { /* Must match ALL the bits that we want */ + 1017668: e0fff98b ldhu r3,-26(fp) + 101766c: e0bffb0b ldhu r2,-20(fp) + 1017670: 18800d1e bne r3,r2,10176a8 + if (consume == OS_TRUE) { /* See if we need to consume the flags */ + 1017674: e0bff903 ldbu r2,-28(fp) + 1017678: 10800058 cmpnei r2,r2,1 + 101767c: 10000d1e bne r2,zero,10176b4 + pgrp->OSFlagFlags &= ~flags_rdy; /* Clear ONLY the flags that we wanted */ + 1017680: e0bffa17 ldw r2,-24(fp) + 1017684: 1080020b ldhu r2,8(r2) + 1017688: 1007883a mov r3,r2 + 101768c: e0bff98b ldhu r2,-26(fp) + 1017690: 0084303a nor r2,zero,r2 + 1017694: 1884703a and r2,r3,r2 + 1017698: 1007883a mov r3,r2 + 101769c: e0bffa17 ldw r2,-24(fp) + 10176a0: 10c0020d sth r3,8(r2) + 10176a4: 00000306 br 10176b4 + } + } else { + *perr = OS_ERR_FLAG_NOT_RDY; + 10176a8: e0fffd17 ldw r3,-12(fp) + 10176ac: 00801c04 movi r2,112 + 10176b0: 18800005 stb r2,0(r3) + 10176b4: e0bff817 ldw r2,-32(fp) + 10176b8: e0bff615 stw r2,-40(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 10176bc: e0bff617 ldw r2,-40(fp) + 10176c0: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); + break; + 10176c4: 00005f06 br 1017844 + + case OS_FLAG_WAIT_SET_ANY: + flags_rdy = (OS_FLAGS)(pgrp->OSFlagFlags & flags); /* Extract only the bits we want */ + 10176c8: e0bffa17 ldw r2,-24(fp) + 10176cc: 10c0020b ldhu r3,8(r2) + 10176d0: e0bffb0b ldhu r2,-20(fp) + 10176d4: 1884703a and r2,r3,r2 + 10176d8: e0bff98d sth r2,-26(fp) + if (flags_rdy != (OS_FLAGS)0) { /* See if any flag set */ + 10176dc: e0bff98b ldhu r2,-26(fp) + 10176e0: 1005003a cmpeq r2,r2,zero + 10176e4: 10000d1e bne r2,zero,101771c + if (consume == OS_TRUE) { /* See if we need to consume the flags */ + 10176e8: e0bff903 ldbu r2,-28(fp) + 10176ec: 10800058 cmpnei r2,r2,1 + 10176f0: 10000d1e bne r2,zero,1017728 + pgrp->OSFlagFlags &= ~flags_rdy; /* Clear ONLY the flags that we got */ + 10176f4: e0bffa17 ldw r2,-24(fp) + 10176f8: 1080020b ldhu r2,8(r2) + 10176fc: 1007883a mov r3,r2 + 1017700: e0bff98b ldhu r2,-26(fp) + 1017704: 0084303a nor r2,zero,r2 + 1017708: 1884703a and r2,r3,r2 + 101770c: 1007883a mov r3,r2 + 1017710: e0bffa17 ldw r2,-24(fp) + 1017714: 10c0020d sth r3,8(r2) + 1017718: 00000306 br 1017728 + } + } else { + *perr = OS_ERR_FLAG_NOT_RDY; + 101771c: e0fffd17 ldw r3,-12(fp) + 1017720: 00801c04 movi r2,112 + 1017724: 18800005 stb r2,0(r3) + 1017728: e0bff817 ldw r2,-32(fp) + 101772c: e0bff515 stw r2,-44(fp) + 1017730: e0bff517 ldw r2,-44(fp) + 1017734: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); + break; + 1017738: 00004206 br 1017844 + +#if OS_FLAG_WAIT_CLR_EN > 0 + case OS_FLAG_WAIT_CLR_ALL: /* See if all required flags are cleared */ + flags_rdy = (OS_FLAGS)(~pgrp->OSFlagFlags & flags); /* Extract only the bits we want */ + 101773c: e0bffa17 ldw r2,-24(fp) + 1017740: 1080020b ldhu r2,8(r2) + 1017744: 0084303a nor r2,zero,r2 + 1017748: 1007883a mov r3,r2 + 101774c: e0bffb0b ldhu r2,-20(fp) + 1017750: 1884703a and r2,r3,r2 + 1017754: e0bff98d sth r2,-26(fp) + if (flags_rdy == flags) { /* Must match ALL the bits that we want */ + 1017758: e0fff98b ldhu r3,-26(fp) + 101775c: e0bffb0b ldhu r2,-20(fp) + 1017760: 18800b1e bne r3,r2,1017790 + if (consume == OS_TRUE) { /* See if we need to consume the flags */ + 1017764: e0bff903 ldbu r2,-28(fp) + 1017768: 10800058 cmpnei r2,r2,1 + 101776c: 10000b1e bne r2,zero,101779c + pgrp->OSFlagFlags |= flags_rdy; /* Set ONLY the flags that we wanted */ + 1017770: e0bffa17 ldw r2,-24(fp) + 1017774: 10c0020b ldhu r3,8(r2) + 1017778: e0bff98b ldhu r2,-26(fp) + 101777c: 1884b03a or r2,r3,r2 + 1017780: 1007883a mov r3,r2 + 1017784: e0bffa17 ldw r2,-24(fp) + 1017788: 10c0020d sth r3,8(r2) + 101778c: 00000306 br 101779c + } + } else { + *perr = OS_ERR_FLAG_NOT_RDY; + 1017790: e0fffd17 ldw r3,-12(fp) + 1017794: 00801c04 movi r2,112 + 1017798: 18800005 stb r2,0(r3) + 101779c: e0bff817 ldw r2,-32(fp) + 10177a0: e0bff415 stw r2,-48(fp) + 10177a4: e0bff417 ldw r2,-48(fp) + 10177a8: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); + break; + 10177ac: 00002506 br 1017844 + + case OS_FLAG_WAIT_CLR_ANY: + flags_rdy = (OS_FLAGS)(~pgrp->OSFlagFlags & flags); /* Extract only the bits we want */ + 10177b0: e0bffa17 ldw r2,-24(fp) + 10177b4: 1080020b ldhu r2,8(r2) + 10177b8: 0084303a nor r2,zero,r2 + 10177bc: 1007883a mov r3,r2 + 10177c0: e0bffb0b ldhu r2,-20(fp) + 10177c4: 1884703a and r2,r3,r2 + 10177c8: e0bff98d sth r2,-26(fp) + if (flags_rdy != (OS_FLAGS)0) { /* See if any flag cleared */ + 10177cc: e0bff98b ldhu r2,-26(fp) + 10177d0: 1005003a cmpeq r2,r2,zero + 10177d4: 10000b1e bne r2,zero,1017804 + if (consume == OS_TRUE) { /* See if we need to consume the flags */ + 10177d8: e0bff903 ldbu r2,-28(fp) + 10177dc: 10800058 cmpnei r2,r2,1 + 10177e0: 10000b1e bne r2,zero,1017810 + pgrp->OSFlagFlags |= flags_rdy; /* Set ONLY the flags that we got */ + 10177e4: e0bffa17 ldw r2,-24(fp) + 10177e8: 10c0020b ldhu r3,8(r2) + 10177ec: e0bff98b ldhu r2,-26(fp) + 10177f0: 1884b03a or r2,r3,r2 + 10177f4: 1007883a mov r3,r2 + 10177f8: e0bffa17 ldw r2,-24(fp) + 10177fc: 10c0020d sth r3,8(r2) + 1017800: 00000306 br 1017810 + } + } else { + *perr = OS_ERR_FLAG_NOT_RDY; + 1017804: e0fffd17 ldw r3,-12(fp) + 1017808: 00801c04 movi r2,112 + 101780c: 18800005 stb r2,0(r3) + 1017810: e0bff817 ldw r2,-32(fp) + 1017814: e0bff315 stw r2,-52(fp) + 1017818: e0bff317 ldw r2,-52(fp) + 101781c: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); + break; + 1017820: 00000806 br 1017844 + 1017824: e0bff817 ldw r2,-32(fp) + 1017828: e0bff215 stw r2,-56(fp) + 101782c: e0bff217 ldw r2,-56(fp) + 1017830: 1001703a wrctl status,r2 +#endif + + default: + OS_EXIT_CRITICAL(); + flags_rdy = (OS_FLAGS)0; + 1017834: e03ff98d sth zero,-26(fp) + *perr = OS_ERR_FLAG_WAIT_TYPE; + 1017838: e0fffd17 ldw r3,-12(fp) + 101783c: 00801bc4 movi r2,111 + 1017840: 18800005 stb r2,0(r3) + break; + } + return (flags_rdy); + 1017844: e0bff98b ldhu r2,-26(fp) + 1017848: e0bfff15 stw r2,-4(fp) + 101784c: e0bfff17 ldw r2,-4(fp) +} + 1017850: e037883a mov sp,fp + 1017854: df000017 ldw fp,0(sp) + 1017858: dec00104 addi sp,sp,4 + 101785c: f800283a ret + +01017860 : +* Called from: Task ONLY +********************************************************************************************************* +*/ + +OS_FLAG_GRP *OSFlagCreate (OS_FLAGS flags, INT8U *perr) +{ + 1017860: defff704 addi sp,sp,-36 + 1017864: df000815 stw fp,32(sp) + 1017868: df000804 addi fp,sp,32 + 101786c: e17ffe15 stw r5,-8(fp) + 1017870: e13ffd0d sth r4,-12(fp) + OS_FLAG_GRP *pgrp; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 1017874: e03ffb15 stw zero,-20(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + 1017878: e0bffe17 ldw r2,-8(fp) + 101787c: 1004c03a cmpne r2,r2,zero + 1017880: 1000021e bne r2,zero,101788c + return ((OS_FLAG_GRP *)0); + 1017884: e03fff15 stw zero,-4(fp) + 1017888: 00003f06 br 1017988 + } +#endif + if (OSIntNesting > 0) { /* See if called from ISR ... */ + 101788c: 008040b4 movhi r2,258 + 1017890: 10952204 addi r2,r2,21640 + 1017894: 10800003 ldbu r2,0(r2) + 1017898: 10803fcc andi r2,r2,255 + 101789c: 1005003a cmpeq r2,r2,zero + 10178a0: 1000051e bne r2,zero,10178b8 + *perr = OS_ERR_CREATE_ISR; /* ... can't CREATE from an ISR */ + 10178a4: e0fffe17 ldw r3,-8(fp) + 10178a8: 00800404 movi r2,16 + 10178ac: 18800005 stb r2,0(r3) + return ((OS_FLAG_GRP *)0); + 10178b0: e03fff15 stw zero,-4(fp) + 10178b4: 00003406 br 1017988 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 10178b8: 0005303a rdctl r2,status + 10178bc: e0bffa15 stw r2,-24(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 10178c0: e0fffa17 ldw r3,-24(fp) + 10178c4: 00bfff84 movi r2,-2 + 10178c8: 1884703a and r2,r3,r2 + 10178cc: 1001703a wrctl status,r2 + + return context; + 10178d0: e0bffa17 ldw r2,-24(fp) + } + OS_ENTER_CRITICAL(); + 10178d4: e0bffb15 stw r2,-20(fp) + pgrp = OSFlagFreeList; /* Get next free event flag */ + 10178d8: 008040b4 movhi r2,258 + 10178dc: 10952504 addi r2,r2,21652 + 10178e0: 10800017 ldw r2,0(r2) + 10178e4: e0bffc15 stw r2,-16(fp) + if (pgrp != (OS_FLAG_GRP *)0) { /* See if we have event flag groups available */ + 10178e8: e0bffc17 ldw r2,-16(fp) + 10178ec: 1005003a cmpeq r2,r2,zero + 10178f0: 10001c1e bne r2,zero,1017964 + /* Adjust free list */ + OSFlagFreeList = (OS_FLAG_GRP *)OSFlagFreeList->OSFlagWaitList; + 10178f4: 008040b4 movhi r2,258 + 10178f8: 10952504 addi r2,r2,21652 + 10178fc: 10800017 ldw r2,0(r2) + 1017900: 10800117 ldw r2,4(r2) + 1017904: 1007883a mov r3,r2 + 1017908: 008040b4 movhi r2,258 + 101790c: 10952504 addi r2,r2,21652 + 1017910: 10c00015 stw r3,0(r2) + pgrp->OSFlagType = OS_EVENT_TYPE_FLAG; /* Set to event flag group type */ + 1017914: e0fffc17 ldw r3,-16(fp) + 1017918: 00800144 movi r2,5 + 101791c: 18800005 stb r2,0(r3) + pgrp->OSFlagFlags = flags; /* Set to desired initial value */ + 1017920: e0fffc17 ldw r3,-16(fp) + 1017924: e0bffd0b ldhu r2,-12(fp) + 1017928: 1880020d sth r2,8(r3) + pgrp->OSFlagWaitList = (void *)0; /* Clear list of tasks waiting on flags */ + 101792c: e0bffc17 ldw r2,-16(fp) + 1017930: 10000115 stw zero,4(r2) +#if OS_FLAG_NAME_SIZE > 1 + pgrp->OSFlagName[0] = '?'; + 1017934: e0fffc17 ldw r3,-16(fp) + 1017938: 00800fc4 movi r2,63 + 101793c: 18800285 stb r2,10(r3) + pgrp->OSFlagName[1] = OS_ASCII_NUL; + 1017940: e0bffc17 ldw r2,-16(fp) + 1017944: 100002c5 stb zero,11(r2) + 1017948: e0bffb17 ldw r2,-20(fp) + 101794c: e0bff915 stw r2,-28(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1017950: e0bff917 ldw r2,-28(fp) + 1017954: 1001703a wrctl status,r2 +#endif + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + 1017958: e0bffe17 ldw r2,-8(fp) + 101795c: 10000005 stb zero,0(r2) + 1017960: 00000706 br 1017980 + 1017964: e0bffb17 ldw r2,-20(fp) + 1017968: e0bff815 stw r2,-32(fp) + 101796c: e0bff817 ldw r2,-32(fp) + 1017970: 1001703a wrctl status,r2 + } else { + OS_EXIT_CRITICAL(); + *perr = OS_ERR_FLAG_GRP_DEPLETED; + 1017974: e0fffe17 ldw r3,-8(fp) + 1017978: 00801c84 movi r2,114 + 101797c: 18800005 stb r2,0(r3) + } + return (pgrp); /* Return pointer to event flag group */ + 1017980: e0bffc17 ldw r2,-16(fp) + 1017984: e0bfff15 stw r2,-4(fp) + 1017988: e0bfff17 ldw r2,-4(fp) +} + 101798c: e037883a mov sp,fp + 1017990: df000017 ldw fp,0(sp) + 1017994: dec00104 addi sp,sp,4 + 1017998: f800283a ret + +0101799c : +********************************************************************************************************* +*/ + +#if OS_FLAG_DEL_EN > 0 +OS_FLAG_GRP *OSFlagDel (OS_FLAG_GRP *pgrp, INT8U opt, INT8U *perr) +{ + 101799c: defff004 addi sp,sp,-64 + 10179a0: dfc00f15 stw ra,60(sp) + 10179a4: df000e15 stw fp,56(sp) + 10179a8: df000e04 addi fp,sp,56 + 10179ac: e13ffb15 stw r4,-20(fp) + 10179b0: e1bffd15 stw r6,-12(fp) + 10179b4: e17ffc05 stb r5,-16(fp) + BOOLEAN tasks_waiting; + OS_FLAG_NODE *pnode; + OS_FLAG_GRP *pgrp_return; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 10179b8: e03ff715 stw zero,-36(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + 10179bc: e0bffd17 ldw r2,-12(fp) + 10179c0: 1004c03a cmpne r2,r2,zero + 10179c4: 1000031e bne r2,zero,10179d4 + return (pgrp); + 10179c8: e0bffb17 ldw r2,-20(fp) + 10179cc: e0bfff15 stw r2,-4(fp) + 10179d0: 00009606 br 1017c2c + } + if (pgrp == (OS_FLAG_GRP *)0) { /* Validate 'pgrp' */ + 10179d4: e0bffb17 ldw r2,-20(fp) + 10179d8: 1004c03a cmpne r2,r2,zero + 10179dc: 1000061e bne r2,zero,10179f8 + *perr = OS_ERR_FLAG_INVALID_PGRP; + 10179e0: e0fffd17 ldw r3,-12(fp) + 10179e4: 00801b84 movi r2,110 + 10179e8: 18800005 stb r2,0(r3) + return (pgrp); + 10179ec: e0fffb17 ldw r3,-20(fp) + 10179f0: e0ffff15 stw r3,-4(fp) + 10179f4: 00008d06 br 1017c2c + } +#endif + if (OSIntNesting > 0) { /* See if called from ISR ... */ + 10179f8: 008040b4 movhi r2,258 + 10179fc: 10952204 addi r2,r2,21640 + 1017a00: 10800003 ldbu r2,0(r2) + 1017a04: 10803fcc andi r2,r2,255 + 1017a08: 1005003a cmpeq r2,r2,zero + 1017a0c: 1000061e bne r2,zero,1017a28 + *perr = OS_ERR_DEL_ISR; /* ... can't DELETE from an ISR */ + 1017a10: e0fffd17 ldw r3,-12(fp) + 1017a14: 008003c4 movi r2,15 + 1017a18: 18800005 stb r2,0(r3) + return (pgrp); + 1017a1c: e0bffb17 ldw r2,-20(fp) + 1017a20: e0bfff15 stw r2,-4(fp) + 1017a24: 00008106 br 1017c2c + } + if (pgrp->OSFlagType != OS_EVENT_TYPE_FLAG) { /* Validate event group type */ + 1017a28: e0bffb17 ldw r2,-20(fp) + 1017a2c: 10800003 ldbu r2,0(r2) + 1017a30: 10803fcc andi r2,r2,255 + 1017a34: 10800160 cmpeqi r2,r2,5 + 1017a38: 1000061e bne r2,zero,1017a54 + *perr = OS_ERR_EVENT_TYPE; + 1017a3c: e0fffd17 ldw r3,-12(fp) + 1017a40: 00800044 movi r2,1 + 1017a44: 18800005 stb r2,0(r3) + return (pgrp); + 1017a48: e0fffb17 ldw r3,-20(fp) + 1017a4c: e0ffff15 stw r3,-4(fp) + 1017a50: 00007606 br 1017c2c +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1017a54: 0005303a rdctl r2,status + 1017a58: e0bff615 stw r2,-40(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1017a5c: e0fff617 ldw r3,-40(fp) + 1017a60: 00bfff84 movi r2,-2 + 1017a64: 1884703a and r2,r3,r2 + 1017a68: 1001703a wrctl status,r2 + + return context; + 1017a6c: e0bff617 ldw r2,-40(fp) + } + OS_ENTER_CRITICAL(); + 1017a70: e0bff715 stw r2,-36(fp) + if (pgrp->OSFlagWaitList != (void *)0) { /* See if any tasks waiting on event flags */ + 1017a74: e0bffb17 ldw r2,-20(fp) + 1017a78: 10800117 ldw r2,4(r2) + 1017a7c: 1005003a cmpeq r2,r2,zero + 1017a80: 1000031e bne r2,zero,1017a90 + tasks_waiting = OS_TRUE; /* Yes */ + 1017a84: 00800044 movi r2,1 + 1017a88: e0bffa05 stb r2,-24(fp) + 1017a8c: 00000106 br 1017a94 + } else { + tasks_waiting = OS_FALSE; /* No */ + 1017a90: e03ffa05 stb zero,-24(fp) + } + switch (opt) { + 1017a94: e0bffc03 ldbu r2,-16(fp) + 1017a98: e0bffe15 stw r2,-8(fp) + 1017a9c: e0fffe17 ldw r3,-8(fp) + 1017aa0: 1805003a cmpeq r2,r3,zero + 1017aa4: 1000041e bne r2,zero,1017ab8 + 1017aa8: e0fffe17 ldw r3,-8(fp) + 1017aac: 18800060 cmpeqi r2,r3,1 + 1017ab0: 1000281e bne r2,zero,1017b54 + 1017ab4: 00005206 br 1017c00 + case OS_DEL_NO_PEND: /* Delete group if no task waiting */ + if (tasks_waiting == OS_FALSE) { + 1017ab8: e0bffa03 ldbu r2,-24(fp) + 1017abc: 1004c03a cmpne r2,r2,zero + 1017ac0: 10001a1e bne r2,zero,1017b2c +#if OS_FLAG_NAME_SIZE > 1 + pgrp->OSFlagName[0] = '?'; /* Unknown name */ + 1017ac4: e0fffb17 ldw r3,-20(fp) + 1017ac8: 00800fc4 movi r2,63 + 1017acc: 18800285 stb r2,10(r3) + pgrp->OSFlagName[1] = OS_ASCII_NUL; + 1017ad0: e0bffb17 ldw r2,-20(fp) + 1017ad4: 100002c5 stb zero,11(r2) +#endif + pgrp->OSFlagType = OS_EVENT_TYPE_UNUSED; + 1017ad8: e0bffb17 ldw r2,-20(fp) + 1017adc: 10000005 stb zero,0(r2) + pgrp->OSFlagWaitList = (void *)OSFlagFreeList; /* Return group to free list */ + 1017ae0: 008040b4 movhi r2,258 + 1017ae4: 10952504 addi r2,r2,21652 + 1017ae8: 10c00017 ldw r3,0(r2) + 1017aec: e0bffb17 ldw r2,-20(fp) + 1017af0: 10c00115 stw r3,4(r2) + pgrp->OSFlagFlags = (OS_FLAGS)0; + 1017af4: e0bffb17 ldw r2,-20(fp) + 1017af8: 1000020d sth zero,8(r2) + OSFlagFreeList = pgrp; + 1017afc: 00c040b4 movhi r3,258 + 1017b00: 18d52504 addi r3,r3,21652 + 1017b04: e0bffb17 ldw r2,-20(fp) + 1017b08: 18800015 stw r2,0(r3) + 1017b0c: e0bff717 ldw r2,-36(fp) + 1017b10: e0bff515 stw r2,-44(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1017b14: e0bff517 ldw r2,-44(fp) + 1017b18: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + 1017b1c: e0bffd17 ldw r2,-12(fp) + 1017b20: 10000005 stb zero,0(r2) + pgrp_return = (OS_FLAG_GRP *)0; /* Event Flag Group has been deleted */ + 1017b24: e03ff815 stw zero,-32(fp) + 1017b28: 00003e06 br 1017c24 + 1017b2c: e0bff717 ldw r2,-36(fp) + 1017b30: e0bff415 stw r2,-48(fp) + 1017b34: e0bff417 ldw r2,-48(fp) + 1017b38: 1001703a wrctl status,r2 + } else { + OS_EXIT_CRITICAL(); + *perr = OS_ERR_TASK_WAITING; + 1017b3c: e0fffd17 ldw r3,-12(fp) + 1017b40: 00801244 movi r2,73 + 1017b44: 18800005 stb r2,0(r3) + pgrp_return = pgrp; + 1017b48: e0bffb17 ldw r2,-20(fp) + 1017b4c: e0bff815 stw r2,-32(fp) + } + break; + 1017b50: 00003406 br 1017c24 + + case OS_DEL_ALWAYS: /* Always delete the event flag group */ + pnode = (OS_FLAG_NODE *)pgrp->OSFlagWaitList; + 1017b54: e0bffb17 ldw r2,-20(fp) + 1017b58: 10800117 ldw r2,4(r2) + 1017b5c: e0bff915 stw r2,-28(fp) + while (pnode != (OS_FLAG_NODE *)0) { /* Ready ALL tasks waiting for flags */ + 1017b60: 00000606 br 1017b7c + (void)OS_FlagTaskRdy(pnode, (OS_FLAGS)0); + 1017b64: e13ff917 ldw r4,-28(fp) + 1017b68: 000b883a mov r5,zero + 1017b6c: 1018cac0 call 1018cac + pnode = (OS_FLAG_NODE *)pnode->OSFlagNodeNext; + 1017b70: e0bff917 ldw r2,-28(fp) + 1017b74: 10800017 ldw r2,0(r2) + 1017b78: e0bff915 stw r2,-28(fp) + } + break; + + case OS_DEL_ALWAYS: /* Always delete the event flag group */ + pnode = (OS_FLAG_NODE *)pgrp->OSFlagWaitList; + while (pnode != (OS_FLAG_NODE *)0) { /* Ready ALL tasks waiting for flags */ + 1017b7c: e0bff917 ldw r2,-28(fp) + 1017b80: 1004c03a cmpne r2,r2,zero + 1017b84: 103ff71e bne r2,zero,1017b64 + (void)OS_FlagTaskRdy(pnode, (OS_FLAGS)0); + pnode = (OS_FLAG_NODE *)pnode->OSFlagNodeNext; + } +#if OS_FLAG_NAME_SIZE > 1 + pgrp->OSFlagName[0] = '?'; /* Unknown name */ + 1017b88: e0fffb17 ldw r3,-20(fp) + 1017b8c: 00800fc4 movi r2,63 + 1017b90: 18800285 stb r2,10(r3) + pgrp->OSFlagName[1] = OS_ASCII_NUL; + 1017b94: e0bffb17 ldw r2,-20(fp) + 1017b98: 100002c5 stb zero,11(r2) +#endif + pgrp->OSFlagType = OS_EVENT_TYPE_UNUSED; + 1017b9c: e0bffb17 ldw r2,-20(fp) + 1017ba0: 10000005 stb zero,0(r2) + pgrp->OSFlagWaitList = (void *)OSFlagFreeList;/* Return group to free list */ + 1017ba4: 008040b4 movhi r2,258 + 1017ba8: 10952504 addi r2,r2,21652 + 1017bac: 10c00017 ldw r3,0(r2) + 1017bb0: e0bffb17 ldw r2,-20(fp) + 1017bb4: 10c00115 stw r3,4(r2) + pgrp->OSFlagFlags = (OS_FLAGS)0; + 1017bb8: e0bffb17 ldw r2,-20(fp) + 1017bbc: 1000020d sth zero,8(r2) + OSFlagFreeList = pgrp; + 1017bc0: 00c040b4 movhi r3,258 + 1017bc4: 18d52504 addi r3,r3,21652 + 1017bc8: e0bffb17 ldw r2,-20(fp) + 1017bcc: 18800015 stw r2,0(r3) + 1017bd0: e0bff717 ldw r2,-36(fp) + 1017bd4: e0bff315 stw r2,-52(fp) + 1017bd8: e0bff317 ldw r2,-52(fp) + 1017bdc: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + if (tasks_waiting == OS_TRUE) { /* Reschedule only if task(s) were waiting */ + 1017be0: e0bffa03 ldbu r2,-24(fp) + 1017be4: 10800058 cmpnei r2,r2,1 + 1017be8: 1000011e bne r2,zero,1017bf0 + OS_Sched(); /* Find highest priority task ready to run */ + 1017bec: 1016cb80 call 1016cb8 + } + *perr = OS_ERR_NONE; + 1017bf0: e0bffd17 ldw r2,-12(fp) + 1017bf4: 10000005 stb zero,0(r2) + pgrp_return = (OS_FLAG_GRP *)0; /* Event Flag Group has been deleted */ + 1017bf8: e03ff815 stw zero,-32(fp) + break; + 1017bfc: 00000906 br 1017c24 + 1017c00: e0bff717 ldw r2,-36(fp) + 1017c04: e0bff215 stw r2,-56(fp) + 1017c08: e0bff217 ldw r2,-56(fp) + 1017c0c: 1001703a wrctl status,r2 + + default: + OS_EXIT_CRITICAL(); + *perr = OS_ERR_INVALID_OPT; + 1017c10: e0fffd17 ldw r3,-12(fp) + 1017c14: 008001c4 movi r2,7 + 1017c18: 18800005 stb r2,0(r3) + pgrp_return = pgrp; + 1017c1c: e0bffb17 ldw r2,-20(fp) + 1017c20: e0bff815 stw r2,-32(fp) + break; + } + return (pgrp_return); + 1017c24: e0bff817 ldw r2,-32(fp) + 1017c28: e0bfff15 stw r2,-4(fp) + 1017c2c: e0bfff17 ldw r2,-4(fp) +} + 1017c30: e037883a mov sp,fp + 1017c34: dfc00117 ldw ra,4(sp) + 1017c38: df000017 ldw fp,0(sp) + 1017c3c: dec00204 addi sp,sp,8 + 1017c40: f800283a ret + +01017c44 : +********************************************************************************************************* +*/ + +#if OS_FLAG_NAME_SIZE > 1 +INT8U OSFlagNameGet (OS_FLAG_GRP *pgrp, INT8U *pname, INT8U *perr) +{ + 1017c44: defff504 addi sp,sp,-44 + 1017c48: dfc00a15 stw ra,40(sp) + 1017c4c: df000915 stw fp,36(sp) + 1017c50: df000904 addi fp,sp,36 + 1017c54: e13ffc15 stw r4,-16(fp) + 1017c58: e17ffd15 stw r5,-12(fp) + 1017c5c: e1bffe15 stw r6,-8(fp) + INT8U len; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 1017c60: e03ffa15 stw zero,-24(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + 1017c64: e0bffe17 ldw r2,-8(fp) + 1017c68: 1004c03a cmpne r2,r2,zero + 1017c6c: 1000021e bne r2,zero,1017c78 + return (0); + 1017c70: e03fff15 stw zero,-4(fp) + 1017c74: 00003e06 br 1017d70 + } + if (pgrp == (OS_FLAG_GRP *)0) { /* Is 'pgrp' a NULL pointer? */ + 1017c78: e0bffc17 ldw r2,-16(fp) + 1017c7c: 1004c03a cmpne r2,r2,zero + 1017c80: 1000051e bne r2,zero,1017c98 + *perr = OS_ERR_FLAG_INVALID_PGRP; + 1017c84: e0fffe17 ldw r3,-8(fp) + 1017c88: 00801b84 movi r2,110 + 1017c8c: 18800005 stb r2,0(r3) + return (0); + 1017c90: e03fff15 stw zero,-4(fp) + 1017c94: 00003606 br 1017d70 + } + if (pname == (INT8U *)0) { /* Is 'pname' a NULL pointer? */ + 1017c98: e0bffd17 ldw r2,-12(fp) + 1017c9c: 1004c03a cmpne r2,r2,zero + 1017ca0: 1000051e bne r2,zero,1017cb8 + *perr = OS_ERR_PNAME_NULL; + 1017ca4: e0fffe17 ldw r3,-8(fp) + 1017ca8: 00800304 movi r2,12 + 1017cac: 18800005 stb r2,0(r3) + return (0); + 1017cb0: e03fff15 stw zero,-4(fp) + 1017cb4: 00002e06 br 1017d70 + } +#endif + if (OSIntNesting > 0) { /* See if trying to call from an ISR */ + 1017cb8: 008040b4 movhi r2,258 + 1017cbc: 10952204 addi r2,r2,21640 + 1017cc0: 10800003 ldbu r2,0(r2) + 1017cc4: 10803fcc andi r2,r2,255 + 1017cc8: 1005003a cmpeq r2,r2,zero + 1017ccc: 1000051e bne r2,zero,1017ce4 + *perr = OS_ERR_NAME_GET_ISR; + 1017cd0: e0fffe17 ldw r3,-8(fp) + 1017cd4: 00800444 movi r2,17 + 1017cd8: 18800005 stb r2,0(r3) + return (0); + 1017cdc: e03fff15 stw zero,-4(fp) + 1017ce0: 00002306 br 1017d70 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1017ce4: 0005303a rdctl r2,status + 1017ce8: e0bff915 stw r2,-28(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1017cec: e0fff917 ldw r3,-28(fp) + 1017cf0: 00bfff84 movi r2,-2 + 1017cf4: 1884703a and r2,r3,r2 + 1017cf8: 1001703a wrctl status,r2 + + return context; + 1017cfc: e0bff917 ldw r2,-28(fp) + } + OS_ENTER_CRITICAL(); + 1017d00: e0bffa15 stw r2,-24(fp) + if (pgrp->OSFlagType != OS_EVENT_TYPE_FLAG) { + 1017d04: e0bffc17 ldw r2,-16(fp) + 1017d08: 10800003 ldbu r2,0(r2) + 1017d0c: 10803fcc andi r2,r2,255 + 1017d10: 10800160 cmpeqi r2,r2,5 + 1017d14: 1000091e bne r2,zero,1017d3c + 1017d18: e0bffa17 ldw r2,-24(fp) + 1017d1c: e0bff815 stw r2,-32(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1017d20: e0bff817 ldw r2,-32(fp) + 1017d24: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + *perr = OS_ERR_EVENT_TYPE; + 1017d28: e0fffe17 ldw r3,-8(fp) + 1017d2c: 00800044 movi r2,1 + 1017d30: 18800005 stb r2,0(r3) + return (0); + 1017d34: e03fff15 stw zero,-4(fp) + 1017d38: 00000d06 br 1017d70 + } + len = OS_StrCopy(pname, pgrp->OSFlagName); /* Copy name from OS_FLAG_GRP */ + 1017d3c: e0bffc17 ldw r2,-16(fp) + 1017d40: 11400284 addi r5,r2,10 + 1017d44: e13ffd17 ldw r4,-12(fp) + 1017d48: 1016dfc0 call 1016dfc + 1017d4c: e0bffb05 stb r2,-20(fp) + 1017d50: e0bffa17 ldw r2,-24(fp) + 1017d54: e0bff715 stw r2,-36(fp) + 1017d58: e0bff717 ldw r2,-36(fp) + 1017d5c: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + 1017d60: e0bffe17 ldw r2,-8(fp) + 1017d64: 10000005 stb zero,0(r2) + return (len); + 1017d68: e0bffb03 ldbu r2,-20(fp) + 1017d6c: e0bfff15 stw r2,-4(fp) + 1017d70: e0bfff17 ldw r2,-4(fp) +} + 1017d74: e037883a mov sp,fp + 1017d78: dfc00117 ldw ra,4(sp) + 1017d7c: df000017 ldw fp,0(sp) + 1017d80: dec00204 addi sp,sp,8 + 1017d84: f800283a ret + +01017d88 : +********************************************************************************************************* +*/ + +#if OS_FLAG_NAME_SIZE > 1 +void OSFlagNameSet (OS_FLAG_GRP *pgrp, INT8U *pname, INT8U *perr) +{ + 1017d88: defff504 addi sp,sp,-44 + 1017d8c: dfc00a15 stw ra,40(sp) + 1017d90: df000915 stw fp,36(sp) + 1017d94: df000904 addi fp,sp,36 + 1017d98: e13ffd15 stw r4,-12(fp) + 1017d9c: e17ffe15 stw r5,-8(fp) + 1017da0: e1bfff15 stw r6,-4(fp) + INT8U len; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 1017da4: e03ffb15 stw zero,-20(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + 1017da8: e0bfff17 ldw r2,-4(fp) + 1017dac: 1005003a cmpeq r2,r2,zero + 1017db0: 1000451e bne r2,zero,1017ec8 + return; + } + if (pgrp == (OS_FLAG_GRP *)0) { /* Is 'pgrp' a NULL pointer? */ + 1017db4: e0bffd17 ldw r2,-12(fp) + 1017db8: 1004c03a cmpne r2,r2,zero + 1017dbc: 1000041e bne r2,zero,1017dd0 + *perr = OS_ERR_FLAG_INVALID_PGRP; + 1017dc0: e0ffff17 ldw r3,-4(fp) + 1017dc4: 00801b84 movi r2,110 + 1017dc8: 18800005 stb r2,0(r3) + return; + 1017dcc: 00003e06 br 1017ec8 + } + if (pname == (INT8U *)0) { /* Is 'pname' a NULL pointer? */ + 1017dd0: e0bffe17 ldw r2,-8(fp) + 1017dd4: 1004c03a cmpne r2,r2,zero + 1017dd8: 1000041e bne r2,zero,1017dec + *perr = OS_ERR_PNAME_NULL; + 1017ddc: e0ffff17 ldw r3,-4(fp) + 1017de0: 00800304 movi r2,12 + 1017de4: 18800005 stb r2,0(r3) + return; + 1017de8: 00003706 br 1017ec8 + } +#endif + if (OSIntNesting > 0) { /* See if trying to call from an ISR */ + 1017dec: 008040b4 movhi r2,258 + 1017df0: 10952204 addi r2,r2,21640 + 1017df4: 10800003 ldbu r2,0(r2) + 1017df8: 10803fcc andi r2,r2,255 + 1017dfc: 1005003a cmpeq r2,r2,zero + 1017e00: 1000041e bne r2,zero,1017e14 + *perr = OS_ERR_NAME_SET_ISR; + 1017e04: e0ffff17 ldw r3,-4(fp) + 1017e08: 00800484 movi r2,18 + 1017e0c: 18800005 stb r2,0(r3) + return; + 1017e10: 00002d06 br 1017ec8 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1017e14: 0005303a rdctl r2,status + 1017e18: e0bffa15 stw r2,-24(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1017e1c: e0fffa17 ldw r3,-24(fp) + 1017e20: 00bfff84 movi r2,-2 + 1017e24: 1884703a and r2,r3,r2 + 1017e28: 1001703a wrctl status,r2 + + return context; + 1017e2c: e0bffa17 ldw r2,-24(fp) + } + OS_ENTER_CRITICAL(); + 1017e30: e0bffb15 stw r2,-20(fp) + if (pgrp->OSFlagType != OS_EVENT_TYPE_FLAG) { + 1017e34: e0bffd17 ldw r2,-12(fp) + 1017e38: 10800003 ldbu r2,0(r2) + 1017e3c: 10803fcc andi r2,r2,255 + 1017e40: 10800160 cmpeqi r2,r2,5 + 1017e44: 1000081e bne r2,zero,1017e68 + 1017e48: e0bffb17 ldw r2,-20(fp) + 1017e4c: e0bff915 stw r2,-28(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1017e50: e0bff917 ldw r2,-28(fp) + 1017e54: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + *perr = OS_ERR_EVENT_TYPE; + 1017e58: e0ffff17 ldw r3,-4(fp) + 1017e5c: 00800044 movi r2,1 + 1017e60: 18800005 stb r2,0(r3) + return; + 1017e64: 00001806 br 1017ec8 + } + len = OS_StrLen(pname); /* Can we fit the string in the storage area? */ + 1017e68: e13ffe17 ldw r4,-8(fp) + 1017e6c: 1016e7c0 call 1016e7c + 1017e70: e0bffc05 stb r2,-16(fp) + if (len > (OS_FLAG_NAME_SIZE - 1)) { /* No */ + 1017e74: e0bffc03 ldbu r2,-16(fp) + 1017e78: 10800830 cmpltui r2,r2,32 + 1017e7c: 1000081e bne r2,zero,1017ea0 + 1017e80: e0bffb17 ldw r2,-20(fp) + 1017e84: e0bff815 stw r2,-32(fp) + 1017e88: e0bff817 ldw r2,-32(fp) + 1017e8c: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + *perr = OS_ERR_FLAG_NAME_TOO_LONG; + 1017e90: e0ffff17 ldw r3,-4(fp) + 1017e94: 00801cc4 movi r2,115 + 1017e98: 18800005 stb r2,0(r3) + return; + 1017e9c: 00000a06 br 1017ec8 + } + (void)OS_StrCopy(pgrp->OSFlagName, pname); /* Yes, copy name from OS_FLAG_GRP */ + 1017ea0: e0bffd17 ldw r2,-12(fp) + 1017ea4: 11000284 addi r4,r2,10 + 1017ea8: e17ffe17 ldw r5,-8(fp) + 1017eac: 1016dfc0 call 1016dfc + 1017eb0: e0bffb17 ldw r2,-20(fp) + 1017eb4: e0bff715 stw r2,-36(fp) + 1017eb8: e0bff717 ldw r2,-36(fp) + 1017ebc: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + 1017ec0: e0bfff17 ldw r2,-4(fp) + 1017ec4: 10000005 stb zero,0(r2) + return; +} + 1017ec8: e037883a mov sp,fp + 1017ecc: dfc00117 ldw ra,4(sp) + 1017ed0: df000017 ldw fp,0(sp) + 1017ed4: dec00204 addi sp,sp,8 + 1017ed8: f800283a ret + +01017edc : +* event flags. +********************************************************************************************************* +*/ + +OS_FLAGS OSFlagPend (OS_FLAG_GRP *pgrp, OS_FLAGS flags, INT8U wait_type, INT16U timeout, INT8U *perr) +{ + 1017edc: deffe004 addi sp,sp,-128 + 1017ee0: dfc01f15 stw ra,124(sp) + 1017ee4: df001e15 stw fp,120(sp) + 1017ee8: df001e04 addi fp,sp,120 + 1017eec: e13ff915 stw r4,-28(fp) + 1017ef0: e17ffa0d sth r5,-24(fp) + 1017ef4: e1bffb05 stb r6,-20(fp) + 1017ef8: e1fffc0d sth r7,-16(fp) + OS_FLAGS flags_rdy; + INT8U result; + INT8U pend_stat; + BOOLEAN consume; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 1017efc: e03ff115 stw zero,-60(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + 1017f00: e0800217 ldw r2,8(fp) + 1017f04: 1004c03a cmpne r2,r2,zero + 1017f08: 1000021e bne r2,zero,1017f14 + return ((OS_FLAGS)0); + 1017f0c: e03fff15 stw zero,-4(fp) + 1017f10: 00017d06 br 1018508 + } + if (pgrp == (OS_FLAG_GRP *)0) { /* Validate 'pgrp' */ + 1017f14: e0bff917 ldw r2,-28(fp) + 1017f18: 1004c03a cmpne r2,r2,zero + 1017f1c: 1000051e bne r2,zero,1017f34 + *perr = OS_ERR_FLAG_INVALID_PGRP; + 1017f20: e0c00217 ldw r3,8(fp) + 1017f24: 00801b84 movi r2,110 + 1017f28: 18800005 stb r2,0(r3) + return ((OS_FLAGS)0); + 1017f2c: e03fff15 stw zero,-4(fp) + 1017f30: 00017506 br 1018508 + } +#endif + if (OSIntNesting > 0) { /* See if called from ISR ... */ + 1017f34: 008040b4 movhi r2,258 + 1017f38: 10952204 addi r2,r2,21640 + 1017f3c: 10800003 ldbu r2,0(r2) + 1017f40: 10803fcc andi r2,r2,255 + 1017f44: 1005003a cmpeq r2,r2,zero + 1017f48: 1000051e bne r2,zero,1017f60 + *perr = OS_ERR_PEND_ISR; /* ... can't PEND from an ISR */ + 1017f4c: e0c00217 ldw r3,8(fp) + 1017f50: 00800084 movi r2,2 + 1017f54: 18800005 stb r2,0(r3) + return ((OS_FLAGS)0); + 1017f58: e03fff15 stw zero,-4(fp) + 1017f5c: 00016a06 br 1018508 + } + if (OSLockNesting > 0) { /* See if called with scheduler locked ... */ + 1017f60: 008040b4 movhi r2,258 + 1017f64: 10951404 addi r2,r2,21584 + 1017f68: 10800003 ldbu r2,0(r2) + 1017f6c: 10803fcc andi r2,r2,255 + 1017f70: 1005003a cmpeq r2,r2,zero + 1017f74: 1000051e bne r2,zero,1017f8c + *perr = OS_ERR_PEND_LOCKED; /* ... can't PEND when locked */ + 1017f78: e0c00217 ldw r3,8(fp) + 1017f7c: 00800344 movi r2,13 + 1017f80: 18800005 stb r2,0(r3) + return ((OS_FLAGS)0); + 1017f84: e03fff15 stw zero,-4(fp) + 1017f88: 00015f06 br 1018508 + } + if (pgrp->OSFlagType != OS_EVENT_TYPE_FLAG) { /* Validate event block type */ + 1017f8c: e0bff917 ldw r2,-28(fp) + 1017f90: 10800003 ldbu r2,0(r2) + 1017f94: 10803fcc andi r2,r2,255 + 1017f98: 10800160 cmpeqi r2,r2,5 + 1017f9c: 1000051e bne r2,zero,1017fb4 + *perr = OS_ERR_EVENT_TYPE; + 1017fa0: e0c00217 ldw r3,8(fp) + 1017fa4: 00800044 movi r2,1 + 1017fa8: 18800005 stb r2,0(r3) + return ((OS_FLAGS)0); + 1017fac: e03fff15 stw zero,-4(fp) + 1017fb0: 00015506 br 1018508 + } + result = (INT8U)(wait_type & OS_FLAG_CONSUME); + 1017fb4: e0fffb03 ldbu r3,-20(fp) + 1017fb8: 00bfe004 movi r2,-128 + 1017fbc: 1884703a and r2,r3,r2 + 1017fc0: e0bff285 stb r2,-54(fp) + if (result != (INT8U)0) { /* See if we need to consume the flags */ + 1017fc4: e0bff283 ldbu r2,-54(fp) + 1017fc8: 1005003a cmpeq r2,r2,zero + 1017fcc: 1000071e bne r2,zero,1017fec + wait_type &= ~(INT8U)OS_FLAG_CONSUME; + 1017fd0: 00c01fc4 movi r3,127 + 1017fd4: e0bffb03 ldbu r2,-20(fp) + 1017fd8: 10c4703a and r2,r2,r3 + 1017fdc: e0bffb05 stb r2,-20(fp) + consume = OS_TRUE; + 1017fe0: 00800044 movi r2,1 + 1017fe4: e0bff205 stb r2,-56(fp) + 1017fe8: 00000106 br 1017ff0 + } else { + consume = OS_FALSE; + 1017fec: e03ff205 stb zero,-56(fp) +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1017ff0: 0005303a rdctl r2,status + 1017ff4: e0bff015 stw r2,-64(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1017ff8: e0fff017 ldw r3,-64(fp) + 1017ffc: 00bfff84 movi r2,-2 + 1018000: 1884703a and r2,r3,r2 + 1018004: 1001703a wrctl status,r2 + + return context; + 1018008: e0bff017 ldw r2,-64(fp) + } +/*$PAGE*/ + OS_ENTER_CRITICAL(); + 101800c: e0bff115 stw r2,-60(fp) + switch (wait_type) { + 1018010: e0bffb03 ldbu r2,-20(fp) + 1018014: e0bffe15 stw r2,-8(fp) + 1018018: e0fffe17 ldw r3,-8(fp) + 101801c: 18800060 cmpeqi r2,r3,1 + 1018020: 1000981e bne r2,zero,1018284 + 1018024: e0fffe17 ldw r3,-8(fp) + 1018028: 18800088 cmpgei r2,r3,2 + 101802c: 1000041e bne r2,zero,1018040 + 1018030: e0fffe17 ldw r3,-8(fp) + 1018034: 1805003a cmpeq r2,r3,zero + 1018038: 1000641e bne r2,zero,10181cc + 101803c: 0000bf06 br 101833c + 1018040: e0fffe17 ldw r3,-8(fp) + 1018044: 188000a0 cmpeqi r2,r3,2 + 1018048: 1000041e bne r2,zero,101805c + 101804c: e0fffe17 ldw r3,-8(fp) + 1018050: 188000e0 cmpeqi r2,r3,3 + 1018054: 10002f1e bne r2,zero,1018114 + 1018058: 0000b806 br 101833c + case OS_FLAG_WAIT_SET_ALL: /* See if all required flags are set */ + flags_rdy = (OS_FLAGS)(pgrp->OSFlagFlags & flags); /* Extract only the bits we want */ + 101805c: e0bff917 ldw r2,-28(fp) + 1018060: 10c0020b ldhu r3,8(r2) + 1018064: e0bffa0b ldhu r2,-24(fp) + 1018068: 1884703a and r2,r3,r2 + 101806c: e0bff30d sth r2,-52(fp) + if (flags_rdy == flags) { /* Must match ALL the bits that we want */ + 1018070: e0fff30b ldhu r3,-52(fp) + 1018074: e0bffa0b ldhu r2,-24(fp) + 1018078: 18801a1e bne r3,r2,10180e4 + if (consume == OS_TRUE) { /* See if we need to consume the flags */ + 101807c: e0bff203 ldbu r2,-56(fp) + 1018080: 10800058 cmpnei r2,r2,1 + 1018084: 1000091e bne r2,zero,10180ac + pgrp->OSFlagFlags &= ~flags_rdy; /* Clear ONLY the flags that we wanted */ + 1018088: e0bff917 ldw r2,-28(fp) + 101808c: 1080020b ldhu r2,8(r2) + 1018090: 1007883a mov r3,r2 + 1018094: e0bff30b ldhu r2,-52(fp) + 1018098: 0084303a nor r2,zero,r2 + 101809c: 1884703a and r2,r3,r2 + 10180a0: 1007883a mov r3,r2 + 10180a4: e0bff917 ldw r2,-28(fp) + 10180a8: 10c0020d sth r3,8(r2) + } + OSTCBCur->OSTCBFlagsRdy = flags_rdy; /* Save flags that were ready */ + 10180ac: 008040b4 movhi r2,258 + 10180b0: 10952304 addi r2,r2,21644 + 10180b4: 10c00017 ldw r3,0(r2) + 10180b8: e0bff30b ldhu r2,-52(fp) + 10180bc: 18800b0d sth r2,44(r3) + 10180c0: e0bff117 ldw r2,-60(fp) + 10180c4: e0bfef15 stw r2,-68(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 10180c8: e0bfef17 ldw r2,-68(fp) + 10180cc: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); /* Yes, condition met, return to caller */ + *perr = OS_ERR_NONE; + 10180d0: e0800217 ldw r2,8(fp) + 10180d4: 10000005 stb zero,0(r2) + return (flags_rdy); + 10180d8: e0bff30b ldhu r2,-52(fp) + 10180dc: e0bfff15 stw r2,-4(fp) + 10180e0: 00010906 br 1018508 + } else { /* Block task until events occur or timeout */ + OS_FlagBlock(pgrp, &node, flags, wait_type, timeout); + 10180e4: e1bffa0b ldhu r6,-24(fp) + 10180e8: e1fffb03 ldbu r7,-20(fp) + 10180ec: e0bffc0b ldhu r2,-16(fp) + 10180f0: e17ff404 addi r5,fp,-48 + 10180f4: d8800015 stw r2,0(sp) + 10180f8: e13ff917 ldw r4,-28(fp) + 10180fc: 1018a040 call 1018a04 + 1018100: e0bff117 ldw r2,-60(fp) + 1018104: e0bfee15 stw r2,-72(fp) + 1018108: e0bfee17 ldw r2,-72(fp) + 101810c: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + } + break; + 1018110: 00009506 br 1018368 + + case OS_FLAG_WAIT_SET_ANY: + flags_rdy = (OS_FLAGS)(pgrp->OSFlagFlags & flags); /* Extract only the bits we want */ + 1018114: e0bff917 ldw r2,-28(fp) + 1018118: 10c0020b ldhu r3,8(r2) + 101811c: e0bffa0b ldhu r2,-24(fp) + 1018120: 1884703a and r2,r3,r2 + 1018124: e0bff30d sth r2,-52(fp) + if (flags_rdy != (OS_FLAGS)0) { /* See if any flag set */ + 1018128: e0bff30b ldhu r2,-52(fp) + 101812c: 1005003a cmpeq r2,r2,zero + 1018130: 10001a1e bne r2,zero,101819c + if (consume == OS_TRUE) { /* See if we need to consume the flags */ + 1018134: e0bff203 ldbu r2,-56(fp) + 1018138: 10800058 cmpnei r2,r2,1 + 101813c: 1000091e bne r2,zero,1018164 + pgrp->OSFlagFlags &= ~flags_rdy; /* Clear ONLY the flags that we got */ + 1018140: e0bff917 ldw r2,-28(fp) + 1018144: 1080020b ldhu r2,8(r2) + 1018148: 1007883a mov r3,r2 + 101814c: e0bff30b ldhu r2,-52(fp) + 1018150: 0084303a nor r2,zero,r2 + 1018154: 1884703a and r2,r3,r2 + 1018158: 1007883a mov r3,r2 + 101815c: e0bff917 ldw r2,-28(fp) + 1018160: 10c0020d sth r3,8(r2) + } + OSTCBCur->OSTCBFlagsRdy = flags_rdy; /* Save flags that were ready */ + 1018164: 008040b4 movhi r2,258 + 1018168: 10952304 addi r2,r2,21644 + 101816c: 10c00017 ldw r3,0(r2) + 1018170: e0bff30b ldhu r2,-52(fp) + 1018174: 18800b0d sth r2,44(r3) + 1018178: e0bff117 ldw r2,-60(fp) + 101817c: e0bfed15 stw r2,-76(fp) + 1018180: e0bfed17 ldw r2,-76(fp) + 1018184: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); /* Yes, condition met, return to caller */ + *perr = OS_ERR_NONE; + 1018188: e0800217 ldw r2,8(fp) + 101818c: 10000005 stb zero,0(r2) + return (flags_rdy); + 1018190: e0fff30b ldhu r3,-52(fp) + 1018194: e0ffff15 stw r3,-4(fp) + 1018198: 0000db06 br 1018508 + } else { /* Block task until events occur or timeout */ + OS_FlagBlock(pgrp, &node, flags, wait_type, timeout); + 101819c: e1bffa0b ldhu r6,-24(fp) + 10181a0: e1fffb03 ldbu r7,-20(fp) + 10181a4: e0bffc0b ldhu r2,-16(fp) + 10181a8: e17ff404 addi r5,fp,-48 + 10181ac: d8800015 stw r2,0(sp) + 10181b0: e13ff917 ldw r4,-28(fp) + 10181b4: 1018a040 call 1018a04 + 10181b8: e0bff117 ldw r2,-60(fp) + 10181bc: e0bfec15 stw r2,-80(fp) + 10181c0: e0bfec17 ldw r2,-80(fp) + 10181c4: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + } + break; + 10181c8: 00006706 br 1018368 + +#if OS_FLAG_WAIT_CLR_EN > 0 + case OS_FLAG_WAIT_CLR_ALL: /* See if all required flags are cleared */ + flags_rdy = (OS_FLAGS)(~pgrp->OSFlagFlags & flags); /* Extract only the bits we want */ + 10181cc: e0bff917 ldw r2,-28(fp) + 10181d0: 1080020b ldhu r2,8(r2) + 10181d4: 0084303a nor r2,zero,r2 + 10181d8: 1007883a mov r3,r2 + 10181dc: e0bffa0b ldhu r2,-24(fp) + 10181e0: 1884703a and r2,r3,r2 + 10181e4: e0bff30d sth r2,-52(fp) + if (flags_rdy == flags) { /* Must match ALL the bits that we want */ + 10181e8: e0fff30b ldhu r3,-52(fp) + 10181ec: e0bffa0b ldhu r2,-24(fp) + 10181f0: 1880181e bne r3,r2,1018254 + if (consume == OS_TRUE) { /* See if we need to consume the flags */ + 10181f4: e0bff203 ldbu r2,-56(fp) + 10181f8: 10800058 cmpnei r2,r2,1 + 10181fc: 1000071e bne r2,zero,101821c + pgrp->OSFlagFlags |= flags_rdy; /* Set ONLY the flags that we wanted */ + 1018200: e0bff917 ldw r2,-28(fp) + 1018204: 10c0020b ldhu r3,8(r2) + 1018208: e0bff30b ldhu r2,-52(fp) + 101820c: 1884b03a or r2,r3,r2 + 1018210: 1007883a mov r3,r2 + 1018214: e0bff917 ldw r2,-28(fp) + 1018218: 10c0020d sth r3,8(r2) + } + OSTCBCur->OSTCBFlagsRdy = flags_rdy; /* Save flags that were ready */ + 101821c: 008040b4 movhi r2,258 + 1018220: 10952304 addi r2,r2,21644 + 1018224: 10c00017 ldw r3,0(r2) + 1018228: e0bff30b ldhu r2,-52(fp) + 101822c: 18800b0d sth r2,44(r3) + 1018230: e0bff117 ldw r2,-60(fp) + 1018234: e0bfeb15 stw r2,-84(fp) + 1018238: e0bfeb17 ldw r2,-84(fp) + 101823c: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); /* Yes, condition met, return to caller */ + *perr = OS_ERR_NONE; + 1018240: e0800217 ldw r2,8(fp) + 1018244: 10000005 stb zero,0(r2) + return (flags_rdy); + 1018248: e0bff30b ldhu r2,-52(fp) + 101824c: e0bfff15 stw r2,-4(fp) + 1018250: 0000ad06 br 1018508 + } else { /* Block task until events occur or timeout */ + OS_FlagBlock(pgrp, &node, flags, wait_type, timeout); + 1018254: e1bffa0b ldhu r6,-24(fp) + 1018258: e1fffb03 ldbu r7,-20(fp) + 101825c: e0bffc0b ldhu r2,-16(fp) + 1018260: e17ff404 addi r5,fp,-48 + 1018264: d8800015 stw r2,0(sp) + 1018268: e13ff917 ldw r4,-28(fp) + 101826c: 1018a040 call 1018a04 + 1018270: e0bff117 ldw r2,-60(fp) + 1018274: e0bfea15 stw r2,-88(fp) + 1018278: e0bfea17 ldw r2,-88(fp) + 101827c: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + } + break; + 1018280: 00003906 br 1018368 + + case OS_FLAG_WAIT_CLR_ANY: + flags_rdy = (OS_FLAGS)(~pgrp->OSFlagFlags & flags); /* Extract only the bits we want */ + 1018284: e0bff917 ldw r2,-28(fp) + 1018288: 1080020b ldhu r2,8(r2) + 101828c: 0084303a nor r2,zero,r2 + 1018290: 1007883a mov r3,r2 + 1018294: e0bffa0b ldhu r2,-24(fp) + 1018298: 1884703a and r2,r3,r2 + 101829c: e0bff30d sth r2,-52(fp) + if (flags_rdy != (OS_FLAGS)0) { /* See if any flag cleared */ + 10182a0: e0bff30b ldhu r2,-52(fp) + 10182a4: 1005003a cmpeq r2,r2,zero + 10182a8: 1000181e bne r2,zero,101830c + if (consume == OS_TRUE) { /* See if we need to consume the flags */ + 10182ac: e0bff203 ldbu r2,-56(fp) + 10182b0: 10800058 cmpnei r2,r2,1 + 10182b4: 1000071e bne r2,zero,10182d4 + pgrp->OSFlagFlags |= flags_rdy; /* Set ONLY the flags that we got */ + 10182b8: e0bff917 ldw r2,-28(fp) + 10182bc: 10c0020b ldhu r3,8(r2) + 10182c0: e0bff30b ldhu r2,-52(fp) + 10182c4: 1884b03a or r2,r3,r2 + 10182c8: 1007883a mov r3,r2 + 10182cc: e0bff917 ldw r2,-28(fp) + 10182d0: 10c0020d sth r3,8(r2) + } + OSTCBCur->OSTCBFlagsRdy = flags_rdy; /* Save flags that were ready */ + 10182d4: 008040b4 movhi r2,258 + 10182d8: 10952304 addi r2,r2,21644 + 10182dc: 10c00017 ldw r3,0(r2) + 10182e0: e0bff30b ldhu r2,-52(fp) + 10182e4: 18800b0d sth r2,44(r3) + 10182e8: e0bff117 ldw r2,-60(fp) + 10182ec: e0bfe915 stw r2,-92(fp) + 10182f0: e0bfe917 ldw r2,-92(fp) + 10182f4: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); /* Yes, condition met, return to caller */ + *perr = OS_ERR_NONE; + 10182f8: e0800217 ldw r2,8(fp) + 10182fc: 10000005 stb zero,0(r2) + return (flags_rdy); + 1018300: e0fff30b ldhu r3,-52(fp) + 1018304: e0ffff15 stw r3,-4(fp) + 1018308: 00007f06 br 1018508 + } else { /* Block task until events occur or timeout */ + OS_FlagBlock(pgrp, &node, flags, wait_type, timeout); + 101830c: e1bffa0b ldhu r6,-24(fp) + 1018310: e1fffb03 ldbu r7,-20(fp) + 1018314: e0bffc0b ldhu r2,-16(fp) + 1018318: e17ff404 addi r5,fp,-48 + 101831c: d8800015 stw r2,0(sp) + 1018320: e13ff917 ldw r4,-28(fp) + 1018324: 1018a040 call 1018a04 + 1018328: e0bff117 ldw r2,-60(fp) + 101832c: e0bfe815 stw r2,-96(fp) + 1018330: e0bfe817 ldw r2,-96(fp) + 1018334: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + } + break; + 1018338: 00000b06 br 1018368 + 101833c: e0bff117 ldw r2,-60(fp) + 1018340: e0bfe715 stw r2,-100(fp) + 1018344: e0bfe717 ldw r2,-100(fp) + 1018348: 1001703a wrctl status,r2 +#endif + + default: + OS_EXIT_CRITICAL(); + flags_rdy = (OS_FLAGS)0; + 101834c: e03ff30d sth zero,-52(fp) + *perr = OS_ERR_FLAG_WAIT_TYPE; + 1018350: e0c00217 ldw r3,8(fp) + 1018354: 00801bc4 movi r2,111 + 1018358: 18800005 stb r2,0(r3) + return (flags_rdy); + 101835c: e0bff30b ldhu r2,-52(fp) + 1018360: e0bfff15 stw r2,-4(fp) + 1018364: 00006806 br 1018508 + } +/*$PAGE*/ + OS_Sched(); /* Find next HPT ready to run */ + 1018368: 1016cb80 call 1016cb8 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 101836c: 0005303a rdctl r2,status + 1018370: e0bfe615 stw r2,-104(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1018374: e0ffe617 ldw r3,-104(fp) + 1018378: 00bfff84 movi r2,-2 + 101837c: 1884703a and r2,r3,r2 + 1018380: 1001703a wrctl status,r2 + + return context; + 1018384: e0bfe617 ldw r2,-104(fp) + OS_ENTER_CRITICAL(); + 1018388: e0bff115 stw r2,-60(fp) + if (OSTCBCur->OSTCBStatPend != OS_STAT_PEND_OK) { /* Have we timed-out or aborted? */ + 101838c: 008040b4 movhi r2,258 + 1018390: 10952304 addi r2,r2,21644 + 1018394: 10800017 ldw r2,0(r2) + 1018398: 10800c43 ldbu r2,49(r2) + 101839c: 10803fcc andi r2,r2,255 + 10183a0: 1005003a cmpeq r2,r2,zero + 10183a4: 1000221e bne r2,zero,1018430 + pend_stat = OSTCBCur->OSTCBStatPend; + 10183a8: 008040b4 movhi r2,258 + 10183ac: 10952304 addi r2,r2,21644 + 10183b0: 10800017 ldw r2,0(r2) + 10183b4: 10800c43 ldbu r2,49(r2) + 10183b8: e0bff245 stb r2,-55(fp) + OSTCBCur->OSTCBStatPend = OS_STAT_PEND_OK; + 10183bc: 008040b4 movhi r2,258 + 10183c0: 10952304 addi r2,r2,21644 + 10183c4: 10800017 ldw r2,0(r2) + 10183c8: 10000c45 stb zero,49(r2) + OS_FlagUnlink(&node); + 10183cc: e13ff404 addi r4,fp,-48 + 10183d0: 1018dbc0 call 1018dbc + OSTCBCur->OSTCBStat = OS_STAT_RDY; /* Yes, make task ready-to-run */ + 10183d4: 008040b4 movhi r2,258 + 10183d8: 10952304 addi r2,r2,21644 + 10183dc: 10800017 ldw r2,0(r2) + 10183e0: 10000c05 stb zero,48(r2) + 10183e4: e0bff117 ldw r2,-60(fp) + 10183e8: e0bfe515 stw r2,-108(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 10183ec: e0bfe517 ldw r2,-108(fp) + 10183f0: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + flags_rdy = (OS_FLAGS)0; + 10183f4: e03ff30d sth zero,-52(fp) + switch (pend_stat) { + 10183f8: e0bff243 ldbu r2,-55(fp) + 10183fc: 108000a0 cmpeqi r2,r2,2 + 1018400: 1000011e bne r2,zero,1018408 + 1018404: 00000406 br 1018418 + case OS_STAT_PEND_ABORT: + *perr = OS_ERR_PEND_ABORT; /* Indicate that we aborted waiting */ + 1018408: e0c00217 ldw r3,8(fp) + 101840c: 00800384 movi r2,14 + 1018410: 18800005 stb r2,0(r3) + break; + 1018414: 00000306 br 1018424 + + case OS_STAT_PEND_TO: + default: + *perr = OS_ERR_TIMEOUT; /* Indicate that we timed-out waiting */ + 1018418: e0c00217 ldw r3,8(fp) + 101841c: 00800284 movi r2,10 + 1018420: 18800005 stb r2,0(r3) + break; + } + return (flags_rdy); + 1018424: e0fff30b ldhu r3,-52(fp) + 1018428: e0ffff15 stw r3,-4(fp) + 101842c: 00003606 br 1018508 + } + flags_rdy = OSTCBCur->OSTCBFlagsRdy; + 1018430: 008040b4 movhi r2,258 + 1018434: 10952304 addi r2,r2,21644 + 1018438: 10800017 ldw r2,0(r2) + 101843c: 10800b0b ldhu r2,44(r2) + 1018440: e0bff30d sth r2,-52(fp) + if (consume == OS_TRUE) { /* See if we need to consume the flags */ + 1018444: e0bff203 ldbu r2,-56(fp) + 1018448: 10800058 cmpnei r2,r2,1 + 101844c: 1000261e bne r2,zero,10184e8 + switch (wait_type) { + 1018450: e0bffb03 ldbu r2,-20(fp) + 1018454: e0bffd15 stw r2,-12(fp) + 1018458: e0fffd17 ldw r3,-12(fp) + 101845c: 1804803a cmplt r2,r3,zero + 1018460: 1000181e bne r2,zero,10184c4 + 1018464: e0fffd17 ldw r3,-12(fp) + 1018468: 18800090 cmplti r2,r3,2 + 101846c: 10000d1e bne r2,zero,10184a4 + 1018470: e0fffd17 ldw r3,-12(fp) + 1018474: 18800108 cmpgei r2,r3,4 + 1018478: 1000121e bne r2,zero,10184c4 + case OS_FLAG_WAIT_SET_ALL: + case OS_FLAG_WAIT_SET_ANY: /* Clear ONLY the flags we got */ + pgrp->OSFlagFlags &= ~flags_rdy; + 101847c: e0bff917 ldw r2,-28(fp) + 1018480: 1080020b ldhu r2,8(r2) + 1018484: 1007883a mov r3,r2 + 1018488: e0bff30b ldhu r2,-52(fp) + 101848c: 0084303a nor r2,zero,r2 + 1018490: 1884703a and r2,r3,r2 + 1018494: 1007883a mov r3,r2 + 1018498: e0bff917 ldw r2,-28(fp) + 101849c: 10c0020d sth r3,8(r2) + break; + 10184a0: 00001106 br 10184e8 + +#if OS_FLAG_WAIT_CLR_EN > 0 + case OS_FLAG_WAIT_CLR_ALL: + case OS_FLAG_WAIT_CLR_ANY: /* Set ONLY the flags we got */ + pgrp->OSFlagFlags |= flags_rdy; + 10184a4: e0bff917 ldw r2,-28(fp) + 10184a8: 10c0020b ldhu r3,8(r2) + 10184ac: e0bff30b ldhu r2,-52(fp) + 10184b0: 1884b03a or r2,r3,r2 + 10184b4: 1007883a mov r3,r2 + 10184b8: e0bff917 ldw r2,-28(fp) + 10184bc: 10c0020d sth r3,8(r2) + break; + 10184c0: 00000906 br 10184e8 + 10184c4: e0bff117 ldw r2,-60(fp) + 10184c8: e0bfe415 stw r2,-112(fp) + 10184cc: e0bfe417 ldw r2,-112(fp) + 10184d0: 1001703a wrctl status,r2 +#endif + default: + OS_EXIT_CRITICAL(); + *perr = OS_ERR_FLAG_WAIT_TYPE; + 10184d4: e0c00217 ldw r3,8(fp) + 10184d8: 00801bc4 movi r2,111 + 10184dc: 18800005 stb r2,0(r3) + return ((OS_FLAGS)0); + 10184e0: e03fff15 stw zero,-4(fp) + 10184e4: 00000806 br 1018508 + 10184e8: e0bff117 ldw r2,-60(fp) + 10184ec: e0bfe315 stw r2,-116(fp) + 10184f0: e0bfe317 ldw r2,-116(fp) + 10184f4: 1001703a wrctl status,r2 + } + } + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; /* Event(s) must have occurred */ + 10184f8: e0800217 ldw r2,8(fp) + 10184fc: 10000005 stb zero,0(r2) + return (flags_rdy); + 1018500: e0bff30b ldhu r2,-52(fp) + 1018504: e0bfff15 stw r2,-4(fp) + 1018508: e0bfff17 ldw r2,-4(fp) +} + 101850c: e037883a mov sp,fp + 1018510: dfc00117 ldw ra,4(sp) + 1018514: df000017 ldw fp,0(sp) + 1018518: dec00204 addi sp,sp,8 + 101851c: f800283a ret + +01018520 : +* Called from: Task ONLY +********************************************************************************************************* +*/ + +OS_FLAGS OSFlagPendGetFlagsRdy (void) +{ + 1018520: defffb04 addi sp,sp,-20 + 1018524: df000415 stw fp,16(sp) + 1018528: df000404 addi fp,sp,16 + OS_FLAGS flags; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 101852c: e03ffe15 stw zero,-8(fp) +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1018530: 0005303a rdctl r2,status + 1018534: e0bffd15 stw r2,-12(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1018538: e0fffd17 ldw r3,-12(fp) + 101853c: 00bfff84 movi r2,-2 + 1018540: 1884703a and r2,r3,r2 + 1018544: 1001703a wrctl status,r2 + + return context; + 1018548: e0bffd17 ldw r2,-12(fp) +#endif + + + + OS_ENTER_CRITICAL(); + 101854c: e0bffe15 stw r2,-8(fp) + flags = OSTCBCur->OSTCBFlagsRdy; + 1018550: 008040b4 movhi r2,258 + 1018554: 10952304 addi r2,r2,21644 + 1018558: 10800017 ldw r2,0(r2) + 101855c: 10800b0b ldhu r2,44(r2) + 1018560: e0bfff0d sth r2,-4(fp) + 1018564: e0bffe17 ldw r2,-8(fp) + 1018568: e0bffc15 stw r2,-16(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 101856c: e0bffc17 ldw r2,-16(fp) + 1018570: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (flags); + 1018574: e0bfff0b ldhu r2,-4(fp) +} + 1018578: e037883a mov sp,fp + 101857c: df000017 ldw fp,0(sp) + 1018580: dec00104 addi sp,sp,4 + 1018584: f800283a ret + +01018588 : +* 2) The amount of time interrupts are DISABLED depends on the number of tasks waiting on +* the event flag group. +********************************************************************************************************* +*/ +OS_FLAGS OSFlagPost (OS_FLAG_GRP *pgrp, OS_FLAGS flags, INT8U opt, INT8U *perr) +{ + 1018588: deffed04 addi sp,sp,-76 + 101858c: dfc01215 stw ra,72(sp) + 1018590: df001115 stw fp,68(sp) + 1018594: df001104 addi fp,sp,68 + 1018598: e13ff915 stw r4,-28(fp) + 101859c: e1fffc15 stw r7,-16(fp) + 10185a0: e17ffa0d sth r5,-24(fp) + 10185a4: e1bffb05 stb r6,-20(fp) + BOOLEAN sched; + OS_FLAGS flags_cur; + OS_FLAGS flags_rdy; + BOOLEAN rdy; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 10185a8: e03ff515 stw zero,-44(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + 10185ac: e0bffc17 ldw r2,-16(fp) + 10185b0: 1004c03a cmpne r2,r2,zero + 10185b4: 1000021e bne r2,zero,10185c0 + return ((OS_FLAGS)0); + 10185b8: e03fff15 stw zero,-4(fp) + 10185bc: 0000d606 br 1018918 + } + if (pgrp == (OS_FLAG_GRP *)0) { /* Validate 'pgrp' */ + 10185c0: e0bff917 ldw r2,-28(fp) + 10185c4: 1004c03a cmpne r2,r2,zero + 10185c8: 1000051e bne r2,zero,10185e0 + *perr = OS_ERR_FLAG_INVALID_PGRP; + 10185cc: e0fffc17 ldw r3,-16(fp) + 10185d0: 00801b84 movi r2,110 + 10185d4: 18800005 stb r2,0(r3) + return ((OS_FLAGS)0); + 10185d8: e03fff15 stw zero,-4(fp) + 10185dc: 0000ce06 br 1018918 + } +#endif + if (pgrp->OSFlagType != OS_EVENT_TYPE_FLAG) { /* Make sure we are pointing to an event flag grp */ + 10185e0: e0bff917 ldw r2,-28(fp) + 10185e4: 10800003 ldbu r2,0(r2) + 10185e8: 10803fcc andi r2,r2,255 + 10185ec: 10800160 cmpeqi r2,r2,5 + 10185f0: 1000051e bne r2,zero,1018608 + *perr = OS_ERR_EVENT_TYPE; + 10185f4: e0fffc17 ldw r3,-16(fp) + 10185f8: 00800044 movi r2,1 + 10185fc: 18800005 stb r2,0(r3) + return ((OS_FLAGS)0); + 1018600: e03fff15 stw zero,-4(fp) + 1018604: 0000c406 br 1018918 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1018608: 0005303a rdctl r2,status + 101860c: e0bff415 stw r2,-48(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1018610: e0fff417 ldw r3,-48(fp) + 1018614: 00bfff84 movi r2,-2 + 1018618: 1884703a and r2,r3,r2 + 101861c: 1001703a wrctl status,r2 + + return context; + 1018620: e0bff417 ldw r2,-48(fp) + } +/*$PAGE*/ + OS_ENTER_CRITICAL(); + 1018624: e0bff515 stw r2,-44(fp) + switch (opt) { + 1018628: e0bffb03 ldbu r2,-20(fp) + 101862c: e0bffe15 stw r2,-8(fp) + 1018630: e0fffe17 ldw r3,-8(fp) + 1018634: 1805003a cmpeq r2,r3,zero + 1018638: 1000041e bne r2,zero,101864c + 101863c: e0fffe17 ldw r3,-8(fp) + 1018640: 18800060 cmpeqi r2,r3,1 + 1018644: 10000b1e bne r2,zero,1018674 + 1018648: 00001206 br 1018694 + case OS_FLAG_CLR: + pgrp->OSFlagFlags &= ~flags; /* Clear the flags specified in the group */ + 101864c: e0bff917 ldw r2,-28(fp) + 1018650: 1080020b ldhu r2,8(r2) + 1018654: 1007883a mov r3,r2 + 1018658: e0bffa0b ldhu r2,-24(fp) + 101865c: 0084303a nor r2,zero,r2 + 1018660: 1884703a and r2,r3,r2 + 1018664: 1007883a mov r3,r2 + 1018668: e0bff917 ldw r2,-28(fp) + 101866c: 10c0020d sth r3,8(r2) + break; + 1018670: 00001106 br 10186b8 + + case OS_FLAG_SET: + pgrp->OSFlagFlags |= flags; /* Set the flags specified in the group */ + 1018674: e0bff917 ldw r2,-28(fp) + 1018678: 10c0020b ldhu r3,8(r2) + 101867c: e0bffa0b ldhu r2,-24(fp) + 1018680: 1884b03a or r2,r3,r2 + 1018684: 1007883a mov r3,r2 + 1018688: e0bff917 ldw r2,-28(fp) + 101868c: 10c0020d sth r3,8(r2) + break; + 1018690: 00000906 br 10186b8 + 1018694: e0bff517 ldw r2,-44(fp) + 1018698: e0bff315 stw r2,-52(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 101869c: e0bff317 ldw r2,-52(fp) + 10186a0: 1001703a wrctl status,r2 + + default: + OS_EXIT_CRITICAL(); /* INVALID option */ + *perr = OS_ERR_FLAG_INVALID_OPT; + 10186a4: e0fffc17 ldw r3,-16(fp) + 10186a8: 00801c44 movi r2,113 + 10186ac: 18800005 stb r2,0(r3) + return ((OS_FLAGS)0); + 10186b0: e03fff15 stw zero,-4(fp) + 10186b4: 00009806 br 1018918 + } + sched = OS_FALSE; /* Indicate that we don't need rescheduling */ + 10186b8: e03ff785 stb zero,-34(fp) + pnode = (OS_FLAG_NODE *)pgrp->OSFlagWaitList; + 10186bc: e0bff917 ldw r2,-28(fp) + 10186c0: 10800117 ldw r2,4(r2) + 10186c4: e0bff815 stw r2,-32(fp) + while (pnode != (OS_FLAG_NODE *)0) { /* Go through all tasks waiting on event flag(s) */ + 10186c8: 00007506 br 10188a0 + switch (pnode->OSFlagNodeWaitType) { + 10186cc: e0bff817 ldw r2,-32(fp) + 10186d0: 10800483 ldbu r2,18(r2) + 10186d4: 10803fcc andi r2,r2,255 + 10186d8: e0bffd15 stw r2,-12(fp) + 10186dc: e0fffd17 ldw r3,-12(fp) + 10186e0: 18800060 cmpeqi r2,r3,1 + 10186e4: 10004d1e bne r2,zero,101881c + 10186e8: e0fffd17 ldw r3,-12(fp) + 10186ec: 18800088 cmpgei r2,r3,2 + 10186f0: 1000041e bne r2,zero,1018704 + 10186f4: e0fffd17 ldw r3,-12(fp) + 10186f8: 1805003a cmpeq r2,r3,zero + 10186fc: 1000301e bne r2,zero,10187c0 + 1018700: 00005b06 br 1018870 + 1018704: e0fffd17 ldw r3,-12(fp) + 1018708: 188000a0 cmpeqi r2,r3,2 + 101870c: 1000041e bne r2,zero,1018720 + 1018710: e0fffd17 ldw r3,-12(fp) + 1018714: 188000e0 cmpeqi r2,r3,3 + 1018718: 1000161e bne r2,zero,1018774 + 101871c: 00005406 br 1018870 + case OS_FLAG_WAIT_SET_ALL: /* See if all req. flags are set for current node */ + flags_rdy = (OS_FLAGS)(pgrp->OSFlagFlags & pnode->OSFlagNodeFlags); + 1018720: e0bff917 ldw r2,-28(fp) + 1018724: 10c0020b ldhu r3,8(r2) + 1018728: e0bff817 ldw r2,-32(fp) + 101872c: 1080040b ldhu r2,16(r2) + 1018730: 1884703a and r2,r3,r2 + 1018734: e0bff68d sth r2,-38(fp) + if (flags_rdy == pnode->OSFlagNodeFlags) { + 1018738: e0bff817 ldw r2,-32(fp) + 101873c: 1080040b ldhu r2,16(r2) + 1018740: 10ffffcc andi r3,r2,65535 + 1018744: e0bff68b ldhu r2,-38(fp) + 1018748: 1880521e bne r3,r2,1018894 + rdy = OS_FlagTaskRdy(pnode, flags_rdy); /* Make task RTR, event(s) Rx'd */ + 101874c: e17ff68b ldhu r5,-38(fp) + 1018750: e13ff817 ldw r4,-32(fp) + 1018754: 1018cac0 call 1018cac + 1018758: e0bff605 stb r2,-40(fp) + if (rdy == OS_TRUE) { + 101875c: e0bff603 ldbu r2,-40(fp) + 1018760: 10800058 cmpnei r2,r2,1 + 1018764: 10004b1e bne r2,zero,1018894 + sched = OS_TRUE; /* When done we will reschedule */ + 1018768: 00800044 movi r2,1 + 101876c: e0bff785 stb r2,-34(fp) + } + } + break; + 1018770: 00004806 br 1018894 + + case OS_FLAG_WAIT_SET_ANY: /* See if any flag set */ + flags_rdy = (OS_FLAGS)(pgrp->OSFlagFlags & pnode->OSFlagNodeFlags); + 1018774: e0bff917 ldw r2,-28(fp) + 1018778: 10c0020b ldhu r3,8(r2) + 101877c: e0bff817 ldw r2,-32(fp) + 1018780: 1080040b ldhu r2,16(r2) + 1018784: 1884703a and r2,r3,r2 + 1018788: e0bff68d sth r2,-38(fp) + if (flags_rdy != (OS_FLAGS)0) { + 101878c: e0bff68b ldhu r2,-38(fp) + 1018790: 1005003a cmpeq r2,r2,zero + 1018794: 10003f1e bne r2,zero,1018894 + rdy = OS_FlagTaskRdy(pnode, flags_rdy); /* Make task RTR, event(s) Rx'd */ + 1018798: e17ff68b ldhu r5,-38(fp) + 101879c: e13ff817 ldw r4,-32(fp) + 10187a0: 1018cac0 call 1018cac + 10187a4: e0bff605 stb r2,-40(fp) + if (rdy == OS_TRUE) { + 10187a8: e0bff603 ldbu r2,-40(fp) + 10187ac: 10800058 cmpnei r2,r2,1 + 10187b0: 1000381e bne r2,zero,1018894 + sched = OS_TRUE; /* When done we will reschedule */ + 10187b4: 00800044 movi r2,1 + 10187b8: e0bff785 stb r2,-34(fp) + } + } + break; + 10187bc: 00003506 br 1018894 + +#if OS_FLAG_WAIT_CLR_EN > 0 + case OS_FLAG_WAIT_CLR_ALL: /* See if all req. flags are set for current node */ + flags_rdy = (OS_FLAGS)(~pgrp->OSFlagFlags & pnode->OSFlagNodeFlags); + 10187c0: e0bff917 ldw r2,-28(fp) + 10187c4: 1080020b ldhu r2,8(r2) + 10187c8: 0084303a nor r2,zero,r2 + 10187cc: 1007883a mov r3,r2 + 10187d0: e0bff817 ldw r2,-32(fp) + 10187d4: 1080040b ldhu r2,16(r2) + 10187d8: 1884703a and r2,r3,r2 + 10187dc: e0bff68d sth r2,-38(fp) + if (flags_rdy == pnode->OSFlagNodeFlags) { + 10187e0: e0bff817 ldw r2,-32(fp) + 10187e4: 1080040b ldhu r2,16(r2) + 10187e8: 10ffffcc andi r3,r2,65535 + 10187ec: e0bff68b ldhu r2,-38(fp) + 10187f0: 1880281e bne r3,r2,1018894 + rdy = OS_FlagTaskRdy(pnode, flags_rdy); /* Make task RTR, event(s) Rx'd */ + 10187f4: e17ff68b ldhu r5,-38(fp) + 10187f8: e13ff817 ldw r4,-32(fp) + 10187fc: 1018cac0 call 1018cac + 1018800: e0bff605 stb r2,-40(fp) + if (rdy == OS_TRUE) { + 1018804: e0bff603 ldbu r2,-40(fp) + 1018808: 10800058 cmpnei r2,r2,1 + 101880c: 1000211e bne r2,zero,1018894 + sched = OS_TRUE; /* When done we will reschedule */ + 1018810: 00800044 movi r2,1 + 1018814: e0bff785 stb r2,-34(fp) + } + } + break; + 1018818: 00001e06 br 1018894 + + case OS_FLAG_WAIT_CLR_ANY: /* See if any flag set */ + flags_rdy = (OS_FLAGS)(~pgrp->OSFlagFlags & pnode->OSFlagNodeFlags); + 101881c: e0bff917 ldw r2,-28(fp) + 1018820: 1080020b ldhu r2,8(r2) + 1018824: 0084303a nor r2,zero,r2 + 1018828: 1007883a mov r3,r2 + 101882c: e0bff817 ldw r2,-32(fp) + 1018830: 1080040b ldhu r2,16(r2) + 1018834: 1884703a and r2,r3,r2 + 1018838: e0bff68d sth r2,-38(fp) + if (flags_rdy != (OS_FLAGS)0) { + 101883c: e0bff68b ldhu r2,-38(fp) + 1018840: 1005003a cmpeq r2,r2,zero + 1018844: 1000131e bne r2,zero,1018894 + rdy = OS_FlagTaskRdy(pnode, flags_rdy); /* Make task RTR, event(s) Rx'd */ + 1018848: e17ff68b ldhu r5,-38(fp) + 101884c: e13ff817 ldw r4,-32(fp) + 1018850: 1018cac0 call 1018cac + 1018854: e0bff605 stb r2,-40(fp) + if (rdy == OS_TRUE) { + 1018858: e0bff603 ldbu r2,-40(fp) + 101885c: 10800058 cmpnei r2,r2,1 + 1018860: 10000c1e bne r2,zero,1018894 + sched = OS_TRUE; /* When done we will reschedule */ + 1018864: 00800044 movi r2,1 + 1018868: e0bff785 stb r2,-34(fp) + } + } + break; + 101886c: 00000906 br 1018894 + 1018870: e0bff517 ldw r2,-44(fp) + 1018874: e0bff215 stw r2,-56(fp) + 1018878: e0bff217 ldw r2,-56(fp) + 101887c: 1001703a wrctl status,r2 +#endif + default: + OS_EXIT_CRITICAL(); + *perr = OS_ERR_FLAG_WAIT_TYPE; + 1018880: e0fffc17 ldw r3,-16(fp) + 1018884: 00801bc4 movi r2,111 + 1018888: 18800005 stb r2,0(r3) + return ((OS_FLAGS)0); + 101888c: e03fff15 stw zero,-4(fp) + 1018890: 00002106 br 1018918 + } + pnode = (OS_FLAG_NODE *)pnode->OSFlagNodeNext; /* Point to next task waiting for event flag(s) */ + 1018894: e0bff817 ldw r2,-32(fp) + 1018898: 10800017 ldw r2,0(r2) + 101889c: e0bff815 stw r2,-32(fp) + *perr = OS_ERR_FLAG_INVALID_OPT; + return ((OS_FLAGS)0); + } + sched = OS_FALSE; /* Indicate that we don't need rescheduling */ + pnode = (OS_FLAG_NODE *)pgrp->OSFlagWaitList; + while (pnode != (OS_FLAG_NODE *)0) { /* Go through all tasks waiting on event flag(s) */ + 10188a0: e0bff817 ldw r2,-32(fp) + 10188a4: 1004c03a cmpne r2,r2,zero + 10188a8: 103f881e bne r2,zero,10186cc + 10188ac: e0bff517 ldw r2,-44(fp) + 10188b0: e0bff115 stw r2,-60(fp) + 10188b4: e0bff117 ldw r2,-60(fp) + 10188b8: 1001703a wrctl status,r2 + return ((OS_FLAGS)0); + } + pnode = (OS_FLAG_NODE *)pnode->OSFlagNodeNext; /* Point to next task waiting for event flag(s) */ + } + OS_EXIT_CRITICAL(); + if (sched == OS_TRUE) { + 10188bc: e0bff783 ldbu r2,-34(fp) + 10188c0: 10800058 cmpnei r2,r2,1 + 10188c4: 1000011e bne r2,zero,10188cc + OS_Sched(); + 10188c8: 1016cb80 call 1016cb8 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 10188cc: 0005303a rdctl r2,status + 10188d0: e0bff015 stw r2,-64(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 10188d4: e0fff017 ldw r3,-64(fp) + 10188d8: 00bfff84 movi r2,-2 + 10188dc: 1884703a and r2,r3,r2 + 10188e0: 1001703a wrctl status,r2 + + return context; + 10188e4: e0bff017 ldw r2,-64(fp) + } + OS_ENTER_CRITICAL(); + 10188e8: e0bff515 stw r2,-44(fp) + flags_cur = pgrp->OSFlagFlags; + 10188ec: e0bff917 ldw r2,-28(fp) + 10188f0: 1080020b ldhu r2,8(r2) + 10188f4: e0bff70d sth r2,-36(fp) + 10188f8: e0bff517 ldw r2,-44(fp) + 10188fc: e0bfef15 stw r2,-68(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1018900: e0bfef17 ldw r2,-68(fp) + 1018904: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + 1018908: e0bffc17 ldw r2,-16(fp) + 101890c: 10000005 stb zero,0(r2) + return (flags_cur); + 1018910: e0bff70b ldhu r2,-36(fp) + 1018914: e0bfff15 stw r2,-4(fp) + 1018918: e0bfff17 ldw r2,-4(fp) +} + 101891c: e037883a mov sp,fp + 1018920: dfc00117 ldw ra,4(sp) + 1018924: df000017 ldw fp,0(sp) + 1018928: dec00204 addi sp,sp,8 + 101892c: f800283a ret + +01018930 : +********************************************************************************************************* +*/ + +#if OS_FLAG_QUERY_EN > 0 +OS_FLAGS OSFlagQuery (OS_FLAG_GRP *pgrp, INT8U *perr) +{ + 1018930: defff804 addi sp,sp,-32 + 1018934: df000715 stw fp,28(sp) + 1018938: df000704 addi fp,sp,28 + 101893c: e13ffd15 stw r4,-12(fp) + 1018940: e17ffe15 stw r5,-8(fp) + OS_FLAGS flags; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 1018944: e03ffb15 stw zero,-20(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + 1018948: e0bffe17 ldw r2,-8(fp) + 101894c: 1004c03a cmpne r2,r2,zero + 1018950: 1000021e bne r2,zero,101895c + return ((OS_FLAGS)0); + 1018954: e03fff15 stw zero,-4(fp) + 1018958: 00002506 br 10189f0 + } + if (pgrp == (OS_FLAG_GRP *)0) { /* Validate 'pgrp' */ + 101895c: e0bffd17 ldw r2,-12(fp) + 1018960: 1004c03a cmpne r2,r2,zero + 1018964: 1000051e bne r2,zero,101897c + *perr = OS_ERR_FLAG_INVALID_PGRP; + 1018968: e0fffe17 ldw r3,-8(fp) + 101896c: 00801b84 movi r2,110 + 1018970: 18800005 stb r2,0(r3) + return ((OS_FLAGS)0); + 1018974: e03fff15 stw zero,-4(fp) + 1018978: 00001d06 br 10189f0 + } +#endif + if (pgrp->OSFlagType != OS_EVENT_TYPE_FLAG) { /* Validate event block type */ + 101897c: e0bffd17 ldw r2,-12(fp) + 1018980: 10800003 ldbu r2,0(r2) + 1018984: 10803fcc andi r2,r2,255 + 1018988: 10800160 cmpeqi r2,r2,5 + 101898c: 1000051e bne r2,zero,10189a4 + *perr = OS_ERR_EVENT_TYPE; + 1018990: e0fffe17 ldw r3,-8(fp) + 1018994: 00800044 movi r2,1 + 1018998: 18800005 stb r2,0(r3) + return ((OS_FLAGS)0); + 101899c: e03fff15 stw zero,-4(fp) + 10189a0: 00001306 br 10189f0 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 10189a4: 0005303a rdctl r2,status + 10189a8: e0bffa15 stw r2,-24(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 10189ac: e0fffa17 ldw r3,-24(fp) + 10189b0: 00bfff84 movi r2,-2 + 10189b4: 1884703a and r2,r3,r2 + 10189b8: 1001703a wrctl status,r2 + + return context; + 10189bc: e0bffa17 ldw r2,-24(fp) + } + OS_ENTER_CRITICAL(); + 10189c0: e0bffb15 stw r2,-20(fp) + flags = pgrp->OSFlagFlags; + 10189c4: e0bffd17 ldw r2,-12(fp) + 10189c8: 1080020b ldhu r2,8(r2) + 10189cc: e0bffc0d sth r2,-16(fp) + 10189d0: e0bffb17 ldw r2,-20(fp) + 10189d4: e0bff915 stw r2,-28(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 10189d8: e0bff917 ldw r2,-28(fp) + 10189dc: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + 10189e0: e0bffe17 ldw r2,-8(fp) + 10189e4: 10000005 stb zero,0(r2) + return (flags); /* Return the current value of the event flags */ + 10189e8: e0bffc0b ldhu r2,-16(fp) + 10189ec: e0bfff15 stw r2,-4(fp) + 10189f0: e0bfff17 ldw r2,-4(fp) +} + 10189f4: e037883a mov sp,fp + 10189f8: df000017 ldw fp,0(sp) + 10189fc: dec00104 addi sp,sp,4 + 1018a00: f800283a ret + +01018a04 : +* Note(s) : This function is INTERNAL to uC/OS-II and your application should not call it. +********************************************************************************************************* +*/ + +static void OS_FlagBlock (OS_FLAG_GRP *pgrp, OS_FLAG_NODE *pnode, OS_FLAGS flags, INT8U wait_type, INT16U timeout) +{ + 1018a04: defff804 addi sp,sp,-32 + 1018a08: df000715 stw fp,28(sp) + 1018a0c: df000704 addi fp,sp,28 + 1018a10: e13ffb15 stw r4,-20(fp) + 1018a14: e17ffc15 stw r5,-16(fp) + 1018a18: e0800117 ldw r2,4(fp) + 1018a1c: e1bffd0d sth r6,-12(fp) + 1018a20: e1fffe05 stb r7,-8(fp) + 1018a24: e0bfff0d sth r2,-4(fp) + OS_FLAG_NODE *pnode_next; + INT8U y; + + + OSTCBCur->OSTCBStat |= OS_STAT_FLAG; + 1018a28: 008040b4 movhi r2,258 + 1018a2c: 10952304 addi r2,r2,21644 + 1018a30: 10c00017 ldw r3,0(r2) + 1018a34: 008040b4 movhi r2,258 + 1018a38: 10952304 addi r2,r2,21644 + 1018a3c: 10800017 ldw r2,0(r2) + 1018a40: 10800c03 ldbu r2,48(r2) + 1018a44: 10800814 ori r2,r2,32 + 1018a48: 18800c05 stb r2,48(r3) + OSTCBCur->OSTCBStatPend = OS_STAT_PEND_OK; + 1018a4c: 008040b4 movhi r2,258 + 1018a50: 10952304 addi r2,r2,21644 + 1018a54: 10800017 ldw r2,0(r2) + 1018a58: 10000c45 stb zero,49(r2) + OSTCBCur->OSTCBDly = timeout; /* Store timeout in task's TCB */ + 1018a5c: 008040b4 movhi r2,258 + 1018a60: 10952304 addi r2,r2,21644 + 1018a64: 10c00017 ldw r3,0(r2) + 1018a68: e0bfff0b ldhu r2,-4(fp) + 1018a6c: 18800b8d sth r2,46(r3) +#if OS_TASK_DEL_EN > 0 + OSTCBCur->OSTCBFlagNode = pnode; /* TCB to link to node */ + 1018a70: 008040b4 movhi r2,258 + 1018a74: 10952304 addi r2,r2,21644 + 1018a78: 10c00017 ldw r3,0(r2) + 1018a7c: e0bffc17 ldw r2,-16(fp) + 1018a80: 18800a15 stw r2,40(r3) +#endif + pnode->OSFlagNodeFlags = flags; /* Save the flags that we need to wait for */ + 1018a84: e0fffc17 ldw r3,-16(fp) + 1018a88: e0bffd0b ldhu r2,-12(fp) + 1018a8c: 1880040d sth r2,16(r3) + pnode->OSFlagNodeWaitType = wait_type; /* Save the type of wait we are doing */ + 1018a90: e0fffc17 ldw r3,-16(fp) + 1018a94: e0bffe03 ldbu r2,-8(fp) + 1018a98: 18800485 stb r2,18(r3) + pnode->OSFlagNodeTCB = (void *)OSTCBCur; /* Link to task's TCB */ + 1018a9c: 008040b4 movhi r2,258 + 1018aa0: 10952304 addi r2,r2,21644 + 1018aa4: 10c00017 ldw r3,0(r2) + 1018aa8: e0bffc17 ldw r2,-16(fp) + 1018aac: 10c00215 stw r3,8(r2) + pnode->OSFlagNodeNext = pgrp->OSFlagWaitList; /* Add node at beginning of event flag wait list */ + 1018ab0: e0bffb17 ldw r2,-20(fp) + 1018ab4: 10c00117 ldw r3,4(r2) + 1018ab8: e0bffc17 ldw r2,-16(fp) + 1018abc: 10c00015 stw r3,0(r2) + pnode->OSFlagNodePrev = (void *)0; + 1018ac0: e0bffc17 ldw r2,-16(fp) + 1018ac4: 10000115 stw zero,4(r2) + pnode->OSFlagNodeFlagGrp = (void *)pgrp; /* Link to Event Flag Group */ + 1018ac8: e0fffc17 ldw r3,-16(fp) + 1018acc: e0bffb17 ldw r2,-20(fp) + 1018ad0: 18800315 stw r2,12(r3) + pnode_next = (OS_FLAG_NODE *)pgrp->OSFlagWaitList; + 1018ad4: e0bffb17 ldw r2,-20(fp) + 1018ad8: 10800117 ldw r2,4(r2) + 1018adc: e0bffa15 stw r2,-24(fp) + if (pnode_next != (void *)0) { /* Is this the first NODE to insert? */ + 1018ae0: e0bffa17 ldw r2,-24(fp) + 1018ae4: 1005003a cmpeq r2,r2,zero + 1018ae8: 1000031e bne r2,zero,1018af8 + pnode_next->OSFlagNodePrev = pnode; /* No, link in doubly linked list */ + 1018aec: e0fffa17 ldw r3,-24(fp) + 1018af0: e0bffc17 ldw r2,-16(fp) + 1018af4: 18800115 stw r2,4(r3) + } + pgrp->OSFlagWaitList = (void *)pnode; + 1018af8: e0fffb17 ldw r3,-20(fp) + 1018afc: e0bffc17 ldw r2,-16(fp) + 1018b00: 18800115 stw r2,4(r3) + + y = OSTCBCur->OSTCBY; /* Suspend current task until flag(s) received */ + 1018b04: 008040b4 movhi r2,258 + 1018b08: 10952304 addi r2,r2,21644 + 1018b0c: 10800017 ldw r2,0(r2) + 1018b10: 10800d03 ldbu r2,52(r2) + 1018b14: e0bff905 stb r2,-28(fp) + OSRdyTbl[y] &= ~OSTCBCur->OSTCBBitX; + 1018b18: e13ff903 ldbu r4,-28(fp) + 1018b1c: e0fff903 ldbu r3,-28(fp) + 1018b20: 008040b4 movhi r2,258 + 1018b24: 10952044 addi r2,r2,21633 + 1018b28: 10c5883a add r2,r2,r3 + 1018b2c: 10800003 ldbu r2,0(r2) + 1018b30: 1007883a mov r3,r2 + 1018b34: 008040b4 movhi r2,258 + 1018b38: 10952304 addi r2,r2,21644 + 1018b3c: 10800017 ldw r2,0(r2) + 1018b40: 10800d43 ldbu r2,53(r2) + 1018b44: 0084303a nor r2,zero,r2 + 1018b48: 1884703a and r2,r3,r2 + 1018b4c: 1007883a mov r3,r2 + 1018b50: 008040b4 movhi r2,258 + 1018b54: 10952044 addi r2,r2,21633 + 1018b58: 1105883a add r2,r2,r4 + 1018b5c: 10c00005 stb r3,0(r2) + if (OSRdyTbl[y] == 0x00) { + 1018b60: e0fff903 ldbu r3,-28(fp) + 1018b64: 008040b4 movhi r2,258 + 1018b68: 10952044 addi r2,r2,21633 + 1018b6c: 10c5883a add r2,r2,r3 + 1018b70: 10800003 ldbu r2,0(r2) + 1018b74: 10803fcc andi r2,r2,255 + 1018b78: 1004c03a cmpne r2,r2,zero + 1018b7c: 10000e1e bne r2,zero,1018bb8 + OSRdyGrp &= ~OSTCBCur->OSTCBBitY; + 1018b80: 008040b4 movhi r2,258 + 1018b84: 10952304 addi r2,r2,21644 + 1018b88: 10800017 ldw r2,0(r2) + 1018b8c: 10800d83 ldbu r2,54(r2) + 1018b90: 0084303a nor r2,zero,r2 + 1018b94: 1007883a mov r3,r2 + 1018b98: 008040b4 movhi r2,258 + 1018b9c: 10952004 addi r2,r2,21632 + 1018ba0: 10800003 ldbu r2,0(r2) + 1018ba4: 1884703a and r2,r3,r2 + 1018ba8: 1007883a mov r3,r2 + 1018bac: 008040b4 movhi r2,258 + 1018bb0: 10952004 addi r2,r2,21632 + 1018bb4: 10c00005 stb r3,0(r2) + } +} + 1018bb8: e037883a mov sp,fp + 1018bbc: df000017 ldw fp,0(sp) + 1018bc0: dec00104 addi sp,sp,4 + 1018bc4: f800283a ret + +01018bc8 : +* WARNING : You MUST NOT call this function from your code. This is an INTERNAL function to uC/OS-II. +********************************************************************************************************* +*/ + +void OS_FlagInit (void) +{ + 1018bc8: defffb04 addi sp,sp,-20 + 1018bcc: dfc00415 stw ra,16(sp) + 1018bd0: df000315 stw fp,12(sp) + 1018bd4: df000304 addi fp,sp,12 + INT16U i; + OS_FLAG_GRP *pgrp1; + OS_FLAG_GRP *pgrp2; + + + OS_MemClr((INT8U *)&OSFlagTbl[0], sizeof(OSFlagTbl)); /* Clear the flag group table */ + 1018bd8: 010040f4 movhi r4,259 + 1018bdc: 21273d04 addi r4,r4,-25356 + 1018be0: 0140dc04 movi r5,880 + 1018be4: 1016bf80 call 1016bf8 + pgrp1 = &OSFlagTbl[0]; + 1018be8: 008040f4 movhi r2,259 + 1018bec: 10a73d04 addi r2,r2,-25356 + 1018bf0: e0bffe15 stw r2,-8(fp) + pgrp2 = &OSFlagTbl[1]; + 1018bf4: 008040f4 movhi r2,259 + 1018bf8: 10a74804 addi r2,r2,-25312 + 1018bfc: e0bffd15 stw r2,-12(fp) + for (i = 0; i < (OS_MAX_FLAGS - 1); i++) { /* Init. list of free EVENT FLAGS */ + 1018c00: e03fff0d sth zero,-4(fp) + 1018c04: 00001306 br 1018c54 + pgrp1->OSFlagType = OS_EVENT_TYPE_UNUSED; + 1018c08: e0bffe17 ldw r2,-8(fp) + 1018c0c: 10000005 stb zero,0(r2) + pgrp1->OSFlagWaitList = (void *)pgrp2; + 1018c10: e0fffe17 ldw r3,-8(fp) + 1018c14: e0bffd17 ldw r2,-12(fp) + 1018c18: 18800115 stw r2,4(r3) +#if OS_FLAG_NAME_SIZE > 1 + pgrp1->OSFlagName[0] = '?'; /* Unknown name */ + 1018c1c: e0fffe17 ldw r3,-8(fp) + 1018c20: 00800fc4 movi r2,63 + 1018c24: 18800285 stb r2,10(r3) + pgrp1->OSFlagName[1] = OS_ASCII_NUL; + 1018c28: e0bffe17 ldw r2,-8(fp) + 1018c2c: 100002c5 stb zero,11(r2) +#endif + pgrp1++; + 1018c30: e0bffe17 ldw r2,-8(fp) + 1018c34: 10800b04 addi r2,r2,44 + 1018c38: e0bffe15 stw r2,-8(fp) + pgrp2++; + 1018c3c: e0bffd17 ldw r2,-12(fp) + 1018c40: 10800b04 addi r2,r2,44 + 1018c44: e0bffd15 stw r2,-12(fp) + + + OS_MemClr((INT8U *)&OSFlagTbl[0], sizeof(OSFlagTbl)); /* Clear the flag group table */ + pgrp1 = &OSFlagTbl[0]; + pgrp2 = &OSFlagTbl[1]; + for (i = 0; i < (OS_MAX_FLAGS - 1); i++) { /* Init. list of free EVENT FLAGS */ + 1018c48: e0bfff0b ldhu r2,-4(fp) + 1018c4c: 10800044 addi r2,r2,1 + 1018c50: e0bfff0d sth r2,-4(fp) + 1018c54: e0bfff0b ldhu r2,-4(fp) + 1018c58: 108004f0 cmpltui r2,r2,19 + 1018c5c: 103fea1e bne r2,zero,1018c08 + pgrp1->OSFlagName[1] = OS_ASCII_NUL; +#endif + pgrp1++; + pgrp2++; + } + pgrp1->OSFlagType = OS_EVENT_TYPE_UNUSED; + 1018c60: e0bffe17 ldw r2,-8(fp) + 1018c64: 10000005 stb zero,0(r2) + pgrp1->OSFlagWaitList = (void *)0; + 1018c68: e0bffe17 ldw r2,-8(fp) + 1018c6c: 10000115 stw zero,4(r2) +#if OS_FLAG_NAME_SIZE > 1 + pgrp1->OSFlagName[0] = '?'; /* Unknown name */ + 1018c70: e0fffe17 ldw r3,-8(fp) + 1018c74: 00800fc4 movi r2,63 + 1018c78: 18800285 stb r2,10(r3) + pgrp1->OSFlagName[1] = OS_ASCII_NUL; + 1018c7c: e0bffe17 ldw r2,-8(fp) + 1018c80: 100002c5 stb zero,11(r2) +#endif + OSFlagFreeList = &OSFlagTbl[0]; + 1018c84: 00c040b4 movhi r3,258 + 1018c88: 18d52504 addi r3,r3,21652 + 1018c8c: 008040f4 movhi r2,259 + 1018c90: 10a73d04 addi r2,r2,-25356 + 1018c94: 18800015 stw r2,0(r3) +#endif +} + 1018c98: e037883a mov sp,fp + 1018c9c: dfc00117 ldw ra,4(sp) + 1018ca0: df000017 ldw fp,0(sp) + 1018ca4: dec00204 addi sp,sp,8 + 1018ca8: f800283a ret + +01018cac : +* 2) This function is INTERNAL to uC/OS-II and your application should not call it. +********************************************************************************************************* +*/ + +static BOOLEAN OS_FlagTaskRdy (OS_FLAG_NODE *pnode, OS_FLAGS flags_rdy) +{ + 1018cac: defffa04 addi sp,sp,-24 + 1018cb0: dfc00515 stw ra,20(sp) + 1018cb4: df000415 stw fp,16(sp) + 1018cb8: df000404 addi fp,sp,16 + 1018cbc: e13ffe15 stw r4,-8(fp) + 1018cc0: e17fff0d sth r5,-4(fp) + OS_TCB *ptcb; + BOOLEAN sched; + + + ptcb = (OS_TCB *)pnode->OSFlagNodeTCB; /* Point to TCB of waiting task */ + 1018cc4: e0bffe17 ldw r2,-8(fp) + 1018cc8: 10800217 ldw r2,8(r2) + 1018ccc: e0bffd15 stw r2,-12(fp) + ptcb->OSTCBDly = 0; + 1018cd0: e0bffd17 ldw r2,-12(fp) + 1018cd4: 10000b8d sth zero,46(r2) + ptcb->OSTCBFlagsRdy = flags_rdy; + 1018cd8: e0fffd17 ldw r3,-12(fp) + 1018cdc: e0bfff0b ldhu r2,-4(fp) + 1018ce0: 18800b0d sth r2,44(r3) + ptcb->OSTCBStat &= ~(INT8U)OS_STAT_FLAG; + 1018ce4: e0bffd17 ldw r2,-12(fp) + 1018ce8: 10c00c03 ldbu r3,48(r2) + 1018cec: 00bff7c4 movi r2,-33 + 1018cf0: 1884703a and r2,r3,r2 + 1018cf4: 1007883a mov r3,r2 + 1018cf8: e0bffd17 ldw r2,-12(fp) + 1018cfc: 10c00c05 stb r3,48(r2) + ptcb->OSTCBStatPend = OS_STAT_PEND_OK; + 1018d00: e0bffd17 ldw r2,-12(fp) + 1018d04: 10000c45 stb zero,49(r2) + if (ptcb->OSTCBStat == OS_STAT_RDY) { /* Task now ready? */ + 1018d08: e0bffd17 ldw r2,-12(fp) + 1018d0c: 10800c03 ldbu r2,48(r2) + 1018d10: 10803fcc andi r2,r2,255 + 1018d14: 1004c03a cmpne r2,r2,zero + 1018d18: 10001f1e bne r2,zero,1018d98 + OSRdyGrp |= ptcb->OSTCBBitY; /* Put task into ready list */ + 1018d1c: e0bffd17 ldw r2,-12(fp) + 1018d20: 10c00d83 ldbu r3,54(r2) + 1018d24: 008040b4 movhi r2,258 + 1018d28: 10952004 addi r2,r2,21632 + 1018d2c: 10800003 ldbu r2,0(r2) + 1018d30: 1884b03a or r2,r3,r2 + 1018d34: 1007883a mov r3,r2 + 1018d38: 008040b4 movhi r2,258 + 1018d3c: 10952004 addi r2,r2,21632 + 1018d40: 10c00005 stb r3,0(r2) + OSRdyTbl[ptcb->OSTCBY] |= ptcb->OSTCBBitX; + 1018d44: e0bffd17 ldw r2,-12(fp) + 1018d48: 10800d03 ldbu r2,52(r2) + 1018d4c: 11003fcc andi r4,r2,255 + 1018d50: e0bffd17 ldw r2,-12(fp) + 1018d54: 10800d03 ldbu r2,52(r2) + 1018d58: 10c03fcc andi r3,r2,255 + 1018d5c: 008040b4 movhi r2,258 + 1018d60: 10952044 addi r2,r2,21633 + 1018d64: 10c5883a add r2,r2,r3 + 1018d68: 10c00003 ldbu r3,0(r2) + 1018d6c: e0bffd17 ldw r2,-12(fp) + 1018d70: 10800d43 ldbu r2,53(r2) + 1018d74: 1884b03a or r2,r3,r2 + 1018d78: 1007883a mov r3,r2 + 1018d7c: 008040b4 movhi r2,258 + 1018d80: 10952044 addi r2,r2,21633 + 1018d84: 1105883a add r2,r2,r4 + 1018d88: 10c00005 stb r3,0(r2) + sched = OS_TRUE; + 1018d8c: 00800044 movi r2,1 + 1018d90: e0bffc05 stb r2,-16(fp) + 1018d94: 00000106 br 1018d9c + } else { + sched = OS_FALSE; + 1018d98: e03ffc05 stb zero,-16(fp) + } + OS_FlagUnlink(pnode); + 1018d9c: e13ffe17 ldw r4,-8(fp) + 1018da0: 1018dbc0 call 1018dbc + return (sched); + 1018da4: e0bffc03 ldbu r2,-16(fp) +} + 1018da8: e037883a mov sp,fp + 1018dac: dfc00117 ldw ra,4(sp) + 1018db0: df000017 ldw fp,0(sp) + 1018db4: dec00204 addi sp,sp,8 + 1018db8: f800283a ret + +01018dbc : +* 2) This function is INTERNAL to uC/OS-II and your application should not call it. +********************************************************************************************************* +*/ + +void OS_FlagUnlink (OS_FLAG_NODE *pnode) +{ + 1018dbc: defffa04 addi sp,sp,-24 + 1018dc0: df000515 stw fp,20(sp) + 1018dc4: df000504 addi fp,sp,20 + 1018dc8: e13fff15 stw r4,-4(fp) + OS_FLAG_GRP *pgrp; + OS_FLAG_NODE *pnode_prev; + OS_FLAG_NODE *pnode_next; + + + pnode_prev = (OS_FLAG_NODE *)pnode->OSFlagNodePrev; + 1018dcc: e0bfff17 ldw r2,-4(fp) + 1018dd0: 10800117 ldw r2,4(r2) + 1018dd4: e0bffc15 stw r2,-16(fp) + pnode_next = (OS_FLAG_NODE *)pnode->OSFlagNodeNext; + 1018dd8: e0bfff17 ldw r2,-4(fp) + 1018ddc: 10800017 ldw r2,0(r2) + 1018de0: e0bffb15 stw r2,-20(fp) + if (pnode_prev == (OS_FLAG_NODE *)0) { /* Is it first node in wait list? */ + 1018de4: e0bffc17 ldw r2,-16(fp) + 1018de8: 1004c03a cmpne r2,r2,zero + 1018dec: 10000c1e bne r2,zero,1018e20 + pgrp = (OS_FLAG_GRP *)pnode->OSFlagNodeFlagGrp; + 1018df0: e0bfff17 ldw r2,-4(fp) + 1018df4: 10800317 ldw r2,12(r2) + 1018df8: e0bffd15 stw r2,-12(fp) + pgrp->OSFlagWaitList = (void *)pnode_next; /* Update list for new 1st node */ + 1018dfc: e0fffd17 ldw r3,-12(fp) + 1018e00: e0bffb17 ldw r2,-20(fp) + 1018e04: 18800115 stw r2,4(r3) + if (pnode_next != (OS_FLAG_NODE *)0) { + 1018e08: e0bffb17 ldw r2,-20(fp) + 1018e0c: 1005003a cmpeq r2,r2,zero + 1018e10: 10000c1e bne r2,zero,1018e44 + pnode_next->OSFlagNodePrev = (OS_FLAG_NODE *)0; /* Link new 1st node PREV to NULL */ + 1018e14: e0bffb17 ldw r2,-20(fp) + 1018e18: 10000115 stw zero,4(r2) + 1018e1c: 00000906 br 1018e44 + } + } else { /* No, A node somewhere in the list */ + pnode_prev->OSFlagNodeNext = pnode_next; /* Link around the node to unlink */ + 1018e20: e0fffc17 ldw r3,-16(fp) + 1018e24: e0bffb17 ldw r2,-20(fp) + 1018e28: 18800015 stw r2,0(r3) + if (pnode_next != (OS_FLAG_NODE *)0) { /* Was this the LAST node? */ + 1018e2c: e0bffb17 ldw r2,-20(fp) + 1018e30: 1005003a cmpeq r2,r2,zero + 1018e34: 1000031e bne r2,zero,1018e44 + pnode_next->OSFlagNodePrev = pnode_prev; /* No, Link around current node */ + 1018e38: e0fffb17 ldw r3,-20(fp) + 1018e3c: e0bffc17 ldw r2,-16(fp) + 1018e40: 18800115 stw r2,4(r3) + } + } +#if OS_TASK_DEL_EN > 0 + ptcb = (OS_TCB *)pnode->OSFlagNodeTCB; + 1018e44: e0bfff17 ldw r2,-4(fp) + 1018e48: 10800217 ldw r2,8(r2) + 1018e4c: e0bffe15 stw r2,-8(fp) + ptcb->OSTCBFlagNode = (OS_FLAG_NODE *)0; + 1018e50: e0bffe17 ldw r2,-8(fp) + 1018e54: 10000a15 stw zero,40(r2) +#endif +} + 1018e58: e037883a mov sp,fp + 1018e5c: df000017 ldw fp,0(sp) + 1018e60: dec00104 addi sp,sp,4 + 1018e64: f800283a ret + +01018e68 : +* free partition is available. +********************************************************************************************************* +*/ + +OS_MEM *OSMemCreate (void *addr, INT32U nblks, INT32U blksize, INT8U *perr) +{ + 1018e68: defff304 addi sp,sp,-52 + 1018e6c: df000c15 stw fp,48(sp) + 1018e70: df000c04 addi fp,sp,48 + 1018e74: e13ffb15 stw r4,-20(fp) + 1018e78: e17ffc15 stw r5,-16(fp) + 1018e7c: e1bffd15 stw r6,-12(fp) + 1018e80: e1fffe15 stw r7,-8(fp) + OS_MEM *pmem; + INT8U *pblk; + void **plink; + INT32U i; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 1018e84: e03ff615 stw zero,-40(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + 1018e88: e0bffe17 ldw r2,-8(fp) + 1018e8c: 1004c03a cmpne r2,r2,zero + 1018e90: 1000021e bne r2,zero,1018e9c + return ((OS_MEM *)0); + 1018e94: e03fff15 stw zero,-4(fp) + 1018e98: 00007506 br 1019070 + } + if (addr == (void *)0) { /* Must pass a valid address for the memory part.*/ + 1018e9c: e0bffb17 ldw r2,-20(fp) + 1018ea0: 1004c03a cmpne r2,r2,zero + 1018ea4: 1000051e bne r2,zero,1018ebc + *perr = OS_ERR_MEM_INVALID_ADDR; + 1018ea8: e0fffe17 ldw r3,-8(fp) + 1018eac: 00801884 movi r2,98 + 1018eb0: 18800005 stb r2,0(r3) + return ((OS_MEM *)0); + 1018eb4: e03fff15 stw zero,-4(fp) + 1018eb8: 00006d06 br 1019070 + } + if (((INT32U)addr & (sizeof(void *) - 1)) != 0){ /* Must be pointer size aligned */ + 1018ebc: e0bffb17 ldw r2,-20(fp) + 1018ec0: 108000cc andi r2,r2,3 + 1018ec4: 1005003a cmpeq r2,r2,zero + 1018ec8: 1000051e bne r2,zero,1018ee0 + *perr = OS_ERR_MEM_INVALID_ADDR; + 1018ecc: e0fffe17 ldw r3,-8(fp) + 1018ed0: 00801884 movi r2,98 + 1018ed4: 18800005 stb r2,0(r3) + return ((OS_MEM *)0); + 1018ed8: e03fff15 stw zero,-4(fp) + 1018edc: 00006406 br 1019070 + } + if (nblks < 2) { /* Must have at least 2 blocks per partition */ + 1018ee0: e0bffc17 ldw r2,-16(fp) + 1018ee4: 108000a8 cmpgeui r2,r2,2 + 1018ee8: 1000051e bne r2,zero,1018f00 + *perr = OS_ERR_MEM_INVALID_BLKS; + 1018eec: e0fffe17 ldw r3,-8(fp) + 1018ef0: 008016c4 movi r2,91 + 1018ef4: 18800005 stb r2,0(r3) + return ((OS_MEM *)0); + 1018ef8: e03fff15 stw zero,-4(fp) + 1018efc: 00005c06 br 1019070 + } + if (blksize < sizeof(void *)) { /* Must contain space for at least a pointer */ + 1018f00: e0bffd17 ldw r2,-12(fp) + 1018f04: 10800128 cmpgeui r2,r2,4 + 1018f08: 1000051e bne r2,zero,1018f20 + *perr = OS_ERR_MEM_INVALID_SIZE; + 1018f0c: e0fffe17 ldw r3,-8(fp) + 1018f10: 00801704 movi r2,92 + 1018f14: 18800005 stb r2,0(r3) + return ((OS_MEM *)0); + 1018f18: e03fff15 stw zero,-4(fp) + 1018f1c: 00005406 br 1019070 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1018f20: 0005303a rdctl r2,status + 1018f24: e0bff515 stw r2,-44(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1018f28: e0fff517 ldw r3,-44(fp) + 1018f2c: 00bfff84 movi r2,-2 + 1018f30: 1884703a and r2,r3,r2 + 1018f34: 1001703a wrctl status,r2 + + return context; + 1018f38: e0bff517 ldw r2,-44(fp) + } +#endif + OS_ENTER_CRITICAL(); + 1018f3c: e0bff615 stw r2,-40(fp) + pmem = OSMemFreeList; /* Get next free memory partition */ + 1018f40: 008040b4 movhi r2,258 + 1018f44: 10951d04 addi r2,r2,21620 + 1018f48: 10800017 ldw r2,0(r2) + 1018f4c: e0bffa15 stw r2,-24(fp) + if (OSMemFreeList != (OS_MEM *)0) { /* See if pool of free partitions was empty */ + 1018f50: 008040b4 movhi r2,258 + 1018f54: 10951d04 addi r2,r2,21620 + 1018f58: 10800017 ldw r2,0(r2) + 1018f5c: 1005003a cmpeq r2,r2,zero + 1018f60: 1000081e bne r2,zero,1018f84 + OSMemFreeList = (OS_MEM *)OSMemFreeList->OSMemFreeList; + 1018f64: 008040b4 movhi r2,258 + 1018f68: 10951d04 addi r2,r2,21620 + 1018f6c: 10800017 ldw r2,0(r2) + 1018f70: 10800117 ldw r2,4(r2) + 1018f74: 1007883a mov r3,r2 + 1018f78: 008040b4 movhi r2,258 + 1018f7c: 10951d04 addi r2,r2,21620 + 1018f80: 10c00015 stw r3,0(r2) + 1018f84: e0bff617 ldw r2,-40(fp) + 1018f88: e0bff415 stw r2,-48(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1018f8c: e0bff417 ldw r2,-48(fp) + 1018f90: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); + if (pmem == (OS_MEM *)0) { /* See if we have a memory partition */ + 1018f94: e0bffa17 ldw r2,-24(fp) + 1018f98: 1004c03a cmpne r2,r2,zero + 1018f9c: 1000051e bne r2,zero,1018fb4 + *perr = OS_ERR_MEM_INVALID_PART; + 1018fa0: e0fffe17 ldw r3,-8(fp) + 1018fa4: 00801684 movi r2,90 + 1018fa8: 18800005 stb r2,0(r3) + return ((OS_MEM *)0); + 1018fac: e03fff15 stw zero,-4(fp) + 1018fb0: 00002f06 br 1019070 + } + plink = (void **)addr; /* Create linked list of free memory blocks */ + 1018fb4: e0bffb17 ldw r2,-20(fp) + 1018fb8: e0bff815 stw r2,-32(fp) + pblk = (INT8U *)((INT32U)addr + blksize); + 1018fbc: e0bffb17 ldw r2,-20(fp) + 1018fc0: 1007883a mov r3,r2 + 1018fc4: e0bffd17 ldw r2,-12(fp) + 1018fc8: 1885883a add r2,r3,r2 + 1018fcc: e0bff915 stw r2,-28(fp) + for (i = 0; i < (nblks - 1); i++) { + 1018fd0: e03ff715 stw zero,-36(fp) + 1018fd4: 00000d06 br 101900c + *plink = (void *)pblk; /* Save pointer to NEXT block in CURRENT block */ + 1018fd8: e0fff817 ldw r3,-32(fp) + 1018fdc: e0bff917 ldw r2,-28(fp) + 1018fe0: 18800015 stw r2,0(r3) + plink = (void **)pblk; /* Position to NEXT block */ + 1018fe4: e0bff917 ldw r2,-28(fp) + 1018fe8: e0bff815 stw r2,-32(fp) + pblk = (INT8U *)((INT32U)pblk + blksize); /* Point to the FOLLOWING block */ + 1018fec: e0bff917 ldw r2,-28(fp) + 1018ff0: 1007883a mov r3,r2 + 1018ff4: e0bffd17 ldw r2,-12(fp) + 1018ff8: 1885883a add r2,r3,r2 + 1018ffc: e0bff915 stw r2,-28(fp) + *perr = OS_ERR_MEM_INVALID_PART; + return ((OS_MEM *)0); + } + plink = (void **)addr; /* Create linked list of free memory blocks */ + pblk = (INT8U *)((INT32U)addr + blksize); + for (i = 0; i < (nblks - 1); i++) { + 1019000: e0bff717 ldw r2,-36(fp) + 1019004: 10800044 addi r2,r2,1 + 1019008: e0bff715 stw r2,-36(fp) + 101900c: e0bffc17 ldw r2,-16(fp) + 1019010: 10ffffc4 addi r3,r2,-1 + 1019014: e0bff717 ldw r2,-36(fp) + 1019018: 10ffef36 bltu r2,r3,1018fd8 + *plink = (void *)pblk; /* Save pointer to NEXT block in CURRENT block */ + plink = (void **)pblk; /* Position to NEXT block */ + pblk = (INT8U *)((INT32U)pblk + blksize); /* Point to the FOLLOWING block */ + } + *plink = (void *)0; /* Last memory block points to NULL */ + 101901c: e0bff817 ldw r2,-32(fp) + 1019020: 10000015 stw zero,0(r2) + pmem->OSMemAddr = addr; /* Store start address of memory partition */ + 1019024: e0fffa17 ldw r3,-24(fp) + 1019028: e0bffb17 ldw r2,-20(fp) + 101902c: 18800015 stw r2,0(r3) + pmem->OSMemFreeList = addr; /* Initialize pointer to pool of free blocks */ + 1019030: e0fffa17 ldw r3,-24(fp) + 1019034: e0bffb17 ldw r2,-20(fp) + 1019038: 18800115 stw r2,4(r3) + pmem->OSMemNFree = nblks; /* Store number of free blocks in MCB */ + 101903c: e0fffa17 ldw r3,-24(fp) + 1019040: e0bffc17 ldw r2,-16(fp) + 1019044: 18800415 stw r2,16(r3) + pmem->OSMemNBlks = nblks; + 1019048: e0fffa17 ldw r3,-24(fp) + 101904c: e0bffc17 ldw r2,-16(fp) + 1019050: 18800315 stw r2,12(r3) + pmem->OSMemBlkSize = blksize; /* Store block size of each memory blocks */ + 1019054: e0fffa17 ldw r3,-24(fp) + 1019058: e0bffd17 ldw r2,-12(fp) + 101905c: 18800215 stw r2,8(r3) + *perr = OS_ERR_NONE; + 1019060: e0bffe17 ldw r2,-8(fp) + 1019064: 10000005 stb zero,0(r2) + return (pmem); + 1019068: e0bffa17 ldw r2,-24(fp) + 101906c: e0bfff15 stw r2,-4(fp) + 1019070: e0bfff17 ldw r2,-4(fp) +} + 1019074: e037883a mov sp,fp + 1019078: df000017 ldw fp,0(sp) + 101907c: dec00104 addi sp,sp,4 + 1019080: f800283a ret + +01019084 : +* A pointer to NULL if an error is detected +********************************************************************************************************* +*/ + +void *OSMemGet (OS_MEM *pmem, INT8U *perr) +{ + 1019084: defff704 addi sp,sp,-36 + 1019088: df000815 stw fp,32(sp) + 101908c: df000804 addi fp,sp,32 + 1019090: e13ffd15 stw r4,-12(fp) + 1019094: e17ffe15 stw r5,-8(fp) + void *pblk; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 1019098: e03ffb15 stw zero,-20(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + 101909c: e0bffe17 ldw r2,-8(fp) + 10190a0: 1004c03a cmpne r2,r2,zero + 10190a4: 1000021e bne r2,zero,10190b0 + return ((void *)0); + 10190a8: e03fff15 stw zero,-4(fp) + 10190ac: 00003106 br 1019174 + } + if (pmem == (OS_MEM *)0) { /* Must point to a valid memory partition */ + 10190b0: e0bffd17 ldw r2,-12(fp) + 10190b4: 1004c03a cmpne r2,r2,zero + 10190b8: 1000051e bne r2,zero,10190d0 + *perr = OS_ERR_MEM_INVALID_PMEM; + 10190bc: e0fffe17 ldw r3,-8(fp) + 10190c0: 00801804 movi r2,96 + 10190c4: 18800005 stb r2,0(r3) + return ((void *)0); + 10190c8: e03fff15 stw zero,-4(fp) + 10190cc: 00002906 br 1019174 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 10190d0: 0005303a rdctl r2,status + 10190d4: e0bffa15 stw r2,-24(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 10190d8: e0fffa17 ldw r3,-24(fp) + 10190dc: 00bfff84 movi r2,-2 + 10190e0: 1884703a and r2,r3,r2 + 10190e4: 1001703a wrctl status,r2 + + return context; + 10190e8: e0bffa17 ldw r2,-24(fp) + } +#endif + OS_ENTER_CRITICAL(); + 10190ec: e0bffb15 stw r2,-20(fp) + if (pmem->OSMemNFree > 0) { /* See if there are any free memory blocks */ + 10190f0: e0bffd17 ldw r2,-12(fp) + 10190f4: 10800417 ldw r2,16(r2) + 10190f8: 1005003a cmpeq r2,r2,zero + 10190fc: 1000151e bne r2,zero,1019154 + pblk = pmem->OSMemFreeList; /* Yes, point to next free memory block */ + 1019100: e0bffd17 ldw r2,-12(fp) + 1019104: 10800117 ldw r2,4(r2) + 1019108: e0bffc15 stw r2,-16(fp) + pmem->OSMemFreeList = *(void **)pblk; /* Adjust pointer to new free list */ + 101910c: e0bffc17 ldw r2,-16(fp) + 1019110: 10c00017 ldw r3,0(r2) + 1019114: e0bffd17 ldw r2,-12(fp) + 1019118: 10c00115 stw r3,4(r2) + pmem->OSMemNFree--; /* One less memory block in this partition */ + 101911c: e0bffd17 ldw r2,-12(fp) + 1019120: 10800417 ldw r2,16(r2) + 1019124: 10ffffc4 addi r3,r2,-1 + 1019128: e0bffd17 ldw r2,-12(fp) + 101912c: 10c00415 stw r3,16(r2) + 1019130: e0bffb17 ldw r2,-20(fp) + 1019134: e0bff915 stw r2,-28(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1019138: e0bff917 ldw r2,-28(fp) + 101913c: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; /* No error */ + 1019140: e0bffe17 ldw r2,-8(fp) + 1019144: 10000005 stb zero,0(r2) + return (pblk); /* Return memory block to caller */ + 1019148: e0bffc17 ldw r2,-16(fp) + 101914c: e0bfff15 stw r2,-4(fp) + 1019150: 00000806 br 1019174 + 1019154: e0bffb17 ldw r2,-20(fp) + 1019158: e0bff815 stw r2,-32(fp) + 101915c: e0bff817 ldw r2,-32(fp) + 1019160: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); + *perr = OS_ERR_MEM_NO_FREE_BLKS; /* No, Notify caller of empty memory partition */ + 1019164: e0fffe17 ldw r3,-8(fp) + 1019168: 00801744 movi r2,93 + 101916c: 18800005 stb r2,0(r3) + return ((void *)0); /* Return NULL pointer to caller */ + 1019170: e03fff15 stw zero,-4(fp) + 1019174: e0bfff17 ldw r2,-4(fp) +} + 1019178: e037883a mov sp,fp + 101917c: df000017 ldw fp,0(sp) + 1019180: dec00104 addi sp,sp,4 + 1019184: f800283a ret + +01019188 : +********************************************************************************************************* +*/ + +#if OS_MEM_NAME_SIZE > 1 +INT8U OSMemNameGet (OS_MEM *pmem, INT8U *pname, INT8U *perr) +{ + 1019188: defff604 addi sp,sp,-40 + 101918c: dfc00915 stw ra,36(sp) + 1019190: df000815 stw fp,32(sp) + 1019194: df000804 addi fp,sp,32 + 1019198: e13ffc15 stw r4,-16(fp) + 101919c: e17ffd15 stw r5,-12(fp) + 10191a0: e1bffe15 stw r6,-8(fp) + INT8U len; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 10191a4: e03ffa15 stw zero,-24(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + 10191a8: e0bffe17 ldw r2,-8(fp) + 10191ac: 1004c03a cmpne r2,r2,zero + 10191b0: 1000021e bne r2,zero,10191bc + return (0); + 10191b4: e03fff15 stw zero,-4(fp) + 10191b8: 00003006 br 101927c + } + if (pmem == (OS_MEM *)0) { /* Is 'pmem' a NULL pointer? */ + 10191bc: e0bffc17 ldw r2,-16(fp) + 10191c0: 1004c03a cmpne r2,r2,zero + 10191c4: 1000051e bne r2,zero,10191dc + *perr = OS_ERR_MEM_INVALID_PMEM; + 10191c8: e0fffe17 ldw r3,-8(fp) + 10191cc: 00801804 movi r2,96 + 10191d0: 18800005 stb r2,0(r3) + return (0); + 10191d4: e03fff15 stw zero,-4(fp) + 10191d8: 00002806 br 101927c + } + if (pname == (INT8U *)0) { /* Is 'pname' a NULL pointer? */ + 10191dc: e0bffd17 ldw r2,-12(fp) + 10191e0: 1004c03a cmpne r2,r2,zero + 10191e4: 1000051e bne r2,zero,10191fc + *perr = OS_ERR_PNAME_NULL; + 10191e8: e0fffe17 ldw r3,-8(fp) + 10191ec: 00800304 movi r2,12 + 10191f0: 18800005 stb r2,0(r3) + return (0); + 10191f4: e03fff15 stw zero,-4(fp) + 10191f8: 00002006 br 101927c + } +#endif + if (OSIntNesting > 0) { /* See if trying to call from an ISR */ + 10191fc: 008040b4 movhi r2,258 + 1019200: 10952204 addi r2,r2,21640 + 1019204: 10800003 ldbu r2,0(r2) + 1019208: 10803fcc andi r2,r2,255 + 101920c: 1005003a cmpeq r2,r2,zero + 1019210: 1000051e bne r2,zero,1019228 + *perr = OS_ERR_NAME_GET_ISR; + 1019214: e0fffe17 ldw r3,-8(fp) + 1019218: 00800444 movi r2,17 + 101921c: 18800005 stb r2,0(r3) + return (0); + 1019220: e03fff15 stw zero,-4(fp) + 1019224: 00001506 br 101927c +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1019228: 0005303a rdctl r2,status + 101922c: e0bff915 stw r2,-28(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1019230: e0fff917 ldw r3,-28(fp) + 1019234: 00bfff84 movi r2,-2 + 1019238: 1884703a and r2,r3,r2 + 101923c: 1001703a wrctl status,r2 + + return context; + 1019240: e0bff917 ldw r2,-28(fp) + } + OS_ENTER_CRITICAL(); + 1019244: e0bffa15 stw r2,-24(fp) + len = OS_StrCopy(pname, pmem->OSMemName); /* Copy name from OS_MEM */ + 1019248: e0bffc17 ldw r2,-16(fp) + 101924c: 11400504 addi r5,r2,20 + 1019250: e13ffd17 ldw r4,-12(fp) + 1019254: 1016dfc0 call 1016dfc + 1019258: e0bffb05 stb r2,-20(fp) + 101925c: e0bffa17 ldw r2,-24(fp) + 1019260: e0bff815 stw r2,-32(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1019264: e0bff817 ldw r2,-32(fp) + 1019268: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + 101926c: e0bffe17 ldw r2,-8(fp) + 1019270: 10000005 stb zero,0(r2) + return (len); + 1019274: e0bffb03 ldbu r2,-20(fp) + 1019278: e0bfff15 stw r2,-4(fp) + 101927c: e0bfff17 ldw r2,-4(fp) +} + 1019280: e037883a mov sp,fp + 1019284: dfc00117 ldw ra,4(sp) + 1019288: df000017 ldw fp,0(sp) + 101928c: dec00204 addi sp,sp,8 + 1019290: f800283a ret + +01019294 : +********************************************************************************************************* +*/ + +#if OS_MEM_NAME_SIZE > 1 +void OSMemNameSet (OS_MEM *pmem, INT8U *pname, INT8U *perr) +{ + 1019294: defff604 addi sp,sp,-40 + 1019298: dfc00915 stw ra,36(sp) + 101929c: df000815 stw fp,32(sp) + 10192a0: df000804 addi fp,sp,32 + 10192a4: e13ffd15 stw r4,-12(fp) + 10192a8: e17ffe15 stw r5,-8(fp) + 10192ac: e1bfff15 stw r6,-4(fp) + INT8U len; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 10192b0: e03ffb15 stw zero,-20(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + 10192b4: e0bfff17 ldw r2,-4(fp) + 10192b8: 1005003a cmpeq r2,r2,zero + 10192bc: 1000381e bne r2,zero,10193a0 + return; + } + if (pmem == (OS_MEM *)0) { /* Is 'pmem' a NULL pointer? */ + 10192c0: e0bffd17 ldw r2,-12(fp) + 10192c4: 1004c03a cmpne r2,r2,zero + 10192c8: 1000041e bne r2,zero,10192dc + *perr = OS_ERR_MEM_INVALID_PMEM; + 10192cc: e0ffff17 ldw r3,-4(fp) + 10192d0: 00801804 movi r2,96 + 10192d4: 18800005 stb r2,0(r3) + return; + 10192d8: 00003106 br 10193a0 + } + if (pname == (INT8U *)0) { /* Is 'pname' a NULL pointer? */ + 10192dc: e0bffe17 ldw r2,-8(fp) + 10192e0: 1004c03a cmpne r2,r2,zero + 10192e4: 1000041e bne r2,zero,10192f8 + *perr = OS_ERR_PNAME_NULL; + 10192e8: e0ffff17 ldw r3,-4(fp) + 10192ec: 00800304 movi r2,12 + 10192f0: 18800005 stb r2,0(r3) + return; + 10192f4: 00002a06 br 10193a0 + } +#endif + if (OSIntNesting > 0) { /* See if trying to call from an ISR */ + 10192f8: 008040b4 movhi r2,258 + 10192fc: 10952204 addi r2,r2,21640 + 1019300: 10800003 ldbu r2,0(r2) + 1019304: 10803fcc andi r2,r2,255 + 1019308: 1005003a cmpeq r2,r2,zero + 101930c: 1000041e bne r2,zero,1019320 + *perr = OS_ERR_NAME_SET_ISR; + 1019310: e0ffff17 ldw r3,-4(fp) + 1019314: 00800484 movi r2,18 + 1019318: 18800005 stb r2,0(r3) + return; + 101931c: 00002006 br 10193a0 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1019320: 0005303a rdctl r2,status + 1019324: e0bffa15 stw r2,-24(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1019328: e0fffa17 ldw r3,-24(fp) + 101932c: 00bfff84 movi r2,-2 + 1019330: 1884703a and r2,r3,r2 + 1019334: 1001703a wrctl status,r2 + + return context; + 1019338: e0bffa17 ldw r2,-24(fp) + } + OS_ENTER_CRITICAL(); + 101933c: e0bffb15 stw r2,-20(fp) + len = OS_StrLen(pname); /* Can we fit the string in the storage area? */ + 1019340: e13ffe17 ldw r4,-8(fp) + 1019344: 1016e7c0 call 1016e7c + 1019348: e0bffc05 stb r2,-16(fp) + if (len > (OS_MEM_NAME_SIZE - 1)) { /* No */ + 101934c: e0bffc03 ldbu r2,-16(fp) + 1019350: 10800830 cmpltui r2,r2,32 + 1019354: 1000081e bne r2,zero,1019378 + 1019358: e0bffb17 ldw r2,-20(fp) + 101935c: e0bff915 stw r2,-28(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1019360: e0bff917 ldw r2,-28(fp) + 1019364: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + *perr = OS_ERR_MEM_NAME_TOO_LONG; + 1019368: e0ffff17 ldw r3,-4(fp) + 101936c: 008018c4 movi r2,99 + 1019370: 18800005 stb r2,0(r3) + return; + 1019374: 00000a06 br 10193a0 + } + (void)OS_StrCopy(pmem->OSMemName, pname); /* Yes, copy name to the memory partition header */ + 1019378: e0bffd17 ldw r2,-12(fp) + 101937c: 11000504 addi r4,r2,20 + 1019380: e17ffe17 ldw r5,-8(fp) + 1019384: 1016dfc0 call 1016dfc + 1019388: e0bffb17 ldw r2,-20(fp) + 101938c: e0bff815 stw r2,-32(fp) + 1019390: e0bff817 ldw r2,-32(fp) + 1019394: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + 1019398: e0bfff17 ldw r2,-4(fp) + 101939c: 10000005 stb zero,0(r2) +} + 10193a0: e037883a mov sp,fp + 10193a4: dfc00117 ldw ra,4(sp) + 10193a8: df000017 ldw fp,0(sp) + 10193ac: dec00204 addi sp,sp,8 + 10193b0: f800283a ret + +010193b4 : +* OS_ERR_MEM_INVALID_PBLK if you passed a NULL pointer for the block to release. +********************************************************************************************************* +*/ + +INT8U OSMemPut (OS_MEM *pmem, void *pblk) +{ + 10193b4: defff804 addi sp,sp,-32 + 10193b8: df000715 stw fp,28(sp) + 10193bc: df000704 addi fp,sp,28 + 10193c0: e13ffd15 stw r4,-12(fp) + 10193c4: e17ffe15 stw r5,-8(fp) +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 10193c8: e03ffc15 stw zero,-16(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (pmem == (OS_MEM *)0) { /* Must point to a valid memory partition */ + 10193cc: e0bffd17 ldw r2,-12(fp) + 10193d0: 1004c03a cmpne r2,r2,zero + 10193d4: 1000031e bne r2,zero,10193e4 + return (OS_ERR_MEM_INVALID_PMEM); + 10193d8: 00801804 movi r2,96 + 10193dc: e0bfff15 stw r2,-4(fp) + 10193e0: 00002b06 br 1019490 + } + if (pblk == (void *)0) { /* Must release a valid block */ + 10193e4: e0bffe17 ldw r2,-8(fp) + 10193e8: 1004c03a cmpne r2,r2,zero + 10193ec: 1000031e bne r2,zero,10193fc + return (OS_ERR_MEM_INVALID_PBLK); + 10193f0: 008017c4 movi r2,95 + 10193f4: e0bfff15 stw r2,-4(fp) + 10193f8: 00002506 br 1019490 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 10193fc: 0005303a rdctl r2,status + 1019400: e0bffb15 stw r2,-20(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1019404: e0fffb17 ldw r3,-20(fp) + 1019408: 00bfff84 movi r2,-2 + 101940c: 1884703a and r2,r3,r2 + 1019410: 1001703a wrctl status,r2 + + return context; + 1019414: e0bffb17 ldw r2,-20(fp) + } +#endif + OS_ENTER_CRITICAL(); + 1019418: e0bffc15 stw r2,-16(fp) + if (pmem->OSMemNFree >= pmem->OSMemNBlks) { /* Make sure all blocks not already returned */ + 101941c: e0bffd17 ldw r2,-12(fp) + 1019420: 10c00417 ldw r3,16(r2) + 1019424: e0bffd17 ldw r2,-12(fp) + 1019428: 10800317 ldw r2,12(r2) + 101942c: 18800736 bltu r3,r2,101944c + 1019430: e0bffc17 ldw r2,-16(fp) + 1019434: e0bffa15 stw r2,-24(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1019438: e0bffa17 ldw r2,-24(fp) + 101943c: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_MEM_FULL); + 1019440: 00801784 movi r2,94 + 1019444: e0bfff15 stw r2,-4(fp) + 1019448: 00001106 br 1019490 + } + *(void **)pblk = pmem->OSMemFreeList; /* Insert released block into free block list */ + 101944c: e0fffe17 ldw r3,-8(fp) + 1019450: e0bffd17 ldw r2,-12(fp) + 1019454: 10800117 ldw r2,4(r2) + 1019458: 18800015 stw r2,0(r3) + pmem->OSMemFreeList = pblk; + 101945c: e0fffd17 ldw r3,-12(fp) + 1019460: e0bffe17 ldw r2,-8(fp) + 1019464: 18800115 stw r2,4(r3) + pmem->OSMemNFree++; /* One more memory block in this partition */ + 1019468: e0bffd17 ldw r2,-12(fp) + 101946c: 10800417 ldw r2,16(r2) + 1019470: 10c00044 addi r3,r2,1 + 1019474: e0bffd17 ldw r2,-12(fp) + 1019478: 10c00415 stw r3,16(r2) + 101947c: e0bffc17 ldw r2,-16(fp) + 1019480: e0bff915 stw r2,-28(fp) + 1019484: e0bff917 ldw r2,-28(fp) + 1019488: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_NONE); /* Notify caller that memory block was released */ + 101948c: e03fff15 stw zero,-4(fp) + 1019490: e0bfff17 ldw r2,-4(fp) +} + 1019494: e037883a mov sp,fp + 1019498: df000017 ldw fp,0(sp) + 101949c: dec00104 addi sp,sp,4 + 10194a0: f800283a ret + +010194a4 : +********************************************************************************************************* +*/ + +#if OS_MEM_QUERY_EN > 0 +INT8U OSMemQuery (OS_MEM *pmem, OS_MEM_DATA *p_mem_data) +{ + 10194a4: defff904 addi sp,sp,-28 + 10194a8: df000615 stw fp,24(sp) + 10194ac: df000604 addi fp,sp,24 + 10194b0: e13ffd15 stw r4,-12(fp) + 10194b4: e17ffe15 stw r5,-8(fp) +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 10194b8: e03ffc15 stw zero,-16(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (pmem == (OS_MEM *)0) { /* Must point to a valid memory partition */ + 10194bc: e0bffd17 ldw r2,-12(fp) + 10194c0: 1004c03a cmpne r2,r2,zero + 10194c4: 1000031e bne r2,zero,10194d4 + return (OS_ERR_MEM_INVALID_PMEM); + 10194c8: 00801804 movi r2,96 + 10194cc: e0bfff15 stw r2,-4(fp) + 10194d0: 00002e06 br 101958c + } + if (p_mem_data == (OS_MEM_DATA *)0) { /* Must release a valid storage area for the data */ + 10194d4: e0bffe17 ldw r2,-8(fp) + 10194d8: 1004c03a cmpne r2,r2,zero + 10194dc: 1000031e bne r2,zero,10194ec + return (OS_ERR_MEM_INVALID_PDATA); + 10194e0: 00801844 movi r2,97 + 10194e4: e0bfff15 stw r2,-4(fp) + 10194e8: 00002806 br 101958c +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 10194ec: 0005303a rdctl r2,status + 10194f0: e0bffb15 stw r2,-20(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 10194f4: e0fffb17 ldw r3,-20(fp) + 10194f8: 00bfff84 movi r2,-2 + 10194fc: 1884703a and r2,r3,r2 + 1019500: 1001703a wrctl status,r2 + + return context; + 1019504: e0bffb17 ldw r2,-20(fp) + } +#endif + OS_ENTER_CRITICAL(); + 1019508: e0bffc15 stw r2,-16(fp) + p_mem_data->OSAddr = pmem->OSMemAddr; + 101950c: e0bffd17 ldw r2,-12(fp) + 1019510: 10c00017 ldw r3,0(r2) + 1019514: e0bffe17 ldw r2,-8(fp) + 1019518: 10c00015 stw r3,0(r2) + p_mem_data->OSFreeList = pmem->OSMemFreeList; + 101951c: e0bffd17 ldw r2,-12(fp) + 1019520: 10c00117 ldw r3,4(r2) + 1019524: e0bffe17 ldw r2,-8(fp) + 1019528: 10c00115 stw r3,4(r2) + p_mem_data->OSBlkSize = pmem->OSMemBlkSize; + 101952c: e0bffd17 ldw r2,-12(fp) + 1019530: 10c00217 ldw r3,8(r2) + 1019534: e0bffe17 ldw r2,-8(fp) + 1019538: 10c00215 stw r3,8(r2) + p_mem_data->OSNBlks = pmem->OSMemNBlks; + 101953c: e0bffd17 ldw r2,-12(fp) + 1019540: 10c00317 ldw r3,12(r2) + 1019544: e0bffe17 ldw r2,-8(fp) + 1019548: 10c00315 stw r3,12(r2) + p_mem_data->OSNFree = pmem->OSMemNFree; + 101954c: e0bffd17 ldw r2,-12(fp) + 1019550: 10c00417 ldw r3,16(r2) + 1019554: e0bffe17 ldw r2,-8(fp) + 1019558: 10c00415 stw r3,16(r2) + 101955c: e0bffc17 ldw r2,-16(fp) + 1019560: e0bffa15 stw r2,-24(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1019564: e0bffa17 ldw r2,-24(fp) + 1019568: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + p_mem_data->OSNUsed = p_mem_data->OSNBlks - p_mem_data->OSNFree; + 101956c: e0bffe17 ldw r2,-8(fp) + 1019570: 10c00317 ldw r3,12(r2) + 1019574: e0bffe17 ldw r2,-8(fp) + 1019578: 10800417 ldw r2,16(r2) + 101957c: 1887c83a sub r3,r3,r2 + 1019580: e0bffe17 ldw r2,-8(fp) + 1019584: 10c00515 stw r3,20(r2) + return (OS_ERR_NONE); + 1019588: e03fff15 stw zero,-4(fp) + 101958c: e0bfff17 ldw r2,-4(fp) +} + 1019590: e037883a mov sp,fp + 1019594: df000017 ldw fp,0(sp) + 1019598: dec00104 addi sp,sp,4 + 101959c: f800283a ret + +010195a0 : +* Note(s) : This function is INTERNAL to uC/OS-II and your application should not call it. +********************************************************************************************************* +*/ + +void OS_MemInit (void) +{ + 10195a0: defffc04 addi sp,sp,-16 + 10195a4: dfc00315 stw ra,12(sp) + 10195a8: df000215 stw fp,8(sp) + 10195ac: df000204 addi fp,sp,8 +#if OS_MAX_MEM_PART >= 2 + OS_MEM *pmem; + INT16U i; + + + OS_MemClr((INT8U *)&OSMemTbl[0], sizeof(OSMemTbl)); /* Clear the memory partition table */ + 10195b0: 010040f4 movhi r4,259 + 10195b4: 21281904 addi r4,r4,-24476 + 10195b8: 01430c04 movi r5,3120 + 10195bc: 1016bf80 call 1016bf8 + pmem = &OSMemTbl[0]; /* Point to memory control block (MCB) */ + 10195c0: 008040f4 movhi r2,259 + 10195c4: 10a81904 addi r2,r2,-24476 + 10195c8: e0bfff15 stw r2,-4(fp) + for (i = 0; i < (OS_MAX_MEM_PART - 1); i++) { /* Init. list of free memory partitions */ + 10195cc: e03ffe0d sth zero,-8(fp) + 10195d0: 00001306 br 1019620 + pmem->OSMemFreeList = (void *)&OSMemTbl[i+1]; /* Chain list of free partitions */ + 10195d4: e0bffe0b ldhu r2,-8(fp) + 10195d8: 10800d24 muli r2,r2,52 + 10195dc: 1007883a mov r3,r2 + 10195e0: 008040f4 movhi r2,259 + 10195e4: 10a82604 addi r2,r2,-24424 + 10195e8: 1887883a add r3,r3,r2 + 10195ec: e0bfff17 ldw r2,-4(fp) + 10195f0: 10c00115 stw r3,4(r2) +#if OS_MEM_NAME_SIZE > 1 + pmem->OSMemName[0] = '?'; /* Unknown name */ + 10195f4: e0ffff17 ldw r3,-4(fp) + 10195f8: 00800fc4 movi r2,63 + 10195fc: 18800505 stb r2,20(r3) + pmem->OSMemName[1] = OS_ASCII_NUL; + 1019600: e0bfff17 ldw r2,-4(fp) + 1019604: 10000545 stb zero,21(r2) +#endif + pmem++; + 1019608: e0bfff17 ldw r2,-4(fp) + 101960c: 10800d04 addi r2,r2,52 + 1019610: e0bfff15 stw r2,-4(fp) + INT16U i; + + + OS_MemClr((INT8U *)&OSMemTbl[0], sizeof(OSMemTbl)); /* Clear the memory partition table */ + pmem = &OSMemTbl[0]; /* Point to memory control block (MCB) */ + for (i = 0; i < (OS_MAX_MEM_PART - 1); i++) { /* Init. list of free memory partitions */ + 1019614: e0bffe0b ldhu r2,-8(fp) + 1019618: 10800044 addi r2,r2,1 + 101961c: e0bffe0d sth r2,-8(fp) + 1019620: e0bffe0b ldhu r2,-8(fp) + 1019624: 10800ef0 cmpltui r2,r2,59 + 1019628: 103fea1e bne r2,zero,10195d4 + pmem->OSMemName[0] = '?'; /* Unknown name */ + pmem->OSMemName[1] = OS_ASCII_NUL; +#endif + pmem++; + } + pmem->OSMemFreeList = (void *)0; /* Initialize last node */ + 101962c: e0bfff17 ldw r2,-4(fp) + 1019630: 10000115 stw zero,4(r2) +#if OS_MEM_NAME_SIZE > 1 + pmem->OSMemName[0] = '?'; /* Unknown name */ + 1019634: e0ffff17 ldw r3,-4(fp) + 1019638: 00800fc4 movi r2,63 + 101963c: 18800505 stb r2,20(r3) + pmem->OSMemName[1] = OS_ASCII_NUL; + 1019640: e0bfff17 ldw r2,-4(fp) + 1019644: 10000545 stb zero,21(r2) +#endif + + OSMemFreeList = &OSMemTbl[0]; /* Point to beginning of free list */ + 1019648: 00c040b4 movhi r3,258 + 101964c: 18d51d04 addi r3,r3,21620 + 1019650: 008040f4 movhi r2,259 + 1019654: 10a81904 addi r2,r2,-24476 + 1019658: 18800015 stw r2,0(r3) +#endif +} + 101965c: e037883a mov sp,fp + 1019660: dfc00117 ldw ra,4(sp) + 1019664: df000017 ldw fp,0(sp) + 1019668: dec00204 addi sp,sp,8 + 101966c: f800283a ret + +01019670 : +********************************************************************************************************* +*/ + +#if OS_Q_ACCEPT_EN > 0 +void *OSQAccept (OS_EVENT *pevent, INT8U *perr) +{ + 1019670: defff704 addi sp,sp,-36 + 1019674: df000815 stw fp,32(sp) + 1019678: df000804 addi fp,sp,32 + 101967c: e13ffd15 stw r4,-12(fp) + 1019680: e17ffe15 stw r5,-8(fp) + void *pmsg; + OS_Q *pq; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 1019684: e03ffa15 stw zero,-24(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + 1019688: e0bffe17 ldw r2,-8(fp) + 101968c: 1004c03a cmpne r2,r2,zero + 1019690: 1000021e bne r2,zero,101969c + return ((void *)0); + 1019694: e03fff15 stw zero,-4(fp) + 1019698: 00004506 br 10197b0 + } + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + 101969c: e0bffd17 ldw r2,-12(fp) + 10196a0: 1004c03a cmpne r2,r2,zero + 10196a4: 1000051e bne r2,zero,10196bc + *perr = OS_ERR_PEVENT_NULL; + 10196a8: e0fffe17 ldw r3,-8(fp) + 10196ac: 00800104 movi r2,4 + 10196b0: 18800005 stb r2,0(r3) + return ((void *)0); + 10196b4: e03fff15 stw zero,-4(fp) + 10196b8: 00003d06 br 10197b0 + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_Q) {/* Validate event block type */ + 10196bc: e0bffd17 ldw r2,-12(fp) + 10196c0: 10800003 ldbu r2,0(r2) + 10196c4: 10803fcc andi r2,r2,255 + 10196c8: 108000a0 cmpeqi r2,r2,2 + 10196cc: 1000051e bne r2,zero,10196e4 + *perr = OS_ERR_EVENT_TYPE; + 10196d0: e0fffe17 ldw r3,-8(fp) + 10196d4: 00800044 movi r2,1 + 10196d8: 18800005 stb r2,0(r3) + return ((void *)0); + 10196dc: e03fff15 stw zero,-4(fp) + 10196e0: 00003306 br 10197b0 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 10196e4: 0005303a rdctl r2,status + 10196e8: e0bff915 stw r2,-28(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 10196ec: e0fff917 ldw r3,-28(fp) + 10196f0: 00bfff84 movi r2,-2 + 10196f4: 1884703a and r2,r3,r2 + 10196f8: 1001703a wrctl status,r2 + + return context; + 10196fc: e0bff917 ldw r2,-28(fp) + } + OS_ENTER_CRITICAL(); + 1019700: e0bffa15 stw r2,-24(fp) + pq = (OS_Q *)pevent->OSEventPtr; /* Point at queue control block */ + 1019704: e0bffd17 ldw r2,-12(fp) + 1019708: 10800117 ldw r2,4(r2) + 101970c: e0bffb15 stw r2,-20(fp) + if (pq->OSQEntries > 0) { /* See if any messages in the queue */ + 1019710: e0bffb17 ldw r2,-20(fp) + 1019714: 1080058b ldhu r2,22(r2) + 1019718: 10bfffcc andi r2,r2,65535 + 101971c: 1005003a cmpeq r2,r2,zero + 1019720: 1000191e bne r2,zero,1019788 + pmsg = *pq->OSQOut++; /* Yes, extract oldest message from the queue */ + 1019724: e0bffb17 ldw r2,-20(fp) + 1019728: 10c00417 ldw r3,16(r2) + 101972c: 18800017 ldw r2,0(r3) + 1019730: e0bffc15 stw r2,-16(fp) + 1019734: 18c00104 addi r3,r3,4 + 1019738: e0bffb17 ldw r2,-20(fp) + 101973c: 10c00415 stw r3,16(r2) + pq->OSQEntries--; /* Update the number of entries in the queue */ + 1019740: e0bffb17 ldw r2,-20(fp) + 1019744: 1080058b ldhu r2,22(r2) + 1019748: 10bfffc4 addi r2,r2,-1 + 101974c: 1007883a mov r3,r2 + 1019750: e0bffb17 ldw r2,-20(fp) + 1019754: 10c0058d sth r3,22(r2) + if (pq->OSQOut == pq->OSQEnd) { /* Wrap OUT pointer if we are at the end of the queue */ + 1019758: e0bffb17 ldw r2,-20(fp) + 101975c: 10c00417 ldw r3,16(r2) + 1019760: e0bffb17 ldw r2,-20(fp) + 1019764: 10800217 ldw r2,8(r2) + 1019768: 1880041e bne r3,r2,101977c + pq->OSQOut = pq->OSQStart; + 101976c: e0bffb17 ldw r2,-20(fp) + 1019770: 10c00117 ldw r3,4(r2) + 1019774: e0bffb17 ldw r2,-20(fp) + 1019778: 10c00415 stw r3,16(r2) + } + *perr = OS_ERR_NONE; + 101977c: e0bffe17 ldw r2,-8(fp) + 1019780: 10000005 stb zero,0(r2) + 1019784: 00000406 br 1019798 + } else { + *perr = OS_ERR_Q_EMPTY; + 1019788: e0fffe17 ldw r3,-8(fp) + 101978c: 008007c4 movi r2,31 + 1019790: 18800005 stb r2,0(r3) + pmsg = (void *)0; /* Queue is empty */ + 1019794: e03ffc15 stw zero,-16(fp) + 1019798: e0bffa17 ldw r2,-24(fp) + 101979c: e0bff815 stw r2,-32(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 10197a0: e0bff817 ldw r2,-32(fp) + 10197a4: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); + return (pmsg); /* Return message received (or NULL) */ + 10197a8: e0bffc17 ldw r2,-16(fp) + 10197ac: e0bfff15 stw r2,-4(fp) + 10197b0: e0bfff17 ldw r2,-4(fp) +} + 10197b4: e037883a mov sp,fp + 10197b8: df000017 ldw fp,0(sp) + 10197bc: dec00104 addi sp,sp,4 + 10197c0: f800283a ret + +010197c4 : +* == (OS_EVENT *)0 if no event control blocks were available or an error was detected +********************************************************************************************************* +*/ + +OS_EVENT *OSQCreate (void **start, INT16U size) +{ + 10197c4: defff304 addi sp,sp,-52 + 10197c8: dfc00c15 stw ra,48(sp) + 10197cc: df000b15 stw fp,44(sp) + 10197d0: df000b04 addi fp,sp,44 + 10197d4: e13ffd15 stw r4,-12(fp) + 10197d8: e17ffe0d sth r5,-8(fp) + OS_EVENT *pevent; + OS_Q *pq; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 10197dc: e03ffa15 stw zero,-24(fp) +#endif + + + + if (OSIntNesting > 0) { /* See if called from ISR ... */ + 10197e0: 008040b4 movhi r2,258 + 10197e4: 10952204 addi r2,r2,21640 + 10197e8: 10800003 ldbu r2,0(r2) + 10197ec: 10803fcc andi r2,r2,255 + 10197f0: 1005003a cmpeq r2,r2,zero + 10197f4: 1000021e bne r2,zero,1019800 + return ((OS_EVENT *)0); /* ... can't CREATE from an ISR */ + 10197f8: e03fff15 stw zero,-4(fp) + 10197fc: 00007006 br 10199c0 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1019800: 0005303a rdctl r2,status + 1019804: e0bff915 stw r2,-28(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1019808: e0fff917 ldw r3,-28(fp) + 101980c: 00bfff84 movi r2,-2 + 1019810: 1884703a and r2,r3,r2 + 1019814: 1001703a wrctl status,r2 + + return context; + 1019818: e0bff917 ldw r2,-28(fp) + } + OS_ENTER_CRITICAL(); + 101981c: e0bffa15 stw r2,-24(fp) + pevent = OSEventFreeList; /* Get next free event control block */ + 1019820: 008040b4 movhi r2,258 + 1019824: 10952104 addi r2,r2,21636 + 1019828: 10800017 ldw r2,0(r2) + 101982c: e0bffc15 stw r2,-16(fp) + if (OSEventFreeList != (OS_EVENT *)0) { /* See if pool of free ECB pool was empty */ + 1019830: 008040b4 movhi r2,258 + 1019834: 10952104 addi r2,r2,21636 + 1019838: 10800017 ldw r2,0(r2) + 101983c: 1005003a cmpeq r2,r2,zero + 1019840: 1000081e bne r2,zero,1019864 + OSEventFreeList = (OS_EVENT *)OSEventFreeList->OSEventPtr; + 1019844: 008040b4 movhi r2,258 + 1019848: 10952104 addi r2,r2,21636 + 101984c: 10800017 ldw r2,0(r2) + 1019850: 10800117 ldw r2,4(r2) + 1019854: 1007883a mov r3,r2 + 1019858: 008040b4 movhi r2,258 + 101985c: 10952104 addi r2,r2,21636 + 1019860: 10c00015 stw r3,0(r2) + 1019864: e0bffa17 ldw r2,-24(fp) + 1019868: e0bff815 stw r2,-32(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 101986c: e0bff817 ldw r2,-32(fp) + 1019870: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); + if (pevent != (OS_EVENT *)0) { /* See if we have an event control block */ + 1019874: e0bffc17 ldw r2,-16(fp) + 1019878: 1005003a cmpeq r2,r2,zero + 101987c: 10004e1e bne r2,zero,10199b8 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1019880: 0005303a rdctl r2,status + 1019884: e0bff715 stw r2,-36(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1019888: e0fff717 ldw r3,-36(fp) + 101988c: 00bfff84 movi r2,-2 + 1019890: 1884703a and r2,r3,r2 + 1019894: 1001703a wrctl status,r2 + + return context; + 1019898: e0bff717 ldw r2,-36(fp) + OS_ENTER_CRITICAL(); + 101989c: e0bffa15 stw r2,-24(fp) + pq = OSQFreeList; /* Get a free queue control block */ + 10198a0: 008040b4 movhi r2,258 + 10198a4: 10951f04 addi r2,r2,21628 + 10198a8: 10800017 ldw r2,0(r2) + 10198ac: e0bffb15 stw r2,-20(fp) + if (pq != (OS_Q *)0) { /* Were we able to get a queue control block ? */ + 10198b0: e0bffb17 ldw r2,-20(fp) + 10198b4: 1005003a cmpeq r2,r2,zero + 10198b8: 1000311e bne r2,zero,1019980 + OSQFreeList = OSQFreeList->OSQPtr; /* Yes, Adjust free list pointer to next free*/ + 10198bc: 008040b4 movhi r2,258 + 10198c0: 10951f04 addi r2,r2,21628 + 10198c4: 10800017 ldw r2,0(r2) + 10198c8: 10c00017 ldw r3,0(r2) + 10198cc: 008040b4 movhi r2,258 + 10198d0: 10951f04 addi r2,r2,21628 + 10198d4: 10c00015 stw r3,0(r2) + 10198d8: e0bffa17 ldw r2,-24(fp) + 10198dc: e0bff615 stw r2,-40(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 10198e0: e0bff617 ldw r2,-40(fp) + 10198e4: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + pq->OSQStart = start; /* Initialize the queue */ + 10198e8: e0fffb17 ldw r3,-20(fp) + 10198ec: e0bffd17 ldw r2,-12(fp) + 10198f0: 18800115 stw r2,4(r3) + pq->OSQEnd = &start[size]; + 10198f4: e0bffe0b ldhu r2,-8(fp) + 10198f8: 1085883a add r2,r2,r2 + 10198fc: 1085883a add r2,r2,r2 + 1019900: 1007883a mov r3,r2 + 1019904: e0bffd17 ldw r2,-12(fp) + 1019908: 1887883a add r3,r3,r2 + 101990c: e0bffb17 ldw r2,-20(fp) + 1019910: 10c00215 stw r3,8(r2) + pq->OSQIn = start; + 1019914: e0fffb17 ldw r3,-20(fp) + 1019918: e0bffd17 ldw r2,-12(fp) + 101991c: 18800315 stw r2,12(r3) + pq->OSQOut = start; + 1019920: e0fffb17 ldw r3,-20(fp) + 1019924: e0bffd17 ldw r2,-12(fp) + 1019928: 18800415 stw r2,16(r3) + pq->OSQSize = size; + 101992c: e0fffb17 ldw r3,-20(fp) + 1019930: e0bffe0b ldhu r2,-8(fp) + 1019934: 1880050d sth r2,20(r3) + pq->OSQEntries = 0; + 1019938: e0bffb17 ldw r2,-20(fp) + 101993c: 1000058d sth zero,22(r2) + pevent->OSEventType = OS_EVENT_TYPE_Q; + 1019940: e0fffc17 ldw r3,-16(fp) + 1019944: 00800084 movi r2,2 + 1019948: 18800005 stb r2,0(r3) + pevent->OSEventCnt = 0; + 101994c: e0bffc17 ldw r2,-16(fp) + 1019950: 1000020d sth zero,8(r2) + pevent->OSEventPtr = pq; + 1019954: e0fffc17 ldw r3,-16(fp) + 1019958: e0bffb17 ldw r2,-20(fp) + 101995c: 18800115 stw r2,4(r3) +#if OS_EVENT_NAME_SIZE > 1 + pevent->OSEventName[0] = '?'; /* Unknown name */ + 1019960: e0fffc17 ldw r3,-16(fp) + 1019964: 00800fc4 movi r2,63 + 1019968: 18800385 stb r2,14(r3) + pevent->OSEventName[1] = OS_ASCII_NUL; + 101996c: e0bffc17 ldw r2,-16(fp) + 1019970: 100003c5 stb zero,15(r2) +#endif + OS_EventWaitListInit(pevent); /* Initalize the wait list */ + 1019974: e13ffc17 ldw r4,-16(fp) + 1019978: 101682c0 call 101682c + 101997c: 00000e06 br 10199b8 + } else { + pevent->OSEventPtr = (void *)OSEventFreeList; /* No, Return event control block on error */ + 1019980: 008040b4 movhi r2,258 + 1019984: 10952104 addi r2,r2,21636 + 1019988: 10c00017 ldw r3,0(r2) + 101998c: e0bffc17 ldw r2,-16(fp) + 1019990: 10c00115 stw r3,4(r2) + OSEventFreeList = pevent; + 1019994: 00c040b4 movhi r3,258 + 1019998: 18d52104 addi r3,r3,21636 + 101999c: e0bffc17 ldw r2,-16(fp) + 10199a0: 18800015 stw r2,0(r3) + 10199a4: e0bffa17 ldw r2,-24(fp) + 10199a8: e0bff515 stw r2,-44(fp) + 10199ac: e0bff517 ldw r2,-44(fp) + 10199b0: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + pevent = (OS_EVENT *)0; + 10199b4: e03ffc15 stw zero,-16(fp) + } + } + return (pevent); + 10199b8: e0bffc17 ldw r2,-16(fp) + 10199bc: e0bfff15 stw r2,-4(fp) + 10199c0: e0bfff17 ldw r2,-4(fp) +} + 10199c4: e037883a mov sp,fp + 10199c8: dfc00117 ldw ra,4(sp) + 10199cc: df000017 ldw fp,0(sp) + 10199d0: dec00204 addi sp,sp,8 + 10199d4: f800283a ret + +010199d8 : +********************************************************************************************************* +*/ + +#if OS_Q_DEL_EN > 0 +OS_EVENT *OSQDel (OS_EVENT *pevent, INT8U opt, INT8U *perr) +{ + 10199d8: defff004 addi sp,sp,-64 + 10199dc: dfc00f15 stw ra,60(sp) + 10199e0: df000e15 stw fp,56(sp) + 10199e4: df000e04 addi fp,sp,56 + 10199e8: e13ffb15 stw r4,-20(fp) + 10199ec: e1bffd15 stw r6,-12(fp) + 10199f0: e17ffc05 stb r5,-16(fp) + BOOLEAN tasks_waiting; + OS_EVENT *pevent_return; + OS_Q *pq; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 10199f4: e03ff715 stw zero,-36(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + 10199f8: e0bffd17 ldw r2,-12(fp) + 10199fc: 1004c03a cmpne r2,r2,zero + 1019a00: 1000031e bne r2,zero,1019a10 + return (pevent); + 1019a04: e0bffb17 ldw r2,-20(fp) + 1019a08: e0bfff15 stw r2,-4(fp) + 1019a0c: 0000ac06 br 1019cc0 + } + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + 1019a10: e0bffb17 ldw r2,-20(fp) + 1019a14: 1004c03a cmpne r2,r2,zero + 1019a18: 1000061e bne r2,zero,1019a34 + *perr = OS_ERR_PEVENT_NULL; + 1019a1c: e0fffd17 ldw r3,-12(fp) + 1019a20: 00800104 movi r2,4 + 1019a24: 18800005 stb r2,0(r3) + return (pevent); + 1019a28: e0fffb17 ldw r3,-20(fp) + 1019a2c: e0ffff15 stw r3,-4(fp) + 1019a30: 0000a306 br 1019cc0 + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_Q) { /* Validate event block type */ + 1019a34: e0bffb17 ldw r2,-20(fp) + 1019a38: 10800003 ldbu r2,0(r2) + 1019a3c: 10803fcc andi r2,r2,255 + 1019a40: 108000a0 cmpeqi r2,r2,2 + 1019a44: 1000061e bne r2,zero,1019a60 + *perr = OS_ERR_EVENT_TYPE; + 1019a48: e0fffd17 ldw r3,-12(fp) + 1019a4c: 00800044 movi r2,1 + 1019a50: 18800005 stb r2,0(r3) + return (pevent); + 1019a54: e0bffb17 ldw r2,-20(fp) + 1019a58: e0bfff15 stw r2,-4(fp) + 1019a5c: 00009806 br 1019cc0 + } + if (OSIntNesting > 0) { /* See if called from ISR ... */ + 1019a60: 008040b4 movhi r2,258 + 1019a64: 10952204 addi r2,r2,21640 + 1019a68: 10800003 ldbu r2,0(r2) + 1019a6c: 10803fcc andi r2,r2,255 + 1019a70: 1005003a cmpeq r2,r2,zero + 1019a74: 1000061e bne r2,zero,1019a90 + *perr = OS_ERR_DEL_ISR; /* ... can't DELETE from an ISR */ + 1019a78: e0fffd17 ldw r3,-12(fp) + 1019a7c: 008003c4 movi r2,15 + 1019a80: 18800005 stb r2,0(r3) + return (pevent); + 1019a84: e0fffb17 ldw r3,-20(fp) + 1019a88: e0ffff15 stw r3,-4(fp) + 1019a8c: 00008c06 br 1019cc0 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1019a90: 0005303a rdctl r2,status + 1019a94: e0bff615 stw r2,-40(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1019a98: e0fff617 ldw r3,-40(fp) + 1019a9c: 00bfff84 movi r2,-2 + 1019aa0: 1884703a and r2,r3,r2 + 1019aa4: 1001703a wrctl status,r2 + + return context; + 1019aa8: e0bff617 ldw r2,-40(fp) + } + OS_ENTER_CRITICAL(); + 1019aac: e0bff715 stw r2,-36(fp) + if (pevent->OSEventGrp != 0) { /* See if any tasks waiting on queue */ + 1019ab0: e0bffb17 ldw r2,-20(fp) + 1019ab4: 10800283 ldbu r2,10(r2) + 1019ab8: 10803fcc andi r2,r2,255 + 1019abc: 1005003a cmpeq r2,r2,zero + 1019ac0: 1000031e bne r2,zero,1019ad0 + tasks_waiting = OS_TRUE; /* Yes */ + 1019ac4: 00800044 movi r2,1 + 1019ac8: e0bffa05 stb r2,-24(fp) + 1019acc: 00000106 br 1019ad4 + } else { + tasks_waiting = OS_FALSE; /* No */ + 1019ad0: e03ffa05 stb zero,-24(fp) + } + switch (opt) { + 1019ad4: e0bffc03 ldbu r2,-16(fp) + 1019ad8: e0bffe15 stw r2,-8(fp) + 1019adc: e0fffe17 ldw r3,-8(fp) + 1019ae0: 1805003a cmpeq r2,r3,zero + 1019ae4: 1000041e bne r2,zero,1019af8 + 1019ae8: e0fffe17 ldw r3,-8(fp) + 1019aec: 18800060 cmpeqi r2,r3,1 + 1019af0: 1000391e bne r2,zero,1019bd8 + 1019af4: 00006706 br 1019c94 + case OS_DEL_NO_PEND: /* Delete queue only if no task waiting */ + if (tasks_waiting == OS_FALSE) { + 1019af8: e0bffa03 ldbu r2,-24(fp) + 1019afc: 1004c03a cmpne r2,r2,zero + 1019b00: 1000261e bne r2,zero,1019b9c +#if OS_EVENT_NAME_SIZE > 1 + pevent->OSEventName[0] = '?'; /* Unknown name */ + 1019b04: e0fffb17 ldw r3,-20(fp) + 1019b08: 00800fc4 movi r2,63 + 1019b0c: 18800385 stb r2,14(r3) + pevent->OSEventName[1] = OS_ASCII_NUL; + 1019b10: e0bffb17 ldw r2,-20(fp) + 1019b14: 100003c5 stb zero,15(r2) +#endif + pq = (OS_Q *)pevent->OSEventPtr; /* Return OS_Q to free list */ + 1019b18: e0bffb17 ldw r2,-20(fp) + 1019b1c: 10800117 ldw r2,4(r2) + 1019b20: e0bff815 stw r2,-32(fp) + pq->OSQPtr = OSQFreeList; + 1019b24: 008040b4 movhi r2,258 + 1019b28: 10951f04 addi r2,r2,21628 + 1019b2c: 10c00017 ldw r3,0(r2) + 1019b30: e0bff817 ldw r2,-32(fp) + 1019b34: 10c00015 stw r3,0(r2) + OSQFreeList = pq; + 1019b38: 00c040b4 movhi r3,258 + 1019b3c: 18d51f04 addi r3,r3,21628 + 1019b40: e0bff817 ldw r2,-32(fp) + 1019b44: 18800015 stw r2,0(r3) + pevent->OSEventType = OS_EVENT_TYPE_UNUSED; + 1019b48: e0bffb17 ldw r2,-20(fp) + 1019b4c: 10000005 stb zero,0(r2) + pevent->OSEventPtr = OSEventFreeList; /* Return Event Control Block to free list */ + 1019b50: 008040b4 movhi r2,258 + 1019b54: 10952104 addi r2,r2,21636 + 1019b58: 10c00017 ldw r3,0(r2) + 1019b5c: e0bffb17 ldw r2,-20(fp) + 1019b60: 10c00115 stw r3,4(r2) + pevent->OSEventCnt = 0; + 1019b64: e0bffb17 ldw r2,-20(fp) + 1019b68: 1000020d sth zero,8(r2) + OSEventFreeList = pevent; /* Get next free event control block */ + 1019b6c: 00c040b4 movhi r3,258 + 1019b70: 18d52104 addi r3,r3,21636 + 1019b74: e0bffb17 ldw r2,-20(fp) + 1019b78: 18800015 stw r2,0(r3) + 1019b7c: e0bff717 ldw r2,-36(fp) + 1019b80: e0bff515 stw r2,-44(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1019b84: e0bff517 ldw r2,-44(fp) + 1019b88: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + 1019b8c: e0bffd17 ldw r2,-12(fp) + 1019b90: 10000005 stb zero,0(r2) + pevent_return = (OS_EVENT *)0; /* Queue has been deleted */ + 1019b94: e03ff915 stw zero,-28(fp) + 1019b98: 00004706 br 1019cb8 + 1019b9c: e0bff717 ldw r2,-36(fp) + 1019ba0: e0bff415 stw r2,-48(fp) + 1019ba4: e0bff417 ldw r2,-48(fp) + 1019ba8: 1001703a wrctl status,r2 + } else { + OS_EXIT_CRITICAL(); + *perr = OS_ERR_TASK_WAITING; + 1019bac: e0fffd17 ldw r3,-12(fp) + 1019bb0: 00801244 movi r2,73 + 1019bb4: 18800005 stb r2,0(r3) + pevent_return = pevent; + 1019bb8: e0bffb17 ldw r2,-20(fp) + 1019bbc: e0bff915 stw r2,-28(fp) + } + break; + 1019bc0: 00003d06 br 1019cb8 + + case OS_DEL_ALWAYS: /* Always delete the queue */ + while (pevent->OSEventGrp != 0) { /* Ready ALL tasks waiting for queue */ + (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_Q, OS_STAT_PEND_OK); + 1019bc4: e13ffb17 ldw r4,-20(fp) + 1019bc8: 000b883a mov r5,zero + 1019bcc: 01800104 movi r6,4 + 1019bd0: 000f883a mov r7,zero + 1019bd4: 10162780 call 1016278 + pevent_return = pevent; + } + break; + + case OS_DEL_ALWAYS: /* Always delete the queue */ + while (pevent->OSEventGrp != 0) { /* Ready ALL tasks waiting for queue */ + 1019bd8: e0bffb17 ldw r2,-20(fp) + 1019bdc: 10800283 ldbu r2,10(r2) + 1019be0: 10803fcc andi r2,r2,255 + 1019be4: 1004c03a cmpne r2,r2,zero + 1019be8: 103ff61e bne r2,zero,1019bc4 + (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_Q, OS_STAT_PEND_OK); + } +#if OS_EVENT_NAME_SIZE > 1 + pevent->OSEventName[0] = '?'; /* Unknown name */ + 1019bec: e0fffb17 ldw r3,-20(fp) + 1019bf0: 00800fc4 movi r2,63 + 1019bf4: 18800385 stb r2,14(r3) + pevent->OSEventName[1] = OS_ASCII_NUL; + 1019bf8: e0bffb17 ldw r2,-20(fp) + 1019bfc: 100003c5 stb zero,15(r2) +#endif + pq = (OS_Q *)pevent->OSEventPtr; /* Return OS_Q to free list */ + 1019c00: e0bffb17 ldw r2,-20(fp) + 1019c04: 10800117 ldw r2,4(r2) + 1019c08: e0bff815 stw r2,-32(fp) + pq->OSQPtr = OSQFreeList; + 1019c0c: 008040b4 movhi r2,258 + 1019c10: 10951f04 addi r2,r2,21628 + 1019c14: 10c00017 ldw r3,0(r2) + 1019c18: e0bff817 ldw r2,-32(fp) + 1019c1c: 10c00015 stw r3,0(r2) + OSQFreeList = pq; + 1019c20: 00c040b4 movhi r3,258 + 1019c24: 18d51f04 addi r3,r3,21628 + 1019c28: e0bff817 ldw r2,-32(fp) + 1019c2c: 18800015 stw r2,0(r3) + pevent->OSEventType = OS_EVENT_TYPE_UNUSED; + 1019c30: e0bffb17 ldw r2,-20(fp) + 1019c34: 10000005 stb zero,0(r2) + pevent->OSEventPtr = OSEventFreeList; /* Return Event Control Block to free list */ + 1019c38: 008040b4 movhi r2,258 + 1019c3c: 10952104 addi r2,r2,21636 + 1019c40: 10c00017 ldw r3,0(r2) + 1019c44: e0bffb17 ldw r2,-20(fp) + 1019c48: 10c00115 stw r3,4(r2) + pevent->OSEventCnt = 0; + 1019c4c: e0bffb17 ldw r2,-20(fp) + 1019c50: 1000020d sth zero,8(r2) + OSEventFreeList = pevent; /* Get next free event control block */ + 1019c54: 00c040b4 movhi r3,258 + 1019c58: 18d52104 addi r3,r3,21636 + 1019c5c: e0bffb17 ldw r2,-20(fp) + 1019c60: 18800015 stw r2,0(r3) + 1019c64: e0bff717 ldw r2,-36(fp) + 1019c68: e0bff315 stw r2,-52(fp) + 1019c6c: e0bff317 ldw r2,-52(fp) + 1019c70: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + if (tasks_waiting == OS_TRUE) { /* Reschedule only if task(s) were waiting */ + 1019c74: e0bffa03 ldbu r2,-24(fp) + 1019c78: 10800058 cmpnei r2,r2,1 + 1019c7c: 1000011e bne r2,zero,1019c84 + OS_Sched(); /* Find highest priority task ready to run */ + 1019c80: 1016cb80 call 1016cb8 + } + *perr = OS_ERR_NONE; + 1019c84: e0bffd17 ldw r2,-12(fp) + 1019c88: 10000005 stb zero,0(r2) + pevent_return = (OS_EVENT *)0; /* Queue has been deleted */ + 1019c8c: e03ff915 stw zero,-28(fp) + break; + 1019c90: 00000906 br 1019cb8 + 1019c94: e0bff717 ldw r2,-36(fp) + 1019c98: e0bff215 stw r2,-56(fp) + 1019c9c: e0bff217 ldw r2,-56(fp) + 1019ca0: 1001703a wrctl status,r2 + + default: + OS_EXIT_CRITICAL(); + *perr = OS_ERR_INVALID_OPT; + 1019ca4: e0fffd17 ldw r3,-12(fp) + 1019ca8: 008001c4 movi r2,7 + 1019cac: 18800005 stb r2,0(r3) + pevent_return = pevent; + 1019cb0: e0bffb17 ldw r2,-20(fp) + 1019cb4: e0bff915 stw r2,-28(fp) + break; + } + return (pevent_return); + 1019cb8: e0bff917 ldw r2,-28(fp) + 1019cbc: e0bfff15 stw r2,-4(fp) + 1019cc0: e0bfff17 ldw r2,-4(fp) +} + 1019cc4: e037883a mov sp,fp + 1019cc8: dfc00117 ldw ra,4(sp) + 1019ccc: df000017 ldw fp,0(sp) + 1019cd0: dec00204 addi sp,sp,8 + 1019cd4: f800283a ret + +01019cd8 : +********************************************************************************************************* +*/ + +#if OS_Q_FLUSH_EN > 0 +INT8U OSQFlush (OS_EVENT *pevent) +{ + 1019cd8: defff904 addi sp,sp,-28 + 1019cdc: df000615 stw fp,24(sp) + 1019ce0: df000604 addi fp,sp,24 + 1019ce4: e13ffe15 stw r4,-8(fp) + OS_Q *pq; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 1019ce8: e03ffc15 stw zero,-16(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + 1019cec: e0bffe17 ldw r2,-8(fp) + 1019cf0: 1004c03a cmpne r2,r2,zero + 1019cf4: 1000031e bne r2,zero,1019d04 + return (OS_ERR_PEVENT_NULL); + 1019cf8: 00800104 movi r2,4 + 1019cfc: e0bfff15 stw r2,-4(fp) + 1019d00: 00002206 br 1019d8c + } + if (pevent->OSEventType != OS_EVENT_TYPE_Q) { /* Validate event block type */ + 1019d04: e0bffe17 ldw r2,-8(fp) + 1019d08: 10800003 ldbu r2,0(r2) + 1019d0c: 10803fcc andi r2,r2,255 + 1019d10: 108000a0 cmpeqi r2,r2,2 + 1019d14: 1000031e bne r2,zero,1019d24 + return (OS_ERR_EVENT_TYPE); + 1019d18: 00800044 movi r2,1 + 1019d1c: e0bfff15 stw r2,-4(fp) + 1019d20: 00001a06 br 1019d8c +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1019d24: 0005303a rdctl r2,status + 1019d28: e0bffb15 stw r2,-20(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1019d2c: e0fffb17 ldw r3,-20(fp) + 1019d30: 00bfff84 movi r2,-2 + 1019d34: 1884703a and r2,r3,r2 + 1019d38: 1001703a wrctl status,r2 + + return context; + 1019d3c: e0bffb17 ldw r2,-20(fp) + } +#endif + OS_ENTER_CRITICAL(); + 1019d40: e0bffc15 stw r2,-16(fp) + pq = (OS_Q *)pevent->OSEventPtr; /* Point to queue storage structure */ + 1019d44: e0bffe17 ldw r2,-8(fp) + 1019d48: 10800117 ldw r2,4(r2) + 1019d4c: e0bffd15 stw r2,-12(fp) + pq->OSQIn = pq->OSQStart; + 1019d50: e0bffd17 ldw r2,-12(fp) + 1019d54: 10c00117 ldw r3,4(r2) + 1019d58: e0bffd17 ldw r2,-12(fp) + 1019d5c: 10c00315 stw r3,12(r2) + pq->OSQOut = pq->OSQStart; + 1019d60: e0bffd17 ldw r2,-12(fp) + 1019d64: 10c00117 ldw r3,4(r2) + 1019d68: e0bffd17 ldw r2,-12(fp) + 1019d6c: 10c00415 stw r3,16(r2) + pq->OSQEntries = 0; + 1019d70: e0bffd17 ldw r2,-12(fp) + 1019d74: 1000058d sth zero,22(r2) + 1019d78: e0bffc17 ldw r2,-16(fp) + 1019d7c: e0bffa15 stw r2,-24(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1019d80: e0bffa17 ldw r2,-24(fp) + 1019d84: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_NONE); + 1019d88: e03fff15 stw zero,-4(fp) + 1019d8c: e0bfff17 ldw r2,-4(fp) +} + 1019d90: e037883a mov sp,fp + 1019d94: df000017 ldw fp,0(sp) + 1019d98: dec00104 addi sp,sp,4 + 1019d9c: f800283a ret + +01019da0 : +* Note(s) : As of V2.60, this function allows you to receive NULL pointer messages. +********************************************************************************************************* +*/ + +void *OSQPend (OS_EVENT *pevent, INT16U timeout, INT8U *perr) +{ + 1019da0: defff104 addi sp,sp,-60 + 1019da4: dfc00e15 stw ra,56(sp) + 1019da8: df000d15 stw fp,52(sp) + 1019dac: df000d04 addi fp,sp,52 + 1019db0: e13ffb15 stw r4,-20(fp) + 1019db4: e1bffd15 stw r6,-12(fp) + 1019db8: e17ffc0d sth r5,-16(fp) + void *pmsg; + OS_Q *pq; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 1019dbc: e03ff815 stw zero,-32(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + 1019dc0: e0bffd17 ldw r2,-12(fp) + 1019dc4: 1004c03a cmpne r2,r2,zero + 1019dc8: 1000021e bne r2,zero,1019dd4 + return ((void *)0); + 1019dcc: e03fff15 stw zero,-4(fp) + 1019dd0: 0000b506 br 101a0a8 + } + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + 1019dd4: e0bffb17 ldw r2,-20(fp) + 1019dd8: 1004c03a cmpne r2,r2,zero + 1019ddc: 1000051e bne r2,zero,1019df4 + *perr = OS_ERR_PEVENT_NULL; + 1019de0: e0fffd17 ldw r3,-12(fp) + 1019de4: 00800104 movi r2,4 + 1019de8: 18800005 stb r2,0(r3) + return ((void *)0); + 1019dec: e03fff15 stw zero,-4(fp) + 1019df0: 0000ad06 br 101a0a8 + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_Q) {/* Validate event block type */ + 1019df4: e0bffb17 ldw r2,-20(fp) + 1019df8: 10800003 ldbu r2,0(r2) + 1019dfc: 10803fcc andi r2,r2,255 + 1019e00: 108000a0 cmpeqi r2,r2,2 + 1019e04: 1000051e bne r2,zero,1019e1c + *perr = OS_ERR_EVENT_TYPE; + 1019e08: e0fffd17 ldw r3,-12(fp) + 1019e0c: 00800044 movi r2,1 + 1019e10: 18800005 stb r2,0(r3) + return ((void *)0); + 1019e14: e03fff15 stw zero,-4(fp) + 1019e18: 0000a306 br 101a0a8 + } + if (OSIntNesting > 0) { /* See if called from ISR ... */ + 1019e1c: 008040b4 movhi r2,258 + 1019e20: 10952204 addi r2,r2,21640 + 1019e24: 10800003 ldbu r2,0(r2) + 1019e28: 10803fcc andi r2,r2,255 + 1019e2c: 1005003a cmpeq r2,r2,zero + 1019e30: 1000051e bne r2,zero,1019e48 + *perr = OS_ERR_PEND_ISR; /* ... can't PEND from an ISR */ + 1019e34: e0fffd17 ldw r3,-12(fp) + 1019e38: 00800084 movi r2,2 + 1019e3c: 18800005 stb r2,0(r3) + return ((void *)0); + 1019e40: e03fff15 stw zero,-4(fp) + 1019e44: 00009806 br 101a0a8 + } + if (OSLockNesting > 0) { /* See if called with scheduler locked ... */ + 1019e48: 008040b4 movhi r2,258 + 1019e4c: 10951404 addi r2,r2,21584 + 1019e50: 10800003 ldbu r2,0(r2) + 1019e54: 10803fcc andi r2,r2,255 + 1019e58: 1005003a cmpeq r2,r2,zero + 1019e5c: 1000051e bne r2,zero,1019e74 + *perr = OS_ERR_PEND_LOCKED; /* ... can't PEND when locked */ + 1019e60: e0fffd17 ldw r3,-12(fp) + 1019e64: 00800344 movi r2,13 + 1019e68: 18800005 stb r2,0(r3) + return ((void *)0); + 1019e6c: e03fff15 stw zero,-4(fp) + 1019e70: 00008d06 br 101a0a8 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1019e74: 0005303a rdctl r2,status + 1019e78: e0bff715 stw r2,-36(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1019e7c: e0fff717 ldw r3,-36(fp) + 1019e80: 00bfff84 movi r2,-2 + 1019e84: 1884703a and r2,r3,r2 + 1019e88: 1001703a wrctl status,r2 + + return context; + 1019e8c: e0bff717 ldw r2,-36(fp) + } + OS_ENTER_CRITICAL(); + 1019e90: e0bff815 stw r2,-32(fp) + pq = (OS_Q *)pevent->OSEventPtr; /* Point at queue control block */ + 1019e94: e0bffb17 ldw r2,-20(fp) + 1019e98: 10800117 ldw r2,4(r2) + 1019e9c: e0bff915 stw r2,-28(fp) + if (pq->OSQEntries > 0) { /* See if any messages in the queue */ + 1019ea0: e0bff917 ldw r2,-28(fp) + 1019ea4: 1080058b ldhu r2,22(r2) + 1019ea8: 10bfffcc andi r2,r2,65535 + 1019eac: 1005003a cmpeq r2,r2,zero + 1019eb0: 10001f1e bne r2,zero,1019f30 + pmsg = *pq->OSQOut++; /* Yes, extract oldest message from the queue */ + 1019eb4: e0bff917 ldw r2,-28(fp) + 1019eb8: 10c00417 ldw r3,16(r2) + 1019ebc: 18800017 ldw r2,0(r3) + 1019ec0: e0bffa15 stw r2,-24(fp) + 1019ec4: 18c00104 addi r3,r3,4 + 1019ec8: e0bff917 ldw r2,-28(fp) + 1019ecc: 10c00415 stw r3,16(r2) + pq->OSQEntries--; /* Update the number of entries in the queue */ + 1019ed0: e0bff917 ldw r2,-28(fp) + 1019ed4: 1080058b ldhu r2,22(r2) + 1019ed8: 10bfffc4 addi r2,r2,-1 + 1019edc: 1007883a mov r3,r2 + 1019ee0: e0bff917 ldw r2,-28(fp) + 1019ee4: 10c0058d sth r3,22(r2) + if (pq->OSQOut == pq->OSQEnd) { /* Wrap OUT pointer if we are at the end of the queue */ + 1019ee8: e0bff917 ldw r2,-28(fp) + 1019eec: 10c00417 ldw r3,16(r2) + 1019ef0: e0bff917 ldw r2,-28(fp) + 1019ef4: 10800217 ldw r2,8(r2) + 1019ef8: 1880041e bne r3,r2,1019f0c + pq->OSQOut = pq->OSQStart; + 1019efc: e0bff917 ldw r2,-28(fp) + 1019f00: 10c00117 ldw r3,4(r2) + 1019f04: e0bff917 ldw r2,-28(fp) + 1019f08: 10c00415 stw r3,16(r2) + 1019f0c: e0bff817 ldw r2,-32(fp) + 1019f10: e0bff615 stw r2,-40(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1019f14: e0bff617 ldw r2,-40(fp) + 1019f18: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + 1019f1c: e0bffd17 ldw r2,-12(fp) + 1019f20: 10000005 stb zero,0(r2) + return (pmsg); /* Return message received */ + 1019f24: e0bffa17 ldw r2,-24(fp) + 1019f28: e0bfff15 stw r2,-4(fp) + 1019f2c: 00005e06 br 101a0a8 + } + OSTCBCur->OSTCBStat |= OS_STAT_Q; /* Task will have to pend for a message to be posted */ + 1019f30: 008040b4 movhi r2,258 + 1019f34: 10952304 addi r2,r2,21644 + 1019f38: 10c00017 ldw r3,0(r2) + 1019f3c: 008040b4 movhi r2,258 + 1019f40: 10952304 addi r2,r2,21644 + 1019f44: 10800017 ldw r2,0(r2) + 1019f48: 10800c03 ldbu r2,48(r2) + 1019f4c: 10800114 ori r2,r2,4 + 1019f50: 18800c05 stb r2,48(r3) + OSTCBCur->OSTCBStatPend = OS_STAT_PEND_OK; + 1019f54: 008040b4 movhi r2,258 + 1019f58: 10952304 addi r2,r2,21644 + 1019f5c: 10800017 ldw r2,0(r2) + 1019f60: 10000c45 stb zero,49(r2) + OSTCBCur->OSTCBDly = timeout; /* Load timeout into TCB */ + 1019f64: 008040b4 movhi r2,258 + 1019f68: 10952304 addi r2,r2,21644 + 1019f6c: 10c00017 ldw r3,0(r2) + 1019f70: e0bffc0b ldhu r2,-16(fp) + 1019f74: 18800b8d sth r2,46(r3) + OS_EventTaskWait(pevent); /* Suspend task until event or timeout occurs */ + 1019f78: e13ffb17 ldw r4,-20(fp) + 1019f7c: 101640c0 call 101640c + 1019f80: e0bff817 ldw r2,-32(fp) + 1019f84: e0bff515 stw r2,-44(fp) + 1019f88: e0bff517 ldw r2,-44(fp) + 1019f8c: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + OS_Sched(); /* Find next highest priority task ready to run */ + 1019f90: 1016cb80 call 1016cb8 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1019f94: 0005303a rdctl r2,status + 1019f98: e0bff415 stw r2,-48(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1019f9c: e0fff417 ldw r3,-48(fp) + 1019fa0: 00bfff84 movi r2,-2 + 1019fa4: 1884703a and r2,r3,r2 + 1019fa8: 1001703a wrctl status,r2 + + return context; + 1019fac: e0bff417 ldw r2,-48(fp) + OS_ENTER_CRITICAL(); + 1019fb0: e0bff815 stw r2,-32(fp) + switch (OSTCBCur->OSTCBStatPend) { /* See if we timed-out or aborted */ + 1019fb4: 008040b4 movhi r2,258 + 1019fb8: 10952304 addi r2,r2,21644 + 1019fbc: 10800017 ldw r2,0(r2) + 1019fc0: 10800c43 ldbu r2,49(r2) + 1019fc4: 10803fcc andi r2,r2,255 + 1019fc8: e0bffe15 stw r2,-8(fp) + 1019fcc: e0fffe17 ldw r3,-8(fp) + 1019fd0: 1805003a cmpeq r2,r3,zero + 1019fd4: 1000041e bne r2,zero,1019fe8 + 1019fd8: e0fffe17 ldw r3,-8(fp) + 1019fdc: 188000a0 cmpeqi r2,r3,2 + 1019fe0: 1000091e bne r2,zero,101a008 + 1019fe4: 00000d06 br 101a01c + case OS_STAT_PEND_OK: /* Extract message from TCB (Put there by QPost) */ + pmsg = OSTCBCur->OSTCBMsg; + 1019fe8: 008040b4 movhi r2,258 + 1019fec: 10952304 addi r2,r2,21644 + 1019ff0: 10800017 ldw r2,0(r2) + 1019ff4: 10800917 ldw r2,36(r2) + 1019ff8: e0bffa15 stw r2,-24(fp) + *perr = OS_ERR_NONE; + 1019ffc: e0bffd17 ldw r2,-12(fp) + 101a000: 10000005 stb zero,0(r2) + break; + 101a004: 00000e06 br 101a040 + + case OS_STAT_PEND_ABORT: + pmsg = (void *)0; + 101a008: e03ffa15 stw zero,-24(fp) + *perr = OS_ERR_PEND_ABORT; /* Indicate that we aborted */ + 101a00c: e0fffd17 ldw r3,-12(fp) + 101a010: 00800384 movi r2,14 + 101a014: 18800005 stb r2,0(r3) + break; + 101a018: 00000906 br 101a040 + + case OS_STAT_PEND_TO: + default: + OS_EventTaskRemove(OSTCBCur, pevent); + 101a01c: 008040b4 movhi r2,258 + 101a020: 10952304 addi r2,r2,21644 + 101a024: 11000017 ldw r4,0(r2) + 101a028: e17ffb17 ldw r5,-20(fp) + 101a02c: 10166700 call 1016670 + pmsg = (void *)0; + 101a030: e03ffa15 stw zero,-24(fp) + *perr = OS_ERR_TIMEOUT; /* Indicate that we didn't get event within TO */ + 101a034: e0fffd17 ldw r3,-12(fp) + 101a038: 00800284 movi r2,10 + 101a03c: 18800005 stb r2,0(r3) + break; + } + OSTCBCur->OSTCBStat = OS_STAT_RDY; /* Set task status to ready */ + 101a040: 008040b4 movhi r2,258 + 101a044: 10952304 addi r2,r2,21644 + 101a048: 10800017 ldw r2,0(r2) + 101a04c: 10000c05 stb zero,48(r2) + OSTCBCur->OSTCBStatPend = OS_STAT_PEND_OK; /* Clear pend status */ + 101a050: 008040b4 movhi r2,258 + 101a054: 10952304 addi r2,r2,21644 + 101a058: 10800017 ldw r2,0(r2) + 101a05c: 10000c45 stb zero,49(r2) + OSTCBCur->OSTCBEventPtr = (OS_EVENT *)0; /* Clear event pointers */ + 101a060: 008040b4 movhi r2,258 + 101a064: 10952304 addi r2,r2,21644 + 101a068: 10800017 ldw r2,0(r2) + 101a06c: 10000715 stw zero,28(r2) +#if (OS_EVENT_MULTI_EN > 0) + OSTCBCur->OSTCBEventMultiPtr = (OS_EVENT **)0; + 101a070: 008040b4 movhi r2,258 + 101a074: 10952304 addi r2,r2,21644 + 101a078: 10800017 ldw r2,0(r2) + 101a07c: 10000815 stw zero,32(r2) +#endif + OSTCBCur->OSTCBMsg = (void *)0; /* Clear received message */ + 101a080: 008040b4 movhi r2,258 + 101a084: 10952304 addi r2,r2,21644 + 101a088: 10800017 ldw r2,0(r2) + 101a08c: 10000915 stw zero,36(r2) + 101a090: e0bff817 ldw r2,-32(fp) + 101a094: e0bff315 stw r2,-52(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 101a098: e0bff317 ldw r2,-52(fp) + 101a09c: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (pmsg); /* Return received message */ + 101a0a0: e0bffa17 ldw r2,-24(fp) + 101a0a4: e0bfff15 stw r2,-4(fp) + 101a0a8: e0bfff17 ldw r2,-4(fp) +} + 101a0ac: e037883a mov sp,fp + 101a0b0: dfc00117 ldw ra,4(sp) + 101a0b4: df000017 ldw fp,0(sp) + 101a0b8: dec00204 addi sp,sp,8 + 101a0bc: f800283a ret + +0101a0c0 : +********************************************************************************************************* +*/ + +#if OS_Q_PEND_ABORT_EN > 0 +INT8U OSQPendAbort (OS_EVENT *pevent, INT8U opt, INT8U *perr) +{ + 101a0c0: defff504 addi sp,sp,-44 + 101a0c4: dfc00a15 stw ra,40(sp) + 101a0c8: df000915 stw fp,36(sp) + 101a0cc: df000904 addi fp,sp,36 + 101a0d0: e13ffc15 stw r4,-16(fp) + 101a0d4: e1bffe15 stw r6,-8(fp) + 101a0d8: e17ffd05 stb r5,-12(fp) + INT8U nbr_tasks; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 101a0dc: e03ffa15 stw zero,-24(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + 101a0e0: e0bffe17 ldw r2,-8(fp) + 101a0e4: 1004c03a cmpne r2,r2,zero + 101a0e8: 1000021e bne r2,zero,101a0f4 + return (0); + 101a0ec: e03fff15 stw zero,-4(fp) + 101a0f0: 00004c06 br 101a224 + } + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + 101a0f4: e0bffc17 ldw r2,-16(fp) + 101a0f8: 1004c03a cmpne r2,r2,zero + 101a0fc: 1000051e bne r2,zero,101a114 + *perr = OS_ERR_PEVENT_NULL; + 101a100: e0fffe17 ldw r3,-8(fp) + 101a104: 00800104 movi r2,4 + 101a108: 18800005 stb r2,0(r3) + return (0); + 101a10c: e03fff15 stw zero,-4(fp) + 101a110: 00004406 br 101a224 + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_Q) { /* Validate event block type */ + 101a114: e0bffc17 ldw r2,-16(fp) + 101a118: 10800003 ldbu r2,0(r2) + 101a11c: 10803fcc andi r2,r2,255 + 101a120: 108000a0 cmpeqi r2,r2,2 + 101a124: 1000051e bne r2,zero,101a13c + *perr = OS_ERR_EVENT_TYPE; + 101a128: e0fffe17 ldw r3,-8(fp) + 101a12c: 00800044 movi r2,1 + 101a130: 18800005 stb r2,0(r3) + return (0); + 101a134: e03fff15 stw zero,-4(fp) + 101a138: 00003a06 br 101a224 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 101a13c: 0005303a rdctl r2,status + 101a140: e0bff915 stw r2,-28(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 101a144: e0fff917 ldw r3,-28(fp) + 101a148: 00bfff84 movi r2,-2 + 101a14c: 1884703a and r2,r3,r2 + 101a150: 1001703a wrctl status,r2 + + return context; + 101a154: e0bff917 ldw r2,-28(fp) + } + OS_ENTER_CRITICAL(); + 101a158: e0bffa15 stw r2,-24(fp) + if (pevent->OSEventGrp != 0) { /* See if any task waiting on queue? */ + 101a15c: e0bffc17 ldw r2,-16(fp) + 101a160: 10800283 ldbu r2,10(r2) + 101a164: 10803fcc andi r2,r2,255 + 101a168: 1005003a cmpeq r2,r2,zero + 101a16c: 1000261e bne r2,zero,101a208 + nbr_tasks = 0; + 101a170: e03ffb05 stb zero,-20(fp) + switch (opt) { + 101a174: e0bffd03 ldbu r2,-12(fp) + 101a178: 10800060 cmpeqi r2,r2,1 + 101a17c: 1000091e bne r2,zero,101a1a4 + 101a180: 00000e06 br 101a1bc + case OS_PEND_OPT_BROADCAST: /* Do we need to abort ALL waiting tasks? */ + while (pevent->OSEventGrp != 0) { /* Yes, ready ALL tasks waiting on queue */ + (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_Q, OS_STAT_PEND_ABORT); + 101a184: e13ffc17 ldw r4,-16(fp) + 101a188: 000b883a mov r5,zero + 101a18c: 01800104 movi r6,4 + 101a190: 01c00084 movi r7,2 + 101a194: 10162780 call 1016278 + nbr_tasks++; + 101a198: e0bffb03 ldbu r2,-20(fp) + 101a19c: 10800044 addi r2,r2,1 + 101a1a0: e0bffb05 stb r2,-20(fp) + OS_ENTER_CRITICAL(); + if (pevent->OSEventGrp != 0) { /* See if any task waiting on queue? */ + nbr_tasks = 0; + switch (opt) { + case OS_PEND_OPT_BROADCAST: /* Do we need to abort ALL waiting tasks? */ + while (pevent->OSEventGrp != 0) { /* Yes, ready ALL tasks waiting on queue */ + 101a1a4: e0bffc17 ldw r2,-16(fp) + 101a1a8: 10800283 ldbu r2,10(r2) + 101a1ac: 10803fcc andi r2,r2,255 + 101a1b0: 1004c03a cmpne r2,r2,zero + 101a1b4: 103ff31e bne r2,zero,101a184 + (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_Q, OS_STAT_PEND_ABORT); + nbr_tasks++; + } + break; + 101a1b8: 00000806 br 101a1dc + + case OS_PEND_OPT_NONE: + default: /* No, ready HPT waiting on queue */ + (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_Q, OS_STAT_PEND_ABORT); + 101a1bc: e13ffc17 ldw r4,-16(fp) + 101a1c0: 000b883a mov r5,zero + 101a1c4: 01800104 movi r6,4 + 101a1c8: 01c00084 movi r7,2 + 101a1cc: 10162780 call 1016278 + nbr_tasks++; + 101a1d0: e0bffb03 ldbu r2,-20(fp) + 101a1d4: 10800044 addi r2,r2,1 + 101a1d8: e0bffb05 stb r2,-20(fp) + 101a1dc: e0bffa17 ldw r2,-24(fp) + 101a1e0: e0bff815 stw r2,-32(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 101a1e4: e0bff817 ldw r2,-32(fp) + 101a1e8: 1001703a wrctl status,r2 + break; + } + OS_EXIT_CRITICAL(); + OS_Sched(); /* Find HPT ready to run */ + 101a1ec: 1016cb80 call 1016cb8 + *perr = OS_ERR_PEND_ABORT; + 101a1f0: e0fffe17 ldw r3,-8(fp) + 101a1f4: 00800384 movi r2,14 + 101a1f8: 18800005 stb r2,0(r3) + return (nbr_tasks); + 101a1fc: e0bffb03 ldbu r2,-20(fp) + 101a200: e0bfff15 stw r2,-4(fp) + 101a204: 00000706 br 101a224 + 101a208: e0bffa17 ldw r2,-24(fp) + 101a20c: e0bff715 stw r2,-36(fp) + 101a210: e0bff717 ldw r2,-36(fp) + 101a214: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + 101a218: e0bffe17 ldw r2,-8(fp) + 101a21c: 10000005 stb zero,0(r2) + return (0); /* No tasks waiting on queue */ + 101a220: e03fff15 stw zero,-4(fp) + 101a224: e0bfff17 ldw r2,-4(fp) +} + 101a228: e037883a mov sp,fp + 101a22c: dfc00117 ldw ra,4(sp) + 101a230: df000017 ldw fp,0(sp) + 101a234: dec00204 addi sp,sp,8 + 101a238: f800283a ret + +0101a23c : +********************************************************************************************************* +*/ + +#if OS_Q_POST_EN > 0 +INT8U OSQPost (OS_EVENT *pevent, void *pmsg) +{ + 101a23c: defff504 addi sp,sp,-44 + 101a240: dfc00a15 stw ra,40(sp) + 101a244: df000915 stw fp,36(sp) + 101a248: df000904 addi fp,sp,36 + 101a24c: e13ffd15 stw r4,-12(fp) + 101a250: e17ffe15 stw r5,-8(fp) + OS_Q *pq; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 101a254: e03ffb15 stw zero,-20(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + 101a258: e0bffd17 ldw r2,-12(fp) + 101a25c: 1004c03a cmpne r2,r2,zero + 101a260: 1000031e bne r2,zero,101a270 + return (OS_ERR_PEVENT_NULL); + 101a264: 00800104 movi r2,4 + 101a268: e0bfff15 stw r2,-4(fp) + 101a26c: 00004d06 br 101a3a4 + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_Q) { /* Validate event block type */ + 101a270: e0bffd17 ldw r2,-12(fp) + 101a274: 10800003 ldbu r2,0(r2) + 101a278: 10803fcc andi r2,r2,255 + 101a27c: 108000a0 cmpeqi r2,r2,2 + 101a280: 1000031e bne r2,zero,101a290 + return (OS_ERR_EVENT_TYPE); + 101a284: 00800044 movi r2,1 + 101a288: e0bfff15 stw r2,-4(fp) + 101a28c: 00004506 br 101a3a4 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 101a290: 0005303a rdctl r2,status + 101a294: e0bffa15 stw r2,-24(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 101a298: e0fffa17 ldw r3,-24(fp) + 101a29c: 00bfff84 movi r2,-2 + 101a2a0: 1884703a and r2,r3,r2 + 101a2a4: 1001703a wrctl status,r2 + + return context; + 101a2a8: e0bffa17 ldw r2,-24(fp) + } + OS_ENTER_CRITICAL(); + 101a2ac: e0bffb15 stw r2,-20(fp) + if (pevent->OSEventGrp != 0) { /* See if any task pending on queue */ + 101a2b0: e0bffd17 ldw r2,-12(fp) + 101a2b4: 10800283 ldbu r2,10(r2) + 101a2b8: 10803fcc andi r2,r2,255 + 101a2bc: 1005003a cmpeq r2,r2,zero + 101a2c0: 10000c1e bne r2,zero,101a2f4 + /* Ready highest priority task waiting on event */ + (void)OS_EventTaskRdy(pevent, pmsg, OS_STAT_Q, OS_STAT_PEND_OK); + 101a2c4: e13ffd17 ldw r4,-12(fp) + 101a2c8: e17ffe17 ldw r5,-8(fp) + 101a2cc: 01800104 movi r6,4 + 101a2d0: 000f883a mov r7,zero + 101a2d4: 10162780 call 1016278 + 101a2d8: e0bffb17 ldw r2,-20(fp) + 101a2dc: e0bff915 stw r2,-28(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 101a2e0: e0bff917 ldw r2,-28(fp) + 101a2e4: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + OS_Sched(); /* Find highest priority task ready to run */ + 101a2e8: 1016cb80 call 1016cb8 + return (OS_ERR_NONE); + 101a2ec: e03fff15 stw zero,-4(fp) + 101a2f0: 00002c06 br 101a3a4 + } + pq = (OS_Q *)pevent->OSEventPtr; /* Point to queue control block */ + 101a2f4: e0bffd17 ldw r2,-12(fp) + 101a2f8: 10800117 ldw r2,4(r2) + 101a2fc: e0bffc15 stw r2,-16(fp) + if (pq->OSQEntries >= pq->OSQSize) { /* Make sure queue is not full */ + 101a300: e0bffc17 ldw r2,-16(fp) + 101a304: 10c0058b ldhu r3,22(r2) + 101a308: e0bffc17 ldw r2,-16(fp) + 101a30c: 1080050b ldhu r2,20(r2) + 101a310: 18ffffcc andi r3,r3,65535 + 101a314: 10bfffcc andi r2,r2,65535 + 101a318: 18800736 bltu r3,r2,101a338 + 101a31c: e0bffb17 ldw r2,-20(fp) + 101a320: e0bff815 stw r2,-32(fp) + 101a324: e0bff817 ldw r2,-32(fp) + 101a328: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_Q_FULL); + 101a32c: 00800784 movi r2,30 + 101a330: e0bfff15 stw r2,-4(fp) + 101a334: 00001b06 br 101a3a4 + } + *pq->OSQIn++ = pmsg; /* Insert message into queue */ + 101a338: e0bffc17 ldw r2,-16(fp) + 101a33c: 10c00317 ldw r3,12(r2) + 101a340: e0bffe17 ldw r2,-8(fp) + 101a344: 18800015 stw r2,0(r3) + 101a348: 18c00104 addi r3,r3,4 + 101a34c: e0bffc17 ldw r2,-16(fp) + 101a350: 10c00315 stw r3,12(r2) + pq->OSQEntries++; /* Update the nbr of entries in the queue */ + 101a354: e0bffc17 ldw r2,-16(fp) + 101a358: 1080058b ldhu r2,22(r2) + 101a35c: 10800044 addi r2,r2,1 + 101a360: 1007883a mov r3,r2 + 101a364: e0bffc17 ldw r2,-16(fp) + 101a368: 10c0058d sth r3,22(r2) + if (pq->OSQIn == pq->OSQEnd) { /* Wrap IN ptr if we are at end of queue */ + 101a36c: e0bffc17 ldw r2,-16(fp) + 101a370: 10c00317 ldw r3,12(r2) + 101a374: e0bffc17 ldw r2,-16(fp) + 101a378: 10800217 ldw r2,8(r2) + 101a37c: 1880041e bne r3,r2,101a390 + pq->OSQIn = pq->OSQStart; + 101a380: e0bffc17 ldw r2,-16(fp) + 101a384: 10c00117 ldw r3,4(r2) + 101a388: e0bffc17 ldw r2,-16(fp) + 101a38c: 10c00315 stw r3,12(r2) + 101a390: e0bffb17 ldw r2,-20(fp) + 101a394: e0bff715 stw r2,-36(fp) + 101a398: e0bff717 ldw r2,-36(fp) + 101a39c: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); + return (OS_ERR_NONE); + 101a3a0: e03fff15 stw zero,-4(fp) + 101a3a4: e0bfff17 ldw r2,-4(fp) +} + 101a3a8: e037883a mov sp,fp + 101a3ac: dfc00117 ldw ra,4(sp) + 101a3b0: df000017 ldw fp,0(sp) + 101a3b4: dec00204 addi sp,sp,8 + 101a3b8: f800283a ret + +0101a3bc : +********************************************************************************************************* +*/ + +#if OS_Q_POST_FRONT_EN > 0 +INT8U OSQPostFront (OS_EVENT *pevent, void *pmsg) +{ + 101a3bc: defff504 addi sp,sp,-44 + 101a3c0: dfc00a15 stw ra,40(sp) + 101a3c4: df000915 stw fp,36(sp) + 101a3c8: df000904 addi fp,sp,36 + 101a3cc: e13ffd15 stw r4,-12(fp) + 101a3d0: e17ffe15 stw r5,-8(fp) + OS_Q *pq; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 101a3d4: e03ffb15 stw zero,-20(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + 101a3d8: e0bffd17 ldw r2,-12(fp) + 101a3dc: 1004c03a cmpne r2,r2,zero + 101a3e0: 1000031e bne r2,zero,101a3f0 + return (OS_ERR_PEVENT_NULL); + 101a3e4: 00800104 movi r2,4 + 101a3e8: e0bfff15 stw r2,-4(fp) + 101a3ec: 00004f06 br 101a52c + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_Q) { /* Validate event block type */ + 101a3f0: e0bffd17 ldw r2,-12(fp) + 101a3f4: 10800003 ldbu r2,0(r2) + 101a3f8: 10803fcc andi r2,r2,255 + 101a3fc: 108000a0 cmpeqi r2,r2,2 + 101a400: 1000031e bne r2,zero,101a410 + return (OS_ERR_EVENT_TYPE); + 101a404: 00800044 movi r2,1 + 101a408: e0bfff15 stw r2,-4(fp) + 101a40c: 00004706 br 101a52c +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 101a410: 0005303a rdctl r2,status + 101a414: e0bffa15 stw r2,-24(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 101a418: e0fffa17 ldw r3,-24(fp) + 101a41c: 00bfff84 movi r2,-2 + 101a420: 1884703a and r2,r3,r2 + 101a424: 1001703a wrctl status,r2 + + return context; + 101a428: e0bffa17 ldw r2,-24(fp) + } + OS_ENTER_CRITICAL(); + 101a42c: e0bffb15 stw r2,-20(fp) + if (pevent->OSEventGrp != 0) { /* See if any task pending on queue */ + 101a430: e0bffd17 ldw r2,-12(fp) + 101a434: 10800283 ldbu r2,10(r2) + 101a438: 10803fcc andi r2,r2,255 + 101a43c: 1005003a cmpeq r2,r2,zero + 101a440: 10000c1e bne r2,zero,101a474 + /* Ready highest priority task waiting on event */ + (void)OS_EventTaskRdy(pevent, pmsg, OS_STAT_Q, OS_STAT_PEND_OK); + 101a444: e13ffd17 ldw r4,-12(fp) + 101a448: e17ffe17 ldw r5,-8(fp) + 101a44c: 01800104 movi r6,4 + 101a450: 000f883a mov r7,zero + 101a454: 10162780 call 1016278 + 101a458: e0bffb17 ldw r2,-20(fp) + 101a45c: e0bff915 stw r2,-28(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 101a460: e0bff917 ldw r2,-28(fp) + 101a464: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + OS_Sched(); /* Find highest priority task ready to run */ + 101a468: 1016cb80 call 1016cb8 + return (OS_ERR_NONE); + 101a46c: e03fff15 stw zero,-4(fp) + 101a470: 00002e06 br 101a52c + } + pq = (OS_Q *)pevent->OSEventPtr; /* Point to queue control block */ + 101a474: e0bffd17 ldw r2,-12(fp) + 101a478: 10800117 ldw r2,4(r2) + 101a47c: e0bffc15 stw r2,-16(fp) + if (pq->OSQEntries >= pq->OSQSize) { /* Make sure queue is not full */ + 101a480: e0bffc17 ldw r2,-16(fp) + 101a484: 10c0058b ldhu r3,22(r2) + 101a488: e0bffc17 ldw r2,-16(fp) + 101a48c: 1080050b ldhu r2,20(r2) + 101a490: 18ffffcc andi r3,r3,65535 + 101a494: 10bfffcc andi r2,r2,65535 + 101a498: 18800736 bltu r3,r2,101a4b8 + 101a49c: e0bffb17 ldw r2,-20(fp) + 101a4a0: e0bff815 stw r2,-32(fp) + 101a4a4: e0bff817 ldw r2,-32(fp) + 101a4a8: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_Q_FULL); + 101a4ac: 00800784 movi r2,30 + 101a4b0: e0bfff15 stw r2,-4(fp) + 101a4b4: 00001d06 br 101a52c + } + if (pq->OSQOut == pq->OSQStart) { /* Wrap OUT ptr if we are at the 1st queue entry */ + 101a4b8: e0bffc17 ldw r2,-16(fp) + 101a4bc: 10c00417 ldw r3,16(r2) + 101a4c0: e0bffc17 ldw r2,-16(fp) + 101a4c4: 10800117 ldw r2,4(r2) + 101a4c8: 1880041e bne r3,r2,101a4dc + pq->OSQOut = pq->OSQEnd; + 101a4cc: e0bffc17 ldw r2,-16(fp) + 101a4d0: 10c00217 ldw r3,8(r2) + 101a4d4: e0bffc17 ldw r2,-16(fp) + 101a4d8: 10c00415 stw r3,16(r2) + } + pq->OSQOut--; + 101a4dc: e0bffc17 ldw r2,-16(fp) + 101a4e0: 10800417 ldw r2,16(r2) + 101a4e4: 10ffff04 addi r3,r2,-4 + 101a4e8: e0bffc17 ldw r2,-16(fp) + 101a4ec: 10c00415 stw r3,16(r2) + *pq->OSQOut = pmsg; /* Insert message into queue */ + 101a4f0: e0bffc17 ldw r2,-16(fp) + 101a4f4: 10c00417 ldw r3,16(r2) + 101a4f8: e0bffe17 ldw r2,-8(fp) + 101a4fc: 18800015 stw r2,0(r3) + pq->OSQEntries++; /* Update the nbr of entries in the queue */ + 101a500: e0bffc17 ldw r2,-16(fp) + 101a504: 1080058b ldhu r2,22(r2) + 101a508: 10800044 addi r2,r2,1 + 101a50c: 1007883a mov r3,r2 + 101a510: e0bffc17 ldw r2,-16(fp) + 101a514: 10c0058d sth r3,22(r2) + 101a518: e0bffb17 ldw r2,-20(fp) + 101a51c: e0bff715 stw r2,-36(fp) + 101a520: e0bff717 ldw r2,-36(fp) + 101a524: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_NONE); + 101a528: e03fff15 stw zero,-4(fp) + 101a52c: e0bfff17 ldw r2,-4(fp) +} + 101a530: e037883a mov sp,fp + 101a534: dfc00117 ldw ra,4(sp) + 101a538: df000017 ldw fp,0(sp) + 101a53c: dec00204 addi sp,sp,8 + 101a540: f800283a ret + +0101a544 : +********************************************************************************************************* +*/ + +#if OS_Q_POST_OPT_EN > 0 +INT8U OSQPostOpt (OS_EVENT *pevent, void *pmsg, INT8U opt) +{ + 101a544: defff404 addi sp,sp,-48 + 101a548: dfc00b15 stw ra,44(sp) + 101a54c: df000a15 stw fp,40(sp) + 101a550: df000a04 addi fp,sp,40 + 101a554: e13ffc15 stw r4,-16(fp) + 101a558: e17ffd15 stw r5,-12(fp) + 101a55c: e1bffe05 stb r6,-8(fp) + OS_Q *pq; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 101a560: e03ffa15 stw zero,-24(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + 101a564: e0bffc17 ldw r2,-16(fp) + 101a568: 1004c03a cmpne r2,r2,zero + 101a56c: 1000031e bne r2,zero,101a57c + return (OS_ERR_PEVENT_NULL); + 101a570: 00800104 movi r2,4 + 101a574: e0bfff15 stw r2,-4(fp) + 101a578: 00007906 br 101a760 + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_Q) { /* Validate event block type */ + 101a57c: e0bffc17 ldw r2,-16(fp) + 101a580: 10800003 ldbu r2,0(r2) + 101a584: 10803fcc andi r2,r2,255 + 101a588: 108000a0 cmpeqi r2,r2,2 + 101a58c: 1000031e bne r2,zero,101a59c + return (OS_ERR_EVENT_TYPE); + 101a590: 00800044 movi r2,1 + 101a594: e0bfff15 stw r2,-4(fp) + 101a598: 00007106 br 101a760 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 101a59c: 0005303a rdctl r2,status + 101a5a0: e0bff915 stw r2,-28(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 101a5a4: e0fff917 ldw r3,-28(fp) + 101a5a8: 00bfff84 movi r2,-2 + 101a5ac: 1884703a and r2,r3,r2 + 101a5b0: 1001703a wrctl status,r2 + + return context; + 101a5b4: e0bff917 ldw r2,-28(fp) + } + OS_ENTER_CRITICAL(); + 101a5b8: e0bffa15 stw r2,-24(fp) + if (pevent->OSEventGrp != 0x00) { /* See if any task pending on queue */ + 101a5bc: e0bffc17 ldw r2,-16(fp) + 101a5c0: 10800283 ldbu r2,10(r2) + 101a5c4: 10803fcc andi r2,r2,255 + 101a5c8: 1005003a cmpeq r2,r2,zero + 101a5cc: 1000211e bne r2,zero,101a654 + if ((opt & OS_POST_OPT_BROADCAST) != 0x00) { /* Do we need to post msg to ALL waiting tasks ? */ + 101a5d0: e0bffe03 ldbu r2,-8(fp) + 101a5d4: 1080004c andi r2,r2,1 + 101a5d8: 10803fcc andi r2,r2,255 + 101a5dc: 1005003a cmpeq r2,r2,zero + 101a5e0: 10000c1e bne r2,zero,101a614 + while (pevent->OSEventGrp != 0) { /* Yes, Post to ALL tasks waiting on queue */ + 101a5e4: 00000506 br 101a5fc + (void)OS_EventTaskRdy(pevent, pmsg, OS_STAT_Q, OS_STAT_PEND_OK); + 101a5e8: e13ffc17 ldw r4,-16(fp) + 101a5ec: e17ffd17 ldw r5,-12(fp) + 101a5f0: 01800104 movi r6,4 + 101a5f4: 000f883a mov r7,zero + 101a5f8: 10162780 call 1016278 + return (OS_ERR_EVENT_TYPE); + } + OS_ENTER_CRITICAL(); + if (pevent->OSEventGrp != 0x00) { /* See if any task pending on queue */ + if ((opt & OS_POST_OPT_BROADCAST) != 0x00) { /* Do we need to post msg to ALL waiting tasks ? */ + while (pevent->OSEventGrp != 0) { /* Yes, Post to ALL tasks waiting on queue */ + 101a5fc: e0bffc17 ldw r2,-16(fp) + 101a600: 10800283 ldbu r2,10(r2) + 101a604: 10803fcc andi r2,r2,255 + 101a608: 1004c03a cmpne r2,r2,zero + 101a60c: 103ff61e bne r2,zero,101a5e8 + 101a610: 00000506 br 101a628 + (void)OS_EventTaskRdy(pevent, pmsg, OS_STAT_Q, OS_STAT_PEND_OK); + } + } else { /* No, Post to HPT waiting on queue */ + (void)OS_EventTaskRdy(pevent, pmsg, OS_STAT_Q, OS_STAT_PEND_OK); + 101a614: e13ffc17 ldw r4,-16(fp) + 101a618: e17ffd17 ldw r5,-12(fp) + 101a61c: 01800104 movi r6,4 + 101a620: 000f883a mov r7,zero + 101a624: 10162780 call 1016278 + 101a628: e0bffa17 ldw r2,-24(fp) + 101a62c: e0bff815 stw r2,-32(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 101a630: e0bff817 ldw r2,-32(fp) + 101a634: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); + if ((opt & OS_POST_OPT_NO_SCHED) == 0) { /* See if scheduler needs to be invoked */ + 101a638: e0bffe03 ldbu r2,-8(fp) + 101a63c: 1080010c andi r2,r2,4 + 101a640: 1004c03a cmpne r2,r2,zero + 101a644: 1000011e bne r2,zero,101a64c + OS_Sched(); /* Find highest priority task ready to run */ + 101a648: 1016cb80 call 1016cb8 + } + return (OS_ERR_NONE); + 101a64c: e03fff15 stw zero,-4(fp) + 101a650: 00004306 br 101a760 + } + pq = (OS_Q *)pevent->OSEventPtr; /* Point to queue control block */ + 101a654: e0bffc17 ldw r2,-16(fp) + 101a658: 10800117 ldw r2,4(r2) + 101a65c: e0bffb15 stw r2,-20(fp) + if (pq->OSQEntries >= pq->OSQSize) { /* Make sure queue is not full */ + 101a660: e0bffb17 ldw r2,-20(fp) + 101a664: 10c0058b ldhu r3,22(r2) + 101a668: e0bffb17 ldw r2,-20(fp) + 101a66c: 1080050b ldhu r2,20(r2) + 101a670: 18ffffcc andi r3,r3,65535 + 101a674: 10bfffcc andi r2,r2,65535 + 101a678: 18800736 bltu r3,r2,101a698 + 101a67c: e0bffa17 ldw r2,-24(fp) + 101a680: e0bff715 stw r2,-36(fp) + 101a684: e0bff717 ldw r2,-36(fp) + 101a688: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_Q_FULL); + 101a68c: 00800784 movi r2,30 + 101a690: e0bfff15 stw r2,-4(fp) + 101a694: 00003206 br 101a760 + } + if ((opt & OS_POST_OPT_FRONT) != 0x00) { /* Do we post to the FRONT of the queue? */ + 101a698: e0bffe03 ldbu r2,-8(fp) + 101a69c: 1080008c andi r2,r2,2 + 101a6a0: 1005003a cmpeq r2,r2,zero + 101a6a4: 1000131e bne r2,zero,101a6f4 + if (pq->OSQOut == pq->OSQStart) { /* Yes, Post as LIFO, Wrap OUT pointer if we ... */ + 101a6a8: e0bffb17 ldw r2,-20(fp) + 101a6ac: 10c00417 ldw r3,16(r2) + 101a6b0: e0bffb17 ldw r2,-20(fp) + 101a6b4: 10800117 ldw r2,4(r2) + 101a6b8: 1880041e bne r3,r2,101a6cc + pq->OSQOut = pq->OSQEnd; /* ... are at the 1st queue entry */ + 101a6bc: e0bffb17 ldw r2,-20(fp) + 101a6c0: 10c00217 ldw r3,8(r2) + 101a6c4: e0bffb17 ldw r2,-20(fp) + 101a6c8: 10c00415 stw r3,16(r2) + } + pq->OSQOut--; + 101a6cc: e0bffb17 ldw r2,-20(fp) + 101a6d0: 10800417 ldw r2,16(r2) + 101a6d4: 10ffff04 addi r3,r2,-4 + 101a6d8: e0bffb17 ldw r2,-20(fp) + 101a6dc: 10c00415 stw r3,16(r2) + *pq->OSQOut = pmsg; /* Insert message into queue */ + 101a6e0: e0bffb17 ldw r2,-20(fp) + 101a6e4: 10c00417 ldw r3,16(r2) + 101a6e8: e0bffd17 ldw r2,-12(fp) + 101a6ec: 18800015 stw r2,0(r3) + 101a6f0: 00001006 br 101a734 + } else { /* No, Post as FIFO */ + *pq->OSQIn++ = pmsg; /* Insert message into queue */ + 101a6f4: e0bffb17 ldw r2,-20(fp) + 101a6f8: 10c00317 ldw r3,12(r2) + 101a6fc: e0bffd17 ldw r2,-12(fp) + 101a700: 18800015 stw r2,0(r3) + 101a704: 18c00104 addi r3,r3,4 + 101a708: e0bffb17 ldw r2,-20(fp) + 101a70c: 10c00315 stw r3,12(r2) + if (pq->OSQIn == pq->OSQEnd) { /* Wrap IN ptr if we are at end of queue */ + 101a710: e0bffb17 ldw r2,-20(fp) + 101a714: 10c00317 ldw r3,12(r2) + 101a718: e0bffb17 ldw r2,-20(fp) + 101a71c: 10800217 ldw r2,8(r2) + 101a720: 1880041e bne r3,r2,101a734 + pq->OSQIn = pq->OSQStart; + 101a724: e0bffb17 ldw r2,-20(fp) + 101a728: 10c00117 ldw r3,4(r2) + 101a72c: e0bffb17 ldw r2,-20(fp) + 101a730: 10c00315 stw r3,12(r2) + } + } + pq->OSQEntries++; /* Update the nbr of entries in the queue */ + 101a734: e0bffb17 ldw r2,-20(fp) + 101a738: 1080058b ldhu r2,22(r2) + 101a73c: 10800044 addi r2,r2,1 + 101a740: 1007883a mov r3,r2 + 101a744: e0bffb17 ldw r2,-20(fp) + 101a748: 10c0058d sth r3,22(r2) + 101a74c: e0bffa17 ldw r2,-24(fp) + 101a750: e0bff615 stw r2,-40(fp) + 101a754: e0bff617 ldw r2,-40(fp) + 101a758: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_NONE); + 101a75c: e03fff15 stw zero,-4(fp) + 101a760: e0bfff17 ldw r2,-4(fp) +} + 101a764: e037883a mov sp,fp + 101a768: dfc00117 ldw ra,4(sp) + 101a76c: df000017 ldw fp,0(sp) + 101a770: dec00204 addi sp,sp,8 + 101a774: f800283a ret + +0101a778 : +********************************************************************************************************* +*/ + +#if OS_Q_QUERY_EN > 0 +INT8U OSQQuery (OS_EVENT *pevent, OS_Q_DATA *p_q_data) +{ + 101a778: defff504 addi sp,sp,-44 + 101a77c: df000a15 stw fp,40(sp) + 101a780: df000a04 addi fp,sp,40 + 101a784: e13ffd15 stw r4,-12(fp) + 101a788: e17ffe15 stw r5,-8(fp) +#else + INT16U *psrc; + INT16U *pdest; +#endif +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 101a78c: e03ff815 stw zero,-32(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + 101a790: e0bffd17 ldw r2,-12(fp) + 101a794: 1004c03a cmpne r2,r2,zero + 101a798: 1000031e bne r2,zero,101a7a8 + return (OS_ERR_PEVENT_NULL); + 101a79c: 00800104 movi r2,4 + 101a7a0: e0bfff15 stw r2,-4(fp) + 101a7a4: 00004f06 br 101a8e4 + } + if (p_q_data == (OS_Q_DATA *)0) { /* Validate 'p_q_data' */ + 101a7a8: e0bffe17 ldw r2,-8(fp) + 101a7ac: 1004c03a cmpne r2,r2,zero + 101a7b0: 1000031e bne r2,zero,101a7c0 + return (OS_ERR_PDATA_NULL); + 101a7b4: 00800244 movi r2,9 + 101a7b8: e0bfff15 stw r2,-4(fp) + 101a7bc: 00004906 br 101a8e4 + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_Q) { /* Validate event block type */ + 101a7c0: e0bffd17 ldw r2,-12(fp) + 101a7c4: 10800003 ldbu r2,0(r2) + 101a7c8: 10803fcc andi r2,r2,255 + 101a7cc: 108000a0 cmpeqi r2,r2,2 + 101a7d0: 1000031e bne r2,zero,101a7e0 + return (OS_ERR_EVENT_TYPE); + 101a7d4: 00800044 movi r2,1 + 101a7d8: e0bfff15 stw r2,-4(fp) + 101a7dc: 00004106 br 101a8e4 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 101a7e0: 0005303a rdctl r2,status + 101a7e4: e0bff715 stw r2,-36(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 101a7e8: e0fff717 ldw r3,-36(fp) + 101a7ec: 00bfff84 movi r2,-2 + 101a7f0: 1884703a and r2,r3,r2 + 101a7f4: 1001703a wrctl status,r2 + + return context; + 101a7f8: e0bff717 ldw r2,-36(fp) + } + OS_ENTER_CRITICAL(); + 101a7fc: e0bff815 stw r2,-32(fp) + p_q_data->OSEventGrp = pevent->OSEventGrp; /* Copy message queue wait list */ + 101a800: e0bffd17 ldw r2,-12(fp) + 101a804: 10c00283 ldbu r3,10(r2) + 101a808: e0bffe17 ldw r2,-8(fp) + 101a80c: 10c002c5 stb r3,11(r2) + psrc = &pevent->OSEventTbl[0]; + 101a810: e0bffd17 ldw r2,-12(fp) + 101a814: 108002c4 addi r2,r2,11 + 101a818: e0bffa15 stw r2,-24(fp) + pdest = &p_q_data->OSEventTbl[0]; + 101a81c: e0bffe17 ldw r2,-8(fp) + 101a820: 10800204 addi r2,r2,8 + 101a824: e0bff915 stw r2,-28(fp) + for (i = 0; i < OS_EVENT_TBL_SIZE; i++) { + 101a828: e03ffb05 stb zero,-20(fp) + 101a82c: 00000d06 br 101a864 + *pdest++ = *psrc++; + 101a830: e0bffa17 ldw r2,-24(fp) + 101a834: 10c00003 ldbu r3,0(r2) + 101a838: e0bff917 ldw r2,-28(fp) + 101a83c: 10c00005 stb r3,0(r2) + 101a840: e0bff917 ldw r2,-28(fp) + 101a844: 10800044 addi r2,r2,1 + 101a848: e0bff915 stw r2,-28(fp) + 101a84c: e0bffa17 ldw r2,-24(fp) + 101a850: 10800044 addi r2,r2,1 + 101a854: e0bffa15 stw r2,-24(fp) + } + OS_ENTER_CRITICAL(); + p_q_data->OSEventGrp = pevent->OSEventGrp; /* Copy message queue wait list */ + psrc = &pevent->OSEventTbl[0]; + pdest = &p_q_data->OSEventTbl[0]; + for (i = 0; i < OS_EVENT_TBL_SIZE; i++) { + 101a858: e0bffb03 ldbu r2,-20(fp) + 101a85c: 10800044 addi r2,r2,1 + 101a860: e0bffb05 stb r2,-20(fp) + 101a864: e0bffb03 ldbu r2,-20(fp) + 101a868: 108000f0 cmpltui r2,r2,3 + 101a86c: 103ff01e bne r2,zero,101a830 + *pdest++ = *psrc++; + } + pq = (OS_Q *)pevent->OSEventPtr; + 101a870: e0bffd17 ldw r2,-12(fp) + 101a874: 10800117 ldw r2,4(r2) + 101a878: e0bffc15 stw r2,-16(fp) + if (pq->OSQEntries > 0) { + 101a87c: e0bffc17 ldw r2,-16(fp) + 101a880: 1080058b ldhu r2,22(r2) + 101a884: 10bfffcc andi r2,r2,65535 + 101a888: 1005003a cmpeq r2,r2,zero + 101a88c: 1000061e bne r2,zero,101a8a8 + p_q_data->OSMsg = *pq->OSQOut; /* Get next message to return if available */ + 101a890: e0bffc17 ldw r2,-16(fp) + 101a894: 10800417 ldw r2,16(r2) + 101a898: 10c00017 ldw r3,0(r2) + 101a89c: e0bffe17 ldw r2,-8(fp) + 101a8a0: 10c00015 stw r3,0(r2) + 101a8a4: 00000206 br 101a8b0 + } else { + p_q_data->OSMsg = (void *)0; + 101a8a8: e0bffe17 ldw r2,-8(fp) + 101a8ac: 10000015 stw zero,0(r2) + } + p_q_data->OSNMsgs = pq->OSQEntries; + 101a8b0: e0bffc17 ldw r2,-16(fp) + 101a8b4: 10c0058b ldhu r3,22(r2) + 101a8b8: e0bffe17 ldw r2,-8(fp) + 101a8bc: 10c0010d sth r3,4(r2) + p_q_data->OSQSize = pq->OSQSize; + 101a8c0: e0bffc17 ldw r2,-16(fp) + 101a8c4: 10c0050b ldhu r3,20(r2) + 101a8c8: e0bffe17 ldw r2,-8(fp) + 101a8cc: 10c0018d sth r3,6(r2) + 101a8d0: e0bff817 ldw r2,-32(fp) + 101a8d4: e0bff615 stw r2,-40(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 101a8d8: e0bff617 ldw r2,-40(fp) + 101a8dc: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_NONE); + 101a8e0: e03fff15 stw zero,-4(fp) + 101a8e4: e0bfff17 ldw r2,-4(fp) +} + 101a8e8: e037883a mov sp,fp + 101a8ec: df000017 ldw fp,0(sp) + 101a8f0: dec00104 addi sp,sp,4 + 101a8f4: f800283a ret + +0101a8f8 : +* Note(s) : This function is INTERNAL to uC/OS-II and your application should not call it. +********************************************************************************************************* +*/ + +void OS_QInit (void) +{ + 101a8f8: defffb04 addi sp,sp,-20 + 101a8fc: dfc00415 stw ra,16(sp) + 101a900: df000315 stw fp,12(sp) + 101a904: df000304 addi fp,sp,12 + OS_Q *pq1; + OS_Q *pq2; + + + + OS_MemClr((INT8U *)&OSQTbl[0], sizeof(OSQTbl)); /* Clear the queue table */ + 101a908: 010040f4 movhi r4,259 + 101a90c: 212d2504 addi r4,r4,-19308 + 101a910: 01407804 movi r5,480 + 101a914: 1016bf80 call 1016bf8 + pq1 = &OSQTbl[0]; + 101a918: 008040f4 movhi r2,259 + 101a91c: 10ad2504 addi r2,r2,-19308 + 101a920: e0bffe15 stw r2,-8(fp) + pq2 = &OSQTbl[1]; + 101a924: 008040f4 movhi r2,259 + 101a928: 10ad2b04 addi r2,r2,-19284 + 101a92c: e0bffd15 stw r2,-12(fp) + for (i = 0; i < (OS_MAX_QS - 1); i++) { /* Init. list of free QUEUE control blocks */ + 101a930: e03fff0d sth zero,-4(fp) + 101a934: 00000c06 br 101a968 + pq1->OSQPtr = pq2; + 101a938: e0fffe17 ldw r3,-8(fp) + 101a93c: e0bffd17 ldw r2,-12(fp) + 101a940: 18800015 stw r2,0(r3) + pq1++; + 101a944: e0bffe17 ldw r2,-8(fp) + 101a948: 10800604 addi r2,r2,24 + 101a94c: e0bffe15 stw r2,-8(fp) + pq2++; + 101a950: e0bffd17 ldw r2,-12(fp) + 101a954: 10800604 addi r2,r2,24 + 101a958: e0bffd15 stw r2,-12(fp) + + + OS_MemClr((INT8U *)&OSQTbl[0], sizeof(OSQTbl)); /* Clear the queue table */ + pq1 = &OSQTbl[0]; + pq2 = &OSQTbl[1]; + for (i = 0; i < (OS_MAX_QS - 1); i++) { /* Init. list of free QUEUE control blocks */ + 101a95c: e0bfff0b ldhu r2,-4(fp) + 101a960: 10800044 addi r2,r2,1 + 101a964: e0bfff0d sth r2,-4(fp) + 101a968: e0bfff0b ldhu r2,-4(fp) + 101a96c: 108004f0 cmpltui r2,r2,19 + 101a970: 103ff11e bne r2,zero,101a938 + pq1->OSQPtr = pq2; + pq1++; + pq2++; + } + pq1->OSQPtr = (OS_Q *)0; + 101a974: e0bffe17 ldw r2,-8(fp) + 101a978: 10000015 stw zero,0(r2) + OSQFreeList = &OSQTbl[0]; + 101a97c: 00c040b4 movhi r3,258 + 101a980: 18d51f04 addi r3,r3,21628 + 101a984: 008040f4 movhi r2,259 + 101a988: 10ad2504 addi r2,r2,-19308 + 101a98c: 18800015 stw r2,0(r3) +#endif +} + 101a990: e037883a mov sp,fp + 101a994: dfc00117 ldw ra,4(sp) + 101a998: df000017 ldw fp,0(sp) + 101a99c: dec00204 addi sp,sp,8 + 101a9a0: f800283a ret + +0101a9a4 : +********************************************************************************************************* +*/ + +#if OS_SEM_ACCEPT_EN > 0 +INT16U OSSemAccept (OS_EVENT *pevent) +{ + 101a9a4: defff904 addi sp,sp,-28 + 101a9a8: df000615 stw fp,24(sp) + 101a9ac: df000604 addi fp,sp,24 + 101a9b0: e13ffe15 stw r4,-8(fp) + INT16U cnt; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 101a9b4: e03ffc15 stw zero,-16(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + 101a9b8: e0bffe17 ldw r2,-8(fp) + 101a9bc: 1004c03a cmpne r2,r2,zero + 101a9c0: 1000021e bne r2,zero,101a9cc + return (0); + 101a9c4: e03fff15 stw zero,-4(fp) + 101a9c8: 00002106 br 101aa50 + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_SEM) { /* Validate event block type */ + 101a9cc: e0bffe17 ldw r2,-8(fp) + 101a9d0: 10800003 ldbu r2,0(r2) + 101a9d4: 10803fcc andi r2,r2,255 + 101a9d8: 108000e0 cmpeqi r2,r2,3 + 101a9dc: 1000021e bne r2,zero,101a9e8 + return (0); + 101a9e0: e03fff15 stw zero,-4(fp) + 101a9e4: 00001a06 br 101aa50 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 101a9e8: 0005303a rdctl r2,status + 101a9ec: e0bffb15 stw r2,-20(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 101a9f0: e0fffb17 ldw r3,-20(fp) + 101a9f4: 00bfff84 movi r2,-2 + 101a9f8: 1884703a and r2,r3,r2 + 101a9fc: 1001703a wrctl status,r2 + + return context; + 101aa00: e0bffb17 ldw r2,-20(fp) + } + OS_ENTER_CRITICAL(); + 101aa04: e0bffc15 stw r2,-16(fp) + cnt = pevent->OSEventCnt; + 101aa08: e0bffe17 ldw r2,-8(fp) + 101aa0c: 1080020b ldhu r2,8(r2) + 101aa10: e0bffd0d sth r2,-12(fp) + if (cnt > 0) { /* See if resource is available */ + 101aa14: e0bffd0b ldhu r2,-12(fp) + 101aa18: 1005003a cmpeq r2,r2,zero + 101aa1c: 1000061e bne r2,zero,101aa38 + pevent->OSEventCnt--; /* Yes, decrement semaphore and notify caller */ + 101aa20: e0bffe17 ldw r2,-8(fp) + 101aa24: 1080020b ldhu r2,8(r2) + 101aa28: 10bfffc4 addi r2,r2,-1 + 101aa2c: 1007883a mov r3,r2 + 101aa30: e0bffe17 ldw r2,-8(fp) + 101aa34: 10c0020d sth r3,8(r2) + 101aa38: e0bffc17 ldw r2,-16(fp) + 101aa3c: e0bffa15 stw r2,-24(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 101aa40: e0bffa17 ldw r2,-24(fp) + 101aa44: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); + return (cnt); /* Return semaphore count */ + 101aa48: e0bffd0b ldhu r2,-12(fp) + 101aa4c: e0bfff15 stw r2,-4(fp) + 101aa50: e0bfff17 ldw r2,-4(fp) +} + 101aa54: e037883a mov sp,fp + 101aa58: df000017 ldw fp,0(sp) + 101aa5c: dec00104 addi sp,sp,4 + 101aa60: f800283a ret + +0101aa64 : +* == (void *)0 if no event control blocks were available +********************************************************************************************************* +*/ + +OS_EVENT *OSSemCreate (INT16U cnt) +{ + 101aa64: defff804 addi sp,sp,-32 + 101aa68: dfc00715 stw ra,28(sp) + 101aa6c: df000615 stw fp,24(sp) + 101aa70: df000604 addi fp,sp,24 + 101aa74: e13ffe0d sth r4,-8(fp) + OS_EVENT *pevent; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 101aa78: e03ffc15 stw zero,-16(fp) +#endif + + + + if (OSIntNesting > 0) { /* See if called from ISR ... */ + 101aa7c: 008040b4 movhi r2,258 + 101aa80: 10952204 addi r2,r2,21640 + 101aa84: 10800003 ldbu r2,0(r2) + 101aa88: 10803fcc andi r2,r2,255 + 101aa8c: 1005003a cmpeq r2,r2,zero + 101aa90: 1000021e bne r2,zero,101aa9c + return ((OS_EVENT *)0); /* ... can't CREATE from an ISR */ + 101aa94: e03fff15 stw zero,-4(fp) + 101aa98: 00003106 br 101ab60 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 101aa9c: 0005303a rdctl r2,status + 101aaa0: e0bffb15 stw r2,-20(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 101aaa4: e0fffb17 ldw r3,-20(fp) + 101aaa8: 00bfff84 movi r2,-2 + 101aaac: 1884703a and r2,r3,r2 + 101aab0: 1001703a wrctl status,r2 + + return context; + 101aab4: e0bffb17 ldw r2,-20(fp) + } + OS_ENTER_CRITICAL(); + 101aab8: e0bffc15 stw r2,-16(fp) + pevent = OSEventFreeList; /* Get next free event control block */ + 101aabc: 008040b4 movhi r2,258 + 101aac0: 10952104 addi r2,r2,21636 + 101aac4: 10800017 ldw r2,0(r2) + 101aac8: e0bffd15 stw r2,-12(fp) + if (OSEventFreeList != (OS_EVENT *)0) { /* See if pool of free ECB pool was empty */ + 101aacc: 008040b4 movhi r2,258 + 101aad0: 10952104 addi r2,r2,21636 + 101aad4: 10800017 ldw r2,0(r2) + 101aad8: 1005003a cmpeq r2,r2,zero + 101aadc: 1000081e bne r2,zero,101ab00 + OSEventFreeList = (OS_EVENT *)OSEventFreeList->OSEventPtr; + 101aae0: 008040b4 movhi r2,258 + 101aae4: 10952104 addi r2,r2,21636 + 101aae8: 10800017 ldw r2,0(r2) + 101aaec: 10800117 ldw r2,4(r2) + 101aaf0: 1007883a mov r3,r2 + 101aaf4: 008040b4 movhi r2,258 + 101aaf8: 10952104 addi r2,r2,21636 + 101aafc: 10c00015 stw r3,0(r2) + 101ab00: e0bffc17 ldw r2,-16(fp) + 101ab04: e0bffa15 stw r2,-24(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 101ab08: e0bffa17 ldw r2,-24(fp) + 101ab0c: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); + if (pevent != (OS_EVENT *)0) { /* Get an event control block */ + 101ab10: e0bffd17 ldw r2,-12(fp) + 101ab14: 1005003a cmpeq r2,r2,zero + 101ab18: 10000f1e bne r2,zero,101ab58 + pevent->OSEventType = OS_EVENT_TYPE_SEM; + 101ab1c: e0fffd17 ldw r3,-12(fp) + 101ab20: 008000c4 movi r2,3 + 101ab24: 18800005 stb r2,0(r3) + pevent->OSEventCnt = cnt; /* Set semaphore value */ + 101ab28: e0fffd17 ldw r3,-12(fp) + 101ab2c: e0bffe0b ldhu r2,-8(fp) + 101ab30: 1880020d sth r2,8(r3) + pevent->OSEventPtr = (void *)0; /* Unlink from ECB free list */ + 101ab34: e0bffd17 ldw r2,-12(fp) + 101ab38: 10000115 stw zero,4(r2) +#if OS_EVENT_NAME_SIZE > 1 + pevent->OSEventName[0] = '?'; /* Unknown name */ + 101ab3c: e0fffd17 ldw r3,-12(fp) + 101ab40: 00800fc4 movi r2,63 + 101ab44: 18800385 stb r2,14(r3) + pevent->OSEventName[1] = OS_ASCII_NUL; + 101ab48: e0bffd17 ldw r2,-12(fp) + 101ab4c: 100003c5 stb zero,15(r2) +#endif + OS_EventWaitListInit(pevent); /* Initialize to 'nobody waiting' on sem. */ + 101ab50: e13ffd17 ldw r4,-12(fp) + 101ab54: 101682c0 call 101682c + } + return (pevent); + 101ab58: e0bffd17 ldw r2,-12(fp) + 101ab5c: e0bfff15 stw r2,-4(fp) + 101ab60: e0bfff17 ldw r2,-4(fp) +} + 101ab64: e037883a mov sp,fp + 101ab68: dfc00117 ldw ra,4(sp) + 101ab6c: df000017 ldw fp,0(sp) + 101ab70: dec00204 addi sp,sp,8 + 101ab74: f800283a ret + +0101ab78 : +********************************************************************************************************* +*/ + +#if OS_SEM_DEL_EN > 0 +OS_EVENT *OSSemDel (OS_EVENT *pevent, INT8U opt, INT8U *perr) +{ + 101ab78: defff104 addi sp,sp,-60 + 101ab7c: dfc00e15 stw ra,56(sp) + 101ab80: df000d15 stw fp,52(sp) + 101ab84: df000d04 addi fp,sp,52 + 101ab88: e13ffb15 stw r4,-20(fp) + 101ab8c: e1bffd15 stw r6,-12(fp) + 101ab90: e17ffc05 stb r5,-16(fp) + BOOLEAN tasks_waiting; + OS_EVENT *pevent_return; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 101ab94: e03ff815 stw zero,-32(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + 101ab98: e0bffd17 ldw r2,-12(fp) + 101ab9c: 1004c03a cmpne r2,r2,zero + 101aba0: 1000031e bne r2,zero,101abb0 + return (pevent); + 101aba4: e0bffb17 ldw r2,-20(fp) + 101aba8: e0bfff15 stw r2,-4(fp) + 101abac: 00009406 br 101ae00 + } + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + 101abb0: e0bffb17 ldw r2,-20(fp) + 101abb4: 1004c03a cmpne r2,r2,zero + 101abb8: 1000061e bne r2,zero,101abd4 + *perr = OS_ERR_PEVENT_NULL; + 101abbc: e0fffd17 ldw r3,-12(fp) + 101abc0: 00800104 movi r2,4 + 101abc4: 18800005 stb r2,0(r3) + return (pevent); + 101abc8: e0fffb17 ldw r3,-20(fp) + 101abcc: e0ffff15 stw r3,-4(fp) + 101abd0: 00008b06 br 101ae00 + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_SEM) { /* Validate event block type */ + 101abd4: e0bffb17 ldw r2,-20(fp) + 101abd8: 10800003 ldbu r2,0(r2) + 101abdc: 10803fcc andi r2,r2,255 + 101abe0: 108000e0 cmpeqi r2,r2,3 + 101abe4: 1000061e bne r2,zero,101ac00 + *perr = OS_ERR_EVENT_TYPE; + 101abe8: e0fffd17 ldw r3,-12(fp) + 101abec: 00800044 movi r2,1 + 101abf0: 18800005 stb r2,0(r3) + return (pevent); + 101abf4: e0bffb17 ldw r2,-20(fp) + 101abf8: e0bfff15 stw r2,-4(fp) + 101abfc: 00008006 br 101ae00 + } + if (OSIntNesting > 0) { /* See if called from ISR ... */ + 101ac00: 008040b4 movhi r2,258 + 101ac04: 10952204 addi r2,r2,21640 + 101ac08: 10800003 ldbu r2,0(r2) + 101ac0c: 10803fcc andi r2,r2,255 + 101ac10: 1005003a cmpeq r2,r2,zero + 101ac14: 1000061e bne r2,zero,101ac30 + *perr = OS_ERR_DEL_ISR; /* ... can't DELETE from an ISR */ + 101ac18: e0fffd17 ldw r3,-12(fp) + 101ac1c: 008003c4 movi r2,15 + 101ac20: 18800005 stb r2,0(r3) + return (pevent); + 101ac24: e0fffb17 ldw r3,-20(fp) + 101ac28: e0ffff15 stw r3,-4(fp) + 101ac2c: 00007406 br 101ae00 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 101ac30: 0005303a rdctl r2,status + 101ac34: e0bff715 stw r2,-36(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 101ac38: e0fff717 ldw r3,-36(fp) + 101ac3c: 00bfff84 movi r2,-2 + 101ac40: 1884703a and r2,r3,r2 + 101ac44: 1001703a wrctl status,r2 + + return context; + 101ac48: e0bff717 ldw r2,-36(fp) + } + OS_ENTER_CRITICAL(); + 101ac4c: e0bff815 stw r2,-32(fp) + if (pevent->OSEventGrp != 0) { /* See if any tasks waiting on semaphore */ + 101ac50: e0bffb17 ldw r2,-20(fp) + 101ac54: 10800283 ldbu r2,10(r2) + 101ac58: 10803fcc andi r2,r2,255 + 101ac5c: 1005003a cmpeq r2,r2,zero + 101ac60: 1000031e bne r2,zero,101ac70 + tasks_waiting = OS_TRUE; /* Yes */ + 101ac64: 00800044 movi r2,1 + 101ac68: e0bffa05 stb r2,-24(fp) + 101ac6c: 00000106 br 101ac74 + } else { + tasks_waiting = OS_FALSE; /* No */ + 101ac70: e03ffa05 stb zero,-24(fp) + } + switch (opt) { + 101ac74: e0bffc03 ldbu r2,-16(fp) + 101ac78: e0bffe15 stw r2,-8(fp) + 101ac7c: e0fffe17 ldw r3,-8(fp) + 101ac80: 1805003a cmpeq r2,r3,zero + 101ac84: 1000041e bne r2,zero,101ac98 + 101ac88: e0fffe17 ldw r3,-8(fp) + 101ac8c: 18800060 cmpeqi r2,r3,1 + 101ac90: 10002d1e bne r2,zero,101ad48 + 101ac94: 00004f06 br 101add4 + case OS_DEL_NO_PEND: /* Delete semaphore only if no task waiting */ + if (tasks_waiting == OS_FALSE) { + 101ac98: e0bffa03 ldbu r2,-24(fp) + 101ac9c: 1004c03a cmpne r2,r2,zero + 101aca0: 10001a1e bne r2,zero,101ad0c +#if OS_EVENT_NAME_SIZE > 1 + pevent->OSEventName[0] = '?'; /* Unknown name */ + 101aca4: e0fffb17 ldw r3,-20(fp) + 101aca8: 00800fc4 movi r2,63 + 101acac: 18800385 stb r2,14(r3) + pevent->OSEventName[1] = OS_ASCII_NUL; + 101acb0: e0bffb17 ldw r2,-20(fp) + 101acb4: 100003c5 stb zero,15(r2) +#endif + pevent->OSEventType = OS_EVENT_TYPE_UNUSED; + 101acb8: e0bffb17 ldw r2,-20(fp) + 101acbc: 10000005 stb zero,0(r2) + pevent->OSEventPtr = OSEventFreeList; /* Return Event Control Block to free list */ + 101acc0: 008040b4 movhi r2,258 + 101acc4: 10952104 addi r2,r2,21636 + 101acc8: 10c00017 ldw r3,0(r2) + 101accc: e0bffb17 ldw r2,-20(fp) + 101acd0: 10c00115 stw r3,4(r2) + pevent->OSEventCnt = 0; + 101acd4: e0bffb17 ldw r2,-20(fp) + 101acd8: 1000020d sth zero,8(r2) + OSEventFreeList = pevent; /* Get next free event control block */ + 101acdc: 00c040b4 movhi r3,258 + 101ace0: 18d52104 addi r3,r3,21636 + 101ace4: e0bffb17 ldw r2,-20(fp) + 101ace8: 18800015 stw r2,0(r3) + 101acec: e0bff817 ldw r2,-32(fp) + 101acf0: e0bff615 stw r2,-40(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 101acf4: e0bff617 ldw r2,-40(fp) + 101acf8: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + 101acfc: e0bffd17 ldw r2,-12(fp) + 101ad00: 10000005 stb zero,0(r2) + pevent_return = (OS_EVENT *)0; /* Semaphore has been deleted */ + 101ad04: e03ff915 stw zero,-28(fp) + 101ad08: 00003b06 br 101adf8 + 101ad0c: e0bff817 ldw r2,-32(fp) + 101ad10: e0bff515 stw r2,-44(fp) + 101ad14: e0bff517 ldw r2,-44(fp) + 101ad18: 1001703a wrctl status,r2 + } else { + OS_EXIT_CRITICAL(); + *perr = OS_ERR_TASK_WAITING; + 101ad1c: e0fffd17 ldw r3,-12(fp) + 101ad20: 00801244 movi r2,73 + 101ad24: 18800005 stb r2,0(r3) + pevent_return = pevent; + 101ad28: e0bffb17 ldw r2,-20(fp) + 101ad2c: e0bff915 stw r2,-28(fp) + } + break; + 101ad30: 00003106 br 101adf8 + + case OS_DEL_ALWAYS: /* Always delete the semaphore */ + while (pevent->OSEventGrp != 0) { /* Ready ALL tasks waiting for semaphore */ + (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_SEM, OS_STAT_PEND_OK); + 101ad34: e13ffb17 ldw r4,-20(fp) + 101ad38: 000b883a mov r5,zero + 101ad3c: 01800044 movi r6,1 + 101ad40: 000f883a mov r7,zero + 101ad44: 10162780 call 1016278 + pevent_return = pevent; + } + break; + + case OS_DEL_ALWAYS: /* Always delete the semaphore */ + while (pevent->OSEventGrp != 0) { /* Ready ALL tasks waiting for semaphore */ + 101ad48: e0bffb17 ldw r2,-20(fp) + 101ad4c: 10800283 ldbu r2,10(r2) + 101ad50: 10803fcc andi r2,r2,255 + 101ad54: 1004c03a cmpne r2,r2,zero + 101ad58: 103ff61e bne r2,zero,101ad34 + (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_SEM, OS_STAT_PEND_OK); + } +#if OS_EVENT_NAME_SIZE > 1 + pevent->OSEventName[0] = '?'; /* Unknown name */ + 101ad5c: e0fffb17 ldw r3,-20(fp) + 101ad60: 00800fc4 movi r2,63 + 101ad64: 18800385 stb r2,14(r3) + pevent->OSEventName[1] = OS_ASCII_NUL; + 101ad68: e0bffb17 ldw r2,-20(fp) + 101ad6c: 100003c5 stb zero,15(r2) +#endif + pevent->OSEventType = OS_EVENT_TYPE_UNUSED; + 101ad70: e0bffb17 ldw r2,-20(fp) + 101ad74: 10000005 stb zero,0(r2) + pevent->OSEventPtr = OSEventFreeList; /* Return Event Control Block to free list */ + 101ad78: 008040b4 movhi r2,258 + 101ad7c: 10952104 addi r2,r2,21636 + 101ad80: 10c00017 ldw r3,0(r2) + 101ad84: e0bffb17 ldw r2,-20(fp) + 101ad88: 10c00115 stw r3,4(r2) + pevent->OSEventCnt = 0; + 101ad8c: e0bffb17 ldw r2,-20(fp) + 101ad90: 1000020d sth zero,8(r2) + OSEventFreeList = pevent; /* Get next free event control block */ + 101ad94: 00c040b4 movhi r3,258 + 101ad98: 18d52104 addi r3,r3,21636 + 101ad9c: e0bffb17 ldw r2,-20(fp) + 101ada0: 18800015 stw r2,0(r3) + 101ada4: e0bff817 ldw r2,-32(fp) + 101ada8: e0bff415 stw r2,-48(fp) + 101adac: e0bff417 ldw r2,-48(fp) + 101adb0: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + if (tasks_waiting == OS_TRUE) { /* Reschedule only if task(s) were waiting */ + 101adb4: e0bffa03 ldbu r2,-24(fp) + 101adb8: 10800058 cmpnei r2,r2,1 + 101adbc: 1000011e bne r2,zero,101adc4 + OS_Sched(); /* Find highest priority task ready to run */ + 101adc0: 1016cb80 call 1016cb8 + } + *perr = OS_ERR_NONE; + 101adc4: e0bffd17 ldw r2,-12(fp) + 101adc8: 10000005 stb zero,0(r2) + pevent_return = (OS_EVENT *)0; /* Semaphore has been deleted */ + 101adcc: e03ff915 stw zero,-28(fp) + break; + 101add0: 00000906 br 101adf8 + 101add4: e0bff817 ldw r2,-32(fp) + 101add8: e0bff315 stw r2,-52(fp) + 101addc: e0bff317 ldw r2,-52(fp) + 101ade0: 1001703a wrctl status,r2 + + default: + OS_EXIT_CRITICAL(); + *perr = OS_ERR_INVALID_OPT; + 101ade4: e0fffd17 ldw r3,-12(fp) + 101ade8: 008001c4 movi r2,7 + 101adec: 18800005 stb r2,0(r3) + pevent_return = pevent; + 101adf0: e0bffb17 ldw r2,-20(fp) + 101adf4: e0bff915 stw r2,-28(fp) + break; + } + return (pevent_return); + 101adf8: e0bff917 ldw r2,-28(fp) + 101adfc: e0bfff15 stw r2,-4(fp) + 101ae00: e0bfff17 ldw r2,-4(fp) +} + 101ae04: e037883a mov sp,fp + 101ae08: dfc00117 ldw ra,4(sp) + 101ae0c: df000017 ldw fp,0(sp) + 101ae10: dec00204 addi sp,sp,8 + 101ae14: f800283a ret + +0101ae18 : +* Returns : none +********************************************************************************************************* +*/ +/*$PAGE*/ +void OSSemPend (OS_EVENT *pevent, INT16U timeout, INT8U *perr) +{ + 101ae18: defff404 addi sp,sp,-48 + 101ae1c: dfc00b15 stw ra,44(sp) + 101ae20: df000a15 stw fp,40(sp) + 101ae24: df000a04 addi fp,sp,40 + 101ae28: e13ffc15 stw r4,-16(fp) + 101ae2c: e1bffe15 stw r6,-8(fp) + 101ae30: e17ffd0d sth r5,-12(fp) +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 101ae34: e03ffb15 stw zero,-20(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + 101ae38: e0bffe17 ldw r2,-8(fp) + 101ae3c: 1005003a cmpeq r2,r2,zero + 101ae40: 10008f1e bne r2,zero,101b080 + return; + } + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + 101ae44: e0bffc17 ldw r2,-16(fp) + 101ae48: 1004c03a cmpne r2,r2,zero + 101ae4c: 1000041e bne r2,zero,101ae60 + *perr = OS_ERR_PEVENT_NULL; + 101ae50: e0fffe17 ldw r3,-8(fp) + 101ae54: 00800104 movi r2,4 + 101ae58: 18800005 stb r2,0(r3) + return; + 101ae5c: 00008806 br 101b080 + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_SEM) { /* Validate event block type */ + 101ae60: e0bffc17 ldw r2,-16(fp) + 101ae64: 10800003 ldbu r2,0(r2) + 101ae68: 10803fcc andi r2,r2,255 + 101ae6c: 108000e0 cmpeqi r2,r2,3 + 101ae70: 1000041e bne r2,zero,101ae84 + *perr = OS_ERR_EVENT_TYPE; + 101ae74: e0fffe17 ldw r3,-8(fp) + 101ae78: 00800044 movi r2,1 + 101ae7c: 18800005 stb r2,0(r3) + return; + 101ae80: 00007f06 br 101b080 + } + if (OSIntNesting > 0) { /* See if called from ISR ... */ + 101ae84: 008040b4 movhi r2,258 + 101ae88: 10952204 addi r2,r2,21640 + 101ae8c: 10800003 ldbu r2,0(r2) + 101ae90: 10803fcc andi r2,r2,255 + 101ae94: 1005003a cmpeq r2,r2,zero + 101ae98: 1000041e bne r2,zero,101aeac + *perr = OS_ERR_PEND_ISR; /* ... can't PEND from an ISR */ + 101ae9c: e0fffe17 ldw r3,-8(fp) + 101aea0: 00800084 movi r2,2 + 101aea4: 18800005 stb r2,0(r3) + return; + 101aea8: 00007506 br 101b080 + } + if (OSLockNesting > 0) { /* See if called with scheduler locked ... */ + 101aeac: 008040b4 movhi r2,258 + 101aeb0: 10951404 addi r2,r2,21584 + 101aeb4: 10800003 ldbu r2,0(r2) + 101aeb8: 10803fcc andi r2,r2,255 + 101aebc: 1005003a cmpeq r2,r2,zero + 101aec0: 1000041e bne r2,zero,101aed4 + *perr = OS_ERR_PEND_LOCKED; /* ... can't PEND when locked */ + 101aec4: e0fffe17 ldw r3,-8(fp) + 101aec8: 00800344 movi r2,13 + 101aecc: 18800005 stb r2,0(r3) + return; + 101aed0: 00006b06 br 101b080 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 101aed4: 0005303a rdctl r2,status + 101aed8: e0bffa15 stw r2,-24(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 101aedc: e0fffa17 ldw r3,-24(fp) + 101aee0: 00bfff84 movi r2,-2 + 101aee4: 1884703a and r2,r3,r2 + 101aee8: 1001703a wrctl status,r2 + + return context; + 101aeec: e0bffa17 ldw r2,-24(fp) + } + OS_ENTER_CRITICAL(); + 101aef0: e0bffb15 stw r2,-20(fp) + if (pevent->OSEventCnt > 0) { /* If sem. is positive, resource available ... */ + 101aef4: e0bffc17 ldw r2,-16(fp) + 101aef8: 1080020b ldhu r2,8(r2) + 101aefc: 10bfffcc andi r2,r2,65535 + 101af00: 1005003a cmpeq r2,r2,zero + 101af04: 10000d1e bne r2,zero,101af3c + pevent->OSEventCnt--; /* ... decrement semaphore only if positive. */ + 101af08: e0bffc17 ldw r2,-16(fp) + 101af0c: 1080020b ldhu r2,8(r2) + 101af10: 10bfffc4 addi r2,r2,-1 + 101af14: 1007883a mov r3,r2 + 101af18: e0bffc17 ldw r2,-16(fp) + 101af1c: 10c0020d sth r3,8(r2) + 101af20: e0bffb17 ldw r2,-20(fp) + 101af24: e0bff915 stw r2,-28(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 101af28: e0bff917 ldw r2,-28(fp) + 101af2c: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + 101af30: e0bffe17 ldw r2,-8(fp) + 101af34: 10000005 stb zero,0(r2) + return; + 101af38: 00005106 br 101b080 + } + /* Otherwise, must wait until event occurs */ + OSTCBCur->OSTCBStat |= OS_STAT_SEM; /* Resource not available, pend on semaphore */ + 101af3c: 008040b4 movhi r2,258 + 101af40: 10952304 addi r2,r2,21644 + 101af44: 10c00017 ldw r3,0(r2) + 101af48: 008040b4 movhi r2,258 + 101af4c: 10952304 addi r2,r2,21644 + 101af50: 10800017 ldw r2,0(r2) + 101af54: 10800c03 ldbu r2,48(r2) + 101af58: 10800054 ori r2,r2,1 + 101af5c: 18800c05 stb r2,48(r3) + OSTCBCur->OSTCBStatPend = OS_STAT_PEND_OK; + 101af60: 008040b4 movhi r2,258 + 101af64: 10952304 addi r2,r2,21644 + 101af68: 10800017 ldw r2,0(r2) + 101af6c: 10000c45 stb zero,49(r2) + OSTCBCur->OSTCBDly = timeout; /* Store pend timeout in TCB */ + 101af70: 008040b4 movhi r2,258 + 101af74: 10952304 addi r2,r2,21644 + 101af78: 10c00017 ldw r3,0(r2) + 101af7c: e0bffd0b ldhu r2,-12(fp) + 101af80: 18800b8d sth r2,46(r3) + OS_EventTaskWait(pevent); /* Suspend task until event or timeout occurs */ + 101af84: e13ffc17 ldw r4,-16(fp) + 101af88: 101640c0 call 101640c + 101af8c: e0bffb17 ldw r2,-20(fp) + 101af90: e0bff815 stw r2,-32(fp) + 101af94: e0bff817 ldw r2,-32(fp) + 101af98: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + OS_Sched(); /* Find next highest priority task ready */ + 101af9c: 1016cb80 call 1016cb8 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 101afa0: 0005303a rdctl r2,status + 101afa4: e0bff715 stw r2,-36(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 101afa8: e0fff717 ldw r3,-36(fp) + 101afac: 00bfff84 movi r2,-2 + 101afb0: 1884703a and r2,r3,r2 + 101afb4: 1001703a wrctl status,r2 + + return context; + 101afb8: e0bff717 ldw r2,-36(fp) + OS_ENTER_CRITICAL(); + 101afbc: e0bffb15 stw r2,-20(fp) + switch (OSTCBCur->OSTCBStatPend) { /* See if we timed-out or aborted */ + 101afc0: 008040b4 movhi r2,258 + 101afc4: 10952304 addi r2,r2,21644 + 101afc8: 10800017 ldw r2,0(r2) + 101afcc: 10800c43 ldbu r2,49(r2) + 101afd0: 10803fcc andi r2,r2,255 + 101afd4: e0bfff15 stw r2,-4(fp) + 101afd8: e0ffff17 ldw r3,-4(fp) + 101afdc: 1805003a cmpeq r2,r3,zero + 101afe0: 1000041e bne r2,zero,101aff4 + 101afe4: e0ffff17 ldw r3,-4(fp) + 101afe8: 188000a0 cmpeqi r2,r3,2 + 101afec: 1000041e bne r2,zero,101b000 + 101aff0: 00000706 br 101b010 + case OS_STAT_PEND_OK: + *perr = OS_ERR_NONE; + 101aff4: e0bffe17 ldw r2,-8(fp) + 101aff8: 10000005 stb zero,0(r2) + break; + 101affc: 00000c06 br 101b030 + + case OS_STAT_PEND_ABORT: + *perr = OS_ERR_PEND_ABORT; /* Indicate that we aborted */ + 101b000: e0fffe17 ldw r3,-8(fp) + 101b004: 00800384 movi r2,14 + 101b008: 18800005 stb r2,0(r3) + break; + 101b00c: 00000806 br 101b030 + + case OS_STAT_PEND_TO: + default: + OS_EventTaskRemove(OSTCBCur, pevent); + 101b010: 008040b4 movhi r2,258 + 101b014: 10952304 addi r2,r2,21644 + 101b018: 11000017 ldw r4,0(r2) + 101b01c: e17ffc17 ldw r5,-16(fp) + 101b020: 10166700 call 1016670 + *perr = OS_ERR_TIMEOUT; /* Indicate that we didn't get event within TO */ + 101b024: e0fffe17 ldw r3,-8(fp) + 101b028: 00800284 movi r2,10 + 101b02c: 18800005 stb r2,0(r3) + break; + } + OSTCBCur->OSTCBStat = OS_STAT_RDY; /* Set task status to ready */ + 101b030: 008040b4 movhi r2,258 + 101b034: 10952304 addi r2,r2,21644 + 101b038: 10800017 ldw r2,0(r2) + 101b03c: 10000c05 stb zero,48(r2) + OSTCBCur->OSTCBStatPend = OS_STAT_PEND_OK; /* Clear pend status */ + 101b040: 008040b4 movhi r2,258 + 101b044: 10952304 addi r2,r2,21644 + 101b048: 10800017 ldw r2,0(r2) + 101b04c: 10000c45 stb zero,49(r2) + OSTCBCur->OSTCBEventPtr = (OS_EVENT *)0; /* Clear event pointers */ + 101b050: 008040b4 movhi r2,258 + 101b054: 10952304 addi r2,r2,21644 + 101b058: 10800017 ldw r2,0(r2) + 101b05c: 10000715 stw zero,28(r2) +#if (OS_EVENT_MULTI_EN > 0) + OSTCBCur->OSTCBEventMultiPtr = (OS_EVENT **)0; + 101b060: 008040b4 movhi r2,258 + 101b064: 10952304 addi r2,r2,21644 + 101b068: 10800017 ldw r2,0(r2) + 101b06c: 10000815 stw zero,32(r2) + 101b070: e0bffb17 ldw r2,-20(fp) + 101b074: e0bff615 stw r2,-40(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 101b078: e0bff617 ldw r2,-40(fp) + 101b07c: 1001703a wrctl status,r2 +#endif + OS_EXIT_CRITICAL(); +} + 101b080: e037883a mov sp,fp + 101b084: dfc00117 ldw ra,4(sp) + 101b088: df000017 ldw fp,0(sp) + 101b08c: dec00204 addi sp,sp,8 + 101b090: f800283a ret + +0101b094 : +********************************************************************************************************* +*/ + +#if OS_SEM_PEND_ABORT_EN > 0 +INT8U OSSemPendAbort (OS_EVENT *pevent, INT8U opt, INT8U *perr) +{ + 101b094: defff504 addi sp,sp,-44 + 101b098: dfc00a15 stw ra,40(sp) + 101b09c: df000915 stw fp,36(sp) + 101b0a0: df000904 addi fp,sp,36 + 101b0a4: e13ffc15 stw r4,-16(fp) + 101b0a8: e1bffe15 stw r6,-8(fp) + 101b0ac: e17ffd05 stb r5,-12(fp) + INT8U nbr_tasks; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 101b0b0: e03ffa15 stw zero,-24(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + 101b0b4: e0bffe17 ldw r2,-8(fp) + 101b0b8: 1004c03a cmpne r2,r2,zero + 101b0bc: 1000021e bne r2,zero,101b0c8 + return (0); + 101b0c0: e03fff15 stw zero,-4(fp) + 101b0c4: 00004c06 br 101b1f8 + } + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + 101b0c8: e0bffc17 ldw r2,-16(fp) + 101b0cc: 1004c03a cmpne r2,r2,zero + 101b0d0: 1000051e bne r2,zero,101b0e8 + *perr = OS_ERR_PEVENT_NULL; + 101b0d4: e0fffe17 ldw r3,-8(fp) + 101b0d8: 00800104 movi r2,4 + 101b0dc: 18800005 stb r2,0(r3) + return (0); + 101b0e0: e03fff15 stw zero,-4(fp) + 101b0e4: 00004406 br 101b1f8 + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_SEM) { /* Validate event block type */ + 101b0e8: e0bffc17 ldw r2,-16(fp) + 101b0ec: 10800003 ldbu r2,0(r2) + 101b0f0: 10803fcc andi r2,r2,255 + 101b0f4: 108000e0 cmpeqi r2,r2,3 + 101b0f8: 1000051e bne r2,zero,101b110 + *perr = OS_ERR_EVENT_TYPE; + 101b0fc: e0fffe17 ldw r3,-8(fp) + 101b100: 00800044 movi r2,1 + 101b104: 18800005 stb r2,0(r3) + return (0); + 101b108: e03fff15 stw zero,-4(fp) + 101b10c: 00003a06 br 101b1f8 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 101b110: 0005303a rdctl r2,status + 101b114: e0bff915 stw r2,-28(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 101b118: e0fff917 ldw r3,-28(fp) + 101b11c: 00bfff84 movi r2,-2 + 101b120: 1884703a and r2,r3,r2 + 101b124: 1001703a wrctl status,r2 + + return context; + 101b128: e0bff917 ldw r2,-28(fp) + } + OS_ENTER_CRITICAL(); + 101b12c: e0bffa15 stw r2,-24(fp) + if (pevent->OSEventGrp != 0) { /* See if any task waiting on semaphore? */ + 101b130: e0bffc17 ldw r2,-16(fp) + 101b134: 10800283 ldbu r2,10(r2) + 101b138: 10803fcc andi r2,r2,255 + 101b13c: 1005003a cmpeq r2,r2,zero + 101b140: 1000261e bne r2,zero,101b1dc + nbr_tasks = 0; + 101b144: e03ffb05 stb zero,-20(fp) + switch (opt) { + 101b148: e0bffd03 ldbu r2,-12(fp) + 101b14c: 10800060 cmpeqi r2,r2,1 + 101b150: 1000091e bne r2,zero,101b178 + 101b154: 00000e06 br 101b190 + case OS_PEND_OPT_BROADCAST: /* Do we need to abort ALL waiting tasks? */ + while (pevent->OSEventGrp != 0) { /* Yes, ready ALL tasks waiting on semaphore */ + (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_SEM, OS_STAT_PEND_ABORT); + 101b158: e13ffc17 ldw r4,-16(fp) + 101b15c: 000b883a mov r5,zero + 101b160: 01800044 movi r6,1 + 101b164: 01c00084 movi r7,2 + 101b168: 10162780 call 1016278 + nbr_tasks++; + 101b16c: e0bffb03 ldbu r2,-20(fp) + 101b170: 10800044 addi r2,r2,1 + 101b174: e0bffb05 stb r2,-20(fp) + OS_ENTER_CRITICAL(); + if (pevent->OSEventGrp != 0) { /* See if any task waiting on semaphore? */ + nbr_tasks = 0; + switch (opt) { + case OS_PEND_OPT_BROADCAST: /* Do we need to abort ALL waiting tasks? */ + while (pevent->OSEventGrp != 0) { /* Yes, ready ALL tasks waiting on semaphore */ + 101b178: e0bffc17 ldw r2,-16(fp) + 101b17c: 10800283 ldbu r2,10(r2) + 101b180: 10803fcc andi r2,r2,255 + 101b184: 1004c03a cmpne r2,r2,zero + 101b188: 103ff31e bne r2,zero,101b158 + (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_SEM, OS_STAT_PEND_ABORT); + nbr_tasks++; + } + break; + 101b18c: 00000806 br 101b1b0 + + case OS_PEND_OPT_NONE: + default: /* No, ready HPT waiting on semaphore */ + (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_SEM, OS_STAT_PEND_ABORT); + 101b190: e13ffc17 ldw r4,-16(fp) + 101b194: 000b883a mov r5,zero + 101b198: 01800044 movi r6,1 + 101b19c: 01c00084 movi r7,2 + 101b1a0: 10162780 call 1016278 + nbr_tasks++; + 101b1a4: e0bffb03 ldbu r2,-20(fp) + 101b1a8: 10800044 addi r2,r2,1 + 101b1ac: e0bffb05 stb r2,-20(fp) + 101b1b0: e0bffa17 ldw r2,-24(fp) + 101b1b4: e0bff815 stw r2,-32(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 101b1b8: e0bff817 ldw r2,-32(fp) + 101b1bc: 1001703a wrctl status,r2 + break; + } + OS_EXIT_CRITICAL(); + OS_Sched(); /* Find HPT ready to run */ + 101b1c0: 1016cb80 call 1016cb8 + *perr = OS_ERR_PEND_ABORT; + 101b1c4: e0fffe17 ldw r3,-8(fp) + 101b1c8: 00800384 movi r2,14 + 101b1cc: 18800005 stb r2,0(r3) + return (nbr_tasks); + 101b1d0: e0bffb03 ldbu r2,-20(fp) + 101b1d4: e0bfff15 stw r2,-4(fp) + 101b1d8: 00000706 br 101b1f8 + 101b1dc: e0bffa17 ldw r2,-24(fp) + 101b1e0: e0bff715 stw r2,-36(fp) + 101b1e4: e0bff717 ldw r2,-36(fp) + 101b1e8: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + 101b1ec: e0bffe17 ldw r2,-8(fp) + 101b1f0: 10000005 stb zero,0(r2) + return (0); /* No tasks waiting on semaphore */ + 101b1f4: e03fff15 stw zero,-4(fp) + 101b1f8: e0bfff17 ldw r2,-4(fp) +} + 101b1fc: e037883a mov sp,fp + 101b200: dfc00117 ldw ra,4(sp) + 101b204: df000017 ldw fp,0(sp) + 101b208: dec00204 addi sp,sp,8 + 101b20c: f800283a ret + +0101b210 : +* OS_ERR_PEVENT_NULL If 'pevent' is a NULL pointer. +********************************************************************************************************* +*/ + +INT8U OSSemPost (OS_EVENT *pevent) +{ + 101b210: defff704 addi sp,sp,-36 + 101b214: dfc00815 stw ra,32(sp) + 101b218: df000715 stw fp,28(sp) + 101b21c: df000704 addi fp,sp,28 + 101b220: e13ffe15 stw r4,-8(fp) +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 101b224: e03ffd15 stw zero,-12(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + 101b228: e0bffe17 ldw r2,-8(fp) + 101b22c: 1004c03a cmpne r2,r2,zero + 101b230: 1000031e bne r2,zero,101b240 + return (OS_ERR_PEVENT_NULL); + 101b234: 00800104 movi r2,4 + 101b238: e0bfff15 stw r2,-4(fp) + 101b23c: 00003806 br 101b320 + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_SEM) { /* Validate event block type */ + 101b240: e0bffe17 ldw r2,-8(fp) + 101b244: 10800003 ldbu r2,0(r2) + 101b248: 10803fcc andi r2,r2,255 + 101b24c: 108000e0 cmpeqi r2,r2,3 + 101b250: 1000031e bne r2,zero,101b260 + return (OS_ERR_EVENT_TYPE); + 101b254: 00800044 movi r2,1 + 101b258: e0bfff15 stw r2,-4(fp) + 101b25c: 00003006 br 101b320 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 101b260: 0005303a rdctl r2,status + 101b264: e0bffc15 stw r2,-16(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 101b268: e0fffc17 ldw r3,-16(fp) + 101b26c: 00bfff84 movi r2,-2 + 101b270: 1884703a and r2,r3,r2 + 101b274: 1001703a wrctl status,r2 + + return context; + 101b278: e0bffc17 ldw r2,-16(fp) + } + OS_ENTER_CRITICAL(); + 101b27c: e0bffd15 stw r2,-12(fp) + if (pevent->OSEventGrp != 0) { /* See if any task waiting for semaphore */ + 101b280: e0bffe17 ldw r2,-8(fp) + 101b284: 10800283 ldbu r2,10(r2) + 101b288: 10803fcc andi r2,r2,255 + 101b28c: 1005003a cmpeq r2,r2,zero + 101b290: 10000c1e bne r2,zero,101b2c4 + /* Ready HPT waiting on event */ + (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_SEM, OS_STAT_PEND_OK); + 101b294: e13ffe17 ldw r4,-8(fp) + 101b298: 000b883a mov r5,zero + 101b29c: 01800044 movi r6,1 + 101b2a0: 000f883a mov r7,zero + 101b2a4: 10162780 call 1016278 + 101b2a8: e0bffd17 ldw r2,-12(fp) + 101b2ac: e0bffb15 stw r2,-20(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 101b2b0: e0bffb17 ldw r2,-20(fp) + 101b2b4: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + OS_Sched(); /* Find HPT ready to run */ + 101b2b8: 1016cb80 call 1016cb8 + return (OS_ERR_NONE); + 101b2bc: e03fff15 stw zero,-4(fp) + 101b2c0: 00001706 br 101b320 + } + if (pevent->OSEventCnt < 65535u) { /* Make sure semaphore will not overflow */ + 101b2c4: e0bffe17 ldw r2,-8(fp) + 101b2c8: 1080020b ldhu r2,8(r2) + 101b2cc: 10ffffcc andi r3,r2,65535 + 101b2d0: 00bfffd4 movui r2,65535 + 101b2d4: 18800c26 beq r3,r2,101b308 + pevent->OSEventCnt++; /* Increment semaphore count to register event */ + 101b2d8: e0bffe17 ldw r2,-8(fp) + 101b2dc: 1080020b ldhu r2,8(r2) + 101b2e0: 10800044 addi r2,r2,1 + 101b2e4: 1007883a mov r3,r2 + 101b2e8: e0bffe17 ldw r2,-8(fp) + 101b2ec: 10c0020d sth r3,8(r2) + 101b2f0: e0bffd17 ldw r2,-12(fp) + 101b2f4: e0bffa15 stw r2,-24(fp) + 101b2f8: e0bffa17 ldw r2,-24(fp) + 101b2fc: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_NONE); + 101b300: e03fff15 stw zero,-4(fp) + 101b304: 00000606 br 101b320 + 101b308: e0bffd17 ldw r2,-12(fp) + 101b30c: e0bff915 stw r2,-28(fp) + 101b310: e0bff917 ldw r2,-28(fp) + 101b314: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); /* Semaphore value has reached its maximum */ + return (OS_ERR_SEM_OVF); + 101b318: 00800c84 movi r2,50 + 101b31c: e0bfff15 stw r2,-4(fp) + 101b320: e0bfff17 ldw r2,-4(fp) +} + 101b324: e037883a mov sp,fp + 101b328: dfc00117 ldw ra,4(sp) + 101b32c: df000017 ldw fp,0(sp) + 101b330: dec00204 addi sp,sp,8 + 101b334: f800283a ret + +0101b338 : +********************************************************************************************************* +*/ + +#if OS_SEM_QUERY_EN > 0 +INT8U OSSemQuery (OS_EVENT *pevent, OS_SEM_DATA *p_sem_data) +{ + 101b338: defff604 addi sp,sp,-40 + 101b33c: df000915 stw fp,36(sp) + 101b340: df000904 addi fp,sp,36 + 101b344: e13ffd15 stw r4,-12(fp) + 101b348: e17ffe15 stw r5,-8(fp) + INT16U *psrc; + INT16U *pdest; +#endif + INT8U i; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 101b34c: e03ff915 stw zero,-28(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + 101b350: e0bffd17 ldw r2,-12(fp) + 101b354: 1004c03a cmpne r2,r2,zero + 101b358: 1000031e bne r2,zero,101b368 + return (OS_ERR_PEVENT_NULL); + 101b35c: 00800104 movi r2,4 + 101b360: e0bfff15 stw r2,-4(fp) + 101b364: 00003b06 br 101b454 + } + if (p_sem_data == (OS_SEM_DATA *)0) { /* Validate 'p_sem_data' */ + 101b368: e0bffe17 ldw r2,-8(fp) + 101b36c: 1004c03a cmpne r2,r2,zero + 101b370: 1000031e bne r2,zero,101b380 + return (OS_ERR_PDATA_NULL); + 101b374: 00800244 movi r2,9 + 101b378: e0bfff15 stw r2,-4(fp) + 101b37c: 00003506 br 101b454 + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_SEM) { /* Validate event block type */ + 101b380: e0bffd17 ldw r2,-12(fp) + 101b384: 10800003 ldbu r2,0(r2) + 101b388: 10803fcc andi r2,r2,255 + 101b38c: 108000e0 cmpeqi r2,r2,3 + 101b390: 1000031e bne r2,zero,101b3a0 + return (OS_ERR_EVENT_TYPE); + 101b394: 00800044 movi r2,1 + 101b398: e0bfff15 stw r2,-4(fp) + 101b39c: 00002d06 br 101b454 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 101b3a0: 0005303a rdctl r2,status + 101b3a4: e0bff815 stw r2,-32(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 101b3a8: e0fff817 ldw r3,-32(fp) + 101b3ac: 00bfff84 movi r2,-2 + 101b3b0: 1884703a and r2,r3,r2 + 101b3b4: 1001703a wrctl status,r2 + + return context; + 101b3b8: e0bff817 ldw r2,-32(fp) + } + OS_ENTER_CRITICAL(); + 101b3bc: e0bff915 stw r2,-28(fp) + p_sem_data->OSEventGrp = pevent->OSEventGrp; /* Copy message mailbox wait list */ + 101b3c0: e0bffd17 ldw r2,-12(fp) + 101b3c4: 10c00283 ldbu r3,10(r2) + 101b3c8: e0bffe17 ldw r2,-8(fp) + 101b3cc: 10c00145 stb r3,5(r2) + psrc = &pevent->OSEventTbl[0]; + 101b3d0: e0bffd17 ldw r2,-12(fp) + 101b3d4: 108002c4 addi r2,r2,11 + 101b3d8: e0bffc15 stw r2,-16(fp) + pdest = &p_sem_data->OSEventTbl[0]; + 101b3dc: e0bffe17 ldw r2,-8(fp) + 101b3e0: 10800084 addi r2,r2,2 + 101b3e4: e0bffb15 stw r2,-20(fp) + for (i = 0; i < OS_EVENT_TBL_SIZE; i++) { + 101b3e8: e03ffa05 stb zero,-24(fp) + 101b3ec: 00000d06 br 101b424 + *pdest++ = *psrc++; + 101b3f0: e0bffc17 ldw r2,-16(fp) + 101b3f4: 10c00003 ldbu r3,0(r2) + 101b3f8: e0bffb17 ldw r2,-20(fp) + 101b3fc: 10c00005 stb r3,0(r2) + 101b400: e0bffb17 ldw r2,-20(fp) + 101b404: 10800044 addi r2,r2,1 + 101b408: e0bffb15 stw r2,-20(fp) + 101b40c: e0bffc17 ldw r2,-16(fp) + 101b410: 10800044 addi r2,r2,1 + 101b414: e0bffc15 stw r2,-16(fp) + } + OS_ENTER_CRITICAL(); + p_sem_data->OSEventGrp = pevent->OSEventGrp; /* Copy message mailbox wait list */ + psrc = &pevent->OSEventTbl[0]; + pdest = &p_sem_data->OSEventTbl[0]; + for (i = 0; i < OS_EVENT_TBL_SIZE; i++) { + 101b418: e0bffa03 ldbu r2,-24(fp) + 101b41c: 10800044 addi r2,r2,1 + 101b420: e0bffa05 stb r2,-24(fp) + 101b424: e0bffa03 ldbu r2,-24(fp) + 101b428: 108000f0 cmpltui r2,r2,3 + 101b42c: 103ff01e bne r2,zero,101b3f0 + *pdest++ = *psrc++; + } + p_sem_data->OSCnt = pevent->OSEventCnt; /* Get semaphore count */ + 101b430: e0bffd17 ldw r2,-12(fp) + 101b434: 10c0020b ldhu r3,8(r2) + 101b438: e0bffe17 ldw r2,-8(fp) + 101b43c: 10c0000d sth r3,0(r2) + 101b440: e0bff917 ldw r2,-28(fp) + 101b444: e0bff715 stw r2,-36(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 101b448: e0bff717 ldw r2,-36(fp) + 101b44c: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_NONE); + 101b450: e03fff15 stw zero,-4(fp) + 101b454: e0bfff17 ldw r2,-4(fp) +} + 101b458: e037883a mov sp,fp + 101b45c: df000017 ldw fp,0(sp) + 101b460: dec00104 addi sp,sp,4 + 101b464: f800283a ret + +0101b468 : +********************************************************************************************************* +*/ + +#if OS_SEM_SET_EN > 0 +void OSSemSet (OS_EVENT *pevent, INT16U cnt, INT8U *perr) +{ + 101b468: defff904 addi sp,sp,-28 + 101b46c: df000615 stw fp,24(sp) + 101b470: df000604 addi fp,sp,24 + 101b474: e13ffd15 stw r4,-12(fp) + 101b478: e1bfff15 stw r6,-4(fp) + 101b47c: e17ffe0d sth r5,-8(fp) +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 101b480: e03ffc15 stw zero,-16(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + 101b484: e0bfff17 ldw r2,-4(fp) + 101b488: 1005003a cmpeq r2,r2,zero + 101b48c: 1000331e bne r2,zero,101b55c + return; + } + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + 101b490: e0bffd17 ldw r2,-12(fp) + 101b494: 1004c03a cmpne r2,r2,zero + 101b498: 1000041e bne r2,zero,101b4ac + *perr = OS_ERR_PEVENT_NULL; + 101b49c: e0ffff17 ldw r3,-4(fp) + 101b4a0: 00800104 movi r2,4 + 101b4a4: 18800005 stb r2,0(r3) + return; + 101b4a8: 00002c06 br 101b55c + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_SEM) { /* Validate event block type */ + 101b4ac: e0bffd17 ldw r2,-12(fp) + 101b4b0: 10800003 ldbu r2,0(r2) + 101b4b4: 10803fcc andi r2,r2,255 + 101b4b8: 108000e0 cmpeqi r2,r2,3 + 101b4bc: 1000041e bne r2,zero,101b4d0 + *perr = OS_ERR_EVENT_TYPE; + 101b4c0: e0ffff17 ldw r3,-4(fp) + 101b4c4: 00800044 movi r2,1 + 101b4c8: 18800005 stb r2,0(r3) + return; + 101b4cc: 00002306 br 101b55c +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 101b4d0: 0005303a rdctl r2,status + 101b4d4: e0bffb15 stw r2,-20(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 101b4d8: e0fffb17 ldw r3,-20(fp) + 101b4dc: 00bfff84 movi r2,-2 + 101b4e0: 1884703a and r2,r3,r2 + 101b4e4: 1001703a wrctl status,r2 + + return context; + 101b4e8: e0bffb17 ldw r2,-20(fp) + } + OS_ENTER_CRITICAL(); + 101b4ec: e0bffc15 stw r2,-16(fp) + *perr = OS_ERR_NONE; + 101b4f0: e0bfff17 ldw r2,-4(fp) + 101b4f4: 10000005 stb zero,0(r2) + if (pevent->OSEventCnt > 0) { /* See if semaphore already has a count */ + 101b4f8: e0bffd17 ldw r2,-12(fp) + 101b4fc: 1080020b ldhu r2,8(r2) + 101b500: 10bfffcc andi r2,r2,65535 + 101b504: 1005003a cmpeq r2,r2,zero + 101b508: 1000041e bne r2,zero,101b51c + pevent->OSEventCnt = cnt; /* Yes, set it to the new value specified. */ + 101b50c: e0fffd17 ldw r3,-12(fp) + 101b510: e0bffe0b ldhu r2,-8(fp) + 101b514: 1880020d sth r2,8(r3) + 101b518: 00000c06 br 101b54c + } else { /* No */ + if (pevent->OSEventGrp == 0) { /* See if task(s) waiting? */ + 101b51c: e0bffd17 ldw r2,-12(fp) + 101b520: 10800283 ldbu r2,10(r2) + 101b524: 10803fcc andi r2,r2,255 + 101b528: 1004c03a cmpne r2,r2,zero + 101b52c: 1000041e bne r2,zero,101b540 + pevent->OSEventCnt = cnt; /* No, OK to set the value */ + 101b530: e0fffd17 ldw r3,-12(fp) + 101b534: e0bffe0b ldhu r2,-8(fp) + 101b538: 1880020d sth r2,8(r3) + 101b53c: 00000306 br 101b54c + } else { + *perr = OS_ERR_TASK_WAITING; + 101b540: e0ffff17 ldw r3,-4(fp) + 101b544: 00801244 movi r2,73 + 101b548: 18800005 stb r2,0(r3) + 101b54c: e0bffc17 ldw r2,-16(fp) + 101b550: e0bffa15 stw r2,-24(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 101b554: e0bffa17 ldw r2,-24(fp) + 101b558: 1001703a wrctl status,r2 + } + } + OS_EXIT_CRITICAL(); +} + 101b55c: e037883a mov sp,fp + 101b560: df000017 ldw fp,0(sp) + 101b564: dec00104 addi sp,sp,4 + 101b568: f800283a ret + +0101b56c : +********************************************************************************************************* +*/ + +#if OS_TASK_CHANGE_PRIO_EN > 0 +INT8U OSTaskChangePrio (INT8U oldprio, INT8U newprio) +{ + 101b56c: defff004 addi sp,sp,-64 + 101b570: dfc00f15 stw ra,60(sp) + 101b574: df000e15 stw fp,56(sp) + 101b578: df000e04 addi fp,sp,56 + 101b57c: e13ffd05 stb r4,-12(fp) + 101b580: e17ffe05 stb r5,-8(fp) + INT16U bitx_new; + INT16U bity_old; + INT16U bitx_old; +#endif +#if OS_CRITICAL_METHOD == 3 + OS_CPU_SR cpu_sr = 0; /* Storage for CPU status register */ + 101b584: e03ff715 stw zero,-36(fp) +#endif + + +/*$PAGE*/ +#if OS_ARG_CHK_EN > 0 + if (oldprio >= OS_LOWEST_PRIO) { + 101b588: e0bffd03 ldbu r2,-12(fp) + 101b58c: 10800530 cmpltui r2,r2,20 + 101b590: 1000061e bne r2,zero,101b5ac + if (oldprio != OS_PRIO_SELF) { + 101b594: e0bffd03 ldbu r2,-12(fp) + 101b598: 10803fe0 cmpeqi r2,r2,255 + 101b59c: 1000031e bne r2,zero,101b5ac + return (OS_ERR_PRIO_INVALID); + 101b5a0: 00800a84 movi r2,42 + 101b5a4: e0bfff15 stw r2,-4(fp) + 101b5a8: 00014706 br 101bac8 + } + } + if (newprio >= OS_LOWEST_PRIO) { + 101b5ac: e0bffe03 ldbu r2,-8(fp) + 101b5b0: 10800530 cmpltui r2,r2,20 + 101b5b4: 1000031e bne r2,zero,101b5c4 + return (OS_ERR_PRIO_INVALID); + 101b5b8: 00800a84 movi r2,42 + 101b5bc: e0bfff15 stw r2,-4(fp) + 101b5c0: 00014106 br 101bac8 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 101b5c4: 0005303a rdctl r2,status + 101b5c8: e0bff615 stw r2,-40(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 101b5cc: e0fff617 ldw r3,-40(fp) + 101b5d0: 00bfff84 movi r2,-2 + 101b5d4: 1884703a and r2,r3,r2 + 101b5d8: 1001703a wrctl status,r2 + + return context; + 101b5dc: e0bff617 ldw r2,-40(fp) + } +#endif + OS_ENTER_CRITICAL(); + 101b5e0: e0bff715 stw r2,-36(fp) + if (OSTCBPrioTbl[newprio] != (OS_TCB *)0) { /* New priority must not already exist */ + 101b5e4: e0bffe03 ldbu r2,-8(fp) + 101b5e8: 00c040f4 movhi r3,259 + 101b5ec: 18f3b104 addi r3,r3,-12604 + 101b5f0: 1085883a add r2,r2,r2 + 101b5f4: 1085883a add r2,r2,r2 + 101b5f8: 10c5883a add r2,r2,r3 + 101b5fc: 10800017 ldw r2,0(r2) + 101b600: 1005003a cmpeq r2,r2,zero + 101b604: 1000071e bne r2,zero,101b624 + 101b608: e0bff717 ldw r2,-36(fp) + 101b60c: e0bff515 stw r2,-44(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 101b610: e0bff517 ldw r2,-44(fp) + 101b614: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_PRIO_EXIST); + 101b618: 00800a04 movi r2,40 + 101b61c: e0bfff15 stw r2,-4(fp) + 101b620: 00012906 br 101bac8 + } + if (oldprio == OS_PRIO_SELF) { /* See if changing self */ + 101b624: e0bffd03 ldbu r2,-12(fp) + 101b628: 10803fd8 cmpnei r2,r2,255 + 101b62c: 1000051e bne r2,zero,101b644 + oldprio = OSTCBCur->OSTCBPrio; /* Yes, get priority */ + 101b630: 008040b4 movhi r2,258 + 101b634: 10952304 addi r2,r2,21644 + 101b638: 10800017 ldw r2,0(r2) + 101b63c: 10800c83 ldbu r2,50(r2) + 101b640: e0bffd05 stb r2,-12(fp) + } + ptcb = OSTCBPrioTbl[oldprio]; + 101b644: e0bffd03 ldbu r2,-12(fp) + 101b648: 00c040f4 movhi r3,259 + 101b64c: 18f3b104 addi r3,r3,-12604 + 101b650: 1085883a add r2,r2,r2 + 101b654: 1085883a add r2,r2,r2 + 101b658: 10c5883a add r2,r2,r3 + 101b65c: 10800017 ldw r2,0(r2) + 101b660: e0bffa15 stw r2,-24(fp) + if (ptcb == (OS_TCB *)0) { /* Does task to change exist? */ + 101b664: e0bffa17 ldw r2,-24(fp) + 101b668: 1004c03a cmpne r2,r2,zero + 101b66c: 1000071e bne r2,zero,101b68c + 101b670: e0bff717 ldw r2,-36(fp) + 101b674: e0bff415 stw r2,-48(fp) + 101b678: e0bff417 ldw r2,-48(fp) + 101b67c: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); /* No, can't change its priority! */ + return (OS_ERR_PRIO); + 101b680: 00800a44 movi r2,41 + 101b684: e0bfff15 stw r2,-4(fp) + 101b688: 00010f06 br 101bac8 + } + if (ptcb == OS_TCB_RESERVED) { /* Is task assigned to Mutex */ + 101b68c: e0bffa17 ldw r2,-24(fp) + 101b690: 10800058 cmpnei r2,r2,1 + 101b694: 1000071e bne r2,zero,101b6b4 + 101b698: e0bff717 ldw r2,-36(fp) + 101b69c: e0bff315 stw r2,-52(fp) + 101b6a0: e0bff317 ldw r2,-52(fp) + 101b6a4: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); /* No, can't change its priority! */ + return (OS_ERR_TASK_NOT_EXIST); + 101b6a8: 008010c4 movi r2,67 + 101b6ac: e0bfff15 stw r2,-4(fp) + 101b6b0: 00010506 br 101bac8 + } +#if OS_LOWEST_PRIO <= 63 + y_new = (INT8U)(newprio >> 3); /* Yes, compute new TCB fields */ + 101b6b4: e0bffe03 ldbu r2,-8(fp) + 101b6b8: 1004d0fa srli r2,r2,3 + 101b6bc: e0bff985 stb r2,-26(fp) + x_new = (INT8U)(newprio & 0x07); + 101b6c0: e0bffe03 ldbu r2,-8(fp) + 101b6c4: 108001cc andi r2,r2,7 + 101b6c8: e0bff945 stb r2,-27(fp) + bity_new = (INT8U)(1 << y_new); + 101b6cc: e0fff983 ldbu r3,-26(fp) + 101b6d0: 00800044 movi r2,1 + 101b6d4: 10c4983a sll r2,r2,r3 + 101b6d8: e0bff8c5 stb r2,-29(fp) + bitx_new = (INT8U)(1 << x_new); + 101b6dc: e0fff943 ldbu r3,-27(fp) + 101b6e0: 00800044 movi r2,1 + 101b6e4: 10c4983a sll r2,r2,r3 + 101b6e8: e0bff885 stb r2,-30(fp) + x_new = (INT8U)( newprio & 0x0F); + bity_new = (INT16U)(1 << y_new); + bitx_new = (INT16U)(1 << x_new); +#endif + + OSTCBPrioTbl[oldprio] = (OS_TCB *)0; /* Remove TCB from old priority */ + 101b6ec: e0bffd03 ldbu r2,-12(fp) + 101b6f0: 00c040f4 movhi r3,259 + 101b6f4: 18f3b104 addi r3,r3,-12604 + 101b6f8: 1085883a add r2,r2,r2 + 101b6fc: 1085883a add r2,r2,r2 + 101b700: 10c5883a add r2,r2,r3 + 101b704: 10000015 stw zero,0(r2) + OSTCBPrioTbl[newprio] = ptcb; /* Place pointer to TCB @ new priority */ + 101b708: e0bffe03 ldbu r2,-8(fp) + 101b70c: 00c040f4 movhi r3,259 + 101b710: 18f3b104 addi r3,r3,-12604 + 101b714: 1085883a add r2,r2,r2 + 101b718: 1085883a add r2,r2,r2 + 101b71c: 10c7883a add r3,r2,r3 + 101b720: e0bffa17 ldw r2,-24(fp) + 101b724: 18800015 stw r2,0(r3) + y_old = ptcb->OSTCBY; + 101b728: e0bffa17 ldw r2,-24(fp) + 101b72c: 10800d03 ldbu r2,52(r2) + 101b730: e0bff905 stb r2,-28(fp) + bity_old = ptcb->OSTCBBitY; + 101b734: e0bffa17 ldw r2,-24(fp) + 101b738: 10800d83 ldbu r2,54(r2) + 101b73c: e0bff845 stb r2,-31(fp) + bitx_old = ptcb->OSTCBBitX; + 101b740: e0bffa17 ldw r2,-24(fp) + 101b744: 10800d43 ldbu r2,53(r2) + 101b748: e0bff805 stb r2,-32(fp) + if ((OSRdyTbl[y_old] & bitx_old) != 0) { /* If task is ready make it not */ + 101b74c: e0fff903 ldbu r3,-28(fp) + 101b750: 008040b4 movhi r2,258 + 101b754: 10952044 addi r2,r2,21633 + 101b758: 10c5883a add r2,r2,r3 + 101b75c: 10c00003 ldbu r3,0(r2) + 101b760: e0bff803 ldbu r2,-32(fp) + 101b764: 1884703a and r2,r3,r2 + 101b768: 10803fcc andi r2,r2,255 + 101b76c: 1005003a cmpeq r2,r2,zero + 101b770: 1000381e bne r2,zero,101b854 + OSRdyTbl[y_old] &= ~bitx_old; + 101b774: e13ff903 ldbu r4,-28(fp) + 101b778: e0fff903 ldbu r3,-28(fp) + 101b77c: 008040b4 movhi r2,258 + 101b780: 10952044 addi r2,r2,21633 + 101b784: 10c5883a add r2,r2,r3 + 101b788: 10800003 ldbu r2,0(r2) + 101b78c: 1007883a mov r3,r2 + 101b790: e0bff803 ldbu r2,-32(fp) + 101b794: 0084303a nor r2,zero,r2 + 101b798: 1884703a and r2,r3,r2 + 101b79c: 1007883a mov r3,r2 + 101b7a0: 008040b4 movhi r2,258 + 101b7a4: 10952044 addi r2,r2,21633 + 101b7a8: 1105883a add r2,r2,r4 + 101b7ac: 10c00005 stb r3,0(r2) + if (OSRdyTbl[y_old] == 0) { + 101b7b0: e0fff903 ldbu r3,-28(fp) + 101b7b4: 008040b4 movhi r2,258 + 101b7b8: 10952044 addi r2,r2,21633 + 101b7bc: 10c5883a add r2,r2,r3 + 101b7c0: 10800003 ldbu r2,0(r2) + 101b7c4: 10803fcc andi r2,r2,255 + 101b7c8: 1004c03a cmpne r2,r2,zero + 101b7cc: 10000b1e bne r2,zero,101b7fc + OSRdyGrp &= ~bity_old; + 101b7d0: e0bff843 ldbu r2,-31(fp) + 101b7d4: 0084303a nor r2,zero,r2 + 101b7d8: 1007883a mov r3,r2 + 101b7dc: 008040b4 movhi r2,258 + 101b7e0: 10952004 addi r2,r2,21632 + 101b7e4: 10800003 ldbu r2,0(r2) + 101b7e8: 1884703a and r2,r3,r2 + 101b7ec: 1007883a mov r3,r2 + 101b7f0: 008040b4 movhi r2,258 + 101b7f4: 10952004 addi r2,r2,21632 + 101b7f8: 10c00005 stb r3,0(r2) + } + OSRdyGrp |= bity_new; /* Make new priority ready to run */ + 101b7fc: 008040b4 movhi r2,258 + 101b800: 10952004 addi r2,r2,21632 + 101b804: 10c00003 ldbu r3,0(r2) + 101b808: e0bff8c3 ldbu r2,-29(fp) + 101b80c: 1884b03a or r2,r3,r2 + 101b810: 1007883a mov r3,r2 + 101b814: 008040b4 movhi r2,258 + 101b818: 10952004 addi r2,r2,21632 + 101b81c: 10c00005 stb r3,0(r2) + OSRdyTbl[y_new] |= bitx_new; + 101b820: e13ff983 ldbu r4,-26(fp) + 101b824: e0fff983 ldbu r3,-26(fp) + 101b828: 008040b4 movhi r2,258 + 101b82c: 10952044 addi r2,r2,21633 + 101b830: 10c5883a add r2,r2,r3 + 101b834: 10c00003 ldbu r3,0(r2) + 101b838: e0bff883 ldbu r2,-30(fp) + 101b83c: 1884b03a or r2,r3,r2 + 101b840: 1007883a mov r3,r2 + 101b844: 008040b4 movhi r2,258 + 101b848: 10952044 addi r2,r2,21633 + 101b84c: 1105883a add r2,r2,r4 + 101b850: 10c00005 stb r3,0(r2) + } + +#if (OS_EVENT_EN) + pevent = ptcb->OSTCBEventPtr; + 101b854: e0bffa17 ldw r2,-24(fp) + 101b858: 10800717 ldw r2,28(r2) + 101b85c: e0bffc15 stw r2,-16(fp) + if (pevent != (OS_EVENT *)0) { + 101b860: e0bffc17 ldw r2,-16(fp) + 101b864: 1005003a cmpeq r2,r2,zero + 101b868: 1000341e bne r2,zero,101b93c + pevent->OSEventTbl[y_old] &= ~bitx_old; /* Remove old task prio from wait list */ + 101b86c: e13ff903 ldbu r4,-28(fp) + 101b870: e0fff903 ldbu r3,-28(fp) + 101b874: e0bffc17 ldw r2,-16(fp) + 101b878: 1885883a add r2,r3,r2 + 101b87c: 10800204 addi r2,r2,8 + 101b880: 108000c3 ldbu r2,3(r2) + 101b884: 1007883a mov r3,r2 + 101b888: e0bff803 ldbu r2,-32(fp) + 101b88c: 0084303a nor r2,zero,r2 + 101b890: 1884703a and r2,r3,r2 + 101b894: 1007883a mov r3,r2 + 101b898: e0bffc17 ldw r2,-16(fp) + 101b89c: 2085883a add r2,r4,r2 + 101b8a0: 10800204 addi r2,r2,8 + 101b8a4: 10c000c5 stb r3,3(r2) + if (pevent->OSEventTbl[y_old] == 0) { + 101b8a8: e0fff903 ldbu r3,-28(fp) + 101b8ac: e0bffc17 ldw r2,-16(fp) + 101b8b0: 1885883a add r2,r3,r2 + 101b8b4: 10800204 addi r2,r2,8 + 101b8b8: 108000c3 ldbu r2,3(r2) + 101b8bc: 10803fcc andi r2,r2,255 + 101b8c0: 1004c03a cmpne r2,r2,zero + 101b8c4: 1000091e bne r2,zero,101b8ec + pevent->OSEventGrp &= ~bity_old; + 101b8c8: e0bffc17 ldw r2,-16(fp) + 101b8cc: 10800283 ldbu r2,10(r2) + 101b8d0: 1007883a mov r3,r2 + 101b8d4: e0bff843 ldbu r2,-31(fp) + 101b8d8: 0084303a nor r2,zero,r2 + 101b8dc: 1884703a and r2,r3,r2 + 101b8e0: 1007883a mov r3,r2 + 101b8e4: e0bffc17 ldw r2,-16(fp) + 101b8e8: 10c00285 stb r3,10(r2) + } + pevent->OSEventGrp |= bity_new; /* Add new task prio to wait list */ + 101b8ec: e0bffc17 ldw r2,-16(fp) + 101b8f0: 10c00283 ldbu r3,10(r2) + 101b8f4: e0bff8c3 ldbu r2,-29(fp) + 101b8f8: 1884b03a or r2,r3,r2 + 101b8fc: 1007883a mov r3,r2 + 101b900: e0bffc17 ldw r2,-16(fp) + 101b904: 10c00285 stb r3,10(r2) + pevent->OSEventTbl[y_new] |= bitx_new; + 101b908: e13ff983 ldbu r4,-26(fp) + 101b90c: e0fff983 ldbu r3,-26(fp) + 101b910: e0bffc17 ldw r2,-16(fp) + 101b914: 1885883a add r2,r3,r2 + 101b918: 10800204 addi r2,r2,8 + 101b91c: 10c000c3 ldbu r3,3(r2) + 101b920: e0bff883 ldbu r2,-30(fp) + 101b924: 1884b03a or r2,r3,r2 + 101b928: 1007883a mov r3,r2 + 101b92c: e0bffc17 ldw r2,-16(fp) + 101b930: 2085883a add r2,r4,r2 + 101b934: 10800204 addi r2,r2,8 + 101b938: 10c000c5 stb r3,3(r2) + } +#if (OS_EVENT_MULTI_EN > 0) + if (ptcb->OSTCBEventMultiPtr != (OS_EVENT **)0) { + 101b93c: e0bffa17 ldw r2,-24(fp) + 101b940: 10800817 ldw r2,32(r2) + 101b944: 1005003a cmpeq r2,r2,zero + 101b948: 1000441e bne r2,zero,101ba5c + pevents = ptcb->OSTCBEventMultiPtr; + 101b94c: e0bffa17 ldw r2,-24(fp) + 101b950: 10800817 ldw r2,32(r2) + 101b954: e0bffb15 stw r2,-20(fp) + pevent = *pevents; + 101b958: e0bffb17 ldw r2,-20(fp) + 101b95c: 10800017 ldw r2,0(r2) + 101b960: e0bffc15 stw r2,-16(fp) + while (pevent != (OS_EVENT *)0) { + 101b964: 00003a06 br 101ba50 + pevent->OSEventTbl[y_old] &= ~bitx_old; /* Remove old task prio from wait lists */ + 101b968: e13ff903 ldbu r4,-28(fp) + 101b96c: e0fff903 ldbu r3,-28(fp) + 101b970: e0bffc17 ldw r2,-16(fp) + 101b974: 1885883a add r2,r3,r2 + 101b978: 10800204 addi r2,r2,8 + 101b97c: 108000c3 ldbu r2,3(r2) + 101b980: 1007883a mov r3,r2 + 101b984: e0bff803 ldbu r2,-32(fp) + 101b988: 0084303a nor r2,zero,r2 + 101b98c: 1884703a and r2,r3,r2 + 101b990: 1007883a mov r3,r2 + 101b994: e0bffc17 ldw r2,-16(fp) + 101b998: 2085883a add r2,r4,r2 + 101b99c: 10800204 addi r2,r2,8 + 101b9a0: 10c000c5 stb r3,3(r2) + if (pevent->OSEventTbl[y_old] == 0) { + 101b9a4: e0fff903 ldbu r3,-28(fp) + 101b9a8: e0bffc17 ldw r2,-16(fp) + 101b9ac: 1885883a add r2,r3,r2 + 101b9b0: 10800204 addi r2,r2,8 + 101b9b4: 108000c3 ldbu r2,3(r2) + 101b9b8: 10803fcc andi r2,r2,255 + 101b9bc: 1004c03a cmpne r2,r2,zero + 101b9c0: 1000091e bne r2,zero,101b9e8 + pevent->OSEventGrp &= ~bity_old; + 101b9c4: e0bffc17 ldw r2,-16(fp) + 101b9c8: 10800283 ldbu r2,10(r2) + 101b9cc: 1007883a mov r3,r2 + 101b9d0: e0bff843 ldbu r2,-31(fp) + 101b9d4: 0084303a nor r2,zero,r2 + 101b9d8: 1884703a and r2,r3,r2 + 101b9dc: 1007883a mov r3,r2 + 101b9e0: e0bffc17 ldw r2,-16(fp) + 101b9e4: 10c00285 stb r3,10(r2) + } + pevent->OSEventGrp |= bity_new; /* Add new task prio to wait lists */ + 101b9e8: e0bffc17 ldw r2,-16(fp) + 101b9ec: 10c00283 ldbu r3,10(r2) + 101b9f0: e0bff8c3 ldbu r2,-29(fp) + 101b9f4: 1884b03a or r2,r3,r2 + 101b9f8: 1007883a mov r3,r2 + 101b9fc: e0bffc17 ldw r2,-16(fp) + 101ba00: 10c00285 stb r3,10(r2) + pevent->OSEventTbl[y_new] |= bitx_new; + 101ba04: e13ff983 ldbu r4,-26(fp) + 101ba08: e0fff983 ldbu r3,-26(fp) + 101ba0c: e0bffc17 ldw r2,-16(fp) + 101ba10: 1885883a add r2,r3,r2 + 101ba14: 10800204 addi r2,r2,8 + 101ba18: 10c000c3 ldbu r3,3(r2) + 101ba1c: e0bff883 ldbu r2,-30(fp) + 101ba20: 1884b03a or r2,r3,r2 + 101ba24: 1007883a mov r3,r2 + 101ba28: e0bffc17 ldw r2,-16(fp) + 101ba2c: 2085883a add r2,r4,r2 + 101ba30: 10800204 addi r2,r2,8 + 101ba34: 10c000c5 stb r3,3(r2) + pevents++; + 101ba38: e0bffb17 ldw r2,-20(fp) + 101ba3c: 10800104 addi r2,r2,4 + 101ba40: e0bffb15 stw r2,-20(fp) + pevent = *pevents; + 101ba44: e0bffb17 ldw r2,-20(fp) + 101ba48: 10800017 ldw r2,0(r2) + 101ba4c: e0bffc15 stw r2,-16(fp) + } +#if (OS_EVENT_MULTI_EN > 0) + if (ptcb->OSTCBEventMultiPtr != (OS_EVENT **)0) { + pevents = ptcb->OSTCBEventMultiPtr; + pevent = *pevents; + while (pevent != (OS_EVENT *)0) { + 101ba50: e0bffc17 ldw r2,-16(fp) + 101ba54: 1004c03a cmpne r2,r2,zero + 101ba58: 103fc31e bne r2,zero,101b968 + } + } +#endif +#endif + + ptcb->OSTCBPrio = newprio; /* Set new task priority */ + 101ba5c: e0fffa17 ldw r3,-24(fp) + 101ba60: e0bffe03 ldbu r2,-8(fp) + 101ba64: 18800c85 stb r2,50(r3) + ptcb->OSTCBY = y_new; + 101ba68: e0fffa17 ldw r3,-24(fp) + 101ba6c: e0bff983 ldbu r2,-26(fp) + 101ba70: 18800d05 stb r2,52(r3) + ptcb->OSTCBX = x_new; + 101ba74: e0fffa17 ldw r3,-24(fp) + 101ba78: e0bff943 ldbu r2,-27(fp) + 101ba7c: 18800cc5 stb r2,51(r3) + ptcb->OSTCBBitY = bity_new; + 101ba80: e0fffa17 ldw r3,-24(fp) + 101ba84: e0bff8c3 ldbu r2,-29(fp) + 101ba88: 18800d85 stb r2,54(r3) + ptcb->OSTCBBitX = bitx_new; + 101ba8c: e0fffa17 ldw r3,-24(fp) + 101ba90: e0bff883 ldbu r2,-30(fp) + 101ba94: 18800d45 stb r2,53(r3) + 101ba98: e0bff717 ldw r2,-36(fp) + 101ba9c: e0bff215 stw r2,-56(fp) + 101baa0: e0bff217 ldw r2,-56(fp) + 101baa4: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + if (OSRunning == OS_TRUE) { + 101baa8: 008040b4 movhi r2,258 + 101baac: 10951444 addi r2,r2,21585 + 101bab0: 10800003 ldbu r2,0(r2) + 101bab4: 10803fcc andi r2,r2,255 + 101bab8: 10800058 cmpnei r2,r2,1 + 101babc: 1000011e bne r2,zero,101bac4 + OS_Sched(); /* Find new highest priority task */ + 101bac0: 1016cb80 call 1016cb8 + } + return (OS_ERR_NONE); + 101bac4: e03fff15 stw zero,-4(fp) + 101bac8: e0bfff17 ldw r2,-4(fp) +} + 101bacc: e037883a mov sp,fp + 101bad0: dfc00117 ldw ra,4(sp) + 101bad4: df000017 ldw fp,0(sp) + 101bad8: dec00204 addi sp,sp,8 + 101badc: f800283a ret + +0101bae0 : +********************************************************************************************************* +*/ + +#if OS_TASK_CREATE_EN > 0 +INT8U OSTaskCreate (void (*task)(void *p_arg), void *p_arg, OS_STK *ptos, INT8U prio) +{ + 101bae0: deffed04 addi sp,sp,-76 + 101bae4: dfc01215 stw ra,72(sp) + 101bae8: df001115 stw fp,68(sp) + 101baec: df001104 addi fp,sp,68 + 101baf0: e13ffb15 stw r4,-20(fp) + 101baf4: e17ffc15 stw r5,-16(fp) + 101baf8: e1bffd15 stw r6,-12(fp) + 101bafc: e1fffe05 stb r7,-8(fp) + OS_STK *psp; + INT8U err; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 101bb00: e03ff815 stw zero,-32(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (prio > OS_LOWEST_PRIO) { /* Make sure priority is within allowable range */ + 101bb04: e0bffe03 ldbu r2,-8(fp) + 101bb08: 10800570 cmpltui r2,r2,21 + 101bb0c: 1000031e bne r2,zero,101bb1c + return (OS_ERR_PRIO_INVALID); + 101bb10: 00800a84 movi r2,42 + 101bb14: e0bfff15 stw r2,-4(fp) + 101bb18: 00006006 br 101bc9c +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 101bb1c: 0005303a rdctl r2,status + 101bb20: e0bff715 stw r2,-36(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 101bb24: e0fff717 ldw r3,-36(fp) + 101bb28: 00bfff84 movi r2,-2 + 101bb2c: 1884703a and r2,r3,r2 + 101bb30: 1001703a wrctl status,r2 + + return context; + 101bb34: e0bff717 ldw r2,-36(fp) + } +#endif + OS_ENTER_CRITICAL(); + 101bb38: e0bff815 stw r2,-32(fp) + if (OSIntNesting > 0) { /* Make sure we don't create the task from within an ISR */ + 101bb3c: 008040b4 movhi r2,258 + 101bb40: 10952204 addi r2,r2,21640 + 101bb44: 10800003 ldbu r2,0(r2) + 101bb48: 10803fcc andi r2,r2,255 + 101bb4c: 1005003a cmpeq r2,r2,zero + 101bb50: 1000071e bne r2,zero,101bb70 + 101bb54: e0bff817 ldw r2,-32(fp) + 101bb58: e0bff615 stw r2,-40(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 101bb5c: e0bff617 ldw r2,-40(fp) + 101bb60: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_CREATE_ISR); + 101bb64: 00800f04 movi r2,60 + 101bb68: e0bfff15 stw r2,-4(fp) + 101bb6c: 00004b06 br 101bc9c + } + if (OSTCBPrioTbl[prio] == (OS_TCB *)0) { /* Make sure task doesn't already exist at this priority */ + 101bb70: e0bffe03 ldbu r2,-8(fp) + 101bb74: 00c040f4 movhi r3,259 + 101bb78: 18f3b104 addi r3,r3,-12604 + 101bb7c: 1085883a add r2,r2,r2 + 101bb80: 1085883a add r2,r2,r2 + 101bb84: 10c5883a add r2,r2,r3 + 101bb88: 10800017 ldw r2,0(r2) + 101bb8c: 1004c03a cmpne r2,r2,zero + 101bb90: 10003c1e bne r2,zero,101bc84 + OSTCBPrioTbl[prio] = OS_TCB_RESERVED;/* Reserve the priority to prevent others from doing ... */ + 101bb94: e0bffe03 ldbu r2,-8(fp) + 101bb98: 00c040f4 movhi r3,259 + 101bb9c: 18f3b104 addi r3,r3,-12604 + 101bba0: 1085883a add r2,r2,r2 + 101bba4: 1085883a add r2,r2,r2 + 101bba8: 10c7883a add r3,r2,r3 + 101bbac: 00800044 movi r2,1 + 101bbb0: 18800015 stw r2,0(r3) + 101bbb4: e0bff817 ldw r2,-32(fp) + 101bbb8: e0bff515 stw r2,-44(fp) + 101bbbc: e0bff517 ldw r2,-44(fp) + 101bbc0: 1001703a wrctl status,r2 + /* ... the same thing until task is created. */ + OS_EXIT_CRITICAL(); + psp = OSTaskStkInit(task, p_arg, ptos, 0); /* Initialize the task's stack */ + 101bbc4: e13ffb17 ldw r4,-20(fp) + 101bbc8: e17ffc17 ldw r5,-16(fp) + 101bbcc: e1bffd17 ldw r6,-12(fp) + 101bbd0: 000f883a mov r7,zero + 101bbd4: 10200dc0 call 10200dc + 101bbd8: e0bffa15 stw r2,-24(fp) + err = OS_TCBInit(prio, psp, (OS_STK *)0, 0, 0, (void *)0, 0); + 101bbdc: e13ffe03 ldbu r4,-8(fp) + 101bbe0: d8000015 stw zero,0(sp) + 101bbe4: d8000115 stw zero,4(sp) + 101bbe8: d8000215 stw zero,8(sp) + 101bbec: e17ffa17 ldw r5,-24(fp) + 101bbf0: 000d883a mov r6,zero + 101bbf4: 000f883a mov r7,zero + 101bbf8: 10170c00 call 10170c0 + 101bbfc: e0bff905 stb r2,-28(fp) + if (err == OS_ERR_NONE) { + 101bc00: e0bff903 ldbu r2,-28(fp) + 101bc04: 1004c03a cmpne r2,r2,zero + 101bc08: 1000081e bne r2,zero,101bc2c + if (OSRunning == OS_TRUE) { /* Find highest priority task if multitasking has started */ + 101bc0c: 008040b4 movhi r2,258 + 101bc10: 10951444 addi r2,r2,21585 + 101bc14: 10800003 ldbu r2,0(r2) + 101bc18: 10803fcc andi r2,r2,255 + 101bc1c: 10800058 cmpnei r2,r2,1 + 101bc20: 1000151e bne r2,zero,101bc78 + OS_Sched(); + 101bc24: 1016cb80 call 1016cb8 + 101bc28: 00001306 br 101bc78 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 101bc2c: 0005303a rdctl r2,status + 101bc30: e0bff415 stw r2,-48(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 101bc34: e0fff417 ldw r3,-48(fp) + 101bc38: 00bfff84 movi r2,-2 + 101bc3c: 1884703a and r2,r3,r2 + 101bc40: 1001703a wrctl status,r2 + + return context; + 101bc44: e0bff417 ldw r2,-48(fp) + } + } else { + OS_ENTER_CRITICAL(); + 101bc48: e0bff815 stw r2,-32(fp) + OSTCBPrioTbl[prio] = (OS_TCB *)0;/* Make this priority available to others */ + 101bc4c: e0bffe03 ldbu r2,-8(fp) + 101bc50: 00c040f4 movhi r3,259 + 101bc54: 18f3b104 addi r3,r3,-12604 + 101bc58: 1085883a add r2,r2,r2 + 101bc5c: 1085883a add r2,r2,r2 + 101bc60: 10c5883a add r2,r2,r3 + 101bc64: 10000015 stw zero,0(r2) + 101bc68: e0bff817 ldw r2,-32(fp) + 101bc6c: e0bff315 stw r2,-52(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 101bc70: e0bff317 ldw r2,-52(fp) + 101bc74: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + } + return (err); + 101bc78: e0bff903 ldbu r2,-28(fp) + 101bc7c: e0bfff15 stw r2,-4(fp) + 101bc80: 00000606 br 101bc9c + 101bc84: e0bff817 ldw r2,-32(fp) + 101bc88: e0bff215 stw r2,-56(fp) + 101bc8c: e0bff217 ldw r2,-56(fp) + 101bc90: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); + return (OS_ERR_PRIO_EXIST); + 101bc94: 00800a04 movi r2,40 + 101bc98: e0bfff15 stw r2,-4(fp) + 101bc9c: e0bfff17 ldw r2,-4(fp) +} + 101bca0: e037883a mov sp,fp + 101bca4: dfc00117 ldw ra,4(sp) + 101bca8: df000017 ldw fp,0(sp) + 101bcac: dec00204 addi sp,sp,8 + 101bcb0: f800283a ret + +0101bcb4 : + INT16U id, + OS_STK *pbos, + INT32U stk_size, + void *pext, + INT16U opt) +{ + 101bcb4: deffeb04 addi sp,sp,-84 + 101bcb8: dfc01415 stw ra,80(sp) + 101bcbc: df001315 stw fp,76(sp) + 101bcc0: df001304 addi fp,sp,76 + 101bcc4: e13ff915 stw r4,-28(fp) + 101bcc8: e17ffa15 stw r5,-24(fp) + 101bccc: e1bffb15 stw r6,-20(fp) + 101bcd0: e0800217 ldw r2,8(fp) + 101bcd4: e0c00617 ldw r3,24(fp) + 101bcd8: e1fffc05 stb r7,-16(fp) + 101bcdc: e0bffd0d sth r2,-12(fp) + 101bce0: e0fffe0d sth r3,-8(fp) + OS_STK *psp; + INT8U err; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 101bce4: e03ff615 stw zero,-40(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (prio > OS_LOWEST_PRIO) { /* Make sure priority is within allowable range */ + 101bce8: e0bffc03 ldbu r2,-16(fp) + 101bcec: 10800570 cmpltui r2,r2,21 + 101bcf0: 1000031e bne r2,zero,101bd00 + return (OS_ERR_PRIO_INVALID); + 101bcf4: 00800a84 movi r2,42 + 101bcf8: e0bfff15 stw r2,-4(fp) + 101bcfc: 00006706 br 101be9c +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 101bd00: 0005303a rdctl r2,status + 101bd04: e0bff515 stw r2,-44(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 101bd08: e0fff517 ldw r3,-44(fp) + 101bd0c: 00bfff84 movi r2,-2 + 101bd10: 1884703a and r2,r3,r2 + 101bd14: 1001703a wrctl status,r2 + + return context; + 101bd18: e0bff517 ldw r2,-44(fp) + } +#endif + OS_ENTER_CRITICAL(); + 101bd1c: e0bff615 stw r2,-40(fp) + if (OSIntNesting > 0) { /* Make sure we don't create the task from within an ISR */ + 101bd20: 008040b4 movhi r2,258 + 101bd24: 10952204 addi r2,r2,21640 + 101bd28: 10800003 ldbu r2,0(r2) + 101bd2c: 10803fcc andi r2,r2,255 + 101bd30: 1005003a cmpeq r2,r2,zero + 101bd34: 1000071e bne r2,zero,101bd54 + 101bd38: e0bff617 ldw r2,-40(fp) + 101bd3c: e0bff415 stw r2,-48(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 101bd40: e0bff417 ldw r2,-48(fp) + 101bd44: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_CREATE_ISR); + 101bd48: 00800f04 movi r2,60 + 101bd4c: e0bfff15 stw r2,-4(fp) + 101bd50: 00005206 br 101be9c + } + if (OSTCBPrioTbl[prio] == (OS_TCB *)0) { /* Make sure task doesn't already exist at this priority */ + 101bd54: e0bffc03 ldbu r2,-16(fp) + 101bd58: 00c040f4 movhi r3,259 + 101bd5c: 18f3b104 addi r3,r3,-12604 + 101bd60: 1085883a add r2,r2,r2 + 101bd64: 1085883a add r2,r2,r2 + 101bd68: 10c5883a add r2,r2,r3 + 101bd6c: 10800017 ldw r2,0(r2) + 101bd70: 1004c03a cmpne r2,r2,zero + 101bd74: 1000431e bne r2,zero,101be84 + OSTCBPrioTbl[prio] = OS_TCB_RESERVED;/* Reserve the priority to prevent others from doing ... */ + 101bd78: e0bffc03 ldbu r2,-16(fp) + 101bd7c: 00c040f4 movhi r3,259 + 101bd80: 18f3b104 addi r3,r3,-12604 + 101bd84: 1085883a add r2,r2,r2 + 101bd88: 1085883a add r2,r2,r2 + 101bd8c: 10c7883a add r3,r2,r3 + 101bd90: 00800044 movi r2,1 + 101bd94: 18800015 stw r2,0(r3) + 101bd98: e0bff617 ldw r2,-40(fp) + 101bd9c: e0bff315 stw r2,-52(fp) + 101bda0: e0bff317 ldw r2,-52(fp) + 101bda4: 1001703a wrctl status,r2 + /* ... the same thing until task is created. */ + OS_EXIT_CRITICAL(); + +#if (OS_TASK_STAT_STK_CHK_EN > 0) + OS_TaskStkClr(pbos, stk_size, opt); /* Clear the task stack (if needed) */ + 101bda8: e1bffe0b ldhu r6,-8(fp) + 101bdac: e1000317 ldw r4,12(fp) + 101bdb0: e1400417 ldw r5,16(fp) + 101bdb4: 101cf300 call 101cf30 +#endif + + psp = OSTaskStkInit(task, p_arg, ptos, opt); /* Initialize the task's stack */ + 101bdb8: e1fffe0b ldhu r7,-8(fp) + 101bdbc: e13ff917 ldw r4,-28(fp) + 101bdc0: e17ffa17 ldw r5,-24(fp) + 101bdc4: e1bffb17 ldw r6,-20(fp) + 101bdc8: 10200dc0 call 10200dc + 101bdcc: e0bff815 stw r2,-32(fp) + err = OS_TCBInit(prio, psp, pbos, id, stk_size, pext, opt); + 101bdd0: e13ffc03 ldbu r4,-16(fp) + 101bdd4: e1fffd0b ldhu r7,-12(fp) + 101bdd8: e0fffe0b ldhu r3,-8(fp) + 101bddc: e0800417 ldw r2,16(fp) + 101bde0: d8800015 stw r2,0(sp) + 101bde4: e0800517 ldw r2,20(fp) + 101bde8: d8800115 stw r2,4(sp) + 101bdec: d8c00215 stw r3,8(sp) + 101bdf0: e17ff817 ldw r5,-32(fp) + 101bdf4: e1800317 ldw r6,12(fp) + 101bdf8: 10170c00 call 10170c0 + 101bdfc: e0bff705 stb r2,-36(fp) + if (err == OS_ERR_NONE) { + 101be00: e0bff703 ldbu r2,-36(fp) + 101be04: 1004c03a cmpne r2,r2,zero + 101be08: 1000081e bne r2,zero,101be2c + if (OSRunning == OS_TRUE) { /* Find HPT if multitasking has started */ + 101be0c: 008040b4 movhi r2,258 + 101be10: 10951444 addi r2,r2,21585 + 101be14: 10800003 ldbu r2,0(r2) + 101be18: 10803fcc andi r2,r2,255 + 101be1c: 10800058 cmpnei r2,r2,1 + 101be20: 1000151e bne r2,zero,101be78 + OS_Sched(); + 101be24: 1016cb80 call 1016cb8 + 101be28: 00001306 br 101be78 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 101be2c: 0005303a rdctl r2,status + 101be30: e0bff215 stw r2,-56(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 101be34: e0fff217 ldw r3,-56(fp) + 101be38: 00bfff84 movi r2,-2 + 101be3c: 1884703a and r2,r3,r2 + 101be40: 1001703a wrctl status,r2 + + return context; + 101be44: e0bff217 ldw r2,-56(fp) + } + } else { + OS_ENTER_CRITICAL(); + 101be48: e0bff615 stw r2,-40(fp) + OSTCBPrioTbl[prio] = (OS_TCB *)0; /* Make this priority avail. to others */ + 101be4c: e0bffc03 ldbu r2,-16(fp) + 101be50: 00c040f4 movhi r3,259 + 101be54: 18f3b104 addi r3,r3,-12604 + 101be58: 1085883a add r2,r2,r2 + 101be5c: 1085883a add r2,r2,r2 + 101be60: 10c5883a add r2,r2,r3 + 101be64: 10000015 stw zero,0(r2) + 101be68: e0bff617 ldw r2,-40(fp) + 101be6c: e0bff115 stw r2,-60(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 101be70: e0bff117 ldw r2,-60(fp) + 101be74: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + } + return (err); + 101be78: e0bff703 ldbu r2,-36(fp) + 101be7c: e0bfff15 stw r2,-4(fp) + 101be80: 00000606 br 101be9c + 101be84: e0bff617 ldw r2,-40(fp) + 101be88: e0bff015 stw r2,-64(fp) + 101be8c: e0bff017 ldw r2,-64(fp) + 101be90: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); + return (OS_ERR_PRIO_EXIST); + 101be94: 00800a04 movi r2,40 + 101be98: e0bfff15 stw r2,-4(fp) + 101be9c: e0bfff17 ldw r2,-4(fp) +} + 101bea0: e037883a mov sp,fp + 101bea4: dfc00117 ldw ra,4(sp) + 101bea8: df000017 ldw fp,0(sp) + 101beac: dec00204 addi sp,sp,8 + 101beb0: f800283a ret + +0101beb4 : +********************************************************************************************************* +*/ + +#if OS_TASK_DEL_EN > 0 +INT8U OSTaskDel (INT8U prio) +{ + 101beb4: defff304 addi sp,sp,-52 + 101beb8: dfc00c15 stw ra,48(sp) + 101bebc: df000b15 stw fp,44(sp) + 101bec0: df000b04 addi fp,sp,44 + 101bec4: e13ffe05 stb r4,-8(fp) +#if (OS_FLAG_EN > 0) && (OS_MAX_FLAGS > 0) + OS_FLAG_NODE *pnode; +#endif + OS_TCB *ptcb; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 101bec8: e03ffb15 stw zero,-20(fp) +#endif + + + + if (OSIntNesting > 0) { /* See if trying to delete from ISR */ + 101becc: 008040b4 movhi r2,258 + 101bed0: 10952204 addi r2,r2,21640 + 101bed4: 10800003 ldbu r2,0(r2) + 101bed8: 10803fcc andi r2,r2,255 + 101bedc: 1005003a cmpeq r2,r2,zero + 101bee0: 1000031e bne r2,zero,101bef0 + return (OS_ERR_TASK_DEL_ISR); + 101bee4: 00801004 movi r2,64 + 101bee8: e0bfff15 stw r2,-4(fp) + 101beec: 0000ee06 br 101c2a8 + } + if (prio == OS_TASK_IDLE_PRIO) { /* Not allowed to delete idle task */ + 101bef0: e0bffe03 ldbu r2,-8(fp) + 101bef4: 10800518 cmpnei r2,r2,20 + 101bef8: 1000031e bne r2,zero,101bf08 + return (OS_ERR_TASK_DEL_IDLE); + 101befc: 00800f84 movi r2,62 + 101bf00: e0bfff15 stw r2,-4(fp) + 101bf04: 0000e806 br 101c2a8 + } +#if OS_ARG_CHK_EN > 0 + if (prio >= OS_LOWEST_PRIO) { /* Task priority valid ? */ + 101bf08: e0bffe03 ldbu r2,-8(fp) + 101bf0c: 10800530 cmpltui r2,r2,20 + 101bf10: 1000061e bne r2,zero,101bf2c + if (prio != OS_PRIO_SELF) { + 101bf14: e0bffe03 ldbu r2,-8(fp) + 101bf18: 10803fe0 cmpeqi r2,r2,255 + 101bf1c: 1000031e bne r2,zero,101bf2c + return (OS_ERR_PRIO_INVALID); + 101bf20: 00800a84 movi r2,42 + 101bf24: e0bfff15 stw r2,-4(fp) + 101bf28: 0000df06 br 101c2a8 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 101bf2c: 0005303a rdctl r2,status + 101bf30: e0bffa15 stw r2,-24(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 101bf34: e0fffa17 ldw r3,-24(fp) + 101bf38: 00bfff84 movi r2,-2 + 101bf3c: 1884703a and r2,r3,r2 + 101bf40: 1001703a wrctl status,r2 + + return context; + 101bf44: e0bffa17 ldw r2,-24(fp) + } + } +#endif + +/*$PAGE*/ + OS_ENTER_CRITICAL(); + 101bf48: e0bffb15 stw r2,-20(fp) + if (prio == OS_PRIO_SELF) { /* See if requesting to delete self */ + 101bf4c: e0bffe03 ldbu r2,-8(fp) + 101bf50: 10803fd8 cmpnei r2,r2,255 + 101bf54: 1000051e bne r2,zero,101bf6c + prio = OSTCBCur->OSTCBPrio; /* Set priority to delete to current */ + 101bf58: 008040b4 movhi r2,258 + 101bf5c: 10952304 addi r2,r2,21644 + 101bf60: 10800017 ldw r2,0(r2) + 101bf64: 10800c83 ldbu r2,50(r2) + 101bf68: e0bffe05 stb r2,-8(fp) + } + ptcb = OSTCBPrioTbl[prio]; + 101bf6c: e0bffe03 ldbu r2,-8(fp) + 101bf70: 00c040f4 movhi r3,259 + 101bf74: 18f3b104 addi r3,r3,-12604 + 101bf78: 1085883a add r2,r2,r2 + 101bf7c: 1085883a add r2,r2,r2 + 101bf80: 10c5883a add r2,r2,r3 + 101bf84: 10800017 ldw r2,0(r2) + 101bf88: e0bffc15 stw r2,-16(fp) + if (ptcb == (OS_TCB *)0) { /* Task to delete must exist */ + 101bf8c: e0bffc17 ldw r2,-16(fp) + 101bf90: 1004c03a cmpne r2,r2,zero + 101bf94: 1000071e bne r2,zero,101bfb4 + 101bf98: e0bffb17 ldw r2,-20(fp) + 101bf9c: e0bff915 stw r2,-28(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 101bfa0: e0bff917 ldw r2,-28(fp) + 101bfa4: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_NOT_EXIST); + 101bfa8: 008010c4 movi r2,67 + 101bfac: e0bfff15 stw r2,-4(fp) + 101bfb0: 0000bd06 br 101c2a8 + } + if (ptcb == OS_TCB_RESERVED) { /* Must not be assigned to Mutex */ + 101bfb4: e0bffc17 ldw r2,-16(fp) + 101bfb8: 10800058 cmpnei r2,r2,1 + 101bfbc: 1000071e bne r2,zero,101bfdc + 101bfc0: e0bffb17 ldw r2,-20(fp) + 101bfc4: e0bff815 stw r2,-32(fp) + 101bfc8: e0bff817 ldw r2,-32(fp) + 101bfcc: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_DEL); + 101bfd0: 00800f44 movi r2,61 + 101bfd4: e0bfff15 stw r2,-4(fp) + 101bfd8: 0000b306 br 101c2a8 + } + + OSRdyTbl[ptcb->OSTCBY] &= ~ptcb->OSTCBBitX; + 101bfdc: e0bffc17 ldw r2,-16(fp) + 101bfe0: 10800d03 ldbu r2,52(r2) + 101bfe4: 11003fcc andi r4,r2,255 + 101bfe8: e0bffc17 ldw r2,-16(fp) + 101bfec: 10800d03 ldbu r2,52(r2) + 101bff0: 10c03fcc andi r3,r2,255 + 101bff4: 008040b4 movhi r2,258 + 101bff8: 10952044 addi r2,r2,21633 + 101bffc: 10c5883a add r2,r2,r3 + 101c000: 10800003 ldbu r2,0(r2) + 101c004: 1007883a mov r3,r2 + 101c008: e0bffc17 ldw r2,-16(fp) + 101c00c: 10800d43 ldbu r2,53(r2) + 101c010: 0084303a nor r2,zero,r2 + 101c014: 1884703a and r2,r3,r2 + 101c018: 1007883a mov r3,r2 + 101c01c: 008040b4 movhi r2,258 + 101c020: 10952044 addi r2,r2,21633 + 101c024: 1105883a add r2,r2,r4 + 101c028: 10c00005 stb r3,0(r2) + if (OSRdyTbl[ptcb->OSTCBY] == 0) { /* Make task not ready */ + 101c02c: e0bffc17 ldw r2,-16(fp) + 101c030: 10800d03 ldbu r2,52(r2) + 101c034: 10c03fcc andi r3,r2,255 + 101c038: 008040b4 movhi r2,258 + 101c03c: 10952044 addi r2,r2,21633 + 101c040: 10c5883a add r2,r2,r3 + 101c044: 10800003 ldbu r2,0(r2) + 101c048: 10803fcc andi r2,r2,255 + 101c04c: 1004c03a cmpne r2,r2,zero + 101c050: 10000c1e bne r2,zero,101c084 + OSRdyGrp &= ~ptcb->OSTCBBitY; + 101c054: e0bffc17 ldw r2,-16(fp) + 101c058: 10800d83 ldbu r2,54(r2) + 101c05c: 0084303a nor r2,zero,r2 + 101c060: 1007883a mov r3,r2 + 101c064: 008040b4 movhi r2,258 + 101c068: 10952004 addi r2,r2,21632 + 101c06c: 10800003 ldbu r2,0(r2) + 101c070: 1884703a and r2,r3,r2 + 101c074: 1007883a mov r3,r2 + 101c078: 008040b4 movhi r2,258 + 101c07c: 10952004 addi r2,r2,21632 + 101c080: 10c00005 stb r3,0(r2) + } + +#if (OS_EVENT_EN) + if (ptcb->OSTCBEventPtr != (OS_EVENT *)0) { + 101c084: e0bffc17 ldw r2,-16(fp) + 101c088: 10800717 ldw r2,28(r2) + 101c08c: 1005003a cmpeq r2,r2,zero + 101c090: 1000041e bne r2,zero,101c0a4 + OS_EventTaskRemove(ptcb, ptcb->OSTCBEventPtr); /* Remove this task from any event wait list */ + 101c094: e0bffc17 ldw r2,-16(fp) + 101c098: 11400717 ldw r5,28(r2) + 101c09c: e13ffc17 ldw r4,-16(fp) + 101c0a0: 10166700 call 1016670 + } +#if (OS_EVENT_MULTI_EN > 0) + if (ptcb->OSTCBEventMultiPtr != (OS_EVENT **)0) { /* Remove this task from any events' wait lists*/ + 101c0a4: e0bffc17 ldw r2,-16(fp) + 101c0a8: 10800817 ldw r2,32(r2) + 101c0ac: 1005003a cmpeq r2,r2,zero + 101c0b0: 1000041e bne r2,zero,101c0c4 + OS_EventTaskRemoveMulti(ptcb, ptcb->OSTCBEventMultiPtr); + 101c0b4: e0bffc17 ldw r2,-16(fp) + 101c0b8: 11400817 ldw r5,32(r2) + 101c0bc: e13ffc17 ldw r4,-16(fp) + 101c0c0: 10167280 call 1016728 + } +#endif +#endif + +#if (OS_FLAG_EN > 0) && (OS_MAX_FLAGS > 0) + pnode = ptcb->OSTCBFlagNode; + 101c0c4: e0bffc17 ldw r2,-16(fp) + 101c0c8: 10800a17 ldw r2,40(r2) + 101c0cc: e0bffd15 stw r2,-12(fp) + if (pnode != (OS_FLAG_NODE *)0) { /* If task is waiting on event flag */ + 101c0d0: e0bffd17 ldw r2,-12(fp) + 101c0d4: 1005003a cmpeq r2,r2,zero + 101c0d8: 1000021e bne r2,zero,101c0e4 + OS_FlagUnlink(pnode); /* Remove from wait list */ + 101c0dc: e13ffd17 ldw r4,-12(fp) + 101c0e0: 1018dbc0 call 1018dbc + } +#endif + + ptcb->OSTCBDly = 0; /* Prevent OSTimeTick() from updating */ + 101c0e4: e0bffc17 ldw r2,-16(fp) + 101c0e8: 10000b8d sth zero,46(r2) + ptcb->OSTCBStat = OS_STAT_RDY; /* Prevent task from being resumed */ + 101c0ec: e0bffc17 ldw r2,-16(fp) + 101c0f0: 10000c05 stb zero,48(r2) + ptcb->OSTCBStatPend = OS_STAT_PEND_OK; + 101c0f4: e0bffc17 ldw r2,-16(fp) + 101c0f8: 10000c45 stb zero,49(r2) + if (OSLockNesting < 255u) { /* Make sure we don't context switch */ + 101c0fc: 008040b4 movhi r2,258 + 101c100: 10951404 addi r2,r2,21584 + 101c104: 10800003 ldbu r2,0(r2) + 101c108: 10803fcc andi r2,r2,255 + 101c10c: 10803fe0 cmpeqi r2,r2,255 + 101c110: 1000081e bne r2,zero,101c134 + OSLockNesting++; + 101c114: 008040b4 movhi r2,258 + 101c118: 10951404 addi r2,r2,21584 + 101c11c: 10800003 ldbu r2,0(r2) + 101c120: 10800044 addi r2,r2,1 + 101c124: 1007883a mov r3,r2 + 101c128: 008040b4 movhi r2,258 + 101c12c: 10951404 addi r2,r2,21584 + 101c130: 10c00005 stb r3,0(r2) + 101c134: e0bffb17 ldw r2,-20(fp) + 101c138: e0bff715 stw r2,-36(fp) + 101c13c: e0bff717 ldw r2,-36(fp) + 101c140: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); /* Enabling INT. ignores next instruc. */ + OS_Dummy(); /* ... Dummy ensures that INTs will be */ + 101c144: 101625c0 call 101625c +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 101c148: 0005303a rdctl r2,status + 101c14c: e0bff615 stw r2,-40(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 101c150: e0fff617 ldw r3,-40(fp) + 101c154: 00bfff84 movi r2,-2 + 101c158: 1884703a and r2,r3,r2 + 101c15c: 1001703a wrctl status,r2 + + return context; + 101c160: e0bff617 ldw r2,-40(fp) + OS_ENTER_CRITICAL(); /* ... disabled HERE! */ + 101c164: e0bffb15 stw r2,-20(fp) + if (OSLockNesting > 0) { /* Remove context switch lock */ + 101c168: 008040b4 movhi r2,258 + 101c16c: 10951404 addi r2,r2,21584 + 101c170: 10800003 ldbu r2,0(r2) + 101c174: 10803fcc andi r2,r2,255 + 101c178: 1005003a cmpeq r2,r2,zero + 101c17c: 1000081e bne r2,zero,101c1a0 + OSLockNesting--; + 101c180: 008040b4 movhi r2,258 + 101c184: 10951404 addi r2,r2,21584 + 101c188: 10800003 ldbu r2,0(r2) + 101c18c: 10bfffc4 addi r2,r2,-1 + 101c190: 1007883a mov r3,r2 + 101c194: 008040b4 movhi r2,258 + 101c198: 10951404 addi r2,r2,21584 + 101c19c: 10c00005 stb r3,0(r2) + } + OSTaskDelHook(ptcb); /* Call user defined hook */ + 101c1a0: e13ffc17 ldw r4,-16(fp) + 101c1a4: 102040c0 call 102040c + OSTaskCtr--; /* One less task being managed */ + 101c1a8: 008040b4 movhi r2,258 + 101c1ac: 10951c44 addi r2,r2,21617 + 101c1b0: 10800003 ldbu r2,0(r2) + 101c1b4: 10bfffc4 addi r2,r2,-1 + 101c1b8: 1007883a mov r3,r2 + 101c1bc: 008040b4 movhi r2,258 + 101c1c0: 10951c44 addi r2,r2,21617 + 101c1c4: 10c00005 stb r3,0(r2) + OSTCBPrioTbl[prio] = (OS_TCB *)0; /* Clear old priority entry */ + 101c1c8: e0bffe03 ldbu r2,-8(fp) + 101c1cc: 00c040f4 movhi r3,259 + 101c1d0: 18f3b104 addi r3,r3,-12604 + 101c1d4: 1085883a add r2,r2,r2 + 101c1d8: 1085883a add r2,r2,r2 + 101c1dc: 10c5883a add r2,r2,r3 + 101c1e0: 10000015 stw zero,0(r2) + if (ptcb->OSTCBPrev == (OS_TCB *)0) { /* Remove from TCB chain */ + 101c1e4: e0bffc17 ldw r2,-16(fp) + 101c1e8: 10800617 ldw r2,24(r2) + 101c1ec: 1004c03a cmpne r2,r2,zero + 101c1f0: 1000091e bne r2,zero,101c218 + ptcb->OSTCBNext->OSTCBPrev = (OS_TCB *)0; + 101c1f4: e0bffc17 ldw r2,-16(fp) + 101c1f8: 10800517 ldw r2,20(r2) + 101c1fc: 10000615 stw zero,24(r2) + OSTCBList = ptcb->OSTCBNext; + 101c200: e0bffc17 ldw r2,-16(fp) + 101c204: 10c00517 ldw r3,20(r2) + 101c208: 008040b4 movhi r2,258 + 101c20c: 10951704 addi r2,r2,21596 + 101c210: 10c00015 stw r3,0(r2) + 101c214: 00000a06 br 101c240 + } else { + ptcb->OSTCBPrev->OSTCBNext = ptcb->OSTCBNext; + 101c218: e0bffc17 ldw r2,-16(fp) + 101c21c: 10c00617 ldw r3,24(r2) + 101c220: e0bffc17 ldw r2,-16(fp) + 101c224: 10800517 ldw r2,20(r2) + 101c228: 18800515 stw r2,20(r3) + ptcb->OSTCBNext->OSTCBPrev = ptcb->OSTCBPrev; + 101c22c: e0bffc17 ldw r2,-16(fp) + 101c230: 10c00517 ldw r3,20(r2) + 101c234: e0bffc17 ldw r2,-16(fp) + 101c238: 10800617 ldw r2,24(r2) + 101c23c: 18800615 stw r2,24(r3) + } + ptcb->OSTCBNext = OSTCBFreeList; /* Return TCB to free TCB list */ + 101c240: 008040b4 movhi r2,258 + 101c244: 10951b04 addi r2,r2,21612 + 101c248: 10c00017 ldw r3,0(r2) + 101c24c: e0bffc17 ldw r2,-16(fp) + 101c250: 10c00515 stw r3,20(r2) + OSTCBFreeList = ptcb; + 101c254: 00c040b4 movhi r3,258 + 101c258: 18d51b04 addi r3,r3,21612 + 101c25c: e0bffc17 ldw r2,-16(fp) + 101c260: 18800015 stw r2,0(r3) +#if OS_TASK_NAME_SIZE > 1 + ptcb->OSTCBTaskName[0] = '?'; /* Unknown name */ + 101c264: e0fffc17 ldw r3,-16(fp) + 101c268: 00800fc4 movi r2,63 + 101c26c: 18801305 stb r2,76(r3) + ptcb->OSTCBTaskName[1] = OS_ASCII_NUL; + 101c270: e0bffc17 ldw r2,-16(fp) + 101c274: 10001345 stb zero,77(r2) + 101c278: e0bffb17 ldw r2,-20(fp) + 101c27c: e0bff515 stw r2,-44(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 101c280: e0bff517 ldw r2,-44(fp) + 101c284: 1001703a wrctl status,r2 +#endif + OS_EXIT_CRITICAL(); + if (OSRunning == OS_TRUE) { + 101c288: 008040b4 movhi r2,258 + 101c28c: 10951444 addi r2,r2,21585 + 101c290: 10800003 ldbu r2,0(r2) + 101c294: 10803fcc andi r2,r2,255 + 101c298: 10800058 cmpnei r2,r2,1 + 101c29c: 1000011e bne r2,zero,101c2a4 + OS_Sched(); /* Find new highest priority task */ + 101c2a0: 1016cb80 call 1016cb8 + } + return (OS_ERR_NONE); + 101c2a4: e03fff15 stw zero,-4(fp) + 101c2a8: e0bfff17 ldw r2,-4(fp) +} + 101c2ac: e037883a mov sp,fp + 101c2b0: dfc00117 ldw ra,4(sp) + 101c2b4: df000017 ldw fp,0(sp) + 101c2b8: dec00204 addi sp,sp,8 + 101c2bc: f800283a ret + +0101c2c0 : +********************************************************************************************************* +*/ +/*$PAGE*/ +#if OS_TASK_DEL_EN > 0 +INT8U OSTaskDelReq (INT8U prio) +{ + 101c2c0: defff404 addi sp,sp,-48 + 101c2c4: df000b15 stw fp,44(sp) + 101c2c8: df000b04 addi fp,sp,44 + 101c2cc: e13ffe05 stb r4,-8(fp) + INT8U stat; + OS_TCB *ptcb; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 101c2d0: e03ffb15 stw zero,-20(fp) +#endif + + + + if (prio == OS_TASK_IDLE_PRIO) { /* Not allowed to delete idle task */ + 101c2d4: e0bffe03 ldbu r2,-8(fp) + 101c2d8: 10800518 cmpnei r2,r2,20 + 101c2dc: 1000031e bne r2,zero,101c2ec + return (OS_ERR_TASK_DEL_IDLE); + 101c2e0: 00800f84 movi r2,62 + 101c2e4: e0bfff15 stw r2,-4(fp) + 101c2e8: 00004c06 br 101c41c + } +#if OS_ARG_CHK_EN > 0 + if (prio >= OS_LOWEST_PRIO) { /* Task priority valid ? */ + 101c2ec: e0bffe03 ldbu r2,-8(fp) + 101c2f0: 10800530 cmpltui r2,r2,20 + 101c2f4: 1000061e bne r2,zero,101c310 + if (prio != OS_PRIO_SELF) { + 101c2f8: e0bffe03 ldbu r2,-8(fp) + 101c2fc: 10803fe0 cmpeqi r2,r2,255 + 101c300: 1000031e bne r2,zero,101c310 + return (OS_ERR_PRIO_INVALID); + 101c304: 00800a84 movi r2,42 + 101c308: e0bfff15 stw r2,-4(fp) + 101c30c: 00004306 br 101c41c + } + } +#endif + if (prio == OS_PRIO_SELF) { /* See if a task is requesting to ... */ + 101c310: e0bffe03 ldbu r2,-8(fp) + 101c314: 10803fd8 cmpnei r2,r2,255 + 101c318: 1000141e bne r2,zero,101c36c +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 101c31c: 0005303a rdctl r2,status + 101c320: e0bffa15 stw r2,-24(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 101c324: e0fffa17 ldw r3,-24(fp) + 101c328: 00bfff84 movi r2,-2 + 101c32c: 1884703a and r2,r3,r2 + 101c330: 1001703a wrctl status,r2 + + return context; + 101c334: e0bffa17 ldw r2,-24(fp) + OS_ENTER_CRITICAL(); /* ... this task to delete itself */ + 101c338: e0bffb15 stw r2,-20(fp) + stat = OSTCBCur->OSTCBDelReq; /* Return request status to caller */ + 101c33c: 008040b4 movhi r2,258 + 101c340: 10952304 addi r2,r2,21644 + 101c344: 10800017 ldw r2,0(r2) + 101c348: 10800dc3 ldbu r2,55(r2) + 101c34c: e0bffd05 stb r2,-12(fp) + 101c350: e0bffb17 ldw r2,-20(fp) + 101c354: e0bff915 stw r2,-28(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 101c358: e0bff917 ldw r2,-28(fp) + 101c35c: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (stat); + 101c360: e0bffd03 ldbu r2,-12(fp) + 101c364: e0bfff15 stw r2,-4(fp) + 101c368: 00002c06 br 101c41c +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 101c36c: 0005303a rdctl r2,status + 101c370: e0bff815 stw r2,-32(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 101c374: e0fff817 ldw r3,-32(fp) + 101c378: 00bfff84 movi r2,-2 + 101c37c: 1884703a and r2,r3,r2 + 101c380: 1001703a wrctl status,r2 + + return context; + 101c384: e0bff817 ldw r2,-32(fp) + } + OS_ENTER_CRITICAL(); + 101c388: e0bffb15 stw r2,-20(fp) + ptcb = OSTCBPrioTbl[prio]; + 101c38c: e0bffe03 ldbu r2,-8(fp) + 101c390: 00c040f4 movhi r3,259 + 101c394: 18f3b104 addi r3,r3,-12604 + 101c398: 1085883a add r2,r2,r2 + 101c39c: 1085883a add r2,r2,r2 + 101c3a0: 10c5883a add r2,r2,r3 + 101c3a4: 10800017 ldw r2,0(r2) + 101c3a8: e0bffc15 stw r2,-16(fp) + if (ptcb == (OS_TCB *)0) { /* Task to delete must exist */ + 101c3ac: e0bffc17 ldw r2,-16(fp) + 101c3b0: 1004c03a cmpne r2,r2,zero + 101c3b4: 1000071e bne r2,zero,101c3d4 + 101c3b8: e0bffb17 ldw r2,-20(fp) + 101c3bc: e0bff715 stw r2,-36(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 101c3c0: e0bff717 ldw r2,-36(fp) + 101c3c4: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_NOT_EXIST); /* Task must already be deleted */ + 101c3c8: 008010c4 movi r2,67 + 101c3cc: e0bfff15 stw r2,-4(fp) + 101c3d0: 00001206 br 101c41c + } + if (ptcb == OS_TCB_RESERVED) { /* Must NOT be assigned to a Mutex */ + 101c3d4: e0bffc17 ldw r2,-16(fp) + 101c3d8: 10800058 cmpnei r2,r2,1 + 101c3dc: 1000071e bne r2,zero,101c3fc + 101c3e0: e0bffb17 ldw r2,-20(fp) + 101c3e4: e0bff615 stw r2,-40(fp) + 101c3e8: e0bff617 ldw r2,-40(fp) + 101c3ec: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_DEL); + 101c3f0: 00800f44 movi r2,61 + 101c3f4: e0bfff15 stw r2,-4(fp) + 101c3f8: 00000806 br 101c41c + } + ptcb->OSTCBDelReq = OS_ERR_TASK_DEL_REQ; /* Set flag indicating task to be DEL. */ + 101c3fc: e0fffc17 ldw r3,-16(fp) + 101c400: 00800fc4 movi r2,63 + 101c404: 18800dc5 stb r2,55(r3) + 101c408: e0bffb17 ldw r2,-20(fp) + 101c40c: e0bff515 stw r2,-44(fp) + 101c410: e0bff517 ldw r2,-44(fp) + 101c414: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_NONE); + 101c418: e03fff15 stw zero,-4(fp) + 101c41c: e0bfff17 ldw r2,-4(fp) +} + 101c420: e037883a mov sp,fp + 101c424: df000017 ldw fp,0(sp) + 101c428: dec00104 addi sp,sp,4 + 101c42c: f800283a ret + +0101c430 : +********************************************************************************************************* +*/ + +#if OS_TASK_NAME_SIZE > 1 +INT8U OSTaskNameGet (INT8U prio, INT8U *pname, INT8U *perr) +{ + 101c430: defff304 addi sp,sp,-52 + 101c434: dfc00c15 stw ra,48(sp) + 101c438: df000b15 stw fp,44(sp) + 101c43c: df000b04 addi fp,sp,44 + 101c440: e17ffd15 stw r5,-12(fp) + 101c444: e1bffe15 stw r6,-8(fp) + 101c448: e13ffc05 stb r4,-16(fp) + OS_TCB *ptcb; + INT8U len; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 101c44c: e03ff915 stw zero,-28(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + 101c450: e0bffe17 ldw r2,-8(fp) + 101c454: 1004c03a cmpne r2,r2,zero + 101c458: 1000021e bne r2,zero,101c464 + return (0); + 101c45c: e03fff15 stw zero,-4(fp) + 101c460: 00005b06 br 101c5d0 + } + if (prio > OS_LOWEST_PRIO) { /* Task priority valid ? */ + 101c464: e0bffc03 ldbu r2,-16(fp) + 101c468: 10800570 cmpltui r2,r2,21 + 101c46c: 1000081e bne r2,zero,101c490 + if (prio != OS_PRIO_SELF) { + 101c470: e0bffc03 ldbu r2,-16(fp) + 101c474: 10803fe0 cmpeqi r2,r2,255 + 101c478: 1000051e bne r2,zero,101c490 + *perr = OS_ERR_PRIO_INVALID; /* No */ + 101c47c: e0fffe17 ldw r3,-8(fp) + 101c480: 00800a84 movi r2,42 + 101c484: 18800005 stb r2,0(r3) + return (0); + 101c488: e03fff15 stw zero,-4(fp) + 101c48c: 00005006 br 101c5d0 + } + } + if (pname == (INT8U *)0) { /* Is 'pname' a NULL pointer? */ + 101c490: e0bffd17 ldw r2,-12(fp) + 101c494: 1004c03a cmpne r2,r2,zero + 101c498: 1000051e bne r2,zero,101c4b0 + *perr = OS_ERR_PNAME_NULL; /* Yes */ + 101c49c: e0fffe17 ldw r3,-8(fp) + 101c4a0: 00800304 movi r2,12 + 101c4a4: 18800005 stb r2,0(r3) + return (0); + 101c4a8: e03fff15 stw zero,-4(fp) + 101c4ac: 00004806 br 101c5d0 + } +#endif + if (OSIntNesting > 0) { /* See if trying to call from an ISR */ + 101c4b0: 008040b4 movhi r2,258 + 101c4b4: 10952204 addi r2,r2,21640 + 101c4b8: 10800003 ldbu r2,0(r2) + 101c4bc: 10803fcc andi r2,r2,255 + 101c4c0: 1005003a cmpeq r2,r2,zero + 101c4c4: 1000051e bne r2,zero,101c4dc + *perr = OS_ERR_NAME_GET_ISR; + 101c4c8: e0fffe17 ldw r3,-8(fp) + 101c4cc: 00800444 movi r2,17 + 101c4d0: 18800005 stb r2,0(r3) + return (0); + 101c4d4: e03fff15 stw zero,-4(fp) + 101c4d8: 00003d06 br 101c5d0 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 101c4dc: 0005303a rdctl r2,status + 101c4e0: e0bff815 stw r2,-32(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 101c4e4: e0fff817 ldw r3,-32(fp) + 101c4e8: 00bfff84 movi r2,-2 + 101c4ec: 1884703a and r2,r3,r2 + 101c4f0: 1001703a wrctl status,r2 + + return context; + 101c4f4: e0bff817 ldw r2,-32(fp) + } + OS_ENTER_CRITICAL(); + 101c4f8: e0bff915 stw r2,-28(fp) + if (prio == OS_PRIO_SELF) { /* See if caller desires it's own name */ + 101c4fc: e0bffc03 ldbu r2,-16(fp) + 101c500: 10803fd8 cmpnei r2,r2,255 + 101c504: 1000051e bne r2,zero,101c51c + prio = OSTCBCur->OSTCBPrio; + 101c508: 008040b4 movhi r2,258 + 101c50c: 10952304 addi r2,r2,21644 + 101c510: 10800017 ldw r2,0(r2) + 101c514: 10800c83 ldbu r2,50(r2) + 101c518: e0bffc05 stb r2,-16(fp) + } + ptcb = OSTCBPrioTbl[prio]; + 101c51c: e0bffc03 ldbu r2,-16(fp) + 101c520: 00c040f4 movhi r3,259 + 101c524: 18f3b104 addi r3,r3,-12604 + 101c528: 1085883a add r2,r2,r2 + 101c52c: 1085883a add r2,r2,r2 + 101c530: 10c5883a add r2,r2,r3 + 101c534: 10800017 ldw r2,0(r2) + 101c538: e0bffb15 stw r2,-20(fp) + if (ptcb == (OS_TCB *)0) { /* Does task exist? */ + 101c53c: e0bffb17 ldw r2,-20(fp) + 101c540: 1004c03a cmpne r2,r2,zero + 101c544: 1000091e bne r2,zero,101c56c + 101c548: e0bff917 ldw r2,-28(fp) + 101c54c: e0bff715 stw r2,-36(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 101c550: e0bff717 ldw r2,-36(fp) + 101c554: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); /* No */ + *perr = OS_ERR_TASK_NOT_EXIST; + 101c558: e0fffe17 ldw r3,-8(fp) + 101c55c: 008010c4 movi r2,67 + 101c560: 18800005 stb r2,0(r3) + return (0); + 101c564: e03fff15 stw zero,-4(fp) + 101c568: 00001906 br 101c5d0 + } + if (ptcb == OS_TCB_RESERVED) { /* Task assigned to a Mutex? */ + 101c56c: e0bffb17 ldw r2,-20(fp) + 101c570: 10800058 cmpnei r2,r2,1 + 101c574: 1000091e bne r2,zero,101c59c + 101c578: e0bff917 ldw r2,-28(fp) + 101c57c: e0bff615 stw r2,-40(fp) + 101c580: e0bff617 ldw r2,-40(fp) + 101c584: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); /* Yes */ + *perr = OS_ERR_TASK_NOT_EXIST; + 101c588: e0fffe17 ldw r3,-8(fp) + 101c58c: 008010c4 movi r2,67 + 101c590: 18800005 stb r2,0(r3) + return (0); + 101c594: e03fff15 stw zero,-4(fp) + 101c598: 00000d06 br 101c5d0 + } + len = OS_StrCopy(pname, ptcb->OSTCBTaskName); /* Yes, copy name from TCB */ + 101c59c: e0bffb17 ldw r2,-20(fp) + 101c5a0: 11401304 addi r5,r2,76 + 101c5a4: e13ffd17 ldw r4,-12(fp) + 101c5a8: 1016dfc0 call 1016dfc + 101c5ac: e0bffa05 stb r2,-24(fp) + 101c5b0: e0bff917 ldw r2,-28(fp) + 101c5b4: e0bff515 stw r2,-44(fp) + 101c5b8: e0bff517 ldw r2,-44(fp) + 101c5bc: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + 101c5c0: e0bffe17 ldw r2,-8(fp) + 101c5c4: 10000005 stb zero,0(r2) + return (len); + 101c5c8: e0bffa03 ldbu r2,-24(fp) + 101c5cc: e0bfff15 stw r2,-4(fp) + 101c5d0: e0bfff17 ldw r2,-4(fp) +} + 101c5d4: e037883a mov sp,fp + 101c5d8: dfc00117 ldw ra,4(sp) + 101c5dc: df000017 ldw fp,0(sp) + 101c5e0: dec00204 addi sp,sp,8 + 101c5e4: f800283a ret + +0101c5e8 : +* Returns : None +********************************************************************************************************* +*/ +#if OS_TASK_NAME_SIZE > 1 +void OSTaskNameSet (INT8U prio, INT8U *pname, INT8U *perr) +{ + 101c5e8: defff304 addi sp,sp,-52 + 101c5ec: dfc00c15 stw ra,48(sp) + 101c5f0: df000b15 stw fp,44(sp) + 101c5f4: df000b04 addi fp,sp,44 + 101c5f8: e17ffe15 stw r5,-8(fp) + 101c5fc: e1bfff15 stw r6,-4(fp) + 101c600: e13ffd05 stb r4,-12(fp) + INT8U len; + OS_TCB *ptcb; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 101c604: e03ffa15 stw zero,-24(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + 101c608: e0bfff17 ldw r2,-4(fp) + 101c60c: 1005003a cmpeq r2,r2,zero + 101c610: 1000611e bne r2,zero,101c798 + return; + } + if (prio > OS_LOWEST_PRIO) { /* Task priority valid ? */ + 101c614: e0bffd03 ldbu r2,-12(fp) + 101c618: 10800570 cmpltui r2,r2,21 + 101c61c: 1000071e bne r2,zero,101c63c + if (prio != OS_PRIO_SELF) { + 101c620: e0bffd03 ldbu r2,-12(fp) + 101c624: 10803fe0 cmpeqi r2,r2,255 + 101c628: 1000041e bne r2,zero,101c63c + *perr = OS_ERR_PRIO_INVALID; /* No */ + 101c62c: e0ffff17 ldw r3,-4(fp) + 101c630: 00800a84 movi r2,42 + 101c634: 18800005 stb r2,0(r3) + return; + 101c638: 00005706 br 101c798 + } + } + if (pname == (INT8U *)0) { /* Is 'pname' a NULL pointer? */ + 101c63c: e0bffe17 ldw r2,-8(fp) + 101c640: 1004c03a cmpne r2,r2,zero + 101c644: 1000041e bne r2,zero,101c658 + *perr = OS_ERR_PNAME_NULL; /* Yes */ + 101c648: e0ffff17 ldw r3,-4(fp) + 101c64c: 00800304 movi r2,12 + 101c650: 18800005 stb r2,0(r3) + return; + 101c654: 00005006 br 101c798 + } +#endif + if (OSIntNesting > 0) { /* See if trying to call from an ISR */ + 101c658: 008040b4 movhi r2,258 + 101c65c: 10952204 addi r2,r2,21640 + 101c660: 10800003 ldbu r2,0(r2) + 101c664: 10803fcc andi r2,r2,255 + 101c668: 1005003a cmpeq r2,r2,zero + 101c66c: 1000041e bne r2,zero,101c680 + *perr = OS_ERR_NAME_SET_ISR; + 101c670: e0ffff17 ldw r3,-4(fp) + 101c674: 00800484 movi r2,18 + 101c678: 18800005 stb r2,0(r3) + return; + 101c67c: 00004606 br 101c798 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 101c680: 0005303a rdctl r2,status + 101c684: e0bff915 stw r2,-28(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 101c688: e0fff917 ldw r3,-28(fp) + 101c68c: 00bfff84 movi r2,-2 + 101c690: 1884703a and r2,r3,r2 + 101c694: 1001703a wrctl status,r2 + + return context; + 101c698: e0bff917 ldw r2,-28(fp) + } + OS_ENTER_CRITICAL(); + 101c69c: e0bffa15 stw r2,-24(fp) + if (prio == OS_PRIO_SELF) { /* See if caller desires to set it's own name */ + 101c6a0: e0bffd03 ldbu r2,-12(fp) + 101c6a4: 10803fd8 cmpnei r2,r2,255 + 101c6a8: 1000051e bne r2,zero,101c6c0 + prio = OSTCBCur->OSTCBPrio; + 101c6ac: 008040b4 movhi r2,258 + 101c6b0: 10952304 addi r2,r2,21644 + 101c6b4: 10800017 ldw r2,0(r2) + 101c6b8: 10800c83 ldbu r2,50(r2) + 101c6bc: e0bffd05 stb r2,-12(fp) + } + ptcb = OSTCBPrioTbl[prio]; + 101c6c0: e0bffd03 ldbu r2,-12(fp) + 101c6c4: 00c040f4 movhi r3,259 + 101c6c8: 18f3b104 addi r3,r3,-12604 + 101c6cc: 1085883a add r2,r2,r2 + 101c6d0: 1085883a add r2,r2,r2 + 101c6d4: 10c5883a add r2,r2,r3 + 101c6d8: 10800017 ldw r2,0(r2) + 101c6dc: e0bffb15 stw r2,-20(fp) + if (ptcb == (OS_TCB *)0) { /* Does task exist? */ + 101c6e0: e0bffb17 ldw r2,-20(fp) + 101c6e4: 1004c03a cmpne r2,r2,zero + 101c6e8: 1000081e bne r2,zero,101c70c + 101c6ec: e0bffa17 ldw r2,-24(fp) + 101c6f0: e0bff815 stw r2,-32(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 101c6f4: e0bff817 ldw r2,-32(fp) + 101c6f8: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); /* No */ + *perr = OS_ERR_TASK_NOT_EXIST; + 101c6fc: e0ffff17 ldw r3,-4(fp) + 101c700: 008010c4 movi r2,67 + 101c704: 18800005 stb r2,0(r3) + return; + 101c708: 00002306 br 101c798 + } + if (ptcb == OS_TCB_RESERVED) { /* Task assigned to a Mutex? */ + 101c70c: e0bffb17 ldw r2,-20(fp) + 101c710: 10800058 cmpnei r2,r2,1 + 101c714: 1000081e bne r2,zero,101c738 + 101c718: e0bffa17 ldw r2,-24(fp) + 101c71c: e0bff715 stw r2,-36(fp) + 101c720: e0bff717 ldw r2,-36(fp) + 101c724: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); /* Yes */ + *perr = OS_ERR_TASK_NOT_EXIST; + 101c728: e0ffff17 ldw r3,-4(fp) + 101c72c: 008010c4 movi r2,67 + 101c730: 18800005 stb r2,0(r3) + return; + 101c734: 00001806 br 101c798 + } + len = OS_StrLen(pname); /* Yes, Can we fit the string in the TCB? */ + 101c738: e13ffe17 ldw r4,-8(fp) + 101c73c: 1016e7c0 call 1016e7c + 101c740: e0bffc05 stb r2,-16(fp) + if (len > (OS_TASK_NAME_SIZE - 1)) { /* No */ + 101c744: e0bffc03 ldbu r2,-16(fp) + 101c748: 10800830 cmpltui r2,r2,32 + 101c74c: 1000081e bne r2,zero,101c770 + 101c750: e0bffa17 ldw r2,-24(fp) + 101c754: e0bff615 stw r2,-40(fp) + 101c758: e0bff617 ldw r2,-40(fp) + 101c75c: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + *perr = OS_ERR_TASK_NAME_TOO_LONG; + 101c760: e0ffff17 ldw r3,-4(fp) + 101c764: 00801044 movi r2,65 + 101c768: 18800005 stb r2,0(r3) + return; + 101c76c: 00000a06 br 101c798 + } + (void)OS_StrCopy(ptcb->OSTCBTaskName, pname); /* Yes, copy to TCB */ + 101c770: e0bffb17 ldw r2,-20(fp) + 101c774: 11001304 addi r4,r2,76 + 101c778: e17ffe17 ldw r5,-8(fp) + 101c77c: 1016dfc0 call 1016dfc + 101c780: e0bffa17 ldw r2,-24(fp) + 101c784: e0bff515 stw r2,-44(fp) + 101c788: e0bff517 ldw r2,-44(fp) + 101c78c: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + 101c790: e0bfff17 ldw r2,-4(fp) + 101c794: 10000005 stb zero,0(r2) +} + 101c798: e037883a mov sp,fp + 101c79c: dfc00117 ldw ra,4(sp) + 101c7a0: df000017 ldw fp,0(sp) + 101c7a4: dec00204 addi sp,sp,8 + 101c7a8: f800283a ret + +0101c7ac : +********************************************************************************************************* +*/ + +#if OS_TASK_SUSPEND_EN > 0 +INT8U OSTaskResume (INT8U prio) +{ + 101c7ac: defff304 addi sp,sp,-52 + 101c7b0: dfc00c15 stw ra,48(sp) + 101c7b4: df000b15 stw fp,44(sp) + 101c7b8: df000b04 addi fp,sp,44 + 101c7bc: e13ffe05 stb r4,-8(fp) + OS_TCB *ptcb; +#if OS_CRITICAL_METHOD == 3 /* Storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 101c7c0: e03ffc15 stw zero,-16(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (prio >= OS_LOWEST_PRIO) { /* Make sure task priority is valid */ + 101c7c4: e0bffe03 ldbu r2,-8(fp) + 101c7c8: 10800530 cmpltui r2,r2,20 + 101c7cc: 1000031e bne r2,zero,101c7dc + return (OS_ERR_PRIO_INVALID); + 101c7d0: 00800a84 movi r2,42 + 101c7d4: e0bfff15 stw r2,-4(fp) + 101c7d8: 00007406 br 101c9ac +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 101c7dc: 0005303a rdctl r2,status + 101c7e0: e0bffb15 stw r2,-20(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 101c7e4: e0fffb17 ldw r3,-20(fp) + 101c7e8: 00bfff84 movi r2,-2 + 101c7ec: 1884703a and r2,r3,r2 + 101c7f0: 1001703a wrctl status,r2 + + return context; + 101c7f4: e0bffb17 ldw r2,-20(fp) + } +#endif + OS_ENTER_CRITICAL(); + 101c7f8: e0bffc15 stw r2,-16(fp) + ptcb = OSTCBPrioTbl[prio]; + 101c7fc: e0bffe03 ldbu r2,-8(fp) + 101c800: 00c040f4 movhi r3,259 + 101c804: 18f3b104 addi r3,r3,-12604 + 101c808: 1085883a add r2,r2,r2 + 101c80c: 1085883a add r2,r2,r2 + 101c810: 10c5883a add r2,r2,r3 + 101c814: 10800017 ldw r2,0(r2) + 101c818: e0bffd15 stw r2,-12(fp) + if (ptcb == (OS_TCB *)0) { /* Task to suspend must exist */ + 101c81c: e0bffd17 ldw r2,-12(fp) + 101c820: 1004c03a cmpne r2,r2,zero + 101c824: 1000071e bne r2,zero,101c844 + 101c828: e0bffc17 ldw r2,-16(fp) + 101c82c: e0bffa15 stw r2,-24(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 101c830: e0bffa17 ldw r2,-24(fp) + 101c834: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_RESUME_PRIO); + 101c838: 00801184 movi r2,70 + 101c83c: e0bfff15 stw r2,-4(fp) + 101c840: 00005a06 br 101c9ac + } + if (ptcb == OS_TCB_RESERVED) { /* See if assigned to Mutex */ + 101c844: e0bffd17 ldw r2,-12(fp) + 101c848: 10800058 cmpnei r2,r2,1 + 101c84c: 1000071e bne r2,zero,101c86c + 101c850: e0bffc17 ldw r2,-16(fp) + 101c854: e0bff915 stw r2,-28(fp) + 101c858: e0bff917 ldw r2,-28(fp) + 101c85c: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_NOT_EXIST); + 101c860: 008010c4 movi r2,67 + 101c864: e0bfff15 stw r2,-4(fp) + 101c868: 00005006 br 101c9ac + } + if ((ptcb->OSTCBStat & OS_STAT_SUSPEND) != OS_STAT_RDY) { /* Task must be suspended */ + 101c86c: e0bffd17 ldw r2,-12(fp) + 101c870: 10800c03 ldbu r2,48(r2) + 101c874: 10803fcc andi r2,r2,255 + 101c878: 1080020c andi r2,r2,8 + 101c87c: 1005003a cmpeq r2,r2,zero + 101c880: 1000441e bne r2,zero,101c994 + ptcb->OSTCBStat &= ~(INT8U)OS_STAT_SUSPEND; /* Remove suspension */ + 101c884: e0bffd17 ldw r2,-12(fp) + 101c888: 10c00c03 ldbu r3,48(r2) + 101c88c: 00bffdc4 movi r2,-9 + 101c890: 1884703a and r2,r3,r2 + 101c894: 1007883a mov r3,r2 + 101c898: e0bffd17 ldw r2,-12(fp) + 101c89c: 10c00c05 stb r3,48(r2) + if (ptcb->OSTCBStat == OS_STAT_RDY) { /* See if task is now ready */ + 101c8a0: e0bffd17 ldw r2,-12(fp) + 101c8a4: 10800c03 ldbu r2,48(r2) + 101c8a8: 10803fcc andi r2,r2,255 + 101c8ac: 1004c03a cmpne r2,r2,zero + 101c8b0: 1000321e bne r2,zero,101c97c + if (ptcb->OSTCBDly == 0) { + 101c8b4: e0bffd17 ldw r2,-12(fp) + 101c8b8: 10800b8b ldhu r2,46(r2) + 101c8bc: 10bfffcc andi r2,r2,65535 + 101c8c0: 1004c03a cmpne r2,r2,zero + 101c8c4: 1000281e bne r2,zero,101c968 + OSRdyGrp |= ptcb->OSTCBBitY; /* Yes, Make task ready to run */ + 101c8c8: e0bffd17 ldw r2,-12(fp) + 101c8cc: 10c00d83 ldbu r3,54(r2) + 101c8d0: 008040b4 movhi r2,258 + 101c8d4: 10952004 addi r2,r2,21632 + 101c8d8: 10800003 ldbu r2,0(r2) + 101c8dc: 1884b03a or r2,r3,r2 + 101c8e0: 1007883a mov r3,r2 + 101c8e4: 008040b4 movhi r2,258 + 101c8e8: 10952004 addi r2,r2,21632 + 101c8ec: 10c00005 stb r3,0(r2) + OSRdyTbl[ptcb->OSTCBY] |= ptcb->OSTCBBitX; + 101c8f0: e0bffd17 ldw r2,-12(fp) + 101c8f4: 10800d03 ldbu r2,52(r2) + 101c8f8: 11003fcc andi r4,r2,255 + 101c8fc: e0bffd17 ldw r2,-12(fp) + 101c900: 10800d03 ldbu r2,52(r2) + 101c904: 10c03fcc andi r3,r2,255 + 101c908: 008040b4 movhi r2,258 + 101c90c: 10952044 addi r2,r2,21633 + 101c910: 10c5883a add r2,r2,r3 + 101c914: 10c00003 ldbu r3,0(r2) + 101c918: e0bffd17 ldw r2,-12(fp) + 101c91c: 10800d43 ldbu r2,53(r2) + 101c920: 1884b03a or r2,r3,r2 + 101c924: 1007883a mov r3,r2 + 101c928: 008040b4 movhi r2,258 + 101c92c: 10952044 addi r2,r2,21633 + 101c930: 1105883a add r2,r2,r4 + 101c934: 10c00005 stb r3,0(r2) + 101c938: e0bffc17 ldw r2,-16(fp) + 101c93c: e0bff815 stw r2,-32(fp) + 101c940: e0bff817 ldw r2,-32(fp) + 101c944: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + if (OSRunning == OS_TRUE) { + 101c948: 008040b4 movhi r2,258 + 101c94c: 10951444 addi r2,r2,21585 + 101c950: 10800003 ldbu r2,0(r2) + 101c954: 10803fcc andi r2,r2,255 + 101c958: 10800058 cmpnei r2,r2,1 + 101c95c: 10000b1e bne r2,zero,101c98c + OS_Sched(); /* Find new highest priority task */ + 101c960: 1016cb80 call 1016cb8 + 101c964: 00000906 br 101c98c + 101c968: e0bffc17 ldw r2,-16(fp) + 101c96c: e0bff715 stw r2,-36(fp) + 101c970: e0bff717 ldw r2,-36(fp) + 101c974: 1001703a wrctl status,r2 + 101c978: 00000406 br 101c98c + 101c97c: e0bffc17 ldw r2,-16(fp) + 101c980: e0bff615 stw r2,-40(fp) + 101c984: e0bff617 ldw r2,-40(fp) + 101c988: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + } + } else { /* Must be pending on event */ + OS_EXIT_CRITICAL(); + } + return (OS_ERR_NONE); + 101c98c: e03fff15 stw zero,-4(fp) + 101c990: 00000606 br 101c9ac + 101c994: e0bffc17 ldw r2,-16(fp) + 101c998: e0bff515 stw r2,-44(fp) + 101c99c: e0bff517 ldw r2,-44(fp) + 101c9a0: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_NOT_SUSPENDED); + 101c9a4: 00801104 movi r2,68 + 101c9a8: e0bfff15 stw r2,-4(fp) + 101c9ac: e0bfff17 ldw r2,-4(fp) +} + 101c9b0: e037883a mov sp,fp + 101c9b4: dfc00117 ldw ra,4(sp) + 101c9b8: df000017 ldw fp,0(sp) + 101c9bc: dec00204 addi sp,sp,8 + 101c9c0: f800283a ret + +0101c9c4 : +* OS_ERR_PDATA_NULL if 'p_stk_data' is a NULL pointer +********************************************************************************************************* +*/ +#if (OS_TASK_STAT_STK_CHK_EN > 0) && (OS_TASK_CREATE_EXT_EN > 0) +INT8U OSTaskStkChk (INT8U prio, OS_STK_DATA *p_stk_data) +{ + 101c9c4: defff204 addi sp,sp,-56 + 101c9c8: df000d15 stw fp,52(sp) + 101c9cc: df000d04 addi fp,sp,52 + 101c9d0: e17ffe15 stw r5,-8(fp) + 101c9d4: e13ffd05 stb r4,-12(fp) + OS_TCB *ptcb; + OS_STK *pchk; + INT32U nfree; + INT32U size; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 101c9d8: e03ff815 stw zero,-32(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (prio > OS_LOWEST_PRIO) { /* Make sure task priority is valid */ + 101c9dc: e0bffd03 ldbu r2,-12(fp) + 101c9e0: 10800570 cmpltui r2,r2,21 + 101c9e4: 1000061e bne r2,zero,101ca00 + if (prio != OS_PRIO_SELF) { + 101c9e8: e0bffd03 ldbu r2,-12(fp) + 101c9ec: 10803fe0 cmpeqi r2,r2,255 + 101c9f0: 1000031e bne r2,zero,101ca00 + return (OS_ERR_PRIO_INVALID); + 101c9f4: 00800a84 movi r2,42 + 101c9f8: e0bfff15 stw r2,-4(fp) + 101c9fc: 00006b06 br 101cbac + } + } + if (p_stk_data == (OS_STK_DATA *)0) { /* Validate 'p_stk_data' */ + 101ca00: e0bffe17 ldw r2,-8(fp) + 101ca04: 1004c03a cmpne r2,r2,zero + 101ca08: 1000031e bne r2,zero,101ca18 + return (OS_ERR_PDATA_NULL); + 101ca0c: 00800244 movi r2,9 + 101ca10: e0bfff15 stw r2,-4(fp) + 101ca14: 00006506 br 101cbac + } +#endif + p_stk_data->OSFree = 0; /* Assume failure, set to 0 size */ + 101ca18: e0bffe17 ldw r2,-8(fp) + 101ca1c: 10000015 stw zero,0(r2) + p_stk_data->OSUsed = 0; + 101ca20: e0bffe17 ldw r2,-8(fp) + 101ca24: 10000115 stw zero,4(r2) +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 101ca28: 0005303a rdctl r2,status + 101ca2c: e0bff715 stw r2,-36(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 101ca30: e0fff717 ldw r3,-36(fp) + 101ca34: 00bfff84 movi r2,-2 + 101ca38: 1884703a and r2,r3,r2 + 101ca3c: 1001703a wrctl status,r2 + + return context; + 101ca40: e0bff717 ldw r2,-36(fp) + OS_ENTER_CRITICAL(); + 101ca44: e0bff815 stw r2,-32(fp) + if (prio == OS_PRIO_SELF) { /* See if check for SELF */ + 101ca48: e0bffd03 ldbu r2,-12(fp) + 101ca4c: 10803fd8 cmpnei r2,r2,255 + 101ca50: 1000051e bne r2,zero,101ca68 + prio = OSTCBCur->OSTCBPrio; + 101ca54: 008040b4 movhi r2,258 + 101ca58: 10952304 addi r2,r2,21644 + 101ca5c: 10800017 ldw r2,0(r2) + 101ca60: 10800c83 ldbu r2,50(r2) + 101ca64: e0bffd05 stb r2,-12(fp) + } + ptcb = OSTCBPrioTbl[prio]; + 101ca68: e0bffd03 ldbu r2,-12(fp) + 101ca6c: 00c040f4 movhi r3,259 + 101ca70: 18f3b104 addi r3,r3,-12604 + 101ca74: 1085883a add r2,r2,r2 + 101ca78: 1085883a add r2,r2,r2 + 101ca7c: 10c5883a add r2,r2,r3 + 101ca80: 10800017 ldw r2,0(r2) + 101ca84: e0bffc15 stw r2,-16(fp) + if (ptcb == (OS_TCB *)0) { /* Make sure task exist */ + 101ca88: e0bffc17 ldw r2,-16(fp) + 101ca8c: 1004c03a cmpne r2,r2,zero + 101ca90: 1000071e bne r2,zero,101cab0 + 101ca94: e0bff817 ldw r2,-32(fp) + 101ca98: e0bff615 stw r2,-40(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 101ca9c: e0bff617 ldw r2,-40(fp) + 101caa0: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_NOT_EXIST); + 101caa4: 008010c4 movi r2,67 + 101caa8: e0bfff15 stw r2,-4(fp) + 101caac: 00003f06 br 101cbac + } + if (ptcb == OS_TCB_RESERVED) { + 101cab0: e0bffc17 ldw r2,-16(fp) + 101cab4: 10800058 cmpnei r2,r2,1 + 101cab8: 1000071e bne r2,zero,101cad8 + 101cabc: e0bff817 ldw r2,-32(fp) + 101cac0: e0bff515 stw r2,-44(fp) + 101cac4: e0bff517 ldw r2,-44(fp) + 101cac8: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_NOT_EXIST); + 101cacc: 008010c4 movi r2,67 + 101cad0: e0bfff15 stw r2,-4(fp) + 101cad4: 00003506 br 101cbac + } + if ((ptcb->OSTCBOpt & OS_TASK_OPT_STK_CHK) == 0) { /* Make sure stack checking option is set */ + 101cad8: e0bffc17 ldw r2,-16(fp) + 101cadc: 1080040b ldhu r2,16(r2) + 101cae0: 10bfffcc andi r2,r2,65535 + 101cae4: 1080004c andi r2,r2,1 + 101cae8: 1004c03a cmpne r2,r2,zero + 101caec: 1000071e bne r2,zero,101cb0c + 101caf0: e0bff817 ldw r2,-32(fp) + 101caf4: e0bff415 stw r2,-48(fp) + 101caf8: e0bff417 ldw r2,-48(fp) + 101cafc: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_OPT); + 101cb00: 00801144 movi r2,69 + 101cb04: e0bfff15 stw r2,-4(fp) + 101cb08: 00002806 br 101cbac + } + nfree = 0; + 101cb0c: e03ffa15 stw zero,-24(fp) + size = ptcb->OSTCBStkSize; + 101cb10: e0bffc17 ldw r2,-16(fp) + 101cb14: 10800317 ldw r2,12(r2) + 101cb18: e0bff915 stw r2,-28(fp) + pchk = ptcb->OSTCBStkBottom; + 101cb1c: e0bffc17 ldw r2,-16(fp) + 101cb20: 10800217 ldw r2,8(r2) + 101cb24: e0bffb15 stw r2,-20(fp) + 101cb28: e0bff817 ldw r2,-32(fp) + 101cb2c: e0bff315 stw r2,-52(fp) + 101cb30: e0bff317 ldw r2,-52(fp) + 101cb34: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); +#if OS_STK_GROWTH == 1 + while (*pchk++ == (OS_STK)0) { /* Compute the number of zero entries on the stk */ + 101cb38: 00000306 br 101cb48 + nfree++; + 101cb3c: e0bffa17 ldw r2,-24(fp) + 101cb40: 10800044 addi r2,r2,1 + 101cb44: e0bffa15 stw r2,-24(fp) + nfree = 0; + size = ptcb->OSTCBStkSize; + pchk = ptcb->OSTCBStkBottom; + OS_EXIT_CRITICAL(); +#if OS_STK_GROWTH == 1 + while (*pchk++ == (OS_STK)0) { /* Compute the number of zero entries on the stk */ + 101cb48: e0bffb17 ldw r2,-20(fp) + 101cb4c: 10800017 ldw r2,0(r2) + 101cb50: 1005003a cmpeq r2,r2,zero + 101cb54: 1007883a mov r3,r2 + 101cb58: e0bffb17 ldw r2,-20(fp) + 101cb5c: 10800104 addi r2,r2,4 + 101cb60: e0bffb15 stw r2,-20(fp) + 101cb64: 18803fcc andi r2,r3,255 + 101cb68: 1004c03a cmpne r2,r2,zero + 101cb6c: 103ff31e bne r2,zero,101cb3c +#else + while (*pchk-- == (OS_STK)0) { + nfree++; + } +#endif + p_stk_data->OSFree = nfree * sizeof(OS_STK); /* Compute number of free bytes on the stack */ + 101cb70: e0bffa17 ldw r2,-24(fp) + 101cb74: 1085883a add r2,r2,r2 + 101cb78: 1085883a add r2,r2,r2 + 101cb7c: 1007883a mov r3,r2 + 101cb80: e0bffe17 ldw r2,-8(fp) + 101cb84: 10c00015 stw r3,0(r2) + p_stk_data->OSUsed = (size - nfree) * sizeof(OS_STK); /* Compute number of bytes used on the stack */ + 101cb88: e0fff917 ldw r3,-28(fp) + 101cb8c: e0bffa17 ldw r2,-24(fp) + 101cb90: 1885c83a sub r2,r3,r2 + 101cb94: 1085883a add r2,r2,r2 + 101cb98: 1085883a add r2,r2,r2 + 101cb9c: 1007883a mov r3,r2 + 101cba0: e0bffe17 ldw r2,-8(fp) + 101cba4: 10c00115 stw r3,4(r2) + return (OS_ERR_NONE); + 101cba8: e03fff15 stw zero,-4(fp) + 101cbac: e0bfff17 ldw r2,-4(fp) +} + 101cbb0: e037883a mov sp,fp + 101cbb4: df000017 ldw fp,0(sp) + 101cbb8: dec00104 addi sp,sp,4 + 101cbbc: f800283a ret + +0101cbc0 : +********************************************************************************************************* +*/ + +#if OS_TASK_SUSPEND_EN > 0 +INT8U OSTaskSuspend (INT8U prio) +{ + 101cbc0: defff404 addi sp,sp,-48 + 101cbc4: dfc00b15 stw ra,44(sp) + 101cbc8: df000a15 stw fp,40(sp) + 101cbcc: df000a04 addi fp,sp,40 + 101cbd0: e13ffe05 stb r4,-8(fp) + BOOLEAN self; + OS_TCB *ptcb; + INT8U y; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 101cbd4: e03ffa15 stw zero,-24(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (prio == OS_TASK_IDLE_PRIO) { /* Not allowed to suspend idle task */ + 101cbd8: e0bffe03 ldbu r2,-8(fp) + 101cbdc: 10800518 cmpnei r2,r2,20 + 101cbe0: 1000031e bne r2,zero,101cbf0 + return (OS_ERR_TASK_SUSPEND_IDLE); + 101cbe4: 008011c4 movi r2,71 + 101cbe8: e0bfff15 stw r2,-4(fp) + 101cbec: 00007906 br 101cdd4 + } + if (prio >= OS_LOWEST_PRIO) { /* Task priority valid ? */ + 101cbf0: e0bffe03 ldbu r2,-8(fp) + 101cbf4: 10800530 cmpltui r2,r2,20 + 101cbf8: 1000061e bne r2,zero,101cc14 + if (prio != OS_PRIO_SELF) { + 101cbfc: e0bffe03 ldbu r2,-8(fp) + 101cc00: 10803fe0 cmpeqi r2,r2,255 + 101cc04: 1000031e bne r2,zero,101cc14 + return (OS_ERR_PRIO_INVALID); + 101cc08: 00800a84 movi r2,42 + 101cc0c: e0bfff15 stw r2,-4(fp) + 101cc10: 00007006 br 101cdd4 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 101cc14: 0005303a rdctl r2,status + 101cc18: e0bff915 stw r2,-28(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 101cc1c: e0fff917 ldw r3,-28(fp) + 101cc20: 00bfff84 movi r2,-2 + 101cc24: 1884703a and r2,r3,r2 + 101cc28: 1001703a wrctl status,r2 + + return context; + 101cc2c: e0bff917 ldw r2,-28(fp) + } + } +#endif + OS_ENTER_CRITICAL(); + 101cc30: e0bffa15 stw r2,-24(fp) + if (prio == OS_PRIO_SELF) { /* See if suspend SELF */ + 101cc34: e0bffe03 ldbu r2,-8(fp) + 101cc38: 10803fd8 cmpnei r2,r2,255 + 101cc3c: 1000081e bne r2,zero,101cc60 + prio = OSTCBCur->OSTCBPrio; + 101cc40: 008040b4 movhi r2,258 + 101cc44: 10952304 addi r2,r2,21644 + 101cc48: 10800017 ldw r2,0(r2) + 101cc4c: 10800c83 ldbu r2,50(r2) + 101cc50: e0bffe05 stb r2,-8(fp) + self = OS_TRUE; + 101cc54: 00800044 movi r2,1 + 101cc58: e0bffd05 stb r2,-12(fp) + 101cc5c: 00000b06 br 101cc8c + } else if (prio == OSTCBCur->OSTCBPrio) { /* See if suspending self */ + 101cc60: 008040b4 movhi r2,258 + 101cc64: 10952304 addi r2,r2,21644 + 101cc68: 10800017 ldw r2,0(r2) + 101cc6c: 10800c83 ldbu r2,50(r2) + 101cc70: 10c03fcc andi r3,r2,255 + 101cc74: e0bffe03 ldbu r2,-8(fp) + 101cc78: 1880031e bne r3,r2,101cc88 + self = OS_TRUE; + 101cc7c: 00800044 movi r2,1 + 101cc80: e0bffd05 stb r2,-12(fp) + 101cc84: 00000106 br 101cc8c + } else { + self = OS_FALSE; /* No suspending another task */ + 101cc88: e03ffd05 stb zero,-12(fp) + } + ptcb = OSTCBPrioTbl[prio]; + 101cc8c: e0bffe03 ldbu r2,-8(fp) + 101cc90: 00c040f4 movhi r3,259 + 101cc94: 18f3b104 addi r3,r3,-12604 + 101cc98: 1085883a add r2,r2,r2 + 101cc9c: 1085883a add r2,r2,r2 + 101cca0: 10c5883a add r2,r2,r3 + 101cca4: 10800017 ldw r2,0(r2) + 101cca8: e0bffc15 stw r2,-16(fp) + if (ptcb == (OS_TCB *)0) { /* Task to suspend must exist */ + 101ccac: e0bffc17 ldw r2,-16(fp) + 101ccb0: 1004c03a cmpne r2,r2,zero + 101ccb4: 1000071e bne r2,zero,101ccd4 + 101ccb8: e0bffa17 ldw r2,-24(fp) + 101ccbc: e0bff815 stw r2,-32(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 101ccc0: e0bff817 ldw r2,-32(fp) + 101ccc4: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_SUSPEND_PRIO); + 101ccc8: 00801204 movi r2,72 + 101cccc: e0bfff15 stw r2,-4(fp) + 101ccd0: 00004006 br 101cdd4 + } + if (ptcb == OS_TCB_RESERVED) { /* See if assigned to Mutex */ + 101ccd4: e0bffc17 ldw r2,-16(fp) + 101ccd8: 10800058 cmpnei r2,r2,1 + 101ccdc: 1000071e bne r2,zero,101ccfc + 101cce0: e0bffa17 ldw r2,-24(fp) + 101cce4: e0bff715 stw r2,-36(fp) + 101cce8: e0bff717 ldw r2,-36(fp) + 101ccec: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_NOT_EXIST); + 101ccf0: 008010c4 movi r2,67 + 101ccf4: e0bfff15 stw r2,-4(fp) + 101ccf8: 00003606 br 101cdd4 + } + y = ptcb->OSTCBY; + 101ccfc: e0bffc17 ldw r2,-16(fp) + 101cd00: 10800d03 ldbu r2,52(r2) + 101cd04: e0bffb05 stb r2,-20(fp) + OSRdyTbl[y] &= ~ptcb->OSTCBBitX; /* Make task not ready */ + 101cd08: e13ffb03 ldbu r4,-20(fp) + 101cd0c: e0fffb03 ldbu r3,-20(fp) + 101cd10: 008040b4 movhi r2,258 + 101cd14: 10952044 addi r2,r2,21633 + 101cd18: 10c5883a add r2,r2,r3 + 101cd1c: 10800003 ldbu r2,0(r2) + 101cd20: 1007883a mov r3,r2 + 101cd24: e0bffc17 ldw r2,-16(fp) + 101cd28: 10800d43 ldbu r2,53(r2) + 101cd2c: 0084303a nor r2,zero,r2 + 101cd30: 1884703a and r2,r3,r2 + 101cd34: 1007883a mov r3,r2 + 101cd38: 008040b4 movhi r2,258 + 101cd3c: 10952044 addi r2,r2,21633 + 101cd40: 1105883a add r2,r2,r4 + 101cd44: 10c00005 stb r3,0(r2) + if (OSRdyTbl[y] == 0) { + 101cd48: e0fffb03 ldbu r3,-20(fp) + 101cd4c: 008040b4 movhi r2,258 + 101cd50: 10952044 addi r2,r2,21633 + 101cd54: 10c5883a add r2,r2,r3 + 101cd58: 10800003 ldbu r2,0(r2) + 101cd5c: 10803fcc andi r2,r2,255 + 101cd60: 1004c03a cmpne r2,r2,zero + 101cd64: 10000c1e bne r2,zero,101cd98 + OSRdyGrp &= ~ptcb->OSTCBBitY; + 101cd68: e0bffc17 ldw r2,-16(fp) + 101cd6c: 10800d83 ldbu r2,54(r2) + 101cd70: 0084303a nor r2,zero,r2 + 101cd74: 1007883a mov r3,r2 + 101cd78: 008040b4 movhi r2,258 + 101cd7c: 10952004 addi r2,r2,21632 + 101cd80: 10800003 ldbu r2,0(r2) + 101cd84: 1884703a and r2,r3,r2 + 101cd88: 1007883a mov r3,r2 + 101cd8c: 008040b4 movhi r2,258 + 101cd90: 10952004 addi r2,r2,21632 + 101cd94: 10c00005 stb r3,0(r2) + } + ptcb->OSTCBStat |= OS_STAT_SUSPEND; /* Status of task is 'SUSPENDED' */ + 101cd98: e0bffc17 ldw r2,-16(fp) + 101cd9c: 10800c03 ldbu r2,48(r2) + 101cda0: 10800214 ori r2,r2,8 + 101cda4: 1007883a mov r3,r2 + 101cda8: e0bffc17 ldw r2,-16(fp) + 101cdac: 10c00c05 stb r3,48(r2) + 101cdb0: e0bffa17 ldw r2,-24(fp) + 101cdb4: e0bff615 stw r2,-40(fp) + 101cdb8: e0bff617 ldw r2,-40(fp) + 101cdbc: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + if (self == OS_TRUE) { /* Context switch only if SELF */ + 101cdc0: e0bffd03 ldbu r2,-12(fp) + 101cdc4: 10800058 cmpnei r2,r2,1 + 101cdc8: 1000011e bne r2,zero,101cdd0 + OS_Sched(); /* Find new highest priority task */ + 101cdcc: 1016cb80 call 1016cb8 + } + return (OS_ERR_NONE); + 101cdd0: e03fff15 stw zero,-4(fp) + 101cdd4: e0bfff17 ldw r2,-4(fp) +} + 101cdd8: e037883a mov sp,fp + 101cddc: dfc00117 ldw ra,4(sp) + 101cde0: df000017 ldw fp,0(sp) + 101cde4: dec00204 addi sp,sp,8 + 101cde8: f800283a ret + +0101cdec : +********************************************************************************************************* +*/ + +#if OS_TASK_QUERY_EN > 0 +INT8U OSTaskQuery (INT8U prio, OS_TCB *p_task_data) +{ + 101cdec: defff504 addi sp,sp,-44 + 101cdf0: dfc00a15 stw ra,40(sp) + 101cdf4: df000915 stw fp,36(sp) + 101cdf8: df000904 addi fp,sp,36 + 101cdfc: e17ffe15 stw r5,-8(fp) + 101ce00: e13ffd05 stb r4,-12(fp) + OS_TCB *ptcb; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 101ce04: e03ffb15 stw zero,-20(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (prio > OS_LOWEST_PRIO) { /* Task priority valid ? */ + 101ce08: e0bffd03 ldbu r2,-12(fp) + 101ce0c: 10800570 cmpltui r2,r2,21 + 101ce10: 1000061e bne r2,zero,101ce2c + if (prio != OS_PRIO_SELF) { + 101ce14: e0bffd03 ldbu r2,-12(fp) + 101ce18: 10803fe0 cmpeqi r2,r2,255 + 101ce1c: 1000031e bne r2,zero,101ce2c + return (OS_ERR_PRIO_INVALID); + 101ce20: 00800a84 movi r2,42 + 101ce24: e0bfff15 stw r2,-4(fp) + 101ce28: 00003b06 br 101cf18 + } + } + if (p_task_data == (OS_TCB *)0) { /* Validate 'p_task_data' */ + 101ce2c: e0bffe17 ldw r2,-8(fp) + 101ce30: 1004c03a cmpne r2,r2,zero + 101ce34: 1000031e bne r2,zero,101ce44 + return (OS_ERR_PDATA_NULL); + 101ce38: 00800244 movi r2,9 + 101ce3c: e0bfff15 stw r2,-4(fp) + 101ce40: 00003506 br 101cf18 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 101ce44: 0005303a rdctl r2,status + 101ce48: e0bffa15 stw r2,-24(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 101ce4c: e0fffa17 ldw r3,-24(fp) + 101ce50: 00bfff84 movi r2,-2 + 101ce54: 1884703a and r2,r3,r2 + 101ce58: 1001703a wrctl status,r2 + + return context; + 101ce5c: e0bffa17 ldw r2,-24(fp) + } +#endif + OS_ENTER_CRITICAL(); + 101ce60: e0bffb15 stw r2,-20(fp) + if (prio == OS_PRIO_SELF) { /* See if suspend SELF */ + 101ce64: e0bffd03 ldbu r2,-12(fp) + 101ce68: 10803fd8 cmpnei r2,r2,255 + 101ce6c: 1000051e bne r2,zero,101ce84 + prio = OSTCBCur->OSTCBPrio; + 101ce70: 008040b4 movhi r2,258 + 101ce74: 10952304 addi r2,r2,21644 + 101ce78: 10800017 ldw r2,0(r2) + 101ce7c: 10800c83 ldbu r2,50(r2) + 101ce80: e0bffd05 stb r2,-12(fp) + } + ptcb = OSTCBPrioTbl[prio]; + 101ce84: e0bffd03 ldbu r2,-12(fp) + 101ce88: 00c040f4 movhi r3,259 + 101ce8c: 18f3b104 addi r3,r3,-12604 + 101ce90: 1085883a add r2,r2,r2 + 101ce94: 1085883a add r2,r2,r2 + 101ce98: 10c5883a add r2,r2,r3 + 101ce9c: 10800017 ldw r2,0(r2) + 101cea0: e0bffc15 stw r2,-16(fp) + if (ptcb == (OS_TCB *)0) { /* Task to query must exist */ + 101cea4: e0bffc17 ldw r2,-16(fp) + 101cea8: 1004c03a cmpne r2,r2,zero + 101ceac: 1000071e bne r2,zero,101cecc + 101ceb0: e0bffb17 ldw r2,-20(fp) + 101ceb4: e0bff915 stw r2,-28(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 101ceb8: e0bff917 ldw r2,-28(fp) + 101cebc: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_PRIO); + 101cec0: 00800a44 movi r2,41 + 101cec4: e0bfff15 stw r2,-4(fp) + 101cec8: 00001306 br 101cf18 + } + if (ptcb == OS_TCB_RESERVED) { /* Task to query must not be assigned to a Mutex */ + 101cecc: e0bffc17 ldw r2,-16(fp) + 101ced0: 10800058 cmpnei r2,r2,1 + 101ced4: 1000071e bne r2,zero,101cef4 + 101ced8: e0bffb17 ldw r2,-20(fp) + 101cedc: e0bff815 stw r2,-32(fp) + 101cee0: e0bff817 ldw r2,-32(fp) + 101cee4: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_NOT_EXIST); + 101cee8: 008010c4 movi r2,67 + 101ceec: e0bfff15 stw r2,-4(fp) + 101cef0: 00000906 br 101cf18 + } + /* Copy TCB into user storage area */ + OS_MemCopy((INT8U *)p_task_data, (INT8U *)ptcb, sizeof(OS_TCB)); + 101cef4: e13ffe17 ldw r4,-8(fp) + 101cef8: e17ffc17 ldw r5,-16(fp) + 101cefc: 01801b04 movi r6,108 + 101cf00: 1016c4c0 call 1016c4c + 101cf04: e0bffb17 ldw r2,-20(fp) + 101cf08: e0bff715 stw r2,-36(fp) + 101cf0c: e0bff717 ldw r2,-36(fp) + 101cf10: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_NONE); + 101cf14: e03fff15 stw zero,-4(fp) + 101cf18: e0bfff17 ldw r2,-4(fp) +} + 101cf1c: e037883a mov sp,fp + 101cf20: dfc00117 ldw ra,4(sp) + 101cf24: df000017 ldw fp,0(sp) + 101cf28: dec00204 addi sp,sp,8 + 101cf2c: f800283a ret + +0101cf30 : +* Returns : none +********************************************************************************************************* +*/ +#if (OS_TASK_STAT_STK_CHK_EN > 0) && (OS_TASK_CREATE_EXT_EN > 0) +void OS_TaskStkClr (OS_STK *pbos, INT32U size, INT16U opt) +{ + 101cf30: defffc04 addi sp,sp,-16 + 101cf34: df000315 stw fp,12(sp) + 101cf38: df000304 addi fp,sp,12 + 101cf3c: e13ffd15 stw r4,-12(fp) + 101cf40: e17ffe15 stw r5,-8(fp) + 101cf44: e1bfff0d sth r6,-4(fp) + if ((opt & OS_TASK_OPT_STK_CHK) != 0x0000) { /* See if stack checking has been enabled */ + 101cf48: e0bfff0b ldhu r2,-4(fp) + 101cf4c: 1080004c andi r2,r2,1 + 101cf50: 10803fcc andi r2,r2,255 + 101cf54: 1005003a cmpeq r2,r2,zero + 101cf58: 1000101e bne r2,zero,101cf9c + if ((opt & OS_TASK_OPT_STK_CLR) != 0x0000) { /* See if stack needs to be cleared */ + 101cf5c: e0bfff0b ldhu r2,-4(fp) + 101cf60: 1080008c andi r2,r2,2 + 101cf64: 1005003a cmpeq r2,r2,zero + 101cf68: 10000c1e bne r2,zero,101cf9c +#if OS_STK_GROWTH == 1 + while (size > 0) { /* Stack grows from HIGH to LOW memory */ + 101cf6c: 00000806 br 101cf90 + size--; + 101cf70: e0bffe17 ldw r2,-8(fp) + 101cf74: 10bfffc4 addi r2,r2,-1 + 101cf78: e0bffe15 stw r2,-8(fp) + *pbos++ = (OS_STK)0; /* Clear from bottom of stack and up! */ + 101cf7c: e0bffd17 ldw r2,-12(fp) + 101cf80: 10000015 stw zero,0(r2) + 101cf84: e0bffd17 ldw r2,-12(fp) + 101cf88: 10800104 addi r2,r2,4 + 101cf8c: e0bffd15 stw r2,-12(fp) +void OS_TaskStkClr (OS_STK *pbos, INT32U size, INT16U opt) +{ + if ((opt & OS_TASK_OPT_STK_CHK) != 0x0000) { /* See if stack checking has been enabled */ + if ((opt & OS_TASK_OPT_STK_CLR) != 0x0000) { /* See if stack needs to be cleared */ +#if OS_STK_GROWTH == 1 + while (size > 0) { /* Stack grows from HIGH to LOW memory */ + 101cf90: e0bffe17 ldw r2,-8(fp) + 101cf94: 1004c03a cmpne r2,r2,zero + 101cf98: 103ff51e bne r2,zero,101cf70 + *pbos-- = (OS_STK)0; /* Clear from bottom of stack and down */ + } +#endif + } + } +} + 101cf9c: e037883a mov sp,fp + 101cfa0: df000017 ldw fp,0(sp) + 101cfa4: dec00104 addi sp,sp,4 + 101cfa8: f800283a ret + +0101cfac : +* Returns : none +********************************************************************************************************* +*/ + +void OSTimeDly (INT16U ticks) +{ + 101cfac: defff904 addi sp,sp,-28 + 101cfb0: dfc00615 stw ra,24(sp) + 101cfb4: df000515 stw fp,20(sp) + 101cfb8: df000504 addi fp,sp,20 + 101cfbc: e13fff0d sth r4,-4(fp) + INT8U y; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 101cfc0: e03ffd15 stw zero,-12(fp) +#endif + + + + if (OSIntNesting > 0) { /* See if trying to call from an ISR */ + 101cfc4: 008040b4 movhi r2,258 + 101cfc8: 10952204 addi r2,r2,21640 + 101cfcc: 10800003 ldbu r2,0(r2) + 101cfd0: 10803fcc andi r2,r2,255 + 101cfd4: 1004c03a cmpne r2,r2,zero + 101cfd8: 1000421e bne r2,zero,101d0e4 + return; + } + if (ticks > 0) { /* 0 means no delay! */ + 101cfdc: e0bfff0b ldhu r2,-4(fp) + 101cfe0: 1005003a cmpeq r2,r2,zero + 101cfe4: 10003f1e bne r2,zero,101d0e4 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 101cfe8: 0005303a rdctl r2,status + 101cfec: e0bffc15 stw r2,-16(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 101cff0: e0fffc17 ldw r3,-16(fp) + 101cff4: 00bfff84 movi r2,-2 + 101cff8: 1884703a and r2,r3,r2 + 101cffc: 1001703a wrctl status,r2 + + return context; + 101d000: e0bffc17 ldw r2,-16(fp) + OS_ENTER_CRITICAL(); + 101d004: e0bffd15 stw r2,-12(fp) + y = OSTCBCur->OSTCBY; /* Delay current task */ + 101d008: 008040b4 movhi r2,258 + 101d00c: 10952304 addi r2,r2,21644 + 101d010: 10800017 ldw r2,0(r2) + 101d014: 10800d03 ldbu r2,52(r2) + 101d018: e0bffe05 stb r2,-8(fp) + OSRdyTbl[y] &= ~OSTCBCur->OSTCBBitX; + 101d01c: e13ffe03 ldbu r4,-8(fp) + 101d020: e0fffe03 ldbu r3,-8(fp) + 101d024: 008040b4 movhi r2,258 + 101d028: 10952044 addi r2,r2,21633 + 101d02c: 10c5883a add r2,r2,r3 + 101d030: 10800003 ldbu r2,0(r2) + 101d034: 1007883a mov r3,r2 + 101d038: 008040b4 movhi r2,258 + 101d03c: 10952304 addi r2,r2,21644 + 101d040: 10800017 ldw r2,0(r2) + 101d044: 10800d43 ldbu r2,53(r2) + 101d048: 0084303a nor r2,zero,r2 + 101d04c: 1884703a and r2,r3,r2 + 101d050: 1007883a mov r3,r2 + 101d054: 008040b4 movhi r2,258 + 101d058: 10952044 addi r2,r2,21633 + 101d05c: 1105883a add r2,r2,r4 + 101d060: 10c00005 stb r3,0(r2) + if (OSRdyTbl[y] == 0) { + 101d064: e0fffe03 ldbu r3,-8(fp) + 101d068: 008040b4 movhi r2,258 + 101d06c: 10952044 addi r2,r2,21633 + 101d070: 10c5883a add r2,r2,r3 + 101d074: 10800003 ldbu r2,0(r2) + 101d078: 10803fcc andi r2,r2,255 + 101d07c: 1004c03a cmpne r2,r2,zero + 101d080: 10000e1e bne r2,zero,101d0bc + OSRdyGrp &= ~OSTCBCur->OSTCBBitY; + 101d084: 008040b4 movhi r2,258 + 101d088: 10952304 addi r2,r2,21644 + 101d08c: 10800017 ldw r2,0(r2) + 101d090: 10800d83 ldbu r2,54(r2) + 101d094: 0084303a nor r2,zero,r2 + 101d098: 1007883a mov r3,r2 + 101d09c: 008040b4 movhi r2,258 + 101d0a0: 10952004 addi r2,r2,21632 + 101d0a4: 10800003 ldbu r2,0(r2) + 101d0a8: 1884703a and r2,r3,r2 + 101d0ac: 1007883a mov r3,r2 + 101d0b0: 008040b4 movhi r2,258 + 101d0b4: 10952004 addi r2,r2,21632 + 101d0b8: 10c00005 stb r3,0(r2) + } + OSTCBCur->OSTCBDly = ticks; /* Load ticks in TCB */ + 101d0bc: 008040b4 movhi r2,258 + 101d0c0: 10952304 addi r2,r2,21644 + 101d0c4: 10c00017 ldw r3,0(r2) + 101d0c8: e0bfff0b ldhu r2,-4(fp) + 101d0cc: 18800b8d sth r2,46(r3) + 101d0d0: e0bffd17 ldw r2,-12(fp) + 101d0d4: e0bffb15 stw r2,-20(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 101d0d8: e0bffb17 ldw r2,-20(fp) + 101d0dc: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + OS_Sched(); /* Find next task to run! */ + 101d0e0: 1016cb80 call 1016cb8 + } +} + 101d0e4: e037883a mov sp,fp + 101d0e8: dfc00117 ldw ra,4(sp) + 101d0ec: df000017 ldw fp,0(sp) + 101d0f0: dec00204 addi sp,sp,8 + 101d0f4: f800283a ret + +0101d0f8 : +********************************************************************************************************* +*/ + +#if OS_TIME_DLY_HMSM_EN > 0 +INT8U OSTimeDlyHMSM (INT8U hours, INT8U minutes, INT8U seconds, INT16U ms) +{ + 101d0f8: defff604 addi sp,sp,-40 + 101d0fc: dfc00915 stw ra,36(sp) + 101d100: df000815 stw fp,32(sp) + 101d104: dc000715 stw r16,28(sp) + 101d108: df000704 addi fp,sp,28 + 101d10c: e13ffb05 stb r4,-20(fp) + 101d110: e17ffc05 stb r5,-16(fp) + 101d114: e1bffd05 stb r6,-12(fp) + 101d118: e1fffe0d sth r7,-8(fp) + INT32U ticks; + INT16U loops; + + + if (OSIntNesting > 0) { /* See if trying to call from an ISR */ + 101d11c: 008040b4 movhi r2,258 + 101d120: 10952204 addi r2,r2,21640 + 101d124: 10800003 ldbu r2,0(r2) + 101d128: 10803fcc andi r2,r2,255 + 101d12c: 1005003a cmpeq r2,r2,zero + 101d130: 1000031e bne r2,zero,101d140 + return (OS_ERR_TIME_DLY_ISR); + 101d134: 00801544 movi r2,85 + 101d138: e0bfff15 stw r2,-4(fp) + 101d13c: 00004406 br 101d250 + } +#if OS_ARG_CHK_EN > 0 + if (hours == 0) { + 101d140: e0bffb03 ldbu r2,-20(fp) + 101d144: 1004c03a cmpne r2,r2,zero + 101d148: 10000c1e bne r2,zero,101d17c + if (minutes == 0) { + 101d14c: e0bffc03 ldbu r2,-16(fp) + 101d150: 1004c03a cmpne r2,r2,zero + 101d154: 1000091e bne r2,zero,101d17c + if (seconds == 0) { + 101d158: e0bffd03 ldbu r2,-12(fp) + 101d15c: 1004c03a cmpne r2,r2,zero + 101d160: 1000061e bne r2,zero,101d17c + if (ms == 0) { + 101d164: e0bffe0b ldhu r2,-8(fp) + 101d168: 1004c03a cmpne r2,r2,zero + 101d16c: 1000031e bne r2,zero,101d17c + return (OS_ERR_TIME_ZERO_DLY); + 101d170: 00801504 movi r2,84 + 101d174: e0bfff15 stw r2,-4(fp) + 101d178: 00003506 br 101d250 + } + } + } + } + if (minutes > 59) { + 101d17c: e0bffc03 ldbu r2,-16(fp) + 101d180: 10800f30 cmpltui r2,r2,60 + 101d184: 1000031e bne r2,zero,101d194 + return (OS_ERR_TIME_INVALID_MINUTES); /* Validate arguments to be within range */ + 101d188: 00801444 movi r2,81 + 101d18c: e0bfff15 stw r2,-4(fp) + 101d190: 00002f06 br 101d250 + } + if (seconds > 59) { + 101d194: e0bffd03 ldbu r2,-12(fp) + 101d198: 10800f30 cmpltui r2,r2,60 + 101d19c: 1000031e bne r2,zero,101d1ac + return (OS_ERR_TIME_INVALID_SECONDS); + 101d1a0: 00801484 movi r2,82 + 101d1a4: e0bfff15 stw r2,-4(fp) + 101d1a8: 00002906 br 101d250 + } + if (ms > 999) { + 101d1ac: e0bffe0b ldhu r2,-8(fp) + 101d1b0: 1080fa30 cmpltui r2,r2,1000 + 101d1b4: 1000031e bne r2,zero,101d1c4 + return (OS_ERR_TIME_INVALID_MS); + 101d1b8: 008014c4 movi r2,83 + 101d1bc: e0bfff15 stw r2,-4(fp) + 101d1c0: 00002306 br 101d250 + } +#endif + /* Compute the total number of clock ticks required.. */ + /* .. (rounded to the nearest tick) */ + ticks = ((INT32U)hours * 3600L + (INT32U)minutes * 60L + (INT32U)seconds) * OS_TICKS_PER_SEC + 101d1c4: e0bffb03 ldbu r2,-20(fp) + 101d1c8: 10c38424 muli r3,r2,3600 + 101d1cc: e0bffc03 ldbu r2,-16(fp) + 101d1d0: 10800f24 muli r2,r2,60 + 101d1d4: 1887883a add r3,r3,r2 + 101d1d8: e0bffd03 ldbu r2,-12(fp) + 101d1dc: 1885883a add r2,r3,r2 + 101d1e0: 1400fa24 muli r16,r2,1000 + 101d1e4: e0bffe0b ldhu r2,-8(fp) + 101d1e8: 1100fa24 muli r4,r2,1000 + 101d1ec: 0140fa04 movi r5,1000 + 101d1f0: 1013c340 call 1013c34 <__udivsi3> + 101d1f4: 8085883a add r2,r16,r2 + 101d1f8: e0bffa15 stw r2,-24(fp) + + OS_TICKS_PER_SEC * ((INT32U)ms + 500L / OS_TICKS_PER_SEC) / 1000L; + loops = (INT16U)(ticks >> 16); /* Compute the integral number of 65536 tick delays */ + 101d1fc: e0bffa17 ldw r2,-24(fp) + 101d200: 1004d43a srli r2,r2,16 + 101d204: e0bff90d sth r2,-28(fp) + ticks = ticks & 0xFFFFL; /* Obtain the fractional number of ticks */ + 101d208: e0bffa17 ldw r2,-24(fp) + 101d20c: 10bfffcc andi r2,r2,65535 + 101d210: e0bffa15 stw r2,-24(fp) + OSTimeDly((INT16U)ticks); + 101d214: e0bffa17 ldw r2,-24(fp) + 101d218: 113fffcc andi r4,r2,65535 + 101d21c: 101cfac0 call 101cfac + while (loops > 0) { + 101d220: 00000706 br 101d240 + OSTimeDly((INT16U)32768u); + 101d224: 01200014 movui r4,32768 + 101d228: 101cfac0 call 101cfac + OSTimeDly((INT16U)32768u); + 101d22c: 01200014 movui r4,32768 + 101d230: 101cfac0 call 101cfac + loops--; + 101d234: e0bff90b ldhu r2,-28(fp) + 101d238: 10bfffc4 addi r2,r2,-1 + 101d23c: e0bff90d sth r2,-28(fp) + ticks = ((INT32U)hours * 3600L + (INT32U)minutes * 60L + (INT32U)seconds) * OS_TICKS_PER_SEC + + OS_TICKS_PER_SEC * ((INT32U)ms + 500L / OS_TICKS_PER_SEC) / 1000L; + loops = (INT16U)(ticks >> 16); /* Compute the integral number of 65536 tick delays */ + ticks = ticks & 0xFFFFL; /* Obtain the fractional number of ticks */ + OSTimeDly((INT16U)ticks); + while (loops > 0) { + 101d240: e0bff90b ldhu r2,-28(fp) + 101d244: 1004c03a cmpne r2,r2,zero + 101d248: 103ff61e bne r2,zero,101d224 + OSTimeDly((INT16U)32768u); + OSTimeDly((INT16U)32768u); + loops--; + } + return (OS_ERR_NONE); + 101d24c: e03fff15 stw zero,-4(fp) + 101d250: e0bfff17 ldw r2,-4(fp) +} + 101d254: e037883a mov sp,fp + 101d258: dfc00217 ldw ra,8(sp) + 101d25c: df000117 ldw fp,4(sp) + 101d260: dc000017 ldw r16,0(sp) + 101d264: dec00304 addi sp,sp,12 + 101d268: f800283a ret + +0101d26c : +********************************************************************************************************* +*/ + +#if OS_TIME_DLY_RESUME_EN > 0 +INT8U OSTimeDlyResume (INT8U prio) +{ + 101d26c: defff404 addi sp,sp,-48 + 101d270: dfc00b15 stw ra,44(sp) + 101d274: df000a15 stw fp,40(sp) + 101d278: df000a04 addi fp,sp,40 + 101d27c: e13ffe05 stb r4,-8(fp) + OS_TCB *ptcb; +#if OS_CRITICAL_METHOD == 3 /* Storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 101d280: e03ffc15 stw zero,-16(fp) +#endif + + + + if (prio >= OS_LOWEST_PRIO) { + 101d284: e0bffe03 ldbu r2,-8(fp) + 101d288: 10800530 cmpltui r2,r2,20 + 101d28c: 1000031e bne r2,zero,101d29c + return (OS_ERR_PRIO_INVALID); + 101d290: 00800a84 movi r2,42 + 101d294: e0bfff15 stw r2,-4(fp) + 101d298: 00007206 br 101d464 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 101d29c: 0005303a rdctl r2,status + 101d2a0: e0bffb15 stw r2,-20(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 101d2a4: e0fffb17 ldw r3,-20(fp) + 101d2a8: 00bfff84 movi r2,-2 + 101d2ac: 1884703a and r2,r3,r2 + 101d2b0: 1001703a wrctl status,r2 + + return context; + 101d2b4: e0bffb17 ldw r2,-20(fp) + } + OS_ENTER_CRITICAL(); + 101d2b8: e0bffc15 stw r2,-16(fp) + ptcb = OSTCBPrioTbl[prio]; /* Make sure that task exist */ + 101d2bc: e0bffe03 ldbu r2,-8(fp) + 101d2c0: 00c040f4 movhi r3,259 + 101d2c4: 18f3b104 addi r3,r3,-12604 + 101d2c8: 1085883a add r2,r2,r2 + 101d2cc: 1085883a add r2,r2,r2 + 101d2d0: 10c5883a add r2,r2,r3 + 101d2d4: 10800017 ldw r2,0(r2) + 101d2d8: e0bffd15 stw r2,-12(fp) + if (ptcb == (OS_TCB *)0) { + 101d2dc: e0bffd17 ldw r2,-12(fp) + 101d2e0: 1004c03a cmpne r2,r2,zero + 101d2e4: 1000071e bne r2,zero,101d304 + 101d2e8: e0bffc17 ldw r2,-16(fp) + 101d2ec: e0bffa15 stw r2,-24(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 101d2f0: e0bffa17 ldw r2,-24(fp) + 101d2f4: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_NOT_EXIST); /* The task does not exist */ + 101d2f8: 008010c4 movi r2,67 + 101d2fc: e0bfff15 stw r2,-4(fp) + 101d300: 00005806 br 101d464 + } + if (ptcb == OS_TCB_RESERVED) { + 101d304: e0bffd17 ldw r2,-12(fp) + 101d308: 10800058 cmpnei r2,r2,1 + 101d30c: 1000071e bne r2,zero,101d32c + 101d310: e0bffc17 ldw r2,-16(fp) + 101d314: e0bff915 stw r2,-28(fp) + 101d318: e0bff917 ldw r2,-28(fp) + 101d31c: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_NOT_EXIST); /* The task does not exist */ + 101d320: 008010c4 movi r2,67 + 101d324: e0bfff15 stw r2,-4(fp) + 101d328: 00004e06 br 101d464 + } + if (ptcb->OSTCBDly == 0) { /* See if task is delayed */ + 101d32c: e0bffd17 ldw r2,-12(fp) + 101d330: 10800b8b ldhu r2,46(r2) + 101d334: 10bfffcc andi r2,r2,65535 + 101d338: 1004c03a cmpne r2,r2,zero + 101d33c: 1000071e bne r2,zero,101d35c + 101d340: e0bffc17 ldw r2,-16(fp) + 101d344: e0bff815 stw r2,-32(fp) + 101d348: e0bff817 ldw r2,-32(fp) + 101d34c: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_TIME_NOT_DLY); /* Indicate that task was not delayed */ + 101d350: 00801404 movi r2,80 + 101d354: e0bfff15 stw r2,-4(fp) + 101d358: 00004206 br 101d464 + } + + ptcb->OSTCBDly = 0; /* Clear the time delay */ + 101d35c: e0bffd17 ldw r2,-12(fp) + 101d360: 10000b8d sth zero,46(r2) + if ((ptcb->OSTCBStat & OS_STAT_PEND_ANY) != OS_STAT_RDY) { + 101d364: e0bffd17 ldw r2,-12(fp) + 101d368: 10800c03 ldbu r2,48(r2) + 101d36c: 10803fcc andi r2,r2,255 + 101d370: 10800dcc andi r2,r2,55 + 101d374: 1005003a cmpeq r2,r2,zero + 101d378: 10000b1e bne r2,zero,101d3a8 + ptcb->OSTCBStat &= ~OS_STAT_PEND_ANY; /* Yes, Clear status flag */ + 101d37c: e0bffd17 ldw r2,-12(fp) + 101d380: 10c00c03 ldbu r3,48(r2) + 101d384: 00bff204 movi r2,-56 + 101d388: 1884703a and r2,r3,r2 + 101d38c: 1007883a mov r3,r2 + 101d390: e0bffd17 ldw r2,-12(fp) + 101d394: 10c00c05 stb r3,48(r2) + ptcb->OSTCBStatPend = OS_STAT_PEND_TO; /* Indicate PEND timeout */ + 101d398: e0fffd17 ldw r3,-12(fp) + 101d39c: 00800044 movi r2,1 + 101d3a0: 18800c45 stb r2,49(r3) + 101d3a4: 00000206 br 101d3b0 + } else { + ptcb->OSTCBStatPend = OS_STAT_PEND_OK; + 101d3a8: e0bffd17 ldw r2,-12(fp) + 101d3ac: 10000c45 stb zero,49(r2) + } + if ((ptcb->OSTCBStat & OS_STAT_SUSPEND) == OS_STAT_RDY) { /* Is task suspended? */ + 101d3b0: e0bffd17 ldw r2,-12(fp) + 101d3b4: 10800c03 ldbu r2,48(r2) + 101d3b8: 10803fcc andi r2,r2,255 + 101d3bc: 1080020c andi r2,r2,8 + 101d3c0: 1004c03a cmpne r2,r2,zero + 101d3c4: 1000221e bne r2,zero,101d450 + OSRdyGrp |= ptcb->OSTCBBitY; /* No, Make ready */ + 101d3c8: e0bffd17 ldw r2,-12(fp) + 101d3cc: 10c00d83 ldbu r3,54(r2) + 101d3d0: 008040b4 movhi r2,258 + 101d3d4: 10952004 addi r2,r2,21632 + 101d3d8: 10800003 ldbu r2,0(r2) + 101d3dc: 1884b03a or r2,r3,r2 + 101d3e0: 1007883a mov r3,r2 + 101d3e4: 008040b4 movhi r2,258 + 101d3e8: 10952004 addi r2,r2,21632 + 101d3ec: 10c00005 stb r3,0(r2) + OSRdyTbl[ptcb->OSTCBY] |= ptcb->OSTCBBitX; + 101d3f0: e0bffd17 ldw r2,-12(fp) + 101d3f4: 10800d03 ldbu r2,52(r2) + 101d3f8: 11003fcc andi r4,r2,255 + 101d3fc: e0bffd17 ldw r2,-12(fp) + 101d400: 10800d03 ldbu r2,52(r2) + 101d404: 10c03fcc andi r3,r2,255 + 101d408: 008040b4 movhi r2,258 + 101d40c: 10952044 addi r2,r2,21633 + 101d410: 10c5883a add r2,r2,r3 + 101d414: 10c00003 ldbu r3,0(r2) + 101d418: e0bffd17 ldw r2,-12(fp) + 101d41c: 10800d43 ldbu r2,53(r2) + 101d420: 1884b03a or r2,r3,r2 + 101d424: 1007883a mov r3,r2 + 101d428: 008040b4 movhi r2,258 + 101d42c: 10952044 addi r2,r2,21633 + 101d430: 1105883a add r2,r2,r4 + 101d434: 10c00005 stb r3,0(r2) + 101d438: e0bffc17 ldw r2,-16(fp) + 101d43c: e0bff715 stw r2,-36(fp) + 101d440: e0bff717 ldw r2,-36(fp) + 101d444: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + OS_Sched(); /* See if this is new highest priority */ + 101d448: 1016cb80 call 1016cb8 + 101d44c: 00000406 br 101d460 + 101d450: e0bffc17 ldw r2,-16(fp) + 101d454: e0bff615 stw r2,-40(fp) + 101d458: e0bff617 ldw r2,-40(fp) + 101d45c: 1001703a wrctl status,r2 + } else { + OS_EXIT_CRITICAL(); /* Task may be suspended */ + } + return (OS_ERR_NONE); + 101d460: e03fff15 stw zero,-4(fp) + 101d464: e0bfff17 ldw r2,-4(fp) +} + 101d468: e037883a mov sp,fp + 101d46c: dfc00117 ldw ra,4(sp) + 101d470: df000017 ldw fp,0(sp) + 101d474: dec00204 addi sp,sp,8 + 101d478: f800283a ret + +0101d47c : +********************************************************************************************************* +*/ + +#if OS_TIME_GET_SET_EN > 0 +INT32U OSTimeGet (void) +{ + 101d47c: defffb04 addi sp,sp,-20 + 101d480: df000415 stw fp,16(sp) + 101d484: df000404 addi fp,sp,16 + INT32U ticks; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 101d488: e03ffe15 stw zero,-8(fp) +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 101d48c: 0005303a rdctl r2,status + 101d490: e0bffd15 stw r2,-12(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 101d494: e0fffd17 ldw r3,-12(fp) + 101d498: 00bfff84 movi r2,-2 + 101d49c: 1884703a and r2,r3,r2 + 101d4a0: 1001703a wrctl status,r2 + + return context; + 101d4a4: e0bffd17 ldw r2,-12(fp) +#endif + + + + OS_ENTER_CRITICAL(); + 101d4a8: e0bffe15 stw r2,-8(fp) + ticks = OSTime; + 101d4ac: 008040b4 movhi r2,258 + 101d4b0: 10952404 addi r2,r2,21648 + 101d4b4: 10800017 ldw r2,0(r2) + 101d4b8: e0bfff15 stw r2,-4(fp) + 101d4bc: e0bffe17 ldw r2,-8(fp) + 101d4c0: e0bffc15 stw r2,-16(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 101d4c4: e0bffc17 ldw r2,-16(fp) + 101d4c8: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (ticks); + 101d4cc: e0bfff17 ldw r2,-4(fp) +} + 101d4d0: e037883a mov sp,fp + 101d4d4: df000017 ldw fp,0(sp) + 101d4d8: dec00104 addi sp,sp,4 + 101d4dc: f800283a ret + +0101d4e0 : +********************************************************************************************************* +*/ + +#if OS_TIME_GET_SET_EN > 0 +void OSTimeSet (INT32U ticks) +{ + 101d4e0: defffb04 addi sp,sp,-20 + 101d4e4: df000415 stw fp,16(sp) + 101d4e8: df000404 addi fp,sp,16 + 101d4ec: e13fff15 stw r4,-4(fp) +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 101d4f0: e03ffe15 stw zero,-8(fp) +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 101d4f4: 0005303a rdctl r2,status + 101d4f8: e0bffd15 stw r2,-12(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 101d4fc: e0fffd17 ldw r3,-12(fp) + 101d500: 00bfff84 movi r2,-2 + 101d504: 1884703a and r2,r3,r2 + 101d508: 1001703a wrctl status,r2 + + return context; + 101d50c: e0bffd17 ldw r2,-12(fp) +#endif + + + + OS_ENTER_CRITICAL(); + 101d510: e0bffe15 stw r2,-8(fp) + OSTime = ticks; + 101d514: 00c040b4 movhi r3,258 + 101d518: 18d52404 addi r3,r3,21648 + 101d51c: e0bfff17 ldw r2,-4(fp) + 101d520: 18800015 stw r2,0(r3) + 101d524: e0bffe17 ldw r2,-8(fp) + 101d528: e0bffc15 stw r2,-16(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 101d52c: e0bffc17 ldw r2,-16(fp) + 101d530: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); +} + 101d534: e037883a mov sp,fp + 101d538: df000017 ldw fp,0(sp) + 101d53c: dec00104 addi sp,sp,4 + 101d540: f800283a ret + +0101d544 : + * The "base" parameter is ignored and only + * present for backwards-compatibility. + */ + +void alt_irq_init ( const void* base ) +{ + 101d544: defffd04 addi sp,sp,-12 + 101d548: dfc00215 stw ra,8(sp) + 101d54c: df000115 stw fp,4(sp) + 101d550: df000104 addi fp,sp,4 + 101d554: e13fff15 stw r4,-4(fp) + ALTERA_NIOS2_QSYS_IRQ_INIT ( CPU, cpu); + 101d558: 101ffec0 call 101ffec + * alt_irq_cpu_enable_interrupts() enables the CPU to start taking interrupts. + */ +static ALT_INLINE void ALT_ALWAYS_INLINE + alt_irq_cpu_enable_interrupts () +{ + NIOS2_WRITE_STATUS(NIOS2_STATUS_PIE_MSK + 101d55c: 00800044 movi r2,1 + 101d560: 1001703a wrctl status,r2 + alt_irq_cpu_enable_interrupts(); +} + 101d564: e037883a mov sp,fp + 101d568: dfc00117 ldw ra,4(sp) + 101d56c: df000017 ldw fp,0(sp) + 101d570: dec00204 addi sp,sp,8 + 101d574: f800283a ret + +0101d578 : + * Initialize the non-interrupt controller devices. + * Called after alt_irq_init(). + */ + +void alt_sys_init( void ) +{ + 101d578: defffe04 addi sp,sp,-8 + 101d57c: dfc00115 stw ra,4(sp) + 101d580: df000015 stw fp,0(sp) + 101d584: d839883a mov fp,sp + ALTERA_AVALON_TIMER_INIT ( SYS_CLK_TIMER, sys_clk_timer); + 101d588: 01008034 movhi r4,512 + 101d58c: 21041004 addi r4,r4,4160 + 101d590: 000b883a mov r5,zero + 101d594: 01800044 movi r6,1 + 101d598: 01c0fa04 movi r7,1000 + 101d59c: 101e4040 call 101e404 + ALTERA_AVALON_JTAG_UART_INIT ( JTAG_UART_0, jtag_uart_0); + 101d5a0: 010040b4 movhi r4,258 + 101d5a4: 21096904 addi r4,r4,9636 + 101d5a8: 000b883a mov r5,zero + 101d5ac: 01800384 movi r6,14 + 101d5b0: 101d7800 call 101d780 + 101d5b4: 010040b4 movhi r4,258 + 101d5b8: 21095f04 addi r4,r4,9596 + 101d5bc: 101d6000 call 101d600 + ALTERA_AVALON_SYSID_QSYS_INIT ( SYSID, sysid); + ALTERA_AVALON_UART_INIT ( UART_0, uart_0); + 101d5c0: 010040b4 movhi r4,258 + 101d5c4: 210d8404 addi r4,r4,13840 + 101d5c8: 000b883a mov r5,zero + 101d5cc: 01800104 movi r6,4 + 101d5d0: 101e5840 call 101e584 + 101d5d4: 010040b4 movhi r4,258 + 101d5d8: 210d7a04 addi r4,r4,13800 + 101d5dc: 101d6000 call 101d600 + ALTERA_UP_AVALON_RS232_INIT ( RS232_MOTOR, rs232_motor); + 101d5e0: 010040b4 movhi r4,258 + 101d5e4: 210dae04 addi r4,r4,14008 + 101d5e8: 101d6000 call 101d600 +} + 101d5ec: e037883a mov sp,fp + 101d5f0: dfc00117 ldw ra,4(sp) + 101d5f4: df000017 ldw fp,0(sp) + 101d5f8: dec00204 addi sp,sp,8 + 101d5fc: f800283a ret + +0101d600 : + */ + +extern int alt_fs_reg (alt_dev* dev); + +static ALT_INLINE int alt_dev_reg (alt_dev* dev) +{ + 101d600: defffd04 addi sp,sp,-12 + 101d604: dfc00215 stw ra,8(sp) + 101d608: df000115 stw fp,4(sp) + 101d60c: df000104 addi fp,sp,4 + 101d610: e13fff15 stw r4,-4(fp) + extern alt_llist alt_dev_list; + + return alt_dev_llist_insert ((alt_dev_llist*) dev, &alt_dev_list); + 101d614: e13fff17 ldw r4,-4(fp) + 101d618: 014040b4 movhi r5,258 + 101d61c: 294dce04 addi r5,r5,14136 + 101d620: 101f5e40 call 101f5e4 +} + 101d624: e037883a mov sp,fp + 101d628: dfc00117 ldw ra,4(sp) + 101d62c: df000017 ldw fp,0(sp) + 101d630: dec00204 addi sp,sp,8 + 101d634: f800283a ret + +0101d638 : + * + */ + +int +altera_avalon_jtag_uart_read_fd(alt_fd* fd, char* buffer, int space) +{ + 101d638: defffa04 addi sp,sp,-24 + 101d63c: dfc00515 stw ra,20(sp) + 101d640: df000415 stw fp,16(sp) + 101d644: df000404 addi fp,sp,16 + 101d648: e13ffd15 stw r4,-12(fp) + 101d64c: e17ffe15 stw r5,-8(fp) + 101d650: e1bfff15 stw r6,-4(fp) + altera_avalon_jtag_uart_dev* dev = (altera_avalon_jtag_uart_dev*) fd->dev; + 101d654: e0bffd17 ldw r2,-12(fp) + 101d658: 10800017 ldw r2,0(r2) + 101d65c: e0bffc15 stw r2,-16(fp) + + return altera_avalon_jtag_uart_read(&dev->state, buffer, space, + 101d660: e0bffc17 ldw r2,-16(fp) + 101d664: 11000a04 addi r4,r2,40 + 101d668: e0bffd17 ldw r2,-12(fp) + 101d66c: 11c00217 ldw r7,8(r2) + 101d670: e17ffe17 ldw r5,-8(fp) + 101d674: e1bfff17 ldw r6,-4(fp) + 101d678: 101ddf40 call 101ddf4 + fd->fd_flags); +} + 101d67c: e037883a mov sp,fp + 101d680: dfc00117 ldw ra,4(sp) + 101d684: df000017 ldw fp,0(sp) + 101d688: dec00204 addi sp,sp,8 + 101d68c: f800283a ret + +0101d690 : + +int +altera_avalon_jtag_uart_write_fd(alt_fd* fd, const char* buffer, int space) +{ + 101d690: defffa04 addi sp,sp,-24 + 101d694: dfc00515 stw ra,20(sp) + 101d698: df000415 stw fp,16(sp) + 101d69c: df000404 addi fp,sp,16 + 101d6a0: e13ffd15 stw r4,-12(fp) + 101d6a4: e17ffe15 stw r5,-8(fp) + 101d6a8: e1bfff15 stw r6,-4(fp) + altera_avalon_jtag_uart_dev* dev = (altera_avalon_jtag_uart_dev*) fd->dev; + 101d6ac: e0bffd17 ldw r2,-12(fp) + 101d6b0: 10800017 ldw r2,0(r2) + 101d6b4: e0bffc15 stw r2,-16(fp) + + return altera_avalon_jtag_uart_write(&dev->state, buffer, space, + 101d6b8: e0bffc17 ldw r2,-16(fp) + 101d6bc: 11000a04 addi r4,r2,40 + 101d6c0: e0bffd17 ldw r2,-12(fp) + 101d6c4: 11c00217 ldw r7,8(r2) + 101d6c8: e17ffe17 ldw r5,-8(fp) + 101d6cc: e1bfff17 ldw r6,-4(fp) + 101d6d0: 101e0b40 call 101e0b4 + fd->fd_flags); +} + 101d6d4: e037883a mov sp,fp + 101d6d8: dfc00117 ldw ra,4(sp) + 101d6dc: df000017 ldw fp,0(sp) + 101d6e0: dec00204 addi sp,sp,8 + 101d6e4: f800283a ret + +0101d6e8 : + +#ifndef ALTERA_AVALON_JTAG_UART_SMALL + +int +altera_avalon_jtag_uart_close_fd(alt_fd* fd) +{ + 101d6e8: defffc04 addi sp,sp,-16 + 101d6ec: dfc00315 stw ra,12(sp) + 101d6f0: df000215 stw fp,8(sp) + 101d6f4: df000204 addi fp,sp,8 + 101d6f8: e13fff15 stw r4,-4(fp) + altera_avalon_jtag_uart_dev* dev = (altera_avalon_jtag_uart_dev*) fd->dev; + 101d6fc: e0bfff17 ldw r2,-4(fp) + 101d700: 10800017 ldw r2,0(r2) + 101d704: e0bffe15 stw r2,-8(fp) + + return altera_avalon_jtag_uart_close(&dev->state, fd->fd_flags); + 101d708: e0bffe17 ldw r2,-8(fp) + 101d70c: 11000a04 addi r4,r2,40 + 101d710: e0bfff17 ldw r2,-4(fp) + 101d714: 11400217 ldw r5,8(r2) + 101d718: 101dc8c0 call 101dc8c +} + 101d71c: e037883a mov sp,fp + 101d720: dfc00117 ldw ra,4(sp) + 101d724: df000017 ldw fp,0(sp) + 101d728: dec00204 addi sp,sp,8 + 101d72c: f800283a ret + +0101d730 : + +int +altera_avalon_jtag_uart_ioctl_fd(alt_fd* fd, int req, void* arg) +{ + 101d730: defffa04 addi sp,sp,-24 + 101d734: dfc00515 stw ra,20(sp) + 101d738: df000415 stw fp,16(sp) + 101d73c: df000404 addi fp,sp,16 + 101d740: e13ffd15 stw r4,-12(fp) + 101d744: e17ffe15 stw r5,-8(fp) + 101d748: e1bfff15 stw r6,-4(fp) + altera_avalon_jtag_uart_dev* dev = (altera_avalon_jtag_uart_dev*) fd->dev; + 101d74c: e0bffd17 ldw r2,-12(fp) + 101d750: 10800017 ldw r2,0(r2) + 101d754: e0bffc15 stw r2,-16(fp) + + return altera_avalon_jtag_uart_ioctl(&dev->state, req, arg); + 101d758: e0bffc17 ldw r2,-16(fp) + 101d75c: 11000a04 addi r4,r2,40 + 101d760: e17ffe17 ldw r5,-8(fp) + 101d764: e1bfff17 ldw r6,-4(fp) + 101d768: 101dd000 call 101dd00 +} + 101d76c: e037883a mov sp,fp + 101d770: dfc00117 ldw ra,4(sp) + 101d774: df000017 ldw fp,0(sp) + 101d778: dec00204 addi sp,sp,8 + 101d77c: f800283a ret + +0101d780 : + * Return 1 on sucessful IRQ register and 0 on failure. + */ + +void altera_avalon_jtag_uart_init(altera_avalon_jtag_uart_state* sp, + int irq_controller_id, int irq) +{ + 101d780: defff504 addi sp,sp,-44 + 101d784: dfc00a15 stw ra,40(sp) + 101d788: df000915 stw fp,36(sp) + 101d78c: df000904 addi fp,sp,36 + 101d790: e13ffd15 stw r4,-12(fp) + 101d794: e17ffe15 stw r5,-8(fp) + 101d798: e1bfff15 stw r6,-4(fp) + ALT_FLAG_CREATE(&sp->events, 0); + 101d79c: e0bffd17 ldw r2,-12(fp) + 101d7a0: 10800c04 addi r2,r2,48 + 101d7a4: e0bffb15 stw r2,-20(fp) + 101d7a8: e03ffc0d sth zero,-16(fp) + +static ALT_INLINE int ALT_ALWAYS_INLINE alt_flag_create (OS_FLAG_GRP** pgroup, + OS_FLAGS flags) +{ + INT8U err; + *pgroup = OSFlagCreate (flags, &err); + 101d7ac: e13ffc0b ldhu r4,-16(fp) + 101d7b0: e17ffc84 addi r5,fp,-14 + 101d7b4: 10178600 call 1017860 + 101d7b8: 1007883a mov r3,r2 + 101d7bc: e0bffb17 ldw r2,-20(fp) + 101d7c0: 10c00015 stw r3,0(r2) + ALT_SEM_CREATE(&sp->read_lock, 1); + 101d7c4: e0bffd17 ldw r2,-12(fp) + 101d7c8: 10800a04 addi r2,r2,40 + 101d7cc: e0bff915 stw r2,-28(fp) + 101d7d0: 00800044 movi r2,1 + 101d7d4: e0bffa0d sth r2,-24(fp) + 101d7d8: e13ffa0b ldhu r4,-24(fp) + 101d7dc: 101aa640 call 101aa64 + 101d7e0: 1007883a mov r3,r2 + 101d7e4: e0bff917 ldw r2,-28(fp) + 101d7e8: 10c00015 stw r3,0(r2) + ALT_SEM_CREATE(&sp->write_lock, 1); + 101d7ec: e0bffd17 ldw r2,-12(fp) + 101d7f0: 10800b04 addi r2,r2,44 + 101d7f4: e0bff715 stw r2,-36(fp) + 101d7f8: 00800044 movi r2,1 + 101d7fc: e0bff80d sth r2,-32(fp) + 101d800: e13ff80b ldhu r4,-32(fp) + 101d804: 101aa640 call 101aa64 + 101d808: 1007883a mov r3,r2 + 101d80c: e0bff717 ldw r2,-36(fp) + 101d810: 10c00015 stw r3,0(r2) + + /* enable read interrupts at the device */ + sp->irq_enable = ALTERA_AVALON_JTAG_UART_CONTROL_RE_MSK; + 101d814: e0fffd17 ldw r3,-12(fp) + 101d818: 00800044 movi r2,1 + 101d81c: 18800815 stw r2,32(r3) + + IOWR_ALTERA_AVALON_JTAG_UART_CONTROL(sp->base, sp->irq_enable); + 101d820: e0bffd17 ldw r2,-12(fp) + 101d824: 10800017 ldw r2,0(r2) + 101d828: 11000104 addi r4,r2,4 + 101d82c: e0bffd17 ldw r2,-12(fp) + 101d830: 10800817 ldw r2,32(r2) + 101d834: 1007883a mov r3,r2 + 101d838: 2005883a mov r2,r4 + 101d83c: 10c00035 stwio r3,0(r2) + /* register the interrupt handler */ +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT + alt_ic_isr_register(irq_controller_id, irq, altera_avalon_jtag_uart_irq, + sp, NULL); +#else + alt_irq_register(irq, sp, altera_avalon_jtag_uart_irq); + 101d840: e13fff17 ldw r4,-4(fp) + 101d844: e17ffd17 ldw r5,-12(fp) + 101d848: 018040b4 movhi r6,258 + 101d84c: 31b62c04 addi r6,r6,-10064 + 101d850: 101f9c00 call 101f9c0 +#endif + + /* Register an alarm to go off every second to check for presence of host */ + sp->host_inactive = 0; + 101d854: e0bffd17 ldw r2,-12(fp) + 101d858: 10000915 stw zero,36(r2) + + if (alt_alarm_start(&sp->alarm, alt_ticks_per_second(), + 101d85c: e0bffd17 ldw r2,-12(fp) + 101d860: 11000204 addi r4,r2,8 + * Obtain the system clock rate in ticks/s. + */ + +static ALT_INLINE alt_u32 ALT_ALWAYS_INLINE alt_ticks_per_second (void) +{ + return _alt_tick_rate; + 101d864: 008040b4 movhi r2,258 + 101d868: 10952904 addi r2,r2,21668 + 101d86c: 10800017 ldw r2,0(r2) + 101d870: 100b883a mov r5,r2 + 101d874: 018040b4 movhi r6,258 + 101d878: 31b6de04 addi r6,r6,-9352 + 101d87c: e1fffd17 ldw r7,-12(fp) + 101d880: 101f44c0 call 101f44c + 101d884: 1004403a cmpge r2,r2,zero + 101d888: 1000041e bne r2,zero,101d89c + &altera_avalon_jtag_uart_timeout, sp) < 0) + { + /* If we can't set the alarm then record "don't know if host present" + * and behave as though the host is present. + */ + sp->timeout = INT_MAX; + 101d88c: e0fffd17 ldw r3,-12(fp) + 101d890: 00a00034 movhi r2,32768 + 101d894: 10bfffc4 addi r2,r2,-1 + 101d898: 18800115 stw r2,4(r3) + } + + /* ALT_LOG - see altera_hal/HAL/inc/sys/alt_log_printf.h */ + ALT_LOG_JTAG_UART_ALARM_REGISTER(sp, sp->base); +} + 101d89c: e037883a mov sp,fp + 101d8a0: dfc00117 ldw ra,4(sp) + 101d8a4: df000017 ldw fp,0(sp) + 101d8a8: dec00204 addi sp,sp,8 + 101d8ac: f800283a ret + +0101d8b0 : +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT +static void altera_avalon_jtag_uart_irq(void* context) +#else +static void altera_avalon_jtag_uart_irq(void* context, alt_u32 id) +#endif +{ + 101d8b0: defff104 addi sp,sp,-60 + 101d8b4: dfc00e15 stw ra,56(sp) + 101d8b8: df000d15 stw fp,52(sp) + 101d8bc: df000d04 addi fp,sp,52 + 101d8c0: e13ffe15 stw r4,-8(fp) + 101d8c4: e17fff15 stw r5,-4(fp) + altera_avalon_jtag_uart_state* sp = (altera_avalon_jtag_uart_state*) context; + 101d8c8: e0bffe17 ldw r2,-8(fp) + 101d8cc: e0bffc15 stw r2,-16(fp) + unsigned int base = sp->base; + 101d8d0: e0bffc17 ldw r2,-16(fp) + 101d8d4: 10800017 ldw r2,0(r2) + 101d8d8: e0bffb15 stw r2,-20(fp) + 101d8dc: 00000006 br 101d8e0 + /* ALT_LOG - see altera_hal/HAL/inc/sys/alt_log_printf.h */ + ALT_LOG_JTAG_UART_ISR_FUNCTION(base, sp); + + for ( ; ; ) + { + unsigned int control = IORD_ALTERA_AVALON_JTAG_UART_CONTROL(base); + 101d8e0: e0bffb17 ldw r2,-20(fp) + 101d8e4: 10800104 addi r2,r2,4 + 101d8e8: 10800037 ldwio r2,0(r2) + 101d8ec: e0bffa15 stw r2,-24(fp) + + /* Return once nothing more to do */ + if ((control & (ALTERA_AVALON_JTAG_UART_CONTROL_RI_MSK | ALTERA_AVALON_JTAG_UART_CONTROL_WI_MSK)) == 0) + 101d8f0: e0bffa17 ldw r2,-24(fp) + 101d8f4: 1080c00c andi r2,r2,768 + 101d8f8: 1005003a cmpeq r2,r2,zero + 101d8fc: 1000991e bne r2,zero,101db64 + break; + + if (control & ALTERA_AVALON_JTAG_UART_CONTROL_RI_MSK) + 101d900: e0bffa17 ldw r2,-24(fp) + 101d904: 1080400c andi r2,r2,256 + 101d908: 1005003a cmpeq r2,r2,zero + 101d90c: 1000481e bne r2,zero,101da30 + { + /* process a read irq. Start by assuming that there is data in the + * receive FIFO (otherwise why would we have been interrupted?) + */ + unsigned int data = 1 << ALTERA_AVALON_JTAG_UART_DATA_RAVAIL_OFST; + 101d910: 00800074 movhi r2,1 + 101d914: e0bff915 stw r2,-28(fp) + 101d918: 00000006 br 101d91c + for ( ; ; ) + { + /* Check whether there is space in the buffer. If not then we must not + * read any characters from the buffer as they will be lost. + */ + unsigned int next = (sp->rx_in + 1) % ALTERA_AVALON_JTAG_UART_BUF_LEN; + 101d91c: e0bffc17 ldw r2,-16(fp) + 101d920: 10800d17 ldw r2,52(r2) + 101d924: 10800044 addi r2,r2,1 + 101d928: 1081ffcc andi r2,r2,2047 + 101d92c: e0bff815 stw r2,-32(fp) + if (next == sp->rx_out) + 101d930: e0bffc17 ldw r2,-16(fp) + 101d934: 10c00e17 ldw r3,56(r2) + 101d938: e0bff817 ldw r2,-32(fp) + 101d93c: 18802826 beq r3,r2,101d9e0 + break; + + /* Try to remove a character from the FIFO and find out whether there + * are any more characters remaining. + */ + data = IORD_ALTERA_AVALON_JTAG_UART_DATA(base); + 101d940: e0bffb17 ldw r2,-20(fp) + 101d944: 10800037 ldwio r2,0(r2) + 101d948: e0bff915 stw r2,-28(fp) + + if ((data & ALTERA_AVALON_JTAG_UART_DATA_RVALID_MSK) == 0) + 101d94c: e0bff917 ldw r2,-28(fp) + 101d950: 10a0000c andi r2,r2,32768 + 101d954: 1005003a cmpeq r2,r2,zero + 101d958: 1000211e bne r2,zero,101d9e0 + break; + + sp->rx_buf[sp->rx_in] = (data & ALTERA_AVALON_JTAG_UART_DATA_DATA_MSK) >> ALTERA_AVALON_JTAG_UART_DATA_DATA_OFST; + 101d95c: e0bffc17 ldw r2,-16(fp) + 101d960: 10c00d17 ldw r3,52(r2) + 101d964: e0bff917 ldw r2,-28(fp) + 101d968: 1009883a mov r4,r2 + 101d96c: e0bffc17 ldw r2,-16(fp) + 101d970: 1885883a add r2,r3,r2 + 101d974: 10801104 addi r2,r2,68 + 101d978: 11000005 stb r4,0(r2) + sp->rx_in = (sp->rx_in + 1) % ALTERA_AVALON_JTAG_UART_BUF_LEN; + 101d97c: e0bffc17 ldw r2,-16(fp) + 101d980: 10800d17 ldw r2,52(r2) + 101d984: 10800044 addi r2,r2,1 + 101d988: 10c1ffcc andi r3,r2,2047 + 101d98c: e0bffc17 ldw r2,-16(fp) + 101d990: 10c00d15 stw r3,52(r2) + + /* Post an event to notify jtag_uart_read that a character has been read */ + ALT_FLAG_POST (sp->events, ALT_JTAG_UART_READ_RDY, OS_FLAG_SET); + 101d994: e0bffc17 ldw r2,-16(fp) + 101d998: 10800c17 ldw r2,48(r2) + 101d99c: e0bff515 stw r2,-44(fp) + 101d9a0: 00800044 movi r2,1 + 101d9a4: e0bff60d sth r2,-40(fp) + 101d9a8: 00800044 movi r2,1 + 101d9ac: e0bff685 stb r2,-38(fp) + OS_FLAGS flags, + INT8U opt) +{ + INT8U err; + + if (OSRunning) + 101d9b0: 008040b4 movhi r2,258 + 101d9b4: 10951444 addi r2,r2,21585 + 101d9b8: 10800003 ldbu r2,0(r2) + 101d9bc: 10803fcc andi r2,r2,255 + 101d9c0: 1005003a cmpeq r2,r2,zero + 101d9c4: 103fd51e bne r2,zero,101d91c + { + OSFlagPost (group, flags, opt, &err); + 101d9c8: e17ff60b ldhu r5,-40(fp) + 101d9cc: e1bff683 ldbu r6,-38(fp) + 101d9d0: e1fffd04 addi r7,fp,-12 + 101d9d4: e13ff517 ldw r4,-44(fp) + 101d9d8: 10185880 call 1018588 + return err; + 101d9dc: 003fcf06 br 101d91c + } + + if (data & ALTERA_AVALON_JTAG_UART_DATA_RAVAIL_MSK) + 101d9e0: e0bff917 ldw r2,-28(fp) + 101d9e4: 10bfffec andhi r2,r2,65535 + 101d9e8: 1005003a cmpeq r2,r2,zero + 101d9ec: 1000101e bne r2,zero,101da30 + { + /* If there is still data available here then the buffer is full + * so turn off receive interrupts until some space becomes available. + */ + sp->irq_enable &= ~ALTERA_AVALON_JTAG_UART_CONTROL_RE_MSK; + 101d9f0: e0bffc17 ldw r2,-16(fp) + 101d9f4: 10c00817 ldw r3,32(r2) + 101d9f8: 00bfff84 movi r2,-2 + 101d9fc: 1886703a and r3,r3,r2 + 101da00: e0bffc17 ldw r2,-16(fp) + 101da04: 10c00815 stw r3,32(r2) + IOWR_ALTERA_AVALON_JTAG_UART_CONTROL(base, sp->irq_enable); + 101da08: e0bffb17 ldw r2,-20(fp) + 101da0c: 11000104 addi r4,r2,4 + 101da10: e0bffc17 ldw r2,-16(fp) + 101da14: 10800817 ldw r2,32(r2) + 101da18: 1007883a mov r3,r2 + 101da1c: 2005883a mov r2,r4 + 101da20: 10c00035 stwio r3,0(r2) + + /* Dummy read to ensure IRQ is cleared prior to ISR completion */ + IORD_ALTERA_AVALON_JTAG_UART_CONTROL(base); + 101da24: e0bffb17 ldw r2,-20(fp) + 101da28: 10800104 addi r2,r2,4 + 101da2c: 10800037 ldwio r2,0(r2) + } + } + + if (control & ALTERA_AVALON_JTAG_UART_CONTROL_WI_MSK) + 101da30: e0bffa17 ldw r2,-24(fp) + 101da34: 1080800c andi r2,r2,512 + 101da38: 1005003a cmpeq r2,r2,zero + 101da3c: 103fa81e bne r2,zero,101d8e0 + { + /* process a write irq */ + unsigned int space = (control & ALTERA_AVALON_JTAG_UART_CONTROL_WSPACE_MSK) >> ALTERA_AVALON_JTAG_UART_CONTROL_WSPACE_OFST; + 101da40: e0bffa17 ldw r2,-24(fp) + 101da44: 10bfffec andhi r2,r2,65535 + 101da48: 1004d43a srli r2,r2,16 + 101da4c: e0bff715 stw r2,-36(fp) + + while (space > 0 && sp->tx_out != sp->tx_in) + 101da50: 00002706 br 101daf0 + { + IOWR_ALTERA_AVALON_JTAG_UART_DATA(base, sp->tx_buf[sp->tx_out]); + 101da54: e13ffb17 ldw r4,-20(fp) + 101da58: e0bffc17 ldw r2,-16(fp) + 101da5c: 10c01017 ldw r3,64(r2) + 101da60: e0bffc17 ldw r2,-16(fp) + 101da64: 1885883a add r2,r3,r2 + 101da68: 10821104 addi r2,r2,2116 + 101da6c: 10800003 ldbu r2,0(r2) + 101da70: 10c03fcc andi r3,r2,255 + 101da74: 18c0201c xori r3,r3,128 + 101da78: 18ffe004 addi r3,r3,-128 + 101da7c: 2005883a mov r2,r4 + 101da80: 10c00035 stwio r3,0(r2) + + sp->tx_out = (sp->tx_out + 1) % ALTERA_AVALON_JTAG_UART_BUF_LEN; + 101da84: e0bffc17 ldw r2,-16(fp) + 101da88: 10801017 ldw r2,64(r2) + 101da8c: 10800044 addi r2,r2,1 + 101da90: 10c1ffcc andi r3,r2,2047 + 101da94: e0bffc17 ldw r2,-16(fp) + 101da98: 10c01015 stw r3,64(r2) + + /* Post an event to notify jtag_uart_write that a character has been written */ + ALT_FLAG_POST (sp->events, ALT_JTAG_UART_WRITE_RDY, OS_FLAG_SET); + 101da9c: e0bffc17 ldw r2,-16(fp) + 101daa0: 10800c17 ldw r2,48(r2) + 101daa4: e0bff315 stw r2,-52(fp) + 101daa8: 00800084 movi r2,2 + 101daac: e0bff40d sth r2,-48(fp) + 101dab0: 00800044 movi r2,1 + 101dab4: e0bff485 stb r2,-46(fp) + OS_FLAGS flags, + INT8U opt) +{ + INT8U err; + + if (OSRunning) + 101dab8: 008040b4 movhi r2,258 + 101dabc: 10951444 addi r2,r2,21585 + 101dac0: 10800003 ldbu r2,0(r2) + 101dac4: 10803fcc andi r2,r2,255 + 101dac8: 1005003a cmpeq r2,r2,zero + 101dacc: 1000051e bne r2,zero,101dae4 + { + OSFlagPost (group, flags, opt, &err); + 101dad0: e17ff40b ldhu r5,-48(fp) + 101dad4: e1bff483 ldbu r6,-46(fp) + 101dad8: e1fffd44 addi r7,fp,-11 + 101dadc: e13ff317 ldw r4,-52(fp) + 101dae0: 10185880 call 1018588 + + space--; + 101dae4: e0bff717 ldw r2,-36(fp) + 101dae8: 10bfffc4 addi r2,r2,-1 + 101daec: e0bff715 stw r2,-36(fp) + if (control & ALTERA_AVALON_JTAG_UART_CONTROL_WI_MSK) + { + /* process a write irq */ + unsigned int space = (control & ALTERA_AVALON_JTAG_UART_CONTROL_WSPACE_MSK) >> ALTERA_AVALON_JTAG_UART_CONTROL_WSPACE_OFST; + + while (space > 0 && sp->tx_out != sp->tx_in) + 101daf0: e0bff717 ldw r2,-36(fp) + 101daf4: 1005003a cmpeq r2,r2,zero + 101daf8: 1000051e bne r2,zero,101db10 + 101dafc: e0bffc17 ldw r2,-16(fp) + 101db00: 10c01017 ldw r3,64(r2) + 101db04: e0bffc17 ldw r2,-16(fp) + 101db08: 10800f17 ldw r2,60(r2) + 101db0c: 18bfd11e bne r3,r2,101da54 + ALT_FLAG_POST (sp->events, ALT_JTAG_UART_WRITE_RDY, OS_FLAG_SET); + + space--; + } + + if (space > 0) + 101db10: e0bff717 ldw r2,-36(fp) + 101db14: 1005003a cmpeq r2,r2,zero + 101db18: 103f711e bne r2,zero,101d8e0 + { + /* If we don't have any more data available then turn off the TX interrupt */ + sp->irq_enable &= ~ALTERA_AVALON_JTAG_UART_CONTROL_WE_MSK; + 101db1c: e0bffc17 ldw r2,-16(fp) + 101db20: 10c00817 ldw r3,32(r2) + 101db24: 00bfff44 movi r2,-3 + 101db28: 1886703a and r3,r3,r2 + 101db2c: e0bffc17 ldw r2,-16(fp) + 101db30: 10c00815 stw r3,32(r2) + IOWR_ALTERA_AVALON_JTAG_UART_CONTROL(sp->base, sp->irq_enable); + 101db34: e0bffc17 ldw r2,-16(fp) + 101db38: 10800017 ldw r2,0(r2) + 101db3c: 11000104 addi r4,r2,4 + 101db40: e0bffc17 ldw r2,-16(fp) + 101db44: 10800817 ldw r2,32(r2) + 101db48: 1007883a mov r3,r2 + 101db4c: 2005883a mov r2,r4 + 101db50: 10c00035 stwio r3,0(r2) + + /* Dummy read to ensure IRQ is cleared prior to ISR completion */ + IORD_ALTERA_AVALON_JTAG_UART_CONTROL(base); + 101db54: e0bffb17 ldw r2,-20(fp) + 101db58: 10800104 addi r2,r2,4 + 101db5c: 10800037 ldwio r2,0(r2) + } + } + } + 101db60: 003f5f06 br 101d8e0 +} + 101db64: e037883a mov sp,fp + 101db68: dfc00117 ldw ra,4(sp) + 101db6c: df000017 ldw fp,0(sp) + 101db70: dec00204 addi sp,sp,8 + 101db74: f800283a ret + +0101db78 : + * Timeout routine is called every second + */ + +static alt_u32 +altera_avalon_jtag_uart_timeout(void* context) +{ + 101db78: defff804 addi sp,sp,-32 + 101db7c: dfc00715 stw ra,28(sp) + 101db80: df000615 stw fp,24(sp) + 101db84: df000604 addi fp,sp,24 + 101db88: e13fff15 stw r4,-4(fp) + altera_avalon_jtag_uart_state* sp = (altera_avalon_jtag_uart_state *) context; + 101db8c: e0bfff17 ldw r2,-4(fp) + 101db90: e0bffd15 stw r2,-12(fp) + + unsigned int control = IORD_ALTERA_AVALON_JTAG_UART_CONTROL(sp->base); + 101db94: e0bffd17 ldw r2,-12(fp) + 101db98: 10800017 ldw r2,0(r2) + 101db9c: 10800104 addi r2,r2,4 + 101dba0: 10800037 ldwio r2,0(r2) + 101dba4: e0bffc15 stw r2,-16(fp) + + if (control & ALTERA_AVALON_JTAG_UART_CONTROL_AC_MSK) + 101dba8: e0bffc17 ldw r2,-16(fp) + 101dbac: 1081000c andi r2,r2,1024 + 101dbb0: 1005003a cmpeq r2,r2,zero + 101dbb4: 10000c1e bne r2,zero,101dbe8 + { + IOWR_ALTERA_AVALON_JTAG_UART_CONTROL(sp->base, sp->irq_enable | ALTERA_AVALON_JTAG_UART_CONTROL_AC_MSK); + 101dbb8: e0bffd17 ldw r2,-12(fp) + 101dbbc: 10800017 ldw r2,0(r2) + 101dbc0: 11000104 addi r4,r2,4 + 101dbc4: e0bffd17 ldw r2,-12(fp) + 101dbc8: 10800817 ldw r2,32(r2) + 101dbcc: 10810014 ori r2,r2,1024 + 101dbd0: 1007883a mov r3,r2 + 101dbd4: 2005883a mov r2,r4 + 101dbd8: 10c00035 stwio r3,0(r2) + sp->host_inactive = 0; + 101dbdc: e0bffd17 ldw r2,-12(fp) + 101dbe0: 10000915 stw zero,36(r2) + 101dbe4: 00002106 br 101dc6c + } + else if (sp->host_inactive < INT_MAX - 2) { + 101dbe8: e0bffd17 ldw r2,-12(fp) + 101dbec: 10c00917 ldw r3,36(r2) + 101dbf0: 00a00034 movhi r2,32768 + 101dbf4: 10bfff04 addi r2,r2,-4 + 101dbf8: 10c01c36 bltu r2,r3,101dc6c + sp->host_inactive++; + 101dbfc: e0bffd17 ldw r2,-12(fp) + 101dc00: 10800917 ldw r2,36(r2) + 101dc04: 10c00044 addi r3,r2,1 + 101dc08: e0bffd17 ldw r2,-12(fp) + 101dc0c: 10c00915 stw r3,36(r2) + + if (sp->host_inactive >= sp->timeout) { + 101dc10: e0bffd17 ldw r2,-12(fp) + 101dc14: 10c00917 ldw r3,36(r2) + 101dc18: e0bffd17 ldw r2,-12(fp) + 101dc1c: 10800117 ldw r2,4(r2) + 101dc20: 18801236 bltu r3,r2,101dc6c + /* Post an event to indicate host is inactive (for jtag_uart_read */ + ALT_FLAG_POST (sp->events, ALT_JTAG_UART_TIMEOUT, OS_FLAG_SET); + 101dc24: e0bffd17 ldw r2,-12(fp) + 101dc28: 10800c17 ldw r2,48(r2) + 101dc2c: e0bffa15 stw r2,-24(fp) + 101dc30: 00800104 movi r2,4 + 101dc34: e0bffb0d sth r2,-20(fp) + 101dc38: 00800044 movi r2,1 + 101dc3c: e0bffb85 stb r2,-18(fp) + OS_FLAGS flags, + INT8U opt) +{ + INT8U err; + + if (OSRunning) + 101dc40: 008040b4 movhi r2,258 + 101dc44: 10951444 addi r2,r2,21585 + 101dc48: 10800003 ldbu r2,0(r2) + 101dc4c: 10803fcc andi r2,r2,255 + 101dc50: 1005003a cmpeq r2,r2,zero + 101dc54: 1000051e bne r2,zero,101dc6c + { + OSFlagPost (group, flags, opt, &err); + 101dc58: e17ffb0b ldhu r5,-20(fp) + 101dc5c: e1bffb83 ldbu r6,-18(fp) + 101dc60: e1fffe04 addi r7,fp,-8 + 101dc64: e13ffa17 ldw r4,-24(fp) + 101dc68: 10185880 call 1018588 + 101dc6c: 008040b4 movhi r2,258 + 101dc70: 10952904 addi r2,r2,21668 + 101dc74: 10800017 ldw r2,0(r2) + } + } + + return alt_ticks_per_second(); +} + 101dc78: e037883a mov sp,fp + 101dc7c: dfc00117 ldw ra,4(sp) + 101dc80: df000017 ldw fp,0(sp) + 101dc84: dec00204 addi sp,sp,8 + 101dc88: f800283a ret + +0101dc8c : + * The close routine is not implemented for the small driver; instead it will + * map to null. This is because the small driver simply waits while characters + * are transmitted; there is no interrupt-serviced buffer to empty + */ +int altera_avalon_jtag_uart_close(altera_avalon_jtag_uart_state* sp, int flags) +{ + 101dc8c: defffc04 addi sp,sp,-16 + 101dc90: df000315 stw fp,12(sp) + 101dc94: df000304 addi fp,sp,12 + 101dc98: e13ffd15 stw r4,-12(fp) + 101dc9c: e17ffe15 stw r5,-8(fp) + /* + * Wait for all transmit data to be emptied by the JTAG UART ISR, or + * for a host-inactivity timeout, in which case transmit data will be lost + */ + while ( (sp->tx_out != sp->tx_in) && (sp->host_inactive < sp->timeout) ) { + 101dca0: 00000706 br 101dcc0 + if (flags & O_NONBLOCK) { + 101dca4: e0bffe17 ldw r2,-8(fp) + 101dca8: 1090000c andi r2,r2,16384 + 101dcac: 1005003a cmpeq r2,r2,zero + 101dcb0: 1000031e bne r2,zero,101dcc0 + return -EWOULDBLOCK; + 101dcb4: 00bffd44 movi r2,-11 + 101dcb8: e0bfff15 stw r2,-4(fp) + 101dcbc: 00000b06 br 101dcec +{ + /* + * Wait for all transmit data to be emptied by the JTAG UART ISR, or + * for a host-inactivity timeout, in which case transmit data will be lost + */ + while ( (sp->tx_out != sp->tx_in) && (sp->host_inactive < sp->timeout) ) { + 101dcc0: e0bffd17 ldw r2,-12(fp) + 101dcc4: 10c01017 ldw r3,64(r2) + 101dcc8: e0bffd17 ldw r2,-12(fp) + 101dccc: 10800f17 ldw r2,60(r2) + 101dcd0: 18800526 beq r3,r2,101dce8 + 101dcd4: e0bffd17 ldw r2,-12(fp) + 101dcd8: 10c00917 ldw r3,36(r2) + 101dcdc: e0bffd17 ldw r2,-12(fp) + 101dce0: 10800117 ldw r2,4(r2) + 101dce4: 18bfef36 bltu r3,r2,101dca4 + if (flags & O_NONBLOCK) { + return -EWOULDBLOCK; + } + } + + return 0; + 101dce8: e03fff15 stw zero,-4(fp) + 101dcec: e0bfff17 ldw r2,-4(fp) +} + 101dcf0: e037883a mov sp,fp + 101dcf4: df000017 ldw fp,0(sp) + 101dcf8: dec00104 addi sp,sp,4 + 101dcfc: f800283a ret + +0101dd00 : +/* ----------------------------------------------------------- */ + +int +altera_avalon_jtag_uart_ioctl(altera_avalon_jtag_uart_state* sp, int req, + void* arg) +{ + 101dd00: defff804 addi sp,sp,-32 + 101dd04: df000715 stw fp,28(sp) + 101dd08: df000704 addi fp,sp,28 + 101dd0c: e13ffb15 stw r4,-20(fp) + 101dd10: e17ffc15 stw r5,-16(fp) + 101dd14: e1bffd15 stw r6,-12(fp) + int rc = -ENOTTY; + 101dd18: 00bff9c4 movi r2,-25 + 101dd1c: e0bffa15 stw r2,-24(fp) + + switch (req) + 101dd20: e0bffc17 ldw r2,-16(fp) + 101dd24: e0bfff15 stw r2,-4(fp) + 101dd28: e0ffff17 ldw r3,-4(fp) + 101dd2c: 189a8060 cmpeqi r2,r3,27137 + 101dd30: 1000041e bne r2,zero,101dd44 + 101dd34: e0ffff17 ldw r3,-4(fp) + 101dd38: 189a80a0 cmpeqi r2,r3,27138 + 101dd3c: 10001b1e bne r2,zero,101ddac + 101dd40: 00002706 br 101dde0 + { + case TIOCSTIMEOUT: + /* Set the time to wait until assuming host is not connected */ + if (sp->timeout != INT_MAX) + 101dd44: e0bffb17 ldw r2,-20(fp) + 101dd48: 10c00117 ldw r3,4(r2) + 101dd4c: 00a00034 movhi r2,32768 + 101dd50: 10bfffc4 addi r2,r2,-1 + 101dd54: 18802226 beq r3,r2,101dde0 + { + int timeout = *((int *)arg); + 101dd58: e0bffd17 ldw r2,-12(fp) + 101dd5c: 10800017 ldw r2,0(r2) + 101dd60: e0bff915 stw r2,-28(fp) + sp->timeout = (timeout >= 2 && timeout < INT_MAX) ? timeout : INT_MAX - 1; + 101dd64: e0bff917 ldw r2,-28(fp) + 101dd68: 10800090 cmplti r2,r2,2 + 101dd6c: 1000071e bne r2,zero,101dd8c + 101dd70: e0fff917 ldw r3,-28(fp) + 101dd74: 00a00034 movhi r2,32768 + 101dd78: 10bfffc4 addi r2,r2,-1 + 101dd7c: 18800326 beq r3,r2,101dd8c + 101dd80: e0bff917 ldw r2,-28(fp) + 101dd84: e0bffe15 stw r2,-8(fp) + 101dd88: 00000306 br 101dd98 + 101dd8c: 00e00034 movhi r3,32768 + 101dd90: 18ffff84 addi r3,r3,-2 + 101dd94: e0fffe15 stw r3,-8(fp) + 101dd98: e0bffb17 ldw r2,-20(fp) + 101dd9c: e0fffe17 ldw r3,-8(fp) + 101dda0: 10c00115 stw r3,4(r2) + rc = 0; + 101dda4: e03ffa15 stw zero,-24(fp) + } + break; + 101dda8: 00000d06 br 101dde0 + + case TIOCGCONNECTED: + /* Find out whether host is connected */ + if (sp->timeout != INT_MAX) + 101ddac: e0bffb17 ldw r2,-20(fp) + 101ddb0: 10c00117 ldw r3,4(r2) + 101ddb4: 00a00034 movhi r2,32768 + 101ddb8: 10bfffc4 addi r2,r2,-1 + 101ddbc: 18800826 beq r3,r2,101dde0 + { + *((int *)arg) = (sp->host_inactive < sp->timeout) ? 1 : 0; + 101ddc0: e13ffd17 ldw r4,-12(fp) + 101ddc4: e0bffb17 ldw r2,-20(fp) + 101ddc8: 10c00917 ldw r3,36(r2) + 101ddcc: e0bffb17 ldw r2,-20(fp) + 101ddd0: 10800117 ldw r2,4(r2) + 101ddd4: 1885803a cmpltu r2,r3,r2 + 101ddd8: 20800015 stw r2,0(r4) + rc = 0; + 101dddc: e03ffa15 stw zero,-24(fp) + + default: + break; + } + + return rc; + 101dde0: e0bffa17 ldw r2,-24(fp) +} + 101dde4: e037883a mov sp,fp + 101dde8: df000017 ldw fp,0(sp) + 101ddec: dec00104 addi sp,sp,4 + 101ddf0: f800283a ret + +0101ddf4 : +/* ----------------------------------------------------------- */ + +int +altera_avalon_jtag_uart_read(altera_avalon_jtag_uart_state* sp, + char * buffer, int space, int flags) +{ + 101ddf4: deffeb04 addi sp,sp,-84 + 101ddf8: dfc01415 stw ra,80(sp) + 101ddfc: df001315 stw fp,76(sp) + 101de00: df001304 addi fp,sp,76 + 101de04: e13ffb15 stw r4,-20(fp) + 101de08: e17ffc15 stw r5,-16(fp) + 101de0c: e1bffd15 stw r6,-12(fp) + 101de10: e1fffe15 stw r7,-8(fp) + char * ptr = buffer; + 101de14: e0bffc17 ldw r2,-16(fp) + 101de18: e0bff915 stw r2,-28(fp) + + /* + * When running in a multi threaded environment, obtain the "read_lock" + * semaphore. This ensures that reading from the device is thread-safe. + */ + ALT_SEM_PEND (sp->read_lock, 0); + 101de1c: e0bffb17 ldw r2,-20(fp) + 101de20: 10800a17 ldw r2,40(r2) + 101de24: e0bff315 stw r2,-52(fp) + 101de28: e03ff40d sth zero,-48(fp) + +static ALT_INLINE int ALT_ALWAYS_INLINE alt_sem_pend (OS_EVENT* sem, + INT16U timeout) +{ + INT8U err; + OSSemPend (sem, timeout, &err); + 101de2c: e17ff40b ldhu r5,-48(fp) + 101de30: e1bffa44 addi r6,fp,-23 + 101de34: e13ff317 ldw r4,-52(fp) + 101de38: 101ae180 call 101ae18 + + while (space > 0) + 101de3c: 00006406 br 101dfd0 + unsigned int in, out; + + /* Read as much data as possible */ + do + { + in = sp->rx_in; + 101de40: e0bffb17 ldw r2,-20(fp) + 101de44: 10800d17 ldw r2,52(r2) + 101de48: e0bff615 stw r2,-40(fp) + out = sp->rx_out; + 101de4c: e0bffb17 ldw r2,-20(fp) + 101de50: 10800e17 ldw r2,56(r2) + 101de54: e0bff515 stw r2,-44(fp) + + if (in >= out) + 101de58: e0fff617 ldw r3,-40(fp) + 101de5c: e0bff517 ldw r2,-44(fp) + 101de60: 18800536 bltu r3,r2,101de78 + n = in - out; + 101de64: e0bff617 ldw r2,-40(fp) + 101de68: e0fff517 ldw r3,-44(fp) + 101de6c: 10c5c83a sub r2,r2,r3 + 101de70: e0bff715 stw r2,-36(fp) + 101de74: 00000406 br 101de88 + else + n = ALTERA_AVALON_JTAG_UART_BUF_LEN - out; + 101de78: 00820004 movi r2,2048 + 101de7c: e0fff517 ldw r3,-44(fp) + 101de80: 10c5c83a sub r2,r2,r3 + 101de84: e0bff715 stw r2,-36(fp) + + if (n == 0) + 101de88: e0bff717 ldw r2,-36(fp) + 101de8c: 1005003a cmpeq r2,r2,zero + 101de90: 10001f1e bne r2,zero,101df10 + break; /* No more data available */ + + if (n > space) + 101de94: e0fffd17 ldw r3,-12(fp) + 101de98: e0bff717 ldw r2,-36(fp) + 101de9c: 1880022e bgeu r3,r2,101dea8 + n = space; + 101dea0: e0bffd17 ldw r2,-12(fp) + 101dea4: e0bff715 stw r2,-36(fp) + + memcpy(ptr, sp->rx_buf + out, n); + 101dea8: e0bffb17 ldw r2,-20(fp) + 101deac: 10c01104 addi r3,r2,68 + 101deb0: e0bff517 ldw r2,-44(fp) + 101deb4: 1887883a add r3,r3,r2 + 101deb8: e0bff917 ldw r2,-28(fp) + 101debc: 1009883a mov r4,r2 + 101dec0: 180b883a mov r5,r3 + 101dec4: e1bff717 ldw r6,-36(fp) + 101dec8: 100aa3c0 call 100aa3c + ptr += n; + 101decc: e0fff717 ldw r3,-36(fp) + 101ded0: e0bff917 ldw r2,-28(fp) + 101ded4: 10c5883a add r2,r2,r3 + 101ded8: e0bff915 stw r2,-28(fp) + space -= n; + 101dedc: e0fffd17 ldw r3,-12(fp) + 101dee0: e0bff717 ldw r2,-36(fp) + 101dee4: 1885c83a sub r2,r3,r2 + 101dee8: e0bffd15 stw r2,-12(fp) + + sp->rx_out = (out + n) % ALTERA_AVALON_JTAG_UART_BUF_LEN; + 101deec: e0fff517 ldw r3,-44(fp) + 101def0: e0bff717 ldw r2,-36(fp) + 101def4: 1885883a add r2,r3,r2 + 101def8: 10c1ffcc andi r3,r2,2047 + 101defc: e0bffb17 ldw r2,-20(fp) + 101df00: 10c00e15 stw r3,56(r2) + } + while (space > 0); + 101df04: e0bffd17 ldw r2,-12(fp) + 101df08: 10800048 cmpgei r2,r2,1 + 101df0c: 103fcc1e bne r2,zero,101de40 + + /* If we read any data then return it */ + if (ptr != buffer) + 101df10: e0fff917 ldw r3,-28(fp) + 101df14: e0bffc17 ldw r2,-16(fp) + 101df18: 1880301e bne r3,r2,101dfdc + break; + + /* If in non-blocking mode then return error */ + if (flags & O_NONBLOCK) + 101df1c: e0bffe17 ldw r2,-8(fp) + 101df20: 1090000c andi r2,r2,16384 + 101df24: 1004c03a cmpne r2,r2,zero + 101df28: 10002c1e bne r2,zero,101dfdc + break; + +#ifdef __ucosii__ + /* OS Present: Pend on a flag if the OS is running, otherwise spin */ + if(OSRunning == OS_TRUE) { + 101df2c: 008040b4 movhi r2,258 + 101df30: 10951444 addi r2,r2,21585 + 101df34: 10800003 ldbu r2,0(r2) + 101df38: 10803fcc andi r2,r2,255 + 101df3c: 10800058 cmpnei r2,r2,1 + 101df40: 1000161e bne r2,zero,101df9c + * When running in a multi-threaded mode, we pend on the read event + * flag set and timeout event flag set in the isr. This avoids wasting CPU + * cycles waiting in this thread, when we could be doing something more + * profitable elsewhere. + */ + ALT_FLAG_PEND (sp->events, + 101df44: e0bffb17 ldw r2,-20(fp) + 101df48: 10800c17 ldw r2,48(r2) + 101df4c: e0bff015 stw r2,-64(fp) + 101df50: 00800144 movi r2,5 + 101df54: e0bff10d sth r2,-60(fp) + 101df58: 00bfe0c4 movi r2,-125 + 101df5c: e0bff185 stb r2,-58(fp) + 101df60: e03ff20d sth zero,-56(fp) + OS_FLAGS flags, + INT8U wait_type, + INT16U timeout) +{ + INT8U err; + if (OSRunning) + 101df64: 008040b4 movhi r2,258 + 101df68: 10951444 addi r2,r2,21585 + 101df6c: 10800003 ldbu r2,0(r2) + 101df70: 10803fcc andi r2,r2,255 + 101df74: 1005003a cmpeq r2,r2,zero + 101df78: 1000111e bne r2,zero,101dfc0 + { + OSFlagPend (group, flags, wait_type, timeout, &err); + 101df7c: e17ff10b ldhu r5,-60(fp) + 101df80: e1bff183 ldbu r6,-58(fp) + 101df84: e1fff20b ldhu r7,-56(fp) + 101df88: e0bffa04 addi r2,fp,-24 + 101df8c: d8800015 stw r2,0(sp) + 101df90: e13ff017 ldw r4,-64(fp) + 101df94: 1017edc0 call 1017edc + return err; + 101df98: 00000906 br 101dfc0 + OS_FLAG_WAIT_SET_ANY + OS_FLAG_CONSUME, + 0); + } + else { + /* Spin until more data arrives or until host disconnects */ + while (in == sp->rx_in && sp->host_inactive < sp->timeout) + 101df9c: e0bffb17 ldw r2,-20(fp) + 101dfa0: 10c00d17 ldw r3,52(r2) + 101dfa4: e0bff617 ldw r2,-40(fp) + 101dfa8: 1880051e bne r3,r2,101dfc0 + 101dfac: e0bffb17 ldw r2,-20(fp) + 101dfb0: 10c00917 ldw r3,36(r2) + 101dfb4: e0bffb17 ldw r2,-20(fp) + 101dfb8: 10800117 ldw r2,4(r2) + 101dfbc: 18bff736 bltu r3,r2,101df9c + /* No OS: Always spin */ + while (in == sp->rx_in && sp->host_inactive < sp->timeout) + ; +#endif /* __ucosii__ */ + + if (in == sp->rx_in) + 101dfc0: e0bffb17 ldw r2,-20(fp) + 101dfc4: 10c00d17 ldw r3,52(r2) + 101dfc8: e0bff617 ldw r2,-40(fp) + 101dfcc: 18800326 beq r3,r2,101dfdc + * When running in a multi threaded environment, obtain the "read_lock" + * semaphore. This ensures that reading from the device is thread-safe. + */ + ALT_SEM_PEND (sp->read_lock, 0); + + while (space > 0) + 101dfd0: e0bffd17 ldw r2,-12(fp) + 101dfd4: 10800048 cmpgei r2,r2,1 + 101dfd8: 103f991e bne r2,zero,101de40 + /* + * Now that access to the circular buffer is complete, release the read + * semaphore so that other threads can access the buffer. + */ + + ALT_SEM_POST (sp->read_lock); + 101dfdc: e0bffb17 ldw r2,-20(fp) + 101dfe0: 11000a17 ldw r4,40(r2) + 101dfe4: 101b2100 call 101b210 + + if (ptr != buffer) + 101dfe8: e0fff917 ldw r3,-28(fp) + 101dfec: e0bffc17 ldw r2,-16(fp) + 101dff0: 18801926 beq r3,r2,101e058 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 101dff4: 0005303a rdctl r2,status + 101dff8: e0bfef15 stw r2,-68(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 101dffc: e0ffef17 ldw r3,-68(fp) + 101e000: 00bfff84 movi r2,-2 + 101e004: 1884703a and r2,r3,r2 + 101e008: 1001703a wrctl status,r2 + + return context; + 101e00c: e0bfef17 ldw r2,-68(fp) + { + /* If we read any data then there is space in the buffer so enable interrupts */ + context = alt_irq_disable_all(); + 101e010: e0bff815 stw r2,-32(fp) + sp->irq_enable |= ALTERA_AVALON_JTAG_UART_CONTROL_RE_MSK; + 101e014: e0bffb17 ldw r2,-20(fp) + 101e018: 10800817 ldw r2,32(r2) + 101e01c: 10c00054 ori r3,r2,1 + 101e020: e0bffb17 ldw r2,-20(fp) + 101e024: 10c00815 stw r3,32(r2) + IOWR_ALTERA_AVALON_JTAG_UART_CONTROL(sp->base, sp->irq_enable); + 101e028: e0bffb17 ldw r2,-20(fp) + 101e02c: 10800017 ldw r2,0(r2) + 101e030: 11000104 addi r4,r2,4 + 101e034: e0bffb17 ldw r2,-20(fp) + 101e038: 10800817 ldw r2,32(r2) + 101e03c: 1007883a mov r3,r2 + 101e040: 2005883a mov r2,r4 + 101e044: 10c00035 stwio r3,0(r2) + 101e048: e0bff817 ldw r2,-32(fp) + 101e04c: e0bfee15 stw r2,-72(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 101e050: e0bfee17 ldw r2,-72(fp) + 101e054: 1001703a wrctl status,r2 + alt_irq_enable_all(context); + } + + if (ptr != buffer) + 101e058: e0fff917 ldw r3,-28(fp) + 101e05c: e0bffc17 ldw r2,-16(fp) + 101e060: 18800526 beq r3,r2,101e078 + return ptr - buffer; + 101e064: e0fff917 ldw r3,-28(fp) + 101e068: e0bffc17 ldw r2,-16(fp) + 101e06c: 1887c83a sub r3,r3,r2 + 101e070: e0ffff15 stw r3,-4(fp) + 101e074: 00000906 br 101e09c + else if (flags & O_NONBLOCK) + 101e078: e0bffe17 ldw r2,-8(fp) + 101e07c: 1090000c andi r2,r2,16384 + 101e080: 1005003a cmpeq r2,r2,zero + 101e084: 1000031e bne r2,zero,101e094 + return -EWOULDBLOCK; + 101e088: 00bffd44 movi r2,-11 + 101e08c: e0bfff15 stw r2,-4(fp) + 101e090: 00000206 br 101e09c + else + return -EIO; + 101e094: 00bffec4 movi r2,-5 + 101e098: e0bfff15 stw r2,-4(fp) + 101e09c: e0bfff17 ldw r2,-4(fp) +} + 101e0a0: e037883a mov sp,fp + 101e0a4: dfc00117 ldw ra,4(sp) + 101e0a8: df000017 ldw fp,0(sp) + 101e0ac: dec00204 addi sp,sp,8 + 101e0b0: f800283a ret + +0101e0b4 : +/* ----------------------------------------------------------- */ + +int +altera_avalon_jtag_uart_write(altera_avalon_jtag_uart_state* sp, + const char * ptr, int count, int flags) +{ + 101e0b4: deffeb04 addi sp,sp,-84 + 101e0b8: dfc01415 stw ra,80(sp) + 101e0bc: df001315 stw fp,76(sp) + 101e0c0: df001304 addi fp,sp,76 + 101e0c4: e13ffb15 stw r4,-20(fp) + 101e0c8: e17ffc15 stw r5,-16(fp) + 101e0cc: e1bffd15 stw r6,-12(fp) + 101e0d0: e1fffe15 stw r7,-8(fp) + /* Remove warning at optimisation level 03 by seting out to 0 */ + unsigned int in, out=0; + 101e0d4: e03ff815 stw zero,-32(fp) + unsigned int n; + alt_irq_context context; + + const char * start = ptr; + 101e0d8: e0bffc17 ldw r2,-16(fp) + 101e0dc: e0bff515 stw r2,-44(fp) + + /* + * When running in a multi threaded environment, obtain the "write_lock" + * semaphore. This ensures that writing to the device is thread-safe. + */ + ALT_SEM_PEND (sp->write_lock, 0); + 101e0e0: e0bffb17 ldw r2,-20(fp) + 101e0e4: 10800b17 ldw r2,44(r2) + 101e0e8: e0bff315 stw r2,-52(fp) + 101e0ec: e03ff40d sth zero,-48(fp) + 101e0f0: e17ff40b ldhu r5,-48(fp) + 101e0f4: e1bffa04 addi r6,fp,-24 + 101e0f8: e13ff317 ldw r4,-52(fp) + 101e0fc: 101ae180 call 101ae18 + + do + { + /* Copy as much as we can into the transmit buffer */ + while (count > 0) + 101e100: 00003a06 br 101e1ec + { + /* We need a stable value of the out pointer to calculate the space available */ + in = sp->tx_in; + 101e104: e0bffb17 ldw r2,-20(fp) + 101e108: 10800f17 ldw r2,60(r2) + 101e10c: e0bff915 stw r2,-28(fp) + out = sp->tx_out; + 101e110: e0bffb17 ldw r2,-20(fp) + 101e114: 10801017 ldw r2,64(r2) + 101e118: e0bff815 stw r2,-32(fp) + + if (in < out) + 101e11c: e0fff917 ldw r3,-28(fp) + 101e120: e0bff817 ldw r2,-32(fp) + 101e124: 1880062e bgeu r3,r2,101e140 + n = out - 1 - in; + 101e128: e0fff817 ldw r3,-32(fp) + 101e12c: e0bff917 ldw r2,-28(fp) + 101e130: 1885c83a sub r2,r3,r2 + 101e134: 10bfffc4 addi r2,r2,-1 + 101e138: e0bff715 stw r2,-36(fp) + 101e13c: 00000c06 br 101e170 + else if (out > 0) + 101e140: e0bff817 ldw r2,-32(fp) + 101e144: 1005003a cmpeq r2,r2,zero + 101e148: 1000051e bne r2,zero,101e160 + n = ALTERA_AVALON_JTAG_UART_BUF_LEN - in; + 101e14c: 00820004 movi r2,2048 + 101e150: e0fff917 ldw r3,-28(fp) + 101e154: 10c5c83a sub r2,r2,r3 + 101e158: e0bff715 stw r2,-36(fp) + 101e15c: 00000406 br 101e170 + else + n = ALTERA_AVALON_JTAG_UART_BUF_LEN - 1 - in; + 101e160: 0081ffc4 movi r2,2047 + 101e164: e0fff917 ldw r3,-28(fp) + 101e168: 10c5c83a sub r2,r2,r3 + 101e16c: e0bff715 stw r2,-36(fp) + + if (n == 0) + 101e170: e0bff717 ldw r2,-36(fp) + 101e174: 1005003a cmpeq r2,r2,zero + 101e178: 10001f1e bne r2,zero,101e1f8 + break; + + if (n > count) + 101e17c: e0fffd17 ldw r3,-12(fp) + 101e180: e0bff717 ldw r2,-36(fp) + 101e184: 1880022e bgeu r3,r2,101e190 + n = count; + 101e188: e0bffd17 ldw r2,-12(fp) + 101e18c: e0bff715 stw r2,-36(fp) + + memcpy(sp->tx_buf + in, ptr, n); + 101e190: e0bffb17 ldw r2,-20(fp) + 101e194: 10c21104 addi r3,r2,2116 + 101e198: e0bff917 ldw r2,-28(fp) + 101e19c: 1885883a add r2,r3,r2 + 101e1a0: e0fffc17 ldw r3,-16(fp) + 101e1a4: 1009883a mov r4,r2 + 101e1a8: 180b883a mov r5,r3 + 101e1ac: e1bff717 ldw r6,-36(fp) + 101e1b0: 100aa3c0 call 100aa3c + ptr += n; + 101e1b4: e0fff717 ldw r3,-36(fp) + 101e1b8: e0bffc17 ldw r2,-16(fp) + 101e1bc: 10c5883a add r2,r2,r3 + 101e1c0: e0bffc15 stw r2,-16(fp) + count -= n; + 101e1c4: e0fffd17 ldw r3,-12(fp) + 101e1c8: e0bff717 ldw r2,-36(fp) + 101e1cc: 1885c83a sub r2,r3,r2 + 101e1d0: e0bffd15 stw r2,-12(fp) + + sp->tx_in = (in + n) % ALTERA_AVALON_JTAG_UART_BUF_LEN; + 101e1d4: e0fff917 ldw r3,-28(fp) + 101e1d8: e0bff717 ldw r2,-36(fp) + 101e1dc: 1885883a add r2,r3,r2 + 101e1e0: 10c1ffcc andi r3,r2,2047 + 101e1e4: e0bffb17 ldw r2,-20(fp) + 101e1e8: 10c00f15 stw r3,60(r2) + ALT_SEM_PEND (sp->write_lock, 0); + + do + { + /* Copy as much as we can into the transmit buffer */ + while (count > 0) + 101e1ec: e0bffd17 ldw r2,-12(fp) + 101e1f0: 10800048 cmpgei r2,r2,1 + 101e1f4: 103fc31e bne r2,zero,101e104 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 101e1f8: 0005303a rdctl r2,status + 101e1fc: e0bff215 stw r2,-56(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 101e200: e0fff217 ldw r3,-56(fp) + 101e204: 00bfff84 movi r2,-2 + 101e208: 1884703a and r2,r3,r2 + 101e20c: 1001703a wrctl status,r2 + + return context; + 101e210: e0bff217 ldw r2,-56(fp) + * to enable interrupts if there is no space left in the FIFO + * + * For now kick the interrupt routine every time to make it transmit + * the data + */ + context = alt_irq_disable_all(); + 101e214: e0bff615 stw r2,-40(fp) + sp->irq_enable |= ALTERA_AVALON_JTAG_UART_CONTROL_WE_MSK; + 101e218: e0bffb17 ldw r2,-20(fp) + 101e21c: 10800817 ldw r2,32(r2) + 101e220: 10c00094 ori r3,r2,2 + 101e224: e0bffb17 ldw r2,-20(fp) + 101e228: 10c00815 stw r3,32(r2) + IOWR_ALTERA_AVALON_JTAG_UART_CONTROL(sp->base, sp->irq_enable); + 101e22c: e0bffb17 ldw r2,-20(fp) + 101e230: 10800017 ldw r2,0(r2) + 101e234: 11000104 addi r4,r2,4 + 101e238: e0bffb17 ldw r2,-20(fp) + 101e23c: 10800817 ldw r2,32(r2) + 101e240: 1007883a mov r3,r2 + 101e244: 2005883a mov r2,r4 + 101e248: 10c00035 stwio r3,0(r2) + 101e24c: e0bff617 ldw r2,-40(fp) + 101e250: e0bff115 stw r2,-60(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 101e254: e0bff117 ldw r2,-60(fp) + 101e258: 1001703a wrctl status,r2 + /* + * If there is any data left then either return now or block until + * some has been sent + */ + /* consider: test whether there is anything there while doing this and delay for at most 2s. */ + if (count > 0) + 101e25c: e0bffd17 ldw r2,-12(fp) + 101e260: 10800050 cmplti r2,r2,1 + 101e264: 10002d1e bne r2,zero,101e31c + { + if (flags & O_NONBLOCK) + 101e268: e0bffe17 ldw r2,-8(fp) + 101e26c: 1090000c andi r2,r2,16384 + 101e270: 1004c03a cmpne r2,r2,zero + 101e274: 10002c1e bne r2,zero,101e328 + break; + +#ifdef __ucosii__ + /* OS Present: Pend on a flag if the OS is running, otherwise spin */ + if(OSRunning == OS_TRUE) { + 101e278: 008040b4 movhi r2,258 + 101e27c: 10951444 addi r2,r2,21585 + 101e280: 10800003 ldbu r2,0(r2) + 101e284: 10803fcc andi r2,r2,255 + 101e288: 10800058 cmpnei r2,r2,1 + 101e28c: 1000161e bne r2,zero,101e2e8 + * When running in a multi-threaded mode, we pend on the write event + * flag set or the timeout flag in the isr. This avoids wasting CPU + * cycles waiting in this thread, when we could be doing something + * more profitable elsewhere. + */ + ALT_FLAG_PEND (sp->events, + 101e290: e0bffb17 ldw r2,-20(fp) + 101e294: 10800c17 ldw r2,48(r2) + 101e298: e0bfee15 stw r2,-72(fp) + 101e29c: 00800184 movi r2,6 + 101e2a0: e0bfef0d sth r2,-68(fp) + 101e2a4: 00bfe0c4 movi r2,-125 + 101e2a8: e0bfef85 stb r2,-66(fp) + 101e2ac: e03ff00d sth zero,-64(fp) + OS_FLAGS flags, + INT8U wait_type, + INT16U timeout) +{ + INT8U err; + if (OSRunning) + 101e2b0: 008040b4 movhi r2,258 + 101e2b4: 10951444 addi r2,r2,21585 + 101e2b8: 10800003 ldbu r2,0(r2) + 101e2bc: 10803fcc andi r2,r2,255 + 101e2c0: 1005003a cmpeq r2,r2,zero + 101e2c4: 1000111e bne r2,zero,101e30c + { + OSFlagPend (group, flags, wait_type, timeout, &err); + 101e2c8: e17fef0b ldhu r5,-68(fp) + 101e2cc: e1bfef83 ldbu r6,-66(fp) + 101e2d0: e1fff00b ldhu r7,-64(fp) + 101e2d4: e0bffa44 addi r2,fp,-23 + 101e2d8: d8800015 stw r2,0(sp) + 101e2dc: e13fee17 ldw r4,-72(fp) + 101e2e0: 1017edc0 call 1017edc + return err; + 101e2e4: 00000906 br 101e30c + /* + * OS not running: Wait for data to be removed from buffer. + * Once the interrupt routine has removed some data then we + * will be able to insert some more. + */ + while (out == sp->tx_out && sp->host_inactive < sp->timeout) + 101e2e8: e0bffb17 ldw r2,-20(fp) + 101e2ec: 10c01017 ldw r3,64(r2) + 101e2f0: e0bff817 ldw r2,-32(fp) + 101e2f4: 1880051e bne r3,r2,101e30c + 101e2f8: e0bffb17 ldw r2,-20(fp) + 101e2fc: 10c00917 ldw r3,36(r2) + 101e300: e0bffb17 ldw r2,-20(fp) + 101e304: 10800117 ldw r2,4(r2) + 101e308: 18bff736 bltu r3,r2,101e2e8 + */ + while (out == sp->tx_out && sp->host_inactive < sp->timeout) + ; +#endif /* __ucosii__ */ + + if (out == sp->tx_out) + 101e30c: e0bffb17 ldw r2,-20(fp) + 101e310: 10c01017 ldw r3,64(r2) + 101e314: e0bff817 ldw r2,-32(fp) + 101e318: 18800326 beq r3,r2,101e328 + break; + } + } + while (count > 0); + 101e31c: e0bffd17 ldw r2,-12(fp) + 101e320: 10800048 cmpgei r2,r2,1 + 101e324: 103fb11e bne r2,zero,101e1ec + + /* + * Now that access to the circular buffer is complete, release the write + * semaphore so that other threads can access the buffer. + */ + ALT_SEM_POST (sp->write_lock); + 101e328: e0bffb17 ldw r2,-20(fp) + 101e32c: 11000b17 ldw r4,44(r2) + 101e330: 101b2100 call 101b210 + + if (ptr != start) + 101e334: e0fffc17 ldw r3,-16(fp) + 101e338: e0bff517 ldw r2,-44(fp) + 101e33c: 18800526 beq r3,r2,101e354 + return ptr - start; + 101e340: e0fffc17 ldw r3,-16(fp) + 101e344: e0bff517 ldw r2,-44(fp) + 101e348: 1887c83a sub r3,r3,r2 + 101e34c: e0ffff15 stw r3,-4(fp) + 101e350: 00000906 br 101e378 + else if (flags & O_NONBLOCK) + 101e354: e0bffe17 ldw r2,-8(fp) + 101e358: 1090000c andi r2,r2,16384 + 101e35c: 1005003a cmpeq r2,r2,zero + 101e360: 1000031e bne r2,zero,101e370 + return -EWOULDBLOCK; + 101e364: 00bffd44 movi r2,-11 + 101e368: e0bfff15 stw r2,-4(fp) + 101e36c: 00000206 br 101e378 + else + return -EIO; /* Host not connected */ + 101e370: 00bffec4 movi r2,-5 + 101e374: e0bfff15 stw r2,-4(fp) + 101e378: e0bfff17 ldw r2,-4(fp) +} + 101e37c: e037883a mov sp,fp + 101e380: dfc00117 ldw ra,4(sp) + 101e384: df000017 ldw fp,0(sp) + 101e388: dec00204 addi sp,sp,8 + 101e38c: f800283a ret + +0101e390 : +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT +static void alt_avalon_timer_sc_irq (void* base) +#else +static void alt_avalon_timer_sc_irq (void* base, alt_u32 id) +#endif +{ + 101e390: defff904 addi sp,sp,-28 + 101e394: dfc00615 stw ra,24(sp) + 101e398: df000515 stw fp,20(sp) + 101e39c: df000504 addi fp,sp,20 + 101e3a0: e13ffe15 stw r4,-8(fp) + 101e3a4: e17fff15 stw r5,-4(fp) + alt_irq_context cpu_sr; + + /* clear the interrupt */ + IOWR_ALTERA_AVALON_TIMER_STATUS (base, 0); + 101e3a8: e0bffe17 ldw r2,-8(fp) + 101e3ac: 10000035 stwio zero,0(r2) + /* + * Dummy read to ensure IRQ is negated before the ISR returns. + * The control register is read because reading the status + * register has side-effects per the register map documentation. + */ + IORD_ALTERA_AVALON_TIMER_CONTROL (base); + 101e3b0: e0bffe17 ldw r2,-8(fp) + 101e3b4: 10800104 addi r2,r2,4 + 101e3b8: 10800037 ldwio r2,0(r2) +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 101e3bc: 0005303a rdctl r2,status + 101e3c0: e0bffc15 stw r2,-16(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 101e3c4: e0fffc17 ldw r3,-16(fp) + 101e3c8: 00bfff84 movi r2,-2 + 101e3cc: 1884703a and r2,r3,r2 + 101e3d0: 1001703a wrctl status,r2 + + return context; + 101e3d4: e0bffc17 ldw r2,-16(fp) + + /* + * Notify the system of a clock tick. disable interrupts + * during this time to safely support ISR preemption + */ + cpu_sr = alt_irq_disable_all(); + 101e3d8: e0bffd15 stw r2,-12(fp) + alt_tick (); + 101e3dc: 101fedc0 call 101fedc + 101e3e0: e0bffd17 ldw r2,-12(fp) + 101e3e4: e0bffb15 stw r2,-20(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 101e3e8: e0bffb17 ldw r2,-20(fp) + 101e3ec: 1001703a wrctl status,r2 + alt_irq_enable_all(cpu_sr); +} + 101e3f0: e037883a mov sp,fp + 101e3f4: dfc00117 ldw ra,4(sp) + 101e3f8: df000017 ldw fp,0(sp) + 101e3fc: dec00204 addi sp,sp,8 + 101e400: f800283a ret + +0101e404 : + * auto-generated alt_sys_init() function. + */ + +void alt_avalon_timer_sc_init (void* base, alt_u32 irq_controller_id, + alt_u32 irq, alt_u32 freq) +{ + 101e404: defff904 addi sp,sp,-28 + 101e408: dfc00615 stw ra,24(sp) + 101e40c: df000515 stw fp,20(sp) + 101e410: df000504 addi fp,sp,20 + 101e414: e13ffc15 stw r4,-16(fp) + 101e418: e17ffd15 stw r5,-12(fp) + 101e41c: e1bffe15 stw r6,-8(fp) + 101e420: e1ffff15 stw r7,-4(fp) + 101e424: e0bfff17 ldw r2,-4(fp) + 101e428: e0bffb15 stw r2,-20(fp) + * in order to initialise the value of the clock frequency. + */ + +static ALT_INLINE int ALT_ALWAYS_INLINE alt_sysclk_init (alt_u32 nticks) +{ + if (! _alt_tick_rate) + 101e42c: 008040b4 movhi r2,258 + 101e430: 10952904 addi r2,r2,21668 + 101e434: 10800017 ldw r2,0(r2) + 101e438: 1004c03a cmpne r2,r2,zero + 101e43c: 1000041e bne r2,zero,101e450 + { + _alt_tick_rate = nticks; + 101e440: 00c040b4 movhi r3,258 + 101e444: 18d52904 addi r3,r3,21668 + 101e448: e0bffb17 ldw r2,-20(fp) + 101e44c: 18800015 stw r2,0(r3) + + alt_sysclk_init (freq); + + /* set to free running mode */ + + IOWR_ALTERA_AVALON_TIMER_CONTROL (base, + 101e450: e0bffc17 ldw r2,-16(fp) + 101e454: 10800104 addi r2,r2,4 + 101e458: 1007883a mov r3,r2 + 101e45c: 008001c4 movi r2,7 + 101e460: 18800035 stwio r2,0(r3) + /* register the interrupt handler, and enable the interrupt */ +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT + alt_ic_isr_register(irq_controller_id, irq, alt_avalon_timer_sc_irq, + base, NULL); +#else + alt_irq_register (irq, base, alt_avalon_timer_sc_irq); + 101e464: e13ffe17 ldw r4,-8(fp) + 101e468: e17ffc17 ldw r5,-16(fp) + 101e46c: 018040b4 movhi r6,258 + 101e470: 31b8e404 addi r6,r6,-7280 + 101e474: 101f9c00 call 101f9c0 +#endif +} + 101e478: e037883a mov sp,fp + 101e47c: dfc00117 ldw ra,4(sp) + 101e480: df000017 ldw fp,0(sp) + 101e484: dec00204 addi sp,sp,8 + 101e488: f800283a ret + +0101e48c : + * + */ + +int +altera_avalon_uart_read_fd(alt_fd* fd, char* buffer, int space) +{ + 101e48c: defffa04 addi sp,sp,-24 + 101e490: dfc00515 stw ra,20(sp) + 101e494: df000415 stw fp,16(sp) + 101e498: df000404 addi fp,sp,16 + 101e49c: e13ffd15 stw r4,-12(fp) + 101e4a0: e17ffe15 stw r5,-8(fp) + 101e4a4: e1bfff15 stw r6,-4(fp) + altera_avalon_uart_dev* dev = (altera_avalon_uart_dev*) fd->dev; + 101e4a8: e0bffd17 ldw r2,-12(fp) + 101e4ac: 10800017 ldw r2,0(r2) + 101e4b0: e0bffc15 stw r2,-16(fp) + + return altera_avalon_uart_read(&dev->state, buffer, space, + 101e4b4: e0bffc17 ldw r2,-16(fp) + 101e4b8: 11000a04 addi r4,r2,40 + 101e4bc: e0bffd17 ldw r2,-12(fp) + 101e4c0: 11c00217 ldw r7,8(r2) + 101e4c4: e17ffe17 ldw r5,-8(fp) + 101e4c8: e1bfff17 ldw r6,-4(fp) + 101e4cc: 101eafc0 call 101eafc + fd->fd_flags); +} + 101e4d0: e037883a mov sp,fp + 101e4d4: dfc00117 ldw ra,4(sp) + 101e4d8: df000017 ldw fp,0(sp) + 101e4dc: dec00204 addi sp,sp,8 + 101e4e0: f800283a ret + +0101e4e4 : + +int +altera_avalon_uart_write_fd(alt_fd* fd, const char* buffer, int space) +{ + 101e4e4: defffa04 addi sp,sp,-24 + 101e4e8: dfc00515 stw ra,20(sp) + 101e4ec: df000415 stw fp,16(sp) + 101e4f0: df000404 addi fp,sp,16 + 101e4f4: e13ffd15 stw r4,-12(fp) + 101e4f8: e17ffe15 stw r5,-8(fp) + 101e4fc: e1bfff15 stw r6,-4(fp) + altera_avalon_uart_dev* dev = (altera_avalon_uart_dev*) fd->dev; + 101e500: e0bffd17 ldw r2,-12(fp) + 101e504: 10800017 ldw r2,0(r2) + 101e508: e0bffc15 stw r2,-16(fp) + + return altera_avalon_uart_write(&dev->state, buffer, space, + 101e50c: e0bffc17 ldw r2,-16(fp) + 101e510: 11000a04 addi r4,r2,40 + 101e514: e0bffd17 ldw r2,-12(fp) + 101e518: 11c00217 ldw r7,8(r2) + 101e51c: e17ffe17 ldw r5,-8(fp) + 101e520: e1bfff17 ldw r6,-4(fp) + 101e524: 101ee0c0 call 101ee0c + fd->fd_flags); +} + 101e528: e037883a mov sp,fp + 101e52c: dfc00117 ldw ra,4(sp) + 101e530: df000017 ldw fp,0(sp) + 101e534: dec00204 addi sp,sp,8 + 101e538: f800283a ret + +0101e53c : + +#endif /* ALTERA_AVALON_UART_USE_IOCTL */ + +int +altera_avalon_uart_close_fd(alt_fd* fd) +{ + 101e53c: defffc04 addi sp,sp,-16 + 101e540: dfc00315 stw ra,12(sp) + 101e544: df000215 stw fp,8(sp) + 101e548: df000204 addi fp,sp,8 + 101e54c: e13fff15 stw r4,-4(fp) + altera_avalon_uart_dev* dev = (altera_avalon_uart_dev*) fd->dev; + 101e550: e0bfff17 ldw r2,-4(fp) + 101e554: 10800017 ldw r2,0(r2) + 101e558: e0bffe15 stw r2,-8(fp) + + return altera_avalon_uart_close(&dev->state, fd->fd_flags); + 101e55c: e0bffe17 ldw r2,-8(fp) + 101e560: 11000a04 addi r4,r2,40 + 101e564: e0bfff17 ldw r2,-4(fp) + 101e568: 11400217 ldw r5,8(r2) + 101e56c: 101ea9c0 call 101ea9c +} + 101e570: e037883a mov sp,fp + 101e574: dfc00117 ldw ra,4(sp) + 101e578: df000017 ldw fp,0(sp) + 101e57c: dec00204 addi sp,sp,8 + 101e580: f800283a ret + +0101e584 : + alt_u32 status); + +void +altera_avalon_uart_init(altera_avalon_uart_state* sp, + alt_u32 irq_controller_id, alt_u32 irq) +{ + 101e584: deffef04 addi sp,sp,-68 + 101e588: dfc01015 stw ra,64(sp) + 101e58c: df000f15 stw fp,60(sp) + 101e590: df000f04 addi fp,sp,60 + 101e594: e13ffa15 stw r4,-24(fp) + 101e598: e17ffb15 stw r5,-20(fp) + 101e59c: e1bffc15 stw r6,-16(fp) + void* base = sp->base; + 101e5a0: e0bffa17 ldw r2,-24(fp) + 101e5a4: 10800017 ldw r2,0(r2) + 101e5a8: e0bff815 stw r2,-32(fp) + /* + * Initialise the read and write flags and the semaphores used to + * protect access to the circular buffers when running in a multi-threaded + * environment. + */ + error = ALT_FLAG_CREATE (&sp->events, 0) || + 101e5ac: e0bffa17 ldw r2,-24(fp) + 101e5b0: 10800704 addi r2,r2,28 + 101e5b4: e0bff515 stw r2,-44(fp) + 101e5b8: e03ff60d sth zero,-40(fp) + +static ALT_INLINE int ALT_ALWAYS_INLINE alt_flag_create (OS_FLAG_GRP** pgroup, + OS_FLAGS flags) +{ + INT8U err; + *pgroup = OSFlagCreate (flags, &err); + 101e5bc: e13ff60b ldhu r4,-40(fp) + 101e5c0: e17ff904 addi r5,fp,-28 + 101e5c4: 10178600 call 1017860 + 101e5c8: 1007883a mov r3,r2 + 101e5cc: e0bff517 ldw r2,-44(fp) + 101e5d0: 10c00015 stw r3,0(r2) + return err; + 101e5d4: e0bff903 ldbu r2,-28(fp) + 101e5d8: 10803fcc andi r2,r2,255 + 101e5dc: 1004c03a cmpne r2,r2,zero + 101e5e0: 10002a1e bne r2,zero,101e68c + 101e5e4: e0bffa17 ldw r2,-24(fp) + 101e5e8: 10800804 addi r2,r2,32 + 101e5ec: e0bff315 stw r2,-52(fp) + 101e5f0: 00800044 movi r2,1 + 101e5f4: e0bff40d sth r2,-48(fp) + */ + +static ALT_INLINE int ALT_ALWAYS_INLINE alt_sem_create (OS_EVENT** sem, + INT16U value) +{ + *sem = OSSemCreate (value); + 101e5f8: e13ff40b ldhu r4,-48(fp) + 101e5fc: 101aa640 call 101aa64 + 101e600: 1007883a mov r3,r2 + 101e604: e0bff317 ldw r2,-52(fp) + 101e608: 10c00015 stw r3,0(r2) + return *sem ? 0 : -1; + 101e60c: e0bff317 ldw r2,-52(fp) + 101e610: 10800017 ldw r2,0(r2) + 101e614: 1005003a cmpeq r2,r2,zero + 101e618: 1000021e bne r2,zero,101e624 + 101e61c: e03ffe15 stw zero,-8(fp) + 101e620: 00000206 br 101e62c + 101e624: 00bfffc4 movi r2,-1 + 101e628: e0bffe15 stw r2,-8(fp) + 101e62c: e0bffe17 ldw r2,-8(fp) + 101e630: 1004c03a cmpne r2,r2,zero + 101e634: 1000151e bne r2,zero,101e68c + 101e638: e0bffa17 ldw r2,-24(fp) + 101e63c: 10800904 addi r2,r2,36 + 101e640: e0bff115 stw r2,-60(fp) + 101e644: 00800044 movi r2,1 + 101e648: e0bff20d sth r2,-56(fp) + */ + +static ALT_INLINE int ALT_ALWAYS_INLINE alt_sem_create (OS_EVENT** sem, + INT16U value) +{ + *sem = OSSemCreate (value); + 101e64c: e13ff20b ldhu r4,-56(fp) + 101e650: 101aa640 call 101aa64 + 101e654: 1007883a mov r3,r2 + 101e658: e0bff117 ldw r2,-60(fp) + 101e65c: 10c00015 stw r3,0(r2) + return *sem ? 0 : -1; + 101e660: e0bff117 ldw r2,-60(fp) + 101e664: 10800017 ldw r2,0(r2) + 101e668: 1005003a cmpeq r2,r2,zero + 101e66c: 1000021e bne r2,zero,101e678 + 101e670: e03ffd15 stw zero,-12(fp) + 101e674: 00000206 br 101e680 + 101e678: 00bfffc4 movi r2,-1 + 101e67c: e0bffd15 stw r2,-12(fp) + 101e680: e0bffd17 ldw r2,-12(fp) + 101e684: 1005003a cmpeq r2,r2,zero + 101e688: 1000031e bne r2,zero,101e698 + 101e68c: 00800044 movi r2,1 + 101e690: e0bfff15 stw r2,-4(fp) + 101e694: 00000106 br 101e69c + 101e698: e03fff15 stw zero,-4(fp) + 101e69c: e0bfff17 ldw r2,-4(fp) + 101e6a0: e0bff715 stw r2,-36(fp) + ALT_SEM_CREATE (&sp->read_lock, 1) || + ALT_SEM_CREATE (&sp->write_lock, 1); + + if (!error) + 101e6a4: e0bff717 ldw r2,-36(fp) + 101e6a8: 1004c03a cmpne r2,r2,zero + 101e6ac: 10000f1e bne r2,zero,101e6ec + { + /* enable interrupts at the device */ + sp->ctrl = ALTERA_AVALON_UART_CONTROL_RTS_MSK | + 101e6b0: e0fffa17 ldw r3,-24(fp) + 101e6b4: 00832004 movi r2,3200 + 101e6b8: 18800115 stw r2,4(r3) + ALTERA_AVALON_UART_CONTROL_RRDY_MSK | + ALTERA_AVALON_UART_CONTROL_DCTS_MSK; + + IOWR_ALTERA_AVALON_UART_CONTROL(base, sp->ctrl); + 101e6bc: e0bff817 ldw r2,-32(fp) + 101e6c0: 11000304 addi r4,r2,12 + 101e6c4: e0bffa17 ldw r2,-24(fp) + 101e6c8: 10800117 ldw r2,4(r2) + 101e6cc: 1007883a mov r3,r2 + 101e6d0: 2005883a mov r2,r4 + 101e6d4: 10c00035 stwio r3,0(r2) + /* register the interrupt handler */ +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT + alt_ic_isr_register(irq_controller_id, irq, altera_avalon_uart_irq, sp, + 0x0); +#else + alt_irq_register (irq, sp, altera_avalon_uart_irq); + 101e6d8: e13ffc17 ldw r4,-16(fp) + 101e6dc: e17ffa17 ldw r5,-24(fp) + 101e6e0: 018040b4 movhi r6,258 + 101e6e4: 31b9c004 addi r6,r6,-6400 + 101e6e8: 101f9c00 call 101f9c0 +#endif + } +} + 101e6ec: e037883a mov sp,fp + 101e6f0: dfc00117 ldw ra,4(sp) + 101e6f4: df000017 ldw fp,0(sp) + 101e6f8: dec00204 addi sp,sp,8 + 101e6fc: f800283a ret + +0101e700 : +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT +static void altera_avalon_uart_irq(void* context) +#else +static void altera_avalon_uart_irq(void* context, alt_u32 id) +#endif +{ + 101e700: defff904 addi sp,sp,-28 + 101e704: dfc00615 stw ra,24(sp) + 101e708: df000515 stw fp,20(sp) + 101e70c: df000504 addi fp,sp,20 + 101e710: e13ffe15 stw r4,-8(fp) + 101e714: e17fff15 stw r5,-4(fp) + alt_u32 status; + + altera_avalon_uart_state* sp = (altera_avalon_uart_state*) context; + 101e718: e0bffe17 ldw r2,-8(fp) + 101e71c: e0bffc15 stw r2,-16(fp) + void* base = sp->base; + 101e720: e0bffc17 ldw r2,-16(fp) + 101e724: 10800017 ldw r2,0(r2) + 101e728: e0bffb15 stw r2,-20(fp) + /* + * Read the status register in order to determine the cause of the + * interrupt. + */ + + status = IORD_ALTERA_AVALON_UART_STATUS(base); + 101e72c: e0bffb17 ldw r2,-20(fp) + 101e730: 10800204 addi r2,r2,8 + 101e734: 10800037 ldwio r2,0(r2) + 101e738: e0bffd15 stw r2,-12(fp) + + /* Clear any error flags set at the device */ + IOWR_ALTERA_AVALON_UART_STATUS(base, 0); + 101e73c: e0bffb17 ldw r2,-20(fp) + 101e740: 10800204 addi r2,r2,8 + 101e744: 10000035 stwio zero,0(r2) + + /* Dummy read to ensure IRQ is negated before ISR returns */ + IORD_ALTERA_AVALON_UART_STATUS(base); + 101e748: e0bffb17 ldw r2,-20(fp) + 101e74c: 10800204 addi r2,r2,8 + 101e750: 10800037 ldwio r2,0(r2) + + /* process a read irq */ + if (status & ALTERA_AVALON_UART_STATUS_RRDY_MSK) + 101e754: e0bffd17 ldw r2,-12(fp) + 101e758: 1080200c andi r2,r2,128 + 101e75c: 1005003a cmpeq r2,r2,zero + 101e760: 1000031e bne r2,zero,101e770 + { + altera_avalon_uart_rxirq(sp, status); + 101e764: e13ffc17 ldw r4,-16(fp) + 101e768: e17ffd17 ldw r5,-12(fp) + 101e76c: 101e7a00 call 101e7a0 + } + + /* process a write irq */ + if (status & (ALTERA_AVALON_UART_STATUS_TRDY_MSK | + 101e770: e0bffd17 ldw r2,-12(fp) + 101e774: 1081100c andi r2,r2,1088 + 101e778: 1005003a cmpeq r2,r2,zero + 101e77c: 1000031e bne r2,zero,101e78c + ALTERA_AVALON_UART_STATUS_DCTS_MSK)) + { + altera_avalon_uart_txirq(sp, status); + 101e780: e13ffc17 ldw r4,-16(fp) + 101e784: e17ffd17 ldw r5,-12(fp) + 101e788: 101e8dc0 call 101e8dc + } + + +} + 101e78c: e037883a mov sp,fp + 101e790: dfc00117 ldw ra,4(sp) + 101e794: df000017 ldw fp,0(sp) + 101e798: dec00204 addi sp,sp,8 + 101e79c: f800283a ret + +0101e7a0 : + * the receive circular buffer, and sets the apropriate flags to indicate + * that there is data ready to be processed. + */ +static void +altera_avalon_uart_rxirq(altera_avalon_uart_state* sp, alt_u32 status) +{ + 101e7a0: defff804 addi sp,sp,-32 + 101e7a4: dfc00715 stw ra,28(sp) + 101e7a8: df000615 stw fp,24(sp) + 101e7ac: df000604 addi fp,sp,24 + 101e7b0: e13ffe15 stw r4,-8(fp) + 101e7b4: e17fff15 stw r5,-4(fp) + alt_u32 next; + + /* If there was an error, discard the data */ + + if (status & (ALTERA_AVALON_UART_STATUS_PE_MSK | + 101e7b8: e0bfff17 ldw r2,-4(fp) + 101e7bc: 108000cc andi r2,r2,3 + 101e7c0: 1004c03a cmpne r2,r2,zero + 101e7c4: 1000401e bne r2,zero,101e8c8 + * In a multi-threaded environment, set the read event flag to indicate + * that there is data ready. This is only done if the circular buffer was + * previously empty. + */ + + if (sp->rx_end == sp->rx_start) + 101e7c8: e0bffe17 ldw r2,-8(fp) + 101e7cc: 10c00317 ldw r3,12(r2) + 101e7d0: e0bffe17 ldw r2,-8(fp) + 101e7d4: 10800217 ldw r2,8(r2) + 101e7d8: 1880121e bne r3,r2,101e824 + { + ALT_FLAG_POST (sp->events, ALT_UART_READ_RDY, OS_FLAG_SET); + 101e7dc: e0bffe17 ldw r2,-8(fp) + 101e7e0: 10800717 ldw r2,28(r2) + 101e7e4: e0bffa15 stw r2,-24(fp) + 101e7e8: 00800044 movi r2,1 + 101e7ec: e0bffb0d sth r2,-20(fp) + 101e7f0: 00800044 movi r2,1 + 101e7f4: e0bffb85 stb r2,-18(fp) + OS_FLAGS flags, + INT8U opt) +{ + INT8U err; + + if (OSRunning) + 101e7f8: 008040b4 movhi r2,258 + 101e7fc: 10951444 addi r2,r2,21585 + 101e800: 10800003 ldbu r2,0(r2) + 101e804: 10803fcc andi r2,r2,255 + 101e808: 1005003a cmpeq r2,r2,zero + 101e80c: 1000051e bne r2,zero,101e824 + { + OSFlagPost (group, flags, opt, &err); + 101e810: e17ffb0b ldhu r5,-20(fp) + 101e814: e1bffb83 ldbu r6,-18(fp) + 101e818: e1fffd04 addi r7,fp,-12 + 101e81c: e13ffa17 ldw r4,-24(fp) + 101e820: 10185880 call 1018588 + } + + /* Determine which slot to use next in the circular buffer */ + + next = (sp->rx_end + 1) & ALT_AVALON_UART_BUF_MSK; + 101e824: e0bffe17 ldw r2,-8(fp) + 101e828: 10800317 ldw r2,12(r2) + 101e82c: 10800044 addi r2,r2,1 + 101e830: 10800fcc andi r2,r2,63 + 101e834: e0bffc15 stw r2,-16(fp) + + /* Transfer data from the device to the circular buffer */ + + sp->rx_buf[sp->rx_end] = IORD_ALTERA_AVALON_UART_RXDATA(sp->base); + 101e838: e0bffe17 ldw r2,-8(fp) + 101e83c: 11000317 ldw r4,12(r2) + 101e840: e0bffe17 ldw r2,-8(fp) + 101e844: 10800017 ldw r2,0(r2) + 101e848: 10800037 ldwio r2,0(r2) + 101e84c: 1007883a mov r3,r2 + 101e850: e0bffe17 ldw r2,-8(fp) + 101e854: 2085883a add r2,r4,r2 + 101e858: 10800a04 addi r2,r2,40 + 101e85c: 10c00005 stb r3,0(r2) + + sp->rx_end = next; + 101e860: e0fffe17 ldw r3,-8(fp) + 101e864: e0bffc17 ldw r2,-16(fp) + 101e868: 18800315 stw r2,12(r3) + + next = (sp->rx_end + 1) & ALT_AVALON_UART_BUF_MSK; + 101e86c: e0bffe17 ldw r2,-8(fp) + 101e870: 10800317 ldw r2,12(r2) + 101e874: 10800044 addi r2,r2,1 + 101e878: 10800fcc andi r2,r2,63 + 101e87c: e0bffc15 stw r2,-16(fp) + /* + * If the cicular buffer was full, disable interrupts. Interrupts will be + * re-enabled when data is removed from the buffer. + */ + + if (next == sp->rx_start) + 101e880: e0bffe17 ldw r2,-8(fp) + 101e884: 10c00217 ldw r3,8(r2) + 101e888: e0bffc17 ldw r2,-16(fp) + 101e88c: 18800e1e bne r3,r2,101e8c8 + { + sp->ctrl &= ~ALTERA_AVALON_UART_CONTROL_RRDY_MSK; + 101e890: e0bffe17 ldw r2,-8(fp) + 101e894: 10c00117 ldw r3,4(r2) + 101e898: 00bfdfc4 movi r2,-129 + 101e89c: 1886703a and r3,r3,r2 + 101e8a0: e0bffe17 ldw r2,-8(fp) + 101e8a4: 10c00115 stw r3,4(r2) + IOWR_ALTERA_AVALON_UART_CONTROL(sp->base, sp->ctrl); + 101e8a8: e0bffe17 ldw r2,-8(fp) + 101e8ac: 10800017 ldw r2,0(r2) + 101e8b0: 11000304 addi r4,r2,12 + 101e8b4: e0bffe17 ldw r2,-8(fp) + 101e8b8: 10800117 ldw r2,4(r2) + 101e8bc: 1007883a mov r3,r2 + 101e8c0: 2005883a mov r2,r4 + 101e8c4: 10c00035 stwio r3,0(r2) + } +} + 101e8c8: e037883a mov sp,fp + 101e8cc: dfc00117 ldw ra,4(sp) + 101e8d0: df000017 ldw fp,0(sp) + 101e8d4: dec00204 addi sp,sp,8 + 101e8d8: f800283a ret + +0101e8dc : + * buffer to the device, and sets the apropriate flags to indicate that + * there is data ready to be processed. + */ +static void +altera_avalon_uart_txirq(altera_avalon_uart_state* sp, alt_u32 status) +{ + 101e8dc: defffa04 addi sp,sp,-24 + 101e8e0: dfc00515 stw ra,20(sp) + 101e8e4: df000415 stw fp,16(sp) + 101e8e8: df000404 addi fp,sp,16 + 101e8ec: e13ffe15 stw r4,-8(fp) + 101e8f0: e17fff15 stw r5,-4(fp) + /* Transfer data if there is some ready to be transfered */ + + if (sp->tx_start != sp->tx_end) + 101e8f4: e0bffe17 ldw r2,-8(fp) + 101e8f8: 10c00417 ldw r3,16(r2) + 101e8fc: e0bffe17 ldw r2,-8(fp) + 101e900: 10800517 ldw r2,20(r2) + 101e904: 18804d26 beq r3,r2,101ea3c + /* + * If the device is using flow control (i.e. RTS/CTS), then the + * transmitter is required to throttle if CTS is high. + */ + + if (!(sp->flags & ALT_AVALON_UART_FC) || + 101e908: e0bffe17 ldw r2,-8(fp) + 101e90c: 10800617 ldw r2,24(r2) + 101e910: 1080008c andi r2,r2,2 + 101e914: 1005003a cmpeq r2,r2,zero + 101e918: 1000041e bne r2,zero,101e92c + 101e91c: e0bfff17 ldw r2,-4(fp) + 101e920: 1082000c andi r2,r2,2048 + 101e924: 1005003a cmpeq r2,r2,zero + 101e928: 1000351e bne r2,zero,101ea00 + * In a multi-threaded environment, set the write event flag to indicate + * that there is space in the circular buffer. This is only done if the + * buffer was previously empty. + */ + + if (sp->tx_start == ((sp->tx_end + 1) & ALT_AVALON_UART_BUF_MSK)) + 101e92c: e0bffe17 ldw r2,-8(fp) + 101e930: 10c00417 ldw r3,16(r2) + 101e934: e0bffe17 ldw r2,-8(fp) + 101e938: 10800517 ldw r2,20(r2) + 101e93c: 10800044 addi r2,r2,1 + 101e940: 10800fcc andi r2,r2,63 + 101e944: 1880121e bne r3,r2,101e990 + { + ALT_FLAG_POST (sp->events, + 101e948: e0bffe17 ldw r2,-8(fp) + 101e94c: 10800717 ldw r2,28(r2) + 101e950: e0bffc15 stw r2,-16(fp) + 101e954: 00800084 movi r2,2 + 101e958: e0bffd0d sth r2,-12(fp) + 101e95c: 00800044 movi r2,1 + 101e960: e0bffd85 stb r2,-10(fp) + OS_FLAGS flags, + INT8U opt) +{ + INT8U err; + + if (OSRunning) + 101e964: 008040b4 movhi r2,258 + 101e968: 10951444 addi r2,r2,21585 + 101e96c: 10800003 ldbu r2,0(r2) + 101e970: 10803fcc andi r2,r2,255 + 101e974: 1005003a cmpeq r2,r2,zero + 101e978: 1000051e bne r2,zero,101e990 + { + OSFlagPost (group, flags, opt, &err); + 101e97c: e17ffd0b ldhu r5,-12(fp) + 101e980: e1bffd83 ldbu r6,-10(fp) + 101e984: e1fffdc4 addi r7,fp,-9 + 101e988: e13ffc17 ldw r4,-16(fp) + 101e98c: 10185880 call 1018588 + OS_FLAG_SET); + } + + /* Write the data to the device */ + + IOWR_ALTERA_AVALON_UART_TXDATA(sp->base, sp->tx_buf[sp->tx_start]); + 101e990: e0bffe17 ldw r2,-8(fp) + 101e994: 10800017 ldw r2,0(r2) + 101e998: 11000104 addi r4,r2,4 + 101e99c: e0bffe17 ldw r2,-8(fp) + 101e9a0: 10c00417 ldw r3,16(r2) + 101e9a4: e0bffe17 ldw r2,-8(fp) + 101e9a8: 1885883a add r2,r3,r2 + 101e9ac: 10801a04 addi r2,r2,104 + 101e9b0: 10800003 ldbu r2,0(r2) + 101e9b4: 10c03fcc andi r3,r2,255 + 101e9b8: 2005883a mov r2,r4 + 101e9bc: 10c00035 stwio r3,0(r2) + + sp->tx_start = (++sp->tx_start) & ALT_AVALON_UART_BUF_MSK; + 101e9c0: e0bffe17 ldw r2,-8(fp) + 101e9c4: 10800417 ldw r2,16(r2) + 101e9c8: 10c00044 addi r3,r2,1 + 101e9cc: e0bffe17 ldw r2,-8(fp) + 101e9d0: 10c00415 stw r3,16(r2) + 101e9d4: e0bffe17 ldw r2,-8(fp) + 101e9d8: 10800417 ldw r2,16(r2) + 101e9dc: 10c00fcc andi r3,r2,63 + 101e9e0: e0bffe17 ldw r2,-8(fp) + 101e9e4: 10c00415 stw r3,16(r2) + /* + * In case the tranmit interrupt had previously been disabled by + * detecting a low value on CTS, it is reenabled here. + */ + + sp->ctrl |= ALTERA_AVALON_UART_CONTROL_TRDY_MSK; + 101e9e8: e0bffe17 ldw r2,-8(fp) + 101e9ec: 10800117 ldw r2,4(r2) + 101e9f0: 10c01014 ori r3,r2,64 + 101e9f4: e0bffe17 ldw r2,-8(fp) + 101e9f8: 10c00115 stw r3,4(r2) + /* + * If the device is using flow control (i.e. RTS/CTS), then the + * transmitter is required to throttle if CTS is high. + */ + + if (!(sp->flags & ALT_AVALON_UART_FC) || + 101e9fc: 00000f06 br 101ea3c + * the last write to the status register. To avoid this resulting in + * deadlock, it's necessary to re-check the status register here + * before throttling. + */ + + status = IORD_ALTERA_AVALON_UART_STATUS(sp->base); + 101ea00: e0bffe17 ldw r2,-8(fp) + 101ea04: 10800017 ldw r2,0(r2) + 101ea08: 10800204 addi r2,r2,8 + 101ea0c: 10800037 ldwio r2,0(r2) + 101ea10: e0bfff15 stw r2,-4(fp) + + if (!(status & ALTERA_AVALON_UART_STATUS_CTS_MSK)) + 101ea14: e0bfff17 ldw r2,-4(fp) + 101ea18: 1082000c andi r2,r2,2048 + 101ea1c: 1004c03a cmpne r2,r2,zero + 101ea20: 1000061e bne r2,zero,101ea3c + { + sp->ctrl &= ~ALTERA_AVALON_UART_CONTROL_TRDY_MSK; + 101ea24: e0bffe17 ldw r2,-8(fp) + 101ea28: 10c00117 ldw r3,4(r2) + 101ea2c: 00bfefc4 movi r2,-65 + 101ea30: 1886703a and r3,r3,r2 + 101ea34: e0bffe17 ldw r2,-8(fp) + 101ea38: 10c00115 stw r3,4(r2) + /* + * If the circular buffer is empty, disable the interrupt. This will be + * re-enabled when new data is placed in the buffer. + */ + + if (sp->tx_start == sp->tx_end) + 101ea3c: e0bffe17 ldw r2,-8(fp) + 101ea40: 10c00417 ldw r3,16(r2) + 101ea44: e0bffe17 ldw r2,-8(fp) + 101ea48: 10800517 ldw r2,20(r2) + 101ea4c: 1880061e bne r3,r2,101ea68 + { + sp->ctrl &= ~(ALTERA_AVALON_UART_CONTROL_TRDY_MSK | + 101ea50: e0bffe17 ldw r2,-8(fp) + 101ea54: 10c00117 ldw r3,4(r2) + 101ea58: 00beefc4 movi r2,-1089 + 101ea5c: 1886703a and r3,r3,r2 + 101ea60: e0bffe17 ldw r2,-8(fp) + 101ea64: 10c00115 stw r3,4(r2) + ALTERA_AVALON_UART_CONTROL_DCTS_MSK); + } + + IOWR_ALTERA_AVALON_UART_CONTROL(sp->base, sp->ctrl); + 101ea68: e0bffe17 ldw r2,-8(fp) + 101ea6c: 10800017 ldw r2,0(r2) + 101ea70: 11000304 addi r4,r2,12 + 101ea74: e0bffe17 ldw r2,-8(fp) + 101ea78: 10800117 ldw r2,4(r2) + 101ea7c: 1007883a mov r3,r2 + 101ea80: 2005883a mov r2,r4 + 101ea84: 10c00035 stwio r3,0(r2) +} + 101ea88: e037883a mov sp,fp + 101ea8c: dfc00117 ldw ra,4(sp) + 101ea90: df000017 ldw fp,0(sp) + 101ea94: dec00204 addi sp,sp,8 + 101ea98: f800283a ret + +0101ea9c : + * The close routine is not implemented for the small driver; instead it will + * map to null. This is because the small driver simply waits while characters + * are transmitted; there is no interrupt-serviced buffer to empty + */ +int altera_avalon_uart_close(altera_avalon_uart_state* sp, int flags) +{ + 101ea9c: defffc04 addi sp,sp,-16 + 101eaa0: df000315 stw fp,12(sp) + 101eaa4: df000304 addi fp,sp,12 + 101eaa8: e13ffd15 stw r4,-12(fp) + 101eaac: e17ffe15 stw r5,-8(fp) + /* + * Wait for all transmit data to be emptied by the UART ISR. + */ + while (sp->tx_start != sp->tx_end) { + 101eab0: 00000706 br 101ead0 + if (flags & O_NONBLOCK) { + 101eab4: e0bffe17 ldw r2,-8(fp) + 101eab8: 1090000c andi r2,r2,16384 + 101eabc: 1005003a cmpeq r2,r2,zero + 101eac0: 1000031e bne r2,zero,101ead0 + return -EWOULDBLOCK; + 101eac4: 00bffd44 movi r2,-11 + 101eac8: e0bfff15 stw r2,-4(fp) + 101eacc: 00000606 br 101eae8 +int altera_avalon_uart_close(altera_avalon_uart_state* sp, int flags) +{ + /* + * Wait for all transmit data to be emptied by the UART ISR. + */ + while (sp->tx_start != sp->tx_end) { + 101ead0: e0bffd17 ldw r2,-12(fp) + 101ead4: 10c00417 ldw r3,16(r2) + 101ead8: e0bffd17 ldw r2,-12(fp) + 101eadc: 10800517 ldw r2,20(r2) + 101eae0: 18bff41e bne r3,r2,101eab4 + if (flags & O_NONBLOCK) { + return -EWOULDBLOCK; + } + } + + return 0; + 101eae4: e03fff15 stw zero,-4(fp) + 101eae8: e0bfff17 ldw r2,-4(fp) +} + 101eaec: e037883a mov sp,fp + 101eaf0: df000017 ldw fp,0(sp) + 101eaf4: dec00104 addi sp,sp,4 + 101eaf8: f800283a ret + +0101eafc : + */ + +int +altera_avalon_uart_read(altera_avalon_uart_state* sp, char* ptr, int len, + int flags) +{ + 101eafc: deffe904 addi sp,sp,-92 + 101eb00: dfc01615 stw ra,88(sp) + 101eb04: df001515 stw fp,84(sp) + 101eb08: df001504 addi fp,sp,84 + 101eb0c: e13ffb15 stw r4,-20(fp) + 101eb10: e17ffc15 stw r5,-16(fp) + 101eb14: e1bffd15 stw r6,-12(fp) + 101eb18: e1fffe15 stw r7,-8(fp) + alt_irq_context context; + int block; + alt_u32 next; + alt_u8 read_would_block = 0; + 101eb1c: e03ff605 stb zero,-40(fp) + int count = 0; + 101eb20: e03ff515 stw zero,-44(fp) + /* + * Construct a flag to indicate whether the device is being accessed in + * blocking or non-blocking mode. + */ + + block = !(flags & O_NONBLOCK); + 101eb24: e0bffe17 ldw r2,-8(fp) + 101eb28: 1090000c andi r2,r2,16384 + 101eb2c: 1005003a cmpeq r2,r2,zero + 101eb30: e0bff815 stw r2,-32(fp) + /* + * When running in a multi threaded environment, obtain the "read_lock" + * semaphore. This ensures that reading from the device is thread-safe. + */ + + ALT_SEM_PEND (sp->read_lock, 0); + 101eb34: e0bffb17 ldw r2,-20(fp) + 101eb38: 10800817 ldw r2,32(r2) + 101eb3c: e0bff315 stw r2,-52(fp) + 101eb40: e03ff40d sth zero,-48(fp) + +static ALT_INLINE int ALT_ALWAYS_INLINE alt_sem_pend (OS_EVENT* sem, + INT16U timeout) +{ + INT8U err; + OSSemPend (sem, timeout, &err); + 101eb44: e17ff40b ldhu r5,-48(fp) + 101eb48: e1bffa04 addi r6,fp,-24 + 101eb4c: e13ff317 ldw r4,-52(fp) + 101eb50: 101ae180 call 101ae18 + /* + * Calculate which slot in the circular buffer is the next one to read + * data from. + */ + + next = (sp->rx_start + 1) & ALT_AVALON_UART_BUF_MSK; + 101eb54: e0bffb17 ldw r2,-20(fp) + 101eb58: 10800217 ldw r2,8(r2) + 101eb5c: 10800044 addi r2,r2,1 + 101eb60: 10800fcc andi r2,r2,63 + 101eb64: e0bff715 stw r2,-36(fp) + /* + * Read the required amount of data, until the circular buffer runs + * empty + */ + + while ((count < len) && (sp->rx_start != sp->rx_end)) + 101eb68: 00001906 br 101ebd0 + { + count++; + 101eb6c: e0bff517 ldw r2,-44(fp) + 101eb70: 10800044 addi r2,r2,1 + 101eb74: e0bff515 stw r2,-44(fp) + *ptr++ = sp->rx_buf[sp->rx_start]; + 101eb78: e0bffb17 ldw r2,-20(fp) + 101eb7c: 10c00217 ldw r3,8(r2) + 101eb80: e0bffb17 ldw r2,-20(fp) + 101eb84: 1885883a add r2,r3,r2 + 101eb88: 10800a04 addi r2,r2,40 + 101eb8c: 10800003 ldbu r2,0(r2) + 101eb90: 1007883a mov r3,r2 + 101eb94: e0bffc17 ldw r2,-16(fp) + 101eb98: 10c00005 stb r3,0(r2) + 101eb9c: e0bffc17 ldw r2,-16(fp) + 101eba0: 10800044 addi r2,r2,1 + 101eba4: e0bffc15 stw r2,-16(fp) + + sp->rx_start = (++sp->rx_start) & ALT_AVALON_UART_BUF_MSK; + 101eba8: e0bffb17 ldw r2,-20(fp) + 101ebac: 10800217 ldw r2,8(r2) + 101ebb0: 10c00044 addi r3,r2,1 + 101ebb4: e0bffb17 ldw r2,-20(fp) + 101ebb8: 10c00215 stw r3,8(r2) + 101ebbc: e0bffb17 ldw r2,-20(fp) + 101ebc0: 10800217 ldw r2,8(r2) + 101ebc4: 10c00fcc andi r3,r2,63 + 101ebc8: e0bffb17 ldw r2,-20(fp) + 101ebcc: 10c00215 stw r3,8(r2) + /* + * Read the required amount of data, until the circular buffer runs + * empty + */ + + while ((count < len) && (sp->rx_start != sp->rx_end)) + 101ebd0: e0fff517 ldw r3,-44(fp) + 101ebd4: e0bffd17 ldw r2,-12(fp) + 101ebd8: 1880050e bge r3,r2,101ebf0 + 101ebdc: e0bffb17 ldw r2,-20(fp) + 101ebe0: 10c00217 ldw r3,8(r2) + 101ebe4: e0bffb17 ldw r2,-20(fp) + 101ebe8: 10800317 ldw r2,12(r2) + 101ebec: 18bfdf1e bne r3,r2,101eb6c + /* + * If no data has been transferred, the circular buffer is empty, and + * this is not a non-blocking access, block waiting for data to arrive. + */ + + if (!count && (sp->rx_start == sp->rx_end)) + 101ebf0: e0bff517 ldw r2,-44(fp) + 101ebf4: 1004c03a cmpne r2,r2,zero + 101ebf8: 10003c1e bne r2,zero,101ecec + 101ebfc: e0bffb17 ldw r2,-20(fp) + 101ec00: 10c00217 ldw r3,8(r2) + 101ec04: e0bffb17 ldw r2,-20(fp) + 101ec08: 10800317 ldw r2,12(r2) + 101ec0c: 1880371e bne r3,r2,101ecec + { + if (!block) + 101ec10: e0bff817 ldw r2,-32(fp) + 101ec14: 1004c03a cmpne r2,r2,zero + 101ec18: 1000061e bne r2,zero,101ec34 + { + /* Set errno to indicate the reason we're not returning any data */ + + ALT_ERRNO = EWOULDBLOCK; + 101ec1c: 101edac0 call 101edac + 101ec20: 00c002c4 movi r3,11 + 101ec24: 10c00015 stw r3,0(r2) + read_would_block = 1; + 101ec28: 00800044 movi r2,1 + 101ec2c: e0bff605 stb r2,-40(fp) + break; + 101ec30: 00003406 br 101ed04 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 101ec34: 0005303a rdctl r2,status + 101ec38: e0bff215 stw r2,-56(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 101ec3c: e0fff217 ldw r3,-56(fp) + 101ec40: 00bfff84 movi r2,-2 + 101ec44: 1884703a and r2,r3,r2 + 101ec48: 1001703a wrctl status,r2 + + return context; + 101ec4c: e0bff217 ldw r2,-56(fp) + { + /* Block waiting for some data to arrive */ + + /* First, ensure read interrupts are enabled to avoid deadlock */ + + context = alt_irq_disable_all (); + 101ec50: e0bff915 stw r2,-28(fp) + sp->ctrl |= ALTERA_AVALON_UART_CONTROL_RRDY_MSK; + 101ec54: e0bffb17 ldw r2,-20(fp) + 101ec58: 10800117 ldw r2,4(r2) + 101ec5c: 10c02014 ori r3,r2,128 + 101ec60: e0bffb17 ldw r2,-20(fp) + 101ec64: 10c00115 stw r3,4(r2) + IOWR_ALTERA_AVALON_UART_CONTROL(sp->base, sp->ctrl); + 101ec68: e0bffb17 ldw r2,-20(fp) + 101ec6c: 10800017 ldw r2,0(r2) + 101ec70: 11000304 addi r4,r2,12 + 101ec74: e0bffb17 ldw r2,-20(fp) + 101ec78: 10800117 ldw r2,4(r2) + 101ec7c: 1007883a mov r3,r2 + 101ec80: 2005883a mov r2,r4 + 101ec84: 10c00035 stwio r3,0(r2) + 101ec88: e0bff917 ldw r2,-28(fp) + 101ec8c: e0bff115 stw r2,-60(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 101ec90: e0bff117 ldw r2,-60(fp) + 101ec94: 1001703a wrctl status,r2 + * flag set in the interrupt service routine. This avoids wasting CPU + * cycles waiting in this thread, when we could be doing something more + * profitable elsewhere. + */ + + ALT_FLAG_PEND (sp->events, + 101ec98: e0bffb17 ldw r2,-20(fp) + 101ec9c: 10800717 ldw r2,28(r2) + 101eca0: e0bfee15 stw r2,-72(fp) + 101eca4: 00800044 movi r2,1 + 101eca8: e0bfef0d sth r2,-68(fp) + 101ecac: 00bfe0c4 movi r2,-125 + 101ecb0: e0bfef85 stb r2,-66(fp) + 101ecb4: e03ff00d sth zero,-64(fp) + OS_FLAGS flags, + INT8U wait_type, + INT16U timeout) +{ + INT8U err; + if (OSRunning) + 101ecb8: 008040b4 movhi r2,258 + 101ecbc: 10951444 addi r2,r2,21585 + 101ecc0: 10800003 ldbu r2,0(r2) + 101ecc4: 10803fcc andi r2,r2,255 + 101ecc8: 1005003a cmpeq r2,r2,zero + 101eccc: 1000071e bne r2,zero,101ecec + { + OSFlagPend (group, flags, wait_type, timeout, &err); + 101ecd0: e17fef0b ldhu r5,-68(fp) + 101ecd4: e1bfef83 ldbu r6,-66(fp) + 101ecd8: e1fff00b ldhu r7,-64(fp) + 101ecdc: e0bffa44 addi r2,fp,-23 + 101ece0: d8800015 stw r2,0(sp) + 101ece4: e13fee17 ldw r4,-72(fp) + 101ece8: 1017edc0 call 1017edc + OS_FLAG_WAIT_SET_ANY + OS_FLAG_CONSUME, + 0); + } + } + } + while (!count && len); + 101ecec: e0bff517 ldw r2,-44(fp) + 101ecf0: 1004c03a cmpne r2,r2,zero + 101ecf4: 1000031e bne r2,zero,101ed04 + 101ecf8: e0bffd17 ldw r2,-12(fp) + 101ecfc: 1004c03a cmpne r2,r2,zero + 101ed00: 103fb31e bne r2,zero,101ebd0 + /* + * Now that access to the circular buffer is complete, release the read + * semaphore so that other threads can access the buffer. + */ + + ALT_SEM_POST (sp->read_lock); + 101ed04: e0bffb17 ldw r2,-20(fp) + 101ed08: 11000817 ldw r4,32(r2) + 101ed0c: 101b2100 call 101b210 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 101ed10: 0005303a rdctl r2,status + 101ed14: e0bfed15 stw r2,-76(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 101ed18: e0ffed17 ldw r3,-76(fp) + 101ed1c: 00bfff84 movi r2,-2 + 101ed20: 1884703a and r2,r3,r2 + 101ed24: 1001703a wrctl status,r2 + + return context; + 101ed28: e0bfed17 ldw r2,-76(fp) + /* + * Ensure that interrupts are enabled, so that the circular buffer can + * re-fill. + */ + + context = alt_irq_disable_all (); + 101ed2c: e0bff915 stw r2,-28(fp) + sp->ctrl |= ALTERA_AVALON_UART_CONTROL_RRDY_MSK; + 101ed30: e0bffb17 ldw r2,-20(fp) + 101ed34: 10800117 ldw r2,4(r2) + 101ed38: 10c02014 ori r3,r2,128 + 101ed3c: e0bffb17 ldw r2,-20(fp) + 101ed40: 10c00115 stw r3,4(r2) + IOWR_ALTERA_AVALON_UART_CONTROL(sp->base, sp->ctrl); + 101ed44: e0bffb17 ldw r2,-20(fp) + 101ed48: 10800017 ldw r2,0(r2) + 101ed4c: 11000304 addi r4,r2,12 + 101ed50: e0bffb17 ldw r2,-20(fp) + 101ed54: 10800117 ldw r2,4(r2) + 101ed58: 1007883a mov r3,r2 + 101ed5c: 2005883a mov r2,r4 + 101ed60: 10c00035 stwio r3,0(r2) + 101ed64: e0bff917 ldw r2,-28(fp) + 101ed68: e0bfec15 stw r2,-80(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 101ed6c: e0bfec17 ldw r2,-80(fp) + 101ed70: 1001703a wrctl status,r2 + alt_irq_enable_all (context); + + /* Return the number of bytes read */ + if(read_would_block) { + 101ed74: e0bff603 ldbu r2,-40(fp) + 101ed78: 1005003a cmpeq r2,r2,zero + 101ed7c: 1000031e bne r2,zero,101ed8c + return ~EWOULDBLOCK; + 101ed80: 00bffd04 movi r2,-12 + 101ed84: e0bfff15 stw r2,-4(fp) + 101ed88: 00000206 br 101ed94 + } + else { + return count; + 101ed8c: e0bff517 ldw r2,-44(fp) + 101ed90: e0bfff15 stw r2,-4(fp) + 101ed94: e0bfff17 ldw r2,-4(fp) + } +} + 101ed98: e037883a mov sp,fp + 101ed9c: dfc00117 ldw ra,4(sp) + 101eda0: df000017 ldw fp,0(sp) + 101eda4: dec00204 addi sp,sp,8 + 101eda8: f800283a ret + +0101edac : +#undef errno + +extern int errno; + +static ALT_INLINE int* alt_get_errno(void) +{ + 101edac: defffd04 addi sp,sp,-12 + 101edb0: dfc00215 stw ra,8(sp) + 101edb4: df000115 stw fp,4(sp) + 101edb8: df000104 addi fp,sp,4 + return ((alt_errno) ? alt_errno() : &errno); + 101edbc: 008040b4 movhi r2,258 + 101edc0: 108dd104 addi r2,r2,14148 + 101edc4: 10800017 ldw r2,0(r2) + 101edc8: 1005003a cmpeq r2,r2,zero + 101edcc: 1000061e bne r2,zero,101ede8 + 101edd0: 008040b4 movhi r2,258 + 101edd4: 108dd104 addi r2,r2,14148 + 101edd8: 10800017 ldw r2,0(r2) + 101eddc: 103ee83a callr r2 + 101ede0: e0bfff15 stw r2,-4(fp) + 101ede4: 00000306 br 101edf4 + 101ede8: 008040b4 movhi r2,258 + 101edec: 10950804 addi r2,r2,21536 + 101edf0: e0bfff15 stw r2,-4(fp) + 101edf4: e0bfff17 ldw r2,-4(fp) +} + 101edf8: e037883a mov sp,fp + 101edfc: dfc00117 ldw ra,4(sp) + 101ee00: df000017 ldw fp,0(sp) + 101ee04: dec00204 addi sp,sp,8 + 101ee08: f800283a ret + +0101ee0c : + */ + +int +altera_avalon_uart_write(altera_avalon_uart_state* sp, const char* ptr, int len, + int flags) +{ + 101ee0c: deffeb04 addi sp,sp,-84 + 101ee10: dfc01415 stw ra,80(sp) + 101ee14: df001315 stw fp,76(sp) + 101ee18: df001304 addi fp,sp,76 + 101ee1c: e13ffc15 stw r4,-16(fp) + 101ee20: e17ffd15 stw r5,-12(fp) + 101ee24: e1bffe15 stw r6,-8(fp) + 101ee28: e1ffff15 stw r7,-4(fp) + alt_irq_context context; + int no_block; + alt_u32 next; + int count = len; + 101ee2c: e0bffe17 ldw r2,-8(fp) + 101ee30: e0bff715 stw r2,-36(fp) + /* + * Construct a flag to indicate whether the device is being accessed in + * blocking or non-blocking mode. + */ + + no_block = (flags & O_NONBLOCK); + 101ee34: e0bfff17 ldw r2,-4(fp) + 101ee38: 1090000c andi r2,r2,16384 + 101ee3c: e0bff915 stw r2,-28(fp) + /* + * When running in a multi threaded environment, obtain the "write_lock" + * semaphore. This ensures that writing to the device is thread-safe. + */ + + ALT_SEM_PEND (sp->write_lock, 0); + 101ee40: e0bffc17 ldw r2,-16(fp) + 101ee44: 10800917 ldw r2,36(r2) + 101ee48: e0bff515 stw r2,-44(fp) + 101ee4c: e03ff60d sth zero,-40(fp) + 101ee50: e17ff60b ldhu r5,-40(fp) + 101ee54: e1bffb04 addi r6,fp,-20 + 101ee58: e13ff517 ldw r4,-44(fp) + 101ee5c: 101ae180 call 101ae18 + * Loop transferring data from the input buffer to the transmit circular + * buffer. The loop is terminated once all the data has been transferred, + * or, (if in non-blocking mode) the buffer becomes full. + */ + + while (count) + 101ee60: 00005506 br 101efb8 + { + /* Determine the next slot in the buffer to access */ + + next = (sp->tx_end + 1) & ALT_AVALON_UART_BUF_MSK; + 101ee64: e0bffc17 ldw r2,-16(fp) + 101ee68: 10800517 ldw r2,20(r2) + 101ee6c: 10800044 addi r2,r2,1 + 101ee70: 10800fcc andi r2,r2,63 + 101ee74: e0bff815 stw r2,-32(fp) + + /* block waiting for space if necessary */ + + if (next == sp->tx_start) + 101ee78: e0bffc17 ldw r2,-16(fp) + 101ee7c: 10c00417 ldw r3,16(r2) + 101ee80: e0bff817 ldw r2,-32(fp) + 101ee84: 18803a1e bne r3,r2,101ef70 + { + if (no_block) + 101ee88: e0bff917 ldw r2,-28(fp) + 101ee8c: 1005003a cmpeq r2,r2,zero + 101ee90: 1000051e bne r2,zero,101eea8 + { + /* Set errno to indicate why this function returned early */ + + ALT_ERRNO = EWOULDBLOCK; + 101ee94: 101f0540 call 101f054 + 101ee98: 1007883a mov r3,r2 + 101ee9c: 008002c4 movi r2,11 + 101eea0: 18800015 stw r2,0(r3) + break; + 101eea4: 00004706 br 101efc4 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 101eea8: 0005303a rdctl r2,status + 101eeac: e0bff415 stw r2,-48(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 101eeb0: e0fff417 ldw r3,-48(fp) + 101eeb4: 00bfff84 movi r2,-2 + 101eeb8: 1884703a and r2,r3,r2 + 101eebc: 1001703a wrctl status,r2 + + return context; + 101eec0: e0bff417 ldw r2,-48(fp) + { + /* Block waiting for space in the circular buffer */ + + /* First, ensure transmit interrupts are enabled to avoid deadlock */ + + context = alt_irq_disable_all (); + 101eec4: e0bffa15 stw r2,-24(fp) + sp->ctrl |= (ALTERA_AVALON_UART_CONTROL_TRDY_MSK | + 101eec8: e0bffc17 ldw r2,-16(fp) + 101eecc: 10800117 ldw r2,4(r2) + 101eed0: 10c11014 ori r3,r2,1088 + 101eed4: e0bffc17 ldw r2,-16(fp) + 101eed8: 10c00115 stw r3,4(r2) + ALTERA_AVALON_UART_CONTROL_DCTS_MSK); + IOWR_ALTERA_AVALON_UART_CONTROL(sp->base, sp->ctrl); + 101eedc: e0bffc17 ldw r2,-16(fp) + 101eee0: 10800017 ldw r2,0(r2) + 101eee4: 11000304 addi r4,r2,12 + 101eee8: e0bffc17 ldw r2,-16(fp) + 101eeec: 10800117 ldw r2,4(r2) + 101eef0: 1007883a mov r3,r2 + 101eef4: 2005883a mov r2,r4 + 101eef8: 10c00035 stwio r3,0(r2) + 101eefc: e0bffa17 ldw r2,-24(fp) + 101ef00: e0bff315 stw r2,-52(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 101ef04: e0bff317 ldw r2,-52(fp) + 101ef08: 1001703a wrctl status,r2 + * flag set in the interrupt service routine. This avoids wasting CPU + * cycles waiting in this thread, when we could be doing something + * more profitable elsewhere. + */ + + ALT_FLAG_PEND (sp->events, + 101ef0c: e0bffc17 ldw r2,-16(fp) + 101ef10: 10800717 ldw r2,28(r2) + 101ef14: e0bff015 stw r2,-64(fp) + 101ef18: 00800084 movi r2,2 + 101ef1c: e0bff10d sth r2,-60(fp) + 101ef20: 00bfe0c4 movi r2,-125 + 101ef24: e0bff185 stb r2,-58(fp) + 101ef28: e03ff20d sth zero,-56(fp) + OS_FLAGS flags, + INT8U wait_type, + INT16U timeout) +{ + INT8U err; + if (OSRunning) + 101ef2c: 008040b4 movhi r2,258 + 101ef30: 10951444 addi r2,r2,21585 + 101ef34: 10800003 ldbu r2,0(r2) + 101ef38: 10803fcc andi r2,r2,255 + 101ef3c: 1005003a cmpeq r2,r2,zero + 101ef40: 1000071e bne r2,zero,101ef60 + { + OSFlagPend (group, flags, wait_type, timeout, &err); + 101ef44: e17ff10b ldhu r5,-60(fp) + 101ef48: e1bff183 ldbu r6,-58(fp) + 101ef4c: e1fff20b ldhu r7,-56(fp) + 101ef50: e0bffb44 addi r2,fp,-19 + 101ef54: d8800015 stw r2,0(sp) + 101ef58: e13ff017 ldw r4,-64(fp) + 101ef5c: 1017edc0 call 1017edc + ALT_UART_WRITE_RDY, + OS_FLAG_WAIT_SET_ANY + OS_FLAG_CONSUME, + 0); + } + while ((next == sp->tx_start)); + 101ef60: e0bffc17 ldw r2,-16(fp) + 101ef64: 10c00417 ldw r3,16(r2) + 101ef68: e0bff817 ldw r2,-32(fp) + 101ef6c: 18bfe726 beq r3,r2,101ef0c + } + } + + count--; + 101ef70: e0bff717 ldw r2,-36(fp) + 101ef74: 10bfffc4 addi r2,r2,-1 + 101ef78: e0bff715 stw r2,-36(fp) + + /* Add the next character to the transmit buffer */ + + sp->tx_buf[sp->tx_end] = *ptr++; + 101ef7c: e0bffc17 ldw r2,-16(fp) + 101ef80: 10c00517 ldw r3,20(r2) + 101ef84: e0bffd17 ldw r2,-12(fp) + 101ef88: 10800003 ldbu r2,0(r2) + 101ef8c: 1009883a mov r4,r2 + 101ef90: e0bffc17 ldw r2,-16(fp) + 101ef94: 1885883a add r2,r3,r2 + 101ef98: 10801a04 addi r2,r2,104 + 101ef9c: 11000005 stb r4,0(r2) + 101efa0: e0bffd17 ldw r2,-12(fp) + 101efa4: 10800044 addi r2,r2,1 + 101efa8: e0bffd15 stw r2,-12(fp) + sp->tx_end = next; + 101efac: e0fffc17 ldw r3,-16(fp) + 101efb0: e0bff817 ldw r2,-32(fp) + 101efb4: 18800515 stw r2,20(r3) + * Loop transferring data from the input buffer to the transmit circular + * buffer. The loop is terminated once all the data has been transferred, + * or, (if in non-blocking mode) the buffer becomes full. + */ + + while (count) + 101efb8: e0bff717 ldw r2,-36(fp) + 101efbc: 1004c03a cmpne r2,r2,zero + 101efc0: 103fa81e bne r2,zero,101ee64 + /* + * Now that access to the circular buffer is complete, release the write + * semaphore so that other threads can access the buffer. + */ + + ALT_SEM_POST (sp->write_lock); + 101efc4: e0bffc17 ldw r2,-16(fp) + 101efc8: 11000917 ldw r4,36(r2) + 101efcc: 101b2100 call 101b210 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 101efd0: 0005303a rdctl r2,status + 101efd4: e0bfef15 stw r2,-68(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 101efd8: e0ffef17 ldw r3,-68(fp) + 101efdc: 00bfff84 movi r2,-2 + 101efe0: 1884703a and r2,r3,r2 + 101efe4: 1001703a wrctl status,r2 + + return context; + 101efe8: e0bfef17 ldw r2,-68(fp) + /* + * Ensure that interrupts are enabled, so that the circular buffer can + * drain. + */ + + context = alt_irq_disable_all (); + 101efec: e0bffa15 stw r2,-24(fp) + sp->ctrl |= ALTERA_AVALON_UART_CONTROL_TRDY_MSK | + 101eff0: e0bffc17 ldw r2,-16(fp) + 101eff4: 10800117 ldw r2,4(r2) + 101eff8: 10c11014 ori r3,r2,1088 + 101effc: e0bffc17 ldw r2,-16(fp) + 101f000: 10c00115 stw r3,4(r2) + ALTERA_AVALON_UART_CONTROL_DCTS_MSK; + IOWR_ALTERA_AVALON_UART_CONTROL(sp->base, sp->ctrl); + 101f004: e0bffc17 ldw r2,-16(fp) + 101f008: 10800017 ldw r2,0(r2) + 101f00c: 11000304 addi r4,r2,12 + 101f010: e0bffc17 ldw r2,-16(fp) + 101f014: 10800117 ldw r2,4(r2) + 101f018: 1007883a mov r3,r2 + 101f01c: 2005883a mov r2,r4 + 101f020: 10c00035 stwio r3,0(r2) + 101f024: e0bffa17 ldw r2,-24(fp) + 101f028: e0bfee15 stw r2,-72(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 101f02c: e0bfee17 ldw r2,-72(fp) + 101f030: 1001703a wrctl status,r2 + alt_irq_enable_all (context); + + /* return the number of bytes written */ + + return (len - count); + 101f034: e0fffe17 ldw r3,-8(fp) + 101f038: e0bff717 ldw r2,-36(fp) + 101f03c: 1885c83a sub r2,r3,r2 +} + 101f040: e037883a mov sp,fp + 101f044: dfc00117 ldw ra,4(sp) + 101f048: df000017 ldw fp,0(sp) + 101f04c: dec00204 addi sp,sp,8 + 101f050: f800283a ret + +0101f054 : +#undef errno + +extern int errno; + +static ALT_INLINE int* alt_get_errno(void) +{ + 101f054: defffd04 addi sp,sp,-12 + 101f058: dfc00215 stw ra,8(sp) + 101f05c: df000115 stw fp,4(sp) + 101f060: df000104 addi fp,sp,4 + return ((alt_errno) ? alt_errno() : &errno); + 101f064: 008040b4 movhi r2,258 + 101f068: 108dd104 addi r2,r2,14148 + 101f06c: 10800017 ldw r2,0(r2) + 101f070: 1005003a cmpeq r2,r2,zero + 101f074: 1000061e bne r2,zero,101f090 + 101f078: 008040b4 movhi r2,258 + 101f07c: 108dd104 addi r2,r2,14148 + 101f080: 10800017 ldw r2,0(r2) + 101f084: 103ee83a callr r2 + 101f088: e0bfff15 stw r2,-4(fp) + 101f08c: 00000306 br 101f09c + 101f090: 008040b4 movhi r2,258 + 101f094: 10950804 addi r2,r2,21536 + 101f098: e0bfff15 stw r2,-4(fp) + 101f09c: e0bfff17 ldw r2,-4(fp) +} + 101f0a0: e037883a mov sp,fp + 101f0a4: dfc00117 ldw ra,4(sp) + 101f0a8: df000017 ldw fp,0(sp) + 101f0ac: dec00204 addi sp,sp,8 + 101f0b0: f800283a ret + +0101f0b4 : +#include "altera_up_avalon_rs232.h" +#include "altera_up_avalon_rs232_regs.h" + + +void alt_up_rs232_enable_read_interrupt(alt_up_rs232_dev *rs232) +{ + 101f0b4: defffd04 addi sp,sp,-12 + 101f0b8: df000215 stw fp,8(sp) + 101f0bc: df000204 addi fp,sp,8 + 101f0c0: e13fff15 stw r4,-4(fp) + alt_u32 ctrl_reg; + ctrl_reg = IORD_ALT_UP_RS232_CONTROL(rs232->base); + 101f0c4: e0bfff17 ldw r2,-4(fp) + 101f0c8: 10800a17 ldw r2,40(r2) + 101f0cc: 10800104 addi r2,r2,4 + 101f0d0: 10800037 ldwio r2,0(r2) + 101f0d4: e0bffe15 stw r2,-8(fp) + // set RE to 1 while maintaining other bits the same + ctrl_reg |= ALT_UP_RS232_CONTROL_RE_MSK; + 101f0d8: e0bffe17 ldw r2,-8(fp) + 101f0dc: 10800054 ori r2,r2,1 + 101f0e0: e0bffe15 stw r2,-8(fp) + IOWR_ALT_UP_RS232_CONTROL(rs232->base, ctrl_reg); + 101f0e4: e0bfff17 ldw r2,-4(fp) + 101f0e8: 10800a17 ldw r2,40(r2) + 101f0ec: 10800104 addi r2,r2,4 + 101f0f0: e0fffe17 ldw r3,-8(fp) + 101f0f4: 10c00035 stwio r3,0(r2) +} + 101f0f8: e037883a mov sp,fp + 101f0fc: df000017 ldw fp,0(sp) + 101f100: dec00104 addi sp,sp,4 + 101f104: f800283a ret + +0101f108 : + +void alt_up_rs232_disable_read_interrupt(alt_up_rs232_dev *rs232) +{ + 101f108: defffd04 addi sp,sp,-12 + 101f10c: df000215 stw fp,8(sp) + 101f110: df000204 addi fp,sp,8 + 101f114: e13fff15 stw r4,-4(fp) + alt_u32 ctrl_reg; + ctrl_reg = IORD_ALT_UP_RS232_CONTROL(rs232->base); + 101f118: e0bfff17 ldw r2,-4(fp) + 101f11c: 10800a17 ldw r2,40(r2) + 101f120: 10800104 addi r2,r2,4 + 101f124: 10800037 ldwio r2,0(r2) + 101f128: e0bffe15 stw r2,-8(fp) + // set RE to 0 while maintaining other bits the same + ctrl_reg &= ~ALT_UP_RS232_CONTROL_RE_MSK; + 101f12c: e0fffe17 ldw r3,-8(fp) + 101f130: 00bfff84 movi r2,-2 + 101f134: 1884703a and r2,r3,r2 + 101f138: e0bffe15 stw r2,-8(fp) + IOWR_ALT_UP_RS232_CONTROL(rs232->base, ctrl_reg); + 101f13c: e0bfff17 ldw r2,-4(fp) + 101f140: 10800a17 ldw r2,40(r2) + 101f144: 10800104 addi r2,r2,4 + 101f148: e0fffe17 ldw r3,-8(fp) + 101f14c: 10c00035 stwio r3,0(r2) +} + 101f150: e037883a mov sp,fp + 101f154: df000017 ldw fp,0(sp) + 101f158: dec00104 addi sp,sp,4 + 101f15c: f800283a ret + +0101f160 : + +unsigned alt_up_rs232_get_used_space_in_read_FIFO(alt_up_rs232_dev *rs232) +{ + 101f160: defffd04 addi sp,sp,-12 + 101f164: df000215 stw fp,8(sp) + 101f168: df000204 addi fp,sp,8 + 101f16c: e13fff15 stw r4,-4(fp) + alt_u16 ravail = 0; + 101f170: e03ffe0d sth zero,-8(fp) + // we can only read the 16 bits for RAVAIL --- a read of DATA will discard the data +// ravail = IORD_16DIRECT(IOADDR_ALT_UP_RS232_DATA(rs232->base), 2); + ravail = IORD_ALT_UP_RS232_RAVAIL(rs232->base); + 101f174: e0bfff17 ldw r2,-4(fp) + 101f178: 10800a17 ldw r2,40(r2) + 101f17c: 10800084 addi r2,r2,2 + 101f180: 1080002b ldhuio r2,0(r2) + 101f184: e0bffe0d sth r2,-8(fp) +// return ravail; + return (ravail & ALT_UP_RS232_RAVAIL_MSK) >> ALT_UP_RS232_RAVAIL_OFST; + 101f188: e0bffe0b ldhu r2,-8(fp) +} + 101f18c: e037883a mov sp,fp + 101f190: df000017 ldw fp,0(sp) + 101f194: dec00104 addi sp,sp,4 + 101f198: f800283a ret + +0101f19c : + +unsigned alt_up_rs232_get_available_space_in_write_FIFO(alt_up_rs232_dev *rs232) +{ + 101f19c: defffd04 addi sp,sp,-12 + 101f1a0: df000215 stw fp,8(sp) + 101f1a4: df000204 addi fp,sp,8 + 101f1a8: e13fff15 stw r4,-4(fp) + alt_u32 ctrl_reg; + ctrl_reg = IORD_ALT_UP_RS232_CONTROL(rs232->base); + 101f1ac: e0bfff17 ldw r2,-4(fp) + 101f1b0: 10800a17 ldw r2,40(r2) + 101f1b4: 10800104 addi r2,r2,4 + 101f1b8: 10800037 ldwio r2,0(r2) + 101f1bc: e0bffe15 stw r2,-8(fp) + return (ctrl_reg & ALT_UP_RS232_CONTROL_WSPACE_MSK) >> ALT_UP_RS232_CONTROL_WSPACE_OFST; + 101f1c0: e0bffe17 ldw r2,-8(fp) + 101f1c4: 10bfffec andhi r2,r2,65535 + 101f1c8: 1004d43a srli r2,r2,16 +} + 101f1cc: e037883a mov sp,fp + 101f1d0: df000017 ldw fp,0(sp) + 101f1d4: dec00104 addi sp,sp,4 + 101f1d8: f800283a ret + +0101f1dc : + +int alt_up_rs232_check_parity(alt_u32 data_reg) +{ + 101f1dc: defffc04 addi sp,sp,-16 + 101f1e0: df000315 stw fp,12(sp) + 101f1e4: df000304 addi fp,sp,12 + 101f1e8: e13ffe15 stw r4,-8(fp) + unsigned parity_error = (data_reg & ALT_UP_RS232_DATA_PE_MSK) >> ALT_UP_RS232_DATA_PE_OFST; + 101f1ec: e0bffe17 ldw r2,-8(fp) + 101f1f0: 1080800c andi r2,r2,512 + 101f1f4: 1004d27a srli r2,r2,9 + 101f1f8: e0bffd15 stw r2,-12(fp) + return (parity_error ? -1 : 0); + 101f1fc: e0bffd17 ldw r2,-12(fp) + 101f200: 1005003a cmpeq r2,r2,zero + 101f204: 1000031e bne r2,zero,101f214 + 101f208: 00bfffc4 movi r2,-1 + 101f20c: e0bfff15 stw r2,-4(fp) + 101f210: 00000106 br 101f218 + 101f214: e03fff15 stw zero,-4(fp) + 101f218: e0bfff17 ldw r2,-4(fp) +} + 101f21c: e037883a mov sp,fp + 101f220: df000017 ldw fp,0(sp) + 101f224: dec00104 addi sp,sp,4 + 101f228: f800283a ret + +0101f22c : + +int alt_up_rs232_write_data(alt_up_rs232_dev *rs232, alt_u8 data) +{ + 101f22c: defffc04 addi sp,sp,-16 + 101f230: df000315 stw fp,12(sp) + 101f234: df000304 addi fp,sp,12 + 101f238: e13ffe15 stw r4,-8(fp) + 101f23c: e17fff05 stb r5,-4(fp) + alt_u32 data_reg; + data_reg = IORD_ALT_UP_RS232_DATA(rs232->base); + 101f240: e0bffe17 ldw r2,-8(fp) + 101f244: 10800a17 ldw r2,40(r2) + 101f248: 10800037 ldwio r2,0(r2) + 101f24c: e0bffd15 stw r2,-12(fp) + + // we can write directly without thinking about other bit fields for this + // case ONLY, because only DATA field of the data register is writable + IOWR_ALT_UP_RS232_DATA(rs232->base, (data>>ALT_UP_RS232_DATA_DATA_OFST) & ALT_UP_RS232_DATA_DATA_MSK); + 101f250: e0bffe17 ldw r2,-8(fp) + 101f254: 10800a17 ldw r2,40(r2) + 101f258: e0ffff03 ldbu r3,-4(fp) + 101f25c: 10c00035 stwio r3,0(r2) + return 0; + 101f260: 0005883a mov r2,zero +} + 101f264: e037883a mov sp,fp + 101f268: df000017 ldw fp,0(sp) + 101f26c: dec00104 addi sp,sp,4 + 101f270: f800283a ret + +0101f274 : + +int alt_up_rs232_read_data(alt_up_rs232_dev *rs232, alt_u8 *data, alt_u8 *parity_error) +{ + 101f274: defffa04 addi sp,sp,-24 + 101f278: dfc00515 stw ra,20(sp) + 101f27c: df000415 stw fp,16(sp) + 101f280: df000404 addi fp,sp,16 + 101f284: e13ffd15 stw r4,-12(fp) + 101f288: e17ffe15 stw r5,-8(fp) + 101f28c: e1bfff15 stw r6,-4(fp) + alt_u32 data_reg; + data_reg = IORD_ALT_UP_RS232_DATA(rs232->base); + 101f290: e0bffd17 ldw r2,-12(fp) + 101f294: 10800a17 ldw r2,40(r2) + 101f298: 10800037 ldwio r2,0(r2) + 101f29c: e0bffc15 stw r2,-16(fp) + *data = (data_reg & ALT_UP_RS232_DATA_DATA_MSK) >> ALT_UP_RS232_DATA_DATA_OFST; + 101f2a0: e0bffc17 ldw r2,-16(fp) + 101f2a4: 1007883a mov r3,r2 + 101f2a8: e0bffe17 ldw r2,-8(fp) + 101f2ac: 10c00005 stb r3,0(r2) + *parity_error = alt_up_rs232_check_parity(data_reg); + 101f2b0: e13ffc17 ldw r4,-16(fp) + 101f2b4: 101f1dc0 call 101f1dc + 101f2b8: 1007883a mov r3,r2 + 101f2bc: e0bfff17 ldw r2,-4(fp) + 101f2c0: 10c00005 stb r3,0(r2) + return (((data_reg & ALT_UP_RS232_DATA_RVALID_MSK) >> ALT_UP_RS232_DATA_RVALID_OFST) - 1); + 101f2c4: e0bffc17 ldw r2,-16(fp) + 101f2c8: 10a0000c andi r2,r2,32768 + 101f2cc: 1004d3fa srli r2,r2,15 + 101f2d0: 10bfffc4 addi r2,r2,-1 +} + 101f2d4: e037883a mov sp,fp + 101f2d8: dfc00117 ldw ra,4(sp) + 101f2dc: df000017 ldw fp,0(sp) + 101f2e0: dec00204 addi sp,sp,8 + 101f2e4: f800283a ret + +0101f2e8 : + +int alt_up_rs232_read_fd (alt_fd* fd, char* ptr, int len) +{ + 101f2e8: defff804 addi sp,sp,-32 + 101f2ec: dfc00715 stw ra,28(sp) + 101f2f0: df000615 stw fp,24(sp) + 101f2f4: df000604 addi fp,sp,24 + 101f2f8: e13ffd15 stw r4,-12(fp) + 101f2fc: e17ffe15 stw r5,-8(fp) + 101f300: e1bfff15 stw r6,-4(fp) + alt_up_rs232_dev *rs232 = (alt_up_rs232_dev*)fd->dev; + 101f304: e0bffd17 ldw r2,-12(fp) + 101f308: 10800017 ldw r2,0(r2) + 101f30c: e0bffb15 stw r2,-20(fp) + int count = 0; + 101f310: e03ffa15 stw zero,-24(fp) + alt_u8 parity_error; + while(len--) + 101f314: 00000c06 br 101f348 + { + if (alt_up_rs232_read_data(rs232, ptr++, &parity_error)==0) + 101f318: e17ffe17 ldw r5,-8(fp) + 101f31c: e0bffe17 ldw r2,-8(fp) + 101f320: 10800044 addi r2,r2,1 + 101f324: e0bffe15 stw r2,-8(fp) + 101f328: e1bffc04 addi r6,fp,-16 + 101f32c: e13ffb17 ldw r4,-20(fp) + 101f330: 101f2740 call 101f274 + 101f334: 1004c03a cmpne r2,r2,zero + 101f338: 1000091e bne r2,zero,101f360 + count++; + 101f33c: e0bffa17 ldw r2,-24(fp) + 101f340: 10800044 addi r2,r2,1 + 101f344: e0bffa15 stw r2,-24(fp) +int alt_up_rs232_read_fd (alt_fd* fd, char* ptr, int len) +{ + alt_up_rs232_dev *rs232 = (alt_up_rs232_dev*)fd->dev; + int count = 0; + alt_u8 parity_error; + while(len--) + 101f348: e0bfff17 ldw r2,-4(fp) + 101f34c: 10bfffc4 addi r2,r2,-1 + 101f350: e0bfff15 stw r2,-4(fp) + 101f354: e0bfff17 ldw r2,-4(fp) + 101f358: 10bfffd8 cmpnei r2,r2,-1 + 101f35c: 103fee1e bne r2,zero,101f318 + if (alt_up_rs232_read_data(rs232, ptr++, &parity_error)==0) + count++; + else + break; + } + return count; + 101f360: e0bffa17 ldw r2,-24(fp) +} + 101f364: e037883a mov sp,fp + 101f368: dfc00117 ldw ra,4(sp) + 101f36c: df000017 ldw fp,0(sp) + 101f370: dec00204 addi sp,sp,8 + 101f374: f800283a ret + +0101f378 : + +int alt_up_rs232_write_fd (alt_fd* fd, const char* ptr, int len) +{ + 101f378: defff904 addi sp,sp,-28 + 101f37c: dfc00615 stw ra,24(sp) + 101f380: df000515 stw fp,20(sp) + 101f384: df000504 addi fp,sp,20 + 101f388: e13ffd15 stw r4,-12(fp) + 101f38c: e17ffe15 stw r5,-8(fp) + 101f390: e1bfff15 stw r6,-4(fp) + alt_up_rs232_dev *rs232 = (alt_up_rs232_dev*)fd->dev; + 101f394: e0bffd17 ldw r2,-12(fp) + 101f398: 10800017 ldw r2,0(r2) + 101f39c: e0bffc15 stw r2,-16(fp) + int count = 0; + 101f3a0: e03ffb15 stw zero,-20(fp) + while(len--) + 101f3a4: 00000d06 br 101f3dc + { + if (alt_up_rs232_write_data(rs232, *ptr)==0) + 101f3a8: e0bffe17 ldw r2,-8(fp) + 101f3ac: 10800003 ldbu r2,0(r2) + 101f3b0: 11403fcc andi r5,r2,255 + 101f3b4: e13ffc17 ldw r4,-16(fp) + 101f3b8: 101f22c0 call 101f22c + 101f3bc: 1004c03a cmpne r2,r2,zero + 101f3c0: 10000c1e bne r2,zero,101f3f4 + { + count++; + 101f3c4: e0bffb17 ldw r2,-20(fp) + 101f3c8: 10800044 addi r2,r2,1 + 101f3cc: e0bffb15 stw r2,-20(fp) + ptr++; + 101f3d0: e0bffe17 ldw r2,-8(fp) + 101f3d4: 10800044 addi r2,r2,1 + 101f3d8: e0bffe15 stw r2,-8(fp) + +int alt_up_rs232_write_fd (alt_fd* fd, const char* ptr, int len) +{ + alt_up_rs232_dev *rs232 = (alt_up_rs232_dev*)fd->dev; + int count = 0; + while(len--) + 101f3dc: e0bfff17 ldw r2,-4(fp) + 101f3e0: 10bfffc4 addi r2,r2,-1 + 101f3e4: e0bfff15 stw r2,-4(fp) + 101f3e8: e0bfff17 ldw r2,-4(fp) + 101f3ec: 10bfffd8 cmpnei r2,r2,-1 + 101f3f0: 103fed1e bne r2,zero,101f3a8 + ptr++; + } + else + break; + } + return count; + 101f3f4: e0bffb17 ldw r2,-20(fp) +} + 101f3f8: e037883a mov sp,fp + 101f3fc: dfc00117 ldw ra,4(sp) + 101f400: df000017 ldw fp,0(sp) + 101f404: dec00204 addi sp,sp,8 + 101f408: f800283a ret + +0101f40c : + +alt_up_rs232_dev* alt_up_rs232_open_dev(const char* name) +{ + 101f40c: defffc04 addi sp,sp,-16 + 101f410: dfc00315 stw ra,12(sp) + 101f414: df000215 stw fp,8(sp) + 101f418: df000204 addi fp,sp,8 + 101f41c: e13fff15 stw r4,-4(fp) + // find the device from the device list + // (see altera_hal/HAL/inc/priv/alt_file.h + // and altera_hal/HAL/src/alt_find_dev.c + // for details) + alt_up_rs232_dev *dev = (alt_up_rs232_dev*)alt_find_dev(name, &alt_dev_list); + 101f420: e13fff17 ldw r4,-4(fp) + 101f424: 014040b4 movhi r5,258 + 101f428: 294dce04 addi r5,r5,14136 + 101f42c: 101f7c00 call 101f7c0 + 101f430: e0bffe15 stw r2,-8(fp) + + return dev; + 101f434: e0bffe17 ldw r2,-8(fp) +} + 101f438: e037883a mov sp,fp + 101f43c: dfc00117 ldw ra,4(sp) + 101f440: df000017 ldw fp,0(sp) + 101f444: dec00204 addi sp,sp,8 + 101f448: f800283a ret + +0101f44c : + */ + +int alt_alarm_start (alt_alarm* alarm, alt_u32 nticks, + alt_u32 (*callback) (void* context), + void* context) +{ + 101f44c: defff404 addi sp,sp,-48 + 101f450: df000b15 stw fp,44(sp) + 101f454: df000b04 addi fp,sp,44 + 101f458: e13ffb15 stw r4,-20(fp) + 101f45c: e17ffc15 stw r5,-16(fp) + 101f460: e1bffd15 stw r6,-12(fp) + 101f464: e1fffe15 stw r7,-8(fp) + alt_irq_context irq_context; + alt_u32 current_nticks = 0; + 101f468: e03ff915 stw zero,-28(fp) + * Obtain the system clock rate in ticks/s. + */ + +static ALT_INLINE alt_u32 ALT_ALWAYS_INLINE alt_ticks_per_second (void) +{ + return _alt_tick_rate; + 101f46c: 008040b4 movhi r2,258 + 101f470: 10952904 addi r2,r2,21668 + 101f474: 10800017 ldw r2,0(r2) + + if (alt_ticks_per_second ()) + 101f478: 1005003a cmpeq r2,r2,zero + 101f47c: 1000411e bne r2,zero,101f584 + { + if (alarm) + 101f480: e0bffb17 ldw r2,-20(fp) + 101f484: 1005003a cmpeq r2,r2,zero + 101f488: 10003b1e bne r2,zero,101f578 + { + alarm->callback = callback; + 101f48c: e0fffb17 ldw r3,-20(fp) + 101f490: e0bffd17 ldw r2,-12(fp) + 101f494: 18800315 stw r2,12(r3) + alarm->context = context; + 101f498: e0fffb17 ldw r3,-20(fp) + 101f49c: e0bffe17 ldw r2,-8(fp) + 101f4a0: 18800515 stw r2,20(r3) +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 101f4a4: 0005303a rdctl r2,status + 101f4a8: e0bff815 stw r2,-32(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 101f4ac: e0fff817 ldw r3,-32(fp) + 101f4b0: 00bfff84 movi r2,-2 + 101f4b4: 1884703a and r2,r3,r2 + 101f4b8: 1001703a wrctl status,r2 + + return context; + 101f4bc: e0bff817 ldw r2,-32(fp) + + irq_context = alt_irq_disable_all (); + 101f4c0: e0bffa15 stw r2,-24(fp) + * alt_nticks() returns the elapsed number of system clock ticks since reset. + */ + +static ALT_INLINE alt_u32 ALT_ALWAYS_INLINE alt_nticks (void) +{ + return _alt_nticks; + 101f4c4: 008040b4 movhi r2,258 + 101f4c8: 10952a04 addi r2,r2,21672 + 101f4cc: 10800017 ldw r2,0(r2) + + current_nticks = alt_nticks(); + 101f4d0: e0bff915 stw r2,-28(fp) + + alarm->time = nticks + current_nticks + 1; + 101f4d4: e0fffc17 ldw r3,-16(fp) + 101f4d8: e0bff917 ldw r2,-28(fp) + 101f4dc: 1885883a add r2,r3,r2 + 101f4e0: 10c00044 addi r3,r2,1 + 101f4e4: e0bffb17 ldw r2,-20(fp) + 101f4e8: 10c00215 stw r3,8(r2) + /* + * If the desired alarm time causes a roll-over, set the rollover + * flag. This will prevent the subsequent tick event from causing + * an alarm too early. + */ + if(alarm->time < current_nticks) + 101f4ec: e0bffb17 ldw r2,-20(fp) + 101f4f0: 10c00217 ldw r3,8(r2) + 101f4f4: e0bff917 ldw r2,-28(fp) + 101f4f8: 1880042e bgeu r3,r2,101f50c + { + alarm->rollover = 1; + 101f4fc: e0fffb17 ldw r3,-20(fp) + 101f500: 00800044 movi r2,1 + 101f504: 18800405 stb r2,16(r3) + 101f508: 00000206 br 101f514 + } + else + { + alarm->rollover = 0; + 101f50c: e0bffb17 ldw r2,-20(fp) + 101f510: 10000405 stb zero,16(r2) + } + + alt_llist_insert (&alt_alarm_list, &alarm->llist); + 101f514: e0fffb17 ldw r3,-20(fp) + 101f518: 008040b4 movhi r2,258 + 101f51c: 108df304 addi r2,r2,14284 + 101f520: e0bff615 stw r2,-40(fp) + 101f524: e0fff715 stw r3,-36(fp) + */ + +static ALT_INLINE void ALT_ALWAYS_INLINE alt_llist_insert(alt_llist* list, + alt_llist* entry) +{ + entry->previous = list; + 101f528: e0fff717 ldw r3,-36(fp) + 101f52c: e0bff617 ldw r2,-40(fp) + 101f530: 18800115 stw r2,4(r3) + entry->next = list->next; + 101f534: e0bff617 ldw r2,-40(fp) + 101f538: 10c00017 ldw r3,0(r2) + 101f53c: e0bff717 ldw r2,-36(fp) + 101f540: 10c00015 stw r3,0(r2) + + list->next->previous = entry; + 101f544: e0bff617 ldw r2,-40(fp) + 101f548: 10c00017 ldw r3,0(r2) + 101f54c: e0bff717 ldw r2,-36(fp) + 101f550: 18800115 stw r2,4(r3) + list->next = entry; + 101f554: e0fff617 ldw r3,-40(fp) + 101f558: e0bff717 ldw r2,-36(fp) + 101f55c: 18800015 stw r2,0(r3) + 101f560: e0bffa17 ldw r2,-24(fp) + 101f564: e0bff515 stw r2,-44(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 101f568: e0bff517 ldw r2,-44(fp) + 101f56c: 1001703a wrctl status,r2 + alt_irq_enable_all (irq_context); + + return 0; + 101f570: e03fff15 stw zero,-4(fp) + 101f574: 00000506 br 101f58c + } + else + { + return -EINVAL; + 101f578: 00bffa84 movi r2,-22 + 101f57c: e0bfff15 stw r2,-4(fp) + 101f580: 00000206 br 101f58c + } + } + else + { + return -ENOTSUP; + 101f584: 00bfde84 movi r2,-134 + 101f588: e0bfff15 stw r2,-4(fp) + 101f58c: e0bfff17 ldw r2,-4(fp) + } +} + 101f590: e037883a mov sp,fp + 101f594: df000017 ldw fp,0(sp) + 101f598: dec00104 addi sp,sp,4 + 101f59c: f800283a ret + +0101f5a0 : +/* + * alt_dcache_flush_all() is called to flush the entire data cache. + */ + +void alt_dcache_flush_all (void) +{ + 101f5a0: defffe04 addi sp,sp,-8 + 101f5a4: df000115 stw fp,4(sp) + 101f5a8: df000104 addi fp,sp,4 +#if NIOS2_DCACHE_SIZE > 0 + char* i; + + for (i = (char*) 0; i < (char*) NIOS2_DCACHE_SIZE; i+= NIOS2_DCACHE_LINE_SIZE) + 101f5ac: e03fff15 stw zero,-4(fp) + 101f5b0: 00000506 br 101f5c8 + { + __asm__ volatile ("flushd (%0)" :: "r" (i)); + 101f5b4: e0bfff17 ldw r2,-4(fp) + 101f5b8: 1000003b flushd 0(r2) +void alt_dcache_flush_all (void) +{ +#if NIOS2_DCACHE_SIZE > 0 + char* i; + + for (i = (char*) 0; i < (char*) NIOS2_DCACHE_SIZE; i+= NIOS2_DCACHE_LINE_SIZE) + 101f5bc: e0bfff17 ldw r2,-4(fp) + 101f5c0: 10800804 addi r2,r2,32 + 101f5c4: e0bfff15 stw r2,-4(fp) + 101f5c8: e0bfff17 ldw r2,-4(fp) + 101f5cc: 10840030 cmpltui r2,r2,4096 + 101f5d0: 103ff81e bne r2,zero,101f5b4 + { + __asm__ volatile ("flushd (%0)" :: "r" (i)); + } +#endif /* NIOS2_DCACHE_SIZE > 0 */ +} + 101f5d4: e037883a mov sp,fp + 101f5d8: df000017 ldw fp,0(sp) + 101f5dc: dec00104 addi sp,sp,4 + 101f5e0: f800283a ret + +0101f5e4 : +/* + * + */ + +int alt_dev_llist_insert (alt_dev_llist* dev, alt_llist* list) +{ + 101f5e4: defff904 addi sp,sp,-28 + 101f5e8: dfc00615 stw ra,24(sp) + 101f5ec: df000515 stw fp,20(sp) + 101f5f0: df000504 addi fp,sp,20 + 101f5f4: e13ffd15 stw r4,-12(fp) + 101f5f8: e17ffe15 stw r5,-8(fp) + /* + * check that the device exists, and that it has a valid name. + */ + + if (!dev || !dev->name) + 101f5fc: e0bffd17 ldw r2,-12(fp) + 101f600: 1005003a cmpeq r2,r2,zero + 101f604: 1000041e bne r2,zero,101f618 + 101f608: e0bffd17 ldw r2,-12(fp) + 101f60c: 10800217 ldw r2,8(r2) + 101f610: 1004c03a cmpne r2,r2,zero + 101f614: 1000071e bne r2,zero,101f634 + { + ALT_ERRNO = EINVAL; + 101f618: 101f6980 call 101f698 + 101f61c: 1007883a mov r3,r2 + 101f620: 00800584 movi r2,22 + 101f624: 18800015 stw r2,0(r3) + return -EINVAL; + 101f628: 00bffa84 movi r2,-22 + 101f62c: e0bfff15 stw r2,-4(fp) + 101f630: 00001306 br 101f680 + + /* + * register the device. + */ + + alt_llist_insert(list, &dev->llist); + 101f634: e0fffd17 ldw r3,-12(fp) + 101f638: e0bffe17 ldw r2,-8(fp) + 101f63c: e0bffb15 stw r2,-20(fp) + 101f640: e0fffc15 stw r3,-16(fp) + */ + +static ALT_INLINE void ALT_ALWAYS_INLINE alt_llist_insert(alt_llist* list, + alt_llist* entry) +{ + entry->previous = list; + 101f644: e0fffc17 ldw r3,-16(fp) + 101f648: e0bffb17 ldw r2,-20(fp) + 101f64c: 18800115 stw r2,4(r3) + entry->next = list->next; + 101f650: e0bffb17 ldw r2,-20(fp) + 101f654: 10c00017 ldw r3,0(r2) + 101f658: e0bffc17 ldw r2,-16(fp) + 101f65c: 10c00015 stw r3,0(r2) + + list->next->previous = entry; + 101f660: e0bffb17 ldw r2,-20(fp) + 101f664: 10c00017 ldw r3,0(r2) + 101f668: e0bffc17 ldw r2,-16(fp) + 101f66c: 18800115 stw r2,4(r3) + list->next = entry; + 101f670: e0fffb17 ldw r3,-20(fp) + 101f674: e0bffc17 ldw r2,-16(fp) + 101f678: 18800015 stw r2,0(r3) + + return 0; + 101f67c: e03fff15 stw zero,-4(fp) + 101f680: e0bfff17 ldw r2,-4(fp) +} + 101f684: e037883a mov sp,fp + 101f688: dfc00117 ldw ra,4(sp) + 101f68c: df000017 ldw fp,0(sp) + 101f690: dec00204 addi sp,sp,8 + 101f694: f800283a ret + +0101f698 : +#undef errno + +extern int errno; + +static ALT_INLINE int* alt_get_errno(void) +{ + 101f698: defffd04 addi sp,sp,-12 + 101f69c: dfc00215 stw ra,8(sp) + 101f6a0: df000115 stw fp,4(sp) + 101f6a4: df000104 addi fp,sp,4 + return ((alt_errno) ? alt_errno() : &errno); + 101f6a8: 008040b4 movhi r2,258 + 101f6ac: 108dd104 addi r2,r2,14148 + 101f6b0: 10800017 ldw r2,0(r2) + 101f6b4: 1005003a cmpeq r2,r2,zero + 101f6b8: 1000061e bne r2,zero,101f6d4 + 101f6bc: 008040b4 movhi r2,258 + 101f6c0: 108dd104 addi r2,r2,14148 + 101f6c4: 10800017 ldw r2,0(r2) + 101f6c8: 103ee83a callr r2 + 101f6cc: e0bfff15 stw r2,-4(fp) + 101f6d0: 00000306 br 101f6e0 + 101f6d4: 008040b4 movhi r2,258 + 101f6d8: 10950804 addi r2,r2,21536 + 101f6dc: e0bfff15 stw r2,-4(fp) + 101f6e0: e0bfff17 ldw r2,-4(fp) +} + 101f6e4: e037883a mov sp,fp + 101f6e8: dfc00117 ldw ra,4(sp) + 101f6ec: df000017 ldw fp,0(sp) + 101f6f0: dec00204 addi sp,sp,8 + 101f6f4: f800283a ret + +0101f6f8 <_do_ctors>: +/* + * Run the C++ static constructors. + */ + +void _do_ctors(void) +{ + 101f6f8: defffd04 addi sp,sp,-12 + 101f6fc: dfc00215 stw ra,8(sp) + 101f700: df000115 stw fp,4(sp) + 101f704: df000104 addi fp,sp,4 + constructor* ctor; + + for (ctor = &__CTOR_END__[-1]; ctor >= __CTOR_LIST__; ctor--) + 101f708: 00bfff04 movi r2,-4 + 101f70c: 00c040b4 movhi r3,258 + 101f710: 18c38004 addi r3,r3,3584 + 101f714: 1885883a add r2,r3,r2 + 101f718: e0bfff15 stw r2,-4(fp) + 101f71c: 00000606 br 101f738 <_do_ctors+0x40> + (*ctor) (); + 101f720: e0bfff17 ldw r2,-4(fp) + 101f724: 10800017 ldw r2,0(r2) + 101f728: 103ee83a callr r2 + +void _do_ctors(void) +{ + constructor* ctor; + + for (ctor = &__CTOR_END__[-1]; ctor >= __CTOR_LIST__; ctor--) + 101f72c: e0bfff17 ldw r2,-4(fp) + 101f730: 10bfff04 addi r2,r2,-4 + 101f734: e0bfff15 stw r2,-4(fp) + 101f738: e0ffff17 ldw r3,-4(fp) + 101f73c: 008040b4 movhi r2,258 + 101f740: 10837e04 addi r2,r2,3576 + 101f744: 18bff62e bgeu r3,r2,101f720 <_do_ctors+0x28> + (*ctor) (); +} + 101f748: e037883a mov sp,fp + 101f74c: dfc00117 ldw ra,4(sp) + 101f750: df000017 ldw fp,0(sp) + 101f754: dec00204 addi sp,sp,8 + 101f758: f800283a ret + +0101f75c <_do_dtors>: +/* + * Run the C++ static destructors. + */ + +void _do_dtors(void) +{ + 101f75c: defffd04 addi sp,sp,-12 + 101f760: dfc00215 stw ra,8(sp) + 101f764: df000115 stw fp,4(sp) + 101f768: df000104 addi fp,sp,4 + destructor* dtor; + + for (dtor = &__DTOR_END__[-1]; dtor >= __DTOR_LIST__; dtor--) + 101f76c: 00bfff04 movi r2,-4 + 101f770: 00c040b4 movhi r3,258 + 101f774: 18c38004 addi r3,r3,3584 + 101f778: 1885883a add r2,r3,r2 + 101f77c: e0bfff15 stw r2,-4(fp) + 101f780: 00000606 br 101f79c <_do_dtors+0x40> + (*dtor) (); + 101f784: e0bfff17 ldw r2,-4(fp) + 101f788: 10800017 ldw r2,0(r2) + 101f78c: 103ee83a callr r2 + +void _do_dtors(void) +{ + destructor* dtor; + + for (dtor = &__DTOR_END__[-1]; dtor >= __DTOR_LIST__; dtor--) + 101f790: e0bfff17 ldw r2,-4(fp) + 101f794: 10bfff04 addi r2,r2,-4 + 101f798: e0bfff15 stw r2,-4(fp) + 101f79c: e0ffff17 ldw r3,-4(fp) + 101f7a0: 008040b4 movhi r2,258 + 101f7a4: 10838004 addi r2,r2,3584 + 101f7a8: 18bff62e bgeu r3,r2,101f784 <_do_dtors+0x28> + (*dtor) (); +} + 101f7ac: e037883a mov sp,fp + 101f7b0: dfc00117 ldw ra,4(sp) + 101f7b4: df000017 ldw fp,0(sp) + 101f7b8: dec00204 addi sp,sp,8 + 101f7bc: f800283a ret + +0101f7c0 : + * "name" must be an exact match for the devices registered name for a match to + * be found. + */ + +alt_dev* alt_find_dev(const char* name, alt_llist* llist) +{ + 101f7c0: defff904 addi sp,sp,-28 + 101f7c4: dfc00615 stw ra,24(sp) + 101f7c8: df000515 stw fp,20(sp) + 101f7cc: df000504 addi fp,sp,20 + 101f7d0: e13ffd15 stw r4,-12(fp) + 101f7d4: e17ffe15 stw r5,-8(fp) + alt_dev* next = (alt_dev*) llist->next; + 101f7d8: e0bffe17 ldw r2,-8(fp) + 101f7dc: 10800017 ldw r2,0(r2) + 101f7e0: e0bffc15 stw r2,-16(fp) + alt_32 len; + + len = strlen(name) + 1; + 101f7e4: e13ffd17 ldw r4,-12(fp) + 101f7e8: 100b1640 call 100b164 + 101f7ec: 10800044 addi r2,r2,1 + 101f7f0: e0bffb15 stw r2,-20(fp) + /* + * Check each list entry in turn, until a match is found, or we reach the + * end of the list (i.e. next winds up pointing back to the list head). + */ + + while (next != (alt_dev*) llist) + 101f7f4: 00000d06 br 101f82c + /* + * memcmp() is used here rather than strcmp() in order to reduce the size + * of the executable. + */ + + if (!memcmp (next->name, name, len)) + 101f7f8: e0bffc17 ldw r2,-16(fp) + 101f7fc: 11000217 ldw r4,8(r2) + 101f800: e1bffb17 ldw r6,-20(fp) + 101f804: e17ffd17 ldw r5,-12(fp) + 101f808: 100a9c80 call 100a9c8 + 101f80c: 1004c03a cmpne r2,r2,zero + 101f810: 1000031e bne r2,zero,101f820 + { + /* match found */ + + return next; + 101f814: e0bffc17 ldw r2,-16(fp) + 101f818: e0bfff15 stw r2,-4(fp) + 101f81c: 00000706 br 101f83c + } + next = (alt_dev*) next->llist.next; + 101f820: e0bffc17 ldw r2,-16(fp) + 101f824: 10800017 ldw r2,0(r2) + 101f828: e0bffc15 stw r2,-16(fp) + /* + * Check each list entry in turn, until a match is found, or we reach the + * end of the list (i.e. next winds up pointing back to the list head). + */ + + while (next != (alt_dev*) llist) + 101f82c: e0fffe17 ldw r3,-8(fp) + 101f830: e0bffc17 ldw r2,-16(fp) + 101f834: 10fff01e bne r2,r3,101f7f8 + next = (alt_dev*) next->llist.next; + } + + /* No match found */ + + return NULL; + 101f838: e03fff15 stw zero,-4(fp) + 101f83c: e0bfff17 ldw r2,-4(fp) +} + 101f840: e037883a mov sp,fp + 101f844: dfc00117 ldw ra,4(sp) + 101f848: df000017 ldw fp,0(sp) + 101f84c: dec00204 addi sp,sp,8 + 101f850: f800283a ret + +0101f854 : +/* + * alt_icache_flush_all() is called to flush the entire instruction cache. + */ + +void alt_icache_flush_all (void) +{ + 101f854: defffe04 addi sp,sp,-8 + 101f858: dfc00115 stw ra,4(sp) + 101f85c: df000015 stw fp,0(sp) + 101f860: d839883a mov fp,sp +#if NIOS2_ICACHE_SIZE > 0 + alt_icache_flush (0, NIOS2_ICACHE_SIZE); + 101f864: 0009883a mov r4,zero + 101f868: 01480004 movi r5,8192 + 101f86c: 10207080 call 1020708 +#endif +} + 101f870: e037883a mov sp,fp + 101f874: dfc00117 ldw ra,4(sp) + 101f878: df000017 ldw fp,0(sp) + 101f87c: dec00204 addi sp,sp,8 + 101f880: f800283a ret + +0101f884 : + * If the device can not be succesfully opened, then the input file descriptor + * remains unchanged. + */ + +static void alt_open_fd(alt_fd* fd, const char* name, int flags, int mode) +{ + 101f884: defff904 addi sp,sp,-28 + 101f888: dfc00615 stw ra,24(sp) + 101f88c: df000515 stw fp,20(sp) + 101f890: df000504 addi fp,sp,20 + 101f894: e13ffc15 stw r4,-16(fp) + 101f898: e17ffd15 stw r5,-12(fp) + 101f89c: e1bffe15 stw r6,-8(fp) + 101f8a0: e1ffff15 stw r7,-4(fp) + int old; + + old = open (name, flags, mode); + 101f8a4: e13ffd17 ldw r4,-12(fp) + 101f8a8: e17ffe17 ldw r5,-8(fp) + 101f8ac: e1bfff17 ldw r6,-4(fp) + 101f8b0: 101fc5c0 call 101fc5c + 101f8b4: e0bffb15 stw r2,-20(fp) + + if (old >= 0) + 101f8b8: e0bffb17 ldw r2,-20(fp) + 101f8bc: 1004803a cmplt r2,r2,zero + 101f8c0: 10001c1e bne r2,zero,101f934 + { + fd->dev = alt_fd_list[old].dev; + 101f8c4: e0bffb17 ldw r2,-20(fp) + 101f8c8: 00c040b4 movhi r3,258 + 101f8cc: 18c8ff04 addi r3,r3,9212 + 101f8d0: 10800324 muli r2,r2,12 + 101f8d4: 10c5883a add r2,r2,r3 + 101f8d8: 10c00017 ldw r3,0(r2) + 101f8dc: e0bffc17 ldw r2,-16(fp) + 101f8e0: 10c00015 stw r3,0(r2) + fd->priv = alt_fd_list[old].priv; + 101f8e4: e0bffb17 ldw r2,-20(fp) + 101f8e8: 00c040b4 movhi r3,258 + 101f8ec: 18c8ff04 addi r3,r3,9212 + 101f8f0: 10800324 muli r2,r2,12 + 101f8f4: 10c5883a add r2,r2,r3 + 101f8f8: 10800104 addi r2,r2,4 + 101f8fc: 10c00017 ldw r3,0(r2) + 101f900: e0bffc17 ldw r2,-16(fp) + 101f904: 10c00115 stw r3,4(r2) + fd->fd_flags = alt_fd_list[old].fd_flags; + 101f908: e0bffb17 ldw r2,-20(fp) + 101f90c: 00c040b4 movhi r3,258 + 101f910: 18c8ff04 addi r3,r3,9212 + 101f914: 10800324 muli r2,r2,12 + 101f918: 10c5883a add r2,r2,r3 + 101f91c: 10800204 addi r2,r2,8 + 101f920: 10c00017 ldw r3,0(r2) + 101f924: e0bffc17 ldw r2,-16(fp) + 101f928: 10c00215 stw r3,8(r2) + + alt_release_fd (old); + 101f92c: e13ffb17 ldw r4,-20(fp) + 101f930: 1014cfc0 call 1014cfc + } +} + 101f934: e037883a mov sp,fp + 101f938: dfc00117 ldw ra,4(sp) + 101f93c: df000017 ldw fp,0(sp) + 101f940: dec00204 addi sp,sp,8 + 101f944: f800283a ret + +0101f948 : + */ + +void alt_io_redirect(const char* stdout_dev, + const char* stdin_dev, + const char* stderr_dev) +{ + 101f948: defffb04 addi sp,sp,-20 + 101f94c: dfc00415 stw ra,16(sp) + 101f950: df000315 stw fp,12(sp) + 101f954: df000304 addi fp,sp,12 + 101f958: e13ffd15 stw r4,-12(fp) + 101f95c: e17ffe15 stw r5,-8(fp) + 101f960: e1bfff15 stw r6,-4(fp) + /* Redirect the channels */ + + alt_open_fd (&alt_fd_list[STDOUT_FILENO], stdout_dev, O_WRONLY, 0777); + 101f964: 010040b4 movhi r4,258 + 101f968: 21090204 addi r4,r4,9224 + 101f96c: e17ffd17 ldw r5,-12(fp) + 101f970: 01800044 movi r6,1 + 101f974: 01c07fc4 movi r7,511 + 101f978: 101f8840 call 101f884 + alt_open_fd (&alt_fd_list[STDIN_FILENO], stdin_dev, O_RDONLY, 0777); + 101f97c: 010040b4 movhi r4,258 + 101f980: 2108ff04 addi r4,r4,9212 + 101f984: e17ffe17 ldw r5,-8(fp) + 101f988: 000d883a mov r6,zero + 101f98c: 01c07fc4 movi r7,511 + 101f990: 101f8840 call 101f884 + alt_open_fd (&alt_fd_list[STDERR_FILENO], stderr_dev, O_WRONLY, 0777); + 101f994: 010040b4 movhi r4,258 + 101f998: 21090504 addi r4,r4,9236 + 101f99c: e17fff17 ldw r5,-4(fp) + 101f9a0: 01800044 movi r6,1 + 101f9a4: 01c07fc4 movi r7,511 + 101f9a8: 101f8840 call 101f884 +} + 101f9ac: e037883a mov sp,fp + 101f9b0: dfc00117 ldw ra,4(sp) + 101f9b4: df000017 ldw fp,0(sp) + 101f9b8: dec00204 addi sp,sp,8 + 101f9bc: f800283a ret + +0101f9c0 : + */ + +int alt_irq_register (alt_u32 id, + void* context, + alt_isr_func handler) +{ + 101f9c0: deffef04 addi sp,sp,-68 + 101f9c4: df001015 stw fp,64(sp) + 101f9c8: df001004 addi fp,sp,64 + 101f9cc: e13ffc15 stw r4,-16(fp) + 101f9d0: e17ffd15 stw r5,-12(fp) + 101f9d4: e1bffe15 stw r6,-8(fp) + int rc = -EINVAL; + 101f9d8: 00bffa84 movi r2,-22 + 101f9dc: e0bffb15 stw r2,-20(fp) + alt_irq_context status; + + if (id < ALT_NIRQ) + 101f9e0: e0bffc17 ldw r2,-16(fp) + 101f9e4: 10800828 cmpgeui r2,r2,32 + 101f9e8: 1000601e bne r2,zero,101fb6c +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 101f9ec: 0005303a rdctl r2,status + 101f9f0: e0bff915 stw r2,-28(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 101f9f4: e0fff917 ldw r3,-28(fp) + 101f9f8: 00bfff84 movi r2,-2 + 101f9fc: 1884703a and r2,r3,r2 + 101fa00: 1001703a wrctl status,r2 + + return context; + 101fa04: e0bff917 ldw r2,-28(fp) + * interrupts are disabled while the handler tables are updated to ensure + * that an interrupt doesn't occur while the tables are in an inconsistant + * state. + */ + + status = alt_irq_disable_all (); + 101fa08: e0bffa15 stw r2,-24(fp) + + alt_irq[id].handler = handler; + 101fa0c: e0bffc17 ldw r2,-16(fp) + 101fa10: 00c040f4 movhi r3,259 + 101fa14: 18f3c604 addi r3,r3,-12520 + 101fa18: 100490fa slli r2,r2,3 + 101fa1c: 10c7883a add r3,r2,r3 + 101fa20: e0bffe17 ldw r2,-8(fp) + 101fa24: 18800015 stw r2,0(r3) + alt_irq[id].context = context; + 101fa28: e0bffc17 ldw r2,-16(fp) + 101fa2c: 00c040f4 movhi r3,259 + 101fa30: 18f3c604 addi r3,r3,-12520 + 101fa34: 100490fa slli r2,r2,3 + 101fa38: 10c5883a add r2,r2,r3 + 101fa3c: 10c00104 addi r3,r2,4 + 101fa40: e0bffd17 ldw r2,-12(fp) + 101fa44: 18800015 stw r2,0(r3) + + rc = (handler) ? alt_irq_enable (id): alt_irq_disable (id); + 101fa48: e0bffe17 ldw r2,-8(fp) + 101fa4c: 1005003a cmpeq r2,r2,zero + 101fa50: 1000201e bne r2,zero,101fad4 + 101fa54: e0bffc17 ldw r2,-16(fp) + 101fa58: e0bff715 stw r2,-36(fp) +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 101fa5c: 0005303a rdctl r2,status + 101fa60: e0bff615 stw r2,-40(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 101fa64: e0fff617 ldw r3,-40(fp) + 101fa68: 00bfff84 movi r2,-2 + 101fa6c: 1884703a and r2,r3,r2 + 101fa70: 1001703a wrctl status,r2 + + return context; + 101fa74: e0bff617 ldw r2,-40(fp) +static ALT_INLINE int ALT_ALWAYS_INLINE alt_irq_enable (alt_u32 id) +{ + alt_irq_context status; + extern volatile alt_u32 alt_irq_active; + + status = alt_irq_disable_all (); + 101fa78: e0bff815 stw r2,-32(fp) + + alt_irq_active |= (1 << id); + 101fa7c: e0fff717 ldw r3,-36(fp) + 101fa80: 00800044 movi r2,1 + 101fa84: 10c4983a sll r2,r2,r3 + 101fa88: 1007883a mov r3,r2 + 101fa8c: 008040b4 movhi r2,258 + 101fa90: 10952804 addi r2,r2,21664 + 101fa94: 10800017 ldw r2,0(r2) + 101fa98: 1886b03a or r3,r3,r2 + 101fa9c: 008040b4 movhi r2,258 + 101faa0: 10952804 addi r2,r2,21664 + 101faa4: 10c00015 stw r3,0(r2) + NIOS2_WRITE_IENABLE (alt_irq_active); + 101faa8: 008040b4 movhi r2,258 + 101faac: 10952804 addi r2,r2,21664 + 101fab0: 10800017 ldw r2,0(r2) + 101fab4: 100170fa wrctl ienable,r2 + 101fab8: e0bff817 ldw r2,-32(fp) + 101fabc: e0bff515 stw r2,-44(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 101fac0: e0bff517 ldw r2,-44(fp) + 101fac4: 1001703a wrctl status,r2 + + alt_irq_enable_all(status); + + return 0; + 101fac8: 0005883a mov r2,zero + 101facc: e0bfff15 stw r2,-4(fp) + 101fad0: 00002006 br 101fb54 + 101fad4: e0bffc17 ldw r2,-16(fp) + 101fad8: e0bff315 stw r2,-52(fp) +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 101fadc: 0005303a rdctl r2,status + 101fae0: e0bff215 stw r2,-56(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 101fae4: e0fff217 ldw r3,-56(fp) + 101fae8: 00bfff84 movi r2,-2 + 101faec: 1884703a and r2,r3,r2 + 101faf0: 1001703a wrctl status,r2 + + return context; + 101faf4: e0bff217 ldw r2,-56(fp) +static ALT_INLINE int ALT_ALWAYS_INLINE alt_irq_disable (alt_u32 id) +{ + alt_irq_context status; + extern volatile alt_u32 alt_irq_active; + + status = alt_irq_disable_all (); + 101faf8: e0bff415 stw r2,-48(fp) + + alt_irq_active &= ~(1 << id); + 101fafc: e0fff317 ldw r3,-52(fp) + 101fb00: 00800044 movi r2,1 + 101fb04: 10c4983a sll r2,r2,r3 + 101fb08: 0084303a nor r2,zero,r2 + 101fb0c: 1007883a mov r3,r2 + 101fb10: 008040b4 movhi r2,258 + 101fb14: 10952804 addi r2,r2,21664 + 101fb18: 10800017 ldw r2,0(r2) + 101fb1c: 1886703a and r3,r3,r2 + 101fb20: 008040b4 movhi r2,258 + 101fb24: 10952804 addi r2,r2,21664 + 101fb28: 10c00015 stw r3,0(r2) + NIOS2_WRITE_IENABLE (alt_irq_active); + 101fb2c: 008040b4 movhi r2,258 + 101fb30: 10952804 addi r2,r2,21664 + 101fb34: 10800017 ldw r2,0(r2) + 101fb38: 100170fa wrctl ienable,r2 + 101fb3c: e0bff417 ldw r2,-48(fp) + 101fb40: e0bff115 stw r2,-60(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 101fb44: e0bff117 ldw r2,-60(fp) + 101fb48: 1001703a wrctl status,r2 + + alt_irq_enable_all(status); + + return 0; + 101fb4c: 0005883a mov r2,zero + 101fb50: e0bfff15 stw r2,-4(fp) + 101fb54: e0bfff17 ldw r2,-4(fp) + 101fb58: e0bffb15 stw r2,-20(fp) + 101fb5c: e0bffa17 ldw r2,-24(fp) + 101fb60: e0bff015 stw r2,-64(fp) + 101fb64: e0bff017 ldw r2,-64(fp) + 101fb68: 1001703a wrctl status,r2 + + alt_irq_enable_all(status); + } + return rc; + 101fb6c: e0bffb17 ldw r2,-20(fp) +} + 101fb70: e037883a mov sp,fp + 101fb74: df000017 ldw fp,0(sp) + 101fb78: dec00104 addi sp,sp,4 + 101fb7c: f800283a ret + +0101fb80 : + * performed for devices. Filesystems are required to handle the ioctl() call + * themselves, and report the error from the filesystems open() function. + */ + +static int alt_file_locked (alt_fd* fd) +{ + 101fb80: defffc04 addi sp,sp,-16 + 101fb84: df000315 stw fp,12(sp) + 101fb88: df000304 addi fp,sp,12 + 101fb8c: e13ffe15 stw r4,-8(fp) + + /* + * Mark the file descriptor as belonging to a device. + */ + + fd->fd_flags |= ALT_FD_DEV; + 101fb90: e0bffe17 ldw r2,-8(fp) + 101fb94: 10800217 ldw r2,8(r2) + 101fb98: 10d00034 orhi r3,r2,16384 + 101fb9c: e0bffe17 ldw r2,-8(fp) + 101fba0: 10c00215 stw r3,8(r2) + /* + * Loop through all current file descriptors searching for one that's locked + * for exclusive access. If a match is found, generate an error. + */ + + for (i = 0; i <= alt_max_fd; i++) + 101fba4: e03ffd15 stw zero,-12(fp) + 101fba8: 00002006 br 101fc2c + { + if ((alt_fd_list[i].dev == fd->dev) && + 101fbac: e0bffd17 ldw r2,-12(fp) + 101fbb0: 00c040b4 movhi r3,258 + 101fbb4: 18c8ff04 addi r3,r3,9212 + 101fbb8: 10800324 muli r2,r2,12 + 101fbbc: 10c5883a add r2,r2,r3 + 101fbc0: 10c00017 ldw r3,0(r2) + 101fbc4: e0bffe17 ldw r2,-8(fp) + 101fbc8: 10800017 ldw r2,0(r2) + 101fbcc: 1880141e bne r3,r2,101fc20 + 101fbd0: e0bffd17 ldw r2,-12(fp) + 101fbd4: 00c040b4 movhi r3,258 + 101fbd8: 18c8ff04 addi r3,r3,9212 + 101fbdc: 10800324 muli r2,r2,12 + 101fbe0: 10c5883a add r2,r2,r3 + 101fbe4: 10800204 addi r2,r2,8 + 101fbe8: 10800017 ldw r2,0(r2) + 101fbec: 1004403a cmpge r2,r2,zero + 101fbf0: 10000b1e bne r2,zero,101fc20 + 101fbf4: e0bffd17 ldw r2,-12(fp) + 101fbf8: 10800324 muli r2,r2,12 + 101fbfc: 1007883a mov r3,r2 + 101fc00: 008040b4 movhi r2,258 + 101fc04: 1088ff04 addi r2,r2,9212 + 101fc08: 1887883a add r3,r3,r2 + 101fc0c: e0bffe17 ldw r2,-8(fp) + 101fc10: 18800326 beq r3,r2,101fc20 + (alt_fd_list[i].fd_flags & ALT_FD_EXCL) && + (&alt_fd_list[i] != fd)) + { + return -EACCES; + 101fc14: 00bffcc4 movi r2,-13 + 101fc18: e0bfff15 stw r2,-4(fp) + 101fc1c: 00000a06 br 101fc48 + /* + * Loop through all current file descriptors searching for one that's locked + * for exclusive access. If a match is found, generate an error. + */ + + for (i = 0; i <= alt_max_fd; i++) + 101fc20: e0bffd17 ldw r2,-12(fp) + 101fc24: 10800044 addi r2,r2,1 + 101fc28: e0bffd15 stw r2,-12(fp) + 101fc2c: 008040b4 movhi r2,258 + 101fc30: 108dd004 addi r2,r2,14144 + 101fc34: 10800017 ldw r2,0(r2) + 101fc38: 1007883a mov r3,r2 + 101fc3c: e0bffd17 ldw r2,-12(fp) + 101fc40: 18bfda2e bgeu r3,r2,101fbac + } + } + + /* The device is not locked */ + + return 0; + 101fc44: e03fff15 stw zero,-4(fp) + 101fc48: e0bfff17 ldw r2,-4(fp) +} + 101fc4c: e037883a mov sp,fp + 101fc50: df000017 ldw fp,0(sp) + 101fc54: dec00104 addi sp,sp,4 + 101fc58: f800283a ret + +0101fc5c : + * + * ALT_OPEN is mapped onto the open() system call in alt_syscall.h + */ + +int ALT_OPEN (const char* file, int flags, int mode) +{ + 101fc5c: defff404 addi sp,sp,-48 + 101fc60: dfc00b15 stw ra,44(sp) + 101fc64: df000a15 stw fp,40(sp) + 101fc68: df000a04 addi fp,sp,40 + 101fc6c: e13ffb15 stw r4,-20(fp) + 101fc70: e17ffc15 stw r5,-16(fp) + 101fc74: e1bffd15 stw r6,-12(fp) + alt_dev* dev; + alt_fd* fd; + int index = -1; + 101fc78: 00bfffc4 movi r2,-1 + 101fc7c: e0bff815 stw r2,-32(fp) + int status = -ENODEV; + 101fc80: 00bffb44 movi r2,-19 + 101fc84: e0bff715 stw r2,-36(fp) + int isafs = 0; + 101fc88: e03ff615 stw zero,-40(fp) + /* + * Check the device list, to see if a device with a matching name is + * registered. + */ + + if (!(dev = alt_find_dev (file, &alt_dev_list))) + 101fc8c: e13ffb17 ldw r4,-20(fp) + 101fc90: 014040b4 movhi r5,258 + 101fc94: 294dce04 addi r5,r5,14136 + 101fc98: 101f7c00 call 101f7c0 + 101fc9c: e0bffa15 stw r2,-24(fp) + 101fca0: e0bffa17 ldw r2,-24(fp) + 101fca4: 1004c03a cmpne r2,r2,zero + 101fca8: 1000051e bne r2,zero,101fcc0 + { + /* No matching device, so try the filesystem list */ + + dev = alt_find_file (file); + 101fcac: e13ffb17 ldw r4,-20(fp) + 101fcb0: 10204f40 call 10204f4 + 101fcb4: e0bffa15 stw r2,-24(fp) + isafs = 1; + 101fcb8: 00800044 movi r2,1 + 101fcbc: e0bff615 stw r2,-40(fp) + + /* + * If a matching device or filesystem is found, allocate a file descriptor. + */ + + if (dev) + 101fcc0: e0bffa17 ldw r2,-24(fp) + 101fcc4: 1005003a cmpeq r2,r2,zero + 101fcc8: 1000301e bne r2,zero,101fd8c + { + if ((index = alt_get_fd (dev)) < 0) + 101fccc: e13ffa17 ldw r4,-24(fp) + 101fcd0: 10206140 call 1020614 + 101fcd4: e0bff815 stw r2,-32(fp) + 101fcd8: e0bff817 ldw r2,-32(fp) + 101fcdc: 1004403a cmpge r2,r2,zero + 101fce0: 1000031e bne r2,zero,101fcf0 + { + status = index; + 101fce4: e0bff817 ldw r2,-32(fp) + 101fce8: e0bff715 stw r2,-36(fp) + 101fcec: 00002906 br 101fd94 + } + else + { + fd = &alt_fd_list[index]; + 101fcf0: e0bff817 ldw r2,-32(fp) + 101fcf4: 10800324 muli r2,r2,12 + 101fcf8: 1007883a mov r3,r2 + 101fcfc: 008040b4 movhi r2,258 + 101fd00: 1088ff04 addi r2,r2,9212 + 101fd04: 1885883a add r2,r3,r2 + 101fd08: e0bff915 stw r2,-28(fp) + fd->fd_flags = (flags & ~ALT_FD_FLAGS_MASK); + 101fd0c: e0fffc17 ldw r3,-16(fp) + 101fd10: 00900034 movhi r2,16384 + 101fd14: 10bfffc4 addi r2,r2,-1 + 101fd18: 1886703a and r3,r3,r2 + 101fd1c: e0bff917 ldw r2,-28(fp) + 101fd20: 10c00215 stw r3,8(r2) + + /* If this is a device, ensure it isn't already locked */ + + if (isafs || ((status = alt_file_locked (fd)) >= 0)) + 101fd24: e0bff617 ldw r2,-40(fp) + 101fd28: 1004c03a cmpne r2,r2,zero + 101fd2c: 1000061e bne r2,zero,101fd48 + 101fd30: e13ff917 ldw r4,-28(fp) + 101fd34: 101fb800 call 101fb80 + 101fd38: e0bff715 stw r2,-36(fp) + 101fd3c: e0bff717 ldw r2,-36(fp) + 101fd40: 1004803a cmplt r2,r2,zero + 101fd44: 1000131e bne r2,zero,101fd94 + /* + * If the device or filesystem provides an open() callback function, + * call it now to perform any device/filesystem specific operations. + */ + + status = (dev->open) ? dev->open(fd, file, flags, mode): 0; + 101fd48: e0bffa17 ldw r2,-24(fp) + 101fd4c: 10800317 ldw r2,12(r2) + 101fd50: 1005003a cmpeq r2,r2,zero + 101fd54: 1000091e bne r2,zero,101fd7c + 101fd58: e0bffa17 ldw r2,-24(fp) + 101fd5c: 10800317 ldw r2,12(r2) + 101fd60: e13ff917 ldw r4,-28(fp) + 101fd64: e17ffb17 ldw r5,-20(fp) + 101fd68: e1bffc17 ldw r6,-16(fp) + 101fd6c: e1fffd17 ldw r7,-12(fp) + 101fd70: 103ee83a callr r2 + 101fd74: e0bfff15 stw r2,-4(fp) + 101fd78: 00000106 br 101fd80 + 101fd7c: e03fff15 stw zero,-4(fp) + 101fd80: e0bfff17 ldw r2,-4(fp) + 101fd84: e0bff715 stw r2,-36(fp) + 101fd88: 00000206 br 101fd94 + } + } + } + else + { + status = -ENODEV; + 101fd8c: 00bffb44 movi r2,-19 + 101fd90: e0bff715 stw r2,-36(fp) + } + + /* Allocation failed, so clean up and return an error */ + + if (status < 0) + 101fd94: e0bff717 ldw r2,-36(fp) + 101fd98: 1004403a cmpge r2,r2,zero + 101fd9c: 1000091e bne r2,zero,101fdc4 + { + alt_release_fd (index); + 101fda0: e13ff817 ldw r4,-32(fp) + 101fda4: 1014cfc0 call 1014cfc + ALT_ERRNO = -status; + 101fda8: 101fde40 call 101fde4 + 101fdac: e0fff717 ldw r3,-36(fp) + 101fdb0: 00c7c83a sub r3,zero,r3 + 101fdb4: 10c00015 stw r3,0(r2) + return -1; + 101fdb8: 00bfffc4 movi r2,-1 + 101fdbc: e0bffe15 stw r2,-8(fp) + 101fdc0: 00000206 br 101fdcc + } + + /* return the reference upon success */ + + return index; + 101fdc4: e0bff817 ldw r2,-32(fp) + 101fdc8: e0bffe15 stw r2,-8(fp) + 101fdcc: e0bffe17 ldw r2,-8(fp) +} + 101fdd0: e037883a mov sp,fp + 101fdd4: dfc00117 ldw ra,4(sp) + 101fdd8: df000017 ldw fp,0(sp) + 101fddc: dec00204 addi sp,sp,8 + 101fde0: f800283a ret + +0101fde4 : +#undef errno + +extern int errno; + +static ALT_INLINE int* alt_get_errno(void) +{ + 101fde4: defffd04 addi sp,sp,-12 + 101fde8: dfc00215 stw ra,8(sp) + 101fdec: df000115 stw fp,4(sp) + 101fdf0: df000104 addi fp,sp,4 + return ((alt_errno) ? alt_errno() : &errno); + 101fdf4: 008040b4 movhi r2,258 + 101fdf8: 108dd104 addi r2,r2,14148 + 101fdfc: 10800017 ldw r2,0(r2) + 101fe00: 1005003a cmpeq r2,r2,zero + 101fe04: 1000061e bne r2,zero,101fe20 + 101fe08: 008040b4 movhi r2,258 + 101fe0c: 108dd104 addi r2,r2,14148 + 101fe10: 10800017 ldw r2,0(r2) + 101fe14: 103ee83a callr r2 + 101fe18: e0bfff15 stw r2,-4(fp) + 101fe1c: 00000306 br 101fe2c + 101fe20: 008040b4 movhi r2,258 + 101fe24: 10950804 addi r2,r2,21536 + 101fe28: e0bfff15 stw r2,-4(fp) + 101fe2c: e0bfff17 ldw r2,-4(fp) +} + 101fe30: e037883a mov sp,fp + 101fe34: dfc00117 ldw ra,4(sp) + 101fe38: df000017 ldw fp,0(sp) + 101fe3c: dec00204 addi sp,sp,8 + 101fe40: f800283a ret + +0101fe44 : + * alarms. Alternatively an alarm can unregister itself by returning zero when + * the alarm executes. + */ + +void alt_alarm_stop (alt_alarm* alarm) +{ + 101fe44: defffa04 addi sp,sp,-24 + 101fe48: df000515 stw fp,20(sp) + 101fe4c: df000504 addi fp,sp,20 + 101fe50: e13fff15 stw r4,-4(fp) +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 101fe54: 0005303a rdctl r2,status + 101fe58: e0bffd15 stw r2,-12(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 101fe5c: e0fffd17 ldw r3,-12(fp) + 101fe60: 00bfff84 movi r2,-2 + 101fe64: 1884703a and r2,r3,r2 + 101fe68: 1001703a wrctl status,r2 + + return context; + 101fe6c: e0bffd17 ldw r2,-12(fp) + alt_irq_context irq_context; + + irq_context = alt_irq_disable_all(); + 101fe70: e0bffe15 stw r2,-8(fp) + alt_llist_remove (&alarm->llist); + 101fe74: e0bfff17 ldw r2,-4(fp) + 101fe78: e0bffc15 stw r2,-16(fp) + * input argument is the element to remove. + */ + +static ALT_INLINE void ALT_ALWAYS_INLINE alt_llist_remove(alt_llist* entry) +{ + entry->next->previous = entry->previous; + 101fe7c: e0bffc17 ldw r2,-16(fp) + 101fe80: 10c00017 ldw r3,0(r2) + 101fe84: e0bffc17 ldw r2,-16(fp) + 101fe88: 10800117 ldw r2,4(r2) + 101fe8c: 18800115 stw r2,4(r3) + entry->previous->next = entry->next; + 101fe90: e0bffc17 ldw r2,-16(fp) + 101fe94: 10c00117 ldw r3,4(r2) + 101fe98: e0bffc17 ldw r2,-16(fp) + 101fe9c: 10800017 ldw r2,0(r2) + 101fea0: 18800015 stw r2,0(r3) + /* + * Set the entry to point to itself, so that any further calls to + * alt_llist_remove() are harmless. + */ + + entry->previous = entry; + 101fea4: e0fffc17 ldw r3,-16(fp) + 101fea8: e0bffc17 ldw r2,-16(fp) + 101feac: 18800115 stw r2,4(r3) + entry->next = entry; + 101feb0: e0fffc17 ldw r3,-16(fp) + 101feb4: e0bffc17 ldw r2,-16(fp) + 101feb8: 18800015 stw r2,0(r3) + 101febc: e0bffe17 ldw r2,-8(fp) + 101fec0: e0bffb15 stw r2,-20(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 101fec4: e0bffb17 ldw r2,-20(fp) + 101fec8: 1001703a wrctl status,r2 + alt_irq_enable_all (irq_context); +} + 101fecc: e037883a mov sp,fp + 101fed0: df000017 ldw fp,0(sp) + 101fed4: dec00104 addi sp,sp,4 + 101fed8: f800283a ret + +0101fedc : + * + * alt_tick() is expected to run at interrupt level. + */ + +void alt_tick (void) +{ + 101fedc: defffb04 addi sp,sp,-20 + 101fee0: dfc00415 stw ra,16(sp) + 101fee4: df000315 stw fp,12(sp) + 101fee8: df000304 addi fp,sp,12 + alt_alarm* next; + alt_alarm* alarm = (alt_alarm*) alt_alarm_list.next; + 101feec: d0a03a17 ldw r2,-32536(gp) + 101fef0: e0bffe15 stw r2,-8(fp) + + alt_u32 next_callback; + + /* update the tick counter */ + + _alt_nticks++; + 101fef4: d0a77117 ldw r2,-25148(gp) + 101fef8: 10800044 addi r2,r2,1 + 101fefc: d0a77115 stw r2,-25148(gp) + + /* process the registered callbacks */ + + while (alarm != (alt_alarm*) &alt_alarm_list) + 101ff00: 00003106 br 101ffc8 + { + next = (alt_alarm*) alarm->llist.next; + 101ff04: e0bffe17 ldw r2,-8(fp) + 101ff08: 10800017 ldw r2,0(r2) + 101ff0c: e0bfff15 stw r2,-4(fp) + /* + * Upon the tick-counter rolling over it is safe to clear the + * roll-over flag; once the flag is cleared this (or subsequnt) + * tick events are enabled to generate an alarm event. + */ + if ((alarm->rollover) && (_alt_nticks == 0)) + 101ff10: e0bffe17 ldw r2,-8(fp) + 101ff14: 10800403 ldbu r2,16(r2) + 101ff18: 10803fcc andi r2,r2,255 + 101ff1c: 1005003a cmpeq r2,r2,zero + 101ff20: 1000051e bne r2,zero,101ff38 + 101ff24: d0a77117 ldw r2,-25148(gp) + 101ff28: 1004c03a cmpne r2,r2,zero + 101ff2c: 1000021e bne r2,zero,101ff38 + { + alarm->rollover = 0; + 101ff30: e0bffe17 ldw r2,-8(fp) + 101ff34: 10000405 stb zero,16(r2) + } + + /* if the alarm period has expired, make the callback */ + if ((alarm->time <= _alt_nticks) && (alarm->rollover == 0)) + 101ff38: e0bffe17 ldw r2,-8(fp) + 101ff3c: 10c00217 ldw r3,8(r2) + 101ff40: d0a77117 ldw r2,-25148(gp) + 101ff44: 10c01e36 bltu r2,r3,101ffc0 + 101ff48: e0bffe17 ldw r2,-8(fp) + 101ff4c: 10800403 ldbu r2,16(r2) + 101ff50: 10803fcc andi r2,r2,255 + 101ff54: 1004c03a cmpne r2,r2,zero + 101ff58: 1000191e bne r2,zero,101ffc0 + { + next_callback = alarm->callback (alarm->context); + 101ff5c: e0bffe17 ldw r2,-8(fp) + 101ff60: 10c00317 ldw r3,12(r2) + 101ff64: e0bffe17 ldw r2,-8(fp) + 101ff68: 11000517 ldw r4,20(r2) + 101ff6c: 183ee83a callr r3 + 101ff70: e0bffd15 stw r2,-12(fp) + + /* deactivate the alarm if the return value is zero */ + + if (next_callback == 0) + 101ff74: e0bffd17 ldw r2,-12(fp) + 101ff78: 1004c03a cmpne r2,r2,zero + 101ff7c: 1000031e bne r2,zero,101ff8c + { + alt_alarm_stop (alarm); + 101ff80: e13ffe17 ldw r4,-8(fp) + 101ff84: 101fe440 call 101fe44 + 101ff88: 00000d06 br 101ffc0 + } + else + { + alarm->time += next_callback; + 101ff8c: e0bffe17 ldw r2,-8(fp) + 101ff90: 10c00217 ldw r3,8(r2) + 101ff94: e0bffd17 ldw r2,-12(fp) + 101ff98: 1887883a add r3,r3,r2 + 101ff9c: e0bffe17 ldw r2,-8(fp) + 101ffa0: 10c00215 stw r3,8(r2) + /* + * If the desired alarm time causes a roll-over, set the rollover + * flag. This will prevent the subsequent tick event from causing + * an alarm too early. + */ + if(alarm->time < _alt_nticks) + 101ffa4: e0bffe17 ldw r2,-8(fp) + 101ffa8: 10c00217 ldw r3,8(r2) + 101ffac: d0a77117 ldw r2,-25148(gp) + 101ffb0: 1880032e bgeu r3,r2,101ffc0 + { + alarm->rollover = 1; + 101ffb4: e0fffe17 ldw r3,-8(fp) + 101ffb8: 00800044 movi r2,1 + 101ffbc: 18800405 stb r2,16(r3) + } + } + } + alarm = next; + 101ffc0: e0bfff17 ldw r2,-4(fp) + 101ffc4: e0bffe15 stw r2,-8(fp) + + _alt_nticks++; + + /* process the registered callbacks */ + + while (alarm != (alt_alarm*) &alt_alarm_list) + 101ffc8: d0e03a04 addi r3,gp,-32536 + 101ffcc: e0bffe17 ldw r2,-8(fp) + 101ffd0: 10ffcc1e bne r2,r3,101ff04 + + /* + * Update the operating system specific timer facilities. + */ + + ALT_OS_TIME_TICK(); + 101ffd4: 1015ffc0 call 1015ffc +} + 101ffd8: e037883a mov sp,fp + 101ffdc: dfc00117 ldw ra,4(sp) + 101ffe0: df000017 ldw fp,0(sp) + 101ffe4: dec00204 addi sp,sp,8 + 101ffe8: f800283a ret + +0101ffec : +/* + * To initialize the internal interrupt controller, just clear the IENABLE + * register so that all possible IRQs are disabled. + */ +void altera_nios2_qsys_irq_init(void) +{ + 101ffec: deffff04 addi sp,sp,-4 + 101fff0: df000015 stw fp,0(sp) + 101fff4: d839883a mov fp,sp + NIOS2_WRITE_IENABLE(0); + 101fff8: 000170fa wrctl ienable,zero +} + 101fffc: e037883a mov sp,fp + 1020000: df000017 ldw fp,0(sp) + 1020004: dec00104 addi sp,sp,4 + 1020008: f800283a ret + +0102000c : + + /* + * Save the remaining registers to the stack. + */ + + addi sp, sp, -44 + 102000c: defff504 addi sp,sp,-44 + bltu sp, et, .Lstack_overflow + +#endif + +#if OS_THREAD_SAFE_NEWLIB + ldw r3, %gprel(_impure_ptr)(gp) /* load the pointer */ + 1020010: d0e00f17 ldw r3,-32708(gp) +#endif /* OS_THREAD_SAFE_NEWLIB */ + + ldw r4, %gprel(OSTCBCur)(gp) + 1020014: d1276a17 ldw r4,-25176(gp) + + stw ra, 0(sp) + 1020018: dfc00015 stw ra,0(sp) + stw fp, 4(sp) + 102001c: df000115 stw fp,4(sp) + stw r23, 8(sp) + 1020020: ddc00215 stw r23,8(sp) + stw r22, 12(sp) + 1020024: dd800315 stw r22,12(sp) + stw r21, 16(sp) + 1020028: dd400415 stw r21,16(sp) + stw r20, 20(sp) + 102002c: dd000515 stw r20,20(sp) + stw r19, 24(sp) + 1020030: dcc00615 stw r19,24(sp) + stw r18, 28(sp) + 1020034: dc800715 stw r18,28(sp) + stw r17, 32(sp) + 1020038: dc400815 stw r17,32(sp) + stw r16, 36(sp) + 102003c: dc000915 stw r16,36(sp) + * store the current value of _impure_ptr so it can be restored + * later; _impure_ptr is asigned on a per task basis. It is used + * by Newlib to achieve reentrancy. + */ + + stw r3, 40(sp) /* save the impure pointer */ + 1020040: d8c00a15 stw r3,40(sp) + /* + * Save the current tasks stack pointer into the current tasks OS_TCB. + * i.e. OSTCBCur->OSTCBStkPtr = sp; + */ + + stw sp, (r4) /* save the stack pointer (OSTCBStkPtr */ + 1020044: 26c00015 stw sp,0(r4) + + /* + * Call the user definable OSTaskSWHook() + */ + + call OSTaskSwHook + 1020048: 102042c0 call 102042c + /* + * OSTCBCur = OSTCBHighRdy; + * OSPrioCur = OSPrioHighRdy; + */ + + ldw r4, %gprel(OSTCBHighRdy)(gp) + 102004c: d1276517 ldw r4,-25196(gp) + ldb r5, %gprel(OSPrioHighRdy)(gp) + 1020050: d1675d07 ldb r5,-25228(gp) + + stw r4, %gprel(OSTCBCur)(gp) /* set the current task to be the new task */ + 1020054: d1276a15 stw r4,-25176(gp) + stb r5, %gprel(OSPrioCur)(gp) /* store the new task's priority as the current */ + 1020058: d1675d45 stb r5,-25227(gp) + + /* + * Set the stack pointer to point to the new task's stack + */ + + ldw sp, (r4) /* the stack pointer is the first entry in the OS_TCB structure */ + 102005c: 26c00017 ldw sp,0(r4) + /* + * restore the value of _impure_ptr ; _impure_ptr is asigned on a + * per task basis. It is used by Newlib to achieve reentrancy. + */ + + ldw r3, 40(sp) /* load the new impure pointer */ + 1020060: d8c00a17 ldw r3,40(sp) + + /* + * Restore the saved registers for the new task. + */ + + ldw ra, 0(sp) + 1020064: dfc00017 ldw ra,0(sp) + ldw fp, 4(sp) + 1020068: df000117 ldw fp,4(sp) + ldw r23, 8(sp) + 102006c: ddc00217 ldw r23,8(sp) + ldw r22, 12(sp) + 1020070: dd800317 ldw r22,12(sp) + ldw r21, 16(sp) + 1020074: dd400417 ldw r21,16(sp) + ldw r20, 20(sp) + 1020078: dd000517 ldw r20,20(sp) + ldw r19, 24(sp) + 102007c: dcc00617 ldw r19,24(sp) + ldw r18, 28(sp) + 1020080: dc800717 ldw r18,28(sp) + ldw r17, 32(sp) + 1020084: dc400817 ldw r17,32(sp) + ldw r16, 36(sp) + 1020088: dc000917 ldw r16,36(sp) + +#if OS_THREAD_SAFE_NEWLIB + + stw r3, %gprel(_impure_ptr)(gp) /* update _impure_ptr */ + 102008c: d0e00f15 stw r3,-32708(gp) + + stw et, %gprel(alt_stack_limit_value)(gp) + +#endif + + addi sp, sp, 44 + 1020090: dec00b04 addi sp,sp,44 + + /* + * resume execution of the new task. + */ + + ret + 1020094: f800283a ret + +01020098 : + + /* + * disable interrupts so that the scheduler doesn't run while + * we're initialising this task. + */ + rdctl r18, status + 1020098: 0025303a rdctl r18,status + subi r17, zero, 2 /* r17 = 0xfffffffe */ + 102009c: 047fff84 movi r17,-2 + and r18, r18, r17 + 10200a0: 9464703a and r18,r18,r17 + wrctl status, r18 + 10200a4: 9001703a wrctl status,r18 + + /* + * Call the user definable OSTaskSWHook() + */ + + call OSTaskSwHook + 10200a8: 102042c0 call 102042c + + /* + * set OSRunning = TRUE. + */ + + movi r18, 1 /* set r18 to the value 'TRUE' */ + 10200ac: 04800044 movi r18,1 + stb r18, %gprel(OSRunning)(gp) /* save this to OSRunning */ + 10200b0: d4a75b45 stb r18,-25235(gp) + + /* + * start execution of the new task. + */ + + br 9b + 10200b4: 003fe506 br 102004c + +010200b8 : + +OSStartTsk: + /* This instruction is never executed. Its here to make the + * backtrace work right + */ + movi sp, 0 + 10200b8: 06c00004 movi sp,0 + + /* Enable interrupts */ + rdctl r2, status + 10200bc: 0005303a rdctl r2,status + ori r2, r2, 0x1 + 10200c0: 10800054 ori r2,r2,1 + wrctl status, r2 + 10200c4: 1001703a wrctl status,r2 + + ldw r2, 4(sp) + 10200c8: d8800117 ldw r2,4(sp) + ldw r4, 0(sp) + 10200cc: d9000017 ldw r4,0(sp) + + addi sp, sp, 8 + 10200d0: dec00204 addi sp,sp,8 + + callr r2 + 10200d4: 103ee83a callr r2 + + nop + 10200d8: 0001883a nop + +010200dc : + * been placed on the stack in the proper order. + * + ***********************************************************************************************/ + +OS_STK *OSTaskStkInit(void (*task)(void *pd), void *pdata, OS_STK *pstk, INT16U opt) +{ + 10200dc: defff704 addi sp,sp,-36 + 10200e0: dfc00815 stw ra,32(sp) + 10200e4: df000715 stw fp,28(sp) + 10200e8: df000704 addi fp,sp,28 + 10200ec: e13ffc15 stw r4,-16(fp) + 10200f0: e17ffd15 stw r5,-12(fp) + 10200f4: e1bffe15 stw r6,-8(fp) + 10200f8: e1ffff0d sth r7,-4(fp) + * create and initialise the impure pointer used for Newlib thread local storage. + * This is only done if the C library is being used in a thread safe mode. Otherwise + * a single reent structure is used for all threads, which saves memory. + */ + + local_impure_ptr = (struct _reent*)((((INT32U)(pstk)) & ~0x3) - sizeof(struct _reent)); + 10200fc: e0bffe17 ldw r2,-8(fp) + 1020100: 1007883a mov r3,r2 + 1020104: 00bfff04 movi r2,-4 + 1020108: 1884703a and r2,r3,r2 + 102010c: 10bf0004 addi r2,r2,-1024 + 1020110: e0bff915 stw r2,-28(fp) + + _REENT_INIT_PTR (local_impure_ptr); + 1020114: e0bff917 ldw r2,-28(fp) + 1020118: 10000015 stw zero,0(r2) + 102011c: e0bff917 ldw r2,-28(fp) + 1020120: 10c0bb04 addi r3,r2,748 + 1020124: e0bff917 ldw r2,-28(fp) + 1020128: 10c00115 stw r3,4(r2) + 102012c: e0bff917 ldw r2,-28(fp) + 1020130: 1080bb04 addi r2,r2,748 + 1020134: 10c01704 addi r3,r2,92 + 1020138: e0bff917 ldw r2,-28(fp) + 102013c: 10c00215 stw r3,8(r2) + 1020140: e0bff917 ldw r2,-28(fp) + 1020144: 1080bb04 addi r2,r2,748 + 1020148: 10c02e04 addi r3,r2,184 + 102014c: e0bff917 ldw r2,-28(fp) + 1020150: 10c00315 stw r3,12(r2) + 1020154: e0bff917 ldw r2,-28(fp) + 1020158: 10000415 stw zero,16(r2) + 102015c: e0bff917 ldw r2,-28(fp) + 1020160: 10800504 addi r2,r2,20 + 1020164: 1009883a mov r4,r2 + 1020168: 01800644 movi r6,25 + 102016c: 000b883a mov r5,zero + 1020170: 100abbc0 call 100abbc + 1020174: e0bff917 ldw r2,-28(fp) + 1020178: 10000c15 stw zero,48(r2) + 102017c: e0fff917 ldw r3,-28(fp) + 1020180: 008040b4 movhi r2,258 + 1020184: 1086ef04 addi r2,r2,7100 + 1020188: 18800d15 stw r2,52(r3) + 102018c: e0bff917 ldw r2,-28(fp) + 1020190: 10000e15 stw zero,56(r2) + 1020194: e0bff917 ldw r2,-28(fp) + 1020198: 10000f15 stw zero,60(r2) + 102019c: e0bff917 ldw r2,-28(fp) + 10201a0: 10001015 stw zero,64(r2) + 10201a4: e0bff917 ldw r2,-28(fp) + 10201a8: 10001115 stw zero,68(r2) + 10201ac: e0bff917 ldw r2,-28(fp) + 10201b0: 10001215 stw zero,72(r2) + 10201b4: e0bff917 ldw r2,-28(fp) + 10201b8: 10001315 stw zero,76(r2) + 10201bc: e0bff917 ldw r2,-28(fp) + 10201c0: 10001415 stw zero,80(r2) + 10201c4: e0bff917 ldw r2,-28(fp) + 10201c8: 10001515 stw zero,84(r2) + 10201cc: e0bff917 ldw r2,-28(fp) + 10201d0: 10001615 stw zero,88(r2) + 10201d4: e0bff917 ldw r2,-28(fp) + 10201d8: 10001715 stw zero,92(r2) + 10201dc: e0bff917 ldw r2,-28(fp) + 10201e0: 10001805 stb zero,96(r2) + 10201e4: e0bff917 ldw r2,-28(fp) + 10201e8: 10801f04 addi r2,r2,124 + 10201ec: 10000015 stw zero,0(r2) + 10201f0: 10000115 stw zero,4(r2) + 10201f4: 10000215 stw zero,8(r2) + 10201f8: 10000315 stw zero,12(r2) + 10201fc: 10000415 stw zero,16(r2) + 1020200: 10000515 stw zero,20(r2) + 1020204: 10000615 stw zero,24(r2) + 1020208: 10000715 stw zero,28(r2) + 102020c: 10000815 stw zero,32(r2) + 1020210: e0bff917 ldw r2,-28(fp) + 1020214: 10002815 stw zero,160(r2) + 1020218: e0fff917 ldw r3,-28(fp) + 102021c: 00800044 movi r2,1 + 1020220: 18802915 stw r2,164(r3) + 1020224: 18002a15 stw zero,168(r3) + 1020228: e0fff917 ldw r3,-28(fp) + 102022c: 008cc384 movi r2,13070 + 1020230: 18802b0d sth r2,172(r3) + 1020234: e0fff917 ldw r3,-28(fp) + 1020238: 00aaf344 movi r2,-21555 + 102023c: 18802b8d sth r2,174(r3) + 1020240: e0fff917 ldw r3,-28(fp) + 1020244: 00848d04 movi r2,4660 + 1020248: 18802c0d sth r2,176(r3) + 102024c: e0fff917 ldw r3,-28(fp) + 1020250: 00b99b44 movi r2,-6547 + 1020254: 18802c8d sth r2,178(r3) + 1020258: e0fff917 ldw r3,-28(fp) + 102025c: 00b7bb04 movi r2,-8468 + 1020260: 18802d0d sth r2,180(r3) + 1020264: e0fff917 ldw r3,-28(fp) + 1020268: 00800144 movi r2,5 + 102026c: 18802d8d sth r2,182(r3) + 1020270: e0fff917 ldw r3,-28(fp) + 1020274: 008002c4 movi r2,11 + 1020278: 18802e0d sth r2,184(r3) + 102027c: e0bff917 ldw r2,-28(fp) + 1020280: 10002f15 stw zero,188(r2) + 1020284: e0bff917 ldw r2,-28(fp) + 1020288: 10003015 stw zero,192(r2) + 102028c: e0bff917 ldw r2,-28(fp) + 1020290: 10003115 stw zero,196(r2) + 1020294: e0bff917 ldw r2,-28(fp) + 1020298: 10003215 stw zero,200(r2) + 102029c: e0bff917 ldw r2,-28(fp) + 10202a0: 10003315 stw zero,204(r2) + 10202a4: e0bff917 ldw r2,-28(fp) + 10202a8: 10003415 stw zero,208(r2) + 10202ac: e0bff917 ldw r2,-28(fp) + 10202b0: 10003e15 stw zero,248(r2) + 10202b4: e0bff917 ldw r2,-28(fp) + 10202b8: 10003f15 stw zero,252(r2) + 10202bc: e0bff917 ldw r2,-28(fp) + 10202c0: 10004015 stw zero,256(r2) + 10202c4: e0bff917 ldw r2,-28(fp) + 10202c8: 10004115 stw zero,260(r2) + 10202cc: e0bff917 ldw r2,-28(fp) + 10202d0: 10004215 stw zero,264(r2) + 10202d4: e0bff917 ldw r2,-28(fp) + 10202d8: 10004315 stw zero,268(r2) + 10202dc: e0bff917 ldw r2,-28(fp) + 10202e0: 10004415 stw zero,272(r2) + 10202e4: e0bff917 ldw r2,-28(fp) + 10202e8: 10004515 stw zero,276(r2) + 10202ec: e0bff917 ldw r2,-28(fp) + 10202f0: 10004615 stw zero,280(r2) + 10202f4: e0bff917 ldw r2,-28(fp) + 10202f8: 10004715 stw zero,284(r2) + 10202fc: e0bff917 ldw r2,-28(fp) + 1020300: 10003505 stb zero,212(r2) + 1020304: e0bff917 ldw r2,-28(fp) + 1020308: 10003705 stb zero,220(r2) + 102030c: e0bff917 ldw r2,-28(fp) + 1020310: 10003d15 stw zero,244(r2) + 1020314: e0bff917 ldw r2,-28(fp) + 1020318: 10005215 stw zero,328(r2) + 102031c: e0bff917 ldw r2,-28(fp) + 1020320: 10005315 stw zero,332(r2) + 1020324: e0bff917 ldw r2,-28(fp) + 1020328: 10005415 stw zero,336(r2) + 102032c: e0bff917 ldw r2,-28(fp) + 1020330: 10005515 stw zero,340(r2) + 1020334: e0bff917 ldw r2,-28(fp) + 1020338: 1000b515 stw zero,724(r2) + 102033c: e0bff917 ldw r2,-28(fp) + 1020340: 10007515 stw zero,468(r2) + 1020344: e0bff917 ldw r2,-28(fp) + 1020348: 1000b715 stw zero,732(r2) + 102034c: e0bff917 ldw r2,-28(fp) + 1020350: 1000b815 stw zero,736(r2) + 1020354: e0bff917 ldw r2,-28(fp) + 1020358: 1000b915 stw zero,740(r2) + 102035c: e0bff917 ldw r2,-28(fp) + 1020360: 1000ba15 stw zero,744(r2) + 1020364: e0bff917 ldw r2,-28(fp) + 1020368: 1080bb04 addi r2,r2,748 + 102036c: 1009883a mov r4,r2 + 1020370: 01804504 movi r6,276 + 1020374: 000b883a mov r5,zero + 1020378: 100abbc0 call 100abbc + /* + * create a stack frame at the top of the stack (leaving space for the + * reentrant data structure). + */ + + frame_pointer = (INT32U*) local_impure_ptr; + 102037c: e0bff917 ldw r2,-28(fp) + 1020380: e0bffb15 stw r2,-20(fp) +#else + frame_pointer = (INT32U*) (((INT32U)(pstk)) & ~0x3); +#endif /* OS_THREAD_SAFE_NEWLIB */ + stk = frame_pointer - 13; + 1020384: e0bffb17 ldw r2,-20(fp) + 1020388: 10bff304 addi r2,r2,-52 + 102038c: e0bffa15 stw r2,-24(fp) + + /* Now fill the stack frame. */ + + stk[12] = (INT32U)task; /* task address (ra) */ + 1020390: e0bffa17 ldw r2,-24(fp) + 1020394: 10c00c04 addi r3,r2,48 + 1020398: e0bffc17 ldw r2,-16(fp) + 102039c: 18800015 stw r2,0(r3) + stk[11] = (INT32U) pdata; /* first register argument (r4) */ + 10203a0: e0bffa17 ldw r2,-24(fp) + 10203a4: 10c00b04 addi r3,r2,44 + 10203a8: e0bffd17 ldw r2,-12(fp) + 10203ac: 18800015 stw r2,0(r3) + +#if OS_THREAD_SAFE_NEWLIB + stk[10] = (INT32U) local_impure_ptr; /* value of _impure_ptr for this thread */ + 10203b0: e0bffa17 ldw r2,-24(fp) + 10203b4: 10c00a04 addi r3,r2,40 + 10203b8: e0bff917 ldw r2,-28(fp) + 10203bc: 18800015 stw r2,0(r3) +#endif /* OS_THREAD_SAFE_NEWLIB */ + stk[0] = ((INT32U)&OSStartTsk) + 4;/* exception return address (ea) */ + 10203c0: 008040b4 movhi r2,258 + 10203c4: 10802e04 addi r2,r2,184 + 10203c8: 10c00104 addi r3,r2,4 + 10203cc: e0bffa17 ldw r2,-24(fp) + 10203d0: 10c00015 stw r3,0(r2) + */ + __asm__ (".set OSTCBNext_OFFSET,%0" :: "i" (offsetof(OS_TCB, OSTCBNext))); + __asm__ (".set OSTCBPrio_OFFSET,%0" :: "i" (offsetof(OS_TCB, OSTCBPrio))); + __asm__ (".set OSTCBStkPtr_OFFSET,%0" :: "i" (offsetof(OS_TCB, OSTCBStkPtr))); + + return((OS_STK *)stk); + 10203d4: e0bffa17 ldw r2,-24(fp) +} + 10203d8: e037883a mov sp,fp + 10203dc: dfc00117 ldw ra,4(sp) + 10203e0: df000017 ldw fp,0(sp) + 10203e4: dec00204 addi sp,sp,8 + 10203e8: f800283a ret + +010203ec : +* +* Note(s) : 1) Interrupts are disabled during this call. +********************************************************************************************************* +*/ +void OSTaskCreateHook (OS_TCB *ptcb) +{ + 10203ec: defffe04 addi sp,sp,-8 + 10203f0: df000115 stw fp,4(sp) + 10203f4: df000104 addi fp,sp,4 + 10203f8: e13fff15 stw r4,-4(fp) + ptcb = ptcb; /* Prevent compiler warning */ +} + 10203fc: e037883a mov sp,fp + 1020400: df000017 ldw fp,0(sp) + 1020404: dec00104 addi sp,sp,4 + 1020408: f800283a ret + +0102040c : +* +* Note(s) : 1) Interrupts are disabled during this call. +********************************************************************************************************* +*/ +void OSTaskDelHook (OS_TCB *ptcb) +{ + 102040c: defffe04 addi sp,sp,-8 + 1020410: df000115 stw fp,4(sp) + 1020414: df000104 addi fp,sp,4 + 1020418: e13fff15 stw r4,-4(fp) + ptcb = ptcb; /* Prevent compiler warning */ +} + 102041c: e037883a mov sp,fp + 1020420: df000017 ldw fp,0(sp) + 1020424: dec00104 addi sp,sp,4 + 1020428: f800283a ret + +0102042c : +* will be 'switched in' (i.e. the highest priority task) and, 'OSTCBCur' points to the +* task being switched out (i.e. the preempted task). +********************************************************************************************************* +*/ +void OSTaskSwHook (void) +{ + 102042c: deffff04 addi sp,sp,-4 + 1020430: df000015 stw fp,0(sp) + 1020434: d839883a mov fp,sp +} + 1020438: e037883a mov sp,fp + 102043c: df000017 ldw fp,0(sp) + 1020440: dec00104 addi sp,sp,4 + 1020444: f800283a ret + +01020448 : +* +* Arguments : none +********************************************************************************************************* +*/ +void OSTaskStatHook (void) +{ + 1020448: deffff04 addi sp,sp,-4 + 102044c: df000015 stw fp,0(sp) + 1020450: d839883a mov fp,sp +} + 1020454: e037883a mov sp,fp + 1020458: df000017 ldw fp,0(sp) + 102045c: dec00104 addi sp,sp,4 + 1020460: f800283a ret + +01020464 : +#ifdef ALT_INICHE +void cticks_hook(void); +#endif + +void OSTimeTickHook (void) +{ + 1020464: deffff04 addi sp,sp,-4 + 1020468: df000015 stw fp,0(sp) + 102046c: d839883a mov fp,sp + +#ifdef ALT_INICHE + /* Service the Interniche timer */ + cticks_hook(); +#endif +} + 1020470: e037883a mov sp,fp + 1020474: df000017 ldw fp,0(sp) + 1020478: dec00104 addi sp,sp,4 + 102047c: f800283a ret + +01020480 : + +void OSInitHookBegin(void) +{ + 1020480: deffff04 addi sp,sp,-4 + 1020484: df000015 stw fp,0(sp) + 1020488: d839883a mov fp,sp +#if OS_TMR_EN > 0 + OSTmrCtr = 0; +#endif +} + 102048c: e037883a mov sp,fp + 1020490: df000017 ldw fp,0(sp) + 1020494: dec00104 addi sp,sp,4 + 1020498: f800283a ret + +0102049c : + +void OSInitHookEnd(void) +{ + 102049c: deffff04 addi sp,sp,-4 + 10204a0: df000015 stw fp,0(sp) + 10204a4: d839883a mov fp,sp +} + 10204a8: e037883a mov sp,fp + 10204ac: df000017 ldw fp,0(sp) + 10204b0: dec00104 addi sp,sp,4 + 10204b4: f800283a ret + +010204b8 : + +void OSTaskIdleHook(void) +{ + 10204b8: deffff04 addi sp,sp,-4 + 10204bc: df000015 stw fp,0(sp) + 10204c0: d839883a mov fp,sp +} + 10204c4: e037883a mov sp,fp + 10204c8: df000017 ldw fp,0(sp) + 10204cc: dec00104 addi sp,sp,4 + 10204d0: f800283a ret + +010204d4 : + +void OSTCBInitHook(OS_TCB *ptcb) +{ + 10204d4: defffe04 addi sp,sp,-8 + 10204d8: df000115 stw fp,4(sp) + 10204dc: df000104 addi fp,sp,4 + 10204e0: e13fff15 stw r4,-4(fp) +} + 10204e4: e037883a mov sp,fp + 10204e8: df000017 ldw fp,0(sp) + 10204ec: dec00104 addi sp,sp,4 + 10204f0: f800283a ret + +010204f4 : + * either '/' or '\0' is the prefix of the filename. For example the filename: + * "/myfilesystem/junk.txt" would match: "/myfilesystem", but not: "/myfile". + */ + +alt_dev* alt_find_file (const char* name) +{ + 10204f4: defffa04 addi sp,sp,-24 + 10204f8: dfc00515 stw ra,20(sp) + 10204fc: df000415 stw fp,16(sp) + 1020500: df000404 addi fp,sp,16 + 1020504: e13ffe15 stw r4,-8(fp) + alt_dev* next = (alt_dev*) alt_fs_list.next; + 1020508: 008040b4 movhi r2,258 + 102050c: 108dcc04 addi r2,r2,14128 + 1020510: 10800017 ldw r2,0(r2) + 1020514: e0bffd15 stw r2,-12(fp) + /* + * Check each list entry in turn, until a match is found, or we reach the + * end of the list (i.e. next winds up pointing back to the list head). + */ + + while (next != (alt_dev*) &alt_fs_list) + 1020518: 00003306 br 10205e8 + { + len = strlen(next->name); + 102051c: e0bffd17 ldw r2,-12(fp) + 1020520: 11000217 ldw r4,8(r2) + 1020524: 100b1640 call 100b164 + 1020528: e0bffc15 stw r2,-16(fp) + + if (next->name[len-1] == '/') + 102052c: e0bffd17 ldw r2,-12(fp) + 1020530: 10c00217 ldw r3,8(r2) + 1020534: e0bffc17 ldw r2,-16(fp) + 1020538: 1885883a add r2,r3,r2 + 102053c: 10bfffc4 addi r2,r2,-1 + 1020540: 10800003 ldbu r2,0(r2) + 1020544: 10803fcc andi r2,r2,255 + 1020548: 1080201c xori r2,r2,128 + 102054c: 10bfe004 addi r2,r2,-128 + 1020550: 10800bd8 cmpnei r2,r2,47 + 1020554: 1000031e bne r2,zero,1020564 + { + len -= 1; + 1020558: e0bffc17 ldw r2,-16(fp) + 102055c: 10bfffc4 addi r2,r2,-1 + 1020560: e0bffc15 stw r2,-16(fp) + } + + if (((name[len] == '/') || (name[len] == '\0')) && + 1020564: e0bffc17 ldw r2,-16(fp) + 1020568: 1007883a mov r3,r2 + 102056c: e0bffe17 ldw r2,-8(fp) + 1020570: 1885883a add r2,r3,r2 + 1020574: 10800003 ldbu r2,0(r2) + 1020578: 10803fcc andi r2,r2,255 + 102057c: 1080201c xori r2,r2,128 + 1020580: 10bfe004 addi r2,r2,-128 + 1020584: 10800be0 cmpeqi r2,r2,47 + 1020588: 10000a1e bne r2,zero,10205b4 + 102058c: e0bffc17 ldw r2,-16(fp) + 1020590: 1007883a mov r3,r2 + 1020594: e0bffe17 ldw r2,-8(fp) + 1020598: 1885883a add r2,r3,r2 + 102059c: 10800003 ldbu r2,0(r2) + 10205a0: 10803fcc andi r2,r2,255 + 10205a4: 1080201c xori r2,r2,128 + 10205a8: 10bfe004 addi r2,r2,-128 + 10205ac: 1004c03a cmpne r2,r2,zero + 10205b0: 10000a1e bne r2,zero,10205dc + 10205b4: e0bffd17 ldw r2,-12(fp) + 10205b8: 11000217 ldw r4,8(r2) + 10205bc: e1bffc17 ldw r6,-16(fp) + 10205c0: e17ffe17 ldw r5,-8(fp) + 10205c4: 100a9c80 call 100a9c8 + 10205c8: 1004c03a cmpne r2,r2,zero + 10205cc: 1000031e bne r2,zero,10205dc + !memcmp (next->name, name, len)) + { + /* match found */ + + return next; + 10205d0: e0bffd17 ldw r2,-12(fp) + 10205d4: e0bfff15 stw r2,-4(fp) + 10205d8: 00000806 br 10205fc + } + next = (alt_dev*) next->llist.next; + 10205dc: e0bffd17 ldw r2,-12(fp) + 10205e0: 10800017 ldw r2,0(r2) + 10205e4: e0bffd15 stw r2,-12(fp) + /* + * Check each list entry in turn, until a match is found, or we reach the + * end of the list (i.e. next winds up pointing back to the list head). + */ + + while (next != (alt_dev*) &alt_fs_list) + 10205e8: 00c040b4 movhi r3,258 + 10205ec: 18cdcc04 addi r3,r3,14128 + 10205f0: e0bffd17 ldw r2,-12(fp) + 10205f4: 10ffc91e bne r2,r3,102051c + next = (alt_dev*) next->llist.next; + } + + /* No match found */ + + return NULL; + 10205f8: e03fff15 stw zero,-4(fp) + 10205fc: e0bfff17 ldw r2,-4(fp) +} + 1020600: e037883a mov sp,fp + 1020604: dfc00117 ldw ra,4(sp) + 1020608: df000017 ldw fp,0(sp) + 102060c: dec00204 addi sp,sp,8 + 1020610: f800283a ret + +01020614 : + * the offset of the file descriptor within the file descriptor array). A + * negative value indicates failure. + */ + +int alt_get_fd (alt_dev* dev) +{ + 1020614: defff804 addi sp,sp,-32 + 1020618: dfc00715 stw ra,28(sp) + 102061c: df000615 stw fp,24(sp) + 1020620: df000604 addi fp,sp,24 + 1020624: e13fff15 stw r4,-4(fp) + alt_32 i; + int rc = -EMFILE; + 1020628: 00bffa04 movi r2,-24 + 102062c: e0bffc15 stw r2,-16(fp) + /* + * Take the alt_fd_list_lock semaphore in order to avoid races when + * accessing the file descriptor pool. + */ + + ALT_SEM_PEND(alt_fd_list_lock, 0); + 1020630: 008040b4 movhi r2,258 + 1020634: 10950c04 addi r2,r2,21552 + 1020638: 10800017 ldw r2,0(r2) + 102063c: e0bffa15 stw r2,-24(fp) + 1020640: e03ffb0d sth zero,-20(fp) + 1020644: e17ffb0b ldhu r5,-20(fp) + 1020648: e1bffe04 addi r6,fp,-8 + 102064c: e13ffa17 ldw r4,-24(fp) + 1020650: 101ae180 call 101ae18 + * indicates the highest file descriptor ever allocated. This is used to + * improve efficency when searching the file descriptor list, and + * therefore reduce contention on the alt_fd_list_lock semaphore. + */ + + for (i = 0; i < ALT_MAX_FD; i++) + 1020654: e03ffd15 stw zero,-12(fp) + 1020658: 00001e06 br 10206d4 + { + if (!alt_fd_list[i].dev) + 102065c: e0bffd17 ldw r2,-12(fp) + 1020660: 00c040b4 movhi r3,258 + 1020664: 18c8ff04 addi r3,r3,9212 + 1020668: 10800324 muli r2,r2,12 + 102066c: 10c5883a add r2,r2,r3 + 1020670: 10800017 ldw r2,0(r2) + 1020674: 1004c03a cmpne r2,r2,zero + 1020678: 1000131e bne r2,zero,10206c8 + { + alt_fd_list[i].dev = dev; + 102067c: e0bffd17 ldw r2,-12(fp) + 1020680: 00c040b4 movhi r3,258 + 1020684: 18c8ff04 addi r3,r3,9212 + 1020688: 10800324 muli r2,r2,12 + 102068c: 10c7883a add r3,r2,r3 + 1020690: e0bfff17 ldw r2,-4(fp) + 1020694: 18800015 stw r2,0(r3) + if (i > alt_max_fd) + 1020698: 008040b4 movhi r2,258 + 102069c: 108dd004 addi r2,r2,14144 + 10206a0: 10c00017 ldw r3,0(r2) + 10206a4: e0bffd17 ldw r2,-12(fp) + 10206a8: 1880040e bge r3,r2,10206bc + { + alt_max_fd = i; + 10206ac: 00c040b4 movhi r3,258 + 10206b0: 18cdd004 addi r3,r3,14144 + 10206b4: e0bffd17 ldw r2,-12(fp) + 10206b8: 18800015 stw r2,0(r3) + } + rc = i; + 10206bc: e0bffd17 ldw r2,-12(fp) + 10206c0: e0bffc15 stw r2,-16(fp) + goto alt_get_fd_exit; + 10206c4: 00000606 br 10206e0 + * indicates the highest file descriptor ever allocated. This is used to + * improve efficency when searching the file descriptor list, and + * therefore reduce contention on the alt_fd_list_lock semaphore. + */ + + for (i = 0; i < ALT_MAX_FD; i++) + 10206c8: e0bffd17 ldw r2,-12(fp) + 10206cc: 10800044 addi r2,r2,1 + 10206d0: e0bffd15 stw r2,-12(fp) + 10206d4: e0bffd17 ldw r2,-12(fp) + 10206d8: 10800810 cmplti r2,r2,32 + 10206dc: 103fdf1e bne r2,zero,102065c + /* + * Release the alt_fd_list_lock semaphore now that we are done with the + * file descriptor pool. + */ + + ALT_SEM_POST(alt_fd_list_lock); + 10206e0: 008040b4 movhi r2,258 + 10206e4: 10950c04 addi r2,r2,21552 + 10206e8: 11000017 ldw r4,0(r2) + 10206ec: 101b2100 call 101b210 + + return rc; + 10206f0: e0bffc17 ldw r2,-16(fp) +} + 10206f4: e037883a mov sp,fp + 10206f8: dfc00117 ldw ra,4(sp) + 10206fc: df000017 ldw fp,0(sp) + 1020700: dec00204 addi sp,sp,8 + 1020704: f800283a ret + +01020708 : + * alt_icache_flush() is called to flush the instruction cache for a memory + * region of length "len" bytes, starting at address "start". + */ + +void alt_icache_flush (void* start, alt_u32 len) +{ + 1020708: defffb04 addi sp,sp,-20 + 102070c: df000415 stw fp,16(sp) + 1020710: df000404 addi fp,sp,16 + 1020714: e13ffe15 stw r4,-8(fp) + 1020718: e17fff15 stw r5,-4(fp) + + /* + * This is the most we would ever need to flush. + */ + + if (len > NIOS2_ICACHE_SIZE) + 102071c: e0bfff17 ldw r2,-4(fp) + 1020720: 10880070 cmpltui r2,r2,8193 + 1020724: 1000021e bne r2,zero,1020730 + { + len = NIOS2_ICACHE_SIZE; + 1020728: 00880004 movi r2,8192 + 102072c: e0bfff15 stw r2,-4(fp) + } + + end = ((char*) start) + len; + 1020730: e0fffe17 ldw r3,-8(fp) + 1020734: e0bfff17 ldw r2,-4(fp) + 1020738: 1885883a add r2,r3,r2 + 102073c: e0bffc15 stw r2,-16(fp) + + for (i = start; i < end; i+= NIOS2_ICACHE_LINE_SIZE) + 1020740: e0bffe17 ldw r2,-8(fp) + 1020744: e0bffd15 stw r2,-12(fp) + 1020748: 00000506 br 1020760 + { + __asm__ volatile ("flushi %0" :: "r" (i)); + 102074c: e0bffd17 ldw r2,-12(fp) + 1020750: 1000603a flushi r2 + len = NIOS2_ICACHE_SIZE; + } + + end = ((char*) start) + len; + + for (i = start; i < end; i+= NIOS2_ICACHE_LINE_SIZE) + 1020754: e0bffd17 ldw r2,-12(fp) + 1020758: 10800804 addi r2,r2,32 + 102075c: e0bffd15 stw r2,-12(fp) + 1020760: e0fffd17 ldw r3,-12(fp) + 1020764: e0bffc17 ldw r2,-16(fp) + 1020768: 18bff836 bltu r3,r2,102074c + * For an unaligned flush request, we've got one more line left. + * Note that this is dependent on NIOS2_ICACHE_LINE_SIZE to be a + * multiple of 2 (which it always is). + */ + + if (((alt_u32) start) & (NIOS2_ICACHE_LINE_SIZE - 1)) + 102076c: e0bffe17 ldw r2,-8(fp) + 1020770: 108007cc andi r2,r2,31 + 1020774: 1005003a cmpeq r2,r2,zero + 1020778: 1000021e bne r2,zero,1020784 + { + __asm__ volatile ("flushi %0" :: "r" (i)); + 102077c: e0bffd17 ldw r2,-12(fp) + 1020780: 1000603a flushi r2 + /* + * Having flushed the cache, flush any stale instructions in the + * pipeline + */ + + __asm__ volatile ("flushp"); + 1020784: 0000203a flushp + +#endif /* NIOS2_ICACHE_SIZE > 0 */ +} + 1020788: e037883a mov sp,fp + 102078c: df000017 ldw fp,0(sp) + 1020790: dec00104 addi sp,sp,4 + 1020794: f800283a ret + +01020798 : + 1020798: 200b883a mov r5,r4 + 102079c: 000d883a mov r6,zero + 10207a0: 0009883a mov r4,zero + 10207a4: 000f883a mov r7,zero + 10207a8: 10207e41 jmpi 10207e4 <__register_exitproc> + +010207ac : + 10207ac: defffe04 addi sp,sp,-8 + 10207b0: 000b883a mov r5,zero + 10207b4: dc000015 stw r16,0(sp) + 10207b8: dfc00115 stw ra,4(sp) + 10207bc: 2021883a mov r16,r4 + 10207c0: 102091c0 call 102091c <__call_exitprocs> + 10207c4: 008040b4 movhi r2,258 + 10207c8: 108dc904 addi r2,r2,14116 + 10207cc: 11000017 ldw r4,0(r2) + 10207d0: 20800f17 ldw r2,60(r4) + 10207d4: 10000126 beq r2,zero,10207dc + 10207d8: 103ee83a callr r2 + 10207dc: 8009883a mov r4,r16 + 10207e0: 10144380 call 1014438 <_exit> + +010207e4 <__register_exitproc>: + 10207e4: defffa04 addi sp,sp,-24 + 10207e8: 008040b4 movhi r2,258 + 10207ec: 108dc904 addi r2,r2,14116 + 10207f0: dc000015 stw r16,0(sp) + 10207f4: 14000017 ldw r16,0(r2) + 10207f8: dd000415 stw r20,16(sp) + 10207fc: 2829883a mov r20,r5 + 1020800: 81405217 ldw r5,328(r16) + 1020804: dcc00315 stw r19,12(sp) + 1020808: dc800215 stw r18,8(sp) + 102080c: dc400115 stw r17,4(sp) + 1020810: dfc00515 stw ra,20(sp) + 1020814: 2023883a mov r17,r4 + 1020818: 3027883a mov r19,r6 + 102081c: 3825883a mov r18,r7 + 1020820: 28002526 beq r5,zero,10208b8 <__register_exitproc+0xd4> + 1020824: 29000117 ldw r4,4(r5) + 1020828: 008007c4 movi r2,31 + 102082c: 11002716 blt r2,r4,10208cc <__register_exitproc+0xe8> + 1020830: 8800101e bne r17,zero,1020874 <__register_exitproc+0x90> + 1020834: 2105883a add r2,r4,r4 + 1020838: 1085883a add r2,r2,r2 + 102083c: 20c00044 addi r3,r4,1 + 1020840: 1145883a add r2,r2,r5 + 1020844: 0009883a mov r4,zero + 1020848: 15000215 stw r20,8(r2) + 102084c: 28c00115 stw r3,4(r5) + 1020850: 2005883a mov r2,r4 + 1020854: dfc00517 ldw ra,20(sp) + 1020858: dd000417 ldw r20,16(sp) + 102085c: dcc00317 ldw r19,12(sp) + 1020860: dc800217 ldw r18,8(sp) + 1020864: dc400117 ldw r17,4(sp) + 1020868: dc000017 ldw r16,0(sp) + 102086c: dec00604 addi sp,sp,24 + 1020870: f800283a ret + 1020874: 29802204 addi r6,r5,136 + 1020878: 00800044 movi r2,1 + 102087c: 110e983a sll r7,r2,r4 + 1020880: 30c04017 ldw r3,256(r6) + 1020884: 2105883a add r2,r4,r4 + 1020888: 1085883a add r2,r2,r2 + 102088c: 1185883a add r2,r2,r6 + 1020890: 19c6b03a or r3,r3,r7 + 1020894: 14802015 stw r18,128(r2) + 1020898: 14c00015 stw r19,0(r2) + 102089c: 00800084 movi r2,2 + 10208a0: 30c04015 stw r3,256(r6) + 10208a4: 88bfe31e bne r17,r2,1020834 <__register_exitproc+0x50> + 10208a8: 30804117 ldw r2,260(r6) + 10208ac: 11c4b03a or r2,r2,r7 + 10208b0: 30804115 stw r2,260(r6) + 10208b4: 003fdf06 br 1020834 <__register_exitproc+0x50> + 10208b8: 008040f4 movhi r2,259 + 10208bc: 10b40604 addi r2,r2,-12264 + 10208c0: 100b883a mov r5,r2 + 10208c4: 80805215 stw r2,328(r16) + 10208c8: 003fd606 br 1020824 <__register_exitproc+0x40> + 10208cc: 00804074 movhi r2,257 + 10208d0: 10a86404 addi r2,r2,-24176 + 10208d4: 1000021e bne r2,zero,10208e0 <__register_exitproc+0xfc> + 10208d8: 013fffc4 movi r4,-1 + 10208dc: 003fdc06 br 1020850 <__register_exitproc+0x6c> + 10208e0: 01006404 movi r4,400 + 10208e4: 103ee83a callr r2 + 10208e8: 1007883a mov r3,r2 + 10208ec: 103ffa26 beq r2,zero,10208d8 <__register_exitproc+0xf4> + 10208f0: 80805217 ldw r2,328(r16) + 10208f4: 180b883a mov r5,r3 + 10208f8: 18000115 stw zero,4(r3) + 10208fc: 18800015 stw r2,0(r3) + 1020900: 80c05215 stw r3,328(r16) + 1020904: 18006215 stw zero,392(r3) + 1020908: 18006315 stw zero,396(r3) + 102090c: 0009883a mov r4,zero + 1020910: 883fc826 beq r17,zero,1020834 <__register_exitproc+0x50> + 1020914: 003fd706 br 1020874 <__register_exitproc+0x90> + +01020918 : + 1020918: f800283a ret + +0102091c <__call_exitprocs>: + 102091c: 008040b4 movhi r2,258 + 1020920: 108dc904 addi r2,r2,14116 + 1020924: 10800017 ldw r2,0(r2) + 1020928: defff304 addi sp,sp,-52 + 102092c: df000b15 stw fp,44(sp) + 1020930: d8800115 stw r2,4(sp) + 1020934: 00804074 movhi r2,257 + 1020938: 10a85f04 addi r2,r2,-24196 + 102093c: 1005003a cmpeq r2,r2,zero + 1020940: d8800215 stw r2,8(sp) + 1020944: d8800117 ldw r2,4(sp) + 1020948: dd400815 stw r21,32(sp) + 102094c: dd000715 stw r20,28(sp) + 1020950: 10805204 addi r2,r2,328 + 1020954: dfc00c15 stw ra,48(sp) + 1020958: ddc00a15 stw r23,40(sp) + 102095c: dd800915 stw r22,36(sp) + 1020960: dcc00615 stw r19,24(sp) + 1020964: dc800515 stw r18,20(sp) + 1020968: dc400415 stw r17,16(sp) + 102096c: dc000315 stw r16,12(sp) + 1020970: 282b883a mov r21,r5 + 1020974: 2039883a mov fp,r4 + 1020978: d8800015 stw r2,0(sp) + 102097c: 2829003a cmpeq r20,r5,zero + 1020980: d8800117 ldw r2,4(sp) + 1020984: 14405217 ldw r17,328(r2) + 1020988: 88001026 beq r17,zero,10209cc <__call_exitprocs+0xb0> + 102098c: ddc00017 ldw r23,0(sp) + 1020990: 88800117 ldw r2,4(r17) + 1020994: 8c802204 addi r18,r17,136 + 1020998: 143fffc4 addi r16,r2,-1 + 102099c: 80000916 blt r16,zero,10209c4 <__call_exitprocs+0xa8> + 10209a0: 05bfffc4 movi r22,-1 + 10209a4: a000151e bne r20,zero,10209fc <__call_exitprocs+0xe0> + 10209a8: 8409883a add r4,r16,r16 + 10209ac: 2105883a add r2,r4,r4 + 10209b0: 1485883a add r2,r2,r18 + 10209b4: 10c02017 ldw r3,128(r2) + 10209b8: a8c01126 beq r21,r3,1020a00 <__call_exitprocs+0xe4> + 10209bc: 843fffc4 addi r16,r16,-1 + 10209c0: 85bff81e bne r16,r22,10209a4 <__call_exitprocs+0x88> + 10209c4: d8800217 ldw r2,8(sp) + 10209c8: 10003126 beq r2,zero,1020a90 <__call_exitprocs+0x174> + 10209cc: dfc00c17 ldw ra,48(sp) + 10209d0: df000b17 ldw fp,44(sp) + 10209d4: ddc00a17 ldw r23,40(sp) + 10209d8: dd800917 ldw r22,36(sp) + 10209dc: dd400817 ldw r21,32(sp) + 10209e0: dd000717 ldw r20,28(sp) + 10209e4: dcc00617 ldw r19,24(sp) + 10209e8: dc800517 ldw r18,20(sp) + 10209ec: dc400417 ldw r17,16(sp) + 10209f0: dc000317 ldw r16,12(sp) + 10209f4: dec00d04 addi sp,sp,52 + 10209f8: f800283a ret + 10209fc: 8409883a add r4,r16,r16 + 1020a00: 88c00117 ldw r3,4(r17) + 1020a04: 2105883a add r2,r4,r4 + 1020a08: 1445883a add r2,r2,r17 + 1020a0c: 18ffffc4 addi r3,r3,-1 + 1020a10: 11800217 ldw r6,8(r2) + 1020a14: 1c001526 beq r3,r16,1020a6c <__call_exitprocs+0x150> + 1020a18: 10000215 stw zero,8(r2) + 1020a1c: 303fe726 beq r6,zero,10209bc <__call_exitprocs+0xa0> + 1020a20: 00c00044 movi r3,1 + 1020a24: 1c06983a sll r3,r3,r16 + 1020a28: 90804017 ldw r2,256(r18) + 1020a2c: 8cc00117 ldw r19,4(r17) + 1020a30: 1884703a and r2,r3,r2 + 1020a34: 10001426 beq r2,zero,1020a88 <__call_exitprocs+0x16c> + 1020a38: 90804117 ldw r2,260(r18) + 1020a3c: 1884703a and r2,r3,r2 + 1020a40: 10000c1e bne r2,zero,1020a74 <__call_exitprocs+0x158> + 1020a44: 2105883a add r2,r4,r4 + 1020a48: 1485883a add r2,r2,r18 + 1020a4c: 11400017 ldw r5,0(r2) + 1020a50: e009883a mov r4,fp + 1020a54: 303ee83a callr r6 + 1020a58: 88800117 ldw r2,4(r17) + 1020a5c: 98bfc81e bne r19,r2,1020980 <__call_exitprocs+0x64> + 1020a60: b8800017 ldw r2,0(r23) + 1020a64: 147fd526 beq r2,r17,10209bc <__call_exitprocs+0xa0> + 1020a68: 003fc506 br 1020980 <__call_exitprocs+0x64> + 1020a6c: 8c000115 stw r16,4(r17) + 1020a70: 003fea06 br 1020a1c <__call_exitprocs+0x100> + 1020a74: 2105883a add r2,r4,r4 + 1020a78: 1485883a add r2,r2,r18 + 1020a7c: 11000017 ldw r4,0(r2) + 1020a80: 303ee83a callr r6 + 1020a84: 003ff406 br 1020a58 <__call_exitprocs+0x13c> + 1020a88: 303ee83a callr r6 + 1020a8c: 003ff206 br 1020a58 <__call_exitprocs+0x13c> + 1020a90: 88800117 ldw r2,4(r17) + 1020a94: 1000081e bne r2,zero,1020ab8 <__call_exitprocs+0x19c> + 1020a98: 89000017 ldw r4,0(r17) + 1020a9c: 20000726 beq r4,zero,1020abc <__call_exitprocs+0x1a0> + 1020aa0: b9000015 stw r4,0(r23) + 1020aa4: 8809883a mov r4,r17 + 1020aa8: 100a17c0 call 100a17c + 1020aac: bc400017 ldw r17,0(r23) + 1020ab0: 883fb71e bne r17,zero,1020990 <__call_exitprocs+0x74> + 1020ab4: 003fc506 br 10209cc <__call_exitprocs+0xb0> + 1020ab8: 89000017 ldw r4,0(r17) + 1020abc: 882f883a mov r23,r17 + 1020ac0: 2023883a mov r17,r4 + 1020ac4: 883fb21e bne r17,zero,1020990 <__call_exitprocs+0x74> + 1020ac8: 003fc006 br 10209cc <__call_exitprocs+0xb0> + 1020acc: 0401ffff 0x401ffff + 1020ad0: 00010000 call 1000 + 1020ad4: 0201ffff 0x201ffff + 1020ad8: ffff0000 call ffff000 <__alt_data_end+0xdfff000> + 1020adc: 00006001 jmpi 600 + 1020ae0: 00020001 jmpi 2000 + 1020ae4: 00040003 ldbu zero,4096(zero) + 1020ae8: 00060005 stb zero,6144(zero) + 1020aec: 00080007 ldb zero,8192(zero) + 1020af0: 000a0009 0xa0009 + 1020af4: 000c000b ldhu zero,12288(zero) + 1020af8: 000e000d sth zero,14336(zero) + 1020afc: 0010000f ldh zero,16384(zero) + 1020b00: 00120011 0x120011 + 1020b04: 00140013 initda 20480(zero) + 1020b08: 00160015 stw zero,22528(zero) + 1020b0c: 00180017 ldw zero,24576(zero) + 1020b10: 001a0019 0x1a0019 + 1020b14: 001c001b flushda 28672(zero) + 1020b18: 001e001d stc zero,30720(zero) + 1020b1c: 0020001f ldl zero,-32768(zero) + 1020b20: 00220021 0x220021 + 1020b24: 00240023 ldbuio zero,-28672(zero) + 1020b28: 00260025 stbio zero,-26624(zero) + 1020b2c: 00280027 ldbio zero,-24576(zero) + 1020b30: 002a0029 0x2a0029 + 1020b34: 002c002b ldhuio zero,-20480(zero) + 1020b38: 002e002d sthio zero,-18432(zero) + 1020b3c: 883a002f ldhio zero,-6144(r17) + 1020b40: 01090bff 0x1090bff + 1020b44: 7f010002 0x7f010002 + 1020b48: 00000000 call 0 + 1020b4c: 01ffff00 call 1ffff0 + 1020b50: 00000002 0x2 + 1020b54: 01090bff 0x1090bff + 1020b58: 7f010002 0x7f010002 + 1020b5c: 00000000 call 0 + 1020b60: 01ffff00 call 1ffff0 + 1020b64: ff000002 0xff000002 + 1020b68: 000201ff 0x201ff + 1020b6c: 00000000 call 0 + 1020b70: 01090bff 0x1090bff + 1020b74: 01010004 movi r4,1024 + 1020b78: 00007f00 call 7f0 + 1020b7c: 00000000 call 0 + 1020b80: 01090bff 0x1090bff + 1020b84: 01010004 movi r4,1024 + 1020b88: 00007f00 call 7f0 + 1020b8c: 00000000 call 0 + 1020b90: 010d0bff 0x10d0bff + 1020b94: 01010006 br 1020f98 <_ZTS12MotorHandler+0x84> + 1020b98: 7f000200 call 7f00020 <__alt_data_end+0x5f00020> + 1020b9c: 00000000 call 0 + 1020ba0: 01ffff00 call 1ffff0 + 1020ba4: ff000002 0xff000002 + 1020ba8: 000201ff 0x201ff + 1020bac: 01ffff00 call 1ffff0 + 1020bb0: ff000002 0xff000002 + 1020bb4: 000201ff 0x201ff + 1020bb8: 01ffff00 call 1ffff0 + 1020bbc: 01000004 movi r4,0 + 1020bc0: 01ffff00 call 1ffff0 + 1020bc4: 01000004 movi r4,0 + 1020bc8: 01ffff00 call 1ffff0 + 1020bcc: 01000004 movi r4,0 + 1020bd0: 01ffff00 call 1ffff0 + 1020bd4: 01000008 cmpgei r4,zero,0 + 1020bd8: 03000200 call 300020 + 1020bdc: 00000000 call 0 + 1020be0: 010d0bff 0x10d0bff + 1020be4: 01000004 movi r4,0 + 1020be8: 00000101 jmpi 10 + 1020bec: 00000000 call 0 + 1020bf0: 010d0bff 0x10d0bff + 1020bf4: 01000004 movi r4,0 + 1020bf8: 00000101 jmpi 10 + 1020bfc: 00000000 call 0 + 1020c00: 010d0bff 0x10d0bff + 1020c04: 01000004 movi r4,0 + 1020c08: 00000101 jmpi 10 + 1020c0c: 00000000 call 0 + 1020c10: 01090bff 0x1090bff + 1020c14: 7f010002 0x7f010002 + ... + 1020c20: 01090bff 0x1090bff + 1020c24: 7f010002 0x7f010002 + ... + 1020c30: 010d0bff 0x10d0bff + 1020c34: 7f010002 0x7f010002 + 1020c38: 00000000 call 0 + 1020c3c: 01021450 cmplti r4,zero,2129 + 1020c40: 00000001 jmpi 0 + 1020c44: 010d0bff 0x10d0bff + 1020c48: 01030004 movi r4,3072 + 1020c4c: 7f000000 call 7f00000 <__alt_data_end+0x5f00000> + 1020c50: 0000007d 0x7d + 1020c54: 00000000 call 0 + 1020c58: 01110bff 0x1110bff + 1020c5c: 01030008 cmpgei r4,zero,3072 + 1020c60: 03000203 ldbu r12,8(zero) + 1020c64: 7f000000 call 7f00000 <__alt_data_end+0x5f00000> + 1020c68: 0000007d 0x7d + 1020c6c: 00000000 call 0 + 1020c70: 01110bff 0x1110bff + 1020c74: 01030008 cmpgei r4,zero,3072 + 1020c78: 03000203 ldbu r12,8(zero) + 1020c7c: 7f000000 call 7f00000 <__alt_data_end+0x5f00000> + 1020c80: 0000007d 0x7d + 1020c84: 00000000 call 0 + 1020c88: 01110bff 0x1110bff + 1020c8c: 01030008 cmpgei r4,zero,3072 + 1020c90: 03000203 ldbu r12,8(zero) + 1020c94: 7f000000 call 7f00000 <__alt_data_end+0x5f00000> + 1020c98: 0000007d 0x7d + 1020c9c: 00000000 call 0 + 1020ca0: 01110bff 0x1110bff + 1020ca4: 01030008 cmpgei r4,zero,3072 + 1020ca8: 03000203 ldbu r12,8(zero) + 1020cac: 7f000000 call 7f00000 <__alt_data_end+0x5f00000> + 1020cb0: 0000007d 0x7d + 1020cb4: 00000000 call 0 + 1020cb8: 01110bff 0x1110bff + 1020cbc: 01030008 cmpgei r4,zero,3072 + 1020cc0: 03000203 ldbu r12,8(zero) + 1020cc4: 7f000000 call 7f00000 <__alt_data_end+0x5f00000> + 1020cc8: 0000007d 0x7d + 1020ccc: 00000000 call 0 + 1020cd0: 01110bff 0x1110bff + 1020cd4: 01030008 cmpgei r4,zero,3072 + 1020cd8: 03000203 ldbu r12,8(zero) + 1020cdc: 7f000000 call 7f00000 <__alt_data_end+0x5f00000> + 1020ce0: 0000007d 0x7d + 1020ce4: 00000000 call 0 + 1020ce8: 01110bff 0x1110bff + 1020cec: 01030008 cmpgei r4,zero,3072 + 1020cf0: 03000203 ldbu r12,8(zero) + 1020cf4: 7f000000 call 7f00000 <__alt_data_end+0x5f00000> + 1020cf8: 0000007d 0x7d + 1020cfc: 00000000 call 0 + 1020d00: 01110bff 0x1110bff + 1020d04: 01030008 cmpgei r4,zero,3072 + 1020d08: 03000203 ldbu r12,8(zero) + 1020d0c: 7f000000 call 7f00000 <__alt_data_end+0x5f00000> + 1020d10: 0000007d 0x7d + 1020d14: 00000000 call 0 + 1020d18: 01110bff 0x1110bff + 1020d1c: 01030008 cmpgei r4,zero,3072 + 1020d20: 03000203 ldbu r12,8(zero) + 1020d24: 7f000000 call 7f00000 <__alt_data_end+0x5f00000> + 1020d28: 0000007d 0x7d + 1020d2c: 00000000 call 0 + 1020d30: 01090bff 0x1090bff + 1020d34: 7f030002 0x7f030002 + 1020d38: 007d0000 call 7d000 + 1020d3c: 00000000 call 0 + 1020d40: 01090bff 0x1090bff + 1020d44: 7f030002 0x7f030002 + 1020d48: 007d0000 call 7d000 + 1020d4c: 00000000 call 0 + 1020d50: 01090bff 0x1090bff + 1020d54: 7f030002 0x7f030002 + 1020d58: 007d0000 call 7d000 + 1020d5c: 00000000 call 0 + 1020d60: 01090bff 0x1090bff + 1020d64: 7f030002 0x7f030002 + 1020d68: 007d0000 call 7d000 + 1020d6c: 00000000 call 0 + 1020d70: 01090bff 0x1090bff + 1020d74: 7f030002 0x7f030002 + 1020d78: 007d0000 call 7d000 + 1020d7c: 00000000 call 0 + 1020d80: 01090bff 0x1090bff + 1020d84: 7f030002 0x7f030002 + 1020d88: 007d0000 call 7d000 + 1020d8c: 01ffff00 call 1ffff0 + 1020d90: ff000002 0xff000002 + 1020d94: 000201ff 0x201ff + 1020d98: 01ffff00 call 1ffff0 + 1020d9c: ff000002 0xff000002 + 1020da0: 000201ff 0x201ff + 1020da4: 00000000 call 0 + 1020da8: 01090bff 0x1090bff + 1020dac: 7f030002 0x7f030002 + 1020db0: 007d0000 call 7d000 + 1020db4: 00000000 call 0 + 1020db8: 01090bff 0x1090bff + 1020dbc: 7f030002 0x7f030002 + 1020dc0: 007d0000 call 7d000 + 1020dc4: 00000000 call 0 + 1020dc8: 01090bff 0x1090bff + 1020dcc: 7f030002 0x7f030002 + 1020dd0: 007d0000 call 7d000 + 1020dd4: 00000000 call 0 + 1020dd8: 01090bff 0x1090bff + 1020ddc: 7f030002 0x7f030002 + 1020de0: 007d0000 call 7d000 + 1020de4: 00000000 call 0 + 1020de8: 01090bff 0x1090bff + 1020dec: 7f030002 0x7f030002 + 1020df0: 007d0000 call 7d000 + 1020df4: 00000000 call 0 + 1020df8: 01000a2c andhi r4,zero,40 + 1020dfc: 01020918 cmpnei r4,zero,2084 diff --git a/MCTEST/DE0-nano-HD/Software/MCTest/Makefile b/MCTEST/DE0-nano-HD/Software/MCTest/Makefile new file mode 100644 index 00000000..f9560ce1 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/MCTest/Makefile @@ -0,0 +1,1087 @@ +#------------------------------------------------------------------------------ +# VARIABLES APPENDED TO BY INCLUDED MAKEFILE FRAGMENTS +#------------------------------------------------------------------------------ + +# List of include directories for -I compiler option (-I added when used). +# Includes the BSP. +ALT_INCLUDE_DIRS := + +# List of library directories for -L linker option (-L added when used). +# Includes the BSP. +ALT_LIBRARY_DIRS := + +# List of library names for -l linker option (-l added when used). +# Includes the BSP. +ALT_LIBRARY_NAMES := + +# List of library names for -msys-lib linker option (-msys-lib added when used). +# These are libraries that might be located in the BSP and depend on the BSP +# library, or vice versa +ALT_BSP_DEP_LIBRARY_NAMES := + +# List of dependencies for the linker. This is usually the full pathname +# of each library (*.a) file. +# Includes the BSP. +ALT_LDDEPS := + +# List of root library directories that support running make to build them. +# Includes the BSP and any ALT libraries. +MAKEABLE_LIBRARY_ROOT_DIRS := + +# Generic flags passed to the compiler for different types of input files. +ALT_CFLAGS := +ALT_CXXFLAGS := +ALT_CPPFLAGS := +ALT_ASFLAGS := +ALT_LDFLAGS := + + +#------------------------------------------------------------------------------ +# The adjust-path macro +# +# If COMSPEC/ComSpec is defined, Make is launched from Windows through +# Cygwin. The adjust-path macro converts absolute windows paths into +# unix style paths (Example: c:/dir -> /c/dir). This will ensture +# paths are readable by GNU Make. +# +# If COMSPEC/ComSpec is not defined, Make is launched from linux, and no +# adjustment is necessary +# +#------------------------------------------------------------------------------ + +ifndef COMSPEC +ifdef ComSpec +COMSPEC = $(ComSpec) +endif # ComSpec +endif # COMSPEC + +ifdef COMSPEC # if Windows OS + +ifeq ($(MAKE_VERSION),3.81) +# +# adjust-path/adjust-path-mixed for Mingw Gnu Make on Windows +# +# Example Usage: +# $(call adjust-path,c:/aaa/bbb) => /c/aaa/bbb +# $(call adjust-path-mixed,/c/aaa/bbb) => c:/aaa/bbb +# $(call adjust-path-mixed,/cygdrive/c/aaa/bbb) => c:/aaa/bbb +# + +# +# adjust-path +# - converts back slash characters into forward slashes +# - if input arg ($1) is an empty string then return the empty string +# - if input arg ($1) does not contain the string ":/", then return input arg +# - using sed, convert mixed path [c:/...] into mingw path [/c/...] +define adjust-path +$(strip \ +$(if $1,\ +$(if $(findstring :/,$(subst \,/,$1)),\ +$(shell echo $(subst \,/,$1) | sed -e 's,^\([a-zA-Z]\):/,/\1/,'),\ +$(subst \,/,$1)))) +endef + +# +# adjust-path-mixed +# - converts back slash characters into forward slashes +# - if input arg ($1) is an empty string then return the empty string +# - if input arg ($1) does not begin with a forward slash '/' char, then +# return input arg +# - using sed, convert mingw path [/c/...] or cygwin path [/c/cygdrive/...] +# into a mixed path [c:/...] +define adjust-path-mixed +$(strip \ +$(if $1,\ +$(if $(findstring $(subst \,/,$1),$(patsubst /%,%,$(subst \,/,$1))),\ +$(subst \,/,$1),\ +$(shell echo $(subst \,/,$1) | sed -e 's,^/cygdrive/\([a-zA-Z]\)/,\1:/,' -e 's,^/\([a-zA-Z]\)/,\1:/,')))) +endef + +else # MAKE_VERSION != 3.81 (MAKE_VERSION == 3.80 or MAKE_VERSION == 3.79) +# +# adjust-path for Cygwin Gnu Make +# $(call adjust-path,c:/aaa/bbb) = /cygdrive/c/aaa/bbb +# $(call adjust-path-mixed,/cygdrive/c/aaa/bbb) = c:/aaa/bbb +# +adjust-path = $(if $1,$(shell cygpath -u "$1"),) +adjust-path-mixed = $(if $1,$(shell cygpath -m "$1"),) +endif + +else # !COMSPEC + +adjust-path = $1 +adjust-path-mixed = $1 + +endif # COMSPEC + + +#vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv +# GENERATED SETTINGS START v +#vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv + +#START GENERATED +ACTIVE_BUILD_CONFIG := default +BUILD_CONFIGS := default + +# The following TYPE comment allows tools to identify the 'type' of target this +# makefile is associated with. +# TYPE: APP_MAKEFILE + +# This following VERSION comment indicates the version of the tool used to +# generate this makefile. A makefile variable is provided for VERSION as well. +# ACDS_VERSION: 12.1sp1 +ACDS_VERSION := 12.1sp1 + +# This following BUILD_NUMBER comment indicates the build number of the tool +# used to generate this makefile. +# BUILD_NUMBER: 243 + +# Define path to the application ELF. +# It may be used by the makefile fragments so is defined before including them. +# +ELF := MCTest.elf + +# Paths to C, C++, and assembly source files. +C_SRCS := +CXX_SRCS += MotorHandler.cpp +CXX_SRCS += main.cpp +ASM_SRCS := + + +# Path to root of object file tree. +OBJ_ROOT_DIR := obj + +# Options to control objdump. +CREATE_OBJDUMP := 1 +OBJDUMP_INCLUDE_SOURCE := 1 +OBJDUMP_FULL_CONTENTS := 0 + +# Options to enable/disable optional files. +CREATE_ELF_DERIVED_FILES := 0 +CREATE_LINKER_MAP := 1 + +# Common arguments for ALT_CFLAGSs +APP_CFLAGS_DEFINED_SYMBOLS := +APP_CFLAGS_UNDEFINED_SYMBOLS := +APP_CFLAGS_OPTIMIZATION := -O0 +APP_CFLAGS_DEBUG_LEVEL := -g +APP_CFLAGS_WARNINGS := -Wall +APP_CFLAGS_USER_FLAGS := + +APP_ASFLAGS_USER := +APP_LDFLAGS_USER := + +# Linker options that have default values assigned later if not +# assigned here. +LINKER_SCRIPT := +CRT0 := +SYS_LIB := + +# Define path to the root of the BSP. +BSP_ROOT_DIR := ../MCTest_bsp/ + +# List of application specific include directories, library directories and library names +APP_INCLUDE_DIRS := +APP_LIBRARY_DIRS := +APP_LIBRARY_NAMES := + +# Pre- and post- processor settings. +BUILD_PRE_PROCESS := +BUILD_POST_PROCESS := + +QUARTUS_PROJECT_DIR := ../../ + + +#END GENERATED + +#^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +# GENERATED SETTINGS END ^ +#^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + + +#------------------------------------------------------------------------------ +# DEFAULT TARGET +#------------------------------------------------------------------------------ + +# Define the variable used to echo output if not already defined. +ifeq ($(ECHO),) +ECHO := echo +endif + +# Put "all" rule before included makefile fragments because they may +# define rules and we don't want one of those to become the default rule. +.PHONY : all + +all: + @$(ECHO) [$(APP_NAME) build complete] + +all : build_pre_process libs app build_post_process + + +#------------------------------------------------------------------------------ +# VARIABLES DEPENDENT ON GENERATED CONTENT +#------------------------------------------------------------------------------ + +# Define object file directory per build configuration +CONFIG_OBJ_DIR := $(OBJ_ROOT_DIR)/$(ACTIVE_BUILD_CONFIG) + +ifeq ($(BSP_ROOT_DIR),) +$(error Edit Makefile and provide a value for BSP_ROOT_DIR) +endif + +ifeq ($(wildcard $(BSP_ROOT_DIR)),) +$(error BSP directory does not exist: $(BSP_ROOT_DIR)) +endif + +# Define absolute path to the root of the BSP. +ABS_BSP_ROOT_DIR := $(call adjust-path-mixed,$(shell cd "$(BSP_ROOT_DIR)"; pwd)) + +# Include makefile fragments. Define variable ALT_LIBRARY_ROOT_DIR before +# including each makefile fragment so that it knows the path to itself. +BSP_INCLUDE_FILE := $(BSP_ROOT_DIR)/public.mk +ALT_LIBRARY_ROOT_DIR := $(BSP_ROOT_DIR) +include $(BSP_INCLUDE_FILE) +# C2H will need this to touch the BSP public.mk and avoid the sopc file +# out-of-date error during a BSP make +ABS_BSP_INCLUDE_FILE := $(ABS_BSP_ROOT_DIR)/public.mk + + +ifneq ($(WARNING.SMALL_STACK_SIZE),) +# This WARNING is here to protect you from unknowingly using a very small stack +# If the warning is set, increase your stack size or enable the BSP small stack +# setting to eliminate the warning +$(warning WARNING: $(WARNING.SMALL_STACK_SIZE)) +endif + + +# If the BSP public.mk indicates that ALT_SIM_OPTIMIZE is set, rename the ELF +# by prefixing it with RUN_ON_HDL_SIMULATOR_ONLY_. +ifneq ($(filter -DALT_SIM_OPTIMIZE,$(ALT_CPPFLAGS)),) +ELF := RUN_ON_HDL_SIMULATOR_ONLY_$(ELF) +endif + +# If the BSP public.mk indicates that ALT_PROVIDE_GMON is set, add option to +# download_elf target +ifneq ($(filter -DALT_PROVIDE_GMON,$(ALT_CPPFLAGS)),) +GMON_OUT_FILENAME := gmon.out +WRITE_GMON_OPTION := --write-gmon $(GMON_OUT_FILENAME) +endif + +# Name of ELF application. +APP_NAME := $(basename $(ELF)) + +# Set to defaults if variables not already defined in settings. +ifeq ($(LINKER_SCRIPT),) +LINKER_SCRIPT := $(BSP_LINKER_SCRIPT) +endif +ifeq ($(CRT0),) +CRT0 := $(BSP_CRT0) +endif +ifeq ($(SYS_LIB),) +SYS_LIB := $(BSP_SYS_LIB) +endif + +OBJDUMP_NAME := $(APP_NAME).objdump +OBJDUMP_FLAGS := --disassemble --syms --all-header +ifeq ($(OBJDUMP_INCLUDE_SOURCE),1) +OBJDUMP_FLAGS += --source +endif +ifeq ($(OBJDUMP_FULL_CONTENTS),1) +OBJDUMP_FLAGS += --full-contents +endif + +# Create list of linker dependencies (*.a files). +APP_LDDEPS := $(ALT_LDDEPS) $(LDDEPS) + +# Take lists and add required prefixes. +APP_INC_DIRS := $(addprefix -I, $(ALT_INCLUDE_DIRS) $(APP_INCLUDE_DIRS) $(INC_DIRS)) +ASM_INC_PREFIX := -Wa,-I +APP_ASM_INC_DIRS := $(addprefix $(ASM_INC_PREFIX), $(ALT_INCLUDE_DIRS) $(APP_INCLUDE_DIRS) $(INC_DIRS)) +APP_LIB_DIRS := $(addprefix -L, $(ALT_LIBRARY_DIRS) $(APP_LIBRARY_DIRS) $(LIB_DIRS)) +APP_LIBS := $(addprefix -l, $(ALT_LIBRARY_NAMES) $(APP_LIBRARY_NAMES) $(LIBS)) + +ifneq ($(AVOID_NIOS2_GCC3_OPTIONS),) + +# +# Avoid Nios II GCC 3.X options. +# + +# Detect if small newlib C library is requested. +# If yes, remove the -msmallc option because it is +# now handled by other means. +ifneq ($(filter -msmallc,$(ALT_LDFLAGS)),) + ALT_LDFLAGS := $(filter-out -msmallc,$(ALT_LDFLAGS)) + ALT_C_LIBRARY := smallc +else + ALT_C_LIBRARY := c +endif + +# Put each BSP dependent library in a group to avoid circular dependencies. +APP_BSP_DEP_LIBS := $(foreach l,$(ALT_BSP_DEP_LIBRARY_NAMES),-Wl,--start-group -l$(ALT_C_LIBRARY) -lgcc -l$(l) -Wl,--end-group) + +else # !AVOID_NIOS2_GCC3_OPTIONS + +# +# Use Nios II GCC 3.X options. +# +APP_BSP_DEP_LIBS := $(addprefix -msys-lib=, $(ALT_BSP_DEP_LIBRARY_NAMES)) + +endif # !AVOID_NIOS2_GCC3_OPTIONS + +# Arguments for the C preprocessor, C/C++ compiler, assembler, and linker. +APP_CFLAGS := $(APP_CFLAGS_DEFINED_SYMBOLS) \ + $(APP_CFLAGS_UNDEFINED_SYMBOLS) \ + $(APP_CFLAGS_OPTIMIZATION) \ + $(APP_CFLAGS_DEBUG_LEVEL) \ + $(APP_CFLAGS_WARNINGS) \ + $(APP_CFLAGS_USER_FLAGS) \ + $(ALT_CFLAGS) \ + $(CFLAGS) + +# Arguments only for the C++ compiler. +APP_CXXFLAGS := $(ALT_CXXFLAGS) $(CXXFLAGS) + +# Arguments only for the C preprocessor. +# Prefix each include directory with -I. +APP_CPPFLAGS := $(APP_INC_DIRS) \ + $(ALT_CPPFLAGS) \ + $(CPPFLAGS) + +# Arguments only for the assembler. +APP_ASFLAGS := $(APP_ASM_INC_DIRS) \ + $(ALT_ASFLAGS) \ + $(APP_ASFLAGS_USER) \ + $(ASFLAGS) + +# Arguments only for the linker. +APP_LDFLAGS := $(APP_LDFLAGS_USER) + +ifneq ($(LINKER_SCRIPT),) +APP_LDFLAGS += -T'$(LINKER_SCRIPT)' +endif + +ifneq ($(AVOID_NIOS2_GCC3_OPTIONS),) + +# Avoid Nios II GCC 3.x options. +ifneq ($(CRT0),) +APP_LDFLAGS += $(CRT0) +endif + +# The equivalent of the -msys-lib option is provided +# by the GROUP() command in the linker script. +# Note this means the SYS_LIB variable is now ignored. + +else # !AVOID_NIOS2_GCC3_OPTIONS + +# Use Nios II GCC 3.x options. +ifneq ($(CRT0),) +APP_LDFLAGS += -msys-crt0='$(CRT0)' +endif +ifneq ($(SYS_LIB),) +APP_LDFLAGS += -msys-lib=$(SYS_LIB) +endif + +endif # !AVOID_NIOS2_GCC3_OPTIONS + +APP_LDFLAGS += \ + $(APP_LIB_DIRS) \ + $(ALT_LDFLAGS) \ + $(LDFLAGS) + +LINKER_MAP_NAME := $(APP_NAME).map +ifeq ($(CREATE_LINKER_MAP), 1) +APP_LDFLAGS += -Wl,-Map=$(LINKER_MAP_NAME) +endif + +# QUARTUS_PROJECT_DIR and SOPC_NAME need to be defined if you want the +# mem_init_install target of the mem_init.mk (located in the associated BSP) +# to know how to copy memory initialization files (e.g. .dat, .hex) into +# directories required for Quartus compilation or RTL simulation. + +# Defining QUARTUS_PROJECT_DIR causes mem_init_install to copy memory +# initialization files into your Quartus project directory. This is required +# to provide the initial memory contents of FPGA memories that can be +# initialized by the programming file (.sof) or Hardcopy ROMs. It is also used +# for VHDL simulation of on-chip memories. + +# Defining SOPC_NAME causes the mem_init_install target to copy memory +# initialization files into your RTL simulation directory. This is required +# to provide the initial memory contents of all memories that can be +# initialized by RTL simulation. This variable should be set to the same name +# as your SOPC Builder system name. For example, if you have a system called +# "foo.sopc", this variable should be set to "foo". + +# If SOPC_NAME is not set and QUARTUS_PROJECT_DIR is set, then derive SOPC_NAME. +ifeq ($(SOPC_NAME),) +ifneq ($(QUARTUS_PROJECT_DIR),) +SOPC_NAME := $(basename $(notdir $(wildcard $(QUARTUS_PROJECT_DIR)/*.sopcinfo))) +endif +endif + +# Defining JDI_FILE is required to specify the JTAG Debug Information File +# path. This file is generated by Quartus, and is needed along with the +# .sopcinfo file to resolve processor instance ID's from names in a multi-CPU +# systems. For multi-CPU systems, the processor instance ID is used to select +# from multiple CPU's during ELF download. + +# Both JDI_FILE and SOPCINFO_FILE are provided by the BSP if they found during +# BSP creation. If JDI_FILE is not set and QUARTUS_PROJECT_DIR is set, then +# derive JDI_FILE. We do not attempt to derive SOPCINFO_FILE since there may be +# multiple .sopcinfo files in a Quartus project. +ifeq ($(JDI_FILE),) +ifneq ($(QUARTUS_PROJECT_DIR),) +JDI_FILE := $(wildcard $(QUARTUS_PROJECT_DIR)/*.jdi) +endif +endif + +# Path to root runtime directory used for hdl simulation +RUNTIME_ROOT_DIR := $(CONFIG_OBJ_DIR)/runtime + + + +#------------------------------------------------------------------------------ +# MAKEFILE INCLUDES DEPENDENT ON GENERATED CONTENT +#------------------------------------------------------------------------------ +# mem_init.mk is a generated makefile fragment. This file defines all targets +# used to generate HDL initialization simulation files and pre-initialized +# onchip memory files. +MEM_INIT_FILE := $(BSP_ROOT_DIR)/mem_init.mk +include $(MEM_INIT_FILE) + +# Create list of object files to be built using the list of source files. +# The source file hierarchy is preserved in the object tree. +# The supported file extensions are: +# +# .c - for C files +# .cxx .cc .cpp - for C++ files +# .S .s - for assembler files +# +# Handle source files specified by --src-dir & --src-rdir differently, to +# save some processing time in calling the adjust-path macro. + +OBJ_LIST_C := $(patsubst %.c,%.o,$(filter %.c,$(C_SRCS))) +OBJ_LIST_CPP := $(patsubst %.cpp,%.o,$(filter %.cpp,$(CXX_SRCS))) +OBJ_LIST_CXX := $(patsubst %.cxx,%.o,$(filter %.cxx,$(CXX_SRCS))) +OBJ_LIST_CC := $(patsubst %.cc,%.o,$(filter %.cc,$(CXX_SRCS))) +OBJ_LIST_S := $(patsubst %.S,%.o,$(filter %.S,$(ASM_SRCS))) +OBJ_LIST_SS := $(patsubst %.s,%.o,$(filter %.s,$(ASM_SRCS))) + +OBJ_LIST := $(sort $(OBJ_LIST_C) $(OBJ_LIST_CPP) $(OBJ_LIST_CXX) \ + $(OBJ_LIST_CC) $(OBJ_LIST_S) $(OBJ_LIST_SS)) + +SDIR_OBJ_LIST_C := $(patsubst %.c,%.o,$(filter %.c,$(SDIR_C_SRCS))) +SDIR_OBJ_LIST_CPP := $(patsubst %.cpp,%.o,$(filter %.cpp,$(SDIR_CXX_SRCS))) +SDIR_OBJ_LIST_CXX := $(patsubst %.cxx,%.o,$(filter %.cxx,$(SDIR_CXX_SRCS))) +SDIR_OBJ_LIST_CC := $(patsubst %.cc,%.o,$(filter %.cc,$(SDIR_CXX_SRCS))) +SDIR_OBJ_LIST_S := $(patsubst %.S,%.o,$(filter %.S,$(SDIR_ASM_SRCS))) +SDIR_OBJ_LIST_SS := $(patsubst %.s,%.o,$(filter %.s,$(SDIR_ASM_SRCS))) + +SDIR_OBJ_LIST := $(sort $(SDIR_OBJ_LIST_C) $(SDIR_OBJ_LIST_CPP) \ + $(SDIR_OBJ_LIST_CXX) $(SDIR_OBJ_LIST_CC) $(SDIR_OBJ_LIST_S) \ + $(SDIR_OBJ_LIST_SS)) + +# Relative-pathed objects that being with "../" are handled differently. +# +# Regular objects are created as +# $(CONFIG_OBJ_DIR)//.o +# where the path structure is maintained under the obj directory. This +# applies for both absolute and relative paths; in the absolute path +# case this means the entire source path will be recreated under the obj +# directory. This is done to allow two source files with the same name +# to be included as part of the project. +# +# Note: On Cygwin, the path recreated under the obj directory will be +# the cygpath -u output path. +# +# Relative-path objects that begin with "../" cause problems under this +# scheme, as $(CONFIG_OBJ_DIR)/..// can potentially put the object +# files anywhere in the system, creating clutter and polluting the source tree. +# As such, their paths are flattened - the object file created will be +# $(CONFIG_OBJ_DIR)/.o. Due to this, two files specified with +# "../" in the beginning cannot have the same name in the project. VPATH +# will be set for these sources to allow make to relocate the source file +# via %.o rules. +# +# The following lines separate the object list into the flatten and regular +# lists, and then handles them as appropriate. + +FLATTEN_OBJ_LIST := $(filter ../%,$(OBJ_LIST)) +FLATTEN_APP_OBJS := $(addprefix $(CONFIG_OBJ_DIR)/,$(notdir $(FLATTEN_OBJ_LIST))) + +REGULAR_OBJ_LIST := $(filter-out $(FLATTEN_OBJ_LIST),$(OBJ_LIST)) +REGULAR_OBJ_LIST_C := $(filter $(OBJ_LIST_C),$(REGULAR_OBJ_LIST)) +REGULAR_OBJ_LIST_CPP := $(filter $(OBJ_LIST_CPP),$(REGULAR_OBJ_LIST)) +REGULAR_OBJ_LIST_CXX := $(filter $(OBJ_LIST_CXX),$(REGULAR_OBJ_LIST)) +REGULAR_OBJ_LIST_CC := $(filter $(OBJ_LIST_CC),$(REGULAR_OBJ_LIST)) +REGULAR_OBJ_LIST_S := $(filter $(OBJ_LIST_S),$(REGULAR_OBJ_LIST)) +REGULAR_OBJ_LIST_SS := $(filter $(OBJ_LIST_SS),$(REGULAR_OBJ_LIST)) + +FLATTEN_SDIR_OBJ_LIST := $(filter ../%,$(SDIR_OBJ_LIST)) +FLATTEN_SDIR_APP_OBJS := $(addprefix $(CONFIG_OBJ_DIR)/,$(notdir $(FLATTEN_SDIR_OBJ_LIST))) + +REGULAR_SDIR_OBJ_LIST := $(filter-out $(FLATTEN_SDIR_OBJ_LIST),$(SDIR_OBJ_LIST)) +REGULAR_SDIR_OBJ_LIST_C := $(filter $(SDIR_OBJ_LIST_C),$(REGULAR_SDIR_OBJ_LIST)) +REGULAR_SDIR_OBJ_LIST_CPP := $(filter $(SDIR_OBJ_LIST_CPP),$(REGULAR_SDIR_OBJ_LIST)) +REGULAR_SDIR_OBJ_LIST_CXX := $(filter $(SDIR_OBJ_LIST_CXX),$(REGULAR_SDIR_OBJ_LIST)) +REGULAR_SDIR_OBJ_LIST_CC := $(filter $(SDIR_OBJ_LIST_CC),$(REGULAR_SDIR_OBJ_LIST)) +REGULAR_SDIR_OBJ_LIST_S := $(filter $(SDIR_OBJ_LIST_S),$(REGULAR_SDIR_OBJ_LIST)) +REGULAR_SDIR_OBJ_LIST_SS := $(filter $(SDIR_OBJ_LIST_SS),$(REGULAR_SDIR_OBJ_LIST)) + +VPATH := $(sort $(dir $(FLATTEN_OBJ_LIST)) $(dir $(FLATTEN_SDIR_OBJ_LIST))) + +APP_OBJS_C := $(addprefix $(CONFIG_OBJ_DIR)/,\ + $(REGULAR_SDIR_OBJ_LIST_C) \ + $(foreach s,$(REGULAR_OBJ_LIST_C),$(call adjust-path,$s))) + +APP_OBJS_CPP := $(addprefix $(CONFIG_OBJ_DIR)/,\ + $(REGULAR_SDIR_OBJ_LIST_CPP) \ + $(foreach s,$(REGULAR_OBJ_LIST_CPP),$(call adjust-path,$s))) + +APP_OBJS_CXX := $(addprefix $(CONFIG_OBJ_DIR)/,\ + $(REGULAR_SDIR_OBJ_LIST_CXX) \ + $(foreach s,$(REGULAR_OBJ_LIST_CXX),$(call adjust-path,$s))) + +APP_OBJS_CC := $(addprefix $(CONFIG_OBJ_DIR)/,\ + $(REGULAR_SDIR_OBJ_LIST_CC) \ + $(foreach s,$(REGULAR_OBJ_LIST_CC),$(call adjust-path,$s))) + +APP_OBJS_S := $(addprefix $(CONFIG_OBJ_DIR)/,\ + $(REGULAR_SDIR_OBJ_LIST_S) \ + $(foreach s,$(REGULAR_OBJ_LIST_S),$(call adjust-path,$s))) + +APP_OBJS_SS := $(addprefix $(CONFIG_OBJ_DIR)/,\ + $(REGULAR_SDIR_OBJ_LIST_SS) \ + $(foreach s,$(REGULAR_OBJ_LIST_SS),$(call adjust-path,$s))) + +APP_OBJS := $(APP_OBJS_C) $(APP_OBJS_CPP) $(APP_OBJS_CXX) $(APP_OBJS_CC) \ + $(APP_OBJS_S) $(APP_OBJS_SS) \ + $(FLATTEN_APP_OBJS) $(FLATTEN_SDIR_APP_OBJS) + +# Add any extra user-provided object files. +APP_OBJS += $(OBJS) + +# Create list of dependancy files for each object file. +APP_DEPS := $(APP_OBJS:.o=.d) + +# Patch the Elf file with system specific information + +# Patch the Elf with the name of the sopc system +ifneq ($(SOPC_NAME),) +ELF_PATCH_FLAG += --sopc_system_name $(SOPC_NAME) +endif + +# Patch the Elf with the absolute path to the Quartus Project Directory +ifneq ($(QUARTUS_PROJECT_DIR),) +ABS_QUARTUS_PROJECT_DIR := $(call adjust-path-mixed,$(shell cd "$(QUARTUS_PROJECT_DIR)"; pwd)) +ELF_PATCH_FLAG += --quartus_project_dir "$(ABS_QUARTUS_PROJECT_DIR)" +endif + +# Patch the Elf and download args with the JDI_FILE if specified +ifneq ($(wildcard $(JDI_FILE)),) +ELF_PATCH_FLAG += --jdi $(JDI_FILE) +DOWNLOAD_JDI_FLAG := --jdi $(JDI_FILE) +endif + +# Patch the Elf with the SOPCINFO_FILE if specified +ifneq ($(wildcard $(SOPCINFO_FILE)),) +ELF_PATCH_FLAG += --sopcinfo $(SOPCINFO_FILE) +endif + +# Use the DOWNLOAD_CABLE variable to specify which JTAG cable to use. +# This is not needed if you only have one cable. +ifneq ($(DOWNLOAD_CABLE),) +DOWNLOAD_CABLE_FLAG := --cable '$(DOWNLOAD_CABLE)' +endif + + +#------------------------------------------------------------------------------ +# BUILD PRE/POST PROCESS +#------------------------------------------------------------------------------ +build_pre_process : + $(BUILD_PRE_PROCESS) + +build_post_process : + $(BUILD_POST_PROCESS) + +.PHONY: build_pre_process build_post_process + + +#------------------------------------------------------------------------------ +# TOOLS +#------------------------------------------------------------------------------ + +# +# Set tool default variables if not already defined. +# If these are defined, they would typically be defined in an +# included makefile fragment. +# +ifeq ($(DEFAULT_CROSS_COMPILE),) +DEFAULT_CROSS_COMPILE := nios2-elf- +endif + +ifeq ($(DEFAULT_STACK_REPORT),) +DEFAULT_STACKREPORT := nios2-stackreport +endif + +ifeq ($(DEFAULT_DOWNLOAD),) +DEFAULT_DOWNLOAD := nios2-download +endif + +ifeq ($(DEFAULT_FLASHPROG),) +DEFAULT_FLASHPROG := nios2-flash-programmer +endif + +ifeq ($(DEFAULT_ELFPATCH),) +DEFAULT_ELFPATCH := nios2-elf-insert +endif + +ifeq ($(DEFAULT_RM),) +DEFAULT_RM := rm -f +endif + +ifeq ($(DEFAULT_CP),) +DEFAULT_CP := cp -f +endif + +ifeq ($(DEFAULT_MKDIR),) +DEFAULT_MKDIR := mkdir -p +endif + +# +# Set tool variables to defaults if not already defined. +# If these are defined, they would typically be defined by a +# setting in the generated portion of this makefile. +# +ifeq ($(CROSS_COMPILE),) +CROSS_COMPILE := $(DEFAULT_CROSS_COMPILE) +endif + +ifeq ($(origin CC),default) +CC := $(CROSS_COMPILE)gcc -xc +endif + +ifeq ($(origin CXX),default) +CXX := $(CROSS_COMPILE)gcc -xc++ +endif + +ifeq ($(origin AS),default) +AS := $(CROSS_COMPILE)gcc +endif + +ifeq ($(origin AR),default) +AR := $(CROSS_COMPILE)ar +endif + +ifeq ($(origin LD),default) +LD := $(CROSS_COMPILE)g++ +endif + +ifeq ($(origin NM),default) +NM := $(CROSS_COMPILE)nm +endif + +ifeq ($(origin RM),default) +RM := $(DEFAULT_RM) +endif + +ifeq ($(origin CP),default) +CP := $(DEFAULT_CP) +endif + +ifeq ($(OBJDUMP),) +OBJDUMP := $(CROSS_COMPILE)objdump +endif + +ifeq ($(OBJCOPY),) +OBJCOPY := $(CROSS_COMPILE)objcopy +endif + +ifeq ($(STACKREPORT),) +ifeq ($(CROSS_COMPILE),nios2-elf-) +STACKREPORT := $(DEFAULT_STACKREPORT) +else +DISABLE_STACKREPORT := 1 +endif +endif + +ifeq ($(DOWNLOAD),) +DOWNLOAD := $(DEFAULT_DOWNLOAD) +endif + +ifeq ($(FLASHPROG),) +FLASHPROG := $(DEFAULT_FLASHPROG) +endif + +ifeq ($(ELFPATCH),) +ELFPATCH := $(DEFAULT_ELFPATCH) +endif + +ifeq ($(MKDIR),) +MKDIR := $(DEFAULT_MKDIR) +endif + +#------------------------------------------------------------------------------ +# PATTERN RULES TO BUILD OBJECTS +#------------------------------------------------------------------------------ + +define compile.c +@$(ECHO) Info: Compiling $< to $@ +@$(MKDIR) $(@D) +$(CC) -MP -MMD -c $(APP_CPPFLAGS) $(APP_CFLAGS) -o $@ $< +$(CC_POST_PROCESS) +endef + +define compile.cpp +@$(ECHO) Info: Compiling $< to $@ +@$(MKDIR) $(@D) +$(CXX) -MP -MMD -c $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $< +$(CXX_POST_PROCESS) +endef + +# If assembling with the compiler, ensure "-Wa," is prepended to all APP_ASFLAGS +ifeq ($(AS),$(patsubst %as,%,$(AS))) +COMMA := , +APP_ASFLAGS := $(filter-out $(APP_CFLAGS),$(addprefix -Wa$(COMMA),$(patsubst -Wa$(COMMA)%,%,$(APP_ASFLAGS)))) +endif + +define compile.s +@$(ECHO) Info: Assembling $< to $@ +@$(MKDIR) $(@D) +$(AS) -MP -MMD -c $(APP_CPPFLAGS) $(APP_CFLAGS) $(APP_ASFLAGS) -o $@ $< +$(AS_POST_PROCESS) +endef + +ifeq ($(MAKE_VERSION),3.81) +.SECONDEXPANSION: + +$(APP_OBJS_C): $(CONFIG_OBJ_DIR)/%.o: $$(call adjust-path-mixed,%.c) + $(compile.c) + +$(APP_OBJS_CPP): $(CONFIG_OBJ_DIR)/%.o: $$(call adjust-path-mixed,%.cpp) + $(compile.cpp) + +$(APP_OBJS_CC): $(CONFIG_OBJ_DIR)/%.o: $$(call adjust-path-mixed,%.cc) + $(compile.cpp) + +$(APP_OBJS_CXX): $(CONFIG_OBJ_DIR)/%.o: $$(call adjust-path-mixed,%.cxx) + $(compile.cpp) + +$(APP_OBJS_S): $(CONFIG_OBJ_DIR)/%.o: $$(call adjust-path-mixed,%.S) + $(compile.s) + +$(APP_OBJS_SS): $(CONFIG_OBJ_DIR)/%.o: $$(call adjust-path-mixed,%.s) + $(compile.s) + +endif # MAKE_VERSION != 3.81 + +$(CONFIG_OBJ_DIR)/%.o: %.c + $(compile.c) + +$(CONFIG_OBJ_DIR)/%.o: %.cpp + $(compile.cpp) + +$(CONFIG_OBJ_DIR)/%.o: %.cc + $(compile.cpp) + +$(CONFIG_OBJ_DIR)/%.o: %.cxx + $(compile.cpp) + +$(CONFIG_OBJ_DIR)/%.o: %.S + $(compile.s) + +$(CONFIG_OBJ_DIR)/%.o: %.s + $(compile.s) + + +#------------------------------------------------------------------------------ +# PATTERN RULES TO INTERMEDIATE FILES +#------------------------------------------------------------------------------ + +$(CONFIG_OBJ_DIR)/%.s: %.c + @$(ECHO) Info: Compiling $< to $@ + @$(MKDIR) $(@D) + $(CC) -S $(APP_CPPFLAGS) $(APP_CFLAGS) -o $@ $< + +$(CONFIG_OBJ_DIR)/%.s: %.cpp + @$(ECHO) Info: Compiling $< to $@ + @$(MKDIR) $(@D) + $(CXX) -S $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $< + +$(CONFIG_OBJ_DIR)/%.s: %.cc + @$(ECHO) Info: Compiling $< to $@ + @$(MKDIR) $(@D) + $(CXX) -S $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $< + +$(CONFIG_OBJ_DIR)/%.s: %.cxx + @$(ECHO) Info: Compiling $< to $@ + @$(MKDIR) $(@D) + $(CXX) -S $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $< + +$(CONFIG_OBJ_DIR)/%.i: %.c + @$(ECHO) Info: Compiling $< to $@ + @$(MKDIR) $(@D) + $(CC) -E $(APP_CPPFLAGS) $(APP_CFLAGS) -o $@ $< + +$(CONFIG_OBJ_DIR)/%.i: %.cpp + @$(ECHO) Info: Compiling $< to $@ + @$(MKDIR) $(@D) + $(CXX) -E $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $< + +$(CONFIG_OBJ_DIR)/%.i: %.cc + @$(ECHO) Info: Compiling $< to $@ + @$(MKDIR) $(@D) + $(CXX) -E $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $< + +$(CONFIG_OBJ_DIR)/%.i: %.cxx + @$(ECHO) Info: Compiling $< to $@ + @$(MKDIR) $(@D) + $(CXX) -E $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $< + + +#------------------------------------------------------------------------------ +# TARGET RULES +#------------------------------------------------------------------------------ + +.PHONY : help +help : + @$(ECHO) "Summary of Makefile targets" + @$(ECHO) " Build targets:" + @$(ECHO) " all (default) - Application and all libraries (including BSP)" + @$(ECHO) " bsp - Just the BSP" + @$(ECHO) " libs - All libraries (including BSP)" + @$(ECHO) " flash - All flash files" + @$(ECHO) " mem_init_generate - All memory initialization files" +ifeq ($(QSYS),1) + @$(ECHO) " mem_init_install - This target is deprecated for QSys Systems" + @$(ECHO) " --> Use the mem_init_generate target and then" + @$(ECHO) " add the generated meminit.qip file to your" + @$(ECHO) " Quartus II Project." +else # if QSYS != 1 + @$(ECHO) " mem_init_install - Copy memory initialization files to Quartus II project" +endif # QSYS == 1 + @$(ECHO) + @$(ECHO) " Clean targets:" + @$(ECHO) " clean_all - Application and all libraries (including BSP)" + @$(ECHO) " clean - Just the application" + @$(ECHO) " clean_bsp - Just the BSP" + @$(ECHO) " clean_libs - All libraries (including BSP)" + @$(ECHO) + @$(ECHO) " Run targets:" + @$(ECHO) " download-elf - Download and run your elf executable" + @$(ECHO) " program-flash - Program flash contents to the board" + +# Handy rule to skip making libraries and just make application. +.PHONY : app +app : $(ELF) + +ifeq ($(CREATE_OBJDUMP), 1) +app : $(OBJDUMP_NAME) +endif + +ifeq ($(CREATE_ELF_DERIVED_FILES),1) +app : elf_derived_files +endif + +.PHONY: elf_derived_files +elf_derived_files: default_mem_init + +# Handy rule for making just the BSP. +.PHONY : bsp +bsp : + @$(ECHO) Info: Building $(BSP_ROOT_DIR) + @$(MAKE) --no-print-directory -C $(BSP_ROOT_DIR) + + +# Make sure all makeable libraries (including the BSP) are up-to-date. +LIB_TARGETS := $(patsubst %,%-recurs-make-lib,$(MAKEABLE_LIBRARY_ROOT_DIRS)) + +.PHONY : libs +libs : $(LIB_TARGETS) + +ifneq ($(strip $(LIB_TARGETS)),) +$(LIB_TARGETS): %-recurs-make-lib: + @$(ECHO) Info: Building $* + $(MAKE) --no-print-directory -C $* +endif + +ifneq ($(strip $(APP_LDDEPS)),) +$(APP_LDDEPS): libs + @true +endif + +# Rules to force your project to rebuild or relink +# .force_relink file will cause any application that depends on this project to relink +# .force_rebuild file will cause this project to rebuild object files +# .force_rebuild_all file will cause this project and any project that depends on this project to rebuild object files + +FORCE_RELINK_DEP := .force_relink +FORCE_REBUILD_DEP := .force_rebuild +FORCE_REBUILD_ALL_DEP := .force_rebuild_all +FORCE_REBUILD_DEP_LIST := $(CONFIG_OBJ_DIR)/$(FORCE_RELINK_DEP) $(CONFIG_OBJ_DIR)/$(FORCE_REBUILD_DEP) $(FORCE_REBUILD_ALL_DEP) + +$(FORCE_REBUILD_DEP_LIST): + +$(APP_OBJS): $(wildcard $(CONFIG_OBJ_DIR)/$(FORCE_REBUILD_DEP)) $(wildcard $(addsuffix /$(FORCE_REBUILD_ALL_DEP), . $(ALT_LIBRARY_DIRS))) + +$(ELF): $(wildcard $(addsuffix /$(FORCE_RELINK_DEP), $(CONFIG_OBJ_DIR) $(ALT_LIBRARY_DIRS))) + + +# Clean just the application. +.PHONY : clean +ifeq ($(CREATE_ELF_DERIVED_FILES),1) +clean : clean_elf_derived_files +endif + +clean : + @$(RM) -r $(ELF) $(OBJDUMP_NAME) $(LINKER_MAP_NAME) $(OBJ_ROOT_DIR) $(RUNTIME_ROOT_DIR) $(FORCE_REBUILD_DEP_LIST) + @$(ECHO) [$(APP_NAME) clean complete] + +# Clean just the BSP. +.PHONY : clean_bsp +clean_bsp : + @$(ECHO) Info: Cleaning $(BSP_ROOT_DIR) + @$(MAKE) --no-print-directory -C $(BSP_ROOT_DIR) clean + +# Clean all makeable libraries including the BSP. +LIB_CLEAN_TARGETS := $(patsubst %,%-recurs-make-clean-lib,$(MAKEABLE_LIBRARY_ROOT_DIRS)) + +.PHONY : clean_libs +clean_libs : $(LIB_CLEAN_TARGETS) + +ifneq ($(strip $(LIB_CLEAN_TARGETS)),) +$(LIB_CLEAN_TARGETS): %-recurs-make-clean-lib: + @$(ECHO) Info: Cleaning $* + $(MAKE) --no-print-directory -C $* clean +endif + +.PHONY: clean_elf_derived_files +clean_elf_derived_files: mem_init_clean + +# Clean application and all makeable libraries including the BSP. +.PHONY : clean_all +clean_all : clean mem_init_clean clean_libs + +# Include the dependency files unless the make goal is performing a clean +# of the application. +ifneq ($(firstword $(MAKECMDGOALS)),clean) +ifneq ($(firstword $(MAKECMDGOALS)),clean_all) +-include $(APP_DEPS) +endif +endif + +.PHONY : download-elf +download-elf : $(ELF) + @if [ "$(DOWNLOAD)" = "none" ]; \ + then \ + $(ECHO) Downloading $(ELF) not supported; \ + else \ + $(ECHO) Info: Downloading $(ELF); \ + $(DOWNLOAD) --go --cpu_name=$(CPU_NAME) $(DOWNLOAD_CABLE_FLAG) $(SOPC_SYSID_FLAG) $(DOWNLOAD_JDI_FLAG) $(WRITE_GMON_OPTION) $(ELF); \ + fi + +# Delete the target of a rule if it has changed and its commands exit +# with a nonzero exit status. +.DELETE_ON_ERROR: + +# Rules for flash programming commands +PROGRAM_FLASH_SUFFIX := -program +PROGRAM_FLASH_TARGET := $(addsuffix $(PROGRAM_FLASH_SUFFIX), $(FLASH_FILES)) + +.PHONY : program-flash +program-flash : $(PROGRAM_FLASH_TARGET) + +.PHONY : $(PROGRAM_FLASH_TARGET) +$(PROGRAM_FLASH_TARGET) : flash + @if [ "$(FLASHPROG)" = "none" ]; \ + then \ + $(ECHO) Programming flash not supported; \ + else \ + $(ECHO) Info: Programming $(basename $@).flash; \ + if [ -z "$($(basename $@)_EPCS_FLAGS)" ]; \ + then \ + $(ECHO) $(FLASHPROG) $(SOPC_SYSID_FLAG) --base=$($(basename $@)_START) $(basename $@).flash; \ + $(FLASHPROG) $(DOWNLOAD_CABLE_FLAG) $(SOPC_SYSID_FLAG) --base=$($(basename $@)_START) $(basename $@).flash; \ + else \ + $(ECHO) $(FLASHPROG) $(SOPC_SYSID_FLAG) --epcs --base=$($(basename $@)_START) $(basename $@).flash; \ + $(FLASHPROG) $(DOWNLOAD_CABLE_FLAG) $(SOPC_SYSID_FLAG) --epcs --base=$($(basename $@)_START) $(basename $@).flash; \ + fi \ + fi + + +# Rules for simulating with an HDL Simulator [QSYS only] +ifeq ($(QSYS),1) +IP_MAKE_SIMSCRIPT := ip-make-simscript + +ifeq ($(VSIM),) +VSIM_EXE := $(if $(VSIM_DIR),$(VSIM_DIR)/,)vsim +ifeq ($(ENABLE_VSIM_GUI),1) +VSIM := $(VSIM_EXE) -gui +else +VSIM := $(VSIM_EXE) -c +endif # ENABLE_VSIM_GUI == 1 +endif # VSIM not set + +ifeq ($(SPD),) +ifneq ($(ABS_QUARTUS_PROJECT_DIR),) +ifneq ($(SOPC_NAME),) +SPD := $(ABS_QUARTUS_PROJECT_DIR)/$(SOPC_NAME)_tb.spd +endif # SOPC_NAME set +endif # ABS_QUARTUS_PROJECT_DIR set +endif # SPD == empty string + +ifeq ($(MSIM_SCRIPT),) +SIM_SCRIPT_DIR := $(RUNTIME_ROOT_DIR)/sim +MSIM_SCRIPT := $(SIM_SCRIPT_DIR)/mentor/msim_setup.tcl +endif # MSIM_SCRIPT == empty string + +ifeq ($(MAKE_VERSION),3.81) +ABS_MEM_INIT_DESCRIPTOR_FILE := $(abspath $(MEM_INIT_DESCRIPTOR_FILE)) +else +ABS_MEM_INIT_DESCRIPTOR_FILE := $(call adjust-path-mixed,$(shell pwd))/$(MEM_INIT_DESCRIPTOR_FILE) +endif + +$(MSIM_SCRIPT): $(SPD) $(MEM_INIT_DESCRIPTOR_FILE) +ifeq ($(SPD),) + $(error No SPD file specified. Ensure QUARTUS_PROJECT_DIR variable is set) +endif + @$(MKDIR) $(SIM_SCRIPT_DIR) + $(IP_MAKE_SIMSCRIPT) --spd=$(SPD) --spd=$(MEM_INIT_DESCRIPTOR_FILE) --output-directory=$(SIM_SCRIPT_DIR) + +VSIM_COMMAND = \ + cd $(dir $(MSIM_SCRIPT)) && \ + $(VSIM) -do "do $(notdir $(MSIM_SCRIPT)); ld; $(if $(VSIM_RUN_TIME),run ${VSIM_RUN_TIME};quit;)" + +.PHONY: sim +sim: $(MSIM_SCRIPT) mem_init_generate +ifeq ($(MSIM_SCRIPT),) + $(error MSIM_SCRIPT not set) +endif + $(VSIM_COMMAND) + +endif # QSYS == 1 + + +#------------------------------------------------------------------------------ +# ELF TARGET RULE +#------------------------------------------------------------------------------ +# Rule for constructing the executable elf file. +$(ELF) : $(APP_OBJS) $(LINKER_SCRIPT) $(APP_LDDEPS) + @$(ECHO) Info: Linking $@ + $(LD) $(APP_LDFLAGS) $(APP_CFLAGS) -o $@ $(filter-out $(CRT0),$(APP_OBJS)) $(APP_LIBS) $(APP_BSP_DEP_LIBS) +ifneq ($(DISABLE_ELFPATCH),1) + $(ELFPATCH) $@ $(ELF_PATCH_FLAG) +endif +ifneq ($(DISABLE_STACKREPORT),1) + @bash -c "$(STACKREPORT) $@" +endif + +$(OBJDUMP_NAME) : $(ELF) + @$(ECHO) Info: Creating $@ + $(OBJDUMP) $(OBJDUMP_FLAGS) $< >$@ + +# Rule for printing the name of the elf file +.PHONY: print-elf-name +print-elf-name: + @$(ECHO) $(ELF) + + diff --git a/MCTEST/DE0-nano-HD/Software/MCTest/MotorHandler.cpp b/MCTEST/DE0-nano-HD/Software/MCTest/MotorHandler.cpp new file mode 100644 index 00000000..880ec9ce --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/MCTest/MotorHandler.cpp @@ -0,0 +1,136 @@ +/* + * MotorHandler.cpp + * + * Created on: 2014-03-03 + * Author: Amshu Gongal + */ + + +#include +#include + +#include "altera_avalon_pio_regs.h" +#include "includes.h" +#include "system.h" + +#include "MotorHandler.h" + +#define WRITE_FIFO_EMPTY 0x80 +#define MOTOR_ENABLE 1 +#define MOTOR_RESET 0 + +// ALLOCATION +MotorHandler::MotorHandler() {} +MotorHandler::~MotorHandler() {} + + +// INITIALIZATION + +/* + * Initializes this handler. + * @return OK if the handler was initialized without error + */ +Status MotorHandler::init() { + // Enable the motor controller. + reset(); + // Open the serial device to send commands to the motor controller. + motor_dev = alt_up_rs232_open_dev(RS232_MOTOR_NAME); + //printf("%d", motor_dev); + if (motor_dev == NULL) { + return ERR_MOTOR_OPEN; + } else { + return OK; + } +} + +void MotorHandler::configure(){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_CHANGE_CONFIGURATION, "change configuration"); + send(0X01, "2 MOTOR CONFIG"); + printf("\n"); +} + +//Command Interpreter +/* + * Interprets the command from the network handler and sends move commands + * @param motor The motor to move eg. Left or Right + * @param motorDirection The direction of the given motor to move + * @param speed The speed the motor is to move + */ +void MotorHandler::motorCommand(string motor, string motorDirection, string speed){ + char motorID = interpretMotor(motor); + char directionByte = interpretDirection(motorDirection, int(motorID)); + int speedByte = strtol(speed.c_str(), NULL, 0); + move(directionByte, speedByte, (motor.append(motorDirection)).c_str()); +} + + +char MotorHandler::interpretMotor(string motor){ + if(motor.compare(MOTOR_LEFT) == 0){ + return MOTOR_LEFT_CHAR; + } + else{ + return MOTOR_RIGHT_CHAR; + } +} + +char MotorHandler::interpretDirection(string direction, int motor){ + if(direction.compare(MOTOR_FORWARD) == 0){ + return (char) (motor*2 + 1); + } + else{ + return (char) (motor*2); + } +} + +// MOTOR CONTROL + +/*Moves the given motor in specified direction by Motor Direction with specified + * Speed + * @param MotorDirection Motor and direction to move + * @param Speed the speed to move at + * @param string description of motor movement + */ + +void MotorHandler::move(char motorDirection, char speed,const char *description){ + send(MOTOR_START_BYTE, "start"); + send(MOTOR_DEVICE_TYPE, "device"); + send(motorDirection, description); + send(speed, "speed"); + printf("\n"); +} + +// MOTOR CONTROL HELPERS +/* + * Sends a byte-length message to the motor controller. + * @param message - the message to send + * @param description - the string description of the message, for debugging + */ +void MotorHandler::send(char message, const char *description) { + alt_u32 write_space; + // Check for write space. + write_space = alt_up_rs232_get_available_space_in_write_FIFO(motor_dev); + if (write_space >= WRITE_FIFO_EMPTY) { + // If space, write. + int status = alt_up_rs232_write_data(motor_dev, message); + printf("MotorHandler [message: 0x%02x, description: %s", message, description); + // Log errors. + if (status == OK) { + printf("]\n"); + } else { + printf(", error: cannot write]\n"); + } + } else { + // If no space, wait and retry. + printf("MotorHandler [message: 0x%02x, description: %s, error: no write space; retrying]\n", message, description); + OSTimeDlyHMSM(0, 0, 0, 10); + send(message, description); + } +} + +void MotorHandler::reset(){ + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 0); + OSTimeDlyHMSM(0, 0, 0,200 ); + IOWR_ALTERA_AVALON_PIO_DATA(PIO_MOTOR_RST_BASE, 1); + OSTimeDlyHMSM(0, 0, 0, 200); +} diff --git a/MCTEST/DE0-nano-HD/Software/MCTest/MotorHandler.h b/MCTEST/DE0-nano-HD/Software/MCTest/MotorHandler.h new file mode 100644 index 00000000..9e6c9f97 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/MCTest/MotorHandler.h @@ -0,0 +1,73 @@ +/* + * MotorHandler.h + * + * Created on: 2014-03-03 + * Author: Amshu Gongal + */ + +#ifndef MOTORHANDLER_H_ +#define MOTORHANDLER_H_ + +#include "altera_up_avalon_rs232.h" +#include "altera_up_avalon_rs232_regs.h" +#include +using namespace std; +#include +#include "Status.h" + +//Commands from network handler +#define MOTOR_LEFT "left" +#define MOTOR_RIGHT "right" +#define MOTOR_FORWARD "forward" +#define MOTOR_BACKWARD "backward" + + +// Motor messages are LSB first +#define MOTOR_START_BYTE 0x80 +#define MOTOR_DEVICE_TYPE 0x00 +#define MOTOR_LEFT_CHAR 0x02 // motor 1 backward +#define MOTOR_RIGHT_CHAR 0x03 // motor 2 backward +#define MOTOR_LEFT_FORWARD 0x05 // motor 1 forward +#define MOTOR_RIGHT_FORWARD 0x07 // motor 2 forward +#define MOTOR_CONST_SPEED 0x5F +#define MOTOR_STOP_SPEED 0x00 +#define MOTOR_CHANGE_CONFIGURATION 0X02 + +class MotorHandler { +public: + MotorHandler(); + virtual ~MotorHandler(); + + /* + * Initializes this handler. + * @return OK if the handler was initialized without error + */ + Status init(); + void reset(); + void configure(); + void motorCommand(string motor, string motorDirection, string speed); + +private: + /* The device used to send serial commands to the motor controller. */ + alt_up_rs232_dev *motor_dev; + + char interpretMotor(string motor); + char interpretDirection(string direction, int motor); + + /* + * Moves in the given direction at constant speed. + * @param direction - the motor and direction to move in, e.g. MOTOR_MOTOR1_FORWARD + * @param speed speed of the motor + * @param description - the string description of the movement, for debugging + */ + void move(char direction, char speed, const char *description); + + /* + * Sends a byte-length message to the motor controller. + * @param message - the message to send + * @param description - the string description of the message, for debugging + */ + void send(char message, const char *description); +}; + +#endif /* MOTORHANDLER_H_ */ diff --git a/MCTEST/DE0-nano-HD/Software/MCTest/Status.h b/MCTEST/DE0-nano-HD/Software/MCTest/Status.h new file mode 100644 index 00000000..3714fbbd --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/MCTest/Status.h @@ -0,0 +1,16 @@ +/* + * Status.h + * + * Created on: 2014-03-05 + * Author: Kenan Kigunda + */ + +#ifndef STATUS_H_ +#define STATUS_H_ + +typedef enum Status { + OK = 0, + ERR_MOTOR_OPEN +} Status; + +#endif /* STATUS_H_ */ diff --git a/MCTEST/DE0-nano-HD/Software/MCTest/create-this-app b/MCTEST/DE0-nano-HD/Software/MCTest/create-this-app new file mode 100644 index 00000000..9dd2653f --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/MCTest/create-this-app @@ -0,0 +1,114 @@ +#!/bin/bash +# +# This script creates the hello_ucosii application in this directory. + + +BSP_DIR=../MCTest_bsp +QUARTUS_PROJECT_DIR=../../ +NIOS2_APP_GEN_ARGS="--elf-name MCTest.elf --set OBJDUMP_INCLUDE_SOURCE 1 --src-files hello_ucosii.c" + + +# First, check to see if $SOPC_KIT_NIOS2 environmental variable is set. +# This variable is required for the command line tools to execute correctly. +if [ -z "${SOPC_KIT_NIOS2}" ] +then + echo Required \$SOPC_KIT_NIOS2 Environmental Variable is not set! + exit 1 +fi + + +# Also make sure that the APP has not been created already. Check for +# existence of Makefile in the app directory +if [ -f ./Makefile ] +then + echo Application has already been created! Delete Makefile if you want to create a new application makefile + exit 1 +fi + + +# We are selecting ucosii_default bsp because it supports this application. +# Check to see if the ucosii_default has already been generated by checking for +# existence of the public.mk file. If not, we need to run +# create-this-bsp file to generate the bsp. +if [ ! -f ${BSP_DIR}/public.mk ]; then + # Since BSP doesn't exist, create the BSP + # Pass any command line arguments passed to this script to the BSP. + pushd ${BSP_DIR} >> /dev/null + ./create-this-bsp "$@" || { + echo "create-this-bsp failed" + exit 1 + } + popd >> /dev/null +fi + + +# Don't run make if create-this-app script is called with --no-make arg +SKIP_MAKE= +while [ $# -gt 0 ] +do + case "$1" in + --no-make) + SKIP_MAKE=1 + ;; + esac + shift +done + + +# Now we also need to go copy the sources for this application to the +# local directory. +find "${SOPC_KIT_NIOS2}/examples/software/hello_ucosii/" -name '*.c' -or -name '*.h' -or -name 'hostfs*' | xargs -i cp -L {} ./ || { + echo "failed during copying example source files" + exit 1 +} + +find "${SOPC_KIT_NIOS2}/examples/software/hello_ucosii/" -name 'readme.txt' -or -name 'Readme.txt' | xargs -i cp -L {} ./ || { + echo "failed copying readme file" +} + +if [ -d "${SOPC_KIT_NIOS2}/examples/software/hello_ucosii/system" ] +then + cp -RL "${SOPC_KIT_NIOS2}/examples/software/hello_ucosii/system" . || { + echo "failed during copying project support files" + exit 1 + } +fi + +chmod -R +w . || { + echo "failed during changing file permissions" + exit 1 +} + +cmd="nios2-app-generate-makefile --bsp-dir ${BSP_DIR} --set QUARTUS_PROJECT_DIR=${QUARTUS_PROJECT_DIR} ${NIOS2_APP_GEN_ARGS}" + +echo "create-this-app: Running \"${cmd}\"" +$cmd || { + echo "nios2-app-generate-makefile failed" + exit 1 +} + +if [ -z "$SKIP_MAKE" ]; then + cmd="make" + + echo "create-this-app: Running \"$cmd\"" + $cmd || { + echo "make failed" + exit 1 + } + + echo + echo "To download and run the application:" + echo " 1. Make sure the board is connected to the system." + echo " 2. Run 'nios2-configure-sof ' to configure the FPGA with the hardware design." + echo " 3. If you have a stdio device, run 'nios2-terminal' in a different shell." + echo " 4. Run 'make download-elf' from the application directory." + echo + echo "To debug the application:" + echo " Import the project into Nios II Software Build Tools for Eclipse." + echo " Refer to Nios II Software Build Tools for Eclipse Documentation for more information." + echo + echo -e "" +fi + + +exit 0 diff --git a/MCTEST/DE0-nano-HD/Software/MCTest/main.cpp b/MCTEST/DE0-nano-HD/Software/MCTest/main.cpp new file mode 100644 index 00000000..c3ae48cd --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/MCTest/main.cpp @@ -0,0 +1,163 @@ +/************************************************************************* + * ARCap + * Amshu Gongal, Kenan Kigunda + * February 18, 2014 + ************************************************************************** + * Description: * + * Prototype testing for infrared and mc. + **************************************************************************/ + +#include +#include "includes.h" +#include "altera_avalon_pio_regs.h" +#include "altera_avalon_uart_regs.h" +#include "sys/alt_irq.h" +#include "alt_types.h" +#include "altera_up_avalon_rs232.h" +#include "altera_up_avalon_rs232_regs.h" + +#include "MotorHandler.h" +#include "Status.h" + +/* Task stacks */ +#define TASK_STACKSIZE 2048 +OS_STK ir_task_stk[TASK_STACKSIZE]; +OS_STK mc_task_stk[TASK_STACKSIZE]; +/* Task priorities */ +#define IR_TASK_PRIORITY 2 +#define MC_TASK_PRIORITY 1 + + +#define SW_READ 1 +#define SW_WRITE 2 +#define WRITE_FIFO_EMPTY 0x80 +#define READ_FIFO_EMPTY 0x0 +OS_EVENT *SWQ; +OS_EVENT *RS232Q; +INT8U err; + + +/* Error status */ +#define OK 0 + +/* Message queues */ +#define WAIT_FOREVER 0 + +// ==== INFRARED ==== + +/* Infrared message queue */ +#define IR_MAX_MESSAGES 4 +int ir_messages[IR_MAX_MESSAGES]; +OS_EVENT *ir_queue; + +/* Infrared messages */ +// Together these avoid passing 0 to the queue (which is not allowed since queue messages cannot be null) +// and invert pushbutton input (since the pushbutton returns 0 when it is pushed down). +#define IR_QUEUE_SEND_BASE 1 // Use: IR_QUEUE_SEND_BASE + IORD +#define IR_QUEUE_RECEIVE_BASE 2 // Use: IR_QUEUE_RECEIVE_BASE - OSQPend + + +MotorHandler *motor= new MotorHandler(); + + +// ==== mc + +#define mc_GUARD_TIME 1 + +void mc_task(void *pdata) +{ + printf("mc task\n"); + printf("MotorHandler [init"); + if (motor->init() == OK) { + printf("]\n\n"); + } else { + printf( ", error]\n"); + } + while(1){ + motor->motorCommand("left", "forward", "120"); + motor->motorCommand("right","forward", "120"); + OSTimeDlyHMSM(0, 0, 5, 0); + motor->motorCommand("left", "forward", "0"); + motor->motorCommand("right","forward", "0"); + OSTimeDlyHMSM(0, 0, 5, 0); + motor->motorCommand("left", "backward", "120"); + motor->motorCommand("right","backward", "120"); + OSTimeDlyHMSM(0, 0, 5, 0); + motor->motorCommand("left", "forward", "0"); + motor->motorCommand("right","forward", "0"); + OSTimeDlyHMSM(0, 0, 5, 0); + motor->motorCommand("right","forward", "120"); + OSTimeDlyHMSM(0, 0, 5, 0); + motor->motorCommand("right","forward", "0"); + OSTimeDlyHMSM(0, 0, 5, 0); + motor->motorCommand("left","forward", "120"); + OSTimeDlyHMSM(0, 0, 5, 0); + motor->motorCommand("left","forward", "0"); + OSTimeDlyHMSM(0, 0, 5, 0); + + } +} + + + +// ==== GENERAL + +void queue_init() { + ir_queue = OSQCreate((void**)&ir_messages, IR_MAX_MESSAGES); +} + +/* The main function creates the LCD task, registers the edge counter polling interrupt, + * and starts the OS. */ +int main(void) +{ + int status = OK; + // Initialize components. + queue_init(); + // Create the mc task. + OSTaskCreateExt(mc_task, + NULL, + &mc_task_stk[TASK_STACKSIZE - 1], + MC_TASK_PRIORITY, + MC_TASK_PRIORITY, + mc_task_stk, + TASK_STACKSIZE, + NULL, + 0); + + if (status == OK) { + OSStart(); + } + + return 0; +} + +/****************************************************************************** + * * + * License Agreement * + * * + * Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * + * All rights reserved. * + * * + * Permission is hereby granted, free of charge, to any person obtaining a * + * copy of this software and associated documentation files (the "Software"), * + * to deal in the Software without restriction, including without limitation * + * the rights to use, copy, modify, merge, publish, distribute, sublicense, * + * and/or sell copies of the Software, and to permit persons to whom the * + * Software is furnished to do so, subject to the following conditions: * + * * + * The above copyright notice and this permission notice shall be included in * + * all copies or substantial portions of the Software. * + * * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * + * DEALINGS IN THE SOFTWARE. * + * * + * This agreement shall be governed in all respects by the laws of the State * + * of California and by the laws of the United States of America. * + * Altera does not recommend, suggest or require that this reference design * + * file be used in conjunction or combination with any other product. * + ******************************************************************************/ diff --git a/MCTEST/DE0-nano-HD/Software/MCTest/obj/default/MotorHandler.d b/MCTEST/DE0-nano-HD/Software/MCTest/obj/default/MotorHandler.d new file mode 100644 index 00000000..d76402d5 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/MCTest/obj/default/MotorHandler.d @@ -0,0 +1,87 @@ +obj/default/MotorHandler.o: MotorHandler.cpp \ + ../MCTest_bsp//drivers/inc/altera_avalon_pio_regs.h \ + ../MCTest_bsp//HAL/inc/io.h ../MCTest_bsp//HAL/inc/alt_types.h \ + ../MCTest_bsp//HAL/inc/includes.h ../MCTest_bsp//HAL/inc/os_cpu.h \ + ../MCTest_bsp//HAL/inc/sys/alt_irq.h ../MCTest_bsp//HAL/inc/nios2.h \ + ../MCTest_bsp//HAL/inc/alt_types.h ../MCTest_bsp/system.h \ + ../MCTest_bsp/linker.h ../MCTest_bsp//HAL/inc/priv/alt_legacy_irq.h \ + ../MCTest_bsp/system.h ../MCTest_bsp//HAL/inc/nios2.h \ + ../MCTest_bsp//HAL/inc/alt_types.h ../MCTest_bsp//HAL/inc/sys/alt_irq.h \ + ../MCTest_bsp//UCOSII/inc/os_cfg.h \ + ../MCTest_bsp//HAL/inc/sys/alt_alarm.h \ + ../MCTest_bsp//HAL/inc/sys/alt_llist.h \ + ../MCTest_bsp//HAL/inc/priv/alt_alarm.h ../MCTest_bsp/system.h \ + ../MCTest_bsp//UCOSII/inc/ucos_ii.h ../MCTest_bsp//UCOSII/inc/os_cfg.h \ + ../MCTest_bsp//HAL/inc/os_cpu.h ../MCTest_bsp/system.h MotorHandler.h \ + ../MCTest_bsp//drivers/inc/altera_up_avalon_rs232.h \ + ../MCTest_bsp//HAL/inc/alt_types.h ../MCTest_bsp//HAL/inc/sys/alt_dev.h \ + ../MCTest_bsp//HAL/inc/sys/alt_llist.h \ + ../MCTest_bsp//HAL/inc/priv/alt_dev_llist.h \ + ../MCTest_bsp//HAL/inc/sys/alt_llist.h \ + ../MCTest_bsp//drivers/inc/altera_up_avalon_rs232_regs.h Status.h + +../MCTest_bsp//drivers/inc/altera_avalon_pio_regs.h: + +../MCTest_bsp//HAL/inc/io.h: + +../MCTest_bsp//HAL/inc/alt_types.h: + +../MCTest_bsp//HAL/inc/includes.h: + +../MCTest_bsp//HAL/inc/os_cpu.h: + +../MCTest_bsp//HAL/inc/sys/alt_irq.h: + +../MCTest_bsp//HAL/inc/nios2.h: + +../MCTest_bsp//HAL/inc/alt_types.h: + +../MCTest_bsp/system.h: + +../MCTest_bsp/linker.h: + +../MCTest_bsp//HAL/inc/priv/alt_legacy_irq.h: + +../MCTest_bsp/system.h: + +../MCTest_bsp//HAL/inc/nios2.h: + +../MCTest_bsp//HAL/inc/alt_types.h: + +../MCTest_bsp//HAL/inc/sys/alt_irq.h: + +../MCTest_bsp//UCOSII/inc/os_cfg.h: + +../MCTest_bsp//HAL/inc/sys/alt_alarm.h: + +../MCTest_bsp//HAL/inc/sys/alt_llist.h: + +../MCTest_bsp//HAL/inc/priv/alt_alarm.h: + +../MCTest_bsp/system.h: + +../MCTest_bsp//UCOSII/inc/ucos_ii.h: + +../MCTest_bsp//UCOSII/inc/os_cfg.h: + +../MCTest_bsp//HAL/inc/os_cpu.h: + +../MCTest_bsp/system.h: + +MotorHandler.h: + +../MCTest_bsp//drivers/inc/altera_up_avalon_rs232.h: + +../MCTest_bsp//HAL/inc/alt_types.h: + +../MCTest_bsp//HAL/inc/sys/alt_dev.h: + +../MCTest_bsp//HAL/inc/sys/alt_llist.h: + +../MCTest_bsp//HAL/inc/priv/alt_dev_llist.h: + +../MCTest_bsp//HAL/inc/sys/alt_llist.h: + +../MCTest_bsp//drivers/inc/altera_up_avalon_rs232_regs.h: + +Status.h: diff --git a/MCTEST/DE0-nano-HD/Software/MCTest/obj/default/MotorHandler.o b/MCTEST/DE0-nano-HD/Software/MCTest/obj/default/MotorHandler.o new file mode 100644 index 00000000..52e308aa Binary files /dev/null and b/MCTEST/DE0-nano-HD/Software/MCTest/obj/default/MotorHandler.o differ diff --git a/MCTEST/DE0-nano-HD/Software/MCTest/obj/default/main.d b/MCTEST/DE0-nano-HD/Software/MCTest/obj/default/main.d new file mode 100644 index 00000000..1ae23a56 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/MCTest/obj/default/main.d @@ -0,0 +1,93 @@ +obj/default/main.o: main.cpp ../MCTest_bsp//HAL/inc/includes.h \ + ../MCTest_bsp//HAL/inc/os_cpu.h ../MCTest_bsp//HAL/inc/sys/alt_irq.h \ + ../MCTest_bsp//HAL/inc/nios2.h ../MCTest_bsp//HAL/inc/alt_types.h \ + ../MCTest_bsp/system.h ../MCTest_bsp/linker.h \ + ../MCTest_bsp//HAL/inc/priv/alt_legacy_irq.h ../MCTest_bsp/system.h \ + ../MCTest_bsp//HAL/inc/nios2.h ../MCTest_bsp//HAL/inc/alt_types.h \ + ../MCTest_bsp//HAL/inc/sys/alt_irq.h ../MCTest_bsp//UCOSII/inc/os_cfg.h \ + ../MCTest_bsp//HAL/inc/sys/alt_alarm.h \ + ../MCTest_bsp//HAL/inc/sys/alt_llist.h \ + ../MCTest_bsp//HAL/inc/priv/alt_alarm.h ../MCTest_bsp/system.h \ + ../MCTest_bsp//UCOSII/inc/ucos_ii.h ../MCTest_bsp//UCOSII/inc/os_cfg.h \ + ../MCTest_bsp//HAL/inc/os_cpu.h \ + ../MCTest_bsp//drivers/inc/altera_avalon_pio_regs.h \ + ../MCTest_bsp//HAL/inc/io.h ../MCTest_bsp//HAL/inc/alt_types.h \ + ../MCTest_bsp//drivers/inc/altera_avalon_uart_regs.h \ + ../MCTest_bsp//HAL/inc/sys/alt_irq.h ../MCTest_bsp//HAL/inc/alt_types.h \ + ../MCTest_bsp//drivers/inc/altera_up_avalon_rs232.h \ + ../MCTest_bsp//HAL/inc/alt_types.h ../MCTest_bsp//HAL/inc/sys/alt_dev.h \ + ../MCTest_bsp//HAL/inc/sys/alt_llist.h \ + ../MCTest_bsp//HAL/inc/priv/alt_dev_llist.h \ + ../MCTest_bsp//HAL/inc/sys/alt_llist.h \ + ../MCTest_bsp//drivers/inc/altera_up_avalon_rs232_regs.h MotorHandler.h \ + Status.h + +../MCTest_bsp//HAL/inc/includes.h: + +../MCTest_bsp//HAL/inc/os_cpu.h: + +../MCTest_bsp//HAL/inc/sys/alt_irq.h: + +../MCTest_bsp//HAL/inc/nios2.h: + +../MCTest_bsp//HAL/inc/alt_types.h: + +../MCTest_bsp/system.h: + +../MCTest_bsp/linker.h: + +../MCTest_bsp//HAL/inc/priv/alt_legacy_irq.h: + +../MCTest_bsp/system.h: + +../MCTest_bsp//HAL/inc/nios2.h: + +../MCTest_bsp//HAL/inc/alt_types.h: + +../MCTest_bsp//HAL/inc/sys/alt_irq.h: + +../MCTest_bsp//UCOSII/inc/os_cfg.h: + +../MCTest_bsp//HAL/inc/sys/alt_alarm.h: + +../MCTest_bsp//HAL/inc/sys/alt_llist.h: + +../MCTest_bsp//HAL/inc/priv/alt_alarm.h: + +../MCTest_bsp/system.h: + +../MCTest_bsp//UCOSII/inc/ucos_ii.h: + +../MCTest_bsp//UCOSII/inc/os_cfg.h: + +../MCTest_bsp//HAL/inc/os_cpu.h: + +../MCTest_bsp//drivers/inc/altera_avalon_pio_regs.h: + +../MCTest_bsp//HAL/inc/io.h: + +../MCTest_bsp//HAL/inc/alt_types.h: + +../MCTest_bsp//drivers/inc/altera_avalon_uart_regs.h: + +../MCTest_bsp//HAL/inc/sys/alt_irq.h: + +../MCTest_bsp//HAL/inc/alt_types.h: + +../MCTest_bsp//drivers/inc/altera_up_avalon_rs232.h: + +../MCTest_bsp//HAL/inc/alt_types.h: + +../MCTest_bsp//HAL/inc/sys/alt_dev.h: + +../MCTest_bsp//HAL/inc/sys/alt_llist.h: + +../MCTest_bsp//HAL/inc/priv/alt_dev_llist.h: + +../MCTest_bsp//HAL/inc/sys/alt_llist.h: + +../MCTest_bsp//drivers/inc/altera_up_avalon_rs232_regs.h: + +MotorHandler.h: + +Status.h: diff --git a/MCTEST/DE0-nano-HD/Software/MCTest/obj/default/main.o b/MCTEST/DE0-nano-HD/Software/MCTest/obj/default/main.o new file mode 100644 index 00000000..0f42fe78 Binary files /dev/null and b/MCTEST/DE0-nano-HD/Software/MCTest/obj/default/main.o differ diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0/readme.txt b/MCTEST/DE0-nano-HD/Software/MCTest/readme.txt similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0/readme.txt rename to MCTEST/DE0-nano-HD/Software/MCTest/readme.txt diff --git a/MCTEST/DE0-nano-HD/Software/MCTest_bsp/.cproject b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/.cproject new file mode 100644 index 00000000..0436f645 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/.cproject @@ -0,0 +1,481 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/MCTEST/DE0-nano-HD/Software/MCTest_bsp/.project b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/.project new file mode 100644 index 00000000..bebef029 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/.project @@ -0,0 +1,85 @@ + + + MCTest_bsp + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + + + + org.eclipse.cdt.make.core.buildCommand + make + + + org.eclipse.cdt.make.core.buildLocation + ${workspace_loc://MCTest_bsp} + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + org.eclipse.cdt.core.ccnature + com.altera.sbtgui.project.SBTGUINature + com.altera.sbtgui.project.SBTGUIBspNature + + diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/inc/alt_types.h b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/inc/alt_types.h similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/inc/alt_types.h rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/inc/alt_types.h diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/inc/altera_nios2_qsys_irq.h b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/inc/altera_nios2_qsys_irq.h similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/inc/altera_nios2_qsys_irq.h rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/inc/altera_nios2_qsys_irq.h diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/inc/includes.h b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/inc/includes.h similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/inc/includes.h rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/inc/includes.h diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/inc/io.h b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/inc/io.h similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/inc/io.h rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/inc/io.h diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/inc/nios2.h b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/inc/nios2.h similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/inc/nios2.h rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/inc/nios2.h diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/inc/os/alt_syscall.h b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/inc/os/alt_syscall.h similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/inc/os/alt_syscall.h rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/inc/os/alt_syscall.h diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/inc/os_cpu.h b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/inc/os_cpu.h similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/inc/os_cpu.h rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/inc/os_cpu.h diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/inc/priv/alt_alarm.h b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/inc/priv/alt_alarm.h similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/inc/priv/alt_alarm.h rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/inc/priv/alt_alarm.h diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/inc/priv/alt_busy_sleep.h b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/inc/priv/alt_busy_sleep.h similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/inc/priv/alt_busy_sleep.h rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/inc/priv/alt_busy_sleep.h diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/inc/priv/alt_dev_llist.h b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/inc/priv/alt_dev_llist.h similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/inc/priv/alt_dev_llist.h rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/inc/priv/alt_dev_llist.h diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/inc/priv/alt_exception_handler_registry.h b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/inc/priv/alt_exception_handler_registry.h similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/inc/priv/alt_exception_handler_registry.h rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/inc/priv/alt_exception_handler_registry.h diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/inc/priv/alt_file.h b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/inc/priv/alt_file.h similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/inc/priv/alt_file.h rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/inc/priv/alt_file.h diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/inc/priv/alt_iic_isr_register.h b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/inc/priv/alt_iic_isr_register.h similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/inc/priv/alt_iic_isr_register.h rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/inc/priv/alt_iic_isr_register.h diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/inc/priv/alt_irq_table.h b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/inc/priv/alt_irq_table.h similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/inc/priv/alt_irq_table.h rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/inc/priv/alt_irq_table.h diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/inc/priv/alt_legacy_irq.h b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/inc/priv/alt_legacy_irq.h similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/inc/priv/alt_legacy_irq.h rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/inc/priv/alt_legacy_irq.h diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/inc/priv/alt_no_error.h b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/inc/priv/alt_no_error.h similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/inc/priv/alt_no_error.h rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/inc/priv/alt_no_error.h diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/inc/priv/nios2_gmon_data.h b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/inc/priv/nios2_gmon_data.h similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/inc/priv/nios2_gmon_data.h rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/inc/priv/nios2_gmon_data.h diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/inc/sys/alt_alarm.h b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/inc/sys/alt_alarm.h similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/inc/sys/alt_alarm.h rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/inc/sys/alt_alarm.h diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/inc/sys/alt_cache.h b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/inc/sys/alt_cache.h similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/inc/sys/alt_cache.h rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/inc/sys/alt_cache.h diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/inc/sys/alt_debug.h b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/inc/sys/alt_debug.h similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/inc/sys/alt_debug.h rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/inc/sys/alt_debug.h diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/inc/sys/alt_dev.h b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/inc/sys/alt_dev.h similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/inc/sys/alt_dev.h rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/inc/sys/alt_dev.h diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/inc/sys/alt_dma.h b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/inc/sys/alt_dma.h similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/inc/sys/alt_dma.h rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/inc/sys/alt_dma.h diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/inc/sys/alt_dma_dev.h b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/inc/sys/alt_dma_dev.h similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/inc/sys/alt_dma_dev.h rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/inc/sys/alt_dma_dev.h diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/inc/sys/alt_driver.h b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/inc/sys/alt_driver.h similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/inc/sys/alt_driver.h rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/inc/sys/alt_driver.h diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/inc/sys/alt_errno.h b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/inc/sys/alt_errno.h similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/inc/sys/alt_errno.h rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/inc/sys/alt_errno.h diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/inc/sys/alt_exceptions.h b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/inc/sys/alt_exceptions.h similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/inc/sys/alt_exceptions.h rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/inc/sys/alt_exceptions.h diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/inc/sys/alt_flash.h b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/inc/sys/alt_flash.h similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/inc/sys/alt_flash.h rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/inc/sys/alt_flash.h diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/inc/sys/alt_flash_dev.h b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/inc/sys/alt_flash_dev.h similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/inc/sys/alt_flash_dev.h rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/inc/sys/alt_flash_dev.h diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/inc/sys/alt_flash_types.h b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/inc/sys/alt_flash_types.h similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/inc/sys/alt_flash_types.h rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/inc/sys/alt_flash_types.h diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/inc/sys/alt_irq.h b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/inc/sys/alt_irq.h similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/inc/sys/alt_irq.h rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/inc/sys/alt_irq.h diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/inc/sys/alt_irq_entry.h b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/inc/sys/alt_irq_entry.h similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/inc/sys/alt_irq_entry.h rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/inc/sys/alt_irq_entry.h diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/inc/sys/alt_license_reminder_ucosii.h b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/inc/sys/alt_license_reminder_ucosii.h similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/inc/sys/alt_license_reminder_ucosii.h rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/inc/sys/alt_license_reminder_ucosii.h diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/inc/sys/alt_llist.h b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/inc/sys/alt_llist.h similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/inc/sys/alt_llist.h rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/inc/sys/alt_llist.h diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/inc/sys/alt_load.h b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/inc/sys/alt_load.h similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/inc/sys/alt_load.h rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/inc/sys/alt_load.h diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/inc/sys/alt_log_printf.h b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/inc/sys/alt_log_printf.h similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/inc/sys/alt_log_printf.h rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/inc/sys/alt_log_printf.h diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/inc/sys/alt_set_args.h b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/inc/sys/alt_set_args.h similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/inc/sys/alt_set_args.h rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/inc/sys/alt_set_args.h diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/inc/sys/alt_sim.h b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/inc/sys/alt_sim.h similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/inc/sys/alt_sim.h rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/inc/sys/alt_sim.h diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/inc/sys/alt_stack.h b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/inc/sys/alt_stack.h similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/inc/sys/alt_stack.h rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/inc/sys/alt_stack.h diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/inc/sys/alt_stdio.h b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/inc/sys/alt_stdio.h similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/inc/sys/alt_stdio.h rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/inc/sys/alt_stdio.h diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/inc/sys/alt_sys_init.h b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/inc/sys/alt_sys_init.h similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/inc/sys/alt_sys_init.h rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/inc/sys/alt_sys_init.h diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/inc/sys/alt_sys_wrappers.h b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/inc/sys/alt_sys_wrappers.h similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/inc/sys/alt_sys_wrappers.h rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/inc/sys/alt_sys_wrappers.h diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/inc/sys/alt_timestamp.h b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/inc/sys/alt_timestamp.h similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/inc/sys/alt_timestamp.h rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/inc/sys/alt_timestamp.h diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/inc/sys/alt_warning.h b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/inc/sys/alt_warning.h similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/inc/sys/alt_warning.h rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/inc/sys/alt_warning.h diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/inc/sys/ioctl.h b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/inc/sys/ioctl.h similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/inc/sys/ioctl.h rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/inc/sys/ioctl.h diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/inc/sys/termios.h b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/inc/sys/termios.h similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/inc/sys/termios.h rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/inc/sys/termios.h diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_alarm_start.c b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_alarm_start.c similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_alarm_start.c rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_alarm_start.c diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_busy_sleep.c b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_busy_sleep.c similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_busy_sleep.c rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_busy_sleep.c diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_close.c b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_close.c similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_close.c rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_close.c diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_dcache_flush.c b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_dcache_flush.c similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_dcache_flush.c rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_dcache_flush.c diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_dcache_flush_all.c b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_dcache_flush_all.c similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_dcache_flush_all.c rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_dcache_flush_all.c diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_dcache_flush_no_writeback.c b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_dcache_flush_no_writeback.c similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_dcache_flush_no_writeback.c rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_dcache_flush_no_writeback.c diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_dev.c b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_dev.c similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_dev.c rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_dev.c diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_dev_llist_insert.c b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_dev_llist_insert.c similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_dev_llist_insert.c rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_dev_llist_insert.c diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_dma_rxchan_open.c b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_dma_rxchan_open.c similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_dma_rxchan_open.c rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_dma_rxchan_open.c diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_dma_txchan_open.c b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_dma_txchan_open.c similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_dma_txchan_open.c rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_dma_txchan_open.c diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_do_ctors.c b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_do_ctors.c similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_do_ctors.c rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_do_ctors.c diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_do_dtors.c b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_do_dtors.c similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_do_dtors.c rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_do_dtors.c diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_environ.c b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_environ.c similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_environ.c rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_environ.c diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_errno.c b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_errno.c similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_errno.c rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_errno.c diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_exception_entry.S b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_exception_entry.S similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_exception_entry.S rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_exception_entry.S diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_exception_muldiv.S b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_exception_muldiv.S similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_exception_muldiv.S rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_exception_muldiv.S diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_exception_trap.S b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_exception_trap.S similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_exception_trap.S rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_exception_trap.S diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_execve.c b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_execve.c similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_execve.c rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_execve.c diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_exit.c b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_exit.c similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_exit.c rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_exit.c diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_fcntl.c b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_fcntl.c similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_fcntl.c rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_fcntl.c diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_fd_lock.c b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_fd_lock.c similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_fd_lock.c rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_fd_lock.c diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_fd_unlock.c b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_fd_unlock.c similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_fd_unlock.c rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_fd_unlock.c diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_find_dev.c b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_find_dev.c similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_find_dev.c rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_find_dev.c diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_find_file.c b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_find_file.c similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_find_file.c rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_find_file.c diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_flash_dev.c b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_flash_dev.c similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_flash_dev.c rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_flash_dev.c diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_fork.c b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_fork.c similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_fork.c rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_fork.c diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_fs_reg.c b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_fs_reg.c similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_fs_reg.c rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_fs_reg.c diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_fstat.c b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_fstat.c similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_fstat.c rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_fstat.c diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_get_fd.c b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_get_fd.c similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_get_fd.c rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_get_fd.c diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_getchar.c b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_getchar.c similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_getchar.c rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_getchar.c diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_getpid.c b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_getpid.c similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_getpid.c rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_getpid.c diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_gettod.c b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_gettod.c similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_gettod.c rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_gettod.c diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_gmon.c b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_gmon.c similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_gmon.c rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_gmon.c diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_icache_flush.c b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_icache_flush.c similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_icache_flush.c rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_icache_flush.c diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_icache_flush_all.c b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_icache_flush_all.c similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_icache_flush_all.c rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_icache_flush_all.c diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_iic.c b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_iic.c similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_iic.c rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_iic.c diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_iic_isr_register.c b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_iic_isr_register.c similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_iic_isr_register.c rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_iic_isr_register.c diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_instruction_exception_entry.c b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_instruction_exception_entry.c similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_instruction_exception_entry.c rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_instruction_exception_entry.c diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_instruction_exception_register.c b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_instruction_exception_register.c similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_instruction_exception_register.c rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_instruction_exception_register.c diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_io_redirect.c b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_io_redirect.c similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_io_redirect.c rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_io_redirect.c diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_ioctl.c b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_ioctl.c similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_ioctl.c rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_ioctl.c diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_irq_entry.S b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_irq_entry.S similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_irq_entry.S rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_irq_entry.S diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_irq_handler.c b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_irq_handler.c similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_irq_handler.c rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_irq_handler.c diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_irq_register.c b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_irq_register.c similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_irq_register.c rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_irq_register.c diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_irq_vars.c b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_irq_vars.c similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_irq_vars.c rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_irq_vars.c diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_isatty.c b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_isatty.c similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_isatty.c rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_isatty.c diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_kill.c b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_kill.c similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_kill.c rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_kill.c diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_link.c b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_link.c similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_link.c rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_link.c diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_load.c b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_load.c similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_load.c rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_load.c diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_log_macro.S b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_log_macro.S similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_log_macro.S rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_log_macro.S diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_log_printf.c b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_log_printf.c similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_log_printf.c rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_log_printf.c diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_lseek.c b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_lseek.c similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_lseek.c rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_lseek.c diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_main.c b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_main.c similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_main.c rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_main.c diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_mcount.S b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_mcount.S similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_mcount.S rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_mcount.S diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_open.c b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_open.c similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_open.c rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_open.c diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_printf.c b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_printf.c similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_printf.c rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_printf.c diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_putchar.c b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_putchar.c similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_putchar.c rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_putchar.c diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_putstr.c b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_putstr.c similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_putstr.c rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_putstr.c diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_read.c b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_read.c similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_read.c rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_read.c diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_release_fd.c b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_release_fd.c similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_release_fd.c rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_release_fd.c diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_remap_cached.c b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_remap_cached.c similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_remap_cached.c rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_remap_cached.c diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_remap_uncached.c b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_remap_uncached.c similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_remap_uncached.c rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_remap_uncached.c diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_rename.c b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_rename.c similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_rename.c rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_rename.c diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_sbrk.c b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_sbrk.c similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_sbrk.c rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_sbrk.c diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_settod.c b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_settod.c similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_settod.c rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_settod.c diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_software_exception.S b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_software_exception.S similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_software_exception.S rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_software_exception.S diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_stat.c b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_stat.c similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_stat.c rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_stat.c diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_tick.c b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_tick.c similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_tick.c rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_tick.c diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_times.c b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_times.c similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_times.c rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_times.c diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_uncached_free.c b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_uncached_free.c similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_uncached_free.c rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_uncached_free.c diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_uncached_malloc.c b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_uncached_malloc.c similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_uncached_malloc.c rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_uncached_malloc.c diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_unlink.c b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_unlink.c similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_unlink.c rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_unlink.c diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_usleep.c b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_usleep.c similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_usleep.c rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_usleep.c diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_wait.c b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_wait.c similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_wait.c rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_wait.c diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_write.c b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_write.c similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/alt_write.c rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/alt_write.c diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/altera_nios2_qsys_irq.c b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/altera_nios2_qsys_irq.c similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/altera_nios2_qsys_irq.c rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/altera_nios2_qsys_irq.c diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/crt0.S b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/crt0.S similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/crt0.S rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/crt0.S diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/os_cpu_a.S b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/os_cpu_a.S similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/os_cpu_a.S rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/os_cpu_a.S diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/os_cpu_c.c b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/os_cpu_c.c similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/HAL/src/os_cpu_c.c rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/HAL/src/os_cpu_c.c diff --git a/MCTEST/DE0-nano-HD/Software/MCTest_bsp/Makefile b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/Makefile new file mode 100644 index 00000000..ae0e9d77 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/Makefile @@ -0,0 +1,813 @@ +#------------------------------------------------------------------------------ +# BSP MAKEFILE +# +# This makefile was automatically generated by the nios2-bsp-generate-files +# command. Its purpose is to build a custom Board Support Package (BSP) +# targeting a specific Nios II processor in an SOPC Builder-based design. +# +# To create an application or library Makefile which uses this BSP, try the +# nios2-app-generate-makefile or nios2-lib-generate-makefile commands. +#------------------------------------------------------------------------------ + +#------------------------------------------------------------------------------ +# TOOLS +#------------------------------------------------------------------------------ + +MKDIR := mkdir -p +ECHO := echo +SPACE := $(empty) $(empty) + +#------------------------------------------------------------------------------ +# The adjust-path macro +# +# If COMSPEC is defined, Make is launched from Windows through +# Cygwin. This adjust-path macro will call 'cygpath -u' on all +# paths to ensure they are readable by Make. +# +# If COMSPEC is not defined, Make is launched from *nix, and no adjustment +# is necessary +#------------------------------------------------------------------------------ + +ifndef COMSPEC +ifdef ComSpec +COMSPEC = $(ComSpec) +endif # ComSpec +endif # !COMSPEC + +ifdef COMSPEC + adjust-path = $(subst $(SPACE),\$(SPACE),$(shell cygpath -u "$1")) + adjust-path-mixed = $(subst $(SPACE),\$(SPACE),$(shell cygpath -m "$1")) +else + adjust-path = $(subst $(SPACE),\$(SPACE),$1) + adjust-path-mixed = $(subst $(SPACE),\$(SPACE),$1) +endif + +#------------------------------------------------------------------------------ +# DEFAULT TARGET +# +# The default target, "all", must appear before any other target in the +# Makefile. Note that extra prerequisites are added to the "all" rule later. +#------------------------------------------------------------------------------ +.PHONY: all +all: + @$(ECHO) [BSP build complete] + + +#------------------------------------------------------------------------------ +# PATHS & DIRECTORY NAMES +# +# Explicitly locate absolute path of the BSP root +#------------------------------------------------------------------------------ + +BSP_ROOT_DIR := . + +# Define absolute path to the root of the BSP. +ABS_BSP_ROOT := $(call adjust-path-mixed,$(shell pwd)) + +# Stash all BSP object files here +OBJ_DIR := ./obj + + +#------------------------------------------------------------------------------ +# MANAGED CONTENT +# +# All content between the lines "START MANAGED" and "END MANAGED" below is +# generated based on variables in the BSP settings file when the +# nios2-bsp-generate-files command is invoked. If you wish to persist any +# information pertaining to the build process, it is recomended that you +# utilize the BSP settings mechanism to do so. +# +# Note that most variable assignments in this section have a corresponding BSP +# setting that can be changed by using the nios2-bsp-create-settings or +# nios2-bsp-update-settings command before nios2-bsp-generate-files; if you +# want any variable set to a specific value when this Makefile is re-generated +# (to prevent hand-edits from being over-written), use the BSP settings +# facilities above. +#------------------------------------------------------------------------------ + +#START MANAGED + +# The following TYPE comment allows tools to identify the 'type' of target this +# makefile is associated with. +# TYPE: BSP_PRIVATE_MAKEFILE + +# This following VERSION comment indicates the version of the tool used to +# generate this makefile. A makefile variable is provided for VERSION as well. +# ACDS_VERSION: 12.1sp1 +ACDS_VERSION := 12.1sp1 + +# This following BUILD_NUMBER comment indicates the build number of the tool +# used to generate this makefile. +# BUILD_NUMBER: 243 + +SETTINGS_FILE := settings.bsp +SOPC_FILE := C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo + +#------------------------------------------------------------------------------- +# TOOL & COMMAND DEFINITIONS +# +# The base command for each build operation are expressed here. Additional +# switches may be expressed here. They will run for all instances of the +# utility. +#------------------------------------------------------------------------------- + +# Archiver command. Creates library files. +AR = nios2-elf-ar + +# Assembler command. Note that CC is used for .S files. +AS = nios2-elf-gcc + +# Custom flags only passed to the archiver. This content of this variable is +# directly passed to the archiver rather than the more standard "ARFLAGS". The +# reason for this is that GNU Make assumes some default content in ARFLAGS. +# This setting defines the value of BSP_ARFLAGS in Makefile. +BSP_ARFLAGS = -src + +# Custom flags only passed to the assembler. This setting defines the value of +# BSP_ASFLAGS in Makefile. +BSP_ASFLAGS = -Wa,-gdwarf2 + +# C/C++ compiler debug level. '-g' provides the default set of debug symbols +# typically required to debug a typical application. Omitting '-g' removes +# debug symbols from the ELF. This setting defines the value of +# BSP_CFLAGS_DEBUG in Makefile. +BSP_CFLAGS_DEBUG = -g + +# C/C++ compiler optimization level. "-O0" = no optimization,"-O2" = "normal" +# optimization, etc. "-O0" is recommended for code that you want to debug since +# compiler optimization can remove variables and produce non-sequential +# execution of code while debugging. This setting defines the value of +# BSP_CFLAGS_OPTIMIZATION in Makefile. +BSP_CFLAGS_OPTIMIZATION = -O0 + +# C/C++ compiler warning level. "-Wall" is commonly used.This setting defines +# the value of BSP_CFLAGS_WARNINGS in Makefile. +BSP_CFLAGS_WARNINGS = -Wall + +# C compiler command. +CC = nios2-elf-gcc -xc + +# C++ compiler command. +CXX = nios2-elf-gcc -xc++ + +# Command used to remove files during 'clean' target. +RM = rm -f + + +#------------------------------------------------------------------------------- +# BUILD PRE & POST PROCESS COMMANDS +# +# The following variables are treated as shell commands in the rule +# definitions for each file-type associated with the BSP build, as well as +# commands run at the beginning and end of the entire BSP build operation. +# Pre-process commands are executed before the relevant command (for example, +# a command defined in the "CC_PRE_PROCESS" variable executes before the C +# compiler for building .c files), while post-process commands are executed +# immediately afterwards. +# +# You can view each pre/post-process command in the "Build Rules: All & +# Clean", "Pattern Rules to Build Objects", and "Library Rules" sections of +# this Makefile. +#------------------------------------------------------------------------------- + + +#------------------------------------------------------------------------------- +# BSP SOURCE BUILD SETTINGS (FLAG GENERATION) +# +# Software build settings such as compiler optimization, debug level, warning +# flags, etc., may be defined in the following variables. The variables below +# are concatenated together in the 'Flags' section of this Makefile to form +# final variables of flags passed to the build tools. +# +# These settings are considered private to the BSP and apply to all library & +# driver files in it; they do NOT automatically propagate to, for example, the +# build settings for an application. +# # For additional detail and syntax requirements, please refer to GCC help +# (example: "nios2-elf-gcc --help --verbose"). +# +# Unless indicated otherwise, multiple entries in each variable should be +# space-separated. +#------------------------------------------------------------------------------- + +# Altera HAL alt_sys_init.c generated source file +GENERATED_C_FILES := $(ABS_BSP_ROOT)/alt_sys_init.c +GENERATED_C_LIB_SRCS += alt_sys_init.c + + +#------------------------------------------------------------------------------- +# BSP SOURCE FILE LISTING +# +# All source files that comprise the BSP are listed here, along with path +# information to each file expressed relative to the BSP root. The precise +# list and location of each file is derived from the driver, operating system, +# or software package source file declarations. +# +# Following specification of the source files for each component, driver, etc., +# each source file type (C, assembly, etc.) is concatenated together and used +# to construct a list of objects. Pattern rules to build each object are then +# used to build each file. +#------------------------------------------------------------------------------- + +# altera_avalon_jtag_uart_driver sources root +altera_avalon_jtag_uart_driver_SRCS_ROOT := drivers + +# altera_avalon_jtag_uart_driver sources +altera_avalon_jtag_uart_driver_C_LIB_SRCS := \ + $(altera_avalon_jtag_uart_driver_SRCS_ROOT)/src/altera_avalon_jtag_uart_init.c \ + $(altera_avalon_jtag_uart_driver_SRCS_ROOT)/src/altera_avalon_jtag_uart_read.c \ + $(altera_avalon_jtag_uart_driver_SRCS_ROOT)/src/altera_avalon_jtag_uart_write.c \ + $(altera_avalon_jtag_uart_driver_SRCS_ROOT)/src/altera_avalon_jtag_uart_ioctl.c \ + $(altera_avalon_jtag_uart_driver_SRCS_ROOT)/src/altera_avalon_jtag_uart_fd.c + +# altera_avalon_pio_driver sources root +altera_avalon_pio_driver_SRCS_ROOT := drivers + +# altera_avalon_pio_driver sources +# altera_avalon_sysid_qsys_driver sources root +altera_avalon_sysid_qsys_driver_SRCS_ROOT := drivers + +# altera_avalon_sysid_qsys_driver sources +altera_avalon_sysid_qsys_driver_C_LIB_SRCS := \ + $(altera_avalon_sysid_qsys_driver_SRCS_ROOT)/src/altera_avalon_sysid_qsys.c + +# altera_avalon_timer_driver sources root +altera_avalon_timer_driver_SRCS_ROOT := drivers + +# altera_avalon_timer_driver sources +altera_avalon_timer_driver_C_LIB_SRCS := \ + $(altera_avalon_timer_driver_SRCS_ROOT)/src/altera_avalon_timer_sc.c \ + $(altera_avalon_timer_driver_SRCS_ROOT)/src/altera_avalon_timer_ts.c \ + $(altera_avalon_timer_driver_SRCS_ROOT)/src/altera_avalon_timer_vars.c + +# altera_avalon_uart_driver sources root +altera_avalon_uart_driver_SRCS_ROOT := drivers + +# altera_avalon_uart_driver sources +altera_avalon_uart_driver_C_LIB_SRCS := \ + $(altera_avalon_uart_driver_SRCS_ROOT)/src/altera_avalon_uart_fd.c \ + $(altera_avalon_uart_driver_SRCS_ROOT)/src/altera_avalon_uart_init.c \ + $(altera_avalon_uart_driver_SRCS_ROOT)/src/altera_avalon_uart_ioctl.c \ + $(altera_avalon_uart_driver_SRCS_ROOT)/src/altera_avalon_uart_read.c \ + $(altera_avalon_uart_driver_SRCS_ROOT)/src/altera_avalon_uart_write.c + +# altera_nios2_qsys_ucosii_driver sources root +altera_nios2_qsys_ucosii_driver_SRCS_ROOT := HAL + +# altera_nios2_qsys_ucosii_driver sources +altera_nios2_qsys_ucosii_driver_C_LIB_SRCS := \ + $(altera_nios2_qsys_ucosii_driver_SRCS_ROOT)/src/altera_nios2_qsys_irq.c \ + $(altera_nios2_qsys_ucosii_driver_SRCS_ROOT)/src/alt_busy_sleep.c \ + $(altera_nios2_qsys_ucosii_driver_SRCS_ROOT)/src/alt_irq_vars.c \ + $(altera_nios2_qsys_ucosii_driver_SRCS_ROOT)/src/alt_icache_flush.c \ + $(altera_nios2_qsys_ucosii_driver_SRCS_ROOT)/src/alt_icache_flush_all.c \ + $(altera_nios2_qsys_ucosii_driver_SRCS_ROOT)/src/alt_dcache_flush.c \ + $(altera_nios2_qsys_ucosii_driver_SRCS_ROOT)/src/alt_dcache_flush_all.c \ + $(altera_nios2_qsys_ucosii_driver_SRCS_ROOT)/src/alt_dcache_flush_no_writeback.c \ + $(altera_nios2_qsys_ucosii_driver_SRCS_ROOT)/src/alt_instruction_exception_entry.c \ + $(altera_nios2_qsys_ucosii_driver_SRCS_ROOT)/src/alt_irq_register.c \ + $(altera_nios2_qsys_ucosii_driver_SRCS_ROOT)/src/alt_iic.c \ + $(altera_nios2_qsys_ucosii_driver_SRCS_ROOT)/src/alt_remap_cached.c \ + $(altera_nios2_qsys_ucosii_driver_SRCS_ROOT)/src/alt_remap_uncached.c \ + $(altera_nios2_qsys_ucosii_driver_SRCS_ROOT)/src/alt_uncached_free.c \ + $(altera_nios2_qsys_ucosii_driver_SRCS_ROOT)/src/alt_uncached_malloc.c \ + $(altera_nios2_qsys_ucosii_driver_SRCS_ROOT)/src/alt_do_ctors.c \ + $(altera_nios2_qsys_ucosii_driver_SRCS_ROOT)/src/alt_do_dtors.c \ + $(altera_nios2_qsys_ucosii_driver_SRCS_ROOT)/src/alt_gmon.c \ + $(altera_nios2_qsys_ucosii_driver_SRCS_ROOT)/src/alt_usleep.c \ + $(altera_nios2_qsys_ucosii_driver_SRCS_ROOT)/src/os_cpu_c.c + +altera_nios2_qsys_ucosii_driver_ASM_LIB_SRCS := \ + $(altera_nios2_qsys_ucosii_driver_SRCS_ROOT)/src/alt_exception_entry.S \ + $(altera_nios2_qsys_ucosii_driver_SRCS_ROOT)/src/alt_exception_trap.S \ + $(altera_nios2_qsys_ucosii_driver_SRCS_ROOT)/src/alt_exception_muldiv.S \ + $(altera_nios2_qsys_ucosii_driver_SRCS_ROOT)/src/alt_irq_entry.S \ + $(altera_nios2_qsys_ucosii_driver_SRCS_ROOT)/src/alt_software_exception.S \ + $(altera_nios2_qsys_ucosii_driver_SRCS_ROOT)/src/alt_mcount.S \ + $(altera_nios2_qsys_ucosii_driver_SRCS_ROOT)/src/alt_log_macro.S \ + $(altera_nios2_qsys_ucosii_driver_SRCS_ROOT)/src/crt0.S \ + $(altera_nios2_qsys_ucosii_driver_SRCS_ROOT)/src/os_cpu_a.S + +# hal sources root +hal_SRCS_ROOT := HAL + +# hal sources +hal_C_LIB_SRCS := \ + $(hal_SRCS_ROOT)/src/alt_alarm_start.c \ + $(hal_SRCS_ROOT)/src/alt_close.c \ + $(hal_SRCS_ROOT)/src/alt_dev.c \ + $(hal_SRCS_ROOT)/src/alt_dev_llist_insert.c \ + $(hal_SRCS_ROOT)/src/alt_dma_rxchan_open.c \ + $(hal_SRCS_ROOT)/src/alt_dma_txchan_open.c \ + $(hal_SRCS_ROOT)/src/alt_environ.c \ + $(hal_SRCS_ROOT)/src/alt_errno.c \ + $(hal_SRCS_ROOT)/src/alt_execve.c \ + $(hal_SRCS_ROOT)/src/alt_exit.c \ + $(hal_SRCS_ROOT)/src/alt_fcntl.c \ + $(hal_SRCS_ROOT)/src/alt_fd_lock.c \ + $(hal_SRCS_ROOT)/src/alt_fd_unlock.c \ + $(hal_SRCS_ROOT)/src/alt_find_dev.c \ + $(hal_SRCS_ROOT)/src/alt_find_file.c \ + $(hal_SRCS_ROOT)/src/alt_flash_dev.c \ + $(hal_SRCS_ROOT)/src/alt_fork.c \ + $(hal_SRCS_ROOT)/src/alt_fs_reg.c \ + $(hal_SRCS_ROOT)/src/alt_fstat.c \ + $(hal_SRCS_ROOT)/src/alt_get_fd.c \ + $(hal_SRCS_ROOT)/src/alt_getchar.c \ + $(hal_SRCS_ROOT)/src/alt_getpid.c \ + $(hal_SRCS_ROOT)/src/alt_gettod.c \ + $(hal_SRCS_ROOT)/src/alt_iic_isr_register.c \ + $(hal_SRCS_ROOT)/src/alt_instruction_exception_register.c \ + $(hal_SRCS_ROOT)/src/alt_ioctl.c \ + $(hal_SRCS_ROOT)/src/alt_io_redirect.c \ + $(hal_SRCS_ROOT)/src/alt_irq_handler.c \ + $(hal_SRCS_ROOT)/src/alt_isatty.c \ + $(hal_SRCS_ROOT)/src/alt_kill.c \ + $(hal_SRCS_ROOT)/src/alt_link.c \ + $(hal_SRCS_ROOT)/src/alt_load.c \ + $(hal_SRCS_ROOT)/src/alt_log_printf.c \ + $(hal_SRCS_ROOT)/src/alt_lseek.c \ + $(hal_SRCS_ROOT)/src/alt_main.c \ + $(hal_SRCS_ROOT)/src/alt_open.c \ + $(hal_SRCS_ROOT)/src/alt_printf.c \ + $(hal_SRCS_ROOT)/src/alt_putchar.c \ + $(hal_SRCS_ROOT)/src/alt_putstr.c \ + $(hal_SRCS_ROOT)/src/alt_read.c \ + $(hal_SRCS_ROOT)/src/alt_release_fd.c \ + $(hal_SRCS_ROOT)/src/alt_rename.c \ + $(hal_SRCS_ROOT)/src/alt_sbrk.c \ + $(hal_SRCS_ROOT)/src/alt_settod.c \ + $(hal_SRCS_ROOT)/src/alt_stat.c \ + $(hal_SRCS_ROOT)/src/alt_tick.c \ + $(hal_SRCS_ROOT)/src/alt_times.c \ + $(hal_SRCS_ROOT)/src/alt_unlink.c \ + $(hal_SRCS_ROOT)/src/alt_wait.c \ + $(hal_SRCS_ROOT)/src/alt_write.c + +# ucosii sources root +ucosii_SRCS_ROOT := UCOSII + +# ucosii sources +ucosii_C_LIB_SRCS := \ + $(ucosii_SRCS_ROOT)/src/alt_env_lock.c \ + $(ucosii_SRCS_ROOT)/src/alt_malloc_lock.c \ + $(ucosii_SRCS_ROOT)/src/os_core.c \ + $(ucosii_SRCS_ROOT)/src/os_dbg.c \ + $(ucosii_SRCS_ROOT)/src/os_flag.c \ + $(ucosii_SRCS_ROOT)/src/os_mbox.c \ + $(ucosii_SRCS_ROOT)/src/os_mem.c \ + $(ucosii_SRCS_ROOT)/src/os_mutex.c \ + $(ucosii_SRCS_ROOT)/src/os_q.c \ + $(ucosii_SRCS_ROOT)/src/os_sem.c \ + $(ucosii_SRCS_ROOT)/src/os_task.c \ + $(ucosii_SRCS_ROOT)/src/os_time.c \ + $(ucosii_SRCS_ROOT)/src/os_tmr.c + +# up_avalon_rs232_driver sources root +up_avalon_rs232_driver_SRCS_ROOT := drivers + +# up_avalon_rs232_driver sources +up_avalon_rs232_driver_C_LIB_SRCS := \ + $(up_avalon_rs232_driver_SRCS_ROOT)/src/altera_up_avalon_rs232.c + + +# Assemble all component C source files +COMPONENT_C_LIB_SRCS += \ + $(altera_avalon_jtag_uart_driver_C_LIB_SRCS) \ + $(altera_avalon_sysid_qsys_driver_C_LIB_SRCS) \ + $(altera_avalon_timer_driver_C_LIB_SRCS) \ + $(altera_avalon_uart_driver_C_LIB_SRCS) \ + $(altera_nios2_qsys_ucosii_driver_C_LIB_SRCS) \ + $(hal_C_LIB_SRCS) \ + $(ucosii_C_LIB_SRCS) \ + $(up_avalon_rs232_driver_C_LIB_SRCS) + +# Assemble all component assembly source files +COMPONENT_ASM_LIB_SRCS += \ + $(altera_nios2_qsys_ucosii_driver_ASM_LIB_SRCS) + +# Assemble all component C++ source files +COMPONENT_CPP_LIB_SRCS += \ + +#END MANAGED + +#------------------------------------------------------------------------------ +# PUBLIC.MK +# +# The generated public.mk file contains BSP information that is shared with +# other external makefiles, such as a Nios II application makefile. System- +# dependent information such as hardware-specific compiler flags and +# simulation file generation are stored here. +# +# In addition, public.mk contains include paths that various software, +# such as a device driver, may need for the C compiler. These paths are +# written to public.mk with respect to the BSP root. In public.mk, each +# path is prefixed with a special variable, $(ALT_LIBRARY_ROOT_DIR). The +# purpose of this variable is to allow an external Makefile to append on +# path information to precisely locate paths expressed in public.mk +# Since this is the BSP Makefile, we set ALT_LIBRARY_ROOT_DIR to point right +# here ("."), at the BSP root. +# +# ALT_LIBRARY_ROOT_DIR must always be set before public.mk is included. +#------------------------------------------------------------------------------ +ALT_LIBRARY_ROOT_DIR := . +include public.mk + + +#------------------------------------------------------------------------------ +# FLAGS +# +# Include paths for BSP files are written into the public.mk file and must +# be added to the existing list of pre-processor flags. In addition, "hooks" +# for standard flags left intentionally empty (CFLAGS, CPPFLAGS, ASFLAGS, +# and CXXFLAGS) are provided for conveniently adding to the relevant flags +# on the command-line or via script that calls make. +#------------------------------------------------------------------------------ +# Assemble final list of compiler flags from generated content +BSP_CFLAGS += \ + $(BSP_CFLAGS_DEFINED_SYMBOLS) \ + $(BSP_CFLAGS_UNDEFINED_SYMBOLS) \ + $(BSP_CFLAGS_OPTIMIZATION) \ + $(BSP_CFLAGS_DEBUG) \ + $(BSP_CFLAGS_WARNINGS) \ + $(BSP_CFLAGS_USER_FLAGS) \ + $(ALT_CFLAGS) \ + $(CFLAGS) + +# Make ready the final list of include directories and other C pre-processor +# flags. Each include path is made ready by prefixing it with "-I". +BSP_CPPFLAGS += \ + $(addprefix -I, $(BSP_INC_DIRS)) \ + $(addprefix -I, $(ALT_INCLUDE_DIRS)) \ + $(ALT_CPPFLAGS) \ + $(CPPFLAGS) + +# Finish off assembler flags with any user-provided flags +BSP_ASFLAGS += $(ASFLAGS) + +# Finish off C++ flags with any user-provided flags +BSP_CXXFLAGS += $(CXXFLAGS) + +# And finally, the ordered list +C_SRCS += $(GENERATED_C_LIB_SRCS) \ + $(COMPONENT_C_LIB_SRCS) + +CXX_SRCS += $(GENERATED_CPP_LIB_SRCS) \ + $(COMPONENT_CPP_LIB_SRCS) + +ASM_SRCS += $(GENERATED_ASM_LIB_SRCS) \ + $(COMPONENT_ASM_LIB_SRCS) + + +#------------------------------------------------------------------------------ +# LIST OF GENERATED FILES +# +# A Nios II BSP relies on the generation of several source files used +# by both the BSP and any applications referencing the BSP. +#------------------------------------------------------------------------------ + + +GENERATED_H_FILES := $(ABS_BSP_ROOT)/system.h + +GENERATED_LINKER_SCRIPT := $(ABS_BSP_ROOT)/linker.x + +GENERATED_FILES += $(GENERATED_H_FILES) \ + $(GENERATED_LINKER_SCRIPT) + + +#------------------------------------------------------------------------------ +# SETUP TO BUILD OBJECTS +# +# List of object files which are to be built. This is constructed from the input +# list of C source files (C_SRCS), C++ source files (CXX_SRCS), and assembler +# source file (ASM_SRCS). The permitted file extensions are: +# +# .c .C - for C files +# .cxx .cc .cpp .CXX .CC .CPP - for C++ files +# .S .s - for assembly files +# +# Extended description: The list of objects is a sorted list (duplicates +# removed) of all possible objects, placed beneath the ./obj directory, +# including any path information stored in the "*_SRCS" variable. The +# "patsubst" commands are used to concatenate together multiple file suffix +# types for common files (i.e. c++ as .cxx, .cc, .cpp). +# +# File extensions are case-insensitive in build rules with the exception of +# assembly sources. Nios II assembly sources with the ".S" extension are first +# run through the C preprocessor. Sources with the ".s" extension are not. +#------------------------------------------------------------------------------ +OBJS = $(sort $(addprefix $(OBJ_DIR)/, \ + $(patsubst %.c, %.o, $(patsubst %.C, %.o, $(C_SRCS))) \ + $(patsubst %.cxx, %.o, $(patsubst %.CXX, %.o, \ + $(patsubst %.cc, %.o, $(patsubst %.CC, %.o, \ + $(patsubst %.cpp, %.o, $(patsubst %.CPP, %.o, \ + $(CXX_SRCS) )))))) \ + $(patsubst %.S, %.o, $(patsubst %.s, %.o, $(ASM_SRCS))) )) + +# List of dependancy files for each object file. +DEPS = $(OBJS:.o=.d) + + +# Rules to force your project to rebuild or relink +# .force_relink file will cause any application that depends on this project to relink +# .force_rebuild file will cause this project to rebuild object files +# .force_rebuild_all file will cause this project and any project that depends on this project to rebuild object files + +FORCE_RELINK_DEP := .force_relink +FORCE_REBUILD_DEP := .force_rebuild +FORCE_REBUILD_ALL_DEP := .force_rebuild_all +FORCE_REBUILD_DEP_LIST := $(FORCE_RELINK_DEP) $(FORCE_REBUILD_DEP) $(FORCE_REBUILD_ALL_DEP) + +$(FORCE_REBUILD_DEP_LIST): + +$(OBJS): $(wildcard $(FORCE_REBUILD_DEP)) $(wildcard $(FORCE_REBUILD_ALL_DEP)) + + +#------------------------------------------------------------------------------ +# BUILD RULES: ALL & CLEAN +#------------------------------------------------------------------------------ +.DELETE_ON_ERROR: + +.PHONY: all +all: build_pre_process +all: Makefile $(GENERATED_FILES) $(BSP_LIB) $(NEWLIB_DIR) +all: build_post_process + + +# clean: remove .o/.a/.d +.PHONY: clean +clean: + @$(RM) -r $(BSP_LIB) $(OBJ_DIR) $(FORCE_REBUILD_DEP_LIST) +ifneq ($(wildcard $(NEWLIB_DIR)),) + @$(RM) -r $(NEWLIB_DIR) +endif + @$(ECHO) [BSP clean complete] + + +#------------------------------------------------------------------------------ +# BUILD PRE/POST PROCESS +#------------------------------------------------------------------------------ +build_pre_process : + $(BUILD_PRE_PROCESS) + +build_post_process : + $(BUILD_POST_PROCESS) + +.PHONY: build_pre_process build_post_process + + + +#------------------------------------------------------------------------------ +# MAKEFILE UP TO DATE? +# +# Is this very Makefile up to date? Someone may have changed the BSP settings +# file or the associated target hardware. +#------------------------------------------------------------------------------ +# Skip this check when clean is the only target +ifneq ($(MAKECMDGOALS),clean) + +ifneq ($(wildcard $(SETTINGS_FILE)),$(SETTINGS_FILE)) +$(warning Warning: BSP Settings File $(SETTINGS_FILE) could not be found.) +endif + +Makefile: $(wildcard $(SETTINGS_FILE)) + @$(ECHO) Makefile not up to date. + @$(ECHO) $(SETTINGS_FILE) has been modified since the BSP Makefile was generated. + @$(ECHO) + @$(ECHO) Generate the BSP to update the Makefile, and then build again. + @$(ECHO) + @$(ECHO) To generate from Eclipse: + @$(ECHO) " 1. Right-click the BSP project." + @$(ECHO) " 2. In the Nios II Menu, click Generate BSP." + @$(ECHO) + @$(ECHO) To generate from the command line: + @$(ECHO) " nios2-bsp-generate-files --settings= --bsp-dir=" + @$(ECHO) + @exit 1 + +ifneq ($(wildcard $(SOPC_FILE)),$(SOPC_FILE)) +$(warning Warning: SOPC File $(SOPC_FILE) could not be found.) +endif + +public.mk: $(wildcard $(SOPC_FILE)) + @$(ECHO) Makefile not up to date. + @$(ECHO) $(SOPC_FILE) has been modified since the BSP was generated. + @$(ECHO) + @$(ECHO) Generate the BSP to update the Makefile, and then build again. + @$(ECHO) + @$(ECHO) To generate from Eclipse: + @$(ECHO) " 1. Right-click the BSP project." + @$(ECHO) " 2. In the Nios II Menu, click Generate BSP." + @$(ECHO) + @$(ECHO) To generate from the command line: + @$(ECHO) " nios2-bsp-generate-files --settings= --bsp-dir=" + @$(ECHO) + @exit 1 + +endif # $(MAKECMDGOALS) != clean + +#------------------------------------------------------------------------------ +# PATTERN RULES TO BUILD OBJECTS +#------------------------------------------------------------------------------ +$(OBJ_DIR)/%.o: %.c + @$(ECHO) Compiling $( + +/* + * Device headers + */ + +#include "altera_nios2_qsys_irq.h" +#include "altera_avalon_jtag_uart.h" +#include "altera_avalon_sysid_qsys.h" +#include "altera_avalon_timer.h" +#include "altera_avalon_uart.h" +#include "altera_up_avalon_rs232.h" + +/* + * Allocate the device storage + */ + +ALTERA_NIOS2_QSYS_IRQ_INSTANCE ( CPU, cpu); +ALTERA_AVALON_JTAG_UART_INSTANCE ( JTAG_UART_0, jtag_uart_0); +ALTERA_AVALON_SYSID_QSYS_INSTANCE ( SYSID, sysid); +ALTERA_AVALON_TIMER_INSTANCE ( SYS_CLK_TIMER, sys_clk_timer); +ALTERA_AVALON_UART_INSTANCE ( UART_0, uart_0); +ALTERA_UP_AVALON_RS232_INSTANCE ( RS232_MOTOR, rs232_motor); + +/* + * Initialize the interrupt controller devices + * and then enable interrupts in the CPU. + * Called before alt_sys_init(). + * The "base" parameter is ignored and only + * present for backwards-compatibility. + */ + +void alt_irq_init ( const void* base ) +{ + ALTERA_NIOS2_QSYS_IRQ_INIT ( CPU, cpu); + alt_irq_cpu_enable_interrupts(); +} + +/* + * Initialize the non-interrupt controller devices. + * Called after alt_irq_init(). + */ + +void alt_sys_init( void ) +{ + ALTERA_AVALON_TIMER_INIT ( SYS_CLK_TIMER, sys_clk_timer); + ALTERA_AVALON_JTAG_UART_INIT ( JTAG_UART_0, jtag_uart_0); + ALTERA_AVALON_SYSID_QSYS_INIT ( SYSID, sysid); + ALTERA_AVALON_UART_INIT ( UART_0, uart_0); + ALTERA_UP_AVALON_RS232_INIT ( RS232_MOTOR, rs232_motor); +} diff --git a/MCTEST/DE0-nano-HD/Software/MCTest_bsp/create-this-bsp b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/create-this-bsp new file mode 100644 index 00000000..de0ff276 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/create-this-bsp @@ -0,0 +1,49 @@ +#!/bin/bash +# +# This script creates the ucosii_net_zipfs Board Support Package (BSP). + +BSP_TYPE=ucosii +BSP_DIR=. +SOPC_DIR=../../ +SOPC_FILE=C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo +NIOS2_BSP_ARGS="" +CPU_NAME= + + +# Don't run make if create-this-app script is called with --no-make arg +SKIP_MAKE= +while [ $# -gt 0 ] +do + case "$1" in + --no-make) + SKIP_MAKE=1 + ;; + *) + NIOS2_BSP_ARGS="$NIOS2_BSP_ARGS $1" + ;; + esac + shift +done + + +# Run nios2-bsp utility to create a ucosii BSP in this directory +# for the system with a .sopc file in $SOPC_FILE. +# Deprecating $SOPC_DIR in 10.1. Multiple .sopcinfo files in a directory may exist. + +if [ -z "$SOPC_FILE" ]; then + echo "WARNING: Use of a directory for locating a .sopcinfo file is deprecated in 10.1. Multiple .sopcinfo files may exist. You must specify the full .sopcinfo path." + cmd="nios2-bsp $BSP_TYPE $BSP_DIR $SOPC_DIR $NIOS2_BSP_ARGS $CPU_NAME" +else + cmd="nios2-bsp $BSP_TYPE $BSP_DIR $SOPC_FILE $NIOS2_BSP_ARGS $CPU_NAME" +fi + + +echo "create-this-bsp: Running \"$cmd\"" +$cmd || { + echo "$cmd failed" + exit 1 +} +if [ -z "$SKIP_MAKE" ]; then + echo "create-this-bsp: Running make" + make +fi diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/drivers/inc/altera_avalon_jtag_uart.h b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/drivers/inc/altera_avalon_jtag_uart.h similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/drivers/inc/altera_avalon_jtag_uart.h rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/drivers/inc/altera_avalon_jtag_uart.h diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/drivers/inc/altera_avalon_jtag_uart_fd.h b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/drivers/inc/altera_avalon_jtag_uart_fd.h similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/drivers/inc/altera_avalon_jtag_uart_fd.h rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/drivers/inc/altera_avalon_jtag_uart_fd.h diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/drivers/inc/altera_avalon_jtag_uart_regs.h b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/drivers/inc/altera_avalon_jtag_uart_regs.h similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/drivers/inc/altera_avalon_jtag_uart_regs.h rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/drivers/inc/altera_avalon_jtag_uart_regs.h diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/drivers/inc/altera_avalon_pio_regs.h b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/drivers/inc/altera_avalon_pio_regs.h similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/drivers/inc/altera_avalon_pio_regs.h rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/drivers/inc/altera_avalon_pio_regs.h diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/drivers/inc/altera_avalon_sysid_qsys.h b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/drivers/inc/altera_avalon_sysid_qsys.h similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/drivers/inc/altera_avalon_sysid_qsys.h rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/drivers/inc/altera_avalon_sysid_qsys.h diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/drivers/inc/altera_avalon_sysid_qsys_regs.h b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/drivers/inc/altera_avalon_sysid_qsys_regs.h similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/drivers/inc/altera_avalon_sysid_qsys_regs.h rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/drivers/inc/altera_avalon_sysid_qsys_regs.h diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/drivers/inc/altera_avalon_timer.h b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/drivers/inc/altera_avalon_timer.h similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/drivers/inc/altera_avalon_timer.h rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/drivers/inc/altera_avalon_timer.h diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/drivers/inc/altera_avalon_timer_regs.h b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/drivers/inc/altera_avalon_timer_regs.h similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/drivers/inc/altera_avalon_timer_regs.h rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/drivers/inc/altera_avalon_timer_regs.h diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/drivers/inc/altera_avalon_uart.h b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/drivers/inc/altera_avalon_uart.h similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/drivers/inc/altera_avalon_uart.h rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/drivers/inc/altera_avalon_uart.h diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/drivers/inc/altera_avalon_uart_fd.h b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/drivers/inc/altera_avalon_uart_fd.h similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/drivers/inc/altera_avalon_uart_fd.h rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/drivers/inc/altera_avalon_uart_fd.h diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/drivers/inc/altera_avalon_uart_regs.h b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/drivers/inc/altera_avalon_uart_regs.h similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/drivers/inc/altera_avalon_uart_regs.h rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/drivers/inc/altera_avalon_uart_regs.h diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/drivers/inc/altera_up_avalon_rs232.h b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/drivers/inc/altera_up_avalon_rs232.h similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/drivers/inc/altera_up_avalon_rs232.h rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/drivers/inc/altera_up_avalon_rs232.h diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/drivers/inc/altera_up_avalon_rs232_regs.h b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/drivers/inc/altera_up_avalon_rs232_regs.h similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/drivers/inc/altera_up_avalon_rs232_regs.h rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/drivers/inc/altera_up_avalon_rs232_regs.h diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/drivers/src/altera_avalon_jtag_uart_fd.c b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/drivers/src/altera_avalon_jtag_uart_fd.c similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/drivers/src/altera_avalon_jtag_uart_fd.c rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/drivers/src/altera_avalon_jtag_uart_fd.c diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/drivers/src/altera_avalon_jtag_uart_init.c b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/drivers/src/altera_avalon_jtag_uart_init.c similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/drivers/src/altera_avalon_jtag_uart_init.c rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/drivers/src/altera_avalon_jtag_uart_init.c diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/drivers/src/altera_avalon_jtag_uart_ioctl.c b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/drivers/src/altera_avalon_jtag_uart_ioctl.c similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/drivers/src/altera_avalon_jtag_uart_ioctl.c rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/drivers/src/altera_avalon_jtag_uart_ioctl.c diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/drivers/src/altera_avalon_jtag_uart_read.c b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/drivers/src/altera_avalon_jtag_uart_read.c similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/drivers/src/altera_avalon_jtag_uart_read.c rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/drivers/src/altera_avalon_jtag_uart_read.c diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/drivers/src/altera_avalon_jtag_uart_write.c b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/drivers/src/altera_avalon_jtag_uart_write.c similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/drivers/src/altera_avalon_jtag_uart_write.c rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/drivers/src/altera_avalon_jtag_uart_write.c diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/drivers/src/altera_avalon_sysid_qsys.c b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/drivers/src/altera_avalon_sysid_qsys.c similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/drivers/src/altera_avalon_sysid_qsys.c rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/drivers/src/altera_avalon_sysid_qsys.c diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/drivers/src/altera_avalon_timer_sc.c b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/drivers/src/altera_avalon_timer_sc.c similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/drivers/src/altera_avalon_timer_sc.c rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/drivers/src/altera_avalon_timer_sc.c diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/drivers/src/altera_avalon_timer_ts.c b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/drivers/src/altera_avalon_timer_ts.c similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/drivers/src/altera_avalon_timer_ts.c rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/drivers/src/altera_avalon_timer_ts.c diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/drivers/src/altera_avalon_timer_vars.c b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/drivers/src/altera_avalon_timer_vars.c similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/drivers/src/altera_avalon_timer_vars.c rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/drivers/src/altera_avalon_timer_vars.c diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/drivers/src/altera_avalon_uart_fd.c b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/drivers/src/altera_avalon_uart_fd.c similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/drivers/src/altera_avalon_uart_fd.c rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/drivers/src/altera_avalon_uart_fd.c diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/drivers/src/altera_avalon_uart_init.c b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/drivers/src/altera_avalon_uart_init.c similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/drivers/src/altera_avalon_uart_init.c rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/drivers/src/altera_avalon_uart_init.c diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/drivers/src/altera_avalon_uart_ioctl.c b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/drivers/src/altera_avalon_uart_ioctl.c similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/drivers/src/altera_avalon_uart_ioctl.c rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/drivers/src/altera_avalon_uart_ioctl.c diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/drivers/src/altera_avalon_uart_read.c b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/drivers/src/altera_avalon_uart_read.c similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/drivers/src/altera_avalon_uart_read.c rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/drivers/src/altera_avalon_uart_read.c diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/drivers/src/altera_avalon_uart_write.c b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/drivers/src/altera_avalon_uart_write.c similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/drivers/src/altera_avalon_uart_write.c rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/drivers/src/altera_avalon_uart_write.c diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/drivers/src/altera_up_avalon_rs232.c b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/drivers/src/altera_up_avalon_rs232.c similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/drivers/src/altera_up_avalon_rs232.c rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/drivers/src/altera_up_avalon_rs232.c diff --git a/MCTEST/DE0-nano-HD/Software/MCTest_bsp/libucosii_bsp.a b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/libucosii_bsp.a new file mode 100644 index 00000000..8964ad46 Binary files /dev/null and b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/libucosii_bsp.a differ diff --git a/MCTEST/DE0-nano-HD/Software/MCTest_bsp/linker.h b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/linker.h new file mode 100644 index 00000000..8f1d2eab --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/linker.h @@ -0,0 +1,101 @@ +/* + * linker.h - Linker script mapping information + * + * Machine generated for CPU 'cpu' in SOPC Builder design 'system' + * SOPC Builder design path: C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo + * + * Generated: Thu Mar 06 10:04:03 MST 2014 + */ + +/* + * DO NOT MODIFY THIS FILE + * + * Changing this file will have subtle consequences + * which will almost certainly lead to a nonfunctioning + * system. If you do modify this file, be aware that your + * changes will be overwritten and lost when this file + * is generated again. + * + * DO NOT MODIFY THIS FILE + */ + +/* + * License Agreement + * + * Copyright (c) 2008 + * Altera Corporation, San Jose, California, USA. + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * This agreement shall be governed in all respects by the laws of the State + * of California and by the laws of the United States of America. + */ + +#ifndef __LINKER_H_ +#define __LINKER_H_ + + +/* + * BSP controls alt_load() behavior in crt0. + * + */ + +#define ALT_LOAD_EXPLICITLY_CONTROLLED + + +/* + * Base address and span (size in bytes) of each linker region + * + */ + +#define RESET_REGION_BASE 0x1000000 +#define RESET_REGION_SPAN 32 +#define SDRAM_REGION_BASE 0x1000020 +#define SDRAM_REGION_SPAN 16777184 + + +/* + * Devices associated with code sections + * + */ + +#define ALT_EXCEPTIONS_DEVICE SDRAM +#define ALT_RESET_DEVICE SDRAM +#define ALT_RODATA_DEVICE SDRAM +#define ALT_RWDATA_DEVICE SDRAM +#define ALT_TEXT_DEVICE SDRAM + + +/* + * Initialization code at the reset address is allowed (e.g. no external bootloader). + * + */ + +#define ALT_ALLOW_CODE_AT_RESET + + +/* + * The alt_load() facility is called from crt0 to copy sections into RAM. + * + */ + +#define ALT_LOAD_COPY_RWDATA + +#endif /* __LINKER_H_ */ diff --git a/MCTEST/DE0-nano-HD/Software/MCTest_bsp/linker.x b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/linker.x new file mode 100644 index 00000000..77a5735b --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/linker.x @@ -0,0 +1,385 @@ +/* + * linker.x - Linker script + * + * Machine generated for CPU 'cpu' in SOPC Builder design 'system' + * SOPC Builder design path: C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo + * + * Generated: Thu Mar 06 10:04:03 MST 2014 + */ + +/* + * DO NOT MODIFY THIS FILE + * + * Changing this file will have subtle consequences + * which will almost certainly lead to a nonfunctioning + * system. If you do modify this file, be aware that your + * changes will be overwritten and lost when this file + * is generated again. + * + * DO NOT MODIFY THIS FILE + */ + +/* + * License Agreement + * + * Copyright (c) 2008 + * Altera Corporation, San Jose, California, USA. + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * This agreement shall be governed in all respects by the laws of the State + * of California and by the laws of the United States of America. + */ + +MEMORY +{ + reset : ORIGIN = 0x1000000, LENGTH = 32 + sdram : ORIGIN = 0x1000020, LENGTH = 16777184 +} + +/* Define symbols for each memory base-address */ +__alt_mem_sdram = 0x1000000; + +OUTPUT_FORMAT( "elf32-littlenios2", + "elf32-littlenios2", + "elf32-littlenios2" ) +OUTPUT_ARCH( nios2 ) +ENTRY( _start ) + +/* + * The alt_load() facility is enabled. This typically happens when there isn't + * an external bootloader (e.g. flash bootloader). + * The LMA (aka physical address) of each loaded section is + * set to the .text memory device. + * The HAL alt_load() routine called from crt0 copies sections from + * the .text memory to RAM as needed. + */ + +SECTIONS +{ + + /* + * Output sections associated with reset and exceptions (they have to be first) + */ + + .entry : + { + KEEP (*(.entry)) + } > reset + + .exceptions : + { + PROVIDE (__ram_exceptions_start = ABSOLUTE(.)); + . = ALIGN(0x20); + KEEP (*(.irq)); + KEEP (*(.exceptions.entry.label)); + KEEP (*(.exceptions.entry.user)); + KEEP (*(.exceptions.entry)); + KEEP (*(.exceptions.irqtest.user)); + KEEP (*(.exceptions.irqtest)); + KEEP (*(.exceptions.irqhandler.user)); + KEEP (*(.exceptions.irqhandler)); + KEEP (*(.exceptions.irqreturn.user)); + KEEP (*(.exceptions.irqreturn)); + KEEP (*(.exceptions.notirq.label)); + KEEP (*(.exceptions.notirq.user)); + KEEP (*(.exceptions.notirq)); + KEEP (*(.exceptions.soft.user)); + KEEP (*(.exceptions.soft)); + KEEP (*(.exceptions.unknown.user)); + KEEP (*(.exceptions.unknown)); + KEEP (*(.exceptions.exit.label)); + KEEP (*(.exceptions.exit.user)); + KEEP (*(.exceptions.exit)); + KEEP (*(.exceptions)); + PROVIDE (__ram_exceptions_end = ABSOLUTE(.)); + } > sdram + + PROVIDE (__flash_exceptions_start = LOADADDR(.exceptions)); + + .text : + { + /* + * All code sections are merged into the text output section, along with + * the read only data sections. + * + */ + + PROVIDE (stext = ABSOLUTE(.)); + + *(.interp) + *(.hash) + *(.dynsym) + *(.dynstr) + *(.gnu.version) + *(.gnu.version_d) + *(.gnu.version_r) + *(.rel.init) + *(.rela.init) + *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) + *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) + *(.rel.fini) + *(.rela.fini) + *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) + *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) + *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) + *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) + *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) + *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) + *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) + *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) + *(.rel.ctors) + *(.rela.ctors) + *(.rel.dtors) + *(.rela.dtors) + *(.rel.got) + *(.rela.got) + *(.rel.sdata .rel.sdata.* .rel.gnu.linkonce.s.*) + *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*) + *(.rel.sbss .rel.sbss.* .rel.gnu.linkonce.sb.*) + *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*) + *(.rel.sdata2 .rel.sdata2.* .rel.gnu.linkonce.s2.*) + *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*) + *(.rel.sbss2 .rel.sbss2.* .rel.gnu.linkonce.sb2.*) + *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*) + *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) + *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) + *(.rel.plt) + *(.rela.plt) + *(.rel.dyn) + + KEEP (*(.init)) + *(.plt) + *(.text .stub .text.* .gnu.linkonce.t.*) + + /* .gnu.warning sections are handled specially by elf32.em. */ + + *(.gnu.warning.*) + KEEP (*(.fini)) + PROVIDE (__etext = ABSOLUTE(.)); + PROVIDE (_etext = ABSOLUTE(.)); + PROVIDE (etext = ABSOLUTE(.)); + + *(.eh_frame_hdr) + /* Ensure the __preinit_array_start label is properly aligned. We + could instead move the label definition inside the section, but + the linker would then create the section even if it turns out to + be empty, which isn't pretty. */ + . = ALIGN(4); + PROVIDE (__preinit_array_start = ABSOLUTE(.)); + *(.preinit_array) + PROVIDE (__preinit_array_end = ABSOLUTE(.)); + PROVIDE (__init_array_start = ABSOLUTE(.)); + *(.init_array) + PROVIDE (__init_array_end = ABSOLUTE(.)); + PROVIDE (__fini_array_start = ABSOLUTE(.)); + *(.fini_array) + PROVIDE (__fini_array_end = ABSOLUTE(.)); + SORT(CONSTRUCTORS) + KEEP (*(.eh_frame)) + *(.gcc_except_table) + *(.dynamic) + PROVIDE (__CTOR_LIST__ = ABSOLUTE(.)); + KEEP (*(.ctors)) + KEEP (*(SORT(.ctors.*))) + PROVIDE (__CTOR_END__ = ABSOLUTE(.)); + PROVIDE (__DTOR_LIST__ = ABSOLUTE(.)); + KEEP (*(.dtors)) + KEEP (*(SORT(.dtors.*))) + PROVIDE (__DTOR_END__ = ABSOLUTE(.)); + KEEP (*(.jcr)) + . = ALIGN(4); + } > sdram = 0x3a880100 /* Nios II NOP instruction */ + + .rodata : + { + PROVIDE (__ram_rodata_start = ABSOLUTE(.)); + . = ALIGN(4); + *(.rodata .rodata.* .gnu.linkonce.r.*) + *(.rodata1) + . = ALIGN(4); + PROVIDE (__ram_rodata_end = ABSOLUTE(.)); + } > sdram + + PROVIDE (__flash_rodata_start = LOADADDR(.rodata)); + + /* + * + * This section's LMA is set to the .text region. + * crt0 will copy to this section's specified mapped region virtual memory address (VMA) + * + * .rwdata region equals the .text region, and is set to be loaded into .text region. + * This requires two copies of .rwdata in the .text region. One read writable at VMA. + * and one read-only at LMA. crt0 will copy from LMA to VMA on reset + * + */ + + .rwdata LOADADDR (.rodata) + SIZEOF (.rodata) : AT ( LOADADDR (.rodata) + SIZEOF (.rodata)+ SIZEOF (.rwdata) ) + { + PROVIDE (__ram_rwdata_start = ABSOLUTE(.)); + . = ALIGN(4); + *(.got.plt) *(.got) + *(.data1) + *(.data .data.* .gnu.linkonce.d.*) + + _gp = ABSOLUTE(. + 0x8000); + PROVIDE(gp = _gp); + + *(.rwdata .rwdata.*) + *(.sdata .sdata.* .gnu.linkonce.s.*) + *(.sdata2 .sdata2.* .gnu.linkonce.s2.*) + + . = ALIGN(4); + _edata = ABSOLUTE(.); + PROVIDE (edata = ABSOLUTE(.)); + PROVIDE (__ram_rwdata_end = ABSOLUTE(.)); + } > sdram + + PROVIDE (__flash_rwdata_start = LOADADDR(.rwdata)); + + /* + * + * This section's LMA is set to the .text region. + * crt0 will copy to this section's specified mapped region virtual memory address (VMA) + * + */ + + .bss LOADADDR (.rwdata) + SIZEOF (.rwdata) : AT ( LOADADDR (.rwdata) + SIZEOF (.rwdata) ) + { + __bss_start = ABSOLUTE(.); + PROVIDE (__sbss_start = ABSOLUTE(.)); + PROVIDE (___sbss_start = ABSOLUTE(.)); + + *(.dynsbss) + *(.sbss .sbss.* .gnu.linkonce.sb.*) + *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*) + *(.scommon) + + PROVIDE (__sbss_end = ABSOLUTE(.)); + PROVIDE (___sbss_end = ABSOLUTE(.)); + + *(.dynbss) + *(.bss .bss.* .gnu.linkonce.b.*) + *(COMMON) + + . = ALIGN(4); + __bss_end = ABSOLUTE(.); + } > sdram + + /* + * + * One output section mapped to the associated memory device for each of + * the available memory devices. These are not used by default, but can + * be used by user applications by using the .section directive. + * + * The output section used for the heap is treated in a special way, + * i.e. the symbols "end" and "_end" are added to point to the heap start. + * + * Because alt_load() is enabled, these sections have + * their LMA set to be loaded into the .text memory region. + * However, the alt_load() code will NOT automatically copy + * these sections into their mapped memory region. + * + */ + + /* + * + * This section's LMA is set to the .text region. + * crt0 will copy to this section's specified mapped region virtual memory address (VMA) + * + */ + + .sdram LOADADDR (.bss) + SIZEOF (.bss) : AT ( LOADADDR (.bss) + SIZEOF (.bss) ) + { + PROVIDE (_alt_partition_sdram_start = ABSOLUTE(.)); + *(.sdram. sdram.*) + . = ALIGN(4); + PROVIDE (_alt_partition_sdram_end = ABSOLUTE(.)); + _end = ABSOLUTE(.); + end = ABSOLUTE(.); + __alt_stack_base = ABSOLUTE(.); + } > sdram + + PROVIDE (_alt_partition_sdram_load_addr = LOADADDR(.sdram)); + + /* + * Stabs debugging sections. + * + */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + + /* Altera debug extensions */ + .debug_alt_sim_info 0 : { *(.debug_alt_sim_info) } +} + +/* provide a pointer for the stack */ + +/* + * Don't override this, override the __alt_stack_* symbols instead. + */ +__alt_data_end = 0x2000000; + +/* + * The next two symbols define the location of the default stack. You can + * override them to move the stack to a different memory. + */ +PROVIDE( __alt_stack_pointer = __alt_data_end ); +PROVIDE( __alt_stack_limit = __alt_stack_base ); + +/* + * This symbol controls where the start of the heap is. If the stack is + * contiguous with the heap then the stack will contract as memory is + * allocated to the heap. + * Override this symbol to put the heap in a different memory. + */ +PROVIDE( __alt_heap_start = end ); +PROVIDE( __alt_heap_limit = 0x2000000 ); diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/mem_init.mk b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/mem_init.mk similarity index 100% rename from MCandWifiTestDE0/NewMCWifiTest_bsp/mem_init.mk rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/mem_init.mk diff --git a/MCTEST/DE0-nano-HD/Software/MCTest_bsp/memory.gdb b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/memory.gdb new file mode 100644 index 00000000..b1633b67 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/memory.gdb @@ -0,0 +1,50 @@ +# memory.gdb - GDB memory region definitions +# +# Machine generated for CPU 'cpu' in SOPC Builder design 'system' +# SOPC Builder design path: C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo +# +# Generated: Thu Mar 06 10:04:03 MST 2014 + +# DO NOT MODIFY THIS FILE +# +# Changing this file will have subtle consequences +# which will almost certainly lead to a nonfunctioning +# system. If you do modify this file, be aware that your +# changes will be overwritten and lost when this file +# is generated again. +# +# DO NOT MODIFY THIS FILE + +# License Agreement +# +# Copyright (c) 2008 +# Altera Corporation, San Jose, California, USA. +# All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +# DEALINGS IN THE SOFTWARE. +# +# This agreement shall be governed in all respects by the laws of the State +# of California and by the laws of the United States of America. + +# Define memory regions for each memory connected to the CPU. +# The cache attribute is specified which improves GDB performance +# by allowing GDB to cache memory contents on the host. + +# sdram +memory 0x1000000 0x2000000 cache diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/obj/HAL/src/alt_alarm_start.d b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/obj/HAL/src/alt_alarm_start.d similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/obj/HAL/src/alt_alarm_start.d rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/obj/HAL/src/alt_alarm_start.d diff --git a/MCTEST/DE0-nano-HD/Software/MCTest_bsp/obj/HAL/src/alt_alarm_start.o b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/obj/HAL/src/alt_alarm_start.o new file mode 100644 index 00000000..17806d26 Binary files /dev/null and b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/obj/HAL/src/alt_alarm_start.o differ diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/obj/HAL/src/alt_busy_sleep.d b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/obj/HAL/src/alt_busy_sleep.d similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/obj/HAL/src/alt_busy_sleep.d rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/obj/HAL/src/alt_busy_sleep.d diff --git a/MCTEST/DE0-nano-HD/Software/MCTest_bsp/obj/HAL/src/alt_busy_sleep.o b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/obj/HAL/src/alt_busy_sleep.o new file mode 100644 index 00000000..59308f06 Binary files /dev/null and b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/obj/HAL/src/alt_busy_sleep.o differ diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/obj/HAL/src/alt_close.d b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/obj/HAL/src/alt_close.d similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/obj/HAL/src/alt_close.d rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/obj/HAL/src/alt_close.d diff --git a/MCTEST/DE0-nano-HD/Software/MCTest_bsp/obj/HAL/src/alt_close.o b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/obj/HAL/src/alt_close.o new file mode 100644 index 00000000..c7a3b4f6 Binary files /dev/null and b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/obj/HAL/src/alt_close.o differ diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/obj/HAL/src/alt_dcache_flush.d b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/obj/HAL/src/alt_dcache_flush.d similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/obj/HAL/src/alt_dcache_flush.d rename to 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b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/obj/drivers/src/altera_avalon_timer_vars.d similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/obj/drivers/src/altera_avalon_timer_vars.d rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/obj/drivers/src/altera_avalon_timer_vars.d diff --git a/MCTEST/DE0-nano-HD/Software/MCTest_bsp/obj/drivers/src/altera_avalon_timer_vars.o b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/obj/drivers/src/altera_avalon_timer_vars.o new file mode 100644 index 00000000..c2627173 Binary files /dev/null and b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/obj/drivers/src/altera_avalon_timer_vars.o differ diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/obj/drivers/src/altera_avalon_uart_fd.d b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/obj/drivers/src/altera_avalon_uart_fd.d similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/obj/drivers/src/altera_avalon_uart_fd.d rename to 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MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/obj/drivers/src/altera_avalon_uart_write.d rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/obj/drivers/src/altera_avalon_uart_write.d diff --git a/MCTEST/DE0-nano-HD/Software/MCTest_bsp/obj/drivers/src/altera_avalon_uart_write.o b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/obj/drivers/src/altera_avalon_uart_write.o new file mode 100644 index 00000000..51e0e6da Binary files /dev/null and b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/obj/drivers/src/altera_avalon_uart_write.o differ diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/obj/drivers/src/altera_up_avalon_rs232.d b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/obj/drivers/src/altera_up_avalon_rs232.d similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/obj/drivers/src/altera_up_avalon_rs232.d rename to MCTEST/DE0-nano-HD/Software/MCTest_bsp/obj/drivers/src/altera_up_avalon_rs232.d diff --git a/MCTEST/DE0-nano-HD/Software/MCTest_bsp/obj/drivers/src/altera_up_avalon_rs232.o b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/obj/drivers/src/altera_up_avalon_rs232.o new file mode 100644 index 00000000..e809bc5b Binary files /dev/null and b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/obj/drivers/src/altera_up_avalon_rs232.o differ diff --git a/MCTEST/DE0-nano-HD/Software/MCTest_bsp/public.mk b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/public.mk new file mode 100644 index 00000000..a1607772 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/public.mk @@ -0,0 +1,402 @@ +#------------------------------------------------------------------------------ +# BSP "PUBLIC" MAKEFILE CONTENT +# +# This file is intended to be included in an application or library +# Makefile that is using this BSP. You can create such a Makefile with +# the nios2-app-generate-makefile or nios2-lib-generate-makefile +# commands. +# +# The following variables must be defined before including this file: +# +# ALT_LIBRARY_ROOT_DIR +# Contains the path to the BSP top-level (aka root) directory +#------------------------------------------------------------------------------ + +#------------------------------------------------------------------------------ +# PATHS +#------------------------------------------------------------------------------ + + + +# Path to the provided linker script. +BSP_LINKER_SCRIPT := $(ALT_LIBRARY_ROOT_DIR)/linker.x + +# Include paths: +# The path to root of all header files that a library wishes to make +# available for an application's use is specified here. Note that this +# may not be *all* folders within a hierarchy. For example, if it is +# desired that the application developer type: +# #include +# #include +# With files laid out like this: +# /inc/sockets.h +# /inc/ip/tcpip.h +# +# Then, only /inc need be added to the list of include +# directories. Alternatively, if you wish to be able to directly include +# all files in a hierarchy, separate paths to each folder in that +# hierarchy must be defined. + +# The following are the "base" set of include paths for a BSP. +# These paths are appended to the list that individual software +# components, drivers, etc., add in the generated portion of this +# file (below). +ALT_INCLUDE_DIRS_TO_APPEND += \ + $(ALT_LIBRARY_ROOT_DIR) \ + $(ALT_LIBRARY_ROOT_DIR)/drivers/inc + +# Additions to linker library search-path: +# Here we provide a path to "our self" for the application to construct a +# "-L " out of. This should contain a list of directories, +# relative to the library root, of all directories with .a files to link +# against. +ALT_LIBRARY_DIRS += $(ALT_LIBRARY_ROOT_DIR) + + +#------------------------------------------------------------------------------ +# COMPILATION FLAGS +#------------------------------------------------------------------------------ +# Default C pre-processor flags for a BSP: +ALT_CPPFLAGS += -DSYSTEM_BUS_WIDTH=32 \ + -pipe + + +#------------------------------------------------------------------------------ +# MANAGED CONTENT +# +# All content between the lines "START MANAGED" and "END MANAGED" below is +# generated based on variables in the BSP settings file when the +# nios2-bsp-generate-files command is invoked. If you wish to persist any +# information pertaining to the build process, it is recomended that you +# utilize the BSP settings mechanism to do so. +#------------------------------------------------------------------------------ +#START MANAGED + +# The following TYPE comment allows tools to identify the 'type' of target this +# makefile is associated with. +# TYPE: BSP_PUBLIC_MAKEFILE + +# This following VERSION comment indicates the version of the tool used to +# generate this makefile. A makefile variable is provided for VERSION as well. +# ACDS_VERSION: 12.1sp1 +ACDS_VERSION := 12.1sp1 + +# This following BUILD_NUMBER comment indicates the build number of the tool +# used to generate this makefile. +# BUILD_NUMBER: 243 + +# Quartus Generated JDI File. Required for resolving node instance ID's with +# design component names. +JDI_FILE := C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.jdi + +# Qsys--generated SOPCINFO file. Required for resolving node instance ID's with +# design component names. +SOPCINFO_FILE := C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo + +# Big-Endian operation. +# setting BIG_ENDIAN is false +ALT_CFLAGS += -EL + +# Path to the provided C language runtime initialization code. +BSP_CRT0 := $(ALT_LIBRARY_ROOT_DIR)/obj/HAL/src/crt0.o + +# Name of BSP library as provided to linker using the "-msys-lib" flag or +# linker script GROUP command. +# setting BSP_SYS_LIB is ucosii_bsp +BSP_SYS_LIB := ucosii_bsp +ELF_PATCH_FLAG += --thread_model ucosii + +# Type identifier of the BSP library +# setting BSP_TYPE is ucosii +ALT_CPPFLAGS += -D__hal__ +BSP_TYPE := ucosii + +# CPU Name +# setting CPU_NAME is cpu +CPU_NAME = cpu +ELF_PATCH_FLAG += --cpu_name $(CPU_NAME) + +# Hardware Divider present. +# setting HARDWARE_DIVIDE is false +ALT_CFLAGS += -mno-hw-div + +# Hardware Multiplier present. +# setting HARDWARE_MULTIPLY is true +ALT_CFLAGS += -mhw-mul + +# Hardware Mulx present. +# setting HARDWARE_MULX is false +ALT_CFLAGS += -mno-hw-mulx + +# Debug Core present. +# setting HAS_DEBUG_CORE is true +CPU_HAS_DEBUG_CORE = 1 + +# Qsys generated design +# setting QSYS is 1 +QSYS := 1 +ELF_PATCH_FLAG += --qsys true + +# Design Name +# setting SOPC_NAME is system +SOPC_NAME := system + +# SopcBuilder Simulation Enabled +# setting SOPC_SIMULATION_ENABLED is false +ELF_PATCH_FLAG += --simulation_enabled false + +# The SOPC System ID +# setting SOPC_SYSID is 0 +SOPC_SYSID_FLAG += --id=0 +ELF_PATCH_FLAG += --id 0 + +# The SOPC System ID Base Address +# setting SOPC_SYSID_BASE_ADDRESS is 0x20010a0 +SOPC_SYSID_FLAG += --sidp=0x20010a0 +ELF_PATCH_FLAG += --sidp 0x20010a0 + +# The SOPC Timestamp +# setting SOPC_TIMESTAMP is 1394124174 +SOPC_SYSID_FLAG += --timestamp=1394124174 +ELF_PATCH_FLAG += --timestamp 1394124174 + +# Small-footprint (polled mode) driver none +# setting altera_avalon_jtag_uart_driver.enable_small_driver is false + +# Enable driver ioctl() support. This feature is not compatible with the +# 'small' driver; ioctl() support will not be compiled if either the UART +# 'enable_small_driver' or HAL 'enable_reduced_device_drivers' settings are +# enabled. none +# setting altera_avalon_uart_driver.enable_ioctl is false + +# Small-footprint (polled mode) driver none +# setting altera_avalon_uart_driver.enable_small_driver is false + +# Build a custom version of newlib with the specified space-separated compiler +# flags. The custom newlib build will be placed in the <bsp root>/newlib +# directory, and will be used only for applications that utilize this BSP. +# setting hal.custom_newlib_flags is none + +# Enable support for a subset of the C++ language. This option increases code +# footprint by adding support for C++ constructors. Certain features, such as +# multiple inheritance and exceptions are not supported. If false, adds +# -DALT_NO_C_PLUS_PLUS to ALT_CPPFLAGS in public.mk, and reduces code +# footprint. none +# setting hal.enable_c_plus_plus is 1 + +# When your application exits, close file descriptors, call C++ destructors, +# etc. Code footprint can be reduced by disabling clean exit. If disabled, adds +# -DALT_NO_CLEAN_EXIT to ALT_CPPFLAGS and -Wl,--defsym, exit=_exit to +# ALT_LDFLAGS in public.mk. none +# setting hal.enable_clean_exit is 1 + +# Add exit() support. This option increases code footprint if your "main()" +# routine does "return" or call "exit()". If false, adds -DALT_NO_EXIT to +# ALT_CPPFLAGS in public.mk, and reduces footprint none +# setting hal.enable_exit is 1 + +# Causes code to be compiled with gprof profiling enabled and the application +# ELF to be linked with the GPROF library. If true, adds -DALT_PROVIDE_GMON to +# ALT_CPPFLAGS and -pg to ALT_CFLAGS in public.mk. none +# setting hal.enable_gprof is 0 + +# Enables lightweight device driver API. This reduces code and data footprint +# by removing the HAL layer that maps device names (e.g. /dev/uart0) to file +# descriptors. Instead, driver routines are called directly. The open(), +# close(), and lseek() routines will always fail if called. The read(), +# write(), fstat(), ioctl(), and isatty() routines only work for the stdio +# devices. If true, adds -DALT_USE_DIRECT_DRIVERS to ALT_CPPFLAGS in public.mk. +# The Altera Host and read-only ZIP file systems can't be used if +# hal.enable_lightweight_device_driver_api is true. +# setting hal.enable_lightweight_device_driver_api is 0 + +# Adds code to emulate multiply and divide instructions in case they are +# executed but aren't present in the CPU. Normally this isn't required because +# the compiler won't use multiply and divide instructions that aren't present +# in the CPU. If false, adds -DALT_NO_INSTRUCTION_EMULATION to ALT_CPPFLAGS in +# public.mk. none +# setting hal.enable_mul_div_emulation is 0 +ALT_CPPFLAGS += -DALT_NO_INSTRUCTION_EMULATION + +# Certain drivers are compiled with reduced functionality to reduce code +# footprint. Not all drivers observe this setting. The altera_avalon_uart and +# altera_avalon_jtag_uart drivers switch from interrupt-driven to polled +# operation. CAUTION: Several device drivers are disabled entirely. These +# include the altera_avalon_cfi_flash, altera_avalon_epcs_flash_controller, and +# altera_avalon_lcd_16207 drivers. This can result in certain API (HAL flash +# access routines) to fail. You can define a symbol provided by each driver to +# prevent it from being removed. If true, adds -DALT_USE_SMALL_DRIVERS to +# ALT_CPPFLAGS in public.mk. none +# setting hal.enable_reduced_device_drivers is 0 + +# Turns on HAL runtime stack checking feature. Enabling this setting causes +# additional code to be placed into each subroutine call to generate an +# exception if a stack collision occurs with the heap or statically allocated +# data. If true, adds -DALT_STACK_CHECK and -mstack-check to ALT_CPPFLAGS in +# public.mk. none +# setting hal.enable_runtime_stack_checking is 0 + +# The BSP is compiled with optimizations to speedup HDL simulation such as +# initializing the cache, clearing the .bss section, and skipping long delay +# loops. If true, adds -DALT_SIM_OPTIMIZE to ALT_CPPFLAGS in public.mk. When +# this setting is true, the BSP shouldn't be used to build applications that +# are expected to run real hardware. +# setting hal.enable_sim_optimize is 0 + +# Causes the small newlib (C library) to be used. This reduces code and data +# footprint at the expense of reduced functionality. Several newlib features +# are removed such as floating-point support in printf(), stdin input routines, +# and buffered I/O. The small C library is not compatible with Micrium +# MicroC/OS-II. If true, adds -msmallc to ALT_LDFLAGS in public.mk. none +# setting hal.enable_small_c_library is 0 + +# Enable SOPC Builder System ID. If a System ID SOPC Builder component is +# connected to the CPU associated with this BSP, it will be enabled in the +# creation of command-line arguments to download an ELF to the target. +# Otherwise, system ID and timestamp values are left out of public.mk for +# application Makefile "download-elf" target definition. With the system ID +# check disabled, the Nios II EDS tools will not automatically ensure that the +# application .elf file (and BSP it is linked against) corresponds to the +# hardware design on the target. If false, adds --accept-bad-sysid to +# SOPC_SYSID_FLAG in public.mk. none +# setting hal.enable_sopc_sysid_check is 1 + +# Enable BSP generation to query if SOPC system is big endian. If true ignores +# export of 'ALT_CFLAGS += -EB' to public.mk if big endian system. If true +# ignores export of 'ALT_CFLAGS += -EL' if little endian system. none +# setting hal.make.ignore_system_derived.big_endian is 0 + +# Enable BSP generation to query if SOPC system has a debug core present. If +# true ignores export of 'CPU_HAS_DEBUG_CORE = 1' to public.mk if a debug core +# is found in the system. If true ignores export of 'CPU_HAS_DEBUG_CORE = 0' if +# no debug core is found in the system. none +# setting hal.make.ignore_system_derived.debug_core_present is 0 + +# Enable BSP generation to query if SOPC system has FPU present. If true +# ignores export of 'ALT_CFLAGS += -mhard-float' to public.mk if FPU is found +# in the system. If true ignores export of 'ALT_CFLAGS += -mhard-soft' if FPU +# is not found in the system. none +# setting hal.make.ignore_system_derived.fpu_present is 0 + +# Enable BSP generation to query if SOPC system has hardware divide present. If +# true ignores export of 'ALT_CFLAGS += -mno-hw-div' to public.mk if no +# division is found in system. If true ignores export of 'ALT_CFLAGS += +# -mhw-div' if division is found in the system. none +# setting hal.make.ignore_system_derived.hardware_divide_present is 0 + +# Enable BSP generation to query if SOPC system floating point custom +# instruction with a divider is present. If true ignores export of 'ALT_CFLAGS +# += -mcustom-fpu-cfg=60-2' and 'ALT_LDFLAGS += -mcustom-fpu-cfg=60-2' to +# public.mk if the custom instruction is found in the system. none +# setting hal.make.ignore_system_derived.hardware_fp_cust_inst_divider_present is 0 + +# Enable BSP generation to query if SOPC system floating point custom +# instruction without a divider is present. If true ignores export of +# 'ALT_CFLAGS += -mcustom-fpu-cfg=60-1' and 'ALT_LDFLAGS += +# -mcustom-fpu-cfg=60-1' to public.mk if the custom instruction is found in the +# system. none +# setting hal.make.ignore_system_derived.hardware_fp_cust_inst_no_divider_present is 0 + +# Enable BSP generation to query if SOPC system has multiplier present. If true +# ignores export of 'ALT_CFLAGS += -mno-hw-mul' to public.mk if no multiplier +# is found in the system. If true ignores export of 'ALT_CFLAGS += -mhw-mul' if +# multiplier is found in the system. none +# setting hal.make.ignore_system_derived.hardware_multiplier_present is 0 + +# Enable BSP generation to query if SOPC system has hardware mulx present. If +# true ignores export of 'ALT_CFLAGS += -mno-hw-mulx' to public.mk if no mulx +# is found in the system. If true ignores export of 'ALT_CFLAGS += -mhw-mulx' +# if mulx is found in the system. none +# setting hal.make.ignore_system_derived.hardware_mulx_present is 0 + +# Enable BSP generation to query if SOPC system has simulation enabled. If true +# ignores export of 'ELF_PATCH_FLAG += --simulation_enabled' to public.mk. none +# setting hal.make.ignore_system_derived.sopc_simulation_enabled is 0 + +# Enable BSP generation to query SOPC system for system ID base address. If +# true ignores export of 'SOPC_SYSID_FLAG += --sidp=
' and +# 'ELF_PATCH_FLAG += --sidp=
' to public.mk. none +# setting hal.make.ignore_system_derived.sopc_system_base_address is 0 + +# Enable BSP generation to query SOPC system for system ID. If true ignores +# export of 'SOPC_SYSID_FLAG += --id=' and 'ELF_PATCH_FLAG += +# --id=' to public.mk. none +# setting hal.make.ignore_system_derived.sopc_system_id is 0 + +# Enable BSP generation to query SOPC system for system timestamp. If true +# ignores export of 'SOPC_SYSID_FLAG += --timestamp=' and +# 'ELF_PATCH_FLAG += --timestamp=' to public.mk. none +# setting hal.make.ignore_system_derived.sopc_system_timestamp is 0 + +# Slave descriptor of STDERR character-mode device. This setting is used by the +# ALT_STDERR family of defines in system.h. none +# setting hal.stderr is jtag_uart_0 +ELF_PATCH_FLAG += --stderr_dev jtag_uart_0 + +# Slave descriptor of STDIN character-mode device. This setting is used by the +# ALT_STDIN family of defines in system.h. none +# setting hal.stdin is jtag_uart_0 +ELF_PATCH_FLAG += --stdin_dev jtag_uart_0 + +# Slave descriptor of STDOUT character-mode device. This setting is used by the +# ALT_STDOUT family of defines in system.h. none +# setting hal.stdout is jtag_uart_0 +ELF_PATCH_FLAG += --stdout_dev jtag_uart_0 + + +#------------------------------------------------------------------------------ +# SOFTWARE COMPONENT & DRIVER INCLUDE PATHS +#------------------------------------------------------------------------------ + +ALT_INCLUDE_DIRS += $(ALT_LIBRARY_ROOT_DIR)/UCOSII/inc +ALT_INCLUDE_DIRS += $(ALT_LIBRARY_ROOT_DIR)/HAL/inc + +#------------------------------------------------------------------------------ +# SOFTWARE COMPONENT & DRIVER PRODUCED ALT_CPPFLAGS ADDITIONS +#------------------------------------------------------------------------------ + +ALT_CPPFLAGS += -D__ucosii__ + +#END MANAGED + + +#------------------------------------------------------------------------------ +# LIBRARY INFORMATION +#------------------------------------------------------------------------------ +# Assemble the name of the BSP *.a file using the BSP library name +# (BSP_SYS_LIB) in generated content above. +BSP_LIB := lib$(BSP_SYS_LIB).a + +# Additional libraries to link against: +# An application including this file will prefix each library with "-l". +# For example, to include the Newlib math library "m" is included, which +# becomes "-lm" when linking the application. +ALT_LIBRARY_NAMES += m + +# Additions to linker dependencies: +# An application Makefile will typically add these directly to the list +# of dependencies required to build the executable target(s). The BSP +# library (*.a) file is specified here. +ALT_LDDEPS += $(ALT_LIBRARY_ROOT_DIR)/$(BSP_LIB) + +# Is this library "Makeable"? +# Add to list of root library directories that support running 'make' +# to build them. Because libraries may or may not have a Makefile in their +# root, appending to this variable tells an application to run 'make' in +# the library root to build/update this library. +MAKEABLE_LIBRARY_ROOT_DIRS += $(ALT_LIBRARY_ROOT_DIR) + +# Additional Assembler Flags +# -gdwarf2 flag is required for stepping through assembly code +ALT_ASFLAGS += -gdwarf2 + +#------------------------------------------------------------------------------ +# FINAL INCLUDE PATH LIST +#------------------------------------------------------------------------------ +# Append static include paths to paths specified by OS/driver/sw package +# additions to the BSP thus giving them precedence in case a BSP addition +# is attempting to override BSP sources. +ALT_INCLUDE_DIRS += $(ALT_INCLUDE_DIRS_TO_APPEND) + + + diff --git a/MCTEST/DE0-nano-HD/Software/MCTest_bsp/settings.bsp b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/settings.bsp new file mode 100644 index 00000000..c5b64d4a --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/settings.bsp @@ -0,0 +1,1801 @@ + + + ucosii + default + 14-Mar-2014 4:49:59 PM + 1394837399894 + C:\Users\gongal\Desktop\MCTEST\DE0-nano-HD\Software\MCTest_bsp + settings.bsp + C:\Users\gongal\Desktop\MCTEST\DE0-nano-HD\system.sopcinfo + default + cpu + 1.9 + + hal.sys_clk_timer + ALT_SYS_CLK + UnquotedString + sys_clk_timer + none + system_h_define + Slave descriptor of the system clock timer device. This device provides a periodic interrupt ("tick") and is typically required for RTOS use. This setting defines the value of ALT_SYS_CLK in system.h. + none + false + common + + + hal.timestamp_timer + ALT_TIMESTAMP_CLK + UnquotedString + none + none + system_h_define + Slave descriptor of timestamp timer device. This device is used by Altera HAL timestamp drivers for high-resolution time measurement. This setting defines the value of ALT_TIMESTAMP_CLK in system.h. + none + false + common + + + hal.max_file_descriptors + ALT_MAX_FD + DecimalNumber + 32 + 32 + system_h_define + Determines the number of file descriptors statically allocated. This setting defines the value of ALT_MAX_FD in system.h. + If hal.enable_lightweight_device_driver_api is true, there are no file descriptors so this setting is ignored. If hal.enable_lightweight_device_driver_api is false, this setting must be at least 4 because HAL needs a file descriptor for /dev/null, /dev/stdin, /dev/stdout, and /dev/stderr. + false + + + + hal.enable_instruction_related_exceptions_api + ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API + BooleanDefineOnly + false + false + system_h_define + Enables API for registering handlers to service instruction-related exceptions. Enabling this setting increases the size of the exception entry code. + These exception types can be generated if various processor options are enabled, such as the MMU, MPU, or other advanced exception types. + false + + + + hal.linker.allow_code_at_reset + ALT_ALLOW_CODE_AT_RESET + Boolean + 1 + 0 + none + Indicates if initialization code is allowed at the reset address. If true, defines the macro ALT_ALLOW_CODE_AT_RESET in linker.h. + If true, defines the macro ALT_ALLOW_CODE_AT_RESET in linker.h. This setting is typically false if an external bootloader (e.g. flash bootloader) is present. + false + + + + hal.linker.enable_alt_load + NONE + Boolean + 1 + 0 + none + Enables the alt_load() facility. The alt_load() facility copies sections from the .text memory into RAM. If true, this setting sets up the VMA/LMA of sections in linker.x to allow them to be loaded into the .text memory. + This setting is typically false if an external bootloader (e.g. flash bootloader) is present. + false + + + + hal.linker.enable_alt_load_copy_rodata + NONE + Boolean + 0 + 0 + none + Causes the alt_load() facility to copy the .rodata section. If true, this setting defines the macro ALT_LOAD_COPY_RODATA in linker.h. + none + false + + + + hal.linker.enable_alt_load_copy_rwdata + NONE + Boolean + 1 + 0 + none + Causes the alt_load() facility to copy the .rwdata section. If true, this setting defines the macro ALT_LOAD_COPY_RWDATA in linker.h. + none + false + + + + hal.linker.enable_alt_load_copy_exceptions + NONE + Boolean + 0 + 0 + none + Causes the alt_load() facility to copy the .exceptions section. If true, this setting defines the macro ALT_LOAD_COPY_EXCEPTIONS in linker.h. + none + false + + + + hal.linker.enable_exception_stack + NONE + Boolean + 0 + 0 + none + Enables use of a separate exception stack. If true, defines the macro ALT_EXCEPTION_STACK in linker.h, adds a memory region called exception_stack to linker.x, and provides the symbols __alt_exception_stack_pointer and __alt_exception_stack_limit in linker.x. + The hal.linker.exception_stack_size and hal.linker.exception_stack_memory_region_name settings must also be valid. This setting must be false for MicroC/OS-II BSPs. The exception stack can be used to improve interrupt and other exception performance if the EIC is *not* used. + false + common + + + hal.linker.exception_stack_size + NONE + DecimalNumber + 1024 + 1024 + none + Size of the exception stack in bytes. + Only used if hal.linker.enable_exception_stack is true. + false + common + + + hal.linker.exception_stack_memory_region_name + NONE + UnquotedString + sdram + none + none + Name of the existing memory region that will be divided up to create the 'exception_stack' memory region. The selected region name will be adjusted automatically when the BSP is generated to create the 'exception_stack' memory region. + Only used if hal.linker.enable_exception_stack is true. + false + common + + + hal.linker.enable_interrupt_stack + NONE + Boolean + 0 + 0 + none + Enables use of a separate interrupt stack. If true, defines the macro ALT_INTERRUPT_STACK in linker.h, adds a memory region called interrupt_stack to linker.x, and provides the symbols __alt_interrupt_stack_pointer and __alt_interrupt_stack_limit in linker.x. + The hal.linker.interrupt_stack_size and hal.linker.interrupt_stack_memory_region_name settings must also be valid. This setting must be false for MicroC/OS-II BSPs. Only enable if the EIC is used exclusively. The exception stack can be used to improve interrupt and other exception performance if the EIC is *not* used. + false + common + + + hal.linker.interrupt_stack_size + NONE + DecimalNumber + 1024 + 1024 + none + Size of the interrupt stack in bytes. + Only used if hal.linker.enable_interrupt_stack is true. + false + common + + + hal.linker.interrupt_stack_memory_region_name + NONE + UnquotedString + sdram + none + none + Name of the existing memory region that will be divided up to create the 'interrupt_stack' memory region. The selected region name will be adjusted automatically when the BSP is generated to create the 'interrupt_stack' memory region. + Only used if hal.linker.enable_interrupt_stack is true. + false + common + + + hal.stdin + NONE + UnquotedString + jtag_uart_0 + none + system_h_define + Slave descriptor of STDIN character-mode device. This setting is used by the ALT_STDIN family of defines in system.h. + none + false + common + + + hal.stdout + NONE + UnquotedString + jtag_uart_0 + none + system_h_define + Slave descriptor of STDOUT character-mode device. This setting is used by the ALT_STDOUT family of defines in system.h. + none + false + common + + + hal.stderr + NONE + UnquotedString + jtag_uart_0 + none + system_h_define + Slave descriptor of STDERR character-mode device. This setting is used by the ALT_STDERR family of defines in system.h. + none + false + common + + + hal.log_port + NONE + UnquotedString + none + none + public_mk_define + Slave descriptor of debug logging character-mode device. If defined, it enables extra debug messages in the HAL source. This setting is used by the ALT_LOG_PORT family of defines in system.h. + none + false + none + + + hal.make.build_pre_process + BUILD_PRE_PROCESS + UnquotedString + none + none + makefile_variable + Command executed before BSP built. + none + false + none + + + hal.make.ar_pre_process + AR_PRE_PROCESS + UnquotedString + none + none + makefile_variable + Command executed before archiver execution. + none + false + none + + + hal.make.bsp_cflags_defined_symbols + BSP_CFLAGS_DEFINED_SYMBOLS + UnquotedString + none + none + makefile_variable + Preprocessor macros to define. A macro definition in this setting has the same effect as a "#define" in source code. Adding "-DALT_DEBUG" to this setting has the same effect as "#define ALT_DEBUG" in a souce file. Adding "-DFOO=1" to this setting is equivalent to the macro "#define FOO 1" in a source file. Macros defined with this setting are applied to all .S, .c, and C++ files in the BSP. This setting defines the value of BSP_CFLAGS_DEFINED_SYMBOLS in the BSP Makefile. + none + false + none + + + hal.make.ar_post_process + AR_POST_PROCESS + UnquotedString + none + none + makefile_variable + Command executed after archiver execution. + none + false + none + + + hal.make.as + AS + UnquotedString + nios2-elf-gcc + nios2-elf-gcc + makefile_variable + Assembler command. Note that CC is used for .S files. + none + false + none + + + hal.make.build_post_process + BUILD_POST_PROCESS + UnquotedString + none + none + makefile_variable + Command executed after BSP built. + none + false + none + + + hal.make.bsp_cflags_debug + BSP_CFLAGS_DEBUG + UnquotedString + -g + -g + makefile_variable + C/C++ compiler debug level. '-g' provides the default set of debug symbols typically required to debug a typical application. Omitting '-g' removes debug symbols from the ELF. This setting defines the value of BSP_CFLAGS_DEBUG in Makefile. + none + false + common + + + hal.make.ar + AR + UnquotedString + nios2-elf-ar + nios2-elf-ar + makefile_variable + Archiver command. Creates library files. + none + false + none + + + hal.make.rm + RM + UnquotedString + rm -f + rm -f + makefile_variable + Command used to remove files during 'clean' target. + none + false + none + + + hal.make.cxx_pre_process + CXX_PRE_PROCESS + UnquotedString + none + none + makefile_variable + Command executed before each C++ file is compiled. + none + false + none + + + hal.make.bsp_cflags_warnings + BSP_CFLAGS_WARNINGS + UnquotedString + -Wall + -Wall + makefile_variable + C/C++ compiler warning level. "-Wall" is commonly used.This setting defines the value of BSP_CFLAGS_WARNINGS in Makefile. + none + false + none + + + hal.make.bsp_arflags + BSP_ARFLAGS + UnquotedString + -src + -src + makefile_variable + Custom flags only passed to the archiver. This content of this variable is directly passed to the archiver rather than the more standard "ARFLAGS". The reason for this is that GNU Make assumes some default content in ARFLAGS. This setting defines the value of BSP_ARFLAGS in Makefile. + none + false + none + + + hal.make.bsp_cflags_optimization + BSP_CFLAGS_OPTIMIZATION + UnquotedString + -O0 + -O0 + makefile_variable + C/C++ compiler optimization level. "-O0" = no optimization,"-O2" = "normal" optimization, etc. "-O0" is recommended for code that you want to debug since compiler optimization can remove variables and produce non-sequential execution of code while debugging. This setting defines the value of BSP_CFLAGS_OPTIMIZATION in Makefile. + none + false + common + + + hal.make.as_post_process + AS_POST_PROCESS + UnquotedString + none + none + makefile_variable + Command executed after each assembly file is compiled. + none + false + none + + + hal.make.cc_pre_process + CC_PRE_PROCESS + UnquotedString + none + none + makefile_variable + Command executed before each .c/.S file is compiled. + none + false + none + + + hal.make.bsp_asflags + BSP_ASFLAGS + UnquotedString + -Wa,-gdwarf2 + -Wa,-gdwarf2 + makefile_variable + Custom flags only passed to the assembler. This setting defines the value of BSP_ASFLAGS in Makefile. + none + false + none + + + hal.make.as_pre_process + AS_PRE_PROCESS + UnquotedString + none + none + makefile_variable + Command executed before each assembly file is compiled. + none + false + none + + + hal.make.bsp_cflags_undefined_symbols + BSP_CFLAGS_UNDEFINED_SYMBOLS + UnquotedString + none + none + makefile_variable + Preprocessor macros to undefine. Undefined macros are similar to defined macros, but replicate the "#undef" directive in source code. To undefine the macro FOO use the syntax "-u FOO" in this setting. This is equivalent to "#undef FOO" in a source file. Note: the syntax differs from macro definition (there is a space, i.e. "-u FOO" versus "-DFOO"). Macros defined with this setting are applied to all .S, .c, and C++ files in the BSP. This setting defines the value of BSP_CFLAGS_UNDEFINED_SYMBOLS in the BSP Makefile. + none + false + none + + + hal.make.cc_post_process + CC_POST_PROCESS + UnquotedString + none + none + makefile_variable + Command executed after each .c/.S file is compiled. + none + false + none + + + hal.make.cxx_post_process + CXX_POST_PROCESS + UnquotedString + none + none + makefile_variable + Command executed before each C++ file is compiled. + none + false + none + + + hal.make.cc + CC + UnquotedString + nios2-elf-gcc -xc + nios2-elf-gcc -xc + makefile_variable + C compiler command. + none + false + none + + + hal.make.bsp_cxx_flags + BSP_CXXFLAGS + UnquotedString + none + none + makefile_variable + Custom flags only passed to the C++ compiler. This setting defines the value of BSP_CXXFLAGS in Makefile. + none + false + none + + + hal.make.bsp_inc_dirs + BSP_INC_DIRS + UnquotedString + none + none + makefile_variable + Space separated list of extra include directories to scan for header files. Directories are relative to the top-level BSP directory. The -I prefix's added by the makefile so don't add it here. This setting defines the value of BSP_INC_DIRS in Makefile. + none + false + none + + + hal.make.cxx + CXX + UnquotedString + nios2-elf-gcc -xc++ + nios2-elf-gcc -xc++ + makefile_variable + C++ compiler command. + none + false + none + + + hal.make.bsp_cflags_user_flags + BSP_CFLAGS_USER_FLAGS + UnquotedString + none + none + makefile_variable + Custom flags passed to the compiler when compiling C, C++, and .S files. This setting defines the value of BSP_CFLAGS_USER_FLAGS in Makefile. + none + false + none + + + hal.make.ignore_system_derived.sopc_system_id + NONE + Boolean + 0 + 0 + public_mk_define + Enable BSP generation to query SOPC system for system ID. If true ignores export of 'SOPC_SYSID_FLAG += --id=<sysid>' and 'ELF_PATCH_FLAG += --id=<sysid>' to public.mk. + none + false + none + + + hal.make.ignore_system_derived.sopc_system_timestamp + NONE + Boolean + 0 + 0 + public_mk_define + Enable BSP generation to query SOPC system for system timestamp. If true ignores export of 'SOPC_SYSID_FLAG += --timestamp=<timestamp>' and 'ELF_PATCH_FLAG += --timestamp=<timestamp>' to public.mk. + none + false + none + + + hal.make.ignore_system_derived.sopc_system_base_address + NONE + Boolean + 0 + 0 + public_mk_define + Enable BSP generation to query SOPC system for system ID base address. If true ignores export of 'SOPC_SYSID_FLAG += --sidp=<address>' and 'ELF_PATCH_FLAG += --sidp=<address>' to public.mk. + none + false + none + + + hal.make.ignore_system_derived.sopc_simulation_enabled + NONE + Boolean + 0 + 0 + public_mk_define + Enable BSP generation to query if SOPC system has simulation enabled. If true ignores export of 'ELF_PATCH_FLAG += --simulation_enabled' to public.mk. + none + false + none + + + hal.make.ignore_system_derived.fpu_present + NONE + Boolean + 0 + 0 + public_mk_define + Enable BSP generation to query if SOPC system has FPU present. If true ignores export of 'ALT_CFLAGS += -mhard-float' to public.mk if FPU is found in the system. If true ignores export of 'ALT_CFLAGS += -mhard-soft' if FPU is not found in the system. + none + false + none + + + hal.make.ignore_system_derived.hardware_multiplier_present + NONE + Boolean + 0 + 0 + public_mk_define + Enable BSP generation to query if SOPC system has multiplier present. If true ignores export of 'ALT_CFLAGS += -mno-hw-mul' to public.mk if no multiplier is found in the system. If true ignores export of 'ALT_CFLAGS += -mhw-mul' if multiplier is found in the system. + none + false + none + + + hal.make.ignore_system_derived.hardware_mulx_present + NONE + Boolean + 0 + 0 + public_mk_define + Enable BSP generation to query if SOPC system has hardware mulx present. If true ignores export of 'ALT_CFLAGS += -mno-hw-mulx' to public.mk if no mulx is found in the system. If true ignores export of 'ALT_CFLAGS += -mhw-mulx' if mulx is found in the system. + none + false + none + + + hal.make.ignore_system_derived.hardware_divide_present + NONE + Boolean + 0 + 0 + public_mk_define + Enable BSP generation to query if SOPC system has hardware divide present. If true ignores export of 'ALT_CFLAGS += -mno-hw-div' to public.mk if no division is found in system. If true ignores export of 'ALT_CFLAGS += -mhw-div' if division is found in the system. + none + false + none + + + hal.make.ignore_system_derived.debug_core_present + NONE + Boolean + 0 + 0 + public_mk_define + Enable BSP generation to query if SOPC system has a debug core present. If true ignores export of 'CPU_HAS_DEBUG_CORE = 1' to public.mk if a debug core is found in the system. If true ignores export of 'CPU_HAS_DEBUG_CORE = 0' if no debug core is found in the system. + none + false + none + + + hal.make.ignore_system_derived.big_endian + NONE + Boolean + 0 + 0 + public_mk_define + Enable BSP generation to query if SOPC system is big endian. If true ignores export of 'ALT_CFLAGS += -EB' to public.mk if big endian system. If true ignores export of 'ALT_CFLAGS += -EL' if little endian system. + none + false + none + + + hal.make.ignore_system_derived.hardware_fp_cust_inst_divider_present + NONE + Boolean + 0 + 0 + public_mk_define + Enable BSP generation to query if SOPC system floating point custom instruction with a divider is present. If true ignores export of 'ALT_CFLAGS += -mcustom-fpu-cfg=60-2' and 'ALT_LDFLAGS += -mcustom-fpu-cfg=60-2' to public.mk if the custom instruction is found in the system. + none + false + none + + + hal.make.ignore_system_derived.hardware_fp_cust_inst_no_divider_present + NONE + Boolean + 0 + 0 + public_mk_define + Enable BSP generation to query if SOPC system floating point custom instruction without a divider is present. If true ignores export of 'ALT_CFLAGS += -mcustom-fpu-cfg=60-1' and 'ALT_LDFLAGS += -mcustom-fpu-cfg=60-1' to public.mk if the custom instruction is found in the system. + none + false + none + + + hal.enable_exit + ALT_NO_EXIT + Boolean + 1 + 1 + public_mk_define + Add exit() support. This option increases code footprint if your "main()" routine does "return" or call "exit()". If false, adds -DALT_NO_EXIT to ALT_CPPFLAGS in public.mk, and reduces footprint + none + false + none + + + hal.enable_small_c_library + NONE + Boolean + 0 + 0 + public_mk_define + Causes the small newlib (C library) to be used. This reduces code and data footprint at the expense of reduced functionality. Several newlib features are removed such as floating-point support in printf(), stdin input routines, and buffered I/O. The small C library is not compatible with Micrium MicroC/OS-II. If true, adds -msmallc to ALT_LDFLAGS in public.mk. + none + false + common + + + hal.enable_clean_exit + ALT_NO_CLEAN_EXIT + Boolean + 1 + 1 + public_mk_define + When your application exits, close file descriptors, call C++ destructors, etc. Code footprint can be reduced by disabling clean exit. If disabled, adds -DALT_NO_CLEAN_EXIT to ALT_CPPFLAGS and -Wl,--defsym, exit=_exit to ALT_LDFLAGS in public.mk. + none + false + none + + + hal.enable_runtime_stack_checking + ALT_STACK_CHECK + Boolean + 0 + 0 + public_mk_define + Turns on HAL runtime stack checking feature. Enabling this setting causes additional code to be placed into each subroutine call to generate an exception if a stack collision occurs with the heap or statically allocated data. If true, adds -DALT_STACK_CHECK and -mstack-check to ALT_CPPFLAGS in public.mk. + none + false + none + + + hal.enable_gprof + ALT_PROVIDE_GMON + Boolean + 0 + 0 + public_mk_define + Causes code to be compiled with gprof profiling enabled and the application ELF to be linked with the GPROF library. If true, adds -DALT_PROVIDE_GMON to ALT_CPPFLAGS and -pg to ALT_CFLAGS in public.mk. + none + false + common + + + hal.enable_c_plus_plus + ALT_NO_C_PLUS_PLUS + Boolean + 1 + 1 + public_mk_define + Enable support for a subset of the C++ language. This option increases code footprint by adding support for C++ constructors. Certain features, such as multiple inheritance and exceptions are not supported. If false, adds -DALT_NO_C_PLUS_PLUS to ALT_CPPFLAGS in public.mk, and reduces code footprint. + none + false + none + + + hal.enable_reduced_device_drivers + ALT_USE_SMALL_DRIVERS + Boolean + 0 + 0 + public_mk_define + Certain drivers are compiled with reduced functionality to reduce code footprint. Not all drivers observe this setting. The altera_avalon_uart and altera_avalon_jtag_uart drivers switch from interrupt-driven to polled operation. CAUTION: Several device drivers are disabled entirely. These include the altera_avalon_cfi_flash, altera_avalon_epcs_flash_controller, and altera_avalon_lcd_16207 drivers. This can result in certain API (HAL flash access routines) to fail. You can define a symbol provided by each driver to prevent it from being removed. If true, adds -DALT_USE_SMALL_DRIVERS to ALT_CPPFLAGS in public.mk. + none + false + common + + + hal.enable_lightweight_device_driver_api + ALT_USE_DIRECT_DRIVERS + Boolean + 0 + 0 + public_mk_define + Enables lightweight device driver API. This reduces code and data footprint by removing the HAL layer that maps device names (e.g. /dev/uart0) to file descriptors. Instead, driver routines are called directly. The open(), close(), and lseek() routines will always fail if called. The read(), write(), fstat(), ioctl(), and isatty() routines only work for the stdio devices. If true, adds -DALT_USE_DIRECT_DRIVERS to ALT_CPPFLAGS in public.mk. + The Altera Host and read-only ZIP file systems can't be used if hal.enable_lightweight_device_driver_api is true. + false + none + + + hal.enable_mul_div_emulation + ALT_NO_INSTRUCTION_EMULATION + Boolean + 0 + 0 + public_mk_define + Adds code to emulate multiply and divide instructions in case they are executed but aren't present in the CPU. Normally this isn't required because the compiler won't use multiply and divide instructions that aren't present in the CPU. If false, adds -DALT_NO_INSTRUCTION_EMULATION to ALT_CPPFLAGS in public.mk. + none + false + none + + + hal.enable_sim_optimize + ALT_SIM_OPTIMIZE + Boolean + 0 + 0 + public_mk_define + The BSP is compiled with optimizations to speedup HDL simulation such as initializing the cache, clearing the .bss section, and skipping long delay loops. If true, adds -DALT_SIM_OPTIMIZE to ALT_CPPFLAGS in public.mk. + When this setting is true, the BSP shouldn't be used to build applications that are expected to run real hardware. + false + common + + + hal.enable_sopc_sysid_check + NONE + Boolean + 1 + 1 + public_mk_define + Enable SOPC Builder System ID. If a System ID SOPC Builder component is connected to the CPU associated with this BSP, it will be enabled in the creation of command-line arguments to download an ELF to the target. Otherwise, system ID and timestamp values are left out of public.mk for application Makefile "download-elf" target definition. With the system ID check disabled, the Nios II EDS tools will not automatically ensure that the application .elf file (and BSP it is linked against) corresponds to the hardware design on the target. If false, adds --accept-bad-sysid to SOPC_SYSID_FLAG in public.mk. + none + false + none + + + hal.custom_newlib_flags + CUSTOM_NEWLIB_FLAGS + UnquotedString + none + none + public_mk_define + Build a custom version of newlib with the specified space-separated compiler flags. + The custom newlib build will be placed in the &lt;bsp root>/newlib directory, and will be used only for applications that utilize this BSP. + false + none + + + hal.log_flags + ALT_LOG_FLAGS + DecimalNumber + 0 + 0 + public_mk_define + The value is assigned to ALT_LOG_FLAGS in the generated public.mk. See hal.log_port setting description. Values can be -1 through 3. + hal.log_port must be set for this to be used. + false + none + + + ucosii.os_max_tasks + OS_MAX_TASKS + DecimalNumber + 10 + 10 + system_h_define + Maximum number of tasks + none + false + + + + ucosii.os_lowest_prio + OS_LOWEST_PRIO + DecimalNumber + 20 + 20 + system_h_define + Lowest assignable priority + none + false + + + + ucosii.os_thread_safe_newlib + OS_THREAD_SAFE_NEWLIB + Boolean + 1 + 1 + system_h_define + Thread safe C library + none + false + + + + ucosii.miscellaneous.os_arg_chk_en + OS_ARG_CHK_EN + Boolean + 1 + 1 + system_h_define + Enable argument checking + none + false + + + + ucosii.miscellaneous.os_cpu_hooks_en + OS_CPU_HOOKS_EN + Boolean + 1 + 1 + system_h_define + Enable uCOS-II hooks + none + false + + + + ucosii.miscellaneous.os_debug_en + OS_DEBUG_EN + Boolean + 1 + 1 + system_h_define + Enable debug variables + none + false + + + + ucosii.miscellaneous.os_sched_lock_en + OS_SCHED_LOCK_EN + Boolean + 1 + 1 + system_h_define + Include code for OSSchedLock() and OSSchedUnlock() + none + false + + + + ucosii.miscellaneous.os_task_stat_en + OS_TASK_STAT_EN + Boolean + 1 + 1 + system_h_define + Enable statistics task + none + false + + + + ucosii.miscellaneous.os_task_stat_stk_chk_en + OS_TASK_STAT_STK_CHK_EN + Boolean + 1 + 1 + system_h_define + Check task stacks from statistics task + none + false + + + + ucosii.miscellaneous.os_tick_step_en + OS_TICK_STEP_EN + Boolean + 1 + 1 + system_h_define + Enable tick stepping feature for uCOS-View + none + false + + + + ucosii.miscellaneous.os_event_name_size + OS_EVENT_NAME_SIZE + DecimalNumber + 32 + 32 + system_h_define + Size of name of Event Control Block groups + none + false + + + + ucosii.miscellaneous.os_max_events + OS_MAX_EVENTS + DecimalNumber + 60 + 60 + system_h_define + Maximum number of event control blocks + none + false + + + + ucosii.miscellaneous.os_task_idle_stk_size + OS_TASK_IDLE_STK_SIZE + DecimalNumber + 512 + 512 + system_h_define + Idle task stack size + none + false + + + + ucosii.miscellaneous.os_task_stat_stk_size + OS_TASK_STAT_STK_SIZE + DecimalNumber + 512 + 512 + system_h_define + Statistics task stack size + none + false + + + + ucosii.task.os_task_change_prio_en + OS_TASK_CHANGE_PRIO_EN + Boolean + 1 + 1 + system_h_define + Include code for OSTaskChangePrio() + none + false + + + + ucosii.task.os_task_create_en + OS_TASK_CREATE_EN + Boolean + 1 + 1 + system_h_define + Include code for OSTaskCreate() + none + false + + + + ucosii.task.os_task_create_ext_en + OS_TASK_CREATE_EXT_EN + Boolean + 1 + 1 + system_h_define + Include code for OSTaskCreateExt() + none + false + + + + ucosii.task.os_task_del_en + OS_TASK_DEL_EN + Boolean + 1 + 1 + system_h_define + Include code for OSTaskDel() + none + false + + + + ucosii.task.os_task_name_size + OS_TASK_NAME_SIZE + DecimalNumber + 32 + 32 + system_h_define + Size of task name + none + false + + + + ucosii.task.os_task_profile_en + OS_TASK_PROFILE_EN + Boolean + 1 + 1 + system_h_define + Include data structure for run-time task profiling + none + false + + + + ucosii.task.os_task_query_en + OS_TASK_QUERY_EN + Boolean + 1 + 1 + system_h_define + Include code for OSTaskQuery + none + false + + + + ucosii.task.os_task_suspend_en + OS_TASK_SUSPEND_EN + Boolean + 1 + 1 + system_h_define + Include code for OSTaskSuspend() and OSTaskResume() + none + false + + + + ucosii.task.os_task_sw_hook_en + OS_TASK_SW_HOOK_EN + Boolean + 1 + 1 + system_h_define + Include code for OSTaskSwHook() + none + false + + + + ucosii.time.os_time_tick_hook_en + OS_TIME_TICK_HOOK_EN + Boolean + 1 + 1 + system_h_define + Include code for OSTimeTickHook() + none + false + + + + ucosii.time.os_time_dly_resume_en + OS_TIME_DLY_RESUME_EN + Boolean + 1 + 1 + system_h_define + Include code for OSTimeDlyResume() + none + false + + + + ucosii.time.os_time_dly_hmsm_en + OS_TIME_DLY_HMSM_EN + Boolean + 1 + 1 + system_h_define + Include code for OSTimeDlyHMSM() + none + false + + + + ucosii.time.os_time_get_set_en + OS_TIME_GET_SET_EN + Boolean + 1 + 1 + system_h_define + Include code for OSTimeGet and OSTimeSet() + none + false + + + + ucosii.os_flag_en + OS_FLAG_EN + Boolean + 1 + 1 + system_h_define + Enable code for Event Flags. CAUTION: This is required by the HAL and many Altera device drivers. + none + false + + + + ucosii.event_flag.os_flag_wait_clr_en + OS_FLAG_WAIT_CLR_EN + Boolean + 1 + 1 + system_h_define + Include code for Wait on Clear Event Flags. CAUTION: This is required by the HAL and many Altera device drivers. + none + false + + + + ucosii.event_flag.os_flag_accept_en + OS_FLAG_ACCEPT_EN + Boolean + 1 + 1 + system_h_define + Include code for OSFlagAccept(). CAUTION: This is required by the HAL and many Altera device drivers. + none + false + + + + ucosii.event_flag.os_flag_del_en + OS_FLAG_DEL_EN + Boolean + 1 + 1 + system_h_define + Include code for OSFlagDel(). CAUTION: This is required by the HAL and many Altera device drivers. + none + false + + + + ucosii.event_flag.os_flag_query_en + OS_FLAG_QUERY_EN + Boolean + 1 + 1 + system_h_define + Include code for OSFlagQuery(). CAUTION: This is required by the HAL and many Altera device drivers. + none + false + + + + ucosii.event_flag.os_flag_name_size + OS_FLAG_NAME_SIZE + DecimalNumber + 32 + 32 + system_h_define + Size of name of Event Flags group. CAUTION: This is required by the HAL and many Altera device drivers; use caution in reducing this value. + none + false + + + + ucosii.event_flag.os_flags_nbits + OS_FLAGS_NBITS + DecimalNumber + 16 + 16 + system_h_define + Event Flag bits (8,16,32). CAUTION: This is required by the HAL and many Altera device drivers; use caution in changing this value. + none + false + + + + ucosii.event_flag.os_max_flags + OS_MAX_FLAGS + DecimalNumber + 20 + 20 + system_h_define + Maximum number of Event Flags groups. CAUTION: This is required by the HAL and many Altera device drivers; use caution in reducing this value. + none + false + + + + ucosii.os_mutex_en + OS_MUTEX_EN + Boolean + 1 + 1 + system_h_define + Enable code for Mutex Semaphores + none + false + + + + ucosii.mutex.os_mutex_accept_en + OS_MUTEX_ACCEPT_EN + Boolean + 1 + 1 + system_h_define + Include code for OSMutexAccept() + none + false + + + + ucosii.mutex.os_mutex_del_en + OS_MUTEX_DEL_EN + Boolean + 1 + 1 + system_h_define + Include code for OSMutexDel() + none + false + + + + ucosii.mutex.os_mutex_query_en + OS_MUTEX_QUERY_EN + Boolean + 1 + 1 + system_h_define + Include code for OSMutexQuery + none + false + + + + ucosii.os_sem_en + OS_SEM_EN + Boolean + 1 + 1 + system_h_define + Enable code for semaphores. CAUTION: This is required by the HAL and many Altera device drivers. + none + false + + + + ucosii.semaphore.os_sem_accept_en + OS_SEM_ACCEPT_EN + Boolean + 1 + 1 + system_h_define + Include code for OSSemAccept(). CAUTION: This is required by the HAL and many Altera device drivers. + none + false + + + + ucosii.semaphore.os_sem_set_en + OS_SEM_SET_EN + Boolean + 1 + 1 + system_h_define + Include code for OSSemSet(). CAUTION: This is required by the HAL and many Altera device drivers. + none + false + + + + ucosii.semaphore.os_sem_del_en + OS_SEM_DEL_EN + Boolean + 1 + 1 + system_h_define + Include code for OSSemDel(). CAUTION: This is required by the HAL and many Altera device drivers. + none + false + + + + ucosii.semaphore.os_sem_query_en + OS_SEM_QUERY_EN + Boolean + 1 + 1 + system_h_define + Include code for OSSemQuery(). CAUTION: This is required by the HAL and many Altera device drivers. + none + false + + + + ucosii.os_mbox_en + OS_MBOX_EN + Boolean + 1 + 1 + system_h_define + Enable code for mailboxes + none + false + + + + ucosii.mailbox.os_mbox_accept_en + OS_MBOX_ACCEPT_EN + Boolean + 1 + 1 + system_h_define + Include code for OSMboxAccept() + none + false + + + + ucosii.mailbox.os_mbox_del_en + OS_MBOX_DEL_EN + Boolean + 1 + 1 + system_h_define + Include code for OSMboxDel() + none + false + + + + ucosii.mailbox.os_mbox_post_en + OS_MBOX_POST_EN + Boolean + 1 + 1 + system_h_define + Include code for OSMboxPost() + none + false + + + + ucosii.mailbox.os_mbox_post_opt_en + OS_MBOX_POST_OPT_EN + Boolean + 1 + 1 + system_h_define + Include code for OSMboxPostOpt() + none + false + + + + ucosii.mailbox.os_mbox_query_en + OS_MBOX_QUERY_EN + Boolean + 1 + 1 + system_h_define + Include code for OSMboxQuery() + none + false + + + + ucosii.os_q_en + OS_Q_EN + Boolean + 1 + 1 + system_h_define + Enable code for Queues + none + false + + + + ucosii.queue.os_q_accept_en + OS_Q_ACCEPT_EN + Boolean + 1 + 1 + system_h_define + Include code for OSQAccept() + none + false + + + + ucosii.queue.os_q_del_en + OS_Q_DEL_EN + Boolean + 1 + 1 + system_h_define + Include code for OSQDel() + none + false + + + + ucosii.queue.os_q_flush_en + OS_Q_FLUSH_EN + Boolean + 1 + 1 + system_h_define + Include code for OSQFlush() + none + false + + + + ucosii.queue.os_q_post_en + OS_Q_POST_EN + Boolean + 1 + 1 + system_h_define + Include code of OSQFlush() + none + false + + + + ucosii.queue.os_q_post_front_en + OS_Q_POST_FRONT_EN + Boolean + 1 + 1 + system_h_define + Include code for OSQPostFront() + none + false + + + + ucosii.queue.os_q_post_opt_en + OS_Q_POST_OPT_EN + Boolean + 1 + 1 + system_h_define + Include code for OSQPostOpt() + none + false + + + + ucosii.queue.os_q_query_en + OS_Q_QUERY_EN + Boolean + 1 + 1 + system_h_define + Include code for OSQQuery() + none + false + + + + ucosii.queue.os_max_qs + OS_MAX_QS + DecimalNumber + 20 + 20 + system_h_define + Maximum number of Queue Control Blocks + none + false + + + + ucosii.os_mem_en + OS_MEM_EN + Boolean + 1 + 1 + system_h_define + Enable code for memory management + none + false + + + + ucosii.memory.os_mem_query_en + OS_MEM_QUERY_EN + Boolean + 1 + 1 + system_h_define + Include code for OSMemQuery() + none + false + + + + ucosii.memory.os_mem_name_size + OS_MEM_NAME_SIZE + DecimalNumber + 32 + 32 + system_h_define + Size of memory partition name + none + false + + + + ucosii.memory.os_max_mem_part + OS_MAX_MEM_PART + DecimalNumber + 60 + 60 + system_h_define + Maximum number of memory partitions + none + false + + + + ucosii.os_tmr_en + OS_TMR_EN + Boolean + 0 + 0 + system_h_define + Enable code for timers + none + false + + + + ucosii.timer.os_task_tmr_stk_size + OS_TASK_TMR_STK_SIZE + DecimalNumber + 512 + 512 + system_h_define + Stack size for timer task + none + false + + + + ucosii.timer.os_task_tmr_prio + OS_TASK_TMR_PRIO + DecimalNumber + 0 + 0 + system_h_define + Priority of timer task (0=highest) + none + false + + + + ucosii.timer.os_tmr_cfg_max + OS_TMR_CFG_MAX + DecimalNumber + 16 + 16 + system_h_define + Maximum number of timers + none + false + + + + ucosii.timer.os_tmr_cfg_name_size + OS_TMR_CFG_NAME_SIZE + DecimalNumber + 16 + 16 + system_h_define + Size of timer name + none + false + + + + ucosii.timer.os_tmr_cfg_ticks_per_sec + OS_TMR_CFG_TICKS_PER_SEC + DecimalNumber + 10 + 10 + system_h_define + Rate at which timer management task runs (Hz) + none + false + + + + ucosii.timer.os_tmr_cfg_wheel_size + OS_TMR_CFG_WHEEL_SIZE + DecimalNumber + 2 + 2 + system_h_define + Size of timer wheel (number of spokes) + none + false + + + + altera_avalon_uart_driver.enable_small_driver + ALTERA_AVALON_UART_SMALL + BooleanDefineOnly + false + false + public_mk_define + Small-footprint (polled mode) driver + none + false + + + + altera_avalon_uart_driver.enable_ioctl + ALTERA_AVALON_UART_USE_IOCTL + BooleanDefineOnly + false + false + public_mk_define + Enable driver ioctl() support. This feature is not compatible with the 'small' driver; ioctl() support will not be compiled if either the UART 'enable_small_driver' or HAL 'enable_reduced_device_drivers' settings are enabled. + none + false + + + + altera_avalon_jtag_uart_driver.enable_small_driver + ALTERA_AVALON_JTAG_UART_SMALL + BooleanDefineOnly + false + false + public_mk_define + Small-footprint (polled mode) driver + none + false + + + + sdram + 0x01000000 - 0x01FFFFFF + 16777216 + memory + + + pio_led + 0x02001000 - 0x0200101F + 32 + + + + uart_0 + 0x02001020 - 0x0200103F + 32 + printable + + + sys_clk_timer + 0x02001040 - 0x0200105F + 32 + timer + + + pio_motor_rst + 0x02001060 - 0x0200106F + 16 + + + + pio_sw + 0x02001070 - 0x0200107F + 16 + + + + pio_key + 0x02001080 - 0x0200108F + 16 + + + + rs232_motor + 0x02001090 - 0x02001097 + 8 + + + + jtag_uart_0 + 0x02001098 - 0x0200109F + 8 + printable + + + sysid + 0x020010A0 - 0x020010A7 + 8 + + + + .text + sdram + + + .rodata + sdram + + + .rwdata + sdram + + + .bss + sdram + + + .heap + sdram + + + .stack + sdram + + \ No newline at end of file diff --git a/MCTEST/DE0-nano-HD/Software/MCTest_bsp/summary.html b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/summary.html new file mode 100644 index 00000000..6dd65452 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/summary.html @@ -0,0 +1,3943 @@ + +Altera Nios II BSP Summary + +

BSP Description

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BSP Type:ucosii
SOPC Design File:C:\Users\gongal\Desktop\MCTEST\DE0-nano-HD\system.sopcinfo
Quartus JDI File:default
CPU:cpu
BSP Settings File:settings.bsp
BSP Version:default
BSP Generated On:14-Mar-2014 4:49:59 PM
BSP Generated Timestamp:1394837399894
BSP Generated Location:C:\Users\gongal\Desktop\MCTEST\DE0-nano-HD\Software\MCTest_bsp
+
+

Nios II Memory Map

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Slave DescriptorAddress RangeSizeAttributes
sysid0x020010A0 - 0x020010A78 
jtag_uart_00x02001098 - 0x0200109F8printable
rs232_motor0x02001090 - 0x020010978 
pio_key0x02001080 - 0x0200108F16 
pio_sw0x02001070 - 0x0200107F16 
pio_motor_rst0x02001060 - 0x0200106F16 
sys_clk_timer0x02001040 - 0x0200105F32timer
uart_00x02001020 - 0x0200103F32printable
pio_led0x02001000 - 0x0200101F32 
sdram0x01000000 - 0x01FFFFFF16777216memory
+
+
+

Linker Regions

+ + + + +
RegionAddress RangeSizeMemoryOffset
+
+
+

Linker Section Mappings

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SectionRegion
.textsdram
.rodatasdram
.rwdatasdram
.bsssdram
.heapsdram
.stacksdram
+

Settings

+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:altera_avalon_jtag_uart_driver.enable_small_driver
Identifier:ALTERA_AVALON_JTAG_UART_SMALL
Default Value:false
Value:false
Type:BooleanDefineOnly
Destination:public_mk_define
Description:Small-footprint (polled mode) driver
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:altera_avalon_uart_driver.enable_ioctl
Identifier:ALTERA_AVALON_UART_USE_IOCTL
Default Value:false
Value:false
Type:BooleanDefineOnly
Destination:public_mk_define
Description:Enable driver ioctl() support. This feature is not compatible with the 'small' driver; ioctl() support will not be compiled if either the UART 'enable_small_driver' or HAL 'enable_reduced_device_drivers' settings are enabled.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:altera_avalon_uart_driver.enable_small_driver
Identifier:ALTERA_AVALON_UART_SMALL
Default Value:false
Value:false
Type:BooleanDefineOnly
Destination:public_mk_define
Description:Small-footprint (polled mode) driver
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.custom_newlib_flags
Identifier:CUSTOM_NEWLIB_FLAGS
Default Value:none
Value:none
Type:UnquotedString
Destination:public_mk_define
Description:Build a custom version of newlib with the specified space-separated compiler flags.
Restrictions:The custom newlib build will be placed in the &lt;bsp root>/newlib directory, and will be used only for applications that utilize this BSP.
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.enable_c_plus_plus
Identifier:ALT_NO_C_PLUS_PLUS
Default Value:1
Value:1
Type:Boolean
Destination:public_mk_define
Description:Enable support for a subset of the C++ language. This option increases code footprint by adding support for C++ constructors. Certain features, such as multiple inheritance and exceptions are not supported. If false, adds -DALT_NO_C_PLUS_PLUS to ALT_CPPFLAGS in public.mk, and reduces code footprint.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.enable_clean_exit
Identifier:ALT_NO_CLEAN_EXIT
Default Value:1
Value:1
Type:Boolean
Destination:public_mk_define
Description:When your application exits, close file descriptors, call C++ destructors, etc. Code footprint can be reduced by disabling clean exit. If disabled, adds -DALT_NO_CLEAN_EXIT to ALT_CPPFLAGS and -Wl,--defsym, exit=_exit to ALT_LDFLAGS in public.mk.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.enable_exit
Identifier:ALT_NO_EXIT
Default Value:1
Value:1
Type:Boolean
Destination:public_mk_define
Description:Add exit() support. This option increases code footprint if your "main()" routine does "return" or call "exit()". If false, adds -DALT_NO_EXIT to ALT_CPPFLAGS in public.mk, and reduces footprint
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.enable_gprof
Identifier:ALT_PROVIDE_GMON
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Causes code to be compiled with gprof profiling enabled and the application ELF to be linked with the GPROF library. If true, adds -DALT_PROVIDE_GMON to ALT_CPPFLAGS and -pg to ALT_CFLAGS in public.mk.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.enable_instruction_related_exceptions_api
Identifier:ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API
Default Value:false
Value:false
Type:BooleanDefineOnly
Destination:system_h_define
Description:Enables API for registering handlers to service instruction-related exceptions. Enabling this setting increases the size of the exception entry code.
Restrictions:These exception types can be generated if various processor options are enabled, such as the MMU, MPU, or other advanced exception types.
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.enable_lightweight_device_driver_api
Identifier:ALT_USE_DIRECT_DRIVERS
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Enables lightweight device driver API. This reduces code and data footprint by removing the HAL layer that maps device names (e.g. /dev/uart0) to file descriptors. Instead, driver routines are called directly. The open(), close(), and lseek() routines will always fail if called. The read(), write(), fstat(), ioctl(), and isatty() routines only work for the stdio devices. If true, adds -DALT_USE_DIRECT_DRIVERS to ALT_CPPFLAGS in public.mk.
Restrictions:The Altera Host and read-only ZIP file systems can't be used if hal.enable_lightweight_device_driver_api is true.
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.enable_mul_div_emulation
Identifier:ALT_NO_INSTRUCTION_EMULATION
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Adds code to emulate multiply and divide instructions in case they are executed but aren't present in the CPU. Normally this isn't required because the compiler won't use multiply and divide instructions that aren't present in the CPU. If false, adds -DALT_NO_INSTRUCTION_EMULATION to ALT_CPPFLAGS in public.mk.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.enable_reduced_device_drivers
Identifier:ALT_USE_SMALL_DRIVERS
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Certain drivers are compiled with reduced functionality to reduce code footprint. Not all drivers observe this setting. The altera_avalon_uart and altera_avalon_jtag_uart drivers switch from interrupt-driven to polled operation. CAUTION: Several device drivers are disabled entirely. These include the altera_avalon_cfi_flash, altera_avalon_epcs_flash_controller, and altera_avalon_lcd_16207 drivers. This can result in certain API (HAL flash access routines) to fail. You can define a symbol provided by each driver to prevent it from being removed. If true, adds -DALT_USE_SMALL_DRIVERS to ALT_CPPFLAGS in public.mk.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.enable_runtime_stack_checking
Identifier:ALT_STACK_CHECK
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Turns on HAL runtime stack checking feature. Enabling this setting causes additional code to be placed into each subroutine call to generate an exception if a stack collision occurs with the heap or statically allocated data. If true, adds -DALT_STACK_CHECK and -mstack-check to ALT_CPPFLAGS in public.mk.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.enable_sim_optimize
Identifier:ALT_SIM_OPTIMIZE
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:The BSP is compiled with optimizations to speedup HDL simulation such as initializing the cache, clearing the .bss section, and skipping long delay loops. If true, adds -DALT_SIM_OPTIMIZE to ALT_CPPFLAGS in public.mk.
Restrictions:When this setting is true, the BSP shouldn't be used to build applications that are expected to run real hardware.
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.enable_small_c_library
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Causes the small newlib (C library) to be used. This reduces code and data footprint at the expense of reduced functionality. Several newlib features are removed such as floating-point support in printf(), stdin input routines, and buffered I/O. The small C library is not compatible with Micrium MicroC/OS-II. If true, adds -msmallc to ALT_LDFLAGS in public.mk.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.enable_sopc_sysid_check
Identifier:NONE
Default Value:1
Value:1
Type:Boolean
Destination:public_mk_define
Description:Enable SOPC Builder System ID. If a System ID SOPC Builder component is connected to the CPU associated with this BSP, it will be enabled in the creation of command-line arguments to download an ELF to the target. Otherwise, system ID and timestamp values are left out of public.mk for application Makefile "download-elf" target definition. With the system ID check disabled, the Nios II EDS tools will not automatically ensure that the application .elf file (and BSP it is linked against) corresponds to the hardware design on the target. If false, adds --accept-bad-sysid to SOPC_SYSID_FLAG in public.mk.
Restrictions:none
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+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.linker.allow_code_at_reset
Identifier:ALT_ALLOW_CODE_AT_RESET
Default Value:0
Value:1
Type:Boolean
Destination:none
Description:Indicates if initialization code is allowed at the reset address. If true, defines the macro ALT_ALLOW_CODE_AT_RESET in linker.h.
Restrictions:If true, defines the macro ALT_ALLOW_CODE_AT_RESET in linker.h. This setting is typically false if an external bootloader (e.g. flash bootloader) is present.
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+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.linker.enable_alt_load
Identifier:NONE
Default Value:0
Value:1
Type:Boolean
Destination:none
Description:Enables the alt_load() facility. The alt_load() facility copies sections from the .text memory into RAM. If true, this setting sets up the VMA/LMA of sections in linker.x to allow them to be loaded into the .text memory.
Restrictions:This setting is typically false if an external bootloader (e.g. flash bootloader) is present.
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+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.linker.enable_alt_load_copy_exceptions
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:none
Description:Causes the alt_load() facility to copy the .exceptions section. If true, this setting defines the macro ALT_LOAD_COPY_EXCEPTIONS in linker.h.
Restrictions:none
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+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.linker.enable_alt_load_copy_rodata
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:none
Description:Causes the alt_load() facility to copy the .rodata section. If true, this setting defines the macro ALT_LOAD_COPY_RODATA in linker.h.
Restrictions:none
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+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.linker.enable_alt_load_copy_rwdata
Identifier:NONE
Default Value:0
Value:1
Type:Boolean
Destination:none
Description:Causes the alt_load() facility to copy the .rwdata section. If true, this setting defines the macro ALT_LOAD_COPY_RWDATA in linker.h.
Restrictions:none
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+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.linker.enable_exception_stack
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:none
Description:Enables use of a separate exception stack. If true, defines the macro ALT_EXCEPTION_STACK in linker.h, adds a memory region called exception_stack to linker.x, and provides the symbols __alt_exception_stack_pointer and __alt_exception_stack_limit in linker.x.
Restrictions:The hal.linker.exception_stack_size and hal.linker.exception_stack_memory_region_name settings must also be valid. This setting must be false for MicroC/OS-II BSPs. The exception stack can be used to improve interrupt and other exception performance if the EIC is *not* used.
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+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.linker.enable_interrupt_stack
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:none
Description:Enables use of a separate interrupt stack. If true, defines the macro ALT_INTERRUPT_STACK in linker.h, adds a memory region called interrupt_stack to linker.x, and provides the symbols __alt_interrupt_stack_pointer and __alt_interrupt_stack_limit in linker.x.
Restrictions:The hal.linker.interrupt_stack_size and hal.linker.interrupt_stack_memory_region_name settings must also be valid. This setting must be false for MicroC/OS-II BSPs. Only enable if the EIC is used exclusively. The exception stack can be used to improve interrupt and other exception performance if the EIC is *not* used.
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+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.linker.exception_stack_memory_region_name
Identifier:NONE
Default Value:none
Value:sdram
Type:UnquotedString
Destination:none
Description:Name of the existing memory region that will be divided up to create the 'exception_stack' memory region. The selected region name will be adjusted automatically when the BSP is generated to create the 'exception_stack' memory region.
Restrictions:Only used if hal.linker.enable_exception_stack is true.
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+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.linker.exception_stack_size
Identifier:NONE
Default Value:1024
Value:1024
Type:DecimalNumber
Destination:none
Description:Size of the exception stack in bytes.
Restrictions:Only used if hal.linker.enable_exception_stack is true.
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Setting Name:hal.linker.interrupt_stack_memory_region_name
Identifier:NONE
Default Value:none
Value:sdram
Type:UnquotedString
Destination:none
Description:Name of the existing memory region that will be divided up to create the 'interrupt_stack' memory region. The selected region name will be adjusted automatically when the BSP is generated to create the 'interrupt_stack' memory region.
Restrictions:Only used if hal.linker.enable_interrupt_stack is true.
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+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.linker.interrupt_stack_size
Identifier:NONE
Default Value:1024
Value:1024
Type:DecimalNumber
Destination:none
Description:Size of the interrupt stack in bytes.
Restrictions:Only used if hal.linker.enable_interrupt_stack is true.
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+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.log_flags
Identifier:ALT_LOG_FLAGS
Default Value:0
Value:0
Type:DecimalNumber
Destination:public_mk_define
Description:The value is assigned to ALT_LOG_FLAGS in the generated public.mk. See hal.log_port setting description. Values can be -1 through 3.
Restrictions:hal.log_port must be set for this to be used.
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+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.log_port
Identifier:NONE
Default Value:none
Value:none
Type:UnquotedString
Destination:public_mk_define
Description:Slave descriptor of debug logging character-mode device. If defined, it enables extra debug messages in the HAL source. This setting is used by the ALT_LOG_PORT family of defines in system.h.
Restrictions:none
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+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.ar
Identifier:AR
Default Value:nios2-elf-ar
Value:nios2-elf-ar
Type:UnquotedString
Destination:makefile_variable
Description:Archiver command. Creates library files.
Restrictions:none
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+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.ar_post_process
Identifier:AR_POST_PROCESS
Default Value:none
Value:none
Type:UnquotedString
Destination:makefile_variable
Description:Command executed after archiver execution.
Restrictions:none
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+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.ar_pre_process
Identifier:AR_PRE_PROCESS
Default Value:none
Value:none
Type:UnquotedString
Destination:makefile_variable
Description:Command executed before archiver execution.
Restrictions:none
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+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.as
Identifier:AS
Default Value:nios2-elf-gcc
Value:nios2-elf-gcc
Type:UnquotedString
Destination:makefile_variable
Description:Assembler command. Note that CC is used for .S files.
Restrictions:none
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+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.as_post_process
Identifier:AS_POST_PROCESS
Default Value:none
Value:none
Type:UnquotedString
Destination:makefile_variable
Description:Command executed after each assembly file is compiled.
Restrictions:none
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+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.as_pre_process
Identifier:AS_PRE_PROCESS
Default Value:none
Value:none
Type:UnquotedString
Destination:makefile_variable
Description:Command executed before each assembly file is compiled.
Restrictions:none
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+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.bsp_arflags
Identifier:BSP_ARFLAGS
Default Value:-src
Value:-src
Type:UnquotedString
Destination:makefile_variable
Description:Custom flags only passed to the archiver. This content of this variable is directly passed to the archiver rather than the more standard "ARFLAGS". The reason for this is that GNU Make assumes some default content in ARFLAGS. This setting defines the value of BSP_ARFLAGS in Makefile.
Restrictions:none
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+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.bsp_asflags
Identifier:BSP_ASFLAGS
Default Value:-Wa,-gdwarf2
Value:-Wa,-gdwarf2
Type:UnquotedString
Destination:makefile_variable
Description:Custom flags only passed to the assembler. This setting defines the value of BSP_ASFLAGS in Makefile.
Restrictions:none
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+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.bsp_cflags_debug
Identifier:BSP_CFLAGS_DEBUG
Default Value:-g
Value:-g
Type:UnquotedString
Destination:makefile_variable
Description:C/C++ compiler debug level. '-g' provides the default set of debug symbols typically required to debug a typical application. Omitting '-g' removes debug symbols from the ELF. This setting defines the value of BSP_CFLAGS_DEBUG in Makefile.
Restrictions:none
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+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.bsp_cflags_defined_symbols
Identifier:BSP_CFLAGS_DEFINED_SYMBOLS
Default Value:none
Value:none
Type:UnquotedString
Destination:makefile_variable
Description:Preprocessor macros to define. A macro definition in this setting has the same effect as a "#define" in source code. Adding "-DALT_DEBUG" to this setting has the same effect as "#define ALT_DEBUG" in a souce file. Adding "-DFOO=1" to this setting is equivalent to the macro "#define FOO 1" in a source file. Macros defined with this setting are applied to all .S, .c, and C++ files in the BSP. This setting defines the value of BSP_CFLAGS_DEFINED_SYMBOLS in the BSP Makefile.
Restrictions:none
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+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.bsp_cflags_optimization
Identifier:BSP_CFLAGS_OPTIMIZATION
Default Value:-O0
Value:-O0
Type:UnquotedString
Destination:makefile_variable
Description:C/C++ compiler optimization level. "-O0" = no optimization,"-O2" = "normal" optimization, etc. "-O0" is recommended for code that you want to debug since compiler optimization can remove variables and produce non-sequential execution of code while debugging. This setting defines the value of BSP_CFLAGS_OPTIMIZATION in Makefile.
Restrictions:none
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+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.bsp_cflags_undefined_symbols
Identifier:BSP_CFLAGS_UNDEFINED_SYMBOLS
Default Value:none
Value:none
Type:UnquotedString
Destination:makefile_variable
Description:Preprocessor macros to undefine. Undefined macros are similar to defined macros, but replicate the "#undef" directive in source code. To undefine the macro FOO use the syntax "-u FOO" in this setting. This is equivalent to "#undef FOO" in a source file. Note: the syntax differs from macro definition (there is a space, i.e. "-u FOO" versus "-DFOO"). Macros defined with this setting are applied to all .S, .c, and C++ files in the BSP. This setting defines the value of BSP_CFLAGS_UNDEFINED_SYMBOLS in the BSP Makefile.
Restrictions:none
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+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.bsp_cflags_user_flags
Identifier:BSP_CFLAGS_USER_FLAGS
Default Value:none
Value:none
Type:UnquotedString
Destination:makefile_variable
Description:Custom flags passed to the compiler when compiling C, C++, and .S files. This setting defines the value of BSP_CFLAGS_USER_FLAGS in Makefile.
Restrictions:none
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+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.bsp_cflags_warnings
Identifier:BSP_CFLAGS_WARNINGS
Default Value:-Wall
Value:-Wall
Type:UnquotedString
Destination:makefile_variable
Description:C/C++ compiler warning level. "-Wall" is commonly used.This setting defines the value of BSP_CFLAGS_WARNINGS in Makefile.
Restrictions:none
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+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.bsp_cxx_flags
Identifier:BSP_CXXFLAGS
Default Value:none
Value:none
Type:UnquotedString
Destination:makefile_variable
Description:Custom flags only passed to the C++ compiler. This setting defines the value of BSP_CXXFLAGS in Makefile.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.bsp_inc_dirs
Identifier:BSP_INC_DIRS
Default Value:none
Value:none
Type:UnquotedString
Destination:makefile_variable
Description:Space separated list of extra include directories to scan for header files. Directories are relative to the top-level BSP directory. The -I prefix's added by the makefile so don't add it here. This setting defines the value of BSP_INC_DIRS in Makefile.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.build_post_process
Identifier:BUILD_POST_PROCESS
Default Value:none
Value:none
Type:UnquotedString
Destination:makefile_variable
Description:Command executed after BSP built.
Restrictions:none
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+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.build_pre_process
Identifier:BUILD_PRE_PROCESS
Default Value:none
Value:none
Type:UnquotedString
Destination:makefile_variable
Description:Command executed before BSP built.
Restrictions:none
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+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.cc
Identifier:CC
Default Value:nios2-elf-gcc -xc
Value:nios2-elf-gcc -xc
Type:UnquotedString
Destination:makefile_variable
Description:C compiler command.
Restrictions:none
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+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.cc_post_process
Identifier:CC_POST_PROCESS
Default Value:none
Value:none
Type:UnquotedString
Destination:makefile_variable
Description:Command executed after each .c/.S file is compiled.
Restrictions:none
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+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.cc_pre_process
Identifier:CC_PRE_PROCESS
Default Value:none
Value:none
Type:UnquotedString
Destination:makefile_variable
Description:Command executed before each .c/.S file is compiled.
Restrictions:none
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+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.cxx
Identifier:CXX
Default Value:nios2-elf-gcc -xc++
Value:nios2-elf-gcc -xc++
Type:UnquotedString
Destination:makefile_variable
Description:C++ compiler command.
Restrictions:none
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+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.cxx_post_process
Identifier:CXX_POST_PROCESS
Default Value:none
Value:none
Type:UnquotedString
Destination:makefile_variable
Description:Command executed before each C++ file is compiled.
Restrictions:none
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+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.cxx_pre_process
Identifier:CXX_PRE_PROCESS
Default Value:none
Value:none
Type:UnquotedString
Destination:makefile_variable
Description:Command executed before each C++ file is compiled.
Restrictions:none
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+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.ignore_system_derived.big_endian
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Enable BSP generation to query if SOPC system is big endian. If true ignores export of 'ALT_CFLAGS += -EB' to public.mk if big endian system. If true ignores export of 'ALT_CFLAGS += -EL' if little endian system.
Restrictions:none
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+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.ignore_system_derived.debug_core_present
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Enable BSP generation to query if SOPC system has a debug core present. If true ignores export of 'CPU_HAS_DEBUG_CORE = 1' to public.mk if a debug core is found in the system. If true ignores export of 'CPU_HAS_DEBUG_CORE = 0' if no debug core is found in the system.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.ignore_system_derived.fpu_present
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Enable BSP generation to query if SOPC system has FPU present. If true ignores export of 'ALT_CFLAGS += -mhard-float' to public.mk if FPU is found in the system. If true ignores export of 'ALT_CFLAGS += -mhard-soft' if FPU is not found in the system.
Restrictions:none
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+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.ignore_system_derived.hardware_divide_present
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Enable BSP generation to query if SOPC system has hardware divide present. If true ignores export of 'ALT_CFLAGS += -mno-hw-div' to public.mk if no division is found in system. If true ignores export of 'ALT_CFLAGS += -mhw-div' if division is found in the system.
Restrictions:none
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+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.ignore_system_derived.hardware_fp_cust_inst_divider_present
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Enable BSP generation to query if SOPC system floating point custom instruction with a divider is present. If true ignores export of 'ALT_CFLAGS += -mcustom-fpu-cfg=60-2' and 'ALT_LDFLAGS += -mcustom-fpu-cfg=60-2' to public.mk if the custom instruction is found in the system.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.ignore_system_derived.hardware_fp_cust_inst_no_divider_present
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Enable BSP generation to query if SOPC system floating point custom instruction without a divider is present. If true ignores export of 'ALT_CFLAGS += -mcustom-fpu-cfg=60-1' and 'ALT_LDFLAGS += -mcustom-fpu-cfg=60-1' to public.mk if the custom instruction is found in the system.
Restrictions:none
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+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.ignore_system_derived.hardware_multiplier_present
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Enable BSP generation to query if SOPC system has multiplier present. If true ignores export of 'ALT_CFLAGS += -mno-hw-mul' to public.mk if no multiplier is found in the system. If true ignores export of 'ALT_CFLAGS += -mhw-mul' if multiplier is found in the system.
Restrictions:none
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+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.ignore_system_derived.hardware_mulx_present
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Enable BSP generation to query if SOPC system has hardware mulx present. If true ignores export of 'ALT_CFLAGS += -mno-hw-mulx' to public.mk if no mulx is found in the system. If true ignores export of 'ALT_CFLAGS += -mhw-mulx' if mulx is found in the system.
Restrictions:none
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+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.ignore_system_derived.sopc_simulation_enabled
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Enable BSP generation to query if SOPC system has simulation enabled. If true ignores export of 'ELF_PATCH_FLAG += --simulation_enabled' to public.mk.
Restrictions:none
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+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.ignore_system_derived.sopc_system_base_address
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Enable BSP generation to query SOPC system for system ID base address. If true ignores export of 'SOPC_SYSID_FLAG += --sidp=<address>' and 'ELF_PATCH_FLAG += --sidp=<address>' to public.mk.
Restrictions:none
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+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.ignore_system_derived.sopc_system_id
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Enable BSP generation to query SOPC system for system ID. If true ignores export of 'SOPC_SYSID_FLAG += --id=<sysid>' and 'ELF_PATCH_FLAG += --id=<sysid>' to public.mk.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.ignore_system_derived.sopc_system_timestamp
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Enable BSP generation to query SOPC system for system timestamp. If true ignores export of 'SOPC_SYSID_FLAG += --timestamp=<timestamp>' and 'ELF_PATCH_FLAG += --timestamp=<timestamp>' to public.mk.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.rm
Identifier:RM
Default Value:rm -f
Value:rm -f
Type:UnquotedString
Destination:makefile_variable
Description:Command used to remove files during 'clean' target.
Restrictions:none
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+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.max_file_descriptors
Identifier:ALT_MAX_FD
Default Value:32
Value:32
Type:DecimalNumber
Destination:system_h_define
Description:Determines the number of file descriptors statically allocated. This setting defines the value of ALT_MAX_FD in system.h.
Restrictions:If hal.enable_lightweight_device_driver_api is true, there are no file descriptors so this setting is ignored. If hal.enable_lightweight_device_driver_api is false, this setting must be at least 4 because HAL needs a file descriptor for /dev/null, /dev/stdin, /dev/stdout, and /dev/stderr.
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.stderr
Identifier:NONE
Default Value:none
Value:jtag_uart_0
Type:UnquotedString
Destination:system_h_define
Description:Slave descriptor of STDERR character-mode device. This setting is used by the ALT_STDERR family of defines in system.h.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.stdin
Identifier:NONE
Default Value:none
Value:jtag_uart_0
Type:UnquotedString
Destination:system_h_define
Description:Slave descriptor of STDIN character-mode device. This setting is used by the ALT_STDIN family of defines in system.h.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.stdout
Identifier:NONE
Default Value:none
Value:jtag_uart_0
Type:UnquotedString
Destination:system_h_define
Description:Slave descriptor of STDOUT character-mode device. This setting is used by the ALT_STDOUT family of defines in system.h.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.sys_clk_timer
Identifier:ALT_SYS_CLK
Default Value:none
Value:sys_clk_timer
Type:UnquotedString
Destination:system_h_define
Description:Slave descriptor of the system clock timer device. This device provides a periodic interrupt ("tick") and is typically required for RTOS use. This setting defines the value of ALT_SYS_CLK in system.h.
Restrictions:none
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+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.timestamp_timer
Identifier:ALT_TIMESTAMP_CLK
Default Value:none
Value:none
Type:UnquotedString
Destination:system_h_define
Description:Slave descriptor of timestamp timer device. This device is used by Altera HAL timestamp drivers for high-resolution time measurement. This setting defines the value of ALT_TIMESTAMP_CLK in system.h.
Restrictions:none
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+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.event_flag.os_flag_accept_en
Identifier:OS_FLAG_ACCEPT_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSFlagAccept(). CAUTION: This is required by the HAL and many Altera device drivers.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.event_flag.os_flag_del_en
Identifier:OS_FLAG_DEL_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSFlagDel(). CAUTION: This is required by the HAL and many Altera device drivers.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.event_flag.os_flag_name_size
Identifier:OS_FLAG_NAME_SIZE
Default Value:32
Value:32
Type:DecimalNumber
Destination:system_h_define
Description:Size of name of Event Flags group. CAUTION: This is required by the HAL and many Altera device drivers; use caution in reducing this value.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.event_flag.os_flag_query_en
Identifier:OS_FLAG_QUERY_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSFlagQuery(). CAUTION: This is required by the HAL and many Altera device drivers.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.event_flag.os_flag_wait_clr_en
Identifier:OS_FLAG_WAIT_CLR_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for Wait on Clear Event Flags. CAUTION: This is required by the HAL and many Altera device drivers.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.event_flag.os_flags_nbits
Identifier:OS_FLAGS_NBITS
Default Value:16
Value:16
Type:DecimalNumber
Destination:system_h_define
Description:Event Flag bits (8,16,32). CAUTION: This is required by the HAL and many Altera device drivers; use caution in changing this value.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.event_flag.os_max_flags
Identifier:OS_MAX_FLAGS
Default Value:20
Value:20
Type:DecimalNumber
Destination:system_h_define
Description:Maximum number of Event Flags groups. CAUTION: This is required by the HAL and many Altera device drivers; use caution in reducing this value.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.mailbox.os_mbox_accept_en
Identifier:OS_MBOX_ACCEPT_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSMboxAccept()
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.mailbox.os_mbox_del_en
Identifier:OS_MBOX_DEL_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSMboxDel()
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.mailbox.os_mbox_post_en
Identifier:OS_MBOX_POST_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSMboxPost()
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.mailbox.os_mbox_post_opt_en
Identifier:OS_MBOX_POST_OPT_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSMboxPostOpt()
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.mailbox.os_mbox_query_en
Identifier:OS_MBOX_QUERY_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSMboxQuery()
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.memory.os_max_mem_part
Identifier:OS_MAX_MEM_PART
Default Value:60
Value:60
Type:DecimalNumber
Destination:system_h_define
Description:Maximum number of memory partitions
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.memory.os_mem_name_size
Identifier:OS_MEM_NAME_SIZE
Default Value:32
Value:32
Type:DecimalNumber
Destination:system_h_define
Description:Size of memory partition name
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.memory.os_mem_query_en
Identifier:OS_MEM_QUERY_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSMemQuery()
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.miscellaneous.os_arg_chk_en
Identifier:OS_ARG_CHK_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Enable argument checking
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.miscellaneous.os_cpu_hooks_en
Identifier:OS_CPU_HOOKS_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Enable uCOS-II hooks
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.miscellaneous.os_debug_en
Identifier:OS_DEBUG_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Enable debug variables
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.miscellaneous.os_event_name_size
Identifier:OS_EVENT_NAME_SIZE
Default Value:32
Value:32
Type:DecimalNumber
Destination:system_h_define
Description:Size of name of Event Control Block groups
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.miscellaneous.os_max_events
Identifier:OS_MAX_EVENTS
Default Value:60
Value:60
Type:DecimalNumber
Destination:system_h_define
Description:Maximum number of event control blocks
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.miscellaneous.os_sched_lock_en
Identifier:OS_SCHED_LOCK_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSSchedLock() and OSSchedUnlock()
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.miscellaneous.os_task_idle_stk_size
Identifier:OS_TASK_IDLE_STK_SIZE
Default Value:512
Value:512
Type:DecimalNumber
Destination:system_h_define
Description:Idle task stack size
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.miscellaneous.os_task_stat_en
Identifier:OS_TASK_STAT_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Enable statistics task
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.miscellaneous.os_task_stat_stk_chk_en
Identifier:OS_TASK_STAT_STK_CHK_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Check task stacks from statistics task
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.miscellaneous.os_task_stat_stk_size
Identifier:OS_TASK_STAT_STK_SIZE
Default Value:512
Value:512
Type:DecimalNumber
Destination:system_h_define
Description:Statistics task stack size
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.miscellaneous.os_tick_step_en
Identifier:OS_TICK_STEP_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Enable tick stepping feature for uCOS-View
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.mutex.os_mutex_accept_en
Identifier:OS_MUTEX_ACCEPT_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSMutexAccept()
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.mutex.os_mutex_del_en
Identifier:OS_MUTEX_DEL_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSMutexDel()
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.mutex.os_mutex_query_en
Identifier:OS_MUTEX_QUERY_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSMutexQuery
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.os_flag_en
Identifier:OS_FLAG_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Enable code for Event Flags. CAUTION: This is required by the HAL and many Altera device drivers.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.os_lowest_prio
Identifier:OS_LOWEST_PRIO
Default Value:20
Value:20
Type:DecimalNumber
Destination:system_h_define
Description:Lowest assignable priority
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.os_max_tasks
Identifier:OS_MAX_TASKS
Default Value:10
Value:10
Type:DecimalNumber
Destination:system_h_define
Description:Maximum number of tasks
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.os_mbox_en
Identifier:OS_MBOX_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Enable code for mailboxes
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.os_mem_en
Identifier:OS_MEM_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Enable code for memory management
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.os_mutex_en
Identifier:OS_MUTEX_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Enable code for Mutex Semaphores
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.os_q_en
Identifier:OS_Q_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Enable code for Queues
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.os_sem_en
Identifier:OS_SEM_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Enable code for semaphores. CAUTION: This is required by the HAL and many Altera device drivers.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.os_thread_safe_newlib
Identifier:OS_THREAD_SAFE_NEWLIB
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Thread safe C library
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.os_tmr_en
Identifier:OS_TMR_EN
Default Value:0
Value:0
Type:Boolean
Destination:system_h_define
Description:Enable code for timers
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.queue.os_max_qs
Identifier:OS_MAX_QS
Default Value:20
Value:20
Type:DecimalNumber
Destination:system_h_define
Description:Maximum number of Queue Control Blocks
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.queue.os_q_accept_en
Identifier:OS_Q_ACCEPT_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSQAccept()
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.queue.os_q_del_en
Identifier:OS_Q_DEL_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSQDel()
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.queue.os_q_flush_en
Identifier:OS_Q_FLUSH_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSQFlush()
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.queue.os_q_post_en
Identifier:OS_Q_POST_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code of OSQFlush()
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.queue.os_q_post_front_en
Identifier:OS_Q_POST_FRONT_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSQPostFront()
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.queue.os_q_post_opt_en
Identifier:OS_Q_POST_OPT_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSQPostOpt()
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.queue.os_q_query_en
Identifier:OS_Q_QUERY_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSQQuery()
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.semaphore.os_sem_accept_en
Identifier:OS_SEM_ACCEPT_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSSemAccept(). CAUTION: This is required by the HAL and many Altera device drivers.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.semaphore.os_sem_del_en
Identifier:OS_SEM_DEL_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSSemDel(). CAUTION: This is required by the HAL and many Altera device drivers.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.semaphore.os_sem_query_en
Identifier:OS_SEM_QUERY_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSSemQuery(). CAUTION: This is required by the HAL and many Altera device drivers.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.semaphore.os_sem_set_en
Identifier:OS_SEM_SET_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSSemSet(). CAUTION: This is required by the HAL and many Altera device drivers.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.task.os_task_change_prio_en
Identifier:OS_TASK_CHANGE_PRIO_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSTaskChangePrio()
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.task.os_task_create_en
Identifier:OS_TASK_CREATE_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSTaskCreate()
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.task.os_task_create_ext_en
Identifier:OS_TASK_CREATE_EXT_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSTaskCreateExt()
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.task.os_task_del_en
Identifier:OS_TASK_DEL_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSTaskDel()
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.task.os_task_name_size
Identifier:OS_TASK_NAME_SIZE
Default Value:32
Value:32
Type:DecimalNumber
Destination:system_h_define
Description:Size of task name
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.task.os_task_profile_en
Identifier:OS_TASK_PROFILE_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include data structure for run-time task profiling
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.task.os_task_query_en
Identifier:OS_TASK_QUERY_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSTaskQuery
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.task.os_task_suspend_en
Identifier:OS_TASK_SUSPEND_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSTaskSuspend() and OSTaskResume()
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.task.os_task_sw_hook_en
Identifier:OS_TASK_SW_HOOK_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSTaskSwHook()
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.time.os_time_dly_hmsm_en
Identifier:OS_TIME_DLY_HMSM_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSTimeDlyHMSM()
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.time.os_time_dly_resume_en
Identifier:OS_TIME_DLY_RESUME_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSTimeDlyResume()
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.time.os_time_get_set_en
Identifier:OS_TIME_GET_SET_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSTimeGet and OSTimeSet()
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.time.os_time_tick_hook_en
Identifier:OS_TIME_TICK_HOOK_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSTimeTickHook()
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.timer.os_task_tmr_prio
Identifier:OS_TASK_TMR_PRIO
Default Value:0
Value:0
Type:DecimalNumber
Destination:system_h_define
Description:Priority of timer task (0=highest)
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.timer.os_task_tmr_stk_size
Identifier:OS_TASK_TMR_STK_SIZE
Default Value:512
Value:512
Type:DecimalNumber
Destination:system_h_define
Description:Stack size for timer task
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.timer.os_tmr_cfg_max
Identifier:OS_TMR_CFG_MAX
Default Value:16
Value:16
Type:DecimalNumber
Destination:system_h_define
Description:Maximum number of timers
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.timer.os_tmr_cfg_name_size
Identifier:OS_TMR_CFG_NAME_SIZE
Default Value:16
Value:16
Type:DecimalNumber
Destination:system_h_define
Description:Size of timer name
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.timer.os_tmr_cfg_ticks_per_sec
Identifier:OS_TMR_CFG_TICKS_PER_SEC
Default Value:10
Value:10
Type:DecimalNumber
Destination:system_h_define
Description:Rate at which timer management task runs (Hz)
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.timer.os_tmr_cfg_wheel_size
Identifier:OS_TMR_CFG_WHEEL_SIZE
Default Value:2
Value:2
Type:DecimalNumber
Destination:system_h_define
Description:Size of timer wheel (number of spokes)
Restrictions:none
+
+
+
+ + diff --git a/MCTEST/DE0-nano-HD/Software/MCTest_bsp/system.h b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/system.h new file mode 100644 index 00000000..8b2d4534 --- /dev/null +++ b/MCTEST/DE0-nano-HD/Software/MCTest_bsp/system.h @@ -0,0 +1,509 @@ +/* + * system.h - SOPC Builder system and BSP software package information + * + * Machine generated for CPU 'cpu' in SOPC Builder design 'system' + * SOPC Builder design path: C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo + * + * Generated: Thu Mar 06 10:04:03 MST 2014 + */ + +/* + * DO NOT MODIFY THIS FILE + * + * Changing this file will have subtle consequences + * which will almost certainly lead to a nonfunctioning + * system. If you do modify this file, be aware that your + * changes will be overwritten and lost when this file + * is generated again. + * + * DO NOT MODIFY THIS FILE + */ + +/* + * License Agreement + * + * Copyright (c) 2008 + * Altera Corporation, San Jose, California, USA. + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * This agreement shall be governed in all respects by the laws of the State + * of California and by the laws of the United States of America. + */ + +#ifndef __SYSTEM_H_ +#define __SYSTEM_H_ + +/* Include definitions from linker script generator */ +#include "linker.h" + + +/* + * CPU configuration + * + */ + +#define ALT_CPU_ARCHITECTURE "altera_nios2_qsys" +#define ALT_CPU_BIG_ENDIAN 0 +#define ALT_CPU_BREAK_ADDR 0x2000820 +#define ALT_CPU_CPU_FREQ 100000000u +#define ALT_CPU_CPU_ID_SIZE 1 +#define ALT_CPU_CPU_ID_VALUE 0x00000000 +#define ALT_CPU_CPU_IMPLEMENTATION "fast" +#define ALT_CPU_DATA_ADDR_WIDTH 0x1a +#define ALT_CPU_DCACHE_LINE_SIZE 32 +#define ALT_CPU_DCACHE_LINE_SIZE_LOG2 5 +#define ALT_CPU_DCACHE_SIZE 4096 +#define ALT_CPU_EXCEPTION_ADDR 0x1000020 +#define ALT_CPU_FLUSHDA_SUPPORTED +#define ALT_CPU_FREQ 100000000 +#define ALT_CPU_HARDWARE_DIVIDE_PRESENT 0 +#define ALT_CPU_HARDWARE_MULTIPLY_PRESENT 1 +#define ALT_CPU_HARDWARE_MULX_PRESENT 0 +#define ALT_CPU_HAS_DEBUG_CORE 1 +#define ALT_CPU_HAS_DEBUG_STUB +#define ALT_CPU_HAS_JMPI_INSTRUCTION +#define ALT_CPU_ICACHE_LINE_SIZE 32 +#define ALT_CPU_ICACHE_LINE_SIZE_LOG2 5 +#define ALT_CPU_ICACHE_SIZE 8192 +#define ALT_CPU_INITDA_SUPPORTED +#define ALT_CPU_INST_ADDR_WIDTH 0x1a +#define ALT_CPU_NAME "cpu" +#define ALT_CPU_NUM_OF_SHADOW_REG_SETS 0 +#define ALT_CPU_RESET_ADDR 0x1000000 + + +/* + * CPU configuration (with legacy prefix - don't use these anymore) + * + */ + +#define NIOS2_BIG_ENDIAN 0 +#define NIOS2_BREAK_ADDR 0x2000820 +#define NIOS2_CPU_FREQ 100000000u +#define NIOS2_CPU_ID_SIZE 1 +#define NIOS2_CPU_ID_VALUE 0x00000000 +#define NIOS2_CPU_IMPLEMENTATION "fast" +#define NIOS2_DATA_ADDR_WIDTH 0x1a +#define NIOS2_DCACHE_LINE_SIZE 32 +#define NIOS2_DCACHE_LINE_SIZE_LOG2 5 +#define NIOS2_DCACHE_SIZE 4096 +#define NIOS2_EXCEPTION_ADDR 0x1000020 +#define NIOS2_FLUSHDA_SUPPORTED +#define NIOS2_HARDWARE_DIVIDE_PRESENT 0 +#define NIOS2_HARDWARE_MULTIPLY_PRESENT 1 +#define NIOS2_HARDWARE_MULX_PRESENT 0 +#define NIOS2_HAS_DEBUG_CORE 1 +#define NIOS2_HAS_DEBUG_STUB +#define NIOS2_HAS_JMPI_INSTRUCTION +#define NIOS2_ICACHE_LINE_SIZE 32 +#define NIOS2_ICACHE_LINE_SIZE_LOG2 5 +#define NIOS2_ICACHE_SIZE 8192 +#define NIOS2_INITDA_SUPPORTED +#define NIOS2_INST_ADDR_WIDTH 0x1a +#define NIOS2_NUM_OF_SHADOW_REG_SETS 0 +#define NIOS2_RESET_ADDR 0x1000000 + + +/* + * Define for each module class mastered by the CPU + * + */ + +#define __ALTERA_AVALON_JTAG_UART +#define __ALTERA_AVALON_NEW_SDRAM_CONTROLLER +#define __ALTERA_AVALON_PIO +#define __ALTERA_AVALON_SYSID_QSYS +#define __ALTERA_AVALON_TIMER +#define __ALTERA_AVALON_UART +#define __ALTERA_NIOS2_QSYS +#define __ALTERA_UP_AVALON_RS232 + + +/* + * System configuration + * + */ + +#define ALT_DEVICE_FAMILY "Cyclone IV E" +#define ALT_IRQ_BASE NULL +#define ALT_LEGACY_INTERRUPT_API_PRESENT +#define ALT_LOG_PORT "/dev/null" +#define ALT_LOG_PORT_BASE 0x0 +#define ALT_LOG_PORT_DEV null +#define ALT_LOG_PORT_TYPE "" +#define ALT_NUM_EXTERNAL_INTERRUPT_CONTROLLERS 0 +#define ALT_NUM_INTERNAL_INTERRUPT_CONTROLLERS 1 +#define ALT_NUM_INTERRUPT_CONTROLLERS 1 +#define ALT_STDERR "/dev/jtag_uart_0" +#define ALT_STDERR_BASE 0x2001098 +#define ALT_STDERR_DEV jtag_uart_0 +#define ALT_STDERR_IS_JTAG_UART +#define ALT_STDERR_PRESENT +#define ALT_STDERR_TYPE "altera_avalon_jtag_uart" +#define ALT_STDIN "/dev/jtag_uart_0" +#define ALT_STDIN_BASE 0x2001098 +#define ALT_STDIN_DEV jtag_uart_0 +#define ALT_STDIN_IS_JTAG_UART +#define ALT_STDIN_PRESENT +#define ALT_STDIN_TYPE "altera_avalon_jtag_uart" +#define ALT_STDOUT "/dev/jtag_uart_0" +#define ALT_STDOUT_BASE 0x2001098 +#define ALT_STDOUT_DEV jtag_uart_0 +#define ALT_STDOUT_IS_JTAG_UART +#define ALT_STDOUT_PRESENT +#define ALT_STDOUT_TYPE "altera_avalon_jtag_uart" +#define ALT_SYSTEM_NAME "system" + + +/* + * hal configuration + * + */ + +#define ALT_MAX_FD 32 +#define ALT_SYS_CLK SYS_CLK_TIMER +#define ALT_TIMESTAMP_CLK none + + +/* + * jtag_uart_0 configuration + * + */ + +#define ALT_MODULE_CLASS_jtag_uart_0 altera_avalon_jtag_uart +#define JTAG_UART_0_BASE 0x2001098 +#define JTAG_UART_0_IRQ 14 +#define JTAG_UART_0_IRQ_INTERRUPT_CONTROLLER_ID 0 +#define JTAG_UART_0_NAME "/dev/jtag_uart_0" +#define JTAG_UART_0_READ_DEPTH 64 +#define JTAG_UART_0_READ_THRESHOLD 8 +#define JTAG_UART_0_SPAN 8 +#define JTAG_UART_0_TYPE "altera_avalon_jtag_uart" +#define JTAG_UART_0_WRITE_DEPTH 64 +#define JTAG_UART_0_WRITE_THRESHOLD 8 + + +/* + * pio_key configuration + * + */ + +#define ALT_MODULE_CLASS_pio_key altera_avalon_pio +#define PIO_KEY_BASE 0x2001080 +#define PIO_KEY_BIT_CLEARING_EDGE_REGISTER 0 +#define PIO_KEY_BIT_MODIFYING_OUTPUT_REGISTER 0 +#define PIO_KEY_CAPTURE 0 +#define PIO_KEY_DATA_WIDTH 2 +#define PIO_KEY_DO_TEST_BENCH_WIRING 0 +#define PIO_KEY_DRIVEN_SIM_VALUE 0x0 +#define PIO_KEY_EDGE_TYPE "NONE" +#define PIO_KEY_FREQ 100000000u +#define PIO_KEY_HAS_IN 1 +#define PIO_KEY_HAS_OUT 0 +#define PIO_KEY_HAS_TRI 0 +#define PIO_KEY_IRQ -1 +#define PIO_KEY_IRQ_INTERRUPT_CONTROLLER_ID -1 +#define PIO_KEY_IRQ_TYPE "NONE" +#define PIO_KEY_NAME "/dev/pio_key" +#define PIO_KEY_RESET_VALUE 0x0 +#define PIO_KEY_SPAN 16 +#define PIO_KEY_TYPE "altera_avalon_pio" + + +/* + * pio_led configuration + * + */ + +#define ALT_MODULE_CLASS_pio_led altera_avalon_pio +#define PIO_LED_BASE 0x2001000 +#define PIO_LED_BIT_CLEARING_EDGE_REGISTER 0 +#define PIO_LED_BIT_MODIFYING_OUTPUT_REGISTER 1 +#define PIO_LED_CAPTURE 0 +#define PIO_LED_DATA_WIDTH 7 +#define PIO_LED_DO_TEST_BENCH_WIRING 0 +#define PIO_LED_DRIVEN_SIM_VALUE 0x0 +#define PIO_LED_EDGE_TYPE "NONE" +#define PIO_LED_FREQ 100000000u +#define PIO_LED_HAS_IN 0 +#define PIO_LED_HAS_OUT 1 +#define PIO_LED_HAS_TRI 0 +#define PIO_LED_IRQ -1 +#define PIO_LED_IRQ_INTERRUPT_CONTROLLER_ID -1 +#define PIO_LED_IRQ_TYPE "NONE" +#define PIO_LED_NAME "/dev/pio_led" +#define PIO_LED_RESET_VALUE 0x0 +#define PIO_LED_SPAN 32 +#define PIO_LED_TYPE "altera_avalon_pio" + + +/* + * pio_motor_rst configuration + * + */ + +#define ALT_MODULE_CLASS_pio_motor_rst altera_avalon_pio +#define PIO_MOTOR_RST_BASE 0x2001060 +#define PIO_MOTOR_RST_BIT_CLEARING_EDGE_REGISTER 0 +#define PIO_MOTOR_RST_BIT_MODIFYING_OUTPUT_REGISTER 0 +#define PIO_MOTOR_RST_CAPTURE 0 +#define PIO_MOTOR_RST_DATA_WIDTH 1 +#define PIO_MOTOR_RST_DO_TEST_BENCH_WIRING 0 +#define PIO_MOTOR_RST_DRIVEN_SIM_VALUE 0x0 +#define PIO_MOTOR_RST_EDGE_TYPE "NONE" +#define PIO_MOTOR_RST_FREQ 100000000u +#define PIO_MOTOR_RST_HAS_IN 0 +#define PIO_MOTOR_RST_HAS_OUT 1 +#define PIO_MOTOR_RST_HAS_TRI 0 +#define PIO_MOTOR_RST_IRQ -1 +#define PIO_MOTOR_RST_IRQ_INTERRUPT_CONTROLLER_ID -1 +#define PIO_MOTOR_RST_IRQ_TYPE "NONE" +#define PIO_MOTOR_RST_NAME "/dev/pio_motor_rst" +#define PIO_MOTOR_RST_RESET_VALUE 0x0 +#define PIO_MOTOR_RST_SPAN 16 +#define PIO_MOTOR_RST_TYPE "altera_avalon_pio" + + +/* + * pio_sw configuration + * + */ + +#define ALT_MODULE_CLASS_pio_sw altera_avalon_pio +#define PIO_SW_BASE 0x2001070 +#define PIO_SW_BIT_CLEARING_EDGE_REGISTER 0 +#define PIO_SW_BIT_MODIFYING_OUTPUT_REGISTER 0 +#define PIO_SW_CAPTURE 0 +#define PIO_SW_DATA_WIDTH 4 +#define PIO_SW_DO_TEST_BENCH_WIRING 0 +#define PIO_SW_DRIVEN_SIM_VALUE 0x0 +#define PIO_SW_EDGE_TYPE "NONE" +#define PIO_SW_FREQ 100000000u +#define PIO_SW_HAS_IN 1 +#define PIO_SW_HAS_OUT 0 +#define PIO_SW_HAS_TRI 0 +#define PIO_SW_IRQ -1 +#define PIO_SW_IRQ_INTERRUPT_CONTROLLER_ID -1 +#define PIO_SW_IRQ_TYPE "NONE" +#define PIO_SW_NAME "/dev/pio_sw" +#define PIO_SW_RESET_VALUE 0x0 +#define PIO_SW_SPAN 16 +#define PIO_SW_TYPE "altera_avalon_pio" + + +/* + * rs232_motor configuration + * + */ + +#define ALT_MODULE_CLASS_rs232_motor altera_up_avalon_rs232 +#define RS232_MOTOR_BASE 0x2001090 +#define RS232_MOTOR_IRQ 5 +#define RS232_MOTOR_IRQ_INTERRUPT_CONTROLLER_ID 0 +#define RS232_MOTOR_NAME "/dev/rs232_motor" +#define RS232_MOTOR_SPAN 8 +#define RS232_MOTOR_TYPE "altera_up_avalon_rs232" + + +/* + * sdram configuration + * + */ + +#define ALT_MODULE_CLASS_sdram altera_avalon_new_sdram_controller +#define SDRAM_BASE 0x1000000 +#define SDRAM_CAS_LATENCY 3 +#define SDRAM_CONTENTS_INFO "" +#define SDRAM_INIT_NOP_DELAY 0.0 +#define SDRAM_INIT_REFRESH_COMMANDS 8 +#define SDRAM_IRQ -1 +#define SDRAM_IRQ_INTERRUPT_CONTROLLER_ID -1 +#define SDRAM_IS_INITIALIZED 1 +#define SDRAM_NAME "/dev/sdram" +#define SDRAM_POWERUP_DELAY 200.0 +#define SDRAM_REFRESH_PERIOD 7.8125 +#define SDRAM_REGISTER_DATA_IN 1 +#define SDRAM_SDRAM_ADDR_WIDTH 0x17 +#define SDRAM_SDRAM_BANK_WIDTH 2 +#define SDRAM_SDRAM_COL_WIDTH 8 +#define SDRAM_SDRAM_DATA_WIDTH 16 +#define SDRAM_SDRAM_NUM_BANKS 4 +#define SDRAM_SDRAM_NUM_CHIPSELECTS 1 +#define SDRAM_SDRAM_ROW_WIDTH 13 +#define SDRAM_SHARED_DATA 0 +#define SDRAM_SIM_MODEL_BASE 0 +#define SDRAM_SPAN 16777216 +#define SDRAM_STARVATION_INDICATOR 0 +#define SDRAM_TRISTATE_BRIDGE_SLAVE "" +#define SDRAM_TYPE "altera_avalon_new_sdram_controller" +#define SDRAM_T_AC 5.5 +#define SDRAM_T_MRD 3 +#define SDRAM_T_RCD 20.0 +#define SDRAM_T_RFC 70.0 +#define SDRAM_T_RP 20.0 +#define SDRAM_T_WR 14.0 + + +/* + * sys_clk_timer configuration + * + */ + +#define ALT_MODULE_CLASS_sys_clk_timer altera_avalon_timer +#define SYS_CLK_TIMER_ALWAYS_RUN 0 +#define SYS_CLK_TIMER_BASE 0x2001040 +#define SYS_CLK_TIMER_COUNTER_SIZE 32 +#define SYS_CLK_TIMER_FIXED_PERIOD 0 +#define SYS_CLK_TIMER_FREQ 100000000u +#define SYS_CLK_TIMER_IRQ 1 +#define SYS_CLK_TIMER_IRQ_INTERRUPT_CONTROLLER_ID 0 +#define SYS_CLK_TIMER_LOAD_VALUE 99999ull +#define SYS_CLK_TIMER_MULT 0.0010 +#define SYS_CLK_TIMER_NAME "/dev/sys_clk_timer" +#define SYS_CLK_TIMER_PERIOD 1 +#define SYS_CLK_TIMER_PERIOD_UNITS "ms" +#define SYS_CLK_TIMER_RESET_OUTPUT 0 +#define SYS_CLK_TIMER_SNAPSHOT 1 +#define SYS_CLK_TIMER_SPAN 32 +#define SYS_CLK_TIMER_TICKS_PER_SEC 1000u +#define SYS_CLK_TIMER_TIMEOUT_PULSE_OUTPUT 0 +#define SYS_CLK_TIMER_TYPE "altera_avalon_timer" + + +/* + * sysid configuration + * + */ + +#define ALT_MODULE_CLASS_sysid altera_avalon_sysid_qsys +#define SYSID_BASE 0x20010a0 +#define SYSID_ID 0 +#define SYSID_IRQ -1 +#define SYSID_IRQ_INTERRUPT_CONTROLLER_ID -1 +#define SYSID_NAME "/dev/sysid" +#define SYSID_SPAN 8 +#define SYSID_TIMESTAMP 1394124174 +#define SYSID_TYPE "altera_avalon_sysid_qsys" + + +/* + * uart_0 configuration + * + */ + +#define ALT_MODULE_CLASS_uart_0 altera_avalon_uart +#define UART_0_BASE 0x2001020 +#define UART_0_BAUD 115200 +#define UART_0_DATA_BITS 8 +#define UART_0_FIXED_BAUD 0 +#define UART_0_FREQ 100000000u +#define UART_0_IRQ 4 +#define UART_0_IRQ_INTERRUPT_CONTROLLER_ID 0 +#define UART_0_NAME "/dev/uart_0" +#define UART_0_PARITY 'N' +#define UART_0_SIM_CHAR_STREAM "" +#define UART_0_SIM_TRUE_BAUD 0 +#define UART_0_SPAN 32 +#define UART_0_STOP_BITS 1 +#define UART_0_SYNC_REG_DEPTH 2 +#define UART_0_TYPE "altera_avalon_uart" +#define UART_0_USE_CTS_RTS 0 +#define UART_0_USE_EOP_REGISTER 0 + + +/* + * ucosii configuration + * + */ + +#define OS_ARG_CHK_EN 1 +#define OS_CPU_HOOKS_EN 1 +#define OS_DEBUG_EN 1 +#define OS_EVENT_NAME_SIZE 32 +#define OS_FLAGS_NBITS 16 +#define OS_FLAG_ACCEPT_EN 1 +#define OS_FLAG_DEL_EN 1 +#define OS_FLAG_EN 1 +#define OS_FLAG_NAME_SIZE 32 +#define OS_FLAG_QUERY_EN 1 +#define OS_FLAG_WAIT_CLR_EN 1 +#define OS_LOWEST_PRIO 20 +#define OS_MAX_EVENTS 60 +#define OS_MAX_FLAGS 20 +#define OS_MAX_MEM_PART 60 +#define OS_MAX_QS 20 +#define OS_MAX_TASKS 10 +#define OS_MBOX_ACCEPT_EN 1 +#define OS_MBOX_DEL_EN 1 +#define OS_MBOX_EN 1 +#define OS_MBOX_POST_EN 1 +#define OS_MBOX_POST_OPT_EN 1 +#define OS_MBOX_QUERY_EN 1 +#define OS_MEM_EN 1 +#define OS_MEM_NAME_SIZE 32 +#define OS_MEM_QUERY_EN 1 +#define OS_MUTEX_ACCEPT_EN 1 +#define OS_MUTEX_DEL_EN 1 +#define OS_MUTEX_EN 1 +#define OS_MUTEX_QUERY_EN 1 +#define OS_Q_ACCEPT_EN 1 +#define OS_Q_DEL_EN 1 +#define OS_Q_EN 1 +#define OS_Q_FLUSH_EN 1 +#define OS_Q_POST_EN 1 +#define OS_Q_POST_FRONT_EN 1 +#define OS_Q_POST_OPT_EN 1 +#define OS_Q_QUERY_EN 1 +#define OS_SCHED_LOCK_EN 1 +#define OS_SEM_ACCEPT_EN 1 +#define OS_SEM_DEL_EN 1 +#define OS_SEM_EN 1 +#define OS_SEM_QUERY_EN 1 +#define OS_SEM_SET_EN 1 +#define OS_TASK_CHANGE_PRIO_EN 1 +#define OS_TASK_CREATE_EN 1 +#define OS_TASK_CREATE_EXT_EN 1 +#define OS_TASK_DEL_EN 1 +#define OS_TASK_IDLE_STK_SIZE 512 +#define OS_TASK_NAME_SIZE 32 +#define OS_TASK_PROFILE_EN 1 +#define OS_TASK_QUERY_EN 1 +#define OS_TASK_STAT_EN 1 +#define OS_TASK_STAT_STK_CHK_EN 1 +#define OS_TASK_STAT_STK_SIZE 512 +#define OS_TASK_SUSPEND_EN 1 +#define OS_TASK_SW_HOOK_EN 1 +#define OS_TASK_TMR_PRIO 0 +#define OS_TASK_TMR_STK_SIZE 512 +#define OS_THREAD_SAFE_NEWLIB 1 +#define OS_TICKS_PER_SEC SYS_CLK_TIMER_TICKS_PER_SEC +#define OS_TICK_STEP_EN 1 +#define OS_TIME_DLY_HMSM_EN 1 +#define OS_TIME_DLY_RESUME_EN 1 +#define OS_TIME_GET_SET_EN 1 +#define OS_TIME_TICK_HOOK_EN 1 +#define OS_TMR_CFG_MAX 16 +#define OS_TMR_CFG_NAME_SIZE 16 +#define OS_TMR_CFG_TICKS_PER_SEC 10 +#define OS_TMR_CFG_WHEEL_SIZE 2 +#define OS_TMR_EN 0 + +#endif /* __SYSTEM_H_ */ diff --git a/MCTEST/DE0-nano-HD/db/a_dpfifo_q131.tdf b/MCTEST/DE0-nano-HD/db/a_dpfifo_q131.tdf new file mode 100644 index 00000000..84eb944c --- /dev/null +++ b/MCTEST/DE0-nano-HD/db/a_dpfifo_q131.tdf @@ -0,0 +1,79 @@ +--a_dpfifo ALLOW_RWCYCLE_WHEN_FULL="OFF" DEVICE_FAMILY="Cyclone IV E" LPM_NUMWORDS=64 LPM_SHOWAHEAD="OFF" lpm_width=8 lpm_widthu=6 OVERFLOW_CHECKING="OFF" UNDERFLOW_CHECKING="OFF" aclr clock data empty full q rreq sclr usedw wreq CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 CYCLONEII_M4K_COMPATIBILITY="ON" LOW_POWER_MODE="AUTO" lpm_hint="RAM_BLOCK_TYPE=AUTO" RAM_BLOCK_TYPE="AUTO" +--VERSION_BEGIN 12.1SP1 cbx_altdpram 2013:01:31:18:05:07:SJ cbx_altsyncram 2013:01:31:18:05:07:SJ cbx_cycloneii 2013:01:31:18:05:07:SJ cbx_fifo_common 2013:01:31:18:05:07:SJ cbx_lpm_add_sub 2013:01:31:18:05:07:SJ cbx_lpm_compare 2013:01:31:18:05:07:SJ cbx_lpm_counter 2013:01:31:18:05:07:SJ cbx_lpm_decode 2013:01:31:18:05:07:SJ cbx_lpm_mux 2013:01:31:18:05:07:SJ cbx_mgl 2013:01:31:18:08:27:SJ cbx_scfifo 2013:01:31:18:05:07:SJ cbx_stratix 2013:01:31:18:05:07:SJ cbx_stratixii 2013:01:31:18:05:07:SJ cbx_stratixiii 2013:01:31:18:05:07:SJ cbx_stratixv 2013:01:31:18:05:07:SJ cbx_util_mgl 2013:01:31:18:05:07:SJ VERSION_END + + +-- Copyright (C) 1991-2012 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +FUNCTION a_fefifo_7cf (aclr, clock, rreq, sclr, wreq) +RETURNS ( empty, full, usedw_out[5..0]); +FUNCTION dpram_nl21 (data[7..0], inclock, outclock, outclocken, rdaddress[5..0], wraddress[5..0], wren) +RETURNS ( q[7..0]); +FUNCTION cntr_1ob (aclr, clock, cnt_en, sclr) +RETURNS ( q[5..0]); + +--synthesis_resources = lut 18 M9K 1 reg 20 +SUBDESIGN a_dpfifo_q131 +( + aclr : input; + clock : input; + data[7..0] : input; + empty : output; + full : output; + q[7..0] : output; + rreq : input; + sclr : input; + usedw[5..0] : output; + wreq : input; +) +VARIABLE + fifo_state : a_fefifo_7cf; + FIFOram : dpram_nl21; + rd_ptr_count : cntr_1ob; + wr_ptr : cntr_1ob; + rd_ptr[5..0] : WIRE; + valid_rreq : WIRE; + valid_wreq : WIRE; + +BEGIN + fifo_state.aclr = aclr; + fifo_state.clock = clock; + fifo_state.rreq = rreq; + fifo_state.sclr = sclr; + fifo_state.wreq = wreq; + FIFOram.data[] = data[]; + FIFOram.inclock = clock; + FIFOram.outclock = clock; + FIFOram.outclocken = (valid_rreq # sclr); + FIFOram.rdaddress[] = ((! sclr) & rd_ptr[]); + FIFOram.wraddress[] = wr_ptr.q[]; + FIFOram.wren = valid_wreq; + rd_ptr_count.aclr = aclr; + rd_ptr_count.clock = clock; + rd_ptr_count.cnt_en = valid_rreq; + rd_ptr_count.sclr = sclr; + wr_ptr.aclr = aclr; + wr_ptr.clock = clock; + wr_ptr.cnt_en = valid_wreq; + wr_ptr.sclr = sclr; + empty = fifo_state.empty; + full = fifo_state.full; + q[] = FIFOram.q[]; + rd_ptr[] = rd_ptr_count.q[]; + usedw[] = fifo_state.usedw_out[]; + valid_rreq = rreq; + valid_wreq = wreq; +END; +--VALID FILE diff --git a/MCTEST/DE0-nano-HD/db/a_dpfifo_tq31.tdf b/MCTEST/DE0-nano-HD/db/a_dpfifo_tq31.tdf new file mode 100644 index 00000000..1724dee4 --- /dev/null +++ b/MCTEST/DE0-nano-HD/db/a_dpfifo_tq31.tdf @@ -0,0 +1,142 @@ +--a_dpfifo ADD_RAM_OUTPUT_REGISTER="OFF" ALLOW_RWCYCLE_WHEN_FULL="OFF" DEVICE_FAMILY="Cyclone IV E" LPM_NUMWORDS=128 LPM_SHOWAHEAD="ON" lpm_width=8 lpm_widthu=7 OVERFLOW_CHECKING="OFF" UNDERFLOW_CHECKING="OFF" clock data empty full q rreq sclr usedw wreq CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 CYCLONEII_M4K_COMPATIBILITY="ON" INTENDED_DEVICE_FAMILY="Cyclone II" LOW_POWER_MODE="AUTO" +--VERSION_BEGIN 12.1SP1 cbx_altdpram 2013:01:31:18:05:07:SJ cbx_altsyncram 2013:01:31:18:05:07:SJ cbx_cycloneii 2013:01:31:18:05:07:SJ cbx_fifo_common 2013:01:31:18:05:07:SJ cbx_lpm_add_sub 2013:01:31:18:05:07:SJ cbx_lpm_compare 2013:01:31:18:05:07:SJ cbx_lpm_counter 2013:01:31:18:05:07:SJ cbx_lpm_decode 2013:01:31:18:05:07:SJ cbx_lpm_mux 2013:01:31:18:05:07:SJ cbx_mgl 2013:01:31:18:08:27:SJ cbx_scfifo 2013:01:31:18:05:07:SJ cbx_stratix 2013:01:31:18:05:07:SJ cbx_stratixii 2013:01:31:18:05:07:SJ cbx_stratixiii 2013:01:31:18:05:07:SJ cbx_stratixv 2013:01:31:18:05:07:SJ cbx_util_mgl 2013:01:31:18:05:07:SJ VERSION_END + + +-- Copyright (C) 1991-2012 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +FUNCTION altsyncram_je81 (address_a[6..0], address_b[6..0], clock0, data_a[7..0], wren_a) +RETURNS ( q_b[7..0]); +FUNCTION cmpr_ks8 (dataa[6..0], datab[6..0]) +RETURNS ( aeb); +FUNCTION cntr_v9b (clock, cnt_en, sclr) +RETURNS ( q[5..0]); +FUNCTION cntr_ca7 (clock, cnt_en, sclr, updown) +RETURNS ( q[6..0]); +FUNCTION cntr_0ab (clock, cnt_en, sclr) +RETURNS ( q[6..0]); + +--synthesis_resources = lut 20 M9K 1 reg 35 +SUBDESIGN a_dpfifo_tq31 +( + clock : input; + data[7..0] : input; + empty : output; + full : output; + q[7..0] : output; + rreq : input; + sclr : input; + usedw[6..0] : output; + wreq : input; +) +VARIABLE + FIFOram : altsyncram_je81; + empty_dff : dffe; + full_dff : dffe; + low_addressa[6..0] : dffe; + rd_ptr_lsb : dffe; + usedw_is_0_dff : dffe; + usedw_is_1_dff : dffe; + usedw_is_2_dff : dffe; + wrreq_delaya[1..0] : dffe; + almost_full_comparer : cmpr_ks8; + three_comparison : cmpr_ks8; + rd_ptr_msb : cntr_v9b; + usedw_counter : cntr_ca7; + wr_ptr : cntr_0ab; + aclr : NODE; + asynch_read_counter_enable : WIRE; + empty_out : WIRE; + full_out : WIRE; + pulse_ram_output : WIRE; + ram_read_address[6..0] : WIRE; + rd_ptr[6..0] : WIRE; + usedw_is_0 : WIRE; + usedw_is_1 : WIRE; + usedw_is_2 : WIRE; + usedw_will_be_0 : WIRE; + usedw_will_be_1 : WIRE; + usedw_will_be_2 : WIRE; + valid_rreq : WIRE; + valid_wreq : WIRE; + wait_state : WIRE; + +BEGIN + FIFOram.address_a[] = wr_ptr.q[]; + FIFOram.address_b[] = ram_read_address[]; + FIFOram.clock0 = clock; + FIFOram.data_a[] = data[]; + FIFOram.wren_a = valid_wreq; + empty_dff.clk = clock; + empty_dff.clrn = (! aclr); + empty_dff.d = ((! (usedw_will_be_0 # wait_state)) & (! sclr)); + full_dff.clk = clock; + full_dff.clrn = (! aclr); + full_dff.d = ((! sclr) & (((valid_wreq & (! valid_rreq)) & almost_full_comparer.aeb) # (full_dff.q & (! (valid_wreq $ valid_rreq))))); + low_addressa[].clk = clock; + low_addressa[].clrn = (! aclr); + low_addressa[].d = ((! sclr) & ((asynch_read_counter_enable & rd_ptr[]) # ((! asynch_read_counter_enable) & low_addressa[].q))); + rd_ptr_lsb.clk = clock; + rd_ptr_lsb.clrn = (! aclr); + rd_ptr_lsb.d = ((! rd_ptr_lsb.q) & (! sclr)); + rd_ptr_lsb.ena = (asynch_read_counter_enable # sclr); + usedw_is_0_dff.clk = clock; + usedw_is_0_dff.clrn = (! aclr); + usedw_is_0_dff.d = (! usedw_will_be_0); + usedw_is_1_dff.clk = clock; + usedw_is_1_dff.clrn = (! aclr); + usedw_is_1_dff.d = usedw_will_be_1; + usedw_is_2_dff.clk = clock; + usedw_is_2_dff.clrn = (! aclr); + usedw_is_2_dff.d = usedw_will_be_2; + wrreq_delaya[].clk = clock; + wrreq_delaya[].clrn = (! aclr); + wrreq_delaya[].d = ( ((! sclr) & valid_wreq), ((! sclr) & wrreq_delaya[1].q)); + almost_full_comparer.dataa[] = B"1111111"; + almost_full_comparer.datab[] = usedw_counter.q[]; + three_comparison.dataa[] = usedw_counter.q[]; + three_comparison.datab[] = B"0000011"; + rd_ptr_msb.clock = clock; + rd_ptr_msb.cnt_en = (asynch_read_counter_enable & (! rd_ptr_lsb.q)); + rd_ptr_msb.sclr = sclr; + usedw_counter.clock = clock; + usedw_counter.cnt_en = (valid_wreq $ valid_rreq); + usedw_counter.sclr = sclr; + usedw_counter.updown = valid_wreq; + wr_ptr.clock = clock; + wr_ptr.cnt_en = valid_wreq; + wr_ptr.sclr = sclr; + aclr = GND; + asynch_read_counter_enable = pulse_ram_output; + empty = empty_out; + empty_out = (! empty_dff.q); + full = full_out; + full_out = full_dff.q; + pulse_ram_output = valid_rreq; + q[] = FIFOram.q_b[]; + ram_read_address[] = (((! asynch_read_counter_enable) & low_addressa[].q) # (asynch_read_counter_enable & rd_ptr[])); + rd_ptr[] = ( rd_ptr_msb.q[], (! rd_ptr_lsb.q)); + usedw[] = usedw_counter.q[]; + usedw_is_0 = (! usedw_is_0_dff.q); + usedw_is_1 = usedw_is_1_dff.q; + usedw_is_2 = usedw_is_2_dff.q; + usedw_will_be_0 = (! ((! sclr) & (! (((usedw_is_1 & valid_rreq) & (! valid_wreq)) # (usedw_is_0 & (! (valid_wreq $ valid_rreq))))))); + usedw_will_be_1 = ((! sclr) & (((usedw_is_1 & (! (valid_wreq $ valid_rreq))) # ((usedw_is_0 & valid_wreq) & (! valid_rreq))) # ((usedw_is_2 & valid_rreq) & (! valid_wreq)))); + usedw_will_be_2 = ((! sclr) & (((usedw_is_2_dff.q & (! (valid_wreq $ valid_rreq))) # ((usedw_is_1 & valid_wreq) & (! valid_rreq))) # ((three_comparison.aeb & valid_rreq) & (! valid_wreq)))); + valid_rreq = rreq; + valid_wreq = wreq; + wait_state = (usedw_will_be_1 & valid_wreq); +END; +--VALID FILE diff --git a/MCTEST/DE0-nano-HD/db/a_fefifo_7cf.tdf b/MCTEST/DE0-nano-HD/db/a_fefifo_7cf.tdf new file mode 100644 index 00000000..243eb219 --- /dev/null +++ b/MCTEST/DE0-nano-HD/db/a_fefifo_7cf.tdf @@ -0,0 +1,90 @@ +--a_fefifo ALLOW_RWCYCLE_WHEN_FULL="OFF" LPM_NUMWORDS=64 lpm_widthad=6 OVERFLOW_CHECKING="OFF" UNDERFLOW_CHECKING="OFF" aclr clock empty full rreq sclr usedw_out wreq +--VERSION_BEGIN 12.1SP1 cbx_cycloneii 2013:01:31:18:05:07:SJ cbx_fifo_common 2013:01:31:18:05:07:SJ cbx_lpm_add_sub 2013:01:31:18:05:07:SJ cbx_lpm_compare 2013:01:31:18:05:07:SJ cbx_lpm_counter 2013:01:31:18:05:07:SJ cbx_lpm_decode 2013:01:31:18:05:07:SJ cbx_mgl 2013:01:31:18:08:27:SJ cbx_stratix 2013:01:31:18:05:07:SJ cbx_stratixii 2013:01:31:18:05:07:SJ VERSION_END + + +-- Copyright (C) 1991-2012 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +FUNCTION cntr_do7 (aclr, clock, cnt_en, sclr, updown) +RETURNS ( q[5..0]); + +--synthesis_resources = lut 6 reg 8 +SUBDESIGN a_fefifo_7cf +( + aclr : input; + clock : input; + empty : output; + full : output; + rreq : input; + sclr : input; + usedw_out[5..0] : output; + wreq : input; +) +VARIABLE + b_full : dffe; + b_non_empty : dffe; + count_usedw : cntr_do7; + equal_af1w[5..0] : WIRE; + equal_one[5..0] : WIRE; + is_almost_empty0 : WIRE; + is_almost_empty1 : WIRE; + is_almost_empty2 : WIRE; + is_almost_empty3 : WIRE; + is_almost_empty4 : WIRE; + is_almost_empty5 : WIRE; + is_almost_full0 : WIRE; + is_almost_full1 : WIRE; + is_almost_full2 : WIRE; + is_almost_full3 : WIRE; + is_almost_full4 : WIRE; + is_almost_full5 : WIRE; + usedw[5..0] : WIRE; + valid_rreq : WIRE; + valid_wreq : WIRE; + +BEGIN + b_full.clk = clock; + b_full.clrn = (! aclr); + b_full.d = ((b_full.q & (b_full.q $ (sclr # rreq))) # (((! b_full.q) & b_non_empty.q) & ((! sclr) & ((is_almost_full5 & wreq) & (! rreq))))); + b_non_empty.clk = clock; + b_non_empty.clrn = (! aclr); + b_non_empty.d = (((b_full.q & (b_full.q $ sclr)) # (((! b_non_empty.q) & wreq) & (! sclr))) # (((! b_full.q) & b_non_empty.q) & (((! b_full.q) & b_non_empty.q) $ (sclr # ((is_almost_empty5 & rreq) & (! wreq)))))); + count_usedw.aclr = aclr; + count_usedw.clock = clock; + count_usedw.cnt_en = (valid_wreq $ valid_rreq); + count_usedw.sclr = sclr; + count_usedw.updown = valid_wreq; + empty = (! b_non_empty.q); + equal_af1w[] = ( B"0", B"0", B"0", B"0", B"0", B"0"); + equal_one[] = ( B"1", B"1", B"1", B"1", B"1", B"0"); + full = b_full.q; + is_almost_empty0 = (usedw[0..0] $ equal_one[0..0]); + is_almost_empty1 = ((usedw[1..1] $ equal_one[1..1]) & is_almost_empty0); + is_almost_empty2 = ((usedw[2..2] $ equal_one[2..2]) & is_almost_empty1); + is_almost_empty3 = ((usedw[3..3] $ equal_one[3..3]) & is_almost_empty2); + is_almost_empty4 = ((usedw[4..4] $ equal_one[4..4]) & is_almost_empty3); + is_almost_empty5 = ((usedw[5..5] $ equal_one[5..5]) & is_almost_empty4); + is_almost_full0 = (usedw[0..0] $ equal_af1w[0..0]); + is_almost_full1 = ((usedw[1..1] $ equal_af1w[1..1]) & is_almost_full0); + is_almost_full2 = ((usedw[2..2] $ equal_af1w[2..2]) & is_almost_full1); + is_almost_full3 = ((usedw[3..3] $ equal_af1w[3..3]) & is_almost_full2); + is_almost_full4 = ((usedw[4..4] $ equal_af1w[4..4]) & is_almost_full3); + is_almost_full5 = ((usedw[5..5] $ equal_af1w[5..5]) & is_almost_full4); + usedw[] = count_usedw.q[]; + usedw_out[] = usedw[]; + valid_rreq = rreq; + valid_wreq = wreq; +END; +--VALID FILE diff --git a/MCTEST/DE0-nano-HD/db/add_sub_qvi.tdf b/MCTEST/DE0-nano-HD/db/add_sub_qvi.tdf new file mode 100644 index 00000000..7b8bad7b --- /dev/null +++ b/MCTEST/DE0-nano-HD/db/add_sub_qvi.tdf @@ -0,0 +1,35 @@ +--lpm_add_sub CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="Cyclone IV E" LPM_DIRECTION="DEFAULT" LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=33 ONE_INPUT_IS_CONSTANT="NO" add_sub dataa datab result +--VERSION_BEGIN 12.1SP1 cbx_cycloneii 2013:01:31:18:05:07:SJ cbx_lpm_add_sub 2013:01:31:18:05:07:SJ cbx_mgl 2013:01:31:18:08:27:SJ cbx_stratix 2013:01:31:18:05:07:SJ cbx_stratixii 2013:01:31:18:05:07:SJ VERSION_END + + +-- Copyright (C) 1991-2012 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + + +--synthesis_resources = lut 66 +SUBDESIGN add_sub_qvi +( + add_sub : input; + dataa[32..0] : input; + datab[32..0] : input; + result[32..0] : output; +) +VARIABLE + result_int[33..0] : WIRE; +BEGIN + result_int[] = (dataa[], !add_sub) + (!add_sub $ datab[], !add_sub); + result[] = result_int[33..1]; +END; +--VALID FILE diff --git a/MCTEST/DE0-nano-HD/db/altsyncram_0a02.tdf b/MCTEST/DE0-nano-HD/db/altsyncram_0a02.tdf new file mode 100644 index 00000000..612cb27c --- /dev/null +++ b/MCTEST/DE0-nano-HD/db/altsyncram_0a02.tdf @@ -0,0 +1,1358 @@ +--altsyncram ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK1" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" INDATA_ACLR_A="NONE" INDATA_ACLR_B="NONE" LOW_POWER_MODE="AUTO" NUMWORDS_A=128 NUMWORDS_B=128 OPERATION_MODE="BIDIR_DUAL_PORT" OUTDATA_ACLR_A="NONE" OUTDATA_ACLR_B="NONE" OUTDATA_REG_A="UNREGISTERED" OUTDATA_REG_B="UNREGISTERED" RAM_BLOCK_TYPE="AUTO" READ_DURING_WRITE_MODE_MIXED_PORTS="OLD_DATA" WIDTH_A=36 WIDTH_B=36 WIDTHAD_A=7 WIDTHAD_B=7 WRCONTROL_ACLR_A="NONE" WRCONTROL_ACLR_B="NONE" address_a address_b clock0 clock1 clocken0 clocken1 data_a data_b q_a q_b wren_a wren_b CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 +--VERSION_BEGIN 12.1SP1 cbx_altsyncram 2013:01:31:18:05:07:SJ cbx_cycloneii 2013:01:31:18:05:07:SJ cbx_lpm_add_sub 2013:01:31:18:05:07:SJ cbx_lpm_compare 2013:01:31:18:05:07:SJ cbx_lpm_decode 2013:01:31:18:05:07:SJ cbx_lpm_mux 2013:01:31:18:05:07:SJ cbx_mgl 2013:01:31:18:08:27:SJ cbx_stratix 2013:01:31:18:05:07:SJ cbx_stratixii 2013:01:31:18:05:07:SJ cbx_stratixiii 2013:01:31:18:05:07:SJ cbx_stratixv 2013:01:31:18:05:07:SJ cbx_util_mgl 2013:01:31:18:05:07:SJ VERSION_END + + +-- Copyright (C) 1991-2012 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) +WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS) +RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); + +--synthesis_resources = M9K 2 +OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; + +SUBDESIGN altsyncram_0a02 +( + address_a[6..0] : input; + address_b[6..0] : input; + clock0 : input; + clock1 : input; + clocken0 : input; + clocken1 : input; + data_a[35..0] : input; + data_b[35..0] : input; + q_a[35..0] : output; + q_b[35..0] : output; + wren_a : input; + wren_b : input; +) +VARIABLE + ram_block1a0 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 7, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 127, + PORT_A_LOGICAL_RAM_DEPTH = 128, + PORT_A_LOGICAL_RAM_WIDTH = 36, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 7, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 127, + PORT_B_LOGICAL_RAM_DEPTH = 128, + PORT_B_LOGICAL_RAM_WIDTH = 36, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 7, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 127, + PORT_A_LOGICAL_RAM_DEPTH = 128, + PORT_A_LOGICAL_RAM_WIDTH = 36, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 7, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 127, + PORT_B_LOGICAL_RAM_DEPTH = 128, + PORT_B_LOGICAL_RAM_WIDTH = 36, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 7, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 127, + PORT_A_LOGICAL_RAM_DEPTH = 128, + PORT_A_LOGICAL_RAM_WIDTH = 36, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 7, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 127, + PORT_B_LOGICAL_RAM_DEPTH = 128, + PORT_B_LOGICAL_RAM_WIDTH = 36, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a3 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 7, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 127, + PORT_A_LOGICAL_RAM_DEPTH = 128, + PORT_A_LOGICAL_RAM_WIDTH = 36, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 7, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 127, + PORT_B_LOGICAL_RAM_DEPTH = 128, + PORT_B_LOGICAL_RAM_WIDTH = 36, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a4 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 7, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 127, + PORT_A_LOGICAL_RAM_DEPTH = 128, + PORT_A_LOGICAL_RAM_WIDTH = 36, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 7, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 127, + PORT_B_LOGICAL_RAM_DEPTH = 128, + PORT_B_LOGICAL_RAM_WIDTH = 36, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a5 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 7, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 127, + PORT_A_LOGICAL_RAM_DEPTH = 128, + PORT_A_LOGICAL_RAM_WIDTH = 36, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 7, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 127, + PORT_B_LOGICAL_RAM_DEPTH = 128, + PORT_B_LOGICAL_RAM_WIDTH = 36, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a6 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 7, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 127, + PORT_A_LOGICAL_RAM_DEPTH = 128, + PORT_A_LOGICAL_RAM_WIDTH = 36, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 7, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 127, + PORT_B_LOGICAL_RAM_DEPTH = 128, + PORT_B_LOGICAL_RAM_WIDTH = 36, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a7 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 7, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 127, + PORT_A_LOGICAL_RAM_DEPTH = 128, + PORT_A_LOGICAL_RAM_WIDTH = 36, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 7, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 127, + PORT_B_LOGICAL_RAM_DEPTH = 128, + PORT_B_LOGICAL_RAM_WIDTH = 36, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a8 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 7, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 8, + PORT_A_LAST_ADDRESS = 127, + PORT_A_LOGICAL_RAM_DEPTH = 128, + PORT_A_LOGICAL_RAM_WIDTH = 36, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 7, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 8, + PORT_B_LAST_ADDRESS = 127, + PORT_B_LOGICAL_RAM_DEPTH = 128, + PORT_B_LOGICAL_RAM_WIDTH = 36, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a9 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 7, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 9, + PORT_A_LAST_ADDRESS = 127, + PORT_A_LOGICAL_RAM_DEPTH = 128, + PORT_A_LOGICAL_RAM_WIDTH = 36, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 7, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 9, + PORT_B_LAST_ADDRESS = 127, + PORT_B_LOGICAL_RAM_DEPTH = 128, + PORT_B_LOGICAL_RAM_WIDTH = 36, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a10 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 7, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 10, + PORT_A_LAST_ADDRESS = 127, + PORT_A_LOGICAL_RAM_DEPTH = 128, + PORT_A_LOGICAL_RAM_WIDTH = 36, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 7, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 10, + PORT_B_LAST_ADDRESS = 127, + PORT_B_LOGICAL_RAM_DEPTH = 128, + PORT_B_LOGICAL_RAM_WIDTH = 36, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a11 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 7, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 11, + PORT_A_LAST_ADDRESS = 127, + PORT_A_LOGICAL_RAM_DEPTH = 128, + PORT_A_LOGICAL_RAM_WIDTH = 36, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 7, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 11, + PORT_B_LAST_ADDRESS = 127, + PORT_B_LOGICAL_RAM_DEPTH = 128, + PORT_B_LOGICAL_RAM_WIDTH = 36, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a12 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 7, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 12, + PORT_A_LAST_ADDRESS = 127, + PORT_A_LOGICAL_RAM_DEPTH = 128, + PORT_A_LOGICAL_RAM_WIDTH = 36, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 7, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 12, + PORT_B_LAST_ADDRESS = 127, + PORT_B_LOGICAL_RAM_DEPTH = 128, + PORT_B_LOGICAL_RAM_WIDTH = 36, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a13 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 7, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 13, + PORT_A_LAST_ADDRESS = 127, + PORT_A_LOGICAL_RAM_DEPTH = 128, + PORT_A_LOGICAL_RAM_WIDTH = 36, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 7, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 13, + PORT_B_LAST_ADDRESS = 127, + PORT_B_LOGICAL_RAM_DEPTH = 128, + PORT_B_LOGICAL_RAM_WIDTH = 36, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a14 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 7, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 14, + PORT_A_LAST_ADDRESS = 127, + PORT_A_LOGICAL_RAM_DEPTH = 128, + PORT_A_LOGICAL_RAM_WIDTH = 36, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 7, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 14, + PORT_B_LAST_ADDRESS = 127, + PORT_B_LOGICAL_RAM_DEPTH = 128, + PORT_B_LOGICAL_RAM_WIDTH = 36, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a15 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 7, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 15, + PORT_A_LAST_ADDRESS = 127, + PORT_A_LOGICAL_RAM_DEPTH = 128, + PORT_A_LOGICAL_RAM_WIDTH = 36, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 7, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 15, + PORT_B_LAST_ADDRESS = 127, + PORT_B_LOGICAL_RAM_DEPTH = 128, + PORT_B_LOGICAL_RAM_WIDTH = 36, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a16 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 7, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 16, + PORT_A_LAST_ADDRESS = 127, + PORT_A_LOGICAL_RAM_DEPTH = 128, + PORT_A_LOGICAL_RAM_WIDTH = 36, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 7, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 16, + PORT_B_LAST_ADDRESS = 127, + PORT_B_LOGICAL_RAM_DEPTH = 128, + PORT_B_LOGICAL_RAM_WIDTH = 36, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a17 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 7, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 17, + PORT_A_LAST_ADDRESS = 127, + PORT_A_LOGICAL_RAM_DEPTH = 128, + PORT_A_LOGICAL_RAM_WIDTH = 36, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 7, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 17, + PORT_B_LAST_ADDRESS = 127, + PORT_B_LOGICAL_RAM_DEPTH = 128, + PORT_B_LOGICAL_RAM_WIDTH = 36, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a18 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 7, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 18, + PORT_A_LAST_ADDRESS = 127, + PORT_A_LOGICAL_RAM_DEPTH = 128, + PORT_A_LOGICAL_RAM_WIDTH = 36, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 7, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 18, + PORT_B_LAST_ADDRESS = 127, + PORT_B_LOGICAL_RAM_DEPTH = 128, + PORT_B_LOGICAL_RAM_WIDTH = 36, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a19 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 7, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 19, + PORT_A_LAST_ADDRESS = 127, + PORT_A_LOGICAL_RAM_DEPTH = 128, + PORT_A_LOGICAL_RAM_WIDTH = 36, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 7, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 19, + PORT_B_LAST_ADDRESS = 127, + PORT_B_LOGICAL_RAM_DEPTH = 128, + PORT_B_LOGICAL_RAM_WIDTH = 36, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a20 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 7, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 20, + PORT_A_LAST_ADDRESS = 127, + PORT_A_LOGICAL_RAM_DEPTH = 128, + PORT_A_LOGICAL_RAM_WIDTH = 36, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 7, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 20, + PORT_B_LAST_ADDRESS = 127, + PORT_B_LOGICAL_RAM_DEPTH = 128, + PORT_B_LOGICAL_RAM_WIDTH = 36, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a21 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 7, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 21, + PORT_A_LAST_ADDRESS = 127, + PORT_A_LOGICAL_RAM_DEPTH = 128, + PORT_A_LOGICAL_RAM_WIDTH = 36, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 7, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 21, + PORT_B_LAST_ADDRESS = 127, + PORT_B_LOGICAL_RAM_DEPTH = 128, + PORT_B_LOGICAL_RAM_WIDTH = 36, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a22 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 7, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 22, + PORT_A_LAST_ADDRESS = 127, + PORT_A_LOGICAL_RAM_DEPTH = 128, + PORT_A_LOGICAL_RAM_WIDTH = 36, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 7, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 22, + PORT_B_LAST_ADDRESS = 127, + PORT_B_LOGICAL_RAM_DEPTH = 128, + PORT_B_LOGICAL_RAM_WIDTH = 36, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a23 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 7, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 23, + PORT_A_LAST_ADDRESS = 127, + PORT_A_LOGICAL_RAM_DEPTH = 128, + PORT_A_LOGICAL_RAM_WIDTH = 36, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 7, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 23, + PORT_B_LAST_ADDRESS = 127, + PORT_B_LOGICAL_RAM_DEPTH = 128, + PORT_B_LOGICAL_RAM_WIDTH = 36, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a24 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 7, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 24, + PORT_A_LAST_ADDRESS = 127, + PORT_A_LOGICAL_RAM_DEPTH = 128, + PORT_A_LOGICAL_RAM_WIDTH = 36, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 7, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 24, + PORT_B_LAST_ADDRESS = 127, + PORT_B_LOGICAL_RAM_DEPTH = 128, + PORT_B_LOGICAL_RAM_WIDTH = 36, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a25 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 7, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 25, + PORT_A_LAST_ADDRESS = 127, + PORT_A_LOGICAL_RAM_DEPTH = 128, + PORT_A_LOGICAL_RAM_WIDTH = 36, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 7, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 25, + PORT_B_LAST_ADDRESS = 127, + PORT_B_LOGICAL_RAM_DEPTH = 128, + PORT_B_LOGICAL_RAM_WIDTH = 36, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a26 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 7, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 26, + PORT_A_LAST_ADDRESS = 127, + PORT_A_LOGICAL_RAM_DEPTH = 128, + PORT_A_LOGICAL_RAM_WIDTH = 36, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 7, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 26, + PORT_B_LAST_ADDRESS = 127, + PORT_B_LOGICAL_RAM_DEPTH = 128, + PORT_B_LOGICAL_RAM_WIDTH = 36, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a27 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 7, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 27, + PORT_A_LAST_ADDRESS = 127, + PORT_A_LOGICAL_RAM_DEPTH = 128, + PORT_A_LOGICAL_RAM_WIDTH = 36, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 7, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 27, + PORT_B_LAST_ADDRESS = 127, + PORT_B_LOGICAL_RAM_DEPTH = 128, + PORT_B_LOGICAL_RAM_WIDTH = 36, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a28 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 7, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 28, + PORT_A_LAST_ADDRESS = 127, + PORT_A_LOGICAL_RAM_DEPTH = 128, + PORT_A_LOGICAL_RAM_WIDTH = 36, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 7, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 28, + PORT_B_LAST_ADDRESS = 127, + PORT_B_LOGICAL_RAM_DEPTH = 128, + PORT_B_LOGICAL_RAM_WIDTH = 36, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a29 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 7, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 29, + PORT_A_LAST_ADDRESS = 127, + PORT_A_LOGICAL_RAM_DEPTH = 128, + PORT_A_LOGICAL_RAM_WIDTH = 36, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 7, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 29, + PORT_B_LAST_ADDRESS = 127, + PORT_B_LOGICAL_RAM_DEPTH = 128, + PORT_B_LOGICAL_RAM_WIDTH = 36, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a30 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 7, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 30, + PORT_A_LAST_ADDRESS = 127, + PORT_A_LOGICAL_RAM_DEPTH = 128, + PORT_A_LOGICAL_RAM_WIDTH = 36, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 7, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 30, + PORT_B_LAST_ADDRESS = 127, + PORT_B_LOGICAL_RAM_DEPTH = 128, + PORT_B_LOGICAL_RAM_WIDTH = 36, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a31 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 7, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 31, + PORT_A_LAST_ADDRESS = 127, + PORT_A_LOGICAL_RAM_DEPTH = 128, + PORT_A_LOGICAL_RAM_WIDTH = 36, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 7, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 31, + PORT_B_LAST_ADDRESS = 127, + PORT_B_LOGICAL_RAM_DEPTH = 128, + PORT_B_LOGICAL_RAM_WIDTH = 36, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a32 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 7, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 32, + PORT_A_LAST_ADDRESS = 127, + PORT_A_LOGICAL_RAM_DEPTH = 128, + PORT_A_LOGICAL_RAM_WIDTH = 36, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 7, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 32, + PORT_B_LAST_ADDRESS = 127, + PORT_B_LOGICAL_RAM_DEPTH = 128, + PORT_B_LOGICAL_RAM_WIDTH = 36, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a33 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 7, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 33, + PORT_A_LAST_ADDRESS = 127, + PORT_A_LOGICAL_RAM_DEPTH = 128, + PORT_A_LOGICAL_RAM_WIDTH = 36, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 7, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 33, + PORT_B_LAST_ADDRESS = 127, + PORT_B_LOGICAL_RAM_DEPTH = 128, + PORT_B_LOGICAL_RAM_WIDTH = 36, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a34 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 7, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 34, + PORT_A_LAST_ADDRESS = 127, + PORT_A_LOGICAL_RAM_DEPTH = 128, + PORT_A_LOGICAL_RAM_WIDTH = 36, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 7, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 34, + PORT_B_LAST_ADDRESS = 127, + PORT_B_LOGICAL_RAM_DEPTH = 128, + PORT_B_LOGICAL_RAM_WIDTH = 36, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a35 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 7, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 35, + PORT_A_LAST_ADDRESS = 127, + PORT_A_LOGICAL_RAM_DEPTH = 128, + PORT_A_LOGICAL_RAM_WIDTH = 36, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 7, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 35, + PORT_B_LAST_ADDRESS = 127, + PORT_B_LOGICAL_RAM_DEPTH = 128, + PORT_B_LOGICAL_RAM_WIDTH = 36, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + address_a_wire[6..0] : WIRE; + address_b_wire[6..0] : WIRE; + +BEGIN + ram_block1a[35..0].clk0 = clock0; + ram_block1a[35..0].clk1 = clock1; + ram_block1a[35..0].ena0 = clocken0; + ram_block1a[35..0].ena1 = clocken1; + ram_block1a[35..0].portaaddr[] = ( address_a_wire[6..0]); + ram_block1a[0].portadatain[] = ( data_a[0..0]); + ram_block1a[1].portadatain[] = ( data_a[1..1]); + ram_block1a[2].portadatain[] = ( data_a[2..2]); + ram_block1a[3].portadatain[] = ( data_a[3..3]); + ram_block1a[4].portadatain[] = ( data_a[4..4]); + ram_block1a[5].portadatain[] = ( data_a[5..5]); + ram_block1a[6].portadatain[] = ( data_a[6..6]); + ram_block1a[7].portadatain[] = ( data_a[7..7]); + ram_block1a[8].portadatain[] = ( data_a[8..8]); + ram_block1a[9].portadatain[] = ( data_a[9..9]); + ram_block1a[10].portadatain[] = ( data_a[10..10]); + ram_block1a[11].portadatain[] = ( data_a[11..11]); + ram_block1a[12].portadatain[] = ( data_a[12..12]); + ram_block1a[13].portadatain[] = ( data_a[13..13]); + ram_block1a[14].portadatain[] = ( data_a[14..14]); + ram_block1a[15].portadatain[] = ( data_a[15..15]); + ram_block1a[16].portadatain[] = ( data_a[16..16]); + ram_block1a[17].portadatain[] = ( data_a[17..17]); + ram_block1a[18].portadatain[] = ( data_a[18..18]); + ram_block1a[19].portadatain[] = ( data_a[19..19]); + ram_block1a[20].portadatain[] = ( data_a[20..20]); + ram_block1a[21].portadatain[] = ( data_a[21..21]); + ram_block1a[22].portadatain[] = ( data_a[22..22]); + ram_block1a[23].portadatain[] = ( data_a[23..23]); + ram_block1a[24].portadatain[] = ( data_a[24..24]); + ram_block1a[25].portadatain[] = ( data_a[25..25]); + ram_block1a[26].portadatain[] = ( data_a[26..26]); + ram_block1a[27].portadatain[] = ( data_a[27..27]); + ram_block1a[28].portadatain[] = ( data_a[28..28]); + ram_block1a[29].portadatain[] = ( data_a[29..29]); + ram_block1a[30].portadatain[] = ( data_a[30..30]); + ram_block1a[31].portadatain[] = ( data_a[31..31]); + ram_block1a[32].portadatain[] = ( data_a[32..32]); + ram_block1a[33].portadatain[] = ( data_a[33..33]); + ram_block1a[34].portadatain[] = ( data_a[34..34]); + ram_block1a[35].portadatain[] = ( data_a[35..35]); + ram_block1a[35..0].portare = B"111111111111111111111111111111111111"; + ram_block1a[35..0].portawe = wren_a; + ram_block1a[35..0].portbaddr[] = ( address_b_wire[6..0]); + ram_block1a[0].portbdatain[] = ( data_b[0..0]); + ram_block1a[1].portbdatain[] = ( data_b[1..1]); + ram_block1a[2].portbdatain[] = ( data_b[2..2]); + ram_block1a[3].portbdatain[] = ( data_b[3..3]); + ram_block1a[4].portbdatain[] = ( data_b[4..4]); + ram_block1a[5].portbdatain[] = ( data_b[5..5]); + ram_block1a[6].portbdatain[] = ( data_b[6..6]); + ram_block1a[7].portbdatain[] = ( data_b[7..7]); + ram_block1a[8].portbdatain[] = ( data_b[8..8]); + ram_block1a[9].portbdatain[] = ( data_b[9..9]); + ram_block1a[10].portbdatain[] = ( data_b[10..10]); + ram_block1a[11].portbdatain[] = ( data_b[11..11]); + ram_block1a[12].portbdatain[] = ( data_b[12..12]); + ram_block1a[13].portbdatain[] = ( data_b[13..13]); + ram_block1a[14].portbdatain[] = ( data_b[14..14]); + ram_block1a[15].portbdatain[] = ( data_b[15..15]); + ram_block1a[16].portbdatain[] = ( data_b[16..16]); + ram_block1a[17].portbdatain[] = ( data_b[17..17]); + ram_block1a[18].portbdatain[] = ( data_b[18..18]); + ram_block1a[19].portbdatain[] = ( data_b[19..19]); + ram_block1a[20].portbdatain[] = ( data_b[20..20]); + ram_block1a[21].portbdatain[] = ( data_b[21..21]); + ram_block1a[22].portbdatain[] = ( data_b[22..22]); + ram_block1a[23].portbdatain[] = ( data_b[23..23]); + ram_block1a[24].portbdatain[] = ( data_b[24..24]); + ram_block1a[25].portbdatain[] = ( data_b[25..25]); + ram_block1a[26].portbdatain[] = ( data_b[26..26]); + ram_block1a[27].portbdatain[] = ( data_b[27..27]); + ram_block1a[28].portbdatain[] = ( data_b[28..28]); + ram_block1a[29].portbdatain[] = ( data_b[29..29]); + ram_block1a[30].portbdatain[] = ( data_b[30..30]); + ram_block1a[31].portbdatain[] = ( data_b[31..31]); + ram_block1a[32].portbdatain[] = ( data_b[32..32]); + ram_block1a[33].portbdatain[] = ( data_b[33..33]); + ram_block1a[34].portbdatain[] = ( data_b[34..34]); + ram_block1a[35].portbdatain[] = ( data_b[35..35]); + ram_block1a[35..0].portbre = B"111111111111111111111111111111111111"; + ram_block1a[35..0].portbwe = wren_b; + address_a_wire[] = address_a[]; + address_b_wire[] = address_b[]; + q_a[] = ( ram_block1a[35..0].portadataout[0..0]); + q_b[] = ( ram_block1a[35..0].portbdataout[0..0]); +END; +--VALID FILE diff --git a/MCTEST/DE0-nano-HD/db/altsyncram_2jf1.tdf b/MCTEST/DE0-nano-HD/db/altsyncram_2jf1.tdf new file mode 100644 index 00000000..66a6df96 --- /dev/null +++ b/MCTEST/DE0-nano-HD/db/altsyncram_2jf1.tdf @@ -0,0 +1,1113 @@ +--altsyncram ADDRESS_REG_B="CLOCK0" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" LOW_POWER_MODE="AUTO" MAXIMUM_DEPTH=0 NUMWORDS_A=1024 NUMWORDS_B=1024 OPERATION_MODE="DUAL_PORT" OUTDATA_REG_B="UNREGISTERED" RAM_BLOCK_TYPE="AUTO" RDCONTROL_REG_B="CLOCK0" READ_DURING_WRITE_MODE_MIXED_PORTS="DONT_CARE" WIDTH_A=32 WIDTH_B=32 WIDTH_BYTEENA_A=4 WIDTHAD_A=10 WIDTHAD_B=10 address_a address_b byteena_a clock0 data_a q_b wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 +--VERSION_BEGIN 12.1SP1 cbx_altsyncram 2013:01:31:18:05:07:SJ cbx_cycloneii 2013:01:31:18:05:07:SJ cbx_lpm_add_sub 2013:01:31:18:05:07:SJ cbx_lpm_compare 2013:01:31:18:05:07:SJ cbx_lpm_decode 2013:01:31:18:05:07:SJ cbx_lpm_mux 2013:01:31:18:05:07:SJ cbx_mgl 2013:01:31:18:08:27:SJ cbx_stratix 2013:01:31:18:05:07:SJ cbx_stratixii 2013:01:31:18:05:07:SJ cbx_stratixiii 2013:01:31:18:05:07:SJ cbx_stratixv 2013:01:31:18:05:07:SJ cbx_util_mgl 2013:01:31:18:05:07:SJ VERSION_END + + +-- Copyright (C) 1991-2012 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) +WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS) +RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); + +--synthesis_resources = M9K 4 +OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; + +SUBDESIGN altsyncram_2jf1 +( + address_a[9..0] : input; + address_b[9..0] : input; + byteena_a[3..0] : input; + clock0 : input; + data_a[31..0] : input; + q_b[31..0] : output; + wren_a : input; +) +VARIABLE + ram_block1a0 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "none", + CLK1_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 10, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 1023, + PORT_B_LOGICAL_RAM_DEPTH = 1024, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "none", + CLK1_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 10, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 1023, + PORT_B_LOGICAL_RAM_DEPTH = 1024, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "none", + CLK1_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 10, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 1023, + PORT_B_LOGICAL_RAM_DEPTH = 1024, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a3 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "none", + CLK1_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 10, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 1023, + PORT_B_LOGICAL_RAM_DEPTH = 1024, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a4 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "none", + CLK1_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 10, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 1023, + PORT_B_LOGICAL_RAM_DEPTH = 1024, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a5 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "none", + CLK1_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 10, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 1023, + PORT_B_LOGICAL_RAM_DEPTH = 1024, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a6 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "none", + CLK1_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 10, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 1023, + PORT_B_LOGICAL_RAM_DEPTH = 1024, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a7 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "none", + CLK1_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 10, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 1023, + PORT_B_LOGICAL_RAM_DEPTH = 1024, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a8 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "none", + CLK1_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 8, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 10, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 8, + PORT_B_LAST_ADDRESS = 1023, + PORT_B_LOGICAL_RAM_DEPTH = 1024, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a9 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "none", + CLK1_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 9, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 10, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 9, + PORT_B_LAST_ADDRESS = 1023, + PORT_B_LOGICAL_RAM_DEPTH = 1024, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a10 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "none", + CLK1_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 10, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 10, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 10, + PORT_B_LAST_ADDRESS = 1023, + PORT_B_LOGICAL_RAM_DEPTH = 1024, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a11 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "none", + CLK1_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 11, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 10, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 11, + PORT_B_LAST_ADDRESS = 1023, + PORT_B_LOGICAL_RAM_DEPTH = 1024, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a12 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "none", + CLK1_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 12, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 10, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 12, + PORT_B_LAST_ADDRESS = 1023, + PORT_B_LOGICAL_RAM_DEPTH = 1024, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a13 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "none", + CLK1_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 13, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 10, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 13, + PORT_B_LAST_ADDRESS = 1023, + PORT_B_LOGICAL_RAM_DEPTH = 1024, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a14 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "none", + CLK1_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 14, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 10, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 14, + PORT_B_LAST_ADDRESS = 1023, + PORT_B_LOGICAL_RAM_DEPTH = 1024, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a15 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "none", + CLK1_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 15, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 10, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 15, + PORT_B_LAST_ADDRESS = 1023, + PORT_B_LOGICAL_RAM_DEPTH = 1024, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a16 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "none", + CLK1_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 16, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 10, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 16, + PORT_B_LAST_ADDRESS = 1023, + PORT_B_LOGICAL_RAM_DEPTH = 1024, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a17 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "none", + CLK1_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 17, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 10, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 17, + PORT_B_LAST_ADDRESS = 1023, + PORT_B_LOGICAL_RAM_DEPTH = 1024, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a18 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "none", + CLK1_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 18, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 10, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 18, + PORT_B_LAST_ADDRESS = 1023, + PORT_B_LOGICAL_RAM_DEPTH = 1024, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a19 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "none", + CLK1_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 19, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 10, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 19, + PORT_B_LAST_ADDRESS = 1023, + PORT_B_LOGICAL_RAM_DEPTH = 1024, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a20 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "none", + CLK1_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 20, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 10, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 20, + PORT_B_LAST_ADDRESS = 1023, + PORT_B_LOGICAL_RAM_DEPTH = 1024, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a21 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "none", + CLK1_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 21, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 10, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 21, + PORT_B_LAST_ADDRESS = 1023, + PORT_B_LOGICAL_RAM_DEPTH = 1024, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a22 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "none", + CLK1_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 22, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 10, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 22, + PORT_B_LAST_ADDRESS = 1023, + PORT_B_LOGICAL_RAM_DEPTH = 1024, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a23 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "none", + CLK1_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 23, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 10, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 23, + PORT_B_LAST_ADDRESS = 1023, + PORT_B_LOGICAL_RAM_DEPTH = 1024, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a24 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "none", + CLK1_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 24, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 10, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 24, + PORT_B_LAST_ADDRESS = 1023, + PORT_B_LOGICAL_RAM_DEPTH = 1024, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a25 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "none", + CLK1_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 25, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 10, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 25, + PORT_B_LAST_ADDRESS = 1023, + PORT_B_LOGICAL_RAM_DEPTH = 1024, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a26 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "none", + CLK1_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 26, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 10, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 26, + PORT_B_LAST_ADDRESS = 1023, + PORT_B_LOGICAL_RAM_DEPTH = 1024, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a27 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "none", + CLK1_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 27, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 10, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 27, + PORT_B_LAST_ADDRESS = 1023, + PORT_B_LOGICAL_RAM_DEPTH = 1024, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a28 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "none", + CLK1_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 28, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 10, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 28, + PORT_B_LAST_ADDRESS = 1023, + PORT_B_LOGICAL_RAM_DEPTH = 1024, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a29 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "none", + CLK1_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 29, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 10, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 29, + PORT_B_LAST_ADDRESS = 1023, + PORT_B_LOGICAL_RAM_DEPTH = 1024, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a30 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "none", + CLK1_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 30, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 10, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 30, + PORT_B_LAST_ADDRESS = 1023, + PORT_B_LOGICAL_RAM_DEPTH = 1024, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a31 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "none", + CLK1_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 10, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 31, + PORT_A_LAST_ADDRESS = 1023, + PORT_A_LOGICAL_RAM_DEPTH = 1024, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 10, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 31, + PORT_B_LAST_ADDRESS = 1023, + PORT_B_LOGICAL_RAM_DEPTH = 1024, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + address_a_wire[9..0] : WIRE; + address_b_wire[9..0] : WIRE; + +BEGIN + ram_block1a[31..0].clk0 = clock0; + ram_block1a[31..0].clk1 = clock0; + ram_block1a[31..0].ena0 = wren_a; + ram_block1a[31..0].portaaddr[] = ( address_a_wire[9..0]); + ram_block1a[7..0].portabyteenamasks[] = ( byteena_a[0..0]); + ram_block1a[15..8].portabyteenamasks[] = ( byteena_a[1..1]); + ram_block1a[23..16].portabyteenamasks[] = ( byteena_a[2..2]); + ram_block1a[31..24].portabyteenamasks[] = ( byteena_a[3..3]); + ram_block1a[0].portadatain[] = ( data_a[0..0]); + ram_block1a[1].portadatain[] = ( data_a[1..1]); + ram_block1a[2].portadatain[] = ( data_a[2..2]); + ram_block1a[3].portadatain[] = ( data_a[3..3]); + ram_block1a[4].portadatain[] = ( data_a[4..4]); + ram_block1a[5].portadatain[] = ( data_a[5..5]); + ram_block1a[6].portadatain[] = ( data_a[6..6]); + ram_block1a[7].portadatain[] = ( data_a[7..7]); + ram_block1a[8].portadatain[] = ( data_a[8..8]); + ram_block1a[9].portadatain[] = ( data_a[9..9]); + ram_block1a[10].portadatain[] = ( data_a[10..10]); + ram_block1a[11].portadatain[] = ( data_a[11..11]); + ram_block1a[12].portadatain[] = ( data_a[12..12]); + ram_block1a[13].portadatain[] = ( data_a[13..13]); + ram_block1a[14].portadatain[] = ( data_a[14..14]); + ram_block1a[15].portadatain[] = ( data_a[15..15]); + ram_block1a[16].portadatain[] = ( data_a[16..16]); + ram_block1a[17].portadatain[] = ( data_a[17..17]); + ram_block1a[18].portadatain[] = ( data_a[18..18]); + ram_block1a[19].portadatain[] = ( data_a[19..19]); + ram_block1a[20].portadatain[] = ( data_a[20..20]); + ram_block1a[21].portadatain[] = ( data_a[21..21]); + ram_block1a[22].portadatain[] = ( data_a[22..22]); + ram_block1a[23].portadatain[] = ( data_a[23..23]); + ram_block1a[24].portadatain[] = ( data_a[24..24]); + ram_block1a[25].portadatain[] = ( data_a[25..25]); + ram_block1a[26].portadatain[] = ( data_a[26..26]); + ram_block1a[27].portadatain[] = ( data_a[27..27]); + ram_block1a[28].portadatain[] = ( data_a[28..28]); + ram_block1a[29].portadatain[] = ( data_a[29..29]); + ram_block1a[30].portadatain[] = ( data_a[30..30]); + ram_block1a[31].portadatain[] = ( data_a[31..31]); + ram_block1a[31..0].portawe = wren_a; + ram_block1a[31..0].portbaddr[] = ( address_b_wire[9..0]); + ram_block1a[31..0].portbre = B"11111111111111111111111111111111"; + address_a_wire[] = address_a[]; + address_b_wire[] = address_b[]; + q_b[] = ( ram_block1a[31..0].portbdataout[0..0]); +END; +--VALID FILE diff --git a/MCTEST/DE0-nano-HD/db/altsyncram_d9g1.tdf b/MCTEST/DE0-nano-HD/db/altsyncram_d9g1.tdf new file mode 100644 index 00000000..6e5d1d84 --- /dev/null +++ b/MCTEST/DE0-nano-HD/db/altsyncram_d9g1.tdf @@ -0,0 +1,546 @@ +--altsyncram ADDRESS_REG_B="CLOCK0" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" INIT_FILE="system_cpu_dc_tag_ram.mif" LOW_POWER_MODE="AUTO" MAXIMUM_DEPTH=0 NUMWORDS_A=128 NUMWORDS_B=128 OPERATION_MODE="DUAL_PORT" OUTDATA_REG_B="UNREGISTERED" RAM_BLOCK_TYPE="AUTO" RDCONTROL_REG_B="CLOCK0" READ_DURING_WRITE_MODE_MIXED_PORTS="OLD_DATA" WIDTH_A=16 WIDTH_B=16 WIDTHAD_A=7 WIDTHAD_B=7 address_a address_b clock0 data_a q_b wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 +--VERSION_BEGIN 12.1SP1 cbx_altsyncram 2013:01:31:18:05:07:SJ cbx_cycloneii 2013:01:31:18:05:07:SJ cbx_lpm_add_sub 2013:01:31:18:05:07:SJ cbx_lpm_compare 2013:01:31:18:05:07:SJ cbx_lpm_decode 2013:01:31:18:05:07:SJ cbx_lpm_mux 2013:01:31:18:05:07:SJ cbx_mgl 2013:01:31:18:08:27:SJ cbx_stratix 2013:01:31:18:05:07:SJ cbx_stratixii 2013:01:31:18:05:07:SJ cbx_stratixiii 2013:01:31:18:05:07:SJ cbx_stratixv 2013:01:31:18:05:07:SJ cbx_util_mgl 2013:01:31:18:05:07:SJ VERSION_END + + +-- Copyright (C) 1991-2012 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) +WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS) +RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); + +--synthesis_resources = M9K 1 +OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; + +SUBDESIGN altsyncram_d9g1 +( + address_a[6..0] : input; + address_b[6..0] : input; + clock0 : input; + data_a[15..0] : input; + q_b[15..0] : output; + wren_a : input; +) +VARIABLE + ram_block1a0 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_dc_tag_ram.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 7, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 127, + PORT_A_LOGICAL_RAM_DEPTH = 128, + PORT_A_LOGICAL_RAM_WIDTH = 16, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 7, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 127, + PORT_B_LOGICAL_RAM_DEPTH = 128, + PORT_B_LOGICAL_RAM_WIDTH = 16, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_dc_tag_ram.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 7, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 127, + PORT_A_LOGICAL_RAM_DEPTH = 128, + PORT_A_LOGICAL_RAM_WIDTH = 16, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 7, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 127, + PORT_B_LOGICAL_RAM_DEPTH = 128, + PORT_B_LOGICAL_RAM_WIDTH = 16, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_dc_tag_ram.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 7, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 127, + PORT_A_LOGICAL_RAM_DEPTH = 128, + PORT_A_LOGICAL_RAM_WIDTH = 16, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 7, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 127, + PORT_B_LOGICAL_RAM_DEPTH = 128, + PORT_B_LOGICAL_RAM_WIDTH = 16, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a3 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_dc_tag_ram.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 7, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 127, + PORT_A_LOGICAL_RAM_DEPTH = 128, + PORT_A_LOGICAL_RAM_WIDTH = 16, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 7, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 127, + PORT_B_LOGICAL_RAM_DEPTH = 128, + PORT_B_LOGICAL_RAM_WIDTH = 16, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a4 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_dc_tag_ram.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 7, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 127, + PORT_A_LOGICAL_RAM_DEPTH = 128, + PORT_A_LOGICAL_RAM_WIDTH = 16, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 7, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 127, + PORT_B_LOGICAL_RAM_DEPTH = 128, + PORT_B_LOGICAL_RAM_WIDTH = 16, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a5 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_dc_tag_ram.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 7, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 127, + PORT_A_LOGICAL_RAM_DEPTH = 128, + PORT_A_LOGICAL_RAM_WIDTH = 16, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 7, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 127, + PORT_B_LOGICAL_RAM_DEPTH = 128, + PORT_B_LOGICAL_RAM_WIDTH = 16, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a6 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_dc_tag_ram.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 7, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 127, + PORT_A_LOGICAL_RAM_DEPTH = 128, + PORT_A_LOGICAL_RAM_WIDTH = 16, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 7, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 127, + PORT_B_LOGICAL_RAM_DEPTH = 128, + PORT_B_LOGICAL_RAM_WIDTH = 16, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a7 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_dc_tag_ram.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 7, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 127, + PORT_A_LOGICAL_RAM_DEPTH = 128, + PORT_A_LOGICAL_RAM_WIDTH = 16, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 7, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 127, + PORT_B_LOGICAL_RAM_DEPTH = 128, + PORT_B_LOGICAL_RAM_WIDTH = 16, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a8 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_dc_tag_ram.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 7, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 8, + PORT_A_LAST_ADDRESS = 127, + PORT_A_LOGICAL_RAM_DEPTH = 128, + PORT_A_LOGICAL_RAM_WIDTH = 16, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 7, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 8, + PORT_B_LAST_ADDRESS = 127, + PORT_B_LOGICAL_RAM_DEPTH = 128, + PORT_B_LOGICAL_RAM_WIDTH = 16, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a9 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_dc_tag_ram.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 7, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 9, + PORT_A_LAST_ADDRESS = 127, + PORT_A_LOGICAL_RAM_DEPTH = 128, + PORT_A_LOGICAL_RAM_WIDTH = 16, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 7, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 9, + PORT_B_LAST_ADDRESS = 127, + PORT_B_LOGICAL_RAM_DEPTH = 128, + PORT_B_LOGICAL_RAM_WIDTH = 16, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a10 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_dc_tag_ram.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 7, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 10, + PORT_A_LAST_ADDRESS = 127, + PORT_A_LOGICAL_RAM_DEPTH = 128, + PORT_A_LOGICAL_RAM_WIDTH = 16, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 7, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 10, + PORT_B_LAST_ADDRESS = 127, + PORT_B_LOGICAL_RAM_DEPTH = 128, + PORT_B_LOGICAL_RAM_WIDTH = 16, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a11 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_dc_tag_ram.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 7, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 11, + PORT_A_LAST_ADDRESS = 127, + PORT_A_LOGICAL_RAM_DEPTH = 128, + PORT_A_LOGICAL_RAM_WIDTH = 16, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 7, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 11, + PORT_B_LAST_ADDRESS = 127, + PORT_B_LOGICAL_RAM_DEPTH = 128, + PORT_B_LOGICAL_RAM_WIDTH = 16, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a12 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_dc_tag_ram.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 7, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 12, + PORT_A_LAST_ADDRESS = 127, + PORT_A_LOGICAL_RAM_DEPTH = 128, + PORT_A_LOGICAL_RAM_WIDTH = 16, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 7, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 12, + PORT_B_LAST_ADDRESS = 127, + PORT_B_LOGICAL_RAM_DEPTH = 128, + PORT_B_LOGICAL_RAM_WIDTH = 16, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a13 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_dc_tag_ram.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 7, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 13, + PORT_A_LAST_ADDRESS = 127, + PORT_A_LOGICAL_RAM_DEPTH = 128, + PORT_A_LOGICAL_RAM_WIDTH = 16, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 7, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 13, + PORT_B_LAST_ADDRESS = 127, + PORT_B_LOGICAL_RAM_DEPTH = 128, + PORT_B_LOGICAL_RAM_WIDTH = 16, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a14 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_dc_tag_ram.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 7, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 14, + PORT_A_LAST_ADDRESS = 127, + PORT_A_LOGICAL_RAM_DEPTH = 128, + PORT_A_LOGICAL_RAM_WIDTH = 16, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 7, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 14, + PORT_B_LAST_ADDRESS = 127, + PORT_B_LOGICAL_RAM_DEPTH = 128, + PORT_B_LOGICAL_RAM_WIDTH = 16, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a15 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_dc_tag_ram.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 7, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 15, + PORT_A_LAST_ADDRESS = 127, + PORT_A_LOGICAL_RAM_DEPTH = 128, + PORT_A_LOGICAL_RAM_WIDTH = 16, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 7, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 15, + PORT_B_LAST_ADDRESS = 127, + PORT_B_LOGICAL_RAM_DEPTH = 128, + PORT_B_LOGICAL_RAM_WIDTH = 16, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + address_a_wire[6..0] : WIRE; + address_b_wire[6..0] : WIRE; + +BEGIN + ram_block1a[15..0].clk0 = clock0; + ram_block1a[15..0].portaaddr[] = ( address_a_wire[6..0]); + ram_block1a[0].portadatain[] = ( data_a[0..0]); + ram_block1a[1].portadatain[] = ( data_a[1..1]); + ram_block1a[2].portadatain[] = ( data_a[2..2]); + ram_block1a[3].portadatain[] = ( data_a[3..3]); + ram_block1a[4].portadatain[] = ( data_a[4..4]); + ram_block1a[5].portadatain[] = ( data_a[5..5]); + ram_block1a[6].portadatain[] = ( data_a[6..6]); + ram_block1a[7].portadatain[] = ( data_a[7..7]); + ram_block1a[8].portadatain[] = ( data_a[8..8]); + ram_block1a[9].portadatain[] = ( data_a[9..9]); + ram_block1a[10].portadatain[] = ( data_a[10..10]); + ram_block1a[11].portadatain[] = ( data_a[11..11]); + ram_block1a[12].portadatain[] = ( data_a[12..12]); + ram_block1a[13].portadatain[] = ( data_a[13..13]); + ram_block1a[14].portadatain[] = ( data_a[14..14]); + ram_block1a[15].portadatain[] = ( data_a[15..15]); + ram_block1a[15..0].portawe = wren_a; + ram_block1a[15..0].portbaddr[] = ( address_b_wire[6..0]); + ram_block1a[15..0].portbre = B"1111111111111111"; + address_a_wire[] = address_a[]; + address_b_wire[] = address_b[]; + q_b[] = ( ram_block1a[15..0].portbdataout[0..0]); +END; +--VALID FILE diff --git a/MCTEST/DE0-nano-HD/db/altsyncram_fhg1.tdf b/MCTEST/DE0-nano-HD/db/altsyncram_fhg1.tdf new file mode 100644 index 00000000..a0c37aca --- /dev/null +++ b/MCTEST/DE0-nano-HD/db/altsyncram_fhg1.tdf @@ -0,0 +1,113 @@ +--altsyncram ADDRESS_REG_B="CLOCK0" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" INIT_FILE="system_cpu_bht_ram.mif" LOW_POWER_MODE="AUTO" MAXIMUM_DEPTH=0 NUMWORDS_A=256 NUMWORDS_B=256 OPERATION_MODE="DUAL_PORT" OUTDATA_REG_B="UNREGISTERED" RAM_BLOCK_TYPE="AUTO" RDCONTROL_REG_B="CLOCK0" READ_DURING_WRITE_MODE_MIXED_PORTS="OLD_DATA" WIDTH_A=2 WIDTH_B=2 WIDTHAD_A=8 WIDTHAD_B=8 address_a address_b clock0 data_a q_b rden_b wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 +--VERSION_BEGIN 12.1SP1 cbx_altsyncram 2013:01:31:18:05:07:SJ cbx_cycloneii 2013:01:31:18:05:07:SJ cbx_lpm_add_sub 2013:01:31:18:05:07:SJ cbx_lpm_compare 2013:01:31:18:05:07:SJ cbx_lpm_decode 2013:01:31:18:05:07:SJ cbx_lpm_mux 2013:01:31:18:05:07:SJ cbx_mgl 2013:01:31:18:08:27:SJ cbx_stratix 2013:01:31:18:05:07:SJ cbx_stratixii 2013:01:31:18:05:07:SJ cbx_stratixiii 2013:01:31:18:05:07:SJ cbx_stratixv 2013:01:31:18:05:07:SJ cbx_util_mgl 2013:01:31:18:05:07:SJ VERSION_END + + +-- Copyright (C) 1991-2012 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) +WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS) +RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); + +--synthesis_resources = M9K 1 +OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; + +SUBDESIGN altsyncram_fhg1 +( + address_a[7..0] : input; + address_b[7..0] : input; + clock0 : input; + data_a[1..0] : input; + q_b[1..0] : output; + rden_b : input; + wren_a : input; +) +VARIABLE + ram_block1a0 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_bht_ram.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 2, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 8, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 255, + PORT_B_LOGICAL_RAM_DEPTH = 256, + PORT_B_LOGICAL_RAM_WIDTH = 2, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_bht_ram.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 2, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 8, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 255, + PORT_B_LOGICAL_RAM_DEPTH = 256, + PORT_B_LOGICAL_RAM_WIDTH = 2, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + address_a_wire[7..0] : WIRE; + address_b_wire[7..0] : WIRE; + +BEGIN + ram_block1a[1..0].clk0 = clock0; + ram_block1a[1..0].portaaddr[] = ( address_a_wire[7..0]); + ram_block1a[0].portadatain[] = ( data_a[0..0]); + ram_block1a[1].portadatain[] = ( data_a[1..1]); + ram_block1a[1..0].portawe = wren_a; + ram_block1a[1..0].portbaddr[] = ( address_b_wire[7..0]); + ram_block1a[1..0].portbre = rden_b; + address_a_wire[] = address_a[]; + address_b_wire[] = address_b[]; + q_b[] = ( ram_block1a[1..0].portbdataout[0..0]); +END; +--VALID FILE diff --git a/MCTEST/DE0-nano-HD/db/altsyncram_fvf1.tdf b/MCTEST/DE0-nano-HD/db/altsyncram_fvf1.tdf new file mode 100644 index 00000000..6736a8bb --- /dev/null +++ b/MCTEST/DE0-nano-HD/db/altsyncram_fvf1.tdf @@ -0,0 +1,1042 @@ +--altsyncram ADDRESS_REG_B="CLOCK0" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" INIT_FILE="system_cpu_rf_ram_a.mif" LOW_POWER_MODE="AUTO" MAXIMUM_DEPTH=0 NUMWORDS_A=32 NUMWORDS_B=32 OPERATION_MODE="DUAL_PORT" OUTDATA_REG_B="UNREGISTERED" RAM_BLOCK_TYPE="AUTO" RDCONTROL_REG_B="CLOCK0" READ_DURING_WRITE_MODE_MIXED_PORTS="OLD_DATA" WIDTH_A=32 WIDTH_B=32 WIDTHAD_A=5 WIDTHAD_B=5 address_a address_b clock0 data_a q_b wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 +--VERSION_BEGIN 12.1SP1 cbx_altsyncram 2013:01:31:18:05:07:SJ cbx_cycloneii 2013:01:31:18:05:07:SJ cbx_lpm_add_sub 2013:01:31:18:05:07:SJ cbx_lpm_compare 2013:01:31:18:05:07:SJ cbx_lpm_decode 2013:01:31:18:05:07:SJ cbx_lpm_mux 2013:01:31:18:05:07:SJ cbx_mgl 2013:01:31:18:08:27:SJ cbx_stratix 2013:01:31:18:05:07:SJ cbx_stratixii 2013:01:31:18:05:07:SJ cbx_stratixiii 2013:01:31:18:05:07:SJ cbx_stratixv 2013:01:31:18:05:07:SJ cbx_util_mgl 2013:01:31:18:05:07:SJ VERSION_END + + +-- Copyright (C) 1991-2012 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) +WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS) +RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); + +--synthesis_resources = M9K 1 +OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; + +SUBDESIGN altsyncram_fvf1 +( + address_a[4..0] : input; + address_b[4..0] : input; + clock0 : input; + data_a[31..0] : input; + q_b[31..0] : output; + wren_a : input; +) +VARIABLE + ram_block1a0 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a3 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a4 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a5 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a6 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a7 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a8 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 8, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 8, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a9 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 9, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 9, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a10 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 10, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 10, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a11 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 11, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 11, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a12 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 12, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 12, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a13 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 13, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 13, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a14 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 14, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 14, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a15 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 15, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 15, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a16 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 16, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 16, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a17 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 17, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 17, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a18 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 18, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 18, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a19 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 19, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 19, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a20 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 20, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 20, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a21 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 21, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 21, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a22 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 22, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 22, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a23 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 23, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 23, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a24 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 24, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 24, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a25 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 25, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 25, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a26 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 26, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 26, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a27 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 27, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 27, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a28 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 28, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 28, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a29 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 29, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 29, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a30 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 30, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 30, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a31 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_rf_ram_a.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 31, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 31, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + address_a_wire[4..0] : WIRE; + address_b_wire[4..0] : WIRE; + +BEGIN + ram_block1a[31..0].clk0 = clock0; + ram_block1a[31..0].portaaddr[] = ( address_a_wire[4..0]); + ram_block1a[0].portadatain[] = ( data_a[0..0]); + ram_block1a[1].portadatain[] = ( data_a[1..1]); + ram_block1a[2].portadatain[] = ( data_a[2..2]); + ram_block1a[3].portadatain[] = ( data_a[3..3]); + ram_block1a[4].portadatain[] = ( data_a[4..4]); + ram_block1a[5].portadatain[] = ( data_a[5..5]); + ram_block1a[6].portadatain[] = ( data_a[6..6]); + ram_block1a[7].portadatain[] = ( data_a[7..7]); + ram_block1a[8].portadatain[] = ( data_a[8..8]); + ram_block1a[9].portadatain[] = ( data_a[9..9]); + ram_block1a[10].portadatain[] = ( data_a[10..10]); + ram_block1a[11].portadatain[] = ( data_a[11..11]); + ram_block1a[12].portadatain[] = ( data_a[12..12]); + ram_block1a[13].portadatain[] = ( data_a[13..13]); + ram_block1a[14].portadatain[] = ( data_a[14..14]); + ram_block1a[15].portadatain[] = ( data_a[15..15]); + ram_block1a[16].portadatain[] = ( data_a[16..16]); + ram_block1a[17].portadatain[] = ( data_a[17..17]); + ram_block1a[18].portadatain[] = ( data_a[18..18]); + ram_block1a[19].portadatain[] = ( data_a[19..19]); + ram_block1a[20].portadatain[] = ( data_a[20..20]); + ram_block1a[21].portadatain[] = ( data_a[21..21]); + ram_block1a[22].portadatain[] = ( data_a[22..22]); + ram_block1a[23].portadatain[] = ( data_a[23..23]); + ram_block1a[24].portadatain[] = ( data_a[24..24]); + ram_block1a[25].portadatain[] = ( data_a[25..25]); + ram_block1a[26].portadatain[] = ( data_a[26..26]); + ram_block1a[27].portadatain[] = ( data_a[27..27]); + ram_block1a[28].portadatain[] = ( data_a[28..28]); + ram_block1a[29].portadatain[] = ( data_a[29..29]); + ram_block1a[30].portadatain[] = ( data_a[30..30]); + ram_block1a[31].portadatain[] = ( data_a[31..31]); + ram_block1a[31..0].portawe = wren_a; + ram_block1a[31..0].portbaddr[] = ( address_b_wire[4..0]); + ram_block1a[31..0].portbre = B"11111111111111111111111111111111"; + address_a_wire[] = address_a[]; + address_b_wire[] = address_b[]; + q_b[] = ( ram_block1a[31..0].portbdataout[0..0]); +END; +--VALID FILE diff --git a/MCTEST/DE0-nano-HD/db/altsyncram_gt51.tdf b/MCTEST/DE0-nano-HD/db/altsyncram_gt51.tdf new file mode 100644 index 00000000..2e60fb1e --- /dev/null +++ b/MCTEST/DE0-nano-HD/db/altsyncram_gt51.tdf @@ -0,0 +1,683 @@ +--altsyncram BYTE_SIZE=8 CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" INIT_FILE="system_epcs_flash_controller_boot_rom_synth.hex" LOW_POWER_MODE="AUTO" NUMWORDS_A=256 OPERATION_MODE="ROM" OUTDATA_REG_A="UNREGISTERED" READ_DURING_WRITE_MODE_MIXED_PORTS="DONT_CARE" WIDTH_A=32 WIDTHAD_A=8 address_a clock0 q_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 +--VERSION_BEGIN 12.1SP1 cbx_altsyncram 2013:01:31:18:05:07:SJ cbx_cycloneii 2013:01:31:18:05:07:SJ cbx_lpm_add_sub 2013:01:31:18:05:07:SJ cbx_lpm_compare 2013:01:31:18:05:07:SJ cbx_lpm_decode 2013:01:31:18:05:07:SJ cbx_lpm_mux 2013:01:31:18:05:07:SJ cbx_mgl 2013:01:31:18:08:27:SJ cbx_stratix 2013:01:31:18:05:07:SJ cbx_stratixii 2013:01:31:18:05:07:SJ cbx_stratixiii 2013:01:31:18:05:07:SJ cbx_stratixv 2013:01:31:18:05:07:SJ cbx_util_mgl 2013:01:31:18:05:07:SJ VERSION_END + + +-- Copyright (C) 1991-2012 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) +WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS) +RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); + +--synthesis_resources = M9K 1 +OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; + +SUBDESIGN altsyncram_gt51 +( + address_a[7..0] : input; + clock0 : input; + q_a[31..0] : output; +) +VARIABLE + ram_block1a0 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_epcs_flash_controller_boot_rom_synth.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_epcs_flash_controller_boot_rom_synth.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_epcs_flash_controller_boot_rom_synth.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a3 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_epcs_flash_controller_boot_rom_synth.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a4 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_epcs_flash_controller_boot_rom_synth.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a5 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_epcs_flash_controller_boot_rom_synth.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a6 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_epcs_flash_controller_boot_rom_synth.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a7 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_epcs_flash_controller_boot_rom_synth.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a8 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_epcs_flash_controller_boot_rom_synth.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 8, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a9 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_epcs_flash_controller_boot_rom_synth.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 9, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a10 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_epcs_flash_controller_boot_rom_synth.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 10, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a11 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_epcs_flash_controller_boot_rom_synth.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 11, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a12 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_epcs_flash_controller_boot_rom_synth.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 12, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a13 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_epcs_flash_controller_boot_rom_synth.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 13, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a14 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_epcs_flash_controller_boot_rom_synth.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 14, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a15 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_epcs_flash_controller_boot_rom_synth.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 15, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a16 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_epcs_flash_controller_boot_rom_synth.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 16, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a17 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_epcs_flash_controller_boot_rom_synth.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 17, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a18 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_epcs_flash_controller_boot_rom_synth.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 18, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a19 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_epcs_flash_controller_boot_rom_synth.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 19, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a20 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_epcs_flash_controller_boot_rom_synth.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 20, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a21 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_epcs_flash_controller_boot_rom_synth.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 21, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a22 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_epcs_flash_controller_boot_rom_synth.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 22, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a23 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_epcs_flash_controller_boot_rom_synth.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 23, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a24 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_epcs_flash_controller_boot_rom_synth.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 24, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a25 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_epcs_flash_controller_boot_rom_synth.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 25, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a26 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_epcs_flash_controller_boot_rom_synth.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 26, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a27 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_epcs_flash_controller_boot_rom_synth.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 27, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a28 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_epcs_flash_controller_boot_rom_synth.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 28, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a29 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_epcs_flash_controller_boot_rom_synth.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 29, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a30 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_epcs_flash_controller_boot_rom_synth.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 30, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a31 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_epcs_flash_controller_boot_rom_synth.hex", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 31, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + RAM_BLOCK_TYPE = "AUTO" + ); + address_a_wire[7..0] : WIRE; + +BEGIN + ram_block1a[31..0].clk0 = clock0; + ram_block1a[31..0].portaaddr[] = ( address_a_wire[7..0]); + ram_block1a[31..0].portare = B"11111111111111111111111111111111"; + address_a_wire[] = address_a[]; + q_a[] = ( ram_block1a[31..0].portadataout[0..0]); +END; +--VALID FILE diff --git a/MCTEST/DE0-nano-HD/db/altsyncram_gvf1.tdf b/MCTEST/DE0-nano-HD/db/altsyncram_gvf1.tdf new file mode 100644 index 00000000..76f45cc4 --- /dev/null +++ b/MCTEST/DE0-nano-HD/db/altsyncram_gvf1.tdf @@ -0,0 +1,1042 @@ +--altsyncram ADDRESS_REG_B="CLOCK0" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" INIT_FILE="system_cpu_rf_ram_b.mif" LOW_POWER_MODE="AUTO" MAXIMUM_DEPTH=0 NUMWORDS_A=32 NUMWORDS_B=32 OPERATION_MODE="DUAL_PORT" OUTDATA_REG_B="UNREGISTERED" RAM_BLOCK_TYPE="AUTO" RDCONTROL_REG_B="CLOCK0" READ_DURING_WRITE_MODE_MIXED_PORTS="OLD_DATA" WIDTH_A=32 WIDTH_B=32 WIDTHAD_A=5 WIDTHAD_B=5 address_a address_b clock0 data_a q_b wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 +--VERSION_BEGIN 12.1SP1 cbx_altsyncram 2013:01:31:18:05:07:SJ cbx_cycloneii 2013:01:31:18:05:07:SJ cbx_lpm_add_sub 2013:01:31:18:05:07:SJ cbx_lpm_compare 2013:01:31:18:05:07:SJ cbx_lpm_decode 2013:01:31:18:05:07:SJ cbx_lpm_mux 2013:01:31:18:05:07:SJ cbx_mgl 2013:01:31:18:08:27:SJ cbx_stratix 2013:01:31:18:05:07:SJ cbx_stratixii 2013:01:31:18:05:07:SJ cbx_stratixiii 2013:01:31:18:05:07:SJ cbx_stratixv 2013:01:31:18:05:07:SJ cbx_util_mgl 2013:01:31:18:05:07:SJ VERSION_END + + +-- Copyright (C) 1991-2012 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) +WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS) +RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); + +--synthesis_resources = M9K 1 +OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; + +SUBDESIGN altsyncram_gvf1 +( + address_a[4..0] : input; + address_b[4..0] : input; + clock0 : input; + data_a[31..0] : input; + q_b[31..0] : output; + wren_a : input; +) +VARIABLE + ram_block1a0 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a3 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a4 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a5 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a6 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a7 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a8 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 8, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 8, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a9 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 9, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 9, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a10 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 10, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 10, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a11 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 11, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 11, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a12 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 12, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 12, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a13 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 13, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 13, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a14 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 14, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 14, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a15 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 15, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 15, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a16 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 16, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 16, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a17 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 17, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 17, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a18 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 18, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 18, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a19 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 19, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 19, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a20 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 20, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 20, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a21 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 21, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 21, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a22 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 22, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 22, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a23 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 23, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 23, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a24 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 24, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 24, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a25 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 25, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 25, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a26 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 26, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 26, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a27 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 27, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 27, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a28 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 28, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 28, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a29 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 29, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 29, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a30 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 30, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 30, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a31 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_rf_ram_b.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 31, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 5, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 31, + PORT_B_LAST_ADDRESS = 31, + PORT_B_LOGICAL_RAM_DEPTH = 32, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + address_a_wire[4..0] : WIRE; + address_b_wire[4..0] : WIRE; + +BEGIN + ram_block1a[31..0].clk0 = clock0; + ram_block1a[31..0].portaaddr[] = ( address_a_wire[4..0]); + ram_block1a[0].portadatain[] = ( data_a[0..0]); + ram_block1a[1].portadatain[] = ( data_a[1..1]); + ram_block1a[2].portadatain[] = ( data_a[2..2]); + ram_block1a[3].portadatain[] = ( data_a[3..3]); + ram_block1a[4].portadatain[] = ( data_a[4..4]); + ram_block1a[5].portadatain[] = ( data_a[5..5]); + ram_block1a[6].portadatain[] = ( data_a[6..6]); + ram_block1a[7].portadatain[] = ( data_a[7..7]); + ram_block1a[8].portadatain[] = ( data_a[8..8]); + ram_block1a[9].portadatain[] = ( data_a[9..9]); + ram_block1a[10].portadatain[] = ( data_a[10..10]); + ram_block1a[11].portadatain[] = ( data_a[11..11]); + ram_block1a[12].portadatain[] = ( data_a[12..12]); + ram_block1a[13].portadatain[] = ( data_a[13..13]); + ram_block1a[14].portadatain[] = ( data_a[14..14]); + ram_block1a[15].portadatain[] = ( data_a[15..15]); + ram_block1a[16].portadatain[] = ( data_a[16..16]); + ram_block1a[17].portadatain[] = ( data_a[17..17]); + ram_block1a[18].portadatain[] = ( data_a[18..18]); + ram_block1a[19].portadatain[] = ( data_a[19..19]); + ram_block1a[20].portadatain[] = ( data_a[20..20]); + ram_block1a[21].portadatain[] = ( data_a[21..21]); + ram_block1a[22].portadatain[] = ( data_a[22..22]); + ram_block1a[23].portadatain[] = ( data_a[23..23]); + ram_block1a[24].portadatain[] = ( data_a[24..24]); + ram_block1a[25].portadatain[] = ( data_a[25..25]); + ram_block1a[26].portadatain[] = ( data_a[26..26]); + ram_block1a[27].portadatain[] = ( data_a[27..27]); + ram_block1a[28].portadatain[] = ( data_a[28..28]); + ram_block1a[29].portadatain[] = ( data_a[29..29]); + ram_block1a[30].portadatain[] = ( data_a[30..30]); + ram_block1a[31].portadatain[] = ( data_a[31..31]); + ram_block1a[31..0].portawe = wren_a; + ram_block1a[31..0].portbaddr[] = ( address_b_wire[4..0]); + ram_block1a[31..0].portbre = B"11111111111111111111111111111111"; + address_a_wire[] = address_a[]; + address_b_wire[] = address_b[]; + q_b[] = ( ram_block1a[31..0].portbdataout[0..0]); +END; +--VALID FILE diff --git a/MCTEST/DE0-nano-HD/db/altsyncram_je81.tdf b/MCTEST/DE0-nano-HD/db/altsyncram_je81.tdf new file mode 100644 index 00000000..dba6283b --- /dev/null +++ b/MCTEST/DE0-nano-HD/db/altsyncram_je81.tdf @@ -0,0 +1,300 @@ +--altsyncram ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK0" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" INDATA_ACLR_A="NONE" LOW_POWER_MODE="AUTO" NUMWORDS_A=128 NUMWORDS_B=128 OPERATION_MODE="DUAL_PORT" OUTDATA_REG_B="UNREGISTERED" WIDTH_A=8 WIDTH_B=8 WIDTH_BYTEENA_A=1 WIDTHAD_A=7 WIDTHAD_B=7 WRCONTROL_ACLR_A="NONE" address_a address_b clock0 data_a q_b wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 +--VERSION_BEGIN 12.1SP1 cbx_altsyncram 2013:01:31:18:05:07:SJ cbx_cycloneii 2013:01:31:18:05:07:SJ cbx_lpm_add_sub 2013:01:31:18:05:07:SJ cbx_lpm_compare 2013:01:31:18:05:07:SJ cbx_lpm_decode 2013:01:31:18:05:07:SJ cbx_lpm_mux 2013:01:31:18:05:07:SJ cbx_mgl 2013:01:31:18:08:27:SJ cbx_stratix 2013:01:31:18:05:07:SJ cbx_stratixii 2013:01:31:18:05:07:SJ cbx_stratixiii 2013:01:31:18:05:07:SJ cbx_stratixv 2013:01:31:18:05:07:SJ cbx_util_mgl 2013:01:31:18:05:07:SJ VERSION_END + + +-- Copyright (C) 1991-2012 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) +WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS) +RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); + +--synthesis_resources = M9K 1 +OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; + +SUBDESIGN altsyncram_je81 +( + address_a[6..0] : input; + address_b[6..0] : input; + clock0 : input; + data_a[7..0] : input; + q_b[7..0] : output; + wren_a : input; +) +VARIABLE + ram_block1a0 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "none", + CLK1_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 7, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 127, + PORT_A_LOGICAL_RAM_DEPTH = 128, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 7, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 127, + PORT_B_LOGICAL_RAM_DEPTH = 128, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "none", + CLK1_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 7, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 127, + PORT_A_LOGICAL_RAM_DEPTH = 128, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 7, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 127, + PORT_B_LOGICAL_RAM_DEPTH = 128, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "none", + CLK1_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 7, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 127, + PORT_A_LOGICAL_RAM_DEPTH = 128, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 7, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 127, + PORT_B_LOGICAL_RAM_DEPTH = 128, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a3 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "none", + CLK1_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 7, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 127, + PORT_A_LOGICAL_RAM_DEPTH = 128, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 7, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 127, + PORT_B_LOGICAL_RAM_DEPTH = 128, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a4 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "none", + CLK1_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 7, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 127, + PORT_A_LOGICAL_RAM_DEPTH = 128, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 7, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 127, + PORT_B_LOGICAL_RAM_DEPTH = 128, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a5 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "none", + CLK1_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 7, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 127, + PORT_A_LOGICAL_RAM_DEPTH = 128, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 7, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 127, + PORT_B_LOGICAL_RAM_DEPTH = 128, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a6 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "none", + CLK1_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 7, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 127, + PORT_A_LOGICAL_RAM_DEPTH = 128, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 7, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 127, + PORT_B_LOGICAL_RAM_DEPTH = 128, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a7 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "none", + CLK1_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 7, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 127, + PORT_A_LOGICAL_RAM_DEPTH = 128, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 7, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 127, + PORT_B_LOGICAL_RAM_DEPTH = 128, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + address_a_wire[6..0] : WIRE; + address_b_wire[6..0] : WIRE; + +BEGIN + ram_block1a[7..0].clk0 = clock0; + ram_block1a[7..0].clk1 = clock0; + ram_block1a[7..0].ena0 = wren_a; + ram_block1a[7..0].portaaddr[] = ( address_a_wire[6..0]); + ram_block1a[0].portadatain[] = ( data_a[0..0]); + ram_block1a[1].portadatain[] = ( data_a[1..1]); + ram_block1a[2].portadatain[] = ( data_a[2..2]); + ram_block1a[3].portadatain[] = ( data_a[3..3]); + ram_block1a[4].portadatain[] = ( data_a[4..4]); + ram_block1a[5].portadatain[] = ( data_a[5..5]); + ram_block1a[6].portadatain[] = ( data_a[6..6]); + ram_block1a[7].portadatain[] = ( data_a[7..7]); + ram_block1a[7..0].portawe = wren_a; + ram_block1a[7..0].portbaddr[] = ( address_b_wire[6..0]); + ram_block1a[7..0].portbre = B"11111111"; + address_a_wire[] = address_a[]; + address_b_wire[] = address_b[]; + q_b[] = ( ram_block1a[7..0].portbdataout[0..0]); +END; +--VALID FILE diff --git a/MCTEST/DE0-nano-HD/db/altsyncram_jt72.tdf b/MCTEST/DE0-nano-HD/db/altsyncram_jt72.tdf new file mode 100644 index 00000000..380050f8 --- /dev/null +++ b/MCTEST/DE0-nano-HD/db/altsyncram_jt72.tdf @@ -0,0 +1,1347 @@ +--altsyncram ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK1" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" INDATA_ACLR_A="NONE" INDATA_ACLR_B="NONE" INIT_FILE="system_cpu_ociram_default_contents.mif" LOW_POWER_MODE="AUTO" NUMWORDS_A=256 NUMWORDS_B=256 OPERATION_MODE="BIDIR_DUAL_PORT" OUTDATA_ACLR_A="NONE" OUTDATA_ACLR_B="NONE" OUTDATA_REG_A="UNREGISTERED" OUTDATA_REG_B="UNREGISTERED" RAM_BLOCK_TYPE="AUTO" READ_DURING_WRITE_MODE_MIXED_PORTS="OLD_DATA" WIDTH_A=32 WIDTH_B=32 WIDTH_BYTEENA_A=4 WIDTHAD_A=8 WIDTHAD_B=8 WRCONTROL_ACLR_A="NONE" WRCONTROL_ACLR_B="NONE" address_a address_b byteena_a clock0 clock1 clocken0 clocken1 data_a data_b q_a q_b wren_a wren_b CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 +--VERSION_BEGIN 12.1SP1 cbx_altsyncram 2013:01:31:18:05:07:SJ cbx_cycloneii 2013:01:31:18:05:07:SJ cbx_lpm_add_sub 2013:01:31:18:05:07:SJ cbx_lpm_compare 2013:01:31:18:05:07:SJ cbx_lpm_decode 2013:01:31:18:05:07:SJ cbx_lpm_mux 2013:01:31:18:05:07:SJ cbx_mgl 2013:01:31:18:08:27:SJ cbx_stratix 2013:01:31:18:05:07:SJ cbx_stratixii 2013:01:31:18:05:07:SJ cbx_stratixiii 2013:01:31:18:05:07:SJ cbx_stratixv 2013:01:31:18:05:07:SJ cbx_util_mgl 2013:01:31:18:05:07:SJ VERSION_END + + +-- Copyright (C) 1991-2012 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) +WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS) +RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); + +--synthesis_resources = M9K 2 +OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; + +SUBDESIGN altsyncram_jt72 +( + address_a[7..0] : input; + address_b[7..0] : input; + byteena_a[3..0] : input; + clock0 : input; + clock1 : input; + clocken0 : input; + clocken1 : input; + data_a[31..0] : input; + data_b[31..0] : input; + q_a[31..0] : output; + q_b[31..0] : output; + wren_a : input; + wren_b : input; +) +VARIABLE + ram_block1a0 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 8, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 255, + PORT_B_LOGICAL_RAM_DEPTH = 256, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 8, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 255, + PORT_B_LOGICAL_RAM_DEPTH = 256, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 8, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 255, + PORT_B_LOGICAL_RAM_DEPTH = 256, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a3 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 8, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 255, + PORT_B_LOGICAL_RAM_DEPTH = 256, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a4 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 8, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 255, + PORT_B_LOGICAL_RAM_DEPTH = 256, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a5 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 8, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 255, + PORT_B_LOGICAL_RAM_DEPTH = 256, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a6 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 8, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 255, + PORT_B_LOGICAL_RAM_DEPTH = 256, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a7 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 8, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 255, + PORT_B_LOGICAL_RAM_DEPTH = 256, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a8 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 8, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 8, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 8, + PORT_B_LAST_ADDRESS = 255, + PORT_B_LOGICAL_RAM_DEPTH = 256, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a9 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 9, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 8, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 9, + PORT_B_LAST_ADDRESS = 255, + PORT_B_LOGICAL_RAM_DEPTH = 256, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a10 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 10, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 8, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 10, + PORT_B_LAST_ADDRESS = 255, + PORT_B_LOGICAL_RAM_DEPTH = 256, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a11 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 11, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 8, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 11, + PORT_B_LAST_ADDRESS = 255, + PORT_B_LOGICAL_RAM_DEPTH = 256, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a12 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 12, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 8, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 12, + PORT_B_LAST_ADDRESS = 255, + PORT_B_LOGICAL_RAM_DEPTH = 256, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a13 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 13, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 8, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 13, + PORT_B_LAST_ADDRESS = 255, + PORT_B_LOGICAL_RAM_DEPTH = 256, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a14 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 14, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 8, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 14, + PORT_B_LAST_ADDRESS = 255, + PORT_B_LOGICAL_RAM_DEPTH = 256, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a15 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 15, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 8, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 15, + PORT_B_LAST_ADDRESS = 255, + PORT_B_LOGICAL_RAM_DEPTH = 256, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a16 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 16, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 8, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 16, + PORT_B_LAST_ADDRESS = 255, + PORT_B_LOGICAL_RAM_DEPTH = 256, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a17 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 17, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 8, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 17, + PORT_B_LAST_ADDRESS = 255, + PORT_B_LOGICAL_RAM_DEPTH = 256, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a18 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 18, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 8, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 18, + PORT_B_LAST_ADDRESS = 255, + PORT_B_LOGICAL_RAM_DEPTH = 256, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a19 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 19, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 8, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 19, + PORT_B_LAST_ADDRESS = 255, + PORT_B_LOGICAL_RAM_DEPTH = 256, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a20 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 20, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 8, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 20, + PORT_B_LAST_ADDRESS = 255, + PORT_B_LOGICAL_RAM_DEPTH = 256, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a21 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 21, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 8, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 21, + PORT_B_LAST_ADDRESS = 255, + PORT_B_LOGICAL_RAM_DEPTH = 256, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a22 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 22, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 8, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 22, + PORT_B_LAST_ADDRESS = 255, + PORT_B_LOGICAL_RAM_DEPTH = 256, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a23 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 23, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 8, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 23, + PORT_B_LAST_ADDRESS = 255, + PORT_B_LOGICAL_RAM_DEPTH = 256, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a24 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 24, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 8, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 24, + PORT_B_LAST_ADDRESS = 255, + PORT_B_LOGICAL_RAM_DEPTH = 256, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a25 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 25, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 8, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 25, + PORT_B_LAST_ADDRESS = 255, + PORT_B_LOGICAL_RAM_DEPTH = 256, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a26 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 26, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 8, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 26, + PORT_B_LAST_ADDRESS = 255, + PORT_B_LOGICAL_RAM_DEPTH = 256, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a27 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 27, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 8, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 27, + PORT_B_LAST_ADDRESS = 255, + PORT_B_LOGICAL_RAM_DEPTH = 256, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a28 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 28, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 8, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 28, + PORT_B_LAST_ADDRESS = 255, + PORT_B_LOGICAL_RAM_DEPTH = 256, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a29 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 29, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 8, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 29, + PORT_B_LAST_ADDRESS = 255, + PORT_B_LOGICAL_RAM_DEPTH = 256, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a30 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 30, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 8, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 30, + PORT_B_LAST_ADDRESS = 255, + PORT_B_LOGICAL_RAM_DEPTH = 256, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a31 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "ena0", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_ociram_default_contents.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "bidir_dual_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, + PORT_A_BYTE_SIZE = 1, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 31, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 8, + PORT_B_DATA_IN_CLOCK = "clock1", + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 31, + PORT_B_LAST_ADDRESS = 255, + PORT_B_LOGICAL_RAM_DEPTH = 256, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read", + PORT_B_READ_ENABLE_CLOCK = "clock1", + PORT_B_WRITE_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + address_a_wire[7..0] : WIRE; + address_b_wire[7..0] : WIRE; + +BEGIN + ram_block1a[31..0].clk0 = clock0; + ram_block1a[31..0].clk1 = clock1; + ram_block1a[31..0].ena0 = clocken0; + ram_block1a[31..0].ena1 = clocken1; + ram_block1a[31..0].portaaddr[] = ( address_a_wire[7..0]); + ram_block1a[7..0].portabyteenamasks[] = ( byteena_a[0..0]); + ram_block1a[15..8].portabyteenamasks[] = ( byteena_a[1..1]); + ram_block1a[23..16].portabyteenamasks[] = ( byteena_a[2..2]); + ram_block1a[31..24].portabyteenamasks[] = ( byteena_a[3..3]); + ram_block1a[0].portadatain[] = ( data_a[0..0]); + ram_block1a[1].portadatain[] = ( data_a[1..1]); + ram_block1a[2].portadatain[] = ( data_a[2..2]); + ram_block1a[3].portadatain[] = ( data_a[3..3]); + ram_block1a[4].portadatain[] = ( data_a[4..4]); + ram_block1a[5].portadatain[] = ( data_a[5..5]); + ram_block1a[6].portadatain[] = ( data_a[6..6]); + ram_block1a[7].portadatain[] = ( data_a[7..7]); + ram_block1a[8].portadatain[] = ( data_a[8..8]); + ram_block1a[9].portadatain[] = ( data_a[9..9]); + ram_block1a[10].portadatain[] = ( data_a[10..10]); + ram_block1a[11].portadatain[] = ( data_a[11..11]); + ram_block1a[12].portadatain[] = ( data_a[12..12]); + ram_block1a[13].portadatain[] = ( data_a[13..13]); + ram_block1a[14].portadatain[] = ( data_a[14..14]); + ram_block1a[15].portadatain[] = ( data_a[15..15]); + ram_block1a[16].portadatain[] = ( data_a[16..16]); + ram_block1a[17].portadatain[] = ( data_a[17..17]); + ram_block1a[18].portadatain[] = ( data_a[18..18]); + ram_block1a[19].portadatain[] = ( data_a[19..19]); + ram_block1a[20].portadatain[] = ( data_a[20..20]); + ram_block1a[21].portadatain[] = ( data_a[21..21]); + ram_block1a[22].portadatain[] = ( data_a[22..22]); + ram_block1a[23].portadatain[] = ( data_a[23..23]); + ram_block1a[24].portadatain[] = ( data_a[24..24]); + ram_block1a[25].portadatain[] = ( data_a[25..25]); + ram_block1a[26].portadatain[] = ( data_a[26..26]); + ram_block1a[27].portadatain[] = ( data_a[27..27]); + ram_block1a[28].portadatain[] = ( data_a[28..28]); + ram_block1a[29].portadatain[] = ( data_a[29..29]); + ram_block1a[30].portadatain[] = ( data_a[30..30]); + ram_block1a[31].portadatain[] = ( data_a[31..31]); + ram_block1a[31..0].portare = B"11111111111111111111111111111111"; + ram_block1a[31..0].portawe = wren_a; + ram_block1a[31..0].portbaddr[] = ( address_b_wire[7..0]); + ram_block1a[0].portbdatain[] = ( data_b[0..0]); + ram_block1a[1].portbdatain[] = ( data_b[1..1]); + ram_block1a[2].portbdatain[] = ( data_b[2..2]); + ram_block1a[3].portbdatain[] = ( data_b[3..3]); + ram_block1a[4].portbdatain[] = ( data_b[4..4]); + ram_block1a[5].portbdatain[] = ( data_b[5..5]); + ram_block1a[6].portbdatain[] = ( data_b[6..6]); + ram_block1a[7].portbdatain[] = ( data_b[7..7]); + ram_block1a[8].portbdatain[] = ( data_b[8..8]); + ram_block1a[9].portbdatain[] = ( data_b[9..9]); + ram_block1a[10].portbdatain[] = ( data_b[10..10]); + ram_block1a[11].portbdatain[] = ( data_b[11..11]); + ram_block1a[12].portbdatain[] = ( data_b[12..12]); + ram_block1a[13].portbdatain[] = ( data_b[13..13]); + ram_block1a[14].portbdatain[] = ( data_b[14..14]); + ram_block1a[15].portbdatain[] = ( data_b[15..15]); + ram_block1a[16].portbdatain[] = ( data_b[16..16]); + ram_block1a[17].portbdatain[] = ( data_b[17..17]); + ram_block1a[18].portbdatain[] = ( data_b[18..18]); + ram_block1a[19].portbdatain[] = ( data_b[19..19]); + ram_block1a[20].portbdatain[] = ( data_b[20..20]); + ram_block1a[21].portbdatain[] = ( data_b[21..21]); + ram_block1a[22].portbdatain[] = ( data_b[22..22]); + ram_block1a[23].portbdatain[] = ( data_b[23..23]); + ram_block1a[24].portbdatain[] = ( data_b[24..24]); + ram_block1a[25].portbdatain[] = ( data_b[25..25]); + ram_block1a[26].portbdatain[] = ( data_b[26..26]); + ram_block1a[27].portbdatain[] = ( data_b[27..27]); + ram_block1a[28].portbdatain[] = ( data_b[28..28]); + ram_block1a[29].portbdatain[] = ( data_b[29..29]); + ram_block1a[30].portbdatain[] = ( data_b[30..30]); + ram_block1a[31].portbdatain[] = ( data_b[31..31]); + ram_block1a[31..0].portbre = B"11111111111111111111111111111111"; + ram_block1a[31..0].portbwe = wren_b; + address_a_wire[] = address_a[]; + address_b_wire[] = address_b[]; + q_a[] = ( ram_block1a[31..0].portadataout[0..0]); + q_b[] = ( ram_block1a[31..0].portbdataout[0..0]); +END; +--VALID FILE diff --git a/MCTEST/DE0-nano-HD/db/altsyncram_qtg1.tdf b/MCTEST/DE0-nano-HD/db/altsyncram_qtg1.tdf new file mode 100644 index 00000000..dd52fd2a --- /dev/null +++ b/MCTEST/DE0-nano-HD/db/altsyncram_qtg1.tdf @@ -0,0 +1,702 @@ +--altsyncram ADDRESS_REG_B="CLOCK0" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" INIT_FILE="system_cpu_ic_tag_ram.mif" LOW_POWER_MODE="AUTO" MAXIMUM_DEPTH=0 NUMWORDS_A=256 NUMWORDS_B=256 OPERATION_MODE="DUAL_PORT" OUTDATA_REG_B="UNREGISTERED" RAM_BLOCK_TYPE="AUTO" RDCONTROL_REG_B="CLOCK0" READ_DURING_WRITE_MODE_MIXED_PORTS="OLD_DATA" WIDTH_A=21 WIDTH_B=21 WIDTHAD_A=8 WIDTHAD_B=8 address_a address_b clock0 data_a q_b rden_b wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 +--VERSION_BEGIN 12.1SP1 cbx_altsyncram 2013:01:31:18:05:07:SJ cbx_cycloneii 2013:01:31:18:05:07:SJ cbx_lpm_add_sub 2013:01:31:18:05:07:SJ cbx_lpm_compare 2013:01:31:18:05:07:SJ cbx_lpm_decode 2013:01:31:18:05:07:SJ cbx_lpm_mux 2013:01:31:18:05:07:SJ cbx_mgl 2013:01:31:18:08:27:SJ cbx_stratix 2013:01:31:18:05:07:SJ cbx_stratixii 2013:01:31:18:05:07:SJ cbx_stratixiii 2013:01:31:18:05:07:SJ cbx_stratixv 2013:01:31:18:05:07:SJ cbx_util_mgl 2013:01:31:18:05:07:SJ VERSION_END + + +-- Copyright (C) 1991-2012 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) +WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS) +RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); + +--synthesis_resources = M9K 1 +OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; + +SUBDESIGN altsyncram_qtg1 +( + address_a[7..0] : input; + address_b[7..0] : input; + clock0 : input; + data_a[20..0] : input; + q_b[20..0] : output; + rden_b : input; + wren_a : input; +) +VARIABLE + ram_block1a0 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_ic_tag_ram.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 21, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 8, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 255, + PORT_B_LOGICAL_RAM_DEPTH = 256, + PORT_B_LOGICAL_RAM_WIDTH = 21, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_ic_tag_ram.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 21, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 8, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 255, + PORT_B_LOGICAL_RAM_DEPTH = 256, + PORT_B_LOGICAL_RAM_WIDTH = 21, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_ic_tag_ram.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 21, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 8, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 255, + PORT_B_LOGICAL_RAM_DEPTH = 256, + PORT_B_LOGICAL_RAM_WIDTH = 21, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a3 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_ic_tag_ram.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 21, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 8, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 255, + PORT_B_LOGICAL_RAM_DEPTH = 256, + PORT_B_LOGICAL_RAM_WIDTH = 21, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a4 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_ic_tag_ram.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 21, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 8, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 255, + PORT_B_LOGICAL_RAM_DEPTH = 256, + PORT_B_LOGICAL_RAM_WIDTH = 21, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a5 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_ic_tag_ram.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 21, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 8, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 255, + PORT_B_LOGICAL_RAM_DEPTH = 256, + PORT_B_LOGICAL_RAM_WIDTH = 21, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a6 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_ic_tag_ram.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 21, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 8, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 255, + PORT_B_LOGICAL_RAM_DEPTH = 256, + PORT_B_LOGICAL_RAM_WIDTH = 21, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a7 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_ic_tag_ram.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 21, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 8, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 255, + PORT_B_LOGICAL_RAM_DEPTH = 256, + PORT_B_LOGICAL_RAM_WIDTH = 21, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a8 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_ic_tag_ram.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 8, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 21, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 8, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 8, + PORT_B_LAST_ADDRESS = 255, + PORT_B_LOGICAL_RAM_DEPTH = 256, + PORT_B_LOGICAL_RAM_WIDTH = 21, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a9 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_ic_tag_ram.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 9, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 21, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 8, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 9, + PORT_B_LAST_ADDRESS = 255, + PORT_B_LOGICAL_RAM_DEPTH = 256, + PORT_B_LOGICAL_RAM_WIDTH = 21, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a10 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_ic_tag_ram.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 10, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 21, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 8, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 10, + PORT_B_LAST_ADDRESS = 255, + PORT_B_LOGICAL_RAM_DEPTH = 256, + PORT_B_LOGICAL_RAM_WIDTH = 21, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a11 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_ic_tag_ram.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 11, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 21, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 8, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 11, + PORT_B_LAST_ADDRESS = 255, + PORT_B_LOGICAL_RAM_DEPTH = 256, + PORT_B_LOGICAL_RAM_WIDTH = 21, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a12 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_ic_tag_ram.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 12, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 21, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 8, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 12, + PORT_B_LAST_ADDRESS = 255, + PORT_B_LOGICAL_RAM_DEPTH = 256, + PORT_B_LOGICAL_RAM_WIDTH = 21, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a13 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_ic_tag_ram.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 13, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 21, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 8, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 13, + PORT_B_LAST_ADDRESS = 255, + PORT_B_LOGICAL_RAM_DEPTH = 256, + PORT_B_LOGICAL_RAM_WIDTH = 21, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a14 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_ic_tag_ram.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 14, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 21, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 8, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 14, + PORT_B_LAST_ADDRESS = 255, + PORT_B_LOGICAL_RAM_DEPTH = 256, + PORT_B_LOGICAL_RAM_WIDTH = 21, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a15 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_ic_tag_ram.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 15, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 21, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 8, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 15, + PORT_B_LAST_ADDRESS = 255, + PORT_B_LOGICAL_RAM_DEPTH = 256, + PORT_B_LOGICAL_RAM_WIDTH = 21, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a16 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_ic_tag_ram.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 16, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 21, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 8, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 16, + PORT_B_LAST_ADDRESS = 255, + PORT_B_LOGICAL_RAM_DEPTH = 256, + PORT_B_LOGICAL_RAM_WIDTH = 21, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a17 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_ic_tag_ram.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 17, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 21, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 8, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 17, + PORT_B_LAST_ADDRESS = 255, + PORT_B_LOGICAL_RAM_DEPTH = 256, + PORT_B_LOGICAL_RAM_WIDTH = 21, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a18 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_ic_tag_ram.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 18, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 21, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 8, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 18, + PORT_B_LAST_ADDRESS = 255, + PORT_B_LOGICAL_RAM_DEPTH = 256, + PORT_B_LOGICAL_RAM_WIDTH = 21, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a19 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_ic_tag_ram.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 19, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 21, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 8, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 19, + PORT_B_LAST_ADDRESS = 255, + PORT_B_LOGICAL_RAM_DEPTH = 256, + PORT_B_LOGICAL_RAM_WIDTH = 21, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a20 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "system_cpu_ic_tag_ram.mif", + INIT_FILE_LAYOUT = "port_b", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 8, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 20, + PORT_A_LAST_ADDRESS = 255, + PORT_A_LOGICAL_RAM_DEPTH = 256, + PORT_A_LOGICAL_RAM_WIDTH = 21, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 8, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 20, + PORT_B_LAST_ADDRESS = 255, + PORT_B_LOGICAL_RAM_DEPTH = 256, + PORT_B_LOGICAL_RAM_WIDTH = 21, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + address_a_wire[7..0] : WIRE; + address_b_wire[7..0] : WIRE; + +BEGIN + ram_block1a[20..0].clk0 = clock0; + ram_block1a[20..0].portaaddr[] = ( address_a_wire[7..0]); + ram_block1a[0].portadatain[] = ( data_a[0..0]); + ram_block1a[1].portadatain[] = ( data_a[1..1]); + ram_block1a[2].portadatain[] = ( data_a[2..2]); + ram_block1a[3].portadatain[] = ( data_a[3..3]); + ram_block1a[4].portadatain[] = ( data_a[4..4]); + ram_block1a[5].portadatain[] = ( data_a[5..5]); + ram_block1a[6].portadatain[] = ( data_a[6..6]); + ram_block1a[7].portadatain[] = ( data_a[7..7]); + ram_block1a[8].portadatain[] = ( data_a[8..8]); + ram_block1a[9].portadatain[] = ( data_a[9..9]); + ram_block1a[10].portadatain[] = ( data_a[10..10]); + ram_block1a[11].portadatain[] = ( data_a[11..11]); + ram_block1a[12].portadatain[] = ( data_a[12..12]); + ram_block1a[13].portadatain[] = ( data_a[13..13]); + ram_block1a[14].portadatain[] = ( data_a[14..14]); + ram_block1a[15].portadatain[] = ( data_a[15..15]); + ram_block1a[16].portadatain[] = ( data_a[16..16]); + ram_block1a[17].portadatain[] = ( data_a[17..17]); + ram_block1a[18].portadatain[] = ( data_a[18..18]); + ram_block1a[19].portadatain[] = ( data_a[19..19]); + ram_block1a[20].portadatain[] = ( data_a[20..20]); + ram_block1a[20..0].portawe = wren_a; + ram_block1a[20..0].portbaddr[] = ( address_b_wire[7..0]); + ram_block1a[20..0].portbre = rden_b; + address_a_wire[] = address_a[]; + address_b_wire[] = address_b[]; + q_b[] = ( ram_block1a[20..0].portbdataout[0..0]); +END; +--VALID FILE diff --git a/MCTEST/DE0-nano-HD/db/altsyncram_r1m1.tdf b/MCTEST/DE0-nano-HD/db/altsyncram_r1m1.tdf new file mode 100644 index 00000000..f4703767 --- /dev/null +++ b/MCTEST/DE0-nano-HD/db/altsyncram_r1m1.tdf @@ -0,0 +1,303 @@ +--altsyncram ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK1" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" INDATA_ACLR_A="NONE" LOW_POWER_MODE="AUTO" OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="NONE" OUTDATA_REG_B="UNREGISTERED" RAM_BLOCK_TYPE="AUTO" RDCONTROL_ACLR_B="NONE" RDCONTROL_REG_B="CLOCK0" READ_DURING_WRITE_MODE_MIXED_PORTS="DONT_CARE" WIDTH_A=8 WIDTH_B=8 WIDTH_BYTEENA_A=1 WIDTH_BYTEENA_B=1 WIDTHAD_A=6 WIDTHAD_B=6 WRCONTROL_ACLR_A="NONE" address_a address_b clock0 clock1 clocken1 data_a q_b wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 +--VERSION_BEGIN 12.1SP1 cbx_altsyncram 2013:01:31:18:05:07:SJ cbx_cycloneii 2013:01:31:18:05:07:SJ cbx_lpm_add_sub 2013:01:31:18:05:07:SJ cbx_lpm_compare 2013:01:31:18:05:07:SJ cbx_lpm_decode 2013:01:31:18:05:07:SJ cbx_lpm_mux 2013:01:31:18:05:07:SJ cbx_mgl 2013:01:31:18:08:27:SJ cbx_stratix 2013:01:31:18:05:07:SJ cbx_stratixii 2013:01:31:18:05:07:SJ cbx_stratixiii 2013:01:31:18:05:07:SJ cbx_stratixv 2013:01:31:18:05:07:SJ cbx_util_mgl 2013:01:31:18:05:07:SJ VERSION_END + + +-- Copyright (C) 1991-2012 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) +WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS) +RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); + +--synthesis_resources = M9K 1 +OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; + +SUBDESIGN altsyncram_r1m1 +( + address_a[5..0] : input; + address_b[5..0] : input; + clock0 : input; + clock1 : input; + clocken1 : input; + data_a[7..0] : input; + q_b[7..0] : output; + wren_a : input; +) +VARIABLE + ram_block2a0 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 6, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 63, + PORT_A_LOGICAL_RAM_DEPTH = 64, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 6, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 63, + PORT_B_LOGICAL_RAM_DEPTH = 64, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block2a1 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 6, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 63, + PORT_A_LOGICAL_RAM_DEPTH = 64, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 6, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 63, + PORT_B_LOGICAL_RAM_DEPTH = 64, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block2a2 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 6, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 63, + PORT_A_LOGICAL_RAM_DEPTH = 64, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 6, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 63, + PORT_B_LOGICAL_RAM_DEPTH = 64, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block2a3 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 6, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 63, + PORT_A_LOGICAL_RAM_DEPTH = 64, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 6, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 63, + PORT_B_LOGICAL_RAM_DEPTH = 64, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block2a4 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 6, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 63, + PORT_A_LOGICAL_RAM_DEPTH = 64, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 6, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 63, + PORT_B_LOGICAL_RAM_DEPTH = 64, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block2a5 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 6, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 63, + PORT_A_LOGICAL_RAM_DEPTH = 64, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 6, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 63, + PORT_B_LOGICAL_RAM_DEPTH = 64, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block2a6 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 6, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 63, + PORT_A_LOGICAL_RAM_DEPTH = 64, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 6, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 63, + PORT_B_LOGICAL_RAM_DEPTH = 64, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block2a7 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "ena1", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 6, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 63, + PORT_A_LOGICAL_RAM_DEPTH = 64, + PORT_A_LOGICAL_RAM_WIDTH = 8, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 6, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 63, + PORT_B_LOGICAL_RAM_DEPTH = 64, + PORT_B_LOGICAL_RAM_WIDTH = 8, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + address_a_wire[5..0] : WIRE; + address_b_wire[5..0] : WIRE; + +BEGIN + ram_block2a[7..0].clk0 = clock0; + ram_block2a[7..0].clk1 = clock1; + ram_block2a[7..0].ena0 = wren_a; + ram_block2a[7..0].ena1 = clocken1; + ram_block2a[7..0].portaaddr[] = ( address_a_wire[5..0]); + ram_block2a[0].portadatain[] = ( data_a[0..0]); + ram_block2a[1].portadatain[] = ( data_a[1..1]); + ram_block2a[2].portadatain[] = ( data_a[2..2]); + ram_block2a[3].portadatain[] = ( data_a[3..3]); + ram_block2a[4].portadatain[] = ( data_a[4..4]); + ram_block2a[5].portadatain[] = ( data_a[5..5]); + ram_block2a[6].portadatain[] = ( data_a[6..6]); + ram_block2a[7].portadatain[] = ( data_a[7..7]); + ram_block2a[7..0].portawe = wren_a; + ram_block2a[7..0].portbaddr[] = ( address_b_wire[5..0]); + ram_block2a[7..0].portbre = B"11111111"; + address_a_wire[] = address_a[]; + address_b_wire[] = address_b[]; + q_b[] = ( ram_block2a[7..0].portbdataout[0..0]); +END; +--VALID FILE diff --git a/MCTEST/DE0-nano-HD/db/altsyncram_r3d1.tdf b/MCTEST/DE0-nano-HD/db/altsyncram_r3d1.tdf new file mode 100644 index 00000000..971e4f31 --- /dev/null +++ b/MCTEST/DE0-nano-HD/db/altsyncram_r3d1.tdf @@ -0,0 +1,979 @@ +--altsyncram ADDRESS_REG_B="CLOCK0" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" LOW_POWER_MODE="AUTO" MAXIMUM_DEPTH=0 NUMWORDS_A=8 NUMWORDS_B=8 OPERATION_MODE="DUAL_PORT" OUTDATA_REG_B="UNREGISTERED" RAM_BLOCK_TYPE="AUTO" RDCONTROL_REG_B="CLOCK0" READ_DURING_WRITE_MODE_MIXED_PORTS="OLD_DATA" WIDTH_A=32 WIDTH_B=32 WIDTHAD_A=3 WIDTHAD_B=3 address_a address_b clock0 data_a q_b rden_b wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 +--VERSION_BEGIN 12.1SP1 cbx_altsyncram 2013:01:31:18:05:07:SJ cbx_cycloneii 2013:01:31:18:05:07:SJ cbx_lpm_add_sub 2013:01:31:18:05:07:SJ cbx_lpm_compare 2013:01:31:18:05:07:SJ cbx_lpm_decode 2013:01:31:18:05:07:SJ cbx_lpm_mux 2013:01:31:18:05:07:SJ cbx_mgl 2013:01:31:18:08:27:SJ cbx_stratix 2013:01:31:18:05:07:SJ cbx_stratixii 2013:01:31:18:05:07:SJ cbx_stratixiii 2013:01:31:18:05:07:SJ cbx_stratixv 2013:01:31:18:05:07:SJ cbx_util_mgl 2013:01:31:18:05:07:SJ VERSION_END + + +-- Copyright (C) 1991-2012 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) +WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS) +RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); + +--synthesis_resources = M9K 1 +OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; + +SUBDESIGN altsyncram_r3d1 +( + address_a[2..0] : input; + address_b[2..0] : input; + clock0 : input; + data_a[31..0] : input; + q_b[31..0] : output; + rden_b : input; + wren_a : input; +) +VARIABLE + ram_block1a0 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 3, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 7, + PORT_A_LOGICAL_RAM_DEPTH = 8, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 3, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 7, + PORT_B_LOGICAL_RAM_DEPTH = 8, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 3, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 7, + PORT_A_LOGICAL_RAM_DEPTH = 8, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 3, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 7, + PORT_B_LOGICAL_RAM_DEPTH = 8, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 3, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 7, + PORT_A_LOGICAL_RAM_DEPTH = 8, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 3, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 7, + PORT_B_LOGICAL_RAM_DEPTH = 8, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a3 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 3, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 7, + PORT_A_LOGICAL_RAM_DEPTH = 8, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 3, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 7, + PORT_B_LOGICAL_RAM_DEPTH = 8, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a4 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 3, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 7, + PORT_A_LOGICAL_RAM_DEPTH = 8, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 3, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 7, + PORT_B_LOGICAL_RAM_DEPTH = 8, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a5 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 3, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 7, + PORT_A_LOGICAL_RAM_DEPTH = 8, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 3, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 7, + PORT_B_LOGICAL_RAM_DEPTH = 8, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a6 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 3, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 7, + PORT_A_LOGICAL_RAM_DEPTH = 8, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 3, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 7, + PORT_B_LOGICAL_RAM_DEPTH = 8, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a7 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 3, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 7, + PORT_A_LOGICAL_RAM_DEPTH = 8, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 3, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 7, + PORT_B_LOGICAL_RAM_DEPTH = 8, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a8 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 3, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 8, + PORT_A_LAST_ADDRESS = 7, + PORT_A_LOGICAL_RAM_DEPTH = 8, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 3, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 8, + PORT_B_LAST_ADDRESS = 7, + PORT_B_LOGICAL_RAM_DEPTH = 8, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a9 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 3, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 9, + PORT_A_LAST_ADDRESS = 7, + PORT_A_LOGICAL_RAM_DEPTH = 8, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 3, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 9, + PORT_B_LAST_ADDRESS = 7, + PORT_B_LOGICAL_RAM_DEPTH = 8, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a10 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 3, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 10, + PORT_A_LAST_ADDRESS = 7, + PORT_A_LOGICAL_RAM_DEPTH = 8, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 3, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 10, + PORT_B_LAST_ADDRESS = 7, + PORT_B_LOGICAL_RAM_DEPTH = 8, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a11 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 3, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 11, + PORT_A_LAST_ADDRESS = 7, + PORT_A_LOGICAL_RAM_DEPTH = 8, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 3, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 11, + PORT_B_LAST_ADDRESS = 7, + PORT_B_LOGICAL_RAM_DEPTH = 8, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a12 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 3, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 12, + PORT_A_LAST_ADDRESS = 7, + PORT_A_LOGICAL_RAM_DEPTH = 8, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 3, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 12, + PORT_B_LAST_ADDRESS = 7, + PORT_B_LOGICAL_RAM_DEPTH = 8, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a13 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 3, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 13, + PORT_A_LAST_ADDRESS = 7, + PORT_A_LOGICAL_RAM_DEPTH = 8, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 3, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 13, + PORT_B_LAST_ADDRESS = 7, + PORT_B_LOGICAL_RAM_DEPTH = 8, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a14 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 3, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 14, + PORT_A_LAST_ADDRESS = 7, + PORT_A_LOGICAL_RAM_DEPTH = 8, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 3, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 14, + PORT_B_LAST_ADDRESS = 7, + PORT_B_LOGICAL_RAM_DEPTH = 8, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a15 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 3, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 15, + PORT_A_LAST_ADDRESS = 7, + PORT_A_LOGICAL_RAM_DEPTH = 8, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 3, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 15, + PORT_B_LAST_ADDRESS = 7, + PORT_B_LOGICAL_RAM_DEPTH = 8, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a16 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 3, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 16, + PORT_A_LAST_ADDRESS = 7, + PORT_A_LOGICAL_RAM_DEPTH = 8, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 3, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 16, + PORT_B_LAST_ADDRESS = 7, + PORT_B_LOGICAL_RAM_DEPTH = 8, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a17 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 3, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 17, + PORT_A_LAST_ADDRESS = 7, + PORT_A_LOGICAL_RAM_DEPTH = 8, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 3, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 17, + PORT_B_LAST_ADDRESS = 7, + PORT_B_LOGICAL_RAM_DEPTH = 8, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a18 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 3, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 18, + PORT_A_LAST_ADDRESS = 7, + PORT_A_LOGICAL_RAM_DEPTH = 8, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 3, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 18, + PORT_B_LAST_ADDRESS = 7, + PORT_B_LOGICAL_RAM_DEPTH = 8, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a19 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 3, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 19, + PORT_A_LAST_ADDRESS = 7, + PORT_A_LOGICAL_RAM_DEPTH = 8, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 3, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 19, + PORT_B_LAST_ADDRESS = 7, + PORT_B_LOGICAL_RAM_DEPTH = 8, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a20 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 3, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 20, + PORT_A_LAST_ADDRESS = 7, + PORT_A_LOGICAL_RAM_DEPTH = 8, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 3, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 20, + PORT_B_LAST_ADDRESS = 7, + PORT_B_LOGICAL_RAM_DEPTH = 8, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a21 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 3, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 21, + PORT_A_LAST_ADDRESS = 7, + PORT_A_LOGICAL_RAM_DEPTH = 8, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 3, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 21, + PORT_B_LAST_ADDRESS = 7, + PORT_B_LOGICAL_RAM_DEPTH = 8, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a22 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 3, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 22, + PORT_A_LAST_ADDRESS = 7, + PORT_A_LOGICAL_RAM_DEPTH = 8, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 3, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 22, + PORT_B_LAST_ADDRESS = 7, + PORT_B_LOGICAL_RAM_DEPTH = 8, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a23 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 3, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 23, + PORT_A_LAST_ADDRESS = 7, + PORT_A_LOGICAL_RAM_DEPTH = 8, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 3, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 23, + PORT_B_LAST_ADDRESS = 7, + PORT_B_LOGICAL_RAM_DEPTH = 8, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a24 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 3, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 24, + PORT_A_LAST_ADDRESS = 7, + PORT_A_LOGICAL_RAM_DEPTH = 8, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 3, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 24, + PORT_B_LAST_ADDRESS = 7, + PORT_B_LOGICAL_RAM_DEPTH = 8, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a25 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 3, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 25, + PORT_A_LAST_ADDRESS = 7, + PORT_A_LOGICAL_RAM_DEPTH = 8, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 3, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 25, + PORT_B_LAST_ADDRESS = 7, + PORT_B_LOGICAL_RAM_DEPTH = 8, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a26 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 3, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 26, + PORT_A_LAST_ADDRESS = 7, + PORT_A_LOGICAL_RAM_DEPTH = 8, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 3, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 26, + PORT_B_LAST_ADDRESS = 7, + PORT_B_LOGICAL_RAM_DEPTH = 8, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a27 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 3, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 27, + PORT_A_LAST_ADDRESS = 7, + PORT_A_LOGICAL_RAM_DEPTH = 8, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 3, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 27, + PORT_B_LAST_ADDRESS = 7, + PORT_B_LOGICAL_RAM_DEPTH = 8, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a28 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 3, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 28, + PORT_A_LAST_ADDRESS = 7, + PORT_A_LOGICAL_RAM_DEPTH = 8, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 3, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 28, + PORT_B_LAST_ADDRESS = 7, + PORT_B_LOGICAL_RAM_DEPTH = 8, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a29 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 3, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 29, + PORT_A_LAST_ADDRESS = 7, + PORT_A_LOGICAL_RAM_DEPTH = 8, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 3, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 29, + PORT_B_LAST_ADDRESS = 7, + PORT_B_LOGICAL_RAM_DEPTH = 8, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a30 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 3, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 30, + PORT_A_LAST_ADDRESS = 7, + PORT_A_LOGICAL_RAM_DEPTH = 8, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 3, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 30, + PORT_B_LAST_ADDRESS = 7, + PORT_B_LOGICAL_RAM_DEPTH = 8, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a31 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "none", + CLK0_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "old", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 3, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 31, + PORT_A_LAST_ADDRESS = 7, + PORT_A_LOGICAL_RAM_DEPTH = 8, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock0", + PORT_B_ADDRESS_WIDTH = 3, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 31, + PORT_B_LAST_ADDRESS = 7, + PORT_B_LOGICAL_RAM_DEPTH = 8, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock0", + RAM_BLOCK_TYPE = "AUTO" + ); + address_a_wire[2..0] : WIRE; + address_b_wire[2..0] : WIRE; + +BEGIN + ram_block1a[31..0].clk0 = clock0; + ram_block1a[31..0].portaaddr[] = ( address_a_wire[2..0]); + ram_block1a[0].portadatain[] = ( data_a[0..0]); + ram_block1a[1].portadatain[] = ( data_a[1..1]); + ram_block1a[2].portadatain[] = ( data_a[2..2]); + ram_block1a[3].portadatain[] = ( data_a[3..3]); + ram_block1a[4].portadatain[] = ( data_a[4..4]); + ram_block1a[5].portadatain[] = ( data_a[5..5]); + ram_block1a[6].portadatain[] = ( data_a[6..6]); + ram_block1a[7].portadatain[] = ( data_a[7..7]); + ram_block1a[8].portadatain[] = ( data_a[8..8]); + ram_block1a[9].portadatain[] = ( data_a[9..9]); + ram_block1a[10].portadatain[] = ( data_a[10..10]); + ram_block1a[11].portadatain[] = ( data_a[11..11]); + ram_block1a[12].portadatain[] = ( data_a[12..12]); + ram_block1a[13].portadatain[] = ( data_a[13..13]); + ram_block1a[14].portadatain[] = ( data_a[14..14]); + ram_block1a[15].portadatain[] = ( data_a[15..15]); + ram_block1a[16].portadatain[] = ( data_a[16..16]); + ram_block1a[17].portadatain[] = ( data_a[17..17]); + ram_block1a[18].portadatain[] = ( data_a[18..18]); + ram_block1a[19].portadatain[] = ( data_a[19..19]); + ram_block1a[20].portadatain[] = ( data_a[20..20]); + ram_block1a[21].portadatain[] = ( data_a[21..21]); + ram_block1a[22].portadatain[] = ( data_a[22..22]); + ram_block1a[23].portadatain[] = ( data_a[23..23]); + ram_block1a[24].portadatain[] = ( data_a[24..24]); + ram_block1a[25].portadatain[] = ( data_a[25..25]); + ram_block1a[26].portadatain[] = ( data_a[26..26]); + ram_block1a[27].portadatain[] = ( data_a[27..27]); + ram_block1a[28].portadatain[] = ( data_a[28..28]); + ram_block1a[29].portadatain[] = ( data_a[29..29]); + ram_block1a[30].portadatain[] = ( data_a[30..30]); + ram_block1a[31].portadatain[] = ( data_a[31..31]); + ram_block1a[31..0].portawe = wren_a; + ram_block1a[31..0].portbaddr[] = ( address_b_wire[2..0]); + ram_block1a[31..0].portbre = rden_b; + address_a_wire[] = address_a[]; + address_b_wire[] = address_b[]; + q_b[] = ( ram_block1a[31..0].portbdataout[0..0]); +END; +--VALID FILE diff --git a/MCTEST/DE0-nano-HD/db/altsyncram_sjd1.tdf b/MCTEST/DE0-nano-HD/db/altsyncram_sjd1.tdf new file mode 100644 index 00000000..a9f9b4ae --- /dev/null +++ b/MCTEST/DE0-nano-HD/db/altsyncram_sjd1.tdf @@ -0,0 +1,1049 @@ +--altsyncram ADDRESS_REG_B="CLOCK0" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" LOW_POWER_MODE="AUTO" MAXIMUM_DEPTH=0 NUMWORDS_A=2048 NUMWORDS_B=2048 OPERATION_MODE="DUAL_PORT" OUTDATA_REG_B="UNREGISTERED" RAM_BLOCK_TYPE="AUTO" RDCONTROL_REG_B="CLOCK0" READ_DURING_WRITE_MODE_MIXED_PORTS="DONT_CARE" WIDTH_A=32 WIDTH_B=32 WIDTHAD_A=11 WIDTHAD_B=11 address_a address_b clock0 data_a q_b rden_b wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 +--VERSION_BEGIN 12.1SP1 cbx_altsyncram 2013:01:31:18:05:07:SJ cbx_cycloneii 2013:01:31:18:05:07:SJ cbx_lpm_add_sub 2013:01:31:18:05:07:SJ cbx_lpm_compare 2013:01:31:18:05:07:SJ cbx_lpm_decode 2013:01:31:18:05:07:SJ cbx_lpm_mux 2013:01:31:18:05:07:SJ cbx_mgl 2013:01:31:18:08:27:SJ cbx_stratix 2013:01:31:18:05:07:SJ cbx_stratixii 2013:01:31:18:05:07:SJ cbx_stratixiii 2013:01:31:18:05:07:SJ cbx_stratixv 2013:01:31:18:05:07:SJ cbx_util_mgl 2013:01:31:18:05:07:SJ VERSION_END + + +-- Copyright (C) 1991-2012 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) +WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS) +RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); + +--synthesis_resources = M9K 8 reg 1 +OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; + +SUBDESIGN altsyncram_sjd1 +( + address_a[10..0] : input; + address_b[10..0] : input; + clock0 : input; + data_a[31..0] : input; + q_b[31..0] : output; + rden_b : input; + wren_a : input; +) +VARIABLE + rden_b_store : dffe; + ram_block1a0 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 2047, + PORT_A_LOGICAL_RAM_DEPTH = 2048, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 11, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 0, + PORT_B_LAST_ADDRESS = 2047, + PORT_B_LOGICAL_RAM_DEPTH = 2048, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a1 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 2047, + PORT_A_LOGICAL_RAM_DEPTH = 2048, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 11, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 1, + PORT_B_LAST_ADDRESS = 2047, + PORT_B_LOGICAL_RAM_DEPTH = 2048, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a2 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 2047, + PORT_A_LOGICAL_RAM_DEPTH = 2048, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 11, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 2, + PORT_B_LAST_ADDRESS = 2047, + PORT_B_LOGICAL_RAM_DEPTH = 2048, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a3 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 2047, + PORT_A_LOGICAL_RAM_DEPTH = 2048, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 11, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 3, + PORT_B_LAST_ADDRESS = 2047, + PORT_B_LOGICAL_RAM_DEPTH = 2048, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a4 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 2047, + PORT_A_LOGICAL_RAM_DEPTH = 2048, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 11, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 4, + PORT_B_LAST_ADDRESS = 2047, + PORT_B_LOGICAL_RAM_DEPTH = 2048, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a5 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 2047, + PORT_A_LOGICAL_RAM_DEPTH = 2048, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 11, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 5, + PORT_B_LAST_ADDRESS = 2047, + PORT_B_LOGICAL_RAM_DEPTH = 2048, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a6 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 2047, + PORT_A_LOGICAL_RAM_DEPTH = 2048, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 11, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 6, + PORT_B_LAST_ADDRESS = 2047, + PORT_B_LOGICAL_RAM_DEPTH = 2048, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a7 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 2047, + PORT_A_LOGICAL_RAM_DEPTH = 2048, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 11, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 7, + PORT_B_LAST_ADDRESS = 2047, + PORT_B_LOGICAL_RAM_DEPTH = 2048, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a8 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 8, + PORT_A_LAST_ADDRESS = 2047, + PORT_A_LOGICAL_RAM_DEPTH = 2048, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 11, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 8, + PORT_B_LAST_ADDRESS = 2047, + PORT_B_LOGICAL_RAM_DEPTH = 2048, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a9 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 9, + PORT_A_LAST_ADDRESS = 2047, + PORT_A_LOGICAL_RAM_DEPTH = 2048, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 11, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 9, + PORT_B_LAST_ADDRESS = 2047, + PORT_B_LOGICAL_RAM_DEPTH = 2048, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a10 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 10, + PORT_A_LAST_ADDRESS = 2047, + PORT_A_LOGICAL_RAM_DEPTH = 2048, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 11, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 10, + PORT_B_LAST_ADDRESS = 2047, + PORT_B_LOGICAL_RAM_DEPTH = 2048, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a11 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 11, + PORT_A_LAST_ADDRESS = 2047, + PORT_A_LOGICAL_RAM_DEPTH = 2048, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 11, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 11, + PORT_B_LAST_ADDRESS = 2047, + PORT_B_LOGICAL_RAM_DEPTH = 2048, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a12 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 12, + PORT_A_LAST_ADDRESS = 2047, + PORT_A_LOGICAL_RAM_DEPTH = 2048, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 11, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 12, + PORT_B_LAST_ADDRESS = 2047, + PORT_B_LOGICAL_RAM_DEPTH = 2048, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a13 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 13, + PORT_A_LAST_ADDRESS = 2047, + PORT_A_LOGICAL_RAM_DEPTH = 2048, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 11, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 13, + PORT_B_LAST_ADDRESS = 2047, + PORT_B_LOGICAL_RAM_DEPTH = 2048, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a14 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 14, + PORT_A_LAST_ADDRESS = 2047, + PORT_A_LOGICAL_RAM_DEPTH = 2048, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 11, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 14, + PORT_B_LAST_ADDRESS = 2047, + PORT_B_LOGICAL_RAM_DEPTH = 2048, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a15 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 15, + PORT_A_LAST_ADDRESS = 2047, + PORT_A_LOGICAL_RAM_DEPTH = 2048, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 11, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 15, + PORT_B_LAST_ADDRESS = 2047, + PORT_B_LOGICAL_RAM_DEPTH = 2048, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a16 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 16, + PORT_A_LAST_ADDRESS = 2047, + PORT_A_LOGICAL_RAM_DEPTH = 2048, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 11, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 16, + PORT_B_LAST_ADDRESS = 2047, + PORT_B_LOGICAL_RAM_DEPTH = 2048, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a17 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 17, + PORT_A_LAST_ADDRESS = 2047, + PORT_A_LOGICAL_RAM_DEPTH = 2048, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 11, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 17, + PORT_B_LAST_ADDRESS = 2047, + PORT_B_LOGICAL_RAM_DEPTH = 2048, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a18 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 18, + PORT_A_LAST_ADDRESS = 2047, + PORT_A_LOGICAL_RAM_DEPTH = 2048, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 11, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 18, + PORT_B_LAST_ADDRESS = 2047, + PORT_B_LOGICAL_RAM_DEPTH = 2048, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a19 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 19, + PORT_A_LAST_ADDRESS = 2047, + PORT_A_LOGICAL_RAM_DEPTH = 2048, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 11, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 19, + PORT_B_LAST_ADDRESS = 2047, + PORT_B_LOGICAL_RAM_DEPTH = 2048, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a20 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 20, + PORT_A_LAST_ADDRESS = 2047, + PORT_A_LOGICAL_RAM_DEPTH = 2048, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 11, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 20, + PORT_B_LAST_ADDRESS = 2047, + PORT_B_LOGICAL_RAM_DEPTH = 2048, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a21 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 21, + PORT_A_LAST_ADDRESS = 2047, + PORT_A_LOGICAL_RAM_DEPTH = 2048, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 11, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 21, + PORT_B_LAST_ADDRESS = 2047, + PORT_B_LOGICAL_RAM_DEPTH = 2048, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a22 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 22, + PORT_A_LAST_ADDRESS = 2047, + PORT_A_LOGICAL_RAM_DEPTH = 2048, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 11, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 22, + PORT_B_LAST_ADDRESS = 2047, + PORT_B_LOGICAL_RAM_DEPTH = 2048, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a23 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 23, + PORT_A_LAST_ADDRESS = 2047, + PORT_A_LOGICAL_RAM_DEPTH = 2048, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 11, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 23, + PORT_B_LAST_ADDRESS = 2047, + PORT_B_LOGICAL_RAM_DEPTH = 2048, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a24 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 24, + PORT_A_LAST_ADDRESS = 2047, + PORT_A_LOGICAL_RAM_DEPTH = 2048, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 11, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 24, + PORT_B_LAST_ADDRESS = 2047, + PORT_B_LOGICAL_RAM_DEPTH = 2048, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a25 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 25, + PORT_A_LAST_ADDRESS = 2047, + PORT_A_LOGICAL_RAM_DEPTH = 2048, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 11, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 25, + PORT_B_LAST_ADDRESS = 2047, + PORT_B_LOGICAL_RAM_DEPTH = 2048, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a26 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 26, + PORT_A_LAST_ADDRESS = 2047, + PORT_A_LOGICAL_RAM_DEPTH = 2048, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 11, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 26, + PORT_B_LAST_ADDRESS = 2047, + PORT_B_LOGICAL_RAM_DEPTH = 2048, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a27 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 27, + PORT_A_LAST_ADDRESS = 2047, + PORT_A_LOGICAL_RAM_DEPTH = 2048, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 11, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 27, + PORT_B_LAST_ADDRESS = 2047, + PORT_B_LOGICAL_RAM_DEPTH = 2048, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a28 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 28, + PORT_A_LAST_ADDRESS = 2047, + PORT_A_LOGICAL_RAM_DEPTH = 2048, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 11, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 28, + PORT_B_LAST_ADDRESS = 2047, + PORT_B_LOGICAL_RAM_DEPTH = 2048, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a29 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 29, + PORT_A_LAST_ADDRESS = 2047, + PORT_A_LOGICAL_RAM_DEPTH = 2048, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 11, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 29, + PORT_B_LAST_ADDRESS = 2047, + PORT_B_LOGICAL_RAM_DEPTH = 2048, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a30 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 30, + PORT_A_LAST_ADDRESS = 2047, + PORT_A_LOGICAL_RAM_DEPTH = 2048, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 11, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 30, + PORT_B_LAST_ADDRESS = 2047, + PORT_B_LOGICAL_RAM_DEPTH = 2048, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + ram_block1a31 : cycloneive_ram_block + WITH ( + CLK0_CORE_CLOCK_ENABLE = "ena0", + CLK0_INPUT_CLOCK_ENABLE = "none", + CLK1_CORE_CLOCK_ENABLE = "ena1", + CLK1_INPUT_CLOCK_ENABLE = "none", + CONNECTIVITY_CHECKING = "OFF", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + MIXED_PORT_FEED_THROUGH_MODE = "dont_care", + OPERATION_MODE = "dual_port", + PORT_A_ADDRESS_WIDTH = 11, + PORT_A_DATA_WIDTH = 1, + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 31, + PORT_A_LAST_ADDRESS = 2047, + PORT_A_LOGICAL_RAM_DEPTH = 2048, + PORT_A_LOGICAL_RAM_WIDTH = 32, + PORT_B_ADDRESS_CLEAR = "none", + PORT_B_ADDRESS_CLOCK = "clock1", + PORT_B_ADDRESS_WIDTH = 11, + PORT_B_DATA_OUT_CLEAR = "none", + PORT_B_DATA_WIDTH = 1, + PORT_B_FIRST_ADDRESS = 0, + PORT_B_FIRST_BIT_NUMBER = 31, + PORT_B_LAST_ADDRESS = 2047, + PORT_B_LOGICAL_RAM_DEPTH = 2048, + PORT_B_LOGICAL_RAM_WIDTH = 32, + PORT_B_READ_ENABLE_CLOCK = "clock1", + RAM_BLOCK_TYPE = "AUTO" + ); + address_a_wire[10..0] : WIRE; + address_b_wire[10..0] : WIRE; + +BEGIN + rden_b_store.clk = clock0; + rden_b_store.d = rden_b; + ram_block1a[31..0].clk0 = clock0; + ram_block1a[31..0].clk1 = clock0; + ram_block1a[31..0].ena0 = wren_a; + ram_block1a[31..0].ena1 = (rden_b_store.q # rden_b); + ram_block1a[31..0].portaaddr[] = ( address_a_wire[10..0]); + ram_block1a[0].portadatain[] = ( data_a[0..0]); + ram_block1a[1].portadatain[] = ( data_a[1..1]); + ram_block1a[2].portadatain[] = ( data_a[2..2]); + ram_block1a[3].portadatain[] = ( data_a[3..3]); + ram_block1a[4].portadatain[] = ( data_a[4..4]); + ram_block1a[5].portadatain[] = ( data_a[5..5]); + ram_block1a[6].portadatain[] = ( data_a[6..6]); + ram_block1a[7].portadatain[] = ( data_a[7..7]); + ram_block1a[8].portadatain[] = ( data_a[8..8]); + ram_block1a[9].portadatain[] = ( data_a[9..9]); + ram_block1a[10].portadatain[] = ( data_a[10..10]); + ram_block1a[11].portadatain[] = ( data_a[11..11]); + ram_block1a[12].portadatain[] = ( data_a[12..12]); + ram_block1a[13].portadatain[] = ( data_a[13..13]); + ram_block1a[14].portadatain[] = ( data_a[14..14]); + ram_block1a[15].portadatain[] = ( data_a[15..15]); + ram_block1a[16].portadatain[] = ( data_a[16..16]); + ram_block1a[17].portadatain[] = ( data_a[17..17]); + ram_block1a[18].portadatain[] = ( data_a[18..18]); + ram_block1a[19].portadatain[] = ( data_a[19..19]); + ram_block1a[20].portadatain[] = ( data_a[20..20]); + ram_block1a[21].portadatain[] = ( data_a[21..21]); + ram_block1a[22].portadatain[] = ( data_a[22..22]); + ram_block1a[23].portadatain[] = ( data_a[23..23]); + ram_block1a[24].portadatain[] = ( data_a[24..24]); + ram_block1a[25].portadatain[] = ( data_a[25..25]); + ram_block1a[26].portadatain[] = ( data_a[26..26]); + ram_block1a[27].portadatain[] = ( data_a[27..27]); + ram_block1a[28].portadatain[] = ( data_a[28..28]); + ram_block1a[29].portadatain[] = ( data_a[29..29]); + ram_block1a[30].portadatain[] = ( data_a[30..30]); + ram_block1a[31].portadatain[] = ( data_a[31..31]); + ram_block1a[31..0].portawe = wren_a; + ram_block1a[31..0].portbaddr[] = ( address_b_wire[10..0]); + ram_block1a[31..0].portbre = rden_b; + address_a_wire[] = address_a[]; + address_b_wire[] = address_b[]; + q_b[] = ( ram_block1a[31..0].portbdataout[0..0]); +END; +--VALID FILE diff --git a/MCTEST/DE0-nano-HD/db/cmpr_ks8.tdf b/MCTEST/DE0-nano-HD/db/cmpr_ks8.tdf new file mode 100644 index 00000000..13f2c55e --- /dev/null +++ b/MCTEST/DE0-nano-HD/db/cmpr_ks8.tdf @@ -0,0 +1,41 @@ +--lpm_compare DEVICE_FAMILY="Cyclone IV E" LPM_WIDTH=7 ONE_INPUT_IS_CONSTANT="YES" aeb dataa datab +--VERSION_BEGIN 12.1SP1 cbx_cycloneii 2013:01:31:18:05:07:SJ cbx_lpm_add_sub 2013:01:31:18:05:07:SJ cbx_lpm_compare 2013:01:31:18:05:07:SJ cbx_mgl 2013:01:31:18:08:27:SJ cbx_stratix 2013:01:31:18:05:07:SJ cbx_stratixii 2013:01:31:18:05:07:SJ VERSION_END + + +-- Copyright (C) 1991-2012 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + + +--synthesis_resources = +SUBDESIGN cmpr_ks8 +( + aeb : output; + dataa[6..0] : input; + datab[6..0] : input; +) +VARIABLE + aeb_result_wire[0..0] : WIRE; + aneb_result_wire[0..0] : WIRE; + data_wire[17..0] : WIRE; + eq_wire : WIRE; + +BEGIN + aeb = eq_wire; + aeb_result_wire[] = (! aneb_result_wire[]); + aneb_result_wire[] = (((data_wire[0..0] # data_wire[1..1]) # data_wire[2..2]) # data_wire[3..3]); + data_wire[] = ( datab[6..6], dataa[6..6], datab[5..5], dataa[5..5], datab[4..4], dataa[4..4], datab[3..3], dataa[3..3], datab[2..2], dataa[2..2], datab[1..1], dataa[1..1], datab[0..0], dataa[0..0], (data_wire[16..16] $ data_wire[17..17]), ((data_wire[12..12] $ data_wire[13..13]) # (data_wire[14..14] $ data_wire[15..15])), ((data_wire[8..8] $ data_wire[9..9]) # (data_wire[10..10] $ data_wire[11..11])), ((data_wire[4..4] $ data_wire[5..5]) # (data_wire[6..6] $ data_wire[7..7]))); + eq_wire = aeb_result_wire[]; +END; +--VALID FILE diff --git a/MCTEST/DE0-nano-HD/db/cntr_0ab.tdf b/MCTEST/DE0-nano-HD/db/cntr_0ab.tdf new file mode 100644 index 00000000..cf8e0c99 --- /dev/null +++ b/MCTEST/DE0-nano-HD/db/cntr_0ab.tdf @@ -0,0 +1,101 @@ +--lpm_counter DEVICE_FAMILY="Cyclone IV E" lpm_direction="UP" lpm_port_updown="PORT_UNUSED" lpm_width=7 clock cnt_en q sclr +--VERSION_BEGIN 12.1SP1 cbx_cycloneii 2013:01:31:18:05:07:SJ cbx_lpm_add_sub 2013:01:31:18:05:07:SJ cbx_lpm_compare 2013:01:31:18:05:07:SJ cbx_lpm_counter 2013:01:31:18:05:07:SJ cbx_lpm_decode 2013:01:31:18:05:07:SJ cbx_mgl 2013:01:31:18:08:27:SJ cbx_stratix 2013:01:31:18:05:07:SJ cbx_stratixii 2013:01:31:18:05:07:SJ VERSION_END + + +-- Copyright (C) 1991-2012 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +FUNCTION cycloneive_lcell_comb (cin, dataa, datab, datac, datad) +WITH ( DONT_TOUCH, LUT_MASK, SUM_LUTC_INPUT) +RETURNS ( combout, cout); + +--synthesis_resources = lut 7 reg 7 +SUBDESIGN cntr_0ab +( + clock : input; + cnt_en : input; + q[6..0] : output; + sclr : input; +) +VARIABLE + counter_comb_bita0 : cycloneive_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_comb_bita1 : cycloneive_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_comb_bita2 : cycloneive_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_comb_bita3 : cycloneive_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_comb_bita4 : cycloneive_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_comb_bita5 : cycloneive_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_comb_bita6 : cycloneive_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_reg_bit[6..0] : dffeas; + aclr_actual : WIRE; + clk_en : NODE; + data[6..0] : NODE; + external_cin : WIRE; + s_val[6..0] : WIRE; + safe_q[6..0] : WIRE; + sload : NODE; + sset : NODE; + updown_dir : WIRE; + +BEGIN + counter_comb_bita[6..0].cin = ( counter_comb_bita[5..0].cout, external_cin); + counter_comb_bita[6..0].dataa = ( counter_reg_bit[6..0].q); + counter_comb_bita[6..0].datab = ( updown_dir, updown_dir, updown_dir, updown_dir, updown_dir, updown_dir, updown_dir); + counter_comb_bita[6..0].datad = ( B"1", B"1", B"1", B"1", B"1", B"1", B"1"); + counter_reg_bit[].asdata = ((! sclr) & ((sset & s_val[]) # ((! sset) & data[]))); + counter_reg_bit[].clk = clock; + counter_reg_bit[].clrn = (! aclr_actual); + counter_reg_bit[].d = ( counter_comb_bita[6..0].combout); + counter_reg_bit[].ena = (clk_en & (((sclr # sset) # sload) # cnt_en)); + counter_reg_bit[].sload = ((sclr # sset) # sload); + aclr_actual = B"0"; + clk_en = VCC; + data[] = GND; + external_cin = B"1"; + q[] = safe_q[]; + s_val[] = B"1111111"; + safe_q[] = counter_reg_bit[].q; + sload = GND; + sset = GND; + updown_dir = B"1"; +END; +--VALID FILE diff --git a/MCTEST/DE0-nano-HD/db/cntr_1ob.tdf b/MCTEST/DE0-nano-HD/db/cntr_1ob.tdf new file mode 100644 index 00000000..6b3f0c33 --- /dev/null +++ b/MCTEST/DE0-nano-HD/db/cntr_1ob.tdf @@ -0,0 +1,97 @@ +--lpm_counter DEVICE_FAMILY="Cyclone IV E" lpm_direction="UP" lpm_port_updown="PORT_UNUSED" lpm_width=6 aclr clock cnt_en q sclr +--VERSION_BEGIN 12.1SP1 cbx_cycloneii 2013:01:31:18:05:07:SJ cbx_lpm_add_sub 2013:01:31:18:05:07:SJ cbx_lpm_compare 2013:01:31:18:05:07:SJ cbx_lpm_counter 2013:01:31:18:05:07:SJ cbx_lpm_decode 2013:01:31:18:05:07:SJ cbx_mgl 2013:01:31:18:08:27:SJ cbx_stratix 2013:01:31:18:05:07:SJ cbx_stratixii 2013:01:31:18:05:07:SJ VERSION_END + + +-- Copyright (C) 1991-2012 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +FUNCTION cycloneive_lcell_comb (cin, dataa, datab, datac, datad) +WITH ( DONT_TOUCH, LUT_MASK, SUM_LUTC_INPUT) +RETURNS ( combout, cout); + +--synthesis_resources = lut 6 reg 6 +SUBDESIGN cntr_1ob +( + aclr : input; + clock : input; + cnt_en : input; + q[5..0] : output; + sclr : input; +) +VARIABLE + counter_comb_bita0 : cycloneive_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_comb_bita1 : cycloneive_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_comb_bita2 : cycloneive_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_comb_bita3 : cycloneive_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_comb_bita4 : cycloneive_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_comb_bita5 : cycloneive_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_reg_bit[5..0] : dffeas; + aclr_actual : WIRE; + clk_en : NODE; + data[5..0] : NODE; + external_cin : WIRE; + s_val[5..0] : WIRE; + safe_q[5..0] : WIRE; + sload : NODE; + sset : NODE; + updown_dir : WIRE; + +BEGIN + counter_comb_bita[5..0].cin = ( counter_comb_bita[4..0].cout, external_cin); + counter_comb_bita[5..0].dataa = ( counter_reg_bit[5..0].q); + counter_comb_bita[5..0].datab = ( updown_dir, updown_dir, updown_dir, updown_dir, updown_dir, updown_dir); + counter_comb_bita[5..0].datad = ( B"1", B"1", B"1", B"1", B"1", B"1"); + counter_reg_bit[].asdata = ((! sclr) & ((sset & s_val[]) # ((! sset) & data[]))); + counter_reg_bit[].clk = clock; + counter_reg_bit[].clrn = (! aclr_actual); + counter_reg_bit[].d = ( counter_comb_bita[5..0].combout); + counter_reg_bit[].ena = (clk_en & (((sclr # sset) # sload) # cnt_en)); + counter_reg_bit[].sload = ((sclr # sset) # sload); + aclr_actual = aclr; + clk_en = VCC; + data[] = GND; + external_cin = B"1"; + q[] = safe_q[]; + s_val[] = B"111111"; + safe_q[] = counter_reg_bit[].q; + sload = GND; + sset = GND; + updown_dir = B"1"; +END; +--VALID FILE diff --git a/MCTEST/DE0-nano-HD/db/cntr_ca7.tdf b/MCTEST/DE0-nano-HD/db/cntr_ca7.tdf new file mode 100644 index 00000000..e281e072 --- /dev/null +++ b/MCTEST/DE0-nano-HD/db/cntr_ca7.tdf @@ -0,0 +1,102 @@ +--lpm_counter DEVICE_FAMILY="Cyclone IV E" lpm_width=7 clock cnt_en q sclr updown +--VERSION_BEGIN 12.1SP1 cbx_cycloneii 2013:01:31:18:05:07:SJ cbx_lpm_add_sub 2013:01:31:18:05:07:SJ cbx_lpm_compare 2013:01:31:18:05:07:SJ cbx_lpm_counter 2013:01:31:18:05:07:SJ cbx_lpm_decode 2013:01:31:18:05:07:SJ cbx_mgl 2013:01:31:18:08:27:SJ cbx_stratix 2013:01:31:18:05:07:SJ cbx_stratixii 2013:01:31:18:05:07:SJ VERSION_END + + +-- Copyright (C) 1991-2012 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +FUNCTION cycloneive_lcell_comb (cin, dataa, datab, datac, datad) +WITH ( DONT_TOUCH, LUT_MASK, SUM_LUTC_INPUT) +RETURNS ( combout, cout); + +--synthesis_resources = lut 7 reg 7 +SUBDESIGN cntr_ca7 +( + clock : input; + cnt_en : input; + q[6..0] : output; + sclr : input; + updown : input; +) +VARIABLE + counter_comb_bita0 : cycloneive_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_comb_bita1 : cycloneive_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_comb_bita2 : cycloneive_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_comb_bita3 : cycloneive_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_comb_bita4 : cycloneive_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_comb_bita5 : cycloneive_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_comb_bita6 : cycloneive_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_reg_bit[6..0] : dffeas; + aclr_actual : WIRE; + clk_en : NODE; + data[6..0] : NODE; + external_cin : WIRE; + s_val[6..0] : WIRE; + safe_q[6..0] : WIRE; + sload : NODE; + sset : NODE; + updown_dir : WIRE; + +BEGIN + counter_comb_bita[6..0].cin = ( counter_comb_bita[5..0].cout, external_cin); + counter_comb_bita[6..0].dataa = ( counter_reg_bit[6..0].q); + counter_comb_bita[6..0].datab = ( updown_dir, updown_dir, updown_dir, updown_dir, updown_dir, updown_dir, updown_dir); + counter_comb_bita[6..0].datad = ( B"1", B"1", B"1", B"1", B"1", B"1", B"1"); + counter_reg_bit[].asdata = ((! sclr) & ((sset & s_val[]) # ((! sset) & data[]))); + counter_reg_bit[].clk = clock; + counter_reg_bit[].clrn = (! aclr_actual); + counter_reg_bit[].d = ( counter_comb_bita[6..0].combout); + counter_reg_bit[].ena = (clk_en & (((sclr # sset) # sload) # cnt_en)); + counter_reg_bit[].sload = ((sclr # sset) # sload); + aclr_actual = B"0"; + clk_en = VCC; + data[] = GND; + external_cin = B"1"; + q[] = safe_q[]; + s_val[] = B"1111111"; + safe_q[] = counter_reg_bit[].q; + sload = GND; + sset = GND; + updown_dir = updown; +END; +--VALID FILE diff --git a/MCTEST/DE0-nano-HD/db/cntr_do7.tdf b/MCTEST/DE0-nano-HD/db/cntr_do7.tdf new file mode 100644 index 00000000..ad602ba9 --- /dev/null +++ b/MCTEST/DE0-nano-HD/db/cntr_do7.tdf @@ -0,0 +1,98 @@ +--lpm_counter DEVICE_FAMILY="Cyclone IV E" lpm_width=6 aclr clock cnt_en q sclr updown +--VERSION_BEGIN 12.1SP1 cbx_cycloneii 2013:01:31:18:05:07:SJ cbx_lpm_add_sub 2013:01:31:18:05:07:SJ cbx_lpm_compare 2013:01:31:18:05:07:SJ cbx_lpm_counter 2013:01:31:18:05:07:SJ cbx_lpm_decode 2013:01:31:18:05:07:SJ cbx_mgl 2013:01:31:18:08:27:SJ cbx_stratix 2013:01:31:18:05:07:SJ cbx_stratixii 2013:01:31:18:05:07:SJ VERSION_END + + +-- Copyright (C) 1991-2012 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +FUNCTION cycloneive_lcell_comb (cin, dataa, datab, datac, datad) +WITH ( DONT_TOUCH, LUT_MASK, SUM_LUTC_INPUT) +RETURNS ( combout, cout); + +--synthesis_resources = lut 6 reg 6 +SUBDESIGN cntr_do7 +( + aclr : input; + clock : input; + cnt_en : input; + q[5..0] : output; + sclr : input; + updown : input; +) +VARIABLE + counter_comb_bita0 : cycloneive_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_comb_bita1 : cycloneive_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_comb_bita2 : cycloneive_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_comb_bita3 : cycloneive_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_comb_bita4 : cycloneive_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_comb_bita5 : cycloneive_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_reg_bit[5..0] : dffeas; + aclr_actual : WIRE; + clk_en : NODE; + data[5..0] : NODE; + external_cin : WIRE; + s_val[5..0] : WIRE; + safe_q[5..0] : WIRE; + sload : NODE; + sset : NODE; + updown_dir : WIRE; + +BEGIN + counter_comb_bita[5..0].cin = ( counter_comb_bita[4..0].cout, external_cin); + counter_comb_bita[5..0].dataa = ( counter_reg_bit[5..0].q); + counter_comb_bita[5..0].datab = ( updown_dir, updown_dir, updown_dir, updown_dir, updown_dir, updown_dir); + counter_comb_bita[5..0].datad = ( B"1", B"1", B"1", B"1", B"1", B"1"); + counter_reg_bit[].asdata = ((! sclr) & ((sset & s_val[]) # ((! sset) & data[]))); + counter_reg_bit[].clk = clock; + counter_reg_bit[].clrn = (! aclr_actual); + counter_reg_bit[].d = ( counter_comb_bita[5..0].combout); + counter_reg_bit[].ena = (clk_en & (((sclr # sset) # sload) # cnt_en)); + counter_reg_bit[].sload = ((sclr # sset) # sload); + aclr_actual = aclr; + clk_en = VCC; + data[] = GND; + external_cin = B"1"; + q[] = safe_q[]; + s_val[] = B"111111"; + safe_q[] = counter_reg_bit[].q; + sload = GND; + sset = GND; + updown_dir = updown; +END; +--VALID FILE diff --git a/MCTEST/DE0-nano-HD/db/cntr_v9b.tdf b/MCTEST/DE0-nano-HD/db/cntr_v9b.tdf new file mode 100644 index 00000000..04445799 --- /dev/null +++ b/MCTEST/DE0-nano-HD/db/cntr_v9b.tdf @@ -0,0 +1,96 @@ +--lpm_counter DEVICE_FAMILY="Cyclone IV E" lpm_direction="UP" lpm_port_updown="PORT_UNUSED" lpm_width=6 clock cnt_en q sclr +--VERSION_BEGIN 12.1SP1 cbx_cycloneii 2013:01:31:18:05:07:SJ cbx_lpm_add_sub 2013:01:31:18:05:07:SJ cbx_lpm_compare 2013:01:31:18:05:07:SJ cbx_lpm_counter 2013:01:31:18:05:07:SJ cbx_lpm_decode 2013:01:31:18:05:07:SJ cbx_mgl 2013:01:31:18:08:27:SJ cbx_stratix 2013:01:31:18:05:07:SJ cbx_stratixii 2013:01:31:18:05:07:SJ VERSION_END + + +-- Copyright (C) 1991-2012 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +FUNCTION cycloneive_lcell_comb (cin, dataa, datab, datac, datad) +WITH ( DONT_TOUCH, LUT_MASK, SUM_LUTC_INPUT) +RETURNS ( combout, cout); + +--synthesis_resources = lut 6 reg 6 +SUBDESIGN cntr_v9b +( + clock : input; + cnt_en : input; + q[5..0] : output; + sclr : input; +) +VARIABLE + counter_comb_bita0 : cycloneive_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_comb_bita1 : cycloneive_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_comb_bita2 : cycloneive_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_comb_bita3 : cycloneive_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_comb_bita4 : cycloneive_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_comb_bita5 : cycloneive_lcell_comb + WITH ( + LUT_MASK = "5A90", + SUM_LUTC_INPUT = "cin" + ); + counter_reg_bit[5..0] : dffeas; + aclr_actual : WIRE; + clk_en : NODE; + data[5..0] : NODE; + external_cin : WIRE; + s_val[5..0] : WIRE; + safe_q[5..0] : WIRE; + sload : NODE; + sset : NODE; + updown_dir : WIRE; + +BEGIN + counter_comb_bita[5..0].cin = ( counter_comb_bita[4..0].cout, external_cin); + counter_comb_bita[5..0].dataa = ( counter_reg_bit[5..0].q); + counter_comb_bita[5..0].datab = ( updown_dir, updown_dir, updown_dir, updown_dir, updown_dir, updown_dir); + counter_comb_bita[5..0].datad = ( B"1", B"1", B"1", B"1", B"1", B"1"); + counter_reg_bit[].asdata = ((! sclr) & ((sset & s_val[]) # ((! sset) & data[]))); + counter_reg_bit[].clk = clock; + counter_reg_bit[].clrn = (! aclr_actual); + counter_reg_bit[].d = ( counter_comb_bita[5..0].combout); + counter_reg_bit[].ena = (clk_en & (((sclr # sset) # sload) # cnt_en)); + counter_reg_bit[].sload = ((sclr # sset) # sload); + aclr_actual = B"0"; + clk_en = VCC; + data[] = GND; + external_cin = B"1"; + q[] = safe_q[]; + s_val[] = B"111111"; + safe_q[] = counter_reg_bit[].q; + sload = GND; + sset = GND; + updown_dir = B"1"; +END; +--VALID FILE diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.(0).cnf.cdb b/MCTEST/DE0-nano-HD/db/de0_nano_system.(0).cnf.cdb new file mode 100644 index 00000000..b465cd83 Binary files /dev/null and b/MCTEST/DE0-nano-HD/db/de0_nano_system.(0).cnf.cdb differ diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.(0).cnf.hdb b/MCTEST/DE0-nano-HD/db/de0_nano_system.(0).cnf.hdb new file mode 100644 index 00000000..a567af45 Binary files /dev/null and b/MCTEST/DE0-nano-HD/db/de0_nano_system.(0).cnf.hdb differ diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.(1).cnf.cdb b/MCTEST/DE0-nano-HD/db/de0_nano_system.(1).cnf.cdb new file mode 100644 index 00000000..96aeb6b1 Binary files /dev/null and b/MCTEST/DE0-nano-HD/db/de0_nano_system.(1).cnf.cdb differ diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.(1).cnf.hdb b/MCTEST/DE0-nano-HD/db/de0_nano_system.(1).cnf.hdb new file mode 100644 index 00000000..c10af1fd Binary files /dev/null and b/MCTEST/DE0-nano-HD/db/de0_nano_system.(1).cnf.hdb differ diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.(10).cnf.cdb b/MCTEST/DE0-nano-HD/db/de0_nano_system.(10).cnf.cdb new file mode 100644 index 00000000..9d93c9c5 Binary files /dev/null and b/MCTEST/DE0-nano-HD/db/de0_nano_system.(10).cnf.cdb differ diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.(10).cnf.hdb b/MCTEST/DE0-nano-HD/db/de0_nano_system.(10).cnf.hdb new file mode 100644 index 00000000..b21638ed Binary files /dev/null and b/MCTEST/DE0-nano-HD/db/de0_nano_system.(10).cnf.hdb differ diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.(100).cnf.cdb b/MCTEST/DE0-nano-HD/db/de0_nano_system.(100).cnf.cdb new file mode 100644 index 00000000..a2bba3d7 Binary files /dev/null and b/MCTEST/DE0-nano-HD/db/de0_nano_system.(100).cnf.cdb differ diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.(100).cnf.hdb b/MCTEST/DE0-nano-HD/db/de0_nano_system.(100).cnf.hdb new file mode 100644 index 00000000..ddf18f16 Binary files /dev/null and b/MCTEST/DE0-nano-HD/db/de0_nano_system.(100).cnf.hdb differ diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.(101).cnf.cdb b/MCTEST/DE0-nano-HD/db/de0_nano_system.(101).cnf.cdb new file mode 100644 index 00000000..0171ec4e Binary files /dev/null and b/MCTEST/DE0-nano-HD/db/de0_nano_system.(101).cnf.cdb differ diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.(101).cnf.hdb b/MCTEST/DE0-nano-HD/db/de0_nano_system.(101).cnf.hdb new file mode 100644 index 00000000..166cdd1c Binary files /dev/null and b/MCTEST/DE0-nano-HD/db/de0_nano_system.(101).cnf.hdb differ diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.(102).cnf.cdb b/MCTEST/DE0-nano-HD/db/de0_nano_system.(102).cnf.cdb new file mode 100644 index 00000000..afe2558a Binary files /dev/null and b/MCTEST/DE0-nano-HD/db/de0_nano_system.(102).cnf.cdb differ diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.(102).cnf.hdb b/MCTEST/DE0-nano-HD/db/de0_nano_system.(102).cnf.hdb new file mode 100644 index 00000000..166cdd1c Binary files /dev/null and b/MCTEST/DE0-nano-HD/db/de0_nano_system.(102).cnf.hdb differ diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.(103).cnf.cdb b/MCTEST/DE0-nano-HD/db/de0_nano_system.(103).cnf.cdb new file mode 100644 index 00000000..1f436884 Binary files /dev/null and b/MCTEST/DE0-nano-HD/db/de0_nano_system.(103).cnf.cdb differ diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.(103).cnf.hdb b/MCTEST/DE0-nano-HD/db/de0_nano_system.(103).cnf.hdb new file mode 100644 index 00000000..f12ac1e5 Binary files /dev/null and b/MCTEST/DE0-nano-HD/db/de0_nano_system.(103).cnf.hdb differ diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.(104).cnf.cdb b/MCTEST/DE0-nano-HD/db/de0_nano_system.(104).cnf.cdb new file mode 100644 index 00000000..d86a16a5 Binary files /dev/null and b/MCTEST/DE0-nano-HD/db/de0_nano_system.(104).cnf.cdb differ diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.(104).cnf.hdb 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a/MCTEST/DE0-nano-HD/db/de0_nano_system.(88).cnf.hdb b/MCTEST/DE0-nano-HD/db/de0_nano_system.(88).cnf.hdb new file mode 100644 index 00000000..0f3fc021 Binary files /dev/null and b/MCTEST/DE0-nano-HD/db/de0_nano_system.(88).cnf.hdb differ diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.(89).cnf.cdb b/MCTEST/DE0-nano-HD/db/de0_nano_system.(89).cnf.cdb new file mode 100644 index 00000000..e8c22914 Binary files /dev/null and b/MCTEST/DE0-nano-HD/db/de0_nano_system.(89).cnf.cdb differ diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.(89).cnf.hdb b/MCTEST/DE0-nano-HD/db/de0_nano_system.(89).cnf.hdb new file mode 100644 index 00000000..c2ebcf91 Binary files /dev/null and b/MCTEST/DE0-nano-HD/db/de0_nano_system.(89).cnf.hdb differ diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.(9).cnf.cdb b/MCTEST/DE0-nano-HD/db/de0_nano_system.(9).cnf.cdb new file mode 100644 index 00000000..cbf4c83c Binary files /dev/null and b/MCTEST/DE0-nano-HD/db/de0_nano_system.(9).cnf.cdb differ diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.(9).cnf.hdb b/MCTEST/DE0-nano-HD/db/de0_nano_system.(9).cnf.hdb new file mode 100644 index 00000000..9e0d2f46 Binary files /dev/null and b/MCTEST/DE0-nano-HD/db/de0_nano_system.(9).cnf.hdb differ diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.(90).cnf.cdb b/MCTEST/DE0-nano-HD/db/de0_nano_system.(90).cnf.cdb new file mode 100644 index 00000000..120d80ad Binary files /dev/null and b/MCTEST/DE0-nano-HD/db/de0_nano_system.(90).cnf.cdb differ diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.(90).cnf.hdb b/MCTEST/DE0-nano-HD/db/de0_nano_system.(90).cnf.hdb new file mode 100644 index 00000000..c9074a75 Binary files /dev/null and b/MCTEST/DE0-nano-HD/db/de0_nano_system.(90).cnf.hdb differ diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.(91).cnf.cdb b/MCTEST/DE0-nano-HD/db/de0_nano_system.(91).cnf.cdb new file mode 100644 index 00000000..5fd37f5c Binary files /dev/null and b/MCTEST/DE0-nano-HD/db/de0_nano_system.(91).cnf.cdb differ diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.(91).cnf.hdb b/MCTEST/DE0-nano-HD/db/de0_nano_system.(91).cnf.hdb new file mode 100644 index 00000000..5b71affb Binary files /dev/null and b/MCTEST/DE0-nano-HD/db/de0_nano_system.(91).cnf.hdb differ diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.(92).cnf.cdb b/MCTEST/DE0-nano-HD/db/de0_nano_system.(92).cnf.cdb new file mode 100644 index 00000000..6de12d24 Binary files /dev/null and b/MCTEST/DE0-nano-HD/db/de0_nano_system.(92).cnf.cdb differ diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.(92).cnf.hdb b/MCTEST/DE0-nano-HD/db/de0_nano_system.(92).cnf.hdb new file mode 100644 index 00000000..037c44b2 Binary files /dev/null and b/MCTEST/DE0-nano-HD/db/de0_nano_system.(92).cnf.hdb differ diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.(93).cnf.cdb b/MCTEST/DE0-nano-HD/db/de0_nano_system.(93).cnf.cdb new file mode 100644 index 00000000..f0eeb5e9 Binary files /dev/null and b/MCTEST/DE0-nano-HD/db/de0_nano_system.(93).cnf.cdb differ diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.(93).cnf.hdb b/MCTEST/DE0-nano-HD/db/de0_nano_system.(93).cnf.hdb new file mode 100644 index 00000000..36bfd865 Binary files /dev/null and b/MCTEST/DE0-nano-HD/db/de0_nano_system.(93).cnf.hdb differ diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.(94).cnf.cdb b/MCTEST/DE0-nano-HD/db/de0_nano_system.(94).cnf.cdb new file mode 100644 index 00000000..15ab8e7c Binary files /dev/null and b/MCTEST/DE0-nano-HD/db/de0_nano_system.(94).cnf.cdb differ diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.(94).cnf.hdb b/MCTEST/DE0-nano-HD/db/de0_nano_system.(94).cnf.hdb new file mode 100644 index 00000000..dcc774e2 Binary files /dev/null and b/MCTEST/DE0-nano-HD/db/de0_nano_system.(94).cnf.hdb differ diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.(95).cnf.cdb b/MCTEST/DE0-nano-HD/db/de0_nano_system.(95).cnf.cdb new file mode 100644 index 00000000..b4cb6eeb Binary files /dev/null and b/MCTEST/DE0-nano-HD/db/de0_nano_system.(95).cnf.cdb differ diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.(95).cnf.hdb b/MCTEST/DE0-nano-HD/db/de0_nano_system.(95).cnf.hdb new file mode 100644 index 00000000..02e712c1 Binary files /dev/null and b/MCTEST/DE0-nano-HD/db/de0_nano_system.(95).cnf.hdb differ diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.(96).cnf.cdb b/MCTEST/DE0-nano-HD/db/de0_nano_system.(96).cnf.cdb new file mode 100644 index 00000000..454a12cf Binary files /dev/null and b/MCTEST/DE0-nano-HD/db/de0_nano_system.(96).cnf.cdb differ diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.(96).cnf.hdb b/MCTEST/DE0-nano-HD/db/de0_nano_system.(96).cnf.hdb new file mode 100644 index 00000000..07d5f9e9 Binary files /dev/null and b/MCTEST/DE0-nano-HD/db/de0_nano_system.(96).cnf.hdb differ diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.(97).cnf.cdb b/MCTEST/DE0-nano-HD/db/de0_nano_system.(97).cnf.cdb new file mode 100644 index 00000000..ef89dea6 Binary files /dev/null and b/MCTEST/DE0-nano-HD/db/de0_nano_system.(97).cnf.cdb differ diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.(97).cnf.hdb b/MCTEST/DE0-nano-HD/db/de0_nano_system.(97).cnf.hdb new file mode 100644 index 00000000..2e7e2549 Binary files /dev/null and b/MCTEST/DE0-nano-HD/db/de0_nano_system.(97).cnf.hdb differ diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.(98).cnf.cdb b/MCTEST/DE0-nano-HD/db/de0_nano_system.(98).cnf.cdb new file mode 100644 index 00000000..fb35d388 Binary files /dev/null and b/MCTEST/DE0-nano-HD/db/de0_nano_system.(98).cnf.cdb differ diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.(98).cnf.hdb b/MCTEST/DE0-nano-HD/db/de0_nano_system.(98).cnf.hdb new file mode 100644 index 00000000..fc70322b Binary files /dev/null and b/MCTEST/DE0-nano-HD/db/de0_nano_system.(98).cnf.hdb differ diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.(99).cnf.cdb b/MCTEST/DE0-nano-HD/db/de0_nano_system.(99).cnf.cdb new file mode 100644 index 00000000..788cfb39 Binary files /dev/null and b/MCTEST/DE0-nano-HD/db/de0_nano_system.(99).cnf.cdb differ diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.(99).cnf.hdb b/MCTEST/DE0-nano-HD/db/de0_nano_system.(99).cnf.hdb new file mode 100644 index 00000000..8e342763 Binary files /dev/null and b/MCTEST/DE0-nano-HD/db/de0_nano_system.(99).cnf.hdb differ diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.asm.qmsg b/MCTEST/DE0-nano-HD/db/de0_nano_system.asm.qmsg new file mode 100644 index 00000000..13395777 --- /dev/null +++ b/MCTEST/DE0-nano-HD/db/de0_nano_system.asm.qmsg @@ -0,0 +1,6 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1 1394837373424 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Full Version " "Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1 1394837373425 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Mar 14 16:49:33 2014 " "Processing started: Fri Mar 14 16:49:33 2014" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1 1394837373425 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1 1394837373425 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off de0_nano_system -c de0_nano_system " "Command: quartus_asm --read_settings_files=off --write_settings_files=off de0_nano_system -c de0_nano_system" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1 1394837373425 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "" 0 -1 1394837375362 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "" 0 -1 1394837375394 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "447 " "Peak virtual memory: 447 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1 1394837375824 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Mar 14 16:49:35 2014 " "Processing ended: Fri Mar 14 16:49:35 2014" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1 1394837375824 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1 1394837375824 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1 1394837375824 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1 1394837375824 ""} diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.asm.rdb b/MCTEST/DE0-nano-HD/db/de0_nano_system.asm.rdb new file mode 100644 index 00000000..3b5f996d Binary files /dev/null and b/MCTEST/DE0-nano-HD/db/de0_nano_system.asm.rdb differ diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.asm_labs.ddb b/MCTEST/DE0-nano-HD/db/de0_nano_system.asm_labs.ddb new file mode 100644 index 00000000..9de4f66a Binary files /dev/null and b/MCTEST/DE0-nano-HD/db/de0_nano_system.asm_labs.ddb differ diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.autoh_e40e1.map.reg_db.cdb b/MCTEST/DE0-nano-HD/db/de0_nano_system.autoh_e40e1.map.reg_db.cdb new file mode 100644 index 00000000..d39265cc Binary files /dev/null and b/MCTEST/DE0-nano-HD/db/de0_nano_system.autoh_e40e1.map.reg_db.cdb differ diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.cbx.xml b/MCTEST/DE0-nano-HD/db/de0_nano_system.cbx.xml new file mode 100644 index 00000000..6193b4f2 --- /dev/null +++ b/MCTEST/DE0-nano-HD/db/de0_nano_system.cbx.xml @@ -0,0 +1,23 @@ + + + + + + + + + + + + + + + + + + + + + + + diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.cmp.bpm b/MCTEST/DE0-nano-HD/db/de0_nano_system.cmp.bpm new file mode 100644 index 00000000..a01f9033 Binary files /dev/null and b/MCTEST/DE0-nano-HD/db/de0_nano_system.cmp.bpm differ diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.cmp.cdb b/MCTEST/DE0-nano-HD/db/de0_nano_system.cmp.cdb new file mode 100644 index 00000000..8c85347a Binary files /dev/null and b/MCTEST/DE0-nano-HD/db/de0_nano_system.cmp.cdb differ diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.cmp.hdb b/MCTEST/DE0-nano-HD/db/de0_nano_system.cmp.hdb new file mode 100644 index 00000000..ac49bad6 Binary files /dev/null and b/MCTEST/DE0-nano-HD/db/de0_nano_system.cmp.hdb differ diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.cmp.idb b/MCTEST/DE0-nano-HD/db/de0_nano_system.cmp.idb new file mode 100644 index 00000000..fa98f523 Binary files /dev/null and b/MCTEST/DE0-nano-HD/db/de0_nano_system.cmp.idb differ diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.cmp.kpt b/MCTEST/DE0-nano-HD/db/de0_nano_system.cmp.kpt new file mode 100644 index 00000000..f3a0578f Binary files /dev/null and b/MCTEST/DE0-nano-HD/db/de0_nano_system.cmp.kpt differ diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.cmp.logdb b/MCTEST/DE0-nano-HD/db/de0_nano_system.cmp.logdb new file mode 100644 index 00000000..a30e2b6e --- /dev/null +++ b/MCTEST/DE0-nano-HD/db/de0_nano_system.cmp.logdb @@ -0,0 +1,171 @@ +v1 +DSP_BALANCING_IMPLEMENTATION,DSP_BLOCKS,system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3, +DSP_BALANCING_IMPLEMENTATION,DSP_BLOCKS,system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3, +PORT_SWAPPING,PORT_SWAPPING_FINISHED,system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_mult2, +IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,, +IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,PASS,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,0 such failures found.,,I/O,, +IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,, +IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,, +IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,, +IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,, +IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,, +IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,PASS,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,0 such failures found.,,I/O,, +IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,, +IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,, +IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os.,Critical,0 such failures found.,,I/O,, +IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,, +IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,, +IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,, +IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000033;IO_000034;IO_000042, +IO_RULES_MATRIX,Total Pass,122;37;122;0;0;126;122;0;126;126;0;115;0;0;91;0;115;91;0;0;65;115;0;0;0;0;0;126;0;0, +IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, +IO_RULES_MATRIX,Total Inapplicable,4;89;4;126;126;0;4;126;0;0;126;11;126;126;35;126;11;35;126;126;61;11;126;126;126;126;126;0;126;126, +IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, +IO_RULES_MATRIX,DRAM_CLK,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,DRAM_CKE,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,DRAM_CS_N,Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,DRAM_RAS_N,Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,DRAM_CAS_N,Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,DRAM_WE_N,Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,DRAM_DQM[0],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,DRAM_DQM[1],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,DRAM_ADDR[0],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,DRAM_ADDR[1],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,DRAM_ADDR[2],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,DRAM_ADDR[3],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,DRAM_ADDR[4],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,DRAM_ADDR[5],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,DRAM_ADDR[6],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,DRAM_ADDR[7],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,DRAM_ADDR[8],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,DRAM_ADDR[9],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,DRAM_ADDR[10],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,DRAM_ADDR[11],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,DRAM_ADDR[12],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,DRAM_BA[0],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,DRAM_BA[1],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LED[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LED[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LED[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LED[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LED[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LED[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LED[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,LED[7],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,GPIO_0[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,GPIO_0[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,GPIO_0[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,GPIO_0[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,GPIO_0[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,GPIO_0[7],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,GPIO_0[8],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,GPIO_0[9],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,GPIO_0[10],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,GPIO_0[11],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,GPIO_0[12],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,GPIO_0[13],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,GPIO_0[14],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,GPIO_0[15],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,GPIO_0[16],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,GPIO_0[17],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,GPIO_0[18],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,GPIO_0[19],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,GPIO_0[20],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,GPIO_0[21],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,GPIO_0[22],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,GPIO_0[23],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,GPIO_0[24],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,GPIO_0[25],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,GPIO_0[26],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,GPIO_0[27],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,GPIO_0[28],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,GPIO_0[29],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,GPIO_0[30],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,GPIO_0[31],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,GPIO_0[32],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,GPIO_0[33],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,GPIO_1[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,GPIO_1[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,GPIO_1[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,GPIO_1[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,GPIO_1[4],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,GPIO_1[5],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,GPIO_1[6],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,GPIO_1[7],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,GPIO_1[8],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,GPIO_1[9],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,GPIO_1[10],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,GPIO_1[11],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,GPIO_1[13],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,GPIO_1[14],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,GPIO_1[15],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,GPIO_1[16],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,GPIO_1[17],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,GPIO_1[18],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,GPIO_1[19],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,GPIO_1[20],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,GPIO_1[21],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,GPIO_1[22],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,GPIO_1[23],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,GPIO_1[25],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,GPIO_1[27],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,GPIO_1[28],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,GPIO_1[29],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,GPIO_1[30],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,GPIO_1[31],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,GPIO_1[32],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,GPIO_1[33],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,DRAM_DQ[0],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,DRAM_DQ[1],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,DRAM_DQ[2],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,DRAM_DQ[3],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,DRAM_DQ[4],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,DRAM_DQ[5],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,DRAM_DQ[6],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,DRAM_DQ[7],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,DRAM_DQ[8],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,DRAM_DQ[9],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,DRAM_DQ[10],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,DRAM_DQ[11],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,DRAM_DQ[12],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,DRAM_DQ[13],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,DRAM_DQ[14],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,DRAM_DQ[15],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,GPIO_0[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,GPIO_0[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,GPIO_1[12],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,GPIO_1[24],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,GPIO_1[26],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,CLOCK_50,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[3],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[2],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,KEY[1],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,KEY[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,SW[0],Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,altera_reserved_tms,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,altera_reserved_tck,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,altera_reserved_tdi,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_MATRIX,altera_reserved_tdo,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, +IO_RULES_SUMMARY,Total I/O Rules,30, +IO_RULES_SUMMARY,Number of I/O Rules Passed,14, +IO_RULES_SUMMARY,Number of I/O Rules Failed,0, +IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0, +IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,16, diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.cmp.rdb b/MCTEST/DE0-nano-HD/db/de0_nano_system.cmp.rdb new file mode 100644 index 00000000..78b0e970 Binary files /dev/null and b/MCTEST/DE0-nano-HD/db/de0_nano_system.cmp.rdb differ diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.cmp_merge.kpt b/MCTEST/DE0-nano-HD/db/de0_nano_system.cmp_merge.kpt new file mode 100644 index 00000000..71152185 Binary files /dev/null and b/MCTEST/DE0-nano-HD/db/de0_nano_system.cmp_merge.kpt differ diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd b/MCTEST/DE0-nano-HD/db/de0_nano_system.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd new file mode 100644 index 00000000..430e5ca8 Binary files /dev/null and b/MCTEST/DE0-nano-HD/db/de0_nano_system.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd differ diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.cycloneive_io_sim_cache.45um_tt_1200mv_0c_slow.hsd b/MCTEST/DE0-nano-HD/db/de0_nano_system.cycloneive_io_sim_cache.45um_tt_1200mv_0c_slow.hsd new file mode 100644 index 00000000..dc4c3a39 Binary files /dev/null and b/MCTEST/DE0-nano-HD/db/de0_nano_system.cycloneive_io_sim_cache.45um_tt_1200mv_0c_slow.hsd differ diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.cycloneive_io_sim_cache.45um_tt_1200mv_85c_slow.hsd b/MCTEST/DE0-nano-HD/db/de0_nano_system.cycloneive_io_sim_cache.45um_tt_1200mv_85c_slow.hsd new file mode 100644 index 00000000..2e623f94 Binary files /dev/null and b/MCTEST/DE0-nano-HD/db/de0_nano_system.cycloneive_io_sim_cache.45um_tt_1200mv_85c_slow.hsd differ diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.db_info b/MCTEST/DE0-nano-HD/db/de0_nano_system.db_info new file mode 100644 index 00000000..e723cc50 --- /dev/null +++ b/MCTEST/DE0-nano-HD/db/de0_nano_system.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Full Version +Version_Index = 285274881 +Creation_Time = Thu Mar 20 16:00:31 2014 diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.fit.qmsg b/MCTEST/DE0-nano-HD/db/de0_nano_system.fit.qmsg new file mode 100644 index 00000000..14c378b9 --- /dev/null +++ b/MCTEST/DE0-nano-HD/db/de0_nano_system.fit.qmsg @@ -0,0 +1,63 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1 1394837332919 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 64-Bit " "Running Quartus II 64-Bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Full Version " "Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1 1394837332919 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Mar 14 16:48:52 2014 " "Processing started: Fri Mar 14 16:48:52 2014" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1 1394837332919 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1 1394837332919 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off de0_nano_system -c de0_nano_system " "Command: quartus_fit --read_settings_files=off --write_settings_files=off de0_nano_system -c de0_nano_system" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1 1394837332919 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." { } { } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "" 0 -1 1394837333072 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "de0_nano_system EP4CE22F17C6 " "Selected device EP4CE22F17C6 for design \"de0_nano_system\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 -1 1394837333357 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "" 0 -1 1394837333402 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "" 0 -1 1394837333402 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "" 0 -1 1394837333402 ""} +{ "Info" "ICUT_CUT_PLL_COMPUTATION_SUCCESS" "pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|pll1 Cyclone IV E PLL " "Implemented PLL \"pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|pll1\" as Cyclone IV E PLL type" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|wire_pll1_clk\[0\] 2 1 0 0 " "Implementing clock multiplication of 2, clock division of 1, and phase shift of 0 degrees (0 ps) for pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|wire_pll1_clk\[0\] port" { } { { "db/pll_sys_altpll.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/pll_sys_altpll.v" 45 -1 0 } } { "" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 6111 8336 9085 0} } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "" 0 -1 1394837333449 ""} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|wire_pll1_clk\[1\] 2 1 -54 -1500 " "Implementing clock multiplication of 2, clock division of 1, and phase shift of -54 degrees (-1500 ps) for pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|wire_pll1_clk\[1\] port" { } { { "db/pll_sys_altpll.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/pll_sys_altpll.v" 45 -1 0 } } { "" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 6112 8336 9085 0} } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "" 0 -1 1394837333449 ""} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|wire_pll1_clk\[2\] 1 5 0 0 " "Implementing clock multiplication of 1, clock division of 5, and phase shift of 0 degrees (0 ps) for pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|wire_pll1_clk\[2\] port" { } { { "db/pll_sys_altpll.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/pll_sys_altpll.v" 45 -1 0 } } { "" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 6113 8336 9085 0} } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "" 0 -1 1394837333449 ""} } { { "db/pll_sys_altpll.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/pll_sys_altpll.v" 45 -1 0 } } { "" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 6111 8336 9085 0} } } } } 0 15535 "Implemented %3!s! \"%1!s!\" as %2!s! PLL type" 0 0 "" 0 -1 1394837333449 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0 -1 1394837333648 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE10F17C6 " "Device EP4CE10F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "" 0 -1 1394837333926 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE6F17C6 " "Device EP4CE6F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "" 0 -1 1394837333926 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE15F17C6 " "Device EP4CE15F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "" 0 -1 1394837333926 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 -1 1394837333926 ""} +{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ C1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location C1" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 16267 8336 9085 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1 1394837333940 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ D2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location D2" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 16269 8336 9085 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1 1394837333940 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ H1 " "Pin ~ALTERA_DCLK~ is reserved at location H1" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 16271 8336 9085 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1 1394837333940 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ H2 " "Pin ~ALTERA_DATA0~ is reserved at location H2" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 16273 8336 9085 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1 1394837333940 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ F16 " "Pin ~ALTERA_nCEO~ is reserved at location F16" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 16275 8336 9085 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1 1394837333940 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 -1 1394837333940 ""} +{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "" 0 -1 1394837333942 ""} +{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." { } { } 0 176045 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "" 0 -1 1394837333995 ""} +{ "Info" "ISTA_SDC_STATEMENT_PARENT" "" "Evaluating HDL-embedded SDC commands" { { "Info" "ISTA_SDC_STATEMENT_ENTITY" "alt_jtag_atlantic " "Entity alt_jtag_atlantic" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate1*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate1*\}\] " { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394837335660 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394837335660 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394837335660 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394837335660 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394837335660 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394837335660 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394837335660 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394837335660 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394837335660 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|read1*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|read1*\}\] " { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394837335660 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read_req\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read_req\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394837335660 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394837335660 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|tck_t_dav\}\] " "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|tck_t_dav\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394837335660 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|user_saw_rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid0*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|user_saw_rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid0*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394837335660 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394837335660 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394837335660 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394837335660 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394837335660 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394837335660 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394837335660 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394837335660 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394837335660 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write1*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write1*\}\] " { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394837335660 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_ena*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_ena*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394837335660 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_pause*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_pause*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394837335660 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_valid\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_valid\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394837335660 ""} } { } 0 332165 "Entity %1!s!" 0 0 "" 0 -1 1394837335660 ""} { "Info" "ISTA_SDC_STATEMENT_ENTITY" "altera_std_synchronizer " "Entity altera_std_synchronizer" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -to \[get_keepers \{*altera_std_synchronizer:*\|din_s1\}\] " "set_false_path -to \[get_keepers \{*altera_std_synchronizer:*\|din_s1\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394837335660 ""} } { } 0 332165 "Entity %1!s!" 0 0 "" 0 -1 1394837335660 ""} { "Info" "ISTA_SDC_STATEMENT_ENTITY" "sld_jtag_hub " "Entity sld_jtag_hub" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "create_clock -period 10MHz -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] " "create_clock -period 10MHz -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394837335660 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_clock_groups -asynchronous -group \{altera_reserved_tck\} " "set_clock_groups -asynchronous -group \{altera_reserved_tck\}" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394837335660 ""} } { } 0 332165 "Entity %1!s!" 0 0 "" 0 -1 1394837335660 ""} } { } 0 332164 "Evaluating HDL-embedded SDC commands" 0 0 "" 0 -1 1394837335660 ""} +{ "Info" "ISTA_SDC_FOUND" "de0_nano_system.sdc " "Reading SDC File: 'de0_nano_system.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "" 0 -1 1394837335941 ""} +{ "Warning" "WSTA_OVERWRITING_EXISTING_CLOCK" "altera_reserved_tck " "Overwriting existing clock: altera_reserved_tck" { } { } 0 332043 "Overwriting existing clock: %1!s!" 0 0 "" 0 -1 1394837335956 ""} +{ "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "Deriving PLL clocks " "Deriving PLL clocks" { { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -duty_cycle 50.00 -name \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} " "create_generated_clock -source \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -duty_cycle 50.00 -name \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}" { } { } 0 332110 "%1!s!" 0 0 "" 0 -1 1394837335957 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -phase -54.00 -duty_cycle 50.00 -name \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} " "create_generated_clock -source \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -phase -54.00 -duty_cycle 50.00 -name \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}" { } { } 0 332110 "%1!s!" 0 0 "" 0 -1 1394837335957 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 5 -duty_cycle 50.00 -name \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} " "create_generated_clock -source \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 5 -duty_cycle 50.00 -name \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\]\}" { } { } 0 332110 "%1!s!" 0 0 "" 0 -1 1394837335957 ""} } { } 0 332110 "%1!s!" 0 0 "" 0 -1 1394837335957 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_CALL_IS_DELAYED" "" "Clock uncertainty is not calculated until you update the timing netlist." { } { } 0 332151 "Clock uncertainty is not calculated until you update the timing netlist." 0 0 "" 0 -1 1394837335957 ""} +{ "Info" "ISTA_SDC_FOUND" "system/synthesis/submodules/altera_reset_controller.sdc " "Reading SDC File: 'system/synthesis/submodules/altera_reset_controller.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "" 0 -1 1394837335966 ""} +{ "Info" "ISTA_SDC_FOUND" "system/synthesis/submodules/system_cpu.sdc " "Reading SDC File: 'system/synthesis/submodules/system_cpu.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "" 0 -1 1394837335991 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "" 0 -1 1394837336180 ""} +{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "" 0 -1 1394837336182 ""} +{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 5 clocks " "Found 5 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "" 0 -1 1394837336183 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "" 0 -1 1394837336183 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 100.000 altera_reserved_tck " " 100.000 altera_reserved_tck" { } { } 0 332111 "%1!s!" 0 0 "" 0 -1 1394837336183 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 20.000 CLOCK_50 " " 20.000 CLOCK_50" { } { } 0 332111 "%1!s!" 0 0 "" 0 -1 1394837336183 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 10.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 10.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\]" { } { } 0 332111 "%1!s!" 0 0 "" 0 -1 1394837336183 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 10.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 10.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[1\]" { } { } 0 332111 "%1!s!" 0 0 "" 0 -1 1394837336183 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 100.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 100.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\]" { } { } 0 332111 "%1!s!" 0 0 "" 0 -1 1394837336183 ""} } { } 0 332111 "%1!s!" 0 0 "" 0 -1 1394837336183 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C0 of PLL_4) " "Automatically promoted node pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C0 of PLL_4)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G18 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G18" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1 1394837336613 ""} } { { "db/pll_sys_altpll.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/pll_sys_altpll.v" 80 -1 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { pll_sys:inst_pll_sys|altpll:altpll_component|pll_sys_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 6111 8336 9085 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1 1394837336613 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|wire_pll1_clk\[1\] (placed in counter C2 of PLL_4) " "Automatically promoted node pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|wire_pll1_clk\[1\] (placed in counter C2 of PLL_4)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G17 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G17" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1 1394837336613 ""} } { { "db/pll_sys_altpll.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/pll_sys_altpll.v" 80 -1 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { pll_sys:inst_pll_sys|altpll:altpll_component|pll_sys_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 6111 8336 9085 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1 1394837336613 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|wire_pll1_clk\[2\] (placed in counter C1 of PLL_4) " "Automatically promoted node pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|wire_pll1_clk\[2\] (placed in counter C1 of PLL_4)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G19 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G19" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1 1394837336614 ""} } { { "db/pll_sys_altpll.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/pll_sys_altpll.v" 80 -1 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { pll_sys:inst_pll_sys|altpll:altpll_component|pll_sys_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 6111 8336 9085 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1 1394837336614 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "altera_internal_jtag~TCKUTAP " "Automatically promoted node altera_internal_jtag~TCKUTAP " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1 1394837336614 ""} } { { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 15746 8336 9085 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1 1394837336614 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "system:inst_cpu\|altera_reset_controller:rst_controller\|altera_reset_synchronizer:alt_rst_sync_uq1\|altera_reset_synchronizer_int_chain_out " "Automatically promoted node system:inst_cpu\|altera_reset_controller:rst_controller\|altera_reset_synchronizer:alt_rst_sync_uq1\|altera_reset_synchronizer_int_chain_out " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1 1394837336614 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr\|counter_reg_bit\[6\] " "Destination node system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr\|counter_reg_bit\[6\]" { } { { "db/cntr_0ab.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/cntr_0ab.tdf" 68 17 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 6323 8336 9085 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "" 0 -1 1394837336614 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr\|counter_reg_bit\[5\] " "Destination node system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr\|counter_reg_bit\[5\]" { } { { "db/cntr_0ab.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/cntr_0ab.tdf" 68 17 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 6324 8336 9085 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "" 0 -1 1394837336614 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr\|counter_reg_bit\[4\] " "Destination node system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr\|counter_reg_bit\[4\]" { } { { "db/cntr_0ab.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/cntr_0ab.tdf" 68 17 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 6325 8336 9085 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "" 0 -1 1394837336614 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr\|counter_reg_bit\[3\] " "Destination node system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr\|counter_reg_bit\[3\]" { } { { "db/cntr_0ab.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/cntr_0ab.tdf" 68 17 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 6326 8336 9085 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "" 0 -1 1394837336614 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr\|counter_reg_bit\[2\] " "Destination node system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr\|counter_reg_bit\[2\]" { } { { "db/cntr_0ab.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/cntr_0ab.tdf" 68 17 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 6327 8336 9085 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "" 0 -1 1394837336614 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr\|counter_reg_bit\[1\] " "Destination node system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr\|counter_reg_bit\[1\]" { } { { "db/cntr_0ab.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/cntr_0ab.tdf" 68 17 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 6328 8336 9085 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "" 0 -1 1394837336614 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr\|counter_reg_bit\[0\] " "Destination node system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr\|counter_reg_bit\[0\]" { } { { "db/cntr_0ab.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/cntr_0ab.tdf" 68 17 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 6329 8336 9085 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "" 0 -1 1394837336614 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_ca7:usedw_counter\|counter_reg_bit\[6\] " "Destination node system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_ca7:usedw_counter\|counter_reg_bit\[6\]" { } { { "db/cntr_ca7.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/cntr_ca7.tdf" 69 17 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_ca7:usedw_counter|counter_reg_bit[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 6346 8336 9085 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "" 0 -1 1394837336614 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_ca7:usedw_counter\|counter_reg_bit\[5\] " "Destination node system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_ca7:usedw_counter\|counter_reg_bit\[5\]" { } { { "db/cntr_ca7.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/cntr_ca7.tdf" 69 17 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_ca7:usedw_counter|counter_reg_bit[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 6347 8336 9085 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "" 0 -1 1394837336614 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_ca7:usedw_counter\|counter_reg_bit\[4\] " "Destination node system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_ca7:usedw_counter\|counter_reg_bit\[4\]" { } { { "db/cntr_ca7.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/cntr_ca7.tdf" 69 17 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_ca7:usedw_counter|counter_reg_bit[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 6348 8336 9085 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "" 0 -1 1394837336614 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_LIMITED_TO_SUB" "10 " "Non-global destination nodes limited to 10 nodes" { } { } 0 176358 "Non-global destination nodes limited to %1!d! nodes" 0 0 "" 0 -1 1394837336614 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0 -1 1394837336614 ""} } { { "system/synthesis/submodules/altera_reset_synchronizer.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_reset_synchronizer.v" 62 -1 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 682 8336 9085 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1 1394837336614 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "sld_hub:auto_hub\|sld_jtag_hub:\\jtag_hub_gen:sld_jtag_hub_inst\|clr_reg " "Automatically promoted node sld_hub:auto_hub\|sld_jtag_hub:\\jtag_hub_gen:sld_jtag_hub_inst\|clr_reg " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1 1394837336616 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "sld_hub:auto_hub\|sld_jtag_hub:\\jtag_hub_gen:sld_jtag_hub_inst\|clr_reg~_wirecell " "Destination node sld_hub:auto_hub\|sld_jtag_hub:\\jtag_hub_gen:sld_jtag_hub_inst\|clr_reg~_wirecell" { } { { "sld_jtag_hub.vhd" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/sld_jtag_hub.vhd" 335 -1 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg~_wirecell } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 16127 8336 9085 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "" 0 -1 1394837336616 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0 -1 1394837336616 ""} } { { "sld_jtag_hub.vhd" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/sld_jtag_hub.vhd" 335 -1 0 } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "sld_hub:auto_hub\|sld_jtag_hub:\\jtag_hub_gen:sld_jtag_hub_inst\|clr_reg" } } } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 15877 8336 9085 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1 1394837336616 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "sld_hub:auto_hub\|sld_jtag_hub:\\jtag_hub_gen:sld_jtag_hub_inst\|sld_shadow_jsm:shadow_jsm\|state\[0\] " "Automatically promoted node sld_hub:auto_hub\|sld_jtag_hub:\\jtag_hub_gen:sld_jtag_hub_inst\|sld_shadow_jsm:shadow_jsm\|state\[0\] " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1 1394837336616 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "sld_hub:auto_hub\|sld_jtag_hub:\\jtag_hub_gen:sld_jtag_hub_inst\|sld_shadow_jsm:shadow_jsm\|state~0 " "Destination node sld_hub:auto_hub\|sld_jtag_hub:\\jtag_hub_gen:sld_jtag_hub_inst\|sld_shadow_jsm:shadow_jsm\|state~0" { } { { "sld_jtag_hub.vhd" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/sld_jtag_hub.vhd" 1076 -1 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 16011 8336 9085 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "" 0 -1 1394837336616 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "sld_hub:auto_hub\|sld_jtag_hub:\\jtag_hub_gen:sld_jtag_hub_inst\|sld_shadow_jsm:shadow_jsm\|state~1 " "Destination node sld_hub:auto_hub\|sld_jtag_hub:\\jtag_hub_gen:sld_jtag_hub_inst\|sld_shadow_jsm:shadow_jsm\|state~1" { } { { "sld_jtag_hub.vhd" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/sld_jtag_hub.vhd" 1076 -1 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state~1 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 16012 8336 9085 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "" 0 -1 1394837336616 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "sld_hub:auto_hub\|sld_jtag_hub:\\jtag_hub_gen:sld_jtag_hub_inst\|sld_shadow_jsm:shadow_jsm\|state\[0\]~_wirecell " "Destination node sld_hub:auto_hub\|sld_jtag_hub:\\jtag_hub_gen:sld_jtag_hub_inst\|sld_shadow_jsm:shadow_jsm\|state\[0\]~_wirecell" { } { { "sld_jtag_hub.vhd" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/sld_jtag_hub.vhd" 1090 -1 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0]~_wirecell } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 16128 8336 9085 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "" 0 -1 1394837336616 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0 -1 1394837336616 ""} } { { "sld_jtag_hub.vhd" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/sld_jtag_hub.vhd" 1090 -1 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 15770 8336 9085 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1 1394837336616 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "system:inst_cpu\|altera_reset_controller:rst_controller\|merged_reset~0 " "Automatically promoted node system:inst_cpu\|altera_reset_controller:rst_controller\|merged_reset~0 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1 1394837336617 ""} } { { "system/synthesis/submodules/altera_reset_controller.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_reset_controller.v" 61 -1 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { system:inst_cpu|altera_reset_controller:rst_controller|merged_reset~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 7344 8336 9085 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1 1394837336617 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "" 0 -1 1394837338153 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1 1394837338165 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1 1394837338166 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "" 0 -1 1394837338179 ""} +{ "Warning" "WFSAC_FSAC_IGNORED_FAST_REGISTER_IO_ASSIGNMENTS" "" "Ignoring invalid fast I/O register assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 176250 "Ignoring invalid fast I/O register assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "" 0 -1 1394837340701 ""} +{ "Warning" "WFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS" "" "Ignoring some wildcard destinations of fast I/O register assignments" { { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Enable Register ON oe " "Wildcard assignment \"Fast Output Enable Register=ON\" to \"oe\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1394837340702 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[9\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[9\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1394837340702 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[8\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[8\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1394837340702 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[7\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[7\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1394837340702 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[6\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[6\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1394837340702 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[5\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[5\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1394837340702 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[4\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[4\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1394837340702 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[3\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[3\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1394837340702 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[2\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[2\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1394837340702 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[1\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[1\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1394837340702 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[15\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[15\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1394837340702 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[14\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[14\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1394837340702 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[13\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[13\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1394837340702 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[12\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[12\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1394837340702 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[11\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[11\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1394837340702 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[10\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[10\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1394837340702 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[0\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[0\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1394837340702 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_cmd\[2\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_cmd\[2\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1394837340702 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_cmd\[1\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_cmd\[1\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1394837340702 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_cmd\[0\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_cmd\[0\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1394837340702 ""} } { } 0 176251 "Ignoring some wildcard destinations of fast I/O register assignments" 0 0 "" 0 -1 1394837340702 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "" 0 -1 1394837340703 ""} +{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "" 0 -1 1394837340715 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "" 0 -1 1394837342289 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NUM_REGISTERS_PACKED_INTO_ATOM_TYPE" "10 EC " "Packed 10 registers into blocks of type EC" { } { } 1 176218 "Packed %1!d! registers into blocks of type %2!s!" 0 0 "" 0 -1 1394837343799 ""} { "Extra Info" "IFSAC_NUM_REGISTERS_PACKED_INTO_ATOM_TYPE" "64 Embedded multiplier block " "Packed 64 registers into blocks of type Embedded multiplier block" { } { } 1 176218 "Packed %1!d! registers into blocks of type %2!s!" 0 0 "" 0 -1 1394837343799 ""} { "Extra Info" "IFSAC_NUM_REGISTERS_PACKED_INTO_ATOM_TYPE" "16 I/O Input Buffer " "Packed 16 registers into blocks of type I/O Input Buffer" { } { } 1 176218 "Packed %1!d! registers into blocks of type %2!s!" 0 0 "" 0 -1 1394837343799 ""} { "Extra Info" "IFSAC_NUM_REGISTERS_PACKED_INTO_ATOM_TYPE" "53 I/O Output Buffer " "Packed 53 registers into blocks of type I/O Output Buffer" { } { } 1 176218 "Packed %1!d! registers into blocks of type %2!s!" 0 0 "" 0 -1 1394837343799 ""} { "Extra Info" "IFSAC_NUM_REGISTERS_DUPLICATED" "66 " "Created 66 register duplicates" { } { } 1 176220 "Created %1!d! register duplicates" 0 0 "" 0 -1 1394837343799 ""} } { } 0 176235 "Finished register packing" 0 0 "" 0 -1 1394837343799 ""} +{ "Warning" "WCUT_PLL_CLK_FEEDS_NON_DEDICATED_IO" "pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|pll1 clk\[1\] DRAM_CLK~output " "PLL \"pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|pll1\" output port clk\[1\] feeds output pin \"DRAM_CLK~output\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" { } { { "db/pll_sys_altpll.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/pll_sys_altpll.v" 45 -1 0 } } { "altpll.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altpll.tdf" 897 0 0 } } { "pll_sys.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/pll_sys.vhd" 154 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 149 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 61 0 0 } } } 0 15064 "PLL \"%1!s!\" output port %2!s! feeds output pin \"%3!s!\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" 0 0 "" 0 -1 1394837343945 ""} +{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_CS_N " "Node \"ADC_CS_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1394837344074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SADDR " "Node \"ADC_SADDR\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SADDR" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1394837344074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SCLK " "Node \"ADC_SCLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1394837344074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDAT " "Node \"ADC_SDAT\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1394837344074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0_IN\[0\] " "Node \"GPIO_0_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1394837344074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0_IN\[1\] " "Node \"GPIO_0_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1394837344074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1_IN\[0\] " "Node \"GPIO_1_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1394837344074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1_IN\[1\] " "Node \"GPIO_1_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1394837344074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[0\] " "Node \"GPIO_2\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1394837344074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[10\] " "Node \"GPIO_2\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1394837344074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[11\] " "Node \"GPIO_2\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1394837344074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[12\] " "Node \"GPIO_2\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1394837344074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[1\] " "Node \"GPIO_2\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1394837344074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[2\] " "Node \"GPIO_2\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1394837344074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[3\] " "Node \"GPIO_2\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1394837344074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[4\] " "Node \"GPIO_2\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1394837344074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[5\] " "Node \"GPIO_2\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1394837344074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[6\] " "Node \"GPIO_2\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1394837344074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[7\] " "Node \"GPIO_2\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1394837344074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[8\] " "Node \"GPIO_2\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1394837344074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[9\] " "Node \"GPIO_2\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1394837344074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[0\] " "Node \"GPIO_2_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1394837344074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[1\] " "Node \"GPIO_2_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1394837344074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[2\] " "Node \"GPIO_2_IN\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1394837344074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "G_SENSOR_CS_N " "Node \"G_SENSOR_CS_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "G_SENSOR_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1394837344074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "G_SENSOR_INT " "Node \"G_SENSOR_INT\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "G_SENSOR_INT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1394837344074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SCLK " "Node \"I2C_SCLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "I2C_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1394837344074 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SDAT " "Node \"I2C_SDAT\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1394837344074 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "" 0 -1 1394837344074 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:11 " "Fitter preparation operations ending: elapsed time is 00:00:11" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1 1394837344076 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "" 0 -1 1394837345946 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:02 " "Fitter placement preparation operations ending: elapsed time is 00:00:02" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1 1394837347518 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "" 0 -1 1394837347561 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "" 0 -1 1394837354789 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:07 " "Fitter placement operations ending: elapsed time is 00:00:07" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 -1 1394837354789 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "" 0 -1 1394837356580 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "6 " "Router estimated average interconnect usage is 6% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "29 X21_Y11 X31_Y22 " "Router estimated peak interconnect usage is 29% of the available device resources in the region that extends from location X21_Y11 to location X31_Y22" { } { { "loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 1 { 0 "Router estimated peak interconnect usage is 29% of the available device resources in the region that extends from location X21_Y11 to location X31_Y22"} { { 11 { 0 "Router estimated peak interconnect usage is 29% of the available device resources in the region that extends from location X21_Y11 to location X31_Y22"} 21 11 11 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1 1394837361050 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1 1394837361050 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:08 " "Fitter routing operations ending: elapsed time is 00:00:08" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 -1 1394837365276 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 -1 1394837365279 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 -1 1394837365279 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "" 0 -1 1394837365279 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "" 0 -1 1394837365514 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "" 0 -1 1394837366168 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "" 0 -1 1394837366229 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "" 0 -1 1394837366931 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:04 " "Fitter post-fit operations ending: elapsed time is 00:00:04" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "" 0 -1 1394837369086 ""} +{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "" 0 -1 1394837370111 ""} +{ "Warning" "WFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE" "68 " "Following 68 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[2\] a permanently disabled " "Pin GPIO_0\[2\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[2] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[2\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 307 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394837370166 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[3\] a permanently disabled " "Pin GPIO_0\[3\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[3] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[3\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 308 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394837370166 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[4\] a permanently disabled " "Pin GPIO_0\[4\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[4] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[4\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 309 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394837370166 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[5\] a permanently disabled " "Pin GPIO_0\[5\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[5] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[5\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 310 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394837370166 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[6\] a permanently disabled " "Pin GPIO_0\[6\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[6] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[6\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 311 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394837370166 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[7\] a permanently disabled " "Pin GPIO_0\[7\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[7] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[7\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 312 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394837370166 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[8\] a permanently disabled " "Pin GPIO_0\[8\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[8] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[8\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 313 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394837370166 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[9\] a permanently disabled " "Pin GPIO_0\[9\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[9] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[9\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 314 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394837370166 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[10\] a permanently disabled " "Pin GPIO_0\[10\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[10] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[10\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 315 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394837370166 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[11\] a permanently disabled " "Pin GPIO_0\[11\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[11] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[11\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 316 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394837370166 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[12\] a permanently disabled " "Pin GPIO_0\[12\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[12] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[12\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 317 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394837370166 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[13\] a permanently disabled " "Pin GPIO_0\[13\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[13] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[13\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 318 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394837370166 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[14\] a permanently disabled " "Pin GPIO_0\[14\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[14] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[14\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 319 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394837370166 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[15\] a permanently disabled " "Pin GPIO_0\[15\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[15] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[15\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 320 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394837370166 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[16\] a permanently disabled " "Pin GPIO_0\[16\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[16] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[16\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[16] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 321 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394837370166 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[17\] a permanently disabled " "Pin GPIO_0\[17\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[17] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[17\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[17] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 322 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394837370166 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[18\] a permanently disabled " "Pin GPIO_0\[18\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[18] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[18\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[18] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 323 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394837370166 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[19\] a permanently disabled " "Pin GPIO_0\[19\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[19] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[19\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[19] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 324 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394837370166 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[20\] a permanently disabled " "Pin GPIO_0\[20\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[20] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[20\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[20] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 325 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394837370166 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[21\] a permanently disabled " "Pin GPIO_0\[21\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[21] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[21\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[21] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 326 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394837370166 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[22\] a permanently disabled " "Pin GPIO_0\[22\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[22] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[22\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[22] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 327 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394837370166 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[23\] a permanently disabled " "Pin GPIO_0\[23\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[23] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[23\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[23] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 328 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394837370166 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[24\] a permanently disabled " "Pin GPIO_0\[24\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[24] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[24\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[24] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 329 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394837370166 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[25\] a permanently disabled " "Pin GPIO_0\[25\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[25] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[25\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[25] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 330 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394837370166 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[26\] a permanently disabled " "Pin GPIO_0\[26\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[26] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[26\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[26] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 331 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394837370166 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[27\] a permanently disabled " "Pin GPIO_0\[27\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[27] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[27\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[27] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 332 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394837370166 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[28\] a permanently disabled " "Pin GPIO_0\[28\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[28] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[28\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[28] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 333 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394837370166 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[29\] a permanently disabled " "Pin GPIO_0\[29\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[29] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[29\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[29] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 334 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394837370166 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[30\] a permanently disabled " "Pin GPIO_0\[30\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[30] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[30\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[30] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 335 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394837370166 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[31\] a permanently disabled " "Pin GPIO_0\[31\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[31] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[31\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[31] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 336 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394837370166 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[32\] a permanently disabled " "Pin GPIO_0\[32\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[32] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[32\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[32] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 337 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394837370166 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[33\] a permanently disabled " "Pin GPIO_0\[33\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[33] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[33\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[33] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 338 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394837370166 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[0\] a permanently disabled " "Pin GPIO_1\[0\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[0] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[0\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 339 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394837370166 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[1\] a permanently disabled " "Pin GPIO_1\[1\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[1] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[1\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 340 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394837370166 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[2\] a permanently disabled " "Pin GPIO_1\[2\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[2] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[2\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 341 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394837370166 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[3\] a permanently disabled " "Pin GPIO_1\[3\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[3] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[3\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 342 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394837370166 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[4\] a permanently disabled " "Pin GPIO_1\[4\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[4] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[4\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 343 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394837370166 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[5\] a permanently disabled " "Pin GPIO_1\[5\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[5] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[5\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 344 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394837370166 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[6\] a permanently disabled " "Pin GPIO_1\[6\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[6] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[6\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 345 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394837370166 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[7\] a permanently disabled " "Pin GPIO_1\[7\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[7] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[7\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 346 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394837370166 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[8\] a permanently disabled " "Pin GPIO_1\[8\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[8] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[8\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 347 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394837370166 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[9\] a permanently disabled " "Pin GPIO_1\[9\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[9] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[9\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 348 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394837370166 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[10\] a permanently disabled " "Pin GPIO_1\[10\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[10] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[10\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 349 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394837370166 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[11\] a permanently disabled " "Pin GPIO_1\[11\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[11] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[11\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 350 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394837370166 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[13\] a permanently disabled " "Pin GPIO_1\[13\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[13] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[13\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 351 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394837370166 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[14\] a permanently disabled " "Pin GPIO_1\[14\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[14] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[14\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 352 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394837370166 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[15\] a permanently disabled " "Pin GPIO_1\[15\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[15] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[15\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 353 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394837370166 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[16\] a permanently disabled " "Pin GPIO_1\[16\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[16] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[16\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[16] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 354 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394837370166 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[17\] a permanently disabled " "Pin GPIO_1\[17\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[17] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[17\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[17] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 355 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394837370166 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[18\] a permanently disabled " "Pin GPIO_1\[18\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[18] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[18\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[18] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 356 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394837370166 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[19\] a permanently disabled " "Pin GPIO_1\[19\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[19] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[19\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[19] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 357 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394837370166 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[20\] a permanently disabled " "Pin GPIO_1\[20\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[20] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[20\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[20] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 358 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394837370166 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[21\] a permanently disabled " "Pin GPIO_1\[21\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[21] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[21\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[21] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 359 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394837370166 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[22\] a permanently disabled " "Pin GPIO_1\[22\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[22] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[22\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[22] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 360 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394837370166 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[23\] a permanently disabled " "Pin GPIO_1\[23\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[23] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[23\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[23] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 361 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394837370166 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[25\] a permanently disabled " "Pin GPIO_1\[25\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[25] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[25\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[25] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 362 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394837370166 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[27\] a permanently disabled " "Pin GPIO_1\[27\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[27] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[27\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[27] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 363 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394837370166 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[28\] a permanently disabled " "Pin GPIO_1\[28\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[28] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[28\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[28] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 364 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394837370166 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[29\] a permanently disabled " "Pin GPIO_1\[29\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[29] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[29\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[29] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 365 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394837370166 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[30\] a permanently disabled " "Pin GPIO_1\[30\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[30] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[30\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[30] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 366 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394837370166 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[31\] a permanently disabled " "Pin GPIO_1\[31\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[31] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[31\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[31] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 367 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394837370166 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[32\] a permanently disabled " "Pin GPIO_1\[32\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[32] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[32\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[32] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 368 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394837370166 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[33\] a permanently disabled " "Pin GPIO_1\[33\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[33] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[33\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[33] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 369 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394837370166 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[0\] a permanently enabled " "Pin GPIO_0\[0\] has a permanently enabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[0] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[0\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 255 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394837370166 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[1\] a permanently disabled " "Pin GPIO_0\[1\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[1] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[1\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 259 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394837370166 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[12\] a permanently enabled " "Pin GPIO_1\[12\] has a permanently enabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[12] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[12\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 256 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394837370166 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[24\] a permanently disabled " "Pin GPIO_1\[24\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[24] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[24\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[24] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 258 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394837370166 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[26\] a permanently enabled " "Pin GPIO_1\[26\] has a permanently enabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[26] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[26\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[26] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 257 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394837370166 ""} } { } 0 169064 "Following %1!d! pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results" 0 0 "" 0 -1 1394837370166 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/output_files/de0_nano_system.fit.smsg " "Generated suppressed messages file C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/output_files/de0_nano_system.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "" 0 -1 1394837370731 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 36 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 36 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1130 " "Peak virtual memory: 1130 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1 1394837372253 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Mar 14 16:49:32 2014 " "Processing ended: Fri Mar 14 16:49:32 2014" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1 1394837372253 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:40 " "Elapsed time: 00:00:40" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1 1394837372253 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:49 " "Total CPU time (on all processors): 00:00:49" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1 1394837372253 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1 1394837372253 ""} diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.hier_info b/MCTEST/DE0-nano-HD/db/de0_nano_system.hier_info new file mode 100644 index 00000000..e0e58d82 --- /dev/null +++ b/MCTEST/DE0-nano-HD/db/de0_nano_system.hier_info @@ -0,0 +1,57185 @@ +|de0_nano_system +CLOCK_50 => pll_sys:inst_pll_sys.inclk0 +DRAM_CLK <= pll_sys:inst_pll_sys.c1 +DRAM_CKE <= system:inst_cpu.sdram_cke +DRAM_CS_N <= system:inst_cpu.sdram_cs_n +DRAM_RAS_N <= system:inst_cpu.sdram_ras_n +DRAM_CAS_N <= system:inst_cpu.sdram_cas_n +DRAM_WE_N <= system:inst_cpu.sdram_we_n +DRAM_DQ[0] <> system:inst_cpu.sdram_dq[0] +DRAM_DQ[1] <> system:inst_cpu.sdram_dq[1] +DRAM_DQ[2] <> system:inst_cpu.sdram_dq[2] +DRAM_DQ[3] <> system:inst_cpu.sdram_dq[3] +DRAM_DQ[4] <> system:inst_cpu.sdram_dq[4] +DRAM_DQ[5] <> system:inst_cpu.sdram_dq[5] +DRAM_DQ[6] <> system:inst_cpu.sdram_dq[6] +DRAM_DQ[7] <> system:inst_cpu.sdram_dq[7] +DRAM_DQ[8] <> system:inst_cpu.sdram_dq[8] +DRAM_DQ[9] <> system:inst_cpu.sdram_dq[9] +DRAM_DQ[10] <> system:inst_cpu.sdram_dq[10] +DRAM_DQ[11] <> system:inst_cpu.sdram_dq[11] +DRAM_DQ[12] <> system:inst_cpu.sdram_dq[12] +DRAM_DQ[13] <> system:inst_cpu.sdram_dq[13] +DRAM_DQ[14] <> system:inst_cpu.sdram_dq[14] +DRAM_DQ[15] <> system:inst_cpu.sdram_dq[15] +DRAM_DQM[0] <= system:inst_cpu.sdram_dqm[0] +DRAM_DQM[1] <= system:inst_cpu.sdram_dqm[1] +DRAM_ADDR[0] <= system:inst_cpu.sdram_addr[0] +DRAM_ADDR[1] <= system:inst_cpu.sdram_addr[1] +DRAM_ADDR[2] <= system:inst_cpu.sdram_addr[2] +DRAM_ADDR[3] <= system:inst_cpu.sdram_addr[3] +DRAM_ADDR[4] <= system:inst_cpu.sdram_addr[4] +DRAM_ADDR[5] <= system:inst_cpu.sdram_addr[5] +DRAM_ADDR[6] <= system:inst_cpu.sdram_addr[6] +DRAM_ADDR[7] <= system:inst_cpu.sdram_addr[7] +DRAM_ADDR[8] <= system:inst_cpu.sdram_addr[8] +DRAM_ADDR[9] <= system:inst_cpu.sdram_addr[9] +DRAM_ADDR[10] <= system:inst_cpu.sdram_addr[10] +DRAM_ADDR[11] <= system:inst_cpu.sdram_addr[11] +DRAM_ADDR[12] <= system:inst_cpu.sdram_addr[12] +DRAM_BA[0] <= system:inst_cpu.sdram_ba[0] +DRAM_BA[1] <= system:inst_cpu.sdram_ba[1] +LED[0] <= system:inst_cpu.pio_led_export[0] +LED[1] <= system:inst_cpu.pio_led_export[1] +LED[2] <= system:inst_cpu.pio_led_export[2] +LED[3] <= system:inst_cpu.pio_led_export[3] +LED[4] <= system:inst_cpu.pio_led_export[4] +LED[5] <= system:inst_cpu.pio_led_export[5] +LED[6] <= system:inst_cpu.pio_led_export[6] +LED[7] <= heartbeat:inst_heartbeat.counter_out +KEY[0] => system:inst_cpu.pio_key_export[0] +KEY[1] => system:inst_cpu.pio_key_export[1] +SW[0] => system:inst_cpu.pio_sw_export[0] +SW[1] => system:inst_cpu.pio_sw_export[1] +SW[2] => system:inst_cpu.pio_sw_export[2] +SW[3] => system:inst_cpu.pio_sw_export[3] +GPIO_0[0] <> GPIO_0[0] +GPIO_0[2] <> +GPIO_0[3] <> +GPIO_0[4] <> +GPIO_0[5] <> +GPIO_0[6] <> +GPIO_0[7] <> +GPIO_0[8] <> +GPIO_0[9] <> +GPIO_0[10] <> +GPIO_0[11] <> +GPIO_0[12] <> +GPIO_0[13] <> +GPIO_0[14] <> +GPIO_0[15] <> +GPIO_0[16] <> +GPIO_0[17] <> +GPIO_0[18] <> +GPIO_0[19] <> +GPIO_0[20] <> +GPIO_0[21] <> +GPIO_0[22] <> +GPIO_0[23] <> +GPIO_0[24] <> +GPIO_0[25] <> +GPIO_0[26] <> +GPIO_0[27] <> +GPIO_0[28] <> +GPIO_0[29] <> +GPIO_0[30] <> +GPIO_0[31] <> +GPIO_0[32] <> +GPIO_0[33] <> +GPIO_1[0] <> +GPIO_1[1] <> +GPIO_1[2] <> +GPIO_1[3] <> +GPIO_1[4] <> +GPIO_1[5] <> +GPIO_1[6] <> +GPIO_1[7] <> +GPIO_1[8] <> +GPIO_1[9] <> +GPIO_1[10] <> +GPIO_1[11] <> +GPIO_1[12] <> GPIO_1[12] +GPIO_1[13] <> +GPIO_1[14] <> +GPIO_1[15] <> +GPIO_1[16] <> +GPIO_1[17] <> +GPIO_1[18] <> +GPIO_1[19] <> +GPIO_1[20] <> +GPIO_1[21] <> +GPIO_1[22] <> +GPIO_1[23] <> +GPIO_1[25] <> +GPIO_1[26] <> GPIO_1[26] +GPIO_1[27] <> +GPIO_1[28] <> +GPIO_1[29] <> +GPIO_1[30] <> +GPIO_1[31] <> +GPIO_1[32] <> +GPIO_1[33] <> + + +|de0_nano_system|pll_sys:inst_pll_sys +inclk0 => altpll:altpll_component.inclk[0] +c0 <= altpll:altpll_component.clk[0] +c1 <= altpll:altpll_component.clk[1] +c2 <= altpll:altpll_component.clk[2] +locked <= altpll:altpll_component.locked + + +|de0_nano_system|pll_sys:inst_pll_sys|altpll:altpll_component +inclk[0] => pll_sys_altpll:auto_generated.inclk[0] +inclk[1] => pll_sys_altpll:auto_generated.inclk[1] +fbin => ~NO_FANOUT~ +pllena => ~NO_FANOUT~ +clkswitch => ~NO_FANOUT~ +areset => ~NO_FANOUT~ +pfdena => ~NO_FANOUT~ +clkena[0] => ~NO_FANOUT~ +clkena[1] => ~NO_FANOUT~ +clkena[2] => ~NO_FANOUT~ +clkena[3] => ~NO_FANOUT~ +clkena[4] => ~NO_FANOUT~ +clkena[5] => ~NO_FANOUT~ +extclkena[0] => ~NO_FANOUT~ +extclkena[1] => ~NO_FANOUT~ +extclkena[2] => ~NO_FANOUT~ +extclkena[3] => ~NO_FANOUT~ +scanclk => ~NO_FANOUT~ +scanclkena => ~NO_FANOUT~ +scanaclr => ~NO_FANOUT~ +scanread => ~NO_FANOUT~ +scanwrite => ~NO_FANOUT~ +scandata => ~NO_FANOUT~ +phasecounterselect[0] => ~NO_FANOUT~ +phasecounterselect[1] => ~NO_FANOUT~ +phasecounterselect[2] => ~NO_FANOUT~ +phasecounterselect[3] => ~NO_FANOUT~ +phaseupdown => ~NO_FANOUT~ +phasestep => ~NO_FANOUT~ +configupdate => ~NO_FANOUT~ +fbmimicbidir <> +clk[0] <= clk[0].DB_MAX_OUTPUT_PORT_TYPE +clk[1] <= clk[1].DB_MAX_OUTPUT_PORT_TYPE +clk[2] <= clk[2].DB_MAX_OUTPUT_PORT_TYPE +clk[3] <= clk[3].DB_MAX_OUTPUT_PORT_TYPE +clk[4] <= clk[4].DB_MAX_OUTPUT_PORT_TYPE +extclk[0] <= +extclk[1] <= +extclk[2] <= +extclk[3] <= +clkbad[0] <= +clkbad[1] <= +enable1 <= +enable0 <= +activeclock <= +clkloss <= +locked <= pll_sys_altpll:auto_generated.locked +scandataout <= +scandone <= +sclkout0 <= +sclkout1 <= +phasedone <= +vcooverrange <= +vcounderrange <= +fbout <= +fref <= +icdrclk <= + + +|de0_nano_system|pll_sys:inst_pll_sys|altpll:altpll_component|pll_sys_altpll:auto_generated +clk[0] <= pll1.CLK +clk[1] <= pll1.CLK1 +clk[2] <= pll1.CLK2 +clk[3] <= pll1.CLK3 +clk[4] <= pll1.CLK4 +inclk[0] => pll1.CLK +inclk[1] => pll1.CLK1 +locked <= pll1.LOCKED + + +|de0_nano_system|heartbeat:inst_heartbeat +clk => counter_data[0].CLK +clk => counter_data[1].CLK +clk => counter_data[2].CLK +clk => counter_data[3].CLK +clk => counter_data[4].CLK +clk => counter_data[5].CLK +clk => counter_data[6].CLK +clk => counter_data[7].CLK +clk => counter_data[8].CLK +clk => counter_data[9].CLK +clk => counter_data[10].CLK +clk => counter_data[11].CLK +clk => counter_data[12].CLK +clk => counter_data[13].CLK +clk => counter_data[14].CLK +clk => counter_data[15].CLK +clk => counter_data[16].CLK +clk => counter_data[17].CLK +clk => counter_data[18].CLK +clk => counter_data[19].CLK +clk => counter_data[20].CLK +clk => counter_data[21].CLK +clk => counter_data[22].CLK +clk => counter_data[23].CLK +clk => counter_data[24].CLK +clk => counter_data[25].CLK +clk => counter_data[26].CLK +clk => counter_data[27].CLK +clk => counter_data[28].CLK +clk => counter_data[29].CLK +clk => counter_data[30].CLK +clk => counter_data[31].CLK +counter_out <= counter_data[21].DB_MAX_OUTPUT_PORT_TYPE + + +|de0_nano_system|system:inst_cpu +sdram_addr[0] <= system_sdram:sdram.zs_addr +sdram_addr[1] <= system_sdram:sdram.zs_addr +sdram_addr[2] <= system_sdram:sdram.zs_addr +sdram_addr[3] <= system_sdram:sdram.zs_addr +sdram_addr[4] <= system_sdram:sdram.zs_addr +sdram_addr[5] <= system_sdram:sdram.zs_addr +sdram_addr[6] <= system_sdram:sdram.zs_addr +sdram_addr[7] <= system_sdram:sdram.zs_addr +sdram_addr[8] <= system_sdram:sdram.zs_addr +sdram_addr[9] <= system_sdram:sdram.zs_addr +sdram_addr[10] <= system_sdram:sdram.zs_addr +sdram_addr[11] <= system_sdram:sdram.zs_addr +sdram_addr[12] <= system_sdram:sdram.zs_addr +sdram_ba[0] <= system_sdram:sdram.zs_ba +sdram_ba[1] <= system_sdram:sdram.zs_ba +sdram_cas_n <= system_sdram:sdram.zs_cas_n +sdram_cke <= system_sdram:sdram.zs_cke +sdram_cs_n <= system_sdram:sdram.zs_cs_n +sdram_dq[0] <> system_sdram:sdram.zs_dq +sdram_dq[1] <> system_sdram:sdram.zs_dq +sdram_dq[2] <> system_sdram:sdram.zs_dq +sdram_dq[3] <> system_sdram:sdram.zs_dq +sdram_dq[4] <> system_sdram:sdram.zs_dq +sdram_dq[5] <> system_sdram:sdram.zs_dq +sdram_dq[6] <> system_sdram:sdram.zs_dq +sdram_dq[7] <> system_sdram:sdram.zs_dq +sdram_dq[8] <> system_sdram:sdram.zs_dq +sdram_dq[9] <> system_sdram:sdram.zs_dq +sdram_dq[10] <> system_sdram:sdram.zs_dq +sdram_dq[11] <> system_sdram:sdram.zs_dq +sdram_dq[12] <> system_sdram:sdram.zs_dq +sdram_dq[13] <> system_sdram:sdram.zs_dq +sdram_dq[14] <> system_sdram:sdram.zs_dq +sdram_dq[15] <> system_sdram:sdram.zs_dq +sdram_dqm[0] <= system_sdram:sdram.zs_dqm +sdram_dqm[1] <= system_sdram:sdram.zs_dqm +sdram_ras_n <= system_sdram:sdram.zs_ras_n +sdram_we_n <= system_sdram:sdram.zs_we_n +pio_led_export[0] <= system_pio_led:pio_led.out_port +pio_led_export[1] <= system_pio_led:pio_led.out_port +pio_led_export[2] <= system_pio_led:pio_led.out_port +pio_led_export[3] <= system_pio_led:pio_led.out_port +pio_led_export[4] <= system_pio_led:pio_led.out_port +pio_led_export[5] <= system_pio_led:pio_led.out_port +pio_led_export[6] <= system_pio_led:pio_led.out_port +rs232_motor_RXD => rs232_motor_RXD.IN1 +rs232_motor_TXD <= system_rs232_motor:rs232_motor.UART_TXD +pio_sw_export[0] => pio_sw_export[0].IN1 +pio_sw_export[1] => pio_sw_export[1].IN1 +pio_sw_export[2] => pio_sw_export[2].IN1 +pio_sw_export[3] => pio_sw_export[3].IN1 +pio_motor_rst_export <= system_pio_motor_rst:pio_motor_rst.out_port +uart_0_rxd => uart_0_rxd.IN1 +uart_0_txd <= system_uart_0:uart_0.txd +reset_reset_n => _.IN1 +clk_clk => clk_clk.IN85 +pio_key_export[0] => pio_key_export[0].IN1 +pio_key_export[1] => pio_key_export[1].IN1 + + +|de0_nano_system|system:inst_cpu|system_cpu:cpu +clk => clk.IN11 +d_irq[0] => ~NO_FANOUT~ +d_irq[1] => A_ipending_reg_irq1_nxt.IN0 +d_irq[2] => ~NO_FANOUT~ +d_irq[3] => ~NO_FANOUT~ +d_irq[4] => A_ipending_reg_irq4_nxt.IN0 +d_irq[5] => A_ipending_reg_irq5_nxt.IN0 +d_irq[6] => ~NO_FANOUT~ +d_irq[7] => ~NO_FANOUT~ +d_irq[8] => ~NO_FANOUT~ +d_irq[9] => ~NO_FANOUT~ +d_irq[10] => ~NO_FANOUT~ +d_irq[11] => ~NO_FANOUT~ +d_irq[12] => ~NO_FANOUT~ +d_irq[13] => ~NO_FANOUT~ +d_irq[14] => A_ipending_reg_irq14_nxt.IN0 +d_irq[15] => ~NO_FANOUT~ +d_irq[16] => ~NO_FANOUT~ +d_irq[17] => ~NO_FANOUT~ +d_irq[18] => ~NO_FANOUT~ +d_irq[19] => ~NO_FANOUT~ +d_irq[20] => ~NO_FANOUT~ +d_irq[21] => ~NO_FANOUT~ +d_irq[22] => ~NO_FANOUT~ +d_irq[23] => ~NO_FANOUT~ +d_irq[24] => ~NO_FANOUT~ +d_irq[25] => ~NO_FANOUT~ +d_irq[26] => ~NO_FANOUT~ +d_irq[27] => ~NO_FANOUT~ +d_irq[28] => ~NO_FANOUT~ +d_irq[29] => ~NO_FANOUT~ +d_irq[30] => ~NO_FANOUT~ +d_irq[31] => ~NO_FANOUT~ +d_readdata[0] => d_readdata_d1[0].DATAIN +d_readdata[1] => d_readdata_d1[1].DATAIN +d_readdata[2] => d_readdata_d1[2].DATAIN +d_readdata[3] => d_readdata_d1[3].DATAIN +d_readdata[4] => d_readdata_d1[4].DATAIN +d_readdata[5] => d_readdata_d1[5].DATAIN +d_readdata[6] => d_readdata_d1[6].DATAIN +d_readdata[7] => d_readdata_d1[7].DATAIN +d_readdata[8] => d_readdata_d1[8].DATAIN +d_readdata[9] => d_readdata_d1[9].DATAIN +d_readdata[10] => d_readdata_d1[10].DATAIN +d_readdata[11] => d_readdata_d1[11].DATAIN +d_readdata[12] => d_readdata_d1[12].DATAIN +d_readdata[13] => d_readdata_d1[13].DATAIN +d_readdata[14] => d_readdata_d1[14].DATAIN +d_readdata[15] => d_readdata_d1[15].DATAIN +d_readdata[16] => d_readdata_d1[16].DATAIN +d_readdata[17] => d_readdata_d1[17].DATAIN +d_readdata[18] => d_readdata_d1[18].DATAIN +d_readdata[19] => d_readdata_d1[19].DATAIN +d_readdata[20] => d_readdata_d1[20].DATAIN +d_readdata[21] => d_readdata_d1[21].DATAIN +d_readdata[22] => d_readdata_d1[22].DATAIN +d_readdata[23] => d_readdata_d1[23].DATAIN +d_readdata[24] => d_readdata_d1[24].DATAIN +d_readdata[25] => d_readdata_d1[25].DATAIN +d_readdata[26] => d_readdata_d1[26].DATAIN +d_readdata[27] => d_readdata_d1[27].DATAIN +d_readdata[28] => d_readdata_d1[28].DATAIN +d_readdata[29] => d_readdata_d1[29].DATAIN +d_readdata[30] => d_readdata_d1[30].DATAIN +d_readdata[31] => d_readdata_d1[31].DATAIN +d_readdatavalid => d_readdatavalid_d1.DATAIN +d_waitrequest => d_write_nxt.IN1 +d_waitrequest => d_read_nxt.IN1 +d_waitrequest => A_dc_wb_update_av_writedata.IN1 +d_waitrequest => A_dc_wr_last_transfer.IN1 +d_waitrequest => av_wr_data_transfer.IN0 +d_waitrequest => av_rd_addr_accepted.IN0 +d_waitrequest => av_addr_accepted.IN1 +i_readdata[0] => i_readdata_d1[0].DATAIN +i_readdata[1] => i_readdata_d1[1].DATAIN +i_readdata[2] => i_readdata_d1[2].DATAIN +i_readdata[3] => i_readdata_d1[3].DATAIN +i_readdata[4] => i_readdata_d1[4].DATAIN +i_readdata[5] => i_readdata_d1[5].DATAIN +i_readdata[6] => i_readdata_d1[6].DATAIN +i_readdata[7] => i_readdata_d1[7].DATAIN +i_readdata[8] => i_readdata_d1[8].DATAIN +i_readdata[9] => i_readdata_d1[9].DATAIN +i_readdata[10] => i_readdata_d1[10].DATAIN +i_readdata[11] => i_readdata_d1[11].DATAIN +i_readdata[12] => i_readdata_d1[12].DATAIN +i_readdata[13] => i_readdata_d1[13].DATAIN +i_readdata[14] => i_readdata_d1[14].DATAIN +i_readdata[15] => i_readdata_d1[15].DATAIN +i_readdata[16] => i_readdata_d1[16].DATAIN +i_readdata[17] => i_readdata_d1[17].DATAIN +i_readdata[18] => i_readdata_d1[18].DATAIN +i_readdata[19] => i_readdata_d1[19].DATAIN +i_readdata[20] => i_readdata_d1[20].DATAIN +i_readdata[21] => i_readdata_d1[21].DATAIN +i_readdata[22] => i_readdata_d1[22].DATAIN +i_readdata[23] => i_readdata_d1[23].DATAIN +i_readdata[24] => i_readdata_d1[24].DATAIN +i_readdata[25] => i_readdata_d1[25].DATAIN +i_readdata[26] => i_readdata_d1[26].DATAIN +i_readdata[27] => i_readdata_d1[27].DATAIN +i_readdata[28] => i_readdata_d1[28].DATAIN +i_readdata[29] => i_readdata_d1[29].DATAIN +i_readdata[30] => i_readdata_d1[30].DATAIN +i_readdata[31] => i_readdata_d1[31].DATAIN +i_readdatavalid => i_readdatavalid.IN1 +i_waitrequest => i_read_nxt.IN1 +i_waitrequest => ic_fill_req_accepted.IN0 +jtag_debug_module_address[0] => jtag_debug_module_address[0].IN1 +jtag_debug_module_address[1] => jtag_debug_module_address[1].IN1 +jtag_debug_module_address[2] => jtag_debug_module_address[2].IN1 +jtag_debug_module_address[3] => jtag_debug_module_address[3].IN1 +jtag_debug_module_address[4] => jtag_debug_module_address[4].IN1 +jtag_debug_module_address[5] => jtag_debug_module_address[5].IN1 +jtag_debug_module_address[6] => jtag_debug_module_address[6].IN1 +jtag_debug_module_address[7] => jtag_debug_module_address[7].IN1 +jtag_debug_module_address[8] => jtag_debug_module_address[8].IN1 +jtag_debug_module_begintransfer => jtag_debug_module_begintransfer.IN1 +jtag_debug_module_byteenable[0] => jtag_debug_module_byteenable[0].IN1 +jtag_debug_module_byteenable[1] => jtag_debug_module_byteenable[1].IN1 +jtag_debug_module_byteenable[2] => jtag_debug_module_byteenable[2].IN1 +jtag_debug_module_byteenable[3] => jtag_debug_module_byteenable[3].IN1 +jtag_debug_module_debugaccess => jtag_debug_module_debugaccess.IN1 +jtag_debug_module_select => jtag_debug_module_select.IN1 +jtag_debug_module_write => jtag_debug_module_write.IN1 +jtag_debug_module_writedata[0] => jtag_debug_module_writedata[0].IN1 +jtag_debug_module_writedata[1] => jtag_debug_module_writedata[1].IN1 +jtag_debug_module_writedata[2] => jtag_debug_module_writedata[2].IN1 +jtag_debug_module_writedata[3] => jtag_debug_module_writedata[3].IN1 +jtag_debug_module_writedata[4] => jtag_debug_module_writedata[4].IN1 +jtag_debug_module_writedata[5] => jtag_debug_module_writedata[5].IN1 +jtag_debug_module_writedata[6] => jtag_debug_module_writedata[6].IN1 +jtag_debug_module_writedata[7] => jtag_debug_module_writedata[7].IN1 +jtag_debug_module_writedata[8] => jtag_debug_module_writedata[8].IN1 +jtag_debug_module_writedata[9] => jtag_debug_module_writedata[9].IN1 +jtag_debug_module_writedata[10] => jtag_debug_module_writedata[10].IN1 +jtag_debug_module_writedata[11] => jtag_debug_module_writedata[11].IN1 +jtag_debug_module_writedata[12] => jtag_debug_module_writedata[12].IN1 +jtag_debug_module_writedata[13] => jtag_debug_module_writedata[13].IN1 +jtag_debug_module_writedata[14] => jtag_debug_module_writedata[14].IN1 +jtag_debug_module_writedata[15] => jtag_debug_module_writedata[15].IN1 +jtag_debug_module_writedata[16] => jtag_debug_module_writedata[16].IN1 +jtag_debug_module_writedata[17] => jtag_debug_module_writedata[17].IN1 +jtag_debug_module_writedata[18] => jtag_debug_module_writedata[18].IN1 +jtag_debug_module_writedata[19] => jtag_debug_module_writedata[19].IN1 +jtag_debug_module_writedata[20] => jtag_debug_module_writedata[20].IN1 +jtag_debug_module_writedata[21] => jtag_debug_module_writedata[21].IN1 +jtag_debug_module_writedata[22] => jtag_debug_module_writedata[22].IN1 +jtag_debug_module_writedata[23] => jtag_debug_module_writedata[23].IN1 +jtag_debug_module_writedata[24] => jtag_debug_module_writedata[24].IN1 +jtag_debug_module_writedata[25] => jtag_debug_module_writedata[25].IN1 +jtag_debug_module_writedata[26] => jtag_debug_module_writedata[26].IN1 +jtag_debug_module_writedata[27] => jtag_debug_module_writedata[27].IN1 +jtag_debug_module_writedata[28] => jtag_debug_module_writedata[28].IN1 +jtag_debug_module_writedata[29] => jtag_debug_module_writedata[29].IN1 +jtag_debug_module_writedata[30] => jtag_debug_module_writedata[30].IN1 +jtag_debug_module_writedata[31] => jtag_debug_module_writedata[31].IN1 +reset_n => reset_n.IN3 +d_address[0] <= d_address[0].DB_MAX_OUTPUT_PORT_TYPE +d_address[1] <= d_address[1].DB_MAX_OUTPUT_PORT_TYPE +d_address[2] <= d_address[2].DB_MAX_OUTPUT_PORT_TYPE +d_address[3] <= d_address[3].DB_MAX_OUTPUT_PORT_TYPE +d_address[4] <= d_address[4].DB_MAX_OUTPUT_PORT_TYPE +d_address[5] <= d_address[5].DB_MAX_OUTPUT_PORT_TYPE +d_address[6] <= d_address[6].DB_MAX_OUTPUT_PORT_TYPE +d_address[7] <= d_address[7].DB_MAX_OUTPUT_PORT_TYPE +d_address[8] <= d_address[8].DB_MAX_OUTPUT_PORT_TYPE +d_address[9] <= d_address[9].DB_MAX_OUTPUT_PORT_TYPE +d_address[10] <= d_address[10].DB_MAX_OUTPUT_PORT_TYPE +d_address[11] <= d_address[11].DB_MAX_OUTPUT_PORT_TYPE +d_address[12] <= d_address[12].DB_MAX_OUTPUT_PORT_TYPE +d_address[13] <= d_address[13].DB_MAX_OUTPUT_PORT_TYPE +d_address[14] <= d_address[14].DB_MAX_OUTPUT_PORT_TYPE +d_address[15] <= d_address[15].DB_MAX_OUTPUT_PORT_TYPE +d_address[16] <= d_address[16].DB_MAX_OUTPUT_PORT_TYPE +d_address[17] <= d_address[17].DB_MAX_OUTPUT_PORT_TYPE +d_address[18] <= d_address[18].DB_MAX_OUTPUT_PORT_TYPE +d_address[19] <= d_address[19].DB_MAX_OUTPUT_PORT_TYPE +d_address[20] <= d_address[20].DB_MAX_OUTPUT_PORT_TYPE +d_address[21] <= d_address[21].DB_MAX_OUTPUT_PORT_TYPE +d_address[22] <= d_address[22].DB_MAX_OUTPUT_PORT_TYPE +d_address[23] <= d_address[23].DB_MAX_OUTPUT_PORT_TYPE +d_address[24] <= d_address[24].DB_MAX_OUTPUT_PORT_TYPE +d_address[25] <= d_address[25].DB_MAX_OUTPUT_PORT_TYPE +d_byteenable[0] <= d_byteenable[0].DB_MAX_OUTPUT_PORT_TYPE +d_byteenable[1] <= d_byteenable[1].DB_MAX_OUTPUT_PORT_TYPE +d_byteenable[2] <= d_byteenable[2].DB_MAX_OUTPUT_PORT_TYPE +d_byteenable[3] <= d_byteenable[3].DB_MAX_OUTPUT_PORT_TYPE +d_read <= d_read.DB_MAX_OUTPUT_PORT_TYPE +d_write <= d_write.DB_MAX_OUTPUT_PORT_TYPE +d_writedata[0] <= d_writedata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +d_writedata[1] <= d_writedata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +d_writedata[2] <= d_writedata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +d_writedata[3] <= d_writedata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +d_writedata[4] <= d_writedata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +d_writedata[5] <= d_writedata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +d_writedata[6] <= d_writedata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +d_writedata[7] <= d_writedata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE +d_writedata[8] <= d_writedata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE +d_writedata[9] <= d_writedata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE +d_writedata[10] <= d_writedata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE +d_writedata[11] <= d_writedata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE +d_writedata[12] <= d_writedata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE +d_writedata[13] <= d_writedata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE +d_writedata[14] <= d_writedata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE +d_writedata[15] <= d_writedata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE +d_writedata[16] <= d_writedata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE +d_writedata[17] <= d_writedata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE +d_writedata[18] <= d_writedata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE +d_writedata[19] <= d_writedata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE +d_writedata[20] <= d_writedata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE +d_writedata[21] <= d_writedata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE +d_writedata[22] <= d_writedata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE +d_writedata[23] <= d_writedata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE +d_writedata[24] <= d_writedata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE +d_writedata[25] <= d_writedata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE +d_writedata[26] <= d_writedata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE +d_writedata[27] <= d_writedata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE +d_writedata[28] <= d_writedata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE +d_writedata[29] <= d_writedata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE +d_writedata[30] <= d_writedata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE +d_writedata[31] <= d_writedata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE +i_address[0] <= i_address[0].DB_MAX_OUTPUT_PORT_TYPE +i_address[1] <= i_address[1].DB_MAX_OUTPUT_PORT_TYPE +i_address[2] <= i_address[2].DB_MAX_OUTPUT_PORT_TYPE +i_address[3] <= i_address[3].DB_MAX_OUTPUT_PORT_TYPE +i_address[4] <= i_address[4].DB_MAX_OUTPUT_PORT_TYPE +i_address[5] <= ic_fill_line[0].DB_MAX_OUTPUT_PORT_TYPE +i_address[6] <= ic_fill_line[1].DB_MAX_OUTPUT_PORT_TYPE +i_address[7] <= ic_fill_line[2].DB_MAX_OUTPUT_PORT_TYPE +i_address[8] <= ic_fill_line[3].DB_MAX_OUTPUT_PORT_TYPE +i_address[9] <= ic_fill_line[4].DB_MAX_OUTPUT_PORT_TYPE +i_address[10] <= ic_fill_line[5].DB_MAX_OUTPUT_PORT_TYPE +i_address[11] <= ic_fill_line[6].DB_MAX_OUTPUT_PORT_TYPE +i_address[12] <= ic_fill_line[7].DB_MAX_OUTPUT_PORT_TYPE +i_address[13] <= i_address[13].DB_MAX_OUTPUT_PORT_TYPE +i_address[14] <= i_address[14].DB_MAX_OUTPUT_PORT_TYPE +i_address[15] <= i_address[15].DB_MAX_OUTPUT_PORT_TYPE +i_address[16] <= i_address[16].DB_MAX_OUTPUT_PORT_TYPE +i_address[17] <= i_address[17].DB_MAX_OUTPUT_PORT_TYPE +i_address[18] <= i_address[18].DB_MAX_OUTPUT_PORT_TYPE +i_address[19] <= i_address[19].DB_MAX_OUTPUT_PORT_TYPE +i_address[20] <= i_address[20].DB_MAX_OUTPUT_PORT_TYPE +i_address[21] <= i_address[21].DB_MAX_OUTPUT_PORT_TYPE +i_address[22] <= i_address[22].DB_MAX_OUTPUT_PORT_TYPE +i_address[23] <= i_address[23].DB_MAX_OUTPUT_PORT_TYPE +i_address[24] <= i_address[24].DB_MAX_OUTPUT_PORT_TYPE +i_address[25] <= i_address[25].DB_MAX_OUTPUT_PORT_TYPE +i_read <= i_read.DB_MAX_OUTPUT_PORT_TYPE +jtag_debug_module_debugaccess_to_roms <= system_cpu_nios2_oci:the_system_cpu_nios2_oci.jtag_debug_module_debugaccess_to_roms +jtag_debug_module_readdata[0] <= system_cpu_nios2_oci:the_system_cpu_nios2_oci.readdata +jtag_debug_module_readdata[1] <= system_cpu_nios2_oci:the_system_cpu_nios2_oci.readdata +jtag_debug_module_readdata[2] <= system_cpu_nios2_oci:the_system_cpu_nios2_oci.readdata +jtag_debug_module_readdata[3] <= system_cpu_nios2_oci:the_system_cpu_nios2_oci.readdata +jtag_debug_module_readdata[4] <= system_cpu_nios2_oci:the_system_cpu_nios2_oci.readdata +jtag_debug_module_readdata[5] <= system_cpu_nios2_oci:the_system_cpu_nios2_oci.readdata +jtag_debug_module_readdata[6] <= system_cpu_nios2_oci:the_system_cpu_nios2_oci.readdata +jtag_debug_module_readdata[7] <= system_cpu_nios2_oci:the_system_cpu_nios2_oci.readdata +jtag_debug_module_readdata[8] <= system_cpu_nios2_oci:the_system_cpu_nios2_oci.readdata +jtag_debug_module_readdata[9] <= system_cpu_nios2_oci:the_system_cpu_nios2_oci.readdata +jtag_debug_module_readdata[10] <= system_cpu_nios2_oci:the_system_cpu_nios2_oci.readdata +jtag_debug_module_readdata[11] <= system_cpu_nios2_oci:the_system_cpu_nios2_oci.readdata +jtag_debug_module_readdata[12] <= system_cpu_nios2_oci:the_system_cpu_nios2_oci.readdata +jtag_debug_module_readdata[13] <= system_cpu_nios2_oci:the_system_cpu_nios2_oci.readdata +jtag_debug_module_readdata[14] <= system_cpu_nios2_oci:the_system_cpu_nios2_oci.readdata +jtag_debug_module_readdata[15] <= system_cpu_nios2_oci:the_system_cpu_nios2_oci.readdata +jtag_debug_module_readdata[16] <= system_cpu_nios2_oci:the_system_cpu_nios2_oci.readdata +jtag_debug_module_readdata[17] <= system_cpu_nios2_oci:the_system_cpu_nios2_oci.readdata +jtag_debug_module_readdata[18] <= system_cpu_nios2_oci:the_system_cpu_nios2_oci.readdata +jtag_debug_module_readdata[19] <= system_cpu_nios2_oci:the_system_cpu_nios2_oci.readdata +jtag_debug_module_readdata[20] <= system_cpu_nios2_oci:the_system_cpu_nios2_oci.readdata +jtag_debug_module_readdata[21] <= system_cpu_nios2_oci:the_system_cpu_nios2_oci.readdata +jtag_debug_module_readdata[22] <= system_cpu_nios2_oci:the_system_cpu_nios2_oci.readdata +jtag_debug_module_readdata[23] <= system_cpu_nios2_oci:the_system_cpu_nios2_oci.readdata +jtag_debug_module_readdata[24] <= system_cpu_nios2_oci:the_system_cpu_nios2_oci.readdata +jtag_debug_module_readdata[25] <= system_cpu_nios2_oci:the_system_cpu_nios2_oci.readdata +jtag_debug_module_readdata[26] <= system_cpu_nios2_oci:the_system_cpu_nios2_oci.readdata +jtag_debug_module_readdata[27] <= system_cpu_nios2_oci:the_system_cpu_nios2_oci.readdata +jtag_debug_module_readdata[28] <= system_cpu_nios2_oci:the_system_cpu_nios2_oci.readdata +jtag_debug_module_readdata[29] <= system_cpu_nios2_oci:the_system_cpu_nios2_oci.readdata +jtag_debug_module_readdata[30] <= system_cpu_nios2_oci:the_system_cpu_nios2_oci.readdata +jtag_debug_module_readdata[31] <= system_cpu_nios2_oci:the_system_cpu_nios2_oci.readdata +jtag_debug_module_resetrequest <= system_cpu_nios2_oci:the_system_cpu_nios2_oci.resetrequest +no_ci_readra <= + + +|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_test_bench:the_system_cpu_test_bench +A_bstatus_reg[0] => ~NO_FANOUT~ +A_bstatus_reg[1] => ~NO_FANOUT~ +A_bstatus_reg[2] => ~NO_FANOUT~ +A_bstatus_reg[3] => ~NO_FANOUT~ +A_bstatus_reg[4] => ~NO_FANOUT~ +A_bstatus_reg[5] => ~NO_FANOUT~ +A_bstatus_reg[6] => ~NO_FANOUT~ +A_bstatus_reg[7] => ~NO_FANOUT~ +A_bstatus_reg[8] => ~NO_FANOUT~ +A_bstatus_reg[9] => ~NO_FANOUT~ +A_bstatus_reg[10] => ~NO_FANOUT~ +A_bstatus_reg[11] => ~NO_FANOUT~ +A_bstatus_reg[12] => ~NO_FANOUT~ +A_bstatus_reg[13] => ~NO_FANOUT~ +A_bstatus_reg[14] => ~NO_FANOUT~ +A_bstatus_reg[15] => ~NO_FANOUT~ +A_bstatus_reg[16] => ~NO_FANOUT~ +A_bstatus_reg[17] => ~NO_FANOUT~ +A_bstatus_reg[18] => ~NO_FANOUT~ +A_bstatus_reg[19] => ~NO_FANOUT~ +A_bstatus_reg[20] => ~NO_FANOUT~ +A_bstatus_reg[21] => ~NO_FANOUT~ +A_bstatus_reg[22] => ~NO_FANOUT~ +A_bstatus_reg[23] => ~NO_FANOUT~ +A_bstatus_reg[24] => ~NO_FANOUT~ +A_bstatus_reg[25] => ~NO_FANOUT~ +A_bstatus_reg[26] => ~NO_FANOUT~ +A_bstatus_reg[27] => ~NO_FANOUT~ +A_bstatus_reg[28] => ~NO_FANOUT~ +A_bstatus_reg[29] => ~NO_FANOUT~ +A_bstatus_reg[30] => ~NO_FANOUT~ +A_bstatus_reg[31] => ~NO_FANOUT~ +A_cmp_result => ~NO_FANOUT~ +A_ctrl_exception => ~NO_FANOUT~ +A_ctrl_ld_non_bypass => ~NO_FANOUT~ +A_dst_regnum[0] => ~NO_FANOUT~ +A_dst_regnum[1] => ~NO_FANOUT~ +A_dst_regnum[2] => ~NO_FANOUT~ +A_dst_regnum[3] => ~NO_FANOUT~ +A_dst_regnum[4] => ~NO_FANOUT~ +A_en => ~NO_FANOUT~ +A_estatus_reg[0] => ~NO_FANOUT~ +A_estatus_reg[1] => ~NO_FANOUT~ +A_estatus_reg[2] => ~NO_FANOUT~ +A_estatus_reg[3] => ~NO_FANOUT~ +A_estatus_reg[4] => ~NO_FANOUT~ +A_estatus_reg[5] => ~NO_FANOUT~ +A_estatus_reg[6] => ~NO_FANOUT~ +A_estatus_reg[7] => ~NO_FANOUT~ +A_estatus_reg[8] => ~NO_FANOUT~ +A_estatus_reg[9] => ~NO_FANOUT~ +A_estatus_reg[10] => ~NO_FANOUT~ +A_estatus_reg[11] => ~NO_FANOUT~ +A_estatus_reg[12] => ~NO_FANOUT~ +A_estatus_reg[13] => ~NO_FANOUT~ +A_estatus_reg[14] => ~NO_FANOUT~ +A_estatus_reg[15] => ~NO_FANOUT~ +A_estatus_reg[16] => ~NO_FANOUT~ +A_estatus_reg[17] => ~NO_FANOUT~ +A_estatus_reg[18] => ~NO_FANOUT~ +A_estatus_reg[19] => ~NO_FANOUT~ +A_estatus_reg[20] => ~NO_FANOUT~ +A_estatus_reg[21] => ~NO_FANOUT~ +A_estatus_reg[22] => ~NO_FANOUT~ +A_estatus_reg[23] => ~NO_FANOUT~ +A_estatus_reg[24] => ~NO_FANOUT~ +A_estatus_reg[25] => ~NO_FANOUT~ +A_estatus_reg[26] => ~NO_FANOUT~ +A_estatus_reg[27] => ~NO_FANOUT~ +A_estatus_reg[28] => ~NO_FANOUT~ +A_estatus_reg[29] => ~NO_FANOUT~ +A_estatus_reg[30] => ~NO_FANOUT~ +A_estatus_reg[31] => ~NO_FANOUT~ +A_ienable_reg[0] => ~NO_FANOUT~ +A_ienable_reg[1] => ~NO_FANOUT~ +A_ienable_reg[2] => ~NO_FANOUT~ +A_ienable_reg[3] => ~NO_FANOUT~ +A_ienable_reg[4] => ~NO_FANOUT~ +A_ienable_reg[5] => ~NO_FANOUT~ +A_ienable_reg[6] => ~NO_FANOUT~ +A_ienable_reg[7] => ~NO_FANOUT~ +A_ienable_reg[8] => ~NO_FANOUT~ +A_ienable_reg[9] => ~NO_FANOUT~ +A_ienable_reg[10] => ~NO_FANOUT~ +A_ienable_reg[11] => ~NO_FANOUT~ +A_ienable_reg[12] => ~NO_FANOUT~ +A_ienable_reg[13] => ~NO_FANOUT~ +A_ienable_reg[14] => ~NO_FANOUT~ +A_ienable_reg[15] => ~NO_FANOUT~ +A_ienable_reg[16] => ~NO_FANOUT~ +A_ienable_reg[17] => ~NO_FANOUT~ +A_ienable_reg[18] => ~NO_FANOUT~ +A_ienable_reg[19] => ~NO_FANOUT~ +A_ienable_reg[20] => ~NO_FANOUT~ +A_ienable_reg[21] => ~NO_FANOUT~ +A_ienable_reg[22] => ~NO_FANOUT~ +A_ienable_reg[23] => ~NO_FANOUT~ +A_ienable_reg[24] => ~NO_FANOUT~ +A_ienable_reg[25] => ~NO_FANOUT~ +A_ienable_reg[26] => ~NO_FANOUT~ +A_ienable_reg[27] => ~NO_FANOUT~ +A_ienable_reg[28] => ~NO_FANOUT~ +A_ienable_reg[29] => ~NO_FANOUT~ +A_ienable_reg[30] => ~NO_FANOUT~ +A_ienable_reg[31] => ~NO_FANOUT~ +A_ipending_reg[0] => ~NO_FANOUT~ +A_ipending_reg[1] => ~NO_FANOUT~ +A_ipending_reg[2] => ~NO_FANOUT~ +A_ipending_reg[3] => ~NO_FANOUT~ +A_ipending_reg[4] => ~NO_FANOUT~ +A_ipending_reg[5] => ~NO_FANOUT~ +A_ipending_reg[6] => ~NO_FANOUT~ +A_ipending_reg[7] => ~NO_FANOUT~ +A_ipending_reg[8] => ~NO_FANOUT~ +A_ipending_reg[9] => ~NO_FANOUT~ +A_ipending_reg[10] => ~NO_FANOUT~ +A_ipending_reg[11] => ~NO_FANOUT~ +A_ipending_reg[12] => ~NO_FANOUT~ +A_ipending_reg[13] => ~NO_FANOUT~ +A_ipending_reg[14] => ~NO_FANOUT~ +A_ipending_reg[15] => ~NO_FANOUT~ +A_ipending_reg[16] => ~NO_FANOUT~ +A_ipending_reg[17] => ~NO_FANOUT~ +A_ipending_reg[18] => ~NO_FANOUT~ +A_ipending_reg[19] => ~NO_FANOUT~ +A_ipending_reg[20] => ~NO_FANOUT~ +A_ipending_reg[21] => ~NO_FANOUT~ +A_ipending_reg[22] => ~NO_FANOUT~ +A_ipending_reg[23] => ~NO_FANOUT~ +A_ipending_reg[24] => ~NO_FANOUT~ +A_ipending_reg[25] => ~NO_FANOUT~ +A_ipending_reg[26] => ~NO_FANOUT~ +A_ipending_reg[27] => ~NO_FANOUT~ +A_ipending_reg[28] => ~NO_FANOUT~ +A_ipending_reg[29] => ~NO_FANOUT~ +A_ipending_reg[30] => ~NO_FANOUT~ +A_ipending_reg[31] => ~NO_FANOUT~ +A_iw[0] => ~NO_FANOUT~ +A_iw[1] => ~NO_FANOUT~ +A_iw[2] => ~NO_FANOUT~ +A_iw[3] => ~NO_FANOUT~ +A_iw[4] => ~NO_FANOUT~ +A_iw[5] => ~NO_FANOUT~ +A_iw[6] => ~NO_FANOUT~ +A_iw[7] => ~NO_FANOUT~ +A_iw[8] => ~NO_FANOUT~ +A_iw[9] => ~NO_FANOUT~ +A_iw[10] => ~NO_FANOUT~ +A_iw[11] => ~NO_FANOUT~ +A_iw[12] => ~NO_FANOUT~ +A_iw[13] => ~NO_FANOUT~ +A_iw[14] => ~NO_FANOUT~ +A_iw[15] => ~NO_FANOUT~ +A_iw[16] => ~NO_FANOUT~ +A_iw[17] => ~NO_FANOUT~ +A_iw[18] => ~NO_FANOUT~ +A_iw[19] => ~NO_FANOUT~ +A_iw[20] => ~NO_FANOUT~ +A_iw[21] => ~NO_FANOUT~ +A_iw[22] => ~NO_FANOUT~ +A_iw[23] => ~NO_FANOUT~ +A_iw[24] => ~NO_FANOUT~ +A_iw[25] => ~NO_FANOUT~ +A_iw[26] => ~NO_FANOUT~ +A_iw[27] => ~NO_FANOUT~ +A_iw[28] => ~NO_FANOUT~ +A_iw[29] => ~NO_FANOUT~ +A_iw[30] => ~NO_FANOUT~ +A_iw[31] => ~NO_FANOUT~ +A_mem_byte_en[0] => ~NO_FANOUT~ +A_mem_byte_en[1] => ~NO_FANOUT~ +A_mem_byte_en[2] => ~NO_FANOUT~ +A_mem_byte_en[3] => ~NO_FANOUT~ +A_op_hbreak => ~NO_FANOUT~ +A_op_intr => ~NO_FANOUT~ +A_pcb[0] => ~NO_FANOUT~ +A_pcb[1] => ~NO_FANOUT~ +A_pcb[2] => ~NO_FANOUT~ +A_pcb[3] => ~NO_FANOUT~ +A_pcb[4] => ~NO_FANOUT~ +A_pcb[5] => ~NO_FANOUT~ +A_pcb[6] => ~NO_FANOUT~ +A_pcb[7] => ~NO_FANOUT~ +A_pcb[8] => ~NO_FANOUT~ +A_pcb[9] => ~NO_FANOUT~ +A_pcb[10] => ~NO_FANOUT~ +A_pcb[11] => ~NO_FANOUT~ +A_pcb[12] => ~NO_FANOUT~ +A_pcb[13] => ~NO_FANOUT~ +A_pcb[14] => ~NO_FANOUT~ +A_pcb[15] => ~NO_FANOUT~ +A_pcb[16] => ~NO_FANOUT~ +A_pcb[17] => ~NO_FANOUT~ +A_pcb[18] => ~NO_FANOUT~ +A_pcb[19] => ~NO_FANOUT~ +A_pcb[20] => ~NO_FANOUT~ +A_pcb[21] => ~NO_FANOUT~ +A_pcb[22] => ~NO_FANOUT~ +A_pcb[23] => ~NO_FANOUT~ +A_pcb[24] => ~NO_FANOUT~ +A_pcb[25] => ~NO_FANOUT~ +A_st_data[0] => ~NO_FANOUT~ +A_st_data[1] => ~NO_FANOUT~ +A_st_data[2] => ~NO_FANOUT~ +A_st_data[3] => ~NO_FANOUT~ +A_st_data[4] => ~NO_FANOUT~ +A_st_data[5] => ~NO_FANOUT~ +A_st_data[6] => ~NO_FANOUT~ +A_st_data[7] => ~NO_FANOUT~ +A_st_data[8] => ~NO_FANOUT~ +A_st_data[9] => ~NO_FANOUT~ +A_st_data[10] => ~NO_FANOUT~ +A_st_data[11] => ~NO_FANOUT~ +A_st_data[12] => ~NO_FANOUT~ +A_st_data[13] => ~NO_FANOUT~ +A_st_data[14] => ~NO_FANOUT~ +A_st_data[15] => ~NO_FANOUT~ +A_st_data[16] => ~NO_FANOUT~ +A_st_data[17] => ~NO_FANOUT~ +A_st_data[18] => ~NO_FANOUT~ +A_st_data[19] => ~NO_FANOUT~ +A_st_data[20] => ~NO_FANOUT~ +A_st_data[21] => ~NO_FANOUT~ +A_st_data[22] => ~NO_FANOUT~ +A_st_data[23] => ~NO_FANOUT~ +A_st_data[24] => ~NO_FANOUT~ +A_st_data[25] => ~NO_FANOUT~ +A_st_data[26] => ~NO_FANOUT~ +A_st_data[27] => ~NO_FANOUT~ +A_st_data[28] => ~NO_FANOUT~ +A_st_data[29] => ~NO_FANOUT~ +A_st_data[30] => ~NO_FANOUT~ +A_st_data[31] => ~NO_FANOUT~ +A_status_reg[0] => ~NO_FANOUT~ +A_status_reg[1] => ~NO_FANOUT~ +A_status_reg[2] => ~NO_FANOUT~ +A_status_reg[3] => ~NO_FANOUT~ +A_status_reg[4] => ~NO_FANOUT~ +A_status_reg[5] => ~NO_FANOUT~ +A_status_reg[6] => ~NO_FANOUT~ +A_status_reg[7] => ~NO_FANOUT~ +A_status_reg[8] => ~NO_FANOUT~ +A_status_reg[9] => ~NO_FANOUT~ +A_status_reg[10] => ~NO_FANOUT~ +A_status_reg[11] => ~NO_FANOUT~ +A_status_reg[12] => ~NO_FANOUT~ +A_status_reg[13] => ~NO_FANOUT~ +A_status_reg[14] => ~NO_FANOUT~ +A_status_reg[15] => ~NO_FANOUT~ +A_status_reg[16] => ~NO_FANOUT~ +A_status_reg[17] => ~NO_FANOUT~ +A_status_reg[18] => ~NO_FANOUT~ +A_status_reg[19] => ~NO_FANOUT~ +A_status_reg[20] => ~NO_FANOUT~ +A_status_reg[21] => ~NO_FANOUT~ +A_status_reg[22] => ~NO_FANOUT~ +A_status_reg[23] => ~NO_FANOUT~ +A_status_reg[24] => ~NO_FANOUT~ +A_status_reg[25] => ~NO_FANOUT~ +A_status_reg[26] => ~NO_FANOUT~ +A_status_reg[27] => ~NO_FANOUT~ +A_status_reg[28] => ~NO_FANOUT~ +A_status_reg[29] => ~NO_FANOUT~ +A_status_reg[30] => ~NO_FANOUT~ +A_status_reg[31] => ~NO_FANOUT~ +A_valid => ~NO_FANOUT~ +A_wr_data_unfiltered[0] => A_wr_data_filtered[0].DATAIN +A_wr_data_unfiltered[1] => A_wr_data_filtered[1].DATAIN +A_wr_data_unfiltered[2] => A_wr_data_filtered[2].DATAIN +A_wr_data_unfiltered[3] => A_wr_data_filtered[3].DATAIN +A_wr_data_unfiltered[4] => A_wr_data_filtered[4].DATAIN +A_wr_data_unfiltered[5] => A_wr_data_filtered[5].DATAIN +A_wr_data_unfiltered[6] => A_wr_data_filtered[6].DATAIN +A_wr_data_unfiltered[7] => A_wr_data_filtered[7].DATAIN +A_wr_data_unfiltered[8] => A_wr_data_filtered[8].DATAIN +A_wr_data_unfiltered[9] => A_wr_data_filtered[9].DATAIN +A_wr_data_unfiltered[10] => A_wr_data_filtered[10].DATAIN +A_wr_data_unfiltered[11] => A_wr_data_filtered[11].DATAIN +A_wr_data_unfiltered[12] => A_wr_data_filtered[12].DATAIN +A_wr_data_unfiltered[13] => A_wr_data_filtered[13].DATAIN +A_wr_data_unfiltered[14] => A_wr_data_filtered[14].DATAIN +A_wr_data_unfiltered[15] => A_wr_data_filtered[15].DATAIN +A_wr_data_unfiltered[16] => A_wr_data_filtered[16].DATAIN +A_wr_data_unfiltered[17] => A_wr_data_filtered[17].DATAIN +A_wr_data_unfiltered[18] => A_wr_data_filtered[18].DATAIN +A_wr_data_unfiltered[19] => A_wr_data_filtered[19].DATAIN +A_wr_data_unfiltered[20] => A_wr_data_filtered[20].DATAIN +A_wr_data_unfiltered[21] => A_wr_data_filtered[21].DATAIN +A_wr_data_unfiltered[22] => A_wr_data_filtered[22].DATAIN +A_wr_data_unfiltered[23] => A_wr_data_filtered[23].DATAIN +A_wr_data_unfiltered[24] => A_wr_data_filtered[24].DATAIN +A_wr_data_unfiltered[25] => A_wr_data_filtered[25].DATAIN +A_wr_data_unfiltered[26] => A_wr_data_filtered[26].DATAIN +A_wr_data_unfiltered[27] => A_wr_data_filtered[27].DATAIN +A_wr_data_unfiltered[28] => A_wr_data_filtered[28].DATAIN +A_wr_data_unfiltered[29] => A_wr_data_filtered[29].DATAIN +A_wr_data_unfiltered[30] => A_wr_data_filtered[30].DATAIN +A_wr_data_unfiltered[31] => A_wr_data_filtered[31].DATAIN +A_wr_dst_reg => ~NO_FANOUT~ +E_add_br_to_taken_history_unfiltered => E_add_br_to_taken_history_filtered.DATAIN +E_logic_result[0] => Equal0.IN31 +E_logic_result[1] => Equal0.IN30 +E_logic_result[2] => Equal0.IN29 +E_logic_result[3] => Equal0.IN28 +E_logic_result[4] => Equal0.IN27 +E_logic_result[5] => Equal0.IN26 +E_logic_result[6] => Equal0.IN25 +E_logic_result[7] => Equal0.IN24 +E_logic_result[8] => Equal0.IN23 +E_logic_result[9] => Equal0.IN22 +E_logic_result[10] => Equal0.IN21 +E_logic_result[11] => Equal0.IN20 +E_logic_result[12] => Equal0.IN19 +E_logic_result[13] => Equal0.IN18 +E_logic_result[14] => Equal0.IN17 +E_logic_result[15] => Equal0.IN16 +E_logic_result[16] => Equal0.IN15 +E_logic_result[17] => Equal0.IN14 +E_logic_result[18] => Equal0.IN13 +E_logic_result[19] => Equal0.IN12 +E_logic_result[20] => Equal0.IN11 +E_logic_result[21] => Equal0.IN10 +E_logic_result[22] => Equal0.IN9 +E_logic_result[23] => Equal0.IN8 +E_logic_result[24] => Equal0.IN7 +E_logic_result[25] => Equal0.IN6 +E_logic_result[26] => Equal0.IN5 +E_logic_result[27] => Equal0.IN4 +E_logic_result[28] => Equal0.IN3 +E_logic_result[29] => Equal0.IN2 +E_logic_result[30] => Equal0.IN1 +E_logic_result[31] => Equal0.IN0 +E_valid => ~NO_FANOUT~ +M_bht_ptr_unfiltered[0] => M_bht_ptr_filtered[0].DATAIN +M_bht_ptr_unfiltered[1] => M_bht_ptr_filtered[1].DATAIN +M_bht_ptr_unfiltered[2] => M_bht_ptr_filtered[2].DATAIN +M_bht_ptr_unfiltered[3] => M_bht_ptr_filtered[3].DATAIN +M_bht_ptr_unfiltered[4] => M_bht_ptr_filtered[4].DATAIN +M_bht_ptr_unfiltered[5] => M_bht_ptr_filtered[5].DATAIN +M_bht_ptr_unfiltered[6] => M_bht_ptr_filtered[6].DATAIN +M_bht_ptr_unfiltered[7] => M_bht_ptr_filtered[7].DATAIN +M_bht_wr_data_unfiltered[0] => M_bht_wr_data_filtered[0].DATAIN +M_bht_wr_data_unfiltered[1] => M_bht_wr_data_filtered[1].DATAIN +M_bht_wr_en_unfiltered => M_bht_wr_en_filtered.DATAIN +M_mem_baddr[0] => ~NO_FANOUT~ +M_mem_baddr[1] => ~NO_FANOUT~ +M_mem_baddr[2] => ~NO_FANOUT~ +M_mem_baddr[3] => ~NO_FANOUT~ +M_mem_baddr[4] => ~NO_FANOUT~ +M_mem_baddr[5] => ~NO_FANOUT~ +M_mem_baddr[6] => ~NO_FANOUT~ +M_mem_baddr[7] => ~NO_FANOUT~ +M_mem_baddr[8] => ~NO_FANOUT~ +M_mem_baddr[9] => ~NO_FANOUT~ +M_mem_baddr[10] => ~NO_FANOUT~ +M_mem_baddr[11] => ~NO_FANOUT~ +M_mem_baddr[12] => ~NO_FANOUT~ +M_mem_baddr[13] => ~NO_FANOUT~ +M_mem_baddr[14] => ~NO_FANOUT~ +M_mem_baddr[15] => ~NO_FANOUT~ +M_mem_baddr[16] => ~NO_FANOUT~ +M_mem_baddr[17] => ~NO_FANOUT~ +M_mem_baddr[18] => ~NO_FANOUT~ +M_mem_baddr[19] => ~NO_FANOUT~ +M_mem_baddr[20] => ~NO_FANOUT~ +M_mem_baddr[21] => ~NO_FANOUT~ +M_mem_baddr[22] => ~NO_FANOUT~ +M_mem_baddr[23] => ~NO_FANOUT~ +M_mem_baddr[24] => ~NO_FANOUT~ +M_mem_baddr[25] => ~NO_FANOUT~ +M_target_pcb[0] => ~NO_FANOUT~ +M_target_pcb[1] => ~NO_FANOUT~ +M_target_pcb[2] => ~NO_FANOUT~ +M_target_pcb[3] => ~NO_FANOUT~ +M_target_pcb[4] => ~NO_FANOUT~ +M_target_pcb[5] => ~NO_FANOUT~ +M_target_pcb[6] => ~NO_FANOUT~ +M_target_pcb[7] => ~NO_FANOUT~ +M_target_pcb[8] => ~NO_FANOUT~ +M_target_pcb[9] => ~NO_FANOUT~ +M_target_pcb[10] => ~NO_FANOUT~ +M_target_pcb[11] => ~NO_FANOUT~ +M_target_pcb[12] => ~NO_FANOUT~ +M_target_pcb[13] => ~NO_FANOUT~ +M_target_pcb[14] => ~NO_FANOUT~ +M_target_pcb[15] => ~NO_FANOUT~ +M_target_pcb[16] => ~NO_FANOUT~ +M_target_pcb[17] => ~NO_FANOUT~ +M_target_pcb[18] => ~NO_FANOUT~ +M_target_pcb[19] => ~NO_FANOUT~ +M_target_pcb[20] => ~NO_FANOUT~ +M_target_pcb[21] => ~NO_FANOUT~ +M_target_pcb[22] => ~NO_FANOUT~ +M_target_pcb[23] => ~NO_FANOUT~ +M_target_pcb[24] => ~NO_FANOUT~ +M_target_pcb[25] => ~NO_FANOUT~ +M_valid => ~NO_FANOUT~ +W_dst_regnum[0] => ~NO_FANOUT~ +W_dst_regnum[1] => ~NO_FANOUT~ +W_dst_regnum[2] => ~NO_FANOUT~ +W_dst_regnum[3] => ~NO_FANOUT~ +W_dst_regnum[4] => ~NO_FANOUT~ +W_iw[0] => ~NO_FANOUT~ +W_iw[1] => ~NO_FANOUT~ +W_iw[2] => ~NO_FANOUT~ +W_iw[3] => ~NO_FANOUT~ +W_iw[4] => ~NO_FANOUT~ +W_iw[5] => ~NO_FANOUT~ +W_iw[6] => ~NO_FANOUT~ +W_iw[7] => ~NO_FANOUT~ +W_iw[8] => ~NO_FANOUT~ +W_iw[9] => ~NO_FANOUT~ +W_iw[10] => ~NO_FANOUT~ +W_iw[11] => ~NO_FANOUT~ +W_iw[12] => ~NO_FANOUT~ +W_iw[13] => ~NO_FANOUT~ +W_iw[14] => ~NO_FANOUT~ +W_iw[15] => ~NO_FANOUT~ +W_iw[16] => ~NO_FANOUT~ +W_iw[17] => ~NO_FANOUT~ +W_iw[18] => ~NO_FANOUT~ +W_iw[19] => ~NO_FANOUT~ +W_iw[20] => ~NO_FANOUT~ +W_iw[21] => ~NO_FANOUT~ +W_iw[22] => ~NO_FANOUT~ +W_iw[23] => ~NO_FANOUT~ +W_iw[24] => ~NO_FANOUT~ +W_iw[25] => ~NO_FANOUT~ +W_iw[26] => ~NO_FANOUT~ +W_iw[27] => ~NO_FANOUT~ +W_iw[28] => ~NO_FANOUT~ +W_iw[29] => ~NO_FANOUT~ +W_iw[30] => ~NO_FANOUT~ +W_iw[31] => ~NO_FANOUT~ +W_iw_op[0] => ~NO_FANOUT~ +W_iw_op[1] => ~NO_FANOUT~ +W_iw_op[2] => ~NO_FANOUT~ +W_iw_op[3] => ~NO_FANOUT~ +W_iw_op[4] => ~NO_FANOUT~ +W_iw_op[5] => ~NO_FANOUT~ +W_iw_opx[0] => ~NO_FANOUT~ +W_iw_opx[1] => ~NO_FANOUT~ +W_iw_opx[2] => ~NO_FANOUT~ +W_iw_opx[3] => ~NO_FANOUT~ +W_iw_opx[4] => ~NO_FANOUT~ +W_iw_opx[5] => ~NO_FANOUT~ +W_pcb[0] => ~NO_FANOUT~ +W_pcb[1] => ~NO_FANOUT~ +W_pcb[2] => ~NO_FANOUT~ +W_pcb[3] => ~NO_FANOUT~ +W_pcb[4] => ~NO_FANOUT~ +W_pcb[5] => ~NO_FANOUT~ +W_pcb[6] => ~NO_FANOUT~ +W_pcb[7] => ~NO_FANOUT~ +W_pcb[8] => ~NO_FANOUT~ +W_pcb[9] => ~NO_FANOUT~ +W_pcb[10] => ~NO_FANOUT~ +W_pcb[11] => ~NO_FANOUT~ +W_pcb[12] => ~NO_FANOUT~ +W_pcb[13] => ~NO_FANOUT~ +W_pcb[14] => ~NO_FANOUT~ +W_pcb[15] => ~NO_FANOUT~ +W_pcb[16] => ~NO_FANOUT~ +W_pcb[17] => ~NO_FANOUT~ +W_pcb[18] => ~NO_FANOUT~ +W_pcb[19] => ~NO_FANOUT~ +W_pcb[20] => ~NO_FANOUT~ +W_pcb[21] => ~NO_FANOUT~ +W_pcb[22] => ~NO_FANOUT~ +W_pcb[23] => ~NO_FANOUT~ +W_pcb[24] => ~NO_FANOUT~ +W_pcb[25] => ~NO_FANOUT~ +W_valid => ~NO_FANOUT~ +W_vinst[0] => ~NO_FANOUT~ +W_vinst[1] => ~NO_FANOUT~ +W_vinst[2] => ~NO_FANOUT~ +W_vinst[3] => ~NO_FANOUT~ +W_vinst[4] => ~NO_FANOUT~ +W_vinst[5] => ~NO_FANOUT~ +W_vinst[6] => ~NO_FANOUT~ +W_vinst[7] => ~NO_FANOUT~ +W_vinst[8] => ~NO_FANOUT~ +W_vinst[9] => ~NO_FANOUT~ +W_vinst[10] => ~NO_FANOUT~ +W_vinst[11] => ~NO_FANOUT~ +W_vinst[12] => ~NO_FANOUT~ +W_vinst[13] => ~NO_FANOUT~ +W_vinst[14] => ~NO_FANOUT~ +W_vinst[15] => ~NO_FANOUT~ +W_vinst[16] => ~NO_FANOUT~ +W_vinst[17] => ~NO_FANOUT~ +W_vinst[18] => ~NO_FANOUT~ +W_vinst[19] => ~NO_FANOUT~ +W_vinst[20] => ~NO_FANOUT~ +W_vinst[21] => ~NO_FANOUT~ +W_vinst[22] => ~NO_FANOUT~ +W_vinst[23] => ~NO_FANOUT~ +W_vinst[24] => ~NO_FANOUT~ +W_vinst[25] => ~NO_FANOUT~ +W_vinst[26] => ~NO_FANOUT~ +W_vinst[27] => ~NO_FANOUT~ +W_vinst[28] => ~NO_FANOUT~ +W_vinst[29] => ~NO_FANOUT~ +W_vinst[30] => ~NO_FANOUT~ +W_vinst[31] => ~NO_FANOUT~ +W_vinst[32] => ~NO_FANOUT~ +W_vinst[33] => ~NO_FANOUT~ +W_vinst[34] => ~NO_FANOUT~ +W_vinst[35] => ~NO_FANOUT~ +W_vinst[36] => ~NO_FANOUT~ +W_vinst[37] => ~NO_FANOUT~ +W_vinst[38] => ~NO_FANOUT~ +W_vinst[39] => ~NO_FANOUT~ +W_vinst[40] => ~NO_FANOUT~ +W_vinst[41] => ~NO_FANOUT~ +W_vinst[42] => ~NO_FANOUT~ +W_vinst[43] => ~NO_FANOUT~ +W_vinst[44] => ~NO_FANOUT~ +W_vinst[45] => ~NO_FANOUT~ +W_vinst[46] => ~NO_FANOUT~ +W_vinst[47] => ~NO_FANOUT~ +W_vinst[48] => ~NO_FANOUT~ +W_vinst[49] => ~NO_FANOUT~ +W_vinst[50] => ~NO_FANOUT~ +W_vinst[51] => ~NO_FANOUT~ +W_vinst[52] => ~NO_FANOUT~ +W_vinst[53] => ~NO_FANOUT~ +W_vinst[54] => ~NO_FANOUT~ +W_vinst[55] => ~NO_FANOUT~ +W_wr_dst_reg => ~NO_FANOUT~ +clk => ~NO_FANOUT~ +d_address[0] => ~NO_FANOUT~ +d_address[1] => ~NO_FANOUT~ +d_address[2] => ~NO_FANOUT~ +d_address[3] => ~NO_FANOUT~ +d_address[4] => ~NO_FANOUT~ +d_address[5] => ~NO_FANOUT~ +d_address[6] => ~NO_FANOUT~ +d_address[7] => ~NO_FANOUT~ +d_address[8] => ~NO_FANOUT~ +d_address[9] => ~NO_FANOUT~ +d_address[10] => ~NO_FANOUT~ +d_address[11] => ~NO_FANOUT~ +d_address[12] => ~NO_FANOUT~ +d_address[13] => ~NO_FANOUT~ +d_address[14] => ~NO_FANOUT~ +d_address[15] => ~NO_FANOUT~ +d_address[16] => ~NO_FANOUT~ +d_address[17] => ~NO_FANOUT~ +d_address[18] => ~NO_FANOUT~ +d_address[19] => ~NO_FANOUT~ +d_address[20] => ~NO_FANOUT~ +d_address[21] => ~NO_FANOUT~ +d_address[22] => ~NO_FANOUT~ +d_address[23] => ~NO_FANOUT~ +d_address[24] => ~NO_FANOUT~ +d_address[25] => ~NO_FANOUT~ +d_byteenable[0] => ~NO_FANOUT~ +d_byteenable[1] => ~NO_FANOUT~ +d_byteenable[2] => ~NO_FANOUT~ +d_byteenable[3] => ~NO_FANOUT~ +d_read => ~NO_FANOUT~ +d_write => ~NO_FANOUT~ +i_address[0] => ~NO_FANOUT~ +i_address[1] => ~NO_FANOUT~ +i_address[2] => ~NO_FANOUT~ +i_address[3] => ~NO_FANOUT~ +i_address[4] => ~NO_FANOUT~ +i_address[5] => ~NO_FANOUT~ +i_address[6] => ~NO_FANOUT~ +i_address[7] => ~NO_FANOUT~ +i_address[8] => ~NO_FANOUT~ +i_address[9] => ~NO_FANOUT~ +i_address[10] => ~NO_FANOUT~ +i_address[11] => ~NO_FANOUT~ +i_address[12] => ~NO_FANOUT~ +i_address[13] => ~NO_FANOUT~ +i_address[14] => ~NO_FANOUT~ +i_address[15] => ~NO_FANOUT~ +i_address[16] => ~NO_FANOUT~ +i_address[17] => ~NO_FANOUT~ +i_address[18] => ~NO_FANOUT~ +i_address[19] => ~NO_FANOUT~ +i_address[20] => ~NO_FANOUT~ +i_address[21] => ~NO_FANOUT~ +i_address[22] => ~NO_FANOUT~ +i_address[23] => ~NO_FANOUT~ +i_address[24] => ~NO_FANOUT~ +i_address[25] => ~NO_FANOUT~ +i_read => ~NO_FANOUT~ +i_readdatavalid => ~NO_FANOUT~ +reset_n => ~NO_FANOUT~ +A_wr_data_filtered[0] <= A_wr_data_unfiltered[0].DB_MAX_OUTPUT_PORT_TYPE +A_wr_data_filtered[1] <= A_wr_data_unfiltered[1].DB_MAX_OUTPUT_PORT_TYPE +A_wr_data_filtered[2] <= A_wr_data_unfiltered[2].DB_MAX_OUTPUT_PORT_TYPE +A_wr_data_filtered[3] <= A_wr_data_unfiltered[3].DB_MAX_OUTPUT_PORT_TYPE +A_wr_data_filtered[4] <= A_wr_data_unfiltered[4].DB_MAX_OUTPUT_PORT_TYPE +A_wr_data_filtered[5] <= A_wr_data_unfiltered[5].DB_MAX_OUTPUT_PORT_TYPE +A_wr_data_filtered[6] <= A_wr_data_unfiltered[6].DB_MAX_OUTPUT_PORT_TYPE +A_wr_data_filtered[7] <= A_wr_data_unfiltered[7].DB_MAX_OUTPUT_PORT_TYPE +A_wr_data_filtered[8] <= A_wr_data_unfiltered[8].DB_MAX_OUTPUT_PORT_TYPE +A_wr_data_filtered[9] <= A_wr_data_unfiltered[9].DB_MAX_OUTPUT_PORT_TYPE +A_wr_data_filtered[10] <= A_wr_data_unfiltered[10].DB_MAX_OUTPUT_PORT_TYPE +A_wr_data_filtered[11] <= A_wr_data_unfiltered[11].DB_MAX_OUTPUT_PORT_TYPE +A_wr_data_filtered[12] <= A_wr_data_unfiltered[12].DB_MAX_OUTPUT_PORT_TYPE +A_wr_data_filtered[13] <= A_wr_data_unfiltered[13].DB_MAX_OUTPUT_PORT_TYPE +A_wr_data_filtered[14] <= A_wr_data_unfiltered[14].DB_MAX_OUTPUT_PORT_TYPE +A_wr_data_filtered[15] <= A_wr_data_unfiltered[15].DB_MAX_OUTPUT_PORT_TYPE +A_wr_data_filtered[16] <= A_wr_data_unfiltered[16].DB_MAX_OUTPUT_PORT_TYPE +A_wr_data_filtered[17] <= A_wr_data_unfiltered[17].DB_MAX_OUTPUT_PORT_TYPE +A_wr_data_filtered[18] <= A_wr_data_unfiltered[18].DB_MAX_OUTPUT_PORT_TYPE +A_wr_data_filtered[19] <= A_wr_data_unfiltered[19].DB_MAX_OUTPUT_PORT_TYPE +A_wr_data_filtered[20] <= A_wr_data_unfiltered[20].DB_MAX_OUTPUT_PORT_TYPE +A_wr_data_filtered[21] <= A_wr_data_unfiltered[21].DB_MAX_OUTPUT_PORT_TYPE +A_wr_data_filtered[22] <= A_wr_data_unfiltered[22].DB_MAX_OUTPUT_PORT_TYPE +A_wr_data_filtered[23] <= A_wr_data_unfiltered[23].DB_MAX_OUTPUT_PORT_TYPE +A_wr_data_filtered[24] <= A_wr_data_unfiltered[24].DB_MAX_OUTPUT_PORT_TYPE +A_wr_data_filtered[25] <= A_wr_data_unfiltered[25].DB_MAX_OUTPUT_PORT_TYPE +A_wr_data_filtered[26] <= A_wr_data_unfiltered[26].DB_MAX_OUTPUT_PORT_TYPE +A_wr_data_filtered[27] <= A_wr_data_unfiltered[27].DB_MAX_OUTPUT_PORT_TYPE +A_wr_data_filtered[28] <= A_wr_data_unfiltered[28].DB_MAX_OUTPUT_PORT_TYPE +A_wr_data_filtered[29] <= A_wr_data_unfiltered[29].DB_MAX_OUTPUT_PORT_TYPE +A_wr_data_filtered[30] <= A_wr_data_unfiltered[30].DB_MAX_OUTPUT_PORT_TYPE +A_wr_data_filtered[31] <= A_wr_data_unfiltered[31].DB_MAX_OUTPUT_PORT_TYPE +E_add_br_to_taken_history_filtered <= E_add_br_to_taken_history_unfiltered.DB_MAX_OUTPUT_PORT_TYPE +E_src1_eq_src2 <= Equal0.DB_MAX_OUTPUT_PORT_TYPE +M_bht_ptr_filtered[0] <= M_bht_ptr_unfiltered[0].DB_MAX_OUTPUT_PORT_TYPE +M_bht_ptr_filtered[1] <= M_bht_ptr_unfiltered[1].DB_MAX_OUTPUT_PORT_TYPE +M_bht_ptr_filtered[2] <= M_bht_ptr_unfiltered[2].DB_MAX_OUTPUT_PORT_TYPE +M_bht_ptr_filtered[3] <= M_bht_ptr_unfiltered[3].DB_MAX_OUTPUT_PORT_TYPE +M_bht_ptr_filtered[4] <= M_bht_ptr_unfiltered[4].DB_MAX_OUTPUT_PORT_TYPE +M_bht_ptr_filtered[5] <= M_bht_ptr_unfiltered[5].DB_MAX_OUTPUT_PORT_TYPE +M_bht_ptr_filtered[6] <= M_bht_ptr_unfiltered[6].DB_MAX_OUTPUT_PORT_TYPE +M_bht_ptr_filtered[7] <= M_bht_ptr_unfiltered[7].DB_MAX_OUTPUT_PORT_TYPE +M_bht_wr_data_filtered[0] <= M_bht_wr_data_unfiltered[0].DB_MAX_OUTPUT_PORT_TYPE +M_bht_wr_data_filtered[1] <= M_bht_wr_data_unfiltered[1].DB_MAX_OUTPUT_PORT_TYPE +M_bht_wr_en_filtered <= M_bht_wr_en_unfiltered.DB_MAX_OUTPUT_PORT_TYPE +test_has_ended <= + + +|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data +clock => clock.IN1 +data[0] => data[0].IN1 +data[1] => data[1].IN1 +data[2] => data[2].IN1 +data[3] => data[3].IN1 +data[4] => data[4].IN1 +data[5] => data[5].IN1 +data[6] => data[6].IN1 +data[7] => data[7].IN1 +data[8] => data[8].IN1 +data[9] => data[9].IN1 +data[10] => data[10].IN1 +data[11] => data[11].IN1 +data[12] => data[12].IN1 +data[13] => data[13].IN1 +data[14] => data[14].IN1 +data[15] => data[15].IN1 +data[16] => data[16].IN1 +data[17] => data[17].IN1 +data[18] => data[18].IN1 +data[19] => data[19].IN1 +data[20] => data[20].IN1 +data[21] => data[21].IN1 +data[22] => data[22].IN1 +data[23] => data[23].IN1 +data[24] => data[24].IN1 +data[25] => data[25].IN1 +data[26] => data[26].IN1 +data[27] => data[27].IN1 +data[28] => data[28].IN1 +data[29] => data[29].IN1 +data[30] => data[30].IN1 +data[31] => data[31].IN1 +rdaddress[0] => rdaddress[0].IN1 +rdaddress[1] => rdaddress[1].IN1 +rdaddress[2] => rdaddress[2].IN1 +rdaddress[3] => rdaddress[3].IN1 +rdaddress[4] => rdaddress[4].IN1 +rdaddress[5] => rdaddress[5].IN1 +rdaddress[6] => rdaddress[6].IN1 +rdaddress[7] => rdaddress[7].IN1 +rdaddress[8] => rdaddress[8].IN1 +rdaddress[9] => rdaddress[9].IN1 +rdaddress[10] => rdaddress[10].IN1 +rden => rden.IN1 +wraddress[0] => wraddress[0].IN1 +wraddress[1] => wraddress[1].IN1 +wraddress[2] => wraddress[2].IN1 +wraddress[3] => wraddress[3].IN1 +wraddress[4] => wraddress[4].IN1 +wraddress[5] => wraddress[5].IN1 +wraddress[6] => wraddress[6].IN1 +wraddress[7] => wraddress[7].IN1 +wraddress[8] => wraddress[8].IN1 +wraddress[9] => wraddress[9].IN1 +wraddress[10] => wraddress[10].IN1 +wren => wren.IN1 +q[0] <= altsyncram:the_altsyncram.q_b +q[1] <= altsyncram:the_altsyncram.q_b +q[2] <= altsyncram:the_altsyncram.q_b +q[3] <= altsyncram:the_altsyncram.q_b +q[4] <= altsyncram:the_altsyncram.q_b +q[5] <= altsyncram:the_altsyncram.q_b +q[6] <= altsyncram:the_altsyncram.q_b +q[7] <= altsyncram:the_altsyncram.q_b +q[8] <= altsyncram:the_altsyncram.q_b +q[9] <= altsyncram:the_altsyncram.q_b +q[10] <= altsyncram:the_altsyncram.q_b +q[11] <= altsyncram:the_altsyncram.q_b +q[12] <= altsyncram:the_altsyncram.q_b +q[13] <= altsyncram:the_altsyncram.q_b +q[14] <= altsyncram:the_altsyncram.q_b +q[15] <= altsyncram:the_altsyncram.q_b +q[16] <= altsyncram:the_altsyncram.q_b +q[17] <= altsyncram:the_altsyncram.q_b +q[18] <= altsyncram:the_altsyncram.q_b +q[19] <= altsyncram:the_altsyncram.q_b +q[20] <= altsyncram:the_altsyncram.q_b +q[21] <= altsyncram:the_altsyncram.q_b +q[22] <= altsyncram:the_altsyncram.q_b +q[23] <= altsyncram:the_altsyncram.q_b +q[24] <= altsyncram:the_altsyncram.q_b +q[25] <= altsyncram:the_altsyncram.q_b +q[26] <= altsyncram:the_altsyncram.q_b +q[27] <= altsyncram:the_altsyncram.q_b +q[28] <= altsyncram:the_altsyncram.q_b +q[29] <= altsyncram:the_altsyncram.q_b +q[30] <= altsyncram:the_altsyncram.q_b +q[31] <= altsyncram:the_altsyncram.q_b + + +|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram +wren_a => altsyncram_sjd1:auto_generated.wren_a +rden_a => ~NO_FANOUT~ +wren_b => ~NO_FANOUT~ +rden_b => altsyncram_sjd1:auto_generated.rden_b +data_a[0] => altsyncram_sjd1:auto_generated.data_a[0] +data_a[1] => altsyncram_sjd1:auto_generated.data_a[1] +data_a[2] => altsyncram_sjd1:auto_generated.data_a[2] +data_a[3] => altsyncram_sjd1:auto_generated.data_a[3] +data_a[4] => altsyncram_sjd1:auto_generated.data_a[4] +data_a[5] => altsyncram_sjd1:auto_generated.data_a[5] +data_a[6] => altsyncram_sjd1:auto_generated.data_a[6] +data_a[7] => altsyncram_sjd1:auto_generated.data_a[7] +data_a[8] => altsyncram_sjd1:auto_generated.data_a[8] +data_a[9] => altsyncram_sjd1:auto_generated.data_a[9] +data_a[10] => altsyncram_sjd1:auto_generated.data_a[10] +data_a[11] => altsyncram_sjd1:auto_generated.data_a[11] +data_a[12] => altsyncram_sjd1:auto_generated.data_a[12] +data_a[13] => altsyncram_sjd1:auto_generated.data_a[13] +data_a[14] => altsyncram_sjd1:auto_generated.data_a[14] +data_a[15] => altsyncram_sjd1:auto_generated.data_a[15] +data_a[16] => altsyncram_sjd1:auto_generated.data_a[16] +data_a[17] => altsyncram_sjd1:auto_generated.data_a[17] +data_a[18] => altsyncram_sjd1:auto_generated.data_a[18] +data_a[19] => altsyncram_sjd1:auto_generated.data_a[19] +data_a[20] => altsyncram_sjd1:auto_generated.data_a[20] +data_a[21] => altsyncram_sjd1:auto_generated.data_a[21] +data_a[22] => altsyncram_sjd1:auto_generated.data_a[22] +data_a[23] => altsyncram_sjd1:auto_generated.data_a[23] +data_a[24] => altsyncram_sjd1:auto_generated.data_a[24] +data_a[25] => altsyncram_sjd1:auto_generated.data_a[25] +data_a[26] => altsyncram_sjd1:auto_generated.data_a[26] +data_a[27] => altsyncram_sjd1:auto_generated.data_a[27] +data_a[28] => altsyncram_sjd1:auto_generated.data_a[28] +data_a[29] => altsyncram_sjd1:auto_generated.data_a[29] +data_a[30] => altsyncram_sjd1:auto_generated.data_a[30] +data_a[31] => altsyncram_sjd1:auto_generated.data_a[31] +data_b[0] => ~NO_FANOUT~ +data_b[1] => ~NO_FANOUT~ +data_b[2] => ~NO_FANOUT~ +data_b[3] => ~NO_FANOUT~ +data_b[4] => ~NO_FANOUT~ +data_b[5] => ~NO_FANOUT~ +data_b[6] => ~NO_FANOUT~ +data_b[7] => ~NO_FANOUT~ +data_b[8] => ~NO_FANOUT~ +data_b[9] => ~NO_FANOUT~ +data_b[10] => ~NO_FANOUT~ +data_b[11] => ~NO_FANOUT~ +data_b[12] => ~NO_FANOUT~ +data_b[13] => ~NO_FANOUT~ +data_b[14] => ~NO_FANOUT~ +data_b[15] => ~NO_FANOUT~ +data_b[16] => ~NO_FANOUT~ +data_b[17] => ~NO_FANOUT~ +data_b[18] => ~NO_FANOUT~ +data_b[19] => ~NO_FANOUT~ +data_b[20] => ~NO_FANOUT~ +data_b[21] => ~NO_FANOUT~ +data_b[22] => ~NO_FANOUT~ +data_b[23] => ~NO_FANOUT~ +data_b[24] => ~NO_FANOUT~ +data_b[25] => ~NO_FANOUT~ +data_b[26] => ~NO_FANOUT~ +data_b[27] => ~NO_FANOUT~ +data_b[28] => ~NO_FANOUT~ +data_b[29] => ~NO_FANOUT~ +data_b[30] => ~NO_FANOUT~ +data_b[31] => ~NO_FANOUT~ +address_a[0] => altsyncram_sjd1:auto_generated.address_a[0] +address_a[1] => altsyncram_sjd1:auto_generated.address_a[1] +address_a[2] => altsyncram_sjd1:auto_generated.address_a[2] +address_a[3] => altsyncram_sjd1:auto_generated.address_a[3] +address_a[4] => altsyncram_sjd1:auto_generated.address_a[4] +address_a[5] => altsyncram_sjd1:auto_generated.address_a[5] +address_a[6] => altsyncram_sjd1:auto_generated.address_a[6] +address_a[7] => altsyncram_sjd1:auto_generated.address_a[7] +address_a[8] => altsyncram_sjd1:auto_generated.address_a[8] +address_a[9] => altsyncram_sjd1:auto_generated.address_a[9] +address_a[10] => altsyncram_sjd1:auto_generated.address_a[10] +address_b[0] => altsyncram_sjd1:auto_generated.address_b[0] +address_b[1] => altsyncram_sjd1:auto_generated.address_b[1] +address_b[2] => altsyncram_sjd1:auto_generated.address_b[2] +address_b[3] => altsyncram_sjd1:auto_generated.address_b[3] +address_b[4] => altsyncram_sjd1:auto_generated.address_b[4] +address_b[5] => altsyncram_sjd1:auto_generated.address_b[5] +address_b[6] => altsyncram_sjd1:auto_generated.address_b[6] +address_b[7] => altsyncram_sjd1:auto_generated.address_b[7] +address_b[8] => altsyncram_sjd1:auto_generated.address_b[8] +address_b[9] => altsyncram_sjd1:auto_generated.address_b[9] +address_b[10] => altsyncram_sjd1:auto_generated.address_b[10] +addressstall_a => ~NO_FANOUT~ +addressstall_b => ~NO_FANOUT~ +clock0 => altsyncram_sjd1:auto_generated.clock0 +clock1 => ~NO_FANOUT~ +clocken0 => ~NO_FANOUT~ +clocken1 => ~NO_FANOUT~ +clocken2 => ~NO_FANOUT~ +clocken3 => ~NO_FANOUT~ +aclr0 => ~NO_FANOUT~ +aclr1 => ~NO_FANOUT~ +byteena_a[0] => ~NO_FANOUT~ +byteena_b[0] => ~NO_FANOUT~ +q_a[0] <= +q_a[1] <= +q_a[2] <= +q_a[3] <= +q_a[4] <= +q_a[5] <= +q_a[6] <= +q_a[7] <= +q_a[8] <= +q_a[9] <= +q_a[10] <= +q_a[11] <= +q_a[12] <= +q_a[13] <= +q_a[14] <= +q_a[15] <= +q_a[16] <= +q_a[17] <= +q_a[18] <= +q_a[19] <= +q_a[20] <= +q_a[21] <= +q_a[22] <= +q_a[23] <= +q_a[24] <= +q_a[25] <= +q_a[26] <= +q_a[27] <= +q_a[28] <= +q_a[29] <= +q_a[30] <= +q_a[31] <= +q_b[0] <= altsyncram_sjd1:auto_generated.q_b[0] +q_b[1] <= altsyncram_sjd1:auto_generated.q_b[1] +q_b[2] <= altsyncram_sjd1:auto_generated.q_b[2] +q_b[3] <= altsyncram_sjd1:auto_generated.q_b[3] +q_b[4] <= altsyncram_sjd1:auto_generated.q_b[4] +q_b[5] <= altsyncram_sjd1:auto_generated.q_b[5] +q_b[6] <= altsyncram_sjd1:auto_generated.q_b[6] +q_b[7] <= altsyncram_sjd1:auto_generated.q_b[7] +q_b[8] <= altsyncram_sjd1:auto_generated.q_b[8] +q_b[9] <= altsyncram_sjd1:auto_generated.q_b[9] +q_b[10] <= altsyncram_sjd1:auto_generated.q_b[10] +q_b[11] <= altsyncram_sjd1:auto_generated.q_b[11] +q_b[12] <= altsyncram_sjd1:auto_generated.q_b[12] +q_b[13] <= altsyncram_sjd1:auto_generated.q_b[13] +q_b[14] <= altsyncram_sjd1:auto_generated.q_b[14] +q_b[15] <= altsyncram_sjd1:auto_generated.q_b[15] +q_b[16] <= altsyncram_sjd1:auto_generated.q_b[16] +q_b[17] <= altsyncram_sjd1:auto_generated.q_b[17] +q_b[18] <= altsyncram_sjd1:auto_generated.q_b[18] +q_b[19] <= altsyncram_sjd1:auto_generated.q_b[19] +q_b[20] <= altsyncram_sjd1:auto_generated.q_b[20] +q_b[21] <= altsyncram_sjd1:auto_generated.q_b[21] +q_b[22] <= altsyncram_sjd1:auto_generated.q_b[22] +q_b[23] <= altsyncram_sjd1:auto_generated.q_b[23] +q_b[24] <= altsyncram_sjd1:auto_generated.q_b[24] +q_b[25] <= altsyncram_sjd1:auto_generated.q_b[25] +q_b[26] <= altsyncram_sjd1:auto_generated.q_b[26] +q_b[27] <= altsyncram_sjd1:auto_generated.q_b[27] +q_b[28] <= altsyncram_sjd1:auto_generated.q_b[28] +q_b[29] <= altsyncram_sjd1:auto_generated.q_b[29] +q_b[30] <= altsyncram_sjd1:auto_generated.q_b[30] +q_b[31] <= altsyncram_sjd1:auto_generated.q_b[31] +eccstatus[0] <= +eccstatus[1] <= +eccstatus[2] <= + + +|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated +address_a[0] => ram_block1a0.PORTAADDR +address_a[0] => ram_block1a1.PORTAADDR +address_a[0] => ram_block1a2.PORTAADDR +address_a[0] => ram_block1a3.PORTAADDR +address_a[0] => ram_block1a4.PORTAADDR +address_a[0] => ram_block1a5.PORTAADDR +address_a[0] => ram_block1a6.PORTAADDR +address_a[0] => ram_block1a7.PORTAADDR +address_a[0] => ram_block1a8.PORTAADDR +address_a[0] => ram_block1a9.PORTAADDR +address_a[0] => ram_block1a10.PORTAADDR +address_a[0] => ram_block1a11.PORTAADDR +address_a[0] => ram_block1a12.PORTAADDR +address_a[0] => ram_block1a13.PORTAADDR +address_a[0] => ram_block1a14.PORTAADDR +address_a[0] => ram_block1a15.PORTAADDR +address_a[0] => ram_block1a16.PORTAADDR +address_a[0] => ram_block1a17.PORTAADDR +address_a[0] => ram_block1a18.PORTAADDR +address_a[0] => ram_block1a19.PORTAADDR +address_a[0] => ram_block1a20.PORTAADDR +address_a[0] => ram_block1a21.PORTAADDR +address_a[0] => ram_block1a22.PORTAADDR +address_a[0] => ram_block1a23.PORTAADDR +address_a[0] => ram_block1a24.PORTAADDR +address_a[0] => ram_block1a25.PORTAADDR +address_a[0] => ram_block1a26.PORTAADDR +address_a[0] => ram_block1a27.PORTAADDR +address_a[0] => ram_block1a28.PORTAADDR +address_a[0] => ram_block1a29.PORTAADDR +address_a[0] => ram_block1a30.PORTAADDR +address_a[0] => ram_block1a31.PORTAADDR +address_a[1] => ram_block1a0.PORTAADDR1 +address_a[1] => ram_block1a1.PORTAADDR1 +address_a[1] => ram_block1a2.PORTAADDR1 +address_a[1] => ram_block1a3.PORTAADDR1 +address_a[1] => ram_block1a4.PORTAADDR1 +address_a[1] => ram_block1a5.PORTAADDR1 +address_a[1] => ram_block1a6.PORTAADDR1 +address_a[1] => ram_block1a7.PORTAADDR1 +address_a[1] => ram_block1a8.PORTAADDR1 +address_a[1] => ram_block1a9.PORTAADDR1 +address_a[1] => ram_block1a10.PORTAADDR1 +address_a[1] => ram_block1a11.PORTAADDR1 +address_a[1] => ram_block1a12.PORTAADDR1 +address_a[1] => ram_block1a13.PORTAADDR1 +address_a[1] => ram_block1a14.PORTAADDR1 +address_a[1] => ram_block1a15.PORTAADDR1 +address_a[1] => ram_block1a16.PORTAADDR1 +address_a[1] => ram_block1a17.PORTAADDR1 +address_a[1] => ram_block1a18.PORTAADDR1 +address_a[1] => ram_block1a19.PORTAADDR1 +address_a[1] => ram_block1a20.PORTAADDR1 +address_a[1] => ram_block1a21.PORTAADDR1 +address_a[1] => ram_block1a22.PORTAADDR1 +address_a[1] => ram_block1a23.PORTAADDR1 +address_a[1] => ram_block1a24.PORTAADDR1 +address_a[1] => ram_block1a25.PORTAADDR1 +address_a[1] => ram_block1a26.PORTAADDR1 +address_a[1] => ram_block1a27.PORTAADDR1 +address_a[1] => ram_block1a28.PORTAADDR1 +address_a[1] => ram_block1a29.PORTAADDR1 +address_a[1] => ram_block1a30.PORTAADDR1 +address_a[1] => ram_block1a31.PORTAADDR1 +address_a[2] => ram_block1a0.PORTAADDR2 +address_a[2] => ram_block1a1.PORTAADDR2 +address_a[2] => ram_block1a2.PORTAADDR2 +address_a[2] => ram_block1a3.PORTAADDR2 +address_a[2] => ram_block1a4.PORTAADDR2 +address_a[2] => ram_block1a5.PORTAADDR2 +address_a[2] => ram_block1a6.PORTAADDR2 +address_a[2] => ram_block1a7.PORTAADDR2 +address_a[2] => ram_block1a8.PORTAADDR2 +address_a[2] => ram_block1a9.PORTAADDR2 +address_a[2] => ram_block1a10.PORTAADDR2 +address_a[2] => ram_block1a11.PORTAADDR2 +address_a[2] => ram_block1a12.PORTAADDR2 +address_a[2] => ram_block1a13.PORTAADDR2 +address_a[2] => ram_block1a14.PORTAADDR2 +address_a[2] => ram_block1a15.PORTAADDR2 +address_a[2] => ram_block1a16.PORTAADDR2 +address_a[2] => ram_block1a17.PORTAADDR2 +address_a[2] => ram_block1a18.PORTAADDR2 +address_a[2] => ram_block1a19.PORTAADDR2 +address_a[2] => ram_block1a20.PORTAADDR2 +address_a[2] => ram_block1a21.PORTAADDR2 +address_a[2] => ram_block1a22.PORTAADDR2 +address_a[2] => ram_block1a23.PORTAADDR2 +address_a[2] => ram_block1a24.PORTAADDR2 +address_a[2] => ram_block1a25.PORTAADDR2 +address_a[2] => ram_block1a26.PORTAADDR2 +address_a[2] => ram_block1a27.PORTAADDR2 +address_a[2] => ram_block1a28.PORTAADDR2 +address_a[2] => ram_block1a29.PORTAADDR2 +address_a[2] => ram_block1a30.PORTAADDR2 +address_a[2] => ram_block1a31.PORTAADDR2 +address_a[3] => ram_block1a0.PORTAADDR3 +address_a[3] => ram_block1a1.PORTAADDR3 +address_a[3] => ram_block1a2.PORTAADDR3 +address_a[3] => ram_block1a3.PORTAADDR3 +address_a[3] => ram_block1a4.PORTAADDR3 +address_a[3] => ram_block1a5.PORTAADDR3 +address_a[3] => ram_block1a6.PORTAADDR3 +address_a[3] => ram_block1a7.PORTAADDR3 +address_a[3] => ram_block1a8.PORTAADDR3 +address_a[3] => ram_block1a9.PORTAADDR3 +address_a[3] => ram_block1a10.PORTAADDR3 +address_a[3] => ram_block1a11.PORTAADDR3 +address_a[3] => ram_block1a12.PORTAADDR3 +address_a[3] => ram_block1a13.PORTAADDR3 +address_a[3] => ram_block1a14.PORTAADDR3 +address_a[3] => ram_block1a15.PORTAADDR3 +address_a[3] => ram_block1a16.PORTAADDR3 +address_a[3] => ram_block1a17.PORTAADDR3 +address_a[3] => ram_block1a18.PORTAADDR3 +address_a[3] => ram_block1a19.PORTAADDR3 +address_a[3] => ram_block1a20.PORTAADDR3 +address_a[3] => ram_block1a21.PORTAADDR3 +address_a[3] => ram_block1a22.PORTAADDR3 +address_a[3] => ram_block1a23.PORTAADDR3 +address_a[3] => ram_block1a24.PORTAADDR3 +address_a[3] => ram_block1a25.PORTAADDR3 +address_a[3] => ram_block1a26.PORTAADDR3 +address_a[3] => ram_block1a27.PORTAADDR3 +address_a[3] => ram_block1a28.PORTAADDR3 +address_a[3] => ram_block1a29.PORTAADDR3 +address_a[3] => ram_block1a30.PORTAADDR3 +address_a[3] => ram_block1a31.PORTAADDR3 +address_a[4] => ram_block1a0.PORTAADDR4 +address_a[4] => ram_block1a1.PORTAADDR4 +address_a[4] => ram_block1a2.PORTAADDR4 +address_a[4] => ram_block1a3.PORTAADDR4 +address_a[4] => ram_block1a4.PORTAADDR4 +address_a[4] => ram_block1a5.PORTAADDR4 +address_a[4] => ram_block1a6.PORTAADDR4 +address_a[4] => ram_block1a7.PORTAADDR4 +address_a[4] => ram_block1a8.PORTAADDR4 +address_a[4] => ram_block1a9.PORTAADDR4 +address_a[4] => ram_block1a10.PORTAADDR4 +address_a[4] => ram_block1a11.PORTAADDR4 +address_a[4] => ram_block1a12.PORTAADDR4 +address_a[4] => ram_block1a13.PORTAADDR4 +address_a[4] => ram_block1a14.PORTAADDR4 +address_a[4] => ram_block1a15.PORTAADDR4 +address_a[4] => ram_block1a16.PORTAADDR4 +address_a[4] => ram_block1a17.PORTAADDR4 +address_a[4] => ram_block1a18.PORTAADDR4 +address_a[4] => ram_block1a19.PORTAADDR4 +address_a[4] => ram_block1a20.PORTAADDR4 +address_a[4] => ram_block1a21.PORTAADDR4 +address_a[4] => ram_block1a22.PORTAADDR4 +address_a[4] => ram_block1a23.PORTAADDR4 +address_a[4] => ram_block1a24.PORTAADDR4 +address_a[4] => ram_block1a25.PORTAADDR4 +address_a[4] => ram_block1a26.PORTAADDR4 +address_a[4] => ram_block1a27.PORTAADDR4 +address_a[4] => ram_block1a28.PORTAADDR4 +address_a[4] => ram_block1a29.PORTAADDR4 +address_a[4] => ram_block1a30.PORTAADDR4 +address_a[4] => ram_block1a31.PORTAADDR4 +address_a[5] => ram_block1a0.PORTAADDR5 +address_a[5] => ram_block1a1.PORTAADDR5 +address_a[5] => ram_block1a2.PORTAADDR5 +address_a[5] => ram_block1a3.PORTAADDR5 +address_a[5] => ram_block1a4.PORTAADDR5 +address_a[5] => ram_block1a5.PORTAADDR5 +address_a[5] => ram_block1a6.PORTAADDR5 +address_a[5] => ram_block1a7.PORTAADDR5 +address_a[5] => ram_block1a8.PORTAADDR5 +address_a[5] => ram_block1a9.PORTAADDR5 +address_a[5] => ram_block1a10.PORTAADDR5 +address_a[5] => ram_block1a11.PORTAADDR5 +address_a[5] => ram_block1a12.PORTAADDR5 +address_a[5] => ram_block1a13.PORTAADDR5 +address_a[5] => ram_block1a14.PORTAADDR5 +address_a[5] => ram_block1a15.PORTAADDR5 +address_a[5] => ram_block1a16.PORTAADDR5 +address_a[5] => ram_block1a17.PORTAADDR5 +address_a[5] => ram_block1a18.PORTAADDR5 +address_a[5] => ram_block1a19.PORTAADDR5 +address_a[5] => ram_block1a20.PORTAADDR5 +address_a[5] => ram_block1a21.PORTAADDR5 +address_a[5] => ram_block1a22.PORTAADDR5 +address_a[5] => ram_block1a23.PORTAADDR5 +address_a[5] => ram_block1a24.PORTAADDR5 +address_a[5] => ram_block1a25.PORTAADDR5 +address_a[5] => ram_block1a26.PORTAADDR5 +address_a[5] => ram_block1a27.PORTAADDR5 +address_a[5] => ram_block1a28.PORTAADDR5 +address_a[5] => ram_block1a29.PORTAADDR5 +address_a[5] => ram_block1a30.PORTAADDR5 +address_a[5] => ram_block1a31.PORTAADDR5 +address_a[6] => ram_block1a0.PORTAADDR6 +address_a[6] => ram_block1a1.PORTAADDR6 +address_a[6] => ram_block1a2.PORTAADDR6 +address_a[6] => ram_block1a3.PORTAADDR6 +address_a[6] => ram_block1a4.PORTAADDR6 +address_a[6] => ram_block1a5.PORTAADDR6 +address_a[6] => ram_block1a6.PORTAADDR6 +address_a[6] => ram_block1a7.PORTAADDR6 +address_a[6] => ram_block1a8.PORTAADDR6 +address_a[6] => ram_block1a9.PORTAADDR6 +address_a[6] => ram_block1a10.PORTAADDR6 +address_a[6] => ram_block1a11.PORTAADDR6 +address_a[6] => ram_block1a12.PORTAADDR6 +address_a[6] => ram_block1a13.PORTAADDR6 +address_a[6] => ram_block1a14.PORTAADDR6 +address_a[6] => ram_block1a15.PORTAADDR6 +address_a[6] => ram_block1a16.PORTAADDR6 +address_a[6] => ram_block1a17.PORTAADDR6 +address_a[6] => ram_block1a18.PORTAADDR6 +address_a[6] => ram_block1a19.PORTAADDR6 +address_a[6] => ram_block1a20.PORTAADDR6 +address_a[6] => ram_block1a21.PORTAADDR6 +address_a[6] => ram_block1a22.PORTAADDR6 +address_a[6] => ram_block1a23.PORTAADDR6 +address_a[6] => ram_block1a24.PORTAADDR6 +address_a[6] => ram_block1a25.PORTAADDR6 +address_a[6] => ram_block1a26.PORTAADDR6 +address_a[6] => ram_block1a27.PORTAADDR6 +address_a[6] => ram_block1a28.PORTAADDR6 +address_a[6] => ram_block1a29.PORTAADDR6 +address_a[6] => ram_block1a30.PORTAADDR6 +address_a[6] => ram_block1a31.PORTAADDR6 +address_a[7] => ram_block1a0.PORTAADDR7 +address_a[7] => ram_block1a1.PORTAADDR7 +address_a[7] => ram_block1a2.PORTAADDR7 +address_a[7] => ram_block1a3.PORTAADDR7 +address_a[7] => ram_block1a4.PORTAADDR7 +address_a[7] => ram_block1a5.PORTAADDR7 +address_a[7] => ram_block1a6.PORTAADDR7 +address_a[7] => ram_block1a7.PORTAADDR7 +address_a[7] => ram_block1a8.PORTAADDR7 +address_a[7] => ram_block1a9.PORTAADDR7 +address_a[7] => ram_block1a10.PORTAADDR7 +address_a[7] => ram_block1a11.PORTAADDR7 +address_a[7] => ram_block1a12.PORTAADDR7 +address_a[7] => ram_block1a13.PORTAADDR7 +address_a[7] => ram_block1a14.PORTAADDR7 +address_a[7] => ram_block1a15.PORTAADDR7 +address_a[7] => ram_block1a16.PORTAADDR7 +address_a[7] => ram_block1a17.PORTAADDR7 +address_a[7] => ram_block1a18.PORTAADDR7 +address_a[7] => ram_block1a19.PORTAADDR7 +address_a[7] => ram_block1a20.PORTAADDR7 +address_a[7] => ram_block1a21.PORTAADDR7 +address_a[7] => ram_block1a22.PORTAADDR7 +address_a[7] => ram_block1a23.PORTAADDR7 +address_a[7] => ram_block1a24.PORTAADDR7 +address_a[7] => ram_block1a25.PORTAADDR7 +address_a[7] => ram_block1a26.PORTAADDR7 +address_a[7] => ram_block1a27.PORTAADDR7 +address_a[7] => ram_block1a28.PORTAADDR7 +address_a[7] => ram_block1a29.PORTAADDR7 +address_a[7] => ram_block1a30.PORTAADDR7 +address_a[7] => ram_block1a31.PORTAADDR7 +address_a[8] => ram_block1a0.PORTAADDR8 +address_a[8] => ram_block1a1.PORTAADDR8 +address_a[8] => ram_block1a2.PORTAADDR8 +address_a[8] => ram_block1a3.PORTAADDR8 +address_a[8] => ram_block1a4.PORTAADDR8 +address_a[8] => ram_block1a5.PORTAADDR8 +address_a[8] => ram_block1a6.PORTAADDR8 +address_a[8] => ram_block1a7.PORTAADDR8 +address_a[8] => ram_block1a8.PORTAADDR8 +address_a[8] => ram_block1a9.PORTAADDR8 +address_a[8] => ram_block1a10.PORTAADDR8 +address_a[8] => ram_block1a11.PORTAADDR8 +address_a[8] => ram_block1a12.PORTAADDR8 +address_a[8] => ram_block1a13.PORTAADDR8 +address_a[8] => ram_block1a14.PORTAADDR8 +address_a[8] => ram_block1a15.PORTAADDR8 +address_a[8] => ram_block1a16.PORTAADDR8 +address_a[8] => ram_block1a17.PORTAADDR8 +address_a[8] => ram_block1a18.PORTAADDR8 +address_a[8] => ram_block1a19.PORTAADDR8 +address_a[8] => ram_block1a20.PORTAADDR8 +address_a[8] => ram_block1a21.PORTAADDR8 +address_a[8] => ram_block1a22.PORTAADDR8 +address_a[8] => ram_block1a23.PORTAADDR8 +address_a[8] => ram_block1a24.PORTAADDR8 +address_a[8] => ram_block1a25.PORTAADDR8 +address_a[8] => ram_block1a26.PORTAADDR8 +address_a[8] => ram_block1a27.PORTAADDR8 +address_a[8] => ram_block1a28.PORTAADDR8 +address_a[8] => ram_block1a29.PORTAADDR8 +address_a[8] => ram_block1a30.PORTAADDR8 +address_a[8] => ram_block1a31.PORTAADDR8 +address_a[9] => ram_block1a0.PORTAADDR9 +address_a[9] => ram_block1a1.PORTAADDR9 +address_a[9] => ram_block1a2.PORTAADDR9 +address_a[9] => ram_block1a3.PORTAADDR9 +address_a[9] => ram_block1a4.PORTAADDR9 +address_a[9] => ram_block1a5.PORTAADDR9 +address_a[9] => ram_block1a6.PORTAADDR9 +address_a[9] => ram_block1a7.PORTAADDR9 +address_a[9] => ram_block1a8.PORTAADDR9 +address_a[9] => ram_block1a9.PORTAADDR9 +address_a[9] => ram_block1a10.PORTAADDR9 +address_a[9] => ram_block1a11.PORTAADDR9 +address_a[9] => ram_block1a12.PORTAADDR9 +address_a[9] => ram_block1a13.PORTAADDR9 +address_a[9] => ram_block1a14.PORTAADDR9 +address_a[9] => ram_block1a15.PORTAADDR9 +address_a[9] => ram_block1a16.PORTAADDR9 +address_a[9] => ram_block1a17.PORTAADDR9 +address_a[9] => ram_block1a18.PORTAADDR9 +address_a[9] => ram_block1a19.PORTAADDR9 +address_a[9] => ram_block1a20.PORTAADDR9 +address_a[9] => ram_block1a21.PORTAADDR9 +address_a[9] => ram_block1a22.PORTAADDR9 +address_a[9] => ram_block1a23.PORTAADDR9 +address_a[9] => ram_block1a24.PORTAADDR9 +address_a[9] => ram_block1a25.PORTAADDR9 +address_a[9] => ram_block1a26.PORTAADDR9 +address_a[9] => ram_block1a27.PORTAADDR9 +address_a[9] => ram_block1a28.PORTAADDR9 +address_a[9] => ram_block1a29.PORTAADDR9 +address_a[9] => ram_block1a30.PORTAADDR9 +address_a[9] => ram_block1a31.PORTAADDR9 +address_a[10] => ram_block1a0.PORTAADDR10 +address_a[10] => ram_block1a1.PORTAADDR10 +address_a[10] => ram_block1a2.PORTAADDR10 +address_a[10] => ram_block1a3.PORTAADDR10 +address_a[10] => ram_block1a4.PORTAADDR10 +address_a[10] => ram_block1a5.PORTAADDR10 +address_a[10] => ram_block1a6.PORTAADDR10 +address_a[10] => ram_block1a7.PORTAADDR10 +address_a[10] => ram_block1a8.PORTAADDR10 +address_a[10] => ram_block1a9.PORTAADDR10 +address_a[10] => ram_block1a10.PORTAADDR10 +address_a[10] => ram_block1a11.PORTAADDR10 +address_a[10] => ram_block1a12.PORTAADDR10 +address_a[10] => ram_block1a13.PORTAADDR10 +address_a[10] => ram_block1a14.PORTAADDR10 +address_a[10] => ram_block1a15.PORTAADDR10 +address_a[10] => ram_block1a16.PORTAADDR10 +address_a[10] => ram_block1a17.PORTAADDR10 +address_a[10] => ram_block1a18.PORTAADDR10 +address_a[10] => ram_block1a19.PORTAADDR10 +address_a[10] => ram_block1a20.PORTAADDR10 +address_a[10] => ram_block1a21.PORTAADDR10 +address_a[10] => ram_block1a22.PORTAADDR10 +address_a[10] => ram_block1a23.PORTAADDR10 +address_a[10] => ram_block1a24.PORTAADDR10 +address_a[10] => ram_block1a25.PORTAADDR10 +address_a[10] => ram_block1a26.PORTAADDR10 +address_a[10] => ram_block1a27.PORTAADDR10 +address_a[10] => ram_block1a28.PORTAADDR10 +address_a[10] => ram_block1a29.PORTAADDR10 +address_a[10] => ram_block1a30.PORTAADDR10 +address_a[10] => ram_block1a31.PORTAADDR10 +address_b[0] => ram_block1a0.PORTBADDR +address_b[0] => ram_block1a1.PORTBADDR +address_b[0] => ram_block1a2.PORTBADDR +address_b[0] => ram_block1a3.PORTBADDR +address_b[0] => ram_block1a4.PORTBADDR +address_b[0] => ram_block1a5.PORTBADDR +address_b[0] => ram_block1a6.PORTBADDR +address_b[0] => ram_block1a7.PORTBADDR +address_b[0] => ram_block1a8.PORTBADDR +address_b[0] => ram_block1a9.PORTBADDR +address_b[0] => ram_block1a10.PORTBADDR +address_b[0] => ram_block1a11.PORTBADDR +address_b[0] => ram_block1a12.PORTBADDR +address_b[0] => ram_block1a13.PORTBADDR +address_b[0] => ram_block1a14.PORTBADDR +address_b[0] => ram_block1a15.PORTBADDR +address_b[0] => ram_block1a16.PORTBADDR +address_b[0] => ram_block1a17.PORTBADDR +address_b[0] => ram_block1a18.PORTBADDR +address_b[0] => ram_block1a19.PORTBADDR +address_b[0] => ram_block1a20.PORTBADDR +address_b[0] => ram_block1a21.PORTBADDR +address_b[0] => ram_block1a22.PORTBADDR +address_b[0] => ram_block1a23.PORTBADDR +address_b[0] => ram_block1a24.PORTBADDR +address_b[0] => ram_block1a25.PORTBADDR +address_b[0] => ram_block1a26.PORTBADDR +address_b[0] => ram_block1a27.PORTBADDR +address_b[0] => ram_block1a28.PORTBADDR +address_b[0] => ram_block1a29.PORTBADDR +address_b[0] => ram_block1a30.PORTBADDR +address_b[0] => ram_block1a31.PORTBADDR +address_b[1] => ram_block1a0.PORTBADDR1 +address_b[1] => ram_block1a1.PORTBADDR1 +address_b[1] => ram_block1a2.PORTBADDR1 +address_b[1] => ram_block1a3.PORTBADDR1 +address_b[1] => ram_block1a4.PORTBADDR1 +address_b[1] => ram_block1a5.PORTBADDR1 +address_b[1] => ram_block1a6.PORTBADDR1 +address_b[1] => ram_block1a7.PORTBADDR1 +address_b[1] => ram_block1a8.PORTBADDR1 +address_b[1] => ram_block1a9.PORTBADDR1 +address_b[1] => ram_block1a10.PORTBADDR1 +address_b[1] => ram_block1a11.PORTBADDR1 +address_b[1] => ram_block1a12.PORTBADDR1 +address_b[1] => ram_block1a13.PORTBADDR1 +address_b[1] => ram_block1a14.PORTBADDR1 +address_b[1] => ram_block1a15.PORTBADDR1 +address_b[1] => ram_block1a16.PORTBADDR1 +address_b[1] => ram_block1a17.PORTBADDR1 +address_b[1] => ram_block1a18.PORTBADDR1 +address_b[1] => ram_block1a19.PORTBADDR1 +address_b[1] => ram_block1a20.PORTBADDR1 +address_b[1] => ram_block1a21.PORTBADDR1 +address_b[1] => ram_block1a22.PORTBADDR1 +address_b[1] => ram_block1a23.PORTBADDR1 +address_b[1] => ram_block1a24.PORTBADDR1 +address_b[1] => ram_block1a25.PORTBADDR1 +address_b[1] => ram_block1a26.PORTBADDR1 +address_b[1] => ram_block1a27.PORTBADDR1 +address_b[1] => ram_block1a28.PORTBADDR1 +address_b[1] => ram_block1a29.PORTBADDR1 +address_b[1] => ram_block1a30.PORTBADDR1 +address_b[1] => ram_block1a31.PORTBADDR1 +address_b[2] => ram_block1a0.PORTBADDR2 +address_b[2] => ram_block1a1.PORTBADDR2 +address_b[2] => ram_block1a2.PORTBADDR2 +address_b[2] => ram_block1a3.PORTBADDR2 +address_b[2] => ram_block1a4.PORTBADDR2 +address_b[2] => ram_block1a5.PORTBADDR2 +address_b[2] => ram_block1a6.PORTBADDR2 +address_b[2] => ram_block1a7.PORTBADDR2 +address_b[2] => ram_block1a8.PORTBADDR2 +address_b[2] => ram_block1a9.PORTBADDR2 +address_b[2] => ram_block1a10.PORTBADDR2 +address_b[2] => ram_block1a11.PORTBADDR2 +address_b[2] => ram_block1a12.PORTBADDR2 +address_b[2] => ram_block1a13.PORTBADDR2 +address_b[2] => ram_block1a14.PORTBADDR2 +address_b[2] => ram_block1a15.PORTBADDR2 +address_b[2] => ram_block1a16.PORTBADDR2 +address_b[2] => ram_block1a17.PORTBADDR2 +address_b[2] => ram_block1a18.PORTBADDR2 +address_b[2] => ram_block1a19.PORTBADDR2 +address_b[2] => ram_block1a20.PORTBADDR2 +address_b[2] => ram_block1a21.PORTBADDR2 +address_b[2] => ram_block1a22.PORTBADDR2 +address_b[2] => ram_block1a23.PORTBADDR2 +address_b[2] => ram_block1a24.PORTBADDR2 +address_b[2] => ram_block1a25.PORTBADDR2 +address_b[2] => ram_block1a26.PORTBADDR2 +address_b[2] => ram_block1a27.PORTBADDR2 +address_b[2] => ram_block1a28.PORTBADDR2 +address_b[2] => ram_block1a29.PORTBADDR2 +address_b[2] => ram_block1a30.PORTBADDR2 +address_b[2] => ram_block1a31.PORTBADDR2 +address_b[3] => ram_block1a0.PORTBADDR3 +address_b[3] => ram_block1a1.PORTBADDR3 +address_b[3] => ram_block1a2.PORTBADDR3 +address_b[3] => ram_block1a3.PORTBADDR3 +address_b[3] => ram_block1a4.PORTBADDR3 +address_b[3] => ram_block1a5.PORTBADDR3 +address_b[3] => ram_block1a6.PORTBADDR3 +address_b[3] => ram_block1a7.PORTBADDR3 +address_b[3] => ram_block1a8.PORTBADDR3 +address_b[3] => ram_block1a9.PORTBADDR3 +address_b[3] => ram_block1a10.PORTBADDR3 +address_b[3] => ram_block1a11.PORTBADDR3 +address_b[3] => ram_block1a12.PORTBADDR3 +address_b[3] => ram_block1a13.PORTBADDR3 +address_b[3] => ram_block1a14.PORTBADDR3 +address_b[3] => ram_block1a15.PORTBADDR3 +address_b[3] => ram_block1a16.PORTBADDR3 +address_b[3] => ram_block1a17.PORTBADDR3 +address_b[3] => ram_block1a18.PORTBADDR3 +address_b[3] => ram_block1a19.PORTBADDR3 +address_b[3] => ram_block1a20.PORTBADDR3 +address_b[3] => ram_block1a21.PORTBADDR3 +address_b[3] => ram_block1a22.PORTBADDR3 +address_b[3] => ram_block1a23.PORTBADDR3 +address_b[3] => ram_block1a24.PORTBADDR3 +address_b[3] => ram_block1a25.PORTBADDR3 +address_b[3] => ram_block1a26.PORTBADDR3 +address_b[3] => ram_block1a27.PORTBADDR3 +address_b[3] => ram_block1a28.PORTBADDR3 +address_b[3] => ram_block1a29.PORTBADDR3 +address_b[3] => ram_block1a30.PORTBADDR3 +address_b[3] => ram_block1a31.PORTBADDR3 +address_b[4] => ram_block1a0.PORTBADDR4 +address_b[4] => ram_block1a1.PORTBADDR4 +address_b[4] => ram_block1a2.PORTBADDR4 +address_b[4] => ram_block1a3.PORTBADDR4 +address_b[4] => ram_block1a4.PORTBADDR4 +address_b[4] => ram_block1a5.PORTBADDR4 +address_b[4] => ram_block1a6.PORTBADDR4 +address_b[4] => ram_block1a7.PORTBADDR4 +address_b[4] => ram_block1a8.PORTBADDR4 +address_b[4] => ram_block1a9.PORTBADDR4 +address_b[4] => ram_block1a10.PORTBADDR4 +address_b[4] => ram_block1a11.PORTBADDR4 +address_b[4] => ram_block1a12.PORTBADDR4 +address_b[4] => ram_block1a13.PORTBADDR4 +address_b[4] => ram_block1a14.PORTBADDR4 +address_b[4] => ram_block1a15.PORTBADDR4 +address_b[4] => ram_block1a16.PORTBADDR4 +address_b[4] => ram_block1a17.PORTBADDR4 +address_b[4] => ram_block1a18.PORTBADDR4 +address_b[4] => ram_block1a19.PORTBADDR4 +address_b[4] => ram_block1a20.PORTBADDR4 +address_b[4] => ram_block1a21.PORTBADDR4 +address_b[4] => ram_block1a22.PORTBADDR4 +address_b[4] => ram_block1a23.PORTBADDR4 +address_b[4] => ram_block1a24.PORTBADDR4 +address_b[4] => ram_block1a25.PORTBADDR4 +address_b[4] => ram_block1a26.PORTBADDR4 +address_b[4] => ram_block1a27.PORTBADDR4 +address_b[4] => ram_block1a28.PORTBADDR4 +address_b[4] => ram_block1a29.PORTBADDR4 +address_b[4] => ram_block1a30.PORTBADDR4 +address_b[4] => ram_block1a31.PORTBADDR4 +address_b[5] => ram_block1a0.PORTBADDR5 +address_b[5] => ram_block1a1.PORTBADDR5 +address_b[5] => ram_block1a2.PORTBADDR5 +address_b[5] => ram_block1a3.PORTBADDR5 +address_b[5] => ram_block1a4.PORTBADDR5 +address_b[5] => ram_block1a5.PORTBADDR5 +address_b[5] => ram_block1a6.PORTBADDR5 +address_b[5] => ram_block1a7.PORTBADDR5 +address_b[5] => ram_block1a8.PORTBADDR5 +address_b[5] => ram_block1a9.PORTBADDR5 +address_b[5] => ram_block1a10.PORTBADDR5 +address_b[5] => ram_block1a11.PORTBADDR5 +address_b[5] => ram_block1a12.PORTBADDR5 +address_b[5] => ram_block1a13.PORTBADDR5 +address_b[5] => ram_block1a14.PORTBADDR5 +address_b[5] => ram_block1a15.PORTBADDR5 +address_b[5] => ram_block1a16.PORTBADDR5 +address_b[5] => ram_block1a17.PORTBADDR5 +address_b[5] => ram_block1a18.PORTBADDR5 +address_b[5] => ram_block1a19.PORTBADDR5 +address_b[5] => ram_block1a20.PORTBADDR5 +address_b[5] => ram_block1a21.PORTBADDR5 +address_b[5] => ram_block1a22.PORTBADDR5 +address_b[5] => ram_block1a23.PORTBADDR5 +address_b[5] => ram_block1a24.PORTBADDR5 +address_b[5] => ram_block1a25.PORTBADDR5 +address_b[5] => ram_block1a26.PORTBADDR5 +address_b[5] => ram_block1a27.PORTBADDR5 +address_b[5] => ram_block1a28.PORTBADDR5 +address_b[5] => ram_block1a29.PORTBADDR5 +address_b[5] => ram_block1a30.PORTBADDR5 +address_b[5] => ram_block1a31.PORTBADDR5 +address_b[6] => ram_block1a0.PORTBADDR6 +address_b[6] => ram_block1a1.PORTBADDR6 +address_b[6] => ram_block1a2.PORTBADDR6 +address_b[6] => ram_block1a3.PORTBADDR6 +address_b[6] => ram_block1a4.PORTBADDR6 +address_b[6] => ram_block1a5.PORTBADDR6 +address_b[6] => ram_block1a6.PORTBADDR6 +address_b[6] => ram_block1a7.PORTBADDR6 +address_b[6] => ram_block1a8.PORTBADDR6 +address_b[6] => ram_block1a9.PORTBADDR6 +address_b[6] => ram_block1a10.PORTBADDR6 +address_b[6] => ram_block1a11.PORTBADDR6 +address_b[6] => ram_block1a12.PORTBADDR6 +address_b[6] => ram_block1a13.PORTBADDR6 +address_b[6] => ram_block1a14.PORTBADDR6 +address_b[6] => ram_block1a15.PORTBADDR6 +address_b[6] => ram_block1a16.PORTBADDR6 +address_b[6] => ram_block1a17.PORTBADDR6 +address_b[6] => ram_block1a18.PORTBADDR6 +address_b[6] => ram_block1a19.PORTBADDR6 +address_b[6] => ram_block1a20.PORTBADDR6 +address_b[6] => ram_block1a21.PORTBADDR6 +address_b[6] => ram_block1a22.PORTBADDR6 +address_b[6] => ram_block1a23.PORTBADDR6 +address_b[6] => ram_block1a24.PORTBADDR6 +address_b[6] => ram_block1a25.PORTBADDR6 +address_b[6] => ram_block1a26.PORTBADDR6 +address_b[6] => ram_block1a27.PORTBADDR6 +address_b[6] => ram_block1a28.PORTBADDR6 +address_b[6] => ram_block1a29.PORTBADDR6 +address_b[6] => ram_block1a30.PORTBADDR6 +address_b[6] => ram_block1a31.PORTBADDR6 +address_b[7] => ram_block1a0.PORTBADDR7 +address_b[7] => ram_block1a1.PORTBADDR7 +address_b[7] => ram_block1a2.PORTBADDR7 +address_b[7] => ram_block1a3.PORTBADDR7 +address_b[7] => ram_block1a4.PORTBADDR7 +address_b[7] => ram_block1a5.PORTBADDR7 +address_b[7] => ram_block1a6.PORTBADDR7 +address_b[7] => ram_block1a7.PORTBADDR7 +address_b[7] => ram_block1a8.PORTBADDR7 +address_b[7] => ram_block1a9.PORTBADDR7 +address_b[7] => ram_block1a10.PORTBADDR7 +address_b[7] => ram_block1a11.PORTBADDR7 +address_b[7] => ram_block1a12.PORTBADDR7 +address_b[7] => ram_block1a13.PORTBADDR7 +address_b[7] => ram_block1a14.PORTBADDR7 +address_b[7] => ram_block1a15.PORTBADDR7 +address_b[7] => ram_block1a16.PORTBADDR7 +address_b[7] => ram_block1a17.PORTBADDR7 +address_b[7] => ram_block1a18.PORTBADDR7 +address_b[7] => ram_block1a19.PORTBADDR7 +address_b[7] => ram_block1a20.PORTBADDR7 +address_b[7] => ram_block1a21.PORTBADDR7 +address_b[7] => ram_block1a22.PORTBADDR7 +address_b[7] => ram_block1a23.PORTBADDR7 +address_b[7] => ram_block1a24.PORTBADDR7 +address_b[7] => ram_block1a25.PORTBADDR7 +address_b[7] => ram_block1a26.PORTBADDR7 +address_b[7] => ram_block1a27.PORTBADDR7 +address_b[7] => ram_block1a28.PORTBADDR7 +address_b[7] => ram_block1a29.PORTBADDR7 +address_b[7] => ram_block1a30.PORTBADDR7 +address_b[7] => ram_block1a31.PORTBADDR7 +address_b[8] => ram_block1a0.PORTBADDR8 +address_b[8] => ram_block1a1.PORTBADDR8 +address_b[8] => ram_block1a2.PORTBADDR8 +address_b[8] => ram_block1a3.PORTBADDR8 +address_b[8] => ram_block1a4.PORTBADDR8 +address_b[8] => ram_block1a5.PORTBADDR8 +address_b[8] => ram_block1a6.PORTBADDR8 +address_b[8] => ram_block1a7.PORTBADDR8 +address_b[8] => ram_block1a8.PORTBADDR8 +address_b[8] => ram_block1a9.PORTBADDR8 +address_b[8] => ram_block1a10.PORTBADDR8 +address_b[8] => ram_block1a11.PORTBADDR8 +address_b[8] => ram_block1a12.PORTBADDR8 +address_b[8] => ram_block1a13.PORTBADDR8 +address_b[8] => ram_block1a14.PORTBADDR8 +address_b[8] => ram_block1a15.PORTBADDR8 +address_b[8] => ram_block1a16.PORTBADDR8 +address_b[8] => ram_block1a17.PORTBADDR8 +address_b[8] => ram_block1a18.PORTBADDR8 +address_b[8] => ram_block1a19.PORTBADDR8 +address_b[8] => ram_block1a20.PORTBADDR8 +address_b[8] => ram_block1a21.PORTBADDR8 +address_b[8] => ram_block1a22.PORTBADDR8 +address_b[8] => ram_block1a23.PORTBADDR8 +address_b[8] => ram_block1a24.PORTBADDR8 +address_b[8] => ram_block1a25.PORTBADDR8 +address_b[8] => ram_block1a26.PORTBADDR8 +address_b[8] => ram_block1a27.PORTBADDR8 +address_b[8] => ram_block1a28.PORTBADDR8 +address_b[8] => ram_block1a29.PORTBADDR8 +address_b[8] => ram_block1a30.PORTBADDR8 +address_b[8] => ram_block1a31.PORTBADDR8 +address_b[9] => ram_block1a0.PORTBADDR9 +address_b[9] => ram_block1a1.PORTBADDR9 +address_b[9] => ram_block1a2.PORTBADDR9 +address_b[9] => ram_block1a3.PORTBADDR9 +address_b[9] => ram_block1a4.PORTBADDR9 +address_b[9] => ram_block1a5.PORTBADDR9 +address_b[9] => ram_block1a6.PORTBADDR9 +address_b[9] => ram_block1a7.PORTBADDR9 +address_b[9] => ram_block1a8.PORTBADDR9 +address_b[9] => ram_block1a9.PORTBADDR9 +address_b[9] => ram_block1a10.PORTBADDR9 +address_b[9] => ram_block1a11.PORTBADDR9 +address_b[9] => ram_block1a12.PORTBADDR9 +address_b[9] => ram_block1a13.PORTBADDR9 +address_b[9] => ram_block1a14.PORTBADDR9 +address_b[9] => ram_block1a15.PORTBADDR9 +address_b[9] => ram_block1a16.PORTBADDR9 +address_b[9] => ram_block1a17.PORTBADDR9 +address_b[9] => ram_block1a18.PORTBADDR9 +address_b[9] => ram_block1a19.PORTBADDR9 +address_b[9] => ram_block1a20.PORTBADDR9 +address_b[9] => ram_block1a21.PORTBADDR9 +address_b[9] => ram_block1a22.PORTBADDR9 +address_b[9] => ram_block1a23.PORTBADDR9 +address_b[9] => ram_block1a24.PORTBADDR9 +address_b[9] => ram_block1a25.PORTBADDR9 +address_b[9] => ram_block1a26.PORTBADDR9 +address_b[9] => ram_block1a27.PORTBADDR9 +address_b[9] => ram_block1a28.PORTBADDR9 +address_b[9] => ram_block1a29.PORTBADDR9 +address_b[9] => ram_block1a30.PORTBADDR9 +address_b[9] => ram_block1a31.PORTBADDR9 +address_b[10] => ram_block1a0.PORTBADDR10 +address_b[10] => ram_block1a1.PORTBADDR10 +address_b[10] => ram_block1a2.PORTBADDR10 +address_b[10] => ram_block1a3.PORTBADDR10 +address_b[10] => ram_block1a4.PORTBADDR10 +address_b[10] => ram_block1a5.PORTBADDR10 +address_b[10] => ram_block1a6.PORTBADDR10 +address_b[10] => ram_block1a7.PORTBADDR10 +address_b[10] => ram_block1a8.PORTBADDR10 +address_b[10] => ram_block1a9.PORTBADDR10 +address_b[10] => ram_block1a10.PORTBADDR10 +address_b[10] => ram_block1a11.PORTBADDR10 +address_b[10] => ram_block1a12.PORTBADDR10 +address_b[10] => ram_block1a13.PORTBADDR10 +address_b[10] => ram_block1a14.PORTBADDR10 +address_b[10] => ram_block1a15.PORTBADDR10 +address_b[10] => ram_block1a16.PORTBADDR10 +address_b[10] => ram_block1a17.PORTBADDR10 +address_b[10] => ram_block1a18.PORTBADDR10 +address_b[10] => ram_block1a19.PORTBADDR10 +address_b[10] => ram_block1a20.PORTBADDR10 +address_b[10] => ram_block1a21.PORTBADDR10 +address_b[10] => ram_block1a22.PORTBADDR10 +address_b[10] => ram_block1a23.PORTBADDR10 +address_b[10] => ram_block1a24.PORTBADDR10 +address_b[10] => ram_block1a25.PORTBADDR10 +address_b[10] => ram_block1a26.PORTBADDR10 +address_b[10] => ram_block1a27.PORTBADDR10 +address_b[10] => ram_block1a28.PORTBADDR10 +address_b[10] => ram_block1a29.PORTBADDR10 +address_b[10] => ram_block1a30.PORTBADDR10 +address_b[10] => ram_block1a31.PORTBADDR10 +clock0 => ram_block1a0.CLK0 +clock0 => ram_block1a0.CLK1 +clock0 => ram_block1a1.CLK0 +clock0 => ram_block1a1.CLK1 +clock0 => ram_block1a2.CLK0 +clock0 => ram_block1a2.CLK1 +clock0 => ram_block1a3.CLK0 +clock0 => ram_block1a3.CLK1 +clock0 => ram_block1a4.CLK0 +clock0 => ram_block1a4.CLK1 +clock0 => ram_block1a5.CLK0 +clock0 => ram_block1a5.CLK1 +clock0 => ram_block1a6.CLK0 +clock0 => ram_block1a6.CLK1 +clock0 => ram_block1a7.CLK0 +clock0 => ram_block1a7.CLK1 +clock0 => ram_block1a8.CLK0 +clock0 => ram_block1a8.CLK1 +clock0 => ram_block1a9.CLK0 +clock0 => ram_block1a9.CLK1 +clock0 => ram_block1a10.CLK0 +clock0 => ram_block1a10.CLK1 +clock0 => ram_block1a11.CLK0 +clock0 => ram_block1a11.CLK1 +clock0 => ram_block1a12.CLK0 +clock0 => ram_block1a12.CLK1 +clock0 => ram_block1a13.CLK0 +clock0 => ram_block1a13.CLK1 +clock0 => ram_block1a14.CLK0 +clock0 => ram_block1a14.CLK1 +clock0 => ram_block1a15.CLK0 +clock0 => ram_block1a15.CLK1 +clock0 => ram_block1a16.CLK0 +clock0 => ram_block1a16.CLK1 +clock0 => ram_block1a17.CLK0 +clock0 => ram_block1a17.CLK1 +clock0 => ram_block1a18.CLK0 +clock0 => ram_block1a18.CLK1 +clock0 => ram_block1a19.CLK0 +clock0 => ram_block1a19.CLK1 +clock0 => ram_block1a20.CLK0 +clock0 => ram_block1a20.CLK1 +clock0 => ram_block1a21.CLK0 +clock0 => ram_block1a21.CLK1 +clock0 => ram_block1a22.CLK0 +clock0 => ram_block1a22.CLK1 +clock0 => ram_block1a23.CLK0 +clock0 => ram_block1a23.CLK1 +clock0 => ram_block1a24.CLK0 +clock0 => ram_block1a24.CLK1 +clock0 => ram_block1a25.CLK0 +clock0 => ram_block1a25.CLK1 +clock0 => ram_block1a26.CLK0 +clock0 => ram_block1a26.CLK1 +clock0 => ram_block1a27.CLK0 +clock0 => ram_block1a27.CLK1 +clock0 => ram_block1a28.CLK0 +clock0 => ram_block1a28.CLK1 +clock0 => ram_block1a29.CLK0 +clock0 => ram_block1a29.CLK1 +clock0 => ram_block1a30.CLK0 +clock0 => ram_block1a30.CLK1 +clock0 => ram_block1a31.CLK0 +clock0 => ram_block1a31.CLK1 +clock0 => rden_b_store.CLK +data_a[0] => ram_block1a0.PORTADATAIN +data_a[1] => ram_block1a1.PORTADATAIN +data_a[2] => ram_block1a2.PORTADATAIN +data_a[3] => ram_block1a3.PORTADATAIN +data_a[4] => ram_block1a4.PORTADATAIN +data_a[5] => ram_block1a5.PORTADATAIN +data_a[6] => ram_block1a6.PORTADATAIN +data_a[7] => ram_block1a7.PORTADATAIN +data_a[8] => ram_block1a8.PORTADATAIN +data_a[9] => ram_block1a9.PORTADATAIN +data_a[10] => ram_block1a10.PORTADATAIN +data_a[11] => ram_block1a11.PORTADATAIN +data_a[12] => ram_block1a12.PORTADATAIN +data_a[13] => ram_block1a13.PORTADATAIN +data_a[14] => ram_block1a14.PORTADATAIN +data_a[15] => ram_block1a15.PORTADATAIN +data_a[16] => ram_block1a16.PORTADATAIN +data_a[17] => ram_block1a17.PORTADATAIN +data_a[18] => ram_block1a18.PORTADATAIN +data_a[19] => ram_block1a19.PORTADATAIN +data_a[20] => ram_block1a20.PORTADATAIN +data_a[21] => ram_block1a21.PORTADATAIN +data_a[22] => ram_block1a22.PORTADATAIN +data_a[23] => ram_block1a23.PORTADATAIN +data_a[24] => ram_block1a24.PORTADATAIN +data_a[25] => ram_block1a25.PORTADATAIN +data_a[26] => ram_block1a26.PORTADATAIN +data_a[27] => ram_block1a27.PORTADATAIN +data_a[28] => ram_block1a28.PORTADATAIN +data_a[29] => ram_block1a29.PORTADATAIN +data_a[30] => ram_block1a30.PORTADATAIN +data_a[31] => ram_block1a31.PORTADATAIN +q_b[0] <= ram_block1a0.PORTBDATAOUT +q_b[1] <= ram_block1a1.PORTBDATAOUT +q_b[2] <= ram_block1a2.PORTBDATAOUT +q_b[3] <= ram_block1a3.PORTBDATAOUT +q_b[4] <= ram_block1a4.PORTBDATAOUT +q_b[5] <= ram_block1a5.PORTBDATAOUT +q_b[6] <= ram_block1a6.PORTBDATAOUT +q_b[7] <= ram_block1a7.PORTBDATAOUT +q_b[8] <= ram_block1a8.PORTBDATAOUT +q_b[9] <= ram_block1a9.PORTBDATAOUT +q_b[10] <= ram_block1a10.PORTBDATAOUT +q_b[11] <= ram_block1a11.PORTBDATAOUT +q_b[12] <= ram_block1a12.PORTBDATAOUT +q_b[13] <= ram_block1a13.PORTBDATAOUT +q_b[14] <= ram_block1a14.PORTBDATAOUT +q_b[15] <= ram_block1a15.PORTBDATAOUT +q_b[16] <= ram_block1a16.PORTBDATAOUT +q_b[17] <= ram_block1a17.PORTBDATAOUT +q_b[18] <= ram_block1a18.PORTBDATAOUT +q_b[19] <= ram_block1a19.PORTBDATAOUT +q_b[20] <= ram_block1a20.PORTBDATAOUT +q_b[21] <= ram_block1a21.PORTBDATAOUT +q_b[22] <= ram_block1a22.PORTBDATAOUT +q_b[23] <= ram_block1a23.PORTBDATAOUT +q_b[24] <= ram_block1a24.PORTBDATAOUT +q_b[25] <= ram_block1a25.PORTBDATAOUT +q_b[26] <= ram_block1a26.PORTBDATAOUT +q_b[27] <= ram_block1a27.PORTBDATAOUT +q_b[28] <= ram_block1a28.PORTBDATAOUT +q_b[29] <= ram_block1a29.PORTBDATAOUT +q_b[30] <= ram_block1a30.PORTBDATAOUT +q_b[31] <= ram_block1a31.PORTBDATAOUT +rden_b => ram_block1a0.IN1 +rden_b => ram_block1a0.PORTBRE +rden_b => ram_block1a1.PORTBRE +rden_b => ram_block1a2.PORTBRE +rden_b => ram_block1a3.PORTBRE +rden_b => ram_block1a4.PORTBRE +rden_b => ram_block1a5.PORTBRE +rden_b => ram_block1a6.PORTBRE +rden_b => ram_block1a7.PORTBRE +rden_b => ram_block1a8.PORTBRE +rden_b => ram_block1a9.PORTBRE +rden_b => ram_block1a10.PORTBRE +rden_b => ram_block1a11.PORTBRE +rden_b => ram_block1a12.PORTBRE +rden_b => ram_block1a13.PORTBRE +rden_b => ram_block1a14.PORTBRE +rden_b => ram_block1a15.PORTBRE +rden_b => ram_block1a16.PORTBRE +rden_b => ram_block1a17.PORTBRE +rden_b => ram_block1a18.PORTBRE +rden_b => ram_block1a19.PORTBRE +rden_b => ram_block1a20.PORTBRE +rden_b => ram_block1a21.PORTBRE +rden_b => ram_block1a22.PORTBRE +rden_b => ram_block1a23.PORTBRE +rden_b => ram_block1a24.PORTBRE +rden_b => ram_block1a25.PORTBRE +rden_b => ram_block1a26.PORTBRE +rden_b => ram_block1a27.PORTBRE +rden_b => ram_block1a28.PORTBRE +rden_b => ram_block1a29.PORTBRE +rden_b => ram_block1a30.PORTBRE +rden_b => ram_block1a31.PORTBRE +rden_b => rden_b_store.DATAIN +wren_a => ram_block1a0.PORTAWE +wren_a => ram_block1a0.ENA0 +wren_a => ram_block1a1.PORTAWE +wren_a => ram_block1a1.ENA0 +wren_a => ram_block1a2.PORTAWE +wren_a => ram_block1a2.ENA0 +wren_a => ram_block1a3.PORTAWE +wren_a => ram_block1a3.ENA0 +wren_a => ram_block1a4.PORTAWE +wren_a => ram_block1a4.ENA0 +wren_a => ram_block1a5.PORTAWE +wren_a => ram_block1a5.ENA0 +wren_a => ram_block1a6.PORTAWE +wren_a => ram_block1a6.ENA0 +wren_a => ram_block1a7.PORTAWE +wren_a => ram_block1a7.ENA0 +wren_a => ram_block1a8.PORTAWE +wren_a => ram_block1a8.ENA0 +wren_a => ram_block1a9.PORTAWE +wren_a => ram_block1a9.ENA0 +wren_a => ram_block1a10.PORTAWE +wren_a => ram_block1a10.ENA0 +wren_a => ram_block1a11.PORTAWE +wren_a => ram_block1a11.ENA0 +wren_a => ram_block1a12.PORTAWE +wren_a => ram_block1a12.ENA0 +wren_a => ram_block1a13.PORTAWE +wren_a => ram_block1a13.ENA0 +wren_a => ram_block1a14.PORTAWE +wren_a => ram_block1a14.ENA0 +wren_a => ram_block1a15.PORTAWE +wren_a => ram_block1a15.ENA0 +wren_a => ram_block1a16.PORTAWE +wren_a => ram_block1a16.ENA0 +wren_a => ram_block1a17.PORTAWE +wren_a => ram_block1a17.ENA0 +wren_a => ram_block1a18.PORTAWE +wren_a => ram_block1a18.ENA0 +wren_a => ram_block1a19.PORTAWE +wren_a => ram_block1a19.ENA0 +wren_a => ram_block1a20.PORTAWE +wren_a => ram_block1a20.ENA0 +wren_a => ram_block1a21.PORTAWE +wren_a => ram_block1a21.ENA0 +wren_a => ram_block1a22.PORTAWE +wren_a => ram_block1a22.ENA0 +wren_a => ram_block1a23.PORTAWE +wren_a => ram_block1a23.ENA0 +wren_a => ram_block1a24.PORTAWE +wren_a => ram_block1a24.ENA0 +wren_a => ram_block1a25.PORTAWE +wren_a => ram_block1a25.ENA0 +wren_a => ram_block1a26.PORTAWE +wren_a => ram_block1a26.ENA0 +wren_a => ram_block1a27.PORTAWE +wren_a => ram_block1a27.ENA0 +wren_a => ram_block1a28.PORTAWE +wren_a => ram_block1a28.ENA0 +wren_a => ram_block1a29.PORTAWE +wren_a => ram_block1a29.ENA0 +wren_a => ram_block1a30.PORTAWE +wren_a => ram_block1a30.ENA0 +wren_a => ram_block1a31.PORTAWE +wren_a => ram_block1a31.ENA0 + + +|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag +clock => clock.IN1 +data[0] => data[0].IN1 +data[1] => data[1].IN1 +data[2] => data[2].IN1 +data[3] => data[3].IN1 +data[4] => data[4].IN1 +data[5] => data[5].IN1 +data[6] => data[6].IN1 +data[7] => data[7].IN1 +data[8] => data[8].IN1 +data[9] => data[9].IN1 +data[10] => data[10].IN1 +data[11] => data[11].IN1 +data[12] => data[12].IN1 +data[13] => data[13].IN1 +data[14] => data[14].IN1 +data[15] => data[15].IN1 +data[16] => data[16].IN1 +data[17] => data[17].IN1 +data[18] => data[18].IN1 +data[19] => data[19].IN1 +data[20] => data[20].IN1 +rdaddress[0] => rdaddress[0].IN1 +rdaddress[1] => rdaddress[1].IN1 +rdaddress[2] => rdaddress[2].IN1 +rdaddress[3] => rdaddress[3].IN1 +rdaddress[4] => rdaddress[4].IN1 +rdaddress[5] => rdaddress[5].IN1 +rdaddress[6] => rdaddress[6].IN1 +rdaddress[7] => rdaddress[7].IN1 +rden => rden.IN1 +wraddress[0] => wraddress[0].IN1 +wraddress[1] => wraddress[1].IN1 +wraddress[2] => wraddress[2].IN1 +wraddress[3] => wraddress[3].IN1 +wraddress[4] => wraddress[4].IN1 +wraddress[5] => wraddress[5].IN1 +wraddress[6] => wraddress[6].IN1 +wraddress[7] => wraddress[7].IN1 +wren => wren.IN1 +q[0] <= altsyncram:the_altsyncram.q_b +q[1] <= altsyncram:the_altsyncram.q_b +q[2] <= altsyncram:the_altsyncram.q_b +q[3] <= altsyncram:the_altsyncram.q_b +q[4] <= altsyncram:the_altsyncram.q_b +q[5] <= altsyncram:the_altsyncram.q_b +q[6] <= altsyncram:the_altsyncram.q_b +q[7] <= altsyncram:the_altsyncram.q_b +q[8] <= altsyncram:the_altsyncram.q_b +q[9] <= altsyncram:the_altsyncram.q_b +q[10] <= altsyncram:the_altsyncram.q_b +q[11] <= altsyncram:the_altsyncram.q_b +q[12] <= altsyncram:the_altsyncram.q_b +q[13] <= altsyncram:the_altsyncram.q_b +q[14] <= altsyncram:the_altsyncram.q_b +q[15] <= altsyncram:the_altsyncram.q_b +q[16] <= altsyncram:the_altsyncram.q_b +q[17] <= altsyncram:the_altsyncram.q_b +q[18] <= altsyncram:the_altsyncram.q_b +q[19] <= altsyncram:the_altsyncram.q_b +q[20] <= altsyncram:the_altsyncram.q_b + + +|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram +wren_a => altsyncram_qtg1:auto_generated.wren_a +rden_a => ~NO_FANOUT~ +wren_b => ~NO_FANOUT~ +rden_b => altsyncram_qtg1:auto_generated.rden_b +data_a[0] => altsyncram_qtg1:auto_generated.data_a[0] +data_a[1] => altsyncram_qtg1:auto_generated.data_a[1] +data_a[2] => altsyncram_qtg1:auto_generated.data_a[2] +data_a[3] => altsyncram_qtg1:auto_generated.data_a[3] +data_a[4] => altsyncram_qtg1:auto_generated.data_a[4] +data_a[5] => altsyncram_qtg1:auto_generated.data_a[5] +data_a[6] => altsyncram_qtg1:auto_generated.data_a[6] +data_a[7] => altsyncram_qtg1:auto_generated.data_a[7] +data_a[8] => altsyncram_qtg1:auto_generated.data_a[8] +data_a[9] => altsyncram_qtg1:auto_generated.data_a[9] +data_a[10] => altsyncram_qtg1:auto_generated.data_a[10] +data_a[11] => altsyncram_qtg1:auto_generated.data_a[11] +data_a[12] => altsyncram_qtg1:auto_generated.data_a[12] +data_a[13] => altsyncram_qtg1:auto_generated.data_a[13] +data_a[14] => altsyncram_qtg1:auto_generated.data_a[14] +data_a[15] => altsyncram_qtg1:auto_generated.data_a[15] +data_a[16] => altsyncram_qtg1:auto_generated.data_a[16] +data_a[17] => altsyncram_qtg1:auto_generated.data_a[17] +data_a[18] => altsyncram_qtg1:auto_generated.data_a[18] +data_a[19] => altsyncram_qtg1:auto_generated.data_a[19] +data_a[20] => altsyncram_qtg1:auto_generated.data_a[20] +data_b[0] => ~NO_FANOUT~ +data_b[1] => ~NO_FANOUT~ +data_b[2] => ~NO_FANOUT~ +data_b[3] => ~NO_FANOUT~ +data_b[4] => ~NO_FANOUT~ +data_b[5] => ~NO_FANOUT~ +data_b[6] => ~NO_FANOUT~ +data_b[7] => ~NO_FANOUT~ +data_b[8] => ~NO_FANOUT~ +data_b[9] => ~NO_FANOUT~ +data_b[10] => ~NO_FANOUT~ +data_b[11] => ~NO_FANOUT~ +data_b[12] => ~NO_FANOUT~ +data_b[13] => ~NO_FANOUT~ +data_b[14] => ~NO_FANOUT~ +data_b[15] => ~NO_FANOUT~ +data_b[16] => ~NO_FANOUT~ +data_b[17] => ~NO_FANOUT~ +data_b[18] => ~NO_FANOUT~ +data_b[19] => ~NO_FANOUT~ +data_b[20] => ~NO_FANOUT~ +address_a[0] => altsyncram_qtg1:auto_generated.address_a[0] +address_a[1] => altsyncram_qtg1:auto_generated.address_a[1] +address_a[2] => altsyncram_qtg1:auto_generated.address_a[2] +address_a[3] => altsyncram_qtg1:auto_generated.address_a[3] +address_a[4] => altsyncram_qtg1:auto_generated.address_a[4] +address_a[5] => altsyncram_qtg1:auto_generated.address_a[5] +address_a[6] => altsyncram_qtg1:auto_generated.address_a[6] +address_a[7] => altsyncram_qtg1:auto_generated.address_a[7] +address_b[0] => altsyncram_qtg1:auto_generated.address_b[0] +address_b[1] => altsyncram_qtg1:auto_generated.address_b[1] +address_b[2] => altsyncram_qtg1:auto_generated.address_b[2] +address_b[3] => altsyncram_qtg1:auto_generated.address_b[3] +address_b[4] => altsyncram_qtg1:auto_generated.address_b[4] +address_b[5] => altsyncram_qtg1:auto_generated.address_b[5] +address_b[6] => altsyncram_qtg1:auto_generated.address_b[6] +address_b[7] => altsyncram_qtg1:auto_generated.address_b[7] +addressstall_a => ~NO_FANOUT~ +addressstall_b => ~NO_FANOUT~ +clock0 => altsyncram_qtg1:auto_generated.clock0 +clock1 => ~NO_FANOUT~ +clocken0 => ~NO_FANOUT~ +clocken1 => ~NO_FANOUT~ +clocken2 => ~NO_FANOUT~ +clocken3 => ~NO_FANOUT~ +aclr0 => ~NO_FANOUT~ +aclr1 => ~NO_FANOUT~ +byteena_a[0] => ~NO_FANOUT~ +byteena_b[0] => ~NO_FANOUT~ +q_a[0] <= +q_a[1] <= +q_a[2] <= +q_a[3] <= +q_a[4] <= +q_a[5] <= +q_a[6] <= +q_a[7] <= +q_a[8] <= +q_a[9] <= +q_a[10] <= +q_a[11] <= +q_a[12] <= +q_a[13] <= +q_a[14] <= +q_a[15] <= +q_a[16] <= +q_a[17] <= +q_a[18] <= +q_a[19] <= +q_a[20] <= +q_b[0] <= altsyncram_qtg1:auto_generated.q_b[0] +q_b[1] <= altsyncram_qtg1:auto_generated.q_b[1] +q_b[2] <= altsyncram_qtg1:auto_generated.q_b[2] +q_b[3] <= altsyncram_qtg1:auto_generated.q_b[3] +q_b[4] <= altsyncram_qtg1:auto_generated.q_b[4] +q_b[5] <= altsyncram_qtg1:auto_generated.q_b[5] +q_b[6] <= altsyncram_qtg1:auto_generated.q_b[6] +q_b[7] <= altsyncram_qtg1:auto_generated.q_b[7] +q_b[8] <= altsyncram_qtg1:auto_generated.q_b[8] +q_b[9] <= altsyncram_qtg1:auto_generated.q_b[9] +q_b[10] <= altsyncram_qtg1:auto_generated.q_b[10] +q_b[11] <= altsyncram_qtg1:auto_generated.q_b[11] +q_b[12] <= altsyncram_qtg1:auto_generated.q_b[12] +q_b[13] <= altsyncram_qtg1:auto_generated.q_b[13] +q_b[14] <= altsyncram_qtg1:auto_generated.q_b[14] +q_b[15] <= altsyncram_qtg1:auto_generated.q_b[15] +q_b[16] <= altsyncram_qtg1:auto_generated.q_b[16] +q_b[17] <= altsyncram_qtg1:auto_generated.q_b[17] +q_b[18] <= altsyncram_qtg1:auto_generated.q_b[18] +q_b[19] <= altsyncram_qtg1:auto_generated.q_b[19] +q_b[20] <= altsyncram_qtg1:auto_generated.q_b[20] +eccstatus[0] <= +eccstatus[1] <= +eccstatus[2] <= + + +|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated +address_a[0] => ram_block1a0.PORTAADDR +address_a[0] => ram_block1a1.PORTAADDR +address_a[0] => ram_block1a2.PORTAADDR +address_a[0] => ram_block1a3.PORTAADDR +address_a[0] => ram_block1a4.PORTAADDR +address_a[0] => ram_block1a5.PORTAADDR +address_a[0] => ram_block1a6.PORTAADDR +address_a[0] => ram_block1a7.PORTAADDR +address_a[0] => ram_block1a8.PORTAADDR +address_a[0] => ram_block1a9.PORTAADDR +address_a[0] => ram_block1a10.PORTAADDR +address_a[0] => ram_block1a11.PORTAADDR +address_a[0] => ram_block1a12.PORTAADDR +address_a[0] => ram_block1a13.PORTAADDR +address_a[0] => ram_block1a14.PORTAADDR +address_a[0] => ram_block1a15.PORTAADDR +address_a[0] => ram_block1a16.PORTAADDR +address_a[0] => ram_block1a17.PORTAADDR +address_a[0] => ram_block1a18.PORTAADDR +address_a[0] => ram_block1a19.PORTAADDR +address_a[0] => ram_block1a20.PORTAADDR +address_a[1] => ram_block1a0.PORTAADDR1 +address_a[1] => ram_block1a1.PORTAADDR1 +address_a[1] => ram_block1a2.PORTAADDR1 +address_a[1] => ram_block1a3.PORTAADDR1 +address_a[1] => ram_block1a4.PORTAADDR1 +address_a[1] => ram_block1a5.PORTAADDR1 +address_a[1] => ram_block1a6.PORTAADDR1 +address_a[1] => ram_block1a7.PORTAADDR1 +address_a[1] => ram_block1a8.PORTAADDR1 +address_a[1] => ram_block1a9.PORTAADDR1 +address_a[1] => ram_block1a10.PORTAADDR1 +address_a[1] => ram_block1a11.PORTAADDR1 +address_a[1] => ram_block1a12.PORTAADDR1 +address_a[1] => ram_block1a13.PORTAADDR1 +address_a[1] => ram_block1a14.PORTAADDR1 +address_a[1] => ram_block1a15.PORTAADDR1 +address_a[1] => ram_block1a16.PORTAADDR1 +address_a[1] => ram_block1a17.PORTAADDR1 +address_a[1] => ram_block1a18.PORTAADDR1 +address_a[1] => ram_block1a19.PORTAADDR1 +address_a[1] => ram_block1a20.PORTAADDR1 +address_a[2] => ram_block1a0.PORTAADDR2 +address_a[2] => ram_block1a1.PORTAADDR2 +address_a[2] => ram_block1a2.PORTAADDR2 +address_a[2] => ram_block1a3.PORTAADDR2 +address_a[2] => ram_block1a4.PORTAADDR2 +address_a[2] => ram_block1a5.PORTAADDR2 +address_a[2] => ram_block1a6.PORTAADDR2 +address_a[2] => ram_block1a7.PORTAADDR2 +address_a[2] => ram_block1a8.PORTAADDR2 +address_a[2] => ram_block1a9.PORTAADDR2 +address_a[2] => ram_block1a10.PORTAADDR2 +address_a[2] => ram_block1a11.PORTAADDR2 +address_a[2] => ram_block1a12.PORTAADDR2 +address_a[2] => ram_block1a13.PORTAADDR2 +address_a[2] => ram_block1a14.PORTAADDR2 +address_a[2] => ram_block1a15.PORTAADDR2 +address_a[2] => ram_block1a16.PORTAADDR2 +address_a[2] => ram_block1a17.PORTAADDR2 +address_a[2] => ram_block1a18.PORTAADDR2 +address_a[2] => ram_block1a19.PORTAADDR2 +address_a[2] => ram_block1a20.PORTAADDR2 +address_a[3] => ram_block1a0.PORTAADDR3 +address_a[3] => ram_block1a1.PORTAADDR3 +address_a[3] => ram_block1a2.PORTAADDR3 +address_a[3] => ram_block1a3.PORTAADDR3 +address_a[3] => ram_block1a4.PORTAADDR3 +address_a[3] => ram_block1a5.PORTAADDR3 +address_a[3] => ram_block1a6.PORTAADDR3 +address_a[3] => ram_block1a7.PORTAADDR3 +address_a[3] => ram_block1a8.PORTAADDR3 +address_a[3] => ram_block1a9.PORTAADDR3 +address_a[3] => ram_block1a10.PORTAADDR3 +address_a[3] => ram_block1a11.PORTAADDR3 +address_a[3] => ram_block1a12.PORTAADDR3 +address_a[3] => ram_block1a13.PORTAADDR3 +address_a[3] => ram_block1a14.PORTAADDR3 +address_a[3] => ram_block1a15.PORTAADDR3 +address_a[3] => ram_block1a16.PORTAADDR3 +address_a[3] => ram_block1a17.PORTAADDR3 +address_a[3] => ram_block1a18.PORTAADDR3 +address_a[3] => ram_block1a19.PORTAADDR3 +address_a[3] => ram_block1a20.PORTAADDR3 +address_a[4] => ram_block1a0.PORTAADDR4 +address_a[4] => ram_block1a1.PORTAADDR4 +address_a[4] => ram_block1a2.PORTAADDR4 +address_a[4] => ram_block1a3.PORTAADDR4 +address_a[4] => ram_block1a4.PORTAADDR4 +address_a[4] => ram_block1a5.PORTAADDR4 +address_a[4] => ram_block1a6.PORTAADDR4 +address_a[4] => ram_block1a7.PORTAADDR4 +address_a[4] => ram_block1a8.PORTAADDR4 +address_a[4] => ram_block1a9.PORTAADDR4 +address_a[4] => ram_block1a10.PORTAADDR4 +address_a[4] => ram_block1a11.PORTAADDR4 +address_a[4] => ram_block1a12.PORTAADDR4 +address_a[4] => ram_block1a13.PORTAADDR4 +address_a[4] => ram_block1a14.PORTAADDR4 +address_a[4] => ram_block1a15.PORTAADDR4 +address_a[4] => ram_block1a16.PORTAADDR4 +address_a[4] => ram_block1a17.PORTAADDR4 +address_a[4] => ram_block1a18.PORTAADDR4 +address_a[4] => ram_block1a19.PORTAADDR4 +address_a[4] => ram_block1a20.PORTAADDR4 +address_a[5] => ram_block1a0.PORTAADDR5 +address_a[5] => ram_block1a1.PORTAADDR5 +address_a[5] => ram_block1a2.PORTAADDR5 +address_a[5] => ram_block1a3.PORTAADDR5 +address_a[5] => ram_block1a4.PORTAADDR5 +address_a[5] => ram_block1a5.PORTAADDR5 +address_a[5] => ram_block1a6.PORTAADDR5 +address_a[5] => ram_block1a7.PORTAADDR5 +address_a[5] => ram_block1a8.PORTAADDR5 +address_a[5] => ram_block1a9.PORTAADDR5 +address_a[5] => ram_block1a10.PORTAADDR5 +address_a[5] => ram_block1a11.PORTAADDR5 +address_a[5] => ram_block1a12.PORTAADDR5 +address_a[5] => ram_block1a13.PORTAADDR5 +address_a[5] => ram_block1a14.PORTAADDR5 +address_a[5] => ram_block1a15.PORTAADDR5 +address_a[5] => ram_block1a16.PORTAADDR5 +address_a[5] => ram_block1a17.PORTAADDR5 +address_a[5] => ram_block1a18.PORTAADDR5 +address_a[5] => ram_block1a19.PORTAADDR5 +address_a[5] => ram_block1a20.PORTAADDR5 +address_a[6] => ram_block1a0.PORTAADDR6 +address_a[6] => ram_block1a1.PORTAADDR6 +address_a[6] => ram_block1a2.PORTAADDR6 +address_a[6] => ram_block1a3.PORTAADDR6 +address_a[6] => ram_block1a4.PORTAADDR6 +address_a[6] => ram_block1a5.PORTAADDR6 +address_a[6] => ram_block1a6.PORTAADDR6 +address_a[6] => ram_block1a7.PORTAADDR6 +address_a[6] => ram_block1a8.PORTAADDR6 +address_a[6] => ram_block1a9.PORTAADDR6 +address_a[6] => ram_block1a10.PORTAADDR6 +address_a[6] => ram_block1a11.PORTAADDR6 +address_a[6] => ram_block1a12.PORTAADDR6 +address_a[6] => ram_block1a13.PORTAADDR6 +address_a[6] => ram_block1a14.PORTAADDR6 +address_a[6] => ram_block1a15.PORTAADDR6 +address_a[6] => ram_block1a16.PORTAADDR6 +address_a[6] => ram_block1a17.PORTAADDR6 +address_a[6] => ram_block1a18.PORTAADDR6 +address_a[6] => ram_block1a19.PORTAADDR6 +address_a[6] => ram_block1a20.PORTAADDR6 +address_a[7] => ram_block1a0.PORTAADDR7 +address_a[7] => ram_block1a1.PORTAADDR7 +address_a[7] => ram_block1a2.PORTAADDR7 +address_a[7] => ram_block1a3.PORTAADDR7 +address_a[7] => ram_block1a4.PORTAADDR7 +address_a[7] => ram_block1a5.PORTAADDR7 +address_a[7] => ram_block1a6.PORTAADDR7 +address_a[7] => ram_block1a7.PORTAADDR7 +address_a[7] => ram_block1a8.PORTAADDR7 +address_a[7] => ram_block1a9.PORTAADDR7 +address_a[7] => ram_block1a10.PORTAADDR7 +address_a[7] => ram_block1a11.PORTAADDR7 +address_a[7] => ram_block1a12.PORTAADDR7 +address_a[7] => ram_block1a13.PORTAADDR7 +address_a[7] => ram_block1a14.PORTAADDR7 +address_a[7] => ram_block1a15.PORTAADDR7 +address_a[7] => ram_block1a16.PORTAADDR7 +address_a[7] => ram_block1a17.PORTAADDR7 +address_a[7] => ram_block1a18.PORTAADDR7 +address_a[7] => ram_block1a19.PORTAADDR7 +address_a[7] => ram_block1a20.PORTAADDR7 +address_b[0] => ram_block1a0.PORTBADDR +address_b[0] => ram_block1a1.PORTBADDR +address_b[0] => ram_block1a2.PORTBADDR +address_b[0] => ram_block1a3.PORTBADDR +address_b[0] => ram_block1a4.PORTBADDR +address_b[0] => ram_block1a5.PORTBADDR +address_b[0] => ram_block1a6.PORTBADDR +address_b[0] => ram_block1a7.PORTBADDR +address_b[0] => ram_block1a8.PORTBADDR +address_b[0] => ram_block1a9.PORTBADDR +address_b[0] => ram_block1a10.PORTBADDR +address_b[0] => ram_block1a11.PORTBADDR +address_b[0] => ram_block1a12.PORTBADDR +address_b[0] => ram_block1a13.PORTBADDR +address_b[0] => ram_block1a14.PORTBADDR +address_b[0] => ram_block1a15.PORTBADDR +address_b[0] => ram_block1a16.PORTBADDR +address_b[0] => ram_block1a17.PORTBADDR +address_b[0] => ram_block1a18.PORTBADDR +address_b[0] => ram_block1a19.PORTBADDR +address_b[0] => ram_block1a20.PORTBADDR +address_b[1] => ram_block1a0.PORTBADDR1 +address_b[1] => ram_block1a1.PORTBADDR1 +address_b[1] => ram_block1a2.PORTBADDR1 +address_b[1] => ram_block1a3.PORTBADDR1 +address_b[1] => ram_block1a4.PORTBADDR1 +address_b[1] => ram_block1a5.PORTBADDR1 +address_b[1] => ram_block1a6.PORTBADDR1 +address_b[1] => ram_block1a7.PORTBADDR1 +address_b[1] => ram_block1a8.PORTBADDR1 +address_b[1] => ram_block1a9.PORTBADDR1 +address_b[1] => ram_block1a10.PORTBADDR1 +address_b[1] => ram_block1a11.PORTBADDR1 +address_b[1] => ram_block1a12.PORTBADDR1 +address_b[1] => ram_block1a13.PORTBADDR1 +address_b[1] => ram_block1a14.PORTBADDR1 +address_b[1] => ram_block1a15.PORTBADDR1 +address_b[1] => ram_block1a16.PORTBADDR1 +address_b[1] => ram_block1a17.PORTBADDR1 +address_b[1] => ram_block1a18.PORTBADDR1 +address_b[1] => ram_block1a19.PORTBADDR1 +address_b[1] => ram_block1a20.PORTBADDR1 +address_b[2] => ram_block1a0.PORTBADDR2 +address_b[2] => ram_block1a1.PORTBADDR2 +address_b[2] => ram_block1a2.PORTBADDR2 +address_b[2] => ram_block1a3.PORTBADDR2 +address_b[2] => ram_block1a4.PORTBADDR2 +address_b[2] => ram_block1a5.PORTBADDR2 +address_b[2] => ram_block1a6.PORTBADDR2 +address_b[2] => ram_block1a7.PORTBADDR2 +address_b[2] => ram_block1a8.PORTBADDR2 +address_b[2] => ram_block1a9.PORTBADDR2 +address_b[2] => ram_block1a10.PORTBADDR2 +address_b[2] => ram_block1a11.PORTBADDR2 +address_b[2] => ram_block1a12.PORTBADDR2 +address_b[2] => ram_block1a13.PORTBADDR2 +address_b[2] => ram_block1a14.PORTBADDR2 +address_b[2] => ram_block1a15.PORTBADDR2 +address_b[2] => ram_block1a16.PORTBADDR2 +address_b[2] => ram_block1a17.PORTBADDR2 +address_b[2] => ram_block1a18.PORTBADDR2 +address_b[2] => ram_block1a19.PORTBADDR2 +address_b[2] => ram_block1a20.PORTBADDR2 +address_b[3] => ram_block1a0.PORTBADDR3 +address_b[3] => ram_block1a1.PORTBADDR3 +address_b[3] => ram_block1a2.PORTBADDR3 +address_b[3] => ram_block1a3.PORTBADDR3 +address_b[3] => ram_block1a4.PORTBADDR3 +address_b[3] => ram_block1a5.PORTBADDR3 +address_b[3] => ram_block1a6.PORTBADDR3 +address_b[3] => ram_block1a7.PORTBADDR3 +address_b[3] => ram_block1a8.PORTBADDR3 +address_b[3] => ram_block1a9.PORTBADDR3 +address_b[3] => ram_block1a10.PORTBADDR3 +address_b[3] => ram_block1a11.PORTBADDR3 +address_b[3] => ram_block1a12.PORTBADDR3 +address_b[3] => ram_block1a13.PORTBADDR3 +address_b[3] => ram_block1a14.PORTBADDR3 +address_b[3] => ram_block1a15.PORTBADDR3 +address_b[3] => ram_block1a16.PORTBADDR3 +address_b[3] => ram_block1a17.PORTBADDR3 +address_b[3] => ram_block1a18.PORTBADDR3 +address_b[3] => ram_block1a19.PORTBADDR3 +address_b[3] => ram_block1a20.PORTBADDR3 +address_b[4] => ram_block1a0.PORTBADDR4 +address_b[4] => ram_block1a1.PORTBADDR4 +address_b[4] => ram_block1a2.PORTBADDR4 +address_b[4] => ram_block1a3.PORTBADDR4 +address_b[4] => ram_block1a4.PORTBADDR4 +address_b[4] => ram_block1a5.PORTBADDR4 +address_b[4] => ram_block1a6.PORTBADDR4 +address_b[4] => ram_block1a7.PORTBADDR4 +address_b[4] => ram_block1a8.PORTBADDR4 +address_b[4] => ram_block1a9.PORTBADDR4 +address_b[4] => ram_block1a10.PORTBADDR4 +address_b[4] => ram_block1a11.PORTBADDR4 +address_b[4] => ram_block1a12.PORTBADDR4 +address_b[4] => ram_block1a13.PORTBADDR4 +address_b[4] => ram_block1a14.PORTBADDR4 +address_b[4] => ram_block1a15.PORTBADDR4 +address_b[4] => ram_block1a16.PORTBADDR4 +address_b[4] => ram_block1a17.PORTBADDR4 +address_b[4] => ram_block1a18.PORTBADDR4 +address_b[4] => ram_block1a19.PORTBADDR4 +address_b[4] => ram_block1a20.PORTBADDR4 +address_b[5] => ram_block1a0.PORTBADDR5 +address_b[5] => ram_block1a1.PORTBADDR5 +address_b[5] => ram_block1a2.PORTBADDR5 +address_b[5] => ram_block1a3.PORTBADDR5 +address_b[5] => ram_block1a4.PORTBADDR5 +address_b[5] => ram_block1a5.PORTBADDR5 +address_b[5] => ram_block1a6.PORTBADDR5 +address_b[5] => ram_block1a7.PORTBADDR5 +address_b[5] => ram_block1a8.PORTBADDR5 +address_b[5] => ram_block1a9.PORTBADDR5 +address_b[5] => ram_block1a10.PORTBADDR5 +address_b[5] => ram_block1a11.PORTBADDR5 +address_b[5] => ram_block1a12.PORTBADDR5 +address_b[5] => ram_block1a13.PORTBADDR5 +address_b[5] => ram_block1a14.PORTBADDR5 +address_b[5] => ram_block1a15.PORTBADDR5 +address_b[5] => ram_block1a16.PORTBADDR5 +address_b[5] => ram_block1a17.PORTBADDR5 +address_b[5] => ram_block1a18.PORTBADDR5 +address_b[5] => ram_block1a19.PORTBADDR5 +address_b[5] => ram_block1a20.PORTBADDR5 +address_b[6] => ram_block1a0.PORTBADDR6 +address_b[6] => ram_block1a1.PORTBADDR6 +address_b[6] => ram_block1a2.PORTBADDR6 +address_b[6] => ram_block1a3.PORTBADDR6 +address_b[6] => ram_block1a4.PORTBADDR6 +address_b[6] => ram_block1a5.PORTBADDR6 +address_b[6] => ram_block1a6.PORTBADDR6 +address_b[6] => ram_block1a7.PORTBADDR6 +address_b[6] => ram_block1a8.PORTBADDR6 +address_b[6] => ram_block1a9.PORTBADDR6 +address_b[6] => ram_block1a10.PORTBADDR6 +address_b[6] => ram_block1a11.PORTBADDR6 +address_b[6] => ram_block1a12.PORTBADDR6 +address_b[6] => ram_block1a13.PORTBADDR6 +address_b[6] => ram_block1a14.PORTBADDR6 +address_b[6] => ram_block1a15.PORTBADDR6 +address_b[6] => ram_block1a16.PORTBADDR6 +address_b[6] => ram_block1a17.PORTBADDR6 +address_b[6] => ram_block1a18.PORTBADDR6 +address_b[6] => ram_block1a19.PORTBADDR6 +address_b[6] => ram_block1a20.PORTBADDR6 +address_b[7] => ram_block1a0.PORTBADDR7 +address_b[7] => ram_block1a1.PORTBADDR7 +address_b[7] => ram_block1a2.PORTBADDR7 +address_b[7] => ram_block1a3.PORTBADDR7 +address_b[7] => ram_block1a4.PORTBADDR7 +address_b[7] => ram_block1a5.PORTBADDR7 +address_b[7] => ram_block1a6.PORTBADDR7 +address_b[7] => ram_block1a7.PORTBADDR7 +address_b[7] => ram_block1a8.PORTBADDR7 +address_b[7] => ram_block1a9.PORTBADDR7 +address_b[7] => ram_block1a10.PORTBADDR7 +address_b[7] => ram_block1a11.PORTBADDR7 +address_b[7] => ram_block1a12.PORTBADDR7 +address_b[7] => ram_block1a13.PORTBADDR7 +address_b[7] => ram_block1a14.PORTBADDR7 +address_b[7] => ram_block1a15.PORTBADDR7 +address_b[7] => ram_block1a16.PORTBADDR7 +address_b[7] => ram_block1a17.PORTBADDR7 +address_b[7] => ram_block1a18.PORTBADDR7 +address_b[7] => ram_block1a19.PORTBADDR7 +address_b[7] => ram_block1a20.PORTBADDR7 +clock0 => ram_block1a0.CLK0 +clock0 => ram_block1a1.CLK0 +clock0 => ram_block1a2.CLK0 +clock0 => ram_block1a3.CLK0 +clock0 => ram_block1a4.CLK0 +clock0 => ram_block1a5.CLK0 +clock0 => ram_block1a6.CLK0 +clock0 => ram_block1a7.CLK0 +clock0 => ram_block1a8.CLK0 +clock0 => ram_block1a9.CLK0 +clock0 => ram_block1a10.CLK0 +clock0 => ram_block1a11.CLK0 +clock0 => ram_block1a12.CLK0 +clock0 => ram_block1a13.CLK0 +clock0 => ram_block1a14.CLK0 +clock0 => ram_block1a15.CLK0 +clock0 => ram_block1a16.CLK0 +clock0 => ram_block1a17.CLK0 +clock0 => ram_block1a18.CLK0 +clock0 => ram_block1a19.CLK0 +clock0 => ram_block1a20.CLK0 +data_a[0] => ram_block1a0.PORTADATAIN +data_a[1] => ram_block1a1.PORTADATAIN +data_a[2] => ram_block1a2.PORTADATAIN +data_a[3] => ram_block1a3.PORTADATAIN +data_a[4] => ram_block1a4.PORTADATAIN +data_a[5] => ram_block1a5.PORTADATAIN +data_a[6] => ram_block1a6.PORTADATAIN +data_a[7] => ram_block1a7.PORTADATAIN +data_a[8] => ram_block1a8.PORTADATAIN +data_a[9] => ram_block1a9.PORTADATAIN +data_a[10] => ram_block1a10.PORTADATAIN +data_a[11] => ram_block1a11.PORTADATAIN +data_a[12] => ram_block1a12.PORTADATAIN +data_a[13] => ram_block1a13.PORTADATAIN +data_a[14] => ram_block1a14.PORTADATAIN +data_a[15] => ram_block1a15.PORTADATAIN +data_a[16] => ram_block1a16.PORTADATAIN +data_a[17] => ram_block1a17.PORTADATAIN +data_a[18] => ram_block1a18.PORTADATAIN +data_a[19] => ram_block1a19.PORTADATAIN +data_a[20] => ram_block1a20.PORTADATAIN +q_b[0] <= ram_block1a0.PORTBDATAOUT +q_b[1] <= ram_block1a1.PORTBDATAOUT +q_b[2] <= ram_block1a2.PORTBDATAOUT +q_b[3] <= ram_block1a3.PORTBDATAOUT +q_b[4] <= ram_block1a4.PORTBDATAOUT +q_b[5] <= ram_block1a5.PORTBDATAOUT +q_b[6] <= ram_block1a6.PORTBDATAOUT +q_b[7] <= ram_block1a7.PORTBDATAOUT +q_b[8] <= ram_block1a8.PORTBDATAOUT +q_b[9] <= ram_block1a9.PORTBDATAOUT +q_b[10] <= ram_block1a10.PORTBDATAOUT +q_b[11] <= ram_block1a11.PORTBDATAOUT +q_b[12] <= ram_block1a12.PORTBDATAOUT +q_b[13] <= ram_block1a13.PORTBDATAOUT +q_b[14] <= ram_block1a14.PORTBDATAOUT +q_b[15] <= ram_block1a15.PORTBDATAOUT +q_b[16] <= ram_block1a16.PORTBDATAOUT +q_b[17] <= ram_block1a17.PORTBDATAOUT +q_b[18] <= ram_block1a18.PORTBDATAOUT +q_b[19] <= ram_block1a19.PORTBDATAOUT +q_b[20] <= ram_block1a20.PORTBDATAOUT +rden_b => ram_block1a0.PORTBRE +rden_b => ram_block1a1.PORTBRE +rden_b => ram_block1a2.PORTBRE +rden_b => ram_block1a3.PORTBRE +rden_b => ram_block1a4.PORTBRE +rden_b => ram_block1a5.PORTBRE +rden_b => ram_block1a6.PORTBRE +rden_b => ram_block1a7.PORTBRE +rden_b => ram_block1a8.PORTBRE +rden_b => ram_block1a9.PORTBRE +rden_b => ram_block1a10.PORTBRE +rden_b => ram_block1a11.PORTBRE +rden_b => ram_block1a12.PORTBRE +rden_b => ram_block1a13.PORTBRE +rden_b => ram_block1a14.PORTBRE +rden_b => ram_block1a15.PORTBRE +rden_b => ram_block1a16.PORTBRE +rden_b => ram_block1a17.PORTBRE +rden_b => ram_block1a18.PORTBRE +rden_b => ram_block1a19.PORTBRE +rden_b => ram_block1a20.PORTBRE +wren_a => ram_block1a0.PORTAWE +wren_a => ram_block1a1.PORTAWE +wren_a => ram_block1a2.PORTAWE +wren_a => ram_block1a3.PORTAWE +wren_a => ram_block1a4.PORTAWE +wren_a => ram_block1a5.PORTAWE +wren_a => ram_block1a6.PORTAWE +wren_a => ram_block1a7.PORTAWE +wren_a => ram_block1a8.PORTAWE +wren_a => ram_block1a9.PORTAWE +wren_a => ram_block1a10.PORTAWE +wren_a => ram_block1a11.PORTAWE +wren_a => ram_block1a12.PORTAWE +wren_a => ram_block1a13.PORTAWE +wren_a => ram_block1a14.PORTAWE +wren_a => ram_block1a15.PORTAWE +wren_a => ram_block1a16.PORTAWE +wren_a => ram_block1a17.PORTAWE +wren_a => ram_block1a18.PORTAWE +wren_a => ram_block1a19.PORTAWE +wren_a => ram_block1a20.PORTAWE + + +|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_bht_module:system_cpu_bht +clock => clock.IN1 +data[0] => data[0].IN1 +data[1] => data[1].IN1 +rdaddress[0] => rdaddress[0].IN1 +rdaddress[1] => rdaddress[1].IN1 +rdaddress[2] => rdaddress[2].IN1 +rdaddress[3] => rdaddress[3].IN1 +rdaddress[4] => rdaddress[4].IN1 +rdaddress[5] => rdaddress[5].IN1 +rdaddress[6] => rdaddress[6].IN1 +rdaddress[7] => rdaddress[7].IN1 +rden => rden.IN1 +wraddress[0] => wraddress[0].IN1 +wraddress[1] => wraddress[1].IN1 +wraddress[2] => wraddress[2].IN1 +wraddress[3] => wraddress[3].IN1 +wraddress[4] => wraddress[4].IN1 +wraddress[5] => wraddress[5].IN1 +wraddress[6] => wraddress[6].IN1 +wraddress[7] => wraddress[7].IN1 +wren => wren.IN1 +q[0] <= altsyncram:the_altsyncram.q_b +q[1] <= altsyncram:the_altsyncram.q_b + + +|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_bht_module:system_cpu_bht|altsyncram:the_altsyncram +wren_a => altsyncram_fhg1:auto_generated.wren_a +rden_a => ~NO_FANOUT~ +wren_b => ~NO_FANOUT~ +rden_b => altsyncram_fhg1:auto_generated.rden_b +data_a[0] => altsyncram_fhg1:auto_generated.data_a[0] +data_a[1] => altsyncram_fhg1:auto_generated.data_a[1] +data_b[0] => ~NO_FANOUT~ +data_b[1] => ~NO_FANOUT~ +address_a[0] => altsyncram_fhg1:auto_generated.address_a[0] +address_a[1] => altsyncram_fhg1:auto_generated.address_a[1] +address_a[2] => altsyncram_fhg1:auto_generated.address_a[2] +address_a[3] => altsyncram_fhg1:auto_generated.address_a[3] +address_a[4] => altsyncram_fhg1:auto_generated.address_a[4] +address_a[5] => altsyncram_fhg1:auto_generated.address_a[5] +address_a[6] => altsyncram_fhg1:auto_generated.address_a[6] +address_a[7] => altsyncram_fhg1:auto_generated.address_a[7] +address_b[0] => altsyncram_fhg1:auto_generated.address_b[0] +address_b[1] => altsyncram_fhg1:auto_generated.address_b[1] +address_b[2] => altsyncram_fhg1:auto_generated.address_b[2] +address_b[3] => altsyncram_fhg1:auto_generated.address_b[3] +address_b[4] => altsyncram_fhg1:auto_generated.address_b[4] +address_b[5] => altsyncram_fhg1:auto_generated.address_b[5] +address_b[6] => altsyncram_fhg1:auto_generated.address_b[6] +address_b[7] => altsyncram_fhg1:auto_generated.address_b[7] +addressstall_a => ~NO_FANOUT~ +addressstall_b => ~NO_FANOUT~ +clock0 => altsyncram_fhg1:auto_generated.clock0 +clock1 => ~NO_FANOUT~ +clocken0 => ~NO_FANOUT~ +clocken1 => ~NO_FANOUT~ +clocken2 => ~NO_FANOUT~ +clocken3 => ~NO_FANOUT~ +aclr0 => ~NO_FANOUT~ +aclr1 => ~NO_FANOUT~ +byteena_a[0] => ~NO_FANOUT~ +byteena_b[0] => ~NO_FANOUT~ +q_a[0] <= +q_a[1] <= +q_b[0] <= altsyncram_fhg1:auto_generated.q_b[0] +q_b[1] <= altsyncram_fhg1:auto_generated.q_b[1] +eccstatus[0] <= +eccstatus[1] <= +eccstatus[2] <= + + +|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_bht_module:system_cpu_bht|altsyncram:the_altsyncram|altsyncram_fhg1:auto_generated +address_a[0] => ram_block1a0.PORTAADDR +address_a[0] => ram_block1a1.PORTAADDR +address_a[1] => ram_block1a0.PORTAADDR1 +address_a[1] => ram_block1a1.PORTAADDR1 +address_a[2] => ram_block1a0.PORTAADDR2 +address_a[2] => ram_block1a1.PORTAADDR2 +address_a[3] => ram_block1a0.PORTAADDR3 +address_a[3] => ram_block1a1.PORTAADDR3 +address_a[4] => ram_block1a0.PORTAADDR4 +address_a[4] => ram_block1a1.PORTAADDR4 +address_a[5] => ram_block1a0.PORTAADDR5 +address_a[5] => ram_block1a1.PORTAADDR5 +address_a[6] => ram_block1a0.PORTAADDR6 +address_a[6] => ram_block1a1.PORTAADDR6 +address_a[7] => ram_block1a0.PORTAADDR7 +address_a[7] => ram_block1a1.PORTAADDR7 +address_b[0] => ram_block1a0.PORTBADDR +address_b[0] => ram_block1a1.PORTBADDR +address_b[1] => ram_block1a0.PORTBADDR1 +address_b[1] => ram_block1a1.PORTBADDR1 +address_b[2] => ram_block1a0.PORTBADDR2 +address_b[2] => ram_block1a1.PORTBADDR2 +address_b[3] => ram_block1a0.PORTBADDR3 +address_b[3] => ram_block1a1.PORTBADDR3 +address_b[4] => ram_block1a0.PORTBADDR4 +address_b[4] => ram_block1a1.PORTBADDR4 +address_b[5] => ram_block1a0.PORTBADDR5 +address_b[5] => ram_block1a1.PORTBADDR5 +address_b[6] => ram_block1a0.PORTBADDR6 +address_b[6] => ram_block1a1.PORTBADDR6 +address_b[7] => ram_block1a0.PORTBADDR7 +address_b[7] => ram_block1a1.PORTBADDR7 +clock0 => ram_block1a0.CLK0 +clock0 => ram_block1a1.CLK0 +data_a[0] => ram_block1a0.PORTADATAIN +data_a[1] => ram_block1a1.PORTADATAIN +q_b[0] <= ram_block1a0.PORTBDATAOUT +q_b[1] <= ram_block1a1.PORTBDATAOUT +rden_b => ram_block1a0.PORTBRE +rden_b => ram_block1a1.PORTBRE +wren_a => ram_block1a0.PORTAWE +wren_a => ram_block1a1.PORTAWE + + +|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_register_bank_a_module:system_cpu_register_bank_a +clock => clock.IN1 +data[0] => data[0].IN1 +data[1] => data[1].IN1 +data[2] => data[2].IN1 +data[3] => data[3].IN1 +data[4] => data[4].IN1 +data[5] => data[5].IN1 +data[6] => data[6].IN1 +data[7] => data[7].IN1 +data[8] => data[8].IN1 +data[9] => data[9].IN1 +data[10] => data[10].IN1 +data[11] => data[11].IN1 +data[12] => data[12].IN1 +data[13] => data[13].IN1 +data[14] => data[14].IN1 +data[15] => data[15].IN1 +data[16] => data[16].IN1 +data[17] => data[17].IN1 +data[18] => data[18].IN1 +data[19] => data[19].IN1 +data[20] => data[20].IN1 +data[21] => data[21].IN1 +data[22] => data[22].IN1 +data[23] => data[23].IN1 +data[24] => data[24].IN1 +data[25] => data[25].IN1 +data[26] => data[26].IN1 +data[27] => data[27].IN1 +data[28] => data[28].IN1 +data[29] => data[29].IN1 +data[30] => data[30].IN1 +data[31] => data[31].IN1 +rdaddress[0] => rdaddress[0].IN1 +rdaddress[1] => rdaddress[1].IN1 +rdaddress[2] => rdaddress[2].IN1 +rdaddress[3] => rdaddress[3].IN1 +rdaddress[4] => rdaddress[4].IN1 +wraddress[0] => wraddress[0].IN1 +wraddress[1] => wraddress[1].IN1 +wraddress[2] => wraddress[2].IN1 +wraddress[3] => wraddress[3].IN1 +wraddress[4] => wraddress[4].IN1 +wren => wren.IN1 +q[0] <= altsyncram:the_altsyncram.q_b +q[1] <= altsyncram:the_altsyncram.q_b +q[2] <= altsyncram:the_altsyncram.q_b +q[3] <= altsyncram:the_altsyncram.q_b +q[4] <= altsyncram:the_altsyncram.q_b +q[5] <= altsyncram:the_altsyncram.q_b +q[6] <= altsyncram:the_altsyncram.q_b +q[7] <= altsyncram:the_altsyncram.q_b +q[8] <= altsyncram:the_altsyncram.q_b +q[9] <= altsyncram:the_altsyncram.q_b +q[10] <= altsyncram:the_altsyncram.q_b +q[11] <= altsyncram:the_altsyncram.q_b +q[12] <= altsyncram:the_altsyncram.q_b +q[13] <= altsyncram:the_altsyncram.q_b +q[14] <= altsyncram:the_altsyncram.q_b +q[15] <= altsyncram:the_altsyncram.q_b +q[16] <= altsyncram:the_altsyncram.q_b +q[17] <= altsyncram:the_altsyncram.q_b +q[18] <= altsyncram:the_altsyncram.q_b +q[19] <= altsyncram:the_altsyncram.q_b +q[20] <= altsyncram:the_altsyncram.q_b +q[21] <= altsyncram:the_altsyncram.q_b +q[22] <= altsyncram:the_altsyncram.q_b +q[23] <= altsyncram:the_altsyncram.q_b +q[24] <= altsyncram:the_altsyncram.q_b +q[25] <= altsyncram:the_altsyncram.q_b +q[26] <= altsyncram:the_altsyncram.q_b +q[27] <= altsyncram:the_altsyncram.q_b +q[28] <= altsyncram:the_altsyncram.q_b +q[29] <= altsyncram:the_altsyncram.q_b +q[30] <= altsyncram:the_altsyncram.q_b +q[31] <= altsyncram:the_altsyncram.q_b + + +|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_register_bank_a_module:system_cpu_register_bank_a|altsyncram:the_altsyncram +wren_a => altsyncram_fvf1:auto_generated.wren_a +rden_a => ~NO_FANOUT~ +wren_b => ~NO_FANOUT~ +rden_b => ~NO_FANOUT~ +data_a[0] => altsyncram_fvf1:auto_generated.data_a[0] +data_a[1] => altsyncram_fvf1:auto_generated.data_a[1] +data_a[2] => altsyncram_fvf1:auto_generated.data_a[2] +data_a[3] => altsyncram_fvf1:auto_generated.data_a[3] +data_a[4] => altsyncram_fvf1:auto_generated.data_a[4] +data_a[5] => altsyncram_fvf1:auto_generated.data_a[5] +data_a[6] => altsyncram_fvf1:auto_generated.data_a[6] +data_a[7] => altsyncram_fvf1:auto_generated.data_a[7] +data_a[8] => altsyncram_fvf1:auto_generated.data_a[8] +data_a[9] => altsyncram_fvf1:auto_generated.data_a[9] +data_a[10] => altsyncram_fvf1:auto_generated.data_a[10] +data_a[11] => altsyncram_fvf1:auto_generated.data_a[11] +data_a[12] => altsyncram_fvf1:auto_generated.data_a[12] +data_a[13] => altsyncram_fvf1:auto_generated.data_a[13] +data_a[14] => altsyncram_fvf1:auto_generated.data_a[14] +data_a[15] => altsyncram_fvf1:auto_generated.data_a[15] +data_a[16] => altsyncram_fvf1:auto_generated.data_a[16] +data_a[17] => altsyncram_fvf1:auto_generated.data_a[17] +data_a[18] => altsyncram_fvf1:auto_generated.data_a[18] +data_a[19] => altsyncram_fvf1:auto_generated.data_a[19] +data_a[20] => altsyncram_fvf1:auto_generated.data_a[20] +data_a[21] => altsyncram_fvf1:auto_generated.data_a[21] +data_a[22] => altsyncram_fvf1:auto_generated.data_a[22] +data_a[23] => altsyncram_fvf1:auto_generated.data_a[23] +data_a[24] => altsyncram_fvf1:auto_generated.data_a[24] +data_a[25] => altsyncram_fvf1:auto_generated.data_a[25] +data_a[26] => altsyncram_fvf1:auto_generated.data_a[26] +data_a[27] => altsyncram_fvf1:auto_generated.data_a[27] +data_a[28] => altsyncram_fvf1:auto_generated.data_a[28] +data_a[29] => altsyncram_fvf1:auto_generated.data_a[29] +data_a[30] => altsyncram_fvf1:auto_generated.data_a[30] +data_a[31] => altsyncram_fvf1:auto_generated.data_a[31] +data_b[0] => ~NO_FANOUT~ +data_b[1] => ~NO_FANOUT~ +data_b[2] => ~NO_FANOUT~ +data_b[3] => ~NO_FANOUT~ +data_b[4] => ~NO_FANOUT~ +data_b[5] => ~NO_FANOUT~ +data_b[6] => ~NO_FANOUT~ +data_b[7] => ~NO_FANOUT~ +data_b[8] => ~NO_FANOUT~ +data_b[9] => ~NO_FANOUT~ +data_b[10] => ~NO_FANOUT~ +data_b[11] => ~NO_FANOUT~ +data_b[12] => ~NO_FANOUT~ +data_b[13] => ~NO_FANOUT~ +data_b[14] => ~NO_FANOUT~ +data_b[15] => ~NO_FANOUT~ +data_b[16] => ~NO_FANOUT~ +data_b[17] => ~NO_FANOUT~ +data_b[18] => ~NO_FANOUT~ +data_b[19] => ~NO_FANOUT~ +data_b[20] => ~NO_FANOUT~ +data_b[21] => ~NO_FANOUT~ +data_b[22] => ~NO_FANOUT~ +data_b[23] => ~NO_FANOUT~ +data_b[24] => ~NO_FANOUT~ +data_b[25] => ~NO_FANOUT~ +data_b[26] => ~NO_FANOUT~ +data_b[27] => ~NO_FANOUT~ +data_b[28] => ~NO_FANOUT~ +data_b[29] => ~NO_FANOUT~ +data_b[30] => ~NO_FANOUT~ +data_b[31] => ~NO_FANOUT~ +address_a[0] => altsyncram_fvf1:auto_generated.address_a[0] +address_a[1] => altsyncram_fvf1:auto_generated.address_a[1] +address_a[2] => altsyncram_fvf1:auto_generated.address_a[2] +address_a[3] => altsyncram_fvf1:auto_generated.address_a[3] +address_a[4] => altsyncram_fvf1:auto_generated.address_a[4] +address_b[0] => altsyncram_fvf1:auto_generated.address_b[0] +address_b[1] => altsyncram_fvf1:auto_generated.address_b[1] +address_b[2] => altsyncram_fvf1:auto_generated.address_b[2] +address_b[3] => altsyncram_fvf1:auto_generated.address_b[3] +address_b[4] => altsyncram_fvf1:auto_generated.address_b[4] +addressstall_a => ~NO_FANOUT~ +addressstall_b => ~NO_FANOUT~ +clock0 => altsyncram_fvf1:auto_generated.clock0 +clock1 => ~NO_FANOUT~ +clocken0 => ~NO_FANOUT~ +clocken1 => ~NO_FANOUT~ +clocken2 => ~NO_FANOUT~ +clocken3 => ~NO_FANOUT~ +aclr0 => ~NO_FANOUT~ +aclr1 => ~NO_FANOUT~ +byteena_a[0] => ~NO_FANOUT~ +byteena_b[0] => ~NO_FANOUT~ +q_a[0] <= +q_a[1] <= +q_a[2] <= +q_a[3] <= +q_a[4] <= +q_a[5] <= +q_a[6] <= +q_a[7] <= +q_a[8] <= +q_a[9] <= +q_a[10] <= +q_a[11] <= +q_a[12] <= +q_a[13] <= +q_a[14] <= +q_a[15] <= +q_a[16] <= +q_a[17] <= +q_a[18] <= +q_a[19] <= +q_a[20] <= +q_a[21] <= +q_a[22] <= +q_a[23] <= +q_a[24] <= +q_a[25] <= +q_a[26] <= +q_a[27] <= +q_a[28] <= +q_a[29] <= +q_a[30] <= +q_a[31] <= +q_b[0] <= altsyncram_fvf1:auto_generated.q_b[0] +q_b[1] <= altsyncram_fvf1:auto_generated.q_b[1] +q_b[2] <= altsyncram_fvf1:auto_generated.q_b[2] +q_b[3] <= altsyncram_fvf1:auto_generated.q_b[3] +q_b[4] <= altsyncram_fvf1:auto_generated.q_b[4] +q_b[5] <= altsyncram_fvf1:auto_generated.q_b[5] +q_b[6] <= altsyncram_fvf1:auto_generated.q_b[6] +q_b[7] <= altsyncram_fvf1:auto_generated.q_b[7] +q_b[8] <= altsyncram_fvf1:auto_generated.q_b[8] +q_b[9] <= altsyncram_fvf1:auto_generated.q_b[9] +q_b[10] <= altsyncram_fvf1:auto_generated.q_b[10] +q_b[11] <= altsyncram_fvf1:auto_generated.q_b[11] +q_b[12] <= altsyncram_fvf1:auto_generated.q_b[12] +q_b[13] <= altsyncram_fvf1:auto_generated.q_b[13] +q_b[14] <= altsyncram_fvf1:auto_generated.q_b[14] +q_b[15] <= altsyncram_fvf1:auto_generated.q_b[15] +q_b[16] <= altsyncram_fvf1:auto_generated.q_b[16] +q_b[17] <= altsyncram_fvf1:auto_generated.q_b[17] +q_b[18] <= altsyncram_fvf1:auto_generated.q_b[18] +q_b[19] <= altsyncram_fvf1:auto_generated.q_b[19] +q_b[20] <= altsyncram_fvf1:auto_generated.q_b[20] +q_b[21] <= altsyncram_fvf1:auto_generated.q_b[21] +q_b[22] <= altsyncram_fvf1:auto_generated.q_b[22] +q_b[23] <= altsyncram_fvf1:auto_generated.q_b[23] +q_b[24] <= altsyncram_fvf1:auto_generated.q_b[24] +q_b[25] <= altsyncram_fvf1:auto_generated.q_b[25] +q_b[26] <= altsyncram_fvf1:auto_generated.q_b[26] +q_b[27] <= altsyncram_fvf1:auto_generated.q_b[27] +q_b[28] <= altsyncram_fvf1:auto_generated.q_b[28] +q_b[29] <= altsyncram_fvf1:auto_generated.q_b[29] +q_b[30] <= altsyncram_fvf1:auto_generated.q_b[30] +q_b[31] <= altsyncram_fvf1:auto_generated.q_b[31] +eccstatus[0] <= +eccstatus[1] <= +eccstatus[2] <= + + +|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_register_bank_a_module:system_cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_fvf1:auto_generated +address_a[0] => ram_block1a0.PORTAADDR +address_a[0] => ram_block1a1.PORTAADDR +address_a[0] => ram_block1a2.PORTAADDR +address_a[0] => ram_block1a3.PORTAADDR +address_a[0] => ram_block1a4.PORTAADDR +address_a[0] => ram_block1a5.PORTAADDR +address_a[0] => ram_block1a6.PORTAADDR +address_a[0] => ram_block1a7.PORTAADDR +address_a[0] => ram_block1a8.PORTAADDR +address_a[0] => ram_block1a9.PORTAADDR +address_a[0] => ram_block1a10.PORTAADDR +address_a[0] => ram_block1a11.PORTAADDR +address_a[0] => ram_block1a12.PORTAADDR +address_a[0] => ram_block1a13.PORTAADDR +address_a[0] => ram_block1a14.PORTAADDR +address_a[0] => ram_block1a15.PORTAADDR +address_a[0] => ram_block1a16.PORTAADDR +address_a[0] => ram_block1a17.PORTAADDR +address_a[0] => ram_block1a18.PORTAADDR +address_a[0] => ram_block1a19.PORTAADDR +address_a[0] => ram_block1a20.PORTAADDR +address_a[0] => ram_block1a21.PORTAADDR +address_a[0] => ram_block1a22.PORTAADDR +address_a[0] => ram_block1a23.PORTAADDR +address_a[0] => ram_block1a24.PORTAADDR +address_a[0] => ram_block1a25.PORTAADDR +address_a[0] => ram_block1a26.PORTAADDR +address_a[0] => ram_block1a27.PORTAADDR +address_a[0] => ram_block1a28.PORTAADDR +address_a[0] => ram_block1a29.PORTAADDR +address_a[0] => ram_block1a30.PORTAADDR +address_a[0] => ram_block1a31.PORTAADDR +address_a[1] => ram_block1a0.PORTAADDR1 +address_a[1] => ram_block1a1.PORTAADDR1 +address_a[1] => ram_block1a2.PORTAADDR1 +address_a[1] => ram_block1a3.PORTAADDR1 +address_a[1] => ram_block1a4.PORTAADDR1 +address_a[1] => ram_block1a5.PORTAADDR1 +address_a[1] => ram_block1a6.PORTAADDR1 +address_a[1] => ram_block1a7.PORTAADDR1 +address_a[1] => ram_block1a8.PORTAADDR1 +address_a[1] => ram_block1a9.PORTAADDR1 +address_a[1] => ram_block1a10.PORTAADDR1 +address_a[1] => ram_block1a11.PORTAADDR1 +address_a[1] => ram_block1a12.PORTAADDR1 +address_a[1] => ram_block1a13.PORTAADDR1 +address_a[1] => ram_block1a14.PORTAADDR1 +address_a[1] => ram_block1a15.PORTAADDR1 +address_a[1] => ram_block1a16.PORTAADDR1 +address_a[1] => ram_block1a17.PORTAADDR1 +address_a[1] => ram_block1a18.PORTAADDR1 +address_a[1] => ram_block1a19.PORTAADDR1 +address_a[1] => ram_block1a20.PORTAADDR1 +address_a[1] => ram_block1a21.PORTAADDR1 +address_a[1] => ram_block1a22.PORTAADDR1 +address_a[1] => ram_block1a23.PORTAADDR1 +address_a[1] => ram_block1a24.PORTAADDR1 +address_a[1] => ram_block1a25.PORTAADDR1 +address_a[1] => ram_block1a26.PORTAADDR1 +address_a[1] => ram_block1a27.PORTAADDR1 +address_a[1] => ram_block1a28.PORTAADDR1 +address_a[1] => ram_block1a29.PORTAADDR1 +address_a[1] => ram_block1a30.PORTAADDR1 +address_a[1] => ram_block1a31.PORTAADDR1 +address_a[2] => ram_block1a0.PORTAADDR2 +address_a[2] => ram_block1a1.PORTAADDR2 +address_a[2] => ram_block1a2.PORTAADDR2 +address_a[2] => ram_block1a3.PORTAADDR2 +address_a[2] => ram_block1a4.PORTAADDR2 +address_a[2] => ram_block1a5.PORTAADDR2 +address_a[2] => ram_block1a6.PORTAADDR2 +address_a[2] => ram_block1a7.PORTAADDR2 +address_a[2] => ram_block1a8.PORTAADDR2 +address_a[2] => ram_block1a9.PORTAADDR2 +address_a[2] => ram_block1a10.PORTAADDR2 +address_a[2] => ram_block1a11.PORTAADDR2 +address_a[2] => ram_block1a12.PORTAADDR2 +address_a[2] => ram_block1a13.PORTAADDR2 +address_a[2] => ram_block1a14.PORTAADDR2 +address_a[2] => ram_block1a15.PORTAADDR2 +address_a[2] => ram_block1a16.PORTAADDR2 +address_a[2] => ram_block1a17.PORTAADDR2 +address_a[2] => ram_block1a18.PORTAADDR2 +address_a[2] => ram_block1a19.PORTAADDR2 +address_a[2] => ram_block1a20.PORTAADDR2 +address_a[2] => ram_block1a21.PORTAADDR2 +address_a[2] => ram_block1a22.PORTAADDR2 +address_a[2] => ram_block1a23.PORTAADDR2 +address_a[2] => ram_block1a24.PORTAADDR2 +address_a[2] => ram_block1a25.PORTAADDR2 +address_a[2] => ram_block1a26.PORTAADDR2 +address_a[2] => ram_block1a27.PORTAADDR2 +address_a[2] => ram_block1a28.PORTAADDR2 +address_a[2] => ram_block1a29.PORTAADDR2 +address_a[2] => ram_block1a30.PORTAADDR2 +address_a[2] => ram_block1a31.PORTAADDR2 +address_a[3] => ram_block1a0.PORTAADDR3 +address_a[3] => ram_block1a1.PORTAADDR3 +address_a[3] => ram_block1a2.PORTAADDR3 +address_a[3] => ram_block1a3.PORTAADDR3 +address_a[3] => ram_block1a4.PORTAADDR3 +address_a[3] => ram_block1a5.PORTAADDR3 +address_a[3] => ram_block1a6.PORTAADDR3 +address_a[3] => ram_block1a7.PORTAADDR3 +address_a[3] => ram_block1a8.PORTAADDR3 +address_a[3] => ram_block1a9.PORTAADDR3 +address_a[3] => ram_block1a10.PORTAADDR3 +address_a[3] => ram_block1a11.PORTAADDR3 +address_a[3] => ram_block1a12.PORTAADDR3 +address_a[3] => ram_block1a13.PORTAADDR3 +address_a[3] => ram_block1a14.PORTAADDR3 +address_a[3] => ram_block1a15.PORTAADDR3 +address_a[3] => ram_block1a16.PORTAADDR3 +address_a[3] => ram_block1a17.PORTAADDR3 +address_a[3] => ram_block1a18.PORTAADDR3 +address_a[3] => ram_block1a19.PORTAADDR3 +address_a[3] => ram_block1a20.PORTAADDR3 +address_a[3] => ram_block1a21.PORTAADDR3 +address_a[3] => ram_block1a22.PORTAADDR3 +address_a[3] => ram_block1a23.PORTAADDR3 +address_a[3] => ram_block1a24.PORTAADDR3 +address_a[3] => ram_block1a25.PORTAADDR3 +address_a[3] => ram_block1a26.PORTAADDR3 +address_a[3] => ram_block1a27.PORTAADDR3 +address_a[3] => ram_block1a28.PORTAADDR3 +address_a[3] => ram_block1a29.PORTAADDR3 +address_a[3] => ram_block1a30.PORTAADDR3 +address_a[3] => ram_block1a31.PORTAADDR3 +address_a[4] => ram_block1a0.PORTAADDR4 +address_a[4] => ram_block1a1.PORTAADDR4 +address_a[4] => ram_block1a2.PORTAADDR4 +address_a[4] => ram_block1a3.PORTAADDR4 +address_a[4] => ram_block1a4.PORTAADDR4 +address_a[4] => ram_block1a5.PORTAADDR4 +address_a[4] => ram_block1a6.PORTAADDR4 +address_a[4] => ram_block1a7.PORTAADDR4 +address_a[4] => ram_block1a8.PORTAADDR4 +address_a[4] => ram_block1a9.PORTAADDR4 +address_a[4] => ram_block1a10.PORTAADDR4 +address_a[4] => ram_block1a11.PORTAADDR4 +address_a[4] => ram_block1a12.PORTAADDR4 +address_a[4] => ram_block1a13.PORTAADDR4 +address_a[4] => ram_block1a14.PORTAADDR4 +address_a[4] => ram_block1a15.PORTAADDR4 +address_a[4] => ram_block1a16.PORTAADDR4 +address_a[4] => ram_block1a17.PORTAADDR4 +address_a[4] => ram_block1a18.PORTAADDR4 +address_a[4] => ram_block1a19.PORTAADDR4 +address_a[4] => ram_block1a20.PORTAADDR4 +address_a[4] => ram_block1a21.PORTAADDR4 +address_a[4] => ram_block1a22.PORTAADDR4 +address_a[4] => ram_block1a23.PORTAADDR4 +address_a[4] => ram_block1a24.PORTAADDR4 +address_a[4] => ram_block1a25.PORTAADDR4 +address_a[4] => ram_block1a26.PORTAADDR4 +address_a[4] => ram_block1a27.PORTAADDR4 +address_a[4] => ram_block1a28.PORTAADDR4 +address_a[4] => ram_block1a29.PORTAADDR4 +address_a[4] => ram_block1a30.PORTAADDR4 +address_a[4] => ram_block1a31.PORTAADDR4 +address_b[0] => ram_block1a0.PORTBADDR +address_b[0] => ram_block1a1.PORTBADDR +address_b[0] => ram_block1a2.PORTBADDR +address_b[0] => ram_block1a3.PORTBADDR +address_b[0] => ram_block1a4.PORTBADDR +address_b[0] => ram_block1a5.PORTBADDR +address_b[0] => ram_block1a6.PORTBADDR +address_b[0] => ram_block1a7.PORTBADDR +address_b[0] => ram_block1a8.PORTBADDR +address_b[0] => ram_block1a9.PORTBADDR +address_b[0] => ram_block1a10.PORTBADDR +address_b[0] => ram_block1a11.PORTBADDR +address_b[0] => ram_block1a12.PORTBADDR +address_b[0] => ram_block1a13.PORTBADDR +address_b[0] => ram_block1a14.PORTBADDR +address_b[0] => ram_block1a15.PORTBADDR +address_b[0] => ram_block1a16.PORTBADDR +address_b[0] => ram_block1a17.PORTBADDR +address_b[0] => ram_block1a18.PORTBADDR +address_b[0] => ram_block1a19.PORTBADDR +address_b[0] => ram_block1a20.PORTBADDR +address_b[0] => ram_block1a21.PORTBADDR +address_b[0] => ram_block1a22.PORTBADDR +address_b[0] => ram_block1a23.PORTBADDR +address_b[0] => ram_block1a24.PORTBADDR +address_b[0] => ram_block1a25.PORTBADDR +address_b[0] => ram_block1a26.PORTBADDR +address_b[0] => ram_block1a27.PORTBADDR +address_b[0] => ram_block1a28.PORTBADDR +address_b[0] => ram_block1a29.PORTBADDR +address_b[0] => ram_block1a30.PORTBADDR +address_b[0] => ram_block1a31.PORTBADDR +address_b[1] => ram_block1a0.PORTBADDR1 +address_b[1] => ram_block1a1.PORTBADDR1 +address_b[1] => ram_block1a2.PORTBADDR1 +address_b[1] => ram_block1a3.PORTBADDR1 +address_b[1] => ram_block1a4.PORTBADDR1 +address_b[1] => ram_block1a5.PORTBADDR1 +address_b[1] => ram_block1a6.PORTBADDR1 +address_b[1] => ram_block1a7.PORTBADDR1 +address_b[1] => ram_block1a8.PORTBADDR1 +address_b[1] => ram_block1a9.PORTBADDR1 +address_b[1] => ram_block1a10.PORTBADDR1 +address_b[1] => ram_block1a11.PORTBADDR1 +address_b[1] => ram_block1a12.PORTBADDR1 +address_b[1] => ram_block1a13.PORTBADDR1 +address_b[1] => ram_block1a14.PORTBADDR1 +address_b[1] => ram_block1a15.PORTBADDR1 +address_b[1] => ram_block1a16.PORTBADDR1 +address_b[1] => ram_block1a17.PORTBADDR1 +address_b[1] => ram_block1a18.PORTBADDR1 +address_b[1] => ram_block1a19.PORTBADDR1 +address_b[1] => ram_block1a20.PORTBADDR1 +address_b[1] => ram_block1a21.PORTBADDR1 +address_b[1] => ram_block1a22.PORTBADDR1 +address_b[1] => ram_block1a23.PORTBADDR1 +address_b[1] => ram_block1a24.PORTBADDR1 +address_b[1] => ram_block1a25.PORTBADDR1 +address_b[1] => ram_block1a26.PORTBADDR1 +address_b[1] => ram_block1a27.PORTBADDR1 +address_b[1] => ram_block1a28.PORTBADDR1 +address_b[1] => ram_block1a29.PORTBADDR1 +address_b[1] => ram_block1a30.PORTBADDR1 +address_b[1] => ram_block1a31.PORTBADDR1 +address_b[2] => ram_block1a0.PORTBADDR2 +address_b[2] => ram_block1a1.PORTBADDR2 +address_b[2] => ram_block1a2.PORTBADDR2 +address_b[2] => ram_block1a3.PORTBADDR2 +address_b[2] => ram_block1a4.PORTBADDR2 +address_b[2] => ram_block1a5.PORTBADDR2 +address_b[2] => ram_block1a6.PORTBADDR2 +address_b[2] => ram_block1a7.PORTBADDR2 +address_b[2] => ram_block1a8.PORTBADDR2 +address_b[2] => ram_block1a9.PORTBADDR2 +address_b[2] => ram_block1a10.PORTBADDR2 +address_b[2] => ram_block1a11.PORTBADDR2 +address_b[2] => ram_block1a12.PORTBADDR2 +address_b[2] => ram_block1a13.PORTBADDR2 +address_b[2] => ram_block1a14.PORTBADDR2 +address_b[2] => ram_block1a15.PORTBADDR2 +address_b[2] => ram_block1a16.PORTBADDR2 +address_b[2] => ram_block1a17.PORTBADDR2 +address_b[2] => ram_block1a18.PORTBADDR2 +address_b[2] => ram_block1a19.PORTBADDR2 +address_b[2] => ram_block1a20.PORTBADDR2 +address_b[2] => ram_block1a21.PORTBADDR2 +address_b[2] => ram_block1a22.PORTBADDR2 +address_b[2] => ram_block1a23.PORTBADDR2 +address_b[2] => ram_block1a24.PORTBADDR2 +address_b[2] => ram_block1a25.PORTBADDR2 +address_b[2] => ram_block1a26.PORTBADDR2 +address_b[2] => ram_block1a27.PORTBADDR2 +address_b[2] => ram_block1a28.PORTBADDR2 +address_b[2] => ram_block1a29.PORTBADDR2 +address_b[2] => ram_block1a30.PORTBADDR2 +address_b[2] => ram_block1a31.PORTBADDR2 +address_b[3] => ram_block1a0.PORTBADDR3 +address_b[3] => ram_block1a1.PORTBADDR3 +address_b[3] => ram_block1a2.PORTBADDR3 +address_b[3] => ram_block1a3.PORTBADDR3 +address_b[3] => ram_block1a4.PORTBADDR3 +address_b[3] => ram_block1a5.PORTBADDR3 +address_b[3] => ram_block1a6.PORTBADDR3 +address_b[3] => ram_block1a7.PORTBADDR3 +address_b[3] => ram_block1a8.PORTBADDR3 +address_b[3] => ram_block1a9.PORTBADDR3 +address_b[3] => ram_block1a10.PORTBADDR3 +address_b[3] => ram_block1a11.PORTBADDR3 +address_b[3] => ram_block1a12.PORTBADDR3 +address_b[3] => ram_block1a13.PORTBADDR3 +address_b[3] => ram_block1a14.PORTBADDR3 +address_b[3] => ram_block1a15.PORTBADDR3 +address_b[3] => ram_block1a16.PORTBADDR3 +address_b[3] => ram_block1a17.PORTBADDR3 +address_b[3] => ram_block1a18.PORTBADDR3 +address_b[3] => ram_block1a19.PORTBADDR3 +address_b[3] => ram_block1a20.PORTBADDR3 +address_b[3] => ram_block1a21.PORTBADDR3 +address_b[3] => ram_block1a22.PORTBADDR3 +address_b[3] => ram_block1a23.PORTBADDR3 +address_b[3] => ram_block1a24.PORTBADDR3 +address_b[3] => ram_block1a25.PORTBADDR3 +address_b[3] => ram_block1a26.PORTBADDR3 +address_b[3] => ram_block1a27.PORTBADDR3 +address_b[3] => ram_block1a28.PORTBADDR3 +address_b[3] => ram_block1a29.PORTBADDR3 +address_b[3] => ram_block1a30.PORTBADDR3 +address_b[3] => ram_block1a31.PORTBADDR3 +address_b[4] => ram_block1a0.PORTBADDR4 +address_b[4] => ram_block1a1.PORTBADDR4 +address_b[4] => ram_block1a2.PORTBADDR4 +address_b[4] => ram_block1a3.PORTBADDR4 +address_b[4] => ram_block1a4.PORTBADDR4 +address_b[4] => ram_block1a5.PORTBADDR4 +address_b[4] => ram_block1a6.PORTBADDR4 +address_b[4] => ram_block1a7.PORTBADDR4 +address_b[4] => ram_block1a8.PORTBADDR4 +address_b[4] => ram_block1a9.PORTBADDR4 +address_b[4] => ram_block1a10.PORTBADDR4 +address_b[4] => ram_block1a11.PORTBADDR4 +address_b[4] => ram_block1a12.PORTBADDR4 +address_b[4] => ram_block1a13.PORTBADDR4 +address_b[4] => ram_block1a14.PORTBADDR4 +address_b[4] => ram_block1a15.PORTBADDR4 +address_b[4] => ram_block1a16.PORTBADDR4 +address_b[4] => ram_block1a17.PORTBADDR4 +address_b[4] => ram_block1a18.PORTBADDR4 +address_b[4] => ram_block1a19.PORTBADDR4 +address_b[4] => ram_block1a20.PORTBADDR4 +address_b[4] => ram_block1a21.PORTBADDR4 +address_b[4] => ram_block1a22.PORTBADDR4 +address_b[4] => ram_block1a23.PORTBADDR4 +address_b[4] => ram_block1a24.PORTBADDR4 +address_b[4] => ram_block1a25.PORTBADDR4 +address_b[4] => ram_block1a26.PORTBADDR4 +address_b[4] => ram_block1a27.PORTBADDR4 +address_b[4] => ram_block1a28.PORTBADDR4 +address_b[4] => ram_block1a29.PORTBADDR4 +address_b[4] => ram_block1a30.PORTBADDR4 +address_b[4] => ram_block1a31.PORTBADDR4 +clock0 => ram_block1a0.CLK0 +clock0 => ram_block1a1.CLK0 +clock0 => ram_block1a2.CLK0 +clock0 => ram_block1a3.CLK0 +clock0 => ram_block1a4.CLK0 +clock0 => ram_block1a5.CLK0 +clock0 => ram_block1a6.CLK0 +clock0 => ram_block1a7.CLK0 +clock0 => ram_block1a8.CLK0 +clock0 => ram_block1a9.CLK0 +clock0 => ram_block1a10.CLK0 +clock0 => ram_block1a11.CLK0 +clock0 => ram_block1a12.CLK0 +clock0 => ram_block1a13.CLK0 +clock0 => ram_block1a14.CLK0 +clock0 => ram_block1a15.CLK0 +clock0 => ram_block1a16.CLK0 +clock0 => ram_block1a17.CLK0 +clock0 => ram_block1a18.CLK0 +clock0 => ram_block1a19.CLK0 +clock0 => ram_block1a20.CLK0 +clock0 => ram_block1a21.CLK0 +clock0 => ram_block1a22.CLK0 +clock0 => ram_block1a23.CLK0 +clock0 => ram_block1a24.CLK0 +clock0 => ram_block1a25.CLK0 +clock0 => ram_block1a26.CLK0 +clock0 => ram_block1a27.CLK0 +clock0 => ram_block1a28.CLK0 +clock0 => ram_block1a29.CLK0 +clock0 => ram_block1a30.CLK0 +clock0 => ram_block1a31.CLK0 +data_a[0] => ram_block1a0.PORTADATAIN +data_a[1] => ram_block1a1.PORTADATAIN +data_a[2] => ram_block1a2.PORTADATAIN +data_a[3] => ram_block1a3.PORTADATAIN +data_a[4] => ram_block1a4.PORTADATAIN +data_a[5] => ram_block1a5.PORTADATAIN +data_a[6] => ram_block1a6.PORTADATAIN +data_a[7] => ram_block1a7.PORTADATAIN +data_a[8] => ram_block1a8.PORTADATAIN +data_a[9] => ram_block1a9.PORTADATAIN +data_a[10] => ram_block1a10.PORTADATAIN +data_a[11] => ram_block1a11.PORTADATAIN +data_a[12] => ram_block1a12.PORTADATAIN +data_a[13] => ram_block1a13.PORTADATAIN +data_a[14] => ram_block1a14.PORTADATAIN +data_a[15] => ram_block1a15.PORTADATAIN +data_a[16] => ram_block1a16.PORTADATAIN +data_a[17] => ram_block1a17.PORTADATAIN +data_a[18] => ram_block1a18.PORTADATAIN +data_a[19] => ram_block1a19.PORTADATAIN +data_a[20] => ram_block1a20.PORTADATAIN +data_a[21] => ram_block1a21.PORTADATAIN +data_a[22] => ram_block1a22.PORTADATAIN +data_a[23] => ram_block1a23.PORTADATAIN +data_a[24] => ram_block1a24.PORTADATAIN +data_a[25] => ram_block1a25.PORTADATAIN +data_a[26] => ram_block1a26.PORTADATAIN +data_a[27] => ram_block1a27.PORTADATAIN +data_a[28] => ram_block1a28.PORTADATAIN +data_a[29] => ram_block1a29.PORTADATAIN +data_a[30] => ram_block1a30.PORTADATAIN +data_a[31] => ram_block1a31.PORTADATAIN +q_b[0] <= ram_block1a0.PORTBDATAOUT +q_b[1] <= ram_block1a1.PORTBDATAOUT +q_b[2] <= ram_block1a2.PORTBDATAOUT +q_b[3] <= ram_block1a3.PORTBDATAOUT +q_b[4] <= ram_block1a4.PORTBDATAOUT +q_b[5] <= ram_block1a5.PORTBDATAOUT +q_b[6] <= ram_block1a6.PORTBDATAOUT +q_b[7] <= ram_block1a7.PORTBDATAOUT +q_b[8] <= ram_block1a8.PORTBDATAOUT +q_b[9] <= ram_block1a9.PORTBDATAOUT +q_b[10] <= ram_block1a10.PORTBDATAOUT +q_b[11] <= ram_block1a11.PORTBDATAOUT +q_b[12] <= ram_block1a12.PORTBDATAOUT +q_b[13] <= ram_block1a13.PORTBDATAOUT +q_b[14] <= ram_block1a14.PORTBDATAOUT +q_b[15] <= ram_block1a15.PORTBDATAOUT +q_b[16] <= ram_block1a16.PORTBDATAOUT +q_b[17] <= ram_block1a17.PORTBDATAOUT +q_b[18] <= ram_block1a18.PORTBDATAOUT +q_b[19] <= ram_block1a19.PORTBDATAOUT +q_b[20] <= ram_block1a20.PORTBDATAOUT +q_b[21] <= ram_block1a21.PORTBDATAOUT +q_b[22] <= ram_block1a22.PORTBDATAOUT +q_b[23] <= ram_block1a23.PORTBDATAOUT +q_b[24] <= ram_block1a24.PORTBDATAOUT +q_b[25] <= ram_block1a25.PORTBDATAOUT +q_b[26] <= ram_block1a26.PORTBDATAOUT +q_b[27] <= ram_block1a27.PORTBDATAOUT +q_b[28] <= ram_block1a28.PORTBDATAOUT +q_b[29] <= ram_block1a29.PORTBDATAOUT +q_b[30] <= ram_block1a30.PORTBDATAOUT +q_b[31] <= ram_block1a31.PORTBDATAOUT +wren_a => ram_block1a0.PORTAWE +wren_a => ram_block1a1.PORTAWE +wren_a => ram_block1a2.PORTAWE +wren_a => ram_block1a3.PORTAWE +wren_a => ram_block1a4.PORTAWE +wren_a => ram_block1a5.PORTAWE +wren_a => ram_block1a6.PORTAWE +wren_a => ram_block1a7.PORTAWE +wren_a => ram_block1a8.PORTAWE +wren_a => ram_block1a9.PORTAWE +wren_a => ram_block1a10.PORTAWE +wren_a => ram_block1a11.PORTAWE +wren_a => ram_block1a12.PORTAWE +wren_a => ram_block1a13.PORTAWE +wren_a => ram_block1a14.PORTAWE +wren_a => ram_block1a15.PORTAWE +wren_a => ram_block1a16.PORTAWE +wren_a => ram_block1a17.PORTAWE +wren_a => ram_block1a18.PORTAWE +wren_a => ram_block1a19.PORTAWE +wren_a => ram_block1a20.PORTAWE +wren_a => ram_block1a21.PORTAWE +wren_a => ram_block1a22.PORTAWE +wren_a => ram_block1a23.PORTAWE +wren_a => ram_block1a24.PORTAWE +wren_a => ram_block1a25.PORTAWE +wren_a => ram_block1a26.PORTAWE +wren_a => ram_block1a27.PORTAWE +wren_a => ram_block1a28.PORTAWE +wren_a => ram_block1a29.PORTAWE +wren_a => ram_block1a30.PORTAWE +wren_a => ram_block1a31.PORTAWE + + +|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_register_bank_b_module:system_cpu_register_bank_b +clock => clock.IN1 +data[0] => data[0].IN1 +data[1] => data[1].IN1 +data[2] => data[2].IN1 +data[3] => data[3].IN1 +data[4] => data[4].IN1 +data[5] => data[5].IN1 +data[6] => data[6].IN1 +data[7] => data[7].IN1 +data[8] => data[8].IN1 +data[9] => data[9].IN1 +data[10] => data[10].IN1 +data[11] => data[11].IN1 +data[12] => data[12].IN1 +data[13] => data[13].IN1 +data[14] => data[14].IN1 +data[15] => data[15].IN1 +data[16] => data[16].IN1 +data[17] => data[17].IN1 +data[18] => data[18].IN1 +data[19] => data[19].IN1 +data[20] => data[20].IN1 +data[21] => data[21].IN1 +data[22] => data[22].IN1 +data[23] => data[23].IN1 +data[24] => data[24].IN1 +data[25] => data[25].IN1 +data[26] => data[26].IN1 +data[27] => data[27].IN1 +data[28] => data[28].IN1 +data[29] => data[29].IN1 +data[30] => data[30].IN1 +data[31] => data[31].IN1 +rdaddress[0] => rdaddress[0].IN1 +rdaddress[1] => rdaddress[1].IN1 +rdaddress[2] => rdaddress[2].IN1 +rdaddress[3] => rdaddress[3].IN1 +rdaddress[4] => rdaddress[4].IN1 +wraddress[0] => wraddress[0].IN1 +wraddress[1] => wraddress[1].IN1 +wraddress[2] => wraddress[2].IN1 +wraddress[3] => wraddress[3].IN1 +wraddress[4] => wraddress[4].IN1 +wren => wren.IN1 +q[0] <= altsyncram:the_altsyncram.q_b +q[1] <= altsyncram:the_altsyncram.q_b +q[2] <= altsyncram:the_altsyncram.q_b +q[3] <= altsyncram:the_altsyncram.q_b +q[4] <= altsyncram:the_altsyncram.q_b +q[5] <= altsyncram:the_altsyncram.q_b +q[6] <= altsyncram:the_altsyncram.q_b +q[7] <= altsyncram:the_altsyncram.q_b +q[8] <= altsyncram:the_altsyncram.q_b +q[9] <= altsyncram:the_altsyncram.q_b +q[10] <= altsyncram:the_altsyncram.q_b +q[11] <= altsyncram:the_altsyncram.q_b +q[12] <= altsyncram:the_altsyncram.q_b +q[13] <= altsyncram:the_altsyncram.q_b +q[14] <= altsyncram:the_altsyncram.q_b +q[15] <= altsyncram:the_altsyncram.q_b +q[16] <= altsyncram:the_altsyncram.q_b +q[17] <= altsyncram:the_altsyncram.q_b +q[18] <= altsyncram:the_altsyncram.q_b +q[19] <= altsyncram:the_altsyncram.q_b +q[20] <= altsyncram:the_altsyncram.q_b +q[21] <= altsyncram:the_altsyncram.q_b +q[22] <= altsyncram:the_altsyncram.q_b +q[23] <= altsyncram:the_altsyncram.q_b +q[24] <= altsyncram:the_altsyncram.q_b +q[25] <= altsyncram:the_altsyncram.q_b +q[26] <= altsyncram:the_altsyncram.q_b +q[27] <= altsyncram:the_altsyncram.q_b +q[28] <= altsyncram:the_altsyncram.q_b +q[29] <= altsyncram:the_altsyncram.q_b +q[30] <= altsyncram:the_altsyncram.q_b +q[31] <= altsyncram:the_altsyncram.q_b + + +|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_register_bank_b_module:system_cpu_register_bank_b|altsyncram:the_altsyncram +wren_a => altsyncram_gvf1:auto_generated.wren_a +rden_a => ~NO_FANOUT~ +wren_b => ~NO_FANOUT~ +rden_b => ~NO_FANOUT~ +data_a[0] => altsyncram_gvf1:auto_generated.data_a[0] +data_a[1] => altsyncram_gvf1:auto_generated.data_a[1] +data_a[2] => altsyncram_gvf1:auto_generated.data_a[2] +data_a[3] => altsyncram_gvf1:auto_generated.data_a[3] +data_a[4] => altsyncram_gvf1:auto_generated.data_a[4] +data_a[5] => altsyncram_gvf1:auto_generated.data_a[5] +data_a[6] => altsyncram_gvf1:auto_generated.data_a[6] +data_a[7] => altsyncram_gvf1:auto_generated.data_a[7] +data_a[8] => altsyncram_gvf1:auto_generated.data_a[8] +data_a[9] => altsyncram_gvf1:auto_generated.data_a[9] +data_a[10] => altsyncram_gvf1:auto_generated.data_a[10] +data_a[11] => altsyncram_gvf1:auto_generated.data_a[11] +data_a[12] => altsyncram_gvf1:auto_generated.data_a[12] +data_a[13] => altsyncram_gvf1:auto_generated.data_a[13] +data_a[14] => altsyncram_gvf1:auto_generated.data_a[14] +data_a[15] => altsyncram_gvf1:auto_generated.data_a[15] +data_a[16] => altsyncram_gvf1:auto_generated.data_a[16] +data_a[17] => altsyncram_gvf1:auto_generated.data_a[17] +data_a[18] => altsyncram_gvf1:auto_generated.data_a[18] +data_a[19] => altsyncram_gvf1:auto_generated.data_a[19] +data_a[20] => altsyncram_gvf1:auto_generated.data_a[20] +data_a[21] => altsyncram_gvf1:auto_generated.data_a[21] +data_a[22] => altsyncram_gvf1:auto_generated.data_a[22] +data_a[23] => altsyncram_gvf1:auto_generated.data_a[23] +data_a[24] => altsyncram_gvf1:auto_generated.data_a[24] +data_a[25] => altsyncram_gvf1:auto_generated.data_a[25] +data_a[26] => altsyncram_gvf1:auto_generated.data_a[26] +data_a[27] => altsyncram_gvf1:auto_generated.data_a[27] +data_a[28] => altsyncram_gvf1:auto_generated.data_a[28] +data_a[29] => altsyncram_gvf1:auto_generated.data_a[29] +data_a[30] => altsyncram_gvf1:auto_generated.data_a[30] +data_a[31] => altsyncram_gvf1:auto_generated.data_a[31] +data_b[0] => ~NO_FANOUT~ +data_b[1] => ~NO_FANOUT~ +data_b[2] => ~NO_FANOUT~ +data_b[3] => ~NO_FANOUT~ +data_b[4] => ~NO_FANOUT~ +data_b[5] => ~NO_FANOUT~ +data_b[6] => ~NO_FANOUT~ +data_b[7] => ~NO_FANOUT~ +data_b[8] => ~NO_FANOUT~ +data_b[9] => ~NO_FANOUT~ +data_b[10] => ~NO_FANOUT~ +data_b[11] => ~NO_FANOUT~ +data_b[12] => ~NO_FANOUT~ +data_b[13] => ~NO_FANOUT~ +data_b[14] => ~NO_FANOUT~ +data_b[15] => ~NO_FANOUT~ +data_b[16] => ~NO_FANOUT~ +data_b[17] => ~NO_FANOUT~ +data_b[18] => ~NO_FANOUT~ +data_b[19] => ~NO_FANOUT~ +data_b[20] => ~NO_FANOUT~ +data_b[21] => ~NO_FANOUT~ +data_b[22] => ~NO_FANOUT~ +data_b[23] => ~NO_FANOUT~ +data_b[24] => ~NO_FANOUT~ +data_b[25] => ~NO_FANOUT~ +data_b[26] => ~NO_FANOUT~ +data_b[27] => ~NO_FANOUT~ +data_b[28] => ~NO_FANOUT~ +data_b[29] => ~NO_FANOUT~ +data_b[30] => ~NO_FANOUT~ +data_b[31] => ~NO_FANOUT~ +address_a[0] => altsyncram_gvf1:auto_generated.address_a[0] +address_a[1] => altsyncram_gvf1:auto_generated.address_a[1] +address_a[2] => altsyncram_gvf1:auto_generated.address_a[2] +address_a[3] => altsyncram_gvf1:auto_generated.address_a[3] +address_a[4] => altsyncram_gvf1:auto_generated.address_a[4] +address_b[0] => altsyncram_gvf1:auto_generated.address_b[0] +address_b[1] => altsyncram_gvf1:auto_generated.address_b[1] +address_b[2] => altsyncram_gvf1:auto_generated.address_b[2] +address_b[3] => altsyncram_gvf1:auto_generated.address_b[3] +address_b[4] => altsyncram_gvf1:auto_generated.address_b[4] +addressstall_a => ~NO_FANOUT~ +addressstall_b => ~NO_FANOUT~ +clock0 => altsyncram_gvf1:auto_generated.clock0 +clock1 => ~NO_FANOUT~ +clocken0 => ~NO_FANOUT~ +clocken1 => ~NO_FANOUT~ +clocken2 => ~NO_FANOUT~ +clocken3 => ~NO_FANOUT~ +aclr0 => ~NO_FANOUT~ +aclr1 => ~NO_FANOUT~ +byteena_a[0] => ~NO_FANOUT~ +byteena_b[0] => ~NO_FANOUT~ +q_a[0] <= +q_a[1] <= +q_a[2] <= +q_a[3] <= +q_a[4] <= +q_a[5] <= +q_a[6] <= +q_a[7] <= +q_a[8] <= +q_a[9] <= +q_a[10] <= +q_a[11] <= +q_a[12] <= +q_a[13] <= +q_a[14] <= +q_a[15] <= +q_a[16] <= +q_a[17] <= +q_a[18] <= +q_a[19] <= +q_a[20] <= +q_a[21] <= +q_a[22] <= +q_a[23] <= +q_a[24] <= +q_a[25] <= +q_a[26] <= +q_a[27] <= +q_a[28] <= +q_a[29] <= +q_a[30] <= +q_a[31] <= +q_b[0] <= altsyncram_gvf1:auto_generated.q_b[0] +q_b[1] <= altsyncram_gvf1:auto_generated.q_b[1] +q_b[2] <= altsyncram_gvf1:auto_generated.q_b[2] +q_b[3] <= altsyncram_gvf1:auto_generated.q_b[3] +q_b[4] <= altsyncram_gvf1:auto_generated.q_b[4] +q_b[5] <= altsyncram_gvf1:auto_generated.q_b[5] +q_b[6] <= altsyncram_gvf1:auto_generated.q_b[6] +q_b[7] <= altsyncram_gvf1:auto_generated.q_b[7] +q_b[8] <= altsyncram_gvf1:auto_generated.q_b[8] +q_b[9] <= altsyncram_gvf1:auto_generated.q_b[9] +q_b[10] <= altsyncram_gvf1:auto_generated.q_b[10] +q_b[11] <= altsyncram_gvf1:auto_generated.q_b[11] +q_b[12] <= altsyncram_gvf1:auto_generated.q_b[12] +q_b[13] <= altsyncram_gvf1:auto_generated.q_b[13] +q_b[14] <= altsyncram_gvf1:auto_generated.q_b[14] +q_b[15] <= altsyncram_gvf1:auto_generated.q_b[15] +q_b[16] <= altsyncram_gvf1:auto_generated.q_b[16] +q_b[17] <= altsyncram_gvf1:auto_generated.q_b[17] +q_b[18] <= altsyncram_gvf1:auto_generated.q_b[18] +q_b[19] <= altsyncram_gvf1:auto_generated.q_b[19] +q_b[20] <= altsyncram_gvf1:auto_generated.q_b[20] +q_b[21] <= altsyncram_gvf1:auto_generated.q_b[21] +q_b[22] <= altsyncram_gvf1:auto_generated.q_b[22] +q_b[23] <= altsyncram_gvf1:auto_generated.q_b[23] +q_b[24] <= altsyncram_gvf1:auto_generated.q_b[24] +q_b[25] <= altsyncram_gvf1:auto_generated.q_b[25] +q_b[26] <= altsyncram_gvf1:auto_generated.q_b[26] +q_b[27] <= altsyncram_gvf1:auto_generated.q_b[27] +q_b[28] <= altsyncram_gvf1:auto_generated.q_b[28] +q_b[29] <= altsyncram_gvf1:auto_generated.q_b[29] +q_b[30] <= altsyncram_gvf1:auto_generated.q_b[30] +q_b[31] <= altsyncram_gvf1:auto_generated.q_b[31] +eccstatus[0] <= +eccstatus[1] <= +eccstatus[2] <= + + +|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_register_bank_b_module:system_cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_gvf1:auto_generated +address_a[0] => ram_block1a0.PORTAADDR +address_a[0] => ram_block1a1.PORTAADDR +address_a[0] => ram_block1a2.PORTAADDR +address_a[0] => ram_block1a3.PORTAADDR +address_a[0] => ram_block1a4.PORTAADDR +address_a[0] => ram_block1a5.PORTAADDR +address_a[0] => ram_block1a6.PORTAADDR +address_a[0] => ram_block1a7.PORTAADDR +address_a[0] => ram_block1a8.PORTAADDR +address_a[0] => ram_block1a9.PORTAADDR +address_a[0] => ram_block1a10.PORTAADDR +address_a[0] => ram_block1a11.PORTAADDR +address_a[0] => ram_block1a12.PORTAADDR +address_a[0] => ram_block1a13.PORTAADDR +address_a[0] => ram_block1a14.PORTAADDR +address_a[0] => ram_block1a15.PORTAADDR +address_a[0] => ram_block1a16.PORTAADDR +address_a[0] => ram_block1a17.PORTAADDR +address_a[0] => ram_block1a18.PORTAADDR +address_a[0] => ram_block1a19.PORTAADDR +address_a[0] => ram_block1a20.PORTAADDR +address_a[0] => ram_block1a21.PORTAADDR +address_a[0] => ram_block1a22.PORTAADDR +address_a[0] => ram_block1a23.PORTAADDR +address_a[0] => ram_block1a24.PORTAADDR +address_a[0] => ram_block1a25.PORTAADDR +address_a[0] => ram_block1a26.PORTAADDR +address_a[0] => ram_block1a27.PORTAADDR +address_a[0] => ram_block1a28.PORTAADDR +address_a[0] => ram_block1a29.PORTAADDR +address_a[0] => ram_block1a30.PORTAADDR +address_a[0] => ram_block1a31.PORTAADDR +address_a[1] => ram_block1a0.PORTAADDR1 +address_a[1] => ram_block1a1.PORTAADDR1 +address_a[1] => ram_block1a2.PORTAADDR1 +address_a[1] => ram_block1a3.PORTAADDR1 +address_a[1] => ram_block1a4.PORTAADDR1 +address_a[1] => ram_block1a5.PORTAADDR1 +address_a[1] => ram_block1a6.PORTAADDR1 +address_a[1] => ram_block1a7.PORTAADDR1 +address_a[1] => ram_block1a8.PORTAADDR1 +address_a[1] => ram_block1a9.PORTAADDR1 +address_a[1] => ram_block1a10.PORTAADDR1 +address_a[1] => ram_block1a11.PORTAADDR1 +address_a[1] => ram_block1a12.PORTAADDR1 +address_a[1] => ram_block1a13.PORTAADDR1 +address_a[1] => ram_block1a14.PORTAADDR1 +address_a[1] => ram_block1a15.PORTAADDR1 +address_a[1] => ram_block1a16.PORTAADDR1 +address_a[1] => ram_block1a17.PORTAADDR1 +address_a[1] => ram_block1a18.PORTAADDR1 +address_a[1] => ram_block1a19.PORTAADDR1 +address_a[1] => ram_block1a20.PORTAADDR1 +address_a[1] => ram_block1a21.PORTAADDR1 +address_a[1] => ram_block1a22.PORTAADDR1 +address_a[1] => ram_block1a23.PORTAADDR1 +address_a[1] => ram_block1a24.PORTAADDR1 +address_a[1] => ram_block1a25.PORTAADDR1 +address_a[1] => ram_block1a26.PORTAADDR1 +address_a[1] => ram_block1a27.PORTAADDR1 +address_a[1] => ram_block1a28.PORTAADDR1 +address_a[1] => ram_block1a29.PORTAADDR1 +address_a[1] => ram_block1a30.PORTAADDR1 +address_a[1] => ram_block1a31.PORTAADDR1 +address_a[2] => ram_block1a0.PORTAADDR2 +address_a[2] => ram_block1a1.PORTAADDR2 +address_a[2] => ram_block1a2.PORTAADDR2 +address_a[2] => ram_block1a3.PORTAADDR2 +address_a[2] => ram_block1a4.PORTAADDR2 +address_a[2] => ram_block1a5.PORTAADDR2 +address_a[2] => ram_block1a6.PORTAADDR2 +address_a[2] => ram_block1a7.PORTAADDR2 +address_a[2] => ram_block1a8.PORTAADDR2 +address_a[2] => ram_block1a9.PORTAADDR2 +address_a[2] => ram_block1a10.PORTAADDR2 +address_a[2] => ram_block1a11.PORTAADDR2 +address_a[2] => ram_block1a12.PORTAADDR2 +address_a[2] => ram_block1a13.PORTAADDR2 +address_a[2] => ram_block1a14.PORTAADDR2 +address_a[2] => ram_block1a15.PORTAADDR2 +address_a[2] => ram_block1a16.PORTAADDR2 +address_a[2] => ram_block1a17.PORTAADDR2 +address_a[2] => ram_block1a18.PORTAADDR2 +address_a[2] => ram_block1a19.PORTAADDR2 +address_a[2] => ram_block1a20.PORTAADDR2 +address_a[2] => ram_block1a21.PORTAADDR2 +address_a[2] => ram_block1a22.PORTAADDR2 +address_a[2] => ram_block1a23.PORTAADDR2 +address_a[2] => ram_block1a24.PORTAADDR2 +address_a[2] => ram_block1a25.PORTAADDR2 +address_a[2] => ram_block1a26.PORTAADDR2 +address_a[2] => ram_block1a27.PORTAADDR2 +address_a[2] => ram_block1a28.PORTAADDR2 +address_a[2] => ram_block1a29.PORTAADDR2 +address_a[2] => ram_block1a30.PORTAADDR2 +address_a[2] => ram_block1a31.PORTAADDR2 +address_a[3] => ram_block1a0.PORTAADDR3 +address_a[3] => ram_block1a1.PORTAADDR3 +address_a[3] => ram_block1a2.PORTAADDR3 +address_a[3] => ram_block1a3.PORTAADDR3 +address_a[3] => ram_block1a4.PORTAADDR3 +address_a[3] => ram_block1a5.PORTAADDR3 +address_a[3] => ram_block1a6.PORTAADDR3 +address_a[3] => ram_block1a7.PORTAADDR3 +address_a[3] => ram_block1a8.PORTAADDR3 +address_a[3] => ram_block1a9.PORTAADDR3 +address_a[3] => ram_block1a10.PORTAADDR3 +address_a[3] => ram_block1a11.PORTAADDR3 +address_a[3] => ram_block1a12.PORTAADDR3 +address_a[3] => ram_block1a13.PORTAADDR3 +address_a[3] => ram_block1a14.PORTAADDR3 +address_a[3] => ram_block1a15.PORTAADDR3 +address_a[3] => ram_block1a16.PORTAADDR3 +address_a[3] => ram_block1a17.PORTAADDR3 +address_a[3] => ram_block1a18.PORTAADDR3 +address_a[3] => ram_block1a19.PORTAADDR3 +address_a[3] => ram_block1a20.PORTAADDR3 +address_a[3] => ram_block1a21.PORTAADDR3 +address_a[3] => ram_block1a22.PORTAADDR3 +address_a[3] => ram_block1a23.PORTAADDR3 +address_a[3] => ram_block1a24.PORTAADDR3 +address_a[3] => ram_block1a25.PORTAADDR3 +address_a[3] => ram_block1a26.PORTAADDR3 +address_a[3] => ram_block1a27.PORTAADDR3 +address_a[3] => ram_block1a28.PORTAADDR3 +address_a[3] => ram_block1a29.PORTAADDR3 +address_a[3] => ram_block1a30.PORTAADDR3 +address_a[3] => ram_block1a31.PORTAADDR3 +address_a[4] => ram_block1a0.PORTAADDR4 +address_a[4] => ram_block1a1.PORTAADDR4 +address_a[4] => ram_block1a2.PORTAADDR4 +address_a[4] => ram_block1a3.PORTAADDR4 +address_a[4] => ram_block1a4.PORTAADDR4 +address_a[4] => ram_block1a5.PORTAADDR4 +address_a[4] => ram_block1a6.PORTAADDR4 +address_a[4] => ram_block1a7.PORTAADDR4 +address_a[4] => ram_block1a8.PORTAADDR4 +address_a[4] => ram_block1a9.PORTAADDR4 +address_a[4] => ram_block1a10.PORTAADDR4 +address_a[4] => ram_block1a11.PORTAADDR4 +address_a[4] => ram_block1a12.PORTAADDR4 +address_a[4] => ram_block1a13.PORTAADDR4 +address_a[4] => ram_block1a14.PORTAADDR4 +address_a[4] => ram_block1a15.PORTAADDR4 +address_a[4] => ram_block1a16.PORTAADDR4 +address_a[4] => ram_block1a17.PORTAADDR4 +address_a[4] => ram_block1a18.PORTAADDR4 +address_a[4] => ram_block1a19.PORTAADDR4 +address_a[4] => ram_block1a20.PORTAADDR4 +address_a[4] => ram_block1a21.PORTAADDR4 +address_a[4] => ram_block1a22.PORTAADDR4 +address_a[4] => ram_block1a23.PORTAADDR4 +address_a[4] => ram_block1a24.PORTAADDR4 +address_a[4] => ram_block1a25.PORTAADDR4 +address_a[4] => ram_block1a26.PORTAADDR4 +address_a[4] => ram_block1a27.PORTAADDR4 +address_a[4] => ram_block1a28.PORTAADDR4 +address_a[4] => ram_block1a29.PORTAADDR4 +address_a[4] => ram_block1a30.PORTAADDR4 +address_a[4] => ram_block1a31.PORTAADDR4 +address_b[0] => ram_block1a0.PORTBADDR +address_b[0] => ram_block1a1.PORTBADDR +address_b[0] => ram_block1a2.PORTBADDR +address_b[0] => ram_block1a3.PORTBADDR +address_b[0] => ram_block1a4.PORTBADDR +address_b[0] => ram_block1a5.PORTBADDR +address_b[0] => ram_block1a6.PORTBADDR +address_b[0] => ram_block1a7.PORTBADDR +address_b[0] => ram_block1a8.PORTBADDR +address_b[0] => ram_block1a9.PORTBADDR +address_b[0] => ram_block1a10.PORTBADDR +address_b[0] => ram_block1a11.PORTBADDR +address_b[0] => ram_block1a12.PORTBADDR +address_b[0] => ram_block1a13.PORTBADDR +address_b[0] => ram_block1a14.PORTBADDR +address_b[0] => ram_block1a15.PORTBADDR +address_b[0] => ram_block1a16.PORTBADDR +address_b[0] => ram_block1a17.PORTBADDR +address_b[0] => ram_block1a18.PORTBADDR +address_b[0] => ram_block1a19.PORTBADDR +address_b[0] => ram_block1a20.PORTBADDR +address_b[0] => ram_block1a21.PORTBADDR +address_b[0] => ram_block1a22.PORTBADDR +address_b[0] => ram_block1a23.PORTBADDR +address_b[0] => ram_block1a24.PORTBADDR +address_b[0] => ram_block1a25.PORTBADDR +address_b[0] => ram_block1a26.PORTBADDR +address_b[0] => ram_block1a27.PORTBADDR +address_b[0] => ram_block1a28.PORTBADDR +address_b[0] => ram_block1a29.PORTBADDR +address_b[0] => ram_block1a30.PORTBADDR +address_b[0] => ram_block1a31.PORTBADDR +address_b[1] => ram_block1a0.PORTBADDR1 +address_b[1] => ram_block1a1.PORTBADDR1 +address_b[1] => ram_block1a2.PORTBADDR1 +address_b[1] => ram_block1a3.PORTBADDR1 +address_b[1] => ram_block1a4.PORTBADDR1 +address_b[1] => ram_block1a5.PORTBADDR1 +address_b[1] => ram_block1a6.PORTBADDR1 +address_b[1] => ram_block1a7.PORTBADDR1 +address_b[1] => ram_block1a8.PORTBADDR1 +address_b[1] => ram_block1a9.PORTBADDR1 +address_b[1] => ram_block1a10.PORTBADDR1 +address_b[1] => ram_block1a11.PORTBADDR1 +address_b[1] => ram_block1a12.PORTBADDR1 +address_b[1] => ram_block1a13.PORTBADDR1 +address_b[1] => ram_block1a14.PORTBADDR1 +address_b[1] => ram_block1a15.PORTBADDR1 +address_b[1] => ram_block1a16.PORTBADDR1 +address_b[1] => ram_block1a17.PORTBADDR1 +address_b[1] => ram_block1a18.PORTBADDR1 +address_b[1] => ram_block1a19.PORTBADDR1 +address_b[1] => ram_block1a20.PORTBADDR1 +address_b[1] => ram_block1a21.PORTBADDR1 +address_b[1] => ram_block1a22.PORTBADDR1 +address_b[1] => ram_block1a23.PORTBADDR1 +address_b[1] => ram_block1a24.PORTBADDR1 +address_b[1] => ram_block1a25.PORTBADDR1 +address_b[1] => ram_block1a26.PORTBADDR1 +address_b[1] => ram_block1a27.PORTBADDR1 +address_b[1] => ram_block1a28.PORTBADDR1 +address_b[1] => ram_block1a29.PORTBADDR1 +address_b[1] => ram_block1a30.PORTBADDR1 +address_b[1] => ram_block1a31.PORTBADDR1 +address_b[2] => ram_block1a0.PORTBADDR2 +address_b[2] => ram_block1a1.PORTBADDR2 +address_b[2] => ram_block1a2.PORTBADDR2 +address_b[2] => ram_block1a3.PORTBADDR2 +address_b[2] => ram_block1a4.PORTBADDR2 +address_b[2] => ram_block1a5.PORTBADDR2 +address_b[2] => ram_block1a6.PORTBADDR2 +address_b[2] => ram_block1a7.PORTBADDR2 +address_b[2] => ram_block1a8.PORTBADDR2 +address_b[2] => ram_block1a9.PORTBADDR2 +address_b[2] => ram_block1a10.PORTBADDR2 +address_b[2] => ram_block1a11.PORTBADDR2 +address_b[2] => ram_block1a12.PORTBADDR2 +address_b[2] => ram_block1a13.PORTBADDR2 +address_b[2] => ram_block1a14.PORTBADDR2 +address_b[2] => ram_block1a15.PORTBADDR2 +address_b[2] => ram_block1a16.PORTBADDR2 +address_b[2] => ram_block1a17.PORTBADDR2 +address_b[2] => ram_block1a18.PORTBADDR2 +address_b[2] => ram_block1a19.PORTBADDR2 +address_b[2] => ram_block1a20.PORTBADDR2 +address_b[2] => ram_block1a21.PORTBADDR2 +address_b[2] => ram_block1a22.PORTBADDR2 +address_b[2] => ram_block1a23.PORTBADDR2 +address_b[2] => ram_block1a24.PORTBADDR2 +address_b[2] => ram_block1a25.PORTBADDR2 +address_b[2] => ram_block1a26.PORTBADDR2 +address_b[2] => ram_block1a27.PORTBADDR2 +address_b[2] => ram_block1a28.PORTBADDR2 +address_b[2] => ram_block1a29.PORTBADDR2 +address_b[2] => ram_block1a30.PORTBADDR2 +address_b[2] => ram_block1a31.PORTBADDR2 +address_b[3] => ram_block1a0.PORTBADDR3 +address_b[3] => ram_block1a1.PORTBADDR3 +address_b[3] => ram_block1a2.PORTBADDR3 +address_b[3] => ram_block1a3.PORTBADDR3 +address_b[3] => ram_block1a4.PORTBADDR3 +address_b[3] => ram_block1a5.PORTBADDR3 +address_b[3] => ram_block1a6.PORTBADDR3 +address_b[3] => ram_block1a7.PORTBADDR3 +address_b[3] => ram_block1a8.PORTBADDR3 +address_b[3] => ram_block1a9.PORTBADDR3 +address_b[3] => ram_block1a10.PORTBADDR3 +address_b[3] => ram_block1a11.PORTBADDR3 +address_b[3] => ram_block1a12.PORTBADDR3 +address_b[3] => ram_block1a13.PORTBADDR3 +address_b[3] => ram_block1a14.PORTBADDR3 +address_b[3] => ram_block1a15.PORTBADDR3 +address_b[3] => ram_block1a16.PORTBADDR3 +address_b[3] => ram_block1a17.PORTBADDR3 +address_b[3] => ram_block1a18.PORTBADDR3 +address_b[3] => ram_block1a19.PORTBADDR3 +address_b[3] => ram_block1a20.PORTBADDR3 +address_b[3] => ram_block1a21.PORTBADDR3 +address_b[3] => ram_block1a22.PORTBADDR3 +address_b[3] => ram_block1a23.PORTBADDR3 +address_b[3] => ram_block1a24.PORTBADDR3 +address_b[3] => ram_block1a25.PORTBADDR3 +address_b[3] => ram_block1a26.PORTBADDR3 +address_b[3] => ram_block1a27.PORTBADDR3 +address_b[3] => ram_block1a28.PORTBADDR3 +address_b[3] => ram_block1a29.PORTBADDR3 +address_b[3] => ram_block1a30.PORTBADDR3 +address_b[3] => ram_block1a31.PORTBADDR3 +address_b[4] => ram_block1a0.PORTBADDR4 +address_b[4] => ram_block1a1.PORTBADDR4 +address_b[4] => ram_block1a2.PORTBADDR4 +address_b[4] => ram_block1a3.PORTBADDR4 +address_b[4] => ram_block1a4.PORTBADDR4 +address_b[4] => ram_block1a5.PORTBADDR4 +address_b[4] => ram_block1a6.PORTBADDR4 +address_b[4] => ram_block1a7.PORTBADDR4 +address_b[4] => ram_block1a8.PORTBADDR4 +address_b[4] => ram_block1a9.PORTBADDR4 +address_b[4] => ram_block1a10.PORTBADDR4 +address_b[4] => ram_block1a11.PORTBADDR4 +address_b[4] => ram_block1a12.PORTBADDR4 +address_b[4] => ram_block1a13.PORTBADDR4 +address_b[4] => ram_block1a14.PORTBADDR4 +address_b[4] => ram_block1a15.PORTBADDR4 +address_b[4] => ram_block1a16.PORTBADDR4 +address_b[4] => ram_block1a17.PORTBADDR4 +address_b[4] => ram_block1a18.PORTBADDR4 +address_b[4] => ram_block1a19.PORTBADDR4 +address_b[4] => ram_block1a20.PORTBADDR4 +address_b[4] => ram_block1a21.PORTBADDR4 +address_b[4] => ram_block1a22.PORTBADDR4 +address_b[4] => ram_block1a23.PORTBADDR4 +address_b[4] => ram_block1a24.PORTBADDR4 +address_b[4] => ram_block1a25.PORTBADDR4 +address_b[4] => ram_block1a26.PORTBADDR4 +address_b[4] => ram_block1a27.PORTBADDR4 +address_b[4] => ram_block1a28.PORTBADDR4 +address_b[4] => ram_block1a29.PORTBADDR4 +address_b[4] => ram_block1a30.PORTBADDR4 +address_b[4] => ram_block1a31.PORTBADDR4 +clock0 => ram_block1a0.CLK0 +clock0 => ram_block1a1.CLK0 +clock0 => ram_block1a2.CLK0 +clock0 => ram_block1a3.CLK0 +clock0 => ram_block1a4.CLK0 +clock0 => ram_block1a5.CLK0 +clock0 => ram_block1a6.CLK0 +clock0 => ram_block1a7.CLK0 +clock0 => ram_block1a8.CLK0 +clock0 => ram_block1a9.CLK0 +clock0 => ram_block1a10.CLK0 +clock0 => ram_block1a11.CLK0 +clock0 => ram_block1a12.CLK0 +clock0 => ram_block1a13.CLK0 +clock0 => ram_block1a14.CLK0 +clock0 => ram_block1a15.CLK0 +clock0 => ram_block1a16.CLK0 +clock0 => ram_block1a17.CLK0 +clock0 => ram_block1a18.CLK0 +clock0 => ram_block1a19.CLK0 +clock0 => ram_block1a20.CLK0 +clock0 => ram_block1a21.CLK0 +clock0 => ram_block1a22.CLK0 +clock0 => ram_block1a23.CLK0 +clock0 => ram_block1a24.CLK0 +clock0 => ram_block1a25.CLK0 +clock0 => ram_block1a26.CLK0 +clock0 => ram_block1a27.CLK0 +clock0 => ram_block1a28.CLK0 +clock0 => ram_block1a29.CLK0 +clock0 => ram_block1a30.CLK0 +clock0 => ram_block1a31.CLK0 +data_a[0] => ram_block1a0.PORTADATAIN +data_a[1] => ram_block1a1.PORTADATAIN +data_a[2] => ram_block1a2.PORTADATAIN +data_a[3] => ram_block1a3.PORTADATAIN +data_a[4] => ram_block1a4.PORTADATAIN +data_a[5] => ram_block1a5.PORTADATAIN +data_a[6] => ram_block1a6.PORTADATAIN +data_a[7] => ram_block1a7.PORTADATAIN +data_a[8] => ram_block1a8.PORTADATAIN +data_a[9] => ram_block1a9.PORTADATAIN +data_a[10] => ram_block1a10.PORTADATAIN +data_a[11] => ram_block1a11.PORTADATAIN +data_a[12] => ram_block1a12.PORTADATAIN +data_a[13] => ram_block1a13.PORTADATAIN +data_a[14] => ram_block1a14.PORTADATAIN +data_a[15] => ram_block1a15.PORTADATAIN +data_a[16] => ram_block1a16.PORTADATAIN +data_a[17] => ram_block1a17.PORTADATAIN +data_a[18] => ram_block1a18.PORTADATAIN +data_a[19] => ram_block1a19.PORTADATAIN +data_a[20] => ram_block1a20.PORTADATAIN +data_a[21] => ram_block1a21.PORTADATAIN +data_a[22] => ram_block1a22.PORTADATAIN +data_a[23] => ram_block1a23.PORTADATAIN +data_a[24] => ram_block1a24.PORTADATAIN +data_a[25] => ram_block1a25.PORTADATAIN +data_a[26] => ram_block1a26.PORTADATAIN +data_a[27] => ram_block1a27.PORTADATAIN +data_a[28] => ram_block1a28.PORTADATAIN +data_a[29] => ram_block1a29.PORTADATAIN +data_a[30] => ram_block1a30.PORTADATAIN +data_a[31] => ram_block1a31.PORTADATAIN +q_b[0] <= ram_block1a0.PORTBDATAOUT +q_b[1] <= ram_block1a1.PORTBDATAOUT +q_b[2] <= ram_block1a2.PORTBDATAOUT +q_b[3] <= ram_block1a3.PORTBDATAOUT +q_b[4] <= ram_block1a4.PORTBDATAOUT +q_b[5] <= ram_block1a5.PORTBDATAOUT +q_b[6] <= ram_block1a6.PORTBDATAOUT +q_b[7] <= ram_block1a7.PORTBDATAOUT +q_b[8] <= ram_block1a8.PORTBDATAOUT +q_b[9] <= ram_block1a9.PORTBDATAOUT +q_b[10] <= ram_block1a10.PORTBDATAOUT +q_b[11] <= ram_block1a11.PORTBDATAOUT +q_b[12] <= ram_block1a12.PORTBDATAOUT +q_b[13] <= ram_block1a13.PORTBDATAOUT +q_b[14] <= ram_block1a14.PORTBDATAOUT +q_b[15] <= ram_block1a15.PORTBDATAOUT +q_b[16] <= ram_block1a16.PORTBDATAOUT +q_b[17] <= ram_block1a17.PORTBDATAOUT +q_b[18] <= ram_block1a18.PORTBDATAOUT +q_b[19] <= ram_block1a19.PORTBDATAOUT +q_b[20] <= ram_block1a20.PORTBDATAOUT +q_b[21] <= ram_block1a21.PORTBDATAOUT +q_b[22] <= ram_block1a22.PORTBDATAOUT +q_b[23] <= ram_block1a23.PORTBDATAOUT +q_b[24] <= ram_block1a24.PORTBDATAOUT +q_b[25] <= ram_block1a25.PORTBDATAOUT +q_b[26] <= ram_block1a26.PORTBDATAOUT +q_b[27] <= ram_block1a27.PORTBDATAOUT +q_b[28] <= ram_block1a28.PORTBDATAOUT +q_b[29] <= ram_block1a29.PORTBDATAOUT +q_b[30] <= ram_block1a30.PORTBDATAOUT +q_b[31] <= ram_block1a31.PORTBDATAOUT +wren_a => ram_block1a0.PORTAWE +wren_a => ram_block1a1.PORTAWE +wren_a => ram_block1a2.PORTAWE +wren_a => ram_block1a3.PORTAWE +wren_a => ram_block1a4.PORTAWE +wren_a => ram_block1a5.PORTAWE +wren_a => ram_block1a6.PORTAWE +wren_a => ram_block1a7.PORTAWE +wren_a => ram_block1a8.PORTAWE +wren_a => ram_block1a9.PORTAWE +wren_a => ram_block1a10.PORTAWE +wren_a => ram_block1a11.PORTAWE +wren_a => ram_block1a12.PORTAWE +wren_a => ram_block1a13.PORTAWE +wren_a => ram_block1a14.PORTAWE +wren_a => ram_block1a15.PORTAWE +wren_a => ram_block1a16.PORTAWE +wren_a => ram_block1a17.PORTAWE +wren_a => ram_block1a18.PORTAWE +wren_a => ram_block1a19.PORTAWE +wren_a => ram_block1a20.PORTAWE +wren_a => ram_block1a21.PORTAWE +wren_a => ram_block1a22.PORTAWE +wren_a => ram_block1a23.PORTAWE +wren_a => ram_block1a24.PORTAWE +wren_a => ram_block1a25.PORTAWE +wren_a => ram_block1a26.PORTAWE +wren_a => ram_block1a27.PORTAWE +wren_a => ram_block1a28.PORTAWE +wren_a => ram_block1a29.PORTAWE +wren_a => ram_block1a30.PORTAWE +wren_a => ram_block1a31.PORTAWE + + +|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_dc_tag_module:system_cpu_dc_tag +clock => clock.IN1 +data[0] => data[0].IN1 +data[1] => data[1].IN1 +data[2] => data[2].IN1 +data[3] => data[3].IN1 +data[4] => data[4].IN1 +data[5] => data[5].IN1 +data[6] => data[6].IN1 +data[7] => data[7].IN1 +data[8] => data[8].IN1 +data[9] => data[9].IN1 +data[10] => data[10].IN1 +data[11] => data[11].IN1 +data[12] => data[12].IN1 +data[13] => data[13].IN1 +data[14] => data[14].IN1 +data[15] => data[15].IN1 +rdaddress[0] => rdaddress[0].IN1 +rdaddress[1] => rdaddress[1].IN1 +rdaddress[2] => rdaddress[2].IN1 +rdaddress[3] => rdaddress[3].IN1 +rdaddress[4] => rdaddress[4].IN1 +rdaddress[5] => rdaddress[5].IN1 +rdaddress[6] => rdaddress[6].IN1 +wraddress[0] => wraddress[0].IN1 +wraddress[1] => wraddress[1].IN1 +wraddress[2] => wraddress[2].IN1 +wraddress[3] => wraddress[3].IN1 +wraddress[4] => wraddress[4].IN1 +wraddress[5] => wraddress[5].IN1 +wraddress[6] => wraddress[6].IN1 +wren => wren.IN1 +q[0] <= altsyncram:the_altsyncram.q_b +q[1] <= altsyncram:the_altsyncram.q_b +q[2] <= altsyncram:the_altsyncram.q_b +q[3] <= altsyncram:the_altsyncram.q_b +q[4] <= altsyncram:the_altsyncram.q_b +q[5] <= altsyncram:the_altsyncram.q_b +q[6] <= altsyncram:the_altsyncram.q_b +q[7] <= altsyncram:the_altsyncram.q_b +q[8] <= altsyncram:the_altsyncram.q_b +q[9] <= altsyncram:the_altsyncram.q_b +q[10] <= altsyncram:the_altsyncram.q_b +q[11] <= altsyncram:the_altsyncram.q_b +q[12] <= altsyncram:the_altsyncram.q_b +q[13] <= altsyncram:the_altsyncram.q_b +q[14] <= altsyncram:the_altsyncram.q_b +q[15] <= altsyncram:the_altsyncram.q_b + + +|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_dc_tag_module:system_cpu_dc_tag|altsyncram:the_altsyncram +wren_a => altsyncram_d9g1:auto_generated.wren_a +rden_a => ~NO_FANOUT~ +wren_b => ~NO_FANOUT~ +rden_b => ~NO_FANOUT~ +data_a[0] => altsyncram_d9g1:auto_generated.data_a[0] +data_a[1] => altsyncram_d9g1:auto_generated.data_a[1] +data_a[2] => altsyncram_d9g1:auto_generated.data_a[2] +data_a[3] => altsyncram_d9g1:auto_generated.data_a[3] +data_a[4] => altsyncram_d9g1:auto_generated.data_a[4] +data_a[5] => altsyncram_d9g1:auto_generated.data_a[5] +data_a[6] => altsyncram_d9g1:auto_generated.data_a[6] +data_a[7] => altsyncram_d9g1:auto_generated.data_a[7] +data_a[8] => altsyncram_d9g1:auto_generated.data_a[8] +data_a[9] => altsyncram_d9g1:auto_generated.data_a[9] +data_a[10] => altsyncram_d9g1:auto_generated.data_a[10] +data_a[11] => altsyncram_d9g1:auto_generated.data_a[11] +data_a[12] => altsyncram_d9g1:auto_generated.data_a[12] +data_a[13] => altsyncram_d9g1:auto_generated.data_a[13] +data_a[14] => altsyncram_d9g1:auto_generated.data_a[14] +data_a[15] => altsyncram_d9g1:auto_generated.data_a[15] +data_b[0] => ~NO_FANOUT~ +data_b[1] => ~NO_FANOUT~ +data_b[2] => ~NO_FANOUT~ +data_b[3] => ~NO_FANOUT~ +data_b[4] => ~NO_FANOUT~ +data_b[5] => ~NO_FANOUT~ +data_b[6] => ~NO_FANOUT~ +data_b[7] => ~NO_FANOUT~ +data_b[8] => ~NO_FANOUT~ +data_b[9] => ~NO_FANOUT~ +data_b[10] => ~NO_FANOUT~ +data_b[11] => ~NO_FANOUT~ +data_b[12] => ~NO_FANOUT~ +data_b[13] => ~NO_FANOUT~ +data_b[14] => ~NO_FANOUT~ +data_b[15] => ~NO_FANOUT~ +address_a[0] => altsyncram_d9g1:auto_generated.address_a[0] +address_a[1] => altsyncram_d9g1:auto_generated.address_a[1] +address_a[2] => altsyncram_d9g1:auto_generated.address_a[2] +address_a[3] => altsyncram_d9g1:auto_generated.address_a[3] +address_a[4] => altsyncram_d9g1:auto_generated.address_a[4] +address_a[5] => altsyncram_d9g1:auto_generated.address_a[5] +address_a[6] => altsyncram_d9g1:auto_generated.address_a[6] +address_b[0] => altsyncram_d9g1:auto_generated.address_b[0] +address_b[1] => altsyncram_d9g1:auto_generated.address_b[1] +address_b[2] => altsyncram_d9g1:auto_generated.address_b[2] +address_b[3] => altsyncram_d9g1:auto_generated.address_b[3] +address_b[4] => altsyncram_d9g1:auto_generated.address_b[4] +address_b[5] => altsyncram_d9g1:auto_generated.address_b[5] +address_b[6] => altsyncram_d9g1:auto_generated.address_b[6] +addressstall_a => ~NO_FANOUT~ +addressstall_b => ~NO_FANOUT~ +clock0 => altsyncram_d9g1:auto_generated.clock0 +clock1 => ~NO_FANOUT~ +clocken0 => ~NO_FANOUT~ +clocken1 => ~NO_FANOUT~ +clocken2 => ~NO_FANOUT~ +clocken3 => ~NO_FANOUT~ +aclr0 => ~NO_FANOUT~ +aclr1 => ~NO_FANOUT~ +byteena_a[0] => ~NO_FANOUT~ +byteena_b[0] => ~NO_FANOUT~ +q_a[0] <= +q_a[1] <= +q_a[2] <= +q_a[3] <= +q_a[4] <= +q_a[5] <= +q_a[6] <= +q_a[7] <= +q_a[8] <= +q_a[9] <= +q_a[10] <= +q_a[11] <= +q_a[12] <= +q_a[13] <= +q_a[14] <= +q_a[15] <= +q_b[0] <= altsyncram_d9g1:auto_generated.q_b[0] +q_b[1] <= altsyncram_d9g1:auto_generated.q_b[1] +q_b[2] <= altsyncram_d9g1:auto_generated.q_b[2] +q_b[3] <= altsyncram_d9g1:auto_generated.q_b[3] +q_b[4] <= altsyncram_d9g1:auto_generated.q_b[4] +q_b[5] <= altsyncram_d9g1:auto_generated.q_b[5] +q_b[6] <= altsyncram_d9g1:auto_generated.q_b[6] +q_b[7] <= altsyncram_d9g1:auto_generated.q_b[7] +q_b[8] <= altsyncram_d9g1:auto_generated.q_b[8] +q_b[9] <= altsyncram_d9g1:auto_generated.q_b[9] +q_b[10] <= altsyncram_d9g1:auto_generated.q_b[10] +q_b[11] <= altsyncram_d9g1:auto_generated.q_b[11] +q_b[12] <= altsyncram_d9g1:auto_generated.q_b[12] +q_b[13] <= altsyncram_d9g1:auto_generated.q_b[13] +q_b[14] <= altsyncram_d9g1:auto_generated.q_b[14] +q_b[15] <= altsyncram_d9g1:auto_generated.q_b[15] +eccstatus[0] <= +eccstatus[1] <= +eccstatus[2] <= + + +|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_dc_tag_module:system_cpu_dc_tag|altsyncram:the_altsyncram|altsyncram_d9g1:auto_generated +address_a[0] => ram_block1a0.PORTAADDR +address_a[0] => ram_block1a1.PORTAADDR +address_a[0] => ram_block1a2.PORTAADDR +address_a[0] => ram_block1a3.PORTAADDR +address_a[0] => ram_block1a4.PORTAADDR +address_a[0] => ram_block1a5.PORTAADDR +address_a[0] => ram_block1a6.PORTAADDR +address_a[0] => ram_block1a7.PORTAADDR +address_a[0] => ram_block1a8.PORTAADDR +address_a[0] => ram_block1a9.PORTAADDR +address_a[0] => ram_block1a10.PORTAADDR +address_a[0] => ram_block1a11.PORTAADDR +address_a[0] => ram_block1a12.PORTAADDR +address_a[0] => ram_block1a13.PORTAADDR +address_a[0] => ram_block1a14.PORTAADDR +address_a[0] => ram_block1a15.PORTAADDR +address_a[1] => ram_block1a0.PORTAADDR1 +address_a[1] => ram_block1a1.PORTAADDR1 +address_a[1] => ram_block1a2.PORTAADDR1 +address_a[1] => ram_block1a3.PORTAADDR1 +address_a[1] => ram_block1a4.PORTAADDR1 +address_a[1] => ram_block1a5.PORTAADDR1 +address_a[1] => ram_block1a6.PORTAADDR1 +address_a[1] => ram_block1a7.PORTAADDR1 +address_a[1] => ram_block1a8.PORTAADDR1 +address_a[1] => ram_block1a9.PORTAADDR1 +address_a[1] => ram_block1a10.PORTAADDR1 +address_a[1] => ram_block1a11.PORTAADDR1 +address_a[1] => ram_block1a12.PORTAADDR1 +address_a[1] => ram_block1a13.PORTAADDR1 +address_a[1] => ram_block1a14.PORTAADDR1 +address_a[1] => ram_block1a15.PORTAADDR1 +address_a[2] => ram_block1a0.PORTAADDR2 +address_a[2] => ram_block1a1.PORTAADDR2 +address_a[2] => ram_block1a2.PORTAADDR2 +address_a[2] => ram_block1a3.PORTAADDR2 +address_a[2] => ram_block1a4.PORTAADDR2 +address_a[2] => ram_block1a5.PORTAADDR2 +address_a[2] => ram_block1a6.PORTAADDR2 +address_a[2] => ram_block1a7.PORTAADDR2 +address_a[2] => ram_block1a8.PORTAADDR2 +address_a[2] => ram_block1a9.PORTAADDR2 +address_a[2] => ram_block1a10.PORTAADDR2 +address_a[2] => ram_block1a11.PORTAADDR2 +address_a[2] => ram_block1a12.PORTAADDR2 +address_a[2] => ram_block1a13.PORTAADDR2 +address_a[2] => ram_block1a14.PORTAADDR2 +address_a[2] => ram_block1a15.PORTAADDR2 +address_a[3] => ram_block1a0.PORTAADDR3 +address_a[3] => ram_block1a1.PORTAADDR3 +address_a[3] => ram_block1a2.PORTAADDR3 +address_a[3] => ram_block1a3.PORTAADDR3 +address_a[3] => ram_block1a4.PORTAADDR3 +address_a[3] => ram_block1a5.PORTAADDR3 +address_a[3] => ram_block1a6.PORTAADDR3 +address_a[3] => ram_block1a7.PORTAADDR3 +address_a[3] => ram_block1a8.PORTAADDR3 +address_a[3] => ram_block1a9.PORTAADDR3 +address_a[3] => ram_block1a10.PORTAADDR3 +address_a[3] => ram_block1a11.PORTAADDR3 +address_a[3] => ram_block1a12.PORTAADDR3 +address_a[3] => ram_block1a13.PORTAADDR3 +address_a[3] => ram_block1a14.PORTAADDR3 +address_a[3] => ram_block1a15.PORTAADDR3 +address_a[4] => ram_block1a0.PORTAADDR4 +address_a[4] => ram_block1a1.PORTAADDR4 +address_a[4] => ram_block1a2.PORTAADDR4 +address_a[4] => ram_block1a3.PORTAADDR4 +address_a[4] => ram_block1a4.PORTAADDR4 +address_a[4] => ram_block1a5.PORTAADDR4 +address_a[4] => ram_block1a6.PORTAADDR4 +address_a[4] => ram_block1a7.PORTAADDR4 +address_a[4] => ram_block1a8.PORTAADDR4 +address_a[4] => ram_block1a9.PORTAADDR4 +address_a[4] => ram_block1a10.PORTAADDR4 +address_a[4] => ram_block1a11.PORTAADDR4 +address_a[4] => ram_block1a12.PORTAADDR4 +address_a[4] => ram_block1a13.PORTAADDR4 +address_a[4] => ram_block1a14.PORTAADDR4 +address_a[4] => ram_block1a15.PORTAADDR4 +address_a[5] => ram_block1a0.PORTAADDR5 +address_a[5] => ram_block1a1.PORTAADDR5 +address_a[5] => ram_block1a2.PORTAADDR5 +address_a[5] => ram_block1a3.PORTAADDR5 +address_a[5] => ram_block1a4.PORTAADDR5 +address_a[5] => ram_block1a5.PORTAADDR5 +address_a[5] => ram_block1a6.PORTAADDR5 +address_a[5] => ram_block1a7.PORTAADDR5 +address_a[5] => ram_block1a8.PORTAADDR5 +address_a[5] => ram_block1a9.PORTAADDR5 +address_a[5] => ram_block1a10.PORTAADDR5 +address_a[5] => ram_block1a11.PORTAADDR5 +address_a[5] => ram_block1a12.PORTAADDR5 +address_a[5] => ram_block1a13.PORTAADDR5 +address_a[5] => ram_block1a14.PORTAADDR5 +address_a[5] => ram_block1a15.PORTAADDR5 +address_a[6] => ram_block1a0.PORTAADDR6 +address_a[6] => ram_block1a1.PORTAADDR6 +address_a[6] => ram_block1a2.PORTAADDR6 +address_a[6] => ram_block1a3.PORTAADDR6 +address_a[6] => ram_block1a4.PORTAADDR6 +address_a[6] => ram_block1a5.PORTAADDR6 +address_a[6] => ram_block1a6.PORTAADDR6 +address_a[6] => ram_block1a7.PORTAADDR6 +address_a[6] => ram_block1a8.PORTAADDR6 +address_a[6] => ram_block1a9.PORTAADDR6 +address_a[6] => ram_block1a10.PORTAADDR6 +address_a[6] => ram_block1a11.PORTAADDR6 +address_a[6] => ram_block1a12.PORTAADDR6 +address_a[6] => ram_block1a13.PORTAADDR6 +address_a[6] => ram_block1a14.PORTAADDR6 +address_a[6] => ram_block1a15.PORTAADDR6 +address_b[0] => ram_block1a0.PORTBADDR +address_b[0] => ram_block1a1.PORTBADDR +address_b[0] => ram_block1a2.PORTBADDR +address_b[0] => ram_block1a3.PORTBADDR +address_b[0] => ram_block1a4.PORTBADDR +address_b[0] => ram_block1a5.PORTBADDR +address_b[0] => ram_block1a6.PORTBADDR +address_b[0] => ram_block1a7.PORTBADDR +address_b[0] => ram_block1a8.PORTBADDR +address_b[0] => ram_block1a9.PORTBADDR +address_b[0] => ram_block1a10.PORTBADDR +address_b[0] => ram_block1a11.PORTBADDR +address_b[0] => ram_block1a12.PORTBADDR +address_b[0] => ram_block1a13.PORTBADDR +address_b[0] => ram_block1a14.PORTBADDR +address_b[0] => ram_block1a15.PORTBADDR +address_b[1] => ram_block1a0.PORTBADDR1 +address_b[1] => ram_block1a1.PORTBADDR1 +address_b[1] => ram_block1a2.PORTBADDR1 +address_b[1] => ram_block1a3.PORTBADDR1 +address_b[1] => ram_block1a4.PORTBADDR1 +address_b[1] => ram_block1a5.PORTBADDR1 +address_b[1] => ram_block1a6.PORTBADDR1 +address_b[1] => ram_block1a7.PORTBADDR1 +address_b[1] => ram_block1a8.PORTBADDR1 +address_b[1] => ram_block1a9.PORTBADDR1 +address_b[1] => ram_block1a10.PORTBADDR1 +address_b[1] => ram_block1a11.PORTBADDR1 +address_b[1] => ram_block1a12.PORTBADDR1 +address_b[1] => ram_block1a13.PORTBADDR1 +address_b[1] => ram_block1a14.PORTBADDR1 +address_b[1] => ram_block1a15.PORTBADDR1 +address_b[2] => ram_block1a0.PORTBADDR2 +address_b[2] => ram_block1a1.PORTBADDR2 +address_b[2] => ram_block1a2.PORTBADDR2 +address_b[2] => ram_block1a3.PORTBADDR2 +address_b[2] => ram_block1a4.PORTBADDR2 +address_b[2] => ram_block1a5.PORTBADDR2 +address_b[2] => ram_block1a6.PORTBADDR2 +address_b[2] => ram_block1a7.PORTBADDR2 +address_b[2] => ram_block1a8.PORTBADDR2 +address_b[2] => ram_block1a9.PORTBADDR2 +address_b[2] => ram_block1a10.PORTBADDR2 +address_b[2] => ram_block1a11.PORTBADDR2 +address_b[2] => ram_block1a12.PORTBADDR2 +address_b[2] => ram_block1a13.PORTBADDR2 +address_b[2] => ram_block1a14.PORTBADDR2 +address_b[2] => ram_block1a15.PORTBADDR2 +address_b[3] => ram_block1a0.PORTBADDR3 +address_b[3] => ram_block1a1.PORTBADDR3 +address_b[3] => ram_block1a2.PORTBADDR3 +address_b[3] => ram_block1a3.PORTBADDR3 +address_b[3] => ram_block1a4.PORTBADDR3 +address_b[3] => ram_block1a5.PORTBADDR3 +address_b[3] => ram_block1a6.PORTBADDR3 +address_b[3] => ram_block1a7.PORTBADDR3 +address_b[3] => ram_block1a8.PORTBADDR3 +address_b[3] => ram_block1a9.PORTBADDR3 +address_b[3] => ram_block1a10.PORTBADDR3 +address_b[3] => ram_block1a11.PORTBADDR3 +address_b[3] => ram_block1a12.PORTBADDR3 +address_b[3] => ram_block1a13.PORTBADDR3 +address_b[3] => ram_block1a14.PORTBADDR3 +address_b[3] => ram_block1a15.PORTBADDR3 +address_b[4] => ram_block1a0.PORTBADDR4 +address_b[4] => ram_block1a1.PORTBADDR4 +address_b[4] => ram_block1a2.PORTBADDR4 +address_b[4] => ram_block1a3.PORTBADDR4 +address_b[4] => ram_block1a4.PORTBADDR4 +address_b[4] => ram_block1a5.PORTBADDR4 +address_b[4] => ram_block1a6.PORTBADDR4 +address_b[4] => ram_block1a7.PORTBADDR4 +address_b[4] => ram_block1a8.PORTBADDR4 +address_b[4] => ram_block1a9.PORTBADDR4 +address_b[4] => ram_block1a10.PORTBADDR4 +address_b[4] => ram_block1a11.PORTBADDR4 +address_b[4] => ram_block1a12.PORTBADDR4 +address_b[4] => ram_block1a13.PORTBADDR4 +address_b[4] => ram_block1a14.PORTBADDR4 +address_b[4] => ram_block1a15.PORTBADDR4 +address_b[5] => ram_block1a0.PORTBADDR5 +address_b[5] => ram_block1a1.PORTBADDR5 +address_b[5] => ram_block1a2.PORTBADDR5 +address_b[5] => ram_block1a3.PORTBADDR5 +address_b[5] => ram_block1a4.PORTBADDR5 +address_b[5] => ram_block1a5.PORTBADDR5 +address_b[5] => ram_block1a6.PORTBADDR5 +address_b[5] => ram_block1a7.PORTBADDR5 +address_b[5] => ram_block1a8.PORTBADDR5 +address_b[5] => ram_block1a9.PORTBADDR5 +address_b[5] => ram_block1a10.PORTBADDR5 +address_b[5] => ram_block1a11.PORTBADDR5 +address_b[5] => ram_block1a12.PORTBADDR5 +address_b[5] => ram_block1a13.PORTBADDR5 +address_b[5] => ram_block1a14.PORTBADDR5 +address_b[5] => ram_block1a15.PORTBADDR5 +address_b[6] => ram_block1a0.PORTBADDR6 +address_b[6] => ram_block1a1.PORTBADDR6 +address_b[6] => ram_block1a2.PORTBADDR6 +address_b[6] => ram_block1a3.PORTBADDR6 +address_b[6] => ram_block1a4.PORTBADDR6 +address_b[6] => ram_block1a5.PORTBADDR6 +address_b[6] => ram_block1a6.PORTBADDR6 +address_b[6] => ram_block1a7.PORTBADDR6 +address_b[6] => ram_block1a8.PORTBADDR6 +address_b[6] => ram_block1a9.PORTBADDR6 +address_b[6] => ram_block1a10.PORTBADDR6 +address_b[6] => ram_block1a11.PORTBADDR6 +address_b[6] => ram_block1a12.PORTBADDR6 +address_b[6] => ram_block1a13.PORTBADDR6 +address_b[6] => ram_block1a14.PORTBADDR6 +address_b[6] => ram_block1a15.PORTBADDR6 +clock0 => ram_block1a0.CLK0 +clock0 => ram_block1a1.CLK0 +clock0 => ram_block1a2.CLK0 +clock0 => ram_block1a3.CLK0 +clock0 => ram_block1a4.CLK0 +clock0 => ram_block1a5.CLK0 +clock0 => ram_block1a6.CLK0 +clock0 => ram_block1a7.CLK0 +clock0 => ram_block1a8.CLK0 +clock0 => ram_block1a9.CLK0 +clock0 => ram_block1a10.CLK0 +clock0 => ram_block1a11.CLK0 +clock0 => ram_block1a12.CLK0 +clock0 => ram_block1a13.CLK0 +clock0 => ram_block1a14.CLK0 +clock0 => ram_block1a15.CLK0 +data_a[0] => ram_block1a0.PORTADATAIN +data_a[1] => ram_block1a1.PORTADATAIN +data_a[2] => ram_block1a2.PORTADATAIN +data_a[3] => ram_block1a3.PORTADATAIN +data_a[4] => ram_block1a4.PORTADATAIN +data_a[5] => ram_block1a5.PORTADATAIN +data_a[6] => ram_block1a6.PORTADATAIN +data_a[7] => ram_block1a7.PORTADATAIN +data_a[8] => ram_block1a8.PORTADATAIN +data_a[9] => ram_block1a9.PORTADATAIN +data_a[10] => ram_block1a10.PORTADATAIN +data_a[11] => ram_block1a11.PORTADATAIN +data_a[12] => ram_block1a12.PORTADATAIN +data_a[13] => ram_block1a13.PORTADATAIN +data_a[14] => ram_block1a14.PORTADATAIN +data_a[15] => ram_block1a15.PORTADATAIN +q_b[0] <= ram_block1a0.PORTBDATAOUT +q_b[1] <= ram_block1a1.PORTBDATAOUT +q_b[2] <= ram_block1a2.PORTBDATAOUT +q_b[3] <= ram_block1a3.PORTBDATAOUT +q_b[4] <= ram_block1a4.PORTBDATAOUT +q_b[5] <= ram_block1a5.PORTBDATAOUT +q_b[6] <= ram_block1a6.PORTBDATAOUT +q_b[7] <= ram_block1a7.PORTBDATAOUT +q_b[8] <= ram_block1a8.PORTBDATAOUT +q_b[9] <= ram_block1a9.PORTBDATAOUT +q_b[10] <= ram_block1a10.PORTBDATAOUT +q_b[11] <= ram_block1a11.PORTBDATAOUT +q_b[12] <= ram_block1a12.PORTBDATAOUT +q_b[13] <= ram_block1a13.PORTBDATAOUT +q_b[14] <= ram_block1a14.PORTBDATAOUT +q_b[15] <= ram_block1a15.PORTBDATAOUT +wren_a => ram_block1a0.PORTAWE +wren_a => ram_block1a1.PORTAWE +wren_a => ram_block1a2.PORTAWE +wren_a => ram_block1a3.PORTAWE +wren_a => ram_block1a4.PORTAWE +wren_a => ram_block1a5.PORTAWE +wren_a => ram_block1a6.PORTAWE +wren_a => ram_block1a7.PORTAWE +wren_a => ram_block1a8.PORTAWE +wren_a => ram_block1a9.PORTAWE +wren_a => ram_block1a10.PORTAWE +wren_a => ram_block1a11.PORTAWE +wren_a => ram_block1a12.PORTAWE +wren_a => ram_block1a13.PORTAWE +wren_a => ram_block1a14.PORTAWE +wren_a => ram_block1a15.PORTAWE + + +|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_dc_data_module:system_cpu_dc_data +byteenable[0] => byteenable[0].IN1 +byteenable[1] => byteenable[1].IN1 +byteenable[2] => byteenable[2].IN1 +byteenable[3] => byteenable[3].IN1 +clock => clock.IN1 +data[0] => data[0].IN1 +data[1] => data[1].IN1 +data[2] => data[2].IN1 +data[3] => data[3].IN1 +data[4] => data[4].IN1 +data[5] => data[5].IN1 +data[6] => data[6].IN1 +data[7] => data[7].IN1 +data[8] => data[8].IN1 +data[9] => data[9].IN1 +data[10] => data[10].IN1 +data[11] => data[11].IN1 +data[12] => data[12].IN1 +data[13] => data[13].IN1 +data[14] => data[14].IN1 +data[15] => data[15].IN1 +data[16] => data[16].IN1 +data[17] => data[17].IN1 +data[18] => data[18].IN1 +data[19] => data[19].IN1 +data[20] => data[20].IN1 +data[21] => data[21].IN1 +data[22] => data[22].IN1 +data[23] => data[23].IN1 +data[24] => data[24].IN1 +data[25] => data[25].IN1 +data[26] => data[26].IN1 +data[27] => data[27].IN1 +data[28] => data[28].IN1 +data[29] => data[29].IN1 +data[30] => data[30].IN1 +data[31] => data[31].IN1 +rdaddress[0] => rdaddress[0].IN1 +rdaddress[1] => rdaddress[1].IN1 +rdaddress[2] => rdaddress[2].IN1 +rdaddress[3] => rdaddress[3].IN1 +rdaddress[4] => rdaddress[4].IN1 +rdaddress[5] => rdaddress[5].IN1 +rdaddress[6] => rdaddress[6].IN1 +rdaddress[7] => rdaddress[7].IN1 +rdaddress[8] => rdaddress[8].IN1 +rdaddress[9] => rdaddress[9].IN1 +wraddress[0] => wraddress[0].IN1 +wraddress[1] => wraddress[1].IN1 +wraddress[2] => wraddress[2].IN1 +wraddress[3] => wraddress[3].IN1 +wraddress[4] => wraddress[4].IN1 +wraddress[5] => wraddress[5].IN1 +wraddress[6] => wraddress[6].IN1 +wraddress[7] => wraddress[7].IN1 +wraddress[8] => wraddress[8].IN1 +wraddress[9] => wraddress[9].IN1 +wren => wren.IN1 +q[0] <= altsyncram:the_altsyncram.q_b +q[1] <= altsyncram:the_altsyncram.q_b +q[2] <= altsyncram:the_altsyncram.q_b +q[3] <= altsyncram:the_altsyncram.q_b +q[4] <= altsyncram:the_altsyncram.q_b +q[5] <= altsyncram:the_altsyncram.q_b +q[6] <= altsyncram:the_altsyncram.q_b +q[7] <= altsyncram:the_altsyncram.q_b +q[8] <= altsyncram:the_altsyncram.q_b +q[9] <= altsyncram:the_altsyncram.q_b +q[10] <= altsyncram:the_altsyncram.q_b +q[11] <= altsyncram:the_altsyncram.q_b +q[12] <= altsyncram:the_altsyncram.q_b +q[13] <= altsyncram:the_altsyncram.q_b +q[14] <= altsyncram:the_altsyncram.q_b +q[15] <= altsyncram:the_altsyncram.q_b +q[16] <= altsyncram:the_altsyncram.q_b +q[17] <= altsyncram:the_altsyncram.q_b +q[18] <= altsyncram:the_altsyncram.q_b +q[19] <= altsyncram:the_altsyncram.q_b +q[20] <= altsyncram:the_altsyncram.q_b +q[21] <= altsyncram:the_altsyncram.q_b +q[22] <= altsyncram:the_altsyncram.q_b +q[23] <= altsyncram:the_altsyncram.q_b +q[24] <= altsyncram:the_altsyncram.q_b +q[25] <= altsyncram:the_altsyncram.q_b +q[26] <= altsyncram:the_altsyncram.q_b +q[27] <= altsyncram:the_altsyncram.q_b +q[28] <= altsyncram:the_altsyncram.q_b +q[29] <= altsyncram:the_altsyncram.q_b +q[30] <= altsyncram:the_altsyncram.q_b +q[31] <= altsyncram:the_altsyncram.q_b + + +|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_dc_data_module:system_cpu_dc_data|altsyncram:the_altsyncram +wren_a => altsyncram_2jf1:auto_generated.wren_a +rden_a => ~NO_FANOUT~ +wren_b => ~NO_FANOUT~ +rden_b => ~NO_FANOUT~ +data_a[0] => altsyncram_2jf1:auto_generated.data_a[0] +data_a[1] => altsyncram_2jf1:auto_generated.data_a[1] +data_a[2] => altsyncram_2jf1:auto_generated.data_a[2] +data_a[3] => altsyncram_2jf1:auto_generated.data_a[3] +data_a[4] => altsyncram_2jf1:auto_generated.data_a[4] +data_a[5] => altsyncram_2jf1:auto_generated.data_a[5] +data_a[6] => altsyncram_2jf1:auto_generated.data_a[6] +data_a[7] => altsyncram_2jf1:auto_generated.data_a[7] +data_a[8] => altsyncram_2jf1:auto_generated.data_a[8] +data_a[9] => altsyncram_2jf1:auto_generated.data_a[9] +data_a[10] => altsyncram_2jf1:auto_generated.data_a[10] +data_a[11] => altsyncram_2jf1:auto_generated.data_a[11] +data_a[12] => altsyncram_2jf1:auto_generated.data_a[12] +data_a[13] => altsyncram_2jf1:auto_generated.data_a[13] +data_a[14] => altsyncram_2jf1:auto_generated.data_a[14] +data_a[15] => altsyncram_2jf1:auto_generated.data_a[15] +data_a[16] => altsyncram_2jf1:auto_generated.data_a[16] +data_a[17] => altsyncram_2jf1:auto_generated.data_a[17] +data_a[18] => altsyncram_2jf1:auto_generated.data_a[18] +data_a[19] => altsyncram_2jf1:auto_generated.data_a[19] +data_a[20] => altsyncram_2jf1:auto_generated.data_a[20] +data_a[21] => altsyncram_2jf1:auto_generated.data_a[21] +data_a[22] => altsyncram_2jf1:auto_generated.data_a[22] +data_a[23] => altsyncram_2jf1:auto_generated.data_a[23] +data_a[24] => altsyncram_2jf1:auto_generated.data_a[24] +data_a[25] => altsyncram_2jf1:auto_generated.data_a[25] +data_a[26] => altsyncram_2jf1:auto_generated.data_a[26] +data_a[27] => altsyncram_2jf1:auto_generated.data_a[27] +data_a[28] => altsyncram_2jf1:auto_generated.data_a[28] +data_a[29] => altsyncram_2jf1:auto_generated.data_a[29] +data_a[30] => altsyncram_2jf1:auto_generated.data_a[30] +data_a[31] => altsyncram_2jf1:auto_generated.data_a[31] +data_b[0] => ~NO_FANOUT~ +data_b[1] => ~NO_FANOUT~ +data_b[2] => ~NO_FANOUT~ +data_b[3] => ~NO_FANOUT~ +data_b[4] => ~NO_FANOUT~ +data_b[5] => ~NO_FANOUT~ +data_b[6] => ~NO_FANOUT~ +data_b[7] => ~NO_FANOUT~ +data_b[8] => ~NO_FANOUT~ +data_b[9] => ~NO_FANOUT~ +data_b[10] => ~NO_FANOUT~ +data_b[11] => ~NO_FANOUT~ +data_b[12] => ~NO_FANOUT~ +data_b[13] => ~NO_FANOUT~ +data_b[14] => ~NO_FANOUT~ +data_b[15] => ~NO_FANOUT~ +data_b[16] => ~NO_FANOUT~ +data_b[17] => ~NO_FANOUT~ +data_b[18] => ~NO_FANOUT~ +data_b[19] => ~NO_FANOUT~ +data_b[20] => ~NO_FANOUT~ +data_b[21] => ~NO_FANOUT~ +data_b[22] => ~NO_FANOUT~ +data_b[23] => ~NO_FANOUT~ +data_b[24] => ~NO_FANOUT~ +data_b[25] => ~NO_FANOUT~ +data_b[26] => ~NO_FANOUT~ +data_b[27] => ~NO_FANOUT~ +data_b[28] => ~NO_FANOUT~ +data_b[29] => ~NO_FANOUT~ +data_b[30] => ~NO_FANOUT~ +data_b[31] => ~NO_FANOUT~ +address_a[0] => altsyncram_2jf1:auto_generated.address_a[0] +address_a[1] => altsyncram_2jf1:auto_generated.address_a[1] +address_a[2] => altsyncram_2jf1:auto_generated.address_a[2] +address_a[3] => altsyncram_2jf1:auto_generated.address_a[3] +address_a[4] => altsyncram_2jf1:auto_generated.address_a[4] +address_a[5] => altsyncram_2jf1:auto_generated.address_a[5] +address_a[6] => altsyncram_2jf1:auto_generated.address_a[6] +address_a[7] => altsyncram_2jf1:auto_generated.address_a[7] +address_a[8] => altsyncram_2jf1:auto_generated.address_a[8] +address_a[9] => altsyncram_2jf1:auto_generated.address_a[9] +address_b[0] => altsyncram_2jf1:auto_generated.address_b[0] +address_b[1] => altsyncram_2jf1:auto_generated.address_b[1] +address_b[2] => altsyncram_2jf1:auto_generated.address_b[2] +address_b[3] => altsyncram_2jf1:auto_generated.address_b[3] +address_b[4] => altsyncram_2jf1:auto_generated.address_b[4] +address_b[5] => altsyncram_2jf1:auto_generated.address_b[5] +address_b[6] => altsyncram_2jf1:auto_generated.address_b[6] +address_b[7] => altsyncram_2jf1:auto_generated.address_b[7] +address_b[8] => altsyncram_2jf1:auto_generated.address_b[8] +address_b[9] => altsyncram_2jf1:auto_generated.address_b[9] +addressstall_a => ~NO_FANOUT~ +addressstall_b => ~NO_FANOUT~ +clock0 => altsyncram_2jf1:auto_generated.clock0 +clock1 => ~NO_FANOUT~ +clocken0 => ~NO_FANOUT~ +clocken1 => ~NO_FANOUT~ +clocken2 => ~NO_FANOUT~ +clocken3 => ~NO_FANOUT~ +aclr0 => ~NO_FANOUT~ +aclr1 => ~NO_FANOUT~ +byteena_a[0] => altsyncram_2jf1:auto_generated.byteena_a[0] +byteena_a[1] => altsyncram_2jf1:auto_generated.byteena_a[1] +byteena_a[2] => altsyncram_2jf1:auto_generated.byteena_a[2] +byteena_a[3] => altsyncram_2jf1:auto_generated.byteena_a[3] +byteena_b[0] => ~NO_FANOUT~ +q_a[0] <= +q_a[1] <= +q_a[2] <= +q_a[3] <= +q_a[4] <= +q_a[5] <= +q_a[6] <= +q_a[7] <= +q_a[8] <= +q_a[9] <= +q_a[10] <= +q_a[11] <= +q_a[12] <= +q_a[13] <= +q_a[14] <= +q_a[15] <= +q_a[16] <= +q_a[17] <= +q_a[18] <= +q_a[19] <= +q_a[20] <= +q_a[21] <= +q_a[22] <= +q_a[23] <= +q_a[24] <= +q_a[25] <= +q_a[26] <= +q_a[27] <= +q_a[28] <= +q_a[29] <= +q_a[30] <= +q_a[31] <= +q_b[0] <= altsyncram_2jf1:auto_generated.q_b[0] +q_b[1] <= altsyncram_2jf1:auto_generated.q_b[1] +q_b[2] <= altsyncram_2jf1:auto_generated.q_b[2] +q_b[3] <= altsyncram_2jf1:auto_generated.q_b[3] +q_b[4] <= altsyncram_2jf1:auto_generated.q_b[4] +q_b[5] <= altsyncram_2jf1:auto_generated.q_b[5] +q_b[6] <= altsyncram_2jf1:auto_generated.q_b[6] +q_b[7] <= altsyncram_2jf1:auto_generated.q_b[7] +q_b[8] <= altsyncram_2jf1:auto_generated.q_b[8] +q_b[9] <= altsyncram_2jf1:auto_generated.q_b[9] +q_b[10] <= altsyncram_2jf1:auto_generated.q_b[10] +q_b[11] <= altsyncram_2jf1:auto_generated.q_b[11] +q_b[12] <= altsyncram_2jf1:auto_generated.q_b[12] +q_b[13] <= altsyncram_2jf1:auto_generated.q_b[13] +q_b[14] <= altsyncram_2jf1:auto_generated.q_b[14] +q_b[15] <= altsyncram_2jf1:auto_generated.q_b[15] +q_b[16] <= altsyncram_2jf1:auto_generated.q_b[16] +q_b[17] <= altsyncram_2jf1:auto_generated.q_b[17] +q_b[18] <= altsyncram_2jf1:auto_generated.q_b[18] +q_b[19] <= altsyncram_2jf1:auto_generated.q_b[19] +q_b[20] <= altsyncram_2jf1:auto_generated.q_b[20] +q_b[21] <= altsyncram_2jf1:auto_generated.q_b[21] +q_b[22] <= altsyncram_2jf1:auto_generated.q_b[22] +q_b[23] <= altsyncram_2jf1:auto_generated.q_b[23] +q_b[24] <= altsyncram_2jf1:auto_generated.q_b[24] +q_b[25] <= altsyncram_2jf1:auto_generated.q_b[25] +q_b[26] <= altsyncram_2jf1:auto_generated.q_b[26] +q_b[27] <= altsyncram_2jf1:auto_generated.q_b[27] +q_b[28] <= altsyncram_2jf1:auto_generated.q_b[28] +q_b[29] <= altsyncram_2jf1:auto_generated.q_b[29] +q_b[30] <= altsyncram_2jf1:auto_generated.q_b[30] +q_b[31] <= altsyncram_2jf1:auto_generated.q_b[31] +eccstatus[0] <= +eccstatus[1] <= +eccstatus[2] <= + + +|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_dc_data_module:system_cpu_dc_data|altsyncram:the_altsyncram|altsyncram_2jf1:auto_generated +address_a[0] => ram_block1a0.PORTAADDR +address_a[0] => ram_block1a1.PORTAADDR +address_a[0] => ram_block1a2.PORTAADDR +address_a[0] => ram_block1a3.PORTAADDR +address_a[0] => ram_block1a4.PORTAADDR +address_a[0] => ram_block1a5.PORTAADDR +address_a[0] => ram_block1a6.PORTAADDR +address_a[0] => ram_block1a7.PORTAADDR +address_a[0] => ram_block1a8.PORTAADDR +address_a[0] => ram_block1a9.PORTAADDR +address_a[0] => ram_block1a10.PORTAADDR +address_a[0] => ram_block1a11.PORTAADDR +address_a[0] => ram_block1a12.PORTAADDR +address_a[0] => ram_block1a13.PORTAADDR +address_a[0] => ram_block1a14.PORTAADDR +address_a[0] => ram_block1a15.PORTAADDR +address_a[0] => ram_block1a16.PORTAADDR +address_a[0] => ram_block1a17.PORTAADDR +address_a[0] => ram_block1a18.PORTAADDR +address_a[0] => ram_block1a19.PORTAADDR +address_a[0] => ram_block1a20.PORTAADDR +address_a[0] => ram_block1a21.PORTAADDR +address_a[0] => ram_block1a22.PORTAADDR +address_a[0] => ram_block1a23.PORTAADDR +address_a[0] => ram_block1a24.PORTAADDR +address_a[0] => ram_block1a25.PORTAADDR +address_a[0] => ram_block1a26.PORTAADDR +address_a[0] => ram_block1a27.PORTAADDR +address_a[0] => ram_block1a28.PORTAADDR +address_a[0] => ram_block1a29.PORTAADDR +address_a[0] => ram_block1a30.PORTAADDR +address_a[0] => ram_block1a31.PORTAADDR +address_a[1] => ram_block1a0.PORTAADDR1 +address_a[1] => ram_block1a1.PORTAADDR1 +address_a[1] => ram_block1a2.PORTAADDR1 +address_a[1] => ram_block1a3.PORTAADDR1 +address_a[1] => ram_block1a4.PORTAADDR1 +address_a[1] => ram_block1a5.PORTAADDR1 +address_a[1] => ram_block1a6.PORTAADDR1 +address_a[1] => ram_block1a7.PORTAADDR1 +address_a[1] => ram_block1a8.PORTAADDR1 +address_a[1] => ram_block1a9.PORTAADDR1 +address_a[1] => ram_block1a10.PORTAADDR1 +address_a[1] => ram_block1a11.PORTAADDR1 +address_a[1] => ram_block1a12.PORTAADDR1 +address_a[1] => ram_block1a13.PORTAADDR1 +address_a[1] => ram_block1a14.PORTAADDR1 +address_a[1] => ram_block1a15.PORTAADDR1 +address_a[1] => ram_block1a16.PORTAADDR1 +address_a[1] => ram_block1a17.PORTAADDR1 +address_a[1] => ram_block1a18.PORTAADDR1 +address_a[1] => ram_block1a19.PORTAADDR1 +address_a[1] => ram_block1a20.PORTAADDR1 +address_a[1] => ram_block1a21.PORTAADDR1 +address_a[1] => ram_block1a22.PORTAADDR1 +address_a[1] => ram_block1a23.PORTAADDR1 +address_a[1] => ram_block1a24.PORTAADDR1 +address_a[1] => ram_block1a25.PORTAADDR1 +address_a[1] => ram_block1a26.PORTAADDR1 +address_a[1] => ram_block1a27.PORTAADDR1 +address_a[1] => ram_block1a28.PORTAADDR1 +address_a[1] => ram_block1a29.PORTAADDR1 +address_a[1] => ram_block1a30.PORTAADDR1 +address_a[1] => ram_block1a31.PORTAADDR1 +address_a[2] => ram_block1a0.PORTAADDR2 +address_a[2] => ram_block1a1.PORTAADDR2 +address_a[2] => ram_block1a2.PORTAADDR2 +address_a[2] => ram_block1a3.PORTAADDR2 +address_a[2] => ram_block1a4.PORTAADDR2 +address_a[2] => ram_block1a5.PORTAADDR2 +address_a[2] => ram_block1a6.PORTAADDR2 +address_a[2] => ram_block1a7.PORTAADDR2 +address_a[2] => ram_block1a8.PORTAADDR2 +address_a[2] => ram_block1a9.PORTAADDR2 +address_a[2] => ram_block1a10.PORTAADDR2 +address_a[2] => ram_block1a11.PORTAADDR2 +address_a[2] => ram_block1a12.PORTAADDR2 +address_a[2] => ram_block1a13.PORTAADDR2 +address_a[2] => ram_block1a14.PORTAADDR2 +address_a[2] => ram_block1a15.PORTAADDR2 +address_a[2] => ram_block1a16.PORTAADDR2 +address_a[2] => ram_block1a17.PORTAADDR2 +address_a[2] => ram_block1a18.PORTAADDR2 +address_a[2] => ram_block1a19.PORTAADDR2 +address_a[2] => ram_block1a20.PORTAADDR2 +address_a[2] => ram_block1a21.PORTAADDR2 +address_a[2] => ram_block1a22.PORTAADDR2 +address_a[2] => ram_block1a23.PORTAADDR2 +address_a[2] => ram_block1a24.PORTAADDR2 +address_a[2] => ram_block1a25.PORTAADDR2 +address_a[2] => ram_block1a26.PORTAADDR2 +address_a[2] => ram_block1a27.PORTAADDR2 +address_a[2] => ram_block1a28.PORTAADDR2 +address_a[2] => ram_block1a29.PORTAADDR2 +address_a[2] => ram_block1a30.PORTAADDR2 +address_a[2] => ram_block1a31.PORTAADDR2 +address_a[3] => ram_block1a0.PORTAADDR3 +address_a[3] => ram_block1a1.PORTAADDR3 +address_a[3] => ram_block1a2.PORTAADDR3 +address_a[3] => ram_block1a3.PORTAADDR3 +address_a[3] => ram_block1a4.PORTAADDR3 +address_a[3] => ram_block1a5.PORTAADDR3 +address_a[3] => ram_block1a6.PORTAADDR3 +address_a[3] => ram_block1a7.PORTAADDR3 +address_a[3] => ram_block1a8.PORTAADDR3 +address_a[3] => ram_block1a9.PORTAADDR3 +address_a[3] => ram_block1a10.PORTAADDR3 +address_a[3] => ram_block1a11.PORTAADDR3 +address_a[3] => ram_block1a12.PORTAADDR3 +address_a[3] => ram_block1a13.PORTAADDR3 +address_a[3] => ram_block1a14.PORTAADDR3 +address_a[3] => ram_block1a15.PORTAADDR3 +address_a[3] => ram_block1a16.PORTAADDR3 +address_a[3] => ram_block1a17.PORTAADDR3 +address_a[3] => ram_block1a18.PORTAADDR3 +address_a[3] => ram_block1a19.PORTAADDR3 +address_a[3] => ram_block1a20.PORTAADDR3 +address_a[3] => ram_block1a21.PORTAADDR3 +address_a[3] => ram_block1a22.PORTAADDR3 +address_a[3] => ram_block1a23.PORTAADDR3 +address_a[3] => ram_block1a24.PORTAADDR3 +address_a[3] => ram_block1a25.PORTAADDR3 +address_a[3] => ram_block1a26.PORTAADDR3 +address_a[3] => ram_block1a27.PORTAADDR3 +address_a[3] => ram_block1a28.PORTAADDR3 +address_a[3] => ram_block1a29.PORTAADDR3 +address_a[3] => ram_block1a30.PORTAADDR3 +address_a[3] => ram_block1a31.PORTAADDR3 +address_a[4] => ram_block1a0.PORTAADDR4 +address_a[4] => ram_block1a1.PORTAADDR4 +address_a[4] => ram_block1a2.PORTAADDR4 +address_a[4] => ram_block1a3.PORTAADDR4 +address_a[4] => ram_block1a4.PORTAADDR4 +address_a[4] => ram_block1a5.PORTAADDR4 +address_a[4] => ram_block1a6.PORTAADDR4 +address_a[4] => ram_block1a7.PORTAADDR4 +address_a[4] => ram_block1a8.PORTAADDR4 +address_a[4] => ram_block1a9.PORTAADDR4 +address_a[4] => ram_block1a10.PORTAADDR4 +address_a[4] => ram_block1a11.PORTAADDR4 +address_a[4] => ram_block1a12.PORTAADDR4 +address_a[4] => ram_block1a13.PORTAADDR4 +address_a[4] => ram_block1a14.PORTAADDR4 +address_a[4] => ram_block1a15.PORTAADDR4 +address_a[4] => ram_block1a16.PORTAADDR4 +address_a[4] => ram_block1a17.PORTAADDR4 +address_a[4] => ram_block1a18.PORTAADDR4 +address_a[4] => ram_block1a19.PORTAADDR4 +address_a[4] => ram_block1a20.PORTAADDR4 +address_a[4] => ram_block1a21.PORTAADDR4 +address_a[4] => ram_block1a22.PORTAADDR4 +address_a[4] => ram_block1a23.PORTAADDR4 +address_a[4] => ram_block1a24.PORTAADDR4 +address_a[4] => ram_block1a25.PORTAADDR4 +address_a[4] => ram_block1a26.PORTAADDR4 +address_a[4] => ram_block1a27.PORTAADDR4 +address_a[4] => ram_block1a28.PORTAADDR4 +address_a[4] => ram_block1a29.PORTAADDR4 +address_a[4] => ram_block1a30.PORTAADDR4 +address_a[4] => ram_block1a31.PORTAADDR4 +address_a[5] => ram_block1a0.PORTAADDR5 +address_a[5] => ram_block1a1.PORTAADDR5 +address_a[5] => ram_block1a2.PORTAADDR5 +address_a[5] => ram_block1a3.PORTAADDR5 +address_a[5] => ram_block1a4.PORTAADDR5 +address_a[5] => ram_block1a5.PORTAADDR5 +address_a[5] => ram_block1a6.PORTAADDR5 +address_a[5] => ram_block1a7.PORTAADDR5 +address_a[5] => ram_block1a8.PORTAADDR5 +address_a[5] => ram_block1a9.PORTAADDR5 +address_a[5] => ram_block1a10.PORTAADDR5 +address_a[5] => ram_block1a11.PORTAADDR5 +address_a[5] => ram_block1a12.PORTAADDR5 +address_a[5] => ram_block1a13.PORTAADDR5 +address_a[5] => ram_block1a14.PORTAADDR5 +address_a[5] => ram_block1a15.PORTAADDR5 +address_a[5] => ram_block1a16.PORTAADDR5 +address_a[5] => ram_block1a17.PORTAADDR5 +address_a[5] => ram_block1a18.PORTAADDR5 +address_a[5] => ram_block1a19.PORTAADDR5 +address_a[5] => ram_block1a20.PORTAADDR5 +address_a[5] => ram_block1a21.PORTAADDR5 +address_a[5] => ram_block1a22.PORTAADDR5 +address_a[5] => ram_block1a23.PORTAADDR5 +address_a[5] => ram_block1a24.PORTAADDR5 +address_a[5] => ram_block1a25.PORTAADDR5 +address_a[5] => ram_block1a26.PORTAADDR5 +address_a[5] => ram_block1a27.PORTAADDR5 +address_a[5] => ram_block1a28.PORTAADDR5 +address_a[5] => ram_block1a29.PORTAADDR5 +address_a[5] => ram_block1a30.PORTAADDR5 +address_a[5] => ram_block1a31.PORTAADDR5 +address_a[6] => ram_block1a0.PORTAADDR6 +address_a[6] => ram_block1a1.PORTAADDR6 +address_a[6] => ram_block1a2.PORTAADDR6 +address_a[6] => ram_block1a3.PORTAADDR6 +address_a[6] => ram_block1a4.PORTAADDR6 +address_a[6] => ram_block1a5.PORTAADDR6 +address_a[6] => ram_block1a6.PORTAADDR6 +address_a[6] => ram_block1a7.PORTAADDR6 +address_a[6] => ram_block1a8.PORTAADDR6 +address_a[6] => ram_block1a9.PORTAADDR6 +address_a[6] => ram_block1a10.PORTAADDR6 +address_a[6] => ram_block1a11.PORTAADDR6 +address_a[6] => ram_block1a12.PORTAADDR6 +address_a[6] => ram_block1a13.PORTAADDR6 +address_a[6] => ram_block1a14.PORTAADDR6 +address_a[6] => ram_block1a15.PORTAADDR6 +address_a[6] => ram_block1a16.PORTAADDR6 +address_a[6] => ram_block1a17.PORTAADDR6 +address_a[6] => ram_block1a18.PORTAADDR6 +address_a[6] => ram_block1a19.PORTAADDR6 +address_a[6] => ram_block1a20.PORTAADDR6 +address_a[6] => ram_block1a21.PORTAADDR6 +address_a[6] => ram_block1a22.PORTAADDR6 +address_a[6] => ram_block1a23.PORTAADDR6 +address_a[6] => ram_block1a24.PORTAADDR6 +address_a[6] => ram_block1a25.PORTAADDR6 +address_a[6] => ram_block1a26.PORTAADDR6 +address_a[6] => ram_block1a27.PORTAADDR6 +address_a[6] => ram_block1a28.PORTAADDR6 +address_a[6] => ram_block1a29.PORTAADDR6 +address_a[6] => ram_block1a30.PORTAADDR6 +address_a[6] => ram_block1a31.PORTAADDR6 +address_a[7] => ram_block1a0.PORTAADDR7 +address_a[7] => ram_block1a1.PORTAADDR7 +address_a[7] => ram_block1a2.PORTAADDR7 +address_a[7] => ram_block1a3.PORTAADDR7 +address_a[7] => ram_block1a4.PORTAADDR7 +address_a[7] => ram_block1a5.PORTAADDR7 +address_a[7] => ram_block1a6.PORTAADDR7 +address_a[7] => ram_block1a7.PORTAADDR7 +address_a[7] => ram_block1a8.PORTAADDR7 +address_a[7] => ram_block1a9.PORTAADDR7 +address_a[7] => ram_block1a10.PORTAADDR7 +address_a[7] => ram_block1a11.PORTAADDR7 +address_a[7] => ram_block1a12.PORTAADDR7 +address_a[7] => ram_block1a13.PORTAADDR7 +address_a[7] => ram_block1a14.PORTAADDR7 +address_a[7] => ram_block1a15.PORTAADDR7 +address_a[7] => ram_block1a16.PORTAADDR7 +address_a[7] => ram_block1a17.PORTAADDR7 +address_a[7] => ram_block1a18.PORTAADDR7 +address_a[7] => ram_block1a19.PORTAADDR7 +address_a[7] => ram_block1a20.PORTAADDR7 +address_a[7] => ram_block1a21.PORTAADDR7 +address_a[7] => ram_block1a22.PORTAADDR7 +address_a[7] => ram_block1a23.PORTAADDR7 +address_a[7] => ram_block1a24.PORTAADDR7 +address_a[7] => ram_block1a25.PORTAADDR7 +address_a[7] => ram_block1a26.PORTAADDR7 +address_a[7] => ram_block1a27.PORTAADDR7 +address_a[7] => ram_block1a28.PORTAADDR7 +address_a[7] => ram_block1a29.PORTAADDR7 +address_a[7] => ram_block1a30.PORTAADDR7 +address_a[7] => ram_block1a31.PORTAADDR7 +address_a[8] => ram_block1a0.PORTAADDR8 +address_a[8] => ram_block1a1.PORTAADDR8 +address_a[8] => ram_block1a2.PORTAADDR8 +address_a[8] => ram_block1a3.PORTAADDR8 +address_a[8] => ram_block1a4.PORTAADDR8 +address_a[8] => ram_block1a5.PORTAADDR8 +address_a[8] => ram_block1a6.PORTAADDR8 +address_a[8] => ram_block1a7.PORTAADDR8 +address_a[8] => ram_block1a8.PORTAADDR8 +address_a[8] => ram_block1a9.PORTAADDR8 +address_a[8] => ram_block1a10.PORTAADDR8 +address_a[8] => ram_block1a11.PORTAADDR8 +address_a[8] => ram_block1a12.PORTAADDR8 +address_a[8] => ram_block1a13.PORTAADDR8 +address_a[8] => ram_block1a14.PORTAADDR8 +address_a[8] => ram_block1a15.PORTAADDR8 +address_a[8] => ram_block1a16.PORTAADDR8 +address_a[8] => ram_block1a17.PORTAADDR8 +address_a[8] => ram_block1a18.PORTAADDR8 +address_a[8] => ram_block1a19.PORTAADDR8 +address_a[8] => ram_block1a20.PORTAADDR8 +address_a[8] => ram_block1a21.PORTAADDR8 +address_a[8] => ram_block1a22.PORTAADDR8 +address_a[8] => ram_block1a23.PORTAADDR8 +address_a[8] => ram_block1a24.PORTAADDR8 +address_a[8] => ram_block1a25.PORTAADDR8 +address_a[8] => ram_block1a26.PORTAADDR8 +address_a[8] => ram_block1a27.PORTAADDR8 +address_a[8] => ram_block1a28.PORTAADDR8 +address_a[8] => ram_block1a29.PORTAADDR8 +address_a[8] => ram_block1a30.PORTAADDR8 +address_a[8] => ram_block1a31.PORTAADDR8 +address_a[9] => ram_block1a0.PORTAADDR9 +address_a[9] => ram_block1a1.PORTAADDR9 +address_a[9] => ram_block1a2.PORTAADDR9 +address_a[9] => ram_block1a3.PORTAADDR9 +address_a[9] => ram_block1a4.PORTAADDR9 +address_a[9] => ram_block1a5.PORTAADDR9 +address_a[9] => ram_block1a6.PORTAADDR9 +address_a[9] => ram_block1a7.PORTAADDR9 +address_a[9] => ram_block1a8.PORTAADDR9 +address_a[9] => ram_block1a9.PORTAADDR9 +address_a[9] => ram_block1a10.PORTAADDR9 +address_a[9] => ram_block1a11.PORTAADDR9 +address_a[9] => ram_block1a12.PORTAADDR9 +address_a[9] => ram_block1a13.PORTAADDR9 +address_a[9] => ram_block1a14.PORTAADDR9 +address_a[9] => ram_block1a15.PORTAADDR9 +address_a[9] => ram_block1a16.PORTAADDR9 +address_a[9] => ram_block1a17.PORTAADDR9 +address_a[9] => ram_block1a18.PORTAADDR9 +address_a[9] => ram_block1a19.PORTAADDR9 +address_a[9] => ram_block1a20.PORTAADDR9 +address_a[9] => ram_block1a21.PORTAADDR9 +address_a[9] => ram_block1a22.PORTAADDR9 +address_a[9] => ram_block1a23.PORTAADDR9 +address_a[9] => ram_block1a24.PORTAADDR9 +address_a[9] => ram_block1a25.PORTAADDR9 +address_a[9] => ram_block1a26.PORTAADDR9 +address_a[9] => ram_block1a27.PORTAADDR9 +address_a[9] => ram_block1a28.PORTAADDR9 +address_a[9] => ram_block1a29.PORTAADDR9 +address_a[9] => ram_block1a30.PORTAADDR9 +address_a[9] => ram_block1a31.PORTAADDR9 +address_b[0] => ram_block1a0.PORTBADDR +address_b[0] => ram_block1a1.PORTBADDR +address_b[0] => ram_block1a2.PORTBADDR +address_b[0] => ram_block1a3.PORTBADDR +address_b[0] => ram_block1a4.PORTBADDR +address_b[0] => ram_block1a5.PORTBADDR +address_b[0] => ram_block1a6.PORTBADDR +address_b[0] => ram_block1a7.PORTBADDR +address_b[0] => ram_block1a8.PORTBADDR +address_b[0] => ram_block1a9.PORTBADDR +address_b[0] => ram_block1a10.PORTBADDR +address_b[0] => ram_block1a11.PORTBADDR +address_b[0] => ram_block1a12.PORTBADDR +address_b[0] => ram_block1a13.PORTBADDR +address_b[0] => ram_block1a14.PORTBADDR +address_b[0] => ram_block1a15.PORTBADDR +address_b[0] => ram_block1a16.PORTBADDR +address_b[0] => ram_block1a17.PORTBADDR +address_b[0] => ram_block1a18.PORTBADDR +address_b[0] => ram_block1a19.PORTBADDR +address_b[0] => ram_block1a20.PORTBADDR +address_b[0] => ram_block1a21.PORTBADDR +address_b[0] => ram_block1a22.PORTBADDR +address_b[0] => ram_block1a23.PORTBADDR +address_b[0] => ram_block1a24.PORTBADDR +address_b[0] => ram_block1a25.PORTBADDR +address_b[0] => ram_block1a26.PORTBADDR +address_b[0] => ram_block1a27.PORTBADDR +address_b[0] => ram_block1a28.PORTBADDR +address_b[0] => ram_block1a29.PORTBADDR +address_b[0] => ram_block1a30.PORTBADDR +address_b[0] => ram_block1a31.PORTBADDR +address_b[1] => ram_block1a0.PORTBADDR1 +address_b[1] => ram_block1a1.PORTBADDR1 +address_b[1] => ram_block1a2.PORTBADDR1 +address_b[1] => ram_block1a3.PORTBADDR1 +address_b[1] => ram_block1a4.PORTBADDR1 +address_b[1] => ram_block1a5.PORTBADDR1 +address_b[1] => ram_block1a6.PORTBADDR1 +address_b[1] => ram_block1a7.PORTBADDR1 +address_b[1] => ram_block1a8.PORTBADDR1 +address_b[1] => ram_block1a9.PORTBADDR1 +address_b[1] => ram_block1a10.PORTBADDR1 +address_b[1] => ram_block1a11.PORTBADDR1 +address_b[1] => ram_block1a12.PORTBADDR1 +address_b[1] => ram_block1a13.PORTBADDR1 +address_b[1] => ram_block1a14.PORTBADDR1 +address_b[1] => ram_block1a15.PORTBADDR1 +address_b[1] => ram_block1a16.PORTBADDR1 +address_b[1] => ram_block1a17.PORTBADDR1 +address_b[1] => ram_block1a18.PORTBADDR1 +address_b[1] => ram_block1a19.PORTBADDR1 +address_b[1] => ram_block1a20.PORTBADDR1 +address_b[1] => ram_block1a21.PORTBADDR1 +address_b[1] => ram_block1a22.PORTBADDR1 +address_b[1] => ram_block1a23.PORTBADDR1 +address_b[1] => ram_block1a24.PORTBADDR1 +address_b[1] => ram_block1a25.PORTBADDR1 +address_b[1] => ram_block1a26.PORTBADDR1 +address_b[1] => ram_block1a27.PORTBADDR1 +address_b[1] => ram_block1a28.PORTBADDR1 +address_b[1] => ram_block1a29.PORTBADDR1 +address_b[1] => ram_block1a30.PORTBADDR1 +address_b[1] => ram_block1a31.PORTBADDR1 +address_b[2] => ram_block1a0.PORTBADDR2 +address_b[2] => ram_block1a1.PORTBADDR2 +address_b[2] => ram_block1a2.PORTBADDR2 +address_b[2] => ram_block1a3.PORTBADDR2 +address_b[2] => ram_block1a4.PORTBADDR2 +address_b[2] => ram_block1a5.PORTBADDR2 +address_b[2] => ram_block1a6.PORTBADDR2 +address_b[2] => ram_block1a7.PORTBADDR2 +address_b[2] => ram_block1a8.PORTBADDR2 +address_b[2] => ram_block1a9.PORTBADDR2 +address_b[2] => ram_block1a10.PORTBADDR2 +address_b[2] => ram_block1a11.PORTBADDR2 +address_b[2] => ram_block1a12.PORTBADDR2 +address_b[2] => ram_block1a13.PORTBADDR2 +address_b[2] => ram_block1a14.PORTBADDR2 +address_b[2] => ram_block1a15.PORTBADDR2 +address_b[2] => ram_block1a16.PORTBADDR2 +address_b[2] => ram_block1a17.PORTBADDR2 +address_b[2] => ram_block1a18.PORTBADDR2 +address_b[2] => ram_block1a19.PORTBADDR2 +address_b[2] => ram_block1a20.PORTBADDR2 +address_b[2] => ram_block1a21.PORTBADDR2 +address_b[2] => ram_block1a22.PORTBADDR2 +address_b[2] => ram_block1a23.PORTBADDR2 +address_b[2] => ram_block1a24.PORTBADDR2 +address_b[2] => ram_block1a25.PORTBADDR2 +address_b[2] => ram_block1a26.PORTBADDR2 +address_b[2] => ram_block1a27.PORTBADDR2 +address_b[2] => ram_block1a28.PORTBADDR2 +address_b[2] => ram_block1a29.PORTBADDR2 +address_b[2] => ram_block1a30.PORTBADDR2 +address_b[2] => ram_block1a31.PORTBADDR2 +address_b[3] => ram_block1a0.PORTBADDR3 +address_b[3] => ram_block1a1.PORTBADDR3 +address_b[3] => ram_block1a2.PORTBADDR3 +address_b[3] => ram_block1a3.PORTBADDR3 +address_b[3] => ram_block1a4.PORTBADDR3 +address_b[3] => ram_block1a5.PORTBADDR3 +address_b[3] => ram_block1a6.PORTBADDR3 +address_b[3] => ram_block1a7.PORTBADDR3 +address_b[3] => ram_block1a8.PORTBADDR3 +address_b[3] => ram_block1a9.PORTBADDR3 +address_b[3] => ram_block1a10.PORTBADDR3 +address_b[3] => ram_block1a11.PORTBADDR3 +address_b[3] => ram_block1a12.PORTBADDR3 +address_b[3] => ram_block1a13.PORTBADDR3 +address_b[3] => ram_block1a14.PORTBADDR3 +address_b[3] => ram_block1a15.PORTBADDR3 +address_b[3] => ram_block1a16.PORTBADDR3 +address_b[3] => ram_block1a17.PORTBADDR3 +address_b[3] => ram_block1a18.PORTBADDR3 +address_b[3] => ram_block1a19.PORTBADDR3 +address_b[3] => ram_block1a20.PORTBADDR3 +address_b[3] => ram_block1a21.PORTBADDR3 +address_b[3] => ram_block1a22.PORTBADDR3 +address_b[3] => ram_block1a23.PORTBADDR3 +address_b[3] => ram_block1a24.PORTBADDR3 +address_b[3] => ram_block1a25.PORTBADDR3 +address_b[3] => ram_block1a26.PORTBADDR3 +address_b[3] => ram_block1a27.PORTBADDR3 +address_b[3] => ram_block1a28.PORTBADDR3 +address_b[3] => ram_block1a29.PORTBADDR3 +address_b[3] => ram_block1a30.PORTBADDR3 +address_b[3] => ram_block1a31.PORTBADDR3 +address_b[4] => ram_block1a0.PORTBADDR4 +address_b[4] => ram_block1a1.PORTBADDR4 +address_b[4] => ram_block1a2.PORTBADDR4 +address_b[4] => ram_block1a3.PORTBADDR4 +address_b[4] => ram_block1a4.PORTBADDR4 +address_b[4] => ram_block1a5.PORTBADDR4 +address_b[4] => ram_block1a6.PORTBADDR4 +address_b[4] => ram_block1a7.PORTBADDR4 +address_b[4] => ram_block1a8.PORTBADDR4 +address_b[4] => ram_block1a9.PORTBADDR4 +address_b[4] => ram_block1a10.PORTBADDR4 +address_b[4] => ram_block1a11.PORTBADDR4 +address_b[4] => ram_block1a12.PORTBADDR4 +address_b[4] => ram_block1a13.PORTBADDR4 +address_b[4] => ram_block1a14.PORTBADDR4 +address_b[4] => ram_block1a15.PORTBADDR4 +address_b[4] => ram_block1a16.PORTBADDR4 +address_b[4] => ram_block1a17.PORTBADDR4 +address_b[4] => ram_block1a18.PORTBADDR4 +address_b[4] => ram_block1a19.PORTBADDR4 +address_b[4] => ram_block1a20.PORTBADDR4 +address_b[4] => ram_block1a21.PORTBADDR4 +address_b[4] => ram_block1a22.PORTBADDR4 +address_b[4] => ram_block1a23.PORTBADDR4 +address_b[4] => ram_block1a24.PORTBADDR4 +address_b[4] => ram_block1a25.PORTBADDR4 +address_b[4] => ram_block1a26.PORTBADDR4 +address_b[4] => ram_block1a27.PORTBADDR4 +address_b[4] => ram_block1a28.PORTBADDR4 +address_b[4] => ram_block1a29.PORTBADDR4 +address_b[4] => ram_block1a30.PORTBADDR4 +address_b[4] => ram_block1a31.PORTBADDR4 +address_b[5] => ram_block1a0.PORTBADDR5 +address_b[5] => ram_block1a1.PORTBADDR5 +address_b[5] => ram_block1a2.PORTBADDR5 +address_b[5] => ram_block1a3.PORTBADDR5 +address_b[5] => ram_block1a4.PORTBADDR5 +address_b[5] => ram_block1a5.PORTBADDR5 +address_b[5] => ram_block1a6.PORTBADDR5 +address_b[5] => ram_block1a7.PORTBADDR5 +address_b[5] => ram_block1a8.PORTBADDR5 +address_b[5] => ram_block1a9.PORTBADDR5 +address_b[5] => ram_block1a10.PORTBADDR5 +address_b[5] => ram_block1a11.PORTBADDR5 +address_b[5] => ram_block1a12.PORTBADDR5 +address_b[5] => ram_block1a13.PORTBADDR5 +address_b[5] => ram_block1a14.PORTBADDR5 +address_b[5] => ram_block1a15.PORTBADDR5 +address_b[5] => ram_block1a16.PORTBADDR5 +address_b[5] => ram_block1a17.PORTBADDR5 +address_b[5] => ram_block1a18.PORTBADDR5 +address_b[5] => ram_block1a19.PORTBADDR5 +address_b[5] => ram_block1a20.PORTBADDR5 +address_b[5] => ram_block1a21.PORTBADDR5 +address_b[5] => ram_block1a22.PORTBADDR5 +address_b[5] => ram_block1a23.PORTBADDR5 +address_b[5] => ram_block1a24.PORTBADDR5 +address_b[5] => ram_block1a25.PORTBADDR5 +address_b[5] => ram_block1a26.PORTBADDR5 +address_b[5] => ram_block1a27.PORTBADDR5 +address_b[5] => ram_block1a28.PORTBADDR5 +address_b[5] => ram_block1a29.PORTBADDR5 +address_b[5] => ram_block1a30.PORTBADDR5 +address_b[5] => ram_block1a31.PORTBADDR5 +address_b[6] => ram_block1a0.PORTBADDR6 +address_b[6] => ram_block1a1.PORTBADDR6 +address_b[6] => ram_block1a2.PORTBADDR6 +address_b[6] => ram_block1a3.PORTBADDR6 +address_b[6] => ram_block1a4.PORTBADDR6 +address_b[6] => ram_block1a5.PORTBADDR6 +address_b[6] => ram_block1a6.PORTBADDR6 +address_b[6] => ram_block1a7.PORTBADDR6 +address_b[6] => ram_block1a8.PORTBADDR6 +address_b[6] => ram_block1a9.PORTBADDR6 +address_b[6] => ram_block1a10.PORTBADDR6 +address_b[6] => ram_block1a11.PORTBADDR6 +address_b[6] => ram_block1a12.PORTBADDR6 +address_b[6] => ram_block1a13.PORTBADDR6 +address_b[6] => ram_block1a14.PORTBADDR6 +address_b[6] => ram_block1a15.PORTBADDR6 +address_b[6] => ram_block1a16.PORTBADDR6 +address_b[6] => ram_block1a17.PORTBADDR6 +address_b[6] => ram_block1a18.PORTBADDR6 +address_b[6] => ram_block1a19.PORTBADDR6 +address_b[6] => ram_block1a20.PORTBADDR6 +address_b[6] => ram_block1a21.PORTBADDR6 +address_b[6] => ram_block1a22.PORTBADDR6 +address_b[6] => ram_block1a23.PORTBADDR6 +address_b[6] => ram_block1a24.PORTBADDR6 +address_b[6] => ram_block1a25.PORTBADDR6 +address_b[6] => ram_block1a26.PORTBADDR6 +address_b[6] => ram_block1a27.PORTBADDR6 +address_b[6] => ram_block1a28.PORTBADDR6 +address_b[6] => ram_block1a29.PORTBADDR6 +address_b[6] => ram_block1a30.PORTBADDR6 +address_b[6] => ram_block1a31.PORTBADDR6 +address_b[7] => ram_block1a0.PORTBADDR7 +address_b[7] => ram_block1a1.PORTBADDR7 +address_b[7] => ram_block1a2.PORTBADDR7 +address_b[7] => ram_block1a3.PORTBADDR7 +address_b[7] => ram_block1a4.PORTBADDR7 +address_b[7] => ram_block1a5.PORTBADDR7 +address_b[7] => ram_block1a6.PORTBADDR7 +address_b[7] => ram_block1a7.PORTBADDR7 +address_b[7] => ram_block1a8.PORTBADDR7 +address_b[7] => ram_block1a9.PORTBADDR7 +address_b[7] => ram_block1a10.PORTBADDR7 +address_b[7] => ram_block1a11.PORTBADDR7 +address_b[7] => ram_block1a12.PORTBADDR7 +address_b[7] => ram_block1a13.PORTBADDR7 +address_b[7] => ram_block1a14.PORTBADDR7 +address_b[7] => ram_block1a15.PORTBADDR7 +address_b[7] => ram_block1a16.PORTBADDR7 +address_b[7] => ram_block1a17.PORTBADDR7 +address_b[7] => ram_block1a18.PORTBADDR7 +address_b[7] => ram_block1a19.PORTBADDR7 +address_b[7] => ram_block1a20.PORTBADDR7 +address_b[7] => ram_block1a21.PORTBADDR7 +address_b[7] => ram_block1a22.PORTBADDR7 +address_b[7] => ram_block1a23.PORTBADDR7 +address_b[7] => ram_block1a24.PORTBADDR7 +address_b[7] => ram_block1a25.PORTBADDR7 +address_b[7] => ram_block1a26.PORTBADDR7 +address_b[7] => ram_block1a27.PORTBADDR7 +address_b[7] => ram_block1a28.PORTBADDR7 +address_b[7] => ram_block1a29.PORTBADDR7 +address_b[7] => ram_block1a30.PORTBADDR7 +address_b[7] => ram_block1a31.PORTBADDR7 +address_b[8] => ram_block1a0.PORTBADDR8 +address_b[8] => ram_block1a1.PORTBADDR8 +address_b[8] => ram_block1a2.PORTBADDR8 +address_b[8] => ram_block1a3.PORTBADDR8 +address_b[8] => ram_block1a4.PORTBADDR8 +address_b[8] => ram_block1a5.PORTBADDR8 +address_b[8] => ram_block1a6.PORTBADDR8 +address_b[8] => ram_block1a7.PORTBADDR8 +address_b[8] => ram_block1a8.PORTBADDR8 +address_b[8] => ram_block1a9.PORTBADDR8 +address_b[8] => ram_block1a10.PORTBADDR8 +address_b[8] => ram_block1a11.PORTBADDR8 +address_b[8] => ram_block1a12.PORTBADDR8 +address_b[8] => ram_block1a13.PORTBADDR8 +address_b[8] => ram_block1a14.PORTBADDR8 +address_b[8] => ram_block1a15.PORTBADDR8 +address_b[8] => ram_block1a16.PORTBADDR8 +address_b[8] => ram_block1a17.PORTBADDR8 +address_b[8] => ram_block1a18.PORTBADDR8 +address_b[8] => ram_block1a19.PORTBADDR8 +address_b[8] => ram_block1a20.PORTBADDR8 +address_b[8] => ram_block1a21.PORTBADDR8 +address_b[8] => ram_block1a22.PORTBADDR8 +address_b[8] => ram_block1a23.PORTBADDR8 +address_b[8] => ram_block1a24.PORTBADDR8 +address_b[8] => ram_block1a25.PORTBADDR8 +address_b[8] => ram_block1a26.PORTBADDR8 +address_b[8] => ram_block1a27.PORTBADDR8 +address_b[8] => ram_block1a28.PORTBADDR8 +address_b[8] => ram_block1a29.PORTBADDR8 +address_b[8] => ram_block1a30.PORTBADDR8 +address_b[8] => ram_block1a31.PORTBADDR8 +address_b[9] => ram_block1a0.PORTBADDR9 +address_b[9] => ram_block1a1.PORTBADDR9 +address_b[9] => ram_block1a2.PORTBADDR9 +address_b[9] => ram_block1a3.PORTBADDR9 +address_b[9] => ram_block1a4.PORTBADDR9 +address_b[9] => ram_block1a5.PORTBADDR9 +address_b[9] => ram_block1a6.PORTBADDR9 +address_b[9] => ram_block1a7.PORTBADDR9 +address_b[9] => ram_block1a8.PORTBADDR9 +address_b[9] => ram_block1a9.PORTBADDR9 +address_b[9] => ram_block1a10.PORTBADDR9 +address_b[9] => ram_block1a11.PORTBADDR9 +address_b[9] => ram_block1a12.PORTBADDR9 +address_b[9] => ram_block1a13.PORTBADDR9 +address_b[9] => ram_block1a14.PORTBADDR9 +address_b[9] => ram_block1a15.PORTBADDR9 +address_b[9] => ram_block1a16.PORTBADDR9 +address_b[9] => ram_block1a17.PORTBADDR9 +address_b[9] => ram_block1a18.PORTBADDR9 +address_b[9] => ram_block1a19.PORTBADDR9 +address_b[9] => ram_block1a20.PORTBADDR9 +address_b[9] => ram_block1a21.PORTBADDR9 +address_b[9] => ram_block1a22.PORTBADDR9 +address_b[9] => ram_block1a23.PORTBADDR9 +address_b[9] => ram_block1a24.PORTBADDR9 +address_b[9] => ram_block1a25.PORTBADDR9 +address_b[9] => ram_block1a26.PORTBADDR9 +address_b[9] => ram_block1a27.PORTBADDR9 +address_b[9] => ram_block1a28.PORTBADDR9 +address_b[9] => ram_block1a29.PORTBADDR9 +address_b[9] => ram_block1a30.PORTBADDR9 +address_b[9] => ram_block1a31.PORTBADDR9 +byteena_a[0] => ram_block1a0.PORTABYTEENAMASKS +byteena_a[0] => ram_block1a1.PORTABYTEENAMASKS +byteena_a[0] => ram_block1a2.PORTABYTEENAMASKS +byteena_a[0] => ram_block1a3.PORTABYTEENAMASKS +byteena_a[0] => ram_block1a4.PORTABYTEENAMASKS +byteena_a[0] => ram_block1a5.PORTABYTEENAMASKS +byteena_a[0] => ram_block1a6.PORTABYTEENAMASKS +byteena_a[0] => ram_block1a7.PORTABYTEENAMASKS +byteena_a[1] => ram_block1a8.PORTABYTEENAMASKS +byteena_a[1] => ram_block1a9.PORTABYTEENAMASKS +byteena_a[1] => ram_block1a10.PORTABYTEENAMASKS +byteena_a[1] => ram_block1a11.PORTABYTEENAMASKS +byteena_a[1] => ram_block1a12.PORTABYTEENAMASKS +byteena_a[1] => ram_block1a13.PORTABYTEENAMASKS +byteena_a[1] => ram_block1a14.PORTABYTEENAMASKS +byteena_a[1] => ram_block1a15.PORTABYTEENAMASKS +byteena_a[2] => ram_block1a16.PORTABYTEENAMASKS +byteena_a[2] => ram_block1a17.PORTABYTEENAMASKS +byteena_a[2] => ram_block1a18.PORTABYTEENAMASKS +byteena_a[2] => ram_block1a19.PORTABYTEENAMASKS +byteena_a[2] => ram_block1a20.PORTABYTEENAMASKS +byteena_a[2] => ram_block1a21.PORTABYTEENAMASKS +byteena_a[2] => ram_block1a22.PORTABYTEENAMASKS +byteena_a[2] => ram_block1a23.PORTABYTEENAMASKS +byteena_a[3] => ram_block1a24.PORTABYTEENAMASKS +byteena_a[3] => ram_block1a25.PORTABYTEENAMASKS +byteena_a[3] => ram_block1a26.PORTABYTEENAMASKS +byteena_a[3] => ram_block1a27.PORTABYTEENAMASKS +byteena_a[3] => ram_block1a28.PORTABYTEENAMASKS +byteena_a[3] => ram_block1a29.PORTABYTEENAMASKS +byteena_a[3] => ram_block1a30.PORTABYTEENAMASKS +byteena_a[3] => ram_block1a31.PORTABYTEENAMASKS +clock0 => ram_block1a0.CLK0 +clock0 => ram_block1a0.CLK1 +clock0 => ram_block1a1.CLK0 +clock0 => ram_block1a1.CLK1 +clock0 => ram_block1a2.CLK0 +clock0 => ram_block1a2.CLK1 +clock0 => ram_block1a3.CLK0 +clock0 => ram_block1a3.CLK1 +clock0 => ram_block1a4.CLK0 +clock0 => ram_block1a4.CLK1 +clock0 => ram_block1a5.CLK0 +clock0 => ram_block1a5.CLK1 +clock0 => ram_block1a6.CLK0 +clock0 => ram_block1a6.CLK1 +clock0 => ram_block1a7.CLK0 +clock0 => ram_block1a7.CLK1 +clock0 => ram_block1a8.CLK0 +clock0 => ram_block1a8.CLK1 +clock0 => ram_block1a9.CLK0 +clock0 => ram_block1a9.CLK1 +clock0 => ram_block1a10.CLK0 +clock0 => ram_block1a10.CLK1 +clock0 => ram_block1a11.CLK0 +clock0 => ram_block1a11.CLK1 +clock0 => ram_block1a12.CLK0 +clock0 => ram_block1a12.CLK1 +clock0 => ram_block1a13.CLK0 +clock0 => ram_block1a13.CLK1 +clock0 => ram_block1a14.CLK0 +clock0 => ram_block1a14.CLK1 +clock0 => ram_block1a15.CLK0 +clock0 => ram_block1a15.CLK1 +clock0 => ram_block1a16.CLK0 +clock0 => ram_block1a16.CLK1 +clock0 => ram_block1a17.CLK0 +clock0 => ram_block1a17.CLK1 +clock0 => ram_block1a18.CLK0 +clock0 => ram_block1a18.CLK1 +clock0 => ram_block1a19.CLK0 +clock0 => ram_block1a19.CLK1 +clock0 => ram_block1a20.CLK0 +clock0 => ram_block1a20.CLK1 +clock0 => ram_block1a21.CLK0 +clock0 => ram_block1a21.CLK1 +clock0 => ram_block1a22.CLK0 +clock0 => ram_block1a22.CLK1 +clock0 => ram_block1a23.CLK0 +clock0 => ram_block1a23.CLK1 +clock0 => ram_block1a24.CLK0 +clock0 => ram_block1a24.CLK1 +clock0 => ram_block1a25.CLK0 +clock0 => ram_block1a25.CLK1 +clock0 => ram_block1a26.CLK0 +clock0 => ram_block1a26.CLK1 +clock0 => ram_block1a27.CLK0 +clock0 => ram_block1a27.CLK1 +clock0 => ram_block1a28.CLK0 +clock0 => ram_block1a28.CLK1 +clock0 => ram_block1a29.CLK0 +clock0 => ram_block1a29.CLK1 +clock0 => ram_block1a30.CLK0 +clock0 => ram_block1a30.CLK1 +clock0 => ram_block1a31.CLK0 +clock0 => ram_block1a31.CLK1 +data_a[0] => ram_block1a0.PORTADATAIN +data_a[1] => ram_block1a1.PORTADATAIN +data_a[2] => ram_block1a2.PORTADATAIN +data_a[3] => ram_block1a3.PORTADATAIN +data_a[4] => ram_block1a4.PORTADATAIN +data_a[5] => ram_block1a5.PORTADATAIN +data_a[6] => ram_block1a6.PORTADATAIN +data_a[7] => ram_block1a7.PORTADATAIN +data_a[8] => ram_block1a8.PORTADATAIN +data_a[9] => ram_block1a9.PORTADATAIN +data_a[10] => ram_block1a10.PORTADATAIN +data_a[11] => ram_block1a11.PORTADATAIN +data_a[12] => ram_block1a12.PORTADATAIN +data_a[13] => ram_block1a13.PORTADATAIN +data_a[14] => ram_block1a14.PORTADATAIN +data_a[15] => ram_block1a15.PORTADATAIN +data_a[16] => ram_block1a16.PORTADATAIN +data_a[17] => ram_block1a17.PORTADATAIN +data_a[18] => ram_block1a18.PORTADATAIN +data_a[19] => ram_block1a19.PORTADATAIN +data_a[20] => ram_block1a20.PORTADATAIN +data_a[21] => ram_block1a21.PORTADATAIN +data_a[22] => ram_block1a22.PORTADATAIN +data_a[23] => ram_block1a23.PORTADATAIN +data_a[24] => ram_block1a24.PORTADATAIN +data_a[25] => ram_block1a25.PORTADATAIN +data_a[26] => ram_block1a26.PORTADATAIN +data_a[27] => ram_block1a27.PORTADATAIN +data_a[28] => ram_block1a28.PORTADATAIN +data_a[29] => ram_block1a29.PORTADATAIN +data_a[30] => ram_block1a30.PORTADATAIN +data_a[31] => ram_block1a31.PORTADATAIN +q_b[0] <= ram_block1a0.PORTBDATAOUT +q_b[1] <= ram_block1a1.PORTBDATAOUT +q_b[2] <= ram_block1a2.PORTBDATAOUT +q_b[3] <= ram_block1a3.PORTBDATAOUT +q_b[4] <= ram_block1a4.PORTBDATAOUT +q_b[5] <= ram_block1a5.PORTBDATAOUT +q_b[6] <= ram_block1a6.PORTBDATAOUT +q_b[7] <= ram_block1a7.PORTBDATAOUT +q_b[8] <= ram_block1a8.PORTBDATAOUT +q_b[9] <= ram_block1a9.PORTBDATAOUT +q_b[10] <= ram_block1a10.PORTBDATAOUT +q_b[11] <= ram_block1a11.PORTBDATAOUT +q_b[12] <= ram_block1a12.PORTBDATAOUT +q_b[13] <= ram_block1a13.PORTBDATAOUT +q_b[14] <= ram_block1a14.PORTBDATAOUT +q_b[15] <= ram_block1a15.PORTBDATAOUT +q_b[16] <= ram_block1a16.PORTBDATAOUT +q_b[17] <= ram_block1a17.PORTBDATAOUT +q_b[18] <= ram_block1a18.PORTBDATAOUT +q_b[19] <= ram_block1a19.PORTBDATAOUT +q_b[20] <= ram_block1a20.PORTBDATAOUT +q_b[21] <= ram_block1a21.PORTBDATAOUT +q_b[22] <= ram_block1a22.PORTBDATAOUT +q_b[23] <= ram_block1a23.PORTBDATAOUT +q_b[24] <= ram_block1a24.PORTBDATAOUT +q_b[25] <= ram_block1a25.PORTBDATAOUT +q_b[26] <= ram_block1a26.PORTBDATAOUT +q_b[27] <= ram_block1a27.PORTBDATAOUT +q_b[28] <= ram_block1a28.PORTBDATAOUT +q_b[29] <= ram_block1a29.PORTBDATAOUT +q_b[30] <= ram_block1a30.PORTBDATAOUT +q_b[31] <= ram_block1a31.PORTBDATAOUT +wren_a => ram_block1a0.PORTAWE +wren_a => ram_block1a0.ENA0 +wren_a => ram_block1a1.PORTAWE +wren_a => ram_block1a1.ENA0 +wren_a => ram_block1a2.PORTAWE +wren_a => ram_block1a2.ENA0 +wren_a => ram_block1a3.PORTAWE +wren_a => ram_block1a3.ENA0 +wren_a => ram_block1a4.PORTAWE +wren_a => ram_block1a4.ENA0 +wren_a => ram_block1a5.PORTAWE +wren_a => ram_block1a5.ENA0 +wren_a => ram_block1a6.PORTAWE +wren_a => ram_block1a6.ENA0 +wren_a => ram_block1a7.PORTAWE +wren_a => ram_block1a7.ENA0 +wren_a => ram_block1a8.PORTAWE +wren_a => ram_block1a8.ENA0 +wren_a => ram_block1a9.PORTAWE +wren_a => ram_block1a9.ENA0 +wren_a => ram_block1a10.PORTAWE +wren_a => ram_block1a10.ENA0 +wren_a => ram_block1a11.PORTAWE +wren_a => ram_block1a11.ENA0 +wren_a => ram_block1a12.PORTAWE +wren_a => ram_block1a12.ENA0 +wren_a => ram_block1a13.PORTAWE +wren_a => ram_block1a13.ENA0 +wren_a => ram_block1a14.PORTAWE +wren_a => ram_block1a14.ENA0 +wren_a => ram_block1a15.PORTAWE +wren_a => ram_block1a15.ENA0 +wren_a => ram_block1a16.PORTAWE +wren_a => ram_block1a16.ENA0 +wren_a => ram_block1a17.PORTAWE +wren_a => ram_block1a17.ENA0 +wren_a => ram_block1a18.PORTAWE +wren_a => ram_block1a18.ENA0 +wren_a => ram_block1a19.PORTAWE +wren_a => ram_block1a19.ENA0 +wren_a => ram_block1a20.PORTAWE +wren_a => ram_block1a20.ENA0 +wren_a => ram_block1a21.PORTAWE +wren_a => ram_block1a21.ENA0 +wren_a => ram_block1a22.PORTAWE +wren_a => ram_block1a22.ENA0 +wren_a => ram_block1a23.PORTAWE +wren_a => ram_block1a23.ENA0 +wren_a => ram_block1a24.PORTAWE +wren_a => ram_block1a24.ENA0 +wren_a => ram_block1a25.PORTAWE +wren_a => ram_block1a25.ENA0 +wren_a => ram_block1a26.PORTAWE +wren_a => ram_block1a26.ENA0 +wren_a => ram_block1a27.PORTAWE +wren_a => ram_block1a27.ENA0 +wren_a => ram_block1a28.PORTAWE +wren_a => ram_block1a28.ENA0 +wren_a => ram_block1a29.PORTAWE +wren_a => ram_block1a29.ENA0 +wren_a => ram_block1a30.PORTAWE +wren_a => ram_block1a30.ENA0 +wren_a => ram_block1a31.PORTAWE +wren_a => ram_block1a31.ENA0 + + +|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_dc_victim_module:system_cpu_dc_victim +clock => clock.IN1 +data[0] => data[0].IN1 +data[1] => data[1].IN1 +data[2] => data[2].IN1 +data[3] => data[3].IN1 +data[4] => data[4].IN1 +data[5] => data[5].IN1 +data[6] => data[6].IN1 +data[7] => data[7].IN1 +data[8] => data[8].IN1 +data[9] => data[9].IN1 +data[10] => data[10].IN1 +data[11] => data[11].IN1 +data[12] => data[12].IN1 +data[13] => data[13].IN1 +data[14] => data[14].IN1 +data[15] => data[15].IN1 +data[16] => data[16].IN1 +data[17] => data[17].IN1 +data[18] => data[18].IN1 +data[19] => data[19].IN1 +data[20] => data[20].IN1 +data[21] => data[21].IN1 +data[22] => data[22].IN1 +data[23] => data[23].IN1 +data[24] => data[24].IN1 +data[25] => data[25].IN1 +data[26] => data[26].IN1 +data[27] => data[27].IN1 +data[28] => data[28].IN1 +data[29] => data[29].IN1 +data[30] => data[30].IN1 +data[31] => data[31].IN1 +rdaddress[0] => rdaddress[0].IN1 +rdaddress[1] => rdaddress[1].IN1 +rdaddress[2] => rdaddress[2].IN1 +rden => rden.IN1 +wraddress[0] => wraddress[0].IN1 +wraddress[1] => wraddress[1].IN1 +wraddress[2] => wraddress[2].IN1 +wren => wren.IN1 +q[0] <= altsyncram:the_altsyncram.q_b +q[1] <= altsyncram:the_altsyncram.q_b +q[2] <= altsyncram:the_altsyncram.q_b +q[3] <= altsyncram:the_altsyncram.q_b +q[4] <= altsyncram:the_altsyncram.q_b +q[5] <= altsyncram:the_altsyncram.q_b +q[6] <= altsyncram:the_altsyncram.q_b +q[7] <= altsyncram:the_altsyncram.q_b +q[8] <= altsyncram:the_altsyncram.q_b +q[9] <= altsyncram:the_altsyncram.q_b +q[10] <= altsyncram:the_altsyncram.q_b +q[11] <= altsyncram:the_altsyncram.q_b +q[12] <= altsyncram:the_altsyncram.q_b +q[13] <= altsyncram:the_altsyncram.q_b +q[14] <= altsyncram:the_altsyncram.q_b +q[15] <= altsyncram:the_altsyncram.q_b +q[16] <= altsyncram:the_altsyncram.q_b +q[17] <= altsyncram:the_altsyncram.q_b +q[18] <= altsyncram:the_altsyncram.q_b +q[19] <= altsyncram:the_altsyncram.q_b +q[20] <= altsyncram:the_altsyncram.q_b +q[21] <= altsyncram:the_altsyncram.q_b +q[22] <= altsyncram:the_altsyncram.q_b +q[23] <= altsyncram:the_altsyncram.q_b +q[24] <= altsyncram:the_altsyncram.q_b +q[25] <= altsyncram:the_altsyncram.q_b +q[26] <= altsyncram:the_altsyncram.q_b +q[27] <= altsyncram:the_altsyncram.q_b +q[28] <= altsyncram:the_altsyncram.q_b +q[29] <= altsyncram:the_altsyncram.q_b +q[30] <= altsyncram:the_altsyncram.q_b +q[31] <= altsyncram:the_altsyncram.q_b + + +|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_dc_victim_module:system_cpu_dc_victim|altsyncram:the_altsyncram +wren_a => altsyncram_r3d1:auto_generated.wren_a +rden_a => ~NO_FANOUT~ +wren_b => ~NO_FANOUT~ +rden_b => altsyncram_r3d1:auto_generated.rden_b +data_a[0] => altsyncram_r3d1:auto_generated.data_a[0] +data_a[1] => altsyncram_r3d1:auto_generated.data_a[1] +data_a[2] => altsyncram_r3d1:auto_generated.data_a[2] +data_a[3] => altsyncram_r3d1:auto_generated.data_a[3] +data_a[4] => altsyncram_r3d1:auto_generated.data_a[4] +data_a[5] => altsyncram_r3d1:auto_generated.data_a[5] +data_a[6] => altsyncram_r3d1:auto_generated.data_a[6] +data_a[7] => altsyncram_r3d1:auto_generated.data_a[7] +data_a[8] => altsyncram_r3d1:auto_generated.data_a[8] +data_a[9] => altsyncram_r3d1:auto_generated.data_a[9] +data_a[10] => altsyncram_r3d1:auto_generated.data_a[10] +data_a[11] => altsyncram_r3d1:auto_generated.data_a[11] +data_a[12] => altsyncram_r3d1:auto_generated.data_a[12] +data_a[13] => altsyncram_r3d1:auto_generated.data_a[13] +data_a[14] => altsyncram_r3d1:auto_generated.data_a[14] +data_a[15] => altsyncram_r3d1:auto_generated.data_a[15] +data_a[16] => altsyncram_r3d1:auto_generated.data_a[16] +data_a[17] => altsyncram_r3d1:auto_generated.data_a[17] +data_a[18] => altsyncram_r3d1:auto_generated.data_a[18] +data_a[19] => altsyncram_r3d1:auto_generated.data_a[19] +data_a[20] => altsyncram_r3d1:auto_generated.data_a[20] +data_a[21] => altsyncram_r3d1:auto_generated.data_a[21] +data_a[22] => altsyncram_r3d1:auto_generated.data_a[22] +data_a[23] => altsyncram_r3d1:auto_generated.data_a[23] +data_a[24] => altsyncram_r3d1:auto_generated.data_a[24] +data_a[25] => altsyncram_r3d1:auto_generated.data_a[25] +data_a[26] => altsyncram_r3d1:auto_generated.data_a[26] +data_a[27] => altsyncram_r3d1:auto_generated.data_a[27] +data_a[28] => altsyncram_r3d1:auto_generated.data_a[28] +data_a[29] => altsyncram_r3d1:auto_generated.data_a[29] +data_a[30] => altsyncram_r3d1:auto_generated.data_a[30] +data_a[31] => altsyncram_r3d1:auto_generated.data_a[31] +data_b[0] => ~NO_FANOUT~ +data_b[1] => ~NO_FANOUT~ +data_b[2] => ~NO_FANOUT~ +data_b[3] => ~NO_FANOUT~ +data_b[4] => ~NO_FANOUT~ +data_b[5] => ~NO_FANOUT~ +data_b[6] => ~NO_FANOUT~ +data_b[7] => ~NO_FANOUT~ +data_b[8] => ~NO_FANOUT~ +data_b[9] => ~NO_FANOUT~ +data_b[10] => ~NO_FANOUT~ +data_b[11] => ~NO_FANOUT~ +data_b[12] => ~NO_FANOUT~ +data_b[13] => ~NO_FANOUT~ +data_b[14] => ~NO_FANOUT~ +data_b[15] => ~NO_FANOUT~ +data_b[16] => ~NO_FANOUT~ +data_b[17] => ~NO_FANOUT~ +data_b[18] => ~NO_FANOUT~ +data_b[19] => ~NO_FANOUT~ +data_b[20] => ~NO_FANOUT~ +data_b[21] => ~NO_FANOUT~ +data_b[22] => ~NO_FANOUT~ +data_b[23] => ~NO_FANOUT~ +data_b[24] => ~NO_FANOUT~ +data_b[25] => ~NO_FANOUT~ +data_b[26] => ~NO_FANOUT~ +data_b[27] => ~NO_FANOUT~ +data_b[28] => ~NO_FANOUT~ +data_b[29] => ~NO_FANOUT~ +data_b[30] => ~NO_FANOUT~ +data_b[31] => ~NO_FANOUT~ +address_a[0] => altsyncram_r3d1:auto_generated.address_a[0] +address_a[1] => altsyncram_r3d1:auto_generated.address_a[1] +address_a[2] => altsyncram_r3d1:auto_generated.address_a[2] +address_b[0] => altsyncram_r3d1:auto_generated.address_b[0] +address_b[1] => altsyncram_r3d1:auto_generated.address_b[1] +address_b[2] => altsyncram_r3d1:auto_generated.address_b[2] +addressstall_a => ~NO_FANOUT~ +addressstall_b => ~NO_FANOUT~ +clock0 => altsyncram_r3d1:auto_generated.clock0 +clock1 => ~NO_FANOUT~ +clocken0 => ~NO_FANOUT~ +clocken1 => ~NO_FANOUT~ +clocken2 => ~NO_FANOUT~ +clocken3 => ~NO_FANOUT~ +aclr0 => ~NO_FANOUT~ +aclr1 => ~NO_FANOUT~ +byteena_a[0] => ~NO_FANOUT~ +byteena_b[0] => ~NO_FANOUT~ +q_a[0] <= +q_a[1] <= +q_a[2] <= +q_a[3] <= +q_a[4] <= +q_a[5] <= +q_a[6] <= +q_a[7] <= +q_a[8] <= +q_a[9] <= +q_a[10] <= +q_a[11] <= +q_a[12] <= +q_a[13] <= +q_a[14] <= +q_a[15] <= +q_a[16] <= +q_a[17] <= +q_a[18] <= +q_a[19] <= +q_a[20] <= +q_a[21] <= +q_a[22] <= +q_a[23] <= +q_a[24] <= +q_a[25] <= +q_a[26] <= +q_a[27] <= +q_a[28] <= +q_a[29] <= +q_a[30] <= +q_a[31] <= +q_b[0] <= altsyncram_r3d1:auto_generated.q_b[0] +q_b[1] <= altsyncram_r3d1:auto_generated.q_b[1] +q_b[2] <= altsyncram_r3d1:auto_generated.q_b[2] +q_b[3] <= altsyncram_r3d1:auto_generated.q_b[3] +q_b[4] <= altsyncram_r3d1:auto_generated.q_b[4] +q_b[5] <= altsyncram_r3d1:auto_generated.q_b[5] +q_b[6] <= altsyncram_r3d1:auto_generated.q_b[6] +q_b[7] <= altsyncram_r3d1:auto_generated.q_b[7] +q_b[8] <= altsyncram_r3d1:auto_generated.q_b[8] +q_b[9] <= altsyncram_r3d1:auto_generated.q_b[9] +q_b[10] <= altsyncram_r3d1:auto_generated.q_b[10] +q_b[11] <= altsyncram_r3d1:auto_generated.q_b[11] +q_b[12] <= altsyncram_r3d1:auto_generated.q_b[12] +q_b[13] <= altsyncram_r3d1:auto_generated.q_b[13] +q_b[14] <= altsyncram_r3d1:auto_generated.q_b[14] +q_b[15] <= altsyncram_r3d1:auto_generated.q_b[15] +q_b[16] <= altsyncram_r3d1:auto_generated.q_b[16] +q_b[17] <= altsyncram_r3d1:auto_generated.q_b[17] +q_b[18] <= altsyncram_r3d1:auto_generated.q_b[18] +q_b[19] <= altsyncram_r3d1:auto_generated.q_b[19] +q_b[20] <= altsyncram_r3d1:auto_generated.q_b[20] +q_b[21] <= altsyncram_r3d1:auto_generated.q_b[21] +q_b[22] <= altsyncram_r3d1:auto_generated.q_b[22] +q_b[23] <= altsyncram_r3d1:auto_generated.q_b[23] +q_b[24] <= altsyncram_r3d1:auto_generated.q_b[24] +q_b[25] <= altsyncram_r3d1:auto_generated.q_b[25] +q_b[26] <= altsyncram_r3d1:auto_generated.q_b[26] +q_b[27] <= altsyncram_r3d1:auto_generated.q_b[27] +q_b[28] <= altsyncram_r3d1:auto_generated.q_b[28] +q_b[29] <= altsyncram_r3d1:auto_generated.q_b[29] +q_b[30] <= altsyncram_r3d1:auto_generated.q_b[30] +q_b[31] <= altsyncram_r3d1:auto_generated.q_b[31] +eccstatus[0] <= +eccstatus[1] <= +eccstatus[2] <= + + +|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_dc_victim_module:system_cpu_dc_victim|altsyncram:the_altsyncram|altsyncram_r3d1:auto_generated +address_a[0] => ram_block1a0.PORTAADDR +address_a[0] => ram_block1a1.PORTAADDR +address_a[0] => ram_block1a2.PORTAADDR +address_a[0] => ram_block1a3.PORTAADDR +address_a[0] => ram_block1a4.PORTAADDR +address_a[0] => ram_block1a5.PORTAADDR +address_a[0] => ram_block1a6.PORTAADDR +address_a[0] => ram_block1a7.PORTAADDR +address_a[0] => ram_block1a8.PORTAADDR +address_a[0] => ram_block1a9.PORTAADDR +address_a[0] => ram_block1a10.PORTAADDR +address_a[0] => ram_block1a11.PORTAADDR +address_a[0] => ram_block1a12.PORTAADDR +address_a[0] => ram_block1a13.PORTAADDR +address_a[0] => ram_block1a14.PORTAADDR +address_a[0] => ram_block1a15.PORTAADDR +address_a[0] => ram_block1a16.PORTAADDR +address_a[0] => ram_block1a17.PORTAADDR +address_a[0] => ram_block1a18.PORTAADDR +address_a[0] => ram_block1a19.PORTAADDR +address_a[0] => ram_block1a20.PORTAADDR +address_a[0] => ram_block1a21.PORTAADDR +address_a[0] => ram_block1a22.PORTAADDR +address_a[0] => ram_block1a23.PORTAADDR +address_a[0] => ram_block1a24.PORTAADDR +address_a[0] => ram_block1a25.PORTAADDR +address_a[0] => ram_block1a26.PORTAADDR +address_a[0] => ram_block1a27.PORTAADDR +address_a[0] => ram_block1a28.PORTAADDR +address_a[0] => ram_block1a29.PORTAADDR +address_a[0] => ram_block1a30.PORTAADDR +address_a[0] => ram_block1a31.PORTAADDR +address_a[1] => ram_block1a0.PORTAADDR1 +address_a[1] => ram_block1a1.PORTAADDR1 +address_a[1] => ram_block1a2.PORTAADDR1 +address_a[1] => ram_block1a3.PORTAADDR1 +address_a[1] => ram_block1a4.PORTAADDR1 +address_a[1] => ram_block1a5.PORTAADDR1 +address_a[1] => ram_block1a6.PORTAADDR1 +address_a[1] => ram_block1a7.PORTAADDR1 +address_a[1] => ram_block1a8.PORTAADDR1 +address_a[1] => ram_block1a9.PORTAADDR1 +address_a[1] => ram_block1a10.PORTAADDR1 +address_a[1] => ram_block1a11.PORTAADDR1 +address_a[1] => ram_block1a12.PORTAADDR1 +address_a[1] => ram_block1a13.PORTAADDR1 +address_a[1] => ram_block1a14.PORTAADDR1 +address_a[1] => ram_block1a15.PORTAADDR1 +address_a[1] => ram_block1a16.PORTAADDR1 +address_a[1] => ram_block1a17.PORTAADDR1 +address_a[1] => ram_block1a18.PORTAADDR1 +address_a[1] => ram_block1a19.PORTAADDR1 +address_a[1] => ram_block1a20.PORTAADDR1 +address_a[1] => ram_block1a21.PORTAADDR1 +address_a[1] => ram_block1a22.PORTAADDR1 +address_a[1] => ram_block1a23.PORTAADDR1 +address_a[1] => ram_block1a24.PORTAADDR1 +address_a[1] => ram_block1a25.PORTAADDR1 +address_a[1] => ram_block1a26.PORTAADDR1 +address_a[1] => ram_block1a27.PORTAADDR1 +address_a[1] => ram_block1a28.PORTAADDR1 +address_a[1] => ram_block1a29.PORTAADDR1 +address_a[1] => ram_block1a30.PORTAADDR1 +address_a[1] => ram_block1a31.PORTAADDR1 +address_a[2] => ram_block1a0.PORTAADDR2 +address_a[2] => ram_block1a1.PORTAADDR2 +address_a[2] => ram_block1a2.PORTAADDR2 +address_a[2] => ram_block1a3.PORTAADDR2 +address_a[2] => ram_block1a4.PORTAADDR2 +address_a[2] => ram_block1a5.PORTAADDR2 +address_a[2] => ram_block1a6.PORTAADDR2 +address_a[2] => ram_block1a7.PORTAADDR2 +address_a[2] => ram_block1a8.PORTAADDR2 +address_a[2] => ram_block1a9.PORTAADDR2 +address_a[2] => ram_block1a10.PORTAADDR2 +address_a[2] => ram_block1a11.PORTAADDR2 +address_a[2] => ram_block1a12.PORTAADDR2 +address_a[2] => ram_block1a13.PORTAADDR2 +address_a[2] => ram_block1a14.PORTAADDR2 +address_a[2] => ram_block1a15.PORTAADDR2 +address_a[2] => ram_block1a16.PORTAADDR2 +address_a[2] => ram_block1a17.PORTAADDR2 +address_a[2] => ram_block1a18.PORTAADDR2 +address_a[2] => ram_block1a19.PORTAADDR2 +address_a[2] => ram_block1a20.PORTAADDR2 +address_a[2] => ram_block1a21.PORTAADDR2 +address_a[2] => ram_block1a22.PORTAADDR2 +address_a[2] => ram_block1a23.PORTAADDR2 +address_a[2] => ram_block1a24.PORTAADDR2 +address_a[2] => ram_block1a25.PORTAADDR2 +address_a[2] => ram_block1a26.PORTAADDR2 +address_a[2] => ram_block1a27.PORTAADDR2 +address_a[2] => ram_block1a28.PORTAADDR2 +address_a[2] => ram_block1a29.PORTAADDR2 +address_a[2] => ram_block1a30.PORTAADDR2 +address_a[2] => ram_block1a31.PORTAADDR2 +address_b[0] => ram_block1a0.PORTBADDR +address_b[0] => ram_block1a1.PORTBADDR +address_b[0] => ram_block1a2.PORTBADDR +address_b[0] => ram_block1a3.PORTBADDR +address_b[0] => ram_block1a4.PORTBADDR +address_b[0] => ram_block1a5.PORTBADDR +address_b[0] => ram_block1a6.PORTBADDR +address_b[0] => ram_block1a7.PORTBADDR +address_b[0] => ram_block1a8.PORTBADDR +address_b[0] => ram_block1a9.PORTBADDR +address_b[0] => ram_block1a10.PORTBADDR +address_b[0] => ram_block1a11.PORTBADDR +address_b[0] => ram_block1a12.PORTBADDR +address_b[0] => ram_block1a13.PORTBADDR +address_b[0] => ram_block1a14.PORTBADDR +address_b[0] => ram_block1a15.PORTBADDR +address_b[0] => ram_block1a16.PORTBADDR +address_b[0] => ram_block1a17.PORTBADDR +address_b[0] => ram_block1a18.PORTBADDR +address_b[0] => ram_block1a19.PORTBADDR +address_b[0] => ram_block1a20.PORTBADDR +address_b[0] => ram_block1a21.PORTBADDR +address_b[0] => ram_block1a22.PORTBADDR +address_b[0] => ram_block1a23.PORTBADDR +address_b[0] => ram_block1a24.PORTBADDR +address_b[0] => ram_block1a25.PORTBADDR +address_b[0] => ram_block1a26.PORTBADDR +address_b[0] => ram_block1a27.PORTBADDR +address_b[0] => ram_block1a28.PORTBADDR +address_b[0] => ram_block1a29.PORTBADDR +address_b[0] => ram_block1a30.PORTBADDR +address_b[0] => ram_block1a31.PORTBADDR +address_b[1] => ram_block1a0.PORTBADDR1 +address_b[1] => ram_block1a1.PORTBADDR1 +address_b[1] => ram_block1a2.PORTBADDR1 +address_b[1] => ram_block1a3.PORTBADDR1 +address_b[1] => ram_block1a4.PORTBADDR1 +address_b[1] => ram_block1a5.PORTBADDR1 +address_b[1] => ram_block1a6.PORTBADDR1 +address_b[1] => ram_block1a7.PORTBADDR1 +address_b[1] => ram_block1a8.PORTBADDR1 +address_b[1] => ram_block1a9.PORTBADDR1 +address_b[1] => ram_block1a10.PORTBADDR1 +address_b[1] => ram_block1a11.PORTBADDR1 +address_b[1] => ram_block1a12.PORTBADDR1 +address_b[1] => ram_block1a13.PORTBADDR1 +address_b[1] => ram_block1a14.PORTBADDR1 +address_b[1] => ram_block1a15.PORTBADDR1 +address_b[1] => ram_block1a16.PORTBADDR1 +address_b[1] => ram_block1a17.PORTBADDR1 +address_b[1] => ram_block1a18.PORTBADDR1 +address_b[1] => ram_block1a19.PORTBADDR1 +address_b[1] => ram_block1a20.PORTBADDR1 +address_b[1] => ram_block1a21.PORTBADDR1 +address_b[1] => ram_block1a22.PORTBADDR1 +address_b[1] => ram_block1a23.PORTBADDR1 +address_b[1] => ram_block1a24.PORTBADDR1 +address_b[1] => ram_block1a25.PORTBADDR1 +address_b[1] => ram_block1a26.PORTBADDR1 +address_b[1] => ram_block1a27.PORTBADDR1 +address_b[1] => ram_block1a28.PORTBADDR1 +address_b[1] => ram_block1a29.PORTBADDR1 +address_b[1] => ram_block1a30.PORTBADDR1 +address_b[1] => ram_block1a31.PORTBADDR1 +address_b[2] => ram_block1a0.PORTBADDR2 +address_b[2] => ram_block1a1.PORTBADDR2 +address_b[2] => ram_block1a2.PORTBADDR2 +address_b[2] => ram_block1a3.PORTBADDR2 +address_b[2] => ram_block1a4.PORTBADDR2 +address_b[2] => ram_block1a5.PORTBADDR2 +address_b[2] => ram_block1a6.PORTBADDR2 +address_b[2] => ram_block1a7.PORTBADDR2 +address_b[2] => ram_block1a8.PORTBADDR2 +address_b[2] => ram_block1a9.PORTBADDR2 +address_b[2] => ram_block1a10.PORTBADDR2 +address_b[2] => ram_block1a11.PORTBADDR2 +address_b[2] => ram_block1a12.PORTBADDR2 +address_b[2] => ram_block1a13.PORTBADDR2 +address_b[2] => ram_block1a14.PORTBADDR2 +address_b[2] => ram_block1a15.PORTBADDR2 +address_b[2] => ram_block1a16.PORTBADDR2 +address_b[2] => ram_block1a17.PORTBADDR2 +address_b[2] => ram_block1a18.PORTBADDR2 +address_b[2] => ram_block1a19.PORTBADDR2 +address_b[2] => ram_block1a20.PORTBADDR2 +address_b[2] => ram_block1a21.PORTBADDR2 +address_b[2] => ram_block1a22.PORTBADDR2 +address_b[2] => ram_block1a23.PORTBADDR2 +address_b[2] => ram_block1a24.PORTBADDR2 +address_b[2] => ram_block1a25.PORTBADDR2 +address_b[2] => ram_block1a26.PORTBADDR2 +address_b[2] => ram_block1a27.PORTBADDR2 +address_b[2] => ram_block1a28.PORTBADDR2 +address_b[2] => ram_block1a29.PORTBADDR2 +address_b[2] => ram_block1a30.PORTBADDR2 +address_b[2] => ram_block1a31.PORTBADDR2 +clock0 => ram_block1a0.CLK0 +clock0 => ram_block1a1.CLK0 +clock0 => ram_block1a2.CLK0 +clock0 => ram_block1a3.CLK0 +clock0 => ram_block1a4.CLK0 +clock0 => ram_block1a5.CLK0 +clock0 => ram_block1a6.CLK0 +clock0 => ram_block1a7.CLK0 +clock0 => ram_block1a8.CLK0 +clock0 => ram_block1a9.CLK0 +clock0 => ram_block1a10.CLK0 +clock0 => ram_block1a11.CLK0 +clock0 => ram_block1a12.CLK0 +clock0 => ram_block1a13.CLK0 +clock0 => ram_block1a14.CLK0 +clock0 => ram_block1a15.CLK0 +clock0 => ram_block1a16.CLK0 +clock0 => ram_block1a17.CLK0 +clock0 => ram_block1a18.CLK0 +clock0 => ram_block1a19.CLK0 +clock0 => ram_block1a20.CLK0 +clock0 => ram_block1a21.CLK0 +clock0 => ram_block1a22.CLK0 +clock0 => ram_block1a23.CLK0 +clock0 => ram_block1a24.CLK0 +clock0 => ram_block1a25.CLK0 +clock0 => ram_block1a26.CLK0 +clock0 => ram_block1a27.CLK0 +clock0 => ram_block1a28.CLK0 +clock0 => ram_block1a29.CLK0 +clock0 => ram_block1a30.CLK0 +clock0 => ram_block1a31.CLK0 +data_a[0] => ram_block1a0.PORTADATAIN +data_a[1] => ram_block1a1.PORTADATAIN +data_a[2] => ram_block1a2.PORTADATAIN +data_a[3] => ram_block1a3.PORTADATAIN +data_a[4] => ram_block1a4.PORTADATAIN +data_a[5] => ram_block1a5.PORTADATAIN +data_a[6] => ram_block1a6.PORTADATAIN +data_a[7] => ram_block1a7.PORTADATAIN +data_a[8] => ram_block1a8.PORTADATAIN +data_a[9] => ram_block1a9.PORTADATAIN +data_a[10] => ram_block1a10.PORTADATAIN +data_a[11] => ram_block1a11.PORTADATAIN +data_a[12] => ram_block1a12.PORTADATAIN +data_a[13] => ram_block1a13.PORTADATAIN +data_a[14] => ram_block1a14.PORTADATAIN +data_a[15] => ram_block1a15.PORTADATAIN +data_a[16] => ram_block1a16.PORTADATAIN +data_a[17] => ram_block1a17.PORTADATAIN +data_a[18] => ram_block1a18.PORTADATAIN +data_a[19] => ram_block1a19.PORTADATAIN +data_a[20] => ram_block1a20.PORTADATAIN +data_a[21] => ram_block1a21.PORTADATAIN +data_a[22] => ram_block1a22.PORTADATAIN +data_a[23] => ram_block1a23.PORTADATAIN +data_a[24] => ram_block1a24.PORTADATAIN +data_a[25] => ram_block1a25.PORTADATAIN +data_a[26] => ram_block1a26.PORTADATAIN +data_a[27] => ram_block1a27.PORTADATAIN +data_a[28] => ram_block1a28.PORTADATAIN +data_a[29] => ram_block1a29.PORTADATAIN +data_a[30] => ram_block1a30.PORTADATAIN +data_a[31] => ram_block1a31.PORTADATAIN +q_b[0] <= ram_block1a0.PORTBDATAOUT +q_b[1] <= ram_block1a1.PORTBDATAOUT +q_b[2] <= ram_block1a2.PORTBDATAOUT +q_b[3] <= ram_block1a3.PORTBDATAOUT +q_b[4] <= ram_block1a4.PORTBDATAOUT +q_b[5] <= ram_block1a5.PORTBDATAOUT +q_b[6] <= ram_block1a6.PORTBDATAOUT +q_b[7] <= ram_block1a7.PORTBDATAOUT +q_b[8] <= ram_block1a8.PORTBDATAOUT +q_b[9] <= ram_block1a9.PORTBDATAOUT +q_b[10] <= ram_block1a10.PORTBDATAOUT +q_b[11] <= ram_block1a11.PORTBDATAOUT +q_b[12] <= ram_block1a12.PORTBDATAOUT +q_b[13] <= ram_block1a13.PORTBDATAOUT +q_b[14] <= ram_block1a14.PORTBDATAOUT +q_b[15] <= ram_block1a15.PORTBDATAOUT +q_b[16] <= ram_block1a16.PORTBDATAOUT +q_b[17] <= ram_block1a17.PORTBDATAOUT +q_b[18] <= ram_block1a18.PORTBDATAOUT +q_b[19] <= ram_block1a19.PORTBDATAOUT +q_b[20] <= ram_block1a20.PORTBDATAOUT +q_b[21] <= ram_block1a21.PORTBDATAOUT +q_b[22] <= ram_block1a22.PORTBDATAOUT +q_b[23] <= ram_block1a23.PORTBDATAOUT +q_b[24] <= ram_block1a24.PORTBDATAOUT +q_b[25] <= ram_block1a25.PORTBDATAOUT +q_b[26] <= ram_block1a26.PORTBDATAOUT +q_b[27] <= ram_block1a27.PORTBDATAOUT +q_b[28] <= ram_block1a28.PORTBDATAOUT +q_b[29] <= ram_block1a29.PORTBDATAOUT +q_b[30] <= ram_block1a30.PORTBDATAOUT +q_b[31] <= ram_block1a31.PORTBDATAOUT +rden_b => ram_block1a0.PORTBRE +rden_b => ram_block1a1.PORTBRE +rden_b => ram_block1a2.PORTBRE +rden_b => ram_block1a3.PORTBRE +rden_b => ram_block1a4.PORTBRE +rden_b => ram_block1a5.PORTBRE +rden_b => ram_block1a6.PORTBRE +rden_b => ram_block1a7.PORTBRE +rden_b => ram_block1a8.PORTBRE +rden_b => ram_block1a9.PORTBRE +rden_b => ram_block1a10.PORTBRE +rden_b => ram_block1a11.PORTBRE +rden_b => ram_block1a12.PORTBRE +rden_b => ram_block1a13.PORTBRE +rden_b => ram_block1a14.PORTBRE +rden_b => ram_block1a15.PORTBRE +rden_b => ram_block1a16.PORTBRE +rden_b => ram_block1a17.PORTBRE +rden_b => ram_block1a18.PORTBRE +rden_b => ram_block1a19.PORTBRE +rden_b => ram_block1a20.PORTBRE +rden_b => ram_block1a21.PORTBRE +rden_b => ram_block1a22.PORTBRE +rden_b => ram_block1a23.PORTBRE +rden_b => ram_block1a24.PORTBRE +rden_b => ram_block1a25.PORTBRE +rden_b => ram_block1a26.PORTBRE +rden_b => ram_block1a27.PORTBRE +rden_b => ram_block1a28.PORTBRE +rden_b => ram_block1a29.PORTBRE +rden_b => ram_block1a30.PORTBRE +rden_b => ram_block1a31.PORTBRE +wren_a => ram_block1a0.PORTAWE +wren_a => ram_block1a1.PORTAWE +wren_a => ram_block1a2.PORTAWE +wren_a => ram_block1a3.PORTAWE +wren_a => ram_block1a4.PORTAWE +wren_a => ram_block1a5.PORTAWE +wren_a => ram_block1a6.PORTAWE +wren_a => ram_block1a7.PORTAWE +wren_a => ram_block1a8.PORTAWE +wren_a => ram_block1a9.PORTAWE +wren_a => ram_block1a10.PORTAWE +wren_a => ram_block1a11.PORTAWE +wren_a => ram_block1a12.PORTAWE +wren_a => ram_block1a13.PORTAWE +wren_a => ram_block1a14.PORTAWE +wren_a => ram_block1a15.PORTAWE +wren_a => ram_block1a16.PORTAWE +wren_a => ram_block1a17.PORTAWE +wren_a => ram_block1a18.PORTAWE +wren_a => ram_block1a19.PORTAWE +wren_a => ram_block1a20.PORTAWE +wren_a => ram_block1a21.PORTAWE +wren_a => ram_block1a22.PORTAWE +wren_a => ram_block1a23.PORTAWE +wren_a => ram_block1a24.PORTAWE +wren_a => ram_block1a25.PORTAWE +wren_a => ram_block1a26.PORTAWE +wren_a => ram_block1a27.PORTAWE +wren_a => ram_block1a28.PORTAWE +wren_a => ram_block1a29.PORTAWE +wren_a => ram_block1a30.PORTAWE +wren_a => ram_block1a31.PORTAWE + + +|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell +A_mul_src1[0] => A_mul_src1[0].IN1 +A_mul_src1[1] => A_mul_src1[1].IN1 +A_mul_src1[2] => A_mul_src1[2].IN1 +A_mul_src1[3] => A_mul_src1[3].IN1 +A_mul_src1[4] => A_mul_src1[4].IN1 +A_mul_src1[5] => A_mul_src1[5].IN1 +A_mul_src1[6] => A_mul_src1[6].IN1 +A_mul_src1[7] => A_mul_src1[7].IN1 +A_mul_src1[8] => A_mul_src1[8].IN1 +A_mul_src1[9] => A_mul_src1[9].IN1 +A_mul_src1[10] => A_mul_src1[10].IN1 +A_mul_src1[11] => A_mul_src1[11].IN1 +A_mul_src1[12] => A_mul_src1[12].IN1 +A_mul_src1[13] => A_mul_src1[13].IN1 +A_mul_src1[14] => A_mul_src1[14].IN1 +A_mul_src1[15] => A_mul_src1[15].IN1 +A_mul_src1[16] => A_mul_src1[16].IN1 +A_mul_src1[17] => A_mul_src1[17].IN1 +A_mul_src1[18] => A_mul_src1[18].IN1 +A_mul_src1[19] => A_mul_src1[19].IN1 +A_mul_src1[20] => A_mul_src1[20].IN1 +A_mul_src1[21] => A_mul_src1[21].IN1 +A_mul_src1[22] => A_mul_src1[22].IN1 +A_mul_src1[23] => A_mul_src1[23].IN1 +A_mul_src1[24] => A_mul_src1[24].IN1 +A_mul_src1[25] => A_mul_src1[25].IN1 +A_mul_src1[26] => A_mul_src1[26].IN1 +A_mul_src1[27] => A_mul_src1[27].IN1 +A_mul_src1[28] => A_mul_src1[28].IN1 +A_mul_src1[29] => A_mul_src1[29].IN1 +A_mul_src1[30] => A_mul_src1[30].IN1 +A_mul_src1[31] => A_mul_src1[31].IN1 +A_mul_src2[0] => A_mul_src2[0].IN2 +A_mul_src2[1] => A_mul_src2[1].IN2 +A_mul_src2[2] => A_mul_src2[2].IN2 +A_mul_src2[3] => A_mul_src2[3].IN2 +A_mul_src2[4] => A_mul_src2[4].IN2 +A_mul_src2[5] => A_mul_src2[5].IN2 +A_mul_src2[6] => A_mul_src2[6].IN2 +A_mul_src2[7] => A_mul_src2[7].IN2 +A_mul_src2[8] => A_mul_src2[8].IN2 +A_mul_src2[9] => A_mul_src2[9].IN2 +A_mul_src2[10] => A_mul_src2[10].IN2 +A_mul_src2[11] => A_mul_src2[11].IN2 +A_mul_src2[12] => A_mul_src2[12].IN2 +A_mul_src2[13] => A_mul_src2[13].IN2 +A_mul_src2[14] => A_mul_src2[14].IN2 +A_mul_src2[15] => A_mul_src2[15].IN2 +A_mul_src2[16] => ~NO_FANOUT~ +A_mul_src2[17] => ~NO_FANOUT~ +A_mul_src2[18] => ~NO_FANOUT~ +A_mul_src2[19] => ~NO_FANOUT~ +A_mul_src2[20] => ~NO_FANOUT~ +A_mul_src2[21] => ~NO_FANOUT~ +A_mul_src2[22] => ~NO_FANOUT~ +A_mul_src2[23] => ~NO_FANOUT~ +A_mul_src2[24] => ~NO_FANOUT~ +A_mul_src2[25] => ~NO_FANOUT~ +A_mul_src2[26] => ~NO_FANOUT~ +A_mul_src2[27] => ~NO_FANOUT~ +A_mul_src2[28] => ~NO_FANOUT~ +A_mul_src2[29] => ~NO_FANOUT~ +A_mul_src2[30] => ~NO_FANOUT~ +A_mul_src2[31] => ~NO_FANOUT~ +clk => clk.IN2 +reset_n => mul_clr.IN2 +A_mul_cell_result[0] <= altmult_add:the_altmult_add_part_1.result +A_mul_cell_result[1] <= altmult_add:the_altmult_add_part_1.result +A_mul_cell_result[2] <= altmult_add:the_altmult_add_part_1.result +A_mul_cell_result[3] <= altmult_add:the_altmult_add_part_1.result +A_mul_cell_result[4] <= altmult_add:the_altmult_add_part_1.result +A_mul_cell_result[5] <= altmult_add:the_altmult_add_part_1.result +A_mul_cell_result[6] <= altmult_add:the_altmult_add_part_1.result +A_mul_cell_result[7] <= altmult_add:the_altmult_add_part_1.result +A_mul_cell_result[8] <= altmult_add:the_altmult_add_part_1.result +A_mul_cell_result[9] <= altmult_add:the_altmult_add_part_1.result +A_mul_cell_result[10] <= altmult_add:the_altmult_add_part_1.result +A_mul_cell_result[11] <= altmult_add:the_altmult_add_part_1.result +A_mul_cell_result[12] <= altmult_add:the_altmult_add_part_1.result +A_mul_cell_result[13] <= altmult_add:the_altmult_add_part_1.result +A_mul_cell_result[14] <= altmult_add:the_altmult_add_part_1.result +A_mul_cell_result[15] <= altmult_add:the_altmult_add_part_1.result +A_mul_cell_result[16] <= Add0.DB_MAX_OUTPUT_PORT_TYPE +A_mul_cell_result[17] <= Add0.DB_MAX_OUTPUT_PORT_TYPE +A_mul_cell_result[18] <= Add0.DB_MAX_OUTPUT_PORT_TYPE +A_mul_cell_result[19] <= Add0.DB_MAX_OUTPUT_PORT_TYPE +A_mul_cell_result[20] <= Add0.DB_MAX_OUTPUT_PORT_TYPE +A_mul_cell_result[21] <= Add0.DB_MAX_OUTPUT_PORT_TYPE +A_mul_cell_result[22] <= Add0.DB_MAX_OUTPUT_PORT_TYPE +A_mul_cell_result[23] <= Add0.DB_MAX_OUTPUT_PORT_TYPE +A_mul_cell_result[24] <= Add0.DB_MAX_OUTPUT_PORT_TYPE +A_mul_cell_result[25] <= Add0.DB_MAX_OUTPUT_PORT_TYPE +A_mul_cell_result[26] <= Add0.DB_MAX_OUTPUT_PORT_TYPE +A_mul_cell_result[27] <= Add0.DB_MAX_OUTPUT_PORT_TYPE +A_mul_cell_result[28] <= Add0.DB_MAX_OUTPUT_PORT_TYPE +A_mul_cell_result[29] <= Add0.DB_MAX_OUTPUT_PORT_TYPE +A_mul_cell_result[30] <= Add0.DB_MAX_OUTPUT_PORT_TYPE +A_mul_cell_result[31] <= Add0.DB_MAX_OUTPUT_PORT_TYPE + + +|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1 +accum_sload => ~NO_FANOUT~ +aclr0 => mult_add_75u2:auto_generated.aclr0 +aclr1 => ~NO_FANOUT~ +aclr2 => ~NO_FANOUT~ +aclr3 => ~NO_FANOUT~ +addnsub1 => ~NO_FANOUT~ +addnsub1_round => ~NO_FANOUT~ +addnsub3 => ~NO_FANOUT~ +addnsub3_round => ~NO_FANOUT~ +chainin[0] => ~NO_FANOUT~ +chainout_round => ~NO_FANOUT~ +chainout_sat_overflow <= chainout_sat_overflow.DB_MAX_OUTPUT_PORT_TYPE +chainout_saturate => ~NO_FANOUT~ +clock0 => mult_add_75u2:auto_generated.clock0 +clock1 => ~NO_FANOUT~ +clock2 => ~NO_FANOUT~ +clock3 => ~NO_FANOUT~ +dataa[0] => mult_add_75u2:auto_generated.dataa[0] +dataa[1] => mult_add_75u2:auto_generated.dataa[1] +dataa[2] => mult_add_75u2:auto_generated.dataa[2] +dataa[3] => mult_add_75u2:auto_generated.dataa[3] +dataa[4] => mult_add_75u2:auto_generated.dataa[4] +dataa[5] => mult_add_75u2:auto_generated.dataa[5] +dataa[6] => mult_add_75u2:auto_generated.dataa[6] +dataa[7] => mult_add_75u2:auto_generated.dataa[7] +dataa[8] => mult_add_75u2:auto_generated.dataa[8] +dataa[9] => mult_add_75u2:auto_generated.dataa[9] +dataa[10] => mult_add_75u2:auto_generated.dataa[10] +dataa[11] => mult_add_75u2:auto_generated.dataa[11] +dataa[12] => mult_add_75u2:auto_generated.dataa[12] +dataa[13] => mult_add_75u2:auto_generated.dataa[13] +dataa[14] => mult_add_75u2:auto_generated.dataa[14] +dataa[15] => mult_add_75u2:auto_generated.dataa[15] +datab[0] => mult_add_75u2:auto_generated.datab[0] +datab[1] => mult_add_75u2:auto_generated.datab[1] +datab[2] => mult_add_75u2:auto_generated.datab[2] +datab[3] => mult_add_75u2:auto_generated.datab[3] +datab[4] => mult_add_75u2:auto_generated.datab[4] +datab[5] => mult_add_75u2:auto_generated.datab[5] +datab[6] => mult_add_75u2:auto_generated.datab[6] +datab[7] => mult_add_75u2:auto_generated.datab[7] +datab[8] => mult_add_75u2:auto_generated.datab[8] +datab[9] => mult_add_75u2:auto_generated.datab[9] +datab[10] => mult_add_75u2:auto_generated.datab[10] +datab[11] => mult_add_75u2:auto_generated.datab[11] +datab[12] => mult_add_75u2:auto_generated.datab[12] +datab[13] => mult_add_75u2:auto_generated.datab[13] +datab[14] => mult_add_75u2:auto_generated.datab[14] +datab[15] => mult_add_75u2:auto_generated.datab[15] +ena0 => ~NO_FANOUT~ +ena1 => ~NO_FANOUT~ +ena2 => ~NO_FANOUT~ +ena3 => ~NO_FANOUT~ +mult01_round => ~NO_FANOUT~ +mult01_saturation => ~NO_FANOUT~ +mult0_is_saturated <= mult0_is_saturated.DB_MAX_OUTPUT_PORT_TYPE +mult1_is_saturated <= mult1_is_saturated.DB_MAX_OUTPUT_PORT_TYPE +mult23_round => ~NO_FANOUT~ +mult23_saturation => ~NO_FANOUT~ +mult2_is_saturated <= mult2_is_saturated.DB_MAX_OUTPUT_PORT_TYPE +mult3_is_saturated <= mult3_is_saturated.DB_MAX_OUTPUT_PORT_TYPE +output_round => ~NO_FANOUT~ +output_saturate => ~NO_FANOUT~ +overflow <= overflow.DB_MAX_OUTPUT_PORT_TYPE +result[0] <= mult_add_75u2:auto_generated.result[0] +result[1] <= mult_add_75u2:auto_generated.result[1] +result[2] <= mult_add_75u2:auto_generated.result[2] +result[3] <= mult_add_75u2:auto_generated.result[3] +result[4] <= mult_add_75u2:auto_generated.result[4] +result[5] <= mult_add_75u2:auto_generated.result[5] +result[6] <= mult_add_75u2:auto_generated.result[6] +result[7] <= mult_add_75u2:auto_generated.result[7] +result[8] <= mult_add_75u2:auto_generated.result[8] +result[9] <= mult_add_75u2:auto_generated.result[9] +result[10] <= mult_add_75u2:auto_generated.result[10] +result[11] <= mult_add_75u2:auto_generated.result[11] +result[12] <= mult_add_75u2:auto_generated.result[12] +result[13] <= mult_add_75u2:auto_generated.result[13] +result[14] <= mult_add_75u2:auto_generated.result[14] +result[15] <= mult_add_75u2:auto_generated.result[15] +result[16] <= mult_add_75u2:auto_generated.result[16] +result[17] <= mult_add_75u2:auto_generated.result[17] +result[18] <= mult_add_75u2:auto_generated.result[18] +result[19] <= mult_add_75u2:auto_generated.result[19] +result[20] <= mult_add_75u2:auto_generated.result[20] +result[21] <= mult_add_75u2:auto_generated.result[21] +result[22] <= mult_add_75u2:auto_generated.result[22] +result[23] <= mult_add_75u2:auto_generated.result[23] +result[24] <= mult_add_75u2:auto_generated.result[24] +result[25] <= mult_add_75u2:auto_generated.result[25] +result[26] <= mult_add_75u2:auto_generated.result[26] +result[27] <= mult_add_75u2:auto_generated.result[27] +result[28] <= mult_add_75u2:auto_generated.result[28] +result[29] <= mult_add_75u2:auto_generated.result[29] +result[30] <= mult_add_75u2:auto_generated.result[30] +result[31] <= mult_add_75u2:auto_generated.result[31] +rotate => ~NO_FANOUT~ +scanina[0] => ~NO_FANOUT~ +scanina[1] => ~NO_FANOUT~ +scanina[2] => ~NO_FANOUT~ +scanina[3] => ~NO_FANOUT~ +scanina[4] => ~NO_FANOUT~ +scanina[5] => ~NO_FANOUT~ +scanina[6] => ~NO_FANOUT~ +scanina[7] => ~NO_FANOUT~ +scanina[8] => ~NO_FANOUT~ +scanina[9] => ~NO_FANOUT~ +scanina[10] => ~NO_FANOUT~ +scanina[11] => ~NO_FANOUT~ +scanina[12] => ~NO_FANOUT~ +scanina[13] => ~NO_FANOUT~ +scanina[14] => ~NO_FANOUT~ +scanina[15] => ~NO_FANOUT~ +scaninb[0] => ~NO_FANOUT~ +scaninb[1] => ~NO_FANOUT~ +scaninb[2] => ~NO_FANOUT~ +scaninb[3] => ~NO_FANOUT~ +scaninb[4] => ~NO_FANOUT~ +scaninb[5] => ~NO_FANOUT~ +scaninb[6] => ~NO_FANOUT~ +scaninb[7] => ~NO_FANOUT~ +scaninb[8] => ~NO_FANOUT~ +scaninb[9] => ~NO_FANOUT~ +scaninb[10] => ~NO_FANOUT~ +scaninb[11] => ~NO_FANOUT~ +scaninb[12] => ~NO_FANOUT~ +scaninb[13] => ~NO_FANOUT~ +scaninb[14] => ~NO_FANOUT~ +scaninb[15] => ~NO_FANOUT~ +scanouta[0] <= scanouta[0].DB_MAX_OUTPUT_PORT_TYPE +scanouta[1] <= scanouta[1].DB_MAX_OUTPUT_PORT_TYPE +scanouta[2] <= scanouta[2].DB_MAX_OUTPUT_PORT_TYPE +scanouta[3] <= scanouta[3].DB_MAX_OUTPUT_PORT_TYPE +scanouta[4] <= scanouta[4].DB_MAX_OUTPUT_PORT_TYPE +scanouta[5] <= scanouta[5].DB_MAX_OUTPUT_PORT_TYPE +scanouta[6] <= scanouta[6].DB_MAX_OUTPUT_PORT_TYPE +scanouta[7] <= scanouta[7].DB_MAX_OUTPUT_PORT_TYPE +scanouta[8] <= scanouta[8].DB_MAX_OUTPUT_PORT_TYPE +scanouta[9] <= scanouta[9].DB_MAX_OUTPUT_PORT_TYPE +scanouta[10] <= scanouta[10].DB_MAX_OUTPUT_PORT_TYPE +scanouta[11] <= scanouta[11].DB_MAX_OUTPUT_PORT_TYPE +scanouta[12] <= scanouta[12].DB_MAX_OUTPUT_PORT_TYPE +scanouta[13] <= scanouta[13].DB_MAX_OUTPUT_PORT_TYPE +scanouta[14] <= scanouta[14].DB_MAX_OUTPUT_PORT_TYPE +scanouta[15] <= scanouta[15].DB_MAX_OUTPUT_PORT_TYPE +scanoutb[0] <= scanoutb[0].DB_MAX_OUTPUT_PORT_TYPE +scanoutb[1] <= scanoutb[1].DB_MAX_OUTPUT_PORT_TYPE +scanoutb[2] <= scanoutb[2].DB_MAX_OUTPUT_PORT_TYPE +scanoutb[3] <= scanoutb[3].DB_MAX_OUTPUT_PORT_TYPE +scanoutb[4] <= scanoutb[4].DB_MAX_OUTPUT_PORT_TYPE +scanoutb[5] <= scanoutb[5].DB_MAX_OUTPUT_PORT_TYPE +scanoutb[6] <= scanoutb[6].DB_MAX_OUTPUT_PORT_TYPE +scanoutb[7] <= scanoutb[7].DB_MAX_OUTPUT_PORT_TYPE +scanoutb[8] <= scanoutb[8].DB_MAX_OUTPUT_PORT_TYPE +scanoutb[9] <= scanoutb[9].DB_MAX_OUTPUT_PORT_TYPE +scanoutb[10] <= scanoutb[10].DB_MAX_OUTPUT_PORT_TYPE +scanoutb[11] <= scanoutb[11].DB_MAX_OUTPUT_PORT_TYPE +scanoutb[12] <= scanoutb[12].DB_MAX_OUTPUT_PORT_TYPE +scanoutb[13] <= scanoutb[13].DB_MAX_OUTPUT_PORT_TYPE +scanoutb[14] <= scanoutb[14].DB_MAX_OUTPUT_PORT_TYPE +scanoutb[15] <= scanoutb[15].DB_MAX_OUTPUT_PORT_TYPE +shift_right => ~NO_FANOUT~ +signa => ~NO_FANOUT~ +signb => ~NO_FANOUT~ +sourcea[0] => ~NO_FANOUT~ +sourceb[0] => ~NO_FANOUT~ +zero_chainout => ~NO_FANOUT~ +zero_loopback => ~NO_FANOUT~ +coefsel0[0] => ~NO_FANOUT~ +coefsel0[1] => ~NO_FANOUT~ +coefsel0[2] => ~NO_FANOUT~ +coefsel1[0] => ~NO_FANOUT~ +coefsel1[1] => ~NO_FANOUT~ +coefsel1[2] => ~NO_FANOUT~ +coefsel2[0] => ~NO_FANOUT~ +coefsel2[1] => ~NO_FANOUT~ +coefsel2[2] => ~NO_FANOUT~ +coefsel3[0] => ~NO_FANOUT~ +coefsel3[1] => ~NO_FANOUT~ +coefsel3[2] => ~NO_FANOUT~ +datac[0] => ~NO_FANOUT~ +datac[1] => ~NO_FANOUT~ +datac[2] => ~NO_FANOUT~ +datac[3] => ~NO_FANOUT~ +datac[4] => ~NO_FANOUT~ +datac[5] => ~NO_FANOUT~ +datac[6] => ~NO_FANOUT~ +datac[7] => ~NO_FANOUT~ +datac[8] => ~NO_FANOUT~ +datac[9] => ~NO_FANOUT~ +datac[10] => ~NO_FANOUT~ +datac[11] => ~NO_FANOUT~ +datac[12] => ~NO_FANOUT~ +datac[13] => ~NO_FANOUT~ +datac[14] => ~NO_FANOUT~ +datac[15] => ~NO_FANOUT~ +datac[16] => ~NO_FANOUT~ +datac[17] => ~NO_FANOUT~ +datac[18] => ~NO_FANOUT~ +datac[19] => ~NO_FANOUT~ +datac[20] => ~NO_FANOUT~ +datac[21] => ~NO_FANOUT~ + + +|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated +aclr0 => ded_mult_ks81:ded_mult1.aclr[0] +clock0 => ded_mult_ks81:ded_mult1.clock[0] +dataa[0] => ded_mult_ks81:ded_mult1.dataa[0] +dataa[1] => ded_mult_ks81:ded_mult1.dataa[1] +dataa[2] => ded_mult_ks81:ded_mult1.dataa[2] +dataa[3] => ded_mult_ks81:ded_mult1.dataa[3] +dataa[4] => ded_mult_ks81:ded_mult1.dataa[4] +dataa[5] => ded_mult_ks81:ded_mult1.dataa[5] +dataa[6] => ded_mult_ks81:ded_mult1.dataa[6] +dataa[7] => ded_mult_ks81:ded_mult1.dataa[7] +dataa[8] => ded_mult_ks81:ded_mult1.dataa[8] +dataa[9] => ded_mult_ks81:ded_mult1.dataa[9] +dataa[10] => ded_mult_ks81:ded_mult1.dataa[10] +dataa[11] => ded_mult_ks81:ded_mult1.dataa[11] +dataa[12] => ded_mult_ks81:ded_mult1.dataa[12] +dataa[13] => ded_mult_ks81:ded_mult1.dataa[13] +dataa[14] => ded_mult_ks81:ded_mult1.dataa[14] +dataa[15] => ded_mult_ks81:ded_mult1.dataa[15] +datab[0] => ded_mult_ks81:ded_mult1.datab[0] +datab[1] => ded_mult_ks81:ded_mult1.datab[1] +datab[2] => ded_mult_ks81:ded_mult1.datab[2] +datab[3] => ded_mult_ks81:ded_mult1.datab[3] +datab[4] => ded_mult_ks81:ded_mult1.datab[4] +datab[5] => ded_mult_ks81:ded_mult1.datab[5] +datab[6] => ded_mult_ks81:ded_mult1.datab[6] +datab[7] => ded_mult_ks81:ded_mult1.datab[7] +datab[8] => ded_mult_ks81:ded_mult1.datab[8] +datab[9] => ded_mult_ks81:ded_mult1.datab[9] +datab[10] => ded_mult_ks81:ded_mult1.datab[10] +datab[11] => ded_mult_ks81:ded_mult1.datab[11] +datab[12] => ded_mult_ks81:ded_mult1.datab[12] +datab[13] => ded_mult_ks81:ded_mult1.datab[13] +datab[14] => ded_mult_ks81:ded_mult1.datab[14] +datab[15] => ded_mult_ks81:ded_mult1.datab[15] +result[0] <= pre_result[0].DB_MAX_OUTPUT_PORT_TYPE +result[1] <= pre_result[1].DB_MAX_OUTPUT_PORT_TYPE +result[2] <= pre_result[2].DB_MAX_OUTPUT_PORT_TYPE +result[3] <= pre_result[3].DB_MAX_OUTPUT_PORT_TYPE +result[4] <= pre_result[4].DB_MAX_OUTPUT_PORT_TYPE +result[5] <= pre_result[5].DB_MAX_OUTPUT_PORT_TYPE +result[6] <= pre_result[6].DB_MAX_OUTPUT_PORT_TYPE +result[7] <= pre_result[7].DB_MAX_OUTPUT_PORT_TYPE +result[8] <= pre_result[8].DB_MAX_OUTPUT_PORT_TYPE +result[9] <= pre_result[9].DB_MAX_OUTPUT_PORT_TYPE +result[10] <= pre_result[10].DB_MAX_OUTPUT_PORT_TYPE +result[11] <= pre_result[11].DB_MAX_OUTPUT_PORT_TYPE +result[12] <= pre_result[12].DB_MAX_OUTPUT_PORT_TYPE +result[13] <= pre_result[13].DB_MAX_OUTPUT_PORT_TYPE +result[14] <= pre_result[14].DB_MAX_OUTPUT_PORT_TYPE +result[15] <= pre_result[15].DB_MAX_OUTPUT_PORT_TYPE +result[16] <= pre_result[16].DB_MAX_OUTPUT_PORT_TYPE +result[17] <= pre_result[17].DB_MAX_OUTPUT_PORT_TYPE +result[18] <= pre_result[18].DB_MAX_OUTPUT_PORT_TYPE +result[19] <= pre_result[19].DB_MAX_OUTPUT_PORT_TYPE +result[20] <= pre_result[20].DB_MAX_OUTPUT_PORT_TYPE +result[21] <= pre_result[21].DB_MAX_OUTPUT_PORT_TYPE +result[22] <= pre_result[22].DB_MAX_OUTPUT_PORT_TYPE +result[23] <= pre_result[23].DB_MAX_OUTPUT_PORT_TYPE +result[24] <= pre_result[24].DB_MAX_OUTPUT_PORT_TYPE +result[25] <= pre_result[25].DB_MAX_OUTPUT_PORT_TYPE +result[26] <= pre_result[26].DB_MAX_OUTPUT_PORT_TYPE +result[27] <= pre_result[27].DB_MAX_OUTPUT_PORT_TYPE +result[28] <= pre_result[28].DB_MAX_OUTPUT_PORT_TYPE +result[29] <= pre_result[29].DB_MAX_OUTPUT_PORT_TYPE +result[30] <= pre_result[30].DB_MAX_OUTPUT_PORT_TYPE +result[31] <= pre_result[31].DB_MAX_OUTPUT_PORT_TYPE + + +|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1 +aclr[0] => mac_mult2.ACLR +aclr[0] => mac_out3.ACLR +aclr[1] => ~NO_FANOUT~ +aclr[2] => ~NO_FANOUT~ +aclr[3] => ~NO_FANOUT~ +clock[0] => mac_mult2.CLK +clock[0] => mac_out3.CLK +clock[1] => ~NO_FANOUT~ +clock[2] => ~NO_FANOUT~ +clock[3] => ~NO_FANOUT~ +dataa[0] => mac_mult2.DATAA +dataa[1] => mac_mult2.DATAA1 +dataa[2] => mac_mult2.DATAA2 +dataa[3] => mac_mult2.DATAA3 +dataa[4] => mac_mult2.DATAA4 +dataa[5] => mac_mult2.DATAA5 +dataa[6] => mac_mult2.DATAA6 +dataa[7] => mac_mult2.DATAA7 +dataa[8] => mac_mult2.DATAA8 +dataa[9] => mac_mult2.DATAA9 +dataa[10] => mac_mult2.DATAA10 +dataa[11] => mac_mult2.DATAA11 +dataa[12] => mac_mult2.DATAA12 +dataa[13] => mac_mult2.DATAA13 +dataa[14] => mac_mult2.DATAA14 +dataa[15] => mac_mult2.DATAA15 +datab[0] => mac_mult2.DATAB +datab[1] => mac_mult2.DATAB1 +datab[2] => mac_mult2.DATAB2 +datab[3] => mac_mult2.DATAB3 +datab[4] => mac_mult2.DATAB4 +datab[5] => mac_mult2.DATAB5 +datab[6] => mac_mult2.DATAB6 +datab[7] => mac_mult2.DATAB7 +datab[8] => mac_mult2.DATAB8 +datab[9] => mac_mult2.DATAB9 +datab[10] => mac_mult2.DATAB10 +datab[11] => mac_mult2.DATAB11 +datab[12] => mac_mult2.DATAB12 +datab[13] => mac_mult2.DATAB13 +datab[14] => mac_mult2.DATAB14 +datab[15] => mac_mult2.DATAB15 +ena[0] => mac_mult2.ENA +ena[0] => mac_out3.ENA +ena[1] => ~NO_FANOUT~ +ena[2] => ~NO_FANOUT~ +ena[3] => ~NO_FANOUT~ +result[0] <= dffpipe_93c:pre_result.q[0] +result[1] <= dffpipe_93c:pre_result.q[1] +result[2] <= dffpipe_93c:pre_result.q[2] +result[3] <= dffpipe_93c:pre_result.q[3] +result[4] <= dffpipe_93c:pre_result.q[4] +result[5] <= dffpipe_93c:pre_result.q[5] +result[6] <= dffpipe_93c:pre_result.q[6] +result[7] <= dffpipe_93c:pre_result.q[7] +result[8] <= dffpipe_93c:pre_result.q[8] +result[9] <= dffpipe_93c:pre_result.q[9] +result[10] <= dffpipe_93c:pre_result.q[10] +result[11] <= dffpipe_93c:pre_result.q[11] +result[12] <= dffpipe_93c:pre_result.q[12] +result[13] <= dffpipe_93c:pre_result.q[13] +result[14] <= dffpipe_93c:pre_result.q[14] +result[15] <= dffpipe_93c:pre_result.q[15] +result[16] <= dffpipe_93c:pre_result.q[16] +result[17] <= dffpipe_93c:pre_result.q[17] +result[18] <= dffpipe_93c:pre_result.q[18] +result[19] <= dffpipe_93c:pre_result.q[19] +result[20] <= dffpipe_93c:pre_result.q[20] +result[21] <= dffpipe_93c:pre_result.q[21] +result[22] <= dffpipe_93c:pre_result.q[22] +result[23] <= dffpipe_93c:pre_result.q[23] +result[24] <= dffpipe_93c:pre_result.q[24] +result[25] <= dffpipe_93c:pre_result.q[25] +result[26] <= dffpipe_93c:pre_result.q[26] +result[27] <= dffpipe_93c:pre_result.q[27] +result[28] <= dffpipe_93c:pre_result.q[28] +result[29] <= dffpipe_93c:pre_result.q[29] +result[30] <= dffpipe_93c:pre_result.q[30] +result[31] <= dffpipe_93c:pre_result.q[31] + + +|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|dffpipe_93c:pre_result +d[0] => q[0].DATAIN +d[1] => q[1].DATAIN +d[2] => q[2].DATAIN +d[3] => q[3].DATAIN +d[4] => q[4].DATAIN +d[5] => q[5].DATAIN +d[6] => q[6].DATAIN +d[7] => q[7].DATAIN +d[8] => q[8].DATAIN +d[9] => q[9].DATAIN +d[10] => q[10].DATAIN +d[11] => q[11].DATAIN +d[12] => q[12].DATAIN +d[13] => q[13].DATAIN +d[14] => q[14].DATAIN +d[15] => q[15].DATAIN +d[16] => q[16].DATAIN +d[17] => q[17].DATAIN +d[18] => q[18].DATAIN +d[19] => q[19].DATAIN +d[20] => q[20].DATAIN +d[21] => q[21].DATAIN +d[22] => q[22].DATAIN +d[23] => q[23].DATAIN +d[24] => q[24].DATAIN +d[25] => q[25].DATAIN +d[26] => q[26].DATAIN +d[27] => q[27].DATAIN +d[28] => q[28].DATAIN +d[29] => q[29].DATAIN +d[30] => q[30].DATAIN +d[31] => q[31].DATAIN +q[0] <= d[0].DB_MAX_OUTPUT_PORT_TYPE +q[1] <= d[1].DB_MAX_OUTPUT_PORT_TYPE +q[2] <= d[2].DB_MAX_OUTPUT_PORT_TYPE +q[3] <= d[3].DB_MAX_OUTPUT_PORT_TYPE +q[4] <= d[4].DB_MAX_OUTPUT_PORT_TYPE +q[5] <= d[5].DB_MAX_OUTPUT_PORT_TYPE +q[6] <= d[6].DB_MAX_OUTPUT_PORT_TYPE +q[7] <= d[7].DB_MAX_OUTPUT_PORT_TYPE +q[8] <= d[8].DB_MAX_OUTPUT_PORT_TYPE +q[9] <= d[9].DB_MAX_OUTPUT_PORT_TYPE +q[10] <= d[10].DB_MAX_OUTPUT_PORT_TYPE +q[11] <= d[11].DB_MAX_OUTPUT_PORT_TYPE +q[12] <= d[12].DB_MAX_OUTPUT_PORT_TYPE +q[13] <= d[13].DB_MAX_OUTPUT_PORT_TYPE +q[14] <= d[14].DB_MAX_OUTPUT_PORT_TYPE +q[15] <= d[15].DB_MAX_OUTPUT_PORT_TYPE +q[16] <= d[16].DB_MAX_OUTPUT_PORT_TYPE +q[17] <= d[17].DB_MAX_OUTPUT_PORT_TYPE +q[18] <= d[18].DB_MAX_OUTPUT_PORT_TYPE +q[19] <= d[19].DB_MAX_OUTPUT_PORT_TYPE +q[20] <= d[20].DB_MAX_OUTPUT_PORT_TYPE +q[21] <= d[21].DB_MAX_OUTPUT_PORT_TYPE +q[22] <= d[22].DB_MAX_OUTPUT_PORT_TYPE +q[23] <= d[23].DB_MAX_OUTPUT_PORT_TYPE +q[24] <= d[24].DB_MAX_OUTPUT_PORT_TYPE +q[25] <= d[25].DB_MAX_OUTPUT_PORT_TYPE +q[26] <= d[26].DB_MAX_OUTPUT_PORT_TYPE +q[27] <= d[27].DB_MAX_OUTPUT_PORT_TYPE +q[28] <= d[28].DB_MAX_OUTPUT_PORT_TYPE +q[29] <= d[29].DB_MAX_OUTPUT_PORT_TYPE +q[30] <= d[30].DB_MAX_OUTPUT_PORT_TYPE +q[31] <= d[31].DB_MAX_OUTPUT_PORT_TYPE + + +|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2 +accum_sload => ~NO_FANOUT~ +aclr0 => mult_add_95u2:auto_generated.aclr0 +aclr1 => ~NO_FANOUT~ +aclr2 => ~NO_FANOUT~ +aclr3 => ~NO_FANOUT~ +addnsub1 => ~NO_FANOUT~ +addnsub1_round => ~NO_FANOUT~ +addnsub3 => ~NO_FANOUT~ +addnsub3_round => ~NO_FANOUT~ +chainin[0] => ~NO_FANOUT~ +chainout_round => ~NO_FANOUT~ +chainout_sat_overflow <= chainout_sat_overflow.DB_MAX_OUTPUT_PORT_TYPE +chainout_saturate => ~NO_FANOUT~ +clock0 => mult_add_95u2:auto_generated.clock0 +clock1 => ~NO_FANOUT~ +clock2 => ~NO_FANOUT~ +clock3 => ~NO_FANOUT~ +dataa[0] => mult_add_95u2:auto_generated.dataa[0] +dataa[1] => mult_add_95u2:auto_generated.dataa[1] +dataa[2] => mult_add_95u2:auto_generated.dataa[2] +dataa[3] => mult_add_95u2:auto_generated.dataa[3] +dataa[4] => mult_add_95u2:auto_generated.dataa[4] +dataa[5] => mult_add_95u2:auto_generated.dataa[5] +dataa[6] => mult_add_95u2:auto_generated.dataa[6] +dataa[7] => mult_add_95u2:auto_generated.dataa[7] +dataa[8] => mult_add_95u2:auto_generated.dataa[8] +dataa[9] => mult_add_95u2:auto_generated.dataa[9] +dataa[10] => mult_add_95u2:auto_generated.dataa[10] +dataa[11] => mult_add_95u2:auto_generated.dataa[11] +dataa[12] => mult_add_95u2:auto_generated.dataa[12] +dataa[13] => mult_add_95u2:auto_generated.dataa[13] +dataa[14] => mult_add_95u2:auto_generated.dataa[14] +dataa[15] => mult_add_95u2:auto_generated.dataa[15] +datab[0] => mult_add_95u2:auto_generated.datab[0] +datab[1] => mult_add_95u2:auto_generated.datab[1] +datab[2] => mult_add_95u2:auto_generated.datab[2] +datab[3] => mult_add_95u2:auto_generated.datab[3] +datab[4] => mult_add_95u2:auto_generated.datab[4] +datab[5] => mult_add_95u2:auto_generated.datab[5] +datab[6] => mult_add_95u2:auto_generated.datab[6] +datab[7] => mult_add_95u2:auto_generated.datab[7] +datab[8] => mult_add_95u2:auto_generated.datab[8] +datab[9] => mult_add_95u2:auto_generated.datab[9] +datab[10] => mult_add_95u2:auto_generated.datab[10] +datab[11] => mult_add_95u2:auto_generated.datab[11] +datab[12] => mult_add_95u2:auto_generated.datab[12] +datab[13] => mult_add_95u2:auto_generated.datab[13] +datab[14] => mult_add_95u2:auto_generated.datab[14] +datab[15] => mult_add_95u2:auto_generated.datab[15] +ena0 => ~NO_FANOUT~ +ena1 => ~NO_FANOUT~ +ena2 => ~NO_FANOUT~ +ena3 => ~NO_FANOUT~ +mult01_round => ~NO_FANOUT~ +mult01_saturation => ~NO_FANOUT~ +mult0_is_saturated <= mult0_is_saturated.DB_MAX_OUTPUT_PORT_TYPE +mult1_is_saturated <= mult1_is_saturated.DB_MAX_OUTPUT_PORT_TYPE +mult23_round => ~NO_FANOUT~ +mult23_saturation => ~NO_FANOUT~ +mult2_is_saturated <= mult2_is_saturated.DB_MAX_OUTPUT_PORT_TYPE +mult3_is_saturated <= mult3_is_saturated.DB_MAX_OUTPUT_PORT_TYPE +output_round => ~NO_FANOUT~ +output_saturate => ~NO_FANOUT~ +overflow <= overflow.DB_MAX_OUTPUT_PORT_TYPE +result[0] <= mult_add_95u2:auto_generated.result[0] +result[1] <= mult_add_95u2:auto_generated.result[1] +result[2] <= mult_add_95u2:auto_generated.result[2] +result[3] <= mult_add_95u2:auto_generated.result[3] +result[4] <= mult_add_95u2:auto_generated.result[4] +result[5] <= mult_add_95u2:auto_generated.result[5] +result[6] <= mult_add_95u2:auto_generated.result[6] +result[7] <= mult_add_95u2:auto_generated.result[7] +result[8] <= mult_add_95u2:auto_generated.result[8] +result[9] <= mult_add_95u2:auto_generated.result[9] +result[10] <= mult_add_95u2:auto_generated.result[10] +result[11] <= mult_add_95u2:auto_generated.result[11] +result[12] <= mult_add_95u2:auto_generated.result[12] +result[13] <= mult_add_95u2:auto_generated.result[13] +result[14] <= mult_add_95u2:auto_generated.result[14] +result[15] <= mult_add_95u2:auto_generated.result[15] +rotate => ~NO_FANOUT~ +scanina[0] => ~NO_FANOUT~ +scanina[1] => ~NO_FANOUT~ +scanina[2] => ~NO_FANOUT~ +scanina[3] => ~NO_FANOUT~ +scanina[4] => ~NO_FANOUT~ +scanina[5] => ~NO_FANOUT~ +scanina[6] => ~NO_FANOUT~ +scanina[7] => ~NO_FANOUT~ +scanina[8] => ~NO_FANOUT~ +scanina[9] => ~NO_FANOUT~ +scanina[10] => ~NO_FANOUT~ +scanina[11] => ~NO_FANOUT~ +scanina[12] => ~NO_FANOUT~ +scanina[13] => ~NO_FANOUT~ +scanina[14] => ~NO_FANOUT~ +scanina[15] => ~NO_FANOUT~ +scaninb[0] => ~NO_FANOUT~ +scaninb[1] => ~NO_FANOUT~ +scaninb[2] => ~NO_FANOUT~ +scaninb[3] => ~NO_FANOUT~ +scaninb[4] => ~NO_FANOUT~ +scaninb[5] => ~NO_FANOUT~ +scaninb[6] => ~NO_FANOUT~ +scaninb[7] => ~NO_FANOUT~ +scaninb[8] => ~NO_FANOUT~ +scaninb[9] => ~NO_FANOUT~ +scaninb[10] => ~NO_FANOUT~ +scaninb[11] => ~NO_FANOUT~ +scaninb[12] => ~NO_FANOUT~ +scaninb[13] => ~NO_FANOUT~ +scaninb[14] => ~NO_FANOUT~ +scaninb[15] => ~NO_FANOUT~ +scanouta[0] <= scanouta[0].DB_MAX_OUTPUT_PORT_TYPE +scanouta[1] <= scanouta[1].DB_MAX_OUTPUT_PORT_TYPE +scanouta[2] <= scanouta[2].DB_MAX_OUTPUT_PORT_TYPE +scanouta[3] <= scanouta[3].DB_MAX_OUTPUT_PORT_TYPE +scanouta[4] <= scanouta[4].DB_MAX_OUTPUT_PORT_TYPE +scanouta[5] <= scanouta[5].DB_MAX_OUTPUT_PORT_TYPE +scanouta[6] <= scanouta[6].DB_MAX_OUTPUT_PORT_TYPE +scanouta[7] <= scanouta[7].DB_MAX_OUTPUT_PORT_TYPE +scanouta[8] <= scanouta[8].DB_MAX_OUTPUT_PORT_TYPE +scanouta[9] <= scanouta[9].DB_MAX_OUTPUT_PORT_TYPE +scanouta[10] <= scanouta[10].DB_MAX_OUTPUT_PORT_TYPE +scanouta[11] <= scanouta[11].DB_MAX_OUTPUT_PORT_TYPE +scanouta[12] <= scanouta[12].DB_MAX_OUTPUT_PORT_TYPE +scanouta[13] <= scanouta[13].DB_MAX_OUTPUT_PORT_TYPE +scanouta[14] <= scanouta[14].DB_MAX_OUTPUT_PORT_TYPE +scanouta[15] <= scanouta[15].DB_MAX_OUTPUT_PORT_TYPE +scanoutb[0] <= scanoutb[0].DB_MAX_OUTPUT_PORT_TYPE +scanoutb[1] <= scanoutb[1].DB_MAX_OUTPUT_PORT_TYPE +scanoutb[2] <= scanoutb[2].DB_MAX_OUTPUT_PORT_TYPE +scanoutb[3] <= scanoutb[3].DB_MAX_OUTPUT_PORT_TYPE +scanoutb[4] <= scanoutb[4].DB_MAX_OUTPUT_PORT_TYPE +scanoutb[5] <= scanoutb[5].DB_MAX_OUTPUT_PORT_TYPE +scanoutb[6] <= scanoutb[6].DB_MAX_OUTPUT_PORT_TYPE +scanoutb[7] <= scanoutb[7].DB_MAX_OUTPUT_PORT_TYPE +scanoutb[8] <= scanoutb[8].DB_MAX_OUTPUT_PORT_TYPE +scanoutb[9] <= scanoutb[9].DB_MAX_OUTPUT_PORT_TYPE +scanoutb[10] <= scanoutb[10].DB_MAX_OUTPUT_PORT_TYPE +scanoutb[11] <= scanoutb[11].DB_MAX_OUTPUT_PORT_TYPE +scanoutb[12] <= scanoutb[12].DB_MAX_OUTPUT_PORT_TYPE +scanoutb[13] <= scanoutb[13].DB_MAX_OUTPUT_PORT_TYPE +scanoutb[14] <= scanoutb[14].DB_MAX_OUTPUT_PORT_TYPE +scanoutb[15] <= scanoutb[15].DB_MAX_OUTPUT_PORT_TYPE +shift_right => ~NO_FANOUT~ +signa => ~NO_FANOUT~ +signb => ~NO_FANOUT~ +sourcea[0] => ~NO_FANOUT~ +sourceb[0] => ~NO_FANOUT~ +zero_chainout => ~NO_FANOUT~ +zero_loopback => ~NO_FANOUT~ +coefsel0[0] => ~NO_FANOUT~ +coefsel0[1] => ~NO_FANOUT~ +coefsel0[2] => ~NO_FANOUT~ +coefsel1[0] => ~NO_FANOUT~ +coefsel1[1] => ~NO_FANOUT~ +coefsel1[2] => ~NO_FANOUT~ +coefsel2[0] => ~NO_FANOUT~ +coefsel2[1] => ~NO_FANOUT~ +coefsel2[2] => ~NO_FANOUT~ +coefsel3[0] => ~NO_FANOUT~ +coefsel3[1] => ~NO_FANOUT~ +coefsel3[2] => ~NO_FANOUT~ +datac[0] => ~NO_FANOUT~ +datac[1] => ~NO_FANOUT~ +datac[2] => ~NO_FANOUT~ +datac[3] => ~NO_FANOUT~ +datac[4] => ~NO_FANOUT~ +datac[5] => ~NO_FANOUT~ +datac[6] => ~NO_FANOUT~ +datac[7] => ~NO_FANOUT~ +datac[8] => ~NO_FANOUT~ +datac[9] => ~NO_FANOUT~ +datac[10] => ~NO_FANOUT~ +datac[11] => ~NO_FANOUT~ +datac[12] => ~NO_FANOUT~ +datac[13] => ~NO_FANOUT~ +datac[14] => ~NO_FANOUT~ +datac[15] => ~NO_FANOUT~ +datac[16] => ~NO_FANOUT~ +datac[17] => ~NO_FANOUT~ +datac[18] => ~NO_FANOUT~ +datac[19] => ~NO_FANOUT~ +datac[20] => ~NO_FANOUT~ +datac[21] => ~NO_FANOUT~ + + +|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated +aclr0 => ded_mult_ks81:ded_mult1.aclr[0] +clock0 => ded_mult_ks81:ded_mult1.clock[0] +dataa[0] => ded_mult_ks81:ded_mult1.dataa[0] +dataa[1] => ded_mult_ks81:ded_mult1.dataa[1] +dataa[2] => ded_mult_ks81:ded_mult1.dataa[2] +dataa[3] => ded_mult_ks81:ded_mult1.dataa[3] +dataa[4] => ded_mult_ks81:ded_mult1.dataa[4] +dataa[5] => ded_mult_ks81:ded_mult1.dataa[5] +dataa[6] => ded_mult_ks81:ded_mult1.dataa[6] +dataa[7] => ded_mult_ks81:ded_mult1.dataa[7] +dataa[8] => ded_mult_ks81:ded_mult1.dataa[8] +dataa[9] => ded_mult_ks81:ded_mult1.dataa[9] +dataa[10] => ded_mult_ks81:ded_mult1.dataa[10] +dataa[11] => ded_mult_ks81:ded_mult1.dataa[11] +dataa[12] => ded_mult_ks81:ded_mult1.dataa[12] +dataa[13] => ded_mult_ks81:ded_mult1.dataa[13] +dataa[14] => ded_mult_ks81:ded_mult1.dataa[14] +dataa[15] => ded_mult_ks81:ded_mult1.dataa[15] +datab[0] => ded_mult_ks81:ded_mult1.datab[0] +datab[1] => ded_mult_ks81:ded_mult1.datab[1] +datab[2] => ded_mult_ks81:ded_mult1.datab[2] +datab[3] => ded_mult_ks81:ded_mult1.datab[3] +datab[4] => ded_mult_ks81:ded_mult1.datab[4] +datab[5] => ded_mult_ks81:ded_mult1.datab[5] +datab[6] => ded_mult_ks81:ded_mult1.datab[6] +datab[7] => ded_mult_ks81:ded_mult1.datab[7] +datab[8] => ded_mult_ks81:ded_mult1.datab[8] +datab[9] => ded_mult_ks81:ded_mult1.datab[9] +datab[10] => ded_mult_ks81:ded_mult1.datab[10] +datab[11] => ded_mult_ks81:ded_mult1.datab[11] +datab[12] => ded_mult_ks81:ded_mult1.datab[12] +datab[13] => ded_mult_ks81:ded_mult1.datab[13] +datab[14] => ded_mult_ks81:ded_mult1.datab[14] +datab[15] => ded_mult_ks81:ded_mult1.datab[15] +result[0] <= pre_result[0].DB_MAX_OUTPUT_PORT_TYPE +result[1] <= pre_result[1].DB_MAX_OUTPUT_PORT_TYPE +result[2] <= pre_result[2].DB_MAX_OUTPUT_PORT_TYPE +result[3] <= pre_result[3].DB_MAX_OUTPUT_PORT_TYPE +result[4] <= pre_result[4].DB_MAX_OUTPUT_PORT_TYPE +result[5] <= pre_result[5].DB_MAX_OUTPUT_PORT_TYPE +result[6] <= pre_result[6].DB_MAX_OUTPUT_PORT_TYPE +result[7] <= pre_result[7].DB_MAX_OUTPUT_PORT_TYPE +result[8] <= pre_result[8].DB_MAX_OUTPUT_PORT_TYPE +result[9] <= pre_result[9].DB_MAX_OUTPUT_PORT_TYPE +result[10] <= pre_result[10].DB_MAX_OUTPUT_PORT_TYPE +result[11] <= pre_result[11].DB_MAX_OUTPUT_PORT_TYPE +result[12] <= pre_result[12].DB_MAX_OUTPUT_PORT_TYPE +result[13] <= pre_result[13].DB_MAX_OUTPUT_PORT_TYPE +result[14] <= pre_result[14].DB_MAX_OUTPUT_PORT_TYPE +result[15] <= pre_result[15].DB_MAX_OUTPUT_PORT_TYPE + + +|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated|ded_mult_ks81:ded_mult1 +aclr[0] => mac_mult2.ACLR +aclr[0] => mac_out3.ACLR +aclr[1] => ~NO_FANOUT~ +aclr[2] => ~NO_FANOUT~ +aclr[3] => ~NO_FANOUT~ +clock[0] => mac_mult2.CLK +clock[0] => mac_out3.CLK +clock[1] => ~NO_FANOUT~ +clock[2] => ~NO_FANOUT~ +clock[3] => ~NO_FANOUT~ +dataa[0] => mac_mult2.DATAA +dataa[1] => mac_mult2.DATAA1 +dataa[2] => mac_mult2.DATAA2 +dataa[3] => mac_mult2.DATAA3 +dataa[4] => mac_mult2.DATAA4 +dataa[5] => mac_mult2.DATAA5 +dataa[6] => mac_mult2.DATAA6 +dataa[7] => mac_mult2.DATAA7 +dataa[8] => mac_mult2.DATAA8 +dataa[9] => mac_mult2.DATAA9 +dataa[10] => mac_mult2.DATAA10 +dataa[11] => mac_mult2.DATAA11 +dataa[12] => mac_mult2.DATAA12 +dataa[13] => mac_mult2.DATAA13 +dataa[14] => mac_mult2.DATAA14 +dataa[15] => mac_mult2.DATAA15 +datab[0] => mac_mult2.DATAB +datab[1] => mac_mult2.DATAB1 +datab[2] => mac_mult2.DATAB2 +datab[3] => mac_mult2.DATAB3 +datab[4] => mac_mult2.DATAB4 +datab[5] => mac_mult2.DATAB5 +datab[6] => mac_mult2.DATAB6 +datab[7] => mac_mult2.DATAB7 +datab[8] => mac_mult2.DATAB8 +datab[9] => mac_mult2.DATAB9 +datab[10] => mac_mult2.DATAB10 +datab[11] => mac_mult2.DATAB11 +datab[12] => mac_mult2.DATAB12 +datab[13] => mac_mult2.DATAB13 +datab[14] => mac_mult2.DATAB14 +datab[15] => mac_mult2.DATAB15 +ena[0] => mac_mult2.ENA +ena[0] => mac_out3.ENA +ena[1] => ~NO_FANOUT~ +ena[2] => ~NO_FANOUT~ +ena[3] => ~NO_FANOUT~ +result[0] <= dffpipe_93c:pre_result.q[0] +result[1] <= dffpipe_93c:pre_result.q[1] +result[2] <= dffpipe_93c:pre_result.q[2] +result[3] <= dffpipe_93c:pre_result.q[3] +result[4] <= dffpipe_93c:pre_result.q[4] +result[5] <= dffpipe_93c:pre_result.q[5] +result[6] <= dffpipe_93c:pre_result.q[6] +result[7] <= dffpipe_93c:pre_result.q[7] +result[8] <= dffpipe_93c:pre_result.q[8] +result[9] <= dffpipe_93c:pre_result.q[9] +result[10] <= dffpipe_93c:pre_result.q[10] +result[11] <= dffpipe_93c:pre_result.q[11] +result[12] <= dffpipe_93c:pre_result.q[12] +result[13] <= dffpipe_93c:pre_result.q[13] +result[14] <= dffpipe_93c:pre_result.q[14] +result[15] <= dffpipe_93c:pre_result.q[15] +result[16] <= dffpipe_93c:pre_result.q[16] +result[17] <= dffpipe_93c:pre_result.q[17] +result[18] <= dffpipe_93c:pre_result.q[18] +result[19] <= dffpipe_93c:pre_result.q[19] +result[20] <= dffpipe_93c:pre_result.q[20] +result[21] <= dffpipe_93c:pre_result.q[21] +result[22] <= dffpipe_93c:pre_result.q[22] +result[23] <= dffpipe_93c:pre_result.q[23] +result[24] <= dffpipe_93c:pre_result.q[24] +result[25] <= dffpipe_93c:pre_result.q[25] +result[26] <= dffpipe_93c:pre_result.q[26] +result[27] <= dffpipe_93c:pre_result.q[27] +result[28] <= dffpipe_93c:pre_result.q[28] +result[29] <= dffpipe_93c:pre_result.q[29] +result[30] <= dffpipe_93c:pre_result.q[30] +result[31] <= dffpipe_93c:pre_result.q[31] + + +|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated|ded_mult_ks81:ded_mult1|dffpipe_93c:pre_result +d[0] => q[0].DATAIN +d[1] => q[1].DATAIN +d[2] => q[2].DATAIN +d[3] => q[3].DATAIN +d[4] => q[4].DATAIN +d[5] => q[5].DATAIN +d[6] => q[6].DATAIN +d[7] => q[7].DATAIN +d[8] => q[8].DATAIN +d[9] => q[9].DATAIN +d[10] => q[10].DATAIN +d[11] => q[11].DATAIN +d[12] => q[12].DATAIN +d[13] => q[13].DATAIN +d[14] => q[14].DATAIN +d[15] => q[15].DATAIN +d[16] => q[16].DATAIN +d[17] => q[17].DATAIN +d[18] => q[18].DATAIN +d[19] => q[19].DATAIN +d[20] => q[20].DATAIN +d[21] => q[21].DATAIN +d[22] => q[22].DATAIN +d[23] => q[23].DATAIN +d[24] => q[24].DATAIN +d[25] => q[25].DATAIN +d[26] => q[26].DATAIN +d[27] => q[27].DATAIN +d[28] => q[28].DATAIN +d[29] => q[29].DATAIN +d[30] => q[30].DATAIN +d[31] => q[31].DATAIN +q[0] <= d[0].DB_MAX_OUTPUT_PORT_TYPE +q[1] <= d[1].DB_MAX_OUTPUT_PORT_TYPE +q[2] <= d[2].DB_MAX_OUTPUT_PORT_TYPE +q[3] <= d[3].DB_MAX_OUTPUT_PORT_TYPE +q[4] <= d[4].DB_MAX_OUTPUT_PORT_TYPE +q[5] <= d[5].DB_MAX_OUTPUT_PORT_TYPE +q[6] <= d[6].DB_MAX_OUTPUT_PORT_TYPE +q[7] <= d[7].DB_MAX_OUTPUT_PORT_TYPE +q[8] <= d[8].DB_MAX_OUTPUT_PORT_TYPE +q[9] <= d[9].DB_MAX_OUTPUT_PORT_TYPE +q[10] <= d[10].DB_MAX_OUTPUT_PORT_TYPE +q[11] <= d[11].DB_MAX_OUTPUT_PORT_TYPE +q[12] <= d[12].DB_MAX_OUTPUT_PORT_TYPE +q[13] <= d[13].DB_MAX_OUTPUT_PORT_TYPE +q[14] <= d[14].DB_MAX_OUTPUT_PORT_TYPE +q[15] <= d[15].DB_MAX_OUTPUT_PORT_TYPE +q[16] <= d[16].DB_MAX_OUTPUT_PORT_TYPE +q[17] <= d[17].DB_MAX_OUTPUT_PORT_TYPE +q[18] <= d[18].DB_MAX_OUTPUT_PORT_TYPE +q[19] <= d[19].DB_MAX_OUTPUT_PORT_TYPE +q[20] <= d[20].DB_MAX_OUTPUT_PORT_TYPE +q[21] <= d[21].DB_MAX_OUTPUT_PORT_TYPE +q[22] <= d[22].DB_MAX_OUTPUT_PORT_TYPE +q[23] <= d[23].DB_MAX_OUTPUT_PORT_TYPE +q[24] <= d[24].DB_MAX_OUTPUT_PORT_TYPE +q[25] <= d[25].DB_MAX_OUTPUT_PORT_TYPE +q[26] <= d[26].DB_MAX_OUTPUT_PORT_TYPE +q[27] <= d[27].DB_MAX_OUTPUT_PORT_TYPE +q[28] <= d[28].DB_MAX_OUTPUT_PORT_TYPE +q[29] <= d[29].DB_MAX_OUTPUT_PORT_TYPE +q[30] <= d[30].DB_MAX_OUTPUT_PORT_TYPE +q[31] <= d[31].DB_MAX_OUTPUT_PORT_TYPE + + +|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci +A_cmp_result => A_cmp_result.IN1 +A_ctrl_exception => A_ctrl_exception.IN1 +A_ctrl_ld => A_ctrl_ld.IN1 +A_ctrl_st => A_ctrl_st.IN1 +A_en => A_en.IN2 +A_mem_baddr[0] => A_mem_baddr[0].IN1 +A_mem_baddr[1] => A_mem_baddr[1].IN1 +A_mem_baddr[2] => A_mem_baddr[2].IN1 +A_mem_baddr[3] => A_mem_baddr[3].IN1 +A_mem_baddr[4] => A_mem_baddr[4].IN1 +A_mem_baddr[5] => A_mem_baddr[5].IN1 +A_mem_baddr[6] => A_mem_baddr[6].IN1 +A_mem_baddr[7] => A_mem_baddr[7].IN1 +A_mem_baddr[8] => A_mem_baddr[8].IN1 +A_mem_baddr[9] => A_mem_baddr[9].IN1 +A_mem_baddr[10] => A_mem_baddr[10].IN1 +A_mem_baddr[11] => A_mem_baddr[11].IN1 +A_mem_baddr[12] => A_mem_baddr[12].IN1 +A_mem_baddr[13] => A_mem_baddr[13].IN1 +A_mem_baddr[14] => A_mem_baddr[14].IN1 +A_mem_baddr[15] => A_mem_baddr[15].IN1 +A_mem_baddr[16] => A_mem_baddr[16].IN1 +A_mem_baddr[17] => A_mem_baddr[17].IN1 +A_mem_baddr[18] => A_mem_baddr[18].IN1 +A_mem_baddr[19] => A_mem_baddr[19].IN1 +A_mem_baddr[20] => A_mem_baddr[20].IN1 +A_mem_baddr[21] => A_mem_baddr[21].IN1 +A_mem_baddr[22] => A_mem_baddr[22].IN1 +A_mem_baddr[23] => A_mem_baddr[23].IN1 +A_mem_baddr[24] => A_mem_baddr[24].IN1 +A_mem_baddr[25] => A_mem_baddr[25].IN1 +A_op_beq => A_op_beq.IN1 +A_op_bge => A_op_bge.IN1 +A_op_bgeu => A_op_bgeu.IN1 +A_op_blt => A_op_blt.IN1 +A_op_bltu => A_op_bltu.IN1 +A_op_bne => A_op_bne.IN1 +A_op_br => A_op_br.IN1 +A_op_bret => A_op_bret.IN1 +A_op_call => A_op_call.IN1 +A_op_callr => A_op_callr.IN1 +A_op_eret => A_op_eret.IN1 +A_op_jmp => A_op_jmp.IN1 +A_op_jmpi => A_op_jmpi.IN1 +A_op_ret => A_op_ret.IN1 +A_pcb[0] => A_pcb[0].IN1 +A_pcb[1] => A_pcb[1].IN1 +A_pcb[2] => A_pcb[2].IN1 +A_pcb[3] => A_pcb[3].IN1 +A_pcb[4] => A_pcb[4].IN1 +A_pcb[5] => A_pcb[5].IN1 +A_pcb[6] => A_pcb[6].IN1 +A_pcb[7] => A_pcb[7].IN1 +A_pcb[8] => A_pcb[8].IN1 +A_pcb[9] => A_pcb[9].IN1 +A_pcb[10] => A_pcb[10].IN1 +A_pcb[11] => A_pcb[11].IN1 +A_pcb[12] => A_pcb[12].IN1 +A_pcb[13] => A_pcb[13].IN1 +A_pcb[14] => A_pcb[14].IN1 +A_pcb[15] => A_pcb[15].IN1 +A_pcb[16] => A_pcb[16].IN1 +A_pcb[17] => A_pcb[17].IN1 +A_pcb[18] => A_pcb[18].IN1 +A_pcb[19] => A_pcb[19].IN1 +A_pcb[20] => A_pcb[20].IN1 +A_pcb[21] => A_pcb[21].IN1 +A_pcb[22] => A_pcb[22].IN1 +A_pcb[23] => A_pcb[23].IN1 +A_pcb[24] => A_pcb[24].IN1 +A_pcb[25] => A_pcb[25].IN1 +A_st_data[0] => A_st_data[0].IN1 +A_st_data[1] => A_st_data[1].IN1 +A_st_data[2] => A_st_data[2].IN1 +A_st_data[3] => A_st_data[3].IN1 +A_st_data[4] => A_st_data[4].IN1 +A_st_data[5] => A_st_data[5].IN1 +A_st_data[6] => A_st_data[6].IN1 +A_st_data[7] => A_st_data[7].IN1 +A_st_data[8] => A_st_data[8].IN1 +A_st_data[9] => A_st_data[9].IN1 +A_st_data[10] => A_st_data[10].IN1 +A_st_data[11] => A_st_data[11].IN1 +A_st_data[12] => A_st_data[12].IN1 +A_st_data[13] => A_st_data[13].IN1 +A_st_data[14] => A_st_data[14].IN1 +A_st_data[15] => A_st_data[15].IN1 +A_st_data[16] => A_st_data[16].IN1 +A_st_data[17] => A_st_data[17].IN1 +A_st_data[18] => A_st_data[18].IN1 +A_st_data[19] => A_st_data[19].IN1 +A_st_data[20] => A_st_data[20].IN1 +A_st_data[21] => A_st_data[21].IN1 +A_st_data[22] => A_st_data[22].IN1 +A_st_data[23] => A_st_data[23].IN1 +A_st_data[24] => A_st_data[24].IN1 +A_st_data[25] => A_st_data[25].IN1 +A_st_data[26] => A_st_data[26].IN1 +A_st_data[27] => A_st_data[27].IN1 +A_st_data[28] => A_st_data[28].IN1 +A_st_data[29] => A_st_data[29].IN1 +A_st_data[30] => A_st_data[30].IN1 +A_st_data[31] => A_st_data[31].IN1 +A_valid => A_valid.IN2 +A_wr_data_filtered[0] => A_wr_data_filtered[0].IN2 +A_wr_data_filtered[1] => A_wr_data_filtered[1].IN2 +A_wr_data_filtered[2] => A_wr_data_filtered[2].IN2 +A_wr_data_filtered[3] => A_wr_data_filtered[3].IN2 +A_wr_data_filtered[4] => A_wr_data_filtered[4].IN2 +A_wr_data_filtered[5] => A_wr_data_filtered[5].IN2 +A_wr_data_filtered[6] => A_wr_data_filtered[6].IN2 +A_wr_data_filtered[7] => A_wr_data_filtered[7].IN2 +A_wr_data_filtered[8] => A_wr_data_filtered[8].IN2 +A_wr_data_filtered[9] => A_wr_data_filtered[9].IN2 +A_wr_data_filtered[10] => A_wr_data_filtered[10].IN2 +A_wr_data_filtered[11] => A_wr_data_filtered[11].IN2 +A_wr_data_filtered[12] => A_wr_data_filtered[12].IN2 +A_wr_data_filtered[13] => A_wr_data_filtered[13].IN2 +A_wr_data_filtered[14] => A_wr_data_filtered[14].IN2 +A_wr_data_filtered[15] => A_wr_data_filtered[15].IN2 +A_wr_data_filtered[16] => A_wr_data_filtered[16].IN2 +A_wr_data_filtered[17] => A_wr_data_filtered[17].IN2 +A_wr_data_filtered[18] => A_wr_data_filtered[18].IN2 +A_wr_data_filtered[19] => A_wr_data_filtered[19].IN2 +A_wr_data_filtered[20] => A_wr_data_filtered[20].IN2 +A_wr_data_filtered[21] => A_wr_data_filtered[21].IN2 +A_wr_data_filtered[22] => A_wr_data_filtered[22].IN2 +A_wr_data_filtered[23] => A_wr_data_filtered[23].IN2 +A_wr_data_filtered[24] => A_wr_data_filtered[24].IN2 +A_wr_data_filtered[25] => A_wr_data_filtered[25].IN2 +A_wr_data_filtered[26] => A_wr_data_filtered[26].IN2 +A_wr_data_filtered[27] => A_wr_data_filtered[27].IN2 +A_wr_data_filtered[28] => A_wr_data_filtered[28].IN2 +A_wr_data_filtered[29] => A_wr_data_filtered[29].IN2 +A_wr_data_filtered[30] => A_wr_data_filtered[30].IN2 +A_wr_data_filtered[31] => A_wr_data_filtered[31].IN2 +D_en => D_en.IN1 +E_en => E_en.IN1 +E_valid => E_valid.IN1 +F_pc[0] => F_pc[0].IN1 +F_pc[1] => F_pc[1].IN1 +F_pc[2] => F_pc[2].IN1 +F_pc[3] => F_pc[3].IN1 +F_pc[4] => F_pc[4].IN1 +F_pc[5] => F_pc[5].IN1 +F_pc[6] => F_pc[6].IN1 +F_pc[7] => F_pc[7].IN1 +F_pc[8] => F_pc[8].IN1 +F_pc[9] => F_pc[9].IN1 +F_pc[10] => F_pc[10].IN1 +F_pc[11] => F_pc[11].IN1 +F_pc[12] => F_pc[12].IN1 +F_pc[13] => F_pc[13].IN1 +F_pc[14] => F_pc[14].IN1 +F_pc[15] => F_pc[15].IN1 +F_pc[16] => F_pc[16].IN1 +F_pc[17] => F_pc[17].IN1 +F_pc[18] => F_pc[18].IN1 +F_pc[19] => F_pc[19].IN1 +F_pc[20] => F_pc[20].IN1 +F_pc[21] => F_pc[21].IN1 +F_pc[22] => F_pc[22].IN1 +F_pc[23] => F_pc[23].IN1 +M_en => M_en.IN1 +address[0] => address[0].IN2 +address[1] => address[1].IN2 +address[2] => address[2].IN2 +address[3] => address[3].IN2 +address[4] => address[4].IN2 +address[5] => address[5].IN2 +address[6] => address[6].IN2 +address[7] => address[7].IN2 +address[8] => address[8].IN2 +begintransfer => begintransfer.IN1 +byteenable[0] => byteenable[0].IN1 +byteenable[1] => byteenable[1].IN1 +byteenable[2] => byteenable[2].IN1 +byteenable[3] => byteenable[3].IN1 +chipselect => chipselect.IN2 +clk => clk.IN12 +debugaccess => debugaccess.IN2 +hbreak_enabled => hbreak_enabled.IN1 +reset => reset.IN1 +reset_n => reset_n.IN8 +test_ending => test_ending.IN1 +test_has_ended => test_has_ended.IN1 +write => write.IN2 +writedata[0] => writedata[0].IN2 +writedata[1] => writedata[1].IN2 +writedata[2] => writedata[2].IN2 +writedata[3] => writedata[3].IN2 +writedata[4] => writedata[4].IN2 +writedata[5] => writedata[5].IN2 +writedata[6] => writedata[6].IN2 +writedata[7] => writedata[7].IN2 +writedata[8] => writedata[8].IN2 +writedata[9] => writedata[9].IN2 +writedata[10] => writedata[10].IN2 +writedata[11] => writedata[11].IN2 +writedata[12] => writedata[12].IN2 +writedata[13] => writedata[13].IN2 +writedata[14] => writedata[14].IN2 +writedata[15] => writedata[15].IN2 +writedata[16] => writedata[16].IN2 +writedata[17] => writedata[17].IN2 +writedata[18] => writedata[18].IN2 +writedata[19] => writedata[19].IN2 +writedata[20] => writedata[20].IN2 +writedata[21] => writedata[21].IN2 +writedata[22] => writedata[22].IN2 +writedata[23] => writedata[23].IN2 +writedata[24] => writedata[24].IN2 +writedata[25] => writedata[25].IN2 +writedata[26] => writedata[26].IN2 +writedata[27] => writedata[27].IN2 +writedata[28] => writedata[28].IN2 +writedata[29] => writedata[29].IN2 +writedata[30] => writedata[30].IN2 +writedata[31] => writedata[31].IN2 +jtag_debug_module_debugaccess_to_roms <= debugack.DB_MAX_OUTPUT_PORT_TYPE +oci_hbreak_req <= system_cpu_nios2_oci_debug:the_system_cpu_nios2_oci_debug.oci_hbreak_req +oci_ienable[0] <= system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg.oci_ienable +oci_ienable[1] <= system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg.oci_ienable +oci_ienable[2] <= system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg.oci_ienable +oci_ienable[3] <= system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg.oci_ienable +oci_ienable[4] <= system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg.oci_ienable +oci_ienable[5] <= system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg.oci_ienable +oci_ienable[6] <= system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg.oci_ienable +oci_ienable[7] <= system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg.oci_ienable +oci_ienable[8] <= system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg.oci_ienable +oci_ienable[9] <= system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg.oci_ienable +oci_ienable[10] <= system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg.oci_ienable +oci_ienable[11] <= system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg.oci_ienable +oci_ienable[12] <= system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg.oci_ienable +oci_ienable[13] <= system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg.oci_ienable +oci_ienable[14] <= system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg.oci_ienable +oci_ienable[15] <= system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg.oci_ienable +oci_ienable[16] <= system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg.oci_ienable +oci_ienable[17] <= system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg.oci_ienable +oci_ienable[18] <= system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg.oci_ienable +oci_ienable[19] <= system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg.oci_ienable +oci_ienable[20] <= system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg.oci_ienable +oci_ienable[21] <= system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg.oci_ienable +oci_ienable[22] <= system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg.oci_ienable +oci_ienable[23] <= system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg.oci_ienable +oci_ienable[24] <= system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg.oci_ienable +oci_ienable[25] <= system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg.oci_ienable +oci_ienable[26] <= system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg.oci_ienable +oci_ienable[27] <= system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg.oci_ienable +oci_ienable[28] <= system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg.oci_ienable +oci_ienable[29] <= system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg.oci_ienable +oci_ienable[30] <= system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg.oci_ienable +oci_ienable[31] <= system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg.oci_ienable +oci_single_step_mode <= system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg.oci_single_step_mode +readdata[0] <= readdata.DB_MAX_OUTPUT_PORT_TYPE +readdata[1] <= readdata.DB_MAX_OUTPUT_PORT_TYPE +readdata[2] <= readdata.DB_MAX_OUTPUT_PORT_TYPE +readdata[3] <= readdata.DB_MAX_OUTPUT_PORT_TYPE +readdata[4] <= readdata.DB_MAX_OUTPUT_PORT_TYPE +readdata[5] <= readdata.DB_MAX_OUTPUT_PORT_TYPE +readdata[6] <= readdata.DB_MAX_OUTPUT_PORT_TYPE +readdata[7] <= readdata.DB_MAX_OUTPUT_PORT_TYPE +readdata[8] <= readdata.DB_MAX_OUTPUT_PORT_TYPE +readdata[9] <= readdata.DB_MAX_OUTPUT_PORT_TYPE +readdata[10] <= readdata.DB_MAX_OUTPUT_PORT_TYPE +readdata[11] <= readdata.DB_MAX_OUTPUT_PORT_TYPE +readdata[12] <= readdata.DB_MAX_OUTPUT_PORT_TYPE +readdata[13] <= readdata.DB_MAX_OUTPUT_PORT_TYPE +readdata[14] <= readdata.DB_MAX_OUTPUT_PORT_TYPE +readdata[15] <= readdata.DB_MAX_OUTPUT_PORT_TYPE +readdata[16] <= readdata.DB_MAX_OUTPUT_PORT_TYPE +readdata[17] <= readdata.DB_MAX_OUTPUT_PORT_TYPE +readdata[18] <= readdata.DB_MAX_OUTPUT_PORT_TYPE +readdata[19] <= readdata.DB_MAX_OUTPUT_PORT_TYPE +readdata[20] <= readdata.DB_MAX_OUTPUT_PORT_TYPE +readdata[21] <= readdata.DB_MAX_OUTPUT_PORT_TYPE +readdata[22] <= readdata.DB_MAX_OUTPUT_PORT_TYPE +readdata[23] <= readdata.DB_MAX_OUTPUT_PORT_TYPE +readdata[24] <= readdata.DB_MAX_OUTPUT_PORT_TYPE +readdata[25] <= readdata.DB_MAX_OUTPUT_PORT_TYPE +readdata[26] <= readdata.DB_MAX_OUTPUT_PORT_TYPE +readdata[27] <= readdata.DB_MAX_OUTPUT_PORT_TYPE +readdata[28] <= readdata.DB_MAX_OUTPUT_PORT_TYPE +readdata[29] <= readdata.DB_MAX_OUTPUT_PORT_TYPE +readdata[30] <= readdata.DB_MAX_OUTPUT_PORT_TYPE +readdata[31] <= readdata.DB_MAX_OUTPUT_PORT_TYPE +resetrequest <= resetrequest.DB_MAX_OUTPUT_PORT_TYPE + + +|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_debug:the_system_cpu_nios2_oci_debug +clk => monitor_go~reg0.CLK +clk => monitor_error~reg0.CLK +clk => monitor_ready~reg0.CLK +clk => resetlatch~reg0.CLK +clk => jtag_break.CLK +clk => resetrequest~reg0.CLK +clk => probepresent.CLK +dbrk_break => oci_hbreak_req.IN1 +debugreq => always0.IN0 +debugreq => oci_hbreak_req.IN1 +hbreak_enabled => always0.IN1 +hbreak_enabled => debugack.DATAIN +jdo[0] => ~NO_FANOUT~ +jdo[1] => ~NO_FANOUT~ +jdo[2] => ~NO_FANOUT~ +jdo[3] => ~NO_FANOUT~ +jdo[4] => ~NO_FANOUT~ +jdo[5] => ~NO_FANOUT~ +jdo[6] => ~NO_FANOUT~ +jdo[7] => ~NO_FANOUT~ +jdo[8] => ~NO_FANOUT~ +jdo[9] => ~NO_FANOUT~ +jdo[10] => ~NO_FANOUT~ +jdo[11] => ~NO_FANOUT~ +jdo[12] => ~NO_FANOUT~ +jdo[13] => ~NO_FANOUT~ +jdo[14] => ~NO_FANOUT~ +jdo[15] => ~NO_FANOUT~ +jdo[16] => ~NO_FANOUT~ +jdo[17] => ~NO_FANOUT~ +jdo[18] => probepresent.OUTPUTSELECT +jdo[19] => probepresent.OUTPUTSELECT +jdo[20] => jtag_break.OUTPUTSELECT +jdo[21] => jtag_break.OUTPUTSELECT +jdo[22] => resetrequest~reg0.DATAIN +jdo[23] => always1.IN0 +jdo[24] => resetlatch.OUTPUTSELECT +jdo[25] => always1.IN0 +jdo[26] => ~NO_FANOUT~ +jdo[27] => ~NO_FANOUT~ +jdo[28] => ~NO_FANOUT~ +jdo[29] => ~NO_FANOUT~ +jdo[30] => ~NO_FANOUT~ +jdo[31] => ~NO_FANOUT~ +jdo[32] => ~NO_FANOUT~ +jdo[33] => ~NO_FANOUT~ +jdo[34] => ~NO_FANOUT~ +jdo[35] => ~NO_FANOUT~ +jdo[36] => ~NO_FANOUT~ +jdo[37] => ~NO_FANOUT~ +jrst_n => monitor_go~reg0.ACLR +jrst_n => monitor_error~reg0.ACLR +jrst_n => monitor_ready~reg0.ACLR +jrst_n => jtag_break.ACLR +jrst_n => resetrequest~reg0.ACLR +jrst_n => probepresent.ACLR +jrst_n => resetlatch~reg0.ENA +ocireg_ers => always1.IN0 +ocireg_mrs => always1.IN0 +reset => jtag_break.OUTPUTSELECT +reset => resetlatch.OUTPUTSELECT +st_ready_test_idle => monitor_go.OUTPUTSELECT +take_action_ocimem_a => jtag_break.OUTPUTSELECT +take_action_ocimem_a => resetlatch.OUTPUTSELECT +take_action_ocimem_a => always1.IN1 +take_action_ocimem_a => always1.IN1 +take_action_ocimem_a => probepresent.ENA +take_action_ocimem_a => resetrequest~reg0.ENA +take_action_ocireg => always1.IN1 +take_action_ocireg => always1.IN1 +xbrk_break => oci_hbreak_req.IN1 +debugack <= hbreak_enabled.DB_MAX_OUTPUT_PORT_TYPE +monitor_error <= monitor_error~reg0.DB_MAX_OUTPUT_PORT_TYPE +monitor_go <= monitor_go~reg0.DB_MAX_OUTPUT_PORT_TYPE +monitor_ready <= monitor_ready~reg0.DB_MAX_OUTPUT_PORT_TYPE +oci_hbreak_req <= oci_hbreak_req.DB_MAX_OUTPUT_PORT_TYPE +resetlatch <= resetlatch~reg0.DB_MAX_OUTPUT_PORT_TYPE +resetrequest <= resetrequest~reg0.DB_MAX_OUTPUT_PORT_TYPE + + +|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem +address[0] => address[0].IN1 +address[1] => address[1].IN1 +address[2] => address[2].IN1 +address[3] => address[3].IN1 +address[4] => address[4].IN1 +address[5] => address[5].IN1 +address[6] => address[6].IN1 +address[7] => address[7].IN1 +address[8] => comb.IN1 +begintransfer => avalon.IN0 +byteenable[0] => byteenable[0].IN1 +byteenable[1] => byteenable[1].IN1 +byteenable[2] => byteenable[2].IN1 +byteenable[3] => byteenable[3].IN1 +chipselect => comb.IN0 +clk => clk.IN2 +debugaccess => comb.IN1 +jdo[0] => ~NO_FANOUT~ +jdo[1] => ~NO_FANOUT~ +jdo[2] => ~NO_FANOUT~ +jdo[3] => MonDReg.DATAB +jdo[4] => MonDReg.DATAB +jdo[5] => MonDReg.DATAB +jdo[6] => MonDReg.DATAB +jdo[7] => MonDReg.DATAB +jdo[8] => MonDReg.DATAB +jdo[9] => MonDReg.DATAB +jdo[10] => MonDReg.DATAB +jdo[11] => MonDReg.DATAB +jdo[12] => MonDReg.DATAB +jdo[13] => MonDReg.DATAB +jdo[14] => MonDReg.DATAB +jdo[15] => MonDReg.DATAB +jdo[16] => MonDReg.DATAB +jdo[17] => MonDReg.DATAB +jdo[17] => MonAReg.DATAB +jdo[18] => MonDReg.DATAB +jdo[19] => MonDReg.DATAB +jdo[20] => MonDReg.DATAB +jdo[21] => MonDReg.DATAB +jdo[22] => MonDReg.DATAB +jdo[23] => MonDReg.DATAB +jdo[24] => MonDReg.DATAB +jdo[25] => MonDReg.DATAB +jdo[26] => MonDReg.DATAB +jdo[26] => MonAReg.DATAB +jdo[27] => MonDReg.DATAB +jdo[27] => MonAReg.DATAB +jdo[28] => MonDReg.DATAB +jdo[28] => MonAReg.DATAB +jdo[29] => MonDReg.DATAB +jdo[29] => MonAReg.DATAB +jdo[30] => MonDReg.DATAB +jdo[30] => MonAReg.DATAB +jdo[31] => MonDReg.DATAB +jdo[31] => MonAReg.DATAB +jdo[32] => MonDReg.DATAB +jdo[32] => MonAReg.DATAB +jdo[33] => MonDReg.DATAB +jdo[33] => MonAReg.DATAB +jdo[34] => MonDReg.DATAB +jdo[35] => ~NO_FANOUT~ +jdo[36] => ~NO_FANOUT~ +jdo[37] => ~NO_FANOUT~ +jrst_n => MonDReg[0]~reg0.ACLR +jrst_n => MonDReg[1]~reg0.ACLR +jrst_n => MonDReg[2]~reg0.ACLR +jrst_n => MonDReg[3]~reg0.ACLR +jrst_n => MonDReg[4]~reg0.ACLR +jrst_n => MonDReg[5]~reg0.ACLR +jrst_n => MonDReg[6]~reg0.ACLR +jrst_n => MonDReg[7]~reg0.ACLR +jrst_n => MonDReg[8]~reg0.ACLR +jrst_n => MonDReg[9]~reg0.ACLR +jrst_n => MonDReg[10]~reg0.ACLR +jrst_n => MonDReg[11]~reg0.ACLR +jrst_n => MonDReg[12]~reg0.ACLR +jrst_n => MonDReg[13]~reg0.ACLR +jrst_n => MonDReg[14]~reg0.ACLR +jrst_n => MonDReg[15]~reg0.ACLR +jrst_n => MonDReg[16]~reg0.ACLR +jrst_n => MonDReg[17]~reg0.ACLR +jrst_n => MonDReg[18]~reg0.ACLR +jrst_n => MonDReg[19]~reg0.ACLR +jrst_n => MonDReg[20]~reg0.ACLR +jrst_n => MonDReg[21]~reg0.ACLR +jrst_n => MonDReg[22]~reg0.ACLR +jrst_n => MonDReg[23]~reg0.ACLR +jrst_n => MonDReg[24]~reg0.ACLR +jrst_n => MonDReg[25]~reg0.ACLR +jrst_n => MonDReg[26]~reg0.ACLR +jrst_n => MonDReg[27]~reg0.ACLR +jrst_n => MonDReg[28]~reg0.ACLR +jrst_n => MonDReg[29]~reg0.ACLR +jrst_n => MonDReg[30]~reg0.ACLR +jrst_n => MonDReg[31]~reg0.ACLR +jrst_n => MonAReg[2].ACLR +jrst_n => MonAReg[3].ACLR +jrst_n => MonAReg[4].ACLR +jrst_n => MonAReg[5].ACLR +jrst_n => MonAReg[6].ACLR +jrst_n => MonAReg[7].ACLR +jrst_n => MonAReg[8].ACLR +jrst_n => MonAReg[9].ACLR +jrst_n => MonAReg[10].ACLR +jrst_n => MonRd1.ACLR +jrst_n => MonRd.ACLR +jrst_n => MonWr.ACLR +resetrequest => avalon.IN1 +take_action_ocimem_a => MonAReg.OUTPUTSELECT +take_action_ocimem_a => MonAReg.OUTPUTSELECT +take_action_ocimem_a => MonAReg.OUTPUTSELECT +take_action_ocimem_a => MonAReg.OUTPUTSELECT +take_action_ocimem_a => MonAReg.OUTPUTSELECT +take_action_ocimem_a => MonAReg.OUTPUTSELECT +take_action_ocimem_a => MonAReg.OUTPUTSELECT +take_action_ocimem_a => MonAReg.OUTPUTSELECT +take_action_ocimem_a => MonAReg.OUTPUTSELECT +take_action_ocimem_a => MonRd.OUTPUTSELECT +take_action_ocimem_a => MonDReg.OUTPUTSELECT +take_action_ocimem_a => MonDReg.OUTPUTSELECT +take_action_ocimem_a => MonDReg.OUTPUTSELECT +take_action_ocimem_a => MonDReg.OUTPUTSELECT +take_action_ocimem_a => MonDReg.OUTPUTSELECT +take_action_ocimem_a => MonDReg.OUTPUTSELECT +take_action_ocimem_a => MonDReg.OUTPUTSELECT +take_action_ocimem_a => MonDReg.OUTPUTSELECT +take_action_ocimem_a => MonDReg.OUTPUTSELECT +take_action_ocimem_a => MonDReg.OUTPUTSELECT +take_action_ocimem_a => MonDReg.OUTPUTSELECT +take_action_ocimem_a => MonDReg.OUTPUTSELECT +take_action_ocimem_a => MonDReg.OUTPUTSELECT +take_action_ocimem_a => MonDReg.OUTPUTSELECT +take_action_ocimem_a => MonDReg.OUTPUTSELECT +take_action_ocimem_a => MonDReg.OUTPUTSELECT +take_action_ocimem_a => MonDReg.OUTPUTSELECT +take_action_ocimem_a => MonDReg.OUTPUTSELECT +take_action_ocimem_a => MonDReg.OUTPUTSELECT +take_action_ocimem_a => MonDReg.OUTPUTSELECT +take_action_ocimem_a => MonDReg.OUTPUTSELECT +take_action_ocimem_a => MonDReg.OUTPUTSELECT +take_action_ocimem_a => MonDReg.OUTPUTSELECT +take_action_ocimem_a => MonDReg.OUTPUTSELECT +take_action_ocimem_a => MonDReg.OUTPUTSELECT +take_action_ocimem_a => MonDReg.OUTPUTSELECT +take_action_ocimem_a => MonDReg.OUTPUTSELECT +take_action_ocimem_a => MonDReg.OUTPUTSELECT +take_action_ocimem_a => MonDReg.OUTPUTSELECT +take_action_ocimem_a => MonDReg.OUTPUTSELECT +take_action_ocimem_a => MonDReg.OUTPUTSELECT +take_action_ocimem_a => MonDReg.OUTPUTSELECT +take_action_ocimem_a => MonWr.OUTPUTSELECT +take_action_ocimem_b => MonAReg.OUTPUTSELECT +take_action_ocimem_b => MonAReg.OUTPUTSELECT +take_action_ocimem_b => MonAReg.OUTPUTSELECT +take_action_ocimem_b => MonAReg.OUTPUTSELECT +take_action_ocimem_b => MonAReg.OUTPUTSELECT +take_action_ocimem_b => MonAReg.OUTPUTSELECT +take_action_ocimem_b => MonAReg.OUTPUTSELECT +take_action_ocimem_b => MonAReg.OUTPUTSELECT +take_action_ocimem_b => MonAReg.OUTPUTSELECT +take_action_ocimem_b => MonDReg.OUTPUTSELECT +take_action_ocimem_b => MonDReg.OUTPUTSELECT +take_action_ocimem_b => MonDReg.OUTPUTSELECT +take_action_ocimem_b => MonDReg.OUTPUTSELECT +take_action_ocimem_b => MonDReg.OUTPUTSELECT +take_action_ocimem_b => MonDReg.OUTPUTSELECT +take_action_ocimem_b => MonDReg.OUTPUTSELECT +take_action_ocimem_b => MonDReg.OUTPUTSELECT +take_action_ocimem_b => MonDReg.OUTPUTSELECT +take_action_ocimem_b => MonDReg.OUTPUTSELECT +take_action_ocimem_b => MonDReg.OUTPUTSELECT +take_action_ocimem_b => MonDReg.OUTPUTSELECT +take_action_ocimem_b => MonDReg.OUTPUTSELECT +take_action_ocimem_b => MonDReg.OUTPUTSELECT +take_action_ocimem_b => MonDReg.OUTPUTSELECT +take_action_ocimem_b => MonDReg.OUTPUTSELECT +take_action_ocimem_b => MonDReg.OUTPUTSELECT +take_action_ocimem_b => MonDReg.OUTPUTSELECT +take_action_ocimem_b => MonDReg.OUTPUTSELECT +take_action_ocimem_b => MonDReg.OUTPUTSELECT +take_action_ocimem_b => MonDReg.OUTPUTSELECT +take_action_ocimem_b => MonDReg.OUTPUTSELECT +take_action_ocimem_b => MonDReg.OUTPUTSELECT +take_action_ocimem_b => MonDReg.OUTPUTSELECT +take_action_ocimem_b => MonDReg.OUTPUTSELECT +take_action_ocimem_b => MonDReg.OUTPUTSELECT +take_action_ocimem_b => MonDReg.OUTPUTSELECT +take_action_ocimem_b => MonDReg.OUTPUTSELECT +take_action_ocimem_b => MonDReg.OUTPUTSELECT +take_action_ocimem_b => MonDReg.OUTPUTSELECT +take_action_ocimem_b => MonDReg.OUTPUTSELECT +take_action_ocimem_b => MonDReg.OUTPUTSELECT +take_action_ocimem_b => MonWr.OUTPUTSELECT +take_action_ocimem_b => MonRd.OUTPUTSELECT +take_no_action_ocimem_a => MonAReg.OUTPUTSELECT +take_no_action_ocimem_a => MonAReg.OUTPUTSELECT +take_no_action_ocimem_a => MonAReg.OUTPUTSELECT +take_no_action_ocimem_a => MonAReg.OUTPUTSELECT +take_no_action_ocimem_a => MonAReg.OUTPUTSELECT +take_no_action_ocimem_a => MonAReg.OUTPUTSELECT +take_no_action_ocimem_a => MonAReg.OUTPUTSELECT +take_no_action_ocimem_a => MonAReg.OUTPUTSELECT +take_no_action_ocimem_a => MonAReg.OUTPUTSELECT +take_no_action_ocimem_a => MonRd.OUTPUTSELECT +take_no_action_ocimem_a => MonDReg.OUTPUTSELECT +take_no_action_ocimem_a => MonDReg.OUTPUTSELECT +take_no_action_ocimem_a => MonDReg.OUTPUTSELECT +take_no_action_ocimem_a => MonDReg.OUTPUTSELECT +take_no_action_ocimem_a => MonDReg.OUTPUTSELECT +take_no_action_ocimem_a => MonDReg.OUTPUTSELECT +take_no_action_ocimem_a => MonDReg.OUTPUTSELECT +take_no_action_ocimem_a => MonDReg.OUTPUTSELECT +take_no_action_ocimem_a => MonDReg.OUTPUTSELECT +take_no_action_ocimem_a => MonDReg.OUTPUTSELECT +take_no_action_ocimem_a => MonDReg.OUTPUTSELECT +take_no_action_ocimem_a => MonDReg.OUTPUTSELECT +take_no_action_ocimem_a => MonDReg.OUTPUTSELECT +take_no_action_ocimem_a => MonDReg.OUTPUTSELECT +take_no_action_ocimem_a => MonDReg.OUTPUTSELECT +take_no_action_ocimem_a => MonDReg.OUTPUTSELECT +take_no_action_ocimem_a => MonDReg.OUTPUTSELECT +take_no_action_ocimem_a => MonDReg.OUTPUTSELECT +take_no_action_ocimem_a => MonDReg.OUTPUTSELECT +take_no_action_ocimem_a => MonDReg.OUTPUTSELECT +take_no_action_ocimem_a => MonDReg.OUTPUTSELECT +take_no_action_ocimem_a => MonDReg.OUTPUTSELECT +take_no_action_ocimem_a => MonDReg.OUTPUTSELECT +take_no_action_ocimem_a => MonDReg.OUTPUTSELECT +take_no_action_ocimem_a => MonDReg.OUTPUTSELECT +take_no_action_ocimem_a => MonDReg.OUTPUTSELECT +take_no_action_ocimem_a => MonDReg.OUTPUTSELECT +take_no_action_ocimem_a => MonDReg.OUTPUTSELECT +take_no_action_ocimem_a => MonDReg.OUTPUTSELECT +take_no_action_ocimem_a => MonDReg.OUTPUTSELECT +take_no_action_ocimem_a => MonDReg.OUTPUTSELECT +take_no_action_ocimem_a => MonDReg.OUTPUTSELECT +take_no_action_ocimem_a => MonWr.OUTPUTSELECT +write => comb.IN1 +writedata[0] => writedata[0].IN1 +writedata[1] => writedata[1].IN1 +writedata[2] => writedata[2].IN1 +writedata[3] => writedata[3].IN1 +writedata[4] => writedata[4].IN1 +writedata[5] => writedata[5].IN1 +writedata[6] => writedata[6].IN1 +writedata[7] => writedata[7].IN1 +writedata[8] => writedata[8].IN1 +writedata[9] => writedata[9].IN1 +writedata[10] => writedata[10].IN1 +writedata[11] => writedata[11].IN1 +writedata[12] => writedata[12].IN1 +writedata[13] => writedata[13].IN1 +writedata[14] => writedata[14].IN1 +writedata[15] => writedata[15].IN1 +writedata[16] => writedata[16].IN1 +writedata[17] => writedata[17].IN1 +writedata[18] => writedata[18].IN1 +writedata[19] => writedata[19].IN1 +writedata[20] => writedata[20].IN1 +writedata[21] => writedata[21].IN1 +writedata[22] => writedata[22].IN1 +writedata[23] => writedata[23].IN1 +writedata[24] => writedata[24].IN1 +writedata[25] => writedata[25].IN1 +writedata[26] => writedata[26].IN1 +writedata[27] => writedata[27].IN1 +writedata[28] => writedata[28].IN1 +writedata[29] => writedata[29].IN1 +writedata[30] => writedata[30].IN1 +writedata[31] => writedata[31].IN1 +MonDReg[0] <= MonDReg[0].DB_MAX_OUTPUT_PORT_TYPE +MonDReg[1] <= MonDReg[1].DB_MAX_OUTPUT_PORT_TYPE +MonDReg[2] <= MonDReg[2].DB_MAX_OUTPUT_PORT_TYPE +MonDReg[3] <= MonDReg[3].DB_MAX_OUTPUT_PORT_TYPE +MonDReg[4] <= MonDReg[4].DB_MAX_OUTPUT_PORT_TYPE +MonDReg[5] <= MonDReg[5].DB_MAX_OUTPUT_PORT_TYPE +MonDReg[6] <= MonDReg[6].DB_MAX_OUTPUT_PORT_TYPE +MonDReg[7] <= MonDReg[7].DB_MAX_OUTPUT_PORT_TYPE +MonDReg[8] <= MonDReg[8].DB_MAX_OUTPUT_PORT_TYPE +MonDReg[9] <= MonDReg[9].DB_MAX_OUTPUT_PORT_TYPE +MonDReg[10] <= MonDReg[10].DB_MAX_OUTPUT_PORT_TYPE +MonDReg[11] <= MonDReg[11].DB_MAX_OUTPUT_PORT_TYPE +MonDReg[12] <= MonDReg[12].DB_MAX_OUTPUT_PORT_TYPE +MonDReg[13] <= MonDReg[13].DB_MAX_OUTPUT_PORT_TYPE +MonDReg[14] <= MonDReg[14].DB_MAX_OUTPUT_PORT_TYPE +MonDReg[15] <= MonDReg[15].DB_MAX_OUTPUT_PORT_TYPE +MonDReg[16] <= MonDReg[16].DB_MAX_OUTPUT_PORT_TYPE +MonDReg[17] <= MonDReg[17].DB_MAX_OUTPUT_PORT_TYPE +MonDReg[18] <= MonDReg[18].DB_MAX_OUTPUT_PORT_TYPE +MonDReg[19] <= MonDReg[19].DB_MAX_OUTPUT_PORT_TYPE +MonDReg[20] <= MonDReg[20].DB_MAX_OUTPUT_PORT_TYPE +MonDReg[21] <= MonDReg[21].DB_MAX_OUTPUT_PORT_TYPE +MonDReg[22] <= MonDReg[22].DB_MAX_OUTPUT_PORT_TYPE +MonDReg[23] <= MonDReg[23].DB_MAX_OUTPUT_PORT_TYPE +MonDReg[24] <= MonDReg[24].DB_MAX_OUTPUT_PORT_TYPE +MonDReg[25] <= MonDReg[25].DB_MAX_OUTPUT_PORT_TYPE +MonDReg[26] <= MonDReg[26].DB_MAX_OUTPUT_PORT_TYPE +MonDReg[27] <= MonDReg[27].DB_MAX_OUTPUT_PORT_TYPE +MonDReg[28] <= MonDReg[28].DB_MAX_OUTPUT_PORT_TYPE +MonDReg[29] <= MonDReg[29].DB_MAX_OUTPUT_PORT_TYPE +MonDReg[30] <= MonDReg[30].DB_MAX_OUTPUT_PORT_TYPE +MonDReg[31] <= MonDReg[31].DB_MAX_OUTPUT_PORT_TYPE +oci_ram_readdata[0] <= system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component.q_a +oci_ram_readdata[1] <= system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component.q_a +oci_ram_readdata[2] <= system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component.q_a +oci_ram_readdata[3] <= system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component.q_a +oci_ram_readdata[4] <= system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component.q_a +oci_ram_readdata[5] <= system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component.q_a +oci_ram_readdata[6] <= system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component.q_a +oci_ram_readdata[7] <= system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component.q_a +oci_ram_readdata[8] <= system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component.q_a +oci_ram_readdata[9] <= system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component.q_a +oci_ram_readdata[10] <= system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component.q_a +oci_ram_readdata[11] <= system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component.q_a +oci_ram_readdata[12] <= system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component.q_a +oci_ram_readdata[13] <= system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component.q_a +oci_ram_readdata[14] <= system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component.q_a +oci_ram_readdata[15] <= system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component.q_a +oci_ram_readdata[16] <= system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component.q_a +oci_ram_readdata[17] <= system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component.q_a +oci_ram_readdata[18] <= system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component.q_a +oci_ram_readdata[19] <= system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component.q_a +oci_ram_readdata[20] <= system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component.q_a +oci_ram_readdata[21] <= system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component.q_a +oci_ram_readdata[22] <= system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component.q_a +oci_ram_readdata[23] <= system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component.q_a +oci_ram_readdata[24] <= system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component.q_a +oci_ram_readdata[25] <= system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component.q_a +oci_ram_readdata[26] <= system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component.q_a +oci_ram_readdata[27] <= system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component.q_a +oci_ram_readdata[28] <= system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component.q_a +oci_ram_readdata[29] <= system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component.q_a +oci_ram_readdata[30] <= system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component.q_a +oci_ram_readdata[31] <= system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component.q_a + + +|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component +address_a[0] => address_a[0].IN1 +address_a[1] => address_a[1].IN1 +address_a[2] => address_a[2].IN1 +address_a[3] => address_a[3].IN1 +address_a[4] => address_a[4].IN1 +address_a[5] => address_a[5].IN1 +address_a[6] => address_a[6].IN1 +address_a[7] => address_a[7].IN1 +address_b[0] => address_b[0].IN1 +address_b[1] => address_b[1].IN1 +address_b[2] => address_b[2].IN1 +address_b[3] => address_b[3].IN1 +address_b[4] => address_b[4].IN1 +address_b[5] => address_b[5].IN1 +address_b[6] => address_b[6].IN1 +address_b[7] => address_b[7].IN1 +byteena_a[0] => byteena_a[0].IN1 +byteena_a[1] => byteena_a[1].IN1 +byteena_a[2] => byteena_a[2].IN1 +byteena_a[3] => byteena_a[3].IN1 +clock0 => clock0.IN1 +clock1 => clock1.IN1 +clocken0 => clocken0.IN1 +clocken1 => clocken1.IN1 +data_a[0] => data_a[0].IN1 +data_a[1] => data_a[1].IN1 +data_a[2] => data_a[2].IN1 +data_a[3] => data_a[3].IN1 +data_a[4] => data_a[4].IN1 +data_a[5] => data_a[5].IN1 +data_a[6] => data_a[6].IN1 +data_a[7] => data_a[7].IN1 +data_a[8] => data_a[8].IN1 +data_a[9] => data_a[9].IN1 +data_a[10] => data_a[10].IN1 +data_a[11] => data_a[11].IN1 +data_a[12] => data_a[12].IN1 +data_a[13] => data_a[13].IN1 +data_a[14] => data_a[14].IN1 +data_a[15] => data_a[15].IN1 +data_a[16] => data_a[16].IN1 +data_a[17] => data_a[17].IN1 +data_a[18] => data_a[18].IN1 +data_a[19] => data_a[19].IN1 +data_a[20] => data_a[20].IN1 +data_a[21] => data_a[21].IN1 +data_a[22] => data_a[22].IN1 +data_a[23] => data_a[23].IN1 +data_a[24] => data_a[24].IN1 +data_a[25] => data_a[25].IN1 +data_a[26] => data_a[26].IN1 +data_a[27] => data_a[27].IN1 +data_a[28] => data_a[28].IN1 +data_a[29] => data_a[29].IN1 +data_a[30] => data_a[30].IN1 +data_a[31] => data_a[31].IN1 +data_b[0] => data_b[0].IN1 +data_b[1] => data_b[1].IN1 +data_b[2] => data_b[2].IN1 +data_b[3] => data_b[3].IN1 +data_b[4] => data_b[4].IN1 +data_b[5] => data_b[5].IN1 +data_b[6] => data_b[6].IN1 +data_b[7] => data_b[7].IN1 +data_b[8] => data_b[8].IN1 +data_b[9] => data_b[9].IN1 +data_b[10] => data_b[10].IN1 +data_b[11] => data_b[11].IN1 +data_b[12] => data_b[12].IN1 +data_b[13] => data_b[13].IN1 +data_b[14] => data_b[14].IN1 +data_b[15] => data_b[15].IN1 +data_b[16] => data_b[16].IN1 +data_b[17] => data_b[17].IN1 +data_b[18] => data_b[18].IN1 +data_b[19] => data_b[19].IN1 +data_b[20] => data_b[20].IN1 +data_b[21] => data_b[21].IN1 +data_b[22] => data_b[22].IN1 +data_b[23] => data_b[23].IN1 +data_b[24] => data_b[24].IN1 +data_b[25] => data_b[25].IN1 +data_b[26] => data_b[26].IN1 +data_b[27] => data_b[27].IN1 +data_b[28] => data_b[28].IN1 +data_b[29] => data_b[29].IN1 +data_b[30] => data_b[30].IN1 +data_b[31] => data_b[31].IN1 +wren_a => wren_a.IN1 +wren_b => wren_b.IN1 +q_a[0] <= altsyncram:the_altsyncram.q_a +q_a[1] <= altsyncram:the_altsyncram.q_a +q_a[2] <= altsyncram:the_altsyncram.q_a +q_a[3] <= altsyncram:the_altsyncram.q_a +q_a[4] <= altsyncram:the_altsyncram.q_a +q_a[5] <= altsyncram:the_altsyncram.q_a +q_a[6] <= altsyncram:the_altsyncram.q_a +q_a[7] <= altsyncram:the_altsyncram.q_a +q_a[8] <= altsyncram:the_altsyncram.q_a +q_a[9] <= altsyncram:the_altsyncram.q_a +q_a[10] <= altsyncram:the_altsyncram.q_a +q_a[11] <= altsyncram:the_altsyncram.q_a +q_a[12] <= altsyncram:the_altsyncram.q_a +q_a[13] <= altsyncram:the_altsyncram.q_a +q_a[14] <= altsyncram:the_altsyncram.q_a +q_a[15] <= altsyncram:the_altsyncram.q_a +q_a[16] <= altsyncram:the_altsyncram.q_a +q_a[17] <= altsyncram:the_altsyncram.q_a +q_a[18] <= altsyncram:the_altsyncram.q_a +q_a[19] <= altsyncram:the_altsyncram.q_a +q_a[20] <= altsyncram:the_altsyncram.q_a +q_a[21] <= altsyncram:the_altsyncram.q_a +q_a[22] <= altsyncram:the_altsyncram.q_a +q_a[23] <= altsyncram:the_altsyncram.q_a +q_a[24] <= altsyncram:the_altsyncram.q_a +q_a[25] <= altsyncram:the_altsyncram.q_a +q_a[26] <= altsyncram:the_altsyncram.q_a +q_a[27] <= altsyncram:the_altsyncram.q_a +q_a[28] <= altsyncram:the_altsyncram.q_a +q_a[29] <= altsyncram:the_altsyncram.q_a +q_a[30] <= altsyncram:the_altsyncram.q_a +q_a[31] <= altsyncram:the_altsyncram.q_a +q_b[0] <= altsyncram:the_altsyncram.q_b +q_b[1] <= altsyncram:the_altsyncram.q_b +q_b[2] <= altsyncram:the_altsyncram.q_b +q_b[3] <= altsyncram:the_altsyncram.q_b +q_b[4] <= altsyncram:the_altsyncram.q_b +q_b[5] <= altsyncram:the_altsyncram.q_b +q_b[6] <= altsyncram:the_altsyncram.q_b +q_b[7] <= altsyncram:the_altsyncram.q_b +q_b[8] <= altsyncram:the_altsyncram.q_b +q_b[9] <= altsyncram:the_altsyncram.q_b +q_b[10] <= altsyncram:the_altsyncram.q_b +q_b[11] <= altsyncram:the_altsyncram.q_b +q_b[12] <= altsyncram:the_altsyncram.q_b +q_b[13] <= altsyncram:the_altsyncram.q_b +q_b[14] <= altsyncram:the_altsyncram.q_b +q_b[15] <= altsyncram:the_altsyncram.q_b +q_b[16] <= altsyncram:the_altsyncram.q_b +q_b[17] <= altsyncram:the_altsyncram.q_b +q_b[18] <= altsyncram:the_altsyncram.q_b +q_b[19] <= altsyncram:the_altsyncram.q_b +q_b[20] <= altsyncram:the_altsyncram.q_b +q_b[21] <= altsyncram:the_altsyncram.q_b +q_b[22] <= altsyncram:the_altsyncram.q_b +q_b[23] <= altsyncram:the_altsyncram.q_b +q_b[24] <= altsyncram:the_altsyncram.q_b +q_b[25] <= altsyncram:the_altsyncram.q_b +q_b[26] <= altsyncram:the_altsyncram.q_b +q_b[27] <= altsyncram:the_altsyncram.q_b +q_b[28] <= altsyncram:the_altsyncram.q_b +q_b[29] <= altsyncram:the_altsyncram.q_b +q_b[30] <= altsyncram:the_altsyncram.q_b +q_b[31] <= altsyncram:the_altsyncram.q_b + + +|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram +wren_a => altsyncram_jt72:auto_generated.wren_a +rden_a => ~NO_FANOUT~ +wren_b => altsyncram_jt72:auto_generated.wren_b +rden_b => ~NO_FANOUT~ +data_a[0] => altsyncram_jt72:auto_generated.data_a[0] +data_a[1] => altsyncram_jt72:auto_generated.data_a[1] +data_a[2] => altsyncram_jt72:auto_generated.data_a[2] +data_a[3] => altsyncram_jt72:auto_generated.data_a[3] +data_a[4] => altsyncram_jt72:auto_generated.data_a[4] +data_a[5] => altsyncram_jt72:auto_generated.data_a[5] +data_a[6] => altsyncram_jt72:auto_generated.data_a[6] +data_a[7] => altsyncram_jt72:auto_generated.data_a[7] +data_a[8] => altsyncram_jt72:auto_generated.data_a[8] +data_a[9] => altsyncram_jt72:auto_generated.data_a[9] +data_a[10] => altsyncram_jt72:auto_generated.data_a[10] +data_a[11] => altsyncram_jt72:auto_generated.data_a[11] +data_a[12] => altsyncram_jt72:auto_generated.data_a[12] +data_a[13] => altsyncram_jt72:auto_generated.data_a[13] +data_a[14] => altsyncram_jt72:auto_generated.data_a[14] +data_a[15] => altsyncram_jt72:auto_generated.data_a[15] +data_a[16] => altsyncram_jt72:auto_generated.data_a[16] +data_a[17] => altsyncram_jt72:auto_generated.data_a[17] +data_a[18] => altsyncram_jt72:auto_generated.data_a[18] +data_a[19] => altsyncram_jt72:auto_generated.data_a[19] +data_a[20] => altsyncram_jt72:auto_generated.data_a[20] +data_a[21] => altsyncram_jt72:auto_generated.data_a[21] +data_a[22] => altsyncram_jt72:auto_generated.data_a[22] +data_a[23] => altsyncram_jt72:auto_generated.data_a[23] +data_a[24] => altsyncram_jt72:auto_generated.data_a[24] +data_a[25] => altsyncram_jt72:auto_generated.data_a[25] +data_a[26] => altsyncram_jt72:auto_generated.data_a[26] +data_a[27] => altsyncram_jt72:auto_generated.data_a[27] +data_a[28] => altsyncram_jt72:auto_generated.data_a[28] +data_a[29] => altsyncram_jt72:auto_generated.data_a[29] +data_a[30] => altsyncram_jt72:auto_generated.data_a[30] +data_a[31] => altsyncram_jt72:auto_generated.data_a[31] +data_b[0] => altsyncram_jt72:auto_generated.data_b[0] +data_b[1] => altsyncram_jt72:auto_generated.data_b[1] +data_b[2] => altsyncram_jt72:auto_generated.data_b[2] +data_b[3] => altsyncram_jt72:auto_generated.data_b[3] +data_b[4] => altsyncram_jt72:auto_generated.data_b[4] +data_b[5] => altsyncram_jt72:auto_generated.data_b[5] +data_b[6] => altsyncram_jt72:auto_generated.data_b[6] +data_b[7] => altsyncram_jt72:auto_generated.data_b[7] +data_b[8] => altsyncram_jt72:auto_generated.data_b[8] +data_b[9] => altsyncram_jt72:auto_generated.data_b[9] +data_b[10] => altsyncram_jt72:auto_generated.data_b[10] +data_b[11] => altsyncram_jt72:auto_generated.data_b[11] +data_b[12] => altsyncram_jt72:auto_generated.data_b[12] +data_b[13] => altsyncram_jt72:auto_generated.data_b[13] +data_b[14] => altsyncram_jt72:auto_generated.data_b[14] +data_b[15] => altsyncram_jt72:auto_generated.data_b[15] +data_b[16] => altsyncram_jt72:auto_generated.data_b[16] +data_b[17] => altsyncram_jt72:auto_generated.data_b[17] +data_b[18] => altsyncram_jt72:auto_generated.data_b[18] +data_b[19] => altsyncram_jt72:auto_generated.data_b[19] +data_b[20] => altsyncram_jt72:auto_generated.data_b[20] +data_b[21] => altsyncram_jt72:auto_generated.data_b[21] +data_b[22] => altsyncram_jt72:auto_generated.data_b[22] +data_b[23] => altsyncram_jt72:auto_generated.data_b[23] +data_b[24] => altsyncram_jt72:auto_generated.data_b[24] +data_b[25] => altsyncram_jt72:auto_generated.data_b[25] +data_b[26] => altsyncram_jt72:auto_generated.data_b[26] +data_b[27] => altsyncram_jt72:auto_generated.data_b[27] +data_b[28] => altsyncram_jt72:auto_generated.data_b[28] +data_b[29] => altsyncram_jt72:auto_generated.data_b[29] +data_b[30] => altsyncram_jt72:auto_generated.data_b[30] +data_b[31] => altsyncram_jt72:auto_generated.data_b[31] +address_a[0] => altsyncram_jt72:auto_generated.address_a[0] +address_a[1] => altsyncram_jt72:auto_generated.address_a[1] +address_a[2] => altsyncram_jt72:auto_generated.address_a[2] +address_a[3] => altsyncram_jt72:auto_generated.address_a[3] +address_a[4] => altsyncram_jt72:auto_generated.address_a[4] +address_a[5] => altsyncram_jt72:auto_generated.address_a[5] +address_a[6] => altsyncram_jt72:auto_generated.address_a[6] +address_a[7] => altsyncram_jt72:auto_generated.address_a[7] +address_b[0] => altsyncram_jt72:auto_generated.address_b[0] +address_b[1] => altsyncram_jt72:auto_generated.address_b[1] +address_b[2] => altsyncram_jt72:auto_generated.address_b[2] +address_b[3] => altsyncram_jt72:auto_generated.address_b[3] +address_b[4] => altsyncram_jt72:auto_generated.address_b[4] +address_b[5] => altsyncram_jt72:auto_generated.address_b[5] +address_b[6] => altsyncram_jt72:auto_generated.address_b[6] +address_b[7] => altsyncram_jt72:auto_generated.address_b[7] +addressstall_a => ~NO_FANOUT~ +addressstall_b => ~NO_FANOUT~ +clock0 => altsyncram_jt72:auto_generated.clock0 +clock1 => altsyncram_jt72:auto_generated.clock1 +clocken0 => altsyncram_jt72:auto_generated.clocken0 +clocken1 => altsyncram_jt72:auto_generated.clocken1 +clocken2 => ~NO_FANOUT~ +clocken3 => ~NO_FANOUT~ +aclr0 => ~NO_FANOUT~ +aclr1 => ~NO_FANOUT~ +byteena_a[0] => altsyncram_jt72:auto_generated.byteena_a[0] +byteena_a[1] => altsyncram_jt72:auto_generated.byteena_a[1] +byteena_a[2] => altsyncram_jt72:auto_generated.byteena_a[2] +byteena_a[3] => altsyncram_jt72:auto_generated.byteena_a[3] +byteena_b[0] => ~NO_FANOUT~ +q_a[0] <= altsyncram_jt72:auto_generated.q_a[0] +q_a[1] <= altsyncram_jt72:auto_generated.q_a[1] +q_a[2] <= altsyncram_jt72:auto_generated.q_a[2] +q_a[3] <= altsyncram_jt72:auto_generated.q_a[3] +q_a[4] <= altsyncram_jt72:auto_generated.q_a[4] +q_a[5] <= altsyncram_jt72:auto_generated.q_a[5] +q_a[6] <= altsyncram_jt72:auto_generated.q_a[6] +q_a[7] <= altsyncram_jt72:auto_generated.q_a[7] +q_a[8] <= altsyncram_jt72:auto_generated.q_a[8] +q_a[9] <= altsyncram_jt72:auto_generated.q_a[9] +q_a[10] <= altsyncram_jt72:auto_generated.q_a[10] +q_a[11] <= altsyncram_jt72:auto_generated.q_a[11] +q_a[12] <= altsyncram_jt72:auto_generated.q_a[12] +q_a[13] <= altsyncram_jt72:auto_generated.q_a[13] +q_a[14] <= altsyncram_jt72:auto_generated.q_a[14] +q_a[15] <= altsyncram_jt72:auto_generated.q_a[15] +q_a[16] <= altsyncram_jt72:auto_generated.q_a[16] +q_a[17] <= altsyncram_jt72:auto_generated.q_a[17] +q_a[18] <= altsyncram_jt72:auto_generated.q_a[18] +q_a[19] <= altsyncram_jt72:auto_generated.q_a[19] +q_a[20] <= altsyncram_jt72:auto_generated.q_a[20] +q_a[21] <= altsyncram_jt72:auto_generated.q_a[21] +q_a[22] <= altsyncram_jt72:auto_generated.q_a[22] +q_a[23] <= altsyncram_jt72:auto_generated.q_a[23] +q_a[24] <= altsyncram_jt72:auto_generated.q_a[24] +q_a[25] <= altsyncram_jt72:auto_generated.q_a[25] +q_a[26] <= altsyncram_jt72:auto_generated.q_a[26] +q_a[27] <= altsyncram_jt72:auto_generated.q_a[27] +q_a[28] <= altsyncram_jt72:auto_generated.q_a[28] +q_a[29] <= altsyncram_jt72:auto_generated.q_a[29] +q_a[30] <= altsyncram_jt72:auto_generated.q_a[30] +q_a[31] <= altsyncram_jt72:auto_generated.q_a[31] +q_b[0] <= altsyncram_jt72:auto_generated.q_b[0] +q_b[1] <= altsyncram_jt72:auto_generated.q_b[1] +q_b[2] <= altsyncram_jt72:auto_generated.q_b[2] +q_b[3] <= altsyncram_jt72:auto_generated.q_b[3] +q_b[4] <= altsyncram_jt72:auto_generated.q_b[4] +q_b[5] <= altsyncram_jt72:auto_generated.q_b[5] +q_b[6] <= altsyncram_jt72:auto_generated.q_b[6] +q_b[7] <= altsyncram_jt72:auto_generated.q_b[7] +q_b[8] <= altsyncram_jt72:auto_generated.q_b[8] +q_b[9] <= altsyncram_jt72:auto_generated.q_b[9] +q_b[10] <= altsyncram_jt72:auto_generated.q_b[10] +q_b[11] <= altsyncram_jt72:auto_generated.q_b[11] +q_b[12] <= altsyncram_jt72:auto_generated.q_b[12] +q_b[13] <= altsyncram_jt72:auto_generated.q_b[13] +q_b[14] <= altsyncram_jt72:auto_generated.q_b[14] +q_b[15] <= altsyncram_jt72:auto_generated.q_b[15] +q_b[16] <= altsyncram_jt72:auto_generated.q_b[16] +q_b[17] <= altsyncram_jt72:auto_generated.q_b[17] +q_b[18] <= altsyncram_jt72:auto_generated.q_b[18] +q_b[19] <= altsyncram_jt72:auto_generated.q_b[19] +q_b[20] <= altsyncram_jt72:auto_generated.q_b[20] +q_b[21] <= altsyncram_jt72:auto_generated.q_b[21] +q_b[22] <= altsyncram_jt72:auto_generated.q_b[22] +q_b[23] <= altsyncram_jt72:auto_generated.q_b[23] +q_b[24] <= altsyncram_jt72:auto_generated.q_b[24] +q_b[25] <= altsyncram_jt72:auto_generated.q_b[25] +q_b[26] <= altsyncram_jt72:auto_generated.q_b[26] +q_b[27] <= altsyncram_jt72:auto_generated.q_b[27] +q_b[28] <= altsyncram_jt72:auto_generated.q_b[28] +q_b[29] <= altsyncram_jt72:auto_generated.q_b[29] +q_b[30] <= altsyncram_jt72:auto_generated.q_b[30] +q_b[31] <= altsyncram_jt72:auto_generated.q_b[31] +eccstatus[0] <= +eccstatus[1] <= +eccstatus[2] <= + + +|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated +address_a[0] => ram_block1a0.PORTAADDR +address_a[0] => ram_block1a1.PORTAADDR +address_a[0] => ram_block1a2.PORTAADDR +address_a[0] => ram_block1a3.PORTAADDR +address_a[0] => ram_block1a4.PORTAADDR +address_a[0] => ram_block1a5.PORTAADDR +address_a[0] => ram_block1a6.PORTAADDR +address_a[0] => ram_block1a7.PORTAADDR +address_a[0] => ram_block1a8.PORTAADDR +address_a[0] => ram_block1a9.PORTAADDR +address_a[0] => ram_block1a10.PORTAADDR +address_a[0] => ram_block1a11.PORTAADDR +address_a[0] => ram_block1a12.PORTAADDR +address_a[0] => ram_block1a13.PORTAADDR +address_a[0] => ram_block1a14.PORTAADDR +address_a[0] => ram_block1a15.PORTAADDR +address_a[0] => ram_block1a16.PORTAADDR +address_a[0] => ram_block1a17.PORTAADDR +address_a[0] => ram_block1a18.PORTAADDR +address_a[0] => ram_block1a19.PORTAADDR +address_a[0] => ram_block1a20.PORTAADDR +address_a[0] => ram_block1a21.PORTAADDR +address_a[0] => ram_block1a22.PORTAADDR +address_a[0] => ram_block1a23.PORTAADDR +address_a[0] => ram_block1a24.PORTAADDR +address_a[0] => ram_block1a25.PORTAADDR +address_a[0] => ram_block1a26.PORTAADDR +address_a[0] => ram_block1a27.PORTAADDR +address_a[0] => ram_block1a28.PORTAADDR +address_a[0] => ram_block1a29.PORTAADDR +address_a[0] => ram_block1a30.PORTAADDR +address_a[0] => ram_block1a31.PORTAADDR +address_a[1] => ram_block1a0.PORTAADDR1 +address_a[1] => ram_block1a1.PORTAADDR1 +address_a[1] => ram_block1a2.PORTAADDR1 +address_a[1] => ram_block1a3.PORTAADDR1 +address_a[1] => ram_block1a4.PORTAADDR1 +address_a[1] => ram_block1a5.PORTAADDR1 +address_a[1] => ram_block1a6.PORTAADDR1 +address_a[1] => ram_block1a7.PORTAADDR1 +address_a[1] => ram_block1a8.PORTAADDR1 +address_a[1] => ram_block1a9.PORTAADDR1 +address_a[1] => ram_block1a10.PORTAADDR1 +address_a[1] => ram_block1a11.PORTAADDR1 +address_a[1] => ram_block1a12.PORTAADDR1 +address_a[1] => ram_block1a13.PORTAADDR1 +address_a[1] => ram_block1a14.PORTAADDR1 +address_a[1] => ram_block1a15.PORTAADDR1 +address_a[1] => ram_block1a16.PORTAADDR1 +address_a[1] => ram_block1a17.PORTAADDR1 +address_a[1] => ram_block1a18.PORTAADDR1 +address_a[1] => ram_block1a19.PORTAADDR1 +address_a[1] => ram_block1a20.PORTAADDR1 +address_a[1] => ram_block1a21.PORTAADDR1 +address_a[1] => ram_block1a22.PORTAADDR1 +address_a[1] => ram_block1a23.PORTAADDR1 +address_a[1] => ram_block1a24.PORTAADDR1 +address_a[1] => ram_block1a25.PORTAADDR1 +address_a[1] => ram_block1a26.PORTAADDR1 +address_a[1] => ram_block1a27.PORTAADDR1 +address_a[1] => ram_block1a28.PORTAADDR1 +address_a[1] => ram_block1a29.PORTAADDR1 +address_a[1] => ram_block1a30.PORTAADDR1 +address_a[1] => ram_block1a31.PORTAADDR1 +address_a[2] => ram_block1a0.PORTAADDR2 +address_a[2] => ram_block1a1.PORTAADDR2 +address_a[2] => ram_block1a2.PORTAADDR2 +address_a[2] => ram_block1a3.PORTAADDR2 +address_a[2] => ram_block1a4.PORTAADDR2 +address_a[2] => ram_block1a5.PORTAADDR2 +address_a[2] => ram_block1a6.PORTAADDR2 +address_a[2] => ram_block1a7.PORTAADDR2 +address_a[2] => ram_block1a8.PORTAADDR2 +address_a[2] => ram_block1a9.PORTAADDR2 +address_a[2] => ram_block1a10.PORTAADDR2 +address_a[2] => ram_block1a11.PORTAADDR2 +address_a[2] => ram_block1a12.PORTAADDR2 +address_a[2] => ram_block1a13.PORTAADDR2 +address_a[2] => ram_block1a14.PORTAADDR2 +address_a[2] => ram_block1a15.PORTAADDR2 +address_a[2] => ram_block1a16.PORTAADDR2 +address_a[2] => ram_block1a17.PORTAADDR2 +address_a[2] => ram_block1a18.PORTAADDR2 +address_a[2] => ram_block1a19.PORTAADDR2 +address_a[2] => ram_block1a20.PORTAADDR2 +address_a[2] => ram_block1a21.PORTAADDR2 +address_a[2] => ram_block1a22.PORTAADDR2 +address_a[2] => ram_block1a23.PORTAADDR2 +address_a[2] => ram_block1a24.PORTAADDR2 +address_a[2] => ram_block1a25.PORTAADDR2 +address_a[2] => ram_block1a26.PORTAADDR2 +address_a[2] => ram_block1a27.PORTAADDR2 +address_a[2] => ram_block1a28.PORTAADDR2 +address_a[2] => ram_block1a29.PORTAADDR2 +address_a[2] => ram_block1a30.PORTAADDR2 +address_a[2] => ram_block1a31.PORTAADDR2 +address_a[3] => ram_block1a0.PORTAADDR3 +address_a[3] => ram_block1a1.PORTAADDR3 +address_a[3] => ram_block1a2.PORTAADDR3 +address_a[3] => ram_block1a3.PORTAADDR3 +address_a[3] => ram_block1a4.PORTAADDR3 +address_a[3] => ram_block1a5.PORTAADDR3 +address_a[3] => ram_block1a6.PORTAADDR3 +address_a[3] => ram_block1a7.PORTAADDR3 +address_a[3] => ram_block1a8.PORTAADDR3 +address_a[3] => ram_block1a9.PORTAADDR3 +address_a[3] => ram_block1a10.PORTAADDR3 +address_a[3] => ram_block1a11.PORTAADDR3 +address_a[3] => ram_block1a12.PORTAADDR3 +address_a[3] => ram_block1a13.PORTAADDR3 +address_a[3] => ram_block1a14.PORTAADDR3 +address_a[3] => ram_block1a15.PORTAADDR3 +address_a[3] => ram_block1a16.PORTAADDR3 +address_a[3] => ram_block1a17.PORTAADDR3 +address_a[3] => ram_block1a18.PORTAADDR3 +address_a[3] => ram_block1a19.PORTAADDR3 +address_a[3] => ram_block1a20.PORTAADDR3 +address_a[3] => ram_block1a21.PORTAADDR3 +address_a[3] => ram_block1a22.PORTAADDR3 +address_a[3] => ram_block1a23.PORTAADDR3 +address_a[3] => ram_block1a24.PORTAADDR3 +address_a[3] => ram_block1a25.PORTAADDR3 +address_a[3] => ram_block1a26.PORTAADDR3 +address_a[3] => ram_block1a27.PORTAADDR3 +address_a[3] => ram_block1a28.PORTAADDR3 +address_a[3] => ram_block1a29.PORTAADDR3 +address_a[3] => ram_block1a30.PORTAADDR3 +address_a[3] => ram_block1a31.PORTAADDR3 +address_a[4] => ram_block1a0.PORTAADDR4 +address_a[4] => ram_block1a1.PORTAADDR4 +address_a[4] => ram_block1a2.PORTAADDR4 +address_a[4] => ram_block1a3.PORTAADDR4 +address_a[4] => ram_block1a4.PORTAADDR4 +address_a[4] => ram_block1a5.PORTAADDR4 +address_a[4] => ram_block1a6.PORTAADDR4 +address_a[4] => ram_block1a7.PORTAADDR4 +address_a[4] => ram_block1a8.PORTAADDR4 +address_a[4] => ram_block1a9.PORTAADDR4 +address_a[4] => ram_block1a10.PORTAADDR4 +address_a[4] => ram_block1a11.PORTAADDR4 +address_a[4] => ram_block1a12.PORTAADDR4 +address_a[4] => ram_block1a13.PORTAADDR4 +address_a[4] => ram_block1a14.PORTAADDR4 +address_a[4] => ram_block1a15.PORTAADDR4 +address_a[4] => ram_block1a16.PORTAADDR4 +address_a[4] => ram_block1a17.PORTAADDR4 +address_a[4] => ram_block1a18.PORTAADDR4 +address_a[4] => ram_block1a19.PORTAADDR4 +address_a[4] => ram_block1a20.PORTAADDR4 +address_a[4] => ram_block1a21.PORTAADDR4 +address_a[4] => ram_block1a22.PORTAADDR4 +address_a[4] => ram_block1a23.PORTAADDR4 +address_a[4] => ram_block1a24.PORTAADDR4 +address_a[4] => ram_block1a25.PORTAADDR4 +address_a[4] => ram_block1a26.PORTAADDR4 +address_a[4] => ram_block1a27.PORTAADDR4 +address_a[4] => ram_block1a28.PORTAADDR4 +address_a[4] => ram_block1a29.PORTAADDR4 +address_a[4] => ram_block1a30.PORTAADDR4 +address_a[4] => ram_block1a31.PORTAADDR4 +address_a[5] => ram_block1a0.PORTAADDR5 +address_a[5] => ram_block1a1.PORTAADDR5 +address_a[5] => ram_block1a2.PORTAADDR5 +address_a[5] => ram_block1a3.PORTAADDR5 +address_a[5] => ram_block1a4.PORTAADDR5 +address_a[5] => ram_block1a5.PORTAADDR5 +address_a[5] => ram_block1a6.PORTAADDR5 +address_a[5] => ram_block1a7.PORTAADDR5 +address_a[5] => ram_block1a8.PORTAADDR5 +address_a[5] => ram_block1a9.PORTAADDR5 +address_a[5] => ram_block1a10.PORTAADDR5 +address_a[5] => ram_block1a11.PORTAADDR5 +address_a[5] => ram_block1a12.PORTAADDR5 +address_a[5] => ram_block1a13.PORTAADDR5 +address_a[5] => ram_block1a14.PORTAADDR5 +address_a[5] => ram_block1a15.PORTAADDR5 +address_a[5] => ram_block1a16.PORTAADDR5 +address_a[5] => ram_block1a17.PORTAADDR5 +address_a[5] => ram_block1a18.PORTAADDR5 +address_a[5] => ram_block1a19.PORTAADDR5 +address_a[5] => ram_block1a20.PORTAADDR5 +address_a[5] => ram_block1a21.PORTAADDR5 +address_a[5] => ram_block1a22.PORTAADDR5 +address_a[5] => ram_block1a23.PORTAADDR5 +address_a[5] => ram_block1a24.PORTAADDR5 +address_a[5] => ram_block1a25.PORTAADDR5 +address_a[5] => ram_block1a26.PORTAADDR5 +address_a[5] => ram_block1a27.PORTAADDR5 +address_a[5] => ram_block1a28.PORTAADDR5 +address_a[5] => ram_block1a29.PORTAADDR5 +address_a[5] => ram_block1a30.PORTAADDR5 +address_a[5] => ram_block1a31.PORTAADDR5 +address_a[6] => ram_block1a0.PORTAADDR6 +address_a[6] => ram_block1a1.PORTAADDR6 +address_a[6] => ram_block1a2.PORTAADDR6 +address_a[6] => ram_block1a3.PORTAADDR6 +address_a[6] => ram_block1a4.PORTAADDR6 +address_a[6] => ram_block1a5.PORTAADDR6 +address_a[6] => ram_block1a6.PORTAADDR6 +address_a[6] => ram_block1a7.PORTAADDR6 +address_a[6] => ram_block1a8.PORTAADDR6 +address_a[6] => ram_block1a9.PORTAADDR6 +address_a[6] => ram_block1a10.PORTAADDR6 +address_a[6] => ram_block1a11.PORTAADDR6 +address_a[6] => ram_block1a12.PORTAADDR6 +address_a[6] => ram_block1a13.PORTAADDR6 +address_a[6] => ram_block1a14.PORTAADDR6 +address_a[6] => ram_block1a15.PORTAADDR6 +address_a[6] => ram_block1a16.PORTAADDR6 +address_a[6] => ram_block1a17.PORTAADDR6 +address_a[6] => ram_block1a18.PORTAADDR6 +address_a[6] => ram_block1a19.PORTAADDR6 +address_a[6] => ram_block1a20.PORTAADDR6 +address_a[6] => ram_block1a21.PORTAADDR6 +address_a[6] => ram_block1a22.PORTAADDR6 +address_a[6] => ram_block1a23.PORTAADDR6 +address_a[6] => ram_block1a24.PORTAADDR6 +address_a[6] => ram_block1a25.PORTAADDR6 +address_a[6] => ram_block1a26.PORTAADDR6 +address_a[6] => ram_block1a27.PORTAADDR6 +address_a[6] => ram_block1a28.PORTAADDR6 +address_a[6] => ram_block1a29.PORTAADDR6 +address_a[6] => ram_block1a30.PORTAADDR6 +address_a[6] => ram_block1a31.PORTAADDR6 +address_a[7] => ram_block1a0.PORTAADDR7 +address_a[7] => ram_block1a1.PORTAADDR7 +address_a[7] => ram_block1a2.PORTAADDR7 +address_a[7] => ram_block1a3.PORTAADDR7 +address_a[7] => ram_block1a4.PORTAADDR7 +address_a[7] => ram_block1a5.PORTAADDR7 +address_a[7] => ram_block1a6.PORTAADDR7 +address_a[7] => ram_block1a7.PORTAADDR7 +address_a[7] => ram_block1a8.PORTAADDR7 +address_a[7] => ram_block1a9.PORTAADDR7 +address_a[7] => ram_block1a10.PORTAADDR7 +address_a[7] => ram_block1a11.PORTAADDR7 +address_a[7] => ram_block1a12.PORTAADDR7 +address_a[7] => ram_block1a13.PORTAADDR7 +address_a[7] => ram_block1a14.PORTAADDR7 +address_a[7] => ram_block1a15.PORTAADDR7 +address_a[7] => ram_block1a16.PORTAADDR7 +address_a[7] => ram_block1a17.PORTAADDR7 +address_a[7] => ram_block1a18.PORTAADDR7 +address_a[7] => ram_block1a19.PORTAADDR7 +address_a[7] => ram_block1a20.PORTAADDR7 +address_a[7] => ram_block1a21.PORTAADDR7 +address_a[7] => ram_block1a22.PORTAADDR7 +address_a[7] => ram_block1a23.PORTAADDR7 +address_a[7] => ram_block1a24.PORTAADDR7 +address_a[7] => ram_block1a25.PORTAADDR7 +address_a[7] => ram_block1a26.PORTAADDR7 +address_a[7] => ram_block1a27.PORTAADDR7 +address_a[7] => ram_block1a28.PORTAADDR7 +address_a[7] => ram_block1a29.PORTAADDR7 +address_a[7] => ram_block1a30.PORTAADDR7 +address_a[7] => ram_block1a31.PORTAADDR7 +address_b[0] => ram_block1a0.PORTBADDR +address_b[0] => ram_block1a1.PORTBADDR +address_b[0] => ram_block1a2.PORTBADDR +address_b[0] => ram_block1a3.PORTBADDR +address_b[0] => ram_block1a4.PORTBADDR +address_b[0] => ram_block1a5.PORTBADDR +address_b[0] => ram_block1a6.PORTBADDR +address_b[0] => ram_block1a7.PORTBADDR +address_b[0] => ram_block1a8.PORTBADDR +address_b[0] => ram_block1a9.PORTBADDR +address_b[0] => ram_block1a10.PORTBADDR +address_b[0] => ram_block1a11.PORTBADDR +address_b[0] => ram_block1a12.PORTBADDR +address_b[0] => ram_block1a13.PORTBADDR +address_b[0] => ram_block1a14.PORTBADDR +address_b[0] => ram_block1a15.PORTBADDR +address_b[0] => ram_block1a16.PORTBADDR +address_b[0] => ram_block1a17.PORTBADDR +address_b[0] => ram_block1a18.PORTBADDR +address_b[0] => ram_block1a19.PORTBADDR +address_b[0] => ram_block1a20.PORTBADDR +address_b[0] => ram_block1a21.PORTBADDR +address_b[0] => ram_block1a22.PORTBADDR +address_b[0] => ram_block1a23.PORTBADDR +address_b[0] => ram_block1a24.PORTBADDR +address_b[0] => ram_block1a25.PORTBADDR +address_b[0] => ram_block1a26.PORTBADDR +address_b[0] => ram_block1a27.PORTBADDR +address_b[0] => ram_block1a28.PORTBADDR +address_b[0] => ram_block1a29.PORTBADDR +address_b[0] => ram_block1a30.PORTBADDR +address_b[0] => ram_block1a31.PORTBADDR +address_b[1] => ram_block1a0.PORTBADDR1 +address_b[1] => ram_block1a1.PORTBADDR1 +address_b[1] => ram_block1a2.PORTBADDR1 +address_b[1] => ram_block1a3.PORTBADDR1 +address_b[1] => ram_block1a4.PORTBADDR1 +address_b[1] => ram_block1a5.PORTBADDR1 +address_b[1] => ram_block1a6.PORTBADDR1 +address_b[1] => ram_block1a7.PORTBADDR1 +address_b[1] => ram_block1a8.PORTBADDR1 +address_b[1] => ram_block1a9.PORTBADDR1 +address_b[1] => ram_block1a10.PORTBADDR1 +address_b[1] => ram_block1a11.PORTBADDR1 +address_b[1] => ram_block1a12.PORTBADDR1 +address_b[1] => ram_block1a13.PORTBADDR1 +address_b[1] => ram_block1a14.PORTBADDR1 +address_b[1] => ram_block1a15.PORTBADDR1 +address_b[1] => ram_block1a16.PORTBADDR1 +address_b[1] => ram_block1a17.PORTBADDR1 +address_b[1] => ram_block1a18.PORTBADDR1 +address_b[1] => ram_block1a19.PORTBADDR1 +address_b[1] => ram_block1a20.PORTBADDR1 +address_b[1] => ram_block1a21.PORTBADDR1 +address_b[1] => ram_block1a22.PORTBADDR1 +address_b[1] => ram_block1a23.PORTBADDR1 +address_b[1] => ram_block1a24.PORTBADDR1 +address_b[1] => ram_block1a25.PORTBADDR1 +address_b[1] => ram_block1a26.PORTBADDR1 +address_b[1] => ram_block1a27.PORTBADDR1 +address_b[1] => ram_block1a28.PORTBADDR1 +address_b[1] => ram_block1a29.PORTBADDR1 +address_b[1] => ram_block1a30.PORTBADDR1 +address_b[1] => ram_block1a31.PORTBADDR1 +address_b[2] => ram_block1a0.PORTBADDR2 +address_b[2] => ram_block1a1.PORTBADDR2 +address_b[2] => ram_block1a2.PORTBADDR2 +address_b[2] => ram_block1a3.PORTBADDR2 +address_b[2] => ram_block1a4.PORTBADDR2 +address_b[2] => ram_block1a5.PORTBADDR2 +address_b[2] => ram_block1a6.PORTBADDR2 +address_b[2] => ram_block1a7.PORTBADDR2 +address_b[2] => ram_block1a8.PORTBADDR2 +address_b[2] => ram_block1a9.PORTBADDR2 +address_b[2] => ram_block1a10.PORTBADDR2 +address_b[2] => ram_block1a11.PORTBADDR2 +address_b[2] => ram_block1a12.PORTBADDR2 +address_b[2] => ram_block1a13.PORTBADDR2 +address_b[2] => ram_block1a14.PORTBADDR2 +address_b[2] => ram_block1a15.PORTBADDR2 +address_b[2] => ram_block1a16.PORTBADDR2 +address_b[2] => ram_block1a17.PORTBADDR2 +address_b[2] => ram_block1a18.PORTBADDR2 +address_b[2] => ram_block1a19.PORTBADDR2 +address_b[2] => ram_block1a20.PORTBADDR2 +address_b[2] => ram_block1a21.PORTBADDR2 +address_b[2] => ram_block1a22.PORTBADDR2 +address_b[2] => ram_block1a23.PORTBADDR2 +address_b[2] => ram_block1a24.PORTBADDR2 +address_b[2] => ram_block1a25.PORTBADDR2 +address_b[2] => ram_block1a26.PORTBADDR2 +address_b[2] => ram_block1a27.PORTBADDR2 +address_b[2] => ram_block1a28.PORTBADDR2 +address_b[2] => ram_block1a29.PORTBADDR2 +address_b[2] => ram_block1a30.PORTBADDR2 +address_b[2] => ram_block1a31.PORTBADDR2 +address_b[3] => ram_block1a0.PORTBADDR3 +address_b[3] => ram_block1a1.PORTBADDR3 +address_b[3] => ram_block1a2.PORTBADDR3 +address_b[3] => ram_block1a3.PORTBADDR3 +address_b[3] => ram_block1a4.PORTBADDR3 +address_b[3] => ram_block1a5.PORTBADDR3 +address_b[3] => ram_block1a6.PORTBADDR3 +address_b[3] => ram_block1a7.PORTBADDR3 +address_b[3] => ram_block1a8.PORTBADDR3 +address_b[3] => ram_block1a9.PORTBADDR3 +address_b[3] => ram_block1a10.PORTBADDR3 +address_b[3] => ram_block1a11.PORTBADDR3 +address_b[3] => ram_block1a12.PORTBADDR3 +address_b[3] => ram_block1a13.PORTBADDR3 +address_b[3] => ram_block1a14.PORTBADDR3 +address_b[3] => ram_block1a15.PORTBADDR3 +address_b[3] => ram_block1a16.PORTBADDR3 +address_b[3] => ram_block1a17.PORTBADDR3 +address_b[3] => ram_block1a18.PORTBADDR3 +address_b[3] => ram_block1a19.PORTBADDR3 +address_b[3] => ram_block1a20.PORTBADDR3 +address_b[3] => ram_block1a21.PORTBADDR3 +address_b[3] => ram_block1a22.PORTBADDR3 +address_b[3] => ram_block1a23.PORTBADDR3 +address_b[3] => ram_block1a24.PORTBADDR3 +address_b[3] => ram_block1a25.PORTBADDR3 +address_b[3] => ram_block1a26.PORTBADDR3 +address_b[3] => ram_block1a27.PORTBADDR3 +address_b[3] => ram_block1a28.PORTBADDR3 +address_b[3] => ram_block1a29.PORTBADDR3 +address_b[3] => ram_block1a30.PORTBADDR3 +address_b[3] => ram_block1a31.PORTBADDR3 +address_b[4] => ram_block1a0.PORTBADDR4 +address_b[4] => ram_block1a1.PORTBADDR4 +address_b[4] => ram_block1a2.PORTBADDR4 +address_b[4] => ram_block1a3.PORTBADDR4 +address_b[4] => ram_block1a4.PORTBADDR4 +address_b[4] => ram_block1a5.PORTBADDR4 +address_b[4] => ram_block1a6.PORTBADDR4 +address_b[4] => ram_block1a7.PORTBADDR4 +address_b[4] => ram_block1a8.PORTBADDR4 +address_b[4] => ram_block1a9.PORTBADDR4 +address_b[4] => ram_block1a10.PORTBADDR4 +address_b[4] => ram_block1a11.PORTBADDR4 +address_b[4] => ram_block1a12.PORTBADDR4 +address_b[4] => ram_block1a13.PORTBADDR4 +address_b[4] => ram_block1a14.PORTBADDR4 +address_b[4] => ram_block1a15.PORTBADDR4 +address_b[4] => ram_block1a16.PORTBADDR4 +address_b[4] => ram_block1a17.PORTBADDR4 +address_b[4] => ram_block1a18.PORTBADDR4 +address_b[4] => ram_block1a19.PORTBADDR4 +address_b[4] => ram_block1a20.PORTBADDR4 +address_b[4] => ram_block1a21.PORTBADDR4 +address_b[4] => ram_block1a22.PORTBADDR4 +address_b[4] => ram_block1a23.PORTBADDR4 +address_b[4] => ram_block1a24.PORTBADDR4 +address_b[4] => ram_block1a25.PORTBADDR4 +address_b[4] => ram_block1a26.PORTBADDR4 +address_b[4] => ram_block1a27.PORTBADDR4 +address_b[4] => ram_block1a28.PORTBADDR4 +address_b[4] => ram_block1a29.PORTBADDR4 +address_b[4] => ram_block1a30.PORTBADDR4 +address_b[4] => ram_block1a31.PORTBADDR4 +address_b[5] => ram_block1a0.PORTBADDR5 +address_b[5] => ram_block1a1.PORTBADDR5 +address_b[5] => ram_block1a2.PORTBADDR5 +address_b[5] => ram_block1a3.PORTBADDR5 +address_b[5] => ram_block1a4.PORTBADDR5 +address_b[5] => ram_block1a5.PORTBADDR5 +address_b[5] => ram_block1a6.PORTBADDR5 +address_b[5] => ram_block1a7.PORTBADDR5 +address_b[5] => ram_block1a8.PORTBADDR5 +address_b[5] => ram_block1a9.PORTBADDR5 +address_b[5] => ram_block1a10.PORTBADDR5 +address_b[5] => ram_block1a11.PORTBADDR5 +address_b[5] => ram_block1a12.PORTBADDR5 +address_b[5] => ram_block1a13.PORTBADDR5 +address_b[5] => ram_block1a14.PORTBADDR5 +address_b[5] => ram_block1a15.PORTBADDR5 +address_b[5] => ram_block1a16.PORTBADDR5 +address_b[5] => ram_block1a17.PORTBADDR5 +address_b[5] => ram_block1a18.PORTBADDR5 +address_b[5] => ram_block1a19.PORTBADDR5 +address_b[5] => ram_block1a20.PORTBADDR5 +address_b[5] => ram_block1a21.PORTBADDR5 +address_b[5] => ram_block1a22.PORTBADDR5 +address_b[5] => ram_block1a23.PORTBADDR5 +address_b[5] => ram_block1a24.PORTBADDR5 +address_b[5] => ram_block1a25.PORTBADDR5 +address_b[5] => ram_block1a26.PORTBADDR5 +address_b[5] => ram_block1a27.PORTBADDR5 +address_b[5] => ram_block1a28.PORTBADDR5 +address_b[5] => ram_block1a29.PORTBADDR5 +address_b[5] => ram_block1a30.PORTBADDR5 +address_b[5] => ram_block1a31.PORTBADDR5 +address_b[6] => ram_block1a0.PORTBADDR6 +address_b[6] => ram_block1a1.PORTBADDR6 +address_b[6] => ram_block1a2.PORTBADDR6 +address_b[6] => ram_block1a3.PORTBADDR6 +address_b[6] => ram_block1a4.PORTBADDR6 +address_b[6] => ram_block1a5.PORTBADDR6 +address_b[6] => ram_block1a6.PORTBADDR6 +address_b[6] => ram_block1a7.PORTBADDR6 +address_b[6] => ram_block1a8.PORTBADDR6 +address_b[6] => ram_block1a9.PORTBADDR6 +address_b[6] => ram_block1a10.PORTBADDR6 +address_b[6] => ram_block1a11.PORTBADDR6 +address_b[6] => ram_block1a12.PORTBADDR6 +address_b[6] => ram_block1a13.PORTBADDR6 +address_b[6] => ram_block1a14.PORTBADDR6 +address_b[6] => ram_block1a15.PORTBADDR6 +address_b[6] => ram_block1a16.PORTBADDR6 +address_b[6] => ram_block1a17.PORTBADDR6 +address_b[6] => ram_block1a18.PORTBADDR6 +address_b[6] => ram_block1a19.PORTBADDR6 +address_b[6] => ram_block1a20.PORTBADDR6 +address_b[6] => ram_block1a21.PORTBADDR6 +address_b[6] => ram_block1a22.PORTBADDR6 +address_b[6] => ram_block1a23.PORTBADDR6 +address_b[6] => ram_block1a24.PORTBADDR6 +address_b[6] => ram_block1a25.PORTBADDR6 +address_b[6] => ram_block1a26.PORTBADDR6 +address_b[6] => ram_block1a27.PORTBADDR6 +address_b[6] => ram_block1a28.PORTBADDR6 +address_b[6] => ram_block1a29.PORTBADDR6 +address_b[6] => ram_block1a30.PORTBADDR6 +address_b[6] => ram_block1a31.PORTBADDR6 +address_b[7] => ram_block1a0.PORTBADDR7 +address_b[7] => ram_block1a1.PORTBADDR7 +address_b[7] => ram_block1a2.PORTBADDR7 +address_b[7] => ram_block1a3.PORTBADDR7 +address_b[7] => ram_block1a4.PORTBADDR7 +address_b[7] => ram_block1a5.PORTBADDR7 +address_b[7] => ram_block1a6.PORTBADDR7 +address_b[7] => ram_block1a7.PORTBADDR7 +address_b[7] => ram_block1a8.PORTBADDR7 +address_b[7] => ram_block1a9.PORTBADDR7 +address_b[7] => ram_block1a10.PORTBADDR7 +address_b[7] => ram_block1a11.PORTBADDR7 +address_b[7] => ram_block1a12.PORTBADDR7 +address_b[7] => ram_block1a13.PORTBADDR7 +address_b[7] => ram_block1a14.PORTBADDR7 +address_b[7] => ram_block1a15.PORTBADDR7 +address_b[7] => ram_block1a16.PORTBADDR7 +address_b[7] => ram_block1a17.PORTBADDR7 +address_b[7] => ram_block1a18.PORTBADDR7 +address_b[7] => ram_block1a19.PORTBADDR7 +address_b[7] => ram_block1a20.PORTBADDR7 +address_b[7] => ram_block1a21.PORTBADDR7 +address_b[7] => ram_block1a22.PORTBADDR7 +address_b[7] => ram_block1a23.PORTBADDR7 +address_b[7] => ram_block1a24.PORTBADDR7 +address_b[7] => ram_block1a25.PORTBADDR7 +address_b[7] => ram_block1a26.PORTBADDR7 +address_b[7] => ram_block1a27.PORTBADDR7 +address_b[7] => ram_block1a28.PORTBADDR7 +address_b[7] => ram_block1a29.PORTBADDR7 +address_b[7] => ram_block1a30.PORTBADDR7 +address_b[7] => ram_block1a31.PORTBADDR7 +byteena_a[0] => ram_block1a0.PORTABYTEENAMASKS +byteena_a[0] => ram_block1a1.PORTABYTEENAMASKS +byteena_a[0] => ram_block1a2.PORTABYTEENAMASKS +byteena_a[0] => ram_block1a3.PORTABYTEENAMASKS +byteena_a[0] => ram_block1a4.PORTABYTEENAMASKS +byteena_a[0] => ram_block1a5.PORTABYTEENAMASKS +byteena_a[0] => ram_block1a6.PORTABYTEENAMASKS +byteena_a[0] => ram_block1a7.PORTABYTEENAMASKS +byteena_a[1] => ram_block1a8.PORTABYTEENAMASKS +byteena_a[1] => ram_block1a9.PORTABYTEENAMASKS +byteena_a[1] => ram_block1a10.PORTABYTEENAMASKS +byteena_a[1] => ram_block1a11.PORTABYTEENAMASKS +byteena_a[1] => ram_block1a12.PORTABYTEENAMASKS +byteena_a[1] => ram_block1a13.PORTABYTEENAMASKS +byteena_a[1] => ram_block1a14.PORTABYTEENAMASKS +byteena_a[1] => ram_block1a15.PORTABYTEENAMASKS +byteena_a[2] => ram_block1a16.PORTABYTEENAMASKS +byteena_a[2] => ram_block1a17.PORTABYTEENAMASKS +byteena_a[2] => ram_block1a18.PORTABYTEENAMASKS +byteena_a[2] => ram_block1a19.PORTABYTEENAMASKS +byteena_a[2] => ram_block1a20.PORTABYTEENAMASKS +byteena_a[2] => ram_block1a21.PORTABYTEENAMASKS +byteena_a[2] => ram_block1a22.PORTABYTEENAMASKS +byteena_a[2] => ram_block1a23.PORTABYTEENAMASKS +byteena_a[3] => ram_block1a24.PORTABYTEENAMASKS +byteena_a[3] => ram_block1a25.PORTABYTEENAMASKS +byteena_a[3] => ram_block1a26.PORTABYTEENAMASKS +byteena_a[3] => ram_block1a27.PORTABYTEENAMASKS +byteena_a[3] => ram_block1a28.PORTABYTEENAMASKS +byteena_a[3] => ram_block1a29.PORTABYTEENAMASKS +byteena_a[3] => ram_block1a30.PORTABYTEENAMASKS +byteena_a[3] => ram_block1a31.PORTABYTEENAMASKS +clock0 => ram_block1a0.CLK0 +clock0 => ram_block1a1.CLK0 +clock0 => ram_block1a2.CLK0 +clock0 => ram_block1a3.CLK0 +clock0 => ram_block1a4.CLK0 +clock0 => ram_block1a5.CLK0 +clock0 => ram_block1a6.CLK0 +clock0 => ram_block1a7.CLK0 +clock0 => ram_block1a8.CLK0 +clock0 => ram_block1a9.CLK0 +clock0 => ram_block1a10.CLK0 +clock0 => ram_block1a11.CLK0 +clock0 => ram_block1a12.CLK0 +clock0 => ram_block1a13.CLK0 +clock0 => ram_block1a14.CLK0 +clock0 => ram_block1a15.CLK0 +clock0 => ram_block1a16.CLK0 +clock0 => ram_block1a17.CLK0 +clock0 => ram_block1a18.CLK0 +clock0 => ram_block1a19.CLK0 +clock0 => ram_block1a20.CLK0 +clock0 => ram_block1a21.CLK0 +clock0 => ram_block1a22.CLK0 +clock0 => ram_block1a23.CLK0 +clock0 => ram_block1a24.CLK0 +clock0 => ram_block1a25.CLK0 +clock0 => ram_block1a26.CLK0 +clock0 => ram_block1a27.CLK0 +clock0 => ram_block1a28.CLK0 +clock0 => ram_block1a29.CLK0 +clock0 => ram_block1a30.CLK0 +clock0 => ram_block1a31.CLK0 +clock1 => ram_block1a0.CLK1 +clock1 => ram_block1a1.CLK1 +clock1 => ram_block1a2.CLK1 +clock1 => ram_block1a3.CLK1 +clock1 => ram_block1a4.CLK1 +clock1 => ram_block1a5.CLK1 +clock1 => ram_block1a6.CLK1 +clock1 => ram_block1a7.CLK1 +clock1 => ram_block1a8.CLK1 +clock1 => ram_block1a9.CLK1 +clock1 => ram_block1a10.CLK1 +clock1 => ram_block1a11.CLK1 +clock1 => ram_block1a12.CLK1 +clock1 => ram_block1a13.CLK1 +clock1 => ram_block1a14.CLK1 +clock1 => ram_block1a15.CLK1 +clock1 => ram_block1a16.CLK1 +clock1 => ram_block1a17.CLK1 +clock1 => ram_block1a18.CLK1 +clock1 => ram_block1a19.CLK1 +clock1 => ram_block1a20.CLK1 +clock1 => ram_block1a21.CLK1 +clock1 => ram_block1a22.CLK1 +clock1 => ram_block1a23.CLK1 +clock1 => ram_block1a24.CLK1 +clock1 => ram_block1a25.CLK1 +clock1 => ram_block1a26.CLK1 +clock1 => ram_block1a27.CLK1 +clock1 => ram_block1a28.CLK1 +clock1 => ram_block1a29.CLK1 +clock1 => ram_block1a30.CLK1 +clock1 => ram_block1a31.CLK1 +clocken0 => ram_block1a0.ENA0 +clocken0 => ram_block1a1.ENA0 +clocken0 => ram_block1a2.ENA0 +clocken0 => ram_block1a3.ENA0 +clocken0 => ram_block1a4.ENA0 +clocken0 => ram_block1a5.ENA0 +clocken0 => ram_block1a6.ENA0 +clocken0 => ram_block1a7.ENA0 +clocken0 => ram_block1a8.ENA0 +clocken0 => ram_block1a9.ENA0 +clocken0 => ram_block1a10.ENA0 +clocken0 => ram_block1a11.ENA0 +clocken0 => ram_block1a12.ENA0 +clocken0 => ram_block1a13.ENA0 +clocken0 => ram_block1a14.ENA0 +clocken0 => ram_block1a15.ENA0 +clocken0 => ram_block1a16.ENA0 +clocken0 => ram_block1a17.ENA0 +clocken0 => ram_block1a18.ENA0 +clocken0 => ram_block1a19.ENA0 +clocken0 => ram_block1a20.ENA0 +clocken0 => ram_block1a21.ENA0 +clocken0 => ram_block1a22.ENA0 +clocken0 => ram_block1a23.ENA0 +clocken0 => ram_block1a24.ENA0 +clocken0 => ram_block1a25.ENA0 +clocken0 => ram_block1a26.ENA0 +clocken0 => ram_block1a27.ENA0 +clocken0 => ram_block1a28.ENA0 +clocken0 => ram_block1a29.ENA0 +clocken0 => ram_block1a30.ENA0 +clocken0 => ram_block1a31.ENA0 +clocken1 => ram_block1a0.ENA1 +clocken1 => ram_block1a1.ENA1 +clocken1 => ram_block1a2.ENA1 +clocken1 => ram_block1a3.ENA1 +clocken1 => ram_block1a4.ENA1 +clocken1 => ram_block1a5.ENA1 +clocken1 => ram_block1a6.ENA1 +clocken1 => ram_block1a7.ENA1 +clocken1 => ram_block1a8.ENA1 +clocken1 => ram_block1a9.ENA1 +clocken1 => ram_block1a10.ENA1 +clocken1 => ram_block1a11.ENA1 +clocken1 => ram_block1a12.ENA1 +clocken1 => ram_block1a13.ENA1 +clocken1 => ram_block1a14.ENA1 +clocken1 => ram_block1a15.ENA1 +clocken1 => ram_block1a16.ENA1 +clocken1 => ram_block1a17.ENA1 +clocken1 => ram_block1a18.ENA1 +clocken1 => ram_block1a19.ENA1 +clocken1 => ram_block1a20.ENA1 +clocken1 => ram_block1a21.ENA1 +clocken1 => ram_block1a22.ENA1 +clocken1 => ram_block1a23.ENA1 +clocken1 => ram_block1a24.ENA1 +clocken1 => ram_block1a25.ENA1 +clocken1 => ram_block1a26.ENA1 +clocken1 => ram_block1a27.ENA1 +clocken1 => ram_block1a28.ENA1 +clocken1 => ram_block1a29.ENA1 +clocken1 => ram_block1a30.ENA1 +clocken1 => ram_block1a31.ENA1 +data_a[0] => ram_block1a0.PORTADATAIN +data_a[1] => ram_block1a1.PORTADATAIN +data_a[2] => ram_block1a2.PORTADATAIN +data_a[3] => ram_block1a3.PORTADATAIN +data_a[4] => ram_block1a4.PORTADATAIN +data_a[5] => ram_block1a5.PORTADATAIN +data_a[6] => ram_block1a6.PORTADATAIN +data_a[7] => ram_block1a7.PORTADATAIN +data_a[8] => ram_block1a8.PORTADATAIN +data_a[9] => ram_block1a9.PORTADATAIN +data_a[10] => ram_block1a10.PORTADATAIN +data_a[11] => ram_block1a11.PORTADATAIN +data_a[12] => ram_block1a12.PORTADATAIN +data_a[13] => ram_block1a13.PORTADATAIN +data_a[14] => ram_block1a14.PORTADATAIN +data_a[15] => ram_block1a15.PORTADATAIN +data_a[16] => ram_block1a16.PORTADATAIN +data_a[17] => ram_block1a17.PORTADATAIN +data_a[18] => ram_block1a18.PORTADATAIN +data_a[19] => ram_block1a19.PORTADATAIN +data_a[20] => ram_block1a20.PORTADATAIN +data_a[21] => ram_block1a21.PORTADATAIN +data_a[22] => ram_block1a22.PORTADATAIN +data_a[23] => ram_block1a23.PORTADATAIN +data_a[24] => ram_block1a24.PORTADATAIN +data_a[25] => ram_block1a25.PORTADATAIN +data_a[26] => ram_block1a26.PORTADATAIN +data_a[27] => ram_block1a27.PORTADATAIN +data_a[28] => ram_block1a28.PORTADATAIN +data_a[29] => ram_block1a29.PORTADATAIN +data_a[30] => ram_block1a30.PORTADATAIN +data_a[31] => ram_block1a31.PORTADATAIN +data_b[0] => ram_block1a0.PORTBDATAIN +data_b[1] => ram_block1a1.PORTBDATAIN +data_b[2] => ram_block1a2.PORTBDATAIN +data_b[3] => ram_block1a3.PORTBDATAIN +data_b[4] => ram_block1a4.PORTBDATAIN +data_b[5] => ram_block1a5.PORTBDATAIN +data_b[6] => ram_block1a6.PORTBDATAIN +data_b[7] => ram_block1a7.PORTBDATAIN +data_b[8] => ram_block1a8.PORTBDATAIN +data_b[9] => ram_block1a9.PORTBDATAIN +data_b[10] => ram_block1a10.PORTBDATAIN +data_b[11] => ram_block1a11.PORTBDATAIN +data_b[12] => ram_block1a12.PORTBDATAIN +data_b[13] => ram_block1a13.PORTBDATAIN +data_b[14] => ram_block1a14.PORTBDATAIN +data_b[15] => ram_block1a15.PORTBDATAIN +data_b[16] => ram_block1a16.PORTBDATAIN +data_b[17] => ram_block1a17.PORTBDATAIN +data_b[18] => ram_block1a18.PORTBDATAIN +data_b[19] => ram_block1a19.PORTBDATAIN +data_b[20] => ram_block1a20.PORTBDATAIN +data_b[21] => ram_block1a21.PORTBDATAIN +data_b[22] => ram_block1a22.PORTBDATAIN +data_b[23] => ram_block1a23.PORTBDATAIN +data_b[24] => ram_block1a24.PORTBDATAIN +data_b[25] => ram_block1a25.PORTBDATAIN +data_b[26] => ram_block1a26.PORTBDATAIN +data_b[27] => ram_block1a27.PORTBDATAIN +data_b[28] => ram_block1a28.PORTBDATAIN +data_b[29] => ram_block1a29.PORTBDATAIN +data_b[30] => ram_block1a30.PORTBDATAIN +data_b[31] => ram_block1a31.PORTBDATAIN +q_a[0] <= ram_block1a0.PORTADATAOUT +q_a[1] <= ram_block1a1.PORTADATAOUT +q_a[2] <= ram_block1a2.PORTADATAOUT +q_a[3] <= ram_block1a3.PORTADATAOUT +q_a[4] <= ram_block1a4.PORTADATAOUT +q_a[5] <= ram_block1a5.PORTADATAOUT +q_a[6] <= ram_block1a6.PORTADATAOUT +q_a[7] <= ram_block1a7.PORTADATAOUT +q_a[8] <= ram_block1a8.PORTADATAOUT +q_a[9] <= ram_block1a9.PORTADATAOUT +q_a[10] <= ram_block1a10.PORTADATAOUT +q_a[11] <= ram_block1a11.PORTADATAOUT +q_a[12] <= ram_block1a12.PORTADATAOUT +q_a[13] <= ram_block1a13.PORTADATAOUT +q_a[14] <= ram_block1a14.PORTADATAOUT +q_a[15] <= ram_block1a15.PORTADATAOUT +q_a[16] <= ram_block1a16.PORTADATAOUT +q_a[17] <= ram_block1a17.PORTADATAOUT +q_a[18] <= ram_block1a18.PORTADATAOUT +q_a[19] <= ram_block1a19.PORTADATAOUT +q_a[20] <= ram_block1a20.PORTADATAOUT +q_a[21] <= ram_block1a21.PORTADATAOUT +q_a[22] <= ram_block1a22.PORTADATAOUT +q_a[23] <= ram_block1a23.PORTADATAOUT +q_a[24] <= ram_block1a24.PORTADATAOUT +q_a[25] <= ram_block1a25.PORTADATAOUT +q_a[26] <= ram_block1a26.PORTADATAOUT +q_a[27] <= ram_block1a27.PORTADATAOUT +q_a[28] <= ram_block1a28.PORTADATAOUT +q_a[29] <= ram_block1a29.PORTADATAOUT +q_a[30] <= ram_block1a30.PORTADATAOUT +q_a[31] <= ram_block1a31.PORTADATAOUT +q_b[0] <= ram_block1a0.PORTBDATAOUT +q_b[1] <= ram_block1a1.PORTBDATAOUT +q_b[2] <= ram_block1a2.PORTBDATAOUT +q_b[3] <= ram_block1a3.PORTBDATAOUT +q_b[4] <= ram_block1a4.PORTBDATAOUT +q_b[5] <= ram_block1a5.PORTBDATAOUT +q_b[6] <= ram_block1a6.PORTBDATAOUT +q_b[7] <= ram_block1a7.PORTBDATAOUT +q_b[8] <= ram_block1a8.PORTBDATAOUT +q_b[9] <= ram_block1a9.PORTBDATAOUT +q_b[10] <= ram_block1a10.PORTBDATAOUT +q_b[11] <= ram_block1a11.PORTBDATAOUT +q_b[12] <= ram_block1a12.PORTBDATAOUT +q_b[13] <= ram_block1a13.PORTBDATAOUT +q_b[14] <= ram_block1a14.PORTBDATAOUT +q_b[15] <= ram_block1a15.PORTBDATAOUT +q_b[16] <= ram_block1a16.PORTBDATAOUT +q_b[17] <= ram_block1a17.PORTBDATAOUT +q_b[18] <= ram_block1a18.PORTBDATAOUT +q_b[19] <= ram_block1a19.PORTBDATAOUT +q_b[20] <= ram_block1a20.PORTBDATAOUT +q_b[21] <= ram_block1a21.PORTBDATAOUT +q_b[22] <= ram_block1a22.PORTBDATAOUT +q_b[23] <= ram_block1a23.PORTBDATAOUT +q_b[24] <= ram_block1a24.PORTBDATAOUT +q_b[25] <= ram_block1a25.PORTBDATAOUT +q_b[26] <= ram_block1a26.PORTBDATAOUT +q_b[27] <= ram_block1a27.PORTBDATAOUT +q_b[28] <= ram_block1a28.PORTBDATAOUT +q_b[29] <= ram_block1a29.PORTBDATAOUT +q_b[30] <= ram_block1a30.PORTBDATAOUT +q_b[31] <= ram_block1a31.PORTBDATAOUT +wren_a => ram_block1a0.PORTAWE +wren_a => ram_block1a1.PORTAWE +wren_a => ram_block1a2.PORTAWE +wren_a => ram_block1a3.PORTAWE +wren_a => ram_block1a4.PORTAWE +wren_a => ram_block1a5.PORTAWE +wren_a => ram_block1a6.PORTAWE +wren_a => ram_block1a7.PORTAWE +wren_a => ram_block1a8.PORTAWE +wren_a => ram_block1a9.PORTAWE +wren_a => ram_block1a10.PORTAWE +wren_a => ram_block1a11.PORTAWE +wren_a => ram_block1a12.PORTAWE +wren_a => ram_block1a13.PORTAWE +wren_a => ram_block1a14.PORTAWE +wren_a => ram_block1a15.PORTAWE +wren_a => ram_block1a16.PORTAWE +wren_a => ram_block1a17.PORTAWE +wren_a => ram_block1a18.PORTAWE +wren_a => ram_block1a19.PORTAWE +wren_a => ram_block1a20.PORTAWE +wren_a => ram_block1a21.PORTAWE +wren_a => ram_block1a22.PORTAWE +wren_a => ram_block1a23.PORTAWE +wren_a => ram_block1a24.PORTAWE +wren_a => ram_block1a25.PORTAWE +wren_a => ram_block1a26.PORTAWE +wren_a => ram_block1a27.PORTAWE +wren_a => ram_block1a28.PORTAWE +wren_a => ram_block1a29.PORTAWE +wren_a => ram_block1a30.PORTAWE +wren_a => ram_block1a31.PORTAWE +wren_b => ram_block1a0.PORTBWE +wren_b => ram_block1a1.PORTBWE +wren_b => ram_block1a2.PORTBWE +wren_b => ram_block1a3.PORTBWE +wren_b => ram_block1a4.PORTBWE +wren_b => ram_block1a5.PORTBWE +wren_b => ram_block1a6.PORTBWE +wren_b => ram_block1a7.PORTBWE +wren_b => ram_block1a8.PORTBWE +wren_b => ram_block1a9.PORTBWE +wren_b => ram_block1a10.PORTBWE +wren_b => ram_block1a11.PORTBWE +wren_b => ram_block1a12.PORTBWE +wren_b => ram_block1a13.PORTBWE +wren_b => ram_block1a14.PORTBWE +wren_b => ram_block1a15.PORTBWE +wren_b => ram_block1a16.PORTBWE +wren_b => ram_block1a17.PORTBWE +wren_b => ram_block1a18.PORTBWE +wren_b => ram_block1a19.PORTBWE +wren_b => ram_block1a20.PORTBWE +wren_b => ram_block1a21.PORTBWE +wren_b => ram_block1a22.PORTBWE +wren_b => ram_block1a23.PORTBWE +wren_b => ram_block1a24.PORTBWE +wren_b => ram_block1a25.PORTBWE +wren_b => ram_block1a26.PORTBWE +wren_b => ram_block1a27.PORTBWE +wren_b => ram_block1a28.PORTBWE +wren_b => ram_block1a29.PORTBWE +wren_b => ram_block1a30.PORTBWE +wren_b => ram_block1a31.PORTBWE + + +|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg +address[0] => Equal0.IN8 +address[0] => Equal1.IN1 +address[1] => Equal0.IN7 +address[1] => Equal1.IN8 +address[2] => Equal0.IN6 +address[2] => Equal1.IN7 +address[3] => Equal0.IN5 +address[3] => Equal1.IN6 +address[4] => Equal0.IN4 +address[4] => Equal1.IN5 +address[5] => Equal0.IN3 +address[5] => Equal1.IN4 +address[6] => Equal0.IN2 +address[6] => Equal1.IN3 +address[7] => Equal0.IN1 +address[7] => Equal1.IN2 +address[8] => Equal0.IN0 +address[8] => Equal1.IN0 +chipselect => write_strobe.IN0 +clk => oci_ienable[0]~reg0.CLK +clk => oci_ienable[1]~reg0.CLK +clk => oci_ienable[2]~reg0.CLK +clk => oci_ienable[3]~reg0.CLK +clk => oci_ienable[4]~reg0.CLK +clk => oci_ienable[5]~reg0.CLK +clk => oci_ienable[6]~reg0.CLK +clk => oci_ienable[7]~reg0.CLK +clk => oci_ienable[8]~reg0.CLK +clk => oci_ienable[9]~reg0.CLK +clk => oci_ienable[10]~reg0.CLK +clk => oci_ienable[11]~reg0.CLK +clk => oci_ienable[12]~reg0.CLK +clk => oci_ienable[13]~reg0.CLK +clk => oci_ienable[14]~reg0.CLK +clk => oci_ienable[15]~reg0.CLK +clk => oci_ienable[16]~reg0.CLK +clk => oci_ienable[17]~reg0.CLK +clk => oci_ienable[18]~reg0.CLK +clk => oci_ienable[19]~reg0.CLK +clk => oci_ienable[20]~reg0.CLK +clk => oci_ienable[21]~reg0.CLK +clk => oci_ienable[22]~reg0.CLK +clk => oci_ienable[23]~reg0.CLK +clk => oci_ienable[24]~reg0.CLK +clk => oci_ienable[25]~reg0.CLK +clk => oci_ienable[26]~reg0.CLK +clk => oci_ienable[27]~reg0.CLK +clk => oci_ienable[28]~reg0.CLK +clk => oci_ienable[29]~reg0.CLK +clk => oci_ienable[30]~reg0.CLK +clk => oci_ienable[31]~reg0.CLK +clk => oci_single_step_mode~reg0.CLK +debugaccess => write_strobe.IN1 +monitor_error => oci_reg_readdata.DATAB +monitor_go => oci_reg_readdata.DATAB +monitor_ready => oci_reg_readdata.DATAB +reset_n => oci_ienable[0]~reg0.ACLR +reset_n => oci_ienable[1]~reg0.PRESET +reset_n => oci_ienable[2]~reg0.ACLR +reset_n => oci_ienable[3]~reg0.ACLR +reset_n => oci_ienable[4]~reg0.PRESET +reset_n => oci_ienable[5]~reg0.PRESET +reset_n => oci_ienable[6]~reg0.ACLR +reset_n => oci_ienable[7]~reg0.ACLR +reset_n => oci_ienable[8]~reg0.ACLR +reset_n => oci_ienable[9]~reg0.ACLR +reset_n => oci_ienable[10]~reg0.ACLR +reset_n => oci_ienable[11]~reg0.ACLR +reset_n => oci_ienable[12]~reg0.ACLR +reset_n => oci_ienable[13]~reg0.ACLR +reset_n => oci_ienable[14]~reg0.PRESET +reset_n => oci_ienable[15]~reg0.ACLR +reset_n => oci_ienable[16]~reg0.ACLR +reset_n => oci_ienable[17]~reg0.ACLR +reset_n => oci_ienable[18]~reg0.ACLR +reset_n => oci_ienable[19]~reg0.ACLR +reset_n => oci_ienable[20]~reg0.ACLR +reset_n => oci_ienable[21]~reg0.ACLR +reset_n => oci_ienable[22]~reg0.ACLR +reset_n => oci_ienable[23]~reg0.ACLR +reset_n => oci_ienable[24]~reg0.ACLR +reset_n => oci_ienable[25]~reg0.ACLR +reset_n => oci_ienable[26]~reg0.ACLR +reset_n => oci_ienable[27]~reg0.ACLR +reset_n => oci_ienable[28]~reg0.ACLR +reset_n => oci_ienable[29]~reg0.ACLR +reset_n => oci_ienable[30]~reg0.ACLR +reset_n => oci_ienable[31]~reg0.ACLR +reset_n => oci_single_step_mode~reg0.ACLR +write => write_strobe.IN1 +writedata[0] => ocireg_mrs.DATAIN +writedata[1] => ocireg_ers.DATAIN +writedata[1] => oci_ienable[1]~reg0.DATAIN +writedata[2] => ~NO_FANOUT~ +writedata[3] => oci_single_step_mode~reg0.DATAIN +writedata[4] => oci_ienable[4]~reg0.DATAIN +writedata[5] => oci_ienable[5]~reg0.DATAIN +writedata[6] => ~NO_FANOUT~ +writedata[7] => ~NO_FANOUT~ +writedata[8] => ~NO_FANOUT~ +writedata[9] => ~NO_FANOUT~ +writedata[10] => ~NO_FANOUT~ +writedata[11] => ~NO_FANOUT~ +writedata[12] => ~NO_FANOUT~ +writedata[13] => ~NO_FANOUT~ +writedata[14] => oci_ienable[14]~reg0.DATAIN +writedata[15] => ~NO_FANOUT~ +writedata[16] => ~NO_FANOUT~ +writedata[17] => ~NO_FANOUT~ +writedata[18] => ~NO_FANOUT~ +writedata[19] => ~NO_FANOUT~ +writedata[20] => ~NO_FANOUT~ +writedata[21] => ~NO_FANOUT~ +writedata[22] => ~NO_FANOUT~ +writedata[23] => ~NO_FANOUT~ +writedata[24] => ~NO_FANOUT~ +writedata[25] => ~NO_FANOUT~ +writedata[26] => ~NO_FANOUT~ +writedata[27] => ~NO_FANOUT~ +writedata[28] => ~NO_FANOUT~ +writedata[29] => ~NO_FANOUT~ +writedata[30] => ~NO_FANOUT~ +writedata[31] => ~NO_FANOUT~ +oci_ienable[0] <= oci_ienable[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +oci_ienable[1] <= oci_ienable[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +oci_ienable[2] <= oci_ienable[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +oci_ienable[3] <= oci_ienable[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +oci_ienable[4] <= oci_ienable[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +oci_ienable[5] <= oci_ienable[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +oci_ienable[6] <= oci_ienable[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +oci_ienable[7] <= oci_ienable[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE +oci_ienable[8] <= oci_ienable[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE +oci_ienable[9] <= oci_ienable[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE +oci_ienable[10] <= oci_ienable[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE +oci_ienable[11] <= oci_ienable[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE +oci_ienable[12] <= oci_ienable[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE +oci_ienable[13] <= oci_ienable[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE +oci_ienable[14] <= oci_ienable[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE +oci_ienable[15] <= oci_ienable[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE +oci_ienable[16] <= oci_ienable[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE +oci_ienable[17] <= oci_ienable[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE +oci_ienable[18] <= oci_ienable[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE +oci_ienable[19] <= oci_ienable[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE +oci_ienable[20] <= oci_ienable[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE +oci_ienable[21] <= oci_ienable[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE +oci_ienable[22] <= oci_ienable[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE +oci_ienable[23] <= oci_ienable[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE +oci_ienable[24] <= oci_ienable[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE +oci_ienable[25] <= oci_ienable[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE +oci_ienable[26] <= oci_ienable[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE +oci_ienable[27] <= oci_ienable[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE +oci_ienable[28] <= oci_ienable[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE +oci_ienable[29] <= oci_ienable[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE +oci_ienable[30] <= oci_ienable[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE +oci_ienable[31] <= oci_ienable[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE +oci_reg_readdata[0] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE +oci_reg_readdata[1] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE +oci_reg_readdata[2] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE +oci_reg_readdata[3] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE +oci_reg_readdata[4] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE +oci_reg_readdata[5] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE +oci_reg_readdata[6] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE +oci_reg_readdata[7] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE +oci_reg_readdata[8] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE +oci_reg_readdata[9] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE +oci_reg_readdata[10] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE +oci_reg_readdata[11] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE +oci_reg_readdata[12] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE +oci_reg_readdata[13] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE +oci_reg_readdata[14] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE +oci_reg_readdata[15] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE +oci_reg_readdata[16] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE +oci_reg_readdata[17] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE +oci_reg_readdata[18] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE +oci_reg_readdata[19] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE +oci_reg_readdata[20] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE +oci_reg_readdata[21] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE +oci_reg_readdata[22] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE +oci_reg_readdata[23] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE +oci_reg_readdata[24] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE +oci_reg_readdata[25] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE +oci_reg_readdata[26] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE +oci_reg_readdata[27] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE +oci_reg_readdata[28] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE +oci_reg_readdata[29] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE +oci_reg_readdata[30] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE +oci_reg_readdata[31] <= oci_reg_readdata.DB_MAX_OUTPUT_PORT_TYPE +oci_single_step_mode <= oci_single_step_mode~reg0.DB_MAX_OUTPUT_PORT_TYPE +ocireg_ers <= writedata[1].DB_MAX_OUTPUT_PORT_TYPE +ocireg_mrs <= writedata[0].DB_MAX_OUTPUT_PORT_TYPE +take_action_ocireg <= take_action_ocireg.DB_MAX_OUTPUT_PORT_TYPE + + +|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_break:the_system_cpu_nios2_oci_break +clk => trigger_state.CLK +clk => break_readreg[0]~reg0.CLK +clk => break_readreg[1]~reg0.CLK +clk => break_readreg[2]~reg0.CLK +clk => break_readreg[3]~reg0.CLK +clk => break_readreg[4]~reg0.CLK +clk => break_readreg[5]~reg0.CLK +clk => break_readreg[6]~reg0.CLK +clk => break_readreg[7]~reg0.CLK +clk => break_readreg[8]~reg0.CLK +clk => break_readreg[9]~reg0.CLK +clk => break_readreg[10]~reg0.CLK +clk => break_readreg[11]~reg0.CLK +clk => break_readreg[12]~reg0.CLK +clk => break_readreg[13]~reg0.CLK +clk => break_readreg[14]~reg0.CLK +clk => break_readreg[15]~reg0.CLK +clk => break_readreg[16]~reg0.CLK +clk => break_readreg[17]~reg0.CLK +clk => break_readreg[18]~reg0.CLK +clk => break_readreg[19]~reg0.CLK +clk => break_readreg[20]~reg0.CLK +clk => break_readreg[21]~reg0.CLK +clk => break_readreg[22]~reg0.CLK +clk => break_readreg[23]~reg0.CLK +clk => break_readreg[24]~reg0.CLK +clk => break_readreg[25]~reg0.CLK +clk => break_readreg[26]~reg0.CLK +clk => break_readreg[27]~reg0.CLK +clk => break_readreg[28]~reg0.CLK +clk => break_readreg[29]~reg0.CLK +clk => break_readreg[30]~reg0.CLK +clk => break_readreg[31]~reg0.CLK +clk => trigbrktype~reg0.CLK +dbrk_break => trigbrktype.OUTPUTSELECT +dbrk_goto0 => always2.IN0 +dbrk_goto1 => always2.IN0 +jdo[0] => break_readreg.DATAB +jdo[0] => break_readreg.DATAB +jdo[0] => break_readreg.DATAB +jdo[1] => break_readreg.DATAB +jdo[1] => break_readreg.DATAB +jdo[1] => break_readreg.DATAB +jdo[2] => break_readreg.DATAB +jdo[2] => break_readreg.DATAB +jdo[2] => break_readreg.DATAB +jdo[3] => break_readreg.DATAB +jdo[3] => break_readreg.DATAB +jdo[3] => break_readreg.DATAB +jdo[4] => break_readreg.DATAB +jdo[4] => break_readreg.DATAB +jdo[4] => break_readreg.DATAB +jdo[5] => break_readreg.DATAB +jdo[5] => break_readreg.DATAB +jdo[5] => break_readreg.DATAB +jdo[6] => break_readreg.DATAB +jdo[6] => break_readreg.DATAB +jdo[6] => break_readreg.DATAB +jdo[7] => break_readreg.DATAB +jdo[7] => break_readreg.DATAB +jdo[7] => break_readreg.DATAB +jdo[8] => break_readreg.DATAB +jdo[8] => break_readreg.DATAB +jdo[8] => break_readreg.DATAB +jdo[9] => break_readreg.DATAB +jdo[9] => break_readreg.DATAB +jdo[9] => break_readreg.DATAB +jdo[10] => break_readreg.DATAB +jdo[10] => break_readreg.DATAB +jdo[10] => break_readreg.DATAB +jdo[11] => break_readreg.DATAB +jdo[11] => break_readreg.DATAB +jdo[11] => break_readreg.DATAB +jdo[12] => break_readreg.DATAB +jdo[12] => break_readreg.DATAB +jdo[12] => break_readreg.DATAB +jdo[13] => break_readreg.DATAB +jdo[13] => break_readreg.DATAB +jdo[13] => break_readreg.DATAB +jdo[14] => break_readreg.DATAB +jdo[14] => break_readreg.DATAB +jdo[14] => break_readreg.DATAB +jdo[15] => break_readreg.DATAB +jdo[15] => break_readreg.DATAB +jdo[15] => break_readreg.DATAB +jdo[16] => break_readreg.DATAB +jdo[16] => break_readreg.DATAB +jdo[16] => break_readreg.DATAB +jdo[17] => break_readreg.DATAB +jdo[17] => break_readreg.DATAB +jdo[17] => break_readreg.DATAB +jdo[18] => break_readreg.DATAB +jdo[18] => break_readreg.DATAB +jdo[18] => break_readreg.DATAB +jdo[19] => break_readreg.DATAB +jdo[19] => break_readreg.DATAB +jdo[19] => break_readreg.DATAB +jdo[20] => break_readreg.DATAB +jdo[20] => break_readreg.DATAB +jdo[20] => break_readreg.DATAB +jdo[21] => break_readreg.DATAB +jdo[21] => break_readreg.DATAB +jdo[21] => break_readreg.DATAB +jdo[22] => break_readreg.DATAB +jdo[22] => break_readreg.DATAB +jdo[22] => break_readreg.DATAB +jdo[23] => break_readreg.DATAB +jdo[23] => break_readreg.DATAB +jdo[23] => break_readreg.DATAB +jdo[24] => break_readreg.DATAB +jdo[24] => break_readreg.DATAB +jdo[24] => break_readreg.DATAB +jdo[25] => break_readreg.DATAB +jdo[25] => break_readreg.DATAB +jdo[25] => break_readreg.DATAB +jdo[26] => break_readreg.DATAB +jdo[26] => break_readreg.DATAB +jdo[26] => break_readreg.DATAB +jdo[27] => break_readreg.DATAB +jdo[27] => break_readreg.DATAB +jdo[27] => break_readreg.DATAB +jdo[28] => break_readreg.DATAB +jdo[28] => break_readreg.DATAB +jdo[28] => break_readreg.DATAB +jdo[29] => break_readreg.DATAB +jdo[29] => break_readreg.DATAB +jdo[29] => break_readreg.DATAB +jdo[30] => break_readreg.DATAB +jdo[30] => break_readreg.DATAB +jdo[30] => break_readreg.DATAB +jdo[31] => break_readreg.DATAB +jdo[31] => break_readreg.DATAB +jdo[31] => break_readreg.DATAB +jdo[32] => ~NO_FANOUT~ +jdo[33] => ~NO_FANOUT~ +jdo[34] => ~NO_FANOUT~ +jdo[35] => ~NO_FANOUT~ +jdo[36] => ~NO_FANOUT~ +jdo[37] => ~NO_FANOUT~ +jrst_n => break_readreg[0]~reg0.ACLR +jrst_n => break_readreg[1]~reg0.ACLR +jrst_n => break_readreg[2]~reg0.ACLR +jrst_n => break_readreg[3]~reg0.ACLR +jrst_n => break_readreg[4]~reg0.ACLR +jrst_n => break_readreg[5]~reg0.ACLR +jrst_n => break_readreg[6]~reg0.ACLR +jrst_n => break_readreg[7]~reg0.ACLR +jrst_n => break_readreg[8]~reg0.ACLR +jrst_n => break_readreg[9]~reg0.ACLR +jrst_n => break_readreg[10]~reg0.ACLR +jrst_n => break_readreg[11]~reg0.ACLR +jrst_n => break_readreg[12]~reg0.ACLR +jrst_n => break_readreg[13]~reg0.ACLR +jrst_n => break_readreg[14]~reg0.ACLR +jrst_n => break_readreg[15]~reg0.ACLR +jrst_n => break_readreg[16]~reg0.ACLR +jrst_n => break_readreg[17]~reg0.ACLR +jrst_n => break_readreg[18]~reg0.ACLR +jrst_n => break_readreg[19]~reg0.ACLR +jrst_n => break_readreg[20]~reg0.ACLR +jrst_n => break_readreg[21]~reg0.ACLR +jrst_n => break_readreg[22]~reg0.ACLR +jrst_n => break_readreg[23]~reg0.ACLR +jrst_n => break_readreg[24]~reg0.ACLR +jrst_n => break_readreg[25]~reg0.ACLR +jrst_n => break_readreg[26]~reg0.ACLR +jrst_n => break_readreg[27]~reg0.ACLR +jrst_n => break_readreg[28]~reg0.ACLR +jrst_n => break_readreg[29]~reg0.ACLR +jrst_n => break_readreg[30]~reg0.ACLR +jrst_n => break_readreg[31]~reg0.ACLR +jrst_n => trigbrktype~reg0.ACLR +reset_n => trigger_state.ACLR +take_action_break_a => take_action_any_break.IN0 +take_action_break_b => take_action_any_break.IN1 +take_action_break_c => take_action_any_break.IN1 +take_no_action_break_a => break_readreg.OUTPUTSELECT +take_no_action_break_a => break_readreg.OUTPUTSELECT +take_no_action_break_a => break_readreg.OUTPUTSELECT +take_no_action_break_a => break_readreg.OUTPUTSELECT +take_no_action_break_a => break_readreg.OUTPUTSELECT +take_no_action_break_a => break_readreg.OUTPUTSELECT +take_no_action_break_a => break_readreg.OUTPUTSELECT +take_no_action_break_a => break_readreg.OUTPUTSELECT +take_no_action_break_a => break_readreg.OUTPUTSELECT +take_no_action_break_a => break_readreg.OUTPUTSELECT +take_no_action_break_a => break_readreg.OUTPUTSELECT +take_no_action_break_a => break_readreg.OUTPUTSELECT +take_no_action_break_a => break_readreg.OUTPUTSELECT +take_no_action_break_a => break_readreg.OUTPUTSELECT +take_no_action_break_a => break_readreg.OUTPUTSELECT +take_no_action_break_a => break_readreg.OUTPUTSELECT +take_no_action_break_a => break_readreg.OUTPUTSELECT +take_no_action_break_a => break_readreg.OUTPUTSELECT +take_no_action_break_a => break_readreg.OUTPUTSELECT +take_no_action_break_a => break_readreg.OUTPUTSELECT +take_no_action_break_a => break_readreg.OUTPUTSELECT +take_no_action_break_a => break_readreg.OUTPUTSELECT +take_no_action_break_a => break_readreg.OUTPUTSELECT +take_no_action_break_a => break_readreg.OUTPUTSELECT +take_no_action_break_a => break_readreg.OUTPUTSELECT +take_no_action_break_a => break_readreg.OUTPUTSELECT +take_no_action_break_a => break_readreg.OUTPUTSELECT +take_no_action_break_a => break_readreg.OUTPUTSELECT +take_no_action_break_a => break_readreg.OUTPUTSELECT +take_no_action_break_a => break_readreg.OUTPUTSELECT +take_no_action_break_a => break_readreg.OUTPUTSELECT +take_no_action_break_a => break_readreg.OUTPUTSELECT +take_no_action_break_b => break_readreg.OUTPUTSELECT +take_no_action_break_b => break_readreg.OUTPUTSELECT +take_no_action_break_b => break_readreg.OUTPUTSELECT +take_no_action_break_b => break_readreg.OUTPUTSELECT +take_no_action_break_b => break_readreg.OUTPUTSELECT +take_no_action_break_b => break_readreg.OUTPUTSELECT +take_no_action_break_b => break_readreg.OUTPUTSELECT +take_no_action_break_b => break_readreg.OUTPUTSELECT +take_no_action_break_b => break_readreg.OUTPUTSELECT +take_no_action_break_b => break_readreg.OUTPUTSELECT +take_no_action_break_b => break_readreg.OUTPUTSELECT +take_no_action_break_b => break_readreg.OUTPUTSELECT +take_no_action_break_b => break_readreg.OUTPUTSELECT +take_no_action_break_b => break_readreg.OUTPUTSELECT +take_no_action_break_b => break_readreg.OUTPUTSELECT +take_no_action_break_b => break_readreg.OUTPUTSELECT +take_no_action_break_b => break_readreg.OUTPUTSELECT +take_no_action_break_b => break_readreg.OUTPUTSELECT +take_no_action_break_b => break_readreg.OUTPUTSELECT +take_no_action_break_b => break_readreg.OUTPUTSELECT +take_no_action_break_b => break_readreg.OUTPUTSELECT +take_no_action_break_b => break_readreg.OUTPUTSELECT +take_no_action_break_b => break_readreg.OUTPUTSELECT +take_no_action_break_b => break_readreg.OUTPUTSELECT +take_no_action_break_b => break_readreg.OUTPUTSELECT +take_no_action_break_b => break_readreg.OUTPUTSELECT +take_no_action_break_b => break_readreg.OUTPUTSELECT +take_no_action_break_b => break_readreg.OUTPUTSELECT +take_no_action_break_b => break_readreg.OUTPUTSELECT +take_no_action_break_b => break_readreg.OUTPUTSELECT +take_no_action_break_b => break_readreg.OUTPUTSELECT +take_no_action_break_b => break_readreg.OUTPUTSELECT +take_no_action_break_c => break_readreg.OUTPUTSELECT +take_no_action_break_c => break_readreg.OUTPUTSELECT +take_no_action_break_c => break_readreg.OUTPUTSELECT +take_no_action_break_c => break_readreg.OUTPUTSELECT +take_no_action_break_c => break_readreg.OUTPUTSELECT +take_no_action_break_c => break_readreg.OUTPUTSELECT +take_no_action_break_c => break_readreg.OUTPUTSELECT +take_no_action_break_c => break_readreg.OUTPUTSELECT +take_no_action_break_c => break_readreg.OUTPUTSELECT +take_no_action_break_c => break_readreg.OUTPUTSELECT +take_no_action_break_c => break_readreg.OUTPUTSELECT +take_no_action_break_c => break_readreg.OUTPUTSELECT +take_no_action_break_c => break_readreg.OUTPUTSELECT +take_no_action_break_c => break_readreg.OUTPUTSELECT +take_no_action_break_c => break_readreg.OUTPUTSELECT +take_no_action_break_c => break_readreg.OUTPUTSELECT +take_no_action_break_c => break_readreg.OUTPUTSELECT +take_no_action_break_c => break_readreg.OUTPUTSELECT +take_no_action_break_c => break_readreg.OUTPUTSELECT +take_no_action_break_c => break_readreg.OUTPUTSELECT +take_no_action_break_c => break_readreg.OUTPUTSELECT +take_no_action_break_c => break_readreg.OUTPUTSELECT +take_no_action_break_c => break_readreg.OUTPUTSELECT +take_no_action_break_c => break_readreg.OUTPUTSELECT +take_no_action_break_c => break_readreg.OUTPUTSELECT +take_no_action_break_c => break_readreg.OUTPUTSELECT +take_no_action_break_c => break_readreg.OUTPUTSELECT +take_no_action_break_c => break_readreg.OUTPUTSELECT +take_no_action_break_c => break_readreg.OUTPUTSELECT +take_no_action_break_c => break_readreg.OUTPUTSELECT +take_no_action_break_c => break_readreg.OUTPUTSELECT +take_no_action_break_c => break_readreg.OUTPUTSELECT +xbrk_goto0 => always2.IN1 +xbrk_goto1 => always2.IN1 +break_readreg[0] <= break_readreg[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +break_readreg[1] <= break_readreg[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +break_readreg[2] <= break_readreg[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +break_readreg[3] <= break_readreg[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +break_readreg[4] <= break_readreg[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +break_readreg[5] <= break_readreg[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +break_readreg[6] <= break_readreg[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +break_readreg[7] <= break_readreg[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE +break_readreg[8] <= break_readreg[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE +break_readreg[9] <= break_readreg[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE +break_readreg[10] <= break_readreg[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE +break_readreg[11] <= break_readreg[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE +break_readreg[12] <= break_readreg[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE +break_readreg[13] <= break_readreg[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE +break_readreg[14] <= break_readreg[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE +break_readreg[15] <= break_readreg[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE +break_readreg[16] <= break_readreg[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE +break_readreg[17] <= break_readreg[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE +break_readreg[18] <= break_readreg[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE +break_readreg[19] <= break_readreg[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE +break_readreg[20] <= break_readreg[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE +break_readreg[21] <= break_readreg[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE +break_readreg[22] <= break_readreg[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE +break_readreg[23] <= break_readreg[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE +break_readreg[24] <= break_readreg[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE +break_readreg[25] <= break_readreg[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE +break_readreg[26] <= break_readreg[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE +break_readreg[27] <= break_readreg[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE +break_readreg[28] <= break_readreg[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE +break_readreg[29] <= break_readreg[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE +break_readreg[30] <= break_readreg[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE +break_readreg[31] <= break_readreg[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dbrk_hit0_latch <= +dbrk_hit1_latch <= +dbrk_hit2_latch <= +dbrk_hit3_latch <= +trigbrktype <= trigbrktype~reg0.DB_MAX_OUTPUT_PORT_TYPE +trigger_state_0 <= trigger_state.DB_MAX_OUTPUT_PORT_TYPE +trigger_state_1 <= trigger_state.DB_MAX_OUTPUT_PORT_TYPE +xbrk_ctrl0[0] <= +xbrk_ctrl0[1] <= +xbrk_ctrl0[2] <= +xbrk_ctrl0[3] <= +xbrk_ctrl0[4] <= +xbrk_ctrl0[5] <= +xbrk_ctrl0[6] <= +xbrk_ctrl0[7] <= +xbrk_ctrl1[0] <= +xbrk_ctrl1[1] <= +xbrk_ctrl1[2] <= +xbrk_ctrl1[3] <= +xbrk_ctrl1[4] <= +xbrk_ctrl1[5] <= +xbrk_ctrl1[6] <= +xbrk_ctrl1[7] <= +xbrk_ctrl2[0] <= +xbrk_ctrl2[1] <= +xbrk_ctrl2[2] <= +xbrk_ctrl2[3] <= +xbrk_ctrl2[4] <= +xbrk_ctrl2[5] <= +xbrk_ctrl2[6] <= +xbrk_ctrl2[7] <= +xbrk_ctrl3[0] <= +xbrk_ctrl3[1] <= +xbrk_ctrl3[2] <= +xbrk_ctrl3[3] <= +xbrk_ctrl3[4] <= +xbrk_ctrl3[5] <= +xbrk_ctrl3[6] <= +xbrk_ctrl3[7] <= + + +|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_xbrk:the_system_cpu_nios2_oci_xbrk +D_en => ~NO_FANOUT~ +E_en => xbrk_break~reg0.ENA +E_en => E_xbrk_traceon.ENA +E_en => E_xbrk_traceoff.ENA +E_en => E_xbrk_trigout.ENA +E_en => E_xbrk_goto0.ENA +E_en => E_xbrk_goto1.ENA +E_valid => M_xbrk_traceon.IN1 +E_valid => M_xbrk_traceoff.IN1 +E_valid => M_xbrk_trigout.IN1 +E_valid => M_xbrk_goto0.IN1 +E_valid => M_xbrk_goto1.IN1 +F_pc[0] => ~NO_FANOUT~ +F_pc[1] => ~NO_FANOUT~ +F_pc[2] => ~NO_FANOUT~ +F_pc[3] => ~NO_FANOUT~ +F_pc[4] => ~NO_FANOUT~ +F_pc[5] => ~NO_FANOUT~ +F_pc[6] => ~NO_FANOUT~ +F_pc[7] => ~NO_FANOUT~ +F_pc[8] => ~NO_FANOUT~ +F_pc[9] => ~NO_FANOUT~ +F_pc[10] => ~NO_FANOUT~ +F_pc[11] => ~NO_FANOUT~ +F_pc[12] => ~NO_FANOUT~ +F_pc[13] => ~NO_FANOUT~ +F_pc[14] => ~NO_FANOUT~ +F_pc[15] => ~NO_FANOUT~ +F_pc[16] => ~NO_FANOUT~ +F_pc[17] => ~NO_FANOUT~ +F_pc[18] => ~NO_FANOUT~ +F_pc[19] => ~NO_FANOUT~ +F_pc[20] => ~NO_FANOUT~ +F_pc[21] => ~NO_FANOUT~ +F_pc[22] => ~NO_FANOUT~ +F_pc[23] => ~NO_FANOUT~ +M_en => M_xbrk_traceon.ENA +M_en => M_xbrk_traceoff.ENA +M_en => M_xbrk_trigout.ENA +M_en => M_xbrk_goto0.ENA +M_en => M_xbrk_goto1.ENA +clk => M_xbrk_goto1.CLK +clk => M_xbrk_goto0.CLK +clk => M_xbrk_trigout.CLK +clk => M_xbrk_traceoff.CLK +clk => M_xbrk_traceon.CLK +clk => E_xbrk_goto1.CLK +clk => E_xbrk_goto0.CLK +clk => E_xbrk_trigout.CLK +clk => E_xbrk_traceoff.CLK +clk => E_xbrk_traceon.CLK +clk => xbrk_break~reg0.CLK +reset_n => xbrk_break~reg0.ACLR +reset_n => M_xbrk_goto0.ACLR +reset_n => M_xbrk_goto1.ACLR +reset_n => M_xbrk_traceoff.ACLR +reset_n => M_xbrk_traceon.ACLR +reset_n => M_xbrk_trigout.ACLR +reset_n => E_xbrk_traceon.ACLR +reset_n => E_xbrk_traceoff.ACLR +reset_n => E_xbrk_trigout.ACLR +reset_n => E_xbrk_goto0.ACLR +reset_n => E_xbrk_goto1.ACLR +trigger_state_0 => ~NO_FANOUT~ +trigger_state_1 => ~NO_FANOUT~ +xbrk_ctrl0[0] => ~NO_FANOUT~ +xbrk_ctrl0[1] => ~NO_FANOUT~ +xbrk_ctrl0[2] => ~NO_FANOUT~ +xbrk_ctrl0[3] => ~NO_FANOUT~ +xbrk_ctrl0[4] => ~NO_FANOUT~ +xbrk_ctrl0[5] => ~NO_FANOUT~ +xbrk_ctrl0[6] => ~NO_FANOUT~ +xbrk_ctrl0[7] => ~NO_FANOUT~ +xbrk_ctrl1[0] => ~NO_FANOUT~ +xbrk_ctrl1[1] => ~NO_FANOUT~ +xbrk_ctrl1[2] => ~NO_FANOUT~ +xbrk_ctrl1[3] => ~NO_FANOUT~ +xbrk_ctrl1[4] => ~NO_FANOUT~ +xbrk_ctrl1[5] => ~NO_FANOUT~ +xbrk_ctrl1[6] => ~NO_FANOUT~ +xbrk_ctrl1[7] => ~NO_FANOUT~ +xbrk_ctrl2[0] => ~NO_FANOUT~ +xbrk_ctrl2[1] => ~NO_FANOUT~ +xbrk_ctrl2[2] => ~NO_FANOUT~ +xbrk_ctrl2[3] => ~NO_FANOUT~ +xbrk_ctrl2[4] => ~NO_FANOUT~ +xbrk_ctrl2[5] => ~NO_FANOUT~ +xbrk_ctrl2[6] => ~NO_FANOUT~ +xbrk_ctrl2[7] => ~NO_FANOUT~ +xbrk_ctrl3[0] => ~NO_FANOUT~ +xbrk_ctrl3[1] => ~NO_FANOUT~ +xbrk_ctrl3[2] => ~NO_FANOUT~ +xbrk_ctrl3[3] => ~NO_FANOUT~ +xbrk_ctrl3[4] => ~NO_FANOUT~ +xbrk_ctrl3[5] => ~NO_FANOUT~ +xbrk_ctrl3[6] => ~NO_FANOUT~ +xbrk_ctrl3[7] => ~NO_FANOUT~ +xbrk_break <= xbrk_break~reg0.DB_MAX_OUTPUT_PORT_TYPE +xbrk_goto0 <= M_xbrk_goto0.DB_MAX_OUTPUT_PORT_TYPE +xbrk_goto1 <= M_xbrk_goto1.DB_MAX_OUTPUT_PORT_TYPE +xbrk_traceoff <= M_xbrk_traceoff.DB_MAX_OUTPUT_PORT_TYPE +xbrk_traceon <= M_xbrk_traceon.DB_MAX_OUTPUT_PORT_TYPE +xbrk_trigout <= M_xbrk_trigout.DB_MAX_OUTPUT_PORT_TYPE + + +|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_dbrk:the_system_cpu_nios2_oci_dbrk +A_ctrl_ld => cpu_d_read.IN0 +A_ctrl_st => cpu_d_write.IN0 +A_en => cpu_d_wait.DATAIN +A_mem_baddr[0] => cpu_d_address[0].DATAIN +A_mem_baddr[1] => cpu_d_address[1].DATAIN +A_mem_baddr[2] => cpu_d_address[2].DATAIN +A_mem_baddr[3] => cpu_d_address[3].DATAIN +A_mem_baddr[4] => cpu_d_address[4].DATAIN +A_mem_baddr[5] => cpu_d_address[5].DATAIN +A_mem_baddr[6] => cpu_d_address[6].DATAIN +A_mem_baddr[7] => cpu_d_address[7].DATAIN +A_mem_baddr[8] => cpu_d_address[8].DATAIN +A_mem_baddr[9] => cpu_d_address[9].DATAIN +A_mem_baddr[10] => cpu_d_address[10].DATAIN +A_mem_baddr[11] => cpu_d_address[11].DATAIN +A_mem_baddr[12] => cpu_d_address[12].DATAIN +A_mem_baddr[13] => cpu_d_address[13].DATAIN +A_mem_baddr[14] => cpu_d_address[14].DATAIN +A_mem_baddr[15] => cpu_d_address[15].DATAIN +A_mem_baddr[16] => cpu_d_address[16].DATAIN +A_mem_baddr[17] => cpu_d_address[17].DATAIN +A_mem_baddr[18] => cpu_d_address[18].DATAIN +A_mem_baddr[19] => cpu_d_address[19].DATAIN +A_mem_baddr[20] => cpu_d_address[20].DATAIN +A_mem_baddr[21] => cpu_d_address[21].DATAIN +A_mem_baddr[22] => cpu_d_address[22].DATAIN +A_mem_baddr[23] => cpu_d_address[23].DATAIN +A_mem_baddr[24] => cpu_d_address[24].DATAIN +A_mem_baddr[25] => cpu_d_address[25].DATAIN +A_st_data[0] => cpu_d_writedata[0].DATAIN +A_st_data[1] => cpu_d_writedata[1].DATAIN +A_st_data[2] => cpu_d_writedata[2].DATAIN +A_st_data[3] => cpu_d_writedata[3].DATAIN +A_st_data[4] => cpu_d_writedata[4].DATAIN +A_st_data[5] => cpu_d_writedata[5].DATAIN +A_st_data[6] => cpu_d_writedata[6].DATAIN +A_st_data[7] => cpu_d_writedata[7].DATAIN +A_st_data[8] => cpu_d_writedata[8].DATAIN +A_st_data[9] => cpu_d_writedata[9].DATAIN +A_st_data[10] => cpu_d_writedata[10].DATAIN +A_st_data[11] => cpu_d_writedata[11].DATAIN +A_st_data[12] => cpu_d_writedata[12].DATAIN +A_st_data[13] => cpu_d_writedata[13].DATAIN +A_st_data[14] => cpu_d_writedata[14].DATAIN +A_st_data[15] => cpu_d_writedata[15].DATAIN +A_st_data[16] => cpu_d_writedata[16].DATAIN +A_st_data[17] => cpu_d_writedata[17].DATAIN +A_st_data[18] => cpu_d_writedata[18].DATAIN +A_st_data[19] => cpu_d_writedata[19].DATAIN +A_st_data[20] => cpu_d_writedata[20].DATAIN +A_st_data[21] => cpu_d_writedata[21].DATAIN +A_st_data[22] => cpu_d_writedata[22].DATAIN +A_st_data[23] => cpu_d_writedata[23].DATAIN +A_st_data[24] => cpu_d_writedata[24].DATAIN +A_st_data[25] => cpu_d_writedata[25].DATAIN +A_st_data[26] => cpu_d_writedata[26].DATAIN +A_st_data[27] => cpu_d_writedata[27].DATAIN +A_st_data[28] => cpu_d_writedata[28].DATAIN +A_st_data[29] => cpu_d_writedata[29].DATAIN +A_st_data[30] => cpu_d_writedata[30].DATAIN +A_st_data[31] => cpu_d_writedata[31].DATAIN +A_valid => cpu_d_read.IN1 +A_valid => cpu_d_write.IN1 +A_wr_data_filtered[0] => cpu_d_readdata[0].DATAIN +A_wr_data_filtered[1] => cpu_d_readdata[1].DATAIN +A_wr_data_filtered[2] => cpu_d_readdata[2].DATAIN +A_wr_data_filtered[3] => cpu_d_readdata[3].DATAIN +A_wr_data_filtered[4] => cpu_d_readdata[4].DATAIN +A_wr_data_filtered[5] => cpu_d_readdata[5].DATAIN +A_wr_data_filtered[6] => cpu_d_readdata[6].DATAIN +A_wr_data_filtered[7] => cpu_d_readdata[7].DATAIN +A_wr_data_filtered[8] => cpu_d_readdata[8].DATAIN +A_wr_data_filtered[9] => cpu_d_readdata[9].DATAIN +A_wr_data_filtered[10] => cpu_d_readdata[10].DATAIN +A_wr_data_filtered[11] => cpu_d_readdata[11].DATAIN +A_wr_data_filtered[12] => cpu_d_readdata[12].DATAIN +A_wr_data_filtered[13] => cpu_d_readdata[13].DATAIN +A_wr_data_filtered[14] => cpu_d_readdata[14].DATAIN +A_wr_data_filtered[15] => cpu_d_readdata[15].DATAIN +A_wr_data_filtered[16] => cpu_d_readdata[16].DATAIN +A_wr_data_filtered[17] => cpu_d_readdata[17].DATAIN +A_wr_data_filtered[18] => cpu_d_readdata[18].DATAIN +A_wr_data_filtered[19] => cpu_d_readdata[19].DATAIN +A_wr_data_filtered[20] => cpu_d_readdata[20].DATAIN +A_wr_data_filtered[21] => cpu_d_readdata[21].DATAIN +A_wr_data_filtered[22] => cpu_d_readdata[22].DATAIN +A_wr_data_filtered[23] => cpu_d_readdata[23].DATAIN +A_wr_data_filtered[24] => cpu_d_readdata[24].DATAIN +A_wr_data_filtered[25] => cpu_d_readdata[25].DATAIN +A_wr_data_filtered[26] => cpu_d_readdata[26].DATAIN +A_wr_data_filtered[27] => cpu_d_readdata[27].DATAIN +A_wr_data_filtered[28] => cpu_d_readdata[28].DATAIN +A_wr_data_filtered[29] => cpu_d_readdata[29].DATAIN +A_wr_data_filtered[30] => cpu_d_readdata[30].DATAIN +A_wr_data_filtered[31] => cpu_d_readdata[31].DATAIN +clk => dbrk_goto1~reg0.CLK +clk => dbrk_goto0~reg0.CLK +clk => dbrk_traceme~reg0.CLK +clk => dbrk_traceon~reg0.CLK +clk => dbrk_traceoff~reg0.CLK +clk => dbrk_break_pulse.CLK +clk => dbrk_trigout~reg0.CLK +clk => dbrk_break~reg0.CLK +debugack => dbrk_break.DATAB +reset_n => dbrk_goto1~reg0.ACLR +reset_n => dbrk_goto0~reg0.ACLR +reset_n => dbrk_traceme~reg0.ACLR +reset_n => dbrk_traceon~reg0.ACLR +reset_n => dbrk_traceoff~reg0.ACLR +reset_n => dbrk_break_pulse.ACLR +reset_n => dbrk_trigout~reg0.ACLR +reset_n => dbrk_break~reg0.ACLR +cpu_d_address[0] <= A_mem_baddr[0].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_address[1] <= A_mem_baddr[1].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_address[2] <= A_mem_baddr[2].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_address[3] <= A_mem_baddr[3].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_address[4] <= A_mem_baddr[4].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_address[5] <= A_mem_baddr[5].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_address[6] <= A_mem_baddr[6].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_address[7] <= A_mem_baddr[7].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_address[8] <= A_mem_baddr[8].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_address[9] <= A_mem_baddr[9].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_address[10] <= A_mem_baddr[10].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_address[11] <= A_mem_baddr[11].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_address[12] <= A_mem_baddr[12].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_address[13] <= A_mem_baddr[13].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_address[14] <= A_mem_baddr[14].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_address[15] <= A_mem_baddr[15].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_address[16] <= A_mem_baddr[16].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_address[17] <= A_mem_baddr[17].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_address[18] <= A_mem_baddr[18].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_address[19] <= A_mem_baddr[19].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_address[20] <= A_mem_baddr[20].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_address[21] <= A_mem_baddr[21].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_address[22] <= A_mem_baddr[22].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_address[23] <= A_mem_baddr[23].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_address[24] <= A_mem_baddr[24].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_address[25] <= A_mem_baddr[25].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_read <= cpu_d_read.DB_MAX_OUTPUT_PORT_TYPE +cpu_d_readdata[0] <= A_wr_data_filtered[0].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_readdata[1] <= A_wr_data_filtered[1].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_readdata[2] <= A_wr_data_filtered[2].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_readdata[3] <= A_wr_data_filtered[3].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_readdata[4] <= A_wr_data_filtered[4].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_readdata[5] <= A_wr_data_filtered[5].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_readdata[6] <= A_wr_data_filtered[6].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_readdata[7] <= A_wr_data_filtered[7].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_readdata[8] <= A_wr_data_filtered[8].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_readdata[9] <= A_wr_data_filtered[9].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_readdata[10] <= A_wr_data_filtered[10].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_readdata[11] <= A_wr_data_filtered[11].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_readdata[12] <= A_wr_data_filtered[12].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_readdata[13] <= A_wr_data_filtered[13].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_readdata[14] <= A_wr_data_filtered[14].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_readdata[15] <= A_wr_data_filtered[15].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_readdata[16] <= A_wr_data_filtered[16].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_readdata[17] <= A_wr_data_filtered[17].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_readdata[18] <= A_wr_data_filtered[18].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_readdata[19] <= A_wr_data_filtered[19].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_readdata[20] <= A_wr_data_filtered[20].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_readdata[21] <= A_wr_data_filtered[21].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_readdata[22] <= A_wr_data_filtered[22].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_readdata[23] <= A_wr_data_filtered[23].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_readdata[24] <= A_wr_data_filtered[24].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_readdata[25] <= A_wr_data_filtered[25].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_readdata[26] <= A_wr_data_filtered[26].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_readdata[27] <= A_wr_data_filtered[27].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_readdata[28] <= A_wr_data_filtered[28].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_readdata[29] <= A_wr_data_filtered[29].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_readdata[30] <= A_wr_data_filtered[30].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_readdata[31] <= A_wr_data_filtered[31].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_wait <= A_en.DB_MAX_OUTPUT_PORT_TYPE +cpu_d_write <= cpu_d_write.DB_MAX_OUTPUT_PORT_TYPE +cpu_d_writedata[0] <= A_st_data[0].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_writedata[1] <= A_st_data[1].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_writedata[2] <= A_st_data[2].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_writedata[3] <= A_st_data[3].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_writedata[4] <= A_st_data[4].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_writedata[5] <= A_st_data[5].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_writedata[6] <= A_st_data[6].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_writedata[7] <= A_st_data[7].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_writedata[8] <= A_st_data[8].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_writedata[9] <= A_st_data[9].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_writedata[10] <= A_st_data[10].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_writedata[11] <= A_st_data[11].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_writedata[12] <= A_st_data[12].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_writedata[13] <= A_st_data[13].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_writedata[14] <= A_st_data[14].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_writedata[15] <= A_st_data[15].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_writedata[16] <= A_st_data[16].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_writedata[17] <= A_st_data[17].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_writedata[18] <= A_st_data[18].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_writedata[19] <= A_st_data[19].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_writedata[20] <= A_st_data[20].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_writedata[21] <= A_st_data[21].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_writedata[22] <= A_st_data[22].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_writedata[23] <= A_st_data[23].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_writedata[24] <= A_st_data[24].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_writedata[25] <= A_st_data[25].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_writedata[26] <= A_st_data[26].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_writedata[27] <= A_st_data[27].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_writedata[28] <= A_st_data[28].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_writedata[29] <= A_st_data[29].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_writedata[30] <= A_st_data[30].DB_MAX_OUTPUT_PORT_TYPE +cpu_d_writedata[31] <= A_st_data[31].DB_MAX_OUTPUT_PORT_TYPE +dbrk_break <= dbrk_break~reg0.DB_MAX_OUTPUT_PORT_TYPE +dbrk_goto0 <= dbrk_goto0~reg0.DB_MAX_OUTPUT_PORT_TYPE +dbrk_goto1 <= dbrk_goto1~reg0.DB_MAX_OUTPUT_PORT_TYPE +dbrk_traceme <= dbrk_traceme~reg0.DB_MAX_OUTPUT_PORT_TYPE +dbrk_traceoff <= dbrk_traceoff~reg0.DB_MAX_OUTPUT_PORT_TYPE +dbrk_traceon <= dbrk_traceon~reg0.DB_MAX_OUTPUT_PORT_TYPE +dbrk_trigout <= dbrk_trigout~reg0.DB_MAX_OUTPUT_PORT_TYPE + + +|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_itrace:the_system_cpu_nios2_oci_itrace +A_cmp_result => ~NO_FANOUT~ +A_ctrl_exception => ~NO_FANOUT~ +A_en => instr_retired.IN0 +A_op_beq => ~NO_FANOUT~ +A_op_bge => ~NO_FANOUT~ +A_op_bgeu => ~NO_FANOUT~ +A_op_blt => ~NO_FANOUT~ +A_op_bltu => ~NO_FANOUT~ +A_op_bne => ~NO_FANOUT~ +A_op_br => ~NO_FANOUT~ +A_op_bret => ~NO_FANOUT~ +A_op_call => ~NO_FANOUT~ +A_op_callr => ~NO_FANOUT~ +A_op_eret => ~NO_FANOUT~ +A_op_jmp => ~NO_FANOUT~ +A_op_jmpi => ~NO_FANOUT~ +A_op_ret => ~NO_FANOUT~ +A_pcb[0] => ~NO_FANOUT~ +A_pcb[1] => ~NO_FANOUT~ +A_pcb[2] => ~NO_FANOUT~ +A_pcb[3] => ~NO_FANOUT~ +A_pcb[4] => ~NO_FANOUT~ +A_pcb[5] => ~NO_FANOUT~ +A_pcb[6] => ~NO_FANOUT~ +A_pcb[7] => ~NO_FANOUT~ +A_pcb[8] => ~NO_FANOUT~ +A_pcb[9] => ~NO_FANOUT~ +A_pcb[10] => ~NO_FANOUT~ +A_pcb[11] => ~NO_FANOUT~ +A_pcb[12] => ~NO_FANOUT~ +A_pcb[13] => ~NO_FANOUT~ +A_pcb[14] => ~NO_FANOUT~ +A_pcb[15] => ~NO_FANOUT~ +A_pcb[16] => ~NO_FANOUT~ +A_pcb[17] => ~NO_FANOUT~ +A_pcb[18] => ~NO_FANOUT~ +A_pcb[19] => ~NO_FANOUT~ +A_pcb[20] => ~NO_FANOUT~ +A_pcb[21] => ~NO_FANOUT~ +A_pcb[22] => ~NO_FANOUT~ +A_pcb[23] => ~NO_FANOUT~ +A_pcb[24] => ~NO_FANOUT~ +A_pcb[25] => ~NO_FANOUT~ +A_valid => instr_retired.IN1 +A_wr_data_filtered[0] => ~NO_FANOUT~ +A_wr_data_filtered[1] => ~NO_FANOUT~ +A_wr_data_filtered[2] => ~NO_FANOUT~ +A_wr_data_filtered[3] => ~NO_FANOUT~ +A_wr_data_filtered[4] => ~NO_FANOUT~ +A_wr_data_filtered[5] => ~NO_FANOUT~ +A_wr_data_filtered[6] => ~NO_FANOUT~ +A_wr_data_filtered[7] => ~NO_FANOUT~ +A_wr_data_filtered[8] => ~NO_FANOUT~ +A_wr_data_filtered[9] => ~NO_FANOUT~ +A_wr_data_filtered[10] => ~NO_FANOUT~ +A_wr_data_filtered[11] => ~NO_FANOUT~ +A_wr_data_filtered[12] => ~NO_FANOUT~ +A_wr_data_filtered[13] => ~NO_FANOUT~ +A_wr_data_filtered[14] => ~NO_FANOUT~ +A_wr_data_filtered[15] => ~NO_FANOUT~ +A_wr_data_filtered[16] => ~NO_FANOUT~ +A_wr_data_filtered[17] => ~NO_FANOUT~ +A_wr_data_filtered[18] => ~NO_FANOUT~ +A_wr_data_filtered[19] => ~NO_FANOUT~ +A_wr_data_filtered[20] => ~NO_FANOUT~ +A_wr_data_filtered[21] => ~NO_FANOUT~ +A_wr_data_filtered[22] => ~NO_FANOUT~ +A_wr_data_filtered[23] => ~NO_FANOUT~ +A_wr_data_filtered[24] => ~NO_FANOUT~ +A_wr_data_filtered[25] => ~NO_FANOUT~ +A_wr_data_filtered[26] => ~NO_FANOUT~ +A_wr_data_filtered[27] => ~NO_FANOUT~ +A_wr_data_filtered[28] => ~NO_FANOUT~ +A_wr_data_filtered[29] => ~NO_FANOUT~ +A_wr_data_filtered[30] => ~NO_FANOUT~ +A_wr_data_filtered[31] => ~NO_FANOUT~ +clk => dct_count[0]~reg0.CLK +clk => dct_count[1]~reg0.CLK +clk => dct_count[2]~reg0.CLK +clk => dct_count[3]~reg0.CLK +clk => dct_buffer[0]~reg0.CLK +clk => dct_buffer[1]~reg0.CLK +clk => dct_buffer[2]~reg0.CLK +clk => dct_buffer[3]~reg0.CLK +clk => dct_buffer[4]~reg0.CLK +clk => dct_buffer[5]~reg0.CLK +clk => dct_buffer[6]~reg0.CLK +clk => dct_buffer[7]~reg0.CLK +clk => dct_buffer[8]~reg0.CLK +clk => dct_buffer[9]~reg0.CLK +clk => dct_buffer[10]~reg0.CLK +clk => dct_buffer[11]~reg0.CLK +clk => dct_buffer[12]~reg0.CLK +clk => dct_buffer[13]~reg0.CLK +clk => dct_buffer[14]~reg0.CLK +clk => dct_buffer[15]~reg0.CLK +clk => dct_buffer[16]~reg0.CLK +clk => dct_buffer[17]~reg0.CLK +clk => dct_buffer[18]~reg0.CLK +clk => dct_buffer[19]~reg0.CLK +clk => dct_buffer[20]~reg0.CLK +clk => dct_buffer[21]~reg0.CLK +clk => dct_buffer[22]~reg0.CLK +clk => dct_buffer[23]~reg0.CLK +clk => dct_buffer[24]~reg0.CLK +clk => dct_buffer[25]~reg0.CLK +clk => dct_buffer[26]~reg0.CLK +clk => dct_buffer[27]~reg0.CLK +clk => dct_buffer[28]~reg0.CLK +clk => dct_buffer[29]~reg0.CLK +clk => itm[0]~reg0.CLK +clk => itm[1]~reg0.CLK +clk => itm[2]~reg0.CLK +clk => itm[3]~reg0.CLK +clk => itm[4]~reg0.CLK +clk => itm[5]~reg0.CLK +clk => itm[6]~reg0.CLK +clk => itm[7]~reg0.CLK +clk => itm[8]~reg0.CLK +clk => itm[9]~reg0.CLK +clk => itm[10]~reg0.CLK +clk => itm[11]~reg0.CLK +clk => itm[12]~reg0.CLK +clk => itm[13]~reg0.CLK +clk => itm[14]~reg0.CLK +clk => itm[15]~reg0.CLK +clk => itm[16]~reg0.CLK +clk => itm[17]~reg0.CLK +clk => itm[18]~reg0.CLK +clk => itm[19]~reg0.CLK +clk => itm[20]~reg0.CLK +clk => itm[21]~reg0.CLK +clk => itm[22]~reg0.CLK +clk => itm[23]~reg0.CLK +clk => itm[24]~reg0.CLK +clk => itm[25]~reg0.CLK +clk => itm[26]~reg0.CLK +clk => itm[27]~reg0.CLK +clk => itm[28]~reg0.CLK +clk => itm[29]~reg0.CLK +clk => itm[30]~reg0.CLK +clk => itm[31]~reg0.CLK +clk => itm[32]~reg0.CLK +clk => itm[33]~reg0.CLK +clk => itm[34]~reg0.CLK +clk => itm[35]~reg0.CLK +clk => d1_debugack.CLK +dbrk_traceoff => ~NO_FANOUT~ +dbrk_traceon => ~NO_FANOUT~ +debugack => d1_debugack.DATAIN +jdo[0] => ~NO_FANOUT~ +jdo[1] => ~NO_FANOUT~ +jdo[2] => ~NO_FANOUT~ +jdo[3] => ~NO_FANOUT~ +jdo[4] => ~NO_FANOUT~ +jdo[5] => ~NO_FANOUT~ +jdo[6] => ~NO_FANOUT~ +jdo[7] => ~NO_FANOUT~ +jdo[8] => ~NO_FANOUT~ +jdo[9] => ~NO_FANOUT~ +jdo[10] => ~NO_FANOUT~ +jdo[11] => ~NO_FANOUT~ +jdo[12] => ~NO_FANOUT~ +jdo[13] => ~NO_FANOUT~ +jdo[14] => ~NO_FANOUT~ +jdo[15] => ~NO_FANOUT~ +jrst_n => dct_count[0]~reg0.ACLR +jrst_n => dct_count[1]~reg0.ACLR +jrst_n => dct_count[2]~reg0.ACLR +jrst_n => dct_count[3]~reg0.ACLR +jrst_n => dct_buffer[0]~reg0.ACLR +jrst_n => dct_buffer[1]~reg0.ACLR +jrst_n => dct_buffer[2]~reg0.ACLR +jrst_n => dct_buffer[3]~reg0.ACLR +jrst_n => dct_buffer[4]~reg0.ACLR +jrst_n => dct_buffer[5]~reg0.ACLR +jrst_n => dct_buffer[6]~reg0.ACLR +jrst_n => dct_buffer[7]~reg0.ACLR +jrst_n => dct_buffer[8]~reg0.ACLR +jrst_n => dct_buffer[9]~reg0.ACLR +jrst_n => dct_buffer[10]~reg0.ACLR +jrst_n => dct_buffer[11]~reg0.ACLR +jrst_n => dct_buffer[12]~reg0.ACLR +jrst_n => dct_buffer[13]~reg0.ACLR +jrst_n => dct_buffer[14]~reg0.ACLR +jrst_n => dct_buffer[15]~reg0.ACLR +jrst_n => dct_buffer[16]~reg0.ACLR +jrst_n => dct_buffer[17]~reg0.ACLR +jrst_n => dct_buffer[18]~reg0.ACLR +jrst_n => dct_buffer[19]~reg0.ACLR +jrst_n => dct_buffer[20]~reg0.ACLR +jrst_n => dct_buffer[21]~reg0.ACLR +jrst_n => dct_buffer[22]~reg0.ACLR +jrst_n => dct_buffer[23]~reg0.ACLR +jrst_n => dct_buffer[24]~reg0.ACLR +jrst_n => dct_buffer[25]~reg0.ACLR +jrst_n => dct_buffer[26]~reg0.ACLR +jrst_n => dct_buffer[27]~reg0.ACLR +jrst_n => dct_buffer[28]~reg0.ACLR +jrst_n => dct_buffer[29]~reg0.ACLR +jrst_n => itm[0]~reg0.ACLR +jrst_n => itm[1]~reg0.ACLR +jrst_n => itm[2]~reg0.ACLR +jrst_n => itm[3]~reg0.ACLR +jrst_n => itm[4]~reg0.ACLR +jrst_n => itm[5]~reg0.ACLR +jrst_n => itm[6]~reg0.ACLR +jrst_n => itm[7]~reg0.ACLR +jrst_n => itm[8]~reg0.ACLR +jrst_n => itm[9]~reg0.ACLR +jrst_n => itm[10]~reg0.ACLR +jrst_n => itm[11]~reg0.ACLR +jrst_n => itm[12]~reg0.ACLR +jrst_n => itm[13]~reg0.ACLR +jrst_n => itm[14]~reg0.ACLR +jrst_n => itm[15]~reg0.ACLR +jrst_n => itm[16]~reg0.ACLR +jrst_n => itm[17]~reg0.ACLR +jrst_n => itm[18]~reg0.ACLR +jrst_n => itm[19]~reg0.ACLR +jrst_n => itm[20]~reg0.ACLR +jrst_n => itm[21]~reg0.ACLR +jrst_n => itm[22]~reg0.ACLR +jrst_n => itm[23]~reg0.ACLR +jrst_n => itm[24]~reg0.ACLR +jrst_n => itm[25]~reg0.ACLR +jrst_n => itm[26]~reg0.ACLR +jrst_n => itm[27]~reg0.ACLR +jrst_n => itm[28]~reg0.ACLR +jrst_n => itm[29]~reg0.ACLR +jrst_n => itm[30]~reg0.ACLR +jrst_n => itm[31]~reg0.ACLR +jrst_n => itm[32]~reg0.ACLR +jrst_n => itm[33]~reg0.ACLR +jrst_n => itm[34]~reg0.ACLR +jrst_n => itm[35]~reg0.ACLR +reset_n => d1_debugack.ACLR +take_action_tracectrl => ~NO_FANOUT~ +trc_enb => ~NO_FANOUT~ +xbrk_traceoff => ~NO_FANOUT~ +xbrk_traceon => ~NO_FANOUT~ +xbrk_wrap_traceoff => ~NO_FANOUT~ +dct_buffer[0] <= dct_buffer[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dct_buffer[1] <= dct_buffer[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dct_buffer[2] <= dct_buffer[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dct_buffer[3] <= dct_buffer[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dct_buffer[4] <= dct_buffer[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dct_buffer[5] <= dct_buffer[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dct_buffer[6] <= dct_buffer[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dct_buffer[7] <= dct_buffer[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dct_buffer[8] <= dct_buffer[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dct_buffer[9] <= dct_buffer[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dct_buffer[10] <= dct_buffer[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dct_buffer[11] <= dct_buffer[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dct_buffer[12] <= dct_buffer[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dct_buffer[13] <= dct_buffer[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dct_buffer[14] <= dct_buffer[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dct_buffer[15] <= dct_buffer[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dct_buffer[16] <= dct_buffer[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dct_buffer[17] <= dct_buffer[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dct_buffer[18] <= dct_buffer[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dct_buffer[19] <= dct_buffer[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dct_buffer[20] <= dct_buffer[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dct_buffer[21] <= dct_buffer[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dct_buffer[22] <= dct_buffer[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dct_buffer[23] <= dct_buffer[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dct_buffer[24] <= dct_buffer[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dct_buffer[25] <= dct_buffer[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dct_buffer[26] <= dct_buffer[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dct_buffer[27] <= dct_buffer[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dct_buffer[28] <= dct_buffer[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dct_buffer[29] <= dct_buffer[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dct_count[0] <= dct_count[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dct_count[1] <= dct_count[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dct_count[2] <= dct_count[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dct_count[3] <= dct_count[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +itm[0] <= itm[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +itm[1] <= itm[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +itm[2] <= itm[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +itm[3] <= itm[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +itm[4] <= itm[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +itm[5] <= itm[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +itm[6] <= itm[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +itm[7] <= itm[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE +itm[8] <= itm[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE +itm[9] <= itm[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE +itm[10] <= itm[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE +itm[11] <= itm[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE +itm[12] <= itm[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE +itm[13] <= itm[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE +itm[14] <= itm[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE +itm[15] <= itm[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE +itm[16] <= itm[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE +itm[17] <= itm[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE +itm[18] <= itm[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE +itm[19] <= itm[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE +itm[20] <= itm[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE +itm[21] <= itm[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE +itm[22] <= itm[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE +itm[23] <= itm[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE +itm[24] <= itm[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE +itm[25] <= itm[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE +itm[26] <= itm[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE +itm[27] <= itm[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE +itm[28] <= itm[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE +itm[29] <= itm[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE +itm[30] <= itm[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE +itm[31] <= itm[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE +itm[32] <= itm[32]~reg0.DB_MAX_OUTPUT_PORT_TYPE +itm[33] <= itm[33]~reg0.DB_MAX_OUTPUT_PORT_TYPE +itm[34] <= itm[34]~reg0.DB_MAX_OUTPUT_PORT_TYPE +itm[35] <= itm[35]~reg0.DB_MAX_OUTPUT_PORT_TYPE +trc_ctrl[0] <= +trc_ctrl[1] <= +trc_ctrl[2] <= +trc_ctrl[3] <= +trc_ctrl[4] <= +trc_ctrl[5] <= +trc_ctrl[6] <= +trc_ctrl[7] <= +trc_ctrl[8] <= +trc_ctrl[9] <= +trc_ctrl[10] <= +trc_ctrl[11] <= +trc_ctrl[12] <= +trc_ctrl[13] <= +trc_ctrl[14] <= +trc_ctrl[15] <= +trc_on <= + + +|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_dtrace:the_system_cpu_nios2_oci_dtrace +clk => dtm[0]~reg0.CLK +clk => dtm[1]~reg0.CLK +clk => dtm[2]~reg0.CLK +clk => dtm[3]~reg0.CLK +clk => dtm[4]~reg0.CLK +clk => dtm[5]~reg0.CLK +clk => dtm[6]~reg0.CLK +clk => dtm[7]~reg0.CLK +clk => dtm[8]~reg0.CLK +clk => dtm[9]~reg0.CLK +clk => dtm[10]~reg0.CLK +clk => dtm[11]~reg0.CLK +clk => dtm[12]~reg0.CLK +clk => dtm[13]~reg0.CLK +clk => dtm[14]~reg0.CLK +clk => dtm[15]~reg0.CLK +clk => dtm[16]~reg0.CLK +clk => dtm[17]~reg0.CLK +clk => dtm[18]~reg0.CLK +clk => dtm[19]~reg0.CLK +clk => dtm[20]~reg0.CLK +clk => dtm[21]~reg0.CLK +clk => dtm[22]~reg0.CLK +clk => dtm[23]~reg0.CLK +clk => dtm[24]~reg0.CLK +clk => dtm[25]~reg0.CLK +clk => dtm[26]~reg0.CLK +clk => dtm[27]~reg0.CLK +clk => dtm[28]~reg0.CLK +clk => dtm[29]~reg0.CLK +clk => dtm[30]~reg0.CLK +clk => dtm[31]~reg0.CLK +clk => dtm[32]~reg0.CLK +clk => dtm[33]~reg0.CLK +clk => dtm[34]~reg0.CLK +clk => dtm[35]~reg0.CLK +clk => atm[0]~reg0.CLK +clk => atm[1]~reg0.CLK +clk => atm[2]~reg0.CLK +clk => atm[3]~reg0.CLK +clk => atm[4]~reg0.CLK +clk => atm[5]~reg0.CLK +clk => atm[6]~reg0.CLK +clk => atm[7]~reg0.CLK +clk => atm[8]~reg0.CLK +clk => atm[9]~reg0.CLK +clk => atm[10]~reg0.CLK +clk => atm[11]~reg0.CLK +clk => atm[12]~reg0.CLK +clk => atm[13]~reg0.CLK +clk => atm[14]~reg0.CLK +clk => atm[15]~reg0.CLK +clk => atm[16]~reg0.CLK +clk => atm[17]~reg0.CLK +clk => atm[18]~reg0.CLK +clk => atm[19]~reg0.CLK +clk => atm[20]~reg0.CLK +clk => atm[21]~reg0.CLK +clk => atm[22]~reg0.CLK +clk => atm[23]~reg0.CLK +clk => atm[24]~reg0.CLK +clk => atm[25]~reg0.CLK +clk => atm[26]~reg0.CLK +clk => atm[27]~reg0.CLK +clk => atm[28]~reg0.CLK +clk => atm[29]~reg0.CLK +clk => atm[30]~reg0.CLK +clk => atm[31]~reg0.CLK +clk => atm[32]~reg0.CLK +clk => atm[33]~reg0.CLK +clk => atm[34]~reg0.CLK +clk => atm[35]~reg0.CLK +cpu_d_address[0] => ~NO_FANOUT~ +cpu_d_address[1] => ~NO_FANOUT~ +cpu_d_address[2] => ~NO_FANOUT~ +cpu_d_address[3] => ~NO_FANOUT~ +cpu_d_address[4] => ~NO_FANOUT~ +cpu_d_address[5] => ~NO_FANOUT~ +cpu_d_address[6] => ~NO_FANOUT~ +cpu_d_address[7] => ~NO_FANOUT~ +cpu_d_address[8] => ~NO_FANOUT~ +cpu_d_address[9] => ~NO_FANOUT~ +cpu_d_address[10] => ~NO_FANOUT~ +cpu_d_address[11] => ~NO_FANOUT~ +cpu_d_address[12] => ~NO_FANOUT~ +cpu_d_address[13] => ~NO_FANOUT~ +cpu_d_address[14] => ~NO_FANOUT~ +cpu_d_address[15] => ~NO_FANOUT~ +cpu_d_address[16] => ~NO_FANOUT~ +cpu_d_address[17] => ~NO_FANOUT~ +cpu_d_address[18] => ~NO_FANOUT~ +cpu_d_address[19] => ~NO_FANOUT~ +cpu_d_address[20] => ~NO_FANOUT~ +cpu_d_address[21] => ~NO_FANOUT~ +cpu_d_address[22] => ~NO_FANOUT~ +cpu_d_address[23] => ~NO_FANOUT~ +cpu_d_address[24] => ~NO_FANOUT~ +cpu_d_address[25] => ~NO_FANOUT~ +cpu_d_read => ~NO_FANOUT~ +cpu_d_readdata[0] => ~NO_FANOUT~ +cpu_d_readdata[1] => ~NO_FANOUT~ +cpu_d_readdata[2] => ~NO_FANOUT~ +cpu_d_readdata[3] => ~NO_FANOUT~ +cpu_d_readdata[4] => ~NO_FANOUT~ +cpu_d_readdata[5] => ~NO_FANOUT~ +cpu_d_readdata[6] => ~NO_FANOUT~ +cpu_d_readdata[7] => ~NO_FANOUT~ +cpu_d_readdata[8] => ~NO_FANOUT~ +cpu_d_readdata[9] => ~NO_FANOUT~ +cpu_d_readdata[10] => ~NO_FANOUT~ +cpu_d_readdata[11] => ~NO_FANOUT~ +cpu_d_readdata[12] => ~NO_FANOUT~ +cpu_d_readdata[13] => ~NO_FANOUT~ +cpu_d_readdata[14] => ~NO_FANOUT~ +cpu_d_readdata[15] => ~NO_FANOUT~ +cpu_d_readdata[16] => ~NO_FANOUT~ +cpu_d_readdata[17] => ~NO_FANOUT~ +cpu_d_readdata[18] => ~NO_FANOUT~ +cpu_d_readdata[19] => ~NO_FANOUT~ +cpu_d_readdata[20] => ~NO_FANOUT~ +cpu_d_readdata[21] => ~NO_FANOUT~ +cpu_d_readdata[22] => ~NO_FANOUT~ +cpu_d_readdata[23] => ~NO_FANOUT~ +cpu_d_readdata[24] => ~NO_FANOUT~ +cpu_d_readdata[25] => ~NO_FANOUT~ +cpu_d_readdata[26] => ~NO_FANOUT~ +cpu_d_readdata[27] => ~NO_FANOUT~ +cpu_d_readdata[28] => ~NO_FANOUT~ +cpu_d_readdata[29] => ~NO_FANOUT~ +cpu_d_readdata[30] => ~NO_FANOUT~ +cpu_d_readdata[31] => ~NO_FANOUT~ +cpu_d_wait => ~NO_FANOUT~ +cpu_d_write => ~NO_FANOUT~ +cpu_d_writedata[0] => ~NO_FANOUT~ +cpu_d_writedata[1] => ~NO_FANOUT~ +cpu_d_writedata[2] => ~NO_FANOUT~ +cpu_d_writedata[3] => ~NO_FANOUT~ +cpu_d_writedata[4] => ~NO_FANOUT~ +cpu_d_writedata[5] => ~NO_FANOUT~ +cpu_d_writedata[6] => ~NO_FANOUT~ +cpu_d_writedata[7] => ~NO_FANOUT~ +cpu_d_writedata[8] => ~NO_FANOUT~ +cpu_d_writedata[9] => ~NO_FANOUT~ +cpu_d_writedata[10] => ~NO_FANOUT~ +cpu_d_writedata[11] => ~NO_FANOUT~ +cpu_d_writedata[12] => ~NO_FANOUT~ +cpu_d_writedata[13] => ~NO_FANOUT~ +cpu_d_writedata[14] => ~NO_FANOUT~ +cpu_d_writedata[15] => ~NO_FANOUT~ +cpu_d_writedata[16] => ~NO_FANOUT~ +cpu_d_writedata[17] => ~NO_FANOUT~ +cpu_d_writedata[18] => ~NO_FANOUT~ +cpu_d_writedata[19] => ~NO_FANOUT~ +cpu_d_writedata[20] => ~NO_FANOUT~ +cpu_d_writedata[21] => ~NO_FANOUT~ +cpu_d_writedata[22] => ~NO_FANOUT~ +cpu_d_writedata[23] => ~NO_FANOUT~ +cpu_d_writedata[24] => ~NO_FANOUT~ +cpu_d_writedata[25] => ~NO_FANOUT~ +cpu_d_writedata[26] => ~NO_FANOUT~ +cpu_d_writedata[27] => ~NO_FANOUT~ +cpu_d_writedata[28] => ~NO_FANOUT~ +cpu_d_writedata[29] => ~NO_FANOUT~ +cpu_d_writedata[30] => ~NO_FANOUT~ +cpu_d_writedata[31] => ~NO_FANOUT~ +jrst_n => dtm[0]~reg0.ACLR +jrst_n => dtm[1]~reg0.ACLR +jrst_n => dtm[2]~reg0.ACLR +jrst_n => dtm[3]~reg0.ACLR +jrst_n => dtm[4]~reg0.ACLR +jrst_n => dtm[5]~reg0.ACLR +jrst_n => dtm[6]~reg0.ACLR +jrst_n => dtm[7]~reg0.ACLR +jrst_n => dtm[8]~reg0.ACLR +jrst_n => dtm[9]~reg0.ACLR +jrst_n => dtm[10]~reg0.ACLR +jrst_n => dtm[11]~reg0.ACLR +jrst_n => dtm[12]~reg0.ACLR +jrst_n => dtm[13]~reg0.ACLR +jrst_n => dtm[14]~reg0.ACLR +jrst_n => dtm[15]~reg0.ACLR +jrst_n => dtm[16]~reg0.ACLR +jrst_n => dtm[17]~reg0.ACLR +jrst_n => dtm[18]~reg0.ACLR +jrst_n => dtm[19]~reg0.ACLR +jrst_n => dtm[20]~reg0.ACLR +jrst_n => dtm[21]~reg0.ACLR +jrst_n => dtm[22]~reg0.ACLR +jrst_n => dtm[23]~reg0.ACLR +jrst_n => dtm[24]~reg0.ACLR +jrst_n => dtm[25]~reg0.ACLR +jrst_n => dtm[26]~reg0.ACLR +jrst_n => dtm[27]~reg0.ACLR +jrst_n => dtm[28]~reg0.ACLR +jrst_n => dtm[29]~reg0.ACLR +jrst_n => dtm[30]~reg0.ACLR +jrst_n => dtm[31]~reg0.ACLR +jrst_n => dtm[32]~reg0.ACLR +jrst_n => dtm[33]~reg0.ACLR +jrst_n => dtm[34]~reg0.ACLR +jrst_n => dtm[35]~reg0.ACLR +jrst_n => atm[0]~reg0.ACLR +jrst_n => atm[1]~reg0.ACLR +jrst_n => atm[2]~reg0.ACLR +jrst_n => atm[3]~reg0.ACLR +jrst_n => atm[4]~reg0.ACLR +jrst_n => atm[5]~reg0.ACLR +jrst_n => atm[6]~reg0.ACLR +jrst_n => atm[7]~reg0.ACLR +jrst_n => atm[8]~reg0.ACLR +jrst_n => atm[9]~reg0.ACLR +jrst_n => atm[10]~reg0.ACLR +jrst_n => atm[11]~reg0.ACLR +jrst_n => atm[12]~reg0.ACLR +jrst_n => atm[13]~reg0.ACLR +jrst_n => atm[14]~reg0.ACLR +jrst_n => atm[15]~reg0.ACLR +jrst_n => atm[16]~reg0.ACLR +jrst_n => atm[17]~reg0.ACLR +jrst_n => atm[18]~reg0.ACLR +jrst_n => atm[19]~reg0.ACLR +jrst_n => atm[20]~reg0.ACLR +jrst_n => atm[21]~reg0.ACLR +jrst_n => atm[22]~reg0.ACLR +jrst_n => atm[23]~reg0.ACLR +jrst_n => atm[24]~reg0.ACLR +jrst_n => atm[25]~reg0.ACLR +jrst_n => atm[26]~reg0.ACLR +jrst_n => atm[27]~reg0.ACLR +jrst_n => atm[28]~reg0.ACLR +jrst_n => atm[29]~reg0.ACLR +jrst_n => atm[30]~reg0.ACLR +jrst_n => atm[31]~reg0.ACLR +jrst_n => atm[32]~reg0.ACLR +jrst_n => atm[33]~reg0.ACLR +jrst_n => atm[34]~reg0.ACLR +jrst_n => atm[35]~reg0.ACLR +trc_ctrl[0] => trc_ctrl[0].IN1 +trc_ctrl[1] => trc_ctrl[1].IN1 +trc_ctrl[2] => trc_ctrl[2].IN1 +trc_ctrl[3] => trc_ctrl[3].IN1 +trc_ctrl[4] => trc_ctrl[4].IN1 +trc_ctrl[5] => trc_ctrl[5].IN1 +trc_ctrl[6] => trc_ctrl[6].IN1 +trc_ctrl[7] => trc_ctrl[7].IN1 +trc_ctrl[8] => trc_ctrl[8].IN1 +trc_ctrl[9] => ~NO_FANOUT~ +trc_ctrl[10] => ~NO_FANOUT~ +trc_ctrl[11] => ~NO_FANOUT~ +trc_ctrl[12] => ~NO_FANOUT~ +trc_ctrl[13] => ~NO_FANOUT~ +trc_ctrl[14] => ~NO_FANOUT~ +trc_ctrl[15] => ~NO_FANOUT~ +atm[0] <= atm[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +atm[1] <= atm[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +atm[2] <= atm[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +atm[3] <= atm[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +atm[4] <= atm[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +atm[5] <= atm[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +atm[6] <= atm[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +atm[7] <= atm[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE +atm[8] <= atm[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE +atm[9] <= atm[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE +atm[10] <= atm[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE +atm[11] <= atm[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE +atm[12] <= atm[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE +atm[13] <= atm[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE +atm[14] <= atm[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE +atm[15] <= atm[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE +atm[16] <= atm[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE +atm[17] <= atm[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE +atm[18] <= atm[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE +atm[19] <= atm[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE +atm[20] <= atm[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE +atm[21] <= atm[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE +atm[22] <= atm[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE +atm[23] <= atm[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE +atm[24] <= atm[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE +atm[25] <= atm[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE +atm[26] <= atm[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE +atm[27] <= atm[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE +atm[28] <= atm[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE +atm[29] <= atm[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE +atm[30] <= atm[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE +atm[31] <= atm[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE +atm[32] <= atm[32]~reg0.DB_MAX_OUTPUT_PORT_TYPE +atm[33] <= atm[33]~reg0.DB_MAX_OUTPUT_PORT_TYPE +atm[34] <= atm[34]~reg0.DB_MAX_OUTPUT_PORT_TYPE +atm[35] <= atm[35]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dtm[0] <= dtm[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dtm[1] <= dtm[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dtm[2] <= dtm[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dtm[3] <= dtm[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dtm[4] <= dtm[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dtm[5] <= dtm[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dtm[6] <= dtm[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dtm[7] <= dtm[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dtm[8] <= dtm[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dtm[9] <= dtm[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dtm[10] <= dtm[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dtm[11] <= dtm[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dtm[12] <= dtm[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dtm[13] <= dtm[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dtm[14] <= dtm[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dtm[15] <= dtm[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dtm[16] <= dtm[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dtm[17] <= dtm[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dtm[18] <= dtm[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dtm[19] <= dtm[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dtm[20] <= dtm[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dtm[21] <= dtm[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dtm[22] <= dtm[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dtm[23] <= dtm[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dtm[24] <= dtm[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dtm[25] <= dtm[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dtm[26] <= dtm[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dtm[27] <= dtm[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dtm[28] <= dtm[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dtm[29] <= dtm[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dtm[30] <= dtm[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dtm[31] <= dtm[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dtm[32] <= dtm[32]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dtm[33] <= dtm[33]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dtm[34] <= dtm[34]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dtm[35] <= dtm[35]~reg0.DB_MAX_OUTPUT_PORT_TYPE + + +|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_dtrace:the_system_cpu_nios2_oci_dtrace|system_cpu_nios2_oci_td_mode:system_cpu_nios2_oci_trc_ctrl_td_mode +ctrl[0] => ~NO_FANOUT~ +ctrl[1] => ~NO_FANOUT~ +ctrl[2] => ~NO_FANOUT~ +ctrl[3] => ~NO_FANOUT~ +ctrl[4] => ~NO_FANOUT~ +ctrl[5] => Decoder0.IN2 +ctrl[5] => td_mode[3].DATAIN +ctrl[6] => Decoder0.IN1 +ctrl[6] => Decoder1.IN1 +ctrl[6] => td_mode[2].DATAIN +ctrl[7] => Decoder0.IN0 +ctrl[7] => Decoder1.IN0 +ctrl[8] => ~NO_FANOUT~ +td_mode[0] <= Decoder1.DB_MAX_OUTPUT_PORT_TYPE +td_mode[1] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE +td_mode[2] <= ctrl[6].DB_MAX_OUTPUT_PORT_TYPE +td_mode[3] <= ctrl[5].DB_MAX_OUTPUT_PORT_TYPE + + +|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_fifo:the_system_cpu_nios2_oci_fifo +atm[0] => ~NO_FANOUT~ +atm[1] => ~NO_FANOUT~ +atm[2] => ~NO_FANOUT~ +atm[3] => ~NO_FANOUT~ +atm[4] => ~NO_FANOUT~ +atm[5] => ~NO_FANOUT~ +atm[6] => ~NO_FANOUT~ +atm[7] => ~NO_FANOUT~ +atm[8] => ~NO_FANOUT~ +atm[9] => ~NO_FANOUT~ +atm[10] => ~NO_FANOUT~ +atm[11] => ~NO_FANOUT~ +atm[12] => ~NO_FANOUT~ +atm[13] => ~NO_FANOUT~ +atm[14] => ~NO_FANOUT~ +atm[15] => ~NO_FANOUT~ +atm[16] => ~NO_FANOUT~ +atm[17] => ~NO_FANOUT~ +atm[18] => ~NO_FANOUT~ +atm[19] => ~NO_FANOUT~ +atm[20] => ~NO_FANOUT~ +atm[21] => ~NO_FANOUT~ +atm[22] => ~NO_FANOUT~ +atm[23] => ~NO_FANOUT~ +atm[24] => ~NO_FANOUT~ +atm[25] => ~NO_FANOUT~ +atm[26] => ~NO_FANOUT~ +atm[27] => ~NO_FANOUT~ +atm[28] => ~NO_FANOUT~ +atm[29] => ~NO_FANOUT~ +atm[30] => ~NO_FANOUT~ +atm[31] => ~NO_FANOUT~ +atm[32] => WideOr1.IN0 +atm[33] => WideOr1.IN1 +atm[34] => WideOr1.IN2 +atm[35] => WideOr1.IN3 +clk => fifocount[0].CLK +clk => fifocount[1].CLK +clk => fifocount[2].CLK +clk => fifocount[3].CLK +clk => fifocount[4].CLK +dbrk_traceme => trc_this.IN1 +dbrk_traceoff => trc_this.IN0 +dbrk_traceon => trc_this.IN1 +dct_buffer[0] => dct_buffer[0].IN1 +dct_buffer[1] => dct_buffer[1].IN1 +dct_buffer[2] => dct_buffer[2].IN1 +dct_buffer[3] => dct_buffer[3].IN1 +dct_buffer[4] => dct_buffer[4].IN1 +dct_buffer[5] => dct_buffer[5].IN1 +dct_buffer[6] => dct_buffer[6].IN1 +dct_buffer[7] => dct_buffer[7].IN1 +dct_buffer[8] => dct_buffer[8].IN1 +dct_buffer[9] => dct_buffer[9].IN1 +dct_buffer[10] => dct_buffer[10].IN1 +dct_buffer[11] => dct_buffer[11].IN1 +dct_buffer[12] => dct_buffer[12].IN1 +dct_buffer[13] => dct_buffer[13].IN1 +dct_buffer[14] => dct_buffer[14].IN1 +dct_buffer[15] => dct_buffer[15].IN1 +dct_buffer[16] => dct_buffer[16].IN1 +dct_buffer[17] => dct_buffer[17].IN1 +dct_buffer[18] => dct_buffer[18].IN1 +dct_buffer[19] => dct_buffer[19].IN1 +dct_buffer[20] => dct_buffer[20].IN1 +dct_buffer[21] => dct_buffer[21].IN1 +dct_buffer[22] => dct_buffer[22].IN1 +dct_buffer[23] => dct_buffer[23].IN1 +dct_buffer[24] => dct_buffer[24].IN1 +dct_buffer[25] => dct_buffer[25].IN1 +dct_buffer[26] => dct_buffer[26].IN1 +dct_buffer[27] => dct_buffer[27].IN1 +dct_buffer[28] => dct_buffer[28].IN1 +dct_buffer[29] => dct_buffer[29].IN1 +dct_count[0] => dct_count[0].IN1 +dct_count[1] => dct_count[1].IN1 +dct_count[2] => dct_count[2].IN1 +dct_count[3] => dct_count[3].IN1 +dtm[0] => ~NO_FANOUT~ +dtm[1] => ~NO_FANOUT~ +dtm[2] => ~NO_FANOUT~ +dtm[3] => ~NO_FANOUT~ +dtm[4] => ~NO_FANOUT~ +dtm[5] => ~NO_FANOUT~ +dtm[6] => ~NO_FANOUT~ +dtm[7] => ~NO_FANOUT~ +dtm[8] => ~NO_FANOUT~ +dtm[9] => ~NO_FANOUT~ +dtm[10] => ~NO_FANOUT~ +dtm[11] => ~NO_FANOUT~ +dtm[12] => ~NO_FANOUT~ +dtm[13] => ~NO_FANOUT~ +dtm[14] => ~NO_FANOUT~ +dtm[15] => ~NO_FANOUT~ +dtm[16] => ~NO_FANOUT~ +dtm[17] => ~NO_FANOUT~ +dtm[18] => ~NO_FANOUT~ +dtm[19] => ~NO_FANOUT~ +dtm[20] => ~NO_FANOUT~ +dtm[21] => ~NO_FANOUT~ +dtm[22] => ~NO_FANOUT~ +dtm[23] => ~NO_FANOUT~ +dtm[24] => ~NO_FANOUT~ +dtm[25] => ~NO_FANOUT~ +dtm[26] => ~NO_FANOUT~ +dtm[27] => ~NO_FANOUT~ +dtm[28] => ~NO_FANOUT~ +dtm[29] => ~NO_FANOUT~ +dtm[30] => ~NO_FANOUT~ +dtm[31] => ~NO_FANOUT~ +dtm[32] => WideOr2.IN0 +dtm[33] => WideOr2.IN1 +dtm[34] => WideOr2.IN2 +dtm[35] => WideOr2.IN3 +itm[0] => tw[0].DATAIN +itm[1] => tw[1].DATAIN +itm[2] => tw[2].DATAIN +itm[3] => tw[3].DATAIN +itm[4] => tw[4].DATAIN +itm[5] => tw[5].DATAIN +itm[6] => tw[6].DATAIN +itm[7] => tw[7].DATAIN +itm[8] => tw[8].DATAIN +itm[9] => tw[9].DATAIN +itm[10] => tw[10].DATAIN +itm[11] => tw[11].DATAIN +itm[12] => tw[12].DATAIN +itm[13] => tw[13].DATAIN +itm[14] => tw[14].DATAIN +itm[15] => tw[15].DATAIN +itm[16] => tw[16].DATAIN +itm[17] => tw[17].DATAIN +itm[18] => tw[18].DATAIN +itm[19] => tw[19].DATAIN +itm[20] => tw[20].DATAIN +itm[21] => tw[21].DATAIN +itm[22] => tw[22].DATAIN +itm[23] => tw[23].DATAIN +itm[24] => tw[24].DATAIN +itm[25] => tw[25].DATAIN +itm[26] => tw[26].DATAIN +itm[27] => tw[27].DATAIN +itm[28] => tw[28].DATAIN +itm[29] => tw[29].DATAIN +itm[30] => tw[30].DATAIN +itm[31] => tw[31].DATAIN +itm[32] => WideOr0.IN0 +itm[32] => tw[32].DATAIN +itm[33] => WideOr0.IN1 +itm[33] => tw[33].DATAIN +itm[34] => WideOr0.IN2 +itm[34] => tw[34].DATAIN +itm[35] => WideOr0.IN3 +itm[35] => tw[35].DATAIN +jrst_n => fifocount[0].ACLR +jrst_n => fifocount[1].ACLR +jrst_n => fifocount[2].ACLR +jrst_n => fifocount[3].ACLR +jrst_n => fifocount[4].ACLR +reset_n => ~NO_FANOUT~ +test_ending => test_ending.IN1 +test_has_ended => test_has_ended.IN1 +trc_on => trc_this.IN1 +tw[0] <= itm[0].DB_MAX_OUTPUT_PORT_TYPE +tw[1] <= itm[1].DB_MAX_OUTPUT_PORT_TYPE +tw[2] <= itm[2].DB_MAX_OUTPUT_PORT_TYPE +tw[3] <= itm[3].DB_MAX_OUTPUT_PORT_TYPE +tw[4] <= itm[4].DB_MAX_OUTPUT_PORT_TYPE +tw[5] <= itm[5].DB_MAX_OUTPUT_PORT_TYPE +tw[6] <= itm[6].DB_MAX_OUTPUT_PORT_TYPE +tw[7] <= itm[7].DB_MAX_OUTPUT_PORT_TYPE +tw[8] <= itm[8].DB_MAX_OUTPUT_PORT_TYPE +tw[9] <= itm[9].DB_MAX_OUTPUT_PORT_TYPE +tw[10] <= itm[10].DB_MAX_OUTPUT_PORT_TYPE +tw[11] <= itm[11].DB_MAX_OUTPUT_PORT_TYPE +tw[12] <= itm[12].DB_MAX_OUTPUT_PORT_TYPE +tw[13] <= itm[13].DB_MAX_OUTPUT_PORT_TYPE +tw[14] <= itm[14].DB_MAX_OUTPUT_PORT_TYPE +tw[15] <= itm[15].DB_MAX_OUTPUT_PORT_TYPE +tw[16] <= itm[16].DB_MAX_OUTPUT_PORT_TYPE +tw[17] <= itm[17].DB_MAX_OUTPUT_PORT_TYPE +tw[18] <= itm[18].DB_MAX_OUTPUT_PORT_TYPE +tw[19] <= itm[19].DB_MAX_OUTPUT_PORT_TYPE +tw[20] <= itm[20].DB_MAX_OUTPUT_PORT_TYPE +tw[21] <= itm[21].DB_MAX_OUTPUT_PORT_TYPE +tw[22] <= itm[22].DB_MAX_OUTPUT_PORT_TYPE +tw[23] <= itm[23].DB_MAX_OUTPUT_PORT_TYPE +tw[24] <= itm[24].DB_MAX_OUTPUT_PORT_TYPE +tw[25] <= itm[25].DB_MAX_OUTPUT_PORT_TYPE +tw[26] <= itm[26].DB_MAX_OUTPUT_PORT_TYPE +tw[27] <= itm[27].DB_MAX_OUTPUT_PORT_TYPE +tw[28] <= itm[28].DB_MAX_OUTPUT_PORT_TYPE +tw[29] <= itm[29].DB_MAX_OUTPUT_PORT_TYPE +tw[30] <= itm[30].DB_MAX_OUTPUT_PORT_TYPE +tw[31] <= itm[31].DB_MAX_OUTPUT_PORT_TYPE +tw[32] <= itm[32].DB_MAX_OUTPUT_PORT_TYPE +tw[33] <= itm[33].DB_MAX_OUTPUT_PORT_TYPE +tw[34] <= itm[34].DB_MAX_OUTPUT_PORT_TYPE +tw[35] <= itm[35].DB_MAX_OUTPUT_PORT_TYPE + + +|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_fifo:the_system_cpu_nios2_oci_fifo|system_cpu_nios2_oci_compute_tm_count:system_cpu_nios2_oci_compute_tm_count_tm_count +atm_valid => Decoder0.IN1 +dtm_valid => Decoder0.IN2 +itm_valid => Decoder0.IN0 +compute_tm_count[0] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE +compute_tm_count[1] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE + + +|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_fifo:the_system_cpu_nios2_oci_fifo|system_cpu_nios2_oci_fifowp_inc:system_cpu_nios2_oci_fifowp_inc_fifowp +free2 => always0.IN1 +free3 => always0.IN1 +tm_count[0] => LessThan0.IN4 +tm_count[0] => LessThan1.IN4 +tm_count[0] => Equal0.IN1 +tm_count[1] => LessThan0.IN3 +tm_count[1] => LessThan1.IN3 +tm_count[1] => Equal0.IN0 +fifowp_inc[0] <= fifowp_inc.DB_MAX_OUTPUT_PORT_TYPE +fifowp_inc[1] <= fifowp_inc.DB_MAX_OUTPUT_PORT_TYPE +fifowp_inc[2] <= +fifowp_inc[3] <= + + +|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_fifo:the_system_cpu_nios2_oci_fifo|system_cpu_nios2_oci_fifocount_inc:system_cpu_nios2_oci_fifocount_inc_fifocount +empty => fifocount_inc.OUTPUTSELECT +empty => fifocount_inc.OUTPUTSELECT +empty => fifocount_inc.OUTPUTSELECT +empty => fifocount_inc.OUTPUTSELECT +empty => fifocount_inc.OUTPUTSELECT +free2 => always0.IN1 +free3 => always0.IN1 +tm_count[0] => LessThan0.IN4 +tm_count[0] => LessThan1.IN4 +tm_count[0] => fifocount_inc.DATAB +tm_count[0] => Equal0.IN1 +tm_count[1] => LessThan0.IN3 +tm_count[1] => LessThan1.IN3 +tm_count[1] => fifocount_inc.DATAB +tm_count[1] => Equal0.IN0 +fifocount_inc[0] <= fifocount_inc.DB_MAX_OUTPUT_PORT_TYPE +fifocount_inc[1] <= fifocount_inc.DB_MAX_OUTPUT_PORT_TYPE +fifocount_inc[2] <= fifocount_inc.DB_MAX_OUTPUT_PORT_TYPE +fifocount_inc[3] <= fifocount_inc.DB_MAX_OUTPUT_PORT_TYPE +fifocount_inc[4] <= fifocount_inc.DB_MAX_OUTPUT_PORT_TYPE + + +|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_fifo:the_system_cpu_nios2_oci_fifo|system_cpu_oci_test_bench:the_system_cpu_oci_test_bench +dct_buffer[0] => ~NO_FANOUT~ +dct_buffer[1] => ~NO_FANOUT~ +dct_buffer[2] => ~NO_FANOUT~ +dct_buffer[3] => ~NO_FANOUT~ +dct_buffer[4] => ~NO_FANOUT~ +dct_buffer[5] => ~NO_FANOUT~ +dct_buffer[6] => ~NO_FANOUT~ +dct_buffer[7] => ~NO_FANOUT~ +dct_buffer[8] => ~NO_FANOUT~ +dct_buffer[9] => ~NO_FANOUT~ +dct_buffer[10] => ~NO_FANOUT~ +dct_buffer[11] => ~NO_FANOUT~ +dct_buffer[12] => ~NO_FANOUT~ +dct_buffer[13] => ~NO_FANOUT~ +dct_buffer[14] => ~NO_FANOUT~ +dct_buffer[15] => ~NO_FANOUT~ +dct_buffer[16] => ~NO_FANOUT~ +dct_buffer[17] => ~NO_FANOUT~ +dct_buffer[18] => ~NO_FANOUT~ +dct_buffer[19] => ~NO_FANOUT~ +dct_buffer[20] => ~NO_FANOUT~ +dct_buffer[21] => ~NO_FANOUT~ +dct_buffer[22] => ~NO_FANOUT~ +dct_buffer[23] => ~NO_FANOUT~ +dct_buffer[24] => ~NO_FANOUT~ +dct_buffer[25] => ~NO_FANOUT~ +dct_buffer[26] => ~NO_FANOUT~ +dct_buffer[27] => ~NO_FANOUT~ +dct_buffer[28] => ~NO_FANOUT~ +dct_buffer[29] => ~NO_FANOUT~ +dct_count[0] => ~NO_FANOUT~ +dct_count[1] => ~NO_FANOUT~ +dct_count[2] => ~NO_FANOUT~ +dct_count[3] => ~NO_FANOUT~ +test_ending => ~NO_FANOUT~ +test_has_ended => ~NO_FANOUT~ + + +|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_pib:the_system_cpu_nios2_oci_pib +clk => ~NO_FANOUT~ +clkx2 => ~NO_FANOUT~ +jrst_n => ~NO_FANOUT~ +tw[0] => ~NO_FANOUT~ +tw[1] => ~NO_FANOUT~ +tw[2] => ~NO_FANOUT~ +tw[3] => ~NO_FANOUT~ +tw[4] => ~NO_FANOUT~ +tw[5] => ~NO_FANOUT~ +tw[6] => ~NO_FANOUT~ +tw[7] => ~NO_FANOUT~ +tw[8] => ~NO_FANOUT~ +tw[9] => ~NO_FANOUT~ +tw[10] => ~NO_FANOUT~ +tw[11] => ~NO_FANOUT~ +tw[12] => ~NO_FANOUT~ +tw[13] => ~NO_FANOUT~ +tw[14] => ~NO_FANOUT~ +tw[15] => ~NO_FANOUT~ +tw[16] => ~NO_FANOUT~ +tw[17] => ~NO_FANOUT~ +tw[18] => ~NO_FANOUT~ +tw[19] => ~NO_FANOUT~ +tw[20] => ~NO_FANOUT~ +tw[21] => ~NO_FANOUT~ +tw[22] => ~NO_FANOUT~ +tw[23] => ~NO_FANOUT~ +tw[24] => ~NO_FANOUT~ +tw[25] => ~NO_FANOUT~ +tw[26] => ~NO_FANOUT~ +tw[27] => ~NO_FANOUT~ +tw[28] => ~NO_FANOUT~ +tw[29] => ~NO_FANOUT~ +tw[30] => ~NO_FANOUT~ +tw[31] => ~NO_FANOUT~ +tw[32] => ~NO_FANOUT~ +tw[33] => ~NO_FANOUT~ +tw[34] => ~NO_FANOUT~ +tw[35] => ~NO_FANOUT~ +tr_clk <= +tr_data[0] <= +tr_data[1] <= +tr_data[2] <= +tr_data[3] <= +tr_data[4] <= +tr_data[5] <= +tr_data[6] <= +tr_data[7] <= +tr_data[8] <= +tr_data[9] <= +tr_data[10] <= +tr_data[11] <= +tr_data[12] <= +tr_data[13] <= +tr_data[14] <= +tr_data[15] <= +tr_data[16] <= +tr_data[17] <= + + +|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im +clk => clk.IN2 +jdo[0] => ~NO_FANOUT~ +jdo[1] => jdo[1].IN1 +jdo[2] => jdo[2].IN1 +jdo[3] => jdo[3].IN1 +jdo[4] => jdo[4].IN1 +jdo[5] => jdo[5].IN1 +jdo[6] => jdo[6].IN1 +jdo[7] => jdo[7].IN1 +jdo[8] => jdo[8].IN1 +jdo[9] => jdo[9].IN1 +jdo[10] => jdo[10].IN1 +jdo[11] => jdo[11].IN1 +jdo[12] => jdo[12].IN1 +jdo[13] => jdo[13].IN1 +jdo[14] => jdo[14].IN1 +jdo[15] => jdo[15].IN1 +jdo[16] => jdo[16].IN1 +jdo[17] => jdo[17].IN1 +jdo[18] => jdo[18].IN1 +jdo[19] => jdo[19].IN1 +jdo[20] => jdo[20].IN1 +jdo[21] => jdo[21].IN1 +jdo[22] => jdo[22].IN1 +jdo[23] => jdo[23].IN1 +jdo[24] => jdo[24].IN1 +jdo[25] => jdo[25].IN1 +jdo[26] => jdo[26].IN1 +jdo[27] => jdo[27].IN1 +jdo[28] => jdo[28].IN1 +jdo[29] => jdo[29].IN1 +jdo[30] => jdo[30].IN1 +jdo[31] => jdo[31].IN1 +jdo[32] => jdo[32].IN1 +jdo[33] => jdo[33].IN1 +jdo[34] => jdo[34].IN1 +jdo[35] => jdo[35].IN1 +jdo[36] => jdo[36].IN1 +jdo[37] => ~NO_FANOUT~ +jrst_n => trc_wrap~reg0.ACLR +jrst_n => trc_im_addr[0]~reg0.ACLR +jrst_n => trc_im_addr[1]~reg0.ACLR +jrst_n => trc_im_addr[2]~reg0.ACLR +jrst_n => trc_im_addr[3]~reg0.ACLR +jrst_n => trc_im_addr[4]~reg0.ACLR +jrst_n => trc_im_addr[5]~reg0.ACLR +jrst_n => trc_im_addr[6]~reg0.ACLR +reset_n => trc_jtag_addr[0].ACLR +reset_n => trc_jtag_addr[1].ACLR +reset_n => trc_jtag_addr[2].ACLR +reset_n => trc_jtag_addr[3].ACLR +reset_n => trc_jtag_addr[4].ACLR +reset_n => trc_jtag_addr[5].ACLR +reset_n => trc_jtag_addr[6].ACLR +reset_n => trc_jtag_addr[7].ACLR +reset_n => trc_jtag_addr[8].ACLR +reset_n => trc_jtag_addr[9].ACLR +reset_n => trc_jtag_addr[10].ACLR +reset_n => trc_jtag_addr[11].ACLR +reset_n => trc_jtag_addr[12].ACLR +reset_n => trc_jtag_addr[13].ACLR +reset_n => trc_jtag_addr[14].ACLR +reset_n => trc_jtag_addr[15].ACLR +reset_n => trc_jtag_addr[16].ACLR +take_action_tracectrl => ~NO_FANOUT~ +take_action_tracemem_a => always1.IN0 +take_action_tracemem_a => trc_jtag_addr.OUTPUTSELECT +take_action_tracemem_a => trc_jtag_addr.OUTPUTSELECT +take_action_tracemem_a => trc_jtag_addr.OUTPUTSELECT +take_action_tracemem_a => trc_jtag_addr.OUTPUTSELECT +take_action_tracemem_a => trc_jtag_addr.OUTPUTSELECT +take_action_tracemem_a => trc_jtag_addr.OUTPUTSELECT +take_action_tracemem_a => trc_jtag_addr.OUTPUTSELECT +take_action_tracemem_a => trc_jtag_addr.OUTPUTSELECT +take_action_tracemem_a => trc_jtag_addr.OUTPUTSELECT +take_action_tracemem_a => trc_jtag_addr.OUTPUTSELECT +take_action_tracemem_a => trc_jtag_addr.OUTPUTSELECT +take_action_tracemem_a => trc_jtag_addr.OUTPUTSELECT +take_action_tracemem_a => trc_jtag_addr.OUTPUTSELECT +take_action_tracemem_a => trc_jtag_addr.OUTPUTSELECT +take_action_tracemem_a => trc_jtag_addr.OUTPUTSELECT +take_action_tracemem_a => trc_jtag_addr.OUTPUTSELECT +take_action_tracemem_a => trc_jtag_addr.OUTPUTSELECT +take_action_tracemem_b => take_action_tracemem_b.IN1 +take_no_action_tracemem_a => always1.IN1 +trc_ctrl[0] => comb.IN1 +trc_ctrl[0] => trc_enb.DATAIN +trc_ctrl[0] => tracemem_on.DATAIN +trc_ctrl[1] => ~NO_FANOUT~ +trc_ctrl[2] => ~NO_FANOUT~ +trc_ctrl[3] => ~NO_FANOUT~ +trc_ctrl[4] => ~NO_FANOUT~ +trc_ctrl[5] => ~NO_FANOUT~ +trc_ctrl[6] => ~NO_FANOUT~ +trc_ctrl[7] => ~NO_FANOUT~ +trc_ctrl[8] => ~NO_FANOUT~ +trc_ctrl[9] => ~NO_FANOUT~ +trc_ctrl[10] => xbrk_wrap_traceoff.IN1 +trc_ctrl[11] => ~NO_FANOUT~ +trc_ctrl[12] => ~NO_FANOUT~ +trc_ctrl[13] => ~NO_FANOUT~ +trc_ctrl[14] => ~NO_FANOUT~ +trc_ctrl[15] => ~NO_FANOUT~ +tw[0] => trc_im_data[0].IN1 +tw[1] => trc_im_data[1].IN1 +tw[2] => trc_im_data[2].IN1 +tw[3] => trc_im_data[3].IN1 +tw[4] => trc_im_data[4].IN1 +tw[5] => trc_im_data[5].IN1 +tw[6] => trc_im_data[6].IN1 +tw[7] => trc_im_data[7].IN1 +tw[8] => trc_im_data[8].IN1 +tw[9] => trc_im_data[9].IN1 +tw[10] => trc_im_data[10].IN1 +tw[11] => trc_im_data[11].IN1 +tw[12] => trc_im_data[12].IN1 +tw[13] => trc_im_data[13].IN1 +tw[14] => trc_im_data[14].IN1 +tw[15] => trc_im_data[15].IN1 +tw[16] => trc_im_data[16].IN1 +tw[17] => trc_im_data[17].IN1 +tw[18] => trc_im_data[18].IN1 +tw[19] => trc_im_data[19].IN1 +tw[20] => trc_im_data[20].IN1 +tw[21] => trc_im_data[21].IN1 +tw[22] => trc_im_data[22].IN1 +tw[23] => trc_im_data[23].IN1 +tw[24] => trc_im_data[24].IN1 +tw[25] => trc_im_data[25].IN1 +tw[26] => trc_im_data[26].IN1 +tw[27] => trc_im_data[27].IN1 +tw[28] => trc_im_data[28].IN1 +tw[29] => trc_im_data[29].IN1 +tw[30] => trc_im_data[30].IN1 +tw[31] => trc_im_data[31].IN1 +tw[32] => trc_im_data[32].IN1 +tw[33] => trc_im_data[33].IN1 +tw[34] => trc_im_data[34].IN1 +tw[35] => trc_im_data[35].IN1 +tracemem_on <= trc_ctrl[0].DB_MAX_OUTPUT_PORT_TYPE +tracemem_trcdata[0] <= +tracemem_trcdata[1] <= +tracemem_trcdata[2] <= +tracemem_trcdata[3] <= +tracemem_trcdata[4] <= +tracemem_trcdata[5] <= +tracemem_trcdata[6] <= +tracemem_trcdata[7] <= +tracemem_trcdata[8] <= +tracemem_trcdata[9] <= +tracemem_trcdata[10] <= +tracemem_trcdata[11] <= +tracemem_trcdata[12] <= +tracemem_trcdata[13] <= +tracemem_trcdata[14] <= +tracemem_trcdata[15] <= +tracemem_trcdata[16] <= +tracemem_trcdata[17] <= +tracemem_trcdata[18] <= +tracemem_trcdata[19] <= +tracemem_trcdata[20] <= +tracemem_trcdata[21] <= +tracemem_trcdata[22] <= +tracemem_trcdata[23] <= +tracemem_trcdata[24] <= +tracemem_trcdata[25] <= +tracemem_trcdata[26] <= +tracemem_trcdata[27] <= +tracemem_trcdata[28] <= +tracemem_trcdata[29] <= +tracemem_trcdata[30] <= +tracemem_trcdata[31] <= +tracemem_trcdata[32] <= +tracemem_trcdata[33] <= +tracemem_trcdata[34] <= +tracemem_trcdata[35] <= +tracemem_tw <= tracemem_tw.DB_MAX_OUTPUT_PORT_TYPE +trc_enb <= trc_ctrl[0].DB_MAX_OUTPUT_PORT_TYPE +trc_im_addr[0] <= trc_im_addr[0].DB_MAX_OUTPUT_PORT_TYPE +trc_im_addr[1] <= trc_im_addr[1].DB_MAX_OUTPUT_PORT_TYPE +trc_im_addr[2] <= trc_im_addr[2].DB_MAX_OUTPUT_PORT_TYPE +trc_im_addr[3] <= trc_im_addr[3].DB_MAX_OUTPUT_PORT_TYPE +trc_im_addr[4] <= trc_im_addr[4].DB_MAX_OUTPUT_PORT_TYPE +trc_im_addr[5] <= trc_im_addr[5].DB_MAX_OUTPUT_PORT_TYPE +trc_im_addr[6] <= trc_im_addr[6].DB_MAX_OUTPUT_PORT_TYPE +trc_wrap <= trc_wrap~reg0.DB_MAX_OUTPUT_PORT_TYPE +xbrk_wrap_traceoff <= xbrk_wrap_traceoff.DB_MAX_OUTPUT_PORT_TYPE + + +|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component +address_a[0] => address_a[0].IN1 +address_a[1] => address_a[1].IN1 +address_a[2] => address_a[2].IN1 +address_a[3] => address_a[3].IN1 +address_a[4] => address_a[4].IN1 +address_a[5] => address_a[5].IN1 +address_a[6] => address_a[6].IN1 +address_b[0] => address_b[0].IN1 +address_b[1] => address_b[1].IN1 +address_b[2] => address_b[2].IN1 +address_b[3] => address_b[3].IN1 +address_b[4] => address_b[4].IN1 +address_b[5] => address_b[5].IN1 +address_b[6] => address_b[6].IN1 +clock0 => clock0.IN1 +clock1 => clock1.IN1 +clocken0 => clocken0.IN1 +clocken1 => clocken1.IN1 +data_a[0] => data_a[0].IN1 +data_a[1] => data_a[1].IN1 +data_a[2] => data_a[2].IN1 +data_a[3] => data_a[3].IN1 +data_a[4] => data_a[4].IN1 +data_a[5] => data_a[5].IN1 +data_a[6] => data_a[6].IN1 +data_a[7] => data_a[7].IN1 +data_a[8] => data_a[8].IN1 +data_a[9] => data_a[9].IN1 +data_a[10] => data_a[10].IN1 +data_a[11] => data_a[11].IN1 +data_a[12] => data_a[12].IN1 +data_a[13] => data_a[13].IN1 +data_a[14] => data_a[14].IN1 +data_a[15] => data_a[15].IN1 +data_a[16] => data_a[16].IN1 +data_a[17] => data_a[17].IN1 +data_a[18] => data_a[18].IN1 +data_a[19] => data_a[19].IN1 +data_a[20] => data_a[20].IN1 +data_a[21] => data_a[21].IN1 +data_a[22] => data_a[22].IN1 +data_a[23] => data_a[23].IN1 +data_a[24] => data_a[24].IN1 +data_a[25] => data_a[25].IN1 +data_a[26] => data_a[26].IN1 +data_a[27] => data_a[27].IN1 +data_a[28] => data_a[28].IN1 +data_a[29] => data_a[29].IN1 +data_a[30] => data_a[30].IN1 +data_a[31] => data_a[31].IN1 +data_a[32] => data_a[32].IN1 +data_a[33] => data_a[33].IN1 +data_a[34] => data_a[34].IN1 +data_a[35] => data_a[35].IN1 +data_b[0] => data_b[0].IN1 +data_b[1] => data_b[1].IN1 +data_b[2] => data_b[2].IN1 +data_b[3] => data_b[3].IN1 +data_b[4] => data_b[4].IN1 +data_b[5] => data_b[5].IN1 +data_b[6] => data_b[6].IN1 +data_b[7] => data_b[7].IN1 +data_b[8] => data_b[8].IN1 +data_b[9] => data_b[9].IN1 +data_b[10] => data_b[10].IN1 +data_b[11] => data_b[11].IN1 +data_b[12] => data_b[12].IN1 +data_b[13] => data_b[13].IN1 +data_b[14] => data_b[14].IN1 +data_b[15] => data_b[15].IN1 +data_b[16] => data_b[16].IN1 +data_b[17] => data_b[17].IN1 +data_b[18] => data_b[18].IN1 +data_b[19] => data_b[19].IN1 +data_b[20] => data_b[20].IN1 +data_b[21] => data_b[21].IN1 +data_b[22] => data_b[22].IN1 +data_b[23] => data_b[23].IN1 +data_b[24] => data_b[24].IN1 +data_b[25] => data_b[25].IN1 +data_b[26] => data_b[26].IN1 +data_b[27] => data_b[27].IN1 +data_b[28] => data_b[28].IN1 +data_b[29] => data_b[29].IN1 +data_b[30] => data_b[30].IN1 +data_b[31] => data_b[31].IN1 +data_b[32] => data_b[32].IN1 +data_b[33] => data_b[33].IN1 +data_b[34] => data_b[34].IN1 +data_b[35] => data_b[35].IN1 +wren_a => wren_a.IN1 +wren_b => wren_b.IN1 +q_a[0] <= altsyncram:the_altsyncram.q_a +q_a[1] <= altsyncram:the_altsyncram.q_a +q_a[2] <= altsyncram:the_altsyncram.q_a +q_a[3] <= altsyncram:the_altsyncram.q_a +q_a[4] <= altsyncram:the_altsyncram.q_a +q_a[5] <= altsyncram:the_altsyncram.q_a +q_a[6] <= altsyncram:the_altsyncram.q_a +q_a[7] <= altsyncram:the_altsyncram.q_a +q_a[8] <= altsyncram:the_altsyncram.q_a +q_a[9] <= altsyncram:the_altsyncram.q_a +q_a[10] <= altsyncram:the_altsyncram.q_a +q_a[11] <= altsyncram:the_altsyncram.q_a +q_a[12] <= altsyncram:the_altsyncram.q_a +q_a[13] <= altsyncram:the_altsyncram.q_a +q_a[14] <= altsyncram:the_altsyncram.q_a +q_a[15] <= altsyncram:the_altsyncram.q_a +q_a[16] <= altsyncram:the_altsyncram.q_a +q_a[17] <= altsyncram:the_altsyncram.q_a +q_a[18] <= altsyncram:the_altsyncram.q_a +q_a[19] <= altsyncram:the_altsyncram.q_a +q_a[20] <= altsyncram:the_altsyncram.q_a +q_a[21] <= altsyncram:the_altsyncram.q_a +q_a[22] <= altsyncram:the_altsyncram.q_a +q_a[23] <= altsyncram:the_altsyncram.q_a +q_a[24] <= altsyncram:the_altsyncram.q_a +q_a[25] <= altsyncram:the_altsyncram.q_a +q_a[26] <= altsyncram:the_altsyncram.q_a +q_a[27] <= altsyncram:the_altsyncram.q_a +q_a[28] <= altsyncram:the_altsyncram.q_a +q_a[29] <= altsyncram:the_altsyncram.q_a +q_a[30] <= altsyncram:the_altsyncram.q_a +q_a[31] <= altsyncram:the_altsyncram.q_a +q_a[32] <= altsyncram:the_altsyncram.q_a +q_a[33] <= altsyncram:the_altsyncram.q_a +q_a[34] <= altsyncram:the_altsyncram.q_a +q_a[35] <= altsyncram:the_altsyncram.q_a +q_b[0] <= altsyncram:the_altsyncram.q_b +q_b[1] <= altsyncram:the_altsyncram.q_b +q_b[2] <= altsyncram:the_altsyncram.q_b +q_b[3] <= altsyncram:the_altsyncram.q_b +q_b[4] <= altsyncram:the_altsyncram.q_b +q_b[5] <= altsyncram:the_altsyncram.q_b +q_b[6] <= altsyncram:the_altsyncram.q_b +q_b[7] <= altsyncram:the_altsyncram.q_b +q_b[8] <= altsyncram:the_altsyncram.q_b +q_b[9] <= altsyncram:the_altsyncram.q_b +q_b[10] <= altsyncram:the_altsyncram.q_b +q_b[11] <= altsyncram:the_altsyncram.q_b +q_b[12] <= altsyncram:the_altsyncram.q_b +q_b[13] <= altsyncram:the_altsyncram.q_b +q_b[14] <= altsyncram:the_altsyncram.q_b +q_b[15] <= altsyncram:the_altsyncram.q_b +q_b[16] <= altsyncram:the_altsyncram.q_b +q_b[17] <= altsyncram:the_altsyncram.q_b +q_b[18] <= altsyncram:the_altsyncram.q_b +q_b[19] <= altsyncram:the_altsyncram.q_b +q_b[20] <= altsyncram:the_altsyncram.q_b +q_b[21] <= altsyncram:the_altsyncram.q_b +q_b[22] <= altsyncram:the_altsyncram.q_b +q_b[23] <= altsyncram:the_altsyncram.q_b +q_b[24] <= altsyncram:the_altsyncram.q_b +q_b[25] <= altsyncram:the_altsyncram.q_b +q_b[26] <= altsyncram:the_altsyncram.q_b +q_b[27] <= altsyncram:the_altsyncram.q_b +q_b[28] <= altsyncram:the_altsyncram.q_b +q_b[29] <= altsyncram:the_altsyncram.q_b +q_b[30] <= altsyncram:the_altsyncram.q_b +q_b[31] <= altsyncram:the_altsyncram.q_b +q_b[32] <= altsyncram:the_altsyncram.q_b +q_b[33] <= altsyncram:the_altsyncram.q_b +q_b[34] <= altsyncram:the_altsyncram.q_b +q_b[35] <= altsyncram:the_altsyncram.q_b + + +|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram +wren_a => altsyncram_0a02:auto_generated.wren_a +rden_a => ~NO_FANOUT~ +wren_b => altsyncram_0a02:auto_generated.wren_b +rden_b => ~NO_FANOUT~ +data_a[0] => altsyncram_0a02:auto_generated.data_a[0] +data_a[1] => altsyncram_0a02:auto_generated.data_a[1] +data_a[2] => altsyncram_0a02:auto_generated.data_a[2] +data_a[3] => altsyncram_0a02:auto_generated.data_a[3] +data_a[4] => altsyncram_0a02:auto_generated.data_a[4] +data_a[5] => altsyncram_0a02:auto_generated.data_a[5] +data_a[6] => altsyncram_0a02:auto_generated.data_a[6] +data_a[7] => altsyncram_0a02:auto_generated.data_a[7] +data_a[8] => altsyncram_0a02:auto_generated.data_a[8] +data_a[9] => altsyncram_0a02:auto_generated.data_a[9] +data_a[10] => altsyncram_0a02:auto_generated.data_a[10] +data_a[11] => altsyncram_0a02:auto_generated.data_a[11] +data_a[12] => altsyncram_0a02:auto_generated.data_a[12] +data_a[13] => altsyncram_0a02:auto_generated.data_a[13] +data_a[14] => altsyncram_0a02:auto_generated.data_a[14] +data_a[15] => altsyncram_0a02:auto_generated.data_a[15] +data_a[16] => altsyncram_0a02:auto_generated.data_a[16] +data_a[17] => altsyncram_0a02:auto_generated.data_a[17] +data_a[18] => altsyncram_0a02:auto_generated.data_a[18] +data_a[19] => altsyncram_0a02:auto_generated.data_a[19] +data_a[20] => altsyncram_0a02:auto_generated.data_a[20] +data_a[21] => altsyncram_0a02:auto_generated.data_a[21] +data_a[22] => altsyncram_0a02:auto_generated.data_a[22] +data_a[23] => altsyncram_0a02:auto_generated.data_a[23] +data_a[24] => altsyncram_0a02:auto_generated.data_a[24] +data_a[25] => altsyncram_0a02:auto_generated.data_a[25] +data_a[26] => altsyncram_0a02:auto_generated.data_a[26] +data_a[27] => altsyncram_0a02:auto_generated.data_a[27] +data_a[28] => altsyncram_0a02:auto_generated.data_a[28] +data_a[29] => altsyncram_0a02:auto_generated.data_a[29] +data_a[30] => altsyncram_0a02:auto_generated.data_a[30] +data_a[31] => altsyncram_0a02:auto_generated.data_a[31] +data_a[32] => altsyncram_0a02:auto_generated.data_a[32] +data_a[33] => altsyncram_0a02:auto_generated.data_a[33] +data_a[34] => altsyncram_0a02:auto_generated.data_a[34] +data_a[35] => altsyncram_0a02:auto_generated.data_a[35] +data_b[0] => altsyncram_0a02:auto_generated.data_b[0] +data_b[1] => altsyncram_0a02:auto_generated.data_b[1] +data_b[2] => altsyncram_0a02:auto_generated.data_b[2] +data_b[3] => altsyncram_0a02:auto_generated.data_b[3] +data_b[4] => altsyncram_0a02:auto_generated.data_b[4] +data_b[5] => altsyncram_0a02:auto_generated.data_b[5] +data_b[6] => altsyncram_0a02:auto_generated.data_b[6] +data_b[7] => altsyncram_0a02:auto_generated.data_b[7] +data_b[8] => altsyncram_0a02:auto_generated.data_b[8] +data_b[9] => altsyncram_0a02:auto_generated.data_b[9] +data_b[10] => altsyncram_0a02:auto_generated.data_b[10] +data_b[11] => altsyncram_0a02:auto_generated.data_b[11] +data_b[12] => altsyncram_0a02:auto_generated.data_b[12] +data_b[13] => altsyncram_0a02:auto_generated.data_b[13] +data_b[14] => altsyncram_0a02:auto_generated.data_b[14] +data_b[15] => altsyncram_0a02:auto_generated.data_b[15] +data_b[16] => altsyncram_0a02:auto_generated.data_b[16] +data_b[17] => altsyncram_0a02:auto_generated.data_b[17] +data_b[18] => altsyncram_0a02:auto_generated.data_b[18] +data_b[19] => altsyncram_0a02:auto_generated.data_b[19] +data_b[20] => altsyncram_0a02:auto_generated.data_b[20] +data_b[21] => altsyncram_0a02:auto_generated.data_b[21] +data_b[22] => altsyncram_0a02:auto_generated.data_b[22] +data_b[23] => altsyncram_0a02:auto_generated.data_b[23] +data_b[24] => altsyncram_0a02:auto_generated.data_b[24] +data_b[25] => altsyncram_0a02:auto_generated.data_b[25] +data_b[26] => altsyncram_0a02:auto_generated.data_b[26] +data_b[27] => altsyncram_0a02:auto_generated.data_b[27] +data_b[28] => altsyncram_0a02:auto_generated.data_b[28] +data_b[29] => altsyncram_0a02:auto_generated.data_b[29] +data_b[30] => altsyncram_0a02:auto_generated.data_b[30] +data_b[31] => altsyncram_0a02:auto_generated.data_b[31] +data_b[32] => altsyncram_0a02:auto_generated.data_b[32] +data_b[33] => altsyncram_0a02:auto_generated.data_b[33] +data_b[34] => altsyncram_0a02:auto_generated.data_b[34] +data_b[35] => altsyncram_0a02:auto_generated.data_b[35] +address_a[0] => altsyncram_0a02:auto_generated.address_a[0] +address_a[1] => altsyncram_0a02:auto_generated.address_a[1] +address_a[2] => altsyncram_0a02:auto_generated.address_a[2] +address_a[3] => altsyncram_0a02:auto_generated.address_a[3] +address_a[4] => altsyncram_0a02:auto_generated.address_a[4] +address_a[5] => altsyncram_0a02:auto_generated.address_a[5] +address_a[6] => altsyncram_0a02:auto_generated.address_a[6] +address_b[0] => altsyncram_0a02:auto_generated.address_b[0] +address_b[1] => altsyncram_0a02:auto_generated.address_b[1] +address_b[2] => altsyncram_0a02:auto_generated.address_b[2] +address_b[3] => altsyncram_0a02:auto_generated.address_b[3] +address_b[4] => altsyncram_0a02:auto_generated.address_b[4] +address_b[5] => altsyncram_0a02:auto_generated.address_b[5] +address_b[6] => altsyncram_0a02:auto_generated.address_b[6] +addressstall_a => ~NO_FANOUT~ +addressstall_b => ~NO_FANOUT~ +clock0 => altsyncram_0a02:auto_generated.clock0 +clock1 => altsyncram_0a02:auto_generated.clock1 +clocken0 => altsyncram_0a02:auto_generated.clocken0 +clocken1 => altsyncram_0a02:auto_generated.clocken1 +clocken2 => ~NO_FANOUT~ +clocken3 => ~NO_FANOUT~ +aclr0 => ~NO_FANOUT~ +aclr1 => ~NO_FANOUT~ +byteena_a[0] => ~NO_FANOUT~ +byteena_b[0] => ~NO_FANOUT~ +q_a[0] <= altsyncram_0a02:auto_generated.q_a[0] +q_a[1] <= altsyncram_0a02:auto_generated.q_a[1] +q_a[2] <= altsyncram_0a02:auto_generated.q_a[2] +q_a[3] <= altsyncram_0a02:auto_generated.q_a[3] +q_a[4] <= altsyncram_0a02:auto_generated.q_a[4] +q_a[5] <= altsyncram_0a02:auto_generated.q_a[5] +q_a[6] <= altsyncram_0a02:auto_generated.q_a[6] +q_a[7] <= altsyncram_0a02:auto_generated.q_a[7] +q_a[8] <= altsyncram_0a02:auto_generated.q_a[8] +q_a[9] <= altsyncram_0a02:auto_generated.q_a[9] +q_a[10] <= altsyncram_0a02:auto_generated.q_a[10] +q_a[11] <= altsyncram_0a02:auto_generated.q_a[11] +q_a[12] <= altsyncram_0a02:auto_generated.q_a[12] +q_a[13] <= altsyncram_0a02:auto_generated.q_a[13] +q_a[14] <= altsyncram_0a02:auto_generated.q_a[14] +q_a[15] <= altsyncram_0a02:auto_generated.q_a[15] +q_a[16] <= altsyncram_0a02:auto_generated.q_a[16] +q_a[17] <= altsyncram_0a02:auto_generated.q_a[17] +q_a[18] <= altsyncram_0a02:auto_generated.q_a[18] +q_a[19] <= altsyncram_0a02:auto_generated.q_a[19] +q_a[20] <= altsyncram_0a02:auto_generated.q_a[20] +q_a[21] <= altsyncram_0a02:auto_generated.q_a[21] +q_a[22] <= altsyncram_0a02:auto_generated.q_a[22] +q_a[23] <= altsyncram_0a02:auto_generated.q_a[23] +q_a[24] <= altsyncram_0a02:auto_generated.q_a[24] +q_a[25] <= altsyncram_0a02:auto_generated.q_a[25] +q_a[26] <= altsyncram_0a02:auto_generated.q_a[26] +q_a[27] <= altsyncram_0a02:auto_generated.q_a[27] +q_a[28] <= altsyncram_0a02:auto_generated.q_a[28] +q_a[29] <= altsyncram_0a02:auto_generated.q_a[29] +q_a[30] <= altsyncram_0a02:auto_generated.q_a[30] +q_a[31] <= altsyncram_0a02:auto_generated.q_a[31] +q_a[32] <= altsyncram_0a02:auto_generated.q_a[32] +q_a[33] <= altsyncram_0a02:auto_generated.q_a[33] +q_a[34] <= altsyncram_0a02:auto_generated.q_a[34] +q_a[35] <= altsyncram_0a02:auto_generated.q_a[35] +q_b[0] <= altsyncram_0a02:auto_generated.q_b[0] +q_b[1] <= altsyncram_0a02:auto_generated.q_b[1] +q_b[2] <= altsyncram_0a02:auto_generated.q_b[2] +q_b[3] <= altsyncram_0a02:auto_generated.q_b[3] +q_b[4] <= altsyncram_0a02:auto_generated.q_b[4] +q_b[5] <= altsyncram_0a02:auto_generated.q_b[5] +q_b[6] <= altsyncram_0a02:auto_generated.q_b[6] +q_b[7] <= altsyncram_0a02:auto_generated.q_b[7] +q_b[8] <= altsyncram_0a02:auto_generated.q_b[8] +q_b[9] <= altsyncram_0a02:auto_generated.q_b[9] +q_b[10] <= altsyncram_0a02:auto_generated.q_b[10] +q_b[11] <= altsyncram_0a02:auto_generated.q_b[11] +q_b[12] <= altsyncram_0a02:auto_generated.q_b[12] +q_b[13] <= altsyncram_0a02:auto_generated.q_b[13] +q_b[14] <= altsyncram_0a02:auto_generated.q_b[14] +q_b[15] <= altsyncram_0a02:auto_generated.q_b[15] +q_b[16] <= altsyncram_0a02:auto_generated.q_b[16] +q_b[17] <= altsyncram_0a02:auto_generated.q_b[17] +q_b[18] <= altsyncram_0a02:auto_generated.q_b[18] +q_b[19] <= altsyncram_0a02:auto_generated.q_b[19] +q_b[20] <= altsyncram_0a02:auto_generated.q_b[20] +q_b[21] <= altsyncram_0a02:auto_generated.q_b[21] +q_b[22] <= altsyncram_0a02:auto_generated.q_b[22] +q_b[23] <= altsyncram_0a02:auto_generated.q_b[23] +q_b[24] <= altsyncram_0a02:auto_generated.q_b[24] +q_b[25] <= altsyncram_0a02:auto_generated.q_b[25] +q_b[26] <= altsyncram_0a02:auto_generated.q_b[26] +q_b[27] <= altsyncram_0a02:auto_generated.q_b[27] +q_b[28] <= altsyncram_0a02:auto_generated.q_b[28] +q_b[29] <= altsyncram_0a02:auto_generated.q_b[29] +q_b[30] <= altsyncram_0a02:auto_generated.q_b[30] +q_b[31] <= altsyncram_0a02:auto_generated.q_b[31] +q_b[32] <= altsyncram_0a02:auto_generated.q_b[32] +q_b[33] <= altsyncram_0a02:auto_generated.q_b[33] +q_b[34] <= altsyncram_0a02:auto_generated.q_b[34] +q_b[35] <= altsyncram_0a02:auto_generated.q_b[35] +eccstatus[0] <= +eccstatus[1] <= +eccstatus[2] <= + + +|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated +address_a[0] => ram_block1a0.PORTAADDR +address_a[0] => ram_block1a1.PORTAADDR +address_a[0] => ram_block1a2.PORTAADDR +address_a[0] => ram_block1a3.PORTAADDR +address_a[0] => ram_block1a4.PORTAADDR +address_a[0] => ram_block1a5.PORTAADDR +address_a[0] => ram_block1a6.PORTAADDR +address_a[0] => ram_block1a7.PORTAADDR +address_a[0] => ram_block1a8.PORTAADDR +address_a[0] => ram_block1a9.PORTAADDR +address_a[0] => ram_block1a10.PORTAADDR +address_a[0] => ram_block1a11.PORTAADDR +address_a[0] => ram_block1a12.PORTAADDR +address_a[0] => ram_block1a13.PORTAADDR +address_a[0] => ram_block1a14.PORTAADDR +address_a[0] => ram_block1a15.PORTAADDR +address_a[0] => ram_block1a16.PORTAADDR +address_a[0] => ram_block1a17.PORTAADDR +address_a[0] => ram_block1a18.PORTAADDR +address_a[0] => ram_block1a19.PORTAADDR +address_a[0] => ram_block1a20.PORTAADDR +address_a[0] => ram_block1a21.PORTAADDR +address_a[0] => ram_block1a22.PORTAADDR +address_a[0] => ram_block1a23.PORTAADDR +address_a[0] => ram_block1a24.PORTAADDR +address_a[0] => ram_block1a25.PORTAADDR +address_a[0] => ram_block1a26.PORTAADDR +address_a[0] => ram_block1a27.PORTAADDR +address_a[0] => ram_block1a28.PORTAADDR +address_a[0] => ram_block1a29.PORTAADDR +address_a[0] => ram_block1a30.PORTAADDR +address_a[0] => ram_block1a31.PORTAADDR +address_a[0] => ram_block1a32.PORTAADDR +address_a[0] => ram_block1a33.PORTAADDR +address_a[0] => ram_block1a34.PORTAADDR +address_a[0] => ram_block1a35.PORTAADDR +address_a[1] => ram_block1a0.PORTAADDR1 +address_a[1] => ram_block1a1.PORTAADDR1 +address_a[1] => ram_block1a2.PORTAADDR1 +address_a[1] => ram_block1a3.PORTAADDR1 +address_a[1] => ram_block1a4.PORTAADDR1 +address_a[1] => ram_block1a5.PORTAADDR1 +address_a[1] => ram_block1a6.PORTAADDR1 +address_a[1] => ram_block1a7.PORTAADDR1 +address_a[1] => ram_block1a8.PORTAADDR1 +address_a[1] => ram_block1a9.PORTAADDR1 +address_a[1] => ram_block1a10.PORTAADDR1 +address_a[1] => ram_block1a11.PORTAADDR1 +address_a[1] => ram_block1a12.PORTAADDR1 +address_a[1] => ram_block1a13.PORTAADDR1 +address_a[1] => ram_block1a14.PORTAADDR1 +address_a[1] => ram_block1a15.PORTAADDR1 +address_a[1] => ram_block1a16.PORTAADDR1 +address_a[1] => ram_block1a17.PORTAADDR1 +address_a[1] => ram_block1a18.PORTAADDR1 +address_a[1] => ram_block1a19.PORTAADDR1 +address_a[1] => ram_block1a20.PORTAADDR1 +address_a[1] => ram_block1a21.PORTAADDR1 +address_a[1] => ram_block1a22.PORTAADDR1 +address_a[1] => ram_block1a23.PORTAADDR1 +address_a[1] => ram_block1a24.PORTAADDR1 +address_a[1] => ram_block1a25.PORTAADDR1 +address_a[1] => ram_block1a26.PORTAADDR1 +address_a[1] => ram_block1a27.PORTAADDR1 +address_a[1] => ram_block1a28.PORTAADDR1 +address_a[1] => ram_block1a29.PORTAADDR1 +address_a[1] => ram_block1a30.PORTAADDR1 +address_a[1] => ram_block1a31.PORTAADDR1 +address_a[1] => ram_block1a32.PORTAADDR1 +address_a[1] => ram_block1a33.PORTAADDR1 +address_a[1] => ram_block1a34.PORTAADDR1 +address_a[1] => ram_block1a35.PORTAADDR1 +address_a[2] => ram_block1a0.PORTAADDR2 +address_a[2] => ram_block1a1.PORTAADDR2 +address_a[2] => ram_block1a2.PORTAADDR2 +address_a[2] => ram_block1a3.PORTAADDR2 +address_a[2] => ram_block1a4.PORTAADDR2 +address_a[2] => ram_block1a5.PORTAADDR2 +address_a[2] => ram_block1a6.PORTAADDR2 +address_a[2] => ram_block1a7.PORTAADDR2 +address_a[2] => ram_block1a8.PORTAADDR2 +address_a[2] => ram_block1a9.PORTAADDR2 +address_a[2] => ram_block1a10.PORTAADDR2 +address_a[2] => ram_block1a11.PORTAADDR2 +address_a[2] => ram_block1a12.PORTAADDR2 +address_a[2] => ram_block1a13.PORTAADDR2 +address_a[2] => ram_block1a14.PORTAADDR2 +address_a[2] => ram_block1a15.PORTAADDR2 +address_a[2] => ram_block1a16.PORTAADDR2 +address_a[2] => ram_block1a17.PORTAADDR2 +address_a[2] => ram_block1a18.PORTAADDR2 +address_a[2] => ram_block1a19.PORTAADDR2 +address_a[2] => ram_block1a20.PORTAADDR2 +address_a[2] => ram_block1a21.PORTAADDR2 +address_a[2] => ram_block1a22.PORTAADDR2 +address_a[2] => ram_block1a23.PORTAADDR2 +address_a[2] => ram_block1a24.PORTAADDR2 +address_a[2] => ram_block1a25.PORTAADDR2 +address_a[2] => ram_block1a26.PORTAADDR2 +address_a[2] => ram_block1a27.PORTAADDR2 +address_a[2] => ram_block1a28.PORTAADDR2 +address_a[2] => ram_block1a29.PORTAADDR2 +address_a[2] => ram_block1a30.PORTAADDR2 +address_a[2] => ram_block1a31.PORTAADDR2 +address_a[2] => ram_block1a32.PORTAADDR2 +address_a[2] => ram_block1a33.PORTAADDR2 +address_a[2] => ram_block1a34.PORTAADDR2 +address_a[2] => ram_block1a35.PORTAADDR2 +address_a[3] => ram_block1a0.PORTAADDR3 +address_a[3] => ram_block1a1.PORTAADDR3 +address_a[3] => ram_block1a2.PORTAADDR3 +address_a[3] => ram_block1a3.PORTAADDR3 +address_a[3] => ram_block1a4.PORTAADDR3 +address_a[3] => ram_block1a5.PORTAADDR3 +address_a[3] => ram_block1a6.PORTAADDR3 +address_a[3] => ram_block1a7.PORTAADDR3 +address_a[3] => ram_block1a8.PORTAADDR3 +address_a[3] => ram_block1a9.PORTAADDR3 +address_a[3] => ram_block1a10.PORTAADDR3 +address_a[3] => ram_block1a11.PORTAADDR3 +address_a[3] => ram_block1a12.PORTAADDR3 +address_a[3] => ram_block1a13.PORTAADDR3 +address_a[3] => ram_block1a14.PORTAADDR3 +address_a[3] => ram_block1a15.PORTAADDR3 +address_a[3] => ram_block1a16.PORTAADDR3 +address_a[3] => ram_block1a17.PORTAADDR3 +address_a[3] => ram_block1a18.PORTAADDR3 +address_a[3] => ram_block1a19.PORTAADDR3 +address_a[3] => ram_block1a20.PORTAADDR3 +address_a[3] => ram_block1a21.PORTAADDR3 +address_a[3] => ram_block1a22.PORTAADDR3 +address_a[3] => ram_block1a23.PORTAADDR3 +address_a[3] => ram_block1a24.PORTAADDR3 +address_a[3] => ram_block1a25.PORTAADDR3 +address_a[3] => ram_block1a26.PORTAADDR3 +address_a[3] => ram_block1a27.PORTAADDR3 +address_a[3] => ram_block1a28.PORTAADDR3 +address_a[3] => ram_block1a29.PORTAADDR3 +address_a[3] => ram_block1a30.PORTAADDR3 +address_a[3] => ram_block1a31.PORTAADDR3 +address_a[3] => ram_block1a32.PORTAADDR3 +address_a[3] => ram_block1a33.PORTAADDR3 +address_a[3] => ram_block1a34.PORTAADDR3 +address_a[3] => ram_block1a35.PORTAADDR3 +address_a[4] => ram_block1a0.PORTAADDR4 +address_a[4] => ram_block1a1.PORTAADDR4 +address_a[4] => ram_block1a2.PORTAADDR4 +address_a[4] => ram_block1a3.PORTAADDR4 +address_a[4] => ram_block1a4.PORTAADDR4 +address_a[4] => ram_block1a5.PORTAADDR4 +address_a[4] => ram_block1a6.PORTAADDR4 +address_a[4] => ram_block1a7.PORTAADDR4 +address_a[4] => ram_block1a8.PORTAADDR4 +address_a[4] => ram_block1a9.PORTAADDR4 +address_a[4] => ram_block1a10.PORTAADDR4 +address_a[4] => ram_block1a11.PORTAADDR4 +address_a[4] => ram_block1a12.PORTAADDR4 +address_a[4] => ram_block1a13.PORTAADDR4 +address_a[4] => ram_block1a14.PORTAADDR4 +address_a[4] => ram_block1a15.PORTAADDR4 +address_a[4] => ram_block1a16.PORTAADDR4 +address_a[4] => ram_block1a17.PORTAADDR4 +address_a[4] => ram_block1a18.PORTAADDR4 +address_a[4] => ram_block1a19.PORTAADDR4 +address_a[4] => ram_block1a20.PORTAADDR4 +address_a[4] => ram_block1a21.PORTAADDR4 +address_a[4] => ram_block1a22.PORTAADDR4 +address_a[4] => ram_block1a23.PORTAADDR4 +address_a[4] => ram_block1a24.PORTAADDR4 +address_a[4] => ram_block1a25.PORTAADDR4 +address_a[4] => ram_block1a26.PORTAADDR4 +address_a[4] => ram_block1a27.PORTAADDR4 +address_a[4] => ram_block1a28.PORTAADDR4 +address_a[4] => ram_block1a29.PORTAADDR4 +address_a[4] => ram_block1a30.PORTAADDR4 +address_a[4] => ram_block1a31.PORTAADDR4 +address_a[4] => ram_block1a32.PORTAADDR4 +address_a[4] => ram_block1a33.PORTAADDR4 +address_a[4] => ram_block1a34.PORTAADDR4 +address_a[4] => ram_block1a35.PORTAADDR4 +address_a[5] => ram_block1a0.PORTAADDR5 +address_a[5] => ram_block1a1.PORTAADDR5 +address_a[5] => ram_block1a2.PORTAADDR5 +address_a[5] => ram_block1a3.PORTAADDR5 +address_a[5] => ram_block1a4.PORTAADDR5 +address_a[5] => ram_block1a5.PORTAADDR5 +address_a[5] => ram_block1a6.PORTAADDR5 +address_a[5] => ram_block1a7.PORTAADDR5 +address_a[5] => ram_block1a8.PORTAADDR5 +address_a[5] => ram_block1a9.PORTAADDR5 +address_a[5] => ram_block1a10.PORTAADDR5 +address_a[5] => ram_block1a11.PORTAADDR5 +address_a[5] => ram_block1a12.PORTAADDR5 +address_a[5] => ram_block1a13.PORTAADDR5 +address_a[5] => ram_block1a14.PORTAADDR5 +address_a[5] => ram_block1a15.PORTAADDR5 +address_a[5] => ram_block1a16.PORTAADDR5 +address_a[5] => ram_block1a17.PORTAADDR5 +address_a[5] => ram_block1a18.PORTAADDR5 +address_a[5] => ram_block1a19.PORTAADDR5 +address_a[5] => ram_block1a20.PORTAADDR5 +address_a[5] => ram_block1a21.PORTAADDR5 +address_a[5] => ram_block1a22.PORTAADDR5 +address_a[5] => ram_block1a23.PORTAADDR5 +address_a[5] => ram_block1a24.PORTAADDR5 +address_a[5] => ram_block1a25.PORTAADDR5 +address_a[5] => ram_block1a26.PORTAADDR5 +address_a[5] => ram_block1a27.PORTAADDR5 +address_a[5] => ram_block1a28.PORTAADDR5 +address_a[5] => ram_block1a29.PORTAADDR5 +address_a[5] => ram_block1a30.PORTAADDR5 +address_a[5] => ram_block1a31.PORTAADDR5 +address_a[5] => ram_block1a32.PORTAADDR5 +address_a[5] => ram_block1a33.PORTAADDR5 +address_a[5] => ram_block1a34.PORTAADDR5 +address_a[5] => ram_block1a35.PORTAADDR5 +address_a[6] => ram_block1a0.PORTAADDR6 +address_a[6] => ram_block1a1.PORTAADDR6 +address_a[6] => ram_block1a2.PORTAADDR6 +address_a[6] => ram_block1a3.PORTAADDR6 +address_a[6] => ram_block1a4.PORTAADDR6 +address_a[6] => ram_block1a5.PORTAADDR6 +address_a[6] => ram_block1a6.PORTAADDR6 +address_a[6] => ram_block1a7.PORTAADDR6 +address_a[6] => ram_block1a8.PORTAADDR6 +address_a[6] => ram_block1a9.PORTAADDR6 +address_a[6] => ram_block1a10.PORTAADDR6 +address_a[6] => ram_block1a11.PORTAADDR6 +address_a[6] => ram_block1a12.PORTAADDR6 +address_a[6] => ram_block1a13.PORTAADDR6 +address_a[6] => ram_block1a14.PORTAADDR6 +address_a[6] => ram_block1a15.PORTAADDR6 +address_a[6] => ram_block1a16.PORTAADDR6 +address_a[6] => ram_block1a17.PORTAADDR6 +address_a[6] => ram_block1a18.PORTAADDR6 +address_a[6] => ram_block1a19.PORTAADDR6 +address_a[6] => ram_block1a20.PORTAADDR6 +address_a[6] => ram_block1a21.PORTAADDR6 +address_a[6] => ram_block1a22.PORTAADDR6 +address_a[6] => ram_block1a23.PORTAADDR6 +address_a[6] => ram_block1a24.PORTAADDR6 +address_a[6] => ram_block1a25.PORTAADDR6 +address_a[6] => ram_block1a26.PORTAADDR6 +address_a[6] => ram_block1a27.PORTAADDR6 +address_a[6] => ram_block1a28.PORTAADDR6 +address_a[6] => ram_block1a29.PORTAADDR6 +address_a[6] => ram_block1a30.PORTAADDR6 +address_a[6] => ram_block1a31.PORTAADDR6 +address_a[6] => ram_block1a32.PORTAADDR6 +address_a[6] => ram_block1a33.PORTAADDR6 +address_a[6] => ram_block1a34.PORTAADDR6 +address_a[6] => ram_block1a35.PORTAADDR6 +address_b[0] => ram_block1a0.PORTBADDR +address_b[0] => ram_block1a1.PORTBADDR +address_b[0] => ram_block1a2.PORTBADDR +address_b[0] => ram_block1a3.PORTBADDR +address_b[0] => ram_block1a4.PORTBADDR +address_b[0] => ram_block1a5.PORTBADDR +address_b[0] => ram_block1a6.PORTBADDR +address_b[0] => ram_block1a7.PORTBADDR +address_b[0] => ram_block1a8.PORTBADDR +address_b[0] => ram_block1a9.PORTBADDR +address_b[0] => ram_block1a10.PORTBADDR +address_b[0] => ram_block1a11.PORTBADDR +address_b[0] => ram_block1a12.PORTBADDR +address_b[0] => ram_block1a13.PORTBADDR +address_b[0] => ram_block1a14.PORTBADDR +address_b[0] => ram_block1a15.PORTBADDR +address_b[0] => ram_block1a16.PORTBADDR +address_b[0] => ram_block1a17.PORTBADDR +address_b[0] => ram_block1a18.PORTBADDR +address_b[0] => ram_block1a19.PORTBADDR +address_b[0] => ram_block1a20.PORTBADDR +address_b[0] => ram_block1a21.PORTBADDR +address_b[0] => ram_block1a22.PORTBADDR +address_b[0] => ram_block1a23.PORTBADDR +address_b[0] => ram_block1a24.PORTBADDR +address_b[0] => ram_block1a25.PORTBADDR +address_b[0] => ram_block1a26.PORTBADDR +address_b[0] => ram_block1a27.PORTBADDR +address_b[0] => ram_block1a28.PORTBADDR +address_b[0] => ram_block1a29.PORTBADDR +address_b[0] => ram_block1a30.PORTBADDR +address_b[0] => ram_block1a31.PORTBADDR +address_b[0] => ram_block1a32.PORTBADDR +address_b[0] => ram_block1a33.PORTBADDR +address_b[0] => ram_block1a34.PORTBADDR +address_b[0] => ram_block1a35.PORTBADDR +address_b[1] => ram_block1a0.PORTBADDR1 +address_b[1] => ram_block1a1.PORTBADDR1 +address_b[1] => ram_block1a2.PORTBADDR1 +address_b[1] => ram_block1a3.PORTBADDR1 +address_b[1] => ram_block1a4.PORTBADDR1 +address_b[1] => ram_block1a5.PORTBADDR1 +address_b[1] => ram_block1a6.PORTBADDR1 +address_b[1] => ram_block1a7.PORTBADDR1 +address_b[1] => ram_block1a8.PORTBADDR1 +address_b[1] => ram_block1a9.PORTBADDR1 +address_b[1] => ram_block1a10.PORTBADDR1 +address_b[1] => ram_block1a11.PORTBADDR1 +address_b[1] => ram_block1a12.PORTBADDR1 +address_b[1] => ram_block1a13.PORTBADDR1 +address_b[1] => ram_block1a14.PORTBADDR1 +address_b[1] => ram_block1a15.PORTBADDR1 +address_b[1] => ram_block1a16.PORTBADDR1 +address_b[1] => ram_block1a17.PORTBADDR1 +address_b[1] => ram_block1a18.PORTBADDR1 +address_b[1] => ram_block1a19.PORTBADDR1 +address_b[1] => ram_block1a20.PORTBADDR1 +address_b[1] => ram_block1a21.PORTBADDR1 +address_b[1] => ram_block1a22.PORTBADDR1 +address_b[1] => ram_block1a23.PORTBADDR1 +address_b[1] => ram_block1a24.PORTBADDR1 +address_b[1] => ram_block1a25.PORTBADDR1 +address_b[1] => ram_block1a26.PORTBADDR1 +address_b[1] => ram_block1a27.PORTBADDR1 +address_b[1] => ram_block1a28.PORTBADDR1 +address_b[1] => ram_block1a29.PORTBADDR1 +address_b[1] => ram_block1a30.PORTBADDR1 +address_b[1] => ram_block1a31.PORTBADDR1 +address_b[1] => ram_block1a32.PORTBADDR1 +address_b[1] => ram_block1a33.PORTBADDR1 +address_b[1] => ram_block1a34.PORTBADDR1 +address_b[1] => ram_block1a35.PORTBADDR1 +address_b[2] => ram_block1a0.PORTBADDR2 +address_b[2] => ram_block1a1.PORTBADDR2 +address_b[2] => ram_block1a2.PORTBADDR2 +address_b[2] => ram_block1a3.PORTBADDR2 +address_b[2] => ram_block1a4.PORTBADDR2 +address_b[2] => ram_block1a5.PORTBADDR2 +address_b[2] => ram_block1a6.PORTBADDR2 +address_b[2] => ram_block1a7.PORTBADDR2 +address_b[2] => ram_block1a8.PORTBADDR2 +address_b[2] => ram_block1a9.PORTBADDR2 +address_b[2] => ram_block1a10.PORTBADDR2 +address_b[2] => ram_block1a11.PORTBADDR2 +address_b[2] => ram_block1a12.PORTBADDR2 +address_b[2] => ram_block1a13.PORTBADDR2 +address_b[2] => ram_block1a14.PORTBADDR2 +address_b[2] => ram_block1a15.PORTBADDR2 +address_b[2] => ram_block1a16.PORTBADDR2 +address_b[2] => ram_block1a17.PORTBADDR2 +address_b[2] => ram_block1a18.PORTBADDR2 +address_b[2] => ram_block1a19.PORTBADDR2 +address_b[2] => ram_block1a20.PORTBADDR2 +address_b[2] => ram_block1a21.PORTBADDR2 +address_b[2] => ram_block1a22.PORTBADDR2 +address_b[2] => ram_block1a23.PORTBADDR2 +address_b[2] => ram_block1a24.PORTBADDR2 +address_b[2] => ram_block1a25.PORTBADDR2 +address_b[2] => ram_block1a26.PORTBADDR2 +address_b[2] => ram_block1a27.PORTBADDR2 +address_b[2] => ram_block1a28.PORTBADDR2 +address_b[2] => ram_block1a29.PORTBADDR2 +address_b[2] => ram_block1a30.PORTBADDR2 +address_b[2] => ram_block1a31.PORTBADDR2 +address_b[2] => ram_block1a32.PORTBADDR2 +address_b[2] => ram_block1a33.PORTBADDR2 +address_b[2] => ram_block1a34.PORTBADDR2 +address_b[2] => ram_block1a35.PORTBADDR2 +address_b[3] => ram_block1a0.PORTBADDR3 +address_b[3] => ram_block1a1.PORTBADDR3 +address_b[3] => ram_block1a2.PORTBADDR3 +address_b[3] => ram_block1a3.PORTBADDR3 +address_b[3] => ram_block1a4.PORTBADDR3 +address_b[3] => ram_block1a5.PORTBADDR3 +address_b[3] => ram_block1a6.PORTBADDR3 +address_b[3] => ram_block1a7.PORTBADDR3 +address_b[3] => ram_block1a8.PORTBADDR3 +address_b[3] => ram_block1a9.PORTBADDR3 +address_b[3] => ram_block1a10.PORTBADDR3 +address_b[3] => ram_block1a11.PORTBADDR3 +address_b[3] => ram_block1a12.PORTBADDR3 +address_b[3] => ram_block1a13.PORTBADDR3 +address_b[3] => ram_block1a14.PORTBADDR3 +address_b[3] => ram_block1a15.PORTBADDR3 +address_b[3] => ram_block1a16.PORTBADDR3 +address_b[3] => ram_block1a17.PORTBADDR3 +address_b[3] => ram_block1a18.PORTBADDR3 +address_b[3] => ram_block1a19.PORTBADDR3 +address_b[3] => ram_block1a20.PORTBADDR3 +address_b[3] => ram_block1a21.PORTBADDR3 +address_b[3] => ram_block1a22.PORTBADDR3 +address_b[3] => ram_block1a23.PORTBADDR3 +address_b[3] => ram_block1a24.PORTBADDR3 +address_b[3] => ram_block1a25.PORTBADDR3 +address_b[3] => ram_block1a26.PORTBADDR3 +address_b[3] => ram_block1a27.PORTBADDR3 +address_b[3] => ram_block1a28.PORTBADDR3 +address_b[3] => ram_block1a29.PORTBADDR3 +address_b[3] => ram_block1a30.PORTBADDR3 +address_b[3] => ram_block1a31.PORTBADDR3 +address_b[3] => ram_block1a32.PORTBADDR3 +address_b[3] => ram_block1a33.PORTBADDR3 +address_b[3] => ram_block1a34.PORTBADDR3 +address_b[3] => ram_block1a35.PORTBADDR3 +address_b[4] => ram_block1a0.PORTBADDR4 +address_b[4] => ram_block1a1.PORTBADDR4 +address_b[4] => ram_block1a2.PORTBADDR4 +address_b[4] => ram_block1a3.PORTBADDR4 +address_b[4] => ram_block1a4.PORTBADDR4 +address_b[4] => ram_block1a5.PORTBADDR4 +address_b[4] => ram_block1a6.PORTBADDR4 +address_b[4] => ram_block1a7.PORTBADDR4 +address_b[4] => ram_block1a8.PORTBADDR4 +address_b[4] => ram_block1a9.PORTBADDR4 +address_b[4] => ram_block1a10.PORTBADDR4 +address_b[4] => ram_block1a11.PORTBADDR4 +address_b[4] => ram_block1a12.PORTBADDR4 +address_b[4] => ram_block1a13.PORTBADDR4 +address_b[4] => ram_block1a14.PORTBADDR4 +address_b[4] => ram_block1a15.PORTBADDR4 +address_b[4] => ram_block1a16.PORTBADDR4 +address_b[4] => ram_block1a17.PORTBADDR4 +address_b[4] => ram_block1a18.PORTBADDR4 +address_b[4] => ram_block1a19.PORTBADDR4 +address_b[4] => ram_block1a20.PORTBADDR4 +address_b[4] => ram_block1a21.PORTBADDR4 +address_b[4] => ram_block1a22.PORTBADDR4 +address_b[4] => ram_block1a23.PORTBADDR4 +address_b[4] => ram_block1a24.PORTBADDR4 +address_b[4] => ram_block1a25.PORTBADDR4 +address_b[4] => ram_block1a26.PORTBADDR4 +address_b[4] => ram_block1a27.PORTBADDR4 +address_b[4] => ram_block1a28.PORTBADDR4 +address_b[4] => ram_block1a29.PORTBADDR4 +address_b[4] => ram_block1a30.PORTBADDR4 +address_b[4] => ram_block1a31.PORTBADDR4 +address_b[4] => ram_block1a32.PORTBADDR4 +address_b[4] => ram_block1a33.PORTBADDR4 +address_b[4] => ram_block1a34.PORTBADDR4 +address_b[4] => ram_block1a35.PORTBADDR4 +address_b[5] => ram_block1a0.PORTBADDR5 +address_b[5] => ram_block1a1.PORTBADDR5 +address_b[5] => ram_block1a2.PORTBADDR5 +address_b[5] => ram_block1a3.PORTBADDR5 +address_b[5] => ram_block1a4.PORTBADDR5 +address_b[5] => ram_block1a5.PORTBADDR5 +address_b[5] => ram_block1a6.PORTBADDR5 +address_b[5] => ram_block1a7.PORTBADDR5 +address_b[5] => ram_block1a8.PORTBADDR5 +address_b[5] => ram_block1a9.PORTBADDR5 +address_b[5] => ram_block1a10.PORTBADDR5 +address_b[5] => ram_block1a11.PORTBADDR5 +address_b[5] => ram_block1a12.PORTBADDR5 +address_b[5] => ram_block1a13.PORTBADDR5 +address_b[5] => ram_block1a14.PORTBADDR5 +address_b[5] => ram_block1a15.PORTBADDR5 +address_b[5] => ram_block1a16.PORTBADDR5 +address_b[5] => ram_block1a17.PORTBADDR5 +address_b[5] => ram_block1a18.PORTBADDR5 +address_b[5] => ram_block1a19.PORTBADDR5 +address_b[5] => ram_block1a20.PORTBADDR5 +address_b[5] => ram_block1a21.PORTBADDR5 +address_b[5] => ram_block1a22.PORTBADDR5 +address_b[5] => ram_block1a23.PORTBADDR5 +address_b[5] => ram_block1a24.PORTBADDR5 +address_b[5] => ram_block1a25.PORTBADDR5 +address_b[5] => ram_block1a26.PORTBADDR5 +address_b[5] => ram_block1a27.PORTBADDR5 +address_b[5] => ram_block1a28.PORTBADDR5 +address_b[5] => ram_block1a29.PORTBADDR5 +address_b[5] => ram_block1a30.PORTBADDR5 +address_b[5] => ram_block1a31.PORTBADDR5 +address_b[5] => ram_block1a32.PORTBADDR5 +address_b[5] => ram_block1a33.PORTBADDR5 +address_b[5] => ram_block1a34.PORTBADDR5 +address_b[5] => ram_block1a35.PORTBADDR5 +address_b[6] => ram_block1a0.PORTBADDR6 +address_b[6] => ram_block1a1.PORTBADDR6 +address_b[6] => ram_block1a2.PORTBADDR6 +address_b[6] => ram_block1a3.PORTBADDR6 +address_b[6] => ram_block1a4.PORTBADDR6 +address_b[6] => ram_block1a5.PORTBADDR6 +address_b[6] => ram_block1a6.PORTBADDR6 +address_b[6] => ram_block1a7.PORTBADDR6 +address_b[6] => ram_block1a8.PORTBADDR6 +address_b[6] => ram_block1a9.PORTBADDR6 +address_b[6] => ram_block1a10.PORTBADDR6 +address_b[6] => ram_block1a11.PORTBADDR6 +address_b[6] => ram_block1a12.PORTBADDR6 +address_b[6] => ram_block1a13.PORTBADDR6 +address_b[6] => ram_block1a14.PORTBADDR6 +address_b[6] => ram_block1a15.PORTBADDR6 +address_b[6] => ram_block1a16.PORTBADDR6 +address_b[6] => ram_block1a17.PORTBADDR6 +address_b[6] => ram_block1a18.PORTBADDR6 +address_b[6] => ram_block1a19.PORTBADDR6 +address_b[6] => ram_block1a20.PORTBADDR6 +address_b[6] => ram_block1a21.PORTBADDR6 +address_b[6] => ram_block1a22.PORTBADDR6 +address_b[6] => ram_block1a23.PORTBADDR6 +address_b[6] => ram_block1a24.PORTBADDR6 +address_b[6] => ram_block1a25.PORTBADDR6 +address_b[6] => ram_block1a26.PORTBADDR6 +address_b[6] => ram_block1a27.PORTBADDR6 +address_b[6] => ram_block1a28.PORTBADDR6 +address_b[6] => ram_block1a29.PORTBADDR6 +address_b[6] => ram_block1a30.PORTBADDR6 +address_b[6] => ram_block1a31.PORTBADDR6 +address_b[6] => ram_block1a32.PORTBADDR6 +address_b[6] => ram_block1a33.PORTBADDR6 +address_b[6] => ram_block1a34.PORTBADDR6 +address_b[6] => ram_block1a35.PORTBADDR6 +clock0 => ram_block1a0.CLK0 +clock0 => ram_block1a1.CLK0 +clock0 => ram_block1a2.CLK0 +clock0 => ram_block1a3.CLK0 +clock0 => ram_block1a4.CLK0 +clock0 => ram_block1a5.CLK0 +clock0 => ram_block1a6.CLK0 +clock0 => ram_block1a7.CLK0 +clock0 => ram_block1a8.CLK0 +clock0 => ram_block1a9.CLK0 +clock0 => ram_block1a10.CLK0 +clock0 => ram_block1a11.CLK0 +clock0 => ram_block1a12.CLK0 +clock0 => ram_block1a13.CLK0 +clock0 => ram_block1a14.CLK0 +clock0 => ram_block1a15.CLK0 +clock0 => ram_block1a16.CLK0 +clock0 => ram_block1a17.CLK0 +clock0 => ram_block1a18.CLK0 +clock0 => ram_block1a19.CLK0 +clock0 => ram_block1a20.CLK0 +clock0 => ram_block1a21.CLK0 +clock0 => ram_block1a22.CLK0 +clock0 => ram_block1a23.CLK0 +clock0 => ram_block1a24.CLK0 +clock0 => ram_block1a25.CLK0 +clock0 => ram_block1a26.CLK0 +clock0 => ram_block1a27.CLK0 +clock0 => ram_block1a28.CLK0 +clock0 => ram_block1a29.CLK0 +clock0 => ram_block1a30.CLK0 +clock0 => ram_block1a31.CLK0 +clock0 => ram_block1a32.CLK0 +clock0 => ram_block1a33.CLK0 +clock0 => ram_block1a34.CLK0 +clock0 => ram_block1a35.CLK0 +clock1 => ram_block1a0.CLK1 +clock1 => ram_block1a1.CLK1 +clock1 => ram_block1a2.CLK1 +clock1 => ram_block1a3.CLK1 +clock1 => ram_block1a4.CLK1 +clock1 => ram_block1a5.CLK1 +clock1 => ram_block1a6.CLK1 +clock1 => ram_block1a7.CLK1 +clock1 => ram_block1a8.CLK1 +clock1 => ram_block1a9.CLK1 +clock1 => ram_block1a10.CLK1 +clock1 => ram_block1a11.CLK1 +clock1 => ram_block1a12.CLK1 +clock1 => ram_block1a13.CLK1 +clock1 => ram_block1a14.CLK1 +clock1 => ram_block1a15.CLK1 +clock1 => ram_block1a16.CLK1 +clock1 => ram_block1a17.CLK1 +clock1 => ram_block1a18.CLK1 +clock1 => ram_block1a19.CLK1 +clock1 => ram_block1a20.CLK1 +clock1 => ram_block1a21.CLK1 +clock1 => ram_block1a22.CLK1 +clock1 => ram_block1a23.CLK1 +clock1 => ram_block1a24.CLK1 +clock1 => ram_block1a25.CLK1 +clock1 => ram_block1a26.CLK1 +clock1 => ram_block1a27.CLK1 +clock1 => ram_block1a28.CLK1 +clock1 => ram_block1a29.CLK1 +clock1 => ram_block1a30.CLK1 +clock1 => ram_block1a31.CLK1 +clock1 => ram_block1a32.CLK1 +clock1 => ram_block1a33.CLK1 +clock1 => ram_block1a34.CLK1 +clock1 => ram_block1a35.CLK1 +clocken0 => ram_block1a0.ENA0 +clocken0 => ram_block1a1.ENA0 +clocken0 => ram_block1a2.ENA0 +clocken0 => ram_block1a3.ENA0 +clocken0 => ram_block1a4.ENA0 +clocken0 => ram_block1a5.ENA0 +clocken0 => ram_block1a6.ENA0 +clocken0 => ram_block1a7.ENA0 +clocken0 => ram_block1a8.ENA0 +clocken0 => ram_block1a9.ENA0 +clocken0 => ram_block1a10.ENA0 +clocken0 => ram_block1a11.ENA0 +clocken0 => ram_block1a12.ENA0 +clocken0 => ram_block1a13.ENA0 +clocken0 => ram_block1a14.ENA0 +clocken0 => ram_block1a15.ENA0 +clocken0 => ram_block1a16.ENA0 +clocken0 => ram_block1a17.ENA0 +clocken0 => ram_block1a18.ENA0 +clocken0 => ram_block1a19.ENA0 +clocken0 => ram_block1a20.ENA0 +clocken0 => ram_block1a21.ENA0 +clocken0 => ram_block1a22.ENA0 +clocken0 => ram_block1a23.ENA0 +clocken0 => ram_block1a24.ENA0 +clocken0 => ram_block1a25.ENA0 +clocken0 => ram_block1a26.ENA0 +clocken0 => ram_block1a27.ENA0 +clocken0 => ram_block1a28.ENA0 +clocken0 => ram_block1a29.ENA0 +clocken0 => ram_block1a30.ENA0 +clocken0 => ram_block1a31.ENA0 +clocken0 => ram_block1a32.ENA0 +clocken0 => ram_block1a33.ENA0 +clocken0 => ram_block1a34.ENA0 +clocken0 => ram_block1a35.ENA0 +clocken1 => ram_block1a0.ENA1 +clocken1 => ram_block1a1.ENA1 +clocken1 => ram_block1a2.ENA1 +clocken1 => ram_block1a3.ENA1 +clocken1 => ram_block1a4.ENA1 +clocken1 => ram_block1a5.ENA1 +clocken1 => ram_block1a6.ENA1 +clocken1 => ram_block1a7.ENA1 +clocken1 => ram_block1a8.ENA1 +clocken1 => ram_block1a9.ENA1 +clocken1 => ram_block1a10.ENA1 +clocken1 => ram_block1a11.ENA1 +clocken1 => ram_block1a12.ENA1 +clocken1 => ram_block1a13.ENA1 +clocken1 => ram_block1a14.ENA1 +clocken1 => ram_block1a15.ENA1 +clocken1 => ram_block1a16.ENA1 +clocken1 => ram_block1a17.ENA1 +clocken1 => ram_block1a18.ENA1 +clocken1 => ram_block1a19.ENA1 +clocken1 => ram_block1a20.ENA1 +clocken1 => ram_block1a21.ENA1 +clocken1 => ram_block1a22.ENA1 +clocken1 => ram_block1a23.ENA1 +clocken1 => ram_block1a24.ENA1 +clocken1 => ram_block1a25.ENA1 +clocken1 => ram_block1a26.ENA1 +clocken1 => ram_block1a27.ENA1 +clocken1 => ram_block1a28.ENA1 +clocken1 => ram_block1a29.ENA1 +clocken1 => ram_block1a30.ENA1 +clocken1 => ram_block1a31.ENA1 +clocken1 => ram_block1a32.ENA1 +clocken1 => ram_block1a33.ENA1 +clocken1 => ram_block1a34.ENA1 +clocken1 => ram_block1a35.ENA1 +data_a[0] => ram_block1a0.PORTADATAIN +data_a[1] => ram_block1a1.PORTADATAIN +data_a[2] => ram_block1a2.PORTADATAIN +data_a[3] => ram_block1a3.PORTADATAIN +data_a[4] => ram_block1a4.PORTADATAIN +data_a[5] => ram_block1a5.PORTADATAIN +data_a[6] => ram_block1a6.PORTADATAIN +data_a[7] => ram_block1a7.PORTADATAIN +data_a[8] => ram_block1a8.PORTADATAIN +data_a[9] => ram_block1a9.PORTADATAIN +data_a[10] => ram_block1a10.PORTADATAIN +data_a[11] => ram_block1a11.PORTADATAIN +data_a[12] => ram_block1a12.PORTADATAIN +data_a[13] => ram_block1a13.PORTADATAIN +data_a[14] => ram_block1a14.PORTADATAIN +data_a[15] => ram_block1a15.PORTADATAIN +data_a[16] => ram_block1a16.PORTADATAIN +data_a[17] => ram_block1a17.PORTADATAIN +data_a[18] => ram_block1a18.PORTADATAIN +data_a[19] => ram_block1a19.PORTADATAIN +data_a[20] => ram_block1a20.PORTADATAIN +data_a[21] => ram_block1a21.PORTADATAIN +data_a[22] => ram_block1a22.PORTADATAIN +data_a[23] => ram_block1a23.PORTADATAIN +data_a[24] => ram_block1a24.PORTADATAIN +data_a[25] => ram_block1a25.PORTADATAIN +data_a[26] => ram_block1a26.PORTADATAIN +data_a[27] => ram_block1a27.PORTADATAIN +data_a[28] => ram_block1a28.PORTADATAIN +data_a[29] => ram_block1a29.PORTADATAIN +data_a[30] => ram_block1a30.PORTADATAIN +data_a[31] => ram_block1a31.PORTADATAIN +data_a[32] => ram_block1a32.PORTADATAIN +data_a[33] => ram_block1a33.PORTADATAIN +data_a[34] => ram_block1a34.PORTADATAIN +data_a[35] => ram_block1a35.PORTADATAIN +data_b[0] => ram_block1a0.PORTBDATAIN +data_b[1] => ram_block1a1.PORTBDATAIN +data_b[2] => ram_block1a2.PORTBDATAIN +data_b[3] => ram_block1a3.PORTBDATAIN +data_b[4] => ram_block1a4.PORTBDATAIN +data_b[5] => ram_block1a5.PORTBDATAIN +data_b[6] => ram_block1a6.PORTBDATAIN +data_b[7] => ram_block1a7.PORTBDATAIN +data_b[8] => ram_block1a8.PORTBDATAIN +data_b[9] => ram_block1a9.PORTBDATAIN +data_b[10] => ram_block1a10.PORTBDATAIN +data_b[11] => ram_block1a11.PORTBDATAIN +data_b[12] => ram_block1a12.PORTBDATAIN +data_b[13] => ram_block1a13.PORTBDATAIN +data_b[14] => ram_block1a14.PORTBDATAIN +data_b[15] => ram_block1a15.PORTBDATAIN +data_b[16] => ram_block1a16.PORTBDATAIN +data_b[17] => ram_block1a17.PORTBDATAIN +data_b[18] => ram_block1a18.PORTBDATAIN +data_b[19] => ram_block1a19.PORTBDATAIN +data_b[20] => ram_block1a20.PORTBDATAIN +data_b[21] => ram_block1a21.PORTBDATAIN +data_b[22] => ram_block1a22.PORTBDATAIN +data_b[23] => ram_block1a23.PORTBDATAIN +data_b[24] => ram_block1a24.PORTBDATAIN +data_b[25] => ram_block1a25.PORTBDATAIN +data_b[26] => ram_block1a26.PORTBDATAIN +data_b[27] => ram_block1a27.PORTBDATAIN +data_b[28] => ram_block1a28.PORTBDATAIN +data_b[29] => ram_block1a29.PORTBDATAIN +data_b[30] => ram_block1a30.PORTBDATAIN +data_b[31] => ram_block1a31.PORTBDATAIN +data_b[32] => ram_block1a32.PORTBDATAIN +data_b[33] => ram_block1a33.PORTBDATAIN +data_b[34] => ram_block1a34.PORTBDATAIN +data_b[35] => ram_block1a35.PORTBDATAIN +q_a[0] <= ram_block1a0.PORTADATAOUT +q_a[1] <= ram_block1a1.PORTADATAOUT +q_a[2] <= ram_block1a2.PORTADATAOUT +q_a[3] <= ram_block1a3.PORTADATAOUT +q_a[4] <= ram_block1a4.PORTADATAOUT +q_a[5] <= ram_block1a5.PORTADATAOUT +q_a[6] <= ram_block1a6.PORTADATAOUT +q_a[7] <= ram_block1a7.PORTADATAOUT +q_a[8] <= ram_block1a8.PORTADATAOUT +q_a[9] <= ram_block1a9.PORTADATAOUT +q_a[10] <= ram_block1a10.PORTADATAOUT +q_a[11] <= ram_block1a11.PORTADATAOUT +q_a[12] <= ram_block1a12.PORTADATAOUT +q_a[13] <= ram_block1a13.PORTADATAOUT +q_a[14] <= ram_block1a14.PORTADATAOUT +q_a[15] <= ram_block1a15.PORTADATAOUT +q_a[16] <= ram_block1a16.PORTADATAOUT +q_a[17] <= ram_block1a17.PORTADATAOUT +q_a[18] <= ram_block1a18.PORTADATAOUT +q_a[19] <= ram_block1a19.PORTADATAOUT +q_a[20] <= ram_block1a20.PORTADATAOUT +q_a[21] <= ram_block1a21.PORTADATAOUT +q_a[22] <= ram_block1a22.PORTADATAOUT +q_a[23] <= ram_block1a23.PORTADATAOUT +q_a[24] <= ram_block1a24.PORTADATAOUT +q_a[25] <= ram_block1a25.PORTADATAOUT +q_a[26] <= ram_block1a26.PORTADATAOUT +q_a[27] <= ram_block1a27.PORTADATAOUT +q_a[28] <= ram_block1a28.PORTADATAOUT +q_a[29] <= ram_block1a29.PORTADATAOUT +q_a[30] <= ram_block1a30.PORTADATAOUT +q_a[31] <= ram_block1a31.PORTADATAOUT +q_a[32] <= ram_block1a32.PORTADATAOUT +q_a[33] <= ram_block1a33.PORTADATAOUT +q_a[34] <= ram_block1a34.PORTADATAOUT +q_a[35] <= ram_block1a35.PORTADATAOUT +q_b[0] <= ram_block1a0.PORTBDATAOUT +q_b[1] <= ram_block1a1.PORTBDATAOUT +q_b[2] <= ram_block1a2.PORTBDATAOUT +q_b[3] <= ram_block1a3.PORTBDATAOUT +q_b[4] <= ram_block1a4.PORTBDATAOUT +q_b[5] <= ram_block1a5.PORTBDATAOUT +q_b[6] <= ram_block1a6.PORTBDATAOUT +q_b[7] <= ram_block1a7.PORTBDATAOUT +q_b[8] <= ram_block1a8.PORTBDATAOUT +q_b[9] <= ram_block1a9.PORTBDATAOUT +q_b[10] <= ram_block1a10.PORTBDATAOUT +q_b[11] <= ram_block1a11.PORTBDATAOUT +q_b[12] <= ram_block1a12.PORTBDATAOUT +q_b[13] <= ram_block1a13.PORTBDATAOUT +q_b[14] <= ram_block1a14.PORTBDATAOUT +q_b[15] <= ram_block1a15.PORTBDATAOUT +q_b[16] <= ram_block1a16.PORTBDATAOUT +q_b[17] <= ram_block1a17.PORTBDATAOUT +q_b[18] <= ram_block1a18.PORTBDATAOUT +q_b[19] <= ram_block1a19.PORTBDATAOUT +q_b[20] <= ram_block1a20.PORTBDATAOUT +q_b[21] <= ram_block1a21.PORTBDATAOUT +q_b[22] <= ram_block1a22.PORTBDATAOUT +q_b[23] <= ram_block1a23.PORTBDATAOUT +q_b[24] <= ram_block1a24.PORTBDATAOUT +q_b[25] <= ram_block1a25.PORTBDATAOUT +q_b[26] <= ram_block1a26.PORTBDATAOUT +q_b[27] <= ram_block1a27.PORTBDATAOUT +q_b[28] <= ram_block1a28.PORTBDATAOUT +q_b[29] <= ram_block1a29.PORTBDATAOUT +q_b[30] <= ram_block1a30.PORTBDATAOUT +q_b[31] <= ram_block1a31.PORTBDATAOUT +q_b[32] <= ram_block1a32.PORTBDATAOUT +q_b[33] <= ram_block1a33.PORTBDATAOUT +q_b[34] <= ram_block1a34.PORTBDATAOUT +q_b[35] <= ram_block1a35.PORTBDATAOUT +wren_a => ram_block1a0.PORTAWE +wren_a => ram_block1a1.PORTAWE +wren_a => ram_block1a2.PORTAWE +wren_a => ram_block1a3.PORTAWE +wren_a => ram_block1a4.PORTAWE +wren_a => ram_block1a5.PORTAWE +wren_a => ram_block1a6.PORTAWE +wren_a => ram_block1a7.PORTAWE +wren_a => ram_block1a8.PORTAWE +wren_a => ram_block1a9.PORTAWE +wren_a => ram_block1a10.PORTAWE +wren_a => ram_block1a11.PORTAWE +wren_a => ram_block1a12.PORTAWE +wren_a => ram_block1a13.PORTAWE +wren_a => ram_block1a14.PORTAWE +wren_a => ram_block1a15.PORTAWE +wren_a => ram_block1a16.PORTAWE +wren_a => ram_block1a17.PORTAWE +wren_a => ram_block1a18.PORTAWE +wren_a => ram_block1a19.PORTAWE +wren_a => ram_block1a20.PORTAWE +wren_a => ram_block1a21.PORTAWE +wren_a => ram_block1a22.PORTAWE +wren_a => ram_block1a23.PORTAWE +wren_a => ram_block1a24.PORTAWE +wren_a => ram_block1a25.PORTAWE +wren_a => ram_block1a26.PORTAWE +wren_a => ram_block1a27.PORTAWE +wren_a => ram_block1a28.PORTAWE +wren_a => ram_block1a29.PORTAWE +wren_a => ram_block1a30.PORTAWE +wren_a => ram_block1a31.PORTAWE +wren_a => ram_block1a32.PORTAWE +wren_a => ram_block1a33.PORTAWE +wren_a => ram_block1a34.PORTAWE +wren_a => ram_block1a35.PORTAWE +wren_b => ram_block1a0.PORTBWE +wren_b => ram_block1a1.PORTBWE +wren_b => ram_block1a2.PORTBWE +wren_b => ram_block1a3.PORTBWE +wren_b => ram_block1a4.PORTBWE +wren_b => ram_block1a5.PORTBWE +wren_b => ram_block1a6.PORTBWE +wren_b => ram_block1a7.PORTBWE +wren_b => ram_block1a8.PORTBWE +wren_b => ram_block1a9.PORTBWE +wren_b => ram_block1a10.PORTBWE +wren_b => ram_block1a11.PORTBWE +wren_b => ram_block1a12.PORTBWE +wren_b => ram_block1a13.PORTBWE +wren_b => ram_block1a14.PORTBWE +wren_b => ram_block1a15.PORTBWE +wren_b => ram_block1a16.PORTBWE +wren_b => ram_block1a17.PORTBWE +wren_b => ram_block1a18.PORTBWE +wren_b => ram_block1a19.PORTBWE +wren_b => ram_block1a20.PORTBWE +wren_b => ram_block1a21.PORTBWE +wren_b => ram_block1a22.PORTBWE +wren_b => ram_block1a23.PORTBWE +wren_b => ram_block1a24.PORTBWE +wren_b => ram_block1a25.PORTBWE +wren_b => ram_block1a26.PORTBWE +wren_b => ram_block1a27.PORTBWE +wren_b => ram_block1a28.PORTBWE +wren_b => ram_block1a29.PORTBWE +wren_b => ram_block1a30.PORTBWE +wren_b => ram_block1a31.PORTBWE +wren_b => ram_block1a32.PORTBWE +wren_b => ram_block1a33.PORTBWE +wren_b => ram_block1a34.PORTBWE +wren_b => ram_block1a35.PORTBWE + + +|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper +MonDReg[0] => MonDReg[0].IN1 +MonDReg[1] => MonDReg[1].IN1 +MonDReg[2] => MonDReg[2].IN1 +MonDReg[3] => MonDReg[3].IN1 +MonDReg[4] => MonDReg[4].IN1 +MonDReg[5] => MonDReg[5].IN1 +MonDReg[6] => MonDReg[6].IN1 +MonDReg[7] => MonDReg[7].IN1 +MonDReg[8] => MonDReg[8].IN1 +MonDReg[9] => MonDReg[9].IN1 +MonDReg[10] => MonDReg[10].IN1 +MonDReg[11] => MonDReg[11].IN1 +MonDReg[12] => MonDReg[12].IN1 +MonDReg[13] => MonDReg[13].IN1 +MonDReg[14] => MonDReg[14].IN1 +MonDReg[15] => MonDReg[15].IN1 +MonDReg[16] => MonDReg[16].IN1 +MonDReg[17] => MonDReg[17].IN1 +MonDReg[18] => MonDReg[18].IN1 +MonDReg[19] => MonDReg[19].IN1 +MonDReg[20] => MonDReg[20].IN1 +MonDReg[21] => MonDReg[21].IN1 +MonDReg[22] => MonDReg[22].IN1 +MonDReg[23] => MonDReg[23].IN1 +MonDReg[24] => MonDReg[24].IN1 +MonDReg[25] => MonDReg[25].IN1 +MonDReg[26] => MonDReg[26].IN1 +MonDReg[27] => MonDReg[27].IN1 +MonDReg[28] => MonDReg[28].IN1 +MonDReg[29] => MonDReg[29].IN1 +MonDReg[30] => MonDReg[30].IN1 +MonDReg[31] => MonDReg[31].IN1 +break_readreg[0] => break_readreg[0].IN1 +break_readreg[1] => break_readreg[1].IN1 +break_readreg[2] => break_readreg[2].IN1 +break_readreg[3] => break_readreg[3].IN1 +break_readreg[4] => break_readreg[4].IN1 +break_readreg[5] => break_readreg[5].IN1 +break_readreg[6] => break_readreg[6].IN1 +break_readreg[7] => break_readreg[7].IN1 +break_readreg[8] => break_readreg[8].IN1 +break_readreg[9] => break_readreg[9].IN1 +break_readreg[10] => break_readreg[10].IN1 +break_readreg[11] => break_readreg[11].IN1 +break_readreg[12] => break_readreg[12].IN1 +break_readreg[13] => break_readreg[13].IN1 +break_readreg[14] => break_readreg[14].IN1 +break_readreg[15] => break_readreg[15].IN1 +break_readreg[16] => break_readreg[16].IN1 +break_readreg[17] => break_readreg[17].IN1 +break_readreg[18] => break_readreg[18].IN1 +break_readreg[19] => break_readreg[19].IN1 +break_readreg[20] => break_readreg[20].IN1 +break_readreg[21] => break_readreg[21].IN1 +break_readreg[22] => break_readreg[22].IN1 +break_readreg[23] => break_readreg[23].IN1 +break_readreg[24] => break_readreg[24].IN1 +break_readreg[25] => break_readreg[25].IN1 +break_readreg[26] => break_readreg[26].IN1 +break_readreg[27] => break_readreg[27].IN1 +break_readreg[28] => break_readreg[28].IN1 +break_readreg[29] => break_readreg[29].IN1 +break_readreg[30] => break_readreg[30].IN1 +break_readreg[31] => break_readreg[31].IN1 +clk => clk.IN1 +dbrk_hit0_latch => dbrk_hit0_latch.IN1 +dbrk_hit1_latch => dbrk_hit1_latch.IN1 +dbrk_hit2_latch => dbrk_hit2_latch.IN1 +dbrk_hit3_latch => dbrk_hit3_latch.IN1 +debugack => debugack.IN1 +monitor_error => monitor_error.IN1 +monitor_ready => monitor_ready.IN1 +reset_n => reset_n.IN1 +resetlatch => resetlatch.IN1 +tracemem_on => tracemem_on.IN1 +tracemem_trcdata[0] => tracemem_trcdata[0].IN1 +tracemem_trcdata[1] => tracemem_trcdata[1].IN1 +tracemem_trcdata[2] => tracemem_trcdata[2].IN1 +tracemem_trcdata[3] => tracemem_trcdata[3].IN1 +tracemem_trcdata[4] => tracemem_trcdata[4].IN1 +tracemem_trcdata[5] => tracemem_trcdata[5].IN1 +tracemem_trcdata[6] => tracemem_trcdata[6].IN1 +tracemem_trcdata[7] => tracemem_trcdata[7].IN1 +tracemem_trcdata[8] => tracemem_trcdata[8].IN1 +tracemem_trcdata[9] => tracemem_trcdata[9].IN1 +tracemem_trcdata[10] => tracemem_trcdata[10].IN1 +tracemem_trcdata[11] => tracemem_trcdata[11].IN1 +tracemem_trcdata[12] => tracemem_trcdata[12].IN1 +tracemem_trcdata[13] => tracemem_trcdata[13].IN1 +tracemem_trcdata[14] => tracemem_trcdata[14].IN1 +tracemem_trcdata[15] => tracemem_trcdata[15].IN1 +tracemem_trcdata[16] => tracemem_trcdata[16].IN1 +tracemem_trcdata[17] => tracemem_trcdata[17].IN1 +tracemem_trcdata[18] => tracemem_trcdata[18].IN1 +tracemem_trcdata[19] => tracemem_trcdata[19].IN1 +tracemem_trcdata[20] => tracemem_trcdata[20].IN1 +tracemem_trcdata[21] => tracemem_trcdata[21].IN1 +tracemem_trcdata[22] => tracemem_trcdata[22].IN1 +tracemem_trcdata[23] => tracemem_trcdata[23].IN1 +tracemem_trcdata[24] => tracemem_trcdata[24].IN1 +tracemem_trcdata[25] => tracemem_trcdata[25].IN1 +tracemem_trcdata[26] => tracemem_trcdata[26].IN1 +tracemem_trcdata[27] => tracemem_trcdata[27].IN1 +tracemem_trcdata[28] => tracemem_trcdata[28].IN1 +tracemem_trcdata[29] => tracemem_trcdata[29].IN1 +tracemem_trcdata[30] => tracemem_trcdata[30].IN1 +tracemem_trcdata[31] => tracemem_trcdata[31].IN1 +tracemem_trcdata[32] => tracemem_trcdata[32].IN1 +tracemem_trcdata[33] => tracemem_trcdata[33].IN1 +tracemem_trcdata[34] => tracemem_trcdata[34].IN1 +tracemem_trcdata[35] => tracemem_trcdata[35].IN1 +tracemem_tw => tracemem_tw.IN1 +trc_im_addr[0] => trc_im_addr[0].IN1 +trc_im_addr[1] => trc_im_addr[1].IN1 +trc_im_addr[2] => trc_im_addr[2].IN1 +trc_im_addr[3] => trc_im_addr[3].IN1 +trc_im_addr[4] => trc_im_addr[4].IN1 +trc_im_addr[5] => trc_im_addr[5].IN1 +trc_im_addr[6] => trc_im_addr[6].IN1 +trc_on => trc_on.IN1 +trc_wrap => trc_wrap.IN1 +trigbrktype => trigbrktype.IN1 +trigger_state_1 => trigger_state_1.IN1 +jdo[0] <= system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk.jdo +jdo[1] <= system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk.jdo +jdo[2] <= system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk.jdo +jdo[3] <= system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk.jdo +jdo[4] <= system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk.jdo +jdo[5] <= system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk.jdo +jdo[6] <= system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk.jdo +jdo[7] <= system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk.jdo +jdo[8] <= system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk.jdo +jdo[9] <= system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk.jdo +jdo[10] <= system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk.jdo +jdo[11] <= system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk.jdo +jdo[12] <= system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk.jdo +jdo[13] <= system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk.jdo +jdo[14] <= system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk.jdo +jdo[15] <= system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk.jdo +jdo[16] <= system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk.jdo +jdo[17] <= system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk.jdo +jdo[18] <= system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk.jdo +jdo[19] <= system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk.jdo +jdo[20] <= system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk.jdo +jdo[21] <= system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk.jdo +jdo[22] <= system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk.jdo +jdo[23] <= system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk.jdo +jdo[24] <= system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk.jdo +jdo[25] <= system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk.jdo +jdo[26] <= system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk.jdo +jdo[27] <= system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk.jdo +jdo[28] <= system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk.jdo +jdo[29] <= system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk.jdo +jdo[30] <= system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk.jdo +jdo[31] <= system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk.jdo +jdo[32] <= system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk.jdo +jdo[33] <= system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk.jdo +jdo[34] <= system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk.jdo +jdo[35] <= system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk.jdo +jdo[36] <= system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk.jdo +jdo[37] <= system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk.jdo +jrst_n <= system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck.jrst_n +st_ready_test_idle <= system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck.st_ready_test_idle +take_action_break_a <= system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk.take_action_break_a +take_action_break_b <= system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk.take_action_break_b +take_action_break_c <= system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk.take_action_break_c +take_action_ocimem_a <= system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk.take_action_ocimem_a +take_action_ocimem_b <= system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk.take_action_ocimem_b +take_action_tracectrl <= system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk.take_action_tracectrl +take_action_tracemem_a <= system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk.take_action_tracemem_a +take_action_tracemem_b <= system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk.take_action_tracemem_b +take_no_action_break_a <= system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk.take_no_action_break_a +take_no_action_break_b <= system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk.take_no_action_break_b +take_no_action_break_c <= system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk.take_no_action_break_c +take_no_action_ocimem_a <= system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk.take_no_action_ocimem_a +take_no_action_tracemem_a <= system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk.take_no_action_tracemem_a + + +|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck +MonDReg[0] => Mux36.IN0 +MonDReg[1] => Mux35.IN0 +MonDReg[2] => Mux34.IN0 +MonDReg[3] => Mux33.IN0 +MonDReg[4] => Mux32.IN0 +MonDReg[5] => Mux31.IN0 +MonDReg[6] => Mux30.IN0 +MonDReg[7] => Mux29.IN0 +MonDReg[8] => Mux28.IN1 +MonDReg[9] => Mux27.IN1 +MonDReg[10] => Mux26.IN1 +MonDReg[11] => Mux25.IN1 +MonDReg[12] => Mux24.IN1 +MonDReg[13] => Mux23.IN1 +MonDReg[14] => Mux22.IN1 +MonDReg[15] => Mux21.IN1 +MonDReg[16] => Mux20.IN1 +MonDReg[17] => Mux19.IN1 +MonDReg[18] => Mux18.IN1 +MonDReg[19] => Mux17.IN1 +MonDReg[20] => Mux16.IN1 +MonDReg[21] => Mux15.IN1 +MonDReg[22] => Mux14.IN1 +MonDReg[23] => Mux13.IN1 +MonDReg[24] => Mux12.IN1 +MonDReg[25] => Mux11.IN1 +MonDReg[26] => Mux10.IN1 +MonDReg[27] => Mux9.IN1 +MonDReg[28] => Mux8.IN1 +MonDReg[29] => Mux7.IN1 +MonDReg[30] => Mux6.IN1 +MonDReg[31] => Mux5.IN1 +break_readreg[0] => Mux36.IN1 +break_readreg[1] => Mux35.IN1 +break_readreg[2] => Mux34.IN1 +break_readreg[3] => Mux33.IN1 +break_readreg[4] => Mux32.IN1 +break_readreg[5] => Mux31.IN1 +break_readreg[6] => Mux30.IN1 +break_readreg[7] => Mux29.IN1 +break_readreg[8] => Mux28.IN2 +break_readreg[9] => Mux27.IN2 +break_readreg[10] => Mux26.IN2 +break_readreg[11] => Mux25.IN2 +break_readreg[12] => Mux24.IN2 +break_readreg[13] => Mux23.IN2 +break_readreg[14] => Mux22.IN2 +break_readreg[15] => Mux21.IN2 +break_readreg[16] => Mux20.IN2 +break_readreg[17] => Mux19.IN2 +break_readreg[18] => Mux18.IN2 +break_readreg[19] => Mux17.IN2 +break_readreg[20] => Mux16.IN2 +break_readreg[21] => Mux15.IN2 +break_readreg[22] => Mux14.IN2 +break_readreg[23] => Mux13.IN2 +break_readreg[24] => Mux12.IN2 +break_readreg[25] => Mux11.IN2 +break_readreg[26] => Mux10.IN2 +break_readreg[27] => Mux9.IN2 +break_readreg[28] => Mux8.IN2 +break_readreg[29] => Mux7.IN2 +break_readreg[30] => Mux6.IN2 +break_readreg[31] => Mux5.IN2 +dbrk_hit0_latch => Mux4.IN1 +dbrk_hit1_latch => Mux3.IN1 +dbrk_hit2_latch => Mux2.IN1 +dbrk_hit3_latch => Mux1.IN2 +debugack => debugack.IN1 +ir_in[0] => Mux0.IN3 +ir_in[0] => Mux1.IN4 +ir_in[0] => Mux2.IN3 +ir_in[0] => Mux3.IN3 +ir_in[0] => Mux4.IN3 +ir_in[0] => Mux5.IN4 +ir_in[0] => Mux6.IN4 +ir_in[0] => Mux7.IN4 +ir_in[0] => Mux8.IN4 +ir_in[0] => Mux9.IN4 +ir_in[0] => Mux10.IN4 +ir_in[0] => Mux11.IN4 +ir_in[0] => Mux12.IN4 +ir_in[0] => Mux13.IN4 +ir_in[0] => Mux14.IN4 +ir_in[0] => Mux15.IN4 +ir_in[0] => Mux16.IN4 +ir_in[0] => Mux17.IN4 +ir_in[0] => Mux18.IN4 +ir_in[0] => Mux19.IN4 +ir_in[0] => Mux20.IN4 +ir_in[0] => Mux21.IN4 +ir_in[0] => Mux22.IN4 +ir_in[0] => Mux23.IN4 +ir_in[0] => Mux24.IN4 +ir_in[0] => Mux25.IN4 +ir_in[0] => Mux26.IN4 +ir_in[0] => Mux27.IN4 +ir_in[0] => Mux28.IN4 +ir_in[0] => Mux29.IN3 +ir_in[0] => Mux30.IN3 +ir_in[0] => Mux31.IN3 +ir_in[0] => Mux32.IN3 +ir_in[0] => Mux33.IN3 +ir_in[0] => Mux34.IN3 +ir_in[0] => Mux35.IN3 +ir_in[0] => Mux36.IN3 +ir_in[0] => Mux37.IN1 +ir_in[0] => Decoder0.IN1 +ir_in[1] => Mux0.IN2 +ir_in[1] => Mux1.IN3 +ir_in[1] => Mux2.IN2 +ir_in[1] => Mux3.IN2 +ir_in[1] => Mux4.IN2 +ir_in[1] => Mux5.IN3 +ir_in[1] => Mux6.IN3 +ir_in[1] => Mux7.IN3 +ir_in[1] => Mux8.IN3 +ir_in[1] => Mux9.IN3 +ir_in[1] => Mux10.IN3 +ir_in[1] => Mux11.IN3 +ir_in[1] => Mux12.IN3 +ir_in[1] => Mux13.IN3 +ir_in[1] => Mux14.IN3 +ir_in[1] => Mux15.IN3 +ir_in[1] => Mux16.IN3 +ir_in[1] => Mux17.IN3 +ir_in[1] => Mux18.IN3 +ir_in[1] => Mux19.IN3 +ir_in[1] => Mux20.IN3 +ir_in[1] => Mux21.IN3 +ir_in[1] => Mux22.IN3 +ir_in[1] => Mux23.IN3 +ir_in[1] => Mux24.IN3 +ir_in[1] => Mux25.IN3 +ir_in[1] => Mux26.IN3 +ir_in[1] => Mux27.IN3 +ir_in[1] => Mux28.IN3 +ir_in[1] => Mux29.IN2 +ir_in[1] => Mux30.IN2 +ir_in[1] => Mux31.IN2 +ir_in[1] => Mux32.IN2 +ir_in[1] => Mux33.IN2 +ir_in[1] => Mux34.IN2 +ir_in[1] => Mux35.IN2 +ir_in[1] => Mux36.IN2 +ir_in[1] => Mux37.IN0 +ir_in[1] => Decoder0.IN0 +jtag_state_rti => st_ready_test_idle.DATAIN +monitor_error => Mux3.IN4 +monitor_ready => monitor_ready.IN1 +reset_n => ~NO_FANOUT~ +resetlatch => Mux4.IN4 +tck => tck.IN2 +tdi => sr.DATAB +tdi => sr.DATAB +tdi => sr.DATAB +tdi => sr.DATAB +tdi => sr.DATAB +tdi => sr.DATAB +tracemem_on => Mux1.IN5 +tracemem_trcdata[0] => Mux37.IN2 +tracemem_trcdata[1] => Mux36.IN4 +tracemem_trcdata[2] => Mux35.IN4 +tracemem_trcdata[3] => Mux34.IN4 +tracemem_trcdata[4] => Mux33.IN4 +tracemem_trcdata[5] => Mux32.IN4 +tracemem_trcdata[6] => Mux31.IN4 +tracemem_trcdata[7] => Mux30.IN4 +tracemem_trcdata[8] => Mux29.IN4 +tracemem_trcdata[9] => Mux28.IN5 +tracemem_trcdata[10] => Mux27.IN5 +tracemem_trcdata[11] => Mux26.IN5 +tracemem_trcdata[12] => Mux25.IN5 +tracemem_trcdata[13] => Mux24.IN5 +tracemem_trcdata[14] => Mux23.IN5 +tracemem_trcdata[15] => Mux22.IN5 +tracemem_trcdata[16] => Mux21.IN5 +tracemem_trcdata[17] => Mux20.IN5 +tracemem_trcdata[18] => Mux19.IN5 +tracemem_trcdata[19] => Mux18.IN5 +tracemem_trcdata[20] => Mux17.IN5 +tracemem_trcdata[21] => Mux16.IN5 +tracemem_trcdata[22] => Mux15.IN5 +tracemem_trcdata[23] => Mux14.IN5 +tracemem_trcdata[24] => Mux13.IN5 +tracemem_trcdata[25] => Mux12.IN5 +tracemem_trcdata[26] => Mux11.IN5 +tracemem_trcdata[27] => Mux10.IN5 +tracemem_trcdata[28] => Mux9.IN5 +tracemem_trcdata[29] => Mux8.IN5 +tracemem_trcdata[30] => Mux7.IN5 +tracemem_trcdata[31] => Mux6.IN5 +tracemem_trcdata[32] => Mux5.IN5 +tracemem_trcdata[33] => Mux4.IN5 +tracemem_trcdata[34] => Mux3.IN5 +tracemem_trcdata[35] => Mux2.IN4 +tracemem_tw => Mux0.IN4 +trc_im_addr[0] => Mux35.IN5 +trc_im_addr[1] => Mux34.IN5 +trc_im_addr[2] => Mux33.IN5 +trc_im_addr[3] => Mux32.IN5 +trc_im_addr[4] => Mux31.IN5 +trc_im_addr[5] => Mux30.IN5 +trc_im_addr[6] => Mux29.IN5 +trc_on => Mux37.IN3 +trc_wrap => Mux36.IN5 +trigbrktype => Mux37.IN4 +trigger_state_1 => Mux0.IN5 +vs_cdr => sr.OUTPUTSELECT +vs_cdr => sr.OUTPUTSELECT +vs_cdr => sr.OUTPUTSELECT +vs_cdr => sr.OUTPUTSELECT +vs_cdr => sr.OUTPUTSELECT +vs_cdr => sr.OUTPUTSELECT +vs_cdr => sr.OUTPUTSELECT +vs_cdr => sr.OUTPUTSELECT +vs_cdr => sr.OUTPUTSELECT +vs_cdr => sr.OUTPUTSELECT +vs_cdr => sr.OUTPUTSELECT +vs_cdr => sr.OUTPUTSELECT +vs_cdr => sr.OUTPUTSELECT +vs_cdr => sr.OUTPUTSELECT +vs_cdr => sr.OUTPUTSELECT +vs_cdr => sr.OUTPUTSELECT +vs_cdr => sr.OUTPUTSELECT +vs_cdr => sr.OUTPUTSELECT +vs_cdr => sr.OUTPUTSELECT +vs_cdr => sr.OUTPUTSELECT +vs_cdr => sr.OUTPUTSELECT +vs_cdr => sr.OUTPUTSELECT +vs_cdr => sr.OUTPUTSELECT +vs_cdr => sr.OUTPUTSELECT +vs_cdr => sr.OUTPUTSELECT +vs_cdr => sr.OUTPUTSELECT +vs_cdr => sr.OUTPUTSELECT +vs_cdr => sr.OUTPUTSELECT +vs_cdr => sr.OUTPUTSELECT +vs_cdr => sr.OUTPUTSELECT +vs_cdr => sr.OUTPUTSELECT +vs_cdr => sr.OUTPUTSELECT +vs_cdr => sr.OUTPUTSELECT +vs_cdr => sr.OUTPUTSELECT +vs_cdr => sr.OUTPUTSELECT +vs_cdr => sr.OUTPUTSELECT +vs_cdr => sr.OUTPUTSELECT +vs_cdr => sr.OUTPUTSELECT +vs_sdr => sr.OUTPUTSELECT +vs_sdr => sr.OUTPUTSELECT +vs_sdr => sr.OUTPUTSELECT +vs_sdr => sr.OUTPUTSELECT +vs_sdr => sr.OUTPUTSELECT +vs_sdr => sr.OUTPUTSELECT +vs_sdr => sr.OUTPUTSELECT +vs_sdr => sr.OUTPUTSELECT +vs_sdr => sr.OUTPUTSELECT +vs_sdr => sr.OUTPUTSELECT +vs_sdr => sr.OUTPUTSELECT +vs_sdr => sr.OUTPUTSELECT +vs_sdr => sr.OUTPUTSELECT +vs_sdr => sr.OUTPUTSELECT +vs_sdr => sr.OUTPUTSELECT +vs_sdr => sr.OUTPUTSELECT +vs_sdr => sr.OUTPUTSELECT +vs_sdr => sr.OUTPUTSELECT +vs_sdr => sr.OUTPUTSELECT +vs_sdr => sr.OUTPUTSELECT +vs_sdr => sr.OUTPUTSELECT +vs_sdr => sr.OUTPUTSELECT +vs_sdr => sr.OUTPUTSELECT +vs_sdr => sr.OUTPUTSELECT +vs_sdr => sr.OUTPUTSELECT +vs_sdr => sr.OUTPUTSELECT +vs_sdr => sr.OUTPUTSELECT +vs_sdr => sr.OUTPUTSELECT +vs_sdr => sr.OUTPUTSELECT +vs_sdr => sr.OUTPUTSELECT +vs_sdr => sr.OUTPUTSELECT +vs_sdr => sr.OUTPUTSELECT +vs_sdr => sr.OUTPUTSELECT +vs_sdr => sr.OUTPUTSELECT +vs_sdr => sr.OUTPUTSELECT +vs_sdr => sr.OUTPUTSELECT +vs_sdr => sr.OUTPUTSELECT +vs_sdr => sr.OUTPUTSELECT +vs_uir => DRsize.OUTPUTSELECT +vs_uir => DRsize.OUTPUTSELECT +vs_uir => DRsize.OUTPUTSELECT +vs_uir => DRsize.OUTPUTSELECT +vs_uir => DRsize.OUTPUTSELECT +vs_uir => DRsize.OUTPUTSELECT +ir_out[0] <= ir_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +ir_out[1] <= ir_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +jrst_n <= unxcomplemented_resetxx1.DB_MAX_OUTPUT_PORT_TYPE +sr[0] <= sr[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +sr[1] <= sr[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +sr[2] <= sr[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +sr[3] <= sr[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +sr[4] <= sr[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +sr[5] <= sr[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +sr[6] <= sr[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +sr[7] <= sr[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE +sr[8] <= sr[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE +sr[9] <= sr[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE +sr[10] <= sr[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE +sr[11] <= sr[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE +sr[12] <= sr[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE +sr[13] <= sr[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE +sr[14] <= sr[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE +sr[15] <= sr[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE +sr[16] <= sr[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE +sr[17] <= sr[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE +sr[18] <= sr[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE +sr[19] <= sr[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE +sr[20] <= sr[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE +sr[21] <= sr[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE +sr[22] <= sr[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE +sr[23] <= sr[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE +sr[24] <= sr[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE +sr[25] <= sr[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE +sr[26] <= sr[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE +sr[27] <= sr[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE +sr[28] <= sr[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE +sr[29] <= sr[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE +sr[30] <= sr[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE +sr[31] <= sr[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE +sr[32] <= sr[32]~reg0.DB_MAX_OUTPUT_PORT_TYPE +sr[33] <= sr[33]~reg0.DB_MAX_OUTPUT_PORT_TYPE +sr[34] <= sr[34]~reg0.DB_MAX_OUTPUT_PORT_TYPE +sr[35] <= sr[35]~reg0.DB_MAX_OUTPUT_PORT_TYPE +sr[36] <= sr[36]~reg0.DB_MAX_OUTPUT_PORT_TYPE +sr[37] <= sr[37]~reg0.DB_MAX_OUTPUT_PORT_TYPE +st_ready_test_idle <= jtag_state_rti.DB_MAX_OUTPUT_PORT_TYPE +tdo <= tdo.DB_MAX_OUTPUT_PORT_TYPE + + +|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer +clk => dreg[0].CLK +clk => din_s1.CLK +reset_n => dreg[0].ACLR +reset_n => din_s1.ACLR +din => din_s1.DATAIN +dout <= dout.DB_MAX_OUTPUT_PORT_TYPE + + +|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1 +clk => dreg[0].CLK +clk => din_s1.CLK +reset_n => dreg[0].ACLR +reset_n => din_s1.ACLR +din => din_s1.DATAIN +dout <= dout.DB_MAX_OUTPUT_PORT_TYPE + + +|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk +clk => clk.IN2 +ir_in[0] => ir[0].DATAIN +ir_in[1] => ir[1].DATAIN +sr[0] => jdo[0]~reg0.DATAIN +sr[1] => jdo[1]~reg0.DATAIN +sr[2] => jdo[2]~reg0.DATAIN +sr[3] => jdo[3]~reg0.DATAIN +sr[4] => jdo[4]~reg0.DATAIN +sr[5] => jdo[5]~reg0.DATAIN +sr[6] => jdo[6]~reg0.DATAIN +sr[7] => jdo[7]~reg0.DATAIN +sr[8] => jdo[8]~reg0.DATAIN +sr[9] => jdo[9]~reg0.DATAIN +sr[10] => jdo[10]~reg0.DATAIN +sr[11] => jdo[11]~reg0.DATAIN +sr[12] => jdo[12]~reg0.DATAIN +sr[13] => jdo[13]~reg0.DATAIN +sr[14] => jdo[14]~reg0.DATAIN +sr[15] => jdo[15]~reg0.DATAIN +sr[16] => jdo[16]~reg0.DATAIN +sr[17] => jdo[17]~reg0.DATAIN +sr[18] => jdo[18]~reg0.DATAIN +sr[19] => jdo[19]~reg0.DATAIN +sr[20] => jdo[20]~reg0.DATAIN +sr[21] => jdo[21]~reg0.DATAIN +sr[22] => jdo[22]~reg0.DATAIN +sr[23] => jdo[23]~reg0.DATAIN +sr[24] => jdo[24]~reg0.DATAIN +sr[25] => jdo[25]~reg0.DATAIN +sr[26] => jdo[26]~reg0.DATAIN +sr[27] => jdo[27]~reg0.DATAIN +sr[28] => jdo[28]~reg0.DATAIN +sr[29] => jdo[29]~reg0.DATAIN +sr[30] => jdo[30]~reg0.DATAIN +sr[31] => jdo[31]~reg0.DATAIN +sr[32] => jdo[32]~reg0.DATAIN +sr[33] => jdo[33]~reg0.DATAIN +sr[34] => jdo[34]~reg0.DATAIN +sr[35] => jdo[35]~reg0.DATAIN +sr[36] => jdo[36]~reg0.DATAIN +sr[37] => jdo[37]~reg0.DATAIN +vs_udr => vs_udr.IN1 +vs_uir => vs_uir.IN1 +jdo[0] <= jdo[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +jdo[1] <= jdo[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +jdo[2] <= jdo[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +jdo[3] <= jdo[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +jdo[4] <= jdo[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +jdo[5] <= jdo[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +jdo[6] <= jdo[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +jdo[7] <= jdo[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE +jdo[8] <= jdo[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE +jdo[9] <= jdo[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE +jdo[10] <= jdo[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE +jdo[11] <= jdo[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE +jdo[12] <= jdo[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE +jdo[13] <= jdo[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE +jdo[14] <= jdo[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE +jdo[15] <= jdo[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE +jdo[16] <= jdo[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE +jdo[17] <= jdo[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE +jdo[18] <= jdo[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE +jdo[19] <= jdo[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE +jdo[20] <= jdo[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE +jdo[21] <= jdo[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE +jdo[22] <= jdo[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE +jdo[23] <= jdo[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE +jdo[24] <= jdo[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE +jdo[25] <= jdo[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE +jdo[26] <= jdo[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE +jdo[27] <= jdo[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE +jdo[28] <= jdo[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE +jdo[29] <= jdo[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE +jdo[30] <= jdo[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE +jdo[31] <= jdo[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE +jdo[32] <= jdo[32]~reg0.DB_MAX_OUTPUT_PORT_TYPE +jdo[33] <= jdo[33]~reg0.DB_MAX_OUTPUT_PORT_TYPE +jdo[34] <= jdo[34]~reg0.DB_MAX_OUTPUT_PORT_TYPE +jdo[35] <= jdo[35]~reg0.DB_MAX_OUTPUT_PORT_TYPE +jdo[36] <= jdo[36]~reg0.DB_MAX_OUTPUT_PORT_TYPE +jdo[37] <= jdo[37]~reg0.DB_MAX_OUTPUT_PORT_TYPE +take_action_break_a <= take_action_break_a.DB_MAX_OUTPUT_PORT_TYPE +take_action_break_b <= take_action_break_b.DB_MAX_OUTPUT_PORT_TYPE +take_action_break_c <= take_action_break_c.DB_MAX_OUTPUT_PORT_TYPE +take_action_ocimem_a <= take_action_ocimem_a.DB_MAX_OUTPUT_PORT_TYPE +take_action_ocimem_b <= take_action_ocimem_b.DB_MAX_OUTPUT_PORT_TYPE +take_action_tracectrl <= take_action_tracectrl.DB_MAX_OUTPUT_PORT_TYPE +take_action_tracemem_a <= take_action_tracemem_a.DB_MAX_OUTPUT_PORT_TYPE +take_action_tracemem_b <= take_action_tracemem_b.DB_MAX_OUTPUT_PORT_TYPE +take_no_action_break_a <= take_no_action_break_a.DB_MAX_OUTPUT_PORT_TYPE +take_no_action_break_b <= take_no_action_break_b.DB_MAX_OUTPUT_PORT_TYPE +take_no_action_break_c <= take_no_action_break_c.DB_MAX_OUTPUT_PORT_TYPE +take_no_action_ocimem_a <= take_no_action_ocimem_a.DB_MAX_OUTPUT_PORT_TYPE +take_no_action_tracemem_a <= take_no_action_tracemem_a.DB_MAX_OUTPUT_PORT_TYPE + + +|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer2 +clk => dreg[0].CLK +clk => din_s1.CLK +reset_n => dreg[0].ACLR +reset_n => din_s1.ACLR +din => din_s1.DATAIN +dout <= dout.DB_MAX_OUTPUT_PORT_TYPE + + +|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3 +clk => dreg[0].CLK +clk => din_s1.CLK +reset_n => dreg[0].ACLR +reset_n => din_s1.ACLR +din => din_s1.DATAIN +dout <= dout.DB_MAX_OUTPUT_PORT_TYPE + + +|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy +tck <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_tck +tdi <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_tdi +ir_in[0] <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_ir_in +ir_in[1] <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_ir_in +tdo => tdo.IN1 +ir_out[0] => ir_out[0].IN1 +ir_out[1] => ir_out[1].IN1 +virtual_state_cdr <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_virtual_state_cdr +virtual_state_sdr <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_virtual_state_sdr +virtual_state_e1dr <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_virtual_state_e1dr +virtual_state_pdr <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_virtual_state_pdr +virtual_state_e2dr <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_virtual_state_e2dr +virtual_state_udr <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_virtual_state_udr +virtual_state_cir <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_virtual_state_cir +virtual_state_uir <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_virtual_state_uir +tms <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_tms +jtag_state_tlr <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_jtag_state_tlr +jtag_state_rti <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_jtag_state_rti +jtag_state_sdrs <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_jtag_state_sdrs +jtag_state_cdr <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_jtag_state_cdr +jtag_state_sdr <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_jtag_state_sdr +jtag_state_e1dr <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_jtag_state_e1dr +jtag_state_pdr <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_jtag_state_pdr +jtag_state_e2dr <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_jtag_state_e2dr +jtag_state_udr <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_jtag_state_udr +jtag_state_sirs <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_jtag_state_sirs +jtag_state_cir <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_jtag_state_cir +jtag_state_sir <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_jtag_state_sir +jtag_state_e1ir <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_jtag_state_e1ir +jtag_state_pir <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_jtag_state_pir +jtag_state_e2ir <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_jtag_state_e2ir +jtag_state_uir <= sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst.usr_jtag_state_uir + + +|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst +usr_tck <= raw_tck.DB_MAX_OUTPUT_PORT_TYPE +usr_tdi <= tdi.DB_MAX_OUTPUT_PORT_TYPE +usr_ir_in[0] <= ir_in[0].DB_MAX_OUTPUT_PORT_TYPE +usr_ir_in[1] <= ir_in[1].DB_MAX_OUTPUT_PORT_TYPE +usr_tdo => tdo.DATAIN +usr_ir_out[0] => ir_out[0].DATAIN +usr_ir_out[1] => ir_out[1].DATAIN +usr_virtual_state_cdr <= virtual_state_cdr.DB_MAX_OUTPUT_PORT_TYPE +usr_virtual_state_sdr <= virtual_state_sdr.DB_MAX_OUTPUT_PORT_TYPE +usr_virtual_state_e1dr <= virtual_state_e1dr.DB_MAX_OUTPUT_PORT_TYPE +usr_virtual_state_pdr <= virtual_state_pdr.DB_MAX_OUTPUT_PORT_TYPE +usr_virtual_state_e2dr <= virtual_state_e2dr.DB_MAX_OUTPUT_PORT_TYPE +usr_virtual_state_udr <= virtual_state_udr.DB_MAX_OUTPUT_PORT_TYPE +usr_virtual_state_cir <= jtag_state_cdr.DB_MAX_OUTPUT_PORT_TYPE +usr_virtual_state_uir <= virtual_state_uir.DB_MAX_OUTPUT_PORT_TYPE +usr_tms <= raw_tms.DB_MAX_OUTPUT_PORT_TYPE +usr_jtag_state_tlr <= jtag_state_tlr.DB_MAX_OUTPUT_PORT_TYPE +usr_jtag_state_rti <= jtag_state_rti.DB_MAX_OUTPUT_PORT_TYPE +usr_jtag_state_sdrs <= jtag_state_sdrs.DB_MAX_OUTPUT_PORT_TYPE +usr_jtag_state_cdr <= jtag_state_cdr.DB_MAX_OUTPUT_PORT_TYPE +usr_jtag_state_sdr <= jtag_state_sdr.DB_MAX_OUTPUT_PORT_TYPE +usr_jtag_state_e1dr <= jtag_state_e1dr.DB_MAX_OUTPUT_PORT_TYPE +usr_jtag_state_pdr <= jtag_state_pdr.DB_MAX_OUTPUT_PORT_TYPE +usr_jtag_state_e2dr <= jtag_state_e2dr.DB_MAX_OUTPUT_PORT_TYPE +usr_jtag_state_udr <= jtag_state_udr.DB_MAX_OUTPUT_PORT_TYPE +usr_jtag_state_sirs <= jtag_state_sirs.DB_MAX_OUTPUT_PORT_TYPE +usr_jtag_state_cir <= jtag_state_cir.DB_MAX_OUTPUT_PORT_TYPE +usr_jtag_state_sir <= jtag_state_sir.DB_MAX_OUTPUT_PORT_TYPE +usr_jtag_state_e1ir <= jtag_state_e1ir.DB_MAX_OUTPUT_PORT_TYPE +usr_jtag_state_pir <= jtag_state_pir.DB_MAX_OUTPUT_PORT_TYPE +usr_jtag_state_e2ir <= jtag_state_e2ir.DB_MAX_OUTPUT_PORT_TYPE +usr_jtag_state_uir <= jtag_state_uir.DB_MAX_OUTPUT_PORT_TYPE +raw_tck => usr_tck.DATAIN +raw_tms => usr_tms.DATAIN +tdi => usr_tdi.DATAIN +jtag_state_tlr => usr_jtag_state_tlr.DATAIN +jtag_state_rti => usr_jtag_state_rti.DATAIN +jtag_state_sdrs => usr_jtag_state_sdrs.DATAIN +jtag_state_cdr => virtual_state_cdr.IN1 +jtag_state_cdr => usr_virtual_state_cir.DATAIN +jtag_state_cdr => usr_jtag_state_cdr.DATAIN +jtag_state_sdr => virtual_state_sdr.IN1 +jtag_state_sdr => usr_jtag_state_sdr.DATAIN +jtag_state_e1dr => virtual_state_e1dr.IN1 +jtag_state_e1dr => usr_jtag_state_e1dr.DATAIN +jtag_state_pdr => virtual_state_pdr.IN1 +jtag_state_pdr => usr_jtag_state_pdr.DATAIN +jtag_state_e2dr => virtual_state_e2dr.IN1 +jtag_state_e2dr => usr_jtag_state_e2dr.DATAIN +jtag_state_udr => virtual_state_udr.IN1 +jtag_state_udr => virtual_state_uir.IN1 +jtag_state_udr => usr_jtag_state_udr.DATAIN +jtag_state_sirs => usr_jtag_state_sirs.DATAIN +jtag_state_cir => usr_jtag_state_cir.DATAIN +jtag_state_sir => usr_jtag_state_sir.DATAIN +jtag_state_e1ir => usr_jtag_state_e1ir.DATAIN +jtag_state_pir => usr_jtag_state_pir.DATAIN +jtag_state_e2ir => usr_jtag_state_e2ir.DATAIN +jtag_state_uir => usr_jtag_state_uir.DATAIN +usr1 => virtual_ir_scan.IN0 +usr1 => virtual_dr_scan.IN0 +clr => ~NO_FANOUT~ +ena => virtual_dr_scan.IN1 +ena => virtual_ir_scan.IN1 +ir_in[0] => usr_ir_in[0].DATAIN +ir_in[1] => usr_ir_in[1].DATAIN +tdo <= usr_tdo.DB_MAX_OUTPUT_PORT_TYPE +ir_out[0] <= usr_ir_out[0].DB_MAX_OUTPUT_PORT_TYPE +ir_out[1] <= usr_ir_out[1].DB_MAX_OUTPUT_PORT_TYPE + + +|de0_nano_system|system:inst_cpu|system_sysid:sysid +address => readdata[30].DATAIN +address => readdata[28].DATAIN +address => readdata[25].DATAIN +address => readdata[24].DATAIN +address => readdata[20].DATAIN +address => readdata[19].DATAIN +address => readdata[15].DATAIN +address => readdata[13].DATAIN +address => readdata[10].DATAIN +address => readdata[8].DATAIN +address => readdata[7].DATAIN +address => readdata[3].DATAIN +address => readdata[2].DATAIN +address => readdata[1].DATAIN +clock => ~NO_FANOUT~ +reset_n => ~NO_FANOUT~ +readdata[0] <= +readdata[1] <= address.DB_MAX_OUTPUT_PORT_TYPE +readdata[2] <= address.DB_MAX_OUTPUT_PORT_TYPE +readdata[3] <= address.DB_MAX_OUTPUT_PORT_TYPE +readdata[4] <= +readdata[5] <= +readdata[6] <= +readdata[7] <= address.DB_MAX_OUTPUT_PORT_TYPE +readdata[8] <= address.DB_MAX_OUTPUT_PORT_TYPE +readdata[9] <= +readdata[10] <= address.DB_MAX_OUTPUT_PORT_TYPE +readdata[11] <= +readdata[12] <= +readdata[13] <= address.DB_MAX_OUTPUT_PORT_TYPE +readdata[14] <= +readdata[15] <= address.DB_MAX_OUTPUT_PORT_TYPE +readdata[16] <= +readdata[17] <= +readdata[18] <= +readdata[19] <= address.DB_MAX_OUTPUT_PORT_TYPE +readdata[20] <= address.DB_MAX_OUTPUT_PORT_TYPE +readdata[21] <= +readdata[22] <= +readdata[23] <= +readdata[24] <= address.DB_MAX_OUTPUT_PORT_TYPE +readdata[25] <= address.DB_MAX_OUTPUT_PORT_TYPE +readdata[26] <= +readdata[27] <= +readdata[28] <= address.DB_MAX_OUTPUT_PORT_TYPE +readdata[29] <= +readdata[30] <= address.DB_MAX_OUTPUT_PORT_TYPE +readdata[31] <= + + +|de0_nano_system|system:inst_cpu|system_sdram:sdram +az_addr[0] => az_addr[0].IN1 +az_addr[1] => az_addr[1].IN1 +az_addr[2] => az_addr[2].IN1 +az_addr[3] => az_addr[3].IN1 +az_addr[4] => az_addr[4].IN1 +az_addr[5] => az_addr[5].IN1 +az_addr[6] => az_addr[6].IN1 +az_addr[7] => az_addr[7].IN1 +az_addr[8] => az_addr[8].IN1 +az_addr[9] => az_addr[9].IN1 +az_addr[10] => az_addr[10].IN1 +az_addr[11] => az_addr[11].IN1 +az_addr[12] => az_addr[12].IN1 +az_addr[13] => az_addr[13].IN1 +az_addr[14] => az_addr[14].IN1 +az_addr[15] => az_addr[15].IN1 +az_addr[16] => az_addr[16].IN1 +az_addr[17] => az_addr[17].IN1 +az_addr[18] => az_addr[18].IN1 +az_addr[19] => az_addr[19].IN1 +az_addr[20] => az_addr[20].IN1 +az_addr[21] => az_addr[21].IN1 +az_addr[22] => az_addr[22].IN1 +az_be_n[0] => comb.DATAA +az_be_n[1] => comb.DATAA +az_cs => ~NO_FANOUT~ +az_data[0] => az_data[0].IN1 +az_data[1] => az_data[1].IN1 +az_data[2] => az_data[2].IN1 +az_data[3] => az_data[3].IN1 +az_data[4] => az_data[4].IN1 +az_data[5] => az_data[5].IN1 +az_data[6] => az_data[6].IN1 +az_data[7] => az_data[7].IN1 +az_data[8] => az_data[8].IN1 +az_data[9] => az_data[9].IN1 +az_data[10] => az_data[10].IN1 +az_data[11] => az_data[11].IN1 +az_data[12] => az_data[12].IN1 +az_data[13] => az_data[13].IN1 +az_data[14] => az_data[14].IN1 +az_data[15] => az_data[15].IN1 +az_rd_n => comb.IN0 +az_wr_n => az_wr_n.IN1 +clk => clk.IN1 +reset_n => reset_n.IN1 +za_data[0] <= za_data[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +za_data[1] <= za_data[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +za_data[2] <= za_data[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +za_data[3] <= za_data[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +za_data[4] <= za_data[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +za_data[5] <= za_data[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +za_data[6] <= za_data[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +za_data[7] <= za_data[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE +za_data[8] <= za_data[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE +za_data[9] <= za_data[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE +za_data[10] <= za_data[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE +za_data[11] <= za_data[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE +za_data[12] <= za_data[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE +za_data[13] <= za_data[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE +za_data[14] <= za_data[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE +za_data[15] <= za_data[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE +za_valid <= za_valid~reg0.DB_MAX_OUTPUT_PORT_TYPE +za_waitrequest <= system_sdram_input_efifo_module:the_system_sdram_input_efifo_module.full +zs_addr[0] <= zs_addr[0].DB_MAX_OUTPUT_PORT_TYPE +zs_addr[1] <= zs_addr[1].DB_MAX_OUTPUT_PORT_TYPE +zs_addr[2] <= zs_addr[2].DB_MAX_OUTPUT_PORT_TYPE +zs_addr[3] <= zs_addr[3].DB_MAX_OUTPUT_PORT_TYPE +zs_addr[4] <= zs_addr[4].DB_MAX_OUTPUT_PORT_TYPE +zs_addr[5] <= zs_addr[5].DB_MAX_OUTPUT_PORT_TYPE +zs_addr[6] <= zs_addr[6].DB_MAX_OUTPUT_PORT_TYPE +zs_addr[7] <= zs_addr[7].DB_MAX_OUTPUT_PORT_TYPE +zs_addr[8] <= zs_addr[8].DB_MAX_OUTPUT_PORT_TYPE +zs_addr[9] <= zs_addr[9].DB_MAX_OUTPUT_PORT_TYPE +zs_addr[10] <= zs_addr[10].DB_MAX_OUTPUT_PORT_TYPE +zs_addr[11] <= zs_addr[11].DB_MAX_OUTPUT_PORT_TYPE +zs_addr[12] <= zs_addr[12].DB_MAX_OUTPUT_PORT_TYPE +zs_ba[0] <= zs_ba[0].DB_MAX_OUTPUT_PORT_TYPE +zs_ba[1] <= zs_ba[1].DB_MAX_OUTPUT_PORT_TYPE +zs_cas_n <= zs_cas_n.DB_MAX_OUTPUT_PORT_TYPE +zs_cke <= +zs_cs_n <= zs_cs_n.DB_MAX_OUTPUT_PORT_TYPE +zs_dq[0] <> zs_dq[0] +zs_dq[1] <> zs_dq[1] +zs_dq[2] <> zs_dq[2] +zs_dq[3] <> zs_dq[3] +zs_dq[4] <> zs_dq[4] +zs_dq[5] <> zs_dq[5] +zs_dq[6] <> zs_dq[6] +zs_dq[7] <> zs_dq[7] +zs_dq[8] <> zs_dq[8] +zs_dq[9] <> zs_dq[9] +zs_dq[10] <> zs_dq[10] +zs_dq[11] <> zs_dq[11] +zs_dq[12] <> zs_dq[12] +zs_dq[13] <> zs_dq[13] +zs_dq[14] <> zs_dq[14] +zs_dq[15] <> zs_dq[15] +zs_dqm[0] <= zs_dqm[0].DB_MAX_OUTPUT_PORT_TYPE +zs_dqm[1] <= zs_dqm[1].DB_MAX_OUTPUT_PORT_TYPE +zs_ras_n <= zs_ras_n.DB_MAX_OUTPUT_PORT_TYPE +zs_we_n <= zs_we_n.DB_MAX_OUTPUT_PORT_TYPE + + +|de0_nano_system|system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module +clk => entry_0[0].CLK +clk => entry_0[1].CLK +clk => entry_0[2].CLK +clk => entry_0[3].CLK +clk => entry_0[4].CLK +clk => entry_0[5].CLK +clk => entry_0[6].CLK +clk => entry_0[7].CLK +clk => entry_0[8].CLK +clk => entry_0[9].CLK +clk => entry_0[10].CLK +clk => entry_0[11].CLK +clk => entry_0[12].CLK +clk => entry_0[13].CLK +clk => entry_0[14].CLK +clk => entry_0[15].CLK +clk => entry_0[16].CLK +clk => entry_0[17].CLK +clk => entry_0[18].CLK +clk => entry_0[19].CLK +clk => entry_0[20].CLK +clk => entry_0[21].CLK +clk => entry_0[22].CLK +clk => entry_0[23].CLK +clk => entry_0[24].CLK +clk => entry_0[25].CLK +clk => entry_0[26].CLK +clk => entry_0[27].CLK +clk => entry_0[28].CLK +clk => entry_0[29].CLK +clk => entry_0[30].CLK +clk => entry_0[31].CLK +clk => entry_0[32].CLK +clk => entry_0[33].CLK +clk => entry_0[34].CLK +clk => entry_0[35].CLK +clk => entry_0[36].CLK +clk => entry_0[37].CLK +clk => entry_0[38].CLK +clk => entry_0[39].CLK +clk => entry_0[40].CLK +clk => entry_0[41].CLK +clk => entry_1[0].CLK +clk => entry_1[1].CLK +clk => entry_1[2].CLK +clk => entry_1[3].CLK +clk => entry_1[4].CLK +clk => entry_1[5].CLK +clk => entry_1[6].CLK +clk => entry_1[7].CLK +clk => entry_1[8].CLK +clk => entry_1[9].CLK +clk => entry_1[10].CLK +clk => entry_1[11].CLK +clk => entry_1[12].CLK +clk => entry_1[13].CLK +clk => entry_1[14].CLK +clk => entry_1[15].CLK +clk => entry_1[16].CLK +clk => entry_1[17].CLK +clk => entry_1[18].CLK +clk => entry_1[19].CLK +clk => entry_1[20].CLK +clk => entry_1[21].CLK +clk => entry_1[22].CLK +clk => entry_1[23].CLK +clk => entry_1[24].CLK +clk => entry_1[25].CLK +clk => entry_1[26].CLK +clk => entry_1[27].CLK +clk => entry_1[28].CLK +clk => entry_1[29].CLK +clk => entry_1[30].CLK +clk => entry_1[31].CLK +clk => entry_1[32].CLK +clk => entry_1[33].CLK +clk => entry_1[34].CLK +clk => entry_1[35].CLK +clk => entry_1[36].CLK +clk => entry_1[37].CLK +clk => entry_1[38].CLK +clk => entry_1[39].CLK +clk => entry_1[40].CLK +clk => entry_1[41].CLK +clk => entries[0].CLK +clk => entries[1].CLK +clk => rd_address.CLK +clk => wr_address.CLK +rd => Mux0.IN2 +rd => Mux1.IN4 +rd => Mux2.IN4 +rd => Mux3.IN4 +reset_n => entries[0].ACLR +reset_n => entries[1].ACLR +reset_n => rd_address.ACLR +reset_n => wr_address.ACLR +wr => Mux0.IN3 +wr => Mux1.IN5 +wr => Mux2.IN5 +wr => Mux3.IN5 +wr => always2.IN1 +wr_data[0] => entry_1.DATAB +wr_data[0] => entry_0.DATAA +wr_data[1] => entry_1.DATAB +wr_data[1] => entry_0.DATAA +wr_data[2] => entry_1.DATAB +wr_data[2] => entry_0.DATAA +wr_data[3] => entry_1.DATAB +wr_data[3] => entry_0.DATAA +wr_data[4] => entry_1.DATAB +wr_data[4] => entry_0.DATAA +wr_data[5] => entry_1.DATAB +wr_data[5] => entry_0.DATAA +wr_data[6] => entry_1.DATAB +wr_data[6] => entry_0.DATAA +wr_data[7] => entry_1.DATAB +wr_data[7] => entry_0.DATAA +wr_data[8] => entry_1.DATAB +wr_data[8] => entry_0.DATAA +wr_data[9] => entry_1.DATAB +wr_data[9] => entry_0.DATAA +wr_data[10] => entry_1.DATAB +wr_data[10] => entry_0.DATAA +wr_data[11] => entry_1.DATAB +wr_data[11] => entry_0.DATAA +wr_data[12] => entry_1.DATAB +wr_data[12] => entry_0.DATAA +wr_data[13] => entry_1.DATAB +wr_data[13] => entry_0.DATAA +wr_data[14] => entry_1.DATAB +wr_data[14] => entry_0.DATAA +wr_data[15] => entry_1.DATAB +wr_data[15] => entry_0.DATAA +wr_data[16] => entry_1.DATAB +wr_data[16] => entry_0.DATAA +wr_data[17] => entry_1.DATAB +wr_data[17] => entry_0.DATAA +wr_data[18] => entry_1.DATAB +wr_data[18] => entry_0.DATAA +wr_data[19] => entry_1.DATAB +wr_data[19] => entry_0.DATAA +wr_data[20] => entry_1.DATAB +wr_data[20] => entry_0.DATAA +wr_data[21] => entry_1.DATAB +wr_data[21] => entry_0.DATAA +wr_data[22] => entry_1.DATAB +wr_data[22] => entry_0.DATAA +wr_data[23] => entry_1.DATAB +wr_data[23] => entry_0.DATAA +wr_data[24] => entry_1.DATAB +wr_data[24] => entry_0.DATAA +wr_data[25] => entry_1.DATAB +wr_data[25] => entry_0.DATAA +wr_data[26] => entry_1.DATAB +wr_data[26] => entry_0.DATAA +wr_data[27] => entry_1.DATAB +wr_data[27] => entry_0.DATAA +wr_data[28] => entry_1.DATAB +wr_data[28] => entry_0.DATAA +wr_data[29] => entry_1.DATAB +wr_data[29] => entry_0.DATAA +wr_data[30] => entry_1.DATAB +wr_data[30] => entry_0.DATAA +wr_data[31] => entry_1.DATAB +wr_data[31] => entry_0.DATAA +wr_data[32] => entry_1.DATAB +wr_data[32] => entry_0.DATAA +wr_data[33] => entry_1.DATAB +wr_data[33] => entry_0.DATAA +wr_data[34] => entry_1.DATAB +wr_data[34] => entry_0.DATAA +wr_data[35] => entry_1.DATAB +wr_data[35] => entry_0.DATAA +wr_data[36] => entry_1.DATAB +wr_data[36] => entry_0.DATAA +wr_data[37] => entry_1.DATAB +wr_data[37] => entry_0.DATAA +wr_data[38] => entry_1.DATAB +wr_data[38] => entry_0.DATAA +wr_data[39] => entry_1.DATAB +wr_data[39] => entry_0.DATAA +wr_data[40] => entry_1.DATAB +wr_data[40] => entry_0.DATAA +wr_data[41] => entry_1.DATAB +wr_data[41] => entry_0.DATAA +almost_empty <= LessThan1.DB_MAX_OUTPUT_PORT_TYPE +almost_full <= LessThan0.DB_MAX_OUTPUT_PORT_TYPE +empty <= Equal1.DB_MAX_OUTPUT_PORT_TYPE +full <= Equal0.DB_MAX_OUTPUT_PORT_TYPE +rd_data[0] <= rd_data.DB_MAX_OUTPUT_PORT_TYPE +rd_data[1] <= rd_data.DB_MAX_OUTPUT_PORT_TYPE +rd_data[2] <= rd_data.DB_MAX_OUTPUT_PORT_TYPE +rd_data[3] <= rd_data.DB_MAX_OUTPUT_PORT_TYPE +rd_data[4] <= rd_data.DB_MAX_OUTPUT_PORT_TYPE +rd_data[5] <= rd_data.DB_MAX_OUTPUT_PORT_TYPE +rd_data[6] <= rd_data.DB_MAX_OUTPUT_PORT_TYPE +rd_data[7] <= rd_data.DB_MAX_OUTPUT_PORT_TYPE +rd_data[8] <= rd_data.DB_MAX_OUTPUT_PORT_TYPE +rd_data[9] <= rd_data.DB_MAX_OUTPUT_PORT_TYPE +rd_data[10] <= rd_data.DB_MAX_OUTPUT_PORT_TYPE +rd_data[11] <= rd_data.DB_MAX_OUTPUT_PORT_TYPE +rd_data[12] <= rd_data.DB_MAX_OUTPUT_PORT_TYPE +rd_data[13] <= rd_data.DB_MAX_OUTPUT_PORT_TYPE +rd_data[14] <= rd_data.DB_MAX_OUTPUT_PORT_TYPE +rd_data[15] <= rd_data.DB_MAX_OUTPUT_PORT_TYPE +rd_data[16] <= rd_data.DB_MAX_OUTPUT_PORT_TYPE +rd_data[17] <= rd_data.DB_MAX_OUTPUT_PORT_TYPE +rd_data[18] <= rd_data.DB_MAX_OUTPUT_PORT_TYPE +rd_data[19] <= rd_data.DB_MAX_OUTPUT_PORT_TYPE +rd_data[20] <= rd_data.DB_MAX_OUTPUT_PORT_TYPE +rd_data[21] <= rd_data.DB_MAX_OUTPUT_PORT_TYPE +rd_data[22] <= rd_data.DB_MAX_OUTPUT_PORT_TYPE +rd_data[23] <= rd_data.DB_MAX_OUTPUT_PORT_TYPE +rd_data[24] <= rd_data.DB_MAX_OUTPUT_PORT_TYPE +rd_data[25] <= rd_data.DB_MAX_OUTPUT_PORT_TYPE +rd_data[26] <= rd_data.DB_MAX_OUTPUT_PORT_TYPE +rd_data[27] <= rd_data.DB_MAX_OUTPUT_PORT_TYPE +rd_data[28] <= rd_data.DB_MAX_OUTPUT_PORT_TYPE +rd_data[29] <= rd_data.DB_MAX_OUTPUT_PORT_TYPE +rd_data[30] <= rd_data.DB_MAX_OUTPUT_PORT_TYPE +rd_data[31] <= rd_data.DB_MAX_OUTPUT_PORT_TYPE +rd_data[32] <= rd_data.DB_MAX_OUTPUT_PORT_TYPE +rd_data[33] <= rd_data.DB_MAX_OUTPUT_PORT_TYPE +rd_data[34] <= rd_data.DB_MAX_OUTPUT_PORT_TYPE +rd_data[35] <= rd_data.DB_MAX_OUTPUT_PORT_TYPE +rd_data[36] <= rd_data.DB_MAX_OUTPUT_PORT_TYPE +rd_data[37] <= rd_data.DB_MAX_OUTPUT_PORT_TYPE +rd_data[38] <= rd_data.DB_MAX_OUTPUT_PORT_TYPE +rd_data[39] <= rd_data.DB_MAX_OUTPUT_PORT_TYPE +rd_data[40] <= rd_data.DB_MAX_OUTPUT_PORT_TYPE +rd_data[41] <= rd_data.DB_MAX_OUTPUT_PORT_TYPE + + +|de0_nano_system|system:inst_cpu|system_sys_clk_timer:sys_clk_timer +address[0] => Equal1.IN30 +address[0] => Equal2.IN60 +address[0] => Equal3.IN30 +address[0] => Equal4.IN60 +address[0] => Equal5.IN60 +address[0] => Equal6.IN31 +address[1] => Equal1.IN60 +address[1] => Equal2.IN59 +address[1] => Equal3.IN29 +address[1] => Equal4.IN29 +address[1] => Equal5.IN30 +address[1] => Equal6.IN30 +address[2] => Equal1.IN29 +address[2] => Equal2.IN29 +address[2] => Equal3.IN60 +address[2] => Equal4.IN59 +address[2] => Equal5.IN29 +address[2] => Equal6.IN29 +chipselect => period_l_wr_strobe.IN0 +clk => control_register[0].CLK +clk => control_register[1].CLK +clk => control_register[2].CLK +clk => control_register[3].CLK +clk => counter_snapshot[0].CLK +clk => counter_snapshot[1].CLK +clk => counter_snapshot[2].CLK +clk => counter_snapshot[3].CLK +clk => counter_snapshot[4].CLK +clk => counter_snapshot[5].CLK +clk => counter_snapshot[6].CLK +clk => counter_snapshot[7].CLK +clk => counter_snapshot[8].CLK +clk => counter_snapshot[9].CLK +clk => counter_snapshot[10].CLK +clk => counter_snapshot[11].CLK +clk => counter_snapshot[12].CLK +clk => counter_snapshot[13].CLK +clk => counter_snapshot[14].CLK +clk => counter_snapshot[15].CLK +clk => counter_snapshot[16].CLK +clk => counter_snapshot[17].CLK +clk => counter_snapshot[18].CLK +clk => counter_snapshot[19].CLK +clk => counter_snapshot[20].CLK +clk => counter_snapshot[21].CLK +clk => counter_snapshot[22].CLK +clk => counter_snapshot[23].CLK +clk => counter_snapshot[24].CLK +clk => counter_snapshot[25].CLK +clk => counter_snapshot[26].CLK +clk => counter_snapshot[27].CLK +clk => counter_snapshot[28].CLK +clk => counter_snapshot[29].CLK +clk => counter_snapshot[30].CLK +clk => counter_snapshot[31].CLK +clk => period_h_register[0].CLK +clk => period_h_register[1].CLK +clk => period_h_register[2].CLK +clk => period_h_register[3].CLK +clk => period_h_register[4].CLK +clk => period_h_register[5].CLK +clk => period_h_register[6].CLK +clk => period_h_register[7].CLK +clk => period_h_register[8].CLK +clk => period_h_register[9].CLK +clk => period_h_register[10].CLK +clk => period_h_register[11].CLK +clk => period_h_register[12].CLK +clk => period_h_register[13].CLK +clk => period_h_register[14].CLK +clk => period_h_register[15].CLK +clk => period_l_register[0].CLK +clk => period_l_register[1].CLK +clk => period_l_register[2].CLK +clk => period_l_register[3].CLK +clk => period_l_register[4].CLK +clk => period_l_register[5].CLK +clk => period_l_register[6].CLK +clk => period_l_register[7].CLK +clk => period_l_register[8].CLK +clk => period_l_register[9].CLK +clk => period_l_register[10].CLK +clk => period_l_register[11].CLK +clk => period_l_register[12].CLK +clk => period_l_register[13].CLK +clk => period_l_register[14].CLK +clk => period_l_register[15].CLK +clk => readdata[0]~reg0.CLK +clk => readdata[1]~reg0.CLK +clk => readdata[2]~reg0.CLK +clk => readdata[3]~reg0.CLK +clk => readdata[4]~reg0.CLK +clk => readdata[5]~reg0.CLK +clk => readdata[6]~reg0.CLK +clk => readdata[7]~reg0.CLK +clk => readdata[8]~reg0.CLK +clk => readdata[9]~reg0.CLK +clk => readdata[10]~reg0.CLK +clk => readdata[11]~reg0.CLK +clk => readdata[12]~reg0.CLK +clk => readdata[13]~reg0.CLK +clk => readdata[14]~reg0.CLK +clk => readdata[15]~reg0.CLK +clk => timeout_occurred.CLK +clk => delayed_unxcounter_is_zeroxx0.CLK +clk => counter_is_running.CLK +clk => force_reload.CLK +clk => internal_counter[0].CLK +clk => internal_counter[1].CLK +clk => internal_counter[2].CLK +clk => internal_counter[3].CLK +clk => internal_counter[4].CLK +clk => internal_counter[5].CLK +clk => internal_counter[6].CLK +clk => internal_counter[7].CLK +clk => internal_counter[8].CLK +clk => internal_counter[9].CLK +clk => internal_counter[10].CLK +clk => internal_counter[11].CLK +clk => internal_counter[12].CLK +clk => internal_counter[13].CLK +clk => internal_counter[14].CLK +clk => internal_counter[15].CLK +clk => internal_counter[16].CLK +clk => internal_counter[17].CLK +clk => internal_counter[18].CLK +clk => internal_counter[19].CLK +clk => internal_counter[20].CLK +clk => internal_counter[21].CLK +clk => internal_counter[22].CLK +clk => internal_counter[23].CLK +clk => internal_counter[24].CLK +clk => internal_counter[25].CLK +clk => internal_counter[26].CLK +clk => internal_counter[27].CLK +clk => internal_counter[28].CLK +clk => internal_counter[29].CLK +clk => internal_counter[30].CLK +clk => internal_counter[31].CLK +reset_n => internal_counter[0].PRESET +reset_n => internal_counter[1].PRESET +reset_n => internal_counter[2].PRESET +reset_n => internal_counter[3].PRESET +reset_n => internal_counter[4].PRESET +reset_n => internal_counter[5].ACLR +reset_n => internal_counter[6].ACLR +reset_n => internal_counter[7].PRESET +reset_n => internal_counter[8].ACLR +reset_n => internal_counter[9].PRESET +reset_n => internal_counter[10].PRESET +reset_n => internal_counter[11].ACLR +reset_n => internal_counter[12].ACLR +reset_n => internal_counter[13].ACLR +reset_n => internal_counter[14].ACLR +reset_n => internal_counter[15].PRESET +reset_n => internal_counter[16].PRESET +reset_n => internal_counter[17].ACLR +reset_n => internal_counter[18].ACLR +reset_n => internal_counter[19].ACLR +reset_n => internal_counter[20].ACLR +reset_n => internal_counter[21].ACLR +reset_n => internal_counter[22].ACLR +reset_n => internal_counter[23].ACLR +reset_n => internal_counter[24].ACLR +reset_n => internal_counter[25].ACLR +reset_n => internal_counter[26].ACLR +reset_n => internal_counter[27].ACLR +reset_n => internal_counter[28].ACLR +reset_n => internal_counter[29].ACLR +reset_n => internal_counter[30].ACLR +reset_n => internal_counter[31].ACLR +reset_n => readdata[0]~reg0.ACLR +reset_n => readdata[1]~reg0.ACLR +reset_n => readdata[2]~reg0.ACLR +reset_n => readdata[3]~reg0.ACLR +reset_n => readdata[4]~reg0.ACLR +reset_n => readdata[5]~reg0.ACLR +reset_n => readdata[6]~reg0.ACLR +reset_n => readdata[7]~reg0.ACLR +reset_n => readdata[8]~reg0.ACLR +reset_n => readdata[9]~reg0.ACLR +reset_n => readdata[10]~reg0.ACLR +reset_n => readdata[11]~reg0.ACLR +reset_n => readdata[12]~reg0.ACLR +reset_n => readdata[13]~reg0.ACLR +reset_n => readdata[14]~reg0.ACLR +reset_n => readdata[15]~reg0.ACLR +reset_n => force_reload.ACLR +reset_n => counter_is_running.ACLR +reset_n => delayed_unxcounter_is_zeroxx0.ACLR +reset_n => timeout_occurred.ACLR +reset_n => period_l_register[0].PRESET +reset_n => period_l_register[1].PRESET +reset_n => period_l_register[2].PRESET +reset_n => period_l_register[3].PRESET +reset_n => period_l_register[4].PRESET +reset_n => period_l_register[5].ACLR +reset_n => period_l_register[6].ACLR +reset_n => period_l_register[7].PRESET +reset_n => period_l_register[8].ACLR +reset_n => period_l_register[9].PRESET +reset_n => period_l_register[10].PRESET +reset_n => period_l_register[11].ACLR +reset_n => period_l_register[12].ACLR +reset_n => period_l_register[13].ACLR +reset_n => period_l_register[14].ACLR +reset_n => period_l_register[15].PRESET +reset_n => period_h_register[0].PRESET +reset_n => period_h_register[1].ACLR +reset_n => period_h_register[2].ACLR +reset_n => period_h_register[3].ACLR +reset_n => period_h_register[4].ACLR +reset_n => period_h_register[5].ACLR +reset_n => period_h_register[6].ACLR +reset_n => period_h_register[7].ACLR +reset_n => period_h_register[8].ACLR +reset_n => period_h_register[9].ACLR +reset_n => period_h_register[10].ACLR +reset_n => period_h_register[11].ACLR +reset_n => period_h_register[12].ACLR +reset_n => period_h_register[13].ACLR +reset_n => period_h_register[14].ACLR +reset_n => period_h_register[15].ACLR +reset_n => control_register[0].ACLR +reset_n => control_register[1].ACLR +reset_n => control_register[2].ACLR +reset_n => control_register[3].ACLR +reset_n => counter_snapshot[0].ACLR +reset_n => counter_snapshot[1].ACLR +reset_n => counter_snapshot[2].ACLR +reset_n => counter_snapshot[3].ACLR +reset_n => counter_snapshot[4].ACLR +reset_n => counter_snapshot[5].ACLR +reset_n => counter_snapshot[6].ACLR +reset_n => counter_snapshot[7].ACLR +reset_n => counter_snapshot[8].ACLR +reset_n => counter_snapshot[9].ACLR +reset_n => counter_snapshot[10].ACLR +reset_n => counter_snapshot[11].ACLR +reset_n => counter_snapshot[12].ACLR +reset_n => counter_snapshot[13].ACLR +reset_n => counter_snapshot[14].ACLR +reset_n => counter_snapshot[15].ACLR +reset_n => counter_snapshot[16].ACLR +reset_n => counter_snapshot[17].ACLR +reset_n => counter_snapshot[18].ACLR +reset_n => counter_snapshot[19].ACLR +reset_n => counter_snapshot[20].ACLR +reset_n => counter_snapshot[21].ACLR +reset_n => counter_snapshot[22].ACLR +reset_n => counter_snapshot[23].ACLR +reset_n => counter_snapshot[24].ACLR +reset_n => counter_snapshot[25].ACLR +reset_n => counter_snapshot[26].ACLR +reset_n => counter_snapshot[27].ACLR +reset_n => counter_snapshot[28].ACLR +reset_n => counter_snapshot[29].ACLR +reset_n => counter_snapshot[30].ACLR +reset_n => counter_snapshot[31].ACLR +write_n => period_l_wr_strobe.IN1 +writedata[0] => period_l_register[0].DATAIN +writedata[0] => control_register[0].DATAIN +writedata[0] => period_h_register[0].DATAIN +writedata[1] => period_l_register[1].DATAIN +writedata[1] => period_h_register[1].DATAIN +writedata[1] => control_register[1].DATAIN +writedata[2] => start_strobe.IN1 +writedata[2] => period_l_register[2].DATAIN +writedata[2] => period_h_register[2].DATAIN +writedata[2] => control_register[2].DATAIN +writedata[3] => stop_strobe.IN1 +writedata[3] => period_l_register[3].DATAIN +writedata[3] => period_h_register[3].DATAIN +writedata[3] => control_register[3].DATAIN +writedata[4] => period_l_register[4].DATAIN +writedata[4] => period_h_register[4].DATAIN +writedata[5] => period_l_register[5].DATAIN +writedata[5] => period_h_register[5].DATAIN +writedata[6] => period_l_register[6].DATAIN +writedata[6] => period_h_register[6].DATAIN +writedata[7] => period_l_register[7].DATAIN +writedata[7] => period_h_register[7].DATAIN +writedata[8] => period_l_register[8].DATAIN +writedata[8] => period_h_register[8].DATAIN +writedata[9] => period_l_register[9].DATAIN +writedata[9] => period_h_register[9].DATAIN +writedata[10] => period_l_register[10].DATAIN +writedata[10] => period_h_register[10].DATAIN +writedata[11] => period_l_register[11].DATAIN +writedata[11] => period_h_register[11].DATAIN +writedata[12] => period_l_register[12].DATAIN +writedata[12] => period_h_register[12].DATAIN +writedata[13] => period_l_register[13].DATAIN +writedata[13] => period_h_register[13].DATAIN +writedata[14] => period_l_register[14].DATAIN +writedata[14] => period_h_register[14].DATAIN +writedata[15] => period_l_register[15].DATAIN +writedata[15] => period_h_register[15].DATAIN +irq <= irq.DB_MAX_OUTPUT_PORT_TYPE +readdata[0] <= readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[1] <= readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[2] <= readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[3] <= readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[4] <= readdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[5] <= readdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[6] <= readdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[7] <= readdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[8] <= readdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[9] <= readdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[10] <= readdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[11] <= readdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[12] <= readdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[13] <= readdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[14] <= readdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[15] <= readdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE + + +|de0_nano_system|system:inst_cpu|system_uart_0:uart_0 +address[0] => address[0].IN1 +address[1] => address[1].IN1 +address[2] => address[2].IN1 +begintransfer => begintransfer.IN2 +chipselect => chipselect.IN1 +clk => clk.IN3 +read_n => read_n.IN1 +reset_n => reset_n.IN3 +rxd => rxd.IN1 +write_n => write_n.IN1 +writedata[0] => writedata[0].IN1 +writedata[1] => writedata[1].IN1 +writedata[2] => writedata[2].IN1 +writedata[3] => writedata[3].IN1 +writedata[4] => writedata[4].IN1 +writedata[5] => writedata[5].IN1 +writedata[6] => writedata[6].IN1 +writedata[7] => writedata[7].IN1 +writedata[8] => writedata[8].IN1 +writedata[9] => writedata[9].IN1 +writedata[10] => writedata[10].IN1 +writedata[11] => writedata[11].IN1 +writedata[12] => writedata[12].IN1 +writedata[13] => writedata[13].IN1 +writedata[14] => writedata[14].IN1 +writedata[15] => writedata[15].IN1 +dataavailable <= system_uart_0_regs:the_system_uart_0_regs.dataavailable +irq <= system_uart_0_regs:the_system_uart_0_regs.irq +readdata[0] <= system_uart_0_regs:the_system_uart_0_regs.readdata +readdata[1] <= system_uart_0_regs:the_system_uart_0_regs.readdata +readdata[2] <= system_uart_0_regs:the_system_uart_0_regs.readdata +readdata[3] <= system_uart_0_regs:the_system_uart_0_regs.readdata +readdata[4] <= system_uart_0_regs:the_system_uart_0_regs.readdata +readdata[5] <= system_uart_0_regs:the_system_uart_0_regs.readdata +readdata[6] <= system_uart_0_regs:the_system_uart_0_regs.readdata +readdata[7] <= system_uart_0_regs:the_system_uart_0_regs.readdata +readdata[8] <= system_uart_0_regs:the_system_uart_0_regs.readdata +readdata[9] <= system_uart_0_regs:the_system_uart_0_regs.readdata +readdata[10] <= system_uart_0_regs:the_system_uart_0_regs.readdata +readdata[11] <= system_uart_0_regs:the_system_uart_0_regs.readdata +readdata[12] <= system_uart_0_regs:the_system_uart_0_regs.readdata +readdata[13] <= system_uart_0_regs:the_system_uart_0_regs.readdata +readdata[14] <= system_uart_0_regs:the_system_uart_0_regs.readdata +readdata[15] <= system_uart_0_regs:the_system_uart_0_regs.readdata +readyfordata <= system_uart_0_regs:the_system_uart_0_regs.readyfordata +txd <= system_uart_0_tx:the_system_uart_0_tx.txd + + +|de0_nano_system|system:inst_cpu|system_uart_0:uart_0|system_uart_0_tx:the_system_uart_0_tx +baud_divisor[0] => baud_rate_counter.DATAB +baud_divisor[1] => baud_rate_counter.DATAB +baud_divisor[2] => baud_rate_counter.DATAB +baud_divisor[3] => baud_rate_counter.DATAB +baud_divisor[4] => baud_rate_counter.DATAB +baud_divisor[5] => baud_rate_counter.DATAB +baud_divisor[6] => baud_rate_counter.DATAB +baud_divisor[7] => baud_rate_counter.DATAB +baud_divisor[8] => baud_rate_counter.DATAB +baud_divisor[9] => baud_rate_counter.DATAB +baud_divisor[10] => baud_rate_counter.DATAB +baud_divisor[11] => baud_rate_counter.DATAB +baud_divisor[12] => baud_rate_counter.DATAB +baud_divisor[13] => baud_rate_counter.DATAB +baud_divisor[14] => baud_rate_counter.DATAB +baud_divisor[15] => baud_rate_counter.DATAB +begintransfer => tx_wr_strobe_onset.IN0 +clk => unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[0].CLK +clk => unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[1].CLK +clk => unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[2].CLK +clk => unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[3].CLK +clk => unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[4].CLK +clk => unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[5].CLK +clk => unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[6].CLK +clk => unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[7].CLK +clk => unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[8].CLK +clk => unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[9].CLK +clk => txd~reg0.CLK +clk => pre_txd.CLK +clk => baud_clk_en.CLK +clk => baud_rate_counter[0].CLK +clk => baud_rate_counter[1].CLK +clk => baud_rate_counter[2].CLK +clk => baud_rate_counter[3].CLK +clk => baud_rate_counter[4].CLK +clk => baud_rate_counter[5].CLK +clk => baud_rate_counter[6].CLK +clk => baud_rate_counter[7].CLK +clk => baud_rate_counter[8].CLK +clk => baud_rate_counter[9].CLK +clk => baud_rate_counter[10].CLK +clk => baud_rate_counter[11].CLK +clk => baud_rate_counter[12].CLK +clk => baud_rate_counter[13].CLK +clk => baud_rate_counter[14].CLK +clk => baud_rate_counter[15].CLK +clk => tx_shift_empty~reg0.CLK +clk => tx_overrun~reg0.CLK +clk => tx_ready~reg0.CLK +clk => do_load_shifter.CLK +clk_en => do_load_shifter.ENA +clk_en => tx_ready~reg0.ENA +clk_en => tx_overrun~reg0.ENA +clk_en => tx_shift_empty~reg0.ENA +clk_en => baud_rate_counter[15].ENA +clk_en => baud_rate_counter[14].ENA +clk_en => baud_rate_counter[13].ENA +clk_en => baud_rate_counter[12].ENA +clk_en => baud_rate_counter[11].ENA +clk_en => baud_rate_counter[10].ENA +clk_en => baud_rate_counter[9].ENA +clk_en => baud_rate_counter[8].ENA +clk_en => baud_rate_counter[7].ENA +clk_en => baud_rate_counter[6].ENA +clk_en => baud_rate_counter[5].ENA +clk_en => baud_rate_counter[4].ENA +clk_en => baud_rate_counter[3].ENA +clk_en => baud_rate_counter[2].ENA +clk_en => baud_rate_counter[1].ENA +clk_en => baud_rate_counter[0].ENA +clk_en => unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[0].ENA +clk_en => baud_clk_en.ENA +clk_en => txd~reg0.ENA +clk_en => unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[9].ENA +clk_en => unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[8].ENA +clk_en => unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[7].ENA +clk_en => unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[6].ENA +clk_en => unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[5].ENA +clk_en => unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[4].ENA +clk_en => unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[3].ENA +clk_en => unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[2].ENA +clk_en => unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[1].ENA +do_force_break => txd.IN1 +reset_n => baud_rate_counter[0].ACLR +reset_n => baud_rate_counter[1].ACLR +reset_n => baud_rate_counter[2].ACLR +reset_n => baud_rate_counter[3].ACLR +reset_n => baud_rate_counter[4].ACLR +reset_n => baud_rate_counter[5].ACLR +reset_n => baud_rate_counter[6].ACLR +reset_n => baud_rate_counter[7].ACLR +reset_n => baud_rate_counter[8].ACLR +reset_n => baud_rate_counter[9].ACLR +reset_n => baud_rate_counter[10].ACLR +reset_n => baud_rate_counter[11].ACLR +reset_n => baud_rate_counter[12].ACLR +reset_n => baud_rate_counter[13].ACLR +reset_n => baud_rate_counter[14].ACLR +reset_n => baud_rate_counter[15].ACLR +reset_n => tx_overrun~reg0.ACLR +reset_n => tx_ready~reg0.PRESET +reset_n => tx_shift_empty~reg0.PRESET +reset_n => txd~reg0.PRESET +reset_n => do_load_shifter.ACLR +reset_n => unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[0].ACLR +reset_n => unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[1].ACLR +reset_n => unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[2].ACLR +reset_n => unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[3].ACLR +reset_n => unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[4].ACLR +reset_n => unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[5].ACLR +reset_n => unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[6].ACLR +reset_n => unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[7].ACLR +reset_n => unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[8].ACLR +reset_n => unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[9].ACLR +reset_n => baud_clk_en.ACLR +reset_n => pre_txd.PRESET +status_wr_strobe => tx_overrun.OUTPUTSELECT +tx_data[0] => unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_in[1].DATAB +tx_data[1] => unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_in[2].DATAB +tx_data[2] => unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_in[3].DATAB +tx_data[3] => unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_in[4].DATAB +tx_data[4] => unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_in[5].DATAB +tx_data[5] => unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_in[6].DATAB +tx_data[6] => unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_in[7].DATAB +tx_data[7] => unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_in[8].DATAB +tx_wr_strobe => tx_wr_strobe_onset.IN1 +tx_overrun <= tx_overrun~reg0.DB_MAX_OUTPUT_PORT_TYPE +tx_ready <= tx_ready~reg0.DB_MAX_OUTPUT_PORT_TYPE +tx_shift_empty <= tx_shift_empty~reg0.DB_MAX_OUTPUT_PORT_TYPE +txd <= txd~reg0.DB_MAX_OUTPUT_PORT_TYPE + + +|de0_nano_system|system:inst_cpu|system_uart_0:uart_0|system_uart_0_rx:the_system_uart_0_rx +baud_divisor[0] => baud_divisor[0].IN1 +baud_divisor[1] => baud_divisor[1].IN1 +baud_divisor[2] => baud_divisor[2].IN1 +baud_divisor[3] => baud_divisor[3].IN1 +baud_divisor[4] => baud_divisor[4].IN1 +baud_divisor[5] => baud_divisor[5].IN1 +baud_divisor[6] => baud_divisor[6].IN1 +baud_divisor[7] => baud_divisor[7].IN1 +baud_divisor[8] => baud_divisor[8].IN1 +baud_divisor[9] => baud_divisor[9].IN1 +baud_divisor[10] => baud_divisor[10].IN1 +baud_divisor[11] => baud_divisor[11].IN1 +baud_divisor[12] => baud_divisor[12].IN1 +baud_divisor[13] => baud_divisor[13].IN1 +baud_divisor[14] => baud_divisor[14].IN1 +baud_divisor[15] => baud_divisor[15].IN1 +begintransfer => rx_rd_strobe_onset.IN0 +clk => clk.IN2 +clk_en => clk_en.IN1 +reset_n => reset_n.IN2 +rx_rd_strobe => rx_rd_strobe_onset.IN1 +rxd => rxd.IN1 +status_wr_strobe => framing_error.OUTPUTSELECT +status_wr_strobe => break_detect.OUTPUTSELECT +status_wr_strobe => rx_overrun.OUTPUTSELECT +break_detect <= break_detect~reg0.DB_MAX_OUTPUT_PORT_TYPE +framing_error <= framing_error~reg0.DB_MAX_OUTPUT_PORT_TYPE +parity_error <= +rx_char_ready <= rx_char_ready.DB_MAX_OUTPUT_PORT_TYPE +rx_data[0] <= rx_data[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +rx_data[1] <= rx_data[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +rx_data[2] <= rx_data[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +rx_data[3] <= rx_data[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +rx_data[4] <= rx_data[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +rx_data[5] <= rx_data[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +rx_data[6] <= rx_data[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +rx_data[7] <= rx_data[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE +rx_overrun <= rx_overrun~reg0.DB_MAX_OUTPUT_PORT_TYPE + + +|de0_nano_system|system:inst_cpu|system_uart_0:uart_0|system_uart_0_rx:the_system_uart_0_rx|system_uart_0_rx_stimulus_source:the_system_uart_0_rx_stimulus_source +baud_divisor[0] => ~NO_FANOUT~ +baud_divisor[1] => ~NO_FANOUT~ +baud_divisor[2] => ~NO_FANOUT~ +baud_divisor[3] => ~NO_FANOUT~ +baud_divisor[4] => ~NO_FANOUT~ +baud_divisor[5] => ~NO_FANOUT~ +baud_divisor[6] => ~NO_FANOUT~ +baud_divisor[7] => ~NO_FANOUT~ +baud_divisor[8] => ~NO_FANOUT~ +baud_divisor[9] => ~NO_FANOUT~ +baud_divisor[10] => ~NO_FANOUT~ +baud_divisor[11] => ~NO_FANOUT~ +baud_divisor[12] => ~NO_FANOUT~ +baud_divisor[13] => ~NO_FANOUT~ +baud_divisor[14] => ~NO_FANOUT~ +baud_divisor[15] => ~NO_FANOUT~ +clk => ~NO_FANOUT~ +clk_en => ~NO_FANOUT~ +reset_n => ~NO_FANOUT~ +rx_char_ready => ~NO_FANOUT~ +rxd => source_rxd.DATAIN +source_rxd <= rxd.DB_MAX_OUTPUT_PORT_TYPE + + +|de0_nano_system|system:inst_cpu|system_uart_0:uart_0|system_uart_0_rx:the_system_uart_0_rx|altera_std_synchronizer:the_altera_std_synchronizer +clk => dreg[0].CLK +clk => din_s1.CLK +reset_n => dreg[0].ACLR +reset_n => din_s1.ACLR +din => din_s1.DATAIN +dout <= dout.DB_MAX_OUTPUT_PORT_TYPE + + +|de0_nano_system|system:inst_cpu|system_uart_0:uart_0|system_uart_0_regs:the_system_uart_0_regs +address[0] => Equal0.IN2 +address[0] => Equal1.IN1 +address[0] => Equal2.IN2 +address[0] => Equal3.IN2 +address[0] => Equal4.IN1 +address[1] => Equal0.IN1 +address[1] => Equal1.IN0 +address[1] => Equal2.IN1 +address[1] => Equal3.IN1 +address[1] => Equal4.IN2 +address[2] => Equal0.IN0 +address[2] => Equal1.IN2 +address[2] => Equal2.IN0 +address[2] => Equal3.IN0 +address[2] => Equal4.IN0 +break_detect => status_reg[8].IN1 +break_detect => qualified_irq.IN1 +break_detect => selected_read_data.IN1 +chipselect => rx_rd_strobe.IN0 +chipselect => divisor_wr_strobe.IN0 +clk => d1_tx_ready.CLK +clk => d1_rx_char_ready.CLK +clk => baud_divisor[0]~reg0.CLK +clk => baud_divisor[1]~reg0.CLK +clk => baud_divisor[2]~reg0.CLK +clk => baud_divisor[3]~reg0.CLK +clk => baud_divisor[4]~reg0.CLK +clk => baud_divisor[5]~reg0.CLK +clk => baud_divisor[6]~reg0.CLK +clk => baud_divisor[7]~reg0.CLK +clk => baud_divisor[8]~reg0.CLK +clk => baud_divisor[9]~reg0.CLK +clk => baud_divisor[10]~reg0.CLK +clk => baud_divisor[11]~reg0.CLK +clk => baud_divisor[12]~reg0.CLK +clk => baud_divisor[13]~reg0.CLK +clk => baud_divisor[14]~reg0.CLK +clk => baud_divisor[15]~reg0.CLK +clk => control_reg[0].CLK +clk => control_reg[1].CLK +clk => control_reg[2].CLK +clk => control_reg[3].CLK +clk => control_reg[4].CLK +clk => control_reg[5].CLK +clk => control_reg[6].CLK +clk => control_reg[7].CLK +clk => control_reg[8].CLK +clk => control_reg[9].CLK +clk => tx_data[0]~reg0.CLK +clk => tx_data[1]~reg0.CLK +clk => tx_data[2]~reg0.CLK +clk => tx_data[3]~reg0.CLK +clk => tx_data[4]~reg0.CLK +clk => tx_data[5]~reg0.CLK +clk => tx_data[6]~reg0.CLK +clk => tx_data[7]~reg0.CLK +clk => irq~reg0.CLK +clk => readdata[0]~reg0.CLK +clk => readdata[1]~reg0.CLK +clk => readdata[2]~reg0.CLK +clk => readdata[3]~reg0.CLK +clk => readdata[4]~reg0.CLK +clk => readdata[5]~reg0.CLK +clk => readdata[6]~reg0.CLK +clk => readdata[7]~reg0.CLK +clk => readdata[8]~reg0.CLK +clk => readdata[9]~reg0.CLK +clk => readdata[10]~reg0.CLK +clk => readdata[11]~reg0.CLK +clk => readdata[12]~reg0.CLK +clk => readdata[13]~reg0.CLK +clk => readdata[14]~reg0.CLK +clk => readdata[15]~reg0.CLK +clk_en => readdata[15]~reg0.ENA +clk_en => readdata[14]~reg0.ENA +clk_en => readdata[13]~reg0.ENA +clk_en => readdata[12]~reg0.ENA +clk_en => readdata[11]~reg0.ENA +clk_en => readdata[10]~reg0.ENA +clk_en => readdata[9]~reg0.ENA +clk_en => readdata[8]~reg0.ENA +clk_en => readdata[7]~reg0.ENA +clk_en => readdata[6]~reg0.ENA +clk_en => readdata[5]~reg0.ENA +clk_en => readdata[4]~reg0.ENA +clk_en => readdata[3]~reg0.ENA +clk_en => readdata[2]~reg0.ENA +clk_en => readdata[1]~reg0.ENA +clk_en => readdata[0]~reg0.ENA +clk_en => irq~reg0.ENA +clk_en => d1_rx_char_ready.ENA +clk_en => d1_tx_ready.ENA +framing_error => any_error.IN1 +framing_error => qualified_irq.IN1 +framing_error => selected_read_data.IN1 +parity_error => any_error.IN1 +parity_error => qualified_irq.IN1 +parity_error => selected_read_data.IN1 +read_n => rx_rd_strobe.IN1 +reset_n => baud_divisor[0]~reg0.ALOAD +reset_n => baud_divisor[1]~reg0.ALOAD +reset_n => baud_divisor[2]~reg0.ALOAD +reset_n => baud_divisor[3]~reg0.ALOAD +reset_n => baud_divisor[4]~reg0.ALOAD +reset_n => baud_divisor[5]~reg0.ALOAD +reset_n => baud_divisor[6]~reg0.ALOAD +reset_n => baud_divisor[7]~reg0.ALOAD +reset_n => baud_divisor[8]~reg0.ALOAD +reset_n => baud_divisor[9]~reg0.ALOAD +reset_n => baud_divisor[10]~reg0.ALOAD +reset_n => baud_divisor[11]~reg0.ALOAD +reset_n => baud_divisor[12]~reg0.ALOAD +reset_n => baud_divisor[13]~reg0.ALOAD +reset_n => baud_divisor[14]~reg0.ALOAD +reset_n => baud_divisor[15]~reg0.ALOAD +reset_n => d1_rx_char_ready.ACLR +reset_n => control_reg[0].ACLR +reset_n => control_reg[1].ACLR +reset_n => control_reg[2].ACLR +reset_n => control_reg[3].ACLR +reset_n => control_reg[4].ACLR +reset_n => control_reg[5].ACLR +reset_n => control_reg[6].ACLR +reset_n => control_reg[7].ACLR +reset_n => control_reg[8].ACLR +reset_n => control_reg[9].ACLR +reset_n => irq~reg0.ACLR +reset_n => readdata[0]~reg0.ACLR +reset_n => readdata[1]~reg0.ACLR +reset_n => readdata[2]~reg0.ACLR +reset_n => readdata[3]~reg0.ACLR +reset_n => readdata[4]~reg0.ACLR +reset_n => readdata[5]~reg0.ACLR +reset_n => readdata[6]~reg0.ACLR +reset_n => readdata[7]~reg0.ACLR +reset_n => readdata[8]~reg0.ACLR +reset_n => readdata[9]~reg0.ACLR +reset_n => readdata[10]~reg0.ACLR +reset_n => readdata[11]~reg0.ACLR +reset_n => readdata[12]~reg0.ACLR +reset_n => readdata[13]~reg0.ACLR +reset_n => readdata[14]~reg0.ACLR +reset_n => readdata[15]~reg0.ACLR +reset_n => d1_tx_ready.ACLR +reset_n => tx_data[0]~reg0.ACLR +reset_n => tx_data[1]~reg0.ACLR +reset_n => tx_data[2]~reg0.ACLR +reset_n => tx_data[3]~reg0.ACLR +reset_n => tx_data[4]~reg0.ACLR +reset_n => tx_data[5]~reg0.ACLR +reset_n => tx_data[6]~reg0.ACLR +reset_n => tx_data[7]~reg0.ACLR +rx_char_ready => qualified_irq.IN1 +rx_char_ready => selected_read_data.IN1 +rx_char_ready => d1_rx_char_ready.DATAIN +rx_data[0] => selected_read_data.IN1 +rx_data[1] => selected_read_data.IN1 +rx_data[2] => selected_read_data.IN1 +rx_data[3] => selected_read_data.IN1 +rx_data[4] => selected_read_data.IN1 +rx_data[5] => selected_read_data.IN1 +rx_data[6] => selected_read_data.IN1 +rx_data[7] => selected_read_data.IN1 +rx_overrun => any_error.IN0 +rx_overrun => qualified_irq.IN1 +rx_overrun => selected_read_data.IN1 +tx_overrun => any_error.IN1 +tx_overrun => qualified_irq.IN1 +tx_overrun => selected_read_data.IN1 +tx_ready => qualified_irq.IN1 +tx_ready => selected_read_data.IN1 +tx_ready => d1_tx_ready.DATAIN +tx_shift_empty => selected_read_data.IN1 +tx_shift_empty => qualified_irq.IN1 +write_n => divisor_wr_strobe.IN1 +writedata[0] => tx_data[0]~reg0.DATAIN +writedata[0] => control_reg[0].DATAIN +writedata[0] => baud_divisor[0]~reg0.DATAIN +writedata[1] => tx_data[1]~reg0.DATAIN +writedata[1] => control_reg[1].DATAIN +writedata[1] => baud_divisor[1]~reg0.DATAIN +writedata[2] => tx_data[2]~reg0.DATAIN +writedata[2] => control_reg[2].DATAIN +writedata[2] => baud_divisor[2]~reg0.DATAIN +writedata[3] => tx_data[3]~reg0.DATAIN +writedata[3] => control_reg[3].DATAIN +writedata[3] => baud_divisor[3]~reg0.DATAIN +writedata[4] => tx_data[4]~reg0.DATAIN +writedata[4] => control_reg[4].DATAIN +writedata[4] => baud_divisor[4]~reg0.DATAIN +writedata[5] => tx_data[5]~reg0.DATAIN +writedata[5] => control_reg[5].DATAIN +writedata[5] => baud_divisor[5]~reg0.DATAIN +writedata[6] => tx_data[6]~reg0.DATAIN +writedata[6] => control_reg[6].DATAIN +writedata[6] => baud_divisor[6]~reg0.DATAIN +writedata[7] => tx_data[7]~reg0.DATAIN +writedata[7] => control_reg[7].DATAIN +writedata[7] => baud_divisor[7]~reg0.DATAIN +writedata[8] => control_reg[8].DATAIN +writedata[8] => baud_divisor[8]~reg0.DATAIN +writedata[9] => control_reg[9].DATAIN +writedata[9] => baud_divisor[9]~reg0.DATAIN +writedata[10] => baud_divisor[10]~reg0.DATAIN +writedata[11] => baud_divisor[11]~reg0.DATAIN +writedata[12] => baud_divisor[12]~reg0.DATAIN +writedata[13] => baud_divisor[13]~reg0.DATAIN +writedata[14] => baud_divisor[14]~reg0.DATAIN +writedata[15] => baud_divisor[15]~reg0.DATAIN +baud_divisor[0] <= baud_divisor[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +baud_divisor[1] <= baud_divisor[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +baud_divisor[2] <= baud_divisor[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +baud_divisor[3] <= baud_divisor[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +baud_divisor[4] <= baud_divisor[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +baud_divisor[5] <= baud_divisor[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +baud_divisor[6] <= baud_divisor[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +baud_divisor[7] <= baud_divisor[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE +baud_divisor[8] <= baud_divisor[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE +baud_divisor[9] <= baud_divisor[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE +baud_divisor[10] <= baud_divisor[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE +baud_divisor[11] <= baud_divisor[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE +baud_divisor[12] <= baud_divisor[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE +baud_divisor[13] <= baud_divisor[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE +baud_divisor[14] <= baud_divisor[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE +baud_divisor[15] <= baud_divisor[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE +dataavailable <= d1_rx_char_ready.DB_MAX_OUTPUT_PORT_TYPE +do_force_break <= control_reg[9].DB_MAX_OUTPUT_PORT_TYPE +irq <= irq~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[0] <= readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[1] <= readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[2] <= readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[3] <= readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[4] <= readdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[5] <= readdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[6] <= readdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[7] <= readdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[8] <= readdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[9] <= readdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[10] <= readdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[11] <= readdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[12] <= readdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[13] <= readdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[14] <= readdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[15] <= readdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readyfordata <= d1_tx_ready.DB_MAX_OUTPUT_PORT_TYPE +rx_rd_strobe <= rx_rd_strobe.DB_MAX_OUTPUT_PORT_TYPE +status_wr_strobe <= status_wr_strobe.DB_MAX_OUTPUT_PORT_TYPE +tx_data[0] <= tx_data[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +tx_data[1] <= tx_data[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +tx_data[2] <= tx_data[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +tx_data[3] <= tx_data[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +tx_data[4] <= tx_data[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +tx_data[5] <= tx_data[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +tx_data[6] <= tx_data[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +tx_data[7] <= tx_data[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE +tx_wr_strobe <= tx_wr_strobe.DB_MAX_OUTPUT_PORT_TYPE + + +|de0_nano_system|system:inst_cpu|system_pio_led:pio_led +address[0] => Equal0.IN60 +address[0] => Equal1.IN30 +address[0] => Equal2.IN31 +address[1] => Equal0.IN29 +address[1] => Equal1.IN29 +address[1] => Equal2.IN30 +address[2] => Equal0.IN59 +address[2] => Equal1.IN60 +address[2] => Equal2.IN29 +chipselect => wr_strobe.IN0 +clk => data_out[0].CLK +clk => data_out[1].CLK +clk => data_out[2].CLK +clk => data_out[3].CLK +clk => data_out[4].CLK +clk => data_out[5].CLK +clk => data_out[6].CLK +reset_n => data_out[0].ACLR +reset_n => data_out[1].ACLR +reset_n => data_out[2].ACLR +reset_n => data_out[3].ACLR +reset_n => data_out[4].ACLR +reset_n => data_out[5].ACLR +reset_n => data_out[6].ACLR +write_n => wr_strobe.IN1 +writedata[0] => data_out.IN1 +writedata[0] => data_out.DATAB +writedata[0] => data_out.IN1 +writedata[1] => data_out.IN1 +writedata[1] => data_out.DATAB +writedata[1] => data_out.IN1 +writedata[2] => data_out.IN1 +writedata[2] => data_out.DATAB +writedata[2] => data_out.IN1 +writedata[3] => data_out.IN1 +writedata[3] => data_out.DATAB +writedata[3] => data_out.IN1 +writedata[4] => data_out.IN1 +writedata[4] => data_out.DATAB +writedata[4] => data_out.IN1 +writedata[5] => data_out.IN1 +writedata[5] => data_out.DATAB +writedata[5] => data_out.IN1 +writedata[6] => data_out.IN1 +writedata[6] => data_out.DATAB +writedata[6] => data_out.IN1 +writedata[7] => ~NO_FANOUT~ +writedata[8] => ~NO_FANOUT~ +writedata[9] => ~NO_FANOUT~ +writedata[10] => ~NO_FANOUT~ +writedata[11] => ~NO_FANOUT~ +writedata[12] => ~NO_FANOUT~ +writedata[13] => ~NO_FANOUT~ +writedata[14] => ~NO_FANOUT~ +writedata[15] => ~NO_FANOUT~ +writedata[16] => ~NO_FANOUT~ +writedata[17] => ~NO_FANOUT~ +writedata[18] => ~NO_FANOUT~ +writedata[19] => ~NO_FANOUT~ +writedata[20] => ~NO_FANOUT~ +writedata[21] => ~NO_FANOUT~ +writedata[22] => ~NO_FANOUT~ +writedata[23] => ~NO_FANOUT~ +writedata[24] => ~NO_FANOUT~ +writedata[25] => ~NO_FANOUT~ +writedata[26] => ~NO_FANOUT~ +writedata[27] => ~NO_FANOUT~ +writedata[28] => ~NO_FANOUT~ +writedata[29] => ~NO_FANOUT~ +writedata[30] => ~NO_FANOUT~ +writedata[31] => ~NO_FANOUT~ +out_port[0] <= data_out[0].DB_MAX_OUTPUT_PORT_TYPE +out_port[1] <= data_out[1].DB_MAX_OUTPUT_PORT_TYPE +out_port[2] <= data_out[2].DB_MAX_OUTPUT_PORT_TYPE +out_port[3] <= data_out[3].DB_MAX_OUTPUT_PORT_TYPE +out_port[4] <= data_out[4].DB_MAX_OUTPUT_PORT_TYPE +out_port[5] <= data_out[5].DB_MAX_OUTPUT_PORT_TYPE +out_port[6] <= data_out[6].DB_MAX_OUTPUT_PORT_TYPE +readdata[0] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[1] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[2] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[3] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[4] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[5] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[6] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[7] <= +readdata[8] <= +readdata[9] <= +readdata[10] <= +readdata[11] <= +readdata[12] <= +readdata[13] <= +readdata[14] <= +readdata[15] <= +readdata[16] <= +readdata[17] <= +readdata[18] <= +readdata[19] <= +readdata[20] <= +readdata[21] <= +readdata[22] <= +readdata[23] <= +readdata[24] <= +readdata[25] <= +readdata[26] <= +readdata[27] <= +readdata[28] <= +readdata[29] <= +readdata[30] <= +readdata[31] <= + + +|de0_nano_system|system:inst_cpu|system_pio_key:pio_key +address[0] => Equal0.IN31 +address[1] => Equal0.IN30 +clk => readdata[0]~reg0.CLK +clk => readdata[1]~reg0.CLK +clk => readdata[2]~reg0.CLK +clk => readdata[3]~reg0.CLK +clk => readdata[4]~reg0.CLK +clk => readdata[5]~reg0.CLK +clk => readdata[6]~reg0.CLK +clk => readdata[7]~reg0.CLK +clk => readdata[8]~reg0.CLK +clk => readdata[9]~reg0.CLK +clk => readdata[10]~reg0.CLK +clk => readdata[11]~reg0.CLK +clk => readdata[12]~reg0.CLK +clk => readdata[13]~reg0.CLK +clk => readdata[14]~reg0.CLK +clk => readdata[15]~reg0.CLK +clk => readdata[16]~reg0.CLK +clk => readdata[17]~reg0.CLK +clk => readdata[18]~reg0.CLK +clk => readdata[19]~reg0.CLK +clk => readdata[20]~reg0.CLK +clk => readdata[21]~reg0.CLK +clk => readdata[22]~reg0.CLK +clk => readdata[23]~reg0.CLK +clk => readdata[24]~reg0.CLK +clk => readdata[25]~reg0.CLK +clk => readdata[26]~reg0.CLK +clk => readdata[27]~reg0.CLK +clk => readdata[28]~reg0.CLK +clk => readdata[29]~reg0.CLK +clk => readdata[30]~reg0.CLK +clk => readdata[31]~reg0.CLK +in_port[0] => read_mux_out[0].IN1 +in_port[1] => read_mux_out[1].IN1 +reset_n => readdata[0]~reg0.ACLR +reset_n => readdata[1]~reg0.ACLR +reset_n => readdata[2]~reg0.ACLR +reset_n => readdata[3]~reg0.ACLR +reset_n => readdata[4]~reg0.ACLR +reset_n => readdata[5]~reg0.ACLR +reset_n => readdata[6]~reg0.ACLR +reset_n => readdata[7]~reg0.ACLR +reset_n => readdata[8]~reg0.ACLR +reset_n => readdata[9]~reg0.ACLR +reset_n => readdata[10]~reg0.ACLR +reset_n => readdata[11]~reg0.ACLR +reset_n => readdata[12]~reg0.ACLR +reset_n => readdata[13]~reg0.ACLR +reset_n => readdata[14]~reg0.ACLR +reset_n => readdata[15]~reg0.ACLR +reset_n => readdata[16]~reg0.ACLR +reset_n => readdata[17]~reg0.ACLR +reset_n => readdata[18]~reg0.ACLR +reset_n => readdata[19]~reg0.ACLR +reset_n => readdata[20]~reg0.ACLR +reset_n => readdata[21]~reg0.ACLR +reset_n => readdata[22]~reg0.ACLR +reset_n => readdata[23]~reg0.ACLR +reset_n => readdata[24]~reg0.ACLR +reset_n => readdata[25]~reg0.ACLR +reset_n => readdata[26]~reg0.ACLR +reset_n => readdata[27]~reg0.ACLR +reset_n => readdata[28]~reg0.ACLR +reset_n => readdata[29]~reg0.ACLR +reset_n => readdata[30]~reg0.ACLR +reset_n => readdata[31]~reg0.ACLR +readdata[0] <= readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[1] <= readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[2] <= readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[3] <= readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[4] <= readdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[5] <= readdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[6] <= readdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[7] <= readdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[8] <= readdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[9] <= readdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[10] <= readdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[11] <= readdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[12] <= readdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[13] <= readdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[14] <= readdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[15] <= readdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[16] <= readdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[17] <= readdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[18] <= readdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[19] <= readdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[20] <= readdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[21] <= readdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[22] <= readdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[23] <= readdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[24] <= readdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[25] <= readdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[26] <= readdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[27] <= readdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[28] <= readdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[29] <= readdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[30] <= readdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[31] <= readdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE + + +|de0_nano_system|system:inst_cpu|system_pio_sw:pio_sw +address[0] => Equal0.IN31 +address[1] => Equal0.IN30 +clk => readdata[0]~reg0.CLK +clk => readdata[1]~reg0.CLK +clk => readdata[2]~reg0.CLK +clk => readdata[3]~reg0.CLK +clk => readdata[4]~reg0.CLK +clk => readdata[5]~reg0.CLK +clk => readdata[6]~reg0.CLK +clk => readdata[7]~reg0.CLK +clk => readdata[8]~reg0.CLK +clk => readdata[9]~reg0.CLK +clk => readdata[10]~reg0.CLK +clk => readdata[11]~reg0.CLK +clk => readdata[12]~reg0.CLK +clk => readdata[13]~reg0.CLK +clk => readdata[14]~reg0.CLK +clk => readdata[15]~reg0.CLK +clk => readdata[16]~reg0.CLK +clk => readdata[17]~reg0.CLK +clk => readdata[18]~reg0.CLK +clk => readdata[19]~reg0.CLK +clk => readdata[20]~reg0.CLK +clk => readdata[21]~reg0.CLK +clk => readdata[22]~reg0.CLK +clk => readdata[23]~reg0.CLK +clk => readdata[24]~reg0.CLK +clk => readdata[25]~reg0.CLK +clk => readdata[26]~reg0.CLK +clk => readdata[27]~reg0.CLK +clk => readdata[28]~reg0.CLK +clk => readdata[29]~reg0.CLK +clk => readdata[30]~reg0.CLK +clk => readdata[31]~reg0.CLK +in_port[0] => read_mux_out[0].IN1 +in_port[1] => read_mux_out[1].IN1 +in_port[2] => read_mux_out[2].IN1 +in_port[3] => read_mux_out[3].IN1 +reset_n => readdata[0]~reg0.ACLR +reset_n => readdata[1]~reg0.ACLR +reset_n => readdata[2]~reg0.ACLR +reset_n => readdata[3]~reg0.ACLR +reset_n => readdata[4]~reg0.ACLR +reset_n => readdata[5]~reg0.ACLR +reset_n => readdata[6]~reg0.ACLR +reset_n => readdata[7]~reg0.ACLR +reset_n => readdata[8]~reg0.ACLR +reset_n => readdata[9]~reg0.ACLR +reset_n => readdata[10]~reg0.ACLR +reset_n => readdata[11]~reg0.ACLR +reset_n => readdata[12]~reg0.ACLR +reset_n => readdata[13]~reg0.ACLR +reset_n => readdata[14]~reg0.ACLR +reset_n => readdata[15]~reg0.ACLR +reset_n => readdata[16]~reg0.ACLR +reset_n => readdata[17]~reg0.ACLR +reset_n => readdata[18]~reg0.ACLR +reset_n => readdata[19]~reg0.ACLR +reset_n => readdata[20]~reg0.ACLR +reset_n => readdata[21]~reg0.ACLR +reset_n => readdata[22]~reg0.ACLR +reset_n => readdata[23]~reg0.ACLR +reset_n => readdata[24]~reg0.ACLR +reset_n => readdata[25]~reg0.ACLR +reset_n => readdata[26]~reg0.ACLR +reset_n => readdata[27]~reg0.ACLR +reset_n => readdata[28]~reg0.ACLR +reset_n => readdata[29]~reg0.ACLR +reset_n => readdata[30]~reg0.ACLR +reset_n => readdata[31]~reg0.ACLR +readdata[0] <= readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[1] <= readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[2] <= readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[3] <= readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[4] <= readdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[5] <= readdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[6] <= readdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[7] <= readdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[8] <= readdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[9] <= readdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[10] <= readdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[11] <= readdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[12] <= readdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[13] <= readdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[14] <= readdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[15] <= readdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[16] <= readdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[17] <= readdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[18] <= readdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[19] <= readdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[20] <= readdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[21] <= readdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[22] <= readdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[23] <= readdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[24] <= readdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[25] <= readdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[26] <= readdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[27] <= readdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[28] <= readdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[29] <= readdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[30] <= readdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[31] <= readdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE + + +|de0_nano_system|system:inst_cpu|system_jtag_uart_0:jtag_uart_0 +av_address => ien_AF.OUTPUTSELECT +av_address => ien_AE.OUTPUTSELECT +av_address => ac.OUTPUTSELECT +av_address => fifo_wr.OUTPUTSELECT +av_address => woverflow.OUTPUTSELECT +av_address => rvalid.OUTPUTSELECT +av_address => read_0.DATAB +av_address => fifo_rd.IN1 +av_chipselect => av_waitrequest.IN1 +av_chipselect => always2.IN0 +av_chipselect => always2.IN0 +av_chipselect => fifo_rd.IN0 +av_read_n => always2.IN1 +av_read_n => av_waitrequest.IN0 +av_read_n => fifo_rd.IN1 +av_write_n => always2.IN1 +av_write_n => av_waitrequest.IN1 +av_writedata[0] => fifo_wdata[0].IN1 +av_writedata[1] => fifo_wdata[1].IN1 +av_writedata[2] => fifo_wdata[2].IN1 +av_writedata[3] => fifo_wdata[3].IN1 +av_writedata[4] => fifo_wdata[4].IN1 +av_writedata[5] => fifo_wdata[5].IN1 +av_writedata[6] => fifo_wdata[6].IN1 +av_writedata[7] => fifo_wdata[7].IN1 +av_writedata[8] => ~NO_FANOUT~ +av_writedata[9] => ~NO_FANOUT~ +av_writedata[10] => always2.IN1 +av_writedata[11] => ~NO_FANOUT~ +av_writedata[12] => ~NO_FANOUT~ +av_writedata[13] => ~NO_FANOUT~ +av_writedata[14] => ~NO_FANOUT~ +av_writedata[15] => ~NO_FANOUT~ +av_writedata[16] => ~NO_FANOUT~ +av_writedata[17] => ~NO_FANOUT~ +av_writedata[18] => ~NO_FANOUT~ +av_writedata[19] => ~NO_FANOUT~ +av_writedata[20] => ~NO_FANOUT~ +av_writedata[21] => ~NO_FANOUT~ +av_writedata[22] => ~NO_FANOUT~ +av_writedata[23] => ~NO_FANOUT~ +av_writedata[24] => ~NO_FANOUT~ +av_writedata[25] => ~NO_FANOUT~ +av_writedata[26] => ~NO_FANOUT~ +av_writedata[27] => ~NO_FANOUT~ +av_writedata[28] => ~NO_FANOUT~ +av_writedata[29] => ~NO_FANOUT~ +av_writedata[30] => ~NO_FANOUT~ +av_writedata[31] => ~NO_FANOUT~ +clk => clk.IN3 +rst_n => rst_n.IN2 +av_irq <= av_irq.DB_MAX_OUTPUT_PORT_TYPE +av_readdata[0] <= av_readdata.DB_MAX_OUTPUT_PORT_TYPE +av_readdata[1] <= av_readdata.DB_MAX_OUTPUT_PORT_TYPE +av_readdata[2] <= av_readdata.DB_MAX_OUTPUT_PORT_TYPE +av_readdata[3] <= av_readdata.DB_MAX_OUTPUT_PORT_TYPE +av_readdata[4] <= av_readdata.DB_MAX_OUTPUT_PORT_TYPE +av_readdata[5] <= av_readdata.DB_MAX_OUTPUT_PORT_TYPE +av_readdata[6] <= av_readdata.DB_MAX_OUTPUT_PORT_TYPE +av_readdata[7] <= av_readdata.DB_MAX_OUTPUT_PORT_TYPE +av_readdata[8] <= ipen_AF.DB_MAX_OUTPUT_PORT_TYPE +av_readdata[9] <= ipen_AE.DB_MAX_OUTPUT_PORT_TYPE +av_readdata[10] <= ac.DB_MAX_OUTPUT_PORT_TYPE +av_readdata[11] <= +av_readdata[12] <= system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r.fifo_EF +av_readdata[13] <= system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w.fifo_FF +av_readdata[14] <= woverflow.DB_MAX_OUTPUT_PORT_TYPE +av_readdata[15] <= rvalid.DB_MAX_OUTPUT_PORT_TYPE +av_readdata[16] <= av_readdata.DB_MAX_OUTPUT_PORT_TYPE +av_readdata[17] <= av_readdata.DB_MAX_OUTPUT_PORT_TYPE +av_readdata[18] <= av_readdata.DB_MAX_OUTPUT_PORT_TYPE +av_readdata[19] <= av_readdata.DB_MAX_OUTPUT_PORT_TYPE +av_readdata[20] <= av_readdata.DB_MAX_OUTPUT_PORT_TYPE +av_readdata[21] <= av_readdata.DB_MAX_OUTPUT_PORT_TYPE +av_readdata[22] <= av_readdata.DB_MAX_OUTPUT_PORT_TYPE +av_readdata[23] <= +av_readdata[24] <= +av_readdata[25] <= +av_readdata[26] <= +av_readdata[27] <= +av_readdata[28] <= +av_readdata[29] <= +av_readdata[30] <= +av_readdata[31] <= +av_waitrequest <= av_waitrequest~reg0.DB_MAX_OUTPUT_PORT_TYPE +dataavailable <= dataavailable~reg0.DB_MAX_OUTPUT_PORT_TYPE +readyfordata <= readyfordata~reg0.DB_MAX_OUTPUT_PORT_TYPE + + +|de0_nano_system|system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w +clk => clk.IN1 +fifo_clear => fifo_clear.IN1 +fifo_wdata[0] => fifo_wdata[0].IN1 +fifo_wdata[1] => fifo_wdata[1].IN1 +fifo_wdata[2] => fifo_wdata[2].IN1 +fifo_wdata[3] => fifo_wdata[3].IN1 +fifo_wdata[4] => fifo_wdata[4].IN1 +fifo_wdata[5] => fifo_wdata[5].IN1 +fifo_wdata[6] => fifo_wdata[6].IN1 +fifo_wdata[7] => fifo_wdata[7].IN1 +fifo_wr => fifo_wr.IN1 +rd_wfifo => rd_wfifo.IN1 +fifo_FF <= scfifo:wfifo.full +r_dat[0] <= scfifo:wfifo.q +r_dat[1] <= scfifo:wfifo.q +r_dat[2] <= scfifo:wfifo.q +r_dat[3] <= scfifo:wfifo.q +r_dat[4] <= scfifo:wfifo.q +r_dat[5] <= scfifo:wfifo.q +r_dat[6] <= scfifo:wfifo.q +r_dat[7] <= scfifo:wfifo.q +wfifo_empty <= scfifo:wfifo.empty +wfifo_used[0] <= scfifo:wfifo.usedw +wfifo_used[1] <= scfifo:wfifo.usedw +wfifo_used[2] <= scfifo:wfifo.usedw +wfifo_used[3] <= scfifo:wfifo.usedw +wfifo_used[4] <= scfifo:wfifo.usedw +wfifo_used[5] <= scfifo:wfifo.usedw + + +|de0_nano_system|system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo +data[0] => scfifo_jr21:auto_generated.data[0] +data[1] => scfifo_jr21:auto_generated.data[1] +data[2] => scfifo_jr21:auto_generated.data[2] +data[3] => scfifo_jr21:auto_generated.data[3] +data[4] => scfifo_jr21:auto_generated.data[4] +data[5] => scfifo_jr21:auto_generated.data[5] +data[6] => scfifo_jr21:auto_generated.data[6] +data[7] => scfifo_jr21:auto_generated.data[7] +q[0] <= scfifo_jr21:auto_generated.q[0] +q[1] <= scfifo_jr21:auto_generated.q[1] +q[2] <= scfifo_jr21:auto_generated.q[2] +q[3] <= scfifo_jr21:auto_generated.q[3] +q[4] <= scfifo_jr21:auto_generated.q[4] +q[5] <= scfifo_jr21:auto_generated.q[5] +q[6] <= scfifo_jr21:auto_generated.q[6] +q[7] <= scfifo_jr21:auto_generated.q[7] +wrreq => scfifo_jr21:auto_generated.wrreq +rdreq => scfifo_jr21:auto_generated.rdreq +clock => scfifo_jr21:auto_generated.clock +aclr => scfifo_jr21:auto_generated.aclr +sclr => ~NO_FANOUT~ +empty <= scfifo_jr21:auto_generated.empty +full <= scfifo_jr21:auto_generated.full +almost_full <= +almost_empty <= +usedw[0] <= scfifo_jr21:auto_generated.usedw[0] +usedw[1] <= scfifo_jr21:auto_generated.usedw[1] +usedw[2] <= scfifo_jr21:auto_generated.usedw[2] +usedw[3] <= scfifo_jr21:auto_generated.usedw[3] +usedw[4] <= scfifo_jr21:auto_generated.usedw[4] +usedw[5] <= scfifo_jr21:auto_generated.usedw[5] + + +|de0_nano_system|system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated +aclr => a_dpfifo_q131:dpfifo.aclr +clock => a_dpfifo_q131:dpfifo.clock +data[0] => a_dpfifo_q131:dpfifo.data[0] +data[1] => a_dpfifo_q131:dpfifo.data[1] +data[2] => a_dpfifo_q131:dpfifo.data[2] +data[3] => a_dpfifo_q131:dpfifo.data[3] +data[4] => a_dpfifo_q131:dpfifo.data[4] +data[5] => a_dpfifo_q131:dpfifo.data[5] +data[6] => a_dpfifo_q131:dpfifo.data[6] +data[7] => a_dpfifo_q131:dpfifo.data[7] +empty <= a_dpfifo_q131:dpfifo.empty +full <= a_dpfifo_q131:dpfifo.full +q[0] <= a_dpfifo_q131:dpfifo.q[0] +q[1] <= a_dpfifo_q131:dpfifo.q[1] +q[2] <= a_dpfifo_q131:dpfifo.q[2] +q[3] <= a_dpfifo_q131:dpfifo.q[3] +q[4] <= a_dpfifo_q131:dpfifo.q[4] +q[5] <= a_dpfifo_q131:dpfifo.q[5] +q[6] <= a_dpfifo_q131:dpfifo.q[6] +q[7] <= a_dpfifo_q131:dpfifo.q[7] +rdreq => a_dpfifo_q131:dpfifo.rreq +usedw[0] <= a_dpfifo_q131:dpfifo.usedw[0] +usedw[1] <= a_dpfifo_q131:dpfifo.usedw[1] +usedw[2] <= a_dpfifo_q131:dpfifo.usedw[2] +usedw[3] <= a_dpfifo_q131:dpfifo.usedw[3] +usedw[4] <= a_dpfifo_q131:dpfifo.usedw[4] +usedw[5] <= a_dpfifo_q131:dpfifo.usedw[5] +wrreq => a_dpfifo_q131:dpfifo.wreq + + +|de0_nano_system|system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo +aclr => a_fefifo_7cf:fifo_state.aclr +aclr => cntr_1ob:rd_ptr_count.aclr +aclr => cntr_1ob:wr_ptr.aclr +clock => a_fefifo_7cf:fifo_state.clock +clock => dpram_nl21:FIFOram.inclock +clock => dpram_nl21:FIFOram.outclock +clock => cntr_1ob:rd_ptr_count.clock +clock => cntr_1ob:wr_ptr.clock +data[0] => dpram_nl21:FIFOram.data[0] +data[1] => dpram_nl21:FIFOram.data[1] +data[2] => dpram_nl21:FIFOram.data[2] +data[3] => dpram_nl21:FIFOram.data[3] +data[4] => dpram_nl21:FIFOram.data[4] +data[5] => dpram_nl21:FIFOram.data[5] +data[6] => dpram_nl21:FIFOram.data[6] +data[7] => dpram_nl21:FIFOram.data[7] +empty <= a_fefifo_7cf:fifo_state.empty +full <= a_fefifo_7cf:fifo_state.full +q[0] <= dpram_nl21:FIFOram.q[0] +q[1] <= dpram_nl21:FIFOram.q[1] +q[2] <= dpram_nl21:FIFOram.q[2] +q[3] <= dpram_nl21:FIFOram.q[3] +q[4] <= dpram_nl21:FIFOram.q[4] +q[5] <= dpram_nl21:FIFOram.q[5] +q[6] <= dpram_nl21:FIFOram.q[6] +q[7] <= dpram_nl21:FIFOram.q[7] +rreq => a_fefifo_7cf:fifo_state.rreq +rreq => _.IN0 +rreq => cntr_1ob:rd_ptr_count.cnt_en +sclr => a_fefifo_7cf:fifo_state.sclr +sclr => _.IN1 +sclr => _.IN0 +sclr => cntr_1ob:rd_ptr_count.sclr +sclr => cntr_1ob:wr_ptr.sclr +usedw[0] <= a_fefifo_7cf:fifo_state.usedw_out[0] +usedw[1] <= a_fefifo_7cf:fifo_state.usedw_out[1] +usedw[2] <= a_fefifo_7cf:fifo_state.usedw_out[2] +usedw[3] <= a_fefifo_7cf:fifo_state.usedw_out[3] +usedw[4] <= a_fefifo_7cf:fifo_state.usedw_out[4] +usedw[5] <= a_fefifo_7cf:fifo_state.usedw_out[5] +wreq => a_fefifo_7cf:fifo_state.wreq +wreq => dpram_nl21:FIFOram.wren +wreq => cntr_1ob:wr_ptr.cnt_en + + +|de0_nano_system|system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state +aclr => b_full.IN0 +aclr => b_non_empty.IN0 +aclr => cntr_do7:count_usedw.aclr +clock => cntr_do7:count_usedw.clock +clock => b_full.CLK +clock => b_non_empty.CLK +empty <= empty.DB_MAX_OUTPUT_PORT_TYPE +full <= b_full.DB_MAX_OUTPUT_PORT_TYPE +rreq => _.IN1 +rreq => _.IN0 +rreq => _.IN1 +rreq => _.IN1 +sclr => _.IN0 +sclr => _.IN0 +sclr => _.IN1 +sclr => _.IN0 +sclr => _.IN0 +sclr => cntr_do7:count_usedw.sclr +usedw_out[0] <= usedw[0].DB_MAX_OUTPUT_PORT_TYPE +usedw_out[1] <= usedw[1].DB_MAX_OUTPUT_PORT_TYPE +usedw_out[2] <= usedw[2].DB_MAX_OUTPUT_PORT_TYPE +usedw_out[3] <= usedw[3].DB_MAX_OUTPUT_PORT_TYPE +usedw_out[4] <= usedw[4].DB_MAX_OUTPUT_PORT_TYPE +usedw_out[5] <= usedw[5].DB_MAX_OUTPUT_PORT_TYPE +wreq => _.IN1 +wreq => _.IN1 +wreq => _.IN0 +wreq => _.IN0 +wreq => cntr_do7:count_usedw.updown + + +|de0_nano_system|system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw +aclr => counter_reg_bit[5].IN0 +clock => counter_reg_bit[5].CLK +clock => counter_reg_bit[4].CLK +clock => counter_reg_bit[3].CLK +clock => counter_reg_bit[2].CLK +clock => counter_reg_bit[1].CLK +clock => counter_reg_bit[0].CLK +cnt_en => _.IN1 +q[0] <= counter_reg_bit[0].DB_MAX_OUTPUT_PORT_TYPE +q[1] <= counter_reg_bit[1].DB_MAX_OUTPUT_PORT_TYPE +q[2] <= counter_reg_bit[2].DB_MAX_OUTPUT_PORT_TYPE +q[3] <= counter_reg_bit[3].DB_MAX_OUTPUT_PORT_TYPE +q[4] <= counter_reg_bit[4].DB_MAX_OUTPUT_PORT_TYPE +q[5] <= counter_reg_bit[5].DB_MAX_OUTPUT_PORT_TYPE +sclr => _.IN0 +sclr => _.IN0 +sclr => _.IN0 +updown => counter_comb_bita0.DATAB +updown => counter_comb_bita1.DATAB +updown => counter_comb_bita2.DATAB +updown => counter_comb_bita3.DATAB +updown => counter_comb_bita4.DATAB +updown => counter_comb_bita5.DATAB + + +|de0_nano_system|system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram +data[0] => altsyncram_r1m1:altsyncram1.data_a[0] +data[1] => altsyncram_r1m1:altsyncram1.data_a[1] +data[2] => altsyncram_r1m1:altsyncram1.data_a[2] +data[3] => altsyncram_r1m1:altsyncram1.data_a[3] +data[4] => altsyncram_r1m1:altsyncram1.data_a[4] +data[5] => altsyncram_r1m1:altsyncram1.data_a[5] +data[6] => altsyncram_r1m1:altsyncram1.data_a[6] +data[7] => altsyncram_r1m1:altsyncram1.data_a[7] +inclock => altsyncram_r1m1:altsyncram1.clock0 +outclock => altsyncram_r1m1:altsyncram1.clock1 +outclocken => altsyncram_r1m1:altsyncram1.clocken1 +q[0] <= altsyncram_r1m1:altsyncram1.q_b[0] +q[1] <= altsyncram_r1m1:altsyncram1.q_b[1] +q[2] <= altsyncram_r1m1:altsyncram1.q_b[2] +q[3] <= altsyncram_r1m1:altsyncram1.q_b[3] +q[4] <= altsyncram_r1m1:altsyncram1.q_b[4] +q[5] <= altsyncram_r1m1:altsyncram1.q_b[5] +q[6] <= altsyncram_r1m1:altsyncram1.q_b[6] +q[7] <= altsyncram_r1m1:altsyncram1.q_b[7] +rdaddress[0] => altsyncram_r1m1:altsyncram1.address_b[0] +rdaddress[1] => altsyncram_r1m1:altsyncram1.address_b[1] +rdaddress[2] => altsyncram_r1m1:altsyncram1.address_b[2] +rdaddress[3] => altsyncram_r1m1:altsyncram1.address_b[3] +rdaddress[4] => altsyncram_r1m1:altsyncram1.address_b[4] +rdaddress[5] => altsyncram_r1m1:altsyncram1.address_b[5] +wraddress[0] => altsyncram_r1m1:altsyncram1.address_a[0] +wraddress[1] => altsyncram_r1m1:altsyncram1.address_a[1] +wraddress[2] => altsyncram_r1m1:altsyncram1.address_a[2] +wraddress[3] => altsyncram_r1m1:altsyncram1.address_a[3] +wraddress[4] => altsyncram_r1m1:altsyncram1.address_a[4] +wraddress[5] => altsyncram_r1m1:altsyncram1.address_a[5] +wren => altsyncram_r1m1:altsyncram1.wren_a + + +|de0_nano_system|system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1 +address_a[0] => ram_block2a0.PORTAADDR +address_a[0] => ram_block2a1.PORTAADDR +address_a[0] => ram_block2a2.PORTAADDR +address_a[0] => ram_block2a3.PORTAADDR +address_a[0] => ram_block2a4.PORTAADDR +address_a[0] => ram_block2a5.PORTAADDR +address_a[0] => ram_block2a6.PORTAADDR +address_a[0] => ram_block2a7.PORTAADDR +address_a[1] => ram_block2a0.PORTAADDR1 +address_a[1] => ram_block2a1.PORTAADDR1 +address_a[1] => ram_block2a2.PORTAADDR1 +address_a[1] => ram_block2a3.PORTAADDR1 +address_a[1] => ram_block2a4.PORTAADDR1 +address_a[1] => ram_block2a5.PORTAADDR1 +address_a[1] => ram_block2a6.PORTAADDR1 +address_a[1] => ram_block2a7.PORTAADDR1 +address_a[2] => ram_block2a0.PORTAADDR2 +address_a[2] => ram_block2a1.PORTAADDR2 +address_a[2] => ram_block2a2.PORTAADDR2 +address_a[2] => ram_block2a3.PORTAADDR2 +address_a[2] => ram_block2a4.PORTAADDR2 +address_a[2] => ram_block2a5.PORTAADDR2 +address_a[2] => ram_block2a6.PORTAADDR2 +address_a[2] => ram_block2a7.PORTAADDR2 +address_a[3] => ram_block2a0.PORTAADDR3 +address_a[3] => ram_block2a1.PORTAADDR3 +address_a[3] => ram_block2a2.PORTAADDR3 +address_a[3] => ram_block2a3.PORTAADDR3 +address_a[3] => ram_block2a4.PORTAADDR3 +address_a[3] => ram_block2a5.PORTAADDR3 +address_a[3] => ram_block2a6.PORTAADDR3 +address_a[3] => ram_block2a7.PORTAADDR3 +address_a[4] => ram_block2a0.PORTAADDR4 +address_a[4] => ram_block2a1.PORTAADDR4 +address_a[4] => ram_block2a2.PORTAADDR4 +address_a[4] => ram_block2a3.PORTAADDR4 +address_a[4] => ram_block2a4.PORTAADDR4 +address_a[4] => ram_block2a5.PORTAADDR4 +address_a[4] => ram_block2a6.PORTAADDR4 +address_a[4] => ram_block2a7.PORTAADDR4 +address_a[5] => ram_block2a0.PORTAADDR5 +address_a[5] => ram_block2a1.PORTAADDR5 +address_a[5] => ram_block2a2.PORTAADDR5 +address_a[5] => ram_block2a3.PORTAADDR5 +address_a[5] => ram_block2a4.PORTAADDR5 +address_a[5] => ram_block2a5.PORTAADDR5 +address_a[5] => ram_block2a6.PORTAADDR5 +address_a[5] => ram_block2a7.PORTAADDR5 +address_b[0] => ram_block2a0.PORTBADDR +address_b[0] => ram_block2a1.PORTBADDR +address_b[0] => ram_block2a2.PORTBADDR +address_b[0] => ram_block2a3.PORTBADDR +address_b[0] => ram_block2a4.PORTBADDR +address_b[0] => ram_block2a5.PORTBADDR +address_b[0] => ram_block2a6.PORTBADDR +address_b[0] => ram_block2a7.PORTBADDR +address_b[1] => ram_block2a0.PORTBADDR1 +address_b[1] => ram_block2a1.PORTBADDR1 +address_b[1] => ram_block2a2.PORTBADDR1 +address_b[1] => ram_block2a3.PORTBADDR1 +address_b[1] => ram_block2a4.PORTBADDR1 +address_b[1] => ram_block2a5.PORTBADDR1 +address_b[1] => ram_block2a6.PORTBADDR1 +address_b[1] => ram_block2a7.PORTBADDR1 +address_b[2] => ram_block2a0.PORTBADDR2 +address_b[2] => ram_block2a1.PORTBADDR2 +address_b[2] => ram_block2a2.PORTBADDR2 +address_b[2] => ram_block2a3.PORTBADDR2 +address_b[2] => ram_block2a4.PORTBADDR2 +address_b[2] => ram_block2a5.PORTBADDR2 +address_b[2] => ram_block2a6.PORTBADDR2 +address_b[2] => ram_block2a7.PORTBADDR2 +address_b[3] => ram_block2a0.PORTBADDR3 +address_b[3] => ram_block2a1.PORTBADDR3 +address_b[3] => ram_block2a2.PORTBADDR3 +address_b[3] => ram_block2a3.PORTBADDR3 +address_b[3] => ram_block2a4.PORTBADDR3 +address_b[3] => ram_block2a5.PORTBADDR3 +address_b[3] => ram_block2a6.PORTBADDR3 +address_b[3] => ram_block2a7.PORTBADDR3 +address_b[4] => ram_block2a0.PORTBADDR4 +address_b[4] => ram_block2a1.PORTBADDR4 +address_b[4] => ram_block2a2.PORTBADDR4 +address_b[4] => ram_block2a3.PORTBADDR4 +address_b[4] => ram_block2a4.PORTBADDR4 +address_b[4] => ram_block2a5.PORTBADDR4 +address_b[4] => ram_block2a6.PORTBADDR4 +address_b[4] => ram_block2a7.PORTBADDR4 +address_b[5] => ram_block2a0.PORTBADDR5 +address_b[5] => ram_block2a1.PORTBADDR5 +address_b[5] => ram_block2a2.PORTBADDR5 +address_b[5] => ram_block2a3.PORTBADDR5 +address_b[5] => ram_block2a4.PORTBADDR5 +address_b[5] => ram_block2a5.PORTBADDR5 +address_b[5] => ram_block2a6.PORTBADDR5 +address_b[5] => ram_block2a7.PORTBADDR5 +clock0 => ram_block2a0.CLK0 +clock0 => ram_block2a1.CLK0 +clock0 => ram_block2a2.CLK0 +clock0 => ram_block2a3.CLK0 +clock0 => ram_block2a4.CLK0 +clock0 => ram_block2a5.CLK0 +clock0 => ram_block2a6.CLK0 +clock0 => ram_block2a7.CLK0 +clock1 => ram_block2a0.CLK1 +clock1 => ram_block2a1.CLK1 +clock1 => ram_block2a2.CLK1 +clock1 => ram_block2a3.CLK1 +clock1 => ram_block2a4.CLK1 +clock1 => ram_block2a5.CLK1 +clock1 => ram_block2a6.CLK1 +clock1 => ram_block2a7.CLK1 +clocken1 => ram_block2a0.ENA1 +clocken1 => ram_block2a1.ENA1 +clocken1 => ram_block2a2.ENA1 +clocken1 => ram_block2a3.ENA1 +clocken1 => ram_block2a4.ENA1 +clocken1 => ram_block2a5.ENA1 +clocken1 => ram_block2a6.ENA1 +clocken1 => ram_block2a7.ENA1 +data_a[0] => ram_block2a0.PORTADATAIN +data_a[1] => ram_block2a1.PORTADATAIN +data_a[2] => ram_block2a2.PORTADATAIN +data_a[3] => ram_block2a3.PORTADATAIN +data_a[4] => ram_block2a4.PORTADATAIN +data_a[5] => ram_block2a5.PORTADATAIN +data_a[6] => ram_block2a6.PORTADATAIN +data_a[7] => ram_block2a7.PORTADATAIN +q_b[0] <= ram_block2a0.PORTBDATAOUT +q_b[1] <= ram_block2a1.PORTBDATAOUT +q_b[2] <= ram_block2a2.PORTBDATAOUT +q_b[3] <= ram_block2a3.PORTBDATAOUT +q_b[4] <= ram_block2a4.PORTBDATAOUT +q_b[5] <= ram_block2a5.PORTBDATAOUT +q_b[6] <= ram_block2a6.PORTBDATAOUT +q_b[7] <= ram_block2a7.PORTBDATAOUT +wren_a => ram_block2a0.PORTAWE +wren_a => ram_block2a0.ENA0 +wren_a => ram_block2a1.PORTAWE +wren_a => ram_block2a1.ENA0 +wren_a => ram_block2a2.PORTAWE +wren_a => ram_block2a2.ENA0 +wren_a => ram_block2a3.PORTAWE +wren_a => ram_block2a3.ENA0 +wren_a => ram_block2a4.PORTAWE +wren_a => ram_block2a4.ENA0 +wren_a => ram_block2a5.PORTAWE +wren_a => ram_block2a5.ENA0 +wren_a => ram_block2a6.PORTAWE +wren_a => ram_block2a6.ENA0 +wren_a => ram_block2a7.PORTAWE +wren_a => ram_block2a7.ENA0 + + +|de0_nano_system|system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:rd_ptr_count +aclr => counter_reg_bit[5].IN0 +clock => counter_reg_bit[5].CLK +clock => counter_reg_bit[4].CLK +clock => counter_reg_bit[3].CLK +clock => counter_reg_bit[2].CLK +clock => counter_reg_bit[1].CLK +clock => counter_reg_bit[0].CLK +cnt_en => _.IN1 +q[0] <= counter_reg_bit[0].DB_MAX_OUTPUT_PORT_TYPE +q[1] <= counter_reg_bit[1].DB_MAX_OUTPUT_PORT_TYPE +q[2] <= counter_reg_bit[2].DB_MAX_OUTPUT_PORT_TYPE +q[3] <= counter_reg_bit[3].DB_MAX_OUTPUT_PORT_TYPE +q[4] <= counter_reg_bit[4].DB_MAX_OUTPUT_PORT_TYPE +q[5] <= counter_reg_bit[5].DB_MAX_OUTPUT_PORT_TYPE +sclr => _.IN0 +sclr => _.IN0 +sclr => _.IN0 + + +|de0_nano_system|system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr +aclr => counter_reg_bit[5].IN0 +clock => counter_reg_bit[5].CLK +clock => counter_reg_bit[4].CLK +clock => counter_reg_bit[3].CLK +clock => counter_reg_bit[2].CLK +clock => counter_reg_bit[1].CLK +clock => counter_reg_bit[0].CLK +cnt_en => _.IN1 +q[0] <= counter_reg_bit[0].DB_MAX_OUTPUT_PORT_TYPE +q[1] <= counter_reg_bit[1].DB_MAX_OUTPUT_PORT_TYPE +q[2] <= counter_reg_bit[2].DB_MAX_OUTPUT_PORT_TYPE +q[3] <= counter_reg_bit[3].DB_MAX_OUTPUT_PORT_TYPE +q[4] <= counter_reg_bit[4].DB_MAX_OUTPUT_PORT_TYPE +q[5] <= counter_reg_bit[5].DB_MAX_OUTPUT_PORT_TYPE +sclr => _.IN0 +sclr => _.IN0 +sclr => _.IN0 + + +|de0_nano_system|system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r +clk => clk.IN1 +fifo_clear => fifo_clear.IN1 +fifo_rd => fifo_rd.IN1 +rst_n => ~NO_FANOUT~ +t_dat[0] => t_dat[0].IN1 +t_dat[1] => t_dat[1].IN1 +t_dat[2] => t_dat[2].IN1 +t_dat[3] => t_dat[3].IN1 +t_dat[4] => t_dat[4].IN1 +t_dat[5] => t_dat[5].IN1 +t_dat[6] => t_dat[6].IN1 +t_dat[7] => t_dat[7].IN1 +wr_rfifo => wr_rfifo.IN1 +fifo_EF <= scfifo:rfifo.empty +fifo_rdata[0] <= scfifo:rfifo.q +fifo_rdata[1] <= scfifo:rfifo.q +fifo_rdata[2] <= scfifo:rfifo.q +fifo_rdata[3] <= scfifo:rfifo.q +fifo_rdata[4] <= scfifo:rfifo.q +fifo_rdata[5] <= scfifo:rfifo.q +fifo_rdata[6] <= scfifo:rfifo.q +fifo_rdata[7] <= scfifo:rfifo.q +rfifo_full <= scfifo:rfifo.full +rfifo_used[0] <= scfifo:rfifo.usedw +rfifo_used[1] <= scfifo:rfifo.usedw +rfifo_used[2] <= scfifo:rfifo.usedw +rfifo_used[3] <= scfifo:rfifo.usedw +rfifo_used[4] <= scfifo:rfifo.usedw +rfifo_used[5] <= scfifo:rfifo.usedw + + +|de0_nano_system|system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo +data[0] => scfifo_jr21:auto_generated.data[0] +data[1] => scfifo_jr21:auto_generated.data[1] +data[2] => scfifo_jr21:auto_generated.data[2] +data[3] => scfifo_jr21:auto_generated.data[3] +data[4] => scfifo_jr21:auto_generated.data[4] +data[5] => scfifo_jr21:auto_generated.data[5] +data[6] => scfifo_jr21:auto_generated.data[6] +data[7] => scfifo_jr21:auto_generated.data[7] +q[0] <= scfifo_jr21:auto_generated.q[0] +q[1] <= scfifo_jr21:auto_generated.q[1] +q[2] <= scfifo_jr21:auto_generated.q[2] +q[3] <= scfifo_jr21:auto_generated.q[3] +q[4] <= scfifo_jr21:auto_generated.q[4] +q[5] <= scfifo_jr21:auto_generated.q[5] +q[6] <= scfifo_jr21:auto_generated.q[6] +q[7] <= scfifo_jr21:auto_generated.q[7] +wrreq => scfifo_jr21:auto_generated.wrreq +rdreq => scfifo_jr21:auto_generated.rdreq +clock => scfifo_jr21:auto_generated.clock +aclr => scfifo_jr21:auto_generated.aclr +sclr => ~NO_FANOUT~ +empty <= scfifo_jr21:auto_generated.empty +full <= scfifo_jr21:auto_generated.full +almost_full <= +almost_empty <= +usedw[0] <= scfifo_jr21:auto_generated.usedw[0] +usedw[1] <= scfifo_jr21:auto_generated.usedw[1] +usedw[2] <= scfifo_jr21:auto_generated.usedw[2] +usedw[3] <= scfifo_jr21:auto_generated.usedw[3] +usedw[4] <= scfifo_jr21:auto_generated.usedw[4] +usedw[5] <= scfifo_jr21:auto_generated.usedw[5] + + +|de0_nano_system|system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated +aclr => a_dpfifo_q131:dpfifo.aclr +clock => a_dpfifo_q131:dpfifo.clock +data[0] => a_dpfifo_q131:dpfifo.data[0] +data[1] => a_dpfifo_q131:dpfifo.data[1] +data[2] => a_dpfifo_q131:dpfifo.data[2] +data[3] => a_dpfifo_q131:dpfifo.data[3] +data[4] => a_dpfifo_q131:dpfifo.data[4] +data[5] => a_dpfifo_q131:dpfifo.data[5] +data[6] => a_dpfifo_q131:dpfifo.data[6] +data[7] => a_dpfifo_q131:dpfifo.data[7] +empty <= a_dpfifo_q131:dpfifo.empty +full <= a_dpfifo_q131:dpfifo.full +q[0] <= a_dpfifo_q131:dpfifo.q[0] +q[1] <= a_dpfifo_q131:dpfifo.q[1] +q[2] <= a_dpfifo_q131:dpfifo.q[2] +q[3] <= a_dpfifo_q131:dpfifo.q[3] +q[4] <= a_dpfifo_q131:dpfifo.q[4] +q[5] <= a_dpfifo_q131:dpfifo.q[5] +q[6] <= a_dpfifo_q131:dpfifo.q[6] +q[7] <= a_dpfifo_q131:dpfifo.q[7] +rdreq => a_dpfifo_q131:dpfifo.rreq +usedw[0] <= a_dpfifo_q131:dpfifo.usedw[0] +usedw[1] <= a_dpfifo_q131:dpfifo.usedw[1] +usedw[2] <= a_dpfifo_q131:dpfifo.usedw[2] +usedw[3] <= a_dpfifo_q131:dpfifo.usedw[3] +usedw[4] <= a_dpfifo_q131:dpfifo.usedw[4] +usedw[5] <= a_dpfifo_q131:dpfifo.usedw[5] +wrreq => a_dpfifo_q131:dpfifo.wreq + + +|de0_nano_system|system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo +aclr => a_fefifo_7cf:fifo_state.aclr +aclr => cntr_1ob:rd_ptr_count.aclr +aclr => cntr_1ob:wr_ptr.aclr +clock => a_fefifo_7cf:fifo_state.clock +clock => dpram_nl21:FIFOram.inclock +clock => dpram_nl21:FIFOram.outclock +clock => cntr_1ob:rd_ptr_count.clock +clock => cntr_1ob:wr_ptr.clock +data[0] => dpram_nl21:FIFOram.data[0] +data[1] => dpram_nl21:FIFOram.data[1] +data[2] => dpram_nl21:FIFOram.data[2] +data[3] => dpram_nl21:FIFOram.data[3] +data[4] => dpram_nl21:FIFOram.data[4] +data[5] => dpram_nl21:FIFOram.data[5] +data[6] => dpram_nl21:FIFOram.data[6] +data[7] => dpram_nl21:FIFOram.data[7] +empty <= a_fefifo_7cf:fifo_state.empty +full <= a_fefifo_7cf:fifo_state.full +q[0] <= dpram_nl21:FIFOram.q[0] +q[1] <= dpram_nl21:FIFOram.q[1] +q[2] <= dpram_nl21:FIFOram.q[2] +q[3] <= dpram_nl21:FIFOram.q[3] +q[4] <= dpram_nl21:FIFOram.q[4] +q[5] <= dpram_nl21:FIFOram.q[5] +q[6] <= dpram_nl21:FIFOram.q[6] +q[7] <= dpram_nl21:FIFOram.q[7] +rreq => a_fefifo_7cf:fifo_state.rreq +rreq => _.IN0 +rreq => cntr_1ob:rd_ptr_count.cnt_en +sclr => a_fefifo_7cf:fifo_state.sclr +sclr => _.IN1 +sclr => _.IN0 +sclr => cntr_1ob:rd_ptr_count.sclr +sclr => cntr_1ob:wr_ptr.sclr +usedw[0] <= a_fefifo_7cf:fifo_state.usedw_out[0] +usedw[1] <= a_fefifo_7cf:fifo_state.usedw_out[1] +usedw[2] <= a_fefifo_7cf:fifo_state.usedw_out[2] +usedw[3] <= a_fefifo_7cf:fifo_state.usedw_out[3] +usedw[4] <= a_fefifo_7cf:fifo_state.usedw_out[4] +usedw[5] <= a_fefifo_7cf:fifo_state.usedw_out[5] +wreq => a_fefifo_7cf:fifo_state.wreq +wreq => dpram_nl21:FIFOram.wren +wreq => cntr_1ob:wr_ptr.cnt_en + + +|de0_nano_system|system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state +aclr => b_full.IN0 +aclr => b_non_empty.IN0 +aclr => cntr_do7:count_usedw.aclr +clock => cntr_do7:count_usedw.clock +clock => b_full.CLK +clock => b_non_empty.CLK +empty <= empty.DB_MAX_OUTPUT_PORT_TYPE +full <= b_full.DB_MAX_OUTPUT_PORT_TYPE +rreq => _.IN1 +rreq => _.IN0 +rreq => _.IN1 +rreq => _.IN1 +sclr => _.IN0 +sclr => _.IN0 +sclr => _.IN1 +sclr => _.IN0 +sclr => _.IN0 +sclr => cntr_do7:count_usedw.sclr +usedw_out[0] <= usedw[0].DB_MAX_OUTPUT_PORT_TYPE +usedw_out[1] <= usedw[1].DB_MAX_OUTPUT_PORT_TYPE +usedw_out[2] <= usedw[2].DB_MAX_OUTPUT_PORT_TYPE +usedw_out[3] <= usedw[3].DB_MAX_OUTPUT_PORT_TYPE +usedw_out[4] <= usedw[4].DB_MAX_OUTPUT_PORT_TYPE +usedw_out[5] <= usedw[5].DB_MAX_OUTPUT_PORT_TYPE +wreq => _.IN1 +wreq => _.IN1 +wreq => _.IN0 +wreq => _.IN0 +wreq => cntr_do7:count_usedw.updown + + +|de0_nano_system|system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw +aclr => counter_reg_bit[5].IN0 +clock => counter_reg_bit[5].CLK +clock => counter_reg_bit[4].CLK +clock => counter_reg_bit[3].CLK +clock => counter_reg_bit[2].CLK +clock => counter_reg_bit[1].CLK +clock => counter_reg_bit[0].CLK +cnt_en => _.IN1 +q[0] <= counter_reg_bit[0].DB_MAX_OUTPUT_PORT_TYPE +q[1] <= counter_reg_bit[1].DB_MAX_OUTPUT_PORT_TYPE +q[2] <= counter_reg_bit[2].DB_MAX_OUTPUT_PORT_TYPE +q[3] <= counter_reg_bit[3].DB_MAX_OUTPUT_PORT_TYPE +q[4] <= counter_reg_bit[4].DB_MAX_OUTPUT_PORT_TYPE +q[5] <= counter_reg_bit[5].DB_MAX_OUTPUT_PORT_TYPE +sclr => _.IN0 +sclr => _.IN0 +sclr => _.IN0 +updown => counter_comb_bita0.DATAB +updown => counter_comb_bita1.DATAB +updown => counter_comb_bita2.DATAB +updown => counter_comb_bita3.DATAB +updown => counter_comb_bita4.DATAB +updown => counter_comb_bita5.DATAB + + +|de0_nano_system|system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram +data[0] => altsyncram_r1m1:altsyncram1.data_a[0] +data[1] => altsyncram_r1m1:altsyncram1.data_a[1] +data[2] => altsyncram_r1m1:altsyncram1.data_a[2] +data[3] => altsyncram_r1m1:altsyncram1.data_a[3] +data[4] => altsyncram_r1m1:altsyncram1.data_a[4] +data[5] => altsyncram_r1m1:altsyncram1.data_a[5] +data[6] => altsyncram_r1m1:altsyncram1.data_a[6] +data[7] => altsyncram_r1m1:altsyncram1.data_a[7] +inclock => altsyncram_r1m1:altsyncram1.clock0 +outclock => altsyncram_r1m1:altsyncram1.clock1 +outclocken => altsyncram_r1m1:altsyncram1.clocken1 +q[0] <= altsyncram_r1m1:altsyncram1.q_b[0] +q[1] <= altsyncram_r1m1:altsyncram1.q_b[1] +q[2] <= altsyncram_r1m1:altsyncram1.q_b[2] +q[3] <= altsyncram_r1m1:altsyncram1.q_b[3] +q[4] <= altsyncram_r1m1:altsyncram1.q_b[4] +q[5] <= altsyncram_r1m1:altsyncram1.q_b[5] +q[6] <= altsyncram_r1m1:altsyncram1.q_b[6] +q[7] <= altsyncram_r1m1:altsyncram1.q_b[7] +rdaddress[0] => altsyncram_r1m1:altsyncram1.address_b[0] +rdaddress[1] => altsyncram_r1m1:altsyncram1.address_b[1] +rdaddress[2] => altsyncram_r1m1:altsyncram1.address_b[2] +rdaddress[3] => altsyncram_r1m1:altsyncram1.address_b[3] +rdaddress[4] => altsyncram_r1m1:altsyncram1.address_b[4] +rdaddress[5] => altsyncram_r1m1:altsyncram1.address_b[5] +wraddress[0] => altsyncram_r1m1:altsyncram1.address_a[0] +wraddress[1] => altsyncram_r1m1:altsyncram1.address_a[1] +wraddress[2] => altsyncram_r1m1:altsyncram1.address_a[2] +wraddress[3] => altsyncram_r1m1:altsyncram1.address_a[3] +wraddress[4] => altsyncram_r1m1:altsyncram1.address_a[4] +wraddress[5] => altsyncram_r1m1:altsyncram1.address_a[5] +wren => altsyncram_r1m1:altsyncram1.wren_a + + +|de0_nano_system|system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1 +address_a[0] => ram_block2a0.PORTAADDR +address_a[0] => ram_block2a1.PORTAADDR +address_a[0] => ram_block2a2.PORTAADDR +address_a[0] => ram_block2a3.PORTAADDR +address_a[0] => ram_block2a4.PORTAADDR +address_a[0] => ram_block2a5.PORTAADDR +address_a[0] => ram_block2a6.PORTAADDR +address_a[0] => ram_block2a7.PORTAADDR +address_a[1] => ram_block2a0.PORTAADDR1 +address_a[1] => ram_block2a1.PORTAADDR1 +address_a[1] => ram_block2a2.PORTAADDR1 +address_a[1] => ram_block2a3.PORTAADDR1 +address_a[1] => ram_block2a4.PORTAADDR1 +address_a[1] => ram_block2a5.PORTAADDR1 +address_a[1] => ram_block2a6.PORTAADDR1 +address_a[1] => ram_block2a7.PORTAADDR1 +address_a[2] => ram_block2a0.PORTAADDR2 +address_a[2] => ram_block2a1.PORTAADDR2 +address_a[2] => ram_block2a2.PORTAADDR2 +address_a[2] => ram_block2a3.PORTAADDR2 +address_a[2] => ram_block2a4.PORTAADDR2 +address_a[2] => ram_block2a5.PORTAADDR2 +address_a[2] => ram_block2a6.PORTAADDR2 +address_a[2] => ram_block2a7.PORTAADDR2 +address_a[3] => ram_block2a0.PORTAADDR3 +address_a[3] => ram_block2a1.PORTAADDR3 +address_a[3] => ram_block2a2.PORTAADDR3 +address_a[3] => ram_block2a3.PORTAADDR3 +address_a[3] => ram_block2a4.PORTAADDR3 +address_a[3] => ram_block2a5.PORTAADDR3 +address_a[3] => ram_block2a6.PORTAADDR3 +address_a[3] => ram_block2a7.PORTAADDR3 +address_a[4] => ram_block2a0.PORTAADDR4 +address_a[4] => ram_block2a1.PORTAADDR4 +address_a[4] => ram_block2a2.PORTAADDR4 +address_a[4] => ram_block2a3.PORTAADDR4 +address_a[4] => ram_block2a4.PORTAADDR4 +address_a[4] => ram_block2a5.PORTAADDR4 +address_a[4] => ram_block2a6.PORTAADDR4 +address_a[4] => ram_block2a7.PORTAADDR4 +address_a[5] => ram_block2a0.PORTAADDR5 +address_a[5] => ram_block2a1.PORTAADDR5 +address_a[5] => ram_block2a2.PORTAADDR5 +address_a[5] => ram_block2a3.PORTAADDR5 +address_a[5] => ram_block2a4.PORTAADDR5 +address_a[5] => ram_block2a5.PORTAADDR5 +address_a[5] => ram_block2a6.PORTAADDR5 +address_a[5] => ram_block2a7.PORTAADDR5 +address_b[0] => ram_block2a0.PORTBADDR +address_b[0] => ram_block2a1.PORTBADDR +address_b[0] => ram_block2a2.PORTBADDR +address_b[0] => ram_block2a3.PORTBADDR +address_b[0] => ram_block2a4.PORTBADDR +address_b[0] => ram_block2a5.PORTBADDR +address_b[0] => ram_block2a6.PORTBADDR +address_b[0] => ram_block2a7.PORTBADDR +address_b[1] => ram_block2a0.PORTBADDR1 +address_b[1] => ram_block2a1.PORTBADDR1 +address_b[1] => ram_block2a2.PORTBADDR1 +address_b[1] => ram_block2a3.PORTBADDR1 +address_b[1] => ram_block2a4.PORTBADDR1 +address_b[1] => ram_block2a5.PORTBADDR1 +address_b[1] => ram_block2a6.PORTBADDR1 +address_b[1] => ram_block2a7.PORTBADDR1 +address_b[2] => ram_block2a0.PORTBADDR2 +address_b[2] => ram_block2a1.PORTBADDR2 +address_b[2] => ram_block2a2.PORTBADDR2 +address_b[2] => ram_block2a3.PORTBADDR2 +address_b[2] => ram_block2a4.PORTBADDR2 +address_b[2] => ram_block2a5.PORTBADDR2 +address_b[2] => ram_block2a6.PORTBADDR2 +address_b[2] => ram_block2a7.PORTBADDR2 +address_b[3] => ram_block2a0.PORTBADDR3 +address_b[3] => ram_block2a1.PORTBADDR3 +address_b[3] => ram_block2a2.PORTBADDR3 +address_b[3] => ram_block2a3.PORTBADDR3 +address_b[3] => ram_block2a4.PORTBADDR3 +address_b[3] => ram_block2a5.PORTBADDR3 +address_b[3] => ram_block2a6.PORTBADDR3 +address_b[3] => ram_block2a7.PORTBADDR3 +address_b[4] => ram_block2a0.PORTBADDR4 +address_b[4] => ram_block2a1.PORTBADDR4 +address_b[4] => ram_block2a2.PORTBADDR4 +address_b[4] => ram_block2a3.PORTBADDR4 +address_b[4] => ram_block2a4.PORTBADDR4 +address_b[4] => ram_block2a5.PORTBADDR4 +address_b[4] => ram_block2a6.PORTBADDR4 +address_b[4] => ram_block2a7.PORTBADDR4 +address_b[5] => ram_block2a0.PORTBADDR5 +address_b[5] => ram_block2a1.PORTBADDR5 +address_b[5] => ram_block2a2.PORTBADDR5 +address_b[5] => ram_block2a3.PORTBADDR5 +address_b[5] => ram_block2a4.PORTBADDR5 +address_b[5] => ram_block2a5.PORTBADDR5 +address_b[5] => ram_block2a6.PORTBADDR5 +address_b[5] => ram_block2a7.PORTBADDR5 +clock0 => ram_block2a0.CLK0 +clock0 => ram_block2a1.CLK0 +clock0 => ram_block2a2.CLK0 +clock0 => ram_block2a3.CLK0 +clock0 => ram_block2a4.CLK0 +clock0 => ram_block2a5.CLK0 +clock0 => ram_block2a6.CLK0 +clock0 => ram_block2a7.CLK0 +clock1 => ram_block2a0.CLK1 +clock1 => ram_block2a1.CLK1 +clock1 => ram_block2a2.CLK1 +clock1 => ram_block2a3.CLK1 +clock1 => ram_block2a4.CLK1 +clock1 => ram_block2a5.CLK1 +clock1 => ram_block2a6.CLK1 +clock1 => ram_block2a7.CLK1 +clocken1 => ram_block2a0.ENA1 +clocken1 => ram_block2a1.ENA1 +clocken1 => ram_block2a2.ENA1 +clocken1 => ram_block2a3.ENA1 +clocken1 => ram_block2a4.ENA1 +clocken1 => ram_block2a5.ENA1 +clocken1 => ram_block2a6.ENA1 +clocken1 => ram_block2a7.ENA1 +data_a[0] => ram_block2a0.PORTADATAIN +data_a[1] => ram_block2a1.PORTADATAIN +data_a[2] => ram_block2a2.PORTADATAIN +data_a[3] => ram_block2a3.PORTADATAIN +data_a[4] => ram_block2a4.PORTADATAIN +data_a[5] => ram_block2a5.PORTADATAIN +data_a[6] => ram_block2a6.PORTADATAIN +data_a[7] => ram_block2a7.PORTADATAIN +q_b[0] <= ram_block2a0.PORTBDATAOUT +q_b[1] <= ram_block2a1.PORTBDATAOUT +q_b[2] <= ram_block2a2.PORTBDATAOUT +q_b[3] <= ram_block2a3.PORTBDATAOUT +q_b[4] <= ram_block2a4.PORTBDATAOUT +q_b[5] <= ram_block2a5.PORTBDATAOUT +q_b[6] <= ram_block2a6.PORTBDATAOUT +q_b[7] <= ram_block2a7.PORTBDATAOUT +wren_a => ram_block2a0.PORTAWE +wren_a => ram_block2a0.ENA0 +wren_a => ram_block2a1.PORTAWE +wren_a => ram_block2a1.ENA0 +wren_a => ram_block2a2.PORTAWE +wren_a => ram_block2a2.ENA0 +wren_a => ram_block2a3.PORTAWE +wren_a => ram_block2a3.ENA0 +wren_a => ram_block2a4.PORTAWE +wren_a => ram_block2a4.ENA0 +wren_a => ram_block2a5.PORTAWE +wren_a => ram_block2a5.ENA0 +wren_a => ram_block2a6.PORTAWE +wren_a => ram_block2a6.ENA0 +wren_a => ram_block2a7.PORTAWE +wren_a => ram_block2a7.ENA0 + + +|de0_nano_system|system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:rd_ptr_count +aclr => counter_reg_bit[5].IN0 +clock => counter_reg_bit[5].CLK +clock => counter_reg_bit[4].CLK +clock => counter_reg_bit[3].CLK +clock => counter_reg_bit[2].CLK +clock => counter_reg_bit[1].CLK +clock => counter_reg_bit[0].CLK +cnt_en => _.IN1 +q[0] <= counter_reg_bit[0].DB_MAX_OUTPUT_PORT_TYPE +q[1] <= counter_reg_bit[1].DB_MAX_OUTPUT_PORT_TYPE +q[2] <= counter_reg_bit[2].DB_MAX_OUTPUT_PORT_TYPE +q[3] <= counter_reg_bit[3].DB_MAX_OUTPUT_PORT_TYPE +q[4] <= counter_reg_bit[4].DB_MAX_OUTPUT_PORT_TYPE +q[5] <= counter_reg_bit[5].DB_MAX_OUTPUT_PORT_TYPE +sclr => _.IN0 +sclr => _.IN0 +sclr => _.IN0 + + +|de0_nano_system|system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr +aclr => counter_reg_bit[5].IN0 +clock => counter_reg_bit[5].CLK +clock => counter_reg_bit[4].CLK +clock => counter_reg_bit[3].CLK +clock => counter_reg_bit[2].CLK +clock => counter_reg_bit[1].CLK +clock => counter_reg_bit[0].CLK +cnt_en => _.IN1 +q[0] <= counter_reg_bit[0].DB_MAX_OUTPUT_PORT_TYPE +q[1] <= counter_reg_bit[1].DB_MAX_OUTPUT_PORT_TYPE +q[2] <= counter_reg_bit[2].DB_MAX_OUTPUT_PORT_TYPE +q[3] <= counter_reg_bit[3].DB_MAX_OUTPUT_PORT_TYPE +q[4] <= counter_reg_bit[4].DB_MAX_OUTPUT_PORT_TYPE +q[5] <= counter_reg_bit[5].DB_MAX_OUTPUT_PORT_TYPE +sclr => _.IN0 +sclr => _.IN0 +sclr => _.IN0 + + +|de0_nano_system|system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic +raw_tck => write_stalled.CLK +raw_tck => wdata[0].CLK +raw_tck => wdata[1].CLK +raw_tck => wdata[2].CLK +raw_tck => wdata[3].CLK +raw_tck => wdata[4].CLK +raw_tck => wdata[5].CLK +raw_tck => wdata[6].CLK +raw_tck => wdata[7].CLK +raw_tck => write.CLK +raw_tck => read.CLK +raw_tck => read_req.CLK +raw_tck => write_valid.CLK +raw_tck => count[0].CLK +raw_tck => count[1].CLK +raw_tck => count[2].CLK +raw_tck => count[3].CLK +raw_tck => count[4].CLK +raw_tck => count[5].CLK +raw_tck => count[6].CLK +raw_tck => count[7].CLK +raw_tck => count[8].CLK +raw_tck => count[9].CLK +raw_tck => state.CLK +raw_tck => user_saw_rvalid.CLK +raw_tck => td_shift[0].CLK +raw_tck => td_shift[1].CLK +raw_tck => td_shift[2].CLK +raw_tck => td_shift[3].CLK +raw_tck => td_shift[4].CLK +raw_tck => td_shift[5].CLK +raw_tck => td_shift[6].CLK +raw_tck => td_shift[7].CLK +raw_tck => td_shift[8].CLK +raw_tck => td_shift[9].CLK +raw_tck => td_shift[10].CLK +raw_tck => tck_t_dav.CLK +raw_tck => jupdate.CLK +raw_tck => tdo~reg0.CLK +tck => ~NO_FANOUT~ +tdi => td_shift.OUTPUTSELECT +tdi => count.OUTPUTSELECT +tdi => state.OUTPUTSELECT +tdi => wdata.DATAB +tdi => always0.IN1 +tdi => wdata.DATAB +tdi => td_shift.DATAB +rti => ~NO_FANOUT~ +shift => ~NO_FANOUT~ +update => ~NO_FANOUT~ +usr1 => always0.IN0 +clr => jupdate.ACLR +clr => tdo~reg0.ACLR +clr => write_stalled.ACLR +clr => wdata[0].ACLR +clr => wdata[1].ACLR +clr => wdata[2].ACLR +clr => wdata[3].ACLR +clr => wdata[4].ACLR +clr => wdata[5].ACLR +clr => wdata[6].ACLR +clr => wdata[7].ACLR +clr => write.ACLR +clr => read.ACLR +clr => read_req.ACLR +clr => write_valid.ACLR +clr => count[0].ACLR +clr => count[1].ACLR +clr => count[2].ACLR +clr => count[3].ACLR +clr => count[4].ACLR +clr => count[5].ACLR +clr => count[6].ACLR +clr => count[7].ACLR +clr => count[8].ACLR +clr => count[9].PRESET +clr => state.ACLR +clr => user_saw_rvalid.ACLR +clr => td_shift[0].ACLR +clr => td_shift[1].ACLR +clr => td_shift[2].ACLR +clr => td_shift[3].ACLR +clr => td_shift[4].ACLR +clr => td_shift[5].ACLR +clr => td_shift[6].ACLR +clr => td_shift[7].ACLR +clr => td_shift[8].ACLR +clr => td_shift[9].ACLR +clr => td_shift[10].ACLR +clr => tck_t_dav.ACLR +ena => always0.IN1 +ir_in[0] => Decoder1.IN0 +ir_in[0] => ir_out[0].DATAIN +tdo <= tdo~reg0.DB_MAX_OUTPUT_PORT_TYPE +irq <= +ir_out[0] <= ir_in[0].DB_MAX_OUTPUT_PORT_TYPE +jtag_state_cdr => state.OUTPUTSELECT +jtag_state_cdr => count.OUTPUTSELECT +jtag_state_cdr => count.OUTPUTSELECT +jtag_state_cdr => count.OUTPUTSELECT +jtag_state_cdr => count.OUTPUTSELECT +jtag_state_cdr => count.OUTPUTSELECT +jtag_state_cdr => count.OUTPUTSELECT +jtag_state_cdr => count.OUTPUTSELECT +jtag_state_cdr => count.OUTPUTSELECT +jtag_state_cdr => count.OUTPUTSELECT +jtag_state_cdr => count.OUTPUTSELECT +jtag_state_cdr => td_shift.OUTPUTSELECT +jtag_state_cdr => td_shift.OUTPUTSELECT +jtag_state_cdr => td_shift.OUTPUTSELECT +jtag_state_cdr => td_shift.OUTPUTSELECT +jtag_state_cdr => td_shift.OUTPUTSELECT +jtag_state_cdr => td_shift.OUTPUTSELECT +jtag_state_cdr => td_shift.OUTPUTSELECT +jtag_state_cdr => td_shift.OUTPUTSELECT +jtag_state_cdr => td_shift.OUTPUTSELECT +jtag_state_cdr => td_shift.OUTPUTSELECT +jtag_state_cdr => td_shift.OUTPUTSELECT +jtag_state_sdr => count.OUTPUTSELECT +jtag_state_sdr => count.OUTPUTSELECT +jtag_state_sdr => count.OUTPUTSELECT +jtag_state_sdr => count.OUTPUTSELECT +jtag_state_sdr => count.OUTPUTSELECT +jtag_state_sdr => count.OUTPUTSELECT +jtag_state_sdr => count.OUTPUTSELECT +jtag_state_sdr => count.OUTPUTSELECT +jtag_state_sdr => count.OUTPUTSELECT +jtag_state_sdr => count.OUTPUTSELECT +jtag_state_sdr => td_shift.OUTPUTSELECT +jtag_state_sdr => td_shift.OUTPUTSELECT +jtag_state_sdr => td_shift.OUTPUTSELECT +jtag_state_sdr => td_shift.OUTPUTSELECT +jtag_state_sdr => td_shift.OUTPUTSELECT +jtag_state_sdr => td_shift.OUTPUTSELECT +jtag_state_sdr => td_shift.OUTPUTSELECT +jtag_state_sdr => td_shift.OUTPUTSELECT +jtag_state_sdr => td_shift.OUTPUTSELECT +jtag_state_sdr => td_shift.OUTPUTSELECT +jtag_state_sdr => td_shift.OUTPUTSELECT +jtag_state_sdr => write.OUTPUTSELECT +jtag_state_sdr => wdata.OUTPUTSELECT +jtag_state_sdr => wdata.OUTPUTSELECT +jtag_state_sdr => wdata.OUTPUTSELECT +jtag_state_sdr => wdata.OUTPUTSELECT +jtag_state_sdr => wdata.OUTPUTSELECT +jtag_state_sdr => wdata.OUTPUTSELECT +jtag_state_sdr => wdata.OUTPUTSELECT +jtag_state_sdr => wdata.OUTPUTSELECT +jtag_state_sdr => user_saw_rvalid.OUTPUTSELECT +jtag_state_sdr => read.OUTPUTSELECT +jtag_state_sdr => write_valid.OUTPUTSELECT +jtag_state_sdr => read_req.OUTPUTSELECT +jtag_state_sdr => write_stalled.OUTPUTSELECT +jtag_state_sdr => state.OUTPUTSELECT +jtag_state_udr => jupdate.OUTPUTSELECT +clk => t_pause~reg0.CLK +clk => t_ena~reg0.CLK +clk => rdata[0].CLK +clk => rdata[1].CLK +clk => rdata[2].CLK +clk => rdata[3].CLK +clk => rdata[4].CLK +clk => rdata[5].CLK +clk => rdata[6].CLK +clk => rdata[7].CLK +clk => rvalid.CLK +clk => rvalid0.CLK +clk => r_ena1.CLK +clk => jupdate2.CLK +clk => jupdate1.CLK +clk => write2.CLK +clk => write1.CLK +clk => read2.CLK +clk => read1.CLK +clk => rst2.CLK +clk => rst1.CLK +rst_n => t_pause~reg0.ACLR +rst_n => t_ena~reg0.ACLR +rst_n => rdata[0].ACLR +rst_n => rdata[1].ACLR +rst_n => rdata[2].ACLR +rst_n => rdata[3].ACLR +rst_n => rdata[4].ACLR +rst_n => rdata[5].ACLR +rst_n => rdata[6].ACLR +rst_n => rdata[7].ACLR +rst_n => rvalid.ACLR +rst_n => rvalid0.ACLR +rst_n => r_ena1.ACLR +rst_n => jupdate2.ACLR +rst_n => jupdate1.ACLR +rst_n => write2.ACLR +rst_n => write1.ACLR +rst_n => read2.ACLR +rst_n => read1.ACLR +rst_n => rst2.PRESET +rst_n => rst1.PRESET +r_ena <= r_ena.DB_MAX_OUTPUT_PORT_TYPE +r_val => r_ena.IN1 +r_dat[0] => rdata[0].DATAIN +r_dat[1] => rdata[1].DATAIN +r_dat[2] => rdata[2].DATAIN +r_dat[3] => rdata[3].DATAIN +r_dat[4] => rdata[4].DATAIN +r_dat[5] => rdata[5].DATAIN +r_dat[6] => rdata[6].DATAIN +r_dat[7] => rdata[7].DATAIN +t_dav => always2.IN1 +t_dav => tck_t_dav.DATAIN +t_ena <= t_ena~reg0.DB_MAX_OUTPUT_PORT_TYPE +t_dat[0] <= t_dat[0].DB_MAX_OUTPUT_PORT_TYPE +t_dat[1] <= t_dat[1].DB_MAX_OUTPUT_PORT_TYPE +t_dat[2] <= t_dat[2].DB_MAX_OUTPUT_PORT_TYPE +t_dat[3] <= t_dat[3].DB_MAX_OUTPUT_PORT_TYPE +t_dat[4] <= t_dat[4].DB_MAX_OUTPUT_PORT_TYPE +t_dat[5] <= t_dat[5].DB_MAX_OUTPUT_PORT_TYPE +t_dat[6] <= t_dat[6].DB_MAX_OUTPUT_PORT_TYPE +t_dat[7] <= t_dat[7].DB_MAX_OUTPUT_PORT_TYPE +t_pause <= t_pause~reg0.DB_MAX_OUTPUT_PORT_TYPE + + +|de0_nano_system|system:inst_cpu|system_pio_motor_rst:pio_motor_rst +address[0] => Equal0.IN31 +address[1] => Equal0.IN30 +chipselect => always0.IN0 +clk => data_out.CLK +reset_n => data_out.ACLR +write_n => always0.IN1 +writedata[0] => data_out.DATAIN +writedata[1] => ~NO_FANOUT~ +writedata[2] => ~NO_FANOUT~ +writedata[3] => ~NO_FANOUT~ +writedata[4] => ~NO_FANOUT~ +writedata[5] => ~NO_FANOUT~ +writedata[6] => ~NO_FANOUT~ +writedata[7] => ~NO_FANOUT~ +writedata[8] => ~NO_FANOUT~ +writedata[9] => ~NO_FANOUT~ +writedata[10] => ~NO_FANOUT~ +writedata[11] => ~NO_FANOUT~ +writedata[12] => ~NO_FANOUT~ +writedata[13] => ~NO_FANOUT~ +writedata[14] => ~NO_FANOUT~ +writedata[15] => ~NO_FANOUT~ +writedata[16] => ~NO_FANOUT~ +writedata[17] => ~NO_FANOUT~ +writedata[18] => ~NO_FANOUT~ +writedata[19] => ~NO_FANOUT~ +writedata[20] => ~NO_FANOUT~ +writedata[21] => ~NO_FANOUT~ +writedata[22] => ~NO_FANOUT~ +writedata[23] => ~NO_FANOUT~ +writedata[24] => ~NO_FANOUT~ +writedata[25] => ~NO_FANOUT~ +writedata[26] => ~NO_FANOUT~ +writedata[27] => ~NO_FANOUT~ +writedata[28] => ~NO_FANOUT~ +writedata[29] => ~NO_FANOUT~ +writedata[30] => ~NO_FANOUT~ +writedata[31] => ~NO_FANOUT~ +out_port <= data_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[0] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE +readdata[1] <= +readdata[2] <= +readdata[3] <= +readdata[4] <= +readdata[5] <= +readdata[6] <= +readdata[7] <= +readdata[8] <= +readdata[9] <= +readdata[10] <= +readdata[11] <= +readdata[12] <= +readdata[13] <= +readdata[14] <= +readdata[15] <= +readdata[16] <= +readdata[17] <= +readdata[18] <= +readdata[19] <= +readdata[20] <= +readdata[21] <= +readdata[22] <= +readdata[23] <= +readdata[24] <= +readdata[25] <= +readdata[26] <= +readdata[27] <= +readdata[28] <= +readdata[29] <= +readdata[30] <= +readdata[31] <= + + +|de0_nano_system|system:inst_cpu|system_rs232_motor:rs232_motor +clk => clk.IN2 +reset => reset.IN2 +address => always2.IN1 +address => readdata.OUTPUTSELECT +address => readdata.OUTPUTSELECT +address => readdata.OUTPUTSELECT +address => readdata.OUTPUTSELECT +address => readdata.OUTPUTSELECT +address => readdata.OUTPUTSELECT +address => readdata.OUTPUTSELECT +address => readdata.OUTPUTSELECT +address => readdata.OUTPUTSELECT +address => readdata.OUTPUTSELECT +address => readdata.OUTPUTSELECT +address => readdata.OUTPUTSELECT +address => readdata.OUTPUTSELECT +address => readdata.OUTPUTSELECT +address => readdata.OUTPUTSELECT +address => readdata.OUTPUTSELECT +address => readdata.OUTPUTSELECT +address => readdata.OUTPUTSELECT +address => readdata.OUTPUTSELECT +address => write_fifo_write_en.IN1 +address => read_fifo_read_en.IN1 +chipselect => readdata.OUTPUTSELECT +chipselect => readdata.OUTPUTSELECT +chipselect => readdata.OUTPUTSELECT +chipselect => readdata.OUTPUTSELECT +chipselect => readdata.OUTPUTSELECT +chipselect => readdata.OUTPUTSELECT +chipselect => readdata.OUTPUTSELECT +chipselect => readdata.OUTPUTSELECT +chipselect => readdata.OUTPUTSELECT +chipselect => readdata.OUTPUTSELECT +chipselect => readdata.OUTPUTSELECT +chipselect => readdata.OUTPUTSELECT +chipselect => readdata.OUTPUTSELECT +chipselect => readdata.OUTPUTSELECT +chipselect => readdata.OUTPUTSELECT +chipselect => readdata.OUTPUTSELECT +chipselect => readdata.OUTPUTSELECT +chipselect => readdata.OUTPUTSELECT +chipselect => readdata.OUTPUTSELECT +chipselect => readdata.OUTPUTSELECT +chipselect => readdata.OUTPUTSELECT +chipselect => readdata.OUTPUTSELECT +chipselect => readdata.OUTPUTSELECT +chipselect => readdata.OUTPUTSELECT +chipselect => readdata.OUTPUTSELECT +chipselect => readdata.OUTPUTSELECT +chipselect => readdata.OUTPUTSELECT +chipselect => readdata.OUTPUTSELECT +chipselect => readdata.OUTPUTSELECT +chipselect => readdata.OUTPUTSELECT +chipselect => readdata.OUTPUTSELECT +chipselect => readdata.OUTPUTSELECT +chipselect => always2.IN0 +chipselect => read_fifo_read_en.IN0 +byteenable[0] => always2.IN1 +byteenable[0] => write_fifo_write_en.IN1 +byteenable[0] => read_fifo_read_en.IN1 +byteenable[1] => ~NO_FANOUT~ +byteenable[2] => ~NO_FANOUT~ +byteenable[3] => ~NO_FANOUT~ +read => read_fifo_read_en.IN1 +write => always2.IN1 +writedata[0] => read_interrupt_en.DATAB +writedata[0] => data_to_uart.DATAA +writedata[1] => write_interrupt_en.DATAB +writedata[1] => data_to_uart.DATAA +writedata[2] => data_to_uart.DATAA +writedata[3] => data_to_uart.DATAA +writedata[4] => data_to_uart.DATAA +writedata[5] => data_to_uart.DATAA +writedata[6] => data_to_uart.DATAA +writedata[7] => data_to_uart.DATAA +writedata[8] => ~NO_FANOUT~ +writedata[9] => ~NO_FANOUT~ +writedata[10] => ~NO_FANOUT~ +writedata[11] => ~NO_FANOUT~ +writedata[12] => ~NO_FANOUT~ +writedata[13] => ~NO_FANOUT~ +writedata[14] => ~NO_FANOUT~ +writedata[15] => ~NO_FANOUT~ +writedata[16] => ~NO_FANOUT~ +writedata[17] => ~NO_FANOUT~ +writedata[18] => ~NO_FANOUT~ +writedata[19] => ~NO_FANOUT~ +writedata[20] => ~NO_FANOUT~ +writedata[21] => ~NO_FANOUT~ +writedata[22] => ~NO_FANOUT~ +writedata[23] => ~NO_FANOUT~ +writedata[24] => ~NO_FANOUT~ +writedata[25] => ~NO_FANOUT~ +writedata[26] => ~NO_FANOUT~ +writedata[27] => ~NO_FANOUT~ +writedata[28] => ~NO_FANOUT~ +writedata[29] => ~NO_FANOUT~ +writedata[30] => ~NO_FANOUT~ +writedata[31] => ~NO_FANOUT~ +UART_RXD => UART_RXD.IN1 +irq <= irq~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[0] <= readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[1] <= readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[2] <= readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[3] <= readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[4] <= readdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[5] <= readdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[6] <= readdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[7] <= readdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[8] <= readdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[9] <= readdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[10] <= readdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[11] <= readdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[12] <= readdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[13] <= readdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[14] <= readdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[15] <= readdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[16] <= readdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[17] <= readdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[18] <= readdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[19] <= readdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[20] <= readdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[21] <= readdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[22] <= readdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[23] <= readdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[24] <= readdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[25] <= readdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[26] <= readdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[27] <= readdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[28] <= readdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[29] <= readdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[30] <= readdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE +readdata[31] <= readdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE +UART_TXD <= altera_up_rs232_out_serializer:RS232_Out_Serializer.serial_data_out + + +|de0_nano_system|system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer +clk => clk.IN2 +reset => reset.IN2 +serial_data_in => data_in_shift_reg.DATAB +serial_data_in => receiving_data.OUTPUTSELECT +receive_data_en => comb.IN1 +fifo_read_available[0] <= fifo_read_available[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fifo_read_available[1] <= fifo_read_available[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fifo_read_available[2] <= fifo_read_available[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fifo_read_available[3] <= fifo_read_available[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fifo_read_available[4] <= fifo_read_available[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fifo_read_available[5] <= fifo_read_available[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fifo_read_available[6] <= fifo_read_available[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fifo_read_available[7] <= fifo_read_available[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE +received_data_valid <= altera_up_sync_fifo:RS232_In_FIFO.fifo_is_empty +received_data[0] <= altera_up_sync_fifo:RS232_In_FIFO.read_data +received_data[1] <= altera_up_sync_fifo:RS232_In_FIFO.read_data +received_data[2] <= altera_up_sync_fifo:RS232_In_FIFO.read_data +received_data[3] <= altera_up_sync_fifo:RS232_In_FIFO.read_data +received_data[4] <= altera_up_sync_fifo:RS232_In_FIFO.read_data +received_data[5] <= altera_up_sync_fifo:RS232_In_FIFO.read_data +received_data[6] <= altera_up_sync_fifo:RS232_In_FIFO.read_data +received_data[7] <= altera_up_sync_fifo:RS232_In_FIFO.read_data + + +|de0_nano_system|system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_rs232_counters:RS232_In_Counters +clk => all_bits_transmitted~reg0.CLK +clk => bit_counter[0].CLK +clk => bit_counter[1].CLK +clk => bit_counter[2].CLK +clk => bit_counter[3].CLK +clk => baud_clock_falling_edge~reg0.CLK +clk => baud_clock_rising_edge~reg0.CLK +clk => baud_counter[0].CLK +clk => baud_counter[1].CLK +clk => baud_counter[2].CLK +clk => baud_counter[3].CLK +clk => baud_counter[4].CLK +clk => baud_counter[5].CLK +clk => baud_counter[6].CLK +clk => baud_counter[7].CLK +clk => baud_counter[8].CLK +clk => baud_counter[9].CLK +clk => baud_counter[10].CLK +clk => baud_counter[11].CLK +clk => baud_counter[12].CLK +clk => baud_counter[13].CLK +reset => baud_counter.OUTPUTSELECT +reset => baud_counter.OUTPUTSELECT +reset => baud_counter.OUTPUTSELECT +reset => baud_counter.OUTPUTSELECT +reset => baud_counter.OUTPUTSELECT +reset => baud_counter.OUTPUTSELECT +reset => baud_counter.OUTPUTSELECT +reset => baud_counter.OUTPUTSELECT +reset => baud_counter.OUTPUTSELECT +reset => baud_counter.OUTPUTSELECT +reset => baud_counter.OUTPUTSELECT +reset => baud_counter.OUTPUTSELECT +reset => baud_counter.OUTPUTSELECT +reset => baud_counter.OUTPUTSELECT +reset => baud_clock_rising_edge.OUTPUTSELECT +reset => baud_clock_falling_edge.OUTPUTSELECT +reset => bit_counter.OUTPUTSELECT +reset => bit_counter.OUTPUTSELECT +reset => bit_counter.OUTPUTSELECT +reset => bit_counter.OUTPUTSELECT +reset => all_bits_transmitted.OUTPUTSELECT +reset_counters => baud_counter.OUTPUTSELECT +reset_counters => baud_counter.OUTPUTSELECT +reset_counters => baud_counter.OUTPUTSELECT +reset_counters => baud_counter.OUTPUTSELECT +reset_counters => baud_counter.OUTPUTSELECT +reset_counters => baud_counter.OUTPUTSELECT +reset_counters => baud_counter.OUTPUTSELECT +reset_counters => baud_counter.OUTPUTSELECT +reset_counters => baud_counter.OUTPUTSELECT +reset_counters => baud_counter.OUTPUTSELECT +reset_counters => baud_counter.OUTPUTSELECT +reset_counters => baud_counter.OUTPUTSELECT +reset_counters => baud_counter.OUTPUTSELECT +reset_counters => baud_counter.OUTPUTSELECT +reset_counters => bit_counter.OUTPUTSELECT +reset_counters => bit_counter.OUTPUTSELECT +reset_counters => bit_counter.OUTPUTSELECT +reset_counters => bit_counter.OUTPUTSELECT +baud_clock_rising_edge <= baud_clock_rising_edge~reg0.DB_MAX_OUTPUT_PORT_TYPE +baud_clock_falling_edge <= baud_clock_falling_edge~reg0.DB_MAX_OUTPUT_PORT_TYPE +all_bits_transmitted <= all_bits_transmitted~reg0.DB_MAX_OUTPUT_PORT_TYPE + + +|de0_nano_system|system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO +clk => clk.IN1 +reset => reset.IN1 +write_en => write_en.IN1 +write_data[0] => write_data[0].IN1 +write_data[1] => write_data[1].IN1 +write_data[2] => write_data[2].IN1 +write_data[3] => write_data[3].IN1 +write_data[4] => write_data[4].IN1 +write_data[5] => write_data[5].IN1 +write_data[6] => write_data[6].IN1 +write_data[7] => write_data[7].IN1 +read_en => read_en.IN1 +fifo_is_empty <= scfifo:Sync_FIFO.empty +fifo_is_full <= scfifo:Sync_FIFO.full +words_used[0] <= scfifo:Sync_FIFO.usedw +words_used[1] <= scfifo:Sync_FIFO.usedw +words_used[2] <= scfifo:Sync_FIFO.usedw +words_used[3] <= scfifo:Sync_FIFO.usedw +words_used[4] <= scfifo:Sync_FIFO.usedw +words_used[5] <= scfifo:Sync_FIFO.usedw +words_used[6] <= scfifo:Sync_FIFO.usedw +read_data[0] <= scfifo:Sync_FIFO.q +read_data[1] <= scfifo:Sync_FIFO.q +read_data[2] <= scfifo:Sync_FIFO.q +read_data[3] <= scfifo:Sync_FIFO.q +read_data[4] <= scfifo:Sync_FIFO.q +read_data[5] <= scfifo:Sync_FIFO.q +read_data[6] <= scfifo:Sync_FIFO.q +read_data[7] <= scfifo:Sync_FIFO.q + + +|de0_nano_system|system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO +data[0] => scfifo_a341:auto_generated.data[0] +data[1] => scfifo_a341:auto_generated.data[1] +data[2] => scfifo_a341:auto_generated.data[2] +data[3] => scfifo_a341:auto_generated.data[3] +data[4] => scfifo_a341:auto_generated.data[4] +data[5] => scfifo_a341:auto_generated.data[5] +data[6] => scfifo_a341:auto_generated.data[6] +data[7] => scfifo_a341:auto_generated.data[7] +q[0] <= scfifo_a341:auto_generated.q[0] +q[1] <= scfifo_a341:auto_generated.q[1] +q[2] <= scfifo_a341:auto_generated.q[2] +q[3] <= scfifo_a341:auto_generated.q[3] +q[4] <= scfifo_a341:auto_generated.q[4] +q[5] <= scfifo_a341:auto_generated.q[5] +q[6] <= scfifo_a341:auto_generated.q[6] +q[7] <= scfifo_a341:auto_generated.q[7] +wrreq => scfifo_a341:auto_generated.wrreq +rdreq => scfifo_a341:auto_generated.rdreq +clock => scfifo_a341:auto_generated.clock +aclr => ~NO_FANOUT~ +sclr => scfifo_a341:auto_generated.sclr +empty <= scfifo_a341:auto_generated.empty +full <= scfifo_a341:auto_generated.full +almost_full <= +almost_empty <= +usedw[0] <= scfifo_a341:auto_generated.usedw[0] +usedw[1] <= scfifo_a341:auto_generated.usedw[1] +usedw[2] <= scfifo_a341:auto_generated.usedw[2] +usedw[3] <= scfifo_a341:auto_generated.usedw[3] +usedw[4] <= scfifo_a341:auto_generated.usedw[4] +usedw[5] <= scfifo_a341:auto_generated.usedw[5] +usedw[6] <= scfifo_a341:auto_generated.usedw[6] + + +|de0_nano_system|system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated +clock => a_dpfifo_tq31:dpfifo.clock +data[0] => a_dpfifo_tq31:dpfifo.data[0] +data[1] => a_dpfifo_tq31:dpfifo.data[1] +data[2] => a_dpfifo_tq31:dpfifo.data[2] +data[3] => a_dpfifo_tq31:dpfifo.data[3] +data[4] => a_dpfifo_tq31:dpfifo.data[4] +data[5] => a_dpfifo_tq31:dpfifo.data[5] +data[6] => a_dpfifo_tq31:dpfifo.data[6] +data[7] => a_dpfifo_tq31:dpfifo.data[7] +empty <= a_dpfifo_tq31:dpfifo.empty +full <= a_dpfifo_tq31:dpfifo.full +q[0] <= a_dpfifo_tq31:dpfifo.q[0] +q[1] <= a_dpfifo_tq31:dpfifo.q[1] +q[2] <= a_dpfifo_tq31:dpfifo.q[2] +q[3] <= a_dpfifo_tq31:dpfifo.q[3] +q[4] <= a_dpfifo_tq31:dpfifo.q[4] +q[5] <= a_dpfifo_tq31:dpfifo.q[5] +q[6] <= a_dpfifo_tq31:dpfifo.q[6] +q[7] <= a_dpfifo_tq31:dpfifo.q[7] +rdreq => a_dpfifo_tq31:dpfifo.rreq +sclr => a_dpfifo_tq31:dpfifo.sclr +usedw[0] <= a_dpfifo_tq31:dpfifo.usedw[0] +usedw[1] <= a_dpfifo_tq31:dpfifo.usedw[1] +usedw[2] <= a_dpfifo_tq31:dpfifo.usedw[2] +usedw[3] <= a_dpfifo_tq31:dpfifo.usedw[3] +usedw[4] <= a_dpfifo_tq31:dpfifo.usedw[4] +usedw[5] <= a_dpfifo_tq31:dpfifo.usedw[5] +usedw[6] <= a_dpfifo_tq31:dpfifo.usedw[6] +wrreq => a_dpfifo_tq31:dpfifo.wreq + + +|de0_nano_system|system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo +clock => altsyncram_je81:FIFOram.clock0 +clock => cntr_v9b:rd_ptr_msb.clock +clock => cntr_ca7:usedw_counter.clock +clock => cntr_0ab:wr_ptr.clock +clock => empty_dff.CLK +clock => full_dff.CLK +clock => low_addressa[6].CLK +clock => low_addressa[5].CLK +clock => low_addressa[4].CLK +clock => low_addressa[3].CLK +clock => low_addressa[2].CLK +clock => low_addressa[1].CLK +clock => low_addressa[0].CLK +clock => rd_ptr_lsb.CLK +clock => usedw_is_0_dff.CLK +clock => usedw_is_1_dff.CLK +clock => usedw_is_2_dff.CLK +clock => wrreq_delaya[1].CLK +clock => wrreq_delaya[0].CLK +data[0] => altsyncram_je81:FIFOram.data_a[0] +data[1] => altsyncram_je81:FIFOram.data_a[1] +data[2] => altsyncram_je81:FIFOram.data_a[2] +data[3] => altsyncram_je81:FIFOram.data_a[3] +data[4] => altsyncram_je81:FIFOram.data_a[4] +data[5] => altsyncram_je81:FIFOram.data_a[5] +data[6] => altsyncram_je81:FIFOram.data_a[6] +data[7] => altsyncram_je81:FIFOram.data_a[7] +empty <= empty_out.DB_MAX_OUTPUT_PORT_TYPE +full <= full_dff.DB_MAX_OUTPUT_PORT_TYPE +q[0] <= altsyncram_je81:FIFOram.q_b[0] +q[1] <= altsyncram_je81:FIFOram.q_b[1] +q[2] <= altsyncram_je81:FIFOram.q_b[2] +q[3] <= altsyncram_je81:FIFOram.q_b[3] +q[4] <= altsyncram_je81:FIFOram.q_b[4] +q[5] <= altsyncram_je81:FIFOram.q_b[5] +q[6] <= altsyncram_je81:FIFOram.q_b[6] +q[7] <= altsyncram_je81:FIFOram.q_b[7] +rreq => _.IN0 +rreq => _.IN1 +rreq => _.IN1 +rreq => _.IN1 +rreq => _.IN1 +rreq => _.IN1 +rreq => _.IN0 +rreq => _.IN1 +rreq => _.IN1 +rreq => _.IN0 +rreq => _.IN1 +rreq => _.IN0 +rreq => _.IN0 +rreq => _.IN0 +rreq => _.IN0 +rreq => _.IN0 +rreq => _.IN0 +rreq => _.IN0 +rreq => _.IN0 +rreq => rd_ptr_lsb.IN0 +rreq => _.IN0 +rreq => _.IN0 +rreq => ram_read_address[6].IN0 +rreq => ram_read_address[5].IN0 +rreq => ram_read_address[4].IN0 +rreq => ram_read_address[3].IN0 +rreq => ram_read_address[2].IN0 +rreq => ram_read_address[1].IN0 +rreq => ram_read_address[0].IN0 +sclr => _.IN0 +sclr => _.IN0 +sclr => _.IN0 +sclr => _.IN0 +sclr => rd_ptr_lsb.IN1 +sclr => _.IN0 +sclr => _.IN0 +sclr => cntr_v9b:rd_ptr_msb.sclr +sclr => cntr_ca7:usedw_counter.sclr +sclr => cntr_0ab:wr_ptr.sclr +sclr => _.IN0 +sclr => usedw_will_be_1.IN0 +sclr => usedw_will_be_2.IN0 +usedw[0] <= cntr_ca7:usedw_counter.q[0] +usedw[1] <= cntr_ca7:usedw_counter.q[1] +usedw[2] <= cntr_ca7:usedw_counter.q[2] +usedw[3] <= cntr_ca7:usedw_counter.q[3] +usedw[4] <= cntr_ca7:usedw_counter.q[4] +usedw[5] <= cntr_ca7:usedw_counter.q[5] +usedw[6] <= cntr_ca7:usedw_counter.q[6] +wreq => altsyncram_je81:FIFOram.wren_a +wreq => _.IN0 +wreq => _.IN0 +wreq => wrreq_delaya[1].IN1 +wreq => _.IN0 +wreq => cntr_ca7:usedw_counter.updown +wreq => cntr_0ab:wr_ptr.cnt_en +wreq => _.IN0 +wreq => _.IN0 +wreq => _.IN0 +wreq => _.IN1 +wreq => _.IN0 +wreq => _.IN0 +wreq => _.IN1 +wreq => _.IN0 +wreq => wait_state.IN1 + + +|de0_nano_system|system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram +address_a[0] => ram_block1a0.PORTAADDR +address_a[0] => ram_block1a1.PORTAADDR +address_a[0] => ram_block1a2.PORTAADDR +address_a[0] => ram_block1a3.PORTAADDR +address_a[0] => ram_block1a4.PORTAADDR +address_a[0] => ram_block1a5.PORTAADDR +address_a[0] => ram_block1a6.PORTAADDR +address_a[0] => ram_block1a7.PORTAADDR +address_a[1] => ram_block1a0.PORTAADDR1 +address_a[1] => ram_block1a1.PORTAADDR1 +address_a[1] => ram_block1a2.PORTAADDR1 +address_a[1] => ram_block1a3.PORTAADDR1 +address_a[1] => ram_block1a4.PORTAADDR1 +address_a[1] => ram_block1a5.PORTAADDR1 +address_a[1] => ram_block1a6.PORTAADDR1 +address_a[1] => ram_block1a7.PORTAADDR1 +address_a[2] => ram_block1a0.PORTAADDR2 +address_a[2] => ram_block1a1.PORTAADDR2 +address_a[2] => ram_block1a2.PORTAADDR2 +address_a[2] => ram_block1a3.PORTAADDR2 +address_a[2] => ram_block1a4.PORTAADDR2 +address_a[2] => ram_block1a5.PORTAADDR2 +address_a[2] => ram_block1a6.PORTAADDR2 +address_a[2] => ram_block1a7.PORTAADDR2 +address_a[3] => ram_block1a0.PORTAADDR3 +address_a[3] => ram_block1a1.PORTAADDR3 +address_a[3] => ram_block1a2.PORTAADDR3 +address_a[3] => ram_block1a3.PORTAADDR3 +address_a[3] => ram_block1a4.PORTAADDR3 +address_a[3] => ram_block1a5.PORTAADDR3 +address_a[3] => ram_block1a6.PORTAADDR3 +address_a[3] => ram_block1a7.PORTAADDR3 +address_a[4] => ram_block1a0.PORTAADDR4 +address_a[4] => ram_block1a1.PORTAADDR4 +address_a[4] => ram_block1a2.PORTAADDR4 +address_a[4] => ram_block1a3.PORTAADDR4 +address_a[4] => ram_block1a4.PORTAADDR4 +address_a[4] => ram_block1a5.PORTAADDR4 +address_a[4] => ram_block1a6.PORTAADDR4 +address_a[4] => ram_block1a7.PORTAADDR4 +address_a[5] => ram_block1a0.PORTAADDR5 +address_a[5] => ram_block1a1.PORTAADDR5 +address_a[5] => ram_block1a2.PORTAADDR5 +address_a[5] => ram_block1a3.PORTAADDR5 +address_a[5] => ram_block1a4.PORTAADDR5 +address_a[5] => ram_block1a5.PORTAADDR5 +address_a[5] => ram_block1a6.PORTAADDR5 +address_a[5] => ram_block1a7.PORTAADDR5 +address_a[6] => ram_block1a0.PORTAADDR6 +address_a[6] => ram_block1a1.PORTAADDR6 +address_a[6] => ram_block1a2.PORTAADDR6 +address_a[6] => ram_block1a3.PORTAADDR6 +address_a[6] => ram_block1a4.PORTAADDR6 +address_a[6] => ram_block1a5.PORTAADDR6 +address_a[6] => ram_block1a6.PORTAADDR6 +address_a[6] => ram_block1a7.PORTAADDR6 +address_b[0] => ram_block1a0.PORTBADDR +address_b[0] => ram_block1a1.PORTBADDR +address_b[0] => ram_block1a2.PORTBADDR +address_b[0] => ram_block1a3.PORTBADDR +address_b[0] => ram_block1a4.PORTBADDR +address_b[0] => ram_block1a5.PORTBADDR +address_b[0] => ram_block1a6.PORTBADDR +address_b[0] => ram_block1a7.PORTBADDR +address_b[1] => ram_block1a0.PORTBADDR1 +address_b[1] => ram_block1a1.PORTBADDR1 +address_b[1] => ram_block1a2.PORTBADDR1 +address_b[1] => ram_block1a3.PORTBADDR1 +address_b[1] => ram_block1a4.PORTBADDR1 +address_b[1] => ram_block1a5.PORTBADDR1 +address_b[1] => ram_block1a6.PORTBADDR1 +address_b[1] => ram_block1a7.PORTBADDR1 +address_b[2] => ram_block1a0.PORTBADDR2 +address_b[2] => ram_block1a1.PORTBADDR2 +address_b[2] => ram_block1a2.PORTBADDR2 +address_b[2] => ram_block1a3.PORTBADDR2 +address_b[2] => ram_block1a4.PORTBADDR2 +address_b[2] => ram_block1a5.PORTBADDR2 +address_b[2] => ram_block1a6.PORTBADDR2 +address_b[2] => ram_block1a7.PORTBADDR2 +address_b[3] => ram_block1a0.PORTBADDR3 +address_b[3] => ram_block1a1.PORTBADDR3 +address_b[3] => ram_block1a2.PORTBADDR3 +address_b[3] => ram_block1a3.PORTBADDR3 +address_b[3] => ram_block1a4.PORTBADDR3 +address_b[3] => ram_block1a5.PORTBADDR3 +address_b[3] => ram_block1a6.PORTBADDR3 +address_b[3] => ram_block1a7.PORTBADDR3 +address_b[4] => ram_block1a0.PORTBADDR4 +address_b[4] => ram_block1a1.PORTBADDR4 +address_b[4] => ram_block1a2.PORTBADDR4 +address_b[4] => ram_block1a3.PORTBADDR4 +address_b[4] => ram_block1a4.PORTBADDR4 +address_b[4] => ram_block1a5.PORTBADDR4 +address_b[4] => ram_block1a6.PORTBADDR4 +address_b[4] => ram_block1a7.PORTBADDR4 +address_b[5] => ram_block1a0.PORTBADDR5 +address_b[5] => ram_block1a1.PORTBADDR5 +address_b[5] => ram_block1a2.PORTBADDR5 +address_b[5] => ram_block1a3.PORTBADDR5 +address_b[5] => ram_block1a4.PORTBADDR5 +address_b[5] => ram_block1a5.PORTBADDR5 +address_b[5] => ram_block1a6.PORTBADDR5 +address_b[5] => ram_block1a7.PORTBADDR5 +address_b[6] => ram_block1a0.PORTBADDR6 +address_b[6] => ram_block1a1.PORTBADDR6 +address_b[6] => ram_block1a2.PORTBADDR6 +address_b[6] => ram_block1a3.PORTBADDR6 +address_b[6] => ram_block1a4.PORTBADDR6 +address_b[6] => ram_block1a5.PORTBADDR6 +address_b[6] => ram_block1a6.PORTBADDR6 +address_b[6] => ram_block1a7.PORTBADDR6 +clock0 => ram_block1a0.CLK0 +clock0 => ram_block1a0.CLK1 +clock0 => ram_block1a1.CLK0 +clock0 => ram_block1a1.CLK1 +clock0 => ram_block1a2.CLK0 +clock0 => ram_block1a2.CLK1 +clock0 => ram_block1a3.CLK0 +clock0 => ram_block1a3.CLK1 +clock0 => ram_block1a4.CLK0 +clock0 => ram_block1a4.CLK1 +clock0 => ram_block1a5.CLK0 +clock0 => ram_block1a5.CLK1 +clock0 => ram_block1a6.CLK0 +clock0 => ram_block1a6.CLK1 +clock0 => ram_block1a7.CLK0 +clock0 => ram_block1a7.CLK1 +data_a[0] => ram_block1a0.PORTADATAIN +data_a[1] => ram_block1a1.PORTADATAIN +data_a[2] => ram_block1a2.PORTADATAIN +data_a[3] => ram_block1a3.PORTADATAIN +data_a[4] => ram_block1a4.PORTADATAIN +data_a[5] => ram_block1a5.PORTADATAIN +data_a[6] => ram_block1a6.PORTADATAIN +data_a[7] => ram_block1a7.PORTADATAIN +q_b[0] <= ram_block1a0.PORTBDATAOUT +q_b[1] <= ram_block1a1.PORTBDATAOUT +q_b[2] <= ram_block1a2.PORTBDATAOUT +q_b[3] <= ram_block1a3.PORTBDATAOUT +q_b[4] <= ram_block1a4.PORTBDATAOUT +q_b[5] <= ram_block1a5.PORTBDATAOUT +q_b[6] <= ram_block1a6.PORTBDATAOUT +q_b[7] <= ram_block1a7.PORTBDATAOUT +wren_a => ram_block1a0.PORTAWE +wren_a => ram_block1a0.ENA0 +wren_a => ram_block1a1.PORTAWE +wren_a => ram_block1a1.ENA0 +wren_a => ram_block1a2.PORTAWE +wren_a => ram_block1a2.ENA0 +wren_a => ram_block1a3.PORTAWE +wren_a => ram_block1a3.ENA0 +wren_a => ram_block1a4.PORTAWE +wren_a => ram_block1a4.ENA0 +wren_a => ram_block1a5.PORTAWE +wren_a => ram_block1a5.ENA0 +wren_a => ram_block1a6.PORTAWE +wren_a => ram_block1a6.ENA0 +wren_a => ram_block1a7.PORTAWE +wren_a => ram_block1a7.ENA0 + + +|de0_nano_system|system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cmpr_ks8:almost_full_comparer +aeb <= aeb_result_wire[0].DB_MAX_OUTPUT_PORT_TYPE +dataa[0] => data_wire[0].IN0 +dataa[1] => data_wire[0].IN0 +dataa[2] => data_wire[1].IN0 +dataa[3] => data_wire[1].IN0 +dataa[4] => data_wire[2].IN0 +dataa[5] => data_wire[2].IN0 +dataa[6] => data_wire[3].IN0 +datab[0] => data_wire[0].IN1 +datab[1] => data_wire[0].IN1 +datab[2] => data_wire[1].IN1 +datab[3] => data_wire[1].IN1 +datab[4] => data_wire[2].IN1 +datab[5] => data_wire[2].IN1 +datab[6] => data_wire[3].IN1 + + +|de0_nano_system|system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cmpr_ks8:three_comparison +aeb <= aeb_result_wire[0].DB_MAX_OUTPUT_PORT_TYPE +dataa[0] => data_wire[0].IN0 +dataa[1] => data_wire[0].IN0 +dataa[2] => data_wire[1].IN0 +dataa[3] => data_wire[1].IN0 +dataa[4] => data_wire[2].IN0 +dataa[5] => data_wire[2].IN0 +dataa[6] => data_wire[3].IN0 +datab[0] => data_wire[0].IN1 +datab[1] => data_wire[0].IN1 +datab[2] => data_wire[1].IN1 +datab[3] => data_wire[1].IN1 +datab[4] => data_wire[2].IN1 +datab[5] => data_wire[2].IN1 +datab[6] => data_wire[3].IN1 + + +|de0_nano_system|system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_v9b:rd_ptr_msb +clock => counter_reg_bit[5].CLK +clock => counter_reg_bit[4].CLK +clock => counter_reg_bit[3].CLK +clock => counter_reg_bit[2].CLK +clock => counter_reg_bit[1].CLK +clock => counter_reg_bit[0].CLK +cnt_en => _.IN1 +q[0] <= counter_reg_bit[0].DB_MAX_OUTPUT_PORT_TYPE +q[1] <= counter_reg_bit[1].DB_MAX_OUTPUT_PORT_TYPE +q[2] <= counter_reg_bit[2].DB_MAX_OUTPUT_PORT_TYPE +q[3] <= counter_reg_bit[3].DB_MAX_OUTPUT_PORT_TYPE +q[4] <= counter_reg_bit[4].DB_MAX_OUTPUT_PORT_TYPE +q[5] <= counter_reg_bit[5].DB_MAX_OUTPUT_PORT_TYPE +sclr => _.IN0 +sclr => _.IN0 +sclr => _.IN0 + + +|de0_nano_system|system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_ca7:usedw_counter +clock => counter_reg_bit[6].CLK +clock => counter_reg_bit[5].CLK +clock => counter_reg_bit[4].CLK +clock => counter_reg_bit[3].CLK +clock => counter_reg_bit[2].CLK +clock => counter_reg_bit[1].CLK +clock => counter_reg_bit[0].CLK +cnt_en => _.IN1 +q[0] <= counter_reg_bit[0].DB_MAX_OUTPUT_PORT_TYPE +q[1] <= counter_reg_bit[1].DB_MAX_OUTPUT_PORT_TYPE +q[2] <= counter_reg_bit[2].DB_MAX_OUTPUT_PORT_TYPE +q[3] <= counter_reg_bit[3].DB_MAX_OUTPUT_PORT_TYPE +q[4] <= counter_reg_bit[4].DB_MAX_OUTPUT_PORT_TYPE +q[5] <= counter_reg_bit[5].DB_MAX_OUTPUT_PORT_TYPE +q[6] <= counter_reg_bit[6].DB_MAX_OUTPUT_PORT_TYPE +sclr => _.IN0 +sclr => _.IN0 +sclr => _.IN0 +updown => counter_comb_bita0.DATAB +updown => counter_comb_bita1.DATAB +updown => counter_comb_bita2.DATAB +updown => counter_comb_bita3.DATAB +updown => counter_comb_bita4.DATAB +updown => counter_comb_bita5.DATAB +updown => counter_comb_bita6.DATAB + + +|de0_nano_system|system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr +clock => counter_reg_bit[6].CLK +clock => counter_reg_bit[5].CLK +clock => counter_reg_bit[4].CLK +clock => counter_reg_bit[3].CLK +clock => counter_reg_bit[2].CLK +clock => counter_reg_bit[1].CLK +clock => counter_reg_bit[0].CLK +cnt_en => _.IN1 +q[0] <= counter_reg_bit[0].DB_MAX_OUTPUT_PORT_TYPE +q[1] <= counter_reg_bit[1].DB_MAX_OUTPUT_PORT_TYPE +q[2] <= counter_reg_bit[2].DB_MAX_OUTPUT_PORT_TYPE +q[3] <= counter_reg_bit[3].DB_MAX_OUTPUT_PORT_TYPE +q[4] <= counter_reg_bit[4].DB_MAX_OUTPUT_PORT_TYPE +q[5] <= counter_reg_bit[5].DB_MAX_OUTPUT_PORT_TYPE +q[6] <= counter_reg_bit[6].DB_MAX_OUTPUT_PORT_TYPE +sclr => _.IN0 +sclr => _.IN0 +sclr => _.IN0 + + +|de0_nano_system|system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer +clk => clk.IN2 +reset => reset.IN2 +transmit_data[0] => transmit_data[0].IN1 +transmit_data[1] => transmit_data[1].IN1 +transmit_data[2] => transmit_data[2].IN1 +transmit_data[3] => transmit_data[3].IN1 +transmit_data[4] => transmit_data[4].IN1 +transmit_data[5] => transmit_data[5].IN1 +transmit_data[6] => transmit_data[6].IN1 +transmit_data[7] => transmit_data[7].IN1 +transmit_data_en => comb.IN1 +fifo_write_space[0] <= fifo_write_space[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fifo_write_space[1] <= fifo_write_space[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fifo_write_space[2] <= fifo_write_space[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fifo_write_space[3] <= fifo_write_space[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fifo_write_space[4] <= fifo_write_space[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fifo_write_space[5] <= fifo_write_space[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fifo_write_space[6] <= fifo_write_space[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fifo_write_space[7] <= fifo_write_space[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE +serial_data_out <= serial_data_out~reg0.DB_MAX_OUTPUT_PORT_TYPE + + +|de0_nano_system|system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_rs232_counters:RS232_Out_Counters +clk => all_bits_transmitted~reg0.CLK +clk => bit_counter[0].CLK +clk => bit_counter[1].CLK +clk => bit_counter[2].CLK +clk => bit_counter[3].CLK +clk => baud_clock_falling_edge~reg0.CLK +clk => baud_clock_rising_edge~reg0.CLK +clk => baud_counter[0].CLK +clk => baud_counter[1].CLK +clk => baud_counter[2].CLK +clk => baud_counter[3].CLK +clk => baud_counter[4].CLK +clk => baud_counter[5].CLK +clk => baud_counter[6].CLK +clk => baud_counter[7].CLK +clk => baud_counter[8].CLK +clk => baud_counter[9].CLK +clk => baud_counter[10].CLK +clk => baud_counter[11].CLK +clk => baud_counter[12].CLK +clk => baud_counter[13].CLK +reset => baud_counter.OUTPUTSELECT +reset => baud_counter.OUTPUTSELECT +reset => baud_counter.OUTPUTSELECT +reset => baud_counter.OUTPUTSELECT +reset => baud_counter.OUTPUTSELECT +reset => baud_counter.OUTPUTSELECT +reset => baud_counter.OUTPUTSELECT +reset => baud_counter.OUTPUTSELECT +reset => baud_counter.OUTPUTSELECT +reset => baud_counter.OUTPUTSELECT +reset => baud_counter.OUTPUTSELECT +reset => baud_counter.OUTPUTSELECT +reset => baud_counter.OUTPUTSELECT +reset => baud_counter.OUTPUTSELECT +reset => baud_clock_rising_edge.OUTPUTSELECT +reset => baud_clock_falling_edge.OUTPUTSELECT +reset => bit_counter.OUTPUTSELECT +reset => bit_counter.OUTPUTSELECT +reset => bit_counter.OUTPUTSELECT +reset => bit_counter.OUTPUTSELECT +reset => all_bits_transmitted.OUTPUTSELECT +reset_counters => baud_counter.OUTPUTSELECT +reset_counters => baud_counter.OUTPUTSELECT +reset_counters => baud_counter.OUTPUTSELECT +reset_counters => baud_counter.OUTPUTSELECT +reset_counters => baud_counter.OUTPUTSELECT +reset_counters => baud_counter.OUTPUTSELECT +reset_counters => baud_counter.OUTPUTSELECT +reset_counters => baud_counter.OUTPUTSELECT +reset_counters => baud_counter.OUTPUTSELECT +reset_counters => baud_counter.OUTPUTSELECT +reset_counters => baud_counter.OUTPUTSELECT +reset_counters => baud_counter.OUTPUTSELECT +reset_counters => baud_counter.OUTPUTSELECT +reset_counters => baud_counter.OUTPUTSELECT +reset_counters => bit_counter.OUTPUTSELECT +reset_counters => bit_counter.OUTPUTSELECT +reset_counters => bit_counter.OUTPUTSELECT +reset_counters => bit_counter.OUTPUTSELECT +baud_clock_rising_edge <= baud_clock_rising_edge~reg0.DB_MAX_OUTPUT_PORT_TYPE +baud_clock_falling_edge <= baud_clock_falling_edge~reg0.DB_MAX_OUTPUT_PORT_TYPE +all_bits_transmitted <= all_bits_transmitted~reg0.DB_MAX_OUTPUT_PORT_TYPE + + +|de0_nano_system|system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO +clk => clk.IN1 +reset => reset.IN1 +write_en => write_en.IN1 +write_data[0] => write_data[0].IN1 +write_data[1] => write_data[1].IN1 +write_data[2] => write_data[2].IN1 +write_data[3] => write_data[3].IN1 +write_data[4] => write_data[4].IN1 +write_data[5] => write_data[5].IN1 +write_data[6] => write_data[6].IN1 +write_data[7] => write_data[7].IN1 +read_en => read_en.IN1 +fifo_is_empty <= scfifo:Sync_FIFO.empty +fifo_is_full <= scfifo:Sync_FIFO.full +words_used[0] <= scfifo:Sync_FIFO.usedw +words_used[1] <= scfifo:Sync_FIFO.usedw +words_used[2] <= scfifo:Sync_FIFO.usedw +words_used[3] <= scfifo:Sync_FIFO.usedw +words_used[4] <= scfifo:Sync_FIFO.usedw +words_used[5] <= scfifo:Sync_FIFO.usedw +words_used[6] <= scfifo:Sync_FIFO.usedw +read_data[0] <= scfifo:Sync_FIFO.q +read_data[1] <= scfifo:Sync_FIFO.q +read_data[2] <= scfifo:Sync_FIFO.q +read_data[3] <= scfifo:Sync_FIFO.q +read_data[4] <= scfifo:Sync_FIFO.q +read_data[5] <= scfifo:Sync_FIFO.q +read_data[6] <= scfifo:Sync_FIFO.q +read_data[7] <= scfifo:Sync_FIFO.q + + +|de0_nano_system|system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO +data[0] => scfifo_a341:auto_generated.data[0] +data[1] => scfifo_a341:auto_generated.data[1] +data[2] => scfifo_a341:auto_generated.data[2] +data[3] => scfifo_a341:auto_generated.data[3] +data[4] => scfifo_a341:auto_generated.data[4] +data[5] => scfifo_a341:auto_generated.data[5] +data[6] => scfifo_a341:auto_generated.data[6] +data[7] => scfifo_a341:auto_generated.data[7] +q[0] <= scfifo_a341:auto_generated.q[0] +q[1] <= scfifo_a341:auto_generated.q[1] +q[2] <= scfifo_a341:auto_generated.q[2] +q[3] <= scfifo_a341:auto_generated.q[3] +q[4] <= scfifo_a341:auto_generated.q[4] +q[5] <= scfifo_a341:auto_generated.q[5] +q[6] <= scfifo_a341:auto_generated.q[6] +q[7] <= scfifo_a341:auto_generated.q[7] +wrreq => scfifo_a341:auto_generated.wrreq +rdreq => scfifo_a341:auto_generated.rdreq +clock => scfifo_a341:auto_generated.clock +aclr => ~NO_FANOUT~ +sclr => scfifo_a341:auto_generated.sclr +empty <= scfifo_a341:auto_generated.empty +full <= scfifo_a341:auto_generated.full +almost_full <= +almost_empty <= +usedw[0] <= scfifo_a341:auto_generated.usedw[0] +usedw[1] <= scfifo_a341:auto_generated.usedw[1] +usedw[2] <= scfifo_a341:auto_generated.usedw[2] +usedw[3] <= scfifo_a341:auto_generated.usedw[3] +usedw[4] <= scfifo_a341:auto_generated.usedw[4] +usedw[5] <= scfifo_a341:auto_generated.usedw[5] +usedw[6] <= scfifo_a341:auto_generated.usedw[6] + + +|de0_nano_system|system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated +clock => a_dpfifo_tq31:dpfifo.clock +data[0] => a_dpfifo_tq31:dpfifo.data[0] +data[1] => a_dpfifo_tq31:dpfifo.data[1] +data[2] => a_dpfifo_tq31:dpfifo.data[2] +data[3] => a_dpfifo_tq31:dpfifo.data[3] +data[4] => a_dpfifo_tq31:dpfifo.data[4] +data[5] => a_dpfifo_tq31:dpfifo.data[5] +data[6] => a_dpfifo_tq31:dpfifo.data[6] +data[7] => a_dpfifo_tq31:dpfifo.data[7] +empty <= a_dpfifo_tq31:dpfifo.empty +full <= a_dpfifo_tq31:dpfifo.full +q[0] <= a_dpfifo_tq31:dpfifo.q[0] +q[1] <= a_dpfifo_tq31:dpfifo.q[1] +q[2] <= a_dpfifo_tq31:dpfifo.q[2] +q[3] <= a_dpfifo_tq31:dpfifo.q[3] +q[4] <= a_dpfifo_tq31:dpfifo.q[4] +q[5] <= a_dpfifo_tq31:dpfifo.q[5] +q[6] <= a_dpfifo_tq31:dpfifo.q[6] +q[7] <= a_dpfifo_tq31:dpfifo.q[7] +rdreq => a_dpfifo_tq31:dpfifo.rreq +sclr => a_dpfifo_tq31:dpfifo.sclr +usedw[0] <= a_dpfifo_tq31:dpfifo.usedw[0] +usedw[1] <= a_dpfifo_tq31:dpfifo.usedw[1] +usedw[2] <= a_dpfifo_tq31:dpfifo.usedw[2] +usedw[3] <= a_dpfifo_tq31:dpfifo.usedw[3] +usedw[4] <= a_dpfifo_tq31:dpfifo.usedw[4] +usedw[5] <= a_dpfifo_tq31:dpfifo.usedw[5] +usedw[6] <= a_dpfifo_tq31:dpfifo.usedw[6] +wrreq => a_dpfifo_tq31:dpfifo.wreq + + +|de0_nano_system|system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo +clock => altsyncram_je81:FIFOram.clock0 +clock => cntr_v9b:rd_ptr_msb.clock +clock => cntr_ca7:usedw_counter.clock +clock => cntr_0ab:wr_ptr.clock +clock => empty_dff.CLK +clock => full_dff.CLK +clock => low_addressa[6].CLK +clock => low_addressa[5].CLK +clock => low_addressa[4].CLK +clock => low_addressa[3].CLK +clock => low_addressa[2].CLK +clock => low_addressa[1].CLK +clock => low_addressa[0].CLK +clock => rd_ptr_lsb.CLK +clock => usedw_is_0_dff.CLK +clock => usedw_is_1_dff.CLK +clock => usedw_is_2_dff.CLK +clock => wrreq_delaya[1].CLK +clock => wrreq_delaya[0].CLK +data[0] => altsyncram_je81:FIFOram.data_a[0] +data[1] => altsyncram_je81:FIFOram.data_a[1] +data[2] => altsyncram_je81:FIFOram.data_a[2] +data[3] => altsyncram_je81:FIFOram.data_a[3] +data[4] => altsyncram_je81:FIFOram.data_a[4] +data[5] => altsyncram_je81:FIFOram.data_a[5] +data[6] => altsyncram_je81:FIFOram.data_a[6] +data[7] => altsyncram_je81:FIFOram.data_a[7] +empty <= empty_out.DB_MAX_OUTPUT_PORT_TYPE +full <= full_dff.DB_MAX_OUTPUT_PORT_TYPE +q[0] <= altsyncram_je81:FIFOram.q_b[0] +q[1] <= altsyncram_je81:FIFOram.q_b[1] +q[2] <= altsyncram_je81:FIFOram.q_b[2] +q[3] <= altsyncram_je81:FIFOram.q_b[3] +q[4] <= altsyncram_je81:FIFOram.q_b[4] +q[5] <= altsyncram_je81:FIFOram.q_b[5] +q[6] <= altsyncram_je81:FIFOram.q_b[6] +q[7] <= altsyncram_je81:FIFOram.q_b[7] +rreq => _.IN0 +rreq => _.IN1 +rreq => _.IN1 +rreq => _.IN1 +rreq => _.IN1 +rreq => _.IN1 +rreq => _.IN0 +rreq => _.IN1 +rreq => _.IN1 +rreq => _.IN0 +rreq => _.IN1 +rreq => _.IN0 +rreq => _.IN0 +rreq => _.IN0 +rreq => _.IN0 +rreq => _.IN0 +rreq => _.IN0 +rreq => _.IN0 +rreq => _.IN0 +rreq => rd_ptr_lsb.IN0 +rreq => _.IN0 +rreq => _.IN0 +rreq => ram_read_address[6].IN0 +rreq => ram_read_address[5].IN0 +rreq => ram_read_address[4].IN0 +rreq => ram_read_address[3].IN0 +rreq => ram_read_address[2].IN0 +rreq => ram_read_address[1].IN0 +rreq => ram_read_address[0].IN0 +sclr => _.IN0 +sclr => _.IN0 +sclr => _.IN0 +sclr => _.IN0 +sclr => rd_ptr_lsb.IN1 +sclr => _.IN0 +sclr => _.IN0 +sclr => cntr_v9b:rd_ptr_msb.sclr +sclr => cntr_ca7:usedw_counter.sclr +sclr => cntr_0ab:wr_ptr.sclr +sclr => _.IN0 +sclr => usedw_will_be_1.IN0 +sclr => usedw_will_be_2.IN0 +usedw[0] <= cntr_ca7:usedw_counter.q[0] +usedw[1] <= cntr_ca7:usedw_counter.q[1] +usedw[2] <= cntr_ca7:usedw_counter.q[2] +usedw[3] <= cntr_ca7:usedw_counter.q[3] +usedw[4] <= cntr_ca7:usedw_counter.q[4] +usedw[5] <= cntr_ca7:usedw_counter.q[5] +usedw[6] <= cntr_ca7:usedw_counter.q[6] +wreq => altsyncram_je81:FIFOram.wren_a +wreq => _.IN0 +wreq => _.IN0 +wreq => wrreq_delaya[1].IN1 +wreq => _.IN0 +wreq => cntr_ca7:usedw_counter.updown +wreq => cntr_0ab:wr_ptr.cnt_en +wreq => _.IN0 +wreq => _.IN0 +wreq => _.IN0 +wreq => _.IN1 +wreq => _.IN0 +wreq => _.IN0 +wreq => _.IN1 +wreq => _.IN0 +wreq => wait_state.IN1 + + +|de0_nano_system|system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram +address_a[0] => ram_block1a0.PORTAADDR +address_a[0] => ram_block1a1.PORTAADDR +address_a[0] => ram_block1a2.PORTAADDR +address_a[0] => ram_block1a3.PORTAADDR +address_a[0] => ram_block1a4.PORTAADDR +address_a[0] => ram_block1a5.PORTAADDR +address_a[0] => ram_block1a6.PORTAADDR +address_a[0] => ram_block1a7.PORTAADDR +address_a[1] => ram_block1a0.PORTAADDR1 +address_a[1] => ram_block1a1.PORTAADDR1 +address_a[1] => ram_block1a2.PORTAADDR1 +address_a[1] => ram_block1a3.PORTAADDR1 +address_a[1] => ram_block1a4.PORTAADDR1 +address_a[1] => ram_block1a5.PORTAADDR1 +address_a[1] => ram_block1a6.PORTAADDR1 +address_a[1] => ram_block1a7.PORTAADDR1 +address_a[2] => ram_block1a0.PORTAADDR2 +address_a[2] => ram_block1a1.PORTAADDR2 +address_a[2] => ram_block1a2.PORTAADDR2 +address_a[2] => ram_block1a3.PORTAADDR2 +address_a[2] => ram_block1a4.PORTAADDR2 +address_a[2] => ram_block1a5.PORTAADDR2 +address_a[2] => ram_block1a6.PORTAADDR2 +address_a[2] => ram_block1a7.PORTAADDR2 +address_a[3] => ram_block1a0.PORTAADDR3 +address_a[3] => ram_block1a1.PORTAADDR3 +address_a[3] => ram_block1a2.PORTAADDR3 +address_a[3] => ram_block1a3.PORTAADDR3 +address_a[3] => ram_block1a4.PORTAADDR3 +address_a[3] => ram_block1a5.PORTAADDR3 +address_a[3] => ram_block1a6.PORTAADDR3 +address_a[3] => ram_block1a7.PORTAADDR3 +address_a[4] => ram_block1a0.PORTAADDR4 +address_a[4] => ram_block1a1.PORTAADDR4 +address_a[4] => ram_block1a2.PORTAADDR4 +address_a[4] => ram_block1a3.PORTAADDR4 +address_a[4] => ram_block1a4.PORTAADDR4 +address_a[4] => ram_block1a5.PORTAADDR4 +address_a[4] => ram_block1a6.PORTAADDR4 +address_a[4] => ram_block1a7.PORTAADDR4 +address_a[5] => ram_block1a0.PORTAADDR5 +address_a[5] => ram_block1a1.PORTAADDR5 +address_a[5] => ram_block1a2.PORTAADDR5 +address_a[5] => ram_block1a3.PORTAADDR5 +address_a[5] => ram_block1a4.PORTAADDR5 +address_a[5] => ram_block1a5.PORTAADDR5 +address_a[5] => ram_block1a6.PORTAADDR5 +address_a[5] => ram_block1a7.PORTAADDR5 +address_a[6] => ram_block1a0.PORTAADDR6 +address_a[6] => ram_block1a1.PORTAADDR6 +address_a[6] => ram_block1a2.PORTAADDR6 +address_a[6] => ram_block1a3.PORTAADDR6 +address_a[6] => ram_block1a4.PORTAADDR6 +address_a[6] => ram_block1a5.PORTAADDR6 +address_a[6] => ram_block1a6.PORTAADDR6 +address_a[6] => ram_block1a7.PORTAADDR6 +address_b[0] => ram_block1a0.PORTBADDR +address_b[0] => ram_block1a1.PORTBADDR +address_b[0] => ram_block1a2.PORTBADDR +address_b[0] => ram_block1a3.PORTBADDR +address_b[0] => ram_block1a4.PORTBADDR +address_b[0] => ram_block1a5.PORTBADDR +address_b[0] => ram_block1a6.PORTBADDR +address_b[0] => ram_block1a7.PORTBADDR +address_b[1] => ram_block1a0.PORTBADDR1 +address_b[1] => ram_block1a1.PORTBADDR1 +address_b[1] => ram_block1a2.PORTBADDR1 +address_b[1] => ram_block1a3.PORTBADDR1 +address_b[1] => ram_block1a4.PORTBADDR1 +address_b[1] => ram_block1a5.PORTBADDR1 +address_b[1] => ram_block1a6.PORTBADDR1 +address_b[1] => ram_block1a7.PORTBADDR1 +address_b[2] => ram_block1a0.PORTBADDR2 +address_b[2] => ram_block1a1.PORTBADDR2 +address_b[2] => ram_block1a2.PORTBADDR2 +address_b[2] => ram_block1a3.PORTBADDR2 +address_b[2] => ram_block1a4.PORTBADDR2 +address_b[2] => ram_block1a5.PORTBADDR2 +address_b[2] => ram_block1a6.PORTBADDR2 +address_b[2] => ram_block1a7.PORTBADDR2 +address_b[3] => ram_block1a0.PORTBADDR3 +address_b[3] => ram_block1a1.PORTBADDR3 +address_b[3] => ram_block1a2.PORTBADDR3 +address_b[3] => ram_block1a3.PORTBADDR3 +address_b[3] => ram_block1a4.PORTBADDR3 +address_b[3] => ram_block1a5.PORTBADDR3 +address_b[3] => ram_block1a6.PORTBADDR3 +address_b[3] => ram_block1a7.PORTBADDR3 +address_b[4] => ram_block1a0.PORTBADDR4 +address_b[4] => ram_block1a1.PORTBADDR4 +address_b[4] => ram_block1a2.PORTBADDR4 +address_b[4] => ram_block1a3.PORTBADDR4 +address_b[4] => ram_block1a4.PORTBADDR4 +address_b[4] => ram_block1a5.PORTBADDR4 +address_b[4] => ram_block1a6.PORTBADDR4 +address_b[4] => ram_block1a7.PORTBADDR4 +address_b[5] => ram_block1a0.PORTBADDR5 +address_b[5] => ram_block1a1.PORTBADDR5 +address_b[5] => ram_block1a2.PORTBADDR5 +address_b[5] => ram_block1a3.PORTBADDR5 +address_b[5] => ram_block1a4.PORTBADDR5 +address_b[5] => ram_block1a5.PORTBADDR5 +address_b[5] => ram_block1a6.PORTBADDR5 +address_b[5] => ram_block1a7.PORTBADDR5 +address_b[6] => ram_block1a0.PORTBADDR6 +address_b[6] => ram_block1a1.PORTBADDR6 +address_b[6] => ram_block1a2.PORTBADDR6 +address_b[6] => ram_block1a3.PORTBADDR6 +address_b[6] => ram_block1a4.PORTBADDR6 +address_b[6] => ram_block1a5.PORTBADDR6 +address_b[6] => ram_block1a6.PORTBADDR6 +address_b[6] => ram_block1a7.PORTBADDR6 +clock0 => ram_block1a0.CLK0 +clock0 => ram_block1a0.CLK1 +clock0 => ram_block1a1.CLK0 +clock0 => ram_block1a1.CLK1 +clock0 => ram_block1a2.CLK0 +clock0 => ram_block1a2.CLK1 +clock0 => ram_block1a3.CLK0 +clock0 => ram_block1a3.CLK1 +clock0 => ram_block1a4.CLK0 +clock0 => ram_block1a4.CLK1 +clock0 => ram_block1a5.CLK0 +clock0 => ram_block1a5.CLK1 +clock0 => ram_block1a6.CLK0 +clock0 => ram_block1a6.CLK1 +clock0 => ram_block1a7.CLK0 +clock0 => ram_block1a7.CLK1 +data_a[0] => ram_block1a0.PORTADATAIN +data_a[1] => ram_block1a1.PORTADATAIN +data_a[2] => ram_block1a2.PORTADATAIN +data_a[3] => ram_block1a3.PORTADATAIN +data_a[4] => ram_block1a4.PORTADATAIN +data_a[5] => ram_block1a5.PORTADATAIN +data_a[6] => ram_block1a6.PORTADATAIN +data_a[7] => ram_block1a7.PORTADATAIN +q_b[0] <= ram_block1a0.PORTBDATAOUT +q_b[1] <= ram_block1a1.PORTBDATAOUT +q_b[2] <= ram_block1a2.PORTBDATAOUT +q_b[3] <= ram_block1a3.PORTBDATAOUT +q_b[4] <= ram_block1a4.PORTBDATAOUT +q_b[5] <= ram_block1a5.PORTBDATAOUT +q_b[6] <= ram_block1a6.PORTBDATAOUT +q_b[7] <= ram_block1a7.PORTBDATAOUT +wren_a => ram_block1a0.PORTAWE +wren_a => ram_block1a0.ENA0 +wren_a => ram_block1a1.PORTAWE +wren_a => ram_block1a1.ENA0 +wren_a => ram_block1a2.PORTAWE +wren_a => ram_block1a2.ENA0 +wren_a => ram_block1a3.PORTAWE +wren_a => ram_block1a3.ENA0 +wren_a => ram_block1a4.PORTAWE +wren_a => ram_block1a4.ENA0 +wren_a => ram_block1a5.PORTAWE +wren_a => ram_block1a5.ENA0 +wren_a => ram_block1a6.PORTAWE +wren_a => ram_block1a6.ENA0 +wren_a => ram_block1a7.PORTAWE +wren_a => ram_block1a7.ENA0 + + +|de0_nano_system|system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cmpr_ks8:almost_full_comparer +aeb <= aeb_result_wire[0].DB_MAX_OUTPUT_PORT_TYPE +dataa[0] => data_wire[0].IN0 +dataa[1] => data_wire[0].IN0 +dataa[2] => data_wire[1].IN0 +dataa[3] => data_wire[1].IN0 +dataa[4] => data_wire[2].IN0 +dataa[5] => data_wire[2].IN0 +dataa[6] => data_wire[3].IN0 +datab[0] => data_wire[0].IN1 +datab[1] => data_wire[0].IN1 +datab[2] => data_wire[1].IN1 +datab[3] => data_wire[1].IN1 +datab[4] => data_wire[2].IN1 +datab[5] => data_wire[2].IN1 +datab[6] => data_wire[3].IN1 + + +|de0_nano_system|system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cmpr_ks8:three_comparison +aeb <= aeb_result_wire[0].DB_MAX_OUTPUT_PORT_TYPE +dataa[0] => data_wire[0].IN0 +dataa[1] => data_wire[0].IN0 +dataa[2] => data_wire[1].IN0 +dataa[3] => data_wire[1].IN0 +dataa[4] => data_wire[2].IN0 +dataa[5] => data_wire[2].IN0 +dataa[6] => data_wire[3].IN0 +datab[0] => data_wire[0].IN1 +datab[1] => data_wire[0].IN1 +datab[2] => data_wire[1].IN1 +datab[3] => data_wire[1].IN1 +datab[4] => data_wire[2].IN1 +datab[5] => data_wire[2].IN1 +datab[6] => data_wire[3].IN1 + + +|de0_nano_system|system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_v9b:rd_ptr_msb +clock => counter_reg_bit[5].CLK +clock => counter_reg_bit[4].CLK +clock => counter_reg_bit[3].CLK +clock => counter_reg_bit[2].CLK +clock => counter_reg_bit[1].CLK +clock => counter_reg_bit[0].CLK +cnt_en => _.IN1 +q[0] <= counter_reg_bit[0].DB_MAX_OUTPUT_PORT_TYPE +q[1] <= counter_reg_bit[1].DB_MAX_OUTPUT_PORT_TYPE +q[2] <= counter_reg_bit[2].DB_MAX_OUTPUT_PORT_TYPE +q[3] <= counter_reg_bit[3].DB_MAX_OUTPUT_PORT_TYPE +q[4] <= counter_reg_bit[4].DB_MAX_OUTPUT_PORT_TYPE +q[5] <= counter_reg_bit[5].DB_MAX_OUTPUT_PORT_TYPE +sclr => _.IN0 +sclr => _.IN0 +sclr => _.IN0 + + +|de0_nano_system|system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_ca7:usedw_counter +clock => counter_reg_bit[6].CLK +clock => counter_reg_bit[5].CLK +clock => counter_reg_bit[4].CLK +clock => counter_reg_bit[3].CLK +clock => counter_reg_bit[2].CLK +clock => counter_reg_bit[1].CLK +clock => counter_reg_bit[0].CLK +cnt_en => _.IN1 +q[0] <= counter_reg_bit[0].DB_MAX_OUTPUT_PORT_TYPE +q[1] <= counter_reg_bit[1].DB_MAX_OUTPUT_PORT_TYPE +q[2] <= counter_reg_bit[2].DB_MAX_OUTPUT_PORT_TYPE +q[3] <= counter_reg_bit[3].DB_MAX_OUTPUT_PORT_TYPE +q[4] <= counter_reg_bit[4].DB_MAX_OUTPUT_PORT_TYPE +q[5] <= counter_reg_bit[5].DB_MAX_OUTPUT_PORT_TYPE +q[6] <= counter_reg_bit[6].DB_MAX_OUTPUT_PORT_TYPE +sclr => _.IN0 +sclr => _.IN0 +sclr => _.IN0 +updown => counter_comb_bita0.DATAB +updown => counter_comb_bita1.DATAB +updown => counter_comb_bita2.DATAB +updown => counter_comb_bita3.DATAB +updown => counter_comb_bita4.DATAB +updown => counter_comb_bita5.DATAB +updown => counter_comb_bita6.DATAB + + +|de0_nano_system|system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr +clock => counter_reg_bit[6].CLK +clock => counter_reg_bit[5].CLK +clock => counter_reg_bit[4].CLK +clock => counter_reg_bit[3].CLK +clock => counter_reg_bit[2].CLK +clock => counter_reg_bit[1].CLK +clock => counter_reg_bit[0].CLK +cnt_en => _.IN1 +q[0] <= counter_reg_bit[0].DB_MAX_OUTPUT_PORT_TYPE +q[1] <= counter_reg_bit[1].DB_MAX_OUTPUT_PORT_TYPE +q[2] <= counter_reg_bit[2].DB_MAX_OUTPUT_PORT_TYPE +q[3] <= counter_reg_bit[3].DB_MAX_OUTPUT_PORT_TYPE +q[4] <= counter_reg_bit[4].DB_MAX_OUTPUT_PORT_TYPE +q[5] <= counter_reg_bit[5].DB_MAX_OUTPUT_PORT_TYPE +q[6] <= counter_reg_bit[6].DB_MAX_OUTPUT_PORT_TYPE +sclr => _.IN0 +sclr => _.IN0 +sclr => _.IN0 + + +|de0_nano_system|system:inst_cpu|altera_merlin_master_translator:cpu_instruction_master_translator +clk => ~NO_FANOUT~ +reset => ~NO_FANOUT~ +uav_write <= +uav_read <= av_read.DB_MAX_OUTPUT_PORT_TYPE +uav_address[0] <= av_address[0].DB_MAX_OUTPUT_PORT_TYPE +uav_address[1] <= av_address[1].DB_MAX_OUTPUT_PORT_TYPE +uav_address[2] <= av_address[2].DB_MAX_OUTPUT_PORT_TYPE +uav_address[3] <= av_address[3].DB_MAX_OUTPUT_PORT_TYPE +uav_address[4] <= av_address[4].DB_MAX_OUTPUT_PORT_TYPE +uav_address[5] <= av_address[5].DB_MAX_OUTPUT_PORT_TYPE +uav_address[6] <= av_address[6].DB_MAX_OUTPUT_PORT_TYPE +uav_address[7] <= av_address[7].DB_MAX_OUTPUT_PORT_TYPE +uav_address[8] <= av_address[8].DB_MAX_OUTPUT_PORT_TYPE +uav_address[9] <= av_address[9].DB_MAX_OUTPUT_PORT_TYPE +uav_address[10] <= av_address[10].DB_MAX_OUTPUT_PORT_TYPE +uav_address[11] <= av_address[11].DB_MAX_OUTPUT_PORT_TYPE +uav_address[12] <= av_address[12].DB_MAX_OUTPUT_PORT_TYPE +uav_address[13] <= av_address[13].DB_MAX_OUTPUT_PORT_TYPE +uav_address[14] <= av_address[14].DB_MAX_OUTPUT_PORT_TYPE +uav_address[15] <= av_address[15].DB_MAX_OUTPUT_PORT_TYPE +uav_address[16] <= av_address[16].DB_MAX_OUTPUT_PORT_TYPE +uav_address[17] <= av_address[17].DB_MAX_OUTPUT_PORT_TYPE +uav_address[18] <= av_address[18].DB_MAX_OUTPUT_PORT_TYPE +uav_address[19] <= av_address[19].DB_MAX_OUTPUT_PORT_TYPE +uav_address[20] <= av_address[20].DB_MAX_OUTPUT_PORT_TYPE +uav_address[21] <= av_address[21].DB_MAX_OUTPUT_PORT_TYPE +uav_address[22] <= av_address[22].DB_MAX_OUTPUT_PORT_TYPE +uav_address[23] <= av_address[23].DB_MAX_OUTPUT_PORT_TYPE +uav_address[24] <= av_address[24].DB_MAX_OUTPUT_PORT_TYPE +uav_address[25] <= av_address[25].DB_MAX_OUTPUT_PORT_TYPE +uav_burstcount[0] <= +uav_burstcount[1] <= +uav_burstcount[2] <= +uav_byteenable[0] <= av_byteenable[0].DB_MAX_OUTPUT_PORT_TYPE +uav_byteenable[1] <= av_byteenable[1].DB_MAX_OUTPUT_PORT_TYPE +uav_byteenable[2] <= av_byteenable[2].DB_MAX_OUTPUT_PORT_TYPE +uav_byteenable[3] <= av_byteenable[3].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[0] <= av_writedata[0].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[1] <= av_writedata[1].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[2] <= av_writedata[2].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[3] <= av_writedata[3].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[4] <= av_writedata[4].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[5] <= av_writedata[5].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[6] <= av_writedata[6].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[7] <= av_writedata[7].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[8] <= av_writedata[8].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[9] <= av_writedata[9].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[10] <= av_writedata[10].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[11] <= av_writedata[11].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[12] <= av_writedata[12].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[13] <= av_writedata[13].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[14] <= av_writedata[14].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[15] <= av_writedata[15].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[16] <= av_writedata[16].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[17] <= av_writedata[17].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[18] <= av_writedata[18].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[19] <= av_writedata[19].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[20] <= av_writedata[20].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[21] <= av_writedata[21].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[22] <= av_writedata[22].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[23] <= av_writedata[23].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[24] <= av_writedata[24].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[25] <= av_writedata[25].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[26] <= av_writedata[26].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[27] <= av_writedata[27].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[28] <= av_writedata[28].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[29] <= av_writedata[29].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[30] <= av_writedata[30].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[31] <= av_writedata[31].DB_MAX_OUTPUT_PORT_TYPE +uav_lock <= av_lock.DB_MAX_OUTPUT_PORT_TYPE +uav_debugaccess <= av_debugaccess.DB_MAX_OUTPUT_PORT_TYPE +uav_clken <= av_clken.DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[0] => av_readdata[0].DATAIN +uav_readdata[1] => av_readdata[1].DATAIN +uav_readdata[2] => av_readdata[2].DATAIN +uav_readdata[3] => av_readdata[3].DATAIN +uav_readdata[4] => av_readdata[4].DATAIN +uav_readdata[5] => av_readdata[5].DATAIN +uav_readdata[6] => av_readdata[6].DATAIN +uav_readdata[7] => av_readdata[7].DATAIN +uav_readdata[8] => av_readdata[8].DATAIN +uav_readdata[9] => av_readdata[9].DATAIN +uav_readdata[10] => av_readdata[10].DATAIN +uav_readdata[11] => av_readdata[11].DATAIN +uav_readdata[12] => av_readdata[12].DATAIN +uav_readdata[13] => av_readdata[13].DATAIN +uav_readdata[14] => av_readdata[14].DATAIN +uav_readdata[15] => av_readdata[15].DATAIN +uav_readdata[16] => av_readdata[16].DATAIN +uav_readdata[17] => av_readdata[17].DATAIN +uav_readdata[18] => av_readdata[18].DATAIN +uav_readdata[19] => av_readdata[19].DATAIN +uav_readdata[20] => av_readdata[20].DATAIN +uav_readdata[21] => av_readdata[21].DATAIN +uav_readdata[22] => av_readdata[22].DATAIN +uav_readdata[23] => av_readdata[23].DATAIN +uav_readdata[24] => av_readdata[24].DATAIN +uav_readdata[25] => av_readdata[25].DATAIN +uav_readdata[26] => av_readdata[26].DATAIN +uav_readdata[27] => av_readdata[27].DATAIN +uav_readdata[28] => av_readdata[28].DATAIN +uav_readdata[29] => av_readdata[29].DATAIN +uav_readdata[30] => av_readdata[30].DATAIN +uav_readdata[31] => av_readdata[31].DATAIN +uav_readdatavalid => av_readdatavalid.DATAIN +uav_waitrequest => av_waitrequest.DATAIN +av_write => ~NO_FANOUT~ +av_read => uav_read.DATAIN +av_address[0] => uav_address[0].DATAIN +av_address[1] => uav_address[1].DATAIN +av_address[2] => uav_address[2].DATAIN +av_address[3] => uav_address[3].DATAIN +av_address[4] => uav_address[4].DATAIN +av_address[5] => uav_address[5].DATAIN +av_address[6] => uav_address[6].DATAIN +av_address[7] => uav_address[7].DATAIN +av_address[8] => uav_address[8].DATAIN +av_address[9] => uav_address[9].DATAIN +av_address[10] => uav_address[10].DATAIN +av_address[11] => uav_address[11].DATAIN +av_address[12] => uav_address[12].DATAIN +av_address[13] => uav_address[13].DATAIN +av_address[14] => uav_address[14].DATAIN +av_address[15] => uav_address[15].DATAIN +av_address[16] => uav_address[16].DATAIN +av_address[17] => uav_address[17].DATAIN +av_address[18] => uav_address[18].DATAIN +av_address[19] => uav_address[19].DATAIN +av_address[20] => uav_address[20].DATAIN +av_address[21] => uav_address[21].DATAIN +av_address[22] => uav_address[22].DATAIN +av_address[23] => uav_address[23].DATAIN +av_address[24] => uav_address[24].DATAIN +av_address[25] => uav_address[25].DATAIN +av_byteenable[0] => uav_byteenable[0].DATAIN +av_byteenable[1] => uav_byteenable[1].DATAIN +av_byteenable[2] => uav_byteenable[2].DATAIN +av_byteenable[3] => uav_byteenable[3].DATAIN +av_burstcount[0] => ~NO_FANOUT~ +av_writedata[0] => uav_writedata[0].DATAIN +av_writedata[1] => uav_writedata[1].DATAIN +av_writedata[2] => uav_writedata[2].DATAIN +av_writedata[3] => uav_writedata[3].DATAIN +av_writedata[4] => uav_writedata[4].DATAIN +av_writedata[5] => uav_writedata[5].DATAIN +av_writedata[6] => uav_writedata[6].DATAIN +av_writedata[7] => uav_writedata[7].DATAIN +av_writedata[8] => uav_writedata[8].DATAIN +av_writedata[9] => uav_writedata[9].DATAIN +av_writedata[10] => uav_writedata[10].DATAIN +av_writedata[11] => uav_writedata[11].DATAIN +av_writedata[12] => uav_writedata[12].DATAIN +av_writedata[13] => uav_writedata[13].DATAIN +av_writedata[14] => uav_writedata[14].DATAIN +av_writedata[15] => uav_writedata[15].DATAIN +av_writedata[16] => uav_writedata[16].DATAIN +av_writedata[17] => uav_writedata[17].DATAIN +av_writedata[18] => uav_writedata[18].DATAIN +av_writedata[19] => uav_writedata[19].DATAIN +av_writedata[20] => uav_writedata[20].DATAIN +av_writedata[21] => uav_writedata[21].DATAIN +av_writedata[22] => uav_writedata[22].DATAIN +av_writedata[23] => uav_writedata[23].DATAIN +av_writedata[24] => uav_writedata[24].DATAIN +av_writedata[25] => uav_writedata[25].DATAIN +av_writedata[26] => uav_writedata[26].DATAIN +av_writedata[27] => uav_writedata[27].DATAIN +av_writedata[28] => uav_writedata[28].DATAIN +av_writedata[29] => uav_writedata[29].DATAIN +av_writedata[30] => uav_writedata[30].DATAIN +av_writedata[31] => uav_writedata[31].DATAIN +av_begintransfer => ~NO_FANOUT~ +av_beginbursttransfer => ~NO_FANOUT~ +av_lock => uav_lock.DATAIN +av_chipselect => ~NO_FANOUT~ +av_debugaccess => uav_debugaccess.DATAIN +av_clken => uav_clken.DATAIN +av_readdata[0] <= uav_readdata[0].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[1] <= uav_readdata[1].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[2] <= uav_readdata[2].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[3] <= uav_readdata[3].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[4] <= uav_readdata[4].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[5] <= uav_readdata[5].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[6] <= uav_readdata[6].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[7] <= uav_readdata[7].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[8] <= uav_readdata[8].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[9] <= uav_readdata[9].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[10] <= uav_readdata[10].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[11] <= uav_readdata[11].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[12] <= uav_readdata[12].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[13] <= uav_readdata[13].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[14] <= uav_readdata[14].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[15] <= uav_readdata[15].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[16] <= uav_readdata[16].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[17] <= uav_readdata[17].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[18] <= uav_readdata[18].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[19] <= uav_readdata[19].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[20] <= uav_readdata[20].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[21] <= uav_readdata[21].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[22] <= uav_readdata[22].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[23] <= uav_readdata[23].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[24] <= uav_readdata[24].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[25] <= uav_readdata[25].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[26] <= uav_readdata[26].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[27] <= uav_readdata[27].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[28] <= uav_readdata[28].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[29] <= uav_readdata[29].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[30] <= uav_readdata[30].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[31] <= uav_readdata[31].DB_MAX_OUTPUT_PORT_TYPE +av_readdatavalid <= uav_readdatavalid.DB_MAX_OUTPUT_PORT_TYPE +av_waitrequest <= uav_waitrequest.DB_MAX_OUTPUT_PORT_TYPE + + +|de0_nano_system|system:inst_cpu|altera_merlin_master_translator:cpu_data_master_translator +clk => ~NO_FANOUT~ +reset => ~NO_FANOUT~ +uav_write <= av_write.DB_MAX_OUTPUT_PORT_TYPE +uav_read <= av_read.DB_MAX_OUTPUT_PORT_TYPE +uav_address[0] <= av_address[0].DB_MAX_OUTPUT_PORT_TYPE +uav_address[1] <= av_address[1].DB_MAX_OUTPUT_PORT_TYPE +uav_address[2] <= av_address[2].DB_MAX_OUTPUT_PORT_TYPE +uav_address[3] <= av_address[3].DB_MAX_OUTPUT_PORT_TYPE +uav_address[4] <= av_address[4].DB_MAX_OUTPUT_PORT_TYPE +uav_address[5] <= av_address[5].DB_MAX_OUTPUT_PORT_TYPE +uav_address[6] <= av_address[6].DB_MAX_OUTPUT_PORT_TYPE +uav_address[7] <= av_address[7].DB_MAX_OUTPUT_PORT_TYPE +uav_address[8] <= av_address[8].DB_MAX_OUTPUT_PORT_TYPE +uav_address[9] <= av_address[9].DB_MAX_OUTPUT_PORT_TYPE +uav_address[10] <= av_address[10].DB_MAX_OUTPUT_PORT_TYPE +uav_address[11] <= av_address[11].DB_MAX_OUTPUT_PORT_TYPE +uav_address[12] <= av_address[12].DB_MAX_OUTPUT_PORT_TYPE +uav_address[13] <= av_address[13].DB_MAX_OUTPUT_PORT_TYPE +uav_address[14] <= av_address[14].DB_MAX_OUTPUT_PORT_TYPE +uav_address[15] <= av_address[15].DB_MAX_OUTPUT_PORT_TYPE +uav_address[16] <= av_address[16].DB_MAX_OUTPUT_PORT_TYPE +uav_address[17] <= av_address[17].DB_MAX_OUTPUT_PORT_TYPE +uav_address[18] <= av_address[18].DB_MAX_OUTPUT_PORT_TYPE +uav_address[19] <= av_address[19].DB_MAX_OUTPUT_PORT_TYPE +uav_address[20] <= av_address[20].DB_MAX_OUTPUT_PORT_TYPE +uav_address[21] <= av_address[21].DB_MAX_OUTPUT_PORT_TYPE +uav_address[22] <= av_address[22].DB_MAX_OUTPUT_PORT_TYPE +uav_address[23] <= av_address[23].DB_MAX_OUTPUT_PORT_TYPE +uav_address[24] <= av_address[24].DB_MAX_OUTPUT_PORT_TYPE +uav_address[25] <= av_address[25].DB_MAX_OUTPUT_PORT_TYPE +uav_burstcount[0] <= +uav_burstcount[1] <= +uav_burstcount[2] <= +uav_byteenable[0] <= av_byteenable[0].DB_MAX_OUTPUT_PORT_TYPE +uav_byteenable[1] <= av_byteenable[1].DB_MAX_OUTPUT_PORT_TYPE +uav_byteenable[2] <= av_byteenable[2].DB_MAX_OUTPUT_PORT_TYPE +uav_byteenable[3] <= av_byteenable[3].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[0] <= av_writedata[0].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[1] <= av_writedata[1].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[2] <= av_writedata[2].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[3] <= av_writedata[3].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[4] <= av_writedata[4].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[5] <= av_writedata[5].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[6] <= av_writedata[6].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[7] <= av_writedata[7].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[8] <= av_writedata[8].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[9] <= av_writedata[9].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[10] <= av_writedata[10].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[11] <= av_writedata[11].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[12] <= av_writedata[12].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[13] <= av_writedata[13].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[14] <= av_writedata[14].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[15] <= av_writedata[15].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[16] <= av_writedata[16].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[17] <= av_writedata[17].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[18] <= av_writedata[18].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[19] <= av_writedata[19].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[20] <= av_writedata[20].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[21] <= av_writedata[21].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[22] <= av_writedata[22].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[23] <= av_writedata[23].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[24] <= av_writedata[24].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[25] <= av_writedata[25].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[26] <= av_writedata[26].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[27] <= av_writedata[27].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[28] <= av_writedata[28].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[29] <= av_writedata[29].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[30] <= av_writedata[30].DB_MAX_OUTPUT_PORT_TYPE +uav_writedata[31] <= av_writedata[31].DB_MAX_OUTPUT_PORT_TYPE +uav_lock <= av_lock.DB_MAX_OUTPUT_PORT_TYPE +uav_debugaccess <= av_debugaccess.DB_MAX_OUTPUT_PORT_TYPE +uav_clken <= av_clken.DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[0] => av_readdata[0].DATAIN +uav_readdata[1] => av_readdata[1].DATAIN +uav_readdata[2] => av_readdata[2].DATAIN +uav_readdata[3] => av_readdata[3].DATAIN +uav_readdata[4] => av_readdata[4].DATAIN +uav_readdata[5] => av_readdata[5].DATAIN +uav_readdata[6] => av_readdata[6].DATAIN +uav_readdata[7] => av_readdata[7].DATAIN +uav_readdata[8] => av_readdata[8].DATAIN +uav_readdata[9] => av_readdata[9].DATAIN +uav_readdata[10] => av_readdata[10].DATAIN +uav_readdata[11] => av_readdata[11].DATAIN +uav_readdata[12] => av_readdata[12].DATAIN +uav_readdata[13] => av_readdata[13].DATAIN +uav_readdata[14] => av_readdata[14].DATAIN +uav_readdata[15] => av_readdata[15].DATAIN +uav_readdata[16] => av_readdata[16].DATAIN +uav_readdata[17] => av_readdata[17].DATAIN +uav_readdata[18] => av_readdata[18].DATAIN +uav_readdata[19] => av_readdata[19].DATAIN +uav_readdata[20] => av_readdata[20].DATAIN +uav_readdata[21] => av_readdata[21].DATAIN +uav_readdata[22] => av_readdata[22].DATAIN +uav_readdata[23] => av_readdata[23].DATAIN +uav_readdata[24] => av_readdata[24].DATAIN +uav_readdata[25] => av_readdata[25].DATAIN +uav_readdata[26] => av_readdata[26].DATAIN +uav_readdata[27] => av_readdata[27].DATAIN +uav_readdata[28] => av_readdata[28].DATAIN +uav_readdata[29] => av_readdata[29].DATAIN +uav_readdata[30] => av_readdata[30].DATAIN +uav_readdata[31] => av_readdata[31].DATAIN +uav_readdatavalid => av_readdatavalid.DATAIN +uav_waitrequest => av_waitrequest.DATAIN +av_write => uav_write.DATAIN +av_read => uav_read.DATAIN +av_address[0] => uav_address[0].DATAIN +av_address[1] => uav_address[1].DATAIN +av_address[2] => uav_address[2].DATAIN +av_address[3] => uav_address[3].DATAIN +av_address[4] => uav_address[4].DATAIN +av_address[5] => uav_address[5].DATAIN +av_address[6] => uav_address[6].DATAIN +av_address[7] => uav_address[7].DATAIN +av_address[8] => uav_address[8].DATAIN +av_address[9] => uav_address[9].DATAIN +av_address[10] => uav_address[10].DATAIN +av_address[11] => uav_address[11].DATAIN +av_address[12] => uav_address[12].DATAIN +av_address[13] => uav_address[13].DATAIN +av_address[14] => uav_address[14].DATAIN +av_address[15] => uav_address[15].DATAIN +av_address[16] => uav_address[16].DATAIN +av_address[17] => uav_address[17].DATAIN +av_address[18] => uav_address[18].DATAIN +av_address[19] => uav_address[19].DATAIN +av_address[20] => uav_address[20].DATAIN +av_address[21] => uav_address[21].DATAIN +av_address[22] => uav_address[22].DATAIN +av_address[23] => uav_address[23].DATAIN +av_address[24] => uav_address[24].DATAIN +av_address[25] => uav_address[25].DATAIN +av_byteenable[0] => uav_byteenable[0].DATAIN +av_byteenable[1] => uav_byteenable[1].DATAIN +av_byteenable[2] => uav_byteenable[2].DATAIN +av_byteenable[3] => uav_byteenable[3].DATAIN +av_burstcount[0] => ~NO_FANOUT~ +av_writedata[0] => uav_writedata[0].DATAIN +av_writedata[1] => uav_writedata[1].DATAIN +av_writedata[2] => uav_writedata[2].DATAIN +av_writedata[3] => uav_writedata[3].DATAIN +av_writedata[4] => uav_writedata[4].DATAIN +av_writedata[5] => uav_writedata[5].DATAIN +av_writedata[6] => uav_writedata[6].DATAIN +av_writedata[7] => uav_writedata[7].DATAIN +av_writedata[8] => uav_writedata[8].DATAIN +av_writedata[9] => uav_writedata[9].DATAIN +av_writedata[10] => uav_writedata[10].DATAIN +av_writedata[11] => uav_writedata[11].DATAIN +av_writedata[12] => uav_writedata[12].DATAIN +av_writedata[13] => uav_writedata[13].DATAIN +av_writedata[14] => uav_writedata[14].DATAIN +av_writedata[15] => uav_writedata[15].DATAIN +av_writedata[16] => uav_writedata[16].DATAIN +av_writedata[17] => uav_writedata[17].DATAIN +av_writedata[18] => uav_writedata[18].DATAIN +av_writedata[19] => uav_writedata[19].DATAIN +av_writedata[20] => uav_writedata[20].DATAIN +av_writedata[21] => uav_writedata[21].DATAIN +av_writedata[22] => uav_writedata[22].DATAIN +av_writedata[23] => uav_writedata[23].DATAIN +av_writedata[24] => uav_writedata[24].DATAIN +av_writedata[25] => uav_writedata[25].DATAIN +av_writedata[26] => uav_writedata[26].DATAIN +av_writedata[27] => uav_writedata[27].DATAIN +av_writedata[28] => uav_writedata[28].DATAIN +av_writedata[29] => uav_writedata[29].DATAIN +av_writedata[30] => uav_writedata[30].DATAIN +av_writedata[31] => uav_writedata[31].DATAIN +av_begintransfer => ~NO_FANOUT~ +av_beginbursttransfer => ~NO_FANOUT~ +av_lock => uav_lock.DATAIN +av_chipselect => ~NO_FANOUT~ +av_debugaccess => uav_debugaccess.DATAIN +av_clken => uav_clken.DATAIN +av_readdata[0] <= uav_readdata[0].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[1] <= uav_readdata[1].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[2] <= uav_readdata[2].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[3] <= uav_readdata[3].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[4] <= uav_readdata[4].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[5] <= uav_readdata[5].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[6] <= uav_readdata[6].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[7] <= uav_readdata[7].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[8] <= uav_readdata[8].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[9] <= uav_readdata[9].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[10] <= uav_readdata[10].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[11] <= uav_readdata[11].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[12] <= uav_readdata[12].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[13] <= uav_readdata[13].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[14] <= uav_readdata[14].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[15] <= uav_readdata[15].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[16] <= uav_readdata[16].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[17] <= uav_readdata[17].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[18] <= uav_readdata[18].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[19] <= uav_readdata[19].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[20] <= uav_readdata[20].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[21] <= uav_readdata[21].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[22] <= uav_readdata[22].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[23] <= uav_readdata[23].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[24] <= uav_readdata[24].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[25] <= uav_readdata[25].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[26] <= uav_readdata[26].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[27] <= uav_readdata[27].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[28] <= uav_readdata[28].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[29] <= uav_readdata[29].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[30] <= uav_readdata[30].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[31] <= uav_readdata[31].DB_MAX_OUTPUT_PORT_TYPE +av_readdatavalid <= uav_readdatavalid.DB_MAX_OUTPUT_PORT_TYPE +av_waitrequest <= uav_waitrequest.DB_MAX_OUTPUT_PORT_TYPE + + +|de0_nano_system|system:inst_cpu|altera_merlin_slave_translator:cpu_jtag_debug_module_translator +clk => in_transfer.CLK +clk => end_beginbursttransfer.CLK +clk => end_begintransfer.CLK +clk => av_chipselect_pre.CLK +clk => av_outputenable_pre.CLK +clk => read_latency_shift_reg[0].CLK +clk => av_readdata_pre[0].CLK +clk => av_readdata_pre[1].CLK +clk => av_readdata_pre[2].CLK +clk => av_readdata_pre[3].CLK +clk => av_readdata_pre[4].CLK +clk => av_readdata_pre[5].CLK +clk => av_readdata_pre[6].CLK +clk => av_readdata_pre[7].CLK +clk => av_readdata_pre[8].CLK +clk => av_readdata_pre[9].CLK +clk => av_readdata_pre[10].CLK +clk => av_readdata_pre[11].CLK +clk => av_readdata_pre[12].CLK +clk => av_readdata_pre[13].CLK +clk => av_readdata_pre[14].CLK +clk => av_readdata_pre[15].CLK +clk => av_readdata_pre[16].CLK +clk => av_readdata_pre[17].CLK +clk => av_readdata_pre[18].CLK +clk => av_readdata_pre[19].CLK +clk => av_readdata_pre[20].CLK +clk => av_readdata_pre[21].CLK +clk => av_readdata_pre[22].CLK +clk => av_readdata_pre[23].CLK +clk => av_readdata_pre[24].CLK +clk => av_readdata_pre[25].CLK +clk => av_readdata_pre[26].CLK +clk => av_readdata_pre[27].CLK +clk => av_readdata_pre[28].CLK +clk => av_readdata_pre[29].CLK +clk => av_readdata_pre[30].CLK +clk => av_readdata_pre[31].CLK +clk => waitrequest_reset_override.CLK +clk => wait_latency_counter[0].CLK +clk => wait_latency_counter[1].CLK +reset => in_transfer.ACLR +reset => end_beginbursttransfer.ACLR +reset => end_begintransfer.ACLR +reset => av_chipselect_pre.ACLR +reset => av_outputenable_pre.ACLR +reset => read_latency_shift_reg[0].ACLR +reset => av_readdata_pre[0].ACLR +reset => av_readdata_pre[1].ACLR +reset => av_readdata_pre[2].ACLR +reset => av_readdata_pre[3].ACLR +reset => av_readdata_pre[4].ACLR +reset => av_readdata_pre[5].ACLR +reset => av_readdata_pre[6].ACLR +reset => av_readdata_pre[7].ACLR +reset => av_readdata_pre[8].ACLR +reset => av_readdata_pre[9].ACLR +reset => av_readdata_pre[10].ACLR +reset => av_readdata_pre[11].ACLR +reset => av_readdata_pre[12].ACLR +reset => av_readdata_pre[13].ACLR +reset => av_readdata_pre[14].ACLR +reset => av_readdata_pre[15].ACLR +reset => av_readdata_pre[16].ACLR +reset => av_readdata_pre[17].ACLR +reset => av_readdata_pre[18].ACLR +reset => av_readdata_pre[19].ACLR +reset => av_readdata_pre[20].ACLR +reset => av_readdata_pre[21].ACLR +reset => av_readdata_pre[22].ACLR +reset => av_readdata_pre[23].ACLR +reset => av_readdata_pre[24].ACLR +reset => av_readdata_pre[25].ACLR +reset => av_readdata_pre[26].ACLR +reset => av_readdata_pre[27].ACLR +reset => av_readdata_pre[28].ACLR +reset => av_readdata_pre[29].ACLR +reset => av_readdata_pre[30].ACLR +reset => av_readdata_pre[31].ACLR +reset => waitrequest_reset_override.PRESET +reset => wait_latency_counter[0].ACLR +reset => wait_latency_counter[1].ACLR +uav_address[0] => ~NO_FANOUT~ +uav_address[1] => ~NO_FANOUT~ +uav_address[2] => av_address[0].DATAIN +uav_address[3] => av_address[1].DATAIN +uav_address[4] => av_address[2].DATAIN +uav_address[5] => av_address[3].DATAIN +uav_address[6] => av_address[4].DATAIN +uav_address[7] => av_address[5].DATAIN +uav_address[8] => av_address[6].DATAIN +uav_address[9] => av_address[7].DATAIN +uav_address[10] => av_address[8].DATAIN +uav_address[11] => ~NO_FANOUT~ +uav_address[12] => ~NO_FANOUT~ +uav_address[13] => ~NO_FANOUT~ +uav_address[14] => ~NO_FANOUT~ +uav_address[15] => ~NO_FANOUT~ +uav_address[16] => ~NO_FANOUT~ +uav_address[17] => ~NO_FANOUT~ +uav_address[18] => ~NO_FANOUT~ +uav_address[19] => ~NO_FANOUT~ +uav_address[20] => ~NO_FANOUT~ +uav_address[21] => ~NO_FANOUT~ +uav_address[22] => ~NO_FANOUT~ +uav_address[23] => ~NO_FANOUT~ +uav_address[24] => ~NO_FANOUT~ +uav_address[25] => ~NO_FANOUT~ +uav_writedata[0] => av_writedata[0].DATAIN +uav_writedata[1] => av_writedata[1].DATAIN +uav_writedata[2] => av_writedata[2].DATAIN +uav_writedata[3] => av_writedata[3].DATAIN +uav_writedata[4] => av_writedata[4].DATAIN +uav_writedata[5] => av_writedata[5].DATAIN +uav_writedata[6] => av_writedata[6].DATAIN +uav_writedata[7] => av_writedata[7].DATAIN +uav_writedata[8] => av_writedata[8].DATAIN +uav_writedata[9] => av_writedata[9].DATAIN +uav_writedata[10] => av_writedata[10].DATAIN +uav_writedata[11] => av_writedata[11].DATAIN +uav_writedata[12] => av_writedata[12].DATAIN +uav_writedata[13] => av_writedata[13].DATAIN +uav_writedata[14] => av_writedata[14].DATAIN +uav_writedata[15] => av_writedata[15].DATAIN +uav_writedata[16] => av_writedata[16].DATAIN +uav_writedata[17] => av_writedata[17].DATAIN +uav_writedata[18] => av_writedata[18].DATAIN +uav_writedata[19] => av_writedata[19].DATAIN +uav_writedata[20] => av_writedata[20].DATAIN +uav_writedata[21] => av_writedata[21].DATAIN +uav_writedata[22] => av_writedata[22].DATAIN +uav_writedata[23] => av_writedata[23].DATAIN +uav_writedata[24] => av_writedata[24].DATAIN +uav_writedata[25] => av_writedata[25].DATAIN +uav_writedata[26] => av_writedata[26].DATAIN +uav_writedata[27] => av_writedata[27].DATAIN +uav_writedata[28] => av_writedata[28].DATAIN +uav_writedata[29] => av_writedata[29].DATAIN +uav_writedata[30] => av_writedata[30].DATAIN +uav_writedata[31] => av_writedata[31].DATAIN +uav_write => av_writebyteenable.IN0 +uav_write => av_writebyteenable.IN0 +uav_write => av_writebyteenable.IN0 +uav_write => av_writebyteenable.IN0 +uav_write => av_write.IN1 +uav_write => av_waitrequest_generated.OUTPUTSELECT +uav_write => av_begintransfer.IN0 +uav_write => end_beginbursttransfer.IN1 +uav_write => always19.IN1 +uav_write => in_transfer.OUTPUTSELECT +uav_read => av_read.IN1 +uav_read => read_latency_shift_reg.IN1 +uav_read => av_outputenable.OUTPUTSELECT +uav_read => av_begintransfer.IN1 +uav_read => av_beginbursttransfer.OUTPUTSELECT +uav_burstcount[0] => Equal2.IN3 +uav_burstcount[1] => Equal2.IN2 +uav_burstcount[2] => av_burstcount[0].DATAIN +uav_burstcount[2] => Equal2.IN4 +uav_byteenable[0] => av_writebyteenable.IN1 +uav_byteenable[0] => av_byteenable[0].DATAIN +uav_byteenable[1] => av_writebyteenable.IN1 +uav_byteenable[1] => av_byteenable[1].DATAIN +uav_byteenable[2] => av_writebyteenable.IN1 +uav_byteenable[2] => av_byteenable[2].DATAIN +uav_byteenable[3] => av_writebyteenable.IN1 +uav_byteenable[3] => av_byteenable[3].DATAIN +uav_lock => av_lock.DATAIN +uav_debugaccess => av_debugaccess.DATAIN +uav_clken => ~NO_FANOUT~ +uav_readdatavalid <= read_latency_shift_reg[0].DB_MAX_OUTPUT_PORT_TYPE +uav_waitrequest <= uav_waitrequest.DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[0] <= av_readdata_pre[0].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[1] <= av_readdata_pre[1].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[2] <= av_readdata_pre[2].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[3] <= av_readdata_pre[3].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[4] <= av_readdata_pre[4].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[5] <= av_readdata_pre[5].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[6] <= av_readdata_pre[6].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[7] <= av_readdata_pre[7].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[8] <= av_readdata_pre[8].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[9] <= av_readdata_pre[9].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[10] <= av_readdata_pre[10].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[11] <= av_readdata_pre[11].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[12] <= av_readdata_pre[12].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[13] <= av_readdata_pre[13].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[14] <= av_readdata_pre[14].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[15] <= av_readdata_pre[15].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[16] <= av_readdata_pre[16].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[17] <= av_readdata_pre[17].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[18] <= av_readdata_pre[18].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[19] <= av_readdata_pre[19].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[20] <= av_readdata_pre[20].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[21] <= av_readdata_pre[21].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[22] <= av_readdata_pre[22].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[23] <= av_readdata_pre[23].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[24] <= av_readdata_pre[24].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[25] <= av_readdata_pre[25].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[26] <= av_readdata_pre[26].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[27] <= av_readdata_pre[27].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[28] <= av_readdata_pre[28].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[29] <= av_readdata_pre[29].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[30] <= av_readdata_pre[30].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[31] <= av_readdata_pre[31].DB_MAX_OUTPUT_PORT_TYPE +av_address[0] <= uav_address[2].DB_MAX_OUTPUT_PORT_TYPE +av_address[1] <= uav_address[3].DB_MAX_OUTPUT_PORT_TYPE +av_address[2] <= uav_address[4].DB_MAX_OUTPUT_PORT_TYPE +av_address[3] <= uav_address[5].DB_MAX_OUTPUT_PORT_TYPE +av_address[4] <= uav_address[6].DB_MAX_OUTPUT_PORT_TYPE +av_address[5] <= uav_address[7].DB_MAX_OUTPUT_PORT_TYPE +av_address[6] <= uav_address[8].DB_MAX_OUTPUT_PORT_TYPE +av_address[7] <= uav_address[9].DB_MAX_OUTPUT_PORT_TYPE +av_address[8] <= uav_address[10].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[0] <= uav_writedata[0].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[1] <= uav_writedata[1].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[2] <= uav_writedata[2].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[3] <= uav_writedata[3].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[4] <= uav_writedata[4].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[5] <= uav_writedata[5].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[6] <= uav_writedata[6].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[7] <= uav_writedata[7].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[8] <= uav_writedata[8].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[9] <= uav_writedata[9].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[10] <= uav_writedata[10].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[11] <= uav_writedata[11].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[12] <= uav_writedata[12].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[13] <= uav_writedata[13].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[14] <= uav_writedata[14].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[15] <= uav_writedata[15].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[16] <= uav_writedata[16].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[17] <= uav_writedata[17].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[18] <= uav_writedata[18].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[19] <= uav_writedata[19].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[20] <= uav_writedata[20].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[21] <= uav_writedata[21].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[22] <= uav_writedata[22].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[23] <= uav_writedata[23].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[24] <= uav_writedata[24].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[25] <= uav_writedata[25].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[26] <= uav_writedata[26].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[27] <= uav_writedata[27].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[28] <= uav_writedata[28].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[29] <= uav_writedata[29].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[30] <= uav_writedata[30].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[31] <= uav_writedata[31].DB_MAX_OUTPUT_PORT_TYPE +av_write <= av_write.DB_MAX_OUTPUT_PORT_TYPE +av_read <= av_read.DB_MAX_OUTPUT_PORT_TYPE +av_burstcount[0] <= uav_burstcount[2].DB_MAX_OUTPUT_PORT_TYPE +av_byteenable[0] <= uav_byteenable[0].DB_MAX_OUTPUT_PORT_TYPE +av_byteenable[1] <= uav_byteenable[1].DB_MAX_OUTPUT_PORT_TYPE +av_byteenable[2] <= uav_byteenable[2].DB_MAX_OUTPUT_PORT_TYPE +av_byteenable[3] <= uav_byteenable[3].DB_MAX_OUTPUT_PORT_TYPE +av_writebyteenable[0] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE +av_writebyteenable[1] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE +av_writebyteenable[2] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE +av_writebyteenable[3] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE +av_begintransfer <= av_begintransfer.DB_MAX_OUTPUT_PORT_TYPE +av_chipselect <= av_chipselect.DB_MAX_OUTPUT_PORT_TYPE +av_beginbursttransfer <= av_beginbursttransfer.DB_MAX_OUTPUT_PORT_TYPE +av_lock <= uav_lock.DB_MAX_OUTPUT_PORT_TYPE +av_clken <= +av_debugaccess <= uav_debugaccess.DB_MAX_OUTPUT_PORT_TYPE +av_outputenable <= av_outputenable.DB_MAX_OUTPUT_PORT_TYPE +av_readdata[0] => av_readdata_pre[0].DATAIN +av_readdata[1] => av_readdata_pre[1].DATAIN +av_readdata[2] => av_readdata_pre[2].DATAIN +av_readdata[3] => av_readdata_pre[3].DATAIN +av_readdata[4] => av_readdata_pre[4].DATAIN +av_readdata[5] => av_readdata_pre[5].DATAIN +av_readdata[6] => av_readdata_pre[6].DATAIN +av_readdata[7] => av_readdata_pre[7].DATAIN +av_readdata[8] => av_readdata_pre[8].DATAIN +av_readdata[9] => av_readdata_pre[9].DATAIN +av_readdata[10] => av_readdata_pre[10].DATAIN +av_readdata[11] => av_readdata_pre[11].DATAIN +av_readdata[12] => av_readdata_pre[12].DATAIN +av_readdata[13] => av_readdata_pre[13].DATAIN +av_readdata[14] => av_readdata_pre[14].DATAIN +av_readdata[15] => av_readdata_pre[15].DATAIN +av_readdata[16] => av_readdata_pre[16].DATAIN +av_readdata[17] => av_readdata_pre[17].DATAIN +av_readdata[18] => av_readdata_pre[18].DATAIN +av_readdata[19] => av_readdata_pre[19].DATAIN +av_readdata[20] => av_readdata_pre[20].DATAIN +av_readdata[21] => av_readdata_pre[21].DATAIN +av_readdata[22] => av_readdata_pre[22].DATAIN +av_readdata[23] => av_readdata_pre[23].DATAIN +av_readdata[24] => av_readdata_pre[24].DATAIN +av_readdata[25] => av_readdata_pre[25].DATAIN +av_readdata[26] => av_readdata_pre[26].DATAIN +av_readdata[27] => av_readdata_pre[27].DATAIN +av_readdata[28] => av_readdata_pre[28].DATAIN +av_readdata[29] => av_readdata_pre[29].DATAIN +av_readdata[30] => av_readdata_pre[30].DATAIN +av_readdata[31] => av_readdata_pre[31].DATAIN +av_readdatavalid => ~NO_FANOUT~ +av_waitrequest => ~NO_FANOUT~ + + +|de0_nano_system|system:inst_cpu|altera_merlin_slave_translator:sdram_s1_translator +clk => in_transfer.CLK +clk => end_beginbursttransfer.CLK +clk => end_begintransfer.CLK +clk => av_chipselect_pre.CLK +clk => av_outputenable_pre.CLK +clk => waitrequest_reset_override.CLK +reset => in_transfer.ACLR +reset => end_beginbursttransfer.ACLR +reset => end_begintransfer.ACLR +reset => av_chipselect_pre.ACLR +reset => av_outputenable_pre.ACLR +reset => waitrequest_reset_override.PRESET +uav_address[0] => ~NO_FANOUT~ +uav_address[1] => av_address[0].DATAIN +uav_address[2] => av_address[1].DATAIN +uav_address[3] => av_address[2].DATAIN +uav_address[4] => av_address[3].DATAIN +uav_address[5] => av_address[4].DATAIN +uav_address[6] => av_address[5].DATAIN +uav_address[7] => av_address[6].DATAIN +uav_address[8] => av_address[7].DATAIN +uav_address[9] => av_address[8].DATAIN +uav_address[10] => av_address[9].DATAIN +uav_address[11] => av_address[10].DATAIN +uav_address[12] => av_address[11].DATAIN +uav_address[13] => av_address[12].DATAIN +uav_address[14] => av_address[13].DATAIN +uav_address[15] => av_address[14].DATAIN +uav_address[16] => av_address[15].DATAIN +uav_address[17] => av_address[16].DATAIN +uav_address[18] => av_address[17].DATAIN +uav_address[19] => av_address[18].DATAIN +uav_address[20] => av_address[19].DATAIN +uav_address[21] => av_address[20].DATAIN +uav_address[22] => av_address[21].DATAIN +uav_address[23] => av_address[22].DATAIN +uav_address[24] => ~NO_FANOUT~ +uav_address[25] => ~NO_FANOUT~ +uav_writedata[0] => av_writedata[0].DATAIN +uav_writedata[1] => av_writedata[1].DATAIN +uav_writedata[2] => av_writedata[2].DATAIN +uav_writedata[3] => av_writedata[3].DATAIN +uav_writedata[4] => av_writedata[4].DATAIN +uav_writedata[5] => av_writedata[5].DATAIN +uav_writedata[6] => av_writedata[6].DATAIN +uav_writedata[7] => av_writedata[7].DATAIN +uav_writedata[8] => av_writedata[8].DATAIN +uav_writedata[9] => av_writedata[9].DATAIN +uav_writedata[10] => av_writedata[10].DATAIN +uav_writedata[11] => av_writedata[11].DATAIN +uav_writedata[12] => av_writedata[12].DATAIN +uav_writedata[13] => av_writedata[13].DATAIN +uav_writedata[14] => av_writedata[14].DATAIN +uav_writedata[15] => av_writedata[15].DATAIN +uav_write => av_writebyteenable.IN0 +uav_write => av_writebyteenable.IN0 +uav_write => av_begintransfer.IN0 +uav_write => end_beginbursttransfer.IN1 +uav_write => always19.IN1 +uav_write => in_transfer.OUTPUTSELECT +uav_write => av_write.DATAIN +uav_read => av_outputenable.OUTPUTSELECT +uav_read => av_begintransfer.IN1 +uav_read => av_beginbursttransfer.OUTPUTSELECT +uav_read => av_read.DATAIN +uav_burstcount[0] => Equal0.IN2 +uav_burstcount[1] => av_burstcount[0].DATAIN +uav_burstcount[1] => Equal0.IN3 +uav_byteenable[0] => av_writebyteenable.IN1 +uav_byteenable[0] => av_byteenable[0].DATAIN +uav_byteenable[1] => av_writebyteenable.IN1 +uav_byteenable[1] => av_byteenable[1].DATAIN +uav_lock => av_lock.DATAIN +uav_debugaccess => av_debugaccess.DATAIN +uav_clken => ~NO_FANOUT~ +uav_readdatavalid <= av_readdatavalid.DB_MAX_OUTPUT_PORT_TYPE +uav_waitrequest <= av_waitrequest.DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[0] <= av_readdata[0].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[1] <= av_readdata[1].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[2] <= av_readdata[2].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[3] <= av_readdata[3].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[4] <= av_readdata[4].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[5] <= av_readdata[5].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[6] <= av_readdata[6].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[7] <= av_readdata[7].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[8] <= av_readdata[8].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[9] <= av_readdata[9].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[10] <= av_readdata[10].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[11] <= av_readdata[11].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[12] <= av_readdata[12].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[13] <= av_readdata[13].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[14] <= av_readdata[14].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[15] <= av_readdata[15].DB_MAX_OUTPUT_PORT_TYPE +av_address[0] <= uav_address[1].DB_MAX_OUTPUT_PORT_TYPE +av_address[1] <= uav_address[2].DB_MAX_OUTPUT_PORT_TYPE +av_address[2] <= uav_address[3].DB_MAX_OUTPUT_PORT_TYPE +av_address[3] <= uav_address[4].DB_MAX_OUTPUT_PORT_TYPE +av_address[4] <= uav_address[5].DB_MAX_OUTPUT_PORT_TYPE +av_address[5] <= uav_address[6].DB_MAX_OUTPUT_PORT_TYPE +av_address[6] <= uav_address[7].DB_MAX_OUTPUT_PORT_TYPE +av_address[7] <= uav_address[8].DB_MAX_OUTPUT_PORT_TYPE +av_address[8] <= uav_address[9].DB_MAX_OUTPUT_PORT_TYPE +av_address[9] <= uav_address[10].DB_MAX_OUTPUT_PORT_TYPE +av_address[10] <= uav_address[11].DB_MAX_OUTPUT_PORT_TYPE +av_address[11] <= uav_address[12].DB_MAX_OUTPUT_PORT_TYPE +av_address[12] <= uav_address[13].DB_MAX_OUTPUT_PORT_TYPE +av_address[13] <= uav_address[14].DB_MAX_OUTPUT_PORT_TYPE +av_address[14] <= uav_address[15].DB_MAX_OUTPUT_PORT_TYPE +av_address[15] <= uav_address[16].DB_MAX_OUTPUT_PORT_TYPE +av_address[16] <= uav_address[17].DB_MAX_OUTPUT_PORT_TYPE +av_address[17] <= uav_address[18].DB_MAX_OUTPUT_PORT_TYPE +av_address[18] <= uav_address[19].DB_MAX_OUTPUT_PORT_TYPE +av_address[19] <= uav_address[20].DB_MAX_OUTPUT_PORT_TYPE +av_address[20] <= uav_address[21].DB_MAX_OUTPUT_PORT_TYPE +av_address[21] <= uav_address[22].DB_MAX_OUTPUT_PORT_TYPE +av_address[22] <= uav_address[23].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[0] <= uav_writedata[0].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[1] <= uav_writedata[1].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[2] <= uav_writedata[2].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[3] <= uav_writedata[3].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[4] <= uav_writedata[4].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[5] <= uav_writedata[5].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[6] <= uav_writedata[6].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[7] <= uav_writedata[7].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[8] <= uav_writedata[8].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[9] <= uav_writedata[9].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[10] <= uav_writedata[10].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[11] <= uav_writedata[11].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[12] <= uav_writedata[12].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[13] <= uav_writedata[13].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[14] <= uav_writedata[14].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[15] <= uav_writedata[15].DB_MAX_OUTPUT_PORT_TYPE +av_write <= uav_write.DB_MAX_OUTPUT_PORT_TYPE +av_read <= uav_read.DB_MAX_OUTPUT_PORT_TYPE +av_burstcount[0] <= uav_burstcount[1].DB_MAX_OUTPUT_PORT_TYPE +av_byteenable[0] <= uav_byteenable[0].DB_MAX_OUTPUT_PORT_TYPE +av_byteenable[1] <= uav_byteenable[1].DB_MAX_OUTPUT_PORT_TYPE +av_writebyteenable[0] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE +av_writebyteenable[1] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE +av_begintransfer <= av_begintransfer.DB_MAX_OUTPUT_PORT_TYPE +av_chipselect <= av_chipselect.DB_MAX_OUTPUT_PORT_TYPE +av_beginbursttransfer <= av_beginbursttransfer.DB_MAX_OUTPUT_PORT_TYPE +av_lock <= uav_lock.DB_MAX_OUTPUT_PORT_TYPE +av_clken <= +av_debugaccess <= uav_debugaccess.DB_MAX_OUTPUT_PORT_TYPE +av_outputenable <= av_outputenable.DB_MAX_OUTPUT_PORT_TYPE +av_readdata[0] => uav_readdata[0].DATAIN +av_readdata[1] => uav_readdata[1].DATAIN +av_readdata[2] => uav_readdata[2].DATAIN +av_readdata[3] => uav_readdata[3].DATAIN +av_readdata[4] => uav_readdata[4].DATAIN +av_readdata[5] => uav_readdata[5].DATAIN +av_readdata[6] => uav_readdata[6].DATAIN +av_readdata[7] => uav_readdata[7].DATAIN +av_readdata[8] => uav_readdata[8].DATAIN +av_readdata[9] => uav_readdata[9].DATAIN +av_readdata[10] => uav_readdata[10].DATAIN +av_readdata[11] => uav_readdata[11].DATAIN +av_readdata[12] => uav_readdata[12].DATAIN +av_readdata[13] => uav_readdata[13].DATAIN +av_readdata[14] => uav_readdata[14].DATAIN +av_readdata[15] => uav_readdata[15].DATAIN +av_readdatavalid => uav_readdatavalid.DATAIN +av_waitrequest => always17.IN1 +av_waitrequest => end_begintransfer.OUTPUTSELECT +av_waitrequest => uav_waitrequest.DATAIN + + +|de0_nano_system|system:inst_cpu|altera_merlin_slave_translator:sysid_control_slave_translator +clk => in_transfer.CLK +clk => end_beginbursttransfer.CLK +clk => end_begintransfer.CLK +clk => av_chipselect_pre.CLK +clk => av_outputenable_pre.CLK +clk => read_latency_shift_reg[0].CLK +clk => av_readdata_pre[0].CLK +clk => av_readdata_pre[1].CLK +clk => av_readdata_pre[2].CLK +clk => av_readdata_pre[3].CLK +clk => av_readdata_pre[4].CLK +clk => av_readdata_pre[5].CLK +clk => av_readdata_pre[6].CLK +clk => av_readdata_pre[7].CLK +clk => av_readdata_pre[8].CLK +clk => av_readdata_pre[9].CLK +clk => av_readdata_pre[10].CLK +clk => av_readdata_pre[11].CLK +clk => av_readdata_pre[12].CLK +clk => av_readdata_pre[13].CLK +clk => av_readdata_pre[14].CLK +clk => av_readdata_pre[15].CLK +clk => av_readdata_pre[16].CLK +clk => av_readdata_pre[17].CLK +clk => av_readdata_pre[18].CLK +clk => av_readdata_pre[19].CLK +clk => av_readdata_pre[20].CLK +clk => av_readdata_pre[21].CLK +clk => av_readdata_pre[22].CLK +clk => av_readdata_pre[23].CLK +clk => av_readdata_pre[24].CLK +clk => av_readdata_pre[25].CLK +clk => av_readdata_pre[26].CLK +clk => av_readdata_pre[27].CLK +clk => av_readdata_pre[28].CLK +clk => av_readdata_pre[29].CLK +clk => av_readdata_pre[30].CLK +clk => av_readdata_pre[31].CLK +clk => waitrequest_reset_override.CLK +clk => wait_latency_counter[0].CLK +clk => wait_latency_counter[1].CLK +reset => in_transfer.ACLR +reset => end_beginbursttransfer.ACLR +reset => end_begintransfer.ACLR +reset => av_chipselect_pre.ACLR +reset => av_outputenable_pre.ACLR +reset => read_latency_shift_reg[0].ACLR +reset => av_readdata_pre[0].ACLR +reset => av_readdata_pre[1].ACLR +reset => av_readdata_pre[2].ACLR +reset => av_readdata_pre[3].ACLR +reset => av_readdata_pre[4].ACLR +reset => av_readdata_pre[5].ACLR +reset => av_readdata_pre[6].ACLR +reset => av_readdata_pre[7].ACLR +reset => av_readdata_pre[8].ACLR +reset => av_readdata_pre[9].ACLR +reset => av_readdata_pre[10].ACLR +reset => av_readdata_pre[11].ACLR +reset => av_readdata_pre[12].ACLR +reset => av_readdata_pre[13].ACLR +reset => av_readdata_pre[14].ACLR +reset => av_readdata_pre[15].ACLR +reset => av_readdata_pre[16].ACLR +reset => av_readdata_pre[17].ACLR +reset => av_readdata_pre[18].ACLR +reset => av_readdata_pre[19].ACLR +reset => av_readdata_pre[20].ACLR +reset => av_readdata_pre[21].ACLR +reset => av_readdata_pre[22].ACLR +reset => av_readdata_pre[23].ACLR +reset => av_readdata_pre[24].ACLR +reset => av_readdata_pre[25].ACLR +reset => av_readdata_pre[26].ACLR +reset => av_readdata_pre[27].ACLR +reset => av_readdata_pre[28].ACLR +reset => av_readdata_pre[29].ACLR +reset => av_readdata_pre[30].ACLR +reset => av_readdata_pre[31].ACLR +reset => waitrequest_reset_override.PRESET +reset => wait_latency_counter[0].ACLR +reset => wait_latency_counter[1].ACLR +uav_address[0] => ~NO_FANOUT~ +uav_address[1] => ~NO_FANOUT~ +uav_address[2] => av_address[0].DATAIN +uav_address[3] => ~NO_FANOUT~ +uav_address[4] => ~NO_FANOUT~ +uav_address[5] => ~NO_FANOUT~ +uav_address[6] => ~NO_FANOUT~ +uav_address[7] => ~NO_FANOUT~ +uav_address[8] => ~NO_FANOUT~ +uav_address[9] => ~NO_FANOUT~ +uav_address[10] => ~NO_FANOUT~ +uav_address[11] => ~NO_FANOUT~ +uav_address[12] => ~NO_FANOUT~ +uav_address[13] => ~NO_FANOUT~ +uav_address[14] => ~NO_FANOUT~ +uav_address[15] => ~NO_FANOUT~ +uav_address[16] => ~NO_FANOUT~ +uav_address[17] => ~NO_FANOUT~ +uav_address[18] => ~NO_FANOUT~ +uav_address[19] => ~NO_FANOUT~ +uav_address[20] => ~NO_FANOUT~ +uav_address[21] => ~NO_FANOUT~ +uav_address[22] => ~NO_FANOUT~ +uav_address[23] => ~NO_FANOUT~ +uav_address[24] => ~NO_FANOUT~ +uav_address[25] => ~NO_FANOUT~ +uav_writedata[0] => av_writedata[0].DATAIN +uav_writedata[1] => av_writedata[1].DATAIN +uav_writedata[2] => av_writedata[2].DATAIN +uav_writedata[3] => av_writedata[3].DATAIN +uav_writedata[4] => av_writedata[4].DATAIN +uav_writedata[5] => av_writedata[5].DATAIN +uav_writedata[6] => av_writedata[6].DATAIN +uav_writedata[7] => av_writedata[7].DATAIN +uav_writedata[8] => av_writedata[8].DATAIN +uav_writedata[9] => av_writedata[9].DATAIN +uav_writedata[10] => av_writedata[10].DATAIN +uav_writedata[11] => av_writedata[11].DATAIN +uav_writedata[12] => av_writedata[12].DATAIN +uav_writedata[13] => av_writedata[13].DATAIN +uav_writedata[14] => av_writedata[14].DATAIN +uav_writedata[15] => av_writedata[15].DATAIN +uav_writedata[16] => av_writedata[16].DATAIN +uav_writedata[17] => av_writedata[17].DATAIN +uav_writedata[18] => av_writedata[18].DATAIN +uav_writedata[19] => av_writedata[19].DATAIN +uav_writedata[20] => av_writedata[20].DATAIN +uav_writedata[21] => av_writedata[21].DATAIN +uav_writedata[22] => av_writedata[22].DATAIN +uav_writedata[23] => av_writedata[23].DATAIN +uav_writedata[24] => av_writedata[24].DATAIN +uav_writedata[25] => av_writedata[25].DATAIN +uav_writedata[26] => av_writedata[26].DATAIN +uav_writedata[27] => av_writedata[27].DATAIN +uav_writedata[28] => av_writedata[28].DATAIN +uav_writedata[29] => av_writedata[29].DATAIN +uav_writedata[30] => av_writedata[30].DATAIN +uav_writedata[31] => av_writedata[31].DATAIN +uav_write => av_writebyteenable.IN0 +uav_write => av_writebyteenable.IN0 +uav_write => av_writebyteenable.IN0 +uav_write => av_writebyteenable.IN0 +uav_write => av_write.IN1 +uav_write => av_waitrequest_generated.OUTPUTSELECT +uav_write => av_begintransfer.IN0 +uav_write => end_beginbursttransfer.IN1 +uav_write => always19.IN1 +uav_write => in_transfer.OUTPUTSELECT +uav_read => av_read.IN1 +uav_read => read_latency_shift_reg.IN1 +uav_read => av_outputenable.OUTPUTSELECT +uav_read => av_begintransfer.IN1 +uav_read => av_beginbursttransfer.OUTPUTSELECT +uav_burstcount[0] => Equal2.IN3 +uav_burstcount[1] => Equal2.IN2 +uav_burstcount[2] => av_burstcount[0].DATAIN +uav_burstcount[2] => Equal2.IN4 +uav_byteenable[0] => av_writebyteenable.IN1 +uav_byteenable[0] => av_byteenable[0].DATAIN +uav_byteenable[1] => av_writebyteenable.IN1 +uav_byteenable[1] => av_byteenable[1].DATAIN +uav_byteenable[2] => av_writebyteenable.IN1 +uav_byteenable[2] => av_byteenable[2].DATAIN +uav_byteenable[3] => av_writebyteenable.IN1 +uav_byteenable[3] => av_byteenable[3].DATAIN +uav_lock => av_lock.DATAIN +uav_debugaccess => av_debugaccess.DATAIN +uav_clken => ~NO_FANOUT~ +uav_readdatavalid <= read_latency_shift_reg[0].DB_MAX_OUTPUT_PORT_TYPE +uav_waitrequest <= uav_waitrequest.DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[0] <= av_readdata_pre[0].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[1] <= av_readdata_pre[1].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[2] <= av_readdata_pre[2].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[3] <= av_readdata_pre[3].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[4] <= av_readdata_pre[4].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[5] <= av_readdata_pre[5].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[6] <= av_readdata_pre[6].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[7] <= av_readdata_pre[7].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[8] <= av_readdata_pre[8].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[9] <= av_readdata_pre[9].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[10] <= av_readdata_pre[10].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[11] <= av_readdata_pre[11].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[12] <= av_readdata_pre[12].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[13] <= av_readdata_pre[13].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[14] <= av_readdata_pre[14].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[15] <= av_readdata_pre[15].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[16] <= av_readdata_pre[16].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[17] <= av_readdata_pre[17].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[18] <= av_readdata_pre[18].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[19] <= av_readdata_pre[19].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[20] <= av_readdata_pre[20].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[21] <= av_readdata_pre[21].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[22] <= av_readdata_pre[22].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[23] <= av_readdata_pre[23].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[24] <= av_readdata_pre[24].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[25] <= av_readdata_pre[25].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[26] <= av_readdata_pre[26].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[27] <= av_readdata_pre[27].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[28] <= av_readdata_pre[28].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[29] <= av_readdata_pre[29].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[30] <= av_readdata_pre[30].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[31] <= av_readdata_pre[31].DB_MAX_OUTPUT_PORT_TYPE +av_address[0] <= uav_address[2].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[0] <= uav_writedata[0].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[1] <= uav_writedata[1].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[2] <= uav_writedata[2].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[3] <= uav_writedata[3].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[4] <= uav_writedata[4].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[5] <= uav_writedata[5].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[6] <= uav_writedata[6].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[7] <= uav_writedata[7].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[8] <= uav_writedata[8].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[9] <= uav_writedata[9].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[10] <= uav_writedata[10].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[11] <= uav_writedata[11].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[12] <= uav_writedata[12].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[13] <= uav_writedata[13].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[14] <= uav_writedata[14].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[15] <= uav_writedata[15].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[16] <= uav_writedata[16].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[17] <= uav_writedata[17].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[18] <= uav_writedata[18].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[19] <= uav_writedata[19].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[20] <= uav_writedata[20].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[21] <= uav_writedata[21].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[22] <= uav_writedata[22].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[23] <= uav_writedata[23].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[24] <= uav_writedata[24].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[25] <= uav_writedata[25].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[26] <= uav_writedata[26].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[27] <= uav_writedata[27].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[28] <= uav_writedata[28].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[29] <= uav_writedata[29].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[30] <= uav_writedata[30].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[31] <= uav_writedata[31].DB_MAX_OUTPUT_PORT_TYPE +av_write <= av_write.DB_MAX_OUTPUT_PORT_TYPE +av_read <= av_read.DB_MAX_OUTPUT_PORT_TYPE +av_burstcount[0] <= uav_burstcount[2].DB_MAX_OUTPUT_PORT_TYPE +av_byteenable[0] <= uav_byteenable[0].DB_MAX_OUTPUT_PORT_TYPE +av_byteenable[1] <= uav_byteenable[1].DB_MAX_OUTPUT_PORT_TYPE +av_byteenable[2] <= uav_byteenable[2].DB_MAX_OUTPUT_PORT_TYPE +av_byteenable[3] <= uav_byteenable[3].DB_MAX_OUTPUT_PORT_TYPE +av_writebyteenable[0] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE +av_writebyteenable[1] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE +av_writebyteenable[2] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE +av_writebyteenable[3] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE +av_begintransfer <= av_begintransfer.DB_MAX_OUTPUT_PORT_TYPE +av_chipselect <= av_chipselect.DB_MAX_OUTPUT_PORT_TYPE +av_beginbursttransfer <= av_beginbursttransfer.DB_MAX_OUTPUT_PORT_TYPE +av_lock <= uav_lock.DB_MAX_OUTPUT_PORT_TYPE +av_clken <= +av_debugaccess <= uav_debugaccess.DB_MAX_OUTPUT_PORT_TYPE +av_outputenable <= av_outputenable.DB_MAX_OUTPUT_PORT_TYPE +av_readdata[0] => av_readdata_pre[0].DATAIN +av_readdata[1] => av_readdata_pre[1].DATAIN +av_readdata[2] => av_readdata_pre[2].DATAIN +av_readdata[3] => av_readdata_pre[3].DATAIN +av_readdata[4] => av_readdata_pre[4].DATAIN +av_readdata[5] => av_readdata_pre[5].DATAIN +av_readdata[6] => av_readdata_pre[6].DATAIN +av_readdata[7] => av_readdata_pre[7].DATAIN +av_readdata[8] => av_readdata_pre[8].DATAIN +av_readdata[9] => av_readdata_pre[9].DATAIN +av_readdata[10] => av_readdata_pre[10].DATAIN +av_readdata[11] => av_readdata_pre[11].DATAIN +av_readdata[12] => av_readdata_pre[12].DATAIN +av_readdata[13] => av_readdata_pre[13].DATAIN +av_readdata[14] => av_readdata_pre[14].DATAIN +av_readdata[15] => av_readdata_pre[15].DATAIN +av_readdata[16] => av_readdata_pre[16].DATAIN +av_readdata[17] => av_readdata_pre[17].DATAIN +av_readdata[18] => av_readdata_pre[18].DATAIN +av_readdata[19] => av_readdata_pre[19].DATAIN +av_readdata[20] => av_readdata_pre[20].DATAIN +av_readdata[21] => av_readdata_pre[21].DATAIN +av_readdata[22] => av_readdata_pre[22].DATAIN +av_readdata[23] => av_readdata_pre[23].DATAIN +av_readdata[24] => av_readdata_pre[24].DATAIN +av_readdata[25] => av_readdata_pre[25].DATAIN +av_readdata[26] => av_readdata_pre[26].DATAIN +av_readdata[27] => av_readdata_pre[27].DATAIN +av_readdata[28] => av_readdata_pre[28].DATAIN +av_readdata[29] => av_readdata_pre[29].DATAIN +av_readdata[30] => av_readdata_pre[30].DATAIN +av_readdata[31] => av_readdata_pre[31].DATAIN +av_readdatavalid => ~NO_FANOUT~ +av_waitrequest => ~NO_FANOUT~ + + +|de0_nano_system|system:inst_cpu|altera_merlin_slave_translator:sys_clk_timer_s1_translator +clk => in_transfer.CLK +clk => end_beginbursttransfer.CLK +clk => end_begintransfer.CLK +clk => av_chipselect_pre.CLK +clk => av_outputenable_pre.CLK +clk => read_latency_shift_reg[0].CLK +clk => av_readdata_pre[0].CLK +clk => av_readdata_pre[1].CLK +clk => av_readdata_pre[2].CLK +clk => av_readdata_pre[3].CLK +clk => av_readdata_pre[4].CLK +clk => av_readdata_pre[5].CLK +clk => av_readdata_pre[6].CLK +clk => av_readdata_pre[7].CLK +clk => av_readdata_pre[8].CLK +clk => av_readdata_pre[9].CLK +clk => av_readdata_pre[10].CLK +clk => av_readdata_pre[11].CLK +clk => av_readdata_pre[12].CLK +clk => av_readdata_pre[13].CLK +clk => av_readdata_pre[14].CLK +clk => av_readdata_pre[15].CLK +clk => waitrequest_reset_override.CLK +clk => wait_latency_counter[0].CLK +clk => wait_latency_counter[1].CLK +reset => in_transfer.ACLR +reset => end_beginbursttransfer.ACLR +reset => end_begintransfer.ACLR +reset => av_chipselect_pre.ACLR +reset => av_outputenable_pre.ACLR +reset => read_latency_shift_reg[0].ACLR +reset => av_readdata_pre[0].ACLR +reset => av_readdata_pre[1].ACLR +reset => av_readdata_pre[2].ACLR +reset => av_readdata_pre[3].ACLR +reset => av_readdata_pre[4].ACLR +reset => av_readdata_pre[5].ACLR +reset => av_readdata_pre[6].ACLR +reset => av_readdata_pre[7].ACLR +reset => av_readdata_pre[8].ACLR +reset => av_readdata_pre[9].ACLR +reset => av_readdata_pre[10].ACLR +reset => av_readdata_pre[11].ACLR +reset => av_readdata_pre[12].ACLR +reset => av_readdata_pre[13].ACLR +reset => av_readdata_pre[14].ACLR +reset => av_readdata_pre[15].ACLR +reset => waitrequest_reset_override.PRESET +reset => wait_latency_counter[0].ACLR +reset => wait_latency_counter[1].ACLR +uav_address[0] => ~NO_FANOUT~ +uav_address[1] => ~NO_FANOUT~ +uav_address[2] => av_address[0].DATAIN +uav_address[3] => av_address[1].DATAIN +uav_address[4] => av_address[2].DATAIN +uav_address[5] => ~NO_FANOUT~ +uav_address[6] => ~NO_FANOUT~ +uav_address[7] => ~NO_FANOUT~ +uav_address[8] => ~NO_FANOUT~ +uav_address[9] => ~NO_FANOUT~ +uav_address[10] => ~NO_FANOUT~ +uav_address[11] => ~NO_FANOUT~ +uav_address[12] => ~NO_FANOUT~ +uav_address[13] => ~NO_FANOUT~ +uav_address[14] => ~NO_FANOUT~ +uav_address[15] => ~NO_FANOUT~ +uav_address[16] => ~NO_FANOUT~ +uav_address[17] => ~NO_FANOUT~ +uav_address[18] => ~NO_FANOUT~ +uav_address[19] => ~NO_FANOUT~ +uav_address[20] => ~NO_FANOUT~ +uav_address[21] => ~NO_FANOUT~ +uav_address[22] => ~NO_FANOUT~ +uav_address[23] => ~NO_FANOUT~ +uav_address[24] => ~NO_FANOUT~ +uav_address[25] => ~NO_FANOUT~ +uav_writedata[0] => av_writedata[0].DATAIN +uav_writedata[1] => av_writedata[1].DATAIN +uav_writedata[2] => av_writedata[2].DATAIN +uav_writedata[3] => av_writedata[3].DATAIN +uav_writedata[4] => av_writedata[4].DATAIN +uav_writedata[5] => av_writedata[5].DATAIN +uav_writedata[6] => av_writedata[6].DATAIN +uav_writedata[7] => av_writedata[7].DATAIN +uav_writedata[8] => av_writedata[8].DATAIN +uav_writedata[9] => av_writedata[9].DATAIN +uav_writedata[10] => av_writedata[10].DATAIN +uav_writedata[11] => av_writedata[11].DATAIN +uav_writedata[12] => av_writedata[12].DATAIN +uav_writedata[13] => av_writedata[13].DATAIN +uav_writedata[14] => av_writedata[14].DATAIN +uav_writedata[15] => av_writedata[15].DATAIN +uav_writedata[16] => ~NO_FANOUT~ +uav_writedata[17] => ~NO_FANOUT~ +uav_writedata[18] => ~NO_FANOUT~ +uav_writedata[19] => ~NO_FANOUT~ +uav_writedata[20] => ~NO_FANOUT~ +uav_writedata[21] => ~NO_FANOUT~ +uav_writedata[22] => ~NO_FANOUT~ +uav_writedata[23] => ~NO_FANOUT~ +uav_writedata[24] => ~NO_FANOUT~ +uav_writedata[25] => ~NO_FANOUT~ +uav_writedata[26] => ~NO_FANOUT~ +uav_writedata[27] => ~NO_FANOUT~ +uav_writedata[28] => ~NO_FANOUT~ +uav_writedata[29] => ~NO_FANOUT~ +uav_writedata[30] => ~NO_FANOUT~ +uav_writedata[31] => ~NO_FANOUT~ +uav_write => av_writebyteenable.IN0 +uav_write => av_write.IN1 +uav_write => av_waitrequest_generated.OUTPUTSELECT +uav_write => av_begintransfer.IN0 +uav_write => end_beginbursttransfer.IN1 +uav_write => always19.IN1 +uav_write => in_transfer.OUTPUTSELECT +uav_read => av_read.IN1 +uav_read => read_latency_shift_reg.IN1 +uav_read => av_outputenable.OUTPUTSELECT +uav_read => av_begintransfer.IN1 +uav_read => av_beginbursttransfer.OUTPUTSELECT +uav_burstcount[0] => Equal2.IN3 +uav_burstcount[1] => Equal2.IN2 +uav_burstcount[2] => av_burstcount[0].DATAIN +uav_burstcount[2] => Equal2.IN4 +uav_byteenable[0] => av_writebyteenable.IN1 +uav_byteenable[0] => av_byteenable[0].DATAIN +uav_byteenable[1] => ~NO_FANOUT~ +uav_byteenable[2] => ~NO_FANOUT~ +uav_byteenable[3] => ~NO_FANOUT~ +uav_lock => av_lock.DATAIN +uav_debugaccess => av_debugaccess.DATAIN +uav_clken => ~NO_FANOUT~ +uav_readdatavalid <= read_latency_shift_reg[0].DB_MAX_OUTPUT_PORT_TYPE +uav_waitrequest <= uav_waitrequest.DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[0] <= av_readdata_pre[0].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[1] <= av_readdata_pre[1].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[2] <= av_readdata_pre[2].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[3] <= av_readdata_pre[3].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[4] <= av_readdata_pre[4].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[5] <= av_readdata_pre[5].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[6] <= av_readdata_pre[6].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[7] <= av_readdata_pre[7].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[8] <= av_readdata_pre[8].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[9] <= av_readdata_pre[9].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[10] <= av_readdata_pre[10].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[11] <= av_readdata_pre[11].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[12] <= av_readdata_pre[12].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[13] <= av_readdata_pre[13].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[14] <= av_readdata_pre[14].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[15] <= av_readdata_pre[15].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[16] <= +uav_readdata[17] <= +uav_readdata[18] <= +uav_readdata[19] <= +uav_readdata[20] <= +uav_readdata[21] <= +uav_readdata[22] <= +uav_readdata[23] <= +uav_readdata[24] <= +uav_readdata[25] <= +uav_readdata[26] <= +uav_readdata[27] <= +uav_readdata[28] <= +uav_readdata[29] <= +uav_readdata[30] <= +uav_readdata[31] <= +av_address[0] <= uav_address[2].DB_MAX_OUTPUT_PORT_TYPE +av_address[1] <= uav_address[3].DB_MAX_OUTPUT_PORT_TYPE +av_address[2] <= uav_address[4].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[0] <= uav_writedata[0].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[1] <= uav_writedata[1].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[2] <= uav_writedata[2].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[3] <= uav_writedata[3].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[4] <= uav_writedata[4].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[5] <= uav_writedata[5].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[6] <= uav_writedata[6].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[7] <= uav_writedata[7].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[8] <= uav_writedata[8].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[9] <= uav_writedata[9].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[10] <= uav_writedata[10].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[11] <= uav_writedata[11].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[12] <= uav_writedata[12].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[13] <= uav_writedata[13].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[14] <= uav_writedata[14].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[15] <= uav_writedata[15].DB_MAX_OUTPUT_PORT_TYPE +av_write <= av_write.DB_MAX_OUTPUT_PORT_TYPE +av_read <= av_read.DB_MAX_OUTPUT_PORT_TYPE +av_burstcount[0] <= uav_burstcount[2].DB_MAX_OUTPUT_PORT_TYPE +av_byteenable[0] <= uav_byteenable[0].DB_MAX_OUTPUT_PORT_TYPE +av_writebyteenable[0] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE +av_begintransfer <= av_begintransfer.DB_MAX_OUTPUT_PORT_TYPE +av_chipselect <= av_chipselect.DB_MAX_OUTPUT_PORT_TYPE +av_beginbursttransfer <= av_beginbursttransfer.DB_MAX_OUTPUT_PORT_TYPE +av_lock <= uav_lock.DB_MAX_OUTPUT_PORT_TYPE +av_clken <= +av_debugaccess <= uav_debugaccess.DB_MAX_OUTPUT_PORT_TYPE +av_outputenable <= av_outputenable.DB_MAX_OUTPUT_PORT_TYPE +av_readdata[0] => av_readdata_pre[0].DATAIN +av_readdata[1] => av_readdata_pre[1].DATAIN +av_readdata[2] => av_readdata_pre[2].DATAIN +av_readdata[3] => av_readdata_pre[3].DATAIN +av_readdata[4] => av_readdata_pre[4].DATAIN +av_readdata[5] => av_readdata_pre[5].DATAIN +av_readdata[6] => av_readdata_pre[6].DATAIN +av_readdata[7] => av_readdata_pre[7].DATAIN +av_readdata[8] => av_readdata_pre[8].DATAIN +av_readdata[9] => av_readdata_pre[9].DATAIN +av_readdata[10] => av_readdata_pre[10].DATAIN +av_readdata[11] => av_readdata_pre[11].DATAIN +av_readdata[12] => av_readdata_pre[12].DATAIN +av_readdata[13] => av_readdata_pre[13].DATAIN +av_readdata[14] => av_readdata_pre[14].DATAIN +av_readdata[15] => av_readdata_pre[15].DATAIN +av_readdatavalid => ~NO_FANOUT~ +av_waitrequest => ~NO_FANOUT~ + + +|de0_nano_system|system:inst_cpu|altera_merlin_slave_translator:uart_0_s1_translator +clk => in_transfer.CLK +clk => end_beginbursttransfer.CLK +clk => end_begintransfer.CLK +clk => av_chipselect_pre.CLK +clk => av_outputenable_pre.CLK +clk => read_latency_shift_reg[0].CLK +clk => av_readdata_pre[0].CLK +clk => av_readdata_pre[1].CLK +clk => av_readdata_pre[2].CLK +clk => av_readdata_pre[3].CLK +clk => av_readdata_pre[4].CLK +clk => av_readdata_pre[5].CLK +clk => av_readdata_pre[6].CLK +clk => av_readdata_pre[7].CLK +clk => av_readdata_pre[8].CLK +clk => av_readdata_pre[9].CLK +clk => av_readdata_pre[10].CLK +clk => av_readdata_pre[11].CLK +clk => av_readdata_pre[12].CLK +clk => av_readdata_pre[13].CLK +clk => av_readdata_pre[14].CLK +clk => av_readdata_pre[15].CLK +clk => waitrequest_reset_override.CLK +clk => wait_latency_counter[0].CLK +clk => wait_latency_counter[1].CLK +reset => in_transfer.ACLR +reset => end_beginbursttransfer.ACLR +reset => end_begintransfer.ACLR +reset => av_chipselect_pre.ACLR +reset => av_outputenable_pre.ACLR +reset => read_latency_shift_reg[0].ACLR +reset => av_readdata_pre[0].ACLR +reset => av_readdata_pre[1].ACLR +reset => av_readdata_pre[2].ACLR +reset => av_readdata_pre[3].ACLR +reset => av_readdata_pre[4].ACLR +reset => av_readdata_pre[5].ACLR +reset => av_readdata_pre[6].ACLR +reset => av_readdata_pre[7].ACLR +reset => av_readdata_pre[8].ACLR +reset => av_readdata_pre[9].ACLR +reset => av_readdata_pre[10].ACLR +reset => av_readdata_pre[11].ACLR +reset => av_readdata_pre[12].ACLR +reset => av_readdata_pre[13].ACLR +reset => av_readdata_pre[14].ACLR +reset => av_readdata_pre[15].ACLR +reset => waitrequest_reset_override.PRESET +reset => wait_latency_counter[0].ACLR +reset => wait_latency_counter[1].ACLR +uav_address[0] => ~NO_FANOUT~ +uav_address[1] => ~NO_FANOUT~ +uav_address[2] => av_address[0].DATAIN +uav_address[3] => av_address[1].DATAIN +uav_address[4] => av_address[2].DATAIN +uav_address[5] => ~NO_FANOUT~ +uav_address[6] => ~NO_FANOUT~ +uav_address[7] => ~NO_FANOUT~ +uav_address[8] => ~NO_FANOUT~ +uav_address[9] => ~NO_FANOUT~ +uav_address[10] => ~NO_FANOUT~ +uav_address[11] => ~NO_FANOUT~ +uav_address[12] => ~NO_FANOUT~ +uav_address[13] => ~NO_FANOUT~ +uav_address[14] => ~NO_FANOUT~ +uav_address[15] => ~NO_FANOUT~ +uav_address[16] => ~NO_FANOUT~ +uav_address[17] => ~NO_FANOUT~ +uav_address[18] => ~NO_FANOUT~ +uav_address[19] => ~NO_FANOUT~ +uav_address[20] => ~NO_FANOUT~ +uav_address[21] => ~NO_FANOUT~ +uav_address[22] => ~NO_FANOUT~ +uav_address[23] => ~NO_FANOUT~ +uav_address[24] => ~NO_FANOUT~ +uav_address[25] => ~NO_FANOUT~ +uav_writedata[0] => av_writedata[0].DATAIN +uav_writedata[1] => av_writedata[1].DATAIN +uav_writedata[2] => av_writedata[2].DATAIN +uav_writedata[3] => av_writedata[3].DATAIN +uav_writedata[4] => av_writedata[4].DATAIN +uav_writedata[5] => av_writedata[5].DATAIN +uav_writedata[6] => av_writedata[6].DATAIN +uav_writedata[7] => av_writedata[7].DATAIN +uav_writedata[8] => av_writedata[8].DATAIN +uav_writedata[9] => av_writedata[9].DATAIN +uav_writedata[10] => av_writedata[10].DATAIN +uav_writedata[11] => av_writedata[11].DATAIN +uav_writedata[12] => av_writedata[12].DATAIN +uav_writedata[13] => av_writedata[13].DATAIN +uav_writedata[14] => av_writedata[14].DATAIN +uav_writedata[15] => av_writedata[15].DATAIN +uav_writedata[16] => ~NO_FANOUT~ +uav_writedata[17] => ~NO_FANOUT~ +uav_writedata[18] => ~NO_FANOUT~ +uav_writedata[19] => ~NO_FANOUT~ +uav_writedata[20] => ~NO_FANOUT~ +uav_writedata[21] => ~NO_FANOUT~ +uav_writedata[22] => ~NO_FANOUT~ +uav_writedata[23] => ~NO_FANOUT~ +uav_writedata[24] => ~NO_FANOUT~ +uav_writedata[25] => ~NO_FANOUT~ +uav_writedata[26] => ~NO_FANOUT~ +uav_writedata[27] => ~NO_FANOUT~ +uav_writedata[28] => ~NO_FANOUT~ +uav_writedata[29] => ~NO_FANOUT~ +uav_writedata[30] => ~NO_FANOUT~ +uav_writedata[31] => ~NO_FANOUT~ +uav_write => av_writebyteenable.IN0 +uav_write => av_write.IN1 +uav_write => av_begintransfer.IN0 +uav_write => end_beginbursttransfer.IN1 +uav_write => always19.IN1 +uav_write => in_transfer.OUTPUTSELECT +uav_read => av_read.IN1 +uav_read => read_latency_shift_reg.IN1 +uav_read => av_outputenable.OUTPUTSELECT +uav_read => av_begintransfer.IN1 +uav_read => av_beginbursttransfer.OUTPUTSELECT +uav_burstcount[0] => Equal1.IN3 +uav_burstcount[1] => Equal1.IN2 +uav_burstcount[2] => av_burstcount[0].DATAIN +uav_burstcount[2] => Equal1.IN4 +uav_byteenable[0] => av_writebyteenable.IN1 +uav_byteenable[0] => av_byteenable[0].DATAIN +uav_byteenable[1] => ~NO_FANOUT~ +uav_byteenable[2] => ~NO_FANOUT~ +uav_byteenable[3] => ~NO_FANOUT~ +uav_lock => av_lock.DATAIN +uav_debugaccess => av_debugaccess.DATAIN +uav_clken => ~NO_FANOUT~ +uav_readdatavalid <= read_latency_shift_reg[0].DB_MAX_OUTPUT_PORT_TYPE +uav_waitrequest <= uav_waitrequest.DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[0] <= av_readdata_pre[0].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[1] <= av_readdata_pre[1].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[2] <= av_readdata_pre[2].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[3] <= av_readdata_pre[3].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[4] <= av_readdata_pre[4].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[5] <= av_readdata_pre[5].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[6] <= av_readdata_pre[6].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[7] <= av_readdata_pre[7].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[8] <= av_readdata_pre[8].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[9] <= av_readdata_pre[9].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[10] <= av_readdata_pre[10].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[11] <= av_readdata_pre[11].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[12] <= av_readdata_pre[12].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[13] <= av_readdata_pre[13].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[14] <= av_readdata_pre[14].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[15] <= av_readdata_pre[15].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[16] <= +uav_readdata[17] <= +uav_readdata[18] <= +uav_readdata[19] <= +uav_readdata[20] <= +uav_readdata[21] <= +uav_readdata[22] <= +uav_readdata[23] <= +uav_readdata[24] <= +uav_readdata[25] <= +uav_readdata[26] <= +uav_readdata[27] <= +uav_readdata[28] <= +uav_readdata[29] <= +uav_readdata[30] <= +uav_readdata[31] <= +av_address[0] <= uav_address[2].DB_MAX_OUTPUT_PORT_TYPE +av_address[1] <= uav_address[3].DB_MAX_OUTPUT_PORT_TYPE +av_address[2] <= uav_address[4].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[0] <= uav_writedata[0].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[1] <= uav_writedata[1].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[2] <= uav_writedata[2].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[3] <= uav_writedata[3].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[4] <= uav_writedata[4].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[5] <= uav_writedata[5].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[6] <= uav_writedata[6].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[7] <= uav_writedata[7].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[8] <= uav_writedata[8].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[9] <= uav_writedata[9].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[10] <= uav_writedata[10].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[11] <= uav_writedata[11].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[12] <= uav_writedata[12].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[13] <= uav_writedata[13].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[14] <= uav_writedata[14].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[15] <= uav_writedata[15].DB_MAX_OUTPUT_PORT_TYPE +av_write <= av_write.DB_MAX_OUTPUT_PORT_TYPE +av_read <= av_read.DB_MAX_OUTPUT_PORT_TYPE +av_burstcount[0] <= uav_burstcount[2].DB_MAX_OUTPUT_PORT_TYPE +av_byteenable[0] <= uav_byteenable[0].DB_MAX_OUTPUT_PORT_TYPE +av_writebyteenable[0] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE +av_begintransfer <= av_begintransfer.DB_MAX_OUTPUT_PORT_TYPE +av_chipselect <= av_chipselect.DB_MAX_OUTPUT_PORT_TYPE +av_beginbursttransfer <= av_beginbursttransfer.DB_MAX_OUTPUT_PORT_TYPE +av_lock <= uav_lock.DB_MAX_OUTPUT_PORT_TYPE +av_clken <= +av_debugaccess <= uav_debugaccess.DB_MAX_OUTPUT_PORT_TYPE +av_outputenable <= av_outputenable.DB_MAX_OUTPUT_PORT_TYPE +av_readdata[0] => av_readdata_pre[0].DATAIN +av_readdata[1] => av_readdata_pre[1].DATAIN +av_readdata[2] => av_readdata_pre[2].DATAIN +av_readdata[3] => av_readdata_pre[3].DATAIN +av_readdata[4] => av_readdata_pre[4].DATAIN +av_readdata[5] => av_readdata_pre[5].DATAIN +av_readdata[6] => av_readdata_pre[6].DATAIN +av_readdata[7] => av_readdata_pre[7].DATAIN +av_readdata[8] => av_readdata_pre[8].DATAIN +av_readdata[9] => av_readdata_pre[9].DATAIN +av_readdata[10] => av_readdata_pre[10].DATAIN +av_readdata[11] => av_readdata_pre[11].DATAIN +av_readdata[12] => av_readdata_pre[12].DATAIN +av_readdata[13] => av_readdata_pre[13].DATAIN +av_readdata[14] => av_readdata_pre[14].DATAIN +av_readdata[15] => av_readdata_pre[15].DATAIN +av_readdatavalid => ~NO_FANOUT~ +av_waitrequest => ~NO_FANOUT~ + + +|de0_nano_system|system:inst_cpu|altera_merlin_slave_translator:pio_led_s1_translator +clk => in_transfer.CLK +clk => end_beginbursttransfer.CLK +clk => end_begintransfer.CLK +clk => av_chipselect_pre.CLK +clk => av_outputenable_pre.CLK +clk => read_latency_shift_reg[0].CLK +clk => av_readdata_pre[0].CLK +clk => av_readdata_pre[1].CLK +clk => av_readdata_pre[2].CLK +clk => av_readdata_pre[3].CLK +clk => av_readdata_pre[4].CLK +clk => av_readdata_pre[5].CLK +clk => av_readdata_pre[6].CLK +clk => av_readdata_pre[7].CLK +clk => av_readdata_pre[8].CLK +clk => av_readdata_pre[9].CLK +clk => av_readdata_pre[10].CLK +clk => av_readdata_pre[11].CLK +clk => av_readdata_pre[12].CLK +clk => av_readdata_pre[13].CLK +clk => av_readdata_pre[14].CLK +clk => av_readdata_pre[15].CLK +clk => av_readdata_pre[16].CLK +clk => av_readdata_pre[17].CLK +clk => av_readdata_pre[18].CLK +clk => av_readdata_pre[19].CLK +clk => av_readdata_pre[20].CLK +clk => av_readdata_pre[21].CLK +clk => av_readdata_pre[22].CLK +clk => av_readdata_pre[23].CLK +clk => av_readdata_pre[24].CLK +clk => av_readdata_pre[25].CLK +clk => av_readdata_pre[26].CLK +clk => av_readdata_pre[27].CLK +clk => av_readdata_pre[28].CLK +clk => av_readdata_pre[29].CLK +clk => av_readdata_pre[30].CLK +clk => av_readdata_pre[31].CLK +clk => waitrequest_reset_override.CLK +clk => wait_latency_counter[0].CLK +clk => wait_latency_counter[1].CLK +reset => in_transfer.ACLR +reset => end_beginbursttransfer.ACLR +reset => end_begintransfer.ACLR +reset => av_chipselect_pre.ACLR +reset => av_outputenable_pre.ACLR +reset => read_latency_shift_reg[0].ACLR +reset => av_readdata_pre[0].ACLR +reset => av_readdata_pre[1].ACLR +reset => av_readdata_pre[2].ACLR +reset => av_readdata_pre[3].ACLR +reset => av_readdata_pre[4].ACLR +reset => av_readdata_pre[5].ACLR +reset => av_readdata_pre[6].ACLR +reset => av_readdata_pre[7].ACLR +reset => av_readdata_pre[8].ACLR +reset => av_readdata_pre[9].ACLR +reset => av_readdata_pre[10].ACLR +reset => av_readdata_pre[11].ACLR +reset => av_readdata_pre[12].ACLR +reset => av_readdata_pre[13].ACLR +reset => av_readdata_pre[14].ACLR +reset => av_readdata_pre[15].ACLR +reset => av_readdata_pre[16].ACLR +reset => av_readdata_pre[17].ACLR +reset => av_readdata_pre[18].ACLR +reset => av_readdata_pre[19].ACLR +reset => av_readdata_pre[20].ACLR +reset => av_readdata_pre[21].ACLR +reset => av_readdata_pre[22].ACLR +reset => av_readdata_pre[23].ACLR +reset => av_readdata_pre[24].ACLR +reset => av_readdata_pre[25].ACLR +reset => av_readdata_pre[26].ACLR +reset => av_readdata_pre[27].ACLR +reset => av_readdata_pre[28].ACLR +reset => av_readdata_pre[29].ACLR +reset => av_readdata_pre[30].ACLR +reset => av_readdata_pre[31].ACLR +reset => waitrequest_reset_override.PRESET +reset => wait_latency_counter[0].ACLR +reset => wait_latency_counter[1].ACLR +uav_address[0] => ~NO_FANOUT~ +uav_address[1] => ~NO_FANOUT~ +uav_address[2] => av_address[0].DATAIN +uav_address[3] => av_address[1].DATAIN +uav_address[4] => av_address[2].DATAIN +uav_address[5] => ~NO_FANOUT~ +uav_address[6] => ~NO_FANOUT~ +uav_address[7] => ~NO_FANOUT~ +uav_address[8] => ~NO_FANOUT~ +uav_address[9] => ~NO_FANOUT~ +uav_address[10] => ~NO_FANOUT~ +uav_address[11] => ~NO_FANOUT~ +uav_address[12] => ~NO_FANOUT~ +uav_address[13] => ~NO_FANOUT~ +uav_address[14] => ~NO_FANOUT~ +uav_address[15] => ~NO_FANOUT~ +uav_address[16] => ~NO_FANOUT~ +uav_address[17] => ~NO_FANOUT~ +uav_address[18] => ~NO_FANOUT~ +uav_address[19] => ~NO_FANOUT~ +uav_address[20] => ~NO_FANOUT~ +uav_address[21] => ~NO_FANOUT~ +uav_address[22] => ~NO_FANOUT~ +uav_address[23] => ~NO_FANOUT~ +uav_address[24] => ~NO_FANOUT~ +uav_address[25] => ~NO_FANOUT~ +uav_writedata[0] => av_writedata[0].DATAIN +uav_writedata[1] => av_writedata[1].DATAIN +uav_writedata[2] => av_writedata[2].DATAIN +uav_writedata[3] => av_writedata[3].DATAIN +uav_writedata[4] => av_writedata[4].DATAIN +uav_writedata[5] => av_writedata[5].DATAIN +uav_writedata[6] => av_writedata[6].DATAIN +uav_writedata[7] => av_writedata[7].DATAIN +uav_writedata[8] => av_writedata[8].DATAIN +uav_writedata[9] => av_writedata[9].DATAIN +uav_writedata[10] => av_writedata[10].DATAIN +uav_writedata[11] => av_writedata[11].DATAIN +uav_writedata[12] => av_writedata[12].DATAIN +uav_writedata[13] => av_writedata[13].DATAIN +uav_writedata[14] => av_writedata[14].DATAIN +uav_writedata[15] => av_writedata[15].DATAIN +uav_writedata[16] => av_writedata[16].DATAIN +uav_writedata[17] => av_writedata[17].DATAIN +uav_writedata[18] => av_writedata[18].DATAIN +uav_writedata[19] => av_writedata[19].DATAIN +uav_writedata[20] => av_writedata[20].DATAIN +uav_writedata[21] => av_writedata[21].DATAIN +uav_writedata[22] => av_writedata[22].DATAIN +uav_writedata[23] => av_writedata[23].DATAIN +uav_writedata[24] => av_writedata[24].DATAIN +uav_writedata[25] => av_writedata[25].DATAIN +uav_writedata[26] => av_writedata[26].DATAIN +uav_writedata[27] => av_writedata[27].DATAIN +uav_writedata[28] => av_writedata[28].DATAIN +uav_writedata[29] => av_writedata[29].DATAIN +uav_writedata[30] => av_writedata[30].DATAIN +uav_writedata[31] => av_writedata[31].DATAIN +uav_write => av_writebyteenable.IN0 +uav_write => av_write.IN1 +uav_write => av_waitrequest_generated.OUTPUTSELECT +uav_write => av_begintransfer.IN0 +uav_write => end_beginbursttransfer.IN1 +uav_write => always19.IN1 +uav_write => in_transfer.OUTPUTSELECT +uav_read => av_read.IN1 +uav_read => read_latency_shift_reg.IN1 +uav_read => av_outputenable.OUTPUTSELECT +uav_read => av_begintransfer.IN1 +uav_read => av_beginbursttransfer.OUTPUTSELECT +uav_burstcount[0] => Equal2.IN3 +uav_burstcount[1] => Equal2.IN2 +uav_burstcount[2] => av_burstcount[0].DATAIN +uav_burstcount[2] => Equal2.IN4 +uav_byteenable[0] => av_writebyteenable.IN1 +uav_byteenable[0] => av_byteenable[0].DATAIN +uav_byteenable[1] => ~NO_FANOUT~ +uav_byteenable[2] => ~NO_FANOUT~ +uav_byteenable[3] => ~NO_FANOUT~ +uav_lock => av_lock.DATAIN +uav_debugaccess => av_debugaccess.DATAIN +uav_clken => ~NO_FANOUT~ +uav_readdatavalid <= read_latency_shift_reg[0].DB_MAX_OUTPUT_PORT_TYPE +uav_waitrequest <= uav_waitrequest.DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[0] <= av_readdata_pre[0].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[1] <= av_readdata_pre[1].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[2] <= av_readdata_pre[2].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[3] <= av_readdata_pre[3].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[4] <= av_readdata_pre[4].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[5] <= av_readdata_pre[5].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[6] <= av_readdata_pre[6].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[7] <= av_readdata_pre[7].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[8] <= av_readdata_pre[8].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[9] <= av_readdata_pre[9].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[10] <= av_readdata_pre[10].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[11] <= av_readdata_pre[11].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[12] <= av_readdata_pre[12].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[13] <= av_readdata_pre[13].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[14] <= av_readdata_pre[14].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[15] <= av_readdata_pre[15].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[16] <= av_readdata_pre[16].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[17] <= av_readdata_pre[17].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[18] <= av_readdata_pre[18].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[19] <= av_readdata_pre[19].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[20] <= av_readdata_pre[20].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[21] <= av_readdata_pre[21].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[22] <= av_readdata_pre[22].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[23] <= av_readdata_pre[23].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[24] <= av_readdata_pre[24].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[25] <= av_readdata_pre[25].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[26] <= av_readdata_pre[26].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[27] <= av_readdata_pre[27].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[28] <= av_readdata_pre[28].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[29] <= av_readdata_pre[29].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[30] <= av_readdata_pre[30].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[31] <= av_readdata_pre[31].DB_MAX_OUTPUT_PORT_TYPE +av_address[0] <= uav_address[2].DB_MAX_OUTPUT_PORT_TYPE +av_address[1] <= uav_address[3].DB_MAX_OUTPUT_PORT_TYPE +av_address[2] <= uav_address[4].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[0] <= uav_writedata[0].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[1] <= uav_writedata[1].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[2] <= uav_writedata[2].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[3] <= uav_writedata[3].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[4] <= uav_writedata[4].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[5] <= uav_writedata[5].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[6] <= uav_writedata[6].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[7] <= uav_writedata[7].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[8] <= uav_writedata[8].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[9] <= uav_writedata[9].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[10] <= uav_writedata[10].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[11] <= uav_writedata[11].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[12] <= uav_writedata[12].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[13] <= uav_writedata[13].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[14] <= uav_writedata[14].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[15] <= uav_writedata[15].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[16] <= uav_writedata[16].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[17] <= uav_writedata[17].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[18] <= uav_writedata[18].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[19] <= uav_writedata[19].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[20] <= uav_writedata[20].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[21] <= uav_writedata[21].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[22] <= uav_writedata[22].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[23] <= uav_writedata[23].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[24] <= uav_writedata[24].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[25] <= uav_writedata[25].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[26] <= uav_writedata[26].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[27] <= uav_writedata[27].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[28] <= uav_writedata[28].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[29] <= uav_writedata[29].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[30] <= uav_writedata[30].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[31] <= uav_writedata[31].DB_MAX_OUTPUT_PORT_TYPE +av_write <= av_write.DB_MAX_OUTPUT_PORT_TYPE +av_read <= av_read.DB_MAX_OUTPUT_PORT_TYPE +av_burstcount[0] <= uav_burstcount[2].DB_MAX_OUTPUT_PORT_TYPE +av_byteenable[0] <= uav_byteenable[0].DB_MAX_OUTPUT_PORT_TYPE +av_writebyteenable[0] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE +av_begintransfer <= av_begintransfer.DB_MAX_OUTPUT_PORT_TYPE +av_chipselect <= av_chipselect.DB_MAX_OUTPUT_PORT_TYPE +av_beginbursttransfer <= av_beginbursttransfer.DB_MAX_OUTPUT_PORT_TYPE +av_lock <= uav_lock.DB_MAX_OUTPUT_PORT_TYPE +av_clken <= +av_debugaccess <= uav_debugaccess.DB_MAX_OUTPUT_PORT_TYPE +av_outputenable <= av_outputenable.DB_MAX_OUTPUT_PORT_TYPE +av_readdata[0] => av_readdata_pre[0].DATAIN +av_readdata[1] => av_readdata_pre[1].DATAIN +av_readdata[2] => av_readdata_pre[2].DATAIN +av_readdata[3] => av_readdata_pre[3].DATAIN +av_readdata[4] => av_readdata_pre[4].DATAIN +av_readdata[5] => av_readdata_pre[5].DATAIN +av_readdata[6] => av_readdata_pre[6].DATAIN +av_readdata[7] => av_readdata_pre[7].DATAIN +av_readdata[8] => av_readdata_pre[8].DATAIN +av_readdata[9] => av_readdata_pre[9].DATAIN +av_readdata[10] => av_readdata_pre[10].DATAIN +av_readdata[11] => av_readdata_pre[11].DATAIN +av_readdata[12] => av_readdata_pre[12].DATAIN +av_readdata[13] => av_readdata_pre[13].DATAIN +av_readdata[14] => av_readdata_pre[14].DATAIN +av_readdata[15] => av_readdata_pre[15].DATAIN +av_readdata[16] => av_readdata_pre[16].DATAIN +av_readdata[17] => av_readdata_pre[17].DATAIN +av_readdata[18] => av_readdata_pre[18].DATAIN +av_readdata[19] => av_readdata_pre[19].DATAIN +av_readdata[20] => av_readdata_pre[20].DATAIN +av_readdata[21] => av_readdata_pre[21].DATAIN +av_readdata[22] => av_readdata_pre[22].DATAIN +av_readdata[23] => av_readdata_pre[23].DATAIN +av_readdata[24] => av_readdata_pre[24].DATAIN +av_readdata[25] => av_readdata_pre[25].DATAIN +av_readdata[26] => av_readdata_pre[26].DATAIN +av_readdata[27] => av_readdata_pre[27].DATAIN +av_readdata[28] => av_readdata_pre[28].DATAIN +av_readdata[29] => av_readdata_pre[29].DATAIN +av_readdata[30] => av_readdata_pre[30].DATAIN +av_readdata[31] => av_readdata_pre[31].DATAIN +av_readdatavalid => ~NO_FANOUT~ +av_waitrequest => ~NO_FANOUT~ + + +|de0_nano_system|system:inst_cpu|altera_merlin_slave_translator:pio_key_s1_translator +clk => in_transfer.CLK +clk => end_beginbursttransfer.CLK +clk => end_begintransfer.CLK +clk => av_chipselect_pre.CLK +clk => av_outputenable_pre.CLK +clk => read_latency_shift_reg[0].CLK +clk => av_readdata_pre[0].CLK +clk => av_readdata_pre[1].CLK +clk => av_readdata_pre[2].CLK +clk => av_readdata_pre[3].CLK +clk => av_readdata_pre[4].CLK +clk => av_readdata_pre[5].CLK +clk => av_readdata_pre[6].CLK +clk => av_readdata_pre[7].CLK +clk => av_readdata_pre[8].CLK +clk => av_readdata_pre[9].CLK +clk => av_readdata_pre[10].CLK +clk => av_readdata_pre[11].CLK +clk => av_readdata_pre[12].CLK +clk => av_readdata_pre[13].CLK +clk => av_readdata_pre[14].CLK +clk => av_readdata_pre[15].CLK +clk => av_readdata_pre[16].CLK +clk => av_readdata_pre[17].CLK +clk => av_readdata_pre[18].CLK +clk => av_readdata_pre[19].CLK +clk => av_readdata_pre[20].CLK +clk => av_readdata_pre[21].CLK +clk => av_readdata_pre[22].CLK +clk => av_readdata_pre[23].CLK +clk => av_readdata_pre[24].CLK +clk => av_readdata_pre[25].CLK +clk => av_readdata_pre[26].CLK +clk => av_readdata_pre[27].CLK +clk => av_readdata_pre[28].CLK +clk => av_readdata_pre[29].CLK +clk => av_readdata_pre[30].CLK +clk => av_readdata_pre[31].CLK +clk => waitrequest_reset_override.CLK +clk => wait_latency_counter[0].CLK +clk => wait_latency_counter[1].CLK +reset => in_transfer.ACLR +reset => end_beginbursttransfer.ACLR +reset => end_begintransfer.ACLR +reset => av_chipselect_pre.ACLR +reset => av_outputenable_pre.ACLR +reset => read_latency_shift_reg[0].ACLR +reset => av_readdata_pre[0].ACLR +reset => av_readdata_pre[1].ACLR +reset => av_readdata_pre[2].ACLR +reset => av_readdata_pre[3].ACLR +reset => av_readdata_pre[4].ACLR +reset => av_readdata_pre[5].ACLR +reset => av_readdata_pre[6].ACLR +reset => av_readdata_pre[7].ACLR +reset => av_readdata_pre[8].ACLR +reset => av_readdata_pre[9].ACLR +reset => av_readdata_pre[10].ACLR +reset => av_readdata_pre[11].ACLR +reset => av_readdata_pre[12].ACLR +reset => av_readdata_pre[13].ACLR +reset => av_readdata_pre[14].ACLR +reset => av_readdata_pre[15].ACLR +reset => av_readdata_pre[16].ACLR +reset => av_readdata_pre[17].ACLR +reset => av_readdata_pre[18].ACLR +reset => av_readdata_pre[19].ACLR +reset => av_readdata_pre[20].ACLR +reset => av_readdata_pre[21].ACLR +reset => av_readdata_pre[22].ACLR +reset => av_readdata_pre[23].ACLR +reset => av_readdata_pre[24].ACLR +reset => av_readdata_pre[25].ACLR +reset => av_readdata_pre[26].ACLR +reset => av_readdata_pre[27].ACLR +reset => av_readdata_pre[28].ACLR +reset => av_readdata_pre[29].ACLR +reset => av_readdata_pre[30].ACLR +reset => av_readdata_pre[31].ACLR +reset => waitrequest_reset_override.PRESET +reset => wait_latency_counter[0].ACLR +reset => wait_latency_counter[1].ACLR +uav_address[0] => ~NO_FANOUT~ +uav_address[1] => ~NO_FANOUT~ +uav_address[2] => av_address[0].DATAIN +uav_address[3] => av_address[1].DATAIN +uav_address[4] => ~NO_FANOUT~ +uav_address[5] => ~NO_FANOUT~ +uav_address[6] => ~NO_FANOUT~ +uav_address[7] => ~NO_FANOUT~ +uav_address[8] => ~NO_FANOUT~ +uav_address[9] => ~NO_FANOUT~ +uav_address[10] => ~NO_FANOUT~ +uav_address[11] => ~NO_FANOUT~ +uav_address[12] => ~NO_FANOUT~ +uav_address[13] => ~NO_FANOUT~ +uav_address[14] => ~NO_FANOUT~ +uav_address[15] => ~NO_FANOUT~ +uav_address[16] => ~NO_FANOUT~ +uav_address[17] => ~NO_FANOUT~ +uav_address[18] => ~NO_FANOUT~ +uav_address[19] => ~NO_FANOUT~ +uav_address[20] => ~NO_FANOUT~ +uav_address[21] => ~NO_FANOUT~ +uav_address[22] => ~NO_FANOUT~ +uav_address[23] => ~NO_FANOUT~ +uav_address[24] => ~NO_FANOUT~ +uav_address[25] => ~NO_FANOUT~ +uav_writedata[0] => av_writedata[0].DATAIN +uav_writedata[1] => av_writedata[1].DATAIN +uav_writedata[2] => av_writedata[2].DATAIN +uav_writedata[3] => av_writedata[3].DATAIN +uav_writedata[4] => av_writedata[4].DATAIN +uav_writedata[5] => av_writedata[5].DATAIN +uav_writedata[6] => av_writedata[6].DATAIN +uav_writedata[7] => av_writedata[7].DATAIN +uav_writedata[8] => av_writedata[8].DATAIN +uav_writedata[9] => av_writedata[9].DATAIN +uav_writedata[10] => av_writedata[10].DATAIN +uav_writedata[11] => av_writedata[11].DATAIN +uav_writedata[12] => av_writedata[12].DATAIN +uav_writedata[13] => av_writedata[13].DATAIN +uav_writedata[14] => av_writedata[14].DATAIN +uav_writedata[15] => av_writedata[15].DATAIN +uav_writedata[16] => av_writedata[16].DATAIN +uav_writedata[17] => av_writedata[17].DATAIN +uav_writedata[18] => av_writedata[18].DATAIN +uav_writedata[19] => av_writedata[19].DATAIN +uav_writedata[20] => av_writedata[20].DATAIN +uav_writedata[21] => av_writedata[21].DATAIN +uav_writedata[22] => av_writedata[22].DATAIN +uav_writedata[23] => av_writedata[23].DATAIN +uav_writedata[24] => av_writedata[24].DATAIN +uav_writedata[25] => av_writedata[25].DATAIN +uav_writedata[26] => av_writedata[26].DATAIN +uav_writedata[27] => av_writedata[27].DATAIN +uav_writedata[28] => av_writedata[28].DATAIN +uav_writedata[29] => av_writedata[29].DATAIN +uav_writedata[30] => av_writedata[30].DATAIN +uav_writedata[31] => av_writedata[31].DATAIN +uav_write => av_writebyteenable.IN0 +uav_write => av_write.IN1 +uav_write => av_waitrequest_generated.OUTPUTSELECT +uav_write => av_begintransfer.IN0 +uav_write => end_beginbursttransfer.IN1 +uav_write => always19.IN1 +uav_write => in_transfer.OUTPUTSELECT +uav_read => av_read.IN1 +uav_read => read_latency_shift_reg.IN1 +uav_read => av_outputenable.OUTPUTSELECT +uav_read => av_begintransfer.IN1 +uav_read => av_beginbursttransfer.OUTPUTSELECT +uav_burstcount[0] => Equal2.IN3 +uav_burstcount[1] => Equal2.IN2 +uav_burstcount[2] => av_burstcount[0].DATAIN +uav_burstcount[2] => Equal2.IN4 +uav_byteenable[0] => av_writebyteenable.IN1 +uav_byteenable[0] => av_byteenable[0].DATAIN +uav_byteenable[1] => ~NO_FANOUT~ +uav_byteenable[2] => ~NO_FANOUT~ +uav_byteenable[3] => ~NO_FANOUT~ +uav_lock => av_lock.DATAIN +uav_debugaccess => av_debugaccess.DATAIN +uav_clken => ~NO_FANOUT~ +uav_readdatavalid <= read_latency_shift_reg[0].DB_MAX_OUTPUT_PORT_TYPE +uav_waitrequest <= uav_waitrequest.DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[0] <= av_readdata_pre[0].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[1] <= av_readdata_pre[1].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[2] <= av_readdata_pre[2].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[3] <= av_readdata_pre[3].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[4] <= av_readdata_pre[4].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[5] <= av_readdata_pre[5].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[6] <= av_readdata_pre[6].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[7] <= av_readdata_pre[7].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[8] <= av_readdata_pre[8].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[9] <= av_readdata_pre[9].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[10] <= av_readdata_pre[10].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[11] <= av_readdata_pre[11].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[12] <= av_readdata_pre[12].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[13] <= av_readdata_pre[13].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[14] <= av_readdata_pre[14].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[15] <= av_readdata_pre[15].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[16] <= av_readdata_pre[16].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[17] <= av_readdata_pre[17].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[18] <= av_readdata_pre[18].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[19] <= av_readdata_pre[19].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[20] <= av_readdata_pre[20].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[21] <= av_readdata_pre[21].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[22] <= av_readdata_pre[22].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[23] <= av_readdata_pre[23].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[24] <= av_readdata_pre[24].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[25] <= av_readdata_pre[25].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[26] <= av_readdata_pre[26].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[27] <= av_readdata_pre[27].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[28] <= av_readdata_pre[28].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[29] <= av_readdata_pre[29].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[30] <= av_readdata_pre[30].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[31] <= av_readdata_pre[31].DB_MAX_OUTPUT_PORT_TYPE +av_address[0] <= uav_address[2].DB_MAX_OUTPUT_PORT_TYPE +av_address[1] <= uav_address[3].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[0] <= uav_writedata[0].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[1] <= uav_writedata[1].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[2] <= uav_writedata[2].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[3] <= uav_writedata[3].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[4] <= uav_writedata[4].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[5] <= uav_writedata[5].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[6] <= uav_writedata[6].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[7] <= uav_writedata[7].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[8] <= uav_writedata[8].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[9] <= uav_writedata[9].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[10] <= uav_writedata[10].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[11] <= uav_writedata[11].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[12] <= uav_writedata[12].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[13] <= uav_writedata[13].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[14] <= uav_writedata[14].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[15] <= uav_writedata[15].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[16] <= uav_writedata[16].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[17] <= uav_writedata[17].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[18] <= uav_writedata[18].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[19] <= uav_writedata[19].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[20] <= uav_writedata[20].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[21] <= uav_writedata[21].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[22] <= uav_writedata[22].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[23] <= uav_writedata[23].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[24] <= uav_writedata[24].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[25] <= uav_writedata[25].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[26] <= uav_writedata[26].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[27] <= uav_writedata[27].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[28] <= uav_writedata[28].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[29] <= uav_writedata[29].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[30] <= uav_writedata[30].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[31] <= uav_writedata[31].DB_MAX_OUTPUT_PORT_TYPE +av_write <= av_write.DB_MAX_OUTPUT_PORT_TYPE +av_read <= av_read.DB_MAX_OUTPUT_PORT_TYPE +av_burstcount[0] <= uav_burstcount[2].DB_MAX_OUTPUT_PORT_TYPE +av_byteenable[0] <= uav_byteenable[0].DB_MAX_OUTPUT_PORT_TYPE +av_writebyteenable[0] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE +av_begintransfer <= av_begintransfer.DB_MAX_OUTPUT_PORT_TYPE +av_chipselect <= av_chipselect.DB_MAX_OUTPUT_PORT_TYPE +av_beginbursttransfer <= av_beginbursttransfer.DB_MAX_OUTPUT_PORT_TYPE +av_lock <= uav_lock.DB_MAX_OUTPUT_PORT_TYPE +av_clken <= +av_debugaccess <= uav_debugaccess.DB_MAX_OUTPUT_PORT_TYPE +av_outputenable <= av_outputenable.DB_MAX_OUTPUT_PORT_TYPE +av_readdata[0] => av_readdata_pre[0].DATAIN +av_readdata[1] => av_readdata_pre[1].DATAIN +av_readdata[2] => av_readdata_pre[2].DATAIN +av_readdata[3] => av_readdata_pre[3].DATAIN +av_readdata[4] => av_readdata_pre[4].DATAIN +av_readdata[5] => av_readdata_pre[5].DATAIN +av_readdata[6] => av_readdata_pre[6].DATAIN +av_readdata[7] => av_readdata_pre[7].DATAIN +av_readdata[8] => av_readdata_pre[8].DATAIN +av_readdata[9] => av_readdata_pre[9].DATAIN +av_readdata[10] => av_readdata_pre[10].DATAIN +av_readdata[11] => av_readdata_pre[11].DATAIN +av_readdata[12] => av_readdata_pre[12].DATAIN +av_readdata[13] => av_readdata_pre[13].DATAIN +av_readdata[14] => av_readdata_pre[14].DATAIN +av_readdata[15] => av_readdata_pre[15].DATAIN +av_readdata[16] => av_readdata_pre[16].DATAIN +av_readdata[17] => av_readdata_pre[17].DATAIN +av_readdata[18] => av_readdata_pre[18].DATAIN +av_readdata[19] => av_readdata_pre[19].DATAIN +av_readdata[20] => av_readdata_pre[20].DATAIN +av_readdata[21] => av_readdata_pre[21].DATAIN +av_readdata[22] => av_readdata_pre[22].DATAIN +av_readdata[23] => av_readdata_pre[23].DATAIN +av_readdata[24] => av_readdata_pre[24].DATAIN +av_readdata[25] => av_readdata_pre[25].DATAIN +av_readdata[26] => av_readdata_pre[26].DATAIN +av_readdata[27] => av_readdata_pre[27].DATAIN +av_readdata[28] => av_readdata_pre[28].DATAIN +av_readdata[29] => av_readdata_pre[29].DATAIN +av_readdata[30] => av_readdata_pre[30].DATAIN +av_readdata[31] => av_readdata_pre[31].DATAIN +av_readdatavalid => ~NO_FANOUT~ +av_waitrequest => ~NO_FANOUT~ + + +|de0_nano_system|system:inst_cpu|altera_merlin_slave_translator:pio_sw_s1_translator +clk => in_transfer.CLK +clk => end_beginbursttransfer.CLK +clk => end_begintransfer.CLK +clk => av_chipselect_pre.CLK +clk => av_outputenable_pre.CLK +clk => read_latency_shift_reg[0].CLK +clk => av_readdata_pre[0].CLK +clk => av_readdata_pre[1].CLK +clk => av_readdata_pre[2].CLK +clk => av_readdata_pre[3].CLK +clk => av_readdata_pre[4].CLK +clk => av_readdata_pre[5].CLK +clk => av_readdata_pre[6].CLK +clk => av_readdata_pre[7].CLK +clk => av_readdata_pre[8].CLK +clk => av_readdata_pre[9].CLK +clk => av_readdata_pre[10].CLK +clk => av_readdata_pre[11].CLK +clk => av_readdata_pre[12].CLK +clk => av_readdata_pre[13].CLK +clk => av_readdata_pre[14].CLK +clk => av_readdata_pre[15].CLK +clk => av_readdata_pre[16].CLK +clk => av_readdata_pre[17].CLK +clk => av_readdata_pre[18].CLK +clk => av_readdata_pre[19].CLK +clk => av_readdata_pre[20].CLK +clk => av_readdata_pre[21].CLK +clk => av_readdata_pre[22].CLK +clk => av_readdata_pre[23].CLK +clk => av_readdata_pre[24].CLK +clk => av_readdata_pre[25].CLK +clk => av_readdata_pre[26].CLK +clk => av_readdata_pre[27].CLK +clk => av_readdata_pre[28].CLK +clk => av_readdata_pre[29].CLK +clk => av_readdata_pre[30].CLK +clk => av_readdata_pre[31].CLK +clk => waitrequest_reset_override.CLK +clk => wait_latency_counter[0].CLK +clk => wait_latency_counter[1].CLK +reset => in_transfer.ACLR +reset => end_beginbursttransfer.ACLR +reset => end_begintransfer.ACLR +reset => av_chipselect_pre.ACLR +reset => av_outputenable_pre.ACLR +reset => read_latency_shift_reg[0].ACLR +reset => av_readdata_pre[0].ACLR +reset => av_readdata_pre[1].ACLR +reset => av_readdata_pre[2].ACLR +reset => av_readdata_pre[3].ACLR +reset => av_readdata_pre[4].ACLR +reset => av_readdata_pre[5].ACLR +reset => av_readdata_pre[6].ACLR +reset => av_readdata_pre[7].ACLR +reset => av_readdata_pre[8].ACLR +reset => av_readdata_pre[9].ACLR +reset => av_readdata_pre[10].ACLR +reset => av_readdata_pre[11].ACLR +reset => av_readdata_pre[12].ACLR +reset => av_readdata_pre[13].ACLR +reset => av_readdata_pre[14].ACLR +reset => av_readdata_pre[15].ACLR +reset => av_readdata_pre[16].ACLR +reset => av_readdata_pre[17].ACLR +reset => av_readdata_pre[18].ACLR +reset => av_readdata_pre[19].ACLR +reset => av_readdata_pre[20].ACLR +reset => av_readdata_pre[21].ACLR +reset => av_readdata_pre[22].ACLR +reset => av_readdata_pre[23].ACLR +reset => av_readdata_pre[24].ACLR +reset => av_readdata_pre[25].ACLR +reset => av_readdata_pre[26].ACLR +reset => av_readdata_pre[27].ACLR +reset => av_readdata_pre[28].ACLR +reset => av_readdata_pre[29].ACLR +reset => av_readdata_pre[30].ACLR +reset => av_readdata_pre[31].ACLR +reset => waitrequest_reset_override.PRESET +reset => wait_latency_counter[0].ACLR +reset => wait_latency_counter[1].ACLR +uav_address[0] => ~NO_FANOUT~ +uav_address[1] => ~NO_FANOUT~ +uav_address[2] => av_address[0].DATAIN +uav_address[3] => av_address[1].DATAIN +uav_address[4] => ~NO_FANOUT~ +uav_address[5] => ~NO_FANOUT~ +uav_address[6] => ~NO_FANOUT~ +uav_address[7] => ~NO_FANOUT~ +uav_address[8] => ~NO_FANOUT~ +uav_address[9] => ~NO_FANOUT~ +uav_address[10] => ~NO_FANOUT~ +uav_address[11] => ~NO_FANOUT~ +uav_address[12] => ~NO_FANOUT~ +uav_address[13] => ~NO_FANOUT~ +uav_address[14] => ~NO_FANOUT~ +uav_address[15] => ~NO_FANOUT~ +uav_address[16] => ~NO_FANOUT~ +uav_address[17] => ~NO_FANOUT~ +uav_address[18] => ~NO_FANOUT~ +uav_address[19] => ~NO_FANOUT~ +uav_address[20] => ~NO_FANOUT~ +uav_address[21] => ~NO_FANOUT~ +uav_address[22] => ~NO_FANOUT~ +uav_address[23] => ~NO_FANOUT~ +uav_address[24] => ~NO_FANOUT~ +uav_address[25] => ~NO_FANOUT~ +uav_writedata[0] => av_writedata[0].DATAIN +uav_writedata[1] => av_writedata[1].DATAIN +uav_writedata[2] => av_writedata[2].DATAIN +uav_writedata[3] => av_writedata[3].DATAIN +uav_writedata[4] => av_writedata[4].DATAIN +uav_writedata[5] => av_writedata[5].DATAIN +uav_writedata[6] => av_writedata[6].DATAIN +uav_writedata[7] => av_writedata[7].DATAIN +uav_writedata[8] => av_writedata[8].DATAIN +uav_writedata[9] => av_writedata[9].DATAIN +uav_writedata[10] => av_writedata[10].DATAIN +uav_writedata[11] => av_writedata[11].DATAIN +uav_writedata[12] => av_writedata[12].DATAIN +uav_writedata[13] => av_writedata[13].DATAIN +uav_writedata[14] => av_writedata[14].DATAIN +uav_writedata[15] => av_writedata[15].DATAIN +uav_writedata[16] => av_writedata[16].DATAIN +uav_writedata[17] => av_writedata[17].DATAIN +uav_writedata[18] => av_writedata[18].DATAIN +uav_writedata[19] => av_writedata[19].DATAIN +uav_writedata[20] => av_writedata[20].DATAIN +uav_writedata[21] => av_writedata[21].DATAIN +uav_writedata[22] => av_writedata[22].DATAIN +uav_writedata[23] => av_writedata[23].DATAIN +uav_writedata[24] => av_writedata[24].DATAIN +uav_writedata[25] => av_writedata[25].DATAIN +uav_writedata[26] => av_writedata[26].DATAIN +uav_writedata[27] => av_writedata[27].DATAIN +uav_writedata[28] => av_writedata[28].DATAIN +uav_writedata[29] => av_writedata[29].DATAIN +uav_writedata[30] => av_writedata[30].DATAIN +uav_writedata[31] => av_writedata[31].DATAIN +uav_write => av_writebyteenable.IN0 +uav_write => av_write.IN1 +uav_write => av_waitrequest_generated.OUTPUTSELECT +uav_write => av_begintransfer.IN0 +uav_write => end_beginbursttransfer.IN1 +uav_write => always19.IN1 +uav_write => in_transfer.OUTPUTSELECT +uav_read => av_read.IN1 +uav_read => read_latency_shift_reg.IN1 +uav_read => av_outputenable.OUTPUTSELECT +uav_read => av_begintransfer.IN1 +uav_read => av_beginbursttransfer.OUTPUTSELECT +uav_burstcount[0] => Equal2.IN3 +uav_burstcount[1] => Equal2.IN2 +uav_burstcount[2] => av_burstcount[0].DATAIN +uav_burstcount[2] => Equal2.IN4 +uav_byteenable[0] => av_writebyteenable.IN1 +uav_byteenable[0] => av_byteenable[0].DATAIN +uav_byteenable[1] => ~NO_FANOUT~ +uav_byteenable[2] => ~NO_FANOUT~ +uav_byteenable[3] => ~NO_FANOUT~ +uav_lock => av_lock.DATAIN +uav_debugaccess => av_debugaccess.DATAIN +uav_clken => ~NO_FANOUT~ +uav_readdatavalid <= read_latency_shift_reg[0].DB_MAX_OUTPUT_PORT_TYPE +uav_waitrequest <= uav_waitrequest.DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[0] <= av_readdata_pre[0].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[1] <= av_readdata_pre[1].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[2] <= av_readdata_pre[2].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[3] <= av_readdata_pre[3].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[4] <= av_readdata_pre[4].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[5] <= av_readdata_pre[5].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[6] <= av_readdata_pre[6].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[7] <= av_readdata_pre[7].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[8] <= av_readdata_pre[8].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[9] <= av_readdata_pre[9].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[10] <= av_readdata_pre[10].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[11] <= av_readdata_pre[11].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[12] <= av_readdata_pre[12].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[13] <= av_readdata_pre[13].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[14] <= av_readdata_pre[14].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[15] <= av_readdata_pre[15].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[16] <= av_readdata_pre[16].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[17] <= av_readdata_pre[17].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[18] <= av_readdata_pre[18].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[19] <= av_readdata_pre[19].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[20] <= av_readdata_pre[20].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[21] <= av_readdata_pre[21].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[22] <= av_readdata_pre[22].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[23] <= av_readdata_pre[23].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[24] <= av_readdata_pre[24].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[25] <= av_readdata_pre[25].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[26] <= av_readdata_pre[26].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[27] <= av_readdata_pre[27].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[28] <= av_readdata_pre[28].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[29] <= av_readdata_pre[29].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[30] <= av_readdata_pre[30].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[31] <= av_readdata_pre[31].DB_MAX_OUTPUT_PORT_TYPE +av_address[0] <= uav_address[2].DB_MAX_OUTPUT_PORT_TYPE +av_address[1] <= uav_address[3].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[0] <= uav_writedata[0].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[1] <= uav_writedata[1].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[2] <= uav_writedata[2].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[3] <= uav_writedata[3].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[4] <= uav_writedata[4].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[5] <= uav_writedata[5].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[6] <= uav_writedata[6].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[7] <= uav_writedata[7].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[8] <= uav_writedata[8].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[9] <= uav_writedata[9].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[10] <= uav_writedata[10].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[11] <= uav_writedata[11].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[12] <= uav_writedata[12].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[13] <= uav_writedata[13].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[14] <= uav_writedata[14].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[15] <= uav_writedata[15].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[16] <= uav_writedata[16].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[17] <= uav_writedata[17].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[18] <= uav_writedata[18].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[19] <= uav_writedata[19].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[20] <= uav_writedata[20].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[21] <= uav_writedata[21].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[22] <= uav_writedata[22].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[23] <= uav_writedata[23].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[24] <= uav_writedata[24].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[25] <= uav_writedata[25].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[26] <= uav_writedata[26].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[27] <= uav_writedata[27].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[28] <= uav_writedata[28].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[29] <= uav_writedata[29].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[30] <= uav_writedata[30].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[31] <= uav_writedata[31].DB_MAX_OUTPUT_PORT_TYPE +av_write <= av_write.DB_MAX_OUTPUT_PORT_TYPE +av_read <= av_read.DB_MAX_OUTPUT_PORT_TYPE +av_burstcount[0] <= uav_burstcount[2].DB_MAX_OUTPUT_PORT_TYPE +av_byteenable[0] <= uav_byteenable[0].DB_MAX_OUTPUT_PORT_TYPE +av_writebyteenable[0] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE +av_begintransfer <= av_begintransfer.DB_MAX_OUTPUT_PORT_TYPE +av_chipselect <= av_chipselect.DB_MAX_OUTPUT_PORT_TYPE +av_beginbursttransfer <= av_beginbursttransfer.DB_MAX_OUTPUT_PORT_TYPE +av_lock <= uav_lock.DB_MAX_OUTPUT_PORT_TYPE +av_clken <= +av_debugaccess <= uav_debugaccess.DB_MAX_OUTPUT_PORT_TYPE +av_outputenable <= av_outputenable.DB_MAX_OUTPUT_PORT_TYPE +av_readdata[0] => av_readdata_pre[0].DATAIN +av_readdata[1] => av_readdata_pre[1].DATAIN +av_readdata[2] => av_readdata_pre[2].DATAIN +av_readdata[3] => av_readdata_pre[3].DATAIN +av_readdata[4] => av_readdata_pre[4].DATAIN +av_readdata[5] => av_readdata_pre[5].DATAIN +av_readdata[6] => av_readdata_pre[6].DATAIN +av_readdata[7] => av_readdata_pre[7].DATAIN +av_readdata[8] => av_readdata_pre[8].DATAIN +av_readdata[9] => av_readdata_pre[9].DATAIN +av_readdata[10] => av_readdata_pre[10].DATAIN +av_readdata[11] => av_readdata_pre[11].DATAIN +av_readdata[12] => av_readdata_pre[12].DATAIN +av_readdata[13] => av_readdata_pre[13].DATAIN +av_readdata[14] => av_readdata_pre[14].DATAIN +av_readdata[15] => av_readdata_pre[15].DATAIN +av_readdata[16] => av_readdata_pre[16].DATAIN +av_readdata[17] => av_readdata_pre[17].DATAIN +av_readdata[18] => av_readdata_pre[18].DATAIN +av_readdata[19] => av_readdata_pre[19].DATAIN +av_readdata[20] => av_readdata_pre[20].DATAIN +av_readdata[21] => av_readdata_pre[21].DATAIN +av_readdata[22] => av_readdata_pre[22].DATAIN +av_readdata[23] => av_readdata_pre[23].DATAIN +av_readdata[24] => av_readdata_pre[24].DATAIN +av_readdata[25] => av_readdata_pre[25].DATAIN +av_readdata[26] => av_readdata_pre[26].DATAIN +av_readdata[27] => av_readdata_pre[27].DATAIN +av_readdata[28] => av_readdata_pre[28].DATAIN +av_readdata[29] => av_readdata_pre[29].DATAIN +av_readdata[30] => av_readdata_pre[30].DATAIN +av_readdata[31] => av_readdata_pre[31].DATAIN +av_readdatavalid => ~NO_FANOUT~ +av_waitrequest => ~NO_FANOUT~ + + +|de0_nano_system|system:inst_cpu|altera_merlin_slave_translator:jtag_uart_0_avalon_jtag_slave_translator +clk => in_transfer.CLK +clk => end_beginbursttransfer.CLK +clk => end_begintransfer.CLK +clk => av_chipselect_pre.CLK +clk => av_outputenable_pre.CLK +clk => read_latency_shift_reg[0].CLK +clk => av_readdata_pre[0].CLK +clk => av_readdata_pre[1].CLK +clk => av_readdata_pre[2].CLK +clk => av_readdata_pre[3].CLK +clk => av_readdata_pre[4].CLK +clk => av_readdata_pre[5].CLK +clk => av_readdata_pre[6].CLK +clk => av_readdata_pre[7].CLK +clk => av_readdata_pre[8].CLK +clk => av_readdata_pre[9].CLK +clk => av_readdata_pre[10].CLK +clk => av_readdata_pre[11].CLK +clk => av_readdata_pre[12].CLK +clk => av_readdata_pre[13].CLK +clk => av_readdata_pre[14].CLK +clk => av_readdata_pre[15].CLK +clk => av_readdata_pre[16].CLK +clk => av_readdata_pre[17].CLK +clk => av_readdata_pre[18].CLK +clk => av_readdata_pre[19].CLK +clk => av_readdata_pre[20].CLK +clk => av_readdata_pre[21].CLK +clk => av_readdata_pre[22].CLK +clk => av_readdata_pre[23].CLK +clk => av_readdata_pre[24].CLK +clk => av_readdata_pre[25].CLK +clk => av_readdata_pre[26].CLK +clk => av_readdata_pre[27].CLK +clk => av_readdata_pre[28].CLK +clk => av_readdata_pre[29].CLK +clk => av_readdata_pre[30].CLK +clk => av_readdata_pre[31].CLK +clk => waitrequest_reset_override.CLK +reset => in_transfer.ACLR +reset => end_beginbursttransfer.ACLR +reset => end_begintransfer.ACLR +reset => av_chipselect_pre.ACLR +reset => av_outputenable_pre.ACLR +reset => read_latency_shift_reg[0].ACLR +reset => av_readdata_pre[0].ACLR +reset => av_readdata_pre[1].ACLR +reset => av_readdata_pre[2].ACLR +reset => av_readdata_pre[3].ACLR +reset => av_readdata_pre[4].ACLR +reset => av_readdata_pre[5].ACLR +reset => av_readdata_pre[6].ACLR +reset => av_readdata_pre[7].ACLR +reset => av_readdata_pre[8].ACLR +reset => av_readdata_pre[9].ACLR +reset => av_readdata_pre[10].ACLR +reset => av_readdata_pre[11].ACLR +reset => av_readdata_pre[12].ACLR +reset => av_readdata_pre[13].ACLR +reset => av_readdata_pre[14].ACLR +reset => av_readdata_pre[15].ACLR +reset => av_readdata_pre[16].ACLR +reset => av_readdata_pre[17].ACLR +reset => av_readdata_pre[18].ACLR +reset => av_readdata_pre[19].ACLR +reset => av_readdata_pre[20].ACLR +reset => av_readdata_pre[21].ACLR +reset => av_readdata_pre[22].ACLR +reset => av_readdata_pre[23].ACLR +reset => av_readdata_pre[24].ACLR +reset => av_readdata_pre[25].ACLR +reset => av_readdata_pre[26].ACLR +reset => av_readdata_pre[27].ACLR +reset => av_readdata_pre[28].ACLR +reset => av_readdata_pre[29].ACLR +reset => av_readdata_pre[30].ACLR +reset => av_readdata_pre[31].ACLR +reset => waitrequest_reset_override.PRESET +uav_address[0] => ~NO_FANOUT~ +uav_address[1] => ~NO_FANOUT~ +uav_address[2] => av_address[0].DATAIN +uav_address[3] => ~NO_FANOUT~ +uav_address[4] => ~NO_FANOUT~ +uav_address[5] => ~NO_FANOUT~ +uav_address[6] => ~NO_FANOUT~ +uav_address[7] => ~NO_FANOUT~ +uav_address[8] => ~NO_FANOUT~ +uav_address[9] => ~NO_FANOUT~ +uav_address[10] => ~NO_FANOUT~ +uav_address[11] => ~NO_FANOUT~ +uav_address[12] => ~NO_FANOUT~ +uav_address[13] => ~NO_FANOUT~ +uav_address[14] => ~NO_FANOUT~ +uav_address[15] => ~NO_FANOUT~ +uav_address[16] => ~NO_FANOUT~ +uav_address[17] => ~NO_FANOUT~ +uav_address[18] => ~NO_FANOUT~ +uav_address[19] => ~NO_FANOUT~ +uav_address[20] => ~NO_FANOUT~ +uav_address[21] => ~NO_FANOUT~ +uav_address[22] => ~NO_FANOUT~ +uav_address[23] => ~NO_FANOUT~ +uav_address[24] => ~NO_FANOUT~ +uav_address[25] => ~NO_FANOUT~ +uav_writedata[0] => av_writedata[0].DATAIN +uav_writedata[1] => av_writedata[1].DATAIN +uav_writedata[2] => av_writedata[2].DATAIN +uav_writedata[3] => av_writedata[3].DATAIN +uav_writedata[4] => av_writedata[4].DATAIN +uav_writedata[5] => av_writedata[5].DATAIN +uav_writedata[6] => av_writedata[6].DATAIN +uav_writedata[7] => av_writedata[7].DATAIN +uav_writedata[8] => av_writedata[8].DATAIN +uav_writedata[9] => av_writedata[9].DATAIN +uav_writedata[10] => av_writedata[10].DATAIN +uav_writedata[11] => av_writedata[11].DATAIN +uav_writedata[12] => av_writedata[12].DATAIN +uav_writedata[13] => av_writedata[13].DATAIN +uav_writedata[14] => av_writedata[14].DATAIN +uav_writedata[15] => av_writedata[15].DATAIN +uav_writedata[16] => av_writedata[16].DATAIN +uav_writedata[17] => av_writedata[17].DATAIN +uav_writedata[18] => av_writedata[18].DATAIN +uav_writedata[19] => av_writedata[19].DATAIN +uav_writedata[20] => av_writedata[20].DATAIN +uav_writedata[21] => av_writedata[21].DATAIN +uav_writedata[22] => av_writedata[22].DATAIN +uav_writedata[23] => av_writedata[23].DATAIN +uav_writedata[24] => av_writedata[24].DATAIN +uav_writedata[25] => av_writedata[25].DATAIN +uav_writedata[26] => av_writedata[26].DATAIN +uav_writedata[27] => av_writedata[27].DATAIN +uav_writedata[28] => av_writedata[28].DATAIN +uav_writedata[29] => av_writedata[29].DATAIN +uav_writedata[30] => av_writedata[30].DATAIN +uav_writedata[31] => av_writedata[31].DATAIN +uav_write => av_writebyteenable.IN0 +uav_write => av_begintransfer.IN0 +uav_write => end_beginbursttransfer.IN1 +uav_write => always19.IN1 +uav_write => in_transfer.OUTPUTSELECT +uav_write => av_write.DATAIN +uav_read => read_latency_shift_reg.IN1 +uav_read => av_outputenable.OUTPUTSELECT +uav_read => av_begintransfer.IN1 +uav_read => av_beginbursttransfer.OUTPUTSELECT +uav_read => av_read.DATAIN +uav_burstcount[0] => Equal0.IN3 +uav_burstcount[1] => Equal0.IN2 +uav_burstcount[2] => av_burstcount[0].DATAIN +uav_burstcount[2] => Equal0.IN4 +uav_byteenable[0] => av_writebyteenable.IN1 +uav_byteenable[0] => av_byteenable[0].DATAIN +uav_byteenable[1] => ~NO_FANOUT~ +uav_byteenable[2] => ~NO_FANOUT~ +uav_byteenable[3] => ~NO_FANOUT~ +uav_lock => av_lock.DATAIN +uav_debugaccess => av_debugaccess.DATAIN +uav_clken => ~NO_FANOUT~ +uav_readdatavalid <= read_latency_shift_reg[0].DB_MAX_OUTPUT_PORT_TYPE +uav_waitrequest <= av_waitrequest.DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[0] <= av_readdata_pre[0].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[1] <= av_readdata_pre[1].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[2] <= av_readdata_pre[2].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[3] <= av_readdata_pre[3].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[4] <= av_readdata_pre[4].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[5] <= av_readdata_pre[5].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[6] <= av_readdata_pre[6].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[7] <= av_readdata_pre[7].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[8] <= av_readdata_pre[8].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[9] <= av_readdata_pre[9].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[10] <= av_readdata_pre[10].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[11] <= av_readdata_pre[11].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[12] <= av_readdata_pre[12].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[13] <= av_readdata_pre[13].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[14] <= av_readdata_pre[14].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[15] <= av_readdata_pre[15].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[16] <= av_readdata_pre[16].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[17] <= av_readdata_pre[17].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[18] <= av_readdata_pre[18].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[19] <= av_readdata_pre[19].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[20] <= av_readdata_pre[20].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[21] <= av_readdata_pre[21].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[22] <= av_readdata_pre[22].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[23] <= av_readdata_pre[23].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[24] <= av_readdata_pre[24].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[25] <= av_readdata_pre[25].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[26] <= av_readdata_pre[26].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[27] <= av_readdata_pre[27].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[28] <= av_readdata_pre[28].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[29] <= av_readdata_pre[29].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[30] <= av_readdata_pre[30].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[31] <= av_readdata_pre[31].DB_MAX_OUTPUT_PORT_TYPE +av_address[0] <= uav_address[2].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[0] <= uav_writedata[0].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[1] <= uav_writedata[1].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[2] <= uav_writedata[2].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[3] <= uav_writedata[3].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[4] <= uav_writedata[4].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[5] <= uav_writedata[5].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[6] <= uav_writedata[6].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[7] <= uav_writedata[7].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[8] <= uav_writedata[8].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[9] <= uav_writedata[9].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[10] <= uav_writedata[10].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[11] <= uav_writedata[11].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[12] <= uav_writedata[12].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[13] <= uav_writedata[13].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[14] <= uav_writedata[14].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[15] <= uav_writedata[15].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[16] <= uav_writedata[16].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[17] <= uav_writedata[17].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[18] <= uav_writedata[18].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[19] <= uav_writedata[19].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[20] <= uav_writedata[20].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[21] <= uav_writedata[21].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[22] <= uav_writedata[22].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[23] <= uav_writedata[23].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[24] <= uav_writedata[24].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[25] <= uav_writedata[25].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[26] <= uav_writedata[26].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[27] <= uav_writedata[27].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[28] <= uav_writedata[28].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[29] <= uav_writedata[29].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[30] <= uav_writedata[30].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[31] <= uav_writedata[31].DB_MAX_OUTPUT_PORT_TYPE +av_write <= uav_write.DB_MAX_OUTPUT_PORT_TYPE +av_read <= uav_read.DB_MAX_OUTPUT_PORT_TYPE +av_burstcount[0] <= uav_burstcount[2].DB_MAX_OUTPUT_PORT_TYPE +av_byteenable[0] <= uav_byteenable[0].DB_MAX_OUTPUT_PORT_TYPE +av_writebyteenable[0] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE +av_begintransfer <= av_begintransfer.DB_MAX_OUTPUT_PORT_TYPE +av_chipselect <= av_chipselect.DB_MAX_OUTPUT_PORT_TYPE +av_beginbursttransfer <= av_beginbursttransfer.DB_MAX_OUTPUT_PORT_TYPE +av_lock <= uav_lock.DB_MAX_OUTPUT_PORT_TYPE +av_clken <= +av_debugaccess <= uav_debugaccess.DB_MAX_OUTPUT_PORT_TYPE +av_outputenable <= av_outputenable.DB_MAX_OUTPUT_PORT_TYPE +av_readdata[0] => av_readdata_pre[0].DATAIN +av_readdata[1] => av_readdata_pre[1].DATAIN +av_readdata[2] => av_readdata_pre[2].DATAIN +av_readdata[3] => av_readdata_pre[3].DATAIN +av_readdata[4] => av_readdata_pre[4].DATAIN +av_readdata[5] => av_readdata_pre[5].DATAIN +av_readdata[6] => av_readdata_pre[6].DATAIN +av_readdata[7] => av_readdata_pre[7].DATAIN +av_readdata[8] => av_readdata_pre[8].DATAIN +av_readdata[9] => av_readdata_pre[9].DATAIN +av_readdata[10] => av_readdata_pre[10].DATAIN +av_readdata[11] => av_readdata_pre[11].DATAIN +av_readdata[12] => av_readdata_pre[12].DATAIN +av_readdata[13] => av_readdata_pre[13].DATAIN +av_readdata[14] => av_readdata_pre[14].DATAIN +av_readdata[15] => av_readdata_pre[15].DATAIN +av_readdata[16] => av_readdata_pre[16].DATAIN +av_readdata[17] => av_readdata_pre[17].DATAIN +av_readdata[18] => av_readdata_pre[18].DATAIN +av_readdata[19] => av_readdata_pre[19].DATAIN +av_readdata[20] => av_readdata_pre[20].DATAIN +av_readdata[21] => av_readdata_pre[21].DATAIN +av_readdata[22] => av_readdata_pre[22].DATAIN +av_readdata[23] => av_readdata_pre[23].DATAIN +av_readdata[24] => av_readdata_pre[24].DATAIN +av_readdata[25] => av_readdata_pre[25].DATAIN +av_readdata[26] => av_readdata_pre[26].DATAIN +av_readdata[27] => av_readdata_pre[27].DATAIN +av_readdata[28] => av_readdata_pre[28].DATAIN +av_readdata[29] => av_readdata_pre[29].DATAIN +av_readdata[30] => av_readdata_pre[30].DATAIN +av_readdata[31] => av_readdata_pre[31].DATAIN +av_readdatavalid => ~NO_FANOUT~ +av_waitrequest => always17.IN1 +av_waitrequest => end_begintransfer.OUTPUTSELECT +av_waitrequest => uav_waitrequest.DATAIN +av_waitrequest => read_latency_shift_reg.IN1 + + +|de0_nano_system|system:inst_cpu|altera_merlin_slave_translator:pio_motor_rst_s1_translator +clk => in_transfer.CLK +clk => end_beginbursttransfer.CLK +clk => end_begintransfer.CLK +clk => av_chipselect_pre.CLK +clk => av_outputenable_pre.CLK +clk => read_latency_shift_reg[0].CLK +clk => av_readdata_pre[0].CLK +clk => av_readdata_pre[1].CLK +clk => av_readdata_pre[2].CLK +clk => av_readdata_pre[3].CLK +clk => av_readdata_pre[4].CLK +clk => av_readdata_pre[5].CLK +clk => av_readdata_pre[6].CLK +clk => av_readdata_pre[7].CLK +clk => av_readdata_pre[8].CLK +clk => av_readdata_pre[9].CLK +clk => av_readdata_pre[10].CLK +clk => av_readdata_pre[11].CLK +clk => av_readdata_pre[12].CLK +clk => av_readdata_pre[13].CLK +clk => av_readdata_pre[14].CLK +clk => av_readdata_pre[15].CLK +clk => av_readdata_pre[16].CLK +clk => av_readdata_pre[17].CLK +clk => av_readdata_pre[18].CLK +clk => av_readdata_pre[19].CLK +clk => av_readdata_pre[20].CLK +clk => av_readdata_pre[21].CLK +clk => av_readdata_pre[22].CLK +clk => av_readdata_pre[23].CLK +clk => av_readdata_pre[24].CLK +clk => av_readdata_pre[25].CLK +clk => av_readdata_pre[26].CLK +clk => av_readdata_pre[27].CLK +clk => av_readdata_pre[28].CLK +clk => av_readdata_pre[29].CLK +clk => av_readdata_pre[30].CLK +clk => av_readdata_pre[31].CLK +clk => waitrequest_reset_override.CLK +clk => wait_latency_counter[0].CLK +clk => wait_latency_counter[1].CLK +reset => in_transfer.ACLR +reset => end_beginbursttransfer.ACLR +reset => end_begintransfer.ACLR +reset => av_chipselect_pre.ACLR +reset => av_outputenable_pre.ACLR +reset => read_latency_shift_reg[0].ACLR +reset => av_readdata_pre[0].ACLR +reset => av_readdata_pre[1].ACLR +reset => av_readdata_pre[2].ACLR +reset => av_readdata_pre[3].ACLR +reset => av_readdata_pre[4].ACLR +reset => av_readdata_pre[5].ACLR +reset => av_readdata_pre[6].ACLR +reset => av_readdata_pre[7].ACLR +reset => av_readdata_pre[8].ACLR +reset => av_readdata_pre[9].ACLR +reset => av_readdata_pre[10].ACLR +reset => av_readdata_pre[11].ACLR +reset => av_readdata_pre[12].ACLR +reset => av_readdata_pre[13].ACLR +reset => av_readdata_pre[14].ACLR +reset => av_readdata_pre[15].ACLR +reset => av_readdata_pre[16].ACLR +reset => av_readdata_pre[17].ACLR +reset => av_readdata_pre[18].ACLR +reset => av_readdata_pre[19].ACLR +reset => av_readdata_pre[20].ACLR +reset => av_readdata_pre[21].ACLR +reset => av_readdata_pre[22].ACLR +reset => av_readdata_pre[23].ACLR +reset => av_readdata_pre[24].ACLR +reset => av_readdata_pre[25].ACLR +reset => av_readdata_pre[26].ACLR +reset => av_readdata_pre[27].ACLR +reset => av_readdata_pre[28].ACLR +reset => av_readdata_pre[29].ACLR +reset => av_readdata_pre[30].ACLR +reset => av_readdata_pre[31].ACLR +reset => waitrequest_reset_override.PRESET +reset => wait_latency_counter[0].ACLR +reset => wait_latency_counter[1].ACLR +uav_address[0] => ~NO_FANOUT~ +uav_address[1] => ~NO_FANOUT~ +uav_address[2] => av_address[0].DATAIN +uav_address[3] => av_address[1].DATAIN +uav_address[4] => ~NO_FANOUT~ +uav_address[5] => ~NO_FANOUT~ +uav_address[6] => ~NO_FANOUT~ +uav_address[7] => ~NO_FANOUT~ +uav_address[8] => ~NO_FANOUT~ +uav_address[9] => ~NO_FANOUT~ +uav_address[10] => ~NO_FANOUT~ +uav_address[11] => ~NO_FANOUT~ +uav_address[12] => ~NO_FANOUT~ +uav_address[13] => ~NO_FANOUT~ +uav_address[14] => ~NO_FANOUT~ +uav_address[15] => ~NO_FANOUT~ +uav_address[16] => ~NO_FANOUT~ +uav_address[17] => ~NO_FANOUT~ +uav_address[18] => ~NO_FANOUT~ +uav_address[19] => ~NO_FANOUT~ +uav_address[20] => ~NO_FANOUT~ +uav_address[21] => ~NO_FANOUT~ +uav_address[22] => ~NO_FANOUT~ +uav_address[23] => ~NO_FANOUT~ +uav_address[24] => ~NO_FANOUT~ +uav_address[25] => ~NO_FANOUT~ +uav_writedata[0] => av_writedata[0].DATAIN +uav_writedata[1] => av_writedata[1].DATAIN +uav_writedata[2] => av_writedata[2].DATAIN +uav_writedata[3] => av_writedata[3].DATAIN +uav_writedata[4] => av_writedata[4].DATAIN +uav_writedata[5] => av_writedata[5].DATAIN +uav_writedata[6] => av_writedata[6].DATAIN +uav_writedata[7] => av_writedata[7].DATAIN +uav_writedata[8] => av_writedata[8].DATAIN +uav_writedata[9] => av_writedata[9].DATAIN +uav_writedata[10] => av_writedata[10].DATAIN +uav_writedata[11] => av_writedata[11].DATAIN +uav_writedata[12] => av_writedata[12].DATAIN +uav_writedata[13] => av_writedata[13].DATAIN +uav_writedata[14] => av_writedata[14].DATAIN +uav_writedata[15] => av_writedata[15].DATAIN +uav_writedata[16] => av_writedata[16].DATAIN +uav_writedata[17] => av_writedata[17].DATAIN +uav_writedata[18] => av_writedata[18].DATAIN +uav_writedata[19] => av_writedata[19].DATAIN +uav_writedata[20] => av_writedata[20].DATAIN +uav_writedata[21] => av_writedata[21].DATAIN +uav_writedata[22] => av_writedata[22].DATAIN +uav_writedata[23] => av_writedata[23].DATAIN +uav_writedata[24] => av_writedata[24].DATAIN +uav_writedata[25] => av_writedata[25].DATAIN +uav_writedata[26] => av_writedata[26].DATAIN +uav_writedata[27] => av_writedata[27].DATAIN +uav_writedata[28] => av_writedata[28].DATAIN +uav_writedata[29] => av_writedata[29].DATAIN +uav_writedata[30] => av_writedata[30].DATAIN +uav_writedata[31] => av_writedata[31].DATAIN +uav_write => av_writebyteenable.IN0 +uav_write => av_write.IN1 +uav_write => av_waitrequest_generated.OUTPUTSELECT +uav_write => av_begintransfer.IN0 +uav_write => end_beginbursttransfer.IN1 +uav_write => always19.IN1 +uav_write => in_transfer.OUTPUTSELECT +uav_read => av_read.IN1 +uav_read => read_latency_shift_reg.IN1 +uav_read => av_outputenable.OUTPUTSELECT +uav_read => av_begintransfer.IN1 +uav_read => av_beginbursttransfer.OUTPUTSELECT +uav_burstcount[0] => Equal2.IN3 +uav_burstcount[1] => Equal2.IN2 +uav_burstcount[2] => av_burstcount[0].DATAIN +uav_burstcount[2] => Equal2.IN4 +uav_byteenable[0] => av_writebyteenable.IN1 +uav_byteenable[0] => av_byteenable[0].DATAIN +uav_byteenable[1] => ~NO_FANOUT~ +uav_byteenable[2] => ~NO_FANOUT~ +uav_byteenable[3] => ~NO_FANOUT~ +uav_lock => av_lock.DATAIN +uav_debugaccess => av_debugaccess.DATAIN +uav_clken => ~NO_FANOUT~ +uav_readdatavalid <= read_latency_shift_reg[0].DB_MAX_OUTPUT_PORT_TYPE +uav_waitrequest <= uav_waitrequest.DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[0] <= av_readdata_pre[0].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[1] <= av_readdata_pre[1].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[2] <= av_readdata_pre[2].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[3] <= av_readdata_pre[3].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[4] <= av_readdata_pre[4].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[5] <= av_readdata_pre[5].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[6] <= av_readdata_pre[6].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[7] <= av_readdata_pre[7].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[8] <= av_readdata_pre[8].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[9] <= av_readdata_pre[9].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[10] <= av_readdata_pre[10].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[11] <= av_readdata_pre[11].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[12] <= av_readdata_pre[12].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[13] <= av_readdata_pre[13].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[14] <= av_readdata_pre[14].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[15] <= av_readdata_pre[15].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[16] <= av_readdata_pre[16].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[17] <= av_readdata_pre[17].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[18] <= av_readdata_pre[18].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[19] <= av_readdata_pre[19].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[20] <= av_readdata_pre[20].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[21] <= av_readdata_pre[21].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[22] <= av_readdata_pre[22].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[23] <= av_readdata_pre[23].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[24] <= av_readdata_pre[24].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[25] <= av_readdata_pre[25].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[26] <= av_readdata_pre[26].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[27] <= av_readdata_pre[27].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[28] <= av_readdata_pre[28].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[29] <= av_readdata_pre[29].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[30] <= av_readdata_pre[30].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[31] <= av_readdata_pre[31].DB_MAX_OUTPUT_PORT_TYPE +av_address[0] <= uav_address[2].DB_MAX_OUTPUT_PORT_TYPE +av_address[1] <= uav_address[3].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[0] <= uav_writedata[0].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[1] <= uav_writedata[1].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[2] <= uav_writedata[2].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[3] <= uav_writedata[3].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[4] <= uav_writedata[4].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[5] <= uav_writedata[5].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[6] <= uav_writedata[6].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[7] <= uav_writedata[7].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[8] <= uav_writedata[8].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[9] <= uav_writedata[9].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[10] <= uav_writedata[10].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[11] <= uav_writedata[11].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[12] <= uav_writedata[12].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[13] <= uav_writedata[13].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[14] <= uav_writedata[14].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[15] <= uav_writedata[15].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[16] <= uav_writedata[16].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[17] <= uav_writedata[17].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[18] <= uav_writedata[18].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[19] <= uav_writedata[19].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[20] <= uav_writedata[20].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[21] <= uav_writedata[21].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[22] <= uav_writedata[22].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[23] <= uav_writedata[23].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[24] <= uav_writedata[24].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[25] <= uav_writedata[25].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[26] <= uav_writedata[26].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[27] <= uav_writedata[27].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[28] <= uav_writedata[28].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[29] <= uav_writedata[29].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[30] <= uav_writedata[30].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[31] <= uav_writedata[31].DB_MAX_OUTPUT_PORT_TYPE +av_write <= av_write.DB_MAX_OUTPUT_PORT_TYPE +av_read <= av_read.DB_MAX_OUTPUT_PORT_TYPE +av_burstcount[0] <= uav_burstcount[2].DB_MAX_OUTPUT_PORT_TYPE +av_byteenable[0] <= uav_byteenable[0].DB_MAX_OUTPUT_PORT_TYPE +av_writebyteenable[0] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE +av_begintransfer <= av_begintransfer.DB_MAX_OUTPUT_PORT_TYPE +av_chipselect <= av_chipselect.DB_MAX_OUTPUT_PORT_TYPE +av_beginbursttransfer <= av_beginbursttransfer.DB_MAX_OUTPUT_PORT_TYPE +av_lock <= uav_lock.DB_MAX_OUTPUT_PORT_TYPE +av_clken <= +av_debugaccess <= uav_debugaccess.DB_MAX_OUTPUT_PORT_TYPE +av_outputenable <= av_outputenable.DB_MAX_OUTPUT_PORT_TYPE +av_readdata[0] => av_readdata_pre[0].DATAIN +av_readdata[1] => av_readdata_pre[1].DATAIN +av_readdata[2] => av_readdata_pre[2].DATAIN +av_readdata[3] => av_readdata_pre[3].DATAIN +av_readdata[4] => av_readdata_pre[4].DATAIN +av_readdata[5] => av_readdata_pre[5].DATAIN +av_readdata[6] => av_readdata_pre[6].DATAIN +av_readdata[7] => av_readdata_pre[7].DATAIN +av_readdata[8] => av_readdata_pre[8].DATAIN +av_readdata[9] => av_readdata_pre[9].DATAIN +av_readdata[10] => av_readdata_pre[10].DATAIN +av_readdata[11] => av_readdata_pre[11].DATAIN +av_readdata[12] => av_readdata_pre[12].DATAIN +av_readdata[13] => av_readdata_pre[13].DATAIN +av_readdata[14] => av_readdata_pre[14].DATAIN +av_readdata[15] => av_readdata_pre[15].DATAIN +av_readdata[16] => av_readdata_pre[16].DATAIN +av_readdata[17] => av_readdata_pre[17].DATAIN +av_readdata[18] => av_readdata_pre[18].DATAIN +av_readdata[19] => av_readdata_pre[19].DATAIN +av_readdata[20] => av_readdata_pre[20].DATAIN +av_readdata[21] => av_readdata_pre[21].DATAIN +av_readdata[22] => av_readdata_pre[22].DATAIN +av_readdata[23] => av_readdata_pre[23].DATAIN +av_readdata[24] => av_readdata_pre[24].DATAIN +av_readdata[25] => av_readdata_pre[25].DATAIN +av_readdata[26] => av_readdata_pre[26].DATAIN +av_readdata[27] => av_readdata_pre[27].DATAIN +av_readdata[28] => av_readdata_pre[28].DATAIN +av_readdata[29] => av_readdata_pre[29].DATAIN +av_readdata[30] => av_readdata_pre[30].DATAIN +av_readdata[31] => av_readdata_pre[31].DATAIN +av_readdatavalid => ~NO_FANOUT~ +av_waitrequest => ~NO_FANOUT~ + + +|de0_nano_system|system:inst_cpu|altera_merlin_slave_translator:rs232_motor_avalon_rs232_slave_translator +clk => in_transfer.CLK +clk => end_beginbursttransfer.CLK +clk => end_begintransfer.CLK +clk => av_chipselect_pre.CLK +clk => av_outputenable_pre.CLK +clk => read_latency_shift_reg[0].CLK +clk => waitrequest_reset_override.CLK +reset => in_transfer.ACLR +reset => end_beginbursttransfer.ACLR +reset => end_begintransfer.ACLR +reset => av_chipselect_pre.ACLR +reset => av_outputenable_pre.ACLR +reset => read_latency_shift_reg[0].ACLR +reset => waitrequest_reset_override.PRESET +uav_address[0] => ~NO_FANOUT~ +uav_address[1] => ~NO_FANOUT~ +uav_address[2] => av_address[0].DATAIN +uav_address[3] => ~NO_FANOUT~ +uav_address[4] => ~NO_FANOUT~ +uav_address[5] => ~NO_FANOUT~ +uav_address[6] => ~NO_FANOUT~ +uav_address[7] => ~NO_FANOUT~ +uav_address[8] => ~NO_FANOUT~ +uav_address[9] => ~NO_FANOUT~ +uav_address[10] => ~NO_FANOUT~ +uav_address[11] => ~NO_FANOUT~ +uav_address[12] => ~NO_FANOUT~ +uav_address[13] => ~NO_FANOUT~ +uav_address[14] => ~NO_FANOUT~ +uav_address[15] => ~NO_FANOUT~ +uav_address[16] => ~NO_FANOUT~ +uav_address[17] => ~NO_FANOUT~ +uav_address[18] => ~NO_FANOUT~ +uav_address[19] => ~NO_FANOUT~ +uav_address[20] => ~NO_FANOUT~ +uav_address[21] => ~NO_FANOUT~ +uav_address[22] => ~NO_FANOUT~ +uav_address[23] => ~NO_FANOUT~ +uav_address[24] => ~NO_FANOUT~ +uav_address[25] => ~NO_FANOUT~ +uav_writedata[0] => av_writedata[0].DATAIN +uav_writedata[1] => av_writedata[1].DATAIN +uav_writedata[2] => av_writedata[2].DATAIN +uav_writedata[3] => av_writedata[3].DATAIN +uav_writedata[4] => av_writedata[4].DATAIN +uav_writedata[5] => av_writedata[5].DATAIN +uav_writedata[6] => av_writedata[6].DATAIN +uav_writedata[7] => av_writedata[7].DATAIN +uav_writedata[8] => av_writedata[8].DATAIN +uav_writedata[9] => av_writedata[9].DATAIN +uav_writedata[10] => av_writedata[10].DATAIN +uav_writedata[11] => av_writedata[11].DATAIN +uav_writedata[12] => av_writedata[12].DATAIN +uav_writedata[13] => av_writedata[13].DATAIN +uav_writedata[14] => av_writedata[14].DATAIN +uav_writedata[15] => av_writedata[15].DATAIN +uav_writedata[16] => av_writedata[16].DATAIN +uav_writedata[17] => av_writedata[17].DATAIN +uav_writedata[18] => av_writedata[18].DATAIN +uav_writedata[19] => av_writedata[19].DATAIN +uav_writedata[20] => av_writedata[20].DATAIN +uav_writedata[21] => av_writedata[21].DATAIN +uav_writedata[22] => av_writedata[22].DATAIN +uav_writedata[23] => av_writedata[23].DATAIN +uav_writedata[24] => av_writedata[24].DATAIN +uav_writedata[25] => av_writedata[25].DATAIN +uav_writedata[26] => av_writedata[26].DATAIN +uav_writedata[27] => av_writedata[27].DATAIN +uav_writedata[28] => av_writedata[28].DATAIN +uav_writedata[29] => av_writedata[29].DATAIN +uav_writedata[30] => av_writedata[30].DATAIN +uav_writedata[31] => av_writedata[31].DATAIN +uav_write => av_writebyteenable.IN0 +uav_write => av_writebyteenable.IN0 +uav_write => av_writebyteenable.IN0 +uav_write => av_writebyteenable.IN0 +uav_write => av_begintransfer.IN0 +uav_write => end_beginbursttransfer.IN1 +uav_write => always19.IN1 +uav_write => in_transfer.OUTPUTSELECT +uav_write => av_write.DATAIN +uav_read => read_latency_shift_reg.IN1 +uav_read => av_outputenable.OUTPUTSELECT +uav_read => av_begintransfer.IN1 +uav_read => av_beginbursttransfer.OUTPUTSELECT +uav_read => av_read.DATAIN +uav_read => av_outputenable_pre.DATAIN +uav_burstcount[0] => Equal0.IN3 +uav_burstcount[1] => Equal0.IN2 +uav_burstcount[2] => av_burstcount[0].DATAIN +uav_burstcount[2] => Equal0.IN4 +uav_byteenable[0] => av_writebyteenable.IN1 +uav_byteenable[0] => av_byteenable[0].DATAIN +uav_byteenable[1] => av_writebyteenable.IN1 +uav_byteenable[1] => av_byteenable[1].DATAIN +uav_byteenable[2] => av_writebyteenable.IN1 +uav_byteenable[2] => av_byteenable[2].DATAIN +uav_byteenable[3] => av_writebyteenable.IN1 +uav_byteenable[3] => av_byteenable[3].DATAIN +uav_lock => av_lock.DATAIN +uav_debugaccess => av_debugaccess.DATAIN +uav_clken => ~NO_FANOUT~ +uav_readdatavalid <= read_latency_shift_reg[0].DB_MAX_OUTPUT_PORT_TYPE +uav_waitrequest <= waitrequest_reset_override.DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[0] <= av_readdata[0].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[1] <= av_readdata[1].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[2] <= av_readdata[2].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[3] <= av_readdata[3].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[4] <= av_readdata[4].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[5] <= av_readdata[5].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[6] <= av_readdata[6].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[7] <= av_readdata[7].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[8] <= av_readdata[8].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[9] <= av_readdata[9].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[10] <= av_readdata[10].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[11] <= av_readdata[11].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[12] <= av_readdata[12].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[13] <= av_readdata[13].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[14] <= av_readdata[14].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[15] <= av_readdata[15].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[16] <= av_readdata[16].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[17] <= av_readdata[17].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[18] <= av_readdata[18].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[19] <= av_readdata[19].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[20] <= av_readdata[20].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[21] <= av_readdata[21].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[22] <= av_readdata[22].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[23] <= av_readdata[23].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[24] <= av_readdata[24].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[25] <= av_readdata[25].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[26] <= av_readdata[26].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[27] <= av_readdata[27].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[28] <= av_readdata[28].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[29] <= av_readdata[29].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[30] <= av_readdata[30].DB_MAX_OUTPUT_PORT_TYPE +uav_readdata[31] <= av_readdata[31].DB_MAX_OUTPUT_PORT_TYPE +av_address[0] <= uav_address[2].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[0] <= uav_writedata[0].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[1] <= uav_writedata[1].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[2] <= uav_writedata[2].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[3] <= uav_writedata[3].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[4] <= uav_writedata[4].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[5] <= uav_writedata[5].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[6] <= uav_writedata[6].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[7] <= uav_writedata[7].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[8] <= uav_writedata[8].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[9] <= uav_writedata[9].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[10] <= uav_writedata[10].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[11] <= uav_writedata[11].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[12] <= uav_writedata[12].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[13] <= uav_writedata[13].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[14] <= uav_writedata[14].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[15] <= uav_writedata[15].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[16] <= uav_writedata[16].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[17] <= uav_writedata[17].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[18] <= uav_writedata[18].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[19] <= uav_writedata[19].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[20] <= uav_writedata[20].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[21] <= uav_writedata[21].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[22] <= uav_writedata[22].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[23] <= uav_writedata[23].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[24] <= uav_writedata[24].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[25] <= uav_writedata[25].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[26] <= uav_writedata[26].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[27] <= uav_writedata[27].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[28] <= uav_writedata[28].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[29] <= uav_writedata[29].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[30] <= uav_writedata[30].DB_MAX_OUTPUT_PORT_TYPE +av_writedata[31] <= uav_writedata[31].DB_MAX_OUTPUT_PORT_TYPE +av_write <= uav_write.DB_MAX_OUTPUT_PORT_TYPE +av_read <= uav_read.DB_MAX_OUTPUT_PORT_TYPE +av_burstcount[0] <= uav_burstcount[2].DB_MAX_OUTPUT_PORT_TYPE +av_byteenable[0] <= uav_byteenable[0].DB_MAX_OUTPUT_PORT_TYPE +av_byteenable[1] <= uav_byteenable[1].DB_MAX_OUTPUT_PORT_TYPE +av_byteenable[2] <= uav_byteenable[2].DB_MAX_OUTPUT_PORT_TYPE +av_byteenable[3] <= uav_byteenable[3].DB_MAX_OUTPUT_PORT_TYPE +av_writebyteenable[0] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE +av_writebyteenable[1] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE +av_writebyteenable[2] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE +av_writebyteenable[3] <= av_writebyteenable.DB_MAX_OUTPUT_PORT_TYPE +av_begintransfer <= av_begintransfer.DB_MAX_OUTPUT_PORT_TYPE +av_chipselect <= av_chipselect.DB_MAX_OUTPUT_PORT_TYPE +av_beginbursttransfer <= av_beginbursttransfer.DB_MAX_OUTPUT_PORT_TYPE +av_lock <= uav_lock.DB_MAX_OUTPUT_PORT_TYPE +av_clken <= +av_debugaccess <= uav_debugaccess.DB_MAX_OUTPUT_PORT_TYPE +av_outputenable <= av_outputenable.DB_MAX_OUTPUT_PORT_TYPE +av_readdata[0] => uav_readdata[0].DATAIN +av_readdata[1] => uav_readdata[1].DATAIN +av_readdata[2] => uav_readdata[2].DATAIN +av_readdata[3] => uav_readdata[3].DATAIN +av_readdata[4] => uav_readdata[4].DATAIN +av_readdata[5] => uav_readdata[5].DATAIN +av_readdata[6] => uav_readdata[6].DATAIN +av_readdata[7] => uav_readdata[7].DATAIN +av_readdata[8] => uav_readdata[8].DATAIN +av_readdata[9] => uav_readdata[9].DATAIN +av_readdata[10] => uav_readdata[10].DATAIN +av_readdata[11] => uav_readdata[11].DATAIN +av_readdata[12] => uav_readdata[12].DATAIN +av_readdata[13] => uav_readdata[13].DATAIN +av_readdata[14] => uav_readdata[14].DATAIN +av_readdata[15] => uav_readdata[15].DATAIN +av_readdata[16] => uav_readdata[16].DATAIN +av_readdata[17] => uav_readdata[17].DATAIN +av_readdata[18] => uav_readdata[18].DATAIN +av_readdata[19] => uav_readdata[19].DATAIN +av_readdata[20] => uav_readdata[20].DATAIN +av_readdata[21] => uav_readdata[21].DATAIN +av_readdata[22] => uav_readdata[22].DATAIN +av_readdata[23] => uav_readdata[23].DATAIN +av_readdata[24] => uav_readdata[24].DATAIN +av_readdata[25] => uav_readdata[25].DATAIN +av_readdata[26] => uav_readdata[26].DATAIN +av_readdata[27] => uav_readdata[27].DATAIN +av_readdata[28] => uav_readdata[28].DATAIN +av_readdata[29] => uav_readdata[29].DATAIN +av_readdata[30] => uav_readdata[30].DATAIN +av_readdata[31] => uav_readdata[31].DATAIN +av_readdatavalid => ~NO_FANOUT~ +av_waitrequest => ~NO_FANOUT~ + + +|de0_nano_system|system:inst_cpu|altera_merlin_master_agent:cpu_instruction_master_translator_avalon_universal_master_0_agent +clk => ~NO_FANOUT~ +reset => ~NO_FANOUT~ +av_address[0] => ~NO_FANOUT~ +av_address[1] => ~NO_FANOUT~ +av_address[2] => cp_data[38].DATAIN +av_address[3] => cp_data[39].DATAIN +av_address[4] => cp_data[40].DATAIN +av_address[5] => cp_data[41].DATAIN +av_address[6] => cp_data[42].DATAIN +av_address[7] => cp_data[43].DATAIN +av_address[8] => cp_data[44].DATAIN +av_address[9] => cp_data[45].DATAIN +av_address[10] => cp_data[46].DATAIN +av_address[11] => cp_data[47].DATAIN +av_address[12] => cp_data[48].DATAIN +av_address[13] => cp_data[49].DATAIN +av_address[14] => cp_data[50].DATAIN +av_address[15] => cp_data[51].DATAIN +av_address[16] => cp_data[52].DATAIN +av_address[17] => cp_data[53].DATAIN +av_address[18] => cp_data[54].DATAIN +av_address[19] => cp_data[55].DATAIN +av_address[20] => cp_data[56].DATAIN +av_address[21] => cp_data[57].DATAIN +av_address[22] => cp_data[58].DATAIN +av_address[23] => cp_data[59].DATAIN +av_address[24] => cp_data[60].DATAIN +av_address[25] => cp_data[61].DATAIN +av_write => always1.IN0 +av_write => cp_data[64].DATAIN +av_write => cp_data[63].DATAIN +av_read => always1.IN1 +av_read => cp_data[65].DATAIN +av_writedata[0] => cp_data[0].DATAIN +av_writedata[1] => cp_data[1].DATAIN +av_writedata[2] => cp_data[2].DATAIN +av_writedata[3] => cp_data[3].DATAIN +av_writedata[4] => cp_data[4].DATAIN +av_writedata[5] => cp_data[5].DATAIN +av_writedata[6] => cp_data[6].DATAIN +av_writedata[7] => cp_data[7].DATAIN +av_writedata[8] => cp_data[8].DATAIN +av_writedata[9] => cp_data[9].DATAIN +av_writedata[10] => cp_data[10].DATAIN +av_writedata[11] => cp_data[11].DATAIN +av_writedata[12] => cp_data[12].DATAIN +av_writedata[13] => cp_data[13].DATAIN +av_writedata[14] => cp_data[14].DATAIN +av_writedata[15] => cp_data[15].DATAIN +av_writedata[16] => cp_data[16].DATAIN +av_writedata[17] => cp_data[17].DATAIN +av_writedata[18] => cp_data[18].DATAIN +av_writedata[19] => cp_data[19].DATAIN +av_writedata[20] => cp_data[20].DATAIN +av_writedata[21] => cp_data[21].DATAIN +av_writedata[22] => cp_data[22].DATAIN +av_writedata[23] => cp_data[23].DATAIN +av_writedata[24] => cp_data[24].DATAIN +av_writedata[25] => cp_data[25].DATAIN +av_writedata[26] => cp_data[26].DATAIN +av_writedata[27] => cp_data[27].DATAIN +av_writedata[28] => cp_data[28].DATAIN +av_writedata[29] => cp_data[29].DATAIN +av_writedata[30] => cp_data[30].DATAIN +av_writedata[31] => cp_data[31].DATAIN +av_readdata[0] <= rp_data[0].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[1] <= rp_data[1].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[2] <= rp_data[2].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[3] <= rp_data[3].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[4] <= rp_data[4].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[5] <= rp_data[5].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[6] <= rp_data[6].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[7] <= rp_data[7].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[8] <= rp_data[8].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[9] <= rp_data[9].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[10] <= rp_data[10].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[11] <= rp_data[11].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[12] <= rp_data[12].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[13] <= rp_data[13].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[14] <= rp_data[14].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[15] <= rp_data[15].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[16] <= rp_data[16].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[17] <= rp_data[17].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[18] <= rp_data[18].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[19] <= rp_data[19].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[20] <= rp_data[20].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[21] <= rp_data[21].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[22] <= rp_data[22].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[23] <= rp_data[23].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[24] <= rp_data[24].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[25] <= rp_data[25].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[26] <= rp_data[26].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[27] <= rp_data[27].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[28] <= rp_data[28].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[29] <= rp_data[29].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[30] <= rp_data[30].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[31] <= rp_data[31].DB_MAX_OUTPUT_PORT_TYPE +av_waitrequest <= cp_ready.DB_MAX_OUTPUT_PORT_TYPE +av_readdatavalid <= rp_valid.DB_MAX_OUTPUT_PORT_TYPE +av_byteenable[0] => cp_data[32].DATAIN +av_byteenable[1] => cp_data[33].DATAIN +av_byteenable[2] => cp_data[34].DATAIN +av_byteenable[3] => cp_data[35].DATAIN +av_burstcount[0] => cp_data[68].DATAIN +av_burstcount[1] => cp_data[69].DATAIN +av_burstcount[2] => cp_data[70].DATAIN +av_debugaccess => cp_data[92].DATAIN +av_lock => cp_data[66].DATAIN +cp_valid <= always1.DB_MAX_OUTPUT_PORT_TYPE +cp_data[0] <= av_writedata[0].DB_MAX_OUTPUT_PORT_TYPE +cp_data[1] <= av_writedata[1].DB_MAX_OUTPUT_PORT_TYPE +cp_data[2] <= av_writedata[2].DB_MAX_OUTPUT_PORT_TYPE +cp_data[3] <= av_writedata[3].DB_MAX_OUTPUT_PORT_TYPE +cp_data[4] <= av_writedata[4].DB_MAX_OUTPUT_PORT_TYPE +cp_data[5] <= av_writedata[5].DB_MAX_OUTPUT_PORT_TYPE +cp_data[6] <= av_writedata[6].DB_MAX_OUTPUT_PORT_TYPE +cp_data[7] <= av_writedata[7].DB_MAX_OUTPUT_PORT_TYPE +cp_data[8] <= av_writedata[8].DB_MAX_OUTPUT_PORT_TYPE +cp_data[9] <= av_writedata[9].DB_MAX_OUTPUT_PORT_TYPE +cp_data[10] <= av_writedata[10].DB_MAX_OUTPUT_PORT_TYPE +cp_data[11] <= av_writedata[11].DB_MAX_OUTPUT_PORT_TYPE +cp_data[12] <= av_writedata[12].DB_MAX_OUTPUT_PORT_TYPE +cp_data[13] <= av_writedata[13].DB_MAX_OUTPUT_PORT_TYPE +cp_data[14] <= av_writedata[14].DB_MAX_OUTPUT_PORT_TYPE +cp_data[15] <= av_writedata[15].DB_MAX_OUTPUT_PORT_TYPE +cp_data[16] <= av_writedata[16].DB_MAX_OUTPUT_PORT_TYPE +cp_data[17] <= av_writedata[17].DB_MAX_OUTPUT_PORT_TYPE +cp_data[18] <= av_writedata[18].DB_MAX_OUTPUT_PORT_TYPE +cp_data[19] <= av_writedata[19].DB_MAX_OUTPUT_PORT_TYPE +cp_data[20] <= av_writedata[20].DB_MAX_OUTPUT_PORT_TYPE +cp_data[21] <= av_writedata[21].DB_MAX_OUTPUT_PORT_TYPE +cp_data[22] <= av_writedata[22].DB_MAX_OUTPUT_PORT_TYPE +cp_data[23] <= av_writedata[23].DB_MAX_OUTPUT_PORT_TYPE +cp_data[24] <= av_writedata[24].DB_MAX_OUTPUT_PORT_TYPE +cp_data[25] <= av_writedata[25].DB_MAX_OUTPUT_PORT_TYPE +cp_data[26] <= av_writedata[26].DB_MAX_OUTPUT_PORT_TYPE +cp_data[27] <= av_writedata[27].DB_MAX_OUTPUT_PORT_TYPE +cp_data[28] <= av_writedata[28].DB_MAX_OUTPUT_PORT_TYPE +cp_data[29] <= av_writedata[29].DB_MAX_OUTPUT_PORT_TYPE +cp_data[30] <= av_writedata[30].DB_MAX_OUTPUT_PORT_TYPE +cp_data[31] <= av_writedata[31].DB_MAX_OUTPUT_PORT_TYPE +cp_data[32] <= av_byteenable[0].DB_MAX_OUTPUT_PORT_TYPE +cp_data[33] <= av_byteenable[1].DB_MAX_OUTPUT_PORT_TYPE +cp_data[34] <= av_byteenable[2].DB_MAX_OUTPUT_PORT_TYPE +cp_data[35] <= av_byteenable[3].DB_MAX_OUTPUT_PORT_TYPE +cp_data[36] <= +cp_data[37] <= +cp_data[38] <= av_address[2].DB_MAX_OUTPUT_PORT_TYPE +cp_data[39] <= av_address[3].DB_MAX_OUTPUT_PORT_TYPE +cp_data[40] <= av_address[4].DB_MAX_OUTPUT_PORT_TYPE +cp_data[41] <= av_address[5].DB_MAX_OUTPUT_PORT_TYPE +cp_data[42] <= av_address[6].DB_MAX_OUTPUT_PORT_TYPE +cp_data[43] <= av_address[7].DB_MAX_OUTPUT_PORT_TYPE +cp_data[44] <= av_address[8].DB_MAX_OUTPUT_PORT_TYPE +cp_data[45] <= av_address[9].DB_MAX_OUTPUT_PORT_TYPE +cp_data[46] <= av_address[10].DB_MAX_OUTPUT_PORT_TYPE +cp_data[47] <= av_address[11].DB_MAX_OUTPUT_PORT_TYPE +cp_data[48] <= av_address[12].DB_MAX_OUTPUT_PORT_TYPE +cp_data[49] <= av_address[13].DB_MAX_OUTPUT_PORT_TYPE +cp_data[50] <= av_address[14].DB_MAX_OUTPUT_PORT_TYPE +cp_data[51] <= av_address[15].DB_MAX_OUTPUT_PORT_TYPE +cp_data[52] <= av_address[16].DB_MAX_OUTPUT_PORT_TYPE +cp_data[53] <= av_address[17].DB_MAX_OUTPUT_PORT_TYPE +cp_data[54] <= av_address[18].DB_MAX_OUTPUT_PORT_TYPE +cp_data[55] <= av_address[19].DB_MAX_OUTPUT_PORT_TYPE +cp_data[56] <= av_address[20].DB_MAX_OUTPUT_PORT_TYPE +cp_data[57] <= av_address[21].DB_MAX_OUTPUT_PORT_TYPE +cp_data[58] <= av_address[22].DB_MAX_OUTPUT_PORT_TYPE +cp_data[59] <= av_address[23].DB_MAX_OUTPUT_PORT_TYPE +cp_data[60] <= av_address[24].DB_MAX_OUTPUT_PORT_TYPE +cp_data[61] <= av_address[25].DB_MAX_OUTPUT_PORT_TYPE +cp_data[62] <= +cp_data[63] <= av_write.DB_MAX_OUTPUT_PORT_TYPE +cp_data[64] <= av_write.DB_MAX_OUTPUT_PORT_TYPE +cp_data[65] <= av_read.DB_MAX_OUTPUT_PORT_TYPE +cp_data[66] <= av_lock.DB_MAX_OUTPUT_PORT_TYPE +cp_data[67] <= +cp_data[68] <= av_burstcount[0].DB_MAX_OUTPUT_PORT_TYPE +cp_data[69] <= av_burstcount[1].DB_MAX_OUTPUT_PORT_TYPE +cp_data[70] <= av_burstcount[2].DB_MAX_OUTPUT_PORT_TYPE +cp_data[71] <= +cp_data[72] <= +cp_data[73] <= +cp_data[74] <= +cp_data[75] <= +cp_data[76] <= +cp_data[77] <= +cp_data[78] <= +cp_data[79] <= +cp_data[80] <= +cp_data[81] <= +cp_data[82] <= +cp_data[83] <= +cp_data[84] <= +cp_data[85] <= +cp_data[86] <= +cp_data[87] <= +cp_data[88] <= +cp_data[89] <= +cp_data[90] <= +cp_data[91] <= +cp_data[92] <= av_debugaccess.DB_MAX_OUTPUT_PORT_TYPE +cp_data[93] <= +cp_data[94] <= +cp_data[95] <= +cp_data[96] <= +cp_data[97] <= +cp_data[98] <= +cp_data[99] <= +cp_data[100] <= +cp_startofpacket <= +cp_endofpacket <= +cp_ready => av_waitrequest.DATAIN +rp_valid => av_readdatavalid.DATAIN +rp_data[0] => av_readdata[0].DATAIN +rp_data[1] => av_readdata[1].DATAIN +rp_data[2] => av_readdata[2].DATAIN +rp_data[3] => av_readdata[3].DATAIN +rp_data[4] => av_readdata[4].DATAIN +rp_data[5] => av_readdata[5].DATAIN +rp_data[6] => av_readdata[6].DATAIN +rp_data[7] => av_readdata[7].DATAIN +rp_data[8] => av_readdata[8].DATAIN +rp_data[9] => av_readdata[9].DATAIN +rp_data[10] => av_readdata[10].DATAIN +rp_data[11] => av_readdata[11].DATAIN +rp_data[12] => av_readdata[12].DATAIN +rp_data[13] => av_readdata[13].DATAIN +rp_data[14] => av_readdata[14].DATAIN +rp_data[15] => av_readdata[15].DATAIN +rp_data[16] => av_readdata[16].DATAIN +rp_data[17] => av_readdata[17].DATAIN +rp_data[18] => av_readdata[18].DATAIN +rp_data[19] => av_readdata[19].DATAIN +rp_data[20] => av_readdata[20].DATAIN +rp_data[21] => av_readdata[21].DATAIN +rp_data[22] => av_readdata[22].DATAIN +rp_data[23] => av_readdata[23].DATAIN +rp_data[24] => av_readdata[24].DATAIN +rp_data[25] => av_readdata[25].DATAIN +rp_data[26] => av_readdata[26].DATAIN +rp_data[27] => av_readdata[27].DATAIN +rp_data[28] => av_readdata[28].DATAIN +rp_data[29] => av_readdata[29].DATAIN +rp_data[30] => av_readdata[30].DATAIN +rp_data[31] => av_readdata[31].DATAIN +rp_data[32] => ~NO_FANOUT~ +rp_data[33] => ~NO_FANOUT~ +rp_data[34] => ~NO_FANOUT~ +rp_data[35] => ~NO_FANOUT~ +rp_data[36] => ~NO_FANOUT~ +rp_data[37] => ~NO_FANOUT~ +rp_data[38] => ~NO_FANOUT~ +rp_data[39] => ~NO_FANOUT~ +rp_data[40] => ~NO_FANOUT~ +rp_data[41] => ~NO_FANOUT~ +rp_data[42] => ~NO_FANOUT~ +rp_data[43] => ~NO_FANOUT~ +rp_data[44] => ~NO_FANOUT~ +rp_data[45] => ~NO_FANOUT~ +rp_data[46] => ~NO_FANOUT~ +rp_data[47] => ~NO_FANOUT~ +rp_data[48] => ~NO_FANOUT~ +rp_data[49] => ~NO_FANOUT~ +rp_data[50] => ~NO_FANOUT~ +rp_data[51] => ~NO_FANOUT~ +rp_data[52] => ~NO_FANOUT~ +rp_data[53] => ~NO_FANOUT~ +rp_data[54] => ~NO_FANOUT~ +rp_data[55] => ~NO_FANOUT~ +rp_data[56] => ~NO_FANOUT~ +rp_data[57] => ~NO_FANOUT~ +rp_data[58] => ~NO_FANOUT~ +rp_data[59] => ~NO_FANOUT~ +rp_data[60] => ~NO_FANOUT~ +rp_data[61] => ~NO_FANOUT~ +rp_data[62] => ~NO_FANOUT~ +rp_data[63] => ~NO_FANOUT~ +rp_data[64] => ~NO_FANOUT~ +rp_data[65] => ~NO_FANOUT~ +rp_data[66] => ~NO_FANOUT~ +rp_data[67] => ~NO_FANOUT~ +rp_data[68] => ~NO_FANOUT~ +rp_data[69] => ~NO_FANOUT~ +rp_data[70] => ~NO_FANOUT~ +rp_data[71] => ~NO_FANOUT~ +rp_data[72] => ~NO_FANOUT~ +rp_data[73] => ~NO_FANOUT~ +rp_data[74] => ~NO_FANOUT~ +rp_data[75] => ~NO_FANOUT~ +rp_data[76] => ~NO_FANOUT~ +rp_data[77] => ~NO_FANOUT~ +rp_data[78] => ~NO_FANOUT~ +rp_data[79] => ~NO_FANOUT~ +rp_data[80] => ~NO_FANOUT~ +rp_data[81] => ~NO_FANOUT~ +rp_data[82] => ~NO_FANOUT~ +rp_data[83] => ~NO_FANOUT~ +rp_data[84] => ~NO_FANOUT~ +rp_data[85] => ~NO_FANOUT~ +rp_data[86] => ~NO_FANOUT~ +rp_data[87] => ~NO_FANOUT~ +rp_data[88] => ~NO_FANOUT~ +rp_data[89] => ~NO_FANOUT~ +rp_data[90] => ~NO_FANOUT~ +rp_data[91] => ~NO_FANOUT~ +rp_data[92] => ~NO_FANOUT~ +rp_data[93] => ~NO_FANOUT~ +rp_data[94] => ~NO_FANOUT~ +rp_data[95] => ~NO_FANOUT~ +rp_data[96] => ~NO_FANOUT~ +rp_data[97] => ~NO_FANOUT~ +rp_data[98] => ~NO_FANOUT~ +rp_data[99] => ~NO_FANOUT~ +rp_data[100] => ~NO_FANOUT~ +rp_channel[0] => ~NO_FANOUT~ +rp_channel[1] => ~NO_FANOUT~ +rp_channel[2] => ~NO_FANOUT~ +rp_channel[3] => ~NO_FANOUT~ +rp_channel[4] => ~NO_FANOUT~ +rp_channel[5] => ~NO_FANOUT~ +rp_channel[6] => ~NO_FANOUT~ +rp_channel[7] => ~NO_FANOUT~ +rp_channel[8] => ~NO_FANOUT~ +rp_channel[9] => ~NO_FANOUT~ +rp_channel[10] => ~NO_FANOUT~ +rp_startofpacket => ~NO_FANOUT~ +rp_endofpacket => ~NO_FANOUT~ +rp_ready <= + + +|de0_nano_system|system:inst_cpu|altera_merlin_master_agent:cpu_data_master_translator_avalon_universal_master_0_agent +clk => ~NO_FANOUT~ +reset => ~NO_FANOUT~ +av_address[0] => ~NO_FANOUT~ +av_address[1] => ~NO_FANOUT~ +av_address[2] => cp_data[38].DATAIN +av_address[3] => cp_data[39].DATAIN +av_address[4] => cp_data[40].DATAIN +av_address[5] => cp_data[41].DATAIN +av_address[6] => cp_data[42].DATAIN +av_address[7] => cp_data[43].DATAIN +av_address[8] => cp_data[44].DATAIN +av_address[9] => cp_data[45].DATAIN +av_address[10] => cp_data[46].DATAIN +av_address[11] => cp_data[47].DATAIN +av_address[12] => cp_data[48].DATAIN +av_address[13] => cp_data[49].DATAIN +av_address[14] => cp_data[50].DATAIN +av_address[15] => cp_data[51].DATAIN +av_address[16] => cp_data[52].DATAIN +av_address[17] => cp_data[53].DATAIN +av_address[18] => cp_data[54].DATAIN +av_address[19] => cp_data[55].DATAIN +av_address[20] => cp_data[56].DATAIN +av_address[21] => cp_data[57].DATAIN +av_address[22] => cp_data[58].DATAIN +av_address[23] => cp_data[59].DATAIN +av_address[24] => cp_data[60].DATAIN +av_address[25] => cp_data[61].DATAIN +av_write => always1.IN0 +av_write => cp_data[64].DATAIN +av_write => cp_data[63].DATAIN +av_read => always1.IN1 +av_read => cp_data[65].DATAIN +av_writedata[0] => cp_data[0].DATAIN +av_writedata[1] => cp_data[1].DATAIN +av_writedata[2] => cp_data[2].DATAIN +av_writedata[3] => cp_data[3].DATAIN +av_writedata[4] => cp_data[4].DATAIN +av_writedata[5] => cp_data[5].DATAIN +av_writedata[6] => cp_data[6].DATAIN +av_writedata[7] => cp_data[7].DATAIN +av_writedata[8] => cp_data[8].DATAIN +av_writedata[9] => cp_data[9].DATAIN +av_writedata[10] => cp_data[10].DATAIN +av_writedata[11] => cp_data[11].DATAIN +av_writedata[12] => cp_data[12].DATAIN +av_writedata[13] => cp_data[13].DATAIN +av_writedata[14] => cp_data[14].DATAIN +av_writedata[15] => cp_data[15].DATAIN +av_writedata[16] => cp_data[16].DATAIN +av_writedata[17] => cp_data[17].DATAIN +av_writedata[18] => cp_data[18].DATAIN +av_writedata[19] => cp_data[19].DATAIN +av_writedata[20] => cp_data[20].DATAIN +av_writedata[21] => cp_data[21].DATAIN +av_writedata[22] => cp_data[22].DATAIN +av_writedata[23] => cp_data[23].DATAIN +av_writedata[24] => cp_data[24].DATAIN +av_writedata[25] => cp_data[25].DATAIN +av_writedata[26] => cp_data[26].DATAIN +av_writedata[27] => cp_data[27].DATAIN +av_writedata[28] => cp_data[28].DATAIN +av_writedata[29] => cp_data[29].DATAIN +av_writedata[30] => cp_data[30].DATAIN +av_writedata[31] => cp_data[31].DATAIN +av_readdata[0] <= rp_data[0].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[1] <= rp_data[1].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[2] <= rp_data[2].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[3] <= rp_data[3].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[4] <= rp_data[4].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[5] <= rp_data[5].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[6] <= rp_data[6].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[7] <= rp_data[7].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[8] <= rp_data[8].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[9] <= rp_data[9].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[10] <= rp_data[10].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[11] <= rp_data[11].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[12] <= rp_data[12].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[13] <= rp_data[13].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[14] <= rp_data[14].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[15] <= rp_data[15].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[16] <= rp_data[16].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[17] <= rp_data[17].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[18] <= rp_data[18].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[19] <= rp_data[19].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[20] <= rp_data[20].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[21] <= rp_data[21].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[22] <= rp_data[22].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[23] <= rp_data[23].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[24] <= rp_data[24].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[25] <= rp_data[25].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[26] <= rp_data[26].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[27] <= rp_data[27].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[28] <= rp_data[28].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[29] <= rp_data[29].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[30] <= rp_data[30].DB_MAX_OUTPUT_PORT_TYPE +av_readdata[31] <= rp_data[31].DB_MAX_OUTPUT_PORT_TYPE +av_waitrequest <= cp_ready.DB_MAX_OUTPUT_PORT_TYPE +av_readdatavalid <= rp_valid.DB_MAX_OUTPUT_PORT_TYPE +av_byteenable[0] => cp_data[32].DATAIN +av_byteenable[1] => cp_data[33].DATAIN +av_byteenable[2] => cp_data[34].DATAIN +av_byteenable[3] => cp_data[35].DATAIN +av_burstcount[0] => cp_data[68].DATAIN +av_burstcount[1] => cp_data[69].DATAIN +av_burstcount[2] => cp_data[70].DATAIN +av_debugaccess => cp_data[92].DATAIN +av_lock => cp_data[66].DATAIN +cp_valid <= always1.DB_MAX_OUTPUT_PORT_TYPE +cp_data[0] <= av_writedata[0].DB_MAX_OUTPUT_PORT_TYPE +cp_data[1] <= av_writedata[1].DB_MAX_OUTPUT_PORT_TYPE +cp_data[2] <= av_writedata[2].DB_MAX_OUTPUT_PORT_TYPE +cp_data[3] <= av_writedata[3].DB_MAX_OUTPUT_PORT_TYPE +cp_data[4] <= av_writedata[4].DB_MAX_OUTPUT_PORT_TYPE +cp_data[5] <= av_writedata[5].DB_MAX_OUTPUT_PORT_TYPE +cp_data[6] <= av_writedata[6].DB_MAX_OUTPUT_PORT_TYPE +cp_data[7] <= av_writedata[7].DB_MAX_OUTPUT_PORT_TYPE +cp_data[8] <= av_writedata[8].DB_MAX_OUTPUT_PORT_TYPE +cp_data[9] <= av_writedata[9].DB_MAX_OUTPUT_PORT_TYPE +cp_data[10] <= av_writedata[10].DB_MAX_OUTPUT_PORT_TYPE +cp_data[11] <= av_writedata[11].DB_MAX_OUTPUT_PORT_TYPE +cp_data[12] <= av_writedata[12].DB_MAX_OUTPUT_PORT_TYPE +cp_data[13] <= av_writedata[13].DB_MAX_OUTPUT_PORT_TYPE +cp_data[14] <= av_writedata[14].DB_MAX_OUTPUT_PORT_TYPE +cp_data[15] <= av_writedata[15].DB_MAX_OUTPUT_PORT_TYPE +cp_data[16] <= av_writedata[16].DB_MAX_OUTPUT_PORT_TYPE +cp_data[17] <= av_writedata[17].DB_MAX_OUTPUT_PORT_TYPE +cp_data[18] <= av_writedata[18].DB_MAX_OUTPUT_PORT_TYPE +cp_data[19] <= av_writedata[19].DB_MAX_OUTPUT_PORT_TYPE +cp_data[20] <= av_writedata[20].DB_MAX_OUTPUT_PORT_TYPE +cp_data[21] <= av_writedata[21].DB_MAX_OUTPUT_PORT_TYPE +cp_data[22] <= av_writedata[22].DB_MAX_OUTPUT_PORT_TYPE +cp_data[23] <= av_writedata[23].DB_MAX_OUTPUT_PORT_TYPE +cp_data[24] <= av_writedata[24].DB_MAX_OUTPUT_PORT_TYPE +cp_data[25] <= av_writedata[25].DB_MAX_OUTPUT_PORT_TYPE +cp_data[26] <= av_writedata[26].DB_MAX_OUTPUT_PORT_TYPE +cp_data[27] <= av_writedata[27].DB_MAX_OUTPUT_PORT_TYPE +cp_data[28] <= av_writedata[28].DB_MAX_OUTPUT_PORT_TYPE +cp_data[29] <= av_writedata[29].DB_MAX_OUTPUT_PORT_TYPE +cp_data[30] <= av_writedata[30].DB_MAX_OUTPUT_PORT_TYPE +cp_data[31] <= av_writedata[31].DB_MAX_OUTPUT_PORT_TYPE +cp_data[32] <= av_byteenable[0].DB_MAX_OUTPUT_PORT_TYPE +cp_data[33] <= av_byteenable[1].DB_MAX_OUTPUT_PORT_TYPE +cp_data[34] <= av_byteenable[2].DB_MAX_OUTPUT_PORT_TYPE +cp_data[35] <= av_byteenable[3].DB_MAX_OUTPUT_PORT_TYPE +cp_data[36] <= +cp_data[37] <= +cp_data[38] <= av_address[2].DB_MAX_OUTPUT_PORT_TYPE +cp_data[39] <= av_address[3].DB_MAX_OUTPUT_PORT_TYPE +cp_data[40] <= av_address[4].DB_MAX_OUTPUT_PORT_TYPE +cp_data[41] <= av_address[5].DB_MAX_OUTPUT_PORT_TYPE +cp_data[42] <= av_address[6].DB_MAX_OUTPUT_PORT_TYPE +cp_data[43] <= av_address[7].DB_MAX_OUTPUT_PORT_TYPE +cp_data[44] <= av_address[8].DB_MAX_OUTPUT_PORT_TYPE +cp_data[45] <= av_address[9].DB_MAX_OUTPUT_PORT_TYPE +cp_data[46] <= av_address[10].DB_MAX_OUTPUT_PORT_TYPE +cp_data[47] <= av_address[11].DB_MAX_OUTPUT_PORT_TYPE +cp_data[48] <= av_address[12].DB_MAX_OUTPUT_PORT_TYPE +cp_data[49] <= av_address[13].DB_MAX_OUTPUT_PORT_TYPE +cp_data[50] <= av_address[14].DB_MAX_OUTPUT_PORT_TYPE +cp_data[51] <= av_address[15].DB_MAX_OUTPUT_PORT_TYPE +cp_data[52] <= av_address[16].DB_MAX_OUTPUT_PORT_TYPE +cp_data[53] <= av_address[17].DB_MAX_OUTPUT_PORT_TYPE +cp_data[54] <= av_address[18].DB_MAX_OUTPUT_PORT_TYPE +cp_data[55] <= av_address[19].DB_MAX_OUTPUT_PORT_TYPE +cp_data[56] <= av_address[20].DB_MAX_OUTPUT_PORT_TYPE +cp_data[57] <= av_address[21].DB_MAX_OUTPUT_PORT_TYPE +cp_data[58] <= av_address[22].DB_MAX_OUTPUT_PORT_TYPE +cp_data[59] <= av_address[23].DB_MAX_OUTPUT_PORT_TYPE +cp_data[60] <= av_address[24].DB_MAX_OUTPUT_PORT_TYPE +cp_data[61] <= av_address[25].DB_MAX_OUTPUT_PORT_TYPE +cp_data[62] <= +cp_data[63] <= av_write.DB_MAX_OUTPUT_PORT_TYPE +cp_data[64] <= av_write.DB_MAX_OUTPUT_PORT_TYPE +cp_data[65] <= av_read.DB_MAX_OUTPUT_PORT_TYPE +cp_data[66] <= av_lock.DB_MAX_OUTPUT_PORT_TYPE +cp_data[67] <= +cp_data[68] <= av_burstcount[0].DB_MAX_OUTPUT_PORT_TYPE +cp_data[69] <= av_burstcount[1].DB_MAX_OUTPUT_PORT_TYPE +cp_data[70] <= av_burstcount[2].DB_MAX_OUTPUT_PORT_TYPE +cp_data[71] <= +cp_data[72] <= +cp_data[73] <= +cp_data[74] <= +cp_data[75] <= +cp_data[76] <= +cp_data[77] <= +cp_data[78] <= +cp_data[79] <= +cp_data[80] <= +cp_data[81] <= +cp_data[82] <= +cp_data[83] <= +cp_data[84] <= +cp_data[85] <= +cp_data[86] <= +cp_data[87] <= +cp_data[88] <= +cp_data[89] <= +cp_data[90] <= +cp_data[91] <= +cp_data[92] <= av_debugaccess.DB_MAX_OUTPUT_PORT_TYPE +cp_data[93] <= +cp_data[94] <= +cp_data[95] <= +cp_data[96] <= +cp_data[97] <= +cp_data[98] <= +cp_data[99] <= +cp_data[100] <= +cp_startofpacket <= +cp_endofpacket <= +cp_ready => av_waitrequest.DATAIN +rp_valid => av_readdatavalid.DATAIN +rp_data[0] => av_readdata[0].DATAIN +rp_data[1] => av_readdata[1].DATAIN +rp_data[2] => av_readdata[2].DATAIN +rp_data[3] => av_readdata[3].DATAIN +rp_data[4] => av_readdata[4].DATAIN +rp_data[5] => av_readdata[5].DATAIN +rp_data[6] => av_readdata[6].DATAIN +rp_data[7] => av_readdata[7].DATAIN +rp_data[8] => av_readdata[8].DATAIN +rp_data[9] => av_readdata[9].DATAIN +rp_data[10] => av_readdata[10].DATAIN +rp_data[11] => av_readdata[11].DATAIN +rp_data[12] => av_readdata[12].DATAIN +rp_data[13] => av_readdata[13].DATAIN +rp_data[14] => av_readdata[14].DATAIN +rp_data[15] => av_readdata[15].DATAIN +rp_data[16] => av_readdata[16].DATAIN +rp_data[17] => av_readdata[17].DATAIN +rp_data[18] => av_readdata[18].DATAIN +rp_data[19] => av_readdata[19].DATAIN +rp_data[20] => av_readdata[20].DATAIN +rp_data[21] => av_readdata[21].DATAIN +rp_data[22] => av_readdata[22].DATAIN +rp_data[23] => av_readdata[23].DATAIN +rp_data[24] => av_readdata[24].DATAIN +rp_data[25] => av_readdata[25].DATAIN +rp_data[26] => av_readdata[26].DATAIN +rp_data[27] => av_readdata[27].DATAIN +rp_data[28] => av_readdata[28].DATAIN +rp_data[29] => av_readdata[29].DATAIN +rp_data[30] => av_readdata[30].DATAIN +rp_data[31] => av_readdata[31].DATAIN +rp_data[32] => ~NO_FANOUT~ +rp_data[33] => ~NO_FANOUT~ +rp_data[34] => ~NO_FANOUT~ +rp_data[35] => ~NO_FANOUT~ +rp_data[36] => ~NO_FANOUT~ +rp_data[37] => ~NO_FANOUT~ +rp_data[38] => ~NO_FANOUT~ +rp_data[39] => ~NO_FANOUT~ +rp_data[40] => ~NO_FANOUT~ +rp_data[41] => ~NO_FANOUT~ +rp_data[42] => ~NO_FANOUT~ +rp_data[43] => ~NO_FANOUT~ +rp_data[44] => ~NO_FANOUT~ +rp_data[45] => ~NO_FANOUT~ +rp_data[46] => ~NO_FANOUT~ +rp_data[47] => ~NO_FANOUT~ +rp_data[48] => ~NO_FANOUT~ +rp_data[49] => ~NO_FANOUT~ +rp_data[50] => ~NO_FANOUT~ +rp_data[51] => ~NO_FANOUT~ +rp_data[52] => ~NO_FANOUT~ +rp_data[53] => ~NO_FANOUT~ +rp_data[54] => ~NO_FANOUT~ +rp_data[55] => ~NO_FANOUT~ +rp_data[56] => ~NO_FANOUT~ +rp_data[57] => ~NO_FANOUT~ +rp_data[58] => ~NO_FANOUT~ +rp_data[59] => ~NO_FANOUT~ +rp_data[60] => ~NO_FANOUT~ +rp_data[61] => ~NO_FANOUT~ +rp_data[62] => ~NO_FANOUT~ +rp_data[63] => ~NO_FANOUT~ +rp_data[64] => ~NO_FANOUT~ +rp_data[65] => ~NO_FANOUT~ +rp_data[66] => ~NO_FANOUT~ +rp_data[67] => ~NO_FANOUT~ +rp_data[68] => ~NO_FANOUT~ +rp_data[69] => ~NO_FANOUT~ +rp_data[70] => ~NO_FANOUT~ +rp_data[71] => ~NO_FANOUT~ +rp_data[72] => ~NO_FANOUT~ +rp_data[73] => ~NO_FANOUT~ +rp_data[74] => ~NO_FANOUT~ +rp_data[75] => ~NO_FANOUT~ +rp_data[76] => ~NO_FANOUT~ +rp_data[77] => ~NO_FANOUT~ +rp_data[78] => ~NO_FANOUT~ +rp_data[79] => ~NO_FANOUT~ +rp_data[80] => ~NO_FANOUT~ +rp_data[81] => ~NO_FANOUT~ +rp_data[82] => ~NO_FANOUT~ +rp_data[83] => ~NO_FANOUT~ +rp_data[84] => ~NO_FANOUT~ +rp_data[85] => ~NO_FANOUT~ +rp_data[86] => ~NO_FANOUT~ +rp_data[87] => ~NO_FANOUT~ +rp_data[88] => ~NO_FANOUT~ +rp_data[89] => ~NO_FANOUT~ +rp_data[90] => ~NO_FANOUT~ +rp_data[91] => ~NO_FANOUT~ +rp_data[92] => ~NO_FANOUT~ +rp_data[93] => ~NO_FANOUT~ +rp_data[94] => ~NO_FANOUT~ +rp_data[95] => ~NO_FANOUT~ +rp_data[96] => ~NO_FANOUT~ +rp_data[97] => ~NO_FANOUT~ +rp_data[98] => ~NO_FANOUT~ +rp_data[99] => ~NO_FANOUT~ +rp_data[100] => ~NO_FANOUT~ +rp_channel[0] => ~NO_FANOUT~ +rp_channel[1] => ~NO_FANOUT~ +rp_channel[2] => ~NO_FANOUT~ +rp_channel[3] => ~NO_FANOUT~ +rp_channel[4] => ~NO_FANOUT~ +rp_channel[5] => ~NO_FANOUT~ +rp_channel[6] => ~NO_FANOUT~ +rp_channel[7] => ~NO_FANOUT~ +rp_channel[8] => ~NO_FANOUT~ +rp_channel[9] => ~NO_FANOUT~ +rp_channel[10] => ~NO_FANOUT~ +rp_startofpacket => ~NO_FANOUT~ +rp_endofpacket => ~NO_FANOUT~ +rp_ready <= + + +|de0_nano_system|system:inst_cpu|altera_merlin_slave_agent:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent +clk => clk.IN1 +reset => reset.IN1 +m0_address[0] <= +m0_address[1] <= +m0_address[2] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE +m0_address[3] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE +m0_address[4] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE +m0_address[5] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE +m0_address[6] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE +m0_address[7] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE +m0_address[8] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE +m0_address[9] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE +m0_address[10] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE +m0_address[11] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE +m0_address[12] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE +m0_address[13] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE +m0_address[14] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE +m0_address[15] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE +m0_address[16] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE +m0_address[17] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE +m0_address[18] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE +m0_address[19] <= cp_data[55].DB_MAX_OUTPUT_PORT_TYPE +m0_address[20] <= cp_data[56].DB_MAX_OUTPUT_PORT_TYPE +m0_address[21] <= cp_data[57].DB_MAX_OUTPUT_PORT_TYPE +m0_address[22] <= cp_data[58].DB_MAX_OUTPUT_PORT_TYPE +m0_address[23] <= cp_data[59].DB_MAX_OUTPUT_PORT_TYPE +m0_address[24] <= cp_data[60].DB_MAX_OUTPUT_PORT_TYPE +m0_address[25] <= cp_data[61].DB_MAX_OUTPUT_PORT_TYPE +m0_burstcount[0] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE +m0_burstcount[1] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE +m0_burstcount[2] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[0] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[1] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[2] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[3] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE +m0_read <= m0_read.DB_MAX_OUTPUT_PORT_TYPE +m0_readdata[0] => rdata_fifo_src_data[0].DATAIN +m0_readdata[1] => rdata_fifo_src_data[1].DATAIN +m0_readdata[2] => rdata_fifo_src_data[2].DATAIN +m0_readdata[3] => rdata_fifo_src_data[3].DATAIN +m0_readdata[4] => rdata_fifo_src_data[4].DATAIN +m0_readdata[5] => rdata_fifo_src_data[5].DATAIN +m0_readdata[6] => rdata_fifo_src_data[6].DATAIN +m0_readdata[7] => rdata_fifo_src_data[7].DATAIN +m0_readdata[8] => rdata_fifo_src_data[8].DATAIN +m0_readdata[9] => rdata_fifo_src_data[9].DATAIN +m0_readdata[10] => rdata_fifo_src_data[10].DATAIN +m0_readdata[11] => rdata_fifo_src_data[11].DATAIN +m0_readdata[12] => rdata_fifo_src_data[12].DATAIN +m0_readdata[13] => rdata_fifo_src_data[13].DATAIN +m0_readdata[14] => rdata_fifo_src_data[14].DATAIN +m0_readdata[15] => rdata_fifo_src_data[15].DATAIN +m0_readdata[16] => rdata_fifo_src_data[16].DATAIN +m0_readdata[17] => rdata_fifo_src_data[17].DATAIN +m0_readdata[18] => rdata_fifo_src_data[18].DATAIN +m0_readdata[19] => rdata_fifo_src_data[19].DATAIN +m0_readdata[20] => rdata_fifo_src_data[20].DATAIN +m0_readdata[21] => rdata_fifo_src_data[21].DATAIN +m0_readdata[22] => rdata_fifo_src_data[22].DATAIN +m0_readdata[23] => rdata_fifo_src_data[23].DATAIN +m0_readdata[24] => rdata_fifo_src_data[24].DATAIN +m0_readdata[25] => rdata_fifo_src_data[25].DATAIN +m0_readdata[26] => rdata_fifo_src_data[26].DATAIN +m0_readdata[27] => rdata_fifo_src_data[27].DATAIN +m0_readdata[28] => rdata_fifo_src_data[28].DATAIN +m0_readdata[29] => rdata_fifo_src_data[29].DATAIN +m0_readdata[30] => rdata_fifo_src_data[30].DATAIN +m0_readdata[31] => rdata_fifo_src_data[31].DATAIN +m0_waitrequest => cp_ready.IN0 +m0_write <= m0_write.DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[0] <= cp_data[0].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[1] <= cp_data[1].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[2] <= cp_data[2].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[3] <= cp_data[3].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[4] <= cp_data[4].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[5] <= cp_data[5].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[6] <= cp_data[6].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[7] <= cp_data[7].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[8] <= cp_data[8].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[9] <= cp_data[9].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[10] <= cp_data[10].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[11] <= cp_data[11].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[12] <= cp_data[12].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[13] <= cp_data[13].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[14] <= cp_data[14].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[15] <= cp_data[15].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[16] <= cp_data[16].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[17] <= cp_data[17].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[18] <= cp_data[18].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[19] <= cp_data[19].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[20] <= cp_data[20].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[21] <= cp_data[21].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[22] <= cp_data[22].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[23] <= cp_data[23].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[24] <= cp_data[24].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[25] <= cp_data[25].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[26] <= cp_data[26].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[27] <= cp_data[27].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[28] <= cp_data[28].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[29] <= cp_data[29].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[30] <= cp_data[30].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[31] <= cp_data[31].DB_MAX_OUTPUT_PORT_TYPE +m0_readdatavalid => rdata_fifo_src_valid.DATAIN +m0_debugaccess <= cp_data[92].DB_MAX_OUTPUT_PORT_TYPE +m0_lock <= m0_lock.DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[0] <= +rf_source_data[1] <= +rf_source_data[2] <= +rf_source_data[3] <= +rf_source_data[4] <= +rf_source_data[5] <= +rf_source_data[6] <= +rf_source_data[7] <= +rf_source_data[8] <= +rf_source_data[9] <= +rf_source_data[10] <= +rf_source_data[11] <= +rf_source_data[12] <= +rf_source_data[13] <= +rf_source_data[14] <= +rf_source_data[15] <= +rf_source_data[16] <= +rf_source_data[17] <= +rf_source_data[18] <= +rf_source_data[19] <= +rf_source_data[20] <= +rf_source_data[21] <= +rf_source_data[22] <= +rf_source_data[23] <= +rf_source_data[24] <= +rf_source_data[25] <= +rf_source_data[26] <= +rf_source_data[27] <= +rf_source_data[28] <= +rf_source_data[29] <= +rf_source_data[30] <= +rf_source_data[31] <= +rf_source_data[32] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[33] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[34] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[35] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[36] <= cp_data[36].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[37] <= cp_data[37].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[38] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[39] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[40] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[41] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[42] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[43] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[44] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[45] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[46] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[47] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[48] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[49] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[50] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[51] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[52] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[53] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[54] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[55] <= cp_data[55].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[56] <= cp_data[56].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[57] <= cp_data[57].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[58] <= cp_data[58].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[59] <= cp_data[59].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[60] <= cp_data[60].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[61] <= cp_data[61].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[62] <= cp_data[62].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[63] <= cp_data[63].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[64] <= cp_data[64].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[65] <= cp_data[65].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[66] <= cp_data[66].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[67] <= cp_data[67].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[68] <= cp_data[68].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[69] <= cp_data[69].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[70] <= cp_data[70].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[71] <= cp_data[71].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[72] <= cp_data[72].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[73] <= cp_data[73].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[74] <= cp_data[74].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[75] <= cp_data[75].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[76] <= cp_data[76].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[77] <= cp_data[77].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[78] <= cp_data[78].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[79] <= cp_data[79].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[80] <= cp_data[80].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[81] <= cp_data[81].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[82] <= cp_data[82].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[83] <= cp_data[83].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[84] <= cp_data[84].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[85] <= cp_data[85].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[86] <= cp_data[86].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[87] <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[88] <= cp_data[88].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[89] <= cp_data[89].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[90] <= cp_data[90].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[91] <= cp_data[91].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[92] <= cp_data[92].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[93] <= +rf_source_data[94] <= +rf_source_data[95] <= cp_data[95].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[96] <= cp_data[96].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[97] <= cp_data[97].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[98] <= cp_data[98].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[99] <= cp_data[99].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[100] <= cp_data[100].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[101] <= nonposted_write_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +rf_source_valid <= rf_source_valid.DB_MAX_OUTPUT_PORT_TYPE +rf_source_startofpacket <= cp_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +rf_source_endofpacket <= cp_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +rf_source_ready => cp_ready.IN1 +rf_source_ready => m0_write.IN1 +rf_source_ready => m0_lock.IN1 +rf_source_ready => rf_source_valid.IN1 +rf_source_ready => m0_read.IN1 +rf_sink_data[0] => ~NO_FANOUT~ +rf_sink_data[1] => ~NO_FANOUT~ +rf_sink_data[2] => ~NO_FANOUT~ +rf_sink_data[3] => ~NO_FANOUT~ +rf_sink_data[4] => ~NO_FANOUT~ +rf_sink_data[5] => ~NO_FANOUT~ +rf_sink_data[6] => ~NO_FANOUT~ +rf_sink_data[7] => ~NO_FANOUT~ +rf_sink_data[8] => ~NO_FANOUT~ +rf_sink_data[9] => ~NO_FANOUT~ +rf_sink_data[10] => ~NO_FANOUT~ +rf_sink_data[11] => ~NO_FANOUT~ +rf_sink_data[12] => ~NO_FANOUT~ +rf_sink_data[13] => ~NO_FANOUT~ +rf_sink_data[14] => ~NO_FANOUT~ +rf_sink_data[15] => ~NO_FANOUT~ +rf_sink_data[16] => ~NO_FANOUT~ +rf_sink_data[17] => ~NO_FANOUT~ +rf_sink_data[18] => ~NO_FANOUT~ +rf_sink_data[19] => ~NO_FANOUT~ +rf_sink_data[20] => ~NO_FANOUT~ +rf_sink_data[21] => ~NO_FANOUT~ +rf_sink_data[22] => ~NO_FANOUT~ +rf_sink_data[23] => ~NO_FANOUT~ +rf_sink_data[24] => ~NO_FANOUT~ +rf_sink_data[25] => ~NO_FANOUT~ +rf_sink_data[26] => ~NO_FANOUT~ +rf_sink_data[27] => ~NO_FANOUT~ +rf_sink_data[28] => ~NO_FANOUT~ +rf_sink_data[29] => ~NO_FANOUT~ +rf_sink_data[30] => ~NO_FANOUT~ +rf_sink_data[31] => ~NO_FANOUT~ +rf_sink_data[32] => rp_data[32].DATAIN +rf_sink_data[33] => rp_data[33].DATAIN +rf_sink_data[34] => rp_data[34].DATAIN +rf_sink_data[35] => rp_data[35].DATAIN +rf_sink_data[36] => rf_sink_addr[0].IN1 +rf_sink_data[37] => rf_sink_addr[1].IN1 +rf_sink_data[38] => rf_sink_addr[2].IN1 +rf_sink_data[39] => rf_sink_addr[3].IN1 +rf_sink_data[40] => rf_sink_addr[4].IN1 +rf_sink_data[41] => rf_sink_addr[5].IN1 +rf_sink_data[42] => rf_sink_addr[6].IN1 +rf_sink_data[43] => rf_sink_addr[7].IN1 +rf_sink_data[44] => rf_sink_addr[8].IN1 +rf_sink_data[45] => rf_sink_addr[9].IN1 +rf_sink_data[46] => rf_sink_addr[10].IN1 +rf_sink_data[47] => rf_sink_addr[11].IN1 +rf_sink_data[48] => rf_sink_addr[12].IN1 +rf_sink_data[49] => rf_sink_addr[13].IN1 +rf_sink_data[50] => rf_sink_addr[14].IN1 +rf_sink_data[51] => rf_sink_addr[15].IN1 +rf_sink_data[52] => rf_sink_addr[16].IN1 +rf_sink_data[53] => rf_sink_addr[17].IN1 +rf_sink_data[54] => rf_sink_addr[18].IN1 +rf_sink_data[55] => rf_sink_addr[19].IN1 +rf_sink_data[56] => rf_sink_addr[20].IN1 +rf_sink_data[57] => rf_sink_addr[21].IN1 +rf_sink_data[58] => rf_sink_addr[22].IN1 +rf_sink_data[59] => rf_sink_addr[23].IN1 +rf_sink_data[60] => rf_sink_addr[24].IN1 +rf_sink_data[61] => rf_sink_addr[25].IN1 +rf_sink_data[62] => rf_sink_compressed.IN1 +rf_sink_data[63] => rp_data[63].DATAIN +rf_sink_data[64] => comb.OUTPUTSELECT +rf_sink_data[64] => rp_data[64].DATAIN +rf_sink_data[65] => rp_data.IN0 +rf_sink_data[66] => rp_data[66].DATAIN +rf_sink_data[67] => rp_data[67].DATAIN +rf_sink_data[68] => rf_sink_byte_cnt[0].IN1 +rf_sink_data[69] => rf_sink_byte_cnt[1].IN1 +rf_sink_data[70] => rf_sink_byte_cnt[2].IN1 +rf_sink_data[71] => rf_sink_burstwrap[0].IN1 +rf_sink_data[72] => rf_sink_burstwrap[1].IN1 +rf_sink_data[73] => rf_sink_burstwrap[2].IN1 +rf_sink_data[74] => rf_sink_burstsize[0].IN1 +rf_sink_data[75] => rf_sink_burstsize[1].IN1 +rf_sink_data[76] => rf_sink_burstsize[2].IN1 +rf_sink_data[77] => rp_data[77].DATAIN +rf_sink_data[78] => rp_data[78].DATAIN +rf_sink_data[79] => rp_data[79].DATAIN +rf_sink_data[80] => rp_data[80].DATAIN +rf_sink_data[81] => rp_data[81].DATAIN +rf_sink_data[82] => rp_data[82].DATAIN +rf_sink_data[83] => rp_data[87].DATAIN +rf_sink_data[84] => rp_data[88].DATAIN +rf_sink_data[85] => rp_data[89].DATAIN +rf_sink_data[86] => rp_data[90].DATAIN +rf_sink_data[87] => rp_data[83].DATAIN +rf_sink_data[88] => rp_data[84].DATAIN +rf_sink_data[89] => rp_data[85].DATAIN +rf_sink_data[90] => rp_data[86].DATAIN +rf_sink_data[91] => rp_data[91].DATAIN +rf_sink_data[92] => rp_data[92].DATAIN +rf_sink_data[93] => rp_data[93].DATAIN +rf_sink_data[94] => rp_data[94].DATAIN +rf_sink_data[95] => rp_data[95].DATAIN +rf_sink_data[96] => rp_data[96].DATAIN +rf_sink_data[97] => rp_data[97].DATAIN +rf_sink_data[98] => rp_data[98].DATAIN +rf_sink_data[99] => ~NO_FANOUT~ +rf_sink_data[100] => ~NO_FANOUT~ +rf_sink_data[101] => rdata_fifo_sink_ready.IN0 +rf_sink_data[101] => comb.IN0 +rf_sink_valid => rdata_fifo_sink_ready.IN1 +rf_sink_valid => comb.IN1 +rf_sink_startofpacket => comb.DATAA +rf_sink_endofpacket => rf_sink_endofpacket.IN1 +rf_sink_ready <= altera_merlin_burst_uncompressor:uncompressor.sink_ready +rdata_fifo_src_data[0] <= m0_readdata[0].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[1] <= m0_readdata[1].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[2] <= m0_readdata[2].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[3] <= m0_readdata[3].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[4] <= m0_readdata[4].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[5] <= m0_readdata[5].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[6] <= m0_readdata[6].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[7] <= m0_readdata[7].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[8] <= m0_readdata[8].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[9] <= m0_readdata[9].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[10] <= m0_readdata[10].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[11] <= m0_readdata[11].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[12] <= m0_readdata[12].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[13] <= m0_readdata[13].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[14] <= m0_readdata[14].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[15] <= m0_readdata[15].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[16] <= m0_readdata[16].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[17] <= m0_readdata[17].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[18] <= m0_readdata[18].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[19] <= m0_readdata[19].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[20] <= m0_readdata[20].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[21] <= m0_readdata[21].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[22] <= m0_readdata[22].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[23] <= m0_readdata[23].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[24] <= m0_readdata[24].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[25] <= m0_readdata[25].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[26] <= m0_readdata[26].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[27] <= m0_readdata[27].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[28] <= m0_readdata[28].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[29] <= m0_readdata[29].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[30] <= m0_readdata[30].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[31] <= m0_readdata[31].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_valid <= m0_readdatavalid.DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_ready => ~NO_FANOUT~ +rdata_fifo_sink_data[0] => rp_data[0].DATAIN +rdata_fifo_sink_data[1] => rp_data[1].DATAIN +rdata_fifo_sink_data[2] => rp_data[2].DATAIN +rdata_fifo_sink_data[3] => rp_data[3].DATAIN +rdata_fifo_sink_data[4] => rp_data[4].DATAIN +rdata_fifo_sink_data[5] => rp_data[5].DATAIN +rdata_fifo_sink_data[6] => rp_data[6].DATAIN +rdata_fifo_sink_data[7] => rp_data[7].DATAIN +rdata_fifo_sink_data[8] => rp_data[8].DATAIN +rdata_fifo_sink_data[9] => rp_data[9].DATAIN +rdata_fifo_sink_data[10] => rp_data[10].DATAIN +rdata_fifo_sink_data[11] => rp_data[11].DATAIN +rdata_fifo_sink_data[12] => rp_data[12].DATAIN +rdata_fifo_sink_data[13] => rp_data[13].DATAIN +rdata_fifo_sink_data[14] => rp_data[14].DATAIN +rdata_fifo_sink_data[15] => rp_data[15].DATAIN +rdata_fifo_sink_data[16] => rp_data[16].DATAIN +rdata_fifo_sink_data[17] => rp_data[17].DATAIN +rdata_fifo_sink_data[18] => rp_data[18].DATAIN +rdata_fifo_sink_data[19] => rp_data[19].DATAIN +rdata_fifo_sink_data[20] => rp_data[20].DATAIN +rdata_fifo_sink_data[21] => rp_data[21].DATAIN +rdata_fifo_sink_data[22] => rp_data[22].DATAIN +rdata_fifo_sink_data[23] => rp_data[23].DATAIN +rdata_fifo_sink_data[24] => rp_data[24].DATAIN +rdata_fifo_sink_data[25] => rp_data[25].DATAIN +rdata_fifo_sink_data[26] => rp_data[26].DATAIN +rdata_fifo_sink_data[27] => rp_data[27].DATAIN +rdata_fifo_sink_data[28] => rp_data[28].DATAIN +rdata_fifo_sink_data[29] => rp_data[29].DATAIN +rdata_fifo_sink_data[30] => rp_data[30].DATAIN +rdata_fifo_sink_data[31] => rp_data[31].DATAIN +rdata_fifo_sink_valid => rp_valid.IN1 +rdata_fifo_sink_valid => rdata_fifo_sink_ready.IN0 +rdata_fifo_sink_valid => comb.IN1 +rdata_fifo_sink_ready <= rdata_fifo_sink_ready.DB_MAX_OUTPUT_PORT_TYPE +cp_ready <= cp_ready.DB_MAX_OUTPUT_PORT_TYPE +cp_valid => local_lock.IN0 +cp_valid => local_write.IN0 +cp_valid => local_read.IN0 +cp_valid => local_compressed_read.IN0 +cp_data[0] => m0_writedata[0].DATAIN +cp_data[1] => m0_writedata[1].DATAIN +cp_data[2] => m0_writedata[2].DATAIN +cp_data[3] => m0_writedata[3].DATAIN +cp_data[4] => m0_writedata[4].DATAIN +cp_data[5] => m0_writedata[5].DATAIN +cp_data[6] => m0_writedata[6].DATAIN +cp_data[7] => m0_writedata[7].DATAIN +cp_data[8] => m0_writedata[8].DATAIN +cp_data[9] => m0_writedata[9].DATAIN +cp_data[10] => m0_writedata[10].DATAIN +cp_data[11] => m0_writedata[11].DATAIN +cp_data[12] => m0_writedata[12].DATAIN +cp_data[13] => m0_writedata[13].DATAIN +cp_data[14] => m0_writedata[14].DATAIN +cp_data[15] => m0_writedata[15].DATAIN +cp_data[16] => m0_writedata[16].DATAIN +cp_data[17] => m0_writedata[17].DATAIN +cp_data[18] => m0_writedata[18].DATAIN +cp_data[19] => m0_writedata[19].DATAIN +cp_data[20] => m0_writedata[20].DATAIN +cp_data[21] => m0_writedata[21].DATAIN +cp_data[22] => m0_writedata[22].DATAIN +cp_data[23] => m0_writedata[23].DATAIN +cp_data[24] => m0_writedata[24].DATAIN +cp_data[25] => m0_writedata[25].DATAIN +cp_data[26] => m0_writedata[26].DATAIN +cp_data[27] => m0_writedata[27].DATAIN +cp_data[28] => m0_writedata[28].DATAIN +cp_data[29] => m0_writedata[29].DATAIN +cp_data[30] => m0_writedata[30].DATAIN +cp_data[31] => m0_writedata[31].DATAIN +cp_data[32] => rf_source_data[32].DATAIN +cp_data[32] => m0_byteenable[0].DATAIN +cp_data[33] => rf_source_data[33].DATAIN +cp_data[33] => m0_byteenable[1].DATAIN +cp_data[34] => rf_source_data[34].DATAIN +cp_data[34] => m0_byteenable[2].DATAIN +cp_data[35] => rf_source_data[35].DATAIN +cp_data[35] => m0_byteenable[3].DATAIN +cp_data[36] => rf_source_data[36].DATAIN +cp_data[37] => rf_source_data[37].DATAIN +cp_data[38] => rf_source_data[38].DATAIN +cp_data[38] => m0_address[2].DATAIN +cp_data[39] => rf_source_data[39].DATAIN +cp_data[39] => m0_address[3].DATAIN +cp_data[40] => rf_source_data[40].DATAIN +cp_data[40] => m0_address[4].DATAIN +cp_data[41] => rf_source_data[41].DATAIN +cp_data[41] => m0_address[5].DATAIN +cp_data[42] => rf_source_data[42].DATAIN +cp_data[42] => m0_address[6].DATAIN +cp_data[43] => rf_source_data[43].DATAIN +cp_data[43] => m0_address[7].DATAIN +cp_data[44] => rf_source_data[44].DATAIN +cp_data[44] => m0_address[8].DATAIN +cp_data[45] => rf_source_data[45].DATAIN +cp_data[45] => m0_address[9].DATAIN +cp_data[46] => rf_source_data[46].DATAIN +cp_data[46] => m0_address[10].DATAIN +cp_data[47] => rf_source_data[47].DATAIN +cp_data[47] => m0_address[11].DATAIN +cp_data[48] => rf_source_data[48].DATAIN +cp_data[48] => m0_address[12].DATAIN +cp_data[49] => rf_source_data[49].DATAIN +cp_data[49] => m0_address[13].DATAIN +cp_data[50] => rf_source_data[50].DATAIN +cp_data[50] => m0_address[14].DATAIN +cp_data[51] => rf_source_data[51].DATAIN +cp_data[51] => m0_address[15].DATAIN +cp_data[52] => rf_source_data[52].DATAIN +cp_data[52] => m0_address[16].DATAIN +cp_data[53] => rf_source_data[53].DATAIN +cp_data[53] => m0_address[17].DATAIN +cp_data[54] => rf_source_data[54].DATAIN +cp_data[54] => m0_address[18].DATAIN +cp_data[55] => rf_source_data[55].DATAIN +cp_data[55] => m0_address[19].DATAIN +cp_data[56] => rf_source_data[56].DATAIN +cp_data[56] => m0_address[20].DATAIN +cp_data[57] => rf_source_data[57].DATAIN +cp_data[57] => m0_address[21].DATAIN +cp_data[58] => rf_source_data[58].DATAIN +cp_data[58] => m0_address[22].DATAIN +cp_data[59] => rf_source_data[59].DATAIN +cp_data[59] => m0_address[23].DATAIN +cp_data[60] => rf_source_data[60].DATAIN +cp_data[60] => m0_address[24].DATAIN +cp_data[61] => rf_source_data[61].DATAIN +cp_data[61] => m0_address[25].DATAIN +cp_data[62] => local_compressed_read.IN1 +cp_data[62] => rf_source_data[62].DATAIN +cp_data[63] => rf_source_data[63].DATAIN +cp_data[63] => comb.IN1 +cp_data[64] => local_write.IN1 +cp_data[64] => rf_source_data[64].DATAIN +cp_data[65] => local_read.IN1 +cp_data[65] => rf_source_data[65].DATAIN +cp_data[66] => local_lock.IN1 +cp_data[66] => rf_source_data[66].DATAIN +cp_data[67] => rf_source_data[67].DATAIN +cp_data[68] => m0_burstcount.DATAA +cp_data[68] => rf_source_data[68].DATAIN +cp_data[69] => m0_burstcount.DATAA +cp_data[69] => rf_source_data[69].DATAIN +cp_data[70] => m0_burstcount.DATAA +cp_data[70] => rf_source_data[70].DATAIN +cp_data[71] => rf_source_data[71].DATAIN +cp_data[72] => rf_source_data[72].DATAIN +cp_data[73] => rf_source_data[73].DATAIN +cp_data[74] => rf_source_data[74].DATAIN +cp_data[75] => rf_source_data[75].DATAIN +cp_data[76] => rf_source_data[76].DATAIN +cp_data[77] => rf_source_data[77].DATAIN +cp_data[78] => rf_source_data[78].DATAIN +cp_data[79] => rf_source_data[79].DATAIN +cp_data[80] => rf_source_data[80].DATAIN +cp_data[81] => rf_source_data[81].DATAIN +cp_data[82] => rf_source_data[82].DATAIN +cp_data[83] => rf_source_data[83].DATAIN +cp_data[84] => rf_source_data[84].DATAIN +cp_data[85] => rf_source_data[85].DATAIN +cp_data[86] => rf_source_data[86].DATAIN +cp_data[87] => rf_source_data[87].DATAIN +cp_data[88] => rf_source_data[88].DATAIN +cp_data[89] => rf_source_data[89].DATAIN +cp_data[90] => rf_source_data[90].DATAIN +cp_data[91] => rf_source_data[91].DATAIN +cp_data[92] => rf_source_data[92].DATAIN +cp_data[92] => m0_debugaccess.DATAIN +cp_data[93] => ~NO_FANOUT~ +cp_data[94] => ~NO_FANOUT~ +cp_data[95] => rf_source_data[95].DATAIN +cp_data[96] => rf_source_data[96].DATAIN +cp_data[97] => rf_source_data[97].DATAIN +cp_data[98] => rf_source_data[98].DATAIN +cp_data[99] => rf_source_data[99].DATAIN +cp_data[100] => rf_source_data[100].DATAIN +cp_channel[0] => ~NO_FANOUT~ +cp_channel[1] => ~NO_FANOUT~ +cp_channel[2] => ~NO_FANOUT~ +cp_channel[3] => ~NO_FANOUT~ +cp_channel[4] => ~NO_FANOUT~ +cp_channel[5] => ~NO_FANOUT~ +cp_channel[6] => ~NO_FANOUT~ +cp_channel[7] => ~NO_FANOUT~ +cp_channel[8] => ~NO_FANOUT~ +cp_channel[9] => ~NO_FANOUT~ +cp_channel[10] => ~NO_FANOUT~ +cp_startofpacket => rf_source_startofpacket.DATAIN +cp_endofpacket => nonposted_write_endofpacket.IN1 +cp_endofpacket => rf_source_endofpacket.DATAIN +rp_ready => rp_ready.IN1 +rp_valid <= rp_valid.DB_MAX_OUTPUT_PORT_TYPE +rp_data[0] <= rdata_fifo_sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +rp_data[1] <= rdata_fifo_sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +rp_data[2] <= rdata_fifo_sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +rp_data[3] <= rdata_fifo_sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +rp_data[4] <= rdata_fifo_sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +rp_data[5] <= rdata_fifo_sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +rp_data[6] <= rdata_fifo_sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +rp_data[7] <= rdata_fifo_sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +rp_data[8] <= rdata_fifo_sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +rp_data[9] <= rdata_fifo_sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +rp_data[10] <= rdata_fifo_sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +rp_data[11] <= rdata_fifo_sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +rp_data[12] <= rdata_fifo_sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +rp_data[13] <= rdata_fifo_sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +rp_data[14] <= rdata_fifo_sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +rp_data[15] <= rdata_fifo_sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +rp_data[16] <= rdata_fifo_sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +rp_data[17] <= rdata_fifo_sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +rp_data[18] <= rdata_fifo_sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +rp_data[19] <= rdata_fifo_sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +rp_data[20] <= rdata_fifo_sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +rp_data[21] <= rdata_fifo_sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +rp_data[22] <= rdata_fifo_sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +rp_data[23] <= rdata_fifo_sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +rp_data[24] <= rdata_fifo_sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +rp_data[25] <= rdata_fifo_sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +rp_data[26] <= rdata_fifo_sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +rp_data[27] <= rdata_fifo_sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +rp_data[28] <= rdata_fifo_sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +rp_data[29] <= rdata_fifo_sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +rp_data[30] <= rdata_fifo_sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +rp_data[31] <= rdata_fifo_sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +rp_data[32] <= rf_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +rp_data[33] <= rf_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +rp_data[34] <= rf_sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +rp_data[35] <= rf_sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +rp_data[36] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[37] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[38] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[39] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[40] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[41] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[42] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[43] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[44] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[45] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[46] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[47] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[48] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[49] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[50] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[51] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[52] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[53] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[54] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[55] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[56] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[57] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[58] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[59] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[60] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[61] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[62] <= altera_merlin_burst_uncompressor:uncompressor.source_is_compressed +rp_data[63] <= rf_sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +rp_data[64] <= rf_sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +rp_data[65] <= rp_data.DB_MAX_OUTPUT_PORT_TYPE +rp_data[66] <= rf_sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +rp_data[67] <= rf_sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +rp_data[68] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt +rp_data[69] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt +rp_data[70] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt +rp_data[71] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap +rp_data[72] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap +rp_data[73] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap +rp_data[74] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize +rp_data[75] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize +rp_data[76] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize +rp_data[77] <= rf_sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +rp_data[78] <= rf_sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +rp_data[79] <= rf_sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +rp_data[80] <= rf_sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +rp_data[81] <= rf_sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +rp_data[82] <= rf_sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +rp_data[83] <= rf_sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +rp_data[84] <= rf_sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +rp_data[85] <= rf_sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +rp_data[86] <= rf_sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +rp_data[87] <= rf_sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +rp_data[88] <= rf_sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +rp_data[89] <= rf_sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +rp_data[90] <= rf_sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +rp_data[91] <= rf_sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +rp_data[92] <= rf_sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +rp_data[93] <= rf_sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +rp_data[94] <= rf_sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +rp_data[95] <= rf_sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +rp_data[96] <= rf_sink_data[96].DB_MAX_OUTPUT_PORT_TYPE +rp_data[97] <= rf_sink_data[97].DB_MAX_OUTPUT_PORT_TYPE +rp_data[98] <= rf_sink_data[98].DB_MAX_OUTPUT_PORT_TYPE +rp_data[99] <= +rp_data[100] <= +rp_startofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_startofpacket +rp_endofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_endofpacket + + +|de0_nano_system|system:inst_cpu|altera_merlin_slave_agent:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor +clk => burst_uncompress_address_offset[0].CLK +clk => burst_uncompress_address_offset[1].CLK +clk => burst_uncompress_address_offset[2].CLK +clk => burst_uncompress_address_offset[3].CLK +clk => burst_uncompress_address_offset[4].CLK +clk => burst_uncompress_address_offset[5].CLK +clk => burst_uncompress_address_offset[6].CLK +clk => burst_uncompress_address_offset[7].CLK +clk => burst_uncompress_address_offset[8].CLK +clk => burst_uncompress_address_offset[9].CLK +clk => burst_uncompress_address_offset[10].CLK +clk => burst_uncompress_address_offset[11].CLK +clk => burst_uncompress_address_offset[12].CLK +clk => burst_uncompress_address_offset[13].CLK +clk => burst_uncompress_address_offset[14].CLK +clk => burst_uncompress_address_offset[15].CLK +clk => burst_uncompress_address_offset[16].CLK +clk => burst_uncompress_address_offset[17].CLK +clk => burst_uncompress_address_offset[18].CLK +clk => burst_uncompress_address_offset[19].CLK +clk => burst_uncompress_address_offset[20].CLK +clk => burst_uncompress_address_offset[21].CLK +clk => burst_uncompress_address_offset[22].CLK +clk => burst_uncompress_address_offset[23].CLK +clk => burst_uncompress_address_offset[24].CLK +clk => burst_uncompress_address_offset[25].CLK +clk => burst_uncompress_address_base[0].CLK +clk => burst_uncompress_address_base[1].CLK +clk => burst_uncompress_address_base[2].CLK +clk => burst_uncompress_address_base[3].CLK +clk => burst_uncompress_address_base[4].CLK +clk => burst_uncompress_address_base[5].CLK +clk => burst_uncompress_address_base[6].CLK +clk => burst_uncompress_address_base[7].CLK +clk => burst_uncompress_address_base[8].CLK +clk => burst_uncompress_address_base[9].CLK +clk => burst_uncompress_address_base[10].CLK +clk => burst_uncompress_address_base[11].CLK +clk => burst_uncompress_address_base[12].CLK +clk => burst_uncompress_address_base[13].CLK +clk => burst_uncompress_address_base[14].CLK +clk => burst_uncompress_address_base[15].CLK +clk => burst_uncompress_address_base[16].CLK +clk => burst_uncompress_address_base[17].CLK +clk => burst_uncompress_address_base[18].CLK +clk => burst_uncompress_address_base[19].CLK +clk => burst_uncompress_address_base[20].CLK +clk => burst_uncompress_address_base[21].CLK +clk => burst_uncompress_address_base[22].CLK +clk => burst_uncompress_address_base[23].CLK +clk => burst_uncompress_address_base[24].CLK +clk => burst_uncompress_address_base[25].CLK +clk => burst_uncompress_byte_counter[0].CLK +clk => burst_uncompress_byte_counter[1].CLK +clk => burst_uncompress_byte_counter[2].CLK +clk => burst_uncompress_busy.CLK +reset => burst_uncompress_address_offset[0].ACLR +reset => burst_uncompress_address_offset[1].ACLR +reset => burst_uncompress_address_offset[2].ACLR +reset => burst_uncompress_address_offset[3].ACLR +reset => burst_uncompress_address_offset[4].ACLR +reset => burst_uncompress_address_offset[5].ACLR +reset => burst_uncompress_address_offset[6].ACLR +reset => burst_uncompress_address_offset[7].ACLR +reset => burst_uncompress_address_offset[8].ACLR +reset => burst_uncompress_address_offset[9].ACLR +reset => burst_uncompress_address_offset[10].ACLR +reset => burst_uncompress_address_offset[11].ACLR +reset => burst_uncompress_address_offset[12].ACLR +reset => burst_uncompress_address_offset[13].ACLR +reset => burst_uncompress_address_offset[14].ACLR +reset => burst_uncompress_address_offset[15].ACLR +reset => burst_uncompress_address_offset[16].ACLR +reset => burst_uncompress_address_offset[17].ACLR +reset => burst_uncompress_address_offset[18].ACLR +reset => burst_uncompress_address_offset[19].ACLR +reset => burst_uncompress_address_offset[20].ACLR +reset => burst_uncompress_address_offset[21].ACLR +reset => burst_uncompress_address_offset[22].ACLR +reset => burst_uncompress_address_offset[23].ACLR +reset => burst_uncompress_address_offset[24].ACLR +reset => burst_uncompress_address_offset[25].ACLR +reset => burst_uncompress_address_base[0].ACLR +reset => burst_uncompress_address_base[1].ACLR +reset => burst_uncompress_address_base[2].ACLR +reset => burst_uncompress_address_base[3].ACLR +reset => burst_uncompress_address_base[4].ACLR +reset => burst_uncompress_address_base[5].ACLR +reset => burst_uncompress_address_base[6].ACLR +reset => burst_uncompress_address_base[7].ACLR +reset => burst_uncompress_address_base[8].ACLR +reset => burst_uncompress_address_base[9].ACLR +reset => burst_uncompress_address_base[10].ACLR +reset => burst_uncompress_address_base[11].ACLR +reset => burst_uncompress_address_base[12].ACLR +reset => burst_uncompress_address_base[13].ACLR +reset => burst_uncompress_address_base[14].ACLR +reset => burst_uncompress_address_base[15].ACLR +reset => burst_uncompress_address_base[16].ACLR +reset => burst_uncompress_address_base[17].ACLR +reset => burst_uncompress_address_base[18].ACLR +reset => burst_uncompress_address_base[19].ACLR +reset => burst_uncompress_address_base[20].ACLR +reset => burst_uncompress_address_base[21].ACLR +reset => burst_uncompress_address_base[22].ACLR +reset => burst_uncompress_address_base[23].ACLR +reset => burst_uncompress_address_base[24].ACLR +reset => burst_uncompress_address_base[25].ACLR +reset => burst_uncompress_byte_counter[0].ACLR +reset => burst_uncompress_byte_counter[1].ACLR +reset => burst_uncompress_byte_counter[2].ACLR +reset => burst_uncompress_busy.ACLR +sink_startofpacket => source_startofpacket.IN1 +sink_endofpacket => source_endofpacket.IN1 +sink_valid => first_packet_beat.IN1 +sink_valid => last_packet_beat.IN1 +sink_valid => last_packet_beat.IN1 +sink_valid => always0.IN1 +sink_valid => sink_ready.IN0 +sink_valid => source_valid.DATAIN +sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE +sink_addr[0] => burst_uncompress_address_base.IN0 +sink_addr[0] => comb.DATAB +sink_addr[0] => source_addr.DATAB +sink_addr[1] => burst_uncompress_address_base.IN0 +sink_addr[1] => comb.DATAB +sink_addr[1] => source_addr.DATAB +sink_addr[2] => burst_uncompress_address_base.IN0 +sink_addr[2] => comb.DATAB +sink_addr[2] => source_addr.DATAB +sink_addr[3] => burst_uncompress_address_base.IN0 +sink_addr[3] => comb.DATAB +sink_addr[3] => source_addr.DATAB +sink_addr[4] => burst_uncompress_address_base.IN0 +sink_addr[4] => comb.DATAB +sink_addr[4] => source_addr.DATAB +sink_addr[5] => burst_uncompress_address_base.IN0 +sink_addr[5] => comb.DATAB +sink_addr[5] => source_addr.DATAB +sink_addr[6] => burst_uncompress_address_base.IN0 +sink_addr[6] => comb.DATAB +sink_addr[6] => source_addr.DATAB +sink_addr[7] => burst_uncompress_address_base.IN0 +sink_addr[7] => comb.DATAB +sink_addr[7] => source_addr.DATAB +sink_addr[8] => burst_uncompress_address_base.IN0 +sink_addr[8] => comb.DATAB +sink_addr[8] => source_addr.DATAB +sink_addr[9] => burst_uncompress_address_base.IN0 +sink_addr[9] => comb.DATAB +sink_addr[9] => source_addr.DATAB +sink_addr[10] => burst_uncompress_address_base.IN0 +sink_addr[10] => comb.DATAB +sink_addr[10] => source_addr.DATAB +sink_addr[11] => burst_uncompress_address_base.IN0 +sink_addr[11] => comb.DATAB +sink_addr[11] => source_addr.DATAB +sink_addr[12] => burst_uncompress_address_base.IN0 +sink_addr[12] => comb.DATAB +sink_addr[12] => source_addr.DATAB +sink_addr[13] => burst_uncompress_address_base.IN0 +sink_addr[13] => comb.DATAB +sink_addr[13] => source_addr.DATAB +sink_addr[14] => burst_uncompress_address_base.IN0 +sink_addr[14] => comb.DATAB +sink_addr[14] => source_addr.DATAB +sink_addr[15] => burst_uncompress_address_base.IN0 +sink_addr[15] => comb.DATAB +sink_addr[15] => source_addr.DATAB +sink_addr[16] => burst_uncompress_address_base.IN0 +sink_addr[16] => comb.DATAB +sink_addr[16] => source_addr.DATAB +sink_addr[17] => burst_uncompress_address_base.IN0 +sink_addr[17] => comb.DATAB +sink_addr[17] => source_addr.DATAB +sink_addr[18] => burst_uncompress_address_base.IN0 +sink_addr[18] => comb.DATAB +sink_addr[18] => source_addr.DATAB +sink_addr[19] => burst_uncompress_address_base.IN0 +sink_addr[19] => comb.DATAB +sink_addr[19] => source_addr.DATAB +sink_addr[20] => burst_uncompress_address_base.IN0 +sink_addr[20] => comb.DATAB +sink_addr[20] => source_addr.DATAB +sink_addr[21] => burst_uncompress_address_base.IN0 +sink_addr[21] => comb.DATAB +sink_addr[21] => source_addr.DATAB +sink_addr[22] => burst_uncompress_address_base.IN0 +sink_addr[22] => comb.DATAB +sink_addr[22] => source_addr.DATAB +sink_addr[23] => burst_uncompress_address_base.IN0 +sink_addr[23] => comb.DATAB +sink_addr[23] => source_addr.DATAB +sink_addr[24] => burst_uncompress_address_base.IN0 +sink_addr[24] => comb.DATAB +sink_addr[24] => source_addr.DATAB +sink_addr[25] => burst_uncompress_address_base.IN0 +sink_addr[25] => comb.DATAB +sink_addr[25] => source_addr.DATAB +sink_burstwrap[0] => p1_burst_uncompress_address_offset[0].IN1 +sink_burstwrap[0] => source_burstwrap[0].DATAIN +sink_burstwrap[0] => burst_uncompress_address_base.IN1 +sink_burstwrap[1] => p1_burst_uncompress_address_offset[1].IN1 +sink_burstwrap[1] => source_burstwrap[1].DATAIN +sink_burstwrap[1] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[2].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[25].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[24].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[23].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[22].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[21].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[20].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[19].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[18].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[17].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[16].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[15].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[14].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[13].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[12].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[11].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[10].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[9].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[8].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[7].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[6].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[5].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[4].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[3].IN1 +sink_burstwrap[2] => source_burstwrap[2].DATAIN +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_byte_cnt[0] => source_byte_cnt.DATAB +sink_byte_cnt[0] => Add1.IN6 +sink_byte_cnt[0] => Equal1.IN2 +sink_byte_cnt[1] => source_byte_cnt.DATAB +sink_byte_cnt[1] => Add1.IN5 +sink_byte_cnt[1] => Equal1.IN1 +sink_byte_cnt[2] => source_byte_cnt.DATAB +sink_byte_cnt[2] => Add1.IN4 +sink_byte_cnt[2] => Equal1.IN0 +sink_is_compressed => last_packet_beat.IN1 +sink_burstsize[0] => Decoder0.IN2 +sink_burstsize[0] => source_burstsize[0].DATAIN +sink_burstsize[1] => Decoder0.IN1 +sink_burstsize[1] => source_burstsize[1].DATAIN +sink_burstsize[2] => Decoder0.IN0 +sink_burstsize[2] => source_burstsize[2].DATAIN +source_startofpacket <= source_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +source_endofpacket <= source_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +source_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE +source_ready => always1.IN1 +source_ready => sink_ready.IN1 +source_addr[0] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[1] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[2] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[3] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[4] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[5] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[6] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[7] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[8] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[9] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[10] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[11] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[12] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[13] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[14] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[15] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[16] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[17] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[18] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[19] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[20] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[21] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[22] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[23] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[24] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[25] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_burstwrap[0] <= sink_burstwrap[0].DB_MAX_OUTPUT_PORT_TYPE +source_burstwrap[1] <= sink_burstwrap[1].DB_MAX_OUTPUT_PORT_TYPE +source_burstwrap[2] <= sink_burstwrap[2].DB_MAX_OUTPUT_PORT_TYPE +source_byte_cnt[0] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE +source_byte_cnt[1] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE +source_byte_cnt[2] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE +source_is_compressed <= +source_burstsize[0] <= sink_burstsize[0].DB_MAX_OUTPUT_PORT_TYPE +source_burstsize[1] <= sink_burstsize[1].DB_MAX_OUTPUT_PORT_TYPE +source_burstsize[2] <= sink_burstsize[2].DB_MAX_OUTPUT_PORT_TYPE + + +|de0_nano_system|system:inst_cpu|altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo +clk => csr_readdata[0]~reg0.CLK +clk => csr_readdata[1]~reg0.CLK +clk => csr_readdata[2]~reg0.CLK +clk => csr_readdata[3]~reg0.CLK +clk => csr_readdata[4]~reg0.CLK +clk => csr_readdata[5]~reg0.CLK +clk => csr_readdata[6]~reg0.CLK +clk => csr_readdata[7]~reg0.CLK +clk => csr_readdata[8]~reg0.CLK +clk => csr_readdata[9]~reg0.CLK +clk => csr_readdata[10]~reg0.CLK +clk => csr_readdata[11]~reg0.CLK +clk => csr_readdata[12]~reg0.CLK +clk => csr_readdata[13]~reg0.CLK +clk => csr_readdata[14]~reg0.CLK +clk => csr_readdata[15]~reg0.CLK +clk => csr_readdata[16]~reg0.CLK +clk => csr_readdata[17]~reg0.CLK +clk => csr_readdata[18]~reg0.CLK +clk => csr_readdata[19]~reg0.CLK +clk => csr_readdata[20]~reg0.CLK +clk => csr_readdata[21]~reg0.CLK +clk => csr_readdata[22]~reg0.CLK +clk => csr_readdata[23]~reg0.CLK +clk => csr_readdata[24]~reg0.CLK +clk => csr_readdata[25]~reg0.CLK +clk => csr_readdata[26]~reg0.CLK +clk => csr_readdata[27]~reg0.CLK +clk => csr_readdata[28]~reg0.CLK +clk => csr_readdata[29]~reg0.CLK +clk => csr_readdata[30]~reg0.CLK +clk => csr_readdata[31]~reg0.CLK +clk => mem_used[1].CLK +clk => mem_used[0].CLK +clk => mem[1][0].CLK +clk => mem[1][1].CLK +clk => mem[1][2].CLK +clk => mem[1][3].CLK +clk => mem[1][4].CLK +clk => mem[1][5].CLK +clk => mem[1][6].CLK +clk => mem[1][7].CLK +clk => mem[1][8].CLK +clk => mem[1][9].CLK +clk => mem[1][10].CLK +clk => mem[1][11].CLK +clk => mem[1][12].CLK +clk => mem[1][13].CLK +clk => mem[1][14].CLK +clk => mem[1][15].CLK +clk => mem[1][16].CLK +clk => mem[1][17].CLK +clk => mem[1][18].CLK +clk => mem[1][19].CLK +clk => mem[1][20].CLK +clk => mem[1][21].CLK +clk => mem[1][22].CLK +clk => mem[1][23].CLK +clk => mem[1][24].CLK +clk => mem[1][25].CLK +clk => mem[1][26].CLK +clk => mem[1][27].CLK +clk => mem[1][28].CLK +clk => mem[1][29].CLK +clk => mem[1][30].CLK +clk => mem[1][31].CLK +clk => mem[1][32].CLK +clk => mem[1][33].CLK +clk => mem[1][34].CLK +clk => mem[1][35].CLK +clk => mem[1][36].CLK +clk => mem[1][37].CLK +clk => mem[1][38].CLK +clk => mem[1][39].CLK +clk => mem[1][40].CLK +clk => mem[1][41].CLK +clk => mem[1][42].CLK +clk => mem[1][43].CLK +clk => mem[1][44].CLK +clk => mem[1][45].CLK +clk => mem[1][46].CLK +clk => mem[1][47].CLK +clk => mem[1][48].CLK +clk => mem[1][49].CLK +clk => mem[1][50].CLK +clk => mem[1][51].CLK +clk => mem[1][52].CLK +clk => mem[1][53].CLK +clk => mem[1][54].CLK +clk => mem[1][55].CLK +clk => mem[1][56].CLK +clk => mem[1][57].CLK +clk => mem[1][58].CLK +clk => mem[1][59].CLK +clk => mem[1][60].CLK +clk => mem[1][61].CLK +clk => mem[1][62].CLK +clk => mem[1][63].CLK +clk => mem[1][64].CLK +clk => mem[1][65].CLK +clk => mem[1][66].CLK +clk => mem[1][67].CLK +clk => mem[1][68].CLK +clk => mem[1][69].CLK +clk => mem[1][70].CLK +clk => mem[1][71].CLK +clk => mem[1][72].CLK +clk => mem[1][73].CLK +clk => mem[1][74].CLK +clk => mem[1][75].CLK +clk => mem[1][76].CLK +clk => mem[1][77].CLK +clk => mem[1][78].CLK +clk => mem[1][79].CLK +clk => mem[1][80].CLK +clk => mem[1][81].CLK +clk => mem[1][82].CLK +clk => mem[1][83].CLK +clk => mem[1][84].CLK +clk => mem[1][85].CLK +clk => mem[1][86].CLK +clk => mem[1][87].CLK +clk => mem[1][88].CLK +clk => mem[1][89].CLK +clk => mem[1][90].CLK +clk => mem[1][91].CLK +clk => mem[1][92].CLK +clk => mem[1][93].CLK +clk => mem[1][94].CLK +clk => mem[1][95].CLK +clk => mem[1][96].CLK +clk => mem[1][97].CLK +clk => mem[1][98].CLK +clk => mem[1][99].CLK +clk => mem[1][100].CLK +clk => mem[1][101].CLK +clk => mem[1][102].CLK +clk => mem[1][103].CLK +clk => mem[0][0].CLK +clk => mem[0][1].CLK +clk => mem[0][2].CLK +clk => mem[0][3].CLK +clk => mem[0][4].CLK +clk => mem[0][5].CLK +clk => mem[0][6].CLK +clk => mem[0][7].CLK +clk => mem[0][8].CLK +clk => mem[0][9].CLK +clk => mem[0][10].CLK +clk => mem[0][11].CLK +clk => mem[0][12].CLK +clk => mem[0][13].CLK +clk => mem[0][14].CLK +clk => mem[0][15].CLK +clk => mem[0][16].CLK +clk => mem[0][17].CLK +clk => mem[0][18].CLK +clk => mem[0][19].CLK +clk => mem[0][20].CLK +clk => mem[0][21].CLK +clk => mem[0][22].CLK +clk => mem[0][23].CLK +clk => mem[0][24].CLK +clk => mem[0][25].CLK +clk => mem[0][26].CLK +clk => mem[0][27].CLK +clk => mem[0][28].CLK +clk => mem[0][29].CLK +clk => mem[0][30].CLK +clk => mem[0][31].CLK +clk => mem[0][32].CLK +clk => mem[0][33].CLK +clk => mem[0][34].CLK +clk => mem[0][35].CLK +clk => mem[0][36].CLK +clk => mem[0][37].CLK +clk => mem[0][38].CLK +clk => mem[0][39].CLK +clk => mem[0][40].CLK +clk => mem[0][41].CLK +clk => mem[0][42].CLK +clk => mem[0][43].CLK +clk => mem[0][44].CLK +clk => mem[0][45].CLK +clk => mem[0][46].CLK +clk => mem[0][47].CLK +clk => mem[0][48].CLK +clk => mem[0][49].CLK +clk => mem[0][50].CLK +clk => mem[0][51].CLK +clk => mem[0][52].CLK +clk => mem[0][53].CLK +clk => mem[0][54].CLK +clk => mem[0][55].CLK +clk => mem[0][56].CLK +clk => mem[0][57].CLK +clk => mem[0][58].CLK +clk => mem[0][59].CLK +clk => mem[0][60].CLK +clk => mem[0][61].CLK +clk => mem[0][62].CLK +clk => mem[0][63].CLK +clk => mem[0][64].CLK +clk => mem[0][65].CLK +clk => mem[0][66].CLK +clk => mem[0][67].CLK +clk => mem[0][68].CLK +clk => mem[0][69].CLK +clk => mem[0][70].CLK +clk => mem[0][71].CLK +clk => mem[0][72].CLK +clk => mem[0][73].CLK +clk => mem[0][74].CLK +clk => mem[0][75].CLK +clk => mem[0][76].CLK +clk => mem[0][77].CLK +clk => mem[0][78].CLK +clk => mem[0][79].CLK +clk => mem[0][80].CLK +clk => mem[0][81].CLK +clk => mem[0][82].CLK +clk => mem[0][83].CLK +clk => mem[0][84].CLK +clk => mem[0][85].CLK +clk => mem[0][86].CLK +clk => mem[0][87].CLK +clk => mem[0][88].CLK +clk => mem[0][89].CLK +clk => mem[0][90].CLK +clk => mem[0][91].CLK +clk => mem[0][92].CLK +clk => mem[0][93].CLK +clk => mem[0][94].CLK +clk => mem[0][95].CLK +clk => mem[0][96].CLK +clk => mem[0][97].CLK +clk => mem[0][98].CLK +clk => mem[0][99].CLK +clk => mem[0][100].CLK +clk => mem[0][101].CLK +clk => mem[0][102].CLK +clk => mem[0][103].CLK +reset => csr_readdata[0]~reg0.ACLR +reset => csr_readdata[1]~reg0.ACLR +reset => csr_readdata[2]~reg0.ACLR +reset => csr_readdata[3]~reg0.ACLR +reset => csr_readdata[4]~reg0.ACLR +reset => csr_readdata[5]~reg0.ACLR +reset => csr_readdata[6]~reg0.ACLR +reset => csr_readdata[7]~reg0.ACLR +reset => csr_readdata[8]~reg0.ACLR +reset => csr_readdata[9]~reg0.ACLR +reset => csr_readdata[10]~reg0.ACLR +reset => csr_readdata[11]~reg0.ACLR +reset => csr_readdata[12]~reg0.ACLR +reset => csr_readdata[13]~reg0.ACLR +reset => csr_readdata[14]~reg0.ACLR +reset => csr_readdata[15]~reg0.ACLR +reset => csr_readdata[16]~reg0.ACLR +reset => csr_readdata[17]~reg0.ACLR +reset => csr_readdata[18]~reg0.ACLR +reset => csr_readdata[19]~reg0.ACLR +reset => csr_readdata[20]~reg0.ACLR +reset => csr_readdata[21]~reg0.ACLR +reset => csr_readdata[22]~reg0.ACLR +reset => csr_readdata[23]~reg0.ACLR +reset => csr_readdata[24]~reg0.ACLR +reset => csr_readdata[25]~reg0.ACLR +reset => csr_readdata[26]~reg0.ACLR +reset => csr_readdata[27]~reg0.ACLR +reset => csr_readdata[28]~reg0.ACLR +reset => csr_readdata[29]~reg0.ACLR +reset => csr_readdata[30]~reg0.ACLR +reset => csr_readdata[31]~reg0.ACLR +reset => mem_used[1].ACLR +reset => mem_used[0].ACLR +reset => mem[1][0].ACLR +reset => mem[1][1].ACLR +reset => mem[1][2].ACLR +reset => mem[1][3].ACLR +reset => mem[1][4].ACLR +reset => mem[1][5].ACLR +reset => mem[1][6].ACLR +reset => mem[1][7].ACLR +reset => mem[1][8].ACLR +reset => mem[1][9].ACLR +reset => mem[1][10].ACLR +reset => mem[1][11].ACLR +reset => mem[1][12].ACLR +reset => mem[1][13].ACLR +reset => mem[1][14].ACLR +reset => mem[1][15].ACLR +reset => mem[1][16].ACLR +reset => mem[1][17].ACLR +reset => mem[1][18].ACLR +reset => mem[1][19].ACLR +reset => mem[1][20].ACLR +reset => mem[1][21].ACLR +reset => mem[1][22].ACLR +reset => mem[1][23].ACLR +reset => mem[1][24].ACLR +reset => mem[1][25].ACLR +reset => mem[1][26].ACLR +reset => mem[1][27].ACLR +reset => mem[1][28].ACLR +reset => mem[1][29].ACLR +reset => mem[1][30].ACLR +reset => mem[1][31].ACLR +reset => mem[1][32].ACLR +reset => mem[1][33].ACLR +reset => mem[1][34].ACLR +reset => mem[1][35].ACLR +reset => mem[1][36].ACLR +reset => mem[1][37].ACLR +reset => mem[1][38].ACLR +reset => mem[1][39].ACLR +reset => mem[1][40].ACLR +reset => mem[1][41].ACLR +reset => mem[1][42].ACLR +reset => mem[1][43].ACLR +reset => mem[1][44].ACLR +reset => mem[1][45].ACLR +reset => mem[1][46].ACLR +reset => mem[1][47].ACLR +reset => mem[1][48].ACLR +reset => mem[1][49].ACLR +reset => mem[1][50].ACLR +reset => mem[1][51].ACLR +reset => mem[1][52].ACLR +reset => mem[1][53].ACLR +reset => mem[1][54].ACLR +reset => mem[1][55].ACLR +reset => mem[1][56].ACLR +reset => mem[1][57].ACLR +reset => mem[1][58].ACLR +reset => mem[1][59].ACLR +reset => mem[1][60].ACLR +reset => mem[1][61].ACLR +reset => mem[1][62].ACLR +reset => mem[1][63].ACLR +reset => mem[1][64].ACLR +reset => mem[1][65].ACLR +reset => mem[1][66].ACLR +reset => mem[1][67].ACLR +reset => mem[1][68].ACLR +reset => mem[1][69].ACLR +reset => mem[1][70].ACLR +reset => mem[1][71].ACLR +reset => mem[1][72].ACLR +reset => mem[1][73].ACLR +reset => mem[1][74].ACLR +reset => mem[1][75].ACLR +reset => mem[1][76].ACLR +reset => mem[1][77].ACLR +reset => mem[1][78].ACLR +reset => mem[1][79].ACLR +reset => mem[1][80].ACLR +reset => mem[1][81].ACLR +reset => mem[1][82].ACLR +reset => mem[1][83].ACLR +reset => mem[1][84].ACLR +reset => mem[1][85].ACLR +reset => mem[1][86].ACLR +reset => mem[1][87].ACLR +reset => mem[1][88].ACLR +reset => mem[1][89].ACLR +reset => mem[1][90].ACLR +reset => mem[1][91].ACLR +reset => mem[1][92].ACLR +reset => mem[1][93].ACLR +reset => mem[1][94].ACLR +reset => mem[1][95].ACLR +reset => mem[1][96].ACLR +reset => mem[1][97].ACLR +reset => mem[1][98].ACLR +reset => mem[1][99].ACLR +reset => mem[1][100].ACLR +reset => mem[1][101].ACLR +reset => mem[1][102].ACLR +reset => mem[1][103].ACLR +reset => mem[0][0].ACLR +reset => mem[0][1].ACLR +reset => mem[0][2].ACLR +reset => mem[0][3].ACLR +reset => mem[0][4].ACLR +reset => mem[0][5].ACLR +reset => mem[0][6].ACLR +reset => mem[0][7].ACLR +reset => mem[0][8].ACLR +reset => mem[0][9].ACLR +reset => mem[0][10].ACLR +reset => mem[0][11].ACLR +reset => mem[0][12].ACLR +reset => mem[0][13].ACLR +reset => mem[0][14].ACLR +reset => mem[0][15].ACLR +reset => mem[0][16].ACLR +reset => mem[0][17].ACLR +reset => mem[0][18].ACLR +reset => mem[0][19].ACLR +reset => mem[0][20].ACLR +reset => mem[0][21].ACLR +reset => mem[0][22].ACLR +reset => mem[0][23].ACLR +reset => mem[0][24].ACLR +reset => mem[0][25].ACLR +reset => mem[0][26].ACLR +reset => mem[0][27].ACLR +reset => mem[0][28].ACLR +reset => mem[0][29].ACLR +reset => mem[0][30].ACLR +reset => mem[0][31].ACLR +reset => mem[0][32].ACLR +reset => mem[0][33].ACLR +reset => mem[0][34].ACLR +reset => mem[0][35].ACLR +reset => mem[0][36].ACLR +reset => mem[0][37].ACLR +reset => mem[0][38].ACLR +reset => mem[0][39].ACLR +reset => mem[0][40].ACLR +reset => mem[0][41].ACLR +reset => mem[0][42].ACLR +reset => mem[0][43].ACLR +reset => mem[0][44].ACLR +reset => mem[0][45].ACLR +reset => mem[0][46].ACLR +reset => mem[0][47].ACLR +reset => mem[0][48].ACLR +reset => mem[0][49].ACLR +reset => mem[0][50].ACLR +reset => mem[0][51].ACLR +reset => mem[0][52].ACLR +reset => mem[0][53].ACLR +reset => mem[0][54].ACLR +reset => mem[0][55].ACLR +reset => mem[0][56].ACLR +reset => mem[0][57].ACLR +reset => mem[0][58].ACLR +reset => mem[0][59].ACLR +reset => mem[0][60].ACLR +reset => mem[0][61].ACLR +reset => mem[0][62].ACLR +reset => mem[0][63].ACLR +reset => mem[0][64].ACLR +reset => mem[0][65].ACLR +reset => mem[0][66].ACLR +reset => mem[0][67].ACLR +reset => mem[0][68].ACLR +reset => mem[0][69].ACLR +reset => mem[0][70].ACLR +reset => mem[0][71].ACLR +reset => mem[0][72].ACLR +reset => mem[0][73].ACLR +reset => mem[0][74].ACLR +reset => mem[0][75].ACLR +reset => mem[0][76].ACLR +reset => mem[0][77].ACLR +reset => mem[0][78].ACLR +reset => mem[0][79].ACLR +reset => mem[0][80].ACLR +reset => mem[0][81].ACLR +reset => mem[0][82].ACLR +reset => mem[0][83].ACLR +reset => mem[0][84].ACLR +reset => mem[0][85].ACLR +reset => mem[0][86].ACLR +reset => mem[0][87].ACLR +reset => mem[0][88].ACLR +reset => mem[0][89].ACLR +reset => mem[0][90].ACLR +reset => mem[0][91].ACLR +reset => mem[0][92].ACLR +reset => mem[0][93].ACLR +reset => mem[0][94].ACLR +reset => mem[0][95].ACLR +reset => mem[0][96].ACLR +reset => mem[0][97].ACLR +reset => mem[0][98].ACLR +reset => mem[0][99].ACLR +reset => mem[0][100].ACLR +reset => mem[0][101].ACLR +reset => mem[0][102].ACLR +reset => mem[0][103].ACLR +in_data[0] => mem.DATAB +in_data[1] => mem.DATAB +in_data[2] => mem.DATAB +in_data[3] => mem.DATAB +in_data[4] => mem.DATAB +in_data[5] => mem.DATAB +in_data[6] => mem.DATAB +in_data[7] => mem.DATAB +in_data[8] => mem.DATAB +in_data[9] => mem.DATAB +in_data[10] => mem.DATAB +in_data[11] => mem.DATAB +in_data[12] => mem.DATAB +in_data[13] => mem.DATAB +in_data[14] => mem.DATAB +in_data[15] => mem.DATAB +in_data[16] => mem.DATAB +in_data[17] => mem.DATAB +in_data[18] => mem.DATAB +in_data[19] => mem.DATAB +in_data[20] => mem.DATAB +in_data[21] => mem.DATAB +in_data[22] => mem.DATAB +in_data[23] => mem.DATAB +in_data[24] => mem.DATAB +in_data[25] => mem.DATAB +in_data[26] => mem.DATAB +in_data[27] => mem.DATAB +in_data[28] => mem.DATAB +in_data[29] => mem.DATAB +in_data[30] => mem.DATAB +in_data[31] => mem.DATAB +in_data[32] => mem.DATAB +in_data[33] => mem.DATAB +in_data[34] => mem.DATAB +in_data[35] => mem.DATAB +in_data[36] => mem.DATAB +in_data[37] => mem.DATAB +in_data[38] => mem.DATAB +in_data[39] => mem.DATAB +in_data[40] => mem.DATAB +in_data[41] => mem.DATAB +in_data[42] => mem.DATAB +in_data[43] => mem.DATAB +in_data[44] => mem.DATAB +in_data[45] => mem.DATAB +in_data[46] => mem.DATAB +in_data[47] => mem.DATAB +in_data[48] => mem.DATAB +in_data[49] => mem.DATAB +in_data[50] => mem.DATAB +in_data[51] => mem.DATAB +in_data[52] => mem.DATAB +in_data[53] => mem.DATAB +in_data[54] => mem.DATAB +in_data[55] => mem.DATAB +in_data[56] => mem.DATAB +in_data[57] => mem.DATAB +in_data[58] => mem.DATAB +in_data[59] => mem.DATAB +in_data[60] => mem.DATAB +in_data[61] => mem.DATAB +in_data[62] => mem.DATAB +in_data[63] => mem.DATAB +in_data[64] => mem.DATAB +in_data[65] => mem.DATAB +in_data[66] => mem.DATAB +in_data[67] => mem.DATAB +in_data[68] => mem.DATAB +in_data[69] => mem.DATAB +in_data[70] => mem.DATAB +in_data[71] => mem.DATAB +in_data[72] => mem.DATAB +in_data[73] => mem.DATAB +in_data[74] => mem.DATAB +in_data[75] => mem.DATAB +in_data[76] => mem.DATAB +in_data[77] => mem.DATAB +in_data[78] => mem.DATAB +in_data[79] => mem.DATAB +in_data[80] => mem.DATAB +in_data[81] => mem.DATAB +in_data[82] => mem.DATAB +in_data[83] => mem.DATAB +in_data[84] => mem.DATAB +in_data[85] => mem.DATAB +in_data[86] => mem.DATAB +in_data[87] => mem.DATAB +in_data[88] => mem.DATAB +in_data[89] => mem.DATAB +in_data[90] => mem.DATAB +in_data[91] => mem.DATAB +in_data[92] => mem.DATAB +in_data[93] => mem.DATAB +in_data[94] => mem.DATAB +in_data[95] => mem.DATAB +in_data[96] => mem.DATAB +in_data[97] => mem.DATAB +in_data[98] => mem.DATAB +in_data[99] => mem.DATAB +in_data[100] => mem.DATAB +in_data[101] => mem.DATAB +in_valid => write.IN1 +in_startofpacket => mem.DATAB +in_endofpacket => mem.DATAB +in_empty[0] => ~NO_FANOUT~ +in_error[0] => out_error[0].DATAIN +in_error[0] => out_empty[0].DATAIN +in_channel[0] => out_channel[0].DATAIN +in_ready <= mem_used[1].DB_MAX_OUTPUT_PORT_TYPE +out_data[0] <= mem[0][0].DB_MAX_OUTPUT_PORT_TYPE +out_data[1] <= mem[0][1].DB_MAX_OUTPUT_PORT_TYPE +out_data[2] <= mem[0][2].DB_MAX_OUTPUT_PORT_TYPE +out_data[3] <= mem[0][3].DB_MAX_OUTPUT_PORT_TYPE +out_data[4] <= mem[0][4].DB_MAX_OUTPUT_PORT_TYPE +out_data[5] <= mem[0][5].DB_MAX_OUTPUT_PORT_TYPE +out_data[6] <= mem[0][6].DB_MAX_OUTPUT_PORT_TYPE +out_data[7] <= mem[0][7].DB_MAX_OUTPUT_PORT_TYPE +out_data[8] <= mem[0][8].DB_MAX_OUTPUT_PORT_TYPE +out_data[9] <= mem[0][9].DB_MAX_OUTPUT_PORT_TYPE +out_data[10] <= mem[0][10].DB_MAX_OUTPUT_PORT_TYPE +out_data[11] <= mem[0][11].DB_MAX_OUTPUT_PORT_TYPE +out_data[12] <= mem[0][12].DB_MAX_OUTPUT_PORT_TYPE +out_data[13] <= mem[0][13].DB_MAX_OUTPUT_PORT_TYPE +out_data[14] <= mem[0][14].DB_MAX_OUTPUT_PORT_TYPE +out_data[15] <= mem[0][15].DB_MAX_OUTPUT_PORT_TYPE +out_data[16] <= mem[0][16].DB_MAX_OUTPUT_PORT_TYPE +out_data[17] <= mem[0][17].DB_MAX_OUTPUT_PORT_TYPE +out_data[18] <= mem[0][18].DB_MAX_OUTPUT_PORT_TYPE +out_data[19] <= mem[0][19].DB_MAX_OUTPUT_PORT_TYPE +out_data[20] <= mem[0][20].DB_MAX_OUTPUT_PORT_TYPE +out_data[21] <= mem[0][21].DB_MAX_OUTPUT_PORT_TYPE +out_data[22] <= mem[0][22].DB_MAX_OUTPUT_PORT_TYPE +out_data[23] <= mem[0][23].DB_MAX_OUTPUT_PORT_TYPE +out_data[24] <= mem[0][24].DB_MAX_OUTPUT_PORT_TYPE +out_data[25] <= mem[0][25].DB_MAX_OUTPUT_PORT_TYPE +out_data[26] <= mem[0][26].DB_MAX_OUTPUT_PORT_TYPE +out_data[27] <= mem[0][27].DB_MAX_OUTPUT_PORT_TYPE +out_data[28] <= mem[0][28].DB_MAX_OUTPUT_PORT_TYPE +out_data[29] <= mem[0][29].DB_MAX_OUTPUT_PORT_TYPE +out_data[30] <= mem[0][30].DB_MAX_OUTPUT_PORT_TYPE +out_data[31] <= mem[0][31].DB_MAX_OUTPUT_PORT_TYPE +out_data[32] <= mem[0][32].DB_MAX_OUTPUT_PORT_TYPE +out_data[33] <= mem[0][33].DB_MAX_OUTPUT_PORT_TYPE +out_data[34] <= mem[0][34].DB_MAX_OUTPUT_PORT_TYPE +out_data[35] <= mem[0][35].DB_MAX_OUTPUT_PORT_TYPE +out_data[36] <= mem[0][36].DB_MAX_OUTPUT_PORT_TYPE +out_data[37] <= mem[0][37].DB_MAX_OUTPUT_PORT_TYPE +out_data[38] <= mem[0][38].DB_MAX_OUTPUT_PORT_TYPE +out_data[39] <= mem[0][39].DB_MAX_OUTPUT_PORT_TYPE +out_data[40] <= mem[0][40].DB_MAX_OUTPUT_PORT_TYPE +out_data[41] <= mem[0][41].DB_MAX_OUTPUT_PORT_TYPE +out_data[42] <= mem[0][42].DB_MAX_OUTPUT_PORT_TYPE +out_data[43] <= mem[0][43].DB_MAX_OUTPUT_PORT_TYPE +out_data[44] <= mem[0][44].DB_MAX_OUTPUT_PORT_TYPE +out_data[45] <= mem[0][45].DB_MAX_OUTPUT_PORT_TYPE +out_data[46] <= mem[0][46].DB_MAX_OUTPUT_PORT_TYPE +out_data[47] <= mem[0][47].DB_MAX_OUTPUT_PORT_TYPE +out_data[48] <= mem[0][48].DB_MAX_OUTPUT_PORT_TYPE +out_data[49] <= mem[0][49].DB_MAX_OUTPUT_PORT_TYPE +out_data[50] <= mem[0][50].DB_MAX_OUTPUT_PORT_TYPE +out_data[51] <= mem[0][51].DB_MAX_OUTPUT_PORT_TYPE +out_data[52] <= mem[0][52].DB_MAX_OUTPUT_PORT_TYPE +out_data[53] <= mem[0][53].DB_MAX_OUTPUT_PORT_TYPE +out_data[54] <= mem[0][54].DB_MAX_OUTPUT_PORT_TYPE +out_data[55] <= mem[0][55].DB_MAX_OUTPUT_PORT_TYPE +out_data[56] <= mem[0][56].DB_MAX_OUTPUT_PORT_TYPE +out_data[57] <= mem[0][57].DB_MAX_OUTPUT_PORT_TYPE +out_data[58] <= mem[0][58].DB_MAX_OUTPUT_PORT_TYPE +out_data[59] <= mem[0][59].DB_MAX_OUTPUT_PORT_TYPE +out_data[60] <= mem[0][60].DB_MAX_OUTPUT_PORT_TYPE +out_data[61] <= mem[0][61].DB_MAX_OUTPUT_PORT_TYPE +out_data[62] <= mem[0][62].DB_MAX_OUTPUT_PORT_TYPE +out_data[63] <= mem[0][63].DB_MAX_OUTPUT_PORT_TYPE +out_data[64] <= mem[0][64].DB_MAX_OUTPUT_PORT_TYPE +out_data[65] <= mem[0][65].DB_MAX_OUTPUT_PORT_TYPE +out_data[66] <= mem[0][66].DB_MAX_OUTPUT_PORT_TYPE +out_data[67] <= mem[0][67].DB_MAX_OUTPUT_PORT_TYPE +out_data[68] <= mem[0][68].DB_MAX_OUTPUT_PORT_TYPE +out_data[69] <= mem[0][69].DB_MAX_OUTPUT_PORT_TYPE +out_data[70] <= mem[0][70].DB_MAX_OUTPUT_PORT_TYPE +out_data[71] <= mem[0][71].DB_MAX_OUTPUT_PORT_TYPE +out_data[72] <= mem[0][72].DB_MAX_OUTPUT_PORT_TYPE +out_data[73] <= mem[0][73].DB_MAX_OUTPUT_PORT_TYPE +out_data[74] <= mem[0][74].DB_MAX_OUTPUT_PORT_TYPE +out_data[75] <= mem[0][75].DB_MAX_OUTPUT_PORT_TYPE +out_data[76] <= mem[0][76].DB_MAX_OUTPUT_PORT_TYPE +out_data[77] <= mem[0][77].DB_MAX_OUTPUT_PORT_TYPE +out_data[78] <= mem[0][78].DB_MAX_OUTPUT_PORT_TYPE +out_data[79] <= mem[0][79].DB_MAX_OUTPUT_PORT_TYPE +out_data[80] <= mem[0][80].DB_MAX_OUTPUT_PORT_TYPE +out_data[81] <= mem[0][81].DB_MAX_OUTPUT_PORT_TYPE +out_data[82] <= mem[0][82].DB_MAX_OUTPUT_PORT_TYPE +out_data[83] <= mem[0][83].DB_MAX_OUTPUT_PORT_TYPE +out_data[84] <= mem[0][84].DB_MAX_OUTPUT_PORT_TYPE +out_data[85] <= mem[0][85].DB_MAX_OUTPUT_PORT_TYPE +out_data[86] <= mem[0][86].DB_MAX_OUTPUT_PORT_TYPE +out_data[87] <= mem[0][87].DB_MAX_OUTPUT_PORT_TYPE +out_data[88] <= mem[0][88].DB_MAX_OUTPUT_PORT_TYPE +out_data[89] <= mem[0][89].DB_MAX_OUTPUT_PORT_TYPE +out_data[90] <= mem[0][90].DB_MAX_OUTPUT_PORT_TYPE +out_data[91] <= mem[0][91].DB_MAX_OUTPUT_PORT_TYPE +out_data[92] <= mem[0][92].DB_MAX_OUTPUT_PORT_TYPE +out_data[93] <= mem[0][93].DB_MAX_OUTPUT_PORT_TYPE +out_data[94] <= mem[0][94].DB_MAX_OUTPUT_PORT_TYPE +out_data[95] <= mem[0][95].DB_MAX_OUTPUT_PORT_TYPE +out_data[96] <= mem[0][96].DB_MAX_OUTPUT_PORT_TYPE +out_data[97] <= mem[0][97].DB_MAX_OUTPUT_PORT_TYPE +out_data[98] <= mem[0][98].DB_MAX_OUTPUT_PORT_TYPE +out_data[99] <= mem[0][99].DB_MAX_OUTPUT_PORT_TYPE +out_data[100] <= mem[0][100].DB_MAX_OUTPUT_PORT_TYPE +out_data[101] <= mem[0][101].DB_MAX_OUTPUT_PORT_TYPE +out_valid <= mem_used[0].DB_MAX_OUTPUT_PORT_TYPE +out_startofpacket <= mem[0][103].DB_MAX_OUTPUT_PORT_TYPE +out_endofpacket <= mem[0][102].DB_MAX_OUTPUT_PORT_TYPE +out_empty[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE +out_error[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE +out_channel[0] <= in_channel[0].DB_MAX_OUTPUT_PORT_TYPE +out_ready => internal_out_ready.IN1 +csr_address[0] => ~NO_FANOUT~ +csr_address[1] => ~NO_FANOUT~ +csr_write => ~NO_FANOUT~ +csr_read => csr_readdata[0]~reg0.ENA +csr_read => csr_readdata[31]~reg0.ENA +csr_read => csr_readdata[30]~reg0.ENA +csr_read => csr_readdata[29]~reg0.ENA +csr_read => csr_readdata[28]~reg0.ENA +csr_read => csr_readdata[27]~reg0.ENA +csr_read => csr_readdata[26]~reg0.ENA +csr_read => csr_readdata[25]~reg0.ENA +csr_read => csr_readdata[24]~reg0.ENA +csr_read => csr_readdata[23]~reg0.ENA +csr_read => csr_readdata[22]~reg0.ENA +csr_read => csr_readdata[21]~reg0.ENA +csr_read => csr_readdata[20]~reg0.ENA +csr_read => csr_readdata[19]~reg0.ENA +csr_read => csr_readdata[18]~reg0.ENA +csr_read => csr_readdata[17]~reg0.ENA +csr_read => csr_readdata[16]~reg0.ENA +csr_read => csr_readdata[15]~reg0.ENA +csr_read => csr_readdata[14]~reg0.ENA +csr_read => csr_readdata[13]~reg0.ENA +csr_read => csr_readdata[12]~reg0.ENA +csr_read => csr_readdata[11]~reg0.ENA +csr_read => csr_readdata[10]~reg0.ENA +csr_read => csr_readdata[9]~reg0.ENA +csr_read => csr_readdata[8]~reg0.ENA +csr_read => csr_readdata[7]~reg0.ENA +csr_read => csr_readdata[6]~reg0.ENA +csr_read => csr_readdata[5]~reg0.ENA +csr_read => csr_readdata[4]~reg0.ENA +csr_read => csr_readdata[3]~reg0.ENA +csr_read => csr_readdata[2]~reg0.ENA +csr_read => csr_readdata[1]~reg0.ENA +csr_writedata[0] => ~NO_FANOUT~ +csr_writedata[1] => ~NO_FANOUT~ +csr_writedata[2] => ~NO_FANOUT~ +csr_writedata[3] => ~NO_FANOUT~ +csr_writedata[4] => ~NO_FANOUT~ +csr_writedata[5] => ~NO_FANOUT~ +csr_writedata[6] => ~NO_FANOUT~ +csr_writedata[7] => ~NO_FANOUT~ +csr_writedata[8] => ~NO_FANOUT~ +csr_writedata[9] => ~NO_FANOUT~ +csr_writedata[10] => ~NO_FANOUT~ +csr_writedata[11] => ~NO_FANOUT~ +csr_writedata[12] => ~NO_FANOUT~ +csr_writedata[13] => ~NO_FANOUT~ +csr_writedata[14] => ~NO_FANOUT~ +csr_writedata[15] => ~NO_FANOUT~ +csr_writedata[16] => ~NO_FANOUT~ +csr_writedata[17] => ~NO_FANOUT~ +csr_writedata[18] => ~NO_FANOUT~ +csr_writedata[19] => ~NO_FANOUT~ +csr_writedata[20] => ~NO_FANOUT~ +csr_writedata[21] => ~NO_FANOUT~ +csr_writedata[22] => ~NO_FANOUT~ +csr_writedata[23] => ~NO_FANOUT~ +csr_writedata[24] => ~NO_FANOUT~ +csr_writedata[25] => ~NO_FANOUT~ +csr_writedata[26] => ~NO_FANOUT~ +csr_writedata[27] => ~NO_FANOUT~ +csr_writedata[28] => ~NO_FANOUT~ +csr_writedata[29] => ~NO_FANOUT~ +csr_writedata[30] => ~NO_FANOUT~ +csr_writedata[31] => ~NO_FANOUT~ +csr_readdata[0] <= csr_readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[1] <= csr_readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[2] <= csr_readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[3] <= csr_readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[4] <= csr_readdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[5] <= csr_readdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[6] <= csr_readdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[7] <= csr_readdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[8] <= csr_readdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[9] <= csr_readdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[10] <= csr_readdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[11] <= csr_readdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[12] <= csr_readdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[13] <= csr_readdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[14] <= csr_readdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[15] <= csr_readdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[16] <= csr_readdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[17] <= csr_readdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[18] <= csr_readdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[19] <= csr_readdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[20] <= csr_readdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[21] <= csr_readdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[22] <= csr_readdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[23] <= csr_readdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[24] <= csr_readdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[25] <= csr_readdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[26] <= csr_readdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[27] <= csr_readdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[28] <= csr_readdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[29] <= csr_readdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[30] <= csr_readdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[31] <= csr_readdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE +almost_full_data <= +almost_empty_data <= + + +|de0_nano_system|system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent +clk => clk.IN1 +reset => reset.IN1 +m0_address[0] <= +m0_address[1] <= cp_data[19].DB_MAX_OUTPUT_PORT_TYPE +m0_address[2] <= cp_data[20].DB_MAX_OUTPUT_PORT_TYPE +m0_address[3] <= cp_data[21].DB_MAX_OUTPUT_PORT_TYPE +m0_address[4] <= cp_data[22].DB_MAX_OUTPUT_PORT_TYPE +m0_address[5] <= cp_data[23].DB_MAX_OUTPUT_PORT_TYPE +m0_address[6] <= cp_data[24].DB_MAX_OUTPUT_PORT_TYPE +m0_address[7] <= cp_data[25].DB_MAX_OUTPUT_PORT_TYPE +m0_address[8] <= cp_data[26].DB_MAX_OUTPUT_PORT_TYPE +m0_address[9] <= cp_data[27].DB_MAX_OUTPUT_PORT_TYPE +m0_address[10] <= cp_data[28].DB_MAX_OUTPUT_PORT_TYPE +m0_address[11] <= cp_data[29].DB_MAX_OUTPUT_PORT_TYPE +m0_address[12] <= cp_data[30].DB_MAX_OUTPUT_PORT_TYPE +m0_address[13] <= cp_data[31].DB_MAX_OUTPUT_PORT_TYPE +m0_address[14] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE +m0_address[15] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE +m0_address[16] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE +m0_address[17] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE +m0_address[18] <= cp_data[36].DB_MAX_OUTPUT_PORT_TYPE +m0_address[19] <= cp_data[37].DB_MAX_OUTPUT_PORT_TYPE +m0_address[20] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE +m0_address[21] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE +m0_address[22] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE +m0_address[23] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE +m0_address[24] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE +m0_address[25] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE +m0_burstcount[0] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE +m0_burstcount[1] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[0] <= cp_data[16].DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[1] <= cp_data[17].DB_MAX_OUTPUT_PORT_TYPE +m0_read <= m0_read.DB_MAX_OUTPUT_PORT_TYPE +m0_readdata[0] => rdata_fifo_src_data[0].DATAIN +m0_readdata[1] => rdata_fifo_src_data[1].DATAIN +m0_readdata[2] => rdata_fifo_src_data[2].DATAIN +m0_readdata[3] => rdata_fifo_src_data[3].DATAIN +m0_readdata[4] => rdata_fifo_src_data[4].DATAIN +m0_readdata[5] => rdata_fifo_src_data[5].DATAIN +m0_readdata[6] => rdata_fifo_src_data[6].DATAIN +m0_readdata[7] => rdata_fifo_src_data[7].DATAIN +m0_readdata[8] => rdata_fifo_src_data[8].DATAIN +m0_readdata[9] => rdata_fifo_src_data[9].DATAIN +m0_readdata[10] => rdata_fifo_src_data[10].DATAIN +m0_readdata[11] => rdata_fifo_src_data[11].DATAIN +m0_readdata[12] => rdata_fifo_src_data[12].DATAIN +m0_readdata[13] => rdata_fifo_src_data[13].DATAIN +m0_readdata[14] => rdata_fifo_src_data[14].DATAIN +m0_readdata[15] => rdata_fifo_src_data[15].DATAIN +m0_waitrequest => cp_ready.IN1 +m0_write <= m0_write.DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[0] <= cp_data[0].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[1] <= cp_data[1].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[2] <= cp_data[2].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[3] <= cp_data[3].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[4] <= cp_data[4].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[5] <= cp_data[5].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[6] <= cp_data[6].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[7] <= cp_data[7].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[8] <= cp_data[8].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[9] <= cp_data[9].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[10] <= cp_data[10].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[11] <= cp_data[11].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[12] <= cp_data[12].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[13] <= cp_data[13].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[14] <= cp_data[14].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[15] <= cp_data[15].DB_MAX_OUTPUT_PORT_TYPE +m0_readdatavalid => rdata_fifo_src_valid.DATAIN +m0_debugaccess <= cp_data[74].DB_MAX_OUTPUT_PORT_TYPE +m0_lock <= m0_lock.DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[0] <= +rf_source_data[1] <= +rf_source_data[2] <= +rf_source_data[3] <= +rf_source_data[4] <= +rf_source_data[5] <= +rf_source_data[6] <= +rf_source_data[7] <= +rf_source_data[8] <= +rf_source_data[9] <= +rf_source_data[10] <= +rf_source_data[11] <= +rf_source_data[12] <= +rf_source_data[13] <= +rf_source_data[14] <= +rf_source_data[15] <= +rf_source_data[16] <= cp_data[16].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[17] <= cp_data[17].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[18] <= cp_data[18].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[19] <= cp_data[19].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[20] <= cp_data[20].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[21] <= cp_data[21].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[22] <= cp_data[22].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[23] <= cp_data[23].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[24] <= cp_data[24].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[25] <= cp_data[25].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[26] <= cp_data[26].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[27] <= cp_data[27].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[28] <= cp_data[28].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[29] <= cp_data[29].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[30] <= cp_data[30].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[31] <= cp_data[31].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[32] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[33] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[34] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[35] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[36] <= cp_data[36].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[37] <= cp_data[37].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[38] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[39] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[40] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[41] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[42] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[43] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[44] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[45] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[46] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[47] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[48] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[49] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[50] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[51] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[52] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[53] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[54] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[55] <= cp_data[55].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[56] <= cp_data[56].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[57] <= cp_data[57].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[58] <= cp_data[58].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[59] <= cp_data[59].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[60] <= cp_data[60].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[61] <= cp_data[61].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[62] <= cp_data[62].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[63] <= cp_data[63].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[64] <= cp_data[64].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[65] <= cp_data[65].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[66] <= cp_data[66].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[67] <= cp_data[67].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[68] <= cp_data[68].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[69] <= cp_data[69].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[70] <= cp_data[70].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[71] <= cp_data[71].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[72] <= cp_data[72].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[73] <= cp_data[73].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[74] <= cp_data[74].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[75] <= +rf_source_data[76] <= +rf_source_data[77] <= cp_data[77].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[78] <= cp_data[78].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[79] <= cp_data[79].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[80] <= cp_data[80].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[81] <= cp_data[81].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[82] <= cp_data[82].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[83] <= needs_response_synthesis.DB_MAX_OUTPUT_PORT_TYPE +rf_source_valid <= rf_source_valid.DB_MAX_OUTPUT_PORT_TYPE +rf_source_startofpacket <= cp_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +rf_source_endofpacket <= cp_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +rf_source_ready => cp_ready.IN1 +rf_source_ready => m0_read.IN1 +rf_source_ready => m0_write.IN1 +rf_source_ready => m0_lock.IN1 +rf_source_ready => rf_source_valid.IN1 +rf_sink_data[0] => ~NO_FANOUT~ +rf_sink_data[1] => ~NO_FANOUT~ +rf_sink_data[2] => ~NO_FANOUT~ +rf_sink_data[3] => ~NO_FANOUT~ +rf_sink_data[4] => ~NO_FANOUT~ +rf_sink_data[5] => ~NO_FANOUT~ +rf_sink_data[6] => ~NO_FANOUT~ +rf_sink_data[7] => ~NO_FANOUT~ +rf_sink_data[8] => ~NO_FANOUT~ +rf_sink_data[9] => ~NO_FANOUT~ +rf_sink_data[10] => ~NO_FANOUT~ +rf_sink_data[11] => ~NO_FANOUT~ +rf_sink_data[12] => ~NO_FANOUT~ +rf_sink_data[13] => ~NO_FANOUT~ +rf_sink_data[14] => ~NO_FANOUT~ +rf_sink_data[15] => ~NO_FANOUT~ +rf_sink_data[16] => rp_data[16].DATAIN +rf_sink_data[17] => rp_data[17].DATAIN +rf_sink_data[18] => rf_sink_addr[0].IN1 +rf_sink_data[19] => rf_sink_addr[1].IN1 +rf_sink_data[20] => rf_sink_addr[2].IN1 +rf_sink_data[21] => rf_sink_addr[3].IN1 +rf_sink_data[22] => rf_sink_addr[4].IN1 +rf_sink_data[23] => rf_sink_addr[5].IN1 +rf_sink_data[24] => rf_sink_addr[6].IN1 +rf_sink_data[25] => rf_sink_addr[7].IN1 +rf_sink_data[26] => rf_sink_addr[8].IN1 +rf_sink_data[27] => rf_sink_addr[9].IN1 +rf_sink_data[28] => rf_sink_addr[10].IN1 +rf_sink_data[29] => rf_sink_addr[11].IN1 +rf_sink_data[30] => rf_sink_addr[12].IN1 +rf_sink_data[31] => rf_sink_addr[13].IN1 +rf_sink_data[32] => rf_sink_addr[14].IN1 +rf_sink_data[33] => rf_sink_addr[15].IN1 +rf_sink_data[34] => rf_sink_addr[16].IN1 +rf_sink_data[35] => rf_sink_addr[17].IN1 +rf_sink_data[36] => rf_sink_addr[18].IN1 +rf_sink_data[37] => rf_sink_addr[19].IN1 +rf_sink_data[38] => rf_sink_addr[20].IN1 +rf_sink_data[39] => rf_sink_addr[21].IN1 +rf_sink_data[40] => rf_sink_addr[22].IN1 +rf_sink_data[41] => rf_sink_addr[23].IN1 +rf_sink_data[42] => rf_sink_addr[24].IN1 +rf_sink_data[43] => rf_sink_addr[25].IN1 +rf_sink_data[44] => rf_sink_compressed.IN1 +rf_sink_data[45] => rp_data[45].DATAIN +rf_sink_data[46] => comb.OUTPUTSELECT +rf_sink_data[46] => rp_data[46].DATAIN +rf_sink_data[47] => rp_data.IN0 +rf_sink_data[48] => rp_data[48].DATAIN +rf_sink_data[49] => rp_data[49].DATAIN +rf_sink_data[50] => rf_sink_byte_cnt[0].IN1 +rf_sink_data[51] => rf_sink_byte_cnt[1].IN1 +rf_sink_data[52] => rf_sink_byte_cnt[2].IN1 +rf_sink_data[53] => rf_sink_burstwrap[0].IN1 +rf_sink_data[54] => rf_sink_burstwrap[1].IN1 +rf_sink_data[55] => rf_sink_burstwrap[2].IN1 +rf_sink_data[56] => rf_sink_burstsize[0].IN1 +rf_sink_data[57] => rf_sink_burstsize[1].IN1 +rf_sink_data[58] => rf_sink_burstsize[2].IN1 +rf_sink_data[59] => rp_data[59].DATAIN +rf_sink_data[60] => rp_data[60].DATAIN +rf_sink_data[61] => rp_data[61].DATAIN +rf_sink_data[62] => rp_data[62].DATAIN +rf_sink_data[63] => rp_data[63].DATAIN +rf_sink_data[64] => rp_data[64].DATAIN +rf_sink_data[65] => rp_data[69].DATAIN +rf_sink_data[66] => rp_data[70].DATAIN +rf_sink_data[67] => rp_data[71].DATAIN +rf_sink_data[68] => rp_data[72].DATAIN +rf_sink_data[69] => rp_data[65].DATAIN +rf_sink_data[70] => rp_data[66].DATAIN +rf_sink_data[71] => rp_data[67].DATAIN +rf_sink_data[72] => rp_data[68].DATAIN +rf_sink_data[73] => rp_data[73].DATAIN +rf_sink_data[74] => rp_data[74].DATAIN +rf_sink_data[75] => rp_data[75].DATAIN +rf_sink_data[76] => rp_data[76].DATAIN +rf_sink_data[77] => rp_data[77].DATAIN +rf_sink_data[78] => rp_data[78].DATAIN +rf_sink_data[79] => rp_data[79].DATAIN +rf_sink_data[80] => rp_data[80].DATAIN +rf_sink_data[81] => ~NO_FANOUT~ +rf_sink_data[82] => ~NO_FANOUT~ +rf_sink_data[83] => rdata_fifo_sink_ready.IN0 +rf_sink_data[83] => comb.IN0 +rf_sink_valid => rdata_fifo_sink_ready.IN1 +rf_sink_valid => comb.IN1 +rf_sink_startofpacket => comb.DATAA +rf_sink_endofpacket => rf_sink_endofpacket.IN1 +rf_sink_ready <= altera_merlin_burst_uncompressor:uncompressor.sink_ready +rdata_fifo_src_data[0] <= m0_readdata[0].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[1] <= m0_readdata[1].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[2] <= m0_readdata[2].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[3] <= m0_readdata[3].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[4] <= m0_readdata[4].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[5] <= m0_readdata[5].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[6] <= m0_readdata[6].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[7] <= m0_readdata[7].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[8] <= m0_readdata[8].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[9] <= m0_readdata[9].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[10] <= m0_readdata[10].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[11] <= m0_readdata[11].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[12] <= m0_readdata[12].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[13] <= m0_readdata[13].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[14] <= m0_readdata[14].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[15] <= m0_readdata[15].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_valid <= m0_readdatavalid.DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_ready => ~NO_FANOUT~ +rdata_fifo_sink_data[0] => rp_data[0].DATAIN +rdata_fifo_sink_data[1] => rp_data[1].DATAIN +rdata_fifo_sink_data[2] => rp_data[2].DATAIN +rdata_fifo_sink_data[3] => rp_data[3].DATAIN +rdata_fifo_sink_data[4] => rp_data[4].DATAIN +rdata_fifo_sink_data[5] => rp_data[5].DATAIN +rdata_fifo_sink_data[6] => rp_data[6].DATAIN +rdata_fifo_sink_data[7] => rp_data[7].DATAIN +rdata_fifo_sink_data[8] => rp_data[8].DATAIN +rdata_fifo_sink_data[9] => rp_data[9].DATAIN +rdata_fifo_sink_data[10] => rp_data[10].DATAIN +rdata_fifo_sink_data[11] => rp_data[11].DATAIN +rdata_fifo_sink_data[12] => rp_data[12].DATAIN +rdata_fifo_sink_data[13] => rp_data[13].DATAIN +rdata_fifo_sink_data[14] => rp_data[14].DATAIN +rdata_fifo_sink_data[15] => rp_data[15].DATAIN +rdata_fifo_sink_valid => rp_valid.IN1 +rdata_fifo_sink_valid => rdata_fifo_sink_ready.IN0 +rdata_fifo_sink_valid => comb.IN1 +rdata_fifo_sink_ready <= rdata_fifo_sink_ready.DB_MAX_OUTPUT_PORT_TYPE +cp_ready <= cp_ready.DB_MAX_OUTPUT_PORT_TYPE +cp_valid => local_lock.IN0 +cp_valid => local_write.IN0 +cp_valid => local_read.IN0 +cp_valid => local_compressed_read.IN0 +cp_data[0] => m0_writedata[0].DATAIN +cp_data[1] => m0_writedata[1].DATAIN +cp_data[2] => m0_writedata[2].DATAIN +cp_data[3] => m0_writedata[3].DATAIN +cp_data[4] => m0_writedata[4].DATAIN +cp_data[5] => m0_writedata[5].DATAIN +cp_data[6] => m0_writedata[6].DATAIN +cp_data[7] => m0_writedata[7].DATAIN +cp_data[8] => m0_writedata[8].DATAIN +cp_data[9] => m0_writedata[9].DATAIN +cp_data[10] => m0_writedata[10].DATAIN +cp_data[11] => m0_writedata[11].DATAIN +cp_data[12] => m0_writedata[12].DATAIN +cp_data[13] => m0_writedata[13].DATAIN +cp_data[14] => m0_writedata[14].DATAIN +cp_data[15] => m0_writedata[15].DATAIN +cp_data[16] => WideOr0.IN0 +cp_data[16] => m0_byteenable[0].DATAIN +cp_data[16] => rf_source_data[16].DATAIN +cp_data[17] => WideOr0.IN1 +cp_data[17] => m0_byteenable[1].DATAIN +cp_data[17] => rf_source_data[17].DATAIN +cp_data[18] => rf_source_data[18].DATAIN +cp_data[19] => rf_source_data[19].DATAIN +cp_data[19] => m0_address[1].DATAIN +cp_data[20] => rf_source_data[20].DATAIN +cp_data[20] => m0_address[2].DATAIN +cp_data[21] => rf_source_data[21].DATAIN +cp_data[21] => m0_address[3].DATAIN +cp_data[22] => rf_source_data[22].DATAIN +cp_data[22] => m0_address[4].DATAIN +cp_data[23] => rf_source_data[23].DATAIN +cp_data[23] => m0_address[5].DATAIN +cp_data[24] => rf_source_data[24].DATAIN +cp_data[24] => m0_address[6].DATAIN +cp_data[25] => rf_source_data[25].DATAIN +cp_data[25] => m0_address[7].DATAIN +cp_data[26] => rf_source_data[26].DATAIN +cp_data[26] => m0_address[8].DATAIN +cp_data[27] => rf_source_data[27].DATAIN +cp_data[27] => m0_address[9].DATAIN +cp_data[28] => rf_source_data[28].DATAIN +cp_data[28] => m0_address[10].DATAIN +cp_data[29] => rf_source_data[29].DATAIN +cp_data[29] => m0_address[11].DATAIN +cp_data[30] => rf_source_data[30].DATAIN +cp_data[30] => m0_address[12].DATAIN +cp_data[31] => rf_source_data[31].DATAIN +cp_data[31] => m0_address[13].DATAIN +cp_data[32] => rf_source_data[32].DATAIN +cp_data[32] => m0_address[14].DATAIN +cp_data[33] => rf_source_data[33].DATAIN +cp_data[33] => m0_address[15].DATAIN +cp_data[34] => rf_source_data[34].DATAIN +cp_data[34] => m0_address[16].DATAIN +cp_data[35] => rf_source_data[35].DATAIN +cp_data[35] => m0_address[17].DATAIN +cp_data[36] => rf_source_data[36].DATAIN +cp_data[36] => m0_address[18].DATAIN +cp_data[37] => rf_source_data[37].DATAIN +cp_data[37] => m0_address[19].DATAIN +cp_data[38] => rf_source_data[38].DATAIN +cp_data[38] => m0_address[20].DATAIN +cp_data[39] => rf_source_data[39].DATAIN +cp_data[39] => m0_address[21].DATAIN +cp_data[40] => rf_source_data[40].DATAIN +cp_data[40] => m0_address[22].DATAIN +cp_data[41] => rf_source_data[41].DATAIN +cp_data[41] => m0_address[23].DATAIN +cp_data[42] => rf_source_data[42].DATAIN +cp_data[42] => m0_address[24].DATAIN +cp_data[43] => rf_source_data[43].DATAIN +cp_data[43] => m0_address[25].DATAIN +cp_data[44] => local_compressed_read.IN1 +cp_data[44] => rf_source_data[44].DATAIN +cp_data[45] => rf_source_data[45].DATAIN +cp_data[45] => comb.IN1 +cp_data[46] => local_write.IN1 +cp_data[46] => rf_source_data[46].DATAIN +cp_data[47] => local_read.IN1 +cp_data[47] => rf_source_data[47].DATAIN +cp_data[48] => local_lock.IN1 +cp_data[48] => rf_source_data[48].DATAIN +cp_data[49] => rf_source_data[49].DATAIN +cp_data[50] => m0_burstcount.DATAA +cp_data[50] => rf_source_data[50].DATAIN +cp_data[51] => m0_burstcount.DATAA +cp_data[51] => rf_source_data[51].DATAIN +cp_data[52] => rf_source_data[52].DATAIN +cp_data[53] => rf_source_data[53].DATAIN +cp_data[54] => rf_source_data[54].DATAIN +cp_data[55] => rf_source_data[55].DATAIN +cp_data[56] => rf_source_data[56].DATAIN +cp_data[57] => rf_source_data[57].DATAIN +cp_data[58] => rf_source_data[58].DATAIN +cp_data[59] => rf_source_data[59].DATAIN +cp_data[60] => rf_source_data[60].DATAIN +cp_data[61] => rf_source_data[61].DATAIN +cp_data[62] => rf_source_data[62].DATAIN +cp_data[63] => rf_source_data[63].DATAIN +cp_data[64] => rf_source_data[64].DATAIN +cp_data[65] => rf_source_data[65].DATAIN +cp_data[66] => rf_source_data[66].DATAIN +cp_data[67] => rf_source_data[67].DATAIN +cp_data[68] => rf_source_data[68].DATAIN +cp_data[69] => rf_source_data[69].DATAIN +cp_data[70] => rf_source_data[70].DATAIN +cp_data[71] => rf_source_data[71].DATAIN +cp_data[72] => rf_source_data[72].DATAIN +cp_data[73] => rf_source_data[73].DATAIN +cp_data[74] => rf_source_data[74].DATAIN +cp_data[74] => m0_debugaccess.DATAIN +cp_data[75] => ~NO_FANOUT~ +cp_data[76] => ~NO_FANOUT~ +cp_data[77] => rf_source_data[77].DATAIN +cp_data[78] => rf_source_data[78].DATAIN +cp_data[79] => rf_source_data[79].DATAIN +cp_data[80] => rf_source_data[80].DATAIN +cp_data[81] => rf_source_data[81].DATAIN +cp_data[82] => rf_source_data[82].DATAIN +cp_channel[0] => ~NO_FANOUT~ +cp_channel[1] => ~NO_FANOUT~ +cp_channel[2] => ~NO_FANOUT~ +cp_channel[3] => ~NO_FANOUT~ +cp_channel[4] => ~NO_FANOUT~ +cp_channel[5] => ~NO_FANOUT~ +cp_channel[6] => ~NO_FANOUT~ +cp_channel[7] => ~NO_FANOUT~ +cp_channel[8] => ~NO_FANOUT~ +cp_channel[9] => ~NO_FANOUT~ +cp_channel[10] => ~NO_FANOUT~ +cp_startofpacket => rf_source_startofpacket.DATAIN +cp_endofpacket => nonposted_write_endofpacket.IN1 +cp_endofpacket => rf_source_endofpacket.DATAIN +rp_ready => rp_ready.IN1 +rp_valid <= rp_valid.DB_MAX_OUTPUT_PORT_TYPE +rp_data[0] <= rdata_fifo_sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +rp_data[1] <= rdata_fifo_sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +rp_data[2] <= rdata_fifo_sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +rp_data[3] <= rdata_fifo_sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +rp_data[4] <= rdata_fifo_sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +rp_data[5] <= rdata_fifo_sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +rp_data[6] <= rdata_fifo_sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +rp_data[7] <= rdata_fifo_sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +rp_data[8] <= rdata_fifo_sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +rp_data[9] <= rdata_fifo_sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +rp_data[10] <= rdata_fifo_sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +rp_data[11] <= rdata_fifo_sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +rp_data[12] <= rdata_fifo_sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +rp_data[13] <= rdata_fifo_sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +rp_data[14] <= rdata_fifo_sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +rp_data[15] <= rdata_fifo_sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +rp_data[16] <= rf_sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +rp_data[17] <= rf_sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +rp_data[18] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[19] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[20] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[21] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[22] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[23] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[24] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[25] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[26] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[27] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[28] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[29] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[30] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[31] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[32] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[33] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[34] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[35] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[36] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[37] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[38] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[39] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[40] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[41] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[42] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[43] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[44] <= altera_merlin_burst_uncompressor:uncompressor.source_is_compressed +rp_data[45] <= rf_sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +rp_data[46] <= rf_sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +rp_data[47] <= rp_data.DB_MAX_OUTPUT_PORT_TYPE +rp_data[48] <= rf_sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +rp_data[49] <= rf_sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +rp_data[50] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt +rp_data[51] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt +rp_data[52] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt +rp_data[53] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap +rp_data[54] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap +rp_data[55] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap +rp_data[56] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize +rp_data[57] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize +rp_data[58] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize +rp_data[59] <= rf_sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +rp_data[60] <= rf_sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +rp_data[61] <= rf_sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +rp_data[62] <= rf_sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +rp_data[63] <= rf_sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +rp_data[64] <= rf_sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +rp_data[65] <= rf_sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +rp_data[66] <= rf_sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +rp_data[67] <= rf_sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +rp_data[68] <= rf_sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +rp_data[69] <= rf_sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +rp_data[70] <= rf_sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +rp_data[71] <= rf_sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +rp_data[72] <= rf_sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +rp_data[73] <= rf_sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +rp_data[74] <= rf_sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +rp_data[75] <= rf_sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +rp_data[76] <= rf_sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +rp_data[77] <= rf_sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +rp_data[78] <= rf_sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +rp_data[79] <= rf_sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +rp_data[80] <= rf_sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +rp_data[81] <= +rp_data[82] <= +rp_startofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_startofpacket +rp_endofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_endofpacket + + +|de0_nano_system|system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor +clk => burst_uncompress_address_offset[0].CLK +clk => burst_uncompress_address_offset[1].CLK +clk => burst_uncompress_address_offset[2].CLK +clk => burst_uncompress_address_offset[3].CLK +clk => burst_uncompress_address_offset[4].CLK +clk => burst_uncompress_address_offset[5].CLK +clk => burst_uncompress_address_offset[6].CLK +clk => burst_uncompress_address_offset[7].CLK +clk => burst_uncompress_address_offset[8].CLK +clk => burst_uncompress_address_offset[9].CLK +clk => burst_uncompress_address_offset[10].CLK +clk => burst_uncompress_address_offset[11].CLK +clk => burst_uncompress_address_offset[12].CLK +clk => burst_uncompress_address_offset[13].CLK +clk => burst_uncompress_address_offset[14].CLK +clk => burst_uncompress_address_offset[15].CLK +clk => burst_uncompress_address_offset[16].CLK +clk => burst_uncompress_address_offset[17].CLK +clk => burst_uncompress_address_offset[18].CLK +clk => burst_uncompress_address_offset[19].CLK +clk => burst_uncompress_address_offset[20].CLK +clk => burst_uncompress_address_offset[21].CLK +clk => burst_uncompress_address_offset[22].CLK +clk => burst_uncompress_address_offset[23].CLK +clk => burst_uncompress_address_offset[24].CLK +clk => burst_uncompress_address_offset[25].CLK +clk => burst_uncompress_address_base[0].CLK +clk => burst_uncompress_address_base[1].CLK +clk => burst_uncompress_address_base[2].CLK +clk => burst_uncompress_address_base[3].CLK +clk => burst_uncompress_address_base[4].CLK +clk => burst_uncompress_address_base[5].CLK +clk => burst_uncompress_address_base[6].CLK +clk => burst_uncompress_address_base[7].CLK +clk => burst_uncompress_address_base[8].CLK +clk => burst_uncompress_address_base[9].CLK +clk => burst_uncompress_address_base[10].CLK +clk => burst_uncompress_address_base[11].CLK +clk => burst_uncompress_address_base[12].CLK +clk => burst_uncompress_address_base[13].CLK +clk => burst_uncompress_address_base[14].CLK +clk => burst_uncompress_address_base[15].CLK +clk => burst_uncompress_address_base[16].CLK +clk => burst_uncompress_address_base[17].CLK +clk => burst_uncompress_address_base[18].CLK +clk => burst_uncompress_address_base[19].CLK +clk => burst_uncompress_address_base[20].CLK +clk => burst_uncompress_address_base[21].CLK +clk => burst_uncompress_address_base[22].CLK +clk => burst_uncompress_address_base[23].CLK +clk => burst_uncompress_address_base[24].CLK +clk => burst_uncompress_address_base[25].CLK +clk => burst_uncompress_byte_counter[0].CLK +clk => burst_uncompress_byte_counter[1].CLK +clk => burst_uncompress_byte_counter[2].CLK +clk => burst_uncompress_busy.CLK +reset => burst_uncompress_address_offset[0].ACLR +reset => burst_uncompress_address_offset[1].ACLR +reset => burst_uncompress_address_offset[2].ACLR +reset => burst_uncompress_address_offset[3].ACLR +reset => burst_uncompress_address_offset[4].ACLR +reset => burst_uncompress_address_offset[5].ACLR +reset => burst_uncompress_address_offset[6].ACLR +reset => burst_uncompress_address_offset[7].ACLR +reset => burst_uncompress_address_offset[8].ACLR +reset => burst_uncompress_address_offset[9].ACLR +reset => burst_uncompress_address_offset[10].ACLR +reset => burst_uncompress_address_offset[11].ACLR +reset => burst_uncompress_address_offset[12].ACLR +reset => burst_uncompress_address_offset[13].ACLR +reset => burst_uncompress_address_offset[14].ACLR +reset => burst_uncompress_address_offset[15].ACLR +reset => burst_uncompress_address_offset[16].ACLR +reset => burst_uncompress_address_offset[17].ACLR +reset => burst_uncompress_address_offset[18].ACLR +reset => burst_uncompress_address_offset[19].ACLR +reset => burst_uncompress_address_offset[20].ACLR +reset => burst_uncompress_address_offset[21].ACLR +reset => burst_uncompress_address_offset[22].ACLR +reset => burst_uncompress_address_offset[23].ACLR +reset => burst_uncompress_address_offset[24].ACLR +reset => burst_uncompress_address_offset[25].ACLR +reset => burst_uncompress_address_base[0].ACLR +reset => burst_uncompress_address_base[1].ACLR +reset => burst_uncompress_address_base[2].ACLR +reset => burst_uncompress_address_base[3].ACLR +reset => burst_uncompress_address_base[4].ACLR +reset => burst_uncompress_address_base[5].ACLR +reset => burst_uncompress_address_base[6].ACLR +reset => burst_uncompress_address_base[7].ACLR +reset => burst_uncompress_address_base[8].ACLR +reset => burst_uncompress_address_base[9].ACLR +reset => burst_uncompress_address_base[10].ACLR +reset => burst_uncompress_address_base[11].ACLR +reset => burst_uncompress_address_base[12].ACLR +reset => burst_uncompress_address_base[13].ACLR +reset => burst_uncompress_address_base[14].ACLR +reset => burst_uncompress_address_base[15].ACLR +reset => burst_uncompress_address_base[16].ACLR +reset => burst_uncompress_address_base[17].ACLR +reset => burst_uncompress_address_base[18].ACLR +reset => burst_uncompress_address_base[19].ACLR +reset => burst_uncompress_address_base[20].ACLR +reset => burst_uncompress_address_base[21].ACLR +reset => burst_uncompress_address_base[22].ACLR +reset => burst_uncompress_address_base[23].ACLR +reset => burst_uncompress_address_base[24].ACLR +reset => burst_uncompress_address_base[25].ACLR +reset => burst_uncompress_byte_counter[0].ACLR +reset => burst_uncompress_byte_counter[1].ACLR +reset => burst_uncompress_byte_counter[2].ACLR +reset => burst_uncompress_busy.ACLR +sink_startofpacket => source_startofpacket.IN1 +sink_endofpacket => source_endofpacket.IN1 +sink_valid => first_packet_beat.IN1 +sink_valid => last_packet_beat.IN1 +sink_valid => last_packet_beat.IN1 +sink_valid => always0.IN1 +sink_valid => sink_ready.IN0 +sink_valid => source_valid.DATAIN +sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE +sink_addr[0] => burst_uncompress_address_base.IN0 +sink_addr[0] => comb.DATAB +sink_addr[0] => source_addr.DATAB +sink_addr[1] => burst_uncompress_address_base.IN0 +sink_addr[1] => comb.DATAB +sink_addr[1] => source_addr.DATAB +sink_addr[2] => burst_uncompress_address_base.IN0 +sink_addr[2] => comb.DATAB +sink_addr[2] => source_addr.DATAB +sink_addr[3] => burst_uncompress_address_base.IN0 +sink_addr[3] => comb.DATAB +sink_addr[3] => source_addr.DATAB +sink_addr[4] => burst_uncompress_address_base.IN0 +sink_addr[4] => comb.DATAB +sink_addr[4] => source_addr.DATAB +sink_addr[5] => burst_uncompress_address_base.IN0 +sink_addr[5] => comb.DATAB +sink_addr[5] => source_addr.DATAB +sink_addr[6] => burst_uncompress_address_base.IN0 +sink_addr[6] => comb.DATAB +sink_addr[6] => source_addr.DATAB +sink_addr[7] => burst_uncompress_address_base.IN0 +sink_addr[7] => comb.DATAB +sink_addr[7] => source_addr.DATAB +sink_addr[8] => burst_uncompress_address_base.IN0 +sink_addr[8] => comb.DATAB +sink_addr[8] => source_addr.DATAB +sink_addr[9] => burst_uncompress_address_base.IN0 +sink_addr[9] => comb.DATAB +sink_addr[9] => source_addr.DATAB +sink_addr[10] => burst_uncompress_address_base.IN0 +sink_addr[10] => comb.DATAB +sink_addr[10] => source_addr.DATAB +sink_addr[11] => burst_uncompress_address_base.IN0 +sink_addr[11] => comb.DATAB +sink_addr[11] => source_addr.DATAB +sink_addr[12] => burst_uncompress_address_base.IN0 +sink_addr[12] => comb.DATAB +sink_addr[12] => source_addr.DATAB +sink_addr[13] => burst_uncompress_address_base.IN0 +sink_addr[13] => comb.DATAB +sink_addr[13] => source_addr.DATAB +sink_addr[14] => burst_uncompress_address_base.IN0 +sink_addr[14] => comb.DATAB +sink_addr[14] => source_addr.DATAB +sink_addr[15] => burst_uncompress_address_base.IN0 +sink_addr[15] => comb.DATAB +sink_addr[15] => source_addr.DATAB +sink_addr[16] => burst_uncompress_address_base.IN0 +sink_addr[16] => comb.DATAB +sink_addr[16] => source_addr.DATAB +sink_addr[17] => burst_uncompress_address_base.IN0 +sink_addr[17] => comb.DATAB +sink_addr[17] => source_addr.DATAB +sink_addr[18] => burst_uncompress_address_base.IN0 +sink_addr[18] => comb.DATAB +sink_addr[18] => source_addr.DATAB +sink_addr[19] => burst_uncompress_address_base.IN0 +sink_addr[19] => comb.DATAB +sink_addr[19] => source_addr.DATAB +sink_addr[20] => burst_uncompress_address_base.IN0 +sink_addr[20] => comb.DATAB +sink_addr[20] => source_addr.DATAB +sink_addr[21] => burst_uncompress_address_base.IN0 +sink_addr[21] => comb.DATAB +sink_addr[21] => source_addr.DATAB +sink_addr[22] => burst_uncompress_address_base.IN0 +sink_addr[22] => comb.DATAB +sink_addr[22] => source_addr.DATAB +sink_addr[23] => burst_uncompress_address_base.IN0 +sink_addr[23] => comb.DATAB +sink_addr[23] => source_addr.DATAB +sink_addr[24] => burst_uncompress_address_base.IN0 +sink_addr[24] => comb.DATAB +sink_addr[24] => source_addr.DATAB +sink_addr[25] => burst_uncompress_address_base.IN0 +sink_addr[25] => comb.DATAB +sink_addr[25] => source_addr.DATAB +sink_burstwrap[0] => p1_burst_uncompress_address_offset[0].IN1 +sink_burstwrap[0] => source_burstwrap[0].DATAIN +sink_burstwrap[0] => burst_uncompress_address_base.IN1 +sink_burstwrap[1] => p1_burst_uncompress_address_offset[1].IN1 +sink_burstwrap[1] => source_burstwrap[1].DATAIN +sink_burstwrap[1] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[2].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[25].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[24].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[23].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[22].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[21].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[20].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[19].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[18].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[17].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[16].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[15].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[14].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[13].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[12].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[11].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[10].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[9].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[8].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[7].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[6].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[5].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[4].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[3].IN1 +sink_burstwrap[2] => source_burstwrap[2].DATAIN +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_byte_cnt[0] => source_byte_cnt.DATAB +sink_byte_cnt[0] => Add1.IN6 +sink_byte_cnt[0] => Equal1.IN1 +sink_byte_cnt[1] => source_byte_cnt.DATAB +sink_byte_cnt[1] => Add1.IN5 +sink_byte_cnt[1] => Equal1.IN2 +sink_byte_cnt[2] => source_byte_cnt.DATAB +sink_byte_cnt[2] => Add1.IN4 +sink_byte_cnt[2] => Equal1.IN0 +sink_is_compressed => last_packet_beat.IN1 +sink_burstsize[0] => Decoder0.IN2 +sink_burstsize[0] => source_burstsize[0].DATAIN +sink_burstsize[1] => Decoder0.IN1 +sink_burstsize[1] => source_burstsize[1].DATAIN +sink_burstsize[2] => Decoder0.IN0 +sink_burstsize[2] => source_burstsize[2].DATAIN +source_startofpacket <= source_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +source_endofpacket <= source_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +source_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE +source_ready => always1.IN1 +source_ready => sink_ready.IN1 +source_addr[0] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[1] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[2] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[3] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[4] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[5] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[6] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[7] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[8] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[9] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[10] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[11] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[12] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[13] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[14] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[15] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[16] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[17] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[18] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[19] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[20] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[21] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[22] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[23] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[24] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[25] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_burstwrap[0] <= sink_burstwrap[0].DB_MAX_OUTPUT_PORT_TYPE +source_burstwrap[1] <= sink_burstwrap[1].DB_MAX_OUTPUT_PORT_TYPE +source_burstwrap[2] <= sink_burstwrap[2].DB_MAX_OUTPUT_PORT_TYPE +source_byte_cnt[0] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE +source_byte_cnt[1] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE +source_byte_cnt[2] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE +source_is_compressed <= +source_burstsize[0] <= sink_burstsize[0].DB_MAX_OUTPUT_PORT_TYPE +source_burstsize[1] <= sink_burstsize[1].DB_MAX_OUTPUT_PORT_TYPE +source_burstsize[2] <= sink_burstsize[2].DB_MAX_OUTPUT_PORT_TYPE + + +|de0_nano_system|system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo +clk => csr_readdata[0]~reg0.CLK +clk => csr_readdata[1]~reg0.CLK +clk => csr_readdata[2]~reg0.CLK +clk => csr_readdata[3]~reg0.CLK +clk => csr_readdata[4]~reg0.CLK +clk => csr_readdata[5]~reg0.CLK +clk => csr_readdata[6]~reg0.CLK +clk => csr_readdata[7]~reg0.CLK +clk => csr_readdata[8]~reg0.CLK +clk => csr_readdata[9]~reg0.CLK +clk => csr_readdata[10]~reg0.CLK +clk => csr_readdata[11]~reg0.CLK +clk => csr_readdata[12]~reg0.CLK +clk => csr_readdata[13]~reg0.CLK +clk => csr_readdata[14]~reg0.CLK +clk => csr_readdata[15]~reg0.CLK +clk => csr_readdata[16]~reg0.CLK +clk => csr_readdata[17]~reg0.CLK +clk => csr_readdata[18]~reg0.CLK +clk => csr_readdata[19]~reg0.CLK +clk => csr_readdata[20]~reg0.CLK +clk => csr_readdata[21]~reg0.CLK +clk => csr_readdata[22]~reg0.CLK +clk => csr_readdata[23]~reg0.CLK +clk => csr_readdata[24]~reg0.CLK +clk => csr_readdata[25]~reg0.CLK +clk => csr_readdata[26]~reg0.CLK +clk => csr_readdata[27]~reg0.CLK +clk => csr_readdata[28]~reg0.CLK +clk => csr_readdata[29]~reg0.CLK +clk => csr_readdata[30]~reg0.CLK +clk => csr_readdata[31]~reg0.CLK +clk => mem_used[6].CLK +clk => mem_used[5].CLK +clk => mem_used[4].CLK +clk => mem_used[3].CLK +clk => mem_used[2].CLK +clk => mem_used[1].CLK +clk => mem_used[7].CLK +clk => mem_used[0].CLK +clk => mem[7][0].CLK +clk => mem[7][1].CLK +clk => mem[7][2].CLK +clk => mem[7][3].CLK +clk => mem[7][4].CLK +clk => mem[7][5].CLK +clk => mem[7][6].CLK +clk => mem[7][7].CLK +clk => mem[7][8].CLK +clk => mem[7][9].CLK +clk => mem[7][10].CLK +clk => mem[7][11].CLK +clk => mem[7][12].CLK +clk => mem[7][13].CLK +clk => mem[7][14].CLK +clk => mem[7][15].CLK +clk => mem[7][16].CLK +clk => mem[7][17].CLK +clk => mem[7][18].CLK +clk => mem[7][19].CLK +clk => mem[7][20].CLK +clk => mem[7][21].CLK +clk => mem[7][22].CLK +clk => mem[7][23].CLK +clk => mem[7][24].CLK +clk => mem[7][25].CLK +clk => mem[7][26].CLK +clk => mem[7][27].CLK +clk => mem[7][28].CLK +clk => mem[7][29].CLK +clk => mem[7][30].CLK +clk => mem[7][31].CLK +clk => mem[7][32].CLK +clk => mem[7][33].CLK +clk => mem[7][34].CLK +clk => mem[7][35].CLK +clk => mem[7][36].CLK +clk => mem[7][37].CLK +clk => mem[7][38].CLK +clk => mem[7][39].CLK +clk => mem[7][40].CLK +clk => mem[7][41].CLK +clk => mem[7][42].CLK +clk => mem[7][43].CLK +clk => mem[7][44].CLK +clk => mem[7][45].CLK +clk => mem[7][46].CLK +clk => mem[7][47].CLK +clk => mem[7][48].CLK +clk => mem[7][49].CLK +clk => mem[7][50].CLK +clk => mem[7][51].CLK +clk => mem[7][52].CLK +clk => mem[7][53].CLK +clk => mem[7][54].CLK +clk => mem[7][55].CLK +clk => mem[7][56].CLK +clk => mem[7][57].CLK +clk => mem[7][58].CLK +clk => mem[7][59].CLK +clk => mem[7][60].CLK +clk => mem[7][61].CLK +clk => mem[7][62].CLK +clk => mem[7][63].CLK +clk => mem[7][64].CLK +clk => mem[7][65].CLK +clk => mem[7][66].CLK +clk => mem[7][67].CLK +clk => mem[7][68].CLK +clk => mem[7][69].CLK +clk => mem[7][70].CLK +clk => mem[7][71].CLK +clk => mem[7][72].CLK +clk => mem[7][73].CLK +clk => mem[7][74].CLK +clk => mem[7][75].CLK +clk => mem[7][76].CLK +clk => mem[7][77].CLK +clk => mem[7][78].CLK +clk => mem[7][79].CLK +clk => mem[7][80].CLK +clk => mem[7][81].CLK +clk => mem[7][82].CLK +clk => mem[7][83].CLK +clk => mem[7][84].CLK +clk => mem[7][85].CLK +clk => mem[6][0].CLK +clk => mem[6][1].CLK +clk => mem[6][2].CLK +clk => mem[6][3].CLK +clk => mem[6][4].CLK +clk => mem[6][5].CLK +clk => mem[6][6].CLK +clk => mem[6][7].CLK +clk => mem[6][8].CLK +clk => mem[6][9].CLK +clk => mem[6][10].CLK +clk => mem[6][11].CLK +clk => mem[6][12].CLK +clk => mem[6][13].CLK +clk => mem[6][14].CLK +clk => mem[6][15].CLK +clk => mem[6][16].CLK +clk => mem[6][17].CLK +clk => mem[6][18].CLK +clk => mem[6][19].CLK +clk => mem[6][20].CLK +clk => mem[6][21].CLK +clk => mem[6][22].CLK +clk => mem[6][23].CLK +clk => mem[6][24].CLK +clk => mem[6][25].CLK +clk => mem[6][26].CLK +clk => mem[6][27].CLK +clk => mem[6][28].CLK +clk => mem[6][29].CLK +clk => mem[6][30].CLK +clk => mem[6][31].CLK +clk => mem[6][32].CLK +clk => mem[6][33].CLK +clk => mem[6][34].CLK +clk => mem[6][35].CLK +clk => mem[6][36].CLK +clk => mem[6][37].CLK +clk => mem[6][38].CLK +clk => mem[6][39].CLK +clk => mem[6][40].CLK +clk => mem[6][41].CLK +clk => mem[6][42].CLK +clk => mem[6][43].CLK +clk => mem[6][44].CLK +clk => mem[6][45].CLK +clk => mem[6][46].CLK +clk => mem[6][47].CLK +clk => mem[6][48].CLK +clk => mem[6][49].CLK +clk => mem[6][50].CLK +clk => mem[6][51].CLK +clk => mem[6][52].CLK +clk => mem[6][53].CLK +clk => mem[6][54].CLK +clk => mem[6][55].CLK +clk => mem[6][56].CLK +clk => mem[6][57].CLK +clk => mem[6][58].CLK +clk => mem[6][59].CLK +clk => mem[6][60].CLK +clk => mem[6][61].CLK +clk => mem[6][62].CLK +clk => mem[6][63].CLK +clk => mem[6][64].CLK +clk => mem[6][65].CLK +clk => mem[6][66].CLK +clk => mem[6][67].CLK +clk => mem[6][68].CLK +clk => mem[6][69].CLK +clk => mem[6][70].CLK +clk => mem[6][71].CLK +clk => mem[6][72].CLK +clk => mem[6][73].CLK +clk => mem[6][74].CLK +clk => mem[6][75].CLK +clk => mem[6][76].CLK +clk => mem[6][77].CLK +clk => mem[6][78].CLK +clk => mem[6][79].CLK +clk => mem[6][80].CLK +clk => mem[6][81].CLK +clk => mem[6][82].CLK +clk => mem[6][83].CLK +clk => mem[6][84].CLK +clk => mem[6][85].CLK +clk => mem[5][0].CLK +clk => mem[5][1].CLK +clk => mem[5][2].CLK +clk => mem[5][3].CLK +clk => mem[5][4].CLK +clk => mem[5][5].CLK +clk => mem[5][6].CLK +clk => mem[5][7].CLK +clk => mem[5][8].CLK +clk => mem[5][9].CLK +clk => mem[5][10].CLK +clk => mem[5][11].CLK +clk => mem[5][12].CLK +clk => mem[5][13].CLK +clk => mem[5][14].CLK +clk => mem[5][15].CLK +clk => mem[5][16].CLK +clk => mem[5][17].CLK +clk => mem[5][18].CLK +clk => mem[5][19].CLK +clk => mem[5][20].CLK +clk => mem[5][21].CLK +clk => mem[5][22].CLK +clk => mem[5][23].CLK +clk => mem[5][24].CLK +clk => mem[5][25].CLK +clk => mem[5][26].CLK +clk => mem[5][27].CLK +clk => mem[5][28].CLK +clk => mem[5][29].CLK +clk => mem[5][30].CLK +clk => mem[5][31].CLK +clk => mem[5][32].CLK +clk => mem[5][33].CLK +clk => mem[5][34].CLK +clk => mem[5][35].CLK +clk => mem[5][36].CLK +clk => mem[5][37].CLK +clk => mem[5][38].CLK +clk => mem[5][39].CLK +clk => mem[5][40].CLK +clk => mem[5][41].CLK +clk => mem[5][42].CLK +clk => mem[5][43].CLK +clk => mem[5][44].CLK +clk => mem[5][45].CLK +clk => mem[5][46].CLK +clk => mem[5][47].CLK +clk => mem[5][48].CLK +clk => mem[5][49].CLK +clk => mem[5][50].CLK +clk => mem[5][51].CLK +clk => mem[5][52].CLK +clk => mem[5][53].CLK +clk => mem[5][54].CLK +clk => mem[5][55].CLK +clk => mem[5][56].CLK +clk => mem[5][57].CLK +clk => mem[5][58].CLK +clk => mem[5][59].CLK +clk => mem[5][60].CLK +clk => mem[5][61].CLK +clk => mem[5][62].CLK +clk => mem[5][63].CLK +clk => mem[5][64].CLK +clk => mem[5][65].CLK +clk => mem[5][66].CLK +clk => mem[5][67].CLK +clk => mem[5][68].CLK +clk => mem[5][69].CLK +clk => mem[5][70].CLK +clk => mem[5][71].CLK +clk => mem[5][72].CLK +clk => mem[5][73].CLK +clk => mem[5][74].CLK +clk => mem[5][75].CLK +clk => mem[5][76].CLK +clk => mem[5][77].CLK +clk => mem[5][78].CLK +clk => mem[5][79].CLK +clk => mem[5][80].CLK +clk => mem[5][81].CLK +clk => mem[5][82].CLK +clk => mem[5][83].CLK +clk => mem[5][84].CLK +clk => mem[5][85].CLK +clk => mem[4][0].CLK +clk => mem[4][1].CLK +clk => mem[4][2].CLK +clk => mem[4][3].CLK +clk => mem[4][4].CLK +clk => mem[4][5].CLK +clk => mem[4][6].CLK +clk => mem[4][7].CLK +clk => mem[4][8].CLK +clk => mem[4][9].CLK +clk => mem[4][10].CLK +clk => mem[4][11].CLK +clk => mem[4][12].CLK +clk => mem[4][13].CLK +clk => mem[4][14].CLK +clk => mem[4][15].CLK +clk => mem[4][16].CLK +clk => mem[4][17].CLK +clk => mem[4][18].CLK +clk => mem[4][19].CLK +clk => mem[4][20].CLK +clk => mem[4][21].CLK +clk => mem[4][22].CLK +clk => mem[4][23].CLK +clk => mem[4][24].CLK +clk => mem[4][25].CLK +clk => mem[4][26].CLK +clk => mem[4][27].CLK +clk => mem[4][28].CLK +clk => mem[4][29].CLK +clk => mem[4][30].CLK +clk => mem[4][31].CLK +clk => mem[4][32].CLK +clk => mem[4][33].CLK +clk => mem[4][34].CLK +clk => mem[4][35].CLK +clk => mem[4][36].CLK +clk => mem[4][37].CLK +clk => mem[4][38].CLK +clk => mem[4][39].CLK +clk => mem[4][40].CLK +clk => mem[4][41].CLK +clk => mem[4][42].CLK +clk => mem[4][43].CLK +clk => mem[4][44].CLK +clk => mem[4][45].CLK +clk => mem[4][46].CLK +clk => mem[4][47].CLK +clk => mem[4][48].CLK +clk => mem[4][49].CLK +clk => mem[4][50].CLK +clk => mem[4][51].CLK +clk => mem[4][52].CLK +clk => mem[4][53].CLK +clk => mem[4][54].CLK +clk => mem[4][55].CLK +clk => mem[4][56].CLK +clk => mem[4][57].CLK +clk => mem[4][58].CLK +clk => mem[4][59].CLK +clk => mem[4][60].CLK +clk => mem[4][61].CLK +clk => mem[4][62].CLK +clk => mem[4][63].CLK +clk => mem[4][64].CLK +clk => mem[4][65].CLK +clk => mem[4][66].CLK +clk => mem[4][67].CLK +clk => mem[4][68].CLK +clk => mem[4][69].CLK +clk => mem[4][70].CLK +clk => mem[4][71].CLK +clk => mem[4][72].CLK +clk => mem[4][73].CLK +clk => mem[4][74].CLK +clk => mem[4][75].CLK +clk => mem[4][76].CLK +clk => mem[4][77].CLK +clk => mem[4][78].CLK +clk => mem[4][79].CLK +clk => mem[4][80].CLK +clk => mem[4][81].CLK +clk => mem[4][82].CLK +clk => mem[4][83].CLK +clk => mem[4][84].CLK +clk => mem[4][85].CLK +clk => mem[3][0].CLK +clk => mem[3][1].CLK +clk => mem[3][2].CLK +clk => mem[3][3].CLK +clk => mem[3][4].CLK +clk => mem[3][5].CLK +clk => mem[3][6].CLK +clk => mem[3][7].CLK +clk => mem[3][8].CLK +clk => mem[3][9].CLK +clk => mem[3][10].CLK +clk => mem[3][11].CLK +clk => mem[3][12].CLK +clk => mem[3][13].CLK +clk => mem[3][14].CLK +clk => mem[3][15].CLK +clk => mem[3][16].CLK +clk => mem[3][17].CLK +clk => mem[3][18].CLK +clk => mem[3][19].CLK +clk => mem[3][20].CLK +clk => mem[3][21].CLK +clk => mem[3][22].CLK +clk => mem[3][23].CLK +clk => mem[3][24].CLK +clk => mem[3][25].CLK +clk => mem[3][26].CLK +clk => mem[3][27].CLK +clk => mem[3][28].CLK +clk => mem[3][29].CLK +clk => mem[3][30].CLK +clk => mem[3][31].CLK +clk => mem[3][32].CLK +clk => mem[3][33].CLK +clk => mem[3][34].CLK +clk => mem[3][35].CLK +clk => mem[3][36].CLK +clk => mem[3][37].CLK +clk => mem[3][38].CLK +clk => mem[3][39].CLK +clk => mem[3][40].CLK +clk => mem[3][41].CLK +clk => mem[3][42].CLK +clk => mem[3][43].CLK +clk => mem[3][44].CLK +clk => mem[3][45].CLK +clk => mem[3][46].CLK +clk => mem[3][47].CLK +clk => mem[3][48].CLK +clk => mem[3][49].CLK +clk => mem[3][50].CLK +clk => mem[3][51].CLK +clk => mem[3][52].CLK +clk => mem[3][53].CLK +clk => mem[3][54].CLK +clk => mem[3][55].CLK +clk => mem[3][56].CLK +clk => mem[3][57].CLK +clk => mem[3][58].CLK +clk => mem[3][59].CLK +clk => mem[3][60].CLK +clk => mem[3][61].CLK +clk => mem[3][62].CLK +clk => mem[3][63].CLK +clk => mem[3][64].CLK +clk => mem[3][65].CLK +clk => mem[3][66].CLK +clk => mem[3][67].CLK +clk => mem[3][68].CLK +clk => mem[3][69].CLK +clk => mem[3][70].CLK +clk => mem[3][71].CLK +clk => mem[3][72].CLK +clk => mem[3][73].CLK +clk => mem[3][74].CLK +clk => mem[3][75].CLK +clk => mem[3][76].CLK +clk => mem[3][77].CLK +clk => mem[3][78].CLK +clk => mem[3][79].CLK +clk => mem[3][80].CLK +clk => mem[3][81].CLK +clk => mem[3][82].CLK +clk => mem[3][83].CLK +clk => mem[3][84].CLK +clk => mem[3][85].CLK +clk => mem[2][0].CLK +clk => mem[2][1].CLK +clk => mem[2][2].CLK +clk => mem[2][3].CLK +clk => mem[2][4].CLK +clk => mem[2][5].CLK +clk => mem[2][6].CLK +clk => mem[2][7].CLK +clk => mem[2][8].CLK +clk => mem[2][9].CLK +clk => mem[2][10].CLK +clk => mem[2][11].CLK +clk => mem[2][12].CLK +clk => mem[2][13].CLK +clk => mem[2][14].CLK +clk => mem[2][15].CLK +clk => mem[2][16].CLK +clk => mem[2][17].CLK +clk => mem[2][18].CLK +clk => mem[2][19].CLK +clk => mem[2][20].CLK +clk => mem[2][21].CLK +clk => mem[2][22].CLK +clk => mem[2][23].CLK +clk => mem[2][24].CLK +clk => mem[2][25].CLK +clk => mem[2][26].CLK +clk => mem[2][27].CLK +clk => mem[2][28].CLK +clk => mem[2][29].CLK +clk => mem[2][30].CLK +clk => mem[2][31].CLK +clk => mem[2][32].CLK +clk => mem[2][33].CLK +clk => mem[2][34].CLK +clk => mem[2][35].CLK +clk => mem[2][36].CLK +clk => mem[2][37].CLK +clk => mem[2][38].CLK +clk => mem[2][39].CLK +clk => mem[2][40].CLK +clk => mem[2][41].CLK +clk => mem[2][42].CLK +clk => mem[2][43].CLK +clk => mem[2][44].CLK +clk => mem[2][45].CLK +clk => mem[2][46].CLK +clk => mem[2][47].CLK +clk => mem[2][48].CLK +clk => mem[2][49].CLK +clk => mem[2][50].CLK +clk => mem[2][51].CLK +clk => mem[2][52].CLK +clk => mem[2][53].CLK +clk => mem[2][54].CLK +clk => mem[2][55].CLK +clk => mem[2][56].CLK +clk => mem[2][57].CLK +clk => mem[2][58].CLK +clk => mem[2][59].CLK +clk => mem[2][60].CLK +clk => mem[2][61].CLK +clk => mem[2][62].CLK +clk => mem[2][63].CLK +clk => mem[2][64].CLK +clk => mem[2][65].CLK +clk => mem[2][66].CLK +clk => mem[2][67].CLK +clk => mem[2][68].CLK +clk => mem[2][69].CLK +clk => mem[2][70].CLK +clk => mem[2][71].CLK +clk => mem[2][72].CLK +clk => mem[2][73].CLK +clk => mem[2][74].CLK +clk => mem[2][75].CLK +clk => mem[2][76].CLK +clk => mem[2][77].CLK +clk => mem[2][78].CLK +clk => mem[2][79].CLK +clk => mem[2][80].CLK +clk => mem[2][81].CLK +clk => mem[2][82].CLK +clk => mem[2][83].CLK +clk => mem[2][84].CLK +clk => mem[2][85].CLK +clk => mem[1][0].CLK +clk => mem[1][1].CLK +clk => mem[1][2].CLK +clk => mem[1][3].CLK +clk => mem[1][4].CLK +clk => mem[1][5].CLK +clk => mem[1][6].CLK +clk => mem[1][7].CLK +clk => mem[1][8].CLK +clk => mem[1][9].CLK +clk => mem[1][10].CLK +clk => mem[1][11].CLK +clk => mem[1][12].CLK +clk => mem[1][13].CLK +clk => mem[1][14].CLK +clk => mem[1][15].CLK +clk => mem[1][16].CLK +clk => mem[1][17].CLK +clk => mem[1][18].CLK +clk => mem[1][19].CLK +clk => mem[1][20].CLK +clk => mem[1][21].CLK +clk => mem[1][22].CLK +clk => mem[1][23].CLK +clk => mem[1][24].CLK +clk => mem[1][25].CLK +clk => mem[1][26].CLK +clk => mem[1][27].CLK +clk => mem[1][28].CLK +clk => mem[1][29].CLK +clk => mem[1][30].CLK +clk => mem[1][31].CLK +clk => mem[1][32].CLK +clk => mem[1][33].CLK +clk => mem[1][34].CLK +clk => mem[1][35].CLK +clk => mem[1][36].CLK +clk => mem[1][37].CLK +clk => mem[1][38].CLK +clk => mem[1][39].CLK +clk => mem[1][40].CLK +clk => mem[1][41].CLK +clk => mem[1][42].CLK +clk => mem[1][43].CLK +clk => mem[1][44].CLK +clk => mem[1][45].CLK +clk => mem[1][46].CLK +clk => mem[1][47].CLK +clk => mem[1][48].CLK +clk => mem[1][49].CLK +clk => mem[1][50].CLK +clk => mem[1][51].CLK +clk => mem[1][52].CLK +clk => mem[1][53].CLK +clk => mem[1][54].CLK +clk => mem[1][55].CLK +clk => mem[1][56].CLK +clk => mem[1][57].CLK +clk => mem[1][58].CLK +clk => mem[1][59].CLK +clk => mem[1][60].CLK +clk => mem[1][61].CLK +clk => mem[1][62].CLK +clk => mem[1][63].CLK +clk => mem[1][64].CLK +clk => mem[1][65].CLK +clk => mem[1][66].CLK +clk => mem[1][67].CLK +clk => mem[1][68].CLK +clk => mem[1][69].CLK +clk => mem[1][70].CLK +clk => mem[1][71].CLK +clk => mem[1][72].CLK +clk => mem[1][73].CLK +clk => mem[1][74].CLK +clk => mem[1][75].CLK +clk => mem[1][76].CLK +clk => mem[1][77].CLK +clk => mem[1][78].CLK +clk => mem[1][79].CLK +clk => mem[1][80].CLK +clk => mem[1][81].CLK +clk => mem[1][82].CLK +clk => mem[1][83].CLK +clk => mem[1][84].CLK +clk => mem[1][85].CLK +clk => mem[0][0].CLK +clk => mem[0][1].CLK +clk => mem[0][2].CLK +clk => mem[0][3].CLK +clk => mem[0][4].CLK +clk => mem[0][5].CLK +clk => mem[0][6].CLK +clk => mem[0][7].CLK +clk => mem[0][8].CLK +clk => mem[0][9].CLK +clk => mem[0][10].CLK +clk => mem[0][11].CLK +clk => mem[0][12].CLK +clk => mem[0][13].CLK +clk => mem[0][14].CLK +clk => mem[0][15].CLK +clk => mem[0][16].CLK +clk => mem[0][17].CLK +clk => mem[0][18].CLK +clk => mem[0][19].CLK +clk => mem[0][20].CLK +clk => mem[0][21].CLK +clk => mem[0][22].CLK +clk => mem[0][23].CLK +clk => mem[0][24].CLK +clk => mem[0][25].CLK +clk => mem[0][26].CLK +clk => mem[0][27].CLK +clk => mem[0][28].CLK +clk => mem[0][29].CLK +clk => mem[0][30].CLK +clk => mem[0][31].CLK +clk => mem[0][32].CLK +clk => mem[0][33].CLK +clk => mem[0][34].CLK +clk => mem[0][35].CLK +clk => mem[0][36].CLK +clk => mem[0][37].CLK +clk => mem[0][38].CLK +clk => mem[0][39].CLK +clk => mem[0][40].CLK +clk => mem[0][41].CLK +clk => mem[0][42].CLK +clk => mem[0][43].CLK +clk => mem[0][44].CLK +clk => mem[0][45].CLK +clk => mem[0][46].CLK +clk => mem[0][47].CLK +clk => mem[0][48].CLK +clk => mem[0][49].CLK +clk => mem[0][50].CLK +clk => mem[0][51].CLK +clk => mem[0][52].CLK +clk => mem[0][53].CLK +clk => mem[0][54].CLK +clk => mem[0][55].CLK +clk => mem[0][56].CLK +clk => mem[0][57].CLK +clk => mem[0][58].CLK +clk => mem[0][59].CLK +clk => mem[0][60].CLK +clk => mem[0][61].CLK +clk => mem[0][62].CLK +clk => mem[0][63].CLK +clk => mem[0][64].CLK +clk => mem[0][65].CLK +clk => mem[0][66].CLK +clk => mem[0][67].CLK +clk => mem[0][68].CLK +clk => mem[0][69].CLK +clk => mem[0][70].CLK +clk => mem[0][71].CLK +clk => mem[0][72].CLK +clk => mem[0][73].CLK +clk => mem[0][74].CLK +clk => mem[0][75].CLK +clk => mem[0][76].CLK +clk => mem[0][77].CLK +clk => mem[0][78].CLK +clk => mem[0][79].CLK +clk => mem[0][80].CLK +clk => mem[0][81].CLK +clk => mem[0][82].CLK +clk => mem[0][83].CLK +clk => mem[0][84].CLK +clk => mem[0][85].CLK +reset => csr_readdata[0]~reg0.ACLR +reset => csr_readdata[1]~reg0.ACLR +reset => csr_readdata[2]~reg0.ACLR +reset => csr_readdata[3]~reg0.ACLR +reset => csr_readdata[4]~reg0.ACLR +reset => csr_readdata[5]~reg0.ACLR +reset => csr_readdata[6]~reg0.ACLR +reset => csr_readdata[7]~reg0.ACLR +reset => csr_readdata[8]~reg0.ACLR +reset => csr_readdata[9]~reg0.ACLR +reset => csr_readdata[10]~reg0.ACLR +reset => csr_readdata[11]~reg0.ACLR +reset => csr_readdata[12]~reg0.ACLR +reset => csr_readdata[13]~reg0.ACLR +reset => csr_readdata[14]~reg0.ACLR +reset => csr_readdata[15]~reg0.ACLR +reset => csr_readdata[16]~reg0.ACLR +reset => csr_readdata[17]~reg0.ACLR +reset => csr_readdata[18]~reg0.ACLR +reset => csr_readdata[19]~reg0.ACLR +reset => csr_readdata[20]~reg0.ACLR +reset => csr_readdata[21]~reg0.ACLR +reset => csr_readdata[22]~reg0.ACLR +reset => csr_readdata[23]~reg0.ACLR +reset => csr_readdata[24]~reg0.ACLR +reset => csr_readdata[25]~reg0.ACLR +reset => csr_readdata[26]~reg0.ACLR +reset => csr_readdata[27]~reg0.ACLR +reset => csr_readdata[28]~reg0.ACLR +reset => csr_readdata[29]~reg0.ACLR +reset => csr_readdata[30]~reg0.ACLR +reset => csr_readdata[31]~reg0.ACLR +reset => mem_used[6].ACLR +reset => mem_used[5].ACLR +reset => mem_used[4].ACLR +reset => mem_used[3].ACLR +reset => mem_used[2].ACLR +reset => mem_used[1].ACLR +reset => mem_used[7].ACLR +reset => mem_used[0].ACLR +reset => mem[7][0].ACLR +reset => mem[7][1].ACLR +reset => mem[7][2].ACLR +reset => mem[7][3].ACLR +reset => mem[7][4].ACLR +reset => mem[7][5].ACLR +reset => mem[7][6].ACLR +reset => mem[7][7].ACLR +reset => mem[7][8].ACLR +reset => mem[7][9].ACLR +reset => mem[7][10].ACLR +reset => mem[7][11].ACLR +reset => mem[7][12].ACLR +reset => mem[7][13].ACLR +reset => mem[7][14].ACLR +reset => mem[7][15].ACLR +reset => mem[7][16].ACLR +reset => mem[7][17].ACLR +reset => mem[7][18].ACLR +reset => mem[7][19].ACLR +reset => mem[7][20].ACLR +reset => mem[7][21].ACLR +reset => mem[7][22].ACLR +reset => mem[7][23].ACLR +reset => mem[7][24].ACLR +reset => mem[7][25].ACLR +reset => mem[7][26].ACLR +reset => mem[7][27].ACLR +reset => mem[7][28].ACLR +reset => mem[7][29].ACLR +reset => mem[7][30].ACLR +reset => mem[7][31].ACLR +reset => mem[7][32].ACLR +reset => mem[7][33].ACLR +reset => mem[7][34].ACLR +reset => mem[7][35].ACLR +reset => mem[7][36].ACLR +reset => mem[7][37].ACLR +reset => mem[7][38].ACLR +reset => mem[7][39].ACLR +reset => mem[7][40].ACLR +reset => mem[7][41].ACLR +reset => mem[7][42].ACLR +reset => mem[7][43].ACLR +reset => mem[7][44].ACLR +reset => mem[7][45].ACLR +reset => mem[7][46].ACLR +reset => mem[7][47].ACLR +reset => mem[7][48].ACLR +reset => mem[7][49].ACLR +reset => mem[7][50].ACLR +reset => mem[7][51].ACLR +reset => mem[7][52].ACLR +reset => mem[7][53].ACLR +reset => mem[7][54].ACLR +reset => mem[7][55].ACLR +reset => mem[7][56].ACLR +reset => mem[7][57].ACLR +reset => mem[7][58].ACLR +reset => mem[7][59].ACLR +reset => mem[7][60].ACLR +reset => mem[7][61].ACLR +reset => mem[7][62].ACLR +reset => mem[7][63].ACLR +reset => mem[7][64].ACLR +reset => mem[7][65].ACLR +reset => mem[7][66].ACLR +reset => mem[7][67].ACLR +reset => mem[7][68].ACLR +reset => mem[7][69].ACLR +reset => mem[7][70].ACLR +reset => mem[7][71].ACLR +reset => mem[7][72].ACLR +reset => mem[7][73].ACLR +reset => mem[7][74].ACLR +reset => mem[7][75].ACLR +reset => mem[7][76].ACLR +reset => mem[7][77].ACLR +reset => mem[7][78].ACLR +reset => mem[7][79].ACLR +reset => mem[7][80].ACLR +reset => mem[7][81].ACLR +reset => mem[7][82].ACLR +reset => mem[7][83].ACLR +reset => mem[7][84].ACLR +reset => mem[7][85].ACLR +reset => mem[6][0].ACLR +reset => mem[6][1].ACLR +reset => mem[6][2].ACLR +reset => mem[6][3].ACLR +reset => mem[6][4].ACLR +reset => mem[6][5].ACLR +reset => mem[6][6].ACLR +reset => mem[6][7].ACLR +reset => mem[6][8].ACLR +reset => mem[6][9].ACLR +reset => mem[6][10].ACLR +reset => mem[6][11].ACLR +reset => mem[6][12].ACLR +reset => mem[6][13].ACLR +reset => mem[6][14].ACLR +reset => mem[6][15].ACLR +reset => mem[6][16].ACLR +reset => mem[6][17].ACLR +reset => mem[6][18].ACLR +reset => mem[6][19].ACLR +reset => mem[6][20].ACLR +reset => mem[6][21].ACLR +reset => mem[6][22].ACLR +reset => mem[6][23].ACLR +reset => mem[6][24].ACLR +reset => mem[6][25].ACLR +reset => mem[6][26].ACLR +reset => mem[6][27].ACLR +reset => mem[6][28].ACLR +reset => mem[6][29].ACLR +reset => mem[6][30].ACLR +reset => mem[6][31].ACLR +reset => mem[6][32].ACLR +reset => mem[6][33].ACLR +reset => mem[6][34].ACLR +reset => mem[6][35].ACLR +reset => mem[6][36].ACLR +reset => mem[6][37].ACLR +reset => mem[6][38].ACLR +reset => mem[6][39].ACLR +reset => mem[6][40].ACLR +reset => mem[6][41].ACLR +reset => mem[6][42].ACLR +reset => mem[6][43].ACLR +reset => mem[6][44].ACLR +reset => mem[6][45].ACLR +reset => mem[6][46].ACLR +reset => mem[6][47].ACLR +reset => mem[6][48].ACLR +reset => mem[6][49].ACLR +reset => mem[6][50].ACLR +reset => mem[6][51].ACLR +reset => mem[6][52].ACLR +reset => mem[6][53].ACLR +reset => mem[6][54].ACLR +reset => mem[6][55].ACLR +reset => mem[6][56].ACLR +reset => mem[6][57].ACLR +reset => mem[6][58].ACLR +reset => mem[6][59].ACLR +reset => mem[6][60].ACLR +reset => mem[6][61].ACLR +reset => mem[6][62].ACLR +reset => mem[6][63].ACLR +reset => mem[6][64].ACLR +reset => mem[6][65].ACLR +reset => mem[6][66].ACLR +reset => mem[6][67].ACLR +reset => mem[6][68].ACLR +reset => mem[6][69].ACLR +reset => mem[6][70].ACLR +reset => mem[6][71].ACLR +reset => mem[6][72].ACLR +reset => mem[6][73].ACLR +reset => mem[6][74].ACLR +reset => mem[6][75].ACLR +reset => mem[6][76].ACLR +reset => mem[6][77].ACLR +reset => mem[6][78].ACLR +reset => mem[6][79].ACLR +reset => mem[6][80].ACLR +reset => mem[6][81].ACLR +reset => mem[6][82].ACLR +reset => mem[6][83].ACLR +reset => mem[6][84].ACLR +reset => mem[6][85].ACLR +reset => mem[5][0].ACLR +reset => mem[5][1].ACLR +reset => mem[5][2].ACLR +reset => mem[5][3].ACLR +reset => mem[5][4].ACLR +reset => mem[5][5].ACLR +reset => mem[5][6].ACLR +reset => mem[5][7].ACLR +reset => mem[5][8].ACLR +reset => mem[5][9].ACLR +reset => mem[5][10].ACLR +reset => mem[5][11].ACLR +reset => mem[5][12].ACLR +reset => mem[5][13].ACLR +reset => mem[5][14].ACLR +reset => mem[5][15].ACLR +reset => mem[5][16].ACLR +reset => mem[5][17].ACLR +reset => mem[5][18].ACLR +reset => mem[5][19].ACLR +reset => mem[5][20].ACLR +reset => mem[5][21].ACLR +reset => mem[5][22].ACLR +reset => mem[5][23].ACLR +reset => mem[5][24].ACLR +reset => mem[5][25].ACLR +reset => mem[5][26].ACLR +reset => mem[5][27].ACLR +reset => mem[5][28].ACLR +reset => mem[5][29].ACLR +reset => mem[5][30].ACLR +reset => mem[5][31].ACLR +reset => mem[5][32].ACLR +reset => mem[5][33].ACLR +reset => mem[5][34].ACLR +reset => mem[5][35].ACLR +reset => mem[5][36].ACLR +reset => mem[5][37].ACLR +reset => mem[5][38].ACLR +reset => mem[5][39].ACLR +reset => mem[5][40].ACLR +reset => mem[5][41].ACLR +reset => mem[5][42].ACLR +reset => mem[5][43].ACLR +reset => mem[5][44].ACLR +reset => mem[5][45].ACLR +reset => mem[5][46].ACLR +reset => mem[5][47].ACLR +reset => mem[5][48].ACLR +reset => mem[5][49].ACLR +reset => mem[5][50].ACLR +reset => mem[5][51].ACLR +reset => mem[5][52].ACLR +reset => mem[5][53].ACLR +reset => mem[5][54].ACLR +reset => mem[5][55].ACLR +reset => mem[5][56].ACLR +reset => mem[5][57].ACLR +reset => mem[5][58].ACLR +reset => mem[5][59].ACLR +reset => mem[5][60].ACLR +reset => mem[5][61].ACLR +reset => mem[5][62].ACLR +reset => mem[5][63].ACLR +reset => mem[5][64].ACLR +reset => mem[5][65].ACLR +reset => mem[5][66].ACLR +reset => mem[5][67].ACLR +reset => mem[5][68].ACLR +reset => mem[5][69].ACLR +reset => mem[5][70].ACLR +reset => mem[5][71].ACLR +reset => mem[5][72].ACLR +reset => mem[5][73].ACLR +reset => mem[5][74].ACLR +reset => mem[5][75].ACLR +reset => mem[5][76].ACLR +reset => mem[5][77].ACLR +reset => mem[5][78].ACLR +reset => mem[5][79].ACLR +reset => mem[5][80].ACLR +reset => mem[5][81].ACLR +reset => mem[5][82].ACLR +reset => mem[5][83].ACLR +reset => mem[5][84].ACLR +reset => mem[5][85].ACLR +reset => mem[4][0].ACLR +reset => mem[4][1].ACLR +reset => mem[4][2].ACLR +reset => mem[4][3].ACLR +reset => mem[4][4].ACLR +reset => mem[4][5].ACLR +reset => mem[4][6].ACLR +reset => mem[4][7].ACLR +reset => mem[4][8].ACLR +reset => mem[4][9].ACLR +reset => mem[4][10].ACLR +reset => mem[4][11].ACLR +reset => mem[4][12].ACLR +reset => mem[4][13].ACLR +reset => mem[4][14].ACLR +reset => mem[4][15].ACLR +reset => mem[4][16].ACLR +reset => mem[4][17].ACLR +reset => mem[4][18].ACLR +reset => mem[4][19].ACLR +reset => mem[4][20].ACLR +reset => mem[4][21].ACLR +reset => mem[4][22].ACLR +reset => mem[4][23].ACLR +reset => mem[4][24].ACLR +reset => mem[4][25].ACLR +reset => mem[4][26].ACLR +reset => mem[4][27].ACLR +reset => mem[4][28].ACLR +reset => mem[4][29].ACLR +reset => mem[4][30].ACLR +reset => mem[4][31].ACLR +reset => mem[4][32].ACLR +reset => mem[4][33].ACLR +reset => mem[4][34].ACLR +reset => mem[4][35].ACLR +reset => mem[4][36].ACLR +reset => mem[4][37].ACLR +reset => mem[4][38].ACLR +reset => mem[4][39].ACLR +reset => mem[4][40].ACLR +reset => mem[4][41].ACLR +reset => mem[4][42].ACLR +reset => mem[4][43].ACLR +reset => mem[4][44].ACLR +reset => mem[4][45].ACLR +reset => mem[4][46].ACLR +reset => mem[4][47].ACLR +reset => mem[4][48].ACLR +reset => mem[4][49].ACLR +reset => mem[4][50].ACLR +reset => mem[4][51].ACLR +reset => mem[4][52].ACLR +reset => mem[4][53].ACLR +reset => mem[4][54].ACLR +reset => mem[4][55].ACLR +reset => mem[4][56].ACLR +reset => mem[4][57].ACLR +reset => mem[4][58].ACLR +reset => mem[4][59].ACLR +reset => mem[4][60].ACLR +reset => mem[4][61].ACLR +reset => mem[4][62].ACLR +reset => mem[4][63].ACLR +reset => mem[4][64].ACLR +reset => mem[4][65].ACLR +reset => mem[4][66].ACLR +reset => mem[4][67].ACLR +reset => mem[4][68].ACLR +reset => mem[4][69].ACLR +reset => mem[4][70].ACLR +reset => mem[4][71].ACLR +reset => mem[4][72].ACLR +reset => mem[4][73].ACLR +reset => mem[4][74].ACLR +reset => mem[4][75].ACLR +reset => mem[4][76].ACLR +reset => mem[4][77].ACLR +reset => mem[4][78].ACLR +reset => mem[4][79].ACLR +reset => mem[4][80].ACLR +reset => mem[4][81].ACLR +reset => mem[4][82].ACLR +reset => mem[4][83].ACLR +reset => mem[4][84].ACLR +reset => mem[4][85].ACLR +reset => mem[3][0].ACLR +reset => mem[3][1].ACLR +reset => mem[3][2].ACLR +reset => mem[3][3].ACLR +reset => mem[3][4].ACLR +reset => mem[3][5].ACLR +reset => mem[3][6].ACLR +reset => mem[3][7].ACLR +reset => mem[3][8].ACLR +reset => mem[3][9].ACLR +reset => mem[3][10].ACLR +reset => mem[3][11].ACLR +reset => mem[3][12].ACLR +reset => mem[3][13].ACLR +reset => mem[3][14].ACLR +reset => mem[3][15].ACLR +reset => mem[3][16].ACLR +reset => mem[3][17].ACLR +reset => mem[3][18].ACLR +reset => mem[3][19].ACLR +reset => mem[3][20].ACLR +reset => mem[3][21].ACLR +reset => mem[3][22].ACLR +reset => mem[3][23].ACLR +reset => mem[3][24].ACLR +reset => mem[3][25].ACLR +reset => mem[3][26].ACLR +reset => mem[3][27].ACLR +reset => mem[3][28].ACLR +reset => mem[3][29].ACLR +reset => mem[3][30].ACLR +reset => mem[3][31].ACLR +reset => mem[3][32].ACLR +reset => mem[3][33].ACLR +reset => mem[3][34].ACLR +reset => mem[3][35].ACLR +reset => mem[3][36].ACLR +reset => mem[3][37].ACLR +reset => mem[3][38].ACLR +reset => mem[3][39].ACLR +reset => mem[3][40].ACLR +reset => mem[3][41].ACLR +reset => mem[3][42].ACLR +reset => mem[3][43].ACLR +reset => mem[3][44].ACLR +reset => mem[3][45].ACLR +reset => mem[3][46].ACLR +reset => mem[3][47].ACLR +reset => mem[3][48].ACLR +reset => mem[3][49].ACLR +reset => mem[3][50].ACLR +reset => mem[3][51].ACLR +reset => mem[3][52].ACLR +reset => mem[3][53].ACLR +reset => mem[3][54].ACLR +reset => mem[3][55].ACLR +reset => mem[3][56].ACLR +reset => mem[3][57].ACLR +reset => mem[3][58].ACLR +reset => mem[3][59].ACLR +reset => mem[3][60].ACLR +reset => mem[3][61].ACLR +reset => mem[3][62].ACLR +reset => mem[3][63].ACLR +reset => mem[3][64].ACLR +reset => mem[3][65].ACLR +reset => mem[3][66].ACLR +reset => mem[3][67].ACLR +reset => mem[3][68].ACLR +reset => mem[3][69].ACLR +reset => mem[3][70].ACLR +reset => mem[3][71].ACLR +reset => mem[3][72].ACLR +reset => mem[3][73].ACLR +reset => mem[3][74].ACLR +reset => mem[3][75].ACLR +reset => mem[3][76].ACLR +reset => mem[3][77].ACLR +reset => mem[3][78].ACLR +reset => mem[3][79].ACLR +reset => mem[3][80].ACLR +reset => mem[3][81].ACLR +reset => mem[3][82].ACLR +reset => mem[3][83].ACLR +reset => mem[3][84].ACLR +reset => mem[3][85].ACLR +reset => mem[2][0].ACLR +reset => mem[2][1].ACLR +reset => mem[2][2].ACLR +reset => mem[2][3].ACLR +reset => mem[2][4].ACLR +reset => mem[2][5].ACLR +reset => mem[2][6].ACLR +reset => mem[2][7].ACLR +reset => mem[2][8].ACLR +reset => mem[2][9].ACLR +reset => mem[2][10].ACLR +reset => mem[2][11].ACLR +reset => mem[2][12].ACLR +reset => mem[2][13].ACLR +reset => mem[2][14].ACLR +reset => mem[2][15].ACLR +reset => mem[2][16].ACLR +reset => mem[2][17].ACLR +reset => mem[2][18].ACLR +reset => mem[2][19].ACLR +reset => mem[2][20].ACLR +reset => mem[2][21].ACLR +reset => mem[2][22].ACLR +reset => mem[2][23].ACLR +reset => mem[2][24].ACLR +reset => mem[2][25].ACLR +reset => mem[2][26].ACLR +reset => mem[2][27].ACLR +reset => mem[2][28].ACLR +reset => mem[2][29].ACLR +reset => mem[2][30].ACLR +reset => mem[2][31].ACLR +reset => mem[2][32].ACLR +reset => mem[2][33].ACLR +reset => mem[2][34].ACLR +reset => mem[2][35].ACLR +reset => mem[2][36].ACLR +reset => mem[2][37].ACLR +reset => mem[2][38].ACLR +reset => mem[2][39].ACLR +reset => mem[2][40].ACLR +reset => mem[2][41].ACLR +reset => mem[2][42].ACLR +reset => mem[2][43].ACLR +reset => mem[2][44].ACLR +reset => mem[2][45].ACLR +reset => mem[2][46].ACLR +reset => mem[2][47].ACLR +reset => mem[2][48].ACLR +reset => mem[2][49].ACLR +reset => mem[2][50].ACLR +reset => mem[2][51].ACLR +reset => mem[2][52].ACLR +reset => mem[2][53].ACLR +reset => mem[2][54].ACLR +reset => mem[2][55].ACLR +reset => mem[2][56].ACLR +reset => mem[2][57].ACLR +reset => mem[2][58].ACLR +reset => mem[2][59].ACLR +reset => mem[2][60].ACLR +reset => mem[2][61].ACLR +reset => mem[2][62].ACLR +reset => mem[2][63].ACLR +reset => mem[2][64].ACLR +reset => mem[2][65].ACLR +reset => mem[2][66].ACLR +reset => mem[2][67].ACLR +reset => mem[2][68].ACLR +reset => mem[2][69].ACLR +reset => mem[2][70].ACLR +reset => mem[2][71].ACLR +reset => mem[2][72].ACLR +reset => mem[2][73].ACLR +reset => mem[2][74].ACLR +reset => mem[2][75].ACLR +reset => mem[2][76].ACLR +reset => mem[2][77].ACLR +reset => mem[2][78].ACLR +reset => mem[2][79].ACLR +reset => mem[2][80].ACLR +reset => mem[2][81].ACLR +reset => mem[2][82].ACLR +reset => mem[2][83].ACLR +reset => mem[2][84].ACLR +reset => mem[2][85].ACLR +reset => mem[1][0].ACLR +reset => mem[1][1].ACLR +reset => mem[1][2].ACLR +reset => mem[1][3].ACLR +reset => mem[1][4].ACLR +reset => mem[1][5].ACLR +reset => mem[1][6].ACLR +reset => mem[1][7].ACLR +reset => mem[1][8].ACLR +reset => mem[1][9].ACLR +reset => mem[1][10].ACLR +reset => mem[1][11].ACLR +reset => mem[1][12].ACLR +reset => mem[1][13].ACLR +reset => mem[1][14].ACLR +reset => mem[1][15].ACLR +reset => mem[1][16].ACLR +reset => mem[1][17].ACLR +reset => mem[1][18].ACLR +reset => mem[1][19].ACLR +reset => mem[1][20].ACLR +reset => mem[1][21].ACLR +reset => mem[1][22].ACLR +reset => mem[1][23].ACLR +reset => mem[1][24].ACLR +reset => mem[1][25].ACLR +reset => mem[1][26].ACLR +reset => mem[1][27].ACLR +reset => mem[1][28].ACLR +reset => mem[1][29].ACLR +reset => mem[1][30].ACLR +reset => mem[1][31].ACLR +reset => mem[1][32].ACLR +reset => mem[1][33].ACLR +reset => mem[1][34].ACLR +reset => mem[1][35].ACLR +reset => mem[1][36].ACLR +reset => mem[1][37].ACLR +reset => mem[1][38].ACLR +reset => mem[1][39].ACLR +reset => mem[1][40].ACLR +reset => mem[1][41].ACLR +reset => mem[1][42].ACLR +reset => mem[1][43].ACLR +reset => mem[1][44].ACLR +reset => mem[1][45].ACLR +reset => mem[1][46].ACLR +reset => mem[1][47].ACLR +reset => mem[1][48].ACLR +reset => mem[1][49].ACLR +reset => mem[1][50].ACLR +reset => mem[1][51].ACLR +reset => mem[1][52].ACLR +reset => mem[1][53].ACLR +reset => mem[1][54].ACLR +reset => mem[1][55].ACLR +reset => mem[1][56].ACLR +reset => mem[1][57].ACLR +reset => mem[1][58].ACLR +reset => mem[1][59].ACLR +reset => mem[1][60].ACLR +reset => mem[1][61].ACLR +reset => mem[1][62].ACLR +reset => mem[1][63].ACLR +reset => mem[1][64].ACLR +reset => mem[1][65].ACLR +reset => mem[1][66].ACLR +reset => mem[1][67].ACLR +reset => mem[1][68].ACLR +reset => mem[1][69].ACLR +reset => mem[1][70].ACLR +reset => mem[1][71].ACLR +reset => mem[1][72].ACLR +reset => mem[1][73].ACLR +reset => mem[1][74].ACLR +reset => mem[1][75].ACLR +reset => mem[1][76].ACLR +reset => mem[1][77].ACLR +reset => mem[1][78].ACLR +reset => mem[1][79].ACLR +reset => mem[1][80].ACLR +reset => mem[1][81].ACLR +reset => mem[1][82].ACLR +reset => mem[1][83].ACLR +reset => mem[1][84].ACLR +reset => mem[1][85].ACLR +reset => mem[0][0].ACLR +reset => mem[0][1].ACLR +reset => mem[0][2].ACLR +reset => mem[0][3].ACLR +reset => mem[0][4].ACLR +reset => mem[0][5].ACLR +reset => mem[0][6].ACLR +reset => mem[0][7].ACLR +reset => mem[0][8].ACLR +reset => mem[0][9].ACLR +reset => mem[0][10].ACLR +reset => mem[0][11].ACLR +reset => mem[0][12].ACLR +reset => mem[0][13].ACLR +reset => mem[0][14].ACLR +reset => mem[0][15].ACLR +reset => mem[0][16].ACLR +reset => mem[0][17].ACLR +reset => mem[0][18].ACLR +reset => mem[0][19].ACLR +reset => mem[0][20].ACLR +reset => mem[0][21].ACLR +reset => mem[0][22].ACLR +reset => mem[0][23].ACLR +reset => mem[0][24].ACLR +reset => mem[0][25].ACLR +reset => mem[0][26].ACLR +reset => mem[0][27].ACLR +reset => mem[0][28].ACLR +reset => mem[0][29].ACLR +reset => mem[0][30].ACLR +reset => mem[0][31].ACLR +reset => mem[0][32].ACLR +reset => mem[0][33].ACLR +reset => mem[0][34].ACLR +reset => mem[0][35].ACLR +reset => mem[0][36].ACLR +reset => mem[0][37].ACLR +reset => mem[0][38].ACLR +reset => mem[0][39].ACLR +reset => mem[0][40].ACLR +reset => mem[0][41].ACLR +reset => mem[0][42].ACLR +reset => mem[0][43].ACLR +reset => mem[0][44].ACLR +reset => mem[0][45].ACLR +reset => mem[0][46].ACLR +reset => mem[0][47].ACLR +reset => mem[0][48].ACLR +reset => mem[0][49].ACLR +reset => mem[0][50].ACLR +reset => mem[0][51].ACLR +reset => mem[0][52].ACLR +reset => mem[0][53].ACLR +reset => mem[0][54].ACLR +reset => mem[0][55].ACLR +reset => mem[0][56].ACLR +reset => mem[0][57].ACLR +reset => mem[0][58].ACLR +reset => mem[0][59].ACLR +reset => mem[0][60].ACLR +reset => mem[0][61].ACLR +reset => mem[0][62].ACLR +reset => mem[0][63].ACLR +reset => mem[0][64].ACLR +reset => mem[0][65].ACLR +reset => mem[0][66].ACLR +reset => mem[0][67].ACLR +reset => mem[0][68].ACLR +reset => mem[0][69].ACLR +reset => mem[0][70].ACLR +reset => mem[0][71].ACLR +reset => mem[0][72].ACLR +reset => mem[0][73].ACLR +reset => mem[0][74].ACLR +reset => mem[0][75].ACLR +reset => mem[0][76].ACLR +reset => mem[0][77].ACLR +reset => mem[0][78].ACLR +reset => mem[0][79].ACLR +reset => mem[0][80].ACLR +reset => mem[0][81].ACLR +reset => mem[0][82].ACLR +reset => mem[0][83].ACLR +reset => mem[0][84].ACLR +reset => mem[0][85].ACLR +in_data[0] => mem.DATAB +in_data[0] => mem.DATAB +in_data[0] => mem.DATAB +in_data[0] => mem.DATAB +in_data[0] => mem.DATAB +in_data[0] => mem.DATAB +in_data[0] => mem.DATAB +in_data[1] => mem.DATAB +in_data[1] => mem.DATAB +in_data[1] => mem.DATAB +in_data[1] => mem.DATAB +in_data[1] => mem.DATAB +in_data[1] => mem.DATAB +in_data[1] => mem.DATAB +in_data[2] => mem.DATAB +in_data[2] => mem.DATAB +in_data[2] => mem.DATAB +in_data[2] => mem.DATAB +in_data[2] => mem.DATAB +in_data[2] => mem.DATAB +in_data[2] => mem.DATAB +in_data[3] => mem.DATAB +in_data[3] => mem.DATAB +in_data[3] => mem.DATAB +in_data[3] => mem.DATAB +in_data[3] => mem.DATAB +in_data[3] => mem.DATAB +in_data[3] => mem.DATAB +in_data[4] => mem.DATAB +in_data[4] => mem.DATAB +in_data[4] => mem.DATAB +in_data[4] => mem.DATAB +in_data[4] => mem.DATAB +in_data[4] => mem.DATAB +in_data[4] => mem.DATAB +in_data[5] => mem.DATAB +in_data[5] => mem.DATAB +in_data[5] => mem.DATAB +in_data[5] => mem.DATAB +in_data[5] => mem.DATAB +in_data[5] => mem.DATAB +in_data[5] => mem.DATAB +in_data[6] => mem.DATAB +in_data[6] => mem.DATAB +in_data[6] => mem.DATAB +in_data[6] => mem.DATAB +in_data[6] => mem.DATAB +in_data[6] => mem.DATAB +in_data[6] => mem.DATAB +in_data[7] => mem.DATAB +in_data[7] => mem.DATAB +in_data[7] => mem.DATAB +in_data[7] => mem.DATAB +in_data[7] => mem.DATAB +in_data[7] => mem.DATAB +in_data[7] => mem.DATAB +in_data[8] => mem.DATAB +in_data[8] => mem.DATAB +in_data[8] => mem.DATAB +in_data[8] => mem.DATAB +in_data[8] => mem.DATAB +in_data[8] => mem.DATAB +in_data[8] => mem.DATAB +in_data[9] => mem.DATAB +in_data[9] => mem.DATAB +in_data[9] => mem.DATAB +in_data[9] => mem.DATAB +in_data[9] => mem.DATAB +in_data[9] => mem.DATAB +in_data[9] => mem.DATAB +in_data[10] => mem.DATAB +in_data[10] => mem.DATAB +in_data[10] => mem.DATAB +in_data[10] => mem.DATAB +in_data[10] => mem.DATAB +in_data[10] => mem.DATAB +in_data[10] => mem.DATAB +in_data[11] => mem.DATAB +in_data[11] => mem.DATAB +in_data[11] => mem.DATAB +in_data[11] => mem.DATAB +in_data[11] => mem.DATAB +in_data[11] => mem.DATAB +in_data[11] => mem.DATAB +in_data[12] => mem.DATAB +in_data[12] => mem.DATAB +in_data[12] => mem.DATAB +in_data[12] => mem.DATAB +in_data[12] => mem.DATAB +in_data[12] => mem.DATAB +in_data[12] => mem.DATAB +in_data[13] => mem.DATAB +in_data[13] => mem.DATAB +in_data[13] => mem.DATAB +in_data[13] => mem.DATAB +in_data[13] => mem.DATAB +in_data[13] => mem.DATAB +in_data[13] => mem.DATAB +in_data[14] => mem.DATAB +in_data[14] => mem.DATAB +in_data[14] => mem.DATAB +in_data[14] => mem.DATAB +in_data[14] => mem.DATAB +in_data[14] => mem.DATAB +in_data[14] => mem.DATAB +in_data[15] => mem.DATAB +in_data[15] => mem.DATAB +in_data[15] => mem.DATAB +in_data[15] => mem.DATAB +in_data[15] => mem.DATAB +in_data[15] => mem.DATAB +in_data[15] => mem.DATAB +in_data[16] => mem.DATAB +in_data[16] => mem.DATAB +in_data[16] => mem.DATAB +in_data[16] => mem.DATAB +in_data[16] => mem.DATAB +in_data[16] => mem.DATAB +in_data[16] => mem.DATAB +in_data[17] => mem.DATAB +in_data[17] => mem.DATAB +in_data[17] => mem.DATAB +in_data[17] => mem.DATAB +in_data[17] => mem.DATAB +in_data[17] => mem.DATAB +in_data[17] => mem.DATAB +in_data[18] => mem.DATAB +in_data[18] => mem.DATAB +in_data[18] => mem.DATAB +in_data[18] => mem.DATAB +in_data[18] => mem.DATAB +in_data[18] => mem.DATAB +in_data[18] => mem.DATAB +in_data[19] => mem.DATAB +in_data[19] => mem.DATAB +in_data[19] => mem.DATAB +in_data[19] => mem.DATAB +in_data[19] => mem.DATAB +in_data[19] => mem.DATAB +in_data[19] => mem.DATAB +in_data[20] => mem.DATAB +in_data[20] => mem.DATAB +in_data[20] => mem.DATAB +in_data[20] => mem.DATAB +in_data[20] => mem.DATAB +in_data[20] => mem.DATAB +in_data[20] => mem.DATAB +in_data[21] => mem.DATAB +in_data[21] => mem.DATAB +in_data[21] => mem.DATAB +in_data[21] => mem.DATAB +in_data[21] => mem.DATAB +in_data[21] => mem.DATAB +in_data[21] => mem.DATAB +in_data[22] => mem.DATAB +in_data[22] => mem.DATAB +in_data[22] => mem.DATAB +in_data[22] => mem.DATAB +in_data[22] => mem.DATAB +in_data[22] => mem.DATAB +in_data[22] => mem.DATAB +in_data[23] => mem.DATAB +in_data[23] => mem.DATAB +in_data[23] => mem.DATAB +in_data[23] => mem.DATAB +in_data[23] => mem.DATAB +in_data[23] => mem.DATAB +in_data[23] => mem.DATAB +in_data[24] => mem.DATAB +in_data[24] => mem.DATAB +in_data[24] => mem.DATAB +in_data[24] => mem.DATAB +in_data[24] => mem.DATAB +in_data[24] => mem.DATAB +in_data[24] => mem.DATAB +in_data[25] => mem.DATAB +in_data[25] => mem.DATAB +in_data[25] => mem.DATAB +in_data[25] => mem.DATAB +in_data[25] => mem.DATAB +in_data[25] => mem.DATAB +in_data[25] => mem.DATAB +in_data[26] => mem.DATAB +in_data[26] => mem.DATAB +in_data[26] => mem.DATAB +in_data[26] => mem.DATAB +in_data[26] => mem.DATAB +in_data[26] => mem.DATAB +in_data[26] => mem.DATAB +in_data[27] => mem.DATAB +in_data[27] => mem.DATAB +in_data[27] => mem.DATAB +in_data[27] => mem.DATAB +in_data[27] => mem.DATAB +in_data[27] => mem.DATAB +in_data[27] => mem.DATAB +in_data[28] => mem.DATAB +in_data[28] => mem.DATAB +in_data[28] => mem.DATAB +in_data[28] => mem.DATAB +in_data[28] => mem.DATAB +in_data[28] => mem.DATAB +in_data[28] => mem.DATAB +in_data[29] => mem.DATAB +in_data[29] => mem.DATAB +in_data[29] => mem.DATAB +in_data[29] => mem.DATAB +in_data[29] => mem.DATAB +in_data[29] => mem.DATAB +in_data[29] => mem.DATAB +in_data[30] => mem.DATAB +in_data[30] => mem.DATAB +in_data[30] => mem.DATAB +in_data[30] => mem.DATAB +in_data[30] => mem.DATAB +in_data[30] => mem.DATAB +in_data[30] => mem.DATAB +in_data[31] => mem.DATAB +in_data[31] => mem.DATAB +in_data[31] => mem.DATAB +in_data[31] => mem.DATAB +in_data[31] => mem.DATAB +in_data[31] => mem.DATAB +in_data[31] => mem.DATAB +in_data[32] => mem.DATAB +in_data[32] => mem.DATAB +in_data[32] => mem.DATAB +in_data[32] => mem.DATAB +in_data[32] => mem.DATAB +in_data[32] => mem.DATAB +in_data[32] => mem.DATAB +in_data[33] => mem.DATAB +in_data[33] => mem.DATAB +in_data[33] => mem.DATAB +in_data[33] => mem.DATAB +in_data[33] => mem.DATAB +in_data[33] => mem.DATAB +in_data[33] => mem.DATAB +in_data[34] => mem.DATAB +in_data[34] => mem.DATAB +in_data[34] => mem.DATAB +in_data[34] => mem.DATAB +in_data[34] => mem.DATAB +in_data[34] => mem.DATAB +in_data[34] => mem.DATAB +in_data[35] => mem.DATAB +in_data[35] => mem.DATAB +in_data[35] => mem.DATAB +in_data[35] => mem.DATAB +in_data[35] => mem.DATAB +in_data[35] => mem.DATAB +in_data[35] => mem.DATAB +in_data[36] => mem.DATAB +in_data[36] => mem.DATAB +in_data[36] => mem.DATAB +in_data[36] => mem.DATAB +in_data[36] => mem.DATAB +in_data[36] => mem.DATAB +in_data[36] => mem.DATAB +in_data[37] => mem.DATAB +in_data[37] => mem.DATAB +in_data[37] => mem.DATAB +in_data[37] => mem.DATAB +in_data[37] => mem.DATAB +in_data[37] => mem.DATAB +in_data[37] => mem.DATAB +in_data[38] => mem.DATAB +in_data[38] => mem.DATAB +in_data[38] => mem.DATAB +in_data[38] => mem.DATAB +in_data[38] => mem.DATAB +in_data[38] => mem.DATAB +in_data[38] => mem.DATAB +in_data[39] => mem.DATAB +in_data[39] => mem.DATAB +in_data[39] => mem.DATAB +in_data[39] => mem.DATAB +in_data[39] => mem.DATAB +in_data[39] => mem.DATAB +in_data[39] => mem.DATAB +in_data[40] => mem.DATAB +in_data[40] => mem.DATAB +in_data[40] => mem.DATAB +in_data[40] => mem.DATAB +in_data[40] => mem.DATAB +in_data[40] => mem.DATAB +in_data[40] => mem.DATAB +in_data[41] => mem.DATAB +in_data[41] => mem.DATAB +in_data[41] => mem.DATAB +in_data[41] => mem.DATAB +in_data[41] => mem.DATAB +in_data[41] => mem.DATAB +in_data[41] => mem.DATAB +in_data[42] => mem.DATAB +in_data[42] => mem.DATAB +in_data[42] => mem.DATAB +in_data[42] => mem.DATAB +in_data[42] => mem.DATAB +in_data[42] => mem.DATAB +in_data[42] => mem.DATAB +in_data[43] => mem.DATAB +in_data[43] => mem.DATAB +in_data[43] => mem.DATAB +in_data[43] => mem.DATAB +in_data[43] => mem.DATAB +in_data[43] => mem.DATAB +in_data[43] => mem.DATAB +in_data[44] => mem.DATAB +in_data[44] => mem.DATAB +in_data[44] => mem.DATAB +in_data[44] => mem.DATAB +in_data[44] => mem.DATAB +in_data[44] => mem.DATAB +in_data[44] => mem.DATAB +in_data[45] => mem.DATAB +in_data[45] => mem.DATAB +in_data[45] => mem.DATAB +in_data[45] => mem.DATAB +in_data[45] => mem.DATAB +in_data[45] => mem.DATAB +in_data[45] => mem.DATAB +in_data[46] => mem.DATAB +in_data[46] => mem.DATAB +in_data[46] => mem.DATAB +in_data[46] => mem.DATAB +in_data[46] => mem.DATAB +in_data[46] => mem.DATAB +in_data[46] => mem.DATAB +in_data[47] => mem.DATAB +in_data[47] => mem.DATAB +in_data[47] => mem.DATAB +in_data[47] => mem.DATAB +in_data[47] => mem.DATAB +in_data[47] => mem.DATAB +in_data[47] => mem.DATAB +in_data[48] => mem.DATAB +in_data[48] => mem.DATAB +in_data[48] => mem.DATAB +in_data[48] => mem.DATAB +in_data[48] => mem.DATAB +in_data[48] => mem.DATAB +in_data[48] => mem.DATAB +in_data[49] => mem.DATAB +in_data[49] => mem.DATAB +in_data[49] => mem.DATAB +in_data[49] => mem.DATAB +in_data[49] => mem.DATAB +in_data[49] => mem.DATAB +in_data[49] => mem.DATAB +in_data[50] => mem.DATAB +in_data[50] => mem.DATAB +in_data[50] => mem.DATAB +in_data[50] => mem.DATAB +in_data[50] => mem.DATAB +in_data[50] => mem.DATAB +in_data[50] => mem.DATAB +in_data[51] => mem.DATAB +in_data[51] => mem.DATAB +in_data[51] => mem.DATAB +in_data[51] => mem.DATAB +in_data[51] => mem.DATAB +in_data[51] => mem.DATAB +in_data[51] => mem.DATAB +in_data[52] => mem.DATAB +in_data[52] => mem.DATAB +in_data[52] => mem.DATAB +in_data[52] => mem.DATAB +in_data[52] => mem.DATAB +in_data[52] => mem.DATAB +in_data[52] => mem.DATAB +in_data[53] => mem.DATAB +in_data[53] => mem.DATAB +in_data[53] => mem.DATAB +in_data[53] => mem.DATAB +in_data[53] => mem.DATAB +in_data[53] => mem.DATAB +in_data[53] => mem.DATAB +in_data[54] => mem.DATAB +in_data[54] => mem.DATAB +in_data[54] => mem.DATAB +in_data[54] => mem.DATAB +in_data[54] => mem.DATAB +in_data[54] => mem.DATAB +in_data[54] => mem.DATAB +in_data[55] => mem.DATAB +in_data[55] => mem.DATAB +in_data[55] => mem.DATAB +in_data[55] => mem.DATAB +in_data[55] => mem.DATAB +in_data[55] => mem.DATAB +in_data[55] => mem.DATAB +in_data[56] => mem.DATAB +in_data[56] => mem.DATAB +in_data[56] => mem.DATAB +in_data[56] => mem.DATAB +in_data[56] => mem.DATAB +in_data[56] => mem.DATAB +in_data[56] => mem.DATAB +in_data[57] => mem.DATAB +in_data[57] => mem.DATAB +in_data[57] => mem.DATAB +in_data[57] => mem.DATAB +in_data[57] => mem.DATAB +in_data[57] => mem.DATAB +in_data[57] => mem.DATAB +in_data[58] => mem.DATAB +in_data[58] => mem.DATAB +in_data[58] => mem.DATAB +in_data[58] => mem.DATAB +in_data[58] => mem.DATAB +in_data[58] => mem.DATAB +in_data[58] => mem.DATAB +in_data[59] => mem.DATAB +in_data[59] => mem.DATAB +in_data[59] => mem.DATAB +in_data[59] => mem.DATAB +in_data[59] => mem.DATAB +in_data[59] => mem.DATAB +in_data[59] => mem.DATAB +in_data[60] => mem.DATAB +in_data[60] => mem.DATAB +in_data[60] => mem.DATAB +in_data[60] => mem.DATAB +in_data[60] => mem.DATAB +in_data[60] => mem.DATAB +in_data[60] => mem.DATAB +in_data[61] => mem.DATAB +in_data[61] => mem.DATAB +in_data[61] => mem.DATAB +in_data[61] => mem.DATAB +in_data[61] => mem.DATAB +in_data[61] => mem.DATAB +in_data[61] => mem.DATAB +in_data[62] => mem.DATAB +in_data[62] => mem.DATAB +in_data[62] => mem.DATAB +in_data[62] => mem.DATAB +in_data[62] => mem.DATAB +in_data[62] => mem.DATAB +in_data[62] => mem.DATAB +in_data[63] => mem.DATAB +in_data[63] => mem.DATAB +in_data[63] => mem.DATAB +in_data[63] => mem.DATAB +in_data[63] => mem.DATAB +in_data[63] => mem.DATAB +in_data[63] => mem.DATAB +in_data[64] => mem.DATAB +in_data[64] => mem.DATAB +in_data[64] => mem.DATAB +in_data[64] => mem.DATAB +in_data[64] => mem.DATAB +in_data[64] => mem.DATAB +in_data[64] => mem.DATAB +in_data[65] => mem.DATAB +in_data[65] => mem.DATAB +in_data[65] => mem.DATAB +in_data[65] => mem.DATAB +in_data[65] => mem.DATAB +in_data[65] => mem.DATAB +in_data[65] => mem.DATAB +in_data[66] => mem.DATAB +in_data[66] => mem.DATAB +in_data[66] => mem.DATAB +in_data[66] => mem.DATAB +in_data[66] => mem.DATAB +in_data[66] => mem.DATAB +in_data[66] => mem.DATAB +in_data[67] => mem.DATAB +in_data[67] => mem.DATAB +in_data[67] => mem.DATAB +in_data[67] => mem.DATAB +in_data[67] => mem.DATAB +in_data[67] => mem.DATAB +in_data[67] => mem.DATAB +in_data[68] => mem.DATAB +in_data[68] => mem.DATAB +in_data[68] => mem.DATAB +in_data[68] => mem.DATAB +in_data[68] => mem.DATAB +in_data[68] => mem.DATAB +in_data[68] => mem.DATAB +in_data[69] => mem.DATAB +in_data[69] => mem.DATAB +in_data[69] => mem.DATAB +in_data[69] => mem.DATAB +in_data[69] => mem.DATAB +in_data[69] => mem.DATAB +in_data[69] => mem.DATAB +in_data[70] => mem.DATAB +in_data[70] => mem.DATAB +in_data[70] => mem.DATAB +in_data[70] => mem.DATAB +in_data[70] => mem.DATAB +in_data[70] => mem.DATAB +in_data[70] => mem.DATAB +in_data[71] => mem.DATAB +in_data[71] => mem.DATAB +in_data[71] => mem.DATAB +in_data[71] => mem.DATAB +in_data[71] => mem.DATAB +in_data[71] => mem.DATAB +in_data[71] => mem.DATAB +in_data[72] => mem.DATAB +in_data[72] => mem.DATAB +in_data[72] => mem.DATAB +in_data[72] => mem.DATAB +in_data[72] => mem.DATAB +in_data[72] => mem.DATAB +in_data[72] => mem.DATAB +in_data[73] => mem.DATAB +in_data[73] => mem.DATAB +in_data[73] => mem.DATAB +in_data[73] => mem.DATAB +in_data[73] => mem.DATAB +in_data[73] => mem.DATAB +in_data[73] => mem.DATAB +in_data[74] => mem.DATAB +in_data[74] => mem.DATAB +in_data[74] => mem.DATAB +in_data[74] => mem.DATAB +in_data[74] => mem.DATAB +in_data[74] => mem.DATAB +in_data[74] => mem.DATAB +in_data[75] => mem.DATAB +in_data[75] => mem.DATAB +in_data[75] => mem.DATAB +in_data[75] => mem.DATAB +in_data[75] => mem.DATAB +in_data[75] => mem.DATAB +in_data[75] => mem.DATAB +in_data[76] => mem.DATAB +in_data[76] => mem.DATAB +in_data[76] => mem.DATAB +in_data[76] => mem.DATAB +in_data[76] => mem.DATAB +in_data[76] => mem.DATAB +in_data[76] => mem.DATAB +in_data[77] => mem.DATAB +in_data[77] => mem.DATAB +in_data[77] => mem.DATAB +in_data[77] => mem.DATAB +in_data[77] => mem.DATAB +in_data[77] => mem.DATAB +in_data[77] => mem.DATAB +in_data[78] => mem.DATAB +in_data[78] => mem.DATAB +in_data[78] => mem.DATAB +in_data[78] => mem.DATAB +in_data[78] => mem.DATAB +in_data[78] => mem.DATAB +in_data[78] => mem.DATAB +in_data[79] => mem.DATAB +in_data[79] => mem.DATAB +in_data[79] => mem.DATAB +in_data[79] => mem.DATAB +in_data[79] => mem.DATAB +in_data[79] => mem.DATAB +in_data[79] => mem.DATAB +in_data[80] => mem.DATAB +in_data[80] => mem.DATAB +in_data[80] => mem.DATAB +in_data[80] => mem.DATAB +in_data[80] => mem.DATAB +in_data[80] => mem.DATAB +in_data[80] => mem.DATAB +in_data[81] => mem.DATAB +in_data[81] => mem.DATAB +in_data[81] => mem.DATAB +in_data[81] => mem.DATAB +in_data[81] => mem.DATAB +in_data[81] => mem.DATAB +in_data[81] => mem.DATAB +in_data[82] => mem.DATAB +in_data[82] => mem.DATAB +in_data[82] => mem.DATAB +in_data[82] => mem.DATAB +in_data[82] => mem.DATAB +in_data[82] => mem.DATAB +in_data[82] => mem.DATAB +in_data[83] => mem.DATAB +in_data[83] => mem.DATAB +in_data[83] => mem.DATAB +in_data[83] => mem.DATAB +in_data[83] => mem.DATAB +in_data[83] => mem.DATAB +in_data[83] => mem.DATAB +in_valid => write.IN1 +in_startofpacket => mem.DATAB +in_startofpacket => mem.DATAB +in_startofpacket => mem.DATAB +in_startofpacket => mem.DATAB +in_startofpacket => mem.DATAB +in_startofpacket => mem.DATAB +in_startofpacket => mem.DATAB +in_endofpacket => mem.DATAB +in_endofpacket => mem.DATAB +in_endofpacket => mem.DATAB +in_endofpacket => mem.DATAB +in_endofpacket => mem.DATAB +in_endofpacket => mem.DATAB +in_endofpacket => mem.DATAB +in_empty[0] => ~NO_FANOUT~ +in_error[0] => out_error[0].DATAIN +in_error[0] => out_empty[0].DATAIN +in_channel[0] => out_channel[0].DATAIN +in_ready <= mem_used[7].DB_MAX_OUTPUT_PORT_TYPE +out_data[0] <= mem[0][0].DB_MAX_OUTPUT_PORT_TYPE +out_data[1] <= mem[0][1].DB_MAX_OUTPUT_PORT_TYPE +out_data[2] <= mem[0][2].DB_MAX_OUTPUT_PORT_TYPE +out_data[3] <= mem[0][3].DB_MAX_OUTPUT_PORT_TYPE +out_data[4] <= mem[0][4].DB_MAX_OUTPUT_PORT_TYPE +out_data[5] <= mem[0][5].DB_MAX_OUTPUT_PORT_TYPE +out_data[6] <= mem[0][6].DB_MAX_OUTPUT_PORT_TYPE +out_data[7] <= mem[0][7].DB_MAX_OUTPUT_PORT_TYPE +out_data[8] <= mem[0][8].DB_MAX_OUTPUT_PORT_TYPE +out_data[9] <= mem[0][9].DB_MAX_OUTPUT_PORT_TYPE +out_data[10] <= mem[0][10].DB_MAX_OUTPUT_PORT_TYPE +out_data[11] <= mem[0][11].DB_MAX_OUTPUT_PORT_TYPE +out_data[12] <= mem[0][12].DB_MAX_OUTPUT_PORT_TYPE +out_data[13] <= mem[0][13].DB_MAX_OUTPUT_PORT_TYPE +out_data[14] <= mem[0][14].DB_MAX_OUTPUT_PORT_TYPE +out_data[15] <= mem[0][15].DB_MAX_OUTPUT_PORT_TYPE +out_data[16] <= mem[0][16].DB_MAX_OUTPUT_PORT_TYPE +out_data[17] <= mem[0][17].DB_MAX_OUTPUT_PORT_TYPE +out_data[18] <= mem[0][18].DB_MAX_OUTPUT_PORT_TYPE +out_data[19] <= mem[0][19].DB_MAX_OUTPUT_PORT_TYPE +out_data[20] <= mem[0][20].DB_MAX_OUTPUT_PORT_TYPE +out_data[21] <= mem[0][21].DB_MAX_OUTPUT_PORT_TYPE +out_data[22] <= mem[0][22].DB_MAX_OUTPUT_PORT_TYPE +out_data[23] <= mem[0][23].DB_MAX_OUTPUT_PORT_TYPE +out_data[24] <= mem[0][24].DB_MAX_OUTPUT_PORT_TYPE +out_data[25] <= mem[0][25].DB_MAX_OUTPUT_PORT_TYPE +out_data[26] <= mem[0][26].DB_MAX_OUTPUT_PORT_TYPE +out_data[27] <= mem[0][27].DB_MAX_OUTPUT_PORT_TYPE +out_data[28] <= mem[0][28].DB_MAX_OUTPUT_PORT_TYPE +out_data[29] <= mem[0][29].DB_MAX_OUTPUT_PORT_TYPE +out_data[30] <= mem[0][30].DB_MAX_OUTPUT_PORT_TYPE +out_data[31] <= mem[0][31].DB_MAX_OUTPUT_PORT_TYPE +out_data[32] <= mem[0][32].DB_MAX_OUTPUT_PORT_TYPE +out_data[33] <= mem[0][33].DB_MAX_OUTPUT_PORT_TYPE +out_data[34] <= mem[0][34].DB_MAX_OUTPUT_PORT_TYPE +out_data[35] <= mem[0][35].DB_MAX_OUTPUT_PORT_TYPE +out_data[36] <= mem[0][36].DB_MAX_OUTPUT_PORT_TYPE +out_data[37] <= mem[0][37].DB_MAX_OUTPUT_PORT_TYPE +out_data[38] <= mem[0][38].DB_MAX_OUTPUT_PORT_TYPE +out_data[39] <= mem[0][39].DB_MAX_OUTPUT_PORT_TYPE +out_data[40] <= mem[0][40].DB_MAX_OUTPUT_PORT_TYPE +out_data[41] <= mem[0][41].DB_MAX_OUTPUT_PORT_TYPE +out_data[42] <= mem[0][42].DB_MAX_OUTPUT_PORT_TYPE +out_data[43] <= mem[0][43].DB_MAX_OUTPUT_PORT_TYPE +out_data[44] <= mem[0][44].DB_MAX_OUTPUT_PORT_TYPE +out_data[45] <= mem[0][45].DB_MAX_OUTPUT_PORT_TYPE +out_data[46] <= mem[0][46].DB_MAX_OUTPUT_PORT_TYPE +out_data[47] <= mem[0][47].DB_MAX_OUTPUT_PORT_TYPE +out_data[48] <= mem[0][48].DB_MAX_OUTPUT_PORT_TYPE +out_data[49] <= mem[0][49].DB_MAX_OUTPUT_PORT_TYPE +out_data[50] <= mem[0][50].DB_MAX_OUTPUT_PORT_TYPE +out_data[51] <= mem[0][51].DB_MAX_OUTPUT_PORT_TYPE +out_data[52] <= mem[0][52].DB_MAX_OUTPUT_PORT_TYPE +out_data[53] <= mem[0][53].DB_MAX_OUTPUT_PORT_TYPE +out_data[54] <= mem[0][54].DB_MAX_OUTPUT_PORT_TYPE +out_data[55] <= mem[0][55].DB_MAX_OUTPUT_PORT_TYPE +out_data[56] <= mem[0][56].DB_MAX_OUTPUT_PORT_TYPE +out_data[57] <= mem[0][57].DB_MAX_OUTPUT_PORT_TYPE +out_data[58] <= mem[0][58].DB_MAX_OUTPUT_PORT_TYPE +out_data[59] <= mem[0][59].DB_MAX_OUTPUT_PORT_TYPE +out_data[60] <= mem[0][60].DB_MAX_OUTPUT_PORT_TYPE +out_data[61] <= mem[0][61].DB_MAX_OUTPUT_PORT_TYPE +out_data[62] <= mem[0][62].DB_MAX_OUTPUT_PORT_TYPE +out_data[63] <= mem[0][63].DB_MAX_OUTPUT_PORT_TYPE +out_data[64] <= mem[0][64].DB_MAX_OUTPUT_PORT_TYPE +out_data[65] <= mem[0][65].DB_MAX_OUTPUT_PORT_TYPE +out_data[66] <= mem[0][66].DB_MAX_OUTPUT_PORT_TYPE +out_data[67] <= mem[0][67].DB_MAX_OUTPUT_PORT_TYPE +out_data[68] <= mem[0][68].DB_MAX_OUTPUT_PORT_TYPE +out_data[69] <= mem[0][69].DB_MAX_OUTPUT_PORT_TYPE +out_data[70] <= mem[0][70].DB_MAX_OUTPUT_PORT_TYPE +out_data[71] <= mem[0][71].DB_MAX_OUTPUT_PORT_TYPE +out_data[72] <= mem[0][72].DB_MAX_OUTPUT_PORT_TYPE +out_data[73] <= mem[0][73].DB_MAX_OUTPUT_PORT_TYPE +out_data[74] <= mem[0][74].DB_MAX_OUTPUT_PORT_TYPE +out_data[75] <= mem[0][75].DB_MAX_OUTPUT_PORT_TYPE +out_data[76] <= mem[0][76].DB_MAX_OUTPUT_PORT_TYPE +out_data[77] <= mem[0][77].DB_MAX_OUTPUT_PORT_TYPE +out_data[78] <= mem[0][78].DB_MAX_OUTPUT_PORT_TYPE +out_data[79] <= mem[0][79].DB_MAX_OUTPUT_PORT_TYPE +out_data[80] <= mem[0][80].DB_MAX_OUTPUT_PORT_TYPE +out_data[81] <= mem[0][81].DB_MAX_OUTPUT_PORT_TYPE +out_data[82] <= mem[0][82].DB_MAX_OUTPUT_PORT_TYPE +out_data[83] <= mem[0][83].DB_MAX_OUTPUT_PORT_TYPE +out_valid <= mem_used[0].DB_MAX_OUTPUT_PORT_TYPE +out_startofpacket <= mem[0][85].DB_MAX_OUTPUT_PORT_TYPE +out_endofpacket <= mem[0][84].DB_MAX_OUTPUT_PORT_TYPE +out_empty[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE +out_error[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE +out_channel[0] <= in_channel[0].DB_MAX_OUTPUT_PORT_TYPE +out_ready => internal_out_ready.IN1 +csr_address[0] => ~NO_FANOUT~ +csr_address[1] => ~NO_FANOUT~ +csr_write => ~NO_FANOUT~ +csr_read => csr_readdata[0]~reg0.ENA +csr_read => csr_readdata[31]~reg0.ENA +csr_read => csr_readdata[30]~reg0.ENA +csr_read => csr_readdata[29]~reg0.ENA +csr_read => csr_readdata[28]~reg0.ENA +csr_read => csr_readdata[27]~reg0.ENA +csr_read => csr_readdata[26]~reg0.ENA +csr_read => csr_readdata[25]~reg0.ENA +csr_read => csr_readdata[24]~reg0.ENA +csr_read => csr_readdata[23]~reg0.ENA +csr_read => csr_readdata[22]~reg0.ENA +csr_read => csr_readdata[21]~reg0.ENA +csr_read => csr_readdata[20]~reg0.ENA +csr_read => csr_readdata[19]~reg0.ENA +csr_read => csr_readdata[18]~reg0.ENA +csr_read => csr_readdata[17]~reg0.ENA +csr_read => csr_readdata[16]~reg0.ENA +csr_read => csr_readdata[15]~reg0.ENA +csr_read => csr_readdata[14]~reg0.ENA +csr_read => csr_readdata[13]~reg0.ENA +csr_read => csr_readdata[12]~reg0.ENA +csr_read => csr_readdata[11]~reg0.ENA +csr_read => csr_readdata[10]~reg0.ENA +csr_read => csr_readdata[9]~reg0.ENA +csr_read => csr_readdata[8]~reg0.ENA +csr_read => csr_readdata[7]~reg0.ENA +csr_read => csr_readdata[6]~reg0.ENA +csr_read => csr_readdata[5]~reg0.ENA +csr_read => csr_readdata[4]~reg0.ENA +csr_read => csr_readdata[3]~reg0.ENA +csr_read => csr_readdata[2]~reg0.ENA +csr_read => csr_readdata[1]~reg0.ENA +csr_writedata[0] => ~NO_FANOUT~ +csr_writedata[1] => ~NO_FANOUT~ +csr_writedata[2] => ~NO_FANOUT~ +csr_writedata[3] => ~NO_FANOUT~ +csr_writedata[4] => ~NO_FANOUT~ +csr_writedata[5] => ~NO_FANOUT~ +csr_writedata[6] => ~NO_FANOUT~ +csr_writedata[7] => ~NO_FANOUT~ +csr_writedata[8] => ~NO_FANOUT~ +csr_writedata[9] => ~NO_FANOUT~ +csr_writedata[10] => ~NO_FANOUT~ +csr_writedata[11] => ~NO_FANOUT~ +csr_writedata[12] => ~NO_FANOUT~ +csr_writedata[13] => ~NO_FANOUT~ +csr_writedata[14] => ~NO_FANOUT~ +csr_writedata[15] => ~NO_FANOUT~ +csr_writedata[16] => ~NO_FANOUT~ +csr_writedata[17] => ~NO_FANOUT~ +csr_writedata[18] => ~NO_FANOUT~ +csr_writedata[19] => ~NO_FANOUT~ +csr_writedata[20] => ~NO_FANOUT~ +csr_writedata[21] => ~NO_FANOUT~ +csr_writedata[22] => ~NO_FANOUT~ +csr_writedata[23] => ~NO_FANOUT~ +csr_writedata[24] => ~NO_FANOUT~ +csr_writedata[25] => ~NO_FANOUT~ +csr_writedata[26] => ~NO_FANOUT~ +csr_writedata[27] => ~NO_FANOUT~ +csr_writedata[28] => ~NO_FANOUT~ +csr_writedata[29] => ~NO_FANOUT~ +csr_writedata[30] => ~NO_FANOUT~ +csr_writedata[31] => ~NO_FANOUT~ +csr_readdata[0] <= csr_readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[1] <= csr_readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[2] <= csr_readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[3] <= csr_readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[4] <= csr_readdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[5] <= csr_readdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[6] <= csr_readdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[7] <= csr_readdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[8] <= csr_readdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[9] <= csr_readdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[10] <= csr_readdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[11] <= csr_readdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[12] <= csr_readdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[13] <= csr_readdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[14] <= csr_readdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[15] <= csr_readdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[16] <= csr_readdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[17] <= csr_readdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[18] <= csr_readdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[19] <= csr_readdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[20] <= csr_readdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[21] <= csr_readdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[22] <= csr_readdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[23] <= csr_readdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[24] <= csr_readdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[25] <= csr_readdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[26] <= csr_readdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[27] <= csr_readdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[28] <= csr_readdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[29] <= csr_readdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[30] <= csr_readdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[31] <= csr_readdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE +almost_full_data <= +almost_empty_data <= + + +|de0_nano_system|system:inst_cpu|altera_merlin_slave_agent:sysid_control_slave_translator_avalon_universal_slave_0_agent +clk => clk.IN1 +reset => reset.IN1 +m0_address[0] <= +m0_address[1] <= +m0_address[2] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE +m0_address[3] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE +m0_address[4] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE +m0_address[5] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE +m0_address[6] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE +m0_address[7] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE +m0_address[8] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE +m0_address[9] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE +m0_address[10] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE +m0_address[11] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE +m0_address[12] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE +m0_address[13] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE +m0_address[14] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE +m0_address[15] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE +m0_address[16] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE +m0_address[17] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE +m0_address[18] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE +m0_address[19] <= cp_data[55].DB_MAX_OUTPUT_PORT_TYPE +m0_address[20] <= cp_data[56].DB_MAX_OUTPUT_PORT_TYPE +m0_address[21] <= cp_data[57].DB_MAX_OUTPUT_PORT_TYPE +m0_address[22] <= cp_data[58].DB_MAX_OUTPUT_PORT_TYPE +m0_address[23] <= cp_data[59].DB_MAX_OUTPUT_PORT_TYPE +m0_address[24] <= cp_data[60].DB_MAX_OUTPUT_PORT_TYPE +m0_address[25] <= cp_data[61].DB_MAX_OUTPUT_PORT_TYPE +m0_burstcount[0] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE +m0_burstcount[1] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE +m0_burstcount[2] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[0] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[1] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[2] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[3] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE +m0_read <= m0_read.DB_MAX_OUTPUT_PORT_TYPE +m0_readdata[0] => rdata_fifo_src_data[0].DATAIN +m0_readdata[1] => rdata_fifo_src_data[1].DATAIN +m0_readdata[2] => rdata_fifo_src_data[2].DATAIN +m0_readdata[3] => rdata_fifo_src_data[3].DATAIN +m0_readdata[4] => rdata_fifo_src_data[4].DATAIN +m0_readdata[5] => rdata_fifo_src_data[5].DATAIN +m0_readdata[6] => rdata_fifo_src_data[6].DATAIN +m0_readdata[7] => rdata_fifo_src_data[7].DATAIN +m0_readdata[8] => rdata_fifo_src_data[8].DATAIN +m0_readdata[9] => rdata_fifo_src_data[9].DATAIN +m0_readdata[10] => rdata_fifo_src_data[10].DATAIN +m0_readdata[11] => rdata_fifo_src_data[11].DATAIN +m0_readdata[12] => rdata_fifo_src_data[12].DATAIN +m0_readdata[13] => rdata_fifo_src_data[13].DATAIN +m0_readdata[14] => rdata_fifo_src_data[14].DATAIN +m0_readdata[15] => rdata_fifo_src_data[15].DATAIN +m0_readdata[16] => rdata_fifo_src_data[16].DATAIN +m0_readdata[17] => rdata_fifo_src_data[17].DATAIN +m0_readdata[18] => rdata_fifo_src_data[18].DATAIN +m0_readdata[19] => rdata_fifo_src_data[19].DATAIN +m0_readdata[20] => rdata_fifo_src_data[20].DATAIN +m0_readdata[21] => rdata_fifo_src_data[21].DATAIN +m0_readdata[22] => rdata_fifo_src_data[22].DATAIN +m0_readdata[23] => rdata_fifo_src_data[23].DATAIN +m0_readdata[24] => rdata_fifo_src_data[24].DATAIN +m0_readdata[25] => rdata_fifo_src_data[25].DATAIN +m0_readdata[26] => rdata_fifo_src_data[26].DATAIN +m0_readdata[27] => rdata_fifo_src_data[27].DATAIN +m0_readdata[28] => rdata_fifo_src_data[28].DATAIN +m0_readdata[29] => rdata_fifo_src_data[29].DATAIN +m0_readdata[30] => rdata_fifo_src_data[30].DATAIN +m0_readdata[31] => rdata_fifo_src_data[31].DATAIN +m0_waitrequest => cp_ready.IN0 +m0_write <= m0_write.DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[0] <= cp_data[0].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[1] <= cp_data[1].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[2] <= cp_data[2].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[3] <= cp_data[3].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[4] <= cp_data[4].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[5] <= cp_data[5].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[6] <= cp_data[6].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[7] <= cp_data[7].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[8] <= cp_data[8].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[9] <= cp_data[9].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[10] <= cp_data[10].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[11] <= cp_data[11].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[12] <= cp_data[12].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[13] <= cp_data[13].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[14] <= cp_data[14].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[15] <= cp_data[15].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[16] <= cp_data[16].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[17] <= cp_data[17].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[18] <= cp_data[18].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[19] <= cp_data[19].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[20] <= cp_data[20].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[21] <= cp_data[21].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[22] <= cp_data[22].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[23] <= cp_data[23].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[24] <= cp_data[24].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[25] <= cp_data[25].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[26] <= cp_data[26].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[27] <= cp_data[27].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[28] <= cp_data[28].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[29] <= cp_data[29].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[30] <= cp_data[30].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[31] <= cp_data[31].DB_MAX_OUTPUT_PORT_TYPE +m0_readdatavalid => rdata_fifo_src_valid.DATAIN +m0_debugaccess <= cp_data[92].DB_MAX_OUTPUT_PORT_TYPE +m0_lock <= m0_lock.DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[0] <= +rf_source_data[1] <= +rf_source_data[2] <= +rf_source_data[3] <= +rf_source_data[4] <= +rf_source_data[5] <= +rf_source_data[6] <= +rf_source_data[7] <= +rf_source_data[8] <= +rf_source_data[9] <= +rf_source_data[10] <= +rf_source_data[11] <= +rf_source_data[12] <= +rf_source_data[13] <= +rf_source_data[14] <= +rf_source_data[15] <= +rf_source_data[16] <= +rf_source_data[17] <= +rf_source_data[18] <= +rf_source_data[19] <= +rf_source_data[20] <= +rf_source_data[21] <= +rf_source_data[22] <= +rf_source_data[23] <= +rf_source_data[24] <= +rf_source_data[25] <= +rf_source_data[26] <= +rf_source_data[27] <= +rf_source_data[28] <= +rf_source_data[29] <= +rf_source_data[30] <= +rf_source_data[31] <= +rf_source_data[32] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[33] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[34] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[35] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[36] <= cp_data[36].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[37] <= cp_data[37].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[38] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[39] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[40] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[41] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[42] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[43] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[44] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[45] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[46] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[47] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[48] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[49] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[50] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[51] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[52] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[53] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[54] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[55] <= cp_data[55].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[56] <= cp_data[56].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[57] <= cp_data[57].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[58] <= cp_data[58].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[59] <= cp_data[59].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[60] <= cp_data[60].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[61] <= cp_data[61].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[62] <= cp_data[62].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[63] <= cp_data[63].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[64] <= cp_data[64].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[65] <= cp_data[65].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[66] <= cp_data[66].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[67] <= cp_data[67].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[68] <= cp_data[68].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[69] <= cp_data[69].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[70] <= cp_data[70].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[71] <= cp_data[71].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[72] <= cp_data[72].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[73] <= cp_data[73].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[74] <= cp_data[74].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[75] <= cp_data[75].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[76] <= cp_data[76].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[77] <= cp_data[77].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[78] <= cp_data[78].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[79] <= cp_data[79].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[80] <= cp_data[80].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[81] <= cp_data[81].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[82] <= cp_data[82].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[83] <= cp_data[83].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[84] <= cp_data[84].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[85] <= cp_data[85].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[86] <= cp_data[86].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[87] <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[88] <= cp_data[88].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[89] <= cp_data[89].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[90] <= cp_data[90].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[91] <= cp_data[91].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[92] <= cp_data[92].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[93] <= +rf_source_data[94] <= +rf_source_data[95] <= cp_data[95].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[96] <= cp_data[96].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[97] <= cp_data[97].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[98] <= cp_data[98].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[99] <= cp_data[99].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[100] <= cp_data[100].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[101] <= nonposted_write_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +rf_source_valid <= rf_source_valid.DB_MAX_OUTPUT_PORT_TYPE +rf_source_startofpacket <= cp_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +rf_source_endofpacket <= cp_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +rf_source_ready => cp_ready.IN1 +rf_source_ready => m0_write.IN1 +rf_source_ready => m0_lock.IN1 +rf_source_ready => rf_source_valid.IN1 +rf_source_ready => m0_read.IN1 +rf_sink_data[0] => ~NO_FANOUT~ +rf_sink_data[1] => ~NO_FANOUT~ +rf_sink_data[2] => ~NO_FANOUT~ +rf_sink_data[3] => ~NO_FANOUT~ +rf_sink_data[4] => ~NO_FANOUT~ +rf_sink_data[5] => ~NO_FANOUT~ +rf_sink_data[6] => ~NO_FANOUT~ +rf_sink_data[7] => ~NO_FANOUT~ +rf_sink_data[8] => ~NO_FANOUT~ +rf_sink_data[9] => ~NO_FANOUT~ +rf_sink_data[10] => ~NO_FANOUT~ +rf_sink_data[11] => ~NO_FANOUT~ +rf_sink_data[12] => ~NO_FANOUT~ +rf_sink_data[13] => ~NO_FANOUT~ +rf_sink_data[14] => ~NO_FANOUT~ +rf_sink_data[15] => ~NO_FANOUT~ +rf_sink_data[16] => ~NO_FANOUT~ +rf_sink_data[17] => ~NO_FANOUT~ +rf_sink_data[18] => ~NO_FANOUT~ +rf_sink_data[19] => ~NO_FANOUT~ +rf_sink_data[20] => ~NO_FANOUT~ +rf_sink_data[21] => ~NO_FANOUT~ +rf_sink_data[22] => ~NO_FANOUT~ +rf_sink_data[23] => ~NO_FANOUT~ +rf_sink_data[24] => ~NO_FANOUT~ +rf_sink_data[25] => ~NO_FANOUT~ +rf_sink_data[26] => ~NO_FANOUT~ +rf_sink_data[27] => ~NO_FANOUT~ +rf_sink_data[28] => ~NO_FANOUT~ +rf_sink_data[29] => ~NO_FANOUT~ +rf_sink_data[30] => ~NO_FANOUT~ +rf_sink_data[31] => ~NO_FANOUT~ +rf_sink_data[32] => rp_data[32].DATAIN +rf_sink_data[33] => rp_data[33].DATAIN +rf_sink_data[34] => rp_data[34].DATAIN +rf_sink_data[35] => rp_data[35].DATAIN +rf_sink_data[36] => rf_sink_addr[0].IN1 +rf_sink_data[37] => rf_sink_addr[1].IN1 +rf_sink_data[38] => rf_sink_addr[2].IN1 +rf_sink_data[39] => rf_sink_addr[3].IN1 +rf_sink_data[40] => rf_sink_addr[4].IN1 +rf_sink_data[41] => rf_sink_addr[5].IN1 +rf_sink_data[42] => rf_sink_addr[6].IN1 +rf_sink_data[43] => rf_sink_addr[7].IN1 +rf_sink_data[44] => rf_sink_addr[8].IN1 +rf_sink_data[45] => rf_sink_addr[9].IN1 +rf_sink_data[46] => rf_sink_addr[10].IN1 +rf_sink_data[47] => rf_sink_addr[11].IN1 +rf_sink_data[48] => rf_sink_addr[12].IN1 +rf_sink_data[49] => rf_sink_addr[13].IN1 +rf_sink_data[50] => rf_sink_addr[14].IN1 +rf_sink_data[51] => rf_sink_addr[15].IN1 +rf_sink_data[52] => rf_sink_addr[16].IN1 +rf_sink_data[53] => rf_sink_addr[17].IN1 +rf_sink_data[54] => rf_sink_addr[18].IN1 +rf_sink_data[55] => rf_sink_addr[19].IN1 +rf_sink_data[56] => rf_sink_addr[20].IN1 +rf_sink_data[57] => rf_sink_addr[21].IN1 +rf_sink_data[58] => rf_sink_addr[22].IN1 +rf_sink_data[59] => rf_sink_addr[23].IN1 +rf_sink_data[60] => rf_sink_addr[24].IN1 +rf_sink_data[61] => rf_sink_addr[25].IN1 +rf_sink_data[62] => rf_sink_compressed.IN1 +rf_sink_data[63] => rp_data[63].DATAIN +rf_sink_data[64] => comb.OUTPUTSELECT +rf_sink_data[64] => rp_data[64].DATAIN +rf_sink_data[65] => rp_data.IN0 +rf_sink_data[66] => rp_data[66].DATAIN +rf_sink_data[67] => rp_data[67].DATAIN +rf_sink_data[68] => rf_sink_byte_cnt[0].IN1 +rf_sink_data[69] => rf_sink_byte_cnt[1].IN1 +rf_sink_data[70] => rf_sink_byte_cnt[2].IN1 +rf_sink_data[71] => rf_sink_burstwrap[0].IN1 +rf_sink_data[72] => rf_sink_burstwrap[1].IN1 +rf_sink_data[73] => rf_sink_burstwrap[2].IN1 +rf_sink_data[74] => rf_sink_burstsize[0].IN1 +rf_sink_data[75] => rf_sink_burstsize[1].IN1 +rf_sink_data[76] => rf_sink_burstsize[2].IN1 +rf_sink_data[77] => rp_data[77].DATAIN +rf_sink_data[78] => rp_data[78].DATAIN +rf_sink_data[79] => rp_data[79].DATAIN +rf_sink_data[80] => rp_data[80].DATAIN +rf_sink_data[81] => rp_data[81].DATAIN +rf_sink_data[82] => rp_data[82].DATAIN +rf_sink_data[83] => rp_data[87].DATAIN +rf_sink_data[84] => rp_data[88].DATAIN +rf_sink_data[85] => rp_data[89].DATAIN +rf_sink_data[86] => rp_data[90].DATAIN +rf_sink_data[87] => rp_data[83].DATAIN +rf_sink_data[88] => rp_data[84].DATAIN +rf_sink_data[89] => rp_data[85].DATAIN +rf_sink_data[90] => rp_data[86].DATAIN +rf_sink_data[91] => rp_data[91].DATAIN +rf_sink_data[92] => rp_data[92].DATAIN +rf_sink_data[93] => rp_data[93].DATAIN +rf_sink_data[94] => rp_data[94].DATAIN +rf_sink_data[95] => rp_data[95].DATAIN +rf_sink_data[96] => rp_data[96].DATAIN +rf_sink_data[97] => rp_data[97].DATAIN +rf_sink_data[98] => rp_data[98].DATAIN +rf_sink_data[99] => ~NO_FANOUT~ +rf_sink_data[100] => ~NO_FANOUT~ +rf_sink_data[101] => rdata_fifo_sink_ready.IN0 +rf_sink_data[101] => comb.IN0 +rf_sink_valid => rdata_fifo_sink_ready.IN1 +rf_sink_valid => comb.IN1 +rf_sink_startofpacket => comb.DATAA +rf_sink_endofpacket => rf_sink_endofpacket.IN1 +rf_sink_ready <= altera_merlin_burst_uncompressor:uncompressor.sink_ready +rdata_fifo_src_data[0] <= m0_readdata[0].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[1] <= m0_readdata[1].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[2] <= m0_readdata[2].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[3] <= m0_readdata[3].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[4] <= m0_readdata[4].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[5] <= m0_readdata[5].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[6] <= m0_readdata[6].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[7] <= m0_readdata[7].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[8] <= m0_readdata[8].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[9] <= m0_readdata[9].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[10] <= m0_readdata[10].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[11] <= m0_readdata[11].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[12] <= m0_readdata[12].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[13] <= m0_readdata[13].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[14] <= m0_readdata[14].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[15] <= m0_readdata[15].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[16] <= m0_readdata[16].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[17] <= m0_readdata[17].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[18] <= m0_readdata[18].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[19] <= m0_readdata[19].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[20] <= m0_readdata[20].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[21] <= m0_readdata[21].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[22] <= m0_readdata[22].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[23] <= m0_readdata[23].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[24] <= m0_readdata[24].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[25] <= m0_readdata[25].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[26] <= m0_readdata[26].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[27] <= m0_readdata[27].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[28] <= m0_readdata[28].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[29] <= m0_readdata[29].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[30] <= m0_readdata[30].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[31] <= m0_readdata[31].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_valid <= m0_readdatavalid.DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_ready => ~NO_FANOUT~ +rdata_fifo_sink_data[0] => rp_data[0].DATAIN +rdata_fifo_sink_data[1] => rp_data[1].DATAIN +rdata_fifo_sink_data[2] => rp_data[2].DATAIN +rdata_fifo_sink_data[3] => rp_data[3].DATAIN +rdata_fifo_sink_data[4] => rp_data[4].DATAIN +rdata_fifo_sink_data[5] => rp_data[5].DATAIN +rdata_fifo_sink_data[6] => rp_data[6].DATAIN +rdata_fifo_sink_data[7] => rp_data[7].DATAIN +rdata_fifo_sink_data[8] => rp_data[8].DATAIN +rdata_fifo_sink_data[9] => rp_data[9].DATAIN +rdata_fifo_sink_data[10] => rp_data[10].DATAIN +rdata_fifo_sink_data[11] => rp_data[11].DATAIN +rdata_fifo_sink_data[12] => rp_data[12].DATAIN +rdata_fifo_sink_data[13] => rp_data[13].DATAIN +rdata_fifo_sink_data[14] => rp_data[14].DATAIN +rdata_fifo_sink_data[15] => rp_data[15].DATAIN +rdata_fifo_sink_data[16] => rp_data[16].DATAIN +rdata_fifo_sink_data[17] => rp_data[17].DATAIN +rdata_fifo_sink_data[18] => rp_data[18].DATAIN +rdata_fifo_sink_data[19] => rp_data[19].DATAIN +rdata_fifo_sink_data[20] => rp_data[20].DATAIN +rdata_fifo_sink_data[21] => rp_data[21].DATAIN +rdata_fifo_sink_data[22] => rp_data[22].DATAIN +rdata_fifo_sink_data[23] => rp_data[23].DATAIN +rdata_fifo_sink_data[24] => rp_data[24].DATAIN +rdata_fifo_sink_data[25] => rp_data[25].DATAIN +rdata_fifo_sink_data[26] => rp_data[26].DATAIN +rdata_fifo_sink_data[27] => rp_data[27].DATAIN +rdata_fifo_sink_data[28] => rp_data[28].DATAIN +rdata_fifo_sink_data[29] => rp_data[29].DATAIN +rdata_fifo_sink_data[30] => rp_data[30].DATAIN +rdata_fifo_sink_data[31] => rp_data[31].DATAIN +rdata_fifo_sink_valid => rp_valid.IN1 +rdata_fifo_sink_valid => rdata_fifo_sink_ready.IN0 +rdata_fifo_sink_valid => comb.IN1 +rdata_fifo_sink_ready <= rdata_fifo_sink_ready.DB_MAX_OUTPUT_PORT_TYPE +cp_ready <= cp_ready.DB_MAX_OUTPUT_PORT_TYPE +cp_valid => local_lock.IN0 +cp_valid => local_write.IN0 +cp_valid => local_read.IN0 +cp_valid => local_compressed_read.IN0 +cp_data[0] => m0_writedata[0].DATAIN +cp_data[1] => m0_writedata[1].DATAIN +cp_data[2] => m0_writedata[2].DATAIN +cp_data[3] => m0_writedata[3].DATAIN +cp_data[4] => m0_writedata[4].DATAIN +cp_data[5] => m0_writedata[5].DATAIN +cp_data[6] => m0_writedata[6].DATAIN +cp_data[7] => m0_writedata[7].DATAIN +cp_data[8] => m0_writedata[8].DATAIN +cp_data[9] => m0_writedata[9].DATAIN +cp_data[10] => m0_writedata[10].DATAIN +cp_data[11] => m0_writedata[11].DATAIN +cp_data[12] => m0_writedata[12].DATAIN +cp_data[13] => m0_writedata[13].DATAIN +cp_data[14] => m0_writedata[14].DATAIN +cp_data[15] => m0_writedata[15].DATAIN +cp_data[16] => m0_writedata[16].DATAIN +cp_data[17] => m0_writedata[17].DATAIN +cp_data[18] => m0_writedata[18].DATAIN +cp_data[19] => m0_writedata[19].DATAIN +cp_data[20] => m0_writedata[20].DATAIN +cp_data[21] => m0_writedata[21].DATAIN +cp_data[22] => m0_writedata[22].DATAIN +cp_data[23] => m0_writedata[23].DATAIN +cp_data[24] => m0_writedata[24].DATAIN +cp_data[25] => m0_writedata[25].DATAIN +cp_data[26] => m0_writedata[26].DATAIN +cp_data[27] => m0_writedata[27].DATAIN +cp_data[28] => m0_writedata[28].DATAIN +cp_data[29] => m0_writedata[29].DATAIN +cp_data[30] => m0_writedata[30].DATAIN +cp_data[31] => m0_writedata[31].DATAIN +cp_data[32] => rf_source_data[32].DATAIN +cp_data[32] => m0_byteenable[0].DATAIN +cp_data[33] => rf_source_data[33].DATAIN +cp_data[33] => m0_byteenable[1].DATAIN +cp_data[34] => rf_source_data[34].DATAIN +cp_data[34] => m0_byteenable[2].DATAIN +cp_data[35] => rf_source_data[35].DATAIN +cp_data[35] => m0_byteenable[3].DATAIN +cp_data[36] => rf_source_data[36].DATAIN +cp_data[37] => rf_source_data[37].DATAIN +cp_data[38] => rf_source_data[38].DATAIN +cp_data[38] => m0_address[2].DATAIN +cp_data[39] => rf_source_data[39].DATAIN +cp_data[39] => m0_address[3].DATAIN +cp_data[40] => rf_source_data[40].DATAIN +cp_data[40] => m0_address[4].DATAIN +cp_data[41] => rf_source_data[41].DATAIN +cp_data[41] => m0_address[5].DATAIN +cp_data[42] => rf_source_data[42].DATAIN +cp_data[42] => m0_address[6].DATAIN +cp_data[43] => rf_source_data[43].DATAIN +cp_data[43] => m0_address[7].DATAIN +cp_data[44] => rf_source_data[44].DATAIN +cp_data[44] => m0_address[8].DATAIN +cp_data[45] => rf_source_data[45].DATAIN +cp_data[45] => m0_address[9].DATAIN +cp_data[46] => rf_source_data[46].DATAIN +cp_data[46] => m0_address[10].DATAIN +cp_data[47] => rf_source_data[47].DATAIN +cp_data[47] => m0_address[11].DATAIN +cp_data[48] => rf_source_data[48].DATAIN +cp_data[48] => m0_address[12].DATAIN +cp_data[49] => rf_source_data[49].DATAIN +cp_data[49] => m0_address[13].DATAIN +cp_data[50] => rf_source_data[50].DATAIN +cp_data[50] => m0_address[14].DATAIN +cp_data[51] => rf_source_data[51].DATAIN +cp_data[51] => m0_address[15].DATAIN +cp_data[52] => rf_source_data[52].DATAIN +cp_data[52] => m0_address[16].DATAIN +cp_data[53] => rf_source_data[53].DATAIN +cp_data[53] => m0_address[17].DATAIN +cp_data[54] => rf_source_data[54].DATAIN +cp_data[54] => m0_address[18].DATAIN +cp_data[55] => rf_source_data[55].DATAIN +cp_data[55] => m0_address[19].DATAIN +cp_data[56] => rf_source_data[56].DATAIN +cp_data[56] => m0_address[20].DATAIN +cp_data[57] => rf_source_data[57].DATAIN +cp_data[57] => m0_address[21].DATAIN +cp_data[58] => rf_source_data[58].DATAIN +cp_data[58] => m0_address[22].DATAIN +cp_data[59] => rf_source_data[59].DATAIN +cp_data[59] => m0_address[23].DATAIN +cp_data[60] => rf_source_data[60].DATAIN +cp_data[60] => m0_address[24].DATAIN +cp_data[61] => rf_source_data[61].DATAIN +cp_data[61] => m0_address[25].DATAIN +cp_data[62] => local_compressed_read.IN1 +cp_data[62] => rf_source_data[62].DATAIN +cp_data[63] => rf_source_data[63].DATAIN +cp_data[63] => comb.IN1 +cp_data[64] => local_write.IN1 +cp_data[64] => rf_source_data[64].DATAIN +cp_data[65] => local_read.IN1 +cp_data[65] => rf_source_data[65].DATAIN +cp_data[66] => local_lock.IN1 +cp_data[66] => rf_source_data[66].DATAIN +cp_data[67] => rf_source_data[67].DATAIN +cp_data[68] => m0_burstcount.DATAA +cp_data[68] => rf_source_data[68].DATAIN +cp_data[69] => m0_burstcount.DATAA +cp_data[69] => rf_source_data[69].DATAIN +cp_data[70] => m0_burstcount.DATAA +cp_data[70] => rf_source_data[70].DATAIN +cp_data[71] => rf_source_data[71].DATAIN +cp_data[72] => rf_source_data[72].DATAIN +cp_data[73] => rf_source_data[73].DATAIN +cp_data[74] => rf_source_data[74].DATAIN +cp_data[75] => rf_source_data[75].DATAIN +cp_data[76] => rf_source_data[76].DATAIN +cp_data[77] => rf_source_data[77].DATAIN +cp_data[78] => rf_source_data[78].DATAIN +cp_data[79] => rf_source_data[79].DATAIN +cp_data[80] => rf_source_data[80].DATAIN +cp_data[81] => rf_source_data[81].DATAIN +cp_data[82] => rf_source_data[82].DATAIN +cp_data[83] => rf_source_data[83].DATAIN +cp_data[84] => rf_source_data[84].DATAIN +cp_data[85] => rf_source_data[85].DATAIN +cp_data[86] => rf_source_data[86].DATAIN +cp_data[87] => rf_source_data[87].DATAIN +cp_data[88] => rf_source_data[88].DATAIN +cp_data[89] => rf_source_data[89].DATAIN +cp_data[90] => rf_source_data[90].DATAIN +cp_data[91] => rf_source_data[91].DATAIN +cp_data[92] => rf_source_data[92].DATAIN +cp_data[92] => m0_debugaccess.DATAIN +cp_data[93] => ~NO_FANOUT~ +cp_data[94] => ~NO_FANOUT~ +cp_data[95] => rf_source_data[95].DATAIN +cp_data[96] => rf_source_data[96].DATAIN +cp_data[97] => rf_source_data[97].DATAIN +cp_data[98] => rf_source_data[98].DATAIN +cp_data[99] => rf_source_data[99].DATAIN +cp_data[100] => rf_source_data[100].DATAIN +cp_channel[0] => ~NO_FANOUT~ +cp_channel[1] => ~NO_FANOUT~ +cp_channel[2] => ~NO_FANOUT~ +cp_channel[3] => ~NO_FANOUT~ +cp_channel[4] => ~NO_FANOUT~ +cp_channel[5] => ~NO_FANOUT~ +cp_channel[6] => ~NO_FANOUT~ +cp_channel[7] => ~NO_FANOUT~ +cp_channel[8] => ~NO_FANOUT~ +cp_channel[9] => ~NO_FANOUT~ +cp_channel[10] => ~NO_FANOUT~ +cp_startofpacket => rf_source_startofpacket.DATAIN +cp_endofpacket => nonposted_write_endofpacket.IN1 +cp_endofpacket => rf_source_endofpacket.DATAIN +rp_ready => rp_ready.IN1 +rp_valid <= rp_valid.DB_MAX_OUTPUT_PORT_TYPE +rp_data[0] <= rdata_fifo_sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +rp_data[1] <= rdata_fifo_sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +rp_data[2] <= rdata_fifo_sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +rp_data[3] <= rdata_fifo_sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +rp_data[4] <= rdata_fifo_sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +rp_data[5] <= rdata_fifo_sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +rp_data[6] <= rdata_fifo_sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +rp_data[7] <= rdata_fifo_sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +rp_data[8] <= rdata_fifo_sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +rp_data[9] <= rdata_fifo_sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +rp_data[10] <= rdata_fifo_sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +rp_data[11] <= rdata_fifo_sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +rp_data[12] <= rdata_fifo_sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +rp_data[13] <= rdata_fifo_sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +rp_data[14] <= rdata_fifo_sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +rp_data[15] <= rdata_fifo_sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +rp_data[16] <= rdata_fifo_sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +rp_data[17] <= rdata_fifo_sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +rp_data[18] <= rdata_fifo_sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +rp_data[19] <= rdata_fifo_sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +rp_data[20] <= rdata_fifo_sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +rp_data[21] <= rdata_fifo_sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +rp_data[22] <= rdata_fifo_sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +rp_data[23] <= rdata_fifo_sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +rp_data[24] <= rdata_fifo_sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +rp_data[25] <= rdata_fifo_sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +rp_data[26] <= rdata_fifo_sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +rp_data[27] <= rdata_fifo_sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +rp_data[28] <= rdata_fifo_sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +rp_data[29] <= rdata_fifo_sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +rp_data[30] <= rdata_fifo_sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +rp_data[31] <= rdata_fifo_sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +rp_data[32] <= rf_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +rp_data[33] <= rf_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +rp_data[34] <= rf_sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +rp_data[35] <= rf_sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +rp_data[36] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[37] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[38] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[39] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[40] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[41] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[42] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[43] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[44] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[45] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[46] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[47] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[48] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[49] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[50] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[51] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[52] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[53] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[54] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[55] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[56] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[57] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[58] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[59] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[60] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[61] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[62] <= altera_merlin_burst_uncompressor:uncompressor.source_is_compressed +rp_data[63] <= rf_sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +rp_data[64] <= rf_sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +rp_data[65] <= rp_data.DB_MAX_OUTPUT_PORT_TYPE +rp_data[66] <= rf_sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +rp_data[67] <= rf_sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +rp_data[68] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt +rp_data[69] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt +rp_data[70] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt +rp_data[71] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap +rp_data[72] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap +rp_data[73] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap +rp_data[74] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize +rp_data[75] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize +rp_data[76] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize +rp_data[77] <= rf_sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +rp_data[78] <= rf_sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +rp_data[79] <= rf_sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +rp_data[80] <= rf_sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +rp_data[81] <= rf_sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +rp_data[82] <= rf_sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +rp_data[83] <= rf_sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +rp_data[84] <= rf_sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +rp_data[85] <= rf_sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +rp_data[86] <= rf_sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +rp_data[87] <= rf_sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +rp_data[88] <= rf_sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +rp_data[89] <= rf_sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +rp_data[90] <= rf_sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +rp_data[91] <= rf_sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +rp_data[92] <= rf_sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +rp_data[93] <= rf_sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +rp_data[94] <= rf_sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +rp_data[95] <= rf_sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +rp_data[96] <= rf_sink_data[96].DB_MAX_OUTPUT_PORT_TYPE +rp_data[97] <= rf_sink_data[97].DB_MAX_OUTPUT_PORT_TYPE +rp_data[98] <= rf_sink_data[98].DB_MAX_OUTPUT_PORT_TYPE +rp_data[99] <= +rp_data[100] <= +rp_startofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_startofpacket +rp_endofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_endofpacket + + +|de0_nano_system|system:inst_cpu|altera_merlin_slave_agent:sysid_control_slave_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor +clk => burst_uncompress_address_offset[0].CLK +clk => burst_uncompress_address_offset[1].CLK +clk => burst_uncompress_address_offset[2].CLK +clk => burst_uncompress_address_offset[3].CLK +clk => burst_uncompress_address_offset[4].CLK +clk => burst_uncompress_address_offset[5].CLK +clk => burst_uncompress_address_offset[6].CLK +clk => burst_uncompress_address_offset[7].CLK +clk => burst_uncompress_address_offset[8].CLK +clk => burst_uncompress_address_offset[9].CLK +clk => burst_uncompress_address_offset[10].CLK +clk => burst_uncompress_address_offset[11].CLK +clk => burst_uncompress_address_offset[12].CLK +clk => burst_uncompress_address_offset[13].CLK +clk => burst_uncompress_address_offset[14].CLK +clk => burst_uncompress_address_offset[15].CLK +clk => burst_uncompress_address_offset[16].CLK +clk => burst_uncompress_address_offset[17].CLK +clk => burst_uncompress_address_offset[18].CLK +clk => burst_uncompress_address_offset[19].CLK +clk => burst_uncompress_address_offset[20].CLK +clk => burst_uncompress_address_offset[21].CLK +clk => burst_uncompress_address_offset[22].CLK +clk => burst_uncompress_address_offset[23].CLK +clk => burst_uncompress_address_offset[24].CLK +clk => burst_uncompress_address_offset[25].CLK +clk => burst_uncompress_address_base[0].CLK +clk => burst_uncompress_address_base[1].CLK +clk => burst_uncompress_address_base[2].CLK +clk => burst_uncompress_address_base[3].CLK +clk => burst_uncompress_address_base[4].CLK +clk => burst_uncompress_address_base[5].CLK +clk => burst_uncompress_address_base[6].CLK +clk => burst_uncompress_address_base[7].CLK +clk => burst_uncompress_address_base[8].CLK +clk => burst_uncompress_address_base[9].CLK +clk => burst_uncompress_address_base[10].CLK +clk => burst_uncompress_address_base[11].CLK +clk => burst_uncompress_address_base[12].CLK +clk => burst_uncompress_address_base[13].CLK +clk => burst_uncompress_address_base[14].CLK +clk => burst_uncompress_address_base[15].CLK +clk => burst_uncompress_address_base[16].CLK +clk => burst_uncompress_address_base[17].CLK +clk => burst_uncompress_address_base[18].CLK +clk => burst_uncompress_address_base[19].CLK +clk => burst_uncompress_address_base[20].CLK +clk => burst_uncompress_address_base[21].CLK +clk => burst_uncompress_address_base[22].CLK +clk => burst_uncompress_address_base[23].CLK +clk => burst_uncompress_address_base[24].CLK +clk => burst_uncompress_address_base[25].CLK +clk => burst_uncompress_byte_counter[0].CLK +clk => burst_uncompress_byte_counter[1].CLK +clk => burst_uncompress_byte_counter[2].CLK +clk => burst_uncompress_busy.CLK +reset => burst_uncompress_address_offset[0].ACLR +reset => burst_uncompress_address_offset[1].ACLR +reset => burst_uncompress_address_offset[2].ACLR +reset => burst_uncompress_address_offset[3].ACLR +reset => burst_uncompress_address_offset[4].ACLR +reset => burst_uncompress_address_offset[5].ACLR +reset => burst_uncompress_address_offset[6].ACLR +reset => burst_uncompress_address_offset[7].ACLR +reset => burst_uncompress_address_offset[8].ACLR +reset => burst_uncompress_address_offset[9].ACLR +reset => burst_uncompress_address_offset[10].ACLR +reset => burst_uncompress_address_offset[11].ACLR +reset => burst_uncompress_address_offset[12].ACLR +reset => burst_uncompress_address_offset[13].ACLR +reset => burst_uncompress_address_offset[14].ACLR +reset => burst_uncompress_address_offset[15].ACLR +reset => burst_uncompress_address_offset[16].ACLR +reset => burst_uncompress_address_offset[17].ACLR +reset => burst_uncompress_address_offset[18].ACLR +reset => burst_uncompress_address_offset[19].ACLR +reset => burst_uncompress_address_offset[20].ACLR +reset => burst_uncompress_address_offset[21].ACLR +reset => burst_uncompress_address_offset[22].ACLR +reset => burst_uncompress_address_offset[23].ACLR +reset => burst_uncompress_address_offset[24].ACLR +reset => burst_uncompress_address_offset[25].ACLR +reset => burst_uncompress_address_base[0].ACLR +reset => burst_uncompress_address_base[1].ACLR +reset => burst_uncompress_address_base[2].ACLR +reset => burst_uncompress_address_base[3].ACLR +reset => burst_uncompress_address_base[4].ACLR +reset => burst_uncompress_address_base[5].ACLR +reset => burst_uncompress_address_base[6].ACLR +reset => burst_uncompress_address_base[7].ACLR +reset => burst_uncompress_address_base[8].ACLR +reset => burst_uncompress_address_base[9].ACLR +reset => burst_uncompress_address_base[10].ACLR +reset => burst_uncompress_address_base[11].ACLR +reset => burst_uncompress_address_base[12].ACLR +reset => burst_uncompress_address_base[13].ACLR +reset => burst_uncompress_address_base[14].ACLR +reset => burst_uncompress_address_base[15].ACLR +reset => burst_uncompress_address_base[16].ACLR +reset => burst_uncompress_address_base[17].ACLR +reset => burst_uncompress_address_base[18].ACLR +reset => burst_uncompress_address_base[19].ACLR +reset => burst_uncompress_address_base[20].ACLR +reset => burst_uncompress_address_base[21].ACLR +reset => burst_uncompress_address_base[22].ACLR +reset => burst_uncompress_address_base[23].ACLR +reset => burst_uncompress_address_base[24].ACLR +reset => burst_uncompress_address_base[25].ACLR +reset => burst_uncompress_byte_counter[0].ACLR +reset => burst_uncompress_byte_counter[1].ACLR +reset => burst_uncompress_byte_counter[2].ACLR +reset => burst_uncompress_busy.ACLR +sink_startofpacket => source_startofpacket.IN1 +sink_endofpacket => source_endofpacket.IN1 +sink_valid => first_packet_beat.IN1 +sink_valid => last_packet_beat.IN1 +sink_valid => last_packet_beat.IN1 +sink_valid => always0.IN1 +sink_valid => sink_ready.IN0 +sink_valid => source_valid.DATAIN +sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE +sink_addr[0] => burst_uncompress_address_base.IN0 +sink_addr[0] => comb.DATAB +sink_addr[0] => source_addr.DATAB +sink_addr[1] => burst_uncompress_address_base.IN0 +sink_addr[1] => comb.DATAB +sink_addr[1] => source_addr.DATAB +sink_addr[2] => burst_uncompress_address_base.IN0 +sink_addr[2] => comb.DATAB +sink_addr[2] => source_addr.DATAB +sink_addr[3] => burst_uncompress_address_base.IN0 +sink_addr[3] => comb.DATAB +sink_addr[3] => source_addr.DATAB +sink_addr[4] => burst_uncompress_address_base.IN0 +sink_addr[4] => comb.DATAB +sink_addr[4] => source_addr.DATAB +sink_addr[5] => burst_uncompress_address_base.IN0 +sink_addr[5] => comb.DATAB +sink_addr[5] => source_addr.DATAB +sink_addr[6] => burst_uncompress_address_base.IN0 +sink_addr[6] => comb.DATAB +sink_addr[6] => source_addr.DATAB +sink_addr[7] => burst_uncompress_address_base.IN0 +sink_addr[7] => comb.DATAB +sink_addr[7] => source_addr.DATAB +sink_addr[8] => burst_uncompress_address_base.IN0 +sink_addr[8] => comb.DATAB +sink_addr[8] => source_addr.DATAB +sink_addr[9] => burst_uncompress_address_base.IN0 +sink_addr[9] => comb.DATAB +sink_addr[9] => source_addr.DATAB +sink_addr[10] => burst_uncompress_address_base.IN0 +sink_addr[10] => comb.DATAB +sink_addr[10] => source_addr.DATAB +sink_addr[11] => burst_uncompress_address_base.IN0 +sink_addr[11] => comb.DATAB +sink_addr[11] => source_addr.DATAB +sink_addr[12] => burst_uncompress_address_base.IN0 +sink_addr[12] => comb.DATAB +sink_addr[12] => source_addr.DATAB +sink_addr[13] => burst_uncompress_address_base.IN0 +sink_addr[13] => comb.DATAB +sink_addr[13] => source_addr.DATAB +sink_addr[14] => burst_uncompress_address_base.IN0 +sink_addr[14] => comb.DATAB +sink_addr[14] => source_addr.DATAB +sink_addr[15] => burst_uncompress_address_base.IN0 +sink_addr[15] => comb.DATAB +sink_addr[15] => source_addr.DATAB +sink_addr[16] => burst_uncompress_address_base.IN0 +sink_addr[16] => comb.DATAB +sink_addr[16] => source_addr.DATAB +sink_addr[17] => burst_uncompress_address_base.IN0 +sink_addr[17] => comb.DATAB +sink_addr[17] => source_addr.DATAB +sink_addr[18] => burst_uncompress_address_base.IN0 +sink_addr[18] => comb.DATAB +sink_addr[18] => source_addr.DATAB +sink_addr[19] => burst_uncompress_address_base.IN0 +sink_addr[19] => comb.DATAB +sink_addr[19] => source_addr.DATAB +sink_addr[20] => burst_uncompress_address_base.IN0 +sink_addr[20] => comb.DATAB +sink_addr[20] => source_addr.DATAB +sink_addr[21] => burst_uncompress_address_base.IN0 +sink_addr[21] => comb.DATAB +sink_addr[21] => source_addr.DATAB +sink_addr[22] => burst_uncompress_address_base.IN0 +sink_addr[22] => comb.DATAB +sink_addr[22] => source_addr.DATAB +sink_addr[23] => burst_uncompress_address_base.IN0 +sink_addr[23] => comb.DATAB +sink_addr[23] => source_addr.DATAB +sink_addr[24] => burst_uncompress_address_base.IN0 +sink_addr[24] => comb.DATAB +sink_addr[24] => source_addr.DATAB +sink_addr[25] => burst_uncompress_address_base.IN0 +sink_addr[25] => comb.DATAB +sink_addr[25] => source_addr.DATAB +sink_burstwrap[0] => p1_burst_uncompress_address_offset[0].IN1 +sink_burstwrap[0] => source_burstwrap[0].DATAIN +sink_burstwrap[0] => burst_uncompress_address_base.IN1 +sink_burstwrap[1] => p1_burst_uncompress_address_offset[1].IN1 +sink_burstwrap[1] => source_burstwrap[1].DATAIN +sink_burstwrap[1] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[2].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[25].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[24].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[23].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[22].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[21].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[20].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[19].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[18].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[17].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[16].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[15].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[14].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[13].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[12].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[11].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[10].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[9].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[8].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[7].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[6].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[5].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[4].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[3].IN1 +sink_burstwrap[2] => source_burstwrap[2].DATAIN +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_byte_cnt[0] => source_byte_cnt.DATAB +sink_byte_cnt[0] => Add1.IN6 +sink_byte_cnt[0] => Equal1.IN2 +sink_byte_cnt[1] => source_byte_cnt.DATAB +sink_byte_cnt[1] => Add1.IN5 +sink_byte_cnt[1] => Equal1.IN1 +sink_byte_cnt[2] => source_byte_cnt.DATAB +sink_byte_cnt[2] => Add1.IN4 +sink_byte_cnt[2] => Equal1.IN0 +sink_is_compressed => last_packet_beat.IN1 +sink_burstsize[0] => Decoder0.IN2 +sink_burstsize[0] => source_burstsize[0].DATAIN +sink_burstsize[1] => Decoder0.IN1 +sink_burstsize[1] => source_burstsize[1].DATAIN +sink_burstsize[2] => Decoder0.IN0 +sink_burstsize[2] => source_burstsize[2].DATAIN +source_startofpacket <= source_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +source_endofpacket <= source_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +source_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE +source_ready => always1.IN1 +source_ready => sink_ready.IN1 +source_addr[0] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[1] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[2] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[3] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[4] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[5] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[6] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[7] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[8] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[9] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[10] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[11] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[12] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[13] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[14] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[15] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[16] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[17] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[18] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[19] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[20] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[21] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[22] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[23] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[24] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[25] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_burstwrap[0] <= sink_burstwrap[0].DB_MAX_OUTPUT_PORT_TYPE +source_burstwrap[1] <= sink_burstwrap[1].DB_MAX_OUTPUT_PORT_TYPE +source_burstwrap[2] <= sink_burstwrap[2].DB_MAX_OUTPUT_PORT_TYPE +source_byte_cnt[0] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE +source_byte_cnt[1] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE +source_byte_cnt[2] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE +source_is_compressed <= +source_burstsize[0] <= sink_burstsize[0].DB_MAX_OUTPUT_PORT_TYPE +source_burstsize[1] <= sink_burstsize[1].DB_MAX_OUTPUT_PORT_TYPE +source_burstsize[2] <= sink_burstsize[2].DB_MAX_OUTPUT_PORT_TYPE + + +|de0_nano_system|system:inst_cpu|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo +clk => csr_readdata[0]~reg0.CLK +clk => csr_readdata[1]~reg0.CLK +clk => csr_readdata[2]~reg0.CLK +clk => csr_readdata[3]~reg0.CLK +clk => csr_readdata[4]~reg0.CLK +clk => csr_readdata[5]~reg0.CLK +clk => csr_readdata[6]~reg0.CLK +clk => csr_readdata[7]~reg0.CLK +clk => csr_readdata[8]~reg0.CLK +clk => csr_readdata[9]~reg0.CLK +clk => csr_readdata[10]~reg0.CLK +clk => csr_readdata[11]~reg0.CLK +clk => csr_readdata[12]~reg0.CLK +clk => csr_readdata[13]~reg0.CLK +clk => csr_readdata[14]~reg0.CLK +clk => csr_readdata[15]~reg0.CLK +clk => csr_readdata[16]~reg0.CLK +clk => csr_readdata[17]~reg0.CLK +clk => csr_readdata[18]~reg0.CLK +clk => csr_readdata[19]~reg0.CLK +clk => csr_readdata[20]~reg0.CLK +clk => csr_readdata[21]~reg0.CLK +clk => csr_readdata[22]~reg0.CLK +clk => csr_readdata[23]~reg0.CLK +clk => csr_readdata[24]~reg0.CLK +clk => csr_readdata[25]~reg0.CLK +clk => csr_readdata[26]~reg0.CLK +clk => csr_readdata[27]~reg0.CLK +clk => csr_readdata[28]~reg0.CLK +clk => csr_readdata[29]~reg0.CLK +clk => csr_readdata[30]~reg0.CLK +clk => csr_readdata[31]~reg0.CLK +clk => mem_used[1].CLK +clk => mem_used[0].CLK +clk => mem[1][0].CLK +clk => mem[1][1].CLK +clk => mem[1][2].CLK +clk => mem[1][3].CLK +clk => mem[1][4].CLK +clk => mem[1][5].CLK +clk => mem[1][6].CLK +clk => mem[1][7].CLK +clk => mem[1][8].CLK +clk => mem[1][9].CLK +clk => mem[1][10].CLK +clk => mem[1][11].CLK +clk => mem[1][12].CLK +clk => mem[1][13].CLK +clk => mem[1][14].CLK +clk => mem[1][15].CLK +clk => mem[1][16].CLK +clk => mem[1][17].CLK +clk => mem[1][18].CLK +clk => mem[1][19].CLK +clk => mem[1][20].CLK +clk => mem[1][21].CLK +clk => mem[1][22].CLK +clk => mem[1][23].CLK +clk => mem[1][24].CLK +clk => mem[1][25].CLK +clk => mem[1][26].CLK +clk => mem[1][27].CLK +clk => mem[1][28].CLK +clk => mem[1][29].CLK +clk => mem[1][30].CLK +clk => mem[1][31].CLK +clk => mem[1][32].CLK +clk => mem[1][33].CLK +clk => mem[1][34].CLK +clk => mem[1][35].CLK +clk => mem[1][36].CLK +clk => mem[1][37].CLK +clk => mem[1][38].CLK +clk => mem[1][39].CLK +clk => mem[1][40].CLK +clk => mem[1][41].CLK +clk => mem[1][42].CLK +clk => mem[1][43].CLK +clk => mem[1][44].CLK +clk => mem[1][45].CLK +clk => mem[1][46].CLK +clk => mem[1][47].CLK +clk => mem[1][48].CLK +clk => mem[1][49].CLK +clk => mem[1][50].CLK +clk => mem[1][51].CLK +clk => mem[1][52].CLK +clk => mem[1][53].CLK +clk => mem[1][54].CLK +clk => mem[1][55].CLK +clk => mem[1][56].CLK +clk => mem[1][57].CLK +clk => mem[1][58].CLK +clk => mem[1][59].CLK +clk => mem[1][60].CLK +clk => mem[1][61].CLK +clk => mem[1][62].CLK +clk => mem[1][63].CLK +clk => mem[1][64].CLK +clk => mem[1][65].CLK +clk => mem[1][66].CLK +clk => mem[1][67].CLK +clk => mem[1][68].CLK +clk => mem[1][69].CLK +clk => mem[1][70].CLK +clk => mem[1][71].CLK +clk => mem[1][72].CLK +clk => mem[1][73].CLK +clk => mem[1][74].CLK +clk => mem[1][75].CLK +clk => mem[1][76].CLK +clk => mem[1][77].CLK +clk => mem[1][78].CLK +clk => mem[1][79].CLK +clk => mem[1][80].CLK +clk => mem[1][81].CLK +clk => mem[1][82].CLK +clk => mem[1][83].CLK +clk => mem[1][84].CLK +clk => mem[1][85].CLK +clk => mem[1][86].CLK +clk => mem[1][87].CLK +clk => mem[1][88].CLK +clk => mem[1][89].CLK +clk => mem[1][90].CLK +clk => mem[1][91].CLK +clk => mem[1][92].CLK +clk => mem[1][93].CLK +clk => mem[1][94].CLK +clk => mem[1][95].CLK +clk => mem[1][96].CLK +clk => mem[1][97].CLK +clk => mem[1][98].CLK +clk => mem[1][99].CLK +clk => mem[1][100].CLK +clk => mem[1][101].CLK +clk => mem[1][102].CLK +clk => mem[1][103].CLK +clk => mem[0][0].CLK +clk => mem[0][1].CLK +clk => mem[0][2].CLK +clk => mem[0][3].CLK +clk => mem[0][4].CLK +clk => mem[0][5].CLK +clk => mem[0][6].CLK +clk => mem[0][7].CLK +clk => mem[0][8].CLK +clk => mem[0][9].CLK +clk => mem[0][10].CLK +clk => mem[0][11].CLK +clk => mem[0][12].CLK +clk => mem[0][13].CLK +clk => mem[0][14].CLK +clk => mem[0][15].CLK +clk => mem[0][16].CLK +clk => mem[0][17].CLK +clk => mem[0][18].CLK +clk => mem[0][19].CLK +clk => mem[0][20].CLK +clk => mem[0][21].CLK +clk => mem[0][22].CLK +clk => mem[0][23].CLK +clk => mem[0][24].CLK +clk => mem[0][25].CLK +clk => mem[0][26].CLK +clk => mem[0][27].CLK +clk => mem[0][28].CLK +clk => mem[0][29].CLK +clk => mem[0][30].CLK +clk => mem[0][31].CLK +clk => mem[0][32].CLK +clk => mem[0][33].CLK +clk => mem[0][34].CLK +clk => mem[0][35].CLK +clk => mem[0][36].CLK +clk => mem[0][37].CLK +clk => mem[0][38].CLK +clk => mem[0][39].CLK +clk => mem[0][40].CLK +clk => mem[0][41].CLK +clk => mem[0][42].CLK +clk => mem[0][43].CLK +clk => mem[0][44].CLK +clk => mem[0][45].CLK +clk => mem[0][46].CLK +clk => mem[0][47].CLK +clk => mem[0][48].CLK +clk => mem[0][49].CLK +clk => mem[0][50].CLK +clk => mem[0][51].CLK +clk => mem[0][52].CLK +clk => mem[0][53].CLK +clk => mem[0][54].CLK +clk => mem[0][55].CLK +clk => mem[0][56].CLK +clk => mem[0][57].CLK +clk => mem[0][58].CLK +clk => mem[0][59].CLK +clk => mem[0][60].CLK +clk => mem[0][61].CLK +clk => mem[0][62].CLK +clk => mem[0][63].CLK +clk => mem[0][64].CLK +clk => mem[0][65].CLK +clk => mem[0][66].CLK +clk => mem[0][67].CLK +clk => mem[0][68].CLK +clk => mem[0][69].CLK +clk => mem[0][70].CLK +clk => mem[0][71].CLK +clk => mem[0][72].CLK +clk => mem[0][73].CLK +clk => mem[0][74].CLK +clk => mem[0][75].CLK +clk => mem[0][76].CLK +clk => mem[0][77].CLK +clk => mem[0][78].CLK +clk => mem[0][79].CLK +clk => mem[0][80].CLK +clk => mem[0][81].CLK +clk => mem[0][82].CLK +clk => mem[0][83].CLK +clk => mem[0][84].CLK +clk => mem[0][85].CLK +clk => mem[0][86].CLK +clk => mem[0][87].CLK +clk => mem[0][88].CLK +clk => mem[0][89].CLK +clk => mem[0][90].CLK +clk => mem[0][91].CLK +clk => mem[0][92].CLK +clk => mem[0][93].CLK +clk => mem[0][94].CLK +clk => mem[0][95].CLK +clk => mem[0][96].CLK +clk => mem[0][97].CLK +clk => mem[0][98].CLK +clk => mem[0][99].CLK +clk => mem[0][100].CLK +clk => mem[0][101].CLK +clk => mem[0][102].CLK +clk => mem[0][103].CLK +reset => csr_readdata[0]~reg0.ACLR +reset => csr_readdata[1]~reg0.ACLR +reset => csr_readdata[2]~reg0.ACLR +reset => csr_readdata[3]~reg0.ACLR +reset => csr_readdata[4]~reg0.ACLR +reset => csr_readdata[5]~reg0.ACLR +reset => csr_readdata[6]~reg0.ACLR +reset => csr_readdata[7]~reg0.ACLR +reset => csr_readdata[8]~reg0.ACLR +reset => csr_readdata[9]~reg0.ACLR +reset => csr_readdata[10]~reg0.ACLR +reset => csr_readdata[11]~reg0.ACLR +reset => csr_readdata[12]~reg0.ACLR +reset => csr_readdata[13]~reg0.ACLR +reset => csr_readdata[14]~reg0.ACLR +reset => csr_readdata[15]~reg0.ACLR +reset => csr_readdata[16]~reg0.ACLR +reset => csr_readdata[17]~reg0.ACLR +reset => csr_readdata[18]~reg0.ACLR +reset => csr_readdata[19]~reg0.ACLR +reset => csr_readdata[20]~reg0.ACLR +reset => csr_readdata[21]~reg0.ACLR +reset => csr_readdata[22]~reg0.ACLR +reset => csr_readdata[23]~reg0.ACLR +reset => csr_readdata[24]~reg0.ACLR +reset => csr_readdata[25]~reg0.ACLR +reset => csr_readdata[26]~reg0.ACLR +reset => csr_readdata[27]~reg0.ACLR +reset => csr_readdata[28]~reg0.ACLR +reset => csr_readdata[29]~reg0.ACLR +reset => csr_readdata[30]~reg0.ACLR +reset => csr_readdata[31]~reg0.ACLR +reset => mem_used[1].ACLR +reset => mem_used[0].ACLR +reset => mem[1][0].ACLR +reset => mem[1][1].ACLR +reset => mem[1][2].ACLR +reset => mem[1][3].ACLR +reset => mem[1][4].ACLR +reset => mem[1][5].ACLR +reset => mem[1][6].ACLR +reset => mem[1][7].ACLR +reset => mem[1][8].ACLR +reset => mem[1][9].ACLR +reset => mem[1][10].ACLR +reset => mem[1][11].ACLR +reset => mem[1][12].ACLR +reset => mem[1][13].ACLR +reset => mem[1][14].ACLR +reset => mem[1][15].ACLR +reset => mem[1][16].ACLR +reset => mem[1][17].ACLR +reset => mem[1][18].ACLR +reset => mem[1][19].ACLR +reset => mem[1][20].ACLR +reset => mem[1][21].ACLR +reset => mem[1][22].ACLR +reset => mem[1][23].ACLR +reset => mem[1][24].ACLR +reset => mem[1][25].ACLR +reset => mem[1][26].ACLR +reset => mem[1][27].ACLR +reset => mem[1][28].ACLR +reset => mem[1][29].ACLR +reset => mem[1][30].ACLR +reset => mem[1][31].ACLR +reset => mem[1][32].ACLR +reset => mem[1][33].ACLR +reset => mem[1][34].ACLR +reset => mem[1][35].ACLR +reset => mem[1][36].ACLR +reset => mem[1][37].ACLR +reset => mem[1][38].ACLR +reset => mem[1][39].ACLR +reset => mem[1][40].ACLR +reset => mem[1][41].ACLR +reset => mem[1][42].ACLR +reset => mem[1][43].ACLR +reset => mem[1][44].ACLR +reset => mem[1][45].ACLR +reset => mem[1][46].ACLR +reset => mem[1][47].ACLR +reset => mem[1][48].ACLR +reset => mem[1][49].ACLR +reset => mem[1][50].ACLR +reset => mem[1][51].ACLR +reset => mem[1][52].ACLR +reset => mem[1][53].ACLR +reset => mem[1][54].ACLR +reset => mem[1][55].ACLR +reset => mem[1][56].ACLR +reset => mem[1][57].ACLR +reset => mem[1][58].ACLR +reset => mem[1][59].ACLR +reset => mem[1][60].ACLR +reset => mem[1][61].ACLR +reset => mem[1][62].ACLR +reset => mem[1][63].ACLR +reset => mem[1][64].ACLR +reset => mem[1][65].ACLR +reset => mem[1][66].ACLR +reset => mem[1][67].ACLR +reset => mem[1][68].ACLR +reset => mem[1][69].ACLR +reset => mem[1][70].ACLR +reset => mem[1][71].ACLR +reset => mem[1][72].ACLR +reset => mem[1][73].ACLR +reset => mem[1][74].ACLR +reset => mem[1][75].ACLR +reset => mem[1][76].ACLR +reset => mem[1][77].ACLR +reset => mem[1][78].ACLR +reset => mem[1][79].ACLR +reset => mem[1][80].ACLR +reset => mem[1][81].ACLR +reset => mem[1][82].ACLR +reset => mem[1][83].ACLR +reset => mem[1][84].ACLR +reset => mem[1][85].ACLR +reset => mem[1][86].ACLR +reset => mem[1][87].ACLR +reset => mem[1][88].ACLR +reset => mem[1][89].ACLR +reset => mem[1][90].ACLR +reset => mem[1][91].ACLR +reset => mem[1][92].ACLR +reset => mem[1][93].ACLR +reset => mem[1][94].ACLR +reset => mem[1][95].ACLR +reset => mem[1][96].ACLR +reset => mem[1][97].ACLR +reset => mem[1][98].ACLR +reset => mem[1][99].ACLR +reset => mem[1][100].ACLR +reset => mem[1][101].ACLR +reset => mem[1][102].ACLR +reset => mem[1][103].ACLR +reset => mem[0][0].ACLR +reset => mem[0][1].ACLR +reset => mem[0][2].ACLR +reset => mem[0][3].ACLR +reset => mem[0][4].ACLR +reset => mem[0][5].ACLR +reset => mem[0][6].ACLR +reset => mem[0][7].ACLR +reset => mem[0][8].ACLR +reset => mem[0][9].ACLR +reset => mem[0][10].ACLR +reset => mem[0][11].ACLR +reset => mem[0][12].ACLR +reset => mem[0][13].ACLR +reset => mem[0][14].ACLR +reset => mem[0][15].ACLR +reset => mem[0][16].ACLR +reset => mem[0][17].ACLR +reset => mem[0][18].ACLR +reset => mem[0][19].ACLR +reset => mem[0][20].ACLR +reset => mem[0][21].ACLR +reset => mem[0][22].ACLR +reset => mem[0][23].ACLR +reset => mem[0][24].ACLR +reset => mem[0][25].ACLR +reset => mem[0][26].ACLR +reset => mem[0][27].ACLR +reset => mem[0][28].ACLR +reset => mem[0][29].ACLR +reset => mem[0][30].ACLR +reset => mem[0][31].ACLR +reset => mem[0][32].ACLR +reset => mem[0][33].ACLR +reset => mem[0][34].ACLR +reset => mem[0][35].ACLR +reset => mem[0][36].ACLR +reset => mem[0][37].ACLR +reset => mem[0][38].ACLR +reset => mem[0][39].ACLR +reset => mem[0][40].ACLR +reset => mem[0][41].ACLR +reset => mem[0][42].ACLR +reset => mem[0][43].ACLR +reset => mem[0][44].ACLR +reset => mem[0][45].ACLR +reset => mem[0][46].ACLR +reset => mem[0][47].ACLR +reset => mem[0][48].ACLR +reset => mem[0][49].ACLR +reset => mem[0][50].ACLR +reset => mem[0][51].ACLR +reset => mem[0][52].ACLR +reset => mem[0][53].ACLR +reset => mem[0][54].ACLR +reset => mem[0][55].ACLR +reset => mem[0][56].ACLR +reset => mem[0][57].ACLR +reset => mem[0][58].ACLR +reset => mem[0][59].ACLR +reset => mem[0][60].ACLR +reset => mem[0][61].ACLR +reset => mem[0][62].ACLR +reset => mem[0][63].ACLR +reset => mem[0][64].ACLR +reset => mem[0][65].ACLR +reset => mem[0][66].ACLR +reset => mem[0][67].ACLR +reset => mem[0][68].ACLR +reset => mem[0][69].ACLR +reset => mem[0][70].ACLR +reset => mem[0][71].ACLR +reset => mem[0][72].ACLR +reset => mem[0][73].ACLR +reset => mem[0][74].ACLR +reset => mem[0][75].ACLR +reset => mem[0][76].ACLR +reset => mem[0][77].ACLR +reset => mem[0][78].ACLR +reset => mem[0][79].ACLR +reset => mem[0][80].ACLR +reset => mem[0][81].ACLR +reset => mem[0][82].ACLR +reset => mem[0][83].ACLR +reset => mem[0][84].ACLR +reset => mem[0][85].ACLR +reset => mem[0][86].ACLR +reset => mem[0][87].ACLR +reset => mem[0][88].ACLR +reset => mem[0][89].ACLR +reset => mem[0][90].ACLR +reset => mem[0][91].ACLR +reset => mem[0][92].ACLR +reset => mem[0][93].ACLR +reset => mem[0][94].ACLR +reset => mem[0][95].ACLR +reset => mem[0][96].ACLR +reset => mem[0][97].ACLR +reset => mem[0][98].ACLR +reset => mem[0][99].ACLR +reset => mem[0][100].ACLR +reset => mem[0][101].ACLR +reset => mem[0][102].ACLR +reset => mem[0][103].ACLR +in_data[0] => mem.DATAB +in_data[1] => mem.DATAB +in_data[2] => mem.DATAB +in_data[3] => mem.DATAB +in_data[4] => mem.DATAB +in_data[5] => mem.DATAB +in_data[6] => mem.DATAB +in_data[7] => mem.DATAB +in_data[8] => mem.DATAB +in_data[9] => mem.DATAB +in_data[10] => mem.DATAB +in_data[11] => mem.DATAB +in_data[12] => mem.DATAB +in_data[13] => mem.DATAB +in_data[14] => mem.DATAB +in_data[15] => mem.DATAB +in_data[16] => mem.DATAB +in_data[17] => mem.DATAB +in_data[18] => mem.DATAB +in_data[19] => mem.DATAB +in_data[20] => mem.DATAB +in_data[21] => mem.DATAB +in_data[22] => mem.DATAB +in_data[23] => mem.DATAB +in_data[24] => mem.DATAB +in_data[25] => mem.DATAB +in_data[26] => mem.DATAB +in_data[27] => mem.DATAB +in_data[28] => mem.DATAB +in_data[29] => mem.DATAB +in_data[30] => mem.DATAB +in_data[31] => mem.DATAB +in_data[32] => mem.DATAB +in_data[33] => mem.DATAB +in_data[34] => mem.DATAB +in_data[35] => mem.DATAB +in_data[36] => mem.DATAB +in_data[37] => mem.DATAB +in_data[38] => mem.DATAB +in_data[39] => mem.DATAB +in_data[40] => mem.DATAB +in_data[41] => mem.DATAB +in_data[42] => mem.DATAB +in_data[43] => mem.DATAB +in_data[44] => mem.DATAB +in_data[45] => mem.DATAB +in_data[46] => mem.DATAB +in_data[47] => mem.DATAB +in_data[48] => mem.DATAB +in_data[49] => mem.DATAB +in_data[50] => mem.DATAB +in_data[51] => mem.DATAB +in_data[52] => mem.DATAB +in_data[53] => mem.DATAB +in_data[54] => mem.DATAB +in_data[55] => mem.DATAB +in_data[56] => mem.DATAB +in_data[57] => mem.DATAB +in_data[58] => mem.DATAB +in_data[59] => mem.DATAB +in_data[60] => mem.DATAB +in_data[61] => mem.DATAB +in_data[62] => mem.DATAB +in_data[63] => mem.DATAB +in_data[64] => mem.DATAB +in_data[65] => mem.DATAB +in_data[66] => mem.DATAB +in_data[67] => mem.DATAB +in_data[68] => mem.DATAB +in_data[69] => mem.DATAB +in_data[70] => mem.DATAB +in_data[71] => mem.DATAB +in_data[72] => mem.DATAB +in_data[73] => mem.DATAB +in_data[74] => mem.DATAB +in_data[75] => mem.DATAB +in_data[76] => mem.DATAB +in_data[77] => mem.DATAB +in_data[78] => mem.DATAB +in_data[79] => mem.DATAB +in_data[80] => mem.DATAB +in_data[81] => mem.DATAB +in_data[82] => mem.DATAB +in_data[83] => mem.DATAB +in_data[84] => mem.DATAB +in_data[85] => mem.DATAB +in_data[86] => mem.DATAB +in_data[87] => mem.DATAB +in_data[88] => mem.DATAB +in_data[89] => mem.DATAB +in_data[90] => mem.DATAB +in_data[91] => mem.DATAB +in_data[92] => mem.DATAB +in_data[93] => mem.DATAB +in_data[94] => mem.DATAB +in_data[95] => mem.DATAB +in_data[96] => mem.DATAB +in_data[97] => mem.DATAB +in_data[98] => mem.DATAB +in_data[99] => mem.DATAB +in_data[100] => mem.DATAB +in_data[101] => mem.DATAB +in_valid => write.IN1 +in_startofpacket => mem.DATAB +in_endofpacket => mem.DATAB +in_empty[0] => ~NO_FANOUT~ +in_error[0] => out_error[0].DATAIN +in_error[0] => out_empty[0].DATAIN +in_channel[0] => out_channel[0].DATAIN +in_ready <= mem_used[1].DB_MAX_OUTPUT_PORT_TYPE +out_data[0] <= mem[0][0].DB_MAX_OUTPUT_PORT_TYPE +out_data[1] <= mem[0][1].DB_MAX_OUTPUT_PORT_TYPE +out_data[2] <= mem[0][2].DB_MAX_OUTPUT_PORT_TYPE +out_data[3] <= mem[0][3].DB_MAX_OUTPUT_PORT_TYPE +out_data[4] <= mem[0][4].DB_MAX_OUTPUT_PORT_TYPE +out_data[5] <= mem[0][5].DB_MAX_OUTPUT_PORT_TYPE +out_data[6] <= mem[0][6].DB_MAX_OUTPUT_PORT_TYPE +out_data[7] <= mem[0][7].DB_MAX_OUTPUT_PORT_TYPE +out_data[8] <= mem[0][8].DB_MAX_OUTPUT_PORT_TYPE +out_data[9] <= mem[0][9].DB_MAX_OUTPUT_PORT_TYPE +out_data[10] <= mem[0][10].DB_MAX_OUTPUT_PORT_TYPE +out_data[11] <= mem[0][11].DB_MAX_OUTPUT_PORT_TYPE +out_data[12] <= mem[0][12].DB_MAX_OUTPUT_PORT_TYPE +out_data[13] <= mem[0][13].DB_MAX_OUTPUT_PORT_TYPE +out_data[14] <= mem[0][14].DB_MAX_OUTPUT_PORT_TYPE +out_data[15] <= mem[0][15].DB_MAX_OUTPUT_PORT_TYPE +out_data[16] <= mem[0][16].DB_MAX_OUTPUT_PORT_TYPE +out_data[17] <= mem[0][17].DB_MAX_OUTPUT_PORT_TYPE +out_data[18] <= mem[0][18].DB_MAX_OUTPUT_PORT_TYPE +out_data[19] <= mem[0][19].DB_MAX_OUTPUT_PORT_TYPE +out_data[20] <= mem[0][20].DB_MAX_OUTPUT_PORT_TYPE +out_data[21] <= mem[0][21].DB_MAX_OUTPUT_PORT_TYPE +out_data[22] <= mem[0][22].DB_MAX_OUTPUT_PORT_TYPE +out_data[23] <= mem[0][23].DB_MAX_OUTPUT_PORT_TYPE +out_data[24] <= mem[0][24].DB_MAX_OUTPUT_PORT_TYPE +out_data[25] <= mem[0][25].DB_MAX_OUTPUT_PORT_TYPE +out_data[26] <= mem[0][26].DB_MAX_OUTPUT_PORT_TYPE +out_data[27] <= mem[0][27].DB_MAX_OUTPUT_PORT_TYPE +out_data[28] <= mem[0][28].DB_MAX_OUTPUT_PORT_TYPE +out_data[29] <= mem[0][29].DB_MAX_OUTPUT_PORT_TYPE +out_data[30] <= mem[0][30].DB_MAX_OUTPUT_PORT_TYPE +out_data[31] <= mem[0][31].DB_MAX_OUTPUT_PORT_TYPE +out_data[32] <= mem[0][32].DB_MAX_OUTPUT_PORT_TYPE +out_data[33] <= mem[0][33].DB_MAX_OUTPUT_PORT_TYPE +out_data[34] <= mem[0][34].DB_MAX_OUTPUT_PORT_TYPE +out_data[35] <= mem[0][35].DB_MAX_OUTPUT_PORT_TYPE +out_data[36] <= mem[0][36].DB_MAX_OUTPUT_PORT_TYPE +out_data[37] <= mem[0][37].DB_MAX_OUTPUT_PORT_TYPE +out_data[38] <= mem[0][38].DB_MAX_OUTPUT_PORT_TYPE +out_data[39] <= mem[0][39].DB_MAX_OUTPUT_PORT_TYPE +out_data[40] <= mem[0][40].DB_MAX_OUTPUT_PORT_TYPE +out_data[41] <= mem[0][41].DB_MAX_OUTPUT_PORT_TYPE +out_data[42] <= mem[0][42].DB_MAX_OUTPUT_PORT_TYPE +out_data[43] <= mem[0][43].DB_MAX_OUTPUT_PORT_TYPE +out_data[44] <= mem[0][44].DB_MAX_OUTPUT_PORT_TYPE +out_data[45] <= mem[0][45].DB_MAX_OUTPUT_PORT_TYPE +out_data[46] <= mem[0][46].DB_MAX_OUTPUT_PORT_TYPE +out_data[47] <= mem[0][47].DB_MAX_OUTPUT_PORT_TYPE +out_data[48] <= mem[0][48].DB_MAX_OUTPUT_PORT_TYPE +out_data[49] <= mem[0][49].DB_MAX_OUTPUT_PORT_TYPE +out_data[50] <= mem[0][50].DB_MAX_OUTPUT_PORT_TYPE +out_data[51] <= mem[0][51].DB_MAX_OUTPUT_PORT_TYPE +out_data[52] <= mem[0][52].DB_MAX_OUTPUT_PORT_TYPE +out_data[53] <= mem[0][53].DB_MAX_OUTPUT_PORT_TYPE +out_data[54] <= mem[0][54].DB_MAX_OUTPUT_PORT_TYPE +out_data[55] <= mem[0][55].DB_MAX_OUTPUT_PORT_TYPE +out_data[56] <= mem[0][56].DB_MAX_OUTPUT_PORT_TYPE +out_data[57] <= mem[0][57].DB_MAX_OUTPUT_PORT_TYPE +out_data[58] <= mem[0][58].DB_MAX_OUTPUT_PORT_TYPE +out_data[59] <= mem[0][59].DB_MAX_OUTPUT_PORT_TYPE +out_data[60] <= mem[0][60].DB_MAX_OUTPUT_PORT_TYPE +out_data[61] <= mem[0][61].DB_MAX_OUTPUT_PORT_TYPE +out_data[62] <= mem[0][62].DB_MAX_OUTPUT_PORT_TYPE +out_data[63] <= mem[0][63].DB_MAX_OUTPUT_PORT_TYPE +out_data[64] <= mem[0][64].DB_MAX_OUTPUT_PORT_TYPE +out_data[65] <= mem[0][65].DB_MAX_OUTPUT_PORT_TYPE +out_data[66] <= mem[0][66].DB_MAX_OUTPUT_PORT_TYPE +out_data[67] <= mem[0][67].DB_MAX_OUTPUT_PORT_TYPE +out_data[68] <= mem[0][68].DB_MAX_OUTPUT_PORT_TYPE +out_data[69] <= mem[0][69].DB_MAX_OUTPUT_PORT_TYPE +out_data[70] <= mem[0][70].DB_MAX_OUTPUT_PORT_TYPE +out_data[71] <= mem[0][71].DB_MAX_OUTPUT_PORT_TYPE +out_data[72] <= mem[0][72].DB_MAX_OUTPUT_PORT_TYPE +out_data[73] <= mem[0][73].DB_MAX_OUTPUT_PORT_TYPE +out_data[74] <= mem[0][74].DB_MAX_OUTPUT_PORT_TYPE +out_data[75] <= mem[0][75].DB_MAX_OUTPUT_PORT_TYPE +out_data[76] <= mem[0][76].DB_MAX_OUTPUT_PORT_TYPE +out_data[77] <= mem[0][77].DB_MAX_OUTPUT_PORT_TYPE +out_data[78] <= mem[0][78].DB_MAX_OUTPUT_PORT_TYPE +out_data[79] <= mem[0][79].DB_MAX_OUTPUT_PORT_TYPE +out_data[80] <= mem[0][80].DB_MAX_OUTPUT_PORT_TYPE +out_data[81] <= mem[0][81].DB_MAX_OUTPUT_PORT_TYPE +out_data[82] <= mem[0][82].DB_MAX_OUTPUT_PORT_TYPE +out_data[83] <= mem[0][83].DB_MAX_OUTPUT_PORT_TYPE +out_data[84] <= mem[0][84].DB_MAX_OUTPUT_PORT_TYPE +out_data[85] <= mem[0][85].DB_MAX_OUTPUT_PORT_TYPE +out_data[86] <= mem[0][86].DB_MAX_OUTPUT_PORT_TYPE +out_data[87] <= mem[0][87].DB_MAX_OUTPUT_PORT_TYPE +out_data[88] <= mem[0][88].DB_MAX_OUTPUT_PORT_TYPE +out_data[89] <= mem[0][89].DB_MAX_OUTPUT_PORT_TYPE +out_data[90] <= mem[0][90].DB_MAX_OUTPUT_PORT_TYPE +out_data[91] <= mem[0][91].DB_MAX_OUTPUT_PORT_TYPE +out_data[92] <= mem[0][92].DB_MAX_OUTPUT_PORT_TYPE +out_data[93] <= mem[0][93].DB_MAX_OUTPUT_PORT_TYPE +out_data[94] <= mem[0][94].DB_MAX_OUTPUT_PORT_TYPE +out_data[95] <= mem[0][95].DB_MAX_OUTPUT_PORT_TYPE +out_data[96] <= mem[0][96].DB_MAX_OUTPUT_PORT_TYPE +out_data[97] <= mem[0][97].DB_MAX_OUTPUT_PORT_TYPE +out_data[98] <= mem[0][98].DB_MAX_OUTPUT_PORT_TYPE +out_data[99] <= mem[0][99].DB_MAX_OUTPUT_PORT_TYPE +out_data[100] <= mem[0][100].DB_MAX_OUTPUT_PORT_TYPE +out_data[101] <= mem[0][101].DB_MAX_OUTPUT_PORT_TYPE +out_valid <= mem_used[0].DB_MAX_OUTPUT_PORT_TYPE +out_startofpacket <= mem[0][103].DB_MAX_OUTPUT_PORT_TYPE +out_endofpacket <= mem[0][102].DB_MAX_OUTPUT_PORT_TYPE +out_empty[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE +out_error[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE +out_channel[0] <= in_channel[0].DB_MAX_OUTPUT_PORT_TYPE +out_ready => internal_out_ready.IN1 +csr_address[0] => ~NO_FANOUT~ +csr_address[1] => ~NO_FANOUT~ +csr_write => ~NO_FANOUT~ +csr_read => csr_readdata[0]~reg0.ENA +csr_read => csr_readdata[31]~reg0.ENA +csr_read => csr_readdata[30]~reg0.ENA +csr_read => csr_readdata[29]~reg0.ENA +csr_read => csr_readdata[28]~reg0.ENA +csr_read => csr_readdata[27]~reg0.ENA +csr_read => csr_readdata[26]~reg0.ENA +csr_read => csr_readdata[25]~reg0.ENA +csr_read => csr_readdata[24]~reg0.ENA +csr_read => csr_readdata[23]~reg0.ENA +csr_read => csr_readdata[22]~reg0.ENA +csr_read => csr_readdata[21]~reg0.ENA +csr_read => csr_readdata[20]~reg0.ENA +csr_read => csr_readdata[19]~reg0.ENA +csr_read => csr_readdata[18]~reg0.ENA +csr_read => csr_readdata[17]~reg0.ENA +csr_read => csr_readdata[16]~reg0.ENA +csr_read => csr_readdata[15]~reg0.ENA +csr_read => csr_readdata[14]~reg0.ENA +csr_read => csr_readdata[13]~reg0.ENA +csr_read => csr_readdata[12]~reg0.ENA +csr_read => csr_readdata[11]~reg0.ENA +csr_read => csr_readdata[10]~reg0.ENA +csr_read => csr_readdata[9]~reg0.ENA +csr_read => csr_readdata[8]~reg0.ENA +csr_read => csr_readdata[7]~reg0.ENA +csr_read => csr_readdata[6]~reg0.ENA +csr_read => csr_readdata[5]~reg0.ENA +csr_read => csr_readdata[4]~reg0.ENA +csr_read => csr_readdata[3]~reg0.ENA +csr_read => csr_readdata[2]~reg0.ENA +csr_read => csr_readdata[1]~reg0.ENA +csr_writedata[0] => ~NO_FANOUT~ +csr_writedata[1] => ~NO_FANOUT~ +csr_writedata[2] => ~NO_FANOUT~ +csr_writedata[3] => ~NO_FANOUT~ +csr_writedata[4] => ~NO_FANOUT~ +csr_writedata[5] => ~NO_FANOUT~ +csr_writedata[6] => ~NO_FANOUT~ +csr_writedata[7] => ~NO_FANOUT~ +csr_writedata[8] => ~NO_FANOUT~ +csr_writedata[9] => ~NO_FANOUT~ +csr_writedata[10] => ~NO_FANOUT~ +csr_writedata[11] => ~NO_FANOUT~ +csr_writedata[12] => ~NO_FANOUT~ +csr_writedata[13] => ~NO_FANOUT~ +csr_writedata[14] => ~NO_FANOUT~ +csr_writedata[15] => ~NO_FANOUT~ +csr_writedata[16] => ~NO_FANOUT~ +csr_writedata[17] => ~NO_FANOUT~ +csr_writedata[18] => ~NO_FANOUT~ +csr_writedata[19] => ~NO_FANOUT~ +csr_writedata[20] => ~NO_FANOUT~ +csr_writedata[21] => ~NO_FANOUT~ +csr_writedata[22] => ~NO_FANOUT~ +csr_writedata[23] => ~NO_FANOUT~ +csr_writedata[24] => ~NO_FANOUT~ +csr_writedata[25] => ~NO_FANOUT~ +csr_writedata[26] => ~NO_FANOUT~ +csr_writedata[27] => ~NO_FANOUT~ +csr_writedata[28] => ~NO_FANOUT~ +csr_writedata[29] => ~NO_FANOUT~ +csr_writedata[30] => ~NO_FANOUT~ +csr_writedata[31] => ~NO_FANOUT~ +csr_readdata[0] <= csr_readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[1] <= csr_readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[2] <= csr_readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[3] <= csr_readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[4] <= csr_readdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[5] <= csr_readdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[6] <= csr_readdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[7] <= csr_readdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[8] <= csr_readdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[9] <= csr_readdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[10] <= csr_readdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[11] <= csr_readdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[12] <= csr_readdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[13] <= csr_readdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[14] <= csr_readdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[15] <= csr_readdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[16] <= csr_readdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[17] <= csr_readdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[18] <= csr_readdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[19] <= csr_readdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[20] <= csr_readdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[21] <= csr_readdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[22] <= csr_readdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[23] <= csr_readdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[24] <= csr_readdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[25] <= csr_readdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[26] <= csr_readdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[27] <= csr_readdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[28] <= csr_readdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[29] <= csr_readdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[30] <= csr_readdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[31] <= csr_readdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE +almost_full_data <= +almost_empty_data <= + + +|de0_nano_system|system:inst_cpu|altera_merlin_slave_agent:sys_clk_timer_s1_translator_avalon_universal_slave_0_agent +clk => clk.IN1 +reset => reset.IN1 +m0_address[0] <= +m0_address[1] <= +m0_address[2] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE +m0_address[3] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE +m0_address[4] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE +m0_address[5] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE +m0_address[6] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE +m0_address[7] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE +m0_address[8] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE +m0_address[9] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE +m0_address[10] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE +m0_address[11] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE +m0_address[12] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE +m0_address[13] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE +m0_address[14] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE +m0_address[15] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE +m0_address[16] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE +m0_address[17] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE +m0_address[18] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE +m0_address[19] <= cp_data[55].DB_MAX_OUTPUT_PORT_TYPE +m0_address[20] <= cp_data[56].DB_MAX_OUTPUT_PORT_TYPE +m0_address[21] <= cp_data[57].DB_MAX_OUTPUT_PORT_TYPE +m0_address[22] <= cp_data[58].DB_MAX_OUTPUT_PORT_TYPE +m0_address[23] <= cp_data[59].DB_MAX_OUTPUT_PORT_TYPE +m0_address[24] <= cp_data[60].DB_MAX_OUTPUT_PORT_TYPE +m0_address[25] <= cp_data[61].DB_MAX_OUTPUT_PORT_TYPE +m0_burstcount[0] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE +m0_burstcount[1] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE +m0_burstcount[2] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[0] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[1] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[2] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[3] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE +m0_read <= m0_read.DB_MAX_OUTPUT_PORT_TYPE +m0_readdata[0] => rdata_fifo_src_data[0].DATAIN +m0_readdata[1] => rdata_fifo_src_data[1].DATAIN +m0_readdata[2] => rdata_fifo_src_data[2].DATAIN +m0_readdata[3] => rdata_fifo_src_data[3].DATAIN +m0_readdata[4] => rdata_fifo_src_data[4].DATAIN +m0_readdata[5] => rdata_fifo_src_data[5].DATAIN +m0_readdata[6] => rdata_fifo_src_data[6].DATAIN +m0_readdata[7] => rdata_fifo_src_data[7].DATAIN +m0_readdata[8] => rdata_fifo_src_data[8].DATAIN +m0_readdata[9] => rdata_fifo_src_data[9].DATAIN +m0_readdata[10] => rdata_fifo_src_data[10].DATAIN +m0_readdata[11] => rdata_fifo_src_data[11].DATAIN +m0_readdata[12] => rdata_fifo_src_data[12].DATAIN +m0_readdata[13] => rdata_fifo_src_data[13].DATAIN +m0_readdata[14] => rdata_fifo_src_data[14].DATAIN +m0_readdata[15] => rdata_fifo_src_data[15].DATAIN +m0_readdata[16] => rdata_fifo_src_data[16].DATAIN +m0_readdata[17] => rdata_fifo_src_data[17].DATAIN +m0_readdata[18] => rdata_fifo_src_data[18].DATAIN +m0_readdata[19] => rdata_fifo_src_data[19].DATAIN +m0_readdata[20] => rdata_fifo_src_data[20].DATAIN +m0_readdata[21] => rdata_fifo_src_data[21].DATAIN +m0_readdata[22] => rdata_fifo_src_data[22].DATAIN +m0_readdata[23] => rdata_fifo_src_data[23].DATAIN +m0_readdata[24] => rdata_fifo_src_data[24].DATAIN +m0_readdata[25] => rdata_fifo_src_data[25].DATAIN +m0_readdata[26] => rdata_fifo_src_data[26].DATAIN +m0_readdata[27] => rdata_fifo_src_data[27].DATAIN +m0_readdata[28] => rdata_fifo_src_data[28].DATAIN +m0_readdata[29] => rdata_fifo_src_data[29].DATAIN +m0_readdata[30] => rdata_fifo_src_data[30].DATAIN +m0_readdata[31] => rdata_fifo_src_data[31].DATAIN +m0_waitrequest => cp_ready.IN0 +m0_write <= m0_write.DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[0] <= cp_data[0].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[1] <= cp_data[1].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[2] <= cp_data[2].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[3] <= cp_data[3].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[4] <= cp_data[4].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[5] <= cp_data[5].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[6] <= cp_data[6].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[7] <= cp_data[7].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[8] <= cp_data[8].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[9] <= cp_data[9].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[10] <= cp_data[10].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[11] <= cp_data[11].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[12] <= cp_data[12].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[13] <= cp_data[13].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[14] <= cp_data[14].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[15] <= cp_data[15].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[16] <= cp_data[16].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[17] <= cp_data[17].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[18] <= cp_data[18].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[19] <= cp_data[19].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[20] <= cp_data[20].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[21] <= cp_data[21].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[22] <= cp_data[22].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[23] <= cp_data[23].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[24] <= cp_data[24].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[25] <= cp_data[25].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[26] <= cp_data[26].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[27] <= cp_data[27].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[28] <= cp_data[28].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[29] <= cp_data[29].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[30] <= cp_data[30].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[31] <= cp_data[31].DB_MAX_OUTPUT_PORT_TYPE +m0_readdatavalid => rdata_fifo_src_valid.DATAIN +m0_debugaccess <= cp_data[92].DB_MAX_OUTPUT_PORT_TYPE +m0_lock <= m0_lock.DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[0] <= +rf_source_data[1] <= +rf_source_data[2] <= +rf_source_data[3] <= +rf_source_data[4] <= +rf_source_data[5] <= +rf_source_data[6] <= +rf_source_data[7] <= +rf_source_data[8] <= +rf_source_data[9] <= +rf_source_data[10] <= +rf_source_data[11] <= +rf_source_data[12] <= +rf_source_data[13] <= +rf_source_data[14] <= +rf_source_data[15] <= +rf_source_data[16] <= +rf_source_data[17] <= +rf_source_data[18] <= +rf_source_data[19] <= +rf_source_data[20] <= +rf_source_data[21] <= +rf_source_data[22] <= +rf_source_data[23] <= +rf_source_data[24] <= +rf_source_data[25] <= +rf_source_data[26] <= +rf_source_data[27] <= +rf_source_data[28] <= +rf_source_data[29] <= +rf_source_data[30] <= +rf_source_data[31] <= +rf_source_data[32] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[33] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[34] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[35] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[36] <= cp_data[36].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[37] <= cp_data[37].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[38] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[39] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[40] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[41] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[42] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[43] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[44] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[45] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[46] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[47] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[48] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[49] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[50] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[51] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[52] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[53] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[54] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[55] <= cp_data[55].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[56] <= cp_data[56].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[57] <= cp_data[57].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[58] <= cp_data[58].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[59] <= cp_data[59].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[60] <= cp_data[60].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[61] <= cp_data[61].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[62] <= cp_data[62].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[63] <= cp_data[63].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[64] <= cp_data[64].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[65] <= cp_data[65].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[66] <= cp_data[66].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[67] <= cp_data[67].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[68] <= cp_data[68].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[69] <= cp_data[69].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[70] <= cp_data[70].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[71] <= cp_data[71].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[72] <= cp_data[72].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[73] <= cp_data[73].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[74] <= cp_data[74].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[75] <= cp_data[75].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[76] <= cp_data[76].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[77] <= cp_data[77].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[78] <= cp_data[78].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[79] <= cp_data[79].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[80] <= cp_data[80].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[81] <= cp_data[81].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[82] <= cp_data[82].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[83] <= cp_data[83].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[84] <= cp_data[84].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[85] <= cp_data[85].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[86] <= cp_data[86].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[87] <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[88] <= cp_data[88].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[89] <= cp_data[89].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[90] <= cp_data[90].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[91] <= cp_data[91].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[92] <= cp_data[92].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[93] <= +rf_source_data[94] <= +rf_source_data[95] <= cp_data[95].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[96] <= cp_data[96].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[97] <= cp_data[97].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[98] <= cp_data[98].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[99] <= cp_data[99].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[100] <= cp_data[100].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[101] <= nonposted_write_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +rf_source_valid <= rf_source_valid.DB_MAX_OUTPUT_PORT_TYPE +rf_source_startofpacket <= cp_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +rf_source_endofpacket <= cp_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +rf_source_ready => cp_ready.IN1 +rf_source_ready => m0_write.IN1 +rf_source_ready => m0_lock.IN1 +rf_source_ready => rf_source_valid.IN1 +rf_source_ready => m0_read.IN1 +rf_sink_data[0] => ~NO_FANOUT~ +rf_sink_data[1] => ~NO_FANOUT~ +rf_sink_data[2] => ~NO_FANOUT~ +rf_sink_data[3] => ~NO_FANOUT~ +rf_sink_data[4] => ~NO_FANOUT~ +rf_sink_data[5] => ~NO_FANOUT~ +rf_sink_data[6] => ~NO_FANOUT~ +rf_sink_data[7] => ~NO_FANOUT~ +rf_sink_data[8] => ~NO_FANOUT~ +rf_sink_data[9] => ~NO_FANOUT~ +rf_sink_data[10] => ~NO_FANOUT~ +rf_sink_data[11] => ~NO_FANOUT~ +rf_sink_data[12] => ~NO_FANOUT~ +rf_sink_data[13] => ~NO_FANOUT~ +rf_sink_data[14] => ~NO_FANOUT~ +rf_sink_data[15] => ~NO_FANOUT~ +rf_sink_data[16] => ~NO_FANOUT~ +rf_sink_data[17] => ~NO_FANOUT~ +rf_sink_data[18] => ~NO_FANOUT~ +rf_sink_data[19] => ~NO_FANOUT~ +rf_sink_data[20] => ~NO_FANOUT~ +rf_sink_data[21] => ~NO_FANOUT~ +rf_sink_data[22] => ~NO_FANOUT~ +rf_sink_data[23] => ~NO_FANOUT~ +rf_sink_data[24] => ~NO_FANOUT~ +rf_sink_data[25] => ~NO_FANOUT~ +rf_sink_data[26] => ~NO_FANOUT~ +rf_sink_data[27] => ~NO_FANOUT~ +rf_sink_data[28] => ~NO_FANOUT~ +rf_sink_data[29] => ~NO_FANOUT~ +rf_sink_data[30] => ~NO_FANOUT~ +rf_sink_data[31] => ~NO_FANOUT~ +rf_sink_data[32] => rp_data[32].DATAIN +rf_sink_data[33] => rp_data[33].DATAIN +rf_sink_data[34] => rp_data[34].DATAIN +rf_sink_data[35] => rp_data[35].DATAIN +rf_sink_data[36] => rf_sink_addr[0].IN1 +rf_sink_data[37] => rf_sink_addr[1].IN1 +rf_sink_data[38] => rf_sink_addr[2].IN1 +rf_sink_data[39] => rf_sink_addr[3].IN1 +rf_sink_data[40] => rf_sink_addr[4].IN1 +rf_sink_data[41] => rf_sink_addr[5].IN1 +rf_sink_data[42] => rf_sink_addr[6].IN1 +rf_sink_data[43] => rf_sink_addr[7].IN1 +rf_sink_data[44] => rf_sink_addr[8].IN1 +rf_sink_data[45] => rf_sink_addr[9].IN1 +rf_sink_data[46] => rf_sink_addr[10].IN1 +rf_sink_data[47] => rf_sink_addr[11].IN1 +rf_sink_data[48] => rf_sink_addr[12].IN1 +rf_sink_data[49] => rf_sink_addr[13].IN1 +rf_sink_data[50] => rf_sink_addr[14].IN1 +rf_sink_data[51] => rf_sink_addr[15].IN1 +rf_sink_data[52] => rf_sink_addr[16].IN1 +rf_sink_data[53] => rf_sink_addr[17].IN1 +rf_sink_data[54] => rf_sink_addr[18].IN1 +rf_sink_data[55] => rf_sink_addr[19].IN1 +rf_sink_data[56] => rf_sink_addr[20].IN1 +rf_sink_data[57] => rf_sink_addr[21].IN1 +rf_sink_data[58] => rf_sink_addr[22].IN1 +rf_sink_data[59] => rf_sink_addr[23].IN1 +rf_sink_data[60] => rf_sink_addr[24].IN1 +rf_sink_data[61] => rf_sink_addr[25].IN1 +rf_sink_data[62] => rf_sink_compressed.IN1 +rf_sink_data[63] => rp_data[63].DATAIN +rf_sink_data[64] => comb.OUTPUTSELECT +rf_sink_data[64] => rp_data[64].DATAIN +rf_sink_data[65] => rp_data.IN0 +rf_sink_data[66] => rp_data[66].DATAIN +rf_sink_data[67] => rp_data[67].DATAIN +rf_sink_data[68] => rf_sink_byte_cnt[0].IN1 +rf_sink_data[69] => rf_sink_byte_cnt[1].IN1 +rf_sink_data[70] => rf_sink_byte_cnt[2].IN1 +rf_sink_data[71] => rf_sink_burstwrap[0].IN1 +rf_sink_data[72] => rf_sink_burstwrap[1].IN1 +rf_sink_data[73] => rf_sink_burstwrap[2].IN1 +rf_sink_data[74] => rf_sink_burstsize[0].IN1 +rf_sink_data[75] => rf_sink_burstsize[1].IN1 +rf_sink_data[76] => rf_sink_burstsize[2].IN1 +rf_sink_data[77] => rp_data[77].DATAIN +rf_sink_data[78] => rp_data[78].DATAIN +rf_sink_data[79] => rp_data[79].DATAIN +rf_sink_data[80] => rp_data[80].DATAIN +rf_sink_data[81] => rp_data[81].DATAIN +rf_sink_data[82] => rp_data[82].DATAIN +rf_sink_data[83] => rp_data[87].DATAIN +rf_sink_data[84] => rp_data[88].DATAIN +rf_sink_data[85] => rp_data[89].DATAIN +rf_sink_data[86] => rp_data[90].DATAIN +rf_sink_data[87] => rp_data[83].DATAIN +rf_sink_data[88] => rp_data[84].DATAIN +rf_sink_data[89] => rp_data[85].DATAIN +rf_sink_data[90] => rp_data[86].DATAIN +rf_sink_data[91] => rp_data[91].DATAIN +rf_sink_data[92] => rp_data[92].DATAIN +rf_sink_data[93] => rp_data[93].DATAIN +rf_sink_data[94] => rp_data[94].DATAIN +rf_sink_data[95] => rp_data[95].DATAIN +rf_sink_data[96] => rp_data[96].DATAIN +rf_sink_data[97] => rp_data[97].DATAIN +rf_sink_data[98] => rp_data[98].DATAIN +rf_sink_data[99] => ~NO_FANOUT~ +rf_sink_data[100] => ~NO_FANOUT~ +rf_sink_data[101] => rdata_fifo_sink_ready.IN0 +rf_sink_data[101] => comb.IN0 +rf_sink_valid => rdata_fifo_sink_ready.IN1 +rf_sink_valid => comb.IN1 +rf_sink_startofpacket => comb.DATAA +rf_sink_endofpacket => rf_sink_endofpacket.IN1 +rf_sink_ready <= altera_merlin_burst_uncompressor:uncompressor.sink_ready +rdata_fifo_src_data[0] <= m0_readdata[0].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[1] <= m0_readdata[1].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[2] <= m0_readdata[2].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[3] <= m0_readdata[3].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[4] <= m0_readdata[4].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[5] <= m0_readdata[5].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[6] <= m0_readdata[6].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[7] <= m0_readdata[7].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[8] <= m0_readdata[8].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[9] <= m0_readdata[9].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[10] <= m0_readdata[10].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[11] <= m0_readdata[11].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[12] <= m0_readdata[12].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[13] <= m0_readdata[13].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[14] <= m0_readdata[14].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[15] <= m0_readdata[15].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[16] <= m0_readdata[16].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[17] <= m0_readdata[17].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[18] <= m0_readdata[18].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[19] <= m0_readdata[19].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[20] <= m0_readdata[20].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[21] <= m0_readdata[21].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[22] <= m0_readdata[22].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[23] <= m0_readdata[23].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[24] <= m0_readdata[24].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[25] <= m0_readdata[25].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[26] <= m0_readdata[26].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[27] <= m0_readdata[27].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[28] <= m0_readdata[28].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[29] <= m0_readdata[29].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[30] <= m0_readdata[30].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[31] <= m0_readdata[31].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_valid <= m0_readdatavalid.DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_ready => ~NO_FANOUT~ +rdata_fifo_sink_data[0] => rp_data[0].DATAIN +rdata_fifo_sink_data[1] => rp_data[1].DATAIN +rdata_fifo_sink_data[2] => rp_data[2].DATAIN +rdata_fifo_sink_data[3] => rp_data[3].DATAIN +rdata_fifo_sink_data[4] => rp_data[4].DATAIN +rdata_fifo_sink_data[5] => rp_data[5].DATAIN +rdata_fifo_sink_data[6] => rp_data[6].DATAIN +rdata_fifo_sink_data[7] => rp_data[7].DATAIN +rdata_fifo_sink_data[8] => rp_data[8].DATAIN +rdata_fifo_sink_data[9] => rp_data[9].DATAIN +rdata_fifo_sink_data[10] => rp_data[10].DATAIN +rdata_fifo_sink_data[11] => rp_data[11].DATAIN +rdata_fifo_sink_data[12] => rp_data[12].DATAIN +rdata_fifo_sink_data[13] => rp_data[13].DATAIN +rdata_fifo_sink_data[14] => rp_data[14].DATAIN +rdata_fifo_sink_data[15] => rp_data[15].DATAIN +rdata_fifo_sink_data[16] => rp_data[16].DATAIN +rdata_fifo_sink_data[17] => rp_data[17].DATAIN +rdata_fifo_sink_data[18] => rp_data[18].DATAIN +rdata_fifo_sink_data[19] => rp_data[19].DATAIN +rdata_fifo_sink_data[20] => rp_data[20].DATAIN +rdata_fifo_sink_data[21] => rp_data[21].DATAIN +rdata_fifo_sink_data[22] => rp_data[22].DATAIN +rdata_fifo_sink_data[23] => rp_data[23].DATAIN +rdata_fifo_sink_data[24] => rp_data[24].DATAIN +rdata_fifo_sink_data[25] => rp_data[25].DATAIN +rdata_fifo_sink_data[26] => rp_data[26].DATAIN +rdata_fifo_sink_data[27] => rp_data[27].DATAIN +rdata_fifo_sink_data[28] => rp_data[28].DATAIN +rdata_fifo_sink_data[29] => rp_data[29].DATAIN +rdata_fifo_sink_data[30] => rp_data[30].DATAIN +rdata_fifo_sink_data[31] => rp_data[31].DATAIN +rdata_fifo_sink_valid => rp_valid.IN1 +rdata_fifo_sink_valid => rdata_fifo_sink_ready.IN0 +rdata_fifo_sink_valid => comb.IN1 +rdata_fifo_sink_ready <= rdata_fifo_sink_ready.DB_MAX_OUTPUT_PORT_TYPE +cp_ready <= cp_ready.DB_MAX_OUTPUT_PORT_TYPE +cp_valid => local_lock.IN0 +cp_valid => local_write.IN0 +cp_valid => local_read.IN0 +cp_valid => local_compressed_read.IN0 +cp_data[0] => m0_writedata[0].DATAIN +cp_data[1] => m0_writedata[1].DATAIN +cp_data[2] => m0_writedata[2].DATAIN +cp_data[3] => m0_writedata[3].DATAIN +cp_data[4] => m0_writedata[4].DATAIN +cp_data[5] => m0_writedata[5].DATAIN +cp_data[6] => m0_writedata[6].DATAIN +cp_data[7] => m0_writedata[7].DATAIN +cp_data[8] => m0_writedata[8].DATAIN +cp_data[9] => m0_writedata[9].DATAIN +cp_data[10] => m0_writedata[10].DATAIN +cp_data[11] => m0_writedata[11].DATAIN +cp_data[12] => m0_writedata[12].DATAIN +cp_data[13] => m0_writedata[13].DATAIN +cp_data[14] => m0_writedata[14].DATAIN +cp_data[15] => m0_writedata[15].DATAIN +cp_data[16] => m0_writedata[16].DATAIN +cp_data[17] => m0_writedata[17].DATAIN +cp_data[18] => m0_writedata[18].DATAIN +cp_data[19] => m0_writedata[19].DATAIN +cp_data[20] => m0_writedata[20].DATAIN +cp_data[21] => m0_writedata[21].DATAIN +cp_data[22] => m0_writedata[22].DATAIN +cp_data[23] => m0_writedata[23].DATAIN +cp_data[24] => m0_writedata[24].DATAIN +cp_data[25] => m0_writedata[25].DATAIN +cp_data[26] => m0_writedata[26].DATAIN +cp_data[27] => m0_writedata[27].DATAIN +cp_data[28] => m0_writedata[28].DATAIN +cp_data[29] => m0_writedata[29].DATAIN +cp_data[30] => m0_writedata[30].DATAIN +cp_data[31] => m0_writedata[31].DATAIN +cp_data[32] => rf_source_data[32].DATAIN +cp_data[32] => m0_byteenable[0].DATAIN +cp_data[33] => rf_source_data[33].DATAIN +cp_data[33] => m0_byteenable[1].DATAIN +cp_data[34] => rf_source_data[34].DATAIN +cp_data[34] => m0_byteenable[2].DATAIN +cp_data[35] => rf_source_data[35].DATAIN +cp_data[35] => m0_byteenable[3].DATAIN +cp_data[36] => rf_source_data[36].DATAIN +cp_data[37] => rf_source_data[37].DATAIN +cp_data[38] => rf_source_data[38].DATAIN +cp_data[38] => m0_address[2].DATAIN +cp_data[39] => rf_source_data[39].DATAIN +cp_data[39] => m0_address[3].DATAIN +cp_data[40] => rf_source_data[40].DATAIN +cp_data[40] => m0_address[4].DATAIN +cp_data[41] => rf_source_data[41].DATAIN +cp_data[41] => m0_address[5].DATAIN +cp_data[42] => rf_source_data[42].DATAIN +cp_data[42] => m0_address[6].DATAIN +cp_data[43] => rf_source_data[43].DATAIN +cp_data[43] => m0_address[7].DATAIN +cp_data[44] => rf_source_data[44].DATAIN +cp_data[44] => m0_address[8].DATAIN +cp_data[45] => rf_source_data[45].DATAIN +cp_data[45] => m0_address[9].DATAIN +cp_data[46] => rf_source_data[46].DATAIN +cp_data[46] => m0_address[10].DATAIN +cp_data[47] => rf_source_data[47].DATAIN +cp_data[47] => m0_address[11].DATAIN +cp_data[48] => rf_source_data[48].DATAIN +cp_data[48] => m0_address[12].DATAIN +cp_data[49] => rf_source_data[49].DATAIN +cp_data[49] => m0_address[13].DATAIN +cp_data[50] => rf_source_data[50].DATAIN +cp_data[50] => m0_address[14].DATAIN +cp_data[51] => rf_source_data[51].DATAIN +cp_data[51] => m0_address[15].DATAIN +cp_data[52] => rf_source_data[52].DATAIN +cp_data[52] => m0_address[16].DATAIN +cp_data[53] => rf_source_data[53].DATAIN +cp_data[53] => m0_address[17].DATAIN +cp_data[54] => rf_source_data[54].DATAIN +cp_data[54] => m0_address[18].DATAIN +cp_data[55] => rf_source_data[55].DATAIN +cp_data[55] => m0_address[19].DATAIN +cp_data[56] => rf_source_data[56].DATAIN +cp_data[56] => m0_address[20].DATAIN +cp_data[57] => rf_source_data[57].DATAIN +cp_data[57] => m0_address[21].DATAIN +cp_data[58] => rf_source_data[58].DATAIN +cp_data[58] => m0_address[22].DATAIN +cp_data[59] => rf_source_data[59].DATAIN +cp_data[59] => m0_address[23].DATAIN +cp_data[60] => rf_source_data[60].DATAIN +cp_data[60] => m0_address[24].DATAIN +cp_data[61] => rf_source_data[61].DATAIN +cp_data[61] => m0_address[25].DATAIN +cp_data[62] => local_compressed_read.IN1 +cp_data[62] => rf_source_data[62].DATAIN +cp_data[63] => rf_source_data[63].DATAIN +cp_data[63] => comb.IN1 +cp_data[64] => local_write.IN1 +cp_data[64] => rf_source_data[64].DATAIN +cp_data[65] => local_read.IN1 +cp_data[65] => rf_source_data[65].DATAIN +cp_data[66] => local_lock.IN1 +cp_data[66] => rf_source_data[66].DATAIN +cp_data[67] => rf_source_data[67].DATAIN +cp_data[68] => m0_burstcount.DATAA +cp_data[68] => rf_source_data[68].DATAIN +cp_data[69] => m0_burstcount.DATAA +cp_data[69] => rf_source_data[69].DATAIN +cp_data[70] => m0_burstcount.DATAA +cp_data[70] => rf_source_data[70].DATAIN +cp_data[71] => rf_source_data[71].DATAIN +cp_data[72] => rf_source_data[72].DATAIN +cp_data[73] => rf_source_data[73].DATAIN +cp_data[74] => rf_source_data[74].DATAIN +cp_data[75] => rf_source_data[75].DATAIN +cp_data[76] => rf_source_data[76].DATAIN +cp_data[77] => rf_source_data[77].DATAIN +cp_data[78] => rf_source_data[78].DATAIN +cp_data[79] => rf_source_data[79].DATAIN +cp_data[80] => rf_source_data[80].DATAIN +cp_data[81] => rf_source_data[81].DATAIN +cp_data[82] => rf_source_data[82].DATAIN +cp_data[83] => rf_source_data[83].DATAIN +cp_data[84] => rf_source_data[84].DATAIN +cp_data[85] => rf_source_data[85].DATAIN +cp_data[86] => rf_source_data[86].DATAIN +cp_data[87] => rf_source_data[87].DATAIN +cp_data[88] => rf_source_data[88].DATAIN +cp_data[89] => rf_source_data[89].DATAIN +cp_data[90] => rf_source_data[90].DATAIN +cp_data[91] => rf_source_data[91].DATAIN +cp_data[92] => rf_source_data[92].DATAIN +cp_data[92] => m0_debugaccess.DATAIN +cp_data[93] => ~NO_FANOUT~ +cp_data[94] => ~NO_FANOUT~ +cp_data[95] => rf_source_data[95].DATAIN +cp_data[96] => rf_source_data[96].DATAIN +cp_data[97] => rf_source_data[97].DATAIN +cp_data[98] => rf_source_data[98].DATAIN +cp_data[99] => rf_source_data[99].DATAIN +cp_data[100] => rf_source_data[100].DATAIN +cp_channel[0] => ~NO_FANOUT~ +cp_channel[1] => ~NO_FANOUT~ +cp_channel[2] => ~NO_FANOUT~ +cp_channel[3] => ~NO_FANOUT~ +cp_channel[4] => ~NO_FANOUT~ +cp_channel[5] => ~NO_FANOUT~ +cp_channel[6] => ~NO_FANOUT~ +cp_channel[7] => ~NO_FANOUT~ +cp_channel[8] => ~NO_FANOUT~ +cp_channel[9] => ~NO_FANOUT~ +cp_channel[10] => ~NO_FANOUT~ +cp_startofpacket => rf_source_startofpacket.DATAIN +cp_endofpacket => nonposted_write_endofpacket.IN1 +cp_endofpacket => rf_source_endofpacket.DATAIN +rp_ready => rp_ready.IN1 +rp_valid <= rp_valid.DB_MAX_OUTPUT_PORT_TYPE +rp_data[0] <= rdata_fifo_sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +rp_data[1] <= rdata_fifo_sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +rp_data[2] <= rdata_fifo_sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +rp_data[3] <= rdata_fifo_sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +rp_data[4] <= rdata_fifo_sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +rp_data[5] <= rdata_fifo_sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +rp_data[6] <= rdata_fifo_sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +rp_data[7] <= rdata_fifo_sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +rp_data[8] <= rdata_fifo_sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +rp_data[9] <= rdata_fifo_sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +rp_data[10] <= rdata_fifo_sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +rp_data[11] <= rdata_fifo_sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +rp_data[12] <= rdata_fifo_sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +rp_data[13] <= rdata_fifo_sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +rp_data[14] <= rdata_fifo_sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +rp_data[15] <= rdata_fifo_sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +rp_data[16] <= rdata_fifo_sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +rp_data[17] <= rdata_fifo_sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +rp_data[18] <= rdata_fifo_sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +rp_data[19] <= rdata_fifo_sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +rp_data[20] <= rdata_fifo_sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +rp_data[21] <= rdata_fifo_sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +rp_data[22] <= rdata_fifo_sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +rp_data[23] <= rdata_fifo_sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +rp_data[24] <= rdata_fifo_sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +rp_data[25] <= rdata_fifo_sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +rp_data[26] <= rdata_fifo_sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +rp_data[27] <= rdata_fifo_sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +rp_data[28] <= rdata_fifo_sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +rp_data[29] <= rdata_fifo_sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +rp_data[30] <= rdata_fifo_sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +rp_data[31] <= rdata_fifo_sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +rp_data[32] <= rf_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +rp_data[33] <= rf_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +rp_data[34] <= rf_sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +rp_data[35] <= rf_sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +rp_data[36] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[37] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[38] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[39] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[40] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[41] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[42] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[43] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[44] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[45] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[46] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[47] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[48] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[49] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[50] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[51] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[52] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[53] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[54] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[55] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[56] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[57] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[58] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[59] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[60] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[61] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[62] <= altera_merlin_burst_uncompressor:uncompressor.source_is_compressed +rp_data[63] <= rf_sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +rp_data[64] <= rf_sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +rp_data[65] <= rp_data.DB_MAX_OUTPUT_PORT_TYPE +rp_data[66] <= rf_sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +rp_data[67] <= rf_sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +rp_data[68] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt +rp_data[69] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt +rp_data[70] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt +rp_data[71] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap +rp_data[72] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap +rp_data[73] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap +rp_data[74] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize +rp_data[75] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize +rp_data[76] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize +rp_data[77] <= rf_sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +rp_data[78] <= rf_sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +rp_data[79] <= rf_sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +rp_data[80] <= rf_sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +rp_data[81] <= rf_sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +rp_data[82] <= rf_sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +rp_data[83] <= rf_sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +rp_data[84] <= rf_sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +rp_data[85] <= rf_sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +rp_data[86] <= rf_sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +rp_data[87] <= rf_sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +rp_data[88] <= rf_sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +rp_data[89] <= rf_sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +rp_data[90] <= rf_sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +rp_data[91] <= rf_sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +rp_data[92] <= rf_sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +rp_data[93] <= rf_sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +rp_data[94] <= rf_sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +rp_data[95] <= rf_sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +rp_data[96] <= rf_sink_data[96].DB_MAX_OUTPUT_PORT_TYPE +rp_data[97] <= rf_sink_data[97].DB_MAX_OUTPUT_PORT_TYPE +rp_data[98] <= rf_sink_data[98].DB_MAX_OUTPUT_PORT_TYPE +rp_data[99] <= +rp_data[100] <= +rp_startofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_startofpacket +rp_endofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_endofpacket + + +|de0_nano_system|system:inst_cpu|altera_merlin_slave_agent:sys_clk_timer_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor +clk => burst_uncompress_address_offset[0].CLK +clk => burst_uncompress_address_offset[1].CLK +clk => burst_uncompress_address_offset[2].CLK +clk => burst_uncompress_address_offset[3].CLK +clk => burst_uncompress_address_offset[4].CLK +clk => burst_uncompress_address_offset[5].CLK +clk => burst_uncompress_address_offset[6].CLK +clk => burst_uncompress_address_offset[7].CLK +clk => burst_uncompress_address_offset[8].CLK +clk => burst_uncompress_address_offset[9].CLK +clk => burst_uncompress_address_offset[10].CLK +clk => burst_uncompress_address_offset[11].CLK +clk => burst_uncompress_address_offset[12].CLK +clk => burst_uncompress_address_offset[13].CLK +clk => burst_uncompress_address_offset[14].CLK +clk => burst_uncompress_address_offset[15].CLK +clk => burst_uncompress_address_offset[16].CLK +clk => burst_uncompress_address_offset[17].CLK +clk => burst_uncompress_address_offset[18].CLK +clk => burst_uncompress_address_offset[19].CLK +clk => burst_uncompress_address_offset[20].CLK +clk => burst_uncompress_address_offset[21].CLK +clk => burst_uncompress_address_offset[22].CLK +clk => burst_uncompress_address_offset[23].CLK +clk => burst_uncompress_address_offset[24].CLK +clk => burst_uncompress_address_offset[25].CLK +clk => burst_uncompress_address_base[0].CLK +clk => burst_uncompress_address_base[1].CLK +clk => burst_uncompress_address_base[2].CLK +clk => burst_uncompress_address_base[3].CLK +clk => burst_uncompress_address_base[4].CLK +clk => burst_uncompress_address_base[5].CLK +clk => burst_uncompress_address_base[6].CLK +clk => burst_uncompress_address_base[7].CLK +clk => burst_uncompress_address_base[8].CLK +clk => burst_uncompress_address_base[9].CLK +clk => burst_uncompress_address_base[10].CLK +clk => burst_uncompress_address_base[11].CLK +clk => burst_uncompress_address_base[12].CLK +clk => burst_uncompress_address_base[13].CLK +clk => burst_uncompress_address_base[14].CLK +clk => burst_uncompress_address_base[15].CLK +clk => burst_uncompress_address_base[16].CLK +clk => burst_uncompress_address_base[17].CLK +clk => burst_uncompress_address_base[18].CLK +clk => burst_uncompress_address_base[19].CLK +clk => burst_uncompress_address_base[20].CLK +clk => burst_uncompress_address_base[21].CLK +clk => burst_uncompress_address_base[22].CLK +clk => burst_uncompress_address_base[23].CLK +clk => burst_uncompress_address_base[24].CLK +clk => burst_uncompress_address_base[25].CLK +clk => burst_uncompress_byte_counter[0].CLK +clk => burst_uncompress_byte_counter[1].CLK +clk => burst_uncompress_byte_counter[2].CLK +clk => burst_uncompress_busy.CLK +reset => burst_uncompress_address_offset[0].ACLR +reset => burst_uncompress_address_offset[1].ACLR +reset => burst_uncompress_address_offset[2].ACLR +reset => burst_uncompress_address_offset[3].ACLR +reset => burst_uncompress_address_offset[4].ACLR +reset => burst_uncompress_address_offset[5].ACLR +reset => burst_uncompress_address_offset[6].ACLR +reset => burst_uncompress_address_offset[7].ACLR +reset => burst_uncompress_address_offset[8].ACLR +reset => burst_uncompress_address_offset[9].ACLR +reset => burst_uncompress_address_offset[10].ACLR +reset => burst_uncompress_address_offset[11].ACLR +reset => burst_uncompress_address_offset[12].ACLR +reset => burst_uncompress_address_offset[13].ACLR +reset => burst_uncompress_address_offset[14].ACLR +reset => burst_uncompress_address_offset[15].ACLR +reset => burst_uncompress_address_offset[16].ACLR +reset => burst_uncompress_address_offset[17].ACLR +reset => burst_uncompress_address_offset[18].ACLR +reset => burst_uncompress_address_offset[19].ACLR +reset => burst_uncompress_address_offset[20].ACLR +reset => burst_uncompress_address_offset[21].ACLR +reset => burst_uncompress_address_offset[22].ACLR +reset => burst_uncompress_address_offset[23].ACLR +reset => burst_uncompress_address_offset[24].ACLR +reset => burst_uncompress_address_offset[25].ACLR +reset => burst_uncompress_address_base[0].ACLR +reset => burst_uncompress_address_base[1].ACLR +reset => burst_uncompress_address_base[2].ACLR +reset => burst_uncompress_address_base[3].ACLR +reset => burst_uncompress_address_base[4].ACLR +reset => burst_uncompress_address_base[5].ACLR +reset => burst_uncompress_address_base[6].ACLR +reset => burst_uncompress_address_base[7].ACLR +reset => burst_uncompress_address_base[8].ACLR +reset => burst_uncompress_address_base[9].ACLR +reset => burst_uncompress_address_base[10].ACLR +reset => burst_uncompress_address_base[11].ACLR +reset => burst_uncompress_address_base[12].ACLR +reset => burst_uncompress_address_base[13].ACLR +reset => burst_uncompress_address_base[14].ACLR +reset => burst_uncompress_address_base[15].ACLR +reset => burst_uncompress_address_base[16].ACLR +reset => burst_uncompress_address_base[17].ACLR +reset => burst_uncompress_address_base[18].ACLR +reset => burst_uncompress_address_base[19].ACLR +reset => burst_uncompress_address_base[20].ACLR +reset => burst_uncompress_address_base[21].ACLR +reset => burst_uncompress_address_base[22].ACLR +reset => burst_uncompress_address_base[23].ACLR +reset => burst_uncompress_address_base[24].ACLR +reset => burst_uncompress_address_base[25].ACLR +reset => burst_uncompress_byte_counter[0].ACLR +reset => burst_uncompress_byte_counter[1].ACLR +reset => burst_uncompress_byte_counter[2].ACLR +reset => burst_uncompress_busy.ACLR +sink_startofpacket => source_startofpacket.IN1 +sink_endofpacket => source_endofpacket.IN1 +sink_valid => first_packet_beat.IN1 +sink_valid => last_packet_beat.IN1 +sink_valid => last_packet_beat.IN1 +sink_valid => always0.IN1 +sink_valid => sink_ready.IN0 +sink_valid => source_valid.DATAIN +sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE +sink_addr[0] => burst_uncompress_address_base.IN0 +sink_addr[0] => comb.DATAB +sink_addr[0] => source_addr.DATAB +sink_addr[1] => burst_uncompress_address_base.IN0 +sink_addr[1] => comb.DATAB +sink_addr[1] => source_addr.DATAB +sink_addr[2] => burst_uncompress_address_base.IN0 +sink_addr[2] => comb.DATAB +sink_addr[2] => source_addr.DATAB +sink_addr[3] => burst_uncompress_address_base.IN0 +sink_addr[3] => comb.DATAB +sink_addr[3] => source_addr.DATAB +sink_addr[4] => burst_uncompress_address_base.IN0 +sink_addr[4] => comb.DATAB +sink_addr[4] => source_addr.DATAB +sink_addr[5] => burst_uncompress_address_base.IN0 +sink_addr[5] => comb.DATAB +sink_addr[5] => source_addr.DATAB +sink_addr[6] => burst_uncompress_address_base.IN0 +sink_addr[6] => comb.DATAB +sink_addr[6] => source_addr.DATAB +sink_addr[7] => burst_uncompress_address_base.IN0 +sink_addr[7] => comb.DATAB +sink_addr[7] => source_addr.DATAB +sink_addr[8] => burst_uncompress_address_base.IN0 +sink_addr[8] => comb.DATAB +sink_addr[8] => source_addr.DATAB +sink_addr[9] => burst_uncompress_address_base.IN0 +sink_addr[9] => comb.DATAB +sink_addr[9] => source_addr.DATAB +sink_addr[10] => burst_uncompress_address_base.IN0 +sink_addr[10] => comb.DATAB +sink_addr[10] => source_addr.DATAB +sink_addr[11] => burst_uncompress_address_base.IN0 +sink_addr[11] => comb.DATAB +sink_addr[11] => source_addr.DATAB +sink_addr[12] => burst_uncompress_address_base.IN0 +sink_addr[12] => comb.DATAB +sink_addr[12] => source_addr.DATAB +sink_addr[13] => burst_uncompress_address_base.IN0 +sink_addr[13] => comb.DATAB +sink_addr[13] => source_addr.DATAB +sink_addr[14] => burst_uncompress_address_base.IN0 +sink_addr[14] => comb.DATAB +sink_addr[14] => source_addr.DATAB +sink_addr[15] => burst_uncompress_address_base.IN0 +sink_addr[15] => comb.DATAB +sink_addr[15] => source_addr.DATAB +sink_addr[16] => burst_uncompress_address_base.IN0 +sink_addr[16] => comb.DATAB +sink_addr[16] => source_addr.DATAB +sink_addr[17] => burst_uncompress_address_base.IN0 +sink_addr[17] => comb.DATAB +sink_addr[17] => source_addr.DATAB +sink_addr[18] => burst_uncompress_address_base.IN0 +sink_addr[18] => comb.DATAB +sink_addr[18] => source_addr.DATAB +sink_addr[19] => burst_uncompress_address_base.IN0 +sink_addr[19] => comb.DATAB +sink_addr[19] => source_addr.DATAB +sink_addr[20] => burst_uncompress_address_base.IN0 +sink_addr[20] => comb.DATAB +sink_addr[20] => source_addr.DATAB +sink_addr[21] => burst_uncompress_address_base.IN0 +sink_addr[21] => comb.DATAB +sink_addr[21] => source_addr.DATAB +sink_addr[22] => burst_uncompress_address_base.IN0 +sink_addr[22] => comb.DATAB +sink_addr[22] => source_addr.DATAB +sink_addr[23] => burst_uncompress_address_base.IN0 +sink_addr[23] => comb.DATAB +sink_addr[23] => source_addr.DATAB +sink_addr[24] => burst_uncompress_address_base.IN0 +sink_addr[24] => comb.DATAB +sink_addr[24] => source_addr.DATAB +sink_addr[25] => burst_uncompress_address_base.IN0 +sink_addr[25] => comb.DATAB +sink_addr[25] => source_addr.DATAB +sink_burstwrap[0] => p1_burst_uncompress_address_offset[0].IN1 +sink_burstwrap[0] => source_burstwrap[0].DATAIN +sink_burstwrap[0] => burst_uncompress_address_base.IN1 +sink_burstwrap[1] => p1_burst_uncompress_address_offset[1].IN1 +sink_burstwrap[1] => source_burstwrap[1].DATAIN +sink_burstwrap[1] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[2].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[25].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[24].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[23].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[22].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[21].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[20].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[19].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[18].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[17].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[16].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[15].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[14].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[13].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[12].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[11].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[10].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[9].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[8].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[7].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[6].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[5].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[4].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[3].IN1 +sink_burstwrap[2] => source_burstwrap[2].DATAIN +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_byte_cnt[0] => source_byte_cnt.DATAB +sink_byte_cnt[0] => Add1.IN6 +sink_byte_cnt[0] => Equal1.IN2 +sink_byte_cnt[1] => source_byte_cnt.DATAB +sink_byte_cnt[1] => Add1.IN5 +sink_byte_cnt[1] => Equal1.IN1 +sink_byte_cnt[2] => source_byte_cnt.DATAB +sink_byte_cnt[2] => Add1.IN4 +sink_byte_cnt[2] => Equal1.IN0 +sink_is_compressed => last_packet_beat.IN1 +sink_burstsize[0] => Decoder0.IN2 +sink_burstsize[0] => source_burstsize[0].DATAIN +sink_burstsize[1] => Decoder0.IN1 +sink_burstsize[1] => source_burstsize[1].DATAIN +sink_burstsize[2] => Decoder0.IN0 +sink_burstsize[2] => source_burstsize[2].DATAIN +source_startofpacket <= source_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +source_endofpacket <= source_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +source_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE +source_ready => always1.IN1 +source_ready => sink_ready.IN1 +source_addr[0] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[1] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[2] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[3] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[4] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[5] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[6] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[7] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[8] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[9] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[10] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[11] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[12] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[13] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[14] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[15] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[16] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[17] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[18] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[19] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[20] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[21] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[22] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[23] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[24] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[25] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_burstwrap[0] <= sink_burstwrap[0].DB_MAX_OUTPUT_PORT_TYPE +source_burstwrap[1] <= sink_burstwrap[1].DB_MAX_OUTPUT_PORT_TYPE +source_burstwrap[2] <= sink_burstwrap[2].DB_MAX_OUTPUT_PORT_TYPE +source_byte_cnt[0] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE +source_byte_cnt[1] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE +source_byte_cnt[2] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE +source_is_compressed <= +source_burstsize[0] <= sink_burstsize[0].DB_MAX_OUTPUT_PORT_TYPE +source_burstsize[1] <= sink_burstsize[1].DB_MAX_OUTPUT_PORT_TYPE +source_burstsize[2] <= sink_burstsize[2].DB_MAX_OUTPUT_PORT_TYPE + + +|de0_nano_system|system:inst_cpu|altera_avalon_sc_fifo:sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo +clk => csr_readdata[0]~reg0.CLK +clk => csr_readdata[1]~reg0.CLK +clk => csr_readdata[2]~reg0.CLK +clk => csr_readdata[3]~reg0.CLK +clk => csr_readdata[4]~reg0.CLK +clk => csr_readdata[5]~reg0.CLK +clk => csr_readdata[6]~reg0.CLK +clk => csr_readdata[7]~reg0.CLK +clk => csr_readdata[8]~reg0.CLK +clk => csr_readdata[9]~reg0.CLK +clk => csr_readdata[10]~reg0.CLK +clk => csr_readdata[11]~reg0.CLK +clk => csr_readdata[12]~reg0.CLK +clk => csr_readdata[13]~reg0.CLK +clk => csr_readdata[14]~reg0.CLK +clk => csr_readdata[15]~reg0.CLK +clk => csr_readdata[16]~reg0.CLK +clk => csr_readdata[17]~reg0.CLK +clk => csr_readdata[18]~reg0.CLK +clk => csr_readdata[19]~reg0.CLK +clk => csr_readdata[20]~reg0.CLK +clk => csr_readdata[21]~reg0.CLK +clk => csr_readdata[22]~reg0.CLK +clk => csr_readdata[23]~reg0.CLK +clk => csr_readdata[24]~reg0.CLK +clk => csr_readdata[25]~reg0.CLK +clk => csr_readdata[26]~reg0.CLK +clk => csr_readdata[27]~reg0.CLK +clk => csr_readdata[28]~reg0.CLK +clk => csr_readdata[29]~reg0.CLK +clk => csr_readdata[30]~reg0.CLK +clk => csr_readdata[31]~reg0.CLK +clk => mem_used[1].CLK +clk => mem_used[0].CLK +clk => mem[1][0].CLK +clk => mem[1][1].CLK +clk => mem[1][2].CLK +clk => mem[1][3].CLK +clk => mem[1][4].CLK +clk => mem[1][5].CLK +clk => mem[1][6].CLK +clk => mem[1][7].CLK +clk => mem[1][8].CLK +clk => mem[1][9].CLK +clk => mem[1][10].CLK +clk => mem[1][11].CLK +clk => mem[1][12].CLK +clk => mem[1][13].CLK +clk => mem[1][14].CLK +clk => mem[1][15].CLK +clk => mem[1][16].CLK +clk => mem[1][17].CLK +clk => mem[1][18].CLK +clk => mem[1][19].CLK +clk => mem[1][20].CLK +clk => mem[1][21].CLK +clk => mem[1][22].CLK +clk => mem[1][23].CLK +clk => mem[1][24].CLK +clk => mem[1][25].CLK +clk => mem[1][26].CLK +clk => mem[1][27].CLK +clk => mem[1][28].CLK +clk => mem[1][29].CLK +clk => mem[1][30].CLK +clk => mem[1][31].CLK +clk => mem[1][32].CLK +clk => mem[1][33].CLK +clk => mem[1][34].CLK +clk => mem[1][35].CLK +clk => mem[1][36].CLK +clk => mem[1][37].CLK +clk => mem[1][38].CLK +clk => mem[1][39].CLK +clk => mem[1][40].CLK +clk => mem[1][41].CLK +clk => mem[1][42].CLK +clk => mem[1][43].CLK +clk => mem[1][44].CLK +clk => mem[1][45].CLK +clk => mem[1][46].CLK +clk => mem[1][47].CLK +clk => mem[1][48].CLK +clk => mem[1][49].CLK +clk => mem[1][50].CLK +clk => mem[1][51].CLK +clk => mem[1][52].CLK +clk => mem[1][53].CLK +clk => mem[1][54].CLK +clk => mem[1][55].CLK +clk => mem[1][56].CLK +clk => mem[1][57].CLK +clk => mem[1][58].CLK +clk => mem[1][59].CLK +clk => mem[1][60].CLK +clk => mem[1][61].CLK +clk => mem[1][62].CLK +clk => mem[1][63].CLK +clk => mem[1][64].CLK +clk => mem[1][65].CLK +clk => mem[1][66].CLK +clk => mem[1][67].CLK +clk => mem[1][68].CLK +clk => mem[1][69].CLK +clk => mem[1][70].CLK +clk => mem[1][71].CLK +clk => mem[1][72].CLK +clk => mem[1][73].CLK +clk => mem[1][74].CLK +clk => mem[1][75].CLK +clk => mem[1][76].CLK +clk => mem[1][77].CLK +clk => mem[1][78].CLK +clk => mem[1][79].CLK +clk => mem[1][80].CLK +clk => mem[1][81].CLK +clk => mem[1][82].CLK +clk => mem[1][83].CLK +clk => mem[1][84].CLK +clk => mem[1][85].CLK +clk => mem[1][86].CLK +clk => mem[1][87].CLK +clk => mem[1][88].CLK +clk => mem[1][89].CLK +clk => mem[1][90].CLK +clk => mem[1][91].CLK +clk => mem[1][92].CLK +clk => mem[1][93].CLK +clk => mem[1][94].CLK +clk => mem[1][95].CLK +clk => mem[1][96].CLK +clk => mem[1][97].CLK +clk => mem[1][98].CLK +clk => mem[1][99].CLK +clk => mem[1][100].CLK +clk => mem[1][101].CLK +clk => mem[1][102].CLK +clk => mem[1][103].CLK +clk => mem[0][0].CLK +clk => mem[0][1].CLK +clk => mem[0][2].CLK +clk => mem[0][3].CLK +clk => mem[0][4].CLK +clk => mem[0][5].CLK +clk => mem[0][6].CLK +clk => mem[0][7].CLK +clk => mem[0][8].CLK +clk => mem[0][9].CLK +clk => mem[0][10].CLK +clk => mem[0][11].CLK +clk => mem[0][12].CLK +clk => mem[0][13].CLK +clk => mem[0][14].CLK +clk => mem[0][15].CLK +clk => mem[0][16].CLK +clk => mem[0][17].CLK +clk => mem[0][18].CLK +clk => mem[0][19].CLK +clk => mem[0][20].CLK +clk => mem[0][21].CLK +clk => mem[0][22].CLK +clk => mem[0][23].CLK +clk => mem[0][24].CLK +clk => mem[0][25].CLK +clk => mem[0][26].CLK +clk => mem[0][27].CLK +clk => mem[0][28].CLK +clk => mem[0][29].CLK +clk => mem[0][30].CLK +clk => mem[0][31].CLK +clk => mem[0][32].CLK +clk => mem[0][33].CLK +clk => mem[0][34].CLK +clk => mem[0][35].CLK +clk => mem[0][36].CLK +clk => mem[0][37].CLK +clk => mem[0][38].CLK +clk => mem[0][39].CLK +clk => mem[0][40].CLK +clk => mem[0][41].CLK +clk => mem[0][42].CLK +clk => mem[0][43].CLK +clk => mem[0][44].CLK +clk => mem[0][45].CLK +clk => mem[0][46].CLK +clk => mem[0][47].CLK +clk => mem[0][48].CLK +clk => mem[0][49].CLK +clk => mem[0][50].CLK +clk => mem[0][51].CLK +clk => mem[0][52].CLK +clk => mem[0][53].CLK +clk => mem[0][54].CLK +clk => mem[0][55].CLK +clk => mem[0][56].CLK +clk => mem[0][57].CLK +clk => mem[0][58].CLK +clk => mem[0][59].CLK +clk => mem[0][60].CLK +clk => mem[0][61].CLK +clk => mem[0][62].CLK +clk => mem[0][63].CLK +clk => mem[0][64].CLK +clk => mem[0][65].CLK +clk => mem[0][66].CLK +clk => mem[0][67].CLK +clk => mem[0][68].CLK +clk => mem[0][69].CLK +clk => mem[0][70].CLK +clk => mem[0][71].CLK +clk => mem[0][72].CLK +clk => mem[0][73].CLK +clk => mem[0][74].CLK +clk => mem[0][75].CLK +clk => mem[0][76].CLK +clk => mem[0][77].CLK +clk => mem[0][78].CLK +clk => mem[0][79].CLK +clk => mem[0][80].CLK +clk => mem[0][81].CLK +clk => mem[0][82].CLK +clk => mem[0][83].CLK +clk => mem[0][84].CLK +clk => mem[0][85].CLK +clk => mem[0][86].CLK +clk => mem[0][87].CLK +clk => mem[0][88].CLK +clk => mem[0][89].CLK +clk => mem[0][90].CLK +clk => mem[0][91].CLK +clk => mem[0][92].CLK +clk => mem[0][93].CLK +clk => mem[0][94].CLK +clk => mem[0][95].CLK +clk => mem[0][96].CLK +clk => mem[0][97].CLK +clk => mem[0][98].CLK +clk => mem[0][99].CLK +clk => mem[0][100].CLK +clk => mem[0][101].CLK +clk => mem[0][102].CLK +clk => mem[0][103].CLK +reset => csr_readdata[0]~reg0.ACLR +reset => csr_readdata[1]~reg0.ACLR +reset => csr_readdata[2]~reg0.ACLR +reset => csr_readdata[3]~reg0.ACLR +reset => csr_readdata[4]~reg0.ACLR +reset => csr_readdata[5]~reg0.ACLR +reset => csr_readdata[6]~reg0.ACLR +reset => csr_readdata[7]~reg0.ACLR +reset => csr_readdata[8]~reg0.ACLR +reset => csr_readdata[9]~reg0.ACLR +reset => csr_readdata[10]~reg0.ACLR +reset => csr_readdata[11]~reg0.ACLR +reset => csr_readdata[12]~reg0.ACLR +reset => csr_readdata[13]~reg0.ACLR +reset => csr_readdata[14]~reg0.ACLR +reset => csr_readdata[15]~reg0.ACLR +reset => csr_readdata[16]~reg0.ACLR +reset => csr_readdata[17]~reg0.ACLR +reset => csr_readdata[18]~reg0.ACLR +reset => csr_readdata[19]~reg0.ACLR +reset => csr_readdata[20]~reg0.ACLR +reset => csr_readdata[21]~reg0.ACLR +reset => csr_readdata[22]~reg0.ACLR +reset => csr_readdata[23]~reg0.ACLR +reset => csr_readdata[24]~reg0.ACLR +reset => csr_readdata[25]~reg0.ACLR +reset => csr_readdata[26]~reg0.ACLR +reset => csr_readdata[27]~reg0.ACLR +reset => csr_readdata[28]~reg0.ACLR +reset => csr_readdata[29]~reg0.ACLR +reset => csr_readdata[30]~reg0.ACLR +reset => csr_readdata[31]~reg0.ACLR +reset => mem_used[1].ACLR +reset => mem_used[0].ACLR +reset => mem[1][0].ACLR +reset => mem[1][1].ACLR +reset => mem[1][2].ACLR +reset => mem[1][3].ACLR +reset => mem[1][4].ACLR +reset => mem[1][5].ACLR +reset => mem[1][6].ACLR +reset => mem[1][7].ACLR +reset => mem[1][8].ACLR +reset => mem[1][9].ACLR +reset => mem[1][10].ACLR +reset => mem[1][11].ACLR +reset => mem[1][12].ACLR +reset => mem[1][13].ACLR +reset => mem[1][14].ACLR +reset => mem[1][15].ACLR +reset => mem[1][16].ACLR +reset => mem[1][17].ACLR +reset => mem[1][18].ACLR +reset => mem[1][19].ACLR +reset => mem[1][20].ACLR +reset => mem[1][21].ACLR +reset => mem[1][22].ACLR +reset => mem[1][23].ACLR +reset => mem[1][24].ACLR +reset => mem[1][25].ACLR +reset => mem[1][26].ACLR +reset => mem[1][27].ACLR +reset => mem[1][28].ACLR +reset => mem[1][29].ACLR +reset => mem[1][30].ACLR +reset => mem[1][31].ACLR +reset => mem[1][32].ACLR +reset => mem[1][33].ACLR +reset => mem[1][34].ACLR +reset => mem[1][35].ACLR +reset => mem[1][36].ACLR +reset => mem[1][37].ACLR +reset => mem[1][38].ACLR +reset => mem[1][39].ACLR +reset => mem[1][40].ACLR +reset => mem[1][41].ACLR +reset => mem[1][42].ACLR +reset => mem[1][43].ACLR +reset => mem[1][44].ACLR +reset => mem[1][45].ACLR +reset => mem[1][46].ACLR +reset => mem[1][47].ACLR +reset => mem[1][48].ACLR +reset => mem[1][49].ACLR +reset => mem[1][50].ACLR +reset => mem[1][51].ACLR +reset => mem[1][52].ACLR +reset => mem[1][53].ACLR +reset => mem[1][54].ACLR +reset => mem[1][55].ACLR +reset => mem[1][56].ACLR +reset => mem[1][57].ACLR +reset => mem[1][58].ACLR +reset => mem[1][59].ACLR +reset => mem[1][60].ACLR +reset => mem[1][61].ACLR +reset => mem[1][62].ACLR +reset => mem[1][63].ACLR +reset => mem[1][64].ACLR +reset => mem[1][65].ACLR +reset => mem[1][66].ACLR +reset => mem[1][67].ACLR +reset => mem[1][68].ACLR +reset => mem[1][69].ACLR +reset => mem[1][70].ACLR +reset => mem[1][71].ACLR +reset => mem[1][72].ACLR +reset => mem[1][73].ACLR +reset => mem[1][74].ACLR +reset => mem[1][75].ACLR +reset => mem[1][76].ACLR +reset => mem[1][77].ACLR +reset => mem[1][78].ACLR +reset => mem[1][79].ACLR +reset => mem[1][80].ACLR +reset => mem[1][81].ACLR +reset => mem[1][82].ACLR +reset => mem[1][83].ACLR +reset => mem[1][84].ACLR +reset => mem[1][85].ACLR +reset => mem[1][86].ACLR +reset => mem[1][87].ACLR +reset => mem[1][88].ACLR +reset => mem[1][89].ACLR +reset => mem[1][90].ACLR +reset => mem[1][91].ACLR +reset => mem[1][92].ACLR +reset => mem[1][93].ACLR +reset => mem[1][94].ACLR +reset => mem[1][95].ACLR +reset => mem[1][96].ACLR +reset => mem[1][97].ACLR +reset => mem[1][98].ACLR +reset => mem[1][99].ACLR +reset => mem[1][100].ACLR +reset => mem[1][101].ACLR +reset => mem[1][102].ACLR +reset => mem[1][103].ACLR +reset => mem[0][0].ACLR +reset => mem[0][1].ACLR +reset => mem[0][2].ACLR +reset => mem[0][3].ACLR +reset => mem[0][4].ACLR +reset => mem[0][5].ACLR +reset => mem[0][6].ACLR +reset => mem[0][7].ACLR +reset => mem[0][8].ACLR +reset => mem[0][9].ACLR +reset => mem[0][10].ACLR +reset => mem[0][11].ACLR +reset => mem[0][12].ACLR +reset => mem[0][13].ACLR +reset => mem[0][14].ACLR +reset => mem[0][15].ACLR +reset => mem[0][16].ACLR +reset => mem[0][17].ACLR +reset => mem[0][18].ACLR +reset => mem[0][19].ACLR +reset => mem[0][20].ACLR +reset => mem[0][21].ACLR +reset => mem[0][22].ACLR +reset => mem[0][23].ACLR +reset => mem[0][24].ACLR +reset => mem[0][25].ACLR +reset => mem[0][26].ACLR +reset => mem[0][27].ACLR +reset => mem[0][28].ACLR +reset => mem[0][29].ACLR +reset => mem[0][30].ACLR +reset => mem[0][31].ACLR +reset => mem[0][32].ACLR +reset => mem[0][33].ACLR +reset => mem[0][34].ACLR +reset => mem[0][35].ACLR +reset => mem[0][36].ACLR +reset => mem[0][37].ACLR +reset => mem[0][38].ACLR +reset => mem[0][39].ACLR +reset => mem[0][40].ACLR +reset => mem[0][41].ACLR +reset => mem[0][42].ACLR +reset => mem[0][43].ACLR +reset => mem[0][44].ACLR +reset => mem[0][45].ACLR +reset => mem[0][46].ACLR +reset => mem[0][47].ACLR +reset => mem[0][48].ACLR +reset => mem[0][49].ACLR +reset => mem[0][50].ACLR +reset => mem[0][51].ACLR +reset => mem[0][52].ACLR +reset => mem[0][53].ACLR +reset => mem[0][54].ACLR +reset => mem[0][55].ACLR +reset => mem[0][56].ACLR +reset => mem[0][57].ACLR +reset => mem[0][58].ACLR +reset => mem[0][59].ACLR +reset => mem[0][60].ACLR +reset => mem[0][61].ACLR +reset => mem[0][62].ACLR +reset => mem[0][63].ACLR +reset => mem[0][64].ACLR +reset => mem[0][65].ACLR +reset => mem[0][66].ACLR +reset => mem[0][67].ACLR +reset => mem[0][68].ACLR +reset => mem[0][69].ACLR +reset => mem[0][70].ACLR +reset => mem[0][71].ACLR +reset => mem[0][72].ACLR +reset => mem[0][73].ACLR +reset => mem[0][74].ACLR +reset => mem[0][75].ACLR +reset => mem[0][76].ACLR +reset => mem[0][77].ACLR +reset => mem[0][78].ACLR +reset => mem[0][79].ACLR +reset => mem[0][80].ACLR +reset => mem[0][81].ACLR +reset => mem[0][82].ACLR +reset => mem[0][83].ACLR +reset => mem[0][84].ACLR +reset => mem[0][85].ACLR +reset => mem[0][86].ACLR +reset => mem[0][87].ACLR +reset => mem[0][88].ACLR +reset => mem[0][89].ACLR +reset => mem[0][90].ACLR +reset => mem[0][91].ACLR +reset => mem[0][92].ACLR +reset => mem[0][93].ACLR +reset => mem[0][94].ACLR +reset => mem[0][95].ACLR +reset => mem[0][96].ACLR +reset => mem[0][97].ACLR +reset => mem[0][98].ACLR +reset => mem[0][99].ACLR +reset => mem[0][100].ACLR +reset => mem[0][101].ACLR +reset => mem[0][102].ACLR +reset => mem[0][103].ACLR +in_data[0] => mem.DATAB +in_data[1] => mem.DATAB +in_data[2] => mem.DATAB +in_data[3] => mem.DATAB +in_data[4] => mem.DATAB +in_data[5] => mem.DATAB +in_data[6] => mem.DATAB +in_data[7] => mem.DATAB +in_data[8] => mem.DATAB +in_data[9] => mem.DATAB +in_data[10] => mem.DATAB +in_data[11] => mem.DATAB +in_data[12] => mem.DATAB +in_data[13] => mem.DATAB +in_data[14] => mem.DATAB +in_data[15] => mem.DATAB +in_data[16] => mem.DATAB +in_data[17] => mem.DATAB +in_data[18] => mem.DATAB +in_data[19] => mem.DATAB +in_data[20] => mem.DATAB +in_data[21] => mem.DATAB +in_data[22] => mem.DATAB +in_data[23] => mem.DATAB +in_data[24] => mem.DATAB +in_data[25] => mem.DATAB +in_data[26] => mem.DATAB +in_data[27] => mem.DATAB +in_data[28] => mem.DATAB +in_data[29] => mem.DATAB +in_data[30] => mem.DATAB +in_data[31] => mem.DATAB +in_data[32] => mem.DATAB +in_data[33] => mem.DATAB +in_data[34] => mem.DATAB +in_data[35] => mem.DATAB +in_data[36] => mem.DATAB +in_data[37] => mem.DATAB +in_data[38] => mem.DATAB +in_data[39] => mem.DATAB +in_data[40] => mem.DATAB +in_data[41] => mem.DATAB +in_data[42] => mem.DATAB +in_data[43] => mem.DATAB +in_data[44] => mem.DATAB +in_data[45] => mem.DATAB +in_data[46] => mem.DATAB +in_data[47] => mem.DATAB +in_data[48] => mem.DATAB +in_data[49] => mem.DATAB +in_data[50] => mem.DATAB +in_data[51] => mem.DATAB +in_data[52] => mem.DATAB +in_data[53] => mem.DATAB +in_data[54] => mem.DATAB +in_data[55] => mem.DATAB +in_data[56] => mem.DATAB +in_data[57] => mem.DATAB +in_data[58] => mem.DATAB +in_data[59] => mem.DATAB +in_data[60] => mem.DATAB +in_data[61] => mem.DATAB +in_data[62] => mem.DATAB +in_data[63] => mem.DATAB +in_data[64] => mem.DATAB +in_data[65] => mem.DATAB +in_data[66] => mem.DATAB +in_data[67] => mem.DATAB +in_data[68] => mem.DATAB +in_data[69] => mem.DATAB +in_data[70] => mem.DATAB +in_data[71] => mem.DATAB +in_data[72] => mem.DATAB +in_data[73] => mem.DATAB +in_data[74] => mem.DATAB +in_data[75] => mem.DATAB +in_data[76] => mem.DATAB +in_data[77] => mem.DATAB +in_data[78] => mem.DATAB +in_data[79] => mem.DATAB +in_data[80] => mem.DATAB +in_data[81] => mem.DATAB +in_data[82] => mem.DATAB +in_data[83] => mem.DATAB +in_data[84] => mem.DATAB +in_data[85] => mem.DATAB +in_data[86] => mem.DATAB +in_data[87] => mem.DATAB +in_data[88] => mem.DATAB +in_data[89] => mem.DATAB +in_data[90] => mem.DATAB +in_data[91] => mem.DATAB +in_data[92] => mem.DATAB +in_data[93] => mem.DATAB +in_data[94] => mem.DATAB +in_data[95] => mem.DATAB +in_data[96] => mem.DATAB +in_data[97] => mem.DATAB +in_data[98] => mem.DATAB +in_data[99] => mem.DATAB +in_data[100] => mem.DATAB +in_data[101] => mem.DATAB +in_valid => write.IN1 +in_startofpacket => mem.DATAB +in_endofpacket => mem.DATAB +in_empty[0] => ~NO_FANOUT~ +in_error[0] => out_error[0].DATAIN +in_error[0] => out_empty[0].DATAIN +in_channel[0] => out_channel[0].DATAIN +in_ready <= mem_used[1].DB_MAX_OUTPUT_PORT_TYPE +out_data[0] <= mem[0][0].DB_MAX_OUTPUT_PORT_TYPE +out_data[1] <= mem[0][1].DB_MAX_OUTPUT_PORT_TYPE +out_data[2] <= mem[0][2].DB_MAX_OUTPUT_PORT_TYPE +out_data[3] <= mem[0][3].DB_MAX_OUTPUT_PORT_TYPE +out_data[4] <= mem[0][4].DB_MAX_OUTPUT_PORT_TYPE +out_data[5] <= mem[0][5].DB_MAX_OUTPUT_PORT_TYPE +out_data[6] <= mem[0][6].DB_MAX_OUTPUT_PORT_TYPE +out_data[7] <= mem[0][7].DB_MAX_OUTPUT_PORT_TYPE +out_data[8] <= mem[0][8].DB_MAX_OUTPUT_PORT_TYPE +out_data[9] <= mem[0][9].DB_MAX_OUTPUT_PORT_TYPE +out_data[10] <= mem[0][10].DB_MAX_OUTPUT_PORT_TYPE +out_data[11] <= mem[0][11].DB_MAX_OUTPUT_PORT_TYPE +out_data[12] <= mem[0][12].DB_MAX_OUTPUT_PORT_TYPE +out_data[13] <= mem[0][13].DB_MAX_OUTPUT_PORT_TYPE +out_data[14] <= mem[0][14].DB_MAX_OUTPUT_PORT_TYPE +out_data[15] <= mem[0][15].DB_MAX_OUTPUT_PORT_TYPE +out_data[16] <= mem[0][16].DB_MAX_OUTPUT_PORT_TYPE +out_data[17] <= mem[0][17].DB_MAX_OUTPUT_PORT_TYPE +out_data[18] <= mem[0][18].DB_MAX_OUTPUT_PORT_TYPE +out_data[19] <= mem[0][19].DB_MAX_OUTPUT_PORT_TYPE +out_data[20] <= mem[0][20].DB_MAX_OUTPUT_PORT_TYPE +out_data[21] <= mem[0][21].DB_MAX_OUTPUT_PORT_TYPE +out_data[22] <= mem[0][22].DB_MAX_OUTPUT_PORT_TYPE +out_data[23] <= mem[0][23].DB_MAX_OUTPUT_PORT_TYPE +out_data[24] <= mem[0][24].DB_MAX_OUTPUT_PORT_TYPE +out_data[25] <= mem[0][25].DB_MAX_OUTPUT_PORT_TYPE +out_data[26] <= mem[0][26].DB_MAX_OUTPUT_PORT_TYPE +out_data[27] <= mem[0][27].DB_MAX_OUTPUT_PORT_TYPE +out_data[28] <= mem[0][28].DB_MAX_OUTPUT_PORT_TYPE +out_data[29] <= mem[0][29].DB_MAX_OUTPUT_PORT_TYPE +out_data[30] <= mem[0][30].DB_MAX_OUTPUT_PORT_TYPE +out_data[31] <= mem[0][31].DB_MAX_OUTPUT_PORT_TYPE +out_data[32] <= mem[0][32].DB_MAX_OUTPUT_PORT_TYPE +out_data[33] <= mem[0][33].DB_MAX_OUTPUT_PORT_TYPE +out_data[34] <= mem[0][34].DB_MAX_OUTPUT_PORT_TYPE +out_data[35] <= mem[0][35].DB_MAX_OUTPUT_PORT_TYPE +out_data[36] <= mem[0][36].DB_MAX_OUTPUT_PORT_TYPE +out_data[37] <= mem[0][37].DB_MAX_OUTPUT_PORT_TYPE +out_data[38] <= mem[0][38].DB_MAX_OUTPUT_PORT_TYPE +out_data[39] <= mem[0][39].DB_MAX_OUTPUT_PORT_TYPE +out_data[40] <= mem[0][40].DB_MAX_OUTPUT_PORT_TYPE +out_data[41] <= mem[0][41].DB_MAX_OUTPUT_PORT_TYPE +out_data[42] <= mem[0][42].DB_MAX_OUTPUT_PORT_TYPE +out_data[43] <= mem[0][43].DB_MAX_OUTPUT_PORT_TYPE +out_data[44] <= mem[0][44].DB_MAX_OUTPUT_PORT_TYPE +out_data[45] <= mem[0][45].DB_MAX_OUTPUT_PORT_TYPE +out_data[46] <= mem[0][46].DB_MAX_OUTPUT_PORT_TYPE +out_data[47] <= mem[0][47].DB_MAX_OUTPUT_PORT_TYPE +out_data[48] <= mem[0][48].DB_MAX_OUTPUT_PORT_TYPE +out_data[49] <= mem[0][49].DB_MAX_OUTPUT_PORT_TYPE +out_data[50] <= mem[0][50].DB_MAX_OUTPUT_PORT_TYPE +out_data[51] <= mem[0][51].DB_MAX_OUTPUT_PORT_TYPE +out_data[52] <= mem[0][52].DB_MAX_OUTPUT_PORT_TYPE +out_data[53] <= mem[0][53].DB_MAX_OUTPUT_PORT_TYPE +out_data[54] <= mem[0][54].DB_MAX_OUTPUT_PORT_TYPE +out_data[55] <= mem[0][55].DB_MAX_OUTPUT_PORT_TYPE +out_data[56] <= mem[0][56].DB_MAX_OUTPUT_PORT_TYPE +out_data[57] <= mem[0][57].DB_MAX_OUTPUT_PORT_TYPE +out_data[58] <= mem[0][58].DB_MAX_OUTPUT_PORT_TYPE +out_data[59] <= mem[0][59].DB_MAX_OUTPUT_PORT_TYPE +out_data[60] <= mem[0][60].DB_MAX_OUTPUT_PORT_TYPE +out_data[61] <= mem[0][61].DB_MAX_OUTPUT_PORT_TYPE +out_data[62] <= mem[0][62].DB_MAX_OUTPUT_PORT_TYPE +out_data[63] <= mem[0][63].DB_MAX_OUTPUT_PORT_TYPE +out_data[64] <= mem[0][64].DB_MAX_OUTPUT_PORT_TYPE +out_data[65] <= mem[0][65].DB_MAX_OUTPUT_PORT_TYPE +out_data[66] <= mem[0][66].DB_MAX_OUTPUT_PORT_TYPE +out_data[67] <= mem[0][67].DB_MAX_OUTPUT_PORT_TYPE +out_data[68] <= mem[0][68].DB_MAX_OUTPUT_PORT_TYPE +out_data[69] <= mem[0][69].DB_MAX_OUTPUT_PORT_TYPE +out_data[70] <= mem[0][70].DB_MAX_OUTPUT_PORT_TYPE +out_data[71] <= mem[0][71].DB_MAX_OUTPUT_PORT_TYPE +out_data[72] <= mem[0][72].DB_MAX_OUTPUT_PORT_TYPE +out_data[73] <= mem[0][73].DB_MAX_OUTPUT_PORT_TYPE +out_data[74] <= mem[0][74].DB_MAX_OUTPUT_PORT_TYPE +out_data[75] <= mem[0][75].DB_MAX_OUTPUT_PORT_TYPE +out_data[76] <= mem[0][76].DB_MAX_OUTPUT_PORT_TYPE +out_data[77] <= mem[0][77].DB_MAX_OUTPUT_PORT_TYPE +out_data[78] <= mem[0][78].DB_MAX_OUTPUT_PORT_TYPE +out_data[79] <= mem[0][79].DB_MAX_OUTPUT_PORT_TYPE +out_data[80] <= mem[0][80].DB_MAX_OUTPUT_PORT_TYPE +out_data[81] <= mem[0][81].DB_MAX_OUTPUT_PORT_TYPE +out_data[82] <= mem[0][82].DB_MAX_OUTPUT_PORT_TYPE +out_data[83] <= mem[0][83].DB_MAX_OUTPUT_PORT_TYPE +out_data[84] <= mem[0][84].DB_MAX_OUTPUT_PORT_TYPE +out_data[85] <= mem[0][85].DB_MAX_OUTPUT_PORT_TYPE +out_data[86] <= mem[0][86].DB_MAX_OUTPUT_PORT_TYPE +out_data[87] <= mem[0][87].DB_MAX_OUTPUT_PORT_TYPE +out_data[88] <= mem[0][88].DB_MAX_OUTPUT_PORT_TYPE +out_data[89] <= mem[0][89].DB_MAX_OUTPUT_PORT_TYPE +out_data[90] <= mem[0][90].DB_MAX_OUTPUT_PORT_TYPE +out_data[91] <= mem[0][91].DB_MAX_OUTPUT_PORT_TYPE +out_data[92] <= mem[0][92].DB_MAX_OUTPUT_PORT_TYPE +out_data[93] <= mem[0][93].DB_MAX_OUTPUT_PORT_TYPE +out_data[94] <= mem[0][94].DB_MAX_OUTPUT_PORT_TYPE +out_data[95] <= mem[0][95].DB_MAX_OUTPUT_PORT_TYPE +out_data[96] <= mem[0][96].DB_MAX_OUTPUT_PORT_TYPE +out_data[97] <= mem[0][97].DB_MAX_OUTPUT_PORT_TYPE +out_data[98] <= mem[0][98].DB_MAX_OUTPUT_PORT_TYPE +out_data[99] <= mem[0][99].DB_MAX_OUTPUT_PORT_TYPE +out_data[100] <= mem[0][100].DB_MAX_OUTPUT_PORT_TYPE +out_data[101] <= mem[0][101].DB_MAX_OUTPUT_PORT_TYPE +out_valid <= mem_used[0].DB_MAX_OUTPUT_PORT_TYPE +out_startofpacket <= mem[0][103].DB_MAX_OUTPUT_PORT_TYPE +out_endofpacket <= mem[0][102].DB_MAX_OUTPUT_PORT_TYPE +out_empty[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE +out_error[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE +out_channel[0] <= in_channel[0].DB_MAX_OUTPUT_PORT_TYPE +out_ready => internal_out_ready.IN1 +csr_address[0] => ~NO_FANOUT~ +csr_address[1] => ~NO_FANOUT~ +csr_write => ~NO_FANOUT~ +csr_read => csr_readdata[0]~reg0.ENA +csr_read => csr_readdata[31]~reg0.ENA +csr_read => csr_readdata[30]~reg0.ENA +csr_read => csr_readdata[29]~reg0.ENA +csr_read => csr_readdata[28]~reg0.ENA +csr_read => csr_readdata[27]~reg0.ENA +csr_read => csr_readdata[26]~reg0.ENA +csr_read => csr_readdata[25]~reg0.ENA +csr_read => csr_readdata[24]~reg0.ENA +csr_read => csr_readdata[23]~reg0.ENA +csr_read => csr_readdata[22]~reg0.ENA +csr_read => csr_readdata[21]~reg0.ENA +csr_read => csr_readdata[20]~reg0.ENA +csr_read => csr_readdata[19]~reg0.ENA +csr_read => csr_readdata[18]~reg0.ENA +csr_read => csr_readdata[17]~reg0.ENA +csr_read => csr_readdata[16]~reg0.ENA +csr_read => csr_readdata[15]~reg0.ENA +csr_read => csr_readdata[14]~reg0.ENA +csr_read => csr_readdata[13]~reg0.ENA +csr_read => csr_readdata[12]~reg0.ENA +csr_read => csr_readdata[11]~reg0.ENA +csr_read => csr_readdata[10]~reg0.ENA +csr_read => csr_readdata[9]~reg0.ENA +csr_read => csr_readdata[8]~reg0.ENA +csr_read => csr_readdata[7]~reg0.ENA +csr_read => csr_readdata[6]~reg0.ENA +csr_read => csr_readdata[5]~reg0.ENA +csr_read => csr_readdata[4]~reg0.ENA +csr_read => csr_readdata[3]~reg0.ENA +csr_read => csr_readdata[2]~reg0.ENA +csr_read => csr_readdata[1]~reg0.ENA +csr_writedata[0] => ~NO_FANOUT~ +csr_writedata[1] => ~NO_FANOUT~ +csr_writedata[2] => ~NO_FANOUT~ +csr_writedata[3] => ~NO_FANOUT~ +csr_writedata[4] => ~NO_FANOUT~ +csr_writedata[5] => ~NO_FANOUT~ +csr_writedata[6] => ~NO_FANOUT~ +csr_writedata[7] => ~NO_FANOUT~ +csr_writedata[8] => ~NO_FANOUT~ +csr_writedata[9] => ~NO_FANOUT~ +csr_writedata[10] => ~NO_FANOUT~ +csr_writedata[11] => ~NO_FANOUT~ +csr_writedata[12] => ~NO_FANOUT~ +csr_writedata[13] => ~NO_FANOUT~ +csr_writedata[14] => ~NO_FANOUT~ +csr_writedata[15] => ~NO_FANOUT~ +csr_writedata[16] => ~NO_FANOUT~ +csr_writedata[17] => ~NO_FANOUT~ +csr_writedata[18] => ~NO_FANOUT~ +csr_writedata[19] => ~NO_FANOUT~ +csr_writedata[20] => ~NO_FANOUT~ +csr_writedata[21] => ~NO_FANOUT~ +csr_writedata[22] => ~NO_FANOUT~ +csr_writedata[23] => ~NO_FANOUT~ +csr_writedata[24] => ~NO_FANOUT~ +csr_writedata[25] => ~NO_FANOUT~ +csr_writedata[26] => ~NO_FANOUT~ +csr_writedata[27] => ~NO_FANOUT~ +csr_writedata[28] => ~NO_FANOUT~ +csr_writedata[29] => ~NO_FANOUT~ +csr_writedata[30] => ~NO_FANOUT~ +csr_writedata[31] => ~NO_FANOUT~ +csr_readdata[0] <= csr_readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[1] <= csr_readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[2] <= csr_readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[3] <= csr_readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[4] <= csr_readdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[5] <= csr_readdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[6] <= csr_readdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[7] <= csr_readdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[8] <= csr_readdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[9] <= csr_readdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[10] <= csr_readdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[11] <= csr_readdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[12] <= csr_readdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[13] <= csr_readdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[14] <= csr_readdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[15] <= csr_readdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[16] <= csr_readdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[17] <= csr_readdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[18] <= csr_readdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[19] <= csr_readdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[20] <= csr_readdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[21] <= csr_readdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[22] <= csr_readdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[23] <= csr_readdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[24] <= csr_readdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[25] <= csr_readdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[26] <= csr_readdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[27] <= csr_readdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[28] <= csr_readdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[29] <= csr_readdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[30] <= csr_readdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[31] <= csr_readdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE +almost_full_data <= +almost_empty_data <= + + +|de0_nano_system|system:inst_cpu|altera_merlin_slave_agent:uart_0_s1_translator_avalon_universal_slave_0_agent +clk => clk.IN1 +reset => reset.IN1 +m0_address[0] <= +m0_address[1] <= +m0_address[2] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE +m0_address[3] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE +m0_address[4] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE +m0_address[5] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE +m0_address[6] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE +m0_address[7] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE +m0_address[8] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE +m0_address[9] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE +m0_address[10] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE +m0_address[11] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE +m0_address[12] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE +m0_address[13] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE +m0_address[14] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE +m0_address[15] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE +m0_address[16] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE +m0_address[17] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE +m0_address[18] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE +m0_address[19] <= cp_data[55].DB_MAX_OUTPUT_PORT_TYPE +m0_address[20] <= cp_data[56].DB_MAX_OUTPUT_PORT_TYPE +m0_address[21] <= cp_data[57].DB_MAX_OUTPUT_PORT_TYPE +m0_address[22] <= cp_data[58].DB_MAX_OUTPUT_PORT_TYPE +m0_address[23] <= cp_data[59].DB_MAX_OUTPUT_PORT_TYPE +m0_address[24] <= cp_data[60].DB_MAX_OUTPUT_PORT_TYPE +m0_address[25] <= cp_data[61].DB_MAX_OUTPUT_PORT_TYPE +m0_burstcount[0] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE +m0_burstcount[1] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE +m0_burstcount[2] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[0] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[1] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[2] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[3] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE +m0_read <= m0_read.DB_MAX_OUTPUT_PORT_TYPE +m0_readdata[0] => rdata_fifo_src_data[0].DATAIN +m0_readdata[1] => rdata_fifo_src_data[1].DATAIN +m0_readdata[2] => rdata_fifo_src_data[2].DATAIN +m0_readdata[3] => rdata_fifo_src_data[3].DATAIN +m0_readdata[4] => rdata_fifo_src_data[4].DATAIN +m0_readdata[5] => rdata_fifo_src_data[5].DATAIN +m0_readdata[6] => rdata_fifo_src_data[6].DATAIN +m0_readdata[7] => rdata_fifo_src_data[7].DATAIN +m0_readdata[8] => rdata_fifo_src_data[8].DATAIN +m0_readdata[9] => rdata_fifo_src_data[9].DATAIN +m0_readdata[10] => rdata_fifo_src_data[10].DATAIN +m0_readdata[11] => rdata_fifo_src_data[11].DATAIN +m0_readdata[12] => rdata_fifo_src_data[12].DATAIN +m0_readdata[13] => rdata_fifo_src_data[13].DATAIN +m0_readdata[14] => rdata_fifo_src_data[14].DATAIN +m0_readdata[15] => rdata_fifo_src_data[15].DATAIN +m0_readdata[16] => rdata_fifo_src_data[16].DATAIN +m0_readdata[17] => rdata_fifo_src_data[17].DATAIN +m0_readdata[18] => rdata_fifo_src_data[18].DATAIN +m0_readdata[19] => rdata_fifo_src_data[19].DATAIN +m0_readdata[20] => rdata_fifo_src_data[20].DATAIN +m0_readdata[21] => rdata_fifo_src_data[21].DATAIN +m0_readdata[22] => rdata_fifo_src_data[22].DATAIN +m0_readdata[23] => rdata_fifo_src_data[23].DATAIN +m0_readdata[24] => rdata_fifo_src_data[24].DATAIN +m0_readdata[25] => rdata_fifo_src_data[25].DATAIN +m0_readdata[26] => rdata_fifo_src_data[26].DATAIN +m0_readdata[27] => rdata_fifo_src_data[27].DATAIN +m0_readdata[28] => rdata_fifo_src_data[28].DATAIN +m0_readdata[29] => rdata_fifo_src_data[29].DATAIN +m0_readdata[30] => rdata_fifo_src_data[30].DATAIN +m0_readdata[31] => rdata_fifo_src_data[31].DATAIN +m0_waitrequest => cp_ready.IN0 +m0_write <= m0_write.DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[0] <= cp_data[0].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[1] <= cp_data[1].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[2] <= cp_data[2].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[3] <= cp_data[3].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[4] <= cp_data[4].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[5] <= cp_data[5].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[6] <= cp_data[6].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[7] <= cp_data[7].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[8] <= cp_data[8].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[9] <= cp_data[9].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[10] <= cp_data[10].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[11] <= cp_data[11].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[12] <= cp_data[12].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[13] <= cp_data[13].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[14] <= cp_data[14].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[15] <= cp_data[15].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[16] <= cp_data[16].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[17] <= cp_data[17].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[18] <= cp_data[18].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[19] <= cp_data[19].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[20] <= cp_data[20].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[21] <= cp_data[21].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[22] <= cp_data[22].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[23] <= cp_data[23].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[24] <= cp_data[24].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[25] <= cp_data[25].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[26] <= cp_data[26].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[27] <= cp_data[27].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[28] <= cp_data[28].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[29] <= cp_data[29].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[30] <= cp_data[30].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[31] <= cp_data[31].DB_MAX_OUTPUT_PORT_TYPE +m0_readdatavalid => rdata_fifo_src_valid.DATAIN +m0_debugaccess <= cp_data[92].DB_MAX_OUTPUT_PORT_TYPE +m0_lock <= m0_lock.DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[0] <= +rf_source_data[1] <= +rf_source_data[2] <= +rf_source_data[3] <= +rf_source_data[4] <= +rf_source_data[5] <= +rf_source_data[6] <= +rf_source_data[7] <= +rf_source_data[8] <= +rf_source_data[9] <= +rf_source_data[10] <= +rf_source_data[11] <= +rf_source_data[12] <= +rf_source_data[13] <= +rf_source_data[14] <= +rf_source_data[15] <= +rf_source_data[16] <= +rf_source_data[17] <= +rf_source_data[18] <= +rf_source_data[19] <= +rf_source_data[20] <= +rf_source_data[21] <= +rf_source_data[22] <= +rf_source_data[23] <= +rf_source_data[24] <= +rf_source_data[25] <= +rf_source_data[26] <= +rf_source_data[27] <= +rf_source_data[28] <= +rf_source_data[29] <= +rf_source_data[30] <= +rf_source_data[31] <= +rf_source_data[32] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[33] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[34] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[35] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[36] <= cp_data[36].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[37] <= cp_data[37].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[38] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[39] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[40] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[41] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[42] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[43] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[44] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[45] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[46] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[47] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[48] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[49] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[50] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[51] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[52] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[53] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[54] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[55] <= cp_data[55].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[56] <= cp_data[56].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[57] <= cp_data[57].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[58] <= cp_data[58].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[59] <= cp_data[59].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[60] <= cp_data[60].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[61] <= cp_data[61].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[62] <= cp_data[62].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[63] <= cp_data[63].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[64] <= cp_data[64].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[65] <= cp_data[65].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[66] <= cp_data[66].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[67] <= cp_data[67].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[68] <= cp_data[68].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[69] <= cp_data[69].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[70] <= cp_data[70].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[71] <= cp_data[71].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[72] <= cp_data[72].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[73] <= cp_data[73].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[74] <= cp_data[74].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[75] <= cp_data[75].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[76] <= cp_data[76].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[77] <= cp_data[77].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[78] <= cp_data[78].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[79] <= cp_data[79].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[80] <= cp_data[80].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[81] <= cp_data[81].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[82] <= cp_data[82].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[83] <= cp_data[83].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[84] <= cp_data[84].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[85] <= cp_data[85].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[86] <= cp_data[86].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[87] <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[88] <= cp_data[88].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[89] <= cp_data[89].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[90] <= cp_data[90].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[91] <= cp_data[91].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[92] <= cp_data[92].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[93] <= +rf_source_data[94] <= +rf_source_data[95] <= cp_data[95].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[96] <= cp_data[96].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[97] <= cp_data[97].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[98] <= cp_data[98].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[99] <= cp_data[99].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[100] <= cp_data[100].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[101] <= nonposted_write_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +rf_source_valid <= rf_source_valid.DB_MAX_OUTPUT_PORT_TYPE +rf_source_startofpacket <= cp_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +rf_source_endofpacket <= cp_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +rf_source_ready => cp_ready.IN1 +rf_source_ready => m0_write.IN1 +rf_source_ready => m0_lock.IN1 +rf_source_ready => rf_source_valid.IN1 +rf_source_ready => m0_read.IN1 +rf_sink_data[0] => ~NO_FANOUT~ +rf_sink_data[1] => ~NO_FANOUT~ +rf_sink_data[2] => ~NO_FANOUT~ +rf_sink_data[3] => ~NO_FANOUT~ +rf_sink_data[4] => ~NO_FANOUT~ +rf_sink_data[5] => ~NO_FANOUT~ +rf_sink_data[6] => ~NO_FANOUT~ +rf_sink_data[7] => ~NO_FANOUT~ +rf_sink_data[8] => ~NO_FANOUT~ +rf_sink_data[9] => ~NO_FANOUT~ +rf_sink_data[10] => ~NO_FANOUT~ +rf_sink_data[11] => ~NO_FANOUT~ +rf_sink_data[12] => ~NO_FANOUT~ +rf_sink_data[13] => ~NO_FANOUT~ +rf_sink_data[14] => ~NO_FANOUT~ +rf_sink_data[15] => ~NO_FANOUT~ +rf_sink_data[16] => ~NO_FANOUT~ +rf_sink_data[17] => ~NO_FANOUT~ +rf_sink_data[18] => ~NO_FANOUT~ +rf_sink_data[19] => ~NO_FANOUT~ +rf_sink_data[20] => ~NO_FANOUT~ +rf_sink_data[21] => ~NO_FANOUT~ +rf_sink_data[22] => ~NO_FANOUT~ +rf_sink_data[23] => ~NO_FANOUT~ +rf_sink_data[24] => ~NO_FANOUT~ +rf_sink_data[25] => ~NO_FANOUT~ +rf_sink_data[26] => ~NO_FANOUT~ +rf_sink_data[27] => ~NO_FANOUT~ +rf_sink_data[28] => ~NO_FANOUT~ +rf_sink_data[29] => ~NO_FANOUT~ +rf_sink_data[30] => ~NO_FANOUT~ +rf_sink_data[31] => ~NO_FANOUT~ +rf_sink_data[32] => rp_data[32].DATAIN +rf_sink_data[33] => rp_data[33].DATAIN +rf_sink_data[34] => rp_data[34].DATAIN +rf_sink_data[35] => rp_data[35].DATAIN +rf_sink_data[36] => rf_sink_addr[0].IN1 +rf_sink_data[37] => rf_sink_addr[1].IN1 +rf_sink_data[38] => rf_sink_addr[2].IN1 +rf_sink_data[39] => rf_sink_addr[3].IN1 +rf_sink_data[40] => rf_sink_addr[4].IN1 +rf_sink_data[41] => rf_sink_addr[5].IN1 +rf_sink_data[42] => rf_sink_addr[6].IN1 +rf_sink_data[43] => rf_sink_addr[7].IN1 +rf_sink_data[44] => rf_sink_addr[8].IN1 +rf_sink_data[45] => rf_sink_addr[9].IN1 +rf_sink_data[46] => rf_sink_addr[10].IN1 +rf_sink_data[47] => rf_sink_addr[11].IN1 +rf_sink_data[48] => rf_sink_addr[12].IN1 +rf_sink_data[49] => rf_sink_addr[13].IN1 +rf_sink_data[50] => rf_sink_addr[14].IN1 +rf_sink_data[51] => rf_sink_addr[15].IN1 +rf_sink_data[52] => rf_sink_addr[16].IN1 +rf_sink_data[53] => rf_sink_addr[17].IN1 +rf_sink_data[54] => rf_sink_addr[18].IN1 +rf_sink_data[55] => rf_sink_addr[19].IN1 +rf_sink_data[56] => rf_sink_addr[20].IN1 +rf_sink_data[57] => rf_sink_addr[21].IN1 +rf_sink_data[58] => rf_sink_addr[22].IN1 +rf_sink_data[59] => rf_sink_addr[23].IN1 +rf_sink_data[60] => rf_sink_addr[24].IN1 +rf_sink_data[61] => rf_sink_addr[25].IN1 +rf_sink_data[62] => rf_sink_compressed.IN1 +rf_sink_data[63] => rp_data[63].DATAIN +rf_sink_data[64] => comb.OUTPUTSELECT +rf_sink_data[64] => rp_data[64].DATAIN +rf_sink_data[65] => rp_data.IN0 +rf_sink_data[66] => rp_data[66].DATAIN +rf_sink_data[67] => rp_data[67].DATAIN +rf_sink_data[68] => rf_sink_byte_cnt[0].IN1 +rf_sink_data[69] => rf_sink_byte_cnt[1].IN1 +rf_sink_data[70] => rf_sink_byte_cnt[2].IN1 +rf_sink_data[71] => rf_sink_burstwrap[0].IN1 +rf_sink_data[72] => rf_sink_burstwrap[1].IN1 +rf_sink_data[73] => rf_sink_burstwrap[2].IN1 +rf_sink_data[74] => rf_sink_burstsize[0].IN1 +rf_sink_data[75] => rf_sink_burstsize[1].IN1 +rf_sink_data[76] => rf_sink_burstsize[2].IN1 +rf_sink_data[77] => rp_data[77].DATAIN +rf_sink_data[78] => rp_data[78].DATAIN +rf_sink_data[79] => rp_data[79].DATAIN +rf_sink_data[80] => rp_data[80].DATAIN +rf_sink_data[81] => rp_data[81].DATAIN +rf_sink_data[82] => rp_data[82].DATAIN +rf_sink_data[83] => rp_data[87].DATAIN +rf_sink_data[84] => rp_data[88].DATAIN +rf_sink_data[85] => rp_data[89].DATAIN +rf_sink_data[86] => rp_data[90].DATAIN +rf_sink_data[87] => rp_data[83].DATAIN +rf_sink_data[88] => rp_data[84].DATAIN +rf_sink_data[89] => rp_data[85].DATAIN +rf_sink_data[90] => rp_data[86].DATAIN +rf_sink_data[91] => rp_data[91].DATAIN +rf_sink_data[92] => rp_data[92].DATAIN +rf_sink_data[93] => rp_data[93].DATAIN +rf_sink_data[94] => rp_data[94].DATAIN +rf_sink_data[95] => rp_data[95].DATAIN +rf_sink_data[96] => rp_data[96].DATAIN +rf_sink_data[97] => rp_data[97].DATAIN +rf_sink_data[98] => rp_data[98].DATAIN +rf_sink_data[99] => ~NO_FANOUT~ +rf_sink_data[100] => ~NO_FANOUT~ +rf_sink_data[101] => rdata_fifo_sink_ready.IN0 +rf_sink_data[101] => comb.IN0 +rf_sink_valid => rdata_fifo_sink_ready.IN1 +rf_sink_valid => comb.IN1 +rf_sink_startofpacket => comb.DATAA +rf_sink_endofpacket => rf_sink_endofpacket.IN1 +rf_sink_ready <= altera_merlin_burst_uncompressor:uncompressor.sink_ready +rdata_fifo_src_data[0] <= m0_readdata[0].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[1] <= m0_readdata[1].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[2] <= m0_readdata[2].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[3] <= m0_readdata[3].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[4] <= m0_readdata[4].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[5] <= m0_readdata[5].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[6] <= m0_readdata[6].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[7] <= m0_readdata[7].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[8] <= m0_readdata[8].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[9] <= m0_readdata[9].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[10] <= m0_readdata[10].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[11] <= m0_readdata[11].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[12] <= m0_readdata[12].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[13] <= m0_readdata[13].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[14] <= m0_readdata[14].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[15] <= m0_readdata[15].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[16] <= m0_readdata[16].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[17] <= m0_readdata[17].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[18] <= m0_readdata[18].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[19] <= m0_readdata[19].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[20] <= m0_readdata[20].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[21] <= m0_readdata[21].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[22] <= m0_readdata[22].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[23] <= m0_readdata[23].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[24] <= m0_readdata[24].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[25] <= m0_readdata[25].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[26] <= m0_readdata[26].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[27] <= m0_readdata[27].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[28] <= m0_readdata[28].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[29] <= m0_readdata[29].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[30] <= m0_readdata[30].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[31] <= m0_readdata[31].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_valid <= m0_readdatavalid.DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_ready => ~NO_FANOUT~ +rdata_fifo_sink_data[0] => rp_data[0].DATAIN +rdata_fifo_sink_data[1] => rp_data[1].DATAIN +rdata_fifo_sink_data[2] => rp_data[2].DATAIN +rdata_fifo_sink_data[3] => rp_data[3].DATAIN +rdata_fifo_sink_data[4] => rp_data[4].DATAIN +rdata_fifo_sink_data[5] => rp_data[5].DATAIN +rdata_fifo_sink_data[6] => rp_data[6].DATAIN +rdata_fifo_sink_data[7] => rp_data[7].DATAIN +rdata_fifo_sink_data[8] => rp_data[8].DATAIN +rdata_fifo_sink_data[9] => rp_data[9].DATAIN +rdata_fifo_sink_data[10] => rp_data[10].DATAIN +rdata_fifo_sink_data[11] => rp_data[11].DATAIN +rdata_fifo_sink_data[12] => rp_data[12].DATAIN +rdata_fifo_sink_data[13] => rp_data[13].DATAIN +rdata_fifo_sink_data[14] => rp_data[14].DATAIN +rdata_fifo_sink_data[15] => rp_data[15].DATAIN +rdata_fifo_sink_data[16] => rp_data[16].DATAIN +rdata_fifo_sink_data[17] => rp_data[17].DATAIN +rdata_fifo_sink_data[18] => rp_data[18].DATAIN +rdata_fifo_sink_data[19] => rp_data[19].DATAIN +rdata_fifo_sink_data[20] => rp_data[20].DATAIN +rdata_fifo_sink_data[21] => rp_data[21].DATAIN +rdata_fifo_sink_data[22] => rp_data[22].DATAIN +rdata_fifo_sink_data[23] => rp_data[23].DATAIN +rdata_fifo_sink_data[24] => rp_data[24].DATAIN +rdata_fifo_sink_data[25] => rp_data[25].DATAIN +rdata_fifo_sink_data[26] => rp_data[26].DATAIN +rdata_fifo_sink_data[27] => rp_data[27].DATAIN +rdata_fifo_sink_data[28] => rp_data[28].DATAIN +rdata_fifo_sink_data[29] => rp_data[29].DATAIN +rdata_fifo_sink_data[30] => rp_data[30].DATAIN +rdata_fifo_sink_data[31] => rp_data[31].DATAIN +rdata_fifo_sink_valid => rp_valid.IN1 +rdata_fifo_sink_valid => rdata_fifo_sink_ready.IN0 +rdata_fifo_sink_valid => comb.IN1 +rdata_fifo_sink_ready <= rdata_fifo_sink_ready.DB_MAX_OUTPUT_PORT_TYPE +cp_ready <= cp_ready.DB_MAX_OUTPUT_PORT_TYPE +cp_valid => local_lock.IN0 +cp_valid => local_write.IN0 +cp_valid => local_read.IN0 +cp_valid => local_compressed_read.IN0 +cp_data[0] => m0_writedata[0].DATAIN +cp_data[1] => m0_writedata[1].DATAIN +cp_data[2] => m0_writedata[2].DATAIN +cp_data[3] => m0_writedata[3].DATAIN +cp_data[4] => m0_writedata[4].DATAIN +cp_data[5] => m0_writedata[5].DATAIN +cp_data[6] => m0_writedata[6].DATAIN +cp_data[7] => m0_writedata[7].DATAIN +cp_data[8] => m0_writedata[8].DATAIN +cp_data[9] => m0_writedata[9].DATAIN +cp_data[10] => m0_writedata[10].DATAIN +cp_data[11] => m0_writedata[11].DATAIN +cp_data[12] => m0_writedata[12].DATAIN +cp_data[13] => m0_writedata[13].DATAIN +cp_data[14] => m0_writedata[14].DATAIN +cp_data[15] => m0_writedata[15].DATAIN +cp_data[16] => m0_writedata[16].DATAIN +cp_data[17] => m0_writedata[17].DATAIN +cp_data[18] => m0_writedata[18].DATAIN +cp_data[19] => m0_writedata[19].DATAIN +cp_data[20] => m0_writedata[20].DATAIN +cp_data[21] => m0_writedata[21].DATAIN +cp_data[22] => m0_writedata[22].DATAIN +cp_data[23] => m0_writedata[23].DATAIN +cp_data[24] => m0_writedata[24].DATAIN +cp_data[25] => m0_writedata[25].DATAIN +cp_data[26] => m0_writedata[26].DATAIN +cp_data[27] => m0_writedata[27].DATAIN +cp_data[28] => m0_writedata[28].DATAIN +cp_data[29] => m0_writedata[29].DATAIN +cp_data[30] => m0_writedata[30].DATAIN +cp_data[31] => m0_writedata[31].DATAIN +cp_data[32] => rf_source_data[32].DATAIN +cp_data[32] => m0_byteenable[0].DATAIN +cp_data[33] => rf_source_data[33].DATAIN +cp_data[33] => m0_byteenable[1].DATAIN +cp_data[34] => rf_source_data[34].DATAIN +cp_data[34] => m0_byteenable[2].DATAIN +cp_data[35] => rf_source_data[35].DATAIN +cp_data[35] => m0_byteenable[3].DATAIN +cp_data[36] => rf_source_data[36].DATAIN +cp_data[37] => rf_source_data[37].DATAIN +cp_data[38] => rf_source_data[38].DATAIN +cp_data[38] => m0_address[2].DATAIN +cp_data[39] => rf_source_data[39].DATAIN +cp_data[39] => m0_address[3].DATAIN +cp_data[40] => rf_source_data[40].DATAIN +cp_data[40] => m0_address[4].DATAIN +cp_data[41] => rf_source_data[41].DATAIN +cp_data[41] => m0_address[5].DATAIN +cp_data[42] => rf_source_data[42].DATAIN +cp_data[42] => m0_address[6].DATAIN +cp_data[43] => rf_source_data[43].DATAIN +cp_data[43] => m0_address[7].DATAIN +cp_data[44] => rf_source_data[44].DATAIN +cp_data[44] => m0_address[8].DATAIN +cp_data[45] => rf_source_data[45].DATAIN +cp_data[45] => m0_address[9].DATAIN +cp_data[46] => rf_source_data[46].DATAIN +cp_data[46] => m0_address[10].DATAIN +cp_data[47] => rf_source_data[47].DATAIN +cp_data[47] => m0_address[11].DATAIN +cp_data[48] => rf_source_data[48].DATAIN +cp_data[48] => m0_address[12].DATAIN +cp_data[49] => rf_source_data[49].DATAIN +cp_data[49] => m0_address[13].DATAIN +cp_data[50] => rf_source_data[50].DATAIN +cp_data[50] => m0_address[14].DATAIN +cp_data[51] => rf_source_data[51].DATAIN +cp_data[51] => m0_address[15].DATAIN +cp_data[52] => rf_source_data[52].DATAIN +cp_data[52] => m0_address[16].DATAIN +cp_data[53] => rf_source_data[53].DATAIN +cp_data[53] => m0_address[17].DATAIN +cp_data[54] => rf_source_data[54].DATAIN +cp_data[54] => m0_address[18].DATAIN +cp_data[55] => rf_source_data[55].DATAIN +cp_data[55] => m0_address[19].DATAIN +cp_data[56] => rf_source_data[56].DATAIN +cp_data[56] => m0_address[20].DATAIN +cp_data[57] => rf_source_data[57].DATAIN +cp_data[57] => m0_address[21].DATAIN +cp_data[58] => rf_source_data[58].DATAIN +cp_data[58] => m0_address[22].DATAIN +cp_data[59] => rf_source_data[59].DATAIN +cp_data[59] => m0_address[23].DATAIN +cp_data[60] => rf_source_data[60].DATAIN +cp_data[60] => m0_address[24].DATAIN +cp_data[61] => rf_source_data[61].DATAIN +cp_data[61] => m0_address[25].DATAIN +cp_data[62] => local_compressed_read.IN1 +cp_data[62] => rf_source_data[62].DATAIN +cp_data[63] => rf_source_data[63].DATAIN +cp_data[63] => comb.IN1 +cp_data[64] => local_write.IN1 +cp_data[64] => rf_source_data[64].DATAIN +cp_data[65] => local_read.IN1 +cp_data[65] => rf_source_data[65].DATAIN +cp_data[66] => local_lock.IN1 +cp_data[66] => rf_source_data[66].DATAIN +cp_data[67] => rf_source_data[67].DATAIN +cp_data[68] => m0_burstcount.DATAA +cp_data[68] => rf_source_data[68].DATAIN +cp_data[69] => m0_burstcount.DATAA +cp_data[69] => rf_source_data[69].DATAIN +cp_data[70] => m0_burstcount.DATAA +cp_data[70] => rf_source_data[70].DATAIN +cp_data[71] => rf_source_data[71].DATAIN +cp_data[72] => rf_source_data[72].DATAIN +cp_data[73] => rf_source_data[73].DATAIN +cp_data[74] => rf_source_data[74].DATAIN +cp_data[75] => rf_source_data[75].DATAIN +cp_data[76] => rf_source_data[76].DATAIN +cp_data[77] => rf_source_data[77].DATAIN +cp_data[78] => rf_source_data[78].DATAIN +cp_data[79] => rf_source_data[79].DATAIN +cp_data[80] => rf_source_data[80].DATAIN +cp_data[81] => rf_source_data[81].DATAIN +cp_data[82] => rf_source_data[82].DATAIN +cp_data[83] => rf_source_data[83].DATAIN +cp_data[84] => rf_source_data[84].DATAIN +cp_data[85] => rf_source_data[85].DATAIN +cp_data[86] => rf_source_data[86].DATAIN +cp_data[87] => rf_source_data[87].DATAIN +cp_data[88] => rf_source_data[88].DATAIN +cp_data[89] => rf_source_data[89].DATAIN +cp_data[90] => rf_source_data[90].DATAIN +cp_data[91] => rf_source_data[91].DATAIN +cp_data[92] => rf_source_data[92].DATAIN +cp_data[92] => m0_debugaccess.DATAIN +cp_data[93] => ~NO_FANOUT~ +cp_data[94] => ~NO_FANOUT~ +cp_data[95] => rf_source_data[95].DATAIN +cp_data[96] => rf_source_data[96].DATAIN +cp_data[97] => rf_source_data[97].DATAIN +cp_data[98] => rf_source_data[98].DATAIN +cp_data[99] => rf_source_data[99].DATAIN +cp_data[100] => rf_source_data[100].DATAIN +cp_channel[0] => ~NO_FANOUT~ +cp_channel[1] => ~NO_FANOUT~ +cp_channel[2] => ~NO_FANOUT~ +cp_channel[3] => ~NO_FANOUT~ +cp_channel[4] => ~NO_FANOUT~ +cp_channel[5] => ~NO_FANOUT~ +cp_channel[6] => ~NO_FANOUT~ +cp_channel[7] => ~NO_FANOUT~ +cp_channel[8] => ~NO_FANOUT~ +cp_channel[9] => ~NO_FANOUT~ +cp_channel[10] => ~NO_FANOUT~ +cp_startofpacket => rf_source_startofpacket.DATAIN +cp_endofpacket => nonposted_write_endofpacket.IN1 +cp_endofpacket => rf_source_endofpacket.DATAIN +rp_ready => rp_ready.IN1 +rp_valid <= rp_valid.DB_MAX_OUTPUT_PORT_TYPE +rp_data[0] <= rdata_fifo_sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +rp_data[1] <= rdata_fifo_sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +rp_data[2] <= rdata_fifo_sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +rp_data[3] <= rdata_fifo_sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +rp_data[4] <= rdata_fifo_sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +rp_data[5] <= rdata_fifo_sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +rp_data[6] <= rdata_fifo_sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +rp_data[7] <= rdata_fifo_sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +rp_data[8] <= rdata_fifo_sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +rp_data[9] <= rdata_fifo_sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +rp_data[10] <= rdata_fifo_sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +rp_data[11] <= rdata_fifo_sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +rp_data[12] <= rdata_fifo_sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +rp_data[13] <= rdata_fifo_sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +rp_data[14] <= rdata_fifo_sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +rp_data[15] <= rdata_fifo_sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +rp_data[16] <= rdata_fifo_sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +rp_data[17] <= rdata_fifo_sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +rp_data[18] <= rdata_fifo_sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +rp_data[19] <= rdata_fifo_sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +rp_data[20] <= rdata_fifo_sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +rp_data[21] <= rdata_fifo_sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +rp_data[22] <= rdata_fifo_sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +rp_data[23] <= rdata_fifo_sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +rp_data[24] <= rdata_fifo_sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +rp_data[25] <= rdata_fifo_sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +rp_data[26] <= rdata_fifo_sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +rp_data[27] <= rdata_fifo_sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +rp_data[28] <= rdata_fifo_sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +rp_data[29] <= rdata_fifo_sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +rp_data[30] <= rdata_fifo_sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +rp_data[31] <= rdata_fifo_sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +rp_data[32] <= rf_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +rp_data[33] <= rf_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +rp_data[34] <= rf_sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +rp_data[35] <= rf_sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +rp_data[36] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[37] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[38] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[39] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[40] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[41] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[42] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[43] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[44] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[45] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[46] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[47] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[48] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[49] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[50] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[51] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[52] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[53] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[54] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[55] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[56] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[57] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[58] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[59] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[60] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[61] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[62] <= altera_merlin_burst_uncompressor:uncompressor.source_is_compressed +rp_data[63] <= rf_sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +rp_data[64] <= rf_sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +rp_data[65] <= rp_data.DB_MAX_OUTPUT_PORT_TYPE +rp_data[66] <= rf_sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +rp_data[67] <= rf_sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +rp_data[68] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt +rp_data[69] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt +rp_data[70] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt +rp_data[71] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap +rp_data[72] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap +rp_data[73] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap +rp_data[74] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize +rp_data[75] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize +rp_data[76] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize +rp_data[77] <= rf_sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +rp_data[78] <= rf_sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +rp_data[79] <= rf_sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +rp_data[80] <= rf_sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +rp_data[81] <= rf_sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +rp_data[82] <= rf_sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +rp_data[83] <= rf_sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +rp_data[84] <= rf_sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +rp_data[85] <= rf_sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +rp_data[86] <= rf_sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +rp_data[87] <= rf_sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +rp_data[88] <= rf_sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +rp_data[89] <= rf_sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +rp_data[90] <= rf_sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +rp_data[91] <= rf_sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +rp_data[92] <= rf_sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +rp_data[93] <= rf_sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +rp_data[94] <= rf_sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +rp_data[95] <= rf_sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +rp_data[96] <= rf_sink_data[96].DB_MAX_OUTPUT_PORT_TYPE +rp_data[97] <= rf_sink_data[97].DB_MAX_OUTPUT_PORT_TYPE +rp_data[98] <= rf_sink_data[98].DB_MAX_OUTPUT_PORT_TYPE +rp_data[99] <= +rp_data[100] <= +rp_startofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_startofpacket +rp_endofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_endofpacket + + +|de0_nano_system|system:inst_cpu|altera_merlin_slave_agent:uart_0_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor +clk => burst_uncompress_address_offset[0].CLK +clk => burst_uncompress_address_offset[1].CLK +clk => burst_uncompress_address_offset[2].CLK +clk => burst_uncompress_address_offset[3].CLK +clk => burst_uncompress_address_offset[4].CLK +clk => burst_uncompress_address_offset[5].CLK +clk => burst_uncompress_address_offset[6].CLK +clk => burst_uncompress_address_offset[7].CLK +clk => burst_uncompress_address_offset[8].CLK +clk => burst_uncompress_address_offset[9].CLK +clk => burst_uncompress_address_offset[10].CLK +clk => burst_uncompress_address_offset[11].CLK +clk => burst_uncompress_address_offset[12].CLK +clk => burst_uncompress_address_offset[13].CLK +clk => burst_uncompress_address_offset[14].CLK +clk => burst_uncompress_address_offset[15].CLK +clk => burst_uncompress_address_offset[16].CLK +clk => burst_uncompress_address_offset[17].CLK +clk => burst_uncompress_address_offset[18].CLK +clk => burst_uncompress_address_offset[19].CLK +clk => burst_uncompress_address_offset[20].CLK +clk => burst_uncompress_address_offset[21].CLK +clk => burst_uncompress_address_offset[22].CLK +clk => burst_uncompress_address_offset[23].CLK +clk => burst_uncompress_address_offset[24].CLK +clk => burst_uncompress_address_offset[25].CLK +clk => burst_uncompress_address_base[0].CLK +clk => burst_uncompress_address_base[1].CLK +clk => burst_uncompress_address_base[2].CLK +clk => burst_uncompress_address_base[3].CLK +clk => burst_uncompress_address_base[4].CLK +clk => burst_uncompress_address_base[5].CLK +clk => burst_uncompress_address_base[6].CLK +clk => burst_uncompress_address_base[7].CLK +clk => burst_uncompress_address_base[8].CLK +clk => burst_uncompress_address_base[9].CLK +clk => burst_uncompress_address_base[10].CLK +clk => burst_uncompress_address_base[11].CLK +clk => burst_uncompress_address_base[12].CLK +clk => burst_uncompress_address_base[13].CLK +clk => burst_uncompress_address_base[14].CLK +clk => burst_uncompress_address_base[15].CLK +clk => burst_uncompress_address_base[16].CLK +clk => burst_uncompress_address_base[17].CLK +clk => burst_uncompress_address_base[18].CLK +clk => burst_uncompress_address_base[19].CLK +clk => burst_uncompress_address_base[20].CLK +clk => burst_uncompress_address_base[21].CLK +clk => burst_uncompress_address_base[22].CLK +clk => burst_uncompress_address_base[23].CLK +clk => burst_uncompress_address_base[24].CLK +clk => burst_uncompress_address_base[25].CLK +clk => burst_uncompress_byte_counter[0].CLK +clk => burst_uncompress_byte_counter[1].CLK +clk => burst_uncompress_byte_counter[2].CLK +clk => burst_uncompress_busy.CLK +reset => burst_uncompress_address_offset[0].ACLR +reset => burst_uncompress_address_offset[1].ACLR +reset => burst_uncompress_address_offset[2].ACLR +reset => burst_uncompress_address_offset[3].ACLR +reset => burst_uncompress_address_offset[4].ACLR +reset => burst_uncompress_address_offset[5].ACLR +reset => burst_uncompress_address_offset[6].ACLR +reset => burst_uncompress_address_offset[7].ACLR +reset => burst_uncompress_address_offset[8].ACLR +reset => burst_uncompress_address_offset[9].ACLR +reset => burst_uncompress_address_offset[10].ACLR +reset => burst_uncompress_address_offset[11].ACLR +reset => burst_uncompress_address_offset[12].ACLR +reset => burst_uncompress_address_offset[13].ACLR +reset => burst_uncompress_address_offset[14].ACLR +reset => burst_uncompress_address_offset[15].ACLR +reset => burst_uncompress_address_offset[16].ACLR +reset => burst_uncompress_address_offset[17].ACLR +reset => burst_uncompress_address_offset[18].ACLR +reset => burst_uncompress_address_offset[19].ACLR +reset => burst_uncompress_address_offset[20].ACLR +reset => burst_uncompress_address_offset[21].ACLR +reset => burst_uncompress_address_offset[22].ACLR +reset => burst_uncompress_address_offset[23].ACLR +reset => burst_uncompress_address_offset[24].ACLR +reset => burst_uncompress_address_offset[25].ACLR +reset => burst_uncompress_address_base[0].ACLR +reset => burst_uncompress_address_base[1].ACLR +reset => burst_uncompress_address_base[2].ACLR +reset => burst_uncompress_address_base[3].ACLR +reset => burst_uncompress_address_base[4].ACLR +reset => burst_uncompress_address_base[5].ACLR +reset => burst_uncompress_address_base[6].ACLR +reset => burst_uncompress_address_base[7].ACLR +reset => burst_uncompress_address_base[8].ACLR +reset => burst_uncompress_address_base[9].ACLR +reset => burst_uncompress_address_base[10].ACLR +reset => burst_uncompress_address_base[11].ACLR +reset => burst_uncompress_address_base[12].ACLR +reset => burst_uncompress_address_base[13].ACLR +reset => burst_uncompress_address_base[14].ACLR +reset => burst_uncompress_address_base[15].ACLR +reset => burst_uncompress_address_base[16].ACLR +reset => burst_uncompress_address_base[17].ACLR +reset => burst_uncompress_address_base[18].ACLR +reset => burst_uncompress_address_base[19].ACLR +reset => burst_uncompress_address_base[20].ACLR +reset => burst_uncompress_address_base[21].ACLR +reset => burst_uncompress_address_base[22].ACLR +reset => burst_uncompress_address_base[23].ACLR +reset => burst_uncompress_address_base[24].ACLR +reset => burst_uncompress_address_base[25].ACLR +reset => burst_uncompress_byte_counter[0].ACLR +reset => burst_uncompress_byte_counter[1].ACLR +reset => burst_uncompress_byte_counter[2].ACLR +reset => burst_uncompress_busy.ACLR +sink_startofpacket => source_startofpacket.IN1 +sink_endofpacket => source_endofpacket.IN1 +sink_valid => first_packet_beat.IN1 +sink_valid => last_packet_beat.IN1 +sink_valid => last_packet_beat.IN1 +sink_valid => always0.IN1 +sink_valid => sink_ready.IN0 +sink_valid => source_valid.DATAIN +sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE +sink_addr[0] => burst_uncompress_address_base.IN0 +sink_addr[0] => comb.DATAB +sink_addr[0] => source_addr.DATAB +sink_addr[1] => burst_uncompress_address_base.IN0 +sink_addr[1] => comb.DATAB +sink_addr[1] => source_addr.DATAB +sink_addr[2] => burst_uncompress_address_base.IN0 +sink_addr[2] => comb.DATAB +sink_addr[2] => source_addr.DATAB +sink_addr[3] => burst_uncompress_address_base.IN0 +sink_addr[3] => comb.DATAB +sink_addr[3] => source_addr.DATAB +sink_addr[4] => burst_uncompress_address_base.IN0 +sink_addr[4] => comb.DATAB +sink_addr[4] => source_addr.DATAB +sink_addr[5] => burst_uncompress_address_base.IN0 +sink_addr[5] => comb.DATAB +sink_addr[5] => source_addr.DATAB +sink_addr[6] => burst_uncompress_address_base.IN0 +sink_addr[6] => comb.DATAB +sink_addr[6] => source_addr.DATAB +sink_addr[7] => burst_uncompress_address_base.IN0 +sink_addr[7] => comb.DATAB +sink_addr[7] => source_addr.DATAB +sink_addr[8] => burst_uncompress_address_base.IN0 +sink_addr[8] => comb.DATAB +sink_addr[8] => source_addr.DATAB +sink_addr[9] => burst_uncompress_address_base.IN0 +sink_addr[9] => comb.DATAB +sink_addr[9] => source_addr.DATAB +sink_addr[10] => burst_uncompress_address_base.IN0 +sink_addr[10] => comb.DATAB +sink_addr[10] => source_addr.DATAB +sink_addr[11] => burst_uncompress_address_base.IN0 +sink_addr[11] => comb.DATAB +sink_addr[11] => source_addr.DATAB +sink_addr[12] => burst_uncompress_address_base.IN0 +sink_addr[12] => comb.DATAB +sink_addr[12] => source_addr.DATAB +sink_addr[13] => burst_uncompress_address_base.IN0 +sink_addr[13] => comb.DATAB +sink_addr[13] => source_addr.DATAB +sink_addr[14] => burst_uncompress_address_base.IN0 +sink_addr[14] => comb.DATAB +sink_addr[14] => source_addr.DATAB +sink_addr[15] => burst_uncompress_address_base.IN0 +sink_addr[15] => comb.DATAB +sink_addr[15] => source_addr.DATAB +sink_addr[16] => burst_uncompress_address_base.IN0 +sink_addr[16] => comb.DATAB +sink_addr[16] => source_addr.DATAB +sink_addr[17] => burst_uncompress_address_base.IN0 +sink_addr[17] => comb.DATAB +sink_addr[17] => source_addr.DATAB +sink_addr[18] => burst_uncompress_address_base.IN0 +sink_addr[18] => comb.DATAB +sink_addr[18] => source_addr.DATAB +sink_addr[19] => burst_uncompress_address_base.IN0 +sink_addr[19] => comb.DATAB +sink_addr[19] => source_addr.DATAB +sink_addr[20] => burst_uncompress_address_base.IN0 +sink_addr[20] => comb.DATAB +sink_addr[20] => source_addr.DATAB +sink_addr[21] => burst_uncompress_address_base.IN0 +sink_addr[21] => comb.DATAB +sink_addr[21] => source_addr.DATAB +sink_addr[22] => burst_uncompress_address_base.IN0 +sink_addr[22] => comb.DATAB +sink_addr[22] => source_addr.DATAB +sink_addr[23] => burst_uncompress_address_base.IN0 +sink_addr[23] => comb.DATAB +sink_addr[23] => source_addr.DATAB +sink_addr[24] => burst_uncompress_address_base.IN0 +sink_addr[24] => comb.DATAB +sink_addr[24] => source_addr.DATAB +sink_addr[25] => burst_uncompress_address_base.IN0 +sink_addr[25] => comb.DATAB +sink_addr[25] => source_addr.DATAB +sink_burstwrap[0] => p1_burst_uncompress_address_offset[0].IN1 +sink_burstwrap[0] => source_burstwrap[0].DATAIN +sink_burstwrap[0] => burst_uncompress_address_base.IN1 +sink_burstwrap[1] => p1_burst_uncompress_address_offset[1].IN1 +sink_burstwrap[1] => source_burstwrap[1].DATAIN +sink_burstwrap[1] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[2].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[25].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[24].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[23].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[22].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[21].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[20].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[19].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[18].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[17].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[16].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[15].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[14].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[13].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[12].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[11].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[10].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[9].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[8].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[7].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[6].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[5].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[4].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[3].IN1 +sink_burstwrap[2] => source_burstwrap[2].DATAIN +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_byte_cnt[0] => source_byte_cnt.DATAB +sink_byte_cnt[0] => Add1.IN6 +sink_byte_cnt[0] => Equal1.IN2 +sink_byte_cnt[1] => source_byte_cnt.DATAB +sink_byte_cnt[1] => Add1.IN5 +sink_byte_cnt[1] => Equal1.IN1 +sink_byte_cnt[2] => source_byte_cnt.DATAB +sink_byte_cnt[2] => Add1.IN4 +sink_byte_cnt[2] => Equal1.IN0 +sink_is_compressed => last_packet_beat.IN1 +sink_burstsize[0] => Decoder0.IN2 +sink_burstsize[0] => source_burstsize[0].DATAIN +sink_burstsize[1] => Decoder0.IN1 +sink_burstsize[1] => source_burstsize[1].DATAIN +sink_burstsize[2] => Decoder0.IN0 +sink_burstsize[2] => source_burstsize[2].DATAIN +source_startofpacket <= source_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +source_endofpacket <= source_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +source_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE +source_ready => always1.IN1 +source_ready => sink_ready.IN1 +source_addr[0] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[1] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[2] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[3] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[4] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[5] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[6] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[7] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[8] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[9] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[10] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[11] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[12] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[13] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[14] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[15] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[16] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[17] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[18] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[19] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[20] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[21] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[22] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[23] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[24] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[25] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_burstwrap[0] <= sink_burstwrap[0].DB_MAX_OUTPUT_PORT_TYPE +source_burstwrap[1] <= sink_burstwrap[1].DB_MAX_OUTPUT_PORT_TYPE +source_burstwrap[2] <= sink_burstwrap[2].DB_MAX_OUTPUT_PORT_TYPE +source_byte_cnt[0] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE +source_byte_cnt[1] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE +source_byte_cnt[2] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE +source_is_compressed <= +source_burstsize[0] <= sink_burstsize[0].DB_MAX_OUTPUT_PORT_TYPE +source_burstsize[1] <= sink_burstsize[1].DB_MAX_OUTPUT_PORT_TYPE +source_burstsize[2] <= sink_burstsize[2].DB_MAX_OUTPUT_PORT_TYPE + + +|de0_nano_system|system:inst_cpu|altera_avalon_sc_fifo:uart_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo +clk => csr_readdata[0]~reg0.CLK +clk => csr_readdata[1]~reg0.CLK +clk => csr_readdata[2]~reg0.CLK +clk => csr_readdata[3]~reg0.CLK +clk => csr_readdata[4]~reg0.CLK +clk => csr_readdata[5]~reg0.CLK +clk => csr_readdata[6]~reg0.CLK +clk => csr_readdata[7]~reg0.CLK +clk => csr_readdata[8]~reg0.CLK +clk => csr_readdata[9]~reg0.CLK +clk => csr_readdata[10]~reg0.CLK +clk => csr_readdata[11]~reg0.CLK +clk => csr_readdata[12]~reg0.CLK +clk => csr_readdata[13]~reg0.CLK +clk => csr_readdata[14]~reg0.CLK +clk => csr_readdata[15]~reg0.CLK +clk => csr_readdata[16]~reg0.CLK +clk => csr_readdata[17]~reg0.CLK +clk => csr_readdata[18]~reg0.CLK +clk => csr_readdata[19]~reg0.CLK +clk => csr_readdata[20]~reg0.CLK +clk => csr_readdata[21]~reg0.CLK +clk => csr_readdata[22]~reg0.CLK +clk => csr_readdata[23]~reg0.CLK +clk => csr_readdata[24]~reg0.CLK +clk => csr_readdata[25]~reg0.CLK +clk => csr_readdata[26]~reg0.CLK +clk => csr_readdata[27]~reg0.CLK +clk => csr_readdata[28]~reg0.CLK +clk => csr_readdata[29]~reg0.CLK +clk => csr_readdata[30]~reg0.CLK +clk => csr_readdata[31]~reg0.CLK +clk => mem_used[1].CLK +clk => mem_used[0].CLK +clk => mem[1][0].CLK +clk => mem[1][1].CLK +clk => mem[1][2].CLK +clk => mem[1][3].CLK +clk => mem[1][4].CLK +clk => mem[1][5].CLK +clk => mem[1][6].CLK +clk => mem[1][7].CLK +clk => mem[1][8].CLK +clk => mem[1][9].CLK +clk => mem[1][10].CLK +clk => mem[1][11].CLK +clk => mem[1][12].CLK +clk => mem[1][13].CLK +clk => mem[1][14].CLK +clk => mem[1][15].CLK +clk => mem[1][16].CLK +clk => mem[1][17].CLK +clk => mem[1][18].CLK +clk => mem[1][19].CLK +clk => mem[1][20].CLK +clk => mem[1][21].CLK +clk => mem[1][22].CLK +clk => mem[1][23].CLK +clk => mem[1][24].CLK +clk => mem[1][25].CLK +clk => mem[1][26].CLK +clk => mem[1][27].CLK +clk => mem[1][28].CLK +clk => mem[1][29].CLK +clk => mem[1][30].CLK +clk => mem[1][31].CLK +clk => mem[1][32].CLK +clk => mem[1][33].CLK +clk => mem[1][34].CLK +clk => mem[1][35].CLK +clk => mem[1][36].CLK +clk => mem[1][37].CLK +clk => mem[1][38].CLK +clk => mem[1][39].CLK +clk => mem[1][40].CLK +clk => mem[1][41].CLK +clk => mem[1][42].CLK +clk => mem[1][43].CLK +clk => mem[1][44].CLK +clk => mem[1][45].CLK +clk => mem[1][46].CLK +clk => mem[1][47].CLK +clk => mem[1][48].CLK +clk => mem[1][49].CLK +clk => mem[1][50].CLK +clk => mem[1][51].CLK +clk => mem[1][52].CLK +clk => mem[1][53].CLK +clk => mem[1][54].CLK +clk => mem[1][55].CLK +clk => mem[1][56].CLK +clk => mem[1][57].CLK +clk => mem[1][58].CLK +clk => mem[1][59].CLK +clk => mem[1][60].CLK +clk => mem[1][61].CLK +clk => mem[1][62].CLK +clk => mem[1][63].CLK +clk => mem[1][64].CLK +clk => mem[1][65].CLK +clk => mem[1][66].CLK +clk => mem[1][67].CLK +clk => mem[1][68].CLK +clk => mem[1][69].CLK +clk => mem[1][70].CLK +clk => mem[1][71].CLK +clk => mem[1][72].CLK +clk => mem[1][73].CLK +clk => mem[1][74].CLK +clk => mem[1][75].CLK +clk => mem[1][76].CLK +clk => mem[1][77].CLK +clk => mem[1][78].CLK +clk => mem[1][79].CLK +clk => mem[1][80].CLK +clk => mem[1][81].CLK +clk => mem[1][82].CLK +clk => mem[1][83].CLK +clk => mem[1][84].CLK +clk => mem[1][85].CLK +clk => mem[1][86].CLK +clk => mem[1][87].CLK +clk => mem[1][88].CLK +clk => mem[1][89].CLK +clk => mem[1][90].CLK +clk => mem[1][91].CLK +clk => mem[1][92].CLK +clk => mem[1][93].CLK +clk => mem[1][94].CLK +clk => mem[1][95].CLK +clk => mem[1][96].CLK +clk => mem[1][97].CLK +clk => mem[1][98].CLK +clk => mem[1][99].CLK +clk => mem[1][100].CLK +clk => mem[1][101].CLK +clk => mem[1][102].CLK +clk => mem[1][103].CLK +clk => mem[0][0].CLK +clk => mem[0][1].CLK +clk => mem[0][2].CLK +clk => mem[0][3].CLK +clk => mem[0][4].CLK +clk => mem[0][5].CLK +clk => mem[0][6].CLK +clk => mem[0][7].CLK +clk => mem[0][8].CLK +clk => mem[0][9].CLK +clk => mem[0][10].CLK +clk => mem[0][11].CLK +clk => mem[0][12].CLK +clk => mem[0][13].CLK +clk => mem[0][14].CLK +clk => mem[0][15].CLK +clk => mem[0][16].CLK +clk => mem[0][17].CLK +clk => mem[0][18].CLK +clk => mem[0][19].CLK +clk => mem[0][20].CLK +clk => mem[0][21].CLK +clk => mem[0][22].CLK +clk => mem[0][23].CLK +clk => mem[0][24].CLK +clk => mem[0][25].CLK +clk => mem[0][26].CLK +clk => mem[0][27].CLK +clk => mem[0][28].CLK +clk => mem[0][29].CLK +clk => mem[0][30].CLK +clk => mem[0][31].CLK +clk => mem[0][32].CLK +clk => mem[0][33].CLK +clk => mem[0][34].CLK +clk => mem[0][35].CLK +clk => mem[0][36].CLK +clk => mem[0][37].CLK +clk => mem[0][38].CLK +clk => mem[0][39].CLK +clk => mem[0][40].CLK +clk => mem[0][41].CLK +clk => mem[0][42].CLK +clk => mem[0][43].CLK +clk => mem[0][44].CLK +clk => mem[0][45].CLK +clk => mem[0][46].CLK +clk => mem[0][47].CLK +clk => mem[0][48].CLK +clk => mem[0][49].CLK +clk => mem[0][50].CLK +clk => mem[0][51].CLK +clk => mem[0][52].CLK +clk => mem[0][53].CLK +clk => mem[0][54].CLK +clk => mem[0][55].CLK +clk => mem[0][56].CLK +clk => mem[0][57].CLK +clk => mem[0][58].CLK +clk => mem[0][59].CLK +clk => mem[0][60].CLK +clk => mem[0][61].CLK +clk => mem[0][62].CLK +clk => mem[0][63].CLK +clk => mem[0][64].CLK +clk => mem[0][65].CLK +clk => mem[0][66].CLK +clk => mem[0][67].CLK +clk => mem[0][68].CLK +clk => mem[0][69].CLK +clk => mem[0][70].CLK +clk => mem[0][71].CLK +clk => mem[0][72].CLK +clk => mem[0][73].CLK +clk => mem[0][74].CLK +clk => mem[0][75].CLK +clk => mem[0][76].CLK +clk => mem[0][77].CLK +clk => mem[0][78].CLK +clk => mem[0][79].CLK +clk => mem[0][80].CLK +clk => mem[0][81].CLK +clk => mem[0][82].CLK +clk => mem[0][83].CLK +clk => mem[0][84].CLK +clk => mem[0][85].CLK +clk => mem[0][86].CLK +clk => mem[0][87].CLK +clk => mem[0][88].CLK +clk => mem[0][89].CLK +clk => mem[0][90].CLK +clk => mem[0][91].CLK +clk => mem[0][92].CLK +clk => mem[0][93].CLK +clk => mem[0][94].CLK +clk => mem[0][95].CLK +clk => mem[0][96].CLK +clk => mem[0][97].CLK +clk => mem[0][98].CLK +clk => mem[0][99].CLK +clk => mem[0][100].CLK +clk => mem[0][101].CLK +clk => mem[0][102].CLK +clk => mem[0][103].CLK +reset => csr_readdata[0]~reg0.ACLR +reset => csr_readdata[1]~reg0.ACLR +reset => csr_readdata[2]~reg0.ACLR +reset => csr_readdata[3]~reg0.ACLR +reset => csr_readdata[4]~reg0.ACLR +reset => csr_readdata[5]~reg0.ACLR +reset => csr_readdata[6]~reg0.ACLR +reset => csr_readdata[7]~reg0.ACLR +reset => csr_readdata[8]~reg0.ACLR +reset => csr_readdata[9]~reg0.ACLR +reset => csr_readdata[10]~reg0.ACLR +reset => csr_readdata[11]~reg0.ACLR +reset => csr_readdata[12]~reg0.ACLR +reset => csr_readdata[13]~reg0.ACLR +reset => csr_readdata[14]~reg0.ACLR +reset => csr_readdata[15]~reg0.ACLR +reset => csr_readdata[16]~reg0.ACLR +reset => csr_readdata[17]~reg0.ACLR +reset => csr_readdata[18]~reg0.ACLR +reset => csr_readdata[19]~reg0.ACLR +reset => csr_readdata[20]~reg0.ACLR +reset => csr_readdata[21]~reg0.ACLR +reset => csr_readdata[22]~reg0.ACLR +reset => csr_readdata[23]~reg0.ACLR +reset => csr_readdata[24]~reg0.ACLR +reset => csr_readdata[25]~reg0.ACLR +reset => csr_readdata[26]~reg0.ACLR +reset => csr_readdata[27]~reg0.ACLR +reset => csr_readdata[28]~reg0.ACLR +reset => csr_readdata[29]~reg0.ACLR +reset => csr_readdata[30]~reg0.ACLR +reset => csr_readdata[31]~reg0.ACLR +reset => mem_used[1].ACLR +reset => mem_used[0].ACLR +reset => mem[1][0].ACLR +reset => mem[1][1].ACLR +reset => mem[1][2].ACLR +reset => mem[1][3].ACLR +reset => mem[1][4].ACLR +reset => mem[1][5].ACLR +reset => mem[1][6].ACLR +reset => mem[1][7].ACLR +reset => mem[1][8].ACLR +reset => mem[1][9].ACLR +reset => mem[1][10].ACLR +reset => mem[1][11].ACLR +reset => mem[1][12].ACLR +reset => mem[1][13].ACLR +reset => mem[1][14].ACLR +reset => mem[1][15].ACLR +reset => mem[1][16].ACLR +reset => mem[1][17].ACLR +reset => mem[1][18].ACLR +reset => mem[1][19].ACLR +reset => mem[1][20].ACLR +reset => mem[1][21].ACLR +reset => mem[1][22].ACLR +reset => mem[1][23].ACLR +reset => mem[1][24].ACLR +reset => mem[1][25].ACLR +reset => mem[1][26].ACLR +reset => mem[1][27].ACLR +reset => mem[1][28].ACLR +reset => mem[1][29].ACLR +reset => mem[1][30].ACLR +reset => mem[1][31].ACLR +reset => mem[1][32].ACLR +reset => mem[1][33].ACLR +reset => mem[1][34].ACLR +reset => mem[1][35].ACLR +reset => mem[1][36].ACLR +reset => mem[1][37].ACLR +reset => mem[1][38].ACLR +reset => mem[1][39].ACLR +reset => mem[1][40].ACLR +reset => mem[1][41].ACLR +reset => mem[1][42].ACLR +reset => mem[1][43].ACLR +reset => mem[1][44].ACLR +reset => mem[1][45].ACLR +reset => mem[1][46].ACLR +reset => mem[1][47].ACLR +reset => mem[1][48].ACLR +reset => mem[1][49].ACLR +reset => mem[1][50].ACLR +reset => mem[1][51].ACLR +reset => mem[1][52].ACLR +reset => mem[1][53].ACLR +reset => mem[1][54].ACLR +reset => mem[1][55].ACLR +reset => mem[1][56].ACLR +reset => mem[1][57].ACLR +reset => mem[1][58].ACLR +reset => mem[1][59].ACLR +reset => mem[1][60].ACLR +reset => mem[1][61].ACLR +reset => mem[1][62].ACLR +reset => mem[1][63].ACLR +reset => mem[1][64].ACLR +reset => mem[1][65].ACLR +reset => mem[1][66].ACLR +reset => mem[1][67].ACLR +reset => mem[1][68].ACLR +reset => mem[1][69].ACLR +reset => mem[1][70].ACLR +reset => mem[1][71].ACLR +reset => mem[1][72].ACLR +reset => mem[1][73].ACLR +reset => mem[1][74].ACLR +reset => mem[1][75].ACLR +reset => mem[1][76].ACLR +reset => mem[1][77].ACLR +reset => mem[1][78].ACLR +reset => mem[1][79].ACLR +reset => mem[1][80].ACLR +reset => mem[1][81].ACLR +reset => mem[1][82].ACLR +reset => mem[1][83].ACLR +reset => mem[1][84].ACLR +reset => mem[1][85].ACLR +reset => mem[1][86].ACLR +reset => mem[1][87].ACLR +reset => mem[1][88].ACLR +reset => mem[1][89].ACLR +reset => mem[1][90].ACLR +reset => mem[1][91].ACLR +reset => mem[1][92].ACLR +reset => mem[1][93].ACLR +reset => mem[1][94].ACLR +reset => mem[1][95].ACLR +reset => mem[1][96].ACLR +reset => mem[1][97].ACLR +reset => mem[1][98].ACLR +reset => mem[1][99].ACLR +reset => mem[1][100].ACLR +reset => mem[1][101].ACLR +reset => mem[1][102].ACLR +reset => mem[1][103].ACLR +reset => mem[0][0].ACLR +reset => mem[0][1].ACLR +reset => mem[0][2].ACLR +reset => mem[0][3].ACLR +reset => mem[0][4].ACLR +reset => mem[0][5].ACLR +reset => mem[0][6].ACLR +reset => mem[0][7].ACLR +reset => mem[0][8].ACLR +reset => mem[0][9].ACLR +reset => mem[0][10].ACLR +reset => mem[0][11].ACLR +reset => mem[0][12].ACLR +reset => mem[0][13].ACLR +reset => mem[0][14].ACLR +reset => mem[0][15].ACLR +reset => mem[0][16].ACLR +reset => mem[0][17].ACLR +reset => mem[0][18].ACLR +reset => mem[0][19].ACLR +reset => mem[0][20].ACLR +reset => mem[0][21].ACLR +reset => mem[0][22].ACLR +reset => mem[0][23].ACLR +reset => mem[0][24].ACLR +reset => mem[0][25].ACLR +reset => mem[0][26].ACLR +reset => mem[0][27].ACLR +reset => mem[0][28].ACLR +reset => mem[0][29].ACLR +reset => mem[0][30].ACLR +reset => mem[0][31].ACLR +reset => mem[0][32].ACLR +reset => mem[0][33].ACLR +reset => mem[0][34].ACLR +reset => mem[0][35].ACLR +reset => mem[0][36].ACLR +reset => mem[0][37].ACLR +reset => mem[0][38].ACLR +reset => mem[0][39].ACLR +reset => mem[0][40].ACLR +reset => mem[0][41].ACLR +reset => mem[0][42].ACLR +reset => mem[0][43].ACLR +reset => mem[0][44].ACLR +reset => mem[0][45].ACLR +reset => mem[0][46].ACLR +reset => mem[0][47].ACLR +reset => mem[0][48].ACLR +reset => mem[0][49].ACLR +reset => mem[0][50].ACLR +reset => mem[0][51].ACLR +reset => mem[0][52].ACLR +reset => mem[0][53].ACLR +reset => mem[0][54].ACLR +reset => mem[0][55].ACLR +reset => mem[0][56].ACLR +reset => mem[0][57].ACLR +reset => mem[0][58].ACLR +reset => mem[0][59].ACLR +reset => mem[0][60].ACLR +reset => mem[0][61].ACLR +reset => mem[0][62].ACLR +reset => mem[0][63].ACLR +reset => mem[0][64].ACLR +reset => mem[0][65].ACLR +reset => mem[0][66].ACLR +reset => mem[0][67].ACLR +reset => mem[0][68].ACLR +reset => mem[0][69].ACLR +reset => mem[0][70].ACLR +reset => mem[0][71].ACLR +reset => mem[0][72].ACLR +reset => mem[0][73].ACLR +reset => mem[0][74].ACLR +reset => mem[0][75].ACLR +reset => mem[0][76].ACLR +reset => mem[0][77].ACLR +reset => mem[0][78].ACLR +reset => mem[0][79].ACLR +reset => mem[0][80].ACLR +reset => mem[0][81].ACLR +reset => mem[0][82].ACLR +reset => mem[0][83].ACLR +reset => mem[0][84].ACLR +reset => mem[0][85].ACLR +reset => mem[0][86].ACLR +reset => mem[0][87].ACLR +reset => mem[0][88].ACLR +reset => mem[0][89].ACLR +reset => mem[0][90].ACLR +reset => mem[0][91].ACLR +reset => mem[0][92].ACLR +reset => mem[0][93].ACLR +reset => mem[0][94].ACLR +reset => mem[0][95].ACLR +reset => mem[0][96].ACLR +reset => mem[0][97].ACLR +reset => mem[0][98].ACLR +reset => mem[0][99].ACLR +reset => mem[0][100].ACLR +reset => mem[0][101].ACLR +reset => mem[0][102].ACLR +reset => mem[0][103].ACLR +in_data[0] => mem.DATAB +in_data[1] => mem.DATAB +in_data[2] => mem.DATAB +in_data[3] => mem.DATAB +in_data[4] => mem.DATAB +in_data[5] => mem.DATAB +in_data[6] => mem.DATAB +in_data[7] => mem.DATAB +in_data[8] => mem.DATAB +in_data[9] => mem.DATAB +in_data[10] => mem.DATAB +in_data[11] => mem.DATAB +in_data[12] => mem.DATAB +in_data[13] => mem.DATAB +in_data[14] => mem.DATAB +in_data[15] => mem.DATAB +in_data[16] => mem.DATAB +in_data[17] => mem.DATAB +in_data[18] => mem.DATAB +in_data[19] => mem.DATAB +in_data[20] => mem.DATAB +in_data[21] => mem.DATAB +in_data[22] => mem.DATAB +in_data[23] => mem.DATAB +in_data[24] => mem.DATAB +in_data[25] => mem.DATAB +in_data[26] => mem.DATAB +in_data[27] => mem.DATAB +in_data[28] => mem.DATAB +in_data[29] => mem.DATAB +in_data[30] => mem.DATAB +in_data[31] => mem.DATAB +in_data[32] => mem.DATAB +in_data[33] => mem.DATAB +in_data[34] => mem.DATAB +in_data[35] => mem.DATAB +in_data[36] => mem.DATAB +in_data[37] => mem.DATAB +in_data[38] => mem.DATAB +in_data[39] => mem.DATAB +in_data[40] => mem.DATAB +in_data[41] => mem.DATAB +in_data[42] => mem.DATAB +in_data[43] => mem.DATAB +in_data[44] => mem.DATAB +in_data[45] => mem.DATAB +in_data[46] => mem.DATAB +in_data[47] => mem.DATAB +in_data[48] => mem.DATAB +in_data[49] => mem.DATAB +in_data[50] => mem.DATAB +in_data[51] => mem.DATAB +in_data[52] => mem.DATAB +in_data[53] => mem.DATAB +in_data[54] => mem.DATAB +in_data[55] => mem.DATAB +in_data[56] => mem.DATAB +in_data[57] => mem.DATAB +in_data[58] => mem.DATAB +in_data[59] => mem.DATAB +in_data[60] => mem.DATAB +in_data[61] => mem.DATAB +in_data[62] => mem.DATAB +in_data[63] => mem.DATAB +in_data[64] => mem.DATAB +in_data[65] => mem.DATAB +in_data[66] => mem.DATAB +in_data[67] => mem.DATAB +in_data[68] => mem.DATAB +in_data[69] => mem.DATAB +in_data[70] => mem.DATAB +in_data[71] => mem.DATAB +in_data[72] => mem.DATAB +in_data[73] => mem.DATAB +in_data[74] => mem.DATAB +in_data[75] => mem.DATAB +in_data[76] => mem.DATAB +in_data[77] => mem.DATAB +in_data[78] => mem.DATAB +in_data[79] => mem.DATAB +in_data[80] => mem.DATAB +in_data[81] => mem.DATAB +in_data[82] => mem.DATAB +in_data[83] => mem.DATAB +in_data[84] => mem.DATAB +in_data[85] => mem.DATAB +in_data[86] => mem.DATAB +in_data[87] => mem.DATAB +in_data[88] => mem.DATAB +in_data[89] => mem.DATAB +in_data[90] => mem.DATAB +in_data[91] => mem.DATAB +in_data[92] => mem.DATAB +in_data[93] => mem.DATAB +in_data[94] => mem.DATAB +in_data[95] => mem.DATAB +in_data[96] => mem.DATAB +in_data[97] => mem.DATAB +in_data[98] => mem.DATAB +in_data[99] => mem.DATAB +in_data[100] => mem.DATAB +in_data[101] => mem.DATAB +in_valid => write.IN1 +in_startofpacket => mem.DATAB +in_endofpacket => mem.DATAB +in_empty[0] => ~NO_FANOUT~ +in_error[0] => out_error[0].DATAIN +in_error[0] => out_empty[0].DATAIN +in_channel[0] => out_channel[0].DATAIN +in_ready <= mem_used[1].DB_MAX_OUTPUT_PORT_TYPE +out_data[0] <= mem[0][0].DB_MAX_OUTPUT_PORT_TYPE +out_data[1] <= mem[0][1].DB_MAX_OUTPUT_PORT_TYPE +out_data[2] <= mem[0][2].DB_MAX_OUTPUT_PORT_TYPE +out_data[3] <= mem[0][3].DB_MAX_OUTPUT_PORT_TYPE +out_data[4] <= mem[0][4].DB_MAX_OUTPUT_PORT_TYPE +out_data[5] <= mem[0][5].DB_MAX_OUTPUT_PORT_TYPE +out_data[6] <= mem[0][6].DB_MAX_OUTPUT_PORT_TYPE +out_data[7] <= mem[0][7].DB_MAX_OUTPUT_PORT_TYPE +out_data[8] <= mem[0][8].DB_MAX_OUTPUT_PORT_TYPE +out_data[9] <= mem[0][9].DB_MAX_OUTPUT_PORT_TYPE +out_data[10] <= mem[0][10].DB_MAX_OUTPUT_PORT_TYPE +out_data[11] <= mem[0][11].DB_MAX_OUTPUT_PORT_TYPE +out_data[12] <= mem[0][12].DB_MAX_OUTPUT_PORT_TYPE +out_data[13] <= mem[0][13].DB_MAX_OUTPUT_PORT_TYPE +out_data[14] <= mem[0][14].DB_MAX_OUTPUT_PORT_TYPE +out_data[15] <= mem[0][15].DB_MAX_OUTPUT_PORT_TYPE +out_data[16] <= mem[0][16].DB_MAX_OUTPUT_PORT_TYPE +out_data[17] <= mem[0][17].DB_MAX_OUTPUT_PORT_TYPE +out_data[18] <= mem[0][18].DB_MAX_OUTPUT_PORT_TYPE +out_data[19] <= mem[0][19].DB_MAX_OUTPUT_PORT_TYPE +out_data[20] <= mem[0][20].DB_MAX_OUTPUT_PORT_TYPE +out_data[21] <= mem[0][21].DB_MAX_OUTPUT_PORT_TYPE +out_data[22] <= mem[0][22].DB_MAX_OUTPUT_PORT_TYPE +out_data[23] <= mem[0][23].DB_MAX_OUTPUT_PORT_TYPE +out_data[24] <= mem[0][24].DB_MAX_OUTPUT_PORT_TYPE +out_data[25] <= mem[0][25].DB_MAX_OUTPUT_PORT_TYPE +out_data[26] <= mem[0][26].DB_MAX_OUTPUT_PORT_TYPE +out_data[27] <= mem[0][27].DB_MAX_OUTPUT_PORT_TYPE +out_data[28] <= mem[0][28].DB_MAX_OUTPUT_PORT_TYPE +out_data[29] <= mem[0][29].DB_MAX_OUTPUT_PORT_TYPE +out_data[30] <= mem[0][30].DB_MAX_OUTPUT_PORT_TYPE +out_data[31] <= mem[0][31].DB_MAX_OUTPUT_PORT_TYPE +out_data[32] <= mem[0][32].DB_MAX_OUTPUT_PORT_TYPE +out_data[33] <= mem[0][33].DB_MAX_OUTPUT_PORT_TYPE +out_data[34] <= mem[0][34].DB_MAX_OUTPUT_PORT_TYPE +out_data[35] <= mem[0][35].DB_MAX_OUTPUT_PORT_TYPE +out_data[36] <= mem[0][36].DB_MAX_OUTPUT_PORT_TYPE +out_data[37] <= mem[0][37].DB_MAX_OUTPUT_PORT_TYPE +out_data[38] <= mem[0][38].DB_MAX_OUTPUT_PORT_TYPE +out_data[39] <= mem[0][39].DB_MAX_OUTPUT_PORT_TYPE +out_data[40] <= mem[0][40].DB_MAX_OUTPUT_PORT_TYPE +out_data[41] <= mem[0][41].DB_MAX_OUTPUT_PORT_TYPE +out_data[42] <= mem[0][42].DB_MAX_OUTPUT_PORT_TYPE +out_data[43] <= mem[0][43].DB_MAX_OUTPUT_PORT_TYPE +out_data[44] <= mem[0][44].DB_MAX_OUTPUT_PORT_TYPE +out_data[45] <= mem[0][45].DB_MAX_OUTPUT_PORT_TYPE +out_data[46] <= mem[0][46].DB_MAX_OUTPUT_PORT_TYPE +out_data[47] <= mem[0][47].DB_MAX_OUTPUT_PORT_TYPE +out_data[48] <= mem[0][48].DB_MAX_OUTPUT_PORT_TYPE +out_data[49] <= mem[0][49].DB_MAX_OUTPUT_PORT_TYPE +out_data[50] <= mem[0][50].DB_MAX_OUTPUT_PORT_TYPE +out_data[51] <= mem[0][51].DB_MAX_OUTPUT_PORT_TYPE +out_data[52] <= mem[0][52].DB_MAX_OUTPUT_PORT_TYPE +out_data[53] <= mem[0][53].DB_MAX_OUTPUT_PORT_TYPE +out_data[54] <= mem[0][54].DB_MAX_OUTPUT_PORT_TYPE +out_data[55] <= mem[0][55].DB_MAX_OUTPUT_PORT_TYPE +out_data[56] <= mem[0][56].DB_MAX_OUTPUT_PORT_TYPE +out_data[57] <= mem[0][57].DB_MAX_OUTPUT_PORT_TYPE +out_data[58] <= mem[0][58].DB_MAX_OUTPUT_PORT_TYPE +out_data[59] <= mem[0][59].DB_MAX_OUTPUT_PORT_TYPE +out_data[60] <= mem[0][60].DB_MAX_OUTPUT_PORT_TYPE +out_data[61] <= mem[0][61].DB_MAX_OUTPUT_PORT_TYPE +out_data[62] <= mem[0][62].DB_MAX_OUTPUT_PORT_TYPE +out_data[63] <= mem[0][63].DB_MAX_OUTPUT_PORT_TYPE +out_data[64] <= mem[0][64].DB_MAX_OUTPUT_PORT_TYPE +out_data[65] <= mem[0][65].DB_MAX_OUTPUT_PORT_TYPE +out_data[66] <= mem[0][66].DB_MAX_OUTPUT_PORT_TYPE +out_data[67] <= mem[0][67].DB_MAX_OUTPUT_PORT_TYPE +out_data[68] <= mem[0][68].DB_MAX_OUTPUT_PORT_TYPE +out_data[69] <= mem[0][69].DB_MAX_OUTPUT_PORT_TYPE +out_data[70] <= mem[0][70].DB_MAX_OUTPUT_PORT_TYPE +out_data[71] <= mem[0][71].DB_MAX_OUTPUT_PORT_TYPE +out_data[72] <= mem[0][72].DB_MAX_OUTPUT_PORT_TYPE +out_data[73] <= mem[0][73].DB_MAX_OUTPUT_PORT_TYPE +out_data[74] <= mem[0][74].DB_MAX_OUTPUT_PORT_TYPE +out_data[75] <= mem[0][75].DB_MAX_OUTPUT_PORT_TYPE +out_data[76] <= mem[0][76].DB_MAX_OUTPUT_PORT_TYPE +out_data[77] <= mem[0][77].DB_MAX_OUTPUT_PORT_TYPE +out_data[78] <= mem[0][78].DB_MAX_OUTPUT_PORT_TYPE +out_data[79] <= mem[0][79].DB_MAX_OUTPUT_PORT_TYPE +out_data[80] <= mem[0][80].DB_MAX_OUTPUT_PORT_TYPE +out_data[81] <= mem[0][81].DB_MAX_OUTPUT_PORT_TYPE +out_data[82] <= mem[0][82].DB_MAX_OUTPUT_PORT_TYPE +out_data[83] <= mem[0][83].DB_MAX_OUTPUT_PORT_TYPE +out_data[84] <= mem[0][84].DB_MAX_OUTPUT_PORT_TYPE +out_data[85] <= mem[0][85].DB_MAX_OUTPUT_PORT_TYPE +out_data[86] <= mem[0][86].DB_MAX_OUTPUT_PORT_TYPE +out_data[87] <= mem[0][87].DB_MAX_OUTPUT_PORT_TYPE +out_data[88] <= mem[0][88].DB_MAX_OUTPUT_PORT_TYPE +out_data[89] <= mem[0][89].DB_MAX_OUTPUT_PORT_TYPE +out_data[90] <= mem[0][90].DB_MAX_OUTPUT_PORT_TYPE +out_data[91] <= mem[0][91].DB_MAX_OUTPUT_PORT_TYPE +out_data[92] <= mem[0][92].DB_MAX_OUTPUT_PORT_TYPE +out_data[93] <= mem[0][93].DB_MAX_OUTPUT_PORT_TYPE +out_data[94] <= mem[0][94].DB_MAX_OUTPUT_PORT_TYPE +out_data[95] <= mem[0][95].DB_MAX_OUTPUT_PORT_TYPE +out_data[96] <= mem[0][96].DB_MAX_OUTPUT_PORT_TYPE +out_data[97] <= mem[0][97].DB_MAX_OUTPUT_PORT_TYPE +out_data[98] <= mem[0][98].DB_MAX_OUTPUT_PORT_TYPE +out_data[99] <= mem[0][99].DB_MAX_OUTPUT_PORT_TYPE +out_data[100] <= mem[0][100].DB_MAX_OUTPUT_PORT_TYPE +out_data[101] <= mem[0][101].DB_MAX_OUTPUT_PORT_TYPE +out_valid <= mem_used[0].DB_MAX_OUTPUT_PORT_TYPE +out_startofpacket <= mem[0][103].DB_MAX_OUTPUT_PORT_TYPE +out_endofpacket <= mem[0][102].DB_MAX_OUTPUT_PORT_TYPE +out_empty[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE +out_error[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE +out_channel[0] <= in_channel[0].DB_MAX_OUTPUT_PORT_TYPE +out_ready => internal_out_ready.IN1 +csr_address[0] => ~NO_FANOUT~ +csr_address[1] => ~NO_FANOUT~ +csr_write => ~NO_FANOUT~ +csr_read => csr_readdata[0]~reg0.ENA +csr_read => csr_readdata[31]~reg0.ENA +csr_read => csr_readdata[30]~reg0.ENA +csr_read => csr_readdata[29]~reg0.ENA +csr_read => csr_readdata[28]~reg0.ENA +csr_read => csr_readdata[27]~reg0.ENA +csr_read => csr_readdata[26]~reg0.ENA +csr_read => csr_readdata[25]~reg0.ENA +csr_read => csr_readdata[24]~reg0.ENA +csr_read => csr_readdata[23]~reg0.ENA +csr_read => csr_readdata[22]~reg0.ENA +csr_read => csr_readdata[21]~reg0.ENA +csr_read => csr_readdata[20]~reg0.ENA +csr_read => csr_readdata[19]~reg0.ENA +csr_read => csr_readdata[18]~reg0.ENA +csr_read => csr_readdata[17]~reg0.ENA +csr_read => csr_readdata[16]~reg0.ENA +csr_read => csr_readdata[15]~reg0.ENA +csr_read => csr_readdata[14]~reg0.ENA +csr_read => csr_readdata[13]~reg0.ENA +csr_read => csr_readdata[12]~reg0.ENA +csr_read => csr_readdata[11]~reg0.ENA +csr_read => csr_readdata[10]~reg0.ENA +csr_read => csr_readdata[9]~reg0.ENA +csr_read => csr_readdata[8]~reg0.ENA +csr_read => csr_readdata[7]~reg0.ENA +csr_read => csr_readdata[6]~reg0.ENA +csr_read => csr_readdata[5]~reg0.ENA +csr_read => csr_readdata[4]~reg0.ENA +csr_read => csr_readdata[3]~reg0.ENA +csr_read => csr_readdata[2]~reg0.ENA +csr_read => csr_readdata[1]~reg0.ENA +csr_writedata[0] => ~NO_FANOUT~ +csr_writedata[1] => ~NO_FANOUT~ +csr_writedata[2] => ~NO_FANOUT~ +csr_writedata[3] => ~NO_FANOUT~ +csr_writedata[4] => ~NO_FANOUT~ +csr_writedata[5] => ~NO_FANOUT~ +csr_writedata[6] => ~NO_FANOUT~ +csr_writedata[7] => ~NO_FANOUT~ +csr_writedata[8] => ~NO_FANOUT~ +csr_writedata[9] => ~NO_FANOUT~ +csr_writedata[10] => ~NO_FANOUT~ +csr_writedata[11] => ~NO_FANOUT~ +csr_writedata[12] => ~NO_FANOUT~ +csr_writedata[13] => ~NO_FANOUT~ +csr_writedata[14] => ~NO_FANOUT~ +csr_writedata[15] => ~NO_FANOUT~ +csr_writedata[16] => ~NO_FANOUT~ +csr_writedata[17] => ~NO_FANOUT~ +csr_writedata[18] => ~NO_FANOUT~ +csr_writedata[19] => ~NO_FANOUT~ +csr_writedata[20] => ~NO_FANOUT~ +csr_writedata[21] => ~NO_FANOUT~ +csr_writedata[22] => ~NO_FANOUT~ +csr_writedata[23] => ~NO_FANOUT~ +csr_writedata[24] => ~NO_FANOUT~ +csr_writedata[25] => ~NO_FANOUT~ +csr_writedata[26] => ~NO_FANOUT~ +csr_writedata[27] => ~NO_FANOUT~ +csr_writedata[28] => ~NO_FANOUT~ +csr_writedata[29] => ~NO_FANOUT~ +csr_writedata[30] => ~NO_FANOUT~ +csr_writedata[31] => ~NO_FANOUT~ +csr_readdata[0] <= csr_readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[1] <= csr_readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[2] <= csr_readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[3] <= csr_readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[4] <= csr_readdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[5] <= csr_readdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[6] <= csr_readdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[7] <= csr_readdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[8] <= csr_readdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[9] <= csr_readdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[10] <= csr_readdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[11] <= csr_readdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[12] <= csr_readdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[13] <= csr_readdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[14] <= csr_readdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[15] <= csr_readdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[16] <= csr_readdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[17] <= csr_readdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[18] <= csr_readdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[19] <= csr_readdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[20] <= csr_readdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[21] <= csr_readdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[22] <= csr_readdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[23] <= csr_readdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[24] <= csr_readdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[25] <= csr_readdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[26] <= csr_readdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[27] <= csr_readdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[28] <= csr_readdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[29] <= csr_readdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[30] <= csr_readdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[31] <= csr_readdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE +almost_full_data <= +almost_empty_data <= + + +|de0_nano_system|system:inst_cpu|altera_merlin_slave_agent:pio_led_s1_translator_avalon_universal_slave_0_agent +clk => clk.IN1 +reset => reset.IN1 +m0_address[0] <= +m0_address[1] <= +m0_address[2] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE +m0_address[3] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE +m0_address[4] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE +m0_address[5] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE +m0_address[6] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE +m0_address[7] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE +m0_address[8] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE +m0_address[9] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE +m0_address[10] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE +m0_address[11] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE +m0_address[12] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE +m0_address[13] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE +m0_address[14] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE +m0_address[15] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE +m0_address[16] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE +m0_address[17] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE +m0_address[18] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE +m0_address[19] <= cp_data[55].DB_MAX_OUTPUT_PORT_TYPE +m0_address[20] <= cp_data[56].DB_MAX_OUTPUT_PORT_TYPE +m0_address[21] <= cp_data[57].DB_MAX_OUTPUT_PORT_TYPE +m0_address[22] <= cp_data[58].DB_MAX_OUTPUT_PORT_TYPE +m0_address[23] <= cp_data[59].DB_MAX_OUTPUT_PORT_TYPE +m0_address[24] <= cp_data[60].DB_MAX_OUTPUT_PORT_TYPE +m0_address[25] <= cp_data[61].DB_MAX_OUTPUT_PORT_TYPE +m0_burstcount[0] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE +m0_burstcount[1] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE +m0_burstcount[2] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[0] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[1] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[2] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[3] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE +m0_read <= m0_read.DB_MAX_OUTPUT_PORT_TYPE +m0_readdata[0] => rdata_fifo_src_data[0].DATAIN +m0_readdata[1] => rdata_fifo_src_data[1].DATAIN +m0_readdata[2] => rdata_fifo_src_data[2].DATAIN +m0_readdata[3] => rdata_fifo_src_data[3].DATAIN +m0_readdata[4] => rdata_fifo_src_data[4].DATAIN +m0_readdata[5] => rdata_fifo_src_data[5].DATAIN +m0_readdata[6] => rdata_fifo_src_data[6].DATAIN +m0_readdata[7] => rdata_fifo_src_data[7].DATAIN +m0_readdata[8] => rdata_fifo_src_data[8].DATAIN +m0_readdata[9] => rdata_fifo_src_data[9].DATAIN +m0_readdata[10] => rdata_fifo_src_data[10].DATAIN +m0_readdata[11] => rdata_fifo_src_data[11].DATAIN +m0_readdata[12] => rdata_fifo_src_data[12].DATAIN +m0_readdata[13] => rdata_fifo_src_data[13].DATAIN +m0_readdata[14] => rdata_fifo_src_data[14].DATAIN +m0_readdata[15] => rdata_fifo_src_data[15].DATAIN +m0_readdata[16] => rdata_fifo_src_data[16].DATAIN +m0_readdata[17] => rdata_fifo_src_data[17].DATAIN +m0_readdata[18] => rdata_fifo_src_data[18].DATAIN +m0_readdata[19] => rdata_fifo_src_data[19].DATAIN +m0_readdata[20] => rdata_fifo_src_data[20].DATAIN +m0_readdata[21] => rdata_fifo_src_data[21].DATAIN +m0_readdata[22] => rdata_fifo_src_data[22].DATAIN +m0_readdata[23] => rdata_fifo_src_data[23].DATAIN +m0_readdata[24] => rdata_fifo_src_data[24].DATAIN +m0_readdata[25] => rdata_fifo_src_data[25].DATAIN +m0_readdata[26] => rdata_fifo_src_data[26].DATAIN +m0_readdata[27] => rdata_fifo_src_data[27].DATAIN +m0_readdata[28] => rdata_fifo_src_data[28].DATAIN +m0_readdata[29] => rdata_fifo_src_data[29].DATAIN +m0_readdata[30] => rdata_fifo_src_data[30].DATAIN +m0_readdata[31] => rdata_fifo_src_data[31].DATAIN +m0_waitrequest => cp_ready.IN0 +m0_write <= m0_write.DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[0] <= cp_data[0].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[1] <= cp_data[1].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[2] <= cp_data[2].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[3] <= cp_data[3].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[4] <= cp_data[4].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[5] <= cp_data[5].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[6] <= cp_data[6].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[7] <= cp_data[7].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[8] <= cp_data[8].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[9] <= cp_data[9].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[10] <= cp_data[10].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[11] <= cp_data[11].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[12] <= cp_data[12].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[13] <= cp_data[13].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[14] <= cp_data[14].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[15] <= cp_data[15].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[16] <= cp_data[16].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[17] <= cp_data[17].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[18] <= cp_data[18].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[19] <= cp_data[19].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[20] <= cp_data[20].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[21] <= cp_data[21].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[22] <= cp_data[22].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[23] <= cp_data[23].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[24] <= cp_data[24].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[25] <= cp_data[25].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[26] <= cp_data[26].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[27] <= cp_data[27].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[28] <= cp_data[28].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[29] <= cp_data[29].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[30] <= cp_data[30].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[31] <= cp_data[31].DB_MAX_OUTPUT_PORT_TYPE +m0_readdatavalid => rdata_fifo_src_valid.DATAIN +m0_debugaccess <= cp_data[92].DB_MAX_OUTPUT_PORT_TYPE +m0_lock <= m0_lock.DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[0] <= +rf_source_data[1] <= +rf_source_data[2] <= +rf_source_data[3] <= +rf_source_data[4] <= +rf_source_data[5] <= +rf_source_data[6] <= +rf_source_data[7] <= +rf_source_data[8] <= +rf_source_data[9] <= +rf_source_data[10] <= +rf_source_data[11] <= +rf_source_data[12] <= +rf_source_data[13] <= +rf_source_data[14] <= +rf_source_data[15] <= +rf_source_data[16] <= +rf_source_data[17] <= +rf_source_data[18] <= +rf_source_data[19] <= +rf_source_data[20] <= +rf_source_data[21] <= +rf_source_data[22] <= +rf_source_data[23] <= +rf_source_data[24] <= +rf_source_data[25] <= +rf_source_data[26] <= +rf_source_data[27] <= +rf_source_data[28] <= +rf_source_data[29] <= +rf_source_data[30] <= +rf_source_data[31] <= +rf_source_data[32] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[33] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[34] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[35] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[36] <= cp_data[36].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[37] <= cp_data[37].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[38] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[39] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[40] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[41] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[42] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[43] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[44] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[45] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[46] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[47] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[48] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[49] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[50] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[51] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[52] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[53] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[54] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[55] <= cp_data[55].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[56] <= cp_data[56].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[57] <= cp_data[57].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[58] <= cp_data[58].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[59] <= cp_data[59].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[60] <= cp_data[60].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[61] <= cp_data[61].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[62] <= cp_data[62].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[63] <= cp_data[63].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[64] <= cp_data[64].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[65] <= cp_data[65].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[66] <= cp_data[66].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[67] <= cp_data[67].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[68] <= cp_data[68].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[69] <= cp_data[69].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[70] <= cp_data[70].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[71] <= cp_data[71].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[72] <= cp_data[72].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[73] <= cp_data[73].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[74] <= cp_data[74].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[75] <= cp_data[75].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[76] <= cp_data[76].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[77] <= cp_data[77].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[78] <= cp_data[78].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[79] <= cp_data[79].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[80] <= cp_data[80].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[81] <= cp_data[81].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[82] <= cp_data[82].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[83] <= cp_data[83].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[84] <= cp_data[84].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[85] <= cp_data[85].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[86] <= cp_data[86].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[87] <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[88] <= cp_data[88].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[89] <= cp_data[89].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[90] <= cp_data[90].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[91] <= cp_data[91].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[92] <= cp_data[92].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[93] <= +rf_source_data[94] <= +rf_source_data[95] <= cp_data[95].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[96] <= cp_data[96].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[97] <= cp_data[97].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[98] <= cp_data[98].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[99] <= cp_data[99].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[100] <= cp_data[100].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[101] <= nonposted_write_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +rf_source_valid <= rf_source_valid.DB_MAX_OUTPUT_PORT_TYPE +rf_source_startofpacket <= cp_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +rf_source_endofpacket <= cp_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +rf_source_ready => cp_ready.IN1 +rf_source_ready => m0_write.IN1 +rf_source_ready => m0_lock.IN1 +rf_source_ready => rf_source_valid.IN1 +rf_source_ready => m0_read.IN1 +rf_sink_data[0] => ~NO_FANOUT~ +rf_sink_data[1] => ~NO_FANOUT~ +rf_sink_data[2] => ~NO_FANOUT~ +rf_sink_data[3] => ~NO_FANOUT~ +rf_sink_data[4] => ~NO_FANOUT~ +rf_sink_data[5] => ~NO_FANOUT~ +rf_sink_data[6] => ~NO_FANOUT~ +rf_sink_data[7] => ~NO_FANOUT~ +rf_sink_data[8] => ~NO_FANOUT~ +rf_sink_data[9] => ~NO_FANOUT~ +rf_sink_data[10] => ~NO_FANOUT~ +rf_sink_data[11] => ~NO_FANOUT~ +rf_sink_data[12] => ~NO_FANOUT~ +rf_sink_data[13] => ~NO_FANOUT~ +rf_sink_data[14] => ~NO_FANOUT~ +rf_sink_data[15] => ~NO_FANOUT~ +rf_sink_data[16] => ~NO_FANOUT~ +rf_sink_data[17] => ~NO_FANOUT~ +rf_sink_data[18] => ~NO_FANOUT~ +rf_sink_data[19] => ~NO_FANOUT~ +rf_sink_data[20] => ~NO_FANOUT~ +rf_sink_data[21] => ~NO_FANOUT~ +rf_sink_data[22] => ~NO_FANOUT~ +rf_sink_data[23] => ~NO_FANOUT~ +rf_sink_data[24] => ~NO_FANOUT~ +rf_sink_data[25] => ~NO_FANOUT~ +rf_sink_data[26] => ~NO_FANOUT~ +rf_sink_data[27] => ~NO_FANOUT~ +rf_sink_data[28] => ~NO_FANOUT~ +rf_sink_data[29] => ~NO_FANOUT~ +rf_sink_data[30] => ~NO_FANOUT~ +rf_sink_data[31] => ~NO_FANOUT~ +rf_sink_data[32] => rp_data[32].DATAIN +rf_sink_data[33] => rp_data[33].DATAIN +rf_sink_data[34] => rp_data[34].DATAIN +rf_sink_data[35] => rp_data[35].DATAIN +rf_sink_data[36] => rf_sink_addr[0].IN1 +rf_sink_data[37] => rf_sink_addr[1].IN1 +rf_sink_data[38] => rf_sink_addr[2].IN1 +rf_sink_data[39] => rf_sink_addr[3].IN1 +rf_sink_data[40] => rf_sink_addr[4].IN1 +rf_sink_data[41] => rf_sink_addr[5].IN1 +rf_sink_data[42] => rf_sink_addr[6].IN1 +rf_sink_data[43] => rf_sink_addr[7].IN1 +rf_sink_data[44] => rf_sink_addr[8].IN1 +rf_sink_data[45] => rf_sink_addr[9].IN1 +rf_sink_data[46] => rf_sink_addr[10].IN1 +rf_sink_data[47] => rf_sink_addr[11].IN1 +rf_sink_data[48] => rf_sink_addr[12].IN1 +rf_sink_data[49] => rf_sink_addr[13].IN1 +rf_sink_data[50] => rf_sink_addr[14].IN1 +rf_sink_data[51] => rf_sink_addr[15].IN1 +rf_sink_data[52] => rf_sink_addr[16].IN1 +rf_sink_data[53] => rf_sink_addr[17].IN1 +rf_sink_data[54] => rf_sink_addr[18].IN1 +rf_sink_data[55] => rf_sink_addr[19].IN1 +rf_sink_data[56] => rf_sink_addr[20].IN1 +rf_sink_data[57] => rf_sink_addr[21].IN1 +rf_sink_data[58] => rf_sink_addr[22].IN1 +rf_sink_data[59] => rf_sink_addr[23].IN1 +rf_sink_data[60] => rf_sink_addr[24].IN1 +rf_sink_data[61] => rf_sink_addr[25].IN1 +rf_sink_data[62] => rf_sink_compressed.IN1 +rf_sink_data[63] => rp_data[63].DATAIN +rf_sink_data[64] => comb.OUTPUTSELECT +rf_sink_data[64] => rp_data[64].DATAIN +rf_sink_data[65] => rp_data.IN0 +rf_sink_data[66] => rp_data[66].DATAIN +rf_sink_data[67] => rp_data[67].DATAIN +rf_sink_data[68] => rf_sink_byte_cnt[0].IN1 +rf_sink_data[69] => rf_sink_byte_cnt[1].IN1 +rf_sink_data[70] => rf_sink_byte_cnt[2].IN1 +rf_sink_data[71] => rf_sink_burstwrap[0].IN1 +rf_sink_data[72] => rf_sink_burstwrap[1].IN1 +rf_sink_data[73] => rf_sink_burstwrap[2].IN1 +rf_sink_data[74] => rf_sink_burstsize[0].IN1 +rf_sink_data[75] => rf_sink_burstsize[1].IN1 +rf_sink_data[76] => rf_sink_burstsize[2].IN1 +rf_sink_data[77] => rp_data[77].DATAIN +rf_sink_data[78] => rp_data[78].DATAIN +rf_sink_data[79] => rp_data[79].DATAIN +rf_sink_data[80] => rp_data[80].DATAIN +rf_sink_data[81] => rp_data[81].DATAIN +rf_sink_data[82] => rp_data[82].DATAIN +rf_sink_data[83] => rp_data[87].DATAIN +rf_sink_data[84] => rp_data[88].DATAIN +rf_sink_data[85] => rp_data[89].DATAIN +rf_sink_data[86] => rp_data[90].DATAIN +rf_sink_data[87] => rp_data[83].DATAIN +rf_sink_data[88] => rp_data[84].DATAIN +rf_sink_data[89] => rp_data[85].DATAIN +rf_sink_data[90] => rp_data[86].DATAIN +rf_sink_data[91] => rp_data[91].DATAIN +rf_sink_data[92] => rp_data[92].DATAIN +rf_sink_data[93] => rp_data[93].DATAIN +rf_sink_data[94] => rp_data[94].DATAIN +rf_sink_data[95] => rp_data[95].DATAIN +rf_sink_data[96] => rp_data[96].DATAIN +rf_sink_data[97] => rp_data[97].DATAIN +rf_sink_data[98] => rp_data[98].DATAIN +rf_sink_data[99] => ~NO_FANOUT~ +rf_sink_data[100] => ~NO_FANOUT~ +rf_sink_data[101] => rdata_fifo_sink_ready.IN0 +rf_sink_data[101] => comb.IN0 +rf_sink_valid => rdata_fifo_sink_ready.IN1 +rf_sink_valid => comb.IN1 +rf_sink_startofpacket => comb.DATAA +rf_sink_endofpacket => rf_sink_endofpacket.IN1 +rf_sink_ready <= altera_merlin_burst_uncompressor:uncompressor.sink_ready +rdata_fifo_src_data[0] <= m0_readdata[0].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[1] <= m0_readdata[1].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[2] <= m0_readdata[2].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[3] <= m0_readdata[3].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[4] <= m0_readdata[4].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[5] <= m0_readdata[5].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[6] <= m0_readdata[6].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[7] <= m0_readdata[7].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[8] <= m0_readdata[8].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[9] <= m0_readdata[9].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[10] <= m0_readdata[10].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[11] <= m0_readdata[11].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[12] <= m0_readdata[12].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[13] <= m0_readdata[13].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[14] <= m0_readdata[14].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[15] <= m0_readdata[15].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[16] <= m0_readdata[16].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[17] <= m0_readdata[17].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[18] <= m0_readdata[18].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[19] <= m0_readdata[19].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[20] <= m0_readdata[20].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[21] <= m0_readdata[21].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[22] <= m0_readdata[22].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[23] <= m0_readdata[23].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[24] <= m0_readdata[24].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[25] <= m0_readdata[25].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[26] <= m0_readdata[26].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[27] <= m0_readdata[27].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[28] <= m0_readdata[28].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[29] <= m0_readdata[29].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[30] <= m0_readdata[30].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[31] <= m0_readdata[31].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_valid <= m0_readdatavalid.DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_ready => ~NO_FANOUT~ +rdata_fifo_sink_data[0] => rp_data[0].DATAIN +rdata_fifo_sink_data[1] => rp_data[1].DATAIN +rdata_fifo_sink_data[2] => rp_data[2].DATAIN +rdata_fifo_sink_data[3] => rp_data[3].DATAIN +rdata_fifo_sink_data[4] => rp_data[4].DATAIN +rdata_fifo_sink_data[5] => rp_data[5].DATAIN +rdata_fifo_sink_data[6] => rp_data[6].DATAIN +rdata_fifo_sink_data[7] => rp_data[7].DATAIN +rdata_fifo_sink_data[8] => rp_data[8].DATAIN +rdata_fifo_sink_data[9] => rp_data[9].DATAIN +rdata_fifo_sink_data[10] => rp_data[10].DATAIN +rdata_fifo_sink_data[11] => rp_data[11].DATAIN +rdata_fifo_sink_data[12] => rp_data[12].DATAIN +rdata_fifo_sink_data[13] => rp_data[13].DATAIN +rdata_fifo_sink_data[14] => rp_data[14].DATAIN +rdata_fifo_sink_data[15] => rp_data[15].DATAIN +rdata_fifo_sink_data[16] => rp_data[16].DATAIN +rdata_fifo_sink_data[17] => rp_data[17].DATAIN +rdata_fifo_sink_data[18] => rp_data[18].DATAIN +rdata_fifo_sink_data[19] => rp_data[19].DATAIN +rdata_fifo_sink_data[20] => rp_data[20].DATAIN +rdata_fifo_sink_data[21] => rp_data[21].DATAIN +rdata_fifo_sink_data[22] => rp_data[22].DATAIN +rdata_fifo_sink_data[23] => rp_data[23].DATAIN +rdata_fifo_sink_data[24] => rp_data[24].DATAIN +rdata_fifo_sink_data[25] => rp_data[25].DATAIN +rdata_fifo_sink_data[26] => rp_data[26].DATAIN +rdata_fifo_sink_data[27] => rp_data[27].DATAIN +rdata_fifo_sink_data[28] => rp_data[28].DATAIN +rdata_fifo_sink_data[29] => rp_data[29].DATAIN +rdata_fifo_sink_data[30] => rp_data[30].DATAIN +rdata_fifo_sink_data[31] => rp_data[31].DATAIN +rdata_fifo_sink_valid => rp_valid.IN1 +rdata_fifo_sink_valid => rdata_fifo_sink_ready.IN0 +rdata_fifo_sink_valid => comb.IN1 +rdata_fifo_sink_ready <= rdata_fifo_sink_ready.DB_MAX_OUTPUT_PORT_TYPE +cp_ready <= cp_ready.DB_MAX_OUTPUT_PORT_TYPE +cp_valid => local_lock.IN0 +cp_valid => local_write.IN0 +cp_valid => local_read.IN0 +cp_valid => local_compressed_read.IN0 +cp_data[0] => m0_writedata[0].DATAIN +cp_data[1] => m0_writedata[1].DATAIN +cp_data[2] => m0_writedata[2].DATAIN +cp_data[3] => m0_writedata[3].DATAIN +cp_data[4] => m0_writedata[4].DATAIN +cp_data[5] => m0_writedata[5].DATAIN +cp_data[6] => m0_writedata[6].DATAIN +cp_data[7] => m0_writedata[7].DATAIN +cp_data[8] => m0_writedata[8].DATAIN +cp_data[9] => m0_writedata[9].DATAIN +cp_data[10] => m0_writedata[10].DATAIN +cp_data[11] => m0_writedata[11].DATAIN +cp_data[12] => m0_writedata[12].DATAIN +cp_data[13] => m0_writedata[13].DATAIN +cp_data[14] => m0_writedata[14].DATAIN +cp_data[15] => m0_writedata[15].DATAIN +cp_data[16] => m0_writedata[16].DATAIN +cp_data[17] => m0_writedata[17].DATAIN +cp_data[18] => m0_writedata[18].DATAIN +cp_data[19] => m0_writedata[19].DATAIN +cp_data[20] => m0_writedata[20].DATAIN +cp_data[21] => m0_writedata[21].DATAIN +cp_data[22] => m0_writedata[22].DATAIN +cp_data[23] => m0_writedata[23].DATAIN +cp_data[24] => m0_writedata[24].DATAIN +cp_data[25] => m0_writedata[25].DATAIN +cp_data[26] => m0_writedata[26].DATAIN +cp_data[27] => m0_writedata[27].DATAIN +cp_data[28] => m0_writedata[28].DATAIN +cp_data[29] => m0_writedata[29].DATAIN +cp_data[30] => m0_writedata[30].DATAIN +cp_data[31] => m0_writedata[31].DATAIN +cp_data[32] => rf_source_data[32].DATAIN +cp_data[32] => m0_byteenable[0].DATAIN +cp_data[33] => rf_source_data[33].DATAIN +cp_data[33] => m0_byteenable[1].DATAIN +cp_data[34] => rf_source_data[34].DATAIN +cp_data[34] => m0_byteenable[2].DATAIN +cp_data[35] => rf_source_data[35].DATAIN +cp_data[35] => m0_byteenable[3].DATAIN +cp_data[36] => rf_source_data[36].DATAIN +cp_data[37] => rf_source_data[37].DATAIN +cp_data[38] => rf_source_data[38].DATAIN +cp_data[38] => m0_address[2].DATAIN +cp_data[39] => rf_source_data[39].DATAIN +cp_data[39] => m0_address[3].DATAIN +cp_data[40] => rf_source_data[40].DATAIN +cp_data[40] => m0_address[4].DATAIN +cp_data[41] => rf_source_data[41].DATAIN +cp_data[41] => m0_address[5].DATAIN +cp_data[42] => rf_source_data[42].DATAIN +cp_data[42] => m0_address[6].DATAIN +cp_data[43] => rf_source_data[43].DATAIN +cp_data[43] => m0_address[7].DATAIN +cp_data[44] => rf_source_data[44].DATAIN +cp_data[44] => m0_address[8].DATAIN +cp_data[45] => rf_source_data[45].DATAIN +cp_data[45] => m0_address[9].DATAIN +cp_data[46] => rf_source_data[46].DATAIN +cp_data[46] => m0_address[10].DATAIN +cp_data[47] => rf_source_data[47].DATAIN +cp_data[47] => m0_address[11].DATAIN +cp_data[48] => rf_source_data[48].DATAIN +cp_data[48] => m0_address[12].DATAIN +cp_data[49] => rf_source_data[49].DATAIN +cp_data[49] => m0_address[13].DATAIN +cp_data[50] => rf_source_data[50].DATAIN +cp_data[50] => m0_address[14].DATAIN +cp_data[51] => rf_source_data[51].DATAIN +cp_data[51] => m0_address[15].DATAIN +cp_data[52] => rf_source_data[52].DATAIN +cp_data[52] => m0_address[16].DATAIN +cp_data[53] => rf_source_data[53].DATAIN +cp_data[53] => m0_address[17].DATAIN +cp_data[54] => rf_source_data[54].DATAIN +cp_data[54] => m0_address[18].DATAIN +cp_data[55] => rf_source_data[55].DATAIN +cp_data[55] => m0_address[19].DATAIN +cp_data[56] => rf_source_data[56].DATAIN +cp_data[56] => m0_address[20].DATAIN +cp_data[57] => rf_source_data[57].DATAIN +cp_data[57] => m0_address[21].DATAIN +cp_data[58] => rf_source_data[58].DATAIN +cp_data[58] => m0_address[22].DATAIN +cp_data[59] => rf_source_data[59].DATAIN +cp_data[59] => m0_address[23].DATAIN +cp_data[60] => rf_source_data[60].DATAIN +cp_data[60] => m0_address[24].DATAIN +cp_data[61] => rf_source_data[61].DATAIN +cp_data[61] => m0_address[25].DATAIN +cp_data[62] => local_compressed_read.IN1 +cp_data[62] => rf_source_data[62].DATAIN +cp_data[63] => rf_source_data[63].DATAIN +cp_data[63] => comb.IN1 +cp_data[64] => local_write.IN1 +cp_data[64] => rf_source_data[64].DATAIN +cp_data[65] => local_read.IN1 +cp_data[65] => rf_source_data[65].DATAIN +cp_data[66] => local_lock.IN1 +cp_data[66] => rf_source_data[66].DATAIN +cp_data[67] => rf_source_data[67].DATAIN +cp_data[68] => m0_burstcount.DATAA +cp_data[68] => rf_source_data[68].DATAIN +cp_data[69] => m0_burstcount.DATAA +cp_data[69] => rf_source_data[69].DATAIN +cp_data[70] => m0_burstcount.DATAA +cp_data[70] => rf_source_data[70].DATAIN +cp_data[71] => rf_source_data[71].DATAIN +cp_data[72] => rf_source_data[72].DATAIN +cp_data[73] => rf_source_data[73].DATAIN +cp_data[74] => rf_source_data[74].DATAIN +cp_data[75] => rf_source_data[75].DATAIN +cp_data[76] => rf_source_data[76].DATAIN +cp_data[77] => rf_source_data[77].DATAIN +cp_data[78] => rf_source_data[78].DATAIN +cp_data[79] => rf_source_data[79].DATAIN +cp_data[80] => rf_source_data[80].DATAIN +cp_data[81] => rf_source_data[81].DATAIN +cp_data[82] => rf_source_data[82].DATAIN +cp_data[83] => rf_source_data[83].DATAIN +cp_data[84] => rf_source_data[84].DATAIN +cp_data[85] => rf_source_data[85].DATAIN +cp_data[86] => rf_source_data[86].DATAIN +cp_data[87] => rf_source_data[87].DATAIN +cp_data[88] => rf_source_data[88].DATAIN +cp_data[89] => rf_source_data[89].DATAIN +cp_data[90] => rf_source_data[90].DATAIN +cp_data[91] => rf_source_data[91].DATAIN +cp_data[92] => rf_source_data[92].DATAIN +cp_data[92] => m0_debugaccess.DATAIN +cp_data[93] => ~NO_FANOUT~ +cp_data[94] => ~NO_FANOUT~ +cp_data[95] => rf_source_data[95].DATAIN +cp_data[96] => rf_source_data[96].DATAIN +cp_data[97] => rf_source_data[97].DATAIN +cp_data[98] => rf_source_data[98].DATAIN +cp_data[99] => rf_source_data[99].DATAIN +cp_data[100] => rf_source_data[100].DATAIN +cp_channel[0] => ~NO_FANOUT~ +cp_channel[1] => ~NO_FANOUT~ +cp_channel[2] => ~NO_FANOUT~ +cp_channel[3] => ~NO_FANOUT~ +cp_channel[4] => ~NO_FANOUT~ +cp_channel[5] => ~NO_FANOUT~ +cp_channel[6] => ~NO_FANOUT~ +cp_channel[7] => ~NO_FANOUT~ +cp_channel[8] => ~NO_FANOUT~ +cp_channel[9] => ~NO_FANOUT~ +cp_channel[10] => ~NO_FANOUT~ +cp_startofpacket => rf_source_startofpacket.DATAIN +cp_endofpacket => nonposted_write_endofpacket.IN1 +cp_endofpacket => rf_source_endofpacket.DATAIN +rp_ready => rp_ready.IN1 +rp_valid <= rp_valid.DB_MAX_OUTPUT_PORT_TYPE +rp_data[0] <= rdata_fifo_sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +rp_data[1] <= rdata_fifo_sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +rp_data[2] <= rdata_fifo_sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +rp_data[3] <= rdata_fifo_sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +rp_data[4] <= rdata_fifo_sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +rp_data[5] <= rdata_fifo_sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +rp_data[6] <= rdata_fifo_sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +rp_data[7] <= rdata_fifo_sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +rp_data[8] <= rdata_fifo_sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +rp_data[9] <= rdata_fifo_sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +rp_data[10] <= rdata_fifo_sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +rp_data[11] <= rdata_fifo_sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +rp_data[12] <= rdata_fifo_sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +rp_data[13] <= rdata_fifo_sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +rp_data[14] <= rdata_fifo_sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +rp_data[15] <= rdata_fifo_sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +rp_data[16] <= rdata_fifo_sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +rp_data[17] <= rdata_fifo_sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +rp_data[18] <= rdata_fifo_sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +rp_data[19] <= rdata_fifo_sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +rp_data[20] <= rdata_fifo_sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +rp_data[21] <= rdata_fifo_sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +rp_data[22] <= rdata_fifo_sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +rp_data[23] <= rdata_fifo_sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +rp_data[24] <= rdata_fifo_sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +rp_data[25] <= rdata_fifo_sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +rp_data[26] <= rdata_fifo_sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +rp_data[27] <= rdata_fifo_sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +rp_data[28] <= rdata_fifo_sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +rp_data[29] <= rdata_fifo_sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +rp_data[30] <= rdata_fifo_sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +rp_data[31] <= rdata_fifo_sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +rp_data[32] <= rf_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +rp_data[33] <= rf_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +rp_data[34] <= rf_sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +rp_data[35] <= rf_sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +rp_data[36] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[37] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[38] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[39] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[40] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[41] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[42] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[43] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[44] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[45] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[46] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[47] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[48] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[49] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[50] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[51] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[52] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[53] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[54] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[55] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[56] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[57] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[58] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[59] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[60] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[61] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[62] <= altera_merlin_burst_uncompressor:uncompressor.source_is_compressed +rp_data[63] <= rf_sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +rp_data[64] <= rf_sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +rp_data[65] <= rp_data.DB_MAX_OUTPUT_PORT_TYPE +rp_data[66] <= rf_sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +rp_data[67] <= rf_sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +rp_data[68] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt +rp_data[69] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt +rp_data[70] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt +rp_data[71] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap +rp_data[72] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap +rp_data[73] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap +rp_data[74] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize +rp_data[75] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize +rp_data[76] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize +rp_data[77] <= rf_sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +rp_data[78] <= rf_sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +rp_data[79] <= rf_sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +rp_data[80] <= rf_sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +rp_data[81] <= rf_sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +rp_data[82] <= rf_sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +rp_data[83] <= rf_sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +rp_data[84] <= rf_sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +rp_data[85] <= rf_sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +rp_data[86] <= rf_sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +rp_data[87] <= rf_sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +rp_data[88] <= rf_sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +rp_data[89] <= rf_sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +rp_data[90] <= rf_sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +rp_data[91] <= rf_sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +rp_data[92] <= rf_sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +rp_data[93] <= rf_sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +rp_data[94] <= rf_sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +rp_data[95] <= rf_sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +rp_data[96] <= rf_sink_data[96].DB_MAX_OUTPUT_PORT_TYPE +rp_data[97] <= rf_sink_data[97].DB_MAX_OUTPUT_PORT_TYPE +rp_data[98] <= rf_sink_data[98].DB_MAX_OUTPUT_PORT_TYPE +rp_data[99] <= +rp_data[100] <= +rp_startofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_startofpacket +rp_endofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_endofpacket + + +|de0_nano_system|system:inst_cpu|altera_merlin_slave_agent:pio_led_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor +clk => burst_uncompress_address_offset[0].CLK +clk => burst_uncompress_address_offset[1].CLK +clk => burst_uncompress_address_offset[2].CLK +clk => burst_uncompress_address_offset[3].CLK +clk => burst_uncompress_address_offset[4].CLK +clk => burst_uncompress_address_offset[5].CLK +clk => burst_uncompress_address_offset[6].CLK +clk => burst_uncompress_address_offset[7].CLK +clk => burst_uncompress_address_offset[8].CLK +clk => burst_uncompress_address_offset[9].CLK +clk => burst_uncompress_address_offset[10].CLK +clk => burst_uncompress_address_offset[11].CLK +clk => burst_uncompress_address_offset[12].CLK +clk => burst_uncompress_address_offset[13].CLK +clk => burst_uncompress_address_offset[14].CLK +clk => burst_uncompress_address_offset[15].CLK +clk => burst_uncompress_address_offset[16].CLK +clk => burst_uncompress_address_offset[17].CLK +clk => burst_uncompress_address_offset[18].CLK +clk => burst_uncompress_address_offset[19].CLK +clk => burst_uncompress_address_offset[20].CLK +clk => burst_uncompress_address_offset[21].CLK +clk => burst_uncompress_address_offset[22].CLK +clk => burst_uncompress_address_offset[23].CLK +clk => burst_uncompress_address_offset[24].CLK +clk => burst_uncompress_address_offset[25].CLK +clk => burst_uncompress_address_base[0].CLK +clk => burst_uncompress_address_base[1].CLK +clk => burst_uncompress_address_base[2].CLK +clk => burst_uncompress_address_base[3].CLK +clk => burst_uncompress_address_base[4].CLK +clk => burst_uncompress_address_base[5].CLK +clk => burst_uncompress_address_base[6].CLK +clk => burst_uncompress_address_base[7].CLK +clk => burst_uncompress_address_base[8].CLK +clk => burst_uncompress_address_base[9].CLK +clk => burst_uncompress_address_base[10].CLK +clk => burst_uncompress_address_base[11].CLK +clk => burst_uncompress_address_base[12].CLK +clk => burst_uncompress_address_base[13].CLK +clk => burst_uncompress_address_base[14].CLK +clk => burst_uncompress_address_base[15].CLK +clk => burst_uncompress_address_base[16].CLK +clk => burst_uncompress_address_base[17].CLK +clk => burst_uncompress_address_base[18].CLK +clk => burst_uncompress_address_base[19].CLK +clk => burst_uncompress_address_base[20].CLK +clk => burst_uncompress_address_base[21].CLK +clk => burst_uncompress_address_base[22].CLK +clk => burst_uncompress_address_base[23].CLK +clk => burst_uncompress_address_base[24].CLK +clk => burst_uncompress_address_base[25].CLK +clk => burst_uncompress_byte_counter[0].CLK +clk => burst_uncompress_byte_counter[1].CLK +clk => burst_uncompress_byte_counter[2].CLK +clk => burst_uncompress_busy.CLK +reset => burst_uncompress_address_offset[0].ACLR +reset => burst_uncompress_address_offset[1].ACLR +reset => burst_uncompress_address_offset[2].ACLR +reset => burst_uncompress_address_offset[3].ACLR +reset => burst_uncompress_address_offset[4].ACLR +reset => burst_uncompress_address_offset[5].ACLR +reset => burst_uncompress_address_offset[6].ACLR +reset => burst_uncompress_address_offset[7].ACLR +reset => burst_uncompress_address_offset[8].ACLR +reset => burst_uncompress_address_offset[9].ACLR +reset => burst_uncompress_address_offset[10].ACLR +reset => burst_uncompress_address_offset[11].ACLR +reset => burst_uncompress_address_offset[12].ACLR +reset => burst_uncompress_address_offset[13].ACLR +reset => burst_uncompress_address_offset[14].ACLR +reset => burst_uncompress_address_offset[15].ACLR +reset => burst_uncompress_address_offset[16].ACLR +reset => burst_uncompress_address_offset[17].ACLR +reset => burst_uncompress_address_offset[18].ACLR +reset => burst_uncompress_address_offset[19].ACLR +reset => burst_uncompress_address_offset[20].ACLR +reset => burst_uncompress_address_offset[21].ACLR +reset => burst_uncompress_address_offset[22].ACLR +reset => burst_uncompress_address_offset[23].ACLR +reset => burst_uncompress_address_offset[24].ACLR +reset => burst_uncompress_address_offset[25].ACLR +reset => burst_uncompress_address_base[0].ACLR +reset => burst_uncompress_address_base[1].ACLR +reset => burst_uncompress_address_base[2].ACLR +reset => burst_uncompress_address_base[3].ACLR +reset => burst_uncompress_address_base[4].ACLR +reset => burst_uncompress_address_base[5].ACLR +reset => burst_uncompress_address_base[6].ACLR +reset => burst_uncompress_address_base[7].ACLR +reset => burst_uncompress_address_base[8].ACLR +reset => burst_uncompress_address_base[9].ACLR +reset => burst_uncompress_address_base[10].ACLR +reset => burst_uncompress_address_base[11].ACLR +reset => burst_uncompress_address_base[12].ACLR +reset => burst_uncompress_address_base[13].ACLR +reset => burst_uncompress_address_base[14].ACLR +reset => burst_uncompress_address_base[15].ACLR +reset => burst_uncompress_address_base[16].ACLR +reset => burst_uncompress_address_base[17].ACLR +reset => burst_uncompress_address_base[18].ACLR +reset => burst_uncompress_address_base[19].ACLR +reset => burst_uncompress_address_base[20].ACLR +reset => burst_uncompress_address_base[21].ACLR +reset => burst_uncompress_address_base[22].ACLR +reset => burst_uncompress_address_base[23].ACLR +reset => burst_uncompress_address_base[24].ACLR +reset => burst_uncompress_address_base[25].ACLR +reset => burst_uncompress_byte_counter[0].ACLR +reset => burst_uncompress_byte_counter[1].ACLR +reset => burst_uncompress_byte_counter[2].ACLR +reset => burst_uncompress_busy.ACLR +sink_startofpacket => source_startofpacket.IN1 +sink_endofpacket => source_endofpacket.IN1 +sink_valid => first_packet_beat.IN1 +sink_valid => last_packet_beat.IN1 +sink_valid => last_packet_beat.IN1 +sink_valid => always0.IN1 +sink_valid => sink_ready.IN0 +sink_valid => source_valid.DATAIN +sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE +sink_addr[0] => burst_uncompress_address_base.IN0 +sink_addr[0] => comb.DATAB +sink_addr[0] => source_addr.DATAB +sink_addr[1] => burst_uncompress_address_base.IN0 +sink_addr[1] => comb.DATAB +sink_addr[1] => source_addr.DATAB +sink_addr[2] => burst_uncompress_address_base.IN0 +sink_addr[2] => comb.DATAB +sink_addr[2] => source_addr.DATAB +sink_addr[3] => burst_uncompress_address_base.IN0 +sink_addr[3] => comb.DATAB +sink_addr[3] => source_addr.DATAB +sink_addr[4] => burst_uncompress_address_base.IN0 +sink_addr[4] => comb.DATAB +sink_addr[4] => source_addr.DATAB +sink_addr[5] => burst_uncompress_address_base.IN0 +sink_addr[5] => comb.DATAB +sink_addr[5] => source_addr.DATAB +sink_addr[6] => burst_uncompress_address_base.IN0 +sink_addr[6] => comb.DATAB +sink_addr[6] => source_addr.DATAB +sink_addr[7] => burst_uncompress_address_base.IN0 +sink_addr[7] => comb.DATAB +sink_addr[7] => source_addr.DATAB +sink_addr[8] => burst_uncompress_address_base.IN0 +sink_addr[8] => comb.DATAB +sink_addr[8] => source_addr.DATAB +sink_addr[9] => burst_uncompress_address_base.IN0 +sink_addr[9] => comb.DATAB +sink_addr[9] => source_addr.DATAB +sink_addr[10] => burst_uncompress_address_base.IN0 +sink_addr[10] => comb.DATAB +sink_addr[10] => source_addr.DATAB +sink_addr[11] => burst_uncompress_address_base.IN0 +sink_addr[11] => comb.DATAB +sink_addr[11] => source_addr.DATAB +sink_addr[12] => burst_uncompress_address_base.IN0 +sink_addr[12] => comb.DATAB +sink_addr[12] => source_addr.DATAB +sink_addr[13] => burst_uncompress_address_base.IN0 +sink_addr[13] => comb.DATAB +sink_addr[13] => source_addr.DATAB +sink_addr[14] => burst_uncompress_address_base.IN0 +sink_addr[14] => comb.DATAB +sink_addr[14] => source_addr.DATAB +sink_addr[15] => burst_uncompress_address_base.IN0 +sink_addr[15] => comb.DATAB +sink_addr[15] => source_addr.DATAB +sink_addr[16] => burst_uncompress_address_base.IN0 +sink_addr[16] => comb.DATAB +sink_addr[16] => source_addr.DATAB +sink_addr[17] => burst_uncompress_address_base.IN0 +sink_addr[17] => comb.DATAB +sink_addr[17] => source_addr.DATAB +sink_addr[18] => burst_uncompress_address_base.IN0 +sink_addr[18] => comb.DATAB +sink_addr[18] => source_addr.DATAB +sink_addr[19] => burst_uncompress_address_base.IN0 +sink_addr[19] => comb.DATAB +sink_addr[19] => source_addr.DATAB +sink_addr[20] => burst_uncompress_address_base.IN0 +sink_addr[20] => comb.DATAB +sink_addr[20] => source_addr.DATAB +sink_addr[21] => burst_uncompress_address_base.IN0 +sink_addr[21] => comb.DATAB +sink_addr[21] => source_addr.DATAB +sink_addr[22] => burst_uncompress_address_base.IN0 +sink_addr[22] => comb.DATAB +sink_addr[22] => source_addr.DATAB +sink_addr[23] => burst_uncompress_address_base.IN0 +sink_addr[23] => comb.DATAB +sink_addr[23] => source_addr.DATAB +sink_addr[24] => burst_uncompress_address_base.IN0 +sink_addr[24] => comb.DATAB +sink_addr[24] => source_addr.DATAB +sink_addr[25] => burst_uncompress_address_base.IN0 +sink_addr[25] => comb.DATAB +sink_addr[25] => source_addr.DATAB +sink_burstwrap[0] => p1_burst_uncompress_address_offset[0].IN1 +sink_burstwrap[0] => source_burstwrap[0].DATAIN +sink_burstwrap[0] => burst_uncompress_address_base.IN1 +sink_burstwrap[1] => p1_burst_uncompress_address_offset[1].IN1 +sink_burstwrap[1] => source_burstwrap[1].DATAIN +sink_burstwrap[1] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[2].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[25].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[24].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[23].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[22].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[21].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[20].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[19].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[18].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[17].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[16].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[15].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[14].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[13].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[12].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[11].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[10].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[9].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[8].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[7].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[6].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[5].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[4].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[3].IN1 +sink_burstwrap[2] => source_burstwrap[2].DATAIN +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_byte_cnt[0] => source_byte_cnt.DATAB +sink_byte_cnt[0] => Add1.IN6 +sink_byte_cnt[0] => Equal1.IN2 +sink_byte_cnt[1] => source_byte_cnt.DATAB +sink_byte_cnt[1] => Add1.IN5 +sink_byte_cnt[1] => Equal1.IN1 +sink_byte_cnt[2] => source_byte_cnt.DATAB +sink_byte_cnt[2] => Add1.IN4 +sink_byte_cnt[2] => Equal1.IN0 +sink_is_compressed => last_packet_beat.IN1 +sink_burstsize[0] => Decoder0.IN2 +sink_burstsize[0] => source_burstsize[0].DATAIN +sink_burstsize[1] => Decoder0.IN1 +sink_burstsize[1] => source_burstsize[1].DATAIN +sink_burstsize[2] => Decoder0.IN0 +sink_burstsize[2] => source_burstsize[2].DATAIN +source_startofpacket <= source_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +source_endofpacket <= source_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +source_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE +source_ready => always1.IN1 +source_ready => sink_ready.IN1 +source_addr[0] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[1] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[2] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[3] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[4] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[5] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[6] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[7] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[8] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[9] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[10] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[11] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[12] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[13] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[14] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[15] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[16] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[17] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[18] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[19] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[20] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[21] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[22] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[23] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[24] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[25] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_burstwrap[0] <= sink_burstwrap[0].DB_MAX_OUTPUT_PORT_TYPE +source_burstwrap[1] <= sink_burstwrap[1].DB_MAX_OUTPUT_PORT_TYPE +source_burstwrap[2] <= sink_burstwrap[2].DB_MAX_OUTPUT_PORT_TYPE +source_byte_cnt[0] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE +source_byte_cnt[1] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE +source_byte_cnt[2] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE +source_is_compressed <= +source_burstsize[0] <= sink_burstsize[0].DB_MAX_OUTPUT_PORT_TYPE +source_burstsize[1] <= sink_burstsize[1].DB_MAX_OUTPUT_PORT_TYPE +source_burstsize[2] <= sink_burstsize[2].DB_MAX_OUTPUT_PORT_TYPE + + +|de0_nano_system|system:inst_cpu|altera_avalon_sc_fifo:pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo +clk => csr_readdata[0]~reg0.CLK +clk => csr_readdata[1]~reg0.CLK +clk => csr_readdata[2]~reg0.CLK +clk => csr_readdata[3]~reg0.CLK +clk => csr_readdata[4]~reg0.CLK +clk => csr_readdata[5]~reg0.CLK +clk => csr_readdata[6]~reg0.CLK +clk => csr_readdata[7]~reg0.CLK +clk => csr_readdata[8]~reg0.CLK +clk => csr_readdata[9]~reg0.CLK +clk => csr_readdata[10]~reg0.CLK +clk => csr_readdata[11]~reg0.CLK +clk => csr_readdata[12]~reg0.CLK +clk => csr_readdata[13]~reg0.CLK +clk => csr_readdata[14]~reg0.CLK +clk => csr_readdata[15]~reg0.CLK +clk => csr_readdata[16]~reg0.CLK +clk => csr_readdata[17]~reg0.CLK +clk => csr_readdata[18]~reg0.CLK +clk => csr_readdata[19]~reg0.CLK +clk => csr_readdata[20]~reg0.CLK +clk => csr_readdata[21]~reg0.CLK +clk => csr_readdata[22]~reg0.CLK +clk => csr_readdata[23]~reg0.CLK +clk => csr_readdata[24]~reg0.CLK +clk => csr_readdata[25]~reg0.CLK +clk => csr_readdata[26]~reg0.CLK +clk => csr_readdata[27]~reg0.CLK +clk => csr_readdata[28]~reg0.CLK +clk => csr_readdata[29]~reg0.CLK +clk => csr_readdata[30]~reg0.CLK +clk => csr_readdata[31]~reg0.CLK +clk => mem_used[1].CLK +clk => mem_used[0].CLK +clk => mem[1][0].CLK +clk => mem[1][1].CLK +clk => mem[1][2].CLK +clk => mem[1][3].CLK +clk => mem[1][4].CLK +clk => mem[1][5].CLK +clk => mem[1][6].CLK +clk => mem[1][7].CLK +clk => mem[1][8].CLK +clk => mem[1][9].CLK +clk => mem[1][10].CLK +clk => mem[1][11].CLK +clk => mem[1][12].CLK +clk => mem[1][13].CLK +clk => mem[1][14].CLK +clk => mem[1][15].CLK +clk => mem[1][16].CLK +clk => mem[1][17].CLK +clk => mem[1][18].CLK +clk => mem[1][19].CLK +clk => mem[1][20].CLK +clk => mem[1][21].CLK +clk => mem[1][22].CLK +clk => mem[1][23].CLK +clk => mem[1][24].CLK +clk => mem[1][25].CLK +clk => mem[1][26].CLK +clk => mem[1][27].CLK +clk => mem[1][28].CLK +clk => mem[1][29].CLK +clk => mem[1][30].CLK +clk => mem[1][31].CLK +clk => mem[1][32].CLK +clk => mem[1][33].CLK +clk => mem[1][34].CLK +clk => mem[1][35].CLK +clk => mem[1][36].CLK +clk => mem[1][37].CLK +clk => mem[1][38].CLK +clk => mem[1][39].CLK +clk => mem[1][40].CLK +clk => mem[1][41].CLK +clk => mem[1][42].CLK +clk => mem[1][43].CLK +clk => mem[1][44].CLK +clk => mem[1][45].CLK +clk => mem[1][46].CLK +clk => mem[1][47].CLK +clk => mem[1][48].CLK +clk => mem[1][49].CLK +clk => mem[1][50].CLK +clk => mem[1][51].CLK +clk => mem[1][52].CLK +clk => mem[1][53].CLK +clk => mem[1][54].CLK +clk => mem[1][55].CLK +clk => mem[1][56].CLK +clk => mem[1][57].CLK +clk => mem[1][58].CLK +clk => mem[1][59].CLK +clk => mem[1][60].CLK +clk => mem[1][61].CLK +clk => mem[1][62].CLK +clk => mem[1][63].CLK +clk => mem[1][64].CLK +clk => mem[1][65].CLK +clk => mem[1][66].CLK +clk => mem[1][67].CLK +clk => mem[1][68].CLK +clk => mem[1][69].CLK +clk => mem[1][70].CLK +clk => mem[1][71].CLK +clk => mem[1][72].CLK +clk => mem[1][73].CLK +clk => mem[1][74].CLK +clk => mem[1][75].CLK +clk => mem[1][76].CLK +clk => mem[1][77].CLK +clk => mem[1][78].CLK +clk => mem[1][79].CLK +clk => mem[1][80].CLK +clk => mem[1][81].CLK +clk => mem[1][82].CLK +clk => mem[1][83].CLK +clk => mem[1][84].CLK +clk => mem[1][85].CLK +clk => mem[1][86].CLK +clk => mem[1][87].CLK +clk => mem[1][88].CLK +clk => mem[1][89].CLK +clk => mem[1][90].CLK +clk => mem[1][91].CLK +clk => mem[1][92].CLK +clk => mem[1][93].CLK +clk => mem[1][94].CLK +clk => mem[1][95].CLK +clk => mem[1][96].CLK +clk => mem[1][97].CLK +clk => mem[1][98].CLK +clk => mem[1][99].CLK +clk => mem[1][100].CLK +clk => mem[1][101].CLK +clk => mem[1][102].CLK +clk => mem[1][103].CLK +clk => mem[0][0].CLK +clk => mem[0][1].CLK +clk => mem[0][2].CLK +clk => mem[0][3].CLK +clk => mem[0][4].CLK +clk => mem[0][5].CLK +clk => mem[0][6].CLK +clk => mem[0][7].CLK +clk => mem[0][8].CLK +clk => mem[0][9].CLK +clk => mem[0][10].CLK +clk => mem[0][11].CLK +clk => mem[0][12].CLK +clk => mem[0][13].CLK +clk => mem[0][14].CLK +clk => mem[0][15].CLK +clk => mem[0][16].CLK +clk => mem[0][17].CLK +clk => mem[0][18].CLK +clk => mem[0][19].CLK +clk => mem[0][20].CLK +clk => mem[0][21].CLK +clk => mem[0][22].CLK +clk => mem[0][23].CLK +clk => mem[0][24].CLK +clk => mem[0][25].CLK +clk => mem[0][26].CLK +clk => mem[0][27].CLK +clk => mem[0][28].CLK +clk => mem[0][29].CLK +clk => mem[0][30].CLK +clk => mem[0][31].CLK +clk => mem[0][32].CLK +clk => mem[0][33].CLK +clk => mem[0][34].CLK +clk => mem[0][35].CLK +clk => mem[0][36].CLK +clk => mem[0][37].CLK +clk => mem[0][38].CLK +clk => mem[0][39].CLK +clk => mem[0][40].CLK +clk => mem[0][41].CLK +clk => mem[0][42].CLK +clk => mem[0][43].CLK +clk => mem[0][44].CLK +clk => mem[0][45].CLK +clk => mem[0][46].CLK +clk => mem[0][47].CLK +clk => mem[0][48].CLK +clk => mem[0][49].CLK +clk => mem[0][50].CLK +clk => mem[0][51].CLK +clk => mem[0][52].CLK +clk => mem[0][53].CLK +clk => mem[0][54].CLK +clk => mem[0][55].CLK +clk => mem[0][56].CLK +clk => mem[0][57].CLK +clk => mem[0][58].CLK +clk => mem[0][59].CLK +clk => mem[0][60].CLK +clk => mem[0][61].CLK +clk => mem[0][62].CLK +clk => mem[0][63].CLK +clk => mem[0][64].CLK +clk => mem[0][65].CLK +clk => mem[0][66].CLK +clk => mem[0][67].CLK +clk => mem[0][68].CLK +clk => mem[0][69].CLK +clk => mem[0][70].CLK +clk => mem[0][71].CLK +clk => mem[0][72].CLK +clk => mem[0][73].CLK +clk => mem[0][74].CLK +clk => mem[0][75].CLK +clk => mem[0][76].CLK +clk => mem[0][77].CLK +clk => mem[0][78].CLK +clk => mem[0][79].CLK +clk => mem[0][80].CLK +clk => mem[0][81].CLK +clk => mem[0][82].CLK +clk => mem[0][83].CLK +clk => mem[0][84].CLK +clk => mem[0][85].CLK +clk => mem[0][86].CLK +clk => mem[0][87].CLK +clk => mem[0][88].CLK +clk => mem[0][89].CLK +clk => mem[0][90].CLK +clk => mem[0][91].CLK +clk => mem[0][92].CLK +clk => mem[0][93].CLK +clk => mem[0][94].CLK +clk => mem[0][95].CLK +clk => mem[0][96].CLK +clk => mem[0][97].CLK +clk => mem[0][98].CLK +clk => mem[0][99].CLK +clk => mem[0][100].CLK +clk => mem[0][101].CLK +clk => mem[0][102].CLK +clk => mem[0][103].CLK +reset => csr_readdata[0]~reg0.ACLR +reset => csr_readdata[1]~reg0.ACLR +reset => csr_readdata[2]~reg0.ACLR +reset => csr_readdata[3]~reg0.ACLR +reset => csr_readdata[4]~reg0.ACLR +reset => csr_readdata[5]~reg0.ACLR +reset => csr_readdata[6]~reg0.ACLR +reset => csr_readdata[7]~reg0.ACLR +reset => csr_readdata[8]~reg0.ACLR +reset => csr_readdata[9]~reg0.ACLR +reset => csr_readdata[10]~reg0.ACLR +reset => csr_readdata[11]~reg0.ACLR +reset => csr_readdata[12]~reg0.ACLR +reset => csr_readdata[13]~reg0.ACLR +reset => csr_readdata[14]~reg0.ACLR +reset => csr_readdata[15]~reg0.ACLR +reset => csr_readdata[16]~reg0.ACLR +reset => csr_readdata[17]~reg0.ACLR +reset => csr_readdata[18]~reg0.ACLR +reset => csr_readdata[19]~reg0.ACLR +reset => csr_readdata[20]~reg0.ACLR +reset => csr_readdata[21]~reg0.ACLR +reset => csr_readdata[22]~reg0.ACLR +reset => csr_readdata[23]~reg0.ACLR +reset => csr_readdata[24]~reg0.ACLR +reset => csr_readdata[25]~reg0.ACLR +reset => csr_readdata[26]~reg0.ACLR +reset => csr_readdata[27]~reg0.ACLR +reset => csr_readdata[28]~reg0.ACLR +reset => csr_readdata[29]~reg0.ACLR +reset => csr_readdata[30]~reg0.ACLR +reset => csr_readdata[31]~reg0.ACLR +reset => mem_used[1].ACLR +reset => mem_used[0].ACLR +reset => mem[1][0].ACLR +reset => mem[1][1].ACLR +reset => mem[1][2].ACLR +reset => mem[1][3].ACLR +reset => mem[1][4].ACLR +reset => mem[1][5].ACLR +reset => mem[1][6].ACLR +reset => mem[1][7].ACLR +reset => mem[1][8].ACLR +reset => mem[1][9].ACLR +reset => mem[1][10].ACLR +reset => mem[1][11].ACLR +reset => mem[1][12].ACLR +reset => mem[1][13].ACLR +reset => mem[1][14].ACLR +reset => mem[1][15].ACLR +reset => mem[1][16].ACLR +reset => mem[1][17].ACLR +reset => mem[1][18].ACLR +reset => mem[1][19].ACLR +reset => mem[1][20].ACLR +reset => mem[1][21].ACLR +reset => mem[1][22].ACLR +reset => mem[1][23].ACLR +reset => mem[1][24].ACLR +reset => mem[1][25].ACLR +reset => mem[1][26].ACLR +reset => mem[1][27].ACLR +reset => mem[1][28].ACLR +reset => mem[1][29].ACLR +reset => mem[1][30].ACLR +reset => mem[1][31].ACLR +reset => mem[1][32].ACLR +reset => mem[1][33].ACLR +reset => mem[1][34].ACLR +reset => mem[1][35].ACLR +reset => mem[1][36].ACLR +reset => mem[1][37].ACLR +reset => mem[1][38].ACLR +reset => mem[1][39].ACLR +reset => mem[1][40].ACLR +reset => mem[1][41].ACLR +reset => mem[1][42].ACLR +reset => mem[1][43].ACLR +reset => mem[1][44].ACLR +reset => mem[1][45].ACLR +reset => mem[1][46].ACLR +reset => mem[1][47].ACLR +reset => mem[1][48].ACLR +reset => mem[1][49].ACLR +reset => mem[1][50].ACLR +reset => mem[1][51].ACLR +reset => mem[1][52].ACLR +reset => mem[1][53].ACLR +reset => mem[1][54].ACLR +reset => mem[1][55].ACLR +reset => mem[1][56].ACLR +reset => mem[1][57].ACLR +reset => mem[1][58].ACLR +reset => mem[1][59].ACLR +reset => mem[1][60].ACLR +reset => mem[1][61].ACLR +reset => mem[1][62].ACLR +reset => mem[1][63].ACLR +reset => mem[1][64].ACLR +reset => mem[1][65].ACLR +reset => mem[1][66].ACLR +reset => mem[1][67].ACLR +reset => mem[1][68].ACLR +reset => mem[1][69].ACLR +reset => mem[1][70].ACLR +reset => mem[1][71].ACLR +reset => mem[1][72].ACLR +reset => mem[1][73].ACLR +reset => mem[1][74].ACLR +reset => mem[1][75].ACLR +reset => mem[1][76].ACLR +reset => mem[1][77].ACLR +reset => mem[1][78].ACLR +reset => mem[1][79].ACLR +reset => mem[1][80].ACLR +reset => mem[1][81].ACLR +reset => mem[1][82].ACLR +reset => mem[1][83].ACLR +reset => mem[1][84].ACLR +reset => mem[1][85].ACLR +reset => mem[1][86].ACLR +reset => mem[1][87].ACLR +reset => mem[1][88].ACLR +reset => mem[1][89].ACLR +reset => mem[1][90].ACLR +reset => mem[1][91].ACLR +reset => mem[1][92].ACLR +reset => mem[1][93].ACLR +reset => mem[1][94].ACLR +reset => mem[1][95].ACLR +reset => mem[1][96].ACLR +reset => mem[1][97].ACLR +reset => mem[1][98].ACLR +reset => mem[1][99].ACLR +reset => mem[1][100].ACLR +reset => mem[1][101].ACLR +reset => mem[1][102].ACLR +reset => mem[1][103].ACLR +reset => mem[0][0].ACLR +reset => mem[0][1].ACLR +reset => mem[0][2].ACLR +reset => mem[0][3].ACLR +reset => mem[0][4].ACLR +reset => mem[0][5].ACLR +reset => mem[0][6].ACLR +reset => mem[0][7].ACLR +reset => mem[0][8].ACLR +reset => mem[0][9].ACLR +reset => mem[0][10].ACLR +reset => mem[0][11].ACLR +reset => mem[0][12].ACLR +reset => mem[0][13].ACLR +reset => mem[0][14].ACLR +reset => mem[0][15].ACLR +reset => mem[0][16].ACLR +reset => mem[0][17].ACLR +reset => mem[0][18].ACLR +reset => mem[0][19].ACLR +reset => mem[0][20].ACLR +reset => mem[0][21].ACLR +reset => mem[0][22].ACLR +reset => mem[0][23].ACLR +reset => mem[0][24].ACLR +reset => mem[0][25].ACLR +reset => mem[0][26].ACLR +reset => mem[0][27].ACLR +reset => mem[0][28].ACLR +reset => mem[0][29].ACLR +reset => mem[0][30].ACLR +reset => mem[0][31].ACLR +reset => mem[0][32].ACLR +reset => mem[0][33].ACLR +reset => mem[0][34].ACLR +reset => mem[0][35].ACLR +reset => mem[0][36].ACLR +reset => mem[0][37].ACLR +reset => mem[0][38].ACLR +reset => mem[0][39].ACLR +reset => mem[0][40].ACLR +reset => mem[0][41].ACLR +reset => mem[0][42].ACLR +reset => mem[0][43].ACLR +reset => mem[0][44].ACLR +reset => mem[0][45].ACLR +reset => mem[0][46].ACLR +reset => mem[0][47].ACLR +reset => mem[0][48].ACLR +reset => mem[0][49].ACLR +reset => mem[0][50].ACLR +reset => mem[0][51].ACLR +reset => mem[0][52].ACLR +reset => mem[0][53].ACLR +reset => mem[0][54].ACLR +reset => mem[0][55].ACLR +reset => mem[0][56].ACLR +reset => mem[0][57].ACLR +reset => mem[0][58].ACLR +reset => mem[0][59].ACLR +reset => mem[0][60].ACLR +reset => mem[0][61].ACLR +reset => mem[0][62].ACLR +reset => mem[0][63].ACLR +reset => mem[0][64].ACLR +reset => mem[0][65].ACLR +reset => mem[0][66].ACLR +reset => mem[0][67].ACLR +reset => mem[0][68].ACLR +reset => mem[0][69].ACLR +reset => mem[0][70].ACLR +reset => mem[0][71].ACLR +reset => mem[0][72].ACLR +reset => mem[0][73].ACLR +reset => mem[0][74].ACLR +reset => mem[0][75].ACLR +reset => mem[0][76].ACLR +reset => mem[0][77].ACLR +reset => mem[0][78].ACLR +reset => mem[0][79].ACLR +reset => mem[0][80].ACLR +reset => mem[0][81].ACLR +reset => mem[0][82].ACLR +reset => mem[0][83].ACLR +reset => mem[0][84].ACLR +reset => mem[0][85].ACLR +reset => mem[0][86].ACLR +reset => mem[0][87].ACLR +reset => mem[0][88].ACLR +reset => mem[0][89].ACLR +reset => mem[0][90].ACLR +reset => mem[0][91].ACLR +reset => mem[0][92].ACLR +reset => mem[0][93].ACLR +reset => mem[0][94].ACLR +reset => mem[0][95].ACLR +reset => mem[0][96].ACLR +reset => mem[0][97].ACLR +reset => mem[0][98].ACLR +reset => mem[0][99].ACLR +reset => mem[0][100].ACLR +reset => mem[0][101].ACLR +reset => mem[0][102].ACLR +reset => mem[0][103].ACLR +in_data[0] => mem.DATAB +in_data[1] => mem.DATAB +in_data[2] => mem.DATAB +in_data[3] => mem.DATAB +in_data[4] => mem.DATAB +in_data[5] => mem.DATAB +in_data[6] => mem.DATAB +in_data[7] => mem.DATAB +in_data[8] => mem.DATAB +in_data[9] => mem.DATAB +in_data[10] => mem.DATAB +in_data[11] => mem.DATAB +in_data[12] => mem.DATAB +in_data[13] => mem.DATAB +in_data[14] => mem.DATAB +in_data[15] => mem.DATAB +in_data[16] => mem.DATAB +in_data[17] => mem.DATAB +in_data[18] => mem.DATAB +in_data[19] => mem.DATAB +in_data[20] => mem.DATAB +in_data[21] => mem.DATAB +in_data[22] => mem.DATAB +in_data[23] => mem.DATAB +in_data[24] => mem.DATAB +in_data[25] => mem.DATAB +in_data[26] => mem.DATAB +in_data[27] => mem.DATAB +in_data[28] => mem.DATAB +in_data[29] => mem.DATAB +in_data[30] => mem.DATAB +in_data[31] => mem.DATAB +in_data[32] => mem.DATAB +in_data[33] => mem.DATAB +in_data[34] => mem.DATAB +in_data[35] => mem.DATAB +in_data[36] => mem.DATAB +in_data[37] => mem.DATAB +in_data[38] => mem.DATAB +in_data[39] => mem.DATAB +in_data[40] => mem.DATAB +in_data[41] => mem.DATAB +in_data[42] => mem.DATAB +in_data[43] => mem.DATAB +in_data[44] => mem.DATAB +in_data[45] => mem.DATAB +in_data[46] => mem.DATAB +in_data[47] => mem.DATAB +in_data[48] => mem.DATAB +in_data[49] => mem.DATAB +in_data[50] => mem.DATAB +in_data[51] => mem.DATAB +in_data[52] => mem.DATAB +in_data[53] => mem.DATAB +in_data[54] => mem.DATAB +in_data[55] => mem.DATAB +in_data[56] => mem.DATAB +in_data[57] => mem.DATAB +in_data[58] => mem.DATAB +in_data[59] => mem.DATAB +in_data[60] => mem.DATAB +in_data[61] => mem.DATAB +in_data[62] => mem.DATAB +in_data[63] => mem.DATAB +in_data[64] => mem.DATAB +in_data[65] => mem.DATAB +in_data[66] => mem.DATAB +in_data[67] => mem.DATAB +in_data[68] => mem.DATAB +in_data[69] => mem.DATAB +in_data[70] => mem.DATAB +in_data[71] => mem.DATAB +in_data[72] => mem.DATAB +in_data[73] => mem.DATAB +in_data[74] => mem.DATAB +in_data[75] => mem.DATAB +in_data[76] => mem.DATAB +in_data[77] => mem.DATAB +in_data[78] => mem.DATAB +in_data[79] => mem.DATAB +in_data[80] => mem.DATAB +in_data[81] => mem.DATAB +in_data[82] => mem.DATAB +in_data[83] => mem.DATAB +in_data[84] => mem.DATAB +in_data[85] => mem.DATAB +in_data[86] => mem.DATAB +in_data[87] => mem.DATAB +in_data[88] => mem.DATAB +in_data[89] => mem.DATAB +in_data[90] => mem.DATAB +in_data[91] => mem.DATAB +in_data[92] => mem.DATAB +in_data[93] => mem.DATAB +in_data[94] => mem.DATAB +in_data[95] => mem.DATAB +in_data[96] => mem.DATAB +in_data[97] => mem.DATAB +in_data[98] => mem.DATAB +in_data[99] => mem.DATAB +in_data[100] => mem.DATAB +in_data[101] => mem.DATAB +in_valid => write.IN1 +in_startofpacket => mem.DATAB +in_endofpacket => mem.DATAB +in_empty[0] => ~NO_FANOUT~ +in_error[0] => out_error[0].DATAIN +in_error[0] => out_empty[0].DATAIN +in_channel[0] => out_channel[0].DATAIN +in_ready <= mem_used[1].DB_MAX_OUTPUT_PORT_TYPE +out_data[0] <= mem[0][0].DB_MAX_OUTPUT_PORT_TYPE +out_data[1] <= mem[0][1].DB_MAX_OUTPUT_PORT_TYPE +out_data[2] <= mem[0][2].DB_MAX_OUTPUT_PORT_TYPE +out_data[3] <= mem[0][3].DB_MAX_OUTPUT_PORT_TYPE +out_data[4] <= mem[0][4].DB_MAX_OUTPUT_PORT_TYPE +out_data[5] <= mem[0][5].DB_MAX_OUTPUT_PORT_TYPE +out_data[6] <= mem[0][6].DB_MAX_OUTPUT_PORT_TYPE +out_data[7] <= mem[0][7].DB_MAX_OUTPUT_PORT_TYPE +out_data[8] <= mem[0][8].DB_MAX_OUTPUT_PORT_TYPE +out_data[9] <= mem[0][9].DB_MAX_OUTPUT_PORT_TYPE +out_data[10] <= mem[0][10].DB_MAX_OUTPUT_PORT_TYPE +out_data[11] <= mem[0][11].DB_MAX_OUTPUT_PORT_TYPE +out_data[12] <= mem[0][12].DB_MAX_OUTPUT_PORT_TYPE +out_data[13] <= mem[0][13].DB_MAX_OUTPUT_PORT_TYPE +out_data[14] <= mem[0][14].DB_MAX_OUTPUT_PORT_TYPE +out_data[15] <= mem[0][15].DB_MAX_OUTPUT_PORT_TYPE +out_data[16] <= mem[0][16].DB_MAX_OUTPUT_PORT_TYPE +out_data[17] <= mem[0][17].DB_MAX_OUTPUT_PORT_TYPE +out_data[18] <= mem[0][18].DB_MAX_OUTPUT_PORT_TYPE +out_data[19] <= mem[0][19].DB_MAX_OUTPUT_PORT_TYPE +out_data[20] <= mem[0][20].DB_MAX_OUTPUT_PORT_TYPE +out_data[21] <= mem[0][21].DB_MAX_OUTPUT_PORT_TYPE +out_data[22] <= mem[0][22].DB_MAX_OUTPUT_PORT_TYPE +out_data[23] <= mem[0][23].DB_MAX_OUTPUT_PORT_TYPE +out_data[24] <= mem[0][24].DB_MAX_OUTPUT_PORT_TYPE +out_data[25] <= mem[0][25].DB_MAX_OUTPUT_PORT_TYPE +out_data[26] <= mem[0][26].DB_MAX_OUTPUT_PORT_TYPE +out_data[27] <= mem[0][27].DB_MAX_OUTPUT_PORT_TYPE +out_data[28] <= mem[0][28].DB_MAX_OUTPUT_PORT_TYPE +out_data[29] <= mem[0][29].DB_MAX_OUTPUT_PORT_TYPE +out_data[30] <= mem[0][30].DB_MAX_OUTPUT_PORT_TYPE +out_data[31] <= mem[0][31].DB_MAX_OUTPUT_PORT_TYPE +out_data[32] <= mem[0][32].DB_MAX_OUTPUT_PORT_TYPE +out_data[33] <= mem[0][33].DB_MAX_OUTPUT_PORT_TYPE +out_data[34] <= mem[0][34].DB_MAX_OUTPUT_PORT_TYPE +out_data[35] <= mem[0][35].DB_MAX_OUTPUT_PORT_TYPE +out_data[36] <= mem[0][36].DB_MAX_OUTPUT_PORT_TYPE +out_data[37] <= mem[0][37].DB_MAX_OUTPUT_PORT_TYPE +out_data[38] <= mem[0][38].DB_MAX_OUTPUT_PORT_TYPE +out_data[39] <= mem[0][39].DB_MAX_OUTPUT_PORT_TYPE +out_data[40] <= mem[0][40].DB_MAX_OUTPUT_PORT_TYPE +out_data[41] <= mem[0][41].DB_MAX_OUTPUT_PORT_TYPE +out_data[42] <= mem[0][42].DB_MAX_OUTPUT_PORT_TYPE +out_data[43] <= mem[0][43].DB_MAX_OUTPUT_PORT_TYPE +out_data[44] <= mem[0][44].DB_MAX_OUTPUT_PORT_TYPE +out_data[45] <= mem[0][45].DB_MAX_OUTPUT_PORT_TYPE +out_data[46] <= mem[0][46].DB_MAX_OUTPUT_PORT_TYPE +out_data[47] <= mem[0][47].DB_MAX_OUTPUT_PORT_TYPE +out_data[48] <= mem[0][48].DB_MAX_OUTPUT_PORT_TYPE +out_data[49] <= mem[0][49].DB_MAX_OUTPUT_PORT_TYPE +out_data[50] <= mem[0][50].DB_MAX_OUTPUT_PORT_TYPE +out_data[51] <= mem[0][51].DB_MAX_OUTPUT_PORT_TYPE +out_data[52] <= mem[0][52].DB_MAX_OUTPUT_PORT_TYPE +out_data[53] <= mem[0][53].DB_MAX_OUTPUT_PORT_TYPE +out_data[54] <= mem[0][54].DB_MAX_OUTPUT_PORT_TYPE +out_data[55] <= mem[0][55].DB_MAX_OUTPUT_PORT_TYPE +out_data[56] <= mem[0][56].DB_MAX_OUTPUT_PORT_TYPE +out_data[57] <= mem[0][57].DB_MAX_OUTPUT_PORT_TYPE +out_data[58] <= mem[0][58].DB_MAX_OUTPUT_PORT_TYPE +out_data[59] <= mem[0][59].DB_MAX_OUTPUT_PORT_TYPE +out_data[60] <= mem[0][60].DB_MAX_OUTPUT_PORT_TYPE +out_data[61] <= mem[0][61].DB_MAX_OUTPUT_PORT_TYPE +out_data[62] <= mem[0][62].DB_MAX_OUTPUT_PORT_TYPE +out_data[63] <= mem[0][63].DB_MAX_OUTPUT_PORT_TYPE +out_data[64] <= mem[0][64].DB_MAX_OUTPUT_PORT_TYPE +out_data[65] <= mem[0][65].DB_MAX_OUTPUT_PORT_TYPE +out_data[66] <= mem[0][66].DB_MAX_OUTPUT_PORT_TYPE +out_data[67] <= mem[0][67].DB_MAX_OUTPUT_PORT_TYPE +out_data[68] <= mem[0][68].DB_MAX_OUTPUT_PORT_TYPE +out_data[69] <= mem[0][69].DB_MAX_OUTPUT_PORT_TYPE +out_data[70] <= mem[0][70].DB_MAX_OUTPUT_PORT_TYPE +out_data[71] <= mem[0][71].DB_MAX_OUTPUT_PORT_TYPE +out_data[72] <= mem[0][72].DB_MAX_OUTPUT_PORT_TYPE +out_data[73] <= mem[0][73].DB_MAX_OUTPUT_PORT_TYPE +out_data[74] <= mem[0][74].DB_MAX_OUTPUT_PORT_TYPE +out_data[75] <= mem[0][75].DB_MAX_OUTPUT_PORT_TYPE +out_data[76] <= mem[0][76].DB_MAX_OUTPUT_PORT_TYPE +out_data[77] <= mem[0][77].DB_MAX_OUTPUT_PORT_TYPE +out_data[78] <= mem[0][78].DB_MAX_OUTPUT_PORT_TYPE +out_data[79] <= mem[0][79].DB_MAX_OUTPUT_PORT_TYPE +out_data[80] <= mem[0][80].DB_MAX_OUTPUT_PORT_TYPE +out_data[81] <= mem[0][81].DB_MAX_OUTPUT_PORT_TYPE +out_data[82] <= mem[0][82].DB_MAX_OUTPUT_PORT_TYPE +out_data[83] <= mem[0][83].DB_MAX_OUTPUT_PORT_TYPE +out_data[84] <= mem[0][84].DB_MAX_OUTPUT_PORT_TYPE +out_data[85] <= mem[0][85].DB_MAX_OUTPUT_PORT_TYPE +out_data[86] <= mem[0][86].DB_MAX_OUTPUT_PORT_TYPE +out_data[87] <= mem[0][87].DB_MAX_OUTPUT_PORT_TYPE +out_data[88] <= mem[0][88].DB_MAX_OUTPUT_PORT_TYPE +out_data[89] <= mem[0][89].DB_MAX_OUTPUT_PORT_TYPE +out_data[90] <= mem[0][90].DB_MAX_OUTPUT_PORT_TYPE +out_data[91] <= mem[0][91].DB_MAX_OUTPUT_PORT_TYPE +out_data[92] <= mem[0][92].DB_MAX_OUTPUT_PORT_TYPE +out_data[93] <= mem[0][93].DB_MAX_OUTPUT_PORT_TYPE +out_data[94] <= mem[0][94].DB_MAX_OUTPUT_PORT_TYPE +out_data[95] <= mem[0][95].DB_MAX_OUTPUT_PORT_TYPE +out_data[96] <= mem[0][96].DB_MAX_OUTPUT_PORT_TYPE +out_data[97] <= mem[0][97].DB_MAX_OUTPUT_PORT_TYPE +out_data[98] <= mem[0][98].DB_MAX_OUTPUT_PORT_TYPE +out_data[99] <= mem[0][99].DB_MAX_OUTPUT_PORT_TYPE +out_data[100] <= mem[0][100].DB_MAX_OUTPUT_PORT_TYPE +out_data[101] <= mem[0][101].DB_MAX_OUTPUT_PORT_TYPE +out_valid <= mem_used[0].DB_MAX_OUTPUT_PORT_TYPE +out_startofpacket <= mem[0][103].DB_MAX_OUTPUT_PORT_TYPE +out_endofpacket <= mem[0][102].DB_MAX_OUTPUT_PORT_TYPE +out_empty[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE +out_error[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE +out_channel[0] <= in_channel[0].DB_MAX_OUTPUT_PORT_TYPE +out_ready => internal_out_ready.IN1 +csr_address[0] => ~NO_FANOUT~ +csr_address[1] => ~NO_FANOUT~ +csr_write => ~NO_FANOUT~ +csr_read => csr_readdata[0]~reg0.ENA +csr_read => csr_readdata[31]~reg0.ENA +csr_read => csr_readdata[30]~reg0.ENA +csr_read => csr_readdata[29]~reg0.ENA +csr_read => csr_readdata[28]~reg0.ENA +csr_read => csr_readdata[27]~reg0.ENA +csr_read => csr_readdata[26]~reg0.ENA +csr_read => csr_readdata[25]~reg0.ENA +csr_read => csr_readdata[24]~reg0.ENA +csr_read => csr_readdata[23]~reg0.ENA +csr_read => csr_readdata[22]~reg0.ENA +csr_read => csr_readdata[21]~reg0.ENA +csr_read => csr_readdata[20]~reg0.ENA +csr_read => csr_readdata[19]~reg0.ENA +csr_read => csr_readdata[18]~reg0.ENA +csr_read => csr_readdata[17]~reg0.ENA +csr_read => csr_readdata[16]~reg0.ENA +csr_read => csr_readdata[15]~reg0.ENA +csr_read => csr_readdata[14]~reg0.ENA +csr_read => csr_readdata[13]~reg0.ENA +csr_read => csr_readdata[12]~reg0.ENA +csr_read => csr_readdata[11]~reg0.ENA +csr_read => csr_readdata[10]~reg0.ENA +csr_read => csr_readdata[9]~reg0.ENA +csr_read => csr_readdata[8]~reg0.ENA +csr_read => csr_readdata[7]~reg0.ENA +csr_read => csr_readdata[6]~reg0.ENA +csr_read => csr_readdata[5]~reg0.ENA +csr_read => csr_readdata[4]~reg0.ENA +csr_read => csr_readdata[3]~reg0.ENA +csr_read => csr_readdata[2]~reg0.ENA +csr_read => csr_readdata[1]~reg0.ENA +csr_writedata[0] => ~NO_FANOUT~ +csr_writedata[1] => ~NO_FANOUT~ +csr_writedata[2] => ~NO_FANOUT~ +csr_writedata[3] => ~NO_FANOUT~ +csr_writedata[4] => ~NO_FANOUT~ +csr_writedata[5] => ~NO_FANOUT~ +csr_writedata[6] => ~NO_FANOUT~ +csr_writedata[7] => ~NO_FANOUT~ +csr_writedata[8] => ~NO_FANOUT~ +csr_writedata[9] => ~NO_FANOUT~ +csr_writedata[10] => ~NO_FANOUT~ +csr_writedata[11] => ~NO_FANOUT~ +csr_writedata[12] => ~NO_FANOUT~ +csr_writedata[13] => ~NO_FANOUT~ +csr_writedata[14] => ~NO_FANOUT~ +csr_writedata[15] => ~NO_FANOUT~ +csr_writedata[16] => ~NO_FANOUT~ +csr_writedata[17] => ~NO_FANOUT~ +csr_writedata[18] => ~NO_FANOUT~ +csr_writedata[19] => ~NO_FANOUT~ +csr_writedata[20] => ~NO_FANOUT~ +csr_writedata[21] => ~NO_FANOUT~ +csr_writedata[22] => ~NO_FANOUT~ +csr_writedata[23] => ~NO_FANOUT~ +csr_writedata[24] => ~NO_FANOUT~ +csr_writedata[25] => ~NO_FANOUT~ +csr_writedata[26] => ~NO_FANOUT~ +csr_writedata[27] => ~NO_FANOUT~ +csr_writedata[28] => ~NO_FANOUT~ +csr_writedata[29] => ~NO_FANOUT~ +csr_writedata[30] => ~NO_FANOUT~ +csr_writedata[31] => ~NO_FANOUT~ +csr_readdata[0] <= csr_readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[1] <= csr_readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[2] <= csr_readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[3] <= csr_readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[4] <= csr_readdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[5] <= csr_readdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[6] <= csr_readdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[7] <= csr_readdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[8] <= csr_readdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[9] <= csr_readdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[10] <= csr_readdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[11] <= csr_readdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[12] <= csr_readdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[13] <= csr_readdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[14] <= csr_readdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[15] <= csr_readdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[16] <= csr_readdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[17] <= csr_readdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[18] <= csr_readdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[19] <= csr_readdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[20] <= csr_readdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[21] <= csr_readdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[22] <= csr_readdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[23] <= csr_readdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[24] <= csr_readdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[25] <= csr_readdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[26] <= csr_readdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[27] <= csr_readdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[28] <= csr_readdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[29] <= csr_readdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[30] <= csr_readdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[31] <= csr_readdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE +almost_full_data <= +almost_empty_data <= + + +|de0_nano_system|system:inst_cpu|altera_merlin_slave_agent:pio_key_s1_translator_avalon_universal_slave_0_agent +clk => clk.IN1 +reset => reset.IN1 +m0_address[0] <= +m0_address[1] <= +m0_address[2] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE +m0_address[3] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE +m0_address[4] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE +m0_address[5] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE +m0_address[6] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE +m0_address[7] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE +m0_address[8] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE +m0_address[9] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE +m0_address[10] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE +m0_address[11] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE +m0_address[12] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE +m0_address[13] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE +m0_address[14] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE +m0_address[15] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE +m0_address[16] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE +m0_address[17] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE +m0_address[18] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE +m0_address[19] <= cp_data[55].DB_MAX_OUTPUT_PORT_TYPE +m0_address[20] <= cp_data[56].DB_MAX_OUTPUT_PORT_TYPE +m0_address[21] <= cp_data[57].DB_MAX_OUTPUT_PORT_TYPE +m0_address[22] <= cp_data[58].DB_MAX_OUTPUT_PORT_TYPE +m0_address[23] <= cp_data[59].DB_MAX_OUTPUT_PORT_TYPE +m0_address[24] <= cp_data[60].DB_MAX_OUTPUT_PORT_TYPE +m0_address[25] <= cp_data[61].DB_MAX_OUTPUT_PORT_TYPE +m0_burstcount[0] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE +m0_burstcount[1] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE +m0_burstcount[2] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[0] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[1] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[2] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[3] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE +m0_read <= m0_read.DB_MAX_OUTPUT_PORT_TYPE +m0_readdata[0] => rdata_fifo_src_data[0].DATAIN +m0_readdata[1] => rdata_fifo_src_data[1].DATAIN +m0_readdata[2] => rdata_fifo_src_data[2].DATAIN +m0_readdata[3] => rdata_fifo_src_data[3].DATAIN +m0_readdata[4] => rdata_fifo_src_data[4].DATAIN +m0_readdata[5] => rdata_fifo_src_data[5].DATAIN +m0_readdata[6] => rdata_fifo_src_data[6].DATAIN +m0_readdata[7] => rdata_fifo_src_data[7].DATAIN +m0_readdata[8] => rdata_fifo_src_data[8].DATAIN +m0_readdata[9] => rdata_fifo_src_data[9].DATAIN +m0_readdata[10] => rdata_fifo_src_data[10].DATAIN +m0_readdata[11] => rdata_fifo_src_data[11].DATAIN +m0_readdata[12] => rdata_fifo_src_data[12].DATAIN +m0_readdata[13] => rdata_fifo_src_data[13].DATAIN +m0_readdata[14] => rdata_fifo_src_data[14].DATAIN +m0_readdata[15] => rdata_fifo_src_data[15].DATAIN +m0_readdata[16] => rdata_fifo_src_data[16].DATAIN +m0_readdata[17] => rdata_fifo_src_data[17].DATAIN +m0_readdata[18] => rdata_fifo_src_data[18].DATAIN +m0_readdata[19] => rdata_fifo_src_data[19].DATAIN +m0_readdata[20] => rdata_fifo_src_data[20].DATAIN +m0_readdata[21] => rdata_fifo_src_data[21].DATAIN +m0_readdata[22] => rdata_fifo_src_data[22].DATAIN +m0_readdata[23] => rdata_fifo_src_data[23].DATAIN +m0_readdata[24] => rdata_fifo_src_data[24].DATAIN +m0_readdata[25] => rdata_fifo_src_data[25].DATAIN +m0_readdata[26] => rdata_fifo_src_data[26].DATAIN +m0_readdata[27] => rdata_fifo_src_data[27].DATAIN +m0_readdata[28] => rdata_fifo_src_data[28].DATAIN +m0_readdata[29] => rdata_fifo_src_data[29].DATAIN +m0_readdata[30] => rdata_fifo_src_data[30].DATAIN +m0_readdata[31] => rdata_fifo_src_data[31].DATAIN +m0_waitrequest => cp_ready.IN0 +m0_write <= m0_write.DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[0] <= cp_data[0].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[1] <= cp_data[1].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[2] <= cp_data[2].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[3] <= cp_data[3].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[4] <= cp_data[4].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[5] <= cp_data[5].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[6] <= cp_data[6].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[7] <= cp_data[7].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[8] <= cp_data[8].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[9] <= cp_data[9].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[10] <= cp_data[10].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[11] <= cp_data[11].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[12] <= cp_data[12].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[13] <= cp_data[13].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[14] <= cp_data[14].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[15] <= cp_data[15].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[16] <= cp_data[16].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[17] <= cp_data[17].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[18] <= cp_data[18].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[19] <= cp_data[19].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[20] <= cp_data[20].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[21] <= cp_data[21].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[22] <= cp_data[22].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[23] <= cp_data[23].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[24] <= cp_data[24].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[25] <= cp_data[25].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[26] <= cp_data[26].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[27] <= cp_data[27].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[28] <= cp_data[28].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[29] <= cp_data[29].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[30] <= cp_data[30].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[31] <= cp_data[31].DB_MAX_OUTPUT_PORT_TYPE +m0_readdatavalid => rdata_fifo_src_valid.DATAIN +m0_debugaccess <= cp_data[92].DB_MAX_OUTPUT_PORT_TYPE +m0_lock <= m0_lock.DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[0] <= +rf_source_data[1] <= +rf_source_data[2] <= +rf_source_data[3] <= +rf_source_data[4] <= +rf_source_data[5] <= +rf_source_data[6] <= +rf_source_data[7] <= +rf_source_data[8] <= +rf_source_data[9] <= +rf_source_data[10] <= +rf_source_data[11] <= +rf_source_data[12] <= +rf_source_data[13] <= +rf_source_data[14] <= +rf_source_data[15] <= +rf_source_data[16] <= +rf_source_data[17] <= +rf_source_data[18] <= +rf_source_data[19] <= +rf_source_data[20] <= +rf_source_data[21] <= +rf_source_data[22] <= +rf_source_data[23] <= +rf_source_data[24] <= +rf_source_data[25] <= +rf_source_data[26] <= +rf_source_data[27] <= +rf_source_data[28] <= +rf_source_data[29] <= +rf_source_data[30] <= +rf_source_data[31] <= +rf_source_data[32] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[33] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[34] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[35] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[36] <= cp_data[36].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[37] <= cp_data[37].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[38] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[39] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[40] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[41] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[42] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[43] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[44] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[45] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[46] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[47] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[48] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[49] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[50] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[51] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[52] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[53] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[54] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[55] <= cp_data[55].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[56] <= cp_data[56].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[57] <= cp_data[57].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[58] <= cp_data[58].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[59] <= cp_data[59].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[60] <= cp_data[60].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[61] <= cp_data[61].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[62] <= cp_data[62].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[63] <= cp_data[63].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[64] <= cp_data[64].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[65] <= cp_data[65].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[66] <= cp_data[66].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[67] <= cp_data[67].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[68] <= cp_data[68].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[69] <= cp_data[69].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[70] <= cp_data[70].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[71] <= cp_data[71].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[72] <= cp_data[72].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[73] <= cp_data[73].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[74] <= cp_data[74].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[75] <= cp_data[75].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[76] <= cp_data[76].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[77] <= cp_data[77].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[78] <= cp_data[78].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[79] <= cp_data[79].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[80] <= cp_data[80].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[81] <= cp_data[81].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[82] <= cp_data[82].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[83] <= cp_data[83].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[84] <= cp_data[84].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[85] <= cp_data[85].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[86] <= cp_data[86].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[87] <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[88] <= cp_data[88].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[89] <= cp_data[89].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[90] <= cp_data[90].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[91] <= cp_data[91].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[92] <= cp_data[92].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[93] <= +rf_source_data[94] <= +rf_source_data[95] <= cp_data[95].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[96] <= cp_data[96].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[97] <= cp_data[97].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[98] <= cp_data[98].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[99] <= cp_data[99].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[100] <= cp_data[100].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[101] <= nonposted_write_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +rf_source_valid <= rf_source_valid.DB_MAX_OUTPUT_PORT_TYPE +rf_source_startofpacket <= cp_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +rf_source_endofpacket <= cp_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +rf_source_ready => cp_ready.IN1 +rf_source_ready => m0_write.IN1 +rf_source_ready => m0_lock.IN1 +rf_source_ready => rf_source_valid.IN1 +rf_source_ready => m0_read.IN1 +rf_sink_data[0] => ~NO_FANOUT~ +rf_sink_data[1] => ~NO_FANOUT~ +rf_sink_data[2] => ~NO_FANOUT~ +rf_sink_data[3] => ~NO_FANOUT~ +rf_sink_data[4] => ~NO_FANOUT~ +rf_sink_data[5] => ~NO_FANOUT~ +rf_sink_data[6] => ~NO_FANOUT~ +rf_sink_data[7] => ~NO_FANOUT~ +rf_sink_data[8] => ~NO_FANOUT~ +rf_sink_data[9] => ~NO_FANOUT~ +rf_sink_data[10] => ~NO_FANOUT~ +rf_sink_data[11] => ~NO_FANOUT~ +rf_sink_data[12] => ~NO_FANOUT~ +rf_sink_data[13] => ~NO_FANOUT~ +rf_sink_data[14] => ~NO_FANOUT~ +rf_sink_data[15] => ~NO_FANOUT~ +rf_sink_data[16] => ~NO_FANOUT~ +rf_sink_data[17] => ~NO_FANOUT~ +rf_sink_data[18] => ~NO_FANOUT~ +rf_sink_data[19] => ~NO_FANOUT~ +rf_sink_data[20] => ~NO_FANOUT~ +rf_sink_data[21] => ~NO_FANOUT~ +rf_sink_data[22] => ~NO_FANOUT~ +rf_sink_data[23] => ~NO_FANOUT~ +rf_sink_data[24] => ~NO_FANOUT~ +rf_sink_data[25] => ~NO_FANOUT~ +rf_sink_data[26] => ~NO_FANOUT~ +rf_sink_data[27] => ~NO_FANOUT~ +rf_sink_data[28] => ~NO_FANOUT~ +rf_sink_data[29] => ~NO_FANOUT~ +rf_sink_data[30] => ~NO_FANOUT~ +rf_sink_data[31] => ~NO_FANOUT~ +rf_sink_data[32] => rp_data[32].DATAIN +rf_sink_data[33] => rp_data[33].DATAIN +rf_sink_data[34] => rp_data[34].DATAIN +rf_sink_data[35] => rp_data[35].DATAIN +rf_sink_data[36] => rf_sink_addr[0].IN1 +rf_sink_data[37] => rf_sink_addr[1].IN1 +rf_sink_data[38] => rf_sink_addr[2].IN1 +rf_sink_data[39] => rf_sink_addr[3].IN1 +rf_sink_data[40] => rf_sink_addr[4].IN1 +rf_sink_data[41] => rf_sink_addr[5].IN1 +rf_sink_data[42] => rf_sink_addr[6].IN1 +rf_sink_data[43] => rf_sink_addr[7].IN1 +rf_sink_data[44] => rf_sink_addr[8].IN1 +rf_sink_data[45] => rf_sink_addr[9].IN1 +rf_sink_data[46] => rf_sink_addr[10].IN1 +rf_sink_data[47] => rf_sink_addr[11].IN1 +rf_sink_data[48] => rf_sink_addr[12].IN1 +rf_sink_data[49] => rf_sink_addr[13].IN1 +rf_sink_data[50] => rf_sink_addr[14].IN1 +rf_sink_data[51] => rf_sink_addr[15].IN1 +rf_sink_data[52] => rf_sink_addr[16].IN1 +rf_sink_data[53] => rf_sink_addr[17].IN1 +rf_sink_data[54] => rf_sink_addr[18].IN1 +rf_sink_data[55] => rf_sink_addr[19].IN1 +rf_sink_data[56] => rf_sink_addr[20].IN1 +rf_sink_data[57] => rf_sink_addr[21].IN1 +rf_sink_data[58] => rf_sink_addr[22].IN1 +rf_sink_data[59] => rf_sink_addr[23].IN1 +rf_sink_data[60] => rf_sink_addr[24].IN1 +rf_sink_data[61] => rf_sink_addr[25].IN1 +rf_sink_data[62] => rf_sink_compressed.IN1 +rf_sink_data[63] => rp_data[63].DATAIN +rf_sink_data[64] => comb.OUTPUTSELECT +rf_sink_data[64] => rp_data[64].DATAIN +rf_sink_data[65] => rp_data.IN0 +rf_sink_data[66] => rp_data[66].DATAIN +rf_sink_data[67] => rp_data[67].DATAIN +rf_sink_data[68] => rf_sink_byte_cnt[0].IN1 +rf_sink_data[69] => rf_sink_byte_cnt[1].IN1 +rf_sink_data[70] => rf_sink_byte_cnt[2].IN1 +rf_sink_data[71] => rf_sink_burstwrap[0].IN1 +rf_sink_data[72] => rf_sink_burstwrap[1].IN1 +rf_sink_data[73] => rf_sink_burstwrap[2].IN1 +rf_sink_data[74] => rf_sink_burstsize[0].IN1 +rf_sink_data[75] => rf_sink_burstsize[1].IN1 +rf_sink_data[76] => rf_sink_burstsize[2].IN1 +rf_sink_data[77] => rp_data[77].DATAIN +rf_sink_data[78] => rp_data[78].DATAIN +rf_sink_data[79] => rp_data[79].DATAIN +rf_sink_data[80] => rp_data[80].DATAIN +rf_sink_data[81] => rp_data[81].DATAIN +rf_sink_data[82] => rp_data[82].DATAIN +rf_sink_data[83] => rp_data[87].DATAIN +rf_sink_data[84] => rp_data[88].DATAIN +rf_sink_data[85] => rp_data[89].DATAIN +rf_sink_data[86] => rp_data[90].DATAIN +rf_sink_data[87] => rp_data[83].DATAIN +rf_sink_data[88] => rp_data[84].DATAIN +rf_sink_data[89] => rp_data[85].DATAIN +rf_sink_data[90] => rp_data[86].DATAIN +rf_sink_data[91] => rp_data[91].DATAIN +rf_sink_data[92] => rp_data[92].DATAIN +rf_sink_data[93] => rp_data[93].DATAIN +rf_sink_data[94] => rp_data[94].DATAIN +rf_sink_data[95] => rp_data[95].DATAIN +rf_sink_data[96] => rp_data[96].DATAIN +rf_sink_data[97] => rp_data[97].DATAIN +rf_sink_data[98] => rp_data[98].DATAIN +rf_sink_data[99] => ~NO_FANOUT~ +rf_sink_data[100] => ~NO_FANOUT~ +rf_sink_data[101] => rdata_fifo_sink_ready.IN0 +rf_sink_data[101] => comb.IN0 +rf_sink_valid => rdata_fifo_sink_ready.IN1 +rf_sink_valid => comb.IN1 +rf_sink_startofpacket => comb.DATAA +rf_sink_endofpacket => rf_sink_endofpacket.IN1 +rf_sink_ready <= altera_merlin_burst_uncompressor:uncompressor.sink_ready +rdata_fifo_src_data[0] <= m0_readdata[0].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[1] <= m0_readdata[1].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[2] <= m0_readdata[2].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[3] <= m0_readdata[3].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[4] <= m0_readdata[4].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[5] <= m0_readdata[5].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[6] <= m0_readdata[6].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[7] <= m0_readdata[7].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[8] <= m0_readdata[8].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[9] <= m0_readdata[9].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[10] <= m0_readdata[10].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[11] <= m0_readdata[11].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[12] <= m0_readdata[12].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[13] <= m0_readdata[13].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[14] <= m0_readdata[14].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[15] <= m0_readdata[15].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[16] <= m0_readdata[16].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[17] <= m0_readdata[17].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[18] <= m0_readdata[18].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[19] <= m0_readdata[19].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[20] <= m0_readdata[20].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[21] <= m0_readdata[21].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[22] <= m0_readdata[22].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[23] <= m0_readdata[23].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[24] <= m0_readdata[24].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[25] <= m0_readdata[25].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[26] <= m0_readdata[26].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[27] <= m0_readdata[27].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[28] <= m0_readdata[28].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[29] <= m0_readdata[29].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[30] <= m0_readdata[30].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[31] <= m0_readdata[31].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_valid <= m0_readdatavalid.DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_ready => ~NO_FANOUT~ +rdata_fifo_sink_data[0] => rp_data[0].DATAIN +rdata_fifo_sink_data[1] => rp_data[1].DATAIN +rdata_fifo_sink_data[2] => rp_data[2].DATAIN +rdata_fifo_sink_data[3] => rp_data[3].DATAIN +rdata_fifo_sink_data[4] => rp_data[4].DATAIN +rdata_fifo_sink_data[5] => rp_data[5].DATAIN +rdata_fifo_sink_data[6] => rp_data[6].DATAIN +rdata_fifo_sink_data[7] => rp_data[7].DATAIN +rdata_fifo_sink_data[8] => rp_data[8].DATAIN +rdata_fifo_sink_data[9] => rp_data[9].DATAIN +rdata_fifo_sink_data[10] => rp_data[10].DATAIN +rdata_fifo_sink_data[11] => rp_data[11].DATAIN +rdata_fifo_sink_data[12] => rp_data[12].DATAIN +rdata_fifo_sink_data[13] => rp_data[13].DATAIN +rdata_fifo_sink_data[14] => rp_data[14].DATAIN +rdata_fifo_sink_data[15] => rp_data[15].DATAIN +rdata_fifo_sink_data[16] => rp_data[16].DATAIN +rdata_fifo_sink_data[17] => rp_data[17].DATAIN +rdata_fifo_sink_data[18] => rp_data[18].DATAIN +rdata_fifo_sink_data[19] => rp_data[19].DATAIN +rdata_fifo_sink_data[20] => rp_data[20].DATAIN +rdata_fifo_sink_data[21] => rp_data[21].DATAIN +rdata_fifo_sink_data[22] => rp_data[22].DATAIN +rdata_fifo_sink_data[23] => rp_data[23].DATAIN +rdata_fifo_sink_data[24] => rp_data[24].DATAIN +rdata_fifo_sink_data[25] => rp_data[25].DATAIN +rdata_fifo_sink_data[26] => rp_data[26].DATAIN +rdata_fifo_sink_data[27] => rp_data[27].DATAIN +rdata_fifo_sink_data[28] => rp_data[28].DATAIN +rdata_fifo_sink_data[29] => rp_data[29].DATAIN +rdata_fifo_sink_data[30] => rp_data[30].DATAIN +rdata_fifo_sink_data[31] => rp_data[31].DATAIN +rdata_fifo_sink_valid => rp_valid.IN1 +rdata_fifo_sink_valid => rdata_fifo_sink_ready.IN0 +rdata_fifo_sink_valid => comb.IN1 +rdata_fifo_sink_ready <= rdata_fifo_sink_ready.DB_MAX_OUTPUT_PORT_TYPE +cp_ready <= cp_ready.DB_MAX_OUTPUT_PORT_TYPE +cp_valid => local_lock.IN0 +cp_valid => local_write.IN0 +cp_valid => local_read.IN0 +cp_valid => local_compressed_read.IN0 +cp_data[0] => m0_writedata[0].DATAIN +cp_data[1] => m0_writedata[1].DATAIN +cp_data[2] => m0_writedata[2].DATAIN +cp_data[3] => m0_writedata[3].DATAIN +cp_data[4] => m0_writedata[4].DATAIN +cp_data[5] => m0_writedata[5].DATAIN +cp_data[6] => m0_writedata[6].DATAIN +cp_data[7] => m0_writedata[7].DATAIN +cp_data[8] => m0_writedata[8].DATAIN +cp_data[9] => m0_writedata[9].DATAIN +cp_data[10] => m0_writedata[10].DATAIN +cp_data[11] => m0_writedata[11].DATAIN +cp_data[12] => m0_writedata[12].DATAIN +cp_data[13] => m0_writedata[13].DATAIN +cp_data[14] => m0_writedata[14].DATAIN +cp_data[15] => m0_writedata[15].DATAIN +cp_data[16] => m0_writedata[16].DATAIN +cp_data[17] => m0_writedata[17].DATAIN +cp_data[18] => m0_writedata[18].DATAIN +cp_data[19] => m0_writedata[19].DATAIN +cp_data[20] => m0_writedata[20].DATAIN +cp_data[21] => m0_writedata[21].DATAIN +cp_data[22] => m0_writedata[22].DATAIN +cp_data[23] => m0_writedata[23].DATAIN +cp_data[24] => m0_writedata[24].DATAIN +cp_data[25] => m0_writedata[25].DATAIN +cp_data[26] => m0_writedata[26].DATAIN +cp_data[27] => m0_writedata[27].DATAIN +cp_data[28] => m0_writedata[28].DATAIN +cp_data[29] => m0_writedata[29].DATAIN +cp_data[30] => m0_writedata[30].DATAIN +cp_data[31] => m0_writedata[31].DATAIN +cp_data[32] => rf_source_data[32].DATAIN +cp_data[32] => m0_byteenable[0].DATAIN +cp_data[33] => rf_source_data[33].DATAIN +cp_data[33] => m0_byteenable[1].DATAIN +cp_data[34] => rf_source_data[34].DATAIN +cp_data[34] => m0_byteenable[2].DATAIN +cp_data[35] => rf_source_data[35].DATAIN +cp_data[35] => m0_byteenable[3].DATAIN +cp_data[36] => rf_source_data[36].DATAIN +cp_data[37] => rf_source_data[37].DATAIN +cp_data[38] => rf_source_data[38].DATAIN +cp_data[38] => m0_address[2].DATAIN +cp_data[39] => rf_source_data[39].DATAIN +cp_data[39] => m0_address[3].DATAIN +cp_data[40] => rf_source_data[40].DATAIN +cp_data[40] => m0_address[4].DATAIN +cp_data[41] => rf_source_data[41].DATAIN +cp_data[41] => m0_address[5].DATAIN +cp_data[42] => rf_source_data[42].DATAIN +cp_data[42] => m0_address[6].DATAIN +cp_data[43] => rf_source_data[43].DATAIN +cp_data[43] => m0_address[7].DATAIN +cp_data[44] => rf_source_data[44].DATAIN +cp_data[44] => m0_address[8].DATAIN +cp_data[45] => rf_source_data[45].DATAIN +cp_data[45] => m0_address[9].DATAIN +cp_data[46] => rf_source_data[46].DATAIN +cp_data[46] => m0_address[10].DATAIN +cp_data[47] => rf_source_data[47].DATAIN +cp_data[47] => m0_address[11].DATAIN +cp_data[48] => rf_source_data[48].DATAIN +cp_data[48] => m0_address[12].DATAIN +cp_data[49] => rf_source_data[49].DATAIN +cp_data[49] => m0_address[13].DATAIN +cp_data[50] => rf_source_data[50].DATAIN +cp_data[50] => m0_address[14].DATAIN +cp_data[51] => rf_source_data[51].DATAIN +cp_data[51] => m0_address[15].DATAIN +cp_data[52] => rf_source_data[52].DATAIN +cp_data[52] => m0_address[16].DATAIN +cp_data[53] => rf_source_data[53].DATAIN +cp_data[53] => m0_address[17].DATAIN +cp_data[54] => rf_source_data[54].DATAIN +cp_data[54] => m0_address[18].DATAIN +cp_data[55] => rf_source_data[55].DATAIN +cp_data[55] => m0_address[19].DATAIN +cp_data[56] => rf_source_data[56].DATAIN +cp_data[56] => m0_address[20].DATAIN +cp_data[57] => rf_source_data[57].DATAIN +cp_data[57] => m0_address[21].DATAIN +cp_data[58] => rf_source_data[58].DATAIN +cp_data[58] => m0_address[22].DATAIN +cp_data[59] => rf_source_data[59].DATAIN +cp_data[59] => m0_address[23].DATAIN +cp_data[60] => rf_source_data[60].DATAIN +cp_data[60] => m0_address[24].DATAIN +cp_data[61] => rf_source_data[61].DATAIN +cp_data[61] => m0_address[25].DATAIN +cp_data[62] => local_compressed_read.IN1 +cp_data[62] => rf_source_data[62].DATAIN +cp_data[63] => rf_source_data[63].DATAIN +cp_data[63] => comb.IN1 +cp_data[64] => local_write.IN1 +cp_data[64] => rf_source_data[64].DATAIN +cp_data[65] => local_read.IN1 +cp_data[65] => rf_source_data[65].DATAIN +cp_data[66] => local_lock.IN1 +cp_data[66] => rf_source_data[66].DATAIN +cp_data[67] => rf_source_data[67].DATAIN +cp_data[68] => m0_burstcount.DATAA +cp_data[68] => rf_source_data[68].DATAIN +cp_data[69] => m0_burstcount.DATAA +cp_data[69] => rf_source_data[69].DATAIN +cp_data[70] => m0_burstcount.DATAA +cp_data[70] => rf_source_data[70].DATAIN +cp_data[71] => rf_source_data[71].DATAIN +cp_data[72] => rf_source_data[72].DATAIN +cp_data[73] => rf_source_data[73].DATAIN +cp_data[74] => rf_source_data[74].DATAIN +cp_data[75] => rf_source_data[75].DATAIN +cp_data[76] => rf_source_data[76].DATAIN +cp_data[77] => rf_source_data[77].DATAIN +cp_data[78] => rf_source_data[78].DATAIN +cp_data[79] => rf_source_data[79].DATAIN +cp_data[80] => rf_source_data[80].DATAIN +cp_data[81] => rf_source_data[81].DATAIN +cp_data[82] => rf_source_data[82].DATAIN +cp_data[83] => rf_source_data[83].DATAIN +cp_data[84] => rf_source_data[84].DATAIN +cp_data[85] => rf_source_data[85].DATAIN +cp_data[86] => rf_source_data[86].DATAIN +cp_data[87] => rf_source_data[87].DATAIN +cp_data[88] => rf_source_data[88].DATAIN +cp_data[89] => rf_source_data[89].DATAIN +cp_data[90] => rf_source_data[90].DATAIN +cp_data[91] => rf_source_data[91].DATAIN +cp_data[92] => rf_source_data[92].DATAIN +cp_data[92] => m0_debugaccess.DATAIN +cp_data[93] => ~NO_FANOUT~ +cp_data[94] => ~NO_FANOUT~ +cp_data[95] => rf_source_data[95].DATAIN +cp_data[96] => rf_source_data[96].DATAIN +cp_data[97] => rf_source_data[97].DATAIN +cp_data[98] => rf_source_data[98].DATAIN +cp_data[99] => rf_source_data[99].DATAIN +cp_data[100] => rf_source_data[100].DATAIN +cp_channel[0] => ~NO_FANOUT~ +cp_channel[1] => ~NO_FANOUT~ +cp_channel[2] => ~NO_FANOUT~ +cp_channel[3] => ~NO_FANOUT~ +cp_channel[4] => ~NO_FANOUT~ +cp_channel[5] => ~NO_FANOUT~ +cp_channel[6] => ~NO_FANOUT~ +cp_channel[7] => ~NO_FANOUT~ +cp_channel[8] => ~NO_FANOUT~ +cp_channel[9] => ~NO_FANOUT~ +cp_channel[10] => ~NO_FANOUT~ +cp_startofpacket => rf_source_startofpacket.DATAIN +cp_endofpacket => nonposted_write_endofpacket.IN1 +cp_endofpacket => rf_source_endofpacket.DATAIN +rp_ready => rp_ready.IN1 +rp_valid <= rp_valid.DB_MAX_OUTPUT_PORT_TYPE +rp_data[0] <= rdata_fifo_sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +rp_data[1] <= rdata_fifo_sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +rp_data[2] <= rdata_fifo_sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +rp_data[3] <= rdata_fifo_sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +rp_data[4] <= rdata_fifo_sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +rp_data[5] <= rdata_fifo_sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +rp_data[6] <= rdata_fifo_sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +rp_data[7] <= rdata_fifo_sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +rp_data[8] <= rdata_fifo_sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +rp_data[9] <= rdata_fifo_sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +rp_data[10] <= rdata_fifo_sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +rp_data[11] <= rdata_fifo_sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +rp_data[12] <= rdata_fifo_sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +rp_data[13] <= rdata_fifo_sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +rp_data[14] <= rdata_fifo_sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +rp_data[15] <= rdata_fifo_sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +rp_data[16] <= rdata_fifo_sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +rp_data[17] <= rdata_fifo_sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +rp_data[18] <= rdata_fifo_sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +rp_data[19] <= rdata_fifo_sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +rp_data[20] <= rdata_fifo_sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +rp_data[21] <= rdata_fifo_sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +rp_data[22] <= rdata_fifo_sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +rp_data[23] <= rdata_fifo_sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +rp_data[24] <= rdata_fifo_sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +rp_data[25] <= rdata_fifo_sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +rp_data[26] <= rdata_fifo_sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +rp_data[27] <= rdata_fifo_sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +rp_data[28] <= rdata_fifo_sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +rp_data[29] <= rdata_fifo_sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +rp_data[30] <= rdata_fifo_sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +rp_data[31] <= rdata_fifo_sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +rp_data[32] <= rf_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +rp_data[33] <= rf_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +rp_data[34] <= rf_sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +rp_data[35] <= rf_sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +rp_data[36] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[37] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[38] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[39] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[40] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[41] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[42] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[43] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[44] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[45] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[46] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[47] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[48] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[49] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[50] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[51] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[52] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[53] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[54] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[55] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[56] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[57] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[58] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[59] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[60] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[61] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[62] <= altera_merlin_burst_uncompressor:uncompressor.source_is_compressed +rp_data[63] <= rf_sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +rp_data[64] <= rf_sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +rp_data[65] <= rp_data.DB_MAX_OUTPUT_PORT_TYPE +rp_data[66] <= rf_sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +rp_data[67] <= rf_sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +rp_data[68] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt +rp_data[69] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt +rp_data[70] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt +rp_data[71] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap +rp_data[72] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap +rp_data[73] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap +rp_data[74] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize +rp_data[75] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize +rp_data[76] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize +rp_data[77] <= rf_sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +rp_data[78] <= rf_sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +rp_data[79] <= rf_sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +rp_data[80] <= rf_sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +rp_data[81] <= rf_sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +rp_data[82] <= rf_sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +rp_data[83] <= rf_sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +rp_data[84] <= rf_sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +rp_data[85] <= rf_sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +rp_data[86] <= rf_sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +rp_data[87] <= rf_sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +rp_data[88] <= rf_sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +rp_data[89] <= rf_sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +rp_data[90] <= rf_sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +rp_data[91] <= rf_sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +rp_data[92] <= rf_sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +rp_data[93] <= rf_sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +rp_data[94] <= rf_sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +rp_data[95] <= rf_sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +rp_data[96] <= rf_sink_data[96].DB_MAX_OUTPUT_PORT_TYPE +rp_data[97] <= rf_sink_data[97].DB_MAX_OUTPUT_PORT_TYPE +rp_data[98] <= rf_sink_data[98].DB_MAX_OUTPUT_PORT_TYPE +rp_data[99] <= +rp_data[100] <= +rp_startofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_startofpacket +rp_endofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_endofpacket + + +|de0_nano_system|system:inst_cpu|altera_merlin_slave_agent:pio_key_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor +clk => burst_uncompress_address_offset[0].CLK +clk => burst_uncompress_address_offset[1].CLK +clk => burst_uncompress_address_offset[2].CLK +clk => burst_uncompress_address_offset[3].CLK +clk => burst_uncompress_address_offset[4].CLK +clk => burst_uncompress_address_offset[5].CLK +clk => burst_uncompress_address_offset[6].CLK +clk => burst_uncompress_address_offset[7].CLK +clk => burst_uncompress_address_offset[8].CLK +clk => burst_uncompress_address_offset[9].CLK +clk => burst_uncompress_address_offset[10].CLK +clk => burst_uncompress_address_offset[11].CLK +clk => burst_uncompress_address_offset[12].CLK +clk => burst_uncompress_address_offset[13].CLK +clk => burst_uncompress_address_offset[14].CLK +clk => burst_uncompress_address_offset[15].CLK +clk => burst_uncompress_address_offset[16].CLK +clk => burst_uncompress_address_offset[17].CLK +clk => burst_uncompress_address_offset[18].CLK +clk => burst_uncompress_address_offset[19].CLK +clk => burst_uncompress_address_offset[20].CLK +clk => burst_uncompress_address_offset[21].CLK +clk => burst_uncompress_address_offset[22].CLK +clk => burst_uncompress_address_offset[23].CLK +clk => burst_uncompress_address_offset[24].CLK +clk => burst_uncompress_address_offset[25].CLK +clk => burst_uncompress_address_base[0].CLK +clk => burst_uncompress_address_base[1].CLK +clk => burst_uncompress_address_base[2].CLK +clk => burst_uncompress_address_base[3].CLK +clk => burst_uncompress_address_base[4].CLK +clk => burst_uncompress_address_base[5].CLK +clk => burst_uncompress_address_base[6].CLK +clk => burst_uncompress_address_base[7].CLK +clk => burst_uncompress_address_base[8].CLK +clk => burst_uncompress_address_base[9].CLK +clk => burst_uncompress_address_base[10].CLK +clk => burst_uncompress_address_base[11].CLK +clk => burst_uncompress_address_base[12].CLK +clk => burst_uncompress_address_base[13].CLK +clk => burst_uncompress_address_base[14].CLK +clk => burst_uncompress_address_base[15].CLK +clk => burst_uncompress_address_base[16].CLK +clk => burst_uncompress_address_base[17].CLK +clk => burst_uncompress_address_base[18].CLK +clk => burst_uncompress_address_base[19].CLK +clk => burst_uncompress_address_base[20].CLK +clk => burst_uncompress_address_base[21].CLK +clk => burst_uncompress_address_base[22].CLK +clk => burst_uncompress_address_base[23].CLK +clk => burst_uncompress_address_base[24].CLK +clk => burst_uncompress_address_base[25].CLK +clk => burst_uncompress_byte_counter[0].CLK +clk => burst_uncompress_byte_counter[1].CLK +clk => burst_uncompress_byte_counter[2].CLK +clk => burst_uncompress_busy.CLK +reset => burst_uncompress_address_offset[0].ACLR +reset => burst_uncompress_address_offset[1].ACLR +reset => burst_uncompress_address_offset[2].ACLR +reset => burst_uncompress_address_offset[3].ACLR +reset => burst_uncompress_address_offset[4].ACLR +reset => burst_uncompress_address_offset[5].ACLR +reset => burst_uncompress_address_offset[6].ACLR +reset => burst_uncompress_address_offset[7].ACLR +reset => burst_uncompress_address_offset[8].ACLR +reset => burst_uncompress_address_offset[9].ACLR +reset => burst_uncompress_address_offset[10].ACLR +reset => burst_uncompress_address_offset[11].ACLR +reset => burst_uncompress_address_offset[12].ACLR +reset => burst_uncompress_address_offset[13].ACLR +reset => burst_uncompress_address_offset[14].ACLR +reset => burst_uncompress_address_offset[15].ACLR +reset => burst_uncompress_address_offset[16].ACLR +reset => burst_uncompress_address_offset[17].ACLR +reset => burst_uncompress_address_offset[18].ACLR +reset => burst_uncompress_address_offset[19].ACLR +reset => burst_uncompress_address_offset[20].ACLR +reset => burst_uncompress_address_offset[21].ACLR +reset => burst_uncompress_address_offset[22].ACLR +reset => burst_uncompress_address_offset[23].ACLR +reset => burst_uncompress_address_offset[24].ACLR +reset => burst_uncompress_address_offset[25].ACLR +reset => burst_uncompress_address_base[0].ACLR +reset => burst_uncompress_address_base[1].ACLR +reset => burst_uncompress_address_base[2].ACLR +reset => burst_uncompress_address_base[3].ACLR +reset => burst_uncompress_address_base[4].ACLR +reset => burst_uncompress_address_base[5].ACLR +reset => burst_uncompress_address_base[6].ACLR +reset => burst_uncompress_address_base[7].ACLR +reset => burst_uncompress_address_base[8].ACLR +reset => burst_uncompress_address_base[9].ACLR +reset => burst_uncompress_address_base[10].ACLR +reset => burst_uncompress_address_base[11].ACLR +reset => burst_uncompress_address_base[12].ACLR +reset => burst_uncompress_address_base[13].ACLR +reset => burst_uncompress_address_base[14].ACLR +reset => burst_uncompress_address_base[15].ACLR +reset => burst_uncompress_address_base[16].ACLR +reset => burst_uncompress_address_base[17].ACLR +reset => burst_uncompress_address_base[18].ACLR +reset => burst_uncompress_address_base[19].ACLR +reset => burst_uncompress_address_base[20].ACLR +reset => burst_uncompress_address_base[21].ACLR +reset => burst_uncompress_address_base[22].ACLR +reset => burst_uncompress_address_base[23].ACLR +reset => burst_uncompress_address_base[24].ACLR +reset => burst_uncompress_address_base[25].ACLR +reset => burst_uncompress_byte_counter[0].ACLR +reset => burst_uncompress_byte_counter[1].ACLR +reset => burst_uncompress_byte_counter[2].ACLR +reset => burst_uncompress_busy.ACLR +sink_startofpacket => source_startofpacket.IN1 +sink_endofpacket => source_endofpacket.IN1 +sink_valid => first_packet_beat.IN1 +sink_valid => last_packet_beat.IN1 +sink_valid => last_packet_beat.IN1 +sink_valid => always0.IN1 +sink_valid => sink_ready.IN0 +sink_valid => source_valid.DATAIN +sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE +sink_addr[0] => burst_uncompress_address_base.IN0 +sink_addr[0] => comb.DATAB +sink_addr[0] => source_addr.DATAB +sink_addr[1] => burst_uncompress_address_base.IN0 +sink_addr[1] => comb.DATAB +sink_addr[1] => source_addr.DATAB +sink_addr[2] => burst_uncompress_address_base.IN0 +sink_addr[2] => comb.DATAB +sink_addr[2] => source_addr.DATAB +sink_addr[3] => burst_uncompress_address_base.IN0 +sink_addr[3] => comb.DATAB +sink_addr[3] => source_addr.DATAB +sink_addr[4] => burst_uncompress_address_base.IN0 +sink_addr[4] => comb.DATAB +sink_addr[4] => source_addr.DATAB +sink_addr[5] => burst_uncompress_address_base.IN0 +sink_addr[5] => comb.DATAB +sink_addr[5] => source_addr.DATAB +sink_addr[6] => burst_uncompress_address_base.IN0 +sink_addr[6] => comb.DATAB +sink_addr[6] => source_addr.DATAB +sink_addr[7] => burst_uncompress_address_base.IN0 +sink_addr[7] => comb.DATAB +sink_addr[7] => source_addr.DATAB +sink_addr[8] => burst_uncompress_address_base.IN0 +sink_addr[8] => comb.DATAB +sink_addr[8] => source_addr.DATAB +sink_addr[9] => burst_uncompress_address_base.IN0 +sink_addr[9] => comb.DATAB +sink_addr[9] => source_addr.DATAB +sink_addr[10] => burst_uncompress_address_base.IN0 +sink_addr[10] => comb.DATAB +sink_addr[10] => source_addr.DATAB +sink_addr[11] => burst_uncompress_address_base.IN0 +sink_addr[11] => comb.DATAB +sink_addr[11] => source_addr.DATAB +sink_addr[12] => burst_uncompress_address_base.IN0 +sink_addr[12] => comb.DATAB +sink_addr[12] => source_addr.DATAB +sink_addr[13] => burst_uncompress_address_base.IN0 +sink_addr[13] => comb.DATAB +sink_addr[13] => source_addr.DATAB +sink_addr[14] => burst_uncompress_address_base.IN0 +sink_addr[14] => comb.DATAB +sink_addr[14] => source_addr.DATAB +sink_addr[15] => burst_uncompress_address_base.IN0 +sink_addr[15] => comb.DATAB +sink_addr[15] => source_addr.DATAB +sink_addr[16] => burst_uncompress_address_base.IN0 +sink_addr[16] => comb.DATAB +sink_addr[16] => source_addr.DATAB +sink_addr[17] => burst_uncompress_address_base.IN0 +sink_addr[17] => comb.DATAB +sink_addr[17] => source_addr.DATAB +sink_addr[18] => burst_uncompress_address_base.IN0 +sink_addr[18] => comb.DATAB +sink_addr[18] => source_addr.DATAB +sink_addr[19] => burst_uncompress_address_base.IN0 +sink_addr[19] => comb.DATAB +sink_addr[19] => source_addr.DATAB +sink_addr[20] => burst_uncompress_address_base.IN0 +sink_addr[20] => comb.DATAB +sink_addr[20] => source_addr.DATAB +sink_addr[21] => burst_uncompress_address_base.IN0 +sink_addr[21] => comb.DATAB +sink_addr[21] => source_addr.DATAB +sink_addr[22] => burst_uncompress_address_base.IN0 +sink_addr[22] => comb.DATAB +sink_addr[22] => source_addr.DATAB +sink_addr[23] => burst_uncompress_address_base.IN0 +sink_addr[23] => comb.DATAB +sink_addr[23] => source_addr.DATAB +sink_addr[24] => burst_uncompress_address_base.IN0 +sink_addr[24] => comb.DATAB +sink_addr[24] => source_addr.DATAB +sink_addr[25] => burst_uncompress_address_base.IN0 +sink_addr[25] => comb.DATAB +sink_addr[25] => source_addr.DATAB +sink_burstwrap[0] => p1_burst_uncompress_address_offset[0].IN1 +sink_burstwrap[0] => source_burstwrap[0].DATAIN +sink_burstwrap[0] => burst_uncompress_address_base.IN1 +sink_burstwrap[1] => p1_burst_uncompress_address_offset[1].IN1 +sink_burstwrap[1] => source_burstwrap[1].DATAIN +sink_burstwrap[1] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[2].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[25].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[24].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[23].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[22].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[21].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[20].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[19].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[18].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[17].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[16].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[15].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[14].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[13].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[12].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[11].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[10].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[9].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[8].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[7].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[6].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[5].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[4].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[3].IN1 +sink_burstwrap[2] => source_burstwrap[2].DATAIN +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_byte_cnt[0] => source_byte_cnt.DATAB +sink_byte_cnt[0] => Add1.IN6 +sink_byte_cnt[0] => Equal1.IN2 +sink_byte_cnt[1] => source_byte_cnt.DATAB +sink_byte_cnt[1] => Add1.IN5 +sink_byte_cnt[1] => Equal1.IN1 +sink_byte_cnt[2] => source_byte_cnt.DATAB +sink_byte_cnt[2] => Add1.IN4 +sink_byte_cnt[2] => Equal1.IN0 +sink_is_compressed => last_packet_beat.IN1 +sink_burstsize[0] => Decoder0.IN2 +sink_burstsize[0] => source_burstsize[0].DATAIN +sink_burstsize[1] => Decoder0.IN1 +sink_burstsize[1] => source_burstsize[1].DATAIN +sink_burstsize[2] => Decoder0.IN0 +sink_burstsize[2] => source_burstsize[2].DATAIN +source_startofpacket <= source_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +source_endofpacket <= source_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +source_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE +source_ready => always1.IN1 +source_ready => sink_ready.IN1 +source_addr[0] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[1] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[2] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[3] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[4] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[5] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[6] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[7] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[8] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[9] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[10] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[11] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[12] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[13] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[14] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[15] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[16] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[17] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[18] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[19] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[20] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[21] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[22] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[23] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[24] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[25] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_burstwrap[0] <= sink_burstwrap[0].DB_MAX_OUTPUT_PORT_TYPE +source_burstwrap[1] <= sink_burstwrap[1].DB_MAX_OUTPUT_PORT_TYPE +source_burstwrap[2] <= sink_burstwrap[2].DB_MAX_OUTPUT_PORT_TYPE +source_byte_cnt[0] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE +source_byte_cnt[1] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE +source_byte_cnt[2] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE +source_is_compressed <= +source_burstsize[0] <= sink_burstsize[0].DB_MAX_OUTPUT_PORT_TYPE +source_burstsize[1] <= sink_burstsize[1].DB_MAX_OUTPUT_PORT_TYPE +source_burstsize[2] <= sink_burstsize[2].DB_MAX_OUTPUT_PORT_TYPE + + +|de0_nano_system|system:inst_cpu|altera_avalon_sc_fifo:pio_key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo +clk => csr_readdata[0]~reg0.CLK +clk => csr_readdata[1]~reg0.CLK +clk => csr_readdata[2]~reg0.CLK +clk => csr_readdata[3]~reg0.CLK +clk => csr_readdata[4]~reg0.CLK +clk => csr_readdata[5]~reg0.CLK +clk => csr_readdata[6]~reg0.CLK +clk => csr_readdata[7]~reg0.CLK +clk => csr_readdata[8]~reg0.CLK +clk => csr_readdata[9]~reg0.CLK +clk => csr_readdata[10]~reg0.CLK +clk => csr_readdata[11]~reg0.CLK +clk => csr_readdata[12]~reg0.CLK +clk => csr_readdata[13]~reg0.CLK +clk => csr_readdata[14]~reg0.CLK +clk => csr_readdata[15]~reg0.CLK +clk => csr_readdata[16]~reg0.CLK +clk => csr_readdata[17]~reg0.CLK +clk => csr_readdata[18]~reg0.CLK +clk => csr_readdata[19]~reg0.CLK +clk => csr_readdata[20]~reg0.CLK +clk => csr_readdata[21]~reg0.CLK +clk => csr_readdata[22]~reg0.CLK +clk => csr_readdata[23]~reg0.CLK +clk => csr_readdata[24]~reg0.CLK +clk => csr_readdata[25]~reg0.CLK +clk => csr_readdata[26]~reg0.CLK +clk => csr_readdata[27]~reg0.CLK +clk => csr_readdata[28]~reg0.CLK +clk => csr_readdata[29]~reg0.CLK +clk => csr_readdata[30]~reg0.CLK +clk => csr_readdata[31]~reg0.CLK +clk => mem_used[1].CLK +clk => mem_used[0].CLK +clk => mem[1][0].CLK +clk => mem[1][1].CLK +clk => mem[1][2].CLK +clk => mem[1][3].CLK +clk => mem[1][4].CLK +clk => mem[1][5].CLK +clk => mem[1][6].CLK +clk => mem[1][7].CLK +clk => mem[1][8].CLK +clk => mem[1][9].CLK +clk => mem[1][10].CLK +clk => mem[1][11].CLK +clk => mem[1][12].CLK +clk => mem[1][13].CLK +clk => mem[1][14].CLK +clk => mem[1][15].CLK +clk => mem[1][16].CLK +clk => mem[1][17].CLK +clk => mem[1][18].CLK +clk => mem[1][19].CLK +clk => mem[1][20].CLK +clk => mem[1][21].CLK +clk => mem[1][22].CLK +clk => mem[1][23].CLK +clk => mem[1][24].CLK +clk => mem[1][25].CLK +clk => mem[1][26].CLK +clk => mem[1][27].CLK +clk => mem[1][28].CLK +clk => mem[1][29].CLK +clk => mem[1][30].CLK +clk => mem[1][31].CLK +clk => mem[1][32].CLK +clk => mem[1][33].CLK +clk => mem[1][34].CLK +clk => mem[1][35].CLK +clk => mem[1][36].CLK +clk => mem[1][37].CLK +clk => mem[1][38].CLK +clk => mem[1][39].CLK +clk => mem[1][40].CLK +clk => mem[1][41].CLK +clk => mem[1][42].CLK +clk => mem[1][43].CLK +clk => mem[1][44].CLK +clk => mem[1][45].CLK +clk => mem[1][46].CLK +clk => mem[1][47].CLK +clk => mem[1][48].CLK +clk => mem[1][49].CLK +clk => mem[1][50].CLK +clk => mem[1][51].CLK +clk => mem[1][52].CLK +clk => mem[1][53].CLK +clk => mem[1][54].CLK +clk => mem[1][55].CLK +clk => mem[1][56].CLK +clk => mem[1][57].CLK +clk => mem[1][58].CLK +clk => mem[1][59].CLK +clk => mem[1][60].CLK +clk => mem[1][61].CLK +clk => mem[1][62].CLK +clk => mem[1][63].CLK +clk => mem[1][64].CLK +clk => mem[1][65].CLK +clk => mem[1][66].CLK +clk => mem[1][67].CLK +clk => mem[1][68].CLK +clk => mem[1][69].CLK +clk => mem[1][70].CLK +clk => mem[1][71].CLK +clk => mem[1][72].CLK +clk => mem[1][73].CLK +clk => mem[1][74].CLK +clk => mem[1][75].CLK +clk => mem[1][76].CLK +clk => mem[1][77].CLK +clk => mem[1][78].CLK +clk => mem[1][79].CLK +clk => mem[1][80].CLK +clk => mem[1][81].CLK +clk => mem[1][82].CLK +clk => mem[1][83].CLK +clk => mem[1][84].CLK +clk => mem[1][85].CLK +clk => mem[1][86].CLK +clk => mem[1][87].CLK +clk => mem[1][88].CLK +clk => mem[1][89].CLK +clk => mem[1][90].CLK +clk => mem[1][91].CLK +clk => mem[1][92].CLK +clk => mem[1][93].CLK +clk => mem[1][94].CLK +clk => mem[1][95].CLK +clk => mem[1][96].CLK +clk => mem[1][97].CLK +clk => mem[1][98].CLK +clk => mem[1][99].CLK +clk => mem[1][100].CLK +clk => mem[1][101].CLK +clk => mem[1][102].CLK +clk => mem[1][103].CLK +clk => mem[0][0].CLK +clk => mem[0][1].CLK +clk => mem[0][2].CLK +clk => mem[0][3].CLK +clk => mem[0][4].CLK +clk => mem[0][5].CLK +clk => mem[0][6].CLK +clk => mem[0][7].CLK +clk => mem[0][8].CLK +clk => mem[0][9].CLK +clk => mem[0][10].CLK +clk => mem[0][11].CLK +clk => mem[0][12].CLK +clk => mem[0][13].CLK +clk => mem[0][14].CLK +clk => mem[0][15].CLK +clk => mem[0][16].CLK +clk => mem[0][17].CLK +clk => mem[0][18].CLK +clk => mem[0][19].CLK +clk => mem[0][20].CLK +clk => mem[0][21].CLK +clk => mem[0][22].CLK +clk => mem[0][23].CLK +clk => mem[0][24].CLK +clk => mem[0][25].CLK +clk => mem[0][26].CLK +clk => mem[0][27].CLK +clk => mem[0][28].CLK +clk => mem[0][29].CLK +clk => mem[0][30].CLK +clk => mem[0][31].CLK +clk => mem[0][32].CLK +clk => mem[0][33].CLK +clk => mem[0][34].CLK +clk => mem[0][35].CLK +clk => mem[0][36].CLK +clk => mem[0][37].CLK +clk => mem[0][38].CLK +clk => mem[0][39].CLK +clk => mem[0][40].CLK +clk => mem[0][41].CLK +clk => mem[0][42].CLK +clk => mem[0][43].CLK +clk => mem[0][44].CLK +clk => mem[0][45].CLK +clk => mem[0][46].CLK +clk => mem[0][47].CLK +clk => mem[0][48].CLK +clk => mem[0][49].CLK +clk => mem[0][50].CLK +clk => mem[0][51].CLK +clk => mem[0][52].CLK +clk => mem[0][53].CLK +clk => mem[0][54].CLK +clk => mem[0][55].CLK +clk => mem[0][56].CLK +clk => mem[0][57].CLK +clk => mem[0][58].CLK +clk => mem[0][59].CLK +clk => mem[0][60].CLK +clk => mem[0][61].CLK +clk => mem[0][62].CLK +clk => mem[0][63].CLK +clk => mem[0][64].CLK +clk => mem[0][65].CLK +clk => mem[0][66].CLK +clk => mem[0][67].CLK +clk => mem[0][68].CLK +clk => mem[0][69].CLK +clk => mem[0][70].CLK +clk => mem[0][71].CLK +clk => mem[0][72].CLK +clk => mem[0][73].CLK +clk => mem[0][74].CLK +clk => mem[0][75].CLK +clk => mem[0][76].CLK +clk => mem[0][77].CLK +clk => mem[0][78].CLK +clk => mem[0][79].CLK +clk => mem[0][80].CLK +clk => mem[0][81].CLK +clk => mem[0][82].CLK +clk => mem[0][83].CLK +clk => mem[0][84].CLK +clk => mem[0][85].CLK +clk => mem[0][86].CLK +clk => mem[0][87].CLK +clk => mem[0][88].CLK +clk => mem[0][89].CLK +clk => mem[0][90].CLK +clk => mem[0][91].CLK +clk => mem[0][92].CLK +clk => mem[0][93].CLK +clk => mem[0][94].CLK +clk => mem[0][95].CLK +clk => mem[0][96].CLK +clk => mem[0][97].CLK +clk => mem[0][98].CLK +clk => mem[0][99].CLK +clk => mem[0][100].CLK +clk => mem[0][101].CLK +clk => mem[0][102].CLK +clk => mem[0][103].CLK +reset => csr_readdata[0]~reg0.ACLR +reset => csr_readdata[1]~reg0.ACLR +reset => csr_readdata[2]~reg0.ACLR +reset => csr_readdata[3]~reg0.ACLR +reset => csr_readdata[4]~reg0.ACLR +reset => csr_readdata[5]~reg0.ACLR +reset => csr_readdata[6]~reg0.ACLR +reset => csr_readdata[7]~reg0.ACLR +reset => csr_readdata[8]~reg0.ACLR +reset => csr_readdata[9]~reg0.ACLR +reset => csr_readdata[10]~reg0.ACLR +reset => csr_readdata[11]~reg0.ACLR +reset => csr_readdata[12]~reg0.ACLR +reset => csr_readdata[13]~reg0.ACLR +reset => csr_readdata[14]~reg0.ACLR +reset => csr_readdata[15]~reg0.ACLR +reset => csr_readdata[16]~reg0.ACLR +reset => csr_readdata[17]~reg0.ACLR +reset => csr_readdata[18]~reg0.ACLR +reset => csr_readdata[19]~reg0.ACLR +reset => csr_readdata[20]~reg0.ACLR +reset => csr_readdata[21]~reg0.ACLR +reset => csr_readdata[22]~reg0.ACLR +reset => csr_readdata[23]~reg0.ACLR +reset => csr_readdata[24]~reg0.ACLR +reset => csr_readdata[25]~reg0.ACLR +reset => csr_readdata[26]~reg0.ACLR +reset => csr_readdata[27]~reg0.ACLR +reset => csr_readdata[28]~reg0.ACLR +reset => csr_readdata[29]~reg0.ACLR +reset => csr_readdata[30]~reg0.ACLR +reset => csr_readdata[31]~reg0.ACLR +reset => mem_used[1].ACLR +reset => mem_used[0].ACLR +reset => mem[1][0].ACLR +reset => mem[1][1].ACLR +reset => mem[1][2].ACLR +reset => mem[1][3].ACLR +reset => mem[1][4].ACLR +reset => mem[1][5].ACLR +reset => mem[1][6].ACLR +reset => mem[1][7].ACLR +reset => mem[1][8].ACLR +reset => mem[1][9].ACLR +reset => mem[1][10].ACLR +reset => mem[1][11].ACLR +reset => mem[1][12].ACLR +reset => mem[1][13].ACLR +reset => mem[1][14].ACLR +reset => mem[1][15].ACLR +reset => mem[1][16].ACLR +reset => mem[1][17].ACLR +reset => mem[1][18].ACLR +reset => mem[1][19].ACLR +reset => mem[1][20].ACLR +reset => mem[1][21].ACLR +reset => mem[1][22].ACLR +reset => mem[1][23].ACLR +reset => mem[1][24].ACLR +reset => mem[1][25].ACLR +reset => mem[1][26].ACLR +reset => mem[1][27].ACLR +reset => mem[1][28].ACLR +reset => mem[1][29].ACLR +reset => mem[1][30].ACLR +reset => mem[1][31].ACLR +reset => mem[1][32].ACLR +reset => mem[1][33].ACLR +reset => mem[1][34].ACLR +reset => mem[1][35].ACLR +reset => mem[1][36].ACLR +reset => mem[1][37].ACLR +reset => mem[1][38].ACLR +reset => mem[1][39].ACLR +reset => mem[1][40].ACLR +reset => mem[1][41].ACLR +reset => mem[1][42].ACLR +reset => mem[1][43].ACLR +reset => mem[1][44].ACLR +reset => mem[1][45].ACLR +reset => mem[1][46].ACLR +reset => mem[1][47].ACLR +reset => mem[1][48].ACLR +reset => mem[1][49].ACLR +reset => mem[1][50].ACLR +reset => mem[1][51].ACLR +reset => mem[1][52].ACLR +reset => mem[1][53].ACLR +reset => mem[1][54].ACLR +reset => mem[1][55].ACLR +reset => mem[1][56].ACLR +reset => mem[1][57].ACLR +reset => mem[1][58].ACLR +reset => mem[1][59].ACLR +reset => mem[1][60].ACLR +reset => mem[1][61].ACLR +reset => mem[1][62].ACLR +reset => mem[1][63].ACLR +reset => mem[1][64].ACLR +reset => mem[1][65].ACLR +reset => mem[1][66].ACLR +reset => mem[1][67].ACLR +reset => mem[1][68].ACLR +reset => mem[1][69].ACLR +reset => mem[1][70].ACLR +reset => mem[1][71].ACLR +reset => mem[1][72].ACLR +reset => mem[1][73].ACLR +reset => mem[1][74].ACLR +reset => mem[1][75].ACLR +reset => mem[1][76].ACLR +reset => mem[1][77].ACLR +reset => mem[1][78].ACLR +reset => mem[1][79].ACLR +reset => mem[1][80].ACLR +reset => mem[1][81].ACLR +reset => mem[1][82].ACLR +reset => mem[1][83].ACLR +reset => mem[1][84].ACLR +reset => mem[1][85].ACLR +reset => mem[1][86].ACLR +reset => mem[1][87].ACLR +reset => mem[1][88].ACLR +reset => mem[1][89].ACLR +reset => mem[1][90].ACLR +reset => mem[1][91].ACLR +reset => mem[1][92].ACLR +reset => mem[1][93].ACLR +reset => mem[1][94].ACLR +reset => mem[1][95].ACLR +reset => mem[1][96].ACLR +reset => mem[1][97].ACLR +reset => mem[1][98].ACLR +reset => mem[1][99].ACLR +reset => mem[1][100].ACLR +reset => mem[1][101].ACLR +reset => mem[1][102].ACLR +reset => mem[1][103].ACLR +reset => mem[0][0].ACLR +reset => mem[0][1].ACLR +reset => mem[0][2].ACLR +reset => mem[0][3].ACLR +reset => mem[0][4].ACLR +reset => mem[0][5].ACLR +reset => mem[0][6].ACLR +reset => mem[0][7].ACLR +reset => mem[0][8].ACLR +reset => mem[0][9].ACLR +reset => mem[0][10].ACLR +reset => mem[0][11].ACLR +reset => mem[0][12].ACLR +reset => mem[0][13].ACLR +reset => mem[0][14].ACLR +reset => mem[0][15].ACLR +reset => mem[0][16].ACLR +reset => mem[0][17].ACLR +reset => mem[0][18].ACLR +reset => mem[0][19].ACLR +reset => mem[0][20].ACLR +reset => mem[0][21].ACLR +reset => mem[0][22].ACLR +reset => mem[0][23].ACLR +reset => mem[0][24].ACLR +reset => mem[0][25].ACLR +reset => mem[0][26].ACLR +reset => mem[0][27].ACLR +reset => mem[0][28].ACLR +reset => mem[0][29].ACLR +reset => mem[0][30].ACLR +reset => mem[0][31].ACLR +reset => mem[0][32].ACLR +reset => mem[0][33].ACLR +reset => mem[0][34].ACLR +reset => mem[0][35].ACLR +reset => mem[0][36].ACLR +reset => mem[0][37].ACLR +reset => mem[0][38].ACLR +reset => mem[0][39].ACLR +reset => mem[0][40].ACLR +reset => mem[0][41].ACLR +reset => mem[0][42].ACLR +reset => mem[0][43].ACLR +reset => mem[0][44].ACLR +reset => mem[0][45].ACLR +reset => mem[0][46].ACLR +reset => mem[0][47].ACLR +reset => mem[0][48].ACLR +reset => mem[0][49].ACLR +reset => mem[0][50].ACLR +reset => mem[0][51].ACLR +reset => mem[0][52].ACLR +reset => mem[0][53].ACLR +reset => mem[0][54].ACLR +reset => mem[0][55].ACLR +reset => mem[0][56].ACLR +reset => mem[0][57].ACLR +reset => mem[0][58].ACLR +reset => mem[0][59].ACLR +reset => mem[0][60].ACLR +reset => mem[0][61].ACLR +reset => mem[0][62].ACLR +reset => mem[0][63].ACLR +reset => mem[0][64].ACLR +reset => mem[0][65].ACLR +reset => mem[0][66].ACLR +reset => mem[0][67].ACLR +reset => mem[0][68].ACLR +reset => mem[0][69].ACLR +reset => mem[0][70].ACLR +reset => mem[0][71].ACLR +reset => mem[0][72].ACLR +reset => mem[0][73].ACLR +reset => mem[0][74].ACLR +reset => mem[0][75].ACLR +reset => mem[0][76].ACLR +reset => mem[0][77].ACLR +reset => mem[0][78].ACLR +reset => mem[0][79].ACLR +reset => mem[0][80].ACLR +reset => mem[0][81].ACLR +reset => mem[0][82].ACLR +reset => mem[0][83].ACLR +reset => mem[0][84].ACLR +reset => mem[0][85].ACLR +reset => mem[0][86].ACLR +reset => mem[0][87].ACLR +reset => mem[0][88].ACLR +reset => mem[0][89].ACLR +reset => mem[0][90].ACLR +reset => mem[0][91].ACLR +reset => mem[0][92].ACLR +reset => mem[0][93].ACLR +reset => mem[0][94].ACLR +reset => mem[0][95].ACLR +reset => mem[0][96].ACLR +reset => mem[0][97].ACLR +reset => mem[0][98].ACLR +reset => mem[0][99].ACLR +reset => mem[0][100].ACLR +reset => mem[0][101].ACLR +reset => mem[0][102].ACLR +reset => mem[0][103].ACLR +in_data[0] => mem.DATAB +in_data[1] => mem.DATAB +in_data[2] => mem.DATAB +in_data[3] => mem.DATAB +in_data[4] => mem.DATAB +in_data[5] => mem.DATAB +in_data[6] => mem.DATAB +in_data[7] => mem.DATAB +in_data[8] => mem.DATAB +in_data[9] => mem.DATAB +in_data[10] => mem.DATAB +in_data[11] => mem.DATAB +in_data[12] => mem.DATAB +in_data[13] => mem.DATAB +in_data[14] => mem.DATAB +in_data[15] => mem.DATAB +in_data[16] => mem.DATAB +in_data[17] => mem.DATAB +in_data[18] => mem.DATAB +in_data[19] => mem.DATAB +in_data[20] => mem.DATAB +in_data[21] => mem.DATAB +in_data[22] => mem.DATAB +in_data[23] => mem.DATAB +in_data[24] => mem.DATAB +in_data[25] => mem.DATAB +in_data[26] => mem.DATAB +in_data[27] => mem.DATAB +in_data[28] => mem.DATAB +in_data[29] => mem.DATAB +in_data[30] => mem.DATAB +in_data[31] => mem.DATAB +in_data[32] => mem.DATAB +in_data[33] => mem.DATAB +in_data[34] => mem.DATAB +in_data[35] => mem.DATAB +in_data[36] => mem.DATAB +in_data[37] => mem.DATAB +in_data[38] => mem.DATAB +in_data[39] => mem.DATAB +in_data[40] => mem.DATAB +in_data[41] => mem.DATAB +in_data[42] => mem.DATAB +in_data[43] => mem.DATAB +in_data[44] => mem.DATAB +in_data[45] => mem.DATAB +in_data[46] => mem.DATAB +in_data[47] => mem.DATAB +in_data[48] => mem.DATAB +in_data[49] => mem.DATAB +in_data[50] => mem.DATAB +in_data[51] => mem.DATAB +in_data[52] => mem.DATAB +in_data[53] => mem.DATAB +in_data[54] => mem.DATAB +in_data[55] => mem.DATAB +in_data[56] => mem.DATAB +in_data[57] => mem.DATAB +in_data[58] => mem.DATAB +in_data[59] => mem.DATAB +in_data[60] => mem.DATAB +in_data[61] => mem.DATAB +in_data[62] => mem.DATAB +in_data[63] => mem.DATAB +in_data[64] => mem.DATAB +in_data[65] => mem.DATAB +in_data[66] => mem.DATAB +in_data[67] => mem.DATAB +in_data[68] => mem.DATAB +in_data[69] => mem.DATAB +in_data[70] => mem.DATAB +in_data[71] => mem.DATAB +in_data[72] => mem.DATAB +in_data[73] => mem.DATAB +in_data[74] => mem.DATAB +in_data[75] => mem.DATAB +in_data[76] => mem.DATAB +in_data[77] => mem.DATAB +in_data[78] => mem.DATAB +in_data[79] => mem.DATAB +in_data[80] => mem.DATAB +in_data[81] => mem.DATAB +in_data[82] => mem.DATAB +in_data[83] => mem.DATAB +in_data[84] => mem.DATAB +in_data[85] => mem.DATAB +in_data[86] => mem.DATAB +in_data[87] => mem.DATAB +in_data[88] => mem.DATAB +in_data[89] => mem.DATAB +in_data[90] => mem.DATAB +in_data[91] => mem.DATAB +in_data[92] => mem.DATAB +in_data[93] => mem.DATAB +in_data[94] => mem.DATAB +in_data[95] => mem.DATAB +in_data[96] => mem.DATAB +in_data[97] => mem.DATAB +in_data[98] => mem.DATAB +in_data[99] => mem.DATAB +in_data[100] => mem.DATAB +in_data[101] => mem.DATAB +in_valid => write.IN1 +in_startofpacket => mem.DATAB +in_endofpacket => mem.DATAB +in_empty[0] => ~NO_FANOUT~ +in_error[0] => out_error[0].DATAIN +in_error[0] => out_empty[0].DATAIN +in_channel[0] => out_channel[0].DATAIN +in_ready <= mem_used[1].DB_MAX_OUTPUT_PORT_TYPE +out_data[0] <= mem[0][0].DB_MAX_OUTPUT_PORT_TYPE +out_data[1] <= mem[0][1].DB_MAX_OUTPUT_PORT_TYPE +out_data[2] <= mem[0][2].DB_MAX_OUTPUT_PORT_TYPE +out_data[3] <= mem[0][3].DB_MAX_OUTPUT_PORT_TYPE +out_data[4] <= mem[0][4].DB_MAX_OUTPUT_PORT_TYPE +out_data[5] <= mem[0][5].DB_MAX_OUTPUT_PORT_TYPE +out_data[6] <= mem[0][6].DB_MAX_OUTPUT_PORT_TYPE +out_data[7] <= mem[0][7].DB_MAX_OUTPUT_PORT_TYPE +out_data[8] <= mem[0][8].DB_MAX_OUTPUT_PORT_TYPE +out_data[9] <= mem[0][9].DB_MAX_OUTPUT_PORT_TYPE +out_data[10] <= mem[0][10].DB_MAX_OUTPUT_PORT_TYPE +out_data[11] <= mem[0][11].DB_MAX_OUTPUT_PORT_TYPE +out_data[12] <= mem[0][12].DB_MAX_OUTPUT_PORT_TYPE +out_data[13] <= mem[0][13].DB_MAX_OUTPUT_PORT_TYPE +out_data[14] <= mem[0][14].DB_MAX_OUTPUT_PORT_TYPE +out_data[15] <= mem[0][15].DB_MAX_OUTPUT_PORT_TYPE +out_data[16] <= mem[0][16].DB_MAX_OUTPUT_PORT_TYPE +out_data[17] <= mem[0][17].DB_MAX_OUTPUT_PORT_TYPE +out_data[18] <= mem[0][18].DB_MAX_OUTPUT_PORT_TYPE +out_data[19] <= mem[0][19].DB_MAX_OUTPUT_PORT_TYPE +out_data[20] <= mem[0][20].DB_MAX_OUTPUT_PORT_TYPE +out_data[21] <= mem[0][21].DB_MAX_OUTPUT_PORT_TYPE +out_data[22] <= mem[0][22].DB_MAX_OUTPUT_PORT_TYPE +out_data[23] <= mem[0][23].DB_MAX_OUTPUT_PORT_TYPE +out_data[24] <= mem[0][24].DB_MAX_OUTPUT_PORT_TYPE +out_data[25] <= mem[0][25].DB_MAX_OUTPUT_PORT_TYPE +out_data[26] <= mem[0][26].DB_MAX_OUTPUT_PORT_TYPE +out_data[27] <= mem[0][27].DB_MAX_OUTPUT_PORT_TYPE +out_data[28] <= mem[0][28].DB_MAX_OUTPUT_PORT_TYPE +out_data[29] <= mem[0][29].DB_MAX_OUTPUT_PORT_TYPE +out_data[30] <= mem[0][30].DB_MAX_OUTPUT_PORT_TYPE +out_data[31] <= mem[0][31].DB_MAX_OUTPUT_PORT_TYPE +out_data[32] <= mem[0][32].DB_MAX_OUTPUT_PORT_TYPE +out_data[33] <= mem[0][33].DB_MAX_OUTPUT_PORT_TYPE +out_data[34] <= mem[0][34].DB_MAX_OUTPUT_PORT_TYPE +out_data[35] <= mem[0][35].DB_MAX_OUTPUT_PORT_TYPE +out_data[36] <= mem[0][36].DB_MAX_OUTPUT_PORT_TYPE +out_data[37] <= mem[0][37].DB_MAX_OUTPUT_PORT_TYPE +out_data[38] <= mem[0][38].DB_MAX_OUTPUT_PORT_TYPE +out_data[39] <= mem[0][39].DB_MAX_OUTPUT_PORT_TYPE +out_data[40] <= mem[0][40].DB_MAX_OUTPUT_PORT_TYPE +out_data[41] <= mem[0][41].DB_MAX_OUTPUT_PORT_TYPE +out_data[42] <= mem[0][42].DB_MAX_OUTPUT_PORT_TYPE +out_data[43] <= mem[0][43].DB_MAX_OUTPUT_PORT_TYPE +out_data[44] <= mem[0][44].DB_MAX_OUTPUT_PORT_TYPE +out_data[45] <= mem[0][45].DB_MAX_OUTPUT_PORT_TYPE +out_data[46] <= mem[0][46].DB_MAX_OUTPUT_PORT_TYPE +out_data[47] <= mem[0][47].DB_MAX_OUTPUT_PORT_TYPE +out_data[48] <= mem[0][48].DB_MAX_OUTPUT_PORT_TYPE +out_data[49] <= mem[0][49].DB_MAX_OUTPUT_PORT_TYPE +out_data[50] <= mem[0][50].DB_MAX_OUTPUT_PORT_TYPE +out_data[51] <= mem[0][51].DB_MAX_OUTPUT_PORT_TYPE +out_data[52] <= mem[0][52].DB_MAX_OUTPUT_PORT_TYPE +out_data[53] <= mem[0][53].DB_MAX_OUTPUT_PORT_TYPE +out_data[54] <= mem[0][54].DB_MAX_OUTPUT_PORT_TYPE +out_data[55] <= mem[0][55].DB_MAX_OUTPUT_PORT_TYPE +out_data[56] <= mem[0][56].DB_MAX_OUTPUT_PORT_TYPE +out_data[57] <= mem[0][57].DB_MAX_OUTPUT_PORT_TYPE +out_data[58] <= mem[0][58].DB_MAX_OUTPUT_PORT_TYPE +out_data[59] <= mem[0][59].DB_MAX_OUTPUT_PORT_TYPE +out_data[60] <= mem[0][60].DB_MAX_OUTPUT_PORT_TYPE +out_data[61] <= mem[0][61].DB_MAX_OUTPUT_PORT_TYPE +out_data[62] <= mem[0][62].DB_MAX_OUTPUT_PORT_TYPE +out_data[63] <= mem[0][63].DB_MAX_OUTPUT_PORT_TYPE +out_data[64] <= mem[0][64].DB_MAX_OUTPUT_PORT_TYPE +out_data[65] <= mem[0][65].DB_MAX_OUTPUT_PORT_TYPE +out_data[66] <= mem[0][66].DB_MAX_OUTPUT_PORT_TYPE +out_data[67] <= mem[0][67].DB_MAX_OUTPUT_PORT_TYPE +out_data[68] <= mem[0][68].DB_MAX_OUTPUT_PORT_TYPE +out_data[69] <= mem[0][69].DB_MAX_OUTPUT_PORT_TYPE +out_data[70] <= mem[0][70].DB_MAX_OUTPUT_PORT_TYPE +out_data[71] <= mem[0][71].DB_MAX_OUTPUT_PORT_TYPE +out_data[72] <= mem[0][72].DB_MAX_OUTPUT_PORT_TYPE +out_data[73] <= mem[0][73].DB_MAX_OUTPUT_PORT_TYPE +out_data[74] <= mem[0][74].DB_MAX_OUTPUT_PORT_TYPE +out_data[75] <= mem[0][75].DB_MAX_OUTPUT_PORT_TYPE +out_data[76] <= mem[0][76].DB_MAX_OUTPUT_PORT_TYPE +out_data[77] <= mem[0][77].DB_MAX_OUTPUT_PORT_TYPE +out_data[78] <= mem[0][78].DB_MAX_OUTPUT_PORT_TYPE +out_data[79] <= mem[0][79].DB_MAX_OUTPUT_PORT_TYPE +out_data[80] <= mem[0][80].DB_MAX_OUTPUT_PORT_TYPE +out_data[81] <= mem[0][81].DB_MAX_OUTPUT_PORT_TYPE +out_data[82] <= mem[0][82].DB_MAX_OUTPUT_PORT_TYPE +out_data[83] <= mem[0][83].DB_MAX_OUTPUT_PORT_TYPE +out_data[84] <= mem[0][84].DB_MAX_OUTPUT_PORT_TYPE +out_data[85] <= mem[0][85].DB_MAX_OUTPUT_PORT_TYPE +out_data[86] <= mem[0][86].DB_MAX_OUTPUT_PORT_TYPE +out_data[87] <= mem[0][87].DB_MAX_OUTPUT_PORT_TYPE +out_data[88] <= mem[0][88].DB_MAX_OUTPUT_PORT_TYPE +out_data[89] <= mem[0][89].DB_MAX_OUTPUT_PORT_TYPE +out_data[90] <= mem[0][90].DB_MAX_OUTPUT_PORT_TYPE +out_data[91] <= mem[0][91].DB_MAX_OUTPUT_PORT_TYPE +out_data[92] <= mem[0][92].DB_MAX_OUTPUT_PORT_TYPE +out_data[93] <= mem[0][93].DB_MAX_OUTPUT_PORT_TYPE +out_data[94] <= mem[0][94].DB_MAX_OUTPUT_PORT_TYPE +out_data[95] <= mem[0][95].DB_MAX_OUTPUT_PORT_TYPE +out_data[96] <= mem[0][96].DB_MAX_OUTPUT_PORT_TYPE +out_data[97] <= mem[0][97].DB_MAX_OUTPUT_PORT_TYPE +out_data[98] <= mem[0][98].DB_MAX_OUTPUT_PORT_TYPE +out_data[99] <= mem[0][99].DB_MAX_OUTPUT_PORT_TYPE +out_data[100] <= mem[0][100].DB_MAX_OUTPUT_PORT_TYPE +out_data[101] <= mem[0][101].DB_MAX_OUTPUT_PORT_TYPE +out_valid <= mem_used[0].DB_MAX_OUTPUT_PORT_TYPE +out_startofpacket <= mem[0][103].DB_MAX_OUTPUT_PORT_TYPE +out_endofpacket <= mem[0][102].DB_MAX_OUTPUT_PORT_TYPE +out_empty[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE +out_error[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE +out_channel[0] <= in_channel[0].DB_MAX_OUTPUT_PORT_TYPE +out_ready => internal_out_ready.IN1 +csr_address[0] => ~NO_FANOUT~ +csr_address[1] => ~NO_FANOUT~ +csr_write => ~NO_FANOUT~ +csr_read => csr_readdata[0]~reg0.ENA +csr_read => csr_readdata[31]~reg0.ENA +csr_read => csr_readdata[30]~reg0.ENA +csr_read => csr_readdata[29]~reg0.ENA +csr_read => csr_readdata[28]~reg0.ENA +csr_read => csr_readdata[27]~reg0.ENA +csr_read => csr_readdata[26]~reg0.ENA +csr_read => csr_readdata[25]~reg0.ENA +csr_read => csr_readdata[24]~reg0.ENA +csr_read => csr_readdata[23]~reg0.ENA +csr_read => csr_readdata[22]~reg0.ENA +csr_read => csr_readdata[21]~reg0.ENA +csr_read => csr_readdata[20]~reg0.ENA +csr_read => csr_readdata[19]~reg0.ENA +csr_read => csr_readdata[18]~reg0.ENA +csr_read => csr_readdata[17]~reg0.ENA +csr_read => csr_readdata[16]~reg0.ENA +csr_read => csr_readdata[15]~reg0.ENA +csr_read => csr_readdata[14]~reg0.ENA +csr_read => csr_readdata[13]~reg0.ENA +csr_read => csr_readdata[12]~reg0.ENA +csr_read => csr_readdata[11]~reg0.ENA +csr_read => csr_readdata[10]~reg0.ENA +csr_read => csr_readdata[9]~reg0.ENA +csr_read => csr_readdata[8]~reg0.ENA +csr_read => csr_readdata[7]~reg0.ENA +csr_read => csr_readdata[6]~reg0.ENA +csr_read => csr_readdata[5]~reg0.ENA +csr_read => csr_readdata[4]~reg0.ENA +csr_read => csr_readdata[3]~reg0.ENA +csr_read => csr_readdata[2]~reg0.ENA +csr_read => csr_readdata[1]~reg0.ENA +csr_writedata[0] => ~NO_FANOUT~ +csr_writedata[1] => ~NO_FANOUT~ +csr_writedata[2] => ~NO_FANOUT~ +csr_writedata[3] => ~NO_FANOUT~ +csr_writedata[4] => ~NO_FANOUT~ +csr_writedata[5] => ~NO_FANOUT~ +csr_writedata[6] => ~NO_FANOUT~ +csr_writedata[7] => ~NO_FANOUT~ +csr_writedata[8] => ~NO_FANOUT~ +csr_writedata[9] => ~NO_FANOUT~ +csr_writedata[10] => ~NO_FANOUT~ +csr_writedata[11] => ~NO_FANOUT~ +csr_writedata[12] => ~NO_FANOUT~ +csr_writedata[13] => ~NO_FANOUT~ +csr_writedata[14] => ~NO_FANOUT~ +csr_writedata[15] => ~NO_FANOUT~ +csr_writedata[16] => ~NO_FANOUT~ +csr_writedata[17] => ~NO_FANOUT~ +csr_writedata[18] => ~NO_FANOUT~ +csr_writedata[19] => ~NO_FANOUT~ +csr_writedata[20] => ~NO_FANOUT~ +csr_writedata[21] => ~NO_FANOUT~ +csr_writedata[22] => ~NO_FANOUT~ +csr_writedata[23] => ~NO_FANOUT~ +csr_writedata[24] => ~NO_FANOUT~ +csr_writedata[25] => ~NO_FANOUT~ +csr_writedata[26] => ~NO_FANOUT~ +csr_writedata[27] => ~NO_FANOUT~ +csr_writedata[28] => ~NO_FANOUT~ +csr_writedata[29] => ~NO_FANOUT~ +csr_writedata[30] => ~NO_FANOUT~ +csr_writedata[31] => ~NO_FANOUT~ +csr_readdata[0] <= csr_readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[1] <= csr_readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[2] <= csr_readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[3] <= csr_readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[4] <= csr_readdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[5] <= csr_readdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[6] <= csr_readdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[7] <= csr_readdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[8] <= csr_readdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[9] <= csr_readdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[10] <= csr_readdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[11] <= csr_readdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[12] <= csr_readdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[13] <= csr_readdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[14] <= csr_readdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[15] <= csr_readdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[16] <= csr_readdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[17] <= csr_readdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[18] <= csr_readdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[19] <= csr_readdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[20] <= csr_readdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[21] <= csr_readdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[22] <= csr_readdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[23] <= csr_readdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[24] <= csr_readdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[25] <= csr_readdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[26] <= csr_readdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[27] <= csr_readdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[28] <= csr_readdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[29] <= csr_readdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[30] <= csr_readdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[31] <= csr_readdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE +almost_full_data <= +almost_empty_data <= + + +|de0_nano_system|system:inst_cpu|altera_merlin_slave_agent:pio_sw_s1_translator_avalon_universal_slave_0_agent +clk => clk.IN1 +reset => reset.IN1 +m0_address[0] <= +m0_address[1] <= +m0_address[2] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE +m0_address[3] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE +m0_address[4] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE +m0_address[5] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE +m0_address[6] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE +m0_address[7] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE +m0_address[8] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE +m0_address[9] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE +m0_address[10] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE +m0_address[11] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE +m0_address[12] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE +m0_address[13] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE +m0_address[14] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE +m0_address[15] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE +m0_address[16] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE +m0_address[17] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE +m0_address[18] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE +m0_address[19] <= cp_data[55].DB_MAX_OUTPUT_PORT_TYPE +m0_address[20] <= cp_data[56].DB_MAX_OUTPUT_PORT_TYPE +m0_address[21] <= cp_data[57].DB_MAX_OUTPUT_PORT_TYPE +m0_address[22] <= cp_data[58].DB_MAX_OUTPUT_PORT_TYPE +m0_address[23] <= cp_data[59].DB_MAX_OUTPUT_PORT_TYPE +m0_address[24] <= cp_data[60].DB_MAX_OUTPUT_PORT_TYPE +m0_address[25] <= cp_data[61].DB_MAX_OUTPUT_PORT_TYPE +m0_burstcount[0] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE +m0_burstcount[1] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE +m0_burstcount[2] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[0] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[1] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[2] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[3] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE +m0_read <= m0_read.DB_MAX_OUTPUT_PORT_TYPE +m0_readdata[0] => rdata_fifo_src_data[0].DATAIN +m0_readdata[1] => rdata_fifo_src_data[1].DATAIN +m0_readdata[2] => rdata_fifo_src_data[2].DATAIN +m0_readdata[3] => rdata_fifo_src_data[3].DATAIN +m0_readdata[4] => rdata_fifo_src_data[4].DATAIN +m0_readdata[5] => rdata_fifo_src_data[5].DATAIN +m0_readdata[6] => rdata_fifo_src_data[6].DATAIN +m0_readdata[7] => rdata_fifo_src_data[7].DATAIN +m0_readdata[8] => rdata_fifo_src_data[8].DATAIN +m0_readdata[9] => rdata_fifo_src_data[9].DATAIN +m0_readdata[10] => rdata_fifo_src_data[10].DATAIN +m0_readdata[11] => rdata_fifo_src_data[11].DATAIN +m0_readdata[12] => rdata_fifo_src_data[12].DATAIN +m0_readdata[13] => rdata_fifo_src_data[13].DATAIN +m0_readdata[14] => rdata_fifo_src_data[14].DATAIN +m0_readdata[15] => rdata_fifo_src_data[15].DATAIN +m0_readdata[16] => rdata_fifo_src_data[16].DATAIN +m0_readdata[17] => rdata_fifo_src_data[17].DATAIN +m0_readdata[18] => rdata_fifo_src_data[18].DATAIN +m0_readdata[19] => rdata_fifo_src_data[19].DATAIN +m0_readdata[20] => rdata_fifo_src_data[20].DATAIN +m0_readdata[21] => rdata_fifo_src_data[21].DATAIN +m0_readdata[22] => rdata_fifo_src_data[22].DATAIN +m0_readdata[23] => rdata_fifo_src_data[23].DATAIN +m0_readdata[24] => rdata_fifo_src_data[24].DATAIN +m0_readdata[25] => rdata_fifo_src_data[25].DATAIN +m0_readdata[26] => rdata_fifo_src_data[26].DATAIN +m0_readdata[27] => rdata_fifo_src_data[27].DATAIN +m0_readdata[28] => rdata_fifo_src_data[28].DATAIN +m0_readdata[29] => rdata_fifo_src_data[29].DATAIN +m0_readdata[30] => rdata_fifo_src_data[30].DATAIN +m0_readdata[31] => rdata_fifo_src_data[31].DATAIN +m0_waitrequest => cp_ready.IN0 +m0_write <= m0_write.DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[0] <= cp_data[0].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[1] <= cp_data[1].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[2] <= cp_data[2].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[3] <= cp_data[3].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[4] <= cp_data[4].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[5] <= cp_data[5].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[6] <= cp_data[6].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[7] <= cp_data[7].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[8] <= cp_data[8].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[9] <= cp_data[9].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[10] <= cp_data[10].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[11] <= cp_data[11].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[12] <= cp_data[12].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[13] <= cp_data[13].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[14] <= cp_data[14].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[15] <= cp_data[15].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[16] <= cp_data[16].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[17] <= cp_data[17].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[18] <= cp_data[18].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[19] <= cp_data[19].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[20] <= cp_data[20].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[21] <= cp_data[21].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[22] <= cp_data[22].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[23] <= cp_data[23].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[24] <= cp_data[24].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[25] <= cp_data[25].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[26] <= cp_data[26].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[27] <= cp_data[27].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[28] <= cp_data[28].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[29] <= cp_data[29].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[30] <= cp_data[30].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[31] <= cp_data[31].DB_MAX_OUTPUT_PORT_TYPE +m0_readdatavalid => rdata_fifo_src_valid.DATAIN +m0_debugaccess <= cp_data[92].DB_MAX_OUTPUT_PORT_TYPE +m0_lock <= m0_lock.DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[0] <= +rf_source_data[1] <= +rf_source_data[2] <= +rf_source_data[3] <= +rf_source_data[4] <= +rf_source_data[5] <= +rf_source_data[6] <= +rf_source_data[7] <= +rf_source_data[8] <= +rf_source_data[9] <= +rf_source_data[10] <= +rf_source_data[11] <= +rf_source_data[12] <= +rf_source_data[13] <= +rf_source_data[14] <= +rf_source_data[15] <= +rf_source_data[16] <= +rf_source_data[17] <= +rf_source_data[18] <= +rf_source_data[19] <= +rf_source_data[20] <= +rf_source_data[21] <= +rf_source_data[22] <= +rf_source_data[23] <= +rf_source_data[24] <= +rf_source_data[25] <= +rf_source_data[26] <= +rf_source_data[27] <= +rf_source_data[28] <= +rf_source_data[29] <= +rf_source_data[30] <= +rf_source_data[31] <= +rf_source_data[32] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[33] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[34] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[35] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[36] <= cp_data[36].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[37] <= cp_data[37].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[38] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[39] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[40] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[41] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[42] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[43] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[44] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[45] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[46] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[47] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[48] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[49] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[50] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[51] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[52] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[53] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[54] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[55] <= cp_data[55].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[56] <= cp_data[56].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[57] <= cp_data[57].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[58] <= cp_data[58].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[59] <= cp_data[59].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[60] <= cp_data[60].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[61] <= cp_data[61].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[62] <= cp_data[62].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[63] <= cp_data[63].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[64] <= cp_data[64].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[65] <= cp_data[65].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[66] <= cp_data[66].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[67] <= cp_data[67].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[68] <= cp_data[68].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[69] <= cp_data[69].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[70] <= cp_data[70].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[71] <= cp_data[71].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[72] <= cp_data[72].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[73] <= cp_data[73].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[74] <= cp_data[74].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[75] <= cp_data[75].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[76] <= cp_data[76].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[77] <= cp_data[77].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[78] <= cp_data[78].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[79] <= cp_data[79].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[80] <= cp_data[80].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[81] <= cp_data[81].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[82] <= cp_data[82].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[83] <= cp_data[83].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[84] <= cp_data[84].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[85] <= cp_data[85].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[86] <= cp_data[86].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[87] <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[88] <= cp_data[88].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[89] <= cp_data[89].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[90] <= cp_data[90].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[91] <= cp_data[91].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[92] <= cp_data[92].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[93] <= +rf_source_data[94] <= +rf_source_data[95] <= cp_data[95].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[96] <= cp_data[96].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[97] <= cp_data[97].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[98] <= cp_data[98].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[99] <= cp_data[99].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[100] <= cp_data[100].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[101] <= nonposted_write_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +rf_source_valid <= rf_source_valid.DB_MAX_OUTPUT_PORT_TYPE +rf_source_startofpacket <= cp_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +rf_source_endofpacket <= cp_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +rf_source_ready => cp_ready.IN1 +rf_source_ready => m0_write.IN1 +rf_source_ready => m0_lock.IN1 +rf_source_ready => rf_source_valid.IN1 +rf_source_ready => m0_read.IN1 +rf_sink_data[0] => ~NO_FANOUT~ +rf_sink_data[1] => ~NO_FANOUT~ +rf_sink_data[2] => ~NO_FANOUT~ +rf_sink_data[3] => ~NO_FANOUT~ +rf_sink_data[4] => ~NO_FANOUT~ +rf_sink_data[5] => ~NO_FANOUT~ +rf_sink_data[6] => ~NO_FANOUT~ +rf_sink_data[7] => ~NO_FANOUT~ +rf_sink_data[8] => ~NO_FANOUT~ +rf_sink_data[9] => ~NO_FANOUT~ +rf_sink_data[10] => ~NO_FANOUT~ +rf_sink_data[11] => ~NO_FANOUT~ +rf_sink_data[12] => ~NO_FANOUT~ +rf_sink_data[13] => ~NO_FANOUT~ +rf_sink_data[14] => ~NO_FANOUT~ +rf_sink_data[15] => ~NO_FANOUT~ +rf_sink_data[16] => ~NO_FANOUT~ +rf_sink_data[17] => ~NO_FANOUT~ +rf_sink_data[18] => ~NO_FANOUT~ +rf_sink_data[19] => ~NO_FANOUT~ +rf_sink_data[20] => ~NO_FANOUT~ +rf_sink_data[21] => ~NO_FANOUT~ +rf_sink_data[22] => ~NO_FANOUT~ +rf_sink_data[23] => ~NO_FANOUT~ +rf_sink_data[24] => ~NO_FANOUT~ +rf_sink_data[25] => ~NO_FANOUT~ +rf_sink_data[26] => ~NO_FANOUT~ +rf_sink_data[27] => ~NO_FANOUT~ +rf_sink_data[28] => ~NO_FANOUT~ +rf_sink_data[29] => ~NO_FANOUT~ +rf_sink_data[30] => ~NO_FANOUT~ +rf_sink_data[31] => ~NO_FANOUT~ +rf_sink_data[32] => rp_data[32].DATAIN +rf_sink_data[33] => rp_data[33].DATAIN +rf_sink_data[34] => rp_data[34].DATAIN +rf_sink_data[35] => rp_data[35].DATAIN +rf_sink_data[36] => rf_sink_addr[0].IN1 +rf_sink_data[37] => rf_sink_addr[1].IN1 +rf_sink_data[38] => rf_sink_addr[2].IN1 +rf_sink_data[39] => rf_sink_addr[3].IN1 +rf_sink_data[40] => rf_sink_addr[4].IN1 +rf_sink_data[41] => rf_sink_addr[5].IN1 +rf_sink_data[42] => rf_sink_addr[6].IN1 +rf_sink_data[43] => rf_sink_addr[7].IN1 +rf_sink_data[44] => rf_sink_addr[8].IN1 +rf_sink_data[45] => rf_sink_addr[9].IN1 +rf_sink_data[46] => rf_sink_addr[10].IN1 +rf_sink_data[47] => rf_sink_addr[11].IN1 +rf_sink_data[48] => rf_sink_addr[12].IN1 +rf_sink_data[49] => rf_sink_addr[13].IN1 +rf_sink_data[50] => rf_sink_addr[14].IN1 +rf_sink_data[51] => rf_sink_addr[15].IN1 +rf_sink_data[52] => rf_sink_addr[16].IN1 +rf_sink_data[53] => rf_sink_addr[17].IN1 +rf_sink_data[54] => rf_sink_addr[18].IN1 +rf_sink_data[55] => rf_sink_addr[19].IN1 +rf_sink_data[56] => rf_sink_addr[20].IN1 +rf_sink_data[57] => rf_sink_addr[21].IN1 +rf_sink_data[58] => rf_sink_addr[22].IN1 +rf_sink_data[59] => rf_sink_addr[23].IN1 +rf_sink_data[60] => rf_sink_addr[24].IN1 +rf_sink_data[61] => rf_sink_addr[25].IN1 +rf_sink_data[62] => rf_sink_compressed.IN1 +rf_sink_data[63] => rp_data[63].DATAIN +rf_sink_data[64] => comb.OUTPUTSELECT +rf_sink_data[64] => rp_data[64].DATAIN +rf_sink_data[65] => rp_data.IN0 +rf_sink_data[66] => rp_data[66].DATAIN +rf_sink_data[67] => rp_data[67].DATAIN +rf_sink_data[68] => rf_sink_byte_cnt[0].IN1 +rf_sink_data[69] => rf_sink_byte_cnt[1].IN1 +rf_sink_data[70] => rf_sink_byte_cnt[2].IN1 +rf_sink_data[71] => rf_sink_burstwrap[0].IN1 +rf_sink_data[72] => rf_sink_burstwrap[1].IN1 +rf_sink_data[73] => rf_sink_burstwrap[2].IN1 +rf_sink_data[74] => rf_sink_burstsize[0].IN1 +rf_sink_data[75] => rf_sink_burstsize[1].IN1 +rf_sink_data[76] => rf_sink_burstsize[2].IN1 +rf_sink_data[77] => rp_data[77].DATAIN +rf_sink_data[78] => rp_data[78].DATAIN +rf_sink_data[79] => rp_data[79].DATAIN +rf_sink_data[80] => rp_data[80].DATAIN +rf_sink_data[81] => rp_data[81].DATAIN +rf_sink_data[82] => rp_data[82].DATAIN +rf_sink_data[83] => rp_data[87].DATAIN +rf_sink_data[84] => rp_data[88].DATAIN +rf_sink_data[85] => rp_data[89].DATAIN +rf_sink_data[86] => rp_data[90].DATAIN +rf_sink_data[87] => rp_data[83].DATAIN +rf_sink_data[88] => rp_data[84].DATAIN +rf_sink_data[89] => rp_data[85].DATAIN +rf_sink_data[90] => rp_data[86].DATAIN +rf_sink_data[91] => rp_data[91].DATAIN +rf_sink_data[92] => rp_data[92].DATAIN +rf_sink_data[93] => rp_data[93].DATAIN +rf_sink_data[94] => rp_data[94].DATAIN +rf_sink_data[95] => rp_data[95].DATAIN +rf_sink_data[96] => rp_data[96].DATAIN +rf_sink_data[97] => rp_data[97].DATAIN +rf_sink_data[98] => rp_data[98].DATAIN +rf_sink_data[99] => ~NO_FANOUT~ +rf_sink_data[100] => ~NO_FANOUT~ +rf_sink_data[101] => rdata_fifo_sink_ready.IN0 +rf_sink_data[101] => comb.IN0 +rf_sink_valid => rdata_fifo_sink_ready.IN1 +rf_sink_valid => comb.IN1 +rf_sink_startofpacket => comb.DATAA +rf_sink_endofpacket => rf_sink_endofpacket.IN1 +rf_sink_ready <= altera_merlin_burst_uncompressor:uncompressor.sink_ready +rdata_fifo_src_data[0] <= m0_readdata[0].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[1] <= m0_readdata[1].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[2] <= m0_readdata[2].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[3] <= m0_readdata[3].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[4] <= m0_readdata[4].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[5] <= m0_readdata[5].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[6] <= m0_readdata[6].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[7] <= m0_readdata[7].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[8] <= m0_readdata[8].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[9] <= m0_readdata[9].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[10] <= m0_readdata[10].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[11] <= m0_readdata[11].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[12] <= m0_readdata[12].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[13] <= m0_readdata[13].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[14] <= m0_readdata[14].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[15] <= m0_readdata[15].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[16] <= m0_readdata[16].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[17] <= m0_readdata[17].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[18] <= m0_readdata[18].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[19] <= m0_readdata[19].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[20] <= m0_readdata[20].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[21] <= m0_readdata[21].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[22] <= m0_readdata[22].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[23] <= m0_readdata[23].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[24] <= m0_readdata[24].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[25] <= m0_readdata[25].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[26] <= m0_readdata[26].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[27] <= m0_readdata[27].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[28] <= m0_readdata[28].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[29] <= m0_readdata[29].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[30] <= m0_readdata[30].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[31] <= m0_readdata[31].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_valid <= m0_readdatavalid.DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_ready => ~NO_FANOUT~ +rdata_fifo_sink_data[0] => rp_data[0].DATAIN +rdata_fifo_sink_data[1] => rp_data[1].DATAIN +rdata_fifo_sink_data[2] => rp_data[2].DATAIN +rdata_fifo_sink_data[3] => rp_data[3].DATAIN +rdata_fifo_sink_data[4] => rp_data[4].DATAIN +rdata_fifo_sink_data[5] => rp_data[5].DATAIN +rdata_fifo_sink_data[6] => rp_data[6].DATAIN +rdata_fifo_sink_data[7] => rp_data[7].DATAIN +rdata_fifo_sink_data[8] => rp_data[8].DATAIN +rdata_fifo_sink_data[9] => rp_data[9].DATAIN +rdata_fifo_sink_data[10] => rp_data[10].DATAIN +rdata_fifo_sink_data[11] => rp_data[11].DATAIN +rdata_fifo_sink_data[12] => rp_data[12].DATAIN +rdata_fifo_sink_data[13] => rp_data[13].DATAIN +rdata_fifo_sink_data[14] => rp_data[14].DATAIN +rdata_fifo_sink_data[15] => rp_data[15].DATAIN +rdata_fifo_sink_data[16] => rp_data[16].DATAIN +rdata_fifo_sink_data[17] => rp_data[17].DATAIN +rdata_fifo_sink_data[18] => rp_data[18].DATAIN +rdata_fifo_sink_data[19] => rp_data[19].DATAIN +rdata_fifo_sink_data[20] => rp_data[20].DATAIN +rdata_fifo_sink_data[21] => rp_data[21].DATAIN +rdata_fifo_sink_data[22] => rp_data[22].DATAIN +rdata_fifo_sink_data[23] => rp_data[23].DATAIN +rdata_fifo_sink_data[24] => rp_data[24].DATAIN +rdata_fifo_sink_data[25] => rp_data[25].DATAIN +rdata_fifo_sink_data[26] => rp_data[26].DATAIN +rdata_fifo_sink_data[27] => rp_data[27].DATAIN +rdata_fifo_sink_data[28] => rp_data[28].DATAIN +rdata_fifo_sink_data[29] => rp_data[29].DATAIN +rdata_fifo_sink_data[30] => rp_data[30].DATAIN +rdata_fifo_sink_data[31] => rp_data[31].DATAIN +rdata_fifo_sink_valid => rp_valid.IN1 +rdata_fifo_sink_valid => rdata_fifo_sink_ready.IN0 +rdata_fifo_sink_valid => comb.IN1 +rdata_fifo_sink_ready <= rdata_fifo_sink_ready.DB_MAX_OUTPUT_PORT_TYPE +cp_ready <= cp_ready.DB_MAX_OUTPUT_PORT_TYPE +cp_valid => local_lock.IN0 +cp_valid => local_write.IN0 +cp_valid => local_read.IN0 +cp_valid => local_compressed_read.IN0 +cp_data[0] => m0_writedata[0].DATAIN +cp_data[1] => m0_writedata[1].DATAIN +cp_data[2] => m0_writedata[2].DATAIN +cp_data[3] => m0_writedata[3].DATAIN +cp_data[4] => m0_writedata[4].DATAIN +cp_data[5] => m0_writedata[5].DATAIN +cp_data[6] => m0_writedata[6].DATAIN +cp_data[7] => m0_writedata[7].DATAIN +cp_data[8] => m0_writedata[8].DATAIN +cp_data[9] => m0_writedata[9].DATAIN +cp_data[10] => m0_writedata[10].DATAIN +cp_data[11] => m0_writedata[11].DATAIN +cp_data[12] => m0_writedata[12].DATAIN +cp_data[13] => m0_writedata[13].DATAIN +cp_data[14] => m0_writedata[14].DATAIN +cp_data[15] => m0_writedata[15].DATAIN +cp_data[16] => m0_writedata[16].DATAIN +cp_data[17] => m0_writedata[17].DATAIN +cp_data[18] => m0_writedata[18].DATAIN +cp_data[19] => m0_writedata[19].DATAIN +cp_data[20] => m0_writedata[20].DATAIN +cp_data[21] => m0_writedata[21].DATAIN +cp_data[22] => m0_writedata[22].DATAIN +cp_data[23] => m0_writedata[23].DATAIN +cp_data[24] => m0_writedata[24].DATAIN +cp_data[25] => m0_writedata[25].DATAIN +cp_data[26] => m0_writedata[26].DATAIN +cp_data[27] => m0_writedata[27].DATAIN +cp_data[28] => m0_writedata[28].DATAIN +cp_data[29] => m0_writedata[29].DATAIN +cp_data[30] => m0_writedata[30].DATAIN +cp_data[31] => m0_writedata[31].DATAIN +cp_data[32] => rf_source_data[32].DATAIN +cp_data[32] => m0_byteenable[0].DATAIN +cp_data[33] => rf_source_data[33].DATAIN +cp_data[33] => m0_byteenable[1].DATAIN +cp_data[34] => rf_source_data[34].DATAIN +cp_data[34] => m0_byteenable[2].DATAIN +cp_data[35] => rf_source_data[35].DATAIN +cp_data[35] => m0_byteenable[3].DATAIN +cp_data[36] => rf_source_data[36].DATAIN +cp_data[37] => rf_source_data[37].DATAIN +cp_data[38] => rf_source_data[38].DATAIN +cp_data[38] => m0_address[2].DATAIN +cp_data[39] => rf_source_data[39].DATAIN +cp_data[39] => m0_address[3].DATAIN +cp_data[40] => rf_source_data[40].DATAIN +cp_data[40] => m0_address[4].DATAIN +cp_data[41] => rf_source_data[41].DATAIN +cp_data[41] => m0_address[5].DATAIN +cp_data[42] => rf_source_data[42].DATAIN +cp_data[42] => m0_address[6].DATAIN +cp_data[43] => rf_source_data[43].DATAIN +cp_data[43] => m0_address[7].DATAIN +cp_data[44] => rf_source_data[44].DATAIN +cp_data[44] => m0_address[8].DATAIN +cp_data[45] => rf_source_data[45].DATAIN +cp_data[45] => m0_address[9].DATAIN +cp_data[46] => rf_source_data[46].DATAIN +cp_data[46] => m0_address[10].DATAIN +cp_data[47] => rf_source_data[47].DATAIN +cp_data[47] => m0_address[11].DATAIN +cp_data[48] => rf_source_data[48].DATAIN +cp_data[48] => m0_address[12].DATAIN +cp_data[49] => rf_source_data[49].DATAIN +cp_data[49] => m0_address[13].DATAIN +cp_data[50] => rf_source_data[50].DATAIN +cp_data[50] => m0_address[14].DATAIN +cp_data[51] => rf_source_data[51].DATAIN +cp_data[51] => m0_address[15].DATAIN +cp_data[52] => rf_source_data[52].DATAIN +cp_data[52] => m0_address[16].DATAIN +cp_data[53] => rf_source_data[53].DATAIN +cp_data[53] => m0_address[17].DATAIN +cp_data[54] => rf_source_data[54].DATAIN +cp_data[54] => m0_address[18].DATAIN +cp_data[55] => rf_source_data[55].DATAIN +cp_data[55] => m0_address[19].DATAIN +cp_data[56] => rf_source_data[56].DATAIN +cp_data[56] => m0_address[20].DATAIN +cp_data[57] => rf_source_data[57].DATAIN +cp_data[57] => m0_address[21].DATAIN +cp_data[58] => rf_source_data[58].DATAIN +cp_data[58] => m0_address[22].DATAIN +cp_data[59] => rf_source_data[59].DATAIN +cp_data[59] => m0_address[23].DATAIN +cp_data[60] => rf_source_data[60].DATAIN +cp_data[60] => m0_address[24].DATAIN +cp_data[61] => rf_source_data[61].DATAIN +cp_data[61] => m0_address[25].DATAIN +cp_data[62] => local_compressed_read.IN1 +cp_data[62] => rf_source_data[62].DATAIN +cp_data[63] => rf_source_data[63].DATAIN +cp_data[63] => comb.IN1 +cp_data[64] => local_write.IN1 +cp_data[64] => rf_source_data[64].DATAIN +cp_data[65] => local_read.IN1 +cp_data[65] => rf_source_data[65].DATAIN +cp_data[66] => local_lock.IN1 +cp_data[66] => rf_source_data[66].DATAIN +cp_data[67] => rf_source_data[67].DATAIN +cp_data[68] => m0_burstcount.DATAA +cp_data[68] => rf_source_data[68].DATAIN +cp_data[69] => m0_burstcount.DATAA +cp_data[69] => rf_source_data[69].DATAIN +cp_data[70] => m0_burstcount.DATAA +cp_data[70] => rf_source_data[70].DATAIN +cp_data[71] => rf_source_data[71].DATAIN +cp_data[72] => rf_source_data[72].DATAIN +cp_data[73] => rf_source_data[73].DATAIN +cp_data[74] => rf_source_data[74].DATAIN +cp_data[75] => rf_source_data[75].DATAIN +cp_data[76] => rf_source_data[76].DATAIN +cp_data[77] => rf_source_data[77].DATAIN +cp_data[78] => rf_source_data[78].DATAIN +cp_data[79] => rf_source_data[79].DATAIN +cp_data[80] => rf_source_data[80].DATAIN +cp_data[81] => rf_source_data[81].DATAIN +cp_data[82] => rf_source_data[82].DATAIN +cp_data[83] => rf_source_data[83].DATAIN +cp_data[84] => rf_source_data[84].DATAIN +cp_data[85] => rf_source_data[85].DATAIN +cp_data[86] => rf_source_data[86].DATAIN +cp_data[87] => rf_source_data[87].DATAIN +cp_data[88] => rf_source_data[88].DATAIN +cp_data[89] => rf_source_data[89].DATAIN +cp_data[90] => rf_source_data[90].DATAIN +cp_data[91] => rf_source_data[91].DATAIN +cp_data[92] => rf_source_data[92].DATAIN +cp_data[92] => m0_debugaccess.DATAIN +cp_data[93] => ~NO_FANOUT~ +cp_data[94] => ~NO_FANOUT~ +cp_data[95] => rf_source_data[95].DATAIN +cp_data[96] => rf_source_data[96].DATAIN +cp_data[97] => rf_source_data[97].DATAIN +cp_data[98] => rf_source_data[98].DATAIN +cp_data[99] => rf_source_data[99].DATAIN +cp_data[100] => rf_source_data[100].DATAIN +cp_channel[0] => ~NO_FANOUT~ +cp_channel[1] => ~NO_FANOUT~ +cp_channel[2] => ~NO_FANOUT~ +cp_channel[3] => ~NO_FANOUT~ +cp_channel[4] => ~NO_FANOUT~ +cp_channel[5] => ~NO_FANOUT~ +cp_channel[6] => ~NO_FANOUT~ +cp_channel[7] => ~NO_FANOUT~ +cp_channel[8] => ~NO_FANOUT~ +cp_channel[9] => ~NO_FANOUT~ +cp_channel[10] => ~NO_FANOUT~ +cp_startofpacket => rf_source_startofpacket.DATAIN +cp_endofpacket => nonposted_write_endofpacket.IN1 +cp_endofpacket => rf_source_endofpacket.DATAIN +rp_ready => rp_ready.IN1 +rp_valid <= rp_valid.DB_MAX_OUTPUT_PORT_TYPE +rp_data[0] <= rdata_fifo_sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +rp_data[1] <= rdata_fifo_sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +rp_data[2] <= rdata_fifo_sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +rp_data[3] <= rdata_fifo_sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +rp_data[4] <= rdata_fifo_sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +rp_data[5] <= rdata_fifo_sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +rp_data[6] <= rdata_fifo_sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +rp_data[7] <= rdata_fifo_sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +rp_data[8] <= rdata_fifo_sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +rp_data[9] <= rdata_fifo_sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +rp_data[10] <= rdata_fifo_sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +rp_data[11] <= rdata_fifo_sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +rp_data[12] <= rdata_fifo_sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +rp_data[13] <= rdata_fifo_sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +rp_data[14] <= rdata_fifo_sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +rp_data[15] <= rdata_fifo_sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +rp_data[16] <= rdata_fifo_sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +rp_data[17] <= rdata_fifo_sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +rp_data[18] <= rdata_fifo_sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +rp_data[19] <= rdata_fifo_sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +rp_data[20] <= rdata_fifo_sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +rp_data[21] <= rdata_fifo_sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +rp_data[22] <= rdata_fifo_sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +rp_data[23] <= rdata_fifo_sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +rp_data[24] <= rdata_fifo_sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +rp_data[25] <= rdata_fifo_sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +rp_data[26] <= rdata_fifo_sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +rp_data[27] <= rdata_fifo_sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +rp_data[28] <= rdata_fifo_sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +rp_data[29] <= rdata_fifo_sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +rp_data[30] <= rdata_fifo_sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +rp_data[31] <= rdata_fifo_sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +rp_data[32] <= rf_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +rp_data[33] <= rf_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +rp_data[34] <= rf_sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +rp_data[35] <= rf_sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +rp_data[36] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[37] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[38] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[39] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[40] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[41] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[42] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[43] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[44] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[45] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[46] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[47] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[48] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[49] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[50] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[51] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[52] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[53] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[54] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[55] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[56] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[57] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[58] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[59] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[60] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[61] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[62] <= altera_merlin_burst_uncompressor:uncompressor.source_is_compressed +rp_data[63] <= rf_sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +rp_data[64] <= rf_sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +rp_data[65] <= rp_data.DB_MAX_OUTPUT_PORT_TYPE +rp_data[66] <= rf_sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +rp_data[67] <= rf_sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +rp_data[68] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt +rp_data[69] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt +rp_data[70] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt +rp_data[71] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap +rp_data[72] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap +rp_data[73] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap +rp_data[74] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize +rp_data[75] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize +rp_data[76] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize +rp_data[77] <= rf_sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +rp_data[78] <= rf_sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +rp_data[79] <= rf_sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +rp_data[80] <= rf_sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +rp_data[81] <= rf_sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +rp_data[82] <= rf_sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +rp_data[83] <= rf_sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +rp_data[84] <= rf_sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +rp_data[85] <= rf_sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +rp_data[86] <= rf_sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +rp_data[87] <= rf_sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +rp_data[88] <= rf_sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +rp_data[89] <= rf_sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +rp_data[90] <= rf_sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +rp_data[91] <= rf_sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +rp_data[92] <= rf_sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +rp_data[93] <= rf_sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +rp_data[94] <= rf_sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +rp_data[95] <= rf_sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +rp_data[96] <= rf_sink_data[96].DB_MAX_OUTPUT_PORT_TYPE +rp_data[97] <= rf_sink_data[97].DB_MAX_OUTPUT_PORT_TYPE +rp_data[98] <= rf_sink_data[98].DB_MAX_OUTPUT_PORT_TYPE +rp_data[99] <= +rp_data[100] <= +rp_startofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_startofpacket +rp_endofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_endofpacket + + +|de0_nano_system|system:inst_cpu|altera_merlin_slave_agent:pio_sw_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor +clk => burst_uncompress_address_offset[0].CLK +clk => burst_uncompress_address_offset[1].CLK +clk => burst_uncompress_address_offset[2].CLK +clk => burst_uncompress_address_offset[3].CLK +clk => burst_uncompress_address_offset[4].CLK +clk => burst_uncompress_address_offset[5].CLK +clk => burst_uncompress_address_offset[6].CLK +clk => burst_uncompress_address_offset[7].CLK +clk => burst_uncompress_address_offset[8].CLK +clk => burst_uncompress_address_offset[9].CLK +clk => burst_uncompress_address_offset[10].CLK +clk => burst_uncompress_address_offset[11].CLK +clk => burst_uncompress_address_offset[12].CLK +clk => burst_uncompress_address_offset[13].CLK +clk => burst_uncompress_address_offset[14].CLK +clk => burst_uncompress_address_offset[15].CLK +clk => burst_uncompress_address_offset[16].CLK +clk => burst_uncompress_address_offset[17].CLK +clk => burst_uncompress_address_offset[18].CLK +clk => burst_uncompress_address_offset[19].CLK +clk => burst_uncompress_address_offset[20].CLK +clk => burst_uncompress_address_offset[21].CLK +clk => burst_uncompress_address_offset[22].CLK +clk => burst_uncompress_address_offset[23].CLK +clk => burst_uncompress_address_offset[24].CLK +clk => burst_uncompress_address_offset[25].CLK +clk => burst_uncompress_address_base[0].CLK +clk => burst_uncompress_address_base[1].CLK +clk => burst_uncompress_address_base[2].CLK +clk => burst_uncompress_address_base[3].CLK +clk => burst_uncompress_address_base[4].CLK +clk => burst_uncompress_address_base[5].CLK +clk => burst_uncompress_address_base[6].CLK +clk => burst_uncompress_address_base[7].CLK +clk => burst_uncompress_address_base[8].CLK +clk => burst_uncompress_address_base[9].CLK +clk => burst_uncompress_address_base[10].CLK +clk => burst_uncompress_address_base[11].CLK +clk => burst_uncompress_address_base[12].CLK +clk => burst_uncompress_address_base[13].CLK +clk => burst_uncompress_address_base[14].CLK +clk => burst_uncompress_address_base[15].CLK +clk => burst_uncompress_address_base[16].CLK +clk => burst_uncompress_address_base[17].CLK +clk => burst_uncompress_address_base[18].CLK +clk => burst_uncompress_address_base[19].CLK +clk => burst_uncompress_address_base[20].CLK +clk => burst_uncompress_address_base[21].CLK +clk => burst_uncompress_address_base[22].CLK +clk => burst_uncompress_address_base[23].CLK +clk => burst_uncompress_address_base[24].CLK +clk => burst_uncompress_address_base[25].CLK +clk => burst_uncompress_byte_counter[0].CLK +clk => burst_uncompress_byte_counter[1].CLK +clk => burst_uncompress_byte_counter[2].CLK +clk => burst_uncompress_busy.CLK +reset => burst_uncompress_address_offset[0].ACLR +reset => burst_uncompress_address_offset[1].ACLR +reset => burst_uncompress_address_offset[2].ACLR +reset => burst_uncompress_address_offset[3].ACLR +reset => burst_uncompress_address_offset[4].ACLR +reset => burst_uncompress_address_offset[5].ACLR +reset => burst_uncompress_address_offset[6].ACLR +reset => burst_uncompress_address_offset[7].ACLR +reset => burst_uncompress_address_offset[8].ACLR +reset => burst_uncompress_address_offset[9].ACLR +reset => burst_uncompress_address_offset[10].ACLR +reset => burst_uncompress_address_offset[11].ACLR +reset => burst_uncompress_address_offset[12].ACLR +reset => burst_uncompress_address_offset[13].ACLR +reset => burst_uncompress_address_offset[14].ACLR +reset => burst_uncompress_address_offset[15].ACLR +reset => burst_uncompress_address_offset[16].ACLR +reset => burst_uncompress_address_offset[17].ACLR +reset => burst_uncompress_address_offset[18].ACLR +reset => burst_uncompress_address_offset[19].ACLR +reset => burst_uncompress_address_offset[20].ACLR +reset => burst_uncompress_address_offset[21].ACLR +reset => burst_uncompress_address_offset[22].ACLR +reset => burst_uncompress_address_offset[23].ACLR +reset => burst_uncompress_address_offset[24].ACLR +reset => burst_uncompress_address_offset[25].ACLR +reset => burst_uncompress_address_base[0].ACLR +reset => burst_uncompress_address_base[1].ACLR +reset => burst_uncompress_address_base[2].ACLR +reset => burst_uncompress_address_base[3].ACLR +reset => burst_uncompress_address_base[4].ACLR +reset => burst_uncompress_address_base[5].ACLR +reset => burst_uncompress_address_base[6].ACLR +reset => burst_uncompress_address_base[7].ACLR +reset => burst_uncompress_address_base[8].ACLR +reset => burst_uncompress_address_base[9].ACLR +reset => burst_uncompress_address_base[10].ACLR +reset => burst_uncompress_address_base[11].ACLR +reset => burst_uncompress_address_base[12].ACLR +reset => burst_uncompress_address_base[13].ACLR +reset => burst_uncompress_address_base[14].ACLR +reset => burst_uncompress_address_base[15].ACLR +reset => burst_uncompress_address_base[16].ACLR +reset => burst_uncompress_address_base[17].ACLR +reset => burst_uncompress_address_base[18].ACLR +reset => burst_uncompress_address_base[19].ACLR +reset => burst_uncompress_address_base[20].ACLR +reset => burst_uncompress_address_base[21].ACLR +reset => burst_uncompress_address_base[22].ACLR +reset => burst_uncompress_address_base[23].ACLR +reset => burst_uncompress_address_base[24].ACLR +reset => burst_uncompress_address_base[25].ACLR +reset => burst_uncompress_byte_counter[0].ACLR +reset => burst_uncompress_byte_counter[1].ACLR +reset => burst_uncompress_byte_counter[2].ACLR +reset => burst_uncompress_busy.ACLR +sink_startofpacket => source_startofpacket.IN1 +sink_endofpacket => source_endofpacket.IN1 +sink_valid => first_packet_beat.IN1 +sink_valid => last_packet_beat.IN1 +sink_valid => last_packet_beat.IN1 +sink_valid => always0.IN1 +sink_valid => sink_ready.IN0 +sink_valid => source_valid.DATAIN +sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE +sink_addr[0] => burst_uncompress_address_base.IN0 +sink_addr[0] => comb.DATAB +sink_addr[0] => source_addr.DATAB +sink_addr[1] => burst_uncompress_address_base.IN0 +sink_addr[1] => comb.DATAB +sink_addr[1] => source_addr.DATAB +sink_addr[2] => burst_uncompress_address_base.IN0 +sink_addr[2] => comb.DATAB +sink_addr[2] => source_addr.DATAB +sink_addr[3] => burst_uncompress_address_base.IN0 +sink_addr[3] => comb.DATAB +sink_addr[3] => source_addr.DATAB +sink_addr[4] => burst_uncompress_address_base.IN0 +sink_addr[4] => comb.DATAB +sink_addr[4] => source_addr.DATAB +sink_addr[5] => burst_uncompress_address_base.IN0 +sink_addr[5] => comb.DATAB +sink_addr[5] => source_addr.DATAB +sink_addr[6] => burst_uncompress_address_base.IN0 +sink_addr[6] => comb.DATAB +sink_addr[6] => source_addr.DATAB +sink_addr[7] => burst_uncompress_address_base.IN0 +sink_addr[7] => comb.DATAB +sink_addr[7] => source_addr.DATAB +sink_addr[8] => burst_uncompress_address_base.IN0 +sink_addr[8] => comb.DATAB +sink_addr[8] => source_addr.DATAB +sink_addr[9] => burst_uncompress_address_base.IN0 +sink_addr[9] => comb.DATAB +sink_addr[9] => source_addr.DATAB +sink_addr[10] => burst_uncompress_address_base.IN0 +sink_addr[10] => comb.DATAB +sink_addr[10] => source_addr.DATAB +sink_addr[11] => burst_uncompress_address_base.IN0 +sink_addr[11] => comb.DATAB +sink_addr[11] => source_addr.DATAB +sink_addr[12] => burst_uncompress_address_base.IN0 +sink_addr[12] => comb.DATAB +sink_addr[12] => source_addr.DATAB +sink_addr[13] => burst_uncompress_address_base.IN0 +sink_addr[13] => comb.DATAB +sink_addr[13] => source_addr.DATAB +sink_addr[14] => burst_uncompress_address_base.IN0 +sink_addr[14] => comb.DATAB +sink_addr[14] => source_addr.DATAB +sink_addr[15] => burst_uncompress_address_base.IN0 +sink_addr[15] => comb.DATAB +sink_addr[15] => source_addr.DATAB +sink_addr[16] => burst_uncompress_address_base.IN0 +sink_addr[16] => comb.DATAB +sink_addr[16] => source_addr.DATAB +sink_addr[17] => burst_uncompress_address_base.IN0 +sink_addr[17] => comb.DATAB +sink_addr[17] => source_addr.DATAB +sink_addr[18] => burst_uncompress_address_base.IN0 +sink_addr[18] => comb.DATAB +sink_addr[18] => source_addr.DATAB +sink_addr[19] => burst_uncompress_address_base.IN0 +sink_addr[19] => comb.DATAB +sink_addr[19] => source_addr.DATAB +sink_addr[20] => burst_uncompress_address_base.IN0 +sink_addr[20] => comb.DATAB +sink_addr[20] => source_addr.DATAB +sink_addr[21] => burst_uncompress_address_base.IN0 +sink_addr[21] => comb.DATAB +sink_addr[21] => source_addr.DATAB +sink_addr[22] => burst_uncompress_address_base.IN0 +sink_addr[22] => comb.DATAB +sink_addr[22] => source_addr.DATAB +sink_addr[23] => burst_uncompress_address_base.IN0 +sink_addr[23] => comb.DATAB +sink_addr[23] => source_addr.DATAB +sink_addr[24] => burst_uncompress_address_base.IN0 +sink_addr[24] => comb.DATAB +sink_addr[24] => source_addr.DATAB +sink_addr[25] => burst_uncompress_address_base.IN0 +sink_addr[25] => comb.DATAB +sink_addr[25] => source_addr.DATAB +sink_burstwrap[0] => p1_burst_uncompress_address_offset[0].IN1 +sink_burstwrap[0] => source_burstwrap[0].DATAIN +sink_burstwrap[0] => burst_uncompress_address_base.IN1 +sink_burstwrap[1] => p1_burst_uncompress_address_offset[1].IN1 +sink_burstwrap[1] => source_burstwrap[1].DATAIN +sink_burstwrap[1] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[2].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[25].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[24].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[23].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[22].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[21].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[20].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[19].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[18].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[17].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[16].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[15].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[14].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[13].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[12].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[11].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[10].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[9].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[8].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[7].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[6].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[5].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[4].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[3].IN1 +sink_burstwrap[2] => source_burstwrap[2].DATAIN +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_byte_cnt[0] => source_byte_cnt.DATAB +sink_byte_cnt[0] => Add1.IN6 +sink_byte_cnt[0] => Equal1.IN2 +sink_byte_cnt[1] => source_byte_cnt.DATAB +sink_byte_cnt[1] => Add1.IN5 +sink_byte_cnt[1] => Equal1.IN1 +sink_byte_cnt[2] => source_byte_cnt.DATAB +sink_byte_cnt[2] => Add1.IN4 +sink_byte_cnt[2] => Equal1.IN0 +sink_is_compressed => last_packet_beat.IN1 +sink_burstsize[0] => Decoder0.IN2 +sink_burstsize[0] => source_burstsize[0].DATAIN +sink_burstsize[1] => Decoder0.IN1 +sink_burstsize[1] => source_burstsize[1].DATAIN +sink_burstsize[2] => Decoder0.IN0 +sink_burstsize[2] => source_burstsize[2].DATAIN +source_startofpacket <= source_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +source_endofpacket <= source_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +source_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE +source_ready => always1.IN1 +source_ready => sink_ready.IN1 +source_addr[0] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[1] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[2] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[3] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[4] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[5] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[6] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[7] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[8] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[9] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[10] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[11] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[12] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[13] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[14] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[15] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[16] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[17] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[18] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[19] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[20] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[21] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[22] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[23] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[24] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[25] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_burstwrap[0] <= sink_burstwrap[0].DB_MAX_OUTPUT_PORT_TYPE +source_burstwrap[1] <= sink_burstwrap[1].DB_MAX_OUTPUT_PORT_TYPE +source_burstwrap[2] <= sink_burstwrap[2].DB_MAX_OUTPUT_PORT_TYPE +source_byte_cnt[0] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE +source_byte_cnt[1] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE +source_byte_cnt[2] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE +source_is_compressed <= +source_burstsize[0] <= sink_burstsize[0].DB_MAX_OUTPUT_PORT_TYPE +source_burstsize[1] <= sink_burstsize[1].DB_MAX_OUTPUT_PORT_TYPE +source_burstsize[2] <= sink_burstsize[2].DB_MAX_OUTPUT_PORT_TYPE + + +|de0_nano_system|system:inst_cpu|altera_avalon_sc_fifo:pio_sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo +clk => csr_readdata[0]~reg0.CLK +clk => csr_readdata[1]~reg0.CLK +clk => csr_readdata[2]~reg0.CLK +clk => csr_readdata[3]~reg0.CLK +clk => csr_readdata[4]~reg0.CLK +clk => csr_readdata[5]~reg0.CLK +clk => csr_readdata[6]~reg0.CLK +clk => csr_readdata[7]~reg0.CLK +clk => csr_readdata[8]~reg0.CLK +clk => csr_readdata[9]~reg0.CLK +clk => csr_readdata[10]~reg0.CLK +clk => csr_readdata[11]~reg0.CLK +clk => csr_readdata[12]~reg0.CLK +clk => csr_readdata[13]~reg0.CLK +clk => csr_readdata[14]~reg0.CLK +clk => csr_readdata[15]~reg0.CLK +clk => csr_readdata[16]~reg0.CLK +clk => csr_readdata[17]~reg0.CLK +clk => csr_readdata[18]~reg0.CLK +clk => csr_readdata[19]~reg0.CLK +clk => csr_readdata[20]~reg0.CLK +clk => csr_readdata[21]~reg0.CLK +clk => csr_readdata[22]~reg0.CLK +clk => csr_readdata[23]~reg0.CLK +clk => csr_readdata[24]~reg0.CLK +clk => csr_readdata[25]~reg0.CLK +clk => csr_readdata[26]~reg0.CLK +clk => csr_readdata[27]~reg0.CLK +clk => csr_readdata[28]~reg0.CLK +clk => csr_readdata[29]~reg0.CLK +clk => csr_readdata[30]~reg0.CLK +clk => csr_readdata[31]~reg0.CLK +clk => mem_used[1].CLK +clk => mem_used[0].CLK +clk => mem[1][0].CLK +clk => mem[1][1].CLK +clk => mem[1][2].CLK +clk => mem[1][3].CLK +clk => mem[1][4].CLK +clk => mem[1][5].CLK +clk => mem[1][6].CLK +clk => mem[1][7].CLK +clk => mem[1][8].CLK +clk => mem[1][9].CLK +clk => mem[1][10].CLK +clk => mem[1][11].CLK +clk => mem[1][12].CLK +clk => mem[1][13].CLK +clk => mem[1][14].CLK +clk => mem[1][15].CLK +clk => mem[1][16].CLK +clk => mem[1][17].CLK +clk => mem[1][18].CLK +clk => mem[1][19].CLK +clk => mem[1][20].CLK +clk => mem[1][21].CLK +clk => mem[1][22].CLK +clk => mem[1][23].CLK +clk => mem[1][24].CLK +clk => mem[1][25].CLK +clk => mem[1][26].CLK +clk => mem[1][27].CLK +clk => mem[1][28].CLK +clk => mem[1][29].CLK +clk => mem[1][30].CLK +clk => mem[1][31].CLK +clk => mem[1][32].CLK +clk => mem[1][33].CLK +clk => mem[1][34].CLK +clk => mem[1][35].CLK +clk => mem[1][36].CLK +clk => mem[1][37].CLK +clk => mem[1][38].CLK +clk => mem[1][39].CLK +clk => mem[1][40].CLK +clk => mem[1][41].CLK +clk => mem[1][42].CLK +clk => mem[1][43].CLK +clk => mem[1][44].CLK +clk => mem[1][45].CLK +clk => mem[1][46].CLK +clk => mem[1][47].CLK +clk => mem[1][48].CLK +clk => mem[1][49].CLK +clk => mem[1][50].CLK +clk => mem[1][51].CLK +clk => mem[1][52].CLK +clk => mem[1][53].CLK +clk => mem[1][54].CLK +clk => mem[1][55].CLK +clk => mem[1][56].CLK +clk => mem[1][57].CLK +clk => mem[1][58].CLK +clk => mem[1][59].CLK +clk => mem[1][60].CLK +clk => mem[1][61].CLK +clk => mem[1][62].CLK +clk => mem[1][63].CLK +clk => mem[1][64].CLK +clk => mem[1][65].CLK +clk => mem[1][66].CLK +clk => mem[1][67].CLK +clk => mem[1][68].CLK +clk => mem[1][69].CLK +clk => mem[1][70].CLK +clk => mem[1][71].CLK +clk => mem[1][72].CLK +clk => mem[1][73].CLK +clk => mem[1][74].CLK +clk => mem[1][75].CLK +clk => mem[1][76].CLK +clk => mem[1][77].CLK +clk => mem[1][78].CLK +clk => mem[1][79].CLK +clk => mem[1][80].CLK +clk => mem[1][81].CLK +clk => mem[1][82].CLK +clk => mem[1][83].CLK +clk => mem[1][84].CLK +clk => mem[1][85].CLK +clk => mem[1][86].CLK +clk => mem[1][87].CLK +clk => mem[1][88].CLK +clk => mem[1][89].CLK +clk => mem[1][90].CLK +clk => mem[1][91].CLK +clk => mem[1][92].CLK +clk => mem[1][93].CLK +clk => mem[1][94].CLK +clk => mem[1][95].CLK +clk => mem[1][96].CLK +clk => mem[1][97].CLK +clk => mem[1][98].CLK +clk => mem[1][99].CLK +clk => mem[1][100].CLK +clk => mem[1][101].CLK +clk => mem[1][102].CLK +clk => mem[1][103].CLK +clk => mem[0][0].CLK +clk => mem[0][1].CLK +clk => mem[0][2].CLK +clk => mem[0][3].CLK +clk => mem[0][4].CLK +clk => mem[0][5].CLK +clk => mem[0][6].CLK +clk => mem[0][7].CLK +clk => mem[0][8].CLK +clk => mem[0][9].CLK +clk => mem[0][10].CLK +clk => mem[0][11].CLK +clk => mem[0][12].CLK +clk => mem[0][13].CLK +clk => mem[0][14].CLK +clk => mem[0][15].CLK +clk => mem[0][16].CLK +clk => mem[0][17].CLK +clk => mem[0][18].CLK +clk => mem[0][19].CLK +clk => mem[0][20].CLK +clk => mem[0][21].CLK +clk => mem[0][22].CLK +clk => mem[0][23].CLK +clk => mem[0][24].CLK +clk => mem[0][25].CLK +clk => mem[0][26].CLK +clk => mem[0][27].CLK +clk => mem[0][28].CLK +clk => mem[0][29].CLK +clk => mem[0][30].CLK +clk => mem[0][31].CLK +clk => mem[0][32].CLK +clk => mem[0][33].CLK +clk => mem[0][34].CLK +clk => mem[0][35].CLK +clk => mem[0][36].CLK +clk => mem[0][37].CLK +clk => mem[0][38].CLK +clk => mem[0][39].CLK +clk => mem[0][40].CLK +clk => mem[0][41].CLK +clk => mem[0][42].CLK +clk => mem[0][43].CLK +clk => mem[0][44].CLK +clk => mem[0][45].CLK +clk => mem[0][46].CLK +clk => mem[0][47].CLK +clk => mem[0][48].CLK +clk => mem[0][49].CLK +clk => mem[0][50].CLK +clk => mem[0][51].CLK +clk => mem[0][52].CLK +clk => mem[0][53].CLK +clk => mem[0][54].CLK +clk => mem[0][55].CLK +clk => mem[0][56].CLK +clk => mem[0][57].CLK +clk => mem[0][58].CLK +clk => mem[0][59].CLK +clk => mem[0][60].CLK +clk => mem[0][61].CLK +clk => mem[0][62].CLK +clk => mem[0][63].CLK +clk => mem[0][64].CLK +clk => mem[0][65].CLK +clk => mem[0][66].CLK +clk => mem[0][67].CLK +clk => mem[0][68].CLK +clk => mem[0][69].CLK +clk => mem[0][70].CLK +clk => mem[0][71].CLK +clk => mem[0][72].CLK +clk => mem[0][73].CLK +clk => mem[0][74].CLK +clk => mem[0][75].CLK +clk => mem[0][76].CLK +clk => mem[0][77].CLK +clk => mem[0][78].CLK +clk => mem[0][79].CLK +clk => mem[0][80].CLK +clk => mem[0][81].CLK +clk => mem[0][82].CLK +clk => mem[0][83].CLK +clk => mem[0][84].CLK +clk => mem[0][85].CLK +clk => mem[0][86].CLK +clk => mem[0][87].CLK +clk => mem[0][88].CLK +clk => mem[0][89].CLK +clk => mem[0][90].CLK +clk => mem[0][91].CLK +clk => mem[0][92].CLK +clk => mem[0][93].CLK +clk => mem[0][94].CLK +clk => mem[0][95].CLK +clk => mem[0][96].CLK +clk => mem[0][97].CLK +clk => mem[0][98].CLK +clk => mem[0][99].CLK +clk => mem[0][100].CLK +clk => mem[0][101].CLK +clk => mem[0][102].CLK +clk => mem[0][103].CLK +reset => csr_readdata[0]~reg0.ACLR +reset => csr_readdata[1]~reg0.ACLR +reset => csr_readdata[2]~reg0.ACLR +reset => csr_readdata[3]~reg0.ACLR +reset => csr_readdata[4]~reg0.ACLR +reset => csr_readdata[5]~reg0.ACLR +reset => csr_readdata[6]~reg0.ACLR +reset => csr_readdata[7]~reg0.ACLR +reset => csr_readdata[8]~reg0.ACLR +reset => csr_readdata[9]~reg0.ACLR +reset => csr_readdata[10]~reg0.ACLR +reset => csr_readdata[11]~reg0.ACLR +reset => csr_readdata[12]~reg0.ACLR +reset => csr_readdata[13]~reg0.ACLR +reset => csr_readdata[14]~reg0.ACLR +reset => csr_readdata[15]~reg0.ACLR +reset => csr_readdata[16]~reg0.ACLR +reset => csr_readdata[17]~reg0.ACLR +reset => csr_readdata[18]~reg0.ACLR +reset => csr_readdata[19]~reg0.ACLR +reset => csr_readdata[20]~reg0.ACLR +reset => csr_readdata[21]~reg0.ACLR +reset => csr_readdata[22]~reg0.ACLR +reset => csr_readdata[23]~reg0.ACLR +reset => csr_readdata[24]~reg0.ACLR +reset => csr_readdata[25]~reg0.ACLR +reset => csr_readdata[26]~reg0.ACLR +reset => csr_readdata[27]~reg0.ACLR +reset => csr_readdata[28]~reg0.ACLR +reset => csr_readdata[29]~reg0.ACLR +reset => csr_readdata[30]~reg0.ACLR +reset => csr_readdata[31]~reg0.ACLR +reset => mem_used[1].ACLR +reset => mem_used[0].ACLR +reset => mem[1][0].ACLR +reset => mem[1][1].ACLR +reset => mem[1][2].ACLR +reset => mem[1][3].ACLR +reset => mem[1][4].ACLR +reset => mem[1][5].ACLR +reset => mem[1][6].ACLR +reset => mem[1][7].ACLR +reset => mem[1][8].ACLR +reset => mem[1][9].ACLR +reset => mem[1][10].ACLR +reset => mem[1][11].ACLR +reset => mem[1][12].ACLR +reset => mem[1][13].ACLR +reset => mem[1][14].ACLR +reset => mem[1][15].ACLR +reset => mem[1][16].ACLR +reset => mem[1][17].ACLR +reset => mem[1][18].ACLR +reset => mem[1][19].ACLR +reset => mem[1][20].ACLR +reset => mem[1][21].ACLR +reset => mem[1][22].ACLR +reset => mem[1][23].ACLR +reset => mem[1][24].ACLR +reset => mem[1][25].ACLR +reset => mem[1][26].ACLR +reset => mem[1][27].ACLR +reset => mem[1][28].ACLR +reset => mem[1][29].ACLR +reset => mem[1][30].ACLR +reset => mem[1][31].ACLR +reset => mem[1][32].ACLR +reset => mem[1][33].ACLR +reset => mem[1][34].ACLR +reset => mem[1][35].ACLR +reset => mem[1][36].ACLR +reset => mem[1][37].ACLR +reset => mem[1][38].ACLR +reset => mem[1][39].ACLR +reset => mem[1][40].ACLR +reset => mem[1][41].ACLR +reset => mem[1][42].ACLR +reset => mem[1][43].ACLR +reset => mem[1][44].ACLR +reset => mem[1][45].ACLR +reset => mem[1][46].ACLR +reset => mem[1][47].ACLR +reset => mem[1][48].ACLR +reset => mem[1][49].ACLR +reset => mem[1][50].ACLR +reset => mem[1][51].ACLR +reset => mem[1][52].ACLR +reset => mem[1][53].ACLR +reset => mem[1][54].ACLR +reset => mem[1][55].ACLR +reset => mem[1][56].ACLR +reset => mem[1][57].ACLR +reset => mem[1][58].ACLR +reset => mem[1][59].ACLR +reset => mem[1][60].ACLR +reset => mem[1][61].ACLR +reset => mem[1][62].ACLR +reset => mem[1][63].ACLR +reset => mem[1][64].ACLR +reset => mem[1][65].ACLR +reset => mem[1][66].ACLR +reset => mem[1][67].ACLR +reset => mem[1][68].ACLR +reset => mem[1][69].ACLR +reset => mem[1][70].ACLR +reset => mem[1][71].ACLR +reset => mem[1][72].ACLR +reset => mem[1][73].ACLR +reset => mem[1][74].ACLR +reset => mem[1][75].ACLR +reset => mem[1][76].ACLR +reset => mem[1][77].ACLR +reset => mem[1][78].ACLR +reset => mem[1][79].ACLR +reset => mem[1][80].ACLR +reset => mem[1][81].ACLR +reset => mem[1][82].ACLR +reset => mem[1][83].ACLR +reset => mem[1][84].ACLR +reset => mem[1][85].ACLR +reset => mem[1][86].ACLR +reset => mem[1][87].ACLR +reset => mem[1][88].ACLR +reset => mem[1][89].ACLR +reset => mem[1][90].ACLR +reset => mem[1][91].ACLR +reset => mem[1][92].ACLR +reset => mem[1][93].ACLR +reset => mem[1][94].ACLR +reset => mem[1][95].ACLR +reset => mem[1][96].ACLR +reset => mem[1][97].ACLR +reset => mem[1][98].ACLR +reset => mem[1][99].ACLR +reset => mem[1][100].ACLR +reset => mem[1][101].ACLR +reset => mem[1][102].ACLR +reset => mem[1][103].ACLR +reset => mem[0][0].ACLR +reset => mem[0][1].ACLR +reset => mem[0][2].ACLR +reset => mem[0][3].ACLR +reset => mem[0][4].ACLR +reset => mem[0][5].ACLR +reset => mem[0][6].ACLR +reset => mem[0][7].ACLR +reset => mem[0][8].ACLR +reset => mem[0][9].ACLR +reset => mem[0][10].ACLR +reset => mem[0][11].ACLR +reset => mem[0][12].ACLR +reset => mem[0][13].ACLR +reset => mem[0][14].ACLR +reset => mem[0][15].ACLR +reset => mem[0][16].ACLR +reset => mem[0][17].ACLR +reset => mem[0][18].ACLR +reset => mem[0][19].ACLR +reset => mem[0][20].ACLR +reset => mem[0][21].ACLR +reset => mem[0][22].ACLR +reset => mem[0][23].ACLR +reset => mem[0][24].ACLR +reset => mem[0][25].ACLR +reset => mem[0][26].ACLR +reset => mem[0][27].ACLR +reset => mem[0][28].ACLR +reset => mem[0][29].ACLR +reset => mem[0][30].ACLR +reset => mem[0][31].ACLR +reset => mem[0][32].ACLR +reset => mem[0][33].ACLR +reset => mem[0][34].ACLR +reset => mem[0][35].ACLR +reset => mem[0][36].ACLR +reset => mem[0][37].ACLR +reset => mem[0][38].ACLR +reset => mem[0][39].ACLR +reset => mem[0][40].ACLR +reset => mem[0][41].ACLR +reset => mem[0][42].ACLR +reset => mem[0][43].ACLR +reset => mem[0][44].ACLR +reset => mem[0][45].ACLR +reset => mem[0][46].ACLR +reset => mem[0][47].ACLR +reset => mem[0][48].ACLR +reset => mem[0][49].ACLR +reset => mem[0][50].ACLR +reset => mem[0][51].ACLR +reset => mem[0][52].ACLR +reset => mem[0][53].ACLR +reset => mem[0][54].ACLR +reset => mem[0][55].ACLR +reset => mem[0][56].ACLR +reset => mem[0][57].ACLR +reset => mem[0][58].ACLR +reset => mem[0][59].ACLR +reset => mem[0][60].ACLR +reset => mem[0][61].ACLR +reset => mem[0][62].ACLR +reset => mem[0][63].ACLR +reset => mem[0][64].ACLR +reset => mem[0][65].ACLR +reset => mem[0][66].ACLR +reset => mem[0][67].ACLR +reset => mem[0][68].ACLR +reset => mem[0][69].ACLR +reset => mem[0][70].ACLR +reset => mem[0][71].ACLR +reset => mem[0][72].ACLR +reset => mem[0][73].ACLR +reset => mem[0][74].ACLR +reset => mem[0][75].ACLR +reset => mem[0][76].ACLR +reset => mem[0][77].ACLR +reset => mem[0][78].ACLR +reset => mem[0][79].ACLR +reset => mem[0][80].ACLR +reset => mem[0][81].ACLR +reset => mem[0][82].ACLR +reset => mem[0][83].ACLR +reset => mem[0][84].ACLR +reset => mem[0][85].ACLR +reset => mem[0][86].ACLR +reset => mem[0][87].ACLR +reset => mem[0][88].ACLR +reset => mem[0][89].ACLR +reset => mem[0][90].ACLR +reset => mem[0][91].ACLR +reset => mem[0][92].ACLR +reset => mem[0][93].ACLR +reset => mem[0][94].ACLR +reset => mem[0][95].ACLR +reset => mem[0][96].ACLR +reset => mem[0][97].ACLR +reset => mem[0][98].ACLR +reset => mem[0][99].ACLR +reset => mem[0][100].ACLR +reset => mem[0][101].ACLR +reset => mem[0][102].ACLR +reset => mem[0][103].ACLR +in_data[0] => mem.DATAB +in_data[1] => mem.DATAB +in_data[2] => mem.DATAB +in_data[3] => mem.DATAB +in_data[4] => mem.DATAB +in_data[5] => mem.DATAB +in_data[6] => mem.DATAB +in_data[7] => mem.DATAB +in_data[8] => mem.DATAB +in_data[9] => mem.DATAB +in_data[10] => mem.DATAB +in_data[11] => mem.DATAB +in_data[12] => mem.DATAB +in_data[13] => mem.DATAB +in_data[14] => mem.DATAB +in_data[15] => mem.DATAB +in_data[16] => mem.DATAB +in_data[17] => mem.DATAB +in_data[18] => mem.DATAB +in_data[19] => mem.DATAB +in_data[20] => mem.DATAB +in_data[21] => mem.DATAB +in_data[22] => mem.DATAB +in_data[23] => mem.DATAB +in_data[24] => mem.DATAB +in_data[25] => mem.DATAB +in_data[26] => mem.DATAB +in_data[27] => mem.DATAB +in_data[28] => mem.DATAB +in_data[29] => mem.DATAB +in_data[30] => mem.DATAB +in_data[31] => mem.DATAB +in_data[32] => mem.DATAB +in_data[33] => mem.DATAB +in_data[34] => mem.DATAB +in_data[35] => mem.DATAB +in_data[36] => mem.DATAB +in_data[37] => mem.DATAB +in_data[38] => mem.DATAB +in_data[39] => mem.DATAB +in_data[40] => mem.DATAB +in_data[41] => mem.DATAB +in_data[42] => mem.DATAB +in_data[43] => mem.DATAB +in_data[44] => mem.DATAB +in_data[45] => mem.DATAB +in_data[46] => mem.DATAB +in_data[47] => mem.DATAB +in_data[48] => mem.DATAB +in_data[49] => mem.DATAB +in_data[50] => mem.DATAB +in_data[51] => mem.DATAB +in_data[52] => mem.DATAB +in_data[53] => mem.DATAB +in_data[54] => mem.DATAB +in_data[55] => mem.DATAB +in_data[56] => mem.DATAB +in_data[57] => mem.DATAB +in_data[58] => mem.DATAB +in_data[59] => mem.DATAB +in_data[60] => mem.DATAB +in_data[61] => mem.DATAB +in_data[62] => mem.DATAB +in_data[63] => mem.DATAB +in_data[64] => mem.DATAB +in_data[65] => mem.DATAB +in_data[66] => mem.DATAB +in_data[67] => mem.DATAB +in_data[68] => mem.DATAB +in_data[69] => mem.DATAB +in_data[70] => mem.DATAB +in_data[71] => mem.DATAB +in_data[72] => mem.DATAB +in_data[73] => mem.DATAB +in_data[74] => mem.DATAB +in_data[75] => mem.DATAB +in_data[76] => mem.DATAB +in_data[77] => mem.DATAB +in_data[78] => mem.DATAB +in_data[79] => mem.DATAB +in_data[80] => mem.DATAB +in_data[81] => mem.DATAB +in_data[82] => mem.DATAB +in_data[83] => mem.DATAB +in_data[84] => mem.DATAB +in_data[85] => mem.DATAB +in_data[86] => mem.DATAB +in_data[87] => mem.DATAB +in_data[88] => mem.DATAB +in_data[89] => mem.DATAB +in_data[90] => mem.DATAB +in_data[91] => mem.DATAB +in_data[92] => mem.DATAB +in_data[93] => mem.DATAB +in_data[94] => mem.DATAB +in_data[95] => mem.DATAB +in_data[96] => mem.DATAB +in_data[97] => mem.DATAB +in_data[98] => mem.DATAB +in_data[99] => mem.DATAB +in_data[100] => mem.DATAB +in_data[101] => mem.DATAB +in_valid => write.IN1 +in_startofpacket => mem.DATAB +in_endofpacket => mem.DATAB +in_empty[0] => ~NO_FANOUT~ +in_error[0] => out_error[0].DATAIN +in_error[0] => out_empty[0].DATAIN +in_channel[0] => out_channel[0].DATAIN +in_ready <= mem_used[1].DB_MAX_OUTPUT_PORT_TYPE +out_data[0] <= mem[0][0].DB_MAX_OUTPUT_PORT_TYPE +out_data[1] <= mem[0][1].DB_MAX_OUTPUT_PORT_TYPE +out_data[2] <= mem[0][2].DB_MAX_OUTPUT_PORT_TYPE +out_data[3] <= mem[0][3].DB_MAX_OUTPUT_PORT_TYPE +out_data[4] <= mem[0][4].DB_MAX_OUTPUT_PORT_TYPE +out_data[5] <= mem[0][5].DB_MAX_OUTPUT_PORT_TYPE +out_data[6] <= mem[0][6].DB_MAX_OUTPUT_PORT_TYPE +out_data[7] <= mem[0][7].DB_MAX_OUTPUT_PORT_TYPE +out_data[8] <= mem[0][8].DB_MAX_OUTPUT_PORT_TYPE +out_data[9] <= mem[0][9].DB_MAX_OUTPUT_PORT_TYPE +out_data[10] <= mem[0][10].DB_MAX_OUTPUT_PORT_TYPE +out_data[11] <= mem[0][11].DB_MAX_OUTPUT_PORT_TYPE +out_data[12] <= mem[0][12].DB_MAX_OUTPUT_PORT_TYPE +out_data[13] <= mem[0][13].DB_MAX_OUTPUT_PORT_TYPE +out_data[14] <= mem[0][14].DB_MAX_OUTPUT_PORT_TYPE +out_data[15] <= mem[0][15].DB_MAX_OUTPUT_PORT_TYPE +out_data[16] <= mem[0][16].DB_MAX_OUTPUT_PORT_TYPE +out_data[17] <= mem[0][17].DB_MAX_OUTPUT_PORT_TYPE +out_data[18] <= mem[0][18].DB_MAX_OUTPUT_PORT_TYPE +out_data[19] <= mem[0][19].DB_MAX_OUTPUT_PORT_TYPE +out_data[20] <= mem[0][20].DB_MAX_OUTPUT_PORT_TYPE +out_data[21] <= mem[0][21].DB_MAX_OUTPUT_PORT_TYPE +out_data[22] <= mem[0][22].DB_MAX_OUTPUT_PORT_TYPE +out_data[23] <= mem[0][23].DB_MAX_OUTPUT_PORT_TYPE +out_data[24] <= mem[0][24].DB_MAX_OUTPUT_PORT_TYPE +out_data[25] <= mem[0][25].DB_MAX_OUTPUT_PORT_TYPE +out_data[26] <= mem[0][26].DB_MAX_OUTPUT_PORT_TYPE +out_data[27] <= mem[0][27].DB_MAX_OUTPUT_PORT_TYPE +out_data[28] <= mem[0][28].DB_MAX_OUTPUT_PORT_TYPE +out_data[29] <= mem[0][29].DB_MAX_OUTPUT_PORT_TYPE +out_data[30] <= mem[0][30].DB_MAX_OUTPUT_PORT_TYPE +out_data[31] <= mem[0][31].DB_MAX_OUTPUT_PORT_TYPE +out_data[32] <= mem[0][32].DB_MAX_OUTPUT_PORT_TYPE +out_data[33] <= mem[0][33].DB_MAX_OUTPUT_PORT_TYPE +out_data[34] <= mem[0][34].DB_MAX_OUTPUT_PORT_TYPE +out_data[35] <= mem[0][35].DB_MAX_OUTPUT_PORT_TYPE +out_data[36] <= mem[0][36].DB_MAX_OUTPUT_PORT_TYPE +out_data[37] <= mem[0][37].DB_MAX_OUTPUT_PORT_TYPE +out_data[38] <= mem[0][38].DB_MAX_OUTPUT_PORT_TYPE +out_data[39] <= mem[0][39].DB_MAX_OUTPUT_PORT_TYPE +out_data[40] <= mem[0][40].DB_MAX_OUTPUT_PORT_TYPE +out_data[41] <= mem[0][41].DB_MAX_OUTPUT_PORT_TYPE +out_data[42] <= mem[0][42].DB_MAX_OUTPUT_PORT_TYPE +out_data[43] <= mem[0][43].DB_MAX_OUTPUT_PORT_TYPE +out_data[44] <= mem[0][44].DB_MAX_OUTPUT_PORT_TYPE +out_data[45] <= mem[0][45].DB_MAX_OUTPUT_PORT_TYPE +out_data[46] <= mem[0][46].DB_MAX_OUTPUT_PORT_TYPE +out_data[47] <= mem[0][47].DB_MAX_OUTPUT_PORT_TYPE +out_data[48] <= mem[0][48].DB_MAX_OUTPUT_PORT_TYPE +out_data[49] <= mem[0][49].DB_MAX_OUTPUT_PORT_TYPE +out_data[50] <= mem[0][50].DB_MAX_OUTPUT_PORT_TYPE +out_data[51] <= mem[0][51].DB_MAX_OUTPUT_PORT_TYPE +out_data[52] <= mem[0][52].DB_MAX_OUTPUT_PORT_TYPE +out_data[53] <= mem[0][53].DB_MAX_OUTPUT_PORT_TYPE +out_data[54] <= mem[0][54].DB_MAX_OUTPUT_PORT_TYPE +out_data[55] <= mem[0][55].DB_MAX_OUTPUT_PORT_TYPE +out_data[56] <= mem[0][56].DB_MAX_OUTPUT_PORT_TYPE +out_data[57] <= mem[0][57].DB_MAX_OUTPUT_PORT_TYPE +out_data[58] <= mem[0][58].DB_MAX_OUTPUT_PORT_TYPE +out_data[59] <= mem[0][59].DB_MAX_OUTPUT_PORT_TYPE +out_data[60] <= mem[0][60].DB_MAX_OUTPUT_PORT_TYPE +out_data[61] <= mem[0][61].DB_MAX_OUTPUT_PORT_TYPE +out_data[62] <= mem[0][62].DB_MAX_OUTPUT_PORT_TYPE +out_data[63] <= mem[0][63].DB_MAX_OUTPUT_PORT_TYPE +out_data[64] <= mem[0][64].DB_MAX_OUTPUT_PORT_TYPE +out_data[65] <= mem[0][65].DB_MAX_OUTPUT_PORT_TYPE +out_data[66] <= mem[0][66].DB_MAX_OUTPUT_PORT_TYPE +out_data[67] <= mem[0][67].DB_MAX_OUTPUT_PORT_TYPE +out_data[68] <= mem[0][68].DB_MAX_OUTPUT_PORT_TYPE +out_data[69] <= mem[0][69].DB_MAX_OUTPUT_PORT_TYPE +out_data[70] <= mem[0][70].DB_MAX_OUTPUT_PORT_TYPE +out_data[71] <= mem[0][71].DB_MAX_OUTPUT_PORT_TYPE +out_data[72] <= mem[0][72].DB_MAX_OUTPUT_PORT_TYPE +out_data[73] <= mem[0][73].DB_MAX_OUTPUT_PORT_TYPE +out_data[74] <= mem[0][74].DB_MAX_OUTPUT_PORT_TYPE +out_data[75] <= mem[0][75].DB_MAX_OUTPUT_PORT_TYPE +out_data[76] <= mem[0][76].DB_MAX_OUTPUT_PORT_TYPE +out_data[77] <= mem[0][77].DB_MAX_OUTPUT_PORT_TYPE +out_data[78] <= mem[0][78].DB_MAX_OUTPUT_PORT_TYPE +out_data[79] <= mem[0][79].DB_MAX_OUTPUT_PORT_TYPE +out_data[80] <= mem[0][80].DB_MAX_OUTPUT_PORT_TYPE +out_data[81] <= mem[0][81].DB_MAX_OUTPUT_PORT_TYPE +out_data[82] <= mem[0][82].DB_MAX_OUTPUT_PORT_TYPE +out_data[83] <= mem[0][83].DB_MAX_OUTPUT_PORT_TYPE +out_data[84] <= mem[0][84].DB_MAX_OUTPUT_PORT_TYPE +out_data[85] <= mem[0][85].DB_MAX_OUTPUT_PORT_TYPE +out_data[86] <= mem[0][86].DB_MAX_OUTPUT_PORT_TYPE +out_data[87] <= mem[0][87].DB_MAX_OUTPUT_PORT_TYPE +out_data[88] <= mem[0][88].DB_MAX_OUTPUT_PORT_TYPE +out_data[89] <= mem[0][89].DB_MAX_OUTPUT_PORT_TYPE +out_data[90] <= mem[0][90].DB_MAX_OUTPUT_PORT_TYPE +out_data[91] <= mem[0][91].DB_MAX_OUTPUT_PORT_TYPE +out_data[92] <= mem[0][92].DB_MAX_OUTPUT_PORT_TYPE +out_data[93] <= mem[0][93].DB_MAX_OUTPUT_PORT_TYPE +out_data[94] <= mem[0][94].DB_MAX_OUTPUT_PORT_TYPE +out_data[95] <= mem[0][95].DB_MAX_OUTPUT_PORT_TYPE +out_data[96] <= mem[0][96].DB_MAX_OUTPUT_PORT_TYPE +out_data[97] <= mem[0][97].DB_MAX_OUTPUT_PORT_TYPE +out_data[98] <= mem[0][98].DB_MAX_OUTPUT_PORT_TYPE +out_data[99] <= mem[0][99].DB_MAX_OUTPUT_PORT_TYPE +out_data[100] <= mem[0][100].DB_MAX_OUTPUT_PORT_TYPE +out_data[101] <= mem[0][101].DB_MAX_OUTPUT_PORT_TYPE +out_valid <= mem_used[0].DB_MAX_OUTPUT_PORT_TYPE +out_startofpacket <= mem[0][103].DB_MAX_OUTPUT_PORT_TYPE +out_endofpacket <= mem[0][102].DB_MAX_OUTPUT_PORT_TYPE +out_empty[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE +out_error[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE +out_channel[0] <= in_channel[0].DB_MAX_OUTPUT_PORT_TYPE +out_ready => internal_out_ready.IN1 +csr_address[0] => ~NO_FANOUT~ +csr_address[1] => ~NO_FANOUT~ +csr_write => ~NO_FANOUT~ +csr_read => csr_readdata[0]~reg0.ENA +csr_read => csr_readdata[31]~reg0.ENA +csr_read => csr_readdata[30]~reg0.ENA +csr_read => csr_readdata[29]~reg0.ENA +csr_read => csr_readdata[28]~reg0.ENA +csr_read => csr_readdata[27]~reg0.ENA +csr_read => csr_readdata[26]~reg0.ENA +csr_read => csr_readdata[25]~reg0.ENA +csr_read => csr_readdata[24]~reg0.ENA +csr_read => csr_readdata[23]~reg0.ENA +csr_read => csr_readdata[22]~reg0.ENA +csr_read => csr_readdata[21]~reg0.ENA +csr_read => csr_readdata[20]~reg0.ENA +csr_read => csr_readdata[19]~reg0.ENA +csr_read => csr_readdata[18]~reg0.ENA +csr_read => csr_readdata[17]~reg0.ENA +csr_read => csr_readdata[16]~reg0.ENA +csr_read => csr_readdata[15]~reg0.ENA +csr_read => csr_readdata[14]~reg0.ENA +csr_read => csr_readdata[13]~reg0.ENA +csr_read => csr_readdata[12]~reg0.ENA +csr_read => csr_readdata[11]~reg0.ENA +csr_read => csr_readdata[10]~reg0.ENA +csr_read => csr_readdata[9]~reg0.ENA +csr_read => csr_readdata[8]~reg0.ENA +csr_read => csr_readdata[7]~reg0.ENA +csr_read => csr_readdata[6]~reg0.ENA +csr_read => csr_readdata[5]~reg0.ENA +csr_read => csr_readdata[4]~reg0.ENA +csr_read => csr_readdata[3]~reg0.ENA +csr_read => csr_readdata[2]~reg0.ENA +csr_read => csr_readdata[1]~reg0.ENA +csr_writedata[0] => ~NO_FANOUT~ +csr_writedata[1] => ~NO_FANOUT~ +csr_writedata[2] => ~NO_FANOUT~ +csr_writedata[3] => ~NO_FANOUT~ +csr_writedata[4] => ~NO_FANOUT~ +csr_writedata[5] => ~NO_FANOUT~ +csr_writedata[6] => ~NO_FANOUT~ +csr_writedata[7] => ~NO_FANOUT~ +csr_writedata[8] => ~NO_FANOUT~ +csr_writedata[9] => ~NO_FANOUT~ +csr_writedata[10] => ~NO_FANOUT~ +csr_writedata[11] => ~NO_FANOUT~ +csr_writedata[12] => ~NO_FANOUT~ +csr_writedata[13] => ~NO_FANOUT~ +csr_writedata[14] => ~NO_FANOUT~ +csr_writedata[15] => ~NO_FANOUT~ +csr_writedata[16] => ~NO_FANOUT~ +csr_writedata[17] => ~NO_FANOUT~ +csr_writedata[18] => ~NO_FANOUT~ +csr_writedata[19] => ~NO_FANOUT~ +csr_writedata[20] => ~NO_FANOUT~ +csr_writedata[21] => ~NO_FANOUT~ +csr_writedata[22] => ~NO_FANOUT~ +csr_writedata[23] => ~NO_FANOUT~ +csr_writedata[24] => ~NO_FANOUT~ +csr_writedata[25] => ~NO_FANOUT~ +csr_writedata[26] => ~NO_FANOUT~ +csr_writedata[27] => ~NO_FANOUT~ +csr_writedata[28] => ~NO_FANOUT~ +csr_writedata[29] => ~NO_FANOUT~ +csr_writedata[30] => ~NO_FANOUT~ +csr_writedata[31] => ~NO_FANOUT~ +csr_readdata[0] <= csr_readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[1] <= csr_readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[2] <= csr_readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[3] <= csr_readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[4] <= csr_readdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[5] <= csr_readdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[6] <= csr_readdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[7] <= csr_readdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[8] <= csr_readdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[9] <= csr_readdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[10] <= csr_readdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[11] <= csr_readdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[12] <= csr_readdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[13] <= csr_readdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[14] <= csr_readdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[15] <= csr_readdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[16] <= csr_readdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[17] <= csr_readdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[18] <= csr_readdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[19] <= csr_readdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[20] <= csr_readdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[21] <= csr_readdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[22] <= csr_readdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[23] <= csr_readdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[24] <= csr_readdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[25] <= csr_readdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[26] <= csr_readdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[27] <= csr_readdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[28] <= csr_readdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[29] <= csr_readdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[30] <= csr_readdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[31] <= csr_readdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE +almost_full_data <= +almost_empty_data <= + + +|de0_nano_system|system:inst_cpu|altera_merlin_slave_agent:jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent +clk => clk.IN1 +reset => reset.IN1 +m0_address[0] <= +m0_address[1] <= +m0_address[2] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE +m0_address[3] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE +m0_address[4] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE +m0_address[5] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE +m0_address[6] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE +m0_address[7] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE +m0_address[8] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE +m0_address[9] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE +m0_address[10] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE +m0_address[11] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE +m0_address[12] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE +m0_address[13] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE +m0_address[14] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE +m0_address[15] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE +m0_address[16] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE +m0_address[17] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE +m0_address[18] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE +m0_address[19] <= cp_data[55].DB_MAX_OUTPUT_PORT_TYPE +m0_address[20] <= cp_data[56].DB_MAX_OUTPUT_PORT_TYPE +m0_address[21] <= cp_data[57].DB_MAX_OUTPUT_PORT_TYPE +m0_address[22] <= cp_data[58].DB_MAX_OUTPUT_PORT_TYPE +m0_address[23] <= cp_data[59].DB_MAX_OUTPUT_PORT_TYPE +m0_address[24] <= cp_data[60].DB_MAX_OUTPUT_PORT_TYPE +m0_address[25] <= cp_data[61].DB_MAX_OUTPUT_PORT_TYPE +m0_burstcount[0] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE +m0_burstcount[1] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE +m0_burstcount[2] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[0] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[1] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[2] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[3] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE +m0_read <= m0_read.DB_MAX_OUTPUT_PORT_TYPE +m0_readdata[0] => rdata_fifo_src_data[0].DATAIN +m0_readdata[1] => rdata_fifo_src_data[1].DATAIN +m0_readdata[2] => rdata_fifo_src_data[2].DATAIN +m0_readdata[3] => rdata_fifo_src_data[3].DATAIN +m0_readdata[4] => rdata_fifo_src_data[4].DATAIN +m0_readdata[5] => rdata_fifo_src_data[5].DATAIN +m0_readdata[6] => rdata_fifo_src_data[6].DATAIN +m0_readdata[7] => rdata_fifo_src_data[7].DATAIN +m0_readdata[8] => rdata_fifo_src_data[8].DATAIN +m0_readdata[9] => rdata_fifo_src_data[9].DATAIN +m0_readdata[10] => rdata_fifo_src_data[10].DATAIN +m0_readdata[11] => rdata_fifo_src_data[11].DATAIN +m0_readdata[12] => rdata_fifo_src_data[12].DATAIN +m0_readdata[13] => rdata_fifo_src_data[13].DATAIN +m0_readdata[14] => rdata_fifo_src_data[14].DATAIN +m0_readdata[15] => rdata_fifo_src_data[15].DATAIN +m0_readdata[16] => rdata_fifo_src_data[16].DATAIN +m0_readdata[17] => rdata_fifo_src_data[17].DATAIN +m0_readdata[18] => rdata_fifo_src_data[18].DATAIN +m0_readdata[19] => rdata_fifo_src_data[19].DATAIN +m0_readdata[20] => rdata_fifo_src_data[20].DATAIN +m0_readdata[21] => rdata_fifo_src_data[21].DATAIN +m0_readdata[22] => rdata_fifo_src_data[22].DATAIN +m0_readdata[23] => rdata_fifo_src_data[23].DATAIN +m0_readdata[24] => rdata_fifo_src_data[24].DATAIN +m0_readdata[25] => rdata_fifo_src_data[25].DATAIN +m0_readdata[26] => rdata_fifo_src_data[26].DATAIN +m0_readdata[27] => rdata_fifo_src_data[27].DATAIN +m0_readdata[28] => rdata_fifo_src_data[28].DATAIN +m0_readdata[29] => rdata_fifo_src_data[29].DATAIN +m0_readdata[30] => rdata_fifo_src_data[30].DATAIN +m0_readdata[31] => rdata_fifo_src_data[31].DATAIN +m0_waitrequest => cp_ready.IN0 +m0_write <= m0_write.DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[0] <= cp_data[0].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[1] <= cp_data[1].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[2] <= cp_data[2].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[3] <= cp_data[3].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[4] <= cp_data[4].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[5] <= cp_data[5].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[6] <= cp_data[6].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[7] <= cp_data[7].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[8] <= cp_data[8].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[9] <= cp_data[9].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[10] <= cp_data[10].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[11] <= cp_data[11].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[12] <= cp_data[12].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[13] <= cp_data[13].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[14] <= cp_data[14].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[15] <= cp_data[15].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[16] <= cp_data[16].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[17] <= cp_data[17].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[18] <= cp_data[18].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[19] <= cp_data[19].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[20] <= cp_data[20].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[21] <= cp_data[21].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[22] <= cp_data[22].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[23] <= cp_data[23].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[24] <= cp_data[24].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[25] <= cp_data[25].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[26] <= cp_data[26].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[27] <= cp_data[27].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[28] <= cp_data[28].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[29] <= cp_data[29].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[30] <= cp_data[30].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[31] <= cp_data[31].DB_MAX_OUTPUT_PORT_TYPE +m0_readdatavalid => rdata_fifo_src_valid.DATAIN +m0_debugaccess <= cp_data[92].DB_MAX_OUTPUT_PORT_TYPE +m0_lock <= m0_lock.DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[0] <= +rf_source_data[1] <= +rf_source_data[2] <= +rf_source_data[3] <= +rf_source_data[4] <= +rf_source_data[5] <= +rf_source_data[6] <= +rf_source_data[7] <= +rf_source_data[8] <= +rf_source_data[9] <= +rf_source_data[10] <= +rf_source_data[11] <= +rf_source_data[12] <= +rf_source_data[13] <= +rf_source_data[14] <= +rf_source_data[15] <= +rf_source_data[16] <= +rf_source_data[17] <= +rf_source_data[18] <= +rf_source_data[19] <= +rf_source_data[20] <= +rf_source_data[21] <= +rf_source_data[22] <= +rf_source_data[23] <= +rf_source_data[24] <= +rf_source_data[25] <= +rf_source_data[26] <= +rf_source_data[27] <= +rf_source_data[28] <= +rf_source_data[29] <= +rf_source_data[30] <= +rf_source_data[31] <= +rf_source_data[32] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[33] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[34] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[35] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[36] <= cp_data[36].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[37] <= cp_data[37].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[38] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[39] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[40] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[41] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[42] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[43] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[44] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[45] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[46] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[47] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[48] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[49] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[50] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[51] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[52] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[53] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[54] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[55] <= cp_data[55].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[56] <= cp_data[56].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[57] <= cp_data[57].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[58] <= cp_data[58].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[59] <= cp_data[59].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[60] <= cp_data[60].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[61] <= cp_data[61].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[62] <= cp_data[62].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[63] <= cp_data[63].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[64] <= cp_data[64].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[65] <= cp_data[65].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[66] <= cp_data[66].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[67] <= cp_data[67].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[68] <= cp_data[68].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[69] <= cp_data[69].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[70] <= cp_data[70].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[71] <= cp_data[71].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[72] <= cp_data[72].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[73] <= cp_data[73].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[74] <= cp_data[74].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[75] <= cp_data[75].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[76] <= cp_data[76].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[77] <= cp_data[77].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[78] <= cp_data[78].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[79] <= cp_data[79].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[80] <= cp_data[80].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[81] <= cp_data[81].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[82] <= cp_data[82].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[83] <= cp_data[83].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[84] <= cp_data[84].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[85] <= cp_data[85].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[86] <= cp_data[86].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[87] <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[88] <= cp_data[88].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[89] <= cp_data[89].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[90] <= cp_data[90].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[91] <= cp_data[91].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[92] <= cp_data[92].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[93] <= +rf_source_data[94] <= +rf_source_data[95] <= cp_data[95].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[96] <= cp_data[96].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[97] <= cp_data[97].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[98] <= cp_data[98].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[99] <= cp_data[99].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[100] <= cp_data[100].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[101] <= nonposted_write_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +rf_source_valid <= rf_source_valid.DB_MAX_OUTPUT_PORT_TYPE +rf_source_startofpacket <= cp_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +rf_source_endofpacket <= cp_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +rf_source_ready => cp_ready.IN1 +rf_source_ready => m0_write.IN1 +rf_source_ready => m0_lock.IN1 +rf_source_ready => rf_source_valid.IN1 +rf_source_ready => m0_read.IN1 +rf_sink_data[0] => ~NO_FANOUT~ +rf_sink_data[1] => ~NO_FANOUT~ +rf_sink_data[2] => ~NO_FANOUT~ +rf_sink_data[3] => ~NO_FANOUT~ +rf_sink_data[4] => ~NO_FANOUT~ +rf_sink_data[5] => ~NO_FANOUT~ +rf_sink_data[6] => ~NO_FANOUT~ +rf_sink_data[7] => ~NO_FANOUT~ +rf_sink_data[8] => ~NO_FANOUT~ +rf_sink_data[9] => ~NO_FANOUT~ +rf_sink_data[10] => ~NO_FANOUT~ +rf_sink_data[11] => ~NO_FANOUT~ +rf_sink_data[12] => ~NO_FANOUT~ +rf_sink_data[13] => ~NO_FANOUT~ +rf_sink_data[14] => ~NO_FANOUT~ +rf_sink_data[15] => ~NO_FANOUT~ +rf_sink_data[16] => ~NO_FANOUT~ +rf_sink_data[17] => ~NO_FANOUT~ +rf_sink_data[18] => ~NO_FANOUT~ +rf_sink_data[19] => ~NO_FANOUT~ +rf_sink_data[20] => ~NO_FANOUT~ +rf_sink_data[21] => ~NO_FANOUT~ +rf_sink_data[22] => ~NO_FANOUT~ +rf_sink_data[23] => ~NO_FANOUT~ +rf_sink_data[24] => ~NO_FANOUT~ +rf_sink_data[25] => ~NO_FANOUT~ +rf_sink_data[26] => ~NO_FANOUT~ +rf_sink_data[27] => ~NO_FANOUT~ +rf_sink_data[28] => ~NO_FANOUT~ +rf_sink_data[29] => ~NO_FANOUT~ +rf_sink_data[30] => ~NO_FANOUT~ +rf_sink_data[31] => ~NO_FANOUT~ +rf_sink_data[32] => rp_data[32].DATAIN +rf_sink_data[33] => rp_data[33].DATAIN +rf_sink_data[34] => rp_data[34].DATAIN +rf_sink_data[35] => rp_data[35].DATAIN +rf_sink_data[36] => rf_sink_addr[0].IN1 +rf_sink_data[37] => rf_sink_addr[1].IN1 +rf_sink_data[38] => rf_sink_addr[2].IN1 +rf_sink_data[39] => rf_sink_addr[3].IN1 +rf_sink_data[40] => rf_sink_addr[4].IN1 +rf_sink_data[41] => rf_sink_addr[5].IN1 +rf_sink_data[42] => rf_sink_addr[6].IN1 +rf_sink_data[43] => rf_sink_addr[7].IN1 +rf_sink_data[44] => rf_sink_addr[8].IN1 +rf_sink_data[45] => rf_sink_addr[9].IN1 +rf_sink_data[46] => rf_sink_addr[10].IN1 +rf_sink_data[47] => rf_sink_addr[11].IN1 +rf_sink_data[48] => rf_sink_addr[12].IN1 +rf_sink_data[49] => rf_sink_addr[13].IN1 +rf_sink_data[50] => rf_sink_addr[14].IN1 +rf_sink_data[51] => rf_sink_addr[15].IN1 +rf_sink_data[52] => rf_sink_addr[16].IN1 +rf_sink_data[53] => rf_sink_addr[17].IN1 +rf_sink_data[54] => rf_sink_addr[18].IN1 +rf_sink_data[55] => rf_sink_addr[19].IN1 +rf_sink_data[56] => rf_sink_addr[20].IN1 +rf_sink_data[57] => rf_sink_addr[21].IN1 +rf_sink_data[58] => rf_sink_addr[22].IN1 +rf_sink_data[59] => rf_sink_addr[23].IN1 +rf_sink_data[60] => rf_sink_addr[24].IN1 +rf_sink_data[61] => rf_sink_addr[25].IN1 +rf_sink_data[62] => rf_sink_compressed.IN1 +rf_sink_data[63] => rp_data[63].DATAIN +rf_sink_data[64] => comb.OUTPUTSELECT +rf_sink_data[64] => rp_data[64].DATAIN +rf_sink_data[65] => rp_data.IN0 +rf_sink_data[66] => rp_data[66].DATAIN +rf_sink_data[67] => rp_data[67].DATAIN +rf_sink_data[68] => rf_sink_byte_cnt[0].IN1 +rf_sink_data[69] => rf_sink_byte_cnt[1].IN1 +rf_sink_data[70] => rf_sink_byte_cnt[2].IN1 +rf_sink_data[71] => rf_sink_burstwrap[0].IN1 +rf_sink_data[72] => rf_sink_burstwrap[1].IN1 +rf_sink_data[73] => rf_sink_burstwrap[2].IN1 +rf_sink_data[74] => rf_sink_burstsize[0].IN1 +rf_sink_data[75] => rf_sink_burstsize[1].IN1 +rf_sink_data[76] => rf_sink_burstsize[2].IN1 +rf_sink_data[77] => rp_data[77].DATAIN +rf_sink_data[78] => rp_data[78].DATAIN +rf_sink_data[79] => rp_data[79].DATAIN +rf_sink_data[80] => rp_data[80].DATAIN +rf_sink_data[81] => rp_data[81].DATAIN +rf_sink_data[82] => rp_data[82].DATAIN +rf_sink_data[83] => rp_data[87].DATAIN +rf_sink_data[84] => rp_data[88].DATAIN +rf_sink_data[85] => rp_data[89].DATAIN +rf_sink_data[86] => rp_data[90].DATAIN +rf_sink_data[87] => rp_data[83].DATAIN +rf_sink_data[88] => rp_data[84].DATAIN +rf_sink_data[89] => rp_data[85].DATAIN +rf_sink_data[90] => rp_data[86].DATAIN +rf_sink_data[91] => rp_data[91].DATAIN +rf_sink_data[92] => rp_data[92].DATAIN +rf_sink_data[93] => rp_data[93].DATAIN +rf_sink_data[94] => rp_data[94].DATAIN +rf_sink_data[95] => rp_data[95].DATAIN +rf_sink_data[96] => rp_data[96].DATAIN +rf_sink_data[97] => rp_data[97].DATAIN +rf_sink_data[98] => rp_data[98].DATAIN +rf_sink_data[99] => ~NO_FANOUT~ +rf_sink_data[100] => ~NO_FANOUT~ +rf_sink_data[101] => rdata_fifo_sink_ready.IN0 +rf_sink_data[101] => comb.IN0 +rf_sink_valid => rdata_fifo_sink_ready.IN1 +rf_sink_valid => comb.IN1 +rf_sink_startofpacket => comb.DATAA +rf_sink_endofpacket => rf_sink_endofpacket.IN1 +rf_sink_ready <= altera_merlin_burst_uncompressor:uncompressor.sink_ready +rdata_fifo_src_data[0] <= m0_readdata[0].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[1] <= m0_readdata[1].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[2] <= m0_readdata[2].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[3] <= m0_readdata[3].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[4] <= m0_readdata[4].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[5] <= m0_readdata[5].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[6] <= m0_readdata[6].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[7] <= m0_readdata[7].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[8] <= m0_readdata[8].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[9] <= m0_readdata[9].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[10] <= m0_readdata[10].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[11] <= m0_readdata[11].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[12] <= m0_readdata[12].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[13] <= m0_readdata[13].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[14] <= m0_readdata[14].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[15] <= m0_readdata[15].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[16] <= m0_readdata[16].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[17] <= m0_readdata[17].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[18] <= m0_readdata[18].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[19] <= m0_readdata[19].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[20] <= m0_readdata[20].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[21] <= m0_readdata[21].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[22] <= m0_readdata[22].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[23] <= m0_readdata[23].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[24] <= m0_readdata[24].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[25] <= m0_readdata[25].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[26] <= m0_readdata[26].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[27] <= m0_readdata[27].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[28] <= m0_readdata[28].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[29] <= m0_readdata[29].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[30] <= m0_readdata[30].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[31] <= m0_readdata[31].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_valid <= m0_readdatavalid.DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_ready => ~NO_FANOUT~ +rdata_fifo_sink_data[0] => rp_data[0].DATAIN +rdata_fifo_sink_data[1] => rp_data[1].DATAIN +rdata_fifo_sink_data[2] => rp_data[2].DATAIN +rdata_fifo_sink_data[3] => rp_data[3].DATAIN +rdata_fifo_sink_data[4] => rp_data[4].DATAIN +rdata_fifo_sink_data[5] => rp_data[5].DATAIN +rdata_fifo_sink_data[6] => rp_data[6].DATAIN +rdata_fifo_sink_data[7] => rp_data[7].DATAIN +rdata_fifo_sink_data[8] => rp_data[8].DATAIN +rdata_fifo_sink_data[9] => rp_data[9].DATAIN +rdata_fifo_sink_data[10] => rp_data[10].DATAIN +rdata_fifo_sink_data[11] => rp_data[11].DATAIN +rdata_fifo_sink_data[12] => rp_data[12].DATAIN +rdata_fifo_sink_data[13] => rp_data[13].DATAIN +rdata_fifo_sink_data[14] => rp_data[14].DATAIN +rdata_fifo_sink_data[15] => rp_data[15].DATAIN +rdata_fifo_sink_data[16] => rp_data[16].DATAIN +rdata_fifo_sink_data[17] => rp_data[17].DATAIN +rdata_fifo_sink_data[18] => rp_data[18].DATAIN +rdata_fifo_sink_data[19] => rp_data[19].DATAIN +rdata_fifo_sink_data[20] => rp_data[20].DATAIN +rdata_fifo_sink_data[21] => rp_data[21].DATAIN +rdata_fifo_sink_data[22] => rp_data[22].DATAIN +rdata_fifo_sink_data[23] => rp_data[23].DATAIN +rdata_fifo_sink_data[24] => rp_data[24].DATAIN +rdata_fifo_sink_data[25] => rp_data[25].DATAIN +rdata_fifo_sink_data[26] => rp_data[26].DATAIN +rdata_fifo_sink_data[27] => rp_data[27].DATAIN +rdata_fifo_sink_data[28] => rp_data[28].DATAIN +rdata_fifo_sink_data[29] => rp_data[29].DATAIN +rdata_fifo_sink_data[30] => rp_data[30].DATAIN +rdata_fifo_sink_data[31] => rp_data[31].DATAIN +rdata_fifo_sink_valid => rp_valid.IN1 +rdata_fifo_sink_valid => rdata_fifo_sink_ready.IN0 +rdata_fifo_sink_valid => comb.IN1 +rdata_fifo_sink_ready <= rdata_fifo_sink_ready.DB_MAX_OUTPUT_PORT_TYPE +cp_ready <= cp_ready.DB_MAX_OUTPUT_PORT_TYPE +cp_valid => local_lock.IN0 +cp_valid => local_write.IN0 +cp_valid => local_read.IN0 +cp_valid => local_compressed_read.IN0 +cp_data[0] => m0_writedata[0].DATAIN +cp_data[1] => m0_writedata[1].DATAIN +cp_data[2] => m0_writedata[2].DATAIN +cp_data[3] => m0_writedata[3].DATAIN +cp_data[4] => m0_writedata[4].DATAIN +cp_data[5] => m0_writedata[5].DATAIN +cp_data[6] => m0_writedata[6].DATAIN +cp_data[7] => m0_writedata[7].DATAIN +cp_data[8] => m0_writedata[8].DATAIN +cp_data[9] => m0_writedata[9].DATAIN +cp_data[10] => m0_writedata[10].DATAIN +cp_data[11] => m0_writedata[11].DATAIN +cp_data[12] => m0_writedata[12].DATAIN +cp_data[13] => m0_writedata[13].DATAIN +cp_data[14] => m0_writedata[14].DATAIN +cp_data[15] => m0_writedata[15].DATAIN +cp_data[16] => m0_writedata[16].DATAIN +cp_data[17] => m0_writedata[17].DATAIN +cp_data[18] => m0_writedata[18].DATAIN +cp_data[19] => m0_writedata[19].DATAIN +cp_data[20] => m0_writedata[20].DATAIN +cp_data[21] => m0_writedata[21].DATAIN +cp_data[22] => m0_writedata[22].DATAIN +cp_data[23] => m0_writedata[23].DATAIN +cp_data[24] => m0_writedata[24].DATAIN +cp_data[25] => m0_writedata[25].DATAIN +cp_data[26] => m0_writedata[26].DATAIN +cp_data[27] => m0_writedata[27].DATAIN +cp_data[28] => m0_writedata[28].DATAIN +cp_data[29] => m0_writedata[29].DATAIN +cp_data[30] => m0_writedata[30].DATAIN +cp_data[31] => m0_writedata[31].DATAIN +cp_data[32] => rf_source_data[32].DATAIN +cp_data[32] => m0_byteenable[0].DATAIN +cp_data[33] => rf_source_data[33].DATAIN +cp_data[33] => m0_byteenable[1].DATAIN +cp_data[34] => rf_source_data[34].DATAIN +cp_data[34] => m0_byteenable[2].DATAIN +cp_data[35] => rf_source_data[35].DATAIN +cp_data[35] => m0_byteenable[3].DATAIN +cp_data[36] => rf_source_data[36].DATAIN +cp_data[37] => rf_source_data[37].DATAIN +cp_data[38] => rf_source_data[38].DATAIN +cp_data[38] => m0_address[2].DATAIN +cp_data[39] => rf_source_data[39].DATAIN +cp_data[39] => m0_address[3].DATAIN +cp_data[40] => rf_source_data[40].DATAIN +cp_data[40] => m0_address[4].DATAIN +cp_data[41] => rf_source_data[41].DATAIN +cp_data[41] => m0_address[5].DATAIN +cp_data[42] => rf_source_data[42].DATAIN +cp_data[42] => m0_address[6].DATAIN +cp_data[43] => rf_source_data[43].DATAIN +cp_data[43] => m0_address[7].DATAIN +cp_data[44] => rf_source_data[44].DATAIN +cp_data[44] => m0_address[8].DATAIN +cp_data[45] => rf_source_data[45].DATAIN +cp_data[45] => m0_address[9].DATAIN +cp_data[46] => rf_source_data[46].DATAIN +cp_data[46] => m0_address[10].DATAIN +cp_data[47] => rf_source_data[47].DATAIN +cp_data[47] => m0_address[11].DATAIN +cp_data[48] => rf_source_data[48].DATAIN +cp_data[48] => m0_address[12].DATAIN +cp_data[49] => rf_source_data[49].DATAIN +cp_data[49] => m0_address[13].DATAIN +cp_data[50] => rf_source_data[50].DATAIN +cp_data[50] => m0_address[14].DATAIN +cp_data[51] => rf_source_data[51].DATAIN +cp_data[51] => m0_address[15].DATAIN +cp_data[52] => rf_source_data[52].DATAIN +cp_data[52] => m0_address[16].DATAIN +cp_data[53] => rf_source_data[53].DATAIN +cp_data[53] => m0_address[17].DATAIN +cp_data[54] => rf_source_data[54].DATAIN +cp_data[54] => m0_address[18].DATAIN +cp_data[55] => rf_source_data[55].DATAIN +cp_data[55] => m0_address[19].DATAIN +cp_data[56] => rf_source_data[56].DATAIN +cp_data[56] => m0_address[20].DATAIN +cp_data[57] => rf_source_data[57].DATAIN +cp_data[57] => m0_address[21].DATAIN +cp_data[58] => rf_source_data[58].DATAIN +cp_data[58] => m0_address[22].DATAIN +cp_data[59] => rf_source_data[59].DATAIN +cp_data[59] => m0_address[23].DATAIN +cp_data[60] => rf_source_data[60].DATAIN +cp_data[60] => m0_address[24].DATAIN +cp_data[61] => rf_source_data[61].DATAIN +cp_data[61] => m0_address[25].DATAIN +cp_data[62] => local_compressed_read.IN1 +cp_data[62] => rf_source_data[62].DATAIN +cp_data[63] => rf_source_data[63].DATAIN +cp_data[63] => comb.IN1 +cp_data[64] => local_write.IN1 +cp_data[64] => rf_source_data[64].DATAIN +cp_data[65] => local_read.IN1 +cp_data[65] => rf_source_data[65].DATAIN +cp_data[66] => local_lock.IN1 +cp_data[66] => rf_source_data[66].DATAIN +cp_data[67] => rf_source_data[67].DATAIN +cp_data[68] => m0_burstcount.DATAA +cp_data[68] => rf_source_data[68].DATAIN +cp_data[69] => m0_burstcount.DATAA +cp_data[69] => rf_source_data[69].DATAIN +cp_data[70] => m0_burstcount.DATAA +cp_data[70] => rf_source_data[70].DATAIN +cp_data[71] => rf_source_data[71].DATAIN +cp_data[72] => rf_source_data[72].DATAIN +cp_data[73] => rf_source_data[73].DATAIN +cp_data[74] => rf_source_data[74].DATAIN +cp_data[75] => rf_source_data[75].DATAIN +cp_data[76] => rf_source_data[76].DATAIN +cp_data[77] => rf_source_data[77].DATAIN +cp_data[78] => rf_source_data[78].DATAIN +cp_data[79] => rf_source_data[79].DATAIN +cp_data[80] => rf_source_data[80].DATAIN +cp_data[81] => rf_source_data[81].DATAIN +cp_data[82] => rf_source_data[82].DATAIN +cp_data[83] => rf_source_data[83].DATAIN +cp_data[84] => rf_source_data[84].DATAIN +cp_data[85] => rf_source_data[85].DATAIN +cp_data[86] => rf_source_data[86].DATAIN +cp_data[87] => rf_source_data[87].DATAIN +cp_data[88] => rf_source_data[88].DATAIN +cp_data[89] => rf_source_data[89].DATAIN +cp_data[90] => rf_source_data[90].DATAIN +cp_data[91] => rf_source_data[91].DATAIN +cp_data[92] => rf_source_data[92].DATAIN +cp_data[92] => m0_debugaccess.DATAIN +cp_data[93] => ~NO_FANOUT~ +cp_data[94] => ~NO_FANOUT~ +cp_data[95] => rf_source_data[95].DATAIN +cp_data[96] => rf_source_data[96].DATAIN +cp_data[97] => rf_source_data[97].DATAIN +cp_data[98] => rf_source_data[98].DATAIN +cp_data[99] => rf_source_data[99].DATAIN +cp_data[100] => rf_source_data[100].DATAIN +cp_channel[0] => ~NO_FANOUT~ +cp_channel[1] => ~NO_FANOUT~ +cp_channel[2] => ~NO_FANOUT~ +cp_channel[3] => ~NO_FANOUT~ +cp_channel[4] => ~NO_FANOUT~ +cp_channel[5] => ~NO_FANOUT~ +cp_channel[6] => ~NO_FANOUT~ +cp_channel[7] => ~NO_FANOUT~ +cp_channel[8] => ~NO_FANOUT~ +cp_channel[9] => ~NO_FANOUT~ +cp_channel[10] => ~NO_FANOUT~ +cp_startofpacket => rf_source_startofpacket.DATAIN +cp_endofpacket => nonposted_write_endofpacket.IN1 +cp_endofpacket => rf_source_endofpacket.DATAIN +rp_ready => rp_ready.IN1 +rp_valid <= rp_valid.DB_MAX_OUTPUT_PORT_TYPE +rp_data[0] <= rdata_fifo_sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +rp_data[1] <= rdata_fifo_sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +rp_data[2] <= rdata_fifo_sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +rp_data[3] <= rdata_fifo_sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +rp_data[4] <= rdata_fifo_sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +rp_data[5] <= rdata_fifo_sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +rp_data[6] <= rdata_fifo_sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +rp_data[7] <= rdata_fifo_sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +rp_data[8] <= rdata_fifo_sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +rp_data[9] <= rdata_fifo_sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +rp_data[10] <= rdata_fifo_sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +rp_data[11] <= rdata_fifo_sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +rp_data[12] <= rdata_fifo_sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +rp_data[13] <= rdata_fifo_sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +rp_data[14] <= rdata_fifo_sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +rp_data[15] <= rdata_fifo_sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +rp_data[16] <= rdata_fifo_sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +rp_data[17] <= rdata_fifo_sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +rp_data[18] <= rdata_fifo_sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +rp_data[19] <= rdata_fifo_sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +rp_data[20] <= rdata_fifo_sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +rp_data[21] <= rdata_fifo_sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +rp_data[22] <= rdata_fifo_sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +rp_data[23] <= rdata_fifo_sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +rp_data[24] <= rdata_fifo_sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +rp_data[25] <= rdata_fifo_sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +rp_data[26] <= rdata_fifo_sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +rp_data[27] <= rdata_fifo_sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +rp_data[28] <= rdata_fifo_sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +rp_data[29] <= rdata_fifo_sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +rp_data[30] <= rdata_fifo_sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +rp_data[31] <= rdata_fifo_sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +rp_data[32] <= rf_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +rp_data[33] <= rf_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +rp_data[34] <= rf_sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +rp_data[35] <= rf_sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +rp_data[36] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[37] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[38] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[39] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[40] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[41] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[42] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[43] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[44] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[45] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[46] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[47] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[48] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[49] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[50] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[51] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[52] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[53] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[54] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[55] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[56] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[57] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[58] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[59] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[60] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[61] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[62] <= altera_merlin_burst_uncompressor:uncompressor.source_is_compressed +rp_data[63] <= rf_sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +rp_data[64] <= rf_sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +rp_data[65] <= rp_data.DB_MAX_OUTPUT_PORT_TYPE +rp_data[66] <= rf_sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +rp_data[67] <= rf_sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +rp_data[68] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt +rp_data[69] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt +rp_data[70] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt +rp_data[71] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap +rp_data[72] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap +rp_data[73] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap +rp_data[74] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize +rp_data[75] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize +rp_data[76] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize +rp_data[77] <= rf_sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +rp_data[78] <= rf_sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +rp_data[79] <= rf_sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +rp_data[80] <= rf_sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +rp_data[81] <= rf_sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +rp_data[82] <= rf_sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +rp_data[83] <= rf_sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +rp_data[84] <= rf_sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +rp_data[85] <= rf_sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +rp_data[86] <= rf_sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +rp_data[87] <= rf_sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +rp_data[88] <= rf_sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +rp_data[89] <= rf_sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +rp_data[90] <= rf_sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +rp_data[91] <= rf_sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +rp_data[92] <= rf_sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +rp_data[93] <= rf_sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +rp_data[94] <= rf_sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +rp_data[95] <= rf_sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +rp_data[96] <= rf_sink_data[96].DB_MAX_OUTPUT_PORT_TYPE +rp_data[97] <= rf_sink_data[97].DB_MAX_OUTPUT_PORT_TYPE +rp_data[98] <= rf_sink_data[98].DB_MAX_OUTPUT_PORT_TYPE +rp_data[99] <= +rp_data[100] <= +rp_startofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_startofpacket +rp_endofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_endofpacket + + +|de0_nano_system|system:inst_cpu|altera_merlin_slave_agent:jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor +clk => burst_uncompress_address_offset[0].CLK +clk => burst_uncompress_address_offset[1].CLK +clk => burst_uncompress_address_offset[2].CLK +clk => burst_uncompress_address_offset[3].CLK +clk => burst_uncompress_address_offset[4].CLK +clk => burst_uncompress_address_offset[5].CLK +clk => burst_uncompress_address_offset[6].CLK +clk => burst_uncompress_address_offset[7].CLK +clk => burst_uncompress_address_offset[8].CLK +clk => burst_uncompress_address_offset[9].CLK +clk => burst_uncompress_address_offset[10].CLK +clk => burst_uncompress_address_offset[11].CLK +clk => burst_uncompress_address_offset[12].CLK +clk => burst_uncompress_address_offset[13].CLK +clk => burst_uncompress_address_offset[14].CLK +clk => burst_uncompress_address_offset[15].CLK +clk => burst_uncompress_address_offset[16].CLK +clk => burst_uncompress_address_offset[17].CLK +clk => burst_uncompress_address_offset[18].CLK +clk => burst_uncompress_address_offset[19].CLK +clk => burst_uncompress_address_offset[20].CLK +clk => burst_uncompress_address_offset[21].CLK +clk => burst_uncompress_address_offset[22].CLK +clk => burst_uncompress_address_offset[23].CLK +clk => burst_uncompress_address_offset[24].CLK +clk => burst_uncompress_address_offset[25].CLK +clk => burst_uncompress_address_base[0].CLK +clk => burst_uncompress_address_base[1].CLK +clk => burst_uncompress_address_base[2].CLK +clk => burst_uncompress_address_base[3].CLK +clk => burst_uncompress_address_base[4].CLK +clk => burst_uncompress_address_base[5].CLK +clk => burst_uncompress_address_base[6].CLK +clk => burst_uncompress_address_base[7].CLK +clk => burst_uncompress_address_base[8].CLK +clk => burst_uncompress_address_base[9].CLK +clk => burst_uncompress_address_base[10].CLK +clk => burst_uncompress_address_base[11].CLK +clk => burst_uncompress_address_base[12].CLK +clk => burst_uncompress_address_base[13].CLK +clk => burst_uncompress_address_base[14].CLK +clk => burst_uncompress_address_base[15].CLK +clk => burst_uncompress_address_base[16].CLK +clk => burst_uncompress_address_base[17].CLK +clk => burst_uncompress_address_base[18].CLK +clk => burst_uncompress_address_base[19].CLK +clk => burst_uncompress_address_base[20].CLK +clk => burst_uncompress_address_base[21].CLK +clk => burst_uncompress_address_base[22].CLK +clk => burst_uncompress_address_base[23].CLK +clk => burst_uncompress_address_base[24].CLK +clk => burst_uncompress_address_base[25].CLK +clk => burst_uncompress_byte_counter[0].CLK +clk => burst_uncompress_byte_counter[1].CLK +clk => burst_uncompress_byte_counter[2].CLK +clk => burst_uncompress_busy.CLK +reset => burst_uncompress_address_offset[0].ACLR +reset => burst_uncompress_address_offset[1].ACLR +reset => burst_uncompress_address_offset[2].ACLR +reset => burst_uncompress_address_offset[3].ACLR +reset => burst_uncompress_address_offset[4].ACLR +reset => burst_uncompress_address_offset[5].ACLR +reset => burst_uncompress_address_offset[6].ACLR +reset => burst_uncompress_address_offset[7].ACLR +reset => burst_uncompress_address_offset[8].ACLR +reset => burst_uncompress_address_offset[9].ACLR +reset => burst_uncompress_address_offset[10].ACLR +reset => burst_uncompress_address_offset[11].ACLR +reset => burst_uncompress_address_offset[12].ACLR +reset => burst_uncompress_address_offset[13].ACLR +reset => burst_uncompress_address_offset[14].ACLR +reset => burst_uncompress_address_offset[15].ACLR +reset => burst_uncompress_address_offset[16].ACLR +reset => burst_uncompress_address_offset[17].ACLR +reset => burst_uncompress_address_offset[18].ACLR +reset => burst_uncompress_address_offset[19].ACLR +reset => burst_uncompress_address_offset[20].ACLR +reset => burst_uncompress_address_offset[21].ACLR +reset => burst_uncompress_address_offset[22].ACLR +reset => burst_uncompress_address_offset[23].ACLR +reset => burst_uncompress_address_offset[24].ACLR +reset => burst_uncompress_address_offset[25].ACLR +reset => burst_uncompress_address_base[0].ACLR +reset => burst_uncompress_address_base[1].ACLR +reset => burst_uncompress_address_base[2].ACLR +reset => burst_uncompress_address_base[3].ACLR +reset => burst_uncompress_address_base[4].ACLR +reset => burst_uncompress_address_base[5].ACLR +reset => burst_uncompress_address_base[6].ACLR +reset => burst_uncompress_address_base[7].ACLR +reset => burst_uncompress_address_base[8].ACLR +reset => burst_uncompress_address_base[9].ACLR +reset => burst_uncompress_address_base[10].ACLR +reset => burst_uncompress_address_base[11].ACLR +reset => burst_uncompress_address_base[12].ACLR +reset => burst_uncompress_address_base[13].ACLR +reset => burst_uncompress_address_base[14].ACLR +reset => burst_uncompress_address_base[15].ACLR +reset => burst_uncompress_address_base[16].ACLR +reset => burst_uncompress_address_base[17].ACLR +reset => burst_uncompress_address_base[18].ACLR +reset => burst_uncompress_address_base[19].ACLR +reset => burst_uncompress_address_base[20].ACLR +reset => burst_uncompress_address_base[21].ACLR +reset => burst_uncompress_address_base[22].ACLR +reset => burst_uncompress_address_base[23].ACLR +reset => burst_uncompress_address_base[24].ACLR +reset => burst_uncompress_address_base[25].ACLR +reset => burst_uncompress_byte_counter[0].ACLR +reset => burst_uncompress_byte_counter[1].ACLR +reset => burst_uncompress_byte_counter[2].ACLR +reset => burst_uncompress_busy.ACLR +sink_startofpacket => source_startofpacket.IN1 +sink_endofpacket => source_endofpacket.IN1 +sink_valid => first_packet_beat.IN1 +sink_valid => last_packet_beat.IN1 +sink_valid => last_packet_beat.IN1 +sink_valid => always0.IN1 +sink_valid => sink_ready.IN0 +sink_valid => source_valid.DATAIN +sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE +sink_addr[0] => burst_uncompress_address_base.IN0 +sink_addr[0] => comb.DATAB +sink_addr[0] => source_addr.DATAB +sink_addr[1] => burst_uncompress_address_base.IN0 +sink_addr[1] => comb.DATAB +sink_addr[1] => source_addr.DATAB +sink_addr[2] => burst_uncompress_address_base.IN0 +sink_addr[2] => comb.DATAB +sink_addr[2] => source_addr.DATAB +sink_addr[3] => burst_uncompress_address_base.IN0 +sink_addr[3] => comb.DATAB +sink_addr[3] => source_addr.DATAB +sink_addr[4] => burst_uncompress_address_base.IN0 +sink_addr[4] => comb.DATAB +sink_addr[4] => source_addr.DATAB +sink_addr[5] => burst_uncompress_address_base.IN0 +sink_addr[5] => comb.DATAB +sink_addr[5] => source_addr.DATAB +sink_addr[6] => burst_uncompress_address_base.IN0 +sink_addr[6] => comb.DATAB +sink_addr[6] => source_addr.DATAB +sink_addr[7] => burst_uncompress_address_base.IN0 +sink_addr[7] => comb.DATAB +sink_addr[7] => source_addr.DATAB +sink_addr[8] => burst_uncompress_address_base.IN0 +sink_addr[8] => comb.DATAB +sink_addr[8] => source_addr.DATAB +sink_addr[9] => burst_uncompress_address_base.IN0 +sink_addr[9] => comb.DATAB +sink_addr[9] => source_addr.DATAB +sink_addr[10] => burst_uncompress_address_base.IN0 +sink_addr[10] => comb.DATAB +sink_addr[10] => source_addr.DATAB +sink_addr[11] => burst_uncompress_address_base.IN0 +sink_addr[11] => comb.DATAB +sink_addr[11] => source_addr.DATAB +sink_addr[12] => burst_uncompress_address_base.IN0 +sink_addr[12] => comb.DATAB +sink_addr[12] => source_addr.DATAB +sink_addr[13] => burst_uncompress_address_base.IN0 +sink_addr[13] => comb.DATAB +sink_addr[13] => source_addr.DATAB +sink_addr[14] => burst_uncompress_address_base.IN0 +sink_addr[14] => comb.DATAB +sink_addr[14] => source_addr.DATAB +sink_addr[15] => burst_uncompress_address_base.IN0 +sink_addr[15] => comb.DATAB +sink_addr[15] => source_addr.DATAB +sink_addr[16] => burst_uncompress_address_base.IN0 +sink_addr[16] => comb.DATAB +sink_addr[16] => source_addr.DATAB +sink_addr[17] => burst_uncompress_address_base.IN0 +sink_addr[17] => comb.DATAB +sink_addr[17] => source_addr.DATAB +sink_addr[18] => burst_uncompress_address_base.IN0 +sink_addr[18] => comb.DATAB +sink_addr[18] => source_addr.DATAB +sink_addr[19] => burst_uncompress_address_base.IN0 +sink_addr[19] => comb.DATAB +sink_addr[19] => source_addr.DATAB +sink_addr[20] => burst_uncompress_address_base.IN0 +sink_addr[20] => comb.DATAB +sink_addr[20] => source_addr.DATAB +sink_addr[21] => burst_uncompress_address_base.IN0 +sink_addr[21] => comb.DATAB +sink_addr[21] => source_addr.DATAB +sink_addr[22] => burst_uncompress_address_base.IN0 +sink_addr[22] => comb.DATAB +sink_addr[22] => source_addr.DATAB +sink_addr[23] => burst_uncompress_address_base.IN0 +sink_addr[23] => comb.DATAB +sink_addr[23] => source_addr.DATAB +sink_addr[24] => burst_uncompress_address_base.IN0 +sink_addr[24] => comb.DATAB +sink_addr[24] => source_addr.DATAB +sink_addr[25] => burst_uncompress_address_base.IN0 +sink_addr[25] => comb.DATAB +sink_addr[25] => source_addr.DATAB +sink_burstwrap[0] => p1_burst_uncompress_address_offset[0].IN1 +sink_burstwrap[0] => source_burstwrap[0].DATAIN +sink_burstwrap[0] => burst_uncompress_address_base.IN1 +sink_burstwrap[1] => p1_burst_uncompress_address_offset[1].IN1 +sink_burstwrap[1] => source_burstwrap[1].DATAIN +sink_burstwrap[1] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[2].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[25].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[24].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[23].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[22].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[21].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[20].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[19].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[18].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[17].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[16].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[15].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[14].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[13].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[12].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[11].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[10].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[9].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[8].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[7].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[6].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[5].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[4].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[3].IN1 +sink_burstwrap[2] => source_burstwrap[2].DATAIN +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_byte_cnt[0] => source_byte_cnt.DATAB +sink_byte_cnt[0] => Add1.IN6 +sink_byte_cnt[0] => Equal1.IN2 +sink_byte_cnt[1] => source_byte_cnt.DATAB +sink_byte_cnt[1] => Add1.IN5 +sink_byte_cnt[1] => Equal1.IN1 +sink_byte_cnt[2] => source_byte_cnt.DATAB +sink_byte_cnt[2] => Add1.IN4 +sink_byte_cnt[2] => Equal1.IN0 +sink_is_compressed => last_packet_beat.IN1 +sink_burstsize[0] => Decoder0.IN2 +sink_burstsize[0] => source_burstsize[0].DATAIN +sink_burstsize[1] => Decoder0.IN1 +sink_burstsize[1] => source_burstsize[1].DATAIN +sink_burstsize[2] => Decoder0.IN0 +sink_burstsize[2] => source_burstsize[2].DATAIN +source_startofpacket <= source_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +source_endofpacket <= source_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +source_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE +source_ready => always1.IN1 +source_ready => sink_ready.IN1 +source_addr[0] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[1] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[2] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[3] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[4] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[5] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[6] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[7] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[8] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[9] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[10] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[11] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[12] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[13] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[14] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[15] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[16] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[17] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[18] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[19] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[20] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[21] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[22] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[23] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[24] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[25] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_burstwrap[0] <= sink_burstwrap[0].DB_MAX_OUTPUT_PORT_TYPE +source_burstwrap[1] <= sink_burstwrap[1].DB_MAX_OUTPUT_PORT_TYPE +source_burstwrap[2] <= sink_burstwrap[2].DB_MAX_OUTPUT_PORT_TYPE +source_byte_cnt[0] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE +source_byte_cnt[1] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE +source_byte_cnt[2] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE +source_is_compressed <= +source_burstsize[0] <= sink_burstsize[0].DB_MAX_OUTPUT_PORT_TYPE +source_burstsize[1] <= sink_burstsize[1].DB_MAX_OUTPUT_PORT_TYPE +source_burstsize[2] <= sink_burstsize[2].DB_MAX_OUTPUT_PORT_TYPE + + +|de0_nano_system|system:inst_cpu|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo +clk => csr_readdata[0]~reg0.CLK +clk => csr_readdata[1]~reg0.CLK +clk => csr_readdata[2]~reg0.CLK +clk => csr_readdata[3]~reg0.CLK +clk => csr_readdata[4]~reg0.CLK +clk => csr_readdata[5]~reg0.CLK +clk => csr_readdata[6]~reg0.CLK +clk => csr_readdata[7]~reg0.CLK +clk => csr_readdata[8]~reg0.CLK +clk => csr_readdata[9]~reg0.CLK +clk => csr_readdata[10]~reg0.CLK +clk => csr_readdata[11]~reg0.CLK +clk => csr_readdata[12]~reg0.CLK +clk => csr_readdata[13]~reg0.CLK +clk => csr_readdata[14]~reg0.CLK +clk => csr_readdata[15]~reg0.CLK +clk => csr_readdata[16]~reg0.CLK +clk => csr_readdata[17]~reg0.CLK +clk => csr_readdata[18]~reg0.CLK +clk => csr_readdata[19]~reg0.CLK +clk => csr_readdata[20]~reg0.CLK +clk => csr_readdata[21]~reg0.CLK +clk => csr_readdata[22]~reg0.CLK +clk => csr_readdata[23]~reg0.CLK +clk => csr_readdata[24]~reg0.CLK +clk => csr_readdata[25]~reg0.CLK +clk => csr_readdata[26]~reg0.CLK +clk => csr_readdata[27]~reg0.CLK +clk => csr_readdata[28]~reg0.CLK +clk => csr_readdata[29]~reg0.CLK +clk => csr_readdata[30]~reg0.CLK +clk => csr_readdata[31]~reg0.CLK +clk => mem_used[1].CLK +clk => mem_used[0].CLK +clk => mem[1][0].CLK +clk => mem[1][1].CLK +clk => mem[1][2].CLK +clk => mem[1][3].CLK +clk => mem[1][4].CLK +clk => mem[1][5].CLK +clk => mem[1][6].CLK +clk => mem[1][7].CLK +clk => mem[1][8].CLK +clk => mem[1][9].CLK +clk => mem[1][10].CLK +clk => mem[1][11].CLK +clk => mem[1][12].CLK +clk => mem[1][13].CLK +clk => mem[1][14].CLK +clk => mem[1][15].CLK +clk => mem[1][16].CLK +clk => mem[1][17].CLK +clk => mem[1][18].CLK +clk => mem[1][19].CLK +clk => mem[1][20].CLK +clk => mem[1][21].CLK +clk => mem[1][22].CLK +clk => mem[1][23].CLK +clk => mem[1][24].CLK +clk => mem[1][25].CLK +clk => mem[1][26].CLK +clk => mem[1][27].CLK +clk => mem[1][28].CLK +clk => mem[1][29].CLK +clk => mem[1][30].CLK +clk => mem[1][31].CLK +clk => mem[1][32].CLK +clk => mem[1][33].CLK +clk => mem[1][34].CLK +clk => mem[1][35].CLK +clk => mem[1][36].CLK +clk => mem[1][37].CLK +clk => mem[1][38].CLK +clk => mem[1][39].CLK +clk => mem[1][40].CLK +clk => mem[1][41].CLK +clk => mem[1][42].CLK +clk => mem[1][43].CLK +clk => mem[1][44].CLK +clk => mem[1][45].CLK +clk => mem[1][46].CLK +clk => mem[1][47].CLK +clk => mem[1][48].CLK +clk => mem[1][49].CLK +clk => mem[1][50].CLK +clk => mem[1][51].CLK +clk => mem[1][52].CLK +clk => mem[1][53].CLK +clk => mem[1][54].CLK +clk => mem[1][55].CLK +clk => mem[1][56].CLK +clk => mem[1][57].CLK +clk => mem[1][58].CLK +clk => mem[1][59].CLK +clk => mem[1][60].CLK +clk => mem[1][61].CLK +clk => mem[1][62].CLK +clk => mem[1][63].CLK +clk => mem[1][64].CLK +clk => mem[1][65].CLK +clk => mem[1][66].CLK +clk => mem[1][67].CLK +clk => mem[1][68].CLK +clk => mem[1][69].CLK +clk => mem[1][70].CLK +clk => mem[1][71].CLK +clk => mem[1][72].CLK +clk => mem[1][73].CLK +clk => mem[1][74].CLK +clk => mem[1][75].CLK +clk => mem[1][76].CLK +clk => mem[1][77].CLK +clk => mem[1][78].CLK +clk => mem[1][79].CLK +clk => mem[1][80].CLK +clk => mem[1][81].CLK +clk => mem[1][82].CLK +clk => mem[1][83].CLK +clk => mem[1][84].CLK +clk => mem[1][85].CLK +clk => mem[1][86].CLK +clk => mem[1][87].CLK +clk => mem[1][88].CLK +clk => mem[1][89].CLK +clk => mem[1][90].CLK +clk => mem[1][91].CLK +clk => mem[1][92].CLK +clk => mem[1][93].CLK +clk => mem[1][94].CLK +clk => mem[1][95].CLK +clk => mem[1][96].CLK +clk => mem[1][97].CLK +clk => mem[1][98].CLK +clk => mem[1][99].CLK +clk => mem[1][100].CLK +clk => mem[1][101].CLK +clk => mem[1][102].CLK +clk => mem[1][103].CLK +clk => mem[0][0].CLK +clk => mem[0][1].CLK +clk => mem[0][2].CLK +clk => mem[0][3].CLK +clk => mem[0][4].CLK +clk => mem[0][5].CLK +clk => mem[0][6].CLK +clk => mem[0][7].CLK +clk => mem[0][8].CLK +clk => mem[0][9].CLK +clk => mem[0][10].CLK +clk => mem[0][11].CLK +clk => mem[0][12].CLK +clk => mem[0][13].CLK +clk => mem[0][14].CLK +clk => mem[0][15].CLK +clk => mem[0][16].CLK +clk => mem[0][17].CLK +clk => mem[0][18].CLK +clk => mem[0][19].CLK +clk => mem[0][20].CLK +clk => mem[0][21].CLK +clk => mem[0][22].CLK +clk => mem[0][23].CLK +clk => mem[0][24].CLK +clk => mem[0][25].CLK +clk => mem[0][26].CLK +clk => mem[0][27].CLK +clk => mem[0][28].CLK +clk => mem[0][29].CLK +clk => mem[0][30].CLK +clk => mem[0][31].CLK +clk => mem[0][32].CLK +clk => mem[0][33].CLK +clk => mem[0][34].CLK +clk => mem[0][35].CLK +clk => mem[0][36].CLK +clk => mem[0][37].CLK +clk => mem[0][38].CLK +clk => mem[0][39].CLK +clk => mem[0][40].CLK +clk => mem[0][41].CLK +clk => mem[0][42].CLK +clk => mem[0][43].CLK +clk => mem[0][44].CLK +clk => mem[0][45].CLK +clk => mem[0][46].CLK +clk => mem[0][47].CLK +clk => mem[0][48].CLK +clk => mem[0][49].CLK +clk => mem[0][50].CLK +clk => mem[0][51].CLK +clk => mem[0][52].CLK +clk => mem[0][53].CLK +clk => mem[0][54].CLK +clk => mem[0][55].CLK +clk => mem[0][56].CLK +clk => mem[0][57].CLK +clk => mem[0][58].CLK +clk => mem[0][59].CLK +clk => mem[0][60].CLK +clk => mem[0][61].CLK +clk => mem[0][62].CLK +clk => mem[0][63].CLK +clk => mem[0][64].CLK +clk => mem[0][65].CLK +clk => mem[0][66].CLK +clk => mem[0][67].CLK +clk => mem[0][68].CLK +clk => mem[0][69].CLK +clk => mem[0][70].CLK +clk => mem[0][71].CLK +clk => mem[0][72].CLK +clk => mem[0][73].CLK +clk => mem[0][74].CLK +clk => mem[0][75].CLK +clk => mem[0][76].CLK +clk => mem[0][77].CLK +clk => mem[0][78].CLK +clk => mem[0][79].CLK +clk => mem[0][80].CLK +clk => mem[0][81].CLK +clk => mem[0][82].CLK +clk => mem[0][83].CLK +clk => mem[0][84].CLK +clk => mem[0][85].CLK +clk => mem[0][86].CLK +clk => mem[0][87].CLK +clk => mem[0][88].CLK +clk => mem[0][89].CLK +clk => mem[0][90].CLK +clk => mem[0][91].CLK +clk => mem[0][92].CLK +clk => mem[0][93].CLK +clk => mem[0][94].CLK +clk => mem[0][95].CLK +clk => mem[0][96].CLK +clk => mem[0][97].CLK +clk => mem[0][98].CLK +clk => mem[0][99].CLK +clk => mem[0][100].CLK +clk => mem[0][101].CLK +clk => mem[0][102].CLK +clk => mem[0][103].CLK +reset => csr_readdata[0]~reg0.ACLR +reset => csr_readdata[1]~reg0.ACLR +reset => csr_readdata[2]~reg0.ACLR +reset => csr_readdata[3]~reg0.ACLR +reset => csr_readdata[4]~reg0.ACLR +reset => csr_readdata[5]~reg0.ACLR +reset => csr_readdata[6]~reg0.ACLR +reset => csr_readdata[7]~reg0.ACLR +reset => csr_readdata[8]~reg0.ACLR +reset => csr_readdata[9]~reg0.ACLR +reset => csr_readdata[10]~reg0.ACLR +reset => csr_readdata[11]~reg0.ACLR +reset => csr_readdata[12]~reg0.ACLR +reset => csr_readdata[13]~reg0.ACLR +reset => csr_readdata[14]~reg0.ACLR +reset => csr_readdata[15]~reg0.ACLR +reset => csr_readdata[16]~reg0.ACLR +reset => csr_readdata[17]~reg0.ACLR +reset => csr_readdata[18]~reg0.ACLR +reset => csr_readdata[19]~reg0.ACLR +reset => csr_readdata[20]~reg0.ACLR +reset => csr_readdata[21]~reg0.ACLR +reset => csr_readdata[22]~reg0.ACLR +reset => csr_readdata[23]~reg0.ACLR +reset => csr_readdata[24]~reg0.ACLR +reset => csr_readdata[25]~reg0.ACLR +reset => csr_readdata[26]~reg0.ACLR +reset => csr_readdata[27]~reg0.ACLR +reset => csr_readdata[28]~reg0.ACLR +reset => csr_readdata[29]~reg0.ACLR +reset => csr_readdata[30]~reg0.ACLR +reset => csr_readdata[31]~reg0.ACLR +reset => mem_used[1].ACLR +reset => mem_used[0].ACLR +reset => mem[1][0].ACLR +reset => mem[1][1].ACLR +reset => mem[1][2].ACLR +reset => mem[1][3].ACLR +reset => mem[1][4].ACLR +reset => mem[1][5].ACLR +reset => mem[1][6].ACLR +reset => mem[1][7].ACLR +reset => mem[1][8].ACLR +reset => mem[1][9].ACLR +reset => mem[1][10].ACLR +reset => mem[1][11].ACLR +reset => mem[1][12].ACLR +reset => mem[1][13].ACLR +reset => mem[1][14].ACLR +reset => mem[1][15].ACLR +reset => mem[1][16].ACLR +reset => mem[1][17].ACLR +reset => mem[1][18].ACLR +reset => mem[1][19].ACLR +reset => mem[1][20].ACLR +reset => mem[1][21].ACLR +reset => mem[1][22].ACLR +reset => mem[1][23].ACLR +reset => mem[1][24].ACLR +reset => mem[1][25].ACLR +reset => mem[1][26].ACLR +reset => mem[1][27].ACLR +reset => mem[1][28].ACLR +reset => mem[1][29].ACLR +reset => mem[1][30].ACLR +reset => mem[1][31].ACLR +reset => mem[1][32].ACLR +reset => mem[1][33].ACLR +reset => mem[1][34].ACLR +reset => mem[1][35].ACLR +reset => mem[1][36].ACLR +reset => mem[1][37].ACLR +reset => mem[1][38].ACLR +reset => mem[1][39].ACLR +reset => mem[1][40].ACLR +reset => mem[1][41].ACLR +reset => mem[1][42].ACLR +reset => mem[1][43].ACLR +reset => mem[1][44].ACLR +reset => mem[1][45].ACLR +reset => mem[1][46].ACLR +reset => mem[1][47].ACLR +reset => mem[1][48].ACLR +reset => mem[1][49].ACLR +reset => mem[1][50].ACLR +reset => mem[1][51].ACLR +reset => mem[1][52].ACLR +reset => mem[1][53].ACLR +reset => mem[1][54].ACLR +reset => mem[1][55].ACLR +reset => mem[1][56].ACLR +reset => mem[1][57].ACLR +reset => mem[1][58].ACLR +reset => mem[1][59].ACLR +reset => mem[1][60].ACLR +reset => mem[1][61].ACLR +reset => mem[1][62].ACLR +reset => mem[1][63].ACLR +reset => mem[1][64].ACLR +reset => mem[1][65].ACLR +reset => mem[1][66].ACLR +reset => mem[1][67].ACLR +reset => mem[1][68].ACLR +reset => mem[1][69].ACLR +reset => mem[1][70].ACLR +reset => mem[1][71].ACLR +reset => mem[1][72].ACLR +reset => mem[1][73].ACLR +reset => mem[1][74].ACLR +reset => mem[1][75].ACLR +reset => mem[1][76].ACLR +reset => mem[1][77].ACLR +reset => mem[1][78].ACLR +reset => mem[1][79].ACLR +reset => mem[1][80].ACLR +reset => mem[1][81].ACLR +reset => mem[1][82].ACLR +reset => mem[1][83].ACLR +reset => mem[1][84].ACLR +reset => mem[1][85].ACLR +reset => mem[1][86].ACLR +reset => mem[1][87].ACLR +reset => mem[1][88].ACLR +reset => mem[1][89].ACLR +reset => mem[1][90].ACLR +reset => mem[1][91].ACLR +reset => mem[1][92].ACLR +reset => mem[1][93].ACLR +reset => mem[1][94].ACLR +reset => mem[1][95].ACLR +reset => mem[1][96].ACLR +reset => mem[1][97].ACLR +reset => mem[1][98].ACLR +reset => mem[1][99].ACLR +reset => mem[1][100].ACLR +reset => mem[1][101].ACLR +reset => mem[1][102].ACLR +reset => mem[1][103].ACLR +reset => mem[0][0].ACLR +reset => mem[0][1].ACLR +reset => mem[0][2].ACLR +reset => mem[0][3].ACLR +reset => mem[0][4].ACLR +reset => mem[0][5].ACLR +reset => mem[0][6].ACLR +reset => mem[0][7].ACLR +reset => mem[0][8].ACLR +reset => mem[0][9].ACLR +reset => mem[0][10].ACLR +reset => mem[0][11].ACLR +reset => mem[0][12].ACLR +reset => mem[0][13].ACLR +reset => mem[0][14].ACLR +reset => mem[0][15].ACLR +reset => mem[0][16].ACLR +reset => mem[0][17].ACLR +reset => mem[0][18].ACLR +reset => mem[0][19].ACLR +reset => mem[0][20].ACLR +reset => mem[0][21].ACLR +reset => mem[0][22].ACLR +reset => mem[0][23].ACLR +reset => mem[0][24].ACLR +reset => mem[0][25].ACLR +reset => mem[0][26].ACLR +reset => mem[0][27].ACLR +reset => mem[0][28].ACLR +reset => mem[0][29].ACLR +reset => mem[0][30].ACLR +reset => mem[0][31].ACLR +reset => mem[0][32].ACLR +reset => mem[0][33].ACLR +reset => mem[0][34].ACLR +reset => mem[0][35].ACLR +reset => mem[0][36].ACLR +reset => mem[0][37].ACLR +reset => mem[0][38].ACLR +reset => mem[0][39].ACLR +reset => mem[0][40].ACLR +reset => mem[0][41].ACLR +reset => mem[0][42].ACLR +reset => mem[0][43].ACLR +reset => mem[0][44].ACLR +reset => mem[0][45].ACLR +reset => mem[0][46].ACLR +reset => mem[0][47].ACLR +reset => mem[0][48].ACLR +reset => mem[0][49].ACLR +reset => mem[0][50].ACLR +reset => mem[0][51].ACLR +reset => mem[0][52].ACLR +reset => mem[0][53].ACLR +reset => mem[0][54].ACLR +reset => mem[0][55].ACLR +reset => mem[0][56].ACLR +reset => mem[0][57].ACLR +reset => mem[0][58].ACLR +reset => mem[0][59].ACLR +reset => mem[0][60].ACLR +reset => mem[0][61].ACLR +reset => mem[0][62].ACLR +reset => mem[0][63].ACLR +reset => mem[0][64].ACLR +reset => mem[0][65].ACLR +reset => mem[0][66].ACLR +reset => mem[0][67].ACLR +reset => mem[0][68].ACLR +reset => mem[0][69].ACLR +reset => mem[0][70].ACLR +reset => mem[0][71].ACLR +reset => mem[0][72].ACLR +reset => mem[0][73].ACLR +reset => mem[0][74].ACLR +reset => mem[0][75].ACLR +reset => mem[0][76].ACLR +reset => mem[0][77].ACLR +reset => mem[0][78].ACLR +reset => mem[0][79].ACLR +reset => mem[0][80].ACLR +reset => mem[0][81].ACLR +reset => mem[0][82].ACLR +reset => mem[0][83].ACLR +reset => mem[0][84].ACLR +reset => mem[0][85].ACLR +reset => mem[0][86].ACLR +reset => mem[0][87].ACLR +reset => mem[0][88].ACLR +reset => mem[0][89].ACLR +reset => mem[0][90].ACLR +reset => mem[0][91].ACLR +reset => mem[0][92].ACLR +reset => mem[0][93].ACLR +reset => mem[0][94].ACLR +reset => mem[0][95].ACLR +reset => mem[0][96].ACLR +reset => mem[0][97].ACLR +reset => mem[0][98].ACLR +reset => mem[0][99].ACLR +reset => mem[0][100].ACLR +reset => mem[0][101].ACLR +reset => mem[0][102].ACLR +reset => mem[0][103].ACLR +in_data[0] => mem.DATAB +in_data[1] => mem.DATAB +in_data[2] => mem.DATAB +in_data[3] => mem.DATAB +in_data[4] => mem.DATAB +in_data[5] => mem.DATAB +in_data[6] => mem.DATAB +in_data[7] => mem.DATAB +in_data[8] => mem.DATAB +in_data[9] => mem.DATAB +in_data[10] => mem.DATAB +in_data[11] => mem.DATAB +in_data[12] => mem.DATAB +in_data[13] => mem.DATAB +in_data[14] => mem.DATAB +in_data[15] => mem.DATAB +in_data[16] => mem.DATAB +in_data[17] => mem.DATAB +in_data[18] => mem.DATAB +in_data[19] => mem.DATAB +in_data[20] => mem.DATAB +in_data[21] => mem.DATAB +in_data[22] => mem.DATAB +in_data[23] => mem.DATAB +in_data[24] => mem.DATAB +in_data[25] => mem.DATAB +in_data[26] => mem.DATAB +in_data[27] => mem.DATAB +in_data[28] => mem.DATAB +in_data[29] => mem.DATAB +in_data[30] => mem.DATAB +in_data[31] => mem.DATAB +in_data[32] => mem.DATAB +in_data[33] => mem.DATAB +in_data[34] => mem.DATAB +in_data[35] => mem.DATAB +in_data[36] => mem.DATAB +in_data[37] => mem.DATAB +in_data[38] => mem.DATAB +in_data[39] => mem.DATAB +in_data[40] => mem.DATAB +in_data[41] => mem.DATAB +in_data[42] => mem.DATAB +in_data[43] => mem.DATAB +in_data[44] => mem.DATAB +in_data[45] => mem.DATAB +in_data[46] => mem.DATAB +in_data[47] => mem.DATAB +in_data[48] => mem.DATAB +in_data[49] => mem.DATAB +in_data[50] => mem.DATAB +in_data[51] => mem.DATAB +in_data[52] => mem.DATAB +in_data[53] => mem.DATAB +in_data[54] => mem.DATAB +in_data[55] => mem.DATAB +in_data[56] => mem.DATAB +in_data[57] => mem.DATAB +in_data[58] => mem.DATAB +in_data[59] => mem.DATAB +in_data[60] => mem.DATAB +in_data[61] => mem.DATAB +in_data[62] => mem.DATAB +in_data[63] => mem.DATAB +in_data[64] => mem.DATAB +in_data[65] => mem.DATAB +in_data[66] => mem.DATAB +in_data[67] => mem.DATAB +in_data[68] => mem.DATAB +in_data[69] => mem.DATAB +in_data[70] => mem.DATAB +in_data[71] => mem.DATAB +in_data[72] => mem.DATAB +in_data[73] => mem.DATAB +in_data[74] => mem.DATAB +in_data[75] => mem.DATAB +in_data[76] => mem.DATAB +in_data[77] => mem.DATAB +in_data[78] => mem.DATAB +in_data[79] => mem.DATAB +in_data[80] => mem.DATAB +in_data[81] => mem.DATAB +in_data[82] => mem.DATAB +in_data[83] => mem.DATAB +in_data[84] => mem.DATAB +in_data[85] => mem.DATAB +in_data[86] => mem.DATAB +in_data[87] => mem.DATAB +in_data[88] => mem.DATAB +in_data[89] => mem.DATAB +in_data[90] => mem.DATAB +in_data[91] => mem.DATAB +in_data[92] => mem.DATAB +in_data[93] => mem.DATAB +in_data[94] => mem.DATAB +in_data[95] => mem.DATAB +in_data[96] => mem.DATAB +in_data[97] => mem.DATAB +in_data[98] => mem.DATAB +in_data[99] => mem.DATAB +in_data[100] => mem.DATAB +in_data[101] => mem.DATAB +in_valid => write.IN1 +in_startofpacket => mem.DATAB +in_endofpacket => mem.DATAB +in_empty[0] => ~NO_FANOUT~ +in_error[0] => out_error[0].DATAIN +in_error[0] => out_empty[0].DATAIN +in_channel[0] => out_channel[0].DATAIN +in_ready <= mem_used[1].DB_MAX_OUTPUT_PORT_TYPE +out_data[0] <= mem[0][0].DB_MAX_OUTPUT_PORT_TYPE +out_data[1] <= mem[0][1].DB_MAX_OUTPUT_PORT_TYPE +out_data[2] <= mem[0][2].DB_MAX_OUTPUT_PORT_TYPE +out_data[3] <= mem[0][3].DB_MAX_OUTPUT_PORT_TYPE +out_data[4] <= mem[0][4].DB_MAX_OUTPUT_PORT_TYPE +out_data[5] <= mem[0][5].DB_MAX_OUTPUT_PORT_TYPE +out_data[6] <= mem[0][6].DB_MAX_OUTPUT_PORT_TYPE +out_data[7] <= mem[0][7].DB_MAX_OUTPUT_PORT_TYPE +out_data[8] <= mem[0][8].DB_MAX_OUTPUT_PORT_TYPE +out_data[9] <= mem[0][9].DB_MAX_OUTPUT_PORT_TYPE +out_data[10] <= mem[0][10].DB_MAX_OUTPUT_PORT_TYPE +out_data[11] <= mem[0][11].DB_MAX_OUTPUT_PORT_TYPE +out_data[12] <= mem[0][12].DB_MAX_OUTPUT_PORT_TYPE +out_data[13] <= mem[0][13].DB_MAX_OUTPUT_PORT_TYPE +out_data[14] <= mem[0][14].DB_MAX_OUTPUT_PORT_TYPE +out_data[15] <= mem[0][15].DB_MAX_OUTPUT_PORT_TYPE +out_data[16] <= mem[0][16].DB_MAX_OUTPUT_PORT_TYPE +out_data[17] <= mem[0][17].DB_MAX_OUTPUT_PORT_TYPE +out_data[18] <= mem[0][18].DB_MAX_OUTPUT_PORT_TYPE +out_data[19] <= mem[0][19].DB_MAX_OUTPUT_PORT_TYPE +out_data[20] <= mem[0][20].DB_MAX_OUTPUT_PORT_TYPE +out_data[21] <= mem[0][21].DB_MAX_OUTPUT_PORT_TYPE +out_data[22] <= mem[0][22].DB_MAX_OUTPUT_PORT_TYPE +out_data[23] <= mem[0][23].DB_MAX_OUTPUT_PORT_TYPE +out_data[24] <= mem[0][24].DB_MAX_OUTPUT_PORT_TYPE +out_data[25] <= mem[0][25].DB_MAX_OUTPUT_PORT_TYPE +out_data[26] <= mem[0][26].DB_MAX_OUTPUT_PORT_TYPE +out_data[27] <= mem[0][27].DB_MAX_OUTPUT_PORT_TYPE +out_data[28] <= mem[0][28].DB_MAX_OUTPUT_PORT_TYPE +out_data[29] <= mem[0][29].DB_MAX_OUTPUT_PORT_TYPE +out_data[30] <= mem[0][30].DB_MAX_OUTPUT_PORT_TYPE +out_data[31] <= mem[0][31].DB_MAX_OUTPUT_PORT_TYPE +out_data[32] <= mem[0][32].DB_MAX_OUTPUT_PORT_TYPE +out_data[33] <= mem[0][33].DB_MAX_OUTPUT_PORT_TYPE +out_data[34] <= mem[0][34].DB_MAX_OUTPUT_PORT_TYPE +out_data[35] <= mem[0][35].DB_MAX_OUTPUT_PORT_TYPE +out_data[36] <= mem[0][36].DB_MAX_OUTPUT_PORT_TYPE +out_data[37] <= mem[0][37].DB_MAX_OUTPUT_PORT_TYPE +out_data[38] <= mem[0][38].DB_MAX_OUTPUT_PORT_TYPE +out_data[39] <= mem[0][39].DB_MAX_OUTPUT_PORT_TYPE +out_data[40] <= mem[0][40].DB_MAX_OUTPUT_PORT_TYPE +out_data[41] <= mem[0][41].DB_MAX_OUTPUT_PORT_TYPE +out_data[42] <= mem[0][42].DB_MAX_OUTPUT_PORT_TYPE +out_data[43] <= mem[0][43].DB_MAX_OUTPUT_PORT_TYPE +out_data[44] <= mem[0][44].DB_MAX_OUTPUT_PORT_TYPE +out_data[45] <= mem[0][45].DB_MAX_OUTPUT_PORT_TYPE +out_data[46] <= mem[0][46].DB_MAX_OUTPUT_PORT_TYPE +out_data[47] <= mem[0][47].DB_MAX_OUTPUT_PORT_TYPE +out_data[48] <= mem[0][48].DB_MAX_OUTPUT_PORT_TYPE +out_data[49] <= mem[0][49].DB_MAX_OUTPUT_PORT_TYPE +out_data[50] <= mem[0][50].DB_MAX_OUTPUT_PORT_TYPE +out_data[51] <= mem[0][51].DB_MAX_OUTPUT_PORT_TYPE +out_data[52] <= mem[0][52].DB_MAX_OUTPUT_PORT_TYPE +out_data[53] <= mem[0][53].DB_MAX_OUTPUT_PORT_TYPE +out_data[54] <= mem[0][54].DB_MAX_OUTPUT_PORT_TYPE +out_data[55] <= mem[0][55].DB_MAX_OUTPUT_PORT_TYPE +out_data[56] <= mem[0][56].DB_MAX_OUTPUT_PORT_TYPE +out_data[57] <= mem[0][57].DB_MAX_OUTPUT_PORT_TYPE +out_data[58] <= mem[0][58].DB_MAX_OUTPUT_PORT_TYPE +out_data[59] <= mem[0][59].DB_MAX_OUTPUT_PORT_TYPE +out_data[60] <= mem[0][60].DB_MAX_OUTPUT_PORT_TYPE +out_data[61] <= mem[0][61].DB_MAX_OUTPUT_PORT_TYPE +out_data[62] <= mem[0][62].DB_MAX_OUTPUT_PORT_TYPE +out_data[63] <= mem[0][63].DB_MAX_OUTPUT_PORT_TYPE +out_data[64] <= mem[0][64].DB_MAX_OUTPUT_PORT_TYPE +out_data[65] <= mem[0][65].DB_MAX_OUTPUT_PORT_TYPE +out_data[66] <= mem[0][66].DB_MAX_OUTPUT_PORT_TYPE +out_data[67] <= mem[0][67].DB_MAX_OUTPUT_PORT_TYPE +out_data[68] <= mem[0][68].DB_MAX_OUTPUT_PORT_TYPE +out_data[69] <= mem[0][69].DB_MAX_OUTPUT_PORT_TYPE +out_data[70] <= mem[0][70].DB_MAX_OUTPUT_PORT_TYPE +out_data[71] <= mem[0][71].DB_MAX_OUTPUT_PORT_TYPE +out_data[72] <= mem[0][72].DB_MAX_OUTPUT_PORT_TYPE +out_data[73] <= mem[0][73].DB_MAX_OUTPUT_PORT_TYPE +out_data[74] <= mem[0][74].DB_MAX_OUTPUT_PORT_TYPE +out_data[75] <= mem[0][75].DB_MAX_OUTPUT_PORT_TYPE +out_data[76] <= mem[0][76].DB_MAX_OUTPUT_PORT_TYPE +out_data[77] <= mem[0][77].DB_MAX_OUTPUT_PORT_TYPE +out_data[78] <= mem[0][78].DB_MAX_OUTPUT_PORT_TYPE +out_data[79] <= mem[0][79].DB_MAX_OUTPUT_PORT_TYPE +out_data[80] <= mem[0][80].DB_MAX_OUTPUT_PORT_TYPE +out_data[81] <= mem[0][81].DB_MAX_OUTPUT_PORT_TYPE +out_data[82] <= mem[0][82].DB_MAX_OUTPUT_PORT_TYPE +out_data[83] <= mem[0][83].DB_MAX_OUTPUT_PORT_TYPE +out_data[84] <= mem[0][84].DB_MAX_OUTPUT_PORT_TYPE +out_data[85] <= mem[0][85].DB_MAX_OUTPUT_PORT_TYPE +out_data[86] <= mem[0][86].DB_MAX_OUTPUT_PORT_TYPE +out_data[87] <= mem[0][87].DB_MAX_OUTPUT_PORT_TYPE +out_data[88] <= mem[0][88].DB_MAX_OUTPUT_PORT_TYPE +out_data[89] <= mem[0][89].DB_MAX_OUTPUT_PORT_TYPE +out_data[90] <= mem[0][90].DB_MAX_OUTPUT_PORT_TYPE +out_data[91] <= mem[0][91].DB_MAX_OUTPUT_PORT_TYPE +out_data[92] <= mem[0][92].DB_MAX_OUTPUT_PORT_TYPE +out_data[93] <= mem[0][93].DB_MAX_OUTPUT_PORT_TYPE +out_data[94] <= mem[0][94].DB_MAX_OUTPUT_PORT_TYPE +out_data[95] <= mem[0][95].DB_MAX_OUTPUT_PORT_TYPE +out_data[96] <= mem[0][96].DB_MAX_OUTPUT_PORT_TYPE +out_data[97] <= mem[0][97].DB_MAX_OUTPUT_PORT_TYPE +out_data[98] <= mem[0][98].DB_MAX_OUTPUT_PORT_TYPE +out_data[99] <= mem[0][99].DB_MAX_OUTPUT_PORT_TYPE +out_data[100] <= mem[0][100].DB_MAX_OUTPUT_PORT_TYPE +out_data[101] <= mem[0][101].DB_MAX_OUTPUT_PORT_TYPE +out_valid <= mem_used[0].DB_MAX_OUTPUT_PORT_TYPE +out_startofpacket <= mem[0][103].DB_MAX_OUTPUT_PORT_TYPE +out_endofpacket <= mem[0][102].DB_MAX_OUTPUT_PORT_TYPE +out_empty[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE +out_error[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE +out_channel[0] <= in_channel[0].DB_MAX_OUTPUT_PORT_TYPE +out_ready => internal_out_ready.IN1 +csr_address[0] => ~NO_FANOUT~ +csr_address[1] => ~NO_FANOUT~ +csr_write => ~NO_FANOUT~ +csr_read => csr_readdata[0]~reg0.ENA +csr_read => csr_readdata[31]~reg0.ENA +csr_read => csr_readdata[30]~reg0.ENA +csr_read => csr_readdata[29]~reg0.ENA +csr_read => csr_readdata[28]~reg0.ENA +csr_read => csr_readdata[27]~reg0.ENA +csr_read => csr_readdata[26]~reg0.ENA +csr_read => csr_readdata[25]~reg0.ENA +csr_read => csr_readdata[24]~reg0.ENA +csr_read => csr_readdata[23]~reg0.ENA +csr_read => csr_readdata[22]~reg0.ENA +csr_read => csr_readdata[21]~reg0.ENA +csr_read => csr_readdata[20]~reg0.ENA +csr_read => csr_readdata[19]~reg0.ENA +csr_read => csr_readdata[18]~reg0.ENA +csr_read => csr_readdata[17]~reg0.ENA +csr_read => csr_readdata[16]~reg0.ENA +csr_read => csr_readdata[15]~reg0.ENA +csr_read => csr_readdata[14]~reg0.ENA +csr_read => csr_readdata[13]~reg0.ENA +csr_read => csr_readdata[12]~reg0.ENA +csr_read => csr_readdata[11]~reg0.ENA +csr_read => csr_readdata[10]~reg0.ENA +csr_read => csr_readdata[9]~reg0.ENA +csr_read => csr_readdata[8]~reg0.ENA +csr_read => csr_readdata[7]~reg0.ENA +csr_read => csr_readdata[6]~reg0.ENA +csr_read => csr_readdata[5]~reg0.ENA +csr_read => csr_readdata[4]~reg0.ENA +csr_read => csr_readdata[3]~reg0.ENA +csr_read => csr_readdata[2]~reg0.ENA +csr_read => csr_readdata[1]~reg0.ENA +csr_writedata[0] => ~NO_FANOUT~ +csr_writedata[1] => ~NO_FANOUT~ +csr_writedata[2] => ~NO_FANOUT~ +csr_writedata[3] => ~NO_FANOUT~ +csr_writedata[4] => ~NO_FANOUT~ +csr_writedata[5] => ~NO_FANOUT~ +csr_writedata[6] => ~NO_FANOUT~ +csr_writedata[7] => ~NO_FANOUT~ +csr_writedata[8] => ~NO_FANOUT~ +csr_writedata[9] => ~NO_FANOUT~ +csr_writedata[10] => ~NO_FANOUT~ +csr_writedata[11] => ~NO_FANOUT~ +csr_writedata[12] => ~NO_FANOUT~ +csr_writedata[13] => ~NO_FANOUT~ +csr_writedata[14] => ~NO_FANOUT~ +csr_writedata[15] => ~NO_FANOUT~ +csr_writedata[16] => ~NO_FANOUT~ +csr_writedata[17] => ~NO_FANOUT~ +csr_writedata[18] => ~NO_FANOUT~ +csr_writedata[19] => ~NO_FANOUT~ +csr_writedata[20] => ~NO_FANOUT~ +csr_writedata[21] => ~NO_FANOUT~ +csr_writedata[22] => ~NO_FANOUT~ +csr_writedata[23] => ~NO_FANOUT~ +csr_writedata[24] => ~NO_FANOUT~ +csr_writedata[25] => ~NO_FANOUT~ +csr_writedata[26] => ~NO_FANOUT~ +csr_writedata[27] => ~NO_FANOUT~ +csr_writedata[28] => ~NO_FANOUT~ +csr_writedata[29] => ~NO_FANOUT~ +csr_writedata[30] => ~NO_FANOUT~ +csr_writedata[31] => ~NO_FANOUT~ +csr_readdata[0] <= csr_readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[1] <= csr_readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[2] <= csr_readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[3] <= csr_readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[4] <= csr_readdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[5] <= csr_readdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[6] <= csr_readdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[7] <= csr_readdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[8] <= csr_readdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[9] <= csr_readdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[10] <= csr_readdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[11] <= csr_readdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[12] <= csr_readdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[13] <= csr_readdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[14] <= csr_readdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[15] <= csr_readdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[16] <= csr_readdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[17] <= csr_readdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[18] <= csr_readdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[19] <= csr_readdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[20] <= csr_readdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[21] <= csr_readdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[22] <= csr_readdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[23] <= csr_readdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[24] <= csr_readdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[25] <= csr_readdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[26] <= csr_readdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[27] <= csr_readdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[28] <= csr_readdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[29] <= csr_readdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[30] <= csr_readdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[31] <= csr_readdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE +almost_full_data <= +almost_empty_data <= + + +|de0_nano_system|system:inst_cpu|altera_merlin_slave_agent:pio_motor_rst_s1_translator_avalon_universal_slave_0_agent +clk => clk.IN1 +reset => reset.IN1 +m0_address[0] <= +m0_address[1] <= +m0_address[2] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE +m0_address[3] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE +m0_address[4] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE +m0_address[5] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE +m0_address[6] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE +m0_address[7] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE +m0_address[8] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE +m0_address[9] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE +m0_address[10] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE +m0_address[11] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE +m0_address[12] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE +m0_address[13] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE +m0_address[14] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE +m0_address[15] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE +m0_address[16] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE +m0_address[17] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE +m0_address[18] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE +m0_address[19] <= cp_data[55].DB_MAX_OUTPUT_PORT_TYPE +m0_address[20] <= cp_data[56].DB_MAX_OUTPUT_PORT_TYPE +m0_address[21] <= cp_data[57].DB_MAX_OUTPUT_PORT_TYPE +m0_address[22] <= cp_data[58].DB_MAX_OUTPUT_PORT_TYPE +m0_address[23] <= cp_data[59].DB_MAX_OUTPUT_PORT_TYPE +m0_address[24] <= cp_data[60].DB_MAX_OUTPUT_PORT_TYPE +m0_address[25] <= cp_data[61].DB_MAX_OUTPUT_PORT_TYPE +m0_burstcount[0] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE +m0_burstcount[1] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE +m0_burstcount[2] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[0] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[1] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[2] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[3] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE +m0_read <= m0_read.DB_MAX_OUTPUT_PORT_TYPE +m0_readdata[0] => rdata_fifo_src_data[0].DATAIN +m0_readdata[1] => rdata_fifo_src_data[1].DATAIN +m0_readdata[2] => rdata_fifo_src_data[2].DATAIN +m0_readdata[3] => rdata_fifo_src_data[3].DATAIN +m0_readdata[4] => rdata_fifo_src_data[4].DATAIN +m0_readdata[5] => rdata_fifo_src_data[5].DATAIN +m0_readdata[6] => rdata_fifo_src_data[6].DATAIN +m0_readdata[7] => rdata_fifo_src_data[7].DATAIN +m0_readdata[8] => rdata_fifo_src_data[8].DATAIN +m0_readdata[9] => rdata_fifo_src_data[9].DATAIN +m0_readdata[10] => rdata_fifo_src_data[10].DATAIN +m0_readdata[11] => rdata_fifo_src_data[11].DATAIN +m0_readdata[12] => rdata_fifo_src_data[12].DATAIN +m0_readdata[13] => rdata_fifo_src_data[13].DATAIN +m0_readdata[14] => rdata_fifo_src_data[14].DATAIN +m0_readdata[15] => rdata_fifo_src_data[15].DATAIN +m0_readdata[16] => rdata_fifo_src_data[16].DATAIN +m0_readdata[17] => rdata_fifo_src_data[17].DATAIN +m0_readdata[18] => rdata_fifo_src_data[18].DATAIN +m0_readdata[19] => rdata_fifo_src_data[19].DATAIN +m0_readdata[20] => rdata_fifo_src_data[20].DATAIN +m0_readdata[21] => rdata_fifo_src_data[21].DATAIN +m0_readdata[22] => rdata_fifo_src_data[22].DATAIN +m0_readdata[23] => rdata_fifo_src_data[23].DATAIN +m0_readdata[24] => rdata_fifo_src_data[24].DATAIN +m0_readdata[25] => rdata_fifo_src_data[25].DATAIN +m0_readdata[26] => rdata_fifo_src_data[26].DATAIN +m0_readdata[27] => rdata_fifo_src_data[27].DATAIN +m0_readdata[28] => rdata_fifo_src_data[28].DATAIN +m0_readdata[29] => rdata_fifo_src_data[29].DATAIN +m0_readdata[30] => rdata_fifo_src_data[30].DATAIN +m0_readdata[31] => rdata_fifo_src_data[31].DATAIN +m0_waitrequest => cp_ready.IN0 +m0_write <= m0_write.DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[0] <= cp_data[0].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[1] <= cp_data[1].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[2] <= cp_data[2].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[3] <= cp_data[3].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[4] <= cp_data[4].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[5] <= cp_data[5].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[6] <= cp_data[6].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[7] <= cp_data[7].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[8] <= cp_data[8].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[9] <= cp_data[9].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[10] <= cp_data[10].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[11] <= cp_data[11].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[12] <= cp_data[12].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[13] <= cp_data[13].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[14] <= cp_data[14].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[15] <= cp_data[15].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[16] <= cp_data[16].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[17] <= cp_data[17].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[18] <= cp_data[18].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[19] <= cp_data[19].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[20] <= cp_data[20].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[21] <= cp_data[21].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[22] <= cp_data[22].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[23] <= cp_data[23].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[24] <= cp_data[24].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[25] <= cp_data[25].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[26] <= cp_data[26].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[27] <= cp_data[27].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[28] <= cp_data[28].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[29] <= cp_data[29].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[30] <= cp_data[30].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[31] <= cp_data[31].DB_MAX_OUTPUT_PORT_TYPE +m0_readdatavalid => rdata_fifo_src_valid.DATAIN +m0_debugaccess <= cp_data[92].DB_MAX_OUTPUT_PORT_TYPE +m0_lock <= m0_lock.DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[0] <= +rf_source_data[1] <= +rf_source_data[2] <= +rf_source_data[3] <= +rf_source_data[4] <= +rf_source_data[5] <= +rf_source_data[6] <= +rf_source_data[7] <= +rf_source_data[8] <= +rf_source_data[9] <= +rf_source_data[10] <= +rf_source_data[11] <= +rf_source_data[12] <= +rf_source_data[13] <= +rf_source_data[14] <= +rf_source_data[15] <= +rf_source_data[16] <= +rf_source_data[17] <= +rf_source_data[18] <= +rf_source_data[19] <= +rf_source_data[20] <= +rf_source_data[21] <= +rf_source_data[22] <= +rf_source_data[23] <= +rf_source_data[24] <= +rf_source_data[25] <= +rf_source_data[26] <= +rf_source_data[27] <= +rf_source_data[28] <= +rf_source_data[29] <= +rf_source_data[30] <= +rf_source_data[31] <= +rf_source_data[32] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[33] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[34] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[35] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[36] <= cp_data[36].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[37] <= cp_data[37].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[38] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[39] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[40] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[41] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[42] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[43] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[44] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[45] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[46] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[47] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[48] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[49] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[50] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[51] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[52] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[53] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[54] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[55] <= cp_data[55].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[56] <= cp_data[56].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[57] <= cp_data[57].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[58] <= cp_data[58].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[59] <= cp_data[59].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[60] <= cp_data[60].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[61] <= cp_data[61].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[62] <= cp_data[62].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[63] <= cp_data[63].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[64] <= cp_data[64].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[65] <= cp_data[65].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[66] <= cp_data[66].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[67] <= cp_data[67].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[68] <= cp_data[68].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[69] <= cp_data[69].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[70] <= cp_data[70].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[71] <= cp_data[71].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[72] <= cp_data[72].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[73] <= cp_data[73].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[74] <= cp_data[74].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[75] <= cp_data[75].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[76] <= cp_data[76].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[77] <= cp_data[77].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[78] <= cp_data[78].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[79] <= cp_data[79].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[80] <= cp_data[80].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[81] <= cp_data[81].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[82] <= cp_data[82].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[83] <= cp_data[83].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[84] <= cp_data[84].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[85] <= cp_data[85].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[86] <= cp_data[86].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[87] <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[88] <= cp_data[88].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[89] <= cp_data[89].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[90] <= cp_data[90].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[91] <= cp_data[91].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[92] <= cp_data[92].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[93] <= +rf_source_data[94] <= +rf_source_data[95] <= cp_data[95].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[96] <= cp_data[96].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[97] <= cp_data[97].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[98] <= cp_data[98].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[99] <= cp_data[99].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[100] <= cp_data[100].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[101] <= nonposted_write_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +rf_source_valid <= rf_source_valid.DB_MAX_OUTPUT_PORT_TYPE +rf_source_startofpacket <= cp_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +rf_source_endofpacket <= cp_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +rf_source_ready => cp_ready.IN1 +rf_source_ready => m0_write.IN1 +rf_source_ready => m0_lock.IN1 +rf_source_ready => rf_source_valid.IN1 +rf_source_ready => m0_read.IN1 +rf_sink_data[0] => ~NO_FANOUT~ +rf_sink_data[1] => ~NO_FANOUT~ +rf_sink_data[2] => ~NO_FANOUT~ +rf_sink_data[3] => ~NO_FANOUT~ +rf_sink_data[4] => ~NO_FANOUT~ +rf_sink_data[5] => ~NO_FANOUT~ +rf_sink_data[6] => ~NO_FANOUT~ +rf_sink_data[7] => ~NO_FANOUT~ +rf_sink_data[8] => ~NO_FANOUT~ +rf_sink_data[9] => ~NO_FANOUT~ +rf_sink_data[10] => ~NO_FANOUT~ +rf_sink_data[11] => ~NO_FANOUT~ +rf_sink_data[12] => ~NO_FANOUT~ +rf_sink_data[13] => ~NO_FANOUT~ +rf_sink_data[14] => ~NO_FANOUT~ +rf_sink_data[15] => ~NO_FANOUT~ +rf_sink_data[16] => ~NO_FANOUT~ +rf_sink_data[17] => ~NO_FANOUT~ +rf_sink_data[18] => ~NO_FANOUT~ +rf_sink_data[19] => ~NO_FANOUT~ +rf_sink_data[20] => ~NO_FANOUT~ +rf_sink_data[21] => ~NO_FANOUT~ +rf_sink_data[22] => ~NO_FANOUT~ +rf_sink_data[23] => ~NO_FANOUT~ +rf_sink_data[24] => ~NO_FANOUT~ +rf_sink_data[25] => ~NO_FANOUT~ +rf_sink_data[26] => ~NO_FANOUT~ +rf_sink_data[27] => ~NO_FANOUT~ +rf_sink_data[28] => ~NO_FANOUT~ +rf_sink_data[29] => ~NO_FANOUT~ +rf_sink_data[30] => ~NO_FANOUT~ +rf_sink_data[31] => ~NO_FANOUT~ +rf_sink_data[32] => rp_data[32].DATAIN +rf_sink_data[33] => rp_data[33].DATAIN +rf_sink_data[34] => rp_data[34].DATAIN +rf_sink_data[35] => rp_data[35].DATAIN +rf_sink_data[36] => rf_sink_addr[0].IN1 +rf_sink_data[37] => rf_sink_addr[1].IN1 +rf_sink_data[38] => rf_sink_addr[2].IN1 +rf_sink_data[39] => rf_sink_addr[3].IN1 +rf_sink_data[40] => rf_sink_addr[4].IN1 +rf_sink_data[41] => rf_sink_addr[5].IN1 +rf_sink_data[42] => rf_sink_addr[6].IN1 +rf_sink_data[43] => rf_sink_addr[7].IN1 +rf_sink_data[44] => rf_sink_addr[8].IN1 +rf_sink_data[45] => rf_sink_addr[9].IN1 +rf_sink_data[46] => rf_sink_addr[10].IN1 +rf_sink_data[47] => rf_sink_addr[11].IN1 +rf_sink_data[48] => rf_sink_addr[12].IN1 +rf_sink_data[49] => rf_sink_addr[13].IN1 +rf_sink_data[50] => rf_sink_addr[14].IN1 +rf_sink_data[51] => rf_sink_addr[15].IN1 +rf_sink_data[52] => rf_sink_addr[16].IN1 +rf_sink_data[53] => rf_sink_addr[17].IN1 +rf_sink_data[54] => rf_sink_addr[18].IN1 +rf_sink_data[55] => rf_sink_addr[19].IN1 +rf_sink_data[56] => rf_sink_addr[20].IN1 +rf_sink_data[57] => rf_sink_addr[21].IN1 +rf_sink_data[58] => rf_sink_addr[22].IN1 +rf_sink_data[59] => rf_sink_addr[23].IN1 +rf_sink_data[60] => rf_sink_addr[24].IN1 +rf_sink_data[61] => rf_sink_addr[25].IN1 +rf_sink_data[62] => rf_sink_compressed.IN1 +rf_sink_data[63] => rp_data[63].DATAIN +rf_sink_data[64] => comb.OUTPUTSELECT +rf_sink_data[64] => rp_data[64].DATAIN +rf_sink_data[65] => rp_data.IN0 +rf_sink_data[66] => rp_data[66].DATAIN +rf_sink_data[67] => rp_data[67].DATAIN +rf_sink_data[68] => rf_sink_byte_cnt[0].IN1 +rf_sink_data[69] => rf_sink_byte_cnt[1].IN1 +rf_sink_data[70] => rf_sink_byte_cnt[2].IN1 +rf_sink_data[71] => rf_sink_burstwrap[0].IN1 +rf_sink_data[72] => rf_sink_burstwrap[1].IN1 +rf_sink_data[73] => rf_sink_burstwrap[2].IN1 +rf_sink_data[74] => rf_sink_burstsize[0].IN1 +rf_sink_data[75] => rf_sink_burstsize[1].IN1 +rf_sink_data[76] => rf_sink_burstsize[2].IN1 +rf_sink_data[77] => rp_data[77].DATAIN +rf_sink_data[78] => rp_data[78].DATAIN +rf_sink_data[79] => rp_data[79].DATAIN +rf_sink_data[80] => rp_data[80].DATAIN +rf_sink_data[81] => rp_data[81].DATAIN +rf_sink_data[82] => rp_data[82].DATAIN +rf_sink_data[83] => rp_data[87].DATAIN +rf_sink_data[84] => rp_data[88].DATAIN +rf_sink_data[85] => rp_data[89].DATAIN +rf_sink_data[86] => rp_data[90].DATAIN +rf_sink_data[87] => rp_data[83].DATAIN +rf_sink_data[88] => rp_data[84].DATAIN +rf_sink_data[89] => rp_data[85].DATAIN +rf_sink_data[90] => rp_data[86].DATAIN +rf_sink_data[91] => rp_data[91].DATAIN +rf_sink_data[92] => rp_data[92].DATAIN +rf_sink_data[93] => rp_data[93].DATAIN +rf_sink_data[94] => rp_data[94].DATAIN +rf_sink_data[95] => rp_data[95].DATAIN +rf_sink_data[96] => rp_data[96].DATAIN +rf_sink_data[97] => rp_data[97].DATAIN +rf_sink_data[98] => rp_data[98].DATAIN +rf_sink_data[99] => ~NO_FANOUT~ +rf_sink_data[100] => ~NO_FANOUT~ +rf_sink_data[101] => rdata_fifo_sink_ready.IN0 +rf_sink_data[101] => comb.IN0 +rf_sink_valid => rdata_fifo_sink_ready.IN1 +rf_sink_valid => comb.IN1 +rf_sink_startofpacket => comb.DATAA +rf_sink_endofpacket => rf_sink_endofpacket.IN1 +rf_sink_ready <= altera_merlin_burst_uncompressor:uncompressor.sink_ready +rdata_fifo_src_data[0] <= m0_readdata[0].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[1] <= m0_readdata[1].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[2] <= m0_readdata[2].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[3] <= m0_readdata[3].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[4] <= m0_readdata[4].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[5] <= m0_readdata[5].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[6] <= m0_readdata[6].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[7] <= m0_readdata[7].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[8] <= m0_readdata[8].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[9] <= m0_readdata[9].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[10] <= m0_readdata[10].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[11] <= m0_readdata[11].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[12] <= m0_readdata[12].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[13] <= m0_readdata[13].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[14] <= m0_readdata[14].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[15] <= m0_readdata[15].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[16] <= m0_readdata[16].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[17] <= m0_readdata[17].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[18] <= m0_readdata[18].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[19] <= m0_readdata[19].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[20] <= m0_readdata[20].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[21] <= m0_readdata[21].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[22] <= m0_readdata[22].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[23] <= m0_readdata[23].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[24] <= m0_readdata[24].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[25] <= m0_readdata[25].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[26] <= m0_readdata[26].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[27] <= m0_readdata[27].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[28] <= m0_readdata[28].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[29] <= m0_readdata[29].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[30] <= m0_readdata[30].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[31] <= m0_readdata[31].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_valid <= m0_readdatavalid.DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_ready => ~NO_FANOUT~ +rdata_fifo_sink_data[0] => rp_data[0].DATAIN +rdata_fifo_sink_data[1] => rp_data[1].DATAIN +rdata_fifo_sink_data[2] => rp_data[2].DATAIN +rdata_fifo_sink_data[3] => rp_data[3].DATAIN +rdata_fifo_sink_data[4] => rp_data[4].DATAIN +rdata_fifo_sink_data[5] => rp_data[5].DATAIN +rdata_fifo_sink_data[6] => rp_data[6].DATAIN +rdata_fifo_sink_data[7] => rp_data[7].DATAIN +rdata_fifo_sink_data[8] => rp_data[8].DATAIN +rdata_fifo_sink_data[9] => rp_data[9].DATAIN +rdata_fifo_sink_data[10] => rp_data[10].DATAIN +rdata_fifo_sink_data[11] => rp_data[11].DATAIN +rdata_fifo_sink_data[12] => rp_data[12].DATAIN +rdata_fifo_sink_data[13] => rp_data[13].DATAIN +rdata_fifo_sink_data[14] => rp_data[14].DATAIN +rdata_fifo_sink_data[15] => rp_data[15].DATAIN +rdata_fifo_sink_data[16] => rp_data[16].DATAIN +rdata_fifo_sink_data[17] => rp_data[17].DATAIN +rdata_fifo_sink_data[18] => rp_data[18].DATAIN +rdata_fifo_sink_data[19] => rp_data[19].DATAIN +rdata_fifo_sink_data[20] => rp_data[20].DATAIN +rdata_fifo_sink_data[21] => rp_data[21].DATAIN +rdata_fifo_sink_data[22] => rp_data[22].DATAIN +rdata_fifo_sink_data[23] => rp_data[23].DATAIN +rdata_fifo_sink_data[24] => rp_data[24].DATAIN +rdata_fifo_sink_data[25] => rp_data[25].DATAIN +rdata_fifo_sink_data[26] => rp_data[26].DATAIN +rdata_fifo_sink_data[27] => rp_data[27].DATAIN +rdata_fifo_sink_data[28] => rp_data[28].DATAIN +rdata_fifo_sink_data[29] => rp_data[29].DATAIN +rdata_fifo_sink_data[30] => rp_data[30].DATAIN +rdata_fifo_sink_data[31] => rp_data[31].DATAIN +rdata_fifo_sink_valid => rp_valid.IN1 +rdata_fifo_sink_valid => rdata_fifo_sink_ready.IN0 +rdata_fifo_sink_valid => comb.IN1 +rdata_fifo_sink_ready <= rdata_fifo_sink_ready.DB_MAX_OUTPUT_PORT_TYPE +cp_ready <= cp_ready.DB_MAX_OUTPUT_PORT_TYPE +cp_valid => local_lock.IN0 +cp_valid => local_write.IN0 +cp_valid => local_read.IN0 +cp_valid => local_compressed_read.IN0 +cp_data[0] => m0_writedata[0].DATAIN +cp_data[1] => m0_writedata[1].DATAIN +cp_data[2] => m0_writedata[2].DATAIN +cp_data[3] => m0_writedata[3].DATAIN +cp_data[4] => m0_writedata[4].DATAIN +cp_data[5] => m0_writedata[5].DATAIN +cp_data[6] => m0_writedata[6].DATAIN +cp_data[7] => m0_writedata[7].DATAIN +cp_data[8] => m0_writedata[8].DATAIN +cp_data[9] => m0_writedata[9].DATAIN +cp_data[10] => m0_writedata[10].DATAIN +cp_data[11] => m0_writedata[11].DATAIN +cp_data[12] => m0_writedata[12].DATAIN +cp_data[13] => m0_writedata[13].DATAIN +cp_data[14] => m0_writedata[14].DATAIN +cp_data[15] => m0_writedata[15].DATAIN +cp_data[16] => m0_writedata[16].DATAIN +cp_data[17] => m0_writedata[17].DATAIN +cp_data[18] => m0_writedata[18].DATAIN +cp_data[19] => m0_writedata[19].DATAIN +cp_data[20] => m0_writedata[20].DATAIN +cp_data[21] => m0_writedata[21].DATAIN +cp_data[22] => m0_writedata[22].DATAIN +cp_data[23] => m0_writedata[23].DATAIN +cp_data[24] => m0_writedata[24].DATAIN +cp_data[25] => m0_writedata[25].DATAIN +cp_data[26] => m0_writedata[26].DATAIN +cp_data[27] => m0_writedata[27].DATAIN +cp_data[28] => m0_writedata[28].DATAIN +cp_data[29] => m0_writedata[29].DATAIN +cp_data[30] => m0_writedata[30].DATAIN +cp_data[31] => m0_writedata[31].DATAIN +cp_data[32] => rf_source_data[32].DATAIN +cp_data[32] => m0_byteenable[0].DATAIN +cp_data[33] => rf_source_data[33].DATAIN +cp_data[33] => m0_byteenable[1].DATAIN +cp_data[34] => rf_source_data[34].DATAIN +cp_data[34] => m0_byteenable[2].DATAIN +cp_data[35] => rf_source_data[35].DATAIN +cp_data[35] => m0_byteenable[3].DATAIN +cp_data[36] => rf_source_data[36].DATAIN +cp_data[37] => rf_source_data[37].DATAIN +cp_data[38] => rf_source_data[38].DATAIN +cp_data[38] => m0_address[2].DATAIN +cp_data[39] => rf_source_data[39].DATAIN +cp_data[39] => m0_address[3].DATAIN +cp_data[40] => rf_source_data[40].DATAIN +cp_data[40] => m0_address[4].DATAIN +cp_data[41] => rf_source_data[41].DATAIN +cp_data[41] => m0_address[5].DATAIN +cp_data[42] => rf_source_data[42].DATAIN +cp_data[42] => m0_address[6].DATAIN +cp_data[43] => rf_source_data[43].DATAIN +cp_data[43] => m0_address[7].DATAIN +cp_data[44] => rf_source_data[44].DATAIN +cp_data[44] => m0_address[8].DATAIN +cp_data[45] => rf_source_data[45].DATAIN +cp_data[45] => m0_address[9].DATAIN +cp_data[46] => rf_source_data[46].DATAIN +cp_data[46] => m0_address[10].DATAIN +cp_data[47] => rf_source_data[47].DATAIN +cp_data[47] => m0_address[11].DATAIN +cp_data[48] => rf_source_data[48].DATAIN +cp_data[48] => m0_address[12].DATAIN +cp_data[49] => rf_source_data[49].DATAIN +cp_data[49] => m0_address[13].DATAIN +cp_data[50] => rf_source_data[50].DATAIN +cp_data[50] => m0_address[14].DATAIN +cp_data[51] => rf_source_data[51].DATAIN +cp_data[51] => m0_address[15].DATAIN +cp_data[52] => rf_source_data[52].DATAIN +cp_data[52] => m0_address[16].DATAIN +cp_data[53] => rf_source_data[53].DATAIN +cp_data[53] => m0_address[17].DATAIN +cp_data[54] => rf_source_data[54].DATAIN +cp_data[54] => m0_address[18].DATAIN +cp_data[55] => rf_source_data[55].DATAIN +cp_data[55] => m0_address[19].DATAIN +cp_data[56] => rf_source_data[56].DATAIN +cp_data[56] => m0_address[20].DATAIN +cp_data[57] => rf_source_data[57].DATAIN +cp_data[57] => m0_address[21].DATAIN +cp_data[58] => rf_source_data[58].DATAIN +cp_data[58] => m0_address[22].DATAIN +cp_data[59] => rf_source_data[59].DATAIN +cp_data[59] => m0_address[23].DATAIN +cp_data[60] => rf_source_data[60].DATAIN +cp_data[60] => m0_address[24].DATAIN +cp_data[61] => rf_source_data[61].DATAIN +cp_data[61] => m0_address[25].DATAIN +cp_data[62] => local_compressed_read.IN1 +cp_data[62] => rf_source_data[62].DATAIN +cp_data[63] => rf_source_data[63].DATAIN +cp_data[63] => comb.IN1 +cp_data[64] => local_write.IN1 +cp_data[64] => rf_source_data[64].DATAIN +cp_data[65] => local_read.IN1 +cp_data[65] => rf_source_data[65].DATAIN +cp_data[66] => local_lock.IN1 +cp_data[66] => rf_source_data[66].DATAIN +cp_data[67] => rf_source_data[67].DATAIN +cp_data[68] => m0_burstcount.DATAA +cp_data[68] => rf_source_data[68].DATAIN +cp_data[69] => m0_burstcount.DATAA +cp_data[69] => rf_source_data[69].DATAIN +cp_data[70] => m0_burstcount.DATAA +cp_data[70] => rf_source_data[70].DATAIN +cp_data[71] => rf_source_data[71].DATAIN +cp_data[72] => rf_source_data[72].DATAIN +cp_data[73] => rf_source_data[73].DATAIN +cp_data[74] => rf_source_data[74].DATAIN +cp_data[75] => rf_source_data[75].DATAIN +cp_data[76] => rf_source_data[76].DATAIN +cp_data[77] => rf_source_data[77].DATAIN +cp_data[78] => rf_source_data[78].DATAIN +cp_data[79] => rf_source_data[79].DATAIN +cp_data[80] => rf_source_data[80].DATAIN +cp_data[81] => rf_source_data[81].DATAIN +cp_data[82] => rf_source_data[82].DATAIN +cp_data[83] => rf_source_data[83].DATAIN +cp_data[84] => rf_source_data[84].DATAIN +cp_data[85] => rf_source_data[85].DATAIN +cp_data[86] => rf_source_data[86].DATAIN +cp_data[87] => rf_source_data[87].DATAIN +cp_data[88] => rf_source_data[88].DATAIN +cp_data[89] => rf_source_data[89].DATAIN +cp_data[90] => rf_source_data[90].DATAIN +cp_data[91] => rf_source_data[91].DATAIN +cp_data[92] => rf_source_data[92].DATAIN +cp_data[92] => m0_debugaccess.DATAIN +cp_data[93] => ~NO_FANOUT~ +cp_data[94] => ~NO_FANOUT~ +cp_data[95] => rf_source_data[95].DATAIN +cp_data[96] => rf_source_data[96].DATAIN +cp_data[97] => rf_source_data[97].DATAIN +cp_data[98] => rf_source_data[98].DATAIN +cp_data[99] => rf_source_data[99].DATAIN +cp_data[100] => rf_source_data[100].DATAIN +cp_channel[0] => ~NO_FANOUT~ +cp_channel[1] => ~NO_FANOUT~ +cp_channel[2] => ~NO_FANOUT~ +cp_channel[3] => ~NO_FANOUT~ +cp_channel[4] => ~NO_FANOUT~ +cp_channel[5] => ~NO_FANOUT~ +cp_channel[6] => ~NO_FANOUT~ +cp_channel[7] => ~NO_FANOUT~ +cp_channel[8] => ~NO_FANOUT~ +cp_channel[9] => ~NO_FANOUT~ +cp_channel[10] => ~NO_FANOUT~ +cp_startofpacket => rf_source_startofpacket.DATAIN +cp_endofpacket => nonposted_write_endofpacket.IN1 +cp_endofpacket => rf_source_endofpacket.DATAIN +rp_ready => rp_ready.IN1 +rp_valid <= rp_valid.DB_MAX_OUTPUT_PORT_TYPE +rp_data[0] <= rdata_fifo_sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +rp_data[1] <= rdata_fifo_sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +rp_data[2] <= rdata_fifo_sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +rp_data[3] <= rdata_fifo_sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +rp_data[4] <= rdata_fifo_sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +rp_data[5] <= rdata_fifo_sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +rp_data[6] <= rdata_fifo_sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +rp_data[7] <= rdata_fifo_sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +rp_data[8] <= rdata_fifo_sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +rp_data[9] <= rdata_fifo_sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +rp_data[10] <= rdata_fifo_sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +rp_data[11] <= rdata_fifo_sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +rp_data[12] <= rdata_fifo_sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +rp_data[13] <= rdata_fifo_sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +rp_data[14] <= rdata_fifo_sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +rp_data[15] <= rdata_fifo_sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +rp_data[16] <= rdata_fifo_sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +rp_data[17] <= rdata_fifo_sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +rp_data[18] <= rdata_fifo_sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +rp_data[19] <= rdata_fifo_sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +rp_data[20] <= rdata_fifo_sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +rp_data[21] <= rdata_fifo_sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +rp_data[22] <= rdata_fifo_sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +rp_data[23] <= rdata_fifo_sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +rp_data[24] <= rdata_fifo_sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +rp_data[25] <= rdata_fifo_sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +rp_data[26] <= rdata_fifo_sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +rp_data[27] <= rdata_fifo_sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +rp_data[28] <= rdata_fifo_sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +rp_data[29] <= rdata_fifo_sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +rp_data[30] <= rdata_fifo_sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +rp_data[31] <= rdata_fifo_sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +rp_data[32] <= rf_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +rp_data[33] <= rf_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +rp_data[34] <= rf_sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +rp_data[35] <= rf_sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +rp_data[36] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[37] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[38] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[39] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[40] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[41] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[42] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[43] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[44] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[45] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[46] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[47] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[48] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[49] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[50] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[51] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[52] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[53] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[54] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[55] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[56] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[57] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[58] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[59] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[60] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[61] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[62] <= altera_merlin_burst_uncompressor:uncompressor.source_is_compressed +rp_data[63] <= rf_sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +rp_data[64] <= rf_sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +rp_data[65] <= rp_data.DB_MAX_OUTPUT_PORT_TYPE +rp_data[66] <= rf_sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +rp_data[67] <= rf_sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +rp_data[68] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt +rp_data[69] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt +rp_data[70] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt +rp_data[71] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap +rp_data[72] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap +rp_data[73] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap +rp_data[74] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize +rp_data[75] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize +rp_data[76] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize +rp_data[77] <= rf_sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +rp_data[78] <= rf_sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +rp_data[79] <= rf_sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +rp_data[80] <= rf_sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +rp_data[81] <= rf_sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +rp_data[82] <= rf_sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +rp_data[83] <= rf_sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +rp_data[84] <= rf_sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +rp_data[85] <= rf_sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +rp_data[86] <= rf_sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +rp_data[87] <= rf_sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +rp_data[88] <= rf_sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +rp_data[89] <= rf_sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +rp_data[90] <= rf_sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +rp_data[91] <= rf_sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +rp_data[92] <= rf_sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +rp_data[93] <= rf_sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +rp_data[94] <= rf_sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +rp_data[95] <= rf_sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +rp_data[96] <= rf_sink_data[96].DB_MAX_OUTPUT_PORT_TYPE +rp_data[97] <= rf_sink_data[97].DB_MAX_OUTPUT_PORT_TYPE +rp_data[98] <= rf_sink_data[98].DB_MAX_OUTPUT_PORT_TYPE +rp_data[99] <= +rp_data[100] <= +rp_startofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_startofpacket +rp_endofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_endofpacket + + +|de0_nano_system|system:inst_cpu|altera_merlin_slave_agent:pio_motor_rst_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor +clk => burst_uncompress_address_offset[0].CLK +clk => burst_uncompress_address_offset[1].CLK +clk => burst_uncompress_address_offset[2].CLK +clk => burst_uncompress_address_offset[3].CLK +clk => burst_uncompress_address_offset[4].CLK +clk => burst_uncompress_address_offset[5].CLK +clk => burst_uncompress_address_offset[6].CLK +clk => burst_uncompress_address_offset[7].CLK +clk => burst_uncompress_address_offset[8].CLK +clk => burst_uncompress_address_offset[9].CLK +clk => burst_uncompress_address_offset[10].CLK +clk => burst_uncompress_address_offset[11].CLK +clk => burst_uncompress_address_offset[12].CLK +clk => burst_uncompress_address_offset[13].CLK +clk => burst_uncompress_address_offset[14].CLK +clk => burst_uncompress_address_offset[15].CLK +clk => burst_uncompress_address_offset[16].CLK +clk => burst_uncompress_address_offset[17].CLK +clk => burst_uncompress_address_offset[18].CLK +clk => burst_uncompress_address_offset[19].CLK +clk => burst_uncompress_address_offset[20].CLK +clk => burst_uncompress_address_offset[21].CLK +clk => burst_uncompress_address_offset[22].CLK +clk => burst_uncompress_address_offset[23].CLK +clk => burst_uncompress_address_offset[24].CLK +clk => burst_uncompress_address_offset[25].CLK +clk => burst_uncompress_address_base[0].CLK +clk => burst_uncompress_address_base[1].CLK +clk => burst_uncompress_address_base[2].CLK +clk => burst_uncompress_address_base[3].CLK +clk => burst_uncompress_address_base[4].CLK +clk => burst_uncompress_address_base[5].CLK +clk => burst_uncompress_address_base[6].CLK +clk => burst_uncompress_address_base[7].CLK +clk => burst_uncompress_address_base[8].CLK +clk => burst_uncompress_address_base[9].CLK +clk => burst_uncompress_address_base[10].CLK +clk => burst_uncompress_address_base[11].CLK +clk => burst_uncompress_address_base[12].CLK +clk => burst_uncompress_address_base[13].CLK +clk => burst_uncompress_address_base[14].CLK +clk => burst_uncompress_address_base[15].CLK +clk => burst_uncompress_address_base[16].CLK +clk => burst_uncompress_address_base[17].CLK +clk => burst_uncompress_address_base[18].CLK +clk => burst_uncompress_address_base[19].CLK +clk => burst_uncompress_address_base[20].CLK +clk => burst_uncompress_address_base[21].CLK +clk => burst_uncompress_address_base[22].CLK +clk => burst_uncompress_address_base[23].CLK +clk => burst_uncompress_address_base[24].CLK +clk => burst_uncompress_address_base[25].CLK +clk => burst_uncompress_byte_counter[0].CLK +clk => burst_uncompress_byte_counter[1].CLK +clk => burst_uncompress_byte_counter[2].CLK +clk => burst_uncompress_busy.CLK +reset => burst_uncompress_address_offset[0].ACLR +reset => burst_uncompress_address_offset[1].ACLR +reset => burst_uncompress_address_offset[2].ACLR +reset => burst_uncompress_address_offset[3].ACLR +reset => burst_uncompress_address_offset[4].ACLR +reset => burst_uncompress_address_offset[5].ACLR +reset => burst_uncompress_address_offset[6].ACLR +reset => burst_uncompress_address_offset[7].ACLR +reset => burst_uncompress_address_offset[8].ACLR +reset => burst_uncompress_address_offset[9].ACLR +reset => burst_uncompress_address_offset[10].ACLR +reset => burst_uncompress_address_offset[11].ACLR +reset => burst_uncompress_address_offset[12].ACLR +reset => burst_uncompress_address_offset[13].ACLR +reset => burst_uncompress_address_offset[14].ACLR +reset => burst_uncompress_address_offset[15].ACLR +reset => burst_uncompress_address_offset[16].ACLR +reset => burst_uncompress_address_offset[17].ACLR +reset => burst_uncompress_address_offset[18].ACLR +reset => burst_uncompress_address_offset[19].ACLR +reset => burst_uncompress_address_offset[20].ACLR +reset => burst_uncompress_address_offset[21].ACLR +reset => burst_uncompress_address_offset[22].ACLR +reset => burst_uncompress_address_offset[23].ACLR +reset => burst_uncompress_address_offset[24].ACLR +reset => burst_uncompress_address_offset[25].ACLR +reset => burst_uncompress_address_base[0].ACLR +reset => burst_uncompress_address_base[1].ACLR +reset => burst_uncompress_address_base[2].ACLR +reset => burst_uncompress_address_base[3].ACLR +reset => burst_uncompress_address_base[4].ACLR +reset => burst_uncompress_address_base[5].ACLR +reset => burst_uncompress_address_base[6].ACLR +reset => burst_uncompress_address_base[7].ACLR +reset => burst_uncompress_address_base[8].ACLR +reset => burst_uncompress_address_base[9].ACLR +reset => burst_uncompress_address_base[10].ACLR +reset => burst_uncompress_address_base[11].ACLR +reset => burst_uncompress_address_base[12].ACLR +reset => burst_uncompress_address_base[13].ACLR +reset => burst_uncompress_address_base[14].ACLR +reset => burst_uncompress_address_base[15].ACLR +reset => burst_uncompress_address_base[16].ACLR +reset => burst_uncompress_address_base[17].ACLR +reset => burst_uncompress_address_base[18].ACLR +reset => burst_uncompress_address_base[19].ACLR +reset => burst_uncompress_address_base[20].ACLR +reset => burst_uncompress_address_base[21].ACLR +reset => burst_uncompress_address_base[22].ACLR +reset => burst_uncompress_address_base[23].ACLR +reset => burst_uncompress_address_base[24].ACLR +reset => burst_uncompress_address_base[25].ACLR +reset => burst_uncompress_byte_counter[0].ACLR +reset => burst_uncompress_byte_counter[1].ACLR +reset => burst_uncompress_byte_counter[2].ACLR +reset => burst_uncompress_busy.ACLR +sink_startofpacket => source_startofpacket.IN1 +sink_endofpacket => source_endofpacket.IN1 +sink_valid => first_packet_beat.IN1 +sink_valid => last_packet_beat.IN1 +sink_valid => last_packet_beat.IN1 +sink_valid => always0.IN1 +sink_valid => sink_ready.IN0 +sink_valid => source_valid.DATAIN +sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE +sink_addr[0] => burst_uncompress_address_base.IN0 +sink_addr[0] => comb.DATAB +sink_addr[0] => source_addr.DATAB +sink_addr[1] => burst_uncompress_address_base.IN0 +sink_addr[1] => comb.DATAB +sink_addr[1] => source_addr.DATAB +sink_addr[2] => burst_uncompress_address_base.IN0 +sink_addr[2] => comb.DATAB +sink_addr[2] => source_addr.DATAB +sink_addr[3] => burst_uncompress_address_base.IN0 +sink_addr[3] => comb.DATAB +sink_addr[3] => source_addr.DATAB +sink_addr[4] => burst_uncompress_address_base.IN0 +sink_addr[4] => comb.DATAB +sink_addr[4] => source_addr.DATAB +sink_addr[5] => burst_uncompress_address_base.IN0 +sink_addr[5] => comb.DATAB +sink_addr[5] => source_addr.DATAB +sink_addr[6] => burst_uncompress_address_base.IN0 +sink_addr[6] => comb.DATAB +sink_addr[6] => source_addr.DATAB +sink_addr[7] => burst_uncompress_address_base.IN0 +sink_addr[7] => comb.DATAB +sink_addr[7] => source_addr.DATAB +sink_addr[8] => burst_uncompress_address_base.IN0 +sink_addr[8] => comb.DATAB +sink_addr[8] => source_addr.DATAB +sink_addr[9] => burst_uncompress_address_base.IN0 +sink_addr[9] => comb.DATAB +sink_addr[9] => source_addr.DATAB +sink_addr[10] => burst_uncompress_address_base.IN0 +sink_addr[10] => comb.DATAB +sink_addr[10] => source_addr.DATAB +sink_addr[11] => burst_uncompress_address_base.IN0 +sink_addr[11] => comb.DATAB +sink_addr[11] => source_addr.DATAB +sink_addr[12] => burst_uncompress_address_base.IN0 +sink_addr[12] => comb.DATAB +sink_addr[12] => source_addr.DATAB +sink_addr[13] => burst_uncompress_address_base.IN0 +sink_addr[13] => comb.DATAB +sink_addr[13] => source_addr.DATAB +sink_addr[14] => burst_uncompress_address_base.IN0 +sink_addr[14] => comb.DATAB +sink_addr[14] => source_addr.DATAB +sink_addr[15] => burst_uncompress_address_base.IN0 +sink_addr[15] => comb.DATAB +sink_addr[15] => source_addr.DATAB +sink_addr[16] => burst_uncompress_address_base.IN0 +sink_addr[16] => comb.DATAB +sink_addr[16] => source_addr.DATAB +sink_addr[17] => burst_uncompress_address_base.IN0 +sink_addr[17] => comb.DATAB +sink_addr[17] => source_addr.DATAB +sink_addr[18] => burst_uncompress_address_base.IN0 +sink_addr[18] => comb.DATAB +sink_addr[18] => source_addr.DATAB +sink_addr[19] => burst_uncompress_address_base.IN0 +sink_addr[19] => comb.DATAB +sink_addr[19] => source_addr.DATAB +sink_addr[20] => burst_uncompress_address_base.IN0 +sink_addr[20] => comb.DATAB +sink_addr[20] => source_addr.DATAB +sink_addr[21] => burst_uncompress_address_base.IN0 +sink_addr[21] => comb.DATAB +sink_addr[21] => source_addr.DATAB +sink_addr[22] => burst_uncompress_address_base.IN0 +sink_addr[22] => comb.DATAB +sink_addr[22] => source_addr.DATAB +sink_addr[23] => burst_uncompress_address_base.IN0 +sink_addr[23] => comb.DATAB +sink_addr[23] => source_addr.DATAB +sink_addr[24] => burst_uncompress_address_base.IN0 +sink_addr[24] => comb.DATAB +sink_addr[24] => source_addr.DATAB +sink_addr[25] => burst_uncompress_address_base.IN0 +sink_addr[25] => comb.DATAB +sink_addr[25] => source_addr.DATAB +sink_burstwrap[0] => p1_burst_uncompress_address_offset[0].IN1 +sink_burstwrap[0] => source_burstwrap[0].DATAIN +sink_burstwrap[0] => burst_uncompress_address_base.IN1 +sink_burstwrap[1] => p1_burst_uncompress_address_offset[1].IN1 +sink_burstwrap[1] => source_burstwrap[1].DATAIN +sink_burstwrap[1] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[2].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[25].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[24].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[23].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[22].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[21].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[20].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[19].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[18].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[17].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[16].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[15].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[14].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[13].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[12].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[11].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[10].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[9].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[8].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[7].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[6].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[5].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[4].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[3].IN1 +sink_burstwrap[2] => source_burstwrap[2].DATAIN +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_byte_cnt[0] => source_byte_cnt.DATAB +sink_byte_cnt[0] => Add1.IN6 +sink_byte_cnt[0] => Equal1.IN2 +sink_byte_cnt[1] => source_byte_cnt.DATAB +sink_byte_cnt[1] => Add1.IN5 +sink_byte_cnt[1] => Equal1.IN1 +sink_byte_cnt[2] => source_byte_cnt.DATAB +sink_byte_cnt[2] => Add1.IN4 +sink_byte_cnt[2] => Equal1.IN0 +sink_is_compressed => last_packet_beat.IN1 +sink_burstsize[0] => Decoder0.IN2 +sink_burstsize[0] => source_burstsize[0].DATAIN +sink_burstsize[1] => Decoder0.IN1 +sink_burstsize[1] => source_burstsize[1].DATAIN +sink_burstsize[2] => Decoder0.IN0 +sink_burstsize[2] => source_burstsize[2].DATAIN +source_startofpacket <= source_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +source_endofpacket <= source_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +source_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE +source_ready => always1.IN1 +source_ready => sink_ready.IN1 +source_addr[0] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[1] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[2] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[3] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[4] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[5] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[6] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[7] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[8] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[9] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[10] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[11] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[12] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[13] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[14] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[15] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[16] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[17] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[18] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[19] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[20] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[21] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[22] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[23] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[24] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[25] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_burstwrap[0] <= sink_burstwrap[0].DB_MAX_OUTPUT_PORT_TYPE +source_burstwrap[1] <= sink_burstwrap[1].DB_MAX_OUTPUT_PORT_TYPE +source_burstwrap[2] <= sink_burstwrap[2].DB_MAX_OUTPUT_PORT_TYPE +source_byte_cnt[0] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE +source_byte_cnt[1] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE +source_byte_cnt[2] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE +source_is_compressed <= +source_burstsize[0] <= sink_burstsize[0].DB_MAX_OUTPUT_PORT_TYPE +source_burstsize[1] <= sink_burstsize[1].DB_MAX_OUTPUT_PORT_TYPE +source_burstsize[2] <= sink_burstsize[2].DB_MAX_OUTPUT_PORT_TYPE + + +|de0_nano_system|system:inst_cpu|altera_avalon_sc_fifo:pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rsp_fifo +clk => csr_readdata[0]~reg0.CLK +clk => csr_readdata[1]~reg0.CLK +clk => csr_readdata[2]~reg0.CLK +clk => csr_readdata[3]~reg0.CLK +clk => csr_readdata[4]~reg0.CLK +clk => csr_readdata[5]~reg0.CLK +clk => csr_readdata[6]~reg0.CLK +clk => csr_readdata[7]~reg0.CLK +clk => csr_readdata[8]~reg0.CLK +clk => csr_readdata[9]~reg0.CLK +clk => csr_readdata[10]~reg0.CLK +clk => csr_readdata[11]~reg0.CLK +clk => csr_readdata[12]~reg0.CLK +clk => csr_readdata[13]~reg0.CLK +clk => csr_readdata[14]~reg0.CLK +clk => csr_readdata[15]~reg0.CLK +clk => csr_readdata[16]~reg0.CLK +clk => csr_readdata[17]~reg0.CLK +clk => csr_readdata[18]~reg0.CLK +clk => csr_readdata[19]~reg0.CLK +clk => csr_readdata[20]~reg0.CLK +clk => csr_readdata[21]~reg0.CLK +clk => csr_readdata[22]~reg0.CLK +clk => csr_readdata[23]~reg0.CLK +clk => csr_readdata[24]~reg0.CLK +clk => csr_readdata[25]~reg0.CLK +clk => csr_readdata[26]~reg0.CLK +clk => csr_readdata[27]~reg0.CLK +clk => csr_readdata[28]~reg0.CLK +clk => csr_readdata[29]~reg0.CLK +clk => csr_readdata[30]~reg0.CLK +clk => csr_readdata[31]~reg0.CLK +clk => mem_used[1].CLK +clk => mem_used[0].CLK +clk => mem[1][0].CLK +clk => mem[1][1].CLK +clk => mem[1][2].CLK +clk => mem[1][3].CLK +clk => mem[1][4].CLK +clk => mem[1][5].CLK +clk => mem[1][6].CLK +clk => mem[1][7].CLK +clk => mem[1][8].CLK +clk => mem[1][9].CLK +clk => mem[1][10].CLK +clk => mem[1][11].CLK +clk => mem[1][12].CLK +clk => mem[1][13].CLK +clk => mem[1][14].CLK +clk => mem[1][15].CLK +clk => mem[1][16].CLK +clk => mem[1][17].CLK +clk => mem[1][18].CLK +clk => mem[1][19].CLK +clk => mem[1][20].CLK +clk => mem[1][21].CLK +clk => mem[1][22].CLK +clk => mem[1][23].CLK +clk => mem[1][24].CLK +clk => mem[1][25].CLK +clk => mem[1][26].CLK +clk => mem[1][27].CLK +clk => mem[1][28].CLK +clk => mem[1][29].CLK +clk => mem[1][30].CLK +clk => mem[1][31].CLK +clk => mem[1][32].CLK +clk => mem[1][33].CLK +clk => mem[1][34].CLK +clk => mem[1][35].CLK +clk => mem[1][36].CLK +clk => mem[1][37].CLK +clk => mem[1][38].CLK +clk => mem[1][39].CLK +clk => mem[1][40].CLK +clk => mem[1][41].CLK +clk => mem[1][42].CLK +clk => mem[1][43].CLK +clk => mem[1][44].CLK +clk => mem[1][45].CLK +clk => mem[1][46].CLK +clk => mem[1][47].CLK +clk => mem[1][48].CLK +clk => mem[1][49].CLK +clk => mem[1][50].CLK +clk => mem[1][51].CLK +clk => mem[1][52].CLK +clk => mem[1][53].CLK +clk => mem[1][54].CLK +clk => mem[1][55].CLK +clk => mem[1][56].CLK +clk => mem[1][57].CLK +clk => mem[1][58].CLK +clk => mem[1][59].CLK +clk => mem[1][60].CLK +clk => mem[1][61].CLK +clk => mem[1][62].CLK +clk => mem[1][63].CLK +clk => mem[1][64].CLK +clk => mem[1][65].CLK +clk => mem[1][66].CLK +clk => mem[1][67].CLK +clk => mem[1][68].CLK +clk => mem[1][69].CLK +clk => mem[1][70].CLK +clk => mem[1][71].CLK +clk => mem[1][72].CLK +clk => mem[1][73].CLK +clk => mem[1][74].CLK +clk => mem[1][75].CLK +clk => mem[1][76].CLK +clk => mem[1][77].CLK +clk => mem[1][78].CLK +clk => mem[1][79].CLK +clk => mem[1][80].CLK +clk => mem[1][81].CLK +clk => mem[1][82].CLK +clk => mem[1][83].CLK +clk => mem[1][84].CLK +clk => mem[1][85].CLK +clk => mem[1][86].CLK +clk => mem[1][87].CLK +clk => mem[1][88].CLK +clk => mem[1][89].CLK +clk => mem[1][90].CLK +clk => mem[1][91].CLK +clk => mem[1][92].CLK +clk => mem[1][93].CLK +clk => mem[1][94].CLK +clk => mem[1][95].CLK +clk => mem[1][96].CLK +clk => mem[1][97].CLK +clk => mem[1][98].CLK +clk => mem[1][99].CLK +clk => mem[1][100].CLK +clk => mem[1][101].CLK +clk => mem[1][102].CLK +clk => mem[1][103].CLK +clk => mem[0][0].CLK +clk => mem[0][1].CLK +clk => mem[0][2].CLK +clk => mem[0][3].CLK +clk => mem[0][4].CLK +clk => mem[0][5].CLK +clk => mem[0][6].CLK +clk => mem[0][7].CLK +clk => mem[0][8].CLK +clk => mem[0][9].CLK +clk => mem[0][10].CLK +clk => mem[0][11].CLK +clk => mem[0][12].CLK +clk => mem[0][13].CLK +clk => mem[0][14].CLK +clk => mem[0][15].CLK +clk => mem[0][16].CLK +clk => mem[0][17].CLK +clk => mem[0][18].CLK +clk => mem[0][19].CLK +clk => mem[0][20].CLK +clk => mem[0][21].CLK +clk => mem[0][22].CLK +clk => mem[0][23].CLK +clk => mem[0][24].CLK +clk => mem[0][25].CLK +clk => mem[0][26].CLK +clk => mem[0][27].CLK +clk => mem[0][28].CLK +clk => mem[0][29].CLK +clk => mem[0][30].CLK +clk => mem[0][31].CLK +clk => mem[0][32].CLK +clk => mem[0][33].CLK +clk => mem[0][34].CLK +clk => mem[0][35].CLK +clk => mem[0][36].CLK +clk => mem[0][37].CLK +clk => mem[0][38].CLK +clk => mem[0][39].CLK +clk => mem[0][40].CLK +clk => mem[0][41].CLK +clk => mem[0][42].CLK +clk => mem[0][43].CLK +clk => mem[0][44].CLK +clk => mem[0][45].CLK +clk => mem[0][46].CLK +clk => mem[0][47].CLK +clk => mem[0][48].CLK +clk => mem[0][49].CLK +clk => mem[0][50].CLK +clk => mem[0][51].CLK +clk => mem[0][52].CLK +clk => mem[0][53].CLK +clk => mem[0][54].CLK +clk => mem[0][55].CLK +clk => mem[0][56].CLK +clk => mem[0][57].CLK +clk => mem[0][58].CLK +clk => mem[0][59].CLK +clk => mem[0][60].CLK +clk => mem[0][61].CLK +clk => mem[0][62].CLK +clk => mem[0][63].CLK +clk => mem[0][64].CLK +clk => mem[0][65].CLK +clk => mem[0][66].CLK +clk => mem[0][67].CLK +clk => mem[0][68].CLK +clk => mem[0][69].CLK +clk => mem[0][70].CLK +clk => mem[0][71].CLK +clk => mem[0][72].CLK +clk => mem[0][73].CLK +clk => mem[0][74].CLK +clk => mem[0][75].CLK +clk => mem[0][76].CLK +clk => mem[0][77].CLK +clk => mem[0][78].CLK +clk => mem[0][79].CLK +clk => mem[0][80].CLK +clk => mem[0][81].CLK +clk => mem[0][82].CLK +clk => mem[0][83].CLK +clk => mem[0][84].CLK +clk => mem[0][85].CLK +clk => mem[0][86].CLK +clk => mem[0][87].CLK +clk => mem[0][88].CLK +clk => mem[0][89].CLK +clk => mem[0][90].CLK +clk => mem[0][91].CLK +clk => mem[0][92].CLK +clk => mem[0][93].CLK +clk => mem[0][94].CLK +clk => mem[0][95].CLK +clk => mem[0][96].CLK +clk => mem[0][97].CLK +clk => mem[0][98].CLK +clk => mem[0][99].CLK +clk => mem[0][100].CLK +clk => mem[0][101].CLK +clk => mem[0][102].CLK +clk => mem[0][103].CLK +reset => csr_readdata[0]~reg0.ACLR +reset => csr_readdata[1]~reg0.ACLR +reset => csr_readdata[2]~reg0.ACLR +reset => csr_readdata[3]~reg0.ACLR +reset => csr_readdata[4]~reg0.ACLR +reset => csr_readdata[5]~reg0.ACLR +reset => csr_readdata[6]~reg0.ACLR +reset => csr_readdata[7]~reg0.ACLR +reset => csr_readdata[8]~reg0.ACLR +reset => csr_readdata[9]~reg0.ACLR +reset => csr_readdata[10]~reg0.ACLR +reset => csr_readdata[11]~reg0.ACLR +reset => csr_readdata[12]~reg0.ACLR +reset => csr_readdata[13]~reg0.ACLR +reset => csr_readdata[14]~reg0.ACLR +reset => csr_readdata[15]~reg0.ACLR +reset => csr_readdata[16]~reg0.ACLR +reset => csr_readdata[17]~reg0.ACLR +reset => csr_readdata[18]~reg0.ACLR +reset => csr_readdata[19]~reg0.ACLR +reset => csr_readdata[20]~reg0.ACLR +reset => csr_readdata[21]~reg0.ACLR +reset => csr_readdata[22]~reg0.ACLR +reset => csr_readdata[23]~reg0.ACLR +reset => csr_readdata[24]~reg0.ACLR +reset => csr_readdata[25]~reg0.ACLR +reset => csr_readdata[26]~reg0.ACLR +reset => csr_readdata[27]~reg0.ACLR +reset => csr_readdata[28]~reg0.ACLR +reset => csr_readdata[29]~reg0.ACLR +reset => csr_readdata[30]~reg0.ACLR +reset => csr_readdata[31]~reg0.ACLR +reset => mem_used[1].ACLR +reset => mem_used[0].ACLR +reset => mem[1][0].ACLR +reset => mem[1][1].ACLR +reset => mem[1][2].ACLR +reset => mem[1][3].ACLR +reset => mem[1][4].ACLR +reset => mem[1][5].ACLR +reset => mem[1][6].ACLR +reset => mem[1][7].ACLR +reset => mem[1][8].ACLR +reset => mem[1][9].ACLR +reset => mem[1][10].ACLR +reset => mem[1][11].ACLR +reset => mem[1][12].ACLR +reset => mem[1][13].ACLR +reset => mem[1][14].ACLR +reset => mem[1][15].ACLR +reset => mem[1][16].ACLR +reset => mem[1][17].ACLR +reset => mem[1][18].ACLR +reset => mem[1][19].ACLR +reset => mem[1][20].ACLR +reset => mem[1][21].ACLR +reset => mem[1][22].ACLR +reset => mem[1][23].ACLR +reset => mem[1][24].ACLR +reset => mem[1][25].ACLR +reset => mem[1][26].ACLR +reset => mem[1][27].ACLR +reset => mem[1][28].ACLR +reset => mem[1][29].ACLR +reset => mem[1][30].ACLR +reset => mem[1][31].ACLR +reset => mem[1][32].ACLR +reset => mem[1][33].ACLR +reset => mem[1][34].ACLR +reset => mem[1][35].ACLR +reset => mem[1][36].ACLR +reset => mem[1][37].ACLR +reset => mem[1][38].ACLR +reset => mem[1][39].ACLR +reset => mem[1][40].ACLR +reset => mem[1][41].ACLR +reset => mem[1][42].ACLR +reset => mem[1][43].ACLR +reset => mem[1][44].ACLR +reset => mem[1][45].ACLR +reset => mem[1][46].ACLR +reset => mem[1][47].ACLR +reset => mem[1][48].ACLR +reset => mem[1][49].ACLR +reset => mem[1][50].ACLR +reset => mem[1][51].ACLR +reset => mem[1][52].ACLR +reset => mem[1][53].ACLR +reset => mem[1][54].ACLR +reset => mem[1][55].ACLR +reset => mem[1][56].ACLR +reset => mem[1][57].ACLR +reset => mem[1][58].ACLR +reset => mem[1][59].ACLR +reset => mem[1][60].ACLR +reset => mem[1][61].ACLR +reset => mem[1][62].ACLR +reset => mem[1][63].ACLR +reset => mem[1][64].ACLR +reset => mem[1][65].ACLR +reset => mem[1][66].ACLR +reset => mem[1][67].ACLR +reset => mem[1][68].ACLR +reset => mem[1][69].ACLR +reset => mem[1][70].ACLR +reset => mem[1][71].ACLR +reset => mem[1][72].ACLR +reset => mem[1][73].ACLR +reset => mem[1][74].ACLR +reset => mem[1][75].ACLR +reset => mem[1][76].ACLR +reset => mem[1][77].ACLR +reset => mem[1][78].ACLR +reset => mem[1][79].ACLR +reset => mem[1][80].ACLR +reset => mem[1][81].ACLR +reset => mem[1][82].ACLR +reset => mem[1][83].ACLR +reset => mem[1][84].ACLR +reset => mem[1][85].ACLR +reset => mem[1][86].ACLR +reset => mem[1][87].ACLR +reset => mem[1][88].ACLR +reset => mem[1][89].ACLR +reset => mem[1][90].ACLR +reset => mem[1][91].ACLR +reset => mem[1][92].ACLR +reset => mem[1][93].ACLR +reset => mem[1][94].ACLR +reset => mem[1][95].ACLR +reset => mem[1][96].ACLR +reset => mem[1][97].ACLR +reset => mem[1][98].ACLR +reset => mem[1][99].ACLR +reset => mem[1][100].ACLR +reset => mem[1][101].ACLR +reset => mem[1][102].ACLR +reset => mem[1][103].ACLR +reset => mem[0][0].ACLR +reset => mem[0][1].ACLR +reset => mem[0][2].ACLR +reset => mem[0][3].ACLR +reset => mem[0][4].ACLR +reset => mem[0][5].ACLR +reset => mem[0][6].ACLR +reset => mem[0][7].ACLR +reset => mem[0][8].ACLR +reset => mem[0][9].ACLR +reset => mem[0][10].ACLR +reset => mem[0][11].ACLR +reset => mem[0][12].ACLR +reset => mem[0][13].ACLR +reset => mem[0][14].ACLR +reset => mem[0][15].ACLR +reset => mem[0][16].ACLR +reset => mem[0][17].ACLR +reset => mem[0][18].ACLR +reset => mem[0][19].ACLR +reset => mem[0][20].ACLR +reset => mem[0][21].ACLR +reset => mem[0][22].ACLR +reset => mem[0][23].ACLR +reset => mem[0][24].ACLR +reset => mem[0][25].ACLR +reset => mem[0][26].ACLR +reset => mem[0][27].ACLR +reset => mem[0][28].ACLR +reset => mem[0][29].ACLR +reset => mem[0][30].ACLR +reset => mem[0][31].ACLR +reset => mem[0][32].ACLR +reset => mem[0][33].ACLR +reset => mem[0][34].ACLR +reset => mem[0][35].ACLR +reset => mem[0][36].ACLR +reset => mem[0][37].ACLR +reset => mem[0][38].ACLR +reset => mem[0][39].ACLR +reset => mem[0][40].ACLR +reset => mem[0][41].ACLR +reset => mem[0][42].ACLR +reset => mem[0][43].ACLR +reset => mem[0][44].ACLR +reset => mem[0][45].ACLR +reset => mem[0][46].ACLR +reset => mem[0][47].ACLR +reset => mem[0][48].ACLR +reset => mem[0][49].ACLR +reset => mem[0][50].ACLR +reset => mem[0][51].ACLR +reset => mem[0][52].ACLR +reset => mem[0][53].ACLR +reset => mem[0][54].ACLR +reset => mem[0][55].ACLR +reset => mem[0][56].ACLR +reset => mem[0][57].ACLR +reset => mem[0][58].ACLR +reset => mem[0][59].ACLR +reset => mem[0][60].ACLR +reset => mem[0][61].ACLR +reset => mem[0][62].ACLR +reset => mem[0][63].ACLR +reset => mem[0][64].ACLR +reset => mem[0][65].ACLR +reset => mem[0][66].ACLR +reset => mem[0][67].ACLR +reset => mem[0][68].ACLR +reset => mem[0][69].ACLR +reset => mem[0][70].ACLR +reset => mem[0][71].ACLR +reset => mem[0][72].ACLR +reset => mem[0][73].ACLR +reset => mem[0][74].ACLR +reset => mem[0][75].ACLR +reset => mem[0][76].ACLR +reset => mem[0][77].ACLR +reset => mem[0][78].ACLR +reset => mem[0][79].ACLR +reset => mem[0][80].ACLR +reset => mem[0][81].ACLR +reset => mem[0][82].ACLR +reset => mem[0][83].ACLR +reset => mem[0][84].ACLR +reset => mem[0][85].ACLR +reset => mem[0][86].ACLR +reset => mem[0][87].ACLR +reset => mem[0][88].ACLR +reset => mem[0][89].ACLR +reset => mem[0][90].ACLR +reset => mem[0][91].ACLR +reset => mem[0][92].ACLR +reset => mem[0][93].ACLR +reset => mem[0][94].ACLR +reset => mem[0][95].ACLR +reset => mem[0][96].ACLR +reset => mem[0][97].ACLR +reset => mem[0][98].ACLR +reset => mem[0][99].ACLR +reset => mem[0][100].ACLR +reset => mem[0][101].ACLR +reset => mem[0][102].ACLR +reset => mem[0][103].ACLR +in_data[0] => mem.DATAB +in_data[1] => mem.DATAB +in_data[2] => mem.DATAB +in_data[3] => mem.DATAB +in_data[4] => mem.DATAB +in_data[5] => mem.DATAB +in_data[6] => mem.DATAB +in_data[7] => mem.DATAB +in_data[8] => mem.DATAB +in_data[9] => mem.DATAB +in_data[10] => mem.DATAB +in_data[11] => mem.DATAB +in_data[12] => mem.DATAB +in_data[13] => mem.DATAB +in_data[14] => mem.DATAB +in_data[15] => mem.DATAB +in_data[16] => mem.DATAB +in_data[17] => mem.DATAB +in_data[18] => mem.DATAB +in_data[19] => mem.DATAB +in_data[20] => mem.DATAB +in_data[21] => mem.DATAB +in_data[22] => mem.DATAB +in_data[23] => mem.DATAB +in_data[24] => mem.DATAB +in_data[25] => mem.DATAB +in_data[26] => mem.DATAB +in_data[27] => mem.DATAB +in_data[28] => mem.DATAB +in_data[29] => mem.DATAB +in_data[30] => mem.DATAB +in_data[31] => mem.DATAB +in_data[32] => mem.DATAB +in_data[33] => mem.DATAB +in_data[34] => mem.DATAB +in_data[35] => mem.DATAB +in_data[36] => mem.DATAB +in_data[37] => mem.DATAB +in_data[38] => mem.DATAB +in_data[39] => mem.DATAB +in_data[40] => mem.DATAB +in_data[41] => mem.DATAB +in_data[42] => mem.DATAB +in_data[43] => mem.DATAB +in_data[44] => mem.DATAB +in_data[45] => mem.DATAB +in_data[46] => mem.DATAB +in_data[47] => mem.DATAB +in_data[48] => mem.DATAB +in_data[49] => mem.DATAB +in_data[50] => mem.DATAB +in_data[51] => mem.DATAB +in_data[52] => mem.DATAB +in_data[53] => mem.DATAB +in_data[54] => mem.DATAB +in_data[55] => mem.DATAB +in_data[56] => mem.DATAB +in_data[57] => mem.DATAB +in_data[58] => mem.DATAB +in_data[59] => mem.DATAB +in_data[60] => mem.DATAB +in_data[61] => mem.DATAB +in_data[62] => mem.DATAB +in_data[63] => mem.DATAB +in_data[64] => mem.DATAB +in_data[65] => mem.DATAB +in_data[66] => mem.DATAB +in_data[67] => mem.DATAB +in_data[68] => mem.DATAB +in_data[69] => mem.DATAB +in_data[70] => mem.DATAB +in_data[71] => mem.DATAB +in_data[72] => mem.DATAB +in_data[73] => mem.DATAB +in_data[74] => mem.DATAB +in_data[75] => mem.DATAB +in_data[76] => mem.DATAB +in_data[77] => mem.DATAB +in_data[78] => mem.DATAB +in_data[79] => mem.DATAB +in_data[80] => mem.DATAB +in_data[81] => mem.DATAB +in_data[82] => mem.DATAB +in_data[83] => mem.DATAB +in_data[84] => mem.DATAB +in_data[85] => mem.DATAB +in_data[86] => mem.DATAB +in_data[87] => mem.DATAB +in_data[88] => mem.DATAB +in_data[89] => mem.DATAB +in_data[90] => mem.DATAB +in_data[91] => mem.DATAB +in_data[92] => mem.DATAB +in_data[93] => mem.DATAB +in_data[94] => mem.DATAB +in_data[95] => mem.DATAB +in_data[96] => mem.DATAB +in_data[97] => mem.DATAB +in_data[98] => mem.DATAB +in_data[99] => mem.DATAB +in_data[100] => mem.DATAB +in_data[101] => mem.DATAB +in_valid => write.IN1 +in_startofpacket => mem.DATAB +in_endofpacket => mem.DATAB +in_empty[0] => ~NO_FANOUT~ +in_error[0] => out_error[0].DATAIN +in_error[0] => out_empty[0].DATAIN +in_channel[0] => out_channel[0].DATAIN +in_ready <= mem_used[1].DB_MAX_OUTPUT_PORT_TYPE +out_data[0] <= mem[0][0].DB_MAX_OUTPUT_PORT_TYPE +out_data[1] <= mem[0][1].DB_MAX_OUTPUT_PORT_TYPE +out_data[2] <= mem[0][2].DB_MAX_OUTPUT_PORT_TYPE +out_data[3] <= mem[0][3].DB_MAX_OUTPUT_PORT_TYPE +out_data[4] <= mem[0][4].DB_MAX_OUTPUT_PORT_TYPE +out_data[5] <= mem[0][5].DB_MAX_OUTPUT_PORT_TYPE +out_data[6] <= mem[0][6].DB_MAX_OUTPUT_PORT_TYPE +out_data[7] <= mem[0][7].DB_MAX_OUTPUT_PORT_TYPE +out_data[8] <= mem[0][8].DB_MAX_OUTPUT_PORT_TYPE +out_data[9] <= mem[0][9].DB_MAX_OUTPUT_PORT_TYPE +out_data[10] <= mem[0][10].DB_MAX_OUTPUT_PORT_TYPE +out_data[11] <= mem[0][11].DB_MAX_OUTPUT_PORT_TYPE +out_data[12] <= mem[0][12].DB_MAX_OUTPUT_PORT_TYPE +out_data[13] <= mem[0][13].DB_MAX_OUTPUT_PORT_TYPE +out_data[14] <= mem[0][14].DB_MAX_OUTPUT_PORT_TYPE +out_data[15] <= mem[0][15].DB_MAX_OUTPUT_PORT_TYPE +out_data[16] <= mem[0][16].DB_MAX_OUTPUT_PORT_TYPE +out_data[17] <= mem[0][17].DB_MAX_OUTPUT_PORT_TYPE +out_data[18] <= mem[0][18].DB_MAX_OUTPUT_PORT_TYPE +out_data[19] <= mem[0][19].DB_MAX_OUTPUT_PORT_TYPE +out_data[20] <= mem[0][20].DB_MAX_OUTPUT_PORT_TYPE +out_data[21] <= mem[0][21].DB_MAX_OUTPUT_PORT_TYPE +out_data[22] <= mem[0][22].DB_MAX_OUTPUT_PORT_TYPE +out_data[23] <= mem[0][23].DB_MAX_OUTPUT_PORT_TYPE +out_data[24] <= mem[0][24].DB_MAX_OUTPUT_PORT_TYPE +out_data[25] <= mem[0][25].DB_MAX_OUTPUT_PORT_TYPE +out_data[26] <= mem[0][26].DB_MAX_OUTPUT_PORT_TYPE +out_data[27] <= mem[0][27].DB_MAX_OUTPUT_PORT_TYPE +out_data[28] <= mem[0][28].DB_MAX_OUTPUT_PORT_TYPE +out_data[29] <= mem[0][29].DB_MAX_OUTPUT_PORT_TYPE +out_data[30] <= mem[0][30].DB_MAX_OUTPUT_PORT_TYPE +out_data[31] <= mem[0][31].DB_MAX_OUTPUT_PORT_TYPE +out_data[32] <= mem[0][32].DB_MAX_OUTPUT_PORT_TYPE +out_data[33] <= mem[0][33].DB_MAX_OUTPUT_PORT_TYPE +out_data[34] <= mem[0][34].DB_MAX_OUTPUT_PORT_TYPE +out_data[35] <= mem[0][35].DB_MAX_OUTPUT_PORT_TYPE +out_data[36] <= mem[0][36].DB_MAX_OUTPUT_PORT_TYPE +out_data[37] <= mem[0][37].DB_MAX_OUTPUT_PORT_TYPE +out_data[38] <= mem[0][38].DB_MAX_OUTPUT_PORT_TYPE +out_data[39] <= mem[0][39].DB_MAX_OUTPUT_PORT_TYPE +out_data[40] <= mem[0][40].DB_MAX_OUTPUT_PORT_TYPE +out_data[41] <= mem[0][41].DB_MAX_OUTPUT_PORT_TYPE +out_data[42] <= mem[0][42].DB_MAX_OUTPUT_PORT_TYPE +out_data[43] <= mem[0][43].DB_MAX_OUTPUT_PORT_TYPE +out_data[44] <= mem[0][44].DB_MAX_OUTPUT_PORT_TYPE +out_data[45] <= mem[0][45].DB_MAX_OUTPUT_PORT_TYPE +out_data[46] <= mem[0][46].DB_MAX_OUTPUT_PORT_TYPE +out_data[47] <= mem[0][47].DB_MAX_OUTPUT_PORT_TYPE +out_data[48] <= mem[0][48].DB_MAX_OUTPUT_PORT_TYPE +out_data[49] <= mem[0][49].DB_MAX_OUTPUT_PORT_TYPE +out_data[50] <= mem[0][50].DB_MAX_OUTPUT_PORT_TYPE +out_data[51] <= mem[0][51].DB_MAX_OUTPUT_PORT_TYPE +out_data[52] <= mem[0][52].DB_MAX_OUTPUT_PORT_TYPE +out_data[53] <= mem[0][53].DB_MAX_OUTPUT_PORT_TYPE +out_data[54] <= mem[0][54].DB_MAX_OUTPUT_PORT_TYPE +out_data[55] <= mem[0][55].DB_MAX_OUTPUT_PORT_TYPE +out_data[56] <= mem[0][56].DB_MAX_OUTPUT_PORT_TYPE +out_data[57] <= mem[0][57].DB_MAX_OUTPUT_PORT_TYPE +out_data[58] <= mem[0][58].DB_MAX_OUTPUT_PORT_TYPE +out_data[59] <= mem[0][59].DB_MAX_OUTPUT_PORT_TYPE +out_data[60] <= mem[0][60].DB_MAX_OUTPUT_PORT_TYPE +out_data[61] <= mem[0][61].DB_MAX_OUTPUT_PORT_TYPE +out_data[62] <= mem[0][62].DB_MAX_OUTPUT_PORT_TYPE +out_data[63] <= mem[0][63].DB_MAX_OUTPUT_PORT_TYPE +out_data[64] <= mem[0][64].DB_MAX_OUTPUT_PORT_TYPE +out_data[65] <= mem[0][65].DB_MAX_OUTPUT_PORT_TYPE +out_data[66] <= mem[0][66].DB_MAX_OUTPUT_PORT_TYPE +out_data[67] <= mem[0][67].DB_MAX_OUTPUT_PORT_TYPE +out_data[68] <= mem[0][68].DB_MAX_OUTPUT_PORT_TYPE +out_data[69] <= mem[0][69].DB_MAX_OUTPUT_PORT_TYPE +out_data[70] <= mem[0][70].DB_MAX_OUTPUT_PORT_TYPE +out_data[71] <= mem[0][71].DB_MAX_OUTPUT_PORT_TYPE +out_data[72] <= mem[0][72].DB_MAX_OUTPUT_PORT_TYPE +out_data[73] <= mem[0][73].DB_MAX_OUTPUT_PORT_TYPE +out_data[74] <= mem[0][74].DB_MAX_OUTPUT_PORT_TYPE +out_data[75] <= mem[0][75].DB_MAX_OUTPUT_PORT_TYPE +out_data[76] <= mem[0][76].DB_MAX_OUTPUT_PORT_TYPE +out_data[77] <= mem[0][77].DB_MAX_OUTPUT_PORT_TYPE +out_data[78] <= mem[0][78].DB_MAX_OUTPUT_PORT_TYPE +out_data[79] <= mem[0][79].DB_MAX_OUTPUT_PORT_TYPE +out_data[80] <= mem[0][80].DB_MAX_OUTPUT_PORT_TYPE +out_data[81] <= mem[0][81].DB_MAX_OUTPUT_PORT_TYPE +out_data[82] <= mem[0][82].DB_MAX_OUTPUT_PORT_TYPE +out_data[83] <= mem[0][83].DB_MAX_OUTPUT_PORT_TYPE +out_data[84] <= mem[0][84].DB_MAX_OUTPUT_PORT_TYPE +out_data[85] <= mem[0][85].DB_MAX_OUTPUT_PORT_TYPE +out_data[86] <= mem[0][86].DB_MAX_OUTPUT_PORT_TYPE +out_data[87] <= mem[0][87].DB_MAX_OUTPUT_PORT_TYPE +out_data[88] <= mem[0][88].DB_MAX_OUTPUT_PORT_TYPE +out_data[89] <= mem[0][89].DB_MAX_OUTPUT_PORT_TYPE +out_data[90] <= mem[0][90].DB_MAX_OUTPUT_PORT_TYPE +out_data[91] <= mem[0][91].DB_MAX_OUTPUT_PORT_TYPE +out_data[92] <= mem[0][92].DB_MAX_OUTPUT_PORT_TYPE +out_data[93] <= mem[0][93].DB_MAX_OUTPUT_PORT_TYPE +out_data[94] <= mem[0][94].DB_MAX_OUTPUT_PORT_TYPE +out_data[95] <= mem[0][95].DB_MAX_OUTPUT_PORT_TYPE +out_data[96] <= mem[0][96].DB_MAX_OUTPUT_PORT_TYPE +out_data[97] <= mem[0][97].DB_MAX_OUTPUT_PORT_TYPE +out_data[98] <= mem[0][98].DB_MAX_OUTPUT_PORT_TYPE +out_data[99] <= mem[0][99].DB_MAX_OUTPUT_PORT_TYPE +out_data[100] <= mem[0][100].DB_MAX_OUTPUT_PORT_TYPE +out_data[101] <= mem[0][101].DB_MAX_OUTPUT_PORT_TYPE +out_valid <= mem_used[0].DB_MAX_OUTPUT_PORT_TYPE +out_startofpacket <= mem[0][103].DB_MAX_OUTPUT_PORT_TYPE +out_endofpacket <= mem[0][102].DB_MAX_OUTPUT_PORT_TYPE +out_empty[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE +out_error[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE +out_channel[0] <= in_channel[0].DB_MAX_OUTPUT_PORT_TYPE +out_ready => internal_out_ready.IN1 +csr_address[0] => ~NO_FANOUT~ +csr_address[1] => ~NO_FANOUT~ +csr_write => ~NO_FANOUT~ +csr_read => csr_readdata[0]~reg0.ENA +csr_read => csr_readdata[31]~reg0.ENA +csr_read => csr_readdata[30]~reg0.ENA +csr_read => csr_readdata[29]~reg0.ENA +csr_read => csr_readdata[28]~reg0.ENA +csr_read => csr_readdata[27]~reg0.ENA +csr_read => csr_readdata[26]~reg0.ENA +csr_read => csr_readdata[25]~reg0.ENA +csr_read => csr_readdata[24]~reg0.ENA +csr_read => csr_readdata[23]~reg0.ENA +csr_read => csr_readdata[22]~reg0.ENA +csr_read => csr_readdata[21]~reg0.ENA +csr_read => csr_readdata[20]~reg0.ENA +csr_read => csr_readdata[19]~reg0.ENA +csr_read => csr_readdata[18]~reg0.ENA +csr_read => csr_readdata[17]~reg0.ENA +csr_read => csr_readdata[16]~reg0.ENA +csr_read => csr_readdata[15]~reg0.ENA +csr_read => csr_readdata[14]~reg0.ENA +csr_read => csr_readdata[13]~reg0.ENA +csr_read => csr_readdata[12]~reg0.ENA +csr_read => csr_readdata[11]~reg0.ENA +csr_read => csr_readdata[10]~reg0.ENA +csr_read => csr_readdata[9]~reg0.ENA +csr_read => csr_readdata[8]~reg0.ENA +csr_read => csr_readdata[7]~reg0.ENA +csr_read => csr_readdata[6]~reg0.ENA +csr_read => csr_readdata[5]~reg0.ENA +csr_read => csr_readdata[4]~reg0.ENA +csr_read => csr_readdata[3]~reg0.ENA +csr_read => csr_readdata[2]~reg0.ENA +csr_read => csr_readdata[1]~reg0.ENA +csr_writedata[0] => ~NO_FANOUT~ +csr_writedata[1] => ~NO_FANOUT~ +csr_writedata[2] => ~NO_FANOUT~ +csr_writedata[3] => ~NO_FANOUT~ +csr_writedata[4] => ~NO_FANOUT~ +csr_writedata[5] => ~NO_FANOUT~ +csr_writedata[6] => ~NO_FANOUT~ +csr_writedata[7] => ~NO_FANOUT~ +csr_writedata[8] => ~NO_FANOUT~ +csr_writedata[9] => ~NO_FANOUT~ +csr_writedata[10] => ~NO_FANOUT~ +csr_writedata[11] => ~NO_FANOUT~ +csr_writedata[12] => ~NO_FANOUT~ +csr_writedata[13] => ~NO_FANOUT~ +csr_writedata[14] => ~NO_FANOUT~ +csr_writedata[15] => ~NO_FANOUT~ +csr_writedata[16] => ~NO_FANOUT~ +csr_writedata[17] => ~NO_FANOUT~ +csr_writedata[18] => ~NO_FANOUT~ +csr_writedata[19] => ~NO_FANOUT~ +csr_writedata[20] => ~NO_FANOUT~ +csr_writedata[21] => ~NO_FANOUT~ +csr_writedata[22] => ~NO_FANOUT~ +csr_writedata[23] => ~NO_FANOUT~ +csr_writedata[24] => ~NO_FANOUT~ +csr_writedata[25] => ~NO_FANOUT~ +csr_writedata[26] => ~NO_FANOUT~ +csr_writedata[27] => ~NO_FANOUT~ +csr_writedata[28] => ~NO_FANOUT~ +csr_writedata[29] => ~NO_FANOUT~ +csr_writedata[30] => ~NO_FANOUT~ +csr_writedata[31] => ~NO_FANOUT~ +csr_readdata[0] <= csr_readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[1] <= csr_readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[2] <= csr_readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[3] <= csr_readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[4] <= csr_readdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[5] <= csr_readdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[6] <= csr_readdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[7] <= csr_readdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[8] <= csr_readdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[9] <= csr_readdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[10] <= csr_readdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[11] <= csr_readdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[12] <= csr_readdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[13] <= csr_readdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[14] <= csr_readdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[15] <= csr_readdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[16] <= csr_readdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[17] <= csr_readdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[18] <= csr_readdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[19] <= csr_readdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[20] <= csr_readdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[21] <= csr_readdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[22] <= csr_readdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[23] <= csr_readdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[24] <= csr_readdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[25] <= csr_readdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[26] <= csr_readdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[27] <= csr_readdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[28] <= csr_readdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[29] <= csr_readdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[30] <= csr_readdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[31] <= csr_readdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE +almost_full_data <= +almost_empty_data <= + + +|de0_nano_system|system:inst_cpu|altera_merlin_slave_agent:rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent +clk => clk.IN1 +reset => reset.IN1 +m0_address[0] <= +m0_address[1] <= +m0_address[2] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE +m0_address[3] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE +m0_address[4] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE +m0_address[5] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE +m0_address[6] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE +m0_address[7] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE +m0_address[8] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE +m0_address[9] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE +m0_address[10] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE +m0_address[11] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE +m0_address[12] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE +m0_address[13] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE +m0_address[14] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE +m0_address[15] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE +m0_address[16] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE +m0_address[17] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE +m0_address[18] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE +m0_address[19] <= cp_data[55].DB_MAX_OUTPUT_PORT_TYPE +m0_address[20] <= cp_data[56].DB_MAX_OUTPUT_PORT_TYPE +m0_address[21] <= cp_data[57].DB_MAX_OUTPUT_PORT_TYPE +m0_address[22] <= cp_data[58].DB_MAX_OUTPUT_PORT_TYPE +m0_address[23] <= cp_data[59].DB_MAX_OUTPUT_PORT_TYPE +m0_address[24] <= cp_data[60].DB_MAX_OUTPUT_PORT_TYPE +m0_address[25] <= cp_data[61].DB_MAX_OUTPUT_PORT_TYPE +m0_burstcount[0] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE +m0_burstcount[1] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE +m0_burstcount[2] <= m0_burstcount.DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[0] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[1] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[2] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE +m0_byteenable[3] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE +m0_read <= m0_read.DB_MAX_OUTPUT_PORT_TYPE +m0_readdata[0] => rdata_fifo_src_data[0].DATAIN +m0_readdata[1] => rdata_fifo_src_data[1].DATAIN +m0_readdata[2] => rdata_fifo_src_data[2].DATAIN +m0_readdata[3] => rdata_fifo_src_data[3].DATAIN +m0_readdata[4] => rdata_fifo_src_data[4].DATAIN +m0_readdata[5] => rdata_fifo_src_data[5].DATAIN +m0_readdata[6] => rdata_fifo_src_data[6].DATAIN +m0_readdata[7] => rdata_fifo_src_data[7].DATAIN +m0_readdata[8] => rdata_fifo_src_data[8].DATAIN +m0_readdata[9] => rdata_fifo_src_data[9].DATAIN +m0_readdata[10] => rdata_fifo_src_data[10].DATAIN +m0_readdata[11] => rdata_fifo_src_data[11].DATAIN +m0_readdata[12] => rdata_fifo_src_data[12].DATAIN +m0_readdata[13] => rdata_fifo_src_data[13].DATAIN +m0_readdata[14] => rdata_fifo_src_data[14].DATAIN +m0_readdata[15] => rdata_fifo_src_data[15].DATAIN +m0_readdata[16] => rdata_fifo_src_data[16].DATAIN +m0_readdata[17] => rdata_fifo_src_data[17].DATAIN +m0_readdata[18] => rdata_fifo_src_data[18].DATAIN +m0_readdata[19] => rdata_fifo_src_data[19].DATAIN +m0_readdata[20] => rdata_fifo_src_data[20].DATAIN +m0_readdata[21] => rdata_fifo_src_data[21].DATAIN +m0_readdata[22] => rdata_fifo_src_data[22].DATAIN +m0_readdata[23] => rdata_fifo_src_data[23].DATAIN +m0_readdata[24] => rdata_fifo_src_data[24].DATAIN +m0_readdata[25] => rdata_fifo_src_data[25].DATAIN +m0_readdata[26] => rdata_fifo_src_data[26].DATAIN +m0_readdata[27] => rdata_fifo_src_data[27].DATAIN +m0_readdata[28] => rdata_fifo_src_data[28].DATAIN +m0_readdata[29] => rdata_fifo_src_data[29].DATAIN +m0_readdata[30] => rdata_fifo_src_data[30].DATAIN +m0_readdata[31] => rdata_fifo_src_data[31].DATAIN +m0_waitrequest => cp_ready.IN0 +m0_write <= m0_write.DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[0] <= cp_data[0].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[1] <= cp_data[1].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[2] <= cp_data[2].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[3] <= cp_data[3].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[4] <= cp_data[4].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[5] <= cp_data[5].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[6] <= cp_data[6].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[7] <= cp_data[7].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[8] <= cp_data[8].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[9] <= cp_data[9].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[10] <= cp_data[10].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[11] <= cp_data[11].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[12] <= cp_data[12].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[13] <= cp_data[13].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[14] <= cp_data[14].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[15] <= cp_data[15].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[16] <= cp_data[16].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[17] <= cp_data[17].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[18] <= cp_data[18].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[19] <= cp_data[19].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[20] <= cp_data[20].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[21] <= cp_data[21].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[22] <= cp_data[22].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[23] <= cp_data[23].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[24] <= cp_data[24].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[25] <= cp_data[25].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[26] <= cp_data[26].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[27] <= cp_data[27].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[28] <= cp_data[28].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[29] <= cp_data[29].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[30] <= cp_data[30].DB_MAX_OUTPUT_PORT_TYPE +m0_writedata[31] <= cp_data[31].DB_MAX_OUTPUT_PORT_TYPE +m0_readdatavalid => rdata_fifo_src_valid.DATAIN +m0_debugaccess <= cp_data[92].DB_MAX_OUTPUT_PORT_TYPE +m0_lock <= m0_lock.DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[0] <= +rf_source_data[1] <= +rf_source_data[2] <= +rf_source_data[3] <= +rf_source_data[4] <= +rf_source_data[5] <= +rf_source_data[6] <= +rf_source_data[7] <= +rf_source_data[8] <= +rf_source_data[9] <= +rf_source_data[10] <= +rf_source_data[11] <= +rf_source_data[12] <= +rf_source_data[13] <= +rf_source_data[14] <= +rf_source_data[15] <= +rf_source_data[16] <= +rf_source_data[17] <= +rf_source_data[18] <= +rf_source_data[19] <= +rf_source_data[20] <= +rf_source_data[21] <= +rf_source_data[22] <= +rf_source_data[23] <= +rf_source_data[24] <= +rf_source_data[25] <= +rf_source_data[26] <= +rf_source_data[27] <= +rf_source_data[28] <= +rf_source_data[29] <= +rf_source_data[30] <= +rf_source_data[31] <= +rf_source_data[32] <= cp_data[32].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[33] <= cp_data[33].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[34] <= cp_data[34].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[35] <= cp_data[35].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[36] <= cp_data[36].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[37] <= cp_data[37].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[38] <= cp_data[38].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[39] <= cp_data[39].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[40] <= cp_data[40].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[41] <= cp_data[41].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[42] <= cp_data[42].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[43] <= cp_data[43].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[44] <= cp_data[44].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[45] <= cp_data[45].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[46] <= cp_data[46].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[47] <= cp_data[47].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[48] <= cp_data[48].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[49] <= cp_data[49].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[50] <= cp_data[50].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[51] <= cp_data[51].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[52] <= cp_data[52].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[53] <= cp_data[53].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[54] <= cp_data[54].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[55] <= cp_data[55].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[56] <= cp_data[56].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[57] <= cp_data[57].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[58] <= cp_data[58].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[59] <= cp_data[59].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[60] <= cp_data[60].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[61] <= cp_data[61].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[62] <= cp_data[62].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[63] <= cp_data[63].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[64] <= cp_data[64].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[65] <= cp_data[65].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[66] <= cp_data[66].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[67] <= cp_data[67].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[68] <= cp_data[68].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[69] <= cp_data[69].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[70] <= cp_data[70].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[71] <= cp_data[71].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[72] <= cp_data[72].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[73] <= cp_data[73].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[74] <= cp_data[74].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[75] <= cp_data[75].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[76] <= cp_data[76].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[77] <= cp_data[77].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[78] <= cp_data[78].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[79] <= cp_data[79].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[80] <= cp_data[80].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[81] <= cp_data[81].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[82] <= cp_data[82].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[83] <= cp_data[83].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[84] <= cp_data[84].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[85] <= cp_data[85].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[86] <= cp_data[86].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[87] <= cp_data[87].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[88] <= cp_data[88].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[89] <= cp_data[89].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[90] <= cp_data[90].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[91] <= cp_data[91].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[92] <= cp_data[92].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[93] <= +rf_source_data[94] <= +rf_source_data[95] <= cp_data[95].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[96] <= cp_data[96].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[97] <= cp_data[97].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[98] <= cp_data[98].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[99] <= cp_data[99].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[100] <= cp_data[100].DB_MAX_OUTPUT_PORT_TYPE +rf_source_data[101] <= nonposted_write_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +rf_source_valid <= rf_source_valid.DB_MAX_OUTPUT_PORT_TYPE +rf_source_startofpacket <= cp_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +rf_source_endofpacket <= cp_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +rf_source_ready => cp_ready.IN1 +rf_source_ready => m0_write.IN1 +rf_source_ready => m0_lock.IN1 +rf_source_ready => rf_source_valid.IN1 +rf_source_ready => m0_read.IN1 +rf_sink_data[0] => ~NO_FANOUT~ +rf_sink_data[1] => ~NO_FANOUT~ +rf_sink_data[2] => ~NO_FANOUT~ +rf_sink_data[3] => ~NO_FANOUT~ +rf_sink_data[4] => ~NO_FANOUT~ +rf_sink_data[5] => ~NO_FANOUT~ +rf_sink_data[6] => ~NO_FANOUT~ +rf_sink_data[7] => ~NO_FANOUT~ +rf_sink_data[8] => ~NO_FANOUT~ +rf_sink_data[9] => ~NO_FANOUT~ +rf_sink_data[10] => ~NO_FANOUT~ +rf_sink_data[11] => ~NO_FANOUT~ +rf_sink_data[12] => ~NO_FANOUT~ +rf_sink_data[13] => ~NO_FANOUT~ +rf_sink_data[14] => ~NO_FANOUT~ +rf_sink_data[15] => ~NO_FANOUT~ +rf_sink_data[16] => ~NO_FANOUT~ +rf_sink_data[17] => ~NO_FANOUT~ +rf_sink_data[18] => ~NO_FANOUT~ +rf_sink_data[19] => ~NO_FANOUT~ +rf_sink_data[20] => ~NO_FANOUT~ +rf_sink_data[21] => ~NO_FANOUT~ +rf_sink_data[22] => ~NO_FANOUT~ +rf_sink_data[23] => ~NO_FANOUT~ +rf_sink_data[24] => ~NO_FANOUT~ +rf_sink_data[25] => ~NO_FANOUT~ +rf_sink_data[26] => ~NO_FANOUT~ +rf_sink_data[27] => ~NO_FANOUT~ +rf_sink_data[28] => ~NO_FANOUT~ +rf_sink_data[29] => ~NO_FANOUT~ +rf_sink_data[30] => ~NO_FANOUT~ +rf_sink_data[31] => ~NO_FANOUT~ +rf_sink_data[32] => rp_data[32].DATAIN +rf_sink_data[33] => rp_data[33].DATAIN +rf_sink_data[34] => rp_data[34].DATAIN +rf_sink_data[35] => rp_data[35].DATAIN +rf_sink_data[36] => rf_sink_addr[0].IN1 +rf_sink_data[37] => rf_sink_addr[1].IN1 +rf_sink_data[38] => rf_sink_addr[2].IN1 +rf_sink_data[39] => rf_sink_addr[3].IN1 +rf_sink_data[40] => rf_sink_addr[4].IN1 +rf_sink_data[41] => rf_sink_addr[5].IN1 +rf_sink_data[42] => rf_sink_addr[6].IN1 +rf_sink_data[43] => rf_sink_addr[7].IN1 +rf_sink_data[44] => rf_sink_addr[8].IN1 +rf_sink_data[45] => rf_sink_addr[9].IN1 +rf_sink_data[46] => rf_sink_addr[10].IN1 +rf_sink_data[47] => rf_sink_addr[11].IN1 +rf_sink_data[48] => rf_sink_addr[12].IN1 +rf_sink_data[49] => rf_sink_addr[13].IN1 +rf_sink_data[50] => rf_sink_addr[14].IN1 +rf_sink_data[51] => rf_sink_addr[15].IN1 +rf_sink_data[52] => rf_sink_addr[16].IN1 +rf_sink_data[53] => rf_sink_addr[17].IN1 +rf_sink_data[54] => rf_sink_addr[18].IN1 +rf_sink_data[55] => rf_sink_addr[19].IN1 +rf_sink_data[56] => rf_sink_addr[20].IN1 +rf_sink_data[57] => rf_sink_addr[21].IN1 +rf_sink_data[58] => rf_sink_addr[22].IN1 +rf_sink_data[59] => rf_sink_addr[23].IN1 +rf_sink_data[60] => rf_sink_addr[24].IN1 +rf_sink_data[61] => rf_sink_addr[25].IN1 +rf_sink_data[62] => rf_sink_compressed.IN1 +rf_sink_data[63] => rp_data[63].DATAIN +rf_sink_data[64] => comb.OUTPUTSELECT +rf_sink_data[64] => rp_data[64].DATAIN +rf_sink_data[65] => rp_data.IN0 +rf_sink_data[66] => rp_data[66].DATAIN +rf_sink_data[67] => rp_data[67].DATAIN +rf_sink_data[68] => rf_sink_byte_cnt[0].IN1 +rf_sink_data[69] => rf_sink_byte_cnt[1].IN1 +rf_sink_data[70] => rf_sink_byte_cnt[2].IN1 +rf_sink_data[71] => rf_sink_burstwrap[0].IN1 +rf_sink_data[72] => rf_sink_burstwrap[1].IN1 +rf_sink_data[73] => rf_sink_burstwrap[2].IN1 +rf_sink_data[74] => rf_sink_burstsize[0].IN1 +rf_sink_data[75] => rf_sink_burstsize[1].IN1 +rf_sink_data[76] => rf_sink_burstsize[2].IN1 +rf_sink_data[77] => rp_data[77].DATAIN +rf_sink_data[78] => rp_data[78].DATAIN +rf_sink_data[79] => rp_data[79].DATAIN +rf_sink_data[80] => rp_data[80].DATAIN +rf_sink_data[81] => rp_data[81].DATAIN +rf_sink_data[82] => rp_data[82].DATAIN +rf_sink_data[83] => rp_data[87].DATAIN +rf_sink_data[84] => rp_data[88].DATAIN +rf_sink_data[85] => rp_data[89].DATAIN +rf_sink_data[86] => rp_data[90].DATAIN +rf_sink_data[87] => rp_data[83].DATAIN +rf_sink_data[88] => rp_data[84].DATAIN +rf_sink_data[89] => rp_data[85].DATAIN +rf_sink_data[90] => rp_data[86].DATAIN +rf_sink_data[91] => rp_data[91].DATAIN +rf_sink_data[92] => rp_data[92].DATAIN +rf_sink_data[93] => rp_data[93].DATAIN +rf_sink_data[94] => rp_data[94].DATAIN +rf_sink_data[95] => rp_data[95].DATAIN +rf_sink_data[96] => rp_data[96].DATAIN +rf_sink_data[97] => rp_data[97].DATAIN +rf_sink_data[98] => rp_data[98].DATAIN +rf_sink_data[99] => ~NO_FANOUT~ +rf_sink_data[100] => ~NO_FANOUT~ +rf_sink_data[101] => rdata_fifo_sink_ready.IN0 +rf_sink_data[101] => comb.IN0 +rf_sink_valid => rdata_fifo_sink_ready.IN1 +rf_sink_valid => comb.IN1 +rf_sink_startofpacket => comb.DATAA +rf_sink_endofpacket => rf_sink_endofpacket.IN1 +rf_sink_ready <= altera_merlin_burst_uncompressor:uncompressor.sink_ready +rdata_fifo_src_data[0] <= m0_readdata[0].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[1] <= m0_readdata[1].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[2] <= m0_readdata[2].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[3] <= m0_readdata[3].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[4] <= m0_readdata[4].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[5] <= m0_readdata[5].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[6] <= m0_readdata[6].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[7] <= m0_readdata[7].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[8] <= m0_readdata[8].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[9] <= m0_readdata[9].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[10] <= m0_readdata[10].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[11] <= m0_readdata[11].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[12] <= m0_readdata[12].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[13] <= m0_readdata[13].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[14] <= m0_readdata[14].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[15] <= m0_readdata[15].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[16] <= m0_readdata[16].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[17] <= m0_readdata[17].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[18] <= m0_readdata[18].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[19] <= m0_readdata[19].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[20] <= m0_readdata[20].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[21] <= m0_readdata[21].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[22] <= m0_readdata[22].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[23] <= m0_readdata[23].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[24] <= m0_readdata[24].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[25] <= m0_readdata[25].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[26] <= m0_readdata[26].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[27] <= m0_readdata[27].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[28] <= m0_readdata[28].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[29] <= m0_readdata[29].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[30] <= m0_readdata[30].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_data[31] <= m0_readdata[31].DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_valid <= m0_readdatavalid.DB_MAX_OUTPUT_PORT_TYPE +rdata_fifo_src_ready => ~NO_FANOUT~ +rdata_fifo_sink_data[0] => rp_data[0].DATAIN +rdata_fifo_sink_data[1] => rp_data[1].DATAIN +rdata_fifo_sink_data[2] => rp_data[2].DATAIN +rdata_fifo_sink_data[3] => rp_data[3].DATAIN +rdata_fifo_sink_data[4] => rp_data[4].DATAIN +rdata_fifo_sink_data[5] => rp_data[5].DATAIN +rdata_fifo_sink_data[6] => rp_data[6].DATAIN +rdata_fifo_sink_data[7] => rp_data[7].DATAIN +rdata_fifo_sink_data[8] => rp_data[8].DATAIN +rdata_fifo_sink_data[9] => rp_data[9].DATAIN +rdata_fifo_sink_data[10] => rp_data[10].DATAIN +rdata_fifo_sink_data[11] => rp_data[11].DATAIN +rdata_fifo_sink_data[12] => rp_data[12].DATAIN +rdata_fifo_sink_data[13] => rp_data[13].DATAIN +rdata_fifo_sink_data[14] => rp_data[14].DATAIN +rdata_fifo_sink_data[15] => rp_data[15].DATAIN +rdata_fifo_sink_data[16] => rp_data[16].DATAIN +rdata_fifo_sink_data[17] => rp_data[17].DATAIN +rdata_fifo_sink_data[18] => rp_data[18].DATAIN +rdata_fifo_sink_data[19] => rp_data[19].DATAIN +rdata_fifo_sink_data[20] => rp_data[20].DATAIN +rdata_fifo_sink_data[21] => rp_data[21].DATAIN +rdata_fifo_sink_data[22] => rp_data[22].DATAIN +rdata_fifo_sink_data[23] => rp_data[23].DATAIN +rdata_fifo_sink_data[24] => rp_data[24].DATAIN +rdata_fifo_sink_data[25] => rp_data[25].DATAIN +rdata_fifo_sink_data[26] => rp_data[26].DATAIN +rdata_fifo_sink_data[27] => rp_data[27].DATAIN +rdata_fifo_sink_data[28] => rp_data[28].DATAIN +rdata_fifo_sink_data[29] => rp_data[29].DATAIN +rdata_fifo_sink_data[30] => rp_data[30].DATAIN +rdata_fifo_sink_data[31] => rp_data[31].DATAIN +rdata_fifo_sink_valid => rp_valid.IN1 +rdata_fifo_sink_valid => rdata_fifo_sink_ready.IN0 +rdata_fifo_sink_valid => comb.IN1 +rdata_fifo_sink_ready <= rdata_fifo_sink_ready.DB_MAX_OUTPUT_PORT_TYPE +cp_ready <= cp_ready.DB_MAX_OUTPUT_PORT_TYPE +cp_valid => local_lock.IN0 +cp_valid => local_write.IN0 +cp_valid => local_read.IN0 +cp_valid => local_compressed_read.IN0 +cp_data[0] => m0_writedata[0].DATAIN +cp_data[1] => m0_writedata[1].DATAIN +cp_data[2] => m0_writedata[2].DATAIN +cp_data[3] => m0_writedata[3].DATAIN +cp_data[4] => m0_writedata[4].DATAIN +cp_data[5] => m0_writedata[5].DATAIN +cp_data[6] => m0_writedata[6].DATAIN +cp_data[7] => m0_writedata[7].DATAIN +cp_data[8] => m0_writedata[8].DATAIN +cp_data[9] => m0_writedata[9].DATAIN +cp_data[10] => m0_writedata[10].DATAIN +cp_data[11] => m0_writedata[11].DATAIN +cp_data[12] => m0_writedata[12].DATAIN +cp_data[13] => m0_writedata[13].DATAIN +cp_data[14] => m0_writedata[14].DATAIN +cp_data[15] => m0_writedata[15].DATAIN +cp_data[16] => m0_writedata[16].DATAIN +cp_data[17] => m0_writedata[17].DATAIN +cp_data[18] => m0_writedata[18].DATAIN +cp_data[19] => m0_writedata[19].DATAIN +cp_data[20] => m0_writedata[20].DATAIN +cp_data[21] => m0_writedata[21].DATAIN +cp_data[22] => m0_writedata[22].DATAIN +cp_data[23] => m0_writedata[23].DATAIN +cp_data[24] => m0_writedata[24].DATAIN +cp_data[25] => m0_writedata[25].DATAIN +cp_data[26] => m0_writedata[26].DATAIN +cp_data[27] => m0_writedata[27].DATAIN +cp_data[28] => m0_writedata[28].DATAIN +cp_data[29] => m0_writedata[29].DATAIN +cp_data[30] => m0_writedata[30].DATAIN +cp_data[31] => m0_writedata[31].DATAIN +cp_data[32] => rf_source_data[32].DATAIN +cp_data[32] => m0_byteenable[0].DATAIN +cp_data[33] => rf_source_data[33].DATAIN +cp_data[33] => m0_byteenable[1].DATAIN +cp_data[34] => rf_source_data[34].DATAIN +cp_data[34] => m0_byteenable[2].DATAIN +cp_data[35] => rf_source_data[35].DATAIN +cp_data[35] => m0_byteenable[3].DATAIN +cp_data[36] => rf_source_data[36].DATAIN +cp_data[37] => rf_source_data[37].DATAIN +cp_data[38] => rf_source_data[38].DATAIN +cp_data[38] => m0_address[2].DATAIN +cp_data[39] => rf_source_data[39].DATAIN +cp_data[39] => m0_address[3].DATAIN +cp_data[40] => rf_source_data[40].DATAIN +cp_data[40] => m0_address[4].DATAIN +cp_data[41] => rf_source_data[41].DATAIN +cp_data[41] => m0_address[5].DATAIN +cp_data[42] => rf_source_data[42].DATAIN +cp_data[42] => m0_address[6].DATAIN +cp_data[43] => rf_source_data[43].DATAIN +cp_data[43] => m0_address[7].DATAIN +cp_data[44] => rf_source_data[44].DATAIN +cp_data[44] => m0_address[8].DATAIN +cp_data[45] => rf_source_data[45].DATAIN +cp_data[45] => m0_address[9].DATAIN +cp_data[46] => rf_source_data[46].DATAIN +cp_data[46] => m0_address[10].DATAIN +cp_data[47] => rf_source_data[47].DATAIN +cp_data[47] => m0_address[11].DATAIN +cp_data[48] => rf_source_data[48].DATAIN +cp_data[48] => m0_address[12].DATAIN +cp_data[49] => rf_source_data[49].DATAIN +cp_data[49] => m0_address[13].DATAIN +cp_data[50] => rf_source_data[50].DATAIN +cp_data[50] => m0_address[14].DATAIN +cp_data[51] => rf_source_data[51].DATAIN +cp_data[51] => m0_address[15].DATAIN +cp_data[52] => rf_source_data[52].DATAIN +cp_data[52] => m0_address[16].DATAIN +cp_data[53] => rf_source_data[53].DATAIN +cp_data[53] => m0_address[17].DATAIN +cp_data[54] => rf_source_data[54].DATAIN +cp_data[54] => m0_address[18].DATAIN +cp_data[55] => rf_source_data[55].DATAIN +cp_data[55] => m0_address[19].DATAIN +cp_data[56] => rf_source_data[56].DATAIN +cp_data[56] => m0_address[20].DATAIN +cp_data[57] => rf_source_data[57].DATAIN +cp_data[57] => m0_address[21].DATAIN +cp_data[58] => rf_source_data[58].DATAIN +cp_data[58] => m0_address[22].DATAIN +cp_data[59] => rf_source_data[59].DATAIN +cp_data[59] => m0_address[23].DATAIN +cp_data[60] => rf_source_data[60].DATAIN +cp_data[60] => m0_address[24].DATAIN +cp_data[61] => rf_source_data[61].DATAIN +cp_data[61] => m0_address[25].DATAIN +cp_data[62] => local_compressed_read.IN1 +cp_data[62] => rf_source_data[62].DATAIN +cp_data[63] => rf_source_data[63].DATAIN +cp_data[63] => comb.IN1 +cp_data[64] => local_write.IN1 +cp_data[64] => rf_source_data[64].DATAIN +cp_data[65] => local_read.IN1 +cp_data[65] => rf_source_data[65].DATAIN +cp_data[66] => local_lock.IN1 +cp_data[66] => rf_source_data[66].DATAIN +cp_data[67] => rf_source_data[67].DATAIN +cp_data[68] => m0_burstcount.DATAA +cp_data[68] => rf_source_data[68].DATAIN +cp_data[69] => m0_burstcount.DATAA +cp_data[69] => rf_source_data[69].DATAIN +cp_data[70] => m0_burstcount.DATAA +cp_data[70] => rf_source_data[70].DATAIN +cp_data[71] => rf_source_data[71].DATAIN +cp_data[72] => rf_source_data[72].DATAIN +cp_data[73] => rf_source_data[73].DATAIN +cp_data[74] => rf_source_data[74].DATAIN +cp_data[75] => rf_source_data[75].DATAIN +cp_data[76] => rf_source_data[76].DATAIN +cp_data[77] => rf_source_data[77].DATAIN +cp_data[78] => rf_source_data[78].DATAIN +cp_data[79] => rf_source_data[79].DATAIN +cp_data[80] => rf_source_data[80].DATAIN +cp_data[81] => rf_source_data[81].DATAIN +cp_data[82] => rf_source_data[82].DATAIN +cp_data[83] => rf_source_data[83].DATAIN +cp_data[84] => rf_source_data[84].DATAIN +cp_data[85] => rf_source_data[85].DATAIN +cp_data[86] => rf_source_data[86].DATAIN +cp_data[87] => rf_source_data[87].DATAIN +cp_data[88] => rf_source_data[88].DATAIN +cp_data[89] => rf_source_data[89].DATAIN +cp_data[90] => rf_source_data[90].DATAIN +cp_data[91] => rf_source_data[91].DATAIN +cp_data[92] => rf_source_data[92].DATAIN +cp_data[92] => m0_debugaccess.DATAIN +cp_data[93] => ~NO_FANOUT~ +cp_data[94] => ~NO_FANOUT~ +cp_data[95] => rf_source_data[95].DATAIN +cp_data[96] => rf_source_data[96].DATAIN +cp_data[97] => rf_source_data[97].DATAIN +cp_data[98] => rf_source_data[98].DATAIN +cp_data[99] => rf_source_data[99].DATAIN +cp_data[100] => rf_source_data[100].DATAIN +cp_channel[0] => ~NO_FANOUT~ +cp_channel[1] => ~NO_FANOUT~ +cp_channel[2] => ~NO_FANOUT~ +cp_channel[3] => ~NO_FANOUT~ +cp_channel[4] => ~NO_FANOUT~ +cp_channel[5] => ~NO_FANOUT~ +cp_channel[6] => ~NO_FANOUT~ +cp_channel[7] => ~NO_FANOUT~ +cp_channel[8] => ~NO_FANOUT~ +cp_channel[9] => ~NO_FANOUT~ +cp_channel[10] => ~NO_FANOUT~ +cp_startofpacket => rf_source_startofpacket.DATAIN +cp_endofpacket => nonposted_write_endofpacket.IN1 +cp_endofpacket => rf_source_endofpacket.DATAIN +rp_ready => rp_ready.IN1 +rp_valid <= rp_valid.DB_MAX_OUTPUT_PORT_TYPE +rp_data[0] <= rdata_fifo_sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +rp_data[1] <= rdata_fifo_sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +rp_data[2] <= rdata_fifo_sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +rp_data[3] <= rdata_fifo_sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +rp_data[4] <= rdata_fifo_sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +rp_data[5] <= rdata_fifo_sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +rp_data[6] <= rdata_fifo_sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +rp_data[7] <= rdata_fifo_sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +rp_data[8] <= rdata_fifo_sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +rp_data[9] <= rdata_fifo_sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +rp_data[10] <= rdata_fifo_sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +rp_data[11] <= rdata_fifo_sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +rp_data[12] <= rdata_fifo_sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +rp_data[13] <= rdata_fifo_sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +rp_data[14] <= rdata_fifo_sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +rp_data[15] <= rdata_fifo_sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +rp_data[16] <= rdata_fifo_sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +rp_data[17] <= rdata_fifo_sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +rp_data[18] <= rdata_fifo_sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +rp_data[19] <= rdata_fifo_sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +rp_data[20] <= rdata_fifo_sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +rp_data[21] <= rdata_fifo_sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +rp_data[22] <= rdata_fifo_sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +rp_data[23] <= rdata_fifo_sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +rp_data[24] <= rdata_fifo_sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +rp_data[25] <= rdata_fifo_sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +rp_data[26] <= rdata_fifo_sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +rp_data[27] <= rdata_fifo_sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +rp_data[28] <= rdata_fifo_sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +rp_data[29] <= rdata_fifo_sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +rp_data[30] <= rdata_fifo_sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +rp_data[31] <= rdata_fifo_sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +rp_data[32] <= rf_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +rp_data[33] <= rf_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +rp_data[34] <= rf_sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +rp_data[35] <= rf_sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +rp_data[36] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[37] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[38] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[39] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[40] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[41] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[42] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[43] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[44] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[45] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[46] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[47] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[48] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[49] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[50] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[51] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[52] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[53] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[54] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[55] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[56] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[57] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[58] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[59] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[60] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[61] <= altera_merlin_burst_uncompressor:uncompressor.source_addr +rp_data[62] <= altera_merlin_burst_uncompressor:uncompressor.source_is_compressed +rp_data[63] <= rf_sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +rp_data[64] <= rf_sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +rp_data[65] <= rp_data.DB_MAX_OUTPUT_PORT_TYPE +rp_data[66] <= rf_sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +rp_data[67] <= rf_sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +rp_data[68] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt +rp_data[69] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt +rp_data[70] <= altera_merlin_burst_uncompressor:uncompressor.source_byte_cnt +rp_data[71] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap +rp_data[72] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap +rp_data[73] <= altera_merlin_burst_uncompressor:uncompressor.source_burstwrap +rp_data[74] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize +rp_data[75] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize +rp_data[76] <= altera_merlin_burst_uncompressor:uncompressor.source_burstsize +rp_data[77] <= rf_sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +rp_data[78] <= rf_sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +rp_data[79] <= rf_sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +rp_data[80] <= rf_sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +rp_data[81] <= rf_sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +rp_data[82] <= rf_sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +rp_data[83] <= rf_sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +rp_data[84] <= rf_sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +rp_data[85] <= rf_sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +rp_data[86] <= rf_sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +rp_data[87] <= rf_sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +rp_data[88] <= rf_sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +rp_data[89] <= rf_sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +rp_data[90] <= rf_sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +rp_data[91] <= rf_sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +rp_data[92] <= rf_sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +rp_data[93] <= rf_sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +rp_data[94] <= rf_sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +rp_data[95] <= rf_sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +rp_data[96] <= rf_sink_data[96].DB_MAX_OUTPUT_PORT_TYPE +rp_data[97] <= rf_sink_data[97].DB_MAX_OUTPUT_PORT_TYPE +rp_data[98] <= rf_sink_data[98].DB_MAX_OUTPUT_PORT_TYPE +rp_data[99] <= +rp_data[100] <= +rp_startofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_startofpacket +rp_endofpacket <= altera_merlin_burst_uncompressor:uncompressor.source_endofpacket + + +|de0_nano_system|system:inst_cpu|altera_merlin_slave_agent:rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor +clk => burst_uncompress_address_offset[0].CLK +clk => burst_uncompress_address_offset[1].CLK +clk => burst_uncompress_address_offset[2].CLK +clk => burst_uncompress_address_offset[3].CLK +clk => burst_uncompress_address_offset[4].CLK +clk => burst_uncompress_address_offset[5].CLK +clk => burst_uncompress_address_offset[6].CLK +clk => burst_uncompress_address_offset[7].CLK +clk => burst_uncompress_address_offset[8].CLK +clk => burst_uncompress_address_offset[9].CLK +clk => burst_uncompress_address_offset[10].CLK +clk => burst_uncompress_address_offset[11].CLK +clk => burst_uncompress_address_offset[12].CLK +clk => burst_uncompress_address_offset[13].CLK +clk => burst_uncompress_address_offset[14].CLK +clk => burst_uncompress_address_offset[15].CLK +clk => burst_uncompress_address_offset[16].CLK +clk => burst_uncompress_address_offset[17].CLK +clk => burst_uncompress_address_offset[18].CLK +clk => burst_uncompress_address_offset[19].CLK +clk => burst_uncompress_address_offset[20].CLK +clk => burst_uncompress_address_offset[21].CLK +clk => burst_uncompress_address_offset[22].CLK +clk => burst_uncompress_address_offset[23].CLK +clk => burst_uncompress_address_offset[24].CLK +clk => burst_uncompress_address_offset[25].CLK +clk => burst_uncompress_address_base[0].CLK +clk => burst_uncompress_address_base[1].CLK +clk => burst_uncompress_address_base[2].CLK +clk => burst_uncompress_address_base[3].CLK +clk => burst_uncompress_address_base[4].CLK +clk => burst_uncompress_address_base[5].CLK +clk => burst_uncompress_address_base[6].CLK +clk => burst_uncompress_address_base[7].CLK +clk => burst_uncompress_address_base[8].CLK +clk => burst_uncompress_address_base[9].CLK +clk => burst_uncompress_address_base[10].CLK +clk => burst_uncompress_address_base[11].CLK +clk => burst_uncompress_address_base[12].CLK +clk => burst_uncompress_address_base[13].CLK +clk => burst_uncompress_address_base[14].CLK +clk => burst_uncompress_address_base[15].CLK +clk => burst_uncompress_address_base[16].CLK +clk => burst_uncompress_address_base[17].CLK +clk => burst_uncompress_address_base[18].CLK +clk => burst_uncompress_address_base[19].CLK +clk => burst_uncompress_address_base[20].CLK +clk => burst_uncompress_address_base[21].CLK +clk => burst_uncompress_address_base[22].CLK +clk => burst_uncompress_address_base[23].CLK +clk => burst_uncompress_address_base[24].CLK +clk => burst_uncompress_address_base[25].CLK +clk => burst_uncompress_byte_counter[0].CLK +clk => burst_uncompress_byte_counter[1].CLK +clk => burst_uncompress_byte_counter[2].CLK +clk => burst_uncompress_busy.CLK +reset => burst_uncompress_address_offset[0].ACLR +reset => burst_uncompress_address_offset[1].ACLR +reset => burst_uncompress_address_offset[2].ACLR +reset => burst_uncompress_address_offset[3].ACLR +reset => burst_uncompress_address_offset[4].ACLR +reset => burst_uncompress_address_offset[5].ACLR +reset => burst_uncompress_address_offset[6].ACLR +reset => burst_uncompress_address_offset[7].ACLR +reset => burst_uncompress_address_offset[8].ACLR +reset => burst_uncompress_address_offset[9].ACLR +reset => burst_uncompress_address_offset[10].ACLR +reset => burst_uncompress_address_offset[11].ACLR +reset => burst_uncompress_address_offset[12].ACLR +reset => burst_uncompress_address_offset[13].ACLR +reset => burst_uncompress_address_offset[14].ACLR +reset => burst_uncompress_address_offset[15].ACLR +reset => burst_uncompress_address_offset[16].ACLR +reset => burst_uncompress_address_offset[17].ACLR +reset => burst_uncompress_address_offset[18].ACLR +reset => burst_uncompress_address_offset[19].ACLR +reset => burst_uncompress_address_offset[20].ACLR +reset => burst_uncompress_address_offset[21].ACLR +reset => burst_uncompress_address_offset[22].ACLR +reset => burst_uncompress_address_offset[23].ACLR +reset => burst_uncompress_address_offset[24].ACLR +reset => burst_uncompress_address_offset[25].ACLR +reset => burst_uncompress_address_base[0].ACLR +reset => burst_uncompress_address_base[1].ACLR +reset => burst_uncompress_address_base[2].ACLR +reset => burst_uncompress_address_base[3].ACLR +reset => burst_uncompress_address_base[4].ACLR +reset => burst_uncompress_address_base[5].ACLR +reset => burst_uncompress_address_base[6].ACLR +reset => burst_uncompress_address_base[7].ACLR +reset => burst_uncompress_address_base[8].ACLR +reset => burst_uncompress_address_base[9].ACLR +reset => burst_uncompress_address_base[10].ACLR +reset => burst_uncompress_address_base[11].ACLR +reset => burst_uncompress_address_base[12].ACLR +reset => burst_uncompress_address_base[13].ACLR +reset => burst_uncompress_address_base[14].ACLR +reset => burst_uncompress_address_base[15].ACLR +reset => burst_uncompress_address_base[16].ACLR +reset => burst_uncompress_address_base[17].ACLR +reset => burst_uncompress_address_base[18].ACLR +reset => burst_uncompress_address_base[19].ACLR +reset => burst_uncompress_address_base[20].ACLR +reset => burst_uncompress_address_base[21].ACLR +reset => burst_uncompress_address_base[22].ACLR +reset => burst_uncompress_address_base[23].ACLR +reset => burst_uncompress_address_base[24].ACLR +reset => burst_uncompress_address_base[25].ACLR +reset => burst_uncompress_byte_counter[0].ACLR +reset => burst_uncompress_byte_counter[1].ACLR +reset => burst_uncompress_byte_counter[2].ACLR +reset => burst_uncompress_busy.ACLR +sink_startofpacket => source_startofpacket.IN1 +sink_endofpacket => source_endofpacket.IN1 +sink_valid => first_packet_beat.IN1 +sink_valid => last_packet_beat.IN1 +sink_valid => last_packet_beat.IN1 +sink_valid => always0.IN1 +sink_valid => sink_ready.IN0 +sink_valid => source_valid.DATAIN +sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE +sink_addr[0] => burst_uncompress_address_base.IN0 +sink_addr[0] => comb.DATAB +sink_addr[0] => source_addr.DATAB +sink_addr[1] => burst_uncompress_address_base.IN0 +sink_addr[1] => comb.DATAB +sink_addr[1] => source_addr.DATAB +sink_addr[2] => burst_uncompress_address_base.IN0 +sink_addr[2] => comb.DATAB +sink_addr[2] => source_addr.DATAB +sink_addr[3] => burst_uncompress_address_base.IN0 +sink_addr[3] => comb.DATAB +sink_addr[3] => source_addr.DATAB +sink_addr[4] => burst_uncompress_address_base.IN0 +sink_addr[4] => comb.DATAB +sink_addr[4] => source_addr.DATAB +sink_addr[5] => burst_uncompress_address_base.IN0 +sink_addr[5] => comb.DATAB +sink_addr[5] => source_addr.DATAB +sink_addr[6] => burst_uncompress_address_base.IN0 +sink_addr[6] => comb.DATAB +sink_addr[6] => source_addr.DATAB +sink_addr[7] => burst_uncompress_address_base.IN0 +sink_addr[7] => comb.DATAB +sink_addr[7] => source_addr.DATAB +sink_addr[8] => burst_uncompress_address_base.IN0 +sink_addr[8] => comb.DATAB +sink_addr[8] => source_addr.DATAB +sink_addr[9] => burst_uncompress_address_base.IN0 +sink_addr[9] => comb.DATAB +sink_addr[9] => source_addr.DATAB +sink_addr[10] => burst_uncompress_address_base.IN0 +sink_addr[10] => comb.DATAB +sink_addr[10] => source_addr.DATAB +sink_addr[11] => burst_uncompress_address_base.IN0 +sink_addr[11] => comb.DATAB +sink_addr[11] => source_addr.DATAB +sink_addr[12] => burst_uncompress_address_base.IN0 +sink_addr[12] => comb.DATAB +sink_addr[12] => source_addr.DATAB +sink_addr[13] => burst_uncompress_address_base.IN0 +sink_addr[13] => comb.DATAB +sink_addr[13] => source_addr.DATAB +sink_addr[14] => burst_uncompress_address_base.IN0 +sink_addr[14] => comb.DATAB +sink_addr[14] => source_addr.DATAB +sink_addr[15] => burst_uncompress_address_base.IN0 +sink_addr[15] => comb.DATAB +sink_addr[15] => source_addr.DATAB +sink_addr[16] => burst_uncompress_address_base.IN0 +sink_addr[16] => comb.DATAB +sink_addr[16] => source_addr.DATAB +sink_addr[17] => burst_uncompress_address_base.IN0 +sink_addr[17] => comb.DATAB +sink_addr[17] => source_addr.DATAB +sink_addr[18] => burst_uncompress_address_base.IN0 +sink_addr[18] => comb.DATAB +sink_addr[18] => source_addr.DATAB +sink_addr[19] => burst_uncompress_address_base.IN0 +sink_addr[19] => comb.DATAB +sink_addr[19] => source_addr.DATAB +sink_addr[20] => burst_uncompress_address_base.IN0 +sink_addr[20] => comb.DATAB +sink_addr[20] => source_addr.DATAB +sink_addr[21] => burst_uncompress_address_base.IN0 +sink_addr[21] => comb.DATAB +sink_addr[21] => source_addr.DATAB +sink_addr[22] => burst_uncompress_address_base.IN0 +sink_addr[22] => comb.DATAB +sink_addr[22] => source_addr.DATAB +sink_addr[23] => burst_uncompress_address_base.IN0 +sink_addr[23] => comb.DATAB +sink_addr[23] => source_addr.DATAB +sink_addr[24] => burst_uncompress_address_base.IN0 +sink_addr[24] => comb.DATAB +sink_addr[24] => source_addr.DATAB +sink_addr[25] => burst_uncompress_address_base.IN0 +sink_addr[25] => comb.DATAB +sink_addr[25] => source_addr.DATAB +sink_burstwrap[0] => p1_burst_uncompress_address_offset[0].IN1 +sink_burstwrap[0] => source_burstwrap[0].DATAIN +sink_burstwrap[0] => burst_uncompress_address_base.IN1 +sink_burstwrap[1] => p1_burst_uncompress_address_offset[1].IN1 +sink_burstwrap[1] => source_burstwrap[1].DATAIN +sink_burstwrap[1] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[2].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[25].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[24].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[23].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[22].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[21].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[20].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[19].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[18].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[17].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[16].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[15].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[14].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[13].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[12].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[11].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[10].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[9].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[8].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[7].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[6].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[5].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[4].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[3].IN1 +sink_burstwrap[2] => source_burstwrap[2].DATAIN +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_byte_cnt[0] => source_byte_cnt.DATAB +sink_byte_cnt[0] => Add1.IN6 +sink_byte_cnt[0] => Equal1.IN2 +sink_byte_cnt[1] => source_byte_cnt.DATAB +sink_byte_cnt[1] => Add1.IN5 +sink_byte_cnt[1] => Equal1.IN1 +sink_byte_cnt[2] => source_byte_cnt.DATAB +sink_byte_cnt[2] => Add1.IN4 +sink_byte_cnt[2] => Equal1.IN0 +sink_is_compressed => last_packet_beat.IN1 +sink_burstsize[0] => Decoder0.IN2 +sink_burstsize[0] => source_burstsize[0].DATAIN +sink_burstsize[1] => Decoder0.IN1 +sink_burstsize[1] => source_burstsize[1].DATAIN +sink_burstsize[2] => Decoder0.IN0 +sink_burstsize[2] => source_burstsize[2].DATAIN +source_startofpacket <= source_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +source_endofpacket <= source_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +source_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE +source_ready => always1.IN1 +source_ready => sink_ready.IN1 +source_addr[0] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[1] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[2] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[3] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[4] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[5] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[6] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[7] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[8] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[9] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[10] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[11] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[12] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[13] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[14] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[15] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[16] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[17] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[18] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[19] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[20] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[21] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[22] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[23] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[24] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[25] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_burstwrap[0] <= sink_burstwrap[0].DB_MAX_OUTPUT_PORT_TYPE +source_burstwrap[1] <= sink_burstwrap[1].DB_MAX_OUTPUT_PORT_TYPE +source_burstwrap[2] <= sink_burstwrap[2].DB_MAX_OUTPUT_PORT_TYPE +source_byte_cnt[0] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE +source_byte_cnt[1] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE +source_byte_cnt[2] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE +source_is_compressed <= +source_burstsize[0] <= sink_burstsize[0].DB_MAX_OUTPUT_PORT_TYPE +source_burstsize[1] <= sink_burstsize[1].DB_MAX_OUTPUT_PORT_TYPE +source_burstsize[2] <= sink_burstsize[2].DB_MAX_OUTPUT_PORT_TYPE + + +|de0_nano_system|system:inst_cpu|altera_avalon_sc_fifo:rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo +clk => csr_readdata[0]~reg0.CLK +clk => csr_readdata[1]~reg0.CLK +clk => csr_readdata[2]~reg0.CLK +clk => csr_readdata[3]~reg0.CLK +clk => csr_readdata[4]~reg0.CLK +clk => csr_readdata[5]~reg0.CLK +clk => csr_readdata[6]~reg0.CLK +clk => csr_readdata[7]~reg0.CLK +clk => csr_readdata[8]~reg0.CLK +clk => csr_readdata[9]~reg0.CLK +clk => csr_readdata[10]~reg0.CLK +clk => csr_readdata[11]~reg0.CLK +clk => csr_readdata[12]~reg0.CLK +clk => csr_readdata[13]~reg0.CLK +clk => csr_readdata[14]~reg0.CLK +clk => csr_readdata[15]~reg0.CLK +clk => csr_readdata[16]~reg0.CLK +clk => csr_readdata[17]~reg0.CLK +clk => csr_readdata[18]~reg0.CLK +clk => csr_readdata[19]~reg0.CLK +clk => csr_readdata[20]~reg0.CLK +clk => csr_readdata[21]~reg0.CLK +clk => csr_readdata[22]~reg0.CLK +clk => csr_readdata[23]~reg0.CLK +clk => csr_readdata[24]~reg0.CLK +clk => csr_readdata[25]~reg0.CLK +clk => csr_readdata[26]~reg0.CLK +clk => csr_readdata[27]~reg0.CLK +clk => csr_readdata[28]~reg0.CLK +clk => csr_readdata[29]~reg0.CLK +clk => csr_readdata[30]~reg0.CLK +clk => csr_readdata[31]~reg0.CLK +clk => mem_used[1].CLK +clk => mem_used[0].CLK +clk => mem[1][0].CLK +clk => mem[1][1].CLK +clk => mem[1][2].CLK +clk => mem[1][3].CLK +clk => mem[1][4].CLK +clk => mem[1][5].CLK +clk => mem[1][6].CLK +clk => mem[1][7].CLK +clk => mem[1][8].CLK +clk => mem[1][9].CLK +clk => mem[1][10].CLK +clk => mem[1][11].CLK +clk => mem[1][12].CLK +clk => mem[1][13].CLK +clk => mem[1][14].CLK +clk => mem[1][15].CLK +clk => mem[1][16].CLK +clk => mem[1][17].CLK +clk => mem[1][18].CLK +clk => mem[1][19].CLK +clk => mem[1][20].CLK +clk => mem[1][21].CLK +clk => mem[1][22].CLK +clk => mem[1][23].CLK +clk => mem[1][24].CLK +clk => mem[1][25].CLK +clk => mem[1][26].CLK +clk => mem[1][27].CLK +clk => mem[1][28].CLK +clk => mem[1][29].CLK +clk => mem[1][30].CLK +clk => mem[1][31].CLK +clk => mem[1][32].CLK +clk => mem[1][33].CLK +clk => mem[1][34].CLK +clk => mem[1][35].CLK +clk => mem[1][36].CLK +clk => mem[1][37].CLK +clk => mem[1][38].CLK +clk => mem[1][39].CLK +clk => mem[1][40].CLK +clk => mem[1][41].CLK +clk => mem[1][42].CLK +clk => mem[1][43].CLK +clk => mem[1][44].CLK +clk => mem[1][45].CLK +clk => mem[1][46].CLK +clk => mem[1][47].CLK +clk => mem[1][48].CLK +clk => mem[1][49].CLK +clk => mem[1][50].CLK +clk => mem[1][51].CLK +clk => mem[1][52].CLK +clk => mem[1][53].CLK +clk => mem[1][54].CLK +clk => mem[1][55].CLK +clk => mem[1][56].CLK +clk => mem[1][57].CLK +clk => mem[1][58].CLK +clk => mem[1][59].CLK +clk => mem[1][60].CLK +clk => mem[1][61].CLK +clk => mem[1][62].CLK +clk => mem[1][63].CLK +clk => mem[1][64].CLK +clk => mem[1][65].CLK +clk => mem[1][66].CLK +clk => mem[1][67].CLK +clk => mem[1][68].CLK +clk => mem[1][69].CLK +clk => mem[1][70].CLK +clk => mem[1][71].CLK +clk => mem[1][72].CLK +clk => mem[1][73].CLK +clk => mem[1][74].CLK +clk => mem[1][75].CLK +clk => mem[1][76].CLK +clk => mem[1][77].CLK +clk => mem[1][78].CLK +clk => mem[1][79].CLK +clk => mem[1][80].CLK +clk => mem[1][81].CLK +clk => mem[1][82].CLK +clk => mem[1][83].CLK +clk => mem[1][84].CLK +clk => mem[1][85].CLK +clk => mem[1][86].CLK +clk => mem[1][87].CLK +clk => mem[1][88].CLK +clk => mem[1][89].CLK +clk => mem[1][90].CLK +clk => mem[1][91].CLK +clk => mem[1][92].CLK +clk => mem[1][93].CLK +clk => mem[1][94].CLK +clk => mem[1][95].CLK +clk => mem[1][96].CLK +clk => mem[1][97].CLK +clk => mem[1][98].CLK +clk => mem[1][99].CLK +clk => mem[1][100].CLK +clk => mem[1][101].CLK +clk => mem[1][102].CLK +clk => mem[1][103].CLK +clk => mem[0][0].CLK +clk => mem[0][1].CLK +clk => mem[0][2].CLK +clk => mem[0][3].CLK +clk => mem[0][4].CLK +clk => mem[0][5].CLK +clk => mem[0][6].CLK +clk => mem[0][7].CLK +clk => mem[0][8].CLK +clk => mem[0][9].CLK +clk => mem[0][10].CLK +clk => mem[0][11].CLK +clk => mem[0][12].CLK +clk => mem[0][13].CLK +clk => mem[0][14].CLK +clk => mem[0][15].CLK +clk => mem[0][16].CLK +clk => mem[0][17].CLK +clk => mem[0][18].CLK +clk => mem[0][19].CLK +clk => mem[0][20].CLK +clk => mem[0][21].CLK +clk => mem[0][22].CLK +clk => mem[0][23].CLK +clk => mem[0][24].CLK +clk => mem[0][25].CLK +clk => mem[0][26].CLK +clk => mem[0][27].CLK +clk => mem[0][28].CLK +clk => mem[0][29].CLK +clk => mem[0][30].CLK +clk => mem[0][31].CLK +clk => mem[0][32].CLK +clk => mem[0][33].CLK +clk => mem[0][34].CLK +clk => mem[0][35].CLK +clk => mem[0][36].CLK +clk => mem[0][37].CLK +clk => mem[0][38].CLK +clk => mem[0][39].CLK +clk => mem[0][40].CLK +clk => mem[0][41].CLK +clk => mem[0][42].CLK +clk => mem[0][43].CLK +clk => mem[0][44].CLK +clk => mem[0][45].CLK +clk => mem[0][46].CLK +clk => mem[0][47].CLK +clk => mem[0][48].CLK +clk => mem[0][49].CLK +clk => mem[0][50].CLK +clk => mem[0][51].CLK +clk => mem[0][52].CLK +clk => mem[0][53].CLK +clk => mem[0][54].CLK +clk => mem[0][55].CLK +clk => mem[0][56].CLK +clk => mem[0][57].CLK +clk => mem[0][58].CLK +clk => mem[0][59].CLK +clk => mem[0][60].CLK +clk => mem[0][61].CLK +clk => mem[0][62].CLK +clk => mem[0][63].CLK +clk => mem[0][64].CLK +clk => mem[0][65].CLK +clk => mem[0][66].CLK +clk => mem[0][67].CLK +clk => mem[0][68].CLK +clk => mem[0][69].CLK +clk => mem[0][70].CLK +clk => mem[0][71].CLK +clk => mem[0][72].CLK +clk => mem[0][73].CLK +clk => mem[0][74].CLK +clk => mem[0][75].CLK +clk => mem[0][76].CLK +clk => mem[0][77].CLK +clk => mem[0][78].CLK +clk => mem[0][79].CLK +clk => mem[0][80].CLK +clk => mem[0][81].CLK +clk => mem[0][82].CLK +clk => mem[0][83].CLK +clk => mem[0][84].CLK +clk => mem[0][85].CLK +clk => mem[0][86].CLK +clk => mem[0][87].CLK +clk => mem[0][88].CLK +clk => mem[0][89].CLK +clk => mem[0][90].CLK +clk => mem[0][91].CLK +clk => mem[0][92].CLK +clk => mem[0][93].CLK +clk => mem[0][94].CLK +clk => mem[0][95].CLK +clk => mem[0][96].CLK +clk => mem[0][97].CLK +clk => mem[0][98].CLK +clk => mem[0][99].CLK +clk => mem[0][100].CLK +clk => mem[0][101].CLK +clk => mem[0][102].CLK +clk => mem[0][103].CLK +reset => csr_readdata[0]~reg0.ACLR +reset => csr_readdata[1]~reg0.ACLR +reset => csr_readdata[2]~reg0.ACLR +reset => csr_readdata[3]~reg0.ACLR +reset => csr_readdata[4]~reg0.ACLR +reset => csr_readdata[5]~reg0.ACLR +reset => csr_readdata[6]~reg0.ACLR +reset => csr_readdata[7]~reg0.ACLR +reset => csr_readdata[8]~reg0.ACLR +reset => csr_readdata[9]~reg0.ACLR +reset => csr_readdata[10]~reg0.ACLR +reset => csr_readdata[11]~reg0.ACLR +reset => csr_readdata[12]~reg0.ACLR +reset => csr_readdata[13]~reg0.ACLR +reset => csr_readdata[14]~reg0.ACLR +reset => csr_readdata[15]~reg0.ACLR +reset => csr_readdata[16]~reg0.ACLR +reset => csr_readdata[17]~reg0.ACLR +reset => csr_readdata[18]~reg0.ACLR +reset => csr_readdata[19]~reg0.ACLR +reset => csr_readdata[20]~reg0.ACLR +reset => csr_readdata[21]~reg0.ACLR +reset => csr_readdata[22]~reg0.ACLR +reset => csr_readdata[23]~reg0.ACLR +reset => csr_readdata[24]~reg0.ACLR +reset => csr_readdata[25]~reg0.ACLR +reset => csr_readdata[26]~reg0.ACLR +reset => csr_readdata[27]~reg0.ACLR +reset => csr_readdata[28]~reg0.ACLR +reset => csr_readdata[29]~reg0.ACLR +reset => csr_readdata[30]~reg0.ACLR +reset => csr_readdata[31]~reg0.ACLR +reset => mem_used[1].ACLR +reset => mem_used[0].ACLR +reset => mem[1][0].ACLR +reset => mem[1][1].ACLR +reset => mem[1][2].ACLR +reset => mem[1][3].ACLR +reset => mem[1][4].ACLR +reset => mem[1][5].ACLR +reset => mem[1][6].ACLR +reset => mem[1][7].ACLR +reset => mem[1][8].ACLR +reset => mem[1][9].ACLR +reset => mem[1][10].ACLR +reset => mem[1][11].ACLR +reset => mem[1][12].ACLR +reset => mem[1][13].ACLR +reset => mem[1][14].ACLR +reset => mem[1][15].ACLR +reset => mem[1][16].ACLR +reset => mem[1][17].ACLR +reset => mem[1][18].ACLR +reset => mem[1][19].ACLR +reset => mem[1][20].ACLR +reset => mem[1][21].ACLR +reset => mem[1][22].ACLR +reset => mem[1][23].ACLR +reset => mem[1][24].ACLR +reset => mem[1][25].ACLR +reset => mem[1][26].ACLR +reset => mem[1][27].ACLR +reset => mem[1][28].ACLR +reset => mem[1][29].ACLR +reset => mem[1][30].ACLR +reset => mem[1][31].ACLR +reset => mem[1][32].ACLR +reset => mem[1][33].ACLR +reset => mem[1][34].ACLR +reset => mem[1][35].ACLR +reset => mem[1][36].ACLR +reset => mem[1][37].ACLR +reset => mem[1][38].ACLR +reset => mem[1][39].ACLR +reset => mem[1][40].ACLR +reset => mem[1][41].ACLR +reset => mem[1][42].ACLR +reset => mem[1][43].ACLR +reset => mem[1][44].ACLR +reset => mem[1][45].ACLR +reset => mem[1][46].ACLR +reset => mem[1][47].ACLR +reset => mem[1][48].ACLR +reset => mem[1][49].ACLR +reset => mem[1][50].ACLR +reset => mem[1][51].ACLR +reset => mem[1][52].ACLR +reset => mem[1][53].ACLR +reset => mem[1][54].ACLR +reset => mem[1][55].ACLR +reset => mem[1][56].ACLR +reset => mem[1][57].ACLR +reset => mem[1][58].ACLR +reset => mem[1][59].ACLR +reset => mem[1][60].ACLR +reset => mem[1][61].ACLR +reset => mem[1][62].ACLR +reset => mem[1][63].ACLR +reset => mem[1][64].ACLR +reset => mem[1][65].ACLR +reset => mem[1][66].ACLR +reset => mem[1][67].ACLR +reset => mem[1][68].ACLR +reset => mem[1][69].ACLR +reset => mem[1][70].ACLR +reset => mem[1][71].ACLR +reset => mem[1][72].ACLR +reset => mem[1][73].ACLR +reset => mem[1][74].ACLR +reset => mem[1][75].ACLR +reset => mem[1][76].ACLR +reset => mem[1][77].ACLR +reset => mem[1][78].ACLR +reset => mem[1][79].ACLR +reset => mem[1][80].ACLR +reset => mem[1][81].ACLR +reset => mem[1][82].ACLR +reset => mem[1][83].ACLR +reset => mem[1][84].ACLR +reset => mem[1][85].ACLR +reset => mem[1][86].ACLR +reset => mem[1][87].ACLR +reset => mem[1][88].ACLR +reset => mem[1][89].ACLR +reset => mem[1][90].ACLR +reset => mem[1][91].ACLR +reset => mem[1][92].ACLR +reset => mem[1][93].ACLR +reset => mem[1][94].ACLR +reset => mem[1][95].ACLR +reset => mem[1][96].ACLR +reset => mem[1][97].ACLR +reset => mem[1][98].ACLR +reset => mem[1][99].ACLR +reset => mem[1][100].ACLR +reset => mem[1][101].ACLR +reset => mem[1][102].ACLR +reset => mem[1][103].ACLR +reset => mem[0][0].ACLR +reset => mem[0][1].ACLR +reset => mem[0][2].ACLR +reset => mem[0][3].ACLR +reset => mem[0][4].ACLR +reset => mem[0][5].ACLR +reset => mem[0][6].ACLR +reset => mem[0][7].ACLR +reset => mem[0][8].ACLR +reset => mem[0][9].ACLR +reset => mem[0][10].ACLR +reset => mem[0][11].ACLR +reset => mem[0][12].ACLR +reset => mem[0][13].ACLR +reset => mem[0][14].ACLR +reset => mem[0][15].ACLR +reset => mem[0][16].ACLR +reset => mem[0][17].ACLR +reset => mem[0][18].ACLR +reset => mem[0][19].ACLR +reset => mem[0][20].ACLR +reset => mem[0][21].ACLR +reset => mem[0][22].ACLR +reset => mem[0][23].ACLR +reset => mem[0][24].ACLR +reset => mem[0][25].ACLR +reset => mem[0][26].ACLR +reset => mem[0][27].ACLR +reset => mem[0][28].ACLR +reset => mem[0][29].ACLR +reset => mem[0][30].ACLR +reset => mem[0][31].ACLR +reset => mem[0][32].ACLR +reset => mem[0][33].ACLR +reset => mem[0][34].ACLR +reset => mem[0][35].ACLR +reset => mem[0][36].ACLR +reset => mem[0][37].ACLR +reset => mem[0][38].ACLR +reset => mem[0][39].ACLR +reset => mem[0][40].ACLR +reset => mem[0][41].ACLR +reset => mem[0][42].ACLR +reset => mem[0][43].ACLR +reset => mem[0][44].ACLR +reset => mem[0][45].ACLR +reset => mem[0][46].ACLR +reset => mem[0][47].ACLR +reset => mem[0][48].ACLR +reset => mem[0][49].ACLR +reset => mem[0][50].ACLR +reset => mem[0][51].ACLR +reset => mem[0][52].ACLR +reset => mem[0][53].ACLR +reset => mem[0][54].ACLR +reset => mem[0][55].ACLR +reset => mem[0][56].ACLR +reset => mem[0][57].ACLR +reset => mem[0][58].ACLR +reset => mem[0][59].ACLR +reset => mem[0][60].ACLR +reset => mem[0][61].ACLR +reset => mem[0][62].ACLR +reset => mem[0][63].ACLR +reset => mem[0][64].ACLR +reset => mem[0][65].ACLR +reset => mem[0][66].ACLR +reset => mem[0][67].ACLR +reset => mem[0][68].ACLR +reset => mem[0][69].ACLR +reset => mem[0][70].ACLR +reset => mem[0][71].ACLR +reset => mem[0][72].ACLR +reset => mem[0][73].ACLR +reset => mem[0][74].ACLR +reset => mem[0][75].ACLR +reset => mem[0][76].ACLR +reset => mem[0][77].ACLR +reset => mem[0][78].ACLR +reset => mem[0][79].ACLR +reset => mem[0][80].ACLR +reset => mem[0][81].ACLR +reset => mem[0][82].ACLR +reset => mem[0][83].ACLR +reset => mem[0][84].ACLR +reset => mem[0][85].ACLR +reset => mem[0][86].ACLR +reset => mem[0][87].ACLR +reset => mem[0][88].ACLR +reset => mem[0][89].ACLR +reset => mem[0][90].ACLR +reset => mem[0][91].ACLR +reset => mem[0][92].ACLR +reset => mem[0][93].ACLR +reset => mem[0][94].ACLR +reset => mem[0][95].ACLR +reset => mem[0][96].ACLR +reset => mem[0][97].ACLR +reset => mem[0][98].ACLR +reset => mem[0][99].ACLR +reset => mem[0][100].ACLR +reset => mem[0][101].ACLR +reset => mem[0][102].ACLR +reset => mem[0][103].ACLR +in_data[0] => mem.DATAB +in_data[1] => mem.DATAB +in_data[2] => mem.DATAB +in_data[3] => mem.DATAB +in_data[4] => mem.DATAB +in_data[5] => mem.DATAB +in_data[6] => mem.DATAB +in_data[7] => mem.DATAB +in_data[8] => mem.DATAB +in_data[9] => mem.DATAB +in_data[10] => mem.DATAB +in_data[11] => mem.DATAB +in_data[12] => mem.DATAB +in_data[13] => mem.DATAB +in_data[14] => mem.DATAB +in_data[15] => mem.DATAB +in_data[16] => mem.DATAB +in_data[17] => mem.DATAB +in_data[18] => mem.DATAB +in_data[19] => mem.DATAB +in_data[20] => mem.DATAB +in_data[21] => mem.DATAB +in_data[22] => mem.DATAB +in_data[23] => mem.DATAB +in_data[24] => mem.DATAB +in_data[25] => mem.DATAB +in_data[26] => mem.DATAB +in_data[27] => mem.DATAB +in_data[28] => mem.DATAB +in_data[29] => mem.DATAB +in_data[30] => mem.DATAB +in_data[31] => mem.DATAB +in_data[32] => mem.DATAB +in_data[33] => mem.DATAB +in_data[34] => mem.DATAB +in_data[35] => mem.DATAB +in_data[36] => mem.DATAB +in_data[37] => mem.DATAB +in_data[38] => mem.DATAB +in_data[39] => mem.DATAB +in_data[40] => mem.DATAB +in_data[41] => mem.DATAB +in_data[42] => mem.DATAB +in_data[43] => mem.DATAB +in_data[44] => mem.DATAB +in_data[45] => mem.DATAB +in_data[46] => mem.DATAB +in_data[47] => mem.DATAB +in_data[48] => mem.DATAB +in_data[49] => mem.DATAB +in_data[50] => mem.DATAB +in_data[51] => mem.DATAB +in_data[52] => mem.DATAB +in_data[53] => mem.DATAB +in_data[54] => mem.DATAB +in_data[55] => mem.DATAB +in_data[56] => mem.DATAB +in_data[57] => mem.DATAB +in_data[58] => mem.DATAB +in_data[59] => mem.DATAB +in_data[60] => mem.DATAB +in_data[61] => mem.DATAB +in_data[62] => mem.DATAB +in_data[63] => mem.DATAB +in_data[64] => mem.DATAB +in_data[65] => mem.DATAB +in_data[66] => mem.DATAB +in_data[67] => mem.DATAB +in_data[68] => mem.DATAB +in_data[69] => mem.DATAB +in_data[70] => mem.DATAB +in_data[71] => mem.DATAB +in_data[72] => mem.DATAB +in_data[73] => mem.DATAB +in_data[74] => mem.DATAB +in_data[75] => mem.DATAB +in_data[76] => mem.DATAB +in_data[77] => mem.DATAB +in_data[78] => mem.DATAB +in_data[79] => mem.DATAB +in_data[80] => mem.DATAB +in_data[81] => mem.DATAB +in_data[82] => mem.DATAB +in_data[83] => mem.DATAB +in_data[84] => mem.DATAB +in_data[85] => mem.DATAB +in_data[86] => mem.DATAB +in_data[87] => mem.DATAB +in_data[88] => mem.DATAB +in_data[89] => mem.DATAB +in_data[90] => mem.DATAB +in_data[91] => mem.DATAB +in_data[92] => mem.DATAB +in_data[93] => mem.DATAB +in_data[94] => mem.DATAB +in_data[95] => mem.DATAB +in_data[96] => mem.DATAB +in_data[97] => mem.DATAB +in_data[98] => mem.DATAB +in_data[99] => mem.DATAB +in_data[100] => mem.DATAB +in_data[101] => mem.DATAB +in_valid => write.IN1 +in_startofpacket => mem.DATAB +in_endofpacket => mem.DATAB +in_empty[0] => ~NO_FANOUT~ +in_error[0] => out_error[0].DATAIN +in_error[0] => out_empty[0].DATAIN +in_channel[0] => out_channel[0].DATAIN +in_ready <= mem_used[1].DB_MAX_OUTPUT_PORT_TYPE +out_data[0] <= mem[0][0].DB_MAX_OUTPUT_PORT_TYPE +out_data[1] <= mem[0][1].DB_MAX_OUTPUT_PORT_TYPE +out_data[2] <= mem[0][2].DB_MAX_OUTPUT_PORT_TYPE +out_data[3] <= mem[0][3].DB_MAX_OUTPUT_PORT_TYPE +out_data[4] <= mem[0][4].DB_MAX_OUTPUT_PORT_TYPE +out_data[5] <= mem[0][5].DB_MAX_OUTPUT_PORT_TYPE +out_data[6] <= mem[0][6].DB_MAX_OUTPUT_PORT_TYPE +out_data[7] <= mem[0][7].DB_MAX_OUTPUT_PORT_TYPE +out_data[8] <= mem[0][8].DB_MAX_OUTPUT_PORT_TYPE +out_data[9] <= mem[0][9].DB_MAX_OUTPUT_PORT_TYPE +out_data[10] <= mem[0][10].DB_MAX_OUTPUT_PORT_TYPE +out_data[11] <= mem[0][11].DB_MAX_OUTPUT_PORT_TYPE +out_data[12] <= mem[0][12].DB_MAX_OUTPUT_PORT_TYPE +out_data[13] <= mem[0][13].DB_MAX_OUTPUT_PORT_TYPE +out_data[14] <= mem[0][14].DB_MAX_OUTPUT_PORT_TYPE +out_data[15] <= mem[0][15].DB_MAX_OUTPUT_PORT_TYPE +out_data[16] <= mem[0][16].DB_MAX_OUTPUT_PORT_TYPE +out_data[17] <= mem[0][17].DB_MAX_OUTPUT_PORT_TYPE +out_data[18] <= mem[0][18].DB_MAX_OUTPUT_PORT_TYPE +out_data[19] <= mem[0][19].DB_MAX_OUTPUT_PORT_TYPE +out_data[20] <= mem[0][20].DB_MAX_OUTPUT_PORT_TYPE +out_data[21] <= mem[0][21].DB_MAX_OUTPUT_PORT_TYPE +out_data[22] <= mem[0][22].DB_MAX_OUTPUT_PORT_TYPE +out_data[23] <= mem[0][23].DB_MAX_OUTPUT_PORT_TYPE +out_data[24] <= mem[0][24].DB_MAX_OUTPUT_PORT_TYPE +out_data[25] <= mem[0][25].DB_MAX_OUTPUT_PORT_TYPE +out_data[26] <= mem[0][26].DB_MAX_OUTPUT_PORT_TYPE +out_data[27] <= mem[0][27].DB_MAX_OUTPUT_PORT_TYPE +out_data[28] <= mem[0][28].DB_MAX_OUTPUT_PORT_TYPE +out_data[29] <= mem[0][29].DB_MAX_OUTPUT_PORT_TYPE +out_data[30] <= mem[0][30].DB_MAX_OUTPUT_PORT_TYPE +out_data[31] <= mem[0][31].DB_MAX_OUTPUT_PORT_TYPE +out_data[32] <= mem[0][32].DB_MAX_OUTPUT_PORT_TYPE +out_data[33] <= mem[0][33].DB_MAX_OUTPUT_PORT_TYPE +out_data[34] <= mem[0][34].DB_MAX_OUTPUT_PORT_TYPE +out_data[35] <= mem[0][35].DB_MAX_OUTPUT_PORT_TYPE +out_data[36] <= mem[0][36].DB_MAX_OUTPUT_PORT_TYPE +out_data[37] <= mem[0][37].DB_MAX_OUTPUT_PORT_TYPE +out_data[38] <= mem[0][38].DB_MAX_OUTPUT_PORT_TYPE +out_data[39] <= mem[0][39].DB_MAX_OUTPUT_PORT_TYPE +out_data[40] <= mem[0][40].DB_MAX_OUTPUT_PORT_TYPE +out_data[41] <= mem[0][41].DB_MAX_OUTPUT_PORT_TYPE +out_data[42] <= mem[0][42].DB_MAX_OUTPUT_PORT_TYPE +out_data[43] <= mem[0][43].DB_MAX_OUTPUT_PORT_TYPE +out_data[44] <= mem[0][44].DB_MAX_OUTPUT_PORT_TYPE +out_data[45] <= mem[0][45].DB_MAX_OUTPUT_PORT_TYPE +out_data[46] <= mem[0][46].DB_MAX_OUTPUT_PORT_TYPE +out_data[47] <= mem[0][47].DB_MAX_OUTPUT_PORT_TYPE +out_data[48] <= mem[0][48].DB_MAX_OUTPUT_PORT_TYPE +out_data[49] <= mem[0][49].DB_MAX_OUTPUT_PORT_TYPE +out_data[50] <= mem[0][50].DB_MAX_OUTPUT_PORT_TYPE +out_data[51] <= mem[0][51].DB_MAX_OUTPUT_PORT_TYPE +out_data[52] <= mem[0][52].DB_MAX_OUTPUT_PORT_TYPE +out_data[53] <= mem[0][53].DB_MAX_OUTPUT_PORT_TYPE +out_data[54] <= mem[0][54].DB_MAX_OUTPUT_PORT_TYPE +out_data[55] <= mem[0][55].DB_MAX_OUTPUT_PORT_TYPE +out_data[56] <= mem[0][56].DB_MAX_OUTPUT_PORT_TYPE +out_data[57] <= mem[0][57].DB_MAX_OUTPUT_PORT_TYPE +out_data[58] <= mem[0][58].DB_MAX_OUTPUT_PORT_TYPE +out_data[59] <= mem[0][59].DB_MAX_OUTPUT_PORT_TYPE +out_data[60] <= mem[0][60].DB_MAX_OUTPUT_PORT_TYPE +out_data[61] <= mem[0][61].DB_MAX_OUTPUT_PORT_TYPE +out_data[62] <= mem[0][62].DB_MAX_OUTPUT_PORT_TYPE +out_data[63] <= mem[0][63].DB_MAX_OUTPUT_PORT_TYPE +out_data[64] <= mem[0][64].DB_MAX_OUTPUT_PORT_TYPE +out_data[65] <= mem[0][65].DB_MAX_OUTPUT_PORT_TYPE +out_data[66] <= mem[0][66].DB_MAX_OUTPUT_PORT_TYPE +out_data[67] <= mem[0][67].DB_MAX_OUTPUT_PORT_TYPE +out_data[68] <= mem[0][68].DB_MAX_OUTPUT_PORT_TYPE +out_data[69] <= mem[0][69].DB_MAX_OUTPUT_PORT_TYPE +out_data[70] <= mem[0][70].DB_MAX_OUTPUT_PORT_TYPE +out_data[71] <= mem[0][71].DB_MAX_OUTPUT_PORT_TYPE +out_data[72] <= mem[0][72].DB_MAX_OUTPUT_PORT_TYPE +out_data[73] <= mem[0][73].DB_MAX_OUTPUT_PORT_TYPE +out_data[74] <= mem[0][74].DB_MAX_OUTPUT_PORT_TYPE +out_data[75] <= mem[0][75].DB_MAX_OUTPUT_PORT_TYPE +out_data[76] <= mem[0][76].DB_MAX_OUTPUT_PORT_TYPE +out_data[77] <= mem[0][77].DB_MAX_OUTPUT_PORT_TYPE +out_data[78] <= mem[0][78].DB_MAX_OUTPUT_PORT_TYPE +out_data[79] <= mem[0][79].DB_MAX_OUTPUT_PORT_TYPE +out_data[80] <= mem[0][80].DB_MAX_OUTPUT_PORT_TYPE +out_data[81] <= mem[0][81].DB_MAX_OUTPUT_PORT_TYPE +out_data[82] <= mem[0][82].DB_MAX_OUTPUT_PORT_TYPE +out_data[83] <= mem[0][83].DB_MAX_OUTPUT_PORT_TYPE +out_data[84] <= mem[0][84].DB_MAX_OUTPUT_PORT_TYPE +out_data[85] <= mem[0][85].DB_MAX_OUTPUT_PORT_TYPE +out_data[86] <= mem[0][86].DB_MAX_OUTPUT_PORT_TYPE +out_data[87] <= mem[0][87].DB_MAX_OUTPUT_PORT_TYPE +out_data[88] <= mem[0][88].DB_MAX_OUTPUT_PORT_TYPE +out_data[89] <= mem[0][89].DB_MAX_OUTPUT_PORT_TYPE +out_data[90] <= mem[0][90].DB_MAX_OUTPUT_PORT_TYPE +out_data[91] <= mem[0][91].DB_MAX_OUTPUT_PORT_TYPE +out_data[92] <= mem[0][92].DB_MAX_OUTPUT_PORT_TYPE +out_data[93] <= mem[0][93].DB_MAX_OUTPUT_PORT_TYPE +out_data[94] <= mem[0][94].DB_MAX_OUTPUT_PORT_TYPE +out_data[95] <= mem[0][95].DB_MAX_OUTPUT_PORT_TYPE +out_data[96] <= mem[0][96].DB_MAX_OUTPUT_PORT_TYPE +out_data[97] <= mem[0][97].DB_MAX_OUTPUT_PORT_TYPE +out_data[98] <= mem[0][98].DB_MAX_OUTPUT_PORT_TYPE +out_data[99] <= mem[0][99].DB_MAX_OUTPUT_PORT_TYPE +out_data[100] <= mem[0][100].DB_MAX_OUTPUT_PORT_TYPE +out_data[101] <= mem[0][101].DB_MAX_OUTPUT_PORT_TYPE +out_valid <= mem_used[0].DB_MAX_OUTPUT_PORT_TYPE +out_startofpacket <= mem[0][103].DB_MAX_OUTPUT_PORT_TYPE +out_endofpacket <= mem[0][102].DB_MAX_OUTPUT_PORT_TYPE +out_empty[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE +out_error[0] <= in_error[0].DB_MAX_OUTPUT_PORT_TYPE +out_channel[0] <= in_channel[0].DB_MAX_OUTPUT_PORT_TYPE +out_ready => internal_out_ready.IN1 +csr_address[0] => ~NO_FANOUT~ +csr_address[1] => ~NO_FANOUT~ +csr_write => ~NO_FANOUT~ +csr_read => csr_readdata[0]~reg0.ENA +csr_read => csr_readdata[31]~reg0.ENA +csr_read => csr_readdata[30]~reg0.ENA +csr_read => csr_readdata[29]~reg0.ENA +csr_read => csr_readdata[28]~reg0.ENA +csr_read => csr_readdata[27]~reg0.ENA +csr_read => csr_readdata[26]~reg0.ENA +csr_read => csr_readdata[25]~reg0.ENA +csr_read => csr_readdata[24]~reg0.ENA +csr_read => csr_readdata[23]~reg0.ENA +csr_read => csr_readdata[22]~reg0.ENA +csr_read => csr_readdata[21]~reg0.ENA +csr_read => csr_readdata[20]~reg0.ENA +csr_read => csr_readdata[19]~reg0.ENA +csr_read => csr_readdata[18]~reg0.ENA +csr_read => csr_readdata[17]~reg0.ENA +csr_read => csr_readdata[16]~reg0.ENA +csr_read => csr_readdata[15]~reg0.ENA +csr_read => csr_readdata[14]~reg0.ENA +csr_read => csr_readdata[13]~reg0.ENA +csr_read => csr_readdata[12]~reg0.ENA +csr_read => csr_readdata[11]~reg0.ENA +csr_read => csr_readdata[10]~reg0.ENA +csr_read => csr_readdata[9]~reg0.ENA +csr_read => csr_readdata[8]~reg0.ENA +csr_read => csr_readdata[7]~reg0.ENA +csr_read => csr_readdata[6]~reg0.ENA +csr_read => csr_readdata[5]~reg0.ENA +csr_read => csr_readdata[4]~reg0.ENA +csr_read => csr_readdata[3]~reg0.ENA +csr_read => csr_readdata[2]~reg0.ENA +csr_read => csr_readdata[1]~reg0.ENA +csr_writedata[0] => ~NO_FANOUT~ +csr_writedata[1] => ~NO_FANOUT~ +csr_writedata[2] => ~NO_FANOUT~ +csr_writedata[3] => ~NO_FANOUT~ +csr_writedata[4] => ~NO_FANOUT~ +csr_writedata[5] => ~NO_FANOUT~ +csr_writedata[6] => ~NO_FANOUT~ +csr_writedata[7] => ~NO_FANOUT~ +csr_writedata[8] => ~NO_FANOUT~ +csr_writedata[9] => ~NO_FANOUT~ +csr_writedata[10] => ~NO_FANOUT~ +csr_writedata[11] => ~NO_FANOUT~ +csr_writedata[12] => ~NO_FANOUT~ +csr_writedata[13] => ~NO_FANOUT~ +csr_writedata[14] => ~NO_FANOUT~ +csr_writedata[15] => ~NO_FANOUT~ +csr_writedata[16] => ~NO_FANOUT~ +csr_writedata[17] => ~NO_FANOUT~ +csr_writedata[18] => ~NO_FANOUT~ +csr_writedata[19] => ~NO_FANOUT~ +csr_writedata[20] => ~NO_FANOUT~ +csr_writedata[21] => ~NO_FANOUT~ +csr_writedata[22] => ~NO_FANOUT~ +csr_writedata[23] => ~NO_FANOUT~ +csr_writedata[24] => ~NO_FANOUT~ +csr_writedata[25] => ~NO_FANOUT~ +csr_writedata[26] => ~NO_FANOUT~ +csr_writedata[27] => ~NO_FANOUT~ +csr_writedata[28] => ~NO_FANOUT~ +csr_writedata[29] => ~NO_FANOUT~ +csr_writedata[30] => ~NO_FANOUT~ +csr_writedata[31] => ~NO_FANOUT~ +csr_readdata[0] <= csr_readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[1] <= csr_readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[2] <= csr_readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[3] <= csr_readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[4] <= csr_readdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[5] <= csr_readdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[6] <= csr_readdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[7] <= csr_readdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[8] <= csr_readdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[9] <= csr_readdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[10] <= csr_readdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[11] <= csr_readdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[12] <= csr_readdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[13] <= csr_readdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[14] <= csr_readdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[15] <= csr_readdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[16] <= csr_readdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[17] <= csr_readdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[18] <= csr_readdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[19] <= csr_readdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[20] <= csr_readdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[21] <= csr_readdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[22] <= csr_readdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[23] <= csr_readdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[24] <= csr_readdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[25] <= csr_readdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[26] <= csr_readdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[27] <= csr_readdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[28] <= csr_readdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[29] <= csr_readdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[30] <= csr_readdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE +csr_readdata[31] <= csr_readdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE +almost_full_data <= +almost_empty_data <= + + +|de0_nano_system|system:inst_cpu|system_addr_router:addr_router +clk => ~NO_FANOUT~ +reset => ~NO_FANOUT~ +sink_valid => src_valid.DATAIN +sink_data[0] => src_data[0].DATAIN +sink_data[1] => src_data[1].DATAIN +sink_data[2] => src_data[2].DATAIN +sink_data[3] => src_data[3].DATAIN +sink_data[4] => src_data[4].DATAIN +sink_data[5] => src_data[5].DATAIN +sink_data[6] => src_data[6].DATAIN +sink_data[7] => src_data[7].DATAIN +sink_data[8] => src_data[8].DATAIN +sink_data[9] => src_data[9].DATAIN +sink_data[10] => src_data[10].DATAIN +sink_data[11] => src_data[11].DATAIN +sink_data[12] => src_data[12].DATAIN +sink_data[13] => src_data[13].DATAIN +sink_data[14] => src_data[14].DATAIN +sink_data[15] => src_data[15].DATAIN +sink_data[16] => src_data[16].DATAIN +sink_data[17] => src_data[17].DATAIN +sink_data[18] => src_data[18].DATAIN +sink_data[19] => src_data[19].DATAIN +sink_data[20] => src_data[20].DATAIN +sink_data[21] => src_data[21].DATAIN +sink_data[22] => src_data[22].DATAIN +sink_data[23] => src_data[23].DATAIN +sink_data[24] => src_data[24].DATAIN +sink_data[25] => src_data[25].DATAIN +sink_data[26] => src_data[26].DATAIN +sink_data[27] => src_data[27].DATAIN +sink_data[28] => src_data[28].DATAIN +sink_data[29] => src_data[29].DATAIN +sink_data[30] => src_data[30].DATAIN +sink_data[31] => src_data[31].DATAIN +sink_data[32] => src_data[32].DATAIN +sink_data[33] => src_data[33].DATAIN +sink_data[34] => src_data[34].DATAIN +sink_data[35] => src_data[35].DATAIN +sink_data[36] => src_data[36].DATAIN +sink_data[37] => src_data[37].DATAIN +sink_data[38] => src_data[38].DATAIN +sink_data[39] => src_data[39].DATAIN +sink_data[40] => src_data[40].DATAIN +sink_data[41] => src_data[41].DATAIN +sink_data[42] => src_data[42].DATAIN +sink_data[43] => src_data[43].DATAIN +sink_data[44] => src_data[44].DATAIN +sink_data[45] => src_data[45].DATAIN +sink_data[46] => src_data[46].DATAIN +sink_data[47] => src_data[47].DATAIN +sink_data[47] => Equal1.IN1 +sink_data[48] => src_data[48].DATAIN +sink_data[48] => Equal1.IN14 +sink_data[49] => src_data[49].DATAIN +sink_data[49] => Equal1.IN13 +sink_data[50] => src_data[50].DATAIN +sink_data[50] => Equal1.IN12 +sink_data[51] => src_data[51].DATAIN +sink_data[51] => Equal1.IN11 +sink_data[52] => src_data[52].DATAIN +sink_data[52] => Equal1.IN10 +sink_data[53] => src_data[53].DATAIN +sink_data[53] => Equal1.IN9 +sink_data[54] => src_data[54].DATAIN +sink_data[54] => Equal1.IN8 +sink_data[55] => src_data[55].DATAIN +sink_data[55] => Equal1.IN7 +sink_data[56] => src_data[56].DATAIN +sink_data[56] => Equal1.IN6 +sink_data[57] => src_data[57].DATAIN +sink_data[57] => Equal1.IN5 +sink_data[58] => src_data[58].DATAIN +sink_data[58] => Equal1.IN4 +sink_data[59] => src_data[59].DATAIN +sink_data[59] => Equal1.IN3 +sink_data[60] => src_data[60].DATAIN +sink_data[60] => Equal0.IN0 +sink_data[60] => Equal1.IN2 +sink_data[61] => src_data[61].DATAIN +sink_data[61] => Equal0.IN1 +sink_data[61] => Equal1.IN0 +sink_data[62] => src_data[62].DATAIN +sink_data[63] => src_data[63].DATAIN +sink_data[64] => src_data[64].DATAIN +sink_data[65] => src_data[65].DATAIN +sink_data[66] => src_data[66].DATAIN +sink_data[67] => src_data[67].DATAIN +sink_data[68] => src_data[68].DATAIN +sink_data[69] => src_data[69].DATAIN +sink_data[70] => src_data[70].DATAIN +sink_data[71] => src_data[71].DATAIN +sink_data[72] => src_data[72].DATAIN +sink_data[73] => src_data[73].DATAIN +sink_data[74] => src_data[74].DATAIN +sink_data[75] => src_data[75].DATAIN +sink_data[76] => src_data[76].DATAIN +sink_data[77] => src_data[77].DATAIN +sink_data[78] => src_data[78].DATAIN +sink_data[79] => src_data[79].DATAIN +sink_data[80] => src_data[80].DATAIN +sink_data[81] => src_data[81].DATAIN +sink_data[82] => src_data[82].DATAIN +sink_data[83] => src_data[83].DATAIN +sink_data[84] => src_data[84].DATAIN +sink_data[85] => src_data[85].DATAIN +sink_data[86] => src_data[86].DATAIN +sink_data[87] => ~NO_FANOUT~ +sink_data[88] => ~NO_FANOUT~ +sink_data[89] => ~NO_FANOUT~ +sink_data[90] => ~NO_FANOUT~ +sink_data[91] => src_data[91].DATAIN +sink_data[92] => src_data[92].DATAIN +sink_data[93] => src_data[93].DATAIN +sink_data[94] => src_data[94].DATAIN +sink_data[95] => src_data[95].DATAIN +sink_data[96] => src_data[96].DATAIN +sink_data[97] => src_data[97].DATAIN +sink_data[98] => src_data[98].DATAIN +sink_data[99] => src_data[99].DATAIN +sink_data[100] => src_data[100].DATAIN +sink_startofpacket => src_startofpacket.DATAIN +sink_endofpacket => src_endofpacket.DATAIN +sink_ready <= src_ready.DB_MAX_OUTPUT_PORT_TYPE +src_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE +src_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src_data[87] <= src_data.DB_MAX_OUTPUT_PORT_TYPE +src_data[88] <= src_data.DB_MAX_OUTPUT_PORT_TYPE +src_data[89] <= src_data.DB_MAX_OUTPUT_PORT_TYPE +src_data[90] <= src_data.DB_MAX_OUTPUT_PORT_TYPE +src_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src_data[96] <= sink_data[96].DB_MAX_OUTPUT_PORT_TYPE +src_data[97] <= sink_data[97].DB_MAX_OUTPUT_PORT_TYPE +src_data[98] <= sink_data[98].DB_MAX_OUTPUT_PORT_TYPE +src_data[99] <= sink_data[99].DB_MAX_OUTPUT_PORT_TYPE +src_data[100] <= sink_data[100].DB_MAX_OUTPUT_PORT_TYPE +src_channel[0] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[1] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[2] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[3] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[4] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[5] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[6] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[7] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[8] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[9] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[10] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src_ready => sink_ready.DATAIN + + +|de0_nano_system|system:inst_cpu|system_addr_router:addr_router|system_addr_router_default_decode:the_default_decode +default_destination_id[0] <= +default_destination_id[1] <= +default_destination_id[2] <= +default_destination_id[3] <= +default_src_channel[0] <= +default_src_channel[1] <= +default_src_channel[2] <= +default_src_channel[3] <= +default_src_channel[4] <= +default_src_channel[5] <= +default_src_channel[6] <= +default_src_channel[7] <= +default_src_channel[8] <= +default_src_channel[9] <= +default_src_channel[10] <= + + +|de0_nano_system|system:inst_cpu|system_addr_router_001:addr_router_001 +clk => ~NO_FANOUT~ +reset => ~NO_FANOUT~ +sink_valid => src_valid.DATAIN +sink_data[0] => src_data[0].DATAIN +sink_data[1] => src_data[1].DATAIN +sink_data[2] => src_data[2].DATAIN +sink_data[3] => src_data[3].DATAIN +sink_data[4] => src_data[4].DATAIN +sink_data[5] => src_data[5].DATAIN +sink_data[6] => src_data[6].DATAIN +sink_data[7] => src_data[7].DATAIN +sink_data[8] => src_data[8].DATAIN +sink_data[9] => src_data[9].DATAIN +sink_data[10] => src_data[10].DATAIN +sink_data[11] => src_data[11].DATAIN +sink_data[12] => src_data[12].DATAIN +sink_data[13] => src_data[13].DATAIN +sink_data[14] => src_data[14].DATAIN +sink_data[15] => src_data[15].DATAIN +sink_data[16] => src_data[16].DATAIN +sink_data[17] => src_data[17].DATAIN +sink_data[18] => src_data[18].DATAIN +sink_data[19] => src_data[19].DATAIN +sink_data[20] => src_data[20].DATAIN +sink_data[21] => src_data[21].DATAIN +sink_data[22] => src_data[22].DATAIN +sink_data[23] => src_data[23].DATAIN +sink_data[24] => src_data[24].DATAIN +sink_data[25] => src_data[25].DATAIN +sink_data[26] => src_data[26].DATAIN +sink_data[27] => src_data[27].DATAIN +sink_data[28] => src_data[28].DATAIN +sink_data[29] => src_data[29].DATAIN +sink_data[30] => src_data[30].DATAIN +sink_data[31] => src_data[31].DATAIN +sink_data[32] => src_data[32].DATAIN +sink_data[33] => src_data[33].DATAIN +sink_data[34] => src_data[34].DATAIN +sink_data[35] => src_data[35].DATAIN +sink_data[36] => src_data[36].DATAIN +sink_data[37] => src_data[37].DATAIN +sink_data[38] => src_data[38].DATAIN +sink_data[39] => src_data[39].DATAIN +sink_data[39] => Equal8.IN22 +sink_data[39] => Equal9.IN4 +sink_data[39] => Equal10.IN22 +sink_data[40] => src_data[40].DATAIN +sink_data[40] => Equal5.IN21 +sink_data[40] => Equal6.IN4 +sink_data[40] => Equal7.IN21 +sink_data[40] => Equal8.IN3 +sink_data[40] => Equal9.IN3 +sink_data[40] => Equal10.IN21 +sink_data[41] => src_data[41].DATAIN +sink_data[41] => Equal2.IN20 +sink_data[41] => Equal3.IN2 +sink_data[41] => Equal4.IN20 +sink_data[41] => Equal5.IN3 +sink_data[41] => Equal6.IN3 +sink_data[41] => Equal7.IN20 +sink_data[41] => Equal8.IN21 +sink_data[41] => Equal9.IN22 +sink_data[41] => Equal10.IN3 +sink_data[42] => src_data[42].DATAIN +sink_data[42] => Equal2.IN19 +sink_data[42] => Equal3.IN20 +sink_data[42] => Equal4.IN2 +sink_data[42] => Equal5.IN2 +sink_data[42] => Equal6.IN2 +sink_data[42] => Equal7.IN19 +sink_data[42] => Equal8.IN20 +sink_data[42] => Equal9.IN21 +sink_data[42] => Equal10.IN20 +sink_data[43] => src_data[43].DATAIN +sink_data[43] => Equal2.IN18 +sink_data[43] => Equal3.IN19 +sink_data[43] => Equal4.IN19 +sink_data[43] => Equal5.IN20 +sink_data[43] => Equal6.IN21 +sink_data[43] => Equal7.IN2 +sink_data[43] => Equal8.IN2 +sink_data[43] => Equal9.IN2 +sink_data[43] => Equal10.IN2 +sink_data[44] => src_data[44].DATAIN +sink_data[44] => Equal2.IN17 +sink_data[44] => Equal3.IN18 +sink_data[44] => Equal4.IN18 +sink_data[44] => Equal5.IN19 +sink_data[44] => Equal6.IN20 +sink_data[44] => Equal7.IN18 +sink_data[44] => Equal8.IN19 +sink_data[44] => Equal9.IN20 +sink_data[44] => Equal10.IN19 +sink_data[45] => src_data[45].DATAIN +sink_data[45] => Equal2.IN16 +sink_data[45] => Equal3.IN17 +sink_data[45] => Equal4.IN17 +sink_data[45] => Equal5.IN18 +sink_data[45] => Equal6.IN19 +sink_data[45] => Equal7.IN17 +sink_data[45] => Equal8.IN18 +sink_data[45] => Equal9.IN19 +sink_data[45] => Equal10.IN18 +sink_data[46] => src_data[46].DATAIN +sink_data[46] => Equal2.IN15 +sink_data[46] => Equal3.IN16 +sink_data[46] => Equal4.IN16 +sink_data[46] => Equal5.IN17 +sink_data[46] => Equal6.IN18 +sink_data[46] => Equal7.IN16 +sink_data[46] => Equal8.IN17 +sink_data[46] => Equal9.IN18 +sink_data[46] => Equal10.IN17 +sink_data[47] => src_data[47].DATAIN +sink_data[47] => Equal1.IN1 +sink_data[47] => Equal2.IN14 +sink_data[47] => Equal3.IN15 +sink_data[47] => Equal4.IN15 +sink_data[47] => Equal5.IN16 +sink_data[47] => Equal6.IN17 +sink_data[47] => Equal7.IN15 +sink_data[47] => Equal8.IN16 +sink_data[47] => Equal9.IN17 +sink_data[47] => Equal10.IN16 +sink_data[48] => src_data[48].DATAIN +sink_data[48] => Equal1.IN14 +sink_data[48] => Equal2.IN1 +sink_data[48] => Equal3.IN1 +sink_data[48] => Equal4.IN1 +sink_data[48] => Equal5.IN1 +sink_data[48] => Equal6.IN1 +sink_data[48] => Equal7.IN1 +sink_data[48] => Equal8.IN1 +sink_data[48] => Equal9.IN1 +sink_data[48] => Equal10.IN1 +sink_data[49] => src_data[49].DATAIN +sink_data[49] => Equal1.IN13 +sink_data[49] => Equal2.IN13 +sink_data[49] => Equal3.IN14 +sink_data[49] => Equal4.IN14 +sink_data[49] => Equal5.IN15 +sink_data[49] => Equal6.IN16 +sink_data[49] => Equal7.IN14 +sink_data[49] => Equal8.IN15 +sink_data[49] => Equal9.IN16 +sink_data[49] => Equal10.IN15 +sink_data[50] => src_data[50].DATAIN +sink_data[50] => Equal1.IN12 +sink_data[50] => Equal2.IN12 +sink_data[50] => Equal3.IN13 +sink_data[50] => Equal4.IN13 +sink_data[50] => Equal5.IN14 +sink_data[50] => Equal6.IN15 +sink_data[50] => Equal7.IN13 +sink_data[50] => Equal8.IN14 +sink_data[50] => Equal9.IN15 +sink_data[50] => Equal10.IN14 +sink_data[51] => src_data[51].DATAIN +sink_data[51] => Equal1.IN11 +sink_data[51] => Equal2.IN11 +sink_data[51] => Equal3.IN12 +sink_data[51] => Equal4.IN12 +sink_data[51] => Equal5.IN13 +sink_data[51] => Equal6.IN14 +sink_data[51] => Equal7.IN12 +sink_data[51] => Equal8.IN13 +sink_data[51] => Equal9.IN14 +sink_data[51] => Equal10.IN13 +sink_data[52] => src_data[52].DATAIN +sink_data[52] => Equal1.IN10 +sink_data[52] => Equal2.IN10 +sink_data[52] => Equal3.IN11 +sink_data[52] => Equal4.IN11 +sink_data[52] => Equal5.IN12 +sink_data[52] => Equal6.IN13 +sink_data[52] => Equal7.IN11 +sink_data[52] => Equal8.IN12 +sink_data[52] => Equal9.IN13 +sink_data[52] => Equal10.IN12 +sink_data[53] => src_data[53].DATAIN +sink_data[53] => Equal1.IN9 +sink_data[53] => Equal2.IN9 +sink_data[53] => Equal3.IN10 +sink_data[53] => Equal4.IN10 +sink_data[53] => Equal5.IN11 +sink_data[53] => Equal6.IN12 +sink_data[53] => Equal7.IN10 +sink_data[53] => Equal8.IN11 +sink_data[53] => Equal9.IN12 +sink_data[53] => Equal10.IN11 +sink_data[54] => src_data[54].DATAIN +sink_data[54] => Equal1.IN8 +sink_data[54] => Equal2.IN8 +sink_data[54] => Equal3.IN9 +sink_data[54] => Equal4.IN9 +sink_data[54] => Equal5.IN10 +sink_data[54] => Equal6.IN11 +sink_data[54] => Equal7.IN9 +sink_data[54] => Equal8.IN10 +sink_data[54] => Equal9.IN11 +sink_data[54] => Equal10.IN10 +sink_data[55] => src_data[55].DATAIN +sink_data[55] => Equal1.IN7 +sink_data[55] => Equal2.IN7 +sink_data[55] => Equal3.IN8 +sink_data[55] => Equal4.IN8 +sink_data[55] => Equal5.IN9 +sink_data[55] => Equal6.IN10 +sink_data[55] => Equal7.IN8 +sink_data[55] => Equal8.IN9 +sink_data[55] => Equal9.IN10 +sink_data[55] => Equal10.IN9 +sink_data[56] => src_data[56].DATAIN +sink_data[56] => Equal1.IN6 +sink_data[56] => Equal2.IN6 +sink_data[56] => Equal3.IN7 +sink_data[56] => Equal4.IN7 +sink_data[56] => Equal5.IN8 +sink_data[56] => Equal6.IN9 +sink_data[56] => Equal7.IN7 +sink_data[56] => Equal8.IN8 +sink_data[56] => Equal9.IN9 +sink_data[56] => Equal10.IN8 +sink_data[57] => src_data[57].DATAIN +sink_data[57] => Equal1.IN5 +sink_data[57] => Equal2.IN5 +sink_data[57] => Equal3.IN6 +sink_data[57] => Equal4.IN6 +sink_data[57] => Equal5.IN7 +sink_data[57] => Equal6.IN8 +sink_data[57] => Equal7.IN6 +sink_data[57] => Equal8.IN7 +sink_data[57] => Equal9.IN8 +sink_data[57] => Equal10.IN7 +sink_data[58] => src_data[58].DATAIN +sink_data[58] => Equal1.IN4 +sink_data[58] => Equal2.IN4 +sink_data[58] => Equal3.IN5 +sink_data[58] => Equal4.IN5 +sink_data[58] => Equal5.IN6 +sink_data[58] => Equal6.IN7 +sink_data[58] => Equal7.IN5 +sink_data[58] => Equal8.IN6 +sink_data[58] => Equal9.IN7 +sink_data[58] => Equal10.IN6 +sink_data[59] => src_data[59].DATAIN +sink_data[59] => Equal1.IN3 +sink_data[59] => Equal2.IN3 +sink_data[59] => Equal3.IN4 +sink_data[59] => Equal4.IN4 +sink_data[59] => Equal5.IN5 +sink_data[59] => Equal6.IN6 +sink_data[59] => Equal7.IN4 +sink_data[59] => Equal8.IN5 +sink_data[59] => Equal9.IN6 +sink_data[59] => Equal10.IN5 +sink_data[60] => src_data[60].DATAIN +sink_data[60] => Equal0.IN0 +sink_data[60] => Equal1.IN2 +sink_data[60] => Equal2.IN2 +sink_data[60] => Equal3.IN3 +sink_data[60] => Equal4.IN3 +sink_data[60] => Equal5.IN4 +sink_data[60] => Equal6.IN5 +sink_data[60] => Equal7.IN3 +sink_data[60] => Equal8.IN4 +sink_data[60] => Equal9.IN5 +sink_data[60] => Equal10.IN4 +sink_data[61] => src_data[61].DATAIN +sink_data[61] => Equal0.IN1 +sink_data[61] => Equal1.IN0 +sink_data[61] => Equal2.IN0 +sink_data[61] => Equal3.IN0 +sink_data[61] => Equal4.IN0 +sink_data[61] => Equal5.IN0 +sink_data[61] => Equal6.IN0 +sink_data[61] => Equal7.IN0 +sink_data[61] => Equal8.IN0 +sink_data[61] => Equal9.IN0 +sink_data[61] => Equal10.IN0 +sink_data[62] => src_data[62].DATAIN +sink_data[63] => src_data[63].DATAIN +sink_data[64] => src_data[64].DATAIN +sink_data[65] => src_data[65].DATAIN +sink_data[66] => src_data[66].DATAIN +sink_data[67] => src_data[67].DATAIN +sink_data[68] => src_data[68].DATAIN +sink_data[69] => src_data[69].DATAIN +sink_data[70] => src_data[70].DATAIN +sink_data[71] => src_data[71].DATAIN +sink_data[72] => src_data[72].DATAIN +sink_data[73] => src_data[73].DATAIN +sink_data[74] => src_data[74].DATAIN +sink_data[75] => src_data[75].DATAIN +sink_data[76] => src_data[76].DATAIN +sink_data[77] => src_data[77].DATAIN +sink_data[78] => src_data[78].DATAIN +sink_data[79] => src_data[79].DATAIN +sink_data[80] => src_data[80].DATAIN +sink_data[81] => src_data[81].DATAIN +sink_data[82] => src_data[82].DATAIN +sink_data[83] => src_data[83].DATAIN +sink_data[84] => src_data[84].DATAIN +sink_data[85] => src_data[85].DATAIN +sink_data[86] => src_data[86].DATAIN +sink_data[87] => ~NO_FANOUT~ +sink_data[88] => ~NO_FANOUT~ +sink_data[89] => ~NO_FANOUT~ +sink_data[90] => ~NO_FANOUT~ +sink_data[91] => src_data[91].DATAIN +sink_data[92] => src_data[92].DATAIN +sink_data[93] => src_data[93].DATAIN +sink_data[94] => src_data[94].DATAIN +sink_data[95] => src_data[95].DATAIN +sink_data[96] => src_data[96].DATAIN +sink_data[97] => src_data[97].DATAIN +sink_data[98] => src_data[98].DATAIN +sink_data[99] => src_data[99].DATAIN +sink_data[100] => src_data[100].DATAIN +sink_startofpacket => src_startofpacket.DATAIN +sink_endofpacket => src_endofpacket.DATAIN +sink_ready <= src_ready.DB_MAX_OUTPUT_PORT_TYPE +src_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE +src_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src_data[87] <= src_data.DB_MAX_OUTPUT_PORT_TYPE +src_data[88] <= src_data.DB_MAX_OUTPUT_PORT_TYPE +src_data[89] <= src_data.DB_MAX_OUTPUT_PORT_TYPE +src_data[90] <= src_data.DB_MAX_OUTPUT_PORT_TYPE +src_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src_data[96] <= sink_data[96].DB_MAX_OUTPUT_PORT_TYPE +src_data[97] <= sink_data[97].DB_MAX_OUTPUT_PORT_TYPE +src_data[98] <= sink_data[98].DB_MAX_OUTPUT_PORT_TYPE +src_data[99] <= sink_data[99].DB_MAX_OUTPUT_PORT_TYPE +src_data[100] <= sink_data[100].DB_MAX_OUTPUT_PORT_TYPE +src_channel[0] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[1] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[2] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[3] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[4] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[5] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[6] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[7] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[8] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[9] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[10] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src_ready => sink_ready.DATAIN + + +|de0_nano_system|system:inst_cpu|system_addr_router_001:addr_router_001|system_addr_router_001_default_decode:the_default_decode +default_destination_id[0] <= +default_destination_id[1] <= +default_destination_id[2] <= +default_destination_id[3] <= +default_src_channel[0] <= +default_src_channel[1] <= +default_src_channel[2] <= +default_src_channel[3] <= +default_src_channel[4] <= +default_src_channel[5] <= +default_src_channel[6] <= +default_src_channel[7] <= +default_src_channel[8] <= +default_src_channel[9] <= +default_src_channel[10] <= + + +|de0_nano_system|system:inst_cpu|system_id_router:id_router +clk => ~NO_FANOUT~ +reset => ~NO_FANOUT~ +sink_valid => src_valid.DATAIN +sink_data[0] => src_data[0].DATAIN +sink_data[1] => src_data[1].DATAIN +sink_data[2] => src_data[2].DATAIN +sink_data[3] => src_data[3].DATAIN +sink_data[4] => src_data[4].DATAIN +sink_data[5] => src_data[5].DATAIN +sink_data[6] => src_data[6].DATAIN +sink_data[7] => src_data[7].DATAIN +sink_data[8] => src_data[8].DATAIN +sink_data[9] => src_data[9].DATAIN +sink_data[10] => src_data[10].DATAIN +sink_data[11] => src_data[11].DATAIN +sink_data[12] => src_data[12].DATAIN +sink_data[13] => src_data[13].DATAIN +sink_data[14] => src_data[14].DATAIN +sink_data[15] => src_data[15].DATAIN +sink_data[16] => src_data[16].DATAIN +sink_data[17] => src_data[17].DATAIN +sink_data[18] => src_data[18].DATAIN +sink_data[19] => src_data[19].DATAIN +sink_data[20] => src_data[20].DATAIN +sink_data[21] => src_data[21].DATAIN +sink_data[22] => src_data[22].DATAIN +sink_data[23] => src_data[23].DATAIN +sink_data[24] => src_data[24].DATAIN +sink_data[25] => src_data[25].DATAIN +sink_data[26] => src_data[26].DATAIN +sink_data[27] => src_data[27].DATAIN +sink_data[28] => src_data[28].DATAIN +sink_data[29] => src_data[29].DATAIN +sink_data[30] => src_data[30].DATAIN +sink_data[31] => src_data[31].DATAIN +sink_data[32] => src_data[32].DATAIN +sink_data[33] => src_data[33].DATAIN +sink_data[34] => src_data[34].DATAIN +sink_data[35] => src_data[35].DATAIN +sink_data[36] => src_data[36].DATAIN +sink_data[37] => src_data[37].DATAIN +sink_data[38] => src_data[38].DATAIN +sink_data[39] => src_data[39].DATAIN +sink_data[40] => src_data[40].DATAIN +sink_data[41] => src_data[41].DATAIN +sink_data[42] => src_data[42].DATAIN +sink_data[43] => src_data[43].DATAIN +sink_data[44] => src_data[44].DATAIN +sink_data[45] => src_data[45].DATAIN +sink_data[46] => src_data[46].DATAIN +sink_data[47] => src_data[47].DATAIN +sink_data[48] => src_data[48].DATAIN +sink_data[49] => src_data[49].DATAIN +sink_data[50] => src_data[50].DATAIN +sink_data[51] => src_data[51].DATAIN +sink_data[52] => src_data[52].DATAIN +sink_data[53] => src_data[53].DATAIN +sink_data[54] => src_data[54].DATAIN +sink_data[55] => src_data[55].DATAIN +sink_data[56] => src_data[56].DATAIN +sink_data[57] => src_data[57].DATAIN +sink_data[58] => src_data[58].DATAIN +sink_data[59] => src_data[59].DATAIN +sink_data[60] => src_data[60].DATAIN +sink_data[61] => src_data[61].DATAIN +sink_data[62] => src_data[62].DATAIN +sink_data[63] => src_data[63].DATAIN +sink_data[64] => src_data[64].DATAIN +sink_data[65] => src_data[65].DATAIN +sink_data[66] => src_data[66].DATAIN +sink_data[67] => src_data[67].DATAIN +sink_data[68] => src_data[68].DATAIN +sink_data[69] => src_data[69].DATAIN +sink_data[70] => src_data[70].DATAIN +sink_data[71] => src_data[71].DATAIN +sink_data[72] => src_data[72].DATAIN +sink_data[73] => src_data[73].DATAIN +sink_data[74] => src_data[74].DATAIN +sink_data[75] => src_data[75].DATAIN +sink_data[76] => src_data[76].DATAIN +sink_data[77] => src_data[77].DATAIN +sink_data[78] => src_data[78].DATAIN +sink_data[79] => src_data[79].DATAIN +sink_data[80] => src_data[80].DATAIN +sink_data[81] => src_data[81].DATAIN +sink_data[82] => src_data[82].DATAIN +sink_data[83] => src_data[83].DATAIN +sink_data[84] => src_data[84].DATAIN +sink_data[85] => src_data[85].DATAIN +sink_data[86] => src_data[86].DATAIN +sink_data[87] => src_data[87].DATAIN +sink_data[87] => Equal0.IN31 +sink_data[87] => Equal1.IN0 +sink_data[88] => src_data[88].DATAIN +sink_data[88] => Equal0.IN30 +sink_data[88] => Equal1.IN31 +sink_data[89] => src_data[89].DATAIN +sink_data[89] => Equal0.IN29 +sink_data[89] => Equal1.IN30 +sink_data[90] => src_data[90].DATAIN +sink_data[90] => Equal0.IN28 +sink_data[90] => Equal1.IN29 +sink_data[91] => src_data[91].DATAIN +sink_data[92] => src_data[92].DATAIN +sink_data[93] => src_data[93].DATAIN +sink_data[94] => src_data[94].DATAIN +sink_data[95] => src_data[95].DATAIN +sink_data[96] => src_data[96].DATAIN +sink_data[97] => src_data[97].DATAIN +sink_data[98] => src_data[98].DATAIN +sink_data[99] => src_data[99].DATAIN +sink_data[100] => src_data[100].DATAIN +sink_startofpacket => src_startofpacket.DATAIN +sink_endofpacket => src_endofpacket.DATAIN +sink_ready <= src_ready.DB_MAX_OUTPUT_PORT_TYPE +src_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE +src_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src_data[96] <= sink_data[96].DB_MAX_OUTPUT_PORT_TYPE +src_data[97] <= sink_data[97].DB_MAX_OUTPUT_PORT_TYPE +src_data[98] <= sink_data[98].DB_MAX_OUTPUT_PORT_TYPE +src_data[99] <= sink_data[99].DB_MAX_OUTPUT_PORT_TYPE +src_data[100] <= sink_data[100].DB_MAX_OUTPUT_PORT_TYPE +src_channel[0] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[1] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[2] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[3] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[4] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[5] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[6] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[7] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[8] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[9] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[10] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src_ready => sink_ready.DATAIN + + +|de0_nano_system|system:inst_cpu|system_id_router:id_router|system_id_router_default_decode:the_default_decode +default_destination_id[0] <= +default_destination_id[1] <= +default_destination_id[2] <= +default_destination_id[3] <= +default_src_channel[0] <= +default_src_channel[1] <= +default_src_channel[2] <= +default_src_channel[3] <= +default_src_channel[4] <= +default_src_channel[5] <= +default_src_channel[6] <= +default_src_channel[7] <= +default_src_channel[8] <= +default_src_channel[9] <= +default_src_channel[10] <= + + +|de0_nano_system|system:inst_cpu|system_id_router_001:id_router_001 +clk => ~NO_FANOUT~ +reset => ~NO_FANOUT~ +sink_valid => src_valid.DATAIN +sink_data[0] => src_data[0].DATAIN +sink_data[1] => src_data[1].DATAIN +sink_data[2] => src_data[2].DATAIN +sink_data[3] => src_data[3].DATAIN +sink_data[4] => src_data[4].DATAIN +sink_data[5] => src_data[5].DATAIN +sink_data[6] => src_data[6].DATAIN +sink_data[7] => src_data[7].DATAIN +sink_data[8] => src_data[8].DATAIN +sink_data[9] => src_data[9].DATAIN +sink_data[10] => src_data[10].DATAIN +sink_data[11] => src_data[11].DATAIN +sink_data[12] => src_data[12].DATAIN +sink_data[13] => src_data[13].DATAIN +sink_data[14] => src_data[14].DATAIN +sink_data[15] => src_data[15].DATAIN +sink_data[16] => src_data[16].DATAIN +sink_data[17] => src_data[17].DATAIN +sink_data[18] => src_data[18].DATAIN +sink_data[19] => src_data[19].DATAIN +sink_data[20] => src_data[20].DATAIN +sink_data[21] => src_data[21].DATAIN +sink_data[22] => src_data[22].DATAIN +sink_data[23] => src_data[23].DATAIN +sink_data[24] => src_data[24].DATAIN +sink_data[25] => src_data[25].DATAIN +sink_data[26] => src_data[26].DATAIN +sink_data[27] => src_data[27].DATAIN +sink_data[28] => src_data[28].DATAIN +sink_data[29] => src_data[29].DATAIN +sink_data[30] => src_data[30].DATAIN +sink_data[31] => src_data[31].DATAIN +sink_data[32] => src_data[32].DATAIN +sink_data[33] => src_data[33].DATAIN +sink_data[34] => src_data[34].DATAIN +sink_data[35] => src_data[35].DATAIN +sink_data[36] => src_data[36].DATAIN +sink_data[37] => src_data[37].DATAIN +sink_data[38] => src_data[38].DATAIN +sink_data[39] => src_data[39].DATAIN +sink_data[40] => src_data[40].DATAIN +sink_data[41] => src_data[41].DATAIN +sink_data[42] => src_data[42].DATAIN +sink_data[43] => src_data[43].DATAIN +sink_data[44] => src_data[44].DATAIN +sink_data[45] => src_data[45].DATAIN +sink_data[46] => src_data[46].DATAIN +sink_data[47] => src_data[47].DATAIN +sink_data[48] => src_data[48].DATAIN +sink_data[49] => src_data[49].DATAIN +sink_data[50] => src_data[50].DATAIN +sink_data[51] => src_data[51].DATAIN +sink_data[52] => src_data[52].DATAIN +sink_data[53] => src_data[53].DATAIN +sink_data[54] => src_data[54].DATAIN +sink_data[55] => src_data[55].DATAIN +sink_data[56] => src_data[56].DATAIN +sink_data[57] => src_data[57].DATAIN +sink_data[58] => src_data[58].DATAIN +sink_data[59] => src_data[59].DATAIN +sink_data[60] => src_data[60].DATAIN +sink_data[61] => src_data[61].DATAIN +sink_data[62] => src_data[62].DATAIN +sink_data[63] => src_data[63].DATAIN +sink_data[64] => src_data[64].DATAIN +sink_data[65] => src_data[65].DATAIN +sink_data[66] => src_data[66].DATAIN +sink_data[67] => src_data[67].DATAIN +sink_data[68] => src_data[68].DATAIN +sink_data[69] => src_data[69].DATAIN +sink_data[69] => Equal0.IN31 +sink_data[69] => Equal1.IN0 +sink_data[70] => src_data[70].DATAIN +sink_data[70] => Equal0.IN30 +sink_data[70] => Equal1.IN31 +sink_data[71] => src_data[71].DATAIN +sink_data[71] => Equal0.IN29 +sink_data[71] => Equal1.IN30 +sink_data[72] => src_data[72].DATAIN +sink_data[72] => Equal0.IN28 +sink_data[72] => Equal1.IN29 +sink_data[73] => src_data[73].DATAIN +sink_data[74] => src_data[74].DATAIN +sink_data[75] => src_data[75].DATAIN +sink_data[76] => src_data[76].DATAIN +sink_data[77] => src_data[77].DATAIN +sink_data[78] => src_data[78].DATAIN +sink_data[79] => src_data[79].DATAIN +sink_data[80] => src_data[80].DATAIN +sink_data[81] => src_data[81].DATAIN +sink_data[82] => src_data[82].DATAIN +sink_startofpacket => src_startofpacket.DATAIN +sink_endofpacket => src_endofpacket.DATAIN +sink_ready <= src_ready.DB_MAX_OUTPUT_PORT_TYPE +src_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE +src_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src_channel[0] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[1] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[2] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[3] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[4] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[5] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[6] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[7] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[8] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[9] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[10] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src_ready => sink_ready.DATAIN + + +|de0_nano_system|system:inst_cpu|system_id_router_001:id_router_001|system_id_router_001_default_decode:the_default_decode +default_destination_id[0] <= +default_destination_id[1] <= +default_destination_id[2] <= +default_destination_id[3] <= +default_src_channel[0] <= +default_src_channel[1] <= +default_src_channel[2] <= +default_src_channel[3] <= +default_src_channel[4] <= +default_src_channel[5] <= +default_src_channel[6] <= +default_src_channel[7] <= +default_src_channel[8] <= +default_src_channel[9] <= +default_src_channel[10] <= + + +|de0_nano_system|system:inst_cpu|system_id_router_002:id_router_002 +clk => ~NO_FANOUT~ +reset => ~NO_FANOUT~ +sink_valid => src_valid.DATAIN +sink_data[0] => src_data[0].DATAIN +sink_data[1] => src_data[1].DATAIN +sink_data[2] => src_data[2].DATAIN +sink_data[3] => src_data[3].DATAIN +sink_data[4] => src_data[4].DATAIN +sink_data[5] => src_data[5].DATAIN +sink_data[6] => src_data[6].DATAIN +sink_data[7] => src_data[7].DATAIN +sink_data[8] => src_data[8].DATAIN +sink_data[9] => src_data[9].DATAIN +sink_data[10] => src_data[10].DATAIN +sink_data[11] => src_data[11].DATAIN +sink_data[12] => src_data[12].DATAIN +sink_data[13] => src_data[13].DATAIN +sink_data[14] => src_data[14].DATAIN +sink_data[15] => src_data[15].DATAIN +sink_data[16] => src_data[16].DATAIN +sink_data[17] => src_data[17].DATAIN +sink_data[18] => src_data[18].DATAIN +sink_data[19] => src_data[19].DATAIN +sink_data[20] => src_data[20].DATAIN +sink_data[21] => src_data[21].DATAIN +sink_data[22] => src_data[22].DATAIN +sink_data[23] => src_data[23].DATAIN +sink_data[24] => src_data[24].DATAIN +sink_data[25] => src_data[25].DATAIN +sink_data[26] => src_data[26].DATAIN +sink_data[27] => src_data[27].DATAIN +sink_data[28] => src_data[28].DATAIN +sink_data[29] => src_data[29].DATAIN +sink_data[30] => src_data[30].DATAIN +sink_data[31] => src_data[31].DATAIN +sink_data[32] => src_data[32].DATAIN +sink_data[33] => src_data[33].DATAIN +sink_data[34] => src_data[34].DATAIN +sink_data[35] => src_data[35].DATAIN +sink_data[36] => src_data[36].DATAIN +sink_data[37] => src_data[37].DATAIN +sink_data[38] => src_data[38].DATAIN +sink_data[39] => src_data[39].DATAIN +sink_data[40] => src_data[40].DATAIN +sink_data[41] => src_data[41].DATAIN +sink_data[42] => src_data[42].DATAIN +sink_data[43] => src_data[43].DATAIN +sink_data[44] => src_data[44].DATAIN +sink_data[45] => src_data[45].DATAIN +sink_data[46] => src_data[46].DATAIN +sink_data[47] => src_data[47].DATAIN +sink_data[48] => src_data[48].DATAIN +sink_data[49] => src_data[49].DATAIN +sink_data[50] => src_data[50].DATAIN +sink_data[51] => src_data[51].DATAIN +sink_data[52] => src_data[52].DATAIN +sink_data[53] => src_data[53].DATAIN +sink_data[54] => src_data[54].DATAIN +sink_data[55] => src_data[55].DATAIN +sink_data[56] => src_data[56].DATAIN +sink_data[57] => src_data[57].DATAIN +sink_data[58] => src_data[58].DATAIN +sink_data[59] => src_data[59].DATAIN +sink_data[60] => src_data[60].DATAIN +sink_data[61] => src_data[61].DATAIN +sink_data[62] => src_data[62].DATAIN +sink_data[63] => src_data[63].DATAIN +sink_data[64] => src_data[64].DATAIN +sink_data[65] => src_data[65].DATAIN +sink_data[66] => src_data[66].DATAIN +sink_data[67] => src_data[67].DATAIN +sink_data[68] => src_data[68].DATAIN +sink_data[69] => src_data[69].DATAIN +sink_data[70] => src_data[70].DATAIN +sink_data[71] => src_data[71].DATAIN +sink_data[72] => src_data[72].DATAIN +sink_data[73] => src_data[73].DATAIN +sink_data[74] => src_data[74].DATAIN +sink_data[75] => src_data[75].DATAIN +sink_data[76] => src_data[76].DATAIN +sink_data[77] => src_data[77].DATAIN +sink_data[78] => src_data[78].DATAIN +sink_data[79] => src_data[79].DATAIN +sink_data[80] => src_data[80].DATAIN +sink_data[81] => src_data[81].DATAIN +sink_data[82] => src_data[82].DATAIN +sink_data[83] => src_data[83].DATAIN +sink_data[84] => src_data[84].DATAIN +sink_data[85] => src_data[85].DATAIN +sink_data[86] => src_data[86].DATAIN +sink_data[87] => src_data[87].DATAIN +sink_data[87] => Equal0.IN0 +sink_data[88] => src_data[88].DATAIN +sink_data[88] => Equal0.IN31 +sink_data[89] => src_data[89].DATAIN +sink_data[89] => Equal0.IN30 +sink_data[90] => src_data[90].DATAIN +sink_data[90] => Equal0.IN29 +sink_data[91] => src_data[91].DATAIN +sink_data[92] => src_data[92].DATAIN +sink_data[93] => src_data[93].DATAIN +sink_data[94] => src_data[94].DATAIN +sink_data[95] => src_data[95].DATAIN +sink_data[96] => src_data[96].DATAIN +sink_data[97] => src_data[97].DATAIN +sink_data[98] => src_data[98].DATAIN +sink_data[99] => src_data[99].DATAIN +sink_data[100] => src_data[100].DATAIN +sink_startofpacket => src_startofpacket.DATAIN +sink_endofpacket => src_endofpacket.DATAIN +sink_ready <= src_ready.DB_MAX_OUTPUT_PORT_TYPE +src_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE +src_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src_data[96] <= sink_data[96].DB_MAX_OUTPUT_PORT_TYPE +src_data[97] <= sink_data[97].DB_MAX_OUTPUT_PORT_TYPE +src_data[98] <= sink_data[98].DB_MAX_OUTPUT_PORT_TYPE +src_data[99] <= sink_data[99].DB_MAX_OUTPUT_PORT_TYPE +src_data[100] <= sink_data[100].DB_MAX_OUTPUT_PORT_TYPE +src_channel[0] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[1] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[2] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[3] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[4] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[5] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[6] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[7] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[8] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[9] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[10] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src_ready => sink_ready.DATAIN + + +|de0_nano_system|system:inst_cpu|system_id_router_002:id_router_002|system_id_router_002_default_decode:the_default_decode +default_destination_id[0] <= +default_destination_id[1] <= +default_destination_id[2] <= +default_destination_id[3] <= +default_src_channel[0] <= +default_src_channel[1] <= +default_src_channel[2] <= +default_src_channel[3] <= +default_src_channel[4] <= +default_src_channel[5] <= +default_src_channel[6] <= +default_src_channel[7] <= +default_src_channel[8] <= +default_src_channel[9] <= +default_src_channel[10] <= + + +|de0_nano_system|system:inst_cpu|system_id_router_002:id_router_003 +clk => ~NO_FANOUT~ +reset => ~NO_FANOUT~ +sink_valid => src_valid.DATAIN +sink_data[0] => src_data[0].DATAIN +sink_data[1] => src_data[1].DATAIN +sink_data[2] => src_data[2].DATAIN +sink_data[3] => src_data[3].DATAIN +sink_data[4] => src_data[4].DATAIN +sink_data[5] => src_data[5].DATAIN +sink_data[6] => src_data[6].DATAIN +sink_data[7] => src_data[7].DATAIN +sink_data[8] => src_data[8].DATAIN +sink_data[9] => src_data[9].DATAIN +sink_data[10] => src_data[10].DATAIN +sink_data[11] => src_data[11].DATAIN +sink_data[12] => src_data[12].DATAIN +sink_data[13] => src_data[13].DATAIN +sink_data[14] => src_data[14].DATAIN +sink_data[15] => src_data[15].DATAIN +sink_data[16] => src_data[16].DATAIN +sink_data[17] => src_data[17].DATAIN +sink_data[18] => src_data[18].DATAIN +sink_data[19] => src_data[19].DATAIN +sink_data[20] => src_data[20].DATAIN +sink_data[21] => src_data[21].DATAIN +sink_data[22] => src_data[22].DATAIN +sink_data[23] => src_data[23].DATAIN +sink_data[24] => src_data[24].DATAIN +sink_data[25] => src_data[25].DATAIN +sink_data[26] => src_data[26].DATAIN +sink_data[27] => src_data[27].DATAIN +sink_data[28] => src_data[28].DATAIN +sink_data[29] => src_data[29].DATAIN +sink_data[30] => src_data[30].DATAIN +sink_data[31] => src_data[31].DATAIN +sink_data[32] => src_data[32].DATAIN +sink_data[33] => src_data[33].DATAIN +sink_data[34] => src_data[34].DATAIN +sink_data[35] => src_data[35].DATAIN +sink_data[36] => src_data[36].DATAIN +sink_data[37] => src_data[37].DATAIN +sink_data[38] => src_data[38].DATAIN +sink_data[39] => src_data[39].DATAIN +sink_data[40] => src_data[40].DATAIN +sink_data[41] => src_data[41].DATAIN +sink_data[42] => src_data[42].DATAIN +sink_data[43] => src_data[43].DATAIN +sink_data[44] => src_data[44].DATAIN +sink_data[45] => src_data[45].DATAIN +sink_data[46] => src_data[46].DATAIN +sink_data[47] => src_data[47].DATAIN +sink_data[48] => src_data[48].DATAIN +sink_data[49] => src_data[49].DATAIN +sink_data[50] => src_data[50].DATAIN +sink_data[51] => src_data[51].DATAIN +sink_data[52] => src_data[52].DATAIN +sink_data[53] => src_data[53].DATAIN +sink_data[54] => src_data[54].DATAIN +sink_data[55] => src_data[55].DATAIN +sink_data[56] => src_data[56].DATAIN +sink_data[57] => src_data[57].DATAIN +sink_data[58] => src_data[58].DATAIN +sink_data[59] => src_data[59].DATAIN +sink_data[60] => src_data[60].DATAIN +sink_data[61] => src_data[61].DATAIN +sink_data[62] => src_data[62].DATAIN +sink_data[63] => src_data[63].DATAIN +sink_data[64] => src_data[64].DATAIN +sink_data[65] => src_data[65].DATAIN +sink_data[66] => src_data[66].DATAIN +sink_data[67] => src_data[67].DATAIN +sink_data[68] => src_data[68].DATAIN +sink_data[69] => src_data[69].DATAIN +sink_data[70] => src_data[70].DATAIN +sink_data[71] => src_data[71].DATAIN +sink_data[72] => src_data[72].DATAIN +sink_data[73] => src_data[73].DATAIN +sink_data[74] => src_data[74].DATAIN +sink_data[75] => src_data[75].DATAIN +sink_data[76] => src_data[76].DATAIN +sink_data[77] => src_data[77].DATAIN +sink_data[78] => src_data[78].DATAIN +sink_data[79] => src_data[79].DATAIN +sink_data[80] => src_data[80].DATAIN +sink_data[81] => src_data[81].DATAIN +sink_data[82] => src_data[82].DATAIN +sink_data[83] => src_data[83].DATAIN +sink_data[84] => src_data[84].DATAIN +sink_data[85] => src_data[85].DATAIN +sink_data[86] => src_data[86].DATAIN +sink_data[87] => src_data[87].DATAIN +sink_data[87] => Equal0.IN0 +sink_data[88] => src_data[88].DATAIN +sink_data[88] => Equal0.IN31 +sink_data[89] => src_data[89].DATAIN +sink_data[89] => Equal0.IN30 +sink_data[90] => src_data[90].DATAIN +sink_data[90] => Equal0.IN29 +sink_data[91] => src_data[91].DATAIN +sink_data[92] => src_data[92].DATAIN +sink_data[93] => src_data[93].DATAIN +sink_data[94] => src_data[94].DATAIN +sink_data[95] => src_data[95].DATAIN +sink_data[96] => src_data[96].DATAIN +sink_data[97] => src_data[97].DATAIN +sink_data[98] => src_data[98].DATAIN +sink_data[99] => src_data[99].DATAIN +sink_data[100] => src_data[100].DATAIN +sink_startofpacket => src_startofpacket.DATAIN +sink_endofpacket => src_endofpacket.DATAIN +sink_ready <= src_ready.DB_MAX_OUTPUT_PORT_TYPE +src_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE +src_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src_data[96] <= sink_data[96].DB_MAX_OUTPUT_PORT_TYPE +src_data[97] <= sink_data[97].DB_MAX_OUTPUT_PORT_TYPE +src_data[98] <= sink_data[98].DB_MAX_OUTPUT_PORT_TYPE +src_data[99] <= sink_data[99].DB_MAX_OUTPUT_PORT_TYPE +src_data[100] <= sink_data[100].DB_MAX_OUTPUT_PORT_TYPE +src_channel[0] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[1] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[2] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[3] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[4] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[5] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[6] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[7] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[8] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[9] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[10] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src_ready => sink_ready.DATAIN + + +|de0_nano_system|system:inst_cpu|system_id_router_002:id_router_003|system_id_router_002_default_decode:the_default_decode +default_destination_id[0] <= +default_destination_id[1] <= +default_destination_id[2] <= +default_destination_id[3] <= +default_src_channel[0] <= +default_src_channel[1] <= +default_src_channel[2] <= +default_src_channel[3] <= +default_src_channel[4] <= +default_src_channel[5] <= +default_src_channel[6] <= +default_src_channel[7] <= +default_src_channel[8] <= +default_src_channel[9] <= +default_src_channel[10] <= + + +|de0_nano_system|system:inst_cpu|system_id_router_002:id_router_004 +clk => ~NO_FANOUT~ +reset => ~NO_FANOUT~ +sink_valid => src_valid.DATAIN +sink_data[0] => src_data[0].DATAIN +sink_data[1] => src_data[1].DATAIN +sink_data[2] => src_data[2].DATAIN +sink_data[3] => src_data[3].DATAIN +sink_data[4] => src_data[4].DATAIN +sink_data[5] => src_data[5].DATAIN +sink_data[6] => src_data[6].DATAIN +sink_data[7] => src_data[7].DATAIN +sink_data[8] => src_data[8].DATAIN +sink_data[9] => src_data[9].DATAIN +sink_data[10] => src_data[10].DATAIN +sink_data[11] => src_data[11].DATAIN +sink_data[12] => src_data[12].DATAIN +sink_data[13] => src_data[13].DATAIN +sink_data[14] => src_data[14].DATAIN +sink_data[15] => src_data[15].DATAIN +sink_data[16] => src_data[16].DATAIN +sink_data[17] => src_data[17].DATAIN +sink_data[18] => src_data[18].DATAIN +sink_data[19] => src_data[19].DATAIN +sink_data[20] => src_data[20].DATAIN +sink_data[21] => src_data[21].DATAIN +sink_data[22] => src_data[22].DATAIN +sink_data[23] => src_data[23].DATAIN +sink_data[24] => src_data[24].DATAIN +sink_data[25] => src_data[25].DATAIN +sink_data[26] => src_data[26].DATAIN +sink_data[27] => src_data[27].DATAIN +sink_data[28] => src_data[28].DATAIN +sink_data[29] => src_data[29].DATAIN +sink_data[30] => src_data[30].DATAIN +sink_data[31] => src_data[31].DATAIN +sink_data[32] => src_data[32].DATAIN +sink_data[33] => src_data[33].DATAIN +sink_data[34] => src_data[34].DATAIN +sink_data[35] => src_data[35].DATAIN +sink_data[36] => src_data[36].DATAIN +sink_data[37] => src_data[37].DATAIN +sink_data[38] => src_data[38].DATAIN +sink_data[39] => src_data[39].DATAIN +sink_data[40] => src_data[40].DATAIN +sink_data[41] => src_data[41].DATAIN +sink_data[42] => src_data[42].DATAIN +sink_data[43] => src_data[43].DATAIN +sink_data[44] => src_data[44].DATAIN +sink_data[45] => src_data[45].DATAIN +sink_data[46] => src_data[46].DATAIN +sink_data[47] => src_data[47].DATAIN +sink_data[48] => src_data[48].DATAIN +sink_data[49] => src_data[49].DATAIN +sink_data[50] => src_data[50].DATAIN +sink_data[51] => src_data[51].DATAIN +sink_data[52] => src_data[52].DATAIN +sink_data[53] => src_data[53].DATAIN +sink_data[54] => src_data[54].DATAIN +sink_data[55] => src_data[55].DATAIN +sink_data[56] => src_data[56].DATAIN +sink_data[57] => src_data[57].DATAIN +sink_data[58] => src_data[58].DATAIN +sink_data[59] => src_data[59].DATAIN +sink_data[60] => src_data[60].DATAIN +sink_data[61] => src_data[61].DATAIN +sink_data[62] => src_data[62].DATAIN +sink_data[63] => src_data[63].DATAIN +sink_data[64] => src_data[64].DATAIN +sink_data[65] => src_data[65].DATAIN +sink_data[66] => src_data[66].DATAIN +sink_data[67] => src_data[67].DATAIN +sink_data[68] => src_data[68].DATAIN +sink_data[69] => src_data[69].DATAIN +sink_data[70] => src_data[70].DATAIN +sink_data[71] => src_data[71].DATAIN +sink_data[72] => src_data[72].DATAIN +sink_data[73] => src_data[73].DATAIN +sink_data[74] => src_data[74].DATAIN +sink_data[75] => src_data[75].DATAIN +sink_data[76] => src_data[76].DATAIN +sink_data[77] => src_data[77].DATAIN +sink_data[78] => src_data[78].DATAIN +sink_data[79] => src_data[79].DATAIN +sink_data[80] => src_data[80].DATAIN +sink_data[81] => src_data[81].DATAIN +sink_data[82] => src_data[82].DATAIN +sink_data[83] => src_data[83].DATAIN +sink_data[84] => src_data[84].DATAIN +sink_data[85] => src_data[85].DATAIN +sink_data[86] => src_data[86].DATAIN +sink_data[87] => src_data[87].DATAIN +sink_data[87] => Equal0.IN0 +sink_data[88] => src_data[88].DATAIN +sink_data[88] => Equal0.IN31 +sink_data[89] => src_data[89].DATAIN +sink_data[89] => Equal0.IN30 +sink_data[90] => src_data[90].DATAIN +sink_data[90] => Equal0.IN29 +sink_data[91] => src_data[91].DATAIN +sink_data[92] => src_data[92].DATAIN +sink_data[93] => src_data[93].DATAIN +sink_data[94] => src_data[94].DATAIN +sink_data[95] => src_data[95].DATAIN +sink_data[96] => src_data[96].DATAIN +sink_data[97] => src_data[97].DATAIN +sink_data[98] => src_data[98].DATAIN +sink_data[99] => src_data[99].DATAIN +sink_data[100] => src_data[100].DATAIN +sink_startofpacket => src_startofpacket.DATAIN +sink_endofpacket => src_endofpacket.DATAIN +sink_ready <= src_ready.DB_MAX_OUTPUT_PORT_TYPE +src_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE +src_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src_data[96] <= sink_data[96].DB_MAX_OUTPUT_PORT_TYPE +src_data[97] <= sink_data[97].DB_MAX_OUTPUT_PORT_TYPE +src_data[98] <= sink_data[98].DB_MAX_OUTPUT_PORT_TYPE +src_data[99] <= sink_data[99].DB_MAX_OUTPUT_PORT_TYPE +src_data[100] <= sink_data[100].DB_MAX_OUTPUT_PORT_TYPE +src_channel[0] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[1] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[2] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[3] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[4] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[5] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[6] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[7] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[8] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[9] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[10] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src_ready => sink_ready.DATAIN + + +|de0_nano_system|system:inst_cpu|system_id_router_002:id_router_004|system_id_router_002_default_decode:the_default_decode +default_destination_id[0] <= +default_destination_id[1] <= +default_destination_id[2] <= +default_destination_id[3] <= +default_src_channel[0] <= +default_src_channel[1] <= +default_src_channel[2] <= +default_src_channel[3] <= +default_src_channel[4] <= +default_src_channel[5] <= +default_src_channel[6] <= +default_src_channel[7] <= +default_src_channel[8] <= +default_src_channel[9] <= +default_src_channel[10] <= + + +|de0_nano_system|system:inst_cpu|system_id_router_002:id_router_005 +clk => ~NO_FANOUT~ +reset => ~NO_FANOUT~ +sink_valid => src_valid.DATAIN +sink_data[0] => src_data[0].DATAIN +sink_data[1] => src_data[1].DATAIN +sink_data[2] => src_data[2].DATAIN +sink_data[3] => src_data[3].DATAIN +sink_data[4] => src_data[4].DATAIN +sink_data[5] => src_data[5].DATAIN +sink_data[6] => src_data[6].DATAIN +sink_data[7] => src_data[7].DATAIN +sink_data[8] => src_data[8].DATAIN +sink_data[9] => src_data[9].DATAIN +sink_data[10] => src_data[10].DATAIN +sink_data[11] => src_data[11].DATAIN +sink_data[12] => src_data[12].DATAIN +sink_data[13] => src_data[13].DATAIN +sink_data[14] => src_data[14].DATAIN +sink_data[15] => src_data[15].DATAIN +sink_data[16] => src_data[16].DATAIN +sink_data[17] => src_data[17].DATAIN +sink_data[18] => src_data[18].DATAIN +sink_data[19] => src_data[19].DATAIN +sink_data[20] => src_data[20].DATAIN +sink_data[21] => src_data[21].DATAIN +sink_data[22] => src_data[22].DATAIN +sink_data[23] => src_data[23].DATAIN +sink_data[24] => src_data[24].DATAIN +sink_data[25] => src_data[25].DATAIN +sink_data[26] => src_data[26].DATAIN +sink_data[27] => src_data[27].DATAIN +sink_data[28] => src_data[28].DATAIN +sink_data[29] => src_data[29].DATAIN +sink_data[30] => src_data[30].DATAIN +sink_data[31] => src_data[31].DATAIN +sink_data[32] => src_data[32].DATAIN +sink_data[33] => src_data[33].DATAIN +sink_data[34] => src_data[34].DATAIN +sink_data[35] => src_data[35].DATAIN +sink_data[36] => src_data[36].DATAIN +sink_data[37] => src_data[37].DATAIN +sink_data[38] => src_data[38].DATAIN +sink_data[39] => src_data[39].DATAIN +sink_data[40] => src_data[40].DATAIN +sink_data[41] => src_data[41].DATAIN +sink_data[42] => src_data[42].DATAIN +sink_data[43] => src_data[43].DATAIN +sink_data[44] => src_data[44].DATAIN +sink_data[45] => src_data[45].DATAIN +sink_data[46] => src_data[46].DATAIN +sink_data[47] => src_data[47].DATAIN +sink_data[48] => src_data[48].DATAIN +sink_data[49] => src_data[49].DATAIN +sink_data[50] => src_data[50].DATAIN +sink_data[51] => src_data[51].DATAIN +sink_data[52] => src_data[52].DATAIN +sink_data[53] => src_data[53].DATAIN +sink_data[54] => src_data[54].DATAIN +sink_data[55] => src_data[55].DATAIN +sink_data[56] => src_data[56].DATAIN +sink_data[57] => src_data[57].DATAIN +sink_data[58] => src_data[58].DATAIN +sink_data[59] => src_data[59].DATAIN +sink_data[60] => src_data[60].DATAIN +sink_data[61] => src_data[61].DATAIN +sink_data[62] => src_data[62].DATAIN +sink_data[63] => src_data[63].DATAIN +sink_data[64] => src_data[64].DATAIN +sink_data[65] => src_data[65].DATAIN +sink_data[66] => src_data[66].DATAIN +sink_data[67] => src_data[67].DATAIN +sink_data[68] => src_data[68].DATAIN +sink_data[69] => src_data[69].DATAIN +sink_data[70] => src_data[70].DATAIN +sink_data[71] => src_data[71].DATAIN +sink_data[72] => src_data[72].DATAIN +sink_data[73] => src_data[73].DATAIN +sink_data[74] => src_data[74].DATAIN +sink_data[75] => src_data[75].DATAIN +sink_data[76] => src_data[76].DATAIN +sink_data[77] => src_data[77].DATAIN +sink_data[78] => src_data[78].DATAIN +sink_data[79] => src_data[79].DATAIN +sink_data[80] => src_data[80].DATAIN +sink_data[81] => src_data[81].DATAIN +sink_data[82] => src_data[82].DATAIN +sink_data[83] => src_data[83].DATAIN +sink_data[84] => src_data[84].DATAIN +sink_data[85] => src_data[85].DATAIN +sink_data[86] => src_data[86].DATAIN +sink_data[87] => src_data[87].DATAIN +sink_data[87] => Equal0.IN0 +sink_data[88] => src_data[88].DATAIN +sink_data[88] => Equal0.IN31 +sink_data[89] => src_data[89].DATAIN +sink_data[89] => Equal0.IN30 +sink_data[90] => src_data[90].DATAIN +sink_data[90] => Equal0.IN29 +sink_data[91] => src_data[91].DATAIN +sink_data[92] => src_data[92].DATAIN +sink_data[93] => src_data[93].DATAIN +sink_data[94] => src_data[94].DATAIN +sink_data[95] => src_data[95].DATAIN +sink_data[96] => src_data[96].DATAIN +sink_data[97] => src_data[97].DATAIN +sink_data[98] => src_data[98].DATAIN +sink_data[99] => src_data[99].DATAIN +sink_data[100] => src_data[100].DATAIN +sink_startofpacket => src_startofpacket.DATAIN +sink_endofpacket => src_endofpacket.DATAIN +sink_ready <= src_ready.DB_MAX_OUTPUT_PORT_TYPE +src_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE +src_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src_data[96] <= sink_data[96].DB_MAX_OUTPUT_PORT_TYPE +src_data[97] <= sink_data[97].DB_MAX_OUTPUT_PORT_TYPE +src_data[98] <= sink_data[98].DB_MAX_OUTPUT_PORT_TYPE +src_data[99] <= sink_data[99].DB_MAX_OUTPUT_PORT_TYPE +src_data[100] <= sink_data[100].DB_MAX_OUTPUT_PORT_TYPE +src_channel[0] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[1] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[2] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[3] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[4] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[5] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[6] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[7] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[8] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[9] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[10] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src_ready => sink_ready.DATAIN + + +|de0_nano_system|system:inst_cpu|system_id_router_002:id_router_005|system_id_router_002_default_decode:the_default_decode +default_destination_id[0] <= +default_destination_id[1] <= +default_destination_id[2] <= +default_destination_id[3] <= +default_src_channel[0] <= +default_src_channel[1] <= +default_src_channel[2] <= +default_src_channel[3] <= +default_src_channel[4] <= +default_src_channel[5] <= +default_src_channel[6] <= +default_src_channel[7] <= +default_src_channel[8] <= +default_src_channel[9] <= +default_src_channel[10] <= + + +|de0_nano_system|system:inst_cpu|system_id_router_002:id_router_006 +clk => ~NO_FANOUT~ +reset => ~NO_FANOUT~ +sink_valid => src_valid.DATAIN +sink_data[0] => src_data[0].DATAIN +sink_data[1] => src_data[1].DATAIN +sink_data[2] => src_data[2].DATAIN +sink_data[3] => src_data[3].DATAIN +sink_data[4] => src_data[4].DATAIN +sink_data[5] => src_data[5].DATAIN +sink_data[6] => src_data[6].DATAIN +sink_data[7] => src_data[7].DATAIN +sink_data[8] => src_data[8].DATAIN +sink_data[9] => src_data[9].DATAIN +sink_data[10] => src_data[10].DATAIN +sink_data[11] => src_data[11].DATAIN +sink_data[12] => src_data[12].DATAIN +sink_data[13] => src_data[13].DATAIN +sink_data[14] => src_data[14].DATAIN +sink_data[15] => src_data[15].DATAIN +sink_data[16] => src_data[16].DATAIN +sink_data[17] => src_data[17].DATAIN +sink_data[18] => src_data[18].DATAIN +sink_data[19] => src_data[19].DATAIN +sink_data[20] => src_data[20].DATAIN +sink_data[21] => src_data[21].DATAIN +sink_data[22] => src_data[22].DATAIN +sink_data[23] => src_data[23].DATAIN +sink_data[24] => src_data[24].DATAIN +sink_data[25] => src_data[25].DATAIN +sink_data[26] => src_data[26].DATAIN +sink_data[27] => src_data[27].DATAIN +sink_data[28] => src_data[28].DATAIN +sink_data[29] => src_data[29].DATAIN +sink_data[30] => src_data[30].DATAIN +sink_data[31] => src_data[31].DATAIN +sink_data[32] => src_data[32].DATAIN +sink_data[33] => src_data[33].DATAIN +sink_data[34] => src_data[34].DATAIN +sink_data[35] => src_data[35].DATAIN +sink_data[36] => src_data[36].DATAIN +sink_data[37] => src_data[37].DATAIN +sink_data[38] => src_data[38].DATAIN +sink_data[39] => src_data[39].DATAIN +sink_data[40] => src_data[40].DATAIN +sink_data[41] => src_data[41].DATAIN +sink_data[42] => src_data[42].DATAIN +sink_data[43] => src_data[43].DATAIN +sink_data[44] => src_data[44].DATAIN +sink_data[45] => src_data[45].DATAIN +sink_data[46] => src_data[46].DATAIN +sink_data[47] => src_data[47].DATAIN +sink_data[48] => src_data[48].DATAIN +sink_data[49] => src_data[49].DATAIN +sink_data[50] => src_data[50].DATAIN +sink_data[51] => src_data[51].DATAIN +sink_data[52] => src_data[52].DATAIN +sink_data[53] => src_data[53].DATAIN +sink_data[54] => src_data[54].DATAIN +sink_data[55] => src_data[55].DATAIN +sink_data[56] => src_data[56].DATAIN +sink_data[57] => src_data[57].DATAIN +sink_data[58] => src_data[58].DATAIN +sink_data[59] => src_data[59].DATAIN +sink_data[60] => src_data[60].DATAIN +sink_data[61] => src_data[61].DATAIN +sink_data[62] => src_data[62].DATAIN +sink_data[63] => src_data[63].DATAIN +sink_data[64] => src_data[64].DATAIN +sink_data[65] => src_data[65].DATAIN +sink_data[66] => src_data[66].DATAIN +sink_data[67] => src_data[67].DATAIN +sink_data[68] => src_data[68].DATAIN +sink_data[69] => src_data[69].DATAIN +sink_data[70] => src_data[70].DATAIN +sink_data[71] => src_data[71].DATAIN +sink_data[72] => src_data[72].DATAIN +sink_data[73] => src_data[73].DATAIN +sink_data[74] => src_data[74].DATAIN +sink_data[75] => src_data[75].DATAIN +sink_data[76] => src_data[76].DATAIN +sink_data[77] => src_data[77].DATAIN +sink_data[78] => src_data[78].DATAIN +sink_data[79] => src_data[79].DATAIN +sink_data[80] => src_data[80].DATAIN +sink_data[81] => src_data[81].DATAIN +sink_data[82] => src_data[82].DATAIN +sink_data[83] => src_data[83].DATAIN +sink_data[84] => src_data[84].DATAIN +sink_data[85] => src_data[85].DATAIN +sink_data[86] => src_data[86].DATAIN +sink_data[87] => src_data[87].DATAIN +sink_data[87] => Equal0.IN0 +sink_data[88] => src_data[88].DATAIN +sink_data[88] => Equal0.IN31 +sink_data[89] => src_data[89].DATAIN +sink_data[89] => Equal0.IN30 +sink_data[90] => src_data[90].DATAIN +sink_data[90] => Equal0.IN29 +sink_data[91] => src_data[91].DATAIN +sink_data[92] => src_data[92].DATAIN +sink_data[93] => src_data[93].DATAIN +sink_data[94] => src_data[94].DATAIN +sink_data[95] => src_data[95].DATAIN +sink_data[96] => src_data[96].DATAIN +sink_data[97] => src_data[97].DATAIN +sink_data[98] => src_data[98].DATAIN +sink_data[99] => src_data[99].DATAIN +sink_data[100] => src_data[100].DATAIN +sink_startofpacket => src_startofpacket.DATAIN +sink_endofpacket => src_endofpacket.DATAIN +sink_ready <= src_ready.DB_MAX_OUTPUT_PORT_TYPE +src_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE +src_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src_data[96] <= sink_data[96].DB_MAX_OUTPUT_PORT_TYPE +src_data[97] <= sink_data[97].DB_MAX_OUTPUT_PORT_TYPE +src_data[98] <= sink_data[98].DB_MAX_OUTPUT_PORT_TYPE +src_data[99] <= sink_data[99].DB_MAX_OUTPUT_PORT_TYPE +src_data[100] <= sink_data[100].DB_MAX_OUTPUT_PORT_TYPE +src_channel[0] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[1] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[2] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[3] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[4] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[5] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[6] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[7] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[8] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[9] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[10] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src_ready => sink_ready.DATAIN + + +|de0_nano_system|system:inst_cpu|system_id_router_002:id_router_006|system_id_router_002_default_decode:the_default_decode +default_destination_id[0] <= +default_destination_id[1] <= +default_destination_id[2] <= +default_destination_id[3] <= +default_src_channel[0] <= +default_src_channel[1] <= +default_src_channel[2] <= +default_src_channel[3] <= +default_src_channel[4] <= +default_src_channel[5] <= +default_src_channel[6] <= +default_src_channel[7] <= +default_src_channel[8] <= +default_src_channel[9] <= +default_src_channel[10] <= + + +|de0_nano_system|system:inst_cpu|system_id_router_002:id_router_007 +clk => ~NO_FANOUT~ +reset => ~NO_FANOUT~ +sink_valid => src_valid.DATAIN +sink_data[0] => src_data[0].DATAIN +sink_data[1] => src_data[1].DATAIN +sink_data[2] => src_data[2].DATAIN +sink_data[3] => src_data[3].DATAIN +sink_data[4] => src_data[4].DATAIN +sink_data[5] => src_data[5].DATAIN +sink_data[6] => src_data[6].DATAIN +sink_data[7] => src_data[7].DATAIN +sink_data[8] => src_data[8].DATAIN +sink_data[9] => src_data[9].DATAIN +sink_data[10] => src_data[10].DATAIN +sink_data[11] => src_data[11].DATAIN +sink_data[12] => src_data[12].DATAIN +sink_data[13] => src_data[13].DATAIN +sink_data[14] => src_data[14].DATAIN +sink_data[15] => src_data[15].DATAIN +sink_data[16] => src_data[16].DATAIN +sink_data[17] => src_data[17].DATAIN +sink_data[18] => src_data[18].DATAIN +sink_data[19] => src_data[19].DATAIN +sink_data[20] => src_data[20].DATAIN +sink_data[21] => src_data[21].DATAIN +sink_data[22] => src_data[22].DATAIN +sink_data[23] => src_data[23].DATAIN +sink_data[24] => src_data[24].DATAIN +sink_data[25] => src_data[25].DATAIN +sink_data[26] => src_data[26].DATAIN +sink_data[27] => src_data[27].DATAIN +sink_data[28] => src_data[28].DATAIN +sink_data[29] => src_data[29].DATAIN +sink_data[30] => src_data[30].DATAIN +sink_data[31] => src_data[31].DATAIN +sink_data[32] => src_data[32].DATAIN +sink_data[33] => src_data[33].DATAIN +sink_data[34] => src_data[34].DATAIN +sink_data[35] => src_data[35].DATAIN +sink_data[36] => src_data[36].DATAIN +sink_data[37] => src_data[37].DATAIN +sink_data[38] => src_data[38].DATAIN +sink_data[39] => src_data[39].DATAIN +sink_data[40] => src_data[40].DATAIN +sink_data[41] => src_data[41].DATAIN +sink_data[42] => src_data[42].DATAIN +sink_data[43] => src_data[43].DATAIN +sink_data[44] => src_data[44].DATAIN +sink_data[45] => src_data[45].DATAIN +sink_data[46] => src_data[46].DATAIN +sink_data[47] => src_data[47].DATAIN +sink_data[48] => src_data[48].DATAIN +sink_data[49] => src_data[49].DATAIN +sink_data[50] => src_data[50].DATAIN +sink_data[51] => src_data[51].DATAIN +sink_data[52] => src_data[52].DATAIN +sink_data[53] => src_data[53].DATAIN +sink_data[54] => src_data[54].DATAIN +sink_data[55] => src_data[55].DATAIN +sink_data[56] => src_data[56].DATAIN +sink_data[57] => src_data[57].DATAIN +sink_data[58] => src_data[58].DATAIN +sink_data[59] => src_data[59].DATAIN +sink_data[60] => src_data[60].DATAIN +sink_data[61] => src_data[61].DATAIN +sink_data[62] => src_data[62].DATAIN +sink_data[63] => src_data[63].DATAIN +sink_data[64] => src_data[64].DATAIN +sink_data[65] => src_data[65].DATAIN +sink_data[66] => src_data[66].DATAIN +sink_data[67] => src_data[67].DATAIN +sink_data[68] => src_data[68].DATAIN +sink_data[69] => src_data[69].DATAIN +sink_data[70] => src_data[70].DATAIN +sink_data[71] => src_data[71].DATAIN +sink_data[72] => src_data[72].DATAIN +sink_data[73] => src_data[73].DATAIN +sink_data[74] => src_data[74].DATAIN +sink_data[75] => src_data[75].DATAIN +sink_data[76] => src_data[76].DATAIN +sink_data[77] => src_data[77].DATAIN +sink_data[78] => src_data[78].DATAIN +sink_data[79] => src_data[79].DATAIN +sink_data[80] => src_data[80].DATAIN +sink_data[81] => src_data[81].DATAIN +sink_data[82] => src_data[82].DATAIN +sink_data[83] => src_data[83].DATAIN +sink_data[84] => src_data[84].DATAIN +sink_data[85] => src_data[85].DATAIN +sink_data[86] => src_data[86].DATAIN +sink_data[87] => src_data[87].DATAIN +sink_data[87] => Equal0.IN0 +sink_data[88] => src_data[88].DATAIN +sink_data[88] => Equal0.IN31 +sink_data[89] => src_data[89].DATAIN +sink_data[89] => Equal0.IN30 +sink_data[90] => src_data[90].DATAIN +sink_data[90] => Equal0.IN29 +sink_data[91] => src_data[91].DATAIN +sink_data[92] => src_data[92].DATAIN +sink_data[93] => src_data[93].DATAIN +sink_data[94] => src_data[94].DATAIN +sink_data[95] => src_data[95].DATAIN +sink_data[96] => src_data[96].DATAIN +sink_data[97] => src_data[97].DATAIN +sink_data[98] => src_data[98].DATAIN +sink_data[99] => src_data[99].DATAIN +sink_data[100] => src_data[100].DATAIN +sink_startofpacket => src_startofpacket.DATAIN +sink_endofpacket => src_endofpacket.DATAIN +sink_ready <= src_ready.DB_MAX_OUTPUT_PORT_TYPE +src_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE +src_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src_data[96] <= sink_data[96].DB_MAX_OUTPUT_PORT_TYPE +src_data[97] <= sink_data[97].DB_MAX_OUTPUT_PORT_TYPE +src_data[98] <= sink_data[98].DB_MAX_OUTPUT_PORT_TYPE +src_data[99] <= sink_data[99].DB_MAX_OUTPUT_PORT_TYPE +src_data[100] <= sink_data[100].DB_MAX_OUTPUT_PORT_TYPE +src_channel[0] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[1] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[2] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[3] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[4] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[5] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[6] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[7] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[8] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[9] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[10] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src_ready => sink_ready.DATAIN + + +|de0_nano_system|system:inst_cpu|system_id_router_002:id_router_007|system_id_router_002_default_decode:the_default_decode +default_destination_id[0] <= +default_destination_id[1] <= +default_destination_id[2] <= +default_destination_id[3] <= +default_src_channel[0] <= +default_src_channel[1] <= +default_src_channel[2] <= +default_src_channel[3] <= +default_src_channel[4] <= +default_src_channel[5] <= +default_src_channel[6] <= +default_src_channel[7] <= +default_src_channel[8] <= +default_src_channel[9] <= +default_src_channel[10] <= + + +|de0_nano_system|system:inst_cpu|system_id_router_002:id_router_008 +clk => ~NO_FANOUT~ +reset => ~NO_FANOUT~ +sink_valid => src_valid.DATAIN +sink_data[0] => src_data[0].DATAIN +sink_data[1] => src_data[1].DATAIN +sink_data[2] => src_data[2].DATAIN +sink_data[3] => src_data[3].DATAIN +sink_data[4] => src_data[4].DATAIN +sink_data[5] => src_data[5].DATAIN +sink_data[6] => src_data[6].DATAIN +sink_data[7] => src_data[7].DATAIN +sink_data[8] => src_data[8].DATAIN +sink_data[9] => src_data[9].DATAIN +sink_data[10] => src_data[10].DATAIN +sink_data[11] => src_data[11].DATAIN +sink_data[12] => src_data[12].DATAIN +sink_data[13] => src_data[13].DATAIN +sink_data[14] => src_data[14].DATAIN +sink_data[15] => src_data[15].DATAIN +sink_data[16] => src_data[16].DATAIN +sink_data[17] => src_data[17].DATAIN +sink_data[18] => src_data[18].DATAIN +sink_data[19] => src_data[19].DATAIN +sink_data[20] => src_data[20].DATAIN +sink_data[21] => src_data[21].DATAIN +sink_data[22] => src_data[22].DATAIN +sink_data[23] => src_data[23].DATAIN +sink_data[24] => src_data[24].DATAIN +sink_data[25] => src_data[25].DATAIN +sink_data[26] => src_data[26].DATAIN +sink_data[27] => src_data[27].DATAIN +sink_data[28] => src_data[28].DATAIN +sink_data[29] => src_data[29].DATAIN +sink_data[30] => src_data[30].DATAIN +sink_data[31] => src_data[31].DATAIN +sink_data[32] => src_data[32].DATAIN +sink_data[33] => src_data[33].DATAIN +sink_data[34] => src_data[34].DATAIN +sink_data[35] => src_data[35].DATAIN +sink_data[36] => src_data[36].DATAIN +sink_data[37] => src_data[37].DATAIN +sink_data[38] => src_data[38].DATAIN +sink_data[39] => src_data[39].DATAIN +sink_data[40] => src_data[40].DATAIN +sink_data[41] => src_data[41].DATAIN +sink_data[42] => src_data[42].DATAIN +sink_data[43] => src_data[43].DATAIN +sink_data[44] => src_data[44].DATAIN +sink_data[45] => src_data[45].DATAIN +sink_data[46] => src_data[46].DATAIN +sink_data[47] => src_data[47].DATAIN +sink_data[48] => src_data[48].DATAIN +sink_data[49] => src_data[49].DATAIN +sink_data[50] => src_data[50].DATAIN +sink_data[51] => src_data[51].DATAIN +sink_data[52] => src_data[52].DATAIN +sink_data[53] => src_data[53].DATAIN +sink_data[54] => src_data[54].DATAIN +sink_data[55] => src_data[55].DATAIN +sink_data[56] => src_data[56].DATAIN +sink_data[57] => src_data[57].DATAIN +sink_data[58] => src_data[58].DATAIN +sink_data[59] => src_data[59].DATAIN +sink_data[60] => src_data[60].DATAIN +sink_data[61] => src_data[61].DATAIN +sink_data[62] => src_data[62].DATAIN +sink_data[63] => src_data[63].DATAIN +sink_data[64] => src_data[64].DATAIN +sink_data[65] => src_data[65].DATAIN +sink_data[66] => src_data[66].DATAIN +sink_data[67] => src_data[67].DATAIN +sink_data[68] => src_data[68].DATAIN +sink_data[69] => src_data[69].DATAIN +sink_data[70] => src_data[70].DATAIN +sink_data[71] => src_data[71].DATAIN +sink_data[72] => src_data[72].DATAIN +sink_data[73] => src_data[73].DATAIN +sink_data[74] => src_data[74].DATAIN +sink_data[75] => src_data[75].DATAIN +sink_data[76] => src_data[76].DATAIN +sink_data[77] => src_data[77].DATAIN +sink_data[78] => src_data[78].DATAIN +sink_data[79] => src_data[79].DATAIN +sink_data[80] => src_data[80].DATAIN +sink_data[81] => src_data[81].DATAIN +sink_data[82] => src_data[82].DATAIN +sink_data[83] => src_data[83].DATAIN +sink_data[84] => src_data[84].DATAIN +sink_data[85] => src_data[85].DATAIN +sink_data[86] => src_data[86].DATAIN +sink_data[87] => src_data[87].DATAIN +sink_data[87] => Equal0.IN0 +sink_data[88] => src_data[88].DATAIN +sink_data[88] => Equal0.IN31 +sink_data[89] => src_data[89].DATAIN +sink_data[89] => Equal0.IN30 +sink_data[90] => src_data[90].DATAIN +sink_data[90] => Equal0.IN29 +sink_data[91] => src_data[91].DATAIN +sink_data[92] => src_data[92].DATAIN +sink_data[93] => src_data[93].DATAIN +sink_data[94] => src_data[94].DATAIN +sink_data[95] => src_data[95].DATAIN +sink_data[96] => src_data[96].DATAIN +sink_data[97] => src_data[97].DATAIN +sink_data[98] => src_data[98].DATAIN +sink_data[99] => src_data[99].DATAIN +sink_data[100] => src_data[100].DATAIN +sink_startofpacket => src_startofpacket.DATAIN +sink_endofpacket => src_endofpacket.DATAIN +sink_ready <= src_ready.DB_MAX_OUTPUT_PORT_TYPE +src_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE +src_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src_data[96] <= sink_data[96].DB_MAX_OUTPUT_PORT_TYPE +src_data[97] <= sink_data[97].DB_MAX_OUTPUT_PORT_TYPE +src_data[98] <= sink_data[98].DB_MAX_OUTPUT_PORT_TYPE +src_data[99] <= sink_data[99].DB_MAX_OUTPUT_PORT_TYPE +src_data[100] <= sink_data[100].DB_MAX_OUTPUT_PORT_TYPE +src_channel[0] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[1] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[2] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[3] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[4] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[5] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[6] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[7] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[8] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[9] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[10] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src_ready => sink_ready.DATAIN + + +|de0_nano_system|system:inst_cpu|system_id_router_002:id_router_008|system_id_router_002_default_decode:the_default_decode +default_destination_id[0] <= +default_destination_id[1] <= +default_destination_id[2] <= +default_destination_id[3] <= +default_src_channel[0] <= +default_src_channel[1] <= +default_src_channel[2] <= +default_src_channel[3] <= +default_src_channel[4] <= +default_src_channel[5] <= +default_src_channel[6] <= +default_src_channel[7] <= +default_src_channel[8] <= +default_src_channel[9] <= +default_src_channel[10] <= + + +|de0_nano_system|system:inst_cpu|system_id_router_002:id_router_009 +clk => ~NO_FANOUT~ +reset => ~NO_FANOUT~ +sink_valid => src_valid.DATAIN +sink_data[0] => src_data[0].DATAIN +sink_data[1] => src_data[1].DATAIN +sink_data[2] => src_data[2].DATAIN +sink_data[3] => src_data[3].DATAIN +sink_data[4] => src_data[4].DATAIN +sink_data[5] => src_data[5].DATAIN +sink_data[6] => src_data[6].DATAIN +sink_data[7] => src_data[7].DATAIN +sink_data[8] => src_data[8].DATAIN +sink_data[9] => src_data[9].DATAIN +sink_data[10] => src_data[10].DATAIN +sink_data[11] => src_data[11].DATAIN +sink_data[12] => src_data[12].DATAIN +sink_data[13] => src_data[13].DATAIN +sink_data[14] => src_data[14].DATAIN +sink_data[15] => src_data[15].DATAIN +sink_data[16] => src_data[16].DATAIN +sink_data[17] => src_data[17].DATAIN +sink_data[18] => src_data[18].DATAIN +sink_data[19] => src_data[19].DATAIN +sink_data[20] => src_data[20].DATAIN +sink_data[21] => src_data[21].DATAIN +sink_data[22] => src_data[22].DATAIN +sink_data[23] => src_data[23].DATAIN +sink_data[24] => src_data[24].DATAIN +sink_data[25] => src_data[25].DATAIN +sink_data[26] => src_data[26].DATAIN +sink_data[27] => src_data[27].DATAIN +sink_data[28] => src_data[28].DATAIN +sink_data[29] => src_data[29].DATAIN +sink_data[30] => src_data[30].DATAIN +sink_data[31] => src_data[31].DATAIN +sink_data[32] => src_data[32].DATAIN +sink_data[33] => src_data[33].DATAIN +sink_data[34] => src_data[34].DATAIN +sink_data[35] => src_data[35].DATAIN +sink_data[36] => src_data[36].DATAIN +sink_data[37] => src_data[37].DATAIN +sink_data[38] => src_data[38].DATAIN +sink_data[39] => src_data[39].DATAIN +sink_data[40] => src_data[40].DATAIN +sink_data[41] => src_data[41].DATAIN +sink_data[42] => src_data[42].DATAIN +sink_data[43] => src_data[43].DATAIN +sink_data[44] => src_data[44].DATAIN +sink_data[45] => src_data[45].DATAIN +sink_data[46] => src_data[46].DATAIN +sink_data[47] => src_data[47].DATAIN +sink_data[48] => src_data[48].DATAIN +sink_data[49] => src_data[49].DATAIN +sink_data[50] => src_data[50].DATAIN +sink_data[51] => src_data[51].DATAIN +sink_data[52] => src_data[52].DATAIN +sink_data[53] => src_data[53].DATAIN +sink_data[54] => src_data[54].DATAIN +sink_data[55] => src_data[55].DATAIN +sink_data[56] => src_data[56].DATAIN +sink_data[57] => src_data[57].DATAIN +sink_data[58] => src_data[58].DATAIN +sink_data[59] => src_data[59].DATAIN +sink_data[60] => src_data[60].DATAIN +sink_data[61] => src_data[61].DATAIN +sink_data[62] => src_data[62].DATAIN +sink_data[63] => src_data[63].DATAIN +sink_data[64] => src_data[64].DATAIN +sink_data[65] => src_data[65].DATAIN +sink_data[66] => src_data[66].DATAIN +sink_data[67] => src_data[67].DATAIN +sink_data[68] => src_data[68].DATAIN +sink_data[69] => src_data[69].DATAIN +sink_data[70] => src_data[70].DATAIN +sink_data[71] => src_data[71].DATAIN +sink_data[72] => src_data[72].DATAIN +sink_data[73] => src_data[73].DATAIN +sink_data[74] => src_data[74].DATAIN +sink_data[75] => src_data[75].DATAIN +sink_data[76] => src_data[76].DATAIN +sink_data[77] => src_data[77].DATAIN +sink_data[78] => src_data[78].DATAIN +sink_data[79] => src_data[79].DATAIN +sink_data[80] => src_data[80].DATAIN +sink_data[81] => src_data[81].DATAIN +sink_data[82] => src_data[82].DATAIN +sink_data[83] => src_data[83].DATAIN +sink_data[84] => src_data[84].DATAIN +sink_data[85] => src_data[85].DATAIN +sink_data[86] => src_data[86].DATAIN +sink_data[87] => src_data[87].DATAIN +sink_data[87] => Equal0.IN0 +sink_data[88] => src_data[88].DATAIN +sink_data[88] => Equal0.IN31 +sink_data[89] => src_data[89].DATAIN +sink_data[89] => Equal0.IN30 +sink_data[90] => src_data[90].DATAIN +sink_data[90] => Equal0.IN29 +sink_data[91] => src_data[91].DATAIN +sink_data[92] => src_data[92].DATAIN +sink_data[93] => src_data[93].DATAIN +sink_data[94] => src_data[94].DATAIN +sink_data[95] => src_data[95].DATAIN +sink_data[96] => src_data[96].DATAIN +sink_data[97] => src_data[97].DATAIN +sink_data[98] => src_data[98].DATAIN +sink_data[99] => src_data[99].DATAIN +sink_data[100] => src_data[100].DATAIN +sink_startofpacket => src_startofpacket.DATAIN +sink_endofpacket => src_endofpacket.DATAIN +sink_ready <= src_ready.DB_MAX_OUTPUT_PORT_TYPE +src_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE +src_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src_data[96] <= sink_data[96].DB_MAX_OUTPUT_PORT_TYPE +src_data[97] <= sink_data[97].DB_MAX_OUTPUT_PORT_TYPE +src_data[98] <= sink_data[98].DB_MAX_OUTPUT_PORT_TYPE +src_data[99] <= sink_data[99].DB_MAX_OUTPUT_PORT_TYPE +src_data[100] <= sink_data[100].DB_MAX_OUTPUT_PORT_TYPE +src_channel[0] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[1] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[2] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[3] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[4] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[5] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[6] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[7] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[8] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[9] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[10] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src_ready => sink_ready.DATAIN + + +|de0_nano_system|system:inst_cpu|system_id_router_002:id_router_009|system_id_router_002_default_decode:the_default_decode +default_destination_id[0] <= +default_destination_id[1] <= +default_destination_id[2] <= +default_destination_id[3] <= +default_src_channel[0] <= +default_src_channel[1] <= +default_src_channel[2] <= +default_src_channel[3] <= +default_src_channel[4] <= +default_src_channel[5] <= +default_src_channel[6] <= +default_src_channel[7] <= +default_src_channel[8] <= +default_src_channel[9] <= +default_src_channel[10] <= + + +|de0_nano_system|system:inst_cpu|system_id_router_002:id_router_010 +clk => ~NO_FANOUT~ +reset => ~NO_FANOUT~ +sink_valid => src_valid.DATAIN +sink_data[0] => src_data[0].DATAIN +sink_data[1] => src_data[1].DATAIN +sink_data[2] => src_data[2].DATAIN +sink_data[3] => src_data[3].DATAIN +sink_data[4] => src_data[4].DATAIN +sink_data[5] => src_data[5].DATAIN +sink_data[6] => src_data[6].DATAIN +sink_data[7] => src_data[7].DATAIN +sink_data[8] => src_data[8].DATAIN +sink_data[9] => src_data[9].DATAIN +sink_data[10] => src_data[10].DATAIN +sink_data[11] => src_data[11].DATAIN +sink_data[12] => src_data[12].DATAIN +sink_data[13] => src_data[13].DATAIN +sink_data[14] => src_data[14].DATAIN +sink_data[15] => src_data[15].DATAIN +sink_data[16] => src_data[16].DATAIN +sink_data[17] => src_data[17].DATAIN +sink_data[18] => src_data[18].DATAIN +sink_data[19] => src_data[19].DATAIN +sink_data[20] => src_data[20].DATAIN +sink_data[21] => src_data[21].DATAIN +sink_data[22] => src_data[22].DATAIN +sink_data[23] => src_data[23].DATAIN +sink_data[24] => src_data[24].DATAIN +sink_data[25] => src_data[25].DATAIN +sink_data[26] => src_data[26].DATAIN +sink_data[27] => src_data[27].DATAIN +sink_data[28] => src_data[28].DATAIN +sink_data[29] => src_data[29].DATAIN +sink_data[30] => src_data[30].DATAIN +sink_data[31] => src_data[31].DATAIN +sink_data[32] => src_data[32].DATAIN +sink_data[33] => src_data[33].DATAIN +sink_data[34] => src_data[34].DATAIN +sink_data[35] => src_data[35].DATAIN +sink_data[36] => src_data[36].DATAIN +sink_data[37] => src_data[37].DATAIN +sink_data[38] => src_data[38].DATAIN +sink_data[39] => src_data[39].DATAIN +sink_data[40] => src_data[40].DATAIN +sink_data[41] => src_data[41].DATAIN +sink_data[42] => src_data[42].DATAIN +sink_data[43] => src_data[43].DATAIN +sink_data[44] => src_data[44].DATAIN +sink_data[45] => src_data[45].DATAIN +sink_data[46] => src_data[46].DATAIN +sink_data[47] => src_data[47].DATAIN +sink_data[48] => src_data[48].DATAIN +sink_data[49] => src_data[49].DATAIN +sink_data[50] => src_data[50].DATAIN +sink_data[51] => src_data[51].DATAIN +sink_data[52] => src_data[52].DATAIN +sink_data[53] => src_data[53].DATAIN +sink_data[54] => src_data[54].DATAIN +sink_data[55] => src_data[55].DATAIN +sink_data[56] => src_data[56].DATAIN +sink_data[57] => src_data[57].DATAIN +sink_data[58] => src_data[58].DATAIN +sink_data[59] => src_data[59].DATAIN +sink_data[60] => src_data[60].DATAIN +sink_data[61] => src_data[61].DATAIN +sink_data[62] => src_data[62].DATAIN +sink_data[63] => src_data[63].DATAIN +sink_data[64] => src_data[64].DATAIN +sink_data[65] => src_data[65].DATAIN +sink_data[66] => src_data[66].DATAIN +sink_data[67] => src_data[67].DATAIN +sink_data[68] => src_data[68].DATAIN +sink_data[69] => src_data[69].DATAIN +sink_data[70] => src_data[70].DATAIN +sink_data[71] => src_data[71].DATAIN +sink_data[72] => src_data[72].DATAIN +sink_data[73] => src_data[73].DATAIN +sink_data[74] => src_data[74].DATAIN +sink_data[75] => src_data[75].DATAIN +sink_data[76] => src_data[76].DATAIN +sink_data[77] => src_data[77].DATAIN +sink_data[78] => src_data[78].DATAIN +sink_data[79] => src_data[79].DATAIN +sink_data[80] => src_data[80].DATAIN +sink_data[81] => src_data[81].DATAIN +sink_data[82] => src_data[82].DATAIN +sink_data[83] => src_data[83].DATAIN +sink_data[84] => src_data[84].DATAIN +sink_data[85] => src_data[85].DATAIN +sink_data[86] => src_data[86].DATAIN +sink_data[87] => src_data[87].DATAIN +sink_data[87] => Equal0.IN0 +sink_data[88] => src_data[88].DATAIN +sink_data[88] => Equal0.IN31 +sink_data[89] => src_data[89].DATAIN +sink_data[89] => Equal0.IN30 +sink_data[90] => src_data[90].DATAIN +sink_data[90] => Equal0.IN29 +sink_data[91] => src_data[91].DATAIN +sink_data[92] => src_data[92].DATAIN +sink_data[93] => src_data[93].DATAIN +sink_data[94] => src_data[94].DATAIN +sink_data[95] => src_data[95].DATAIN +sink_data[96] => src_data[96].DATAIN +sink_data[97] => src_data[97].DATAIN +sink_data[98] => src_data[98].DATAIN +sink_data[99] => src_data[99].DATAIN +sink_data[100] => src_data[100].DATAIN +sink_startofpacket => src_startofpacket.DATAIN +sink_endofpacket => src_endofpacket.DATAIN +sink_ready <= src_ready.DB_MAX_OUTPUT_PORT_TYPE +src_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE +src_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src_data[96] <= sink_data[96].DB_MAX_OUTPUT_PORT_TYPE +src_data[97] <= sink_data[97].DB_MAX_OUTPUT_PORT_TYPE +src_data[98] <= sink_data[98].DB_MAX_OUTPUT_PORT_TYPE +src_data[99] <= sink_data[99].DB_MAX_OUTPUT_PORT_TYPE +src_data[100] <= sink_data[100].DB_MAX_OUTPUT_PORT_TYPE +src_channel[0] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[1] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[2] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[3] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[4] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[5] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[6] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[7] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[8] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[9] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_channel[10] <= src_channel.DB_MAX_OUTPUT_PORT_TYPE +src_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src_ready => sink_ready.DATAIN + + +|de0_nano_system|system:inst_cpu|system_id_router_002:id_router_010|system_id_router_002_default_decode:the_default_decode +default_destination_id[0] <= +default_destination_id[1] <= +default_destination_id[2] <= +default_destination_id[3] <= +default_src_channel[0] <= +default_src_channel[1] <= +default_src_channel[2] <= +default_src_channel[3] <= +default_src_channel[4] <= +default_src_channel[5] <= +default_src_channel[6] <= +default_src_channel[7] <= +default_src_channel[8] <= +default_src_channel[9] <= +default_src_channel[10] <= + + +|de0_nano_system|system:inst_cpu|altera_merlin_traffic_limiter:limiter +clk => has_pending_responses.CLK +clk => pending_response_count[0].CLK +clk => pending_response_count[1].CLK +clk => pending_response_count[2].CLK +clk => pending_response_count[3].CLK +clk => last_channel[0].CLK +clk => last_channel[1].CLK +clk => last_channel[2].CLK +clk => last_channel[3].CLK +clk => last_channel[4].CLK +clk => last_channel[5].CLK +clk => last_channel[6].CLK +clk => last_channel[7].CLK +clk => last_channel[8].CLK +clk => last_channel[9].CLK +clk => last_channel[10].CLK +clk => last_dest_id[0].CLK +clk => last_dest_id[1].CLK +clk => last_dest_id[2].CLK +clk => last_dest_id[3].CLK +reset => has_pending_responses.ACLR +reset => pending_response_count[0].ACLR +reset => pending_response_count[1].ACLR +reset => pending_response_count[2].ACLR +reset => pending_response_count[3].ACLR +reset => last_channel[0].ACLR +reset => last_channel[1].ACLR +reset => last_channel[2].ACLR +reset => last_channel[3].ACLR +reset => last_channel[4].ACLR +reset => last_channel[5].ACLR +reset => last_channel[6].ACLR +reset => last_channel[7].ACLR +reset => last_channel[8].ACLR +reset => last_channel[9].ACLR +reset => last_channel[10].ACLR +reset => last_dest_id[0].ACLR +reset => last_dest_id[1].ACLR +reset => last_dest_id[2].ACLR +reset => last_dest_id[3].ACLR +cmd_sink_valid => internal_valid.DATAA +cmd_sink_valid => cmd_src_valid.IN0 +cmd_sink_valid => cmd_src_valid.IN0 +cmd_sink_valid => cmd_src_valid.IN0 +cmd_sink_valid => cmd_src_valid.IN0 +cmd_sink_valid => cmd_src_valid.IN0 +cmd_sink_valid => cmd_src_valid.IN0 +cmd_sink_valid => cmd_src_valid.IN0 +cmd_sink_valid => cmd_src_valid.IN0 +cmd_sink_valid => cmd_src_valid.IN0 +cmd_sink_valid => cmd_src_valid.IN0 +cmd_sink_valid => cmd_src_valid.IN0 +cmd_sink_valid => save_dest_id.IN1 +cmd_sink_data[0] => cmd_src_data[0].DATAIN +cmd_sink_data[1] => cmd_src_data[1].DATAIN +cmd_sink_data[2] => cmd_src_data[2].DATAIN +cmd_sink_data[3] => cmd_src_data[3].DATAIN +cmd_sink_data[4] => cmd_src_data[4].DATAIN +cmd_sink_data[5] => cmd_src_data[5].DATAIN +cmd_sink_data[6] => cmd_src_data[6].DATAIN +cmd_sink_data[7] => cmd_src_data[7].DATAIN +cmd_sink_data[8] => cmd_src_data[8].DATAIN +cmd_sink_data[9] => cmd_src_data[9].DATAIN +cmd_sink_data[10] => cmd_src_data[10].DATAIN +cmd_sink_data[11] => cmd_src_data[11].DATAIN +cmd_sink_data[12] => cmd_src_data[12].DATAIN +cmd_sink_data[13] => cmd_src_data[13].DATAIN +cmd_sink_data[14] => cmd_src_data[14].DATAIN +cmd_sink_data[15] => cmd_src_data[15].DATAIN +cmd_sink_data[16] => cmd_src_data[16].DATAIN +cmd_sink_data[17] => cmd_src_data[17].DATAIN +cmd_sink_data[18] => cmd_src_data[18].DATAIN +cmd_sink_data[19] => cmd_src_data[19].DATAIN +cmd_sink_data[20] => cmd_src_data[20].DATAIN +cmd_sink_data[21] => cmd_src_data[21].DATAIN +cmd_sink_data[22] => cmd_src_data[22].DATAIN +cmd_sink_data[23] => cmd_src_data[23].DATAIN +cmd_sink_data[24] => cmd_src_data[24].DATAIN +cmd_sink_data[25] => cmd_src_data[25].DATAIN +cmd_sink_data[26] => cmd_src_data[26].DATAIN +cmd_sink_data[27] => cmd_src_data[27].DATAIN +cmd_sink_data[28] => cmd_src_data[28].DATAIN +cmd_sink_data[29] => cmd_src_data[29].DATAIN +cmd_sink_data[30] => cmd_src_data[30].DATAIN +cmd_sink_data[31] => cmd_src_data[31].DATAIN +cmd_sink_data[32] => cmd_src_data[32].DATAIN +cmd_sink_data[33] => cmd_src_data[33].DATAIN +cmd_sink_data[34] => cmd_src_data[34].DATAIN +cmd_sink_data[35] => cmd_src_data[35].DATAIN +cmd_sink_data[36] => cmd_src_data[36].DATAIN +cmd_sink_data[37] => cmd_src_data[37].DATAIN +cmd_sink_data[38] => cmd_src_data[38].DATAIN +cmd_sink_data[39] => cmd_src_data[39].DATAIN +cmd_sink_data[40] => cmd_src_data[40].DATAIN +cmd_sink_data[41] => cmd_src_data[41].DATAIN +cmd_sink_data[42] => cmd_src_data[42].DATAIN +cmd_sink_data[43] => cmd_src_data[43].DATAIN +cmd_sink_data[44] => cmd_src_data[44].DATAIN +cmd_sink_data[45] => cmd_src_data[45].DATAIN +cmd_sink_data[46] => cmd_src_data[46].DATAIN +cmd_sink_data[47] => cmd_src_data[47].DATAIN +cmd_sink_data[48] => cmd_src_data[48].DATAIN +cmd_sink_data[49] => cmd_src_data[49].DATAIN +cmd_sink_data[50] => cmd_src_data[50].DATAIN +cmd_sink_data[51] => cmd_src_data[51].DATAIN +cmd_sink_data[52] => cmd_src_data[52].DATAIN +cmd_sink_data[53] => cmd_src_data[53].DATAIN +cmd_sink_data[54] => cmd_src_data[54].DATAIN +cmd_sink_data[55] => cmd_src_data[55].DATAIN +cmd_sink_data[56] => cmd_src_data[56].DATAIN +cmd_sink_data[57] => cmd_src_data[57].DATAIN +cmd_sink_data[58] => cmd_src_data[58].DATAIN +cmd_sink_data[59] => cmd_src_data[59].DATAIN +cmd_sink_data[60] => cmd_src_data[60].DATAIN +cmd_sink_data[61] => cmd_src_data[61].DATAIN +cmd_sink_data[62] => cmd_src_data[62].DATAIN +cmd_sink_data[63] => cmd_src_data[63].DATAIN +cmd_sink_data[63] => save_dest_id.IN1 +cmd_sink_data[63] => nonposted_cmd_accepted.IN1 +cmd_sink_data[63] => suppress.IN1 +cmd_sink_data[64] => cmd_src_data[64].DATAIN +cmd_sink_data[65] => cmd_src_data[65].DATAIN +cmd_sink_data[66] => cmd_src_data[66].DATAIN +cmd_sink_data[67] => cmd_src_data[67].DATAIN +cmd_sink_data[68] => cmd_src_data[68].DATAIN +cmd_sink_data[69] => cmd_src_data[69].DATAIN +cmd_sink_data[70] => cmd_src_data[70].DATAIN +cmd_sink_data[71] => cmd_src_data[71].DATAIN +cmd_sink_data[72] => cmd_src_data[72].DATAIN +cmd_sink_data[73] => cmd_src_data[73].DATAIN +cmd_sink_data[74] => cmd_src_data[74].DATAIN +cmd_sink_data[75] => cmd_src_data[75].DATAIN +cmd_sink_data[76] => cmd_src_data[76].DATAIN +cmd_sink_data[77] => cmd_src_data[77].DATAIN +cmd_sink_data[78] => cmd_src_data[78].DATAIN +cmd_sink_data[79] => cmd_src_data[79].DATAIN +cmd_sink_data[80] => cmd_src_data[80].DATAIN +cmd_sink_data[81] => cmd_src_data[81].DATAIN +cmd_sink_data[82] => cmd_src_data[82].DATAIN +cmd_sink_data[83] => cmd_src_data[83].DATAIN +cmd_sink_data[84] => cmd_src_data[84].DATAIN +cmd_sink_data[85] => cmd_src_data[85].DATAIN +cmd_sink_data[86] => cmd_src_data[86].DATAIN +cmd_sink_data[87] => Equal0.IN3 +cmd_sink_data[87] => cmd_src_data[87].DATAIN +cmd_sink_data[87] => last_dest_id[0].DATAIN +cmd_sink_data[88] => Equal0.IN2 +cmd_sink_data[88] => cmd_src_data[88].DATAIN +cmd_sink_data[88] => last_dest_id[1].DATAIN +cmd_sink_data[89] => Equal0.IN1 +cmd_sink_data[89] => cmd_src_data[89].DATAIN +cmd_sink_data[89] => last_dest_id[2].DATAIN +cmd_sink_data[90] => Equal0.IN0 +cmd_sink_data[90] => cmd_src_data[90].DATAIN +cmd_sink_data[90] => last_dest_id[3].DATAIN +cmd_sink_data[91] => cmd_src_data[91].DATAIN +cmd_sink_data[92] => cmd_src_data[92].DATAIN +cmd_sink_data[93] => cmd_src_data[93].DATAIN +cmd_sink_data[94] => cmd_src_data[94].DATAIN +cmd_sink_data[95] => cmd_src_data[95].DATAIN +cmd_sink_data[96] => cmd_src_data[96].DATAIN +cmd_sink_data[97] => cmd_src_data[97].DATAIN +cmd_sink_data[98] => cmd_src_data[98].DATAIN +cmd_sink_data[99] => cmd_src_data[99].DATAIN +cmd_sink_data[100] => cmd_src_data[100].DATAIN +cmd_sink_channel[0] => cmd_src_valid.IN1 +cmd_sink_channel[0] => cmd_src_channel[0].DATAIN +cmd_sink_channel[0] => last_channel[0].DATAIN +cmd_sink_channel[1] => cmd_src_valid.IN1 +cmd_sink_channel[1] => cmd_src_channel[1].DATAIN +cmd_sink_channel[1] => last_channel[1].DATAIN +cmd_sink_channel[2] => cmd_src_valid.IN1 +cmd_sink_channel[2] => cmd_src_channel[2].DATAIN +cmd_sink_channel[2] => last_channel[2].DATAIN +cmd_sink_channel[3] => cmd_src_valid.IN1 +cmd_sink_channel[3] => cmd_src_channel[3].DATAIN +cmd_sink_channel[3] => last_channel[3].DATAIN +cmd_sink_channel[4] => cmd_src_valid.IN1 +cmd_sink_channel[4] => cmd_src_channel[4].DATAIN +cmd_sink_channel[4] => last_channel[4].DATAIN +cmd_sink_channel[5] => cmd_src_valid.IN1 +cmd_sink_channel[5] => cmd_src_channel[5].DATAIN +cmd_sink_channel[5] => last_channel[5].DATAIN +cmd_sink_channel[6] => cmd_src_valid.IN1 +cmd_sink_channel[6] => cmd_src_channel[6].DATAIN +cmd_sink_channel[6] => last_channel[6].DATAIN +cmd_sink_channel[7] => cmd_src_valid.IN1 +cmd_sink_channel[7] => cmd_src_channel[7].DATAIN +cmd_sink_channel[7] => last_channel[7].DATAIN +cmd_sink_channel[8] => cmd_src_valid.IN1 +cmd_sink_channel[8] => cmd_src_channel[8].DATAIN +cmd_sink_channel[8] => last_channel[8].DATAIN +cmd_sink_channel[9] => cmd_src_valid.IN1 +cmd_sink_channel[9] => cmd_src_channel[9].DATAIN +cmd_sink_channel[9] => last_channel[9].DATAIN +cmd_sink_channel[10] => cmd_src_valid.IN1 +cmd_sink_channel[10] => cmd_src_channel[10].DATAIN +cmd_sink_channel[10] => last_channel[10].DATAIN +cmd_sink_startofpacket => cmd_src_startofpacket.DATAIN +cmd_sink_endofpacket => nonposted_cmd_accepted.IN0 +cmd_sink_endofpacket => cmd_src_endofpacket.DATAIN +cmd_sink_ready <= stage2_ready.DB_MAX_OUTPUT_PORT_TYPE +cmd_src_valid[0] <= cmd_src_valid.DB_MAX_OUTPUT_PORT_TYPE +cmd_src_valid[1] <= cmd_src_valid.DB_MAX_OUTPUT_PORT_TYPE +cmd_src_valid[2] <= cmd_src_valid.DB_MAX_OUTPUT_PORT_TYPE +cmd_src_valid[3] <= cmd_src_valid.DB_MAX_OUTPUT_PORT_TYPE +cmd_src_valid[4] <= cmd_src_valid.DB_MAX_OUTPUT_PORT_TYPE +cmd_src_valid[5] <= cmd_src_valid.DB_MAX_OUTPUT_PORT_TYPE +cmd_src_valid[6] <= cmd_src_valid.DB_MAX_OUTPUT_PORT_TYPE +cmd_src_valid[7] <= cmd_src_valid.DB_MAX_OUTPUT_PORT_TYPE +cmd_src_valid[8] <= cmd_src_valid.DB_MAX_OUTPUT_PORT_TYPE +cmd_src_valid[9] <= cmd_src_valid.DB_MAX_OUTPUT_PORT_TYPE +cmd_src_valid[10] <= cmd_src_valid.DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[0] <= cmd_sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[1] <= cmd_sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[2] <= cmd_sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[3] <= cmd_sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[4] <= cmd_sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[5] <= cmd_sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[6] <= cmd_sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[7] <= cmd_sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[8] <= cmd_sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[9] <= cmd_sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[10] <= cmd_sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[11] <= cmd_sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[12] <= cmd_sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[13] <= cmd_sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[14] <= cmd_sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[15] <= cmd_sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[16] <= cmd_sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[17] <= cmd_sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[18] <= cmd_sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[19] <= cmd_sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[20] <= cmd_sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[21] <= cmd_sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[22] <= cmd_sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[23] <= cmd_sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[24] <= cmd_sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[25] <= cmd_sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[26] <= cmd_sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[27] <= cmd_sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[28] <= cmd_sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[29] <= cmd_sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[30] <= cmd_sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[31] <= cmd_sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[32] <= cmd_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[33] <= cmd_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[34] <= cmd_sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[35] <= cmd_sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[36] <= cmd_sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[37] <= cmd_sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[38] <= cmd_sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[39] <= cmd_sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[40] <= cmd_sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[41] <= cmd_sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[42] <= cmd_sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[43] <= cmd_sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[44] <= cmd_sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[45] <= cmd_sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[46] <= cmd_sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[47] <= cmd_sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[48] <= cmd_sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[49] <= cmd_sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[50] <= cmd_sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[51] <= cmd_sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[52] <= cmd_sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[53] <= cmd_sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[54] <= cmd_sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[55] <= cmd_sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[56] <= cmd_sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[57] <= cmd_sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[58] <= cmd_sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[59] <= cmd_sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[60] <= cmd_sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[61] <= cmd_sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[62] <= cmd_sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[63] <= cmd_sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[64] <= cmd_sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[65] <= cmd_sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[66] <= cmd_sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[67] <= cmd_sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[68] <= cmd_sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[69] <= cmd_sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[70] <= cmd_sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[71] <= cmd_sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[72] <= cmd_sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[73] <= cmd_sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[74] <= cmd_sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[75] <= cmd_sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[76] <= cmd_sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[77] <= cmd_sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[78] <= cmd_sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[79] <= cmd_sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[80] <= cmd_sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[81] <= cmd_sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[82] <= cmd_sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[83] <= cmd_sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[84] <= cmd_sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[85] <= cmd_sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[86] <= cmd_sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[87] <= cmd_sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[88] <= cmd_sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[89] <= cmd_sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[90] <= cmd_sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[91] <= cmd_sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[92] <= cmd_sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[93] <= cmd_sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[94] <= cmd_sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[95] <= cmd_sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[96] <= cmd_sink_data[96].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[97] <= cmd_sink_data[97].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[98] <= cmd_sink_data[98].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[99] <= cmd_sink_data[99].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[100] <= cmd_sink_data[100].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_channel[0] <= cmd_sink_channel[0].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_channel[1] <= cmd_sink_channel[1].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_channel[2] <= cmd_sink_channel[2].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_channel[3] <= cmd_sink_channel[3].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_channel[4] <= cmd_sink_channel[4].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_channel[5] <= cmd_sink_channel[5].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_channel[6] <= cmd_sink_channel[6].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_channel[7] <= cmd_sink_channel[7].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_channel[8] <= cmd_sink_channel[8].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_channel[9] <= cmd_sink_channel[9].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_channel[10] <= cmd_sink_channel[10].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_startofpacket <= cmd_sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +cmd_src_endofpacket <= cmd_sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +cmd_src_ready => nonposted_cmd_accepted.IN1 +cmd_src_ready => stage2_ready.DATAA +rsp_sink_valid => response_accepted.IN0 +rsp_sink_valid => rsp_src_valid.DATAIN +rsp_sink_data[0] => rsp_src_data[0].DATAIN +rsp_sink_data[1] => rsp_src_data[1].DATAIN +rsp_sink_data[2] => rsp_src_data[2].DATAIN +rsp_sink_data[3] => rsp_src_data[3].DATAIN +rsp_sink_data[4] => rsp_src_data[4].DATAIN +rsp_sink_data[5] => rsp_src_data[5].DATAIN +rsp_sink_data[6] => rsp_src_data[6].DATAIN +rsp_sink_data[7] => rsp_src_data[7].DATAIN +rsp_sink_data[8] => rsp_src_data[8].DATAIN +rsp_sink_data[9] => rsp_src_data[9].DATAIN +rsp_sink_data[10] => rsp_src_data[10].DATAIN +rsp_sink_data[11] => rsp_src_data[11].DATAIN +rsp_sink_data[12] => rsp_src_data[12].DATAIN +rsp_sink_data[13] => rsp_src_data[13].DATAIN +rsp_sink_data[14] => rsp_src_data[14].DATAIN +rsp_sink_data[15] => rsp_src_data[15].DATAIN +rsp_sink_data[16] => rsp_src_data[16].DATAIN +rsp_sink_data[17] => rsp_src_data[17].DATAIN +rsp_sink_data[18] => rsp_src_data[18].DATAIN +rsp_sink_data[19] => rsp_src_data[19].DATAIN +rsp_sink_data[20] => rsp_src_data[20].DATAIN +rsp_sink_data[21] => rsp_src_data[21].DATAIN +rsp_sink_data[22] => rsp_src_data[22].DATAIN +rsp_sink_data[23] => rsp_src_data[23].DATAIN +rsp_sink_data[24] => rsp_src_data[24].DATAIN +rsp_sink_data[25] => rsp_src_data[25].DATAIN +rsp_sink_data[26] => rsp_src_data[26].DATAIN +rsp_sink_data[27] => rsp_src_data[27].DATAIN +rsp_sink_data[28] => rsp_src_data[28].DATAIN +rsp_sink_data[29] => rsp_src_data[29].DATAIN +rsp_sink_data[30] => rsp_src_data[30].DATAIN +rsp_sink_data[31] => rsp_src_data[31].DATAIN +rsp_sink_data[32] => rsp_src_data[32].DATAIN +rsp_sink_data[33] => rsp_src_data[33].DATAIN +rsp_sink_data[34] => rsp_src_data[34].DATAIN +rsp_sink_data[35] => rsp_src_data[35].DATAIN +rsp_sink_data[36] => rsp_src_data[36].DATAIN +rsp_sink_data[37] => rsp_src_data[37].DATAIN +rsp_sink_data[38] => rsp_src_data[38].DATAIN +rsp_sink_data[39] => rsp_src_data[39].DATAIN +rsp_sink_data[40] => rsp_src_data[40].DATAIN +rsp_sink_data[41] => rsp_src_data[41].DATAIN +rsp_sink_data[42] => rsp_src_data[42].DATAIN +rsp_sink_data[43] => rsp_src_data[43].DATAIN +rsp_sink_data[44] => rsp_src_data[44].DATAIN +rsp_sink_data[45] => rsp_src_data[45].DATAIN +rsp_sink_data[46] => rsp_src_data[46].DATAIN +rsp_sink_data[47] => rsp_src_data[47].DATAIN +rsp_sink_data[48] => rsp_src_data[48].DATAIN +rsp_sink_data[49] => rsp_src_data[49].DATAIN +rsp_sink_data[50] => rsp_src_data[50].DATAIN +rsp_sink_data[51] => rsp_src_data[51].DATAIN +rsp_sink_data[52] => rsp_src_data[52].DATAIN +rsp_sink_data[53] => rsp_src_data[53].DATAIN +rsp_sink_data[54] => rsp_src_data[54].DATAIN +rsp_sink_data[55] => rsp_src_data[55].DATAIN +rsp_sink_data[56] => rsp_src_data[56].DATAIN +rsp_sink_data[57] => rsp_src_data[57].DATAIN +rsp_sink_data[58] => rsp_src_data[58].DATAIN +rsp_sink_data[59] => rsp_src_data[59].DATAIN +rsp_sink_data[60] => rsp_src_data[60].DATAIN +rsp_sink_data[61] => rsp_src_data[61].DATAIN +rsp_sink_data[62] => rsp_src_data[62].DATAIN +rsp_sink_data[63] => rsp_src_data[63].DATAIN +rsp_sink_data[64] => rsp_src_data[64].DATAIN +rsp_sink_data[65] => rsp_src_data[65].DATAIN +rsp_sink_data[66] => rsp_src_data[66].DATAIN +rsp_sink_data[67] => rsp_src_data[67].DATAIN +rsp_sink_data[68] => rsp_src_data[68].DATAIN +rsp_sink_data[69] => rsp_src_data[69].DATAIN +rsp_sink_data[70] => rsp_src_data[70].DATAIN +rsp_sink_data[71] => rsp_src_data[71].DATAIN +rsp_sink_data[72] => rsp_src_data[72].DATAIN +rsp_sink_data[73] => rsp_src_data[73].DATAIN +rsp_sink_data[74] => rsp_src_data[74].DATAIN +rsp_sink_data[75] => rsp_src_data[75].DATAIN +rsp_sink_data[76] => rsp_src_data[76].DATAIN +rsp_sink_data[77] => rsp_src_data[77].DATAIN +rsp_sink_data[78] => rsp_src_data[78].DATAIN +rsp_sink_data[79] => rsp_src_data[79].DATAIN +rsp_sink_data[80] => rsp_src_data[80].DATAIN +rsp_sink_data[81] => rsp_src_data[81].DATAIN +rsp_sink_data[82] => rsp_src_data[82].DATAIN +rsp_sink_data[83] => rsp_src_data[83].DATAIN +rsp_sink_data[84] => rsp_src_data[84].DATAIN +rsp_sink_data[85] => rsp_src_data[85].DATAIN +rsp_sink_data[86] => rsp_src_data[86].DATAIN +rsp_sink_data[87] => rsp_src_data[87].DATAIN +rsp_sink_data[88] => rsp_src_data[88].DATAIN +rsp_sink_data[89] => rsp_src_data[89].DATAIN +rsp_sink_data[90] => rsp_src_data[90].DATAIN +rsp_sink_data[91] => rsp_src_data[91].DATAIN +rsp_sink_data[92] => rsp_src_data[92].DATAIN +rsp_sink_data[93] => rsp_src_data[93].DATAIN +rsp_sink_data[94] => rsp_src_data[94].DATAIN +rsp_sink_data[95] => rsp_src_data[95].DATAIN +rsp_sink_data[96] => rsp_src_data[96].DATAIN +rsp_sink_data[97] => rsp_src_data[97].DATAIN +rsp_sink_data[98] => rsp_src_data[98].DATAIN +rsp_sink_data[99] => rsp_src_data[99].DATAIN +rsp_sink_data[100] => rsp_src_data[100].DATAIN +rsp_sink_channel[0] => rsp_src_channel[0].DATAIN +rsp_sink_channel[1] => rsp_src_channel[1].DATAIN +rsp_sink_channel[2] => rsp_src_channel[2].DATAIN +rsp_sink_channel[3] => rsp_src_channel[3].DATAIN +rsp_sink_channel[4] => rsp_src_channel[4].DATAIN +rsp_sink_channel[5] => rsp_src_channel[5].DATAIN +rsp_sink_channel[6] => rsp_src_channel[6].DATAIN +rsp_sink_channel[7] => rsp_src_channel[7].DATAIN +rsp_sink_channel[8] => rsp_src_channel[8].DATAIN +rsp_sink_channel[9] => rsp_src_channel[9].DATAIN +rsp_sink_channel[10] => rsp_src_channel[10].DATAIN +rsp_sink_startofpacket => rsp_src_startofpacket.DATAIN +rsp_sink_endofpacket => response_accepted.IN1 +rsp_sink_endofpacket => rsp_src_endofpacket.DATAIN +rsp_sink_ready <= rsp_src_ready.DB_MAX_OUTPUT_PORT_TYPE +rsp_src_valid <= rsp_sink_valid.DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[0] <= rsp_sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[1] <= rsp_sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[2] <= rsp_sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[3] <= rsp_sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[4] <= rsp_sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[5] <= rsp_sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[6] <= rsp_sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[7] <= rsp_sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[8] <= rsp_sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[9] <= rsp_sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[10] <= rsp_sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[11] <= rsp_sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[12] <= rsp_sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[13] <= rsp_sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[14] <= rsp_sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[15] <= rsp_sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[16] <= rsp_sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[17] <= rsp_sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[18] <= rsp_sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[19] <= rsp_sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[20] <= rsp_sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[21] <= rsp_sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[22] <= rsp_sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[23] <= rsp_sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[24] <= rsp_sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[25] <= rsp_sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[26] <= rsp_sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[27] <= rsp_sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[28] <= rsp_sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[29] <= rsp_sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[30] <= rsp_sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[31] <= rsp_sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[32] <= rsp_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[33] <= rsp_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[34] <= rsp_sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[35] <= rsp_sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[36] <= rsp_sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[37] <= rsp_sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[38] <= rsp_sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[39] <= rsp_sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[40] <= rsp_sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[41] <= rsp_sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[42] <= rsp_sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[43] <= rsp_sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[44] <= rsp_sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[45] <= rsp_sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[46] <= rsp_sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[47] <= rsp_sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[48] <= rsp_sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[49] <= rsp_sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[50] <= rsp_sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[51] <= rsp_sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[52] <= rsp_sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[53] <= rsp_sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[54] <= rsp_sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[55] <= rsp_sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[56] <= rsp_sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[57] <= rsp_sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[58] <= rsp_sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[59] <= rsp_sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[60] <= rsp_sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[61] <= rsp_sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[62] <= rsp_sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[63] <= rsp_sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[64] <= rsp_sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[65] <= rsp_sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[66] <= rsp_sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[67] <= rsp_sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[68] <= rsp_sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[69] <= rsp_sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[70] <= rsp_sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[71] <= rsp_sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[72] <= rsp_sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[73] <= rsp_sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[74] <= rsp_sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[75] <= rsp_sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[76] <= rsp_sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[77] <= rsp_sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[78] <= rsp_sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[79] <= rsp_sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[80] <= rsp_sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[81] <= rsp_sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[82] <= rsp_sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[83] <= rsp_sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[84] <= rsp_sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[85] <= rsp_sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[86] <= rsp_sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[87] <= rsp_sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[88] <= rsp_sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[89] <= rsp_sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[90] <= rsp_sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[91] <= rsp_sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[92] <= rsp_sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[93] <= rsp_sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[94] <= rsp_sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[95] <= rsp_sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[96] <= rsp_sink_data[96].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[97] <= rsp_sink_data[97].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[98] <= rsp_sink_data[98].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[99] <= rsp_sink_data[99].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[100] <= rsp_sink_data[100].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_channel[0] <= rsp_sink_channel[0].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_channel[1] <= rsp_sink_channel[1].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_channel[2] <= rsp_sink_channel[2].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_channel[3] <= rsp_sink_channel[3].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_channel[4] <= rsp_sink_channel[4].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_channel[5] <= rsp_sink_channel[5].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_channel[6] <= rsp_sink_channel[6].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_channel[7] <= rsp_sink_channel[7].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_channel[8] <= rsp_sink_channel[8].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_channel[9] <= rsp_sink_channel[9].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_channel[10] <= rsp_sink_channel[10].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_startofpacket <= rsp_sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +rsp_src_endofpacket <= rsp_sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +rsp_src_ready => response_accepted.IN1 +rsp_src_ready => rsp_sink_ready.DATAIN + + +|de0_nano_system|system:inst_cpu|altera_merlin_traffic_limiter:limiter_001 +clk => has_pending_responses.CLK +clk => pending_response_count[0].CLK +clk => pending_response_count[1].CLK +clk => pending_response_count[2].CLK +clk => pending_response_count[3].CLK +clk => last_channel[0].CLK +clk => last_channel[1].CLK +clk => last_channel[2].CLK +clk => last_channel[3].CLK +clk => last_channel[4].CLK +clk => last_channel[5].CLK +clk => last_channel[6].CLK +clk => last_channel[7].CLK +clk => last_channel[8].CLK +clk => last_channel[9].CLK +clk => last_channel[10].CLK +clk => last_dest_id[0].CLK +clk => last_dest_id[1].CLK +clk => last_dest_id[2].CLK +clk => last_dest_id[3].CLK +reset => has_pending_responses.ACLR +reset => pending_response_count[0].ACLR +reset => pending_response_count[1].ACLR +reset => pending_response_count[2].ACLR +reset => pending_response_count[3].ACLR +reset => last_channel[0].ACLR +reset => last_channel[1].ACLR +reset => last_channel[2].ACLR +reset => last_channel[3].ACLR +reset => last_channel[4].ACLR +reset => last_channel[5].ACLR +reset => last_channel[6].ACLR +reset => last_channel[7].ACLR +reset => last_channel[8].ACLR +reset => last_channel[9].ACLR +reset => last_channel[10].ACLR +reset => last_dest_id[0].ACLR +reset => last_dest_id[1].ACLR +reset => last_dest_id[2].ACLR +reset => last_dest_id[3].ACLR +cmd_sink_valid => internal_valid.DATAA +cmd_sink_valid => cmd_src_valid.IN0 +cmd_sink_valid => cmd_src_valid.IN0 +cmd_sink_valid => cmd_src_valid.IN0 +cmd_sink_valid => cmd_src_valid.IN0 +cmd_sink_valid => cmd_src_valid.IN0 +cmd_sink_valid => cmd_src_valid.IN0 +cmd_sink_valid => cmd_src_valid.IN0 +cmd_sink_valid => cmd_src_valid.IN0 +cmd_sink_valid => cmd_src_valid.IN0 +cmd_sink_valid => cmd_src_valid.IN0 +cmd_sink_valid => cmd_src_valid.IN0 +cmd_sink_valid => save_dest_id.IN1 +cmd_sink_data[0] => cmd_src_data[0].DATAIN +cmd_sink_data[1] => cmd_src_data[1].DATAIN +cmd_sink_data[2] => cmd_src_data[2].DATAIN +cmd_sink_data[3] => cmd_src_data[3].DATAIN +cmd_sink_data[4] => cmd_src_data[4].DATAIN +cmd_sink_data[5] => cmd_src_data[5].DATAIN +cmd_sink_data[6] => cmd_src_data[6].DATAIN +cmd_sink_data[7] => cmd_src_data[7].DATAIN +cmd_sink_data[8] => cmd_src_data[8].DATAIN +cmd_sink_data[9] => cmd_src_data[9].DATAIN +cmd_sink_data[10] => cmd_src_data[10].DATAIN +cmd_sink_data[11] => cmd_src_data[11].DATAIN +cmd_sink_data[12] => cmd_src_data[12].DATAIN +cmd_sink_data[13] => cmd_src_data[13].DATAIN +cmd_sink_data[14] => cmd_src_data[14].DATAIN +cmd_sink_data[15] => cmd_src_data[15].DATAIN +cmd_sink_data[16] => cmd_src_data[16].DATAIN +cmd_sink_data[17] => cmd_src_data[17].DATAIN +cmd_sink_data[18] => cmd_src_data[18].DATAIN +cmd_sink_data[19] => cmd_src_data[19].DATAIN +cmd_sink_data[20] => cmd_src_data[20].DATAIN +cmd_sink_data[21] => cmd_src_data[21].DATAIN +cmd_sink_data[22] => cmd_src_data[22].DATAIN +cmd_sink_data[23] => cmd_src_data[23].DATAIN +cmd_sink_data[24] => cmd_src_data[24].DATAIN +cmd_sink_data[25] => cmd_src_data[25].DATAIN +cmd_sink_data[26] => cmd_src_data[26].DATAIN +cmd_sink_data[27] => cmd_src_data[27].DATAIN +cmd_sink_data[28] => cmd_src_data[28].DATAIN +cmd_sink_data[29] => cmd_src_data[29].DATAIN +cmd_sink_data[30] => cmd_src_data[30].DATAIN +cmd_sink_data[31] => cmd_src_data[31].DATAIN +cmd_sink_data[32] => cmd_src_data[32].DATAIN +cmd_sink_data[33] => cmd_src_data[33].DATAIN +cmd_sink_data[34] => cmd_src_data[34].DATAIN +cmd_sink_data[35] => cmd_src_data[35].DATAIN +cmd_sink_data[36] => cmd_src_data[36].DATAIN +cmd_sink_data[37] => cmd_src_data[37].DATAIN +cmd_sink_data[38] => cmd_src_data[38].DATAIN +cmd_sink_data[39] => cmd_src_data[39].DATAIN +cmd_sink_data[40] => cmd_src_data[40].DATAIN +cmd_sink_data[41] => cmd_src_data[41].DATAIN +cmd_sink_data[42] => cmd_src_data[42].DATAIN +cmd_sink_data[43] => cmd_src_data[43].DATAIN +cmd_sink_data[44] => cmd_src_data[44].DATAIN +cmd_sink_data[45] => cmd_src_data[45].DATAIN +cmd_sink_data[46] => cmd_src_data[46].DATAIN +cmd_sink_data[47] => cmd_src_data[47].DATAIN +cmd_sink_data[48] => cmd_src_data[48].DATAIN +cmd_sink_data[49] => cmd_src_data[49].DATAIN +cmd_sink_data[50] => cmd_src_data[50].DATAIN +cmd_sink_data[51] => cmd_src_data[51].DATAIN +cmd_sink_data[52] => cmd_src_data[52].DATAIN +cmd_sink_data[53] => cmd_src_data[53].DATAIN +cmd_sink_data[54] => cmd_src_data[54].DATAIN +cmd_sink_data[55] => cmd_src_data[55].DATAIN +cmd_sink_data[56] => cmd_src_data[56].DATAIN +cmd_sink_data[57] => cmd_src_data[57].DATAIN +cmd_sink_data[58] => cmd_src_data[58].DATAIN +cmd_sink_data[59] => cmd_src_data[59].DATAIN +cmd_sink_data[60] => cmd_src_data[60].DATAIN +cmd_sink_data[61] => cmd_src_data[61].DATAIN +cmd_sink_data[62] => cmd_src_data[62].DATAIN +cmd_sink_data[63] => cmd_src_data[63].DATAIN +cmd_sink_data[63] => save_dest_id.IN1 +cmd_sink_data[63] => nonposted_cmd_accepted.IN1 +cmd_sink_data[63] => suppress.IN1 +cmd_sink_data[64] => cmd_src_data[64].DATAIN +cmd_sink_data[65] => cmd_src_data[65].DATAIN +cmd_sink_data[66] => cmd_src_data[66].DATAIN +cmd_sink_data[67] => cmd_src_data[67].DATAIN +cmd_sink_data[68] => cmd_src_data[68].DATAIN +cmd_sink_data[69] => cmd_src_data[69].DATAIN +cmd_sink_data[70] => cmd_src_data[70].DATAIN +cmd_sink_data[71] => cmd_src_data[71].DATAIN +cmd_sink_data[72] => cmd_src_data[72].DATAIN +cmd_sink_data[73] => cmd_src_data[73].DATAIN +cmd_sink_data[74] => cmd_src_data[74].DATAIN +cmd_sink_data[75] => cmd_src_data[75].DATAIN +cmd_sink_data[76] => cmd_src_data[76].DATAIN +cmd_sink_data[77] => cmd_src_data[77].DATAIN +cmd_sink_data[78] => cmd_src_data[78].DATAIN +cmd_sink_data[79] => cmd_src_data[79].DATAIN +cmd_sink_data[80] => cmd_src_data[80].DATAIN +cmd_sink_data[81] => cmd_src_data[81].DATAIN +cmd_sink_data[82] => cmd_src_data[82].DATAIN +cmd_sink_data[83] => cmd_src_data[83].DATAIN +cmd_sink_data[84] => cmd_src_data[84].DATAIN +cmd_sink_data[85] => cmd_src_data[85].DATAIN +cmd_sink_data[86] => cmd_src_data[86].DATAIN +cmd_sink_data[87] => Equal0.IN3 +cmd_sink_data[87] => cmd_src_data[87].DATAIN +cmd_sink_data[87] => last_dest_id[0].DATAIN +cmd_sink_data[88] => Equal0.IN2 +cmd_sink_data[88] => cmd_src_data[88].DATAIN +cmd_sink_data[88] => last_dest_id[1].DATAIN +cmd_sink_data[89] => Equal0.IN1 +cmd_sink_data[89] => cmd_src_data[89].DATAIN +cmd_sink_data[89] => last_dest_id[2].DATAIN +cmd_sink_data[90] => Equal0.IN0 +cmd_sink_data[90] => cmd_src_data[90].DATAIN +cmd_sink_data[90] => last_dest_id[3].DATAIN +cmd_sink_data[91] => cmd_src_data[91].DATAIN +cmd_sink_data[92] => cmd_src_data[92].DATAIN +cmd_sink_data[93] => cmd_src_data[93].DATAIN +cmd_sink_data[94] => cmd_src_data[94].DATAIN +cmd_sink_data[95] => cmd_src_data[95].DATAIN +cmd_sink_data[96] => cmd_src_data[96].DATAIN +cmd_sink_data[97] => cmd_src_data[97].DATAIN +cmd_sink_data[98] => cmd_src_data[98].DATAIN +cmd_sink_data[99] => cmd_src_data[99].DATAIN +cmd_sink_data[100] => cmd_src_data[100].DATAIN +cmd_sink_channel[0] => cmd_src_valid.IN1 +cmd_sink_channel[0] => cmd_src_channel[0].DATAIN +cmd_sink_channel[0] => last_channel[0].DATAIN +cmd_sink_channel[1] => cmd_src_valid.IN1 +cmd_sink_channel[1] => cmd_src_channel[1].DATAIN +cmd_sink_channel[1] => last_channel[1].DATAIN +cmd_sink_channel[2] => cmd_src_valid.IN1 +cmd_sink_channel[2] => cmd_src_channel[2].DATAIN +cmd_sink_channel[2] => last_channel[2].DATAIN +cmd_sink_channel[3] => cmd_src_valid.IN1 +cmd_sink_channel[3] => cmd_src_channel[3].DATAIN +cmd_sink_channel[3] => last_channel[3].DATAIN +cmd_sink_channel[4] => cmd_src_valid.IN1 +cmd_sink_channel[4] => cmd_src_channel[4].DATAIN +cmd_sink_channel[4] => last_channel[4].DATAIN +cmd_sink_channel[5] => cmd_src_valid.IN1 +cmd_sink_channel[5] => cmd_src_channel[5].DATAIN +cmd_sink_channel[5] => last_channel[5].DATAIN +cmd_sink_channel[6] => cmd_src_valid.IN1 +cmd_sink_channel[6] => cmd_src_channel[6].DATAIN +cmd_sink_channel[6] => last_channel[6].DATAIN +cmd_sink_channel[7] => cmd_src_valid.IN1 +cmd_sink_channel[7] => cmd_src_channel[7].DATAIN +cmd_sink_channel[7] => last_channel[7].DATAIN +cmd_sink_channel[8] => cmd_src_valid.IN1 +cmd_sink_channel[8] => cmd_src_channel[8].DATAIN +cmd_sink_channel[8] => last_channel[8].DATAIN +cmd_sink_channel[9] => cmd_src_valid.IN1 +cmd_sink_channel[9] => cmd_src_channel[9].DATAIN +cmd_sink_channel[9] => last_channel[9].DATAIN +cmd_sink_channel[10] => cmd_src_valid.IN1 +cmd_sink_channel[10] => cmd_src_channel[10].DATAIN +cmd_sink_channel[10] => last_channel[10].DATAIN +cmd_sink_startofpacket => cmd_src_startofpacket.DATAIN +cmd_sink_endofpacket => nonposted_cmd_accepted.IN0 +cmd_sink_endofpacket => cmd_src_endofpacket.DATAIN +cmd_sink_ready <= stage2_ready.DB_MAX_OUTPUT_PORT_TYPE +cmd_src_valid[0] <= cmd_src_valid.DB_MAX_OUTPUT_PORT_TYPE +cmd_src_valid[1] <= cmd_src_valid.DB_MAX_OUTPUT_PORT_TYPE +cmd_src_valid[2] <= cmd_src_valid.DB_MAX_OUTPUT_PORT_TYPE +cmd_src_valid[3] <= cmd_src_valid.DB_MAX_OUTPUT_PORT_TYPE +cmd_src_valid[4] <= cmd_src_valid.DB_MAX_OUTPUT_PORT_TYPE +cmd_src_valid[5] <= cmd_src_valid.DB_MAX_OUTPUT_PORT_TYPE +cmd_src_valid[6] <= cmd_src_valid.DB_MAX_OUTPUT_PORT_TYPE +cmd_src_valid[7] <= cmd_src_valid.DB_MAX_OUTPUT_PORT_TYPE +cmd_src_valid[8] <= cmd_src_valid.DB_MAX_OUTPUT_PORT_TYPE +cmd_src_valid[9] <= cmd_src_valid.DB_MAX_OUTPUT_PORT_TYPE +cmd_src_valid[10] <= cmd_src_valid.DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[0] <= cmd_sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[1] <= cmd_sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[2] <= cmd_sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[3] <= cmd_sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[4] <= cmd_sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[5] <= cmd_sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[6] <= cmd_sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[7] <= cmd_sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[8] <= cmd_sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[9] <= cmd_sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[10] <= cmd_sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[11] <= cmd_sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[12] <= cmd_sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[13] <= cmd_sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[14] <= cmd_sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[15] <= cmd_sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[16] <= cmd_sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[17] <= cmd_sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[18] <= cmd_sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[19] <= cmd_sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[20] <= cmd_sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[21] <= cmd_sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[22] <= cmd_sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[23] <= cmd_sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[24] <= cmd_sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[25] <= cmd_sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[26] <= cmd_sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[27] <= cmd_sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[28] <= cmd_sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[29] <= cmd_sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[30] <= cmd_sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[31] <= cmd_sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[32] <= cmd_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[33] <= cmd_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[34] <= cmd_sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[35] <= cmd_sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[36] <= cmd_sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[37] <= cmd_sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[38] <= cmd_sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[39] <= cmd_sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[40] <= cmd_sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[41] <= cmd_sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[42] <= cmd_sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[43] <= cmd_sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[44] <= cmd_sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[45] <= cmd_sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[46] <= cmd_sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[47] <= cmd_sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[48] <= cmd_sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[49] <= cmd_sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[50] <= cmd_sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[51] <= cmd_sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[52] <= cmd_sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[53] <= cmd_sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[54] <= cmd_sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[55] <= cmd_sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[56] <= cmd_sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[57] <= cmd_sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[58] <= cmd_sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[59] <= cmd_sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[60] <= cmd_sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[61] <= cmd_sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[62] <= cmd_sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[63] <= cmd_sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[64] <= cmd_sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[65] <= cmd_sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[66] <= cmd_sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[67] <= cmd_sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[68] <= cmd_sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[69] <= cmd_sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[70] <= cmd_sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[71] <= cmd_sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[72] <= cmd_sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[73] <= cmd_sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[74] <= cmd_sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[75] <= cmd_sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[76] <= cmd_sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[77] <= cmd_sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[78] <= cmd_sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[79] <= cmd_sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[80] <= cmd_sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[81] <= cmd_sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[82] <= cmd_sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[83] <= cmd_sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[84] <= cmd_sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[85] <= cmd_sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[86] <= cmd_sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[87] <= cmd_sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[88] <= cmd_sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[89] <= cmd_sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[90] <= cmd_sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[91] <= cmd_sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[92] <= cmd_sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[93] <= cmd_sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[94] <= cmd_sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[95] <= cmd_sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[96] <= cmd_sink_data[96].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[97] <= cmd_sink_data[97].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[98] <= cmd_sink_data[98].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[99] <= cmd_sink_data[99].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_data[100] <= cmd_sink_data[100].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_channel[0] <= cmd_sink_channel[0].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_channel[1] <= cmd_sink_channel[1].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_channel[2] <= cmd_sink_channel[2].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_channel[3] <= cmd_sink_channel[3].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_channel[4] <= cmd_sink_channel[4].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_channel[5] <= cmd_sink_channel[5].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_channel[6] <= cmd_sink_channel[6].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_channel[7] <= cmd_sink_channel[7].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_channel[8] <= cmd_sink_channel[8].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_channel[9] <= cmd_sink_channel[9].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_channel[10] <= cmd_sink_channel[10].DB_MAX_OUTPUT_PORT_TYPE +cmd_src_startofpacket <= cmd_sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +cmd_src_endofpacket <= cmd_sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +cmd_src_ready => nonposted_cmd_accepted.IN1 +cmd_src_ready => stage2_ready.DATAA +rsp_sink_valid => response_accepted.IN0 +rsp_sink_valid => rsp_src_valid.DATAIN +rsp_sink_data[0] => rsp_src_data[0].DATAIN +rsp_sink_data[1] => rsp_src_data[1].DATAIN +rsp_sink_data[2] => rsp_src_data[2].DATAIN +rsp_sink_data[3] => rsp_src_data[3].DATAIN +rsp_sink_data[4] => rsp_src_data[4].DATAIN +rsp_sink_data[5] => rsp_src_data[5].DATAIN +rsp_sink_data[6] => rsp_src_data[6].DATAIN +rsp_sink_data[7] => rsp_src_data[7].DATAIN +rsp_sink_data[8] => rsp_src_data[8].DATAIN +rsp_sink_data[9] => rsp_src_data[9].DATAIN +rsp_sink_data[10] => rsp_src_data[10].DATAIN +rsp_sink_data[11] => rsp_src_data[11].DATAIN +rsp_sink_data[12] => rsp_src_data[12].DATAIN +rsp_sink_data[13] => rsp_src_data[13].DATAIN +rsp_sink_data[14] => rsp_src_data[14].DATAIN +rsp_sink_data[15] => rsp_src_data[15].DATAIN +rsp_sink_data[16] => rsp_src_data[16].DATAIN +rsp_sink_data[17] => rsp_src_data[17].DATAIN +rsp_sink_data[18] => rsp_src_data[18].DATAIN +rsp_sink_data[19] => rsp_src_data[19].DATAIN +rsp_sink_data[20] => rsp_src_data[20].DATAIN +rsp_sink_data[21] => rsp_src_data[21].DATAIN +rsp_sink_data[22] => rsp_src_data[22].DATAIN +rsp_sink_data[23] => rsp_src_data[23].DATAIN +rsp_sink_data[24] => rsp_src_data[24].DATAIN +rsp_sink_data[25] => rsp_src_data[25].DATAIN +rsp_sink_data[26] => rsp_src_data[26].DATAIN +rsp_sink_data[27] => rsp_src_data[27].DATAIN +rsp_sink_data[28] => rsp_src_data[28].DATAIN +rsp_sink_data[29] => rsp_src_data[29].DATAIN +rsp_sink_data[30] => rsp_src_data[30].DATAIN +rsp_sink_data[31] => rsp_src_data[31].DATAIN +rsp_sink_data[32] => rsp_src_data[32].DATAIN +rsp_sink_data[33] => rsp_src_data[33].DATAIN +rsp_sink_data[34] => rsp_src_data[34].DATAIN +rsp_sink_data[35] => rsp_src_data[35].DATAIN +rsp_sink_data[36] => rsp_src_data[36].DATAIN +rsp_sink_data[37] => rsp_src_data[37].DATAIN +rsp_sink_data[38] => rsp_src_data[38].DATAIN +rsp_sink_data[39] => rsp_src_data[39].DATAIN +rsp_sink_data[40] => rsp_src_data[40].DATAIN +rsp_sink_data[41] => rsp_src_data[41].DATAIN +rsp_sink_data[42] => rsp_src_data[42].DATAIN +rsp_sink_data[43] => rsp_src_data[43].DATAIN +rsp_sink_data[44] => rsp_src_data[44].DATAIN +rsp_sink_data[45] => rsp_src_data[45].DATAIN +rsp_sink_data[46] => rsp_src_data[46].DATAIN +rsp_sink_data[47] => rsp_src_data[47].DATAIN +rsp_sink_data[48] => rsp_src_data[48].DATAIN +rsp_sink_data[49] => rsp_src_data[49].DATAIN +rsp_sink_data[50] => rsp_src_data[50].DATAIN +rsp_sink_data[51] => rsp_src_data[51].DATAIN +rsp_sink_data[52] => rsp_src_data[52].DATAIN +rsp_sink_data[53] => rsp_src_data[53].DATAIN +rsp_sink_data[54] => rsp_src_data[54].DATAIN +rsp_sink_data[55] => rsp_src_data[55].DATAIN +rsp_sink_data[56] => rsp_src_data[56].DATAIN +rsp_sink_data[57] => rsp_src_data[57].DATAIN +rsp_sink_data[58] => rsp_src_data[58].DATAIN +rsp_sink_data[59] => rsp_src_data[59].DATAIN +rsp_sink_data[60] => rsp_src_data[60].DATAIN +rsp_sink_data[61] => rsp_src_data[61].DATAIN +rsp_sink_data[62] => rsp_src_data[62].DATAIN +rsp_sink_data[63] => rsp_src_data[63].DATAIN +rsp_sink_data[64] => rsp_src_data[64].DATAIN +rsp_sink_data[65] => rsp_src_data[65].DATAIN +rsp_sink_data[66] => rsp_src_data[66].DATAIN +rsp_sink_data[67] => rsp_src_data[67].DATAIN +rsp_sink_data[68] => rsp_src_data[68].DATAIN +rsp_sink_data[69] => rsp_src_data[69].DATAIN +rsp_sink_data[70] => rsp_src_data[70].DATAIN +rsp_sink_data[71] => rsp_src_data[71].DATAIN +rsp_sink_data[72] => rsp_src_data[72].DATAIN +rsp_sink_data[73] => rsp_src_data[73].DATAIN +rsp_sink_data[74] => rsp_src_data[74].DATAIN +rsp_sink_data[75] => rsp_src_data[75].DATAIN +rsp_sink_data[76] => rsp_src_data[76].DATAIN +rsp_sink_data[77] => rsp_src_data[77].DATAIN +rsp_sink_data[78] => rsp_src_data[78].DATAIN +rsp_sink_data[79] => rsp_src_data[79].DATAIN +rsp_sink_data[80] => rsp_src_data[80].DATAIN +rsp_sink_data[81] => rsp_src_data[81].DATAIN +rsp_sink_data[82] => rsp_src_data[82].DATAIN +rsp_sink_data[83] => rsp_src_data[83].DATAIN +rsp_sink_data[84] => rsp_src_data[84].DATAIN +rsp_sink_data[85] => rsp_src_data[85].DATAIN +rsp_sink_data[86] => rsp_src_data[86].DATAIN +rsp_sink_data[87] => rsp_src_data[87].DATAIN +rsp_sink_data[88] => rsp_src_data[88].DATAIN +rsp_sink_data[89] => rsp_src_data[89].DATAIN +rsp_sink_data[90] => rsp_src_data[90].DATAIN +rsp_sink_data[91] => rsp_src_data[91].DATAIN +rsp_sink_data[92] => rsp_src_data[92].DATAIN +rsp_sink_data[93] => rsp_src_data[93].DATAIN +rsp_sink_data[94] => rsp_src_data[94].DATAIN +rsp_sink_data[95] => rsp_src_data[95].DATAIN +rsp_sink_data[96] => rsp_src_data[96].DATAIN +rsp_sink_data[97] => rsp_src_data[97].DATAIN +rsp_sink_data[98] => rsp_src_data[98].DATAIN +rsp_sink_data[99] => rsp_src_data[99].DATAIN +rsp_sink_data[100] => rsp_src_data[100].DATAIN +rsp_sink_channel[0] => rsp_src_channel[0].DATAIN +rsp_sink_channel[1] => rsp_src_channel[1].DATAIN +rsp_sink_channel[2] => rsp_src_channel[2].DATAIN +rsp_sink_channel[3] => rsp_src_channel[3].DATAIN +rsp_sink_channel[4] => rsp_src_channel[4].DATAIN +rsp_sink_channel[5] => rsp_src_channel[5].DATAIN +rsp_sink_channel[6] => rsp_src_channel[6].DATAIN +rsp_sink_channel[7] => rsp_src_channel[7].DATAIN +rsp_sink_channel[8] => rsp_src_channel[8].DATAIN +rsp_sink_channel[9] => rsp_src_channel[9].DATAIN +rsp_sink_channel[10] => rsp_src_channel[10].DATAIN +rsp_sink_startofpacket => rsp_src_startofpacket.DATAIN +rsp_sink_endofpacket => response_accepted.IN1 +rsp_sink_endofpacket => rsp_src_endofpacket.DATAIN +rsp_sink_ready <= rsp_src_ready.DB_MAX_OUTPUT_PORT_TYPE +rsp_src_valid <= rsp_sink_valid.DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[0] <= rsp_sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[1] <= rsp_sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[2] <= rsp_sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[3] <= rsp_sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[4] <= rsp_sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[5] <= rsp_sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[6] <= rsp_sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[7] <= rsp_sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[8] <= rsp_sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[9] <= rsp_sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[10] <= rsp_sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[11] <= rsp_sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[12] <= rsp_sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[13] <= rsp_sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[14] <= rsp_sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[15] <= rsp_sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[16] <= rsp_sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[17] <= rsp_sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[18] <= rsp_sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[19] <= rsp_sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[20] <= rsp_sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[21] <= rsp_sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[22] <= rsp_sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[23] <= rsp_sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[24] <= rsp_sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[25] <= rsp_sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[26] <= rsp_sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[27] <= rsp_sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[28] <= rsp_sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[29] <= rsp_sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[30] <= rsp_sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[31] <= rsp_sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[32] <= rsp_sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[33] <= rsp_sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[34] <= rsp_sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[35] <= rsp_sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[36] <= rsp_sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[37] <= rsp_sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[38] <= rsp_sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[39] <= rsp_sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[40] <= rsp_sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[41] <= rsp_sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[42] <= rsp_sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[43] <= rsp_sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[44] <= rsp_sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[45] <= rsp_sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[46] <= rsp_sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[47] <= rsp_sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[48] <= rsp_sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[49] <= rsp_sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[50] <= rsp_sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[51] <= rsp_sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[52] <= rsp_sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[53] <= rsp_sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[54] <= rsp_sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[55] <= rsp_sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[56] <= rsp_sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[57] <= rsp_sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[58] <= rsp_sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[59] <= rsp_sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[60] <= rsp_sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[61] <= rsp_sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[62] <= rsp_sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[63] <= rsp_sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[64] <= rsp_sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[65] <= rsp_sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[66] <= rsp_sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[67] <= rsp_sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[68] <= rsp_sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[69] <= rsp_sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[70] <= rsp_sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[71] <= rsp_sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[72] <= rsp_sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[73] <= rsp_sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[74] <= rsp_sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[75] <= rsp_sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[76] <= rsp_sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[77] <= rsp_sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[78] <= rsp_sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[79] <= rsp_sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[80] <= rsp_sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[81] <= rsp_sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[82] <= rsp_sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[83] <= rsp_sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[84] <= rsp_sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[85] <= rsp_sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[86] <= rsp_sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[87] <= rsp_sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[88] <= rsp_sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[89] <= rsp_sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[90] <= rsp_sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[91] <= rsp_sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[92] <= rsp_sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[93] <= rsp_sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[94] <= rsp_sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[95] <= rsp_sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[96] <= rsp_sink_data[96].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[97] <= rsp_sink_data[97].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[98] <= rsp_sink_data[98].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[99] <= rsp_sink_data[99].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_data[100] <= rsp_sink_data[100].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_channel[0] <= rsp_sink_channel[0].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_channel[1] <= rsp_sink_channel[1].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_channel[2] <= rsp_sink_channel[2].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_channel[3] <= rsp_sink_channel[3].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_channel[4] <= rsp_sink_channel[4].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_channel[5] <= rsp_sink_channel[5].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_channel[6] <= rsp_sink_channel[6].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_channel[7] <= rsp_sink_channel[7].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_channel[8] <= rsp_sink_channel[8].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_channel[9] <= rsp_sink_channel[9].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_channel[10] <= rsp_sink_channel[10].DB_MAX_OUTPUT_PORT_TYPE +rsp_src_startofpacket <= rsp_sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +rsp_src_endofpacket <= rsp_sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +rsp_src_ready => response_accepted.IN1 +rsp_src_ready => rsp_sink_ready.DATAIN + + +|de0_nano_system|system:inst_cpu|altera_merlin_burst_adapter:burst_adapter +clk => clk.IN1 +reset => reset.IN1 +sink0_valid => sink0_valid.IN1 +sink0_data[0] => sink0_data[0].IN1 +sink0_data[1] => sink0_data[1].IN1 +sink0_data[2] => sink0_data[2].IN1 +sink0_data[3] => sink0_data[3].IN1 +sink0_data[4] => sink0_data[4].IN1 +sink0_data[5] => sink0_data[5].IN1 +sink0_data[6] => sink0_data[6].IN1 +sink0_data[7] => sink0_data[7].IN1 +sink0_data[8] => sink0_data[8].IN1 +sink0_data[9] => sink0_data[9].IN1 +sink0_data[10] => sink0_data[10].IN1 +sink0_data[11] => sink0_data[11].IN1 +sink0_data[12] => sink0_data[12].IN1 +sink0_data[13] => sink0_data[13].IN1 +sink0_data[14] => sink0_data[14].IN1 +sink0_data[15] => sink0_data[15].IN1 +sink0_data[16] => sink0_data[16].IN1 +sink0_data[17] => sink0_data[17].IN1 +sink0_data[18] => sink0_data[18].IN1 +sink0_data[19] => sink0_data[19].IN1 +sink0_data[20] => sink0_data[20].IN1 +sink0_data[21] => sink0_data[21].IN1 +sink0_data[22] => sink0_data[22].IN1 +sink0_data[23] => sink0_data[23].IN1 +sink0_data[24] => sink0_data[24].IN1 +sink0_data[25] => sink0_data[25].IN1 +sink0_data[26] => sink0_data[26].IN1 +sink0_data[27] => sink0_data[27].IN1 +sink0_data[28] => sink0_data[28].IN1 +sink0_data[29] => sink0_data[29].IN1 +sink0_data[30] => sink0_data[30].IN1 +sink0_data[31] => sink0_data[31].IN1 +sink0_data[32] => sink0_data[32].IN1 +sink0_data[33] => sink0_data[33].IN1 +sink0_data[34] => sink0_data[34].IN1 +sink0_data[35] => sink0_data[35].IN1 +sink0_data[36] => sink0_data[36].IN1 +sink0_data[37] => sink0_data[37].IN1 +sink0_data[38] => sink0_data[38].IN1 +sink0_data[39] => sink0_data[39].IN1 +sink0_data[40] => sink0_data[40].IN1 +sink0_data[41] => sink0_data[41].IN1 +sink0_data[42] => sink0_data[42].IN1 +sink0_data[43] => sink0_data[43].IN1 +sink0_data[44] => sink0_data[44].IN1 +sink0_data[45] => sink0_data[45].IN1 +sink0_data[46] => sink0_data[46].IN1 +sink0_data[47] => sink0_data[47].IN1 +sink0_data[48] => sink0_data[48].IN1 +sink0_data[49] => sink0_data[49].IN1 +sink0_data[50] => sink0_data[50].IN1 +sink0_data[51] => sink0_data[51].IN1 +sink0_data[52] => sink0_data[52].IN1 +sink0_data[53] => sink0_data[53].IN1 +sink0_data[54] => sink0_data[54].IN1 +sink0_data[55] => sink0_data[55].IN1 +sink0_data[56] => sink0_data[56].IN1 +sink0_data[57] => sink0_data[57].IN1 +sink0_data[58] => sink0_data[58].IN1 +sink0_data[59] => sink0_data[59].IN1 +sink0_data[60] => sink0_data[60].IN1 +sink0_data[61] => sink0_data[61].IN1 +sink0_data[62] => sink0_data[62].IN1 +sink0_data[63] => sink0_data[63].IN1 +sink0_data[64] => sink0_data[64].IN1 +sink0_data[65] => sink0_data[65].IN1 +sink0_data[66] => sink0_data[66].IN1 +sink0_data[67] => sink0_data[67].IN1 +sink0_data[68] => sink0_data[68].IN1 +sink0_data[69] => sink0_data[69].IN1 +sink0_data[70] => sink0_data[70].IN1 +sink0_data[71] => sink0_data[71].IN1 +sink0_data[72] => sink0_data[72].IN1 +sink0_data[73] => sink0_data[73].IN1 +sink0_data[74] => sink0_data[74].IN1 +sink0_data[75] => sink0_data[75].IN1 +sink0_data[76] => sink0_data[76].IN1 +sink0_data[77] => sink0_data[77].IN1 +sink0_data[78] => sink0_data[78].IN1 +sink0_data[79] => sink0_data[79].IN1 +sink0_data[80] => sink0_data[80].IN1 +sink0_data[81] => sink0_data[81].IN1 +sink0_data[82] => sink0_data[82].IN1 +sink0_channel[0] => sink0_channel[0].IN1 +sink0_channel[1] => sink0_channel[1].IN1 +sink0_channel[2] => sink0_channel[2].IN1 +sink0_channel[3] => sink0_channel[3].IN1 +sink0_channel[4] => sink0_channel[4].IN1 +sink0_channel[5] => sink0_channel[5].IN1 +sink0_channel[6] => sink0_channel[6].IN1 +sink0_channel[7] => sink0_channel[7].IN1 +sink0_channel[8] => sink0_channel[8].IN1 +sink0_channel[9] => sink0_channel[9].IN1 +sink0_channel[10] => sink0_channel[10].IN1 +sink0_startofpacket => sink0_startofpacket.IN1 +sink0_endofpacket => sink0_endofpacket.IN1 +sink0_ready <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.sink0_ready +source0_valid <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_valid +source0_data[0] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_data +source0_data[1] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_data +source0_data[2] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_data +source0_data[3] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_data +source0_data[4] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_data +source0_data[5] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_data +source0_data[6] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_data +source0_data[7] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_data +source0_data[8] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_data +source0_data[9] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_data +source0_data[10] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_data +source0_data[11] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_data +source0_data[12] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_data +source0_data[13] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_data +source0_data[14] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_data +source0_data[15] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_data +source0_data[16] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_data +source0_data[17] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_data +source0_data[18] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_data +source0_data[19] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_data +source0_data[20] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_data +source0_data[21] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_data +source0_data[22] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_data +source0_data[23] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_data +source0_data[24] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_data +source0_data[25] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_data +source0_data[26] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_data +source0_data[27] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_data +source0_data[28] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_data +source0_data[29] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_data +source0_data[30] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_data +source0_data[31] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_data +source0_data[32] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_data +source0_data[33] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_data +source0_data[34] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_data +source0_data[35] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_data +source0_data[36] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_data +source0_data[37] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_data +source0_data[38] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_data +source0_data[39] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_data +source0_data[40] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_data +source0_data[41] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_data +source0_data[42] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_data +source0_data[43] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_data +source0_data[44] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_data +source0_data[45] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_data +source0_data[46] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_data +source0_data[47] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_data +source0_data[48] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_data +source0_data[49] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_data +source0_data[50] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_data +source0_data[51] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_data +source0_data[52] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_data +source0_data[53] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_data +source0_data[54] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_data +source0_data[55] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_data +source0_data[56] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_data +source0_data[57] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_data +source0_data[58] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_data +source0_data[59] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_data +source0_data[60] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_data +source0_data[61] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_data +source0_data[62] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_data +source0_data[63] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_data +source0_data[64] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_data +source0_data[65] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_data +source0_data[66] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_data +source0_data[67] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_data +source0_data[68] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_data +source0_data[69] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_data +source0_data[70] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_data +source0_data[71] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_data +source0_data[72] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_data +source0_data[73] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_data +source0_data[74] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_data +source0_data[75] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_data +source0_data[76] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_data +source0_data[77] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_data +source0_data[78] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_data +source0_data[79] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_data +source0_data[80] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_data +source0_data[81] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_data +source0_data[82] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_data +source0_channel[0] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_channel +source0_channel[1] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_channel +source0_channel[2] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_channel +source0_channel[3] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_channel +source0_channel[4] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_channel +source0_channel[5] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_channel +source0_channel[6] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_channel +source0_channel[7] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_channel +source0_channel[8] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_channel +source0_channel[9] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_channel +source0_channel[10] <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_channel +source0_startofpacket <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_startofpacket +source0_endofpacket <= altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba.source0_endofpacket +source0_ready => source0_ready.IN1 + + +|de0_nano_system|system:inst_cpu|altera_merlin_burst_adapter:burst_adapter|altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba +clk => ~NO_FANOUT~ +reset => ~NO_FANOUT~ +sink0_valid => source0_valid.DATAIN +sink0_data[0] => source0_data[0].DATAIN +sink0_data[1] => source0_data[1].DATAIN +sink0_data[2] => source0_data[2].DATAIN +sink0_data[3] => source0_data[3].DATAIN +sink0_data[4] => source0_data[4].DATAIN +sink0_data[5] => source0_data[5].DATAIN +sink0_data[6] => source0_data[6].DATAIN +sink0_data[7] => source0_data[7].DATAIN +sink0_data[8] => source0_data[8].DATAIN +sink0_data[9] => source0_data[9].DATAIN +sink0_data[10] => source0_data[10].DATAIN +sink0_data[11] => source0_data[11].DATAIN +sink0_data[12] => source0_data[12].DATAIN +sink0_data[13] => source0_data[13].DATAIN +sink0_data[14] => source0_data[14].DATAIN +sink0_data[15] => source0_data[15].DATAIN +sink0_data[16] => source0_data[16].DATAIN +sink0_data[17] => source0_data[17].DATAIN +sink0_data[18] => source0_data[18].DATAIN +sink0_data[19] => source0_data[19].DATAIN +sink0_data[20] => source0_data[20].DATAIN +sink0_data[21] => source0_data[21].DATAIN +sink0_data[22] => source0_data[22].DATAIN +sink0_data[23] => source0_data[23].DATAIN +sink0_data[24] => source0_data[24].DATAIN +sink0_data[25] => source0_data[25].DATAIN +sink0_data[26] => source0_data[26].DATAIN +sink0_data[27] => source0_data[27].DATAIN +sink0_data[28] => source0_data[28].DATAIN +sink0_data[29] => source0_data[29].DATAIN +sink0_data[30] => source0_data[30].DATAIN +sink0_data[31] => source0_data[31].DATAIN +sink0_data[32] => source0_data[32].DATAIN +sink0_data[33] => source0_data[33].DATAIN +sink0_data[34] => source0_data[34].DATAIN +sink0_data[35] => source0_data[35].DATAIN +sink0_data[36] => source0_data[36].DATAIN +sink0_data[37] => source0_data[37].DATAIN +sink0_data[38] => source0_data[38].DATAIN +sink0_data[39] => source0_data[39].DATAIN +sink0_data[40] => source0_data[40].DATAIN +sink0_data[41] => source0_data[41].DATAIN +sink0_data[42] => source0_data[42].DATAIN +sink0_data[43] => source0_data[43].DATAIN +sink0_data[44] => source0_data[44].DATAIN +sink0_data[45] => source0_data[45].DATAIN +sink0_data[46] => source0_data[46].DATAIN +sink0_data[47] => source0_data[47].DATAIN +sink0_data[48] => source0_data[48].DATAIN +sink0_data[49] => source0_data[49].DATAIN +sink0_data[50] => ~NO_FANOUT~ +sink0_data[51] => ~NO_FANOUT~ +sink0_data[52] => ~NO_FANOUT~ +sink0_data[53] => source0_data[53].DATAIN +sink0_data[54] => source0_data[54].DATAIN +sink0_data[55] => source0_data[55].DATAIN +sink0_data[56] => source0_data[56].DATAIN +sink0_data[57] => source0_data[57].DATAIN +sink0_data[58] => source0_data[58].DATAIN +sink0_data[59] => source0_data[59].DATAIN +sink0_data[60] => source0_data[60].DATAIN +sink0_data[61] => source0_data[61].DATAIN +sink0_data[62] => source0_data[62].DATAIN +sink0_data[63] => source0_data[63].DATAIN +sink0_data[64] => source0_data[64].DATAIN +sink0_data[65] => source0_data[65].DATAIN +sink0_data[66] => source0_data[66].DATAIN +sink0_data[67] => source0_data[67].DATAIN +sink0_data[68] => source0_data[68].DATAIN +sink0_data[69] => source0_data[69].DATAIN +sink0_data[70] => source0_data[70].DATAIN +sink0_data[71] => source0_data[71].DATAIN +sink0_data[72] => source0_data[72].DATAIN +sink0_data[73] => source0_data[73].DATAIN +sink0_data[74] => source0_data[74].DATAIN +sink0_data[75] => source0_data[75].DATAIN +sink0_data[76] => source0_data[76].DATAIN +sink0_data[77] => source0_data[77].DATAIN +sink0_data[78] => source0_data[78].DATAIN +sink0_data[79] => source0_data[79].DATAIN +sink0_data[80] => source0_data[80].DATAIN +sink0_data[81] => source0_data[81].DATAIN +sink0_data[82] => source0_data[82].DATAIN +sink0_channel[0] => source0_channel[0].DATAIN +sink0_channel[1] => source0_channel[1].DATAIN +sink0_channel[2] => source0_channel[2].DATAIN +sink0_channel[3] => source0_channel[3].DATAIN +sink0_channel[4] => source0_channel[4].DATAIN +sink0_channel[5] => source0_channel[5].DATAIN +sink0_channel[6] => source0_channel[6].DATAIN +sink0_channel[7] => source0_channel[7].DATAIN +sink0_channel[8] => source0_channel[8].DATAIN +sink0_channel[9] => source0_channel[9].DATAIN +sink0_channel[10] => source0_channel[10].DATAIN +sink0_startofpacket => source0_startofpacket.DATAIN +sink0_endofpacket => source0_endofpacket.DATAIN +sink0_ready <= source0_ready.DB_MAX_OUTPUT_PORT_TYPE +source0_valid <= sink0_valid.DB_MAX_OUTPUT_PORT_TYPE +source0_data[0] <= sink0_data[0].DB_MAX_OUTPUT_PORT_TYPE +source0_data[1] <= sink0_data[1].DB_MAX_OUTPUT_PORT_TYPE +source0_data[2] <= sink0_data[2].DB_MAX_OUTPUT_PORT_TYPE +source0_data[3] <= sink0_data[3].DB_MAX_OUTPUT_PORT_TYPE +source0_data[4] <= sink0_data[4].DB_MAX_OUTPUT_PORT_TYPE +source0_data[5] <= sink0_data[5].DB_MAX_OUTPUT_PORT_TYPE +source0_data[6] <= sink0_data[6].DB_MAX_OUTPUT_PORT_TYPE +source0_data[7] <= sink0_data[7].DB_MAX_OUTPUT_PORT_TYPE +source0_data[8] <= sink0_data[8].DB_MAX_OUTPUT_PORT_TYPE +source0_data[9] <= sink0_data[9].DB_MAX_OUTPUT_PORT_TYPE +source0_data[10] <= sink0_data[10].DB_MAX_OUTPUT_PORT_TYPE +source0_data[11] <= sink0_data[11].DB_MAX_OUTPUT_PORT_TYPE +source0_data[12] <= sink0_data[12].DB_MAX_OUTPUT_PORT_TYPE +source0_data[13] <= sink0_data[13].DB_MAX_OUTPUT_PORT_TYPE +source0_data[14] <= sink0_data[14].DB_MAX_OUTPUT_PORT_TYPE +source0_data[15] <= sink0_data[15].DB_MAX_OUTPUT_PORT_TYPE +source0_data[16] <= sink0_data[16].DB_MAX_OUTPUT_PORT_TYPE +source0_data[17] <= sink0_data[17].DB_MAX_OUTPUT_PORT_TYPE +source0_data[18] <= sink0_data[18].DB_MAX_OUTPUT_PORT_TYPE +source0_data[19] <= sink0_data[19].DB_MAX_OUTPUT_PORT_TYPE +source0_data[20] <= sink0_data[20].DB_MAX_OUTPUT_PORT_TYPE +source0_data[21] <= sink0_data[21].DB_MAX_OUTPUT_PORT_TYPE +source0_data[22] <= sink0_data[22].DB_MAX_OUTPUT_PORT_TYPE +source0_data[23] <= sink0_data[23].DB_MAX_OUTPUT_PORT_TYPE +source0_data[24] <= sink0_data[24].DB_MAX_OUTPUT_PORT_TYPE +source0_data[25] <= sink0_data[25].DB_MAX_OUTPUT_PORT_TYPE +source0_data[26] <= sink0_data[26].DB_MAX_OUTPUT_PORT_TYPE +source0_data[27] <= sink0_data[27].DB_MAX_OUTPUT_PORT_TYPE +source0_data[28] <= sink0_data[28].DB_MAX_OUTPUT_PORT_TYPE +source0_data[29] <= sink0_data[29].DB_MAX_OUTPUT_PORT_TYPE +source0_data[30] <= sink0_data[30].DB_MAX_OUTPUT_PORT_TYPE +source0_data[31] <= sink0_data[31].DB_MAX_OUTPUT_PORT_TYPE +source0_data[32] <= sink0_data[32].DB_MAX_OUTPUT_PORT_TYPE +source0_data[33] <= sink0_data[33].DB_MAX_OUTPUT_PORT_TYPE +source0_data[34] <= sink0_data[34].DB_MAX_OUTPUT_PORT_TYPE +source0_data[35] <= sink0_data[35].DB_MAX_OUTPUT_PORT_TYPE +source0_data[36] <= sink0_data[36].DB_MAX_OUTPUT_PORT_TYPE +source0_data[37] <= sink0_data[37].DB_MAX_OUTPUT_PORT_TYPE +source0_data[38] <= sink0_data[38].DB_MAX_OUTPUT_PORT_TYPE +source0_data[39] <= sink0_data[39].DB_MAX_OUTPUT_PORT_TYPE +source0_data[40] <= sink0_data[40].DB_MAX_OUTPUT_PORT_TYPE +source0_data[41] <= sink0_data[41].DB_MAX_OUTPUT_PORT_TYPE +source0_data[42] <= sink0_data[42].DB_MAX_OUTPUT_PORT_TYPE +source0_data[43] <= sink0_data[43].DB_MAX_OUTPUT_PORT_TYPE +source0_data[44] <= sink0_data[44].DB_MAX_OUTPUT_PORT_TYPE +source0_data[45] <= sink0_data[45].DB_MAX_OUTPUT_PORT_TYPE +source0_data[46] <= sink0_data[46].DB_MAX_OUTPUT_PORT_TYPE +source0_data[47] <= sink0_data[47].DB_MAX_OUTPUT_PORT_TYPE +source0_data[48] <= sink0_data[48].DB_MAX_OUTPUT_PORT_TYPE +source0_data[49] <= sink0_data[49].DB_MAX_OUTPUT_PORT_TYPE +source0_data[50] <= +source0_data[51] <= +source0_data[52] <= +source0_data[53] <= sink0_data[53].DB_MAX_OUTPUT_PORT_TYPE +source0_data[54] <= sink0_data[54].DB_MAX_OUTPUT_PORT_TYPE +source0_data[55] <= sink0_data[55].DB_MAX_OUTPUT_PORT_TYPE +source0_data[56] <= sink0_data[56].DB_MAX_OUTPUT_PORT_TYPE +source0_data[57] <= sink0_data[57].DB_MAX_OUTPUT_PORT_TYPE +source0_data[58] <= sink0_data[58].DB_MAX_OUTPUT_PORT_TYPE +source0_data[59] <= sink0_data[59].DB_MAX_OUTPUT_PORT_TYPE +source0_data[60] <= sink0_data[60].DB_MAX_OUTPUT_PORT_TYPE +source0_data[61] <= sink0_data[61].DB_MAX_OUTPUT_PORT_TYPE +source0_data[62] <= sink0_data[62].DB_MAX_OUTPUT_PORT_TYPE +source0_data[63] <= sink0_data[63].DB_MAX_OUTPUT_PORT_TYPE +source0_data[64] <= sink0_data[64].DB_MAX_OUTPUT_PORT_TYPE +source0_data[65] <= sink0_data[65].DB_MAX_OUTPUT_PORT_TYPE +source0_data[66] <= sink0_data[66].DB_MAX_OUTPUT_PORT_TYPE +source0_data[67] <= sink0_data[67].DB_MAX_OUTPUT_PORT_TYPE +source0_data[68] <= sink0_data[68].DB_MAX_OUTPUT_PORT_TYPE +source0_data[69] <= sink0_data[69].DB_MAX_OUTPUT_PORT_TYPE +source0_data[70] <= sink0_data[70].DB_MAX_OUTPUT_PORT_TYPE +source0_data[71] <= sink0_data[71].DB_MAX_OUTPUT_PORT_TYPE +source0_data[72] <= sink0_data[72].DB_MAX_OUTPUT_PORT_TYPE +source0_data[73] <= sink0_data[73].DB_MAX_OUTPUT_PORT_TYPE +source0_data[74] <= sink0_data[74].DB_MAX_OUTPUT_PORT_TYPE +source0_data[75] <= sink0_data[75].DB_MAX_OUTPUT_PORT_TYPE +source0_data[76] <= sink0_data[76].DB_MAX_OUTPUT_PORT_TYPE +source0_data[77] <= sink0_data[77].DB_MAX_OUTPUT_PORT_TYPE +source0_data[78] <= sink0_data[78].DB_MAX_OUTPUT_PORT_TYPE +source0_data[79] <= sink0_data[79].DB_MAX_OUTPUT_PORT_TYPE +source0_data[80] <= sink0_data[80].DB_MAX_OUTPUT_PORT_TYPE +source0_data[81] <= sink0_data[81].DB_MAX_OUTPUT_PORT_TYPE +source0_data[82] <= sink0_data[82].DB_MAX_OUTPUT_PORT_TYPE +source0_channel[0] <= sink0_channel[0].DB_MAX_OUTPUT_PORT_TYPE +source0_channel[1] <= sink0_channel[1].DB_MAX_OUTPUT_PORT_TYPE +source0_channel[2] <= sink0_channel[2].DB_MAX_OUTPUT_PORT_TYPE +source0_channel[3] <= sink0_channel[3].DB_MAX_OUTPUT_PORT_TYPE +source0_channel[4] <= sink0_channel[4].DB_MAX_OUTPUT_PORT_TYPE +source0_channel[5] <= sink0_channel[5].DB_MAX_OUTPUT_PORT_TYPE +source0_channel[6] <= sink0_channel[6].DB_MAX_OUTPUT_PORT_TYPE +source0_channel[7] <= sink0_channel[7].DB_MAX_OUTPUT_PORT_TYPE +source0_channel[8] <= sink0_channel[8].DB_MAX_OUTPUT_PORT_TYPE +source0_channel[9] <= sink0_channel[9].DB_MAX_OUTPUT_PORT_TYPE +source0_channel[10] <= sink0_channel[10].DB_MAX_OUTPUT_PORT_TYPE +source0_startofpacket <= sink0_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +source0_endofpacket <= sink0_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +source0_ready => sink0_ready.DATAIN + + +|de0_nano_system|system:inst_cpu|altera_reset_controller:rst_controller +reset_in0 => merged_reset.IN0 +reset_in1 => merged_reset.IN1 +reset_in2 => merged_reset.IN1 +reset_in3 => merged_reset.IN1 +reset_in4 => merged_reset.IN1 +reset_in5 => merged_reset.IN1 +reset_in6 => merged_reset.IN1 +reset_in7 => merged_reset.IN1 +reset_in8 => merged_reset.IN1 +reset_in9 => merged_reset.IN1 +reset_in10 => merged_reset.IN1 +reset_in11 => merged_reset.IN1 +reset_in12 => merged_reset.IN1 +reset_in13 => merged_reset.IN1 +reset_in14 => merged_reset.IN1 +reset_in15 => merged_reset.IN1 +clk => clk.IN1 +reset_out <= altera_reset_synchronizer:alt_rst_sync_uq1.reset_out + + +|de0_nano_system|system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1 +reset_in => altera_reset_synchronizer_int_chain_out.PRESET +reset_in => altera_reset_synchronizer_int_chain[0].PRESET +reset_in => altera_reset_synchronizer_int_chain[1].PRESET +clk => altera_reset_synchronizer_int_chain_out.CLK +clk => altera_reset_synchronizer_int_chain[0].CLK +clk => altera_reset_synchronizer_int_chain[1].CLK +reset_out <= altera_reset_synchronizer_int_chain_out.DB_MAX_OUTPUT_PORT_TYPE + + +|de0_nano_system|system:inst_cpu|system_cmd_xbar_demux:cmd_xbar_demux +sink_valid[0] => src0_valid.IN0 +sink_valid[1] => src1_valid.IN0 +sink_valid[2] => ~NO_FANOUT~ +sink_valid[3] => ~NO_FANOUT~ +sink_valid[4] => ~NO_FANOUT~ +sink_valid[5] => ~NO_FANOUT~ +sink_valid[6] => ~NO_FANOUT~ +sink_valid[7] => ~NO_FANOUT~ +sink_valid[8] => ~NO_FANOUT~ +sink_valid[9] => ~NO_FANOUT~ +sink_valid[10] => ~NO_FANOUT~ +sink_data[0] => src1_data[0].DATAIN +sink_data[0] => src0_data[0].DATAIN +sink_data[1] => src1_data[1].DATAIN +sink_data[1] => src0_data[1].DATAIN +sink_data[2] => src1_data[2].DATAIN +sink_data[2] => src0_data[2].DATAIN +sink_data[3] => src1_data[3].DATAIN +sink_data[3] => src0_data[3].DATAIN +sink_data[4] => src1_data[4].DATAIN +sink_data[4] => src0_data[4].DATAIN +sink_data[5] => src1_data[5].DATAIN +sink_data[5] => src0_data[5].DATAIN +sink_data[6] => src1_data[6].DATAIN +sink_data[6] => src0_data[6].DATAIN +sink_data[7] => src1_data[7].DATAIN +sink_data[7] => src0_data[7].DATAIN +sink_data[8] => src1_data[8].DATAIN +sink_data[8] => src0_data[8].DATAIN +sink_data[9] => src1_data[9].DATAIN +sink_data[9] => src0_data[9].DATAIN +sink_data[10] => src1_data[10].DATAIN +sink_data[10] => src0_data[10].DATAIN +sink_data[11] => src1_data[11].DATAIN +sink_data[11] => src0_data[11].DATAIN +sink_data[12] => src1_data[12].DATAIN +sink_data[12] => src0_data[12].DATAIN +sink_data[13] => src1_data[13].DATAIN +sink_data[13] => src0_data[13].DATAIN +sink_data[14] => src1_data[14].DATAIN +sink_data[14] => src0_data[14].DATAIN +sink_data[15] => src1_data[15].DATAIN +sink_data[15] => src0_data[15].DATAIN +sink_data[16] => src1_data[16].DATAIN +sink_data[16] => src0_data[16].DATAIN +sink_data[17] => src1_data[17].DATAIN +sink_data[17] => src0_data[17].DATAIN +sink_data[18] => src1_data[18].DATAIN +sink_data[18] => src0_data[18].DATAIN +sink_data[19] => src1_data[19].DATAIN +sink_data[19] => src0_data[19].DATAIN +sink_data[20] => src1_data[20].DATAIN +sink_data[20] => src0_data[20].DATAIN +sink_data[21] => src1_data[21].DATAIN +sink_data[21] => src0_data[21].DATAIN +sink_data[22] => src1_data[22].DATAIN +sink_data[22] => src0_data[22].DATAIN +sink_data[23] => src1_data[23].DATAIN +sink_data[23] => src0_data[23].DATAIN +sink_data[24] => src1_data[24].DATAIN +sink_data[24] => src0_data[24].DATAIN +sink_data[25] => src1_data[25].DATAIN +sink_data[25] => src0_data[25].DATAIN +sink_data[26] => src1_data[26].DATAIN +sink_data[26] => src0_data[26].DATAIN +sink_data[27] => src1_data[27].DATAIN +sink_data[27] => src0_data[27].DATAIN +sink_data[28] => src1_data[28].DATAIN +sink_data[28] => src0_data[28].DATAIN +sink_data[29] => src1_data[29].DATAIN +sink_data[29] => src0_data[29].DATAIN +sink_data[30] => src1_data[30].DATAIN +sink_data[30] => src0_data[30].DATAIN +sink_data[31] => src1_data[31].DATAIN +sink_data[31] => src0_data[31].DATAIN +sink_data[32] => src1_data[32].DATAIN +sink_data[32] => src0_data[32].DATAIN +sink_data[33] => src1_data[33].DATAIN +sink_data[33] => src0_data[33].DATAIN +sink_data[34] => src1_data[34].DATAIN +sink_data[34] => src0_data[34].DATAIN +sink_data[35] => src1_data[35].DATAIN +sink_data[35] => src0_data[35].DATAIN +sink_data[36] => src1_data[36].DATAIN +sink_data[36] => src0_data[36].DATAIN +sink_data[37] => src1_data[37].DATAIN +sink_data[37] => src0_data[37].DATAIN +sink_data[38] => src1_data[38].DATAIN +sink_data[38] => src0_data[38].DATAIN +sink_data[39] => src1_data[39].DATAIN +sink_data[39] => src0_data[39].DATAIN +sink_data[40] => src1_data[40].DATAIN +sink_data[40] => src0_data[40].DATAIN +sink_data[41] => src1_data[41].DATAIN +sink_data[41] => src0_data[41].DATAIN +sink_data[42] => src1_data[42].DATAIN +sink_data[42] => src0_data[42].DATAIN +sink_data[43] => src1_data[43].DATAIN +sink_data[43] => src0_data[43].DATAIN +sink_data[44] => src1_data[44].DATAIN +sink_data[44] => src0_data[44].DATAIN +sink_data[45] => src1_data[45].DATAIN +sink_data[45] => src0_data[45].DATAIN +sink_data[46] => src1_data[46].DATAIN +sink_data[46] => src0_data[46].DATAIN +sink_data[47] => src1_data[47].DATAIN +sink_data[47] => src0_data[47].DATAIN +sink_data[48] => src1_data[48].DATAIN +sink_data[48] => src0_data[48].DATAIN +sink_data[49] => src1_data[49].DATAIN +sink_data[49] => src0_data[49].DATAIN +sink_data[50] => src1_data[50].DATAIN +sink_data[50] => src0_data[50].DATAIN +sink_data[51] => src1_data[51].DATAIN +sink_data[51] => src0_data[51].DATAIN +sink_data[52] => src1_data[52].DATAIN +sink_data[52] => src0_data[52].DATAIN +sink_data[53] => src1_data[53].DATAIN +sink_data[53] => src0_data[53].DATAIN +sink_data[54] => src1_data[54].DATAIN +sink_data[54] => src0_data[54].DATAIN +sink_data[55] => src1_data[55].DATAIN +sink_data[55] => src0_data[55].DATAIN +sink_data[56] => src1_data[56].DATAIN +sink_data[56] => src0_data[56].DATAIN +sink_data[57] => src1_data[57].DATAIN +sink_data[57] => src0_data[57].DATAIN +sink_data[58] => src1_data[58].DATAIN +sink_data[58] => src0_data[58].DATAIN +sink_data[59] => src1_data[59].DATAIN +sink_data[59] => src0_data[59].DATAIN +sink_data[60] => src1_data[60].DATAIN +sink_data[60] => src0_data[60].DATAIN +sink_data[61] => src1_data[61].DATAIN +sink_data[61] => src0_data[61].DATAIN +sink_data[62] => src1_data[62].DATAIN +sink_data[62] => src0_data[62].DATAIN +sink_data[63] => src1_data[63].DATAIN +sink_data[63] => src0_data[63].DATAIN +sink_data[64] => src1_data[64].DATAIN +sink_data[64] => src0_data[64].DATAIN +sink_data[65] => src1_data[65].DATAIN +sink_data[65] => src0_data[65].DATAIN +sink_data[66] => src1_data[66].DATAIN +sink_data[66] => src0_data[66].DATAIN +sink_data[67] => src1_data[67].DATAIN +sink_data[67] => src0_data[67].DATAIN +sink_data[68] => src1_data[68].DATAIN +sink_data[68] => src0_data[68].DATAIN +sink_data[69] => src1_data[69].DATAIN +sink_data[69] => src0_data[69].DATAIN +sink_data[70] => src1_data[70].DATAIN +sink_data[70] => src0_data[70].DATAIN +sink_data[71] => src1_data[71].DATAIN +sink_data[71] => src0_data[71].DATAIN +sink_data[72] => src1_data[72].DATAIN +sink_data[72] => src0_data[72].DATAIN +sink_data[73] => src1_data[73].DATAIN +sink_data[73] => src0_data[73].DATAIN +sink_data[74] => src1_data[74].DATAIN +sink_data[74] => src0_data[74].DATAIN +sink_data[75] => src1_data[75].DATAIN +sink_data[75] => src0_data[75].DATAIN +sink_data[76] => src1_data[76].DATAIN +sink_data[76] => src0_data[76].DATAIN +sink_data[77] => src1_data[77].DATAIN +sink_data[77] => src0_data[77].DATAIN +sink_data[78] => src1_data[78].DATAIN +sink_data[78] => src0_data[78].DATAIN +sink_data[79] => src1_data[79].DATAIN +sink_data[79] => src0_data[79].DATAIN +sink_data[80] => src1_data[80].DATAIN +sink_data[80] => src0_data[80].DATAIN +sink_data[81] => src1_data[81].DATAIN +sink_data[81] => src0_data[81].DATAIN +sink_data[82] => src1_data[82].DATAIN +sink_data[82] => src0_data[82].DATAIN +sink_data[83] => src1_data[83].DATAIN +sink_data[83] => src0_data[83].DATAIN +sink_data[84] => src1_data[84].DATAIN +sink_data[84] => src0_data[84].DATAIN +sink_data[85] => src1_data[85].DATAIN +sink_data[85] => src0_data[85].DATAIN +sink_data[86] => src1_data[86].DATAIN +sink_data[86] => src0_data[86].DATAIN +sink_data[87] => src1_data[87].DATAIN +sink_data[87] => src0_data[87].DATAIN +sink_data[88] => src1_data[88].DATAIN +sink_data[88] => src0_data[88].DATAIN +sink_data[89] => src1_data[89].DATAIN +sink_data[89] => src0_data[89].DATAIN +sink_data[90] => src1_data[90].DATAIN +sink_data[90] => src0_data[90].DATAIN +sink_data[91] => src1_data[91].DATAIN +sink_data[91] => src0_data[91].DATAIN +sink_data[92] => src1_data[92].DATAIN +sink_data[92] => src0_data[92].DATAIN +sink_data[93] => src1_data[93].DATAIN +sink_data[93] => src0_data[93].DATAIN +sink_data[94] => src1_data[94].DATAIN +sink_data[94] => src0_data[94].DATAIN +sink_data[95] => src1_data[95].DATAIN +sink_data[95] => src0_data[95].DATAIN +sink_data[96] => src1_data[96].DATAIN +sink_data[96] => src0_data[96].DATAIN +sink_data[97] => src1_data[97].DATAIN +sink_data[97] => src0_data[97].DATAIN +sink_data[98] => src1_data[98].DATAIN +sink_data[98] => src0_data[98].DATAIN +sink_data[99] => src1_data[99].DATAIN +sink_data[99] => src0_data[99].DATAIN +sink_data[100] => src1_data[100].DATAIN +sink_data[100] => src0_data[100].DATAIN +sink_channel[0] => src0_valid.IN1 +sink_channel[0] => sink_ready.IN0 +sink_channel[1] => src1_valid.IN1 +sink_channel[1] => sink_ready.IN0 +sink_channel[2] => src1_channel[0].DATAIN +sink_channel[2] => src0_channel[0].DATAIN +sink_channel[3] => src1_channel[1].DATAIN +sink_channel[3] => src0_channel[1].DATAIN +sink_channel[4] => src1_channel[2].DATAIN +sink_channel[4] => src0_channel[2].DATAIN +sink_channel[5] => src1_channel[3].DATAIN +sink_channel[5] => src0_channel[3].DATAIN +sink_channel[6] => src1_channel[4].DATAIN +sink_channel[6] => src0_channel[4].DATAIN +sink_channel[7] => src1_channel[5].DATAIN +sink_channel[7] => src0_channel[5].DATAIN +sink_channel[8] => src1_channel[6].DATAIN +sink_channel[8] => src0_channel[6].DATAIN +sink_channel[9] => src1_channel[7].DATAIN +sink_channel[9] => src0_channel[7].DATAIN +sink_channel[10] => src1_channel[8].DATAIN +sink_channel[10] => src0_channel[8].DATAIN +sink_startofpacket => src1_startofpacket.DATAIN +sink_startofpacket => src0_startofpacket.DATAIN +sink_endofpacket => src1_endofpacket.DATAIN +sink_endofpacket => src0_endofpacket.DATAIN +sink_ready <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE +src0_valid <= src0_valid.DB_MAX_OUTPUT_PORT_TYPE +src0_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src0_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src0_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src0_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src0_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src0_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src0_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src0_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src0_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src0_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src0_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src0_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src0_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src0_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src0_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src0_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src0_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src0_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src0_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src0_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src0_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src0_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src0_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src0_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src0_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src0_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src0_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src0_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src0_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src0_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src0_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src0_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src0_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src0_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src0_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src0_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src0_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src0_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src0_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src0_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src0_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src0_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src0_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src0_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src0_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src0_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src0_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src0_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src0_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src0_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src0_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src0_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src0_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src0_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src0_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src0_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src0_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src0_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src0_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src0_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src0_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src0_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src0_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src0_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src0_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src0_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src0_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src0_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src0_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src0_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src0_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src0_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src0_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src0_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src0_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src0_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src0_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src0_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src0_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src0_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src0_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src0_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src0_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src0_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src0_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src0_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src0_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src0_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src0_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src0_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src0_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src0_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src0_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src0_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src0_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src0_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src0_data[96] <= sink_data[96].DB_MAX_OUTPUT_PORT_TYPE +src0_data[97] <= sink_data[97].DB_MAX_OUTPUT_PORT_TYPE +src0_data[98] <= sink_data[98].DB_MAX_OUTPUT_PORT_TYPE +src0_data[99] <= sink_data[99].DB_MAX_OUTPUT_PORT_TYPE +src0_data[100] <= sink_data[100].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[0] <= sink_channel[2].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[1] <= sink_channel[3].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[2] <= sink_channel[4].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[3] <= sink_channel[5].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[4] <= sink_channel[6].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[5] <= sink_channel[7].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[6] <= sink_channel[8].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[7] <= sink_channel[9].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[8] <= sink_channel[10].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[9] <= +src0_channel[10] <= +src0_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src0_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src0_ready => sink_ready.IN1 +src1_valid <= src1_valid.DB_MAX_OUTPUT_PORT_TYPE +src1_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src1_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src1_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src1_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src1_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src1_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src1_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src1_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src1_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src1_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src1_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src1_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src1_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src1_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src1_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src1_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src1_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src1_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src1_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src1_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src1_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src1_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src1_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src1_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src1_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src1_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src1_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src1_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src1_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src1_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src1_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src1_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src1_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src1_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src1_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src1_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src1_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src1_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src1_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src1_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src1_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src1_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src1_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src1_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src1_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src1_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src1_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src1_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src1_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src1_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src1_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src1_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src1_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src1_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src1_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src1_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src1_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src1_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src1_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src1_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src1_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src1_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src1_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src1_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src1_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src1_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src1_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src1_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src1_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src1_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src1_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src1_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src1_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src1_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src1_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src1_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src1_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src1_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src1_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src1_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src1_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src1_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src1_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src1_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src1_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src1_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src1_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src1_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src1_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src1_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src1_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src1_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src1_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src1_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src1_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src1_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src1_data[96] <= sink_data[96].DB_MAX_OUTPUT_PORT_TYPE +src1_data[97] <= sink_data[97].DB_MAX_OUTPUT_PORT_TYPE +src1_data[98] <= sink_data[98].DB_MAX_OUTPUT_PORT_TYPE +src1_data[99] <= sink_data[99].DB_MAX_OUTPUT_PORT_TYPE +src1_data[100] <= sink_data[100].DB_MAX_OUTPUT_PORT_TYPE +src1_channel[0] <= sink_channel[2].DB_MAX_OUTPUT_PORT_TYPE +src1_channel[1] <= sink_channel[3].DB_MAX_OUTPUT_PORT_TYPE +src1_channel[2] <= sink_channel[4].DB_MAX_OUTPUT_PORT_TYPE +src1_channel[3] <= sink_channel[5].DB_MAX_OUTPUT_PORT_TYPE +src1_channel[4] <= sink_channel[6].DB_MAX_OUTPUT_PORT_TYPE +src1_channel[5] <= sink_channel[7].DB_MAX_OUTPUT_PORT_TYPE +src1_channel[6] <= sink_channel[8].DB_MAX_OUTPUT_PORT_TYPE +src1_channel[7] <= sink_channel[9].DB_MAX_OUTPUT_PORT_TYPE +src1_channel[8] <= sink_channel[10].DB_MAX_OUTPUT_PORT_TYPE +src1_channel[9] <= +src1_channel[10] <= +src1_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src1_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src1_ready => sink_ready.IN1 +clk => ~NO_FANOUT~ +reset => ~NO_FANOUT~ + + +|de0_nano_system|system:inst_cpu|system_cmd_xbar_demux_001:cmd_xbar_demux_001 +sink_valid[0] => src0_valid.IN0 +sink_valid[1] => src1_valid.IN0 +sink_valid[2] => src2_valid.IN0 +sink_valid[3] => src3_valid.IN0 +sink_valid[4] => src4_valid.IN0 +sink_valid[5] => src5_valid.IN0 +sink_valid[6] => src6_valid.IN0 +sink_valid[7] => src7_valid.IN0 +sink_valid[8] => src8_valid.IN0 +sink_valid[9] => src9_valid.IN0 +sink_valid[10] => src10_valid.IN0 +sink_data[0] => src10_data[0].DATAIN +sink_data[0] => src0_data[0].DATAIN +sink_data[0] => src1_data[0].DATAIN +sink_data[0] => src2_data[0].DATAIN +sink_data[0] => src3_data[0].DATAIN +sink_data[0] => src4_data[0].DATAIN +sink_data[0] => src5_data[0].DATAIN +sink_data[0] => src6_data[0].DATAIN +sink_data[0] => src7_data[0].DATAIN +sink_data[0] => src8_data[0].DATAIN +sink_data[0] => src9_data[0].DATAIN +sink_data[1] => src10_data[1].DATAIN +sink_data[1] => src0_data[1].DATAIN +sink_data[1] => src1_data[1].DATAIN +sink_data[1] => src2_data[1].DATAIN +sink_data[1] => src3_data[1].DATAIN +sink_data[1] => src4_data[1].DATAIN +sink_data[1] => src5_data[1].DATAIN +sink_data[1] => src6_data[1].DATAIN +sink_data[1] => src7_data[1].DATAIN +sink_data[1] => src8_data[1].DATAIN +sink_data[1] => src9_data[1].DATAIN +sink_data[2] => src10_data[2].DATAIN +sink_data[2] => src0_data[2].DATAIN +sink_data[2] => src1_data[2].DATAIN +sink_data[2] => src2_data[2].DATAIN +sink_data[2] => src3_data[2].DATAIN +sink_data[2] => src4_data[2].DATAIN +sink_data[2] => src5_data[2].DATAIN +sink_data[2] => src6_data[2].DATAIN +sink_data[2] => src7_data[2].DATAIN +sink_data[2] => src8_data[2].DATAIN +sink_data[2] => src9_data[2].DATAIN +sink_data[3] => src10_data[3].DATAIN +sink_data[3] => src0_data[3].DATAIN +sink_data[3] => src1_data[3].DATAIN +sink_data[3] => src2_data[3].DATAIN +sink_data[3] => src3_data[3].DATAIN +sink_data[3] => src4_data[3].DATAIN +sink_data[3] => src5_data[3].DATAIN +sink_data[3] => src6_data[3].DATAIN +sink_data[3] => src7_data[3].DATAIN +sink_data[3] => src8_data[3].DATAIN +sink_data[3] => src9_data[3].DATAIN +sink_data[4] => src10_data[4].DATAIN +sink_data[4] => src0_data[4].DATAIN +sink_data[4] => src1_data[4].DATAIN +sink_data[4] => src2_data[4].DATAIN +sink_data[4] => src3_data[4].DATAIN +sink_data[4] => src4_data[4].DATAIN +sink_data[4] => src5_data[4].DATAIN +sink_data[4] => src6_data[4].DATAIN +sink_data[4] => src7_data[4].DATAIN +sink_data[4] => src8_data[4].DATAIN +sink_data[4] => src9_data[4].DATAIN +sink_data[5] => src10_data[5].DATAIN +sink_data[5] => src0_data[5].DATAIN +sink_data[5] => src1_data[5].DATAIN +sink_data[5] => src2_data[5].DATAIN +sink_data[5] => src3_data[5].DATAIN +sink_data[5] => src4_data[5].DATAIN +sink_data[5] => src5_data[5].DATAIN +sink_data[5] => src6_data[5].DATAIN +sink_data[5] => src7_data[5].DATAIN +sink_data[5] => src8_data[5].DATAIN +sink_data[5] => src9_data[5].DATAIN +sink_data[6] => src10_data[6].DATAIN +sink_data[6] => src0_data[6].DATAIN +sink_data[6] => src1_data[6].DATAIN +sink_data[6] => src2_data[6].DATAIN +sink_data[6] => src3_data[6].DATAIN +sink_data[6] => src4_data[6].DATAIN +sink_data[6] => src5_data[6].DATAIN +sink_data[6] => src6_data[6].DATAIN +sink_data[6] => src7_data[6].DATAIN +sink_data[6] => src8_data[6].DATAIN +sink_data[6] => src9_data[6].DATAIN +sink_data[7] => src10_data[7].DATAIN +sink_data[7] => src0_data[7].DATAIN +sink_data[7] => src1_data[7].DATAIN +sink_data[7] => src2_data[7].DATAIN +sink_data[7] => src3_data[7].DATAIN +sink_data[7] => src4_data[7].DATAIN +sink_data[7] => src5_data[7].DATAIN +sink_data[7] => src6_data[7].DATAIN +sink_data[7] => src7_data[7].DATAIN +sink_data[7] => src8_data[7].DATAIN +sink_data[7] => src9_data[7].DATAIN +sink_data[8] => src10_data[8].DATAIN +sink_data[8] => src0_data[8].DATAIN +sink_data[8] => src1_data[8].DATAIN +sink_data[8] => src2_data[8].DATAIN +sink_data[8] => src3_data[8].DATAIN +sink_data[8] => src4_data[8].DATAIN +sink_data[8] => src5_data[8].DATAIN +sink_data[8] => src6_data[8].DATAIN +sink_data[8] => src7_data[8].DATAIN +sink_data[8] => src8_data[8].DATAIN +sink_data[8] => src9_data[8].DATAIN +sink_data[9] => src10_data[9].DATAIN +sink_data[9] => src0_data[9].DATAIN +sink_data[9] => src1_data[9].DATAIN +sink_data[9] => src2_data[9].DATAIN +sink_data[9] => src3_data[9].DATAIN +sink_data[9] => src4_data[9].DATAIN +sink_data[9] => src5_data[9].DATAIN +sink_data[9] => src6_data[9].DATAIN +sink_data[9] => src7_data[9].DATAIN +sink_data[9] => src8_data[9].DATAIN +sink_data[9] => src9_data[9].DATAIN +sink_data[10] => src10_data[10].DATAIN +sink_data[10] => src0_data[10].DATAIN +sink_data[10] => src1_data[10].DATAIN +sink_data[10] => src2_data[10].DATAIN +sink_data[10] => src3_data[10].DATAIN +sink_data[10] => src4_data[10].DATAIN +sink_data[10] => src5_data[10].DATAIN +sink_data[10] => src6_data[10].DATAIN +sink_data[10] => src7_data[10].DATAIN +sink_data[10] => src8_data[10].DATAIN +sink_data[10] => src9_data[10].DATAIN +sink_data[11] => src10_data[11].DATAIN +sink_data[11] => src0_data[11].DATAIN +sink_data[11] => src1_data[11].DATAIN +sink_data[11] => src2_data[11].DATAIN +sink_data[11] => src3_data[11].DATAIN +sink_data[11] => src4_data[11].DATAIN +sink_data[11] => src5_data[11].DATAIN +sink_data[11] => src6_data[11].DATAIN +sink_data[11] => src7_data[11].DATAIN +sink_data[11] => src8_data[11].DATAIN +sink_data[11] => src9_data[11].DATAIN +sink_data[12] => src10_data[12].DATAIN +sink_data[12] => src0_data[12].DATAIN +sink_data[12] => src1_data[12].DATAIN +sink_data[12] => src2_data[12].DATAIN +sink_data[12] => src3_data[12].DATAIN +sink_data[12] => src4_data[12].DATAIN +sink_data[12] => src5_data[12].DATAIN +sink_data[12] => src6_data[12].DATAIN +sink_data[12] => src7_data[12].DATAIN +sink_data[12] => src8_data[12].DATAIN +sink_data[12] => src9_data[12].DATAIN +sink_data[13] => src10_data[13].DATAIN +sink_data[13] => src0_data[13].DATAIN +sink_data[13] => src1_data[13].DATAIN +sink_data[13] => src2_data[13].DATAIN +sink_data[13] => src3_data[13].DATAIN +sink_data[13] => src4_data[13].DATAIN +sink_data[13] => src5_data[13].DATAIN +sink_data[13] => src6_data[13].DATAIN +sink_data[13] => src7_data[13].DATAIN +sink_data[13] => src8_data[13].DATAIN +sink_data[13] => src9_data[13].DATAIN +sink_data[14] => src10_data[14].DATAIN +sink_data[14] => src0_data[14].DATAIN +sink_data[14] => src1_data[14].DATAIN +sink_data[14] => src2_data[14].DATAIN +sink_data[14] => src3_data[14].DATAIN +sink_data[14] => src4_data[14].DATAIN +sink_data[14] => src5_data[14].DATAIN +sink_data[14] => src6_data[14].DATAIN +sink_data[14] => src7_data[14].DATAIN +sink_data[14] => src8_data[14].DATAIN +sink_data[14] => src9_data[14].DATAIN +sink_data[15] => src10_data[15].DATAIN +sink_data[15] => src0_data[15].DATAIN +sink_data[15] => src1_data[15].DATAIN +sink_data[15] => src2_data[15].DATAIN +sink_data[15] => src3_data[15].DATAIN +sink_data[15] => src4_data[15].DATAIN +sink_data[15] => src5_data[15].DATAIN +sink_data[15] => src6_data[15].DATAIN +sink_data[15] => src7_data[15].DATAIN +sink_data[15] => src8_data[15].DATAIN +sink_data[15] => src9_data[15].DATAIN +sink_data[16] => src10_data[16].DATAIN +sink_data[16] => src0_data[16].DATAIN +sink_data[16] => src1_data[16].DATAIN +sink_data[16] => src2_data[16].DATAIN +sink_data[16] => src3_data[16].DATAIN +sink_data[16] => src4_data[16].DATAIN +sink_data[16] => src5_data[16].DATAIN +sink_data[16] => src6_data[16].DATAIN +sink_data[16] => src7_data[16].DATAIN +sink_data[16] => src8_data[16].DATAIN +sink_data[16] => src9_data[16].DATAIN +sink_data[17] => src10_data[17].DATAIN +sink_data[17] => src0_data[17].DATAIN +sink_data[17] => src1_data[17].DATAIN +sink_data[17] => src2_data[17].DATAIN +sink_data[17] => src3_data[17].DATAIN +sink_data[17] => src4_data[17].DATAIN +sink_data[17] => src5_data[17].DATAIN +sink_data[17] => src6_data[17].DATAIN +sink_data[17] => src7_data[17].DATAIN +sink_data[17] => src8_data[17].DATAIN +sink_data[17] => src9_data[17].DATAIN +sink_data[18] => src10_data[18].DATAIN +sink_data[18] => src0_data[18].DATAIN +sink_data[18] => src1_data[18].DATAIN +sink_data[18] => src2_data[18].DATAIN +sink_data[18] => src3_data[18].DATAIN +sink_data[18] => src4_data[18].DATAIN +sink_data[18] => src5_data[18].DATAIN +sink_data[18] => src6_data[18].DATAIN +sink_data[18] => src7_data[18].DATAIN +sink_data[18] => src8_data[18].DATAIN +sink_data[18] => src9_data[18].DATAIN +sink_data[19] => src10_data[19].DATAIN +sink_data[19] => src0_data[19].DATAIN +sink_data[19] => src1_data[19].DATAIN +sink_data[19] => src2_data[19].DATAIN +sink_data[19] => src3_data[19].DATAIN +sink_data[19] => src4_data[19].DATAIN +sink_data[19] => src5_data[19].DATAIN +sink_data[19] => src6_data[19].DATAIN +sink_data[19] => src7_data[19].DATAIN +sink_data[19] => src8_data[19].DATAIN +sink_data[19] => src9_data[19].DATAIN +sink_data[20] => src10_data[20].DATAIN +sink_data[20] => src0_data[20].DATAIN +sink_data[20] => src1_data[20].DATAIN +sink_data[20] => src2_data[20].DATAIN +sink_data[20] => src3_data[20].DATAIN +sink_data[20] => src4_data[20].DATAIN +sink_data[20] => src5_data[20].DATAIN +sink_data[20] => src6_data[20].DATAIN +sink_data[20] => src7_data[20].DATAIN +sink_data[20] => src8_data[20].DATAIN +sink_data[20] => src9_data[20].DATAIN +sink_data[21] => src10_data[21].DATAIN +sink_data[21] => src0_data[21].DATAIN +sink_data[21] => src1_data[21].DATAIN +sink_data[21] => src2_data[21].DATAIN +sink_data[21] => src3_data[21].DATAIN +sink_data[21] => src4_data[21].DATAIN +sink_data[21] => src5_data[21].DATAIN +sink_data[21] => src6_data[21].DATAIN +sink_data[21] => src7_data[21].DATAIN +sink_data[21] => src8_data[21].DATAIN +sink_data[21] => src9_data[21].DATAIN +sink_data[22] => src10_data[22].DATAIN +sink_data[22] => src0_data[22].DATAIN +sink_data[22] => src1_data[22].DATAIN +sink_data[22] => src2_data[22].DATAIN +sink_data[22] => src3_data[22].DATAIN +sink_data[22] => src4_data[22].DATAIN +sink_data[22] => src5_data[22].DATAIN +sink_data[22] => src6_data[22].DATAIN +sink_data[22] => src7_data[22].DATAIN +sink_data[22] => src8_data[22].DATAIN +sink_data[22] => src9_data[22].DATAIN +sink_data[23] => src10_data[23].DATAIN +sink_data[23] => src0_data[23].DATAIN +sink_data[23] => src1_data[23].DATAIN +sink_data[23] => src2_data[23].DATAIN +sink_data[23] => src3_data[23].DATAIN +sink_data[23] => src4_data[23].DATAIN +sink_data[23] => src5_data[23].DATAIN +sink_data[23] => src6_data[23].DATAIN +sink_data[23] => src7_data[23].DATAIN +sink_data[23] => src8_data[23].DATAIN +sink_data[23] => src9_data[23].DATAIN +sink_data[24] => src10_data[24].DATAIN +sink_data[24] => src0_data[24].DATAIN +sink_data[24] => src1_data[24].DATAIN +sink_data[24] => src2_data[24].DATAIN +sink_data[24] => src3_data[24].DATAIN +sink_data[24] => src4_data[24].DATAIN +sink_data[24] => src5_data[24].DATAIN +sink_data[24] => src6_data[24].DATAIN +sink_data[24] => src7_data[24].DATAIN +sink_data[24] => src8_data[24].DATAIN +sink_data[24] => src9_data[24].DATAIN +sink_data[25] => src10_data[25].DATAIN +sink_data[25] => src0_data[25].DATAIN +sink_data[25] => src1_data[25].DATAIN +sink_data[25] => src2_data[25].DATAIN +sink_data[25] => src3_data[25].DATAIN +sink_data[25] => src4_data[25].DATAIN +sink_data[25] => src5_data[25].DATAIN +sink_data[25] => src6_data[25].DATAIN +sink_data[25] => src7_data[25].DATAIN +sink_data[25] => src8_data[25].DATAIN +sink_data[25] => src9_data[25].DATAIN +sink_data[26] => src10_data[26].DATAIN +sink_data[26] => src0_data[26].DATAIN +sink_data[26] => src1_data[26].DATAIN +sink_data[26] => src2_data[26].DATAIN +sink_data[26] => src3_data[26].DATAIN +sink_data[26] => src4_data[26].DATAIN +sink_data[26] => src5_data[26].DATAIN +sink_data[26] => src6_data[26].DATAIN +sink_data[26] => src7_data[26].DATAIN +sink_data[26] => src8_data[26].DATAIN +sink_data[26] => src9_data[26].DATAIN +sink_data[27] => src10_data[27].DATAIN +sink_data[27] => src0_data[27].DATAIN +sink_data[27] => src1_data[27].DATAIN +sink_data[27] => src2_data[27].DATAIN +sink_data[27] => src3_data[27].DATAIN +sink_data[27] => src4_data[27].DATAIN +sink_data[27] => src5_data[27].DATAIN +sink_data[27] => src6_data[27].DATAIN +sink_data[27] => src7_data[27].DATAIN +sink_data[27] => src8_data[27].DATAIN +sink_data[27] => src9_data[27].DATAIN +sink_data[28] => src10_data[28].DATAIN +sink_data[28] => src0_data[28].DATAIN +sink_data[28] => src1_data[28].DATAIN +sink_data[28] => src2_data[28].DATAIN +sink_data[28] => src3_data[28].DATAIN +sink_data[28] => src4_data[28].DATAIN +sink_data[28] => src5_data[28].DATAIN +sink_data[28] => src6_data[28].DATAIN +sink_data[28] => src7_data[28].DATAIN +sink_data[28] => src8_data[28].DATAIN +sink_data[28] => src9_data[28].DATAIN +sink_data[29] => src10_data[29].DATAIN +sink_data[29] => src0_data[29].DATAIN +sink_data[29] => src1_data[29].DATAIN +sink_data[29] => src2_data[29].DATAIN +sink_data[29] => src3_data[29].DATAIN +sink_data[29] => src4_data[29].DATAIN +sink_data[29] => src5_data[29].DATAIN +sink_data[29] => src6_data[29].DATAIN +sink_data[29] => src7_data[29].DATAIN +sink_data[29] => src8_data[29].DATAIN +sink_data[29] => src9_data[29].DATAIN +sink_data[30] => src10_data[30].DATAIN +sink_data[30] => src0_data[30].DATAIN +sink_data[30] => src1_data[30].DATAIN +sink_data[30] => src2_data[30].DATAIN +sink_data[30] => src3_data[30].DATAIN +sink_data[30] => src4_data[30].DATAIN +sink_data[30] => src5_data[30].DATAIN +sink_data[30] => src6_data[30].DATAIN +sink_data[30] => src7_data[30].DATAIN +sink_data[30] => src8_data[30].DATAIN +sink_data[30] => src9_data[30].DATAIN +sink_data[31] => src10_data[31].DATAIN +sink_data[31] => src0_data[31].DATAIN +sink_data[31] => src1_data[31].DATAIN +sink_data[31] => src2_data[31].DATAIN +sink_data[31] => src3_data[31].DATAIN +sink_data[31] => src4_data[31].DATAIN +sink_data[31] => src5_data[31].DATAIN +sink_data[31] => src6_data[31].DATAIN +sink_data[31] => src7_data[31].DATAIN +sink_data[31] => src8_data[31].DATAIN +sink_data[31] => src9_data[31].DATAIN +sink_data[32] => src10_data[32].DATAIN +sink_data[32] => src0_data[32].DATAIN +sink_data[32] => src1_data[32].DATAIN +sink_data[32] => src2_data[32].DATAIN +sink_data[32] => src3_data[32].DATAIN +sink_data[32] => src4_data[32].DATAIN +sink_data[32] => src5_data[32].DATAIN +sink_data[32] => src6_data[32].DATAIN +sink_data[32] => src7_data[32].DATAIN +sink_data[32] => src8_data[32].DATAIN +sink_data[32] => src9_data[32].DATAIN +sink_data[33] => src10_data[33].DATAIN +sink_data[33] => src0_data[33].DATAIN +sink_data[33] => src1_data[33].DATAIN +sink_data[33] => src2_data[33].DATAIN +sink_data[33] => src3_data[33].DATAIN +sink_data[33] => src4_data[33].DATAIN +sink_data[33] => src5_data[33].DATAIN +sink_data[33] => src6_data[33].DATAIN +sink_data[33] => src7_data[33].DATAIN +sink_data[33] => src8_data[33].DATAIN +sink_data[33] => src9_data[33].DATAIN +sink_data[34] => src10_data[34].DATAIN +sink_data[34] => src0_data[34].DATAIN +sink_data[34] => src1_data[34].DATAIN +sink_data[34] => src2_data[34].DATAIN +sink_data[34] => src3_data[34].DATAIN +sink_data[34] => src4_data[34].DATAIN +sink_data[34] => src5_data[34].DATAIN +sink_data[34] => src6_data[34].DATAIN +sink_data[34] => src7_data[34].DATAIN +sink_data[34] => src8_data[34].DATAIN +sink_data[34] => src9_data[34].DATAIN +sink_data[35] => src10_data[35].DATAIN +sink_data[35] => src0_data[35].DATAIN +sink_data[35] => src1_data[35].DATAIN +sink_data[35] => src2_data[35].DATAIN +sink_data[35] => src3_data[35].DATAIN +sink_data[35] => src4_data[35].DATAIN +sink_data[35] => src5_data[35].DATAIN +sink_data[35] => src6_data[35].DATAIN +sink_data[35] => src7_data[35].DATAIN +sink_data[35] => src8_data[35].DATAIN +sink_data[35] => src9_data[35].DATAIN +sink_data[36] => src10_data[36].DATAIN +sink_data[36] => src0_data[36].DATAIN +sink_data[36] => src1_data[36].DATAIN +sink_data[36] => src2_data[36].DATAIN +sink_data[36] => src3_data[36].DATAIN +sink_data[36] => src4_data[36].DATAIN +sink_data[36] => src5_data[36].DATAIN +sink_data[36] => src6_data[36].DATAIN +sink_data[36] => src7_data[36].DATAIN +sink_data[36] => src8_data[36].DATAIN +sink_data[36] => src9_data[36].DATAIN +sink_data[37] => src10_data[37].DATAIN +sink_data[37] => src0_data[37].DATAIN +sink_data[37] => src1_data[37].DATAIN +sink_data[37] => src2_data[37].DATAIN +sink_data[37] => src3_data[37].DATAIN +sink_data[37] => src4_data[37].DATAIN +sink_data[37] => src5_data[37].DATAIN +sink_data[37] => src6_data[37].DATAIN +sink_data[37] => src7_data[37].DATAIN +sink_data[37] => src8_data[37].DATAIN +sink_data[37] => src9_data[37].DATAIN +sink_data[38] => src10_data[38].DATAIN +sink_data[38] => src0_data[38].DATAIN +sink_data[38] => src1_data[38].DATAIN +sink_data[38] => src2_data[38].DATAIN +sink_data[38] => src3_data[38].DATAIN +sink_data[38] => src4_data[38].DATAIN +sink_data[38] => src5_data[38].DATAIN +sink_data[38] => src6_data[38].DATAIN +sink_data[38] => src7_data[38].DATAIN +sink_data[38] => src8_data[38].DATAIN +sink_data[38] => src9_data[38].DATAIN +sink_data[39] => src10_data[39].DATAIN +sink_data[39] => src0_data[39].DATAIN +sink_data[39] => src1_data[39].DATAIN +sink_data[39] => src2_data[39].DATAIN +sink_data[39] => src3_data[39].DATAIN +sink_data[39] => src4_data[39].DATAIN +sink_data[39] => src5_data[39].DATAIN +sink_data[39] => src6_data[39].DATAIN +sink_data[39] => src7_data[39].DATAIN +sink_data[39] => src8_data[39].DATAIN +sink_data[39] => src9_data[39].DATAIN +sink_data[40] => src10_data[40].DATAIN +sink_data[40] => src0_data[40].DATAIN +sink_data[40] => src1_data[40].DATAIN +sink_data[40] => src2_data[40].DATAIN +sink_data[40] => src3_data[40].DATAIN +sink_data[40] => src4_data[40].DATAIN +sink_data[40] => src5_data[40].DATAIN +sink_data[40] => src6_data[40].DATAIN +sink_data[40] => src7_data[40].DATAIN +sink_data[40] => src8_data[40].DATAIN +sink_data[40] => src9_data[40].DATAIN +sink_data[41] => src10_data[41].DATAIN +sink_data[41] => src0_data[41].DATAIN +sink_data[41] => src1_data[41].DATAIN +sink_data[41] => src2_data[41].DATAIN +sink_data[41] => src3_data[41].DATAIN +sink_data[41] => src4_data[41].DATAIN +sink_data[41] => src5_data[41].DATAIN +sink_data[41] => src6_data[41].DATAIN +sink_data[41] => src7_data[41].DATAIN +sink_data[41] => src8_data[41].DATAIN +sink_data[41] => src9_data[41].DATAIN +sink_data[42] => src10_data[42].DATAIN +sink_data[42] => src0_data[42].DATAIN +sink_data[42] => src1_data[42].DATAIN +sink_data[42] => src2_data[42].DATAIN +sink_data[42] => src3_data[42].DATAIN +sink_data[42] => src4_data[42].DATAIN +sink_data[42] => src5_data[42].DATAIN +sink_data[42] => src6_data[42].DATAIN +sink_data[42] => src7_data[42].DATAIN +sink_data[42] => src8_data[42].DATAIN +sink_data[42] => src9_data[42].DATAIN +sink_data[43] => src10_data[43].DATAIN +sink_data[43] => src0_data[43].DATAIN +sink_data[43] => src1_data[43].DATAIN +sink_data[43] => src2_data[43].DATAIN +sink_data[43] => src3_data[43].DATAIN +sink_data[43] => src4_data[43].DATAIN +sink_data[43] => src5_data[43].DATAIN +sink_data[43] => src6_data[43].DATAIN +sink_data[43] => src7_data[43].DATAIN +sink_data[43] => src8_data[43].DATAIN +sink_data[43] => src9_data[43].DATAIN +sink_data[44] => src10_data[44].DATAIN +sink_data[44] => src0_data[44].DATAIN +sink_data[44] => src1_data[44].DATAIN +sink_data[44] => src2_data[44].DATAIN +sink_data[44] => src3_data[44].DATAIN +sink_data[44] => src4_data[44].DATAIN +sink_data[44] => src5_data[44].DATAIN +sink_data[44] => src6_data[44].DATAIN +sink_data[44] => src7_data[44].DATAIN +sink_data[44] => src8_data[44].DATAIN +sink_data[44] => src9_data[44].DATAIN +sink_data[45] => src10_data[45].DATAIN +sink_data[45] => src0_data[45].DATAIN +sink_data[45] => src1_data[45].DATAIN +sink_data[45] => src2_data[45].DATAIN +sink_data[45] => src3_data[45].DATAIN +sink_data[45] => src4_data[45].DATAIN +sink_data[45] => src5_data[45].DATAIN +sink_data[45] => src6_data[45].DATAIN +sink_data[45] => src7_data[45].DATAIN +sink_data[45] => src8_data[45].DATAIN +sink_data[45] => src9_data[45].DATAIN +sink_data[46] => src10_data[46].DATAIN +sink_data[46] => src0_data[46].DATAIN +sink_data[46] => src1_data[46].DATAIN +sink_data[46] => src2_data[46].DATAIN +sink_data[46] => src3_data[46].DATAIN +sink_data[46] => src4_data[46].DATAIN +sink_data[46] => src5_data[46].DATAIN +sink_data[46] => src6_data[46].DATAIN +sink_data[46] => src7_data[46].DATAIN +sink_data[46] => src8_data[46].DATAIN +sink_data[46] => src9_data[46].DATAIN +sink_data[47] => src10_data[47].DATAIN +sink_data[47] => src0_data[47].DATAIN +sink_data[47] => src1_data[47].DATAIN +sink_data[47] => src2_data[47].DATAIN +sink_data[47] => src3_data[47].DATAIN +sink_data[47] => src4_data[47].DATAIN +sink_data[47] => src5_data[47].DATAIN +sink_data[47] => src6_data[47].DATAIN +sink_data[47] => src7_data[47].DATAIN +sink_data[47] => src8_data[47].DATAIN +sink_data[47] => src9_data[47].DATAIN +sink_data[48] => src10_data[48].DATAIN +sink_data[48] => src0_data[48].DATAIN +sink_data[48] => src1_data[48].DATAIN +sink_data[48] => src2_data[48].DATAIN +sink_data[48] => src3_data[48].DATAIN +sink_data[48] => src4_data[48].DATAIN +sink_data[48] => src5_data[48].DATAIN +sink_data[48] => src6_data[48].DATAIN +sink_data[48] => src7_data[48].DATAIN +sink_data[48] => src8_data[48].DATAIN +sink_data[48] => src9_data[48].DATAIN +sink_data[49] => src10_data[49].DATAIN +sink_data[49] => src0_data[49].DATAIN +sink_data[49] => src1_data[49].DATAIN +sink_data[49] => src2_data[49].DATAIN +sink_data[49] => src3_data[49].DATAIN +sink_data[49] => src4_data[49].DATAIN +sink_data[49] => src5_data[49].DATAIN +sink_data[49] => src6_data[49].DATAIN +sink_data[49] => src7_data[49].DATAIN +sink_data[49] => src8_data[49].DATAIN +sink_data[49] => src9_data[49].DATAIN +sink_data[50] => src10_data[50].DATAIN +sink_data[50] => src0_data[50].DATAIN +sink_data[50] => src1_data[50].DATAIN +sink_data[50] => src2_data[50].DATAIN +sink_data[50] => src3_data[50].DATAIN +sink_data[50] => src4_data[50].DATAIN +sink_data[50] => src5_data[50].DATAIN +sink_data[50] => src6_data[50].DATAIN +sink_data[50] => src7_data[50].DATAIN +sink_data[50] => src8_data[50].DATAIN +sink_data[50] => src9_data[50].DATAIN +sink_data[51] => src10_data[51].DATAIN +sink_data[51] => src0_data[51].DATAIN +sink_data[51] => src1_data[51].DATAIN +sink_data[51] => src2_data[51].DATAIN +sink_data[51] => src3_data[51].DATAIN +sink_data[51] => src4_data[51].DATAIN +sink_data[51] => src5_data[51].DATAIN +sink_data[51] => src6_data[51].DATAIN +sink_data[51] => src7_data[51].DATAIN +sink_data[51] => src8_data[51].DATAIN +sink_data[51] => src9_data[51].DATAIN +sink_data[52] => src10_data[52].DATAIN +sink_data[52] => src0_data[52].DATAIN +sink_data[52] => src1_data[52].DATAIN +sink_data[52] => src2_data[52].DATAIN +sink_data[52] => src3_data[52].DATAIN +sink_data[52] => src4_data[52].DATAIN +sink_data[52] => src5_data[52].DATAIN +sink_data[52] => src6_data[52].DATAIN +sink_data[52] => src7_data[52].DATAIN +sink_data[52] => src8_data[52].DATAIN +sink_data[52] => src9_data[52].DATAIN +sink_data[53] => src10_data[53].DATAIN +sink_data[53] => src0_data[53].DATAIN +sink_data[53] => src1_data[53].DATAIN +sink_data[53] => src2_data[53].DATAIN +sink_data[53] => src3_data[53].DATAIN +sink_data[53] => src4_data[53].DATAIN +sink_data[53] => src5_data[53].DATAIN +sink_data[53] => src6_data[53].DATAIN +sink_data[53] => src7_data[53].DATAIN +sink_data[53] => src8_data[53].DATAIN +sink_data[53] => src9_data[53].DATAIN +sink_data[54] => src10_data[54].DATAIN +sink_data[54] => src0_data[54].DATAIN +sink_data[54] => src1_data[54].DATAIN +sink_data[54] => src2_data[54].DATAIN +sink_data[54] => src3_data[54].DATAIN +sink_data[54] => src4_data[54].DATAIN +sink_data[54] => src5_data[54].DATAIN +sink_data[54] => src6_data[54].DATAIN +sink_data[54] => src7_data[54].DATAIN +sink_data[54] => src8_data[54].DATAIN +sink_data[54] => src9_data[54].DATAIN +sink_data[55] => src10_data[55].DATAIN +sink_data[55] => src0_data[55].DATAIN +sink_data[55] => src1_data[55].DATAIN +sink_data[55] => src2_data[55].DATAIN +sink_data[55] => src3_data[55].DATAIN +sink_data[55] => src4_data[55].DATAIN +sink_data[55] => src5_data[55].DATAIN +sink_data[55] => src6_data[55].DATAIN +sink_data[55] => src7_data[55].DATAIN +sink_data[55] => src8_data[55].DATAIN +sink_data[55] => src9_data[55].DATAIN +sink_data[56] => src10_data[56].DATAIN +sink_data[56] => src0_data[56].DATAIN +sink_data[56] => src1_data[56].DATAIN +sink_data[56] => src2_data[56].DATAIN +sink_data[56] => src3_data[56].DATAIN +sink_data[56] => src4_data[56].DATAIN +sink_data[56] => src5_data[56].DATAIN +sink_data[56] => src6_data[56].DATAIN +sink_data[56] => src7_data[56].DATAIN +sink_data[56] => src8_data[56].DATAIN +sink_data[56] => src9_data[56].DATAIN +sink_data[57] => src10_data[57].DATAIN +sink_data[57] => src0_data[57].DATAIN +sink_data[57] => src1_data[57].DATAIN +sink_data[57] => src2_data[57].DATAIN +sink_data[57] => src3_data[57].DATAIN +sink_data[57] => src4_data[57].DATAIN +sink_data[57] => src5_data[57].DATAIN +sink_data[57] => src6_data[57].DATAIN +sink_data[57] => src7_data[57].DATAIN +sink_data[57] => src8_data[57].DATAIN +sink_data[57] => src9_data[57].DATAIN +sink_data[58] => src10_data[58].DATAIN +sink_data[58] => src0_data[58].DATAIN +sink_data[58] => src1_data[58].DATAIN +sink_data[58] => src2_data[58].DATAIN +sink_data[58] => src3_data[58].DATAIN +sink_data[58] => src4_data[58].DATAIN +sink_data[58] => src5_data[58].DATAIN +sink_data[58] => src6_data[58].DATAIN +sink_data[58] => src7_data[58].DATAIN +sink_data[58] => src8_data[58].DATAIN +sink_data[58] => src9_data[58].DATAIN +sink_data[59] => src10_data[59].DATAIN +sink_data[59] => src0_data[59].DATAIN +sink_data[59] => src1_data[59].DATAIN +sink_data[59] => src2_data[59].DATAIN +sink_data[59] => src3_data[59].DATAIN +sink_data[59] => src4_data[59].DATAIN +sink_data[59] => src5_data[59].DATAIN +sink_data[59] => src6_data[59].DATAIN +sink_data[59] => src7_data[59].DATAIN +sink_data[59] => src8_data[59].DATAIN +sink_data[59] => src9_data[59].DATAIN +sink_data[60] => src10_data[60].DATAIN +sink_data[60] => src0_data[60].DATAIN +sink_data[60] => src1_data[60].DATAIN +sink_data[60] => src2_data[60].DATAIN +sink_data[60] => src3_data[60].DATAIN +sink_data[60] => src4_data[60].DATAIN +sink_data[60] => src5_data[60].DATAIN +sink_data[60] => src6_data[60].DATAIN +sink_data[60] => src7_data[60].DATAIN +sink_data[60] => src8_data[60].DATAIN +sink_data[60] => src9_data[60].DATAIN +sink_data[61] => src10_data[61].DATAIN +sink_data[61] => src0_data[61].DATAIN +sink_data[61] => src1_data[61].DATAIN +sink_data[61] => src2_data[61].DATAIN +sink_data[61] => src3_data[61].DATAIN +sink_data[61] => src4_data[61].DATAIN +sink_data[61] => src5_data[61].DATAIN +sink_data[61] => src6_data[61].DATAIN +sink_data[61] => src7_data[61].DATAIN +sink_data[61] => src8_data[61].DATAIN +sink_data[61] => src9_data[61].DATAIN +sink_data[62] => src10_data[62].DATAIN +sink_data[62] => src0_data[62].DATAIN +sink_data[62] => src1_data[62].DATAIN +sink_data[62] => src2_data[62].DATAIN +sink_data[62] => src3_data[62].DATAIN +sink_data[62] => src4_data[62].DATAIN +sink_data[62] => src5_data[62].DATAIN +sink_data[62] => src6_data[62].DATAIN +sink_data[62] => src7_data[62].DATAIN +sink_data[62] => src8_data[62].DATAIN +sink_data[62] => src9_data[62].DATAIN +sink_data[63] => src10_data[63].DATAIN +sink_data[63] => src0_data[63].DATAIN +sink_data[63] => src1_data[63].DATAIN +sink_data[63] => src2_data[63].DATAIN +sink_data[63] => src3_data[63].DATAIN +sink_data[63] => src4_data[63].DATAIN +sink_data[63] => src5_data[63].DATAIN +sink_data[63] => src6_data[63].DATAIN +sink_data[63] => src7_data[63].DATAIN +sink_data[63] => src8_data[63].DATAIN +sink_data[63] => src9_data[63].DATAIN +sink_data[64] => src10_data[64].DATAIN +sink_data[64] => src0_data[64].DATAIN +sink_data[64] => src1_data[64].DATAIN +sink_data[64] => src2_data[64].DATAIN +sink_data[64] => src3_data[64].DATAIN +sink_data[64] => src4_data[64].DATAIN +sink_data[64] => src5_data[64].DATAIN +sink_data[64] => src6_data[64].DATAIN +sink_data[64] => src7_data[64].DATAIN +sink_data[64] => src8_data[64].DATAIN +sink_data[64] => src9_data[64].DATAIN +sink_data[65] => src10_data[65].DATAIN +sink_data[65] => src0_data[65].DATAIN +sink_data[65] => src1_data[65].DATAIN +sink_data[65] => src2_data[65].DATAIN +sink_data[65] => src3_data[65].DATAIN +sink_data[65] => src4_data[65].DATAIN +sink_data[65] => src5_data[65].DATAIN +sink_data[65] => src6_data[65].DATAIN +sink_data[65] => src7_data[65].DATAIN +sink_data[65] => src8_data[65].DATAIN +sink_data[65] => src9_data[65].DATAIN +sink_data[66] => src10_data[66].DATAIN +sink_data[66] => src0_data[66].DATAIN +sink_data[66] => src1_data[66].DATAIN +sink_data[66] => src2_data[66].DATAIN +sink_data[66] => src3_data[66].DATAIN +sink_data[66] => src4_data[66].DATAIN +sink_data[66] => src5_data[66].DATAIN +sink_data[66] => src6_data[66].DATAIN +sink_data[66] => src7_data[66].DATAIN +sink_data[66] => src8_data[66].DATAIN +sink_data[66] => src9_data[66].DATAIN +sink_data[67] => src10_data[67].DATAIN +sink_data[67] => src0_data[67].DATAIN +sink_data[67] => src1_data[67].DATAIN +sink_data[67] => src2_data[67].DATAIN +sink_data[67] => src3_data[67].DATAIN +sink_data[67] => src4_data[67].DATAIN +sink_data[67] => src5_data[67].DATAIN +sink_data[67] => src6_data[67].DATAIN +sink_data[67] => src7_data[67].DATAIN +sink_data[67] => src8_data[67].DATAIN +sink_data[67] => src9_data[67].DATAIN +sink_data[68] => src10_data[68].DATAIN +sink_data[68] => src0_data[68].DATAIN +sink_data[68] => src1_data[68].DATAIN +sink_data[68] => src2_data[68].DATAIN +sink_data[68] => src3_data[68].DATAIN +sink_data[68] => src4_data[68].DATAIN +sink_data[68] => src5_data[68].DATAIN +sink_data[68] => src6_data[68].DATAIN +sink_data[68] => src7_data[68].DATAIN +sink_data[68] => src8_data[68].DATAIN +sink_data[68] => src9_data[68].DATAIN +sink_data[69] => src10_data[69].DATAIN +sink_data[69] => src0_data[69].DATAIN +sink_data[69] => src1_data[69].DATAIN +sink_data[69] => src2_data[69].DATAIN +sink_data[69] => src3_data[69].DATAIN +sink_data[69] => src4_data[69].DATAIN +sink_data[69] => src5_data[69].DATAIN +sink_data[69] => src6_data[69].DATAIN +sink_data[69] => src7_data[69].DATAIN +sink_data[69] => src8_data[69].DATAIN +sink_data[69] => src9_data[69].DATAIN +sink_data[70] => src10_data[70].DATAIN +sink_data[70] => src0_data[70].DATAIN +sink_data[70] => src1_data[70].DATAIN +sink_data[70] => src2_data[70].DATAIN +sink_data[70] => src3_data[70].DATAIN +sink_data[70] => src4_data[70].DATAIN +sink_data[70] => src5_data[70].DATAIN +sink_data[70] => src6_data[70].DATAIN +sink_data[70] => src7_data[70].DATAIN +sink_data[70] => src8_data[70].DATAIN +sink_data[70] => src9_data[70].DATAIN +sink_data[71] => src10_data[71].DATAIN +sink_data[71] => src0_data[71].DATAIN +sink_data[71] => src1_data[71].DATAIN +sink_data[71] => src2_data[71].DATAIN +sink_data[71] => src3_data[71].DATAIN +sink_data[71] => src4_data[71].DATAIN +sink_data[71] => src5_data[71].DATAIN +sink_data[71] => src6_data[71].DATAIN +sink_data[71] => src7_data[71].DATAIN +sink_data[71] => src8_data[71].DATAIN +sink_data[71] => src9_data[71].DATAIN +sink_data[72] => src10_data[72].DATAIN +sink_data[72] => src0_data[72].DATAIN +sink_data[72] => src1_data[72].DATAIN +sink_data[72] => src2_data[72].DATAIN +sink_data[72] => src3_data[72].DATAIN +sink_data[72] => src4_data[72].DATAIN +sink_data[72] => src5_data[72].DATAIN +sink_data[72] => src6_data[72].DATAIN +sink_data[72] => src7_data[72].DATAIN +sink_data[72] => src8_data[72].DATAIN +sink_data[72] => src9_data[72].DATAIN +sink_data[73] => src10_data[73].DATAIN +sink_data[73] => src0_data[73].DATAIN +sink_data[73] => src1_data[73].DATAIN +sink_data[73] => src2_data[73].DATAIN +sink_data[73] => src3_data[73].DATAIN +sink_data[73] => src4_data[73].DATAIN +sink_data[73] => src5_data[73].DATAIN +sink_data[73] => src6_data[73].DATAIN +sink_data[73] => src7_data[73].DATAIN +sink_data[73] => src8_data[73].DATAIN +sink_data[73] => src9_data[73].DATAIN +sink_data[74] => src10_data[74].DATAIN +sink_data[74] => src0_data[74].DATAIN +sink_data[74] => src1_data[74].DATAIN +sink_data[74] => src2_data[74].DATAIN +sink_data[74] => src3_data[74].DATAIN +sink_data[74] => src4_data[74].DATAIN +sink_data[74] => src5_data[74].DATAIN +sink_data[74] => src6_data[74].DATAIN +sink_data[74] => src7_data[74].DATAIN +sink_data[74] => src8_data[74].DATAIN +sink_data[74] => src9_data[74].DATAIN +sink_data[75] => src10_data[75].DATAIN +sink_data[75] => src0_data[75].DATAIN +sink_data[75] => src1_data[75].DATAIN +sink_data[75] => src2_data[75].DATAIN +sink_data[75] => src3_data[75].DATAIN +sink_data[75] => src4_data[75].DATAIN +sink_data[75] => src5_data[75].DATAIN +sink_data[75] => src6_data[75].DATAIN +sink_data[75] => src7_data[75].DATAIN +sink_data[75] => src8_data[75].DATAIN +sink_data[75] => src9_data[75].DATAIN +sink_data[76] => src10_data[76].DATAIN +sink_data[76] => src0_data[76].DATAIN +sink_data[76] => src1_data[76].DATAIN +sink_data[76] => src2_data[76].DATAIN +sink_data[76] => src3_data[76].DATAIN +sink_data[76] => src4_data[76].DATAIN +sink_data[76] => src5_data[76].DATAIN +sink_data[76] => src6_data[76].DATAIN +sink_data[76] => src7_data[76].DATAIN +sink_data[76] => src8_data[76].DATAIN +sink_data[76] => src9_data[76].DATAIN +sink_data[77] => src10_data[77].DATAIN +sink_data[77] => src0_data[77].DATAIN +sink_data[77] => src1_data[77].DATAIN +sink_data[77] => src2_data[77].DATAIN +sink_data[77] => src3_data[77].DATAIN +sink_data[77] => src4_data[77].DATAIN +sink_data[77] => src5_data[77].DATAIN +sink_data[77] => src6_data[77].DATAIN +sink_data[77] => src7_data[77].DATAIN +sink_data[77] => src8_data[77].DATAIN +sink_data[77] => src9_data[77].DATAIN +sink_data[78] => src10_data[78].DATAIN +sink_data[78] => src0_data[78].DATAIN +sink_data[78] => src1_data[78].DATAIN +sink_data[78] => src2_data[78].DATAIN +sink_data[78] => src3_data[78].DATAIN +sink_data[78] => src4_data[78].DATAIN +sink_data[78] => src5_data[78].DATAIN +sink_data[78] => src6_data[78].DATAIN +sink_data[78] => src7_data[78].DATAIN +sink_data[78] => src8_data[78].DATAIN +sink_data[78] => src9_data[78].DATAIN +sink_data[79] => src10_data[79].DATAIN +sink_data[79] => src0_data[79].DATAIN +sink_data[79] => src1_data[79].DATAIN +sink_data[79] => src2_data[79].DATAIN +sink_data[79] => src3_data[79].DATAIN +sink_data[79] => src4_data[79].DATAIN +sink_data[79] => src5_data[79].DATAIN +sink_data[79] => src6_data[79].DATAIN +sink_data[79] => src7_data[79].DATAIN +sink_data[79] => src8_data[79].DATAIN +sink_data[79] => src9_data[79].DATAIN +sink_data[80] => src10_data[80].DATAIN +sink_data[80] => src0_data[80].DATAIN +sink_data[80] => src1_data[80].DATAIN +sink_data[80] => src2_data[80].DATAIN +sink_data[80] => src3_data[80].DATAIN +sink_data[80] => src4_data[80].DATAIN +sink_data[80] => src5_data[80].DATAIN +sink_data[80] => src6_data[80].DATAIN +sink_data[80] => src7_data[80].DATAIN +sink_data[80] => src8_data[80].DATAIN +sink_data[80] => src9_data[80].DATAIN +sink_data[81] => src10_data[81].DATAIN +sink_data[81] => src0_data[81].DATAIN +sink_data[81] => src1_data[81].DATAIN +sink_data[81] => src2_data[81].DATAIN +sink_data[81] => src3_data[81].DATAIN +sink_data[81] => src4_data[81].DATAIN +sink_data[81] => src5_data[81].DATAIN +sink_data[81] => src6_data[81].DATAIN +sink_data[81] => src7_data[81].DATAIN +sink_data[81] => src8_data[81].DATAIN +sink_data[81] => src9_data[81].DATAIN +sink_data[82] => src10_data[82].DATAIN +sink_data[82] => src0_data[82].DATAIN +sink_data[82] => src1_data[82].DATAIN +sink_data[82] => src2_data[82].DATAIN +sink_data[82] => src3_data[82].DATAIN +sink_data[82] => src4_data[82].DATAIN +sink_data[82] => src5_data[82].DATAIN +sink_data[82] => src6_data[82].DATAIN +sink_data[82] => src7_data[82].DATAIN +sink_data[82] => src8_data[82].DATAIN +sink_data[82] => src9_data[82].DATAIN +sink_data[83] => src10_data[83].DATAIN +sink_data[83] => src0_data[83].DATAIN +sink_data[83] => src1_data[83].DATAIN +sink_data[83] => src2_data[83].DATAIN +sink_data[83] => src3_data[83].DATAIN +sink_data[83] => src4_data[83].DATAIN +sink_data[83] => src5_data[83].DATAIN +sink_data[83] => src6_data[83].DATAIN +sink_data[83] => src7_data[83].DATAIN +sink_data[83] => src8_data[83].DATAIN +sink_data[83] => src9_data[83].DATAIN +sink_data[84] => src10_data[84].DATAIN +sink_data[84] => src0_data[84].DATAIN +sink_data[84] => src1_data[84].DATAIN +sink_data[84] => src2_data[84].DATAIN +sink_data[84] => src3_data[84].DATAIN +sink_data[84] => src4_data[84].DATAIN +sink_data[84] => src5_data[84].DATAIN +sink_data[84] => src6_data[84].DATAIN +sink_data[84] => src7_data[84].DATAIN +sink_data[84] => src8_data[84].DATAIN +sink_data[84] => src9_data[84].DATAIN +sink_data[85] => src10_data[85].DATAIN +sink_data[85] => src0_data[85].DATAIN +sink_data[85] => src1_data[85].DATAIN +sink_data[85] => src2_data[85].DATAIN +sink_data[85] => src3_data[85].DATAIN +sink_data[85] => src4_data[85].DATAIN +sink_data[85] => src5_data[85].DATAIN +sink_data[85] => src6_data[85].DATAIN +sink_data[85] => src7_data[85].DATAIN +sink_data[85] => src8_data[85].DATAIN +sink_data[85] => src9_data[85].DATAIN +sink_data[86] => src10_data[86].DATAIN +sink_data[86] => src0_data[86].DATAIN +sink_data[86] => src1_data[86].DATAIN +sink_data[86] => src2_data[86].DATAIN +sink_data[86] => src3_data[86].DATAIN +sink_data[86] => src4_data[86].DATAIN +sink_data[86] => src5_data[86].DATAIN +sink_data[86] => src6_data[86].DATAIN +sink_data[86] => src7_data[86].DATAIN +sink_data[86] => src8_data[86].DATAIN +sink_data[86] => src9_data[86].DATAIN +sink_data[87] => src10_data[87].DATAIN +sink_data[87] => src0_data[87].DATAIN +sink_data[87] => src1_data[87].DATAIN +sink_data[87] => src2_data[87].DATAIN +sink_data[87] => src3_data[87].DATAIN +sink_data[87] => src4_data[87].DATAIN +sink_data[87] => src5_data[87].DATAIN +sink_data[87] => src6_data[87].DATAIN +sink_data[87] => src7_data[87].DATAIN +sink_data[87] => src8_data[87].DATAIN +sink_data[87] => src9_data[87].DATAIN +sink_data[88] => src10_data[88].DATAIN +sink_data[88] => src0_data[88].DATAIN +sink_data[88] => src1_data[88].DATAIN +sink_data[88] => src2_data[88].DATAIN +sink_data[88] => src3_data[88].DATAIN +sink_data[88] => src4_data[88].DATAIN +sink_data[88] => src5_data[88].DATAIN +sink_data[88] => src6_data[88].DATAIN +sink_data[88] => src7_data[88].DATAIN +sink_data[88] => src8_data[88].DATAIN +sink_data[88] => src9_data[88].DATAIN +sink_data[89] => src10_data[89].DATAIN +sink_data[89] => src0_data[89].DATAIN +sink_data[89] => src1_data[89].DATAIN +sink_data[89] => src2_data[89].DATAIN +sink_data[89] => src3_data[89].DATAIN +sink_data[89] => src4_data[89].DATAIN +sink_data[89] => src5_data[89].DATAIN +sink_data[89] => src6_data[89].DATAIN +sink_data[89] => src7_data[89].DATAIN +sink_data[89] => src8_data[89].DATAIN +sink_data[89] => src9_data[89].DATAIN +sink_data[90] => src10_data[90].DATAIN +sink_data[90] => src0_data[90].DATAIN +sink_data[90] => src1_data[90].DATAIN +sink_data[90] => src2_data[90].DATAIN +sink_data[90] => src3_data[90].DATAIN +sink_data[90] => src4_data[90].DATAIN +sink_data[90] => src5_data[90].DATAIN +sink_data[90] => src6_data[90].DATAIN +sink_data[90] => src7_data[90].DATAIN +sink_data[90] => src8_data[90].DATAIN +sink_data[90] => src9_data[90].DATAIN +sink_data[91] => src10_data[91].DATAIN +sink_data[91] => src0_data[91].DATAIN +sink_data[91] => src1_data[91].DATAIN +sink_data[91] => src2_data[91].DATAIN +sink_data[91] => src3_data[91].DATAIN +sink_data[91] => src4_data[91].DATAIN +sink_data[91] => src5_data[91].DATAIN +sink_data[91] => src6_data[91].DATAIN +sink_data[91] => src7_data[91].DATAIN +sink_data[91] => src8_data[91].DATAIN +sink_data[91] => src9_data[91].DATAIN +sink_data[92] => src10_data[92].DATAIN +sink_data[92] => src0_data[92].DATAIN +sink_data[92] => src1_data[92].DATAIN +sink_data[92] => src2_data[92].DATAIN +sink_data[92] => src3_data[92].DATAIN +sink_data[92] => src4_data[92].DATAIN +sink_data[92] => src5_data[92].DATAIN +sink_data[92] => src6_data[92].DATAIN +sink_data[92] => src7_data[92].DATAIN +sink_data[92] => src8_data[92].DATAIN +sink_data[92] => src9_data[92].DATAIN +sink_data[93] => src10_data[93].DATAIN +sink_data[93] => src0_data[93].DATAIN +sink_data[93] => src1_data[93].DATAIN +sink_data[93] => src2_data[93].DATAIN +sink_data[93] => src3_data[93].DATAIN +sink_data[93] => src4_data[93].DATAIN +sink_data[93] => src5_data[93].DATAIN +sink_data[93] => src6_data[93].DATAIN +sink_data[93] => src7_data[93].DATAIN +sink_data[93] => src8_data[93].DATAIN +sink_data[93] => src9_data[93].DATAIN +sink_data[94] => src10_data[94].DATAIN +sink_data[94] => src0_data[94].DATAIN +sink_data[94] => src1_data[94].DATAIN +sink_data[94] => src2_data[94].DATAIN +sink_data[94] => src3_data[94].DATAIN +sink_data[94] => src4_data[94].DATAIN +sink_data[94] => src5_data[94].DATAIN +sink_data[94] => src6_data[94].DATAIN +sink_data[94] => src7_data[94].DATAIN +sink_data[94] => src8_data[94].DATAIN +sink_data[94] => src9_data[94].DATAIN +sink_data[95] => src10_data[95].DATAIN +sink_data[95] => src0_data[95].DATAIN +sink_data[95] => src1_data[95].DATAIN +sink_data[95] => src2_data[95].DATAIN +sink_data[95] => src3_data[95].DATAIN +sink_data[95] => src4_data[95].DATAIN +sink_data[95] => src5_data[95].DATAIN +sink_data[95] => src6_data[95].DATAIN +sink_data[95] => src7_data[95].DATAIN +sink_data[95] => src8_data[95].DATAIN +sink_data[95] => src9_data[95].DATAIN +sink_data[96] => src10_data[96].DATAIN +sink_data[96] => src0_data[96].DATAIN +sink_data[96] => src1_data[96].DATAIN +sink_data[96] => src2_data[96].DATAIN +sink_data[96] => src3_data[96].DATAIN +sink_data[96] => src4_data[96].DATAIN +sink_data[96] => src5_data[96].DATAIN +sink_data[96] => src6_data[96].DATAIN +sink_data[96] => src7_data[96].DATAIN +sink_data[96] => src8_data[96].DATAIN +sink_data[96] => src9_data[96].DATAIN +sink_data[97] => src10_data[97].DATAIN +sink_data[97] => src0_data[97].DATAIN +sink_data[97] => src1_data[97].DATAIN +sink_data[97] => src2_data[97].DATAIN +sink_data[97] => src3_data[97].DATAIN +sink_data[97] => src4_data[97].DATAIN +sink_data[97] => src5_data[97].DATAIN +sink_data[97] => src6_data[97].DATAIN +sink_data[97] => src7_data[97].DATAIN +sink_data[97] => src8_data[97].DATAIN +sink_data[97] => src9_data[97].DATAIN +sink_data[98] => src10_data[98].DATAIN +sink_data[98] => src0_data[98].DATAIN +sink_data[98] => src1_data[98].DATAIN +sink_data[98] => src2_data[98].DATAIN +sink_data[98] => src3_data[98].DATAIN +sink_data[98] => src4_data[98].DATAIN +sink_data[98] => src5_data[98].DATAIN +sink_data[98] => src6_data[98].DATAIN +sink_data[98] => src7_data[98].DATAIN +sink_data[98] => src8_data[98].DATAIN +sink_data[98] => src9_data[98].DATAIN +sink_data[99] => src10_data[99].DATAIN +sink_data[99] => src0_data[99].DATAIN +sink_data[99] => src1_data[99].DATAIN +sink_data[99] => src2_data[99].DATAIN +sink_data[99] => src3_data[99].DATAIN +sink_data[99] => src4_data[99].DATAIN +sink_data[99] => src5_data[99].DATAIN +sink_data[99] => src6_data[99].DATAIN +sink_data[99] => src7_data[99].DATAIN +sink_data[99] => src8_data[99].DATAIN +sink_data[99] => src9_data[99].DATAIN +sink_data[100] => src10_data[100].DATAIN +sink_data[100] => src0_data[100].DATAIN +sink_data[100] => src1_data[100].DATAIN +sink_data[100] => src2_data[100].DATAIN +sink_data[100] => src3_data[100].DATAIN +sink_data[100] => src4_data[100].DATAIN +sink_data[100] => src5_data[100].DATAIN +sink_data[100] => src6_data[100].DATAIN +sink_data[100] => src7_data[100].DATAIN +sink_data[100] => src8_data[100].DATAIN +sink_data[100] => src9_data[100].DATAIN +sink_channel[0] => src0_valid.IN1 +sink_channel[0] => sink_ready.IN0 +sink_channel[1] => src1_valid.IN1 +sink_channel[1] => sink_ready.IN0 +sink_channel[2] => src2_valid.IN1 +sink_channel[2] => sink_ready.IN0 +sink_channel[3] => src3_valid.IN1 +sink_channel[3] => sink_ready.IN0 +sink_channel[4] => src4_valid.IN1 +sink_channel[4] => sink_ready.IN0 +sink_channel[5] => src5_valid.IN1 +sink_channel[5] => sink_ready.IN0 +sink_channel[6] => src6_valid.IN1 +sink_channel[6] => sink_ready.IN0 +sink_channel[7] => src7_valid.IN1 +sink_channel[7] => sink_ready.IN0 +sink_channel[8] => src8_valid.IN1 +sink_channel[8] => sink_ready.IN0 +sink_channel[9] => src9_valid.IN1 +sink_channel[9] => sink_ready.IN0 +sink_channel[10] => src10_valid.IN1 +sink_channel[10] => sink_ready.IN0 +sink_startofpacket => src10_startofpacket.DATAIN +sink_startofpacket => src0_startofpacket.DATAIN +sink_startofpacket => src1_startofpacket.DATAIN +sink_startofpacket => src2_startofpacket.DATAIN +sink_startofpacket => src3_startofpacket.DATAIN +sink_startofpacket => src4_startofpacket.DATAIN +sink_startofpacket => src5_startofpacket.DATAIN +sink_startofpacket => src6_startofpacket.DATAIN +sink_startofpacket => src7_startofpacket.DATAIN +sink_startofpacket => src8_startofpacket.DATAIN +sink_startofpacket => src9_startofpacket.DATAIN +sink_endofpacket => src10_endofpacket.DATAIN +sink_endofpacket => src0_endofpacket.DATAIN +sink_endofpacket => src1_endofpacket.DATAIN +sink_endofpacket => src2_endofpacket.DATAIN +sink_endofpacket => src3_endofpacket.DATAIN +sink_endofpacket => src4_endofpacket.DATAIN +sink_endofpacket => src5_endofpacket.DATAIN +sink_endofpacket => src6_endofpacket.DATAIN +sink_endofpacket => src7_endofpacket.DATAIN +sink_endofpacket => src8_endofpacket.DATAIN +sink_endofpacket => src9_endofpacket.DATAIN +sink_ready <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE +src0_valid <= src0_valid.DB_MAX_OUTPUT_PORT_TYPE +src0_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src0_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src0_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src0_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src0_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src0_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src0_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src0_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src0_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src0_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src0_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src0_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src0_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src0_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src0_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src0_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src0_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src0_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src0_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src0_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src0_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src0_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src0_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src0_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src0_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src0_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src0_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src0_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src0_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src0_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src0_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src0_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src0_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src0_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src0_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src0_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src0_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src0_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src0_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src0_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src0_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src0_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src0_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src0_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src0_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src0_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src0_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src0_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src0_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src0_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src0_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src0_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src0_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src0_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src0_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src0_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src0_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src0_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src0_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src0_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src0_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src0_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src0_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src0_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src0_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src0_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src0_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src0_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src0_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src0_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src0_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src0_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src0_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src0_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src0_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src0_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src0_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src0_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src0_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src0_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src0_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src0_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src0_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src0_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src0_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src0_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src0_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src0_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src0_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src0_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src0_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src0_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src0_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src0_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src0_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src0_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src0_data[96] <= sink_data[96].DB_MAX_OUTPUT_PORT_TYPE +src0_data[97] <= sink_data[97].DB_MAX_OUTPUT_PORT_TYPE +src0_data[98] <= sink_data[98].DB_MAX_OUTPUT_PORT_TYPE +src0_data[99] <= sink_data[99].DB_MAX_OUTPUT_PORT_TYPE +src0_data[100] <= sink_data[100].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[0] <= +src0_channel[1] <= +src0_channel[2] <= +src0_channel[3] <= +src0_channel[4] <= +src0_channel[5] <= +src0_channel[6] <= +src0_channel[7] <= +src0_channel[8] <= +src0_channel[9] <= +src0_channel[10] <= +src0_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src0_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src0_ready => sink_ready.IN1 +src1_valid <= src1_valid.DB_MAX_OUTPUT_PORT_TYPE +src1_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src1_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src1_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src1_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src1_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src1_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src1_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src1_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src1_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src1_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src1_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src1_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src1_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src1_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src1_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src1_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src1_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src1_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src1_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src1_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src1_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src1_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src1_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src1_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src1_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src1_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src1_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src1_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src1_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src1_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src1_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src1_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src1_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src1_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src1_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src1_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src1_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src1_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src1_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src1_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src1_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src1_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src1_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src1_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src1_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src1_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src1_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src1_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src1_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src1_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src1_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src1_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src1_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src1_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src1_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src1_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src1_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src1_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src1_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src1_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src1_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src1_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src1_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src1_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src1_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src1_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src1_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src1_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src1_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src1_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src1_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src1_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src1_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src1_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src1_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src1_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src1_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src1_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src1_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src1_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src1_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src1_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src1_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src1_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src1_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src1_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src1_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src1_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src1_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src1_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src1_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src1_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src1_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src1_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src1_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src1_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src1_data[96] <= sink_data[96].DB_MAX_OUTPUT_PORT_TYPE +src1_data[97] <= sink_data[97].DB_MAX_OUTPUT_PORT_TYPE +src1_data[98] <= sink_data[98].DB_MAX_OUTPUT_PORT_TYPE +src1_data[99] <= sink_data[99].DB_MAX_OUTPUT_PORT_TYPE +src1_data[100] <= sink_data[100].DB_MAX_OUTPUT_PORT_TYPE +src1_channel[0] <= +src1_channel[1] <= +src1_channel[2] <= +src1_channel[3] <= +src1_channel[4] <= +src1_channel[5] <= +src1_channel[6] <= +src1_channel[7] <= +src1_channel[8] <= +src1_channel[9] <= +src1_channel[10] <= +src1_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src1_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src1_ready => sink_ready.IN1 +src2_valid <= src2_valid.DB_MAX_OUTPUT_PORT_TYPE +src2_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src2_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src2_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src2_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src2_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src2_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src2_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src2_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src2_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src2_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src2_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src2_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src2_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src2_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src2_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src2_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src2_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src2_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src2_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src2_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src2_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src2_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src2_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src2_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src2_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src2_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src2_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src2_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src2_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src2_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src2_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src2_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src2_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src2_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src2_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src2_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src2_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src2_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src2_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src2_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src2_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src2_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src2_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src2_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src2_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src2_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src2_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src2_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src2_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src2_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src2_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src2_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src2_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src2_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src2_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src2_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src2_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src2_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src2_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src2_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src2_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src2_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src2_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src2_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src2_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src2_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src2_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src2_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src2_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src2_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src2_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src2_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src2_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src2_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src2_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src2_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src2_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src2_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src2_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src2_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src2_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src2_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src2_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src2_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src2_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src2_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src2_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src2_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src2_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src2_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src2_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src2_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src2_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src2_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src2_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src2_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src2_data[96] <= sink_data[96].DB_MAX_OUTPUT_PORT_TYPE +src2_data[97] <= sink_data[97].DB_MAX_OUTPUT_PORT_TYPE +src2_data[98] <= sink_data[98].DB_MAX_OUTPUT_PORT_TYPE +src2_data[99] <= sink_data[99].DB_MAX_OUTPUT_PORT_TYPE +src2_data[100] <= sink_data[100].DB_MAX_OUTPUT_PORT_TYPE +src2_channel[0] <= +src2_channel[1] <= +src2_channel[2] <= +src2_channel[3] <= +src2_channel[4] <= +src2_channel[5] <= +src2_channel[6] <= +src2_channel[7] <= +src2_channel[8] <= +src2_channel[9] <= +src2_channel[10] <= +src2_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src2_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src2_ready => sink_ready.IN1 +src3_valid <= src3_valid.DB_MAX_OUTPUT_PORT_TYPE +src3_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src3_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src3_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src3_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src3_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src3_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src3_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src3_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src3_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src3_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src3_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src3_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src3_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src3_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src3_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src3_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src3_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src3_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src3_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src3_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src3_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src3_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src3_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src3_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src3_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src3_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src3_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src3_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src3_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src3_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src3_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src3_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src3_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src3_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src3_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src3_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src3_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src3_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src3_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src3_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src3_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src3_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src3_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src3_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src3_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src3_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src3_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src3_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src3_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src3_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src3_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src3_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src3_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src3_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src3_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src3_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src3_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src3_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src3_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src3_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src3_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src3_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src3_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src3_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src3_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src3_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src3_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src3_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src3_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src3_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src3_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src3_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src3_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src3_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src3_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src3_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src3_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src3_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src3_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src3_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src3_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src3_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src3_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src3_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src3_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src3_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src3_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src3_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src3_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src3_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src3_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src3_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src3_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src3_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src3_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src3_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src3_data[96] <= sink_data[96].DB_MAX_OUTPUT_PORT_TYPE +src3_data[97] <= sink_data[97].DB_MAX_OUTPUT_PORT_TYPE +src3_data[98] <= sink_data[98].DB_MAX_OUTPUT_PORT_TYPE +src3_data[99] <= sink_data[99].DB_MAX_OUTPUT_PORT_TYPE +src3_data[100] <= sink_data[100].DB_MAX_OUTPUT_PORT_TYPE +src3_channel[0] <= +src3_channel[1] <= +src3_channel[2] <= +src3_channel[3] <= +src3_channel[4] <= +src3_channel[5] <= +src3_channel[6] <= +src3_channel[7] <= +src3_channel[8] <= +src3_channel[9] <= +src3_channel[10] <= +src3_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src3_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src3_ready => sink_ready.IN1 +src4_valid <= src4_valid.DB_MAX_OUTPUT_PORT_TYPE +src4_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src4_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src4_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src4_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src4_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src4_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src4_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src4_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src4_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src4_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src4_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src4_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src4_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src4_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src4_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src4_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src4_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src4_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src4_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src4_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src4_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src4_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src4_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src4_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src4_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src4_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src4_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src4_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src4_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src4_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src4_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src4_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src4_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src4_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src4_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src4_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src4_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src4_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src4_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src4_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src4_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src4_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src4_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src4_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src4_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src4_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src4_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src4_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src4_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src4_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src4_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src4_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src4_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src4_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src4_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src4_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src4_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src4_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src4_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src4_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src4_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src4_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src4_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src4_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src4_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src4_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src4_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src4_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src4_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src4_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src4_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src4_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src4_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src4_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src4_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src4_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src4_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src4_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src4_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src4_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src4_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src4_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src4_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src4_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src4_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src4_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src4_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src4_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src4_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src4_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src4_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src4_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src4_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src4_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src4_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src4_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src4_data[96] <= sink_data[96].DB_MAX_OUTPUT_PORT_TYPE +src4_data[97] <= sink_data[97].DB_MAX_OUTPUT_PORT_TYPE +src4_data[98] <= sink_data[98].DB_MAX_OUTPUT_PORT_TYPE +src4_data[99] <= sink_data[99].DB_MAX_OUTPUT_PORT_TYPE +src4_data[100] <= sink_data[100].DB_MAX_OUTPUT_PORT_TYPE +src4_channel[0] <= +src4_channel[1] <= +src4_channel[2] <= +src4_channel[3] <= +src4_channel[4] <= +src4_channel[5] <= +src4_channel[6] <= +src4_channel[7] <= +src4_channel[8] <= +src4_channel[9] <= +src4_channel[10] <= +src4_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src4_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src4_ready => sink_ready.IN1 +src5_valid <= src5_valid.DB_MAX_OUTPUT_PORT_TYPE +src5_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src5_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src5_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src5_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src5_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src5_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src5_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src5_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src5_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src5_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src5_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src5_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src5_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src5_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src5_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src5_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src5_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src5_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src5_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src5_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src5_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src5_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src5_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src5_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src5_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src5_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src5_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src5_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src5_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src5_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src5_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src5_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src5_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src5_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src5_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src5_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src5_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src5_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src5_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src5_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src5_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src5_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src5_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src5_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src5_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src5_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src5_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src5_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src5_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src5_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src5_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src5_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src5_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src5_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src5_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src5_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src5_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src5_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src5_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src5_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src5_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src5_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src5_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src5_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src5_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src5_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src5_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src5_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src5_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src5_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src5_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src5_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src5_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src5_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src5_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src5_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src5_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src5_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src5_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src5_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src5_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src5_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src5_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src5_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src5_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src5_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src5_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src5_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src5_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src5_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src5_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src5_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src5_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src5_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src5_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src5_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src5_data[96] <= sink_data[96].DB_MAX_OUTPUT_PORT_TYPE +src5_data[97] <= sink_data[97].DB_MAX_OUTPUT_PORT_TYPE +src5_data[98] <= sink_data[98].DB_MAX_OUTPUT_PORT_TYPE +src5_data[99] <= sink_data[99].DB_MAX_OUTPUT_PORT_TYPE +src5_data[100] <= sink_data[100].DB_MAX_OUTPUT_PORT_TYPE +src5_channel[0] <= +src5_channel[1] <= +src5_channel[2] <= +src5_channel[3] <= +src5_channel[4] <= +src5_channel[5] <= +src5_channel[6] <= +src5_channel[7] <= +src5_channel[8] <= +src5_channel[9] <= +src5_channel[10] <= +src5_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src5_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src5_ready => sink_ready.IN1 +src6_valid <= src6_valid.DB_MAX_OUTPUT_PORT_TYPE +src6_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src6_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src6_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src6_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src6_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src6_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src6_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src6_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src6_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src6_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src6_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src6_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src6_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src6_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src6_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src6_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src6_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src6_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src6_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src6_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src6_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src6_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src6_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src6_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src6_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src6_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src6_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src6_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src6_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src6_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src6_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src6_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src6_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src6_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src6_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src6_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src6_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src6_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src6_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src6_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src6_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src6_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src6_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src6_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src6_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src6_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src6_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src6_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src6_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src6_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src6_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src6_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src6_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src6_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src6_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src6_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src6_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src6_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src6_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src6_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src6_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src6_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src6_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src6_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src6_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src6_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src6_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src6_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src6_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src6_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src6_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src6_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src6_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src6_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src6_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src6_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src6_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src6_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src6_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src6_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src6_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src6_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src6_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src6_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src6_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src6_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src6_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src6_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src6_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src6_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src6_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src6_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src6_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src6_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src6_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src6_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src6_data[96] <= sink_data[96].DB_MAX_OUTPUT_PORT_TYPE +src6_data[97] <= sink_data[97].DB_MAX_OUTPUT_PORT_TYPE +src6_data[98] <= sink_data[98].DB_MAX_OUTPUT_PORT_TYPE +src6_data[99] <= sink_data[99].DB_MAX_OUTPUT_PORT_TYPE +src6_data[100] <= sink_data[100].DB_MAX_OUTPUT_PORT_TYPE +src6_channel[0] <= +src6_channel[1] <= +src6_channel[2] <= +src6_channel[3] <= +src6_channel[4] <= +src6_channel[5] <= +src6_channel[6] <= +src6_channel[7] <= +src6_channel[8] <= +src6_channel[9] <= +src6_channel[10] <= +src6_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src6_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src6_ready => sink_ready.IN1 +src7_valid <= src7_valid.DB_MAX_OUTPUT_PORT_TYPE +src7_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src7_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src7_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src7_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src7_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src7_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src7_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src7_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src7_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src7_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src7_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src7_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src7_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src7_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src7_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src7_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src7_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src7_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src7_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src7_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src7_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src7_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src7_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src7_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src7_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src7_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src7_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src7_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src7_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src7_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src7_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src7_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src7_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src7_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src7_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src7_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src7_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src7_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src7_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src7_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src7_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src7_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src7_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src7_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src7_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src7_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src7_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src7_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src7_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src7_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src7_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src7_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src7_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src7_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src7_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src7_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src7_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src7_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src7_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src7_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src7_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src7_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src7_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src7_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src7_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src7_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src7_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src7_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src7_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src7_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src7_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src7_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src7_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src7_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src7_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src7_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src7_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src7_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src7_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src7_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src7_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src7_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src7_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src7_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src7_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src7_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src7_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src7_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src7_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src7_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src7_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src7_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src7_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src7_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src7_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src7_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src7_data[96] <= sink_data[96].DB_MAX_OUTPUT_PORT_TYPE +src7_data[97] <= sink_data[97].DB_MAX_OUTPUT_PORT_TYPE +src7_data[98] <= sink_data[98].DB_MAX_OUTPUT_PORT_TYPE +src7_data[99] <= sink_data[99].DB_MAX_OUTPUT_PORT_TYPE +src7_data[100] <= sink_data[100].DB_MAX_OUTPUT_PORT_TYPE +src7_channel[0] <= +src7_channel[1] <= +src7_channel[2] <= +src7_channel[3] <= +src7_channel[4] <= +src7_channel[5] <= +src7_channel[6] <= +src7_channel[7] <= +src7_channel[8] <= +src7_channel[9] <= +src7_channel[10] <= +src7_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src7_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src7_ready => sink_ready.IN1 +src8_valid <= src8_valid.DB_MAX_OUTPUT_PORT_TYPE +src8_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src8_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src8_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src8_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src8_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src8_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src8_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src8_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src8_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src8_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src8_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src8_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src8_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src8_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src8_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src8_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src8_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src8_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src8_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src8_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src8_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src8_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src8_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src8_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src8_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src8_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src8_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src8_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src8_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src8_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src8_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src8_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src8_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src8_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src8_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src8_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src8_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src8_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src8_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src8_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src8_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src8_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src8_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src8_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src8_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src8_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src8_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src8_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src8_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src8_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src8_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src8_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src8_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src8_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src8_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src8_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src8_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src8_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src8_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src8_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src8_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src8_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src8_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src8_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src8_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src8_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src8_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src8_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src8_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src8_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src8_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src8_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src8_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src8_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src8_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src8_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src8_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src8_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src8_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src8_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src8_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src8_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src8_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src8_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src8_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src8_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src8_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src8_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src8_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src8_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src8_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src8_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src8_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src8_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src8_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src8_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src8_data[96] <= sink_data[96].DB_MAX_OUTPUT_PORT_TYPE +src8_data[97] <= sink_data[97].DB_MAX_OUTPUT_PORT_TYPE +src8_data[98] <= sink_data[98].DB_MAX_OUTPUT_PORT_TYPE +src8_data[99] <= sink_data[99].DB_MAX_OUTPUT_PORT_TYPE +src8_data[100] <= sink_data[100].DB_MAX_OUTPUT_PORT_TYPE +src8_channel[0] <= +src8_channel[1] <= +src8_channel[2] <= +src8_channel[3] <= +src8_channel[4] <= +src8_channel[5] <= +src8_channel[6] <= +src8_channel[7] <= +src8_channel[8] <= +src8_channel[9] <= +src8_channel[10] <= +src8_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src8_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src8_ready => sink_ready.IN1 +src9_valid <= src9_valid.DB_MAX_OUTPUT_PORT_TYPE +src9_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src9_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src9_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src9_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src9_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src9_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src9_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src9_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src9_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src9_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src9_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src9_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src9_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src9_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src9_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src9_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src9_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src9_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src9_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src9_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src9_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src9_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src9_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src9_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src9_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src9_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src9_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src9_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src9_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src9_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src9_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src9_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src9_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src9_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src9_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src9_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src9_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src9_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src9_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src9_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src9_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src9_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src9_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src9_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src9_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src9_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src9_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src9_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src9_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src9_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src9_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src9_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src9_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src9_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src9_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src9_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src9_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src9_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src9_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src9_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src9_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src9_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src9_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src9_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src9_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src9_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src9_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src9_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src9_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src9_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src9_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src9_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src9_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src9_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src9_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src9_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src9_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src9_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src9_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src9_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src9_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src9_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src9_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src9_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src9_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src9_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src9_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src9_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src9_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src9_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src9_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src9_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src9_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src9_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src9_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src9_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src9_data[96] <= sink_data[96].DB_MAX_OUTPUT_PORT_TYPE +src9_data[97] <= sink_data[97].DB_MAX_OUTPUT_PORT_TYPE +src9_data[98] <= sink_data[98].DB_MAX_OUTPUT_PORT_TYPE +src9_data[99] <= sink_data[99].DB_MAX_OUTPUT_PORT_TYPE +src9_data[100] <= sink_data[100].DB_MAX_OUTPUT_PORT_TYPE +src9_channel[0] <= +src9_channel[1] <= +src9_channel[2] <= +src9_channel[3] <= +src9_channel[4] <= +src9_channel[5] <= +src9_channel[6] <= +src9_channel[7] <= +src9_channel[8] <= +src9_channel[9] <= +src9_channel[10] <= +src9_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src9_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src9_ready => sink_ready.IN1 +src10_valid <= src10_valid.DB_MAX_OUTPUT_PORT_TYPE +src10_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src10_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src10_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src10_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src10_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src10_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src10_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src10_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src10_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src10_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src10_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src10_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src10_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src10_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src10_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src10_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src10_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src10_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src10_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src10_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src10_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src10_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src10_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src10_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src10_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src10_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src10_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src10_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src10_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src10_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src10_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src10_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src10_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src10_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src10_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src10_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src10_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src10_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src10_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src10_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src10_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src10_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src10_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src10_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src10_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src10_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src10_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src10_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src10_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src10_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src10_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src10_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src10_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src10_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src10_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src10_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src10_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src10_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src10_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src10_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src10_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src10_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src10_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src10_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src10_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src10_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src10_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src10_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src10_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src10_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src10_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src10_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src10_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src10_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src10_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src10_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src10_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src10_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src10_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src10_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src10_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src10_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src10_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src10_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src10_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src10_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src10_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src10_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src10_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src10_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src10_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src10_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src10_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src10_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src10_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src10_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src10_data[96] <= sink_data[96].DB_MAX_OUTPUT_PORT_TYPE +src10_data[97] <= sink_data[97].DB_MAX_OUTPUT_PORT_TYPE +src10_data[98] <= sink_data[98].DB_MAX_OUTPUT_PORT_TYPE +src10_data[99] <= sink_data[99].DB_MAX_OUTPUT_PORT_TYPE +src10_data[100] <= sink_data[100].DB_MAX_OUTPUT_PORT_TYPE +src10_channel[0] <= +src10_channel[1] <= +src10_channel[2] <= +src10_channel[3] <= +src10_channel[4] <= +src10_channel[5] <= +src10_channel[6] <= +src10_channel[7] <= +src10_channel[8] <= +src10_channel[9] <= +src10_channel[10] <= +src10_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src10_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src10_ready => sink_ready.IN1 +clk => ~NO_FANOUT~ +reset => ~NO_FANOUT~ + + +|de0_nano_system|system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux +sink0_valid => request.IN1 +sink0_valid => src_valid.IN1 +sink0_data[0] => src_payload.IN1 +sink0_data[1] => src_payload.IN1 +sink0_data[2] => src_payload.IN1 +sink0_data[3] => src_payload.IN1 +sink0_data[4] => src_payload.IN1 +sink0_data[5] => src_payload.IN1 +sink0_data[6] => src_payload.IN1 +sink0_data[7] => src_payload.IN1 +sink0_data[8] => src_payload.IN1 +sink0_data[9] => src_payload.IN1 +sink0_data[10] => src_payload.IN1 +sink0_data[11] => src_payload.IN1 +sink0_data[12] => src_payload.IN1 +sink0_data[13] => src_payload.IN1 +sink0_data[14] => src_payload.IN1 +sink0_data[15] => src_payload.IN1 +sink0_data[16] => src_payload.IN1 +sink0_data[17] => src_payload.IN1 +sink0_data[18] => src_payload.IN1 +sink0_data[19] => src_payload.IN1 +sink0_data[20] => src_payload.IN1 +sink0_data[21] => src_payload.IN1 +sink0_data[22] => src_payload.IN1 +sink0_data[23] => src_payload.IN1 +sink0_data[24] => src_payload.IN1 +sink0_data[25] => src_payload.IN1 +sink0_data[26] => src_payload.IN1 +sink0_data[27] => src_payload.IN1 +sink0_data[28] => src_payload.IN1 +sink0_data[29] => src_payload.IN1 +sink0_data[30] => src_payload.IN1 +sink0_data[31] => src_payload.IN1 +sink0_data[32] => src_payload.IN1 +sink0_data[33] => src_payload.IN1 +sink0_data[34] => src_payload.IN1 +sink0_data[35] => src_payload.IN1 +sink0_data[36] => src_payload.IN1 +sink0_data[37] => src_payload.IN1 +sink0_data[38] => src_payload.IN1 +sink0_data[39] => src_payload.IN1 +sink0_data[40] => src_payload.IN1 +sink0_data[41] => src_payload.IN1 +sink0_data[42] => src_payload.IN1 +sink0_data[43] => src_payload.IN1 +sink0_data[44] => src_payload.IN1 +sink0_data[45] => src_payload.IN1 +sink0_data[46] => src_payload.IN1 +sink0_data[47] => src_payload.IN1 +sink0_data[48] => src_payload.IN1 +sink0_data[49] => src_payload.IN1 +sink0_data[50] => src_payload.IN1 +sink0_data[51] => src_payload.IN1 +sink0_data[52] => src_payload.IN1 +sink0_data[53] => src_payload.IN1 +sink0_data[54] => src_payload.IN1 +sink0_data[55] => src_payload.IN1 +sink0_data[56] => src_payload.IN1 +sink0_data[57] => src_payload.IN1 +sink0_data[58] => src_payload.IN1 +sink0_data[59] => src_payload.IN1 +sink0_data[60] => src_payload.IN1 +sink0_data[61] => src_payload.IN1 +sink0_data[62] => src_payload.IN1 +sink0_data[63] => src_payload.IN1 +sink0_data[64] => src_payload.IN1 +sink0_data[65] => src_payload.IN1 +sink0_data[66] => locked.IN1 +sink0_data[66] => src_payload.IN1 +sink0_data[67] => src_payload.IN1 +sink0_data[68] => src_payload.IN1 +sink0_data[69] => src_payload.IN1 +sink0_data[70] => src_payload.IN1 +sink0_data[71] => src_payload.IN1 +sink0_data[72] => src_payload.IN1 +sink0_data[73] => src_payload.IN1 +sink0_data[74] => src_payload.IN1 +sink0_data[75] => src_payload.IN1 +sink0_data[76] => src_payload.IN1 +sink0_data[77] => src_payload.IN1 +sink0_data[78] => src_payload.IN1 +sink0_data[79] => src_payload.IN1 +sink0_data[80] => src_payload.IN1 +sink0_data[81] => src_payload.IN1 +sink0_data[82] => src_payload.IN1 +sink0_data[83] => src_payload.IN1 +sink0_data[84] => src_payload.IN1 +sink0_data[85] => src_payload.IN1 +sink0_data[86] => src_payload.IN1 +sink0_data[87] => src_payload.IN1 +sink0_data[88] => src_payload.IN1 +sink0_data[89] => src_payload.IN1 +sink0_data[90] => src_payload.IN1 +sink0_data[91] => src_payload.IN1 +sink0_data[92] => src_payload.IN1 +sink0_data[93] => src_payload.IN1 +sink0_data[94] => src_payload.IN1 +sink0_data[95] => src_payload.IN1 +sink0_data[96] => src_payload.IN1 +sink0_data[97] => src_payload.IN1 +sink0_data[98] => src_payload.IN1 +sink0_data[99] => src_payload.IN1 +sink0_data[100] => src_payload.IN1 +sink0_channel[0] => src_payload.IN1 +sink0_channel[1] => src_payload.IN1 +sink0_channel[2] => src_payload.IN1 +sink0_channel[3] => src_payload.IN1 +sink0_channel[4] => src_payload.IN1 +sink0_channel[5] => src_payload.IN1 +sink0_channel[6] => src_payload.IN1 +sink0_channel[7] => src_payload.IN1 +sink0_channel[8] => src_payload.IN1 +sink0_channel[9] => src_payload.IN1 +sink0_channel[10] => src_payload.IN1 +sink0_startofpacket => src_payload.IN1 +sink0_endofpacket => src_payload.IN1 +sink0_ready <= sink0_ready.DB_MAX_OUTPUT_PORT_TYPE +sink1_valid => request.IN1 +sink1_valid => src_valid.IN1 +sink1_data[0] => src_payload.IN1 +sink1_data[1] => src_payload.IN1 +sink1_data[2] => src_payload.IN1 +sink1_data[3] => src_payload.IN1 +sink1_data[4] => src_payload.IN1 +sink1_data[5] => src_payload.IN1 +sink1_data[6] => src_payload.IN1 +sink1_data[7] => src_payload.IN1 +sink1_data[8] => src_payload.IN1 +sink1_data[9] => src_payload.IN1 +sink1_data[10] => src_payload.IN1 +sink1_data[11] => src_payload.IN1 +sink1_data[12] => src_payload.IN1 +sink1_data[13] => src_payload.IN1 +sink1_data[14] => src_payload.IN1 +sink1_data[15] => src_payload.IN1 +sink1_data[16] => src_payload.IN1 +sink1_data[17] => src_payload.IN1 +sink1_data[18] => src_payload.IN1 +sink1_data[19] => src_payload.IN1 +sink1_data[20] => src_payload.IN1 +sink1_data[21] => src_payload.IN1 +sink1_data[22] => src_payload.IN1 +sink1_data[23] => src_payload.IN1 +sink1_data[24] => src_payload.IN1 +sink1_data[25] => src_payload.IN1 +sink1_data[26] => src_payload.IN1 +sink1_data[27] => src_payload.IN1 +sink1_data[28] => src_payload.IN1 +sink1_data[29] => src_payload.IN1 +sink1_data[30] => src_payload.IN1 +sink1_data[31] => src_payload.IN1 +sink1_data[32] => src_payload.IN1 +sink1_data[33] => src_payload.IN1 +sink1_data[34] => src_payload.IN1 +sink1_data[35] => src_payload.IN1 +sink1_data[36] => src_payload.IN1 +sink1_data[37] => src_payload.IN1 +sink1_data[38] => src_payload.IN1 +sink1_data[39] => src_payload.IN1 +sink1_data[40] => src_payload.IN1 +sink1_data[41] => src_payload.IN1 +sink1_data[42] => src_payload.IN1 +sink1_data[43] => src_payload.IN1 +sink1_data[44] => src_payload.IN1 +sink1_data[45] => src_payload.IN1 +sink1_data[46] => src_payload.IN1 +sink1_data[47] => src_payload.IN1 +sink1_data[48] => src_payload.IN1 +sink1_data[49] => src_payload.IN1 +sink1_data[50] => src_payload.IN1 +sink1_data[51] => src_payload.IN1 +sink1_data[52] => src_payload.IN1 +sink1_data[53] => src_payload.IN1 +sink1_data[54] => src_payload.IN1 +sink1_data[55] => src_payload.IN1 +sink1_data[56] => src_payload.IN1 +sink1_data[57] => src_payload.IN1 +sink1_data[58] => src_payload.IN1 +sink1_data[59] => src_payload.IN1 +sink1_data[60] => src_payload.IN1 +sink1_data[61] => src_payload.IN1 +sink1_data[62] => src_payload.IN1 +sink1_data[63] => src_payload.IN1 +sink1_data[64] => src_payload.IN1 +sink1_data[65] => src_payload.IN1 +sink1_data[66] => locked.IN1 +sink1_data[66] => src_payload.IN1 +sink1_data[67] => src_payload.IN1 +sink1_data[68] => src_payload.IN1 +sink1_data[69] => src_payload.IN1 +sink1_data[70] => src_payload.IN1 +sink1_data[71] => src_payload.IN1 +sink1_data[72] => src_payload.IN1 +sink1_data[73] => src_payload.IN1 +sink1_data[74] => src_payload.IN1 +sink1_data[75] => src_payload.IN1 +sink1_data[76] => src_payload.IN1 +sink1_data[77] => src_payload.IN1 +sink1_data[78] => src_payload.IN1 +sink1_data[79] => src_payload.IN1 +sink1_data[80] => src_payload.IN1 +sink1_data[81] => src_payload.IN1 +sink1_data[82] => src_payload.IN1 +sink1_data[83] => src_payload.IN1 +sink1_data[84] => src_payload.IN1 +sink1_data[85] => src_payload.IN1 +sink1_data[86] => src_payload.IN1 +sink1_data[87] => src_payload.IN1 +sink1_data[88] => src_payload.IN1 +sink1_data[89] => src_payload.IN1 +sink1_data[90] => src_payload.IN1 +sink1_data[91] => src_payload.IN1 +sink1_data[92] => src_payload.IN1 +sink1_data[93] => src_payload.IN1 +sink1_data[94] => src_payload.IN1 +sink1_data[95] => src_payload.IN1 +sink1_data[96] => src_payload.IN1 +sink1_data[97] => src_payload.IN1 +sink1_data[98] => src_payload.IN1 +sink1_data[99] => src_payload.IN1 +sink1_data[100] => src_payload.IN1 +sink1_channel[0] => src_payload.IN1 +sink1_channel[1] => src_payload.IN1 +sink1_channel[2] => src_payload.IN1 +sink1_channel[3] => src_payload.IN1 +sink1_channel[4] => src_payload.IN1 +sink1_channel[5] => src_payload.IN1 +sink1_channel[6] => src_payload.IN1 +sink1_channel[7] => src_payload.IN1 +sink1_channel[8] => src_payload.IN1 +sink1_channel[9] => src_payload.IN1 +sink1_channel[10] => src_payload.IN1 +sink1_startofpacket => src_payload.IN1 +sink1_endofpacket => src_payload.IN1 +sink1_ready <= sink1_ready.DB_MAX_OUTPUT_PORT_TYPE +src_valid <= src_valid.DB_MAX_OUTPUT_PORT_TYPE +src_data[0] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[1] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[2] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[3] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[4] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[5] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[6] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[7] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[8] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[9] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[10] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[11] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[12] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[13] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[14] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[15] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[16] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[17] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[18] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[19] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[20] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[21] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[22] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[23] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[24] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[25] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[26] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[27] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[28] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[29] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[30] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[31] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[32] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[33] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[34] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[35] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[36] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[37] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[38] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[39] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[40] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[41] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[42] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[43] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[44] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[45] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[46] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[47] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[48] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[49] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[50] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[51] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[52] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[53] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[54] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[55] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[56] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[57] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[58] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[59] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[60] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[61] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[62] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[63] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[64] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[65] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[66] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[67] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[68] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[69] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[70] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[71] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[72] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[73] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[74] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[75] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[76] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[77] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[78] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[79] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[80] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[81] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[82] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[83] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[84] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[85] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[86] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[87] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[88] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[89] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[90] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[91] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[92] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[93] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[94] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[95] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[96] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[97] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[98] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[99] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[100] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[0] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[1] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[2] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[3] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[4] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[5] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[6] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[7] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[8] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[9] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[10] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_startofpacket <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_endofpacket <= src_payload[0].DB_MAX_OUTPUT_PORT_TYPE +src_ready => last_cycle.IN0 +src_ready => sink0_ready.IN1 +src_ready => sink1_ready.IN1 +clk => clk.IN1 +reset => reset.IN1 + + +|de0_nano_system|system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux|altera_merlin_arbitrator:arb +clk => top_priority_reg[0].CLK +clk => top_priority_reg[1].CLK +reset => top_priority_reg[0].PRESET +reset => top_priority_reg[1].ACLR +request[0] => grant_double_vector[0].IN1 +request[0] => grant_double_vector[2].IN1 +request[0] => WideOr0.IN0 +request[0] => _.IN1 +request[0] => _.IN1 +request[1] => grant_double_vector[1].IN1 +request[1] => grant_double_vector[3].IN1 +request[1] => WideOr0.IN1 +request[1] => _.IN1 +request[1] => _.IN1 +grant[0] <= grant.DB_MAX_OUTPUT_PORT_TYPE +grant[1] <= grant.DB_MAX_OUTPUT_PORT_TYPE +increment_top_priority => top_priority_reg.OUTPUTSELECT +increment_top_priority => top_priority_reg.OUTPUTSELECT +save_top_priority => ~NO_FANOUT~ + + +|de0_nano_system|system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder +a[0] => sum.IN0 +a[0] => full_adder.cout[0].IN0 +a[1] => cout.IN0 +a[1] => cout.IN0 +a[2] => cout.IN0 +a[2] => cout.IN0 +a[3] => sum.IN0 +b[0] => sum.IN1 +b[0] => full_adder.cout[0].IN1 +b[1] => cout.IN1 +b[1] => cout.IN1 +b[2] => cout.IN1 +b[2] => cout.IN1 +b[3] => sum.IN1 +sum[0] <= sum.DB_MAX_OUTPUT_PORT_TYPE +sum[1] <= sum.DB_MAX_OUTPUT_PORT_TYPE +sum[2] <= sum.DB_MAX_OUTPUT_PORT_TYPE +sum[3] <= sum.DB_MAX_OUTPUT_PORT_TYPE + + +|de0_nano_system|system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux_001 +sink0_valid => request.IN1 +sink0_valid => src_valid.IN1 +sink0_data[0] => src_payload.IN1 +sink0_data[1] => src_payload.IN1 +sink0_data[2] => src_payload.IN1 +sink0_data[3] => src_payload.IN1 +sink0_data[4] => src_payload.IN1 +sink0_data[5] => src_payload.IN1 +sink0_data[6] => src_payload.IN1 +sink0_data[7] => src_payload.IN1 +sink0_data[8] => src_payload.IN1 +sink0_data[9] => src_payload.IN1 +sink0_data[10] => src_payload.IN1 +sink0_data[11] => src_payload.IN1 +sink0_data[12] => src_payload.IN1 +sink0_data[13] => src_payload.IN1 +sink0_data[14] => src_payload.IN1 +sink0_data[15] => src_payload.IN1 +sink0_data[16] => src_payload.IN1 +sink0_data[17] => src_payload.IN1 +sink0_data[18] => src_payload.IN1 +sink0_data[19] => src_payload.IN1 +sink0_data[20] => src_payload.IN1 +sink0_data[21] => src_payload.IN1 +sink0_data[22] => src_payload.IN1 +sink0_data[23] => src_payload.IN1 +sink0_data[24] => src_payload.IN1 +sink0_data[25] => src_payload.IN1 +sink0_data[26] => src_payload.IN1 +sink0_data[27] => src_payload.IN1 +sink0_data[28] => src_payload.IN1 +sink0_data[29] => src_payload.IN1 +sink0_data[30] => src_payload.IN1 +sink0_data[31] => src_payload.IN1 +sink0_data[32] => src_payload.IN1 +sink0_data[33] => src_payload.IN1 +sink0_data[34] => src_payload.IN1 +sink0_data[35] => src_payload.IN1 +sink0_data[36] => src_payload.IN1 +sink0_data[37] => src_payload.IN1 +sink0_data[38] => src_payload.IN1 +sink0_data[39] => src_payload.IN1 +sink0_data[40] => src_payload.IN1 +sink0_data[41] => src_payload.IN1 +sink0_data[42] => src_payload.IN1 +sink0_data[43] => src_payload.IN1 +sink0_data[44] => src_payload.IN1 +sink0_data[45] => src_payload.IN1 +sink0_data[46] => src_payload.IN1 +sink0_data[47] => src_payload.IN1 +sink0_data[48] => src_payload.IN1 +sink0_data[49] => src_payload.IN1 +sink0_data[50] => src_payload.IN1 +sink0_data[51] => src_payload.IN1 +sink0_data[52] => src_payload.IN1 +sink0_data[53] => src_payload.IN1 +sink0_data[54] => src_payload.IN1 +sink0_data[55] => src_payload.IN1 +sink0_data[56] => src_payload.IN1 +sink0_data[57] => src_payload.IN1 +sink0_data[58] => src_payload.IN1 +sink0_data[59] => src_payload.IN1 +sink0_data[60] => src_payload.IN1 +sink0_data[61] => src_payload.IN1 +sink0_data[62] => src_payload.IN1 +sink0_data[63] => src_payload.IN1 +sink0_data[64] => src_payload.IN1 +sink0_data[65] => src_payload.IN1 +sink0_data[66] => locked.IN1 +sink0_data[66] => src_payload.IN1 +sink0_data[67] => src_payload.IN1 +sink0_data[68] => src_payload.IN1 +sink0_data[69] => src_payload.IN1 +sink0_data[70] => src_payload.IN1 +sink0_data[71] => src_payload.IN1 +sink0_data[72] => src_payload.IN1 +sink0_data[73] => src_payload.IN1 +sink0_data[74] => src_payload.IN1 +sink0_data[75] => src_payload.IN1 +sink0_data[76] => src_payload.IN1 +sink0_data[77] => src_payload.IN1 +sink0_data[78] => src_payload.IN1 +sink0_data[79] => src_payload.IN1 +sink0_data[80] => src_payload.IN1 +sink0_data[81] => src_payload.IN1 +sink0_data[82] => src_payload.IN1 +sink0_data[83] => src_payload.IN1 +sink0_data[84] => src_payload.IN1 +sink0_data[85] => src_payload.IN1 +sink0_data[86] => src_payload.IN1 +sink0_data[87] => src_payload.IN1 +sink0_data[88] => src_payload.IN1 +sink0_data[89] => src_payload.IN1 +sink0_data[90] => src_payload.IN1 +sink0_data[91] => src_payload.IN1 +sink0_data[92] => src_payload.IN1 +sink0_data[93] => src_payload.IN1 +sink0_data[94] => src_payload.IN1 +sink0_data[95] => src_payload.IN1 +sink0_data[96] => src_payload.IN1 +sink0_data[97] => src_payload.IN1 +sink0_data[98] => src_payload.IN1 +sink0_data[99] => src_payload.IN1 +sink0_data[100] => src_payload.IN1 +sink0_channel[0] => src_payload.IN1 +sink0_channel[1] => src_payload.IN1 +sink0_channel[2] => src_payload.IN1 +sink0_channel[3] => src_payload.IN1 +sink0_channel[4] => src_payload.IN1 +sink0_channel[5] => src_payload.IN1 +sink0_channel[6] => src_payload.IN1 +sink0_channel[7] => src_payload.IN1 +sink0_channel[8] => src_payload.IN1 +sink0_channel[9] => src_payload.IN1 +sink0_channel[10] => src_payload.IN1 +sink0_startofpacket => src_payload.IN1 +sink0_endofpacket => src_payload.IN1 +sink0_ready <= sink0_ready.DB_MAX_OUTPUT_PORT_TYPE +sink1_valid => request.IN1 +sink1_valid => src_valid.IN1 +sink1_data[0] => src_payload.IN1 +sink1_data[1] => src_payload.IN1 +sink1_data[2] => src_payload.IN1 +sink1_data[3] => src_payload.IN1 +sink1_data[4] => src_payload.IN1 +sink1_data[5] => src_payload.IN1 +sink1_data[6] => src_payload.IN1 +sink1_data[7] => src_payload.IN1 +sink1_data[8] => src_payload.IN1 +sink1_data[9] => src_payload.IN1 +sink1_data[10] => src_payload.IN1 +sink1_data[11] => src_payload.IN1 +sink1_data[12] => src_payload.IN1 +sink1_data[13] => src_payload.IN1 +sink1_data[14] => src_payload.IN1 +sink1_data[15] => src_payload.IN1 +sink1_data[16] => src_payload.IN1 +sink1_data[17] => src_payload.IN1 +sink1_data[18] => src_payload.IN1 +sink1_data[19] => src_payload.IN1 +sink1_data[20] => src_payload.IN1 +sink1_data[21] => src_payload.IN1 +sink1_data[22] => src_payload.IN1 +sink1_data[23] => src_payload.IN1 +sink1_data[24] => src_payload.IN1 +sink1_data[25] => src_payload.IN1 +sink1_data[26] => src_payload.IN1 +sink1_data[27] => src_payload.IN1 +sink1_data[28] => src_payload.IN1 +sink1_data[29] => src_payload.IN1 +sink1_data[30] => src_payload.IN1 +sink1_data[31] => src_payload.IN1 +sink1_data[32] => src_payload.IN1 +sink1_data[33] => src_payload.IN1 +sink1_data[34] => src_payload.IN1 +sink1_data[35] => src_payload.IN1 +sink1_data[36] => src_payload.IN1 +sink1_data[37] => src_payload.IN1 +sink1_data[38] => src_payload.IN1 +sink1_data[39] => src_payload.IN1 +sink1_data[40] => src_payload.IN1 +sink1_data[41] => src_payload.IN1 +sink1_data[42] => src_payload.IN1 +sink1_data[43] => src_payload.IN1 +sink1_data[44] => src_payload.IN1 +sink1_data[45] => src_payload.IN1 +sink1_data[46] => src_payload.IN1 +sink1_data[47] => src_payload.IN1 +sink1_data[48] => src_payload.IN1 +sink1_data[49] => src_payload.IN1 +sink1_data[50] => src_payload.IN1 +sink1_data[51] => src_payload.IN1 +sink1_data[52] => src_payload.IN1 +sink1_data[53] => src_payload.IN1 +sink1_data[54] => src_payload.IN1 +sink1_data[55] => src_payload.IN1 +sink1_data[56] => src_payload.IN1 +sink1_data[57] => src_payload.IN1 +sink1_data[58] => src_payload.IN1 +sink1_data[59] => src_payload.IN1 +sink1_data[60] => src_payload.IN1 +sink1_data[61] => src_payload.IN1 +sink1_data[62] => src_payload.IN1 +sink1_data[63] => src_payload.IN1 +sink1_data[64] => src_payload.IN1 +sink1_data[65] => src_payload.IN1 +sink1_data[66] => locked.IN1 +sink1_data[66] => src_payload.IN1 +sink1_data[67] => src_payload.IN1 +sink1_data[68] => src_payload.IN1 +sink1_data[69] => src_payload.IN1 +sink1_data[70] => src_payload.IN1 +sink1_data[71] => src_payload.IN1 +sink1_data[72] => src_payload.IN1 +sink1_data[73] => src_payload.IN1 +sink1_data[74] => src_payload.IN1 +sink1_data[75] => src_payload.IN1 +sink1_data[76] => src_payload.IN1 +sink1_data[77] => src_payload.IN1 +sink1_data[78] => src_payload.IN1 +sink1_data[79] => src_payload.IN1 +sink1_data[80] => src_payload.IN1 +sink1_data[81] => src_payload.IN1 +sink1_data[82] => src_payload.IN1 +sink1_data[83] => src_payload.IN1 +sink1_data[84] => src_payload.IN1 +sink1_data[85] => src_payload.IN1 +sink1_data[86] => src_payload.IN1 +sink1_data[87] => src_payload.IN1 +sink1_data[88] => src_payload.IN1 +sink1_data[89] => src_payload.IN1 +sink1_data[90] => src_payload.IN1 +sink1_data[91] => src_payload.IN1 +sink1_data[92] => src_payload.IN1 +sink1_data[93] => src_payload.IN1 +sink1_data[94] => src_payload.IN1 +sink1_data[95] => src_payload.IN1 +sink1_data[96] => src_payload.IN1 +sink1_data[97] => src_payload.IN1 +sink1_data[98] => src_payload.IN1 +sink1_data[99] => src_payload.IN1 +sink1_data[100] => src_payload.IN1 +sink1_channel[0] => src_payload.IN1 +sink1_channel[1] => src_payload.IN1 +sink1_channel[2] => src_payload.IN1 +sink1_channel[3] => src_payload.IN1 +sink1_channel[4] => src_payload.IN1 +sink1_channel[5] => src_payload.IN1 +sink1_channel[6] => src_payload.IN1 +sink1_channel[7] => src_payload.IN1 +sink1_channel[8] => src_payload.IN1 +sink1_channel[9] => src_payload.IN1 +sink1_channel[10] => src_payload.IN1 +sink1_startofpacket => src_payload.IN1 +sink1_endofpacket => src_payload.IN1 +sink1_ready <= sink1_ready.DB_MAX_OUTPUT_PORT_TYPE +src_valid <= src_valid.DB_MAX_OUTPUT_PORT_TYPE +src_data[0] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[1] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[2] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[3] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[4] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[5] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[6] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[7] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[8] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[9] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[10] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[11] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[12] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[13] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[14] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[15] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[16] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[17] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[18] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[19] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[20] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[21] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[22] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[23] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[24] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[25] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[26] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[27] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[28] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[29] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[30] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[31] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[32] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[33] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[34] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[35] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[36] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[37] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[38] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[39] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[40] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[41] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[42] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[43] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[44] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[45] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[46] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[47] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[48] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[49] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[50] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[51] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[52] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[53] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[54] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[55] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[56] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[57] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[58] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[59] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[60] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[61] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[62] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[63] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[64] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[65] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[66] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[67] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[68] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[69] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[70] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[71] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[72] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[73] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[74] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[75] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[76] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[77] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[78] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[79] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[80] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[81] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[82] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[83] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[84] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[85] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[86] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[87] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[88] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[89] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[90] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[91] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[92] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[93] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[94] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[95] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[96] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[97] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[98] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[99] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[100] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[0] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[1] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[2] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[3] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[4] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[5] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[6] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[7] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[8] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[9] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[10] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_startofpacket <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_endofpacket <= src_payload[0].DB_MAX_OUTPUT_PORT_TYPE +src_ready => last_cycle.IN0 +src_ready => sink0_ready.IN1 +src_ready => sink1_ready.IN1 +clk => clk.IN1 +reset => reset.IN1 + + +|de0_nano_system|system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux_001|altera_merlin_arbitrator:arb +clk => top_priority_reg[0].CLK +clk => top_priority_reg[1].CLK +reset => top_priority_reg[0].PRESET +reset => top_priority_reg[1].ACLR +request[0] => grant_double_vector[0].IN1 +request[0] => grant_double_vector[2].IN1 +request[0] => WideOr0.IN0 +request[0] => _.IN1 +request[0] => _.IN1 +request[1] => grant_double_vector[1].IN1 +request[1] => grant_double_vector[3].IN1 +request[1] => WideOr0.IN1 +request[1] => _.IN1 +request[1] => _.IN1 +grant[0] <= grant.DB_MAX_OUTPUT_PORT_TYPE +grant[1] <= grant.DB_MAX_OUTPUT_PORT_TYPE +increment_top_priority => top_priority_reg.OUTPUTSELECT +increment_top_priority => top_priority_reg.OUTPUTSELECT +save_top_priority => ~NO_FANOUT~ + + +|de0_nano_system|system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux_001|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder +a[0] => sum.IN0 +a[0] => full_adder.cout[0].IN0 +a[1] => cout.IN0 +a[1] => cout.IN0 +a[2] => cout.IN0 +a[2] => cout.IN0 +a[3] => sum.IN0 +b[0] => sum.IN1 +b[0] => full_adder.cout[0].IN1 +b[1] => cout.IN1 +b[1] => cout.IN1 +b[2] => cout.IN1 +b[2] => cout.IN1 +b[3] => sum.IN1 +sum[0] <= sum.DB_MAX_OUTPUT_PORT_TYPE +sum[1] <= sum.DB_MAX_OUTPUT_PORT_TYPE +sum[2] <= sum.DB_MAX_OUTPUT_PORT_TYPE +sum[3] <= sum.DB_MAX_OUTPUT_PORT_TYPE + + +|de0_nano_system|system:inst_cpu|system_rsp_xbar_demux:rsp_xbar_demux +sink_valid[0] => src0_valid.IN0 +sink_valid[0] => src1_valid.IN0 +sink_data[0] => src1_data[0].DATAIN +sink_data[0] => src0_data[0].DATAIN +sink_data[1] => src1_data[1].DATAIN +sink_data[1] => src0_data[1].DATAIN +sink_data[2] => src1_data[2].DATAIN +sink_data[2] => src0_data[2].DATAIN +sink_data[3] => src1_data[3].DATAIN +sink_data[3] => src0_data[3].DATAIN +sink_data[4] => src1_data[4].DATAIN +sink_data[4] => src0_data[4].DATAIN +sink_data[5] => src1_data[5].DATAIN +sink_data[5] => src0_data[5].DATAIN +sink_data[6] => src1_data[6].DATAIN +sink_data[6] => src0_data[6].DATAIN +sink_data[7] => src1_data[7].DATAIN +sink_data[7] => src0_data[7].DATAIN +sink_data[8] => src1_data[8].DATAIN +sink_data[8] => src0_data[8].DATAIN +sink_data[9] => src1_data[9].DATAIN +sink_data[9] => src0_data[9].DATAIN +sink_data[10] => src1_data[10].DATAIN +sink_data[10] => src0_data[10].DATAIN +sink_data[11] => src1_data[11].DATAIN +sink_data[11] => src0_data[11].DATAIN +sink_data[12] => src1_data[12].DATAIN +sink_data[12] => src0_data[12].DATAIN +sink_data[13] => src1_data[13].DATAIN +sink_data[13] => src0_data[13].DATAIN +sink_data[14] => src1_data[14].DATAIN +sink_data[14] => src0_data[14].DATAIN +sink_data[15] => src1_data[15].DATAIN +sink_data[15] => src0_data[15].DATAIN +sink_data[16] => src1_data[16].DATAIN +sink_data[16] => src0_data[16].DATAIN +sink_data[17] => src1_data[17].DATAIN +sink_data[17] => src0_data[17].DATAIN +sink_data[18] => src1_data[18].DATAIN +sink_data[18] => src0_data[18].DATAIN +sink_data[19] => src1_data[19].DATAIN +sink_data[19] => src0_data[19].DATAIN +sink_data[20] => src1_data[20].DATAIN +sink_data[20] => src0_data[20].DATAIN +sink_data[21] => src1_data[21].DATAIN +sink_data[21] => src0_data[21].DATAIN +sink_data[22] => src1_data[22].DATAIN +sink_data[22] => src0_data[22].DATAIN +sink_data[23] => src1_data[23].DATAIN +sink_data[23] => src0_data[23].DATAIN +sink_data[24] => src1_data[24].DATAIN +sink_data[24] => src0_data[24].DATAIN +sink_data[25] => src1_data[25].DATAIN +sink_data[25] => src0_data[25].DATAIN +sink_data[26] => src1_data[26].DATAIN +sink_data[26] => src0_data[26].DATAIN +sink_data[27] => src1_data[27].DATAIN +sink_data[27] => src0_data[27].DATAIN +sink_data[28] => src1_data[28].DATAIN +sink_data[28] => src0_data[28].DATAIN +sink_data[29] => src1_data[29].DATAIN +sink_data[29] => src0_data[29].DATAIN +sink_data[30] => src1_data[30].DATAIN +sink_data[30] => src0_data[30].DATAIN +sink_data[31] => src1_data[31].DATAIN +sink_data[31] => src0_data[31].DATAIN +sink_data[32] => src1_data[32].DATAIN +sink_data[32] => src0_data[32].DATAIN +sink_data[33] => src1_data[33].DATAIN +sink_data[33] => src0_data[33].DATAIN +sink_data[34] => src1_data[34].DATAIN +sink_data[34] => src0_data[34].DATAIN +sink_data[35] => src1_data[35].DATAIN +sink_data[35] => src0_data[35].DATAIN +sink_data[36] => src1_data[36].DATAIN +sink_data[36] => src0_data[36].DATAIN +sink_data[37] => src1_data[37].DATAIN +sink_data[37] => src0_data[37].DATAIN +sink_data[38] => src1_data[38].DATAIN +sink_data[38] => src0_data[38].DATAIN +sink_data[39] => src1_data[39].DATAIN +sink_data[39] => src0_data[39].DATAIN +sink_data[40] => src1_data[40].DATAIN +sink_data[40] => src0_data[40].DATAIN +sink_data[41] => src1_data[41].DATAIN +sink_data[41] => src0_data[41].DATAIN +sink_data[42] => src1_data[42].DATAIN +sink_data[42] => src0_data[42].DATAIN +sink_data[43] => src1_data[43].DATAIN +sink_data[43] => src0_data[43].DATAIN +sink_data[44] => src1_data[44].DATAIN +sink_data[44] => src0_data[44].DATAIN +sink_data[45] => src1_data[45].DATAIN +sink_data[45] => src0_data[45].DATAIN +sink_data[46] => src1_data[46].DATAIN +sink_data[46] => src0_data[46].DATAIN +sink_data[47] => src1_data[47].DATAIN +sink_data[47] => src0_data[47].DATAIN +sink_data[48] => src1_data[48].DATAIN +sink_data[48] => src0_data[48].DATAIN +sink_data[49] => src1_data[49].DATAIN +sink_data[49] => src0_data[49].DATAIN +sink_data[50] => src1_data[50].DATAIN +sink_data[50] => src0_data[50].DATAIN +sink_data[51] => src1_data[51].DATAIN +sink_data[51] => src0_data[51].DATAIN +sink_data[52] => src1_data[52].DATAIN +sink_data[52] => src0_data[52].DATAIN +sink_data[53] => src1_data[53].DATAIN +sink_data[53] => src0_data[53].DATAIN +sink_data[54] => src1_data[54].DATAIN +sink_data[54] => src0_data[54].DATAIN +sink_data[55] => src1_data[55].DATAIN +sink_data[55] => src0_data[55].DATAIN +sink_data[56] => src1_data[56].DATAIN +sink_data[56] => src0_data[56].DATAIN +sink_data[57] => src1_data[57].DATAIN +sink_data[57] => src0_data[57].DATAIN +sink_data[58] => src1_data[58].DATAIN +sink_data[58] => src0_data[58].DATAIN +sink_data[59] => src1_data[59].DATAIN +sink_data[59] => src0_data[59].DATAIN +sink_data[60] => src1_data[60].DATAIN +sink_data[60] => src0_data[60].DATAIN +sink_data[61] => src1_data[61].DATAIN +sink_data[61] => src0_data[61].DATAIN +sink_data[62] => src1_data[62].DATAIN +sink_data[62] => src0_data[62].DATAIN +sink_data[63] => src1_data[63].DATAIN +sink_data[63] => src0_data[63].DATAIN +sink_data[64] => src1_data[64].DATAIN +sink_data[64] => src0_data[64].DATAIN +sink_data[65] => src1_data[65].DATAIN +sink_data[65] => src0_data[65].DATAIN +sink_data[66] => src1_data[66].DATAIN +sink_data[66] => src0_data[66].DATAIN +sink_data[67] => src1_data[67].DATAIN +sink_data[67] => src0_data[67].DATAIN +sink_data[68] => src1_data[68].DATAIN +sink_data[68] => src0_data[68].DATAIN +sink_data[69] => src1_data[69].DATAIN +sink_data[69] => src0_data[69].DATAIN +sink_data[70] => src1_data[70].DATAIN +sink_data[70] => src0_data[70].DATAIN +sink_data[71] => src1_data[71].DATAIN +sink_data[71] => src0_data[71].DATAIN +sink_data[72] => src1_data[72].DATAIN +sink_data[72] => src0_data[72].DATAIN +sink_data[73] => src1_data[73].DATAIN +sink_data[73] => src0_data[73].DATAIN +sink_data[74] => src1_data[74].DATAIN +sink_data[74] => src0_data[74].DATAIN +sink_data[75] => src1_data[75].DATAIN +sink_data[75] => src0_data[75].DATAIN +sink_data[76] => src1_data[76].DATAIN +sink_data[76] => src0_data[76].DATAIN +sink_data[77] => src1_data[77].DATAIN +sink_data[77] => src0_data[77].DATAIN +sink_data[78] => src1_data[78].DATAIN +sink_data[78] => src0_data[78].DATAIN +sink_data[79] => src1_data[79].DATAIN +sink_data[79] => src0_data[79].DATAIN +sink_data[80] => src1_data[80].DATAIN +sink_data[80] => src0_data[80].DATAIN +sink_data[81] => src1_data[81].DATAIN +sink_data[81] => src0_data[81].DATAIN +sink_data[82] => src1_data[82].DATAIN +sink_data[82] => src0_data[82].DATAIN +sink_data[83] => src1_data[83].DATAIN +sink_data[83] => src0_data[83].DATAIN +sink_data[84] => src1_data[84].DATAIN +sink_data[84] => src0_data[84].DATAIN +sink_data[85] => src1_data[85].DATAIN +sink_data[85] => src0_data[85].DATAIN +sink_data[86] => src1_data[86].DATAIN +sink_data[86] => src0_data[86].DATAIN +sink_data[87] => src1_data[87].DATAIN +sink_data[87] => src0_data[87].DATAIN +sink_data[88] => src1_data[88].DATAIN +sink_data[88] => src0_data[88].DATAIN +sink_data[89] => src1_data[89].DATAIN +sink_data[89] => src0_data[89].DATAIN +sink_data[90] => src1_data[90].DATAIN +sink_data[90] => src0_data[90].DATAIN +sink_data[91] => src1_data[91].DATAIN +sink_data[91] => src0_data[91].DATAIN +sink_data[92] => src1_data[92].DATAIN +sink_data[92] => src0_data[92].DATAIN +sink_data[93] => src1_data[93].DATAIN +sink_data[93] => src0_data[93].DATAIN +sink_data[94] => src1_data[94].DATAIN +sink_data[94] => src0_data[94].DATAIN +sink_data[95] => src1_data[95].DATAIN +sink_data[95] => src0_data[95].DATAIN +sink_data[96] => src1_data[96].DATAIN +sink_data[96] => src0_data[96].DATAIN +sink_data[97] => src1_data[97].DATAIN +sink_data[97] => src0_data[97].DATAIN +sink_data[98] => src1_data[98].DATAIN +sink_data[98] => src0_data[98].DATAIN +sink_data[99] => src1_data[99].DATAIN +sink_data[99] => src0_data[99].DATAIN +sink_data[100] => src1_data[100].DATAIN +sink_data[100] => src0_data[100].DATAIN +sink_channel[0] => src0_valid.IN1 +sink_channel[0] => sink_ready.IN0 +sink_channel[1] => src1_valid.IN1 +sink_channel[1] => sink_ready.IN0 +sink_channel[2] => src1_channel[0].DATAIN +sink_channel[2] => src0_channel[0].DATAIN +sink_channel[3] => src1_channel[1].DATAIN +sink_channel[3] => src0_channel[1].DATAIN +sink_channel[4] => src1_channel[2].DATAIN +sink_channel[4] => src0_channel[2].DATAIN +sink_channel[5] => src1_channel[3].DATAIN +sink_channel[5] => src0_channel[3].DATAIN +sink_channel[6] => src1_channel[4].DATAIN +sink_channel[6] => src0_channel[4].DATAIN +sink_channel[7] => src1_channel[5].DATAIN +sink_channel[7] => src0_channel[5].DATAIN +sink_channel[8] => src1_channel[6].DATAIN +sink_channel[8] => src0_channel[6].DATAIN +sink_channel[9] => src1_channel[7].DATAIN +sink_channel[9] => src0_channel[7].DATAIN +sink_channel[10] => src1_channel[8].DATAIN +sink_channel[10] => src0_channel[8].DATAIN +sink_startofpacket => src1_startofpacket.DATAIN +sink_startofpacket => src0_startofpacket.DATAIN +sink_endofpacket => src1_endofpacket.DATAIN +sink_endofpacket => src0_endofpacket.DATAIN +sink_ready <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE +src0_valid <= src0_valid.DB_MAX_OUTPUT_PORT_TYPE +src0_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src0_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src0_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src0_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src0_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src0_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src0_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src0_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src0_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src0_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src0_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src0_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src0_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src0_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src0_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src0_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src0_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src0_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src0_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src0_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src0_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src0_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src0_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src0_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src0_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src0_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src0_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src0_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src0_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src0_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src0_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src0_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src0_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src0_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src0_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src0_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src0_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src0_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src0_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src0_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src0_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src0_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src0_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src0_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src0_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src0_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src0_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src0_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src0_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src0_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src0_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src0_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src0_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src0_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src0_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src0_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src0_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src0_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src0_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src0_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src0_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src0_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src0_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src0_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src0_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src0_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src0_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src0_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src0_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src0_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src0_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src0_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src0_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src0_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src0_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src0_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src0_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src0_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src0_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src0_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src0_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src0_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src0_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src0_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src0_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src0_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src0_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src0_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src0_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src0_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src0_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src0_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src0_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src0_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src0_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src0_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src0_data[96] <= sink_data[96].DB_MAX_OUTPUT_PORT_TYPE +src0_data[97] <= sink_data[97].DB_MAX_OUTPUT_PORT_TYPE +src0_data[98] <= sink_data[98].DB_MAX_OUTPUT_PORT_TYPE +src0_data[99] <= sink_data[99].DB_MAX_OUTPUT_PORT_TYPE +src0_data[100] <= sink_data[100].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[0] <= sink_channel[2].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[1] <= sink_channel[3].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[2] <= sink_channel[4].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[3] <= sink_channel[5].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[4] <= sink_channel[6].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[5] <= sink_channel[7].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[6] <= sink_channel[8].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[7] <= sink_channel[9].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[8] <= sink_channel[10].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[9] <= +src0_channel[10] <= +src0_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src0_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src0_ready => sink_ready.IN1 +src1_valid <= src1_valid.DB_MAX_OUTPUT_PORT_TYPE +src1_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src1_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src1_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src1_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src1_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src1_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src1_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src1_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src1_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src1_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src1_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src1_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src1_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src1_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src1_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src1_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src1_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src1_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src1_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src1_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src1_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src1_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src1_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src1_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src1_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src1_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src1_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src1_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src1_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src1_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src1_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src1_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src1_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src1_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src1_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src1_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src1_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src1_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src1_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src1_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src1_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src1_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src1_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src1_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src1_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src1_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src1_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src1_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src1_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src1_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src1_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src1_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src1_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src1_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src1_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src1_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src1_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src1_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src1_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src1_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src1_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src1_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src1_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src1_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src1_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src1_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src1_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src1_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src1_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src1_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src1_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src1_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src1_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src1_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src1_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src1_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src1_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src1_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src1_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src1_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src1_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src1_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src1_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src1_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src1_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src1_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src1_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src1_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src1_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src1_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src1_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src1_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src1_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src1_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src1_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src1_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src1_data[96] <= sink_data[96].DB_MAX_OUTPUT_PORT_TYPE +src1_data[97] <= sink_data[97].DB_MAX_OUTPUT_PORT_TYPE +src1_data[98] <= sink_data[98].DB_MAX_OUTPUT_PORT_TYPE +src1_data[99] <= sink_data[99].DB_MAX_OUTPUT_PORT_TYPE +src1_data[100] <= sink_data[100].DB_MAX_OUTPUT_PORT_TYPE +src1_channel[0] <= sink_channel[2].DB_MAX_OUTPUT_PORT_TYPE +src1_channel[1] <= sink_channel[3].DB_MAX_OUTPUT_PORT_TYPE +src1_channel[2] <= sink_channel[4].DB_MAX_OUTPUT_PORT_TYPE +src1_channel[3] <= sink_channel[5].DB_MAX_OUTPUT_PORT_TYPE +src1_channel[4] <= sink_channel[6].DB_MAX_OUTPUT_PORT_TYPE +src1_channel[5] <= sink_channel[7].DB_MAX_OUTPUT_PORT_TYPE +src1_channel[6] <= sink_channel[8].DB_MAX_OUTPUT_PORT_TYPE +src1_channel[7] <= sink_channel[9].DB_MAX_OUTPUT_PORT_TYPE +src1_channel[8] <= sink_channel[10].DB_MAX_OUTPUT_PORT_TYPE +src1_channel[9] <= +src1_channel[10] <= +src1_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src1_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src1_ready => sink_ready.IN1 +clk => ~NO_FANOUT~ +reset => ~NO_FANOUT~ + + +|de0_nano_system|system:inst_cpu|system_rsp_xbar_demux:rsp_xbar_demux_001 +sink_valid[0] => src0_valid.IN0 +sink_valid[0] => src1_valid.IN0 +sink_data[0] => src1_data[0].DATAIN +sink_data[0] => src0_data[0].DATAIN +sink_data[1] => src1_data[1].DATAIN +sink_data[1] => src0_data[1].DATAIN +sink_data[2] => src1_data[2].DATAIN +sink_data[2] => src0_data[2].DATAIN +sink_data[3] => src1_data[3].DATAIN +sink_data[3] => src0_data[3].DATAIN +sink_data[4] => src1_data[4].DATAIN +sink_data[4] => src0_data[4].DATAIN +sink_data[5] => src1_data[5].DATAIN +sink_data[5] => src0_data[5].DATAIN +sink_data[6] => src1_data[6].DATAIN +sink_data[6] => src0_data[6].DATAIN +sink_data[7] => src1_data[7].DATAIN +sink_data[7] => src0_data[7].DATAIN +sink_data[8] => src1_data[8].DATAIN +sink_data[8] => src0_data[8].DATAIN +sink_data[9] => src1_data[9].DATAIN +sink_data[9] => src0_data[9].DATAIN +sink_data[10] => src1_data[10].DATAIN +sink_data[10] => src0_data[10].DATAIN +sink_data[11] => src1_data[11].DATAIN +sink_data[11] => src0_data[11].DATAIN +sink_data[12] => src1_data[12].DATAIN +sink_data[12] => src0_data[12].DATAIN +sink_data[13] => src1_data[13].DATAIN +sink_data[13] => src0_data[13].DATAIN +sink_data[14] => src1_data[14].DATAIN +sink_data[14] => src0_data[14].DATAIN +sink_data[15] => src1_data[15].DATAIN +sink_data[15] => src0_data[15].DATAIN +sink_data[16] => src1_data[16].DATAIN +sink_data[16] => src0_data[16].DATAIN +sink_data[17] => src1_data[17].DATAIN +sink_data[17] => src0_data[17].DATAIN +sink_data[18] => src1_data[18].DATAIN +sink_data[18] => src0_data[18].DATAIN +sink_data[19] => src1_data[19].DATAIN +sink_data[19] => src0_data[19].DATAIN +sink_data[20] => src1_data[20].DATAIN +sink_data[20] => src0_data[20].DATAIN +sink_data[21] => src1_data[21].DATAIN +sink_data[21] => src0_data[21].DATAIN +sink_data[22] => src1_data[22].DATAIN +sink_data[22] => src0_data[22].DATAIN +sink_data[23] => src1_data[23].DATAIN +sink_data[23] => src0_data[23].DATAIN +sink_data[24] => src1_data[24].DATAIN +sink_data[24] => src0_data[24].DATAIN +sink_data[25] => src1_data[25].DATAIN +sink_data[25] => src0_data[25].DATAIN +sink_data[26] => src1_data[26].DATAIN +sink_data[26] => src0_data[26].DATAIN +sink_data[27] => src1_data[27].DATAIN +sink_data[27] => src0_data[27].DATAIN +sink_data[28] => src1_data[28].DATAIN +sink_data[28] => src0_data[28].DATAIN +sink_data[29] => src1_data[29].DATAIN +sink_data[29] => src0_data[29].DATAIN +sink_data[30] => src1_data[30].DATAIN +sink_data[30] => src0_data[30].DATAIN +sink_data[31] => src1_data[31].DATAIN +sink_data[31] => src0_data[31].DATAIN +sink_data[32] => src1_data[32].DATAIN +sink_data[32] => src0_data[32].DATAIN +sink_data[33] => src1_data[33].DATAIN +sink_data[33] => src0_data[33].DATAIN +sink_data[34] => src1_data[34].DATAIN +sink_data[34] => src0_data[34].DATAIN +sink_data[35] => src1_data[35].DATAIN +sink_data[35] => src0_data[35].DATAIN +sink_data[36] => src1_data[36].DATAIN +sink_data[36] => src0_data[36].DATAIN +sink_data[37] => src1_data[37].DATAIN +sink_data[37] => src0_data[37].DATAIN +sink_data[38] => src1_data[38].DATAIN +sink_data[38] => src0_data[38].DATAIN +sink_data[39] => src1_data[39].DATAIN +sink_data[39] => src0_data[39].DATAIN +sink_data[40] => src1_data[40].DATAIN +sink_data[40] => src0_data[40].DATAIN +sink_data[41] => src1_data[41].DATAIN +sink_data[41] => src0_data[41].DATAIN +sink_data[42] => src1_data[42].DATAIN +sink_data[42] => src0_data[42].DATAIN +sink_data[43] => src1_data[43].DATAIN +sink_data[43] => src0_data[43].DATAIN +sink_data[44] => src1_data[44].DATAIN +sink_data[44] => src0_data[44].DATAIN +sink_data[45] => src1_data[45].DATAIN +sink_data[45] => src0_data[45].DATAIN +sink_data[46] => src1_data[46].DATAIN +sink_data[46] => src0_data[46].DATAIN +sink_data[47] => src1_data[47].DATAIN +sink_data[47] => src0_data[47].DATAIN +sink_data[48] => src1_data[48].DATAIN +sink_data[48] => src0_data[48].DATAIN +sink_data[49] => src1_data[49].DATAIN +sink_data[49] => src0_data[49].DATAIN +sink_data[50] => src1_data[50].DATAIN +sink_data[50] => src0_data[50].DATAIN +sink_data[51] => src1_data[51].DATAIN +sink_data[51] => src0_data[51].DATAIN +sink_data[52] => src1_data[52].DATAIN +sink_data[52] => src0_data[52].DATAIN +sink_data[53] => src1_data[53].DATAIN +sink_data[53] => src0_data[53].DATAIN +sink_data[54] => src1_data[54].DATAIN +sink_data[54] => src0_data[54].DATAIN +sink_data[55] => src1_data[55].DATAIN +sink_data[55] => src0_data[55].DATAIN +sink_data[56] => src1_data[56].DATAIN +sink_data[56] => src0_data[56].DATAIN +sink_data[57] => src1_data[57].DATAIN +sink_data[57] => src0_data[57].DATAIN +sink_data[58] => src1_data[58].DATAIN +sink_data[58] => src0_data[58].DATAIN +sink_data[59] => src1_data[59].DATAIN +sink_data[59] => src0_data[59].DATAIN +sink_data[60] => src1_data[60].DATAIN +sink_data[60] => src0_data[60].DATAIN +sink_data[61] => src1_data[61].DATAIN +sink_data[61] => src0_data[61].DATAIN +sink_data[62] => src1_data[62].DATAIN +sink_data[62] => src0_data[62].DATAIN +sink_data[63] => src1_data[63].DATAIN +sink_data[63] => src0_data[63].DATAIN +sink_data[64] => src1_data[64].DATAIN +sink_data[64] => src0_data[64].DATAIN +sink_data[65] => src1_data[65].DATAIN +sink_data[65] => src0_data[65].DATAIN +sink_data[66] => src1_data[66].DATAIN +sink_data[66] => src0_data[66].DATAIN +sink_data[67] => src1_data[67].DATAIN +sink_data[67] => src0_data[67].DATAIN +sink_data[68] => src1_data[68].DATAIN +sink_data[68] => src0_data[68].DATAIN +sink_data[69] => src1_data[69].DATAIN +sink_data[69] => src0_data[69].DATAIN +sink_data[70] => src1_data[70].DATAIN +sink_data[70] => src0_data[70].DATAIN +sink_data[71] => src1_data[71].DATAIN +sink_data[71] => src0_data[71].DATAIN +sink_data[72] => src1_data[72].DATAIN +sink_data[72] => src0_data[72].DATAIN +sink_data[73] => src1_data[73].DATAIN +sink_data[73] => src0_data[73].DATAIN +sink_data[74] => src1_data[74].DATAIN +sink_data[74] => src0_data[74].DATAIN +sink_data[75] => src1_data[75].DATAIN +sink_data[75] => src0_data[75].DATAIN +sink_data[76] => src1_data[76].DATAIN +sink_data[76] => src0_data[76].DATAIN +sink_data[77] => src1_data[77].DATAIN +sink_data[77] => src0_data[77].DATAIN +sink_data[78] => src1_data[78].DATAIN +sink_data[78] => src0_data[78].DATAIN +sink_data[79] => src1_data[79].DATAIN +sink_data[79] => src0_data[79].DATAIN +sink_data[80] => src1_data[80].DATAIN +sink_data[80] => src0_data[80].DATAIN +sink_data[81] => src1_data[81].DATAIN +sink_data[81] => src0_data[81].DATAIN +sink_data[82] => src1_data[82].DATAIN +sink_data[82] => src0_data[82].DATAIN +sink_data[83] => src1_data[83].DATAIN +sink_data[83] => src0_data[83].DATAIN +sink_data[84] => src1_data[84].DATAIN +sink_data[84] => src0_data[84].DATAIN +sink_data[85] => src1_data[85].DATAIN +sink_data[85] => src0_data[85].DATAIN +sink_data[86] => src1_data[86].DATAIN +sink_data[86] => src0_data[86].DATAIN +sink_data[87] => src1_data[87].DATAIN +sink_data[87] => src0_data[87].DATAIN +sink_data[88] => src1_data[88].DATAIN +sink_data[88] => src0_data[88].DATAIN +sink_data[89] => src1_data[89].DATAIN +sink_data[89] => src0_data[89].DATAIN +sink_data[90] => src1_data[90].DATAIN +sink_data[90] => src0_data[90].DATAIN +sink_data[91] => src1_data[91].DATAIN +sink_data[91] => src0_data[91].DATAIN +sink_data[92] => src1_data[92].DATAIN +sink_data[92] => src0_data[92].DATAIN +sink_data[93] => src1_data[93].DATAIN +sink_data[93] => src0_data[93].DATAIN +sink_data[94] => src1_data[94].DATAIN +sink_data[94] => src0_data[94].DATAIN +sink_data[95] => src1_data[95].DATAIN +sink_data[95] => src0_data[95].DATAIN +sink_data[96] => src1_data[96].DATAIN +sink_data[96] => src0_data[96].DATAIN +sink_data[97] => src1_data[97].DATAIN +sink_data[97] => src0_data[97].DATAIN +sink_data[98] => src1_data[98].DATAIN +sink_data[98] => src0_data[98].DATAIN +sink_data[99] => src1_data[99].DATAIN +sink_data[99] => src0_data[99].DATAIN +sink_data[100] => src1_data[100].DATAIN +sink_data[100] => src0_data[100].DATAIN +sink_channel[0] => src0_valid.IN1 +sink_channel[0] => sink_ready.IN0 +sink_channel[1] => src1_valid.IN1 +sink_channel[1] => sink_ready.IN0 +sink_channel[2] => src1_channel[0].DATAIN +sink_channel[2] => src0_channel[0].DATAIN +sink_channel[3] => src1_channel[1].DATAIN +sink_channel[3] => src0_channel[1].DATAIN +sink_channel[4] => src1_channel[2].DATAIN +sink_channel[4] => src0_channel[2].DATAIN +sink_channel[5] => src1_channel[3].DATAIN +sink_channel[5] => src0_channel[3].DATAIN +sink_channel[6] => src1_channel[4].DATAIN +sink_channel[6] => src0_channel[4].DATAIN +sink_channel[7] => src1_channel[5].DATAIN +sink_channel[7] => src0_channel[5].DATAIN +sink_channel[8] => src1_channel[6].DATAIN +sink_channel[8] => src0_channel[6].DATAIN +sink_channel[9] => src1_channel[7].DATAIN +sink_channel[9] => src0_channel[7].DATAIN +sink_channel[10] => src1_channel[8].DATAIN +sink_channel[10] => src0_channel[8].DATAIN +sink_startofpacket => src1_startofpacket.DATAIN +sink_startofpacket => src0_startofpacket.DATAIN +sink_endofpacket => src1_endofpacket.DATAIN +sink_endofpacket => src0_endofpacket.DATAIN +sink_ready <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE +src0_valid <= src0_valid.DB_MAX_OUTPUT_PORT_TYPE +src0_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src0_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src0_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src0_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src0_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src0_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src0_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src0_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src0_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src0_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src0_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src0_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src0_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src0_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src0_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src0_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src0_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src0_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src0_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src0_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src0_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src0_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src0_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src0_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src0_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src0_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src0_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src0_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src0_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src0_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src0_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src0_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src0_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src0_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src0_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src0_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src0_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src0_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src0_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src0_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src0_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src0_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src0_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src0_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src0_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src0_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src0_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src0_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src0_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src0_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src0_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src0_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src0_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src0_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src0_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src0_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src0_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src0_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src0_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src0_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src0_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src0_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src0_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src0_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src0_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src0_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src0_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src0_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src0_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src0_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src0_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src0_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src0_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src0_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src0_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src0_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src0_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src0_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src0_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src0_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src0_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src0_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src0_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src0_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src0_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src0_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src0_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src0_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src0_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src0_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src0_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src0_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src0_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src0_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src0_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src0_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src0_data[96] <= sink_data[96].DB_MAX_OUTPUT_PORT_TYPE +src0_data[97] <= sink_data[97].DB_MAX_OUTPUT_PORT_TYPE +src0_data[98] <= sink_data[98].DB_MAX_OUTPUT_PORT_TYPE +src0_data[99] <= sink_data[99].DB_MAX_OUTPUT_PORT_TYPE +src0_data[100] <= sink_data[100].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[0] <= sink_channel[2].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[1] <= sink_channel[3].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[2] <= sink_channel[4].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[3] <= sink_channel[5].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[4] <= sink_channel[6].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[5] <= sink_channel[7].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[6] <= sink_channel[8].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[7] <= sink_channel[9].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[8] <= sink_channel[10].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[9] <= +src0_channel[10] <= +src0_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src0_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src0_ready => sink_ready.IN1 +src1_valid <= src1_valid.DB_MAX_OUTPUT_PORT_TYPE +src1_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src1_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src1_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src1_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src1_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src1_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src1_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src1_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src1_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src1_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src1_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src1_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src1_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src1_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src1_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src1_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src1_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src1_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src1_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src1_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src1_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src1_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src1_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src1_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src1_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src1_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src1_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src1_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src1_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src1_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src1_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src1_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src1_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src1_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src1_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src1_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src1_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src1_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src1_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src1_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src1_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src1_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src1_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src1_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src1_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src1_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src1_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src1_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src1_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src1_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src1_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src1_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src1_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src1_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src1_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src1_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src1_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src1_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src1_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src1_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src1_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src1_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src1_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src1_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src1_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src1_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src1_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src1_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src1_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src1_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src1_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src1_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src1_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src1_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src1_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src1_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src1_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src1_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src1_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src1_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src1_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src1_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src1_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src1_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src1_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src1_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src1_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src1_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src1_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src1_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src1_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src1_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src1_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src1_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src1_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src1_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src1_data[96] <= sink_data[96].DB_MAX_OUTPUT_PORT_TYPE +src1_data[97] <= sink_data[97].DB_MAX_OUTPUT_PORT_TYPE +src1_data[98] <= sink_data[98].DB_MAX_OUTPUT_PORT_TYPE +src1_data[99] <= sink_data[99].DB_MAX_OUTPUT_PORT_TYPE +src1_data[100] <= sink_data[100].DB_MAX_OUTPUT_PORT_TYPE +src1_channel[0] <= sink_channel[2].DB_MAX_OUTPUT_PORT_TYPE +src1_channel[1] <= sink_channel[3].DB_MAX_OUTPUT_PORT_TYPE +src1_channel[2] <= sink_channel[4].DB_MAX_OUTPUT_PORT_TYPE +src1_channel[3] <= sink_channel[5].DB_MAX_OUTPUT_PORT_TYPE +src1_channel[4] <= sink_channel[6].DB_MAX_OUTPUT_PORT_TYPE +src1_channel[5] <= sink_channel[7].DB_MAX_OUTPUT_PORT_TYPE +src1_channel[6] <= sink_channel[8].DB_MAX_OUTPUT_PORT_TYPE +src1_channel[7] <= sink_channel[9].DB_MAX_OUTPUT_PORT_TYPE +src1_channel[8] <= sink_channel[10].DB_MAX_OUTPUT_PORT_TYPE +src1_channel[9] <= +src1_channel[10] <= +src1_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src1_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src1_ready => sink_ready.IN1 +clk => ~NO_FANOUT~ +reset => ~NO_FANOUT~ + + +|de0_nano_system|system:inst_cpu|system_rsp_xbar_demux_002:rsp_xbar_demux_002 +sink_valid[0] => src0_valid.IN0 +sink_data[0] => src0_data[0].DATAIN +sink_data[1] => src0_data[1].DATAIN +sink_data[2] => src0_data[2].DATAIN +sink_data[3] => src0_data[3].DATAIN +sink_data[4] => src0_data[4].DATAIN +sink_data[5] => src0_data[5].DATAIN +sink_data[6] => src0_data[6].DATAIN +sink_data[7] => src0_data[7].DATAIN +sink_data[8] => src0_data[8].DATAIN +sink_data[9] => src0_data[9].DATAIN +sink_data[10] => src0_data[10].DATAIN +sink_data[11] => src0_data[11].DATAIN +sink_data[12] => src0_data[12].DATAIN +sink_data[13] => src0_data[13].DATAIN +sink_data[14] => src0_data[14].DATAIN +sink_data[15] => src0_data[15].DATAIN +sink_data[16] => src0_data[16].DATAIN +sink_data[17] => src0_data[17].DATAIN +sink_data[18] => src0_data[18].DATAIN +sink_data[19] => src0_data[19].DATAIN +sink_data[20] => src0_data[20].DATAIN +sink_data[21] => src0_data[21].DATAIN +sink_data[22] => src0_data[22].DATAIN +sink_data[23] => src0_data[23].DATAIN +sink_data[24] => src0_data[24].DATAIN +sink_data[25] => src0_data[25].DATAIN +sink_data[26] => src0_data[26].DATAIN +sink_data[27] => src0_data[27].DATAIN +sink_data[28] => src0_data[28].DATAIN +sink_data[29] => src0_data[29].DATAIN +sink_data[30] => src0_data[30].DATAIN +sink_data[31] => src0_data[31].DATAIN +sink_data[32] => src0_data[32].DATAIN +sink_data[33] => src0_data[33].DATAIN +sink_data[34] => src0_data[34].DATAIN +sink_data[35] => src0_data[35].DATAIN +sink_data[36] => src0_data[36].DATAIN +sink_data[37] => src0_data[37].DATAIN +sink_data[38] => src0_data[38].DATAIN +sink_data[39] => src0_data[39].DATAIN +sink_data[40] => src0_data[40].DATAIN +sink_data[41] => src0_data[41].DATAIN +sink_data[42] => src0_data[42].DATAIN +sink_data[43] => src0_data[43].DATAIN +sink_data[44] => src0_data[44].DATAIN +sink_data[45] => src0_data[45].DATAIN +sink_data[46] => src0_data[46].DATAIN +sink_data[47] => src0_data[47].DATAIN +sink_data[48] => src0_data[48].DATAIN +sink_data[49] => src0_data[49].DATAIN +sink_data[50] => src0_data[50].DATAIN +sink_data[51] => src0_data[51].DATAIN +sink_data[52] => src0_data[52].DATAIN +sink_data[53] => src0_data[53].DATAIN +sink_data[54] => src0_data[54].DATAIN +sink_data[55] => src0_data[55].DATAIN +sink_data[56] => src0_data[56].DATAIN +sink_data[57] => src0_data[57].DATAIN +sink_data[58] => src0_data[58].DATAIN +sink_data[59] => src0_data[59].DATAIN +sink_data[60] => src0_data[60].DATAIN +sink_data[61] => src0_data[61].DATAIN +sink_data[62] => src0_data[62].DATAIN +sink_data[63] => src0_data[63].DATAIN +sink_data[64] => src0_data[64].DATAIN +sink_data[65] => src0_data[65].DATAIN +sink_data[66] => src0_data[66].DATAIN +sink_data[67] => src0_data[67].DATAIN +sink_data[68] => src0_data[68].DATAIN +sink_data[69] => src0_data[69].DATAIN +sink_data[70] => src0_data[70].DATAIN +sink_data[71] => src0_data[71].DATAIN +sink_data[72] => src0_data[72].DATAIN +sink_data[73] => src0_data[73].DATAIN +sink_data[74] => src0_data[74].DATAIN +sink_data[75] => src0_data[75].DATAIN +sink_data[76] => src0_data[76].DATAIN +sink_data[77] => src0_data[77].DATAIN +sink_data[78] => src0_data[78].DATAIN +sink_data[79] => src0_data[79].DATAIN +sink_data[80] => src0_data[80].DATAIN +sink_data[81] => src0_data[81].DATAIN +sink_data[82] => src0_data[82].DATAIN +sink_data[83] => src0_data[83].DATAIN +sink_data[84] => src0_data[84].DATAIN +sink_data[85] => src0_data[85].DATAIN +sink_data[86] => src0_data[86].DATAIN +sink_data[87] => src0_data[87].DATAIN +sink_data[88] => src0_data[88].DATAIN +sink_data[89] => src0_data[89].DATAIN +sink_data[90] => src0_data[90].DATAIN +sink_data[91] => src0_data[91].DATAIN +sink_data[92] => src0_data[92].DATAIN +sink_data[93] => src0_data[93].DATAIN +sink_data[94] => src0_data[94].DATAIN +sink_data[95] => src0_data[95].DATAIN +sink_data[96] => src0_data[96].DATAIN +sink_data[97] => src0_data[97].DATAIN +sink_data[98] => src0_data[98].DATAIN +sink_data[99] => src0_data[99].DATAIN +sink_data[100] => src0_data[100].DATAIN +sink_channel[0] => src0_valid.IN1 +sink_channel[0] => sink_ready.IN0 +sink_channel[1] => src0_channel[0].DATAIN +sink_channel[2] => src0_channel[1].DATAIN +sink_channel[3] => src0_channel[2].DATAIN +sink_channel[4] => src0_channel[3].DATAIN +sink_channel[5] => src0_channel[4].DATAIN +sink_channel[6] => src0_channel[5].DATAIN +sink_channel[7] => src0_channel[6].DATAIN +sink_channel[8] => src0_channel[7].DATAIN +sink_channel[9] => src0_channel[8].DATAIN +sink_channel[10] => src0_channel[9].DATAIN +sink_startofpacket => src0_startofpacket.DATAIN +sink_endofpacket => src0_endofpacket.DATAIN +sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE +src0_valid <= src0_valid.DB_MAX_OUTPUT_PORT_TYPE +src0_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src0_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src0_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src0_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src0_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src0_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src0_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src0_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src0_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src0_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src0_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src0_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src0_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src0_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src0_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src0_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src0_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src0_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src0_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src0_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src0_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src0_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src0_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src0_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src0_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src0_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src0_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src0_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src0_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src0_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src0_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src0_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src0_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src0_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src0_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src0_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src0_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src0_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src0_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src0_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src0_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src0_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src0_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src0_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src0_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src0_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src0_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src0_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src0_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src0_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src0_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src0_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src0_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src0_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src0_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src0_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src0_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src0_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src0_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src0_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src0_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src0_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src0_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src0_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src0_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src0_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src0_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src0_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src0_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src0_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src0_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src0_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src0_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src0_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src0_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src0_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src0_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src0_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src0_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src0_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src0_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src0_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src0_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src0_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src0_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src0_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src0_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src0_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src0_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src0_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src0_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src0_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src0_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src0_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src0_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src0_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src0_data[96] <= sink_data[96].DB_MAX_OUTPUT_PORT_TYPE +src0_data[97] <= sink_data[97].DB_MAX_OUTPUT_PORT_TYPE +src0_data[98] <= sink_data[98].DB_MAX_OUTPUT_PORT_TYPE +src0_data[99] <= sink_data[99].DB_MAX_OUTPUT_PORT_TYPE +src0_data[100] <= sink_data[100].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[0] <= sink_channel[1].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[1] <= sink_channel[2].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[2] <= sink_channel[3].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[3] <= sink_channel[4].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[4] <= sink_channel[5].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[5] <= sink_channel[6].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[6] <= sink_channel[7].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[7] <= sink_channel[8].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[8] <= sink_channel[9].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[9] <= sink_channel[10].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[10] <= +src0_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src0_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src0_ready => sink_ready.IN1 +clk => ~NO_FANOUT~ +reset => ~NO_FANOUT~ + + +|de0_nano_system|system:inst_cpu|system_rsp_xbar_demux_002:rsp_xbar_demux_003 +sink_valid[0] => src0_valid.IN0 +sink_data[0] => src0_data[0].DATAIN +sink_data[1] => src0_data[1].DATAIN +sink_data[2] => src0_data[2].DATAIN +sink_data[3] => src0_data[3].DATAIN +sink_data[4] => src0_data[4].DATAIN +sink_data[5] => src0_data[5].DATAIN +sink_data[6] => src0_data[6].DATAIN +sink_data[7] => src0_data[7].DATAIN +sink_data[8] => src0_data[8].DATAIN +sink_data[9] => src0_data[9].DATAIN +sink_data[10] => src0_data[10].DATAIN +sink_data[11] => src0_data[11].DATAIN +sink_data[12] => src0_data[12].DATAIN +sink_data[13] => src0_data[13].DATAIN +sink_data[14] => src0_data[14].DATAIN +sink_data[15] => src0_data[15].DATAIN +sink_data[16] => src0_data[16].DATAIN +sink_data[17] => src0_data[17].DATAIN +sink_data[18] => src0_data[18].DATAIN +sink_data[19] => src0_data[19].DATAIN +sink_data[20] => src0_data[20].DATAIN +sink_data[21] => src0_data[21].DATAIN +sink_data[22] => src0_data[22].DATAIN +sink_data[23] => src0_data[23].DATAIN +sink_data[24] => src0_data[24].DATAIN +sink_data[25] => src0_data[25].DATAIN +sink_data[26] => src0_data[26].DATAIN +sink_data[27] => src0_data[27].DATAIN +sink_data[28] => src0_data[28].DATAIN +sink_data[29] => src0_data[29].DATAIN +sink_data[30] => src0_data[30].DATAIN +sink_data[31] => src0_data[31].DATAIN +sink_data[32] => src0_data[32].DATAIN +sink_data[33] => src0_data[33].DATAIN +sink_data[34] => src0_data[34].DATAIN +sink_data[35] => src0_data[35].DATAIN +sink_data[36] => src0_data[36].DATAIN +sink_data[37] => src0_data[37].DATAIN +sink_data[38] => src0_data[38].DATAIN +sink_data[39] => src0_data[39].DATAIN +sink_data[40] => src0_data[40].DATAIN +sink_data[41] => src0_data[41].DATAIN +sink_data[42] => src0_data[42].DATAIN +sink_data[43] => src0_data[43].DATAIN +sink_data[44] => src0_data[44].DATAIN +sink_data[45] => src0_data[45].DATAIN +sink_data[46] => src0_data[46].DATAIN +sink_data[47] => src0_data[47].DATAIN +sink_data[48] => src0_data[48].DATAIN +sink_data[49] => src0_data[49].DATAIN +sink_data[50] => src0_data[50].DATAIN +sink_data[51] => src0_data[51].DATAIN +sink_data[52] => src0_data[52].DATAIN +sink_data[53] => src0_data[53].DATAIN +sink_data[54] => src0_data[54].DATAIN +sink_data[55] => src0_data[55].DATAIN +sink_data[56] => src0_data[56].DATAIN +sink_data[57] => src0_data[57].DATAIN +sink_data[58] => src0_data[58].DATAIN +sink_data[59] => src0_data[59].DATAIN +sink_data[60] => src0_data[60].DATAIN +sink_data[61] => src0_data[61].DATAIN +sink_data[62] => src0_data[62].DATAIN +sink_data[63] => src0_data[63].DATAIN +sink_data[64] => src0_data[64].DATAIN +sink_data[65] => src0_data[65].DATAIN +sink_data[66] => src0_data[66].DATAIN +sink_data[67] => src0_data[67].DATAIN +sink_data[68] => src0_data[68].DATAIN +sink_data[69] => src0_data[69].DATAIN +sink_data[70] => src0_data[70].DATAIN +sink_data[71] => src0_data[71].DATAIN +sink_data[72] => src0_data[72].DATAIN +sink_data[73] => src0_data[73].DATAIN +sink_data[74] => src0_data[74].DATAIN +sink_data[75] => src0_data[75].DATAIN +sink_data[76] => src0_data[76].DATAIN +sink_data[77] => src0_data[77].DATAIN +sink_data[78] => src0_data[78].DATAIN +sink_data[79] => src0_data[79].DATAIN +sink_data[80] => src0_data[80].DATAIN +sink_data[81] => src0_data[81].DATAIN +sink_data[82] => src0_data[82].DATAIN +sink_data[83] => src0_data[83].DATAIN +sink_data[84] => src0_data[84].DATAIN +sink_data[85] => src0_data[85].DATAIN +sink_data[86] => src0_data[86].DATAIN +sink_data[87] => src0_data[87].DATAIN +sink_data[88] => src0_data[88].DATAIN +sink_data[89] => src0_data[89].DATAIN +sink_data[90] => src0_data[90].DATAIN +sink_data[91] => src0_data[91].DATAIN +sink_data[92] => src0_data[92].DATAIN +sink_data[93] => src0_data[93].DATAIN +sink_data[94] => src0_data[94].DATAIN +sink_data[95] => src0_data[95].DATAIN +sink_data[96] => src0_data[96].DATAIN +sink_data[97] => src0_data[97].DATAIN +sink_data[98] => src0_data[98].DATAIN +sink_data[99] => src0_data[99].DATAIN +sink_data[100] => src0_data[100].DATAIN +sink_channel[0] => src0_valid.IN1 +sink_channel[0] => sink_ready.IN0 +sink_channel[1] => src0_channel[0].DATAIN +sink_channel[2] => src0_channel[1].DATAIN +sink_channel[3] => src0_channel[2].DATAIN +sink_channel[4] => src0_channel[3].DATAIN +sink_channel[5] => src0_channel[4].DATAIN +sink_channel[6] => src0_channel[5].DATAIN +sink_channel[7] => src0_channel[6].DATAIN +sink_channel[8] => src0_channel[7].DATAIN +sink_channel[9] => src0_channel[8].DATAIN +sink_channel[10] => src0_channel[9].DATAIN +sink_startofpacket => src0_startofpacket.DATAIN +sink_endofpacket => src0_endofpacket.DATAIN +sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE +src0_valid <= src0_valid.DB_MAX_OUTPUT_PORT_TYPE +src0_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src0_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src0_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src0_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src0_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src0_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src0_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src0_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src0_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src0_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src0_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src0_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src0_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src0_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src0_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src0_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src0_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src0_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src0_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src0_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src0_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src0_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src0_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src0_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src0_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src0_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src0_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src0_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src0_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src0_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src0_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src0_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src0_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src0_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src0_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src0_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src0_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src0_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src0_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src0_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src0_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src0_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src0_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src0_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src0_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src0_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src0_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src0_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src0_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src0_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src0_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src0_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src0_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src0_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src0_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src0_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src0_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src0_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src0_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src0_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src0_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src0_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src0_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src0_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src0_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src0_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src0_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src0_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src0_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src0_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src0_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src0_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src0_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src0_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src0_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src0_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src0_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src0_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src0_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src0_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src0_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src0_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src0_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src0_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src0_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src0_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src0_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src0_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src0_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src0_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src0_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src0_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src0_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src0_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src0_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src0_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src0_data[96] <= sink_data[96].DB_MAX_OUTPUT_PORT_TYPE +src0_data[97] <= sink_data[97].DB_MAX_OUTPUT_PORT_TYPE +src0_data[98] <= sink_data[98].DB_MAX_OUTPUT_PORT_TYPE +src0_data[99] <= sink_data[99].DB_MAX_OUTPUT_PORT_TYPE +src0_data[100] <= sink_data[100].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[0] <= sink_channel[1].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[1] <= sink_channel[2].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[2] <= sink_channel[3].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[3] <= sink_channel[4].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[4] <= sink_channel[5].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[5] <= sink_channel[6].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[6] <= sink_channel[7].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[7] <= sink_channel[8].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[8] <= sink_channel[9].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[9] <= sink_channel[10].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[10] <= +src0_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src0_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src0_ready => sink_ready.IN1 +clk => ~NO_FANOUT~ +reset => ~NO_FANOUT~ + + +|de0_nano_system|system:inst_cpu|system_rsp_xbar_demux_002:rsp_xbar_demux_004 +sink_valid[0] => src0_valid.IN0 +sink_data[0] => src0_data[0].DATAIN +sink_data[1] => src0_data[1].DATAIN +sink_data[2] => src0_data[2].DATAIN +sink_data[3] => src0_data[3].DATAIN +sink_data[4] => src0_data[4].DATAIN +sink_data[5] => src0_data[5].DATAIN +sink_data[6] => src0_data[6].DATAIN +sink_data[7] => src0_data[7].DATAIN +sink_data[8] => src0_data[8].DATAIN +sink_data[9] => src0_data[9].DATAIN +sink_data[10] => src0_data[10].DATAIN +sink_data[11] => src0_data[11].DATAIN +sink_data[12] => src0_data[12].DATAIN +sink_data[13] => src0_data[13].DATAIN +sink_data[14] => src0_data[14].DATAIN +sink_data[15] => src0_data[15].DATAIN +sink_data[16] => src0_data[16].DATAIN +sink_data[17] => src0_data[17].DATAIN +sink_data[18] => src0_data[18].DATAIN +sink_data[19] => src0_data[19].DATAIN +sink_data[20] => src0_data[20].DATAIN +sink_data[21] => src0_data[21].DATAIN +sink_data[22] => src0_data[22].DATAIN +sink_data[23] => src0_data[23].DATAIN +sink_data[24] => src0_data[24].DATAIN +sink_data[25] => src0_data[25].DATAIN +sink_data[26] => src0_data[26].DATAIN +sink_data[27] => src0_data[27].DATAIN +sink_data[28] => src0_data[28].DATAIN +sink_data[29] => src0_data[29].DATAIN +sink_data[30] => src0_data[30].DATAIN +sink_data[31] => src0_data[31].DATAIN +sink_data[32] => src0_data[32].DATAIN +sink_data[33] => src0_data[33].DATAIN +sink_data[34] => src0_data[34].DATAIN +sink_data[35] => src0_data[35].DATAIN +sink_data[36] => src0_data[36].DATAIN +sink_data[37] => src0_data[37].DATAIN +sink_data[38] => src0_data[38].DATAIN +sink_data[39] => src0_data[39].DATAIN +sink_data[40] => src0_data[40].DATAIN +sink_data[41] => src0_data[41].DATAIN +sink_data[42] => src0_data[42].DATAIN +sink_data[43] => src0_data[43].DATAIN +sink_data[44] => src0_data[44].DATAIN +sink_data[45] => src0_data[45].DATAIN +sink_data[46] => src0_data[46].DATAIN +sink_data[47] => src0_data[47].DATAIN +sink_data[48] => src0_data[48].DATAIN +sink_data[49] => src0_data[49].DATAIN +sink_data[50] => src0_data[50].DATAIN +sink_data[51] => src0_data[51].DATAIN +sink_data[52] => src0_data[52].DATAIN +sink_data[53] => src0_data[53].DATAIN +sink_data[54] => src0_data[54].DATAIN +sink_data[55] => src0_data[55].DATAIN +sink_data[56] => src0_data[56].DATAIN +sink_data[57] => src0_data[57].DATAIN +sink_data[58] => src0_data[58].DATAIN +sink_data[59] => src0_data[59].DATAIN +sink_data[60] => src0_data[60].DATAIN +sink_data[61] => src0_data[61].DATAIN +sink_data[62] => src0_data[62].DATAIN +sink_data[63] => src0_data[63].DATAIN +sink_data[64] => src0_data[64].DATAIN +sink_data[65] => src0_data[65].DATAIN +sink_data[66] => src0_data[66].DATAIN +sink_data[67] => src0_data[67].DATAIN +sink_data[68] => src0_data[68].DATAIN +sink_data[69] => src0_data[69].DATAIN +sink_data[70] => src0_data[70].DATAIN +sink_data[71] => src0_data[71].DATAIN +sink_data[72] => src0_data[72].DATAIN +sink_data[73] => src0_data[73].DATAIN +sink_data[74] => src0_data[74].DATAIN +sink_data[75] => src0_data[75].DATAIN +sink_data[76] => src0_data[76].DATAIN +sink_data[77] => src0_data[77].DATAIN +sink_data[78] => src0_data[78].DATAIN +sink_data[79] => src0_data[79].DATAIN +sink_data[80] => src0_data[80].DATAIN +sink_data[81] => src0_data[81].DATAIN +sink_data[82] => src0_data[82].DATAIN +sink_data[83] => src0_data[83].DATAIN +sink_data[84] => src0_data[84].DATAIN +sink_data[85] => src0_data[85].DATAIN +sink_data[86] => src0_data[86].DATAIN +sink_data[87] => src0_data[87].DATAIN +sink_data[88] => src0_data[88].DATAIN +sink_data[89] => src0_data[89].DATAIN +sink_data[90] => src0_data[90].DATAIN +sink_data[91] => src0_data[91].DATAIN +sink_data[92] => src0_data[92].DATAIN +sink_data[93] => src0_data[93].DATAIN +sink_data[94] => src0_data[94].DATAIN +sink_data[95] => src0_data[95].DATAIN +sink_data[96] => src0_data[96].DATAIN +sink_data[97] => src0_data[97].DATAIN +sink_data[98] => src0_data[98].DATAIN +sink_data[99] => src0_data[99].DATAIN +sink_data[100] => src0_data[100].DATAIN +sink_channel[0] => src0_valid.IN1 +sink_channel[0] => sink_ready.IN0 +sink_channel[1] => src0_channel[0].DATAIN +sink_channel[2] => src0_channel[1].DATAIN +sink_channel[3] => src0_channel[2].DATAIN +sink_channel[4] => src0_channel[3].DATAIN +sink_channel[5] => src0_channel[4].DATAIN +sink_channel[6] => src0_channel[5].DATAIN +sink_channel[7] => src0_channel[6].DATAIN +sink_channel[8] => src0_channel[7].DATAIN +sink_channel[9] => src0_channel[8].DATAIN +sink_channel[10] => src0_channel[9].DATAIN +sink_startofpacket => src0_startofpacket.DATAIN +sink_endofpacket => src0_endofpacket.DATAIN +sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE +src0_valid <= src0_valid.DB_MAX_OUTPUT_PORT_TYPE +src0_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src0_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src0_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src0_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src0_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src0_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src0_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src0_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src0_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src0_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src0_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src0_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src0_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src0_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src0_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src0_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src0_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src0_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src0_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src0_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src0_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src0_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src0_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src0_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src0_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src0_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src0_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src0_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src0_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src0_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src0_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src0_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src0_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src0_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src0_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src0_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src0_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src0_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src0_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src0_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src0_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src0_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src0_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src0_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src0_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src0_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src0_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src0_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src0_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src0_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src0_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src0_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src0_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src0_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src0_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src0_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src0_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src0_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src0_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src0_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src0_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src0_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src0_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src0_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src0_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src0_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src0_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src0_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src0_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src0_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src0_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src0_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src0_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src0_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src0_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src0_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src0_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src0_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src0_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src0_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src0_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src0_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src0_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src0_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src0_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src0_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src0_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src0_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src0_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src0_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src0_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src0_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src0_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src0_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src0_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src0_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src0_data[96] <= sink_data[96].DB_MAX_OUTPUT_PORT_TYPE +src0_data[97] <= sink_data[97].DB_MAX_OUTPUT_PORT_TYPE +src0_data[98] <= sink_data[98].DB_MAX_OUTPUT_PORT_TYPE +src0_data[99] <= sink_data[99].DB_MAX_OUTPUT_PORT_TYPE +src0_data[100] <= sink_data[100].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[0] <= sink_channel[1].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[1] <= sink_channel[2].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[2] <= sink_channel[3].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[3] <= sink_channel[4].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[4] <= sink_channel[5].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[5] <= sink_channel[6].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[6] <= sink_channel[7].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[7] <= sink_channel[8].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[8] <= sink_channel[9].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[9] <= sink_channel[10].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[10] <= +src0_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src0_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src0_ready => sink_ready.IN1 +clk => ~NO_FANOUT~ +reset => ~NO_FANOUT~ + + +|de0_nano_system|system:inst_cpu|system_rsp_xbar_demux_002:rsp_xbar_demux_005 +sink_valid[0] => src0_valid.IN0 +sink_data[0] => src0_data[0].DATAIN +sink_data[1] => src0_data[1].DATAIN +sink_data[2] => src0_data[2].DATAIN +sink_data[3] => src0_data[3].DATAIN +sink_data[4] => src0_data[4].DATAIN +sink_data[5] => src0_data[5].DATAIN +sink_data[6] => src0_data[6].DATAIN +sink_data[7] => src0_data[7].DATAIN +sink_data[8] => src0_data[8].DATAIN +sink_data[9] => src0_data[9].DATAIN +sink_data[10] => src0_data[10].DATAIN +sink_data[11] => src0_data[11].DATAIN +sink_data[12] => src0_data[12].DATAIN +sink_data[13] => src0_data[13].DATAIN +sink_data[14] => src0_data[14].DATAIN +sink_data[15] => src0_data[15].DATAIN +sink_data[16] => src0_data[16].DATAIN +sink_data[17] => src0_data[17].DATAIN +sink_data[18] => src0_data[18].DATAIN +sink_data[19] => src0_data[19].DATAIN +sink_data[20] => src0_data[20].DATAIN +sink_data[21] => src0_data[21].DATAIN +sink_data[22] => src0_data[22].DATAIN +sink_data[23] => src0_data[23].DATAIN +sink_data[24] => src0_data[24].DATAIN +sink_data[25] => src0_data[25].DATAIN +sink_data[26] => src0_data[26].DATAIN +sink_data[27] => src0_data[27].DATAIN +sink_data[28] => src0_data[28].DATAIN +sink_data[29] => src0_data[29].DATAIN +sink_data[30] => src0_data[30].DATAIN +sink_data[31] => src0_data[31].DATAIN +sink_data[32] => src0_data[32].DATAIN +sink_data[33] => src0_data[33].DATAIN +sink_data[34] => src0_data[34].DATAIN +sink_data[35] => src0_data[35].DATAIN +sink_data[36] => src0_data[36].DATAIN +sink_data[37] => src0_data[37].DATAIN +sink_data[38] => src0_data[38].DATAIN +sink_data[39] => src0_data[39].DATAIN +sink_data[40] => src0_data[40].DATAIN +sink_data[41] => src0_data[41].DATAIN +sink_data[42] => src0_data[42].DATAIN +sink_data[43] => src0_data[43].DATAIN +sink_data[44] => src0_data[44].DATAIN +sink_data[45] => src0_data[45].DATAIN +sink_data[46] => src0_data[46].DATAIN +sink_data[47] => src0_data[47].DATAIN +sink_data[48] => src0_data[48].DATAIN +sink_data[49] => src0_data[49].DATAIN +sink_data[50] => src0_data[50].DATAIN +sink_data[51] => src0_data[51].DATAIN +sink_data[52] => src0_data[52].DATAIN +sink_data[53] => src0_data[53].DATAIN +sink_data[54] => src0_data[54].DATAIN +sink_data[55] => src0_data[55].DATAIN +sink_data[56] => src0_data[56].DATAIN +sink_data[57] => src0_data[57].DATAIN +sink_data[58] => src0_data[58].DATAIN +sink_data[59] => src0_data[59].DATAIN +sink_data[60] => src0_data[60].DATAIN +sink_data[61] => src0_data[61].DATAIN +sink_data[62] => src0_data[62].DATAIN +sink_data[63] => src0_data[63].DATAIN +sink_data[64] => src0_data[64].DATAIN +sink_data[65] => src0_data[65].DATAIN +sink_data[66] => src0_data[66].DATAIN +sink_data[67] => src0_data[67].DATAIN +sink_data[68] => src0_data[68].DATAIN +sink_data[69] => src0_data[69].DATAIN +sink_data[70] => src0_data[70].DATAIN +sink_data[71] => src0_data[71].DATAIN +sink_data[72] => src0_data[72].DATAIN +sink_data[73] => src0_data[73].DATAIN +sink_data[74] => src0_data[74].DATAIN +sink_data[75] => src0_data[75].DATAIN +sink_data[76] => src0_data[76].DATAIN +sink_data[77] => src0_data[77].DATAIN +sink_data[78] => src0_data[78].DATAIN +sink_data[79] => src0_data[79].DATAIN +sink_data[80] => src0_data[80].DATAIN +sink_data[81] => src0_data[81].DATAIN +sink_data[82] => src0_data[82].DATAIN +sink_data[83] => src0_data[83].DATAIN +sink_data[84] => src0_data[84].DATAIN +sink_data[85] => src0_data[85].DATAIN +sink_data[86] => src0_data[86].DATAIN +sink_data[87] => src0_data[87].DATAIN +sink_data[88] => src0_data[88].DATAIN +sink_data[89] => src0_data[89].DATAIN +sink_data[90] => src0_data[90].DATAIN +sink_data[91] => src0_data[91].DATAIN +sink_data[92] => src0_data[92].DATAIN +sink_data[93] => src0_data[93].DATAIN +sink_data[94] => src0_data[94].DATAIN +sink_data[95] => src0_data[95].DATAIN +sink_data[96] => src0_data[96].DATAIN +sink_data[97] => src0_data[97].DATAIN +sink_data[98] => src0_data[98].DATAIN +sink_data[99] => src0_data[99].DATAIN +sink_data[100] => src0_data[100].DATAIN +sink_channel[0] => src0_valid.IN1 +sink_channel[0] => sink_ready.IN0 +sink_channel[1] => src0_channel[0].DATAIN +sink_channel[2] => src0_channel[1].DATAIN +sink_channel[3] => src0_channel[2].DATAIN +sink_channel[4] => src0_channel[3].DATAIN +sink_channel[5] => src0_channel[4].DATAIN +sink_channel[6] => src0_channel[5].DATAIN +sink_channel[7] => src0_channel[6].DATAIN +sink_channel[8] => src0_channel[7].DATAIN +sink_channel[9] => src0_channel[8].DATAIN +sink_channel[10] => src0_channel[9].DATAIN +sink_startofpacket => src0_startofpacket.DATAIN +sink_endofpacket => src0_endofpacket.DATAIN +sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE +src0_valid <= src0_valid.DB_MAX_OUTPUT_PORT_TYPE +src0_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src0_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src0_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src0_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src0_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src0_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src0_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src0_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src0_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src0_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src0_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src0_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src0_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src0_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src0_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src0_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src0_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src0_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src0_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src0_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src0_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src0_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src0_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src0_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src0_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src0_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src0_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src0_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src0_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src0_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src0_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src0_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src0_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src0_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src0_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src0_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src0_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src0_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src0_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src0_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src0_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src0_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src0_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src0_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src0_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src0_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src0_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src0_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src0_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src0_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src0_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src0_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src0_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src0_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src0_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src0_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src0_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src0_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src0_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src0_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src0_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src0_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src0_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src0_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src0_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src0_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src0_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src0_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src0_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src0_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src0_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src0_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src0_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src0_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src0_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src0_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src0_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src0_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src0_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src0_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src0_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src0_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src0_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src0_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src0_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src0_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src0_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src0_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src0_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src0_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src0_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src0_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src0_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src0_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src0_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src0_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src0_data[96] <= sink_data[96].DB_MAX_OUTPUT_PORT_TYPE +src0_data[97] <= sink_data[97].DB_MAX_OUTPUT_PORT_TYPE +src0_data[98] <= sink_data[98].DB_MAX_OUTPUT_PORT_TYPE +src0_data[99] <= sink_data[99].DB_MAX_OUTPUT_PORT_TYPE +src0_data[100] <= sink_data[100].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[0] <= sink_channel[1].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[1] <= sink_channel[2].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[2] <= sink_channel[3].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[3] <= sink_channel[4].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[4] <= sink_channel[5].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[5] <= sink_channel[6].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[6] <= sink_channel[7].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[7] <= sink_channel[8].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[8] <= sink_channel[9].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[9] <= sink_channel[10].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[10] <= +src0_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src0_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src0_ready => sink_ready.IN1 +clk => ~NO_FANOUT~ +reset => ~NO_FANOUT~ + + +|de0_nano_system|system:inst_cpu|system_rsp_xbar_demux_002:rsp_xbar_demux_006 +sink_valid[0] => src0_valid.IN0 +sink_data[0] => src0_data[0].DATAIN +sink_data[1] => src0_data[1].DATAIN +sink_data[2] => src0_data[2].DATAIN +sink_data[3] => src0_data[3].DATAIN +sink_data[4] => src0_data[4].DATAIN +sink_data[5] => src0_data[5].DATAIN +sink_data[6] => src0_data[6].DATAIN +sink_data[7] => src0_data[7].DATAIN +sink_data[8] => src0_data[8].DATAIN +sink_data[9] => src0_data[9].DATAIN +sink_data[10] => src0_data[10].DATAIN +sink_data[11] => src0_data[11].DATAIN +sink_data[12] => src0_data[12].DATAIN +sink_data[13] => src0_data[13].DATAIN +sink_data[14] => src0_data[14].DATAIN +sink_data[15] => src0_data[15].DATAIN +sink_data[16] => src0_data[16].DATAIN +sink_data[17] => src0_data[17].DATAIN +sink_data[18] => src0_data[18].DATAIN +sink_data[19] => src0_data[19].DATAIN +sink_data[20] => src0_data[20].DATAIN +sink_data[21] => src0_data[21].DATAIN +sink_data[22] => src0_data[22].DATAIN +sink_data[23] => src0_data[23].DATAIN +sink_data[24] => src0_data[24].DATAIN +sink_data[25] => src0_data[25].DATAIN +sink_data[26] => src0_data[26].DATAIN +sink_data[27] => src0_data[27].DATAIN +sink_data[28] => src0_data[28].DATAIN +sink_data[29] => src0_data[29].DATAIN +sink_data[30] => src0_data[30].DATAIN +sink_data[31] => src0_data[31].DATAIN +sink_data[32] => src0_data[32].DATAIN +sink_data[33] => src0_data[33].DATAIN +sink_data[34] => src0_data[34].DATAIN +sink_data[35] => src0_data[35].DATAIN +sink_data[36] => src0_data[36].DATAIN +sink_data[37] => src0_data[37].DATAIN +sink_data[38] => src0_data[38].DATAIN +sink_data[39] => src0_data[39].DATAIN +sink_data[40] => src0_data[40].DATAIN +sink_data[41] => src0_data[41].DATAIN +sink_data[42] => src0_data[42].DATAIN +sink_data[43] => src0_data[43].DATAIN +sink_data[44] => src0_data[44].DATAIN +sink_data[45] => src0_data[45].DATAIN +sink_data[46] => src0_data[46].DATAIN +sink_data[47] => src0_data[47].DATAIN +sink_data[48] => src0_data[48].DATAIN +sink_data[49] => src0_data[49].DATAIN +sink_data[50] => src0_data[50].DATAIN +sink_data[51] => src0_data[51].DATAIN +sink_data[52] => src0_data[52].DATAIN +sink_data[53] => src0_data[53].DATAIN +sink_data[54] => src0_data[54].DATAIN +sink_data[55] => src0_data[55].DATAIN +sink_data[56] => src0_data[56].DATAIN +sink_data[57] => src0_data[57].DATAIN +sink_data[58] => src0_data[58].DATAIN +sink_data[59] => src0_data[59].DATAIN +sink_data[60] => src0_data[60].DATAIN +sink_data[61] => src0_data[61].DATAIN +sink_data[62] => src0_data[62].DATAIN +sink_data[63] => src0_data[63].DATAIN +sink_data[64] => src0_data[64].DATAIN +sink_data[65] => src0_data[65].DATAIN +sink_data[66] => src0_data[66].DATAIN +sink_data[67] => src0_data[67].DATAIN +sink_data[68] => src0_data[68].DATAIN +sink_data[69] => src0_data[69].DATAIN +sink_data[70] => src0_data[70].DATAIN +sink_data[71] => src0_data[71].DATAIN +sink_data[72] => src0_data[72].DATAIN +sink_data[73] => src0_data[73].DATAIN +sink_data[74] => src0_data[74].DATAIN +sink_data[75] => src0_data[75].DATAIN +sink_data[76] => src0_data[76].DATAIN +sink_data[77] => src0_data[77].DATAIN +sink_data[78] => src0_data[78].DATAIN +sink_data[79] => src0_data[79].DATAIN +sink_data[80] => src0_data[80].DATAIN +sink_data[81] => src0_data[81].DATAIN +sink_data[82] => src0_data[82].DATAIN +sink_data[83] => src0_data[83].DATAIN +sink_data[84] => src0_data[84].DATAIN +sink_data[85] => src0_data[85].DATAIN +sink_data[86] => src0_data[86].DATAIN +sink_data[87] => src0_data[87].DATAIN +sink_data[88] => src0_data[88].DATAIN +sink_data[89] => src0_data[89].DATAIN +sink_data[90] => src0_data[90].DATAIN +sink_data[91] => src0_data[91].DATAIN +sink_data[92] => src0_data[92].DATAIN +sink_data[93] => src0_data[93].DATAIN +sink_data[94] => src0_data[94].DATAIN +sink_data[95] => src0_data[95].DATAIN +sink_data[96] => src0_data[96].DATAIN +sink_data[97] => src0_data[97].DATAIN +sink_data[98] => src0_data[98].DATAIN +sink_data[99] => src0_data[99].DATAIN +sink_data[100] => src0_data[100].DATAIN +sink_channel[0] => src0_valid.IN1 +sink_channel[0] => sink_ready.IN0 +sink_channel[1] => src0_channel[0].DATAIN +sink_channel[2] => src0_channel[1].DATAIN +sink_channel[3] => src0_channel[2].DATAIN +sink_channel[4] => src0_channel[3].DATAIN +sink_channel[5] => src0_channel[4].DATAIN +sink_channel[6] => src0_channel[5].DATAIN +sink_channel[7] => src0_channel[6].DATAIN +sink_channel[8] => src0_channel[7].DATAIN +sink_channel[9] => src0_channel[8].DATAIN +sink_channel[10] => src0_channel[9].DATAIN +sink_startofpacket => src0_startofpacket.DATAIN +sink_endofpacket => src0_endofpacket.DATAIN +sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE +src0_valid <= src0_valid.DB_MAX_OUTPUT_PORT_TYPE +src0_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src0_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src0_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src0_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src0_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src0_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src0_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src0_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src0_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src0_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src0_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src0_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src0_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src0_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src0_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src0_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src0_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src0_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src0_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src0_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src0_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src0_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src0_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src0_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src0_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src0_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src0_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src0_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src0_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src0_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src0_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src0_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src0_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src0_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src0_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src0_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src0_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src0_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src0_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src0_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src0_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src0_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src0_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src0_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src0_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src0_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src0_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src0_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src0_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src0_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src0_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src0_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src0_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src0_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src0_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src0_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src0_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src0_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src0_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src0_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src0_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src0_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src0_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src0_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src0_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src0_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src0_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src0_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src0_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src0_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src0_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src0_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src0_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src0_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src0_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src0_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src0_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src0_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src0_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src0_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src0_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src0_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src0_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src0_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src0_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src0_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src0_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src0_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src0_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src0_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src0_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src0_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src0_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src0_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src0_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src0_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src0_data[96] <= sink_data[96].DB_MAX_OUTPUT_PORT_TYPE +src0_data[97] <= sink_data[97].DB_MAX_OUTPUT_PORT_TYPE +src0_data[98] <= sink_data[98].DB_MAX_OUTPUT_PORT_TYPE +src0_data[99] <= sink_data[99].DB_MAX_OUTPUT_PORT_TYPE +src0_data[100] <= sink_data[100].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[0] <= sink_channel[1].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[1] <= sink_channel[2].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[2] <= sink_channel[3].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[3] <= sink_channel[4].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[4] <= sink_channel[5].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[5] <= sink_channel[6].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[6] <= sink_channel[7].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[7] <= sink_channel[8].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[8] <= sink_channel[9].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[9] <= sink_channel[10].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[10] <= +src0_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src0_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src0_ready => sink_ready.IN1 +clk => ~NO_FANOUT~ +reset => ~NO_FANOUT~ + + +|de0_nano_system|system:inst_cpu|system_rsp_xbar_demux_002:rsp_xbar_demux_007 +sink_valid[0] => src0_valid.IN0 +sink_data[0] => src0_data[0].DATAIN +sink_data[1] => src0_data[1].DATAIN +sink_data[2] => src0_data[2].DATAIN +sink_data[3] => src0_data[3].DATAIN +sink_data[4] => src0_data[4].DATAIN +sink_data[5] => src0_data[5].DATAIN +sink_data[6] => src0_data[6].DATAIN +sink_data[7] => src0_data[7].DATAIN +sink_data[8] => src0_data[8].DATAIN +sink_data[9] => src0_data[9].DATAIN +sink_data[10] => src0_data[10].DATAIN +sink_data[11] => src0_data[11].DATAIN +sink_data[12] => src0_data[12].DATAIN +sink_data[13] => src0_data[13].DATAIN +sink_data[14] => src0_data[14].DATAIN +sink_data[15] => src0_data[15].DATAIN +sink_data[16] => src0_data[16].DATAIN +sink_data[17] => src0_data[17].DATAIN +sink_data[18] => src0_data[18].DATAIN +sink_data[19] => src0_data[19].DATAIN +sink_data[20] => src0_data[20].DATAIN +sink_data[21] => src0_data[21].DATAIN +sink_data[22] => src0_data[22].DATAIN +sink_data[23] => src0_data[23].DATAIN +sink_data[24] => src0_data[24].DATAIN +sink_data[25] => src0_data[25].DATAIN +sink_data[26] => src0_data[26].DATAIN +sink_data[27] => src0_data[27].DATAIN +sink_data[28] => src0_data[28].DATAIN +sink_data[29] => src0_data[29].DATAIN +sink_data[30] => src0_data[30].DATAIN +sink_data[31] => src0_data[31].DATAIN +sink_data[32] => src0_data[32].DATAIN +sink_data[33] => src0_data[33].DATAIN +sink_data[34] => src0_data[34].DATAIN +sink_data[35] => src0_data[35].DATAIN +sink_data[36] => src0_data[36].DATAIN +sink_data[37] => src0_data[37].DATAIN +sink_data[38] => src0_data[38].DATAIN +sink_data[39] => src0_data[39].DATAIN +sink_data[40] => src0_data[40].DATAIN +sink_data[41] => src0_data[41].DATAIN +sink_data[42] => src0_data[42].DATAIN +sink_data[43] => src0_data[43].DATAIN +sink_data[44] => src0_data[44].DATAIN +sink_data[45] => src0_data[45].DATAIN +sink_data[46] => src0_data[46].DATAIN +sink_data[47] => src0_data[47].DATAIN +sink_data[48] => src0_data[48].DATAIN +sink_data[49] => src0_data[49].DATAIN +sink_data[50] => src0_data[50].DATAIN +sink_data[51] => src0_data[51].DATAIN +sink_data[52] => src0_data[52].DATAIN +sink_data[53] => src0_data[53].DATAIN +sink_data[54] => src0_data[54].DATAIN +sink_data[55] => src0_data[55].DATAIN +sink_data[56] => src0_data[56].DATAIN +sink_data[57] => src0_data[57].DATAIN +sink_data[58] => src0_data[58].DATAIN +sink_data[59] => src0_data[59].DATAIN +sink_data[60] => src0_data[60].DATAIN +sink_data[61] => src0_data[61].DATAIN +sink_data[62] => src0_data[62].DATAIN +sink_data[63] => src0_data[63].DATAIN +sink_data[64] => src0_data[64].DATAIN +sink_data[65] => src0_data[65].DATAIN +sink_data[66] => src0_data[66].DATAIN +sink_data[67] => src0_data[67].DATAIN +sink_data[68] => src0_data[68].DATAIN +sink_data[69] => src0_data[69].DATAIN +sink_data[70] => src0_data[70].DATAIN +sink_data[71] => src0_data[71].DATAIN +sink_data[72] => src0_data[72].DATAIN +sink_data[73] => src0_data[73].DATAIN +sink_data[74] => src0_data[74].DATAIN +sink_data[75] => src0_data[75].DATAIN +sink_data[76] => src0_data[76].DATAIN +sink_data[77] => src0_data[77].DATAIN +sink_data[78] => src0_data[78].DATAIN +sink_data[79] => src0_data[79].DATAIN +sink_data[80] => src0_data[80].DATAIN +sink_data[81] => src0_data[81].DATAIN +sink_data[82] => src0_data[82].DATAIN +sink_data[83] => src0_data[83].DATAIN +sink_data[84] => src0_data[84].DATAIN +sink_data[85] => src0_data[85].DATAIN +sink_data[86] => src0_data[86].DATAIN +sink_data[87] => src0_data[87].DATAIN +sink_data[88] => src0_data[88].DATAIN +sink_data[89] => src0_data[89].DATAIN +sink_data[90] => src0_data[90].DATAIN +sink_data[91] => src0_data[91].DATAIN +sink_data[92] => src0_data[92].DATAIN +sink_data[93] => src0_data[93].DATAIN +sink_data[94] => src0_data[94].DATAIN +sink_data[95] => src0_data[95].DATAIN +sink_data[96] => src0_data[96].DATAIN +sink_data[97] => src0_data[97].DATAIN +sink_data[98] => src0_data[98].DATAIN +sink_data[99] => src0_data[99].DATAIN +sink_data[100] => src0_data[100].DATAIN +sink_channel[0] => src0_valid.IN1 +sink_channel[0] => sink_ready.IN0 +sink_channel[1] => src0_channel[0].DATAIN +sink_channel[2] => src0_channel[1].DATAIN +sink_channel[3] => src0_channel[2].DATAIN +sink_channel[4] => src0_channel[3].DATAIN +sink_channel[5] => src0_channel[4].DATAIN +sink_channel[6] => src0_channel[5].DATAIN +sink_channel[7] => src0_channel[6].DATAIN +sink_channel[8] => src0_channel[7].DATAIN +sink_channel[9] => src0_channel[8].DATAIN +sink_channel[10] => src0_channel[9].DATAIN +sink_startofpacket => src0_startofpacket.DATAIN +sink_endofpacket => src0_endofpacket.DATAIN +sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE +src0_valid <= src0_valid.DB_MAX_OUTPUT_PORT_TYPE +src0_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src0_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src0_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src0_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src0_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src0_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src0_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src0_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src0_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src0_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src0_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src0_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src0_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src0_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src0_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src0_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src0_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src0_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src0_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src0_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src0_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src0_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src0_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src0_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src0_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src0_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src0_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src0_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src0_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src0_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src0_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src0_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src0_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src0_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src0_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src0_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src0_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src0_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src0_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src0_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src0_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src0_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src0_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src0_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src0_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src0_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src0_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src0_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src0_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src0_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src0_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src0_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src0_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src0_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src0_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src0_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src0_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src0_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src0_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src0_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src0_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src0_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src0_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src0_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src0_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src0_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src0_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src0_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src0_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src0_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src0_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src0_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src0_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src0_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src0_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src0_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src0_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src0_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src0_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src0_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src0_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src0_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src0_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src0_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src0_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src0_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src0_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src0_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src0_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src0_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src0_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src0_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src0_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src0_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src0_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src0_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src0_data[96] <= sink_data[96].DB_MAX_OUTPUT_PORT_TYPE +src0_data[97] <= sink_data[97].DB_MAX_OUTPUT_PORT_TYPE +src0_data[98] <= sink_data[98].DB_MAX_OUTPUT_PORT_TYPE +src0_data[99] <= sink_data[99].DB_MAX_OUTPUT_PORT_TYPE +src0_data[100] <= sink_data[100].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[0] <= sink_channel[1].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[1] <= sink_channel[2].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[2] <= sink_channel[3].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[3] <= sink_channel[4].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[4] <= sink_channel[5].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[5] <= sink_channel[6].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[6] <= sink_channel[7].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[7] <= sink_channel[8].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[8] <= sink_channel[9].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[9] <= sink_channel[10].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[10] <= +src0_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src0_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src0_ready => sink_ready.IN1 +clk => ~NO_FANOUT~ +reset => ~NO_FANOUT~ + + +|de0_nano_system|system:inst_cpu|system_rsp_xbar_demux_002:rsp_xbar_demux_008 +sink_valid[0] => src0_valid.IN0 +sink_data[0] => src0_data[0].DATAIN +sink_data[1] => src0_data[1].DATAIN +sink_data[2] => src0_data[2].DATAIN +sink_data[3] => src0_data[3].DATAIN +sink_data[4] => src0_data[4].DATAIN +sink_data[5] => src0_data[5].DATAIN +sink_data[6] => src0_data[6].DATAIN +sink_data[7] => src0_data[7].DATAIN +sink_data[8] => src0_data[8].DATAIN +sink_data[9] => src0_data[9].DATAIN +sink_data[10] => src0_data[10].DATAIN +sink_data[11] => src0_data[11].DATAIN +sink_data[12] => src0_data[12].DATAIN +sink_data[13] => src0_data[13].DATAIN +sink_data[14] => src0_data[14].DATAIN +sink_data[15] => src0_data[15].DATAIN +sink_data[16] => src0_data[16].DATAIN +sink_data[17] => src0_data[17].DATAIN +sink_data[18] => src0_data[18].DATAIN +sink_data[19] => src0_data[19].DATAIN +sink_data[20] => src0_data[20].DATAIN +sink_data[21] => src0_data[21].DATAIN +sink_data[22] => src0_data[22].DATAIN +sink_data[23] => src0_data[23].DATAIN +sink_data[24] => src0_data[24].DATAIN +sink_data[25] => src0_data[25].DATAIN +sink_data[26] => src0_data[26].DATAIN +sink_data[27] => src0_data[27].DATAIN +sink_data[28] => src0_data[28].DATAIN +sink_data[29] => src0_data[29].DATAIN +sink_data[30] => src0_data[30].DATAIN +sink_data[31] => src0_data[31].DATAIN +sink_data[32] => src0_data[32].DATAIN +sink_data[33] => src0_data[33].DATAIN +sink_data[34] => src0_data[34].DATAIN +sink_data[35] => src0_data[35].DATAIN +sink_data[36] => src0_data[36].DATAIN +sink_data[37] => src0_data[37].DATAIN +sink_data[38] => src0_data[38].DATAIN +sink_data[39] => src0_data[39].DATAIN +sink_data[40] => src0_data[40].DATAIN +sink_data[41] => src0_data[41].DATAIN +sink_data[42] => src0_data[42].DATAIN +sink_data[43] => src0_data[43].DATAIN +sink_data[44] => src0_data[44].DATAIN +sink_data[45] => src0_data[45].DATAIN +sink_data[46] => src0_data[46].DATAIN +sink_data[47] => src0_data[47].DATAIN +sink_data[48] => src0_data[48].DATAIN +sink_data[49] => src0_data[49].DATAIN +sink_data[50] => src0_data[50].DATAIN +sink_data[51] => src0_data[51].DATAIN +sink_data[52] => src0_data[52].DATAIN +sink_data[53] => src0_data[53].DATAIN +sink_data[54] => src0_data[54].DATAIN +sink_data[55] => src0_data[55].DATAIN +sink_data[56] => src0_data[56].DATAIN +sink_data[57] => src0_data[57].DATAIN +sink_data[58] => src0_data[58].DATAIN +sink_data[59] => src0_data[59].DATAIN +sink_data[60] => src0_data[60].DATAIN +sink_data[61] => src0_data[61].DATAIN +sink_data[62] => src0_data[62].DATAIN +sink_data[63] => src0_data[63].DATAIN +sink_data[64] => src0_data[64].DATAIN +sink_data[65] => src0_data[65].DATAIN +sink_data[66] => src0_data[66].DATAIN +sink_data[67] => src0_data[67].DATAIN +sink_data[68] => src0_data[68].DATAIN +sink_data[69] => src0_data[69].DATAIN +sink_data[70] => src0_data[70].DATAIN +sink_data[71] => src0_data[71].DATAIN +sink_data[72] => src0_data[72].DATAIN +sink_data[73] => src0_data[73].DATAIN +sink_data[74] => src0_data[74].DATAIN +sink_data[75] => src0_data[75].DATAIN +sink_data[76] => src0_data[76].DATAIN +sink_data[77] => src0_data[77].DATAIN +sink_data[78] => src0_data[78].DATAIN +sink_data[79] => src0_data[79].DATAIN +sink_data[80] => src0_data[80].DATAIN +sink_data[81] => src0_data[81].DATAIN +sink_data[82] => src0_data[82].DATAIN +sink_data[83] => src0_data[83].DATAIN +sink_data[84] => src0_data[84].DATAIN +sink_data[85] => src0_data[85].DATAIN +sink_data[86] => src0_data[86].DATAIN +sink_data[87] => src0_data[87].DATAIN +sink_data[88] => src0_data[88].DATAIN +sink_data[89] => src0_data[89].DATAIN +sink_data[90] => src0_data[90].DATAIN +sink_data[91] => src0_data[91].DATAIN +sink_data[92] => src0_data[92].DATAIN +sink_data[93] => src0_data[93].DATAIN +sink_data[94] => src0_data[94].DATAIN +sink_data[95] => src0_data[95].DATAIN +sink_data[96] => src0_data[96].DATAIN +sink_data[97] => src0_data[97].DATAIN +sink_data[98] => src0_data[98].DATAIN +sink_data[99] => src0_data[99].DATAIN +sink_data[100] => src0_data[100].DATAIN +sink_channel[0] => src0_valid.IN1 +sink_channel[0] => sink_ready.IN0 +sink_channel[1] => src0_channel[0].DATAIN +sink_channel[2] => src0_channel[1].DATAIN +sink_channel[3] => src0_channel[2].DATAIN +sink_channel[4] => src0_channel[3].DATAIN +sink_channel[5] => src0_channel[4].DATAIN +sink_channel[6] => src0_channel[5].DATAIN +sink_channel[7] => src0_channel[6].DATAIN +sink_channel[8] => src0_channel[7].DATAIN +sink_channel[9] => src0_channel[8].DATAIN +sink_channel[10] => src0_channel[9].DATAIN +sink_startofpacket => src0_startofpacket.DATAIN +sink_endofpacket => src0_endofpacket.DATAIN +sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE +src0_valid <= src0_valid.DB_MAX_OUTPUT_PORT_TYPE +src0_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src0_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src0_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src0_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src0_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src0_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src0_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src0_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src0_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src0_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src0_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src0_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src0_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src0_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src0_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src0_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src0_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src0_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src0_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src0_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src0_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src0_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src0_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src0_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src0_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src0_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src0_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src0_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src0_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src0_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src0_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src0_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src0_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src0_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src0_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src0_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src0_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src0_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src0_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src0_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src0_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src0_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src0_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src0_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src0_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src0_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src0_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src0_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src0_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src0_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src0_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src0_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src0_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src0_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src0_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src0_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src0_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src0_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src0_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src0_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src0_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src0_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src0_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src0_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src0_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src0_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src0_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src0_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src0_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src0_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src0_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src0_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src0_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src0_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src0_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src0_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src0_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src0_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src0_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src0_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src0_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src0_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src0_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src0_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src0_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src0_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src0_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src0_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src0_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src0_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src0_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src0_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src0_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src0_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src0_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src0_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src0_data[96] <= sink_data[96].DB_MAX_OUTPUT_PORT_TYPE +src0_data[97] <= sink_data[97].DB_MAX_OUTPUT_PORT_TYPE +src0_data[98] <= sink_data[98].DB_MAX_OUTPUT_PORT_TYPE +src0_data[99] <= sink_data[99].DB_MAX_OUTPUT_PORT_TYPE +src0_data[100] <= sink_data[100].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[0] <= sink_channel[1].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[1] <= sink_channel[2].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[2] <= sink_channel[3].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[3] <= sink_channel[4].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[4] <= sink_channel[5].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[5] <= sink_channel[6].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[6] <= sink_channel[7].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[7] <= sink_channel[8].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[8] <= sink_channel[9].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[9] <= sink_channel[10].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[10] <= +src0_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src0_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src0_ready => sink_ready.IN1 +clk => ~NO_FANOUT~ +reset => ~NO_FANOUT~ + + +|de0_nano_system|system:inst_cpu|system_rsp_xbar_demux_002:rsp_xbar_demux_009 +sink_valid[0] => src0_valid.IN0 +sink_data[0] => src0_data[0].DATAIN +sink_data[1] => src0_data[1].DATAIN +sink_data[2] => src0_data[2].DATAIN +sink_data[3] => src0_data[3].DATAIN +sink_data[4] => src0_data[4].DATAIN +sink_data[5] => src0_data[5].DATAIN +sink_data[6] => src0_data[6].DATAIN +sink_data[7] => src0_data[7].DATAIN +sink_data[8] => src0_data[8].DATAIN +sink_data[9] => src0_data[9].DATAIN +sink_data[10] => src0_data[10].DATAIN +sink_data[11] => src0_data[11].DATAIN +sink_data[12] => src0_data[12].DATAIN +sink_data[13] => src0_data[13].DATAIN +sink_data[14] => src0_data[14].DATAIN +sink_data[15] => src0_data[15].DATAIN +sink_data[16] => src0_data[16].DATAIN +sink_data[17] => src0_data[17].DATAIN +sink_data[18] => src0_data[18].DATAIN +sink_data[19] => src0_data[19].DATAIN +sink_data[20] => src0_data[20].DATAIN +sink_data[21] => src0_data[21].DATAIN +sink_data[22] => src0_data[22].DATAIN +sink_data[23] => src0_data[23].DATAIN +sink_data[24] => src0_data[24].DATAIN +sink_data[25] => src0_data[25].DATAIN +sink_data[26] => src0_data[26].DATAIN +sink_data[27] => src0_data[27].DATAIN +sink_data[28] => src0_data[28].DATAIN +sink_data[29] => src0_data[29].DATAIN +sink_data[30] => src0_data[30].DATAIN +sink_data[31] => src0_data[31].DATAIN +sink_data[32] => src0_data[32].DATAIN +sink_data[33] => src0_data[33].DATAIN +sink_data[34] => src0_data[34].DATAIN +sink_data[35] => src0_data[35].DATAIN +sink_data[36] => src0_data[36].DATAIN +sink_data[37] => src0_data[37].DATAIN +sink_data[38] => src0_data[38].DATAIN +sink_data[39] => src0_data[39].DATAIN +sink_data[40] => src0_data[40].DATAIN +sink_data[41] => src0_data[41].DATAIN +sink_data[42] => src0_data[42].DATAIN +sink_data[43] => src0_data[43].DATAIN +sink_data[44] => src0_data[44].DATAIN +sink_data[45] => src0_data[45].DATAIN +sink_data[46] => src0_data[46].DATAIN +sink_data[47] => src0_data[47].DATAIN +sink_data[48] => src0_data[48].DATAIN +sink_data[49] => src0_data[49].DATAIN +sink_data[50] => src0_data[50].DATAIN +sink_data[51] => src0_data[51].DATAIN +sink_data[52] => src0_data[52].DATAIN +sink_data[53] => src0_data[53].DATAIN +sink_data[54] => src0_data[54].DATAIN +sink_data[55] => src0_data[55].DATAIN +sink_data[56] => src0_data[56].DATAIN +sink_data[57] => src0_data[57].DATAIN +sink_data[58] => src0_data[58].DATAIN +sink_data[59] => src0_data[59].DATAIN +sink_data[60] => src0_data[60].DATAIN +sink_data[61] => src0_data[61].DATAIN +sink_data[62] => src0_data[62].DATAIN +sink_data[63] => src0_data[63].DATAIN +sink_data[64] => src0_data[64].DATAIN +sink_data[65] => src0_data[65].DATAIN +sink_data[66] => src0_data[66].DATAIN +sink_data[67] => src0_data[67].DATAIN +sink_data[68] => src0_data[68].DATAIN +sink_data[69] => src0_data[69].DATAIN +sink_data[70] => src0_data[70].DATAIN +sink_data[71] => src0_data[71].DATAIN +sink_data[72] => src0_data[72].DATAIN +sink_data[73] => src0_data[73].DATAIN +sink_data[74] => src0_data[74].DATAIN +sink_data[75] => src0_data[75].DATAIN +sink_data[76] => src0_data[76].DATAIN +sink_data[77] => src0_data[77].DATAIN +sink_data[78] => src0_data[78].DATAIN +sink_data[79] => src0_data[79].DATAIN +sink_data[80] => src0_data[80].DATAIN +sink_data[81] => src0_data[81].DATAIN +sink_data[82] => src0_data[82].DATAIN +sink_data[83] => src0_data[83].DATAIN +sink_data[84] => src0_data[84].DATAIN +sink_data[85] => src0_data[85].DATAIN +sink_data[86] => src0_data[86].DATAIN +sink_data[87] => src0_data[87].DATAIN +sink_data[88] => src0_data[88].DATAIN +sink_data[89] => src0_data[89].DATAIN +sink_data[90] => src0_data[90].DATAIN +sink_data[91] => src0_data[91].DATAIN +sink_data[92] => src0_data[92].DATAIN +sink_data[93] => src0_data[93].DATAIN +sink_data[94] => src0_data[94].DATAIN +sink_data[95] => src0_data[95].DATAIN +sink_data[96] => src0_data[96].DATAIN +sink_data[97] => src0_data[97].DATAIN +sink_data[98] => src0_data[98].DATAIN +sink_data[99] => src0_data[99].DATAIN +sink_data[100] => src0_data[100].DATAIN +sink_channel[0] => src0_valid.IN1 +sink_channel[0] => sink_ready.IN0 +sink_channel[1] => src0_channel[0].DATAIN +sink_channel[2] => src0_channel[1].DATAIN +sink_channel[3] => src0_channel[2].DATAIN +sink_channel[4] => src0_channel[3].DATAIN +sink_channel[5] => src0_channel[4].DATAIN +sink_channel[6] => src0_channel[5].DATAIN +sink_channel[7] => src0_channel[6].DATAIN +sink_channel[8] => src0_channel[7].DATAIN +sink_channel[9] => src0_channel[8].DATAIN +sink_channel[10] => src0_channel[9].DATAIN +sink_startofpacket => src0_startofpacket.DATAIN +sink_endofpacket => src0_endofpacket.DATAIN +sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE +src0_valid <= src0_valid.DB_MAX_OUTPUT_PORT_TYPE +src0_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src0_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src0_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src0_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src0_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src0_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src0_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src0_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src0_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src0_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src0_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src0_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src0_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src0_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src0_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src0_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src0_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src0_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src0_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src0_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src0_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src0_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src0_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src0_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src0_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src0_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src0_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src0_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src0_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src0_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src0_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src0_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src0_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src0_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src0_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src0_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src0_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src0_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src0_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src0_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src0_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src0_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src0_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src0_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src0_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src0_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src0_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src0_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src0_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src0_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src0_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src0_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src0_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src0_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src0_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src0_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src0_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src0_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src0_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src0_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src0_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src0_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src0_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src0_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src0_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src0_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src0_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src0_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src0_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src0_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src0_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src0_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src0_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src0_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src0_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src0_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src0_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src0_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src0_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src0_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src0_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src0_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src0_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src0_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src0_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src0_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src0_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src0_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src0_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src0_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src0_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src0_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src0_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src0_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src0_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src0_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src0_data[96] <= sink_data[96].DB_MAX_OUTPUT_PORT_TYPE +src0_data[97] <= sink_data[97].DB_MAX_OUTPUT_PORT_TYPE +src0_data[98] <= sink_data[98].DB_MAX_OUTPUT_PORT_TYPE +src0_data[99] <= sink_data[99].DB_MAX_OUTPUT_PORT_TYPE +src0_data[100] <= sink_data[100].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[0] <= sink_channel[1].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[1] <= sink_channel[2].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[2] <= sink_channel[3].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[3] <= sink_channel[4].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[4] <= sink_channel[5].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[5] <= sink_channel[6].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[6] <= sink_channel[7].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[7] <= sink_channel[8].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[8] <= sink_channel[9].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[9] <= sink_channel[10].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[10] <= +src0_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src0_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src0_ready => sink_ready.IN1 +clk => ~NO_FANOUT~ +reset => ~NO_FANOUT~ + + +|de0_nano_system|system:inst_cpu|system_rsp_xbar_demux_002:rsp_xbar_demux_010 +sink_valid[0] => src0_valid.IN0 +sink_data[0] => src0_data[0].DATAIN +sink_data[1] => src0_data[1].DATAIN +sink_data[2] => src0_data[2].DATAIN +sink_data[3] => src0_data[3].DATAIN +sink_data[4] => src0_data[4].DATAIN +sink_data[5] => src0_data[5].DATAIN +sink_data[6] => src0_data[6].DATAIN +sink_data[7] => src0_data[7].DATAIN +sink_data[8] => src0_data[8].DATAIN +sink_data[9] => src0_data[9].DATAIN +sink_data[10] => src0_data[10].DATAIN +sink_data[11] => src0_data[11].DATAIN +sink_data[12] => src0_data[12].DATAIN +sink_data[13] => src0_data[13].DATAIN +sink_data[14] => src0_data[14].DATAIN +sink_data[15] => src0_data[15].DATAIN +sink_data[16] => src0_data[16].DATAIN +sink_data[17] => src0_data[17].DATAIN +sink_data[18] => src0_data[18].DATAIN +sink_data[19] => src0_data[19].DATAIN +sink_data[20] => src0_data[20].DATAIN +sink_data[21] => src0_data[21].DATAIN +sink_data[22] => src0_data[22].DATAIN +sink_data[23] => src0_data[23].DATAIN +sink_data[24] => src0_data[24].DATAIN +sink_data[25] => src0_data[25].DATAIN +sink_data[26] => src0_data[26].DATAIN +sink_data[27] => src0_data[27].DATAIN +sink_data[28] => src0_data[28].DATAIN +sink_data[29] => src0_data[29].DATAIN +sink_data[30] => src0_data[30].DATAIN +sink_data[31] => src0_data[31].DATAIN +sink_data[32] => src0_data[32].DATAIN +sink_data[33] => src0_data[33].DATAIN +sink_data[34] => src0_data[34].DATAIN +sink_data[35] => src0_data[35].DATAIN +sink_data[36] => src0_data[36].DATAIN +sink_data[37] => src0_data[37].DATAIN +sink_data[38] => src0_data[38].DATAIN +sink_data[39] => src0_data[39].DATAIN +sink_data[40] => src0_data[40].DATAIN +sink_data[41] => src0_data[41].DATAIN +sink_data[42] => src0_data[42].DATAIN +sink_data[43] => src0_data[43].DATAIN +sink_data[44] => src0_data[44].DATAIN +sink_data[45] => src0_data[45].DATAIN +sink_data[46] => src0_data[46].DATAIN +sink_data[47] => src0_data[47].DATAIN +sink_data[48] => src0_data[48].DATAIN +sink_data[49] => src0_data[49].DATAIN +sink_data[50] => src0_data[50].DATAIN +sink_data[51] => src0_data[51].DATAIN +sink_data[52] => src0_data[52].DATAIN +sink_data[53] => src0_data[53].DATAIN +sink_data[54] => src0_data[54].DATAIN +sink_data[55] => src0_data[55].DATAIN +sink_data[56] => src0_data[56].DATAIN +sink_data[57] => src0_data[57].DATAIN +sink_data[58] => src0_data[58].DATAIN +sink_data[59] => src0_data[59].DATAIN +sink_data[60] => src0_data[60].DATAIN +sink_data[61] => src0_data[61].DATAIN +sink_data[62] => src0_data[62].DATAIN +sink_data[63] => src0_data[63].DATAIN +sink_data[64] => src0_data[64].DATAIN +sink_data[65] => src0_data[65].DATAIN +sink_data[66] => src0_data[66].DATAIN +sink_data[67] => src0_data[67].DATAIN +sink_data[68] => src0_data[68].DATAIN +sink_data[69] => src0_data[69].DATAIN +sink_data[70] => src0_data[70].DATAIN +sink_data[71] => src0_data[71].DATAIN +sink_data[72] => src0_data[72].DATAIN +sink_data[73] => src0_data[73].DATAIN +sink_data[74] => src0_data[74].DATAIN +sink_data[75] => src0_data[75].DATAIN +sink_data[76] => src0_data[76].DATAIN +sink_data[77] => src0_data[77].DATAIN +sink_data[78] => src0_data[78].DATAIN +sink_data[79] => src0_data[79].DATAIN +sink_data[80] => src0_data[80].DATAIN +sink_data[81] => src0_data[81].DATAIN +sink_data[82] => src0_data[82].DATAIN +sink_data[83] => src0_data[83].DATAIN +sink_data[84] => src0_data[84].DATAIN +sink_data[85] => src0_data[85].DATAIN +sink_data[86] => src0_data[86].DATAIN +sink_data[87] => src0_data[87].DATAIN +sink_data[88] => src0_data[88].DATAIN +sink_data[89] => src0_data[89].DATAIN +sink_data[90] => src0_data[90].DATAIN +sink_data[91] => src0_data[91].DATAIN +sink_data[92] => src0_data[92].DATAIN +sink_data[93] => src0_data[93].DATAIN +sink_data[94] => src0_data[94].DATAIN +sink_data[95] => src0_data[95].DATAIN +sink_data[96] => src0_data[96].DATAIN +sink_data[97] => src0_data[97].DATAIN +sink_data[98] => src0_data[98].DATAIN +sink_data[99] => src0_data[99].DATAIN +sink_data[100] => src0_data[100].DATAIN +sink_channel[0] => src0_valid.IN1 +sink_channel[0] => sink_ready.IN0 +sink_channel[1] => src0_channel[0].DATAIN +sink_channel[2] => src0_channel[1].DATAIN +sink_channel[3] => src0_channel[2].DATAIN +sink_channel[4] => src0_channel[3].DATAIN +sink_channel[5] => src0_channel[4].DATAIN +sink_channel[6] => src0_channel[5].DATAIN +sink_channel[7] => src0_channel[6].DATAIN +sink_channel[8] => src0_channel[7].DATAIN +sink_channel[9] => src0_channel[8].DATAIN +sink_channel[10] => src0_channel[9].DATAIN +sink_startofpacket => src0_startofpacket.DATAIN +sink_endofpacket => src0_endofpacket.DATAIN +sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE +src0_valid <= src0_valid.DB_MAX_OUTPUT_PORT_TYPE +src0_data[0] <= sink_data[0].DB_MAX_OUTPUT_PORT_TYPE +src0_data[1] <= sink_data[1].DB_MAX_OUTPUT_PORT_TYPE +src0_data[2] <= sink_data[2].DB_MAX_OUTPUT_PORT_TYPE +src0_data[3] <= sink_data[3].DB_MAX_OUTPUT_PORT_TYPE +src0_data[4] <= sink_data[4].DB_MAX_OUTPUT_PORT_TYPE +src0_data[5] <= sink_data[5].DB_MAX_OUTPUT_PORT_TYPE +src0_data[6] <= sink_data[6].DB_MAX_OUTPUT_PORT_TYPE +src0_data[7] <= sink_data[7].DB_MAX_OUTPUT_PORT_TYPE +src0_data[8] <= sink_data[8].DB_MAX_OUTPUT_PORT_TYPE +src0_data[9] <= sink_data[9].DB_MAX_OUTPUT_PORT_TYPE +src0_data[10] <= sink_data[10].DB_MAX_OUTPUT_PORT_TYPE +src0_data[11] <= sink_data[11].DB_MAX_OUTPUT_PORT_TYPE +src0_data[12] <= sink_data[12].DB_MAX_OUTPUT_PORT_TYPE +src0_data[13] <= sink_data[13].DB_MAX_OUTPUT_PORT_TYPE +src0_data[14] <= sink_data[14].DB_MAX_OUTPUT_PORT_TYPE +src0_data[15] <= sink_data[15].DB_MAX_OUTPUT_PORT_TYPE +src0_data[16] <= sink_data[16].DB_MAX_OUTPUT_PORT_TYPE +src0_data[17] <= sink_data[17].DB_MAX_OUTPUT_PORT_TYPE +src0_data[18] <= sink_data[18].DB_MAX_OUTPUT_PORT_TYPE +src0_data[19] <= sink_data[19].DB_MAX_OUTPUT_PORT_TYPE +src0_data[20] <= sink_data[20].DB_MAX_OUTPUT_PORT_TYPE +src0_data[21] <= sink_data[21].DB_MAX_OUTPUT_PORT_TYPE +src0_data[22] <= sink_data[22].DB_MAX_OUTPUT_PORT_TYPE +src0_data[23] <= sink_data[23].DB_MAX_OUTPUT_PORT_TYPE +src0_data[24] <= sink_data[24].DB_MAX_OUTPUT_PORT_TYPE +src0_data[25] <= sink_data[25].DB_MAX_OUTPUT_PORT_TYPE +src0_data[26] <= sink_data[26].DB_MAX_OUTPUT_PORT_TYPE +src0_data[27] <= sink_data[27].DB_MAX_OUTPUT_PORT_TYPE +src0_data[28] <= sink_data[28].DB_MAX_OUTPUT_PORT_TYPE +src0_data[29] <= sink_data[29].DB_MAX_OUTPUT_PORT_TYPE +src0_data[30] <= sink_data[30].DB_MAX_OUTPUT_PORT_TYPE +src0_data[31] <= sink_data[31].DB_MAX_OUTPUT_PORT_TYPE +src0_data[32] <= sink_data[32].DB_MAX_OUTPUT_PORT_TYPE +src0_data[33] <= sink_data[33].DB_MAX_OUTPUT_PORT_TYPE +src0_data[34] <= sink_data[34].DB_MAX_OUTPUT_PORT_TYPE +src0_data[35] <= sink_data[35].DB_MAX_OUTPUT_PORT_TYPE +src0_data[36] <= sink_data[36].DB_MAX_OUTPUT_PORT_TYPE +src0_data[37] <= sink_data[37].DB_MAX_OUTPUT_PORT_TYPE +src0_data[38] <= sink_data[38].DB_MAX_OUTPUT_PORT_TYPE +src0_data[39] <= sink_data[39].DB_MAX_OUTPUT_PORT_TYPE +src0_data[40] <= sink_data[40].DB_MAX_OUTPUT_PORT_TYPE +src0_data[41] <= sink_data[41].DB_MAX_OUTPUT_PORT_TYPE +src0_data[42] <= sink_data[42].DB_MAX_OUTPUT_PORT_TYPE +src0_data[43] <= sink_data[43].DB_MAX_OUTPUT_PORT_TYPE +src0_data[44] <= sink_data[44].DB_MAX_OUTPUT_PORT_TYPE +src0_data[45] <= sink_data[45].DB_MAX_OUTPUT_PORT_TYPE +src0_data[46] <= sink_data[46].DB_MAX_OUTPUT_PORT_TYPE +src0_data[47] <= sink_data[47].DB_MAX_OUTPUT_PORT_TYPE +src0_data[48] <= sink_data[48].DB_MAX_OUTPUT_PORT_TYPE +src0_data[49] <= sink_data[49].DB_MAX_OUTPUT_PORT_TYPE +src0_data[50] <= sink_data[50].DB_MAX_OUTPUT_PORT_TYPE +src0_data[51] <= sink_data[51].DB_MAX_OUTPUT_PORT_TYPE +src0_data[52] <= sink_data[52].DB_MAX_OUTPUT_PORT_TYPE +src0_data[53] <= sink_data[53].DB_MAX_OUTPUT_PORT_TYPE +src0_data[54] <= sink_data[54].DB_MAX_OUTPUT_PORT_TYPE +src0_data[55] <= sink_data[55].DB_MAX_OUTPUT_PORT_TYPE +src0_data[56] <= sink_data[56].DB_MAX_OUTPUT_PORT_TYPE +src0_data[57] <= sink_data[57].DB_MAX_OUTPUT_PORT_TYPE +src0_data[58] <= sink_data[58].DB_MAX_OUTPUT_PORT_TYPE +src0_data[59] <= sink_data[59].DB_MAX_OUTPUT_PORT_TYPE +src0_data[60] <= sink_data[60].DB_MAX_OUTPUT_PORT_TYPE +src0_data[61] <= sink_data[61].DB_MAX_OUTPUT_PORT_TYPE +src0_data[62] <= sink_data[62].DB_MAX_OUTPUT_PORT_TYPE +src0_data[63] <= sink_data[63].DB_MAX_OUTPUT_PORT_TYPE +src0_data[64] <= sink_data[64].DB_MAX_OUTPUT_PORT_TYPE +src0_data[65] <= sink_data[65].DB_MAX_OUTPUT_PORT_TYPE +src0_data[66] <= sink_data[66].DB_MAX_OUTPUT_PORT_TYPE +src0_data[67] <= sink_data[67].DB_MAX_OUTPUT_PORT_TYPE +src0_data[68] <= sink_data[68].DB_MAX_OUTPUT_PORT_TYPE +src0_data[69] <= sink_data[69].DB_MAX_OUTPUT_PORT_TYPE +src0_data[70] <= sink_data[70].DB_MAX_OUTPUT_PORT_TYPE +src0_data[71] <= sink_data[71].DB_MAX_OUTPUT_PORT_TYPE +src0_data[72] <= sink_data[72].DB_MAX_OUTPUT_PORT_TYPE +src0_data[73] <= sink_data[73].DB_MAX_OUTPUT_PORT_TYPE +src0_data[74] <= sink_data[74].DB_MAX_OUTPUT_PORT_TYPE +src0_data[75] <= sink_data[75].DB_MAX_OUTPUT_PORT_TYPE +src0_data[76] <= sink_data[76].DB_MAX_OUTPUT_PORT_TYPE +src0_data[77] <= sink_data[77].DB_MAX_OUTPUT_PORT_TYPE +src0_data[78] <= sink_data[78].DB_MAX_OUTPUT_PORT_TYPE +src0_data[79] <= sink_data[79].DB_MAX_OUTPUT_PORT_TYPE +src0_data[80] <= sink_data[80].DB_MAX_OUTPUT_PORT_TYPE +src0_data[81] <= sink_data[81].DB_MAX_OUTPUT_PORT_TYPE +src0_data[82] <= sink_data[82].DB_MAX_OUTPUT_PORT_TYPE +src0_data[83] <= sink_data[83].DB_MAX_OUTPUT_PORT_TYPE +src0_data[84] <= sink_data[84].DB_MAX_OUTPUT_PORT_TYPE +src0_data[85] <= sink_data[85].DB_MAX_OUTPUT_PORT_TYPE +src0_data[86] <= sink_data[86].DB_MAX_OUTPUT_PORT_TYPE +src0_data[87] <= sink_data[87].DB_MAX_OUTPUT_PORT_TYPE +src0_data[88] <= sink_data[88].DB_MAX_OUTPUT_PORT_TYPE +src0_data[89] <= sink_data[89].DB_MAX_OUTPUT_PORT_TYPE +src0_data[90] <= sink_data[90].DB_MAX_OUTPUT_PORT_TYPE +src0_data[91] <= sink_data[91].DB_MAX_OUTPUT_PORT_TYPE +src0_data[92] <= sink_data[92].DB_MAX_OUTPUT_PORT_TYPE +src0_data[93] <= sink_data[93].DB_MAX_OUTPUT_PORT_TYPE +src0_data[94] <= sink_data[94].DB_MAX_OUTPUT_PORT_TYPE +src0_data[95] <= sink_data[95].DB_MAX_OUTPUT_PORT_TYPE +src0_data[96] <= sink_data[96].DB_MAX_OUTPUT_PORT_TYPE +src0_data[97] <= sink_data[97].DB_MAX_OUTPUT_PORT_TYPE +src0_data[98] <= sink_data[98].DB_MAX_OUTPUT_PORT_TYPE +src0_data[99] <= sink_data[99].DB_MAX_OUTPUT_PORT_TYPE +src0_data[100] <= sink_data[100].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[0] <= sink_channel[1].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[1] <= sink_channel[2].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[2] <= sink_channel[3].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[3] <= sink_channel[4].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[4] <= sink_channel[5].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[5] <= sink_channel[6].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[6] <= sink_channel[7].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[7] <= sink_channel[8].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[8] <= sink_channel[9].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[9] <= sink_channel[10].DB_MAX_OUTPUT_PORT_TYPE +src0_channel[10] <= +src0_startofpacket <= sink_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +src0_endofpacket <= sink_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +src0_ready => sink_ready.IN1 +clk => ~NO_FANOUT~ +reset => ~NO_FANOUT~ + + +|de0_nano_system|system:inst_cpu|system_rsp_xbar_mux:rsp_xbar_mux +sink0_valid => request[0].IN1 +sink0_data[0] => src_payload.IN1 +sink0_data[1] => src_payload.IN1 +sink0_data[2] => src_payload.IN1 +sink0_data[3] => src_payload.IN1 +sink0_data[4] => src_payload.IN1 +sink0_data[5] => src_payload.IN1 +sink0_data[6] => src_payload.IN1 +sink0_data[7] => src_payload.IN1 +sink0_data[8] => src_payload.IN1 +sink0_data[9] => src_payload.IN1 +sink0_data[10] => src_payload.IN1 +sink0_data[11] => src_payload.IN1 +sink0_data[12] => src_payload.IN1 +sink0_data[13] => src_payload.IN1 +sink0_data[14] => src_payload.IN1 +sink0_data[15] => src_payload.IN1 +sink0_data[16] => src_payload.IN1 +sink0_data[17] => src_payload.IN1 +sink0_data[18] => src_payload.IN1 +sink0_data[19] => src_payload.IN1 +sink0_data[20] => src_payload.IN1 +sink0_data[21] => src_payload.IN1 +sink0_data[22] => src_payload.IN1 +sink0_data[23] => src_payload.IN1 +sink0_data[24] => src_payload.IN1 +sink0_data[25] => src_payload.IN1 +sink0_data[26] => src_payload.IN1 +sink0_data[27] => src_payload.IN1 +sink0_data[28] => src_payload.IN1 +sink0_data[29] => src_payload.IN1 +sink0_data[30] => src_payload.IN1 +sink0_data[31] => src_payload.IN1 +sink0_data[32] => src_payload.IN1 +sink0_data[33] => src_payload.IN1 +sink0_data[34] => src_payload.IN1 +sink0_data[35] => src_payload.IN1 +sink0_data[36] => src_payload.IN1 +sink0_data[37] => src_payload.IN1 +sink0_data[38] => src_payload.IN1 +sink0_data[39] => src_payload.IN1 +sink0_data[40] => src_payload.IN1 +sink0_data[41] => src_payload.IN1 +sink0_data[42] => src_payload.IN1 +sink0_data[43] => src_payload.IN1 +sink0_data[44] => src_payload.IN1 +sink0_data[45] => src_payload.IN1 +sink0_data[46] => src_payload.IN1 +sink0_data[47] => src_payload.IN1 +sink0_data[48] => src_payload.IN1 +sink0_data[49] => src_payload.IN1 +sink0_data[50] => src_payload.IN1 +sink0_data[51] => src_payload.IN1 +sink0_data[52] => src_payload.IN1 +sink0_data[53] => src_payload.IN1 +sink0_data[54] => src_payload.IN1 +sink0_data[55] => src_payload.IN1 +sink0_data[56] => src_payload.IN1 +sink0_data[57] => src_payload.IN1 +sink0_data[58] => src_payload.IN1 +sink0_data[59] => src_payload.IN1 +sink0_data[60] => src_payload.IN1 +sink0_data[61] => src_payload.IN1 +sink0_data[62] => src_payload.IN1 +sink0_data[63] => src_payload.IN1 +sink0_data[64] => src_payload.IN1 +sink0_data[65] => src_payload.IN1 +sink0_data[66] => src_payload.IN1 +sink0_data[66] => last_cycle.IN1 +sink0_data[67] => src_payload.IN1 +sink0_data[68] => src_payload.IN1 +sink0_data[69] => src_payload.IN1 +sink0_data[70] => src_payload.IN1 +sink0_data[71] => src_payload.IN1 +sink0_data[72] => src_payload.IN1 +sink0_data[73] => src_payload.IN1 +sink0_data[74] => src_payload.IN1 +sink0_data[75] => src_payload.IN1 +sink0_data[76] => src_payload.IN1 +sink0_data[77] => src_payload.IN1 +sink0_data[78] => src_payload.IN1 +sink0_data[79] => src_payload.IN1 +sink0_data[80] => src_payload.IN1 +sink0_data[81] => src_payload.IN1 +sink0_data[82] => src_payload.IN1 +sink0_data[83] => src_payload.IN1 +sink0_data[84] => src_payload.IN1 +sink0_data[85] => src_payload.IN1 +sink0_data[86] => src_payload.IN1 +sink0_data[87] => src_payload.IN1 +sink0_data[88] => src_payload.IN1 +sink0_data[89] => src_payload.IN1 +sink0_data[90] => src_payload.IN1 +sink0_data[91] => src_payload.IN1 +sink0_data[92] => src_payload.IN1 +sink0_data[93] => src_payload.IN1 +sink0_data[94] => src_payload.IN1 +sink0_data[95] => src_payload.IN1 +sink0_data[96] => src_payload.IN1 +sink0_data[97] => src_payload.IN1 +sink0_data[98] => src_payload.IN1 +sink0_data[99] => src_payload.IN1 +sink0_data[100] => src_payload.IN1 +sink0_channel[0] => src_payload.IN1 +sink0_channel[1] => src_payload.IN1 +sink0_channel[2] => src_payload.IN1 +sink0_channel[3] => src_payload.IN1 +sink0_channel[4] => src_payload.IN1 +sink0_channel[5] => src_payload.IN1 +sink0_channel[6] => src_payload.IN1 +sink0_channel[7] => src_payload.IN1 +sink0_channel[8] => src_payload.IN1 +sink0_channel[9] => src_payload.IN1 +sink0_channel[10] => src_payload.IN1 +sink0_startofpacket => src_payload.IN1 +sink0_endofpacket => src_payload.IN1 +sink0_ready <= sink0_ready.DB_MAX_OUTPUT_PORT_TYPE +sink1_valid => request[1].IN1 +sink1_data[0] => src_payload.IN1 +sink1_data[1] => src_payload.IN1 +sink1_data[2] => src_payload.IN1 +sink1_data[3] => src_payload.IN1 +sink1_data[4] => src_payload.IN1 +sink1_data[5] => src_payload.IN1 +sink1_data[6] => src_payload.IN1 +sink1_data[7] => src_payload.IN1 +sink1_data[8] => src_payload.IN1 +sink1_data[9] => src_payload.IN1 +sink1_data[10] => src_payload.IN1 +sink1_data[11] => src_payload.IN1 +sink1_data[12] => src_payload.IN1 +sink1_data[13] => src_payload.IN1 +sink1_data[14] => src_payload.IN1 +sink1_data[15] => src_payload.IN1 +sink1_data[16] => src_payload.IN1 +sink1_data[17] => src_payload.IN1 +sink1_data[18] => src_payload.IN1 +sink1_data[19] => src_payload.IN1 +sink1_data[20] => src_payload.IN1 +sink1_data[21] => src_payload.IN1 +sink1_data[22] => src_payload.IN1 +sink1_data[23] => src_payload.IN1 +sink1_data[24] => src_payload.IN1 +sink1_data[25] => src_payload.IN1 +sink1_data[26] => src_payload.IN1 +sink1_data[27] => src_payload.IN1 +sink1_data[28] => src_payload.IN1 +sink1_data[29] => src_payload.IN1 +sink1_data[30] => src_payload.IN1 +sink1_data[31] => src_payload.IN1 +sink1_data[32] => src_payload.IN1 +sink1_data[33] => src_payload.IN1 +sink1_data[34] => src_payload.IN1 +sink1_data[35] => src_payload.IN1 +sink1_data[36] => src_payload.IN1 +sink1_data[37] => src_payload.IN1 +sink1_data[38] => src_payload.IN1 +sink1_data[39] => src_payload.IN1 +sink1_data[40] => src_payload.IN1 +sink1_data[41] => src_payload.IN1 +sink1_data[42] => src_payload.IN1 +sink1_data[43] => src_payload.IN1 +sink1_data[44] => src_payload.IN1 +sink1_data[45] => src_payload.IN1 +sink1_data[46] => src_payload.IN1 +sink1_data[47] => src_payload.IN1 +sink1_data[48] => src_payload.IN1 +sink1_data[49] => src_payload.IN1 +sink1_data[50] => src_payload.IN1 +sink1_data[51] => src_payload.IN1 +sink1_data[52] => src_payload.IN1 +sink1_data[53] => src_payload.IN1 +sink1_data[54] => src_payload.IN1 +sink1_data[55] => src_payload.IN1 +sink1_data[56] => src_payload.IN1 +sink1_data[57] => src_payload.IN1 +sink1_data[58] => src_payload.IN1 +sink1_data[59] => src_payload.IN1 +sink1_data[60] => src_payload.IN1 +sink1_data[61] => src_payload.IN1 +sink1_data[62] => src_payload.IN1 +sink1_data[63] => src_payload.IN1 +sink1_data[64] => src_payload.IN1 +sink1_data[65] => src_payload.IN1 +sink1_data[66] => src_payload.IN1 +sink1_data[66] => last_cycle.IN1 +sink1_data[67] => src_payload.IN1 +sink1_data[68] => src_payload.IN1 +sink1_data[69] => src_payload.IN1 +sink1_data[70] => src_payload.IN1 +sink1_data[71] => src_payload.IN1 +sink1_data[72] => src_payload.IN1 +sink1_data[73] => src_payload.IN1 +sink1_data[74] => src_payload.IN1 +sink1_data[75] => src_payload.IN1 +sink1_data[76] => src_payload.IN1 +sink1_data[77] => src_payload.IN1 +sink1_data[78] => src_payload.IN1 +sink1_data[79] => src_payload.IN1 +sink1_data[80] => src_payload.IN1 +sink1_data[81] => src_payload.IN1 +sink1_data[82] => src_payload.IN1 +sink1_data[83] => src_payload.IN1 +sink1_data[84] => src_payload.IN1 +sink1_data[85] => src_payload.IN1 +sink1_data[86] => src_payload.IN1 +sink1_data[87] => src_payload.IN1 +sink1_data[88] => src_payload.IN1 +sink1_data[89] => src_payload.IN1 +sink1_data[90] => src_payload.IN1 +sink1_data[91] => src_payload.IN1 +sink1_data[92] => src_payload.IN1 +sink1_data[93] => src_payload.IN1 +sink1_data[94] => src_payload.IN1 +sink1_data[95] => src_payload.IN1 +sink1_data[96] => src_payload.IN1 +sink1_data[97] => src_payload.IN1 +sink1_data[98] => src_payload.IN1 +sink1_data[99] => src_payload.IN1 +sink1_data[100] => src_payload.IN1 +sink1_channel[0] => src_payload.IN1 +sink1_channel[1] => src_payload.IN1 +sink1_channel[2] => src_payload.IN1 +sink1_channel[3] => src_payload.IN1 +sink1_channel[4] => src_payload.IN1 +sink1_channel[5] => src_payload.IN1 +sink1_channel[6] => src_payload.IN1 +sink1_channel[7] => src_payload.IN1 +sink1_channel[8] => src_payload.IN1 +sink1_channel[9] => src_payload.IN1 +sink1_channel[10] => src_payload.IN1 +sink1_startofpacket => src_payload.IN1 +sink1_endofpacket => src_payload.IN1 +sink1_ready <= sink1_ready.DB_MAX_OUTPUT_PORT_TYPE +src_valid <= src_valid.DB_MAX_OUTPUT_PORT_TYPE +src_data[0] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[1] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[2] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[3] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[4] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[5] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[6] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[7] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[8] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[9] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[10] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[11] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[12] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[13] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[14] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[15] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[16] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[17] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[18] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[19] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[20] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[21] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[22] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[23] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[24] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[25] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[26] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[27] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[28] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[29] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[30] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[31] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[32] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[33] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[34] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[35] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[36] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[37] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[38] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[39] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[40] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[41] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[42] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[43] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[44] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[45] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[46] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[47] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[48] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[49] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[50] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[51] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[52] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[53] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[54] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[55] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[56] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[57] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[58] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[59] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[60] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[61] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[62] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[63] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[64] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[65] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[66] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[67] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[68] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[69] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[70] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[71] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[72] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[73] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[74] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[75] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[76] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[77] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[78] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[79] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[80] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[81] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[82] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[83] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[84] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[85] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[86] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[87] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[88] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[89] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[90] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[91] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[92] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[93] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[94] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[95] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[96] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[97] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[98] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[99] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[100] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[0] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[1] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[2] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[3] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[4] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[5] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[6] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[7] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[8] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[9] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[10] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_startofpacket <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_endofpacket <= src_payload[0].DB_MAX_OUTPUT_PORT_TYPE +src_ready => last_cycle.IN0 +src_ready => sink0_ready.IN1 +src_ready => sink1_ready.IN1 +clk => clk.IN1 +reset => reset.IN1 + + +|de0_nano_system|system:inst_cpu|system_rsp_xbar_mux:rsp_xbar_mux|altera_merlin_arbitrator:arb +clk => ~NO_FANOUT~ +reset => ~NO_FANOUT~ +request[0] => grant[0].DATAIN +request[0] => _.IN1 +request[0] => _.IN1 +request[1] => grant[1].DATAIN +request[1] => _.IN1 +request[1] => _.IN1 +grant[0] <= request[0].DB_MAX_OUTPUT_PORT_TYPE +grant[1] <= request[1].DB_MAX_OUTPUT_PORT_TYPE +increment_top_priority => ~NO_FANOUT~ +save_top_priority => ~NO_FANOUT~ + + +|de0_nano_system|system:inst_cpu|system_rsp_xbar_mux:rsp_xbar_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder +a[0] => sum.IN0 +a[0] => full_adder.cout[0].IN0 +a[1] => cout.IN0 +a[1] => cout.IN0 +a[2] => cout.IN0 +a[2] => cout.IN0 +a[3] => sum.IN0 +b[0] => sum.IN1 +b[0] => full_adder.cout[0].IN1 +b[1] => cout.IN1 +b[1] => cout.IN1 +b[2] => cout.IN1 +b[2] => cout.IN1 +b[3] => sum.IN1 +sum[0] <= sum.DB_MAX_OUTPUT_PORT_TYPE +sum[1] <= sum.DB_MAX_OUTPUT_PORT_TYPE +sum[2] <= sum.DB_MAX_OUTPUT_PORT_TYPE +sum[3] <= sum.DB_MAX_OUTPUT_PORT_TYPE + + +|de0_nano_system|system:inst_cpu|system_rsp_xbar_mux_001:rsp_xbar_mux_001 +sink0_valid => request[0].IN1 +sink0_data[0] => src_payload.IN1 +sink0_data[1] => src_payload.IN1 +sink0_data[2] => src_payload.IN1 +sink0_data[3] => src_payload.IN1 +sink0_data[4] => src_payload.IN1 +sink0_data[5] => src_payload.IN1 +sink0_data[6] => src_payload.IN1 +sink0_data[7] => src_payload.IN1 +sink0_data[8] => src_payload.IN1 +sink0_data[9] => src_payload.IN1 +sink0_data[10] => src_payload.IN1 +sink0_data[11] => src_payload.IN1 +sink0_data[12] => src_payload.IN1 +sink0_data[13] => src_payload.IN1 +sink0_data[14] => src_payload.IN1 +sink0_data[15] => src_payload.IN1 +sink0_data[16] => src_payload.IN1 +sink0_data[17] => src_payload.IN1 +sink0_data[18] => src_payload.IN1 +sink0_data[19] => src_payload.IN1 +sink0_data[20] => src_payload.IN1 +sink0_data[21] => src_payload.IN1 +sink0_data[22] => src_payload.IN1 +sink0_data[23] => src_payload.IN1 +sink0_data[24] => src_payload.IN1 +sink0_data[25] => src_payload.IN1 +sink0_data[26] => src_payload.IN1 +sink0_data[27] => src_payload.IN1 +sink0_data[28] => src_payload.IN1 +sink0_data[29] => src_payload.IN1 +sink0_data[30] => src_payload.IN1 +sink0_data[31] => src_payload.IN1 +sink0_data[32] => src_payload.IN1 +sink0_data[33] => src_payload.IN1 +sink0_data[34] => src_payload.IN1 +sink0_data[35] => src_payload.IN1 +sink0_data[36] => src_payload.IN1 +sink0_data[37] => src_payload.IN1 +sink0_data[38] => src_payload.IN1 +sink0_data[39] => src_payload.IN1 +sink0_data[40] => src_payload.IN1 +sink0_data[41] => src_payload.IN1 +sink0_data[42] => src_payload.IN1 +sink0_data[43] => src_payload.IN1 +sink0_data[44] => src_payload.IN1 +sink0_data[45] => src_payload.IN1 +sink0_data[46] => src_payload.IN1 +sink0_data[47] => src_payload.IN1 +sink0_data[48] => src_payload.IN1 +sink0_data[49] => src_payload.IN1 +sink0_data[50] => src_payload.IN1 +sink0_data[51] => src_payload.IN1 +sink0_data[52] => src_payload.IN1 +sink0_data[53] => src_payload.IN1 +sink0_data[54] => src_payload.IN1 +sink0_data[55] => src_payload.IN1 +sink0_data[56] => src_payload.IN1 +sink0_data[57] => src_payload.IN1 +sink0_data[58] => src_payload.IN1 +sink0_data[59] => src_payload.IN1 +sink0_data[60] => src_payload.IN1 +sink0_data[61] => src_payload.IN1 +sink0_data[62] => src_payload.IN1 +sink0_data[63] => src_payload.IN1 +sink0_data[64] => src_payload.IN1 +sink0_data[65] => src_payload.IN1 +sink0_data[66] => src_payload.IN1 +sink0_data[66] => last_cycle.IN1 +sink0_data[67] => src_payload.IN1 +sink0_data[68] => src_payload.IN1 +sink0_data[69] => src_payload.IN1 +sink0_data[70] => src_payload.IN1 +sink0_data[71] => src_payload.IN1 +sink0_data[72] => src_payload.IN1 +sink0_data[73] => src_payload.IN1 +sink0_data[74] => src_payload.IN1 +sink0_data[75] => src_payload.IN1 +sink0_data[76] => src_payload.IN1 +sink0_data[77] => src_payload.IN1 +sink0_data[78] => src_payload.IN1 +sink0_data[79] => src_payload.IN1 +sink0_data[80] => src_payload.IN1 +sink0_data[81] => src_payload.IN1 +sink0_data[82] => src_payload.IN1 +sink0_data[83] => src_payload.IN1 +sink0_data[84] => src_payload.IN1 +sink0_data[85] => src_payload.IN1 +sink0_data[86] => src_payload.IN1 +sink0_data[87] => src_payload.IN1 +sink0_data[88] => src_payload.IN1 +sink0_data[89] => src_payload.IN1 +sink0_data[90] => src_payload.IN1 +sink0_data[91] => src_payload.IN1 +sink0_data[92] => src_payload.IN1 +sink0_data[93] => src_payload.IN1 +sink0_data[94] => src_payload.IN1 +sink0_data[95] => src_payload.IN1 +sink0_data[96] => src_payload.IN1 +sink0_data[97] => src_payload.IN1 +sink0_data[98] => src_payload.IN1 +sink0_data[99] => src_payload.IN1 +sink0_data[100] => src_payload.IN1 +sink0_channel[0] => src_payload.IN1 +sink0_channel[1] => src_payload.IN1 +sink0_channel[2] => src_payload.IN1 +sink0_channel[3] => src_payload.IN1 +sink0_channel[4] => src_payload.IN1 +sink0_channel[5] => src_payload.IN1 +sink0_channel[6] => src_payload.IN1 +sink0_channel[7] => src_payload.IN1 +sink0_channel[8] => src_payload.IN1 +sink0_channel[9] => src_payload.IN1 +sink0_channel[10] => src_payload.IN1 +sink0_startofpacket => src_payload.IN1 +sink0_endofpacket => src_payload.IN1 +sink0_ready <= sink0_ready.DB_MAX_OUTPUT_PORT_TYPE +sink1_valid => request[1].IN1 +sink1_data[0] => src_payload.IN1 +sink1_data[1] => src_payload.IN1 +sink1_data[2] => src_payload.IN1 +sink1_data[3] => src_payload.IN1 +sink1_data[4] => src_payload.IN1 +sink1_data[5] => src_payload.IN1 +sink1_data[6] => src_payload.IN1 +sink1_data[7] => src_payload.IN1 +sink1_data[8] => src_payload.IN1 +sink1_data[9] => src_payload.IN1 +sink1_data[10] => src_payload.IN1 +sink1_data[11] => src_payload.IN1 +sink1_data[12] => src_payload.IN1 +sink1_data[13] => src_payload.IN1 +sink1_data[14] => src_payload.IN1 +sink1_data[15] => src_payload.IN1 +sink1_data[16] => src_payload.IN1 +sink1_data[17] => src_payload.IN1 +sink1_data[18] => src_payload.IN1 +sink1_data[19] => src_payload.IN1 +sink1_data[20] => src_payload.IN1 +sink1_data[21] => src_payload.IN1 +sink1_data[22] => src_payload.IN1 +sink1_data[23] => src_payload.IN1 +sink1_data[24] => src_payload.IN1 +sink1_data[25] => src_payload.IN1 +sink1_data[26] => src_payload.IN1 +sink1_data[27] => src_payload.IN1 +sink1_data[28] => src_payload.IN1 +sink1_data[29] => src_payload.IN1 +sink1_data[30] => src_payload.IN1 +sink1_data[31] => src_payload.IN1 +sink1_data[32] => src_payload.IN1 +sink1_data[33] => src_payload.IN1 +sink1_data[34] => src_payload.IN1 +sink1_data[35] => src_payload.IN1 +sink1_data[36] => src_payload.IN1 +sink1_data[37] => src_payload.IN1 +sink1_data[38] => src_payload.IN1 +sink1_data[39] => src_payload.IN1 +sink1_data[40] => src_payload.IN1 +sink1_data[41] => src_payload.IN1 +sink1_data[42] => src_payload.IN1 +sink1_data[43] => src_payload.IN1 +sink1_data[44] => src_payload.IN1 +sink1_data[45] => src_payload.IN1 +sink1_data[46] => src_payload.IN1 +sink1_data[47] => src_payload.IN1 +sink1_data[48] => src_payload.IN1 +sink1_data[49] => src_payload.IN1 +sink1_data[50] => src_payload.IN1 +sink1_data[51] => src_payload.IN1 +sink1_data[52] => src_payload.IN1 +sink1_data[53] => src_payload.IN1 +sink1_data[54] => src_payload.IN1 +sink1_data[55] => src_payload.IN1 +sink1_data[56] => src_payload.IN1 +sink1_data[57] => src_payload.IN1 +sink1_data[58] => src_payload.IN1 +sink1_data[59] => src_payload.IN1 +sink1_data[60] => src_payload.IN1 +sink1_data[61] => src_payload.IN1 +sink1_data[62] => src_payload.IN1 +sink1_data[63] => src_payload.IN1 +sink1_data[64] => src_payload.IN1 +sink1_data[65] => src_payload.IN1 +sink1_data[66] => src_payload.IN1 +sink1_data[66] => last_cycle.IN1 +sink1_data[67] => src_payload.IN1 +sink1_data[68] => src_payload.IN1 +sink1_data[69] => src_payload.IN1 +sink1_data[70] => src_payload.IN1 +sink1_data[71] => src_payload.IN1 +sink1_data[72] => src_payload.IN1 +sink1_data[73] => src_payload.IN1 +sink1_data[74] => src_payload.IN1 +sink1_data[75] => src_payload.IN1 +sink1_data[76] => src_payload.IN1 +sink1_data[77] => src_payload.IN1 +sink1_data[78] => src_payload.IN1 +sink1_data[79] => src_payload.IN1 +sink1_data[80] => src_payload.IN1 +sink1_data[81] => src_payload.IN1 +sink1_data[82] => src_payload.IN1 +sink1_data[83] => src_payload.IN1 +sink1_data[84] => src_payload.IN1 +sink1_data[85] => src_payload.IN1 +sink1_data[86] => src_payload.IN1 +sink1_data[87] => src_payload.IN1 +sink1_data[88] => src_payload.IN1 +sink1_data[89] => src_payload.IN1 +sink1_data[90] => src_payload.IN1 +sink1_data[91] => src_payload.IN1 +sink1_data[92] => src_payload.IN1 +sink1_data[93] => src_payload.IN1 +sink1_data[94] => src_payload.IN1 +sink1_data[95] => src_payload.IN1 +sink1_data[96] => src_payload.IN1 +sink1_data[97] => src_payload.IN1 +sink1_data[98] => src_payload.IN1 +sink1_data[99] => src_payload.IN1 +sink1_data[100] => src_payload.IN1 +sink1_channel[0] => src_payload.IN1 +sink1_channel[1] => src_payload.IN1 +sink1_channel[2] => src_payload.IN1 +sink1_channel[3] => src_payload.IN1 +sink1_channel[4] => src_payload.IN1 +sink1_channel[5] => src_payload.IN1 +sink1_channel[6] => src_payload.IN1 +sink1_channel[7] => src_payload.IN1 +sink1_channel[8] => src_payload.IN1 +sink1_channel[9] => src_payload.IN1 +sink1_channel[10] => src_payload.IN1 +sink1_startofpacket => src_payload.IN1 +sink1_endofpacket => src_payload.IN1 +sink1_ready <= sink1_ready.DB_MAX_OUTPUT_PORT_TYPE +sink2_valid => request[2].IN1 +sink2_data[0] => src_payload.IN1 +sink2_data[1] => src_payload.IN1 +sink2_data[2] => src_payload.IN1 +sink2_data[3] => src_payload.IN1 +sink2_data[4] => src_payload.IN1 +sink2_data[5] => src_payload.IN1 +sink2_data[6] => src_payload.IN1 +sink2_data[7] => src_payload.IN1 +sink2_data[8] => src_payload.IN1 +sink2_data[9] => src_payload.IN1 +sink2_data[10] => src_payload.IN1 +sink2_data[11] => src_payload.IN1 +sink2_data[12] => src_payload.IN1 +sink2_data[13] => src_payload.IN1 +sink2_data[14] => src_payload.IN1 +sink2_data[15] => src_payload.IN1 +sink2_data[16] => src_payload.IN1 +sink2_data[17] => src_payload.IN1 +sink2_data[18] => src_payload.IN1 +sink2_data[19] => src_payload.IN1 +sink2_data[20] => src_payload.IN1 +sink2_data[21] => src_payload.IN1 +sink2_data[22] => src_payload.IN1 +sink2_data[23] => src_payload.IN1 +sink2_data[24] => src_payload.IN1 +sink2_data[25] => src_payload.IN1 +sink2_data[26] => src_payload.IN1 +sink2_data[27] => src_payload.IN1 +sink2_data[28] => src_payload.IN1 +sink2_data[29] => src_payload.IN1 +sink2_data[30] => src_payload.IN1 +sink2_data[31] => src_payload.IN1 +sink2_data[32] => src_payload.IN1 +sink2_data[33] => src_payload.IN1 +sink2_data[34] => src_payload.IN1 +sink2_data[35] => src_payload.IN1 +sink2_data[36] => src_payload.IN1 +sink2_data[37] => src_payload.IN1 +sink2_data[38] => src_payload.IN1 +sink2_data[39] => src_payload.IN1 +sink2_data[40] => src_payload.IN1 +sink2_data[41] => src_payload.IN1 +sink2_data[42] => src_payload.IN1 +sink2_data[43] => src_payload.IN1 +sink2_data[44] => src_payload.IN1 +sink2_data[45] => src_payload.IN1 +sink2_data[46] => src_payload.IN1 +sink2_data[47] => src_payload.IN1 +sink2_data[48] => src_payload.IN1 +sink2_data[49] => src_payload.IN1 +sink2_data[50] => src_payload.IN1 +sink2_data[51] => src_payload.IN1 +sink2_data[52] => src_payload.IN1 +sink2_data[53] => src_payload.IN1 +sink2_data[54] => src_payload.IN1 +sink2_data[55] => src_payload.IN1 +sink2_data[56] => src_payload.IN1 +sink2_data[57] => src_payload.IN1 +sink2_data[58] => src_payload.IN1 +sink2_data[59] => src_payload.IN1 +sink2_data[60] => src_payload.IN1 +sink2_data[61] => src_payload.IN1 +sink2_data[62] => src_payload.IN1 +sink2_data[63] => src_payload.IN1 +sink2_data[64] => src_payload.IN1 +sink2_data[65] => src_payload.IN1 +sink2_data[66] => src_payload.IN1 +sink2_data[66] => last_cycle.IN1 +sink2_data[67] => src_payload.IN1 +sink2_data[68] => src_payload.IN1 +sink2_data[69] => src_payload.IN1 +sink2_data[70] => src_payload.IN1 +sink2_data[71] => src_payload.IN1 +sink2_data[72] => src_payload.IN1 +sink2_data[73] => src_payload.IN1 +sink2_data[74] => src_payload.IN1 +sink2_data[75] => src_payload.IN1 +sink2_data[76] => src_payload.IN1 +sink2_data[77] => src_payload.IN1 +sink2_data[78] => src_payload.IN1 +sink2_data[79] => src_payload.IN1 +sink2_data[80] => src_payload.IN1 +sink2_data[81] => src_payload.IN1 +sink2_data[82] => src_payload.IN1 +sink2_data[83] => src_payload.IN1 +sink2_data[84] => src_payload.IN1 +sink2_data[85] => src_payload.IN1 +sink2_data[86] => src_payload.IN1 +sink2_data[87] => src_payload.IN1 +sink2_data[88] => src_payload.IN1 +sink2_data[89] => src_payload.IN1 +sink2_data[90] => src_payload.IN1 +sink2_data[91] => src_payload.IN1 +sink2_data[92] => src_payload.IN1 +sink2_data[93] => src_payload.IN1 +sink2_data[94] => src_payload.IN1 +sink2_data[95] => src_payload.IN1 +sink2_data[96] => src_payload.IN1 +sink2_data[97] => src_payload.IN1 +sink2_data[98] => src_payload.IN1 +sink2_data[99] => src_payload.IN1 +sink2_data[100] => src_payload.IN1 +sink2_channel[0] => src_payload.IN1 +sink2_channel[1] => src_payload.IN1 +sink2_channel[2] => src_payload.IN1 +sink2_channel[3] => src_payload.IN1 +sink2_channel[4] => src_payload.IN1 +sink2_channel[5] => src_payload.IN1 +sink2_channel[6] => src_payload.IN1 +sink2_channel[7] => src_payload.IN1 +sink2_channel[8] => src_payload.IN1 +sink2_channel[9] => src_payload.IN1 +sink2_channel[10] => src_payload.IN1 +sink2_startofpacket => src_payload.IN1 +sink2_endofpacket => src_payload.IN1 +sink2_ready <= sink2_ready.DB_MAX_OUTPUT_PORT_TYPE +sink3_valid => request[3].IN1 +sink3_data[0] => src_payload.IN1 +sink3_data[1] => src_payload.IN1 +sink3_data[2] => src_payload.IN1 +sink3_data[3] => src_payload.IN1 +sink3_data[4] => src_payload.IN1 +sink3_data[5] => src_payload.IN1 +sink3_data[6] => src_payload.IN1 +sink3_data[7] => src_payload.IN1 +sink3_data[8] => src_payload.IN1 +sink3_data[9] => src_payload.IN1 +sink3_data[10] => src_payload.IN1 +sink3_data[11] => src_payload.IN1 +sink3_data[12] => src_payload.IN1 +sink3_data[13] => src_payload.IN1 +sink3_data[14] => src_payload.IN1 +sink3_data[15] => src_payload.IN1 +sink3_data[16] => src_payload.IN1 +sink3_data[17] => src_payload.IN1 +sink3_data[18] => src_payload.IN1 +sink3_data[19] => src_payload.IN1 +sink3_data[20] => src_payload.IN1 +sink3_data[21] => src_payload.IN1 +sink3_data[22] => src_payload.IN1 +sink3_data[23] => src_payload.IN1 +sink3_data[24] => src_payload.IN1 +sink3_data[25] => src_payload.IN1 +sink3_data[26] => src_payload.IN1 +sink3_data[27] => src_payload.IN1 +sink3_data[28] => src_payload.IN1 +sink3_data[29] => src_payload.IN1 +sink3_data[30] => src_payload.IN1 +sink3_data[31] => src_payload.IN1 +sink3_data[32] => src_payload.IN1 +sink3_data[33] => src_payload.IN1 +sink3_data[34] => src_payload.IN1 +sink3_data[35] => src_payload.IN1 +sink3_data[36] => src_payload.IN1 +sink3_data[37] => src_payload.IN1 +sink3_data[38] => src_payload.IN1 +sink3_data[39] => src_payload.IN1 +sink3_data[40] => src_payload.IN1 +sink3_data[41] => src_payload.IN1 +sink3_data[42] => src_payload.IN1 +sink3_data[43] => src_payload.IN1 +sink3_data[44] => src_payload.IN1 +sink3_data[45] => src_payload.IN1 +sink3_data[46] => src_payload.IN1 +sink3_data[47] => src_payload.IN1 +sink3_data[48] => src_payload.IN1 +sink3_data[49] => src_payload.IN1 +sink3_data[50] => src_payload.IN1 +sink3_data[51] => src_payload.IN1 +sink3_data[52] => src_payload.IN1 +sink3_data[53] => src_payload.IN1 +sink3_data[54] => src_payload.IN1 +sink3_data[55] => src_payload.IN1 +sink3_data[56] => src_payload.IN1 +sink3_data[57] => src_payload.IN1 +sink3_data[58] => src_payload.IN1 +sink3_data[59] => src_payload.IN1 +sink3_data[60] => src_payload.IN1 +sink3_data[61] => src_payload.IN1 +sink3_data[62] => src_payload.IN1 +sink3_data[63] => src_payload.IN1 +sink3_data[64] => src_payload.IN1 +sink3_data[65] => src_payload.IN1 +sink3_data[66] => src_payload.IN1 +sink3_data[66] => last_cycle.IN1 +sink3_data[67] => src_payload.IN1 +sink3_data[68] => src_payload.IN1 +sink3_data[69] => src_payload.IN1 +sink3_data[70] => src_payload.IN1 +sink3_data[71] => src_payload.IN1 +sink3_data[72] => src_payload.IN1 +sink3_data[73] => src_payload.IN1 +sink3_data[74] => src_payload.IN1 +sink3_data[75] => src_payload.IN1 +sink3_data[76] => src_payload.IN1 +sink3_data[77] => src_payload.IN1 +sink3_data[78] => src_payload.IN1 +sink3_data[79] => src_payload.IN1 +sink3_data[80] => src_payload.IN1 +sink3_data[81] => src_payload.IN1 +sink3_data[82] => src_payload.IN1 +sink3_data[83] => src_payload.IN1 +sink3_data[84] => src_payload.IN1 +sink3_data[85] => src_payload.IN1 +sink3_data[86] => src_payload.IN1 +sink3_data[87] => src_payload.IN1 +sink3_data[88] => src_payload.IN1 +sink3_data[89] => src_payload.IN1 +sink3_data[90] => src_payload.IN1 +sink3_data[91] => src_payload.IN1 +sink3_data[92] => src_payload.IN1 +sink3_data[93] => src_payload.IN1 +sink3_data[94] => src_payload.IN1 +sink3_data[95] => src_payload.IN1 +sink3_data[96] => src_payload.IN1 +sink3_data[97] => src_payload.IN1 +sink3_data[98] => src_payload.IN1 +sink3_data[99] => src_payload.IN1 +sink3_data[100] => src_payload.IN1 +sink3_channel[0] => src_payload.IN1 +sink3_channel[1] => src_payload.IN1 +sink3_channel[2] => src_payload.IN1 +sink3_channel[3] => src_payload.IN1 +sink3_channel[4] => src_payload.IN1 +sink3_channel[5] => src_payload.IN1 +sink3_channel[6] => src_payload.IN1 +sink3_channel[7] => src_payload.IN1 +sink3_channel[8] => src_payload.IN1 +sink3_channel[9] => src_payload.IN1 +sink3_channel[10] => src_payload.IN1 +sink3_startofpacket => src_payload.IN1 +sink3_endofpacket => src_payload.IN1 +sink3_ready <= sink3_ready.DB_MAX_OUTPUT_PORT_TYPE +sink4_valid => request[4].IN1 +sink4_data[0] => src_payload.IN1 +sink4_data[1] => src_payload.IN1 +sink4_data[2] => src_payload.IN1 +sink4_data[3] => src_payload.IN1 +sink4_data[4] => src_payload.IN1 +sink4_data[5] => src_payload.IN1 +sink4_data[6] => src_payload.IN1 +sink4_data[7] => src_payload.IN1 +sink4_data[8] => src_payload.IN1 +sink4_data[9] => src_payload.IN1 +sink4_data[10] => src_payload.IN1 +sink4_data[11] => src_payload.IN1 +sink4_data[12] => src_payload.IN1 +sink4_data[13] => src_payload.IN1 +sink4_data[14] => src_payload.IN1 +sink4_data[15] => src_payload.IN1 +sink4_data[16] => src_payload.IN1 +sink4_data[17] => src_payload.IN1 +sink4_data[18] => src_payload.IN1 +sink4_data[19] => src_payload.IN1 +sink4_data[20] => src_payload.IN1 +sink4_data[21] => src_payload.IN1 +sink4_data[22] => src_payload.IN1 +sink4_data[23] => src_payload.IN1 +sink4_data[24] => src_payload.IN1 +sink4_data[25] => src_payload.IN1 +sink4_data[26] => src_payload.IN1 +sink4_data[27] => src_payload.IN1 +sink4_data[28] => src_payload.IN1 +sink4_data[29] => src_payload.IN1 +sink4_data[30] => src_payload.IN1 +sink4_data[31] => src_payload.IN1 +sink4_data[32] => src_payload.IN1 +sink4_data[33] => src_payload.IN1 +sink4_data[34] => src_payload.IN1 +sink4_data[35] => src_payload.IN1 +sink4_data[36] => src_payload.IN1 +sink4_data[37] => src_payload.IN1 +sink4_data[38] => src_payload.IN1 +sink4_data[39] => src_payload.IN1 +sink4_data[40] => src_payload.IN1 +sink4_data[41] => src_payload.IN1 +sink4_data[42] => src_payload.IN1 +sink4_data[43] => src_payload.IN1 +sink4_data[44] => src_payload.IN1 +sink4_data[45] => src_payload.IN1 +sink4_data[46] => src_payload.IN1 +sink4_data[47] => src_payload.IN1 +sink4_data[48] => src_payload.IN1 +sink4_data[49] => src_payload.IN1 +sink4_data[50] => src_payload.IN1 +sink4_data[51] => src_payload.IN1 +sink4_data[52] => src_payload.IN1 +sink4_data[53] => src_payload.IN1 +sink4_data[54] => src_payload.IN1 +sink4_data[55] => src_payload.IN1 +sink4_data[56] => src_payload.IN1 +sink4_data[57] => src_payload.IN1 +sink4_data[58] => src_payload.IN1 +sink4_data[59] => src_payload.IN1 +sink4_data[60] => src_payload.IN1 +sink4_data[61] => src_payload.IN1 +sink4_data[62] => src_payload.IN1 +sink4_data[63] => src_payload.IN1 +sink4_data[64] => src_payload.IN1 +sink4_data[65] => src_payload.IN1 +sink4_data[66] => src_payload.IN1 +sink4_data[66] => last_cycle.IN1 +sink4_data[67] => src_payload.IN1 +sink4_data[68] => src_payload.IN1 +sink4_data[69] => src_payload.IN1 +sink4_data[70] => src_payload.IN1 +sink4_data[71] => src_payload.IN1 +sink4_data[72] => src_payload.IN1 +sink4_data[73] => src_payload.IN1 +sink4_data[74] => src_payload.IN1 +sink4_data[75] => src_payload.IN1 +sink4_data[76] => src_payload.IN1 +sink4_data[77] => src_payload.IN1 +sink4_data[78] => src_payload.IN1 +sink4_data[79] => src_payload.IN1 +sink4_data[80] => src_payload.IN1 +sink4_data[81] => src_payload.IN1 +sink4_data[82] => src_payload.IN1 +sink4_data[83] => src_payload.IN1 +sink4_data[84] => src_payload.IN1 +sink4_data[85] => src_payload.IN1 +sink4_data[86] => src_payload.IN1 +sink4_data[87] => src_payload.IN1 +sink4_data[88] => src_payload.IN1 +sink4_data[89] => src_payload.IN1 +sink4_data[90] => src_payload.IN1 +sink4_data[91] => src_payload.IN1 +sink4_data[92] => src_payload.IN1 +sink4_data[93] => src_payload.IN1 +sink4_data[94] => src_payload.IN1 +sink4_data[95] => src_payload.IN1 +sink4_data[96] => src_payload.IN1 +sink4_data[97] => src_payload.IN1 +sink4_data[98] => src_payload.IN1 +sink4_data[99] => src_payload.IN1 +sink4_data[100] => src_payload.IN1 +sink4_channel[0] => src_payload.IN1 +sink4_channel[1] => src_payload.IN1 +sink4_channel[2] => src_payload.IN1 +sink4_channel[3] => src_payload.IN1 +sink4_channel[4] => src_payload.IN1 +sink4_channel[5] => src_payload.IN1 +sink4_channel[6] => src_payload.IN1 +sink4_channel[7] => src_payload.IN1 +sink4_channel[8] => src_payload.IN1 +sink4_channel[9] => src_payload.IN1 +sink4_channel[10] => src_payload.IN1 +sink4_startofpacket => src_payload.IN1 +sink4_endofpacket => src_payload.IN1 +sink4_ready <= sink4_ready.DB_MAX_OUTPUT_PORT_TYPE +sink5_valid => request[5].IN1 +sink5_data[0] => src_payload.IN1 +sink5_data[1] => src_payload.IN1 +sink5_data[2] => src_payload.IN1 +sink5_data[3] => src_payload.IN1 +sink5_data[4] => src_payload.IN1 +sink5_data[5] => src_payload.IN1 +sink5_data[6] => src_payload.IN1 +sink5_data[7] => src_payload.IN1 +sink5_data[8] => src_payload.IN1 +sink5_data[9] => src_payload.IN1 +sink5_data[10] => src_payload.IN1 +sink5_data[11] => src_payload.IN1 +sink5_data[12] => src_payload.IN1 +sink5_data[13] => src_payload.IN1 +sink5_data[14] => src_payload.IN1 +sink5_data[15] => src_payload.IN1 +sink5_data[16] => src_payload.IN1 +sink5_data[17] => src_payload.IN1 +sink5_data[18] => src_payload.IN1 +sink5_data[19] => src_payload.IN1 +sink5_data[20] => src_payload.IN1 +sink5_data[21] => src_payload.IN1 +sink5_data[22] => src_payload.IN1 +sink5_data[23] => src_payload.IN1 +sink5_data[24] => src_payload.IN1 +sink5_data[25] => src_payload.IN1 +sink5_data[26] => src_payload.IN1 +sink5_data[27] => src_payload.IN1 +sink5_data[28] => src_payload.IN1 +sink5_data[29] => src_payload.IN1 +sink5_data[30] => src_payload.IN1 +sink5_data[31] => src_payload.IN1 +sink5_data[32] => src_payload.IN1 +sink5_data[33] => src_payload.IN1 +sink5_data[34] => src_payload.IN1 +sink5_data[35] => src_payload.IN1 +sink5_data[36] => src_payload.IN1 +sink5_data[37] => src_payload.IN1 +sink5_data[38] => src_payload.IN1 +sink5_data[39] => src_payload.IN1 +sink5_data[40] => src_payload.IN1 +sink5_data[41] => src_payload.IN1 +sink5_data[42] => src_payload.IN1 +sink5_data[43] => src_payload.IN1 +sink5_data[44] => src_payload.IN1 +sink5_data[45] => src_payload.IN1 +sink5_data[46] => src_payload.IN1 +sink5_data[47] => src_payload.IN1 +sink5_data[48] => src_payload.IN1 +sink5_data[49] => src_payload.IN1 +sink5_data[50] => src_payload.IN1 +sink5_data[51] => src_payload.IN1 +sink5_data[52] => src_payload.IN1 +sink5_data[53] => src_payload.IN1 +sink5_data[54] => src_payload.IN1 +sink5_data[55] => src_payload.IN1 +sink5_data[56] => src_payload.IN1 +sink5_data[57] => src_payload.IN1 +sink5_data[58] => src_payload.IN1 +sink5_data[59] => src_payload.IN1 +sink5_data[60] => src_payload.IN1 +sink5_data[61] => src_payload.IN1 +sink5_data[62] => src_payload.IN1 +sink5_data[63] => src_payload.IN1 +sink5_data[64] => src_payload.IN1 +sink5_data[65] => src_payload.IN1 +sink5_data[66] => src_payload.IN1 +sink5_data[66] => last_cycle.IN1 +sink5_data[67] => src_payload.IN1 +sink5_data[68] => src_payload.IN1 +sink5_data[69] => src_payload.IN1 +sink5_data[70] => src_payload.IN1 +sink5_data[71] => src_payload.IN1 +sink5_data[72] => src_payload.IN1 +sink5_data[73] => src_payload.IN1 +sink5_data[74] => src_payload.IN1 +sink5_data[75] => src_payload.IN1 +sink5_data[76] => src_payload.IN1 +sink5_data[77] => src_payload.IN1 +sink5_data[78] => src_payload.IN1 +sink5_data[79] => src_payload.IN1 +sink5_data[80] => src_payload.IN1 +sink5_data[81] => src_payload.IN1 +sink5_data[82] => src_payload.IN1 +sink5_data[83] => src_payload.IN1 +sink5_data[84] => src_payload.IN1 +sink5_data[85] => src_payload.IN1 +sink5_data[86] => src_payload.IN1 +sink5_data[87] => src_payload.IN1 +sink5_data[88] => src_payload.IN1 +sink5_data[89] => src_payload.IN1 +sink5_data[90] => src_payload.IN1 +sink5_data[91] => src_payload.IN1 +sink5_data[92] => src_payload.IN1 +sink5_data[93] => src_payload.IN1 +sink5_data[94] => src_payload.IN1 +sink5_data[95] => src_payload.IN1 +sink5_data[96] => src_payload.IN1 +sink5_data[97] => src_payload.IN1 +sink5_data[98] => src_payload.IN1 +sink5_data[99] => src_payload.IN1 +sink5_data[100] => src_payload.IN1 +sink5_channel[0] => src_payload.IN1 +sink5_channel[1] => src_payload.IN1 +sink5_channel[2] => src_payload.IN1 +sink5_channel[3] => src_payload.IN1 +sink5_channel[4] => src_payload.IN1 +sink5_channel[5] => src_payload.IN1 +sink5_channel[6] => src_payload.IN1 +sink5_channel[7] => src_payload.IN1 +sink5_channel[8] => src_payload.IN1 +sink5_channel[9] => src_payload.IN1 +sink5_channel[10] => src_payload.IN1 +sink5_startofpacket => src_payload.IN1 +sink5_endofpacket => src_payload.IN1 +sink5_ready <= sink5_ready.DB_MAX_OUTPUT_PORT_TYPE +sink6_valid => request[6].IN1 +sink6_data[0] => src_payload.IN1 +sink6_data[1] => src_payload.IN1 +sink6_data[2] => src_payload.IN1 +sink6_data[3] => src_payload.IN1 +sink6_data[4] => src_payload.IN1 +sink6_data[5] => src_payload.IN1 +sink6_data[6] => src_payload.IN1 +sink6_data[7] => src_payload.IN1 +sink6_data[8] => src_payload.IN1 +sink6_data[9] => src_payload.IN1 +sink6_data[10] => src_payload.IN1 +sink6_data[11] => src_payload.IN1 +sink6_data[12] => src_payload.IN1 +sink6_data[13] => src_payload.IN1 +sink6_data[14] => src_payload.IN1 +sink6_data[15] => src_payload.IN1 +sink6_data[16] => src_payload.IN1 +sink6_data[17] => src_payload.IN1 +sink6_data[18] => src_payload.IN1 +sink6_data[19] => src_payload.IN1 +sink6_data[20] => src_payload.IN1 +sink6_data[21] => src_payload.IN1 +sink6_data[22] => src_payload.IN1 +sink6_data[23] => src_payload.IN1 +sink6_data[24] => src_payload.IN1 +sink6_data[25] => src_payload.IN1 +sink6_data[26] => src_payload.IN1 +sink6_data[27] => src_payload.IN1 +sink6_data[28] => src_payload.IN1 +sink6_data[29] => src_payload.IN1 +sink6_data[30] => src_payload.IN1 +sink6_data[31] => src_payload.IN1 +sink6_data[32] => src_payload.IN1 +sink6_data[33] => src_payload.IN1 +sink6_data[34] => src_payload.IN1 +sink6_data[35] => src_payload.IN1 +sink6_data[36] => src_payload.IN1 +sink6_data[37] => src_payload.IN1 +sink6_data[38] => src_payload.IN1 +sink6_data[39] => src_payload.IN1 +sink6_data[40] => src_payload.IN1 +sink6_data[41] => src_payload.IN1 +sink6_data[42] => src_payload.IN1 +sink6_data[43] => src_payload.IN1 +sink6_data[44] => src_payload.IN1 +sink6_data[45] => src_payload.IN1 +sink6_data[46] => src_payload.IN1 +sink6_data[47] => src_payload.IN1 +sink6_data[48] => src_payload.IN1 +sink6_data[49] => src_payload.IN1 +sink6_data[50] => src_payload.IN1 +sink6_data[51] => src_payload.IN1 +sink6_data[52] => src_payload.IN1 +sink6_data[53] => src_payload.IN1 +sink6_data[54] => src_payload.IN1 +sink6_data[55] => src_payload.IN1 +sink6_data[56] => src_payload.IN1 +sink6_data[57] => src_payload.IN1 +sink6_data[58] => src_payload.IN1 +sink6_data[59] => src_payload.IN1 +sink6_data[60] => src_payload.IN1 +sink6_data[61] => src_payload.IN1 +sink6_data[62] => src_payload.IN1 +sink6_data[63] => src_payload.IN1 +sink6_data[64] => src_payload.IN1 +sink6_data[65] => src_payload.IN1 +sink6_data[66] => src_payload.IN1 +sink6_data[66] => last_cycle.IN1 +sink6_data[67] => src_payload.IN1 +sink6_data[68] => src_payload.IN1 +sink6_data[69] => src_payload.IN1 +sink6_data[70] => src_payload.IN1 +sink6_data[71] => src_payload.IN1 +sink6_data[72] => src_payload.IN1 +sink6_data[73] => src_payload.IN1 +sink6_data[74] => src_payload.IN1 +sink6_data[75] => src_payload.IN1 +sink6_data[76] => src_payload.IN1 +sink6_data[77] => src_payload.IN1 +sink6_data[78] => src_payload.IN1 +sink6_data[79] => src_payload.IN1 +sink6_data[80] => src_payload.IN1 +sink6_data[81] => src_payload.IN1 +sink6_data[82] => src_payload.IN1 +sink6_data[83] => src_payload.IN1 +sink6_data[84] => src_payload.IN1 +sink6_data[85] => src_payload.IN1 +sink6_data[86] => src_payload.IN1 +sink6_data[87] => src_payload.IN1 +sink6_data[88] => src_payload.IN1 +sink6_data[89] => src_payload.IN1 +sink6_data[90] => src_payload.IN1 +sink6_data[91] => src_payload.IN1 +sink6_data[92] => src_payload.IN1 +sink6_data[93] => src_payload.IN1 +sink6_data[94] => src_payload.IN1 +sink6_data[95] => src_payload.IN1 +sink6_data[96] => src_payload.IN1 +sink6_data[97] => src_payload.IN1 +sink6_data[98] => src_payload.IN1 +sink6_data[99] => src_payload.IN1 +sink6_data[100] => src_payload.IN1 +sink6_channel[0] => src_payload.IN1 +sink6_channel[1] => src_payload.IN1 +sink6_channel[2] => src_payload.IN1 +sink6_channel[3] => src_payload.IN1 +sink6_channel[4] => src_payload.IN1 +sink6_channel[5] => src_payload.IN1 +sink6_channel[6] => src_payload.IN1 +sink6_channel[7] => src_payload.IN1 +sink6_channel[8] => src_payload.IN1 +sink6_channel[9] => src_payload.IN1 +sink6_channel[10] => src_payload.IN1 +sink6_startofpacket => src_payload.IN1 +sink6_endofpacket => src_payload.IN1 +sink6_ready <= sink6_ready.DB_MAX_OUTPUT_PORT_TYPE +sink7_valid => request[7].IN1 +sink7_data[0] => src_payload.IN1 +sink7_data[1] => src_payload.IN1 +sink7_data[2] => src_payload.IN1 +sink7_data[3] => src_payload.IN1 +sink7_data[4] => src_payload.IN1 +sink7_data[5] => src_payload.IN1 +sink7_data[6] => src_payload.IN1 +sink7_data[7] => src_payload.IN1 +sink7_data[8] => src_payload.IN1 +sink7_data[9] => src_payload.IN1 +sink7_data[10] => src_payload.IN1 +sink7_data[11] => src_payload.IN1 +sink7_data[12] => src_payload.IN1 +sink7_data[13] => src_payload.IN1 +sink7_data[14] => src_payload.IN1 +sink7_data[15] => src_payload.IN1 +sink7_data[16] => src_payload.IN1 +sink7_data[17] => src_payload.IN1 +sink7_data[18] => src_payload.IN1 +sink7_data[19] => src_payload.IN1 +sink7_data[20] => src_payload.IN1 +sink7_data[21] => src_payload.IN1 +sink7_data[22] => src_payload.IN1 +sink7_data[23] => src_payload.IN1 +sink7_data[24] => src_payload.IN1 +sink7_data[25] => src_payload.IN1 +sink7_data[26] => src_payload.IN1 +sink7_data[27] => src_payload.IN1 +sink7_data[28] => src_payload.IN1 +sink7_data[29] => src_payload.IN1 +sink7_data[30] => src_payload.IN1 +sink7_data[31] => src_payload.IN1 +sink7_data[32] => src_payload.IN1 +sink7_data[33] => src_payload.IN1 +sink7_data[34] => src_payload.IN1 +sink7_data[35] => src_payload.IN1 +sink7_data[36] => src_payload.IN1 +sink7_data[37] => src_payload.IN1 +sink7_data[38] => src_payload.IN1 +sink7_data[39] => src_payload.IN1 +sink7_data[40] => src_payload.IN1 +sink7_data[41] => src_payload.IN1 +sink7_data[42] => src_payload.IN1 +sink7_data[43] => src_payload.IN1 +sink7_data[44] => src_payload.IN1 +sink7_data[45] => src_payload.IN1 +sink7_data[46] => src_payload.IN1 +sink7_data[47] => src_payload.IN1 +sink7_data[48] => src_payload.IN1 +sink7_data[49] => src_payload.IN1 +sink7_data[50] => src_payload.IN1 +sink7_data[51] => src_payload.IN1 +sink7_data[52] => src_payload.IN1 +sink7_data[53] => src_payload.IN1 +sink7_data[54] => src_payload.IN1 +sink7_data[55] => src_payload.IN1 +sink7_data[56] => src_payload.IN1 +sink7_data[57] => src_payload.IN1 +sink7_data[58] => src_payload.IN1 +sink7_data[59] => src_payload.IN1 +sink7_data[60] => src_payload.IN1 +sink7_data[61] => src_payload.IN1 +sink7_data[62] => src_payload.IN1 +sink7_data[63] => src_payload.IN1 +sink7_data[64] => src_payload.IN1 +sink7_data[65] => src_payload.IN1 +sink7_data[66] => src_payload.IN1 +sink7_data[66] => last_cycle.IN1 +sink7_data[67] => src_payload.IN1 +sink7_data[68] => src_payload.IN1 +sink7_data[69] => src_payload.IN1 +sink7_data[70] => src_payload.IN1 +sink7_data[71] => src_payload.IN1 +sink7_data[72] => src_payload.IN1 +sink7_data[73] => src_payload.IN1 +sink7_data[74] => src_payload.IN1 +sink7_data[75] => src_payload.IN1 +sink7_data[76] => src_payload.IN1 +sink7_data[77] => src_payload.IN1 +sink7_data[78] => src_payload.IN1 +sink7_data[79] => src_payload.IN1 +sink7_data[80] => src_payload.IN1 +sink7_data[81] => src_payload.IN1 +sink7_data[82] => src_payload.IN1 +sink7_data[83] => src_payload.IN1 +sink7_data[84] => src_payload.IN1 +sink7_data[85] => src_payload.IN1 +sink7_data[86] => src_payload.IN1 +sink7_data[87] => src_payload.IN1 +sink7_data[88] => src_payload.IN1 +sink7_data[89] => src_payload.IN1 +sink7_data[90] => src_payload.IN1 +sink7_data[91] => src_payload.IN1 +sink7_data[92] => src_payload.IN1 +sink7_data[93] => src_payload.IN1 +sink7_data[94] => src_payload.IN1 +sink7_data[95] => src_payload.IN1 +sink7_data[96] => src_payload.IN1 +sink7_data[97] => src_payload.IN1 +sink7_data[98] => src_payload.IN1 +sink7_data[99] => src_payload.IN1 +sink7_data[100] => src_payload.IN1 +sink7_channel[0] => src_payload.IN1 +sink7_channel[1] => src_payload.IN1 +sink7_channel[2] => src_payload.IN1 +sink7_channel[3] => src_payload.IN1 +sink7_channel[4] => src_payload.IN1 +sink7_channel[5] => src_payload.IN1 +sink7_channel[6] => src_payload.IN1 +sink7_channel[7] => src_payload.IN1 +sink7_channel[8] => src_payload.IN1 +sink7_channel[9] => src_payload.IN1 +sink7_channel[10] => src_payload.IN1 +sink7_startofpacket => src_payload.IN1 +sink7_endofpacket => src_payload.IN1 +sink7_ready <= sink7_ready.DB_MAX_OUTPUT_PORT_TYPE +sink8_valid => request[8].IN1 +sink8_data[0] => src_payload.IN1 +sink8_data[1] => src_payload.IN1 +sink8_data[2] => src_payload.IN1 +sink8_data[3] => src_payload.IN1 +sink8_data[4] => src_payload.IN1 +sink8_data[5] => src_payload.IN1 +sink8_data[6] => src_payload.IN1 +sink8_data[7] => src_payload.IN1 +sink8_data[8] => src_payload.IN1 +sink8_data[9] => src_payload.IN1 +sink8_data[10] => src_payload.IN1 +sink8_data[11] => src_payload.IN1 +sink8_data[12] => src_payload.IN1 +sink8_data[13] => src_payload.IN1 +sink8_data[14] => src_payload.IN1 +sink8_data[15] => src_payload.IN1 +sink8_data[16] => src_payload.IN1 +sink8_data[17] => src_payload.IN1 +sink8_data[18] => src_payload.IN1 +sink8_data[19] => src_payload.IN1 +sink8_data[20] => src_payload.IN1 +sink8_data[21] => src_payload.IN1 +sink8_data[22] => src_payload.IN1 +sink8_data[23] => src_payload.IN1 +sink8_data[24] => src_payload.IN1 +sink8_data[25] => src_payload.IN1 +sink8_data[26] => src_payload.IN1 +sink8_data[27] => src_payload.IN1 +sink8_data[28] => src_payload.IN1 +sink8_data[29] => src_payload.IN1 +sink8_data[30] => src_payload.IN1 +sink8_data[31] => src_payload.IN1 +sink8_data[32] => src_payload.IN1 +sink8_data[33] => src_payload.IN1 +sink8_data[34] => src_payload.IN1 +sink8_data[35] => src_payload.IN1 +sink8_data[36] => src_payload.IN1 +sink8_data[37] => src_payload.IN1 +sink8_data[38] => src_payload.IN1 +sink8_data[39] => src_payload.IN1 +sink8_data[40] => src_payload.IN1 +sink8_data[41] => src_payload.IN1 +sink8_data[42] => src_payload.IN1 +sink8_data[43] => src_payload.IN1 +sink8_data[44] => src_payload.IN1 +sink8_data[45] => src_payload.IN1 +sink8_data[46] => src_payload.IN1 +sink8_data[47] => src_payload.IN1 +sink8_data[48] => src_payload.IN1 +sink8_data[49] => src_payload.IN1 +sink8_data[50] => src_payload.IN1 +sink8_data[51] => src_payload.IN1 +sink8_data[52] => src_payload.IN1 +sink8_data[53] => src_payload.IN1 +sink8_data[54] => src_payload.IN1 +sink8_data[55] => src_payload.IN1 +sink8_data[56] => src_payload.IN1 +sink8_data[57] => src_payload.IN1 +sink8_data[58] => src_payload.IN1 +sink8_data[59] => src_payload.IN1 +sink8_data[60] => src_payload.IN1 +sink8_data[61] => src_payload.IN1 +sink8_data[62] => src_payload.IN1 +sink8_data[63] => src_payload.IN1 +sink8_data[64] => src_payload.IN1 +sink8_data[65] => src_payload.IN1 +sink8_data[66] => src_payload.IN1 +sink8_data[66] => last_cycle.IN1 +sink8_data[67] => src_payload.IN1 +sink8_data[68] => src_payload.IN1 +sink8_data[69] => src_payload.IN1 +sink8_data[70] => src_payload.IN1 +sink8_data[71] => src_payload.IN1 +sink8_data[72] => src_payload.IN1 +sink8_data[73] => src_payload.IN1 +sink8_data[74] => src_payload.IN1 +sink8_data[75] => src_payload.IN1 +sink8_data[76] => src_payload.IN1 +sink8_data[77] => src_payload.IN1 +sink8_data[78] => src_payload.IN1 +sink8_data[79] => src_payload.IN1 +sink8_data[80] => src_payload.IN1 +sink8_data[81] => src_payload.IN1 +sink8_data[82] => src_payload.IN1 +sink8_data[83] => src_payload.IN1 +sink8_data[84] => src_payload.IN1 +sink8_data[85] => src_payload.IN1 +sink8_data[86] => src_payload.IN1 +sink8_data[87] => src_payload.IN1 +sink8_data[88] => src_payload.IN1 +sink8_data[89] => src_payload.IN1 +sink8_data[90] => src_payload.IN1 +sink8_data[91] => src_payload.IN1 +sink8_data[92] => src_payload.IN1 +sink8_data[93] => src_payload.IN1 +sink8_data[94] => src_payload.IN1 +sink8_data[95] => src_payload.IN1 +sink8_data[96] => src_payload.IN1 +sink8_data[97] => src_payload.IN1 +sink8_data[98] => src_payload.IN1 +sink8_data[99] => src_payload.IN1 +sink8_data[100] => src_payload.IN1 +sink8_channel[0] => src_payload.IN1 +sink8_channel[1] => src_payload.IN1 +sink8_channel[2] => src_payload.IN1 +sink8_channel[3] => src_payload.IN1 +sink8_channel[4] => src_payload.IN1 +sink8_channel[5] => src_payload.IN1 +sink8_channel[6] => src_payload.IN1 +sink8_channel[7] => src_payload.IN1 +sink8_channel[8] => src_payload.IN1 +sink8_channel[9] => src_payload.IN1 +sink8_channel[10] => src_payload.IN1 +sink8_startofpacket => src_payload.IN1 +sink8_endofpacket => src_payload.IN1 +sink8_ready <= sink8_ready.DB_MAX_OUTPUT_PORT_TYPE +sink9_valid => request[9].IN1 +sink9_data[0] => src_payload.IN1 +sink9_data[1] => src_payload.IN1 +sink9_data[2] => src_payload.IN1 +sink9_data[3] => src_payload.IN1 +sink9_data[4] => src_payload.IN1 +sink9_data[5] => src_payload.IN1 +sink9_data[6] => src_payload.IN1 +sink9_data[7] => src_payload.IN1 +sink9_data[8] => src_payload.IN1 +sink9_data[9] => src_payload.IN1 +sink9_data[10] => src_payload.IN1 +sink9_data[11] => src_payload.IN1 +sink9_data[12] => src_payload.IN1 +sink9_data[13] => src_payload.IN1 +sink9_data[14] => src_payload.IN1 +sink9_data[15] => src_payload.IN1 +sink9_data[16] => src_payload.IN1 +sink9_data[17] => src_payload.IN1 +sink9_data[18] => src_payload.IN1 +sink9_data[19] => src_payload.IN1 +sink9_data[20] => src_payload.IN1 +sink9_data[21] => src_payload.IN1 +sink9_data[22] => src_payload.IN1 +sink9_data[23] => src_payload.IN1 +sink9_data[24] => src_payload.IN1 +sink9_data[25] => src_payload.IN1 +sink9_data[26] => src_payload.IN1 +sink9_data[27] => src_payload.IN1 +sink9_data[28] => src_payload.IN1 +sink9_data[29] => src_payload.IN1 +sink9_data[30] => src_payload.IN1 +sink9_data[31] => src_payload.IN1 +sink9_data[32] => src_payload.IN1 +sink9_data[33] => src_payload.IN1 +sink9_data[34] => src_payload.IN1 +sink9_data[35] => src_payload.IN1 +sink9_data[36] => src_payload.IN1 +sink9_data[37] => src_payload.IN1 +sink9_data[38] => src_payload.IN1 +sink9_data[39] => src_payload.IN1 +sink9_data[40] => src_payload.IN1 +sink9_data[41] => src_payload.IN1 +sink9_data[42] => src_payload.IN1 +sink9_data[43] => src_payload.IN1 +sink9_data[44] => src_payload.IN1 +sink9_data[45] => src_payload.IN1 +sink9_data[46] => src_payload.IN1 +sink9_data[47] => src_payload.IN1 +sink9_data[48] => src_payload.IN1 +sink9_data[49] => src_payload.IN1 +sink9_data[50] => src_payload.IN1 +sink9_data[51] => src_payload.IN1 +sink9_data[52] => src_payload.IN1 +sink9_data[53] => src_payload.IN1 +sink9_data[54] => src_payload.IN1 +sink9_data[55] => src_payload.IN1 +sink9_data[56] => src_payload.IN1 +sink9_data[57] => src_payload.IN1 +sink9_data[58] => src_payload.IN1 +sink9_data[59] => src_payload.IN1 +sink9_data[60] => src_payload.IN1 +sink9_data[61] => src_payload.IN1 +sink9_data[62] => src_payload.IN1 +sink9_data[63] => src_payload.IN1 +sink9_data[64] => src_payload.IN1 +sink9_data[65] => src_payload.IN1 +sink9_data[66] => src_payload.IN1 +sink9_data[66] => last_cycle.IN1 +sink9_data[67] => src_payload.IN1 +sink9_data[68] => src_payload.IN1 +sink9_data[69] => src_payload.IN1 +sink9_data[70] => src_payload.IN1 +sink9_data[71] => src_payload.IN1 +sink9_data[72] => src_payload.IN1 +sink9_data[73] => src_payload.IN1 +sink9_data[74] => src_payload.IN1 +sink9_data[75] => src_payload.IN1 +sink9_data[76] => src_payload.IN1 +sink9_data[77] => src_payload.IN1 +sink9_data[78] => src_payload.IN1 +sink9_data[79] => src_payload.IN1 +sink9_data[80] => src_payload.IN1 +sink9_data[81] => src_payload.IN1 +sink9_data[82] => src_payload.IN1 +sink9_data[83] => src_payload.IN1 +sink9_data[84] => src_payload.IN1 +sink9_data[85] => src_payload.IN1 +sink9_data[86] => src_payload.IN1 +sink9_data[87] => src_payload.IN1 +sink9_data[88] => src_payload.IN1 +sink9_data[89] => src_payload.IN1 +sink9_data[90] => src_payload.IN1 +sink9_data[91] => src_payload.IN1 +sink9_data[92] => src_payload.IN1 +sink9_data[93] => src_payload.IN1 +sink9_data[94] => src_payload.IN1 +sink9_data[95] => src_payload.IN1 +sink9_data[96] => src_payload.IN1 +sink9_data[97] => src_payload.IN1 +sink9_data[98] => src_payload.IN1 +sink9_data[99] => src_payload.IN1 +sink9_data[100] => src_payload.IN1 +sink9_channel[0] => src_payload.IN1 +sink9_channel[1] => src_payload.IN1 +sink9_channel[2] => src_payload.IN1 +sink9_channel[3] => src_payload.IN1 +sink9_channel[4] => src_payload.IN1 +sink9_channel[5] => src_payload.IN1 +sink9_channel[6] => src_payload.IN1 +sink9_channel[7] => src_payload.IN1 +sink9_channel[8] => src_payload.IN1 +sink9_channel[9] => src_payload.IN1 +sink9_channel[10] => src_payload.IN1 +sink9_startofpacket => src_payload.IN1 +sink9_endofpacket => src_payload.IN1 +sink9_ready <= sink9_ready.DB_MAX_OUTPUT_PORT_TYPE +sink10_valid => request[10].IN1 +sink10_data[0] => src_payload.IN1 +sink10_data[1] => src_payload.IN1 +sink10_data[2] => src_payload.IN1 +sink10_data[3] => src_payload.IN1 +sink10_data[4] => src_payload.IN1 +sink10_data[5] => src_payload.IN1 +sink10_data[6] => src_payload.IN1 +sink10_data[7] => src_payload.IN1 +sink10_data[8] => src_payload.IN1 +sink10_data[9] => src_payload.IN1 +sink10_data[10] => src_payload.IN1 +sink10_data[11] => src_payload.IN1 +sink10_data[12] => src_payload.IN1 +sink10_data[13] => src_payload.IN1 +sink10_data[14] => src_payload.IN1 +sink10_data[15] => src_payload.IN1 +sink10_data[16] => src_payload.IN1 +sink10_data[17] => src_payload.IN1 +sink10_data[18] => src_payload.IN1 +sink10_data[19] => src_payload.IN1 +sink10_data[20] => src_payload.IN1 +sink10_data[21] => src_payload.IN1 +sink10_data[22] => src_payload.IN1 +sink10_data[23] => src_payload.IN1 +sink10_data[24] => src_payload.IN1 +sink10_data[25] => src_payload.IN1 +sink10_data[26] => src_payload.IN1 +sink10_data[27] => src_payload.IN1 +sink10_data[28] => src_payload.IN1 +sink10_data[29] => src_payload.IN1 +sink10_data[30] => src_payload.IN1 +sink10_data[31] => src_payload.IN1 +sink10_data[32] => src_payload.IN1 +sink10_data[33] => src_payload.IN1 +sink10_data[34] => src_payload.IN1 +sink10_data[35] => src_payload.IN1 +sink10_data[36] => src_payload.IN1 +sink10_data[37] => src_payload.IN1 +sink10_data[38] => src_payload.IN1 +sink10_data[39] => src_payload.IN1 +sink10_data[40] => src_payload.IN1 +sink10_data[41] => src_payload.IN1 +sink10_data[42] => src_payload.IN1 +sink10_data[43] => src_payload.IN1 +sink10_data[44] => src_payload.IN1 +sink10_data[45] => src_payload.IN1 +sink10_data[46] => src_payload.IN1 +sink10_data[47] => src_payload.IN1 +sink10_data[48] => src_payload.IN1 +sink10_data[49] => src_payload.IN1 +sink10_data[50] => src_payload.IN1 +sink10_data[51] => src_payload.IN1 +sink10_data[52] => src_payload.IN1 +sink10_data[53] => src_payload.IN1 +sink10_data[54] => src_payload.IN1 +sink10_data[55] => src_payload.IN1 +sink10_data[56] => src_payload.IN1 +sink10_data[57] => src_payload.IN1 +sink10_data[58] => src_payload.IN1 +sink10_data[59] => src_payload.IN1 +sink10_data[60] => src_payload.IN1 +sink10_data[61] => src_payload.IN1 +sink10_data[62] => src_payload.IN1 +sink10_data[63] => src_payload.IN1 +sink10_data[64] => src_payload.IN1 +sink10_data[65] => src_payload.IN1 +sink10_data[66] => src_payload.IN1 +sink10_data[66] => last_cycle.IN1 +sink10_data[67] => src_payload.IN1 +sink10_data[68] => src_payload.IN1 +sink10_data[69] => src_payload.IN1 +sink10_data[70] => src_payload.IN1 +sink10_data[71] => src_payload.IN1 +sink10_data[72] => src_payload.IN1 +sink10_data[73] => src_payload.IN1 +sink10_data[74] => src_payload.IN1 +sink10_data[75] => src_payload.IN1 +sink10_data[76] => src_payload.IN1 +sink10_data[77] => src_payload.IN1 +sink10_data[78] => src_payload.IN1 +sink10_data[79] => src_payload.IN1 +sink10_data[80] => src_payload.IN1 +sink10_data[81] => src_payload.IN1 +sink10_data[82] => src_payload.IN1 +sink10_data[83] => src_payload.IN1 +sink10_data[84] => src_payload.IN1 +sink10_data[85] => src_payload.IN1 +sink10_data[86] => src_payload.IN1 +sink10_data[87] => src_payload.IN1 +sink10_data[88] => src_payload.IN1 +sink10_data[89] => src_payload.IN1 +sink10_data[90] => src_payload.IN1 +sink10_data[91] => src_payload.IN1 +sink10_data[92] => src_payload.IN1 +sink10_data[93] => src_payload.IN1 +sink10_data[94] => src_payload.IN1 +sink10_data[95] => src_payload.IN1 +sink10_data[96] => src_payload.IN1 +sink10_data[97] => src_payload.IN1 +sink10_data[98] => src_payload.IN1 +sink10_data[99] => src_payload.IN1 +sink10_data[100] => src_payload.IN1 +sink10_channel[0] => src_payload.IN1 +sink10_channel[1] => src_payload.IN1 +sink10_channel[2] => src_payload.IN1 +sink10_channel[3] => src_payload.IN1 +sink10_channel[4] => src_payload.IN1 +sink10_channel[5] => src_payload.IN1 +sink10_channel[6] => src_payload.IN1 +sink10_channel[7] => src_payload.IN1 +sink10_channel[8] => src_payload.IN1 +sink10_channel[9] => src_payload.IN1 +sink10_channel[10] => src_payload.IN1 +sink10_startofpacket => src_payload.IN1 +sink10_endofpacket => src_payload.IN1 +sink10_ready <= sink10_ready.DB_MAX_OUTPUT_PORT_TYPE +src_valid <= src_valid.DB_MAX_OUTPUT_PORT_TYPE +src_data[0] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[1] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[2] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[3] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[4] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[5] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[6] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[7] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[8] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[9] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[10] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[11] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[12] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[13] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[14] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[15] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[16] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[17] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[18] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[19] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[20] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[21] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[22] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[23] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[24] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[25] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[26] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[27] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[28] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[29] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[30] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[31] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[32] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[33] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[34] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[35] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[36] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[37] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[38] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[39] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[40] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[41] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[42] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[43] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[44] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[45] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[46] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[47] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[48] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[49] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[50] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[51] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[52] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[53] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[54] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[55] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[56] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[57] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[58] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[59] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[60] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[61] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[62] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[63] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[64] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[65] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[66] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[67] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[68] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[69] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[70] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[71] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[72] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[73] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[74] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[75] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[76] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[77] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[78] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[79] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[80] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[81] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[82] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[83] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[84] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[85] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[86] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[87] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[88] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[89] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[90] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[91] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[92] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[93] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[94] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[95] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[96] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[97] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[98] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[99] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_data[100] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[0] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[1] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[2] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[3] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[4] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[5] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[6] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[7] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[8] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[9] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_channel[10] <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_startofpacket <= src_payload.DB_MAX_OUTPUT_PORT_TYPE +src_endofpacket <= src_payload[0].DB_MAX_OUTPUT_PORT_TYPE +src_ready => last_cycle.IN0 +src_ready => sink0_ready.IN1 +src_ready => sink1_ready.IN1 +src_ready => sink2_ready.IN1 +src_ready => sink3_ready.IN1 +src_ready => sink4_ready.IN1 +src_ready => sink5_ready.IN1 +src_ready => sink6_ready.IN1 +src_ready => sink7_ready.IN1 +src_ready => sink8_ready.IN1 +src_ready => sink9_ready.IN1 +src_ready => sink10_ready.IN1 +clk => clk.IN1 +reset => reset.IN1 + + +|de0_nano_system|system:inst_cpu|system_rsp_xbar_mux_001:rsp_xbar_mux_001|altera_merlin_arbitrator:arb +clk => ~NO_FANOUT~ +reset => ~NO_FANOUT~ +request[0] => grant[0].DATAIN +request[0] => _.IN1 +request[0] => _.IN1 +request[1] => grant[1].DATAIN +request[1] => _.IN1 +request[1] => _.IN1 +request[2] => grant[2].DATAIN +request[2] => _.IN1 +request[2] => _.IN1 +request[3] => grant[3].DATAIN +request[3] => _.IN1 +request[3] => _.IN1 +request[4] => grant[4].DATAIN +request[4] => _.IN1 +request[4] => _.IN1 +request[5] => grant[5].DATAIN +request[5] => _.IN1 +request[5] => _.IN1 +request[6] => grant[6].DATAIN +request[6] => _.IN1 +request[6] => _.IN1 +request[7] => grant[7].DATAIN +request[7] => _.IN1 +request[7] => _.IN1 +request[8] => grant[8].DATAIN +request[8] => _.IN1 +request[8] => _.IN1 +request[9] => grant[9].DATAIN +request[9] => _.IN1 +request[9] => _.IN1 +request[10] => grant[10].DATAIN +request[10] => _.IN1 +request[10] => _.IN1 +grant[0] <= request[0].DB_MAX_OUTPUT_PORT_TYPE +grant[1] <= request[1].DB_MAX_OUTPUT_PORT_TYPE +grant[2] <= request[2].DB_MAX_OUTPUT_PORT_TYPE +grant[3] <= request[3].DB_MAX_OUTPUT_PORT_TYPE +grant[4] <= request[4].DB_MAX_OUTPUT_PORT_TYPE +grant[5] <= request[5].DB_MAX_OUTPUT_PORT_TYPE +grant[6] <= request[6].DB_MAX_OUTPUT_PORT_TYPE +grant[7] <= request[7].DB_MAX_OUTPUT_PORT_TYPE +grant[8] <= request[8].DB_MAX_OUTPUT_PORT_TYPE +grant[9] <= request[9].DB_MAX_OUTPUT_PORT_TYPE +grant[10] <= request[10].DB_MAX_OUTPUT_PORT_TYPE +increment_top_priority => ~NO_FANOUT~ +save_top_priority => ~NO_FANOUT~ + + +|de0_nano_system|system:inst_cpu|system_rsp_xbar_mux_001:rsp_xbar_mux_001|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder +a[0] => Add0.IN22 +a[1] => Add0.IN21 +a[2] => Add0.IN20 +a[3] => Add0.IN19 +a[4] => Add0.IN18 +a[5] => Add0.IN17 +a[6] => Add0.IN16 +a[7] => Add0.IN15 +a[8] => Add0.IN14 +a[9] => Add0.IN13 +a[10] => Add0.IN12 +a[11] => Add0.IN11 +a[12] => Add0.IN10 +a[13] => Add0.IN9 +a[14] => Add0.IN8 +a[15] => Add0.IN7 +a[16] => Add0.IN6 +a[17] => Add0.IN5 +a[18] => Add0.IN4 +a[19] => Add0.IN3 +a[20] => Add0.IN2 +a[21] => Add0.IN1 +b[0] => Add0.IN44 +b[1] => Add0.IN43 +b[2] => Add0.IN42 +b[3] => Add0.IN41 +b[4] => Add0.IN40 +b[5] => Add0.IN39 +b[6] => Add0.IN38 +b[7] => Add0.IN37 +b[8] => Add0.IN36 +b[9] => Add0.IN35 +b[10] => Add0.IN34 +b[11] => Add0.IN33 +b[12] => Add0.IN32 +b[13] => Add0.IN31 +b[14] => Add0.IN30 +b[15] => Add0.IN29 +b[16] => Add0.IN28 +b[17] => Add0.IN27 +b[18] => Add0.IN26 +b[19] => Add0.IN25 +b[20] => Add0.IN24 +b[21] => Add0.IN23 +sum[0] <= Add0.DB_MAX_OUTPUT_PORT_TYPE +sum[1] <= Add0.DB_MAX_OUTPUT_PORT_TYPE +sum[2] <= Add0.DB_MAX_OUTPUT_PORT_TYPE +sum[3] <= Add0.DB_MAX_OUTPUT_PORT_TYPE +sum[4] <= Add0.DB_MAX_OUTPUT_PORT_TYPE +sum[5] <= Add0.DB_MAX_OUTPUT_PORT_TYPE +sum[6] <= Add0.DB_MAX_OUTPUT_PORT_TYPE +sum[7] <= Add0.DB_MAX_OUTPUT_PORT_TYPE +sum[8] <= Add0.DB_MAX_OUTPUT_PORT_TYPE +sum[9] <= Add0.DB_MAX_OUTPUT_PORT_TYPE +sum[10] <= Add0.DB_MAX_OUTPUT_PORT_TYPE +sum[11] <= Add0.DB_MAX_OUTPUT_PORT_TYPE +sum[12] <= Add0.DB_MAX_OUTPUT_PORT_TYPE +sum[13] <= Add0.DB_MAX_OUTPUT_PORT_TYPE +sum[14] <= Add0.DB_MAX_OUTPUT_PORT_TYPE +sum[15] <= Add0.DB_MAX_OUTPUT_PORT_TYPE +sum[16] <= Add0.DB_MAX_OUTPUT_PORT_TYPE +sum[17] <= Add0.DB_MAX_OUTPUT_PORT_TYPE +sum[18] <= Add0.DB_MAX_OUTPUT_PORT_TYPE +sum[19] <= Add0.DB_MAX_OUTPUT_PORT_TYPE +sum[20] <= Add0.DB_MAX_OUTPUT_PORT_TYPE +sum[21] <= Add0.DB_MAX_OUTPUT_PORT_TYPE + + +|de0_nano_system|system:inst_cpu|altera_merlin_width_adapter:width_adapter +clk => byteen_reg[0].CLK +clk => byteen_reg[1].CLK +clk => byteen_reg[2].CLK +clk => byteen_reg[3].CLK +clk => data_reg[0].CLK +clk => data_reg[1].CLK +clk => data_reg[2].CLK +clk => data_reg[3].CLK +clk => data_reg[4].CLK +clk => data_reg[5].CLK +clk => data_reg[6].CLK +clk => data_reg[7].CLK +clk => data_reg[8].CLK +clk => data_reg[9].CLK +clk => data_reg[10].CLK +clk => data_reg[11].CLK +clk => data_reg[12].CLK +clk => data_reg[13].CLK +clk => data_reg[14].CLK +clk => data_reg[15].CLK +clk => endofpacket_reg.CLK +clk => use_reg.CLK +clk => count[0].CLK +clk => byte_cnt_reg[0].CLK +clk => byte_cnt_reg[1].CLK +clk => byte_cnt_reg[2].CLK +clk => address_reg[0].CLK +clk => address_reg[1].CLK +clk => address_reg[2].CLK +clk => address_reg[3].CLK +clk => address_reg[4].CLK +clk => address_reg[5].CLK +clk => address_reg[6].CLK +clk => address_reg[7].CLK +clk => address_reg[8].CLK +clk => address_reg[9].CLK +clk => address_reg[10].CLK +clk => address_reg[11].CLK +clk => address_reg[12].CLK +clk => address_reg[13].CLK +clk => address_reg[14].CLK +clk => address_reg[15].CLK +clk => address_reg[16].CLK +clk => address_reg[17].CLK +clk => address_reg[18].CLK +clk => address_reg[19].CLK +clk => address_reg[20].CLK +clk => address_reg[21].CLK +clk => address_reg[22].CLK +clk => address_reg[23].CLK +clk => address_reg[24].CLK +clk => address_reg[25].CLK +reset => byteen_reg[0].ACLR +reset => byteen_reg[1].ACLR +reset => byteen_reg[2].ACLR +reset => byteen_reg[3].ACLR +reset => data_reg[0].ACLR +reset => data_reg[1].ACLR +reset => data_reg[2].ACLR +reset => data_reg[3].ACLR +reset => data_reg[4].ACLR +reset => data_reg[5].ACLR +reset => data_reg[6].ACLR +reset => data_reg[7].ACLR +reset => data_reg[8].ACLR +reset => data_reg[9].ACLR +reset => data_reg[10].ACLR +reset => data_reg[11].ACLR +reset => data_reg[12].ACLR +reset => data_reg[13].ACLR +reset => data_reg[14].ACLR +reset => data_reg[15].ACLR +reset => endofpacket_reg.ACLR +reset => use_reg.ACLR +reset => count[0].ACLR +reset => byte_cnt_reg[0].ACLR +reset => byte_cnt_reg[1].ACLR +reset => byte_cnt_reg[2].ACLR +reset => address_reg[0].ACLR +reset => address_reg[1].ACLR +reset => address_reg[2].ACLR +reset => address_reg[3].ACLR +reset => address_reg[4].ACLR +reset => address_reg[5].ACLR +reset => address_reg[6].ACLR +reset => address_reg[7].ACLR +reset => address_reg[8].ACLR +reset => address_reg[9].ACLR +reset => address_reg[10].ACLR +reset => address_reg[11].ACLR +reset => address_reg[12].ACLR +reset => address_reg[13].ACLR +reset => address_reg[14].ACLR +reset => address_reg[15].ACLR +reset => address_reg[16].ACLR +reset => address_reg[17].ACLR +reset => address_reg[18].ACLR +reset => address_reg[19].ACLR +reset => address_reg[20].ACLR +reset => address_reg[21].ACLR +reset => address_reg[22].ACLR +reset => address_reg[23].ACLR +reset => address_reg[24].ACLR +reset => address_reg[25].ACLR +in_ready <= in_ready.DB_MAX_OUTPUT_PORT_TYPE +in_valid => always4.IN0 +in_valid => out_valid.DATAIN +in_channel[0] => out_channel[0].DATAIN +in_channel[1] => out_channel[1].DATAIN +in_channel[2] => out_channel[2].DATAIN +in_channel[3] => out_channel[3].DATAIN +in_channel[4] => out_channel[4].DATAIN +in_channel[5] => out_channel[5].DATAIN +in_channel[6] => out_channel[6].DATAIN +in_channel[7] => out_channel[7].DATAIN +in_channel[8] => out_channel[8].DATAIN +in_channel[9] => out_channel[9].DATAIN +in_channel[10] => out_channel[10].DATAIN +in_data[0] => out_data_field.DATAA +in_data[1] => out_data_field.DATAA +in_data[2] => out_data_field.DATAA +in_data[3] => out_data_field.DATAA +in_data[4] => out_data_field.DATAA +in_data[5] => out_data_field.DATAA +in_data[6] => out_data_field.DATAA +in_data[7] => out_data_field.DATAA +in_data[8] => out_data_field.DATAA +in_data[9] => out_data_field.DATAA +in_data[10] => out_data_field.DATAA +in_data[11] => out_data_field.DATAA +in_data[12] => out_data_field.DATAA +in_data[13] => out_data_field.DATAA +in_data[14] => out_data_field.DATAA +in_data[15] => out_data_field.DATAA +in_data[16] => data_reg.DATAB +in_data[17] => data_reg.DATAB +in_data[18] => data_reg.DATAB +in_data[19] => data_reg.DATAB +in_data[20] => data_reg.DATAB +in_data[21] => data_reg.DATAB +in_data[22] => data_reg.DATAB +in_data[23] => data_reg.DATAB +in_data[24] => data_reg.DATAB +in_data[25] => data_reg.DATAB +in_data[26] => data_reg.DATAB +in_data[27] => data_reg.DATAB +in_data[28] => data_reg.DATAB +in_data[29] => data_reg.DATAB +in_data[30] => data_reg.DATAB +in_data[31] => data_reg.DATAB +in_data[32] => out_byteen_field.DATAA +in_data[33] => out_byteen_field.DATAA +in_data[34] => byteen_reg.DATAB +in_data[35] => byteen_reg.DATAB +in_data[36] => out_address_field.DATAA +in_data[37] => out_address_field.DATAA +in_data[38] => address_reg.DATAB +in_data[38] => address_reg.DATAB +in_data[38] => out_address_field.DATAA +in_data[39] => address_reg.DATAB +in_data[39] => address_reg.DATAB +in_data[39] => out_address_field.DATAA +in_data[40] => address_reg.DATAB +in_data[40] => address_reg.DATAB +in_data[40] => out_address_field.DATAA +in_data[41] => address_reg.DATAB +in_data[41] => address_reg.DATAB +in_data[41] => out_address_field.DATAA +in_data[42] => address_reg.DATAB +in_data[42] => address_reg.DATAB +in_data[42] => out_address_field.DATAA +in_data[43] => address_reg.DATAB +in_data[43] => address_reg.DATAB +in_data[43] => out_address_field.DATAA +in_data[44] => address_reg.DATAB +in_data[44] => address_reg.DATAB +in_data[44] => out_address_field.DATAA +in_data[45] => address_reg.DATAB +in_data[45] => address_reg.DATAB +in_data[45] => out_address_field.DATAA +in_data[46] => address_reg.DATAB +in_data[46] => address_reg.DATAB +in_data[46] => out_address_field.DATAA +in_data[47] => address_reg.DATAB +in_data[47] => address_reg.DATAB +in_data[47] => out_address_field.DATAA +in_data[48] => address_reg.DATAB +in_data[48] => address_reg.DATAB +in_data[48] => out_address_field.DATAA +in_data[49] => address_reg.DATAB +in_data[49] => address_reg.DATAB +in_data[49] => out_address_field.DATAA +in_data[50] => address_reg.DATAB +in_data[50] => address_reg.DATAB +in_data[50] => out_address_field.DATAA +in_data[51] => address_reg.DATAB +in_data[51] => address_reg.DATAB +in_data[51] => out_address_field.DATAA +in_data[52] => address_reg.DATAB +in_data[52] => address_reg.DATAB +in_data[52] => out_address_field.DATAA +in_data[53] => address_reg.DATAB +in_data[53] => address_reg.DATAB +in_data[53] => out_address_field.DATAA +in_data[54] => address_reg.DATAB +in_data[54] => address_reg.DATAB +in_data[54] => out_address_field.DATAA +in_data[55] => address_reg.DATAB +in_data[55] => address_reg.DATAB +in_data[55] => out_address_field.DATAA +in_data[56] => address_reg.DATAB +in_data[56] => address_reg.DATAB +in_data[56] => out_address_field.DATAA +in_data[57] => address_reg.DATAB +in_data[57] => address_reg.DATAB +in_data[57] => out_address_field.DATAA +in_data[58] => address_reg.DATAB +in_data[58] => address_reg.DATAB +in_data[58] => out_address_field.DATAA +in_data[59] => address_reg.DATAB +in_data[59] => address_reg.DATAB +in_data[59] => out_address_field.DATAA +in_data[60] => address_reg.DATAB +in_data[60] => address_reg.DATAB +in_data[60] => out_address_field.DATAA +in_data[61] => address_reg.DATAB +in_data[61] => address_reg.DATAB +in_data[61] => out_address_field.DATAA +in_data[62] => always5.IN1 +in_data[62] => out_endofpacket.OUTPUTSELECT +in_data[62] => out_data[44].DATAIN +in_data[62] => always4.IN1 +in_data[63] => out_data[45].DATAIN +in_data[64] => out_data[46].DATAIN +in_data[65] => out_data[47].DATAIN +in_data[66] => out_data[48].DATAIN +in_data[67] => out_lock_field.DATAB +in_data[68] => Add1.IN6 +in_data[68] => out_byte_cnt_field.DATAA +in_data[69] => Add1.IN5 +in_data[69] => out_byte_cnt_field.DATAA +in_data[70] => Add1.IN4 +in_data[70] => out_byte_cnt_field.DATAA +in_data[71] => out_data[53].DATAIN +in_data[72] => out_data[54].DATAIN +in_data[73] => out_data[55].DATAIN +in_data[74] => out_size_field.DATAB +in_data[75] => out_size_field.DATAB +in_data[76] => out_size_field.DATAB +in_data[77] => out_burst_type_field.DATAA +in_data[77] => out_burst_type_field.DATAB +in_data[77] => Equal0.IN1 +in_data[78] => out_burst_type_field.DATAA +in_data[78] => out_burst_type_field.DATAB +in_data[78] => Equal0.IN0 +in_data[79] => out_data[61].DATAIN +in_data[80] => out_data[62].DATAIN +in_data[81] => out_data[63].DATAIN +in_data[82] => out_data[64].DATAIN +in_data[83] => out_data[65].DATAIN +in_data[84] => out_data[66].DATAIN +in_data[85] => out_data[67].DATAIN +in_data[86] => out_data[68].DATAIN +in_data[87] => out_data[69].DATAIN +in_data[88] => out_data[70].DATAIN +in_data[89] => out_data[71].DATAIN +in_data[90] => out_data[72].DATAIN +in_data[91] => out_data[73].DATAIN +in_data[92] => out_data[74].DATAIN +in_data[93] => out_data[75].DATAIN +in_data[94] => out_data[76].DATAIN +in_data[95] => out_data[77].DATAIN +in_data[96] => out_data[78].DATAIN +in_data[97] => out_data[79].DATAIN +in_data[98] => out_data[80].DATAIN +in_data[99] => out_data[81].DATAIN +in_data[100] => out_data[82].DATAIN +in_startofpacket => out_startofpacket.DATAA +in_endofpacket => out_endofpacket.DATAB +in_endofpacket => endofpacket_reg.DATAIN +out_ready => always4.IN1 +out_ready => address_reg.OUTPUTSELECT +out_ready => address_reg.OUTPUTSELECT +out_ready => address_reg.OUTPUTSELECT +out_ready => address_reg.OUTPUTSELECT +out_ready => address_reg.OUTPUTSELECT +out_ready => address_reg.OUTPUTSELECT +out_ready => address_reg.OUTPUTSELECT +out_ready => address_reg.OUTPUTSELECT +out_ready => address_reg.OUTPUTSELECT +out_ready => address_reg.OUTPUTSELECT +out_ready => address_reg.OUTPUTSELECT +out_ready => address_reg.OUTPUTSELECT +out_ready => address_reg.OUTPUTSELECT +out_ready => address_reg.OUTPUTSELECT +out_ready => address_reg.OUTPUTSELECT +out_ready => address_reg.OUTPUTSELECT +out_ready => address_reg.OUTPUTSELECT +out_ready => address_reg.OUTPUTSELECT +out_ready => address_reg.OUTPUTSELECT +out_ready => address_reg.OUTPUTSELECT +out_ready => address_reg.OUTPUTSELECT +out_ready => address_reg.OUTPUTSELECT +out_ready => address_reg.OUTPUTSELECT +out_ready => address_reg.OUTPUTSELECT +out_ready => address_reg.OUTPUTSELECT +out_ready => address_reg.OUTPUTSELECT +out_ready => data_reg.OUTPUTSELECT +out_ready => data_reg.OUTPUTSELECT +out_ready => data_reg.OUTPUTSELECT +out_ready => data_reg.OUTPUTSELECT +out_ready => data_reg.OUTPUTSELECT +out_ready => data_reg.OUTPUTSELECT +out_ready => data_reg.OUTPUTSELECT +out_ready => data_reg.OUTPUTSELECT +out_ready => data_reg.OUTPUTSELECT +out_ready => data_reg.OUTPUTSELECT +out_ready => data_reg.OUTPUTSELECT +out_ready => data_reg.OUTPUTSELECT +out_ready => data_reg.OUTPUTSELECT +out_ready => data_reg.OUTPUTSELECT +out_ready => data_reg.OUTPUTSELECT +out_ready => data_reg.OUTPUTSELECT +out_ready => byteen_reg.OUTPUTSELECT +out_ready => byteen_reg.OUTPUTSELECT +out_ready => byteen_reg.OUTPUTSELECT +out_ready => byteen_reg.OUTPUTSELECT +out_ready => byte_cnt_reg.OUTPUTSELECT +out_ready => byte_cnt_reg.OUTPUTSELECT +out_ready => byte_cnt_reg.OUTPUTSELECT +out_ready => count.OUTPUTSELECT +out_ready => use_reg.OUTPUTSELECT +out_ready => in_ready.DATAB +out_valid <= in_valid.DB_MAX_OUTPUT_PORT_TYPE +out_channel[0] <= in_channel[0].DB_MAX_OUTPUT_PORT_TYPE +out_channel[1] <= in_channel[1].DB_MAX_OUTPUT_PORT_TYPE +out_channel[2] <= in_channel[2].DB_MAX_OUTPUT_PORT_TYPE +out_channel[3] <= in_channel[3].DB_MAX_OUTPUT_PORT_TYPE +out_channel[4] <= in_channel[4].DB_MAX_OUTPUT_PORT_TYPE +out_channel[5] <= in_channel[5].DB_MAX_OUTPUT_PORT_TYPE +out_channel[6] <= in_channel[6].DB_MAX_OUTPUT_PORT_TYPE +out_channel[7] <= in_channel[7].DB_MAX_OUTPUT_PORT_TYPE +out_channel[8] <= in_channel[8].DB_MAX_OUTPUT_PORT_TYPE +out_channel[9] <= in_channel[9].DB_MAX_OUTPUT_PORT_TYPE +out_channel[10] <= in_channel[10].DB_MAX_OUTPUT_PORT_TYPE +out_data[0] <= out_data_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[1] <= out_data_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[2] <= out_data_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[3] <= out_data_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[4] <= out_data_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[5] <= out_data_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[6] <= out_data_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[7] <= out_data_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[8] <= out_data_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[9] <= out_data_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[10] <= out_data_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[11] <= out_data_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[12] <= out_data_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[13] <= out_data_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[14] <= out_data_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[15] <= out_data_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[16] <= out_byteen_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[17] <= out_byteen_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[18] <= out_address_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[19] <= out_address_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[20] <= out_address_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[21] <= out_address_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[22] <= out_address_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[23] <= out_address_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[24] <= out_address_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[25] <= out_address_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[26] <= out_address_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[27] <= out_address_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[28] <= out_address_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[29] <= out_address_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[30] <= out_address_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[31] <= out_address_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[32] <= out_address_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[33] <= out_address_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[34] <= out_address_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[35] <= out_address_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[36] <= out_address_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[37] <= out_address_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[38] <= out_address_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[39] <= out_address_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[40] <= out_address_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[41] <= out_address_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[42] <= out_address_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[43] <= out_address_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[44] <= in_data[62].DB_MAX_OUTPUT_PORT_TYPE +out_data[45] <= in_data[63].DB_MAX_OUTPUT_PORT_TYPE +out_data[46] <= in_data[64].DB_MAX_OUTPUT_PORT_TYPE +out_data[47] <= in_data[65].DB_MAX_OUTPUT_PORT_TYPE +out_data[48] <= in_data[66].DB_MAX_OUTPUT_PORT_TYPE +out_data[49] <= out_lock_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[50] <= out_byte_cnt_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[51] <= out_byte_cnt_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[52] <= out_byte_cnt_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[53] <= in_data[71].DB_MAX_OUTPUT_PORT_TYPE +out_data[54] <= in_data[72].DB_MAX_OUTPUT_PORT_TYPE +out_data[55] <= in_data[73].DB_MAX_OUTPUT_PORT_TYPE +out_data[56] <= out_size_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[57] <= out_size_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[58] <= out_size_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[59] <= out_burst_type_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[60] <= out_burst_type_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[61] <= in_data[79].DB_MAX_OUTPUT_PORT_TYPE +out_data[62] <= in_data[80].DB_MAX_OUTPUT_PORT_TYPE +out_data[63] <= in_data[81].DB_MAX_OUTPUT_PORT_TYPE +out_data[64] <= in_data[82].DB_MAX_OUTPUT_PORT_TYPE +out_data[65] <= in_data[83].DB_MAX_OUTPUT_PORT_TYPE +out_data[66] <= in_data[84].DB_MAX_OUTPUT_PORT_TYPE +out_data[67] <= in_data[85].DB_MAX_OUTPUT_PORT_TYPE +out_data[68] <= in_data[86].DB_MAX_OUTPUT_PORT_TYPE +out_data[69] <= in_data[87].DB_MAX_OUTPUT_PORT_TYPE +out_data[70] <= in_data[88].DB_MAX_OUTPUT_PORT_TYPE +out_data[71] <= in_data[89].DB_MAX_OUTPUT_PORT_TYPE +out_data[72] <= in_data[90].DB_MAX_OUTPUT_PORT_TYPE +out_data[73] <= in_data[91].DB_MAX_OUTPUT_PORT_TYPE +out_data[74] <= in_data[92].DB_MAX_OUTPUT_PORT_TYPE +out_data[75] <= in_data[93].DB_MAX_OUTPUT_PORT_TYPE +out_data[76] <= in_data[94].DB_MAX_OUTPUT_PORT_TYPE +out_data[77] <= in_data[95].DB_MAX_OUTPUT_PORT_TYPE +out_data[78] <= in_data[96].DB_MAX_OUTPUT_PORT_TYPE +out_data[79] <= in_data[97].DB_MAX_OUTPUT_PORT_TYPE +out_data[80] <= in_data[98].DB_MAX_OUTPUT_PORT_TYPE +out_data[81] <= in_data[99].DB_MAX_OUTPUT_PORT_TYPE +out_data[82] <= in_data[100].DB_MAX_OUTPUT_PORT_TYPE +out_startofpacket <= out_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +out_endofpacket <= out_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +in_command_size_data[0] => ~NO_FANOUT~ +in_command_size_data[1] => ~NO_FANOUT~ +in_command_size_data[2] => ~NO_FANOUT~ + + +|de0_nano_system|system:inst_cpu|altera_merlin_width_adapter:width_adapter_001 +clk => clk.IN1 +reset => reset.IN1 +in_ready <= in_ready.DB_MAX_OUTPUT_PORT_TYPE +in_valid => always5.IN1 +in_valid => p0_valid.IN1 +in_channel[0] => p0_channel.DATAA +in_channel[1] => p0_channel.DATAA +in_channel[2] => p0_channel.DATAA +in_channel[3] => p0_channel.DATAA +in_channel[4] => p0_channel.DATAA +in_channel[5] => p0_channel.DATAA +in_channel[6] => p0_channel.DATAA +in_channel[7] => p0_channel.DATAA +in_channel[8] => p0_channel.DATAA +in_channel[9] => p0_channel.DATAA +in_channel[10] => p0_channel.DATAA +in_data[0] => p0_data_field[0].DATAA +in_data[1] => p0_data_field[1].DATAA +in_data[2] => p0_data_field[2].DATAA +in_data[3] => p0_data_field[3].DATAA +in_data[4] => p0_data_field[4].DATAA +in_data[5] => p0_data_field[5].DATAA +in_data[6] => p0_data_field[6].DATAA +in_data[7] => p0_data_field[7].DATAA +in_data[8] => p0_data_field[8].DATAA +in_data[9] => p0_data_field[9].DATAA +in_data[10] => p0_data_field[10].DATAA +in_data[11] => p0_data_field[11].DATAA +in_data[12] => p0_data_field[12].DATAA +in_data[13] => p0_data_field[13].DATAA +in_data[14] => p0_data_field[14].DATAA +in_data[15] => p0_data_field[15].DATAA +in_data[16] => p0_byteen_field[0].DATAA +in_data[17] => p0_byteen_field[1].DATAA +in_data[18] => p0_address_field.DATAA +in_data[19] => p0_address_field.DATAA +in_data[20] => p0_address_field.DATAA +in_data[21] => p0_address_field.DATAA +in_data[22] => p0_address_field.DATAA +in_data[23] => p0_address_field.DATAA +in_data[24] => p0_address_field.DATAA +in_data[25] => p0_address_field.DATAA +in_data[26] => p0_address_field.DATAA +in_data[27] => p0_address_field.DATAA +in_data[28] => p0_address_field.DATAA +in_data[29] => p0_address_field.DATAA +in_data[30] => p0_address_field.DATAA +in_data[31] => p0_address_field.DATAA +in_data[32] => p0_address_field.DATAA +in_data[33] => p0_address_field.DATAA +in_data[34] => p0_address_field.DATAA +in_data[35] => p0_address_field.DATAA +in_data[36] => p0_address_field.DATAA +in_data[37] => p0_address_field.DATAA +in_data[38] => p0_address_field.DATAA +in_data[39] => p0_address_field.DATAA +in_data[40] => p0_address_field.DATAA +in_data[41] => p0_address_field.DATAA +in_data[42] => p0_address_field.DATAA +in_data[43] => p0_address_field.DATAA +in_data[44] => p0_cmpr_read.DATAA +in_data[45] => p0_last_field.DATAA +in_data[46] => p0_last_field.DATAA +in_data[47] => p0_last_field.DATAA +in_data[48] => p0_last_field.DATAA +in_data[49] => p0_out_lock_field.DATAA +in_data[50] => p0_byte_cnt_field.DATAA +in_data[51] => p0_byte_cnt_field.DATAA +in_data[52] => p0_byte_cnt_field.DATAA +in_data[53] => p0_bwrap_field.DATAA +in_data[53] => p0_last_field.DATAA +in_data[54] => p0_bwrap_field.DATAA +in_data[54] => p0_last_field.DATAA +in_data[55] => p0_bwrap_field.DATAA +in_data[55] => p0_last_field.DATAA +in_data[56] => ~NO_FANOUT~ +in_data[57] => ~NO_FANOUT~ +in_data[58] => ~NO_FANOUT~ +in_data[59] => p0_burst_type_field.DATAA +in_data[60] => p0_burst_type_field.DATAA +in_data[61] => p0_last_field.DATAA +in_data[62] => p0_last_field.DATAA +in_data[63] => p0_last_field.DATAA +in_data[64] => p0_last_field.DATAA +in_data[65] => p0_last_field.DATAA +in_data[66] => p0_last_field.DATAA +in_data[67] => p0_last_field.DATAA +in_data[68] => p0_last_field.DATAA +in_data[69] => p0_last_field.DATAA +in_data[70] => p0_last_field.DATAA +in_data[71] => p0_last_field.DATAA +in_data[72] => p0_last_field.DATAA +in_data[73] => p0_last_field.DATAA +in_data[74] => p0_last_field.DATAA +in_data[75] => p0_last_field.DATAA +in_data[76] => p0_last_field.DATAA +in_data[77] => p0_last_field.DATAA +in_data[78] => p0_last_field.DATAA +in_data[79] => p0_last_field.DATAA +in_data[80] => p0_last_field.DATAA +in_data[81] => p0_response_status_field.DATAA +in_data[82] => p0_response_status_field.DATAA +in_startofpacket => p0_startofpacket.DATAA +in_endofpacket => p0_endofpacket.DATAA +out_ready => always8.IN1 +out_ready => p1_ready.IN1 +out_valid <= out_valid.DB_MAX_OUTPUT_PORT_TYPE +out_channel[0] <= p0_channel.DB_MAX_OUTPUT_PORT_TYPE +out_channel[1] <= p0_channel.DB_MAX_OUTPUT_PORT_TYPE +out_channel[2] <= p0_channel.DB_MAX_OUTPUT_PORT_TYPE +out_channel[3] <= p0_channel.DB_MAX_OUTPUT_PORT_TYPE +out_channel[4] <= p0_channel.DB_MAX_OUTPUT_PORT_TYPE +out_channel[5] <= p0_channel.DB_MAX_OUTPUT_PORT_TYPE +out_channel[6] <= p0_channel.DB_MAX_OUTPUT_PORT_TYPE +out_channel[7] <= p0_channel.DB_MAX_OUTPUT_PORT_TYPE +out_channel[8] <= p0_channel.DB_MAX_OUTPUT_PORT_TYPE +out_channel[9] <= p0_channel.DB_MAX_OUTPUT_PORT_TYPE +out_channel[10] <= p0_channel.DB_MAX_OUTPUT_PORT_TYPE +out_data[0] <= out_data_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[1] <= out_data_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[2] <= out_data_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[3] <= out_data_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[4] <= out_data_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[5] <= out_data_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[6] <= out_data_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[7] <= out_data_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[8] <= out_data_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[9] <= out_data_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[10] <= out_data_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[11] <= out_data_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[12] <= out_data_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[13] <= out_data_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[14] <= out_data_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[15] <= out_data_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[16] <= ShiftLeft2.DB_MAX_OUTPUT_PORT_TYPE +out_data[17] <= ShiftLeft2.DB_MAX_OUTPUT_PORT_TYPE +out_data[18] <= ShiftLeft2.DB_MAX_OUTPUT_PORT_TYPE +out_data[19] <= ShiftLeft2.DB_MAX_OUTPUT_PORT_TYPE +out_data[20] <= ShiftLeft2.DB_MAX_OUTPUT_PORT_TYPE +out_data[21] <= ShiftLeft2.DB_MAX_OUTPUT_PORT_TYPE +out_data[22] <= ShiftLeft2.DB_MAX_OUTPUT_PORT_TYPE +out_data[23] <= ShiftLeft2.DB_MAX_OUTPUT_PORT_TYPE +out_data[24] <= ShiftLeft2.DB_MAX_OUTPUT_PORT_TYPE +out_data[25] <= ShiftLeft2.DB_MAX_OUTPUT_PORT_TYPE +out_data[26] <= ShiftLeft2.DB_MAX_OUTPUT_PORT_TYPE +out_data[27] <= ShiftLeft2.DB_MAX_OUTPUT_PORT_TYPE +out_data[28] <= ShiftLeft2.DB_MAX_OUTPUT_PORT_TYPE +out_data[29] <= ShiftLeft2.DB_MAX_OUTPUT_PORT_TYPE +out_data[30] <= ShiftLeft2.DB_MAX_OUTPUT_PORT_TYPE +out_data[31] <= ShiftLeft2.DB_MAX_OUTPUT_PORT_TYPE +out_data[32] <= out_byteen_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[33] <= out_byteen_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[34] <= out_byteen_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[35] <= out_byteen_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[36] <= +out_data[37] <= +out_data[38] <= p1_address_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[39] <= p1_address_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[40] <= p1_address_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[41] <= p1_address_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[42] <= p1_address_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[43] <= p1_address_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[44] <= p1_address_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[45] <= p1_address_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[46] <= p1_address_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[47] <= p1_address_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[48] <= p1_address_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[49] <= p1_address_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[50] <= p1_address_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[51] <= p1_address_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[52] <= p1_address_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[53] <= p1_address_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[54] <= p1_address_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[55] <= p1_address_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[56] <= p1_address_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[57] <= p1_address_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[58] <= p1_address_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[59] <= p1_address_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[60] <= p1_address_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[61] <= p1_address_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[62] <= p1_cmpr_read.DB_MAX_OUTPUT_PORT_TYPE +out_data[63] <= p0_last_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[64] <= p0_last_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[65] <= p0_last_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[66] <= p0_last_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[67] <= p0_out_lock_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[68] <= +out_data[69] <= +out_data[70] <= Add3.DB_MAX_OUTPUT_PORT_TYPE +out_data[71] <= p0_last_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[72] <= p0_last_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[73] <= p0_last_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[74] <= +out_data[75] <= +out_data[76] <= +out_data[77] <= p0_burst_type_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[78] <= p0_burst_type_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[79] <= p0_last_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[80] <= p0_last_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[81] <= p0_last_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[82] <= p0_last_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[83] <= p0_last_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[84] <= p0_last_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[85] <= p0_last_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[86] <= p0_last_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[87] <= p0_last_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[88] <= p0_last_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[89] <= p0_last_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[90] <= p0_last_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[91] <= p0_last_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[92] <= p0_last_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[93] <= p0_last_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[94] <= p0_last_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[95] <= p0_last_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[96] <= p0_last_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[97] <= p0_last_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[98] <= p0_last_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[99] <= p0_response_status_field.DB_MAX_OUTPUT_PORT_TYPE +out_data[100] <= p0_response_status_field.DB_MAX_OUTPUT_PORT_TYPE +out_startofpacket <= out_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +out_endofpacket <= p1_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +in_command_size_data[0] => ~NO_FANOUT~ +in_command_size_data[1] => ~NO_FANOUT~ +in_command_size_data[2] => ~NO_FANOUT~ + + +|de0_nano_system|system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|altera_merlin_burst_uncompressor:uncompressor +clk => burst_uncompress_address_offset[0].CLK +clk => burst_uncompress_address_offset[1].CLK +clk => burst_uncompress_address_offset[2].CLK +clk => burst_uncompress_address_offset[3].CLK +clk => burst_uncompress_address_offset[4].CLK +clk => burst_uncompress_address_offset[5].CLK +clk => burst_uncompress_address_offset[6].CLK +clk => burst_uncompress_address_offset[7].CLK +clk => burst_uncompress_address_offset[8].CLK +clk => burst_uncompress_address_offset[9].CLK +clk => burst_uncompress_address_offset[10].CLK +clk => burst_uncompress_address_offset[11].CLK +clk => burst_uncompress_address_offset[12].CLK +clk => burst_uncompress_address_offset[13].CLK +clk => burst_uncompress_address_offset[14].CLK +clk => burst_uncompress_address_offset[15].CLK +clk => burst_uncompress_address_offset[16].CLK +clk => burst_uncompress_address_offset[17].CLK +clk => burst_uncompress_address_offset[18].CLK +clk => burst_uncompress_address_offset[19].CLK +clk => burst_uncompress_address_offset[20].CLK +clk => burst_uncompress_address_offset[21].CLK +clk => burst_uncompress_address_offset[22].CLK +clk => burst_uncompress_address_offset[23].CLK +clk => burst_uncompress_address_offset[24].CLK +clk => burst_uncompress_address_offset[25].CLK +clk => burst_uncompress_address_base[0].CLK +clk => burst_uncompress_address_base[1].CLK +clk => burst_uncompress_address_base[2].CLK +clk => burst_uncompress_address_base[3].CLK +clk => burst_uncompress_address_base[4].CLK +clk => burst_uncompress_address_base[5].CLK +clk => burst_uncompress_address_base[6].CLK +clk => burst_uncompress_address_base[7].CLK +clk => burst_uncompress_address_base[8].CLK +clk => burst_uncompress_address_base[9].CLK +clk => burst_uncompress_address_base[10].CLK +clk => burst_uncompress_address_base[11].CLK +clk => burst_uncompress_address_base[12].CLK +clk => burst_uncompress_address_base[13].CLK +clk => burst_uncompress_address_base[14].CLK +clk => burst_uncompress_address_base[15].CLK +clk => burst_uncompress_address_base[16].CLK +clk => burst_uncompress_address_base[17].CLK +clk => burst_uncompress_address_base[18].CLK +clk => burst_uncompress_address_base[19].CLK +clk => burst_uncompress_address_base[20].CLK +clk => burst_uncompress_address_base[21].CLK +clk => burst_uncompress_address_base[22].CLK +clk => burst_uncompress_address_base[23].CLK +clk => burst_uncompress_address_base[24].CLK +clk => burst_uncompress_address_base[25].CLK +clk => burst_uncompress_byte_counter[0].CLK +clk => burst_uncompress_byte_counter[1].CLK +clk => burst_uncompress_byte_counter[2].CLK +clk => burst_uncompress_busy.CLK +reset => burst_uncompress_address_offset[0].ACLR +reset => burst_uncompress_address_offset[1].ACLR +reset => burst_uncompress_address_offset[2].ACLR +reset => burst_uncompress_address_offset[3].ACLR +reset => burst_uncompress_address_offset[4].ACLR +reset => burst_uncompress_address_offset[5].ACLR +reset => burst_uncompress_address_offset[6].ACLR +reset => burst_uncompress_address_offset[7].ACLR +reset => burst_uncompress_address_offset[8].ACLR +reset => burst_uncompress_address_offset[9].ACLR +reset => burst_uncompress_address_offset[10].ACLR +reset => burst_uncompress_address_offset[11].ACLR +reset => burst_uncompress_address_offset[12].ACLR +reset => burst_uncompress_address_offset[13].ACLR +reset => burst_uncompress_address_offset[14].ACLR +reset => burst_uncompress_address_offset[15].ACLR +reset => burst_uncompress_address_offset[16].ACLR +reset => burst_uncompress_address_offset[17].ACLR +reset => burst_uncompress_address_offset[18].ACLR +reset => burst_uncompress_address_offset[19].ACLR +reset => burst_uncompress_address_offset[20].ACLR +reset => burst_uncompress_address_offset[21].ACLR +reset => burst_uncompress_address_offset[22].ACLR +reset => burst_uncompress_address_offset[23].ACLR +reset => burst_uncompress_address_offset[24].ACLR +reset => burst_uncompress_address_offset[25].ACLR +reset => burst_uncompress_address_base[0].ACLR +reset => burst_uncompress_address_base[1].ACLR +reset => burst_uncompress_address_base[2].ACLR +reset => burst_uncompress_address_base[3].ACLR +reset => burst_uncompress_address_base[4].ACLR +reset => burst_uncompress_address_base[5].ACLR +reset => burst_uncompress_address_base[6].ACLR +reset => burst_uncompress_address_base[7].ACLR +reset => burst_uncompress_address_base[8].ACLR +reset => burst_uncompress_address_base[9].ACLR +reset => burst_uncompress_address_base[10].ACLR +reset => burst_uncompress_address_base[11].ACLR +reset => burst_uncompress_address_base[12].ACLR +reset => burst_uncompress_address_base[13].ACLR +reset => burst_uncompress_address_base[14].ACLR +reset => burst_uncompress_address_base[15].ACLR +reset => burst_uncompress_address_base[16].ACLR +reset => burst_uncompress_address_base[17].ACLR +reset => burst_uncompress_address_base[18].ACLR +reset => burst_uncompress_address_base[19].ACLR +reset => burst_uncompress_address_base[20].ACLR +reset => burst_uncompress_address_base[21].ACLR +reset => burst_uncompress_address_base[22].ACLR +reset => burst_uncompress_address_base[23].ACLR +reset => burst_uncompress_address_base[24].ACLR +reset => burst_uncompress_address_base[25].ACLR +reset => burst_uncompress_byte_counter[0].ACLR +reset => burst_uncompress_byte_counter[1].ACLR +reset => burst_uncompress_byte_counter[2].ACLR +reset => burst_uncompress_busy.ACLR +sink_startofpacket => source_startofpacket.IN1 +sink_endofpacket => source_endofpacket.IN1 +sink_valid => first_packet_beat.IN1 +sink_valid => last_packet_beat.IN1 +sink_valid => last_packet_beat.IN1 +sink_valid => always0.IN1 +sink_valid => sink_ready.IN0 +sink_valid => source_valid.DATAIN +sink_ready <= sink_ready.DB_MAX_OUTPUT_PORT_TYPE +sink_addr[0] => burst_uncompress_address_base.IN0 +sink_addr[0] => comb.DATAB +sink_addr[0] => source_addr.DATAB +sink_addr[1] => burst_uncompress_address_base.IN0 +sink_addr[1] => comb.DATAB +sink_addr[1] => source_addr.DATAB +sink_addr[2] => burst_uncompress_address_base.IN0 +sink_addr[2] => comb.DATAB +sink_addr[2] => source_addr.DATAB +sink_addr[3] => burst_uncompress_address_base.IN0 +sink_addr[3] => comb.DATAB +sink_addr[3] => source_addr.DATAB +sink_addr[4] => burst_uncompress_address_base.IN0 +sink_addr[4] => comb.DATAB +sink_addr[4] => source_addr.DATAB +sink_addr[5] => burst_uncompress_address_base.IN0 +sink_addr[5] => comb.DATAB +sink_addr[5] => source_addr.DATAB +sink_addr[6] => burst_uncompress_address_base.IN0 +sink_addr[6] => comb.DATAB +sink_addr[6] => source_addr.DATAB +sink_addr[7] => burst_uncompress_address_base.IN0 +sink_addr[7] => comb.DATAB +sink_addr[7] => source_addr.DATAB +sink_addr[8] => burst_uncompress_address_base.IN0 +sink_addr[8] => comb.DATAB +sink_addr[8] => source_addr.DATAB +sink_addr[9] => burst_uncompress_address_base.IN0 +sink_addr[9] => comb.DATAB +sink_addr[9] => source_addr.DATAB +sink_addr[10] => burst_uncompress_address_base.IN0 +sink_addr[10] => comb.DATAB +sink_addr[10] => source_addr.DATAB +sink_addr[11] => burst_uncompress_address_base.IN0 +sink_addr[11] => comb.DATAB +sink_addr[11] => source_addr.DATAB +sink_addr[12] => burst_uncompress_address_base.IN0 +sink_addr[12] => comb.DATAB +sink_addr[12] => source_addr.DATAB +sink_addr[13] => burst_uncompress_address_base.IN0 +sink_addr[13] => comb.DATAB +sink_addr[13] => source_addr.DATAB +sink_addr[14] => burst_uncompress_address_base.IN0 +sink_addr[14] => comb.DATAB +sink_addr[14] => source_addr.DATAB +sink_addr[15] => burst_uncompress_address_base.IN0 +sink_addr[15] => comb.DATAB +sink_addr[15] => source_addr.DATAB +sink_addr[16] => burst_uncompress_address_base.IN0 +sink_addr[16] => comb.DATAB +sink_addr[16] => source_addr.DATAB +sink_addr[17] => burst_uncompress_address_base.IN0 +sink_addr[17] => comb.DATAB +sink_addr[17] => source_addr.DATAB +sink_addr[18] => burst_uncompress_address_base.IN0 +sink_addr[18] => comb.DATAB +sink_addr[18] => source_addr.DATAB +sink_addr[19] => burst_uncompress_address_base.IN0 +sink_addr[19] => comb.DATAB +sink_addr[19] => source_addr.DATAB +sink_addr[20] => burst_uncompress_address_base.IN0 +sink_addr[20] => comb.DATAB +sink_addr[20] => source_addr.DATAB +sink_addr[21] => burst_uncompress_address_base.IN0 +sink_addr[21] => comb.DATAB +sink_addr[21] => source_addr.DATAB +sink_addr[22] => burst_uncompress_address_base.IN0 +sink_addr[22] => comb.DATAB +sink_addr[22] => source_addr.DATAB +sink_addr[23] => burst_uncompress_address_base.IN0 +sink_addr[23] => comb.DATAB +sink_addr[23] => source_addr.DATAB +sink_addr[24] => burst_uncompress_address_base.IN0 +sink_addr[24] => comb.DATAB +sink_addr[24] => source_addr.DATAB +sink_addr[25] => burst_uncompress_address_base.IN0 +sink_addr[25] => comb.DATAB +sink_addr[25] => source_addr.DATAB +sink_burstwrap[0] => p1_burst_uncompress_address_offset[0].IN1 +sink_burstwrap[0] => source_burstwrap[0].DATAIN +sink_burstwrap[0] => burst_uncompress_address_base.IN1 +sink_burstwrap[1] => p1_burst_uncompress_address_offset[1].IN1 +sink_burstwrap[1] => source_burstwrap[1].DATAIN +sink_burstwrap[1] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[2].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[25].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[24].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[23].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[22].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[21].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[20].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[19].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[18].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[17].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[16].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[15].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[14].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[13].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[12].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[11].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[10].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[9].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[8].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[7].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[6].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[5].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[4].IN1 +sink_burstwrap[2] => p1_burst_uncompress_address_offset[3].IN1 +sink_burstwrap[2] => source_burstwrap[2].DATAIN +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_burstwrap[2] => burst_uncompress_address_base.IN1 +sink_byte_cnt[0] => source_byte_cnt.DATAB +sink_byte_cnt[0] => Add1.IN6 +sink_byte_cnt[0] => Equal1.IN1 +sink_byte_cnt[1] => source_byte_cnt.DATAB +sink_byte_cnt[1] => Add1.IN5 +sink_byte_cnt[1] => Equal1.IN2 +sink_byte_cnt[2] => source_byte_cnt.DATAB +sink_byte_cnt[2] => Add1.IN4 +sink_byte_cnt[2] => Equal1.IN0 +sink_is_compressed => last_packet_beat.IN1 +sink_burstsize[0] => Decoder0.IN2 +sink_burstsize[0] => source_burstsize[0].DATAIN +sink_burstsize[1] => Decoder0.IN1 +sink_burstsize[1] => source_burstsize[1].DATAIN +sink_burstsize[2] => Decoder0.IN0 +sink_burstsize[2] => source_burstsize[2].DATAIN +source_startofpacket <= source_startofpacket.DB_MAX_OUTPUT_PORT_TYPE +source_endofpacket <= source_endofpacket.DB_MAX_OUTPUT_PORT_TYPE +source_valid <= sink_valid.DB_MAX_OUTPUT_PORT_TYPE +source_ready => always1.IN1 +source_ready => sink_ready.IN1 +source_addr[0] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[1] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[2] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[3] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[4] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[5] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[6] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[7] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[8] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[9] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[10] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[11] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[12] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[13] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[14] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[15] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[16] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[17] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[18] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[19] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[20] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[21] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[22] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[23] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[24] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_addr[25] <= source_addr.DB_MAX_OUTPUT_PORT_TYPE +source_burstwrap[0] <= sink_burstwrap[0].DB_MAX_OUTPUT_PORT_TYPE +source_burstwrap[1] <= sink_burstwrap[1].DB_MAX_OUTPUT_PORT_TYPE +source_burstwrap[2] <= sink_burstwrap[2].DB_MAX_OUTPUT_PORT_TYPE +source_byte_cnt[0] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE +source_byte_cnt[1] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE +source_byte_cnt[2] <= source_byte_cnt.DB_MAX_OUTPUT_PORT_TYPE +source_is_compressed <= +source_burstsize[0] <= sink_burstsize[0].DB_MAX_OUTPUT_PORT_TYPE +source_burstsize[1] <= sink_burstsize[1].DB_MAX_OUTPUT_PORT_TYPE +source_burstsize[2] <= sink_burstsize[2].DB_MAX_OUTPUT_PORT_TYPE + + +|de0_nano_system|system:inst_cpu|system_irq_mapper:irq_mapper +clk => ~NO_FANOUT~ +reset => ~NO_FANOUT~ +receiver0_irq => sender_irq[1].DATAIN +receiver1_irq => sender_irq[4].DATAIN +receiver2_irq => sender_irq[14].DATAIN +receiver3_irq => sender_irq[5].DATAIN +sender_irq[0] <= +sender_irq[1] <= receiver0_irq.DB_MAX_OUTPUT_PORT_TYPE +sender_irq[2] <= +sender_irq[3] <= +sender_irq[4] <= receiver1_irq.DB_MAX_OUTPUT_PORT_TYPE +sender_irq[5] <= receiver3_irq.DB_MAX_OUTPUT_PORT_TYPE +sender_irq[6] <= +sender_irq[7] <= +sender_irq[8] <= +sender_irq[9] <= +sender_irq[10] <= +sender_irq[11] <= +sender_irq[12] <= +sender_irq[13] <= +sender_irq[14] <= receiver2_irq.DB_MAX_OUTPUT_PORT_TYPE +sender_irq[15] <= +sender_irq[16] <= +sender_irq[17] <= +sender_irq[18] <= +sender_irq[19] <= +sender_irq[20] <= +sender_irq[21] <= +sender_irq[22] <= +sender_irq[23] <= +sender_irq[24] <= +sender_irq[25] <= +sender_irq[26] <= +sender_irq[27] <= +sender_irq[28] <= +sender_irq[29] <= +sender_irq[30] <= +sender_irq[31] <= + + diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.hif b/MCTEST/DE0-nano-HD/db/de0_nano_system.hif new file mode 100644 index 00000000..29aa3a9c Binary files /dev/null and b/MCTEST/DE0-nano-HD/db/de0_nano_system.hif differ diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.ipinfo b/MCTEST/DE0-nano-HD/db/de0_nano_system.ipinfo new file mode 100644 index 00000000..d7f76644 Binary files /dev/null and b/MCTEST/DE0-nano-HD/db/de0_nano_system.ipinfo differ diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.lpc.html b/MCTEST/DE0-nano-HD/db/de0_nano_system.lpc.html new file mode 100644 index 00000000..fc18de8a --- /dev/null +++ b/MCTEST/DE0-nano-HD/db/de0_nano_system.lpc.html @@ -0,0 +1,2722 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
HierarchyInputConstant InputUnused InputFloating InputOutputConstant OutputUnused OutputFloating OutputBidirConstant BidirUnused BidirInput only BidirOutput only Bidir
inst_cpu|irq_mapper6282283228282800000
inst_cpu|width_adapter_001|uncompressor424043344400000
inst_cpu|width_adapter_0011031031011610101000000
inst_cpu|width_adapter1213039833300000
inst_cpu|rsp_xbar_mux_001|arb|adder44220222222222200000
inst_cpu|rsp_xbar_mux_001|arb150401100000000
inst_cpu|rsp_xbar_mux_001126800012600000000
inst_cpu|rsp_xbar_mux|arb|adder8404444400000
inst_cpu|rsp_xbar_mux|arb6040200000000
inst_cpu|rsp_xbar_mux23300011700000000
inst_cpu|rsp_xbar_demux_01011812111611100000
inst_cpu|rsp_xbar_demux_00911812111611100000
inst_cpu|rsp_xbar_demux_00811812111611100000
inst_cpu|rsp_xbar_demux_00711812111611100000
inst_cpu|rsp_xbar_demux_00611812111611100000
inst_cpu|rsp_xbar_demux_00511812111611100000
inst_cpu|rsp_xbar_demux_00411812111611100000
inst_cpu|rsp_xbar_demux_00311812111611100000
inst_cpu|rsp_xbar_demux_00211812111611100000
inst_cpu|rsp_xbar_demux_00111942423144400000
inst_cpu|rsp_xbar_demux11942423144400000
inst_cpu|cmd_xbar_mux_001|arb|adder8202422200000
inst_cpu|cmd_xbar_mux_001|arb6010200000000
inst_cpu|cmd_xbar_mux_00123300011700000000
inst_cpu|cmd_xbar_mux|arb|adder8202422200000
inst_cpu|cmd_xbar_mux|arb6010200000000
inst_cpu|cmd_xbar_mux23300011700000000
inst_cpu|cmd_xbar_demux_0011381212121126612112112100000
inst_cpu|cmd_xbar_demux129411423144400000
inst_cpu|rst_controller|alt_rst_sync_uq12000100000000
inst_cpu|rst_controller1714014114141400000
inst_cpu|burst_adapter|altera_merlin_burst_adapter_uncompressed_only.the_ba1003539833300000
inst_cpu|burst_adapter1000009800000000
inst_cpu|limiter_00123400024200000000
inst_cpu|limiter23400024200000000
inst_cpu|id_router_010|the_default_decode0150151515151500000
inst_cpu|id_router_01010702011600000000
inst_cpu|id_router_009|the_default_decode0150151515151500000
inst_cpu|id_router_00910702011600000000
inst_cpu|id_router_008|the_default_decode0150151515151500000
inst_cpu|id_router_00810702011600000000
inst_cpu|id_router_007|the_default_decode0150151515151500000
inst_cpu|id_router_00710702011600000000
inst_cpu|id_router_006|the_default_decode0150151515151500000
inst_cpu|id_router_00610702011600000000
inst_cpu|id_router_005|the_default_decode0150151515151500000
inst_cpu|id_router_00510702011600000000
inst_cpu|id_router_004|the_default_decode0150151515151500000
inst_cpu|id_router_00410702011600000000
inst_cpu|id_router_003|the_default_decode0150151515151500000
inst_cpu|id_router_00310702011600000000
inst_cpu|id_router_002|the_default_decode0150151515151500000
inst_cpu|id_router_00210702011600000000
inst_cpu|id_router_001|the_default_decode0150151515151500000
inst_cpu|id_router_001890209800000000
inst_cpu|id_router|the_default_decode0150151515151500000
inst_cpu|id_router10702011600000000
inst_cpu|addr_router_001|the_default_decode0150151515151500000
inst_cpu|addr_router_00110706011600000000
inst_cpu|addr_router|the_default_decode0150151515151500000
inst_cpu|addr_router10706011600000000
inst_cpu|rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo1473903910639393900000
inst_cpu|rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent|uncompressor421014011100000
inst_cpu|rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent29238483831438383800000
inst_cpu|pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rsp_fifo1473903910639393900000
inst_cpu|pio_motor_rst_s1_translator_avalon_universal_slave_0_agent|uncompressor421014011100000
inst_cpu|pio_motor_rst_s1_translator_avalon_universal_slave_0_agent29238483831438383800000
inst_cpu|jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo1473903910639393900000
inst_cpu|jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent|uncompressor421014011100000
inst_cpu|jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent29238483831438383800000
inst_cpu|pio_sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo1473903910639393900000
inst_cpu|pio_sw_s1_translator_avalon_universal_slave_0_agent|uncompressor421014011100000
inst_cpu|pio_sw_s1_translator_avalon_universal_slave_0_agent29238483831438383800000
inst_cpu|pio_key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo1473903910639393900000
inst_cpu|pio_key_s1_translator_avalon_universal_slave_0_agent|uncompressor421014011100000
inst_cpu|pio_key_s1_translator_avalon_universal_slave_0_agent29238483831438383800000
inst_cpu|pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo1473903910639393900000
inst_cpu|pio_led_s1_translator_avalon_universal_slave_0_agent|uncompressor421014011100000
inst_cpu|pio_led_s1_translator_avalon_universal_slave_0_agent29238483831438383800000
inst_cpu|uart_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo1473903910639393900000
inst_cpu|uart_0_s1_translator_avalon_universal_slave_0_agent|uncompressor421014011100000
inst_cpu|uart_0_s1_translator_avalon_universal_slave_0_agent29238483831438383800000
inst_cpu|sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo1473903910639393900000
inst_cpu|sys_clk_timer_s1_translator_avalon_universal_slave_0_agent|uncompressor421014011100000
inst_cpu|sys_clk_timer_s1_translator_avalon_universal_slave_0_agent29238483831438383800000
inst_cpu|sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo1473903910639393900000
inst_cpu|sysid_control_slave_translator_avalon_universal_slave_0_agent|uncompressor421014011100000
inst_cpu|sysid_control_slave_translator_avalon_universal_slave_0_agent29238483831438383800000
inst_cpu|sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo129390398839393900000
inst_cpu|sdram_s1_translator_avalon_universal_slave_0_agent|uncompressor421014011100000
inst_cpu|sdram_s1_translator_avalon_universal_slave_0_agent22421322124321212100000
inst_cpu|cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo1473903910639393900000
inst_cpu|cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent|uncompressor421014011100000
inst_cpu|cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent29238483831438383800000
inst_cpu|cpu_data_master_translator_avalon_universal_master_0_agent18736863613936363600000
inst_cpu|cpu_instruction_master_translator_avalon_universal_master_0_agent18736863613936363600000
inst_cpu|rs232_motor_avalon_rs232_slave_translator10632537433300000
inst_cpu|pio_motor_rst_s1_translator10632737033300000
inst_cpu|jtag_uart_0_avalon_jtag_slave_translator10622827022200000
inst_cpu|pio_sw_s1_translator10632733633300000
inst_cpu|pio_key_s1_translator10632733633300000
inst_cpu|pio_led_s1_translator10632637133300000
inst_cpu|uart_0_s1_translator901942195719191900000
inst_cpu|sys_clk_timer_s1_translator901942195519191900000
inst_cpu|sysid_control_slave_translator10632533533300000
inst_cpu|sdram_s1_translator711316211100000
inst_cpu|cpu_jtag_debug_module_translator10631738333300000
inst_cpu|cpu_data_master_translator10792910399900000
inst_cpu|cpu_instruction_master_translator1074824810348484800000
inst_cpu|rs232_motor|RS232_Out_Serializer|RS232_Out_FIFO|Sync_FIFO|auto_generated|dpfifo|wr_ptr3000700000000
inst_cpu|rs232_motor|RS232_Out_Serializer|RS232_Out_FIFO|Sync_FIFO|auto_generated|dpfifo|usedw_counter4000700000000
inst_cpu|rs232_motor|RS232_Out_Serializer|RS232_Out_FIFO|Sync_FIFO|auto_generated|dpfifo|rd_ptr_msb3000600000000
inst_cpu|rs232_motor|RS232_Out_Serializer|RS232_Out_FIFO|Sync_FIFO|auto_generated|dpfifo|three_comparison14707177700000
inst_cpu|rs232_motor|RS232_Out_Serializer|RS232_Out_FIFO|Sync_FIFO|auto_generated|dpfifo|almost_full_comparer14707177700000
inst_cpu|rs232_motor|RS232_Out_Serializer|RS232_Out_FIFO|Sync_FIFO|auto_generated|dpfifo|FIFOram24000800000000
inst_cpu|rs232_motor|RS232_Out_Serializer|RS232_Out_FIFO|Sync_FIFO|auto_generated|dpfifo120001700000000
inst_cpu|rs232_motor|RS232_Out_Serializer|RS232_Out_FIFO|Sync_FIFO|auto_generated120001700000000
inst_cpu|rs232_motor|RS232_Out_Serializer|RS232_Out_FIFO120001700000000
inst_cpu|rs232_motor|RS232_Out_Serializer|RS232_Out_Counters3000200000000
inst_cpu|rs232_motor|RS232_Out_Serializer11000900000000
inst_cpu|rs232_motor|RS232_In_Deserializer|RS232_In_FIFO|Sync_FIFO|auto_generated|dpfifo|wr_ptr3000700000000
inst_cpu|rs232_motor|RS232_In_Deserializer|RS232_In_FIFO|Sync_FIFO|auto_generated|dpfifo|usedw_counter4000700000000
inst_cpu|rs232_motor|RS232_In_Deserializer|RS232_In_FIFO|Sync_FIFO|auto_generated|dpfifo|rd_ptr_msb3000600000000
inst_cpu|rs232_motor|RS232_In_Deserializer|RS232_In_FIFO|Sync_FIFO|auto_generated|dpfifo|three_comparison14707177700000
inst_cpu|rs232_motor|RS232_In_Deserializer|RS232_In_FIFO|Sync_FIFO|auto_generated|dpfifo|almost_full_comparer14707177700000
inst_cpu|rs232_motor|RS232_In_Deserializer|RS232_In_FIFO|Sync_FIFO|auto_generated|dpfifo|FIFOram24000800000000
inst_cpu|rs232_motor|RS232_In_Deserializer|RS232_In_FIFO|Sync_FIFO|auto_generated|dpfifo120001700000000
inst_cpu|rs232_motor|RS232_In_Deserializer|RS232_In_FIFO|Sync_FIFO|auto_generated120001700000000
inst_cpu|rs232_motor|RS232_In_Deserializer|RS232_In_FIFO120001700000000
inst_cpu|rs232_motor|RS232_In_Deserializer|RS232_In_Counters3000200000000
inst_cpu|rs232_motor|RS232_In_Deserializer40001700000000
inst_cpu|rs232_motor4302703400000000
inst_cpu|pio_motor_rst383131313331313100000
inst_cpu|jtag_uart_0|the_system_jtag_uart_0_scfifo_r|rfifo|auto_generated|dpfifo|wr_ptr4000600000000
inst_cpu|jtag_uart_0|the_system_jtag_uart_0_scfifo_r|rfifo|auto_generated|dpfifo|rd_ptr_count4000600000000
inst_cpu|jtag_uart_0|the_system_jtag_uart_0_scfifo_r|rfifo|auto_generated|dpfifo|FIFOram|altsyncram124000800000000
inst_cpu|jtag_uart_0|the_system_jtag_uart_0_scfifo_r|rfifo|auto_generated|dpfifo|FIFOram24000800000000
inst_cpu|jtag_uart_0|the_system_jtag_uart_0_scfifo_r|rfifo|auto_generated|dpfifo|fifo_state|count_usedw5000600000000
inst_cpu|jtag_uart_0|the_system_jtag_uart_0_scfifo_r|rfifo|auto_generated|dpfifo|fifo_state5000800000000
inst_cpu|jtag_uart_0|the_system_jtag_uart_0_scfifo_r|rfifo|auto_generated|dpfifo130001600000000
inst_cpu|jtag_uart_0|the_system_jtag_uart_0_scfifo_r|rfifo|auto_generated120001600000000
inst_cpu|jtag_uart_0|the_system_jtag_uart_0_scfifo_r130101600000000
inst_cpu|jtag_uart_0|the_system_jtag_uart_0_scfifo_w|wfifo|auto_generated|dpfifo|wr_ptr4000600000000
inst_cpu|jtag_uart_0|the_system_jtag_uart_0_scfifo_w|wfifo|auto_generated|dpfifo|rd_ptr_count4000600000000
inst_cpu|jtag_uart_0|the_system_jtag_uart_0_scfifo_w|wfifo|auto_generated|dpfifo|FIFOram|altsyncram124000800000000
inst_cpu|jtag_uart_0|the_system_jtag_uart_0_scfifo_w|wfifo|auto_generated|dpfifo|FIFOram24000800000000
inst_cpu|jtag_uart_0|the_system_jtag_uart_0_scfifo_w|wfifo|auto_generated|dpfifo|fifo_state|count_usedw5000600000000
inst_cpu|jtag_uart_0|the_system_jtag_uart_0_scfifo_w|wfifo|auto_generated|dpfifo|fifo_state5000800000000
inst_cpu|jtag_uart_0|the_system_jtag_uart_0_scfifo_w|wfifo|auto_generated|dpfifo130001600000000
inst_cpu|jtag_uart_0|the_system_jtag_uart_0_scfifo_w|wfifo|auto_generated120001600000000
inst_cpu|jtag_uart_0|the_system_jtag_uart_0_scfifo_w120001600000000
inst_cpu|jtag_uart_0381023103410101000000
inst_cpu|pio_sw80003200000000
inst_cpu|pio_key60003200000000
inst_cpu|pio_led392525253925252500000
inst_cpu|uart_0|the_system_uart_0_regs410004700000000
inst_cpu|uart_0|the_system_uart_0_rx|the_system_uart_0_rx_stimulus_source210200100000000
inst_cpu|uart_0|the_system_uart_0_rx231011311100000
inst_cpu|uart_0|the_system_uart_0_tx31000400000000
inst_cpu|uart_0260001800000000
inst_cpu|sys_clk_timer230001700000000
inst_cpu|sdram|the_system_sdram_input_efifo_module460004600000000
inst_cpu|sdram4611140111160000
inst_cpu|sysid3182183218181800000
inst_cpu|cpu151028012500000000
inst_cpu1000032000160000
inst_heartbeat1000100000000
inst_pll_sys|altpll_component|auto_generated2000600000000
inst_pll_sys1000400000000
diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.lpc.rdb b/MCTEST/DE0-nano-HD/db/de0_nano_system.lpc.rdb new file mode 100644 index 00000000..c7678f11 Binary files /dev/null and b/MCTEST/DE0-nano-HD/db/de0_nano_system.lpc.rdb differ diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.lpc.txt b/MCTEST/DE0-nano-HD/db/de0_nano_system.lpc.txt new file mode 100644 index 00000000..89e3ac94 --- /dev/null +++ b/MCTEST/DE0-nano-HD/db/de0_nano_system.lpc.txt @@ -0,0 +1,175 @@ ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Legal Partition Candidates ; ++---------------------------------------------------------------------------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ +; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ; ++---------------------------------------------------------------------------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ +; inst_cpu|irq_mapper ; 6 ; 28 ; 2 ; 28 ; 32 ; 28 ; 28 ; 28 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|width_adapter_001|uncompressor ; 42 ; 4 ; 0 ; 4 ; 33 ; 4 ; 4 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|width_adapter_001 ; 103 ; 10 ; 3 ; 10 ; 116 ; 10 ; 10 ; 10 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|width_adapter ; 121 ; 3 ; 0 ; 3 ; 98 ; 3 ; 3 ; 3 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|rsp_xbar_mux_001|arb|adder ; 44 ; 22 ; 0 ; 22 ; 22 ; 22 ; 22 ; 22 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|rsp_xbar_mux_001|arb ; 15 ; 0 ; 4 ; 0 ; 11 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|rsp_xbar_mux_001 ; 1268 ; 0 ; 0 ; 0 ; 126 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|rsp_xbar_mux|arb|adder ; 8 ; 4 ; 0 ; 4 ; 4 ; 4 ; 4 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|rsp_xbar_mux|arb ; 6 ; 0 ; 4 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|rsp_xbar_mux ; 233 ; 0 ; 0 ; 0 ; 117 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|rsp_xbar_demux_010 ; 118 ; 1 ; 2 ; 1 ; 116 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|rsp_xbar_demux_009 ; 118 ; 1 ; 2 ; 1 ; 116 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|rsp_xbar_demux_008 ; 118 ; 1 ; 2 ; 1 ; 116 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|rsp_xbar_demux_007 ; 118 ; 1 ; 2 ; 1 ; 116 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|rsp_xbar_demux_006 ; 118 ; 1 ; 2 ; 1 ; 116 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|rsp_xbar_demux_005 ; 118 ; 1 ; 2 ; 1 ; 116 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|rsp_xbar_demux_004 ; 118 ; 1 ; 2 ; 1 ; 116 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|rsp_xbar_demux_003 ; 118 ; 1 ; 2 ; 1 ; 116 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|rsp_xbar_demux_002 ; 118 ; 1 ; 2 ; 1 ; 116 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|rsp_xbar_demux_001 ; 119 ; 4 ; 2 ; 4 ; 231 ; 4 ; 4 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|rsp_xbar_demux ; 119 ; 4 ; 2 ; 4 ; 231 ; 4 ; 4 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|cmd_xbar_mux_001|arb|adder ; 8 ; 2 ; 0 ; 2 ; 4 ; 2 ; 2 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|cmd_xbar_mux_001|arb ; 6 ; 0 ; 1 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|cmd_xbar_mux_001 ; 233 ; 0 ; 0 ; 0 ; 117 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|cmd_xbar_mux|arb|adder ; 8 ; 2 ; 0 ; 2 ; 4 ; 2 ; 2 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|cmd_xbar_mux|arb ; 6 ; 0 ; 1 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|cmd_xbar_mux ; 233 ; 0 ; 0 ; 0 ; 117 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|cmd_xbar_demux_001 ; 138 ; 121 ; 2 ; 121 ; 1266 ; 121 ; 121 ; 121 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|cmd_xbar_demux ; 129 ; 4 ; 11 ; 4 ; 231 ; 4 ; 4 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|rst_controller|alt_rst_sync_uq1 ; 2 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|rst_controller ; 17 ; 14 ; 0 ; 14 ; 1 ; 14 ; 14 ; 14 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|burst_adapter|altera_merlin_burst_adapter_uncompressed_only.the_ba ; 100 ; 3 ; 5 ; 3 ; 98 ; 3 ; 3 ; 3 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|burst_adapter ; 100 ; 0 ; 0 ; 0 ; 98 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|limiter_001 ; 234 ; 0 ; 0 ; 0 ; 242 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|limiter ; 234 ; 0 ; 0 ; 0 ; 242 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|id_router_010|the_default_decode ; 0 ; 15 ; 0 ; 15 ; 15 ; 15 ; 15 ; 15 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|id_router_010 ; 107 ; 0 ; 2 ; 0 ; 116 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|id_router_009|the_default_decode ; 0 ; 15 ; 0 ; 15 ; 15 ; 15 ; 15 ; 15 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|id_router_009 ; 107 ; 0 ; 2 ; 0 ; 116 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|id_router_008|the_default_decode ; 0 ; 15 ; 0 ; 15 ; 15 ; 15 ; 15 ; 15 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|id_router_008 ; 107 ; 0 ; 2 ; 0 ; 116 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|id_router_007|the_default_decode ; 0 ; 15 ; 0 ; 15 ; 15 ; 15 ; 15 ; 15 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|id_router_007 ; 107 ; 0 ; 2 ; 0 ; 116 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|id_router_006|the_default_decode ; 0 ; 15 ; 0 ; 15 ; 15 ; 15 ; 15 ; 15 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|id_router_006 ; 107 ; 0 ; 2 ; 0 ; 116 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|id_router_005|the_default_decode ; 0 ; 15 ; 0 ; 15 ; 15 ; 15 ; 15 ; 15 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|id_router_005 ; 107 ; 0 ; 2 ; 0 ; 116 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|id_router_004|the_default_decode ; 0 ; 15 ; 0 ; 15 ; 15 ; 15 ; 15 ; 15 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|id_router_004 ; 107 ; 0 ; 2 ; 0 ; 116 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|id_router_003|the_default_decode ; 0 ; 15 ; 0 ; 15 ; 15 ; 15 ; 15 ; 15 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|id_router_003 ; 107 ; 0 ; 2 ; 0 ; 116 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|id_router_002|the_default_decode ; 0 ; 15 ; 0 ; 15 ; 15 ; 15 ; 15 ; 15 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|id_router_002 ; 107 ; 0 ; 2 ; 0 ; 116 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|id_router_001|the_default_decode ; 0 ; 15 ; 0 ; 15 ; 15 ; 15 ; 15 ; 15 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|id_router_001 ; 89 ; 0 ; 2 ; 0 ; 98 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|id_router|the_default_decode ; 0 ; 15 ; 0 ; 15 ; 15 ; 15 ; 15 ; 15 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|id_router ; 107 ; 0 ; 2 ; 0 ; 116 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|addr_router_001|the_default_decode ; 0 ; 15 ; 0 ; 15 ; 15 ; 15 ; 15 ; 15 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|addr_router_001 ; 107 ; 0 ; 6 ; 0 ; 116 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|addr_router|the_default_decode ; 0 ; 15 ; 0 ; 15 ; 15 ; 15 ; 15 ; 15 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|addr_router ; 107 ; 0 ; 6 ; 0 ; 116 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo ; 147 ; 39 ; 0 ; 39 ; 106 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent|uncompressor ; 42 ; 1 ; 0 ; 1 ; 40 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent ; 292 ; 38 ; 48 ; 38 ; 314 ; 38 ; 38 ; 38 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; 147 ; 39 ; 0 ; 39 ; 106 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|pio_motor_rst_s1_translator_avalon_universal_slave_0_agent|uncompressor ; 42 ; 1 ; 0 ; 1 ; 40 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|pio_motor_rst_s1_translator_avalon_universal_slave_0_agent ; 292 ; 38 ; 48 ; 38 ; 314 ; 38 ; 38 ; 38 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo ; 147 ; 39 ; 0 ; 39 ; 106 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent|uncompressor ; 42 ; 1 ; 0 ; 1 ; 40 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent ; 292 ; 38 ; 48 ; 38 ; 314 ; 38 ; 38 ; 38 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|pio_sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; 147 ; 39 ; 0 ; 39 ; 106 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|pio_sw_s1_translator_avalon_universal_slave_0_agent|uncompressor ; 42 ; 1 ; 0 ; 1 ; 40 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|pio_sw_s1_translator_avalon_universal_slave_0_agent ; 292 ; 38 ; 48 ; 38 ; 314 ; 38 ; 38 ; 38 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|pio_key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; 147 ; 39 ; 0 ; 39 ; 106 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|pio_key_s1_translator_avalon_universal_slave_0_agent|uncompressor ; 42 ; 1 ; 0 ; 1 ; 40 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|pio_key_s1_translator_avalon_universal_slave_0_agent ; 292 ; 38 ; 48 ; 38 ; 314 ; 38 ; 38 ; 38 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; 147 ; 39 ; 0 ; 39 ; 106 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|pio_led_s1_translator_avalon_universal_slave_0_agent|uncompressor ; 42 ; 1 ; 0 ; 1 ; 40 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|pio_led_s1_translator_avalon_universal_slave_0_agent ; 292 ; 38 ; 48 ; 38 ; 314 ; 38 ; 38 ; 38 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|uart_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; 147 ; 39 ; 0 ; 39 ; 106 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|uart_0_s1_translator_avalon_universal_slave_0_agent|uncompressor ; 42 ; 1 ; 0 ; 1 ; 40 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|uart_0_s1_translator_avalon_universal_slave_0_agent ; 292 ; 38 ; 48 ; 38 ; 314 ; 38 ; 38 ; 38 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; 147 ; 39 ; 0 ; 39 ; 106 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|sys_clk_timer_s1_translator_avalon_universal_slave_0_agent|uncompressor ; 42 ; 1 ; 0 ; 1 ; 40 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|sys_clk_timer_s1_translator_avalon_universal_slave_0_agent ; 292 ; 38 ; 48 ; 38 ; 314 ; 38 ; 38 ; 38 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo ; 147 ; 39 ; 0 ; 39 ; 106 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|sysid_control_slave_translator_avalon_universal_slave_0_agent|uncompressor ; 42 ; 1 ; 0 ; 1 ; 40 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|sysid_control_slave_translator_avalon_universal_slave_0_agent ; 292 ; 38 ; 48 ; 38 ; 314 ; 38 ; 38 ; 38 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; 129 ; 39 ; 0 ; 39 ; 88 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|sdram_s1_translator_avalon_universal_slave_0_agent|uncompressor ; 42 ; 1 ; 0 ; 1 ; 40 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|sdram_s1_translator_avalon_universal_slave_0_agent ; 224 ; 21 ; 32 ; 21 ; 243 ; 21 ; 21 ; 21 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo ; 147 ; 39 ; 0 ; 39 ; 106 ; 39 ; 39 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent|uncompressor ; 42 ; 1 ; 0 ; 1 ; 40 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent ; 292 ; 38 ; 48 ; 38 ; 314 ; 38 ; 38 ; 38 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|cpu_data_master_translator_avalon_universal_master_0_agent ; 187 ; 36 ; 86 ; 36 ; 139 ; 36 ; 36 ; 36 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|cpu_instruction_master_translator_avalon_universal_master_0_agent ; 187 ; 36 ; 86 ; 36 ; 139 ; 36 ; 36 ; 36 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|rs232_motor_avalon_rs232_slave_translator ; 106 ; 3 ; 25 ; 3 ; 74 ; 3 ; 3 ; 3 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|pio_motor_rst_s1_translator ; 106 ; 3 ; 27 ; 3 ; 70 ; 3 ; 3 ; 3 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|jtag_uart_0_avalon_jtag_slave_translator ; 106 ; 2 ; 28 ; 2 ; 70 ; 2 ; 2 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|pio_sw_s1_translator ; 106 ; 3 ; 27 ; 3 ; 36 ; 3 ; 3 ; 3 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|pio_key_s1_translator ; 106 ; 3 ; 27 ; 3 ; 36 ; 3 ; 3 ; 3 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|pio_led_s1_translator ; 106 ; 3 ; 26 ; 3 ; 71 ; 3 ; 3 ; 3 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|uart_0_s1_translator ; 90 ; 19 ; 42 ; 19 ; 57 ; 19 ; 19 ; 19 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|sys_clk_timer_s1_translator ; 90 ; 19 ; 42 ; 19 ; 55 ; 19 ; 19 ; 19 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|sysid_control_slave_translator ; 106 ; 3 ; 25 ; 3 ; 35 ; 3 ; 3 ; 3 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|sdram_s1_translator ; 71 ; 1 ; 3 ; 1 ; 62 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|cpu_jtag_debug_module_translator ; 106 ; 3 ; 17 ; 3 ; 83 ; 3 ; 3 ; 3 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|cpu_data_master_translator ; 107 ; 9 ; 2 ; 9 ; 103 ; 9 ; 9 ; 9 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|cpu_instruction_master_translator ; 107 ; 48 ; 2 ; 48 ; 103 ; 48 ; 48 ; 48 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|rs232_motor|RS232_Out_Serializer|RS232_Out_FIFO|Sync_FIFO|auto_generated|dpfifo|wr_ptr ; 3 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|rs232_motor|RS232_Out_Serializer|RS232_Out_FIFO|Sync_FIFO|auto_generated|dpfifo|usedw_counter ; 4 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|rs232_motor|RS232_Out_Serializer|RS232_Out_FIFO|Sync_FIFO|auto_generated|dpfifo|rd_ptr_msb ; 3 ; 0 ; 0 ; 0 ; 6 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|rs232_motor|RS232_Out_Serializer|RS232_Out_FIFO|Sync_FIFO|auto_generated|dpfifo|three_comparison ; 14 ; 7 ; 0 ; 7 ; 1 ; 7 ; 7 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|rs232_motor|RS232_Out_Serializer|RS232_Out_FIFO|Sync_FIFO|auto_generated|dpfifo|almost_full_comparer ; 14 ; 7 ; 0 ; 7 ; 1 ; 7 ; 7 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|rs232_motor|RS232_Out_Serializer|RS232_Out_FIFO|Sync_FIFO|auto_generated|dpfifo|FIFOram ; 24 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|rs232_motor|RS232_Out_Serializer|RS232_Out_FIFO|Sync_FIFO|auto_generated|dpfifo ; 12 ; 0 ; 0 ; 0 ; 17 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|rs232_motor|RS232_Out_Serializer|RS232_Out_FIFO|Sync_FIFO|auto_generated ; 12 ; 0 ; 0 ; 0 ; 17 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|rs232_motor|RS232_Out_Serializer|RS232_Out_FIFO ; 12 ; 0 ; 0 ; 0 ; 17 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|rs232_motor|RS232_Out_Serializer|RS232_Out_Counters ; 3 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|rs232_motor|RS232_Out_Serializer ; 11 ; 0 ; 0 ; 0 ; 9 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|rs232_motor|RS232_In_Deserializer|RS232_In_FIFO|Sync_FIFO|auto_generated|dpfifo|wr_ptr ; 3 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|rs232_motor|RS232_In_Deserializer|RS232_In_FIFO|Sync_FIFO|auto_generated|dpfifo|usedw_counter ; 4 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|rs232_motor|RS232_In_Deserializer|RS232_In_FIFO|Sync_FIFO|auto_generated|dpfifo|rd_ptr_msb ; 3 ; 0 ; 0 ; 0 ; 6 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|rs232_motor|RS232_In_Deserializer|RS232_In_FIFO|Sync_FIFO|auto_generated|dpfifo|three_comparison ; 14 ; 7 ; 0 ; 7 ; 1 ; 7 ; 7 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|rs232_motor|RS232_In_Deserializer|RS232_In_FIFO|Sync_FIFO|auto_generated|dpfifo|almost_full_comparer ; 14 ; 7 ; 0 ; 7 ; 1 ; 7 ; 7 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|rs232_motor|RS232_In_Deserializer|RS232_In_FIFO|Sync_FIFO|auto_generated|dpfifo|FIFOram ; 24 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|rs232_motor|RS232_In_Deserializer|RS232_In_FIFO|Sync_FIFO|auto_generated|dpfifo ; 12 ; 0 ; 0 ; 0 ; 17 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|rs232_motor|RS232_In_Deserializer|RS232_In_FIFO|Sync_FIFO|auto_generated ; 12 ; 0 ; 0 ; 0 ; 17 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|rs232_motor|RS232_In_Deserializer|RS232_In_FIFO ; 12 ; 0 ; 0 ; 0 ; 17 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|rs232_motor|RS232_In_Deserializer|RS232_In_Counters ; 3 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|rs232_motor|RS232_In_Deserializer ; 4 ; 0 ; 0 ; 0 ; 17 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|rs232_motor ; 43 ; 0 ; 27 ; 0 ; 34 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|pio_motor_rst ; 38 ; 31 ; 31 ; 31 ; 33 ; 31 ; 31 ; 31 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|jtag_uart_0|the_system_jtag_uart_0_scfifo_r|rfifo|auto_generated|dpfifo|wr_ptr ; 4 ; 0 ; 0 ; 0 ; 6 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|jtag_uart_0|the_system_jtag_uart_0_scfifo_r|rfifo|auto_generated|dpfifo|rd_ptr_count ; 4 ; 0 ; 0 ; 0 ; 6 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|jtag_uart_0|the_system_jtag_uart_0_scfifo_r|rfifo|auto_generated|dpfifo|FIFOram|altsyncram1 ; 24 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|jtag_uart_0|the_system_jtag_uart_0_scfifo_r|rfifo|auto_generated|dpfifo|FIFOram ; 24 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|jtag_uart_0|the_system_jtag_uart_0_scfifo_r|rfifo|auto_generated|dpfifo|fifo_state|count_usedw ; 5 ; 0 ; 0 ; 0 ; 6 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|jtag_uart_0|the_system_jtag_uart_0_scfifo_r|rfifo|auto_generated|dpfifo|fifo_state ; 5 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|jtag_uart_0|the_system_jtag_uart_0_scfifo_r|rfifo|auto_generated|dpfifo ; 13 ; 0 ; 0 ; 0 ; 16 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|jtag_uart_0|the_system_jtag_uart_0_scfifo_r|rfifo|auto_generated ; 12 ; 0 ; 0 ; 0 ; 16 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|jtag_uart_0|the_system_jtag_uart_0_scfifo_r ; 13 ; 0 ; 1 ; 0 ; 16 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|jtag_uart_0|the_system_jtag_uart_0_scfifo_w|wfifo|auto_generated|dpfifo|wr_ptr ; 4 ; 0 ; 0 ; 0 ; 6 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|jtag_uart_0|the_system_jtag_uart_0_scfifo_w|wfifo|auto_generated|dpfifo|rd_ptr_count ; 4 ; 0 ; 0 ; 0 ; 6 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|jtag_uart_0|the_system_jtag_uart_0_scfifo_w|wfifo|auto_generated|dpfifo|FIFOram|altsyncram1 ; 24 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|jtag_uart_0|the_system_jtag_uart_0_scfifo_w|wfifo|auto_generated|dpfifo|FIFOram ; 24 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|jtag_uart_0|the_system_jtag_uart_0_scfifo_w|wfifo|auto_generated|dpfifo|fifo_state|count_usedw ; 5 ; 0 ; 0 ; 0 ; 6 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|jtag_uart_0|the_system_jtag_uart_0_scfifo_w|wfifo|auto_generated|dpfifo|fifo_state ; 5 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|jtag_uart_0|the_system_jtag_uart_0_scfifo_w|wfifo|auto_generated|dpfifo ; 13 ; 0 ; 0 ; 0 ; 16 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|jtag_uart_0|the_system_jtag_uart_0_scfifo_w|wfifo|auto_generated ; 12 ; 0 ; 0 ; 0 ; 16 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|jtag_uart_0|the_system_jtag_uart_0_scfifo_w ; 12 ; 0 ; 0 ; 0 ; 16 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|jtag_uart_0 ; 38 ; 10 ; 23 ; 10 ; 34 ; 10 ; 10 ; 10 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|pio_sw ; 8 ; 0 ; 0 ; 0 ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|pio_key ; 6 ; 0 ; 0 ; 0 ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|pio_led ; 39 ; 25 ; 25 ; 25 ; 39 ; 25 ; 25 ; 25 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|uart_0|the_system_uart_0_regs ; 41 ; 0 ; 0 ; 0 ; 47 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|uart_0|the_system_uart_0_rx|the_system_uart_0_rx_stimulus_source ; 21 ; 0 ; 20 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|uart_0|the_system_uart_0_rx ; 23 ; 1 ; 0 ; 1 ; 13 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|uart_0|the_system_uart_0_tx ; 31 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|uart_0 ; 26 ; 0 ; 0 ; 0 ; 18 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|sys_clk_timer ; 23 ; 0 ; 0 ; 0 ; 17 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|sdram|the_system_sdram_input_efifo_module ; 46 ; 0 ; 0 ; 0 ; 46 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|sdram ; 46 ; 1 ; 1 ; 1 ; 40 ; 1 ; 1 ; 1 ; 16 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|sysid ; 3 ; 18 ; 2 ; 18 ; 32 ; 18 ; 18 ; 18 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|cpu ; 151 ; 0 ; 28 ; 0 ; 125 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu ; 10 ; 0 ; 0 ; 0 ; 32 ; 0 ; 0 ; 0 ; 16 ; 0 ; 0 ; 0 ; 0 ; +; inst_heartbeat ; 1 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_pll_sys|altpll_component|auto_generated ; 2 ; 0 ; 0 ; 0 ; 6 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_pll_sys ; 1 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; ++---------------------------------------------------------------------------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.map.bpm b/MCTEST/DE0-nano-HD/db/de0_nano_system.map.bpm new file mode 100644 index 00000000..6f75d513 Binary files /dev/null and b/MCTEST/DE0-nano-HD/db/de0_nano_system.map.bpm differ diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.map.cdb b/MCTEST/DE0-nano-HD/db/de0_nano_system.map.cdb new file mode 100644 index 00000000..a6ec0ada Binary files /dev/null and b/MCTEST/DE0-nano-HD/db/de0_nano_system.map.cdb differ diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.map.hdb b/MCTEST/DE0-nano-HD/db/de0_nano_system.map.hdb new file mode 100644 index 00000000..0a11bfb4 Binary files /dev/null and b/MCTEST/DE0-nano-HD/db/de0_nano_system.map.hdb differ diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.map.kpt b/MCTEST/DE0-nano-HD/db/de0_nano_system.map.kpt new file mode 100644 index 00000000..f92ae439 Binary files /dev/null and b/MCTEST/DE0-nano-HD/db/de0_nano_system.map.kpt differ diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.map.logdb b/MCTEST/DE0-nano-HD/db/de0_nano_system.map.logdb new file mode 100644 index 00000000..385cf1e7 --- /dev/null +++ b/MCTEST/DE0-nano-HD/db/de0_nano_system.map.logdb @@ -0,0 +1,3 @@ +v1 +DSP_BALANCING_IMPLEMENTATION,DSP_BLOCKS,system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3, +DSP_BALANCING_IMPLEMENTATION,DSP_BLOCKS,system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3, diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.map.qmsg b/MCTEST/DE0-nano-HD/db/de0_nano_system.map.qmsg new file mode 100644 index 00000000..9f585066 --- /dev/null +++ b/MCTEST/DE0-nano-HD/db/de0_nano_system.map.qmsg @@ -0,0 +1,308 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1 1394837310058 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Full Version " "Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1 1394837310059 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Mar 14 16:48:29 2014 " "Processing started: Fri Mar 14 16:48:29 2014" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1 1394837310059 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1 1394837310059 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off de0_nano_system -c de0_nano_system " "Command: quartus_map --read_settings_files=on --write_settings_files=off de0_nano_system -c de0_nano_system" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1 1394837310059 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." { } { } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "" 0 -1 1394837310397 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "de0_nano_system.vhd 2 1 " "Found 2 design units, including 1 entities, in source file de0_nano_system.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 de0_nano_system-syn " "Found design unit 1: de0_nano_system-syn" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 86 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1 1394837310843 ""} { "Info" "ISGN_ENTITY_NAME" "1 de0_nano_system " "Found entity 1: de0_nano_system" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 55 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837310843 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394837310843 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "heartbeat.vhd 2 1 " "Found 2 design units, including 1 entities, in source file heartbeat.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 heartbeat-syn " "Found design unit 1: heartbeat-syn" { } { { "heartbeat.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/heartbeat.vhd" 61 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1 1394837310846 ""} { "Info" "ISGN_ENTITY_NAME" "1 heartbeat " "Found entity 1: heartbeat" { } { { "heartbeat.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/heartbeat.vhd" 49 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837310846 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394837310846 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/system.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/system.v" { { "Info" "ISGN_ENTITY_NAME" "1 system " "Found entity 1: system" { } { { "system/synthesis/system.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 6 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837310859 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394837310859 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_irq_mapper.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_irq_mapper.sv" { { "Info" "ISGN_ENTITY_NAME" "1 system_irq_mapper " "Found entity 1: system_irq_mapper" { } { { "system/synthesis/submodules/system_irq_mapper.sv" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_irq_mapper.sv" 31 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837310861 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394837310861 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_merlin_width_adapter.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_width_adapter.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_width_adapter " "Found entity 1: altera_merlin_width_adapter" { } { { "system/synthesis/submodules/altera_merlin_width_adapter.sv" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_width_adapter.sv" 25 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837310866 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394837310866 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_merlin_burst_uncompressor.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_burst_uncompressor.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_burst_uncompressor " "Found entity 1: altera_merlin_burst_uncompressor" { } { { "system/synthesis/submodules/altera_merlin_burst_uncompressor.sv" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_burst_uncompressor.sv" 40 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837310869 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394837310869 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_merlin_address_alignment.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_address_alignment.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_address_alignment " "Found entity 1: altera_merlin_address_alignment" { } { { "system/synthesis/submodules/altera_merlin_address_alignment.sv" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_address_alignment.sv" 26 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837310871 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394837310871 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_merlin_arbitrator.sv 2 2 " "Found 2 design units, including 2 entities, in source file system/synthesis/submodules/altera_merlin_arbitrator.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_arbitrator " "Found entity 1: altera_merlin_arbitrator" { } { { "system/synthesis/submodules/altera_merlin_arbitrator.sv" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_arbitrator.sv" 103 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837310874 ""} { "Info" "ISGN_ENTITY_NAME" "2 altera_merlin_arb_adder " "Found entity 2: altera_merlin_arb_adder" { } { { "system/synthesis/submodules/altera_merlin_arbitrator.sv" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_arbitrator.sv" 228 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837310874 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394837310874 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_rsp_xbar_mux_001.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_rsp_xbar_mux_001.sv" { { "Info" "ISGN_ENTITY_NAME" "1 system_rsp_xbar_mux_001 " "Found entity 1: system_rsp_xbar_mux_001" { } { { "system/synthesis/submodules/system_rsp_xbar_mux_001.sv" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_rsp_xbar_mux_001.sv" 38 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837310877 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394837310877 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_rsp_xbar_mux.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_rsp_xbar_mux.sv" { { "Info" "ISGN_ENTITY_NAME" "1 system_rsp_xbar_mux " "Found entity 1: system_rsp_xbar_mux" { } { { "system/synthesis/submodules/system_rsp_xbar_mux.sv" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_rsp_xbar_mux.sv" 38 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837310880 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394837310880 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_rsp_xbar_demux_002.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_rsp_xbar_demux_002.sv" { { "Info" "ISGN_ENTITY_NAME" "1 system_rsp_xbar_demux_002 " "Found entity 1: system_rsp_xbar_demux_002" { } { { "system/synthesis/submodules/system_rsp_xbar_demux_002.sv" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_rsp_xbar_demux_002.sv" 43 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837310882 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394837310882 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_rsp_xbar_demux.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_rsp_xbar_demux.sv" { { "Info" "ISGN_ENTITY_NAME" "1 system_rsp_xbar_demux " "Found entity 1: system_rsp_xbar_demux" { } { { "system/synthesis/submodules/system_rsp_xbar_demux.sv" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_rsp_xbar_demux.sv" 43 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837310884 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394837310884 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_cmd_xbar_mux.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_cmd_xbar_mux.sv" { { "Info" "ISGN_ENTITY_NAME" "1 system_cmd_xbar_mux " "Found entity 1: system_cmd_xbar_mux" { } { { "system/synthesis/submodules/system_cmd_xbar_mux.sv" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cmd_xbar_mux.sv" 38 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837310887 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394837310887 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_cmd_xbar_demux_001.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_cmd_xbar_demux_001.sv" { { "Info" "ISGN_ENTITY_NAME" "1 system_cmd_xbar_demux_001 " "Found entity 1: system_cmd_xbar_demux_001" { } { { "system/synthesis/submodules/system_cmd_xbar_demux_001.sv" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cmd_xbar_demux_001.sv" 43 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837310889 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394837310889 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_cmd_xbar_demux.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_cmd_xbar_demux.sv" { { "Info" "ISGN_ENTITY_NAME" "1 system_cmd_xbar_demux " "Found entity 1: system_cmd_xbar_demux" { } { { "system/synthesis/submodules/system_cmd_xbar_demux.sv" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cmd_xbar_demux.sv" 43 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837310891 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394837310891 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_reset_controller.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_reset_controller.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_reset_controller " "Found entity 1: altera_reset_controller" { } { { "system/synthesis/submodules/altera_reset_controller.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_reset_controller.v" 28 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837310894 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394837310894 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_reset_synchronizer.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_reset_synchronizer.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_reset_synchronizer " "Found entity 1: altera_reset_synchronizer" { } { { "system/synthesis/submodules/altera_reset_synchronizer.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_reset_synchronizer.v" 24 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837310896 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394837310896 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_merlin_burst_adapter.sv 7 7 " "Found 7 design units, including 7 entities, in source file system/synthesis/submodules/altera_merlin_burst_adapter.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_burst_adapter_burstwrap_increment " "Found entity 1: altera_merlin_burst_adapter_burstwrap_increment" { } { { "system/synthesis/submodules/altera_merlin_burst_adapter.sv" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_burst_adapter.sv" 40 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837310901 ""} { "Info" "ISGN_ENTITY_NAME" "2 altera_merlin_burst_adapter_adder " "Found entity 2: altera_merlin_burst_adapter_adder" { } { { "system/synthesis/submodules/altera_merlin_burst_adapter.sv" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_burst_adapter.sv" 55 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837310901 ""} { "Info" "ISGN_ENTITY_NAME" "3 altera_merlin_burst_adapter_subtractor " "Found entity 3: altera_merlin_burst_adapter_subtractor" { } { { "system/synthesis/submodules/altera_merlin_burst_adapter.sv" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_burst_adapter.sv" 77 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837310901 ""} { "Info" "ISGN_ENTITY_NAME" "4 altera_merlin_burst_adapter_min " "Found entity 4: altera_merlin_burst_adapter_min" { } { { "system/synthesis/submodules/altera_merlin_burst_adapter.sv" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_burst_adapter.sv" 98 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837310901 ""} { "Info" "ISGN_ENTITY_NAME" "5 altera_merlin_burst_adapter " "Found entity 5: altera_merlin_burst_adapter" { } { { "system/synthesis/submodules/altera_merlin_burst_adapter.sv" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_burst_adapter.sv" 264 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837310901 ""} { "Info" "ISGN_ENTITY_NAME" "6 altera_merlin_burst_adapter_uncompressed_only " "Found entity 6: altera_merlin_burst_adapter_uncompressed_only" { } { { "system/synthesis/submodules/altera_merlin_burst_adapter.sv" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_burst_adapter.sv" 414 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837310901 ""} { "Info" "ISGN_ENTITY_NAME" "7 altera_merlin_burst_adapter_full " "Found entity 7: altera_merlin_burst_adapter_full" { } { { "system/synthesis/submodules/altera_merlin_burst_adapter.sv" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_burst_adapter.sv" 468 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837310901 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394837310901 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_merlin_traffic_limiter.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_traffic_limiter.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_traffic_limiter " "Found entity 1: altera_merlin_traffic_limiter" { } { { "system/synthesis/submodules/altera_merlin_traffic_limiter.sv" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_traffic_limiter.sv" 44 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837310905 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394837310905 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_avalon_st_pipeline_base.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_avalon_st_pipeline_base.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_avalon_st_pipeline_base " "Found entity 1: altera_avalon_st_pipeline_base" { } { { "system/synthesis/submodules/altera_avalon_st_pipeline_base.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_avalon_st_pipeline_base.v" 22 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837310907 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394837310907 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_id_router_002.sv 2 2 " "Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_id_router_002.sv" { { "Info" "ISGN_ENTITY_NAME" "1 system_id_router_002_default_decode " "Found entity 1: system_id_router_002_default_decode" { } { { "system/synthesis/submodules/system_id_router_002.sv" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_id_router_002.sv" 32 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837310910 ""} { "Info" "ISGN_ENTITY_NAME" "2 system_id_router_002 " "Found entity 2: system_id_router_002" { } { { "system/synthesis/submodules/system_id_router_002.sv" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_id_router_002.sv" 54 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837310910 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394837310910 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_id_router_001.sv 2 2 " "Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_id_router_001.sv" { { "Info" "ISGN_ENTITY_NAME" "1 system_id_router_001_default_decode " "Found entity 1: system_id_router_001_default_decode" { } { { "system/synthesis/submodules/system_id_router_001.sv" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_id_router_001.sv" 32 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837310913 ""} { "Info" "ISGN_ENTITY_NAME" "2 system_id_router_001 " "Found entity 2: system_id_router_001" { } { { "system/synthesis/submodules/system_id_router_001.sv" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_id_router_001.sv" 54 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837310913 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394837310913 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_id_router.sv 2 2 " "Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_id_router.sv" { { "Info" "ISGN_ENTITY_NAME" "1 system_id_router_default_decode " "Found entity 1: system_id_router_default_decode" { } { { "system/synthesis/submodules/system_id_router.sv" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_id_router.sv" 32 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837310915 ""} { "Info" "ISGN_ENTITY_NAME" "2 system_id_router " "Found entity 2: system_id_router" { } { { "system/synthesis/submodules/system_id_router.sv" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_id_router.sv" 54 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837310915 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394837310915 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_addr_router_001.sv 2 2 " "Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_addr_router_001.sv" { { "Info" "ISGN_ENTITY_NAME" "1 system_addr_router_001_default_decode " "Found entity 1: system_addr_router_001_default_decode" { } { { "system/synthesis/submodules/system_addr_router_001.sv" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_addr_router_001.sv" 32 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837310918 ""} { "Info" "ISGN_ENTITY_NAME" "2 system_addr_router_001 " "Found entity 2: system_addr_router_001" { } { { "system/synthesis/submodules/system_addr_router_001.sv" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_addr_router_001.sv" 54 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837310918 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394837310918 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_addr_router.sv 2 2 " "Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_addr_router.sv" { { "Info" "ISGN_ENTITY_NAME" "1 system_addr_router_default_decode " "Found entity 1: system_addr_router_default_decode" { } { { "system/synthesis/submodules/system_addr_router.sv" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_addr_router.sv" 32 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837310920 ""} { "Info" "ISGN_ENTITY_NAME" "2 system_addr_router " "Found entity 2: system_addr_router" { } { { "system/synthesis/submodules/system_addr_router.sv" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_addr_router.sv" 54 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837310920 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394837310920 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_avalon_sc_fifo.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_avalon_sc_fifo.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_avalon_sc_fifo " "Found entity 1: altera_avalon_sc_fifo" { } { { "system/synthesis/submodules/altera_avalon_sc_fifo.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_avalon_sc_fifo.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837310924 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394837310924 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_merlin_slave_agent.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_slave_agent.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_slave_agent " "Found entity 1: altera_merlin_slave_agent" { } { { "system/synthesis/submodules/altera_merlin_slave_agent.sv" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_slave_agent.sv" 34 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837310927 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394837310927 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_merlin_master_agent.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_master_agent.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_master_agent " "Found entity 1: altera_merlin_master_agent" { } { { "system/synthesis/submodules/altera_merlin_master_agent.sv" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_master_agent.sv" 28 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837310930 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394837310930 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_merlin_slave_translator.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_slave_translator.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_slave_translator " "Found entity 1: altera_merlin_slave_translator" { } { { "system/synthesis/submodules/altera_merlin_slave_translator.sv" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_slave_translator.sv" 35 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837310933 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394837310933 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_merlin_master_translator.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_master_translator.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_master_translator " "Found entity 1: altera_merlin_master_translator" { } { { "system/synthesis/submodules/altera_merlin_master_translator.sv" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_master_translator.sv" 30 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837310935 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394837310935 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_up_rs232_counters.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_up_rs232_counters.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_up_rs232_counters " "Found entity 1: altera_up_rs232_counters" { } { { "system/synthesis/submodules/altera_up_rs232_counters.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_up_rs232_counters.v" 48 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837310938 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394837310938 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_up_rs232_in_deserializer.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_up_rs232_in_deserializer.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_up_rs232_in_deserializer " "Found entity 1: altera_up_rs232_in_deserializer" { } { { "system/synthesis/submodules/altera_up_rs232_in_deserializer.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_up_rs232_in_deserializer.v" 47 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837310940 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394837310940 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_up_rs232_out_serializer.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_up_rs232_out_serializer.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_up_rs232_out_serializer " "Found entity 1: altera_up_rs232_out_serializer" { } { { "system/synthesis/submodules/altera_up_rs232_out_serializer.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_up_rs232_out_serializer.v" 47 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837310943 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394837310943 ""} +{ "Warning" "WVRFX_L2_VERI_INGORE_DANGLING_COMMA" "altera_up_sync_fifo.v(157) " "Verilog HDL Module Instantiation warning at altera_up_sync_fifo.v(157): ignored dangling comma in List of Port Connections" { } { { "system/synthesis/submodules/altera_up_sync_fifo.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_up_sync_fifo.v" 157 0 0 } } } 0 10275 "Verilog HDL Module Instantiation warning at %1!s!: ignored dangling comma in List of Port Connections" 0 0 "" 0 -1 1394837310946 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_up_sync_fifo.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_up_sync_fifo.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_up_sync_fifo " "Found entity 1: altera_up_sync_fifo" { } { { "system/synthesis/submodules/altera_up_sync_fifo.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_up_sync_fifo.v" 47 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837310946 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394837310946 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_rs232_motor.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_rs232_motor.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_rs232_motor " "Found entity 1: system_rs232_motor" { } { { "system/synthesis/submodules/system_rs232_motor.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_rs232_motor.v" 48 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837310948 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394837310948 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_pio_motor_rst.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_pio_motor_rst.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_pio_motor_rst " "Found entity 1: system_pio_motor_rst" { } { { "system/synthesis/submodules/system_pio_motor_rst.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_pio_motor_rst.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837310951 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394837310951 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_jtag_uart_0.v 7 7 " "Found 7 design units, including 7 entities, in source file system/synthesis/submodules/system_jtag_uart_0.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_jtag_uart_0_log_module " "Found entity 1: system_jtag_uart_0_log_module" { } { { "system/synthesis/submodules/system_jtag_uart_0.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_jtag_uart_0.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837310955 ""} { "Info" "ISGN_ENTITY_NAME" "2 system_jtag_uart_0_sim_scfifo_w " "Found entity 2: system_jtag_uart_0_sim_scfifo_w" { } { { "system/synthesis/submodules/system_jtag_uart_0.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_jtag_uart_0.v" 65 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837310955 ""} { "Info" "ISGN_ENTITY_NAME" "3 system_jtag_uart_0_scfifo_w " "Found entity 3: system_jtag_uart_0_scfifo_w" { } { { "system/synthesis/submodules/system_jtag_uart_0.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_jtag_uart_0.v" 123 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837310955 ""} { "Info" "ISGN_ENTITY_NAME" "4 system_jtag_uart_0_drom_module " "Found entity 4: system_jtag_uart_0_drom_module" { } { { "system/synthesis/submodules/system_jtag_uart_0.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_jtag_uart_0.v" 208 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837310955 ""} { "Info" "ISGN_ENTITY_NAME" "5 system_jtag_uart_0_sim_scfifo_r " "Found entity 5: system_jtag_uart_0_sim_scfifo_r" { } { { "system/synthesis/submodules/system_jtag_uart_0.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_jtag_uart_0.v" 362 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837310955 ""} { "Info" "ISGN_ENTITY_NAME" "6 system_jtag_uart_0_scfifo_r " "Found entity 6: system_jtag_uart_0_scfifo_r" { } { { "system/synthesis/submodules/system_jtag_uart_0.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_jtag_uart_0.v" 450 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837310955 ""} { "Info" "ISGN_ENTITY_NAME" "7 system_jtag_uart_0 " "Found entity 7: system_jtag_uart_0" { } { { "system/synthesis/submodules/system_jtag_uart_0.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_jtag_uart_0.v" 537 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837310955 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394837310955 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_pio_sw.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_pio_sw.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_pio_sw " "Found entity 1: system_pio_sw" { } { { "system/synthesis/submodules/system_pio_sw.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_pio_sw.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837310958 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394837310958 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_pio_key.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_pio_key.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_pio_key " "Found entity 1: system_pio_key" { } { { "system/synthesis/submodules/system_pio_key.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_pio_key.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837310960 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394837310960 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_pio_led.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_pio_led.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_pio_led " "Found entity 1: system_pio_led" { } { { "system/synthesis/submodules/system_pio_led.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_pio_led.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837310962 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394837310962 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_uart_0.v 7 7 " "Found 7 design units, including 7 entities, in source file system/synthesis/submodules/system_uart_0.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_uart_0_log_module " "Found entity 1: system_uart_0_log_module" { } { { "system/synthesis/submodules/system_uart_0.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_uart_0.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837310967 ""} { "Info" "ISGN_ENTITY_NAME" "2 system_uart_0_tx " "Found entity 2: system_uart_0_tx" { } { { "system/synthesis/submodules/system_uart_0.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_uart_0.v" 66 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837310967 ""} { "Info" "ISGN_ENTITY_NAME" "3 system_uart_0_rx_stimulus_source_character_source_rom_module " "Found entity 3: system_uart_0_rx_stimulus_source_character_source_rom_module" { } { { "system/synthesis/submodules/system_uart_0.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_uart_0.v" 238 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837310967 ""} { "Info" "ISGN_ENTITY_NAME" "4 system_uart_0_rx_stimulus_source " "Found entity 4: system_uart_0_rx_stimulus_source" { } { { "system/synthesis/submodules/system_uart_0.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_uart_0.v" 387 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837310967 ""} { "Info" "ISGN_ENTITY_NAME" "5 system_uart_0_rx " "Found entity 5: system_uart_0_rx" { } { { "system/synthesis/submodules/system_uart_0.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_uart_0.v" 492 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837310967 ""} { "Info" "ISGN_ENTITY_NAME" "6 system_uart_0_regs " "Found entity 6: system_uart_0_regs" { } { { "system/synthesis/submodules/system_uart_0.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_uart_0.v" 750 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837310967 ""} { "Info" "ISGN_ENTITY_NAME" "7 system_uart_0 " "Found entity 7: system_uart_0" { } { { "system/synthesis/submodules/system_uart_0.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_uart_0.v" 1006 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837310967 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394837310967 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_sys_clk_timer.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_sys_clk_timer.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_sys_clk_timer " "Found entity 1: system_sys_clk_timer" { } { { "system/synthesis/submodules/system_sys_clk_timer.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_sys_clk_timer.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837310969 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394837310969 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_sdram.v 2 2 " "Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_sdram.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_sdram_input_efifo_module " "Found entity 1: system_sdram_input_efifo_module" { } { { "system/synthesis/submodules/system_sdram.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_sdram.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837310973 ""} { "Info" "ISGN_ENTITY_NAME" "2 system_sdram " "Found entity 2: system_sdram" { } { { "system/synthesis/submodules/system_sdram.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_sdram.v" 158 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837310973 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394837310973 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_sysid.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_sysid.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_sysid " "Found entity 1: system_sysid" { } { { "system/synthesis/submodules/system_sysid.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_sysid.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837310975 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394837310975 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_cpu.v 28 28 " "Found 28 design units, including 28 entities, in source file system/synthesis/submodules/system_cpu.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_cpu_ic_data_module " "Found entity 1: system_cpu_ic_data_module" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837312382 ""} { "Info" "ISGN_ENTITY_NAME" "2 system_cpu_ic_tag_module " "Found entity 2: system_cpu_ic_tag_module" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 86 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837312382 ""} { "Info" "ISGN_ENTITY_NAME" "3 system_cpu_bht_module " "Found entity 3: system_cpu_bht_module" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 152 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837312382 ""} { "Info" "ISGN_ENTITY_NAME" "4 system_cpu_register_bank_a_module " "Found entity 4: system_cpu_register_bank_a_module" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 218 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837312382 ""} { "Info" "ISGN_ENTITY_NAME" "5 system_cpu_register_bank_b_module " "Found entity 5: system_cpu_register_bank_b_module" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 281 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837312382 ""} { "Info" "ISGN_ENTITY_NAME" "6 system_cpu_dc_tag_module " "Found entity 6: system_cpu_dc_tag_module" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 344 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837312382 ""} { "Info" "ISGN_ENTITY_NAME" "7 system_cpu_dc_data_module " "Found entity 7: system_cpu_dc_data_module" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 407 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837312382 ""} { "Info" "ISGN_ENTITY_NAME" "8 system_cpu_dc_victim_module " "Found entity 8: system_cpu_dc_victim_module" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 473 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837312382 ""} { "Info" "ISGN_ENTITY_NAME" "9 system_cpu_nios2_oci_debug " "Found entity 9: system_cpu_nios2_oci_debug" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 538 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837312382 ""} { "Info" "ISGN_ENTITY_NAME" "10 system_cpu_ociram_lpm_dram_bdp_component_module " "Found entity 10: system_cpu_ociram_lpm_dram_bdp_component_module" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 666 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837312382 ""} { "Info" "ISGN_ENTITY_NAME" "11 system_cpu_nios2_ocimem " "Found entity 11: system_cpu_nios2_ocimem" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 759 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837312382 ""} { "Info" "ISGN_ENTITY_NAME" "12 system_cpu_nios2_avalon_reg " "Found entity 12: system_cpu_nios2_avalon_reg" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 905 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837312382 ""} { "Info" "ISGN_ENTITY_NAME" "13 system_cpu_nios2_oci_break " "Found entity 13: system_cpu_nios2_oci_break" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 999 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837312382 ""} { "Info" "ISGN_ENTITY_NAME" "14 system_cpu_nios2_oci_xbrk " "Found entity 14: system_cpu_nios2_oci_xbrk" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 1293 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837312382 ""} { "Info" "ISGN_ENTITY_NAME" "15 system_cpu_nios2_oci_dbrk " "Found entity 15: system_cpu_nios2_oci_dbrk" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 1553 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837312382 ""} { "Info" "ISGN_ENTITY_NAME" "16 system_cpu_nios2_oci_itrace " "Found entity 16: system_cpu_nios2_oci_itrace" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 1741 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837312382 ""} { "Info" "ISGN_ENTITY_NAME" "17 system_cpu_nios2_oci_td_mode " "Found entity 17: system_cpu_nios2_oci_td_mode" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 2098 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837312382 ""} { "Info" "ISGN_ENTITY_NAME" "18 system_cpu_nios2_oci_dtrace " "Found entity 18: system_cpu_nios2_oci_dtrace" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 2165 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837312382 ""} { "Info" "ISGN_ENTITY_NAME" "19 system_cpu_nios2_oci_compute_tm_count " "Found entity 19: system_cpu_nios2_oci_compute_tm_count" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 2259 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837312382 ""} { "Info" "ISGN_ENTITY_NAME" "20 system_cpu_nios2_oci_fifowp_inc " "Found entity 20: system_cpu_nios2_oci_fifowp_inc" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 2330 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837312382 ""} { "Info" "ISGN_ENTITY_NAME" "21 system_cpu_nios2_oci_fifocount_inc " "Found entity 21: system_cpu_nios2_oci_fifocount_inc" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 2372 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837312382 ""} { "Info" "ISGN_ENTITY_NAME" "22 system_cpu_nios2_oci_fifo " "Found entity 22: system_cpu_nios2_oci_fifo" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 2418 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837312382 ""} { "Info" "ISGN_ENTITY_NAME" "23 system_cpu_nios2_oci_pib " "Found entity 23: system_cpu_nios2_oci_pib" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 2923 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837312382 ""} { "Info" "ISGN_ENTITY_NAME" "24 system_cpu_traceram_lpm_dram_bdp_component_module " "Found entity 24: system_cpu_traceram_lpm_dram_bdp_component_module" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 2991 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837312382 ""} { "Info" "ISGN_ENTITY_NAME" "25 system_cpu_nios2_oci_im " "Found entity 25: system_cpu_nios2_oci_im" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3080 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837312382 ""} { "Info" "ISGN_ENTITY_NAME" "26 system_cpu_nios2_performance_monitors " "Found entity 26: system_cpu_nios2_performance_monitors" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3217 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837312382 ""} { "Info" "ISGN_ENTITY_NAME" "27 system_cpu_nios2_oci " "Found entity 27: system_cpu_nios2_oci" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3233 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837312382 ""} { "Info" "ISGN_ENTITY_NAME" "28 system_cpu " "Found entity 28: system_cpu" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3736 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837312382 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394837312382 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_cpu_jtag_debug_module_sysclk.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_cpu_jtag_debug_module_sysclk.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_cpu_jtag_debug_module_sysclk " "Found entity 1: system_cpu_jtag_debug_module_sysclk" { } { { "system/synthesis/submodules/system_cpu_jtag_debug_module_sysclk.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu_jtag_debug_module_sysclk.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837312387 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394837312387 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_cpu_jtag_debug_module_tck.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_cpu_jtag_debug_module_tck.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_cpu_jtag_debug_module_tck " "Found entity 1: system_cpu_jtag_debug_module_tck" { } { { "system/synthesis/submodules/system_cpu_jtag_debug_module_tck.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu_jtag_debug_module_tck.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837312390 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394837312390 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_cpu_jtag_debug_module_wrapper " "Found entity 1: system_cpu_jtag_debug_module_wrapper" { } { { "system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837312393 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394837312393 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_cpu_mult_cell.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_cpu_mult_cell.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_cpu_mult_cell " "Found entity 1: system_cpu_mult_cell" { } { { "system/synthesis/submodules/system_cpu_mult_cell.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu_mult_cell.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837312396 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394837312396 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_cpu_oci_test_bench.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_cpu_oci_test_bench.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_cpu_oci_test_bench " "Found entity 1: system_cpu_oci_test_bench" { } { { "system/synthesis/submodules/system_cpu_oci_test_bench.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu_oci_test_bench.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837312398 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394837312398 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_cpu_test_bench.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_cpu_test_bench.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_cpu_test_bench " "Found entity 1: system_cpu_test_bench" { } { { "system/synthesis/submodules/system_cpu_test_bench.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu_test_bench.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837312401 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394837312401 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pll_sys.vhd 2 1 " "Found 2 design units, including 1 entities, in source file pll_sys.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 pll_sys-SYN " "Found design unit 1: pll_sys-SYN" { } { { "pll_sys.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/pll_sys.vhd" 54 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1 1394837312404 ""} { "Info" "ISGN_ENTITY_NAME" "1 pll_sys " "Found entity 1: pll_sys" { } { { "pll_sys.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/pll_sys.vhd" 42 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837312404 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394837312404 ""} +{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "system_cpu.v(2066) " "Verilog HDL or VHDL warning at system_cpu.v(2066): conditional expression evaluates to a constant" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 2066 0 0 } } } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1 1394837312427 ""} +{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "system_cpu.v(2068) " "Verilog HDL or VHDL warning at system_cpu.v(2068): conditional expression evaluates to a constant" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 2068 0 0 } } } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1 1394837312427 ""} +{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "system_cpu.v(2224) " "Verilog HDL or VHDL warning at system_cpu.v(2224): conditional expression evaluates to a constant" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 2224 0 0 } } } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1 1394837312427 ""} +{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "system_cpu.v(3143) " "Verilog HDL or VHDL warning at system_cpu.v(3143): conditional expression evaluates to a constant" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3143 0 0 } } } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1 1394837312431 ""} +{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "system_sdram.v(316) " "Verilog HDL or VHDL warning at system_sdram.v(316): conditional expression evaluates to a constant" { } { { "system/synthesis/submodules/system_sdram.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_sdram.v" 316 0 0 } } } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1 1394837312438 ""} +{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "system_sdram.v(326) " "Verilog HDL or VHDL warning at system_sdram.v(326): conditional expression evaluates to a constant" { } { { "system/synthesis/submodules/system_sdram.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_sdram.v" 326 0 0 } } } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1 1394837312438 ""} +{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "system_sdram.v(336) " "Verilog HDL or VHDL warning at system_sdram.v(336): conditional expression evaluates to a constant" { } { { "system/synthesis/submodules/system_sdram.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_sdram.v" 336 0 0 } } } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1 1394837312438 ""} +{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "system_sdram.v(680) " "Verilog HDL or VHDL warning at system_sdram.v(680): conditional expression evaluates to a constant" { } { { "system/synthesis/submodules/system_sdram.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_sdram.v" 680 0 0 } } } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1 1394837312440 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "de0_nano_system " "Elaborating entity \"de0_nano_system\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1 1394837312593 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pll_sys pll_sys:inst_pll_sys " "Elaborating entity \"pll_sys\" for hierarchy \"pll_sys:inst_pll_sys\"" { } { { "de0_nano_system.vhd" "inst_pll_sys" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 149 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837312597 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll pll_sys:inst_pll_sys\|altpll:altpll_component " "Elaborating entity \"altpll\" for hierarchy \"pll_sys:inst_pll_sys\|altpll:altpll_component\"" { } { { "pll_sys.vhd" "altpll_component" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/pll_sys.vhd" 154 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837312645 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "pll_sys:inst_pll_sys\|altpll:altpll_component " "Elaborated megafunction instantiation \"pll_sys:inst_pll_sys\|altpll:altpll_component\"" { } { { "pll_sys.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/pll_sys.vhd" 154 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1394837312649 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "pll_sys:inst_pll_sys\|altpll:altpll_component " "Instantiated megafunction \"pll_sys:inst_pll_sys\|altpll:altpll_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "bandwidth_type AUTO " "Parameter \"bandwidth_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837312653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_divide_by 1 " "Parameter \"clk0_divide_by\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837312653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_duty_cycle 50 " "Parameter \"clk0_duty_cycle\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837312653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_multiply_by 2 " "Parameter \"clk0_multiply_by\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837312653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_phase_shift 0 " "Parameter \"clk0_phase_shift\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837312653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_divide_by 1 " "Parameter \"clk1_divide_by\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837312653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_duty_cycle 50 " "Parameter \"clk1_duty_cycle\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837312653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_multiply_by 2 " "Parameter \"clk1_multiply_by\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837312653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_phase_shift -1500 " "Parameter \"clk1_phase_shift\" = \"-1500\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837312653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_divide_by 5 " "Parameter \"clk2_divide_by\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837312653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_duty_cycle 50 " "Parameter \"clk2_duty_cycle\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837312653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_multiply_by 1 " "Parameter \"clk2_multiply_by\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837312653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_phase_shift 0 " "Parameter \"clk2_phase_shift\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837312653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "compensate_clock CLK0 " "Parameter \"compensate_clock\" = \"CLK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837312653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "inclk0_input_frequency 20000 " "Parameter \"inclk0_input_frequency\" = \"20000\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837312653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837312653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint CBX_MODULE_PREFIX=pll_sys " "Parameter \"lpm_hint\" = \"CBX_MODULE_PREFIX=pll_sys\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837312653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altpll " "Parameter \"lpm_type\" = \"altpll\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837312653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode NORMAL " "Parameter \"operation_mode\" = \"NORMAL\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837312653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_type AUTO " "Parameter \"pll_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837312653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_activeclock PORT_UNUSED " "Parameter \"port_activeclock\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837312653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_areset PORT_UNUSED " "Parameter \"port_areset\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837312653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad0 PORT_UNUSED " "Parameter \"port_clkbad0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837312653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad1 PORT_UNUSED " "Parameter \"port_clkbad1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837312653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkloss PORT_UNUSED " "Parameter \"port_clkloss\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837312653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkswitch PORT_UNUSED " "Parameter \"port_clkswitch\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837312653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_configupdate PORT_UNUSED " "Parameter \"port_configupdate\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837312653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_fbin PORT_UNUSED " "Parameter \"port_fbin\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837312653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk0 PORT_USED " "Parameter \"port_inclk0\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837312653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk1 PORT_UNUSED " "Parameter \"port_inclk1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837312653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_locked PORT_USED " "Parameter \"port_locked\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837312653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pfdena PORT_UNUSED " "Parameter \"port_pfdena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837312653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasecounterselect PORT_UNUSED " "Parameter \"port_phasecounterselect\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837312653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasedone PORT_UNUSED " "Parameter \"port_phasedone\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837312653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasestep PORT_UNUSED " "Parameter \"port_phasestep\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837312653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phaseupdown PORT_UNUSED " "Parameter \"port_phaseupdown\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837312653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pllena PORT_UNUSED " "Parameter \"port_pllena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837312653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanaclr PORT_UNUSED " "Parameter \"port_scanaclr\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837312653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclk PORT_UNUSED " "Parameter \"port_scanclk\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837312653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclkena PORT_UNUSED " "Parameter \"port_scanclkena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837312653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandata PORT_UNUSED " "Parameter \"port_scandata\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837312653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandataout PORT_UNUSED " "Parameter \"port_scandataout\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837312653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandone PORT_UNUSED " "Parameter \"port_scandone\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837312653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanread PORT_UNUSED " "Parameter \"port_scanread\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837312653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanwrite PORT_UNUSED " "Parameter \"port_scanwrite\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837312653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk0 PORT_USED " "Parameter \"port_clk0\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837312653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk1 PORT_USED " "Parameter \"port_clk1\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837312653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk2 PORT_USED " "Parameter \"port_clk2\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837312653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk3 PORT_UNUSED " "Parameter \"port_clk3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837312653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk4 PORT_UNUSED " "Parameter \"port_clk4\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837312653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk5 PORT_UNUSED " "Parameter \"port_clk5\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837312653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena0 PORT_UNUSED " "Parameter \"port_clkena0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837312653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena1 PORT_UNUSED " "Parameter \"port_clkena1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837312653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena2 PORT_UNUSED " "Parameter \"port_clkena2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837312653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena3 PORT_UNUSED " "Parameter \"port_clkena3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837312653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena4 PORT_UNUSED " "Parameter \"port_clkena4\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837312653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena5 PORT_UNUSED " "Parameter \"port_clkena5\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837312653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk0 PORT_UNUSED " "Parameter \"port_extclk0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837312653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk1 PORT_UNUSED " "Parameter \"port_extclk1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837312653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk2 PORT_UNUSED " "Parameter \"port_extclk2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837312653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk3 PORT_UNUSED " "Parameter \"port_extclk3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837312653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "self_reset_on_loss_lock ON " "Parameter \"self_reset_on_loss_lock\" = \"ON\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837312653 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_clock 5 " "Parameter \"width_clock\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837312653 ""} } { { "pll_sys.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/pll_sys.vhd" 154 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1394837312653 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/pll_sys_altpll.v 1 1 " "Found 1 design units, including 1 entities, in source file db/pll_sys_altpll.v" { { "Info" "ISGN_ENTITY_NAME" "1 pll_sys_altpll " "Found entity 1: pll_sys_altpll" { } { { "db/pll_sys_altpll.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/pll_sys_altpll.v" 29 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837312716 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394837312716 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pll_sys_altpll pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated " "Elaborating entity \"pll_sys_altpll\" for hierarchy \"pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\"" { } { { "altpll.tdf" "auto_generated" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altpll.tdf" 897 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837312718 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "heartbeat heartbeat:inst_heartbeat " "Elaborating entity \"heartbeat\" for hierarchy \"heartbeat:inst_heartbeat\"" { } { { "de0_nano_system.vhd" "inst_heartbeat" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 158 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837312722 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system system:inst_cpu " "Elaborating entity \"system\" for hierarchy \"system:inst_cpu\"" { } { { "de0_nano_system.vhd" "inst_cpu" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 164 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837312725 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu system:inst_cpu\|system_cpu:cpu " "Elaborating entity \"system_cpu\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\"" { } { { "system/synthesis/system.v" "cpu" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 788 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837312773 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_test_bench system:inst_cpu\|system_cpu:cpu\|system_cpu_test_bench:the_system_cpu_test_bench " "Elaborating entity \"system_cpu_test_bench\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_test_bench:the_system_cpu_test_bench\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_test_bench" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 6059 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837312816 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_ic_data_module system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_data_module:system_cpu_ic_data " "Elaborating entity \"system_cpu_ic_data_module\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_data_module:system_cpu_ic_data\"" { } { { "system/synthesis/submodules/system_cpu.v" "system_cpu_ic_data" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 7084 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837312819 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_data_module:system_cpu_ic_data\|altsyncram:the_altsyncram " "Elaborating entity \"altsyncram\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_data_module:system_cpu_ic_data\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_altsyncram" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 58 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837312849 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_data_module:system_cpu_ic_data\|altsyncram:the_altsyncram " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_data_module:system_cpu_ic_data\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 58 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1394837312851 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_data_module:system_cpu_ic_data\|altsyncram:the_altsyncram " "Instantiated megafunction \"system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_data_module:system_cpu_ic_data\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837312852 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 0 " "Parameter \"maximum_depth\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837312852 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 2048 " "Parameter \"numwords_a\" = \"2048\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837312852 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 2048 " "Parameter \"numwords_b\" = \"2048\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837312852 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Parameter \"operation_mode\" = \"DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837312852 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837312852 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837312852 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rdcontrol_reg_b CLOCK0 " "Parameter \"rdcontrol_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837312852 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837312852 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 32 " "Parameter \"width_a\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837312852 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 32 " "Parameter \"width_b\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837312852 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 11 " "Parameter \"widthad_a\" = \"11\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837312852 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 11 " "Parameter \"widthad_b\" = \"11\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837312852 ""} } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 58 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1394837312852 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_sjd1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_sjd1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_sjd1 " "Found entity 1: altsyncram_sjd1" { } { { "db/altsyncram_sjd1.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_sjd1.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837312931 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394837312931 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_sjd1 system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_data_module:system_cpu_ic_data\|altsyncram:the_altsyncram\|altsyncram_sjd1:auto_generated " "Elaborating entity \"altsyncram_sjd1\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_data_module:system_cpu_ic_data\|altsyncram:the_altsyncram\|altsyncram_sjd1:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837312933 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_ic_tag_module system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_tag_module:system_cpu_ic_tag " "Elaborating entity \"system_cpu_ic_tag_module\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_tag_module:system_cpu_ic_tag\"" { } { { "system/synthesis/submodules/system_cpu.v" "system_cpu_ic_tag" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 7150 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837312938 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_tag_module:system_cpu_ic_tag\|altsyncram:the_altsyncram " "Elaborating entity \"altsyncram\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_tag_module:system_cpu_ic_tag\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_altsyncram" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 123 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837312953 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_tag_module:system_cpu_ic_tag\|altsyncram:the_altsyncram " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_tag_module:system_cpu_ic_tag\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 123 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1394837312955 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_tag_module:system_cpu_ic_tag\|altsyncram:the_altsyncram " "Instantiated megafunction \"system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_tag_module:system_cpu_ic_tag\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837312956 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file system_cpu_ic_tag_ram.mif " "Parameter \"init_file\" = \"system_cpu_ic_tag_ram.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837312956 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 0 " "Parameter \"maximum_depth\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837312956 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 256 " "Parameter \"numwords_a\" = \"256\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837312956 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 256 " "Parameter \"numwords_b\" = \"256\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837312956 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Parameter \"operation_mode\" = \"DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837312956 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837312956 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837312956 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rdcontrol_reg_b CLOCK0 " "Parameter \"rdcontrol_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837312956 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports OLD_DATA " "Parameter \"read_during_write_mode_mixed_ports\" = \"OLD_DATA\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837312956 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 21 " "Parameter \"width_a\" = \"21\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837312956 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 21 " "Parameter \"width_b\" = \"21\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837312956 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 8 " "Parameter \"widthad_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837312956 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 8 " "Parameter \"widthad_b\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837312956 ""} } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 123 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1394837312956 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_qtg1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_qtg1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_qtg1 " "Found entity 1: altsyncram_qtg1" { } { { "db/altsyncram_qtg1.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_qtg1.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837313027 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394837313027 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_qtg1 system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_tag_module:system_cpu_ic_tag\|altsyncram:the_altsyncram\|altsyncram_qtg1:auto_generated " "Elaborating entity \"altsyncram_qtg1\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_tag_module:system_cpu_ic_tag\|altsyncram:the_altsyncram\|altsyncram_qtg1:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837313029 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_bht_module system:inst_cpu\|system_cpu:cpu\|system_cpu_bht_module:system_cpu_bht " "Elaborating entity \"system_cpu_bht_module\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_bht_module:system_cpu_bht\"" { } { { "system/synthesis/submodules/system_cpu.v" "system_cpu_bht" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 7354 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837313050 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram system:inst_cpu\|system_cpu:cpu\|system_cpu_bht_module:system_cpu_bht\|altsyncram:the_altsyncram " "Elaborating entity \"altsyncram\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_bht_module:system_cpu_bht\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_altsyncram" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 189 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837313058 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_cpu:cpu\|system_cpu_bht_module:system_cpu_bht\|altsyncram:the_altsyncram " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_bht_module:system_cpu_bht\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 189 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1394837313059 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_cpu:cpu\|system_cpu_bht_module:system_cpu_bht\|altsyncram:the_altsyncram " "Instantiated megafunction \"system:inst_cpu\|system_cpu:cpu\|system_cpu_bht_module:system_cpu_bht\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313060 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file system_cpu_bht_ram.mif " "Parameter \"init_file\" = \"system_cpu_bht_ram.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313060 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 0 " "Parameter \"maximum_depth\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313060 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 256 " "Parameter \"numwords_a\" = \"256\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313060 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 256 " "Parameter \"numwords_b\" = \"256\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313060 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Parameter \"operation_mode\" = \"DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313060 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313060 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313060 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rdcontrol_reg_b CLOCK0 " "Parameter \"rdcontrol_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313060 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports OLD_DATA " "Parameter \"read_during_write_mode_mixed_ports\" = \"OLD_DATA\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313060 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 2 " "Parameter \"width_a\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313060 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 2 " "Parameter \"width_b\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313060 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 8 " "Parameter \"widthad_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313060 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 8 " "Parameter \"widthad_b\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313060 ""} } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 189 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1394837313060 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_fhg1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_fhg1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_fhg1 " "Found entity 1: altsyncram_fhg1" { } { { "db/altsyncram_fhg1.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_fhg1.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837313116 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394837313116 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_fhg1 system:inst_cpu\|system_cpu:cpu\|system_cpu_bht_module:system_cpu_bht\|altsyncram:the_altsyncram\|altsyncram_fhg1:auto_generated " "Elaborating entity \"altsyncram_fhg1\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_bht_module:system_cpu_bht\|altsyncram:the_altsyncram\|altsyncram_fhg1:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837313118 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_register_bank_a_module system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_a_module:system_cpu_register_bank_a " "Elaborating entity \"system_cpu_register_bank_a_module\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_a_module:system_cpu_register_bank_a\"" { } { { "system/synthesis/submodules/system_cpu.v" "system_cpu_register_bank_a" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 7500 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837313124 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_a_module:system_cpu_register_bank_a\|altsyncram:the_altsyncram " "Elaborating entity \"altsyncram\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_a_module:system_cpu_register_bank_a\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_altsyncram" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 252 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837313132 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_a_module:system_cpu_register_bank_a\|altsyncram:the_altsyncram " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_a_module:system_cpu_register_bank_a\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 252 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1394837313134 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_a_module:system_cpu_register_bank_a\|altsyncram:the_altsyncram " "Instantiated megafunction \"system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_a_module:system_cpu_register_bank_a\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313135 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file system_cpu_rf_ram_a.mif " "Parameter \"init_file\" = \"system_cpu_rf_ram_a.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313135 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 0 " "Parameter \"maximum_depth\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313135 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 32 " "Parameter \"numwords_a\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313135 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 32 " "Parameter \"numwords_b\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313135 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Parameter \"operation_mode\" = \"DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313135 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313135 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313135 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rdcontrol_reg_b CLOCK0 " "Parameter \"rdcontrol_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313135 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports OLD_DATA " "Parameter \"read_during_write_mode_mixed_ports\" = \"OLD_DATA\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313135 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 32 " "Parameter \"width_a\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313135 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 32 " "Parameter \"width_b\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313135 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 5 " "Parameter \"widthad_a\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313135 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 5 " "Parameter \"widthad_b\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313135 ""} } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 252 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1394837313135 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_fvf1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_fvf1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_fvf1 " "Found entity 1: altsyncram_fvf1" { } { { "db/altsyncram_fvf1.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_fvf1.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837313213 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394837313213 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_fvf1 system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_a_module:system_cpu_register_bank_a\|altsyncram:the_altsyncram\|altsyncram_fvf1:auto_generated " "Elaborating entity \"altsyncram_fvf1\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_a_module:system_cpu_register_bank_a\|altsyncram:the_altsyncram\|altsyncram_fvf1:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837313215 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_register_bank_b_module system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_b_module:system_cpu_register_bank_b " "Elaborating entity \"system_cpu_register_bank_b_module\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_b_module:system_cpu_register_bank_b\"" { } { { "system/synthesis/submodules/system_cpu.v" "system_cpu_register_bank_b" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 7521 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837313245 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_b_module:system_cpu_register_bank_b\|altsyncram:the_altsyncram " "Elaborating entity \"altsyncram\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_b_module:system_cpu_register_bank_b\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_altsyncram" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 315 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837313253 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_b_module:system_cpu_register_bank_b\|altsyncram:the_altsyncram " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_b_module:system_cpu_register_bank_b\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 315 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1394837313255 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_b_module:system_cpu_register_bank_b\|altsyncram:the_altsyncram " "Instantiated megafunction \"system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_b_module:system_cpu_register_bank_b\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313256 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file system_cpu_rf_ram_b.mif " "Parameter \"init_file\" = \"system_cpu_rf_ram_b.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313256 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 0 " "Parameter \"maximum_depth\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313256 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 32 " "Parameter \"numwords_a\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313256 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 32 " "Parameter \"numwords_b\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313256 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Parameter \"operation_mode\" = \"DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313256 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313256 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313256 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rdcontrol_reg_b CLOCK0 " "Parameter \"rdcontrol_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313256 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports OLD_DATA " "Parameter \"read_during_write_mode_mixed_ports\" = \"OLD_DATA\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313256 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 32 " "Parameter \"width_a\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313256 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 32 " "Parameter \"width_b\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313256 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 5 " "Parameter \"widthad_a\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313256 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 5 " "Parameter \"widthad_b\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313256 ""} } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 315 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1394837313256 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_gvf1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_gvf1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_gvf1 " "Found entity 1: altsyncram_gvf1" { } { { "db/altsyncram_gvf1.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_gvf1.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837313334 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394837313334 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_gvf1 system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_b_module:system_cpu_register_bank_b\|altsyncram:the_altsyncram\|altsyncram_gvf1:auto_generated " "Elaborating entity \"altsyncram_gvf1\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_b_module:system_cpu_register_bank_b\|altsyncram:the_altsyncram\|altsyncram_gvf1:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837313336 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_dc_tag_module system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_tag_module:system_cpu_dc_tag " "Elaborating entity \"system_cpu_dc_tag_module\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_tag_module:system_cpu_dc_tag\"" { } { { "system/synthesis/submodules/system_cpu.v" "system_cpu_dc_tag" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 7954 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837313367 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_tag_module:system_cpu_dc_tag\|altsyncram:the_altsyncram " "Elaborating entity \"altsyncram\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_tag_module:system_cpu_dc_tag\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_altsyncram" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 378 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837313375 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_tag_module:system_cpu_dc_tag\|altsyncram:the_altsyncram " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_tag_module:system_cpu_dc_tag\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 378 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1394837313377 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_tag_module:system_cpu_dc_tag\|altsyncram:the_altsyncram " "Instantiated megafunction \"system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_tag_module:system_cpu_dc_tag\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313378 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file system_cpu_dc_tag_ram.mif " "Parameter \"init_file\" = \"system_cpu_dc_tag_ram.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313378 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 0 " "Parameter \"maximum_depth\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313378 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 128 " "Parameter \"numwords_a\" = \"128\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313378 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 128 " "Parameter \"numwords_b\" = \"128\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313378 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Parameter \"operation_mode\" = \"DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313378 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313378 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313378 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rdcontrol_reg_b CLOCK0 " "Parameter \"rdcontrol_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313378 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports OLD_DATA " "Parameter \"read_during_write_mode_mixed_ports\" = \"OLD_DATA\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313378 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 16 " "Parameter \"width_a\" = \"16\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313378 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 16 " "Parameter \"width_b\" = \"16\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313378 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 7 " "Parameter \"widthad_a\" = \"7\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313378 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 7 " "Parameter \"widthad_b\" = \"7\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313378 ""} } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 378 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1394837313378 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_d9g1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_d9g1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_d9g1 " "Found entity 1: altsyncram_d9g1" { } { { "db/altsyncram_d9g1.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_d9g1.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837313445 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394837313445 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_d9g1 system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_tag_module:system_cpu_dc_tag\|altsyncram:the_altsyncram\|altsyncram_d9g1:auto_generated " "Elaborating entity \"altsyncram_d9g1\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_tag_module:system_cpu_dc_tag\|altsyncram:the_altsyncram\|altsyncram_d9g1:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837313447 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_dc_data_module system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_data_module:system_cpu_dc_data " "Elaborating entity \"system_cpu_dc_data_module\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_data_module:system_cpu_dc_data\"" { } { { "system/synthesis/submodules/system_cpu.v" "system_cpu_dc_data" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 8008 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837313464 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_data_module:system_cpu_dc_data\|altsyncram:the_altsyncram " "Elaborating entity \"altsyncram\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_data_module:system_cpu_dc_data\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_altsyncram" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 444 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837313472 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_data_module:system_cpu_dc_data\|altsyncram:the_altsyncram " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_data_module:system_cpu_dc_data\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 444 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1394837313474 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_data_module:system_cpu_dc_data\|altsyncram:the_altsyncram " "Instantiated megafunction \"system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_data_module:system_cpu_dc_data\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313475 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 0 " "Parameter \"maximum_depth\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313475 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 1024 " "Parameter \"numwords_a\" = \"1024\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313475 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 1024 " "Parameter \"numwords_b\" = \"1024\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313475 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Parameter \"operation_mode\" = \"DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313475 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313475 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313475 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rdcontrol_reg_b CLOCK0 " "Parameter \"rdcontrol_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313475 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313475 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 32 " "Parameter \"width_a\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313475 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 32 " "Parameter \"width_b\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313475 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 4 " "Parameter \"width_byteena_a\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313475 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 10 " "Parameter \"widthad_a\" = \"10\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313475 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 10 " "Parameter \"widthad_b\" = \"10\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313475 ""} } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 444 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1394837313475 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_2jf1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_2jf1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_2jf1 " "Found entity 1: altsyncram_2jf1" { } { { "db/altsyncram_2jf1.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_2jf1.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837313555 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394837313555 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_2jf1 system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_data_module:system_cpu_dc_data\|altsyncram:the_altsyncram\|altsyncram_2jf1:auto_generated " "Elaborating entity \"altsyncram_2jf1\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_data_module:system_cpu_dc_data\|altsyncram:the_altsyncram\|altsyncram_2jf1:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837313557 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_dc_victim_module system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_victim_module:system_cpu_dc_victim " "Elaborating entity \"system_cpu_dc_victim_module\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_victim_module:system_cpu_dc_victim\"" { } { { "system/synthesis/submodules/system_cpu.v" "system_cpu_dc_victim" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 8024 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837313561 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_victim_module:system_cpu_dc_victim\|altsyncram:the_altsyncram " "Elaborating entity \"altsyncram\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_victim_module:system_cpu_dc_victim\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_altsyncram" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 510 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837313569 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_victim_module:system_cpu_dc_victim\|altsyncram:the_altsyncram " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_victim_module:system_cpu_dc_victim\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 510 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1394837313571 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_victim_module:system_cpu_dc_victim\|altsyncram:the_altsyncram " "Instantiated megafunction \"system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_victim_module:system_cpu_dc_victim\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313572 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 0 " "Parameter \"maximum_depth\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313572 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 8 " "Parameter \"numwords_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313572 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 8 " "Parameter \"numwords_b\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313572 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Parameter \"operation_mode\" = \"DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313572 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313572 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313572 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rdcontrol_reg_b CLOCK0 " "Parameter \"rdcontrol_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313572 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports OLD_DATA " "Parameter \"read_during_write_mode_mixed_ports\" = \"OLD_DATA\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313572 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 32 " "Parameter \"width_a\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313572 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 32 " "Parameter \"width_b\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313572 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 3 " "Parameter \"widthad_a\" = \"3\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313572 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 3 " "Parameter \"widthad_b\" = \"3\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313572 ""} } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 510 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1394837313572 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_r3d1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_r3d1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_r3d1 " "Found entity 1: altsyncram_r3d1" { } { { "db/altsyncram_r3d1.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_r3d1.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837313647 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394837313647 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_r3d1 system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_victim_module:system_cpu_dc_victim\|altsyncram:the_altsyncram\|altsyncram_r3d1:auto_generated " "Elaborating entity \"altsyncram_r3d1\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_victim_module:system_cpu_dc_victim\|altsyncram:the_altsyncram\|altsyncram_r3d1:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837313649 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_mult_cell system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell " "Elaborating entity \"system_cpu_mult_cell\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_mult_cell" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 9849 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837313653 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altmult_add system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_1 " "Elaborating entity \"altmult_add\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_1\"" { } { { "system/synthesis/submodules/system_cpu_mult_cell.v" "the_altmult_add_part_1" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu_mult_cell.v" 52 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837313698 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_1 " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_1\"" { } { { "system/synthesis/submodules/system_cpu_mult_cell.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu_mult_cell.v" 52 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1394837313702 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_1 " "Instantiated megafunction \"system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_1\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "addnsub_multiplier_pipeline_aclr1 ACLR0 " "Parameter \"addnsub_multiplier_pipeline_aclr1\" = \"ACLR0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313704 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "addnsub_multiplier_pipeline_register1 CLOCK0 " "Parameter \"addnsub_multiplier_pipeline_register1\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313704 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "addnsub_multiplier_register1 UNREGISTERED " "Parameter \"addnsub_multiplier_register1\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313704 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "dedicated_multiplier_circuitry YES " "Parameter \"dedicated_multiplier_circuitry\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313704 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "input_register_a0 UNREGISTERED " "Parameter \"input_register_a0\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313704 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "input_register_b0 UNREGISTERED " "Parameter \"input_register_b0\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313704 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "input_source_a0 DATAA " "Parameter \"input_source_a0\" = \"DATAA\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313704 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "input_source_b0 DATAB " "Parameter \"input_source_b0\" = \"DATAB\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313704 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family CYCLONEIVE " "Parameter \"intended_device_family\" = \"CYCLONEIVE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313704 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altmult_add " "Parameter \"lpm_type\" = \"altmult_add\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313704 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "multiplier1_direction ADD " "Parameter \"multiplier1_direction\" = \"ADD\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313704 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "multiplier_aclr0 ACLR0 " "Parameter \"multiplier_aclr0\" = \"ACLR0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313704 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "multiplier_register0 CLOCK0 " "Parameter \"multiplier_register0\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313704 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "number_of_multipliers 1 " "Parameter \"number_of_multipliers\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313704 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_register UNREGISTERED " "Parameter \"output_register\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313704 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_addnsub1 PORT_UNUSED " "Parameter \"port_addnsub1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313704 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_addnsub3 PORT_UNUSED " "Parameter \"port_addnsub3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313704 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_signa PORT_UNUSED " "Parameter \"port_signa\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313704 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_signb PORT_UNUSED " "Parameter \"port_signb\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313704 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "representation_a UNSIGNED " "Parameter \"representation_a\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313704 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "representation_b UNSIGNED " "Parameter \"representation_b\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313704 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_pipeline_aclr_a ACLR0 " "Parameter \"signed_pipeline_aclr_a\" = \"ACLR0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313704 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_pipeline_aclr_b ACLR0 " "Parameter \"signed_pipeline_aclr_b\" = \"ACLR0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313704 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_pipeline_register_a CLOCK0 " "Parameter \"signed_pipeline_register_a\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313704 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_pipeline_register_b CLOCK0 " "Parameter \"signed_pipeline_register_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313704 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_register_a UNREGISTERED " "Parameter \"signed_register_a\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313704 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_register_b UNREGISTERED " "Parameter \"signed_register_b\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313704 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 16 " "Parameter \"width_a\" = \"16\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313704 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 16 " "Parameter \"width_b\" = \"16\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313704 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_result 32 " "Parameter \"width_result\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313704 ""} } { { "system/synthesis/submodules/system_cpu_mult_cell.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu_mult_cell.v" 52 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1394837313704 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mult_add_75u2.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mult_add_75u2.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mult_add_75u2 " "Found entity 1: mult_add_75u2" { } { { "db/mult_add_75u2.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/mult_add_75u2.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837313762 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394837313762 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mult_add_75u2 system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_1\|mult_add_75u2:auto_generated " "Elaborating entity \"mult_add_75u2\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_1\|mult_add_75u2:auto_generated\"" { } { { "altmult_add.tdf" "auto_generated" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altmult_add.tdf" 594 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837313765 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ded_mult_ks81.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/ded_mult_ks81.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 ded_mult_ks81 " "Found entity 1: ded_mult_ks81" { } { { "db/ded_mult_ks81.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/ded_mult_ks81.tdf" 30 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837313773 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394837313773 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ded_mult_ks81 system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_1\|mult_add_75u2:auto_generated\|ded_mult_ks81:ded_mult1 " "Elaborating entity \"ded_mult_ks81\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_1\|mult_add_75u2:auto_generated\|ded_mult_ks81:ded_mult1\"" { } { { "db/mult_add_75u2.tdf" "ded_mult1" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/mult_add_75u2.tdf" 33 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837313775 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/dffpipe_93c.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/dffpipe_93c.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 dffpipe_93c " "Found entity 1: dffpipe_93c" { } { { "db/dffpipe_93c.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/dffpipe_93c.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837313784 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394837313784 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dffpipe_93c system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_1\|mult_add_75u2:auto_generated\|ded_mult_ks81:ded_mult1\|dffpipe_93c:pre_result " "Elaborating entity \"dffpipe_93c\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_1\|mult_add_75u2:auto_generated\|ded_mult_ks81:ded_mult1\|dffpipe_93c:pre_result\"" { } { { "db/ded_mult_ks81.tdf" "pre_result" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/ded_mult_ks81.tdf" 50 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837313786 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altmult_add system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_2 " "Elaborating entity \"altmult_add\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_2\"" { } { { "system/synthesis/submodules/system_cpu_mult_cell.v" "the_altmult_add_part_2" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu_mult_cell.v" 93 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837313817 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_2 " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_2\"" { } { { "system/synthesis/submodules/system_cpu_mult_cell.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu_mult_cell.v" 93 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1394837313824 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_2 " "Instantiated megafunction \"system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_2\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "addnsub_multiplier_pipeline_aclr1 ACLR0 " "Parameter \"addnsub_multiplier_pipeline_aclr1\" = \"ACLR0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313825 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "addnsub_multiplier_pipeline_register1 CLOCK0 " "Parameter \"addnsub_multiplier_pipeline_register1\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313825 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "addnsub_multiplier_register1 UNREGISTERED " "Parameter \"addnsub_multiplier_register1\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313825 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "dedicated_multiplier_circuitry YES " "Parameter \"dedicated_multiplier_circuitry\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313825 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "input_register_a0 UNREGISTERED " "Parameter \"input_register_a0\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313825 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "input_register_b0 UNREGISTERED " "Parameter \"input_register_b0\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313825 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "input_source_a0 DATAA " "Parameter \"input_source_a0\" = \"DATAA\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313825 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "input_source_b0 DATAB " "Parameter \"input_source_b0\" = \"DATAB\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313825 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family CYCLONEIVE " "Parameter \"intended_device_family\" = \"CYCLONEIVE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313825 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altmult_add " "Parameter \"lpm_type\" = \"altmult_add\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313825 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "multiplier1_direction ADD " "Parameter \"multiplier1_direction\" = \"ADD\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313825 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "multiplier_aclr0 ACLR0 " "Parameter \"multiplier_aclr0\" = \"ACLR0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313825 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "multiplier_register0 CLOCK0 " "Parameter \"multiplier_register0\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313825 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "number_of_multipliers 1 " "Parameter \"number_of_multipliers\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313825 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_register UNREGISTERED " "Parameter \"output_register\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313825 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_addnsub1 PORT_UNUSED " "Parameter \"port_addnsub1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313825 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_addnsub3 PORT_UNUSED " "Parameter \"port_addnsub3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313825 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_signa PORT_UNUSED " "Parameter \"port_signa\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313825 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_signb PORT_UNUSED " "Parameter \"port_signb\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313825 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "representation_a UNSIGNED " "Parameter \"representation_a\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313825 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "representation_b UNSIGNED " "Parameter \"representation_b\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313825 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_pipeline_aclr_a ACLR0 " "Parameter \"signed_pipeline_aclr_a\" = \"ACLR0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313825 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_pipeline_aclr_b ACLR0 " "Parameter \"signed_pipeline_aclr_b\" = \"ACLR0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313825 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_pipeline_register_a CLOCK0 " "Parameter \"signed_pipeline_register_a\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313825 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_pipeline_register_b CLOCK0 " "Parameter \"signed_pipeline_register_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313825 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_register_a UNREGISTERED " "Parameter \"signed_register_a\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313825 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_register_b UNREGISTERED " "Parameter \"signed_register_b\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313825 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 16 " "Parameter \"width_a\" = \"16\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313825 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 16 " "Parameter \"width_b\" = \"16\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313825 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_result 16 " "Parameter \"width_result\" = \"16\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313825 ""} } { { "system/synthesis/submodules/system_cpu_mult_cell.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu_mult_cell.v" 93 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1394837313825 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mult_add_95u2.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mult_add_95u2.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mult_add_95u2 " "Found entity 1: mult_add_95u2" { } { { "db/mult_add_95u2.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/mult_add_95u2.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837313882 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394837313882 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mult_add_95u2 system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_2\|mult_add_95u2:auto_generated " "Elaborating entity \"mult_add_95u2\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_2\|mult_add_95u2:auto_generated\"" { } { { "altmult_add.tdf" "auto_generated" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altmult_add.tdf" 594 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837313884 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_oci system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci " "Elaborating entity \"system_cpu_nios2_oci\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_nios2_oci" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 10089 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837313892 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_oci_debug system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_debug:the_system_cpu_nios2_oci_debug " "Elaborating entity \"system_cpu_nios2_oci_debug\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_debug:the_system_cpu_nios2_oci_debug\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_nios2_oci_debug" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3444 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837313897 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_ocimem system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem " "Elaborating entity \"system_cpu_nios2_ocimem\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_nios2_ocimem" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3464 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837313898 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_ociram_lpm_dram_bdp_component_module system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem\|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component " "Elaborating entity \"system_cpu_ociram_lpm_dram_bdp_component_module\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem\|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component\"" { } { { "system/synthesis/submodules/system_cpu.v" "system_cpu_ociram_lpm_dram_bdp_component" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 872 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837313901 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem\|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component\|altsyncram:the_altsyncram " "Elaborating entity \"altsyncram\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem\|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_altsyncram" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 720 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837313909 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem\|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component\|altsyncram:the_altsyncram " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem\|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 720 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1394837313912 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem\|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component\|altsyncram:the_altsyncram " "Instantiated megafunction \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem\|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_a NONE " "Parameter \"address_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313913 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_b NONE " "Parameter \"address_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313913 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK1 " "Parameter \"address_reg_b\" = \"CLOCK1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313913 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_aclr_a NONE " "Parameter \"indata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313913 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_aclr_b NONE " "Parameter \"indata_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313913 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file system_cpu_ociram_default_contents.mif " "Parameter \"init_file\" = \"system_cpu_ociram_default_contents.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313913 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family CYCLONEIVE " "Parameter \"intended_device_family\" = \"CYCLONEIVE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313913 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313913 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 256 " "Parameter \"numwords_a\" = \"256\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313913 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 256 " "Parameter \"numwords_b\" = \"256\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313913 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode BIDIR_DUAL_PORT " "Parameter \"operation_mode\" = \"BIDIR_DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313913 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313913 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_b NONE " "Parameter \"outdata_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313913 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a UNREGISTERED " "Parameter \"outdata_reg_a\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313913 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313913 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313913 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports OLD_DATA " "Parameter \"read_during_write_mode_mixed_ports\" = \"OLD_DATA\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313913 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 32 " "Parameter \"width_a\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313913 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 32 " "Parameter \"width_b\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313913 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 4 " "Parameter \"width_byteena_a\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313913 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 8 " "Parameter \"widthad_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313913 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 8 " "Parameter \"widthad_b\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313913 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_aclr_a NONE " "Parameter \"wrcontrol_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313913 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_aclr_b NONE " "Parameter \"wrcontrol_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837313913 ""} } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 720 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1394837313913 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_jt72.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_jt72.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_jt72 " "Found entity 1: altsyncram_jt72" { } { { "db/altsyncram_jt72.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_jt72.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837314003 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394837314003 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_jt72 system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem\|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_jt72:auto_generated " "Elaborating entity \"altsyncram_jt72\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem\|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_jt72:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837314005 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_avalon_reg system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg " "Elaborating entity \"system_cpu_nios2_avalon_reg\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_nios2_avalon_reg" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3484 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837314037 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_oci_break system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_break:the_system_cpu_nios2_oci_break " "Elaborating entity \"system_cpu_nios2_oci_break\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_break:the_system_cpu_nios2_oci_break\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_nios2_oci_break" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3515 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837314039 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_oci_xbrk system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_xbrk:the_system_cpu_nios2_oci_xbrk " "Elaborating entity \"system_cpu_nios2_oci_xbrk\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_xbrk:the_system_cpu_nios2_oci_xbrk\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_nios2_oci_xbrk" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3538 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837314042 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_oci_dbrk system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_dbrk:the_system_cpu_nios2_oci_dbrk " "Elaborating entity \"system_cpu_nios2_oci_dbrk\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_dbrk:the_system_cpu_nios2_oci_dbrk\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_nios2_oci_dbrk" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3565 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837314043 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_oci_itrace system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_itrace:the_system_cpu_nios2_oci_itrace " "Elaborating entity \"system_cpu_nios2_oci_itrace\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_itrace:the_system_cpu_nios2_oci_itrace\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_nios2_oci_itrace" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3606 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837314045 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_oci_dtrace system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_dtrace:the_system_cpu_nios2_oci_dtrace " "Elaborating entity \"system_cpu_nios2_oci_dtrace\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_dtrace:the_system_cpu_nios2_oci_dtrace\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_nios2_oci_dtrace" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3621 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837314047 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_oci_td_mode system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_dtrace:the_system_cpu_nios2_oci_dtrace\|system_cpu_nios2_oci_td_mode:system_cpu_nios2_oci_trc_ctrl_td_mode " "Elaborating entity \"system_cpu_nios2_oci_td_mode\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_dtrace:the_system_cpu_nios2_oci_dtrace\|system_cpu_nios2_oci_td_mode:system_cpu_nios2_oci_trc_ctrl_td_mode\"" { } { { "system/synthesis/submodules/system_cpu.v" "system_cpu_nios2_oci_trc_ctrl_td_mode" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 2213 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837314050 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_oci_fifo system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_fifo:the_system_cpu_nios2_oci_fifo " "Elaborating entity \"system_cpu_nios2_oci_fifo\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_fifo:the_system_cpu_nios2_oci_fifo\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_nios2_oci_fifo" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3640 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837314051 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_oci_compute_tm_count system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_fifo:the_system_cpu_nios2_oci_fifo\|system_cpu_nios2_oci_compute_tm_count:system_cpu_nios2_oci_compute_tm_count_tm_count " "Elaborating entity \"system_cpu_nios2_oci_compute_tm_count\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_fifo:the_system_cpu_nios2_oci_fifo\|system_cpu_nios2_oci_compute_tm_count:system_cpu_nios2_oci_compute_tm_count_tm_count\"" { } { { "system/synthesis/submodules/system_cpu.v" "system_cpu_nios2_oci_compute_tm_count_tm_count" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 2545 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837314053 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_oci_fifowp_inc system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_fifo:the_system_cpu_nios2_oci_fifo\|system_cpu_nios2_oci_fifowp_inc:system_cpu_nios2_oci_fifowp_inc_fifowp " "Elaborating entity \"system_cpu_nios2_oci_fifowp_inc\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_fifo:the_system_cpu_nios2_oci_fifo\|system_cpu_nios2_oci_fifowp_inc:system_cpu_nios2_oci_fifowp_inc_fifowp\"" { } { { "system/synthesis/submodules/system_cpu.v" "system_cpu_nios2_oci_fifowp_inc_fifowp" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 2555 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837314055 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_oci_fifocount_inc system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_fifo:the_system_cpu_nios2_oci_fifo\|system_cpu_nios2_oci_fifocount_inc:system_cpu_nios2_oci_fifocount_inc_fifocount " "Elaborating entity \"system_cpu_nios2_oci_fifocount_inc\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_fifo:the_system_cpu_nios2_oci_fifo\|system_cpu_nios2_oci_fifocount_inc:system_cpu_nios2_oci_fifocount_inc_fifocount\"" { } { { "system/synthesis/submodules/system_cpu.v" "system_cpu_nios2_oci_fifocount_inc_fifocount" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 2565 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837314056 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_oci_test_bench system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_fifo:the_system_cpu_nios2_oci_fifo\|system_cpu_oci_test_bench:the_system_cpu_oci_test_bench " "Elaborating entity \"system_cpu_oci_test_bench\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_fifo:the_system_cpu_nios2_oci_fifo\|system_cpu_oci_test_bench:the_system_cpu_oci_test_bench\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_oci_test_bench" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 2574 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837314059 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_oci_pib system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_pib:the_system_cpu_nios2_oci_pib " "Elaborating entity \"system_cpu_nios2_oci_pib\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_pib:the_system_cpu_nios2_oci_pib\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_nios2_oci_pib" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3650 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837314061 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_oci_im system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im " "Elaborating entity \"system_cpu_nios2_oci_im\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_nios2_oci_im" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837314062 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_traceram_lpm_dram_bdp_component_module system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component " "Elaborating entity \"system_cpu_traceram_lpm_dram_bdp_component_module\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\"" { } { { "system/synthesis/submodules/system_cpu.v" "system_cpu_traceram_lpm_dram_bdp_component" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837314064 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram " "Elaborating entity \"altsyncram\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_altsyncram" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837314073 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1394837314075 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram " "Instantiated megafunction \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_a NONE " "Parameter \"address_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837314077 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_b NONE " "Parameter \"address_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837314077 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK1 " "Parameter \"address_reg_b\" = \"CLOCK1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837314077 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_aclr_a NONE " "Parameter \"indata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837314077 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_aclr_b NONE " "Parameter \"indata_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837314077 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file UNUSED " "Parameter \"init_file\" = \"UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837314077 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family CYCLONEIVE " "Parameter \"intended_device_family\" = \"CYCLONEIVE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837314077 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837314077 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 128 " "Parameter \"numwords_a\" = \"128\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837314077 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 128 " "Parameter \"numwords_b\" = \"128\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837314077 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode BIDIR_DUAL_PORT " "Parameter \"operation_mode\" = \"BIDIR_DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837314077 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837314077 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_b NONE " "Parameter \"outdata_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837314077 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a UNREGISTERED " "Parameter \"outdata_reg_a\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837314077 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837314077 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837314077 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports OLD_DATA " "Parameter \"read_during_write_mode_mixed_ports\" = \"OLD_DATA\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837314077 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 36 " "Parameter \"width_a\" = \"36\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837314077 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 36 " "Parameter \"width_b\" = \"36\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837314077 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 7 " "Parameter \"widthad_a\" = \"7\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837314077 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 7 " "Parameter \"widthad_b\" = \"7\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837314077 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_aclr_a NONE " "Parameter \"wrcontrol_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837314077 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_aclr_b NONE " "Parameter \"wrcontrol_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837314077 ""} } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1394837314077 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_0a02.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_0a02.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_0a02 " "Found entity 1: altsyncram_0a02" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_0a02.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837314166 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394837314166 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_0a02 system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated " "Elaborating entity \"altsyncram_0a02\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837314168 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_jtag_debug_module_wrapper system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper " "Elaborating entity \"system_cpu_jtag_debug_module_wrapper\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_jtag_debug_module_wrapper" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3714 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837314174 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_jtag_debug_module_tck system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck " "Elaborating entity \"system_cpu_jtag_debug_module_tck\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck\"" { } { { "system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v" "the_system_cpu_jtag_debug_module_tck" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v" 165 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837314177 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_std_synchronizer system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck\|altera_std_synchronizer:the_altera_std_synchronizer " "Elaborating entity \"altera_std_synchronizer\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck\|altera_std_synchronizer:the_altera_std_synchronizer\"" { } { { "system/synthesis/submodules/system_cpu_jtag_debug_module_tck.v" "the_altera_std_synchronizer" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu_jtag_debug_module_tck.v" 202 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837314189 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck\|altera_std_synchronizer:the_altera_std_synchronizer " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck\|altera_std_synchronizer:the_altera_std_synchronizer\"" { } { { "system/synthesis/submodules/system_cpu_jtag_debug_module_tck.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu_jtag_debug_module_tck.v" 202 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1394837314189 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck\|altera_std_synchronizer:the_altera_std_synchronizer " "Instantiated megafunction \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck\|altera_std_synchronizer:the_altera_std_synchronizer\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "depth 2 " "Parameter \"depth\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837314190 ""} } { { "system/synthesis/submodules/system_cpu_jtag_debug_module_tck.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu_jtag_debug_module_tck.v" 202 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1394837314190 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_jtag_debug_module_sysclk system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk " "Elaborating entity \"system_cpu_jtag_debug_module_sysclk\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk\"" { } { { "system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v" "the_system_cpu_jtag_debug_module_sysclk" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v" 188 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837314194 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sld_virtual_jtag_basic system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy " "Elaborating entity \"sld_virtual_jtag_basic\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy\"" { } { { "system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v" "system_cpu_jtag_debug_module_phy" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v" 218 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837314212 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy\"" { } { { "system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v" 218 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1394837314213 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy " "Instantiated megafunction \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_auto_instance_index YES " "Parameter \"sld_auto_instance_index\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837314213 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_instance_index 0 " "Parameter \"sld_instance_index\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837314213 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_ir_width 2 " "Parameter \"sld_ir_width\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837314213 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_mfg_id 70 " "Parameter \"sld_mfg_id\" = \"70\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837314213 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_sim_action " "Parameter \"sld_sim_action\" = \"\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837314213 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_sim_n_scan 0 " "Parameter \"sld_sim_n_scan\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837314213 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_sim_total_length 0 " "Parameter \"sld_sim_total_length\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837314213 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_type_id 34 " "Parameter \"sld_type_id\" = \"34\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837314213 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_version 3 " "Parameter \"sld_version\" = \"3\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837314213 ""} } { { "system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v" 218 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1394837314213 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sld_virtual_jtag_impl system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy\|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst " "Elaborating entity \"sld_virtual_jtag_impl\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy\|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst\"" { } { { "sld_virtual_jtag_basic.v" "sld_virtual_jtag_impl_inst" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/sld_virtual_jtag_basic.v" 151 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837314216 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy\|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy\|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst\", which is child of megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy\"" { } { { "sld_virtual_jtag_basic.v" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/sld_virtual_jtag_basic.v" 151 0 0 } } { "system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v" 218 0 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0 -1 1394837314217 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_sysid system:inst_cpu\|system_sysid:sysid " "Elaborating entity \"system_sysid\" for hierarchy \"system:inst_cpu\|system_sysid:sysid\"" { } { { "system/synthesis/system.v" "sysid" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 795 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837314220 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_sdram system:inst_cpu\|system_sdram:sdram " "Elaborating entity \"system_sdram\" for hierarchy \"system:inst_cpu\|system_sdram:sdram\"" { } { { "system/synthesis/system.v" "sdram" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 818 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837314222 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_sdram_input_efifo_module system:inst_cpu\|system_sdram:sdram\|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module " "Elaborating entity \"system_sdram_input_efifo_module\" for hierarchy \"system:inst_cpu\|system_sdram:sdram\|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module\"" { } { { "system/synthesis/submodules/system_sdram.v" "the_system_sdram_input_efifo_module" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_sdram.v" 296 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837314228 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_sys_clk_timer system:inst_cpu\|system_sys_clk_timer:sys_clk_timer " "Elaborating entity \"system_sys_clk_timer\" for hierarchy \"system:inst_cpu\|system_sys_clk_timer:sys_clk_timer\"" { } { { "system/synthesis/system.v" "sys_clk_timer" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 829 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837314231 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_uart_0 system:inst_cpu\|system_uart_0:uart_0 " "Elaborating entity \"system_uart_0\" for hierarchy \"system:inst_cpu\|system_uart_0:uart_0\"" { } { { "system/synthesis/system.v" "uart_0" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 846 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837314233 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_uart_0_tx system:inst_cpu\|system_uart_0:uart_0\|system_uart_0_tx:the_system_uart_0_tx " "Elaborating entity \"system_uart_0_tx\" for hierarchy \"system:inst_cpu\|system_uart_0:uart_0\|system_uart_0_tx:the_system_uart_0_tx\"" { } { { "system/synthesis/submodules/system_uart_0.v" "the_system_uart_0_tx" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_uart_0.v" 1079 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837314236 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_uart_0_rx system:inst_cpu\|system_uart_0:uart_0\|system_uart_0_rx:the_system_uart_0_rx " "Elaborating entity \"system_uart_0_rx\" for hierarchy \"system:inst_cpu\|system_uart_0:uart_0\|system_uart_0_rx:the_system_uart_0_rx\"" { } { { "system/synthesis/submodules/system_uart_0.v" "the_system_uart_0_rx" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_uart_0.v" 1097 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837314239 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_uart_0_rx_stimulus_source system:inst_cpu\|system_uart_0:uart_0\|system_uart_0_rx:the_system_uart_0_rx\|system_uart_0_rx_stimulus_source:the_system_uart_0_rx_stimulus_source " "Elaborating entity \"system_uart_0_rx_stimulus_source\" for hierarchy \"system:inst_cpu\|system_uart_0:uart_0\|system_uart_0_rx:the_system_uart_0_rx\|system_uart_0_rx_stimulus_source:the_system_uart_0_rx_stimulus_source\"" { } { { "system/synthesis/submodules/system_uart_0.v" "the_system_uart_0_rx_stimulus_source" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_uart_0.v" 569 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837314241 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_uart_0_regs system:inst_cpu\|system_uart_0:uart_0\|system_uart_0_regs:the_system_uart_0_regs " "Elaborating entity \"system_uart_0_regs\" for hierarchy \"system:inst_cpu\|system_uart_0:uart_0\|system_uart_0_regs:the_system_uart_0_regs\"" { } { { "system/synthesis/submodules/system_uart_0.v" "the_system_uart_0_regs" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_uart_0.v" 1128 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837314245 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_pio_led system:inst_cpu\|system_pio_led:pio_led " "Elaborating entity \"system_pio_led\" for hierarchy \"system:inst_cpu\|system_pio_led:pio_led\"" { } { { "system/synthesis/system.v" "pio_led" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 857 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837314248 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_pio_key system:inst_cpu\|system_pio_key:pio_key " "Elaborating entity \"system_pio_key\" for hierarchy \"system:inst_cpu\|system_pio_key:pio_key\"" { } { { "system/synthesis/system.v" "pio_key" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 865 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837314249 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_pio_sw system:inst_cpu\|system_pio_sw:pio_sw " "Elaborating entity \"system_pio_sw\" for hierarchy \"system:inst_cpu\|system_pio_sw:pio_sw\"" { } { { "system/synthesis/system.v" "pio_sw" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 873 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837314251 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_jtag_uart_0 system:inst_cpu\|system_jtag_uart_0:jtag_uart_0 " "Elaborating entity \"system_jtag_uart_0\" for hierarchy \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\"" { } { { "system/synthesis/system.v" "jtag_uart_0" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 886 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837314253 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_jtag_uart_0_scfifo_w system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w " "Elaborating entity \"system_jtag_uart_0_scfifo_w\" for hierarchy \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\"" { } { { "system/synthesis/submodules/system_jtag_uart_0.v" "the_system_jtag_uart_0_scfifo_w" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_jtag_uart_0.v" 625 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837314256 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scfifo system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo " "Elaborating entity \"scfifo\" for hierarchy \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\"" { } { { "system/synthesis/submodules/system_jtag_uart_0.v" "wfifo" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_jtag_uart_0.v" 183 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837314304 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo " "Elaborated megafunction instantiation \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\"" { } { { "system/synthesis/submodules/system_jtag_uart_0.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_jtag_uart_0.v" 183 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1394837314305 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo " "Instantiated megafunction \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint RAM_BLOCK_TYPE=AUTO " "Parameter \"lpm_hint\" = \"RAM_BLOCK_TYPE=AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837314306 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_numwords 64 " "Parameter \"lpm_numwords\" = \"64\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837314306 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_showahead OFF " "Parameter \"lpm_showahead\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837314306 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type scfifo " "Parameter \"lpm_type\" = \"scfifo\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837314306 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 8 " "Parameter \"lpm_width\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837314306 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widthu 6 " "Parameter \"lpm_widthu\" = \"6\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837314306 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "overflow_checking OFF " "Parameter \"overflow_checking\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837314306 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "underflow_checking OFF " "Parameter \"underflow_checking\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837314306 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "use_eab ON " "Parameter \"use_eab\" = \"ON\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837314306 ""} } { { "system/synthesis/submodules/system_jtag_uart_0.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_jtag_uart_0.v" 183 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1394837314306 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/scfifo_jr21.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/scfifo_jr21.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 scfifo_jr21 " "Found entity 1: scfifo_jr21" { } { { "db/scfifo_jr21.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/scfifo_jr21.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837314360 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394837314360 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scfifo_jr21 system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated " "Elaborating entity \"scfifo_jr21\" for hierarchy \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\"" { } { { "scfifo.tdf" "auto_generated" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/scfifo.tdf" 296 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837314362 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_dpfifo_q131.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/a_dpfifo_q131.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_dpfifo_q131 " "Found entity 1: a_dpfifo_q131" { } { { "db/a_dpfifo_q131.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/a_dpfifo_q131.tdf" 28 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837314370 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394837314370 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_dpfifo_q131 system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo " "Elaborating entity \"a_dpfifo_q131\" for hierarchy \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\"" { } { { "db/scfifo_jr21.tdf" "dpfifo" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/scfifo_jr21.tdf" 37 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837314372 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_fefifo_7cf.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/a_fefifo_7cf.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_fefifo_7cf " "Found entity 1: a_fefifo_7cf" { } { { "db/a_fefifo_7cf.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/a_fefifo_7cf.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837314381 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394837314381 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_fefifo_7cf system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|a_fefifo_7cf:fifo_state " "Elaborating entity \"a_fefifo_7cf\" for hierarchy \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|a_fefifo_7cf:fifo_state\"" { } { { "db/a_dpfifo_q131.tdf" "fifo_state" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/a_dpfifo_q131.tdf" 42 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837314383 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_do7.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_do7.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_do7 " "Found entity 1: cntr_do7" { } { { "db/cntr_do7.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/cntr_do7.tdf" 25 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837314435 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394837314435 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_do7 system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|a_fefifo_7cf:fifo_state\|cntr_do7:count_usedw " "Elaborating entity \"cntr_do7\" for hierarchy \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|a_fefifo_7cf:fifo_state\|cntr_do7:count_usedw\"" { } { { "db/a_fefifo_7cf.tdf" "count_usedw" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/a_fefifo_7cf.tdf" 38 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837314438 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/dpram_nl21.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/dpram_nl21.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 dpram_nl21 " "Found entity 1: dpram_nl21" { } { { "db/dpram_nl21.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/dpram_nl21.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837314491 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394837314491 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dpram_nl21 system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|dpram_nl21:FIFOram " "Elaborating entity \"dpram_nl21\" for hierarchy \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|dpram_nl21:FIFOram\"" { } { { "db/a_dpfifo_q131.tdf" "FIFOram" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/a_dpfifo_q131.tdf" 43 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837314493 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_r1m1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_r1m1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_r1m1 " "Found entity 1: altsyncram_r1m1" { } { { "db/altsyncram_r1m1.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_r1m1.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837314553 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394837314553 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_r1m1 system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|dpram_nl21:FIFOram\|altsyncram_r1m1:altsyncram1 " "Elaborating entity \"altsyncram_r1m1\" for hierarchy \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|dpram_nl21:FIFOram\|altsyncram_r1m1:altsyncram1\"" { } { { "db/dpram_nl21.tdf" "altsyncram1" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/dpram_nl21.tdf" 36 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837314556 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_1ob.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_1ob.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_1ob " "Found entity 1: cntr_1ob" { } { { "db/cntr_1ob.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/cntr_1ob.tdf" 25 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837314609 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394837314609 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_1ob system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|cntr_1ob:rd_ptr_count " "Elaborating entity \"cntr_1ob\" for hierarchy \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|cntr_1ob:rd_ptr_count\"" { } { { "db/a_dpfifo_q131.tdf" "rd_ptr_count" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/a_dpfifo_q131.tdf" 44 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837314611 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_jtag_uart_0_scfifo_r system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r " "Elaborating entity \"system_jtag_uart_0_scfifo_r\" for hierarchy \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r\"" { } { { "system/synthesis/submodules/system_jtag_uart_0.v" "the_system_jtag_uart_0_scfifo_r" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_jtag_uart_0.v" 639 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837314618 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_jtag_atlantic system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic " "Elaborating entity \"alt_jtag_atlantic\" for hierarchy \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic\"" { } { { "system/synthesis/submodules/system_jtag_uart_0.v" "system_jtag_uart_0_alt_jtag_atlantic" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_jtag_uart_0.v" 774 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837314731 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic " "Elaborated megafunction instantiation \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic\"" { } { { "system/synthesis/submodules/system_jtag_uart_0.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_jtag_uart_0.v" 774 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1394837314733 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic " "Instantiated megafunction \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "INSTANCE_ID 0 " "Parameter \"INSTANCE_ID\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837314733 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LOG2_RXFIFO_DEPTH 6 " "Parameter \"LOG2_RXFIFO_DEPTH\" = \"6\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837314733 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LOG2_TXFIFO_DEPTH 6 " "Parameter \"LOG2_TXFIFO_DEPTH\" = \"6\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837314733 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "SLD_AUTO_INSTANCE_INDEX YES " "Parameter \"SLD_AUTO_INSTANCE_INDEX\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837314733 ""} } { { "system/synthesis/submodules/system_jtag_uart_0.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_jtag_uart_0.v" 774 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1394837314733 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_pio_motor_rst system:inst_cpu\|system_pio_motor_rst:pio_motor_rst " "Elaborating entity \"system_pio_motor_rst\" for hierarchy \"system:inst_cpu\|system_pio_motor_rst:pio_motor_rst\"" { } { { "system/synthesis/system.v" "pio_motor_rst" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 897 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837314739 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_rs232_motor system:inst_cpu\|system_rs232_motor:rs232_motor " "Elaborating entity \"system_rs232_motor\" for hierarchy \"system:inst_cpu\|system_rs232_motor:rs232_motor\"" { } { { "system/synthesis/system.v" "rs232_motor" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 912 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837314741 ""} +{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "write_data_parity system_rs232_motor.v(123) " "Verilog HDL or VHDL warning at system_rs232_motor.v(123): object \"write_data_parity\" assigned a value but never read" { } { { "system/synthesis/submodules/system_rs232_motor.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_rs232_motor.v" 123 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 -1 1394837314742 "|de0_nano_system|system:inst_cpu|system_rs232_motor:rs232_motor"} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_up_rs232_in_deserializer system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_in_deserializer:RS232_In_Deserializer " "Elaborating entity \"altera_up_rs232_in_deserializer\" for hierarchy \"system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\"" { } { { "system/synthesis/submodules/system_rs232_motor.v" "RS232_In_Deserializer" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_rs232_motor.v" 268 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837314744 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_up_rs232_counters system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_rs232_counters:RS232_In_Counters " "Elaborating entity \"altera_up_rs232_counters\" for hierarchy \"system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_rs232_counters:RS232_In_Counters\"" { } { { "system/synthesis/submodules/altera_up_rs232_in_deserializer.v" "RS232_In_Counters" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_up_rs232_in_deserializer.v" 181 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837314747 ""} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 altera_up_rs232_counters.v(124) " "Verilog HDL assignment warning at altera_up_rs232_counters.v(124): truncated value with size 32 to match size of target (14)" { } { { "system/synthesis/submodules/altera_up_rs232_counters.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_up_rs232_counters.v" 124 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 -1 1394837314747 "|de0_nano_system|system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_rs232_counters:RS232_In_Counters"} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_up_sync_fifo system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO " "Elaborating entity \"altera_up_sync_fifo\" for hierarchy \"system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\"" { } { { "system/synthesis/submodules/altera_up_rs232_in_deserializer.v" "RS232_In_FIFO" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_up_rs232_in_deserializer.v" 206 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837314749 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scfifo system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO " "Elaborating entity \"scfifo\" for hierarchy \"system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\"" { } { { "system/synthesis/submodules/altera_up_sync_fifo.v" "Sync_FIFO" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_up_sync_fifo.v" 157 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837314780 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO " "Elaborated megafunction instantiation \"system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\"" { } { { "system/synthesis/submodules/altera_up_sync_fifo.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_up_sync_fifo.v" 157 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1394837314781 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO " "Instantiated megafunction \"system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "add_ram_output_register OFF " "Parameter \"add_ram_output_register\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837314781 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone II " "Parameter \"intended_device_family\" = \"Cyclone II\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837314781 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_numwords 128 " "Parameter \"lpm_numwords\" = \"128\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837314781 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_showahead ON " "Parameter \"lpm_showahead\" = \"ON\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837314781 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type scfifo " "Parameter \"lpm_type\" = \"scfifo\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837314781 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 8 " "Parameter \"lpm_width\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837314781 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widthu 7 " "Parameter \"lpm_widthu\" = \"7\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837314781 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "overflow_checking OFF " "Parameter \"overflow_checking\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837314781 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "underflow_checking OFF " "Parameter \"underflow_checking\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837314781 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "use_eab ON " "Parameter \"use_eab\" = \"ON\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837314781 ""} } { { "system/synthesis/submodules/altera_up_sync_fifo.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_up_sync_fifo.v" 157 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1394837314781 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/scfifo_a341.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/scfifo_a341.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 scfifo_a341 " "Found entity 1: scfifo_a341" { } { { "db/scfifo_a341.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/scfifo_a341.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837314835 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394837314835 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scfifo_a341 system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated " "Elaborating entity \"scfifo_a341\" for hierarchy \"system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\"" { } { { "scfifo.tdf" "auto_generated" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/scfifo.tdf" 296 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837314837 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_dpfifo_tq31.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/a_dpfifo_tq31.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_dpfifo_tq31 " "Found entity 1: a_dpfifo_tq31" { } { { "db/a_dpfifo_tq31.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/a_dpfifo_tq31.tdf" 32 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837314845 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394837314845 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_dpfifo_tq31 system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo " "Elaborating entity \"a_dpfifo_tq31\" for hierarchy \"system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\"" { } { { "db/scfifo_a341.tdf" "dpfifo" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/scfifo_a341.tdf" 37 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837314847 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_je81.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_je81.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_je81 " "Found entity 1: altsyncram_je81" { } { { "db/altsyncram_je81.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_je81.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837314907 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394837314907 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_je81 system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|altsyncram_je81:FIFOram " "Elaborating entity \"altsyncram_je81\" for hierarchy \"system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|altsyncram_je81:FIFOram\"" { } { { "db/a_dpfifo_tq31.tdf" "FIFOram" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/a_dpfifo_tq31.tdf" 45 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837314909 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cmpr_ks8.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cmpr_ks8.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cmpr_ks8 " "Found entity 1: cmpr_ks8" { } { { "db/cmpr_ks8.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/cmpr_ks8.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837314962 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394837314962 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cmpr_ks8 system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cmpr_ks8:almost_full_comparer " "Elaborating entity \"cmpr_ks8\" for hierarchy \"system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cmpr_ks8:almost_full_comparer\"" { } { { "db/a_dpfifo_tq31.tdf" "almost_full_comparer" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/a_dpfifo_tq31.tdf" 54 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837314964 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cmpr_ks8 system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cmpr_ks8:three_comparison " "Elaborating entity \"cmpr_ks8\" for hierarchy \"system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cmpr_ks8:three_comparison\"" { } { { "db/a_dpfifo_tq31.tdf" "three_comparison" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/a_dpfifo_tq31.tdf" 55 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837314968 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_v9b.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_v9b.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_v9b " "Found entity 1: cntr_v9b" { } { { "db/cntr_v9b.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/cntr_v9b.tdf" 25 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837315021 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394837315021 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_v9b system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_v9b:rd_ptr_msb " "Elaborating entity \"cntr_v9b\" for hierarchy \"system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_v9b:rd_ptr_msb\"" { } { { "db/a_dpfifo_tq31.tdf" "rd_ptr_msb" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/a_dpfifo_tq31.tdf" 56 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837315023 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_ca7.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_ca7.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_ca7 " "Found entity 1: cntr_ca7" { } { { "db/cntr_ca7.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/cntr_ca7.tdf" 25 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837315075 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394837315075 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_ca7 system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_ca7:usedw_counter " "Elaborating entity \"cntr_ca7\" for hierarchy \"system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_ca7:usedw_counter\"" { } { { "db/a_dpfifo_tq31.tdf" "usedw_counter" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/a_dpfifo_tq31.tdf" 57 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837315077 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_0ab.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_0ab.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_0ab " "Found entity 1: cntr_0ab" { } { { "db/cntr_0ab.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/cntr_0ab.tdf" 25 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837315130 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394837315130 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_0ab system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr " "Elaborating entity \"cntr_0ab\" for hierarchy \"system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr\"" { } { { "db/a_dpfifo_tq31.tdf" "wr_ptr" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/a_dpfifo_tq31.tdf" 58 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837315132 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_up_rs232_out_serializer system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_out_serializer:RS232_Out_Serializer " "Elaborating entity \"altera_up_rs232_out_serializer\" for hierarchy \"system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_out_serializer:RS232_Out_Serializer\"" { } { { "system/synthesis/submodules/system_rs232_motor.v" "RS232_Out_Serializer" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_rs232_motor.v" 290 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837315137 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_master_translator system:inst_cpu\|altera_merlin_master_translator:cpu_instruction_master_translator " "Elaborating entity \"altera_merlin_master_translator\" for hierarchy \"system:inst_cpu\|altera_merlin_master_translator:cpu_instruction_master_translator\"" { } { { "system/synthesis/system.v" "cpu_instruction_master_translator" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 966 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837315194 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_master_translator system:inst_cpu\|altera_merlin_master_translator:cpu_data_master_translator " "Elaborating entity \"altera_merlin_master_translator\" for hierarchy \"system:inst_cpu\|altera_merlin_master_translator:cpu_data_master_translator\"" { } { { "system/synthesis/system.v" "cpu_data_master_translator" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 1020 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837315196 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_translator system:inst_cpu\|altera_merlin_slave_translator:cpu_jtag_debug_module_translator " "Elaborating entity \"altera_merlin_slave_translator\" for hierarchy \"system:inst_cpu\|altera_merlin_slave_translator:cpu_jtag_debug_module_translator\"" { } { { "system/synthesis/system.v" "cpu_jtag_debug_module_translator" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 1078 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837315199 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_translator system:inst_cpu\|altera_merlin_slave_translator:sdram_s1_translator " "Elaborating entity \"altera_merlin_slave_translator\" for hierarchy \"system:inst_cpu\|altera_merlin_slave_translator:sdram_s1_translator\"" { } { { "system/synthesis/system.v" "sdram_s1_translator" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 1136 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837315202 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_translator system:inst_cpu\|altera_merlin_slave_translator:sysid_control_slave_translator " "Elaborating entity \"altera_merlin_slave_translator\" for hierarchy \"system:inst_cpu\|altera_merlin_slave_translator:sysid_control_slave_translator\"" { } { { "system/synthesis/system.v" "sysid_control_slave_translator" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 1194 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837315205 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_translator system:inst_cpu\|altera_merlin_slave_translator:sys_clk_timer_s1_translator " "Elaborating entity \"altera_merlin_slave_translator\" for hierarchy \"system:inst_cpu\|altera_merlin_slave_translator:sys_clk_timer_s1_translator\"" { } { { "system/synthesis/system.v" "sys_clk_timer_s1_translator" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 1252 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837315208 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_translator system:inst_cpu\|altera_merlin_slave_translator:uart_0_s1_translator " "Elaborating entity \"altera_merlin_slave_translator\" for hierarchy \"system:inst_cpu\|altera_merlin_slave_translator:uart_0_s1_translator\"" { } { { "system/synthesis/system.v" "uart_0_s1_translator" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 1310 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837315211 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_translator system:inst_cpu\|altera_merlin_slave_translator:pio_led_s1_translator " "Elaborating entity \"altera_merlin_slave_translator\" for hierarchy \"system:inst_cpu\|altera_merlin_slave_translator:pio_led_s1_translator\"" { } { { "system/synthesis/system.v" "pio_led_s1_translator" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 1368 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837315214 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_translator system:inst_cpu\|altera_merlin_slave_translator:pio_key_s1_translator " "Elaborating entity \"altera_merlin_slave_translator\" for hierarchy \"system:inst_cpu\|altera_merlin_slave_translator:pio_key_s1_translator\"" { } { { "system/synthesis/system.v" "pio_key_s1_translator" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 1426 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837315216 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_translator system:inst_cpu\|altera_merlin_slave_translator:jtag_uart_0_avalon_jtag_slave_translator " "Elaborating entity \"altera_merlin_slave_translator\" for hierarchy \"system:inst_cpu\|altera_merlin_slave_translator:jtag_uart_0_avalon_jtag_slave_translator\"" { } { { "system/synthesis/system.v" "jtag_uart_0_avalon_jtag_slave_translator" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 1542 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837315221 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_translator system:inst_cpu\|altera_merlin_slave_translator:rs232_motor_avalon_rs232_slave_translator " "Elaborating entity \"altera_merlin_slave_translator\" for hierarchy \"system:inst_cpu\|altera_merlin_slave_translator:rs232_motor_avalon_rs232_slave_translator\"" { } { { "system/synthesis/system.v" "rs232_motor_avalon_rs232_slave_translator" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 1658 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837315225 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_master_agent system:inst_cpu\|altera_merlin_master_agent:cpu_instruction_master_translator_avalon_universal_master_0_agent " "Elaborating entity \"altera_merlin_master_agent\" for hierarchy \"system:inst_cpu\|altera_merlin_master_agent:cpu_instruction_master_translator_avalon_universal_master_0_agent\"" { } { { "system/synthesis/system.v" "cpu_instruction_master_translator_avalon_universal_master_0_agent" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 1730 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837315228 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_master_agent system:inst_cpu\|altera_merlin_master_agent:cpu_data_master_translator_avalon_universal_master_0_agent " "Elaborating entity \"altera_merlin_master_agent\" for hierarchy \"system:inst_cpu\|altera_merlin_master_agent:cpu_data_master_translator_avalon_universal_master_0_agent\"" { } { { "system/synthesis/system.v" "cpu_data_master_translator_avalon_universal_master_0_agent" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 1802 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837315232 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_agent system:inst_cpu\|altera_merlin_slave_agent:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent " "Elaborating entity \"altera_merlin_slave_agent\" for hierarchy \"system:inst_cpu\|altera_merlin_slave_agent:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent\"" { } { { "system/synthesis/system.v" "cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 1878 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837315235 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_burst_uncompressor system:inst_cpu\|altera_merlin_slave_agent:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent\|altera_merlin_burst_uncompressor:uncompressor " "Elaborating entity \"altera_merlin_burst_uncompressor\" for hierarchy \"system:inst_cpu\|altera_merlin_slave_agent:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent\|altera_merlin_burst_uncompressor:uncompressor\"" { } { { "system/synthesis/submodules/altera_merlin_slave_agent.sv" "uncompressor" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_slave_agent.sv" 476 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837315239 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_avalon_sc_fifo system:inst_cpu\|altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo " "Elaborating entity \"altera_avalon_sc_fifo\" for hierarchy \"system:inst_cpu\|altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo\"" { } { { "system/synthesis/system.v" "cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 1919 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837315242 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_agent system:inst_cpu\|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent " "Elaborating entity \"altera_merlin_slave_agent\" for hierarchy \"system:inst_cpu\|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent\"" { } { { "system/synthesis/system.v" "sdram_s1_translator_avalon_universal_slave_0_agent" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 1995 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837315246 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_burst_uncompressor system:inst_cpu\|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent\|altera_merlin_burst_uncompressor:uncompressor " "Elaborating entity \"altera_merlin_burst_uncompressor\" for hierarchy \"system:inst_cpu\|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent\|altera_merlin_burst_uncompressor:uncompressor\"" { } { { "system/synthesis/submodules/altera_merlin_slave_agent.sv" "uncompressor" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_slave_agent.sv" 476 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837315249 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_avalon_sc_fifo system:inst_cpu\|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo " "Elaborating entity \"altera_avalon_sc_fifo\" for hierarchy \"system:inst_cpu\|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo\"" { } { { "system/synthesis/system.v" "sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 2036 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837315252 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_addr_router system:inst_cpu\|system_addr_router:addr_router " "Elaborating entity \"system_addr_router\" for hierarchy \"system:inst_cpu\|system_addr_router:addr_router\"" { } { { "system/synthesis/system.v" "addr_router" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 3105 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837315300 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_addr_router_default_decode system:inst_cpu\|system_addr_router:addr_router\|system_addr_router_default_decode:the_default_decode " "Elaborating entity \"system_addr_router_default_decode\" for hierarchy \"system:inst_cpu\|system_addr_router:addr_router\|system_addr_router_default_decode:the_default_decode\"" { } { { "system/synthesis/submodules/system_addr_router.sv" "the_default_decode" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_addr_router.sv" 140 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837315302 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_addr_router_001 system:inst_cpu\|system_addr_router_001:addr_router_001 " "Elaborating entity \"system_addr_router_001\" for hierarchy \"system:inst_cpu\|system_addr_router_001:addr_router_001\"" { } { { "system/synthesis/system.v" "addr_router_001" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 3121 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837315304 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_addr_router_001_default_decode system:inst_cpu\|system_addr_router_001:addr_router_001\|system_addr_router_001_default_decode:the_default_decode " "Elaborating entity \"system_addr_router_001_default_decode\" for hierarchy \"system:inst_cpu\|system_addr_router_001:addr_router_001\|system_addr_router_001_default_decode:the_default_decode\"" { } { { "system/synthesis/submodules/system_addr_router_001.sv" "the_default_decode" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_addr_router_001.sv" 149 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837315307 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_id_router system:inst_cpu\|system_id_router:id_router " "Elaborating entity \"system_id_router\" for hierarchy \"system:inst_cpu\|system_id_router:id_router\"" { } { { "system/synthesis/system.v" "id_router" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 3137 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837315309 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_id_router_default_decode system:inst_cpu\|system_id_router:id_router\|system_id_router_default_decode:the_default_decode " "Elaborating entity \"system_id_router_default_decode\" for hierarchy \"system:inst_cpu\|system_id_router:id_router\|system_id_router_default_decode:the_default_decode\"" { } { { "system/synthesis/submodules/system_id_router.sv" "the_default_decode" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_id_router.sv" 138 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837315311 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_id_router_001 system:inst_cpu\|system_id_router_001:id_router_001 " "Elaborating entity \"system_id_router_001\" for hierarchy \"system:inst_cpu\|system_id_router_001:id_router_001\"" { } { { "system/synthesis/system.v" "id_router_001" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 3153 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837315313 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_id_router_001_default_decode system:inst_cpu\|system_id_router_001:id_router_001\|system_id_router_001_default_decode:the_default_decode " "Elaborating entity \"system_id_router_001_default_decode\" for hierarchy \"system:inst_cpu\|system_id_router_001:id_router_001\|system_id_router_001_default_decode:the_default_decode\"" { } { { "system/synthesis/submodules/system_id_router_001.sv" "the_default_decode" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_id_router_001.sv" 138 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837315316 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_id_router_002 system:inst_cpu\|system_id_router_002:id_router_002 " "Elaborating entity \"system_id_router_002\" for hierarchy \"system:inst_cpu\|system_id_router_002:id_router_002\"" { } { { "system/synthesis/system.v" "id_router_002" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 3169 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837315317 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_id_router_002_default_decode system:inst_cpu\|system_id_router_002:id_router_002\|system_id_router_002_default_decode:the_default_decode " "Elaborating entity \"system_id_router_002_default_decode\" for hierarchy \"system:inst_cpu\|system_id_router_002:id_router_002\|system_id_router_002_default_decode:the_default_decode\"" { } { { "system/synthesis/submodules/system_id_router_002.sv" "the_default_decode" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_id_router_002.sv" 138 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837315320 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_traffic_limiter system:inst_cpu\|altera_merlin_traffic_limiter:limiter " "Elaborating entity \"altera_merlin_traffic_limiter\" for hierarchy \"system:inst_cpu\|altera_merlin_traffic_limiter:limiter\"" { } { { "system/synthesis/system.v" "limiter" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 3342 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837315338 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_burst_adapter system:inst_cpu\|altera_merlin_burst_adapter:burst_adapter " "Elaborating entity \"altera_merlin_burst_adapter\" for hierarchy \"system:inst_cpu\|altera_merlin_burst_adapter:burst_adapter\"" { } { { "system/synthesis/system.v" "burst_adapter" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 3435 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837315343 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_burst_adapter_uncompressed_only system:inst_cpu\|altera_merlin_burst_adapter:burst_adapter\|altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba " "Elaborating entity \"altera_merlin_burst_adapter_uncompressed_only\" for hierarchy \"system:inst_cpu\|altera_merlin_burst_adapter:burst_adapter\|altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba\"" { } { { "system/synthesis/submodules/altera_merlin_burst_adapter.sv" "altera_merlin_burst_adapter_uncompressed_only.the_ba" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_burst_adapter.sv" 397 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837315346 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_reset_controller system:inst_cpu\|altera_reset_controller:rst_controller " "Elaborating entity \"altera_reset_controller\" for hierarchy \"system:inst_cpu\|altera_reset_controller:rst_controller\"" { } { { "system/synthesis/system.v" "rst_controller" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 3460 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837315348 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_reset_synchronizer system:inst_cpu\|altera_reset_controller:rst_controller\|altera_reset_synchronizer:alt_rst_sync_uq1 " "Elaborating entity \"altera_reset_synchronizer\" for hierarchy \"system:inst_cpu\|altera_reset_controller:rst_controller\|altera_reset_synchronizer:alt_rst_sync_uq1\"" { } { { "system/synthesis/submodules/altera_reset_controller.v" "alt_rst_sync_uq1" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_reset_controller.v" 105 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837315350 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cmd_xbar_demux system:inst_cpu\|system_cmd_xbar_demux:cmd_xbar_demux " "Elaborating entity \"system_cmd_xbar_demux\" for hierarchy \"system:inst_cpu\|system_cmd_xbar_demux:cmd_xbar_demux\"" { } { { "system/synthesis/system.v" "cmd_xbar_demux" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 3483 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837315351 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cmd_xbar_demux_001 system:inst_cpu\|system_cmd_xbar_demux_001:cmd_xbar_demux_001 " "Elaborating entity \"system_cmd_xbar_demux_001\" for hierarchy \"system:inst_cpu\|system_cmd_xbar_demux_001:cmd_xbar_demux_001\"" { } { { "system/synthesis/system.v" "cmd_xbar_demux_001" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 3560 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837315353 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cmd_xbar_mux system:inst_cpu\|system_cmd_xbar_mux:cmd_xbar_mux " "Elaborating entity \"system_cmd_xbar_mux\" for hierarchy \"system:inst_cpu\|system_cmd_xbar_mux:cmd_xbar_mux\"" { } { { "system/synthesis/system.v" "cmd_xbar_mux" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 3583 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837315357 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arbitrator system:inst_cpu\|system_cmd_xbar_mux:cmd_xbar_mux\|altera_merlin_arbitrator:arb " "Elaborating entity \"altera_merlin_arbitrator\" for hierarchy \"system:inst_cpu\|system_cmd_xbar_mux:cmd_xbar_mux\|altera_merlin_arbitrator:arb\"" { } { { "system/synthesis/submodules/system_cmd_xbar_mux.sv" "arb" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cmd_xbar_mux.sv" 273 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837315360 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arb_adder system:inst_cpu\|system_cmd_xbar_mux:cmd_xbar_mux\|altera_merlin_arbitrator:arb\|altera_merlin_arb_adder:adder " "Elaborating entity \"altera_merlin_arb_adder\" for hierarchy \"system:inst_cpu\|system_cmd_xbar_mux:cmd_xbar_mux\|altera_merlin_arbitrator:arb\|altera_merlin_arb_adder:adder\"" { } { { "system/synthesis/submodules/altera_merlin_arbitrator.sv" "adder" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_arbitrator.sv" 169 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837315363 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_rsp_xbar_demux system:inst_cpu\|system_rsp_xbar_demux:rsp_xbar_demux " "Elaborating entity \"system_rsp_xbar_demux\" for hierarchy \"system:inst_cpu\|system_rsp_xbar_demux:rsp_xbar_demux\"" { } { { "system/synthesis/system.v" "rsp_xbar_demux" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 3629 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837315368 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_rsp_xbar_demux_002 system:inst_cpu\|system_rsp_xbar_demux_002:rsp_xbar_demux_002 " "Elaborating entity \"system_rsp_xbar_demux_002\" for hierarchy \"system:inst_cpu\|system_rsp_xbar_demux_002:rsp_xbar_demux_002\"" { } { { "system/synthesis/system.v" "rsp_xbar_demux_002" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 3669 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837315370 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_rsp_xbar_mux system:inst_cpu\|system_rsp_xbar_mux:rsp_xbar_mux " "Elaborating entity \"system_rsp_xbar_mux\" for hierarchy \"system:inst_cpu\|system_rsp_xbar_mux:rsp_xbar_mux\"" { } { { "system/synthesis/system.v" "rsp_xbar_mux" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 3828 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837315377 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arbitrator system:inst_cpu\|system_rsp_xbar_mux:rsp_xbar_mux\|altera_merlin_arbitrator:arb " "Elaborating entity \"altera_merlin_arbitrator\" for hierarchy \"system:inst_cpu\|system_rsp_xbar_mux:rsp_xbar_mux\|altera_merlin_arbitrator:arb\"" { } { { "system/synthesis/submodules/system_rsp_xbar_mux.sv" "arb" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_rsp_xbar_mux.sv" 296 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837315380 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_rsp_xbar_mux_001 system:inst_cpu\|system_rsp_xbar_mux_001:rsp_xbar_mux_001 " "Elaborating entity \"system_rsp_xbar_mux_001\" for hierarchy \"system:inst_cpu\|system_rsp_xbar_mux_001:rsp_xbar_mux_001\"" { } { { "system/synthesis/system.v" "rsp_xbar_mux_001" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 3905 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837315383 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arbitrator system:inst_cpu\|system_rsp_xbar_mux_001:rsp_xbar_mux_001\|altera_merlin_arbitrator:arb " "Elaborating entity \"altera_merlin_arbitrator\" for hierarchy \"system:inst_cpu\|system_rsp_xbar_mux_001:rsp_xbar_mux_001\|altera_merlin_arbitrator:arb\"" { } { { "system/synthesis/submodules/system_rsp_xbar_mux_001.sv" "arb" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_rsp_xbar_mux_001.sv" 440 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837315391 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arb_adder system:inst_cpu\|system_rsp_xbar_mux_001:rsp_xbar_mux_001\|altera_merlin_arbitrator:arb\|altera_merlin_arb_adder:adder " "Elaborating entity \"altera_merlin_arb_adder\" for hierarchy \"system:inst_cpu\|system_rsp_xbar_mux_001:rsp_xbar_mux_001\|altera_merlin_arbitrator:arb\|altera_merlin_arb_adder:adder\"" { } { { "system/synthesis/submodules/altera_merlin_arbitrator.sv" "adder" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_arbitrator.sv" 169 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837315393 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_width_adapter system:inst_cpu\|altera_merlin_width_adapter:width_adapter " "Elaborating entity \"altera_merlin_width_adapter\" for hierarchy \"system:inst_cpu\|altera_merlin_width_adapter:width_adapter\"" { } { { "system/synthesis/system.v" "width_adapter" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 3962 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837315395 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_width_adapter system:inst_cpu\|altera_merlin_width_adapter:width_adapter_001 " "Elaborating entity \"altera_merlin_width_adapter\" for hierarchy \"system:inst_cpu\|altera_merlin_width_adapter:width_adapter_001\"" { } { { "system/synthesis/system.v" "width_adapter_001" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 4019 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837315399 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_irq_mapper system:inst_cpu\|system_irq_mapper:irq_mapper " "Elaborating entity \"system_irq_mapper\" for hierarchy \"system:inst_cpu\|system_irq_mapper:irq_mapper\"" { } { { "system/synthesis/system.v" "irq_mapper" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 4029 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394837315404 ""} +{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "address_b system_cpu_traceram_lpm_dram_bdp_component 17 7 " "Port \"address_b\" on the entity instantiation of \"system_cpu_traceram_lpm_dram_bdp_component\" is connected to a signal of width 17. The formal width of the signal in the module is 7. The extra bits will be ignored." { } { { "system/synthesis/submodules/system_cpu.v" "system_cpu_traceram_lpm_dram_bdp_component" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } } 0 12020 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. The extra bits will be ignored." 0 0 "" 0 -1 1394837317041 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component"} +{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "jdo the_system_cpu_nios2_oci_itrace 38 16 " "Port \"jdo\" on the entity instantiation of \"the_system_cpu_nios2_oci_itrace\" is connected to a signal of width 38. The formal width of the signal in the module is 16. The extra bits will be ignored." { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_nios2_oci_itrace" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3606 0 0 } } } 0 12020 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. The extra bits will be ignored." 0 0 "" 0 -1 1394837317045 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_itrace:the_system_cpu_nios2_oci_itrace"} +{ "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_HDR" "" "Synthesized away the following node(s):" { { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_SUB_HDR" "RAM " "Synthesized away the following RAM node(s):" { { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[0\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[0\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_0a02.tdf" 43 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 10089 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 788 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 164 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1394837318170 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a0"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[1\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[1\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_0a02.tdf" 77 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 10089 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 788 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 164 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1394837318170 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a1"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[2\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[2\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_0a02.tdf" 111 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 10089 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 788 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 164 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1394837318170 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a2"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[3\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[3\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_0a02.tdf" 145 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 10089 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 788 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 164 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1394837318170 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a3"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[4\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[4\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_0a02.tdf" 179 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 10089 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 788 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 164 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1394837318170 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a4"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[5\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[5\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_0a02.tdf" 213 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 10089 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 788 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 164 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1394837318170 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a5"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[6\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[6\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_0a02.tdf" 247 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 10089 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 788 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 164 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1394837318170 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a6"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[7\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[7\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_0a02.tdf" 281 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 10089 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 788 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 164 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1394837318170 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a7"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[8\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[8\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_0a02.tdf" 315 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 10089 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 788 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 164 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1394837318170 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a8"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[9\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[9\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_0a02.tdf" 349 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 10089 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 788 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 164 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1394837318170 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a9"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[10\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[10\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_0a02.tdf" 383 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 10089 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 788 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 164 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1394837318170 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a10"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[11\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[11\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_0a02.tdf" 417 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 10089 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 788 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 164 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1394837318170 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a11"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[12\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[12\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_0a02.tdf" 451 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 10089 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 788 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 164 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1394837318170 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a12"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[13\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[13\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_0a02.tdf" 485 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 10089 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 788 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 164 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1394837318170 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a13"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[14\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[14\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_0a02.tdf" 519 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 10089 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 788 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 164 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1394837318170 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a14"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[15\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[15\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_0a02.tdf" 553 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 10089 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 788 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 164 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1394837318170 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a15"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[16\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[16\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_0a02.tdf" 587 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 10089 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 788 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 164 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1394837318170 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a16"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[17\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[17\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_0a02.tdf" 621 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 10089 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 788 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 164 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1394837318170 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a17"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[18\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[18\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_0a02.tdf" 655 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 10089 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 788 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 164 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1394837318170 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a18"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[19\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[19\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_0a02.tdf" 689 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 10089 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 788 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 164 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1394837318170 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a19"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[20\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[20\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_0a02.tdf" 723 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 10089 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 788 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 164 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1394837318170 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a20"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[21\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[21\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_0a02.tdf" 757 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 10089 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 788 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 164 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1394837318170 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a21"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[22\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[22\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_0a02.tdf" 791 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 10089 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 788 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 164 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1394837318170 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a22"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[23\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[23\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_0a02.tdf" 825 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 10089 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 788 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 164 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1394837318170 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a23"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[24\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[24\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_0a02.tdf" 859 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 10089 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 788 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 164 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1394837318170 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a24"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[25\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[25\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_0a02.tdf" 893 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 10089 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 788 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 164 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1394837318170 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a25"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[26\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[26\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_0a02.tdf" 927 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 10089 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 788 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 164 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1394837318170 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a26"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[27\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[27\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_0a02.tdf" 961 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 10089 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 788 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 164 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1394837318170 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a27"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[28\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[28\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_0a02.tdf" 995 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 10089 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 788 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 164 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1394837318170 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a28"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[29\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[29\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_0a02.tdf" 1029 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 10089 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 788 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 164 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1394837318170 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a29"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[30\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[30\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_0a02.tdf" 1063 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 10089 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 788 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 164 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1394837318170 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a30"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[31\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[31\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_0a02.tdf" 1097 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 10089 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 788 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 164 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1394837318170 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a31"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[32\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[32\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_0a02.tdf" 1131 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 10089 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 788 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 164 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1394837318170 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a32"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[33\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[33\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_0a02.tdf" 1165 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 10089 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 788 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 164 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1394837318170 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a33"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[34\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[34\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_0a02.tdf" 1199 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 10089 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 788 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 164 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1394837318170 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a34"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[35\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[35\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_0a02.tdf" 1233 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 10089 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 788 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 164 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1394837318170 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a35"} } { } 0 14285 "Synthesized away the following %1!s! node(s):" 0 0 "" 0 -1 1394837318170 ""} } { } 0 14284 "Synthesized away the following node(s):" 0 0 "" 0 -1 1394837318170 ""} +{ "Info" "ILPMS_INFERENCING_SUMMARY" "1 " "Inferred 1 megafunctions from design logic" { { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "system:inst_cpu\|system_cpu:cpu\|Add17 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"system:inst_cpu\|system_cpu:cpu\|Add17\"" { } { { "system/synthesis/submodules/system_cpu.v" "Add17" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 8729 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1 1394837323236 ""} } { } 0 278001 "Inferred %1!llu! megafunctions from design logic" 0 0 "" 0 -1 1394837323236 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_cpu:cpu\|lpm_add_sub:Add17 " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|lpm_add_sub:Add17\"" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 8729 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1394837323273 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_cpu:cpu\|lpm_add_sub:Add17 " "Instantiated megafunction \"system:inst_cpu\|system_cpu:cpu\|lpm_add_sub:Add17\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 33 " "Parameter \"LPM_WIDTH\" = \"33\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837323273 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION DEFAULT " "Parameter \"LPM_DIRECTION\" = \"DEFAULT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837323273 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837323273 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT NO " "Parameter \"ONE_INPUT_IS_CONSTANT\" = \"NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394837323273 ""} } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 8729 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1394837323273 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_qvi.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/add_sub_qvi.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_qvi " "Found entity 1: add_sub_qvi" { } { { "db/add_sub_qvi.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/add_sub_qvi.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394837323327 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394837323327 ""} +{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "2 " "2 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "" 0 -1 1394837324211 ""} +{ "Warning" "WMLS_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC_HDR" "" "The following nodes have both tri-state and non-tri-state drivers" { { "Warning" "WMLS_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC" "GPIO_0\[0\] " "Inserted always-enabled tri-state buffer between \"GPIO_0\[0\]\" and its non-tri-state driver." { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 -1 0 } } } 0 13035 "Inserted always-enabled tri-state buffer between \"%1!s!\" and its non-tri-state driver." 0 0 "" 0 -1 1394837324402 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC" "GPIO_1\[12\] " "Inserted always-enabled tri-state buffer between \"GPIO_1\[12\]\" and its non-tri-state driver." { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 -1 0 } } } 0 13035 "Inserted always-enabled tri-state buffer between \"%1!s!\" and its non-tri-state driver." 0 0 "" 0 -1 1394837324402 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC" "GPIO_1\[26\] " "Inserted always-enabled tri-state buffer between \"GPIO_1\[26\]\" and its non-tri-state driver." { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 -1 0 } } } 0 13035 "Inserted always-enabled tri-state buffer between \"%1!s!\" and its non-tri-state driver." 0 0 "" 0 -1 1394837324402 ""} } { } 0 13034 "The following nodes have both tri-state and non-tri-state drivers" 0 0 "" 0 -1 1394837324402 ""} +{ "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI_HDR" "" "The following bidir pins have no drivers" { { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[2\] " "Bidir \"GPIO_0\[2\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394837324403 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[3\] " "Bidir \"GPIO_0\[3\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394837324403 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[4\] " "Bidir \"GPIO_0\[4\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394837324403 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[5\] " "Bidir \"GPIO_0\[5\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394837324403 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[6\] " "Bidir \"GPIO_0\[6\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394837324403 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[7\] " "Bidir \"GPIO_0\[7\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394837324403 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[8\] " "Bidir \"GPIO_0\[8\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394837324403 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[9\] " "Bidir \"GPIO_0\[9\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394837324403 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[10\] " "Bidir \"GPIO_0\[10\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394837324403 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[11\] " "Bidir \"GPIO_0\[11\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394837324403 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[12\] " "Bidir \"GPIO_0\[12\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394837324403 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[13\] " "Bidir \"GPIO_0\[13\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394837324403 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[14\] " "Bidir \"GPIO_0\[14\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394837324403 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[15\] " "Bidir \"GPIO_0\[15\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394837324403 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[16\] " "Bidir \"GPIO_0\[16\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394837324403 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[17\] " "Bidir \"GPIO_0\[17\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394837324403 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[18\] " "Bidir \"GPIO_0\[18\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394837324403 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[19\] " "Bidir \"GPIO_0\[19\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394837324403 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[20\] " "Bidir \"GPIO_0\[20\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394837324403 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[21\] " "Bidir \"GPIO_0\[21\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394837324403 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[22\] " "Bidir \"GPIO_0\[22\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394837324403 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[23\] " "Bidir \"GPIO_0\[23\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394837324403 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[24\] " "Bidir \"GPIO_0\[24\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394837324403 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[25\] " "Bidir \"GPIO_0\[25\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394837324403 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[26\] " "Bidir \"GPIO_0\[26\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394837324403 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[27\] " "Bidir \"GPIO_0\[27\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394837324403 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[28\] " "Bidir \"GPIO_0\[28\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394837324403 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[29\] " "Bidir \"GPIO_0\[29\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394837324403 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[30\] " "Bidir \"GPIO_0\[30\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394837324403 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[31\] " "Bidir \"GPIO_0\[31\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394837324403 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[32\] " "Bidir \"GPIO_0\[32\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394837324403 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[33\] " "Bidir \"GPIO_0\[33\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394837324403 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[0\] " "Bidir \"GPIO_1\[0\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394837324403 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[1\] " "Bidir \"GPIO_1\[1\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394837324403 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[2\] " "Bidir \"GPIO_1\[2\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394837324403 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[3\] " "Bidir \"GPIO_1\[3\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394837324403 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[4\] " "Bidir \"GPIO_1\[4\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394837324403 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[5\] " "Bidir \"GPIO_1\[5\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394837324403 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[6\] " "Bidir \"GPIO_1\[6\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394837324403 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[7\] " "Bidir \"GPIO_1\[7\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394837324403 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[8\] " "Bidir \"GPIO_1\[8\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394837324403 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[9\] " "Bidir \"GPIO_1\[9\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394837324403 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[10\] " "Bidir \"GPIO_1\[10\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394837324403 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[11\] " "Bidir \"GPIO_1\[11\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394837324403 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[13\] " "Bidir \"GPIO_1\[13\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394837324403 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[14\] " "Bidir \"GPIO_1\[14\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394837324403 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[15\] " "Bidir \"GPIO_1\[15\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394837324403 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[16\] " "Bidir \"GPIO_1\[16\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394837324403 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[17\] " "Bidir \"GPIO_1\[17\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394837324403 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[18\] " "Bidir \"GPIO_1\[18\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394837324403 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[19\] " "Bidir \"GPIO_1\[19\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394837324403 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[20\] " "Bidir \"GPIO_1\[20\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394837324403 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[21\] " "Bidir \"GPIO_1\[21\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394837324403 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[22\] " "Bidir \"GPIO_1\[22\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394837324403 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[23\] " "Bidir \"GPIO_1\[23\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394837324403 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[25\] " "Bidir \"GPIO_1\[25\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394837324403 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[27\] " "Bidir \"GPIO_1\[27\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394837324403 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[28\] " "Bidir \"GPIO_1\[28\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394837324403 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[29\] " "Bidir \"GPIO_1\[29\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394837324403 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[30\] " "Bidir \"GPIO_1\[30\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394837324403 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[31\] " "Bidir \"GPIO_1\[31\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394837324403 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[32\] " "Bidir \"GPIO_1\[32\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394837324403 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[33\] " "Bidir \"GPIO_1\[33\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394837324403 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[1\] " "Bidir \"GPIO_0\[1\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394837324403 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[24\] " "Bidir \"GPIO_1\[24\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394837324403 ""} } { } 0 13039 "The following bidir pins have no drivers" 0 0 "" 0 -1 1394837324403 ""} +{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" { } { { "system/synthesis/submodules/system_sdram.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_sdram.v" 440 -1 0 } } { "system/synthesis/submodules/system_sdram.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_sdram.v" 354 -1 0 } } { "system/synthesis/submodules/altera_reset_synchronizer.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_reset_synchronizer.v" 62 -1 0 } } { "system/synthesis/submodules/system_sdram.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_sdram.v" 304 -1 0 } } { "system/synthesis/submodules/altera_merlin_slave_translator.sv" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_slave_translator.sv" 277 -1 0 } } { "system/synthesis/submodules/system_jtag_uart_0.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_jtag_uart_0.v" 558 -1 0 } } { "alt_jtag_atlantic.v" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/alt_jtag_atlantic.v" 291 -1 0 } } { "system/synthesis/submodules/system_uart_0.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_uart_0.v" 89 -1 0 } } { "system/synthesis/submodules/altera_merlin_arbitrator.sv" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_arbitrator.sv" 203 -1 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 5551 -1 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 5949 -1 0 } } { "system/synthesis/submodules/system_jtag_uart_0.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_jtag_uart_0.v" 603 -1 0 } } { "system/synthesis/submodules/system_uart_0.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_uart_0.v" 105 -1 0 } } { "alt_jtag_atlantic.v" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/alt_jtag_atlantic.v" 224 -1 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 5981 -1 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 9277 -1 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 9426 -1 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 982 -1 0 } } { "system/synthesis/submodules/system_uart_0.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_uart_0.v" 87 -1 0 } } { "system/synthesis/submodules/system_uart_0.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_uart_0.v" 88 -1 0 } } { "system/synthesis/submodules/system_uart_0.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_uart_0.v" 891 -1 0 } } { "system/synthesis/submodules/system_sys_clk_timer.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_sys_clk_timer.v" 166 -1 0 } } { "system/synthesis/submodules/system_sys_clk_timer.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_sys_clk_timer.v" 175 -1 0 } } } 0 13000 "Registers with preset signals will power-up high" 0 0 "" 0 -1 1394837324549 ""} +{ "Info" "IMLS_MLS_DEV_CLRN_SETS_REGISTERS" "" "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" { } { } 0 13003 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "" 0 -1 1394837324549 ""} +{ "Warning" "WMLS_MLS_ENABLED_OE" "" "TRI or OPNDRN buffers permanently enabled" { { "Warning" "WMLS_MLS_NODE_NAME" "GPIO_0\[0\]~synth " "Node \"GPIO_0\[0\]~synth\"" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 -1 0 } } } 0 13010 "Node \"%1!s!\"" 0 0 "" 0 -1 1394837326479 ""} { "Warning" "WMLS_MLS_NODE_NAME" "GPIO_1\[12\]~synth " "Node \"GPIO_1\[12\]~synth\"" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 -1 0 } } } 0 13010 "Node \"%1!s!\"" 0 0 "" 0 -1 1394837326479 ""} { "Warning" "WMLS_MLS_NODE_NAME" "GPIO_1\[26\]~synth " "Node \"GPIO_1\[26\]~synth\"" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 -1 0 } } } 0 13010 "Node \"%1!s!\"" 0 0 "" 0 -1 1394837326479 ""} } { } 0 13009 "TRI or OPNDRN buffers permanently enabled" 0 0 "" 0 -1 1394837326479 ""} +{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "DRAM_CKE VCC " "Pin \"DRAM_CKE\" is stuck at VCC" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 62 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1 1394837326480 "|de0_nano_system|DRAM_CKE"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "" 0 -1 1394837326480 ""} +{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING_ON_PARTITION" "Top " "Timing-Driven Synthesis is running on partition \"Top\"" { } { } 0 286031 "Timing-Driven Synthesis is running on partition \"%1!s!\"" 0 0 "" 0 -1 1394837327022 ""} +{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "370 " "370 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "" 0 -1 1394837329627 ""} +{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "1 0 1 0 0 " "Adding 1 node(s), including 0 DDIO, 1 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "" 0 -1 1394837330955 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "" 0 -1 1394837330955 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "5525 " "Implemented 5525 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "10 " "Implemented 10 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "" 0 -1 1394837331560 ""} { "Info" "ICUT_CUT_TM_OPINS" "32 " "Implemented 32 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "" 0 -1 1394837331560 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "84 " "Implemented 84 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "" 0 -1 1394837331560 ""} { "Info" "ICUT_CUT_TM_LCELLS" "5130 " "Implemented 5130 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "" 0 -1 1394837331560 ""} { "Info" "ICUT_CUT_TM_RAMS" "263 " "Implemented 263 RAM segments" { } { } 0 21064 "Implemented %1!d! RAM segments" 0 0 "" 0 -1 1394837331560 ""} { "Info" "ICUT_CUT_TM_PLLS" "1 " "Implemented 1 PLLs" { } { } 0 21065 "Implemented %1!d! PLLs" 0 0 "" 0 -1 1394837331560 ""} { "Info" "ICUT_CUT_TM_DSP_ELEM" "4 " "Implemented 4 DSP elements" { } { } 0 21062 "Implemented %1!d! DSP elements" 0 0 "" 0 -1 1394837331560 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1 1394837331560 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 128 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 128 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "644 " "Peak virtual memory: 644 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1 1394837331689 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Mar 14 16:48:51 2014 " "Processing ended: Fri Mar 14 16:48:51 2014" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1 1394837331689 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:22 " "Elapsed time: 00:00:22" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1 1394837331689 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:21 " "Total CPU time (on all processors): 00:00:21" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1 1394837331689 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1 1394837331689 ""} diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.map.rdb b/MCTEST/DE0-nano-HD/db/de0_nano_system.map.rdb new file mode 100644 index 00000000..44d90ad1 Binary files /dev/null and b/MCTEST/DE0-nano-HD/db/de0_nano_system.map.rdb differ diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.map_bb.cdb b/MCTEST/DE0-nano-HD/db/de0_nano_system.map_bb.cdb new file mode 100644 index 00000000..4701fe1d Binary files /dev/null and b/MCTEST/DE0-nano-HD/db/de0_nano_system.map_bb.cdb differ diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.map_bb.hdb b/MCTEST/DE0-nano-HD/db/de0_nano_system.map_bb.hdb new file mode 100644 index 00000000..2bd151da Binary files /dev/null and b/MCTEST/DE0-nano-HD/db/de0_nano_system.map_bb.hdb differ diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.map_bb.logdb b/MCTEST/DE0-nano-HD/db/de0_nano_system.map_bb.logdb new file mode 100644 index 00000000..385cf1e7 --- /dev/null +++ b/MCTEST/DE0-nano-HD/db/de0_nano_system.map_bb.logdb @@ -0,0 +1,3 @@ +v1 +DSP_BALANCING_IMPLEMENTATION,DSP_BLOCKS,system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3, +DSP_BALANCING_IMPLEMENTATION,DSP_BLOCKS,system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3, diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.pre_map.cdb b/MCTEST/DE0-nano-HD/db/de0_nano_system.pre_map.cdb new file mode 100644 index 00000000..9a11445b Binary files /dev/null and b/MCTEST/DE0-nano-HD/db/de0_nano_system.pre_map.cdb differ diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.pre_map.hdb b/MCTEST/DE0-nano-HD/db/de0_nano_system.pre_map.hdb new file mode 100644 index 00000000..807acf97 Binary files /dev/null and b/MCTEST/DE0-nano-HD/db/de0_nano_system.pre_map.hdb differ diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.qns b/MCTEST/DE0-nano-HD/db/de0_nano_system.qns new file mode 100644 index 00000000..499d5cf5 --- /dev/null +++ b/MCTEST/DE0-nano-HD/db/de0_nano_system.qns @@ -0,0 +1 @@ +de0_nano_system/done diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.root_partition.map.reg_db.cdb b/MCTEST/DE0-nano-HD/db/de0_nano_system.root_partition.map.reg_db.cdb new file mode 100644 index 00000000..56cb22c8 Binary files /dev/null and b/MCTEST/DE0-nano-HD/db/de0_nano_system.root_partition.map.reg_db.cdb differ diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.routing.rdb b/MCTEST/DE0-nano-HD/db/de0_nano_system.routing.rdb new file mode 100644 index 00000000..9feff4bd Binary files /dev/null and b/MCTEST/DE0-nano-HD/db/de0_nano_system.routing.rdb differ diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.rtlv.hdb b/MCTEST/DE0-nano-HD/db/de0_nano_system.rtlv.hdb new file mode 100644 index 00000000..51fd8764 Binary files /dev/null and b/MCTEST/DE0-nano-HD/db/de0_nano_system.rtlv.hdb differ diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.rtlv_sg.cdb b/MCTEST/DE0-nano-HD/db/de0_nano_system.rtlv_sg.cdb new file mode 100644 index 00000000..e5deb3f0 Binary files /dev/null and b/MCTEST/DE0-nano-HD/db/de0_nano_system.rtlv_sg.cdb differ diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.rtlv_sg_swap.cdb b/MCTEST/DE0-nano-HD/db/de0_nano_system.rtlv_sg_swap.cdb new file mode 100644 index 00000000..918415d7 Binary files /dev/null and b/MCTEST/DE0-nano-HD/db/de0_nano_system.rtlv_sg_swap.cdb differ diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.sas b/MCTEST/DE0-nano-HD/db/de0_nano_system.sas new file mode 100644 index 00000000..3ba1e03b --- /dev/null +++ b/MCTEST/DE0-nano-HD/db/de0_nano_system.sas @@ -0,0 +1 @@ +de0_nano_system/DONE diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.sgdiff.cdb b/MCTEST/DE0-nano-HD/db/de0_nano_system.sgdiff.cdb new file mode 100644 index 00000000..8f9c58e3 Binary files /dev/null and b/MCTEST/DE0-nano-HD/db/de0_nano_system.sgdiff.cdb differ diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.sgdiff.hdb b/MCTEST/DE0-nano-HD/db/de0_nano_system.sgdiff.hdb new file mode 100644 index 00000000..d8da6859 Binary files /dev/null and b/MCTEST/DE0-nano-HD/db/de0_nano_system.sgdiff.hdb differ diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.sld_design_entry.sci b/MCTEST/DE0-nano-HD/db/de0_nano_system.sld_design_entry.sci new file mode 100644 index 00000000..e64fc065 Binary files /dev/null and b/MCTEST/DE0-nano-HD/db/de0_nano_system.sld_design_entry.sci differ diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.sld_design_entry_dsc.sci b/MCTEST/DE0-nano-HD/db/de0_nano_system.sld_design_entry_dsc.sci new file mode 100644 index 00000000..8175246a Binary files /dev/null and b/MCTEST/DE0-nano-HD/db/de0_nano_system.sld_design_entry_dsc.sci differ diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.smart_action.txt b/MCTEST/DE0-nano-HD/db/de0_nano_system.smart_action.txt new file mode 100644 index 00000000..c8e8a135 --- /dev/null +++ b/MCTEST/DE0-nano-HD/db/de0_nano_system.smart_action.txt @@ -0,0 +1 @@ +DONE diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.smp_dump.txt b/MCTEST/DE0-nano-HD/db/de0_nano_system.smp_dump.txt new file mode 100644 index 00000000..0c03298a --- /dev/null +++ b/MCTEST/DE0-nano-HD/db/de0_nano_system.smp_dump.txt @@ -0,0 +1,44 @@ + +State Machine - |de0_nano_system|system:inst_cpu|system_sdram:sdram|m_next +Name m_next.010000000 m_next.000010000 m_next.000001000 m_next.000000001 +m_next.000000001 0 0 0 0 +m_next.000001000 0 0 1 1 +m_next.000010000 0 1 0 1 +m_next.010000000 1 0 0 1 + +State Machine - |de0_nano_system|system:inst_cpu|system_sdram:sdram|m_state +Name m_state.100000000 m_state.010000000 m_state.001000000 m_state.000100000 m_state.000010000 m_state.000001000 m_state.000000100 m_state.000000010 m_state.000000001 +m_state.000000001 0 0 0 0 0 0 0 0 0 +m_state.000000010 0 0 0 0 0 0 0 1 1 +m_state.000000100 0 0 0 0 0 0 1 0 1 +m_state.000001000 0 0 0 0 0 1 0 0 1 +m_state.000010000 0 0 0 0 1 0 0 0 1 +m_state.000100000 0 0 0 1 0 0 0 0 1 +m_state.001000000 0 0 1 0 0 0 0 0 1 +m_state.010000000 0 1 0 0 0 0 0 0 1 +m_state.100000000 1 0 0 0 0 0 0 0 1 + +State Machine - |de0_nano_system|system:inst_cpu|system_sdram:sdram|i_next +Name i_next.111 i_next.101 i_next.010 i_next.000 +i_next.000 0 0 0 0 +i_next.010 0 0 1 1 +i_next.101 0 1 0 1 +i_next.111 1 0 0 1 + +State Machine - |de0_nano_system|system:inst_cpu|system_sdram:sdram|i_state +Name i_state.111 i_state.101 i_state.011 i_state.010 i_state.001 i_state.000 +i_state.000 0 0 0 0 0 0 +i_state.001 0 0 0 0 1 1 +i_state.010 0 0 0 1 0 1 +i_state.011 0 0 1 0 0 1 +i_state.101 0 1 0 0 0 1 +i_state.111 1 0 0 0 0 1 + +State Machine - |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|DRsize +Name DRsize.101 DRsize.100 DRsize.011 DRsize.010 DRsize.001 DRsize.000 +DRsize.000 0 0 0 0 0 0 +DRsize.001 0 0 0 0 1 1 +DRsize.010 0 0 0 1 0 1 +DRsize.011 0 0 1 0 0 1 +DRsize.100 0 1 0 0 0 1 +DRsize.101 1 0 0 0 0 1 diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.sta.qmsg b/MCTEST/DE0-nano-HD/db/de0_nano_system.sta.qmsg new file mode 100644 index 00000000..e1b9b564 --- /dev/null +++ b/MCTEST/DE0-nano-HD/db/de0_nano_system.sta.qmsg @@ -0,0 +1,45 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1 1394837377067 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Full Version " "Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1 1394837377067 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Mar 14 16:49:36 2014 " "Processing started: Fri Mar 14 16:49:36 2014" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1 1394837377067 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1 1394837377067 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta de0_nano_system -c de0_nano_system " "Command: quartus_sta de0_nano_system -c de0_nano_system" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1 1394837377068 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "" 0 0 1394837377126 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." { } { } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "" 0 -1 1394837377441 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "" 0 -1 1394837377442 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "" 0 -1 1394837377493 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "" 0 -1 1394837377493 ""} +{ "Info" "ISTA_SDC_STATEMENT_PARENT" "" "Evaluating HDL-embedded SDC commands" { { "Info" "ISTA_SDC_STATEMENT_ENTITY" "alt_jtag_atlantic " "Entity alt_jtag_atlantic" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate1*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate1*\}\] " { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394837378160 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394837378160 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394837378160 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394837378160 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394837378160 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394837378160 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394837378160 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394837378160 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394837378160 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|read1*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|read1*\}\] " { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394837378160 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read_req\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read_req\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394837378160 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394837378160 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|tck_t_dav\}\] " "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|tck_t_dav\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394837378160 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|user_saw_rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid0*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|user_saw_rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid0*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394837378160 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394837378160 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394837378160 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394837378160 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394837378160 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394837378160 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394837378160 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394837378160 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394837378160 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write1*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write1*\}\] " { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394837378160 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_ena*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_ena*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394837378160 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_pause*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_pause*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394837378160 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_valid\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_valid\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394837378160 ""} } { } 0 332165 "Entity %1!s!" 0 0 "" 0 -1 1394837378160 ""} { "Info" "ISTA_SDC_STATEMENT_ENTITY" "altera_std_synchronizer " "Entity altera_std_synchronizer" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -to \[get_keepers \{*altera_std_synchronizer:*\|din_s1\}\] " "set_false_path -to \[get_keepers \{*altera_std_synchronizer:*\|din_s1\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394837378160 ""} } { } 0 332165 "Entity %1!s!" 0 0 "" 0 -1 1394837378160 ""} { "Info" "ISTA_SDC_STATEMENT_ENTITY" "sld_jtag_hub " "Entity sld_jtag_hub" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "create_clock -period 10MHz -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] " "create_clock -period 10MHz -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394837378160 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_clock_groups -asynchronous -group \{altera_reserved_tck\} " "set_clock_groups -asynchronous -group \{altera_reserved_tck\}" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394837378160 ""} } { } 0 332165 "Entity %1!s!" 0 0 "" 0 -1 1394837378160 ""} } { } 0 332164 "Evaluating HDL-embedded SDC commands" 0 0 "" 0 -1 1394837378160 ""} +{ "Info" "ISTA_SDC_FOUND" "de0_nano_system.sdc " "Reading SDC File: 'de0_nano_system.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "" 0 -1 1394837378203 ""} +{ "Warning" "WSTA_OVERWRITING_EXISTING_CLOCK" "altera_reserved_tck " "Overwriting existing clock: altera_reserved_tck" { } { } 0 332043 "Overwriting existing clock: %1!s!" 0 0 "" 0 -1 1394837378204 ""} +{ "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "Deriving PLL clocks " "Deriving PLL clocks" { { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -duty_cycle 50.00 -name \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} " "create_generated_clock -source \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -duty_cycle 50.00 -name \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}" { } { } 0 332110 "%1!s!" 0 0 "" 0 -1 1394837378205 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -phase -54.00 -duty_cycle 50.00 -name \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} " "create_generated_clock -source \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -phase -54.00 -duty_cycle 50.00 -name \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}" { } { } 0 332110 "%1!s!" 0 0 "" 0 -1 1394837378205 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 5 -duty_cycle 50.00 -name \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} " "create_generated_clock -source \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 5 -duty_cycle 50.00 -name \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\]\}" { } { } 0 332110 "%1!s!" 0 0 "" 0 -1 1394837378205 ""} } { } 0 332110 "%1!s!" 0 0 "" 0 -1 1394837378205 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_CALL_IS_DELAYED" "" "Clock uncertainty is not calculated until you update the timing netlist." { } { } 0 332151 "Clock uncertainty is not calculated until you update the timing netlist." 0 0 "" 0 -1 1394837378206 ""} +{ "Info" "ISTA_SDC_FOUND" "system/synthesis/submodules/altera_reset_controller.sdc " "Reading SDC File: 'system/synthesis/submodules/altera_reset_controller.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "" 0 -1 1394837378210 ""} +{ "Info" "ISTA_SDC_FOUND" "system/synthesis/submodules/system_cpu.sdc " "Reading SDC File: 'system/synthesis/submodules/system_cpu.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "" 0 -1 1394837378231 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "" 0 -1 1394837378443 ""} +{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "" 0 0 1394837378445 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "" 0 0 1394837378461 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup 2.020 " "Worst-case setup slack is 2.020" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394837378520 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394837378520 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 2.020 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 2.020 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394837378520 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 97.388 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 97.388 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394837378520 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1394837378520 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.228 " "Worst-case hold slack is 0.228" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394837378543 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394837378543 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.228 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.228 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394837378543 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.361 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 0.361 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394837378543 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1394837378543 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 1.948 " "Worst-case recovery slack is 1.948" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394837378556 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394837378556 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.948 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 1.948 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394837378556 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1394837378556 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "removal 2.209 " "Worst-case removal slack is 2.209" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394837378567 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394837378567 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 2.209 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 2.209 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394837378567 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1394837378567 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 4.693 " "Worst-case minimum pulse width slack is 4.693" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394837378573 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394837378573 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.693 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 4.693 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394837378573 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 9.835 0.000 CLOCK_50 " " 9.835 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394837378573 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 49.624 0.000 altera_reserved_tck " " 49.624 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394837378573 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 49.747 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 49.747 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394837378573 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1394837378573 ""} +{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 5 synchronizer chains. " "Report Metastability: Found 5 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n " "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1394837378852 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 5 " "Number of Synchronizer Chains Found: 5" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1394837378852 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1394837378852 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 0.400 " "Fraction of Chains for which MTBFs Could Not be Calculated: 0.400" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1394837378852 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 16.908 ns " "Worst Case Available Settling Time: 16.908 ns" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1394837378852 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1394837378852 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. " "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions." { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1394837378852 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8 " " - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1394837378852 ""} } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1394837378852 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "" 0 0 1394837379213 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "" 0 -1 1394837379248 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "" 0 -1 1394837380034 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "" 0 -1 1394837380366 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup 2.319 " "Worst-case setup slack is 2.319" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394837380434 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394837380434 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 2.319 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 2.319 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394837380434 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 97.707 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 97.707 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394837380434 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1394837380434 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.224 " "Worst-case hold slack is 0.224" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394837380457 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394837380457 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.224 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.224 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394837380457 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.320 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 0.320 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394837380457 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1394837380457 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 2.259 " "Worst-case recovery slack is 2.259" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394837380470 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394837380470 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 2.259 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 2.259 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394837380470 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1394837380470 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "removal 1.967 " "Worst-case removal slack is 1.967" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394837380483 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394837380483 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.967 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 1.967 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394837380483 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1394837380483 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 4.718 " "Worst-case minimum pulse width slack is 4.718" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394837380492 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394837380492 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.718 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 4.718 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394837380492 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 9.818 0.000 CLOCK_50 " " 9.818 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394837380492 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 49.601 0.000 altera_reserved_tck " " 49.601 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394837380492 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 49.744 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 49.744 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394837380492 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1394837380492 ""} +{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 5 synchronizer chains. " "Report Metastability: Found 5 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n " "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1394837381002 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 5 " "Number of Synchronizer Chains Found: 5" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1394837381002 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1394837381002 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 0.400 " "Fraction of Chains for which MTBFs Could Not be Calculated: 0.400" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1394837381002 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 17.219 ns " "Worst Case Available Settling Time: 17.219 ns" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1394837381002 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1394837381002 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. " "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions." { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1394837381002 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8 " " - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1394837381002 ""} } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1394837381002 ""} +{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "" 0 0 1394837381013 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "" 0 -1 1394837381397 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup 3.265 " "Worst-case setup slack is 3.265" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394837381425 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394837381425 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 3.265 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 3.265 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394837381425 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 98.512 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 98.512 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394837381425 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1394837381425 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.099 " "Worst-case hold slack is 0.099" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394837381451 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394837381451 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.099 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.099 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394837381451 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.193 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 0.193 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394837381451 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1394837381451 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 3.217 " "Worst-case recovery slack is 3.217" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394837381476 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394837381476 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 3.217 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 3.217 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394837381476 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1394837381476 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "removal 1.268 " "Worst-case removal slack is 1.268" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394837381492 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394837381492 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.268 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 1.268 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394837381492 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1394837381492 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 4.749 " "Worst-case minimum pulse width slack is 4.749" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394837381503 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394837381503 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.749 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 4.749 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394837381503 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 9.587 0.000 CLOCK_50 " " 9.587 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394837381503 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 49.482 0.000 altera_reserved_tck " " 49.482 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394837381503 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 49.782 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 49.782 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394837381503 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1394837381503 ""} +{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 5 synchronizer chains. " "Report Metastability: Found 5 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n " "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1394837381810 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 5 " "Number of Synchronizer Chains Found: 5" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1394837381810 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1394837381810 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 0.400 " "Fraction of Chains for which MTBFs Could Not be Calculated: 0.400" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1394837381810 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 18.290 ns " "Worst Case Available Settling Time: 18.290 ns" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1394837381810 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1394837381810 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. " "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions." { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1394837381810 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8 " " - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1394837381810 ""} } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1394837381810 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "" 0 -1 1394837382352 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "" 0 -1 1394837382353 ""} +{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 1 Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "567 " "Peak virtual memory: 567 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1 1394837382684 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Mar 14 16:49:42 2014 " "Processing ended: Fri Mar 14 16:49:42 2014" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1 1394837382684 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1 1394837382684 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1 1394837382684 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1 1394837382684 ""} diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.sta.rdb b/MCTEST/DE0-nano-HD/db/de0_nano_system.sta.rdb new file mode 100644 index 00000000..242ee390 Binary files /dev/null and b/MCTEST/DE0-nano-HD/db/de0_nano_system.sta.rdb differ diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.sta_cmp.6_slow_1200mv_85c.tdb b/MCTEST/DE0-nano-HD/db/de0_nano_system.sta_cmp.6_slow_1200mv_85c.tdb new file mode 100644 index 00000000..ef42d06a Binary files /dev/null and b/MCTEST/DE0-nano-HD/db/de0_nano_system.sta_cmp.6_slow_1200mv_85c.tdb differ diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.syn_hier_info b/MCTEST/DE0-nano-HD/db/de0_nano_system.syn_hier_info new file mode 100644 index 00000000..e69de29b diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.tis_db_list.ddb b/MCTEST/DE0-nano-HD/db/de0_nano_system.tis_db_list.ddb new file mode 100644 index 00000000..884371a6 Binary files /dev/null and b/MCTEST/DE0-nano-HD/db/de0_nano_system.tis_db_list.ddb differ diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.tiscmp.fast_1200mv_0c.ddb b/MCTEST/DE0-nano-HD/db/de0_nano_system.tiscmp.fast_1200mv_0c.ddb new file mode 100644 index 00000000..4efe2add Binary files /dev/null and b/MCTEST/DE0-nano-HD/db/de0_nano_system.tiscmp.fast_1200mv_0c.ddb differ diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.tiscmp.slow_1200mv_0c.ddb b/MCTEST/DE0-nano-HD/db/de0_nano_system.tiscmp.slow_1200mv_0c.ddb new file mode 100644 index 00000000..3c9464e1 Binary files /dev/null and b/MCTEST/DE0-nano-HD/db/de0_nano_system.tiscmp.slow_1200mv_0c.ddb differ diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.tiscmp.slow_1200mv_85c.ddb b/MCTEST/DE0-nano-HD/db/de0_nano_system.tiscmp.slow_1200mv_85c.ddb new file mode 100644 index 00000000..bcc58c6f Binary files /dev/null and b/MCTEST/DE0-nano-HD/db/de0_nano_system.tiscmp.slow_1200mv_85c.ddb differ diff --git a/MCTEST/DE0-nano-HD/db/de0_nano_system.vpr.ammdb b/MCTEST/DE0-nano-HD/db/de0_nano_system.vpr.ammdb new file mode 100644 index 00000000..0b23521e Binary files /dev/null and b/MCTEST/DE0-nano-HD/db/de0_nano_system.vpr.ammdb differ diff --git a/MCTEST/DE0-nano-HD/db/ded_mult_ks81.tdf b/MCTEST/DE0-nano-HD/db/ded_mult_ks81.tdf new file mode 100644 index 00000000..d53ec158 --- /dev/null +++ b/MCTEST/DE0-nano-HD/db/ded_mult_ks81.tdf @@ -0,0 +1,75 @@ +--alt_ded_mult_y CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" dedicated_multiplier_circuitry="YES" device_family="Cyclone IV E" dsp_block_balancing="Auto" extra_latency=0 input_reg_a="UNREGISTERED" input_reg_b="UNREGISTERED" output_aclr="ACLR0" output_reg="CLOCK0" pipeline_reg="UNREGISTERED" representation_a="UNSIGNED" representation_b="UNSIGNED" sub_dedicated_multiplier_circuitry="YES" width_a=16 width_b=16 aclr clock dataa datab ena result +--VERSION_BEGIN 12.1SP1 cbx_alt_ded_mult_y 2013:01:31:18:05:07:SJ cbx_cycloneii 2013:01:31:18:05:07:SJ cbx_lpm_add_sub 2013:01:31:18:05:07:SJ cbx_mgl 2013:01:31:18:08:27:SJ cbx_padd 2013:01:31:18:05:07:SJ cbx_parallel_add 2013:01:31:18:05:07:SJ cbx_stratix 2013:01:31:18:05:07:SJ cbx_stratixii 2013:01:31:18:05:07:SJ cbx_util_mgl 2013:01:31:18:05:07:SJ VERSION_END + + +-- Copyright (C) 1991-2012 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +FUNCTION cycloneive_mac_mult (aclr, clk, dataa[dataa_width-1..0], datab[datab_width-1..0], ena, signa, signb) +WITH ( dataa_clock, dataa_width, datab_clock, datab_width, signa_clock, signb_clock) +RETURNS ( dataout[dataa_width+datab_width-1..0]); +FUNCTION cycloneive_mac_out (aclr, clk, dataa[dataa_width-1..0], ena) +WITH ( dataa_width = 0, output_clock) +RETURNS ( dataout[dataa_width-1..0]); +FUNCTION dffpipe_93c (d[31..0]) +RETURNS ( q[31..0]); + +--synthesis_resources = dsp_9bit 2 +SUBDESIGN ded_mult_ks81 +( + aclr[3..0] : input; + clock[3..0] : input; + dataa[15..0] : input; + datab[15..0] : input; + ena[3..0] : input; + result[31..0] : output; +) +VARIABLE + mac_mult2 : cycloneive_mac_mult + WITH ( + dataa_width = 16, + datab_width = 16 + ); + mac_out3 : cycloneive_mac_out + WITH ( + dataa_width = 32, + output_clock = "0" + ); + pre_result : dffpipe_93c; + x_dataa[15..0] : WIRE; + x_datab[15..0] : WIRE; + x_signa[0..0] : WIRE; + x_signb[0..0] : WIRE; + +BEGIN + mac_mult2.aclr = aclr[0..0]; + mac_mult2.clk = clock[0..0]; + mac_mult2.dataa[] = ( x_dataa[]); + mac_mult2.datab[] = ( x_datab[]); + mac_mult2.ena = ena[0..0]; + mac_mult2.signa = x_signa[]; + mac_mult2.signb = x_signb[]; + mac_out3.aclr = aclr[0..0]; + mac_out3.clk = clock[0..0]; + mac_out3.dataa[] = ( mac_mult2.dataout[31..0]); + mac_out3.ena = ena[0..0]; + pre_result.d[31..0] = mac_out3.dataout[31..0]; + result[] = pre_result.q[]; + x_dataa[] = dataa[]; + x_datab[] = datab[]; + x_signa[] = B"0"; + x_signb[] = B"0"; +END; +--VALID FILE diff --git a/MCTEST/DE0-nano-HD/db/dffpipe_93c.tdf b/MCTEST/DE0-nano-HD/db/dffpipe_93c.tdf new file mode 100644 index 00000000..bd86db1c --- /dev/null +++ b/MCTEST/DE0-nano-HD/db/dffpipe_93c.tdf @@ -0,0 +1,33 @@ +--dffpipe CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DELAY=0 WIDTH=32 d q ALTERA_INTERNAL_OPTIONS=AUTO_SHIFT_REGISTER_RECOGNITION=OFF +--VERSION_BEGIN 12.1SP1 cbx_mgl 2013:01:31:18:08:27:SJ cbx_stratixii 2013:01:31:18:05:07:SJ cbx_util_mgl 2013:01:31:18:05:07:SJ VERSION_END + + +-- Copyright (C) 1991-2012 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + + +--synthesis_resources = +OPTIONS ALTERA_INTERNAL_OPTION = "AUTO_SHIFT_REGISTER_RECOGNITION=OFF"; + +SUBDESIGN dffpipe_93c +( + d[31..0] : input; + q[31..0] : output; +) + +BEGIN + q[] = d[]; +END; +--VALID FILE diff --git a/MCTEST/DE0-nano-HD/db/dpram_nl21.tdf b/MCTEST/DE0-nano-HD/db/dpram_nl21.tdf new file mode 100644 index 00000000..e3b7f74a --- /dev/null +++ b/MCTEST/DE0-nano-HD/db/dpram_nl21.tdf @@ -0,0 +1,48 @@ +--altdpram DEVICE_FAMILY="Cyclone IV E" lpm_hint="RAM_BLOCK_TYPE=AUTO" RAM_BLOCK_TYPE="AUTO" RDCONTROL_ACLR="OFF" RDCONTROL_REG="UNREGISTERED" SUPPRESS_MEMORY_CONVERSION_WARNINGS="ON" USE_EAB="ON" WIDTH=8 WIDTHAD=6 data inclock outclock outclocken q rdaddress wraddress wren CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 CYCLONEII_M4K_COMPATIBILITY="ON" LOW_POWER_MODE="AUTO" +--VERSION_BEGIN 12.1SP1 cbx_altdpram 2013:01:31:18:05:07:SJ cbx_altsyncram 2013:01:31:18:05:07:SJ cbx_cycloneii 2013:01:31:18:05:07:SJ cbx_lpm_add_sub 2013:01:31:18:05:07:SJ cbx_lpm_compare 2013:01:31:18:05:07:SJ cbx_lpm_decode 2013:01:31:18:05:07:SJ cbx_lpm_mux 2013:01:31:18:05:07:SJ cbx_mgl 2013:01:31:18:08:27:SJ cbx_stratix 2013:01:31:18:05:07:SJ cbx_stratixii 2013:01:31:18:05:07:SJ cbx_stratixiii 2013:01:31:18:05:07:SJ cbx_stratixv 2013:01:31:18:05:07:SJ cbx_util_mgl 2013:01:31:18:05:07:SJ VERSION_END + + +-- Copyright (C) 1991-2012 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +FUNCTION altsyncram_r1m1 (address_a[5..0], address_b[5..0], clock0, clock1, clocken1, data_a[7..0], wren_a) +RETURNS ( q_b[7..0]); + +--synthesis_resources = M9K 1 +SUBDESIGN dpram_nl21 +( + data[7..0] : input; + inclock : input; + outclock : input; + outclocken : input; + q[7..0] : output; + rdaddress[5..0] : input; + wraddress[5..0] : input; + wren : input; +) +VARIABLE + altsyncram1 : altsyncram_r1m1; + +BEGIN + altsyncram1.address_a[] = wraddress[]; + altsyncram1.address_b[] = rdaddress[]; + altsyncram1.clock0 = inclock; + altsyncram1.clock1 = outclock; + altsyncram1.clocken1 = outclocken; + altsyncram1.data_a[] = data[]; + altsyncram1.wren_a = wren; + q[] = altsyncram1.q_b[]; +END; +--VALID FILE diff --git a/MCTEST/DE0-nano-HD/db/logic_util_heursitic.dat b/MCTEST/DE0-nano-HD/db/logic_util_heursitic.dat new file mode 100644 index 00000000..4ce68bd9 Binary files /dev/null and b/MCTEST/DE0-nano-HD/db/logic_util_heursitic.dat differ diff --git a/MCTEST/DE0-nano-HD/db/mult_add_75u2.tdf b/MCTEST/DE0-nano-HD/db/mult_add_75u2.tdf new file mode 100644 index 00000000..24861cf5 --- /dev/null +++ b/MCTEST/DE0-nano-HD/db/mult_add_75u2.tdf @@ -0,0 +1,51 @@ +--altmult_add ADDNSUB_MULTIPLIER_PIPELINE_ACLR1="ACLR0" ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1="CLOCK0" ADDNSUB_MULTIPLIER_REGISTER1="UNREGISTERED" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEDICATED_MULTIPLIER_CIRCUITRY="YES" DEVICE_FAMILY="Cyclone IV E" DSP_BLOCK_BALANCING="Auto" INPUT_REGISTER_A0="UNREGISTERED" INPUT_REGISTER_B0="UNREGISTERED" INPUT_SOURCE_A0="DATAA" INPUT_SOURCE_B0="DATAB" MULTIPLIER1_DIRECTION="ADD" MULTIPLIER_ACLR0="ACLR0" MULTIPLIER_REGISTER0="CLOCK0" NUMBER_OF_MULTIPLIERS=1 OUTPUT_REGISTER="UNREGISTERED" port_addnsub1="PORT_UNUSED" port_addnsub3="PORT_UNUSED" port_signa="PORT_UNUSED" port_signb="PORT_UNUSED" REPRESENTATION_A="UNSIGNED" REPRESENTATION_B="UNSIGNED" SIGNED_PIPELINE_ACLR_A="ACLR0" SIGNED_PIPELINE_ACLR_B="ACLR0" SIGNED_PIPELINE_REGISTER_A="CLOCK0" SIGNED_PIPELINE_REGISTER_B="CLOCK0" SIGNED_REGISTER_A="UNREGISTERED" SIGNED_REGISTER_B="UNREGISTERED" WIDTH_A=16 WIDTH_B=16 WIDTH_RESULT=32 aclr0 clock0 dataa datab result CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 +--VERSION_BEGIN 12.1SP1 cbx_alt_ded_mult_y 2013:01:31:18:05:07:SJ cbx_altera_mult_add 2013:01:31:18:05:07:SJ cbx_altmult_add 2013:01:31:18:05:07:SJ cbx_cycloneii 2013:01:31:18:05:07:SJ cbx_lpm_add_sub 2013:01:31:18:05:07:SJ cbx_lpm_mult 2013:01:31:18:05:07:SJ cbx_mgl 2013:01:31:18:08:27:SJ cbx_padd 2013:01:31:18:05:07:SJ cbx_parallel_add 2013:01:31:18:05:07:SJ cbx_stratix 2013:01:31:18:05:07:SJ cbx_stratixii 2013:01:31:18:05:07:SJ cbx_util_mgl 2013:01:31:18:05:07:SJ VERSION_END + + +-- Copyright (C) 1991-2012 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +FUNCTION ded_mult_ks81 (aclr[3..0], clock[3..0], dataa[15..0], datab[15..0], ena[3..0]) +RETURNS ( result[31..0]); + +--synthesis_resources = dsp_9bit 2 +SUBDESIGN mult_add_75u2 +( + aclr0 : input; + clock0 : input; + dataa[15..0] : input; + datab[15..0] : input; + result[31..0] : output; +) +VARIABLE + ded_mult1 : ded_mult_ks81; + dataa_bus[15..0] : WIRE; + datab_bus[15..0] : WIRE; + ena0 : NODE; + pre_result[31..0] : WIRE; + +BEGIN + ded_mult1.aclr[] = ( B"000", aclr0); + ded_mult1.clock[] = ( B"111", clock0); + ded_mult1.dataa[] = ( dataa_bus[15..0]); + ded_mult1.datab[] = ( datab_bus[15..0]); + ded_mult1.ena[] = ( B"111", ena0); + dataa_bus[] = ( dataa[15..0]); + datab_bus[] = ( datab[15..0]); + ena0 = VCC; + pre_result[31..0] = ded_mult1.result[31..0]; + result[31..0] = pre_result[31..0]; +END; +--VALID FILE diff --git a/MCTEST/DE0-nano-HD/db/mult_add_95u2.tdf b/MCTEST/DE0-nano-HD/db/mult_add_95u2.tdf new file mode 100644 index 00000000..2f75903c --- /dev/null +++ b/MCTEST/DE0-nano-HD/db/mult_add_95u2.tdf @@ -0,0 +1,51 @@ +--altmult_add ADDNSUB_MULTIPLIER_PIPELINE_ACLR1="ACLR0" ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1="CLOCK0" ADDNSUB_MULTIPLIER_REGISTER1="UNREGISTERED" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEDICATED_MULTIPLIER_CIRCUITRY="YES" DEVICE_FAMILY="Cyclone IV E" DSP_BLOCK_BALANCING="Auto" INPUT_REGISTER_A0="UNREGISTERED" INPUT_REGISTER_B0="UNREGISTERED" INPUT_SOURCE_A0="DATAA" INPUT_SOURCE_B0="DATAB" MULTIPLIER1_DIRECTION="ADD" MULTIPLIER_ACLR0="ACLR0" MULTIPLIER_REGISTER0="CLOCK0" NUMBER_OF_MULTIPLIERS=1 OUTPUT_REGISTER="UNREGISTERED" port_addnsub1="PORT_UNUSED" port_addnsub3="PORT_UNUSED" port_signa="PORT_UNUSED" port_signb="PORT_UNUSED" REPRESENTATION_A="UNSIGNED" REPRESENTATION_B="UNSIGNED" SIGNED_PIPELINE_ACLR_A="ACLR0" SIGNED_PIPELINE_ACLR_B="ACLR0" SIGNED_PIPELINE_REGISTER_A="CLOCK0" SIGNED_PIPELINE_REGISTER_B="CLOCK0" SIGNED_REGISTER_A="UNREGISTERED" SIGNED_REGISTER_B="UNREGISTERED" WIDTH_A=16 WIDTH_B=16 WIDTH_RESULT=16 aclr0 clock0 dataa datab result CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 +--VERSION_BEGIN 12.1SP1 cbx_alt_ded_mult_y 2013:01:31:18:05:07:SJ cbx_altera_mult_add 2013:01:31:18:05:07:SJ cbx_altmult_add 2013:01:31:18:05:07:SJ cbx_cycloneii 2013:01:31:18:05:07:SJ cbx_lpm_add_sub 2013:01:31:18:05:07:SJ cbx_lpm_mult 2013:01:31:18:05:07:SJ cbx_mgl 2013:01:31:18:08:27:SJ cbx_padd 2013:01:31:18:05:07:SJ cbx_parallel_add 2013:01:31:18:05:07:SJ cbx_stratix 2013:01:31:18:05:07:SJ cbx_stratixii 2013:01:31:18:05:07:SJ cbx_util_mgl 2013:01:31:18:05:07:SJ VERSION_END + + +-- Copyright (C) 1991-2012 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +FUNCTION ded_mult_ks81 (aclr[3..0], clock[3..0], dataa[15..0], datab[15..0], ena[3..0]) +RETURNS ( result[31..0]); + +--synthesis_resources = +SUBDESIGN mult_add_95u2 +( + aclr0 : input; + clock0 : input; + dataa[15..0] : input; + datab[15..0] : input; + result[15..0] : output; +) +VARIABLE + ded_mult1 : ded_mult_ks81; + dataa_bus[15..0] : WIRE; + datab_bus[15..0] : WIRE; + ena0 : NODE; + pre_result[31..0] : WIRE; + +BEGIN + ded_mult1.aclr[] = ( B"000", aclr0); + ded_mult1.clock[] = ( B"111", clock0); + ded_mult1.dataa[] = ( dataa_bus[15..0]); + ded_mult1.datab[] = ( datab_bus[15..0]); + ded_mult1.ena[] = ( B"111", ena0); + dataa_bus[] = ( dataa[15..0]); + datab_bus[] = ( datab[15..0]); + ena0 = VCC; + pre_result[31..0] = ded_mult1.result[31..0]; + result[15..0] = pre_result[15..0]; +END; +--VALID FILE diff --git a/MCTEST/DE0-nano-HD/db/pll_sys_altpll.v b/MCTEST/DE0-nano-HD/db/pll_sys_altpll.v new file mode 100644 index 00000000..5e0d28b5 --- /dev/null +++ b/MCTEST/DE0-nano-HD/db/pll_sys_altpll.v @@ -0,0 +1,105 @@ +//altpll bandwidth_type="AUTO" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" clk0_divide_by=1 clk0_duty_cycle=50 clk0_multiply_by=2 clk0_phase_shift="0" clk1_divide_by=1 clk1_duty_cycle=50 clk1_multiply_by=2 clk1_phase_shift="-1500" clk2_divide_by=5 clk2_duty_cycle=50 clk2_multiply_by=1 clk2_phase_shift="0" compensate_clock="CLK0" device_family="Cyclone IV E" inclk0_input_frequency=20000 intended_device_family="Cyclone IV E" lpm_hint="CBX_MODULE_PREFIX=pll_sys" operation_mode="normal" pll_type="AUTO" port_clk0="PORT_USED" port_clk1="PORT_USED" port_clk2="PORT_USED" port_clk3="PORT_UNUSED" port_clk4="PORT_UNUSED" port_clk5="PORT_UNUSED" port_extclk0="PORT_UNUSED" port_extclk1="PORT_UNUSED" port_extclk2="PORT_UNUSED" port_extclk3="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" self_reset_on_loss_lock="ON" width_clock=5 clk inclk locked CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 +//VERSION_BEGIN 12.1SP1 cbx_altclkbuf 2013:01:31:18:05:07:SJ cbx_altiobuf_bidir 2013:01:31:18:05:07:SJ cbx_altiobuf_in 2013:01:31:18:05:07:SJ cbx_altiobuf_out 2013:01:31:18:05:07:SJ cbx_altpll 2013:01:31:18:05:07:SJ cbx_cycloneii 2013:01:31:18:05:07:SJ cbx_lpm_add_sub 2013:01:31:18:05:07:SJ cbx_lpm_compare 2013:01:31:18:05:07:SJ cbx_lpm_counter 2013:01:31:18:05:07:SJ cbx_lpm_decode 2013:01:31:18:05:07:SJ cbx_lpm_mux 2013:01:31:18:05:07:SJ cbx_mgl 2013:01:31:18:08:27:SJ cbx_stratix 2013:01:31:18:05:07:SJ cbx_stratixii 2013:01:31:18:05:07:SJ cbx_stratixiii 2013:01:31:18:05:07:SJ cbx_stratixv 2013:01:31:18:05:07:SJ cbx_util_mgl 2013:01:31:18:05:07:SJ VERSION_END +//CBXI_INSTANCE_NAME="de0_nano_system_pll_sys_inst_pll_sys_altpll_altpll_component" +// synthesis VERILOG_INPUT_VERSION VERILOG_2001 +// altera message_off 10463 + + + +// Copyright (C) 1991-2012 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + + + +//synthesis_resources = cycloneive_pll 1 +//synopsys translate_off +`timescale 1 ps / 1 ps +//synopsys translate_on +module pll_sys_altpll + ( + clk, + inclk, + locked) /* synthesis synthesis_clearbox=1 */; + output [4:0] clk; + input [1:0] inclk; + output locked; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri0 [1:0] inclk; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [4:0] wire_pll1_clk; + wire wire_pll1_fbout; + wire wire_pll1_locked; + + cycloneive_pll pll1 + ( + .activeclock(), + .clk(wire_pll1_clk), + .clkbad(), + .fbin(wire_pll1_fbout), + .fbout(wire_pll1_fbout), + .inclk(inclk), + .locked(wire_pll1_locked), + .phasedone(), + .scandataout(), + .scandone(), + .vcooverrange(), + .vcounderrange() + `ifndef FORMAL_VERIFICATION + // synopsys translate_off + `endif + , + .areset(1'b0), + .clkswitch(1'b0), + .configupdate(1'b0), + .pfdena(1'b1), + .phasecounterselect({3{1'b0}}), + .phasestep(1'b0), + .phaseupdown(1'b0), + .scanclk(1'b0), + .scanclkena(1'b1), + .scandata(1'b0) + `ifndef FORMAL_VERIFICATION + // synopsys translate_on + `endif + ); + defparam + pll1.bandwidth_type = "auto", + pll1.clk0_divide_by = 1, + pll1.clk0_duty_cycle = 50, + pll1.clk0_multiply_by = 2, + pll1.clk0_phase_shift = "0", + pll1.clk1_divide_by = 1, + pll1.clk1_duty_cycle = 50, + pll1.clk1_multiply_by = 2, + pll1.clk1_phase_shift = "-1500", + pll1.clk2_divide_by = 5, + pll1.clk2_duty_cycle = 50, + pll1.clk2_multiply_by = 1, + pll1.clk2_phase_shift = "0", + pll1.compensate_clock = "clk0", + pll1.inclk0_input_frequency = 20000, + pll1.operation_mode = "normal", + pll1.pll_type = "auto", + pll1.self_reset_on_loss_lock = "on", + pll1.lpm_type = "cycloneive_pll"; + assign + clk = {wire_pll1_clk[4:0]}, + locked = wire_pll1_locked; +endmodule //pll_sys_altpll +//VALID FILE diff --git a/MCTEST/DE0-nano-HD/db/prev_cmp_de0_nano_system.qmsg b/MCTEST/DE0-nano-HD/db/prev_cmp_de0_nano_system.qmsg new file mode 100644 index 00000000..afa07b9d --- /dev/null +++ b/MCTEST/DE0-nano-HD/db/prev_cmp_de0_nano_system.qmsg @@ -0,0 +1,428 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1 1394821247059 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Full Version " "Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1 1394821247059 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Mar 14 12:20:46 2014 " "Processing started: Fri Mar 14 12:20:46 2014" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1 1394821247059 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1 1394821247059 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off de0_nano_system -c de0_nano_system " "Command: quartus_map --read_settings_files=on --write_settings_files=off de0_nano_system -c de0_nano_system" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1 1394821247059 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." { } { } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "" 0 -1 1394821247465 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "de0_nano_system.vhd 2 1 " "Found 2 design units, including 1 entities, in source file de0_nano_system.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 de0_nano_system-syn " "Found design unit 1: de0_nano_system-syn" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 86 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1 1394821248448 ""} { "Info" "ISGN_ENTITY_NAME" "1 de0_nano_system " "Found entity 1: de0_nano_system" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 55 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821248448 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394821248448 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "heartbeat.vhd 2 1 " "Found 2 design units, including 1 entities, in source file heartbeat.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 heartbeat-syn " "Found design unit 1: heartbeat-syn" { } { { "heartbeat.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/heartbeat.vhd" 61 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1 1394821248448 ""} { "Info" "ISGN_ENTITY_NAME" "1 heartbeat " "Found entity 1: heartbeat" { } { { "heartbeat.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/heartbeat.vhd" 49 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821248448 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394821248448 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/system.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/system.v" { { "Info" "ISGN_ENTITY_NAME" "1 system " "Found entity 1: system" { } { { "system/synthesis/system.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 6 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821248463 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394821248463 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_irq_mapper.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_irq_mapper.sv" { { "Info" "ISGN_ENTITY_NAME" "1 system_irq_mapper " "Found entity 1: system_irq_mapper" { } { { "system/synthesis/submodules/system_irq_mapper.sv" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_irq_mapper.sv" 31 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821248463 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394821248463 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_merlin_width_adapter.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_width_adapter.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_width_adapter " "Found entity 1: altera_merlin_width_adapter" { } { { "system/synthesis/submodules/altera_merlin_width_adapter.sv" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_width_adapter.sv" 25 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821248463 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394821248463 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_merlin_burst_uncompressor.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_burst_uncompressor.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_burst_uncompressor " "Found entity 1: altera_merlin_burst_uncompressor" { } { { "system/synthesis/submodules/altera_merlin_burst_uncompressor.sv" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_burst_uncompressor.sv" 40 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821248479 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394821248479 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_merlin_address_alignment.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_address_alignment.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_address_alignment " "Found entity 1: altera_merlin_address_alignment" { } { { "system/synthesis/submodules/altera_merlin_address_alignment.sv" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_address_alignment.sv" 26 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821248479 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394821248479 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_merlin_arbitrator.sv 2 2 " "Found 2 design units, including 2 entities, in source file system/synthesis/submodules/altera_merlin_arbitrator.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_arbitrator " "Found entity 1: altera_merlin_arbitrator" { } { { "system/synthesis/submodules/altera_merlin_arbitrator.sv" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_arbitrator.sv" 103 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821248479 ""} { "Info" "ISGN_ENTITY_NAME" "2 altera_merlin_arb_adder " "Found entity 2: altera_merlin_arb_adder" { } { { "system/synthesis/submodules/altera_merlin_arbitrator.sv" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_arbitrator.sv" 228 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821248479 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394821248479 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_rsp_xbar_mux_001.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_rsp_xbar_mux_001.sv" { { "Info" "ISGN_ENTITY_NAME" "1 system_rsp_xbar_mux_001 " "Found entity 1: system_rsp_xbar_mux_001" { } { { "system/synthesis/submodules/system_rsp_xbar_mux_001.sv" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_rsp_xbar_mux_001.sv" 38 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821248479 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394821248479 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_rsp_xbar_mux.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_rsp_xbar_mux.sv" { { "Info" "ISGN_ENTITY_NAME" "1 system_rsp_xbar_mux " "Found entity 1: system_rsp_xbar_mux" { } { { "system/synthesis/submodules/system_rsp_xbar_mux.sv" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_rsp_xbar_mux.sv" 38 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821248479 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394821248479 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_rsp_xbar_demux_002.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_rsp_xbar_demux_002.sv" { { "Info" "ISGN_ENTITY_NAME" "1 system_rsp_xbar_demux_002 " "Found entity 1: system_rsp_xbar_demux_002" { } { { "system/synthesis/submodules/system_rsp_xbar_demux_002.sv" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_rsp_xbar_demux_002.sv" 43 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821248494 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394821248494 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_rsp_xbar_demux.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_rsp_xbar_demux.sv" { { "Info" "ISGN_ENTITY_NAME" "1 system_rsp_xbar_demux " "Found entity 1: system_rsp_xbar_demux" { } { { "system/synthesis/submodules/system_rsp_xbar_demux.sv" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_rsp_xbar_demux.sv" 43 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821248494 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394821248494 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_cmd_xbar_mux.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_cmd_xbar_mux.sv" { { "Info" "ISGN_ENTITY_NAME" "1 system_cmd_xbar_mux " "Found entity 1: system_cmd_xbar_mux" { } { { "system/synthesis/submodules/system_cmd_xbar_mux.sv" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cmd_xbar_mux.sv" 38 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821248494 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394821248494 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_cmd_xbar_demux_001.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_cmd_xbar_demux_001.sv" { { "Info" "ISGN_ENTITY_NAME" "1 system_cmd_xbar_demux_001 " "Found entity 1: system_cmd_xbar_demux_001" { } { { "system/synthesis/submodules/system_cmd_xbar_demux_001.sv" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cmd_xbar_demux_001.sv" 43 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821248494 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394821248494 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_cmd_xbar_demux.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_cmd_xbar_demux.sv" { { "Info" "ISGN_ENTITY_NAME" "1 system_cmd_xbar_demux " "Found entity 1: system_cmd_xbar_demux" { } { { "system/synthesis/submodules/system_cmd_xbar_demux.sv" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cmd_xbar_demux.sv" 43 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821248494 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394821248494 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_reset_controller.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_reset_controller.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_reset_controller " "Found entity 1: altera_reset_controller" { } { { "system/synthesis/submodules/altera_reset_controller.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_reset_controller.v" 28 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821248494 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394821248494 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_reset_synchronizer.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_reset_synchronizer.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_reset_synchronizer " "Found entity 1: altera_reset_synchronizer" { } { { "system/synthesis/submodules/altera_reset_synchronizer.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_reset_synchronizer.v" 24 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821248494 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394821248494 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_merlin_burst_adapter.sv 7 7 " "Found 7 design units, including 7 entities, in source file system/synthesis/submodules/altera_merlin_burst_adapter.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_burst_adapter_burstwrap_increment " "Found entity 1: altera_merlin_burst_adapter_burstwrap_increment" { } { { "system/synthesis/submodules/altera_merlin_burst_adapter.sv" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_burst_adapter.sv" 40 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821248510 ""} { "Info" "ISGN_ENTITY_NAME" "2 altera_merlin_burst_adapter_adder " "Found entity 2: altera_merlin_burst_adapter_adder" { } { { "system/synthesis/submodules/altera_merlin_burst_adapter.sv" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_burst_adapter.sv" 55 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821248510 ""} { "Info" "ISGN_ENTITY_NAME" "3 altera_merlin_burst_adapter_subtractor " "Found entity 3: altera_merlin_burst_adapter_subtractor" { } { { "system/synthesis/submodules/altera_merlin_burst_adapter.sv" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_burst_adapter.sv" 77 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821248510 ""} { "Info" "ISGN_ENTITY_NAME" "4 altera_merlin_burst_adapter_min " "Found entity 4: altera_merlin_burst_adapter_min" { } { { "system/synthesis/submodules/altera_merlin_burst_adapter.sv" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_burst_adapter.sv" 98 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821248510 ""} { "Info" "ISGN_ENTITY_NAME" "5 altera_merlin_burst_adapter " "Found entity 5: altera_merlin_burst_adapter" { } { { "system/synthesis/submodules/altera_merlin_burst_adapter.sv" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_burst_adapter.sv" 264 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821248510 ""} { "Info" "ISGN_ENTITY_NAME" "6 altera_merlin_burst_adapter_uncompressed_only " "Found entity 6: altera_merlin_burst_adapter_uncompressed_only" { } { { "system/synthesis/submodules/altera_merlin_burst_adapter.sv" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_burst_adapter.sv" 414 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821248510 ""} { "Info" "ISGN_ENTITY_NAME" "7 altera_merlin_burst_adapter_full " "Found entity 7: altera_merlin_burst_adapter_full" { } { { "system/synthesis/submodules/altera_merlin_burst_adapter.sv" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_burst_adapter.sv" 468 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821248510 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394821248510 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_merlin_traffic_limiter.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_traffic_limiter.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_traffic_limiter " "Found entity 1: altera_merlin_traffic_limiter" { } { { "system/synthesis/submodules/altera_merlin_traffic_limiter.sv" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_traffic_limiter.sv" 44 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821248510 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394821248510 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_avalon_st_pipeline_base.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_avalon_st_pipeline_base.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_avalon_st_pipeline_base " "Found entity 1: altera_avalon_st_pipeline_base" { } { { "system/synthesis/submodules/altera_avalon_st_pipeline_base.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_avalon_st_pipeline_base.v" 22 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821248510 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394821248510 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_id_router_002.sv 2 2 " "Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_id_router_002.sv" { { "Info" "ISGN_ENTITY_NAME" "1 system_id_router_002_default_decode " "Found entity 1: system_id_router_002_default_decode" { } { { "system/synthesis/submodules/system_id_router_002.sv" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_id_router_002.sv" 32 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821248510 ""} { "Info" "ISGN_ENTITY_NAME" "2 system_id_router_002 " "Found entity 2: system_id_router_002" { } { { "system/synthesis/submodules/system_id_router_002.sv" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_id_router_002.sv" 54 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821248510 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394821248510 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_id_router_001.sv 2 2 " "Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_id_router_001.sv" { { "Info" "ISGN_ENTITY_NAME" "1 system_id_router_001_default_decode " "Found entity 1: system_id_router_001_default_decode" { } { { "system/synthesis/submodules/system_id_router_001.sv" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_id_router_001.sv" 32 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821248526 ""} { "Info" "ISGN_ENTITY_NAME" "2 system_id_router_001 " "Found entity 2: system_id_router_001" { } { { "system/synthesis/submodules/system_id_router_001.sv" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_id_router_001.sv" 54 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821248526 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394821248526 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_id_router.sv 2 2 " "Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_id_router.sv" { { "Info" "ISGN_ENTITY_NAME" "1 system_id_router_default_decode " "Found entity 1: system_id_router_default_decode" { } { { "system/synthesis/submodules/system_id_router.sv" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_id_router.sv" 32 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821248526 ""} { "Info" "ISGN_ENTITY_NAME" "2 system_id_router " "Found entity 2: system_id_router" { } { { "system/synthesis/submodules/system_id_router.sv" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_id_router.sv" 54 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821248526 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394821248526 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_addr_router_001.sv 2 2 " "Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_addr_router_001.sv" { { "Info" "ISGN_ENTITY_NAME" "1 system_addr_router_001_default_decode " "Found entity 1: system_addr_router_001_default_decode" { } { { "system/synthesis/submodules/system_addr_router_001.sv" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_addr_router_001.sv" 32 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821248526 ""} { "Info" "ISGN_ENTITY_NAME" "2 system_addr_router_001 " "Found entity 2: system_addr_router_001" { } { { "system/synthesis/submodules/system_addr_router_001.sv" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_addr_router_001.sv" 54 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821248526 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394821248526 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_addr_router.sv 2 2 " "Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_addr_router.sv" { { "Info" "ISGN_ENTITY_NAME" "1 system_addr_router_default_decode " "Found entity 1: system_addr_router_default_decode" { } { { "system/synthesis/submodules/system_addr_router.sv" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_addr_router.sv" 32 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821248526 ""} { "Info" "ISGN_ENTITY_NAME" "2 system_addr_router " "Found entity 2: system_addr_router" { } { { "system/synthesis/submodules/system_addr_router.sv" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_addr_router.sv" 54 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821248526 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394821248526 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_avalon_sc_fifo.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_avalon_sc_fifo.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_avalon_sc_fifo " "Found entity 1: altera_avalon_sc_fifo" { } { { "system/synthesis/submodules/altera_avalon_sc_fifo.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_avalon_sc_fifo.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821248526 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394821248526 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_merlin_slave_agent.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_slave_agent.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_slave_agent " "Found entity 1: altera_merlin_slave_agent" { } { { "system/synthesis/submodules/altera_merlin_slave_agent.sv" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_slave_agent.sv" 34 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821248526 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394821248526 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_merlin_master_agent.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_master_agent.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_master_agent " "Found entity 1: altera_merlin_master_agent" { } { { "system/synthesis/submodules/altera_merlin_master_agent.sv" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_master_agent.sv" 28 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821248541 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394821248541 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_merlin_slave_translator.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_slave_translator.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_slave_translator " "Found entity 1: altera_merlin_slave_translator" { } { { "system/synthesis/submodules/altera_merlin_slave_translator.sv" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_slave_translator.sv" 35 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821248541 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394821248541 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_merlin_master_translator.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_master_translator.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_master_translator " "Found entity 1: altera_merlin_master_translator" { } { { "system/synthesis/submodules/altera_merlin_master_translator.sv" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_master_translator.sv" 30 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821248541 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394821248541 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_up_rs232_counters.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_up_rs232_counters.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_up_rs232_counters " "Found entity 1: altera_up_rs232_counters" { } { { "system/synthesis/submodules/altera_up_rs232_counters.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_up_rs232_counters.v" 48 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821248541 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394821248541 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_up_rs232_in_deserializer.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_up_rs232_in_deserializer.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_up_rs232_in_deserializer " "Found entity 1: altera_up_rs232_in_deserializer" { } { { "system/synthesis/submodules/altera_up_rs232_in_deserializer.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_up_rs232_in_deserializer.v" 47 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821248541 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394821248541 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_up_rs232_out_serializer.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_up_rs232_out_serializer.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_up_rs232_out_serializer " "Found entity 1: altera_up_rs232_out_serializer" { } { { "system/synthesis/submodules/altera_up_rs232_out_serializer.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_up_rs232_out_serializer.v" 47 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821248541 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394821248541 ""} +{ "Warning" "WVRFX_L2_VERI_INGORE_DANGLING_COMMA" "altera_up_sync_fifo.v(157) " "Verilog HDL Module Instantiation warning at altera_up_sync_fifo.v(157): ignored dangling comma in List of Port Connections" { } { { "system/synthesis/submodules/altera_up_sync_fifo.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_up_sync_fifo.v" 157 0 0 } } } 0 10275 "Verilog HDL Module Instantiation warning at %1!s!: ignored dangling comma in List of Port Connections" 0 0 "" 0 -1 1394821248557 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_up_sync_fifo.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_up_sync_fifo.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_up_sync_fifo " "Found entity 1: altera_up_sync_fifo" { } { { "system/synthesis/submodules/altera_up_sync_fifo.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_up_sync_fifo.v" 47 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821248557 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394821248557 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_rs232_motor.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_rs232_motor.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_rs232_motor " "Found entity 1: system_rs232_motor" { } { { "system/synthesis/submodules/system_rs232_motor.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_rs232_motor.v" 48 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821248557 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394821248557 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_pio_motor_rst.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_pio_motor_rst.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_pio_motor_rst " "Found entity 1: system_pio_motor_rst" { } { { "system/synthesis/submodules/system_pio_motor_rst.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_pio_motor_rst.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821248557 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394821248557 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_jtag_uart_0.v 7 7 " "Found 7 design units, including 7 entities, in source file system/synthesis/submodules/system_jtag_uart_0.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_jtag_uart_0_log_module " "Found entity 1: system_jtag_uart_0_log_module" { } { { "system/synthesis/submodules/system_jtag_uart_0.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_jtag_uart_0.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821248557 ""} { "Info" "ISGN_ENTITY_NAME" "2 system_jtag_uart_0_sim_scfifo_w " "Found entity 2: system_jtag_uart_0_sim_scfifo_w" { } { { "system/synthesis/submodules/system_jtag_uart_0.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_jtag_uart_0.v" 65 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821248557 ""} { "Info" "ISGN_ENTITY_NAME" "3 system_jtag_uart_0_scfifo_w " "Found entity 3: system_jtag_uart_0_scfifo_w" { } { { "system/synthesis/submodules/system_jtag_uart_0.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_jtag_uart_0.v" 123 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821248557 ""} { "Info" "ISGN_ENTITY_NAME" "4 system_jtag_uart_0_drom_module " "Found entity 4: system_jtag_uart_0_drom_module" { } { { "system/synthesis/submodules/system_jtag_uart_0.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_jtag_uart_0.v" 208 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821248557 ""} { "Info" "ISGN_ENTITY_NAME" "5 system_jtag_uart_0_sim_scfifo_r " "Found entity 5: system_jtag_uart_0_sim_scfifo_r" { } { { "system/synthesis/submodules/system_jtag_uart_0.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_jtag_uart_0.v" 362 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821248557 ""} { "Info" "ISGN_ENTITY_NAME" "6 system_jtag_uart_0_scfifo_r " "Found entity 6: system_jtag_uart_0_scfifo_r" { } { { "system/synthesis/submodules/system_jtag_uart_0.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_jtag_uart_0.v" 450 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821248557 ""} { "Info" "ISGN_ENTITY_NAME" "7 system_jtag_uart_0 " "Found entity 7: system_jtag_uart_0" { } { { "system/synthesis/submodules/system_jtag_uart_0.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_jtag_uart_0.v" 537 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821248557 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394821248557 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_pio_sw.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_pio_sw.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_pio_sw " "Found entity 1: system_pio_sw" { } { { "system/synthesis/submodules/system_pio_sw.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_pio_sw.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821248557 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394821248557 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_pio_key.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_pio_key.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_pio_key " "Found entity 1: system_pio_key" { } { { "system/synthesis/submodules/system_pio_key.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_pio_key.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821248557 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394821248557 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_pio_led.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_pio_led.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_pio_led " "Found entity 1: system_pio_led" { } { { "system/synthesis/submodules/system_pio_led.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_pio_led.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821248572 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394821248572 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_uart_0.v 7 7 " "Found 7 design units, including 7 entities, in source file system/synthesis/submodules/system_uart_0.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_uart_0_log_module " "Found entity 1: system_uart_0_log_module" { } { { "system/synthesis/submodules/system_uart_0.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_uart_0.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821248572 ""} { "Info" "ISGN_ENTITY_NAME" "2 system_uart_0_tx " "Found entity 2: system_uart_0_tx" { } { { "system/synthesis/submodules/system_uart_0.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_uart_0.v" 66 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821248572 ""} { "Info" "ISGN_ENTITY_NAME" "3 system_uart_0_rx_stimulus_source_character_source_rom_module " "Found entity 3: system_uart_0_rx_stimulus_source_character_source_rom_module" { } { { "system/synthesis/submodules/system_uart_0.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_uart_0.v" 238 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821248572 ""} { "Info" "ISGN_ENTITY_NAME" "4 system_uart_0_rx_stimulus_source " "Found entity 4: system_uart_0_rx_stimulus_source" { } { { "system/synthesis/submodules/system_uart_0.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_uart_0.v" 387 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821248572 ""} { "Info" "ISGN_ENTITY_NAME" "5 system_uart_0_rx " "Found entity 5: system_uart_0_rx" { } { { "system/synthesis/submodules/system_uart_0.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_uart_0.v" 492 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821248572 ""} { "Info" "ISGN_ENTITY_NAME" "6 system_uart_0_regs " "Found entity 6: system_uart_0_regs" { } { { "system/synthesis/submodules/system_uart_0.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_uart_0.v" 750 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821248572 ""} { "Info" "ISGN_ENTITY_NAME" "7 system_uart_0 " "Found entity 7: system_uart_0" { } { { "system/synthesis/submodules/system_uart_0.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_uart_0.v" 1006 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821248572 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394821248572 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_sys_clk_timer.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_sys_clk_timer.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_sys_clk_timer " "Found entity 1: system_sys_clk_timer" { } { { "system/synthesis/submodules/system_sys_clk_timer.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_sys_clk_timer.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821248572 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394821248572 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_sdram.v 2 2 " "Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_sdram.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_sdram_input_efifo_module " "Found entity 1: system_sdram_input_efifo_module" { } { { "system/synthesis/submodules/system_sdram.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_sdram.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821248572 ""} { "Info" "ISGN_ENTITY_NAME" "2 system_sdram " "Found entity 2: system_sdram" { } { { "system/synthesis/submodules/system_sdram.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_sdram.v" 158 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821248572 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394821248572 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_sysid.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_sysid.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_sysid " "Found entity 1: system_sysid" { } { { "system/synthesis/submodules/system_sysid.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_sysid.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821248572 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394821248572 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_cpu.v 28 28 " "Found 28 design units, including 28 entities, in source file system/synthesis/submodules/system_cpu.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_cpu_ic_data_module " "Found entity 1: system_cpu_ic_data_module" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821249992 ""} { "Info" "ISGN_ENTITY_NAME" "2 system_cpu_ic_tag_module " "Found entity 2: system_cpu_ic_tag_module" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 86 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821249992 ""} { "Info" "ISGN_ENTITY_NAME" "3 system_cpu_bht_module " "Found entity 3: system_cpu_bht_module" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 152 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821249992 ""} { "Info" "ISGN_ENTITY_NAME" "4 system_cpu_register_bank_a_module " "Found entity 4: system_cpu_register_bank_a_module" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 218 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821249992 ""} { "Info" "ISGN_ENTITY_NAME" "5 system_cpu_register_bank_b_module " "Found entity 5: system_cpu_register_bank_b_module" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 281 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821249992 ""} { "Info" "ISGN_ENTITY_NAME" "6 system_cpu_dc_tag_module " "Found entity 6: system_cpu_dc_tag_module" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 344 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821249992 ""} { "Info" "ISGN_ENTITY_NAME" "7 system_cpu_dc_data_module " "Found entity 7: system_cpu_dc_data_module" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 407 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821249992 ""} { "Info" "ISGN_ENTITY_NAME" "8 system_cpu_dc_victim_module " "Found entity 8: system_cpu_dc_victim_module" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 473 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821249992 ""} { "Info" "ISGN_ENTITY_NAME" "9 system_cpu_nios2_oci_debug " "Found entity 9: system_cpu_nios2_oci_debug" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 538 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821249992 ""} { "Info" "ISGN_ENTITY_NAME" "10 system_cpu_ociram_lpm_dram_bdp_component_module " "Found entity 10: system_cpu_ociram_lpm_dram_bdp_component_module" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 666 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821249992 ""} { "Info" "ISGN_ENTITY_NAME" "11 system_cpu_nios2_ocimem " "Found entity 11: system_cpu_nios2_ocimem" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 759 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821249992 ""} { "Info" "ISGN_ENTITY_NAME" "12 system_cpu_nios2_avalon_reg " "Found entity 12: system_cpu_nios2_avalon_reg" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 905 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821249992 ""} { "Info" "ISGN_ENTITY_NAME" "13 system_cpu_nios2_oci_break " "Found entity 13: system_cpu_nios2_oci_break" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 999 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821249992 ""} { "Info" "ISGN_ENTITY_NAME" "14 system_cpu_nios2_oci_xbrk " "Found entity 14: system_cpu_nios2_oci_xbrk" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 1293 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821249992 ""} { "Info" "ISGN_ENTITY_NAME" "15 system_cpu_nios2_oci_dbrk " "Found entity 15: system_cpu_nios2_oci_dbrk" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 1553 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821249992 ""} { "Info" "ISGN_ENTITY_NAME" "16 system_cpu_nios2_oci_itrace " "Found entity 16: system_cpu_nios2_oci_itrace" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 1741 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821249992 ""} { "Info" "ISGN_ENTITY_NAME" "17 system_cpu_nios2_oci_td_mode " "Found entity 17: system_cpu_nios2_oci_td_mode" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 2098 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821249992 ""} { "Info" "ISGN_ENTITY_NAME" "18 system_cpu_nios2_oci_dtrace " "Found entity 18: system_cpu_nios2_oci_dtrace" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 2165 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821249992 ""} { "Info" "ISGN_ENTITY_NAME" "19 system_cpu_nios2_oci_compute_tm_count " "Found entity 19: system_cpu_nios2_oci_compute_tm_count" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 2259 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821249992 ""} { "Info" "ISGN_ENTITY_NAME" "20 system_cpu_nios2_oci_fifowp_inc " "Found entity 20: system_cpu_nios2_oci_fifowp_inc" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 2330 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821249992 ""} { "Info" "ISGN_ENTITY_NAME" "21 system_cpu_nios2_oci_fifocount_inc " "Found entity 21: system_cpu_nios2_oci_fifocount_inc" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 2372 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821249992 ""} { "Info" "ISGN_ENTITY_NAME" "22 system_cpu_nios2_oci_fifo " "Found entity 22: system_cpu_nios2_oci_fifo" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 2418 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821249992 ""} { "Info" "ISGN_ENTITY_NAME" "23 system_cpu_nios2_oci_pib " "Found entity 23: system_cpu_nios2_oci_pib" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 2923 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821249992 ""} { "Info" "ISGN_ENTITY_NAME" "24 system_cpu_traceram_lpm_dram_bdp_component_module " "Found entity 24: system_cpu_traceram_lpm_dram_bdp_component_module" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 2991 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821249992 ""} { "Info" "ISGN_ENTITY_NAME" "25 system_cpu_nios2_oci_im " "Found entity 25: system_cpu_nios2_oci_im" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3080 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821249992 ""} { "Info" "ISGN_ENTITY_NAME" "26 system_cpu_nios2_performance_monitors " "Found entity 26: system_cpu_nios2_performance_monitors" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3217 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821249992 ""} { "Info" "ISGN_ENTITY_NAME" "27 system_cpu_nios2_oci " "Found entity 27: system_cpu_nios2_oci" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3233 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821249992 ""} { "Info" "ISGN_ENTITY_NAME" "28 system_cpu " "Found entity 28: system_cpu" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3736 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821249992 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394821249992 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_cpu_jtag_debug_module_sysclk.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_cpu_jtag_debug_module_sysclk.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_cpu_jtag_debug_module_sysclk " "Found entity 1: system_cpu_jtag_debug_module_sysclk" { } { { "system/synthesis/submodules/system_cpu_jtag_debug_module_sysclk.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu_jtag_debug_module_sysclk.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821249992 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394821249992 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_cpu_jtag_debug_module_tck.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_cpu_jtag_debug_module_tck.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_cpu_jtag_debug_module_tck " "Found entity 1: system_cpu_jtag_debug_module_tck" { } { { "system/synthesis/submodules/system_cpu_jtag_debug_module_tck.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu_jtag_debug_module_tck.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821250008 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394821250008 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_cpu_jtag_debug_module_wrapper " "Found entity 1: system_cpu_jtag_debug_module_wrapper" { } { { "system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821250008 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394821250008 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_cpu_mult_cell.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_cpu_mult_cell.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_cpu_mult_cell " "Found entity 1: system_cpu_mult_cell" { } { { "system/synthesis/submodules/system_cpu_mult_cell.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu_mult_cell.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821250008 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394821250008 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_cpu_oci_test_bench.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_cpu_oci_test_bench.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_cpu_oci_test_bench " "Found entity 1: system_cpu_oci_test_bench" { } { { "system/synthesis/submodules/system_cpu_oci_test_bench.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu_oci_test_bench.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821250008 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394821250008 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_cpu_test_bench.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_cpu_test_bench.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_cpu_test_bench " "Found entity 1: system_cpu_test_bench" { } { { "system/synthesis/submodules/system_cpu_test_bench.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu_test_bench.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821250008 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394821250008 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pll_sys.vhd 2 1 " "Found 2 design units, including 1 entities, in source file pll_sys.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 pll_sys-SYN " "Found design unit 1: pll_sys-SYN" { } { { "pll_sys.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/pll_sys.vhd" 54 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1 1394821250023 ""} { "Info" "ISGN_ENTITY_NAME" "1 pll_sys " "Found entity 1: pll_sys" { } { { "pll_sys.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/pll_sys.vhd" 42 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821250023 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394821250023 ""} +{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "system_cpu.v(2066) " "Verilog HDL or VHDL warning at system_cpu.v(2066): conditional expression evaluates to a constant" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 2066 0 0 } } } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1 1394821250039 ""} +{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "system_cpu.v(2068) " "Verilog HDL or VHDL warning at system_cpu.v(2068): conditional expression evaluates to a constant" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 2068 0 0 } } } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1 1394821250039 ""} +{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "system_cpu.v(2224) " "Verilog HDL or VHDL warning at system_cpu.v(2224): conditional expression evaluates to a constant" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 2224 0 0 } } } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1 1394821250039 ""} +{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "system_cpu.v(3143) " "Verilog HDL or VHDL warning at system_cpu.v(3143): conditional expression evaluates to a constant" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3143 0 0 } } } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1 1394821250039 ""} +{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "system_sdram.v(316) " "Verilog HDL or VHDL warning at system_sdram.v(316): conditional expression evaluates to a constant" { } { { "system/synthesis/submodules/system_sdram.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_sdram.v" 316 0 0 } } } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1 1394821250054 ""} +{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "system_sdram.v(326) " "Verilog HDL or VHDL warning at system_sdram.v(326): conditional expression evaluates to a constant" { } { { "system/synthesis/submodules/system_sdram.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_sdram.v" 326 0 0 } } } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1 1394821250054 ""} +{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "system_sdram.v(336) " "Verilog HDL or VHDL warning at system_sdram.v(336): conditional expression evaluates to a constant" { } { { "system/synthesis/submodules/system_sdram.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_sdram.v" 336 0 0 } } } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1 1394821250054 ""} +{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "system_sdram.v(680) " "Verilog HDL or VHDL warning at system_sdram.v(680): conditional expression evaluates to a constant" { } { { "system/synthesis/submodules/system_sdram.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_sdram.v" 680 0 0 } } } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1 1394821250054 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "de0_nano_system " "Elaborating entity \"de0_nano_system\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1 1394821250554 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pll_sys pll_sys:inst_pll_sys " "Elaborating entity \"pll_sys\" for hierarchy \"pll_sys:inst_pll_sys\"" { } { { "de0_nano_system.vhd" "inst_pll_sys" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 149 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821250585 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll pll_sys:inst_pll_sys\|altpll:altpll_component " "Elaborating entity \"altpll\" for hierarchy \"pll_sys:inst_pll_sys\|altpll:altpll_component\"" { } { { "pll_sys.vhd" "altpll_component" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/pll_sys.vhd" 154 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821251131 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "pll_sys:inst_pll_sys\|altpll:altpll_component " "Elaborated megafunction instantiation \"pll_sys:inst_pll_sys\|altpll:altpll_component\"" { } { { "pll_sys.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/pll_sys.vhd" 154 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1394821251146 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "pll_sys:inst_pll_sys\|altpll:altpll_component " "Instantiated megafunction \"pll_sys:inst_pll_sys\|altpll:altpll_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "bandwidth_type AUTO " "Parameter \"bandwidth_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251162 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_divide_by 1 " "Parameter \"clk0_divide_by\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251162 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_duty_cycle 50 " "Parameter \"clk0_duty_cycle\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251162 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_multiply_by 2 " "Parameter \"clk0_multiply_by\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251162 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_phase_shift 0 " "Parameter \"clk0_phase_shift\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251162 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_divide_by 1 " "Parameter \"clk1_divide_by\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251162 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_duty_cycle 50 " "Parameter \"clk1_duty_cycle\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251162 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_multiply_by 2 " "Parameter \"clk1_multiply_by\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251162 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_phase_shift -1500 " "Parameter \"clk1_phase_shift\" = \"-1500\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251162 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_divide_by 5 " "Parameter \"clk2_divide_by\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251162 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_duty_cycle 50 " "Parameter \"clk2_duty_cycle\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251162 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_multiply_by 1 " "Parameter \"clk2_multiply_by\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251162 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_phase_shift 0 " "Parameter \"clk2_phase_shift\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251162 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "compensate_clock CLK0 " "Parameter \"compensate_clock\" = \"CLK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251162 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "inclk0_input_frequency 20000 " "Parameter \"inclk0_input_frequency\" = \"20000\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251162 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251162 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint CBX_MODULE_PREFIX=pll_sys " "Parameter \"lpm_hint\" = \"CBX_MODULE_PREFIX=pll_sys\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251162 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altpll " "Parameter \"lpm_type\" = \"altpll\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251162 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode NORMAL " "Parameter \"operation_mode\" = \"NORMAL\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251162 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_type AUTO " "Parameter \"pll_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251162 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_activeclock PORT_UNUSED " "Parameter \"port_activeclock\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251162 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_areset PORT_UNUSED " "Parameter \"port_areset\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251162 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad0 PORT_UNUSED " "Parameter \"port_clkbad0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251162 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad1 PORT_UNUSED " "Parameter \"port_clkbad1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251162 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkloss PORT_UNUSED " "Parameter \"port_clkloss\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251162 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkswitch PORT_UNUSED " "Parameter \"port_clkswitch\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251162 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_configupdate PORT_UNUSED " "Parameter \"port_configupdate\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251162 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_fbin PORT_UNUSED " "Parameter \"port_fbin\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251162 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk0 PORT_USED " "Parameter \"port_inclk0\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251162 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk1 PORT_UNUSED " "Parameter \"port_inclk1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251162 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_locked PORT_USED " "Parameter \"port_locked\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251162 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pfdena PORT_UNUSED " "Parameter \"port_pfdena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251162 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasecounterselect PORT_UNUSED " "Parameter \"port_phasecounterselect\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251162 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasedone PORT_UNUSED " "Parameter \"port_phasedone\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251162 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasestep PORT_UNUSED " "Parameter \"port_phasestep\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251162 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phaseupdown PORT_UNUSED " "Parameter \"port_phaseupdown\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251162 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pllena PORT_UNUSED " "Parameter \"port_pllena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251162 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanaclr PORT_UNUSED " "Parameter \"port_scanaclr\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251162 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclk PORT_UNUSED " "Parameter \"port_scanclk\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251162 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclkena PORT_UNUSED " "Parameter \"port_scanclkena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251162 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandata PORT_UNUSED " "Parameter \"port_scandata\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251162 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandataout PORT_UNUSED " "Parameter \"port_scandataout\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251162 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandone PORT_UNUSED " "Parameter \"port_scandone\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251162 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanread PORT_UNUSED " "Parameter \"port_scanread\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251162 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanwrite PORT_UNUSED " "Parameter \"port_scanwrite\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251162 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk0 PORT_USED " "Parameter \"port_clk0\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251162 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk1 PORT_USED " "Parameter \"port_clk1\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251162 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk2 PORT_USED " "Parameter \"port_clk2\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251162 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk3 PORT_UNUSED " "Parameter \"port_clk3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251162 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk4 PORT_UNUSED " "Parameter \"port_clk4\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251162 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk5 PORT_UNUSED " "Parameter \"port_clk5\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251162 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena0 PORT_UNUSED " "Parameter \"port_clkena0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251162 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena1 PORT_UNUSED " "Parameter \"port_clkena1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251162 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena2 PORT_UNUSED " "Parameter \"port_clkena2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251162 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena3 PORT_UNUSED " "Parameter \"port_clkena3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251162 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena4 PORT_UNUSED " "Parameter \"port_clkena4\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251162 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena5 PORT_UNUSED " "Parameter \"port_clkena5\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251162 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk0 PORT_UNUSED " "Parameter \"port_extclk0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251162 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk1 PORT_UNUSED " "Parameter \"port_extclk1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251162 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk2 PORT_UNUSED " "Parameter \"port_extclk2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251162 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk3 PORT_UNUSED " "Parameter \"port_extclk3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251162 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "self_reset_on_loss_lock ON " "Parameter \"self_reset_on_loss_lock\" = \"ON\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251162 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_clock 5 " "Parameter \"width_clock\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251162 ""} } { { "pll_sys.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/pll_sys.vhd" 154 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1394821251162 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/pll_sys_altpll.v 1 1 " "Found 1 design units, including 1 entities, in source file db/pll_sys_altpll.v" { { "Info" "ISGN_ENTITY_NAME" "1 pll_sys_altpll " "Found entity 1: pll_sys_altpll" { } { { "db/pll_sys_altpll.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/pll_sys_altpll.v" 29 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821251271 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394821251271 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pll_sys_altpll pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated " "Elaborating entity \"pll_sys_altpll\" for hierarchy \"pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\"" { } { { "altpll.tdf" "auto_generated" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altpll.tdf" 897 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821251271 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "heartbeat heartbeat:inst_heartbeat " "Elaborating entity \"heartbeat\" for hierarchy \"heartbeat:inst_heartbeat\"" { } { { "de0_nano_system.vhd" "inst_heartbeat" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 158 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821251318 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system system:inst_cpu " "Elaborating entity \"system\" for hierarchy \"system:inst_cpu\"" { } { { "de0_nano_system.vhd" "inst_cpu" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 164 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821251318 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu system:inst_cpu\|system_cpu:cpu " "Elaborating entity \"system_cpu\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\"" { } { { "system/synthesis/system.v" "cpu" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 788 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821251396 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_test_bench system:inst_cpu\|system_cpu:cpu\|system_cpu_test_bench:the_system_cpu_test_bench " "Elaborating entity \"system_cpu_test_bench\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_test_bench:the_system_cpu_test_bench\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_test_bench" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 6059 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821251490 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_ic_data_module system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_data_module:system_cpu_ic_data " "Elaborating entity \"system_cpu_ic_data_module\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_data_module:system_cpu_ic_data\"" { } { { "system/synthesis/submodules/system_cpu.v" "system_cpu_ic_data" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 7084 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821251521 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_data_module:system_cpu_ic_data\|altsyncram:the_altsyncram " "Elaborating entity \"altsyncram\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_data_module:system_cpu_ic_data\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_altsyncram" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 58 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821251583 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_data_module:system_cpu_ic_data\|altsyncram:the_altsyncram " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_data_module:system_cpu_ic_data\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 58 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1394821251630 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_data_module:system_cpu_ic_data\|altsyncram:the_altsyncram " "Instantiated megafunction \"system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_data_module:system_cpu_ic_data\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251630 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 0 " "Parameter \"maximum_depth\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251630 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 2048 " "Parameter \"numwords_a\" = \"2048\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251630 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 2048 " "Parameter \"numwords_b\" = \"2048\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251630 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Parameter \"operation_mode\" = \"DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251630 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251630 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251630 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rdcontrol_reg_b CLOCK0 " "Parameter \"rdcontrol_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251630 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251630 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 32 " "Parameter \"width_a\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251630 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 32 " "Parameter \"width_b\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251630 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 11 " "Parameter \"widthad_a\" = \"11\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251630 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 11 " "Parameter \"widthad_b\" = \"11\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251630 ""} } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 58 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1394821251630 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_sjd1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_sjd1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_sjd1 " "Found entity 1: altsyncram_sjd1" { } { { "db/altsyncram_sjd1.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_sjd1.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821251708 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394821251708 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_sjd1 system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_data_module:system_cpu_ic_data\|altsyncram:the_altsyncram\|altsyncram_sjd1:auto_generated " "Elaborating entity \"altsyncram_sjd1\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_data_module:system_cpu_ic_data\|altsyncram:the_altsyncram\|altsyncram_sjd1:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821251708 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_ic_tag_module system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_tag_module:system_cpu_ic_tag " "Elaborating entity \"system_cpu_ic_tag_module\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_tag_module:system_cpu_ic_tag\"" { } { { "system/synthesis/submodules/system_cpu.v" "system_cpu_ic_tag" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 7150 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821251739 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_tag_module:system_cpu_ic_tag\|altsyncram:the_altsyncram " "Elaborating entity \"altsyncram\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_tag_module:system_cpu_ic_tag\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_altsyncram" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 123 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821251755 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_tag_module:system_cpu_ic_tag\|altsyncram:the_altsyncram " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_tag_module:system_cpu_ic_tag\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 123 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1394821251770 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_tag_module:system_cpu_ic_tag\|altsyncram:the_altsyncram " "Instantiated megafunction \"system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_tag_module:system_cpu_ic_tag\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251770 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file system_cpu_ic_tag_ram.mif " "Parameter \"init_file\" = \"system_cpu_ic_tag_ram.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251770 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 0 " "Parameter \"maximum_depth\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251770 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 256 " "Parameter \"numwords_a\" = \"256\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251770 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 256 " "Parameter \"numwords_b\" = \"256\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251770 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Parameter \"operation_mode\" = \"DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251770 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251770 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251770 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rdcontrol_reg_b CLOCK0 " "Parameter \"rdcontrol_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251770 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports OLD_DATA " "Parameter \"read_during_write_mode_mixed_ports\" = \"OLD_DATA\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251770 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 21 " "Parameter \"width_a\" = \"21\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251770 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 21 " "Parameter \"width_b\" = \"21\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251770 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 8 " "Parameter \"widthad_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251770 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 8 " "Parameter \"widthad_b\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251770 ""} } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 123 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1394821251770 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_qtg1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_qtg1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_qtg1 " "Found entity 1: altsyncram_qtg1" { } { { "db/altsyncram_qtg1.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_qtg1.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821251848 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394821251848 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_qtg1 system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_tag_module:system_cpu_ic_tag\|altsyncram:the_altsyncram\|altsyncram_qtg1:auto_generated " "Elaborating entity \"altsyncram_qtg1\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_tag_module:system_cpu_ic_tag\|altsyncram:the_altsyncram\|altsyncram_qtg1:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821251848 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_bht_module system:inst_cpu\|system_cpu:cpu\|system_cpu_bht_module:system_cpu_bht " "Elaborating entity \"system_cpu_bht_module\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_bht_module:system_cpu_bht\"" { } { { "system/synthesis/submodules/system_cpu.v" "system_cpu_bht" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 7354 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821251880 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram system:inst_cpu\|system_cpu:cpu\|system_cpu_bht_module:system_cpu_bht\|altsyncram:the_altsyncram " "Elaborating entity \"altsyncram\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_bht_module:system_cpu_bht\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_altsyncram" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 189 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821251911 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_cpu:cpu\|system_cpu_bht_module:system_cpu_bht\|altsyncram:the_altsyncram " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_bht_module:system_cpu_bht\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 189 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1394821251911 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_cpu:cpu\|system_cpu_bht_module:system_cpu_bht\|altsyncram:the_altsyncram " "Instantiated megafunction \"system:inst_cpu\|system_cpu:cpu\|system_cpu_bht_module:system_cpu_bht\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251911 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file system_cpu_bht_ram.mif " "Parameter \"init_file\" = \"system_cpu_bht_ram.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251911 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 0 " "Parameter \"maximum_depth\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251911 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 256 " "Parameter \"numwords_a\" = \"256\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251911 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 256 " "Parameter \"numwords_b\" = \"256\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251911 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Parameter \"operation_mode\" = \"DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251911 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251911 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251911 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rdcontrol_reg_b CLOCK0 " "Parameter \"rdcontrol_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251911 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports OLD_DATA " "Parameter \"read_during_write_mode_mixed_ports\" = \"OLD_DATA\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251911 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 2 " "Parameter \"width_a\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251911 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 2 " "Parameter \"width_b\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251911 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 8 " "Parameter \"widthad_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251911 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 8 " "Parameter \"widthad_b\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821251911 ""} } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 189 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1394821251911 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_fhg1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_fhg1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_fhg1 " "Found entity 1: altsyncram_fhg1" { } { { "db/altsyncram_fhg1.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_fhg1.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821251958 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394821251958 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_fhg1 system:inst_cpu\|system_cpu:cpu\|system_cpu_bht_module:system_cpu_bht\|altsyncram:the_altsyncram\|altsyncram_fhg1:auto_generated " "Elaborating entity \"altsyncram_fhg1\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_bht_module:system_cpu_bht\|altsyncram:the_altsyncram\|altsyncram_fhg1:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821251973 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_register_bank_a_module system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_a_module:system_cpu_register_bank_a " "Elaborating entity \"system_cpu_register_bank_a_module\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_a_module:system_cpu_register_bank_a\"" { } { { "system/synthesis/submodules/system_cpu.v" "system_cpu_register_bank_a" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 7500 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821251973 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_a_module:system_cpu_register_bank_a\|altsyncram:the_altsyncram " "Elaborating entity \"altsyncram\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_a_module:system_cpu_register_bank_a\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_altsyncram" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 252 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821251989 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_a_module:system_cpu_register_bank_a\|altsyncram:the_altsyncram " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_a_module:system_cpu_register_bank_a\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 252 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1394821252051 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_a_module:system_cpu_register_bank_a\|altsyncram:the_altsyncram " "Instantiated megafunction \"system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_a_module:system_cpu_register_bank_a\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252051 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file system_cpu_rf_ram_a.mif " "Parameter \"init_file\" = \"system_cpu_rf_ram_a.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252051 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 0 " "Parameter \"maximum_depth\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252051 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 32 " "Parameter \"numwords_a\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252051 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 32 " "Parameter \"numwords_b\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252051 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Parameter \"operation_mode\" = \"DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252051 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252051 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252051 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rdcontrol_reg_b CLOCK0 " "Parameter \"rdcontrol_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252051 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports OLD_DATA " "Parameter \"read_during_write_mode_mixed_ports\" = \"OLD_DATA\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252051 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 32 " "Parameter \"width_a\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252051 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 32 " "Parameter \"width_b\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252051 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 5 " "Parameter \"widthad_a\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252051 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 5 " "Parameter \"widthad_b\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252051 ""} } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 252 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1394821252051 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_fvf1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_fvf1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_fvf1 " "Found entity 1: altsyncram_fvf1" { } { { "db/altsyncram_fvf1.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_fvf1.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821252129 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394821252129 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_fvf1 system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_a_module:system_cpu_register_bank_a\|altsyncram:the_altsyncram\|altsyncram_fvf1:auto_generated " "Elaborating entity \"altsyncram_fvf1\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_a_module:system_cpu_register_bank_a\|altsyncram:the_altsyncram\|altsyncram_fvf1:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821252129 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_register_bank_b_module system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_b_module:system_cpu_register_bank_b " "Elaborating entity \"system_cpu_register_bank_b_module\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_b_module:system_cpu_register_bank_b\"" { } { { "system/synthesis/submodules/system_cpu.v" "system_cpu_register_bank_b" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 7521 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821252176 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_b_module:system_cpu_register_bank_b\|altsyncram:the_altsyncram " "Elaborating entity \"altsyncram\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_b_module:system_cpu_register_bank_b\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_altsyncram" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 315 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821252176 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_b_module:system_cpu_register_bank_b\|altsyncram:the_altsyncram " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_b_module:system_cpu_register_bank_b\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 315 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1394821252223 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_b_module:system_cpu_register_bank_b\|altsyncram:the_altsyncram " "Instantiated megafunction \"system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_b_module:system_cpu_register_bank_b\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252223 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file system_cpu_rf_ram_b.mif " "Parameter \"init_file\" = \"system_cpu_rf_ram_b.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252223 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 0 " "Parameter \"maximum_depth\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252223 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 32 " "Parameter \"numwords_a\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252223 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 32 " "Parameter \"numwords_b\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252223 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Parameter \"operation_mode\" = \"DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252223 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252223 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252223 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rdcontrol_reg_b CLOCK0 " "Parameter \"rdcontrol_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252223 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports OLD_DATA " "Parameter \"read_during_write_mode_mixed_ports\" = \"OLD_DATA\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252223 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 32 " "Parameter \"width_a\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252223 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 32 " "Parameter \"width_b\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252223 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 5 " "Parameter \"widthad_a\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252223 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 5 " "Parameter \"widthad_b\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252223 ""} } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 315 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1394821252223 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_gvf1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_gvf1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_gvf1 " "Found entity 1: altsyncram_gvf1" { } { { "db/altsyncram_gvf1.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_gvf1.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821252301 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394821252301 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_gvf1 system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_b_module:system_cpu_register_bank_b\|altsyncram:the_altsyncram\|altsyncram_gvf1:auto_generated " "Elaborating entity \"altsyncram_gvf1\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_b_module:system_cpu_register_bank_b\|altsyncram:the_altsyncram\|altsyncram_gvf1:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821252301 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_dc_tag_module system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_tag_module:system_cpu_dc_tag " "Elaborating entity \"system_cpu_dc_tag_module\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_tag_module:system_cpu_dc_tag\"" { } { { "system/synthesis/submodules/system_cpu.v" "system_cpu_dc_tag" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 7954 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821252332 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_tag_module:system_cpu_dc_tag\|altsyncram:the_altsyncram " "Elaborating entity \"altsyncram\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_tag_module:system_cpu_dc_tag\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_altsyncram" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 378 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821252348 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_tag_module:system_cpu_dc_tag\|altsyncram:the_altsyncram " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_tag_module:system_cpu_dc_tag\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 378 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1394821252348 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_tag_module:system_cpu_dc_tag\|altsyncram:the_altsyncram " "Instantiated megafunction \"system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_tag_module:system_cpu_dc_tag\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252348 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file system_cpu_dc_tag_ram.mif " "Parameter \"init_file\" = \"system_cpu_dc_tag_ram.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252348 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 0 " "Parameter \"maximum_depth\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252348 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 128 " "Parameter \"numwords_a\" = \"128\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252348 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 128 " "Parameter \"numwords_b\" = \"128\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252348 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Parameter \"operation_mode\" = \"DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252348 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252348 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252348 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rdcontrol_reg_b CLOCK0 " "Parameter \"rdcontrol_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252348 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports OLD_DATA " "Parameter \"read_during_write_mode_mixed_ports\" = \"OLD_DATA\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252348 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 16 " "Parameter \"width_a\" = \"16\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252348 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 16 " "Parameter \"width_b\" = \"16\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252348 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 7 " "Parameter \"widthad_a\" = \"7\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252348 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 7 " "Parameter \"widthad_b\" = \"7\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252348 ""} } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 378 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1394821252348 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_d9g1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_d9g1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_d9g1 " "Found entity 1: altsyncram_d9g1" { } { { "db/altsyncram_d9g1.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_d9g1.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821252426 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394821252426 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_d9g1 system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_tag_module:system_cpu_dc_tag\|altsyncram:the_altsyncram\|altsyncram_d9g1:auto_generated " "Elaborating entity \"altsyncram_d9g1\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_tag_module:system_cpu_dc_tag\|altsyncram:the_altsyncram\|altsyncram_d9g1:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821252426 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_dc_data_module system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_data_module:system_cpu_dc_data " "Elaborating entity \"system_cpu_dc_data_module\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_data_module:system_cpu_dc_data\"" { } { { "system/synthesis/submodules/system_cpu.v" "system_cpu_dc_data" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 8008 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821252441 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_data_module:system_cpu_dc_data\|altsyncram:the_altsyncram " "Elaborating entity \"altsyncram\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_data_module:system_cpu_dc_data\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_altsyncram" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 444 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821252457 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_data_module:system_cpu_dc_data\|altsyncram:the_altsyncram " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_data_module:system_cpu_dc_data\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 444 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1394821252472 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_data_module:system_cpu_dc_data\|altsyncram:the_altsyncram " "Instantiated megafunction \"system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_data_module:system_cpu_dc_data\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252472 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 0 " "Parameter \"maximum_depth\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252472 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 1024 " "Parameter \"numwords_a\" = \"1024\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252472 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 1024 " "Parameter \"numwords_b\" = \"1024\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252472 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Parameter \"operation_mode\" = \"DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252472 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252472 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252472 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rdcontrol_reg_b CLOCK0 " "Parameter \"rdcontrol_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252472 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252472 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 32 " "Parameter \"width_a\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252472 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 32 " "Parameter \"width_b\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252472 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 4 " "Parameter \"width_byteena_a\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252472 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 10 " "Parameter \"widthad_a\" = \"10\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252472 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 10 " "Parameter \"widthad_b\" = \"10\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252472 ""} } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 444 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1394821252472 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_2jf1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_2jf1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_2jf1 " "Found entity 1: altsyncram_2jf1" { } { { "db/altsyncram_2jf1.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_2jf1.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821252550 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394821252550 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_2jf1 system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_data_module:system_cpu_dc_data\|altsyncram:the_altsyncram\|altsyncram_2jf1:auto_generated " "Elaborating entity \"altsyncram_2jf1\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_data_module:system_cpu_dc_data\|altsyncram:the_altsyncram\|altsyncram_2jf1:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821252550 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_dc_victim_module system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_victim_module:system_cpu_dc_victim " "Elaborating entity \"system_cpu_dc_victim_module\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_victim_module:system_cpu_dc_victim\"" { } { { "system/synthesis/submodules/system_cpu.v" "system_cpu_dc_victim" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 8024 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821252566 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_victim_module:system_cpu_dc_victim\|altsyncram:the_altsyncram " "Elaborating entity \"altsyncram\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_victim_module:system_cpu_dc_victim\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_altsyncram" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 510 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821252582 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_victim_module:system_cpu_dc_victim\|altsyncram:the_altsyncram " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_victim_module:system_cpu_dc_victim\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 510 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1394821252582 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_victim_module:system_cpu_dc_victim\|altsyncram:the_altsyncram " "Instantiated megafunction \"system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_victim_module:system_cpu_dc_victim\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252582 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 0 " "Parameter \"maximum_depth\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252582 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 8 " "Parameter \"numwords_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252582 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 8 " "Parameter \"numwords_b\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252582 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Parameter \"operation_mode\" = \"DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252582 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252582 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252582 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rdcontrol_reg_b CLOCK0 " "Parameter \"rdcontrol_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252582 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports OLD_DATA " "Parameter \"read_during_write_mode_mixed_ports\" = \"OLD_DATA\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252582 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 32 " "Parameter \"width_a\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252582 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 32 " "Parameter \"width_b\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252582 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 3 " "Parameter \"widthad_a\" = \"3\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252582 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 3 " "Parameter \"widthad_b\" = \"3\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252582 ""} } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 510 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1394821252582 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_r3d1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_r3d1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_r3d1 " "Found entity 1: altsyncram_r3d1" { } { { "db/altsyncram_r3d1.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_r3d1.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821252660 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394821252660 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_r3d1 system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_victim_module:system_cpu_dc_victim\|altsyncram:the_altsyncram\|altsyncram_r3d1:auto_generated " "Elaborating entity \"altsyncram_r3d1\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_victim_module:system_cpu_dc_victim\|altsyncram:the_altsyncram\|altsyncram_r3d1:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821252660 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_mult_cell system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell " "Elaborating entity \"system_cpu_mult_cell\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_mult_cell" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 9849 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821252675 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altmult_add system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_1 " "Elaborating entity \"altmult_add\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_1\"" { } { { "system/synthesis/submodules/system_cpu_mult_cell.v" "the_altmult_add_part_1" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu_mult_cell.v" 52 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821252894 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_1 " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_1\"" { } { { "system/synthesis/submodules/system_cpu_mult_cell.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu_mult_cell.v" 52 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1394821252925 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_1 " "Instantiated megafunction \"system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_1\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "addnsub_multiplier_pipeline_aclr1 ACLR0 " "Parameter \"addnsub_multiplier_pipeline_aclr1\" = \"ACLR0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252925 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "addnsub_multiplier_pipeline_register1 CLOCK0 " "Parameter \"addnsub_multiplier_pipeline_register1\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252925 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "addnsub_multiplier_register1 UNREGISTERED " "Parameter \"addnsub_multiplier_register1\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252925 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "dedicated_multiplier_circuitry YES " "Parameter \"dedicated_multiplier_circuitry\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252925 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "input_register_a0 UNREGISTERED " "Parameter \"input_register_a0\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252925 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "input_register_b0 UNREGISTERED " "Parameter \"input_register_b0\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252925 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "input_source_a0 DATAA " "Parameter \"input_source_a0\" = \"DATAA\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252925 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "input_source_b0 DATAB " "Parameter \"input_source_b0\" = \"DATAB\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252925 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family CYCLONEIVE " "Parameter \"intended_device_family\" = \"CYCLONEIVE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252925 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altmult_add " "Parameter \"lpm_type\" = \"altmult_add\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252925 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "multiplier1_direction ADD " "Parameter \"multiplier1_direction\" = \"ADD\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252925 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "multiplier_aclr0 ACLR0 " "Parameter \"multiplier_aclr0\" = \"ACLR0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252925 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "multiplier_register0 CLOCK0 " "Parameter \"multiplier_register0\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252925 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "number_of_multipliers 1 " "Parameter \"number_of_multipliers\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252925 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_register UNREGISTERED " "Parameter \"output_register\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252925 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_addnsub1 PORT_UNUSED " "Parameter \"port_addnsub1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252925 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_addnsub3 PORT_UNUSED " "Parameter \"port_addnsub3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252925 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_signa PORT_UNUSED " "Parameter \"port_signa\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252925 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_signb PORT_UNUSED " "Parameter \"port_signb\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252925 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "representation_a UNSIGNED " "Parameter \"representation_a\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252925 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "representation_b UNSIGNED " "Parameter \"representation_b\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252925 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_pipeline_aclr_a ACLR0 " "Parameter \"signed_pipeline_aclr_a\" = \"ACLR0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252925 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_pipeline_aclr_b ACLR0 " "Parameter \"signed_pipeline_aclr_b\" = \"ACLR0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252925 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_pipeline_register_a CLOCK0 " "Parameter \"signed_pipeline_register_a\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252925 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_pipeline_register_b CLOCK0 " "Parameter \"signed_pipeline_register_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252925 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_register_a UNREGISTERED " "Parameter \"signed_register_a\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252925 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_register_b UNREGISTERED " "Parameter \"signed_register_b\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252925 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 16 " "Parameter \"width_a\" = \"16\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252925 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 16 " "Parameter \"width_b\" = \"16\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252925 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_result 32 " "Parameter \"width_result\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821252925 ""} } { { "system/synthesis/submodules/system_cpu_mult_cell.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu_mult_cell.v" 52 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1394821252925 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mult_add_75u2.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mult_add_75u2.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mult_add_75u2 " "Found entity 1: mult_add_75u2" { } { { "db/mult_add_75u2.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/mult_add_75u2.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821253019 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394821253019 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mult_add_75u2 system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_1\|mult_add_75u2:auto_generated " "Elaborating entity \"mult_add_75u2\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_1\|mult_add_75u2:auto_generated\"" { } { { "altmult_add.tdf" "auto_generated" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altmult_add.tdf" 594 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821253019 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ded_mult_ks81.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/ded_mult_ks81.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 ded_mult_ks81 " "Found entity 1: ded_mult_ks81" { } { { "db/ded_mult_ks81.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/ded_mult_ks81.tdf" 30 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821253050 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394821253050 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ded_mult_ks81 system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_1\|mult_add_75u2:auto_generated\|ded_mult_ks81:ded_mult1 " "Elaborating entity \"ded_mult_ks81\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_1\|mult_add_75u2:auto_generated\|ded_mult_ks81:ded_mult1\"" { } { { "db/mult_add_75u2.tdf" "ded_mult1" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/mult_add_75u2.tdf" 33 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821253050 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/dffpipe_93c.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/dffpipe_93c.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 dffpipe_93c " "Found entity 1: dffpipe_93c" { } { { "db/dffpipe_93c.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/dffpipe_93c.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821253065 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394821253065 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dffpipe_93c system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_1\|mult_add_75u2:auto_generated\|ded_mult_ks81:ded_mult1\|dffpipe_93c:pre_result " "Elaborating entity \"dffpipe_93c\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_1\|mult_add_75u2:auto_generated\|ded_mult_ks81:ded_mult1\|dffpipe_93c:pre_result\"" { } { { "db/ded_mult_ks81.tdf" "pre_result" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/ded_mult_ks81.tdf" 50 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821253065 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altmult_add system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_2 " "Elaborating entity \"altmult_add\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_2\"" { } { { "system/synthesis/submodules/system_cpu_mult_cell.v" "the_altmult_add_part_2" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu_mult_cell.v" 93 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821253097 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_2 " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_2\"" { } { { "system/synthesis/submodules/system_cpu_mult_cell.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu_mult_cell.v" 93 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1394821253112 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_2 " "Instantiated megafunction \"system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_2\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "addnsub_multiplier_pipeline_aclr1 ACLR0 " "Parameter \"addnsub_multiplier_pipeline_aclr1\" = \"ACLR0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821253112 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "addnsub_multiplier_pipeline_register1 CLOCK0 " "Parameter \"addnsub_multiplier_pipeline_register1\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821253112 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "addnsub_multiplier_register1 UNREGISTERED " "Parameter \"addnsub_multiplier_register1\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821253112 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "dedicated_multiplier_circuitry YES " "Parameter \"dedicated_multiplier_circuitry\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821253112 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "input_register_a0 UNREGISTERED " "Parameter \"input_register_a0\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821253112 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "input_register_b0 UNREGISTERED " "Parameter \"input_register_b0\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821253112 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "input_source_a0 DATAA " "Parameter \"input_source_a0\" = \"DATAA\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821253112 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "input_source_b0 DATAB " "Parameter \"input_source_b0\" = \"DATAB\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821253112 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family CYCLONEIVE " "Parameter \"intended_device_family\" = \"CYCLONEIVE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821253112 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altmult_add " "Parameter \"lpm_type\" = \"altmult_add\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821253112 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "multiplier1_direction ADD " "Parameter \"multiplier1_direction\" = \"ADD\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821253112 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "multiplier_aclr0 ACLR0 " "Parameter \"multiplier_aclr0\" = \"ACLR0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821253112 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "multiplier_register0 CLOCK0 " "Parameter \"multiplier_register0\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821253112 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "number_of_multipliers 1 " "Parameter \"number_of_multipliers\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821253112 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_register UNREGISTERED " "Parameter \"output_register\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821253112 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_addnsub1 PORT_UNUSED " "Parameter \"port_addnsub1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821253112 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_addnsub3 PORT_UNUSED " "Parameter \"port_addnsub3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821253112 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_signa PORT_UNUSED " "Parameter \"port_signa\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821253112 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_signb PORT_UNUSED " "Parameter \"port_signb\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821253112 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "representation_a UNSIGNED " "Parameter \"representation_a\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821253112 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "representation_b UNSIGNED " "Parameter \"representation_b\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821253112 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_pipeline_aclr_a ACLR0 " "Parameter \"signed_pipeline_aclr_a\" = \"ACLR0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821253112 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_pipeline_aclr_b ACLR0 " "Parameter \"signed_pipeline_aclr_b\" = \"ACLR0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821253112 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_pipeline_register_a CLOCK0 " "Parameter \"signed_pipeline_register_a\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821253112 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_pipeline_register_b CLOCK0 " "Parameter \"signed_pipeline_register_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821253112 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_register_a UNREGISTERED " "Parameter \"signed_register_a\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821253112 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_register_b UNREGISTERED " "Parameter \"signed_register_b\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821253112 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 16 " "Parameter \"width_a\" = \"16\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821253112 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 16 " "Parameter \"width_b\" = \"16\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821253112 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_result 16 " "Parameter \"width_result\" = \"16\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821253112 ""} } { { "system/synthesis/submodules/system_cpu_mult_cell.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu_mult_cell.v" 93 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1394821253112 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mult_add_95u2.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mult_add_95u2.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mult_add_95u2 " "Found entity 1: mult_add_95u2" { } { { "db/mult_add_95u2.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/mult_add_95u2.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821253159 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394821253159 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mult_add_95u2 system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_2\|mult_add_95u2:auto_generated " "Elaborating entity \"mult_add_95u2\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_2\|mult_add_95u2:auto_generated\"" { } { { "altmult_add.tdf" "auto_generated" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altmult_add.tdf" 594 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821253175 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_oci system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci " "Elaborating entity \"system_cpu_nios2_oci\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_nios2_oci" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 10089 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821253190 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_oci_debug system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_debug:the_system_cpu_nios2_oci_debug " "Elaborating entity \"system_cpu_nios2_oci_debug\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_debug:the_system_cpu_nios2_oci_debug\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_nios2_oci_debug" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3444 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821253206 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_ocimem system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem " "Elaborating entity \"system_cpu_nios2_ocimem\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_nios2_ocimem" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3464 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821253221 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_ociram_lpm_dram_bdp_component_module system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem\|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component " "Elaborating entity \"system_cpu_ociram_lpm_dram_bdp_component_module\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem\|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component\"" { } { { "system/synthesis/submodules/system_cpu.v" "system_cpu_ociram_lpm_dram_bdp_component" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 872 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821253221 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem\|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component\|altsyncram:the_altsyncram " "Elaborating entity \"altsyncram\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem\|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_altsyncram" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 720 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821253237 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem\|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component\|altsyncram:the_altsyncram " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem\|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 720 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1394821253237 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem\|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component\|altsyncram:the_altsyncram " "Instantiated megafunction \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem\|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_a NONE " "Parameter \"address_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821253237 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_b NONE " "Parameter \"address_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821253237 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK1 " "Parameter \"address_reg_b\" = \"CLOCK1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821253237 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_aclr_a NONE " "Parameter \"indata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821253237 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_aclr_b NONE " "Parameter \"indata_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821253237 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file system_cpu_ociram_default_contents.mif " "Parameter \"init_file\" = \"system_cpu_ociram_default_contents.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821253237 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family CYCLONEIVE " "Parameter \"intended_device_family\" = \"CYCLONEIVE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821253237 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821253237 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 256 " "Parameter \"numwords_a\" = \"256\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821253237 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 256 " "Parameter \"numwords_b\" = \"256\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821253237 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode BIDIR_DUAL_PORT " "Parameter \"operation_mode\" = \"BIDIR_DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821253237 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821253237 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_b NONE " "Parameter \"outdata_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821253237 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a UNREGISTERED " "Parameter \"outdata_reg_a\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821253237 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821253237 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821253237 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports OLD_DATA " "Parameter \"read_during_write_mode_mixed_ports\" = \"OLD_DATA\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821253237 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 32 " "Parameter \"width_a\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821253237 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 32 " "Parameter \"width_b\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821253237 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 4 " "Parameter \"width_byteena_a\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821253237 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 8 " "Parameter \"widthad_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821253237 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 8 " "Parameter \"widthad_b\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821253237 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_aclr_a NONE " "Parameter \"wrcontrol_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821253237 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_aclr_b NONE " "Parameter \"wrcontrol_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821253237 ""} } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 720 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1394821253237 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_jt72.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_jt72.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_jt72 " "Found entity 1: altsyncram_jt72" { } { { "db/altsyncram_jt72.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_jt72.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821253331 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394821253331 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_jt72 system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem\|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_jt72:auto_generated " "Elaborating entity \"altsyncram_jt72\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem\|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_jt72:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821253331 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_avalon_reg system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg " "Elaborating entity \"system_cpu_nios2_avalon_reg\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_nios2_avalon_reg" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3484 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821253377 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_oci_break system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_break:the_system_cpu_nios2_oci_break " "Elaborating entity \"system_cpu_nios2_oci_break\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_break:the_system_cpu_nios2_oci_break\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_nios2_oci_break" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3515 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821253377 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_oci_xbrk system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_xbrk:the_system_cpu_nios2_oci_xbrk " "Elaborating entity \"system_cpu_nios2_oci_xbrk\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_xbrk:the_system_cpu_nios2_oci_xbrk\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_nios2_oci_xbrk" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3538 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821253393 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_oci_dbrk system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_dbrk:the_system_cpu_nios2_oci_dbrk " "Elaborating entity \"system_cpu_nios2_oci_dbrk\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_dbrk:the_system_cpu_nios2_oci_dbrk\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_nios2_oci_dbrk" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3565 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821253393 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_oci_itrace system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_itrace:the_system_cpu_nios2_oci_itrace " "Elaborating entity \"system_cpu_nios2_oci_itrace\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_itrace:the_system_cpu_nios2_oci_itrace\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_nios2_oci_itrace" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3606 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821253393 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_oci_dtrace system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_dtrace:the_system_cpu_nios2_oci_dtrace " "Elaborating entity \"system_cpu_nios2_oci_dtrace\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_dtrace:the_system_cpu_nios2_oci_dtrace\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_nios2_oci_dtrace" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3621 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821253409 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_oci_td_mode system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_dtrace:the_system_cpu_nios2_oci_dtrace\|system_cpu_nios2_oci_td_mode:system_cpu_nios2_oci_trc_ctrl_td_mode " "Elaborating entity \"system_cpu_nios2_oci_td_mode\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_dtrace:the_system_cpu_nios2_oci_dtrace\|system_cpu_nios2_oci_td_mode:system_cpu_nios2_oci_trc_ctrl_td_mode\"" { } { { "system/synthesis/submodules/system_cpu.v" "system_cpu_nios2_oci_trc_ctrl_td_mode" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 2213 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821253409 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_oci_fifo system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_fifo:the_system_cpu_nios2_oci_fifo " "Elaborating entity \"system_cpu_nios2_oci_fifo\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_fifo:the_system_cpu_nios2_oci_fifo\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_nios2_oci_fifo" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3640 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821253424 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_oci_compute_tm_count system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_fifo:the_system_cpu_nios2_oci_fifo\|system_cpu_nios2_oci_compute_tm_count:system_cpu_nios2_oci_compute_tm_count_tm_count " "Elaborating entity \"system_cpu_nios2_oci_compute_tm_count\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_fifo:the_system_cpu_nios2_oci_fifo\|system_cpu_nios2_oci_compute_tm_count:system_cpu_nios2_oci_compute_tm_count_tm_count\"" { } { { "system/synthesis/submodules/system_cpu.v" "system_cpu_nios2_oci_compute_tm_count_tm_count" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 2545 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821254423 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_oci_fifowp_inc system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_fifo:the_system_cpu_nios2_oci_fifo\|system_cpu_nios2_oci_fifowp_inc:system_cpu_nios2_oci_fifowp_inc_fifowp " "Elaborating entity \"system_cpu_nios2_oci_fifowp_inc\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_fifo:the_system_cpu_nios2_oci_fifo\|system_cpu_nios2_oci_fifowp_inc:system_cpu_nios2_oci_fifowp_inc_fifowp\"" { } { { "system/synthesis/submodules/system_cpu.v" "system_cpu_nios2_oci_fifowp_inc_fifowp" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 2555 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821254438 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_oci_fifocount_inc system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_fifo:the_system_cpu_nios2_oci_fifo\|system_cpu_nios2_oci_fifocount_inc:system_cpu_nios2_oci_fifocount_inc_fifocount " "Elaborating entity \"system_cpu_nios2_oci_fifocount_inc\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_fifo:the_system_cpu_nios2_oci_fifo\|system_cpu_nios2_oci_fifocount_inc:system_cpu_nios2_oci_fifocount_inc_fifocount\"" { } { { "system/synthesis/submodules/system_cpu.v" "system_cpu_nios2_oci_fifocount_inc_fifocount" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 2565 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821254438 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_oci_test_bench system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_fifo:the_system_cpu_nios2_oci_fifo\|system_cpu_oci_test_bench:the_system_cpu_oci_test_bench " "Elaborating entity \"system_cpu_oci_test_bench\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_fifo:the_system_cpu_nios2_oci_fifo\|system_cpu_oci_test_bench:the_system_cpu_oci_test_bench\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_oci_test_bench" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 2574 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821254438 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_oci_pib system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_pib:the_system_cpu_nios2_oci_pib " "Elaborating entity \"system_cpu_nios2_oci_pib\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_pib:the_system_cpu_nios2_oci_pib\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_nios2_oci_pib" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3650 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821254438 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_oci_im system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im " "Elaborating entity \"system_cpu_nios2_oci_im\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_nios2_oci_im" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821254454 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_traceram_lpm_dram_bdp_component_module system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component " "Elaborating entity \"system_cpu_traceram_lpm_dram_bdp_component_module\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\"" { } { { "system/synthesis/submodules/system_cpu.v" "system_cpu_traceram_lpm_dram_bdp_component" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821254469 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram " "Elaborating entity \"altsyncram\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_altsyncram" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821254469 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1394821254485 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram " "Instantiated megafunction \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_a NONE " "Parameter \"address_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821254485 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_b NONE " "Parameter \"address_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821254485 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK1 " "Parameter \"address_reg_b\" = \"CLOCK1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821254485 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_aclr_a NONE " "Parameter \"indata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821254485 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_aclr_b NONE " "Parameter \"indata_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821254485 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file UNUSED " "Parameter \"init_file\" = \"UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821254485 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family CYCLONEIVE " "Parameter \"intended_device_family\" = \"CYCLONEIVE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821254485 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821254485 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 128 " "Parameter \"numwords_a\" = \"128\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821254485 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 128 " "Parameter \"numwords_b\" = \"128\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821254485 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode BIDIR_DUAL_PORT " "Parameter \"operation_mode\" = \"BIDIR_DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821254485 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821254485 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_b NONE " "Parameter \"outdata_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821254485 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a UNREGISTERED " "Parameter \"outdata_reg_a\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821254485 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821254485 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821254485 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports OLD_DATA " "Parameter \"read_during_write_mode_mixed_ports\" = \"OLD_DATA\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821254485 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 36 " "Parameter \"width_a\" = \"36\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821254485 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 36 " "Parameter \"width_b\" = \"36\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821254485 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 7 " "Parameter \"widthad_a\" = \"7\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821254485 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 7 " "Parameter \"widthad_b\" = \"7\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821254485 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_aclr_a NONE " "Parameter \"wrcontrol_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821254485 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_aclr_b NONE " "Parameter \"wrcontrol_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821254485 ""} } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1394821254485 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_0a02.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_0a02.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_0a02 " "Found entity 1: altsyncram_0a02" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_0a02.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821254579 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394821254579 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_0a02 system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated " "Elaborating entity \"altsyncram_0a02\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821254579 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_jtag_debug_module_wrapper system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper " "Elaborating entity \"system_cpu_jtag_debug_module_wrapper\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_jtag_debug_module_wrapper" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3714 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821254610 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_jtag_debug_module_tck system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck " "Elaborating entity \"system_cpu_jtag_debug_module_tck\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck\"" { } { { "system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v" "the_system_cpu_jtag_debug_module_tck" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v" 165 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821254610 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_std_synchronizer system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck\|altera_std_synchronizer:the_altera_std_synchronizer " "Elaborating entity \"altera_std_synchronizer\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck\|altera_std_synchronizer:the_altera_std_synchronizer\"" { } { { "system/synthesis/submodules/system_cpu_jtag_debug_module_tck.v" "the_altera_std_synchronizer" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu_jtag_debug_module_tck.v" 202 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821254657 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck\|altera_std_synchronizer:the_altera_std_synchronizer " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck\|altera_std_synchronizer:the_altera_std_synchronizer\"" { } { { "system/synthesis/submodules/system_cpu_jtag_debug_module_tck.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu_jtag_debug_module_tck.v" 202 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1394821254672 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck\|altera_std_synchronizer:the_altera_std_synchronizer " "Instantiated megafunction \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck\|altera_std_synchronizer:the_altera_std_synchronizer\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "depth 2 " "Parameter \"depth\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821254672 ""} } { { "system/synthesis/submodules/system_cpu_jtag_debug_module_tck.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu_jtag_debug_module_tck.v" 202 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1394821254672 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_jtag_debug_module_sysclk system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk " "Elaborating entity \"system_cpu_jtag_debug_module_sysclk\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk\"" { } { { "system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v" "the_system_cpu_jtag_debug_module_sysclk" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v" 188 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821254672 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sld_virtual_jtag_basic system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy " "Elaborating entity \"sld_virtual_jtag_basic\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy\"" { } { { "system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v" "system_cpu_jtag_debug_module_phy" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v" 218 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821254703 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy\"" { } { { "system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v" 218 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1394821254719 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy " "Instantiated megafunction \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_auto_instance_index YES " "Parameter \"sld_auto_instance_index\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821254719 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_instance_index 0 " "Parameter \"sld_instance_index\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821254719 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_ir_width 2 " "Parameter \"sld_ir_width\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821254719 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_mfg_id 70 " "Parameter \"sld_mfg_id\" = \"70\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821254719 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_sim_action " "Parameter \"sld_sim_action\" = \"\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821254719 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_sim_n_scan 0 " "Parameter \"sld_sim_n_scan\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821254719 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_sim_total_length 0 " "Parameter \"sld_sim_total_length\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821254719 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_type_id 34 " "Parameter \"sld_type_id\" = \"34\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821254719 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_version 3 " "Parameter \"sld_version\" = \"3\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821254719 ""} } { { "system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v" 218 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1394821254719 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sld_virtual_jtag_impl system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy\|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst " "Elaborating entity \"sld_virtual_jtag_impl\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy\|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst\"" { } { { "sld_virtual_jtag_basic.v" "sld_virtual_jtag_impl_inst" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/sld_virtual_jtag_basic.v" 151 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821254719 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy\|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy\|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst\", which is child of megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy\"" { } { { "sld_virtual_jtag_basic.v" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/sld_virtual_jtag_basic.v" 151 0 0 } } { "system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v" 218 0 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0 -1 1394821254735 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_sysid system:inst_cpu\|system_sysid:sysid " "Elaborating entity \"system_sysid\" for hierarchy \"system:inst_cpu\|system_sysid:sysid\"" { } { { "system/synthesis/system.v" "sysid" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 795 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821254735 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_sdram system:inst_cpu\|system_sdram:sdram " "Elaborating entity \"system_sdram\" for hierarchy \"system:inst_cpu\|system_sdram:sdram\"" { } { { "system/synthesis/system.v" "sdram" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 818 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821254735 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_sdram_input_efifo_module system:inst_cpu\|system_sdram:sdram\|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module " "Elaborating entity \"system_sdram_input_efifo_module\" for hierarchy \"system:inst_cpu\|system_sdram:sdram\|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module\"" { } { { "system/synthesis/submodules/system_sdram.v" "the_system_sdram_input_efifo_module" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_sdram.v" 296 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821254750 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_sys_clk_timer system:inst_cpu\|system_sys_clk_timer:sys_clk_timer " "Elaborating entity \"system_sys_clk_timer\" for hierarchy \"system:inst_cpu\|system_sys_clk_timer:sys_clk_timer\"" { } { { "system/synthesis/system.v" "sys_clk_timer" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 829 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821254766 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_uart_0 system:inst_cpu\|system_uart_0:uart_0 " "Elaborating entity \"system_uart_0\" for hierarchy \"system:inst_cpu\|system_uart_0:uart_0\"" { } { { "system/synthesis/system.v" "uart_0" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 846 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821254781 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_uart_0_tx system:inst_cpu\|system_uart_0:uart_0\|system_uart_0_tx:the_system_uart_0_tx " "Elaborating entity \"system_uart_0_tx\" for hierarchy \"system:inst_cpu\|system_uart_0:uart_0\|system_uart_0_tx:the_system_uart_0_tx\"" { } { { "system/synthesis/submodules/system_uart_0.v" "the_system_uart_0_tx" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_uart_0.v" 1079 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821254797 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_uart_0_rx system:inst_cpu\|system_uart_0:uart_0\|system_uart_0_rx:the_system_uart_0_rx " "Elaborating entity \"system_uart_0_rx\" for hierarchy \"system:inst_cpu\|system_uart_0:uart_0\|system_uart_0_rx:the_system_uart_0_rx\"" { } { { "system/synthesis/submodules/system_uart_0.v" "the_system_uart_0_rx" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_uart_0.v" 1097 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821254813 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_uart_0_rx_stimulus_source system:inst_cpu\|system_uart_0:uart_0\|system_uart_0_rx:the_system_uart_0_rx\|system_uart_0_rx_stimulus_source:the_system_uart_0_rx_stimulus_source " "Elaborating entity \"system_uart_0_rx_stimulus_source\" for hierarchy \"system:inst_cpu\|system_uart_0:uart_0\|system_uart_0_rx:the_system_uart_0_rx\|system_uart_0_rx_stimulus_source:the_system_uart_0_rx_stimulus_source\"" { } { { "system/synthesis/submodules/system_uart_0.v" "the_system_uart_0_rx_stimulus_source" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_uart_0.v" 569 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821254828 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_uart_0_regs system:inst_cpu\|system_uart_0:uart_0\|system_uart_0_regs:the_system_uart_0_regs " "Elaborating entity \"system_uart_0_regs\" for hierarchy \"system:inst_cpu\|system_uart_0:uart_0\|system_uart_0_regs:the_system_uart_0_regs\"" { } { { "system/synthesis/submodules/system_uart_0.v" "the_system_uart_0_regs" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_uart_0.v" 1128 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821254844 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_pio_led system:inst_cpu\|system_pio_led:pio_led " "Elaborating entity \"system_pio_led\" for hierarchy \"system:inst_cpu\|system_pio_led:pio_led\"" { } { { "system/synthesis/system.v" "pio_led" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 857 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821254844 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_pio_key system:inst_cpu\|system_pio_key:pio_key " "Elaborating entity \"system_pio_key\" for hierarchy \"system:inst_cpu\|system_pio_key:pio_key\"" { } { { "system/synthesis/system.v" "pio_key" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 865 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821254859 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_pio_sw system:inst_cpu\|system_pio_sw:pio_sw " "Elaborating entity \"system_pio_sw\" for hierarchy \"system:inst_cpu\|system_pio_sw:pio_sw\"" { } { { "system/synthesis/system.v" "pio_sw" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 873 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821254859 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_jtag_uart_0 system:inst_cpu\|system_jtag_uart_0:jtag_uart_0 " "Elaborating entity \"system_jtag_uart_0\" for hierarchy \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\"" { } { { "system/synthesis/system.v" "jtag_uart_0" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 886 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821254875 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_jtag_uart_0_scfifo_w system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w " "Elaborating entity \"system_jtag_uart_0_scfifo_w\" for hierarchy \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\"" { } { { "system/synthesis/submodules/system_jtag_uart_0.v" "the_system_jtag_uart_0_scfifo_w" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_jtag_uart_0.v" 625 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821254875 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scfifo system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo " "Elaborating entity \"scfifo\" for hierarchy \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\"" { } { { "system/synthesis/submodules/system_jtag_uart_0.v" "wfifo" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_jtag_uart_0.v" 183 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821255015 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo " "Elaborated megafunction instantiation \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\"" { } { { "system/synthesis/submodules/system_jtag_uart_0.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_jtag_uart_0.v" 183 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1394821255015 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo " "Instantiated megafunction \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint RAM_BLOCK_TYPE=AUTO " "Parameter \"lpm_hint\" = \"RAM_BLOCK_TYPE=AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821255015 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_numwords 64 " "Parameter \"lpm_numwords\" = \"64\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821255015 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_showahead OFF " "Parameter \"lpm_showahead\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821255015 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type scfifo " "Parameter \"lpm_type\" = \"scfifo\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821255015 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 8 " "Parameter \"lpm_width\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821255015 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widthu 6 " "Parameter \"lpm_widthu\" = \"6\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821255015 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "overflow_checking OFF " "Parameter \"overflow_checking\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821255015 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "underflow_checking OFF " "Parameter \"underflow_checking\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821255015 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "use_eab ON " "Parameter \"use_eab\" = \"ON\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821255015 ""} } { { "system/synthesis/submodules/system_jtag_uart_0.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_jtag_uart_0.v" 183 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1394821255015 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/scfifo_jr21.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/scfifo_jr21.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 scfifo_jr21 " "Found entity 1: scfifo_jr21" { } { { "db/scfifo_jr21.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/scfifo_jr21.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821255093 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394821255093 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scfifo_jr21 system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated " "Elaborating entity \"scfifo_jr21\" for hierarchy \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\"" { } { { "scfifo.tdf" "auto_generated" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/scfifo.tdf" 296 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821255109 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_dpfifo_q131.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/a_dpfifo_q131.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_dpfifo_q131 " "Found entity 1: a_dpfifo_q131" { } { { "db/a_dpfifo_q131.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/a_dpfifo_q131.tdf" 28 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821255125 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394821255125 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_dpfifo_q131 system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo " "Elaborating entity \"a_dpfifo_q131\" for hierarchy \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\"" { } { { "db/scfifo_jr21.tdf" "dpfifo" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/scfifo_jr21.tdf" 37 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821255125 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_fefifo_7cf.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/a_fefifo_7cf.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_fefifo_7cf " "Found entity 1: a_fefifo_7cf" { } { { "db/a_fefifo_7cf.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/a_fefifo_7cf.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821255140 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394821255140 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_fefifo_7cf system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|a_fefifo_7cf:fifo_state " "Elaborating entity \"a_fefifo_7cf\" for hierarchy \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|a_fefifo_7cf:fifo_state\"" { } { { "db/a_dpfifo_q131.tdf" "fifo_state" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/a_dpfifo_q131.tdf" 42 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821255140 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_do7.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_do7.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_do7 " "Found entity 1: cntr_do7" { } { { "db/cntr_do7.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/cntr_do7.tdf" 25 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821255203 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394821255203 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_do7 system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|a_fefifo_7cf:fifo_state\|cntr_do7:count_usedw " "Elaborating entity \"cntr_do7\" for hierarchy \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|a_fefifo_7cf:fifo_state\|cntr_do7:count_usedw\"" { } { { "db/a_fefifo_7cf.tdf" "count_usedw" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/a_fefifo_7cf.tdf" 38 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821255203 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/dpram_nl21.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/dpram_nl21.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 dpram_nl21 " "Found entity 1: dpram_nl21" { } { { "db/dpram_nl21.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/dpram_nl21.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821255265 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394821255265 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dpram_nl21 system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|dpram_nl21:FIFOram " "Elaborating entity \"dpram_nl21\" for hierarchy \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|dpram_nl21:FIFOram\"" { } { { "db/a_dpfifo_q131.tdf" "FIFOram" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/a_dpfifo_q131.tdf" 43 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821255265 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_r1m1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_r1m1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_r1m1 " "Found entity 1: altsyncram_r1m1" { } { { "db/altsyncram_r1m1.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_r1m1.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821255343 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394821255343 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_r1m1 system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|dpram_nl21:FIFOram\|altsyncram_r1m1:altsyncram1 " "Elaborating entity \"altsyncram_r1m1\" for hierarchy \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|dpram_nl21:FIFOram\|altsyncram_r1m1:altsyncram1\"" { } { { "db/dpram_nl21.tdf" "altsyncram1" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/dpram_nl21.tdf" 36 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821255343 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_1ob.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_1ob.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_1ob " "Found entity 1: cntr_1ob" { } { { "db/cntr_1ob.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/cntr_1ob.tdf" 25 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821255405 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394821255405 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_1ob system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|cntr_1ob:rd_ptr_count " "Elaborating entity \"cntr_1ob\" for hierarchy \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|cntr_1ob:rd_ptr_count\"" { } { { "db/a_dpfifo_q131.tdf" "rd_ptr_count" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/a_dpfifo_q131.tdf" 44 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821255405 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_jtag_uart_0_scfifo_r system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r " "Elaborating entity \"system_jtag_uart_0_scfifo_r\" for hierarchy \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r\"" { } { { "system/synthesis/submodules/system_jtag_uart_0.v" "the_system_jtag_uart_0_scfifo_r" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_jtag_uart_0.v" 639 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821255421 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_jtag_atlantic system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic " "Elaborating entity \"alt_jtag_atlantic\" for hierarchy \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic\"" { } { { "system/synthesis/submodules/system_jtag_uart_0.v" "system_jtag_uart_0_alt_jtag_atlantic" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_jtag_uart_0.v" 774 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821255577 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic " "Elaborated megafunction instantiation \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic\"" { } { { "system/synthesis/submodules/system_jtag_uart_0.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_jtag_uart_0.v" 774 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1394821255577 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic " "Instantiated megafunction \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "INSTANCE_ID 0 " "Parameter \"INSTANCE_ID\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821255577 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LOG2_RXFIFO_DEPTH 6 " "Parameter \"LOG2_RXFIFO_DEPTH\" = \"6\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821255577 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LOG2_TXFIFO_DEPTH 6 " "Parameter \"LOG2_TXFIFO_DEPTH\" = \"6\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821255577 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "SLD_AUTO_INSTANCE_INDEX YES " "Parameter \"SLD_AUTO_INSTANCE_INDEX\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821255577 ""} } { { "system/synthesis/submodules/system_jtag_uart_0.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_jtag_uart_0.v" 774 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1394821255577 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_pio_motor_rst system:inst_cpu\|system_pio_motor_rst:pio_motor_rst " "Elaborating entity \"system_pio_motor_rst\" for hierarchy \"system:inst_cpu\|system_pio_motor_rst:pio_motor_rst\"" { } { { "system/synthesis/system.v" "pio_motor_rst" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 897 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821255593 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_rs232_motor system:inst_cpu\|system_rs232_motor:rs232_motor " "Elaborating entity \"system_rs232_motor\" for hierarchy \"system:inst_cpu\|system_rs232_motor:rs232_motor\"" { } { { "system/synthesis/system.v" "rs232_motor" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 912 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821255608 ""} +{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "write_data_parity system_rs232_motor.v(123) " "Verilog HDL or VHDL warning at system_rs232_motor.v(123): object \"write_data_parity\" assigned a value but never read" { } { { "system/synthesis/submodules/system_rs232_motor.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_rs232_motor.v" 123 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 -1 1394821255608 "|de0_nano_system|system:inst_cpu|system_rs232_motor:rs232_motor"} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_up_rs232_in_deserializer system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_in_deserializer:RS232_In_Deserializer " "Elaborating entity \"altera_up_rs232_in_deserializer\" for hierarchy \"system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\"" { } { { "system/synthesis/submodules/system_rs232_motor.v" "RS232_In_Deserializer" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_rs232_motor.v" 268 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821255608 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_up_rs232_counters system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_rs232_counters:RS232_In_Counters " "Elaborating entity \"altera_up_rs232_counters\" for hierarchy \"system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_rs232_counters:RS232_In_Counters\"" { } { { "system/synthesis/submodules/altera_up_rs232_in_deserializer.v" "RS232_In_Counters" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_up_rs232_in_deserializer.v" 181 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821255608 ""} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 altera_up_rs232_counters.v(124) " "Verilog HDL assignment warning at altera_up_rs232_counters.v(124): truncated value with size 32 to match size of target (14)" { } { { "system/synthesis/submodules/altera_up_rs232_counters.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_up_rs232_counters.v" 124 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 -1 1394821255624 "|de0_nano_system|system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_rs232_counters:RS232_In_Counters"} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_up_sync_fifo system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO " "Elaborating entity \"altera_up_sync_fifo\" for hierarchy \"system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\"" { } { { "system/synthesis/submodules/altera_up_rs232_in_deserializer.v" "RS232_In_FIFO" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_up_rs232_in_deserializer.v" 206 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821255624 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scfifo system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO " "Elaborating entity \"scfifo\" for hierarchy \"system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\"" { } { { "system/synthesis/submodules/altera_up_sync_fifo.v" "Sync_FIFO" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_up_sync_fifo.v" 157 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821255702 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO " "Elaborated megafunction instantiation \"system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\"" { } { { "system/synthesis/submodules/altera_up_sync_fifo.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_up_sync_fifo.v" 157 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1394821255717 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO " "Instantiated megafunction \"system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "add_ram_output_register OFF " "Parameter \"add_ram_output_register\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821255717 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone II " "Parameter \"intended_device_family\" = \"Cyclone II\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821255717 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_numwords 128 " "Parameter \"lpm_numwords\" = \"128\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821255717 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_showahead ON " "Parameter \"lpm_showahead\" = \"ON\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821255717 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type scfifo " "Parameter \"lpm_type\" = \"scfifo\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821255717 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 8 " "Parameter \"lpm_width\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821255717 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widthu 7 " "Parameter \"lpm_widthu\" = \"7\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821255717 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "overflow_checking OFF " "Parameter \"overflow_checking\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821255717 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "underflow_checking OFF " "Parameter \"underflow_checking\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821255717 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "use_eab ON " "Parameter \"use_eab\" = \"ON\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821255717 ""} } { { "system/synthesis/submodules/altera_up_sync_fifo.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_up_sync_fifo.v" 157 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1394821255717 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/scfifo_a341.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/scfifo_a341.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 scfifo_a341 " "Found entity 1: scfifo_a341" { } { { "db/scfifo_a341.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/scfifo_a341.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821255780 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394821255780 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scfifo_a341 system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated " "Elaborating entity \"scfifo_a341\" for hierarchy \"system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\"" { } { { "scfifo.tdf" "auto_generated" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/scfifo.tdf" 296 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821255780 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_dpfifo_tq31.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/a_dpfifo_tq31.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_dpfifo_tq31 " "Found entity 1: a_dpfifo_tq31" { } { { "db/a_dpfifo_tq31.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/a_dpfifo_tq31.tdf" 32 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821255795 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394821255795 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_dpfifo_tq31 system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo " "Elaborating entity \"a_dpfifo_tq31\" for hierarchy \"system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\"" { } { { "db/scfifo_a341.tdf" "dpfifo" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/scfifo_a341.tdf" 37 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821255795 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_je81.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_je81.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_je81 " "Found entity 1: altsyncram_je81" { } { { "db/altsyncram_je81.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_je81.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821255858 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394821255858 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_je81 system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|altsyncram_je81:FIFOram " "Elaborating entity \"altsyncram_je81\" for hierarchy \"system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|altsyncram_je81:FIFOram\"" { } { { "db/a_dpfifo_tq31.tdf" "FIFOram" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/a_dpfifo_tq31.tdf" 45 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821255873 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cmpr_ks8.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cmpr_ks8.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cmpr_ks8 " "Found entity 1: cmpr_ks8" { } { { "db/cmpr_ks8.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/cmpr_ks8.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821255920 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394821255920 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cmpr_ks8 system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cmpr_ks8:almost_full_comparer " "Elaborating entity \"cmpr_ks8\" for hierarchy \"system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cmpr_ks8:almost_full_comparer\"" { } { { "db/a_dpfifo_tq31.tdf" "almost_full_comparer" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/a_dpfifo_tq31.tdf" 54 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821255920 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cmpr_ks8 system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cmpr_ks8:three_comparison " "Elaborating entity \"cmpr_ks8\" for hierarchy \"system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cmpr_ks8:three_comparison\"" { } { { "db/a_dpfifo_tq31.tdf" "three_comparison" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/a_dpfifo_tq31.tdf" 55 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821255951 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_v9b.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_v9b.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_v9b " "Found entity 1: cntr_v9b" { } { { "db/cntr_v9b.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/cntr_v9b.tdf" 25 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821256029 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394821256029 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_v9b system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_v9b:rd_ptr_msb " "Elaborating entity \"cntr_v9b\" for hierarchy \"system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_v9b:rd_ptr_msb\"" { } { { "db/a_dpfifo_tq31.tdf" "rd_ptr_msb" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/a_dpfifo_tq31.tdf" 56 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821256029 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_ca7.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_ca7.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_ca7 " "Found entity 1: cntr_ca7" { } { { "db/cntr_ca7.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/cntr_ca7.tdf" 25 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821256154 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394821256154 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_ca7 system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_ca7:usedw_counter " "Elaborating entity \"cntr_ca7\" for hierarchy \"system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_ca7:usedw_counter\"" { } { { "db/a_dpfifo_tq31.tdf" "usedw_counter" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/a_dpfifo_tq31.tdf" 57 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821256170 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_0ab.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_0ab.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_0ab " "Found entity 1: cntr_0ab" { } { { "db/cntr_0ab.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/cntr_0ab.tdf" 25 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821256217 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394821256217 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_0ab system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr " "Elaborating entity \"cntr_0ab\" for hierarchy \"system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr\"" { } { { "db/a_dpfifo_tq31.tdf" "wr_ptr" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/a_dpfifo_tq31.tdf" 58 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821256217 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_up_rs232_out_serializer system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_out_serializer:RS232_Out_Serializer " "Elaborating entity \"altera_up_rs232_out_serializer\" for hierarchy \"system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_out_serializer:RS232_Out_Serializer\"" { } { { "system/synthesis/submodules/system_rs232_motor.v" "RS232_Out_Serializer" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_rs232_motor.v" 290 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821256232 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_master_translator system:inst_cpu\|altera_merlin_master_translator:cpu_instruction_master_translator " "Elaborating entity \"altera_merlin_master_translator\" for hierarchy \"system:inst_cpu\|altera_merlin_master_translator:cpu_instruction_master_translator\"" { } { { "system/synthesis/system.v" "cpu_instruction_master_translator" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 966 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821256295 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_master_translator system:inst_cpu\|altera_merlin_master_translator:cpu_data_master_translator " "Elaborating entity \"altera_merlin_master_translator\" for hierarchy \"system:inst_cpu\|altera_merlin_master_translator:cpu_data_master_translator\"" { } { { "system/synthesis/system.v" "cpu_data_master_translator" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 1020 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821256295 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_translator system:inst_cpu\|altera_merlin_slave_translator:cpu_jtag_debug_module_translator " "Elaborating entity \"altera_merlin_slave_translator\" for hierarchy \"system:inst_cpu\|altera_merlin_slave_translator:cpu_jtag_debug_module_translator\"" { } { { "system/synthesis/system.v" "cpu_jtag_debug_module_translator" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 1078 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821256310 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_translator system:inst_cpu\|altera_merlin_slave_translator:sdram_s1_translator " "Elaborating entity \"altera_merlin_slave_translator\" for hierarchy \"system:inst_cpu\|altera_merlin_slave_translator:sdram_s1_translator\"" { } { { "system/synthesis/system.v" "sdram_s1_translator" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 1136 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821256357 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_translator system:inst_cpu\|altera_merlin_slave_translator:sysid_control_slave_translator " "Elaborating entity \"altera_merlin_slave_translator\" for hierarchy \"system:inst_cpu\|altera_merlin_slave_translator:sysid_control_slave_translator\"" { } { { "system/synthesis/system.v" "sysid_control_slave_translator" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 1194 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821256357 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_translator system:inst_cpu\|altera_merlin_slave_translator:sys_clk_timer_s1_translator " "Elaborating entity \"altera_merlin_slave_translator\" for hierarchy \"system:inst_cpu\|altera_merlin_slave_translator:sys_clk_timer_s1_translator\"" { } { { "system/synthesis/system.v" "sys_clk_timer_s1_translator" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 1252 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821256373 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_translator system:inst_cpu\|altera_merlin_slave_translator:uart_0_s1_translator " "Elaborating entity \"altera_merlin_slave_translator\" for hierarchy \"system:inst_cpu\|altera_merlin_slave_translator:uart_0_s1_translator\"" { } { { "system/synthesis/system.v" "uart_0_s1_translator" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 1310 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821256388 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_translator system:inst_cpu\|altera_merlin_slave_translator:pio_led_s1_translator " "Elaborating entity \"altera_merlin_slave_translator\" for hierarchy \"system:inst_cpu\|altera_merlin_slave_translator:pio_led_s1_translator\"" { } { { "system/synthesis/system.v" "pio_led_s1_translator" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 1368 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821256388 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_translator system:inst_cpu\|altera_merlin_slave_translator:pio_key_s1_translator " "Elaborating entity \"altera_merlin_slave_translator\" for hierarchy \"system:inst_cpu\|altera_merlin_slave_translator:pio_key_s1_translator\"" { } { { "system/synthesis/system.v" "pio_key_s1_translator" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 1426 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821256404 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_translator system:inst_cpu\|altera_merlin_slave_translator:jtag_uart_0_avalon_jtag_slave_translator " "Elaborating entity \"altera_merlin_slave_translator\" for hierarchy \"system:inst_cpu\|altera_merlin_slave_translator:jtag_uart_0_avalon_jtag_slave_translator\"" { } { { "system/synthesis/system.v" "jtag_uart_0_avalon_jtag_slave_translator" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 1542 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821256435 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_translator system:inst_cpu\|altera_merlin_slave_translator:rs232_motor_avalon_rs232_slave_translator " "Elaborating entity \"altera_merlin_slave_translator\" for hierarchy \"system:inst_cpu\|altera_merlin_slave_translator:rs232_motor_avalon_rs232_slave_translator\"" { } { { "system/synthesis/system.v" "rs232_motor_avalon_rs232_slave_translator" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 1658 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821256435 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_master_agent system:inst_cpu\|altera_merlin_master_agent:cpu_instruction_master_translator_avalon_universal_master_0_agent " "Elaborating entity \"altera_merlin_master_agent\" for hierarchy \"system:inst_cpu\|altera_merlin_master_agent:cpu_instruction_master_translator_avalon_universal_master_0_agent\"" { } { { "system/synthesis/system.v" "cpu_instruction_master_translator_avalon_universal_master_0_agent" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 1730 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821256451 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_master_agent system:inst_cpu\|altera_merlin_master_agent:cpu_data_master_translator_avalon_universal_master_0_agent " "Elaborating entity \"altera_merlin_master_agent\" for hierarchy \"system:inst_cpu\|altera_merlin_master_agent:cpu_data_master_translator_avalon_universal_master_0_agent\"" { } { { "system/synthesis/system.v" "cpu_data_master_translator_avalon_universal_master_0_agent" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 1802 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821256466 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_agent system:inst_cpu\|altera_merlin_slave_agent:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent " "Elaborating entity \"altera_merlin_slave_agent\" for hierarchy \"system:inst_cpu\|altera_merlin_slave_agent:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent\"" { } { { "system/synthesis/system.v" "cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 1878 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821256482 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_burst_uncompressor system:inst_cpu\|altera_merlin_slave_agent:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent\|altera_merlin_burst_uncompressor:uncompressor " "Elaborating entity \"altera_merlin_burst_uncompressor\" for hierarchy \"system:inst_cpu\|altera_merlin_slave_agent:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent\|altera_merlin_burst_uncompressor:uncompressor\"" { } { { "system/synthesis/submodules/altera_merlin_slave_agent.sv" "uncompressor" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_slave_agent.sv" 476 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821256497 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_avalon_sc_fifo system:inst_cpu\|altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo " "Elaborating entity \"altera_avalon_sc_fifo\" for hierarchy \"system:inst_cpu\|altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo\"" { } { { "system/synthesis/system.v" "cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 1919 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821256544 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_agent system:inst_cpu\|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent " "Elaborating entity \"altera_merlin_slave_agent\" for hierarchy \"system:inst_cpu\|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent\"" { } { { "system/synthesis/system.v" "sdram_s1_translator_avalon_universal_slave_0_agent" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 1995 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821256560 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_burst_uncompressor system:inst_cpu\|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent\|altera_merlin_burst_uncompressor:uncompressor " "Elaborating entity \"altera_merlin_burst_uncompressor\" for hierarchy \"system:inst_cpu\|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent\|altera_merlin_burst_uncompressor:uncompressor\"" { } { { "system/synthesis/submodules/altera_merlin_slave_agent.sv" "uncompressor" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_slave_agent.sv" 476 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821256575 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_avalon_sc_fifo system:inst_cpu\|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo " "Elaborating entity \"altera_avalon_sc_fifo\" for hierarchy \"system:inst_cpu\|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo\"" { } { { "system/synthesis/system.v" "sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 2036 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821256591 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_addr_router system:inst_cpu\|system_addr_router:addr_router " "Elaborating entity \"system_addr_router\" for hierarchy \"system:inst_cpu\|system_addr_router:addr_router\"" { } { { "system/synthesis/system.v" "addr_router" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 3105 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821256685 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_addr_router_default_decode system:inst_cpu\|system_addr_router:addr_router\|system_addr_router_default_decode:the_default_decode " "Elaborating entity \"system_addr_router_default_decode\" for hierarchy \"system:inst_cpu\|system_addr_router:addr_router\|system_addr_router_default_decode:the_default_decode\"" { } { { "system/synthesis/submodules/system_addr_router.sv" "the_default_decode" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_addr_router.sv" 140 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821256700 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_addr_router_001 system:inst_cpu\|system_addr_router_001:addr_router_001 " "Elaborating entity \"system_addr_router_001\" for hierarchy \"system:inst_cpu\|system_addr_router_001:addr_router_001\"" { } { { "system/synthesis/system.v" "addr_router_001" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 3121 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821256716 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_addr_router_001_default_decode system:inst_cpu\|system_addr_router_001:addr_router_001\|system_addr_router_001_default_decode:the_default_decode " "Elaborating entity \"system_addr_router_001_default_decode\" for hierarchy \"system:inst_cpu\|system_addr_router_001:addr_router_001\|system_addr_router_001_default_decode:the_default_decode\"" { } { { "system/synthesis/submodules/system_addr_router_001.sv" "the_default_decode" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_addr_router_001.sv" 149 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821256731 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_id_router system:inst_cpu\|system_id_router:id_router " "Elaborating entity \"system_id_router\" for hierarchy \"system:inst_cpu\|system_id_router:id_router\"" { } { { "system/synthesis/system.v" "id_router" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 3137 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821256731 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_id_router_default_decode system:inst_cpu\|system_id_router:id_router\|system_id_router_default_decode:the_default_decode " "Elaborating entity \"system_id_router_default_decode\" for hierarchy \"system:inst_cpu\|system_id_router:id_router\|system_id_router_default_decode:the_default_decode\"" { } { { "system/synthesis/submodules/system_id_router.sv" "the_default_decode" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_id_router.sv" 138 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821256747 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_id_router_001 system:inst_cpu\|system_id_router_001:id_router_001 " "Elaborating entity \"system_id_router_001\" for hierarchy \"system:inst_cpu\|system_id_router_001:id_router_001\"" { } { { "system/synthesis/system.v" "id_router_001" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 3153 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821256747 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_id_router_001_default_decode system:inst_cpu\|system_id_router_001:id_router_001\|system_id_router_001_default_decode:the_default_decode " "Elaborating entity \"system_id_router_001_default_decode\" for hierarchy \"system:inst_cpu\|system_id_router_001:id_router_001\|system_id_router_001_default_decode:the_default_decode\"" { } { { "system/synthesis/submodules/system_id_router_001.sv" "the_default_decode" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_id_router_001.sv" 138 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821256747 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_id_router_002 system:inst_cpu\|system_id_router_002:id_router_002 " "Elaborating entity \"system_id_router_002\" for hierarchy \"system:inst_cpu\|system_id_router_002:id_router_002\"" { } { { "system/synthesis/system.v" "id_router_002" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 3169 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821256763 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_id_router_002_default_decode system:inst_cpu\|system_id_router_002:id_router_002\|system_id_router_002_default_decode:the_default_decode " "Elaborating entity \"system_id_router_002_default_decode\" for hierarchy \"system:inst_cpu\|system_id_router_002:id_router_002\|system_id_router_002_default_decode:the_default_decode\"" { } { { "system/synthesis/submodules/system_id_router_002.sv" "the_default_decode" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_id_router_002.sv" 138 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821256763 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_traffic_limiter system:inst_cpu\|altera_merlin_traffic_limiter:limiter " "Elaborating entity \"altera_merlin_traffic_limiter\" for hierarchy \"system:inst_cpu\|altera_merlin_traffic_limiter:limiter\"" { } { { "system/synthesis/system.v" "limiter" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 3342 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821256794 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_burst_adapter system:inst_cpu\|altera_merlin_burst_adapter:burst_adapter " "Elaborating entity \"altera_merlin_burst_adapter\" for hierarchy \"system:inst_cpu\|altera_merlin_burst_adapter:burst_adapter\"" { } { { "system/synthesis/system.v" "burst_adapter" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 3435 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821256825 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_burst_adapter_uncompressed_only system:inst_cpu\|altera_merlin_burst_adapter:burst_adapter\|altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba " "Elaborating entity \"altera_merlin_burst_adapter_uncompressed_only\" for hierarchy \"system:inst_cpu\|altera_merlin_burst_adapter:burst_adapter\|altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba\"" { } { { "system/synthesis/submodules/altera_merlin_burst_adapter.sv" "altera_merlin_burst_adapter_uncompressed_only.the_ba" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_burst_adapter.sv" 397 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821256856 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_reset_controller system:inst_cpu\|altera_reset_controller:rst_controller " "Elaborating entity \"altera_reset_controller\" for hierarchy \"system:inst_cpu\|altera_reset_controller:rst_controller\"" { } { { "system/synthesis/system.v" "rst_controller" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 3460 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821256872 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_reset_synchronizer system:inst_cpu\|altera_reset_controller:rst_controller\|altera_reset_synchronizer:alt_rst_sync_uq1 " "Elaborating entity \"altera_reset_synchronizer\" for hierarchy \"system:inst_cpu\|altera_reset_controller:rst_controller\|altera_reset_synchronizer:alt_rst_sync_uq1\"" { } { { "system/synthesis/submodules/altera_reset_controller.v" "alt_rst_sync_uq1" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_reset_controller.v" 105 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821256887 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cmd_xbar_demux system:inst_cpu\|system_cmd_xbar_demux:cmd_xbar_demux " "Elaborating entity \"system_cmd_xbar_demux\" for hierarchy \"system:inst_cpu\|system_cmd_xbar_demux:cmd_xbar_demux\"" { } { { "system/synthesis/system.v" "cmd_xbar_demux" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 3483 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821256903 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cmd_xbar_demux_001 system:inst_cpu\|system_cmd_xbar_demux_001:cmd_xbar_demux_001 " "Elaborating entity \"system_cmd_xbar_demux_001\" for hierarchy \"system:inst_cpu\|system_cmd_xbar_demux_001:cmd_xbar_demux_001\"" { } { { "system/synthesis/system.v" "cmd_xbar_demux_001" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 3560 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821256919 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cmd_xbar_mux system:inst_cpu\|system_cmd_xbar_mux:cmd_xbar_mux " "Elaborating entity \"system_cmd_xbar_mux\" for hierarchy \"system:inst_cpu\|system_cmd_xbar_mux:cmd_xbar_mux\"" { } { { "system/synthesis/system.v" "cmd_xbar_mux" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 3583 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821256934 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arbitrator system:inst_cpu\|system_cmd_xbar_mux:cmd_xbar_mux\|altera_merlin_arbitrator:arb " "Elaborating entity \"altera_merlin_arbitrator\" for hierarchy \"system:inst_cpu\|system_cmd_xbar_mux:cmd_xbar_mux\|altera_merlin_arbitrator:arb\"" { } { { "system/synthesis/submodules/system_cmd_xbar_mux.sv" "arb" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cmd_xbar_mux.sv" 273 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821256965 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arb_adder system:inst_cpu\|system_cmd_xbar_mux:cmd_xbar_mux\|altera_merlin_arbitrator:arb\|altera_merlin_arb_adder:adder " "Elaborating entity \"altera_merlin_arb_adder\" for hierarchy \"system:inst_cpu\|system_cmd_xbar_mux:cmd_xbar_mux\|altera_merlin_arbitrator:arb\|altera_merlin_arb_adder:adder\"" { } { { "system/synthesis/submodules/altera_merlin_arbitrator.sv" "adder" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_arbitrator.sv" 169 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821256997 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_rsp_xbar_demux system:inst_cpu\|system_rsp_xbar_demux:rsp_xbar_demux " "Elaborating entity \"system_rsp_xbar_demux\" for hierarchy \"system:inst_cpu\|system_rsp_xbar_demux:rsp_xbar_demux\"" { } { { "system/synthesis/system.v" "rsp_xbar_demux" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 3629 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821257028 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_rsp_xbar_demux_002 system:inst_cpu\|system_rsp_xbar_demux_002:rsp_xbar_demux_002 " "Elaborating entity \"system_rsp_xbar_demux_002\" for hierarchy \"system:inst_cpu\|system_rsp_xbar_demux_002:rsp_xbar_demux_002\"" { } { { "system/synthesis/system.v" "rsp_xbar_demux_002" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 3669 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821257043 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_rsp_xbar_mux system:inst_cpu\|system_rsp_xbar_mux:rsp_xbar_mux " "Elaborating entity \"system_rsp_xbar_mux\" for hierarchy \"system:inst_cpu\|system_rsp_xbar_mux:rsp_xbar_mux\"" { } { { "system/synthesis/system.v" "rsp_xbar_mux" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 3828 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821257059 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arbitrator system:inst_cpu\|system_rsp_xbar_mux:rsp_xbar_mux\|altera_merlin_arbitrator:arb " "Elaborating entity \"altera_merlin_arbitrator\" for hierarchy \"system:inst_cpu\|system_rsp_xbar_mux:rsp_xbar_mux\|altera_merlin_arbitrator:arb\"" { } { { "system/synthesis/submodules/system_rsp_xbar_mux.sv" "arb" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_rsp_xbar_mux.sv" 296 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821257075 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_rsp_xbar_mux_001 system:inst_cpu\|system_rsp_xbar_mux_001:rsp_xbar_mux_001 " "Elaborating entity \"system_rsp_xbar_mux_001\" for hierarchy \"system:inst_cpu\|system_rsp_xbar_mux_001:rsp_xbar_mux_001\"" { } { { "system/synthesis/system.v" "rsp_xbar_mux_001" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 3905 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821257090 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arbitrator system:inst_cpu\|system_rsp_xbar_mux_001:rsp_xbar_mux_001\|altera_merlin_arbitrator:arb " "Elaborating entity \"altera_merlin_arbitrator\" for hierarchy \"system:inst_cpu\|system_rsp_xbar_mux_001:rsp_xbar_mux_001\|altera_merlin_arbitrator:arb\"" { } { { "system/synthesis/submodules/system_rsp_xbar_mux_001.sv" "arb" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_rsp_xbar_mux_001.sv" 440 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821257121 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arb_adder system:inst_cpu\|system_rsp_xbar_mux_001:rsp_xbar_mux_001\|altera_merlin_arbitrator:arb\|altera_merlin_arb_adder:adder " "Elaborating entity \"altera_merlin_arb_adder\" for hierarchy \"system:inst_cpu\|system_rsp_xbar_mux_001:rsp_xbar_mux_001\|altera_merlin_arbitrator:arb\|altera_merlin_arb_adder:adder\"" { } { { "system/synthesis/submodules/altera_merlin_arbitrator.sv" "adder" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_arbitrator.sv" 169 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821257137 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_width_adapter system:inst_cpu\|altera_merlin_width_adapter:width_adapter " "Elaborating entity \"altera_merlin_width_adapter\" for hierarchy \"system:inst_cpu\|altera_merlin_width_adapter:width_adapter\"" { } { { "system/synthesis/system.v" "width_adapter" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 3962 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821257231 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_width_adapter system:inst_cpu\|altera_merlin_width_adapter:width_adapter_001 " "Elaborating entity \"altera_merlin_width_adapter\" for hierarchy \"system:inst_cpu\|altera_merlin_width_adapter:width_adapter_001\"" { } { { "system/synthesis/system.v" "width_adapter_001" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 4019 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821257262 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_irq_mapper system:inst_cpu\|system_irq_mapper:irq_mapper " "Elaborating entity \"system_irq_mapper\" for hierarchy \"system:inst_cpu\|system_irq_mapper:irq_mapper\"" { } { { "system/synthesis/system.v" "irq_mapper" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 4029 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1394821257262 ""} +{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "address_b system_cpu_traceram_lpm_dram_bdp_component 17 7 " "Port \"address_b\" on the entity instantiation of \"system_cpu_traceram_lpm_dram_bdp_component\" is connected to a signal of width 17. The formal width of the signal in the module is 7. The extra bits will be ignored." { } { { "system/synthesis/submodules/system_cpu.v" "system_cpu_traceram_lpm_dram_bdp_component" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } } 0 12020 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. The extra bits will be ignored." 0 0 "" 0 -1 1394821258853 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component"} +{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "jdo the_system_cpu_nios2_oci_itrace 38 16 " "Port \"jdo\" on the entity instantiation of \"the_system_cpu_nios2_oci_itrace\" is connected to a signal of width 38. The formal width of the signal in the module is 16. The extra bits will be ignored." { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_nios2_oci_itrace" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3606 0 0 } } } 0 12020 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. The extra bits will be ignored." 0 0 "" 0 -1 1394821258869 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_itrace:the_system_cpu_nios2_oci_itrace"} +{ "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_HDR" "" "Synthesized away the following node(s):" { { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_SUB_HDR" "RAM " "Synthesized away the following RAM node(s):" { { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[0\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[0\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_0a02.tdf" 43 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 10089 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 788 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 164 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1394821260179 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a0"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[1\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[1\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_0a02.tdf" 77 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 10089 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 788 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 164 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1394821260179 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a1"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[2\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[2\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_0a02.tdf" 111 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 10089 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 788 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 164 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1394821260179 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a2"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[3\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[3\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_0a02.tdf" 145 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 10089 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 788 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 164 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1394821260179 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a3"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[4\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[4\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_0a02.tdf" 179 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 10089 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 788 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 164 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1394821260179 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a4"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[5\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[5\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_0a02.tdf" 213 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 10089 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 788 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 164 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1394821260179 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a5"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[6\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[6\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_0a02.tdf" 247 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 10089 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 788 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 164 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1394821260179 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a6"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[7\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[7\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_0a02.tdf" 281 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 10089 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 788 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 164 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1394821260179 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a7"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[8\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[8\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_0a02.tdf" 315 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 10089 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 788 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 164 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1394821260179 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a8"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[9\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[9\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_0a02.tdf" 349 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 10089 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 788 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 164 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1394821260179 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a9"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[10\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[10\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_0a02.tdf" 383 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 10089 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 788 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 164 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1394821260179 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a10"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[11\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[11\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_0a02.tdf" 417 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 10089 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 788 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 164 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1394821260179 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a11"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[12\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[12\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_0a02.tdf" 451 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 10089 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 788 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 164 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1394821260179 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a12"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[13\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[13\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_0a02.tdf" 485 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 10089 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 788 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 164 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1394821260179 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a13"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[14\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[14\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_0a02.tdf" 519 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 10089 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 788 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 164 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1394821260179 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a14"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[15\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[15\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_0a02.tdf" 553 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 10089 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 788 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 164 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1394821260179 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a15"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[16\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[16\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_0a02.tdf" 587 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 10089 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 788 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 164 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1394821260179 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a16"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[17\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[17\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_0a02.tdf" 621 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 10089 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 788 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 164 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1394821260179 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a17"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[18\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[18\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_0a02.tdf" 655 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 10089 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 788 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 164 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1394821260179 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a18"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[19\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[19\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_0a02.tdf" 689 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 10089 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 788 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 164 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1394821260179 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a19"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[20\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[20\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_0a02.tdf" 723 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 10089 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 788 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 164 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1394821260179 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a20"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[21\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[21\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_0a02.tdf" 757 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 10089 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 788 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 164 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1394821260179 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a21"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[22\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[22\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_0a02.tdf" 791 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 10089 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 788 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 164 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1394821260179 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a22"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[23\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[23\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_0a02.tdf" 825 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 10089 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 788 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 164 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1394821260179 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a23"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[24\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[24\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_0a02.tdf" 859 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 10089 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 788 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 164 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1394821260179 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a24"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[25\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[25\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_0a02.tdf" 893 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 10089 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 788 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 164 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1394821260179 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a25"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[26\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[26\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_0a02.tdf" 927 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 10089 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 788 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 164 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1394821260179 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a26"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[27\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[27\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_0a02.tdf" 961 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 10089 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 788 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 164 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1394821260179 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a27"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[28\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[28\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_0a02.tdf" 995 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 10089 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 788 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 164 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1394821260179 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a28"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[29\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[29\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_0a02.tdf" 1029 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 10089 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 788 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 164 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1394821260179 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a29"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[30\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[30\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_0a02.tdf" 1063 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 10089 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 788 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 164 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1394821260179 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a30"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[31\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[31\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_0a02.tdf" 1097 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 10089 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 788 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 164 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1394821260179 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a31"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[32\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[32\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_0a02.tdf" 1131 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 10089 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 788 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 164 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1394821260179 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a32"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[33\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[33\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_0a02.tdf" 1165 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 10089 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 788 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 164 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1394821260179 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a33"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[34\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[34\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_0a02.tdf" 1199 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 10089 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 788 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 164 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1394821260179 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a34"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[35\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[35\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_0a02.tdf" 1233 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 10089 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v" 788 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 164 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1394821260179 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a35"} } { } 0 14285 "Synthesized away the following %1!s! node(s):" 0 0 "" 0 -1 1394821260179 ""} } { } 0 14284 "Synthesized away the following node(s):" 0 0 "" 0 -1 1394821260179 ""} +{ "Info" "ILPMS_INFERENCING_SUMMARY" "1 " "Inferred 1 megafunctions from design logic" { { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "system:inst_cpu\|system_cpu:cpu\|Add17 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"system:inst_cpu\|system_cpu:cpu\|Add17\"" { } { { "system/synthesis/submodules/system_cpu.v" "Add17" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 8729 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1 1394821265031 ""} } { } 0 278001 "Inferred %1!llu! megafunctions from design logic" 0 0 "" 0 -1 1394821265031 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_cpu:cpu\|lpm_add_sub:Add17 " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|lpm_add_sub:Add17\"" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 8729 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1394821265078 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_cpu:cpu\|lpm_add_sub:Add17 " "Instantiated megafunction \"system:inst_cpu\|system_cpu:cpu\|lpm_add_sub:Add17\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 33 " "Parameter \"LPM_WIDTH\" = \"33\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821265078 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION DEFAULT " "Parameter \"LPM_DIRECTION\" = \"DEFAULT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821265078 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821265078 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT NO " "Parameter \"ONE_INPUT_IS_CONSTANT\" = \"NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1394821265078 ""} } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 8729 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1394821265078 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_qvi.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/add_sub_qvi.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_qvi " "Found entity 1: add_sub_qvi" { } { { "db/add_sub_qvi.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/add_sub_qvi.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1394821265125 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1394821265125 ""} +{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "2 " "2 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "" 0 -1 1394821266341 ""} +{ "Warning" "WMLS_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC_HDR" "" "The following nodes have both tri-state and non-tri-state drivers" { { "Warning" "WMLS_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC" "GPIO_0\[0\] " "Inserted always-enabled tri-state buffer between \"GPIO_0\[0\]\" and its non-tri-state driver." { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 -1 0 } } } 0 13035 "Inserted always-enabled tri-state buffer between \"%1!s!\" and its non-tri-state driver." 0 0 "" 0 -1 1394821266529 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC" "GPIO_1\[12\] " "Inserted always-enabled tri-state buffer between \"GPIO_1\[12\]\" and its non-tri-state driver." { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 -1 0 } } } 0 13035 "Inserted always-enabled tri-state buffer between \"%1!s!\" and its non-tri-state driver." 0 0 "" 0 -1 1394821266529 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC" "GPIO_1\[26\] " "Inserted always-enabled tri-state buffer between \"GPIO_1\[26\]\" and its non-tri-state driver." { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 -1 0 } } } 0 13035 "Inserted always-enabled tri-state buffer between \"%1!s!\" and its non-tri-state driver." 0 0 "" 0 -1 1394821266529 ""} } { } 0 13034 "The following nodes have both tri-state and non-tri-state drivers" 0 0 "" 0 -1 1394821266529 ""} +{ "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI_HDR" "" "The following bidir pins have no drivers" { { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[2\] " "Bidir \"GPIO_0\[2\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394821266529 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[3\] " "Bidir \"GPIO_0\[3\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394821266529 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[4\] " "Bidir \"GPIO_0\[4\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394821266529 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[5\] " "Bidir \"GPIO_0\[5\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394821266529 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[6\] " "Bidir \"GPIO_0\[6\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394821266529 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[7\] " "Bidir \"GPIO_0\[7\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394821266529 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[8\] " "Bidir \"GPIO_0\[8\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394821266529 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[9\] " "Bidir \"GPIO_0\[9\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394821266529 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[10\] " "Bidir \"GPIO_0\[10\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394821266529 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[11\] " "Bidir \"GPIO_0\[11\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394821266529 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[12\] " "Bidir \"GPIO_0\[12\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394821266529 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[13\] " "Bidir \"GPIO_0\[13\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394821266529 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[14\] " "Bidir \"GPIO_0\[14\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394821266529 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[15\] " "Bidir \"GPIO_0\[15\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394821266529 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[16\] " "Bidir \"GPIO_0\[16\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394821266529 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[17\] " "Bidir \"GPIO_0\[17\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394821266529 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[18\] " "Bidir \"GPIO_0\[18\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394821266529 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[19\] " "Bidir \"GPIO_0\[19\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394821266529 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[20\] " "Bidir \"GPIO_0\[20\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394821266529 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[21\] " "Bidir \"GPIO_0\[21\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394821266529 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[22\] " "Bidir \"GPIO_0\[22\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394821266529 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[23\] " "Bidir \"GPIO_0\[23\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394821266529 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[24\] " "Bidir \"GPIO_0\[24\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394821266529 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[25\] " "Bidir \"GPIO_0\[25\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394821266529 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[26\] " "Bidir \"GPIO_0\[26\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394821266529 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[27\] " "Bidir \"GPIO_0\[27\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394821266529 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[28\] " "Bidir \"GPIO_0\[28\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394821266529 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[29\] " "Bidir \"GPIO_0\[29\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394821266529 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[30\] " "Bidir \"GPIO_0\[30\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394821266529 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[31\] " "Bidir \"GPIO_0\[31\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394821266529 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[32\] " "Bidir \"GPIO_0\[32\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394821266529 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[33\] " "Bidir \"GPIO_0\[33\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394821266529 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[0\] " "Bidir \"GPIO_1\[0\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394821266529 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[1\] " "Bidir \"GPIO_1\[1\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394821266529 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[2\] " "Bidir \"GPIO_1\[2\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394821266529 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[3\] " "Bidir \"GPIO_1\[3\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394821266529 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[4\] " "Bidir \"GPIO_1\[4\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394821266529 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[5\] " "Bidir \"GPIO_1\[5\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394821266529 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[6\] " "Bidir \"GPIO_1\[6\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394821266529 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[7\] " "Bidir \"GPIO_1\[7\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394821266529 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[8\] " "Bidir \"GPIO_1\[8\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394821266529 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[9\] " "Bidir \"GPIO_1\[9\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394821266529 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[10\] " "Bidir \"GPIO_1\[10\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394821266529 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[11\] " "Bidir \"GPIO_1\[11\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394821266529 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[13\] " "Bidir \"GPIO_1\[13\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394821266529 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[14\] " "Bidir \"GPIO_1\[14\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394821266529 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[15\] " "Bidir \"GPIO_1\[15\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394821266529 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[16\] " "Bidir \"GPIO_1\[16\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394821266529 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[17\] " "Bidir \"GPIO_1\[17\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394821266529 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[18\] " "Bidir \"GPIO_1\[18\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394821266529 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[19\] " "Bidir \"GPIO_1\[19\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394821266529 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[20\] " "Bidir \"GPIO_1\[20\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394821266529 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[21\] " "Bidir \"GPIO_1\[21\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394821266529 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[22\] " "Bidir \"GPIO_1\[22\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394821266529 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[23\] " "Bidir \"GPIO_1\[23\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394821266529 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[25\] " "Bidir \"GPIO_1\[25\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394821266529 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[27\] " "Bidir \"GPIO_1\[27\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394821266529 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[28\] " "Bidir \"GPIO_1\[28\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394821266529 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[29\] " "Bidir \"GPIO_1\[29\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394821266529 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[30\] " "Bidir \"GPIO_1\[30\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394821266529 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[31\] " "Bidir \"GPIO_1\[31\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394821266529 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[32\] " "Bidir \"GPIO_1\[32\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394821266529 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[33\] " "Bidir \"GPIO_1\[33\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394821266529 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[1\] " "Bidir \"GPIO_0\[1\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394821266529 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[24\] " "Bidir \"GPIO_1\[24\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1394821266529 ""} } { } 0 13039 "The following bidir pins have no drivers" 0 0 "" 0 -1 1394821266529 ""} +{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" { } { { "system/synthesis/submodules/system_sdram.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_sdram.v" 440 -1 0 } } { "system/synthesis/submodules/system_sdram.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_sdram.v" 354 -1 0 } } { "system/synthesis/submodules/altera_reset_synchronizer.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_reset_synchronizer.v" 62 -1 0 } } { "system/synthesis/submodules/system_sdram.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_sdram.v" 304 -1 0 } } { "system/synthesis/submodules/altera_merlin_slave_translator.sv" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_slave_translator.sv" 277 -1 0 } } { "system/synthesis/submodules/system_jtag_uart_0.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_jtag_uart_0.v" 558 -1 0 } } { "alt_jtag_atlantic.v" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/alt_jtag_atlantic.v" 291 -1 0 } } { "system/synthesis/submodules/system_uart_0.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_uart_0.v" 89 -1 0 } } { "system/synthesis/submodules/altera_merlin_arbitrator.sv" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_arbitrator.sv" 203 -1 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 5551 -1 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 5949 -1 0 } } { "system/synthesis/submodules/system_jtag_uart_0.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_jtag_uart_0.v" 603 -1 0 } } { "system/synthesis/submodules/system_uart_0.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_uart_0.v" 105 -1 0 } } { "alt_jtag_atlantic.v" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/alt_jtag_atlantic.v" 224 -1 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 5981 -1 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 9277 -1 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 9426 -1 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v" 982 -1 0 } } { "system/synthesis/submodules/system_uart_0.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_uart_0.v" 87 -1 0 } } { "system/synthesis/submodules/system_uart_0.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_uart_0.v" 88 -1 0 } } { "system/synthesis/submodules/system_uart_0.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_uart_0.v" 891 -1 0 } } { "system/synthesis/submodules/system_sys_clk_timer.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_sys_clk_timer.v" 166 -1 0 } } { "system/synthesis/submodules/system_sys_clk_timer.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_sys_clk_timer.v" 175 -1 0 } } } 0 13000 "Registers with preset signals will power-up high" 0 0 "" 0 -1 1394821266653 ""} +{ "Info" "IMLS_MLS_DEV_CLRN_SETS_REGISTERS" "" "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" { } { } 0 13003 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "" 0 -1 1394821266653 ""} +{ "Warning" "WMLS_MLS_ENABLED_OE" "" "TRI or OPNDRN buffers permanently enabled" { { "Warning" "WMLS_MLS_NODE_NAME" "GPIO_0\[0\]~synth " "Node \"GPIO_0\[0\]~synth\"" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 -1 0 } } } 0 13010 "Node \"%1!s!\"" 0 0 "" 0 -1 1394821268525 ""} { "Warning" "WMLS_MLS_NODE_NAME" "GPIO_1\[12\]~synth " "Node \"GPIO_1\[12\]~synth\"" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 -1 0 } } } 0 13010 "Node \"%1!s!\"" 0 0 "" 0 -1 1394821268525 ""} { "Warning" "WMLS_MLS_NODE_NAME" "GPIO_1\[26\]~synth " "Node \"GPIO_1\[26\]~synth\"" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 -1 0 } } } 0 13010 "Node \"%1!s!\"" 0 0 "" 0 -1 1394821268525 ""} } { } 0 13009 "TRI or OPNDRN buffers permanently enabled" 0 0 "" 0 -1 1394821268525 ""} +{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "DRAM_CKE VCC " "Pin \"DRAM_CKE\" is stuck at VCC" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 62 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1 1394821268525 "|de0_nano_system|DRAM_CKE"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "" 0 -1 1394821268525 ""} +{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING_ON_PARTITION" "Top " "Timing-Driven Synthesis is running on partition \"Top\"" { } { } 0 286031 "Timing-Driven Synthesis is running on partition \"%1!s!\"" 0 0 "" 0 -1 1394821269040 ""} +{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "370 " "370 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "" 0 -1 1394821271568 ""} +{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" { } { { "sld_jtag_hub.vhd" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/sld_jtag_hub.vhd" 346 -1 0 } } { "sld_jtag_hub.vhd" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/sld_jtag_hub.vhd" 479 -1 0 } } } 0 13000 "Registers with preset signals will power-up high" 0 0 "" 0 -1 1394821271755 ""} +{ "Info" "IMLS_MLS_DEV_CLRN_SETS_REGISTERS" "" "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" { } { } 0 13003 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "" 0 -1 1394821271755 ""} +{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "sld_hub:auto_hub\|receive\[0\]\[0\] GND " "Pin \"sld_hub:auto_hub\|receive\[0\]\[0\]\" is stuck at GND" { } { { "sld_hub.vhd" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/sld_hub.vhd" 177 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1 1394821271864 "|de0_nano_system|sld_hub:auto_hub|receive[0][0]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "" 0 -1 1394821271864 ""} +{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING_ON_PARTITION" "sld_hub:auto_hub " "Timing-Driven Synthesis is running on partition \"sld_hub:auto_hub\"" { } { } 0 286031 "Timing-Driven Synthesis is running on partition \"%1!s!\"" 0 0 "" 0 -1 1394821271989 ""} +{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "1 0 1 0 0 " "Adding 1 node(s), including 0 DDIO, 1 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "" 0 -1 1394821273518 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "" 0 -1 1394821273518 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "5529 " "Implemented 5529 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "10 " "Implemented 10 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "" 0 -1 1394821274111 ""} { "Info" "ICUT_CUT_TM_OPINS" "32 " "Implemented 32 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "" 0 -1 1394821274111 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "84 " "Implemented 84 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "" 0 -1 1394821274111 ""} { "Info" "ICUT_CUT_TM_LCELLS" "5134 " "Implemented 5134 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "" 0 -1 1394821274111 ""} { "Info" "ICUT_CUT_TM_RAMS" "263 " "Implemented 263 RAM segments" { } { } 0 21064 "Implemented %1!d! RAM segments" 0 0 "" 0 -1 1394821274111 ""} { "Info" "ICUT_CUT_TM_PLLS" "1 " "Implemented 1 PLLs" { } { } 0 21065 "Implemented %1!d! PLLs" 0 0 "" 0 -1 1394821274111 ""} { "Info" "ICUT_CUT_TM_DSP_ELEM" "4 " "Implemented 4 DSP elements" { } { } 0 21062 "Implemented %1!d! DSP elements" 0 0 "" 0 -1 1394821274111 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1 1394821274111 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 130 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 130 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "637 " "Peak virtual memory: 637 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1 1394821274235 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Mar 14 12:21:14 2014 " "Processing ended: Fri Mar 14 12:21:14 2014" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1 1394821274235 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:28 " "Elapsed time: 00:00:28" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1 1394821274235 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:21 " "Total CPU time (on all processors): 00:00:21" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1 1394821274235 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1 1394821274235 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1 1394821275499 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 64-Bit " "Running Quartus II 64-Bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Full Version " "Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1 1394821275499 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Mar 14 12:21:15 2014 " "Processing started: Fri Mar 14 12:21:15 2014" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1 1394821275499 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1 1394821275499 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off de0_nano_system -c de0_nano_system " "Command: quartus_fit --read_settings_files=off --write_settings_files=off de0_nano_system -c de0_nano_system" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1 1394821275499 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." { } { } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "" 0 -1 1394821275655 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "de0_nano_system EP4CE22F17C6 " "Selected device EP4CE22F17C6 for design \"de0_nano_system\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 -1 1394821275998 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "" 0 -1 1394821276045 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "" 0 -1 1394821276045 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "" 0 -1 1394821276045 ""} +{ "Info" "ICUT_CUT_PLL_COMPUTATION_SUCCESS" "pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|pll1 Cyclone IV E PLL " "Implemented PLL \"pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|pll1\" as Cyclone IV E PLL type" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|wire_pll1_clk\[0\] 2 1 0 0 " "Implementing clock multiplication of 2, clock division of 1, and phase shift of 0 degrees (0 ps) for pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|wire_pll1_clk\[0\] port" { } { { "db/pll_sys_altpll.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/pll_sys_altpll.v" 45 -1 0 } } { "" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 6111 8336 9085 0} } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "" 0 -1 1394821276217 ""} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|wire_pll1_clk\[1\] 2 1 -54 -1500 " "Implementing clock multiplication of 2, clock division of 1, and phase shift of -54 degrees (-1500 ps) for pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|wire_pll1_clk\[1\] port" { } { { "db/pll_sys_altpll.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/pll_sys_altpll.v" 45 -1 0 } } { "" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 6112 8336 9085 0} } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "" 0 -1 1394821276217 ""} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|wire_pll1_clk\[2\] 1 5 0 0 " "Implementing clock multiplication of 1, clock division of 5, and phase shift of 0 degrees (0 ps) for pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|wire_pll1_clk\[2\] port" { } { { "db/pll_sys_altpll.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/pll_sys_altpll.v" 45 -1 0 } } { "" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 6113 8336 9085 0} } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "" 0 -1 1394821276217 ""} } { { "db/pll_sys_altpll.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/pll_sys_altpll.v" 45 -1 0 } } { "" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 6111 8336 9085 0} } } } } 0 15535 "Implemented %3!s! \"%1!s!\" as %2!s! PLL type" 0 0 "" 0 -1 1394821276217 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0 -1 1394821277309 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE10F17C6 " "Device EP4CE10F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "" 0 -1 1394821277699 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE6F17C6 " "Device EP4CE6F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "" 0 -1 1394821277699 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE15F17C6 " "Device EP4CE15F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "" 0 -1 1394821277699 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 -1 1394821277699 ""} +{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ C1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location C1" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 16271 8336 9085 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1 1394821277714 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ D2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location D2" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 16273 8336 9085 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1 1394821277714 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ H1 " "Pin ~ALTERA_DCLK~ is reserved at location H1" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 16275 8336 9085 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1 1394821277714 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ H2 " "Pin ~ALTERA_DATA0~ is reserved at location H2" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 16277 8336 9085 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1 1394821277714 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ F16 " "Pin ~ALTERA_nCEO~ is reserved at location F16" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 16279 8336 9085 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1 1394821277714 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 -1 1394821277714 ""} +{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "" 0 -1 1394821277714 ""} +{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." { } { } 0 176045 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "" 0 -1 1394821277777 ""} +{ "Info" "ISTA_SDC_STATEMENT_PARENT" "" "Evaluating HDL-embedded SDC commands" { { "Info" "ISTA_SDC_STATEMENT_ENTITY" "alt_jtag_atlantic " "Entity alt_jtag_atlantic" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate1*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate1*\}\] " { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394821279555 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394821279555 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394821279555 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394821279555 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394821279555 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394821279555 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394821279555 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394821279555 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394821279555 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|read1*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|read1*\}\] " { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394821279555 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read_req\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read_req\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394821279555 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394821279555 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|tck_t_dav\}\] " "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|tck_t_dav\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394821279555 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|user_saw_rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid0*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|user_saw_rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid0*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394821279555 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394821279555 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394821279555 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394821279555 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394821279555 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394821279555 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394821279555 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394821279555 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394821279555 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write1*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write1*\}\] " { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394821279555 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_ena*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_ena*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394821279555 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_pause*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_pause*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394821279555 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_valid\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_valid\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394821279555 ""} } { } 0 332165 "Entity %1!s!" 0 0 "" 0 -1 1394821279555 ""} { "Info" "ISTA_SDC_STATEMENT_ENTITY" "altera_std_synchronizer " "Entity altera_std_synchronizer" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -to \[get_keepers \{*altera_std_synchronizer:*\|din_s1\}\] " "set_false_path -to \[get_keepers \{*altera_std_synchronizer:*\|din_s1\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394821279555 ""} } { } 0 332165 "Entity %1!s!" 0 0 "" 0 -1 1394821279555 ""} { "Info" "ISTA_SDC_STATEMENT_ENTITY" "sld_jtag_hub " "Entity sld_jtag_hub" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "create_clock -period 10MHz -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] " "create_clock -period 10MHz -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394821279555 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_clock_groups -asynchronous -group \{altera_reserved_tck\} " "set_clock_groups -asynchronous -group \{altera_reserved_tck\}" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394821279555 ""} } { } 0 332165 "Entity %1!s!" 0 0 "" 0 -1 1394821279555 ""} } { } 0 332164 "Evaluating HDL-embedded SDC commands" 0 0 "" 0 -1 1394821279555 ""} +{ "Info" "ISTA_SDC_FOUND" "de0_nano_system.sdc " "Reading SDC File: 'de0_nano_system.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "" 0 -1 1394821279805 ""} +{ "Warning" "WSTA_OVERWRITING_EXISTING_CLOCK" "altera_reserved_tck " "Overwriting existing clock: altera_reserved_tck" { } { } 0 332043 "Overwriting existing clock: %1!s!" 0 0 "" 0 -1 1394821279820 ""} +{ "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "Deriving PLL clocks " "Deriving PLL clocks" { { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -duty_cycle 50.00 -name \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} " "create_generated_clock -source \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -duty_cycle 50.00 -name \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}" { } { } 0 332110 "%1!s!" 0 0 "" 0 -1 1394821279820 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -phase -54.00 -duty_cycle 50.00 -name \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} " "create_generated_clock -source \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -phase -54.00 -duty_cycle 50.00 -name \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}" { } { } 0 332110 "%1!s!" 0 0 "" 0 -1 1394821279820 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 5 -duty_cycle 50.00 -name \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} " "create_generated_clock -source \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 5 -duty_cycle 50.00 -name \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\]\}" { } { } 0 332110 "%1!s!" 0 0 "" 0 -1 1394821279820 ""} } { } 0 332110 "%1!s!" 0 0 "" 0 -1 1394821279820 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_CALL_IS_DELAYED" "" "Clock uncertainty is not calculated until you update the timing netlist." { } { } 0 332151 "Clock uncertainty is not calculated until you update the timing netlist." 0 0 "" 0 -1 1394821279820 ""} +{ "Info" "ISTA_SDC_FOUND" "system/synthesis/submodules/altera_reset_controller.sdc " "Reading SDC File: 'system/synthesis/submodules/altera_reset_controller.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "" 0 -1 1394821279836 ""} +{ "Info" "ISTA_SDC_FOUND" "system/synthesis/submodules/system_cpu.sdc " "Reading SDC File: 'system/synthesis/submodules/system_cpu.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "" 0 -1 1394821279852 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "" 0 -1 1394821280039 ""} +{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "" 0 -1 1394821280039 ""} +{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 5 clocks " "Found 5 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "" 0 -1 1394821280039 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "" 0 -1 1394821280039 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 100.000 altera_reserved_tck " " 100.000 altera_reserved_tck" { } { } 0 332111 "%1!s!" 0 0 "" 0 -1 1394821280039 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 20.000 CLOCK_50 " " 20.000 CLOCK_50" { } { } 0 332111 "%1!s!" 0 0 "" 0 -1 1394821280039 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 10.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 10.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\]" { } { } 0 332111 "%1!s!" 0 0 "" 0 -1 1394821280039 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 10.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 10.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[1\]" { } { } 0 332111 "%1!s!" 0 0 "" 0 -1 1394821280039 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 100.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 100.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\]" { } { } 0 332111 "%1!s!" 0 0 "" 0 -1 1394821280039 ""} } { } 0 332111 "%1!s!" 0 0 "" 0 -1 1394821280039 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C0 of PLL_4) " "Automatically promoted node pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C0 of PLL_4)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G18 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G18" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1 1394821280444 ""} } { { "db/pll_sys_altpll.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/pll_sys_altpll.v" 80 -1 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { pll_sys:inst_pll_sys|altpll:altpll_component|pll_sys_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 6111 8336 9085 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1 1394821280444 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|wire_pll1_clk\[1\] (placed in counter C2 of PLL_4) " "Automatically promoted node pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|wire_pll1_clk\[1\] (placed in counter C2 of PLL_4)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G17 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G17" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1 1394821280444 ""} } { { "db/pll_sys_altpll.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/pll_sys_altpll.v" 80 -1 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { pll_sys:inst_pll_sys|altpll:altpll_component|pll_sys_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 6111 8336 9085 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1 1394821280444 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|wire_pll1_clk\[2\] (placed in counter C1 of PLL_4) " "Automatically promoted node pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|wire_pll1_clk\[2\] (placed in counter C1 of PLL_4)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G19 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G19" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1 1394821280444 ""} } { { "db/pll_sys_altpll.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/pll_sys_altpll.v" 80 -1 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { pll_sys:inst_pll_sys|altpll:altpll_component|pll_sys_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 6111 8336 9085 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1 1394821280444 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "altera_internal_jtag~TCKUTAP " "Automatically promoted node altera_internal_jtag~TCKUTAP " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1 1394821280444 ""} } { { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 15746 8336 9085 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1 1394821280444 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "system:inst_cpu\|altera_reset_controller:rst_controller\|altera_reset_synchronizer:alt_rst_sync_uq1\|altera_reset_synchronizer_int_chain_out " "Automatically promoted node system:inst_cpu\|altera_reset_controller:rst_controller\|altera_reset_synchronizer:alt_rst_sync_uq1\|altera_reset_synchronizer_int_chain_out " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1 1394821280444 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr\|counter_reg_bit\[6\] " "Destination node system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr\|counter_reg_bit\[6\]" { } { { "db/cntr_0ab.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/cntr_0ab.tdf" 68 17 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 6323 8336 9085 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "" 0 -1 1394821280444 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr\|counter_reg_bit\[5\] " "Destination node system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr\|counter_reg_bit\[5\]" { } { { "db/cntr_0ab.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/cntr_0ab.tdf" 68 17 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 6324 8336 9085 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "" 0 -1 1394821280444 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr\|counter_reg_bit\[4\] " "Destination node system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr\|counter_reg_bit\[4\]" { } { { "db/cntr_0ab.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/cntr_0ab.tdf" 68 17 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 6325 8336 9085 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "" 0 -1 1394821280444 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr\|counter_reg_bit\[3\] " "Destination node system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr\|counter_reg_bit\[3\]" { } { { "db/cntr_0ab.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/cntr_0ab.tdf" 68 17 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 6326 8336 9085 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "" 0 -1 1394821280444 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr\|counter_reg_bit\[2\] " "Destination node system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr\|counter_reg_bit\[2\]" { } { { "db/cntr_0ab.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/cntr_0ab.tdf" 68 17 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 6327 8336 9085 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "" 0 -1 1394821280444 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr\|counter_reg_bit\[1\] " "Destination node system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr\|counter_reg_bit\[1\]" { } { { "db/cntr_0ab.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/cntr_0ab.tdf" 68 17 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 6328 8336 9085 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "" 0 -1 1394821280444 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr\|counter_reg_bit\[0\] " "Destination node system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr\|counter_reg_bit\[0\]" { } { { "db/cntr_0ab.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/cntr_0ab.tdf" 68 17 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 6329 8336 9085 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "" 0 -1 1394821280444 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_ca7:usedw_counter\|counter_reg_bit\[6\] " "Destination node system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_ca7:usedw_counter\|counter_reg_bit\[6\]" { } { { "db/cntr_ca7.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/cntr_ca7.tdf" 69 17 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_ca7:usedw_counter|counter_reg_bit[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 6346 8336 9085 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "" 0 -1 1394821280444 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_ca7:usedw_counter\|counter_reg_bit\[5\] " "Destination node system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_ca7:usedw_counter\|counter_reg_bit\[5\]" { } { { "db/cntr_ca7.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/cntr_ca7.tdf" 69 17 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_ca7:usedw_counter|counter_reg_bit[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 6347 8336 9085 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "" 0 -1 1394821280444 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_ca7:usedw_counter\|counter_reg_bit\[4\] " "Destination node system:inst_cpu\|system_rs232_motor:rs232_motor\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_ca7:usedw_counter\|counter_reg_bit\[4\]" { } { { "db/cntr_ca7.tdf" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/cntr_ca7.tdf" 69 17 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_ca7:usedw_counter|counter_reg_bit[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 6348 8336 9085 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "" 0 -1 1394821280444 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_LIMITED_TO_SUB" "10 " "Non-global destination nodes limited to 10 nodes" { } { } 0 176358 "Non-global destination nodes limited to %1!d! nodes" 0 0 "" 0 -1 1394821280444 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0 -1 1394821280444 ""} } { { "system/synthesis/submodules/altera_reset_synchronizer.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_reset_synchronizer.v" 62 -1 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 682 8336 9085 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1 1394821280444 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "sld_hub:auto_hub\|sld_jtag_hub:\\jtag_hub_gen:sld_jtag_hub_inst\|clr_reg " "Automatically promoted node sld_hub:auto_hub\|sld_jtag_hub:\\jtag_hub_gen:sld_jtag_hub_inst\|clr_reg " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1 1394821280444 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "sld_hub:auto_hub\|sld_jtag_hub:\\jtag_hub_gen:sld_jtag_hub_inst\|clr_reg~_wirecell " "Destination node sld_hub:auto_hub\|sld_jtag_hub:\\jtag_hub_gen:sld_jtag_hub_inst\|clr_reg~_wirecell" { } { { "sld_jtag_hub.vhd" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/sld_jtag_hub.vhd" 335 -1 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg~_wirecell } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 16131 8336 9085 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "" 0 -1 1394821280444 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0 -1 1394821280444 ""} } { { "sld_jtag_hub.vhd" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/sld_jtag_hub.vhd" 335 -1 0 } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "sld_hub:auto_hub\|sld_jtag_hub:\\jtag_hub_gen:sld_jtag_hub_inst\|clr_reg" } } } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 15877 8336 9085 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1 1394821280444 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "sld_hub:auto_hub\|sld_jtag_hub:\\jtag_hub_gen:sld_jtag_hub_inst\|sld_shadow_jsm:shadow_jsm\|state\[0\] " "Automatically promoted node sld_hub:auto_hub\|sld_jtag_hub:\\jtag_hub_gen:sld_jtag_hub_inst\|sld_shadow_jsm:shadow_jsm\|state\[0\] " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1 1394821280444 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "sld_hub:auto_hub\|sld_jtag_hub:\\jtag_hub_gen:sld_jtag_hub_inst\|sld_shadow_jsm:shadow_jsm\|state~0 " "Destination node sld_hub:auto_hub\|sld_jtag_hub:\\jtag_hub_gen:sld_jtag_hub_inst\|sld_shadow_jsm:shadow_jsm\|state~0" { } { { "sld_jtag_hub.vhd" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/sld_jtag_hub.vhd" 1076 -1 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 16011 8336 9085 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "" 0 -1 1394821280444 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "sld_hub:auto_hub\|sld_jtag_hub:\\jtag_hub_gen:sld_jtag_hub_inst\|sld_shadow_jsm:shadow_jsm\|state~1 " "Destination node sld_hub:auto_hub\|sld_jtag_hub:\\jtag_hub_gen:sld_jtag_hub_inst\|sld_shadow_jsm:shadow_jsm\|state~1" { } { { "sld_jtag_hub.vhd" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/sld_jtag_hub.vhd" 1076 -1 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state~1 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 16012 8336 9085 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "" 0 -1 1394821280444 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "sld_hub:auto_hub\|sld_jtag_hub:\\jtag_hub_gen:sld_jtag_hub_inst\|sld_shadow_jsm:shadow_jsm\|state\[0\]~_wirecell " "Destination node sld_hub:auto_hub\|sld_jtag_hub:\\jtag_hub_gen:sld_jtag_hub_inst\|sld_shadow_jsm:shadow_jsm\|state\[0\]~_wirecell" { } { { "sld_jtag_hub.vhd" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/sld_jtag_hub.vhd" 1090 -1 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0]~_wirecell } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 16132 8336 9085 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "" 0 -1 1394821280444 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0 -1 1394821280444 ""} } { { "sld_jtag_hub.vhd" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/sld_jtag_hub.vhd" 1090 -1 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 15770 8336 9085 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1 1394821280444 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "system:inst_cpu\|altera_reset_controller:rst_controller\|merged_reset~0 " "Automatically promoted node system:inst_cpu\|altera_reset_controller:rst_controller\|merged_reset~0 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1 1394821280444 ""} } { { "system/synthesis/submodules/altera_reset_controller.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_reset_controller.v" 61 -1 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { system:inst_cpu|altera_reset_controller:rst_controller|merged_reset~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 7344 8336 9085 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1 1394821280444 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "" 0 -1 1394821281958 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1 1394821281973 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1 1394821281973 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "" 0 -1 1394821281973 ""} +{ "Warning" "WFSAC_FSAC_IGNORED_FAST_REGISTER_IO_ASSIGNMENTS" "" "Ignoring invalid fast I/O register assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 176250 "Ignoring invalid fast I/O register assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "" 0 -1 1394821284423 ""} +{ "Warning" "WFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS" "" "Ignoring some wildcard destinations of fast I/O register assignments" { { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Enable Register ON oe " "Wildcard assignment \"Fast Output Enable Register=ON\" to \"oe\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1394821284423 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[9\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[9\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1394821284423 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[8\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[8\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1394821284423 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[7\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[7\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1394821284423 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[6\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[6\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1394821284423 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[5\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[5\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1394821284423 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[4\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[4\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1394821284423 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[3\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[3\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1394821284423 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[2\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[2\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1394821284423 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[1\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[1\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1394821284423 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[15\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[15\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1394821284423 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[14\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[14\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1394821284423 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[13\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[13\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1394821284423 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[12\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[12\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1394821284423 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[11\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[11\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1394821284423 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[10\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[10\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1394821284423 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[0\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[0\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1394821284423 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_cmd\[2\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_cmd\[2\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1394821284423 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_cmd\[1\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_cmd\[1\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1394821284423 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_cmd\[0\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_cmd\[0\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1394821284423 ""} } { } 0 176251 "Ignoring some wildcard destinations of fast I/O register assignments" 0 0 "" 0 -1 1394821284423 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "" 0 -1 1394821284438 ""} +{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "" 0 -1 1394821284438 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "" 0 -1 1394821285951 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NUM_REGISTERS_PACKED_INTO_ATOM_TYPE" "10 EC " "Packed 10 registers into blocks of type EC" { } { } 1 176218 "Packed %1!d! registers into blocks of type %2!s!" 0 0 "" 0 -1 1394821287387 ""} { "Extra Info" "IFSAC_NUM_REGISTERS_PACKED_INTO_ATOM_TYPE" "64 Embedded multiplier block " "Packed 64 registers into blocks of type Embedded multiplier block" { } { } 1 176218 "Packed %1!d! registers into blocks of type %2!s!" 0 0 "" 0 -1 1394821287387 ""} { "Extra Info" "IFSAC_NUM_REGISTERS_PACKED_INTO_ATOM_TYPE" "16 I/O Input Buffer " "Packed 16 registers into blocks of type I/O Input Buffer" { } { } 1 176218 "Packed %1!d! registers into blocks of type %2!s!" 0 0 "" 0 -1 1394821287387 ""} { "Extra Info" "IFSAC_NUM_REGISTERS_PACKED_INTO_ATOM_TYPE" "53 I/O Output Buffer " "Packed 53 registers into blocks of type I/O Output Buffer" { } { } 1 176218 "Packed %1!d! registers into blocks of type %2!s!" 0 0 "" 0 -1 1394821287387 ""} { "Extra Info" "IFSAC_NUM_REGISTERS_DUPLICATED" "66 " "Created 66 register duplicates" { } { } 1 176220 "Created %1!d! register duplicates" 0 0 "" 0 -1 1394821287387 ""} } { } 0 176235 "Finished register packing" 0 0 "" 0 -1 1394821287387 ""} +{ "Warning" "WCUT_PLL_CLK_FEEDS_NON_DEDICATED_IO" "pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|pll1 clk\[1\] DRAM_CLK~output " "PLL \"pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|pll1\" output port clk\[1\] feeds output pin \"DRAM_CLK~output\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" { } { { "db/pll_sys_altpll.v" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/pll_sys_altpll.v" 45 -1 0 } } { "altpll.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altpll.tdf" 897 0 0 } } { "pll_sys.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/pll_sys.vhd" 154 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 149 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 61 0 0 } } } 0 15064 "PLL \"%1!s!\" output port %2!s! feeds output pin \"%3!s!\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" 0 0 "" 0 -1 1394821287527 ""} +{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_CS_N " "Node \"ADC_CS_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1394821287652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SADDR " "Node \"ADC_SADDR\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SADDR" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1394821287652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SCLK " "Node \"ADC_SCLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1394821287652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDAT " "Node \"ADC_SDAT\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1394821287652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0_IN\[0\] " "Node \"GPIO_0_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1394821287652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0_IN\[1\] " "Node \"GPIO_0_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1394821287652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1_IN\[0\] " "Node \"GPIO_1_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1394821287652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1_IN\[1\] " "Node \"GPIO_1_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1394821287652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[0\] " "Node \"GPIO_2\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1394821287652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[10\] " "Node \"GPIO_2\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1394821287652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[11\] " "Node \"GPIO_2\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1394821287652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[12\] " "Node \"GPIO_2\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1394821287652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[1\] " "Node \"GPIO_2\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1394821287652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[2\] " "Node \"GPIO_2\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1394821287652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[3\] " "Node \"GPIO_2\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1394821287652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[4\] " "Node \"GPIO_2\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1394821287652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[5\] " "Node \"GPIO_2\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1394821287652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[6\] " "Node \"GPIO_2\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1394821287652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[7\] " "Node \"GPIO_2\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1394821287652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[8\] " "Node \"GPIO_2\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1394821287652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[9\] " "Node \"GPIO_2\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1394821287652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[0\] " "Node \"GPIO_2_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1394821287652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[1\] " "Node \"GPIO_2_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1394821287652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[2\] " "Node \"GPIO_2_IN\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1394821287652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "G_SENSOR_CS_N " "Node \"G_SENSOR_CS_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "G_SENSOR_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1394821287652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "G_SENSOR_INT " "Node \"G_SENSOR_INT\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "G_SENSOR_INT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1394821287652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SCLK " "Node \"I2C_SCLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "I2C_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1394821287652 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SDAT " "Node \"I2C_SDAT\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1394821287652 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "" 0 -1 1394821287652 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:10 " "Fitter preparation operations ending: elapsed time is 00:00:10" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1 1394821287652 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "" 0 -1 1394821289399 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1 1394821290866 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "" 0 -1 1394821290912 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "" 0 -1 1394821298026 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:07 " "Fitter placement operations ending: elapsed time is 00:00:07" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 -1 1394821298026 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "" 0 -1 1394821299789 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "7 " "Router estimated average interconnect usage is 7% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "25 X21_Y11 X31_Y22 " "Router estimated peak interconnect usage is 25% of the available device resources in the region that extends from location X21_Y11 to location X31_Y22" { } { { "loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 1 { 0 "Router estimated peak interconnect usage is 25% of the available device resources in the region that extends from location X21_Y11 to location X31_Y22"} { { 11 { 0 "Router estimated peak interconnect usage is 25% of the available device resources in the region that extends from location X21_Y11 to location X31_Y22"} 21 11 11 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1 1394821304142 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1 1394821304142 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:06 " "Fitter routing operations ending: elapsed time is 00:00:06" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 -1 1394821306763 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 -1 1394821306763 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 -1 1394821306763 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "" 0 -1 1394821306763 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "" 0 -1 1394821306997 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "" 0 -1 1394821307636 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "" 0 -1 1394821307699 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "" 0 -1 1394821308385 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:04 " "Fitter post-fit operations ending: elapsed time is 00:00:04" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "" 0 -1 1394821310538 ""} +{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "" 0 -1 1394821311131 ""} +{ "Warning" "WFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE" "68 " "Following 68 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[2\] a permanently disabled " "Pin GPIO_0\[2\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[2] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[2\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 307 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394821311193 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[3\] a permanently disabled " "Pin GPIO_0\[3\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[3] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[3\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 308 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394821311193 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[4\] a permanently disabled " "Pin GPIO_0\[4\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[4] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[4\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 309 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394821311193 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[5\] a permanently disabled " "Pin GPIO_0\[5\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[5] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[5\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 310 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394821311193 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[6\] a permanently disabled " "Pin GPIO_0\[6\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[6] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[6\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 311 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394821311193 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[7\] a permanently disabled " "Pin GPIO_0\[7\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[7] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[7\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 312 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394821311193 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[8\] a permanently disabled " "Pin GPIO_0\[8\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[8] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[8\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 313 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394821311193 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[9\] a permanently disabled " "Pin GPIO_0\[9\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[9] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[9\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 314 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394821311193 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[10\] a permanently disabled " "Pin GPIO_0\[10\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[10] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[10\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 315 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394821311193 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[11\] a permanently disabled " "Pin GPIO_0\[11\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[11] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[11\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 316 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394821311193 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[12\] a permanently disabled " "Pin GPIO_0\[12\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[12] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[12\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 317 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394821311193 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[13\] a permanently disabled " "Pin GPIO_0\[13\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[13] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[13\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 318 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394821311193 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[14\] a permanently disabled " "Pin GPIO_0\[14\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[14] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[14\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 319 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394821311193 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[15\] a permanently disabled " "Pin GPIO_0\[15\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[15] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[15\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 320 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394821311193 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[16\] a permanently disabled " "Pin GPIO_0\[16\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[16] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[16\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[16] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 321 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394821311193 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[17\] a permanently disabled " "Pin GPIO_0\[17\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[17] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[17\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[17] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 322 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394821311193 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[18\] a permanently disabled " "Pin GPIO_0\[18\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[18] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[18\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[18] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 323 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394821311193 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[19\] a permanently disabled " "Pin GPIO_0\[19\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[19] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[19\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[19] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 324 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394821311193 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[20\] a permanently disabled " "Pin GPIO_0\[20\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[20] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[20\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[20] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 325 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394821311193 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[21\] a permanently disabled " "Pin GPIO_0\[21\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[21] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[21\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[21] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 326 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394821311193 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[22\] a permanently disabled " "Pin GPIO_0\[22\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[22] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[22\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[22] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 327 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394821311193 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[23\] a permanently disabled " "Pin GPIO_0\[23\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[23] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[23\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[23] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 328 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394821311193 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[24\] a permanently disabled " "Pin GPIO_0\[24\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[24] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[24\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[24] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 329 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394821311193 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[25\] a permanently disabled " "Pin GPIO_0\[25\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[25] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[25\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[25] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 330 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394821311193 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[26\] a permanently disabled " "Pin GPIO_0\[26\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[26] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[26\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[26] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 331 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394821311193 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[27\] a permanently disabled " "Pin GPIO_0\[27\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[27] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[27\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[27] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 332 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394821311193 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[28\] a permanently disabled " "Pin GPIO_0\[28\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[28] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[28\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[28] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 333 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394821311193 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[29\] a permanently disabled " "Pin GPIO_0\[29\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[29] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[29\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[29] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 334 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394821311193 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[30\] a permanently disabled " "Pin GPIO_0\[30\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[30] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[30\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[30] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 335 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394821311193 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[31\] a permanently disabled " "Pin GPIO_0\[31\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[31] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[31\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[31] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 336 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394821311193 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[32\] a permanently disabled " "Pin GPIO_0\[32\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[32] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[32\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[32] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 337 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394821311193 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[33\] a permanently disabled " "Pin GPIO_0\[33\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[33] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[33\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[33] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 338 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394821311193 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[0\] a permanently disabled " "Pin GPIO_1\[0\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[0] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[0\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 339 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394821311193 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[1\] a permanently disabled " "Pin GPIO_1\[1\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[1] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[1\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 340 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394821311193 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[2\] a permanently disabled " "Pin GPIO_1\[2\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[2] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[2\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 341 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394821311193 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[3\] a permanently disabled " "Pin GPIO_1\[3\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[3] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[3\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 342 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394821311193 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[4\] a permanently disabled " "Pin GPIO_1\[4\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[4] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[4\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 343 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394821311193 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[5\] a permanently disabled " "Pin GPIO_1\[5\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[5] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[5\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 344 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394821311193 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[6\] a permanently disabled " "Pin GPIO_1\[6\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[6] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[6\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 345 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394821311193 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[7\] a permanently disabled " "Pin GPIO_1\[7\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[7] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[7\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 346 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394821311193 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[8\] a permanently disabled " "Pin GPIO_1\[8\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[8] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[8\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 347 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394821311193 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[9\] a permanently disabled " "Pin GPIO_1\[9\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[9] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[9\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 348 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394821311193 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[10\] a permanently disabled " "Pin GPIO_1\[10\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[10] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[10\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 349 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394821311193 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[11\] a permanently disabled " "Pin GPIO_1\[11\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[11] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[11\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 350 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394821311193 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[13\] a permanently disabled " "Pin GPIO_1\[13\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[13] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[13\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 351 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394821311193 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[14\] a permanently disabled " "Pin GPIO_1\[14\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[14] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[14\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 352 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394821311193 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[15\] a permanently disabled " "Pin GPIO_1\[15\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[15] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[15\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 353 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394821311193 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[16\] a permanently disabled " "Pin GPIO_1\[16\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[16] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[16\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[16] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 354 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394821311193 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[17\] a permanently disabled " "Pin GPIO_1\[17\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[17] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[17\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[17] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 355 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394821311193 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[18\] a permanently disabled " "Pin GPIO_1\[18\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[18] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[18\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[18] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 356 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394821311193 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[19\] a permanently disabled " "Pin GPIO_1\[19\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[19] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[19\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[19] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 357 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394821311193 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[20\] a permanently disabled " "Pin GPIO_1\[20\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[20] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[20\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[20] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 358 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394821311193 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[21\] a permanently disabled " "Pin GPIO_1\[21\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[21] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[21\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[21] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 359 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394821311193 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[22\] a permanently disabled " "Pin GPIO_1\[22\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[22] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[22\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[22] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 360 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394821311193 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[23\] a permanently disabled " "Pin GPIO_1\[23\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[23] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[23\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[23] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 361 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394821311193 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[25\] a permanently disabled " "Pin GPIO_1\[25\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[25] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[25\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[25] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 362 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394821311193 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[27\] a permanently disabled " "Pin GPIO_1\[27\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[27] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[27\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[27] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 363 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394821311193 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[28\] a permanently disabled " "Pin GPIO_1\[28\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[28] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[28\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[28] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 364 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394821311193 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[29\] a permanently disabled " "Pin GPIO_1\[29\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[29] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[29\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[29] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 365 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394821311193 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[30\] a permanently disabled " "Pin GPIO_1\[30\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[30] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[30\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[30] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 366 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394821311193 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[31\] a permanently disabled " "Pin GPIO_1\[31\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[31] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[31\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[31] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 367 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394821311193 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[32\] a permanently disabled " "Pin GPIO_1\[32\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[32] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[32\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[32] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 368 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394821311193 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[33\] a permanently disabled " "Pin GPIO_1\[33\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[33] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[33\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[33] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 369 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394821311193 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[0\] a permanently enabled " "Pin GPIO_0\[0\] has a permanently enabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[0] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[0\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 255 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394821311193 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[1\] a permanently disabled " "Pin GPIO_0\[1\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[1] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[1\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 259 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394821311193 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[12\] a permanently enabled " "Pin GPIO_1\[12\] has a permanently enabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[12] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[12\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 257 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394821311193 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[24\] a permanently disabled " "Pin GPIO_1\[24\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[24] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[24\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[24] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 258 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394821311193 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[26\] a permanently enabled " "Pin GPIO_1\[26\] has a permanently enabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[26] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[26\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[26] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/" { { 0 { 0 ""} 0 256 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1394821311193 ""} } { } 0 169064 "Following %1!d! pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results" 0 0 "" 0 -1 1394821311193 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/output_files/de0_nano_system.fit.smsg " "Generated suppressed messages file C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/output_files/de0_nano_system.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "" 0 -1 1394821311724 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 36 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 36 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1138 " "Peak virtual memory: 1138 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1 1394821313268 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Mar 14 12:21:53 2014 " "Processing ended: Fri Mar 14 12:21:53 2014" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1 1394821313268 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:38 " "Elapsed time: 00:00:38" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1 1394821313268 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:46 " "Total CPU time (on all processors): 00:00:46" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1 1394821313268 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1 1394821313268 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1 1394821314828 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Full Version " "Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1 1394821314828 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Mar 14 12:21:54 2014 " "Processing started: Fri Mar 14 12:21:54 2014" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1 1394821314828 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1 1394821314828 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off de0_nano_system -c de0_nano_system " "Command: quartus_asm --read_settings_files=off --write_settings_files=off de0_nano_system -c de0_nano_system" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1 1394821314828 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "" 0 -1 1394821316794 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "" 0 -1 1394821316841 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "447 " "Peak virtual memory: 447 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1 1394821317293 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Mar 14 12:21:57 2014 " "Processing ended: Fri Mar 14 12:21:57 2014" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1 1394821317293 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1 1394821317293 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1 1394821317293 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1 1394821317293 ""} +{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "" 0 -1 1394821318057 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1 1394821318791 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Full Version " "Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1 1394821318791 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Mar 14 12:21:58 2014 " "Processing started: Fri Mar 14 12:21:58 2014" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1 1394821318791 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1 1394821318791 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta de0_nano_system -c de0_nano_system " "Command: quartus_sta de0_nano_system -c de0_nano_system" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1 1394821318791 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "" 0 0 1394821318884 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." { } { } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "" 0 -1 1394821319181 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "" 0 -1 1394821319181 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "" 0 -1 1394821319227 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "" 0 -1 1394821319227 ""} +{ "Info" "ISTA_SDC_STATEMENT_PARENT" "" "Evaluating HDL-embedded SDC commands" { { "Info" "ISTA_SDC_STATEMENT_ENTITY" "alt_jtag_atlantic " "Entity alt_jtag_atlantic" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate1*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate1*\}\] " { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394821319883 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394821319883 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394821319883 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394821319883 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394821319883 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394821319883 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394821319883 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394821319883 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394821319883 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|read1*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|read1*\}\] " { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394821319883 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read_req\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read_req\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394821319883 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394821319883 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|tck_t_dav\}\] " "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|tck_t_dav\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394821319883 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|user_saw_rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid0*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|user_saw_rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid0*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394821319883 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394821319883 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394821319883 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394821319883 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394821319883 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394821319883 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394821319883 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394821319883 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394821319883 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write1*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write1*\}\] " { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394821319883 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_ena*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_ena*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394821319883 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_pause*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_pause*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394821319883 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_valid\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_valid\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394821319883 ""} } { } 0 332165 "Entity %1!s!" 0 0 "" 0 -1 1394821319883 ""} { "Info" "ISTA_SDC_STATEMENT_ENTITY" "altera_std_synchronizer " "Entity altera_std_synchronizer" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -to \[get_keepers \{*altera_std_synchronizer:*\|din_s1\}\] " "set_false_path -to \[get_keepers \{*altera_std_synchronizer:*\|din_s1\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394821319883 ""} } { } 0 332165 "Entity %1!s!" 0 0 "" 0 -1 1394821319883 ""} { "Info" "ISTA_SDC_STATEMENT_ENTITY" "sld_jtag_hub " "Entity sld_jtag_hub" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "create_clock -period 10MHz -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] " "create_clock -period 10MHz -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394821319883 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_clock_groups -asynchronous -group \{altera_reserved_tck\} " "set_clock_groups -asynchronous -group \{altera_reserved_tck\}" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1394821319883 ""} } { } 0 332165 "Entity %1!s!" 0 0 "" 0 -1 1394821319883 ""} } { } 0 332164 "Evaluating HDL-embedded SDC commands" 0 0 "" 0 -1 1394821319883 ""} +{ "Info" "ISTA_SDC_FOUND" "de0_nano_system.sdc " "Reading SDC File: 'de0_nano_system.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "" 0 -1 1394821319914 ""} +{ "Warning" "WSTA_OVERWRITING_EXISTING_CLOCK" "altera_reserved_tck " "Overwriting existing clock: altera_reserved_tck" { } { } 0 332043 "Overwriting existing clock: %1!s!" 0 0 "" 0 -1 1394821319914 ""} +{ "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "Deriving PLL clocks " "Deriving PLL clocks" { { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -duty_cycle 50.00 -name \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} " "create_generated_clock -source \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -duty_cycle 50.00 -name \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}" { } { } 0 332110 "%1!s!" 0 0 "" 0 -1 1394821319914 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -phase -54.00 -duty_cycle 50.00 -name \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} " "create_generated_clock -source \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -phase -54.00 -duty_cycle 50.00 -name \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}" { } { } 0 332110 "%1!s!" 0 0 "" 0 -1 1394821319914 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 5 -duty_cycle 50.00 -name \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} " "create_generated_clock -source \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 5 -duty_cycle 50.00 -name \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\]\}" { } { } 0 332110 "%1!s!" 0 0 "" 0 -1 1394821319914 ""} } { } 0 332110 "%1!s!" 0 0 "" 0 -1 1394821319914 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_CALL_IS_DELAYED" "" "Clock uncertainty is not calculated until you update the timing netlist." { } { } 0 332151 "Clock uncertainty is not calculated until you update the timing netlist." 0 0 "" 0 -1 1394821319929 ""} +{ "Info" "ISTA_SDC_FOUND" "system/synthesis/submodules/altera_reset_controller.sdc " "Reading SDC File: 'system/synthesis/submodules/altera_reset_controller.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "" 0 -1 1394821319929 ""} +{ "Info" "ISTA_SDC_FOUND" "system/synthesis/submodules/system_cpu.sdc " "Reading SDC File: 'system/synthesis/submodules/system_cpu.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "" 0 -1 1394821319945 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "" 0 -1 1394821320148 ""} +{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "" 0 0 1394821320148 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "" 0 0 1394821320179 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup 1.661 " "Worst-case setup slack is 1.661" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394821320241 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394821320241 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.661 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 1.661 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394821320241 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 97.388 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 97.388 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394821320241 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1394821320241 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.296 " "Worst-case hold slack is 0.296" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394821320273 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394821320273 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.296 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.296 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394821320273 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.361 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 0.361 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394821320273 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1394821320273 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 2.101 " "Worst-case recovery slack is 2.101" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394821320273 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394821320273 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 2.101 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 2.101 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394821320273 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1394821320273 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "removal 2.380 " "Worst-case removal slack is 2.380" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394821320288 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394821320288 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 2.380 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 2.380 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394821320288 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1394821320288 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 4.696 " "Worst-case minimum pulse width slack is 4.696" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394821320288 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394821320288 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.696 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 4.696 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394821320288 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 9.835 0.000 CLOCK_50 " " 9.835 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394821320288 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 49.623 0.000 altera_reserved_tck " " 49.623 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394821320288 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 49.747 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 49.747 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394821320288 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1394821320288 ""} +{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 5 synchronizer chains. " "Report Metastability: Found 5 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n " "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1394821320632 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 5 " "Number of Synchronizer Chains Found: 5" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1394821320632 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1394821320632 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 0.400 " "Fraction of Chains for which MTBFs Could Not be Calculated: 0.400" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1394821320632 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 17.057 ns " "Worst Case Available Settling Time: 17.057 ns" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1394821320632 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1394821320632 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. " "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions." { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1394821320632 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8 " " - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1394821320632 ""} } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1394821320632 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "" 0 0 1394821320632 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "" 0 -1 1394821320663 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "" 0 -1 1394821321630 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "" 0 -1 1394821321958 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup 2.389 " "Worst-case setup slack is 2.389" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394821322036 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394821322036 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 2.389 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 2.389 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394821322036 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 97.707 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 97.707 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394821322036 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1394821322036 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.291 " "Worst-case hold slack is 0.291" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394821322051 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394821322051 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.291 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.291 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394821322051 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.320 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 0.320 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394821322051 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1394821322051 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 2.424 " "Worst-case recovery slack is 2.424" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394821322067 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394821322067 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 2.424 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 2.424 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394821322067 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1394821322067 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "removal 2.131 " "Worst-case removal slack is 2.131" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394821322082 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394821322082 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 2.131 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 2.131 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394821322082 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1394821322082 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 4.718 " "Worst-case minimum pulse width slack is 4.718" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394821322082 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394821322082 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.718 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 4.718 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394821322082 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 9.818 0.000 CLOCK_50 " " 9.818 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394821322082 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 49.602 0.000 altera_reserved_tck " " 49.602 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394821322082 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 49.744 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 49.744 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394821322082 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1394821322082 ""} +{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 5 synchronizer chains. " "Report Metastability: Found 5 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n " "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1394821322348 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 5 " "Number of Synchronizer Chains Found: 5" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1394821322348 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1394821322348 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 0.400 " "Fraction of Chains for which MTBFs Could Not be Calculated: 0.400" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1394821322348 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 17.343 ns " "Worst Case Available Settling Time: 17.343 ns" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1394821322348 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1394821322348 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. " "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions." { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1394821322348 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8 " " - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1394821322348 ""} } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1394821322348 ""} +{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "" 0 0 1394821322363 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "" 0 -1 1394821322738 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup 3.302 " "Worst-case setup slack is 3.302" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394821322753 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394821322753 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 3.302 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 3.302 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394821322753 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 98.512 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 98.512 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394821322753 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1394821322753 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.139 " "Worst-case hold slack is 0.139" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394821322784 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394821322784 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.139 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.139 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394821322784 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.193 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 0.193 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394821322784 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1394821322784 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 3.297 " "Worst-case recovery slack is 3.297" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394821322800 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394821322800 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 3.297 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 3.297 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394821322800 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1394821322800 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "removal 1.375 " "Worst-case removal slack is 1.375" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394821322816 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394821322816 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.375 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 1.375 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394821322816 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1394821322816 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 4.749 " "Worst-case minimum pulse width slack is 4.749" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394821322831 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394821322831 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.749 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 4.749 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394821322831 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 9.587 0.000 CLOCK_50 " " 9.587 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394821322831 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 49.483 0.000 altera_reserved_tck " " 49.483 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394821322831 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 49.782 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 49.782 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1394821322831 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1394821322831 ""} +{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 5 synchronizer chains. " "Report Metastability: Found 5 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n " "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1394821323159 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 5 " "Number of Synchronizer Chains Found: 5" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1394821323159 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1394821323159 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 0.400 " "Fraction of Chains for which MTBFs Could Not be Calculated: 0.400" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1394821323159 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 18.373 ns " "Worst Case Available Settling Time: 18.373 ns" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1394821323159 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1394821323159 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. " "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions." { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1394821323159 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8 " " - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1394821323159 ""} } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1394821323159 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "" 0 -1 1394821323689 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "" 0 -1 1394821323689 ""} +{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 1 Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "570 " "Peak virtual memory: 570 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1 1394821324032 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Mar 14 12:22:04 2014 " "Processing ended: Fri Mar 14 12:22:04 2014" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1 1394821324032 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1 1394821324032 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1 1394821324032 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1 1394821324032 ""} +{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 167 s " "Quartus II Full Compilation was successful. 0 errors, 167 warnings" { } { } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1 1394821325000 ""} diff --git a/MCTEST/DE0-nano-HD/db/scfifo_a341.tdf b/MCTEST/DE0-nano-HD/db/scfifo_a341.tdf new file mode 100644 index 00000000..c1da0ab1 --- /dev/null +++ b/MCTEST/DE0-nano-HD/db/scfifo_a341.tdf @@ -0,0 +1,50 @@ +--scfifo ADD_RAM_OUTPUT_REGISTER="OFF" DEVICE_FAMILY="Cyclone IV E" LPM_NUMWORDS=128 LPM_SHOWAHEAD="ON" LPM_WIDTH=8 LPM_WIDTHU=7 OPTIMIZE_FOR_SPEED=5 OVERFLOW_CHECKING="OFF" UNDERFLOW_CHECKING="OFF" USE_EAB="ON" clock data empty full q rdreq sclr usedw wrreq CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 CYCLONEII_M4K_COMPATIBILITY="ON" INTENDED_DEVICE_FAMILY="Cyclone II" LOW_POWER_MODE="AUTO" +--VERSION_BEGIN 12.1SP1 cbx_altdpram 2013:01:31:18:05:07:SJ cbx_altsyncram 2013:01:31:18:05:07:SJ cbx_cycloneii 2013:01:31:18:05:07:SJ cbx_fifo_common 2013:01:31:18:05:07:SJ cbx_lpm_add_sub 2013:01:31:18:05:07:SJ cbx_lpm_compare 2013:01:31:18:05:07:SJ cbx_lpm_counter 2013:01:31:18:05:07:SJ cbx_lpm_decode 2013:01:31:18:05:07:SJ cbx_lpm_mux 2013:01:31:18:05:07:SJ cbx_mgl 2013:01:31:18:08:27:SJ cbx_scfifo 2013:01:31:18:05:07:SJ cbx_stratix 2013:01:31:18:05:07:SJ cbx_stratixii 2013:01:31:18:05:07:SJ cbx_stratixiii 2013:01:31:18:05:07:SJ cbx_stratixv 2013:01:31:18:05:07:SJ cbx_util_mgl 2013:01:31:18:05:07:SJ VERSION_END + + +-- Copyright (C) 1991-2012 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +FUNCTION a_dpfifo_tq31 (clock, data[7..0], rreq, sclr, wreq) +RETURNS ( empty, full, q[7..0], usedw[6..0]); + +--synthesis_resources = lut 20 M9K 1 reg 35 +SUBDESIGN scfifo_a341 +( + clock : input; + data[7..0] : input; + empty : output; + full : output; + q[7..0] : output; + rdreq : input; + sclr : input; + usedw[6..0] : output; + wrreq : input; +) +VARIABLE + dpfifo : a_dpfifo_tq31; + +BEGIN + dpfifo.clock = clock; + dpfifo.data[] = data[]; + dpfifo.rreq = rdreq; + dpfifo.sclr = sclr; + dpfifo.wreq = wrreq; + empty = dpfifo.empty; + full = dpfifo.full; + q[] = dpfifo.q[]; + usedw[] = dpfifo.usedw[]; +END; +--VALID FILE diff --git a/MCTEST/DE0-nano-HD/db/scfifo_jr21.tdf b/MCTEST/DE0-nano-HD/db/scfifo_jr21.tdf new file mode 100644 index 00000000..279ce76d --- /dev/null +++ b/MCTEST/DE0-nano-HD/db/scfifo_jr21.tdf @@ -0,0 +1,53 @@ +--scfifo DEVICE_FAMILY="Cyclone IV E" LPM_NUMWORDS=64 LPM_SHOWAHEAD="OFF" LPM_WIDTH=8 LPM_WIDTHU=6 OPTIMIZE_FOR_SPEED=5 OVERFLOW_CHECKING="OFF" UNDERFLOW_CHECKING="OFF" USE_EAB="ON" aclr clock data empty full q rdreq usedw wrreq CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 CYCLONEII_M4K_COMPATIBILITY="ON" LOW_POWER_MODE="AUTO" lpm_hint="RAM_BLOCK_TYPE=AUTO" RAM_BLOCK_TYPE="AUTO" +--VERSION_BEGIN 12.1SP1 cbx_altdpram 2013:01:31:18:05:07:SJ cbx_altsyncram 2013:01:31:18:05:07:SJ cbx_cycloneii 2013:01:31:18:05:07:SJ cbx_fifo_common 2013:01:31:18:05:07:SJ cbx_lpm_add_sub 2013:01:31:18:05:07:SJ cbx_lpm_compare 2013:01:31:18:05:07:SJ cbx_lpm_counter 2013:01:31:18:05:07:SJ cbx_lpm_decode 2013:01:31:18:05:07:SJ cbx_lpm_mux 2013:01:31:18:05:07:SJ cbx_mgl 2013:01:31:18:08:27:SJ cbx_scfifo 2013:01:31:18:05:07:SJ cbx_stratix 2013:01:31:18:05:07:SJ cbx_stratixii 2013:01:31:18:05:07:SJ cbx_stratixiii 2013:01:31:18:05:07:SJ cbx_stratixv 2013:01:31:18:05:07:SJ cbx_util_mgl 2013:01:31:18:05:07:SJ VERSION_END + + +-- Copyright (C) 1991-2012 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +FUNCTION a_dpfifo_q131 (aclr, clock, data[7..0], rreq, sclr, wreq) +RETURNS ( empty, full, q[7..0], usedw[5..0]); + +--synthesis_resources = lut 18 M9K 1 reg 20 +SUBDESIGN scfifo_jr21 +( + aclr : input; + clock : input; + data[7..0] : input; + empty : output; + full : output; + q[7..0] : output; + rdreq : input; + usedw[5..0] : output; + wrreq : input; +) +VARIABLE + dpfifo : a_dpfifo_q131; + sclr : NODE; + +BEGIN + dpfifo.aclr = aclr; + dpfifo.clock = clock; + dpfifo.data[] = data[]; + dpfifo.rreq = rdreq; + dpfifo.sclr = sclr; + dpfifo.wreq = wrreq; + empty = dpfifo.empty; + full = dpfifo.full; + q[] = dpfifo.q[]; + sclr = GND; + usedw[] = dpfifo.usedw[]; +END; +--VALID FILE diff --git a/MCTEST/DE0-nano-HD/de0_nano_system.jdi b/MCTEST/DE0-nano-HD/de0_nano_system.jdi new file mode 100644 index 00000000..38a2d49e --- /dev/null +++ b/MCTEST/DE0-nano-HD/de0_nano_system.jdi @@ -0,0 +1,150 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/MCTEST/DE0-nano-HD/de0_nano_system.qpf b/MCTEST/DE0-nano-HD/de0_nano_system.qpf new file mode 100644 index 00000000..b0df7044 --- /dev/null +++ b/MCTEST/DE0-nano-HD/de0_nano_system.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2012 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Full Version +# Date created = 10:07:53 February 13, 2014 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "12.1" +DATE = "10:07:53 February 13, 2014" + +# Revisions + +PROJECT_REVISION = "de0_nano_system" diff --git a/MCTEST/DE0-nano-HD/de0_nano_system.qsf b/MCTEST/DE0-nano-HD/de0_nano_system.qsf new file mode 100644 index 00000000..ff07e51b --- /dev/null +++ b/MCTEST/DE0-nano-HD/de0_nano_system.qsf @@ -0,0 +1,212 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2012 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Full Version +# Date created = 10:07:53 February 13, 2014 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# de0_nano_system_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone IV E" +set_global_assignment -name DEVICE EP4CE22F17C6 +set_global_assignment -name TOP_LEVEL_ENTITY de0_nano_system +set_global_assignment -name ORIGINAL_QUARTUS_VERSION "12.1 SP1.33" +set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:07:53 FEBRUARY 13, 2014" +set_global_assignment -name LAST_QUARTUS_VERSION "12.1 SP1.33" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 +set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V +set_global_assignment -name VHDL_FILE de0_nano_system.vhd +set_global_assignment -name VHDL_FILE heartbeat.vhd +set_global_assignment -name SDC_FILE de0_nano_system.sdc +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_location_assignment PIN_R8 -to CLOCK_50 +set_location_assignment PIN_A15 -to LED[0] +set_location_assignment PIN_A13 -to LED[1] +set_location_assignment PIN_B13 -to LED[2] +set_location_assignment PIN_A11 -to LED[3] +set_location_assignment PIN_D1 -to LED[4] +set_location_assignment PIN_F3 -to LED[5] +set_location_assignment PIN_B1 -to LED[6] +set_location_assignment PIN_L3 -to LED[7] +set_location_assignment PIN_J15 -to KEY[0] +set_location_assignment PIN_E1 -to KEY[1] +set_location_assignment PIN_M1 -to SW[0] +set_location_assignment PIN_T8 -to SW[1] +set_location_assignment PIN_B9 -to SW[2] +set_location_assignment PIN_M15 -to SW[3] +set_location_assignment PIN_P2 -to DRAM_ADDR[0] +set_location_assignment PIN_N5 -to DRAM_ADDR[1] +set_location_assignment PIN_N6 -to DRAM_ADDR[2] +set_location_assignment PIN_M8 -to DRAM_ADDR[3] +set_location_assignment PIN_P8 -to DRAM_ADDR[4] +set_location_assignment PIN_T7 -to DRAM_ADDR[5] +set_location_assignment PIN_N8 -to DRAM_ADDR[6] +set_location_assignment PIN_T6 -to DRAM_ADDR[7] +set_location_assignment PIN_R1 -to DRAM_ADDR[8] +set_location_assignment PIN_P1 -to DRAM_ADDR[9] +set_location_assignment PIN_N2 -to DRAM_ADDR[10] +set_location_assignment PIN_N1 -to DRAM_ADDR[11] +set_location_assignment PIN_L4 -to DRAM_ADDR[12] +set_location_assignment PIN_M7 -to DRAM_BA[0] +set_location_assignment PIN_M6 -to DRAM_BA[1] +set_location_assignment PIN_L7 -to DRAM_CKE +set_location_assignment PIN_R4 -to DRAM_CLK +set_location_assignment PIN_P6 -to DRAM_CS_N +set_location_assignment PIN_G2 -to DRAM_DQ[0] +set_location_assignment PIN_G1 -to DRAM_DQ[1] +set_location_assignment PIN_L8 -to DRAM_DQ[2] +set_location_assignment PIN_K5 -to DRAM_DQ[3] +set_location_assignment PIN_K2 -to DRAM_DQ[4] +set_location_assignment PIN_J2 -to DRAM_DQ[5] +set_location_assignment PIN_J1 -to DRAM_DQ[6] +set_location_assignment PIN_R7 -to DRAM_DQ[7] +set_location_assignment PIN_T4 -to DRAM_DQ[8] +set_location_assignment PIN_T2 -to DRAM_DQ[9] +set_location_assignment PIN_T3 -to DRAM_DQ[10] +set_location_assignment PIN_R3 -to DRAM_DQ[11] +set_location_assignment PIN_R5 -to DRAM_DQ[12] +set_location_assignment PIN_P3 -to DRAM_DQ[13] +set_location_assignment PIN_N3 -to DRAM_DQ[14] +set_location_assignment PIN_K1 -to DRAM_DQ[15] +set_location_assignment PIN_R6 -to DRAM_DQM[0] +set_location_assignment PIN_T5 -to DRAM_DQM[1] +set_location_assignment PIN_L1 -to DRAM_CAS_N +set_location_assignment PIN_L2 -to DRAM_RAS_N +set_location_assignment PIN_C2 -to DRAM_WE_N +set_location_assignment PIN_F2 -to I2C_SCLK +set_location_assignment PIN_F1 -to I2C_SDAT +set_location_assignment PIN_G5 -to G_SENSOR_CS_N +set_location_assignment PIN_M2 -to G_SENSOR_INT +set_location_assignment PIN_A10 -to ADC_CS_N +set_location_assignment PIN_B10 -to ADC_SADDR +set_location_assignment PIN_B14 -to ADC_SCLK +set_location_assignment PIN_A9 -to ADC_SDAT +set_location_assignment PIN_A14 -to GPIO_2[0] +set_location_assignment PIN_B16 -to GPIO_2[1] +set_location_assignment PIN_C14 -to GPIO_2[2] +set_location_assignment PIN_C16 -to GPIO_2[3] +set_location_assignment PIN_C15 -to GPIO_2[4] +set_location_assignment PIN_D16 -to GPIO_2[5] +set_location_assignment PIN_D15 -to GPIO_2[6] +set_location_assignment PIN_D14 -to GPIO_2[7] +set_location_assignment PIN_F15 -to GPIO_2[8] +set_location_assignment PIN_F16 -to GPIO_2[9] +set_location_assignment PIN_F14 -to GPIO_2[10] +set_location_assignment PIN_G16 -to GPIO_2[11] +set_location_assignment PIN_G15 -to GPIO_2[12] +set_location_assignment PIN_E15 -to GPIO_2_IN[0] +set_location_assignment PIN_E16 -to GPIO_2_IN[1] +set_location_assignment PIN_M16 -to GPIO_2_IN[2] +set_location_assignment PIN_A8 -to GPIO_0_IN[0] +set_location_assignment PIN_D3 -to GPIO_0[0] +set_location_assignment PIN_B8 -to GPIO_0_IN[1] +set_location_assignment PIN_C3 -to GPIO_0[1] +set_location_assignment PIN_A2 -to GPIO_0[2] +set_location_assignment PIN_A3 -to GPIO_0[3] +set_location_assignment PIN_B3 -to GPIO_0[4] +set_location_assignment PIN_B4 -to GPIO_0[5] +set_location_assignment PIN_A4 -to GPIO_0[6] +set_location_assignment PIN_B5 -to GPIO_0[7] +set_location_assignment PIN_A5 -to GPIO_0[8] +set_location_assignment PIN_D5 -to GPIO_0[9] +set_location_assignment PIN_B6 -to GPIO_0[10] +set_location_assignment PIN_A6 -to GPIO_0[11] +set_location_assignment PIN_B7 -to GPIO_0[12] +set_location_assignment PIN_D6 -to GPIO_0[13] +set_location_assignment PIN_A7 -to GPIO_0[14] +set_location_assignment PIN_C6 -to GPIO_0[15] +set_location_assignment PIN_C8 -to GPIO_0[16] +set_location_assignment PIN_E6 -to GPIO_0[17] +set_location_assignment PIN_E7 -to GPIO_0[18] +set_location_assignment PIN_D8 -to GPIO_0[19] +set_location_assignment PIN_E8 -to GPIO_0[20] +set_location_assignment PIN_F8 -to GPIO_0[21] +set_location_assignment PIN_F9 -to GPIO_0[22] +set_location_assignment PIN_E9 -to GPIO_0[23] +set_location_assignment PIN_C9 -to GPIO_0[24] +set_location_assignment PIN_D9 -to GPIO_0[25] +set_location_assignment PIN_E11 -to GPIO_0[26] +set_location_assignment PIN_E10 -to GPIO_0[27] +set_location_assignment PIN_C11 -to GPIO_0[28] +set_location_assignment PIN_B11 -to GPIO_0[29] +set_location_assignment PIN_A12 -to GPIO_0[30] +set_location_assignment PIN_D11 -to GPIO_0[31] +set_location_assignment PIN_D12 -to GPIO_0[32] +set_location_assignment PIN_B12 -to GPIO_0[33] +set_location_assignment PIN_T9 -to GPIO_1_IN[0] +set_location_assignment PIN_F13 -to GPIO_1[0] +set_location_assignment PIN_R9 -to GPIO_1_IN[1] +set_location_assignment PIN_T15 -to GPIO_1[1] +set_location_assignment PIN_T14 -to GPIO_1[2] +set_location_assignment PIN_T13 -to GPIO_1[3] +set_location_assignment PIN_R13 -to GPIO_1[4] +set_location_assignment PIN_T12 -to GPIO_1[5] +set_location_assignment PIN_R12 -to GPIO_1[6] +set_location_assignment PIN_T11 -to GPIO_1[7] +set_location_assignment PIN_T10 -to GPIO_1[8] +set_location_assignment PIN_R11 -to GPIO_1[9] +set_location_assignment PIN_P11 -to GPIO_1[10] +set_location_assignment PIN_R10 -to GPIO_1[11] +set_location_assignment PIN_N12 -to GPIO_1[12] +set_location_assignment PIN_P9 -to GPIO_1[13] +set_location_assignment PIN_N9 -to GPIO_1[14] +set_location_assignment PIN_N11 -to GPIO_1[15] +set_location_assignment PIN_L16 -to GPIO_1[16] +set_location_assignment PIN_K16 -to GPIO_1[17] +set_location_assignment PIN_R16 -to GPIO_1[18] +set_location_assignment PIN_L15 -to GPIO_1[19] +set_location_assignment PIN_P15 -to GPIO_1[20] +set_location_assignment PIN_P16 -to GPIO_1[21] +set_location_assignment PIN_R14 -to GPIO_1[22] +set_location_assignment PIN_N16 -to GPIO_1[23] +set_location_assignment PIN_N15 -to GPIO_1[24] +set_location_assignment PIN_P14 -to GPIO_1[25] +set_location_assignment PIN_L14 -to GPIO_1[26] +set_location_assignment PIN_N14 -to GPIO_1[27] +set_location_assignment PIN_M10 -to GPIO_1[28] +set_location_assignment PIN_L13 -to GPIO_1[29] +set_location_assignment PIN_J16 -to GPIO_1[30] +set_location_assignment PIN_K15 -to GPIO_1[31] +set_location_assignment PIN_J13 -to GPIO_1[32] +set_location_assignment PIN_J14 -to GPIO_1[33] +set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" +set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top +set_global_assignment -name QIP_FILE system/synthesis/system.qip +set_global_assignment -name QIP_FILE pll_sys.qip \ No newline at end of file diff --git a/MCTEST/DE0-nano-HD/de0_nano_system.qsf.bak b/MCTEST/DE0-nano-HD/de0_nano_system.qsf.bak new file mode 100644 index 00000000..8e84df19 --- /dev/null +++ b/MCTEST/DE0-nano-HD/de0_nano_system.qsf.bak @@ -0,0 +1,60 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2012 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Full Version +# Date created = 10:07:53 February 13, 2014 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# de0_nano_system_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone IV E" +set_global_assignment -name DEVICE EP4CE22F17C6 +set_global_assignment -name TOP_LEVEL_ENTITY de0_nano_system +set_global_assignment -name ORIGINAL_QUARTUS_VERSION "12.1 SP1.33" +set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:07:53 FEBRUARY 13, 2014" +set_global_assignment -name LAST_QUARTUS_VERSION "12.1 SP1.33" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 +set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V +set_global_assignment -name QIP_FILE system/synthesis/system.qip +set_global_assignment -name VHDL_FILE de0_nano_system.vhd +set_global_assignment -name VHDL_FILE heartbeat.vhd +set_global_assignment -name SDC_FILE de0_nano_system.sdc +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name QIP_FILE pll_sys.qip +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/MCTEST/DE0-nano-HD/de0_nano_system.qws b/MCTEST/DE0-nano-HD/de0_nano_system.qws new file mode 100644 index 00000000..63563b76 Binary files /dev/null and b/MCTEST/DE0-nano-HD/de0_nano_system.qws differ diff --git a/MCTEST/DE0-nano-HD/de0_nano_system.sdc b/MCTEST/DE0-nano-HD/de0_nano_system.sdc new file mode 100644 index 00000000..154ac75d --- /dev/null +++ b/MCTEST/DE0-nano-HD/de0_nano_system.sdc @@ -0,0 +1,94 @@ +#*************************************************************************** +# Copyright (c) 2012 by Michael Fischer. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# 3. Neither the name of the author nor the names of its contributors may +# be used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL +# THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +# THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +# SUCH DAMAGE. +# +#*************************************************************************** +# History: +# +# 01.08.2012 mifi First version +#*************************************************************************** + + +#*************************************************************************** +# Create Clock +#*************************************************************************** +create_clock -period 50MHz [get_ports CLOCK_50] +create_clock -period 10MHz -name {altera_reserved_tck} {altera_reserved_tck} + +#*************************************************************************** +# Create Generated Clock +#*************************************************************************** +derive_pll_clocks + +#*************************************************************************** +# Set Clock Latency +#*************************************************************************** + +#*************************************************************************** +# Set Clock Uncertainty +#*************************************************************************** +derive_clock_uncertainty + +#*************************************************************************** +# Set Input Delay +#*************************************************************************** + +#*************************************************************************** +# Set Output Delay +#*************************************************************************** + +#*************************************************************************** +# Set Clock Groups +#*************************************************************************** + +#*************************************************************************** +# Set False Path +#*************************************************************************** +set_false_path -from [get_clocks {altera_reserved_tck}] -to [get_clocks {altera_reserved_tck}] + +#*************************************************************************** +# Set Multicycle Path +#*************************************************************************** + +#*************************************************************************** +# Set Maximum Delay +#*************************************************************************** + +#*************************************************************************** +# Set Minimum Delay +#*************************************************************************** + +#*************************************************************************** +# Set Input Transition +#*************************************************************************** + +#*************************************************************************** +# Set Load +#*************************************************************************** + +#*** EOF *** \ No newline at end of file diff --git a/MCTEST/DE0-nano-HD/de0_nano_system.vhd b/MCTEST/DE0-nano-HD/de0_nano_system.vhd new file mode 100644 index 00000000..b651072e --- /dev/null +++ b/MCTEST/DE0-nano-HD/de0_nano_system.vhd @@ -0,0 +1,199 @@ +--***************************************************************************** +-- ARCap +-- Modified 2014 by Amshu Gongal, Kenan Kigunda +-- Last Updated: February 2, 2014 +--***************************************************************************** + +--***************************************************************************** +--* Copyright (c) 2012 by Michael Fischer. All rights reserved. +--* +--* Redistribution and use in source and binary forms, with or without +--* modification, are permitted provided that the following conditions +--* are met: +--* +--* 1. Redistributions of source code must retain the above copyright +--* notice, this list of conditions and the following disclaimer. +--* 2. Redistributions in binary form must reproduce the above copyright +--* notice, this list of conditions and the following disclaimer in the +--* documentation and/or other materials provided with the distribution. +--* 3. Neither the name of the author nor the names of its contributors may +--* be used to endorse or promote products derived from this software +--* without specific prior written permission. +--* +--* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +--* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +--* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +--* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL +--* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +--* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +--* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +--* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +--* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +--* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +--* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +--* SUCH DAMAGE. +--* +--***************************************************************************** +--* History: +--* +--* 01.08.2012 mifi First version +--* 15.08.2012 mifi Added RESET port of the DM9000 +--***************************************************************************** + +--***************************************************************************** +--* DEFINE: Library * +--***************************************************************************** +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + + +--***************************************************************************** +--* DEFINE: Entity * +--***************************************************************************** + +entity de0_nano_system is + port ( + -- Input clock + CLOCK_50 : in std_logic; + + -- DRAM interface + DRAM_CLK : out std_logic; -- Master Clock + DRAM_CKE : out std_logic; -- Clock Enable + DRAM_CS_N : out std_logic; -- Chip Select + DRAM_RAS_N : out std_logic; -- Row Address Strobe + DRAM_CAS_N : out std_logic; -- Column Address Strobe + DRAM_WE_N : out std_logic; -- Write Enable + DRAM_DQ : inout std_logic_vector(15 downto 0); -- Data I/O (16 bits) + DRAM_DQM : out std_logic_vector(1 downto 0); -- Output Disable/Write Mask + DRAM_ADDR : out std_logic_vector(12 downto 0); -- Address Input (13 bits) + DRAM_BA : out std_logic_vector(1 downto 0); -- Bank Address + + -- Parallel I/O + LED : out std_logic_vector(7 downto 0); -- LEDs + KEY : in std_logic_vector(1 downto 0); -- Pushbuttons + SW : in std_logic_vector(3 downto 0); -- Switches + GPIO_0 : inout std_logic_vector(33 downto 0); -- General purpose + GPIO_1 : inout std_logic_vector(33 downto 0) + ); +end entity de0_nano_system; + + +--***************************************************************************** +--* DEFINE: Architecture * +--***************************************************************************** + +architecture syn of de0_nano_system is + + -- + -- Define all components which are included here + -- + + component pll_sys + port ( + inclk0 : in std_logic := '0'; + c0 : out std_logic ; + c1 : out std_logic ; + c2 : out std_logic ; + locked : out std_logic + ); + end component pll_sys; + + + component heartbeat is + port ( + clk : in std_logic; + counter_out : out std_logic + ); + end component heartbeat; + + + component system is + port ( + clk_clk : in std_logic := 'X'; -- clk + reset_reset_n : in std_logic := 'X'; -- reset_n + uart_0_rxd : in std_logic := 'X'; -- rxd + uart_0_txd : out std_logic; -- txd + + rs232_motor_txd : out std_logic; -- txd + rs232_motor_rxd : in std_logic := 'X'; -- rxd + + pio_led_export : out std_logic_vector(6 downto 0); -- export + pio_key_export : in std_logic_vector(1 downto 0) := (others => 'X'); -- export + pio_sw_export : in std_logic_vector(3 downto 0) := (others => 'X'); -- export + pio_motor_rst_export : out std_logic; + sdram_addr : out std_logic_vector(12 downto 0); -- addr + sdram_ba : out std_logic_vector(1 downto 0); -- ba + sdram_cas_n : out std_logic; -- cas_n + sdram_cke : out std_logic; -- cke + sdram_cs_n : out std_logic; -- cs_n + sdram_dq : inout std_logic_vector(15 downto 0) := (others => 'X'); -- dq + sdram_dqm : out std_logic_vector(1 downto 0); -- dqm + sdram_ras_n : out std_logic; -- ras_n + sdram_we_n : out std_logic -- we_n + ); + end component system; + + + -- + -- Define all local signals (like static data) here + -- + signal clk_10 : std_logic; + signal clk_sys : std_logic; + signal pll_locked : std_logic; +-- signal sdram_ba : std_logic_vector(1 downto 0); +-- signal sdram_dqm : std_logic_vector(1 downto 0); + +begin + + inst_pll_sys : pll_sys + port map ( + inclk0 => CLOCK_50, + c0 => clk_sys, + c1 => DRAM_CLK, + c2 => clk_10, + locked => pll_locked + ); + + inst_heartbeat : heartbeat + port map ( + clk => clk_10, + counter_out => LED(7) + ); + + inst_cpu : system + port map ( + clk_clk => clk_sys, + reset_reset_n => pll_locked, + + uart_0_rxd => GPIO_0(1), + uart_0_txd => GPIO_0(0), + + rs232_motor_txd => GPIO_1(12), -- Pin 17 + rs232_motor_rxd =>GPIO_1(24), -- Pin 31 + + sdram_addr => DRAM_ADDR, + sdram_ba => DRAM_BA, + sdram_cas_n => DRAM_CAS_N, + sdram_cke => DRAM_CKE, + sdram_cs_n => DRAM_CS_N, + sdram_dq => DRAM_DQ, + sdram_dqm => DRAM_DQM, + sdram_ras_n => DRAM_RAS_N, + sdram_we_n => DRAM_WE_N, + + pio_motor_rst_export => GPIO_1(26), -- PIN 33 + pio_led_export => LED(6 downto 0), + pio_key_export => KEY, + pio_sw_export => SW + ); + + -- DRAM_BA_1 <= sdram_ba(1); + -- DRAM_BA_0 <= sdram_ba(0); + + -- DRAM_DQMU <= sdram_dqm(1); + -- DRAM_DQML <= sdram_dqm(0); + +end architecture syn; + +-- *** EOF *** diff --git a/MCTEST/DE0-nano-HD/de0_nano_system.vhd.bak b/MCTEST/DE0-nano-HD/de0_nano_system.vhd.bak new file mode 100644 index 00000000..2506d386 --- /dev/null +++ b/MCTEST/DE0-nano-HD/de0_nano_system.vhd.bak @@ -0,0 +1,278 @@ +--***************************************************************************** +--* Copyright (c) 2012 by Michael Fischer. All rights reserved. +--* +--* Redistribution and use in source and binary forms, with or without +--* modification, are permitted provided that the following conditions +--* are met: +--* +--* 1. Redistributions of source code must retain the above copyright +--* notice, this list of conditions and the following disclaimer. +--* 2. Redistributions in binary form must reproduce the above copyright +--* notice, this list of conditions and the following disclaimer in the +--* documentation and/or other materials provided with the distribution. +--* 3. Neither the name of the author nor the names of its contributors may +--* be used to endorse or promote products derived from this software +--* without specific prior written permission. +--* +--* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +--* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +--* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +--* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL +--* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +--* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +--* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +--* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +--* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +--* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +--* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +--* SUCH DAMAGE. +--* +--***************************************************************************** +--* History: +--* +--* 01.08.2012 mifi First version +--* 15.08.2012 mifi Added RESET port of the DM9000 +--***************************************************************************** + +--***************************************************************************** +--* DEFINE: Library * +--***************************************************************************** +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + + +--***************************************************************************** +--* DEFINE: Entity * +--***************************************************************************** + +entity de0_nano_system is + port ( + -- + -- Input clock + -- + CLOCK_50 : in std_logic; + + -- + -- SDRAM interface, + -- here a IS42S16160B (143MHz@CL-3) is used. + -- Reference is made to ISSI datasheet: + -- IS42S16160B, 12/14/05 + -- + SDRAM_CLK : out std_logic; -- Master Clock + SDRAM_CKE : out std_logic; -- Clock Enable + SDRAM_CS_N : out std_logic; -- Chip Select + SDRAM_RAS_N : out std_logic; -- Row Address Strobe + SDRAM_CAS_N : out std_logic; -- Column Address Strobe + SDRAM_WE_N : out std_logic; -- Write Enable + SDRAM_DQ : inout std_logic_vector(15 downto 0); -- Data I/O (16 bits) + SDRAM_DQML : out std_logic; -- Output Disable / Write Mask (low) + SDRAM_DQMU : out std_logic; -- Output Disable / Write Mask (high) + SDRAM_ADDR : out std_logic_vector(12 downto 0); -- Address Input (13 bits) + SDRAM_BA_0 : out std_logic; -- Bank Address 0 + SDRAM_BA_1 : out std_logic; -- Bank Address 1 + + -- + -- EPCS + -- + EPCS_DCLK : out std_logic; + EPCS_NCSO : out std_logic; + EPCS_ASDO : out std_logic; + EPCS_DATA0 : in std_logic; + + -- + -- LEDs, green and heartbeat + -- + LED_GREEN : out std_logic_vector(6 downto 0); + LED_HEARTBEAT : out std_logic; + + -- + -- Swithes and keys + -- + KEY : in std_logic_vector(1 downto 0); + SW : in std_logic_vector(3 downto 0); + + -- + -- UART_0 + -- + UART_TXD : out std_logic; + UART_RXD : in std_logic; + + -- + -- DM9000 + -- + ENET_CMD : out std_logic; + ENET_DQ : inout std_logic_vector(15 downto 0); + ENET_CE_N : out std_logic; + ENET_WE_N : out std_logic; + ENET_OE_N : out std_logic; + ENET_RST_N : out std_logic; + ENET_INT : in std_logic; + + -- + -- VSCODEC + -- + VS_XRESET : out std_logic; + VS_XCS : out std_logic; + VS_XDCS : out std_logic; + VS_DREQ : in std_logic; + VS_SCLK : out std_logic; + VS_SI : out std_logic; + VS_SO : in std_logic + + ); +end entity de0_nano_system; + + +--***************************************************************************** +--* DEFINE: Architecture * +--***************************************************************************** + +architecture syn of de0_nano_system is + + -- + -- Define all components which are included here + -- + + component pll_sys + port ( + inclk0 : in std_logic := '0'; + c0 : out std_logic ; + c1 : out std_logic ; + c2 : out std_logic ; + locked : out std_logic + ); + end component pll_sys; + + + component heartbeat is + port ( + clk : in std_logic; + counter_out : out std_logic + ); + end component heartbeat; + + + component system is + port ( + clk_clk : in std_logic := 'X'; -- clk + reset_reset_n : in std_logic := 'X'; -- reset_n + uart_0_rxd : in std_logic := 'X'; -- rxd + uart_0_txd : out std_logic; -- txd + pio_led_green_export : out std_logic_vector(6 downto 0); -- export + pio_key_export : in std_logic_vector(1 downto 0) := (others => 'X'); -- export + pio_sw_export : in std_logic_vector(3 downto 0) := (others => 'X'); -- export + sdram_addr : out std_logic_vector(12 downto 0); -- addr + sdram_ba : out std_logic_vector(1 downto 0); -- ba + sdram_cas_n : out std_logic; -- cas_n + sdram_cke : out std_logic; -- cke + sdram_cs_n : out std_logic; -- cs_n + sdram_dq : inout std_logic_vector(15 downto 0) := (others => 'X'); -- dq + sdram_dqm : out std_logic_vector(1 downto 0); -- dqm + sdram_ras_n : out std_logic; -- ras_n + sdram_we_n : out std_logic; -- we_n + dm9000e_CMD : out std_logic; -- CMD + dm9000e_DATA : inout std_logic_vector(15 downto 0) := (others => 'X'); -- DATA + dm9000e_WE_N : out std_logic; -- WE_N + dm9000e_OE_N : out std_logic; -- OE_N + dm9000e_CE_N : out std_logic; -- CE_N + dm9000e_INT : in std_logic := 'X'; -- INT + dm9000e_RESET_N : out std_logic; -- RESET_N + epcs_dclk : out std_logic; -- dclk + epcs_sce : out std_logic; -- sce + epcs_sdo : out std_logic; -- sdo + epcs_data0 : in std_logic := 'X'; -- data0 + pio_int3_export : in std_logic := 'X'; -- export + spi_0_MISO : in std_logic := 'X'; -- MISO + spi_0_MOSI : out std_logic; -- MOSI + spi_0_SCLK : out std_logic; -- SCLK + spi_0_SS_n : out std_logic; -- SS_n + pio_vscodec_export : out std_logic_vector(2 downto 0) -- export + ); + end component system; + + + -- + -- Define all local signals (like static data) here + -- + signal clk_10 : std_logic; + signal clk_sys : std_logic; + signal pll_locked : std_logic; + signal sdram_ba : std_logic_vector(1 downto 0); + signal sdram_dqm : std_logic_vector(1 downto 0); + signal vs_pio : std_logic_vector(2 downto 0); + signal spi_cs_n : std_logic; + +begin + + inst_pll_sys : pll_sys + port map ( + inclk0 => CLOCK_50, + c0 => clk_sys, + c1 => SDRAM_CLK, + c2 => clk_10, + locked => pll_locked + ); + + inst_heartbeat : heartbeat + port map ( + clk => clk_10, + counter_out => LED_HEARTBEAT + ); + + inst_cpu : system + port map ( + clk_clk => clk_sys, + reset_reset_n => pll_locked, + + uart_0_rxd => UART_RXD, + uart_0_txd => UART_TXD, + + sdram_addr => SDRAM_ADDR, + sdram_ba => sdram_ba, + sdram_cas_n => SDRAM_CAS_N, + sdram_cke => SDRAM_CKE, + sdram_cs_n => SDRAM_CS_N, + sdram_dq => SDRAM_DQ, + sdram_dqm => sdram_dqm, + sdram_ras_n => SDRAM_RAS_N, + sdram_we_n => SDRAM_WE_N, + + epcs_dclk => EPCS_DCLK, + epcs_sce => EPCS_NCSO, + epcs_sdo => EPCS_ASDO, + epcs_data0 => EPCS_DATA0, + + dm9000e_CMD => ENET_CMD, + dm9000e_DATA => ENET_DQ, + dm9000e_WE_N => ENET_WE_N, + dm9000e_OE_N => ENET_OE_N, + dm9000e_CE_N => ENET_CE_N, + dm9000e_INT => ENET_INT, + dm9000e_RESET_N => ENET_RST_N, + + pio_led_green_export => LED_GREEN, + pio_key_export => KEY, + pio_sw_export => SW, + + pio_int3_export => VS_DREQ, + spi_0_MISO => VS_SO, + spi_0_MOSI => VS_SI, + spi_0_SCLK => VS_SCLK, + spi_0_SS_n => spi_cs_n, + pio_vscodec_export => vs_pio + ); + + SDRAM_BA_1 <= sdram_ba(1); + SDRAM_BA_0 <= sdram_ba(0); + + SDRAM_DQMU <= sdram_dqm(1); + SDRAM_DQML <= sdram_dqm(0); + + VS_XRESET <= vs_pio(0); + VS_XCS <= vs_pio(1); + VS_XDCS <= vs_pio(2); + +end architecture syn; + +-- *** EOF *** diff --git a/MCTEST/DE0-nano-HD/greybox_tmp/cbx_args.txt b/MCTEST/DE0-nano-HD/greybox_tmp/cbx_args.txt new file mode 100644 index 00000000..1ff9d7d5 --- /dev/null +++ b/MCTEST/DE0-nano-HD/greybox_tmp/cbx_args.txt @@ -0,0 +1,71 @@ +BANDWIDTH_TYPE=AUTO +CLK0_DIVIDE_BY=1 +CLK0_DUTY_CYCLE=50 +CLK0_MULTIPLY_BY=2 +CLK0_PHASE_SHIFT=0 +CLK1_DIVIDE_BY=1 +CLK1_DUTY_CYCLE=50 +CLK1_MULTIPLY_BY=2 +CLK1_PHASE_SHIFT=-1500 +CLK2_DIVIDE_BY=5 +CLK2_DUTY_CYCLE=50 +CLK2_MULTIPLY_BY=1 +CLK2_PHASE_SHIFT=0 +COMPENSATE_CLOCK=CLK0 +INCLK0_INPUT_FREQUENCY=20000 +INTENDED_DEVICE_FAMILY="Cyclone IV E" +LPM_TYPE=altpll +OPERATION_MODE=NORMAL +PLL_TYPE=AUTO +PORT_ACTIVECLOCK=PORT_UNUSED +PORT_ARESET=PORT_USED +PORT_CLKBAD0=PORT_UNUSED +PORT_CLKBAD1=PORT_UNUSED +PORT_CLKLOSS=PORT_UNUSED +PORT_CLKSWITCH=PORT_UNUSED +PORT_CONFIGUPDATE=PORT_UNUSED +PORT_FBIN=PORT_UNUSED +PORT_INCLK0=PORT_USED +PORT_INCLK1=PORT_UNUSED +PORT_LOCKED=PORT_USED +PORT_PFDENA=PORT_UNUSED +PORT_PHASECOUNTERSELECT=PORT_UNUSED +PORT_PHASEDONE=PORT_UNUSED +PORT_PHASESTEP=PORT_UNUSED +PORT_PHASEUPDOWN=PORT_UNUSED +PORT_PLLENA=PORT_UNUSED +PORT_SCANACLR=PORT_UNUSED +PORT_SCANCLK=PORT_UNUSED +PORT_SCANCLKENA=PORT_UNUSED +PORT_SCANDATA=PORT_UNUSED +PORT_SCANDATAOUT=PORT_UNUSED +PORT_SCANDONE=PORT_UNUSED +PORT_SCANREAD=PORT_UNUSED +PORT_SCANWRITE=PORT_UNUSED +PORT_clk0=PORT_USED +PORT_clk1=PORT_USED +PORT_clk2=PORT_USED +PORT_clk3=PORT_UNUSED +PORT_clk4=PORT_UNUSED +PORT_clk5=PORT_UNUSED +PORT_clkena0=PORT_UNUSED +PORT_clkena1=PORT_UNUSED +PORT_clkena2=PORT_UNUSED +PORT_clkena3=PORT_UNUSED +PORT_clkena4=PORT_UNUSED +PORT_clkena5=PORT_UNUSED +PORT_extclk0=PORT_UNUSED +PORT_extclk1=PORT_UNUSED +PORT_extclk2=PORT_UNUSED +PORT_extclk3=PORT_UNUSED +SELF_RESET_ON_LOSS_LOCK=ON +WIDTH_CLOCK=5 +DEVICE_FAMILY="Cyclone IV E" +CBX_AUTO_BLACKBOX=ALL +areset +inclk +inclk +clk +clk +clk +locked diff --git a/MCTEST/DE0-nano-HD/heartbeat.vhd b/MCTEST/DE0-nano-HD/heartbeat.vhd new file mode 100644 index 00000000..7d1f71a3 --- /dev/null +++ b/MCTEST/DE0-nano-HD/heartbeat.vhd @@ -0,0 +1,88 @@ +--***************************************************************************** +--* Copyright (c) 2012 by Michael Fischer. All rights reserved. +--* +--* Redistribution and use in source and binary forms, with or without +--* modification, are permitted provided that the following conditions +--* are met: +--* +--* 1. Redistributions of source code must retain the above copyright +--* notice, this list of conditions and the following disclaimer. +--* 2. Redistributions in binary form must reproduce the above copyright +--* notice, this list of conditions and the following disclaimer in the +--* documentation and/or other materials provided with the distribution. +--* 3. Neither the name of the author nor the names of its contributors may +--* be used to endorse or promote products derived from this software +--* without specific prior written permission. +--* +--* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +--* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +--* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +--* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL +--* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +--* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +--* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +--* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +--* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +--* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +--* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +--* SUCH DAMAGE. +--* +--***************************************************************************** +--* History: +--* +--* 14.07.2011 mifi First Version +--***************************************************************************** + + +--***************************************************************************** +--* DEFINE: Library * +--***************************************************************************** +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + + +--***************************************************************************** +--* DEFINE: Entity * +--***************************************************************************** + +entity heartbeat is + port( + clk : in std_logic; + counter_out : out std_logic + ); +end entity heartbeat; + + +--***************************************************************************** +--* DEFINE: Architecture * +--***************************************************************************** + +architecture syn of heartbeat is + + -- + -- Define all components which are included here + -- + + -- + -- Define all local signals (like static data) here + -- + + signal counter_data : std_logic_vector(31 downto 0) := (others => '0'); + +begin + + process(clk) + begin + + if rising_edge(clk) then + counter_data <= std_logic_vector(unsigned(counter_data) + 1); + end if; + + end process; + + counter_out <= counter_data(21); + +end architecture syn; + +-- *** EOF *** diff --git a/MCTEST/DE0-nano-HD/incremental_db/README b/MCTEST/DE0-nano-HD/incremental_db/README new file mode 100644 index 00000000..9f62dcda --- /dev/null +++ b/MCTEST/DE0-nano-HD/incremental_db/README @@ -0,0 +1,11 @@ +This folder contains data for incremental compilation. + +The compiled_partitions sub-folder contains previous compilation results for each partition. +As long as this folder is preserved, incremental compilation results from earlier compiles +can be re-used. To perform a clean compilation from source files for all partitions, both +the db and incremental_db folder should be removed. + +The imported_partitions sub-folder contains the last imported QXP for each imported partition. +As long as this folder is preserved, imported partitions will be automatically re-imported +when the db or incremental_db/compiled_partitions folders are removed. + diff --git a/MCTEST/DE0-nano-HD/incremental_db/compiled_partitions/de0_nano_system.autoh_e40e1.map.cdb b/MCTEST/DE0-nano-HD/incremental_db/compiled_partitions/de0_nano_system.autoh_e40e1.map.cdb new file mode 100644 index 00000000..0c08a08d Binary files /dev/null and b/MCTEST/DE0-nano-HD/incremental_db/compiled_partitions/de0_nano_system.autoh_e40e1.map.cdb differ diff --git a/MCTEST/DE0-nano-HD/incremental_db/compiled_partitions/de0_nano_system.autoh_e40e1.map.dpi b/MCTEST/DE0-nano-HD/incremental_db/compiled_partitions/de0_nano_system.autoh_e40e1.map.dpi new file mode 100644 index 00000000..89af9b0c Binary files /dev/null and b/MCTEST/DE0-nano-HD/incremental_db/compiled_partitions/de0_nano_system.autoh_e40e1.map.dpi differ diff --git a/MCTEST/DE0-nano-HD/incremental_db/compiled_partitions/de0_nano_system.autoh_e40e1.map.hdb b/MCTEST/DE0-nano-HD/incremental_db/compiled_partitions/de0_nano_system.autoh_e40e1.map.hdb new file mode 100644 index 00000000..c94c1f36 Binary files /dev/null and b/MCTEST/DE0-nano-HD/incremental_db/compiled_partitions/de0_nano_system.autoh_e40e1.map.hdb differ diff --git a/MCTEST/DE0-nano-HD/incremental_db/compiled_partitions/de0_nano_system.autoh_e40e1.map.kpt b/MCTEST/DE0-nano-HD/incremental_db/compiled_partitions/de0_nano_system.autoh_e40e1.map.kpt new file mode 100644 index 00000000..c4320c7d Binary files /dev/null and b/MCTEST/DE0-nano-HD/incremental_db/compiled_partitions/de0_nano_system.autoh_e40e1.map.kpt differ diff --git a/MCTEST/DE0-nano-HD/incremental_db/compiled_partitions/de0_nano_system.autoh_e40e1.map.logdb b/MCTEST/DE0-nano-HD/incremental_db/compiled_partitions/de0_nano_system.autoh_e40e1.map.logdb new file mode 100644 index 00000000..626799f0 --- /dev/null +++ b/MCTEST/DE0-nano-HD/incremental_db/compiled_partitions/de0_nano_system.autoh_e40e1.map.logdb @@ -0,0 +1 @@ +v1 diff --git a/MCTEST/DE0-nano-HD/incremental_db/compiled_partitions/de0_nano_system.db_info b/MCTEST/DE0-nano-HD/incremental_db/compiled_partitions/de0_nano_system.db_info new file mode 100644 index 00000000..097b42ea --- /dev/null +++ b/MCTEST/DE0-nano-HD/incremental_db/compiled_partitions/de0_nano_system.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Full Version +Version_Index = 285274881 +Creation_Time = Thu Feb 13 11:18:38 2014 diff --git a/MCTEST/DE0-nano-HD/incremental_db/compiled_partitions/de0_nano_system.root_partition.cmp.ammdb b/MCTEST/DE0-nano-HD/incremental_db/compiled_partitions/de0_nano_system.root_partition.cmp.ammdb new file mode 100644 index 00000000..9a14b393 Binary files /dev/null and b/MCTEST/DE0-nano-HD/incremental_db/compiled_partitions/de0_nano_system.root_partition.cmp.ammdb differ diff --git a/MCTEST/DE0-nano-HD/incremental_db/compiled_partitions/de0_nano_system.root_partition.cmp.cdb b/MCTEST/DE0-nano-HD/incremental_db/compiled_partitions/de0_nano_system.root_partition.cmp.cdb new file mode 100644 index 00000000..16fc018b Binary files /dev/null and b/MCTEST/DE0-nano-HD/incremental_db/compiled_partitions/de0_nano_system.root_partition.cmp.cdb differ diff --git a/MCTEST/DE0-nano-HD/incremental_db/compiled_partitions/de0_nano_system.root_partition.cmp.dfp b/MCTEST/DE0-nano-HD/incremental_db/compiled_partitions/de0_nano_system.root_partition.cmp.dfp new file mode 100644 index 00000000..b1c67d62 Binary files /dev/null and b/MCTEST/DE0-nano-HD/incremental_db/compiled_partitions/de0_nano_system.root_partition.cmp.dfp differ diff --git a/MCTEST/DE0-nano-HD/incremental_db/compiled_partitions/de0_nano_system.root_partition.cmp.hdb b/MCTEST/DE0-nano-HD/incremental_db/compiled_partitions/de0_nano_system.root_partition.cmp.hdb new file mode 100644 index 00000000..19e40793 Binary files /dev/null and b/MCTEST/DE0-nano-HD/incremental_db/compiled_partitions/de0_nano_system.root_partition.cmp.hdb differ diff --git a/MCTEST/DE0-nano-HD/incremental_db/compiled_partitions/de0_nano_system.root_partition.cmp.kpt b/MCTEST/DE0-nano-HD/incremental_db/compiled_partitions/de0_nano_system.root_partition.cmp.kpt new file mode 100644 index 00000000..a49bae92 Binary files /dev/null and b/MCTEST/DE0-nano-HD/incremental_db/compiled_partitions/de0_nano_system.root_partition.cmp.kpt differ diff --git a/MCTEST/DE0-nano-HD/incremental_db/compiled_partitions/de0_nano_system.root_partition.cmp.logdb b/MCTEST/DE0-nano-HD/incremental_db/compiled_partitions/de0_nano_system.root_partition.cmp.logdb new file mode 100644 index 00000000..6a99313c --- /dev/null +++ b/MCTEST/DE0-nano-HD/incremental_db/compiled_partitions/de0_nano_system.root_partition.cmp.logdb @@ -0,0 +1,4 @@ +v1 +DSP_BALANCING_IMPLEMENTATION,DSP_BLOCKS,system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3, +DSP_BALANCING_IMPLEMENTATION,DSP_BLOCKS,system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3, +PORT_SWAPPING,PORT_SWAPPING_FINISHED,system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_mult2, diff --git a/MCTEST/DE0-nano-HD/incremental_db/compiled_partitions/de0_nano_system.root_partition.cmp.rcfdb b/MCTEST/DE0-nano-HD/incremental_db/compiled_partitions/de0_nano_system.root_partition.cmp.rcfdb new file mode 100644 index 00000000..6fba7610 Binary files /dev/null and b/MCTEST/DE0-nano-HD/incremental_db/compiled_partitions/de0_nano_system.root_partition.cmp.rcfdb differ diff --git a/MCTEST/DE0-nano-HD/incremental_db/compiled_partitions/de0_nano_system.root_partition.map.cdb b/MCTEST/DE0-nano-HD/incremental_db/compiled_partitions/de0_nano_system.root_partition.map.cdb new file mode 100644 index 00000000..7413dc59 Binary files /dev/null and b/MCTEST/DE0-nano-HD/incremental_db/compiled_partitions/de0_nano_system.root_partition.map.cdb differ diff --git a/MCTEST/DE0-nano-HD/incremental_db/compiled_partitions/de0_nano_system.root_partition.map.dpi b/MCTEST/DE0-nano-HD/incremental_db/compiled_partitions/de0_nano_system.root_partition.map.dpi new file mode 100644 index 00000000..9e3becd1 Binary files /dev/null and b/MCTEST/DE0-nano-HD/incremental_db/compiled_partitions/de0_nano_system.root_partition.map.dpi differ diff --git a/MCTEST/DE0-nano-HD/incremental_db/compiled_partitions/de0_nano_system.root_partition.map.hbdb.cdb b/MCTEST/DE0-nano-HD/incremental_db/compiled_partitions/de0_nano_system.root_partition.map.hbdb.cdb new file mode 100644 index 00000000..48ab82b0 Binary files /dev/null and b/MCTEST/DE0-nano-HD/incremental_db/compiled_partitions/de0_nano_system.root_partition.map.hbdb.cdb differ diff --git a/MCTEST/DE0-nano-HD/incremental_db/compiled_partitions/de0_nano_system.root_partition.map.hbdb.hb_info b/MCTEST/DE0-nano-HD/incremental_db/compiled_partitions/de0_nano_system.root_partition.map.hbdb.hb_info new file mode 100644 index 00000000..f5c15ccb Binary files /dev/null and b/MCTEST/DE0-nano-HD/incremental_db/compiled_partitions/de0_nano_system.root_partition.map.hbdb.hb_info differ diff --git a/MCTEST/DE0-nano-HD/incremental_db/compiled_partitions/de0_nano_system.root_partition.map.hbdb.hdb b/MCTEST/DE0-nano-HD/incremental_db/compiled_partitions/de0_nano_system.root_partition.map.hbdb.hdb new file mode 100644 index 00000000..e8596bb2 Binary files /dev/null and b/MCTEST/DE0-nano-HD/incremental_db/compiled_partitions/de0_nano_system.root_partition.map.hbdb.hdb differ diff --git a/MCTEST/DE0-nano-HD/incremental_db/compiled_partitions/de0_nano_system.root_partition.map.hbdb.sig b/MCTEST/DE0-nano-HD/incremental_db/compiled_partitions/de0_nano_system.root_partition.map.hbdb.sig new file mode 100644 index 00000000..72981453 --- /dev/null +++ b/MCTEST/DE0-nano-HD/incremental_db/compiled_partitions/de0_nano_system.root_partition.map.hbdb.sig @@ -0,0 +1 @@ +721507e1566b67c275f4e80c87812ce3 \ No newline at end of file diff --git a/MCTEST/DE0-nano-HD/incremental_db/compiled_partitions/de0_nano_system.root_partition.map.hdb b/MCTEST/DE0-nano-HD/incremental_db/compiled_partitions/de0_nano_system.root_partition.map.hdb new file mode 100644 index 00000000..6dcfec93 Binary files /dev/null and b/MCTEST/DE0-nano-HD/incremental_db/compiled_partitions/de0_nano_system.root_partition.map.hdb differ diff --git a/MCTEST/DE0-nano-HD/incremental_db/compiled_partitions/de0_nano_system.root_partition.map.kpt b/MCTEST/DE0-nano-HD/incremental_db/compiled_partitions/de0_nano_system.root_partition.map.kpt new file mode 100644 index 00000000..68e5f344 Binary files /dev/null and b/MCTEST/DE0-nano-HD/incremental_db/compiled_partitions/de0_nano_system.root_partition.map.kpt differ diff --git a/MCTEST/DE0-nano-HD/output_files/de0_nano_system.asm.rpt b/MCTEST/DE0-nano-HD/output_files/de0_nano_system.asm.rpt new file mode 100644 index 00000000..94a9a1d1 --- /dev/null +++ b/MCTEST/DE0-nano-HD/output_files/de0_nano_system.asm.rpt @@ -0,0 +1,128 @@ +Assembler report for de0_nano_system +Fri Mar 14 16:49:35 2014 +Quartus II 64-Bit Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Full Version + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Assembler Summary + 3. Assembler Settings + 4. Assembler Encrypted IP Cores Summary + 5. Assembler Generated Files + 6. Assembler Device Options: C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/output_files/de0_nano_system.sof + 7. Assembler Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2012 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++---------------------------------------------------------------+ +; Assembler Summary ; ++-----------------------+---------------------------------------+ +; Assembler Status ; Successful - Fri Mar 14 16:49:35 2014 ; +; Revision Name ; de0_nano_system ; +; Top-level Entity Name ; de0_nano_system ; +; Family ; Cyclone IV E ; +; Device ; EP4CE22F17C6 ; ++-----------------------+---------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------+ +; Assembler Settings ; ++-----------------------------------------------------------------------------+----------+---------------+ +; Option ; Setting ; Default Value ; ++-----------------------------------------------------------------------------+----------+---------------+ +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Generate compressed bitstreams ; On ; On ; +; Compression mode ; Off ; Off ; +; Clock source for configuration device ; Internal ; Internal ; +; Clock frequency of the configuration device ; 10 MHZ ; 10 MHz ; +; Divide clock frequency by ; 1 ; 1 ; +; Auto user code ; Off ; Off ; +; Use configuration device ; Off ; Off ; +; Configuration device ; Auto ; Auto ; +; Configuration device auto user code ; Off ; Off ; +; Generate Tabular Text File (.ttf) For Target Device ; Off ; Off ; +; Generate Raw Binary File (.rbf) For Target Device ; Off ; Off ; +; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off ; Off ; +; Hexadecimal Output File start address ; 0 ; 0 ; +; Hexadecimal Output File count direction ; Up ; Up ; +; Release clears before tri-states ; Off ; Off ; +; Auto-restart configuration after error ; On ; On ; +; Enable OCT_DONE ; Off ; Off ; +; Generate Serial Vector Format File (.svf) for Target Device ; Off ; Off ; +; Generate a JEDEC STAPL Format File (.jam) for Target Device ; Off ; Off ; +; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off ; Off ; +; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On ; On ; ++-----------------------------------------------------------------------------+----------+---------------+ + + ++-------------------------------------------------------+ +; Assembler Encrypted IP Cores Summary ; ++--------+-------------------------------+--------------+ +; Vendor ; IP Core Name ; License Type ; ++--------+-------------------------------+--------------+ +; Altera ; Nios II Processor (6AF7 00A2) ; Licensed ; +; Altera ; Signal Tap (6AF7 BCE1) ; Licensed ; +; Altera ; Signal Tap (6AF7 BCEC) ; Licensed ; ++--------+-------------------------------+--------------+ + + ++-----------------------------------------------------------------------------+ +; Assembler Generated Files ; ++-----------------------------------------------------------------------------+ +; File Name ; ++-----------------------------------------------------------------------------+ +; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/output_files/de0_nano_system.sof ; ++-----------------------------------------------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------+ +; Assembler Device Options: C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/output_files/de0_nano_system.sof ; ++----------------+--------------------------------------------------------------------------------------+ +; Option ; Setting ; ++----------------+--------------------------------------------------------------------------------------+ +; Device ; EP4CE22F17C6 ; +; JTAG usercode ; 0xFFFFFFFF ; +; Checksum ; 0x00461AAF ; ++----------------+--------------------------------------------------------------------------------------+ + + ++--------------------+ +; Assembler Messages ; ++--------------------+ +Info: ******************************************************************* +Info: Running Quartus II 64-Bit Assembler + Info: Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Full Version + Info: Processing started: Fri Mar 14 16:49:33 2014 +Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off de0_nano_system -c de0_nano_system +Info (115031): Writing out detailed assembly data for power analysis +Info (115030): Assembler is generating device programming files +Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings + Info: Peak virtual memory: 447 megabytes + Info: Processing ended: Fri Mar 14 16:49:35 2014 + Info: Elapsed time: 00:00:02 + Info: Total CPU time (on all processors): 00:00:02 + + diff --git a/MCTEST/DE0-nano-HD/output_files/de0_nano_system.cdf b/MCTEST/DE0-nano-HD/output_files/de0_nano_system.cdf new file mode 100644 index 00000000..1d4b1ec4 --- /dev/null +++ b/MCTEST/DE0-nano-HD/output_files/de0_nano_system.cdf @@ -0,0 +1,13 @@ +/* Quartus II 64-Bit Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Full Version */ +JedecChain; + FileRevision(JESD32A); + DefaultMfr(6E); + + P ActionCode(Cfg) + Device PartName(EP4CE22F17) Path("C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/output_files/") File("de0_nano_system.sof") MfrSpec(OpMask(1)); + +ChainEnd; + +AlteraBegin; + ChainType(JTAG); +AlteraEnd; diff --git a/MCTEST/DE0-nano-HD/output_files/de0_nano_system.done b/MCTEST/DE0-nano-HD/output_files/de0_nano_system.done new file mode 100644 index 00000000..d570f780 --- /dev/null +++ b/MCTEST/DE0-nano-HD/output_files/de0_nano_system.done @@ -0,0 +1 @@ +Fri Mar 14 16:49:43 2014 diff --git a/MCTEST/DE0-nano-HD/output_files/de0_nano_system.fit.rpt b/MCTEST/DE0-nano-HD/output_files/de0_nano_system.fit.rpt new file mode 100644 index 00000000..abbdff2c --- /dev/null +++ b/MCTEST/DE0-nano-HD/output_files/de0_nano_system.fit.rpt @@ -0,0 +1,3775 @@ +Fitter report for de0_nano_system +Fri Mar 14 16:49:30 2014 +Quartus II 64-Bit Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Full Version + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Fitter Summary + 3. Fitter Settings + 4. Parallel Compilation + 5. I/O Assignment Warnings + 6. Fitter Netlist Optimizations + 7. Ignored Assignments + 8. Incremental Compilation Preservation Summary + 9. Incremental Compilation Partition Settings + 10. Incremental Compilation Placement Preservation + 11. Pin-Out File + 12. Fitter Resource Usage Summary + 13. Fitter Partition Statistics + 14. Input Pins + 15. Output Pins + 16. Bidir Pins + 17. Dual Purpose and Dedicated Pins + 18. I/O Bank Usage + 19. All Package Pins + 20. PLL Summary + 21. PLL Usage + 22. Fitter Resource Utilization by Entity + 23. Delay Chain Summary + 24. Pad To Core Delay Chain Fanout + 25. Control Signals + 26. Global & Other Fast Signals + 27. Non-Global High Fan-Out Signals + 28. Fitter RAM Summary + 29. Fitter DSP Block Usage Summary + 30. DSP Block Details + 31. Other Routing Usage Summary + 32. LAB Logic Elements + 33. LAB-wide Signals + 34. LAB Signals Sourced + 35. LAB Signals Sourced Out + 36. LAB Distinct Inputs + 37. I/O Rules Summary + 38. I/O Rules Details + 39. I/O Rules Matrix + 40. Fitter Device Options + 41. Operating Settings and Conditions + 42. Estimated Delay Added for Hold Timing Summary + 43. Estimated Delay Added for Hold Timing Details + 44. Fitter Messages + 45. Fitter Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2012 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++----------------------------------------------------------------------------------------+ +; Fitter Summary ; ++------------------------------------+---------------------------------------------------+ +; Fitter Status ; Successful - Fri Mar 14 16:49:30 2014 ; +; Quartus II 64-Bit Version ; 12.1 Build 243 01/31/2013 SP 1.33 SJ Full Version ; +; Revision Name ; de0_nano_system ; +; Top-level Entity Name ; de0_nano_system ; +; Family ; Cyclone IV E ; +; Device ; EP4CE22F17C6 ; +; Timing Models ; Final ; +; Total logic elements ; 4,562 / 22,320 ( 20 % ) ; +; Total combinational functions ; 3,937 / 22,320 ( 18 % ) ; +; Dedicated logic registers ; 2,790 / 22,320 ( 13 % ) ; +; Total registers ; 2859 ; +; Total pins ; 122 / 154 ( 79 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 119,808 / 608,256 ( 20 % ) ; +; Embedded Multiplier 9-bit elements ; 4 / 132 ( 3 % ) ; +; Total PLLs ; 1 / 4 ( 25 % ) ; ++------------------------------------+---------------------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Settings ; ++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+ +; Option ; Setting ; Default Value ; ++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+ +; Device ; EP4CE22F17C6 ; ; +; Nominal Core Supply Voltage ; 1.2V ; ; +; Minimum Core Junction Temperature ; 0 ; ; +; Maximum Core Junction Temperature ; 85 ; ; +; Fit Attempts to Skip ; 0 ; 0.0 ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Auto Merge PLLs ; On ; On ; +; Router Timing Optimization Level ; Normal ; Normal ; +; Perform Clocking Topology Analysis During Routing ; Off ; Off ; +; Placement Effort Multiplier ; 1.0 ; 1.0 ; +; Router Effort Multiplier ; 1.0 ; 1.0 ; +; Optimize Hold Timing ; All Paths ; All Paths ; +; Optimize Multi-Corner Timing ; On ; On ; +; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; +; SSN Optimization ; Off ; Off ; +; Optimize Timing ; Normal compilation ; Normal compilation ; +; Optimize Timing for ECOs ; Off ; Off ; +; Regenerate full fit report during ECO compiles ; Off ; Off ; +; Optimize IOC Register Placement for Timing ; Normal ; Normal ; +; Limit to One Fitting Attempt ; Off ; Off ; +; Final Placement Optimizations ; Automatically ; Automatically ; +; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ; +; Fitter Initial Placement Seed ; 1 ; 1 ; +; PCI I/O ; Off ; Off ; +; Weak Pull-Up Resistor ; Off ; Off ; +; Enable Bus-Hold Circuitry ; Off ; Off ; +; Auto Packed Registers ; Auto ; Auto ; +; Auto Delay Chains ; On ; On ; +; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ; +; Allow Single-ended Buffer for Differential-XSTL Input ; Off ; Off ; +; Treat Bidirectional Pin as Output Pin ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ; +; Perform Register Duplication for Performance ; Off ; Off ; +; Perform Logic to Memory Mapping for Fitting ; Off ; Off ; +; Perform Register Retiming for Performance ; Off ; Off ; +; Perform Asynchronous Signal Pipelining ; Off ; Off ; +; Fitter Effort ; Auto Fit ; Auto Fit ; +; Physical Synthesis Effort Level ; Normal ; Normal ; +; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ; +; Auto Register Duplication ; Auto ; Auto ; +; Auto Global Clock ; On ; On ; +; Auto Global Register Control Signals ; On ; On ; +; Reserve all unused pins ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ; +; Synchronizer Identification ; Off ; Off ; +; Enable Beneficial Skew Optimization ; On ; On ; +; Optimize Design for Metastability ; On ; On ; +; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ; +; Enable input tri-state on active configuration pins in user mode ; Off ; Off ; ++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 8 ; +; Maximum allowed ; 4 ; +; ; ; +; Average used ; 2.45 ; +; Maximum used ; 4 ; +; ; ; +; Usage by Processor ; % Time Used ; +; 1 processor ; 100.0% ; +; 2-4 processors ; 18.9% ; +; 5-8 processors ; 0.0% ; ++----------------------------+-------------+ + + ++-----------------------------------------------+ +; I/O Assignment Warnings ; ++---------------+-------------------------------+ +; Pin Name ; Reason ; ++---------------+-------------------------------+ +; DRAM_CLK ; Incomplete set of assignments ; +; DRAM_CKE ; Incomplete set of assignments ; +; DRAM_CS_N ; Incomplete set of assignments ; +; DRAM_RAS_N ; Incomplete set of assignments ; +; DRAM_CAS_N ; Incomplete set of assignments ; +; DRAM_WE_N ; Incomplete set of assignments ; +; DRAM_DQM[0] ; Incomplete set of assignments ; +; DRAM_DQM[1] ; Incomplete set of assignments ; +; DRAM_ADDR[0] ; Incomplete set of assignments ; +; DRAM_ADDR[1] ; Incomplete set of assignments ; +; DRAM_ADDR[2] ; Incomplete set of assignments ; +; DRAM_ADDR[3] ; Incomplete set of assignments ; +; DRAM_ADDR[4] ; Incomplete set of assignments ; +; DRAM_ADDR[5] ; Incomplete set of assignments ; +; DRAM_ADDR[6] ; Incomplete set of assignments ; +; DRAM_ADDR[7] ; Incomplete set of assignments ; +; DRAM_ADDR[8] ; Incomplete set of assignments ; +; DRAM_ADDR[9] ; Incomplete set of assignments ; +; DRAM_ADDR[10] ; Incomplete set of assignments ; +; DRAM_ADDR[11] ; Incomplete set of assignments ; +; DRAM_ADDR[12] ; Incomplete set of assignments ; +; DRAM_BA[0] ; Incomplete set of assignments ; +; DRAM_BA[1] ; Incomplete set of assignments ; +; LED[0] ; Incomplete set of assignments ; +; LED[1] ; Incomplete set of assignments ; +; LED[2] ; Incomplete set of assignments ; +; LED[3] ; Incomplete set of assignments ; +; LED[4] ; Incomplete set of assignments ; +; LED[5] ; Incomplete set of assignments ; +; LED[6] ; Incomplete set of assignments ; +; LED[7] ; Incomplete set of assignments ; +; GPIO_0[2] ; Incomplete set of assignments ; +; GPIO_0[3] ; Incomplete set of assignments ; +; GPIO_0[4] ; Incomplete set of assignments ; +; GPIO_0[5] ; Incomplete set of assignments ; +; GPIO_0[6] ; Incomplete set of assignments ; +; GPIO_0[7] ; Incomplete set of assignments ; +; GPIO_0[8] ; Incomplete set of assignments ; +; GPIO_0[9] ; Incomplete set of assignments ; +; GPIO_0[10] ; Incomplete set of assignments ; +; GPIO_0[11] ; Incomplete set of assignments ; +; GPIO_0[12] ; Incomplete set of assignments ; +; GPIO_0[13] ; Incomplete set of assignments ; +; GPIO_0[14] ; Incomplete set of assignments ; +; GPIO_0[15] ; Incomplete set of assignments ; +; GPIO_0[16] ; Incomplete set of assignments ; +; GPIO_0[17] ; Incomplete set of assignments ; +; GPIO_0[18] ; Incomplete set of assignments ; +; GPIO_0[19] ; Incomplete set of assignments ; +; GPIO_0[20] ; Incomplete set of assignments ; +; GPIO_0[21] ; Incomplete set of assignments ; +; GPIO_0[22] ; Incomplete set of assignments ; +; GPIO_0[23] ; Incomplete set of assignments ; +; GPIO_0[24] ; Incomplete set of assignments ; +; GPIO_0[25] ; Incomplete set of assignments ; +; GPIO_0[26] ; Incomplete set of assignments ; +; GPIO_0[27] ; Incomplete set of assignments ; +; GPIO_0[28] ; Incomplete set of assignments ; +; GPIO_0[29] ; Incomplete set of assignments ; +; GPIO_0[30] ; Incomplete set of assignments ; +; GPIO_0[31] ; Incomplete set of assignments ; +; GPIO_0[32] ; Incomplete set of assignments ; +; GPIO_0[33] ; Incomplete set of assignments ; +; GPIO_1[0] ; Incomplete set of assignments ; +; GPIO_1[1] ; Incomplete set of assignments ; +; GPIO_1[2] ; Incomplete set of assignments ; +; GPIO_1[3] ; Incomplete set of assignments ; +; GPIO_1[4] ; Incomplete set of assignments ; +; GPIO_1[5] ; Incomplete set of assignments ; +; GPIO_1[6] ; Incomplete set of assignments ; +; GPIO_1[7] ; Incomplete set of assignments ; +; GPIO_1[8] ; Incomplete set of assignments ; +; GPIO_1[9] ; Incomplete set of assignments ; +; GPIO_1[10] ; Incomplete set of assignments ; +; GPIO_1[11] ; Incomplete set of assignments ; +; GPIO_1[13] ; Incomplete set of assignments ; +; GPIO_1[14] ; Incomplete set of assignments ; +; GPIO_1[15] ; Incomplete set of assignments ; +; GPIO_1[16] ; Incomplete set of assignments ; +; GPIO_1[17] ; Incomplete set of assignments ; +; GPIO_1[18] ; Incomplete set of assignments ; +; GPIO_1[19] ; Incomplete set of assignments ; +; GPIO_1[20] ; Incomplete set of assignments ; +; GPIO_1[21] ; Incomplete set of assignments ; +; GPIO_1[22] ; Incomplete set of assignments ; +; GPIO_1[23] ; Incomplete set of assignments ; +; GPIO_1[25] ; Incomplete set of assignments ; +; GPIO_1[27] ; Incomplete set of assignments ; +; GPIO_1[28] ; Incomplete set of assignments ; +; GPIO_1[29] ; Incomplete set of assignments ; +; GPIO_1[30] ; Incomplete set of assignments ; +; GPIO_1[31] ; Incomplete set of assignments ; +; GPIO_1[32] ; Incomplete set of assignments ; +; GPIO_1[33] ; Incomplete set of assignments ; +; DRAM_DQ[0] ; Incomplete set of assignments ; +; DRAM_DQ[1] ; Incomplete set of assignments ; +; DRAM_DQ[2] ; Incomplete set of assignments ; +; DRAM_DQ[3] ; Incomplete set of assignments ; +; DRAM_DQ[4] ; Incomplete set of assignments ; +; DRAM_DQ[5] ; Incomplete set of assignments ; +; DRAM_DQ[6] ; Incomplete set of assignments ; +; DRAM_DQ[7] ; Incomplete set of assignments ; +; DRAM_DQ[8] ; Incomplete set of assignments ; +; DRAM_DQ[9] ; Incomplete set of assignments ; +; DRAM_DQ[10] ; Incomplete set of assignments ; +; DRAM_DQ[11] ; Incomplete set of assignments ; +; DRAM_DQ[12] ; Incomplete set of assignments ; +; DRAM_DQ[13] ; Incomplete set of assignments ; +; DRAM_DQ[14] ; Incomplete set of assignments ; +; DRAM_DQ[15] ; Incomplete set of assignments ; +; GPIO_0[0] ; Incomplete set of assignments ; +; GPIO_0[1] ; Incomplete set of assignments ; +; GPIO_1[12] ; Incomplete set of assignments ; +; GPIO_1[24] ; Incomplete set of assignments ; +; GPIO_1[26] ; Incomplete set of assignments ; +; CLOCK_50 ; Incomplete set of assignments ; +; SW[3] ; Incomplete set of assignments ; +; SW[2] ; Incomplete set of assignments ; +; SW[1] ; Incomplete set of assignments ; +; KEY[1] ; Incomplete set of assignments ; +; KEY[0] ; Incomplete set of assignments ; +; SW[0] ; Incomplete set of assignments ; ++---------------+-------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Netlist Optimizations ; ++----------------------------------------------------------------------------------------------------------------+-----------------+------------------+----------------------------------------+-----------+----------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------+-----------------------+ +; Node ; Action ; Operation ; Reason ; Node Port ; Node Port Name ; Destination Node ; Destination Port ; Destination Port Name ; ++----------------------------------------------------------------------------------------------------------------+-----------------+------------------+----------------------------------------+-----------+----------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------+-----------------------+ +; system:inst_cpu|system_cpu:cpu|A_mul_src1[0] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_mult2 ; DATAA ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src1[0] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|A_mul_src1[0]~_Duplicate_1 ; Q ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src1[1] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_mult2 ; DATAA ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src1[1] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|A_mul_src1[1]~_Duplicate_1 ; Q ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src1[2] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_mult2 ; DATAA ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src1[2] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|A_mul_src1[2]~_Duplicate_1 ; Q ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src1[3] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_mult2 ; DATAA ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src1[3] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|A_mul_src1[3]~_Duplicate_1 ; Q ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src1[4] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_mult2 ; DATAA ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src1[4] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|A_mul_src1[4]~_Duplicate_1 ; Q ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src1[5] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_mult2 ; DATAA ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src1[5] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|A_mul_src1[5]~_Duplicate_1 ; Q ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src1[6] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_mult2 ; DATAA ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src1[6] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|A_mul_src1[6]~_Duplicate_1 ; Q ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src1[7] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_mult2 ; DATAA ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src1[7] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|A_mul_src1[7]~_Duplicate_1 ; Q ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src1[8] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_mult2 ; DATAA ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src1[8] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|A_mul_src1[8]~_Duplicate_1 ; Q ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src1[9] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_mult2 ; DATAA ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src1[9] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|A_mul_src1[9]~_Duplicate_1 ; Q ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src1[10] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_mult2 ; DATAA ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src1[10] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|A_mul_src1[10]~_Duplicate_1 ; Q ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src1[11] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_mult2 ; DATAA ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src1[11] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|A_mul_src1[11]~_Duplicate_1 ; Q ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src1[12] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_mult2 ; DATAA ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src1[12] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|A_mul_src1[12]~_Duplicate_1 ; Q ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src1[13] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_mult2 ; DATAA ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src1[13] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|A_mul_src1[13]~_Duplicate_1 ; Q ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src1[14] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_mult2 ; DATAA ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src1[14] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|A_mul_src1[14]~_Duplicate_1 ; Q ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src1[15] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_mult2 ; DATAA ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src1[15] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|A_mul_src1[15]~_Duplicate_1 ; Q ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src1[16] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated|ded_mult_ks81:ded_mult1|mac_mult2 ; DATAA ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src1[17] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated|ded_mult_ks81:ded_mult1|mac_mult2 ; DATAA ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src1[18] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated|ded_mult_ks81:ded_mult1|mac_mult2 ; DATAA ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src1[19] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated|ded_mult_ks81:ded_mult1|mac_mult2 ; DATAA ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src1[20] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated|ded_mult_ks81:ded_mult1|mac_mult2 ; DATAA ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src1[21] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated|ded_mult_ks81:ded_mult1|mac_mult2 ; DATAA ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src1[22] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated|ded_mult_ks81:ded_mult1|mac_mult2 ; DATAA ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src1[23] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated|ded_mult_ks81:ded_mult1|mac_mult2 ; DATAA ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src1[24] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated|ded_mult_ks81:ded_mult1|mac_mult2 ; DATAA ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src1[25] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated|ded_mult_ks81:ded_mult1|mac_mult2 ; DATAA ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src1[26] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated|ded_mult_ks81:ded_mult1|mac_mult2 ; DATAA ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src1[27] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated|ded_mult_ks81:ded_mult1|mac_mult2 ; DATAA ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src1[28] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated|ded_mult_ks81:ded_mult1|mac_mult2 ; DATAA ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src1[29] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated|ded_mult_ks81:ded_mult1|mac_mult2 ; DATAA ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src1[30] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated|ded_mult_ks81:ded_mult1|mac_mult2 ; DATAA ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src1[31] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated|ded_mult_ks81:ded_mult1|mac_mult2 ; DATAA ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src2[0] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_mult2 ; DATAB ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src2[0] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|A_mul_src2[0]~_Duplicate_1 ; Q ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src2[0]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated|ded_mult_ks81:ded_mult1|mac_mult2 ; DATAB ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src2[1] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_mult2 ; DATAB ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src2[1] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|A_mul_src2[1]~_Duplicate_1 ; Q ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src2[1]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated|ded_mult_ks81:ded_mult1|mac_mult2 ; DATAB ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src2[2] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_mult2 ; DATAB ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src2[2] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|A_mul_src2[2]~_Duplicate_1 ; Q ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src2[2]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated|ded_mult_ks81:ded_mult1|mac_mult2 ; DATAB ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src2[3] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_mult2 ; DATAB ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src2[3] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|A_mul_src2[3]~_Duplicate_1 ; Q ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src2[3]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated|ded_mult_ks81:ded_mult1|mac_mult2 ; DATAB ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src2[4] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_mult2 ; DATAB ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src2[4] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|A_mul_src2[4]~_Duplicate_1 ; Q ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src2[4]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated|ded_mult_ks81:ded_mult1|mac_mult2 ; DATAB ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src2[5] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_mult2 ; DATAB ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src2[5] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|A_mul_src2[5]~_Duplicate_1 ; Q ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src2[5]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated|ded_mult_ks81:ded_mult1|mac_mult2 ; DATAB ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src2[6] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_mult2 ; DATAB ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src2[6] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|A_mul_src2[6]~_Duplicate_1 ; Q ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src2[6]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated|ded_mult_ks81:ded_mult1|mac_mult2 ; DATAB ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src2[7] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_mult2 ; DATAB ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src2[7] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|A_mul_src2[7]~_Duplicate_1 ; Q ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src2[7]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated|ded_mult_ks81:ded_mult1|mac_mult2 ; DATAB ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src2[8] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_mult2 ; DATAB ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src2[8] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|A_mul_src2[8]~_Duplicate_1 ; Q ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src2[8]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated|ded_mult_ks81:ded_mult1|mac_mult2 ; DATAB ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src2[9] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_mult2 ; DATAB ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src2[9] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|A_mul_src2[9]~_Duplicate_1 ; Q ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src2[9]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated|ded_mult_ks81:ded_mult1|mac_mult2 ; DATAB ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src2[10] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_mult2 ; DATAB ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src2[10] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|A_mul_src2[10]~_Duplicate_1 ; Q ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src2[10]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated|ded_mult_ks81:ded_mult1|mac_mult2 ; DATAB ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src2[11] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_mult2 ; DATAB ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src2[11] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|A_mul_src2[11]~_Duplicate_1 ; Q ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src2[11]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated|ded_mult_ks81:ded_mult1|mac_mult2 ; DATAB ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src2[12] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_mult2 ; DATAB ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src2[12] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|A_mul_src2[12]~_Duplicate_1 ; Q ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src2[12]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated|ded_mult_ks81:ded_mult1|mac_mult2 ; DATAB ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src2[13] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_mult2 ; DATAB ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src2[13] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|A_mul_src2[13]~_Duplicate_1 ; Q ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src2[13]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated|ded_mult_ks81:ded_mult1|mac_mult2 ; DATAB ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src2[14] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_mult2 ; DATAB ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src2[14] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|A_mul_src2[14]~_Duplicate_1 ; Q ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src2[14]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated|ded_mult_ks81:ded_mult1|mac_mult2 ; DATAB ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src2[15] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_mult2 ; DATAB ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src2[15] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|A_mul_src2[15]~_Duplicate_1 ; Q ; ; +; system:inst_cpu|system_cpu:cpu|A_mul_src2[15]~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated|ded_mult_ks81:ded_mult1|mac_mult2 ; DATAB ; ; +; system:inst_cpu|system_cpu:cpu|D_bht_data[0] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|system_cpu_bht_module:system_cpu_bht|altsyncram:the_altsyncram|altsyncram_fhg1:auto_generated|q_b[0] ; PORTBDATAOUT ; ; +; system:inst_cpu|system_cpu:cpu|D_bht_data[1] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_cpu:cpu|system_cpu_bht_module:system_cpu_bht|altsyncram:the_altsyncram|altsyncram_fhg1:auto_generated|q_b[1] ; PORTBDATAOUT ; ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|rdata[0] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|q_b[0] ; PORTBDATAOUT ; ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|rdata[1] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|q_b[1] ; PORTBDATAOUT ; ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|rdata[2] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|q_b[2] ; PORTBDATAOUT ; ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|rdata[3] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|q_b[3] ; PORTBDATAOUT ; ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|rdata[4] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|q_b[4] ; PORTBDATAOUT ; ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|rdata[5] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|q_b[5] ; PORTBDATAOUT ; ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|rdata[6] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|q_b[6] ; PORTBDATAOUT ; ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|rdata[7] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|q_b[7] ; PORTBDATAOUT ; ; +; system:inst_cpu|system_sdram:sdram|m_addr[0] ; Packed Register ; Register Packing ; Fast Output Register assignment ; Q ; ; DRAM_ADDR[0]~output ; I ; ; +; system:inst_cpu|system_sdram:sdram|m_addr[1] ; Packed Register ; Register Packing ; Fast Output Register assignment ; Q ; ; DRAM_ADDR[1]~output ; I ; ; +; system:inst_cpu|system_sdram:sdram|m_addr[2] ; Packed Register ; Register Packing ; Fast Output Register assignment ; Q ; ; DRAM_ADDR[2]~output ; I ; ; +; system:inst_cpu|system_sdram:sdram|m_addr[3] ; Packed Register ; Register Packing ; Fast Output Register assignment ; Q ; ; DRAM_ADDR[3]~output ; I ; ; +; system:inst_cpu|system_sdram:sdram|m_addr[4] ; Packed Register ; Register Packing ; Fast Output Register assignment ; Q ; ; DRAM_ADDR[4]~output ; I ; ; +; system:inst_cpu|system_sdram:sdram|m_addr[5] ; Packed Register ; Register Packing ; Fast Output Register assignment ; Q ; ; DRAM_ADDR[5]~output ; I ; ; +; system:inst_cpu|system_sdram:sdram|m_addr[6] ; Packed Register ; Register Packing ; Fast Output Register assignment ; Q ; ; DRAM_ADDR[6]~output ; I ; ; +; system:inst_cpu|system_sdram:sdram|m_addr[7] ; Packed Register ; Register Packing ; Fast Output Register assignment ; Q ; ; DRAM_ADDR[7]~output ; I ; ; +; system:inst_cpu|system_sdram:sdram|m_addr[8] ; Packed Register ; Register Packing ; Fast Output Register assignment ; Q ; ; DRAM_ADDR[8]~output ; I ; ; +; system:inst_cpu|system_sdram:sdram|m_addr[9] ; Packed Register ; Register Packing ; Fast Output Register assignment ; Q ; ; DRAM_ADDR[9]~output ; I ; ; +; system:inst_cpu|system_sdram:sdram|m_addr[10] ; Packed Register ; Register Packing ; Fast Output Register assignment ; Q ; ; DRAM_ADDR[10]~output ; I ; ; +; system:inst_cpu|system_sdram:sdram|m_addr[11] ; Packed Register ; Register Packing ; Fast Output Register assignment ; Q ; ; DRAM_ADDR[11]~output ; I ; ; +; system:inst_cpu|system_sdram:sdram|m_addr[12] ; Packed Register ; Register Packing ; Fast Output Register assignment ; Q ; ; DRAM_ADDR[12]~output ; I ; ; +; system:inst_cpu|system_sdram:sdram|m_bank[0] ; Packed Register ; Register Packing ; Fast Output Register assignment ; Q ; ; DRAM_BA[0]~output ; I ; ; +; system:inst_cpu|system_sdram:sdram|m_bank[1] ; Packed Register ; Register Packing ; Fast Output Register assignment ; Q ; ; DRAM_BA[1]~output ; I ; ; +; system:inst_cpu|system_sdram:sdram|m_cmd[0] ; Duplicated ; Register Packing ; Fast Output Register assignment ; Q ; ; system:inst_cpu|system_sdram:sdram|m_cmd[0]~_Duplicate_1 ; Q ; ; +; system:inst_cpu|system_sdram:sdram|m_cmd[0] ; Packed Register ; Register Packing ; Fast Output Register assignment ; Q ; ; DRAM_WE_N~output ; I ; ; +; system:inst_cpu|system_sdram:sdram|m_cmd[0] ; Inverted ; Register Packing ; Fast Output Register assignment ; Q ; ; ; ; ; +; system:inst_cpu|system_sdram:sdram|m_cmd[1] ; Duplicated ; Register Packing ; Fast Output Register assignment ; Q ; ; system:inst_cpu|system_sdram:sdram|m_cmd[1]~_Duplicate_1 ; Q ; ; +; system:inst_cpu|system_sdram:sdram|m_cmd[1] ; Packed Register ; Register Packing ; Fast Output Register assignment ; Q ; ; DRAM_CAS_N~output ; I ; ; +; system:inst_cpu|system_sdram:sdram|m_cmd[1] ; Inverted ; Register Packing ; Fast Output Register assignment ; Q ; ; ; ; ; +; system:inst_cpu|system_sdram:sdram|m_cmd[2] ; Duplicated ; Register Packing ; Fast Output Register assignment ; Q ; ; system:inst_cpu|system_sdram:sdram|m_cmd[2]~_Duplicate_1 ; Q ; ; +; system:inst_cpu|system_sdram:sdram|m_cmd[2] ; Packed Register ; Register Packing ; Fast Output Register assignment ; Q ; ; DRAM_RAS_N~output ; I ; ; +; system:inst_cpu|system_sdram:sdram|m_cmd[2] ; Inverted ; Register Packing ; Fast Output Register assignment ; Q ; ; ; ; ; +; system:inst_cpu|system_sdram:sdram|m_cmd[3] ; Packed Register ; Register Packing ; Fast Output Register assignment ; Q ; ; DRAM_CS_N~output ; I ; ; +; system:inst_cpu|system_sdram:sdram|m_cmd[3] ; Inverted ; Register Packing ; Fast Output Register assignment ; Q ; ; ; ; ; +; system:inst_cpu|system_sdram:sdram|m_data[0] ; Duplicated ; Register Packing ; Fast Output Register assignment ; Q ; ; system:inst_cpu|system_sdram:sdram|m_data[0]~_Duplicate_1 ; Q ; ; +; system:inst_cpu|system_sdram:sdram|m_data[0] ; Packed Register ; Register Packing ; Fast Output Register assignment ; Q ; ; DRAM_DQ[0]~output ; I ; ; +; system:inst_cpu|system_sdram:sdram|m_data[1] ; Duplicated ; Register Packing ; Fast Output Register assignment ; Q ; ; system:inst_cpu|system_sdram:sdram|m_data[1]~_Duplicate_1 ; Q ; ; +; system:inst_cpu|system_sdram:sdram|m_data[1] ; Packed Register ; Register Packing ; Fast Output Register assignment ; Q ; ; DRAM_DQ[1]~output ; I ; ; +; system:inst_cpu|system_sdram:sdram|m_data[2] ; Duplicated ; Register Packing ; Fast Output Register assignment ; Q ; ; system:inst_cpu|system_sdram:sdram|m_data[2]~_Duplicate_1 ; Q ; ; +; system:inst_cpu|system_sdram:sdram|m_data[2] ; Packed Register ; Register Packing ; Fast Output Register assignment ; Q ; ; DRAM_DQ[2]~output ; I ; ; +; system:inst_cpu|system_sdram:sdram|m_data[3] ; Duplicated ; Register Packing ; Fast Output Register assignment ; Q ; ; system:inst_cpu|system_sdram:sdram|m_data[3]~_Duplicate_1 ; Q ; ; +; system:inst_cpu|system_sdram:sdram|m_data[3] ; Packed Register ; Register Packing ; Fast Output Register assignment ; Q ; ; DRAM_DQ[3]~output ; I ; ; +; system:inst_cpu|system_sdram:sdram|m_data[4] ; Duplicated ; Register Packing ; Fast Output Register assignment ; Q ; ; system:inst_cpu|system_sdram:sdram|m_data[4]~_Duplicate_1 ; Q ; ; +; system:inst_cpu|system_sdram:sdram|m_data[4] ; Packed Register ; Register Packing ; Fast Output Register assignment ; Q ; ; DRAM_DQ[4]~output ; I ; ; +; system:inst_cpu|system_sdram:sdram|m_data[5] ; Duplicated ; Register Packing ; Fast Output Register assignment ; Q ; ; system:inst_cpu|system_sdram:sdram|m_data[5]~_Duplicate_1 ; Q ; ; +; system:inst_cpu|system_sdram:sdram|m_data[5] ; Packed Register ; Register Packing ; Fast Output Register assignment ; Q ; ; DRAM_DQ[5]~output ; I ; ; +; system:inst_cpu|system_sdram:sdram|m_data[6] ; Duplicated ; Register Packing ; Fast Output Register assignment ; Q ; ; system:inst_cpu|system_sdram:sdram|m_data[6]~_Duplicate_1 ; Q ; ; +; system:inst_cpu|system_sdram:sdram|m_data[6] ; Packed Register ; Register Packing ; Fast Output Register assignment ; Q ; ; DRAM_DQ[6]~output ; I ; ; +; system:inst_cpu|system_sdram:sdram|m_data[7] ; Duplicated ; Register Packing ; Fast Output Register assignment ; Q ; ; system:inst_cpu|system_sdram:sdram|m_data[7]~_Duplicate_1 ; Q ; ; +; system:inst_cpu|system_sdram:sdram|m_data[7] ; Packed Register ; Register Packing ; Fast Output Register assignment ; Q ; ; DRAM_DQ[7]~output ; I ; ; +; system:inst_cpu|system_sdram:sdram|m_data[8] ; Duplicated ; Register Packing ; Fast Output Register assignment ; Q ; ; system:inst_cpu|system_sdram:sdram|m_data[8]~_Duplicate_1 ; Q ; ; +; system:inst_cpu|system_sdram:sdram|m_data[8] ; Packed Register ; Register Packing ; Fast Output Register assignment ; Q ; ; DRAM_DQ[8]~output ; I ; ; +; system:inst_cpu|system_sdram:sdram|m_data[9] ; Duplicated ; Register Packing ; Fast Output Register assignment ; Q ; ; system:inst_cpu|system_sdram:sdram|m_data[9]~_Duplicate_1 ; Q ; ; +; system:inst_cpu|system_sdram:sdram|m_data[9] ; Packed Register ; Register Packing ; Fast Output Register assignment ; Q ; ; DRAM_DQ[9]~output ; I ; ; +; system:inst_cpu|system_sdram:sdram|m_data[10] ; Duplicated ; Register Packing ; Fast Output Register assignment ; Q ; ; system:inst_cpu|system_sdram:sdram|m_data[10]~_Duplicate_1 ; Q ; ; +; system:inst_cpu|system_sdram:sdram|m_data[10] ; Packed Register ; Register Packing ; Fast Output Register assignment ; Q ; ; DRAM_DQ[10]~output ; I ; ; +; system:inst_cpu|system_sdram:sdram|m_data[11] ; Duplicated ; Register Packing ; Fast Output Register assignment ; Q ; ; system:inst_cpu|system_sdram:sdram|m_data[11]~_Duplicate_1 ; Q ; ; +; system:inst_cpu|system_sdram:sdram|m_data[11] ; Packed Register ; Register Packing ; Fast Output Register assignment ; Q ; ; DRAM_DQ[11]~output ; I ; ; +; system:inst_cpu|system_sdram:sdram|m_data[12] ; Duplicated ; Register Packing ; Fast Output Register assignment ; Q ; ; system:inst_cpu|system_sdram:sdram|m_data[12]~_Duplicate_1 ; Q ; ; +; system:inst_cpu|system_sdram:sdram|m_data[12] ; Packed Register ; Register Packing ; Fast Output Register assignment ; Q ; ; DRAM_DQ[12]~output ; I ; ; +; system:inst_cpu|system_sdram:sdram|m_data[13] ; Duplicated ; Register Packing ; Fast Output Register assignment ; Q ; ; system:inst_cpu|system_sdram:sdram|m_data[13]~_Duplicate_1 ; Q ; ; +; system:inst_cpu|system_sdram:sdram|m_data[13] ; Packed Register ; Register Packing ; Fast Output Register assignment ; Q ; ; DRAM_DQ[13]~output ; I ; ; +; system:inst_cpu|system_sdram:sdram|m_data[14] ; Duplicated ; Register Packing ; Fast Output Register assignment ; Q ; ; system:inst_cpu|system_sdram:sdram|m_data[14]~_Duplicate_1 ; Q ; ; +; system:inst_cpu|system_sdram:sdram|m_data[14] ; Packed Register ; Register Packing ; Fast Output Register assignment ; Q ; ; DRAM_DQ[14]~output ; I ; ; +; system:inst_cpu|system_sdram:sdram|m_data[15] ; Duplicated ; Register Packing ; Fast Output Register assignment ; Q ; ; system:inst_cpu|system_sdram:sdram|m_data[15]~_Duplicate_1 ; Q ; ; +; system:inst_cpu|system_sdram:sdram|m_data[15] ; Packed Register ; Register Packing ; Fast Output Register assignment ; Q ; ; DRAM_DQ[15]~output ; I ; ; +; system:inst_cpu|system_sdram:sdram|m_dqm[0] ; Packed Register ; Register Packing ; Fast Output Register assignment ; Q ; ; DRAM_DQM[0]~output ; I ; ; +; system:inst_cpu|system_sdram:sdram|m_dqm[1] ; Packed Register ; Register Packing ; Fast Output Register assignment ; Q ; ; DRAM_DQM[1]~output ; I ; ; +; system:inst_cpu|system_sdram:sdram|oe ; Duplicated ; Register Packing ; Fast Output Enable Register assignment ; Q ; ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_1 ; Q ; ; +; system:inst_cpu|system_sdram:sdram|oe ; Packed Register ; Register Packing ; Fast Output Enable Register assignment ; Q ; ; DRAM_DQ[0]~output ; OE ; ; +; system:inst_cpu|system_sdram:sdram|oe ; Inverted ; Register Packing ; Fast Output Enable Register assignment ; Q ; ; ; ; ; +; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_1 ; Duplicated ; Register Packing ; Fast Output Enable Register assignment ; Q ; ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_2 ; Q ; ; +; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_1 ; Packed Register ; Register Packing ; Fast Output Enable Register assignment ; Q ; ; DRAM_DQ[1]~output ; OE ; ; +; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_1 ; Inverted ; Register Packing ; Fast Output Enable Register assignment ; Q ; ; ; ; ; +; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_2 ; Duplicated ; Register Packing ; Fast Output Enable Register assignment ; Q ; ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_3 ; Q ; ; +; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_2 ; Packed Register ; Register Packing ; Fast Output Enable Register assignment ; Q ; ; DRAM_DQ[2]~output ; OE ; ; +; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_2 ; Inverted ; Register Packing ; Fast Output Enable Register assignment ; Q ; ; ; ; ; +; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_3 ; Duplicated ; Register Packing ; Fast Output Enable Register assignment ; Q ; ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_4 ; Q ; ; +; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_3 ; Packed Register ; Register Packing ; Fast Output Enable Register assignment ; Q ; ; DRAM_DQ[3]~output ; OE ; ; +; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_3 ; Inverted ; Register Packing ; Fast Output Enable Register assignment ; Q ; ; ; ; ; +; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_4 ; Duplicated ; Register Packing ; Fast Output Enable Register assignment ; Q ; ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_5 ; Q ; ; +; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_4 ; Packed Register ; Register Packing ; Fast Output Enable Register assignment ; Q ; ; DRAM_DQ[4]~output ; OE ; ; +; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_4 ; Inverted ; Register Packing ; Fast Output Enable Register assignment ; Q ; ; ; ; ; +; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_5 ; Duplicated ; Register Packing ; Fast Output Enable Register assignment ; Q ; ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_6 ; Q ; ; +; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_5 ; Packed Register ; Register Packing ; Fast Output Enable Register assignment ; Q ; ; DRAM_DQ[5]~output ; OE ; ; +; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_5 ; Inverted ; Register Packing ; Fast Output Enable Register assignment ; Q ; ; ; ; ; +; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_6 ; Duplicated ; Register Packing ; Fast Output Enable Register assignment ; Q ; ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_7 ; Q ; ; +; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_6 ; Packed Register ; Register Packing ; Fast Output Enable Register assignment ; Q ; ; DRAM_DQ[6]~output ; OE ; ; +; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_6 ; Inverted ; Register Packing ; Fast Output Enable Register assignment ; Q ; ; ; ; ; +; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_7 ; Duplicated ; Register Packing ; Fast Output Enable Register assignment ; Q ; ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_8 ; Q ; ; +; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_7 ; Packed Register ; Register Packing ; Fast Output Enable Register assignment ; Q ; ; DRAM_DQ[7]~output ; OE ; ; +; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_7 ; Inverted ; Register Packing ; Fast Output Enable Register assignment ; Q ; ; ; ; ; +; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_8 ; Duplicated ; Register Packing ; Fast Output Enable Register assignment ; Q ; ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_9 ; Q ; ; +; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_8 ; Packed Register ; Register Packing ; Fast Output Enable Register assignment ; Q ; ; DRAM_DQ[8]~output ; OE ; ; +; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_8 ; Inverted ; Register Packing ; Fast Output Enable Register assignment ; Q ; ; ; ; ; +; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_9 ; Duplicated ; Register Packing ; Fast Output Enable Register assignment ; Q ; ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_10 ; Q ; ; +; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_9 ; Packed Register ; Register Packing ; Fast Output Enable Register assignment ; Q ; ; DRAM_DQ[9]~output ; OE ; ; +; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_9 ; Inverted ; Register Packing ; Fast Output Enable Register assignment ; Q ; ; ; ; ; +; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_10 ; Duplicated ; Register Packing ; Fast Output Enable Register assignment ; Q ; ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_11 ; Q ; ; +; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_10 ; Packed Register ; Register Packing ; Fast Output Enable Register assignment ; Q ; ; DRAM_DQ[10]~output ; OE ; ; +; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_10 ; Inverted ; Register Packing ; Fast Output Enable Register assignment ; Q ; ; ; ; ; +; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_11 ; Duplicated ; Register Packing ; Fast Output Enable Register assignment ; Q ; ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_12 ; Q ; ; +; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_11 ; Packed Register ; Register Packing ; Fast Output Enable Register assignment ; Q ; ; DRAM_DQ[11]~output ; OE ; ; +; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_11 ; Inverted ; Register Packing ; Fast Output Enable Register assignment ; Q ; ; ; ; ; +; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_12 ; Duplicated ; Register Packing ; Fast Output Enable Register assignment ; Q ; ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_13 ; Q ; ; +; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_12 ; Packed Register ; Register Packing ; Fast Output Enable Register assignment ; Q ; ; DRAM_DQ[12]~output ; OE ; ; +; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_12 ; Inverted ; Register Packing ; Fast Output Enable Register assignment ; Q ; ; ; ; ; +; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_13 ; Duplicated ; Register Packing ; Fast Output Enable Register assignment ; Q ; ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_14 ; Q ; ; +; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_13 ; Packed Register ; Register Packing ; Fast Output Enable Register assignment ; Q ; ; DRAM_DQ[13]~output ; OE ; ; +; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_13 ; Inverted ; Register Packing ; Fast Output Enable Register assignment ; Q ; ; ; ; ; +; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_14 ; Duplicated ; Register Packing ; Fast Output Enable Register assignment ; Q ; ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_15 ; Q ; ; +; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_14 ; Packed Register ; Register Packing ; Fast Output Enable Register assignment ; Q ; ; DRAM_DQ[14]~output ; OE ; ; +; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_14 ; Inverted ; Register Packing ; Fast Output Enable Register assignment ; Q ; ; ; ; ; +; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_15 ; Packed Register ; Register Packing ; Fast Output Enable Register assignment ; Q ; ; DRAM_DQ[15]~output ; OE ; ; +; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_15 ; Inverted ; Register Packing ; Fast Output Enable Register assignment ; Q ; ; ; ; ; +; system:inst_cpu|system_sdram:sdram|za_data[0] ; Packed Register ; Register Packing ; Fast Input Register assignment ; Q ; ; DRAM_DQ[0]~input ; O ; ; +; system:inst_cpu|system_sdram:sdram|za_data[1] ; Packed Register ; Register Packing ; Fast Input Register assignment ; Q ; ; DRAM_DQ[1]~input ; O ; ; +; system:inst_cpu|system_sdram:sdram|za_data[2] ; Packed Register ; Register Packing ; Fast Input Register assignment ; Q ; ; DRAM_DQ[2]~input ; O ; ; +; system:inst_cpu|system_sdram:sdram|za_data[3] ; Packed Register ; Register Packing ; Fast Input Register assignment ; Q ; ; DRAM_DQ[3]~input ; O ; ; +; system:inst_cpu|system_sdram:sdram|za_data[4] ; Packed Register ; Register Packing ; Fast Input Register assignment ; Q ; ; DRAM_DQ[4]~input ; O ; ; +; system:inst_cpu|system_sdram:sdram|za_data[5] ; Packed Register ; Register Packing ; Fast Input Register assignment ; Q ; ; DRAM_DQ[5]~input ; O ; ; +; system:inst_cpu|system_sdram:sdram|za_data[6] ; Packed Register ; Register Packing ; Fast Input Register assignment ; Q ; ; DRAM_DQ[6]~input ; O ; ; +; system:inst_cpu|system_sdram:sdram|za_data[7] ; Packed Register ; Register Packing ; Fast Input Register assignment ; Q ; ; DRAM_DQ[7]~input ; O ; ; +; system:inst_cpu|system_sdram:sdram|za_data[8] ; Packed Register ; Register Packing ; Fast Input Register assignment ; Q ; ; DRAM_DQ[8]~input ; O ; ; +; system:inst_cpu|system_sdram:sdram|za_data[9] ; Packed Register ; Register Packing ; Fast Input Register assignment ; Q ; ; DRAM_DQ[9]~input ; O ; ; +; system:inst_cpu|system_sdram:sdram|za_data[10] ; Packed Register ; Register Packing ; Fast Input Register assignment ; Q ; ; DRAM_DQ[10]~input ; O ; ; +; system:inst_cpu|system_sdram:sdram|za_data[11] ; Packed Register ; Register Packing ; Fast Input Register assignment ; Q ; ; DRAM_DQ[11]~input ; O ; ; +; system:inst_cpu|system_sdram:sdram|za_data[12] ; Packed Register ; Register Packing ; Fast Input Register assignment ; Q ; ; DRAM_DQ[12]~input ; O ; ; +; system:inst_cpu|system_sdram:sdram|za_data[13] ; Packed Register ; Register Packing ; Fast Input Register assignment ; Q ; ; DRAM_DQ[13]~input ; O ; ; +; system:inst_cpu|system_sdram:sdram|za_data[14] ; Packed Register ; Register Packing ; Fast Input Register assignment ; Q ; ; DRAM_DQ[14]~input ; O ; ; +; system:inst_cpu|system_sdram:sdram|za_data[15] ; Packed Register ; Register Packing ; Fast Input Register assignment ; Q ; ; DRAM_DQ[15]~input ; O ; ; ++----------------------------------------------------------------------------------------------------------------+-----------------+------------------+----------------------------------------+-----------+----------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------+-----------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------+ +; Ignored Assignments ; ++-----------------------------+----------------+--------------+------------------+---------------+----------------------------+ +; Name ; Ignored Entity ; Ignored From ; Ignored To ; Ignored Value ; Ignored Source ; ++-----------------------------+----------------+--------------+------------------+---------------+----------------------------+ +; Location ; ; ; ADC_CS_N ; PIN_A10 ; QSF Assignment ; +; Location ; ; ; ADC_SADDR ; PIN_B10 ; QSF Assignment ; +; Location ; ; ; ADC_SCLK ; PIN_B14 ; QSF Assignment ; +; Location ; ; ; ADC_SDAT ; PIN_A9 ; QSF Assignment ; +; Location ; ; ; GPIO_0_IN[0] ; PIN_A8 ; QSF Assignment ; +; Location ; ; ; GPIO_0_IN[1] ; PIN_B8 ; QSF Assignment ; +; Location ; ; ; GPIO_1_IN[0] ; PIN_T9 ; QSF Assignment ; +; Location ; ; ; GPIO_1_IN[1] ; PIN_R9 ; QSF Assignment ; +; Location ; ; ; GPIO_2[0] ; PIN_A14 ; QSF Assignment ; +; Location ; ; ; GPIO_2[10] ; PIN_F14 ; QSF Assignment ; +; Location ; ; ; GPIO_2[11] ; PIN_G16 ; QSF Assignment ; +; Location ; ; ; GPIO_2[12] ; PIN_G15 ; QSF Assignment ; +; Location ; ; ; GPIO_2[1] ; PIN_B16 ; QSF Assignment ; +; Location ; ; ; GPIO_2[2] ; PIN_C14 ; QSF Assignment ; +; Location ; ; ; GPIO_2[3] ; PIN_C16 ; QSF Assignment ; +; Location ; ; ; GPIO_2[4] ; PIN_C15 ; QSF Assignment ; +; Location ; ; ; GPIO_2[5] ; PIN_D16 ; QSF Assignment ; +; Location ; ; ; GPIO_2[6] ; PIN_D15 ; QSF Assignment ; +; Location ; ; ; GPIO_2[7] ; PIN_D14 ; QSF Assignment ; +; Location ; ; ; GPIO_2[8] ; PIN_F15 ; QSF Assignment ; +; Location ; ; ; GPIO_2[9] ; PIN_F16 ; QSF Assignment ; +; Location ; ; ; GPIO_2_IN[0] ; PIN_E15 ; QSF Assignment ; +; Location ; ; ; GPIO_2_IN[1] ; PIN_E16 ; QSF Assignment ; +; Location ; ; ; GPIO_2_IN[2] ; PIN_M16 ; QSF Assignment ; +; Location ; ; ; G_SENSOR_CS_N ; PIN_G5 ; QSF Assignment ; +; Location ; ; ; G_SENSOR_INT ; PIN_M2 ; QSF Assignment ; +; Location ; ; ; I2C_SCLK ; PIN_F2 ; QSF Assignment ; +; Location ; ; ; I2C_SDAT ; PIN_F1 ; QSF Assignment ; +; Fast Input Register ; system_sdram ; ; za_data[0]~reg0 ; ON ; Compiler or HDL Assignment ; +; Fast Input Register ; system_sdram ; ; za_data[10]~reg0 ; ON ; Compiler or HDL Assignment ; +; Fast Input Register ; system_sdram ; ; za_data[11]~reg0 ; ON ; Compiler or HDL Assignment ; +; Fast Input Register ; system_sdram ; ; za_data[12]~reg0 ; ON ; Compiler or HDL Assignment ; +; Fast Input Register ; system_sdram ; ; za_data[13]~reg0 ; ON ; Compiler or HDL Assignment ; +; Fast Input Register ; system_sdram ; ; za_data[14]~reg0 ; ON ; Compiler or HDL Assignment ; +; Fast Input Register ; system_sdram ; ; za_data[15]~reg0 ; ON ; Compiler or HDL Assignment ; +; Fast Input Register ; system_sdram ; ; za_data[1]~reg0 ; ON ; Compiler or HDL Assignment ; +; Fast Input Register ; system_sdram ; ; za_data[2]~reg0 ; ON ; Compiler or HDL Assignment ; +; Fast Input Register ; system_sdram ; ; za_data[3]~reg0 ; ON ; Compiler or HDL Assignment ; +; Fast Input Register ; system_sdram ; ; za_data[4]~reg0 ; ON ; Compiler or HDL Assignment ; +; Fast Input Register ; system_sdram ; ; za_data[5]~reg0 ; ON ; Compiler or HDL Assignment ; +; Fast Input Register ; system_sdram ; ; za_data[6]~reg0 ; ON ; Compiler or HDL Assignment ; +; Fast Input Register ; system_sdram ; ; za_data[7]~reg0 ; ON ; Compiler or HDL Assignment ; +; Fast Input Register ; system_sdram ; ; za_data[8]~reg0 ; ON ; Compiler or HDL Assignment ; +; Fast Input Register ; system_sdram ; ; za_data[9]~reg0 ; ON ; Compiler or HDL Assignment ; +; Fast Output Enable Register ; system_sdram ; ; m_data[0] ; ON ; Compiler or HDL Assignment ; +; Fast Output Enable Register ; system_sdram ; ; m_data[10] ; ON ; Compiler or HDL Assignment ; +; Fast Output Enable Register ; system_sdram ; ; m_data[11] ; ON ; Compiler or HDL Assignment ; +; Fast Output Enable Register ; system_sdram ; ; m_data[12] ; ON ; Compiler or HDL Assignment ; +; Fast Output Enable Register ; system_sdram ; ; m_data[13] ; ON ; Compiler or HDL Assignment ; +; Fast Output Enable Register ; system_sdram ; ; m_data[14] ; ON ; Compiler or HDL Assignment ; +; Fast Output Enable Register ; system_sdram ; ; m_data[15] ; ON ; Compiler or HDL Assignment ; +; Fast Output Enable Register ; system_sdram ; ; m_data[1] ; ON ; Compiler or HDL Assignment ; +; Fast Output Enable Register ; system_sdram ; ; m_data[2] ; ON ; Compiler or HDL Assignment ; +; Fast Output Enable Register ; system_sdram ; ; m_data[3] ; ON ; Compiler or HDL Assignment ; +; Fast Output Enable Register ; system_sdram ; ; m_data[4] ; ON ; Compiler or HDL Assignment ; +; Fast Output Enable Register ; system_sdram ; ; m_data[5] ; ON ; Compiler or HDL Assignment ; +; Fast Output Enable Register ; system_sdram ; ; m_data[6] ; ON ; Compiler or HDL Assignment ; +; Fast Output Enable Register ; system_sdram ; ; m_data[7] ; ON ; Compiler or HDL Assignment ; +; Fast Output Enable Register ; system_sdram ; ; m_data[8] ; ON ; Compiler or HDL Assignment ; +; Fast Output Enable Register ; system_sdram ; ; m_data[9] ; ON ; Compiler or HDL Assignment ; ++-----------------------------+----------------+--------------+------------------+---------------+----------------------------+ + + ++----------------------------------------------+ +; Incremental Compilation Preservation Summary ; ++---------------------+------------------------+ +; Type ; Value ; ++---------------------+------------------------+ +; Placement (by node) ; ; +; -- Requested ; 0 / 7423 ( 0.00 % ) ; +; -- Achieved ; 0 / 7423 ( 0.00 % ) ; +; ; ; +; Routing (by net) ; ; +; -- Requested ; 0 / 0 ( 0.00 % ) ; +; -- Achieved ; 0 / 0 ( 0.00 % ) ; ++---------------------+------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Partition Settings ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ; +; sld_hub:auto_hub ; Auto-generated ; Post-Synthesis ; N/A ; Post-Synthesis ; N/A ; sld_hub:auto_hub ; +; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ + + ++------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Placement Preservation ; ++--------------------------------+---------+-------------------+-------------------------+-------------------+ +; Partition Name ; # Nodes ; # Preserved Nodes ; Preservation Level Used ; Netlist Type Used ; ++--------------------------------+---------+-------------------+-------------------------+-------------------+ +; Top ; 7154 ; 0 ; N/A ; Source File ; +; sld_hub:auto_hub ; 255 ; 0 ; N/A ; Post-Synthesis ; +; hard_block:auto_generated_inst ; 14 ; 0 ; N/A ; Source File ; ++--------------------------------+---------+-------------------+-------------------------+-------------------+ + + ++--------------+ +; Pin-Out File ; ++--------------+ +The pin-out file can be found in C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/output_files/de0_nano_system.pin. + + ++--------------------------------------------------------------------------+ +; Fitter Resource Usage Summary ; ++---------------------------------------------+----------------------------+ +; Resource ; Usage ; ++---------------------------------------------+----------------------------+ +; Total logic elements ; 4,562 / 22,320 ( 20 % ) ; +; -- Combinational with no register ; 1772 ; +; -- Register only ; 625 ; +; -- Combinational with a register ; 2165 ; +; ; ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 1858 ; +; -- 3 input functions ; 1342 ; +; -- <=2 input functions ; 737 ; +; -- Register only ; 625 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 3580 ; +; -- arithmetic mode ; 357 ; +; ; ; +; Total registers* ; 2,859 / 23,018 ( 12 % ) ; +; -- Dedicated logic registers ; 2,790 / 22,320 ( 13 % ) ; +; -- I/O registers ; 69 / 698 ( 10 % ) ; +; ; ; +; Total LABs: partially or completely used ; 336 / 1,395 ( 24 % ) ; +; Virtual pins ; 0 ; +; I/O pins ; 122 / 154 ( 79 % ) ; +; -- Clock pins ; 5 / 7 ( 71 % ) ; +; -- Dedicated input pins ; 3 / 9 ( 33 % ) ; +; ; ; +; Global signals ; 8 ; +; M9Ks ; 24 / 66 ( 36 % ) ; +; Total block memory bits ; 119,808 / 608,256 ( 20 % ) ; +; Total block memory implementation bits ; 221,184 / 608,256 ( 36 % ) ; +; Embedded Multiplier 9-bit elements ; 4 / 132 ( 3 % ) ; +; PLLs ; 1 / 4 ( 25 % ) ; +; Global clocks ; 8 / 20 ( 40 % ) ; +; JTAGs ; 1 / 1 ( 100 % ) ; +; CRC blocks ; 0 / 1 ( 0 % ) ; +; ASMI blocks ; 0 / 1 ( 0 % ) ; +; Impedance control blocks ; 0 / 4 ( 0 % ) ; +; Average interconnect usage (total/H/V) ; 7% / 7% / 7% ; +; Peak interconnect usage (total/H/V) ; 34% / 33% / 34% ; +; Maximum fan-out ; 2698 ; +; Highest non-global fan-out ; 741 ; +; Total fan-out ; 25273 ; +; Average fan-out ; 3.29 ; ++---------------------------------------------+----------------------------+ +* Register count does not include registers inside RAM blocks or DSP blocks. + + + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Partition Statistics ; ++----------------------------------------------+-----------------------+-----------------------+--------------------------------+ +; Statistic ; Top ; sld_hub:auto_hub ; hard_block:auto_generated_inst ; ++----------------------------------------------+-----------------------+-----------------------+--------------------------------+ +; Difficulty Clustering Region ; Low ; Low ; Low ; +; ; ; ; ; +; Total logic elements ; 4387 / 22320 ( 20 % ) ; 175 / 22320 ( < 1 % ) ; 0 / 22320 ( 0 % ) ; +; -- Combinational with no register ; 1694 ; 78 ; 0 ; +; -- Register only ; 606 ; 19 ; 0 ; +; -- Combinational with a register ; 2087 ; 78 ; 0 ; +; ; ; ; ; +; Logic element usage by number of LUT inputs ; ; ; ; +; -- 4 input functions ; 1789 ; 69 ; 0 ; +; -- 3 input functions ; 1298 ; 44 ; 0 ; +; -- <=2 input functions ; 694 ; 43 ; 0 ; +; -- Register only ; 606 ; 19 ; 0 ; +; ; ; ; ; +; Logic elements by mode ; ; ; ; +; -- normal mode ; 3432 ; 148 ; 0 ; +; -- arithmetic mode ; 349 ; 8 ; 0 ; +; ; ; ; ; +; Total registers ; 2762 ; 97 ; 0 ; +; -- Dedicated logic registers ; 2693 / 22320 ( 12 % ) ; 97 / 22320 ( < 1 % ) ; 0 / 22320 ( 0 % ) ; +; -- I/O registers ; 138 ; 0 ; 0 ; +; ; ; ; ; +; Total LABs: partially or completely used ; 320 / 1395 ( 23 % ) ; 17 / 1395 ( 1 % ) ; 0 / 1395 ( 0 % ) ; +; ; ; ; ; +; Virtual pins ; 0 ; 0 ; 0 ; +; I/O pins ; 122 ; 0 ; 0 ; +; Embedded Multiplier 9-bit elements ; 4 / 132 ( 3 % ) ; 0 / 132 ( 0 % ) ; 0 / 132 ( 0 % ) ; +; Total memory bits ; 119808 ; 0 ; 0 ; +; Total RAM block bits ; 221184 ; 0 ; 0 ; +; JTAG ; 1 / 1 ( 100 % ) ; 0 / 1 ( 0 % ) ; 0 / 1 ( 0 % ) ; +; PLL ; 0 / 4 ( 0 % ) ; 0 / 4 ( 0 % ) ; 1 / 4 ( 25 % ) ; +; M9K ; 24 / 66 ( 36 % ) ; 0 / 66 ( 0 % ) ; 0 / 66 ( 0 % ) ; +; Clock control block ; 3 / 24 ( 12 % ) ; 2 / 24 ( 8 % ) ; 3 / 24 ( 12 % ) ; +; Double Data Rate I/O output circuitry ; 37 / 220 ( 16 % ) ; 0 / 220 ( 0 % ) ; 0 / 220 ( 0 % ) ; +; Double Data Rate I/O output enable circuitry ; 16 / 220 ( 7 % ) ; 0 / 220 ( 0 % ) ; 0 / 220 ( 0 % ) ; +; ; ; ; ; +; Connections ; ; ; ; +; -- Input Connections ; 3070 ; 141 ; 1 ; +; -- Registered Input Connections ; 2812 ; 107 ; 0 ; +; -- Output Connections ; 321 ; 169 ; 2722 ; +; -- Registered Output Connections ; 4 ; 129 ; 0 ; +; ; ; ; ; +; Internal Connections ; ; ; ; +; -- Total Connections ; 24711 ; 1010 ; 2732 ; +; -- Registered Connections ; 11778 ; 618 ; 0 ; +; ; ; ; ; +; External Connections ; ; ; ; +; -- Top ; 360 ; 308 ; 2723 ; +; -- sld_hub:auto_hub ; 308 ; 2 ; 0 ; +; -- hard_block:auto_generated_inst ; 2723 ; 0 ; 0 ; +; ; ; ; ; +; Partition Interface ; ; ; ; +; -- Input Ports ; 47 ; 23 ; 1 ; +; -- Output Ports ; 38 ; 40 ; 4 ; +; -- Bidir Ports ; 84 ; 0 ; 0 ; +; ; ; ; ; +; Registered Ports ; ; ; ; +; -- Registered Input Ports ; 0 ; 3 ; 0 ; +; -- Registered Output Ports ; 0 ; 29 ; 0 ; +; ; ; ; ; +; Port Connectivity ; ; ; ; +; -- Input Ports driven by GND ; 0 ; 9 ; 0 ; +; -- Output Ports driven by GND ; 0 ; 1 ; 0 ; +; -- Input Ports driven by VCC ; 0 ; 0 ; 0 ; +; -- Output Ports driven by VCC ; 0 ; 0 ; 0 ; +; -- Input Ports with no Source ; 0 ; 1 ; 0 ; +; -- Output Ports with no Source ; 0 ; 0 ; 0 ; +; -- Input Ports with no Fanout ; 0 ; 2 ; 0 ; +; -- Output Ports with no Fanout ; 0 ; 26 ; 0 ; ++----------------------------------------------+-----------------------+-----------------------+--------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Input Pins ; ++----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ; ++----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+ +; CLOCK_50 ; R8 ; 3 ; 27 ; 0 ; 21 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; +; KEY[0] ; J15 ; 5 ; 53 ; 14 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; +; KEY[1] ; E1 ; 1 ; 0 ; 16 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; +; SW[0] ; M1 ; 2 ; 0 ; 16 ; 21 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; +; SW[1] ; T8 ; 3 ; 27 ; 0 ; 14 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; +; SW[2] ; B9 ; 7 ; 25 ; 34 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; +; SW[3] ; M15 ; 5 ; 53 ; 17 ; 14 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; ++----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Output Pins ; ++---------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ; ++---------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ +; DRAM_ADDR[0] ; P2 ; 2 ; 0 ; 4 ; 14 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; DRAM_ADDR[10] ; N2 ; 2 ; 0 ; 8 ; 21 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; DRAM_ADDR[11] ; N1 ; 2 ; 0 ; 7 ; 0 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; DRAM_ADDR[12] ; L4 ; 2 ; 0 ; 6 ; 14 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; DRAM_ADDR[1] ; N5 ; 3 ; 5 ; 0 ; 7 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; DRAM_ADDR[2] ; N6 ; 3 ; 5 ; 0 ; 0 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; DRAM_ADDR[3] ; M8 ; 3 ; 20 ; 0 ; 7 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; DRAM_ADDR[4] ; P8 ; 3 ; 25 ; 0 ; 14 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; DRAM_ADDR[5] ; T7 ; 3 ; 18 ; 0 ; 21 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; DRAM_ADDR[6] ; N8 ; 3 ; 20 ; 0 ; 0 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; DRAM_ADDR[7] ; T6 ; 3 ; 14 ; 0 ; 0 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; DRAM_ADDR[8] ; R1 ; 2 ; 0 ; 5 ; 21 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; DRAM_ADDR[9] ; P1 ; 2 ; 0 ; 4 ; 21 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; DRAM_BA[0] ; M7 ; 3 ; 11 ; 0 ; 14 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; DRAM_BA[1] ; M6 ; 3 ; 7 ; 0 ; 7 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; DRAM_CAS_N ; L1 ; 2 ; 0 ; 11 ; 7 ; yes ; no ; yes ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; DRAM_CKE ; L7 ; 3 ; 16 ; 0 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; DRAM_CLK ; R4 ; 3 ; 5 ; 0 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; DRAM_CS_N ; P6 ; 3 ; 11 ; 0 ; 21 ; yes ; no ; yes ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; DRAM_DQM[0] ; R6 ; 3 ; 14 ; 0 ; 7 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; DRAM_DQM[1] ; T5 ; 3 ; 14 ; 0 ; 14 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; DRAM_RAS_N ; L2 ; 2 ; 0 ; 11 ; 0 ; yes ; no ; yes ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; DRAM_WE_N ; C2 ; 1 ; 0 ; 27 ; 0 ; yes ; no ; yes ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; LED[0] ; A15 ; 7 ; 38 ; 34 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; LED[1] ; A13 ; 7 ; 49 ; 34 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; LED[2] ; B13 ; 7 ; 49 ; 34 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; LED[3] ; A11 ; 7 ; 40 ; 34 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; LED[4] ; D1 ; 1 ; 0 ; 25 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; LED[5] ; F3 ; 1 ; 0 ; 26 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; LED[6] ; B1 ; 1 ; 0 ; 28 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; +; LED[7] ; L3 ; 2 ; 0 ; 10 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ; ++---------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Bidir Pins ; ++-------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------+-----------------+------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------+------+-----------------------------------------------------+---------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Output Termination ; Termination Control Block ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ; ++-------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------+-----------------+------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------+------+-----------------------------------------------------+---------------------+ +; DRAM_DQ[0] ; G2 ; 1 ; 0 ; 23 ; 14 ; 0 ; 4 ; no ; yes ; yes ; yes ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; system:inst_cpu|system_sdram:sdram|oe ; - ; +; DRAM_DQ[10] ; T3 ; 3 ; 1 ; 0 ; 0 ; 0 ; 4 ; no ; yes ; yes ; yes ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_10 ; - ; +; DRAM_DQ[11] ; R3 ; 3 ; 1 ; 0 ; 7 ; 0 ; 4 ; no ; yes ; yes ; yes ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_11 ; - ; +; DRAM_DQ[12] ; R5 ; 3 ; 14 ; 0 ; 21 ; 0 ; 4 ; no ; yes ; yes ; yes ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_12 ; - ; +; DRAM_DQ[13] ; P3 ; 3 ; 1 ; 0 ; 14 ; 0 ; 4 ; no ; yes ; yes ; yes ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_13 ; - ; +; DRAM_DQ[14] ; N3 ; 3 ; 1 ; 0 ; 21 ; 0 ; 4 ; no ; yes ; yes ; yes ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_14 ; - ; +; DRAM_DQ[15] ; K1 ; 2 ; 0 ; 12 ; 7 ; 0 ; 4 ; no ; yes ; yes ; yes ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_15 ; - ; +; DRAM_DQ[1] ; G1 ; 1 ; 0 ; 23 ; 21 ; 0 ; 4 ; no ; yes ; yes ; yes ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_1 ; - ; +; DRAM_DQ[2] ; L8 ; 3 ; 18 ; 0 ; 7 ; 0 ; 4 ; no ; yes ; yes ; yes ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_2 ; - ; +; DRAM_DQ[3] ; K5 ; 2 ; 0 ; 7 ; 7 ; 0 ; 4 ; no ; yes ; yes ; yes ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_3 ; - ; +; DRAM_DQ[4] ; K2 ; 2 ; 0 ; 12 ; 0 ; 0 ; 5 ; no ; yes ; yes ; yes ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_4 ; - ; +; DRAM_DQ[5] ; J2 ; 2 ; 0 ; 15 ; 0 ; 0 ; 5 ; no ; yes ; yes ; yes ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_5 ; - ; +; DRAM_DQ[6] ; J1 ; 2 ; 0 ; 15 ; 7 ; 0 ; 4 ; no ; yes ; yes ; yes ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_6 ; - ; +; DRAM_DQ[7] ; R7 ; 3 ; 16 ; 0 ; 14 ; 0 ; 4 ; no ; yes ; yes ; yes ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_7 ; - ; +; DRAM_DQ[8] ; T4 ; 3 ; 5 ; 0 ; 14 ; 0 ; 4 ; no ; yes ; yes ; yes ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_8 ; - ; +; DRAM_DQ[9] ; T2 ; 3 ; 3 ; 0 ; 0 ; 0 ; 4 ; no ; yes ; yes ; yes ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_9 ; - ; +; GPIO_0[0] ; D3 ; 8 ; 1 ; 34 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; - ; - ; +; GPIO_0[10] ; B6 ; 8 ; 16 ; 34 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; - ; - ; +; GPIO_0[11] ; A6 ; 8 ; 16 ; 34 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; - ; - ; +; GPIO_0[12] ; B7 ; 8 ; 18 ; 34 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; - ; - ; +; GPIO_0[13] ; D6 ; 8 ; 9 ; 34 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; - ; - ; +; GPIO_0[14] ; A7 ; 8 ; 20 ; 34 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; - ; - ; +; GPIO_0[15] ; C6 ; 8 ; 18 ; 34 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; - ; - ; +; GPIO_0[16] ; C8 ; 8 ; 23 ; 34 ; 14 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; - ; - ; +; GPIO_0[17] ; E6 ; 8 ; 14 ; 34 ; 14 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; - ; - ; +; GPIO_0[18] ; E7 ; 8 ; 16 ; 34 ; 14 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; - ; - ; +; GPIO_0[19] ; D8 ; 8 ; 23 ; 34 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; - ; - ; +; GPIO_0[1] ; C3 ; 8 ; 1 ; 34 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; - ; - ; +; GPIO_0[20] ; E8 ; 8 ; 20 ; 34 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; - ; - ; +; GPIO_0[21] ; F8 ; 8 ; 20 ; 34 ; 14 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; - ; - ; +; GPIO_0[22] ; F9 ; 7 ; 34 ; 34 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; - ; - ; +; GPIO_0[23] ; E9 ; 7 ; 29 ; 34 ; 14 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; - ; - ; +; GPIO_0[24] ; C9 ; 7 ; 31 ; 34 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; - ; - ; +; GPIO_0[25] ; D9 ; 7 ; 31 ; 34 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; - ; - ; +; GPIO_0[26] ; E11 ; 7 ; 45 ; 34 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; - ; - ; +; GPIO_0[27] ; E10 ; 7 ; 45 ; 34 ; 14 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; - ; - ; +; GPIO_0[28] ; C11 ; 7 ; 38 ; 34 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; - ; - ; +; GPIO_0[29] ; B11 ; 7 ; 40 ; 34 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; - ; - ; +; GPIO_0[2] ; A2 ; 8 ; 7 ; 34 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; - ; - ; +; GPIO_0[30] ; A12 ; 7 ; 43 ; 34 ; 14 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; - ; - ; +; GPIO_0[31] ; D11 ; 7 ; 51 ; 34 ; 14 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; - ; - ; +; GPIO_0[32] ; D12 ; 7 ; 51 ; 34 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; - ; - ; +; GPIO_0[33] ; B12 ; 7 ; 43 ; 34 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; - ; - ; +; GPIO_0[3] ; A3 ; 8 ; 7 ; 34 ; 14 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; - ; - ; +; GPIO_0[4] ; B3 ; 8 ; 3 ; 34 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; - ; - ; +; GPIO_0[5] ; B4 ; 8 ; 7 ; 34 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; - ; - ; +; GPIO_0[6] ; A4 ; 8 ; 9 ; 34 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; - ; - ; +; GPIO_0[7] ; B5 ; 8 ; 11 ; 34 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; - ; - ; +; GPIO_0[8] ; A5 ; 8 ; 14 ; 34 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; - ; - ; +; GPIO_0[9] ; D5 ; 8 ; 5 ; 34 ; 14 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; - ; - ; +; GPIO_1[0] ; F13 ; 6 ; 53 ; 21 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; - ; - ; +; GPIO_1[10] ; P11 ; 4 ; 38 ; 0 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; - ; - ; +; GPIO_1[11] ; R10 ; 4 ; 34 ; 0 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; - ; - ; +; GPIO_1[12] ; N12 ; 4 ; 47 ; 0 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; - ; - ; +; GPIO_1[13] ; P9 ; 4 ; 38 ; 0 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; - ; - ; +; GPIO_1[14] ; N9 ; 4 ; 29 ; 0 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; - ; - ; +; GPIO_1[15] ; N11 ; 4 ; 43 ; 0 ; 14 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; - ; - ; +; GPIO_1[16] ; L16 ; 5 ; 53 ; 11 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; - ; - ; +; GPIO_1[17] ; K16 ; 5 ; 53 ; 12 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; - ; - ; +; GPIO_1[18] ; R16 ; 5 ; 53 ; 8 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; - ; - ; +; GPIO_1[19] ; L15 ; 5 ; 53 ; 11 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; - ; - ; +; GPIO_1[1] ; T15 ; 4 ; 45 ; 0 ; 14 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; - ; - ; +; GPIO_1[20] ; P15 ; 5 ; 53 ; 6 ; 14 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; - ; - ; +; GPIO_1[21] ; P16 ; 5 ; 53 ; 7 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; - ; - ; +; GPIO_1[22] ; R14 ; 4 ; 49 ; 0 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; - ; - ; +; GPIO_1[23] ; N16 ; 5 ; 53 ; 9 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; - ; - ; +; GPIO_1[24] ; N15 ; 5 ; 53 ; 9 ; 14 ; 2 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; - ; - ; +; GPIO_1[25] ; P14 ; 4 ; 49 ; 0 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; - ; - ; +; GPIO_1[26] ; L14 ; 5 ; 53 ; 9 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; - ; - ; +; GPIO_1[27] ; N14 ; 5 ; 53 ; 6 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; - ; - ; +; GPIO_1[28] ; M10 ; 4 ; 43 ; 0 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; - ; - ; +; GPIO_1[29] ; L13 ; 5 ; 53 ; 10 ; 14 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; - ; - ; +; GPIO_1[2] ; T14 ; 4 ; 45 ; 0 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; - ; - ; +; GPIO_1[30] ; J16 ; 5 ; 53 ; 14 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; - ; - ; +; GPIO_1[31] ; K15 ; 5 ; 53 ; 13 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; - ; - ; +; GPIO_1[32] ; J13 ; 5 ; 53 ; 16 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; - ; - ; +; GPIO_1[33] ; J14 ; 5 ; 53 ; 15 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; - ; - ; +; GPIO_1[3] ; T13 ; 4 ; 40 ; 0 ; 14 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; - ; - ; +; GPIO_1[4] ; R13 ; 4 ; 40 ; 0 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; - ; - ; +; GPIO_1[5] ; T12 ; 4 ; 36 ; 0 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; - ; - ; +; GPIO_1[6] ; R12 ; 4 ; 36 ; 0 ; 14 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; - ; - ; +; GPIO_1[7] ; T11 ; 4 ; 36 ; 0 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; - ; - ; +; GPIO_1[8] ; T10 ; 4 ; 34 ; 0 ; 14 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; - ; - ; +; GPIO_1[9] ; R11 ; 4 ; 34 ; 0 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; - ; - ; ++-------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------+-----------------+------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------+------+-----------------------------------------------------+---------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------+ +; Dual Purpose and Dedicated Pins ; ++----------+------------------------------------------+--------------------------+-------------------------+---------------------------+ +; Location ; Pin Name ; Reserved As ; User Signal Name ; Pin Type ; ++----------+------------------------------------------+--------------------------+-------------------------+---------------------------+ +; C1 ; DIFFIO_L3n, DATA1, ASDO ; As input tri-stated ; ~ALTERA_ASDO_DATA1~ ; Dual Purpose Pin ; +; D2 ; DIFFIO_L4p, FLASH_nCE, nCSO ; As input tri-stated ; ~ALTERA_FLASH_nCE_nCSO~ ; Dual Purpose Pin ; +; F4 ; nSTATUS ; - ; - ; Dedicated Programming Pin ; +; H1 ; DCLK ; As output driving ground ; ~ALTERA_DCLK~ ; Dual Purpose Pin ; +; H2 ; DATA0 ; As input tri-stated ; ~ALTERA_DATA0~ ; Dual Purpose Pin ; +; H5 ; nCONFIG ; - ; - ; Dedicated Programming Pin ; +; H4 ; TDI ; - ; altera_reserved_tdi ; JTAG Pin ; +; H3 ; TCK ; - ; altera_reserved_tck ; JTAG Pin ; +; J5 ; TMS ; - ; altera_reserved_tms ; JTAG Pin ; +; J4 ; TDO ; - ; altera_reserved_tdo ; JTAG Pin ; +; J3 ; nCE ; - ; - ; Dedicated Programming Pin ; +; J16 ; DIFFIO_R9n, DEV_OE ; Use as regular IO ; GPIO_1[30] ; Dual Purpose Pin ; +; J15 ; DIFFIO_R9p, DEV_CLRn ; Use as regular IO ; KEY[0] ; Dual Purpose Pin ; +; H14 ; CONF_DONE ; - ; - ; Dedicated Programming Pin ; +; H13 ; MSEL0 ; - ; - ; Dedicated Programming Pin ; +; H12 ; MSEL1 ; - ; - ; Dedicated Programming Pin ; +; G12 ; MSEL2 ; - ; - ; Dedicated Programming Pin ; +; G12 ; MSEL3 ; - ; - ; Dedicated Programming Pin ; +; F16 ; DIFFIO_R4n, nCEO ; Use as programming pin ; ~ALTERA_nCEO~ ; Dual Purpose Pin ; +; B11 ; DIFFIO_T20p, PADD0 ; Use as regular IO ; GPIO_0[29] ; Dual Purpose Pin ; +; A15 ; DIFFIO_T19n, PADD1 ; Use as regular IO ; LED[0] ; Dual Purpose Pin ; +; F9 ; DIFFIO_T17p, PADD4, DQS2T/CQ3T,DPCLK8 ; Use as regular IO ; GPIO_0[22] ; Dual Purpose Pin ; +; C9 ; DIFFIO_T15n, PADD7 ; Use as regular IO ; GPIO_0[24] ; Dual Purpose Pin ; +; D9 ; DIFFIO_T15p, PADD8 ; Use as regular IO ; GPIO_0[25] ; Dual Purpose Pin ; +; E9 ; DIFFIO_T13p, PADD12, DQS4T/CQ5T,DPCLK9 ; Use as regular IO ; GPIO_0[23] ; Dual Purpose Pin ; +; C8 ; DIFFIO_T11p, PADD17, DQS5T/CQ5T#,DPCLK10 ; Use as regular IO ; GPIO_0[16] ; Dual Purpose Pin ; +; E8 ; DIFFIO_T10n, DATA2 ; Use as regular IO ; GPIO_0[20] ; Dual Purpose Pin ; +; F8 ; DIFFIO_T10p, DATA3 ; Use as regular IO ; GPIO_0[21] ; Dual Purpose Pin ; +; A7 ; DIFFIO_T9n, PADD18 ; Use as regular IO ; GPIO_0[14] ; Dual Purpose Pin ; +; B7 ; DIFFIO_T9p, DATA4 ; Use as regular IO ; GPIO_0[12] ; Dual Purpose Pin ; +; A6 ; DIFFIO_T7n, DATA14, DQS3T/CQ3T#,DPCLK11 ; Use as regular IO ; GPIO_0[11] ; Dual Purpose Pin ; +; B6 ; DIFFIO_T7p, DATA13 ; Use as regular IO ; GPIO_0[10] ; Dual Purpose Pin ; +; E7 ; DATA5 ; Use as regular IO ; GPIO_0[18] ; Dual Purpose Pin ; +; E6 ; DIFFIO_T6p, DATA6 ; Use as regular IO ; GPIO_0[17] ; Dual Purpose Pin ; +; A5 ; DIFFIO_T5n, DATA7 ; Use as regular IO ; GPIO_0[8] ; Dual Purpose Pin ; +; B5 ; DIFFIO_T5p, DATA8 ; Use as regular IO ; GPIO_0[7] ; Dual Purpose Pin ; +; D6 ; DIFFIO_T4n, DATA9 ; Use as regular IO ; GPIO_0[13] ; Dual Purpose Pin ; +; A4 ; DIFFIO_T3n, DATA10 ; Use as regular IO ; GPIO_0[6] ; Dual Purpose Pin ; +; B4 ; DIFFIO_T3p, DATA11 ; Use as regular IO ; GPIO_0[5] ; Dual Purpose Pin ; +; B3 ; DATA12, DQS1T/CQ1T#,CDPCLK7 ; Use as regular IO ; GPIO_0[4] ; Dual Purpose Pin ; ++----------+------------------------------------------+--------------------------+-------------------------+---------------------------+ + + ++-------------------------------------------------------------+ +; I/O Bank Usage ; ++----------+-------------------+---------------+--------------+ +; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; ++----------+-------------------+---------------+--------------+ +; 1 ; 11 / 14 ( 79 % ) ; 2.5V ; -- ; +; 2 ; 15 / 16 ( 94 % ) ; 2.5V ; -- ; +; 3 ; 25 / 25 ( 100 % ) ; 2.5V ; -- ; +; 4 ; 18 / 20 ( 90 % ) ; 2.5V ; -- ; +; 5 ; 17 / 18 ( 94 % ) ; 2.5V ; -- ; +; 6 ; 2 / 13 ( 15 % ) ; 2.5V ; -- ; +; 7 ; 17 / 24 ( 71 % ) ; 2.5V ; -- ; +; 8 ; 22 / 24 ( 92 % ) ; 2.5V ; -- ; ++----------+-------------------+---------------+--------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; All Package Pins ; ++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ; ++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +; A1 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; A2 ; 238 ; 8 ; GPIO_0[2] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; A3 ; 239 ; 8 ; GPIO_0[3] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; A4 ; 236 ; 8 ; GPIO_0[6] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; A5 ; 232 ; 8 ; GPIO_0[8] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; A6 ; 225 ; 8 ; GPIO_0[11] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; A7 ; 220 ; 8 ; GPIO_0[14] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; A8 ; 211 ; 8 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; A9 ; 209 ; 7 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; A10 ; 198 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A11 ; 188 ; 7 ; LED[3] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; A12 ; 186 ; 7 ; GPIO_0[30] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; A13 ; 179 ; 7 ; LED[1] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; A14 ; 181 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; A15 ; 191 ; 7 ; LED[0] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; A16 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; B1 ; 5 ; 1 ; LED[6] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; B2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B3 ; 242 ; 8 ; GPIO_0[4] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; B4 ; 237 ; 8 ; GPIO_0[5] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; B5 ; 233 ; 8 ; GPIO_0[7] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; B6 ; 226 ; 8 ; GPIO_0[10] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; B7 ; 221 ; 8 ; GPIO_0[12] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; B8 ; 212 ; 8 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; B9 ; 210 ; 7 ; SW[2] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; B10 ; 199 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B11 ; 189 ; 7 ; GPIO_0[29] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; B12 ; 187 ; 7 ; GPIO_0[33] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; B13 ; 180 ; 7 ; LED[2] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; B14 ; 182 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; B15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B16 ; 164 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C1 ; 7 ; 1 ; ~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ; +; C2 ; 6 ; 1 ; DRAM_WE_N ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; C3 ; 245 ; 8 ; GPIO_0[1] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; C4 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; C5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C6 ; 224 ; 8 ; GPIO_0[15] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; C7 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; C8 ; 215 ; 8 ; GPIO_0[16] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; C9 ; 200 ; 7 ; GPIO_0[24] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; C10 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; C11 ; 190 ; 7 ; GPIO_0[28] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; C12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C13 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; C14 ; 175 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; C15 ; 174 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; C16 ; 173 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D1 ; 10 ; 1 ; LED[4] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; D2 ; 9 ; 1 ; ~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ; +; D3 ; 246 ; 8 ; GPIO_0[0] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; D4 ; ; ; VCCD_PLL3 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; D5 ; 241 ; 8 ; GPIO_0[9] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; D6 ; 234 ; 8 ; GPIO_0[13] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; D7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D8 ; 216 ; 8 ; GPIO_0[19] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; D9 ; 201 ; 7 ; GPIO_0[25] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; D10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D11 ; 177 ; 7 ; GPIO_0[31] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; D12 ; 178 ; 7 ; GPIO_0[32] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; D13 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; D14 ; 176 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D15 ; 170 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; D16 ; 169 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E1 ; 26 ; 1 ; KEY[1] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; E2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E3 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; E4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E5 ; ; ; GNDA3 ; gnd ; ; ; -- ; ; -- ; -- ; +; E6 ; 231 ; 8 ; GPIO_0[17] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; E7 ; 227 ; 8 ; GPIO_0[18] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; E8 ; 218 ; 8 ; GPIO_0[20] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; E9 ; 205 ; 7 ; GPIO_0[23] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; E10 ; 184 ; 7 ; GPIO_0[27] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; E11 ; 183 ; 7 ; GPIO_0[26] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; E12 ; ; ; GNDA2 ; gnd ; ; ; -- ; ; -- ; -- ; +; E13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E14 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; E15 ; 151 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; E16 ; 150 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; F1 ; 14 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F2 ; 13 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F3 ; 8 ; 1 ; LED[5] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; F4 ; 11 ; 1 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ; +; F5 ; ; -- ; VCCA3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F7 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; F8 ; 219 ; 8 ; GPIO_0[21] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; F9 ; 197 ; 7 ; GPIO_0[22] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; F10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; F12 ; ; -- ; VCCA2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F13 ; 161 ; 6 ; GPIO_1[0] ; bidir ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; F14 ; 167 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F15 ; 163 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; F16 ; 162 ; 6 ; ~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; G1 ; 16 ; 1 ; DRAM_DQ[1] ; bidir ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; G2 ; 15 ; 1 ; DRAM_DQ[0] ; bidir ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; G3 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G5 ; 12 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G6 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; G7 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; G8 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; G9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; G10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; G11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G12 ; 155 ; 6 ; ^MSEL2 ; ; ; ; -- ; ; -- ; -- ; +; G12 ; 156 ; 6 ; ^MSEL3 ; ; ; ; -- ; ; -- ; -- ; +; G13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G14 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G15 ; 160 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; G16 ; 159 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H1 ; 17 ; 1 ; ~ALTERA_DCLK~ ; output ; 2.5 V ; ; Row I/O ; N ; no ; On ; +; H2 ; 18 ; 1 ; ~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ; +; H3 ; 21 ; 1 ; altera_reserved_tck ; input ; 2.5 V ; ; -- ; N ; no ; Off ; +; H4 ; 20 ; 1 ; altera_reserved_tdi ; input ; 2.5 V ; ; -- ; N ; no ; Off ; +; H5 ; 19 ; 1 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ; +; H6 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; H7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; H12 ; 154 ; 6 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ; +; H13 ; 153 ; 6 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ; +; H14 ; 152 ; 6 ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ; +; H15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J1 ; 30 ; 2 ; DRAM_DQ[6] ; bidir ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; J2 ; 29 ; 2 ; DRAM_DQ[5] ; bidir ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; J3 ; 24 ; 1 ; ^nCE ; ; ; ; -- ; ; -- ; -- ; +; J4 ; 23 ; 1 ; altera_reserved_tdo ; output ; 2.5 V ; ; -- ; N ; no ; Off ; +; J5 ; 22 ; 1 ; altera_reserved_tms ; input ; 2.5 V ; ; -- ; N ; no ; Off ; +; J6 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J13 ; 146 ; 5 ; GPIO_1[32] ; bidir ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; J14 ; 144 ; 5 ; GPIO_1[33] ; bidir ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; J15 ; 143 ; 5 ; KEY[0] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; J16 ; 142 ; 5 ; GPIO_1[30] ; bidir ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; K1 ; 37 ; 2 ; DRAM_DQ[15] ; bidir ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; K2 ; 36 ; 2 ; DRAM_DQ[4] ; bidir ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; K3 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K5 ; 45 ; 2 ; DRAM_DQ[3] ; bidir ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; K6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K7 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; K8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; K10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; K11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; K12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K14 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; K15 ; 141 ; 5 ; GPIO_1[31] ; bidir ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; K16 ; 140 ; 5 ; GPIO_1[17] ; bidir ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; L1 ; 39 ; 2 ; DRAM_CAS_N ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; L2 ; 38 ; 2 ; DRAM_RAS_N ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; L3 ; 40 ; 2 ; LED[7] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; L4 ; 46 ; 2 ; DRAM_ADDR[12] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; L5 ; ; -- ; VCCA1 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; L6 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; L7 ; 75 ; 3 ; DRAM_CKE ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; L8 ; 79 ; 3 ; DRAM_DQ[2] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; L9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L12 ; ; -- ; VCCA4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; L13 ; 136 ; 5 ; GPIO_1[29] ; bidir ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; L14 ; 134 ; 5 ; GPIO_1[26] ; bidir ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; L15 ; 138 ; 5 ; GPIO_1[19] ; bidir ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; L16 ; 137 ; 5 ; GPIO_1[16] ; bidir ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; M1 ; 28 ; 2 ; SW[0] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; M2 ; 27 ; 2 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; M3 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; M4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M5 ; ; ; GNDA1 ; gnd ; ; ; -- ; ; -- ; -- ; +; M6 ; 64 ; 3 ; DRAM_BA[1] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; M7 ; 68 ; 3 ; DRAM_BA[0] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; M8 ; 81 ; 3 ; DRAM_ADDR[3] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; M9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M10 ; 111 ; 4 ; GPIO_1[28] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; M11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M12 ; ; ; GNDA4 ; gnd ; ; ; -- ; ; -- ; -- ; +; M13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M14 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; M15 ; 149 ; 5 ; SW[3] ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; M16 ; 148 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; N1 ; 44 ; 2 ; DRAM_ADDR[11] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; N2 ; 43 ; 2 ; DRAM_ADDR[10] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; N3 ; 52 ; 3 ; DRAM_DQ[14] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; N4 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; N5 ; 62 ; 3 ; DRAM_ADDR[1] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; N6 ; 63 ; 3 ; DRAM_ADDR[2] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; N7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N8 ; 82 ; 3 ; DRAM_ADDR[6] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; N9 ; 93 ; 4 ; GPIO_1[14] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; N10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N11 ; 112 ; 4 ; GPIO_1[15] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; N12 ; 117 ; 4 ; GPIO_1[12] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; N13 ; ; ; VCCD_PLL4 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; N14 ; 126 ; 5 ; GPIO_1[27] ; bidir ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; N15 ; 133 ; 5 ; GPIO_1[24] ; bidir ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; N16 ; 132 ; 5 ; GPIO_1[23] ; bidir ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; P1 ; 51 ; 2 ; DRAM_ADDR[9] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; P2 ; 50 ; 2 ; DRAM_ADDR[0] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; P3 ; 53 ; 3 ; DRAM_DQ[13] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; P4 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; P5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P6 ; 67 ; 3 ; DRAM_CS_N ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; P7 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; P8 ; 85 ; 3 ; DRAM_ADDR[4] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; P9 ; 105 ; 4 ; GPIO_1[13] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; P10 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; P11 ; 106 ; 4 ; GPIO_1[10] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; P12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P13 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; P14 ; 119 ; 4 ; GPIO_1[25] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; P15 ; 127 ; 5 ; GPIO_1[20] ; bidir ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; P16 ; 128 ; 5 ; GPIO_1[21] ; bidir ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; R1 ; 49 ; 2 ; DRAM_ADDR[8] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; R2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R3 ; 54 ; 3 ; DRAM_DQ[11] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; R4 ; 60 ; 3 ; DRAM_CLK ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; R5 ; 71 ; 3 ; DRAM_DQ[12] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; R6 ; 73 ; 3 ; DRAM_DQM[0] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; R7 ; 76 ; 3 ; DRAM_DQ[7] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; R8 ; 86 ; 3 ; CLOCK_50 ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; R9 ; 88 ; 4 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; R10 ; 96 ; 4 ; GPIO_1[11] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; R11 ; 98 ; 4 ; GPIO_1[9] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; R12 ; 100 ; 4 ; GPIO_1[6] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; R13 ; 107 ; 4 ; GPIO_1[4] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; R14 ; 120 ; 4 ; GPIO_1[22] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; R15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R16 ; 129 ; 5 ; GPIO_1[18] ; bidir ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; T1 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T2 ; 59 ; 3 ; DRAM_DQ[9] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; T3 ; 55 ; 3 ; DRAM_DQ[10] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; T4 ; 61 ; 3 ; DRAM_DQ[8] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; T5 ; 72 ; 3 ; DRAM_DQM[1] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; T6 ; 74 ; 3 ; DRAM_ADDR[7] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; T7 ; 77 ; 3 ; DRAM_ADDR[5] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; T8 ; 87 ; 3 ; SW[1] ; input ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; T9 ; 89 ; 4 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; T10 ; 97 ; 4 ; GPIO_1[8] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; T11 ; 99 ; 4 ; GPIO_1[7] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; T12 ; 101 ; 4 ; GPIO_1[5] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; T13 ; 108 ; 4 ; GPIO_1[3] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; T14 ; 115 ; 4 ; GPIO_1[2] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; T15 ; 116 ; 4 ; GPIO_1[1] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; T16 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; ++----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +Note: Pin directions (input, output or bidir) are based on device operating in user mode. + + ++-----------------------------------------------------------------------------------------------------------------+ +; PLL Summary ; ++-------------------------------+---------------------------------------------------------------------------------+ +; Name ; pll_sys:inst_pll_sys|altpll:altpll_component|pll_sys_altpll:auto_generated|pll1 ; ++-------------------------------+---------------------------------------------------------------------------------+ +; SDC pin name ; inst_pll_sys|altpll_component|auto_generated|pll1 ; +; PLL mode ; Normal ; +; Compensate clock ; clock0 ; +; Compensated input/output pins ; -- ; +; Switchover type ; -- ; +; Input frequency 0 ; 50.0 MHz ; +; Input frequency 1 ; -- ; +; Nominal PFD frequency ; 50.0 MHz ; +; Nominal VCO frequency ; 500.0 MHz ; +; VCO post scale K counter ; 2 ; +; VCO frequency control ; Auto ; +; VCO phase shift step ; 250 ps ; +; VCO multiply ; -- ; +; VCO divide ; -- ; +; Freq min lock ; 30.0 MHz ; +; Freq max lock ; 65.02 MHz ; +; M VCO Tap ; 6 ; +; M Initial ; 1 ; +; M value ; 10 ; +; N value ; 1 ; +; Charge pump current ; setting 1 ; +; Loop filter resistance ; setting 27 ; +; Loop filter capacitance ; setting 0 ; +; Bandwidth ; 1.03 MHz to 1.97 MHz ; +; Bandwidth type ; Medium ; +; Real time reconfigurable ; Off ; +; Scan chain MIF file ; -- ; +; Preserve PLL counter order ; Off ; +; PLL location ; PLL_4 ; +; Inclk0 signal ; CLOCK_50 ; +; Inclk1 signal ; -- ; +; Inclk0 signal type ; Dedicated Pin ; +; Inclk1 signal type ; -- ; ++-------------------------------+---------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; PLL Usage ; ++---------------------------------------------------------------------------------------------+--------------+------+-----+------------------+----------------+------------------+------------+---------+---------------+------------+---------------+---------+---------+----------------------------------------------------------+ +; Name ; Output Clock ; Mult ; Div ; Output Frequency ; Phase Shift ; Phase Shift Step ; Duty Cycle ; Counter ; Counter Value ; High / Low ; Cascade Input ; Initial ; VCO Tap ; SDC Pin Name ; ++---------------------------------------------------------------------------------------------+--------------+------+-----+------------------+----------------+------------------+------------+---------+---------------+------------+---------------+---------+---------+----------------------------------------------------------+ +; pll_sys:inst_pll_sys|altpll:altpll_component|pll_sys_altpll:auto_generated|wire_pll1_clk[0] ; clock0 ; 2 ; 1 ; 100.0 MHz ; 0 (0 ps) ; 9.00 (250 ps) ; 50/50 ; C0 ; 5 ; 3/2 Odd ; -- ; 1 ; 6 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; pll_sys:inst_pll_sys|altpll:altpll_component|pll_sys_altpll:auto_generated|wire_pll1_clk[1] ; clock1 ; 2 ; 1 ; 100.0 MHz ; -54 (-1500 ps) ; 9.00 (250 ps) ; 50/50 ; C2 ; 5 ; 3/2 Odd ; -- ; 1 ; 0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[1] ; +; pll_sys:inst_pll_sys|altpll:altpll_component|pll_sys_altpll:auto_generated|wire_pll1_clk[2] ; clock2 ; 1 ; 5 ; 10.0 MHz ; 0 (0 ps) ; 0.90 (250 ps) ; 50/50 ; C1 ; 50 ; 25/25 Even ; -- ; 1 ; 6 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; ++---------------------------------------------------------------------------------------------+--------------+------+-----+------------------+----------------+------------------+------------+---------+---------------+------------+---------------+---------+---------+----------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Resource Utilization by Entity ; ++-----------------------------------------------------------------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+ +; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Library Name ; ++-----------------------------------------------------------------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+ +; |de0_nano_system ; 4562 (1) ; 2790 (0) ; 69 (69) ; 119808 ; 24 ; 4 ; 0 ; 2 ; 122 ; 0 ; 1772 (1) ; 625 (0) ; 2165 (0) ; |de0_nano_system ; ; +; |heartbeat:inst_heartbeat| ; 22 (22) ; 22 (22) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 22 (22) ; |de0_nano_system|heartbeat:inst_heartbeat ; ; +; |pll_sys:inst_pll_sys| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |de0_nano_system|pll_sys:inst_pll_sys ; ; +; |altpll:altpll_component| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |de0_nano_system|pll_sys:inst_pll_sys|altpll:altpll_component ; ; +; |pll_sys_altpll:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |de0_nano_system|pll_sys:inst_pll_sys|altpll:altpll_component|pll_sys_altpll:auto_generated ; ; +; |sld_hub:auto_hub| ; 175 (1) ; 97 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 78 (1) ; 19 (0) ; 78 (0) ; |de0_nano_system|sld_hub:auto_hub ; ; +; |sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst| ; 174 (133) ; 97 (69) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 77 (64) ; 19 (17) ; 78 (53) ; |de0_nano_system|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst ; ; +; |sld_rom_sr:hub_info_reg| ; 21 (21) ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 12 (12) ; 0 (0) ; 9 (9) ; |de0_nano_system|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg ; ; +; |sld_shadow_jsm:shadow_jsm| ; 20 (20) ; 19 (19) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 2 (2) ; 17 (17) ; |de0_nano_system|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm ; ; +; |system:inst_cpu| ; 4364 (0) ; 2671 (0) ; 0 (0) ; 119808 ; 24 ; 4 ; 0 ; 2 ; 0 ; 0 ; 1693 (0) ; 606 (0) ; 2065 (0) ; |de0_nano_system|system:inst_cpu ; ; +; |altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 8 (8) ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 6 (6) ; |de0_nano_system|system:inst_cpu|altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo ; ; +; |altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 7 (7) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 4 (4) ; |de0_nano_system|system:inst_cpu|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo ; ; +; |altera_avalon_sc_fifo:pio_key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 4 (4) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 4 (4) ; |de0_nano_system|system:inst_cpu|altera_avalon_sc_fifo:pio_key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; ; +; |altera_avalon_sc_fifo:pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 4 (4) ; |de0_nano_system|system:inst_cpu|altera_avalon_sc_fifo:pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; ; +; |altera_avalon_sc_fifo:pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 4 (4) ; |de0_nano_system|system:inst_cpu|altera_avalon_sc_fifo:pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; ; +; |altera_avalon_sc_fifo:pio_sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 4 (4) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 4 (4) ; |de0_nano_system|system:inst_cpu|altera_avalon_sc_fifo:pio_sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; ; +; |altera_avalon_sc_fifo:rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 4 (4) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 4 (4) ; |de0_nano_system|system:inst_cpu|altera_avalon_sc_fifo:rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo ; ; +; |altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 68 (68) ; 56 (56) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 12 (12) ; 6 (6) ; 50 (50) ; |de0_nano_system|system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; ; +; |altera_avalon_sc_fifo:sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 4 (4) ; |de0_nano_system|system:inst_cpu|altera_avalon_sc_fifo:sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; ; +; |altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 4 (4) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 4 (4) ; |de0_nano_system|system:inst_cpu|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo ; ; +; |altera_avalon_sc_fifo:uart_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 4 (4) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 4 (4) ; |de0_nano_system|system:inst_cpu|altera_avalon_sc_fifo:uart_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; ; +; |altera_merlin_slave_agent:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent| ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 2 (2) ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_agent:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent ; ; +; |altera_merlin_slave_agent:pio_key_s1_translator_avalon_universal_slave_0_agent| ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_agent:pio_key_s1_translator_avalon_universal_slave_0_agent ; ; +; |altera_merlin_slave_agent:pio_led_s1_translator_avalon_universal_slave_0_agent| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_agent:pio_led_s1_translator_avalon_universal_slave_0_agent ; ; +; |altera_merlin_slave_agent:pio_sw_s1_translator_avalon_universal_slave_0_agent| ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_agent:pio_sw_s1_translator_avalon_universal_slave_0_agent ; ; +; |altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent| ; 17 (9) ; 3 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 13 (8) ; 0 (0) ; 4 (1) ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent ; ; +; |altera_merlin_burst_uncompressor:uncompressor| ; 8 (8) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 5 (5) ; 0 (0) ; 3 (3) ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor ; ; +; |altera_merlin_slave_agent:sys_clk_timer_s1_translator_avalon_universal_slave_0_agent| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_agent:sys_clk_timer_s1_translator_avalon_universal_slave_0_agent ; ; +; |altera_merlin_slave_agent:sysid_control_slave_translator_avalon_universal_slave_0_agent| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_agent:sysid_control_slave_translator_avalon_universal_slave_0_agent ; ; +; |altera_merlin_slave_translator:cpu_jtag_debug_module_translator| ; 42 (42) ; 37 (37) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 5 (5) ; 0 (0) ; 37 (37) ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_translator:cpu_jtag_debug_module_translator ; ; +; |altera_merlin_slave_translator:jtag_uart_0_avalon_jtag_slave_translator| ; 23 (23) ; 23 (23) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 22 (22) ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_translator:jtag_uart_0_avalon_jtag_slave_translator ; ; +; |altera_merlin_slave_translator:pio_key_s1_translator| ; 7 (7) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 1 (1) ; 4 (4) ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_translator:pio_key_s1_translator ; ; +; |altera_merlin_slave_translator:pio_led_s1_translator| ; 16 (16) ; 10 (10) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 6 (6) ; 0 (0) ; 10 (10) ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_translator:pio_led_s1_translator ; ; +; |altera_merlin_slave_translator:pio_motor_rst_s1_translator| ; 8 (8) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 4 (4) ; 0 (0) ; 4 (4) ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_translator:pio_motor_rst_s1_translator ; ; +; |altera_merlin_slave_translator:pio_sw_s1_translator| ; 9 (9) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 7 (7) ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_translator:pio_sw_s1_translator ; ; +; |altera_merlin_slave_translator:rs232_motor_avalon_rs232_slave_translator| ; 4 (4) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 1 (1) ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_translator:rs232_motor_avalon_rs232_slave_translator ; ; +; |altera_merlin_slave_translator:sys_clk_timer_s1_translator| ; 24 (24) ; 19 (19) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 5 (5) ; 7 (7) ; 12 (12) ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_translator:sys_clk_timer_s1_translator ; ; +; |altera_merlin_slave_translator:sysid_control_slave_translator| ; 13 (13) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 9 (9) ; 1 (1) ; 3 (3) ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_translator:sysid_control_slave_translator ; ; +; |altera_merlin_slave_translator:uart_0_s1_translator| ; 23 (23) ; 20 (20) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 2 (2) ; 18 (18) ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_translator:uart_0_s1_translator ; ; +; |altera_merlin_traffic_limiter:limiter_001| ; 36 (36) ; 20 (20) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 16 (16) ; 0 (0) ; 20 (20) ; |de0_nano_system|system:inst_cpu|altera_merlin_traffic_limiter:limiter_001 ; ; +; |altera_merlin_traffic_limiter:limiter| ; 15 (15) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 8 (8) ; 0 (0) ; 7 (7) ; |de0_nano_system|system:inst_cpu|altera_merlin_traffic_limiter:limiter ; ; +; |altera_merlin_width_adapter:width_adapter_001| ; 32 (32) ; 16 (16) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 16 (16) ; 0 (0) ; 16 (16) ; |de0_nano_system|system:inst_cpu|altera_merlin_width_adapter:width_adapter_001 ; ; +; |altera_merlin_width_adapter:width_adapter| ; 83 (83) ; 44 (44) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 22 (22) ; 8 (8) ; 53 (53) ; |de0_nano_system|system:inst_cpu|altera_merlin_width_adapter:width_adapter ; ; +; |altera_reset_controller:rst_controller| ; 4 (1) ; 3 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 2 (0) ; 1 (0) ; |de0_nano_system|system:inst_cpu|altera_reset_controller:rst_controller ; ; +; |altera_reset_synchronizer:alt_rst_sync_uq1| ; 3 (3) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 2 (2) ; 1 (1) ; |de0_nano_system|system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1 ; ; +; |system_addr_router:addr_router| ; 5 (5) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 3 (3) ; |de0_nano_system|system:inst_cpu|system_addr_router:addr_router ; ; +; |system_addr_router_001:addr_router_001| ; 36 (36) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 23 (23) ; 0 (0) ; 13 (13) ; |de0_nano_system|system:inst_cpu|system_addr_router_001:addr_router_001 ; ; +; |system_cmd_xbar_demux:cmd_xbar_demux| ; 5 (5) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 5 (5) ; 0 (0) ; 0 (0) ; |de0_nano_system|system:inst_cpu|system_cmd_xbar_demux:cmd_xbar_demux ; ; +; |system_cmd_xbar_demux_001:cmd_xbar_demux_001| ; 22 (22) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 21 (21) ; 0 (0) ; 1 (1) ; |de0_nano_system|system:inst_cpu|system_cmd_xbar_demux_001:cmd_xbar_demux_001 ; ; +; |system_cmd_xbar_mux:cmd_xbar_mux_001| ; 52 (48) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 17 (15) ; 2 (2) ; 33 (31) ; |de0_nano_system|system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux_001 ; ; +; |altera_merlin_arbitrator:arb| ; 4 (4) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 2 (2) ; |de0_nano_system|system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux_001|altera_merlin_arbitrator:arb ; ; +; |system_cmd_xbar_mux:cmd_xbar_mux| ; 58 (52) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 50 (46) ; 2 (2) ; 6 (4) ; |de0_nano_system|system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux ; ; +; |altera_merlin_arbitrator:arb| ; 6 (6) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 4 (4) ; 0 (0) ; 2 (2) ; |de0_nano_system|system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux|altera_merlin_arbitrator:arb ; ; +; |system_cpu:cpu| ; 2623 (2263) ; 1588 (1402) ; 0 (0) ; 116736 ; 20 ; 4 ; 0 ; 2 ; 0 ; 0 ; 1007 (863) ; 442 (387) ; 1174 (1011) ; |de0_nano_system|system:inst_cpu|system_cpu:cpu ; ; +; |lpm_add_sub:Add17| ; 66 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 61 (0) ; 0 (0) ; 5 (0) ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|lpm_add_sub:Add17 ; ; +; |add_sub_qvi:auto_generated| ; 66 (66) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 61 (61) ; 0 (0) ; 5 (5) ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|lpm_add_sub:Add17|add_sub_qvi:auto_generated ; ; +; |system_cpu_bht_module:system_cpu_bht| ; 0 (0) ; 0 (0) ; 0 (0) ; 512 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_bht_module:system_cpu_bht ; ; +; |altsyncram:the_altsyncram| ; 0 (0) ; 0 (0) ; 0 (0) ; 512 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_bht_module:system_cpu_bht|altsyncram:the_altsyncram ; ; +; |altsyncram_fhg1:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 512 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_bht_module:system_cpu_bht|altsyncram:the_altsyncram|altsyncram_fhg1:auto_generated ; ; +; |system_cpu_dc_data_module:system_cpu_dc_data| ; 0 (0) ; 0 (0) ; 0 (0) ; 32768 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_dc_data_module:system_cpu_dc_data ; ; +; |altsyncram:the_altsyncram| ; 0 (0) ; 0 (0) ; 0 (0) ; 32768 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_dc_data_module:system_cpu_dc_data|altsyncram:the_altsyncram ; ; +; |altsyncram_2jf1:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 32768 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_dc_data_module:system_cpu_dc_data|altsyncram:the_altsyncram|altsyncram_2jf1:auto_generated ; ; +; |system_cpu_dc_tag_module:system_cpu_dc_tag| ; 0 (0) ; 0 (0) ; 0 (0) ; 2048 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_dc_tag_module:system_cpu_dc_tag ; ; +; |altsyncram:the_altsyncram| ; 0 (0) ; 0 (0) ; 0 (0) ; 2048 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_dc_tag_module:system_cpu_dc_tag|altsyncram:the_altsyncram ; ; +; |altsyncram_d9g1:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 2048 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_dc_tag_module:system_cpu_dc_tag|altsyncram:the_altsyncram|altsyncram_d9g1:auto_generated ; ; +; |system_cpu_dc_victim_module:system_cpu_dc_victim| ; 0 (0) ; 0 (0) ; 0 (0) ; 256 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_dc_victim_module:system_cpu_dc_victim ; ; +; |altsyncram:the_altsyncram| ; 0 (0) ; 0 (0) ; 0 (0) ; 256 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_dc_victim_module:system_cpu_dc_victim|altsyncram:the_altsyncram ; ; +; |altsyncram_r3d1:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 256 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_dc_victim_module:system_cpu_dc_victim|altsyncram:the_altsyncram|altsyncram_r3d1:auto_generated ; ; +; |system_cpu_ic_data_module:system_cpu_ic_data| ; 2 (0) ; 1 (0) ; 0 (0) ; 65536 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 1 (0) ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data ; ; +; |altsyncram:the_altsyncram| ; 2 (0) ; 1 (0) ; 0 (0) ; 65536 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 1 (0) ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram ; ; +; |altsyncram_sjd1:auto_generated| ; 2 (2) ; 1 (1) ; 0 (0) ; 65536 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 1 (1) ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated ; ; +; |system_cpu_ic_tag_module:system_cpu_ic_tag| ; 0 (0) ; 0 (0) ; 0 (0) ; 5376 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag ; ; +; |altsyncram:the_altsyncram| ; 0 (0) ; 0 (0) ; 0 (0) ; 5376 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram ; ; +; |altsyncram_qtg1:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 5376 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated ; ; +; |system_cpu_mult_cell:the_system_cpu_mult_cell| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 4 ; 0 ; 2 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell ; ; +; |altmult_add:the_altmult_add_part_1| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1 ; ; +; |mult_add_75u2:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated ; ; +; |ded_mult_ks81:ded_mult1| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1 ; ; +; |altmult_add:the_altmult_add_part_2| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2 ; ; +; |mult_add_95u2:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated ; ; +; |ded_mult_ks81:ded_mult1| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated|ded_mult_ks81:ded_mult1 ; ; +; |system_cpu_nios2_oci:the_system_cpu_nios2_oci| ; 285 (29) ; 185 (0) ; 0 (0) ; 8192 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 72 (1) ; 55 (0) ; 158 (28) ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci ; ; +; |system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper| ; 145 (0) ; 96 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 49 (0) ; 53 (0) ; 43 (0) ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper ; ; +; |sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy| ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 1 (1) ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy ; ; +; |system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk| ; 53 (49) ; 49 (45) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 4 (4) ; 46 (43) ; 3 (2) ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk ; ; +; |altera_std_synchronizer:the_altera_std_synchronizer2| ; 2 (2) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 1 (1) ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer2 ; ; +; |altera_std_synchronizer:the_altera_std_synchronizer3| ; 2 (2) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 2 (2) ; 0 (0) ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3 ; ; +; |system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck| ; 89 (85) ; 47 (43) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 42 (42) ; 7 (3) ; 40 (40) ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck ; ; +; |altera_std_synchronizer:the_altera_std_synchronizer1| ; 2 (2) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 2 (2) ; 0 (0) ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1 ; ; +; |altera_std_synchronizer:the_altera_std_synchronizer| ; 2 (2) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 2 (2) ; 0 (0) ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer ; ; +; |system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg| ; 14 (14) ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 8 (8) ; 0 (0) ; 6 (6) ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg ; ; +; |system_cpu_nios2_oci_break:the_system_cpu_nios2_oci_break| ; 32 (32) ; 32 (32) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 32 (32) ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_break:the_system_cpu_nios2_oci_break ; ; +; |system_cpu_nios2_oci_debug:the_system_cpu_nios2_oci_debug| ; 9 (9) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 1 (1) ; 6 (6) ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_debug:the_system_cpu_nios2_oci_debug ; ; +; |system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem| ; 56 (56) ; 44 (44) ; 0 (0) ; 8192 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 12 (12) ; 1 (1) ; 43 (43) ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem ; ; +; |system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component| ; 0 (0) ; 0 (0) ; 0 (0) ; 8192 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component ; ; +; |altsyncram:the_altsyncram| ; 0 (0) ; 0 (0) ; 0 (0) ; 8192 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram ; ; +; |altsyncram_jt72:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 8192 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated ; ; +; |system_cpu_register_bank_a_module:system_cpu_register_bank_a| ; 0 (0) ; 0 (0) ; 0 (0) ; 1024 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_register_bank_a_module:system_cpu_register_bank_a ; ; +; |altsyncram:the_altsyncram| ; 0 (0) ; 0 (0) ; 0 (0) ; 1024 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_register_bank_a_module:system_cpu_register_bank_a|altsyncram:the_altsyncram ; ; +; |altsyncram_fvf1:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 1024 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_register_bank_a_module:system_cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_fvf1:auto_generated ; ; +; |system_cpu_register_bank_b_module:system_cpu_register_bank_b| ; 0 (0) ; 0 (0) ; 0 (0) ; 1024 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_register_bank_b_module:system_cpu_register_bank_b ; ; +; |altsyncram:the_altsyncram| ; 0 (0) ; 0 (0) ; 0 (0) ; 1024 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_register_bank_b_module:system_cpu_register_bank_b|altsyncram:the_altsyncram ; ; +; |altsyncram_gvf1:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 1024 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_register_bank_b_module:system_cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_gvf1:auto_generated ; ; +; |system_cpu_test_bench:the_system_cpu_test_bench| ; 10 (10) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 10 (10) ; 0 (0) ; 0 (0) ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_test_bench:the_system_cpu_test_bench ; ; +; |system_jtag_uart_0:jtag_uart_0| ; 165 (42) ; 104 (13) ; 0 (0) ; 1024 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 53 (21) ; 24 (5) ; 88 (16) ; |de0_nano_system|system:inst_cpu|system_jtag_uart_0:jtag_uart_0 ; ; +; |alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic| ; 72 (72) ; 51 (51) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 21 (21) ; 19 (19) ; 32 (32) ; |de0_nano_system|system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic ; ; +; |system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r| ; 26 (0) ; 20 (0) ; 0 (0) ; 512 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 6 (0) ; 0 (0) ; 20 (0) ; |de0_nano_system|system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r ; ; +; |scfifo:rfifo| ; 26 (0) ; 20 (0) ; 0 (0) ; 512 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 6 (0) ; 0 (0) ; 20 (0) ; |de0_nano_system|system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo ; ; +; |scfifo_jr21:auto_generated| ; 26 (0) ; 20 (0) ; 0 (0) ; 512 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 6 (0) ; 0 (0) ; 20 (0) ; |de0_nano_system|system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated ; ; +; |a_dpfifo_q131:dpfifo| ; 26 (0) ; 20 (0) ; 0 (0) ; 512 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 6 (0) ; 0 (0) ; 20 (0) ; |de0_nano_system|system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo ; ; +; |a_fefifo_7cf:fifo_state| ; 14 (8) ; 8 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 6 (6) ; 0 (0) ; 8 (2) ; |de0_nano_system|system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state ; ; +; |cntr_do7:count_usedw| ; 6 (6) ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 6 (6) ; |de0_nano_system|system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw ; ; +; |cntr_1ob:rd_ptr_count| ; 6 (6) ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 6 (6) ; |de0_nano_system|system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:rd_ptr_count ; ; +; |cntr_1ob:wr_ptr| ; 6 (6) ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 6 (6) ; |de0_nano_system|system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr ; ; +; |dpram_nl21:FIFOram| ; 0 (0) ; 0 (0) ; 0 (0) ; 512 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |de0_nano_system|system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram ; ; +; |altsyncram_r1m1:altsyncram1| ; 0 (0) ; 0 (0) ; 0 (0) ; 512 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |de0_nano_system|system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1 ; ; +; |system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w| ; 25 (0) ; 20 (0) ; 0 (0) ; 512 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 5 (0) ; 0 (0) ; 20 (0) ; |de0_nano_system|system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w ; ; +; |scfifo:wfifo| ; 25 (0) ; 20 (0) ; 0 (0) ; 512 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 5 (0) ; 0 (0) ; 20 (0) ; |de0_nano_system|system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo ; ; +; |scfifo_jr21:auto_generated| ; 25 (0) ; 20 (0) ; 0 (0) ; 512 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 5 (0) ; 0 (0) ; 20 (0) ; |de0_nano_system|system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated ; ; +; |a_dpfifo_q131:dpfifo| ; 25 (0) ; 20 (0) ; 0 (0) ; 512 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 5 (0) ; 0 (0) ; 20 (0) ; |de0_nano_system|system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo ; ; +; |a_fefifo_7cf:fifo_state| ; 13 (7) ; 8 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 5 (5) ; 0 (0) ; 8 (2) ; |de0_nano_system|system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state ; ; +; |cntr_do7:count_usedw| ; 6 (6) ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 6 (6) ; |de0_nano_system|system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw ; ; +; |cntr_1ob:rd_ptr_count| ; 6 (6) ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 6 (6) ; |de0_nano_system|system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:rd_ptr_count ; ; +; |cntr_1ob:wr_ptr| ; 6 (6) ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 6 (6) ; |de0_nano_system|system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr ; ; +; |dpram_nl21:FIFOram| ; 0 (0) ; 0 (0) ; 0 (0) ; 512 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |de0_nano_system|system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram ; ; +; |altsyncram_r1m1:altsyncram1| ; 0 (0) ; 0 (0) ; 0 (0) ; 512 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |de0_nano_system|system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1 ; ; +; |system_pio_key:pio_key| ; 2 (2) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 2 (2) ; |de0_nano_system|system:inst_cpu|system_pio_key:pio_key ; ; +; |system_pio_led:pio_led| ; 24 (24) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 10 (10) ; 0 (0) ; 14 (14) ; |de0_nano_system|system:inst_cpu|system_pio_led:pio_led ; ; +; |system_pio_motor_rst:pio_motor_rst| ; 4 (4) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 2 (2) ; |de0_nano_system|system:inst_cpu|system_pio_motor_rst:pio_motor_rst ; ; +; |system_pio_sw:pio_sw| ; 4 (4) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 4 (4) ; |de0_nano_system|system:inst_cpu|system_pio_sw:pio_sw ; ; +; |system_rs232_motor:rs232_motor| ; 248 (37) ; 176 (33) ; 0 (0) ; 2048 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 72 (4) ; 4 (3) ; 172 (30) ; |de0_nano_system|system:inst_cpu|system_rs232_motor:rs232_motor ; ; +; |altera_up_rs232_in_deserializer:RS232_In_Deserializer| ; 106 (22) ; 71 (18) ; 0 (0) ; 1024 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 35 (4) ; 0 (0) ; 71 (18) ; |de0_nano_system|system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer ; ; +; |altera_up_rs232_counters:RS232_In_Counters| ; 32 (32) ; 20 (20) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 12 (12) ; 0 (0) ; 20 (20) ; |de0_nano_system|system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_rs232_counters:RS232_In_Counters ; ; +; |altera_up_sync_fifo:RS232_In_FIFO| ; 52 (0) ; 33 (0) ; 0 (0) ; 1024 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 19 (0) ; 0 (0) ; 33 (0) ; |de0_nano_system|system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO ; ; +; |scfifo:Sync_FIFO| ; 52 (0) ; 33 (0) ; 0 (0) ; 1024 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 19 (0) ; 0 (0) ; 33 (0) ; |de0_nano_system|system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO ; ; +; |scfifo_a341:auto_generated| ; 52 (0) ; 33 (0) ; 0 (0) ; 1024 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 19 (0) ; 0 (0) ; 33 (0) ; |de0_nano_system|system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated ; ; +; |a_dpfifo_tq31:dpfifo| ; 52 (29) ; 33 (13) ; 0 (0) ; 1024 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 19 (16) ; 0 (0) ; 33 (13) ; |de0_nano_system|system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo ; ; +; |altsyncram_je81:FIFOram| ; 0 (0) ; 0 (0) ; 0 (0) ; 1024 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |de0_nano_system|system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram ; ; +; |cntr_0ab:wr_ptr| ; 8 (8) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 7 (7) ; |de0_nano_system|system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr ; ; +; |cntr_ca7:usedw_counter| ; 8 (8) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 7 (7) ; |de0_nano_system|system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_ca7:usedw_counter ; ; +; |cntr_v9b:rd_ptr_msb| ; 7 (7) ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 6 (6) ; |de0_nano_system|system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_v9b:rd_ptr_msb ; ; +; |altera_up_rs232_out_serializer:RS232_Out_Serializer| ; 105 (23) ; 72 (19) ; 0 (0) ; 1024 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 33 (4) ; 1 (0) ; 71 (19) ; |de0_nano_system|system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer ; ; +; |altera_up_rs232_counters:RS232_Out_Counters| ; 30 (30) ; 20 (20) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 10 (10) ; 0 (0) ; 20 (20) ; |de0_nano_system|system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_rs232_counters:RS232_Out_Counters ; ; +; |altera_up_sync_fifo:RS232_Out_FIFO| ; 52 (0) ; 33 (0) ; 0 (0) ; 1024 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 19 (0) ; 1 (0) ; 32 (0) ; |de0_nano_system|system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO ; ; +; |scfifo:Sync_FIFO| ; 52 (0) ; 33 (0) ; 0 (0) ; 1024 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 19 (0) ; 1 (0) ; 32 (0) ; |de0_nano_system|system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO ; ; +; |scfifo_a341:auto_generated| ; 52 (0) ; 33 (0) ; 0 (0) ; 1024 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 19 (0) ; 1 (0) ; 32 (0) ; |de0_nano_system|system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated ; ; +; |a_dpfifo_tq31:dpfifo| ; 52 (29) ; 33 (13) ; 0 (0) ; 1024 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 19 (16) ; 1 (1) ; 32 (12) ; |de0_nano_system|system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo ; ; +; |altsyncram_je81:FIFOram| ; 0 (0) ; 0 (0) ; 0 (0) ; 1024 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |de0_nano_system|system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram ; ; +; |cntr_0ab:wr_ptr| ; 8 (8) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 7 (7) ; |de0_nano_system|system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr ; ; +; |cntr_ca7:usedw_counter| ; 8 (8) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 7 (7) ; |de0_nano_system|system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_ca7:usedw_counter ; ; +; |cntr_v9b:rd_ptr_msb| ; 7 (7) ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 6 (6) ; |de0_nano_system|system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_v9b:rd_ptr_msb ; ; +; |system_rsp_xbar_demux:rsp_xbar_demux_001| ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; |de0_nano_system|system:inst_cpu|system_rsp_xbar_demux:rsp_xbar_demux_001 ; ; +; |system_rsp_xbar_demux:rsp_xbar_demux| ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; |de0_nano_system|system:inst_cpu|system_rsp_xbar_demux:rsp_xbar_demux ; ; +; |system_rsp_xbar_mux:rsp_xbar_mux| ; 34 (34) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 32 (32) ; |de0_nano_system|system:inst_cpu|system_rsp_xbar_mux:rsp_xbar_mux ; ; +; |system_rsp_xbar_mux_001:rsp_xbar_mux_001| ; 121 (121) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 55 (55) ; 0 (0) ; 66 (66) ; |de0_nano_system|system:inst_cpu|system_rsp_xbar_mux_001:rsp_xbar_mux_001 ; ; +; |system_sdram:sdram| ; 350 (235) ; 210 (122) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 140 (114) ; 57 (13) ; 153 (108) ; |de0_nano_system|system:inst_cpu|system_sdram:sdram ; ; +; |system_sdram_input_efifo_module:the_system_sdram_input_efifo_module| ; 117 (117) ; 88 (88) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 26 (26) ; 44 (44) ; 47 (47) ; |de0_nano_system|system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module ; ; +; |system_sys_clk_timer:sys_clk_timer| ; 148 (148) ; 120 (120) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 28 (28) ; 22 (22) ; 98 (98) ; |de0_nano_system|system:inst_cpu|system_sys_clk_timer:sys_clk_timer ; ; +; |system_uart_0:uart_0| ; 186 (0) ; 128 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 58 (0) ; 25 (0) ; 103 (0) ; |de0_nano_system|system:inst_cpu|system_uart_0:uart_0 ; ; +; |system_uart_0_regs:the_system_uart_0_regs| ; 74 (74) ; 51 (51) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 15 (15) ; 21 (21) ; 38 (38) ; |de0_nano_system|system:inst_cpu|system_uart_0:uart_0|system_uart_0_regs:the_system_uart_0_regs ; ; +; |system_uart_0_rx:the_system_uart_0_rx| ; 73 (71) ; 44 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 29 (29) ; 3 (1) ; 41 (41) ; |de0_nano_system|system:inst_cpu|system_uart_0:uart_0|system_uart_0_rx:the_system_uart_0_rx ; ; +; |altera_std_synchronizer:the_altera_std_synchronizer| ; 2 (2) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 2 (2) ; 0 (0) ; |de0_nano_system|system:inst_cpu|system_uart_0:uart_0|system_uart_0_rx:the_system_uart_0_rx|altera_std_synchronizer:the_altera_std_synchronizer ; ; +; |system_uart_0_tx:the_system_uart_0_tx| ; 47 (47) ; 33 (33) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 14 (14) ; 1 (1) ; 32 (32) ; |de0_nano_system|system:inst_cpu|system_uart_0:uart_0|system_uart_0_tx:the_system_uart_0_tx ; ; ++-----------------------------------------------------------------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++--------------------------------------------------------------------------------------------------------+ +; Delay Chain Summary ; ++---------------+----------+---------------+---------------+-----------------------+----------+----------+ +; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ; ++---------------+----------+---------------+---------------+-----------------------+----------+----------+ +; DRAM_CLK ; Output ; -- ; -- ; -- ; -- ; -- ; +; DRAM_CKE ; Output ; -- ; -- ; -- ; -- ; -- ; +; DRAM_CS_N ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; DRAM_RAS_N ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; DRAM_CAS_N ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; DRAM_WE_N ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; DRAM_DQM[0] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; DRAM_DQM[1] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; DRAM_ADDR[0] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; DRAM_ADDR[1] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; DRAM_ADDR[2] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; DRAM_ADDR[3] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; DRAM_ADDR[4] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; DRAM_ADDR[5] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; DRAM_ADDR[6] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; DRAM_ADDR[7] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; DRAM_ADDR[8] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; DRAM_ADDR[9] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; DRAM_ADDR[10] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; DRAM_ADDR[11] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; DRAM_ADDR[12] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; DRAM_BA[0] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; DRAM_BA[1] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; LED[0] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LED[1] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LED[2] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LED[3] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LED[4] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LED[5] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LED[6] ; Output ; -- ; -- ; -- ; -- ; -- ; +; LED[7] ; Output ; -- ; -- ; -- ; -- ; -- ; +; GPIO_0[2] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; GPIO_0[3] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; GPIO_0[4] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; GPIO_0[5] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; GPIO_0[6] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; GPIO_0[7] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; GPIO_0[8] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; GPIO_0[9] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; GPIO_0[10] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; GPIO_0[11] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; GPIO_0[12] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; GPIO_0[13] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; GPIO_0[14] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; GPIO_0[15] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; GPIO_0[16] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; GPIO_0[17] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; GPIO_0[18] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; GPIO_0[19] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; GPIO_0[20] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; GPIO_0[21] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; GPIO_0[22] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; GPIO_0[23] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; GPIO_0[24] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; GPIO_0[25] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; GPIO_0[26] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; GPIO_0[27] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; GPIO_0[28] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; GPIO_0[29] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; GPIO_0[30] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; GPIO_0[31] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; GPIO_0[32] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; GPIO_0[33] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; GPIO_1[0] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; GPIO_1[1] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; GPIO_1[2] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; GPIO_1[3] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; GPIO_1[4] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; GPIO_1[5] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; GPIO_1[6] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; GPIO_1[7] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; GPIO_1[8] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; GPIO_1[9] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; GPIO_1[10] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; GPIO_1[11] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; GPIO_1[13] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; GPIO_1[14] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; GPIO_1[15] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; GPIO_1[16] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; GPIO_1[17] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; GPIO_1[18] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; GPIO_1[19] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; GPIO_1[20] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; GPIO_1[21] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; GPIO_1[22] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; GPIO_1[23] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; GPIO_1[25] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; GPIO_1[27] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; GPIO_1[28] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; GPIO_1[29] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; GPIO_1[30] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; GPIO_1[31] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; GPIO_1[32] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; GPIO_1[33] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; DRAM_DQ[0] ; Bidir ; -- ; -- ; (0) 0 ps ; (0) 0 ps ; (0) 0 ps ; +; DRAM_DQ[1] ; Bidir ; -- ; -- ; (0) 0 ps ; (0) 0 ps ; (0) 0 ps ; +; DRAM_DQ[2] ; Bidir ; -- ; -- ; (0) 0 ps ; (0) 0 ps ; (0) 0 ps ; +; DRAM_DQ[3] ; Bidir ; -- ; -- ; (0) 0 ps ; (0) 0 ps ; (0) 0 ps ; +; DRAM_DQ[4] ; Bidir ; -- ; -- ; (0) 0 ps ; (0) 0 ps ; (0) 0 ps ; +; DRAM_DQ[5] ; Bidir ; -- ; -- ; (0) 0 ps ; (0) 0 ps ; (0) 0 ps ; +; DRAM_DQ[6] ; Bidir ; -- ; -- ; (0) 0 ps ; (0) 0 ps ; (0) 0 ps ; +; DRAM_DQ[7] ; Bidir ; -- ; -- ; (0) 0 ps ; (0) 0 ps ; (0) 0 ps ; +; DRAM_DQ[8] ; Bidir ; -- ; -- ; (0) 0 ps ; (0) 0 ps ; (0) 0 ps ; +; DRAM_DQ[9] ; Bidir ; -- ; -- ; (0) 0 ps ; (0) 0 ps ; (0) 0 ps ; +; DRAM_DQ[10] ; Bidir ; -- ; -- ; (0) 0 ps ; (0) 0 ps ; (0) 0 ps ; +; DRAM_DQ[11] ; Bidir ; -- ; -- ; (0) 0 ps ; (0) 0 ps ; (0) 0 ps ; +; DRAM_DQ[12] ; Bidir ; -- ; -- ; (0) 0 ps ; (0) 0 ps ; (0) 0 ps ; +; DRAM_DQ[13] ; Bidir ; -- ; -- ; (0) 0 ps ; (0) 0 ps ; (0) 0 ps ; +; DRAM_DQ[14] ; Bidir ; -- ; -- ; (0) 0 ps ; (0) 0 ps ; (0) 0 ps ; +; DRAM_DQ[15] ; Bidir ; -- ; -- ; (0) 0 ps ; (0) 0 ps ; (0) 0 ps ; +; GPIO_0[0] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; GPIO_0[1] ; Bidir ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; GPIO_1[12] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; GPIO_1[24] ; Bidir ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; GPIO_1[26] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; CLOCK_50 ; Input ; -- ; -- ; -- ; -- ; -- ; +; SW[3] ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; +; SW[2] ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; +; SW[1] ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; +; KEY[1] ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; +; KEY[0] ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; SW[0] ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; ++---------------+----------+---------------+---------------+-----------------------+----------+----------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Pad To Core Delay Chain Fanout ; ++-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+---------+ +; Source Pin / Fanout ; Pad To Core Index ; Setting ; ++-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+---------+ +; GPIO_0[2] ; ; ; +; GPIO_0[3] ; ; ; +; GPIO_0[4] ; ; ; +; GPIO_0[5] ; ; ; +; GPIO_0[6] ; ; ; +; GPIO_0[7] ; ; ; +; GPIO_0[8] ; ; ; +; GPIO_0[9] ; ; ; +; GPIO_0[10] ; ; ; +; GPIO_0[11] ; ; ; +; GPIO_0[12] ; ; ; +; GPIO_0[13] ; ; ; +; GPIO_0[14] ; ; ; +; GPIO_0[15] ; ; ; +; GPIO_0[16] ; ; ; +; GPIO_0[17] ; ; ; +; GPIO_0[18] ; ; ; +; GPIO_0[19] ; ; ; +; GPIO_0[20] ; ; ; +; GPIO_0[21] ; ; ; +; GPIO_0[22] ; ; ; +; GPIO_0[23] ; ; ; +; GPIO_0[24] ; ; ; +; GPIO_0[25] ; ; ; +; GPIO_0[26] ; ; ; +; GPIO_0[27] ; ; ; +; GPIO_0[28] ; ; ; +; GPIO_0[29] ; ; ; +; GPIO_0[30] ; ; ; +; GPIO_0[31] ; ; ; +; GPIO_0[32] ; ; ; +; GPIO_0[33] ; ; ; +; GPIO_1[0] ; ; ; +; GPIO_1[1] ; ; ; +; GPIO_1[2] ; ; ; +; GPIO_1[3] ; ; ; +; GPIO_1[4] ; ; ; +; GPIO_1[5] ; ; ; +; GPIO_1[6] ; ; ; +; GPIO_1[7] ; ; ; +; GPIO_1[8] ; ; ; +; GPIO_1[9] ; ; ; +; GPIO_1[10] ; ; ; +; GPIO_1[11] ; ; ; +; GPIO_1[13] ; ; ; +; GPIO_1[14] ; ; ; +; GPIO_1[15] ; ; ; +; GPIO_1[16] ; ; ; +; GPIO_1[17] ; ; ; +; GPIO_1[18] ; ; ; +; GPIO_1[19] ; ; ; +; GPIO_1[20] ; ; ; +; GPIO_1[21] ; ; ; +; GPIO_1[22] ; ; ; +; GPIO_1[23] ; ; ; +; GPIO_1[25] ; ; ; +; GPIO_1[27] ; ; ; +; GPIO_1[28] ; ; ; +; GPIO_1[29] ; ; ; +; GPIO_1[30] ; ; ; +; GPIO_1[31] ; ; ; +; GPIO_1[32] ; ; ; +; GPIO_1[33] ; ; ; +; DRAM_DQ[0] ; ; ; +; DRAM_DQ[1] ; ; ; +; DRAM_DQ[2] ; ; ; +; DRAM_DQ[3] ; ; ; +; DRAM_DQ[4] ; ; ; +; DRAM_DQ[5] ; ; ; +; DRAM_DQ[6] ; ; ; +; DRAM_DQ[7] ; ; ; +; DRAM_DQ[8] ; ; ; +; DRAM_DQ[9] ; ; ; +; DRAM_DQ[10] ; ; ; +; DRAM_DQ[11] ; ; ; +; DRAM_DQ[12] ; ; ; +; DRAM_DQ[13] ; ; ; +; DRAM_DQ[14] ; ; ; +; DRAM_DQ[15] ; ; ; +; GPIO_0[0] ; ; ; +; GPIO_0[1] ; ; ; +; - system:inst_cpu|system_uart_0:uart_0|system_uart_0_rx:the_system_uart_0_rx|altera_std_synchronizer:the_altera_std_synchronizer|din_s1~feeder ; 0 ; 6 ; +; GPIO_1[12] ; ; ; +; GPIO_1[24] ; ; ; +; - system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|data_in_shift_reg~9 ; 0 ; 6 ; +; - system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|receiving_data~0 ; 0 ; 6 ; +; GPIO_1[26] ; ; ; +; CLOCK_50 ; ; ; +; SW[3] ; ; ; +; SW[2] ; ; ; +; SW[1] ; ; ; +; KEY[1] ; ; ; +; KEY[0] ; ; ; +; - system:inst_cpu|system_pio_key:pio_key|read_mux_out[0] ; 0 ; 6 ; +; SW[0] ; ; ; ++-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+---------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Control Signals ; ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------+---------+----------------------------------------------------+--------+----------------------+------------------+---------------------------+ +; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------+---------+----------------------------------------------------+--------+----------------------+------------------+---------------------------+ +; CLOCK_50 ; PIN_R8 ; 1 ; Clock ; no ; -- ; -- ; -- ; +; altera_internal_jtag~TCKUTAP ; JTAG_X1_Y17_N0 ; 183 ; Clock ; yes ; Global Clock ; GCLK1 ; -- ; +; altera_internal_jtag~TMSUTAP ; JTAG_X1_Y17_N0 ; 21 ; Sync. clear ; no ; -- ; -- ; -- ; +; pll_sys:inst_pll_sys|altpll:altpll_component|pll_sys_altpll:auto_generated|wire_pll1_clk[0] ; PLL_4 ; 2682 ; Clock ; yes ; Global Clock ; GCLK18 ; -- ; +; pll_sys:inst_pll_sys|altpll:altpll_component|pll_sys_altpll:auto_generated|wire_pll1_clk[2] ; PLL_4 ; 22 ; Clock ; yes ; Global Clock ; GCLK19 ; -- ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; FF_X14_Y19_N1 ; 70 ; Async. clear ; yes ; Global Clock ; GCLK3 ; -- ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_proc~0 ; LCCOMB_X14_Y19_N16 ; 4 ; Sync. load ; no ; -- ; -- ; -- ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_info_reg_ena ; LCCOMB_X15_Y21_N26 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_info_reg_ena~0 ; LCCOMB_X16_Y17_N12 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[0]~2 ; LCCOMB_X15_Y19_N26 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[0]~0 ; LCCOMB_X15_Y19_N12 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]~5 ; LCCOMB_X15_Y18_N28 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]~12 ; LCCOMB_X15_Y18_N8 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2]~3 ; LCCOMB_X16_Y19_N4 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[0]~11 ; LCCOMB_X14_Y21_N2 ; 5 ; Sync. load ; no ; -- ; -- ; -- ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[0]~12 ; LCCOMB_X14_Y19_N14 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena~3 ; LCCOMB_X15_Y20_N24 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][0]~2 ; LCCOMB_X15_Y17_N0 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][0]~9 ; LCCOMB_X15_Y18_N0 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[0]~15 ; LCCOMB_X14_Y19_N26 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[4]~22 ; LCCOMB_X12_Y21_N6 ; 5 ; Sync. clear ; no ; -- ; -- ; -- ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[4]~23 ; LCCOMB_X14_Y21_N10 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; FF_X15_Y20_N3 ; 12 ; Async. clear ; yes ; Global Clock ; GCLK2 ; -- ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[11] ; FF_X15_Y20_N23 ; 12 ; Clock enable ; no ; -- ; -- ; -- ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; FF_X15_Y20_N11 ; 39 ; Sync. load ; no ; -- ; -- ; -- ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; FF_X14_Y19_N25 ; 46 ; Sync. clear ; no ; -- ; -- ; -- ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; FF_X14_Y19_N11 ; 10 ; Async. clear ; no ; -- ; -- ; -- ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_dr_scan_proc~0 ; LCCOMB_X15_Y20_N4 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; FF_X14_Y18_N29 ; 26 ; Async. clear ; no ; -- ; -- ; -- ; +; system:inst_cpu|altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]~3 ; LCCOMB_X21_Y9_N14 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|always0~0 ; LCCOMB_X19_Y10_N10 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|always1~0 ; LCCOMB_X19_Y10_N30 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|always2~0 ; LCCOMB_X19_Y10_N4 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|always3~0 ; LCCOMB_X19_Y10_N18 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|always4~0 ; LCCOMB_X19_Y10_N28 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|always5~0 ; LCCOMB_X18_Y10_N6 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|always6~0 ; LCCOMB_X18_Y10_N18 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[6]~5 ; LCCOMB_X18_Y10_N22 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent|comb~0 ; LCCOMB_X19_Y10_N22 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent|rp_valid ; LCCOMB_X19_Y10_N14 ; 20 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|altera_merlin_slave_translator:cpu_jtag_debug_module_translator|waitrequest_reset_override ; FF_X21_Y15_N17 ; 25 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|altera_merlin_traffic_limiter:limiter_001|pending_response_count[3]~3 ; LCCOMB_X23_Y12_N28 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|altera_merlin_traffic_limiter:limiter_001|save_dest_id~2 ; LCCOMB_X24_Y12_N0 ; 15 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|altera_merlin_traffic_limiter:limiter|pending_response_count[3]~8 ; LCCOMB_X25_Y9_N6 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|altera_merlin_traffic_limiter:limiter|save_dest_id~0 ; LCCOMB_X25_Y9_N16 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|altera_merlin_width_adapter:width_adapter|byteen_reg[0]~0 ; LCCOMB_X18_Y9_N10 ; 40 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|altera_merlin_width_adapter:width_adapter|use_reg ; FF_X18_Y9_N5 ; 75 ; Clock enable, Sync. clear, Sync. load ; no ; -- ; -- ; -- ; +; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; FF_X24_Y33_N17 ; 161 ; Clock enable, Sync. clear, Sync. load ; no ; -- ; -- ; -- ; +; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; FF_X24_Y33_N17 ; 2218 ; Async. clear, Async. load ; yes ; Global Clock ; GCLK14 ; -- ; +; system:inst_cpu|altera_reset_controller:rst_controller|merged_reset~0 ; LCCOMB_X52_Y17_N20 ; 3 ; Async. clear ; yes ; Global Clock ; GCLK8 ; -- ; +; system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux_001|altera_merlin_arbitrator:arb|top_priority_reg[0]~0 ; LCCOMB_X17_Y11_N4 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux_001|update_grant~0 ; LCCOMB_X19_Y9_N26 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux|altera_merlin_arbitrator:arb|top_priority_reg[0]~3 ; LCCOMB_X25_Y10_N24 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux|src_data[46] ; LCCOMB_X25_Y10_N28 ; 35 ; Sync. load ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux|update_grant~1 ; LCCOMB_X25_Y10_N26 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|A_dc_rd_addr_cnt[1]~2 ; LCCOMB_X25_Y12_N14 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|A_dc_rd_data_cnt[2]~0 ; LCCOMB_X25_Y12_N20 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|A_dc_rd_data_cnt[2]~1 ; LCCOMB_X25_Y12_N22 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|A_dc_wb_en ; LCCOMB_X24_Y12_N14 ; 4 ; Clock enable, Read enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|A_dc_wb_update_av_writedata ; LCCOMB_X24_Y12_N8 ; 32 ; Sync. load ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|A_dc_wb_wr_want_dmaster ; LCCOMB_X27_Y12_N6 ; 21 ; Sync. load ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|A_dc_wr_data_cnt[2]~0 ; LCCOMB_X27_Y12_N0 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|A_dc_xfer_rd_data_starting ; FF_X27_Y16_N7 ; 22 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|A_dc_xfer_wr_active ; FF_X28_Y13_N31 ; 1 ; Write enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|A_ienable_reg_irq1~0 ; LCCOMB_X28_Y11_N10 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|A_ld_align_byte1_fill ; FF_X31_Y18_N7 ; 9 ; Sync. load ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|A_ld_align_sh8 ; FF_X30_Y18_N5 ; 10 ; Sync. load ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|A_mul_stall_d3 ; FF_X40_Y19_N13 ; 32 ; Sync. load ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|A_slow_inst_result_en~0 ; LCCOMB_X28_Y15_N22 ; 32 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|A_stall~0 ; LCCOMB_X28_Y13_N30 ; 741 ; Clock enable, Sync. clear ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|A_wr_dst_reg_from_M ; FF_X32_Y12_N3 ; 4 ; Write enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|Add8~5 ; LCCOMB_X36_Y18_N10 ; 32 ; Sync. load ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|D_ctrl_src2_choose_imm ; FF_X30_Y12_N23 ; 33 ; Sync. load ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|D_ic_fill_starting~1 ; LCCOMB_X30_Y9_N28 ; 26 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|E_hbreak_req ; LCCOMB_X30_Y11_N0 ; 30 ; Sync. load ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|E_iw[0] ; FF_X29_Y14_N11 ; 18 ; Sync. clear ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|E_iw[4] ; FF_X28_Y17_N29 ; 34 ; Sync. load ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|F_stall ; LCCOMB_X38_Y12_N4 ; 175 ; Clock enable, Read enable, Sync. clear, Sync. load ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|M_bht_wr_en_unfiltered ; LCCOMB_X32_Y14_N20 ; 1 ; Write enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|M_br_cond_taken_history[0]~0 ; LCCOMB_X32_Y14_N24 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|M_ctrl_rdctl_inst ; FF_X30_Y11_N9 ; 32 ; Sync. clear, Sync. load ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|M_pipe_flush ; FF_X32_Y14_N11 ; 51 ; Sync. load ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|M_rot_rn[3] ; FF_X36_Y18_N15 ; 32 ; Sync. load ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|always138~0 ; LCCOMB_X28_Y13_N8 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|d_address_offset_field[0]~1 ; LCCOMB_X25_Y13_N22 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|d_writedata[15]~34 ; LCCOMB_X24_Y12_N30 ; 32 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|dc_data_wr_port_en ; LCCOMB_X27_Y13_N6 ; 4 ; Clock enable, Write enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|dc_tag_wr_port_en ; LCCOMB_X26_Y13_N18 ; 1 ; Write enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|i_readdatavalid_d1 ; FF_X24_Y10_N31 ; 11 ; Clock enable, Write enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|ic_fill_ap_offset[2]~0 ; LCCOMB_X26_Y9_N20 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|ic_fill_dp_offset_en~0 ; LCCOMB_X28_Y9_N12 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|ic_fill_valid_bits_en ; LCCOMB_X28_Y9_N6 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|ic_tag_clr_valid_bits_nxt~2 ; LCCOMB_X30_Y9_N26 ; 9 ; Sync. load ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|ic_tag_wraddress[6]~6 ; LCCOMB_X29_Y10_N4 ; 8 ; Sync. clear ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|ic_tag_wren ; LCCOMB_X30_Y9_N12 ; 1 ; Write enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a0~0 ; LCCOMB_X34_Y9_N6 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy|virtual_state_sdr~0 ; LCCOMB_X17_Y18_N22 ; 39 ; Sync. load ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy|virtual_state_uir~0 ; LCCOMB_X17_Y18_N10 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|jxuir ; FF_X17_Y18_N31 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|take_action_ocimem_a ; LCCOMB_X20_Y20_N10 ; 15 ; Clock enable, Sync. load ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|take_action_ocimem_a~0 ; LCCOMB_X17_Y17_N30 ; 15 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|take_action_ocimem_b ; LCCOMB_X18_Y17_N6 ; 34 ; Sync. load ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|take_no_action_break_a~0 ; LCCOMB_X17_Y17_N0 ; 64 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|update_jdo_strobe ; FF_X17_Y18_N9 ; 39 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[16]~21 ; LCCOMB_X17_Y21_N20 ; 18 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[36]~28 ; LCCOMB_X17_Y18_N12 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[8]~13 ; LCCOMB_X17_Y18_N4 ; 13 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg|take_action_oci_intr_mask_reg~0 ; LCCOMB_X24_Y16_N16 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[0]~13 ; LCCOMB_X21_Y15_N4 ; 30 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[24]~22 ; LCCOMB_X19_Y19_N4 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonWr ; FF_X21_Y15_N1 ; 3 ; Write enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|comb~1 ; LCCOMB_X23_Y16_N24 ; 2 ; Write enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|r_ena~0 ; LCCOMB_X21_Y20_N4 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|td_shift[0]~4 ; LCCOMB_X16_Y21_N30 ; 21 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|write_stalled~1 ; LCCOMB_X16_Y22_N12 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|write~0 ; LCCOMB_X16_Y21_N10 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|fifo_rd~1 ; LCCOMB_X21_Y17_N10 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|fifo_wr ; FF_X20_Y15_N1 ; 15 ; Clock enable, Write enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|ien_AE~0 ; LCCOMB_X19_Y15_N4 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|r_val~0 ; LCCOMB_X21_Y20_N10 ; 11 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|read_0 ; FF_X19_Y15_N19 ; 16 ; Sync. load ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|_~4 ; LCCOMB_X23_Y18_N14 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|_~0 ; LCCOMB_X24_Y21_N16 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|wr_rfifo ; LCCOMB_X21_Y17_N22 ; 13 ; Clock enable, Write enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_pio_led:pio_led|data_out[0]~2 ; LCCOMB_X23_Y10_N0 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_rs232_counters:RS232_In_Counters|baud_counter[4]~22 ; LCCOMB_X24_Y19_N0 ; 14 ; Sync. clear ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|_~0 ; LCCOMB_X25_Y19_N24 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_ca7:usedw_counter|_~2 ; LCCOMB_X24_Y20_N30 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_v9b:rd_ptr_msb|_~0 ; LCCOMB_X23_Y21_N28 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|rd_ptr_lsb~1 ; LCCOMB_X25_Y18_N24 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|comb~0 ; LCCOMB_X23_Y20_N24 ; 13 ; Clock enable, Write enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|data_in_shift_reg[1]~1 ; LCCOMB_X23_Y22_N18 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_rs232_counters:RS232_Out_Counters|baud_counter[7]~16 ; LCCOMB_X28_Y22_N8 ; 14 ; Sync. clear ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|_~0 ; LCCOMB_X25_Y21_N6 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_ca7:usedw_counter|_~2 ; LCCOMB_X26_Y21_N28 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_v9b:rd_ptr_msb|_~0 ; LCCOMB_X29_Y22_N14 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|comb~0 ; LCCOMB_X26_Y21_N8 ; 12 ; Clock enable, Write enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|data_out_shift_reg[5]~2 ; LCCOMB_X32_Y21_N22 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|data_out_shift_reg[5]~4 ; LCCOMB_X29_Y22_N4 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_rs232_motor:rs232_motor|read_interrupt_en~0 ; LCCOMB_X26_Y20_N2 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_rs232_motor:rs232_motor|readdata[22]~1 ; LCCOMB_X25_Y18_N30 ; 19 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_sdram:sdram|Selector27~6 ; LCCOMB_X9_Y7_N6 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_sdram:sdram|Selector34~3 ; LCCOMB_X9_Y7_N2 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_sdram:sdram|WideOr16~0 ; LCCOMB_X11_Y7_N16 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_sdram:sdram|active_rnw~3 ; LCCOMB_X11_Y7_N14 ; 42 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_sdram:sdram|m_addr[7]~1 ; LCCOMB_X7_Y7_N16 ; 13 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_sdram:sdram|m_state.000000010 ; FF_X11_Y7_N1 ; 33 ; Sync. clear ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_sdram:sdram|m_state.000010000 ; FF_X10_Y7_N27 ; 43 ; Sync. load ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_sdram:sdram|m_state.001000000 ; FF_X7_Y7_N21 ; 20 ; Sync. load ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_sdram:sdram|oe ; DDIOOECELL_X0_Y23_N19 ; 1 ; Output enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_1 ; DDIOOECELL_X0_Y23_N26 ; 1 ; Output enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_10 ; DDIOOECELL_X1_Y0_N5 ; 1 ; Output enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_11 ; DDIOOECELL_X1_Y0_N12 ; 1 ; Output enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_12 ; DDIOOECELL_X14_Y0_N26 ; 1 ; Output enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_13 ; DDIOOECELL_X1_Y0_N19 ; 1 ; Output enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_14 ; DDIOOECELL_X1_Y0_N26 ; 1 ; Output enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_15 ; DDIOOECELL_X0_Y12_N12 ; 1 ; Output enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_2 ; DDIOOECELL_X18_Y0_N12 ; 1 ; Output enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_3 ; DDIOOECELL_X0_Y7_N12 ; 1 ; Output enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_4 ; DDIOOECELL_X0_Y12_N5 ; 1 ; Output enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_5 ; DDIOOECELL_X0_Y15_N5 ; 1 ; Output enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_6 ; DDIOOECELL_X0_Y15_N12 ; 1 ; Output enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_7 ; DDIOOECELL_X16_Y0_N19 ; 1 ; Output enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_8 ; DDIOOECELL_X5_Y0_N19 ; 1 ; Output enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_9 ; DDIOOECELL_X3_Y0_N5 ; 1 ; Output enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[41]~0 ; LCCOMB_X19_Y9_N30 ; 42 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_1[41]~0 ; LCCOMB_X19_Y9_N16 ; 42 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_sys_clk_timer:sys_clk_timer|always0~0 ; LCCOMB_X15_Y14_N2 ; 32 ; Sync. load ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_sys_clk_timer:sys_clk_timer|always0~1 ; LCCOMB_X15_Y14_N18 ; 32 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_sys_clk_timer:sys_clk_timer|control_wr_strobe ; LCCOMB_X15_Y14_N20 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_sys_clk_timer:sys_clk_timer|period_h_wr_strobe ; LCCOMB_X15_Y14_N26 ; 16 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_sys_clk_timer:sys_clk_timer|period_l_wr_strobe ; LCCOMB_X19_Y12_N22 ; 16 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_sys_clk_timer:sys_clk_timer|snap_strobe~0 ; LCCOMB_X16_Y16_N14 ; 32 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_uart_0:uart_0|system_uart_0_regs:the_system_uart_0_regs|control_wr_strobe ; LCCOMB_X18_Y12_N8 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_uart_0:uart_0|system_uart_0_regs:the_system_uart_0_regs|divisor_wr_strobe ; LCCOMB_X17_Y12_N6 ; 16 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_uart_0:uart_0|system_uart_0_rx:the_system_uart_0_rx|baud_clk_en~2 ; LCCOMB_X11_Y15_N24 ; 16 ; Sync. load ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_uart_0:uart_0|system_uart_0_rx:the_system_uart_0_rx|got_new_char ; LCCOMB_X15_Y16_N8 ; 11 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_uart_0:uart_0|system_uart_0_rx:the_system_uart_0_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[0]~0 ; LCCOMB_X11_Y15_N20 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_uart_0:uart_0|system_uart_0_tx:the_system_uart_0_tx|always4~0 ; LCCOMB_X17_Y14_N12 ; 16 ; Sync. load ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_uart_0:uart_0|system_uart_0_tx:the_system_uart_0_tx|tx_wr_strobe_onset~0 ; LCCOMB_X18_Y12_N20 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_uart_0:uart_0|system_uart_0_tx:the_system_uart_0_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_in[2]~1 ; LCCOMB_X17_Y14_N10 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------+---------+----------------------------------------------------+--------+----------------------+------------------+---------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Global & Other Fast Signals ; ++-------------------------------------------------------------------------------------------------------------------------------------------+--------------------+---------+--------------------------------------+----------------------+------------------+---------------------------+ +; Name ; Location ; Fan-Out ; Fan-Out Using Intentional Clock Skew ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; ++-------------------------------------------------------------------------------------------------------------------------------------------+--------------------+---------+--------------------------------------+----------------------+------------------+---------------------------+ +; altera_internal_jtag~TCKUTAP ; JTAG_X1_Y17_N0 ; 183 ; 0 ; Global Clock ; GCLK1 ; -- ; +; pll_sys:inst_pll_sys|altpll:altpll_component|pll_sys_altpll:auto_generated|wire_pll1_clk[0] ; PLL_4 ; 2682 ; 18 ; Global Clock ; GCLK18 ; -- ; +; pll_sys:inst_pll_sys|altpll:altpll_component|pll_sys_altpll:auto_generated|wire_pll1_clk[1] ; PLL_4 ; 1 ; 0 ; Global Clock ; GCLK17 ; -- ; +; pll_sys:inst_pll_sys|altpll:altpll_component|pll_sys_altpll:auto_generated|wire_pll1_clk[2] ; PLL_4 ; 22 ; 0 ; Global Clock ; GCLK19 ; -- ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; FF_X14_Y19_N1 ; 70 ; 0 ; Global Clock ; GCLK3 ; -- ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; FF_X15_Y20_N3 ; 12 ; 0 ; Global Clock ; GCLK2 ; -- ; +; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; FF_X24_Y33_N17 ; 2218 ; 0 ; Global Clock ; GCLK14 ; -- ; +; system:inst_cpu|altera_reset_controller:rst_controller|merged_reset~0 ; LCCOMB_X52_Y17_N20 ; 3 ; 0 ; Global Clock ; GCLK8 ; -- ; ++-------------------------------------------------------------------------------------------------------------------------------------------+--------------------+---------+--------------------------------------+----------------------+------------------+---------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Non-Global High Fan-Out Signals ; ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+ +; Name ; Fan-Out ; ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+ +; system:inst_cpu|system_cpu:cpu|A_stall~0 ; 741 ; +; system:inst_cpu|system_cpu:cpu|F_stall ; 176 ; +; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; 160 ; +; system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux_001|saved_grant[1] ; 80 ; +; system:inst_cpu|altera_merlin_width_adapter:width_adapter|use_reg ; 75 ; +; system:inst_cpu|system_cpu:cpu|A_mul_stall ; 73 ; +; system:inst_cpu|system_cpu:cpu|d_address_offset_field[0] ; 72 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|take_no_action_break_a~0 ; 64 ; +; system:inst_cpu|system_cpu:cpu|A_dc_fill_active ; 55 ; +; system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux|saved_grant[1] ; 55 ; +; system:inst_cpu|system_cpu:cpu|d_address_offset_field[2] ; 55 ; +; system:inst_cpu|system_cpu:cpu|d_address_offset_field[1] ; 52 ; +; system:inst_cpu|system_cpu:cpu|M_pipe_flush ; 51 ; +; ~GND ; 49 ; +; system:inst_cpu|system_cpu:cpu|E_src1[4]~1 ; 48 ; +; system:inst_cpu|system_cpu:cpu|E_src1[4]~0 ; 48 ; +; system:inst_cpu|system_cpu:cpu|D_src2_reg[8]~21 ; 48 ; +; system:inst_cpu|system_cpu:cpu|D_src2_reg[8]~20 ; 48 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; 46 ; +; system:inst_cpu|system_cpu:cpu|d_write ; 46 ; +; system:inst_cpu|system_cpu:cpu|F_iw[2]~7 ; 43 ; +; system:inst_cpu|system_sdram:sdram|m_state.000010000 ; 43 ; +; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|rd_address ; 43 ; +; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[41]~0 ; 42 ; +; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_1[41]~0 ; 42 ; +; system:inst_cpu|system_sdram:sdram|active_rnw~3 ; 42 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1] ; 41 ; +; system:inst_cpu|system_cpu:cpu|A_en_d1 ; 41 ; +; system:inst_cpu|system_cpu:cpu|A_dc_valid_st_bypass_hit ; 41 ; +; system:inst_cpu|system_cpu:cpu|A_ctrl_mul_lsw ; 40 ; +; system:inst_cpu|altera_merlin_width_adapter:width_adapter|byteen_reg[0]~0 ; 40 ; +; system:inst_cpu|system_cpu:cpu|A_mem_bypass_pending ; 40 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; 39 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|update_jdo_strobe ; 39 ; +; system:inst_cpu|system_cpu:cpu|E_ctrl_logic ; 39 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy|virtual_state_sdr~0 ; 39 ; +; system:inst_cpu|system_cpu:cpu|F_pc[15]~0 ; 38 ; +; system:inst_cpu|system_cpu:cpu|E_alu_result~0 ; 38 ; +; system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|source_addr[1]~0 ; 38 ; +; system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux_001|saved_grant[0] ; 38 ; +; system:inst_cpu|system_cpu:cpu|D_src2_hazard_E ; 37 ; +; system:inst_cpu|system_cpu:cpu|D_ctrl_a_not_src ; 37 ; +; system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux|src_data[46] ; 35 ; +; system:inst_cpu|system_cpu:cpu|F_pc[15]~1 ; 34 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|take_action_ocimem_b ; 34 ; +; system:inst_cpu|system_cpu:cpu|E_iw[4] ; 34 ; +; system:inst_cpu|system_cpu:cpu|E_ctrl_alu_subtract ; 34 ; +; system:inst_cpu|system_cpu:cpu|E_regnum_a_cmp_D ; 34 ; +; system:inst_cpu|system_cpu:cpu|D_ctrl_src2_choose_imm ; 33 ; +; system:inst_cpu|system_rsp_xbar_demux:rsp_xbar_demux|src0_valid ; 33 ; +; system:inst_cpu|system_sdram:sdram|m_state.000000010 ; 33 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonAReg[10] ; 33 ; +; system:inst_cpu|system_sys_clk_timer:sys_clk_timer|snap_strobe~0 ; 32 ; +; system:inst_cpu|system_sys_clk_timer:sys_clk_timer|always0~1 ; 32 ; +; system:inst_cpu|system_sys_clk_timer:sys_clk_timer|always0~0 ; 32 ; +; system:inst_cpu|system_cpu:cpu|M_rot_rn[3] ; 32 ; +; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; 32 ; +; system:inst_cpu|system_cpu:cpu|M_rot_rn[4] ; 32 ; +; system:inst_cpu|system_cpu:cpu|A_mul_stall_d3 ; 32 ; +; system:inst_cpu|system_cpu:cpu|A_slow_inst_result_en~0 ; 32 ; +; system:inst_cpu|system_cpu:cpu|M_ctrl_rdctl_inst ; 32 ; +; system:inst_cpu|system_cpu:cpu|M_ctrl_mem ; 32 ; +; system:inst_cpu|system_cpu:cpu|A_rot_fill_bit ; 32 ; +; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|read_fifo_en~0 ; 32 ; +; system:inst_cpu|system_cpu:cpu|A_wr_data_unfiltered[20]~51 ; 32 ; +; system:inst_cpu|system_cpu:cpu|A_dc_xfer_rd_data_offset_match ; 32 ; +; system:inst_cpu|system_cpu:cpu|D_ctrl_hi_imm16 ; 32 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|jdo[36] ; 32 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|jdo[37] ; 32 ; +; system:inst_cpu|system_cpu:cpu|E_logic_op[0] ; 32 ; +; system:inst_cpu|system_cpu:cpu|E_logic_op[1] ; 32 ; +; system:inst_cpu|system_cpu:cpu|d_writedata[15]~34 ; 32 ; +; system:inst_cpu|system_cpu:cpu|A_dc_wb_update_av_writedata ; 32 ; +; system:inst_cpu|system_cpu:cpu|Add8~5 ; 32 ; +; system:inst_cpu|system_cpu:cpu|Add8~3 ; 32 ; +; system:inst_cpu|system_cpu:cpu|D_ctrl_b_is_dst ; 30 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[0]~13 ; 30 ; +; system:inst_cpu|system_cpu:cpu|E_hbreak_req ; 30 ; +; system:inst_cpu|system_cpu:cpu|d_read ; 29 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg|oci_reg_readdata~0 ; 28 ; +; system:inst_cpu|system_pio_led:pio_led|Equal2~2 ; 28 ; +; system:inst_cpu|system_pio_led:pio_led|Equal2~5 ; 27 ; +; system:inst_cpu|altera_merlin_slave_translator:jtag_uart_0_avalon_jtag_slave_translator|read_latency_shift_reg[0] ; 27 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; 26 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0] ; 26 ; +; system:inst_cpu|system_cpu:cpu|D_ic_fill_starting~1 ; 26 ; +; system:inst_cpu|system_cpu:cpu|D_bht_data[1] ; 26 ; +; system:inst_cpu|system_cpu:cpu|E_ctrl_crst ; 25 ; +; system:inst_cpu|system_cpu:cpu|E_ctrl_exception ; 25 ; +; system:inst_cpu|system_cpu:cpu|E_ctrl_break ; 25 ; +; system:inst_cpu|system_cpu:cpu|A_ld_align_sh16 ; 25 ; +; system:inst_cpu|system_cpu:cpu|E_ctrl_br_cond_nxt~1 ; 25 ; +; system:inst_cpu|system_cpu:cpu|E_valid_jmp_indirect ; 25 ; +; system:inst_cpu|system_cpu:cpu|E_ctrl_retaddr ; 25 ; +; system:inst_cpu|altera_merlin_slave_translator:cpu_jtag_debug_module_translator|waitrequest_reset_override ; 25 ; +; system:inst_cpu|system_cpu:cpu|E_ctrl_jmp_indirect ; 24 ; +; system:inst_cpu|system_cpu:cpu|A_wr_data_unfiltered[20]~23 ; 24 ; +; system:inst_cpu|system_cpu:cpu|A_data_ram_ld_align_fill_bit ; 24 ; +; system:inst_cpu|altera_merlin_slave_translator:rs232_motor_avalon_rs232_slave_translator|read_latency_shift_reg[0] ; 24 ; +; system:inst_cpu|system_sdram:sdram|refresh_request ; 24 ; +; system:inst_cpu|system_cpu:cpu|d_address_line_field[0] ; 24 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1] ; 23 ; +; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|comb~2 ; 23 ; +; system:inst_cpu|system_cpu:cpu|D_iw[12] ; 23 ; +; system:inst_cpu|system_pio_led:pio_led|Equal2~1 ; 23 ; +; system:inst_cpu|system_cpu:cpu|E_regnum_b_cmp_D ; 23 ; +; system:inst_cpu|system_cpu:cpu|A_dc_xfer_rd_data_starting ; 22 ; +; system:inst_cpu|system_pio_led:pio_led|Equal2~0 ; 22 ; +; system:inst_cpu|system_sdram:sdram|m_state.000000001 ; 22 ; +; altera_internal_jtag~TMSUTAP ; 21 ; +; system:inst_cpu|system_cpu:cpu|D_iw[16] ; 21 ; +; system:inst_cpu|system_cpu:cpu|D_iw[14] ; 21 ; +; system:inst_cpu|altera_merlin_slave_translator:uart_0_s1_translator|read_latency_shift_reg[0] ; 21 ; +; system:inst_cpu|altera_merlin_slave_translator:sys_clk_timer_s1_translator|read_latency_shift_reg[0] ; 21 ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|td_shift[0]~4 ; 21 ; +; system:inst_cpu|system_cpu:cpu|A_dc_wb_wr_want_dmaster ; 21 ; +; system:inst_cpu|system_cpu:cpu|d_address_tag_field_nxt~0 ; 21 ; +; system:inst_cpu|system_cpu:cpu|E_ctrl_shift_rot_right ; 20 ; +; system:inst_cpu|system_rsp_xbar_demux:rsp_xbar_demux|src1_valid ; 20 ; +; system:inst_cpu|system_cpu:cpu|D_iw[13] ; 20 ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][84] ; 20 ; +; system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent|rp_valid ; 20 ; +; system:inst_cpu|altera_merlin_slave_translator:cpu_jtag_debug_module_translator|read_latency_shift_reg[0] ; 20 ; +; system:inst_cpu|system_sdram:sdram|m_state.001000000 ; 20 ; +; altera_internal_jtag~TDIUTAP ; 19 ; +; system:inst_cpu|system_rs232_motor:rs232_motor|readdata[22]~1 ; 19 ; +; system:inst_cpu|system_cpu:cpu|i_readdatavalid_d1 ; 19 ; +; system:inst_cpu|system_cpu:cpu|M_valid_from_E ; 19 ; +; system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux|saved_grant[0] ; 19 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[16]~21 ; 18 ; +; system:inst_cpu|system_cpu:cpu|D_iw[21] ; 18 ; +; system:inst_cpu|system_cpu:cpu|A_ctrl_ld_signed ; 18 ; +; system:inst_cpu|system_cpu:cpu|A_dc_fill_starting_d1 ; 18 ; +; system:inst_cpu|system_cpu:cpu|D_iw[11] ; 18 ; +; system:inst_cpu|system_cpu:cpu|E_iw[0] ; 18 ; +; system:inst_cpu|system_rsp_xbar_demux:rsp_xbar_demux_001|src1_valid~0 ; 18 ; +; system:inst_cpu|system_rsp_xbar_demux:rsp_xbar_demux_001|src0_valid~0 ; 18 ; +; system:inst_cpu|system_sdram:sdram|always5~0 ; 18 ; +; system:inst_cpu|system_sdram:sdram|init_done ; 18 ; +; system:inst_cpu|system_cpu:cpu|A_slow_ld_data_sign_bit~2 ; 17 ; +; system:inst_cpu|system_cpu:cpu|A_ld_align_byte2_byte3_fill ; 17 ; +; system:inst_cpu|system_cpu:cpu|D_iw[15] ; 17 ; +; system:inst_cpu|altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][83] ; 17 ; +; system:inst_cpu|system_sdram:sdram|WideOr9~0 ; 17 ; +; system:inst_cpu|system_uart_0:uart_0|system_uart_0_rx:the_system_uart_0_rx|baud_clk_en~2 ; 16 ; +; system:inst_cpu|system_uart_0:uart_0|system_uart_0_rx:the_system_uart_0_rx|rxd_edge ; 16 ; +; system:inst_cpu|system_sys_clk_timer:sys_clk_timer|period_h_wr_strobe ; 16 ; +; system:inst_cpu|system_sys_clk_timer:sys_clk_timer|period_l_wr_strobe ; 16 ; +; system:inst_cpu|system_uart_0:uart_0|system_uart_0_regs:the_system_uart_0_regs|divisor_wr_strobe ; 16 ; +; system:inst_cpu|system_uart_0:uart_0|system_uart_0_tx:the_system_uart_0_tx|always4~0 ; 16 ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|read_0 ; 16 ; +; system:inst_cpu|system_rsp_xbar_mux:rsp_xbar_mux|src_payload~0 ; 16 ; +; system:inst_cpu|system_rsp_xbar_mux_001:rsp_xbar_mux_001|src_payload~8 ; 16 ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|fifo_wr ; 16 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr~19 ; 16 ; +; system:inst_cpu|system_cpu:cpu|A_wr_data_unfiltered[14]~22 ; 16 ; +; system:inst_cpu|system_sdram:sdram|m_data[2]~0 ; 16 ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[7] ; 16 ; +; system:inst_cpu|system_cpu:cpu|i_read ; 16 ; +; system:inst_cpu|altera_merlin_traffic_limiter:limiter_001|save_dest_id~2 ; 15 ; +; system:inst_cpu|system_cpu:cpu|D_src2[30]~20 ; 15 ; +; system:inst_cpu|system_cpu:cpu|E_iw[2] ; 15 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|take_action_ocimem_a ; 15 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|take_action_ocimem_a~0 ; 15 ; +; system:inst_cpu|system_cpu:cpu|A_dc_wb_active ; 15 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1] ; 14 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0] ; 14 ; +; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_rs232_counters:RS232_In_Counters|baud_counter[4]~22 ; 14 ; +; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|comb~0 ; 14 ; +; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_rs232_counters:RS232_Out_Counters|baud_counter[7]~16 ; 14 ; +; system:inst_cpu|system_pio_led:pio_led|Equal2~3 ; 14 ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|wr_rfifo ; 14 ; +; system:inst_cpu|system_cpu:cpu|D_iw[2] ; 14 ; +; system:inst_cpu|system_cpu:cpu|D_ic_fill_starting_d1 ; 14 ; +; system:inst_cpu|system_cmd_xbar_demux_001:cmd_xbar_demux_001|WideOr0~13 ; 14 ; +; system:inst_cpu|system_sdram:sdram|m_state.100000000 ; 14 ; +; system:inst_cpu|system_cpu:cpu|d_address_line_field[2] ; 14 ; +; system:inst_cpu|system_cpu:cpu|d_writedata[0] ; 14 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2] ; 13 ; +; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|comb~0 ; 13 ; +; system:inst_cpu|system_uart_0:uart_0|system_uart_0_tx:the_system_uart_0_tx|do_load_shifter ; 13 ; +; system:inst_cpu|system_cpu:cpu|A_dc_xfer_rd_addr_active ; 13 ; +; system:inst_cpu|system_cpu:cpu|D_src2_imm[30]~13 ; 13 ; +; system:inst_cpu|system_cpu:cpu|D_iw[0] ; 13 ; +; system:inst_cpu|system_cpu:cpu|D_iw[1] ; 13 ; +; system:inst_cpu|system_cpu:cpu|D_iw[4] ; 13 ; +; system:inst_cpu|system_cpu:cpu|E_iw[1] ; 13 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[8]~13 ; 13 ; +; system:inst_cpu|system_cpu:cpu|M_alu_result[5] ; 13 ; +; system:inst_cpu|altera_merlin_traffic_limiter:limiter_001|has_pending_responses ; 13 ; +; system:inst_cpu|system_sdram:sdram|Equal0~4 ; 13 ; +; system:inst_cpu|system_sdram:sdram|m_addr[7]~1 ; 13 ; +; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entries[0] ; 13 ; +; system:inst_cpu|system_cpu:cpu|d_writedata[3] ; 13 ; +; system:inst_cpu|system_cpu:cpu|d_writedata[1] ; 13 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6] ; 12 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[11] ; 12 ; +; system:inst_cpu|system_cpu:cpu|A_wr_data_unfiltered[3]~1 ; 12 ; +; system:inst_cpu|system_cpu:cpu|A_wr_data_unfiltered[3]~0 ; 12 ; +; system:inst_cpu|system_cpu:cpu|D_iw[3] ; 12 ; +; system:inst_cpu|system_cpu:cpu|D_iw[5] ; 12 ; +; system:inst_cpu|system_cpu:cpu|ic_fill_dp_offset[0] ; 12 ; +; system:inst_cpu|system_cpu:cpu|E_iw[3] ; 12 ; +; system:inst_cpu|system_cpu:cpu|E_iw[5] ; 12 ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0] ; 12 ; +; system:inst_cpu|system_cpu:cpu|M_alu_result[7] ; 12 ; +; system:inst_cpu|altera_merlin_slave_translator:pio_led_s1_translator|read_latency_shift_reg[0] ; 12 ; +; system:inst_cpu|system_cpu:cpu|M_alu_result[8] ; 12 ; +; system:inst_cpu|system_cpu:cpu|M_alu_result[6] ; 12 ; +; system:inst_cpu|system_cpu:cpu|M_alu_result[9] ; 12 ; +; system:inst_cpu|system_cpu:cpu|M_alu_result[10] ; 12 ; +; system:inst_cpu|system_cpu:cpu|M_alu_result[11] ; 12 ; +; system:inst_cpu|altera_merlin_traffic_limiter:limiter_001|suppress~0 ; 12 ; +; system:inst_cpu|altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; 12 ; +; system:inst_cpu|altera_merlin_slave_translator:pio_led_s1_translator|av_begintransfer~0 ; 12 ; +; system:inst_cpu|system_cpu:cpu|ic_fill_line[3] ; 12 ; +; system:inst_cpu|system_cpu:cpu|ic_fill_line[2] ; 12 ; +; system:inst_cpu|system_cpu:cpu|ic_fill_line[1] ; 12 ; +; system:inst_cpu|system_cpu:cpu|ic_fill_line[0] ; 12 ; +; system:inst_cpu|system_cpu:cpu|ic_fill_line[5] ; 12 ; +; system:inst_cpu|system_cpu:cpu|ic_fill_line[4] ; 12 ; +; system:inst_cpu|system_cpu:cpu|ic_fill_line[7] ; 12 ; +; system:inst_cpu|system_cpu:cpu|ic_fill_line[6] ; 12 ; +; system:inst_cpu|system_sdram:sdram|i_state.011 ; 12 ; +; system:inst_cpu|system_sdram:sdram|i_state.000 ; 12 ; +; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entries[1] ; 12 ; +; system:inst_cpu|system_cpu:cpu|E_src2[0] ; 12 ; +; system:inst_cpu|system_cpu:cpu|E_src2[1] ; 12 ; +; system:inst_cpu|system_cpu:cpu|E_src2[2] ; 12 ; +; system:inst_cpu|system_cpu:cpu|E_src2[3] ; 12 ; +; system:inst_cpu|system_cpu:cpu|E_src2[4] ; 12 ; +; system:inst_cpu|system_cpu:cpu|d_writedata[2] ; 12 ; +; system:inst_cpu|system_uart_0:uart_0|system_uart_0_rx:the_system_uart_0_rx|do_start_rx ; 11 ; +; system:inst_cpu|system_uart_0:uart_0|system_uart_0_rx:the_system_uart_0_rx|got_new_char ; 11 ; +; system:inst_cpu|system_pio_led:pio_led|Equal2~4 ; 11 ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|r_val~0 ; 11 ; +; system:inst_cpu|system_cpu:cpu|A_ctrl_shift_rot ; 11 ; +; system:inst_cpu|system_cpu:cpu|Equal171~1 ; 11 ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][83] ; 11 ; +; system:inst_cpu|system_sdram:sdram|za_valid ; 11 ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|count[9] ; 11 ; +; system:inst_cpu|system_cpu:cpu|A_dc_want_fill ; 11 ; +; system:inst_cpu|altera_merlin_traffic_limiter:limiter_001|suppress~3 ; 11 ; +; system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux|WideOr1 ; 11 ; +; system:inst_cpu|system_sdram:sdram|i_state.101 ; 11 ; +; system:inst_cpu|system_sdram:sdram|i_addr[12] ; 11 ; +; system:inst_cpu|system_sdram:sdram|m_addr[7]~0 ; 11 ; +; system:inst_cpu|system_sdram:sdram|pending ; 11 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; 10 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0] ; 10 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[1] ; 10 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[3] ; 10 ; +; system:inst_cpu|system_uart_0:uart_0|system_uart_0_rx:the_system_uart_0_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[0]~0 ; 10 ; +; system:inst_cpu|system_uart_0:uart_0|system_uart_0_tx:the_system_uart_0_tx|tx_wr_strobe_onset~0 ; 10 ; +; system:inst_cpu|system_rsp_xbar_mux_001:rsp_xbar_mux_001|src_payload~12 ; 10 ; +; system:inst_cpu|system_cpu:cpu|F_ic_tag_rd_addr_nxt[7]~31 ; 10 ; +; system:inst_cpu|system_cpu:cpu|F_ic_tag_rd_addr_nxt[6]~27 ; 10 ; +; system:inst_cpu|system_cpu:cpu|F_ic_tag_rd_addr_nxt[5]~23 ; 10 ; +; system:inst_cpu|system_cpu:cpu|F_ic_tag_rd_addr_nxt[4]~19 ; 10 ; +; system:inst_cpu|system_cpu:cpu|F_ic_tag_rd_addr_nxt[3]~15 ; 10 ; +; system:inst_cpu|system_cpu:cpu|F_ic_tag_rd_addr_nxt[2]~11 ; 10 ; +; system:inst_cpu|system_cpu:cpu|F_ic_tag_rd_addr_nxt[1]~7 ; 10 ; +; system:inst_cpu|system_cpu:cpu|F_ic_tag_rd_addr_nxt[0]~3 ; 10 ; +; system:inst_cpu|system_uart_0:uart_0|system_uart_0_regs:the_system_uart_0_regs|control_wr_strobe ; 10 ; +; system:inst_cpu|system_cpu:cpu|D_iw[8] ; 10 ; +; system:inst_cpu|system_cpu:cpu|A_ld_align_sh8 ; 10 ; +; system:inst_cpu|system_cpu:cpu|ic_fill_dp_offset_nxt[2]~2 ; 10 ; +; system:inst_cpu|system_cpu:cpu|ic_fill_dp_offset_nxt[1]~0 ; 10 ; +; system:inst_cpu|system_cpu:cpu|ic_fill_dp_offset[1] ; 10 ; +; system:inst_cpu|system_cpu:cpu|hbreak_enabled ; 10 ; +; system:inst_cpu|altera_merlin_slave_translator:sysid_control_slave_translator|read_latency_shift_reg[0] ; 10 ; +; system:inst_cpu|system_cmd_xbar_demux:cmd_xbar_demux|WideOr0~1 ; 10 ; +; system:inst_cpu|system_cpu:cpu|M_alu_result[4] ; 10 ; +; system:inst_cpu|system_sdram:sdram|i_state.010 ; 10 ; +; system:inst_cpu|system_addr_router_001:addr_router_001|Equal1~3 ; 10 ; +; system:inst_cpu|system_cpu:cpu|d_writedata[6] ; 10 ; +; system:inst_cpu|system_cpu:cpu|d_writedata[5] ; 10 ; +; system:inst_cpu|system_cpu:cpu|d_writedata[4] ; 10 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; 9 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[0] ; 9 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[2] ; 9 ; +; system:inst_cpu|system_cpu:cpu|ic_tag_clr_valid_bits_nxt ; 9 ; +; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|data_in_shift_reg[1]~1 ; 9 ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[3] ; 9 ; +; system:inst_cpu|system_uart_0:uart_0|system_uart_0_tx:the_system_uart_0_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_in[2]~1 ; 9 ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[4] ; 9 ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[2] ; 9 ; +; system:inst_cpu|system_cpu:cpu|F_ic_data_rd_addr_nxt[2]~11 ; 9 ; +; system:inst_cpu|system_cpu:cpu|F_ic_data_rd_addr_nxt[1]~7 ; 9 ; +; system:inst_cpu|system_cpu:cpu|F_ic_data_rd_addr_nxt[0]~3 ; 9 ; +; system:inst_cpu|system_cpu:cpu|ic_fill_dp_offset_nxt[0]~3 ; 9 ; +; system:inst_cpu|system_cpu:cpu|A_ld_align_byte1_fill ; 9 ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[5] ; 9 ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; 9 ; +; system:inst_cpu|system_cpu:cpu|ic_tag_clr_valid_bits_nxt~2 ; 9 ; +; system:inst_cpu|system_cpu:cpu|Equal171~0 ; 9 ; +; system:inst_cpu|system_cpu:cpu|ic_fill_dp_offset[2] ; 9 ; +; system:inst_cpu|system_cpu:cpu|d_readdatavalid_d1 ; 9 ; +; system:inst_cpu|altera_merlin_slave_translator:pio_sw_s1_translator|read_latency_shift_reg[0] ; 9 ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[6] ; 9 ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|state ; 9 ; +; system:inst_cpu|system_cpu:cpu|A_dc_fill_starting~0 ; 9 ; +; system:inst_cpu|system_cpu:cpu|M_alu_result[3] ; 9 ; +; system:inst_cpu|system_cpu:cpu|M_alu_result[2] ; 9 ; +; system:inst_cpu|altera_merlin_slave_translator:cpu_jtag_debug_module_translator|wait_latency_counter[1]~0 ; 9 ; +; system:inst_cpu|system_addr_router_001:addr_router_001|Equal7~2 ; 9 ; +; system:inst_cpu|system_addr_router_001:addr_router_001|Equal2~1 ; 9 ; +; system:inst_cpu|system_sdram:sdram|m_state.000001000 ; 9 ; +; system:inst_cpu|system_sdram:sdram|m_state.010000000 ; 9 ; +; system:inst_cpu|system_sdram:sdram|m_state.000000100 ; 9 ; +; system:inst_cpu|system_cpu:cpu|d_writedata[7] ; 9 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonAReg[3] ; 9 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonAReg[2] ; 9 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonAReg[4] ; 9 ; +; system:inst_cpu|altera_merlin_width_adapter:width_adapter|address_reg[1] ; 9 ; +; system:inst_cpu|system_cpu:cpu|d_address_line_field[1] ; 9 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|clear_signal ; 8 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4] ; 8 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[4] ; 8 ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|write~0 ; 8 ; +; system:inst_cpu|system_cpu:cpu|M_br_cond_taken_history[0]~0 ; 8 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a0~0 ; 8 ; +; system:inst_cpu|system_cpu:cpu|ic_fill_valid_bits_en ; 8 ; +; system:inst_cpu|system_cpu:cpu|ic_tag_wraddress[6]~6 ; 8 ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|fifo_rd~1 ; 8 ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty ; 8 ; +; system:inst_cpu|system_cpu:cpu|A_rot_pass2 ; 8 ; +; system:inst_cpu|system_cpu:cpu|A_rot_sel_fill2 ; 8 ; +; system:inst_cpu|system_cpu:cpu|A_rot_pass3 ; 8 ; +; system:inst_cpu|system_cpu:cpu|A_rot_sel_fill3 ; 8 ; +; system:inst_cpu|system_cpu:cpu|dc_data_wr_port_en ; 8 ; +; system:inst_cpu|system_cpu:cpu|A_dc_valid_st_bypass_hit_wr_en ; 8 ; +; system:inst_cpu|system_cpu:cpu|A_rot_pass1 ; 8 ; +; system:inst_cpu|system_cpu:cpu|A_rot_sel_fill1 ; 8 ; +; system:inst_cpu|system_cpu:cpu|A_slow_ld_data_fill_bit ; 8 ; +; system:inst_cpu|system_cpu:cpu|A_rot_pass0 ; 8 ; +; system:inst_cpu|system_cpu:cpu|A_rot_sel_fill0 ; 8 ; +; system:inst_cpu|system_cpu:cpu|M_alu_result[0] ; 8 ; +; system:inst_cpu|system_cpu:cpu|Equal171~2 ; 8 ; +; system:inst_cpu|system_cpu:cpu|Equal275~0 ; 8 ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|write~0 ; 8 ; +; system:inst_cpu|altera_merlin_traffic_limiter:limiter|cmd_sink_ready~0 ; 8 ; +; system:inst_cpu|system_sdram:sdram|i_count[1] ; 8 ; +; system:inst_cpu|altera_merlin_slave_translator:sys_clk_timer_s1_translator|read_latency_shift_reg~2 ; 8 ; +; system:inst_cpu|system_cpu:cpu|M_alu_result[14] ; 8 ; +; system:inst_cpu|system_cpu:cpu|M_alu_result[12] ; 8 ; +; system:inst_cpu|altera_merlin_slave_translator:sys_clk_timer_s1_translator|wait_latency_counter[0] ; 8 ; +; system:inst_cpu|altera_avalon_sc_fifo:rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; 8 ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|av_waitrequest ; 8 ; +; system:inst_cpu|system_cmd_xbar_demux_001:cmd_xbar_demux_001|sink_ready~1 ; 8 ; +; system:inst_cpu|system_addr_router_001:addr_router_001|Equal4~1 ; 8 ; +; system:inst_cpu|altera_merlin_slave_translator:sysid_control_slave_translator|wait_latency_counter[1]~1 ; 8 ; +; system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent|WideOr0~1 ; 8 ; +; system:inst_cpu|system_addr_router:addr_router|Equal1~4 ; 8 ; +; system:inst_cpu|altera_merlin_traffic_limiter:limiter|has_pending_responses ; 8 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|q_b[2] ; 8 ; +; system:inst_cpu|system_cpu:cpu|lpm_add_sub:Add17|add_sub_qvi:auto_generated|result_int[32]~64 ; 8 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_dr_scan_reg ; 7 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; 7 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[2] ; 7 ; +; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_ca7:usedw_counter|_~2 ; 7 ; +; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_ca7:usedw_counter|_~2 ; 7 ; +; system:inst_cpu|system_sdram:sdram|f_select ; 7 ; +; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|_~0 ; 7 ; +; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|_~0 ; 7 ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|b_full ; 7 ; +; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|data_out_shift_reg[5]~2 ; 7 ; +; system:inst_cpu|system_cpu:cpu|A_dc_xfer_rd_addr_offset[0] ; 7 ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|b_full ; 7 ; +; system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux|src_data[38] ; 7 ; +; system:inst_cpu|system_cpu:cpu|D_iw[6] ; 7 ; +; system:inst_cpu|system_cpu:cpu|M_alu_result[1] ; 7 ; +; system:inst_cpu|system_cpu:cpu|dc_tag_wr_port_addr~0 ; 7 ; +; system:inst_cpu|altera_merlin_width_adapter:width_adapter|out_endofpacket~0 ; 7 ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem~0 ; 7 ; +; system:inst_cpu|system_cpu:cpu|E_src1[13] ; 7 ; +; system:inst_cpu|system_cpu:cpu|E_src1[14] ; 7 ; +; system:inst_cpu|system_cpu:cpu|E_src1[15] ; 7 ; +; system:inst_cpu|system_cpu:cpu|E_src1[16] ; 7 ; +; system:inst_cpu|system_cpu:cpu|E_src1[17] ; 7 ; +; system:inst_cpu|system_cpu:cpu|E_src1[18] ; 7 ; +; system:inst_cpu|system_cpu:cpu|E_src1[19] ; 7 ; +; system:inst_cpu|system_cpu:cpu|E_src1[20] ; 7 ; +; system:inst_cpu|system_cpu:cpu|E_src1[21] ; 7 ; +; system:inst_cpu|system_cpu:cpu|E_src1[22] ; 7 ; +; system:inst_cpu|system_cpu:cpu|E_src1[23] ; 7 ; +; system:inst_cpu|system_cpu:cpu|E_src1[24] ; 7 ; +; system:inst_cpu|system_cpu:cpu|E_src1[25] ; 7 ; +; system:inst_cpu|system_cpu:cpu|E_src1[12] ; 7 ; +; system:inst_cpu|system_cpu:cpu|E_src1[11] ; 7 ; +; system:inst_cpu|system_cpu:cpu|E_src1[10] ; 7 ; +; system:inst_cpu|system_cpu:cpu|E_src1[9] ; 7 ; +; system:inst_cpu|system_cpu:cpu|E_src1[5] ; 7 ; +; system:inst_cpu|system_cpu:cpu|E_src1[6] ; 7 ; +; system:inst_cpu|system_cpu:cpu|E_src1[7] ; 7 ; +; system:inst_cpu|system_cpu:cpu|E_src1[8] ; 7 ; +; system:inst_cpu|system_cpu:cpu|E_src1[2] ; 7 ; +; system:inst_cpu|system_cpu:cpu|E_src1[3] ; 7 ; +; system:inst_cpu|system_cpu:cpu|E_src1[4] ; 7 ; +; system:inst_cpu|system_cpu:cpu|ic_fill_ap_offset[2]~0 ; 7 ; +; system:inst_cpu|altera_merlin_slave_translator:pio_key_s1_translator|read_latency_shift_reg[0] ; 7 ; +; system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent|comb~0 ; 7 ; +; system:inst_cpu|system_sdram:sdram|i_count[2] ; 7 ; +; system:inst_cpu|system_cpu:cpu|always138~0 ; 7 ; +; system:inst_cpu|system_cpu:cpu|M_alu_result[13] ; 7 ; +; system:inst_cpu|system_cpu:cpu|M_alu_result[18] ; 7 ; +; system:inst_cpu|system_cpu:cpu|M_alu_result[19] ; 7 ; +; system:inst_cpu|system_cpu:cpu|M_alu_result[20] ; 7 ; +; system:inst_cpu|system_cpu:cpu|M_alu_result[21] ; 7 ; +; system:inst_cpu|system_cpu:cpu|M_alu_result[15] ; 7 ; +; system:inst_cpu|system_cpu:cpu|M_alu_result[16] ; 7 ; +; system:inst_cpu|system_cpu:cpu|M_alu_result[17] ; 7 ; +; system:inst_cpu|system_cpu:cpu|M_alu_result[22] ; 7 ; +; system:inst_cpu|system_cpu:cpu|M_alu_result[23] ; 7 ; +; system:inst_cpu|system_cpu:cpu|M_alu_result[24] ; 7 ; +; system:inst_cpu|system_cpu:cpu|M_alu_result[25] ; 7 ; +; system:inst_cpu|system_cpu:cpu|A_dc_wb_wr_active ; 7 ; +; system:inst_cpu|system_cpu:cpu|A_valid ; 7 ; +; system:inst_cpu|system_cpu:cpu|A_dc_wb_rd_data_first ; 7 ; +; system:inst_cpu|altera_avalon_sc_fifo:sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; 7 ; +; system:inst_cpu|altera_merlin_slave_translator:uart_0_s1_translator|wait_latency_counter[1] ; 7 ; +; system:inst_cpu|system_addr_router_001:addr_router_001|src_channel[1]~2 ; 7 ; +; system:inst_cpu|system_sdram:sdram|m_count[1] ; 7 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy|virtual_state_cdr ; 7 ; +; system:inst_cpu|system_pio_led:pio_led|data_out[0]~2 ; 7 ; +; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|Equal1~0 ; 7 ; +; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|full_dff ; 7 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|q_b[1] ; 7 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|q_b[0] ; 7 ; +; system:inst_cpu|system_cpu:cpu|A_dc_fill_has_started ; 7 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena_proc~1 ; 6 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_info_reg_ena~0 ; 6 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[0] ; 6 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[3] ; 6 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[3] ; 6 ; +; system:inst_cpu|system_cpu:cpu|D_ic_fill_starting~1_wirecell ; 6 ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|_~4 ; 6 ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|always6~0 ; 6 ; +; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_v9b:rd_ptr_msb|_~0 ; 6 ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|always5~0 ; 6 ; +; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_rs232_counters:RS232_In_Counters|all_bits_transmitted ; 6 ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|always4~0 ; 6 ; +; system:inst_cpu|system_uart_0:uart_0|system_uart_0_rx:the_system_uart_0_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[0] ; 6 ; +; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_v9b:rd_ptr_msb|_~0 ; 6 ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|_~0 ; 6 ; +; system:inst_cpu|system_cpu:cpu|E_ctrl_shift_rot_left ; 6 ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|always3~0 ; 6 ; +; system:inst_cpu|system_uart_0:uart_0|system_uart_0_tx:the_system_uart_0_tx|tx_ready ; 6 ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|always2~0 ; 6 ; +; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_rs232_counters:RS232_Out_Counters|Equal0~4 ; 6 ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|t_ena~reg0 ; 6 ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw|counter_reg_bit[0] ; 6 ; +; system:inst_cpu|system_cpu:cpu|A_dc_xfer_rd_addr_offset[1] ; 6 ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|always1~0 ; 6 ; +; system:inst_cpu|system_cpu:cpu|D_iw[7] ; 6 ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[6]~5 ; 6 ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|always0~0 ; 6 ; +; system:inst_cpu|system_cpu:cpu|D_issue ; 6 ; +; system:inst_cpu|system_cpu:cpu|E_src1[31] ; 6 ; +; system:inst_cpu|system_cpu:cpu|latched_oci_tb_hbreak_req ; 6 ; +; system:inst_cpu|system_cpu:cpu|E_valid~0 ; 6 ; +; system:inst_cpu|system_cpu:cpu|av_wr_data_transfer~0 ; 6 ; +; system:inst_cpu|altera_merlin_slave_translator:pio_motor_rst_s1_translator|read_latency_shift_reg[0] ; 6 ; +; system:inst_cpu|altera_merlin_traffic_limiter:limiter|response_accepted~0 ; 6 ; +; system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux_001|WideOr1 ; 6 ; +; system:inst_cpu|system_sdram:sdram|m_count[0] ; 6 ; +; system:inst_cpu|system_cpu:cpu|A_mem_baddr[7] ; 6 ; +; system:inst_cpu|system_cpu:cpu|A_mem_baddr[5] ; 6 ; +; system:inst_cpu|system_cpu:cpu|A_mem_baddr[8] ; 6 ; +; system:inst_cpu|system_cpu:cpu|A_mem_baddr[6] ; 6 ; +; system:inst_cpu|system_cpu:cpu|A_mem_baddr[9] ; 6 ; +; system:inst_cpu|system_cpu:cpu|A_mem_baddr[10] ; 6 ; +; system:inst_cpu|system_cpu:cpu|A_mem_baddr[11] ; 6 ; +; system:inst_cpu|system_cpu:cpu|A_dc_wr_data_cnt[3] ; 6 ; +; system:inst_cpu|system_cpu:cpu|A_dc_wb_wr_starting ; 6 ; +; system:inst_cpu|system_addr_router_001:addr_router_001|src_channel[0]~3 ; 6 ; +; system:inst_cpu|system_sys_clk_timer:sys_clk_timer|period_l_wr_strobe~0 ; 6 ; +; system:inst_cpu|altera_avalon_sc_fifo:pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; 6 ; +; system:inst_cpu|system_addr_router_001:addr_router_001|Equal8~0 ; 6 ; +; system:inst_cpu|altera_avalon_sc_fifo:pio_key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; 6 ; +; system:inst_cpu|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; 6 ; +; system:inst_cpu|altera_avalon_sc_fifo:pio_sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; 6 ; +; system:inst_cpu|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; 6 ; +; system:inst_cpu|altera_avalon_sc_fifo:uart_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; 6 ; +; system:inst_cpu|system_sdram:sdram|m_count[2] ; 6 ; +; system:inst_cpu|altera_avalon_sc_fifo:pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; 6 ; +; system:inst_cpu|system_addr_router_001:addr_router_001|Equal7~1 ; 6 ; +; system:inst_cpu|system_sdram:sdram|f_pop ; 6 ; +; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|full_dff ; 6 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|q_b[25] ; 6 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|q_b[26] ; 6 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|q_b[23] ; 6 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|q_b[24] ; 6 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|q_b[31] ; 6 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|q_b[22] ; 6 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|q_b[28] ; 6 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|q_b[29] ; 6 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|q_b[30] ; 6 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|q_b[27] ; 6 ; +; system:inst_cpu|system_cpu:cpu|d_writedata[10] ; 6 ; +; system:inst_cpu|system_cpu:cpu|d_writedata[9] ; 6 ; +; system:inst_cpu|system_cpu:cpu|d_writedata[8] ; 6 ; +; system:inst_cpu|system_cpu:cpu|lpm_add_sub:Add17|add_sub_qvi:auto_generated|result_int[1]~2 ; 6 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[4]~23 ; 5 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[4]~22 ; 5 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[0]~12 ; 5 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[0]~11 ; 5 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][0]~9 ; 5 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][0]~2 ; 5 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2]~3 ; 5 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[3]~0 ; 5 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]~12 ; 5 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]~5 ; 5 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_proc~0 ; 5 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|Equal11~0 ; 5 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[1] ; 5 ; +; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_rs232_counters:RS232_In_Counters|Equal0~2 ; 5 ; +; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_rs232_counters:RS232_In_Counters|bit_counter[0] ; 5 ; +; system:inst_cpu|system_uart_0:uart_0|system_uart_0_rx:the_system_uart_0_rx|altera_std_synchronizer:the_altera_std_synchronizer|dreg[0] ; 5 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg|take_action_oci_intr_mask_reg~0 ; 5 ; +; system:inst_cpu|system_sys_clk_timer:sys_clk_timer|control_wr_strobe ; 5 ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw|counter_reg_bit[0] ; 5 ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw|counter_reg_bit[3] ; 5 ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw|counter_reg_bit[4] ; 5 ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw|counter_reg_bit[5] ; 5 ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw|counter_reg_bit[1] ; 5 ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw|counter_reg_bit[2] ; 5 ; +; system:inst_cpu|system_sdram:sdram|za_data[5] ; 5 ; +; system:inst_cpu|altera_merlin_slave_translator:sysid_control_slave_translator|av_readdata_pre[30] ; 5 ; +; system:inst_cpu|system_sdram:sdram|za_data[4] ; 5 ; +; system:inst_cpu|system_cpu:cpu|M_iw[6] ; 5 ; +; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_rs232_counters:RS232_Out_Counters|bit_counter[0] ; 5 ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw|counter_reg_bit[1] ; 5 ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw|counter_reg_bit[2] ; 5 ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw|counter_reg_bit[3] ; 5 ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw|counter_reg_bit[4] ; 5 ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw|counter_reg_bit[5] ; 5 ; +; system:inst_cpu|system_cpu:cpu|A_dc_xfer_rd_addr_offset[2] ; 5 ; +; system:inst_cpu|system_cpu:cpu|Equal154~6 ; 5 ; +; system:inst_cpu|system_cpu:cpu|A_dc_fill_dp_offset[0] ; 5 ; +; system:inst_cpu|system_cpu:cpu|A_status_reg_pie ; 5 ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|write_stalled~1 ; 5 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg|Equal0~2 ; 5 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg|Equal0~1 ; 5 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg|Equal0~0 ; 5 ; +; system:inst_cpu|system_cpu:cpu|A_wr_data_unfiltered[26]~108 ; 5 ; +; system:inst_cpu|system_cpu:cpu|A_wr_data_unfiltered[27]~105 ; 5 ; +; system:inst_cpu|system_cpu:cpu|A_wr_data_unfiltered[28]~102 ; 5 ; +; system:inst_cpu|system_cpu:cpu|A_wr_data_unfiltered[29]~99 ; 5 ; +; system:inst_cpu|system_cpu:cpu|A_wr_data_unfiltered[30]~96 ; 5 ; +; system:inst_cpu|system_cpu:cpu|A_wr_data_unfiltered[31]~93 ; 5 ; +; system:inst_cpu|system_cpu:cpu|D_iw[19] ; 5 ; +; system:inst_cpu|system_cpu:cpu|A_wr_data_unfiltered[13]~90 ; 5 ; +; system:inst_cpu|system_cpu:cpu|D_iw[20] ; 5 ; +; system:inst_cpu|system_cpu:cpu|A_wr_data_unfiltered[14]~87 ; 5 ; +; system:inst_cpu|system_cpu:cpu|A_wr_data_unfiltered[15]~84 ; 5 ; +; system:inst_cpu|system_cpu:cpu|A_wr_data_unfiltered[16]~81 ; 5 ; +; system:inst_cpu|system_cpu:cpu|A_wr_data_unfiltered[17]~78 ; 5 ; +; system:inst_cpu|system_cpu:cpu|A_wr_data_unfiltered[18]~75 ; 5 ; +; system:inst_cpu|system_cpu:cpu|A_wr_data_unfiltered[19]~72 ; 5 ; +; system:inst_cpu|system_cpu:cpu|A_wr_data_unfiltered[20]~69 ; 5 ; +; system:inst_cpu|system_cpu:cpu|A_wr_data_unfiltered[21]~66 ; 5 ; +; system:inst_cpu|system_cpu:cpu|A_wr_data_unfiltered[22]~63 ; 5 ; +; system:inst_cpu|system_cpu:cpu|A_wr_data_unfiltered[23]~60 ; 5 ; +; system:inst_cpu|system_cpu:cpu|A_wr_data_unfiltered[24]~57 ; 5 ; +; system:inst_cpu|system_cpu:cpu|A_wr_data_unfiltered[25]~54 ; 5 ; +; system:inst_cpu|system_cpu:cpu|D_ctrl_unsigned_lo_imm16 ; 5 ; +; system:inst_cpu|system_cpu:cpu|D_iw[18] ; 5 ; +; system:inst_cpu|system_cpu:cpu|A_wr_data_unfiltered[12]~50 ; 5 ; +; system:inst_cpu|system_cpu:cpu|A_dc_rd_data_cnt[2]~0 ; 5 ; +; system:inst_cpu|system_cpu:cpu|A_wr_data_unfiltered[11]~47 ; 5 ; +; system:inst_cpu|system_cpu:cpu|A_wr_data_unfiltered[10]~44 ; 5 ; +; system:inst_cpu|system_cpu:cpu|A_wr_data_unfiltered[9]~41 ; 5 ; +; system:inst_cpu|system_cpu:cpu|A_wr_data_unfiltered[5]~38 ; 5 ; +; system:inst_cpu|system_cpu:cpu|A_wr_data_unfiltered[6]~34 ; 5 ; +; system:inst_cpu|system_cpu:cpu|A_wr_data_unfiltered[7]~30 ; 5 ; +; system:inst_cpu|system_cpu:cpu|A_wr_data_unfiltered[8]~26 ; 5 ; +; system:inst_cpu|system_cpu:cpu|A_wr_data_unfiltered[0]~21 ; 5 ; +; system:inst_cpu|system_cpu:cpu|A_wr_data_unfiltered[1]~17 ; 5 ; +; system:inst_cpu|system_cpu:cpu|A_wr_data_unfiltered[2]~13 ; 5 ; +; system:inst_cpu|system_cpu:cpu|A_wr_data_unfiltered[3]~9 ; 5 ; +; system:inst_cpu|system_cpu:cpu|A_wr_data_unfiltered[4]~5 ; 5 ; +; system:inst_cpu|system_cpu:cpu|F_pc[1] ; 5 ; +; system:inst_cpu|system_cpu:cpu|F_pc[0] ; 5 ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|jupdate~0 ; 5 ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|td_shift~6 ; 5 ; +; system:inst_cpu|system_cpu:cpu|E_src1[26] ; 5 ; +; system:inst_cpu|system_cpu:cpu|E_src1[27] ; 5 ; +; system:inst_cpu|system_cpu:cpu|E_src1[28] ; 5 ; +; system:inst_cpu|system_cpu:cpu|E_src1[29] ; 5 ; +; system:inst_cpu|system_cpu:cpu|E_src1[30] ; 5 ; +; system:inst_cpu|system_cpu:cpu|A_dc_wb_rd_addr_starting ; 5 ; +; system:inst_cpu|system_cpu:cpu|E_iw[12] ; 5 ; +; system:inst_cpu|system_cpu:cpu|E_iw[14] ; 5 ; +; system:inst_cpu|system_cpu:cpu|E_iw[15] ; 5 ; +; system:inst_cpu|system_cpu:cpu|E_src1[0] ; 5 ; +; system:inst_cpu|system_cpu:cpu|E_src1[1] ; 5 ; +; system:inst_cpu|system_cpu:cpu|A_dc_xfer_rd_addr_starting~2 ; 5 ; +; system:inst_cpu|system_cmd_xbar_demux_001:cmd_xbar_demux_001|sink_ready~3 ; 5 ; +; system:inst_cpu|altera_merlin_traffic_limiter:limiter_001|response_accepted ; 5 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|jdo[35] ; 5 ; +; system:inst_cpu|system_cpu:cpu|A_shift_rot_stall ; 5 ; +; system:inst_cpu|system_addr_router_001:addr_router_001|Equal3~0 ; 5 ; +; system:inst_cpu|altera_merlin_slave_translator:sys_clk_timer_s1_translator|wait_latency_counter[1] ; 5 ; +; system:inst_cpu|system_cpu:cpu|ic_fill_ap_offset[0] ; 5 ; +; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|always2~4 ; 5 ; +; system:inst_cpu|system_addr_router_001:addr_router_001|Equal5~0 ; 5 ; +; system:inst_cpu|system_cpu:cpu|d_byteenable[0] ; 5 ; +; system:inst_cpu|altera_merlin_slave_translator:pio_led_s1_translator|wait_latency_counter[1] ; 5 ; +; system:inst_cpu|system_sdram:sdram|Selector38~2 ; 5 ; +; system:inst_cpu|system_sdram:sdram|m_state.000100000 ; 5 ; +; system:inst_cpu|system_sdram:sdram|pending~10 ; 5 ; +; system:inst_cpu|system_sdram:sdram|active_cs_n ; 5 ; +; system:inst_cpu|system_rs232_motor:rs232_motor|write_fifo_write_en ; 5 ; +; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|transmitting_data ; 5 ; +; system:inst_cpu|system_cpu:cpu|d_writedata[15] ; 5 ; +; system:inst_cpu|system_cpu:cpu|d_writedata[14] ; 5 ; +; system:inst_cpu|system_cpu:cpu|d_writedata[13] ; 5 ; +; system:inst_cpu|system_cpu:cpu|d_writedata[12] ; 5 ; +; system:inst_cpu|system_cpu:cpu|d_writedata[11] ; 5 ; +; system:inst_cpu|system_cpu:cpu|A_slow_inst_sel ; 5 ; +; system:inst_cpu|system_cpu:cpu|lpm_add_sub:Add17|add_sub_qvi:auto_generated|result_int[2]~4 ; 5 ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|td_shift[9] ; 5 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[0]~15 ; 4 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[0]~2 ; 4 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[0]~0 ; 4 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_info_reg_ena ; 4 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_proc~0 ; 4 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[1]~8 ; 4 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena_proc~0 ; 4 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[15] ; 4 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[4] ; 4 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[1] ; 4 ; +; system:inst_cpu|system_addr_router_001:addr_router_001|src_channel[0]~5 ; 4 ; +; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_rs232_counters:RS232_In_Counters|bit_counter[2]~0 ; 4 ; +; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_rs232_counters:RS232_In_Counters|bit_counter[1] ; 4 ; +; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_rs232_counters:RS232_In_Counters|bit_counter[2] ; 4 ; +; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|rd_ptr_lsb ; 4 ; +; system:inst_cpu|altera_merlin_slave_translator:uart_0_s1_translator|end_begintransfer ; 4 ; +; system:inst_cpu|system_uart_0:uart_0|system_uart_0_regs:the_system_uart_0_regs|baud_divisor[15] ; 4 ; +; system:inst_cpu|system_uart_0:uart_0|system_uart_0_regs:the_system_uart_0_regs|baud_divisor[14] ; 4 ; +; system:inst_cpu|system_uart_0:uart_0|system_uart_0_regs:the_system_uart_0_regs|baud_divisor[13] ; 4 ; +; system:inst_cpu|system_uart_0:uart_0|system_uart_0_regs:the_system_uart_0_regs|baud_divisor[12] ; 4 ; +; system:inst_cpu|system_uart_0:uart_0|system_uart_0_regs:the_system_uart_0_regs|baud_divisor[11] ; 4 ; +; system:inst_cpu|system_uart_0:uart_0|system_uart_0_regs:the_system_uart_0_regs|baud_divisor[10] ; 4 ; +; system:inst_cpu|system_uart_0:uart_0|system_uart_0_regs:the_system_uart_0_regs|baud_divisor[7] ; 4 ; +; system:inst_cpu|system_uart_0:uart_0|system_uart_0_regs:the_system_uart_0_regs|baud_divisor[4] ; 4 ; +; system:inst_cpu|system_uart_0:uart_0|system_uart_0_regs:the_system_uart_0_regs|baud_divisor[3] ; 4 ; +; system:inst_cpu|system_uart_0:uart_0|system_uart_0_regs:the_system_uart_0_regs|baud_divisor[1] ; 4 ; +; system:inst_cpu|system_cpu:cpu|D_control_reg_rddata_muxed[1]~0 ; 4 ; +; system:inst_cpu|system_cpu:cpu|E_ctrl_rot ; 4 ; +; system:inst_cpu|system_uart_0:uart_0|system_uart_0_rx:the_system_uart_0_rx|rx_char_ready ; 4 ; +; system:inst_cpu|system_uart_0:uart_0|system_uart_0_rx:the_system_uart_0_rx|framing_error ; 4 ; +; system:inst_cpu|system_uart_0:uart_0|system_uart_0_rx:the_system_uart_0_rx|rx_overrun ; 4 ; +; system:inst_cpu|system_uart_0:uart_0|system_uart_0_rx:the_system_uart_0_rx|break_detect ; 4 ; +; system:inst_cpu|system_uart_0:uart_0|system_uart_0_tx:the_system_uart_0_tx|tx_overrun ; 4 ; +; system:inst_cpu|system_sys_clk_timer:sys_clk_timer|Equal0~10 ; 4 ; +; system:inst_cpu|system_cpu:cpu|A_ienable_reg_irq1~0 ; 4 ; +; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_rs232_counters:RS232_Out_Counters|bit_counter[2]~0 ; 4 ; +; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|rd_ptr_lsb ; 4 ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|fifo_rd~2 ; 4 ; +; system:inst_cpu|system_sdram:sdram|za_data[13] ; 4 ; +; system:inst_cpu|system_sdram:sdram|za_data[14] ; 4 ; +; system:inst_cpu|system_sdram:sdram|za_data[6] ; 4 ; +; system:inst_cpu|system_sdram:sdram|za_data[7] ; 4 ; +; system:inst_cpu|system_sdram:sdram|za_data[15] ; 4 ; +; system:inst_cpu|system_sdram:sdram|za_data[8] ; 4 ; +; system:inst_cpu|system_sdram:sdram|za_data[0] ; 4 ; +; system:inst_cpu|system_sdram:sdram|za_data[9] ; 4 ; +; system:inst_cpu|system_sdram:sdram|za_data[1] ; 4 ; +; system:inst_cpu|system_sdram:sdram|za_data[10] ; 4 ; +; system:inst_cpu|system_sdram:sdram|za_data[2] ; 4 ; +; system:inst_cpu|system_sdram:sdram|za_data[11] ; 4 ; +; system:inst_cpu|system_sdram:sdram|za_data[3] ; 4 ; +; system:inst_cpu|system_sdram:sdram|za_data[12] ; 4 ; +; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_rs232_counters:RS232_Out_Counters|bit_counter[1] ; 4 ; +; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_rs232_counters:RS232_Out_Counters|bit_counter[2] ; 4 ; +; system:inst_cpu|system_cpu:cpu|dc_data_rd_port_addr[9]~19 ; 4 ; +; system:inst_cpu|system_cpu:cpu|dc_data_rd_port_addr[8]~17 ; 4 ; +; system:inst_cpu|system_cpu:cpu|dc_data_rd_port_addr[7]~15 ; 4 ; +; system:inst_cpu|system_cpu:cpu|dc_data_rd_port_addr[6]~13 ; 4 ; +; system:inst_cpu|system_cpu:cpu|dc_data_rd_port_addr[5]~11 ; 4 ; +; system:inst_cpu|system_cpu:cpu|dc_data_rd_port_addr[4]~9 ; 4 ; +; system:inst_cpu|system_cpu:cpu|dc_data_rd_port_addr[3]~7 ; 4 ; +; system:inst_cpu|system_cpu:cpu|dc_data_rd_port_addr[2]~5 ; 4 ; +; system:inst_cpu|system_cpu:cpu|dc_data_rd_port_addr[1]~3 ; 4 ; +; system:inst_cpu|system_cpu:cpu|dc_data_rd_port_addr[0]~1 ; 4 ; +; system:inst_cpu|system_cpu:cpu|A_dc_fill_byte_en~2 ; 4 ; +; system:inst_cpu|system_cpu:cpu|dc_data_wr_port_addr[9]~12 ; 4 ; +; system:inst_cpu|system_cpu:cpu|dc_data_wr_port_addr[8]~11 ; 4 ; +; system:inst_cpu|system_cpu:cpu|dc_data_wr_port_addr[7]~10 ; 4 ; +; system:inst_cpu|system_cpu:cpu|dc_data_wr_port_addr[6]~9 ; 4 ; +; system:inst_cpu|system_cpu:cpu|dc_data_wr_port_addr[5]~8 ; 4 ; +; system:inst_cpu|system_cpu:cpu|dc_data_wr_port_addr[4]~7 ; 4 ; +; system:inst_cpu|system_cpu:cpu|dc_data_wr_port_addr[3]~6 ; 4 ; +; system:inst_cpu|system_cpu:cpu|dc_data_wr_port_addr[2]~5 ; 4 ; +; system:inst_cpu|system_cpu:cpu|dc_data_wr_port_addr[1]~3 ; 4 ; +; system:inst_cpu|system_cpu:cpu|dc_data_wr_port_addr[0]~1 ; 4 ; +; system:inst_cpu|system_cpu:cpu|A_rot_mask[5] ; 4 ; +; system:inst_cpu|system_cpu:cpu|A_rot_mask[6] ; 4 ; +; system:inst_cpu|system_cpu:cpu|A_rot_mask[7] ; 4 ; +; system:inst_cpu|system_cpu:cpu|d_readdata_d1[31] ; 4 ; +; system:inst_cpu|system_cpu:cpu|d_readdata_d1[23] ; 4 ; +; system:inst_cpu|system_cpu:cpu|A_rot_mask[0] ; 4 ; +; system:inst_cpu|system_cpu:cpu|A_rot_mask[1] ; 4 ; +; system:inst_cpu|system_cpu:cpu|A_rot_mask[2] ; 4 ; +; system:inst_cpu|system_cpu:cpu|A_rot_mask[3] ; 4 ; +; system:inst_cpu|system_cpu:cpu|A_dc_fill_dp_offset[1] ; 4 ; +; system:inst_cpu|system_cpu:cpu|A_rot_mask[4] ; 4 ; +; system:inst_cpu|system_cpu:cpu|A_dst_regnum_from_M[4] ; 4 ; +; system:inst_cpu|system_cpu:cpu|A_dst_regnum_from_M[3] ; 4 ; +; system:inst_cpu|system_cpu:cpu|A_dst_regnum_from_M[2] ; 4 ; +; system:inst_cpu|system_cpu:cpu|A_dst_regnum_from_M[1] ; 4 ; +; system:inst_cpu|system_cpu:cpu|A_dst_regnum_from_M[0] ; 4 ; +; system:inst_cpu|system_cpu:cpu|A_wr_dst_reg_from_M ; 4 ; +; system:inst_cpu|system_cpu:cpu|F_iw[0]~13 ; 4 ; +; system:inst_cpu|system_cpu:cpu|D_dst_regnum[4]~6 ; 4 ; +; system:inst_cpu|system_cpu:cpu|D_dst_regnum[2]~5 ; 4 ; +; system:inst_cpu|system_cpu:cpu|D_dst_regnum[3]~4 ; 4 ; +; system:inst_cpu|system_cpu:cpu|D_dst_regnum[0]~3 ; 4 ; +; system:inst_cpu|system_cpu:cpu|D_dst_regnum[4]~2 ; 4 ; +; system:inst_cpu|system_cpu:cpu|F_iw[1]~8 ; 4 ; +; system:inst_cpu|system_cpu:cpu|ic_fill_dp_offset_en~0 ; 4 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|Equal0~1 ; 4 ; +; system:inst_cpu|system_cpu:cpu|A_dc_rd_data_cnt[2]~1 ; 4 ; +; system:inst_cpu|system_cpu:cpu|A_dc_rd_data_cnt[0] ; 4 ; +; system:inst_cpu|system_cpu:cpu|D_iw[17] ; 4 ; +; system:inst_cpu|system_cpu:cpu|D_valid ; 4 ; +; system:inst_cpu|system_cpu:cpu|Equal154~3 ; 4 ; +; system:inst_cpu|system_cpu:cpu|A_dc_dcache_management_wr_en~0 ; 4 ; +; system:inst_cpu|altera_merlin_traffic_limiter:limiter_001|pending_response_count[3]~3 ; 4 ; +; system:inst_cpu|altera_merlin_slave_translator:rs232_motor_avalon_rs232_slave_translator|av_begintransfer~0 ; 4 ; +; system:inst_cpu|system_cpu:cpu|A_dc_rd_addr_cnt[1]~2 ; 4 ; +; system:inst_cpu|system_cpu:cpu|av_rd_addr_accepted~0 ; 4 ; +; system:inst_cpu|system_cpu:cpu|A_dc_rd_addr_cnt[0] ; 4 ; +; system:inst_cpu|system_cpu:cpu|E_br_result~1 ; 4 ; +; system:inst_cpu|system_cpu:cpu|E_ctrl_br_cond ; 4 ; +; system:inst_cpu|system_cpu:cpu|D_op_div~4 ; 4 ; +; system:inst_cpu|system_cpu:cpu|ic_fill_ap_cnt[0] ; 4 ; +; system:inst_cpu|system_sdram:sdram|i_count[0] ; 4 ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|td_shift[10] ; 4 ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|write_stalled ; 4 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|Equal0~0 ; 4 ; +; system:inst_cpu|system_cpu:cpu|E_alu_result[18] ; 4 ; +; system:inst_cpu|system_cpu:cpu|E_alu_result[19] ; 4 ; +; system:inst_cpu|system_cpu:cpu|E_alu_result[20] ; 4 ; +; system:inst_cpu|system_cpu:cpu|E_alu_result[21] ; 4 ; +; system:inst_cpu|system_cpu:cpu|E_alu_result[16] ; 4 ; +; system:inst_cpu|system_cpu:cpu|E_alu_result[17] ; 4 ; +; system:inst_cpu|system_cpu:cpu|E_alu_result[22] ; 4 ; +; system:inst_cpu|system_cpu:cpu|E_alu_result[23] ; 4 ; +; system:inst_cpu|system_cpu:cpu|E_alu_result[24] ; 4 ; +; system:inst_cpu|system_cpu:cpu|E_alu_result[25] ; 4 ; +; system:inst_cpu|system_cpu:cpu|A_dc_wr_data_cnt[2]~0 ; 4 ; +; system:inst_cpu|system_cpu:cpu|A_dc_wr_data_cnt[0] ; 4 ; +; system:inst_cpu|system_cpu:cpu|A_dc_wb_rd_addr_offset[0] ; 4 ; +; system:inst_cpu|system_cpu:cpu|A_dc_wb_en ; 4 ; +; system:inst_cpu|system_cpu:cpu|A_mul_cnt[0] ; 4 ; +; system:inst_cpu|system_cpu:cpu|E_iw[11] ; 4 ; +; system:inst_cpu|system_cpu:cpu|E_iw[13] ; 4 ; +; system:inst_cpu|system_cpu:cpu|E_iw[16] ; 4 ; +; system:inst_cpu|system_cpu:cpu|Equal209~1 ; 4 ; +; system:inst_cpu|system_cpu:cpu|M_dc_hit ; 4 ; +; system:inst_cpu|system_cpu:cpu|M_sel_data_master ; 4 ; +; system:inst_cpu|altera_merlin_slave_translator:sysid_control_slave_translator|wait_latency_counter[1]~3 ; 4 ; +; system:inst_cpu|system_cpu:cpu|D_pc[2] ; 4 ; +; system:inst_cpu|system_cpu:cpu|D_pc[1] ; 4 ; +; system:inst_cpu|system_cpu:cpu|D_pc[0] ; 4 ; +; system:inst_cpu|system_cpu:cpu|d_byteenable_nxt[1]~0 ; 4 ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; 4 ; +; system:inst_cpu|altera_merlin_traffic_limiter:limiter|save_dest_id~0 ; 4 ; +; system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux_001|update_grant~0 ; 4 ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|count[1] ; 4 ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|user_saw_rvalid ; 4 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy|virtual_state_uir~0 ; 4 ; +; system:inst_cpu|system_cpu:cpu|M_ctrl_st_bypass ; 4 ; +; system:inst_cpu|system_cpu:cpu|A_mem_baddr[3] ; 4 ; +; system:inst_cpu|system_cpu:cpu|A_mem_baddr[2] ; 4 ; +; system:inst_cpu|system_cpu:cpu|A_mem_stall ; 4 ; +; system:inst_cpu|system_cpu:cpu|A_mem_baddr[4] ; 4 ; +; system:inst_cpu|system_addr_router_001:addr_router_001|Equal9~1 ; 4 ; +; system:inst_cpu|system_addr_router_001:addr_router_001|Equal7~3 ; 4 ; +; system:inst_cpu|altera_merlin_slave_agent:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent|m0_write~0 ; 4 ; +; system:inst_cpu|altera_merlin_slave_translator:cpu_jtag_debug_module_translator|wait_latency_counter[0] ; 4 ; +; system:inst_cpu|altera_merlin_slave_translator:pio_motor_rst_s1_translator|wait_latency_counter[1] ; 4 ; +; system:inst_cpu|altera_merlin_slave_translator:pio_motor_rst_s1_translator|av_waitrequest_generated~0 ; 4 ; +; system:inst_cpu|system_addr_router_001:addr_router_001|Equal5~2 ; 4 ; +; system:inst_cpu|altera_merlin_slave_translator:pio_motor_rst_s1_translator|wait_latency_counter[0] ; 4 ; +; system:inst_cpu|altera_merlin_slave_translator:sysid_control_slave_translator|av_waitrequest_generated~1 ; 4 ; +; system:inst_cpu|altera_merlin_slave_translator:uart_0_s1_translator|uav_waitrequest~0 ; 4 ; +; system:inst_cpu|altera_merlin_width_adapter:width_adapter|count[0] ; 4 ; +; system:inst_cpu|system_cpu:cpu|ic_fill_ap_offset[1] ; 4 ; +; system:inst_cpu|system_sdram:sdram|i_state.111 ; 4 ; +; system:inst_cpu|system_sdram:sdram|i_state.001 ; 4 ; +; system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent|m0_write ; 4 ; +; system:inst_cpu|system_addr_router_001:addr_router_001|src_data[89]~2 ; 4 ; +; system:inst_cpu|system_addr_router_001:addr_router_001|Equal4~0 ; 4 ; +; system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent|local_read~0 ; 4 ; +; system:inst_cpu|system_cmd_xbar_demux:cmd_xbar_demux|src1_valid~0 ; 4 ; +; system:inst_cpu|system_cpu:cpu|ic_fill_tag[0] ; 4 ; +; system:inst_cpu|system_cpu:cpu|ic_fill_tag[1] ; 4 ; +; system:inst_cpu|system_cpu:cpu|ic_fill_tag[2] ; 4 ; +; system:inst_cpu|system_cpu:cpu|ic_fill_tag[3] ; 4 ; +; system:inst_cpu|system_cpu:cpu|ic_fill_tag[4] ; 4 ; +; system:inst_cpu|system_cpu:cpu|ic_fill_tag[5] ; 4 ; +; system:inst_cpu|system_cpu:cpu|ic_fill_tag[6] ; 4 ; +; system:inst_cpu|system_cpu:cpu|ic_fill_tag[7] ; 4 ; +; system:inst_cpu|system_cpu:cpu|ic_fill_tag[8] ; 4 ; +; system:inst_cpu|system_cpu:cpu|ic_fill_tag[9] ; 4 ; +; system:inst_cpu|system_cpu:cpu|ic_fill_tag[10] ; 4 ; +; system:inst_cpu|system_sdram:sdram|LessThan1~0 ; 4 ; +; system:inst_cpu|system_sdram:sdram|Selector30~2 ; 4 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|Mux37~0 ; 4 ; +; system:inst_cpu|altera_merlin_slave_translator:pio_led_s1_translator|wait_latency_counter[0] ; 4 ; +; system:inst_cpu|system_sdram:sdram|WideOr16~0 ; 4 ; +; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|rd_data[41]~1 ; 4 ; +; system:inst_cpu|system_sdram:sdram|m_next.010000000 ; 4 ; +; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_ca7:usedw_counter|counter_reg_bit[5] ; 4 ; +; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_ca7:usedw_counter|counter_reg_bit[6] ; 4 ; +; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_ca7:usedw_counter|counter_reg_bit[0] ; 4 ; +; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_ca7:usedw_counter|counter_reg_bit[1] ; 4 ; +; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_ca7:usedw_counter|counter_reg_bit[2] ; 4 ; +; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_ca7:usedw_counter|counter_reg_bit[3] ; 4 ; +; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_ca7:usedw_counter|counter_reg_bit[4] ; 4 ; +; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_ca7:usedw_counter|counter_reg_bit[5] ; 4 ; +; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_ca7:usedw_counter|counter_reg_bit[6] ; 4 ; +; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_ca7:usedw_counter|counter_reg_bit[2] ; 4 ; +; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_ca7:usedw_counter|counter_reg_bit[3] ; 4 ; +; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_ca7:usedw_counter|counter_reg_bit[4] ; 4 ; +; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_ca7:usedw_counter|counter_reg_bit[0] ; 4 ; +; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_ca7:usedw_counter|counter_reg_bit[1] ; 4 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[31] ; 4 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_dc_data_module:system_cpu_dc_data|altsyncram:the_altsyncram|altsyncram_2jf1:auto_generated|q_b[23] ; 4 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_dc_data_module:system_cpu_dc_data|altsyncram:the_altsyncram|altsyncram_2jf1:auto_generated|q_b[15] ; 4 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_dc_data_module:system_cpu_dc_data|altsyncram:the_altsyncram|altsyncram_2jf1:auto_generated|q_b[31] ; 4 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_dc_data_module:system_cpu_dc_data|altsyncram:the_altsyncram|altsyncram_2jf1:auto_generated|q_b[7] ; 4 ; +; system:inst_cpu|system_cpu:cpu|M_regnum_b_cmp_D ; 4 ; +; system:inst_cpu|system_cpu:cpu|M_regnum_a_cmp_D ; 4 ; +; system:inst_cpu|system_cpu:cpu|F_pc[23] ; 4 ; +; system:inst_cpu|system_cpu:cpu|F_pc[22] ; 4 ; +; system:inst_cpu|system_cpu:cpu|F_pc[21] ; 4 ; +; system:inst_cpu|system_cpu:cpu|F_pc[20] ; 4 ; +; system:inst_cpu|system_cpu:cpu|F_pc[19] ; 4 ; +; system:inst_cpu|system_cpu:cpu|F_pc[18] ; 4 ; +; system:inst_cpu|system_cpu:cpu|F_pc[17] ; 4 ; +; system:inst_cpu|system_cpu:cpu|F_pc[16] ; 4 ; +; system:inst_cpu|system_cpu:cpu|F_pc[15] ; 4 ; +; system:inst_cpu|system_cpu:cpu|F_pc[14] ; 4 ; +; system:inst_cpu|system_cpu:cpu|F_pc[13] ; 4 ; +; system:inst_cpu|system_cpu:cpu|F_pc[12] ; 4 ; +; system:inst_cpu|system_cpu:cpu|F_pc[11] ; 4 ; +; system:inst_cpu|system_cpu:cpu|lpm_add_sub:Add17|add_sub_qvi:auto_generated|result_int[12]~24 ; 4 ; +; system:inst_cpu|system_cpu:cpu|lpm_add_sub:Add17|add_sub_qvi:auto_generated|result_int[11]~22 ; 4 ; +; system:inst_cpu|system_cpu:cpu|lpm_add_sub:Add17|add_sub_qvi:auto_generated|result_int[10]~20 ; 4 ; +; system:inst_cpu|system_cpu:cpu|lpm_add_sub:Add17|add_sub_qvi:auto_generated|result_int[9]~18 ; 4 ; +; system:inst_cpu|system_cpu:cpu|lpm_add_sub:Add17|add_sub_qvi:auto_generated|result_int[8]~16 ; 4 ; +; system:inst_cpu|system_cpu:cpu|lpm_add_sub:Add17|add_sub_qvi:auto_generated|result_int[7]~14 ; 4 ; +; system:inst_cpu|system_cpu:cpu|lpm_add_sub:Add17|add_sub_qvi:auto_generated|result_int[6]~12 ; 4 ; +; system:inst_cpu|system_cpu:cpu|d_address_line_field[3] ; 4 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[0] ; 3 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0] ; 3 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_dr_scan_proc~0 ; 3 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1] ; 3 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]~11 ; 3 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]~4 ; 3 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[7] ; 3 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[5] ; 3 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; 3 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0 ; 3 ; +; system:inst_cpu|system_cpu:cpu|F_iw[14]~37 ; 3 ; +; system:inst_cpu|system_cpu:cpu|av_addr_accepted~2 ; 3 ; +; system:inst_cpu|system_uart_0:uart_0|system_uart_0_rx:the_system_uart_0_rx|delayed_unxsync_rxdxx1 ; 3 ; +; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_rs232_counters:RS232_In_Counters|bit_counter[3] ; 3 ; +; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|usedw_is_1_dff ; 3 ; +; system:inst_cpu|system_uart_0:uart_0|system_uart_0_rx:the_system_uart_0_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[1] ; 3 ; +; system:inst_cpu|system_uart_0:uart_0|system_uart_0_rx:the_system_uart_0_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[2] ; 3 ; +; system:inst_cpu|system_uart_0:uart_0|system_uart_0_rx:the_system_uart_0_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[3] ; 3 ; +; system:inst_cpu|system_uart_0:uart_0|system_uart_0_rx:the_system_uart_0_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[4] ; 3 ; +; system:inst_cpu|system_uart_0:uart_0|system_uart_0_rx:the_system_uart_0_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[5] ; 3 ; +; system:inst_cpu|system_uart_0:uart_0|system_uart_0_rx:the_system_uart_0_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[6] ; 3 ; +; system:inst_cpu|system_uart_0:uart_0|system_uart_0_rx:the_system_uart_0_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[7] ; 3 ; +; system:inst_cpu|system_uart_0:uart_0|system_uart_0_rx:the_system_uart_0_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[8] ; 3 ; +; system:inst_cpu|system_uart_0:uart_0|system_uart_0_rx:the_system_uart_0_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[9] ; 3 ; +; system:inst_cpu|system_uart_0:uart_0|system_uart_0_regs:the_system_uart_0_regs|status_wr_strobe ; 3 ; +; system:inst_cpu|system_sys_clk_timer:sys_clk_timer|counter_is_running ; 3 ; +; system:inst_cpu|system_sys_clk_timer:sys_clk_timer|force_reload ; 3 ; +; system:inst_cpu|system_uart_0:uart_0|system_uart_0_regs:the_system_uart_0_regs|baud_divisor[9] ; 3 ; +; system:inst_cpu|system_uart_0:uart_0|system_uart_0_regs:the_system_uart_0_regs|baud_divisor[8] ; 3 ; +; system:inst_cpu|system_uart_0:uart_0|system_uart_0_regs:the_system_uart_0_regs|baud_divisor[6] ; 3 ; +; system:inst_cpu|system_uart_0:uart_0|system_uart_0_regs:the_system_uart_0_regs|baud_divisor[5] ; 3 ; +; system:inst_cpu|system_uart_0:uart_0|system_uart_0_regs:the_system_uart_0_regs|baud_divisor[2] ; 3 ; +; system:inst_cpu|system_uart_0:uart_0|system_uart_0_regs:the_system_uart_0_regs|baud_divisor[0] ; 3 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|jdo[23] ; 3 ; +; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|empty_dff ; 3 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|readdata[14]~0 ; 3 ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|ien_AE~0 ; 3 ; +; system:inst_cpu|system_cpu:cpu|E_src2_reg[7] ; 3 ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|write1 ; 3 ; +; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[5] ; 3 ; +; system:inst_cpu|system_cpu:cpu|M_st_data[21] ; 3 ; +; system:inst_cpu|system_cpu:cpu|M_st_data[22] ; 3 ; +; system:inst_cpu|system_cpu:cpu|M_st_data[23] ; 3 ; +; system:inst_cpu|system_cpu:cpu|M_st_data[16] ; 3 ; +; system:inst_cpu|system_cpu:cpu|M_st_data[17] ; 3 ; +; system:inst_cpu|system_cpu:cpu|M_st_data[18] ; 3 ; +; system:inst_cpu|system_cpu:cpu|M_st_data[19] ; 3 ; +; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[4] ; 3 ; +; system:inst_cpu|system_cpu:cpu|M_st_data[20] ; 3 ; +; system:inst_cpu|system_cpu:cpu|M_ctrl_exception ; 3 ; +; system:inst_cpu|system_cpu:cpu|A_estatus_reg_pie ; 3 ; +; system:inst_cpu|system_cpu:cpu|A_bstatus_reg_pie ; 3 ; +; system:inst_cpu|system_cpu:cpu|M_wrctl_bstatus~0 ; 3 ; +; system:inst_cpu|system_cpu:cpu|M_iw[8] ; 3 ; +; system:inst_cpu|system_cpu:cpu|M_ctrl_wrctl_inst ; 3 ; +; system:inst_cpu|system_cpu:cpu|M_iw[7] ; 3 ; +; system:inst_cpu|system_sys_clk_timer:sys_clk_timer|timeout_occurred ; 3 ; +; system:inst_cpu|system_cpu:cpu|M_ctrl_crst ; 3 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|jdo[24] ; 3 ; +; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_rs232_counters:RS232_Out_Counters|bit_counter[3] ; 3 ; +; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|usedw_is_1_dff ; 3 ; +; system:inst_cpu|system_uart_0:uart_0|system_uart_0_tx:the_system_uart_0_tx|WideOr0 ; 3 ; +; system:inst_cpu|system_uart_0:uart_0|system_uart_0_tx:the_system_uart_0_tx|baud_clk_en ; 3 ; +; system:inst_cpu|system_cpu:cpu|M_st_data[15] ; 3 ; +; system:inst_cpu|system_cpu:cpu|M_st_data[14] ; 3 ; +; system:inst_cpu|system_cpu:cpu|M_st_data[13] ; 3 ; +; system:inst_cpu|system_cpu:cpu|M_st_data[12] ; 3 ; +; system:inst_cpu|system_cpu:cpu|M_st_data[11] ; 3 ; +; system:inst_cpu|system_cpu:cpu|M_st_data[10] ; 3 ; +; system:inst_cpu|system_cpu:cpu|M_st_data[9] ; 3 ; +; system:inst_cpu|system_cpu:cpu|M_st_data[8] ; 3 ; +; system:inst_cpu|system_cpu:cpu|M_st_data[7] ; 3 ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty ; 3 ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|td_shift~11 ; 3 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|jdo[31] ; 3 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|jdo[30] ; 3 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|jdo[29] ; 3 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|jdo[18] ; 3 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|jdo[19] ; 3 ; +; system:inst_cpu|system_cpu:cpu|d_readdata_d1[29] ; 3 ; +; system:inst_cpu|system_cpu:cpu|d_readdata_d1[21] ; 3 ; +; system:inst_cpu|system_cpu:cpu|d_readdata_d1[30] ; 3 ; +; system:inst_cpu|system_cpu:cpu|d_readdata_d1[22] ; 3 ; +; system:inst_cpu|system_cpu:cpu|d_readdata_d1[7] ; 3 ; +; system:inst_cpu|system_cpu:cpu|d_readdata_d1[15] ; 3 ; +; system:inst_cpu|system_cpu:cpu|d_readdata_d1[24] ; 3 ; +; system:inst_cpu|system_cpu:cpu|d_readdata_d1[16] ; 3 ; +; system:inst_cpu|system_cpu:cpu|d_readdata_d1[25] ; 3 ; +; system:inst_cpu|system_cpu:cpu|d_readdata_d1[17] ; 3 ; +; system:inst_cpu|system_cpu:cpu|d_readdata_d1[26] ; 3 ; +; system:inst_cpu|system_cpu:cpu|d_readdata_d1[18] ; 3 ; +; system:inst_cpu|system_cpu:cpu|d_readdata_d1[27] ; 3 ; +; system:inst_cpu|system_cpu:cpu|d_readdata_d1[19] ; 3 ; +; system:inst_cpu|system_cpu:cpu|A_dc_fill_dp_offset[2] ; 3 ; +; system:inst_cpu|system_cpu:cpu|d_readdata_d1[28] ; 3 ; +; system:inst_cpu|system_cpu:cpu|d_readdata_d1[20] ; 3 ; +; system:inst_cpu|system_cpu:cpu|M_ctrl_ld8 ; 3 ; +; system:inst_cpu|system_cpu:cpu|M_dst_regnum[4] ; 3 ; +; system:inst_cpu|system_cpu:cpu|M_wr_dst_reg_from_E ; 3 ; +; system:inst_cpu|system_cpu:cpu|M_dst_regnum[2] ; 3 ; +; system:inst_cpu|system_cpu:cpu|M_dst_regnum[3] ; 3 ; +; system:inst_cpu|system_cpu:cpu|M_dst_regnum[0] ; 3 ; +; system:inst_cpu|system_cpu:cpu|M_dst_regnum[1] ; 3 ; +; system:inst_cpu|system_cpu:cpu|A_ctrl_st ; 3 ; +; system:inst_cpu|system_cpu:cpu|F_iw[12]~18 ; 3 ; +; system:inst_cpu|system_cpu:cpu|F_iw[13]~16 ; 3 ; +; system:inst_cpu|system_cpu:cpu|F_iw[15]~15 ; 3 ; +; system:inst_cpu|system_cpu:cpu|F_iw[11]~14 ; 3 ; +; system:inst_cpu|system_cpu:cpu|F_iw[4]~12 ; 3 ; +; system:inst_cpu|system_cpu:cpu|F_iw[3]~11 ; 3 ; +; system:inst_cpu|system_cpu:cpu|F_iw[5]~10 ; 3 ; +; system:inst_cpu|system_cpu:cpu|Equal300~1 ; 3 ; +; system:inst_cpu|system_cpu:cpu|D_ctrl_ignore_dst ; 3 ; +; system:inst_cpu|system_cpu:cpu|D_dst_regnum[1]~1 ; 3 ; +; system:inst_cpu|system_cpu:cpu|D_ctrl_implicit_dst_retaddr ; 3 ; +; system:inst_cpu|system_cpu:cpu|F_iw[2]~9 ; 3 ; +; system:inst_cpu|system_cpu:cpu|F_ctrl_implicit_dst_retaddr~8 ; 3 ; +; system:inst_cpu|system_cpu:cpu|E_dst_regnum[4] ; 3 ; +; system:inst_cpu|system_cpu:cpu|E_dst_regnum[2] ; 3 ; +; system:inst_cpu|system_cpu:cpu|E_dst_regnum[3] ; 3 ; +; system:inst_cpu|system_cpu:cpu|E_dst_regnum[0] ; 3 ; +; system:inst_cpu|system_cpu:cpu|E_dst_regnum[1] ; 3 ; +; system:inst_cpu|system_cpu:cpu|E_wr_dst_reg~0 ; 3 ; +; system:inst_cpu|system_cpu:cpu|D_iw[26] ; 3 ; +; system:inst_cpu|system_cpu:cpu|D_iw[25] ; 3 ; +; system:inst_cpu|system_cpu:cpu|D_iw[24] ; 3 ; +; system:inst_cpu|system_cpu:cpu|D_iw[23] ; 3 ; +; system:inst_cpu|system_cpu:cpu|D_iw[22] ; 3 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_debug:the_system_cpu_nios2_oci_debug|monitor_error ; 3 ; +; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_rs232_counters:RS232_Out_Counters|all_bits_transmitted ; 3 ; +; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|empty_dff ; 3 ; +; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_rs232_counters:RS232_Out_Counters|baud_clock_rising_edge ; 3 ; +; system:inst_cpu|system_uart_0:uart_0|system_uart_0_tx:the_system_uart_0_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[1] ; 3 ; +; system:inst_cpu|system_uart_0:uart_0|system_uart_0_tx:the_system_uart_0_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[9] ; 3 ; +; system:inst_cpu|system_uart_0:uart_0|system_uart_0_tx:the_system_uart_0_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[0] ; 3 ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|rst2 ; 3 ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|r_ena1 ; 3 ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|r_val ; 3 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|jdo[25] ; 3 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg|take_action_ocireg~0 ; 3 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|jdo[17] ; 3 ; ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter RAM Summary ; ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+----------------------------------------+-------------------------------------------------------------------------------------------------------------------------------+ +; Name ; Type ; Mode ; Clock Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Port A Input Registers ; Port A Output Registers ; Port B Input Registers ; Port B Output Registers ; Size ; Implementation Port A Depth ; Implementation Port A Width ; Implementation Port B Depth ; Implementation Port B Width ; Implementation Bits ; M9Ks ; MIF ; Location ; ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+----------------------------------------+-------------------------------------------------------------------------------------------------------------------------------+ +; system:inst_cpu|system_cpu:cpu|system_cpu_bht_module:system_cpu_bht|altsyncram:the_altsyncram|altsyncram_fhg1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 256 ; 2 ; 256 ; 2 ; yes ; no ; yes ; yes ; 512 ; 256 ; 2 ; 256 ; 2 ; 512 ; 1 ; system_cpu_bht_ram.mif ; M9K_X33_Y10_N0 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_dc_data_module:system_cpu_dc_data|altsyncram:the_altsyncram|altsyncram_2jf1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Dual Clocks ; 1024 ; 32 ; 1024 ; 32 ; yes ; no ; yes ; no ; 32768 ; 1024 ; 32 ; 1024 ; 32 ; 32768 ; 4 ; None ; M9K_X33_Y19_N0, M9K_X33_Y15_N0, M9K_X33_Y14_N0, M9K_X33_Y18_N0 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_dc_tag_module:system_cpu_dc_tag|altsyncram:the_altsyncram|altsyncram_d9g1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 128 ; 16 ; 128 ; 16 ; yes ; no ; yes ; no ; 2048 ; 128 ; 16 ; 128 ; 16 ; 2048 ; 1 ; system_cpu_dc_tag_ram.mif ; M9K_X33_Y13_N0 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_dc_victim_module:system_cpu_dc_victim|altsyncram:the_altsyncram|altsyncram_r3d1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 8 ; 32 ; 8 ; 32 ; yes ; no ; yes ; no ; 256 ; 8 ; 32 ; 8 ; 32 ; 256 ; 1 ; None ; M9K_X22_Y14_N0 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Dual Clocks ; 2048 ; 32 ; 2048 ; 32 ; yes ; no ; yes ; no ; 65536 ; 2048 ; 32 ; 2048 ; 32 ; 65536 ; 8 ; None ; M9K_X22_Y10_N0, M9K_X22_Y12_N0, M9K_X33_Y12_N0, M9K_X22_Y15_N0, M9K_X22_Y13_N0, M9K_X22_Y11_N0, M9K_X33_Y11_N0, M9K_X22_Y9_N0 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 256 ; 21 ; 256 ; 21 ; yes ; no ; yes ; no ; 5376 ; 256 ; 21 ; 256 ; 21 ; 5376 ; 1 ; system_cpu_ic_tag_ram.mif ; M9K_X33_Y9_N0 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port ; Single Clock ; 256 ; 32 ; 256 ; 32 ; yes ; no ; yes ; no ; 8192 ; 256 ; 32 ; 256 ; 32 ; 8192 ; 2 ; system_cpu_ociram_default_contents.mif ; M9K_X22_Y16_N0, M9K_X22_Y18_N0 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_register_bank_a_module:system_cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_fvf1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 32 ; 32 ; 32 ; 32 ; yes ; no ; yes ; no ; 1024 ; 32 ; 32 ; 32 ; 32 ; 1024 ; 1 ; system_cpu_rf_ram_a.mif ; M9K_X33_Y16_N0 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_register_bank_b_module:system_cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_gvf1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 32 ; 32 ; 32 ; 32 ; yes ; no ; yes ; no ; 1024 ; 32 ; 32 ; 32 ; 32 ; 1024 ; 1 ; system_cpu_rf_ram_b.mif ; M9K_X33_Y17_N0 ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Dual Clocks ; 64 ; 8 ; 64 ; 8 ; yes ; no ; yes ; no ; 512 ; 64 ; 8 ; 64 ; 8 ; 512 ; 1 ; None ; M9K_X22_Y17_N0 ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Dual Clocks ; 64 ; 8 ; 64 ; 8 ; yes ; no ; yes ; yes ; 512 ; 64 ; 8 ; 64 ; 8 ; 512 ; 1 ; None ; M9K_X22_Y20_N0 ; +; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Dual Clocks ; 128 ; 8 ; 128 ; 8 ; yes ; no ; yes ; no ; 1024 ; 128 ; 8 ; 128 ; 8 ; 1024 ; 1 ; None ; M9K_X22_Y21_N0 ; +; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Dual Clocks ; 128 ; 8 ; 128 ; 8 ; yes ; no ; yes ; no ; 1024 ; 128 ; 8 ; 128 ; 8 ; 1024 ; 1 ; None ; M9K_X33_Y21_N0 ; ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+----------------------------------------+-------------------------------------------------------------------------------------------------------------------------------+ +Note: Fitter may spread logical memories into multiple blocks to improve timing. The actual required RAM blocks can be found in the Fitter Resource Usage section. + + ++-----------------------------------------------------------------------------------------------+ +; Fitter DSP Block Usage Summary ; ++---------------------------------------+-------------+---------------------+-------------------+ +; Statistic ; Number Used ; Available per Block ; Maximum Available ; ++---------------------------------------+-------------+---------------------+-------------------+ +; Simple Multipliers (9-bit) ; 0 ; 2 ; 132 ; +; Simple Multipliers (18-bit) ; 2 ; 1 ; 66 ; +; Embedded Multiplier Blocks ; 2 ; -- ; 66 ; +; Embedded Multiplier 9-bit elements ; 4 ; 2 ; 132 ; +; Signed Embedded Multipliers ; 0 ; -- ; -- ; +; Unsigned Embedded Multipliers ; 2 ; -- ; -- ; +; Mixed Sign Embedded Multipliers ; 0 ; -- ; -- ; +; Variable Sign Embedded Multipliers ; 0 ; -- ; -- ; +; Dedicated Input Shift Register Chains ; 0 ; -- ; -- ; ++---------------------------------------+-------------+---------------------+-------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; DSP Block Details ; ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------+--------------------+---------------------+--------------------------------+-----------------------+-----------------------+-------------------+-----------------+ +; Name ; Mode ; Location ; Sign Representation ; Has Input Shift Register Chain ; Data A Input Register ; Data B Input Register ; Pipeline Register ; Output Register ; ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------+--------------------+---------------------+--------------------------------+-----------------------+-----------------------+-------------------+-----------------+ +; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3 ; Simple Multiplier (18-bit) ; DSPOUT_X42_Y18_N2 ; ; No ; ; ; ; yes ; +; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_mult2 ; ; DSPMULT_X42_Y18_N0 ; Unsigned ; ; yes ; yes ; no ; ; +; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3 ; Simple Multiplier (18-bit) ; DSPOUT_X42_Y17_N2 ; ; No ; ; ; ; yes ; +; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated|ded_mult_ks81:ded_mult1|mac_mult2 ; ; DSPMULT_X42_Y17_N0 ; Unsigned ; ; yes ; yes ; no ; ; ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------+--------------------+---------------------+--------------------------------+-----------------------+-----------------------+-------------------+-----------------+ + + ++-------------------------------------------------------+ +; Other Routing Usage Summary ; ++-----------------------------+-------------------------+ +; Other Routing Resource Type ; Usage ; ++-----------------------------+-------------------------+ +; Block interconnects ; 7,231 / 71,559 ( 10 % ) ; +; C16 interconnects ; 62 / 2,597 ( 2 % ) ; +; C4 interconnects ; 3,726 / 46,848 ( 8 % ) ; +; Direct links ; 999 / 71,559 ( 1 % ) ; +; Global clocks ; 8 / 20 ( 40 % ) ; +; Local interconnects ; 2,440 / 24,624 ( 10 % ) ; +; R24 interconnects ; 122 / 2,496 ( 5 % ) ; +; R4 interconnects ; 4,645 / 62,424 ( 7 % ) ; ++-----------------------------+-------------------------+ + + ++-----------------------------------------------------------------------------+ +; LAB Logic Elements ; ++---------------------------------------------+-------------------------------+ +; Number of Logic Elements (Average = 13.58) ; Number of LABs (Total = 336) ; ++---------------------------------------------+-------------------------------+ +; 1 ; 19 ; +; 2 ; 6 ; +; 3 ; 3 ; +; 4 ; 3 ; +; 5 ; 2 ; +; 6 ; 5 ; +; 7 ; 1 ; +; 8 ; 5 ; +; 9 ; 6 ; +; 10 ; 4 ; +; 11 ; 12 ; +; 12 ; 7 ; +; 13 ; 10 ; +; 14 ; 22 ; +; 15 ; 21 ; +; 16 ; 210 ; ++---------------------------------------------+-------------------------------+ + + ++--------------------------------------------------------------------+ +; LAB-wide Signals ; ++------------------------------------+-------------------------------+ +; LAB-wide Signals (Average = 2.68) ; Number of LABs (Total = 336) ; ++------------------------------------+-------------------------------+ +; 1 Async. clear ; 265 ; +; 1 Clock ; 316 ; +; 1 Clock enable ; 172 ; +; 1 Sync. clear ; 22 ; +; 1 Sync. load ; 60 ; +; 2 Async. clears ; 2 ; +; 2 Clock enables ; 58 ; +; 2 Clocks ; 6 ; ++------------------------------------+-------------------------------+ + + ++------------------------------------------------------------------------------+ +; LAB Signals Sourced ; ++----------------------------------------------+-------------------------------+ +; Number of Signals Sourced (Average = 21.51) ; Number of LABs (Total = 336) ; ++----------------------------------------------+-------------------------------+ +; 0 ; 1 ; +; 1 ; 8 ; +; 2 ; 11 ; +; 3 ; 3 ; +; 4 ; 5 ; +; 5 ; 1 ; +; 6 ; 1 ; +; 7 ; 1 ; +; 8 ; 2 ; +; 9 ; 2 ; +; 10 ; 2 ; +; 11 ; 4 ; +; 12 ; 2 ; +; 13 ; 1 ; +; 14 ; 4 ; +; 15 ; 1 ; +; 16 ; 13 ; +; 17 ; 9 ; +; 18 ; 6 ; +; 19 ; 12 ; +; 20 ; 16 ; +; 21 ; 23 ; +; 22 ; 21 ; +; 23 ; 18 ; +; 24 ; 31 ; +; 25 ; 23 ; +; 26 ; 31 ; +; 27 ; 19 ; +; 28 ; 21 ; +; 29 ; 14 ; +; 30 ; 9 ; +; 31 ; 5 ; +; 32 ; 16 ; ++----------------------------------------------+-------------------------------+ + + ++---------------------------------------------------------------------------------+ +; LAB Signals Sourced Out ; ++-------------------------------------------------+-------------------------------+ +; Number of Signals Sourced Out (Average = 9.71) ; Number of LABs (Total = 336) ; ++-------------------------------------------------+-------------------------------+ +; 0 ; 2 ; +; 1 ; 22 ; +; 2 ; 9 ; +; 3 ; 3 ; +; 4 ; 8 ; +; 5 ; 11 ; +; 6 ; 25 ; +; 7 ; 16 ; +; 8 ; 42 ; +; 9 ; 36 ; +; 10 ; 25 ; +; 11 ; 23 ; +; 12 ; 22 ; +; 13 ; 20 ; +; 14 ; 19 ; +; 15 ; 16 ; +; 16 ; 16 ; +; 17 ; 8 ; +; 18 ; 5 ; +; 19 ; 1 ; +; 20 ; 1 ; +; 21 ; 0 ; +; 22 ; 1 ; +; 23 ; 1 ; +; 24 ; 1 ; +; 25 ; 2 ; +; 26 ; 0 ; +; 27 ; 0 ; +; 28 ; 0 ; +; 29 ; 0 ; +; 30 ; 1 ; ++-------------------------------------------------+-------------------------------+ + + ++------------------------------------------------------------------------------+ +; LAB Distinct Inputs ; ++----------------------------------------------+-------------------------------+ +; Number of Distinct Inputs (Average = 18.89) ; Number of LABs (Total = 336) ; ++----------------------------------------------+-------------------------------+ +; 0 ; 0 ; +; 1 ; 2 ; +; 2 ; 8 ; +; 3 ; 11 ; +; 4 ; 5 ; +; 5 ; 7 ; +; 6 ; 6 ; +; 7 ; 7 ; +; 8 ; 8 ; +; 9 ; 4 ; +; 10 ; 7 ; +; 11 ; 7 ; +; 12 ; 10 ; +; 13 ; 8 ; +; 14 ; 11 ; +; 15 ; 10 ; +; 16 ; 16 ; +; 17 ; 13 ; +; 18 ; 18 ; +; 19 ; 14 ; +; 20 ; 16 ; +; 21 ; 22 ; +; 22 ; 8 ; +; 23 ; 8 ; +; 24 ; 12 ; +; 25 ; 6 ; +; 26 ; 11 ; +; 27 ; 5 ; +; 28 ; 12 ; +; 29 ; 11 ; +; 30 ; 12 ; +; 31 ; 9 ; +; 32 ; 14 ; +; 33 ; 9 ; +; 34 ; 7 ; +; 35 ; 0 ; +; 36 ; 0 ; +; 37 ; 1 ; ++----------------------------------------------+-------------------------------+ + + ++------------------------------------------+ +; I/O Rules Summary ; ++----------------------------------+-------+ +; I/O Rules Statistic ; Total ; ++----------------------------------+-------+ +; Total I/O Rules ; 30 ; +; Number of I/O Rules Passed ; 14 ; +; Number of I/O Rules Failed ; 0 ; +; Number of I/O Rules Unchecked ; 0 ; +; Number of I/O Rules Inapplicable ; 16 ; ++----------------------------------+-------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; I/O Rules Details ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ +; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ +; Pass ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ; +; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ; +; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ; +; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Pass ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; +; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Pass ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Pass ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; +; Pass ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Pass ; IO_000033 ; Electromigration Checks ; Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O. ; High ; No Differential I/O Standard assignments found. ; I/O ; ; +; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks ; No more than 20 outputs are allowed in a VREF group when VREF is being read from. ; High ; No VREF I/O Standard assignments found. ; I/O ; ; +; ---- ; ---- ; Disclaimer ; OCT rules are checked but not reported. ; None ; ---- ; On Chip Termination ; ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; I/O Rules Matrix ; ++---------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+ +; Pin/Rules ; IO_000001 ; IO_000002 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000009 ; IO_000010 ; IO_000011 ; IO_000012 ; IO_000013 ; IO_000014 ; IO_000015 ; IO_000018 ; IO_000019 ; IO_000020 ; IO_000021 ; IO_000022 ; IO_000023 ; IO_000024 ; IO_000026 ; IO_000027 ; IO_000045 ; IO_000046 ; IO_000047 ; IO_000033 ; IO_000034 ; IO_000042 ; ++---------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+ +; Total Pass ; 122 ; 37 ; 122 ; 0 ; 0 ; 126 ; 122 ; 0 ; 126 ; 126 ; 0 ; 115 ; 0 ; 0 ; 91 ; 0 ; 115 ; 91 ; 0 ; 0 ; 65 ; 115 ; 0 ; 0 ; 0 ; 0 ; 0 ; 126 ; 0 ; 0 ; +; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; Total Inapplicable ; 4 ; 89 ; 4 ; 126 ; 126 ; 0 ; 4 ; 126 ; 0 ; 0 ; 126 ; 11 ; 126 ; 126 ; 35 ; 126 ; 11 ; 35 ; 126 ; 126 ; 61 ; 11 ; 126 ; 126 ; 126 ; 126 ; 126 ; 0 ; 126 ; 126 ; +; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; DRAM_CLK ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; DRAM_CKE ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; DRAM_CS_N ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; DRAM_RAS_N ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; DRAM_CAS_N ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; DRAM_WE_N ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; DRAM_DQM[0] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; DRAM_DQM[1] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; DRAM_ADDR[0] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; DRAM_ADDR[1] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; DRAM_ADDR[2] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; DRAM_ADDR[3] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; DRAM_ADDR[4] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; DRAM_ADDR[5] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; DRAM_ADDR[6] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; DRAM_ADDR[7] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; DRAM_ADDR[8] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; DRAM_ADDR[9] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; DRAM_ADDR[10] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; DRAM_ADDR[11] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; DRAM_ADDR[12] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; DRAM_BA[0] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; DRAM_BA[1] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LED[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LED[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LED[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LED[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LED[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LED[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LED[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LED[7] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_0[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_0[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_0[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_0[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_0[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_0[7] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_0[8] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_0[9] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_0[10] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_0[11] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_0[12] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_0[13] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_0[14] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_0[15] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_0[16] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_0[17] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_0[18] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_0[19] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_0[20] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_0[21] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_0[22] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_0[23] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_0[24] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_0[25] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_0[26] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_0[27] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_0[28] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_0[29] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_0[30] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_0[31] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_0[32] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_0[33] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_1[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_1[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_1[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_1[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_1[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_1[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_1[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_1[7] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_1[8] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_1[9] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_1[10] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_1[11] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_1[13] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_1[14] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_1[15] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_1[16] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_1[17] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_1[18] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_1[19] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_1[20] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_1[21] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_1[22] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_1[23] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_1[25] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_1[27] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_1[28] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_1[29] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_1[30] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_1[31] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_1[32] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_1[33] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; DRAM_DQ[0] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; DRAM_DQ[1] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; DRAM_DQ[2] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; DRAM_DQ[3] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; DRAM_DQ[4] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; DRAM_DQ[5] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; DRAM_DQ[6] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; DRAM_DQ[7] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; DRAM_DQ[8] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; DRAM_DQ[9] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; DRAM_DQ[10] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; DRAM_DQ[11] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; DRAM_DQ[12] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; DRAM_DQ[13] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; DRAM_DQ[14] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; DRAM_DQ[15] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_0[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_0[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_1[12] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_1[24] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; GPIO_1[26] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; CLOCK_50 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SW[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SW[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SW[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; KEY[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; KEY[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SW[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; altera_reserved_tms ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; altera_reserved_tck ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; altera_reserved_tdi ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; altera_reserved_tdo ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; ++---------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+ + + ++---------------------------------------------------------------------------------------------+ +; Fitter Device Options ; ++------------------------------------------------------------------+--------------------------+ +; Option ; Setting ; ++------------------------------------------------------------------+--------------------------+ +; Enable user-supplied start-up clock (CLKUSR) ; Off ; +; Enable device-wide reset (DEV_CLRn) ; Off ; +; Enable device-wide output enable (DEV_OE) ; Off ; +; Enable INIT_DONE output ; Off ; +; Configuration scheme ; Active Serial ; +; Error detection CRC ; Off ; +; Enable open drain on CRC_ERROR pin ; Off ; +; Enable input tri-state on active configuration pins in user mode ; Off ; +; Configuration Voltage Level ; Auto ; +; Force Configuration Voltage Level ; Off ; +; nCEO ; As output driving ground ; +; Data[0] ; As input tri-stated ; +; Data[1]/ASDO ; As input tri-stated ; +; Data[7..2] ; Unreserved ; +; FLASH_nCE/nCSO ; As input tri-stated ; +; Other Active Parallel pins ; Unreserved ; +; DCLK ; As output driving ground ; +; Base pin-out file on sameframe device ; Off ; ++------------------------------------------------------------------+--------------------------+ + + ++------------------------------------+ +; Operating Settings and Conditions ; ++---------------------------+--------+ +; Setting ; Value ; ++---------------------------+--------+ +; Nominal Core Voltage ; 1.20 V ; +; Low Junction Temperature ; 0 °C ; +; High Junction Temperature ; 85 °C ; ++---------------------------+--------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------+ +; Estimated Delay Added for Hold Timing Summary ; ++----------------------------------------------------------+----------------------------------------------------------+-------------------+ +; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ; ++----------------------------------------------------------+----------------------------------------------------------+-------------------+ +; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 8.3 ; ++----------------------------------------------------------+----------------------------------------------------------+-------------------+ +Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off. +This will disable optimization of problematic paths and expose them for further analysis using either the TimeQuest Timing Analyzer or the Classic Timing Analyzer. + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Estimated Delay Added for Hold Timing Details ; ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+ +; Source Register ; Destination Register ; Delay Added in ns ; ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+ +; system:inst_cpu|system_cpu:cpu|i_readdata_d1[14] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a14~porta_datain_reg0 ; 0.228 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[31] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a31~portb_datain_reg0 ; 0.222 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[26] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a26~portb_datain_reg0 ; 0.222 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[25] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a25~portb_datain_reg0 ; 0.222 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[8] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_datain_reg0 ; 0.222 ; +; system:inst_cpu|system_rs232_motor:rs232_motor|data_to_uart[1] ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a1~porta_datain_reg0 ; 0.217 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[30] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a30~portb_datain_reg0 ; 0.212 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[29] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a29~portb_datain_reg0 ; 0.212 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[28] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a28~portb_datain_reg0 ; 0.212 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[27] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a27~portb_datain_reg0 ; 0.212 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[13] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a13~portb_datain_reg0 ; 0.212 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[15] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a15~portb_datain_reg0 ; 0.212 ; +; system:inst_cpu|system_cpu:cpu|M_bht_ptr_unfiltered[7] ; system:inst_cpu|system_cpu:cpu|system_cpu_bht_module:system_cpu_bht|altsyncram:the_altsyncram|altsyncram_fhg1:auto_generated|ram_block1a1~porta_address_reg0 ; 0.201 ; +; system:inst_cpu|system_cpu:cpu|M_bht_ptr_unfiltered[3] ; system:inst_cpu|system_cpu:cpu|system_cpu_bht_module:system_cpu_bht|altsyncram:the_altsyncram|altsyncram_fhg1:auto_generated|ram_block1a1~porta_address_reg0 ; 0.201 ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[5] ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_address_reg0 ; 0.200 ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[1] ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_address_reg0 ; 0.200 ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[2] ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_address_reg0 ; 0.200 ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[3] ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_address_reg0 ; 0.200 ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[4] ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_address_reg0 ; 0.200 ; +; system:inst_cpu|system_cpu:cpu|ic_fill_line[3] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a21~porta_address_reg0 ; 0.200 ; +; system:inst_cpu|system_cpu:cpu|ic_fill_line[2] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a21~porta_address_reg0 ; 0.200 ; +; system:inst_cpu|system_cpu:cpu|ic_fill_tag[3] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a11~porta_datain_reg0 ; 0.156 ; +; system:inst_cpu|system_cpu:cpu|ic_fill_tag[1] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a9~porta_datain_reg0 ; 0.156 ; +; system:inst_cpu|system_cpu:cpu|ic_fill_tag[8] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a16~porta_datain_reg0 ; 0.146 ; +; system:inst_cpu|system_cpu:cpu|ic_fill_tag[6] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a14~porta_datain_reg0 ; 0.146 ; +; system:inst_cpu|system_cpu:cpu|ic_fill_tag[7] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a15~porta_datain_reg0 ; 0.146 ; +; system:inst_cpu|system_cpu:cpu|ic_fill_tag[4] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a12~porta_datain_reg0 ; 0.146 ; +; system:inst_cpu|system_cpu:cpu|ic_fill_tag[5] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a13~porta_datain_reg0 ; 0.146 ; +; system:inst_cpu|system_cpu:cpu|ic_fill_tag[2] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a10~porta_datain_reg0 ; 0.146 ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[5] ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_address_reg0 ; 0.130 ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[0] ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_address_reg0 ; 0.128 ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[0] ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_address_reg0 ; 0.128 ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[1] ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_address_reg0 ; 0.128 ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[2] ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_address_reg0 ; 0.128 ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[3] ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_address_reg0 ; 0.128 ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[4] ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_address_reg0 ; 0.128 ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:rd_ptr_count|counter_reg_bit[0] ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~portb_address_reg0 ; 0.120 ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:rd_ptr_count|counter_reg_bit[5] ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~portb_address_reg0 ; 0.119 ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:rd_ptr_count|counter_reg_bit[1] ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~portb_address_reg0 ; 0.119 ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:rd_ptr_count|counter_reg_bit[2] ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~portb_address_reg0 ; 0.119 ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:rd_ptr_count|counter_reg_bit[3] ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~portb_address_reg0 ; 0.119 ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:rd_ptr_count|counter_reg_bit[4] ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~portb_address_reg0 ; 0.119 ; +; system:inst_cpu|system_cpu:cpu|M_ctrl_ld_st ; system:inst_cpu|system_cpu:cpu|M_valid_mem_d1 ; 0.024 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|jdo[37] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_break:the_system_cpu_nios2_oci_break|break_readreg[1] ; 0.024 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|jdo[37] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_break:the_system_cpu_nios2_oci_break|break_readreg[11] ; 0.024 ; +; system:inst_cpu|system_uart_0:uart_0|system_uart_0_regs:the_system_uart_0_regs|tx_data[7] ; system:inst_cpu|system_uart_0:uart_0|system_uart_0_tx:the_system_uart_0_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[8] ; 0.023 ; +; system:inst_cpu|system_uart_0:uart_0|system_uart_0_regs:the_system_uart_0_regs|tx_data[6] ; system:inst_cpu|system_uart_0:uart_0|system_uart_0_tx:the_system_uart_0_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[7] ; 0.023 ; +; system:inst_cpu|system_uart_0:uart_0|system_uart_0_regs:the_system_uart_0_regs|tx_data[5] ; system:inst_cpu|system_uart_0:uart_0|system_uart_0_tx:the_system_uart_0_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[6] ; 0.023 ; +; system:inst_cpu|system_uart_0:uart_0|system_uart_0_regs:the_system_uart_0_regs|tx_data[4] ; system:inst_cpu|system_uart_0:uart_0|system_uart_0_tx:the_system_uart_0_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[5] ; 0.023 ; +; system:inst_cpu|system_uart_0:uart_0|system_uart_0_regs:the_system_uart_0_regs|tx_data[2] ; system:inst_cpu|system_uart_0:uart_0|system_uart_0_tx:the_system_uart_0_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[3] ; 0.023 ; +; system:inst_cpu|system_uart_0:uart_0|system_uart_0_regs:the_system_uart_0_regs|tx_data[1] ; system:inst_cpu|system_uart_0:uart_0|system_uart_0_tx:the_system_uart_0_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[2] ; 0.023 ; +; system:inst_cpu|system_uart_0:uart_0|system_uart_0_regs:the_system_uart_0_regs|tx_data[0] ; system:inst_cpu|system_uart_0:uart_0|system_uart_0_tx:the_system_uart_0_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[1] ; 0.023 ; +; system:inst_cpu|system_cpu:cpu|i_readdata_d1[11] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a11~porta_datain_reg0 ; 0.023 ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[2][55] ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][55] ; 0.023 ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[6][55] ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][55] ; 0.023 ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[2][83] ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][83] ; 0.023 ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[6][83] ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][83] ; 0.023 ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[2][56] ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][56] ; 0.023 ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[6][56] ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][56] ; 0.023 ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[2][53] ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][53] ; 0.023 ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[6][53] ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][53] ; 0.023 ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[2][19] ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][19] ; 0.023 ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[6][19] ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][19] ; 0.023 ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[2][84] ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][84] ; 0.023 ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[6][84] ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][84] ; 0.023 ; +; system:inst_cpu|system_cpu:cpu|A_dc_rd_data[6] ; system:inst_cpu|system_cpu:cpu|A_dc_xfer_wr_data[6] ; 0.022 ; +; system:inst_cpu|system_cpu:cpu|A_dc_rd_data[22] ; system:inst_cpu|system_cpu:cpu|A_dc_xfer_wr_data[22] ; 0.022 ; +; system:inst_cpu|system_cpu:cpu|A_dc_rd_data[2] ; system:inst_cpu|system_cpu:cpu|A_dc_xfer_wr_data[2] ; 0.022 ; +; system:inst_cpu|system_cpu:cpu|A_dc_rd_data[3] ; system:inst_cpu|system_cpu:cpu|A_dc_xfer_wr_data[3] ; 0.022 ; +; system:inst_cpu|system_cpu:cpu|A_dc_rd_data[21] ; system:inst_cpu|system_cpu:cpu|A_dc_xfer_wr_data[21] ; 0.022 ; +; system:inst_cpu|system_cpu:cpu|A_dc_rd_data[25] ; system:inst_cpu|system_cpu:cpu|A_dc_xfer_wr_data[25] ; 0.022 ; +; system:inst_cpu|system_cpu:cpu|A_dc_rd_data[28] ; system:inst_cpu|system_cpu:cpu|A_dc_xfer_wr_data[28] ; 0.022 ; +; system:inst_cpu|system_cpu:cpu|A_dc_rd_data[20] ; system:inst_cpu|system_cpu:cpu|A_dc_xfer_wr_data[20] ; 0.022 ; +; system:inst_cpu|system_cpu:cpu|A_dc_rd_data[18] ; system:inst_cpu|system_cpu:cpu|A_dc_xfer_wr_data[18] ; 0.022 ; +; system:inst_cpu|system_cpu:cpu|A_dc_rd_data[17] ; system:inst_cpu|system_cpu:cpu|A_dc_xfer_wr_data[17] ; 0.022 ; +; system:inst_cpu|system_cpu:cpu|A_dc_rd_data[23] ; system:inst_cpu|system_cpu:cpu|A_dc_xfer_wr_data[23] ; 0.022 ; +; system:inst_cpu|system_cpu:cpu|A_dc_rd_data[15] ; system:inst_cpu|system_cpu:cpu|A_dc_xfer_wr_data[15] ; 0.022 ; +; system:inst_cpu|system_cpu:cpu|A_dc_rd_data[31] ; system:inst_cpu|system_cpu:cpu|A_dc_xfer_wr_data[31] ; 0.022 ; +; system:inst_cpu|system_cpu:cpu|A_dc_rd_data[16] ; system:inst_cpu|system_cpu:cpu|A_dc_xfer_wr_data[16] ; 0.022 ; +; system:inst_cpu|system_cpu:cpu|ic_fill_valid_bits[7] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a7~porta_datain_reg0 ; 0.021 ; +; system:inst_cpu|system_cpu:cpu|ic_fill_valid_bits[4] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a4~porta_datain_reg0 ; 0.021 ; +; system:inst_cpu|system_cpu:cpu|ic_fill_valid_bits[6] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a6~porta_datain_reg0 ; 0.021 ; +; system:inst_cpu|system_rs232_motor:rs232_motor|data_to_uart[7] ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a7~porta_datain_reg0 ; 0.021 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|jdo[1] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_break:the_system_cpu_nios2_oci_break|break_readreg[1] ; 0.021 ; +; system:inst_cpu|system_rs232_motor:rs232_motor|write_interrupt_en ; system:inst_cpu|system_rs232_motor:rs232_motor|write_interrupt ; 0.021 ; +; system:inst_cpu|system_cpu:cpu|D_iw[15] ; system:inst_cpu|system_cpu:cpu|E_ctrl_crst ; 0.021 ; +; system:inst_cpu|system_cpu:cpu|ic_fill_valid_bits[3] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a3~porta_datain_reg0 ; 0.021 ; +; system:inst_cpu|system_cpu:cpu|ic_fill_valid_bits[1] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a1~porta_datain_reg0 ; 0.021 ; +; system:inst_cpu|system_cpu:cpu|ic_fill_valid_bits[0] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; 0.017 ; +; system:inst_cpu|system_cpu:cpu|ic_fill_valid_bits[2] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a2~porta_datain_reg0 ; 0.017 ; +; system:inst_cpu|system_rs232_motor:rs232_motor|data_to_uart[3] ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a3~porta_datain_reg0 ; 0.017 ; +; system:inst_cpu|system_uart_0:uart_0|system_uart_0_rx:the_system_uart_0_rx|altera_std_synchronizer:the_altera_std_synchronizer|dreg[0] ; system:inst_cpu|system_uart_0:uart_0|system_uart_0_rx:the_system_uart_0_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[9] ; 0.012 ; ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+ +Note: This table only shows the top 100 paths that have the largest delay added for hold. + + ++-----------------+ +; Fitter Messages ; ++-----------------+ +Info: ******************************************************************* +Info: Running Quartus II 64-Bit Fitter + Info: Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Full Version + Info: Processing started: Fri Mar 14 16:48:52 2014 +Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off de0_nano_system -c de0_nano_system +Info (11104): Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead. +Info (119006): Selected device EP4CE22F17C6 for design "de0_nano_system" +Info (21077): Core supply voltage is 1.2V +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Info (15535): Implemented PLL "pll_sys:inst_pll_sys|altpll:altpll_component|pll_sys_altpll:auto_generated|pll1" as Cyclone IV E PLL type + Info (15099): Implementing clock multiplication of 2, clock division of 1, and phase shift of 0 degrees (0 ps) for pll_sys:inst_pll_sys|altpll:altpll_component|pll_sys_altpll:auto_generated|wire_pll1_clk[0] port + Info (15099): Implementing clock multiplication of 2, clock division of 1, and phase shift of -54 degrees (-1500 ps) for pll_sys:inst_pll_sys|altpll:altpll_component|pll_sys_altpll:auto_generated|wire_pll1_clk[1] port + Info (15099): Implementing clock multiplication of 1, clock division of 5, and phase shift of 0 degrees (0 ps) for pll_sys:inst_pll_sys|altpll:altpll_component|pll_sys_altpll:auto_generated|wire_pll1_clk[2] port +Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time +Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices + Info (176445): Device EP4CE10F17C6 is compatible + Info (176445): Device EP4CE6F17C6 is compatible + Info (176445): Device EP4CE15F17C6 is compatible +Info (169124): Fitter converted 5 user pins into dedicated programming pins + Info (169125): Pin ~ALTERA_ASDO_DATA1~ is reserved at location C1 + Info (169125): Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location D2 + Info (169125): Pin ~ALTERA_DCLK~ is reserved at location H1 + Info (169125): Pin ~ALTERA_DATA0~ is reserved at location H2 + Info (169125): Pin ~ALTERA_nCEO~ is reserved at location F16 +Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details +Info (176045): Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements. +Info (332164): Evaluating HDL-embedded SDC commands + Info (332165): Entity alt_jtag_atlantic + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|jupdate}] -to [get_registers {*|alt_jtag_atlantic:*|jupdate1*}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|read}] -to [get_registers {*|alt_jtag_atlantic:*|read1*}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|read_req}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rvalid}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] + Info (332166): set_false_path -from [get_registers {*|t_dav}] -to [get_registers {*|alt_jtag_atlantic:*|tck_t_dav}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|user_saw_rvalid}] -to [get_registers {*|alt_jtag_atlantic:*|rvalid0*}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write}] -to [get_registers {*|alt_jtag_atlantic:*|write1*}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write_stalled}] -to [get_registers {*|alt_jtag_atlantic:*|t_ena*}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write_stalled}] -to [get_registers {*|alt_jtag_atlantic:*|t_pause*}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write_valid}] + Info (332165): Entity altera_std_synchronizer + Info (332166): set_false_path -to [get_keepers {*altera_std_synchronizer:*|din_s1}] + Info (332165): Entity sld_jtag_hub + Info (332166): create_clock -period 10MHz -name altera_reserved_tck [get_ports {altera_reserved_tck}] + Info (332166): set_clock_groups -asynchronous -group {altera_reserved_tck} +Info (332104): Reading SDC File: 'de0_nano_system.sdc' +Warning (332043): Overwriting existing clock: altera_reserved_tck +Info (332110): Deriving PLL clocks + Info (332110): create_generated_clock -source {inst_pll_sys|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 2 -duty_cycle 50.00 -name {inst_pll_sys|altpll_component|auto_generated|pll1|clk[0]} {inst_pll_sys|altpll_component|auto_generated|pll1|clk[0]} + Info (332110): create_generated_clock -source {inst_pll_sys|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 2 -phase -54.00 -duty_cycle 50.00 -name {inst_pll_sys|altpll_component|auto_generated|pll1|clk[1]} {inst_pll_sys|altpll_component|auto_generated|pll1|clk[1]} + Info (332110): create_generated_clock -source {inst_pll_sys|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 5 -duty_cycle 50.00 -name {inst_pll_sys|altpll_component|auto_generated|pll1|clk[2]} {inst_pll_sys|altpll_component|auto_generated|pll1|clk[2]} +Info (332151): Clock uncertainty is not calculated until you update the timing netlist. +Info (332104): Reading SDC File: 'system/synthesis/submodules/altera_reset_controller.sdc' +Info (332104): Reading SDC File: 'system/synthesis/submodules/system_cpu.sdc' +Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers. +Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements +Info (332111): Found 5 clocks + Info (332111): Period Clock Name + Info (332111): ======== ============ + Info (332111): 100.000 altera_reserved_tck + Info (332111): 20.000 CLOCK_50 + Info (332111): 10.000 inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] + Info (332111): 10.000 inst_pll_sys|altpll_component|auto_generated|pll1|clk[1] + Info (332111): 100.000 inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] +Info (176353): Automatically promoted node pll_sys:inst_pll_sys|altpll:altpll_component|pll_sys_altpll:auto_generated|wire_pll1_clk[0] (placed in counter C0 of PLL_4) + Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G18 +Info (176353): Automatically promoted node pll_sys:inst_pll_sys|altpll:altpll_component|pll_sys_altpll:auto_generated|wire_pll1_clk[1] (placed in counter C2 of PLL_4) + Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G17 +Info (176353): Automatically promoted node pll_sys:inst_pll_sys|altpll:altpll_component|pll_sys_altpll:auto_generated|wire_pll1_clk[2] (placed in counter C1 of PLL_4) + Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G19 +Info (176353): Automatically promoted node altera_internal_jtag~TCKUTAP + Info (176355): Automatically promoted destinations to use location or clock signal Global Clock +Info (176353): Automatically promoted node system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out + Info (176355): Automatically promoted destinations to use location or clock signal Global Clock + Info (176356): Following destination nodes may be non-global or may not use global or regional clocks + Info (176357): Destination node system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[6] + Info (176357): Destination node system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[5] + Info (176357): Destination node system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[4] + Info (176357): Destination node system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[3] + Info (176357): Destination node system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[2] + Info (176357): Destination node system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[1] + Info (176357): Destination node system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[0] + Info (176357): Destination node system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_ca7:usedw_counter|counter_reg_bit[6] + Info (176357): Destination node system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_ca7:usedw_counter|counter_reg_bit[5] + Info (176357): Destination node system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_ca7:usedw_counter|counter_reg_bit[4] + Info (176358): Non-global destination nodes limited to 10 nodes +Info (176353): Automatically promoted node sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg + Info (176355): Automatically promoted destinations to use location or clock signal Global Clock + Info (176356): Following destination nodes may be non-global or may not use global or regional clocks + Info (176357): Destination node sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg~_wirecell +Info (176353): Automatically promoted node sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] + Info (176355): Automatically promoted destinations to use location or clock signal Global Clock + Info (176356): Following destination nodes may be non-global or may not use global or regional clocks + Info (176357): Destination node sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state~0 + Info (176357): Destination node sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state~1 + Info (176357): Destination node sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0]~_wirecell +Info (176353): Automatically promoted node system:inst_cpu|altera_reset_controller:rst_controller|merged_reset~0 + Info (176355): Automatically promoted destinations to use location or clock signal Global Clock +Info (176233): Starting register packing +Warning (176250): Ignoring invalid fast I/O register assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information. +Warning (176251): Ignoring some wildcard destinations of fast I/O register assignments + Info (176252): Wildcard assignment "Fast Output Enable Register=ON" to "oe" matches multiple destination nodes -- some destinations are not valid targets for this assignment + Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_data[9]" matches multiple destination nodes -- some destinations are not valid targets for this assignment + Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_data[8]" matches multiple destination nodes -- some destinations are not valid targets for this assignment + Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_data[7]" matches multiple destination nodes -- some destinations are not valid targets for this assignment + Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_data[6]" matches multiple destination nodes -- some destinations are not valid targets for this assignment + Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_data[5]" matches multiple destination nodes -- some destinations are not valid targets for this assignment + Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_data[4]" matches multiple destination nodes -- some destinations are not valid targets for this assignment + Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_data[3]" matches multiple destination nodes -- some destinations are not valid targets for this assignment + Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_data[2]" matches multiple destination nodes -- some destinations are not valid targets for this assignment + Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_data[1]" matches multiple destination nodes -- some destinations are not valid targets for this assignment + Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_data[15]" matches multiple destination nodes -- some destinations are not valid targets for this assignment + Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_data[14]" matches multiple destination nodes -- some destinations are not valid targets for this assignment + Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_data[13]" matches multiple destination nodes -- some destinations are not valid targets for this assignment + Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_data[12]" matches multiple destination nodes -- some destinations are not valid targets for this assignment + Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_data[11]" matches multiple destination nodes -- some destinations are not valid targets for this assignment + Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_data[10]" matches multiple destination nodes -- some destinations are not valid targets for this assignment + Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_data[0]" matches multiple destination nodes -- some destinations are not valid targets for this assignment + Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_cmd[2]" matches multiple destination nodes -- some destinations are not valid targets for this assignment + Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_cmd[1]" matches multiple destination nodes -- some destinations are not valid targets for this assignment + Info (176252): Wildcard assignment "Fast Output Register=ON" to "m_cmd[0]" matches multiple destination nodes -- some destinations are not valid targets for this assignment +Info (176235): Finished register packing + Extra Info (176218): Packed 10 registers into blocks of type EC + Extra Info (176218): Packed 64 registers into blocks of type Embedded multiplier block + Extra Info (176218): Packed 16 registers into blocks of type I/O Input Buffer + Extra Info (176218): Packed 53 registers into blocks of type I/O Output Buffer + Extra Info (176220): Created 66 register duplicates +Warning (15064): PLL "pll_sys:inst_pll_sys|altpll:altpll_component|pll_sys_altpll:auto_generated|pll1" output port clk[1] feeds output pin "DRAM_CLK~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance +Warning (15705): Ignored locations or region assignments to the following nodes + Warning (15706): Node "ADC_CS_N" is assigned to location or region, but does not exist in design + Warning (15706): Node "ADC_SADDR" is assigned to location or region, but does not exist in design + Warning (15706): Node "ADC_SCLK" is assigned to location or region, but does not exist in design + Warning (15706): Node "ADC_SDAT" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_0_IN[0]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_0_IN[1]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_1_IN[0]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_1_IN[1]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_2[0]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_2[10]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_2[11]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_2[12]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_2[1]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_2[2]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_2[3]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_2[4]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_2[5]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_2[6]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_2[7]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_2[8]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_2[9]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_2_IN[0]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_2_IN[1]" is assigned to location or region, but does not exist in design + Warning (15706): Node "GPIO_2_IN[2]" is assigned to location or region, but does not exist in design + Warning (15706): Node "G_SENSOR_CS_N" is assigned to location or region, but does not exist in design + Warning (15706): Node "G_SENSOR_INT" is assigned to location or region, but does not exist in design + Warning (15706): Node "I2C_SCLK" is assigned to location or region, but does not exist in design + Warning (15706): Node "I2C_SDAT" is assigned to location or region, but does not exist in design +Info (171121): Fitter preparation operations ending: elapsed time is 00:00:11 +Info (170189): Fitter placement preparation operations beginning +Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:02 +Info (170191): Fitter placement operations beginning +Info (170137): Fitter placement was successful +Info (170192): Fitter placement operations ending: elapsed time is 00:00:07 +Info (170193): Fitter routing operations beginning +Info (170195): Router estimated average interconnect usage is 6% of the available device resources + Info (170196): Router estimated peak interconnect usage is 29% of the available device resources in the region that extends from location X21_Y11 to location X31_Y22 +Info (170194): Fitter routing operations ending: elapsed time is 00:00:08 +Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. + Info (170201): Optimizations that may affect the design's routability were skipped + Info (170200): Optimizations that may affect the design's timing were skipped +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:04 +Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information. +Warning (169064): Following 68 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results + Info (169065): Pin GPIO_0[2] has a permanently disabled output enable + Info (169065): Pin GPIO_0[3] has a permanently disabled output enable + Info (169065): Pin GPIO_0[4] has a permanently disabled output enable + Info (169065): Pin GPIO_0[5] has a permanently disabled output enable + Info (169065): Pin GPIO_0[6] has a permanently disabled output enable + Info (169065): Pin GPIO_0[7] has a permanently disabled output enable + Info (169065): Pin GPIO_0[8] has a permanently disabled output enable + Info (169065): Pin GPIO_0[9] has a permanently disabled output enable + Info (169065): Pin GPIO_0[10] has a permanently disabled output enable + Info (169065): Pin GPIO_0[11] has a permanently disabled output enable + Info (169065): Pin GPIO_0[12] has a permanently disabled output enable + Info (169065): Pin GPIO_0[13] has a permanently disabled output enable + Info (169065): Pin GPIO_0[14] has a permanently disabled output enable + Info (169065): Pin GPIO_0[15] has a permanently disabled output enable + Info (169065): Pin GPIO_0[16] has a permanently disabled output enable + Info (169065): Pin GPIO_0[17] has a permanently disabled output enable + Info (169065): Pin GPIO_0[18] has a permanently disabled output enable + Info (169065): Pin GPIO_0[19] has a permanently disabled output enable + Info (169065): Pin GPIO_0[20] has a permanently disabled output enable + Info (169065): Pin GPIO_0[21] has a permanently disabled output enable + Info (169065): Pin GPIO_0[22] has a permanently disabled output enable + Info (169065): Pin GPIO_0[23] has a permanently disabled output enable + Info (169065): Pin GPIO_0[24] has a permanently disabled output enable + Info (169065): Pin GPIO_0[25] has a permanently disabled output enable + Info (169065): Pin GPIO_0[26] has a permanently disabled output enable + Info (169065): Pin GPIO_0[27] has a permanently disabled output enable + Info (169065): Pin GPIO_0[28] has a permanently disabled output enable + Info (169065): Pin GPIO_0[29] has a permanently disabled output enable + Info (169065): Pin GPIO_0[30] has a permanently disabled output enable + Info (169065): Pin GPIO_0[31] has a permanently disabled output enable + Info (169065): Pin GPIO_0[32] has a permanently disabled output enable + Info (169065): Pin GPIO_0[33] has a permanently disabled output enable + Info (169065): Pin GPIO_1[0] has a permanently disabled output enable + Info (169065): Pin GPIO_1[1] has a permanently disabled output enable + Info (169065): Pin GPIO_1[2] has a permanently disabled output enable + Info (169065): Pin GPIO_1[3] has a permanently disabled output enable + Info (169065): Pin GPIO_1[4] has a permanently disabled output enable + Info (169065): Pin GPIO_1[5] has a permanently disabled output enable + Info (169065): Pin GPIO_1[6] has a permanently disabled output enable + Info (169065): Pin GPIO_1[7] has a permanently disabled output enable + Info (169065): Pin GPIO_1[8] has a permanently disabled output enable + Info (169065): Pin GPIO_1[9] has a permanently disabled output enable + Info (169065): Pin GPIO_1[10] has a permanently disabled output enable + Info (169065): Pin GPIO_1[11] has a permanently disabled output enable + Info (169065): Pin GPIO_1[13] has a permanently disabled output enable + Info (169065): Pin GPIO_1[14] has a permanently disabled output enable + Info (169065): Pin GPIO_1[15] has a permanently disabled output enable + Info (169065): Pin GPIO_1[16] has a permanently disabled output enable + Info (169065): Pin GPIO_1[17] has a permanently disabled output enable + Info (169065): Pin GPIO_1[18] has a permanently disabled output enable + Info (169065): Pin GPIO_1[19] has a permanently disabled output enable + Info (169065): Pin GPIO_1[20] has a permanently disabled output enable + Info (169065): Pin GPIO_1[21] has a permanently disabled output enable + Info (169065): Pin GPIO_1[22] has a permanently disabled output enable + Info (169065): Pin GPIO_1[23] has a permanently disabled output enable + Info (169065): Pin GPIO_1[25] has a permanently disabled output enable + Info (169065): Pin GPIO_1[27] has a permanently disabled output enable + Info (169065): Pin GPIO_1[28] has a permanently disabled output enable + Info (169065): Pin GPIO_1[29] has a permanently disabled output enable + Info (169065): Pin GPIO_1[30] has a permanently disabled output enable + Info (169065): Pin GPIO_1[31] has a permanently disabled output enable + Info (169065): Pin GPIO_1[32] has a permanently disabled output enable + Info (169065): Pin GPIO_1[33] has a permanently disabled output enable + Info (169065): Pin GPIO_0[0] has a permanently enabled output enable + Info (169065): Pin GPIO_0[1] has a permanently disabled output enable + Info (169065): Pin GPIO_1[12] has a permanently enabled output enable + Info (169065): Pin GPIO_1[24] has a permanently disabled output enable + Info (169065): Pin GPIO_1[26] has a permanently enabled output enable +Info (144001): Generated suppressed messages file C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/output_files/de0_nano_system.fit.smsg +Info: Quartus II 64-Bit Fitter was successful. 0 errors, 36 warnings + Info: Peak virtual memory: 1130 megabytes + Info: Processing ended: Fri Mar 14 16:49:32 2014 + Info: Elapsed time: 00:00:40 + Info: Total CPU time (on all processors): 00:00:49 + + ++----------------------------+ +; Fitter Suppressed Messages ; ++----------------------------+ +The suppressed messages can be found in C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/output_files/de0_nano_system.fit.smsg. + + diff --git a/MCTEST/DE0-nano-HD/output_files/de0_nano_system.fit.smsg b/MCTEST/DE0-nano-HD/output_files/de0_nano_system.fit.smsg new file mode 100644 index 00000000..ed080d61 --- /dev/null +++ b/MCTEST/DE0-nano-HD/output_files/de0_nano_system.fit.smsg @@ -0,0 +1,6 @@ +Extra Info (176273): Performing register packing on registers with non-logic cell location assignments +Extra Info (176274): Completed register packing on registers with non-logic cell location assignments +Extra Info (176236): Started Fast Input/Output/OE register processing +Extra Info (176237): Finished Fast Input/Output/OE register processing +Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density +Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks diff --git a/MCTEST/DE0-nano-HD/output_files/de0_nano_system.fit.summary b/MCTEST/DE0-nano-HD/output_files/de0_nano_system.fit.summary new file mode 100644 index 00000000..98187f80 --- /dev/null +++ b/MCTEST/DE0-nano-HD/output_files/de0_nano_system.fit.summary @@ -0,0 +1,16 @@ +Fitter Status : Successful - Fri Mar 14 16:49:30 2014 +Quartus II 64-Bit Version : 12.1 Build 243 01/31/2013 SP 1.33 SJ Full Version +Revision Name : de0_nano_system +Top-level Entity Name : de0_nano_system +Family : Cyclone IV E +Device : EP4CE22F17C6 +Timing Models : Final +Total logic elements : 4,562 / 22,320 ( 20 % ) + Total combinational functions : 3,937 / 22,320 ( 18 % ) + Dedicated logic registers : 2,790 / 22,320 ( 13 % ) +Total registers : 2859 +Total pins : 122 / 154 ( 79 % ) +Total virtual pins : 0 +Total memory bits : 119,808 / 608,256 ( 20 % ) +Embedded Multiplier 9-bit elements : 4 / 132 ( 3 % ) +Total PLLs : 1 / 4 ( 25 % ) diff --git a/MCTEST/DE0-nano-HD/output_files/de0_nano_system.flow.rpt b/MCTEST/DE0-nano-HD/output_files/de0_nano_system.flow.rpt new file mode 100644 index 00000000..d4d9245a --- /dev/null +++ b/MCTEST/DE0-nano-HD/output_files/de0_nano_system.flow.rpt @@ -0,0 +1,231 @@ +Flow report for de0_nano_system +Fri Mar 14 16:49:42 2014 +Quartus II 64-Bit Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Full Version + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Flow Summary + 3. Flow Settings + 4. Flow Non-Default Global Settings + 5. Flow Elapsed Time + 6. Flow OS Summary + 7. Flow Log + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2012 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++----------------------------------------------------------------------------------------+ +; Flow Summary ; ++------------------------------------+---------------------------------------------------+ +; Flow Status ; Successful - Fri Mar 14 16:49:35 2014 ; +; Quartus II 64-Bit Version ; 12.1 Build 243 01/31/2013 SP 1.33 SJ Full Version ; +; Revision Name ; de0_nano_system ; +; Top-level Entity Name ; de0_nano_system ; +; Family ; Cyclone IV E ; +; Device ; EP4CE22F17C6 ; +; Timing Models ; Final ; +; Total logic elements ; 4,562 / 22,320 ( 20 % ) ; +; Total combinational functions ; 3,937 / 22,320 ( 18 % ) ; +; Dedicated logic registers ; 2,790 / 22,320 ( 13 % ) ; +; Total registers ; 2859 ; +; Total pins ; 122 / 154 ( 79 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 119,808 / 608,256 ( 20 % ) ; +; Embedded Multiplier 9-bit elements ; 4 / 132 ( 3 % ) ; +; Total PLLs ; 1 / 4 ( 25 % ) ; ++------------------------------------+---------------------------------------------------+ + + ++-----------------------------------------+ +; Flow Settings ; ++-------------------+---------------------+ +; Option ; Setting ; ++-------------------+---------------------+ +; Start date & time ; 03/14/2014 16:48:30 ; +; Main task ; Compilation ; +; Revision Name ; de0_nano_system ; ++-------------------+---------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Flow Non-Default Global Settings ; ++-------------------------------------+----------------------------------------------------------+---------------+---------------------------------+------------+ +; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; ++-------------------------------------+----------------------------------------------------------+---------------+---------------------------------+------------+ +; COMPILER_SIGNATURE_ID ; 116530612622.139483731001292 ; -- ; -- ; -- ; +; IP_TOOL_ENV ; qsys ; -- ; altera_avalon_sc_fifo ; -- ; +; IP_TOOL_ENV ; qsys ; -- ; altera_merlin_burst_adapter ; -- ; +; IP_TOOL_ENV ; qsys ; -- ; altera_merlin_master_agent ; -- ; +; IP_TOOL_ENV ; qsys ; -- ; altera_merlin_master_translator ; -- ; +; IP_TOOL_ENV ; qsys ; -- ; altera_merlin_slave_agent ; -- ; +; IP_TOOL_ENV ; qsys ; -- ; altera_merlin_slave_translator ; -- ; +; IP_TOOL_ENV ; qsys ; -- ; altera_merlin_traffic_limiter ; -- ; +; IP_TOOL_ENV ; qsys ; -- ; altera_merlin_width_adapter ; -- ; +; IP_TOOL_ENV ; qsys ; -- ; altera_reset_controller ; -- ; +; IP_TOOL_ENV ; qsys ; -- ; system ; -- ; +; IP_TOOL_ENV ; qsys ; -- ; system_addr_router ; -- ; +; IP_TOOL_ENV ; qsys ; -- ; system_addr_router_001 ; -- ; +; IP_TOOL_ENV ; qsys ; -- ; system_cmd_xbar_demux ; -- ; +; IP_TOOL_ENV ; qsys ; -- ; system_cmd_xbar_demux_001 ; -- ; +; IP_TOOL_ENV ; qsys ; -- ; system_cmd_xbar_mux ; -- ; +; IP_TOOL_ENV ; qsys ; -- ; system_cpu ; -- ; +; IP_TOOL_ENV ; qsys ; -- ; system_id_router ; -- ; +; IP_TOOL_ENV ; qsys ; -- ; system_id_router_001 ; -- ; +; IP_TOOL_ENV ; qsys ; -- ; system_id_router_002 ; -- ; +; IP_TOOL_ENV ; qsys ; -- ; system_irq_mapper ; -- ; +; IP_TOOL_ENV ; qsys ; -- ; system_jtag_uart_0 ; -- ; +; IP_TOOL_ENV ; qsys ; -- ; system_pio_key ; -- ; +; IP_TOOL_ENV ; qsys ; -- ; system_pio_led ; -- ; +; IP_TOOL_ENV ; qsys ; -- ; system_pio_motor_rst ; -- ; +; IP_TOOL_ENV ; qsys ; -- ; system_pio_sw ; -- ; +; IP_TOOL_ENV ; qsys ; -- ; system_rsp_xbar_demux ; -- ; +; IP_TOOL_ENV ; qsys ; -- ; system_rsp_xbar_demux_002 ; -- ; +; IP_TOOL_ENV ; qsys ; -- ; system_rsp_xbar_mux ; -- ; +; IP_TOOL_ENV ; qsys ; -- ; system_rsp_xbar_mux_001 ; -- ; +; IP_TOOL_ENV ; qsys ; -- ; system_sdram ; -- ; +; IP_TOOL_ENV ; qsys ; -- ; system_sys_clk_timer ; -- ; +; IP_TOOL_ENV ; qsys ; -- ; system_sysid ; -- ; +; IP_TOOL_ENV ; qsys ; -- ; system_uart_0 ; -- ; +; IP_TOOL_NAME ; ALTPLL ; -- ; -- ; -- ; +; IP_TOOL_NAME ; altera_avalon_sc_fifo ; -- ; altera_avalon_sc_fifo ; -- ; +; IP_TOOL_NAME ; altera_merlin_burst_adapter ; -- ; altera_merlin_burst_adapter ; -- ; +; IP_TOOL_NAME ; altera_merlin_master_agent ; -- ; altera_merlin_master_agent ; -- ; +; IP_TOOL_NAME ; altera_merlin_master_translator ; -- ; altera_merlin_master_translator ; -- ; +; IP_TOOL_NAME ; altera_merlin_slave_agent ; -- ; altera_merlin_slave_agent ; -- ; +; IP_TOOL_NAME ; altera_merlin_slave_translator ; -- ; altera_merlin_slave_translator ; -- ; +; IP_TOOL_NAME ; altera_merlin_traffic_limiter ; -- ; altera_merlin_traffic_limiter ; -- ; +; IP_TOOL_NAME ; altera_merlin_width_adapter ; -- ; altera_merlin_width_adapter ; -- ; +; IP_TOOL_NAME ; altera_reset_controller ; -- ; altera_reset_controller ; -- ; +; IP_TOOL_NAME ; qsys ; -- ; system ; -- ; +; IP_TOOL_NAME ; altera_merlin_router ; -- ; system_addr_router ; -- ; +; IP_TOOL_NAME ; altera_merlin_router ; -- ; system_addr_router_001 ; -- ; +; IP_TOOL_NAME ; altera_merlin_demultiplexer ; -- ; system_cmd_xbar_demux ; -- ; +; IP_TOOL_NAME ; altera_merlin_demultiplexer ; -- ; system_cmd_xbar_demux_001 ; -- ; +; IP_TOOL_NAME ; altera_merlin_multiplexer ; -- ; system_cmd_xbar_mux ; -- ; +; IP_TOOL_NAME ; altera_nios2_qsys ; -- ; system_cpu ; -- ; +; IP_TOOL_NAME ; altera_merlin_router ; -- ; system_id_router ; -- ; +; IP_TOOL_NAME ; altera_merlin_router ; -- ; system_id_router_001 ; -- ; +; IP_TOOL_NAME ; altera_merlin_router ; -- ; system_id_router_002 ; -- ; +; IP_TOOL_NAME ; altera_irq_mapper ; -- ; system_irq_mapper ; -- ; +; IP_TOOL_NAME ; altera_avalon_jtag_uart ; -- ; system_jtag_uart_0 ; -- ; +; IP_TOOL_NAME ; altera_avalon_pio ; -- ; system_pio_key ; -- ; +; IP_TOOL_NAME ; altera_avalon_pio ; -- ; system_pio_led ; -- ; +; IP_TOOL_NAME ; altera_avalon_pio ; -- ; system_pio_motor_rst ; -- ; +; IP_TOOL_NAME ; altera_avalon_pio ; -- ; system_pio_sw ; -- ; +; IP_TOOL_NAME ; altera_merlin_demultiplexer ; -- ; system_rsp_xbar_demux ; -- ; +; IP_TOOL_NAME ; altera_merlin_demultiplexer ; -- ; system_rsp_xbar_demux_002 ; -- ; +; IP_TOOL_NAME ; altera_merlin_multiplexer ; -- ; system_rsp_xbar_mux ; -- ; +; IP_TOOL_NAME ; altera_merlin_multiplexer ; -- ; system_rsp_xbar_mux_001 ; -- ; +; IP_TOOL_NAME ; altera_avalon_new_sdram_controller ; -- ; system_sdram ; -- ; +; IP_TOOL_NAME ; altera_avalon_timer ; -- ; system_sys_clk_timer ; -- ; +; IP_TOOL_NAME ; altera_avalon_sysid_qsys ; -- ; system_sysid ; -- ; +; IP_TOOL_NAME ; altera_avalon_uart ; -- ; system_uart_0 ; -- ; +; IP_TOOL_VERSION ; 12.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 12.1 ; -- ; altera_avalon_sc_fifo ; -- ; +; IP_TOOL_VERSION ; 12.1 ; -- ; altera_merlin_burst_adapter ; -- ; +; IP_TOOL_VERSION ; 12.1 ; -- ; altera_merlin_master_agent ; -- ; +; IP_TOOL_VERSION ; 12.1 ; -- ; altera_merlin_master_translator ; -- ; +; IP_TOOL_VERSION ; 12.1 ; -- ; altera_merlin_slave_agent ; -- ; +; IP_TOOL_VERSION ; 12.1 ; -- ; altera_merlin_slave_translator ; -- ; +; IP_TOOL_VERSION ; 12.1 ; -- ; altera_merlin_traffic_limiter ; -- ; +; IP_TOOL_VERSION ; 12.1 ; -- ; altera_merlin_width_adapter ; -- ; +; IP_TOOL_VERSION ; 12.1 ; -- ; altera_reset_controller ; -- ; +; IP_TOOL_VERSION ; 12.1sp1 ; -- ; system ; -- ; +; IP_TOOL_VERSION ; 12.1 ; -- ; system_addr_router ; -- ; +; IP_TOOL_VERSION ; 12.1 ; -- ; system_addr_router_001 ; -- ; +; IP_TOOL_VERSION ; 12.1 ; -- ; system_cmd_xbar_demux ; -- ; +; IP_TOOL_VERSION ; 12.1 ; -- ; system_cmd_xbar_demux_001 ; -- ; +; IP_TOOL_VERSION ; 12.1 ; -- ; system_cmd_xbar_mux ; -- ; +; IP_TOOL_VERSION ; 12.1 ; -- ; system_cpu ; -- ; +; IP_TOOL_VERSION ; 12.1 ; -- ; system_id_router ; -- ; +; IP_TOOL_VERSION ; 12.1 ; -- ; system_id_router_001 ; -- ; +; IP_TOOL_VERSION ; 12.1 ; -- ; system_id_router_002 ; -- ; +; IP_TOOL_VERSION ; 12.1 ; -- ; system_irq_mapper ; -- ; +; IP_TOOL_VERSION ; 12.1 ; -- ; system_jtag_uart_0 ; -- ; +; IP_TOOL_VERSION ; 12.1 ; -- ; system_pio_key ; -- ; +; IP_TOOL_VERSION ; 12.1 ; -- ; system_pio_led ; -- ; +; IP_TOOL_VERSION ; 12.1 ; -- ; system_pio_motor_rst ; -- ; +; IP_TOOL_VERSION ; 12.1 ; -- ; system_pio_sw ; -- ; +; IP_TOOL_VERSION ; 12.1 ; -- ; system_rsp_xbar_demux ; -- ; +; IP_TOOL_VERSION ; 12.1 ; -- ; system_rsp_xbar_demux_002 ; -- ; +; IP_TOOL_VERSION ; 12.1 ; -- ; system_rsp_xbar_mux ; -- ; +; IP_TOOL_VERSION ; 12.1 ; -- ; system_rsp_xbar_mux_001 ; -- ; +; IP_TOOL_VERSION ; 12.1 ; -- ; system_sdram ; -- ; +; IP_TOOL_VERSION ; 12.1 ; -- ; system_sys_clk_timer ; -- ; +; IP_TOOL_VERSION ; 12.1 ; -- ; system_sysid ; -- ; +; IP_TOOL_VERSION ; 12.1 ; -- ; system_uart_0 ; -- ; +; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; +; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; +; MISC_FILE ; system/synthesis/../../system.cmp ; -- ; -- ; -- ; +; MISC_FILE ; system/synthesis/../../system.qsys ; -- ; -- ; -- ; +; MISC_FILE ; pll_sys.cmp ; -- ; -- ; -- ; +; MISC_FILE ; pll_sys.ppf ; -- ; -- ; -- ; +; NOMINAL_CORE_SUPPLY_VOLTAGE ; 1.2V ; -- ; -- ; -- ; +; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ; +; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING ; -- ; -- ; Top ; +; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ; +; POWER_BOARD_THERMAL_MODEL ; None (CONSERVATIVE) ; -- ; -- ; -- ; +; POWER_PRESET_COOLING_SOLUTION ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; -- ; -- ; -- ; +; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; +; SLD_INFO ; QSYS_NAME system HAS_SOPCINFO 1 GENERATION_ID 1394124174 ; -- ; system ; -- ; +; SOPCINFO_FILE ; system/synthesis/../../system.sopcinfo ; -- ; -- ; -- ; +; SYNTHESIS_ONLY_QIP ; On ; -- ; -- ; -- ; ++-------------------------------------+----------------------------------------------------------+---------------+---------------------------------+------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Flow Elapsed Time ; ++---------------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; ++---------------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Analysis & Synthesis ; 00:00:20 ; 1.0 ; 644 MB ; 00:00:19 ; +; Fitter ; 00:00:38 ; 2.4 ; 1130 MB ; 00:00:47 ; +; Assembler ; 00:00:02 ; 1.0 ; 447 MB ; 00:00:02 ; +; TimeQuest Timing Analyzer ; 00:00:06 ; 3.2 ; 567 MB ; 00:00:06 ; +; Total ; 00:01:06 ; -- ; -- ; 00:01:14 ; ++---------------------------+--------------+-------------------------+---------------------+------------------------------------+ + + ++----------------------------------------------------------------------------------------+ +; Flow OS Summary ; ++---------------------------+------------------+-----------+------------+----------------+ +; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; ++---------------------------+------------------+-----------+------------+----------------+ +; Analysis & Synthesis ; e3-11-10 ; Windows 7 ; 6.1 ; x86_64 ; +; Fitter ; e3-11-10 ; Windows 7 ; 6.1 ; x86_64 ; +; Assembler ; e3-11-10 ; Windows 7 ; 6.1 ; x86_64 ; +; TimeQuest Timing Analyzer ; e3-11-10 ; Windows 7 ; 6.1 ; x86_64 ; ++---------------------------+------------------+-----------+------------+----------------+ + + +------------ +; Flow Log ; +------------ +quartus_map --read_settings_files=on --write_settings_files=off de0_nano_system -c de0_nano_system +quartus_fit --read_settings_files=off --write_settings_files=off de0_nano_system -c de0_nano_system +quartus_asm --read_settings_files=off --write_settings_files=off de0_nano_system -c de0_nano_system +quartus_sta de0_nano_system -c de0_nano_system + + + diff --git a/MCTEST/DE0-nano-HD/output_files/de0_nano_system.jdi b/MCTEST/DE0-nano-HD/output_files/de0_nano_system.jdi new file mode 100644 index 00000000..256900b9 --- /dev/null +++ b/MCTEST/DE0-nano-HD/output_files/de0_nano_system.jdi @@ -0,0 +1,152 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/MCTEST/DE0-nano-HD/output_files/de0_nano_system.map.rpt b/MCTEST/DE0-nano-HD/output_files/de0_nano_system.map.rpt new file mode 100644 index 00000000..5cc7dc27 --- /dev/null +++ b/MCTEST/DE0-nano-HD/output_files/de0_nano_system.map.rpt @@ -0,0 +1,6734 @@ +Analysis & Synthesis report for de0_nano_system +Fri Mar 14 16:48:51 2014 +Quartus II 64-Bit Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Full Version + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Analysis & Synthesis Summary + 3. Analysis & Synthesis Settings + 4. Parallel Compilation + 5. Analysis & Synthesis Source Files Read + 6. Analysis & Synthesis Resource Usage Summary + 7. Analysis & Synthesis Resource Utilization by Entity + 8. Analysis & Synthesis RAM Summary + 9. Analysis & Synthesis DSP Block Usage Summary + 10. Analysis & Synthesis IP Cores Summary + 11. State Machine - |de0_nano_system|system:inst_cpu|system_sdram:sdram|m_next + 12. State Machine - |de0_nano_system|system:inst_cpu|system_sdram:sdram|m_state + 13. State Machine - |de0_nano_system|system:inst_cpu|system_sdram:sdram|i_next + 14. State Machine - |de0_nano_system|system:inst_cpu|system_sdram:sdram|i_state + 15. State Machine - |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|DRsize + 16. Registers Protected by Synthesis + 17. Registers Removed During Synthesis + 18. Removed Registers Triggering Further Register Optimizations + 19. General Register Statistics + 20. Inverted Register Statistics + 21. Multiplexer Restructuring Statistics (Restructuring Performed) + 22. Source assignments for system:inst_cpu|system_sdram:sdram + 23. Source assignments for system:inst_cpu|system_uart_0:uart_0 + 24. Source assignments for system:inst_cpu|system_uart_0:uart_0|system_uart_0_rx:the_system_uart_0_rx|altera_std_synchronizer:the_altera_std_synchronizer + 25. Source assignments for system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1 + 26. Source assignments for system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1 + 27. Source assignments for system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram + 28. Source assignments for system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram + 29. Source assignments for system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1 + 30. Source assignments for system:inst_cpu|system_cmd_xbar_demux:cmd_xbar_demux + 31. Source assignments for system:inst_cpu|system_cmd_xbar_demux_001:cmd_xbar_demux_001 + 32. Source assignments for system:inst_cpu|system_rsp_xbar_demux:rsp_xbar_demux + 33. Source assignments for system:inst_cpu|system_rsp_xbar_demux:rsp_xbar_demux_001 + 34. Source assignments for system:inst_cpu|system_rsp_xbar_demux_002:rsp_xbar_demux_002 + 35. Source assignments for system:inst_cpu|system_rsp_xbar_demux_002:rsp_xbar_demux_003 + 36. Source assignments for system:inst_cpu|system_rsp_xbar_demux_002:rsp_xbar_demux_004 + 37. Source assignments for system:inst_cpu|system_rsp_xbar_demux_002:rsp_xbar_demux_005 + 38. Source assignments for system:inst_cpu|system_rsp_xbar_demux_002:rsp_xbar_demux_006 + 39. Source assignments for system:inst_cpu|system_rsp_xbar_demux_002:rsp_xbar_demux_007 + 40. Source assignments for system:inst_cpu|system_rsp_xbar_demux_002:rsp_xbar_demux_008 + 41. Source assignments for system:inst_cpu|system_rsp_xbar_demux_002:rsp_xbar_demux_009 + 42. Source assignments for system:inst_cpu|system_rsp_xbar_demux_002:rsp_xbar_demux_010 + 43. Parameter Settings for User Entity Instance: pll_sys:inst_pll_sys|altpll:altpll_component + 44. Parameter Settings for User Entity Instance: system:inst_cpu|system_uart_0:uart_0|system_uart_0_rx:the_system_uart_0_rx|altera_std_synchronizer:the_altera_std_synchronizer + 45. Parameter Settings for User Entity Instance: system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo + 46. Parameter Settings for User Entity Instance: system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo + 47. Parameter Settings for User Entity Instance: system:inst_cpu|system_rs232_motor:rs232_motor + 48. Parameter Settings for User Entity Instance: system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer + 49. Parameter Settings for User Entity Instance: system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_rs232_counters:RS232_In_Counters + 50. Parameter Settings for User Entity Instance: system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO + 51. Parameter Settings for User Entity Instance: system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO + 52. Parameter Settings for User Entity Instance: system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer + 53. Parameter Settings for User Entity Instance: system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_rs232_counters:RS232_Out_Counters + 54. Parameter Settings for User Entity Instance: system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO + 55. Parameter Settings for User Entity Instance: system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO + 56. Parameter Settings for User Entity Instance: system:inst_cpu|altera_merlin_master_translator:cpu_instruction_master_translator + 57. Parameter Settings for User Entity Instance: system:inst_cpu|altera_merlin_master_translator:cpu_data_master_translator + 58. Parameter Settings for User Entity Instance: system:inst_cpu|altera_merlin_slave_translator:cpu_jtag_debug_module_translator + 59. Parameter Settings for User Entity Instance: system:inst_cpu|altera_merlin_slave_translator:sdram_s1_translator + 60. Parameter Settings for User Entity Instance: system:inst_cpu|altera_merlin_slave_translator:sysid_control_slave_translator + 61. Parameter Settings for User Entity Instance: system:inst_cpu|altera_merlin_slave_translator:sys_clk_timer_s1_translator + 62. Parameter Settings for User Entity Instance: system:inst_cpu|altera_merlin_slave_translator:uart_0_s1_translator + 63. Parameter Settings for User Entity Instance: system:inst_cpu|altera_merlin_slave_translator:pio_led_s1_translator + 64. Parameter Settings for User Entity Instance: system:inst_cpu|altera_merlin_slave_translator:pio_key_s1_translator + 65. Parameter Settings for User Entity Instance: system:inst_cpu|altera_merlin_slave_translator:pio_sw_s1_translator + 66. Parameter Settings for User Entity Instance: system:inst_cpu|altera_merlin_slave_translator:jtag_uart_0_avalon_jtag_slave_translator + 67. Parameter Settings for User Entity Instance: system:inst_cpu|altera_merlin_slave_translator:pio_motor_rst_s1_translator + 68. Parameter Settings for User Entity Instance: system:inst_cpu|altera_merlin_slave_translator:rs232_motor_avalon_rs232_slave_translator + 69. Parameter Settings for User Entity Instance: system:inst_cpu|altera_merlin_master_agent:cpu_instruction_master_translator_avalon_universal_master_0_agent + 70. Parameter Settings for User Entity Instance: system:inst_cpu|altera_merlin_master_agent:cpu_data_master_translator_avalon_universal_master_0_agent + 71. Parameter Settings for User Entity Instance: system:inst_cpu|altera_merlin_slave_agent:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent + 72. Parameter Settings for User Entity Instance: system:inst_cpu|altera_merlin_slave_agent:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor + 73. Parameter Settings for User Entity Instance: system:inst_cpu|altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo + 74. Parameter Settings for User Entity Instance: system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent + 75. Parameter Settings for User Entity Instance: system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor + 76. Parameter Settings for User Entity Instance: system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo + 77. Parameter Settings for User Entity Instance: system:inst_cpu|altera_merlin_slave_agent:sysid_control_slave_translator_avalon_universal_slave_0_agent + 78. Parameter Settings for User Entity Instance: system:inst_cpu|altera_merlin_slave_agent:sysid_control_slave_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor + 79. Parameter Settings for User Entity Instance: system:inst_cpu|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo + 80. Parameter Settings for User Entity Instance: system:inst_cpu|altera_merlin_slave_agent:sys_clk_timer_s1_translator_avalon_universal_slave_0_agent + 81. Parameter Settings for User Entity Instance: system:inst_cpu|altera_merlin_slave_agent:sys_clk_timer_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor + 82. Parameter Settings for User Entity Instance: system:inst_cpu|altera_avalon_sc_fifo:sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo + 83. Parameter Settings for User Entity Instance: system:inst_cpu|altera_merlin_slave_agent:uart_0_s1_translator_avalon_universal_slave_0_agent + 84. Parameter Settings for User Entity Instance: system:inst_cpu|altera_merlin_slave_agent:uart_0_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor + 85. Parameter Settings for User Entity Instance: system:inst_cpu|altera_avalon_sc_fifo:uart_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo + 86. Parameter Settings for User Entity Instance: system:inst_cpu|altera_merlin_slave_agent:pio_led_s1_translator_avalon_universal_slave_0_agent + 87. Parameter Settings for User Entity Instance: system:inst_cpu|altera_merlin_slave_agent:pio_led_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor + 88. Parameter Settings for User Entity Instance: system:inst_cpu|altera_avalon_sc_fifo:pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo + 89. Parameter Settings for User Entity Instance: system:inst_cpu|altera_merlin_slave_agent:pio_key_s1_translator_avalon_universal_slave_0_agent + 90. Parameter Settings for User Entity Instance: system:inst_cpu|altera_merlin_slave_agent:pio_key_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor + 91. Parameter Settings for User Entity Instance: system:inst_cpu|altera_avalon_sc_fifo:pio_key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo + 92. Parameter Settings for User Entity Instance: system:inst_cpu|altera_merlin_slave_agent:pio_sw_s1_translator_avalon_universal_slave_0_agent + 93. Parameter Settings for User Entity Instance: system:inst_cpu|altera_merlin_slave_agent:pio_sw_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor + 94. Parameter Settings for User Entity Instance: system:inst_cpu|altera_avalon_sc_fifo:pio_sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo + 95. Parameter Settings for User Entity Instance: system:inst_cpu|altera_merlin_slave_agent:jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent + 96. Parameter Settings for User Entity Instance: system:inst_cpu|altera_merlin_slave_agent:jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor + 97. Parameter Settings for User Entity Instance: system:inst_cpu|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo + 98. Parameter Settings for User Entity Instance: system:inst_cpu|altera_merlin_slave_agent:pio_motor_rst_s1_translator_avalon_universal_slave_0_agent + 99. Parameter Settings for User Entity Instance: system:inst_cpu|altera_merlin_slave_agent:pio_motor_rst_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor +100. Parameter Settings for User Entity Instance: system:inst_cpu|altera_avalon_sc_fifo:pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rsp_fifo +101. Parameter Settings for User Entity Instance: system:inst_cpu|altera_merlin_slave_agent:rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent +102. Parameter Settings for User Entity Instance: system:inst_cpu|altera_merlin_slave_agent:rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor +103. Parameter Settings for User Entity Instance: system:inst_cpu|altera_avalon_sc_fifo:rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo +104. Parameter Settings for User Entity Instance: system:inst_cpu|system_addr_router:addr_router|system_addr_router_default_decode:the_default_decode +105. Parameter Settings for User Entity Instance: system:inst_cpu|system_addr_router_001:addr_router_001|system_addr_router_001_default_decode:the_default_decode +106. Parameter Settings for User Entity Instance: system:inst_cpu|system_id_router:id_router|system_id_router_default_decode:the_default_decode +107. Parameter Settings for User Entity Instance: system:inst_cpu|system_id_router_001:id_router_001|system_id_router_001_default_decode:the_default_decode +108. Parameter Settings for User Entity Instance: system:inst_cpu|system_id_router_002:id_router_002|system_id_router_002_default_decode:the_default_decode +109. Parameter Settings for User Entity Instance: system:inst_cpu|system_id_router_002:id_router_003|system_id_router_002_default_decode:the_default_decode +110. Parameter Settings for User Entity Instance: system:inst_cpu|system_id_router_002:id_router_004|system_id_router_002_default_decode:the_default_decode +111. Parameter Settings for User Entity Instance: system:inst_cpu|system_id_router_002:id_router_005|system_id_router_002_default_decode:the_default_decode +112. Parameter Settings for User Entity Instance: system:inst_cpu|system_id_router_002:id_router_006|system_id_router_002_default_decode:the_default_decode +113. Parameter Settings for User Entity Instance: system:inst_cpu|system_id_router_002:id_router_007|system_id_router_002_default_decode:the_default_decode +114. Parameter Settings for User Entity Instance: system:inst_cpu|system_id_router_002:id_router_008|system_id_router_002_default_decode:the_default_decode +115. Parameter Settings for User Entity Instance: system:inst_cpu|system_id_router_002:id_router_009|system_id_router_002_default_decode:the_default_decode +116. Parameter Settings for User Entity Instance: system:inst_cpu|system_id_router_002:id_router_010|system_id_router_002_default_decode:the_default_decode +117. Parameter Settings for User Entity Instance: system:inst_cpu|altera_merlin_traffic_limiter:limiter +118. Parameter Settings for User Entity Instance: system:inst_cpu|altera_merlin_traffic_limiter:limiter_001 +119. Parameter Settings for User Entity Instance: system:inst_cpu|altera_merlin_burst_adapter:burst_adapter +120. Parameter Settings for User Entity Instance: system:inst_cpu|altera_merlin_burst_adapter:burst_adapter|altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba +121. Parameter Settings for User Entity Instance: system:inst_cpu|altera_reset_controller:rst_controller +122. Parameter Settings for User Entity Instance: system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1 +123. Parameter Settings for User Entity Instance: system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux|altera_merlin_arbitrator:arb +124. Parameter Settings for User Entity Instance: system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder +125. Parameter Settings for User Entity Instance: system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux_001|altera_merlin_arbitrator:arb +126. Parameter Settings for User Entity Instance: system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux_001|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder +127. Parameter Settings for User Entity Instance: system:inst_cpu|system_rsp_xbar_mux:rsp_xbar_mux|altera_merlin_arbitrator:arb +128. Parameter Settings for User Entity Instance: system:inst_cpu|system_rsp_xbar_mux:rsp_xbar_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder +129. Parameter Settings for User Entity Instance: system:inst_cpu|system_rsp_xbar_mux_001:rsp_xbar_mux_001|altera_merlin_arbitrator:arb +130. Parameter Settings for User Entity Instance: system:inst_cpu|system_rsp_xbar_mux_001:rsp_xbar_mux_001|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder +131. Parameter Settings for User Entity Instance: system:inst_cpu|altera_merlin_width_adapter:width_adapter +132. Parameter Settings for User Entity Instance: system:inst_cpu|altera_merlin_width_adapter:width_adapter_001 +133. Parameter Settings for User Entity Instance: system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|altera_merlin_burst_uncompressor:uncompressor +134. altpll Parameter Settings by Entity Instance +135. scfifo Parameter Settings by Entity Instance +136. Port Connectivity Checks: "system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|altera_merlin_burst_uncompressor:uncompressor" +137. Port Connectivity Checks: "system:inst_cpu|altera_merlin_width_adapter:width_adapter_001" +138. Port Connectivity Checks: "system:inst_cpu|altera_merlin_width_adapter:width_adapter" +139. Port Connectivity Checks: "system:inst_cpu|system_rsp_xbar_mux_001:rsp_xbar_mux_001|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder" +140. Port Connectivity Checks: "system:inst_cpu|system_rsp_xbar_mux:rsp_xbar_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder" +141. Port Connectivity Checks: "system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder" +142. Port Connectivity Checks: "system:inst_cpu|altera_reset_controller:rst_controller" +143. Port Connectivity Checks: "system:inst_cpu|system_id_router_002:id_router_002|system_id_router_002_default_decode:the_default_decode" +144. Port Connectivity Checks: "system:inst_cpu|system_id_router_001:id_router_001|system_id_router_001_default_decode:the_default_decode" +145. Port Connectivity Checks: "system:inst_cpu|system_id_router:id_router|system_id_router_default_decode:the_default_decode" +146. Port Connectivity Checks: "system:inst_cpu|altera_avalon_sc_fifo:rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo" +147. Port Connectivity Checks: "system:inst_cpu|altera_avalon_sc_fifo:pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" +148. Port Connectivity Checks: "system:inst_cpu|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo" +149. Port Connectivity Checks: "system:inst_cpu|altera_avalon_sc_fifo:pio_sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" +150. Port Connectivity Checks: "system:inst_cpu|altera_avalon_sc_fifo:pio_key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" +151. Port Connectivity Checks: "system:inst_cpu|altera_avalon_sc_fifo:pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" +152. Port Connectivity Checks: "system:inst_cpu|altera_avalon_sc_fifo:uart_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" +153. Port Connectivity Checks: "system:inst_cpu|altera_avalon_sc_fifo:sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" +154. Port Connectivity Checks: "system:inst_cpu|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo" +155. Port Connectivity Checks: "system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" +156. Port Connectivity Checks: "system:inst_cpu|altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo" +157. Port Connectivity Checks: "system:inst_cpu|altera_merlin_slave_translator:rs232_motor_avalon_rs232_slave_translator" +158. Port Connectivity Checks: "system:inst_cpu|altera_merlin_slave_translator:pio_motor_rst_s1_translator" +159. Port Connectivity Checks: "system:inst_cpu|altera_merlin_slave_translator:jtag_uart_0_avalon_jtag_slave_translator" +160. Port Connectivity Checks: "system:inst_cpu|altera_merlin_slave_translator:pio_sw_s1_translator" +161. Port Connectivity Checks: "system:inst_cpu|altera_merlin_slave_translator:pio_key_s1_translator" +162. Port Connectivity Checks: "system:inst_cpu|altera_merlin_slave_translator:pio_led_s1_translator" +163. Port Connectivity Checks: "system:inst_cpu|altera_merlin_slave_translator:uart_0_s1_translator" +164. Port Connectivity Checks: "system:inst_cpu|altera_merlin_slave_translator:sys_clk_timer_s1_translator" +165. Port Connectivity Checks: "system:inst_cpu|altera_merlin_slave_translator:sysid_control_slave_translator" +166. Port Connectivity Checks: "system:inst_cpu|altera_merlin_slave_translator:sdram_s1_translator" +167. Port Connectivity Checks: "system:inst_cpu|altera_merlin_slave_translator:cpu_jtag_debug_module_translator" +168. Port Connectivity Checks: "system:inst_cpu|altera_merlin_master_translator:cpu_data_master_translator" +169. Port Connectivity Checks: "system:inst_cpu|altera_merlin_master_translator:cpu_instruction_master_translator" +170. Port Connectivity Checks: "system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_rs232_counters:RS232_Out_Counters" +171. Port Connectivity Checks: "system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_rs232_counters:RS232_In_Counters" +172. Port Connectivity Checks: "system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic" +173. Port Connectivity Checks: "system:inst_cpu|system_jtag_uart_0:jtag_uart_0" +174. Port Connectivity Checks: "system:inst_cpu|system_uart_0:uart_0" +175. Port Connectivity Checks: "system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module" +176. Port Connectivity Checks: "system:inst_cpu|system_cpu:cpu" +177. Elapsed Time Per Partition +178. Analysis & Synthesis Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2012 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++----------------------------------------------------------------------------------------+ +; Analysis & Synthesis Summary ; ++------------------------------------+---------------------------------------------------+ +; Analysis & Synthesis Status ; Successful - Fri Mar 14 16:48:51 2014 ; +; Quartus II 64-Bit Version ; 12.1 Build 243 01/31/2013 SP 1.33 SJ Full Version ; +; Revision Name ; de0_nano_system ; +; Top-level Entity Name ; de0_nano_system ; +; Family ; Cyclone IV E ; +; Total logic elements ; 4,696 ; +; Total combinational functions ; 3,932 ; +; Dedicated logic registers ; 2,867 ; +; Total registers ; 2867 ; +; Total pins ; 122 ; +; Total virtual pins ; 0 ; +; Total memory bits ; 119,808 ; +; Embedded Multiplier 9-bit elements ; 4 ; +; Total PLLs ; 1 ; ++------------------------------------+---------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Settings ; ++----------------------------------------------------------------------------+--------------------+--------------------+ +; Option ; Setting ; Default Value ; ++----------------------------------------------------------------------------+--------------------+--------------------+ +; Device ; EP4CE22F17C6 ; ; +; Top-level entity name ; de0_nano_system ; de0_nano_system ; +; Family name ; Cyclone IV E ; Cyclone IV GX ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Restructure Multiplexers ; Auto ; Auto ; +; Create Debugging Nodes for IP Cores ; Off ; Off ; +; Preserve fewer node names ; On ; On ; +; Disable OpenCore Plus hardware evaluation ; Off ; Off ; +; Verilog Version ; Verilog_2001 ; Verilog_2001 ; +; VHDL Version ; VHDL_1993 ; VHDL_1993 ; +; State Machine Processing ; Auto ; Auto ; +; Safe State Machine ; Off ; Off ; +; Extract Verilog State Machines ; On ; On ; +; Extract VHDL State Machines ; On ; On ; +; Ignore Verilog initial constructs ; Off ; Off ; +; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; +; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; +; Add Pass-Through Logic to Inferred RAMs ; On ; On ; +; Infer RAMs from Raw Logic ; On ; On ; +; Parallel Synthesis ; On ; On ; +; DSP Block Balancing ; Auto ; Auto ; +; NOT Gate Push-Back ; On ; On ; +; Power-Up Don't Care ; On ; On ; +; Remove Redundant Logic Cells ; Off ; Off ; +; Remove Duplicate Registers ; On ; On ; +; Ignore CARRY Buffers ; Off ; Off ; +; Ignore CASCADE Buffers ; Off ; Off ; +; Ignore GLOBAL Buffers ; Off ; Off ; +; Ignore ROW GLOBAL Buffers ; Off ; Off ; +; Ignore LCELL Buffers ; Off ; Off ; +; Ignore SOFT Buffers ; On ; On ; +; Limit AHDL Integers to 32 Bits ; Off ; Off ; +; Optimization Technique ; Balanced ; Balanced ; +; Carry Chain Length ; 70 ; 70 ; +; Auto Carry Chains ; On ; On ; +; Auto Open-Drain Pins ; On ; On ; +; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; +; Auto ROM Replacement ; On ; On ; +; Auto RAM Replacement ; On ; On ; +; Auto DSP Block Replacement ; On ; On ; +; Auto Shift Register Replacement ; Auto ; Auto ; +; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ; +; Auto Clock Enable Replacement ; On ; On ; +; Strict RAM Replacement ; Off ; Off ; +; Allow Synchronous Control Signals ; On ; On ; +; Force Use of Synchronous Clear Signals ; Off ; Off ; +; Auto RAM Block Balancing ; On ; On ; +; Auto RAM to Logic Cell Conversion ; Off ; Off ; +; Auto Resource Sharing ; Off ; Off ; +; Allow Any RAM Size For Recognition ; Off ; Off ; +; Allow Any ROM Size For Recognition ; Off ; Off ; +; Allow Any Shift Register Size For Recognition ; Off ; Off ; +; Use LogicLock Constraints during Resource Balancing ; On ; On ; +; Ignore translate_off and synthesis_off directives ; Off ; Off ; +; Timing-Driven Synthesis ; On ; On ; +; Report Parameter Settings ; On ; On ; +; Report Source Assignments ; On ; On ; +; Report Connectivity Checks ; On ; On ; +; Ignore Maximum Fan-Out Assignments ; Off ; Off ; +; Synchronization Register Chain Length ; 2 ; 2 ; +; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; +; HDL message level ; Level2 ; Level2 ; +; Suppress Register Optimization Related Messages ; Off ; Off ; +; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; +; Clock MUX Protection ; On ; On ; +; Auto Gated Clock Conversion ; Off ; Off ; +; Block Design Naming ; Auto ; Auto ; +; SDC constraint protection ; Off ; Off ; +; Synthesis Effort ; Auto ; Auto ; +; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; +; Pre-Mapping Resynthesis Optimization ; Off ; Off ; +; Analysis & Synthesis Message Level ; Medium ; Medium ; +; Disable Register Merging Across Hierarchies ; Auto ; Auto ; +; Resource Aware Inference For Block RAM ; On ; On ; +; Synthesis Seed ; 1 ; 1 ; ++----------------------------------------------------------------------------+--------------------+--------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 8 ; +; Maximum allowed ; 4 ; +; ; ; +; Average used ; 1.00 ; +; Maximum used ; 4 ; +; ; ; +; Usage by Processor ; % Time Used ; +; 1 processor ; 100.0% ; +; 2-4 processors ; < 0.1% ; +; 5-8 processors ; 0.0% ; ++----------------------------+-------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Source Files Read ; ++--------------------------------------------------------------------+-----------------+----------------------------------+---------------------------------------------------------------------------------------------------------------+---------+ +; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; ++--------------------------------------------------------------------+-----------------+----------------------------------+---------------------------------------------------------------------------------------------------------------+---------+ +; de0_nano_system.vhd ; yes ; User VHDL File ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/de0_nano_system.vhd ; ; +; heartbeat.vhd ; yes ; User VHDL File ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/heartbeat.vhd ; ; +; system/synthesis/system.v ; yes ; User Verilog HDL File ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v ; system ; +; system/synthesis/submodules/system_irq_mapper.sv ; yes ; User SystemVerilog HDL File ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_irq_mapper.sv ; system ; +; system/synthesis/submodules/altera_merlin_width_adapter.sv ; yes ; User SystemVerilog HDL File ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_width_adapter.sv ; system ; +; system/synthesis/submodules/altera_merlin_burst_uncompressor.sv ; yes ; User SystemVerilog HDL File ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_burst_uncompressor.sv ; system ; +; system/synthesis/submodules/altera_merlin_arbitrator.sv ; yes ; User SystemVerilog HDL File ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_arbitrator.sv ; system ; +; system/synthesis/submodules/system_rsp_xbar_mux_001.sv ; yes ; User SystemVerilog HDL File ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_rsp_xbar_mux_001.sv ; system ; +; system/synthesis/submodules/system_rsp_xbar_mux.sv ; yes ; User SystemVerilog HDL File ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_rsp_xbar_mux.sv ; system ; +; system/synthesis/submodules/system_rsp_xbar_demux_002.sv ; yes ; User SystemVerilog HDL File ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_rsp_xbar_demux_002.sv ; system ; +; system/synthesis/submodules/system_rsp_xbar_demux.sv ; yes ; User SystemVerilog HDL File ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_rsp_xbar_demux.sv ; system ; +; system/synthesis/submodules/system_cmd_xbar_mux.sv ; yes ; User SystemVerilog HDL File ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cmd_xbar_mux.sv ; system ; +; system/synthesis/submodules/system_cmd_xbar_demux_001.sv ; yes ; User SystemVerilog HDL File ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cmd_xbar_demux_001.sv ; system ; +; system/synthesis/submodules/system_cmd_xbar_demux.sv ; yes ; User SystemVerilog HDL File ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cmd_xbar_demux.sv ; system ; +; system/synthesis/submodules/altera_reset_controller.v ; yes ; User Verilog HDL File ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_reset_controller.v ; system ; +; system/synthesis/submodules/altera_reset_synchronizer.v ; yes ; User Verilog HDL File ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_reset_synchronizer.v ; system ; +; system/synthesis/submodules/altera_merlin_burst_adapter.sv ; yes ; User SystemVerilog HDL File ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_burst_adapter.sv ; system ; +; system/synthesis/submodules/altera_merlin_traffic_limiter.sv ; yes ; User SystemVerilog HDL File ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_traffic_limiter.sv ; system ; +; system/synthesis/submodules/system_id_router_002.sv ; yes ; User SystemVerilog HDL File ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_id_router_002.sv ; system ; +; system/synthesis/submodules/system_id_router_001.sv ; yes ; User SystemVerilog HDL File ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_id_router_001.sv ; system ; +; system/synthesis/submodules/system_id_router.sv ; yes ; User SystemVerilog HDL File ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_id_router.sv ; system ; +; system/synthesis/submodules/system_addr_router_001.sv ; yes ; User SystemVerilog HDL File ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_addr_router_001.sv ; system ; +; system/synthesis/submodules/system_addr_router.sv ; yes ; User SystemVerilog HDL File ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_addr_router.sv ; system ; +; system/synthesis/submodules/altera_avalon_sc_fifo.v ; yes ; User Verilog HDL File ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_avalon_sc_fifo.v ; system ; +; system/synthesis/submodules/altera_merlin_slave_agent.sv ; yes ; User SystemVerilog HDL File ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_slave_agent.sv ; system ; +; system/synthesis/submodules/altera_merlin_master_agent.sv ; yes ; User SystemVerilog HDL File ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_master_agent.sv ; system ; +; system/synthesis/submodules/altera_merlin_slave_translator.sv ; yes ; User SystemVerilog HDL File ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_slave_translator.sv ; system ; +; system/synthesis/submodules/altera_merlin_master_translator.sv ; yes ; User SystemVerilog HDL File ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_master_translator.sv ; system ; +; system/synthesis/submodules/altera_up_rs232_counters.v ; yes ; User Verilog HDL File ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_up_rs232_counters.v ; system ; +; system/synthesis/submodules/altera_up_rs232_in_deserializer.v ; yes ; User Verilog HDL File ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_up_rs232_in_deserializer.v ; system ; +; system/synthesis/submodules/altera_up_rs232_out_serializer.v ; yes ; User Verilog HDL File ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_up_rs232_out_serializer.v ; system ; +; system/synthesis/submodules/altera_up_sync_fifo.v ; yes ; User Verilog HDL File ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_up_sync_fifo.v ; system ; +; system/synthesis/submodules/system_rs232_motor.v ; yes ; User Verilog HDL File ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_rs232_motor.v ; system ; +; system/synthesis/submodules/system_pio_motor_rst.v ; yes ; User Verilog HDL File ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_pio_motor_rst.v ; system ; +; system/synthesis/submodules/system_jtag_uart_0.v ; yes ; User Verilog HDL File ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_jtag_uart_0.v ; system ; +; system/synthesis/submodules/system_pio_sw.v ; yes ; User Verilog HDL File ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_pio_sw.v ; system ; +; system/synthesis/submodules/system_pio_key.v ; yes ; User Verilog HDL File ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_pio_key.v ; system ; +; system/synthesis/submodules/system_pio_led.v ; yes ; User Verilog HDL File ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_pio_led.v ; system ; +; system/synthesis/submodules/system_uart_0.v ; yes ; User Verilog HDL File ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_uart_0.v ; system ; +; system/synthesis/submodules/system_sys_clk_timer.v ; yes ; User Verilog HDL File ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_sys_clk_timer.v ; system ; +; system/synthesis/submodules/system_sdram.v ; yes ; User Verilog HDL File ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_sdram.v ; system ; +; system/synthesis/submodules/system_sysid.v ; yes ; User Verilog HDL File ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_sysid.v ; system ; +; system/synthesis/submodules/system_cpu.v ; yes ; Encrypted User Verilog HDL File ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v ; system ; +; system/synthesis/submodules/system_cpu_jtag_debug_module_sysclk.v ; yes ; User Verilog HDL File ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu_jtag_debug_module_sysclk.v ; system ; +; system/synthesis/submodules/system_cpu_jtag_debug_module_tck.v ; yes ; User Verilog HDL File ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu_jtag_debug_module_tck.v ; system ; +; system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v ; yes ; User Verilog HDL File ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v ; system ; +; system/synthesis/submodules/system_cpu_mult_cell.v ; yes ; User Verilog HDL File ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu_mult_cell.v ; system ; +; system/synthesis/submodules/system_cpu_oci_test_bench.v ; yes ; User Verilog HDL File ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu_oci_test_bench.v ; system ; +; system/synthesis/submodules/system_cpu_test_bench.v ; yes ; User Verilog HDL File ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu_test_bench.v ; system ; +; pll_sys.vhd ; yes ; User Wizard-Generated File ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/pll_sys.vhd ; ; +; altpll.tdf ; yes ; Megafunction ; c:/altera/12.1sp1/quartus/libraries/megafunctions/altpll.tdf ; ; +; aglobal121.inc ; yes ; Megafunction ; c:/altera/12.1sp1/quartus/libraries/megafunctions/aglobal121.inc ; ; +; stratix_pll.inc ; yes ; Megafunction ; c:/altera/12.1sp1/quartus/libraries/megafunctions/stratix_pll.inc ; ; +; stratixii_pll.inc ; yes ; Megafunction ; c:/altera/12.1sp1/quartus/libraries/megafunctions/stratixii_pll.inc ; ; +; cycloneii_pll.inc ; yes ; Megafunction ; c:/altera/12.1sp1/quartus/libraries/megafunctions/cycloneii_pll.inc ; ; +; db/pll_sys_altpll.v ; yes ; Auto-Generated Megafunction ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/pll_sys_altpll.v ; ; +; altsyncram.tdf ; yes ; Megafunction ; c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf ; ; +; stratix_ram_block.inc ; yes ; Megafunction ; c:/altera/12.1sp1/quartus/libraries/megafunctions/stratix_ram_block.inc ; ; +; lpm_mux.inc ; yes ; Megafunction ; c:/altera/12.1sp1/quartus/libraries/megafunctions/lpm_mux.inc ; ; +; lpm_decode.inc ; yes ; Megafunction ; c:/altera/12.1sp1/quartus/libraries/megafunctions/lpm_decode.inc ; ; +; a_rdenreg.inc ; yes ; Megafunction ; c:/altera/12.1sp1/quartus/libraries/megafunctions/a_rdenreg.inc ; ; +; altrom.inc ; yes ; Megafunction ; c:/altera/12.1sp1/quartus/libraries/megafunctions/altrom.inc ; ; +; altram.inc ; yes ; Megafunction ; c:/altera/12.1sp1/quartus/libraries/megafunctions/altram.inc ; ; +; altdpram.inc ; yes ; Megafunction ; c:/altera/12.1sp1/quartus/libraries/megafunctions/altdpram.inc ; ; +; db/altsyncram_sjd1.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_sjd1.tdf ; ; +; db/altsyncram_qtg1.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_qtg1.tdf ; ; +; db/altsyncram_fhg1.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_fhg1.tdf ; ; +; db/altsyncram_fvf1.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_fvf1.tdf ; ; +; db/altsyncram_gvf1.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_gvf1.tdf ; ; +; db/altsyncram_d9g1.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_d9g1.tdf ; ; +; db/altsyncram_2jf1.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_2jf1.tdf ; ; +; db/altsyncram_r3d1.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_r3d1.tdf ; ; +; altmult_add.tdf ; yes ; Megafunction ; c:/altera/12.1sp1/quartus/libraries/megafunctions/altmult_add.tdf ; ; +; stratix_mac_mult.inc ; yes ; Megafunction ; c:/altera/12.1sp1/quartus/libraries/megafunctions/stratix_mac_mult.inc ; ; +; stratix_mac_out.inc ; yes ; Megafunction ; c:/altera/12.1sp1/quartus/libraries/megafunctions/stratix_mac_out.inc ; ; +; db/mult_add_75u2.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/mult_add_75u2.tdf ; ; +; db/ded_mult_ks81.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/ded_mult_ks81.tdf ; ; +; db/dffpipe_93c.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/dffpipe_93c.tdf ; ; +; db/mult_add_95u2.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/mult_add_95u2.tdf ; ; +; db/altsyncram_jt72.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_jt72.tdf ; ; +; db/altsyncram_0a02.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_0a02.tdf ; ; +; altera_std_synchronizer.v ; yes ; Megafunction ; c:/altera/12.1sp1/quartus/libraries/megafunctions/altera_std_synchronizer.v ; ; +; sld_virtual_jtag_basic.v ; yes ; Megafunction ; c:/altera/12.1sp1/quartus/libraries/megafunctions/sld_virtual_jtag_basic.v ; ; +; scfifo.tdf ; yes ; Megafunction ; c:/altera/12.1sp1/quartus/libraries/megafunctions/scfifo.tdf ; ; +; a_regfifo.inc ; yes ; Megafunction ; c:/altera/12.1sp1/quartus/libraries/megafunctions/a_regfifo.inc ; ; +; a_dpfifo.inc ; yes ; Megafunction ; c:/altera/12.1sp1/quartus/libraries/megafunctions/a_dpfifo.inc ; ; +; a_i2fifo.inc ; yes ; Megafunction ; c:/altera/12.1sp1/quartus/libraries/megafunctions/a_i2fifo.inc ; ; +; a_fffifo.inc ; yes ; Megafunction ; c:/altera/12.1sp1/quartus/libraries/megafunctions/a_fffifo.inc ; ; +; a_f2fifo.inc ; yes ; Megafunction ; c:/altera/12.1sp1/quartus/libraries/megafunctions/a_f2fifo.inc ; ; +; db/scfifo_jr21.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/scfifo_jr21.tdf ; ; +; db/a_dpfifo_q131.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/a_dpfifo_q131.tdf ; ; +; db/a_fefifo_7cf.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/a_fefifo_7cf.tdf ; ; +; db/cntr_do7.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/cntr_do7.tdf ; ; +; db/dpram_nl21.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/dpram_nl21.tdf ; ; +; db/altsyncram_r1m1.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_r1m1.tdf ; ; +; db/cntr_1ob.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/cntr_1ob.tdf ; ; +; alt_jtag_atlantic.v ; yes ; Encrypted Megafunction ; c:/altera/12.1sp1/quartus/libraries/megafunctions/alt_jtag_atlantic.v ; ; +; db/scfifo_a341.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/scfifo_a341.tdf ; ; +; db/a_dpfifo_tq31.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/a_dpfifo_tq31.tdf ; ; +; db/altsyncram_je81.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/altsyncram_je81.tdf ; ; +; db/cmpr_ks8.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/cmpr_ks8.tdf ; ; +; db/cntr_v9b.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/cntr_v9b.tdf ; ; +; db/cntr_ca7.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/cntr_ca7.tdf ; ; +; db/cntr_0ab.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/cntr_0ab.tdf ; ; +; sld_hub.vhd ; yes ; Encrypted Megafunction ; c:/altera/12.1sp1/quartus/libraries/megafunctions/sld_hub.vhd ; ; +; sld_jtag_hub.vhd ; yes ; Encrypted Megafunction ; c:/altera/12.1sp1/quartus/libraries/megafunctions/sld_jtag_hub.vhd ; ; +; sld_rom_sr.vhd ; yes ; Encrypted Megafunction ; c:/altera/12.1sp1/quartus/libraries/megafunctions/sld_rom_sr.vhd ; ; +; lpm_add_sub.tdf ; yes ; Megafunction ; c:/altera/12.1sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf ; ; +; addcore.inc ; yes ; Megafunction ; c:/altera/12.1sp1/quartus/libraries/megafunctions/addcore.inc ; ; +; look_add.inc ; yes ; Megafunction ; c:/altera/12.1sp1/quartus/libraries/megafunctions/look_add.inc ; ; +; bypassff.inc ; yes ; Megafunction ; c:/altera/12.1sp1/quartus/libraries/megafunctions/bypassff.inc ; ; +; altshift.inc ; yes ; Megafunction ; c:/altera/12.1sp1/quartus/libraries/megafunctions/altshift.inc ; ; +; alt_stratix_add_sub.inc ; yes ; Megafunction ; c:/altera/12.1sp1/quartus/libraries/megafunctions/alt_stratix_add_sub.inc ; ; +; db/add_sub_qvi.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/db/add_sub_qvi.tdf ; ; ++--------------------------------------------------------------------+-----------------+----------------------------------+---------------------------------------------------------------------------------------------------------------+---------+ + + ++------------------------------------------------------+ +; Analysis & Synthesis Resource Usage Summary ; ++---------------------------------------------+--------+ +; Resource ; Usage ; ++---------------------------------------------+--------+ +; Estimated Total logic elements ; 4,696 ; +; ; ; +; Total combinational functions ; 3932 ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 1858 ; +; -- 3 input functions ; 1342 ; +; -- <=2 input functions ; 732 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 3575 ; +; -- arithmetic mode ; 357 ; +; ; ; +; Total registers ; 2867 ; +; -- Dedicated logic registers ; 2867 ; +; -- I/O registers ; 0 ; +; ; ; +; I/O pins ; 122 ; +; Total memory bits ; 119808 ; +; Embedded Multiplier 9-bit elements ; 4 ; +; Total PLLs ; 1 ; +; -- PLLs ; 1 ; +; ; ; +; Maximum fan-out ; 2952 ; +; Total fan-out ; 28751 ; +; Average fan-out ; 3.88 ; ++---------------------------------------------+--------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Resource Utilization by Entity ; ++-----------------------------------------------------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+ +; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ; ++-----------------------------------------------------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+ +; |de0_nano_system ; 3932 (1) ; 2867 (0) ; 119808 ; 4 ; 0 ; 2 ; 122 ; 0 ; |de0_nano_system ; ; +; |heartbeat:inst_heartbeat| ; 22 (22) ; 22 (22) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|heartbeat:inst_heartbeat ; ; +; |pll_sys:inst_pll_sys| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|pll_sys:inst_pll_sys ; ; +; |altpll:altpll_component| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|pll_sys:inst_pll_sys|altpll:altpll_component ; ; +; |pll_sys_altpll:auto_generated| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|pll_sys:inst_pll_sys|altpll:altpll_component|pll_sys_altpll:auto_generated ; ; +; |sld_hub:auto_hub| ; 156 (1) ; 97 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|sld_hub:auto_hub ; ; +; |sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst| ; 155 (117) ; 97 (69) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst ; ; +; |sld_rom_sr:hub_info_reg| ; 21 (21) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg ; ; +; |sld_shadow_jsm:shadow_jsm| ; 17 (17) ; 19 (19) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm ; ; +; |system:inst_cpu| ; 3753 (0) ; 2748 (0) ; 119808 ; 4 ; 0 ; 2 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu ; ; +; |altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 6 (6) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo ; ; +; |altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 7 (7) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo ; ; +; |altera_avalon_sc_fifo:pio_key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 4 (4) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|altera_avalon_sc_fifo:pio_key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; ; +; |altera_avalon_sc_fifo:pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|altera_avalon_sc_fifo:pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; ; +; |altera_avalon_sc_fifo:pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|altera_avalon_sc_fifo:pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; ; +; |altera_avalon_sc_fifo:pio_sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 4 (4) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|altera_avalon_sc_fifo:pio_sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; ; +; |altera_avalon_sc_fifo:rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 4 (4) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|altera_avalon_sc_fifo:rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo ; ; +; |altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 62 (62) ; 56 (56) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; ; +; |altera_avalon_sc_fifo:sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|altera_avalon_sc_fifo:sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; ; +; |altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 4 (4) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo ; ; +; |altera_avalon_sc_fifo:uart_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 4 (4) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|altera_avalon_sc_fifo:uart_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; ; +; |altera_merlin_slave_agent:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_agent:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent ; ; +; |altera_merlin_slave_agent:pio_key_s1_translator_avalon_universal_slave_0_agent| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_agent:pio_key_s1_translator_avalon_universal_slave_0_agent ; ; +; |altera_merlin_slave_agent:pio_led_s1_translator_avalon_universal_slave_0_agent| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_agent:pio_led_s1_translator_avalon_universal_slave_0_agent ; ; +; |altera_merlin_slave_agent:pio_sw_s1_translator_avalon_universal_slave_0_agent| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_agent:pio_sw_s1_translator_avalon_universal_slave_0_agent ; ; +; |altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent| ; 17 (9) ; 3 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent ; ; +; |altera_merlin_burst_uncompressor:uncompressor| ; 8 (8) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor ; ; +; |altera_merlin_slave_agent:sys_clk_timer_s1_translator_avalon_universal_slave_0_agent| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_agent:sys_clk_timer_s1_translator_avalon_universal_slave_0_agent ; ; +; |altera_merlin_slave_agent:sysid_control_slave_translator_avalon_universal_slave_0_agent| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_agent:sysid_control_slave_translator_avalon_universal_slave_0_agent ; ; +; |altera_merlin_slave_translator:cpu_jtag_debug_module_translator| ; 13 (13) ; 37 (37) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_translator:cpu_jtag_debug_module_translator ; ; +; |altera_merlin_slave_translator:jtag_uart_0_avalon_jtag_slave_translator| ; 9 (9) ; 23 (23) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_translator:jtag_uart_0_avalon_jtag_slave_translator ; ; +; |altera_merlin_slave_translator:pio_key_s1_translator| ; 5 (5) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_translator:pio_key_s1_translator ; ; +; |altera_merlin_slave_translator:pio_led_s1_translator| ; 9 (9) ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_translator:pio_led_s1_translator ; ; +; |altera_merlin_slave_translator:pio_motor_rst_s1_translator| ; 7 (7) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_translator:pio_motor_rst_s1_translator ; ; +; |altera_merlin_slave_translator:pio_sw_s1_translator| ; 5 (5) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_translator:pio_sw_s1_translator ; ; +; |altera_merlin_slave_translator:rs232_motor_avalon_rs232_slave_translator| ; 4 (4) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_translator:rs232_motor_avalon_rs232_slave_translator ; ; +; |altera_merlin_slave_translator:sys_clk_timer_s1_translator| ; 8 (8) ; 19 (19) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_translator:sys_clk_timer_s1_translator ; ; +; |altera_merlin_slave_translator:sysid_control_slave_translator| ; 12 (12) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_translator:sysid_control_slave_translator ; ; +; |altera_merlin_slave_translator:uart_0_s1_translator| ; 7 (7) ; 20 (20) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_translator:uart_0_s1_translator ; ; +; |altera_merlin_traffic_limiter:limiter_001| ; 23 (23) ; 20 (20) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|altera_merlin_traffic_limiter:limiter_001 ; ; +; |altera_merlin_traffic_limiter:limiter| ; 14 (14) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|altera_merlin_traffic_limiter:limiter ; ; +; |altera_merlin_width_adapter:width_adapter_001| ; 32 (32) ; 16 (16) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|altera_merlin_width_adapter:width_adapter_001 ; ; +; |altera_merlin_width_adapter:width_adapter| ; 44 (44) ; 44 (44) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|altera_merlin_width_adapter:width_adapter ; ; +; |altera_reset_controller:rst_controller| ; 1 (1) ; 3 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|altera_reset_controller:rst_controller ; ; +; |altera_reset_synchronizer:alt_rst_sync_uq1| ; 0 (0) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1 ; ; +; |system_addr_router:addr_router| ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_addr_router:addr_router ; ; +; |system_addr_router_001:addr_router_001| ; 36 (36) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_addr_router_001:addr_router_001 ; ; +; |system_cmd_xbar_demux:cmd_xbar_demux| ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_cmd_xbar_demux:cmd_xbar_demux ; ; +; |system_cmd_xbar_demux_001:cmd_xbar_demux_001| ; 22 (22) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_cmd_xbar_demux_001:cmd_xbar_demux_001 ; ; +; |system_cmd_xbar_mux:cmd_xbar_mux_001| ; 50 (46) ; 5 (3) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux_001 ; ; +; |altera_merlin_arbitrator:arb| ; 4 (4) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux_001|altera_merlin_arbitrator:arb ; ; +; |system_cmd_xbar_mux:cmd_xbar_mux| ; 55 (50) ; 5 (3) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux ; ; +; |altera_merlin_arbitrator:arb| ; 5 (5) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux|altera_merlin_arbitrator:arb ; ; +; |system_cpu:cpu| ; 2109 (1804) ; 1622 (1436) ; 116736 ; 4 ; 0 ; 2 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_cpu:cpu ; ; +; |lpm_add_sub:Add17| ; 66 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|lpm_add_sub:Add17 ; ; +; |add_sub_qvi:auto_generated| ; 66 (66) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|lpm_add_sub:Add17|add_sub_qvi:auto_generated ; ; +; |system_cpu_bht_module:system_cpu_bht| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_bht_module:system_cpu_bht ; ; +; |altsyncram:the_altsyncram| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_bht_module:system_cpu_bht|altsyncram:the_altsyncram ; ; +; |altsyncram_fhg1:auto_generated| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_bht_module:system_cpu_bht|altsyncram:the_altsyncram|altsyncram_fhg1:auto_generated ; ; +; |system_cpu_dc_data_module:system_cpu_dc_data| ; 0 (0) ; 0 (0) ; 32768 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_dc_data_module:system_cpu_dc_data ; ; +; |altsyncram:the_altsyncram| ; 0 (0) ; 0 (0) ; 32768 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_dc_data_module:system_cpu_dc_data|altsyncram:the_altsyncram ; ; +; |altsyncram_2jf1:auto_generated| ; 0 (0) ; 0 (0) ; 32768 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_dc_data_module:system_cpu_dc_data|altsyncram:the_altsyncram|altsyncram_2jf1:auto_generated ; ; +; |system_cpu_dc_tag_module:system_cpu_dc_tag| ; 0 (0) ; 0 (0) ; 2048 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_dc_tag_module:system_cpu_dc_tag ; ; +; |altsyncram:the_altsyncram| ; 0 (0) ; 0 (0) ; 2048 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_dc_tag_module:system_cpu_dc_tag|altsyncram:the_altsyncram ; ; +; |altsyncram_d9g1:auto_generated| ; 0 (0) ; 0 (0) ; 2048 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_dc_tag_module:system_cpu_dc_tag|altsyncram:the_altsyncram|altsyncram_d9g1:auto_generated ; ; +; |system_cpu_dc_victim_module:system_cpu_dc_victim| ; 0 (0) ; 0 (0) ; 256 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_dc_victim_module:system_cpu_dc_victim ; ; +; |altsyncram:the_altsyncram| ; 0 (0) ; 0 (0) ; 256 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_dc_victim_module:system_cpu_dc_victim|altsyncram:the_altsyncram ; ; +; |altsyncram_r3d1:auto_generated| ; 0 (0) ; 0 (0) ; 256 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_dc_victim_module:system_cpu_dc_victim|altsyncram:the_altsyncram|altsyncram_r3d1:auto_generated ; ; +; |system_cpu_ic_data_module:system_cpu_ic_data| ; 1 (0) ; 1 (0) ; 65536 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data ; ; +; |altsyncram:the_altsyncram| ; 1 (0) ; 1 (0) ; 65536 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram ; ; +; |altsyncram_sjd1:auto_generated| ; 1 (1) ; 1 (1) ; 65536 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated ; ; +; |system_cpu_ic_tag_module:system_cpu_ic_tag| ; 0 (0) ; 0 (0) ; 5376 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag ; ; +; |altsyncram:the_altsyncram| ; 0 (0) ; 0 (0) ; 5376 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram ; ; +; |altsyncram_qtg1:auto_generated| ; 0 (0) ; 0 (0) ; 5376 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated ; ; +; |system_cpu_mult_cell:the_system_cpu_mult_cell| ; 0 (0) ; 0 (0) ; 0 ; 4 ; 0 ; 2 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell ; ; +; |altmult_add:the_altmult_add_part_1| ; 0 (0) ; 0 (0) ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1 ; ; +; |mult_add_75u2:auto_generated| ; 0 (0) ; 0 (0) ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated ; ; +; |ded_mult_ks81:ded_mult1| ; 0 (0) ; 0 (0) ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1 ; ; +; |altmult_add:the_altmult_add_part_2| ; 0 (0) ; 0 (0) ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2 ; ; +; |mult_add_95u2:auto_generated| ; 0 (0) ; 0 (0) ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated ; ; +; |ded_mult_ks81:ded_mult1| ; 0 (0) ; 0 (0) ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated|ded_mult_ks81:ded_mult1 ; ; +; |system_cpu_nios2_oci:the_system_cpu_nios2_oci| ; 228 (29) ; 185 (0) ; 8192 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci ; ; +; |system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper| ; 91 (0) ; 96 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper ; ; +; |sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy ; ; +; |system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk| ; 6 (6) ; 49 (45) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk ; ; +; |altera_std_synchronizer:the_altera_std_synchronizer2| ; 0 (0) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer2 ; ; +; |altera_std_synchronizer:the_altera_std_synchronizer3| ; 0 (0) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3 ; ; +; |system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck| ; 81 (81) ; 47 (43) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck ; ; +; |altera_std_synchronizer:the_altera_std_synchronizer1| ; 0 (0) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1 ; ; +; |altera_std_synchronizer:the_altera_std_synchronizer| ; 0 (0) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer ; ; +; |system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg| ; 13 (13) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg ; ; +; |system_cpu_nios2_oci_break:the_system_cpu_nios2_oci_break| ; 32 (32) ; 32 (32) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_break:the_system_cpu_nios2_oci_break ; ; +; |system_cpu_nios2_oci_debug:the_system_cpu_nios2_oci_debug| ; 8 (8) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_debug:the_system_cpu_nios2_oci_debug ; ; +; |system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem| ; 55 (55) ; 44 (44) ; 8192 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem ; ; +; |system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component| ; 0 (0) ; 0 (0) ; 8192 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component ; ; +; |altsyncram:the_altsyncram| ; 0 (0) ; 0 (0) ; 8192 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram ; ; +; |altsyncram_jt72:auto_generated| ; 0 (0) ; 0 (0) ; 8192 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated ; ; +; |system_cpu_register_bank_a_module:system_cpu_register_bank_a| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_register_bank_a_module:system_cpu_register_bank_a ; ; +; |altsyncram:the_altsyncram| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_register_bank_a_module:system_cpu_register_bank_a|altsyncram:the_altsyncram ; ; +; |altsyncram_fvf1:auto_generated| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_register_bank_a_module:system_cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_fvf1:auto_generated ; ; +; |system_cpu_register_bank_b_module:system_cpu_register_bank_b| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_register_bank_b_module:system_cpu_register_bank_b ; ; +; |altsyncram:the_altsyncram| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_register_bank_b_module:system_cpu_register_bank_b|altsyncram:the_altsyncram ; ; +; |altsyncram_gvf1:auto_generated| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_register_bank_b_module:system_cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_gvf1:auto_generated ; ; +; |system_cpu_test_bench:the_system_cpu_test_bench| ; 10 (10) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_test_bench:the_system_cpu_test_bench ; ; +; |system_jtag_uart_0:jtag_uart_0| ; 141 (37) ; 112 (13) ; 1024 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_jtag_uart_0:jtag_uart_0 ; ; +; |alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic| ; 53 (53) ; 59 (59) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic ; ; +; |system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r| ; 26 (0) ; 20 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r ; ; +; |scfifo:rfifo| ; 26 (0) ; 20 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo ; ; +; |scfifo_jr21:auto_generated| ; 26 (0) ; 20 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated ; ; +; |a_dpfifo_q131:dpfifo| ; 26 (0) ; 20 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo ; ; +; |a_fefifo_7cf:fifo_state| ; 14 (8) ; 8 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state ; ; +; |cntr_do7:count_usedw| ; 6 (6) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw ; ; +; |cntr_1ob:rd_ptr_count| ; 6 (6) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:rd_ptr_count ; ; +; |cntr_1ob:wr_ptr| ; 6 (6) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr ; ; +; |dpram_nl21:FIFOram| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram ; ; +; |altsyncram_r1m1:altsyncram1| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1 ; ; +; |system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w| ; 25 (0) ; 20 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w ; ; +; |scfifo:wfifo| ; 25 (0) ; 20 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo ; ; +; |scfifo_jr21:auto_generated| ; 25 (0) ; 20 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated ; ; +; |a_dpfifo_q131:dpfifo| ; 25 (0) ; 20 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo ; ; +; |a_fefifo_7cf:fifo_state| ; 13 (7) ; 8 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state ; ; +; |cntr_do7:count_usedw| ; 6 (6) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw ; ; +; |cntr_1ob:rd_ptr_count| ; 6 (6) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:rd_ptr_count ; ; +; |cntr_1ob:wr_ptr| ; 6 (6) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr ; ; +; |dpram_nl21:FIFOram| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram ; ; +; |altsyncram_r1m1:altsyncram1| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1 ; ; +; |system_pio_key:pio_key| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_pio_key:pio_key ; ; +; |system_pio_led:pio_led| ; 24 (24) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_pio_led:pio_led ; ; +; |system_pio_motor_rst:pio_motor_rst| ; 4 (4) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_pio_motor_rst:pio_motor_rst ; ; +; |system_pio_sw:pio_sw| ; 4 (4) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_pio_sw:pio_sw ; ; +; |system_rs232_motor:rs232_motor| ; 244 (34) ; 176 (33) ; 2048 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_rs232_motor:rs232_motor ; ; +; |altera_up_rs232_in_deserializer:RS232_In_Deserializer| ; 106 (22) ; 71 (18) ; 1024 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer ; ; +; |altera_up_rs232_counters:RS232_In_Counters| ; 32 (32) ; 20 (20) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_rs232_counters:RS232_In_Counters ; ; +; |altera_up_sync_fifo:RS232_In_FIFO| ; 52 (0) ; 33 (0) ; 1024 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO ; ; +; |scfifo:Sync_FIFO| ; 52 (0) ; 33 (0) ; 1024 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO ; ; +; |scfifo_a341:auto_generated| ; 52 (0) ; 33 (0) ; 1024 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated ; ; +; |a_dpfifo_tq31:dpfifo| ; 52 (29) ; 33 (13) ; 1024 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo ; ; +; |altsyncram_je81:FIFOram| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram ; ; +; |cntr_0ab:wr_ptr| ; 8 (8) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr ; ; +; |cntr_ca7:usedw_counter| ; 8 (8) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_ca7:usedw_counter ; ; +; |cntr_v9b:rd_ptr_msb| ; 7 (7) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_v9b:rd_ptr_msb ; ; +; |altera_up_rs232_out_serializer:RS232_Out_Serializer| ; 104 (23) ; 72 (19) ; 1024 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer ; ; +; |altera_up_rs232_counters:RS232_Out_Counters| ; 30 (30) ; 20 (20) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_rs232_counters:RS232_Out_Counters ; ; +; |altera_up_sync_fifo:RS232_Out_FIFO| ; 51 (0) ; 33 (0) ; 1024 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO ; ; +; |scfifo:Sync_FIFO| ; 51 (0) ; 33 (0) ; 1024 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO ; ; +; |scfifo_a341:auto_generated| ; 51 (0) ; 33 (0) ; 1024 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated ; ; +; |a_dpfifo_tq31:dpfifo| ; 51 (28) ; 33 (13) ; 1024 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo ; ; +; |altsyncram_je81:FIFOram| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram ; ; +; |cntr_0ab:wr_ptr| ; 8 (8) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr ; ; +; |cntr_ca7:usedw_counter| ; 8 (8) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_ca7:usedw_counter ; ; +; |cntr_v9b:rd_ptr_msb| ; 7 (7) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_v9b:rd_ptr_msb ; ; +; |system_rsp_xbar_demux:rsp_xbar_demux_001| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_rsp_xbar_demux:rsp_xbar_demux_001 ; ; +; |system_rsp_xbar_demux:rsp_xbar_demux| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_rsp_xbar_demux:rsp_xbar_demux ; ; +; |system_rsp_xbar_mux:rsp_xbar_mux| ; 34 (34) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_rsp_xbar_mux:rsp_xbar_mux ; ; +; |system_rsp_xbar_mux_001:rsp_xbar_mux_001| ; 121 (121) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_rsp_xbar_mux_001:rsp_xbar_mux_001 ; ; +; |system_sdram:sdram| ; 275 (221) ; 245 (157) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_sdram:sdram ; ; +; |system_sdram_input_efifo_module:the_system_sdram_input_efifo_module| ; 54 (54) ; 88 (88) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module ; ; +; |system_sys_clk_timer:sys_clk_timer| ; 126 (126) ; 120 (120) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_sys_clk_timer:sys_clk_timer ; ; +; |system_uart_0:uart_0| ; 161 (0) ; 128 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_uart_0:uart_0 ; ; +; |system_uart_0_regs:the_system_uart_0_regs| ; 53 (53) ; 51 (51) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_uart_0:uart_0|system_uart_0_regs:the_system_uart_0_regs ; ; +; |system_uart_0_rx:the_system_uart_0_rx| ; 62 (62) ; 44 (42) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_uart_0:uart_0|system_uart_0_rx:the_system_uart_0_rx ; ; +; |altera_std_synchronizer:the_altera_std_synchronizer| ; 0 (0) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_uart_0:uart_0|system_uart_0_rx:the_system_uart_0_rx|altera_std_synchronizer:the_altera_std_synchronizer ; ; +; |system_uart_0_tx:the_system_uart_0_tx| ; 46 (46) ; 33 (33) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_uart_0:uart_0|system_uart_0_tx:the_system_uart_0_tx ; ; ++-----------------------------------------------------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis RAM Summary ; ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+----------------------------------------+ +; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ; ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+----------------------------------------+ +; system:inst_cpu|system_cpu:cpu|system_cpu_bht_module:system_cpu_bht|altsyncram:the_altsyncram|altsyncram_fhg1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 256 ; 2 ; 256 ; 2 ; 512 ; system_cpu_bht_ram.mif ; +; system:inst_cpu|system_cpu:cpu|system_cpu_dc_data_module:system_cpu_dc_data|altsyncram:the_altsyncram|altsyncram_2jf1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 1024 ; 32 ; 1024 ; 32 ; 32768 ; None ; +; system:inst_cpu|system_cpu:cpu|system_cpu_dc_tag_module:system_cpu_dc_tag|altsyncram:the_altsyncram|altsyncram_d9g1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 128 ; 16 ; 128 ; 16 ; 2048 ; system_cpu_dc_tag_ram.mif ; +; system:inst_cpu|system_cpu:cpu|system_cpu_dc_victim_module:system_cpu_dc_victim|altsyncram:the_altsyncram|altsyncram_r3d1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 8 ; 32 ; 8 ; 32 ; 256 ; None ; +; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 2048 ; 32 ; 2048 ; 32 ; 65536 ; None ; +; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 256 ; 21 ; 256 ; 21 ; 5376 ; system_cpu_ic_tag_ram.mif ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port ; 256 ; 32 ; 256 ; 32 ; 8192 ; system_cpu_ociram_default_contents.mif ; +; system:inst_cpu|system_cpu:cpu|system_cpu_register_bank_a_module:system_cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_fvf1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 32 ; 32 ; 32 ; 32 ; 1024 ; system_cpu_rf_ram_a.mif ; +; system:inst_cpu|system_cpu:cpu|system_cpu_register_bank_b_module:system_cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_gvf1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 32 ; 32 ; 32 ; 32 ; 1024 ; system_cpu_rf_ram_b.mif ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 64 ; 8 ; 64 ; 8 ; 512 ; None ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 64 ; 8 ; 64 ; 8 ; 512 ; None ; +; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 128 ; 8 ; 128 ; 8 ; 1024 ; None ; +; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 128 ; 8 ; 128 ; 8 ; 1024 ; None ; ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+----------------------------------------+ + + ++-----------------------------------------------------+ +; Analysis & Synthesis DSP Block Usage Summary ; ++---------------------------------------+-------------+ +; Statistic ; Number Used ; ++---------------------------------------+-------------+ +; Simple Multipliers (9-bit) ; 0 ; +; Simple Multipliers (18-bit) ; 2 ; +; Embedded Multiplier Blocks ; -- ; +; Embedded Multiplier 9-bit elements ; 4 ; +; Signed Embedded Multipliers ; 0 ; +; Unsigned Embedded Multipliers ; 2 ; +; Mixed Sign Embedded Multipliers ; 0 ; +; Variable Sign Embedded Multipliers ; 0 ; +; Dedicated Input Shift Register Chains ; 0 ; ++---------------------------------------+-------------+ +Note: number of Embedded Multiplier Blocks used is only available after a successful fit. + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis IP Cores Summary ; ++--------+------------------------------------+---------+--------------+--------------+------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------+ +; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance ; IP Include File ; ++--------+------------------------------------+---------+--------------+--------------+------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------+ +; Altera ; qsys ; 12.1sp1 ; N/A ; N/A ; |de0_nano_system|system:inst_cpu ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.v ; +; Altera ; altera_merlin_router ; 12.1 ; N/A ; N/A ; |de0_nano_system|system:inst_cpu|system_addr_router:addr_router ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_addr_router.sv ; +; Altera ; altera_merlin_router ; 12.1 ; N/A ; N/A ; |de0_nano_system|system:inst_cpu|system_addr_router_001:addr_router_001 ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_addr_router_001.sv ; +; Altera ; altera_merlin_burst_adapter ; 12.1 ; N/A ; N/A ; |de0_nano_system|system:inst_cpu|altera_merlin_burst_adapter:burst_adapter ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_burst_adapter.sv ; +; Altera ; altera_merlin_demultiplexer ; 12.1 ; N/A ; N/A ; |de0_nano_system|system:inst_cpu|system_cmd_xbar_demux:cmd_xbar_demux ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cmd_xbar_demux.sv ; +; Altera ; altera_merlin_demultiplexer ; 12.1 ; N/A ; N/A ; |de0_nano_system|system:inst_cpu|system_cmd_xbar_demux_001:cmd_xbar_demux_001 ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cmd_xbar_demux_001.sv ; +; Altera ; altera_merlin_multiplexer ; 12.1 ; N/A ; N/A ; |de0_nano_system|system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cmd_xbar_mux.sv ; +; Altera ; altera_merlin_multiplexer ; 12.1 ; N/A ; N/A ; |de0_nano_system|system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux_001 ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cmd_xbar_mux.sv ; +; Altera ; Nios II Processor (6AF7_00A2) ; N/A ; Apr 2009 ; Licensed ; |de0_nano_system|system:inst_cpu|system_cpu:cpu ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v ; +; Altera ; altera_merlin_master_translator ; 12.1 ; N/A ; N/A ; |de0_nano_system|system:inst_cpu|altera_merlin_master_translator:cpu_data_master_translator ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_master_translator.sv ; +; Altera ; altera_merlin_master_agent ; 12.1 ; N/A ; N/A ; |de0_nano_system|system:inst_cpu|altera_merlin_master_agent:cpu_data_master_translator_avalon_universal_master_0_agent ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_master_agent.sv ; +; Altera ; altera_merlin_master_translator ; 12.1 ; N/A ; N/A ; |de0_nano_system|system:inst_cpu|altera_merlin_master_translator:cpu_instruction_master_translator ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_master_translator.sv ; +; Altera ; altera_merlin_master_agent ; 12.1 ; N/A ; N/A ; |de0_nano_system|system:inst_cpu|altera_merlin_master_agent:cpu_instruction_master_translator_avalon_universal_master_0_agent ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_master_agent.sv ; +; Altera ; altera_merlin_slave_translator ; 12.1 ; N/A ; N/A ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_translator:cpu_jtag_debug_module_translator ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_slave_translator.sv ; +; Altera ; altera_merlin_slave_agent ; 12.1 ; N/A ; N/A ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_agent:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_slave_agent.sv ; +; Altera ; altera_avalon_sc_fifo ; 12.1 ; N/A ; N/A ; |de0_nano_system|system:inst_cpu|altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_avalon_sc_fifo.v ; +; Altera ; altera_merlin_router ; 12.1 ; N/A ; N/A ; |de0_nano_system|system:inst_cpu|system_id_router:id_router ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_id_router.sv ; +; Altera ; altera_merlin_router ; 12.1 ; N/A ; N/A ; |de0_nano_system|system:inst_cpu|system_id_router_001:id_router_001 ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_id_router_001.sv ; +; Altera ; altera_merlin_router ; 12.1 ; N/A ; N/A ; |de0_nano_system|system:inst_cpu|system_id_router_002:id_router_002 ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_id_router_002.sv ; +; Altera ; altera_merlin_router ; 12.1 ; N/A ; N/A ; |de0_nano_system|system:inst_cpu|system_id_router_002:id_router_003 ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_id_router_002.sv ; +; Altera ; altera_merlin_router ; 12.1 ; N/A ; N/A ; |de0_nano_system|system:inst_cpu|system_id_router_002:id_router_004 ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_id_router_002.sv ; +; Altera ; altera_merlin_router ; 12.1 ; N/A ; N/A ; |de0_nano_system|system:inst_cpu|system_id_router_002:id_router_005 ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_id_router_002.sv ; +; Altera ; altera_merlin_router ; 12.1 ; N/A ; N/A ; |de0_nano_system|system:inst_cpu|system_id_router_002:id_router_006 ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_id_router_002.sv ; +; Altera ; altera_merlin_router ; 12.1 ; N/A ; N/A ; |de0_nano_system|system:inst_cpu|system_id_router_002:id_router_007 ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_id_router_002.sv ; +; Altera ; altera_merlin_router ; 12.1 ; N/A ; N/A ; |de0_nano_system|system:inst_cpu|system_id_router_002:id_router_008 ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_id_router_002.sv ; +; Altera ; altera_merlin_router ; 12.1 ; N/A ; N/A ; |de0_nano_system|system:inst_cpu|system_id_router_002:id_router_009 ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_id_router_002.sv ; +; Altera ; altera_merlin_router ; 12.1 ; N/A ; N/A ; |de0_nano_system|system:inst_cpu|system_id_router_002:id_router_010 ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_id_router_002.sv ; +; Altera ; altera_irq_mapper ; 12.1 ; N/A ; N/A ; |de0_nano_system|system:inst_cpu|system_irq_mapper:irq_mapper ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_irq_mapper.sv ; +; Altera ; altera_avalon_jtag_uart ; 12.1 ; N/A ; N/A ; |de0_nano_system|system:inst_cpu|system_jtag_uart_0:jtag_uart_0 ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_jtag_uart_0.v ; +; Altera ; altera_merlin_slave_translator ; 12.1 ; N/A ; N/A ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_translator:jtag_uart_0_avalon_jtag_slave_translator ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_slave_translator.sv ; +; Altera ; altera_merlin_slave_agent ; 12.1 ; N/A ; N/A ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_agent:jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_slave_agent.sv ; +; Altera ; altera_avalon_sc_fifo ; 12.1 ; N/A ; N/A ; |de0_nano_system|system:inst_cpu|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_avalon_sc_fifo.v ; +; Altera ; altera_merlin_traffic_limiter ; 12.1 ; N/A ; N/A ; |de0_nano_system|system:inst_cpu|altera_merlin_traffic_limiter:limiter ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_traffic_limiter.sv ; +; Altera ; altera_merlin_traffic_limiter ; 12.1 ; N/A ; N/A ; |de0_nano_system|system:inst_cpu|altera_merlin_traffic_limiter:limiter_001 ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_traffic_limiter.sv ; +; Altera ; altera_avalon_pio ; 12.1 ; N/A ; N/A ; |de0_nano_system|system:inst_cpu|system_pio_key:pio_key ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_pio_key.v ; +; Altera ; altera_merlin_slave_translator ; 12.1 ; N/A ; N/A ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_translator:pio_key_s1_translator ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_slave_translator.sv ; +; Altera ; altera_merlin_slave_agent ; 12.1 ; N/A ; N/A ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_agent:pio_key_s1_translator_avalon_universal_slave_0_agent ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_slave_agent.sv ; +; Altera ; altera_avalon_sc_fifo ; 12.1 ; N/A ; N/A ; |de0_nano_system|system:inst_cpu|altera_avalon_sc_fifo:pio_key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_avalon_sc_fifo.v ; +; Altera ; altera_avalon_pio ; 12.1 ; N/A ; N/A ; |de0_nano_system|system:inst_cpu|system_pio_led:pio_led ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_pio_led.v ; +; Altera ; altera_merlin_slave_translator ; 12.1 ; N/A ; N/A ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_translator:pio_led_s1_translator ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_slave_translator.sv ; +; Altera ; altera_merlin_slave_agent ; 12.1 ; N/A ; N/A ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_agent:pio_led_s1_translator_avalon_universal_slave_0_agent ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_slave_agent.sv ; +; Altera ; altera_avalon_sc_fifo ; 12.1 ; N/A ; N/A ; |de0_nano_system|system:inst_cpu|altera_avalon_sc_fifo:pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_avalon_sc_fifo.v ; +; Altera ; altera_avalon_pio ; 12.1 ; N/A ; N/A ; |de0_nano_system|system:inst_cpu|system_pio_motor_rst:pio_motor_rst ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_pio_motor_rst.v ; +; Altera ; altera_merlin_slave_translator ; 12.1 ; N/A ; N/A ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_translator:pio_motor_rst_s1_translator ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_slave_translator.sv ; +; Altera ; altera_merlin_slave_agent ; 12.1 ; N/A ; N/A ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_agent:pio_motor_rst_s1_translator_avalon_universal_slave_0_agent ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_slave_agent.sv ; +; Altera ; altera_avalon_sc_fifo ; 12.1 ; N/A ; N/A ; |de0_nano_system|system:inst_cpu|altera_avalon_sc_fifo:pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_avalon_sc_fifo.v ; +; Altera ; altera_avalon_pio ; 12.1 ; N/A ; N/A ; |de0_nano_system|system:inst_cpu|system_pio_sw:pio_sw ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_pio_sw.v ; +; Altera ; altera_merlin_slave_translator ; 12.1 ; N/A ; N/A ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_translator:pio_sw_s1_translator ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_slave_translator.sv ; +; Altera ; altera_merlin_slave_agent ; 12.1 ; N/A ; N/A ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_agent:pio_sw_s1_translator_avalon_universal_slave_0_agent ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_slave_agent.sv ; +; Altera ; altera_avalon_sc_fifo ; 12.1 ; N/A ; N/A ; |de0_nano_system|system:inst_cpu|altera_avalon_sc_fifo:pio_sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_avalon_sc_fifo.v ; +; Altera ; altera_merlin_slave_translator ; 12.1 ; N/A ; N/A ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_translator:rs232_motor_avalon_rs232_slave_translator ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_slave_translator.sv ; +; Altera ; altera_merlin_slave_agent ; 12.1 ; N/A ; N/A ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_agent:rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_slave_agent.sv ; +; Altera ; altera_avalon_sc_fifo ; 12.1 ; N/A ; N/A ; |de0_nano_system|system:inst_cpu|altera_avalon_sc_fifo:rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_avalon_sc_fifo.v ; +; Altera ; altera_merlin_demultiplexer ; 12.1 ; N/A ; N/A ; |de0_nano_system|system:inst_cpu|system_rsp_xbar_demux:rsp_xbar_demux ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_rsp_xbar_demux.sv ; +; Altera ; altera_merlin_demultiplexer ; 12.1 ; N/A ; N/A ; |de0_nano_system|system:inst_cpu|system_rsp_xbar_demux:rsp_xbar_demux_001 ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_rsp_xbar_demux.sv ; +; Altera ; altera_merlin_demultiplexer ; 12.1 ; N/A ; N/A ; |de0_nano_system|system:inst_cpu|system_rsp_xbar_demux_002:rsp_xbar_demux_002 ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_rsp_xbar_demux_002.sv ; +; Altera ; altera_merlin_demultiplexer ; 12.1 ; N/A ; N/A ; |de0_nano_system|system:inst_cpu|system_rsp_xbar_demux_002:rsp_xbar_demux_003 ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_rsp_xbar_demux_002.sv ; +; Altera ; altera_merlin_demultiplexer ; 12.1 ; N/A ; N/A ; |de0_nano_system|system:inst_cpu|system_rsp_xbar_demux_002:rsp_xbar_demux_004 ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_rsp_xbar_demux_002.sv ; +; Altera ; altera_merlin_demultiplexer ; 12.1 ; N/A ; N/A ; |de0_nano_system|system:inst_cpu|system_rsp_xbar_demux_002:rsp_xbar_demux_005 ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_rsp_xbar_demux_002.sv ; +; Altera ; altera_merlin_demultiplexer ; 12.1 ; N/A ; N/A ; |de0_nano_system|system:inst_cpu|system_rsp_xbar_demux_002:rsp_xbar_demux_006 ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_rsp_xbar_demux_002.sv ; +; Altera ; altera_merlin_demultiplexer ; 12.1 ; N/A ; N/A ; |de0_nano_system|system:inst_cpu|system_rsp_xbar_demux_002:rsp_xbar_demux_007 ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_rsp_xbar_demux_002.sv ; +; Altera ; altera_merlin_demultiplexer ; 12.1 ; N/A ; N/A ; |de0_nano_system|system:inst_cpu|system_rsp_xbar_demux_002:rsp_xbar_demux_008 ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_rsp_xbar_demux_002.sv ; +; Altera ; altera_merlin_demultiplexer ; 12.1 ; N/A ; N/A ; |de0_nano_system|system:inst_cpu|system_rsp_xbar_demux_002:rsp_xbar_demux_009 ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_rsp_xbar_demux_002.sv ; +; Altera ; altera_merlin_demultiplexer ; 12.1 ; N/A ; N/A ; |de0_nano_system|system:inst_cpu|system_rsp_xbar_demux_002:rsp_xbar_demux_010 ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_rsp_xbar_demux_002.sv ; +; Altera ; altera_merlin_multiplexer ; 12.1 ; N/A ; N/A ; |de0_nano_system|system:inst_cpu|system_rsp_xbar_mux:rsp_xbar_mux ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_rsp_xbar_mux.sv ; +; Altera ; altera_merlin_multiplexer ; 12.1 ; N/A ; N/A ; |de0_nano_system|system:inst_cpu|system_rsp_xbar_mux_001:rsp_xbar_mux_001 ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_rsp_xbar_mux_001.sv ; +; Altera ; altera_reset_controller ; 12.1 ; N/A ; N/A ; |de0_nano_system|system:inst_cpu|altera_reset_controller:rst_controller ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_reset_controller.v ; +; Altera ; altera_avalon_new_sdram_controller ; 12.1 ; N/A ; N/A ; |de0_nano_system|system:inst_cpu|system_sdram:sdram ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_sdram.v ; +; Altera ; altera_merlin_slave_translator ; 12.1 ; N/A ; N/A ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_translator:sdram_s1_translator ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_slave_translator.sv ; +; Altera ; altera_merlin_slave_agent ; 12.1 ; N/A ; N/A ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_slave_agent.sv ; +; Altera ; altera_avalon_sc_fifo ; 12.1 ; N/A ; N/A ; |de0_nano_system|system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_avalon_sc_fifo.v ; +; Altera ; altera_avalon_timer ; 12.1 ; N/A ; N/A ; |de0_nano_system|system:inst_cpu|system_sys_clk_timer:sys_clk_timer ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_sys_clk_timer.v ; +; Altera ; altera_merlin_slave_translator ; 12.1 ; N/A ; N/A ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_translator:sys_clk_timer_s1_translator ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_slave_translator.sv ; +; Altera ; altera_merlin_slave_agent ; 12.1 ; N/A ; N/A ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_agent:sys_clk_timer_s1_translator_avalon_universal_slave_0_agent ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_slave_agent.sv ; +; Altera ; altera_avalon_sc_fifo ; 12.1 ; N/A ; N/A ; |de0_nano_system|system:inst_cpu|altera_avalon_sc_fifo:sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_avalon_sc_fifo.v ; +; Altera ; altera_avalon_sysid_qsys ; 12.1 ; N/A ; N/A ; |de0_nano_system|system:inst_cpu|system_sysid:sysid ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_sysid.v ; +; Altera ; altera_merlin_slave_translator ; 12.1 ; N/A ; N/A ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_translator:sysid_control_slave_translator ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_slave_translator.sv ; +; Altera ; altera_merlin_slave_agent ; 12.1 ; N/A ; N/A ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_agent:sysid_control_slave_translator_avalon_universal_slave_0_agent ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_slave_agent.sv ; +; Altera ; altera_avalon_sc_fifo ; 12.1 ; N/A ; N/A ; |de0_nano_system|system:inst_cpu|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_avalon_sc_fifo.v ; +; Altera ; altera_avalon_uart ; 12.1 ; N/A ; N/A ; |de0_nano_system|system:inst_cpu|system_uart_0:uart_0 ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_uart_0.v ; +; Altera ; altera_merlin_slave_translator ; 12.1 ; N/A ; N/A ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_translator:uart_0_s1_translator ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_slave_translator.sv ; +; Altera ; altera_merlin_slave_agent ; 12.1 ; N/A ; N/A ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_agent:uart_0_s1_translator_avalon_universal_slave_0_agent ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_slave_agent.sv ; +; Altera ; altera_avalon_sc_fifo ; 12.1 ; N/A ; N/A ; |de0_nano_system|system:inst_cpu|altera_avalon_sc_fifo:uart_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_avalon_sc_fifo.v ; +; Altera ; altera_merlin_width_adapter ; 12.1 ; N/A ; N/A ; |de0_nano_system|system:inst_cpu|altera_merlin_width_adapter:width_adapter ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_width_adapter.sv ; +; Altera ; altera_merlin_width_adapter ; 12.1 ; N/A ; N/A ; |de0_nano_system|system:inst_cpu|altera_merlin_width_adapter:width_adapter_001 ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_width_adapter.sv ; +; Altera ; ALTPLL ; 12.1 ; N/A ; N/A ; |de0_nano_system|pll_sys:inst_pll_sys ; C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/pll_sys.vhd ; ++--------+------------------------------------+---------+--------------+--------------+------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------+ + + +Encoding Type: One-Hot ++----------------------------------------------------------------------------------------------+ +; State Machine - |de0_nano_system|system:inst_cpu|system_sdram:sdram|m_next ; ++------------------+------------------+------------------+------------------+------------------+ +; Name ; m_next.010000000 ; m_next.000010000 ; m_next.000001000 ; m_next.000000001 ; ++------------------+------------------+------------------+------------------+------------------+ +; m_next.000000001 ; 0 ; 0 ; 0 ; 0 ; +; m_next.000001000 ; 0 ; 0 ; 1 ; 1 ; +; m_next.000010000 ; 0 ; 1 ; 0 ; 1 ; +; m_next.010000000 ; 1 ; 0 ; 0 ; 1 ; ++------------------+------------------+------------------+------------------+------------------+ + + +Encoding Type: One-Hot ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; State Machine - |de0_nano_system|system:inst_cpu|system_sdram:sdram|m_state ; ++-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+ +; Name ; m_state.100000000 ; m_state.010000000 ; m_state.001000000 ; m_state.000100000 ; m_state.000010000 ; m_state.000001000 ; m_state.000000100 ; m_state.000000010 ; m_state.000000001 ; ++-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+ +; m_state.000000001 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; m_state.000000010 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 ; +; m_state.000000100 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 1 ; +; m_state.000001000 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 1 ; +; m_state.000010000 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 1 ; +; m_state.000100000 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; m_state.001000000 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; m_state.010000000 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; m_state.100000000 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; ++-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+ + + +Encoding Type: One-Hot ++----------------------------------------------------------------------------+ +; State Machine - |de0_nano_system|system:inst_cpu|system_sdram:sdram|i_next ; ++------------+------------+------------+------------+------------------------+ +; Name ; i_next.111 ; i_next.101 ; i_next.010 ; i_next.000 ; ++------------+------------+------------+------------+------------------------+ +; i_next.000 ; 0 ; 0 ; 0 ; 0 ; +; i_next.010 ; 0 ; 0 ; 1 ; 1 ; +; i_next.101 ; 0 ; 1 ; 0 ; 1 ; +; i_next.111 ; 1 ; 0 ; 0 ; 1 ; ++------------+------------+------------+------------+------------------------+ + + +Encoding Type: One-Hot ++-------------------------------------------------------------------------------------------------+ +; State Machine - |de0_nano_system|system:inst_cpu|system_sdram:sdram|i_state ; ++-------------+-------------+-------------+-------------+-------------+-------------+-------------+ +; Name ; i_state.111 ; i_state.101 ; i_state.011 ; i_state.010 ; i_state.001 ; i_state.000 ; ++-------------+-------------+-------------+-------------+-------------+-------------+-------------+ +; i_state.000 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; i_state.001 ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 ; +; i_state.010 ; 0 ; 0 ; 0 ; 1 ; 0 ; 1 ; +; i_state.011 ; 0 ; 0 ; 1 ; 0 ; 0 ; 1 ; +; i_state.101 ; 0 ; 1 ; 0 ; 0 ; 0 ; 1 ; +; i_state.111 ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ; ++-------------+-------------+-------------+-------------+-------------+-------------+-------------+ + + +Encoding Type: One-Hot ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; State Machine - |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|DRsize ; ++------------+------------+------------+------------+------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Name ; DRsize.101 ; DRsize.100 ; DRsize.011 ; DRsize.010 ; DRsize.001 ; DRsize.000 ; ++------------+------------+------------+------------+------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; DRsize.000 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; DRsize.001 ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 ; +; DRsize.010 ; 0 ; 0 ; 0 ; 1 ; 0 ; 1 ; +; DRsize.011 ; 0 ; 0 ; 1 ; 0 ; 0 ; 1 ; +; DRsize.100 ; 0 ; 1 ; 0 ; 0 ; 0 ; 1 ; +; DRsize.101 ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ; ++------------+------------+------------+------------+------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Registers Protected by Synthesis ; ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+ +; Register Name ; Protected by Synthesis Attribute or Preserve Register Assignment ; Not to be Touched by Netlist Optimizations ; ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+ +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|dreg[0] ; yes ; yes ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer|dreg[0] ; yes ; yes ; +; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[0] ; yes ; yes ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|din_s1 ; yes ; yes ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 ; yes ; yes ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|tck_t_dav ; yes ; yes ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|rvalid ; yes ; yes ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|user_saw_rvalid ; yes ; yes ; +; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1] ; yes ; yes ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|write_stalled ; yes ; yes ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|rdata[7] ; yes ; yes ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|rdata[0] ; yes ; yes ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|read_req ; yes ; yes ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer2|dreg[0] ; yes ; yes ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3|dreg[0] ; yes ; yes ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|rdata[1] ; yes ; yes ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|read ; yes ; yes ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer2|din_s1 ; yes ; yes ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3|din_s1 ; yes ; yes ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|write_valid ; yes ; yes ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|rdata[2] ; yes ; yes ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|write ; yes ; yes ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|rdata[3] ; yes ; yes ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|wdata[4] ; yes ; yes ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|wdata[3] ; yes ; yes ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|wdata[2] ; yes ; yes ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|wdata[0] ; yes ; yes ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|wdata[7] ; yes ; yes ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|wdata[6] ; yes ; yes ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|wdata[5] ; yes ; yes ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|wdata[1] ; yes ; yes ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|rdata[4] ; yes ; yes ; +; system:inst_cpu|system_uart_0:uart_0|system_uart_0_rx:the_system_uart_0_rx|altera_std_synchronizer:the_altera_std_synchronizer|dreg[0] ; yes ; yes ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|jupdate ; yes ; yes ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|rdata[5] ; yes ; yes ; +; system:inst_cpu|system_uart_0:uart_0|system_uart_0_rx:the_system_uart_0_rx|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 ; yes ; yes ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|rdata[6] ; yes ; yes ; ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Registers Removed During Synthesis ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Register name ; Reason for Removal ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_itrace:the_system_cpu_nios2_oci_itrace|itm[0..35] ; Lost fanout ; +; system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux_001|locked[0,1] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux|locked[0,1] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_merlin_slave_translator:rs232_motor_avalon_rs232_slave_translator|av_chipselect_pre ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_merlin_slave_translator:pio_motor_rst_s1_translator|av_readdata_pre[1..31] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_merlin_slave_translator:pio_motor_rst_s1_translator|av_chipselect_pre ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_merlin_slave_translator:jtag_uart_0_avalon_jtag_slave_translator|av_readdata_pre[11,23..31] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_merlin_slave_translator:jtag_uart_0_avalon_jtag_slave_translator|av_chipselect_pre ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_merlin_slave_translator:pio_led_s1_translator|av_readdata_pre[7..31] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_merlin_slave_translator:pio_led_s1_translator|av_chipselect_pre ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_merlin_slave_translator:uart_0_s1_translator|av_chipselect_pre ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_merlin_slave_translator:sys_clk_timer_s1_translator|av_chipselect_pre ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_merlin_slave_translator:sysid_control_slave_translator|av_readdata_pre[0,4..6,9,11,12,14,16..18,21..23,26,27,29,31] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_merlin_slave_translator:cpu_jtag_debug_module_translator|av_chipselect_pre ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|system_pio_sw:pio_sw|readdata[4..31] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|system_pio_key:pio_key|readdata[2..31] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|system_sdram:sdram|i_addr[4,5] ; Stuck at VCC due to stuck port data_in ; +; system:inst_cpu|system_cpu:cpu|E_control_reg_rddata[2,3,6..13,15..31] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|system_cpu:cpu|M_control_reg_rddata[2,3,6..13,15..31] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|system_cpu:cpu|E_ctrl_br_always_pred_taken ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|system_cpu:cpu|M_ctrl_br_always_pred_taken ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|trc_im_addr[0..6] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|trc_wrap ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_dbrk:the_system_cpu_nios2_oci_dbrk|dbrk_goto1 ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_dbrk:the_system_cpu_nios2_oci_dbrk|dbrk_break_pulse ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_dbrk:the_system_cpu_nios2_oci_dbrk|dbrk_goto0 ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_xbrk:the_system_cpu_nios2_oci_xbrk|xbrk_break ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_xbrk:the_system_cpu_nios2_oci_xbrk|E_xbrk_goto0 ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_xbrk:the_system_cpu_nios2_oci_xbrk|E_xbrk_goto1 ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_xbrk:the_system_cpu_nios2_oci_xbrk|M_xbrk_goto0 ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_xbrk:the_system_cpu_nios2_oci_xbrk|M_xbrk_goto1 ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_merlin_traffic_limiter:limiter|last_dest_id[1..3] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_merlin_slave_translator:pio_sw_s1_translator|av_readdata_pre[4..31] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_merlin_slave_translator:pio_key_s1_translator|av_readdata_pre[2..31] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_avalon_sc_fifo:rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][86] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][85] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][84] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][83] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][86] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][85] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][84] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][83] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][86] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][85] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][84] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][83] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][86] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][85] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][84] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][83] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][86] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][85] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][84] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][83] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][86] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][85] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][84] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][83] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:pio_sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][86] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:pio_sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][85] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:pio_sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][84] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:pio_sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][83] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:pio_sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][86] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:pio_sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][85] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:pio_sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][84] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:pio_sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][83] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:pio_key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][86] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:pio_key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][85] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:pio_key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][84] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:pio_key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][83] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:pio_key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][86] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:pio_key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][85] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:pio_key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][84] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:pio_key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][83] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][86] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][85] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][84] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][83] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][86] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][85] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][84] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][83] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:uart_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][86] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:uart_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][85] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:uart_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][84] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:uart_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][83] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:uart_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][86] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:uart_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][85] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:uart_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][84] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:uart_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][83] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][86] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][85] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][84] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][83] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][86] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][85] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][84] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][83] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][86] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][85] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][84] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][83] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][86] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][85] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][84] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][83] ; Lost fanout ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|trc_jtag_addr[0..16] ; Lost fanout ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg|oci_ienable[2] ; Merged with system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg|oci_ienable[3] ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg|oci_ienable[3] ; Merged with system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg|oci_ienable[6] ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg|oci_ienable[6] ; Merged with system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg|oci_ienable[7] ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg|oci_ienable[7] ; Merged with system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg|oci_ienable[8] ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg|oci_ienable[8] ; Merged with system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg|oci_ienable[9] ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg|oci_ienable[9] ; Merged with system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg|oci_ienable[10] ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg|oci_ienable[10] ; Merged with system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg|oci_ienable[11] ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg|oci_ienable[11] ; Merged with system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg|oci_ienable[12] ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg|oci_ienable[12] ; Merged with system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg|oci_ienable[13] ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg|oci_ienable[13] ; Merged with system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg|oci_ienable[15] ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg|oci_ienable[15] ; Merged with system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg|oci_ienable[16] ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg|oci_ienable[16] ; Merged with system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg|oci_ienable[17] ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg|oci_ienable[17] ; Merged with system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg|oci_ienable[18] ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg|oci_ienable[18] ; Merged with system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg|oci_ienable[19] ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg|oci_ienable[19] ; Merged with system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg|oci_ienable[20] ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg|oci_ienable[20] ; Merged with system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg|oci_ienable[21] ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg|oci_ienable[21] ; Merged with system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg|oci_ienable[22] ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg|oci_ienable[22] ; Merged with system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg|oci_ienable[23] ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg|oci_ienable[23] ; Merged with system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg|oci_ienable[24] ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg|oci_ienable[24] ; Merged with system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg|oci_ienable[25] ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg|oci_ienable[25] ; Merged with system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg|oci_ienable[26] ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg|oci_ienable[26] ; Merged with system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg|oci_ienable[27] ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg|oci_ienable[27] ; Merged with system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg|oci_ienable[28] ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg|oci_ienable[28] ; Merged with system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg|oci_ienable[29] ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg|oci_ienable[29] ; Merged with system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg|oci_ienable[30] ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg|oci_ienable[30] ; Merged with system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg|oci_ienable[31] ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg|oci_ienable[31] ; Merged with system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg|oci_ienable[0] ; +; system:inst_cpu|altera_merlin_width_adapter:width_adapter|byteen_reg[2] ; Merged with system:inst_cpu|altera_merlin_width_adapter:width_adapter|byteen_reg[3] ; +; system:inst_cpu|altera_merlin_traffic_limiter:limiter|last_channel[1] ; Merged with system:inst_cpu|altera_merlin_traffic_limiter:limiter|last_dest_id[0] ; +; system:inst_cpu|altera_avalon_sc_fifo:rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][70] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][102] ; +; system:inst_cpu|altera_avalon_sc_fifo:rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][68] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][69] ; +; system:inst_cpu|altera_avalon_sc_fifo:pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][70] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][102] ; +; system:inst_cpu|altera_avalon_sc_fifo:pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][69] ; +; system:inst_cpu|altera_avalon_sc_fifo:pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][68] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][69] ; +; system:inst_cpu|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][70] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][102] ; +; system:inst_cpu|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][69] ; +; system:inst_cpu|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][68] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][69] ; +; system:inst_cpu|altera_avalon_sc_fifo:pio_sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][70] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:pio_sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][102] ; +; system:inst_cpu|altera_avalon_sc_fifo:pio_sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][68] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:pio_sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][69] ; +; system:inst_cpu|altera_avalon_sc_fifo:pio_sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:pio_sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][69] ; +; system:inst_cpu|altera_avalon_sc_fifo:pio_key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][70] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:pio_key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][102] ; +; system:inst_cpu|altera_avalon_sc_fifo:pio_key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:pio_key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][69] ; +; system:inst_cpu|altera_avalon_sc_fifo:pio_key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][68] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:pio_key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][69] ; +; system:inst_cpu|altera_avalon_sc_fifo:pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][70] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][102] ; +; system:inst_cpu|altera_avalon_sc_fifo:pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][68] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][69] ; +; system:inst_cpu|altera_avalon_sc_fifo:pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][69] ; +; system:inst_cpu|altera_avalon_sc_fifo:uart_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][70] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:uart_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][102] ; +; system:inst_cpu|altera_avalon_sc_fifo:uart_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:uart_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][69] ; +; system:inst_cpu|altera_avalon_sc_fifo:uart_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][68] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:uart_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][69] ; +; system:inst_cpu|altera_avalon_sc_fifo:sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][70] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][102] ; +; system:inst_cpu|altera_avalon_sc_fifo:sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][69] ; +; system:inst_cpu|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][70] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][102] ; +; system:inst_cpu|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][68] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][69] ; +; system:inst_cpu|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][69] ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][50] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][68] ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][52] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][68] ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][66] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][68] ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][67] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][68] ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][58] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][68] ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][44] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][68] ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][55] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][65] ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][53] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][54] ; +; system:inst_cpu|altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][70] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][102] ; +; system:inst_cpu|altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][68] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][86] ; +; system:inst_cpu|altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][69] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][86] ; +; system:inst_cpu|altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][86] ; +; system:inst_cpu|altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][85] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][86] ; +; system:inst_cpu|altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][84] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][86] ; +; system:inst_cpu|altera_merlin_slave_translator:sysid_control_slave_translator|av_readdata_pre[1..3,7,8,10,13,15,19,20,24,25,28] ; Merged with system:inst_cpu|altera_merlin_slave_translator:sysid_control_slave_translator|av_readdata_pre[30] ; +; system:inst_cpu|system_rs232_motor:rs232_motor|readdata[11..14,24..31] ; Merged with system:inst_cpu|system_rs232_motor:rs232_motor|readdata[10] ; +; system:inst_cpu|system_uart_0:uart_0|system_uart_0_rx:the_system_uart_0_rx|delayed_unxsync_rxdxx2 ; Merged with system:inst_cpu|system_uart_0:uart_0|system_uart_0_rx:the_system_uart_0_rx|delayed_unxsync_rxdxx1 ; +; system:inst_cpu|system_sdram:sdram|i_addr[0..3,6..11] ; Merged with system:inst_cpu|system_sdram:sdram|i_addr[12] ; +; system:inst_cpu|altera_avalon_sc_fifo:rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][62] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][69] ; +; system:inst_cpu|altera_avalon_sc_fifo:sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][68] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][69] ; +; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|p0_reg_bwrap_field[1] ; Merged with system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|p0_reg_bwrap_field[0] ; +; system:inst_cpu|altera_avalon_sc_fifo:rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][70] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][102] ; +; system:inst_cpu|altera_avalon_sc_fifo:rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][68] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62] ; +; system:inst_cpu|altera_avalon_sc_fifo:rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][69] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62] ; +; system:inst_cpu|altera_merlin_slave_agent:rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1] ; Merged with system:inst_cpu|altera_merlin_slave_agent:rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; +; system:inst_cpu|altera_avalon_sc_fifo:pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][70] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][102] ; +; system:inst_cpu|altera_avalon_sc_fifo:pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][68] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62] ; +; system:inst_cpu|altera_avalon_sc_fifo:pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][69] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62] ; +; system:inst_cpu|altera_merlin_slave_agent:pio_motor_rst_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1] ; Merged with system:inst_cpu|altera_merlin_slave_agent:pio_motor_rst_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; +; system:inst_cpu|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][70] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][102] ; +; system:inst_cpu|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][68] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62] ; +; system:inst_cpu|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][69] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62] ; +; system:inst_cpu|altera_merlin_slave_agent:jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1] ; Merged with system:inst_cpu|altera_merlin_slave_agent:jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; +; system:inst_cpu|altera_avalon_sc_fifo:pio_sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][70] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:pio_sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][102] ; +; system:inst_cpu|altera_avalon_sc_fifo:pio_sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][68] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:pio_sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62] ; +; system:inst_cpu|altera_avalon_sc_fifo:pio_sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][69] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:pio_sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62] ; +; system:inst_cpu|altera_merlin_slave_agent:pio_sw_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1] ; Merged with system:inst_cpu|altera_merlin_slave_agent:pio_sw_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; +; system:inst_cpu|altera_avalon_sc_fifo:pio_key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][70] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:pio_key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][102] ; +; system:inst_cpu|altera_avalon_sc_fifo:pio_key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][68] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:pio_key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62] ; +; system:inst_cpu|altera_avalon_sc_fifo:pio_key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][69] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:pio_key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62] ; +; system:inst_cpu|altera_merlin_slave_agent:pio_key_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1] ; Merged with system:inst_cpu|altera_merlin_slave_agent:pio_key_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; +; system:inst_cpu|altera_avalon_sc_fifo:pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][70] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][102] ; +; system:inst_cpu|altera_avalon_sc_fifo:pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][68] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62] ; +; system:inst_cpu|altera_avalon_sc_fifo:pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][69] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62] ; +; system:inst_cpu|altera_merlin_slave_agent:pio_led_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1] ; Merged with system:inst_cpu|altera_merlin_slave_agent:pio_led_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; +; system:inst_cpu|altera_avalon_sc_fifo:uart_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][70] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:uart_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][102] ; +; system:inst_cpu|altera_avalon_sc_fifo:uart_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][68] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:uart_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62] ; +; system:inst_cpu|altera_avalon_sc_fifo:uart_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][69] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:uart_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62] ; +; system:inst_cpu|altera_merlin_slave_agent:uart_0_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1] ; Merged with system:inst_cpu|altera_merlin_slave_agent:uart_0_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; +; system:inst_cpu|altera_avalon_sc_fifo:sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][70] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][102] ; +; system:inst_cpu|altera_avalon_sc_fifo:sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][68] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62] ; +; system:inst_cpu|altera_avalon_sc_fifo:sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][69] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62] ; +; system:inst_cpu|altera_merlin_slave_agent:sys_clk_timer_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1] ; Merged with system:inst_cpu|altera_merlin_slave_agent:sys_clk_timer_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; +; system:inst_cpu|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][70] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][102] ; +; system:inst_cpu|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][68] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62] ; +; system:inst_cpu|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][69] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62] ; +; system:inst_cpu|altera_merlin_slave_agent:sysid_control_slave_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1] ; Merged with system:inst_cpu|altera_merlin_slave_agent:sysid_control_slave_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][50] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][44] ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][52] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][44] ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][58] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][44] ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][66] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][44] ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][67] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][44] ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][68] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][44] ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][65] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][54] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][53] ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][50] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][44] ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][52] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][44] ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][58] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][44] ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][66] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][44] ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][67] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][44] ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][68] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][44] ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][65] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][55] ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][54] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][53] ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[2][50] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[2][44] ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[2][52] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[2][44] ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[2][58] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[2][44] ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[2][66] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[2][44] ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[2][67] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[2][44] ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[2][68] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[2][44] ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[2][65] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[2][55] ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[2][54] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[2][53] ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[3][50] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[3][44] ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[3][52] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[3][44] ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[3][58] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[3][44] ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[3][66] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[3][44] ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[3][67] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[3][44] ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[3][68] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[3][44] ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[3][65] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[3][55] ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[3][54] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[3][53] ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][50] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][44] ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][52] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][44] ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][58] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][44] ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][66] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][44] ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][67] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][44] ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][68] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][44] ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][65] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][55] ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][54] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][53] ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][50] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][44] ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][52] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][44] ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][58] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][44] ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][66] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][44] ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][67] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][44] ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][68] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][44] ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][65] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][55] ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][54] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][53] ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[6][50] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[6][44] ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[6][52] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[6][44] ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[6][58] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[6][44] ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[6][66] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[6][44] ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[6][67] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[6][44] ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[6][68] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[6][44] ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[6][65] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[6][55] ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[6][54] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[6][53] ; +; system:inst_cpu|altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][70] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][102] ; +; system:inst_cpu|altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][68] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62] ; +; system:inst_cpu|altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][69] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62] ; +; system:inst_cpu|altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][84] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62] ; +; system:inst_cpu|altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][85] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62] ; +; system:inst_cpu|altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][86] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62] ; +; system:inst_cpu|altera_merlin_slave_agent:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1] ; Merged with system:inst_cpu|altera_merlin_slave_agent:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; +; system:inst_cpu|altera_merlin_slave_translator:jtag_uart_0_avalon_jtag_slave_translator|waitrequest_reset_override ; Merged with system:inst_cpu|altera_merlin_slave_translator:cpu_jtag_debug_module_translator|waitrequest_reset_override ; +; system:inst_cpu|altera_merlin_slave_translator:pio_key_s1_translator|waitrequest_reset_override ; Merged with system:inst_cpu|altera_merlin_slave_translator:cpu_jtag_debug_module_translator|waitrequest_reset_override ; +; system:inst_cpu|altera_merlin_slave_translator:pio_led_s1_translator|waitrequest_reset_override ; Merged with system:inst_cpu|altera_merlin_slave_translator:cpu_jtag_debug_module_translator|waitrequest_reset_override ; +; system:inst_cpu|altera_merlin_slave_translator:pio_motor_rst_s1_translator|waitrequest_reset_override ; Merged with system:inst_cpu|altera_merlin_slave_translator:cpu_jtag_debug_module_translator|waitrequest_reset_override ; +; system:inst_cpu|altera_merlin_slave_translator:pio_sw_s1_translator|waitrequest_reset_override ; Merged with system:inst_cpu|altera_merlin_slave_translator:cpu_jtag_debug_module_translator|waitrequest_reset_override ; +; system:inst_cpu|altera_merlin_slave_translator:rs232_motor_avalon_rs232_slave_translator|waitrequest_reset_override ; Merged with system:inst_cpu|altera_merlin_slave_translator:cpu_jtag_debug_module_translator|waitrequest_reset_override ; +; system:inst_cpu|altera_merlin_slave_translator:sys_clk_timer_s1_translator|waitrequest_reset_override ; Merged with system:inst_cpu|altera_merlin_slave_translator:cpu_jtag_debug_module_translator|waitrequest_reset_override ; +; system:inst_cpu|altera_merlin_slave_translator:sysid_control_slave_translator|waitrequest_reset_override ; Merged with system:inst_cpu|altera_merlin_slave_translator:cpu_jtag_debug_module_translator|waitrequest_reset_override ; +; system:inst_cpu|altera_merlin_slave_translator:uart_0_s1_translator|waitrequest_reset_override ; Merged with system:inst_cpu|altera_merlin_slave_translator:cpu_jtag_debug_module_translator|waitrequest_reset_override ; +; system:inst_cpu|system_cpu:cpu|clr_break_line ; Merged with system:inst_cpu|altera_merlin_slave_translator:cpu_jtag_debug_module_translator|waitrequest_reset_override ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|rst1 ; Merged with system:inst_cpu|altera_merlin_slave_translator:cpu_jtag_debug_module_translator|waitrequest_reset_override ; +; system:inst_cpu|system_cpu:cpu|D_ctrl_jmp_direct ; Merged with system:inst_cpu|system_cpu:cpu|D_ctrl_a_not_src ; +; system:inst_cpu|system_cpu:cpu|D_ctrl_b_not_src ; Merged with system:inst_cpu|system_cpu:cpu|D_ctrl_b_is_dst ; +; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|p0_reg_cmpr_read ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy ; Stuck at GND due to stuck port clock_enable ; +; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0..2] ; Stuck at GND due to stuck port clock_enable ; +; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_address_base[1] ; Stuck at GND due to stuck port clock_enable ; +; system:inst_cpu|altera_merlin_width_adapter:width_adapter|address_reg[0] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_merlin_width_adapter:width_adapter|byteen_reg[3] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_avalon_sc_fifo:rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][69] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_avalon_sc_fifo:pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][69] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][69] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_avalon_sc_fifo:pio_sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][69] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_avalon_sc_fifo:pio_key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][69] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_avalon_sc_fifo:pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][69] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_avalon_sc_fifo:uart_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][69] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_avalon_sc_fifo:sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][69] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][69] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][68] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][86] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|system_rs232_motor:rs232_motor|readdata[10] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_break:the_system_cpu_nios2_oci_break|trigger_state ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|p0_reg_endofpacket ; Stuck at GND due to stuck port clock_enable ; +; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|p0_reg_data_field[0..15] ; Stuck at GND due to stuck port clock_enable ; +; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|p0_reg_bwrap_field[0,2] ; Stuck at GND due to stuck port clock_enable ; +; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|p0_reg_address_field[0..25] ; Stuck at GND due to stuck port clock_enable ; +; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|p0_reg_byte_cnt_field[0..2] ; Stuck at GND due to stuck port clock_enable ; +; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|p0_reg_channel[0,1] ; Stuck at GND due to stuck port clock_enable ; +; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_address_offset[0..25] ; Stuck at GND due to stuck port clock_enable ; +; system:inst_cpu|altera_avalon_sc_fifo:rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_merlin_slave_agent:rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_merlin_slave_agent:rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,2] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_avalon_sc_fifo:pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_merlin_slave_agent:pio_motor_rst_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_merlin_slave_agent:pio_motor_rst_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,2] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_merlin_slave_agent:jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_merlin_slave_agent:jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,2] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_avalon_sc_fifo:pio_sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_merlin_slave_agent:pio_sw_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_merlin_slave_agent:pio_sw_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,2] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_avalon_sc_fifo:pio_key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_merlin_slave_agent:pio_key_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_merlin_slave_agent:pio_key_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,2] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_avalon_sc_fifo:pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_merlin_slave_agent:pio_led_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_merlin_slave_agent:pio_led_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,2] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_avalon_sc_fifo:uart_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_merlin_slave_agent:uart_0_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_merlin_slave_agent:uart_0_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,2] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_avalon_sc_fifo:sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_merlin_slave_agent:sys_clk_timer_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_merlin_slave_agent:sys_clk_timer_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,2] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_merlin_slave_agent:sysid_control_slave_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_merlin_slave_agent:sysid_control_slave_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,2] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[6][44] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_merlin_slave_agent:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_merlin_slave_agent:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,2] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][44] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][44] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[3][44] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[2][44] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][44] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][44] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0..2] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|p0_use_reg ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][18] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[6][18] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][18] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][18] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[3][18] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[2][18] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][18] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][18] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_address_base[0] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_dbrk:the_system_cpu_nios2_oci_dbrk|dbrk_break ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][57] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_break:the_system_cpu_nios2_oci_break|trigbrktype ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[6][57] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][57] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][57] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[3][57] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[2][57] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][57] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][57] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][51] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][56] ; +; system:inst_cpu|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][101] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_avalon_sc_fifo:sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][101] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_avalon_sc_fifo:uart_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][101] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_avalon_sc_fifo:pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][101] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_avalon_sc_fifo:pio_key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][101] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_avalon_sc_fifo:pio_sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][101] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][101] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_avalon_sc_fifo:pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][101] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_avalon_sc_fifo:rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][101] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][101] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][101] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_avalon_sc_fifo:sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][101] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_avalon_sc_fifo:uart_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][101] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_avalon_sc_fifo:pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][101] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_avalon_sc_fifo:pio_key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][101] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_avalon_sc_fifo:pio_sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][101] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][101] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_avalon_sc_fifo:pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][101] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_avalon_sc_fifo:rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][101] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][101] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux_001|share_count_zero_flag ; Stuck at VCC due to stuck port data_in ; +; system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux|share_count_zero_flag ; Stuck at VCC due to stuck port data_in ; +; system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux_001|share_count[0] ; Lost fanout ; +; system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux|share_count[0] ; Lost fanout ; +; system:inst_cpu|system_sdram:sdram|m_next~9 ; Lost fanout ; +; system:inst_cpu|system_sdram:sdram|m_next~10 ; Lost fanout ; +; system:inst_cpu|system_sdram:sdram|m_next~13 ; Lost fanout ; +; system:inst_cpu|system_sdram:sdram|m_next~14 ; Lost fanout ; +; system:inst_cpu|system_sdram:sdram|m_next~16 ; Lost fanout ; +; system:inst_cpu|system_sdram:sdram|i_next~4 ; Lost fanout ; +; system:inst_cpu|system_sdram:sdram|i_next~5 ; Lost fanout ; +; system:inst_cpu|system_sdram:sdram|i_next~6 ; Lost fanout ; +; system:inst_cpu|system_sdram:sdram|i_state~14 ; Lost fanout ; +; system:inst_cpu|system_sdram:sdram|i_state~15 ; Lost fanout ; +; system:inst_cpu|system_sdram:sdram|i_state~16 ; Lost fanout ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|DRsize~3 ; Lost fanout ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|DRsize~4 ; Lost fanout ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|DRsize~5 ; Lost fanout ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|DRsize.101 ; Lost fanout ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|DRsize.011 ; Merged with system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|DRsize.001 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|DRsize.001 ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_address_offset[25] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][43] ; Lost fanout ; +; system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_address_offset[24] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][42] ; Lost fanout ; +; system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_address_offset[23] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][41] ; Lost fanout ; +; system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_address_offset[22] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][40] ; Lost fanout ; +; system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_address_offset[21] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][39] ; Lost fanout ; +; system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_address_offset[20] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][38] ; Lost fanout ; +; system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_address_offset[19] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][37] ; Lost fanout ; +; system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_address_offset[18] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][36] ; Lost fanout ; +; system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_address_offset[17] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][35] ; Lost fanout ; +; system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_address_offset[16] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][34] ; Lost fanout ; +; system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_address_offset[15] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][33] ; Lost fanout ; +; system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_address_offset[14] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][32] ; Lost fanout ; +; system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_address_offset[13] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][31] ; Lost fanout ; +; system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_address_offset[12] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][30] ; Lost fanout ; +; system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_address_offset[11] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][29] ; Lost fanout ; +; system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_address_offset[10] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][28] ; Lost fanout ; +; system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_address_offset[9] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][27] ; Lost fanout ; +; system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_address_offset[8] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][26] ; Lost fanout ; +; system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_address_offset[7] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][25] ; Lost fanout ; +; system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_address_offset[6] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][24] ; Lost fanout ; +; system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_address_offset[5] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][23] ; Lost fanout ; +; system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_address_offset[4] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][22] ; Lost fanout ; +; system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_address_offset[3] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][21] ; Lost fanout ; +; system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_address_offset[2] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][20] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][43] ; Lost fanout ; +; system:inst_cpu|altera_merlin_width_adapter:width_adapter|address_reg[25] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][42] ; Lost fanout ; +; system:inst_cpu|altera_merlin_width_adapter:width_adapter|address_reg[24] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][41] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][40] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][39] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][38] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][37] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][36] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][35] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][34] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][33] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][32] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][31] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][30] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][29] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][28] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][27] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][26] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][25] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][24] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][23] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][22] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][21] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][20] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[2][43] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[2][42] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[2][41] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[2][40] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[2][39] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[2][38] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[2][37] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[2][36] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[2][35] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[2][34] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[2][33] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[2][32] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[2][31] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[2][30] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[2][29] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[2][28] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[2][27] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[2][26] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[2][25] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[2][24] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[2][23] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[2][22] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[2][21] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[2][20] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[3][43] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[3][42] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[3][41] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[3][40] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[3][39] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[3][38] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[3][37] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[3][36] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[3][35] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[3][34] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[3][33] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[3][32] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[3][31] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[3][30] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[3][29] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[3][28] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[3][27] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[3][26] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[3][25] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[3][24] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[3][23] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[3][22] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[3][21] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[3][20] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][43] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][42] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][41] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][40] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][39] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][38] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][37] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][36] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][35] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][34] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][33] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][32] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][31] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][30] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][29] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][28] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][27] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][26] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][25] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][24] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][23] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][22] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][21] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][20] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][43] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][42] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][41] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][40] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][39] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][38] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][37] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][36] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][35] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][34] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][33] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][32] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][31] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][30] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][29] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][28] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][27] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][26] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][25] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][24] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][23] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][22] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][21] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][20] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[6][43] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[6][42] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[6][41] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[6][40] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[6][39] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[6][38] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[6][37] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[6][36] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[6][35] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[6][34] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[6][33] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[6][32] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[6][31] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[6][30] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[6][29] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[6][28] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[6][27] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[6][26] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[6][25] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[6][24] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[6][23] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[6][22] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[6][21] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[6][20] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][43] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][42] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][41] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][40] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][39] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][38] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][37] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][36] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][35] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][34] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][33] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][32] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][31] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][30] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][29] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][28] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][27] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][26] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][25] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][24] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][23] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][22] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][21] ; Lost fanout ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][20] ; Lost fanout ; +; heartbeat:inst_heartbeat|counter_data[22..31] ; Lost fanout ; +; Total Number of Removed Registers = 1070 ; ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Removed Registers Triggering Further Register Optimizations ; ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Register name ; Reason for Removal ; Registers Removed due to This Register ; ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|p0_reg_cmpr_read ; Stuck at GND ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2], ; +; ; due to stuck port data_in ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1], ; +; ; ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0], ; +; ; ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_address_base[1], ; +; ; ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|p0_reg_data_field[15], ; +; ; ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|p0_reg_data_field[14], ; +; ; ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|p0_reg_data_field[13], ; +; ; ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|p0_reg_data_field[12], ; +; ; ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|p0_reg_data_field[11], ; +; ; ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|p0_reg_data_field[10], ; +; ; ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|p0_reg_data_field[9], ; +; ; ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|p0_reg_data_field[8], ; +; ; ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|p0_reg_data_field[7], ; +; ; ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|p0_reg_data_field[6], ; +; ; ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|p0_reg_data_field[5], ; +; ; ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|p0_reg_data_field[4], ; +; ; ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|p0_reg_data_field[3], ; +; ; ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|p0_reg_data_field[2], ; +; ; ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|p0_reg_data_field[1], ; +; ; ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|p0_reg_data_field[0], ; +; ; ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|p0_reg_byte_cnt_field[2], ; +; ; ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|p0_reg_byte_cnt_field[1], ; +; ; ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|p0_reg_byte_cnt_field[0], ; +; ; ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|p0_reg_channel[0], ; +; ; ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_address_offset[0], ; +; ; ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_address_offset[25], ; +; ; ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_address_offset[24], ; +; ; ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_address_offset[23], ; +; ; ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_address_offset[22], ; +; ; ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_address_offset[21], ; +; ; ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_address_offset[20], ; +; ; ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_address_offset[19], ; +; ; ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_address_offset[18], ; +; ; ; system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_busy, ; +; ; ; system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2], ; +; ; ; system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1], ; +; ; ; system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0], ; +; ; ; system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_address_base[0], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][43], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][42], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][41], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][40], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][39], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][38], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][37], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][36], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][35], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][34], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][33], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][32], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][31], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][30], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][29], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][28], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][27], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][26], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][25], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][24], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][23], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][22], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][21], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][20], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][43], ; +; ; ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|address_reg[25], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][42], ; +; ; ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|address_reg[24], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][41], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][40], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][39], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][38], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][37], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][36], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][35], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][34], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][33], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][32], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][31], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][30], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][29], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][28], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][27], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][26], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][25], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][24], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][23], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][22], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][21], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][20], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[2][43], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[2][42], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[2][41], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[2][40], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[2][39], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[2][38], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[2][37], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[2][36], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[2][35], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[2][34], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[2][33], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[2][32], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[2][31], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[2][30], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[2][29], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[2][28], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[2][27], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[2][26], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[2][25], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[2][24], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[2][23], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[2][22], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[2][21], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[2][20], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[3][43], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[3][42], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[3][41], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[3][40], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[3][39], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[3][38], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[3][37], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[3][36], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[3][35], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[3][34], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[3][33], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[3][32], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[3][31], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[3][30], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[3][29], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[3][28], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[3][27], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[3][26], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[3][25], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[3][24], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[3][23], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[3][22], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[3][21], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[3][20], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][43], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][42], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][41], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][40], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][39], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][38], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][37], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][36], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][35], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][34], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][33], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][32], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][31], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][30], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][29], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][28], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][27], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][26], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][25], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][24], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][23], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][22], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][21], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][20], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][43], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][42], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][41], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][40], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][39], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][38], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][37], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][36], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][35], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][34], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][33], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][32], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][31], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][30], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][29], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][28], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][27], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][26], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][25], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][24], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][23], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][22], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][21], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][20], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[6][43], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[6][42], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[6][41], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[6][40], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[6][39], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[6][38], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[6][37], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[6][36], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[6][35], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[6][34], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[6][33], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[6][32], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[6][31], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[6][30], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[6][29], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[6][28], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[6][27], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[6][26], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[6][25], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[6][24], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[6][23], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[6][22], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[6][21], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[6][20], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][43], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][42], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][41], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][40], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][39], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][38], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][37], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][36], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][35], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][34], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][33], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][32], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][31], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][30], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][29], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][28], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][27], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][26], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][25], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][24], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][23], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][22], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][21], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][20] ; +; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|p0_use_reg ; Stuck at GND ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[6][18], ; +; ; due to stuck port data_in ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][18], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][18], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[3][18], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[2][18], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][18], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[6][57], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][57], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][57], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[3][57], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[2][57], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][57], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][57] ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][68] ; Stuck at GND ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[6][44], ; +; ; due to stuck port data_in ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][44], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][44], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[3][44], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[2][44], ; +; ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][44] ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_dbrk:the_system_cpu_nios2_oci_dbrk|dbrk_break_pulse ; Stuck at GND ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_dbrk:the_system_cpu_nios2_oci_dbrk|dbrk_break, ; +; ; due to stuck port data_in ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_break:the_system_cpu_nios2_oci_break|trigbrktype ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_xbrk:the_system_cpu_nios2_oci_xbrk|xbrk_break ; Stuck at GND ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_xbrk:the_system_cpu_nios2_oci_xbrk|M_xbrk_goto0, ; +; ; due to stuck port data_in ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_xbrk:the_system_cpu_nios2_oci_xbrk|M_xbrk_goto1 ; +; system:inst_cpu|altera_merlin_width_adapter:width_adapter|address_reg[0] ; Stuck at GND ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][18], ; +; ; due to stuck port data_in ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][18] ; +; system:inst_cpu|altera_avalon_sc_fifo:rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][69] ; Stuck at GND ; system:inst_cpu|altera_avalon_sc_fifo:rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62], ; +; ; due to stuck port data_in ; system:inst_cpu|altera_merlin_slave_agent:rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; +; system:inst_cpu|altera_avalon_sc_fifo:pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][69] ; Stuck at GND ; system:inst_cpu|altera_avalon_sc_fifo:pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62], ; +; ; due to stuck port data_in ; system:inst_cpu|altera_merlin_slave_agent:pio_motor_rst_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; +; system:inst_cpu|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][69] ; Stuck at GND ; system:inst_cpu|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62], ; +; ; due to stuck port data_in ; system:inst_cpu|altera_merlin_slave_agent:jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; +; system:inst_cpu|altera_avalon_sc_fifo:pio_sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][69] ; Stuck at GND ; system:inst_cpu|altera_avalon_sc_fifo:pio_sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62], ; +; ; due to stuck port data_in ; system:inst_cpu|altera_merlin_slave_agent:pio_sw_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; +; system:inst_cpu|altera_avalon_sc_fifo:pio_key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][69] ; Stuck at GND ; system:inst_cpu|altera_avalon_sc_fifo:pio_key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62], ; +; ; due to stuck port data_in ; system:inst_cpu|altera_merlin_slave_agent:pio_key_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; +; system:inst_cpu|altera_avalon_sc_fifo:pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][69] ; Stuck at GND ; system:inst_cpu|altera_avalon_sc_fifo:pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62], ; +; ; due to stuck port data_in ; system:inst_cpu|altera_merlin_slave_agent:pio_led_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; +; system:inst_cpu|altera_avalon_sc_fifo:uart_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][69] ; Stuck at GND ; system:inst_cpu|altera_avalon_sc_fifo:uart_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62], ; +; ; due to stuck port data_in ; system:inst_cpu|altera_merlin_slave_agent:uart_0_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; +; system:inst_cpu|altera_avalon_sc_fifo:sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][69] ; Stuck at GND ; system:inst_cpu|altera_avalon_sc_fifo:sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62], ; +; ; due to stuck port data_in ; system:inst_cpu|altera_merlin_slave_agent:sys_clk_timer_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; +; system:inst_cpu|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][69] ; Stuck at GND ; system:inst_cpu|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62], ; +; ; due to stuck port data_in ; system:inst_cpu|altera_merlin_slave_agent:sysid_control_slave_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; +; system:inst_cpu|altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][86] ; Stuck at GND ; system:inst_cpu|altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][62], ; +; ; due to stuck port data_in ; system:inst_cpu|altera_merlin_slave_agent:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; +; system:inst_cpu|system_pio_sw:pio_sw|readdata[16] ; Stuck at GND ; system:inst_cpu|altera_merlin_slave_translator:pio_sw_s1_translator|av_readdata_pre[16] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|system_pio_sw:pio_sw|readdata[15] ; Stuck at GND ; system:inst_cpu|altera_merlin_slave_translator:pio_sw_s1_translator|av_readdata_pre[15] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|system_pio_sw:pio_sw|readdata[14] ; Stuck at GND ; system:inst_cpu|altera_merlin_slave_translator:pio_sw_s1_translator|av_readdata_pre[14] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|system_pio_sw:pio_sw|readdata[13] ; Stuck at GND ; system:inst_cpu|altera_merlin_slave_translator:pio_sw_s1_translator|av_readdata_pre[13] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|system_pio_sw:pio_sw|readdata[12] ; Stuck at GND ; system:inst_cpu|altera_merlin_slave_translator:pio_sw_s1_translator|av_readdata_pre[12] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|system_pio_sw:pio_sw|readdata[11] ; Stuck at GND ; system:inst_cpu|altera_merlin_slave_translator:pio_sw_s1_translator|av_readdata_pre[11] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|system_pio_sw:pio_sw|readdata[10] ; Stuck at GND ; system:inst_cpu|altera_merlin_slave_translator:pio_sw_s1_translator|av_readdata_pre[10] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|system_pio_sw:pio_sw|readdata[9] ; Stuck at GND ; system:inst_cpu|altera_merlin_slave_translator:pio_sw_s1_translator|av_readdata_pre[9] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|system_pio_sw:pio_sw|readdata[8] ; Stuck at GND ; system:inst_cpu|altera_merlin_slave_translator:pio_sw_s1_translator|av_readdata_pre[8] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|system_pio_sw:pio_sw|readdata[7] ; Stuck at GND ; system:inst_cpu|altera_merlin_slave_translator:pio_sw_s1_translator|av_readdata_pre[7] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|system_pio_sw:pio_sw|readdata[6] ; Stuck at GND ; system:inst_cpu|altera_merlin_slave_translator:pio_sw_s1_translator|av_readdata_pre[6] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|system_pio_sw:pio_sw|readdata[5] ; Stuck at GND ; system:inst_cpu|altera_merlin_slave_translator:pio_sw_s1_translator|av_readdata_pre[5] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|system_pio_sw:pio_sw|readdata[4] ; Stuck at GND ; system:inst_cpu|altera_merlin_slave_translator:pio_sw_s1_translator|av_readdata_pre[4] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|system_pio_key:pio_key|readdata[31] ; Stuck at GND ; system:inst_cpu|altera_merlin_slave_translator:pio_key_s1_translator|av_readdata_pre[31] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|system_pio_key:pio_key|readdata[30] ; Stuck at GND ; system:inst_cpu|altera_merlin_slave_translator:pio_key_s1_translator|av_readdata_pre[30] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|system_pio_key:pio_key|readdata[29] ; Stuck at GND ; system:inst_cpu|altera_merlin_slave_translator:pio_key_s1_translator|av_readdata_pre[29] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|system_pio_key:pio_key|readdata[28] ; Stuck at GND ; system:inst_cpu|altera_merlin_slave_translator:pio_key_s1_translator|av_readdata_pre[28] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|system_pio_key:pio_key|readdata[27] ; Stuck at GND ; system:inst_cpu|altera_merlin_slave_translator:pio_key_s1_translator|av_readdata_pre[27] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|system_pio_key:pio_key|readdata[26] ; Stuck at GND ; system:inst_cpu|altera_merlin_slave_translator:pio_key_s1_translator|av_readdata_pre[26] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|system_pio_key:pio_key|readdata[25] ; Stuck at GND ; system:inst_cpu|altera_merlin_slave_translator:pio_key_s1_translator|av_readdata_pre[25] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|system_pio_key:pio_key|readdata[24] ; Stuck at GND ; system:inst_cpu|altera_merlin_slave_translator:pio_key_s1_translator|av_readdata_pre[24] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|system_pio_key:pio_key|readdata[23] ; Stuck at GND ; system:inst_cpu|altera_merlin_slave_translator:pio_key_s1_translator|av_readdata_pre[23] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|system_pio_key:pio_key|readdata[22] ; Stuck at GND ; system:inst_cpu|altera_merlin_slave_translator:pio_key_s1_translator|av_readdata_pre[22] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|system_pio_key:pio_key|readdata[21] ; Stuck at GND ; system:inst_cpu|altera_merlin_slave_translator:pio_key_s1_translator|av_readdata_pre[21] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|system_pio_key:pio_key|readdata[20] ; Stuck at GND ; system:inst_cpu|altera_merlin_slave_translator:pio_key_s1_translator|av_readdata_pre[20] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|system_pio_key:pio_key|readdata[19] ; Stuck at GND ; system:inst_cpu|altera_merlin_slave_translator:pio_key_s1_translator|av_readdata_pre[19] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|system_pio_key:pio_key|readdata[18] ; Stuck at GND ; system:inst_cpu|altera_merlin_slave_translator:pio_key_s1_translator|av_readdata_pre[18] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|system_pio_key:pio_key|readdata[17] ; Stuck at GND ; system:inst_cpu|altera_merlin_slave_translator:pio_key_s1_translator|av_readdata_pre[17] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|system_pio_key:pio_key|readdata[16] ; Stuck at GND ; system:inst_cpu|altera_merlin_slave_translator:pio_key_s1_translator|av_readdata_pre[16] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|system_pio_key:pio_key|readdata[15] ; Stuck at GND ; system:inst_cpu|altera_merlin_slave_translator:pio_key_s1_translator|av_readdata_pre[15] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|system_pio_key:pio_key|readdata[14] ; Stuck at GND ; system:inst_cpu|altera_merlin_slave_translator:pio_key_s1_translator|av_readdata_pre[14] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|system_pio_key:pio_key|readdata[13] ; Stuck at GND ; system:inst_cpu|altera_merlin_slave_translator:pio_key_s1_translator|av_readdata_pre[13] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|system_pio_key:pio_key|readdata[12] ; Stuck at GND ; system:inst_cpu|altera_merlin_slave_translator:pio_key_s1_translator|av_readdata_pre[12] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|system_pio_key:pio_key|readdata[11] ; Stuck at GND ; system:inst_cpu|altera_merlin_slave_translator:pio_key_s1_translator|av_readdata_pre[11] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|system_pio_key:pio_key|readdata[10] ; Stuck at GND ; system:inst_cpu|altera_merlin_slave_translator:pio_key_s1_translator|av_readdata_pre[10] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|system_pio_key:pio_key|readdata[9] ; Stuck at GND ; system:inst_cpu|altera_merlin_slave_translator:pio_key_s1_translator|av_readdata_pre[9] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|system_pio_key:pio_key|readdata[8] ; Stuck at GND ; system:inst_cpu|altera_merlin_slave_translator:pio_key_s1_translator|av_readdata_pre[8] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|system_pio_key:pio_key|readdata[7] ; Stuck at GND ; system:inst_cpu|altera_merlin_slave_translator:pio_key_s1_translator|av_readdata_pre[7] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|system_pio_key:pio_key|readdata[6] ; Stuck at GND ; system:inst_cpu|altera_merlin_slave_translator:pio_key_s1_translator|av_readdata_pre[6] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|system_pio_key:pio_key|readdata[5] ; Stuck at GND ; system:inst_cpu|altera_merlin_slave_translator:pio_key_s1_translator|av_readdata_pre[5] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|system_pio_key:pio_key|readdata[4] ; Stuck at GND ; system:inst_cpu|altera_merlin_slave_translator:pio_key_s1_translator|av_readdata_pre[4] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|system_pio_key:pio_key|readdata[3] ; Stuck at GND ; system:inst_cpu|altera_merlin_slave_translator:pio_key_s1_translator|av_readdata_pre[3] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|system_pio_key:pio_key|readdata[2] ; Stuck at GND ; system:inst_cpu|altera_merlin_slave_translator:pio_key_s1_translator|av_readdata_pre[2] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|system_cpu:cpu|E_control_reg_rddata[31] ; Stuck at GND ; system:inst_cpu|system_cpu:cpu|M_control_reg_rddata[31] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|system_cpu:cpu|E_control_reg_rddata[30] ; Stuck at GND ; system:inst_cpu|system_cpu:cpu|M_control_reg_rddata[30] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|system_cpu:cpu|E_control_reg_rddata[29] ; Stuck at GND ; system:inst_cpu|system_cpu:cpu|M_control_reg_rddata[29] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|system_cpu:cpu|E_control_reg_rddata[28] ; Stuck at GND ; system:inst_cpu|system_cpu:cpu|M_control_reg_rddata[28] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|system_cpu:cpu|E_control_reg_rddata[27] ; Stuck at GND ; system:inst_cpu|system_cpu:cpu|M_control_reg_rddata[27] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|system_cpu:cpu|E_control_reg_rddata[26] ; Stuck at GND ; system:inst_cpu|system_cpu:cpu|M_control_reg_rddata[26] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|system_cpu:cpu|E_control_reg_rddata[25] ; Stuck at GND ; system:inst_cpu|system_cpu:cpu|M_control_reg_rddata[25] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|system_cpu:cpu|E_control_reg_rddata[24] ; Stuck at GND ; system:inst_cpu|system_cpu:cpu|M_control_reg_rddata[24] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|system_cpu:cpu|E_control_reg_rddata[23] ; Stuck at GND ; system:inst_cpu|system_cpu:cpu|M_control_reg_rddata[23] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|system_cpu:cpu|E_control_reg_rddata[22] ; Stuck at GND ; system:inst_cpu|system_cpu:cpu|M_control_reg_rddata[22] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|system_cpu:cpu|E_control_reg_rddata[21] ; Stuck at GND ; system:inst_cpu|system_cpu:cpu|M_control_reg_rddata[21] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|system_cpu:cpu|E_control_reg_rddata[20] ; Stuck at GND ; system:inst_cpu|system_cpu:cpu|M_control_reg_rddata[20] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|system_cpu:cpu|E_control_reg_rddata[19] ; Stuck at GND ; system:inst_cpu|system_cpu:cpu|M_control_reg_rddata[19] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|system_cpu:cpu|E_control_reg_rddata[18] ; Stuck at GND ; system:inst_cpu|system_cpu:cpu|M_control_reg_rddata[18] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|system_cpu:cpu|E_control_reg_rddata[17] ; Stuck at GND ; system:inst_cpu|system_cpu:cpu|M_control_reg_rddata[17] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|system_cpu:cpu|E_control_reg_rddata[16] ; Stuck at GND ; system:inst_cpu|system_cpu:cpu|M_control_reg_rddata[16] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|system_cpu:cpu|E_control_reg_rddata[15] ; Stuck at GND ; system:inst_cpu|system_cpu:cpu|M_control_reg_rddata[15] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|system_cpu:cpu|E_control_reg_rddata[13] ; Stuck at GND ; system:inst_cpu|system_cpu:cpu|M_control_reg_rddata[13] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|system_cpu:cpu|E_control_reg_rddata[12] ; Stuck at GND ; system:inst_cpu|system_cpu:cpu|M_control_reg_rddata[12] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|system_cpu:cpu|E_control_reg_rddata[11] ; Stuck at GND ; system:inst_cpu|system_cpu:cpu|M_control_reg_rddata[11] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|system_cpu:cpu|E_control_reg_rddata[10] ; Stuck at GND ; system:inst_cpu|system_cpu:cpu|M_control_reg_rddata[10] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|system_cpu:cpu|E_control_reg_rddata[9] ; Stuck at GND ; system:inst_cpu|system_cpu:cpu|M_control_reg_rddata[9] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|system_cpu:cpu|E_control_reg_rddata[8] ; Stuck at GND ; system:inst_cpu|system_cpu:cpu|M_control_reg_rddata[8] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|system_cpu:cpu|E_control_reg_rddata[7] ; Stuck at GND ; system:inst_cpu|system_cpu:cpu|M_control_reg_rddata[7] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|system_cpu:cpu|E_control_reg_rddata[6] ; Stuck at GND ; system:inst_cpu|system_cpu:cpu|M_control_reg_rddata[6] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|system_cpu:cpu|E_control_reg_rddata[3] ; Stuck at GND ; system:inst_cpu|system_cpu:cpu|M_control_reg_rddata[3] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|system_cpu:cpu|E_control_reg_rddata[2] ; Stuck at GND ; system:inst_cpu|system_cpu:cpu|M_control_reg_rddata[2] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|system_cpu:cpu|E_ctrl_br_always_pred_taken ; Stuck at GND ; system:inst_cpu|system_cpu:cpu|M_ctrl_br_always_pred_taken ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_dbrk:the_system_cpu_nios2_oci_dbrk|dbrk_goto1 ; Stuck at GND ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_break:the_system_cpu_nios2_oci_break|trigger_state ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|altera_merlin_slave_translator:rs232_motor_avalon_rs232_slave_translator|av_chipselect_pre ; Stuck at GND ; system:inst_cpu|system_rs232_motor:rs232_motor|readdata[10] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|system_pio_sw:pio_sw|readdata[31] ; Stuck at GND ; system:inst_cpu|altera_merlin_slave_translator:pio_sw_s1_translator|av_readdata_pre[31] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|system_pio_sw:pio_sw|readdata[30] ; Stuck at GND ; system:inst_cpu|altera_merlin_slave_translator:pio_sw_s1_translator|av_readdata_pre[30] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|system_pio_sw:pio_sw|readdata[29] ; Stuck at GND ; system:inst_cpu|altera_merlin_slave_translator:pio_sw_s1_translator|av_readdata_pre[29] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|system_pio_sw:pio_sw|readdata[28] ; Stuck at GND ; system:inst_cpu|altera_merlin_slave_translator:pio_sw_s1_translator|av_readdata_pre[28] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|system_pio_sw:pio_sw|readdata[27] ; Stuck at GND ; system:inst_cpu|altera_merlin_slave_translator:pio_sw_s1_translator|av_readdata_pre[27] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|system_pio_sw:pio_sw|readdata[26] ; Stuck at GND ; system:inst_cpu|altera_merlin_slave_translator:pio_sw_s1_translator|av_readdata_pre[26] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|system_pio_sw:pio_sw|readdata[25] ; Stuck at GND ; system:inst_cpu|altera_merlin_slave_translator:pio_sw_s1_translator|av_readdata_pre[25] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|system_pio_sw:pio_sw|readdata[24] ; Stuck at GND ; system:inst_cpu|altera_merlin_slave_translator:pio_sw_s1_translator|av_readdata_pre[24] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|system_pio_sw:pio_sw|readdata[23] ; Stuck at GND ; system:inst_cpu|altera_merlin_slave_translator:pio_sw_s1_translator|av_readdata_pre[23] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|system_pio_sw:pio_sw|readdata[22] ; Stuck at GND ; system:inst_cpu|altera_merlin_slave_translator:pio_sw_s1_translator|av_readdata_pre[22] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|system_pio_sw:pio_sw|readdata[21] ; Stuck at GND ; system:inst_cpu|altera_merlin_slave_translator:pio_sw_s1_translator|av_readdata_pre[21] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|system_pio_sw:pio_sw|readdata[20] ; Stuck at GND ; system:inst_cpu|altera_merlin_slave_translator:pio_sw_s1_translator|av_readdata_pre[20] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|system_pio_sw:pio_sw|readdata[19] ; Stuck at GND ; system:inst_cpu|altera_merlin_slave_translator:pio_sw_s1_translator|av_readdata_pre[19] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|system_pio_sw:pio_sw|readdata[18] ; Stuck at GND ; system:inst_cpu|altera_merlin_slave_translator:pio_sw_s1_translator|av_readdata_pre[18] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|p0_reg_bwrap_field[0] ; Stuck at GND ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_address_offset[1] ; +; ; due to stuck port clock_enable ; ; +; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|p0_reg_address_field[25] ; Stuck at GND ; system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_address_offset[25] ; +; ; due to stuck port clock_enable ; ; +; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|p0_reg_address_field[24] ; Stuck at GND ; system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_address_offset[24] ; +; ; due to stuck port clock_enable ; ; +; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|p0_reg_address_field[23] ; Stuck at GND ; system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_address_offset[23] ; +; ; due to stuck port clock_enable ; ; +; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|p0_reg_address_field[22] ; Stuck at GND ; system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_address_offset[22] ; +; ; due to stuck port clock_enable ; ; +; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|p0_reg_address_field[21] ; Stuck at GND ; system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_address_offset[21] ; +; ; due to stuck port clock_enable ; ; +; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|p0_reg_address_field[20] ; Stuck at GND ; system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_address_offset[20] ; +; ; due to stuck port clock_enable ; ; +; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|p0_reg_address_field[19] ; Stuck at GND ; system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_address_offset[19] ; +; ; due to stuck port clock_enable ; ; +; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|p0_reg_address_field[18] ; Stuck at GND ; system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_address_offset[18] ; +; ; due to stuck port clock_enable ; ; +; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|p0_reg_address_field[17] ; Stuck at GND ; system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_address_offset[17] ; +; ; due to stuck port clock_enable ; ; +; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|p0_reg_address_field[16] ; Stuck at GND ; system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_address_offset[16] ; +; ; due to stuck port clock_enable ; ; +; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|p0_reg_address_field[15] ; Stuck at GND ; system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_address_offset[15] ; +; ; due to stuck port clock_enable ; ; +; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|p0_reg_address_field[14] ; Stuck at GND ; system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_address_offset[14] ; +; ; due to stuck port clock_enable ; ; +; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|p0_reg_address_field[13] ; Stuck at GND ; system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_address_offset[13] ; +; ; due to stuck port clock_enable ; ; +; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|p0_reg_address_field[12] ; Stuck at GND ; system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_address_offset[12] ; +; ; due to stuck port clock_enable ; ; +; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|p0_reg_address_field[11] ; Stuck at GND ; system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_address_offset[11] ; +; ; due to stuck port clock_enable ; ; +; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|p0_reg_address_field[10] ; Stuck at GND ; system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_address_offset[10] ; +; ; due to stuck port clock_enable ; ; +; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|p0_reg_address_field[9] ; Stuck at GND ; system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_address_offset[9] ; +; ; due to stuck port clock_enable ; ; +; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|p0_reg_address_field[8] ; Stuck at GND ; system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_address_offset[8] ; +; ; due to stuck port clock_enable ; ; +; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|p0_reg_address_field[7] ; Stuck at GND ; system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_address_offset[7] ; +; ; due to stuck port clock_enable ; ; +; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|p0_reg_address_field[6] ; Stuck at GND ; system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_address_offset[6] ; +; ; due to stuck port clock_enable ; ; +; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|p0_reg_address_field[5] ; Stuck at GND ; system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_address_offset[5] ; +; ; due to stuck port clock_enable ; ; +; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|p0_reg_address_field[4] ; Stuck at GND ; system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_address_offset[4] ; +; ; due to stuck port clock_enable ; ; +; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|p0_reg_address_field[3] ; Stuck at GND ; system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_address_offset[3] ; +; ; due to stuck port clock_enable ; ; +; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|p0_reg_address_field[2] ; Stuck at GND ; system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_address_offset[2] ; +; ; due to stuck port clock_enable ; ; +; system:inst_cpu|system_pio_sw:pio_sw|readdata[17] ; Stuck at GND ; system:inst_cpu|altera_merlin_slave_translator:pio_sw_s1_translator|av_readdata_pre[17] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][101] ; Stuck at GND ; system:inst_cpu|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][101] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|altera_avalon_sc_fifo:sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][101] ; Stuck at GND ; system:inst_cpu|altera_avalon_sc_fifo:sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][101] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|altera_avalon_sc_fifo:uart_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][101] ; Stuck at GND ; system:inst_cpu|altera_avalon_sc_fifo:uart_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][101] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|altera_avalon_sc_fifo:pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][101] ; Stuck at GND ; system:inst_cpu|altera_avalon_sc_fifo:pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][101] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|altera_avalon_sc_fifo:pio_key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][101] ; Stuck at GND ; system:inst_cpu|altera_avalon_sc_fifo:pio_key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][101] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|altera_avalon_sc_fifo:pio_sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][101] ; Stuck at GND ; system:inst_cpu|altera_avalon_sc_fifo:pio_sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][101] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][101] ; Stuck at GND ; system:inst_cpu|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][101] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|altera_avalon_sc_fifo:pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][101] ; Stuck at GND ; system:inst_cpu|altera_avalon_sc_fifo:pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][101] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|altera_avalon_sc_fifo:rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][101] ; Stuck at GND ; system:inst_cpu|altera_avalon_sc_fifo:rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][101] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][101] ; Stuck at GND ; system:inst_cpu|altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][101] ; +; ; due to stuck port data_in ; ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|DRsize~3 ; Lost Fanouts ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|DRsize.101 ; ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++------------------------------------------------------+ +; General Register Statistics ; ++----------------------------------------------+-------+ +; Statistic ; Value ; ++----------------------------------------------+-------+ +; Total registers ; 2867 ; +; Number of registers using Synchronous Clear ; 134 ; +; Number of registers using Synchronous Load ; 415 ; +; Number of registers using Asynchronous Clear ; 2307 ; +; Number of registers using Asynchronous Load ; 0 ; +; Number of registers using Clock Enable ; 1856 ; +; Number of registers using Preset ; 0 ; ++----------------------------------------------+-------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Inverted Register Statistics ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------+---------+ +; Inverted Register ; Fan out ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------+---------+ +; system:inst_cpu|system_sys_clk_timer:sys_clk_timer|internal_counter[0] ; 3 ; +; system:inst_cpu|system_sys_clk_timer:sys_clk_timer|internal_counter[1] ; 3 ; +; system:inst_cpu|system_sys_clk_timer:sys_clk_timer|internal_counter[2] ; 3 ; +; system:inst_cpu|system_sys_clk_timer:sys_clk_timer|internal_counter[3] ; 3 ; +; system:inst_cpu|system_sys_clk_timer:sys_clk_timer|internal_counter[4] ; 3 ; +; system:inst_cpu|system_sys_clk_timer:sys_clk_timer|internal_counter[7] ; 3 ; +; system:inst_cpu|system_sys_clk_timer:sys_clk_timer|internal_counter[9] ; 3 ; +; system:inst_cpu|system_sys_clk_timer:sys_clk_timer|internal_counter[10] ; 3 ; +; system:inst_cpu|system_sys_clk_timer:sys_clk_timer|internal_counter[15] ; 3 ; +; system:inst_cpu|system_sys_clk_timer:sys_clk_timer|internal_counter[16] ; 3 ; +; system:inst_cpu|system_sdram:sdram|m_cmd[3] ; 1 ; +; system:inst_cpu|system_sdram:sdram|m_cmd[2] ; 2 ; +; system:inst_cpu|system_sdram:sdram|m_cmd[1] ; 2 ; +; system:inst_cpu|system_sdram:sdram|m_cmd[0] ; 2 ; +; system:inst_cpu|system_sdram:sdram|i_cmd[3] ; 2 ; +; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; 2382 ; +; system:inst_cpu|system_sdram:sdram|i_cmd[2] ; 2 ; +; system:inst_cpu|system_sdram:sdram|i_cmd[1] ; 2 ; +; system:inst_cpu|system_sdram:sdram|i_cmd[0] ; 2 ; +; system:inst_cpu|system_sdram:sdram|i_addr[12] ; 11 ; +; system:inst_cpu|system_sdram:sdram|refresh_counter[14] ; 2 ; +; system:inst_cpu|system_sdram:sdram|refresh_counter[11] ; 2 ; +; system:inst_cpu|system_sdram:sdram|refresh_counter[10] ; 2 ; +; system:inst_cpu|system_sdram:sdram|refresh_counter[9] ; 2 ; +; system:inst_cpu|system_sdram:sdram|refresh_counter[5] ; 2 ; +; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[0] ; 1 ; +; system:inst_cpu|altera_merlin_slave_translator:cpu_jtag_debug_module_translator|waitrequest_reset_override ; 25 ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|av_waitrequest ; 8 ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|count[9] ; 11 ; +; system:inst_cpu|system_uart_0:uart_0|system_uart_0_tx:the_system_uart_0_tx|txd ; 1 ; +; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1] ; 1 ; +; system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux_001|altera_merlin_arbitrator:arb|top_priority_reg[0] ; 2 ; +; system:inst_cpu|system_cpu:cpu|M_pipe_flush ; 51 ; +; system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux|altera_merlin_arbitrator:arb|top_priority_reg[0] ; 2 ; +; system:inst_cpu|system_cpu:cpu|hbreak_enabled ; 10 ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|t_dav ; 3 ; +; system:inst_cpu|system_uart_0:uart_0|system_uart_0_tx:the_system_uart_0_tx|pre_txd ; 2 ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|rst2 ; 3 ; +; system:inst_cpu|system_cpu:cpu|ic_tag_clr_valid_bits ; 1 ; +; system:inst_cpu|system_cpu:cpu|M_pipe_flush_waddr[22] ; 1 ; +; system:inst_cpu|system_cpu:cpu|A_wr_dst_reg_from_M ; 66 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg|oci_ienable[1] ; 2 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg|oci_ienable[4] ; 2 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg|oci_ienable[5] ; 2 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg|oci_ienable[14] ; 2 ; +; system:inst_cpu|system_uart_0:uart_0|system_uart_0_tx:the_system_uart_0_tx|tx_ready ; 6 ; +; system:inst_cpu|system_uart_0:uart_0|system_uart_0_tx:the_system_uart_0_tx|tx_shift_empty ; 2 ; +; system:inst_cpu|system_uart_0:uart_0|system_uart_0_regs:the_system_uart_0_regs|baud_divisor[2] ; 3 ; +; system:inst_cpu|system_uart_0:uart_0|system_uart_0_regs:the_system_uart_0_regs|baud_divisor[5] ; 3 ; +; system:inst_cpu|system_uart_0:uart_0|system_uart_0_regs:the_system_uart_0_regs|baud_divisor[6] ; 3 ; +; system:inst_cpu|system_uart_0:uart_0|system_uart_0_regs:the_system_uart_0_regs|baud_divisor[8] ; 3 ; +; system:inst_cpu|system_uart_0:uart_0|system_uart_0_regs:the_system_uart_0_regs|baud_divisor[9] ; 3 ; +; system:inst_cpu|system_sys_clk_timer:sys_clk_timer|period_l_register[0] ; 2 ; +; system:inst_cpu|system_sys_clk_timer:sys_clk_timer|period_l_register[1] ; 2 ; +; system:inst_cpu|system_sys_clk_timer:sys_clk_timer|period_l_register[2] ; 2 ; +; system:inst_cpu|system_sys_clk_timer:sys_clk_timer|period_l_register[3] ; 2 ; +; system:inst_cpu|system_sys_clk_timer:sys_clk_timer|period_l_register[4] ; 2 ; +; system:inst_cpu|system_sys_clk_timer:sys_clk_timer|period_l_register[7] ; 2 ; +; system:inst_cpu|system_sys_clk_timer:sys_clk_timer|period_l_register[9] ; 2 ; +; system:inst_cpu|system_sys_clk_timer:sys_clk_timer|period_l_register[10] ; 2 ; +; system:inst_cpu|system_sys_clk_timer:sys_clk_timer|period_l_register[15] ; 2 ; +; system:inst_cpu|system_sys_clk_timer:sys_clk_timer|period_h_register[0] ; 2 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; 1 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2] ; 2 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1] ; 3 ; +; Total number of inverted registers = 65 ; ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------+---------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Multiplexer Restructuring Statistics (Restructuring Performed) ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_translator:pio_led_s1_translator|wait_latency_counter[1] ; +; 3:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|d_byteenable[0] ; +; 3:1 ; 18 bits ; 36 LEs ; 18 LEs ; 18 LEs ; Yes ; |de0_nano_system|system:inst_cpu|altera_merlin_width_adapter:width_adapter|byteen_reg[0] ; +; 3:1 ; 24 bits ; 48 LEs ; 0 LEs ; 48 LEs ; Yes ; |de0_nano_system|system:inst_cpu|altera_merlin_width_adapter:width_adapter|address_reg[18] ; +; 3:1 ; 21 bits ; 42 LEs ; 42 LEs ; 0 LEs ; Yes ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|d_address_line_field[0] ; +; 3:1 ; 4 bits ; 8 LEs ; 0 LEs ; 8 LEs ; Yes ; |de0_nano_system|system:inst_cpu|altera_merlin_traffic_limiter:limiter_001|pending_response_count[0] ; +; 3:1 ; 10 bits ; 20 LEs ; 10 LEs ; 10 LEs ; Yes ; |de0_nano_system|system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|count[7] ; +; 3:1 ; 4 bits ; 8 LEs ; 0 LEs ; 8 LEs ; Yes ; |de0_nano_system|system:inst_cpu|altera_merlin_traffic_limiter:limiter|pending_response_count[1] ; +; 3:1 ; 6 bits ; 12 LEs ; 6 LEs ; 6 LEs ; Yes ; |de0_nano_system|system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[6] ; +; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_translator:cpu_jtag_debug_module_translator|wait_latency_counter[1] ; +; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_translator:sysid_control_slave_translator|wait_latency_counter[1] ; +; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_translator:sys_clk_timer_s1_translator|wait_latency_counter[1] ; +; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_translator:uart_0_s1_translator|wait_latency_counter[1] ; +; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_translator:pio_key_s1_translator|wait_latency_counter[0] ; +; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_translator:pio_sw_s1_translator|wait_latency_counter[0] ; +; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_translator:pio_motor_rst_s1_translator|wait_latency_counter[0] ; +; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|M_mem_byte_en[0] ; +; 3:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; Yes ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|A_slow_inst_result[2] ; +; 3:1 ; 3 bits ; 6 LEs ; 6 LEs ; 0 LEs ; Yes ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_translator:cpu_jtag_debug_module_translator|av_readdata_pre[3] ; +; 3:1 ; 20 bits ; 40 LEs ; 40 LEs ; 0 LEs ; Yes ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|D_iw[27] ; +; 3:1 ; 27 bits ; 54 LEs ; 54 LEs ; 0 LEs ; Yes ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|A_inst_result[29] ; +; 3:1 ; 5 bits ; 10 LEs ; 10 LEs ; 0 LEs ; Yes ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|A_inst_result[14] ; +; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |de0_nano_system|system:inst_cpu|system_rs232_motor:rs232_motor|read_interrupt_en ; +; 3:1 ; 10 bits ; 20 LEs ; 10 LEs ; 10 LEs ; Yes ; |de0_nano_system|system:inst_cpu|system_uart_0:uart_0|system_uart_0_rx:the_system_uart_0_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[0] ; +; 3:1 ; 9 bits ; 18 LEs ; 9 LEs ; 9 LEs ; Yes ; |de0_nano_system|system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|data_in_shift_reg[1] ; +; 3:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|ic_fill_ap_cnt[2] ; +; 3:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; Yes ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|ic_fill_ap_offset[2] ; +; 4:1 ; 32 bits ; 64 LEs ; 64 LEs ; 0 LEs ; Yes ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|d_writedata[15] ; +; 4:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|A_dc_rd_data_cnt[2] ; +; 4:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|A_dc_rd_addr_cnt[1] ; +; 4:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|A_dc_wr_data_cnt[2] ; +; 4:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |de0_nano_system|system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|td_shift[9] ; +; 4:1 ; 19 bits ; 38 LEs ; 38 LEs ; 0 LEs ; Yes ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[13] ; +; 4:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; Yes ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|ic_tag_wraddress[6] ; +; 4:1 ; 15 bits ; 30 LEs ; 30 LEs ; 0 LEs ; Yes ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|E_src2[26] ; +; 8:1 ; 4 bits ; 20 LEs ; 8 LEs ; 12 LEs ; Yes ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|E_control_reg_rddata[4] ; +; 4:1 ; 7 bits ; 14 LEs ; 14 LEs ; 0 LEs ; Yes ; |de0_nano_system|system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|data_out_shift_reg[5] ; +; 3:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |de0_nano_system|system:inst_cpu|system_uart_0:uart_0|system_uart_0_tx:the_system_uart_0_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[5] ; +; 4:1 ; 14 bits ; 28 LEs ; 14 LEs ; 14 LEs ; Yes ; |de0_nano_system|system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_rs232_counters:RS232_Out_Counters|baud_counter[7] ; +; 4:1 ; 3 bits ; 6 LEs ; 6 LEs ; 0 LEs ; Yes ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_translator:cpu_jtag_debug_module_translator|av_readdata_pre[4] ; +; 4:1 ; 14 bits ; 28 LEs ; 14 LEs ; 14 LEs ; Yes ; |de0_nano_system|system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_rs232_counters:RS232_In_Counters|baud_counter[4] ; +; 4:1 ; 7 bits ; 14 LEs ; 7 LEs ; 7 LEs ; Yes ; |de0_nano_system|system:inst_cpu|system_rs232_motor:rs232_motor|readdata[7] ; +; 4:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |de0_nano_system|system:inst_cpu|system_rs232_motor:rs232_motor|readdata[8] ; +; 4:1 ; 10 bits ; 20 LEs ; 20 LEs ; 0 LEs ; Yes ; |de0_nano_system|system:inst_cpu|system_rs232_motor:rs232_motor|readdata[22] ; +; 4:1 ; 11 bits ; 22 LEs ; 22 LEs ; 0 LEs ; Yes ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[0] ; +; 3:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; Yes ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|M_st_data[30] ; +; 3:1 ; 15 bits ; 30 LEs ; 30 LEs ; 0 LEs ; Yes ; |de0_nano_system|system:inst_cpu|system_uart_0:uart_0|system_uart_0_rx:the_system_uart_0_rx|baud_rate_counter[8] ; +; 6:1 ; 2 bits ; 8 LEs ; 2 LEs ; 6 LEs ; Yes ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[36] ; +; 6:1 ; 2 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[33] ; +; 6:1 ; 13 bits ; 52 LEs ; 26 LEs ; 26 LEs ; Yes ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[8] ; +; 6:1 ; 16 bits ; 64 LEs ; 32 LEs ; 32 LEs ; Yes ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[16] ; +; 4:1 ; 7 bits ; 14 LEs ; 14 LEs ; 0 LEs ; Yes ; |de0_nano_system|system:inst_cpu|system_pio_led:pio_led|data_out[3] ; +; 5:1 ; 3 bits ; 9 LEs ; 6 LEs ; 3 LEs ; Yes ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|d_address_offset_field[0] ; +; 5:1 ; 32 bits ; 96 LEs ; 96 LEs ; 0 LEs ; Yes ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|E_src1[4] ; +; 4:1 ; 9 bits ; 18 LEs ; 9 LEs ; 9 LEs ; Yes ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonAReg[8] ; +; 5:1 ; 4 bits ; 12 LEs ; 4 LEs ; 8 LEs ; Yes ; |de0_nano_system|system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_rs232_counters:RS232_Out_Counters|bit_counter[3] ; +; 5:1 ; 4 bits ; 12 LEs ; 4 LEs ; 8 LEs ; Yes ; |de0_nano_system|system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_rs232_counters:RS232_In_Counters|bit_counter[0] ; +; 4:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |de0_nano_system|system:inst_cpu|system_sdram:sdram|m_dqm[0] ; +; 5:1 ; 32 bits ; 96 LEs ; 32 LEs ; 64 LEs ; Yes ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_break:the_system_cpu_nios2_oci_break|break_readreg[31] ; +; 5:1 ; 2 bits ; 6 LEs ; 6 LEs ; 0 LEs ; Yes ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|M_mem_byte_en[2] ; +; 6:1 ; 13 bits ; 52 LEs ; 52 LEs ; 0 LEs ; Yes ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|F_pc[15] ; +; 6:1 ; 23 bits ; 92 LEs ; 92 LEs ; 0 LEs ; Yes ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|M_pipe_flush_waddr[3] ; +; 6:1 ; 5 bits ; 20 LEs ; 10 LEs ; 10 LEs ; Yes ; |de0_nano_system|system:inst_cpu|system_sdram:sdram|m_addr[9] ; +; 7:1 ; 2 bits ; 8 LEs ; 6 LEs ; 2 LEs ; Yes ; |de0_nano_system|system:inst_cpu|system_sdram:sdram|m_addr[5] ; +; 7:1 ; 6 bits ; 24 LEs ; 18 LEs ; 6 LEs ; Yes ; |de0_nano_system|system:inst_cpu|system_sdram:sdram|m_addr[7] ; +; 5:1 ; 3 bits ; 9 LEs ; 6 LEs ; 3 LEs ; Yes ; |de0_nano_system|system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|td_shift[4] ; +; 5:1 ; 4 bits ; 12 LEs ; 8 LEs ; 4 LEs ; Yes ; |de0_nano_system|system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|td_shift[5] ; +; 12:1 ; 42 bits ; 336 LEs ; 0 LEs ; 336 LEs ; Yes ; |de0_nano_system|system:inst_cpu|system_sdram:sdram|active_addr[22] ; +; 4:1 ; 16 bits ; 32 LEs ; 32 LEs ; 0 LEs ; Yes ; |de0_nano_system|system:inst_cpu|system_sdram:sdram|m_data[2] ; +; 4:1 ; 32 bits ; 64 LEs ; 64 LEs ; 0 LEs ; No ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|E_logic_result[13] ; +; 3:1 ; 12 bits ; 24 LEs ; 24 LEs ; 0 LEs ; No ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|F_iw[2] ; +; 3:1 ; 10 bits ; 20 LEs ; 20 LEs ; 0 LEs ; No ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|dc_data_rd_port_addr[2] ; +; 3:1 ; 7 bits ; 14 LEs ; 7 LEs ; 7 LEs ; No ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|dc_data_wr_port_addr[9] ; +; 3:1 ; 35 bits ; 70 LEs ; 70 LEs ; 0 LEs ; No ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|dc_data_wr_port_data[6] ; +; 4:1 ; 3 bits ; 6 LEs ; 6 LEs ; 0 LEs ; No ; |de0_nano_system|system:inst_cpu|system_addr_router_001:addr_router_001|src_channel[6] ; +; 4:1 ; 5 bits ; 10 LEs ; 10 LEs ; 0 LEs ; No ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|D_dst_regnum[3] ; +; 4:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; No ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|dc_data_wr_port_byte_en[1] ; +; 5:1 ; 32 bits ; 96 LEs ; 96 LEs ; 0 LEs ; No ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|D_src2_reg[8] ; +; 5:1 ; 16 bits ; 48 LEs ; 48 LEs ; 0 LEs ; No ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|A_wr_data_unfiltered[20] ; +; 5:1 ; 8 bits ; 24 LEs ; 24 LEs ; 0 LEs ; No ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|A_wr_data_unfiltered[14] ; +; 6:1 ; 2 bits ; 8 LEs ; 4 LEs ; 4 LEs ; No ; |de0_nano_system|system:inst_cpu|system_addr_router_001:addr_router_001|src_data[88] ; +; 6:1 ; 8 bits ; 32 LEs ; 32 LEs ; 0 LEs ; No ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|A_wr_data_unfiltered[3] ; +; 6:1 ; 11 bits ; 44 LEs ; 44 LEs ; 0 LEs ; No ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|F_ic_tag_rd_addr_nxt[0] ; +; 9:1 ; 2 bits ; 12 LEs ; 12 LEs ; 0 LEs ; No ; |de0_nano_system|system:inst_cpu|system_addr_router_001:addr_router_001|src_data[89] ; +; 10:1 ; 3 bits ; 18 LEs ; 18 LEs ; 0 LEs ; No ; |de0_nano_system|system:inst_cpu|system_addr_router_001:addr_router_001|src_channel[0] ; +; 11:1 ; 2 bits ; 14 LEs ; 4 LEs ; 10 LEs ; No ; |de0_nano_system|system:inst_cpu|system_sdram:sdram|Selector34 ; +; 16:1 ; 2 bits ; 20 LEs ; 8 LEs ; 12 LEs ; No ; |de0_nano_system|system:inst_cpu|system_sdram:sdram|Selector28 ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------+ +; Source assignments for system:inst_cpu|system_sdram:sdram ; ++-----------------------------+-------+------+------------------+ +; Assignment ; Value ; From ; To ; ++-----------------------------+-------+------+------------------+ +; FAST_INPUT_REGISTER ; ON ; - ; za_data[15] ; +; FAST_INPUT_REGISTER ; ON ; - ; za_data[14] ; +; FAST_INPUT_REGISTER ; ON ; - ; za_data[13] ; +; FAST_INPUT_REGISTER ; ON ; - ; za_data[12] ; +; FAST_INPUT_REGISTER ; ON ; - ; za_data[11] ; +; FAST_INPUT_REGISTER ; ON ; - ; za_data[10] ; +; FAST_INPUT_REGISTER ; ON ; - ; za_data[9] ; +; FAST_INPUT_REGISTER ; ON ; - ; za_data[8] ; +; FAST_INPUT_REGISTER ; ON ; - ; za_data[7] ; +; FAST_INPUT_REGISTER ; ON ; - ; za_data[6] ; +; FAST_INPUT_REGISTER ; ON ; - ; za_data[5] ; +; FAST_INPUT_REGISTER ; ON ; - ; za_data[4] ; +; FAST_INPUT_REGISTER ; ON ; - ; za_data[3] ; +; FAST_INPUT_REGISTER ; ON ; - ; za_data[2] ; +; FAST_INPUT_REGISTER ; ON ; - ; za_data[1] ; +; FAST_INPUT_REGISTER ; ON ; - ; za_data[0] ; +; FAST_OUTPUT_REGISTER ; ON ; - ; m_cmd[3] ; +; FAST_OUTPUT_REGISTER ; ON ; - ; m_cmd[2] ; +; FAST_OUTPUT_REGISTER ; ON ; - ; m_cmd[1] ; +; FAST_OUTPUT_REGISTER ; ON ; - ; m_cmd[0] ; +; FAST_OUTPUT_REGISTER ; ON ; - ; m_bank[1] ; +; FAST_OUTPUT_REGISTER ; ON ; - ; m_bank[0] ; +; FAST_OUTPUT_REGISTER ; ON ; - ; m_addr[12] ; +; FAST_OUTPUT_REGISTER ; ON ; - ; m_addr[11] ; +; FAST_OUTPUT_REGISTER ; ON ; - ; m_addr[10] ; +; FAST_OUTPUT_REGISTER ; ON ; - ; m_addr[9] ; +; FAST_OUTPUT_REGISTER ; ON ; - ; m_addr[8] ; +; FAST_OUTPUT_REGISTER ; ON ; - ; m_addr[7] ; +; FAST_OUTPUT_REGISTER ; ON ; - ; m_addr[6] ; +; FAST_OUTPUT_REGISTER ; ON ; - ; m_addr[5] ; +; FAST_OUTPUT_REGISTER ; ON ; - ; m_addr[4] ; +; FAST_OUTPUT_REGISTER ; ON ; - ; m_addr[3] ; +; FAST_OUTPUT_REGISTER ; ON ; - ; m_addr[2] ; +; FAST_OUTPUT_REGISTER ; ON ; - ; m_addr[1] ; +; FAST_OUTPUT_REGISTER ; ON ; - ; m_addr[0] ; +; FAST_OUTPUT_REGISTER ; ON ; - ; m_data[15] ; +; FAST_OUTPUT_ENABLE_REGISTER ; ON ; - ; m_data[15] ; +; FAST_OUTPUT_REGISTER ; ON ; - ; m_data[14] ; +; FAST_OUTPUT_ENABLE_REGISTER ; ON ; - ; m_data[14] ; +; FAST_OUTPUT_REGISTER ; ON ; - ; m_data[13] ; +; FAST_OUTPUT_ENABLE_REGISTER ; ON ; - ; m_data[13] ; +; FAST_OUTPUT_REGISTER ; ON ; - ; m_data[12] ; +; FAST_OUTPUT_ENABLE_REGISTER ; ON ; - ; m_data[12] ; +; FAST_OUTPUT_REGISTER ; ON ; - ; m_data[11] ; +; FAST_OUTPUT_ENABLE_REGISTER ; ON ; - ; m_data[11] ; +; FAST_OUTPUT_REGISTER ; ON ; - ; m_data[10] ; +; FAST_OUTPUT_ENABLE_REGISTER ; ON ; - ; m_data[10] ; +; FAST_OUTPUT_REGISTER ; ON ; - ; m_data[9] ; +; FAST_OUTPUT_ENABLE_REGISTER ; ON ; - ; m_data[9] ; +; FAST_OUTPUT_REGISTER ; ON ; - ; m_data[8] ; +; FAST_OUTPUT_ENABLE_REGISTER ; ON ; - ; m_data[8] ; +; FAST_OUTPUT_REGISTER ; ON ; - ; m_data[7] ; +; FAST_OUTPUT_ENABLE_REGISTER ; ON ; - ; m_data[7] ; +; FAST_OUTPUT_REGISTER ; ON ; - ; m_data[6] ; +; FAST_OUTPUT_ENABLE_REGISTER ; ON ; - ; m_data[6] ; +; FAST_OUTPUT_REGISTER ; ON ; - ; m_data[5] ; +; FAST_OUTPUT_ENABLE_REGISTER ; ON ; - ; m_data[5] ; +; FAST_OUTPUT_REGISTER ; ON ; - ; m_data[4] ; +; FAST_OUTPUT_ENABLE_REGISTER ; ON ; - ; m_data[4] ; +; FAST_OUTPUT_REGISTER ; ON ; - ; m_data[3] ; +; FAST_OUTPUT_ENABLE_REGISTER ; ON ; - ; m_data[3] ; +; FAST_OUTPUT_REGISTER ; ON ; - ; m_data[2] ; +; FAST_OUTPUT_ENABLE_REGISTER ; ON ; - ; m_data[2] ; +; FAST_OUTPUT_REGISTER ; ON ; - ; m_data[1] ; +; FAST_OUTPUT_ENABLE_REGISTER ; ON ; - ; m_data[1] ; +; FAST_OUTPUT_REGISTER ; ON ; - ; m_data[0] ; +; FAST_OUTPUT_ENABLE_REGISTER ; ON ; - ; m_data[0] ; +; FAST_OUTPUT_REGISTER ; ON ; - ; m_dqm[1] ; +; FAST_OUTPUT_REGISTER ; ON ; - ; m_dqm[0] ; +; FAST_OUTPUT_ENABLE_REGISTER ; ON ; - ; oe ; +; FAST_INPUT_REGISTER ; ON ; - ; za_data[15]~reg0 ; +; FAST_INPUT_REGISTER ; ON ; - ; za_data[14]~reg0 ; +; FAST_INPUT_REGISTER ; ON ; - ; za_data[13]~reg0 ; +; FAST_INPUT_REGISTER ; ON ; - ; za_data[12]~reg0 ; +; FAST_INPUT_REGISTER ; ON ; - ; za_data[11]~reg0 ; +; FAST_INPUT_REGISTER ; ON ; - ; za_data[10]~reg0 ; +; FAST_INPUT_REGISTER ; ON ; - ; za_data[9]~reg0 ; +; FAST_INPUT_REGISTER ; ON ; - ; za_data[8]~reg0 ; +; FAST_INPUT_REGISTER ; ON ; - ; za_data[7]~reg0 ; +; FAST_INPUT_REGISTER ; ON ; - ; za_data[6]~reg0 ; +; FAST_INPUT_REGISTER ; ON ; - ; za_data[5]~reg0 ; +; FAST_INPUT_REGISTER ; ON ; - ; za_data[4]~reg0 ; +; FAST_INPUT_REGISTER ; ON ; - ; za_data[3]~reg0 ; +; FAST_INPUT_REGISTER ; ON ; - ; za_data[2]~reg0 ; +; FAST_INPUT_REGISTER ; ON ; - ; za_data[1]~reg0 ; +; FAST_INPUT_REGISTER ; ON ; - ; za_data[0]~reg0 ; ++-----------------------------+-------+------+------------------+ + + ++-------------------------------------------------------------+ +; Source assignments for system:inst_cpu|system_uart_0:uart_0 ; ++-----------------------------+-------+------+----------------+ +; Assignment ; Value ; From ; To ; ++-----------------------------+-------+------+----------------+ +; SYNCHRONIZER_IDENTIFICATION ; OFF ; - ; - ; ++-----------------------------+-------+------+----------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for system:inst_cpu|system_uart_0:uart_0|system_uart_0_rx:the_system_uart_0_rx|altera_std_synchronizer:the_altera_std_synchronizer ; ++-----------------------------+------------------------+------+-----------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++-----------------------------+------------------------+------+-----------------------------------------------------------------------------------------+ +; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; dreg[0] ; +; DONT_MERGE_REGISTER ; ON ; - ; dreg[0] ; +; PRESERVE_REGISTER ; ON ; - ; dreg[0] ; +; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; din_s1 ; +; DONT_MERGE_REGISTER ; ON ; - ; din_s1 ; +; PRESERVE_REGISTER ; ON ; - ; din_s1 ; ++-----------------------------+------------------------+------+-----------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1 ; ++---------------------------------+--------------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+--------------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; ++---------------------------------+--------------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1 ; ++---------------------------------+--------------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+--------------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; ++---------------------------------+--------------------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram ; ++---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; ++---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram ; ++---------------------------------+--------------------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+--------------------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; ++---------------------------------+--------------------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1 ; ++-------------------+-------+------+---------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++-------------------+-------+------+---------------------------------------------------------------------------------------+ +; PRESERVE_REGISTER ; on ; - ; altera_reset_synchronizer_int_chain[1] ; +; PRESERVE_REGISTER ; on ; - ; altera_reset_synchronizer_int_chain[0] ; ++-------------------+-------+------+---------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------+ +; Source assignments for system:inst_cpu|system_cmd_xbar_demux:cmd_xbar_demux ; ++-----------------+-------+------+--------------------------------------------+ +; Assignment ; Value ; From ; To ; ++-----------------+-------+------+--------------------------------------------+ +; MESSAGE_DISABLE ; 15610 ; - ; clk ; +; MESSAGE_DISABLE ; 15610 ; - ; reset ; ++-----------------+-------+------+--------------------------------------------+ + + ++-------------------------------------------------------------------------------------+ +; Source assignments for system:inst_cpu|system_cmd_xbar_demux_001:cmd_xbar_demux_001 ; ++-----------------+-------+------+----------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++-----------------+-------+------+----------------------------------------------------+ +; MESSAGE_DISABLE ; 15610 ; - ; clk ; +; MESSAGE_DISABLE ; 15610 ; - ; reset ; ++-----------------+-------+------+----------------------------------------------------+ + + ++-----------------------------------------------------------------------------+ +; Source assignments for system:inst_cpu|system_rsp_xbar_demux:rsp_xbar_demux ; ++-----------------+-------+------+--------------------------------------------+ +; Assignment ; Value ; From ; To ; ++-----------------+-------+------+--------------------------------------------+ +; MESSAGE_DISABLE ; 15610 ; - ; clk ; +; MESSAGE_DISABLE ; 15610 ; - ; reset ; ++-----------------+-------+------+--------------------------------------------+ + + ++---------------------------------------------------------------------------------+ +; Source assignments for system:inst_cpu|system_rsp_xbar_demux:rsp_xbar_demux_001 ; ++-----------------+-------+------+------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++-----------------+-------+------+------------------------------------------------+ +; MESSAGE_DISABLE ; 15610 ; - ; clk ; +; MESSAGE_DISABLE ; 15610 ; - ; reset ; ++-----------------+-------+------+------------------------------------------------+ + + ++-------------------------------------------------------------------------------------+ +; Source assignments for system:inst_cpu|system_rsp_xbar_demux_002:rsp_xbar_demux_002 ; ++-----------------+-------+------+----------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++-----------------+-------+------+----------------------------------------------------+ +; MESSAGE_DISABLE ; 15610 ; - ; clk ; +; MESSAGE_DISABLE ; 15610 ; - ; reset ; ++-----------------+-------+------+----------------------------------------------------+ + + ++-------------------------------------------------------------------------------------+ +; Source assignments for system:inst_cpu|system_rsp_xbar_demux_002:rsp_xbar_demux_003 ; ++-----------------+-------+------+----------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++-----------------+-------+------+----------------------------------------------------+ +; MESSAGE_DISABLE ; 15610 ; - ; clk ; +; MESSAGE_DISABLE ; 15610 ; - ; reset ; ++-----------------+-------+------+----------------------------------------------------+ + + ++-------------------------------------------------------------------------------------+ +; Source assignments for system:inst_cpu|system_rsp_xbar_demux_002:rsp_xbar_demux_004 ; ++-----------------+-------+------+----------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++-----------------+-------+------+----------------------------------------------------+ +; MESSAGE_DISABLE ; 15610 ; - ; clk ; +; MESSAGE_DISABLE ; 15610 ; - ; reset ; ++-----------------+-------+------+----------------------------------------------------+ + + ++-------------------------------------------------------------------------------------+ +; Source assignments for system:inst_cpu|system_rsp_xbar_demux_002:rsp_xbar_demux_005 ; ++-----------------+-------+------+----------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++-----------------+-------+------+----------------------------------------------------+ +; MESSAGE_DISABLE ; 15610 ; - ; clk ; +; MESSAGE_DISABLE ; 15610 ; - ; reset ; ++-----------------+-------+------+----------------------------------------------------+ + + ++-------------------------------------------------------------------------------------+ +; Source assignments for system:inst_cpu|system_rsp_xbar_demux_002:rsp_xbar_demux_006 ; ++-----------------+-------+------+----------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++-----------------+-------+------+----------------------------------------------------+ +; MESSAGE_DISABLE ; 15610 ; - ; clk ; +; MESSAGE_DISABLE ; 15610 ; - ; reset ; ++-----------------+-------+------+----------------------------------------------------+ + + ++-------------------------------------------------------------------------------------+ +; Source assignments for system:inst_cpu|system_rsp_xbar_demux_002:rsp_xbar_demux_007 ; ++-----------------+-------+------+----------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++-----------------+-------+------+----------------------------------------------------+ +; MESSAGE_DISABLE ; 15610 ; - ; clk ; +; MESSAGE_DISABLE ; 15610 ; - ; reset ; ++-----------------+-------+------+----------------------------------------------------+ + + ++-------------------------------------------------------------------------------------+ +; Source assignments for system:inst_cpu|system_rsp_xbar_demux_002:rsp_xbar_demux_008 ; ++-----------------+-------+------+----------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++-----------------+-------+------+----------------------------------------------------+ +; MESSAGE_DISABLE ; 15610 ; - ; clk ; +; MESSAGE_DISABLE ; 15610 ; - ; reset ; ++-----------------+-------+------+----------------------------------------------------+ + + ++-------------------------------------------------------------------------------------+ +; Source assignments for system:inst_cpu|system_rsp_xbar_demux_002:rsp_xbar_demux_009 ; ++-----------------+-------+------+----------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++-----------------+-------+------+----------------------------------------------------+ +; MESSAGE_DISABLE ; 15610 ; - ; clk ; +; MESSAGE_DISABLE ; 15610 ; - ; reset ; ++-----------------+-------+------+----------------------------------------------------+ + + ++-------------------------------------------------------------------------------------+ +; Source assignments for system:inst_cpu|system_rsp_xbar_demux_002:rsp_xbar_demux_010 ; ++-----------------+-------+------+----------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++-----------------+-------+------+----------------------------------------------------+ +; MESSAGE_DISABLE ; 15610 ; - ; clk ; +; MESSAGE_DISABLE ; 15610 ; - ; reset ; ++-----------------+-------+------+----------------------------------------------------+ + + ++-------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: pll_sys:inst_pll_sys|altpll:altpll_component ; ++-------------------------------+---------------------------+-------------------------------+ +; Parameter Name ; Value ; Type ; ++-------------------------------+---------------------------+-------------------------------+ +; OPERATION_MODE ; NORMAL ; Untyped ; +; PLL_TYPE ; AUTO ; Untyped ; +; LPM_HINT ; CBX_MODULE_PREFIX=pll_sys ; Untyped ; +; QUALIFY_CONF_DONE ; OFF ; Untyped ; +; COMPENSATE_CLOCK ; CLK0 ; Untyped ; +; SCAN_CHAIN ; LONG ; Untyped ; +; PRIMARY_CLOCK ; INCLK0 ; Untyped ; +; INCLK0_INPUT_FREQUENCY ; 20000 ; Signed Integer ; +; INCLK1_INPUT_FREQUENCY ; 0 ; Untyped ; +; GATE_LOCK_SIGNAL ; NO ; Untyped ; +; GATE_LOCK_COUNTER ; 0 ; Untyped ; +; LOCK_HIGH ; 1 ; Untyped ; +; LOCK_LOW ; 1 ; Untyped ; +; VALID_LOCK_MULTIPLIER ; 1 ; Untyped ; +; INVALID_LOCK_MULTIPLIER ; 5 ; Untyped ; +; SWITCH_OVER_ON_LOSSCLK ; OFF ; Untyped ; +; SWITCH_OVER_ON_GATED_LOCK ; OFF ; Untyped ; +; ENABLE_SWITCH_OVER_COUNTER ; OFF ; Untyped ; +; SKIP_VCO ; OFF ; Untyped ; +; SWITCH_OVER_COUNTER ; 0 ; Untyped ; +; SWITCH_OVER_TYPE ; AUTO ; Untyped ; +; FEEDBACK_SOURCE ; EXTCLK0 ; Untyped ; +; BANDWIDTH ; 0 ; Untyped ; +; BANDWIDTH_TYPE ; AUTO ; Untyped ; +; SPREAD_FREQUENCY ; 0 ; Untyped ; +; DOWN_SPREAD ; 0 ; Untyped ; +; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF ; Untyped ; +; SELF_RESET_ON_LOSS_LOCK ; ON ; Untyped ; +; CLK9_MULTIPLY_BY ; 0 ; Untyped ; +; CLK8_MULTIPLY_BY ; 0 ; Untyped ; +; CLK7_MULTIPLY_BY ; 0 ; Untyped ; +; CLK6_MULTIPLY_BY ; 0 ; Untyped ; +; CLK5_MULTIPLY_BY ; 1 ; Untyped ; +; CLK4_MULTIPLY_BY ; 1 ; Untyped ; +; CLK3_MULTIPLY_BY ; 1 ; Untyped ; +; CLK2_MULTIPLY_BY ; 1 ; Signed Integer ; +; CLK1_MULTIPLY_BY ; 2 ; Signed Integer ; +; CLK0_MULTIPLY_BY ; 2 ; Signed Integer ; +; CLK9_DIVIDE_BY ; 0 ; Untyped ; +; CLK8_DIVIDE_BY ; 0 ; Untyped ; +; CLK7_DIVIDE_BY ; 0 ; Untyped ; +; CLK6_DIVIDE_BY ; 0 ; Untyped ; +; CLK5_DIVIDE_BY ; 1 ; Untyped ; +; CLK4_DIVIDE_BY ; 1 ; Untyped ; +; CLK3_DIVIDE_BY ; 1 ; Untyped ; +; CLK2_DIVIDE_BY ; 5 ; Signed Integer ; +; CLK1_DIVIDE_BY ; 1 ; Signed Integer ; +; CLK0_DIVIDE_BY ; 1 ; Signed Integer ; +; CLK9_PHASE_SHIFT ; 0 ; Untyped ; +; CLK8_PHASE_SHIFT ; 0 ; Untyped ; +; CLK7_PHASE_SHIFT ; 0 ; Untyped ; +; CLK6_PHASE_SHIFT ; 0 ; Untyped ; +; CLK5_PHASE_SHIFT ; 0 ; Untyped ; +; CLK4_PHASE_SHIFT ; 0 ; Untyped ; +; CLK3_PHASE_SHIFT ; 0 ; Untyped ; +; CLK2_PHASE_SHIFT ; 0 ; Untyped ; +; CLK1_PHASE_SHIFT ; -1500 ; Untyped ; +; CLK0_PHASE_SHIFT ; 0 ; Untyped ; +; CLK5_TIME_DELAY ; 0 ; Untyped ; +; CLK4_TIME_DELAY ; 0 ; Untyped ; +; CLK3_TIME_DELAY ; 0 ; Untyped ; +; CLK2_TIME_DELAY ; 0 ; Untyped ; +; CLK1_TIME_DELAY ; 0 ; Untyped ; +; CLK0_TIME_DELAY ; 0 ; Untyped ; +; CLK9_DUTY_CYCLE ; 50 ; Untyped ; +; CLK8_DUTY_CYCLE ; 50 ; Untyped ; +; CLK7_DUTY_CYCLE ; 50 ; Untyped ; +; CLK6_DUTY_CYCLE ; 50 ; Untyped ; +; CLK5_DUTY_CYCLE ; 50 ; Untyped ; +; CLK4_DUTY_CYCLE ; 50 ; Untyped ; +; CLK3_DUTY_CYCLE ; 50 ; Untyped ; +; CLK2_DUTY_CYCLE ; 50 ; Signed Integer ; +; CLK1_DUTY_CYCLE ; 50 ; Signed Integer ; +; CLK0_DUTY_CYCLE ; 50 ; Signed Integer ; +; CLK9_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK8_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK7_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK6_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK5_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK4_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK3_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK2_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK1_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK0_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK9_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK8_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK7_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK6_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK5_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK4_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK3_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK2_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK1_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK0_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; LOCK_WINDOW_UI ; 0.05 ; Untyped ; +; LOCK_WINDOW_UI_BITS ; UNUSED ; Untyped ; +; VCO_RANGE_DETECTOR_LOW_BITS ; UNUSED ; Untyped ; +; VCO_RANGE_DETECTOR_HIGH_BITS ; UNUSED ; Untyped ; +; DPA_MULTIPLY_BY ; 0 ; Untyped ; +; DPA_DIVIDE_BY ; 1 ; Untyped ; +; DPA_DIVIDER ; 0 ; Untyped ; +; EXTCLK3_MULTIPLY_BY ; 1 ; Untyped ; +; EXTCLK2_MULTIPLY_BY ; 1 ; Untyped ; +; EXTCLK1_MULTIPLY_BY ; 1 ; Untyped ; +; EXTCLK0_MULTIPLY_BY ; 1 ; Untyped ; +; EXTCLK3_DIVIDE_BY ; 1 ; Untyped ; +; EXTCLK2_DIVIDE_BY ; 1 ; Untyped ; +; EXTCLK1_DIVIDE_BY ; 1 ; Untyped ; +; EXTCLK0_DIVIDE_BY ; 1 ; Untyped ; +; EXTCLK3_PHASE_SHIFT ; 0 ; Untyped ; +; EXTCLK2_PHASE_SHIFT ; 0 ; Untyped ; +; EXTCLK1_PHASE_SHIFT ; 0 ; Untyped ; +; EXTCLK0_PHASE_SHIFT ; 0 ; Untyped ; +; EXTCLK3_TIME_DELAY ; 0 ; Untyped ; +; EXTCLK2_TIME_DELAY ; 0 ; Untyped ; +; EXTCLK1_TIME_DELAY ; 0 ; Untyped ; +; EXTCLK0_TIME_DELAY ; 0 ; Untyped ; +; EXTCLK3_DUTY_CYCLE ; 50 ; Untyped ; +; EXTCLK2_DUTY_CYCLE ; 50 ; Untyped ; +; EXTCLK1_DUTY_CYCLE ; 50 ; Untyped ; +; EXTCLK0_DUTY_CYCLE ; 50 ; Untyped ; +; VCO_MULTIPLY_BY ; 0 ; Untyped ; +; VCO_DIVIDE_BY ; 0 ; Untyped ; +; SCLKOUT0_PHASE_SHIFT ; 0 ; Untyped ; +; SCLKOUT1_PHASE_SHIFT ; 0 ; Untyped ; +; VCO_MIN ; 0 ; Untyped ; +; VCO_MAX ; 0 ; Untyped ; +; VCO_CENTER ; 0 ; Untyped ; +; PFD_MIN ; 0 ; Untyped ; +; PFD_MAX ; 0 ; Untyped ; +; M_INITIAL ; 0 ; Untyped ; +; M ; 0 ; Untyped ; +; N ; 1 ; Untyped ; +; M2 ; 1 ; Untyped ; +; N2 ; 1 ; Untyped ; +; SS ; 1 ; Untyped ; +; C0_HIGH ; 0 ; Untyped ; +; C1_HIGH ; 0 ; Untyped ; +; C2_HIGH ; 0 ; Untyped ; +; C3_HIGH ; 0 ; Untyped ; +; C4_HIGH ; 0 ; Untyped ; +; C5_HIGH ; 0 ; Untyped ; +; C6_HIGH ; 0 ; Untyped ; +; C7_HIGH ; 0 ; Untyped ; +; C8_HIGH ; 0 ; Untyped ; +; C9_HIGH ; 0 ; Untyped ; +; C0_LOW ; 0 ; Untyped ; +; C1_LOW ; 0 ; Untyped ; +; C2_LOW ; 0 ; Untyped ; +; C3_LOW ; 0 ; Untyped ; +; C4_LOW ; 0 ; Untyped ; +; C5_LOW ; 0 ; Untyped ; +; C6_LOW ; 0 ; Untyped ; +; C7_LOW ; 0 ; Untyped ; +; C8_LOW ; 0 ; Untyped ; +; C9_LOW ; 0 ; Untyped ; +; C0_INITIAL ; 0 ; Untyped ; +; C1_INITIAL ; 0 ; Untyped ; +; C2_INITIAL ; 0 ; Untyped ; +; C3_INITIAL ; 0 ; Untyped ; +; C4_INITIAL ; 0 ; Untyped ; +; C5_INITIAL ; 0 ; Untyped ; +; C6_INITIAL ; 0 ; Untyped ; +; C7_INITIAL ; 0 ; Untyped ; +; C8_INITIAL ; 0 ; Untyped ; +; C9_INITIAL ; 0 ; Untyped ; +; C0_MODE ; BYPASS ; Untyped ; +; C1_MODE ; BYPASS ; Untyped ; +; C2_MODE ; BYPASS ; Untyped ; +; C3_MODE ; BYPASS ; Untyped ; +; C4_MODE ; BYPASS ; Untyped ; +; C5_MODE ; BYPASS ; Untyped ; +; C6_MODE ; BYPASS ; Untyped ; +; C7_MODE ; BYPASS ; Untyped ; +; C8_MODE ; BYPASS ; Untyped ; +; C9_MODE ; BYPASS ; Untyped ; +; C0_PH ; 0 ; Untyped ; +; C1_PH ; 0 ; Untyped ; +; C2_PH ; 0 ; Untyped ; +; C3_PH ; 0 ; Untyped ; +; C4_PH ; 0 ; Untyped ; +; C5_PH ; 0 ; Untyped ; +; C6_PH ; 0 ; Untyped ; +; C7_PH ; 0 ; Untyped ; +; C8_PH ; 0 ; Untyped ; +; C9_PH ; 0 ; Untyped ; +; L0_HIGH ; 1 ; Untyped ; +; L1_HIGH ; 1 ; Untyped ; +; G0_HIGH ; 1 ; Untyped ; +; G1_HIGH ; 1 ; Untyped ; +; G2_HIGH ; 1 ; Untyped ; +; G3_HIGH ; 1 ; Untyped ; +; E0_HIGH ; 1 ; Untyped ; +; E1_HIGH ; 1 ; Untyped ; +; E2_HIGH ; 1 ; Untyped ; +; E3_HIGH ; 1 ; Untyped ; +; L0_LOW ; 1 ; Untyped ; +; L1_LOW ; 1 ; Untyped ; +; G0_LOW ; 1 ; Untyped ; +; G1_LOW ; 1 ; Untyped ; +; G2_LOW ; 1 ; Untyped ; +; G3_LOW ; 1 ; Untyped ; +; E0_LOW ; 1 ; Untyped ; +; E1_LOW ; 1 ; Untyped ; +; E2_LOW ; 1 ; Untyped ; +; E3_LOW ; 1 ; Untyped ; +; L0_INITIAL ; 1 ; Untyped ; +; L1_INITIAL ; 1 ; Untyped ; +; G0_INITIAL ; 1 ; Untyped ; +; G1_INITIAL ; 1 ; Untyped ; +; G2_INITIAL ; 1 ; Untyped ; +; G3_INITIAL ; 1 ; Untyped ; +; E0_INITIAL ; 1 ; Untyped ; +; E1_INITIAL ; 1 ; Untyped ; +; E2_INITIAL ; 1 ; Untyped ; +; E3_INITIAL ; 1 ; Untyped ; +; L0_MODE ; BYPASS ; Untyped ; +; L1_MODE ; BYPASS ; Untyped ; +; G0_MODE ; BYPASS ; Untyped ; +; G1_MODE ; BYPASS ; Untyped ; +; G2_MODE ; BYPASS ; Untyped ; +; G3_MODE ; BYPASS ; Untyped ; +; E0_MODE ; BYPASS ; Untyped ; +; E1_MODE ; BYPASS ; Untyped ; +; E2_MODE ; BYPASS ; Untyped ; +; E3_MODE ; BYPASS ; Untyped ; +; L0_PH ; 0 ; Untyped ; +; L1_PH ; 0 ; Untyped ; +; G0_PH ; 0 ; Untyped ; +; G1_PH ; 0 ; Untyped ; +; G2_PH ; 0 ; Untyped ; +; G3_PH ; 0 ; Untyped ; +; E0_PH ; 0 ; Untyped ; +; E1_PH ; 0 ; Untyped ; +; E2_PH ; 0 ; Untyped ; +; E3_PH ; 0 ; Untyped ; +; M_PH ; 0 ; Untyped ; +; C1_USE_CASC_IN ; OFF ; Untyped ; +; C2_USE_CASC_IN ; OFF ; Untyped ; +; C3_USE_CASC_IN ; OFF ; Untyped ; +; C4_USE_CASC_IN ; OFF ; Untyped ; +; C5_USE_CASC_IN ; OFF ; Untyped ; +; C6_USE_CASC_IN ; OFF ; Untyped ; +; C7_USE_CASC_IN ; OFF ; Untyped ; +; C8_USE_CASC_IN ; OFF ; Untyped ; +; C9_USE_CASC_IN ; OFF ; Untyped ; +; CLK0_COUNTER ; G0 ; Untyped ; +; CLK1_COUNTER ; G0 ; Untyped ; +; CLK2_COUNTER ; G0 ; Untyped ; +; CLK3_COUNTER ; G0 ; Untyped ; +; CLK4_COUNTER ; G0 ; Untyped ; +; CLK5_COUNTER ; G0 ; Untyped ; +; CLK6_COUNTER ; E0 ; Untyped ; +; CLK7_COUNTER ; E1 ; Untyped ; +; CLK8_COUNTER ; E2 ; Untyped ; +; CLK9_COUNTER ; E3 ; Untyped ; +; L0_TIME_DELAY ; 0 ; Untyped ; +; L1_TIME_DELAY ; 0 ; Untyped ; +; G0_TIME_DELAY ; 0 ; Untyped ; +; G1_TIME_DELAY ; 0 ; Untyped ; +; G2_TIME_DELAY ; 0 ; Untyped ; +; G3_TIME_DELAY ; 0 ; Untyped ; +; E0_TIME_DELAY ; 0 ; Untyped ; +; E1_TIME_DELAY ; 0 ; Untyped ; +; E2_TIME_DELAY ; 0 ; Untyped ; +; E3_TIME_DELAY ; 0 ; Untyped ; +; M_TIME_DELAY ; 0 ; Untyped ; +; N_TIME_DELAY ; 0 ; Untyped ; +; EXTCLK3_COUNTER ; E3 ; Untyped ; +; EXTCLK2_COUNTER ; E2 ; Untyped ; +; EXTCLK1_COUNTER ; E1 ; Untyped ; +; EXTCLK0_COUNTER ; E0 ; Untyped ; +; ENABLE0_COUNTER ; L0 ; Untyped ; +; ENABLE1_COUNTER ; L0 ; Untyped ; +; CHARGE_PUMP_CURRENT ; 2 ; Untyped ; +; LOOP_FILTER_R ; 1.000000 ; Untyped ; +; LOOP_FILTER_C ; 5 ; Untyped ; +; CHARGE_PUMP_CURRENT_BITS ; 9999 ; Untyped ; +; LOOP_FILTER_R_BITS ; 9999 ; Untyped ; +; LOOP_FILTER_C_BITS ; 9999 ; Untyped ; +; VCO_POST_SCALE ; 0 ; Untyped ; +; CLK2_OUTPUT_FREQUENCY ; 0 ; Untyped ; +; CLK1_OUTPUT_FREQUENCY ; 0 ; Untyped ; +; CLK0_OUTPUT_FREQUENCY ; 0 ; Untyped ; +; INTENDED_DEVICE_FAMILY ; Cyclone IV E ; Untyped ; +; PORT_CLKENA0 ; PORT_UNUSED ; Untyped ; +; PORT_CLKENA1 ; PORT_UNUSED ; Untyped ; +; PORT_CLKENA2 ; PORT_UNUSED ; Untyped ; +; PORT_CLKENA3 ; PORT_UNUSED ; Untyped ; +; PORT_CLKENA4 ; PORT_UNUSED ; Untyped ; +; PORT_CLKENA5 ; PORT_UNUSED ; Untyped ; +; PORT_EXTCLKENA0 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_EXTCLKENA1 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_EXTCLKENA2 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_EXTCLKENA3 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_EXTCLK0 ; PORT_UNUSED ; Untyped ; +; PORT_EXTCLK1 ; PORT_UNUSED ; Untyped ; +; PORT_EXTCLK2 ; PORT_UNUSED ; Untyped ; +; PORT_EXTCLK3 ; PORT_UNUSED ; Untyped ; +; PORT_CLKBAD0 ; PORT_UNUSED ; Untyped ; +; PORT_CLKBAD1 ; PORT_UNUSED ; Untyped ; +; PORT_CLK0 ; PORT_USED ; Untyped ; +; PORT_CLK1 ; PORT_USED ; Untyped ; +; PORT_CLK2 ; PORT_USED ; Untyped ; +; PORT_CLK3 ; PORT_UNUSED ; Untyped ; +; PORT_CLK4 ; PORT_UNUSED ; Untyped ; +; PORT_CLK5 ; PORT_UNUSED ; Untyped ; +; PORT_CLK6 ; PORT_UNUSED ; Untyped ; +; PORT_CLK7 ; PORT_UNUSED ; Untyped ; +; PORT_CLK8 ; PORT_UNUSED ; Untyped ; +; PORT_CLK9 ; PORT_UNUSED ; Untyped ; +; PORT_SCANDATA ; PORT_UNUSED ; Untyped ; +; PORT_SCANDATAOUT ; PORT_UNUSED ; Untyped ; +; PORT_SCANDONE ; PORT_UNUSED ; Untyped ; +; PORT_SCLKOUT1 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_SCLKOUT0 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_ACTIVECLOCK ; PORT_UNUSED ; Untyped ; +; PORT_CLKLOSS ; PORT_UNUSED ; Untyped ; +; PORT_INCLK1 ; PORT_UNUSED ; Untyped ; +; PORT_INCLK0 ; PORT_USED ; Untyped ; +; PORT_FBIN ; PORT_UNUSED ; Untyped ; +; PORT_PLLENA ; PORT_UNUSED ; Untyped ; +; PORT_CLKSWITCH ; PORT_UNUSED ; Untyped ; +; PORT_ARESET ; PORT_UNUSED ; Untyped ; +; PORT_PFDENA ; PORT_UNUSED ; Untyped ; +; PORT_SCANCLK ; PORT_UNUSED ; Untyped ; +; PORT_SCANACLR ; PORT_UNUSED ; Untyped ; +; PORT_SCANREAD ; PORT_UNUSED ; Untyped ; +; PORT_SCANWRITE ; PORT_UNUSED ; Untyped ; +; PORT_ENABLE0 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_ENABLE1 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_LOCKED ; PORT_USED ; Untyped ; +; PORT_CONFIGUPDATE ; PORT_UNUSED ; Untyped ; +; PORT_FBOUT ; PORT_CONNECTIVITY ; Untyped ; +; PORT_PHASEDONE ; PORT_UNUSED ; Untyped ; +; PORT_PHASESTEP ; PORT_UNUSED ; Untyped ; +; PORT_PHASEUPDOWN ; PORT_UNUSED ; Untyped ; +; PORT_SCANCLKENA ; PORT_UNUSED ; Untyped ; +; PORT_PHASECOUNTERSELECT ; PORT_UNUSED ; Untyped ; +; PORT_VCOOVERRANGE ; PORT_CONNECTIVITY ; Untyped ; +; PORT_VCOUNDERRANGE ; PORT_CONNECTIVITY ; Untyped ; +; M_TEST_SOURCE ; 5 ; Untyped ; +; C0_TEST_SOURCE ; 5 ; Untyped ; +; C1_TEST_SOURCE ; 5 ; Untyped ; +; C2_TEST_SOURCE ; 5 ; Untyped ; +; C3_TEST_SOURCE ; 5 ; Untyped ; +; C4_TEST_SOURCE ; 5 ; Untyped ; +; C5_TEST_SOURCE ; 5 ; Untyped ; +; C6_TEST_SOURCE ; 5 ; Untyped ; +; C7_TEST_SOURCE ; 5 ; Untyped ; +; C8_TEST_SOURCE ; 5 ; Untyped ; +; C9_TEST_SOURCE ; 5 ; Untyped ; +; CBXI_PARAMETER ; pll_sys_altpll ; Untyped ; +; VCO_FREQUENCY_CONTROL ; AUTO ; Untyped ; +; VCO_PHASE_SHIFT_STEP ; 0 ; Untyped ; +; WIDTH_CLOCK ; 5 ; Signed Integer ; +; WIDTH_PHASECOUNTERSELECT ; 4 ; Untyped ; +; USING_FBMIMICBIDIR_PORT ; OFF ; Untyped ; +; DEVICE_FAMILY ; Cyclone IV E ; Untyped ; +; SCAN_CHAIN_MIF_FILE ; UNUSED ; Untyped ; +; SIM_GATE_LOCK_DEVICE_BEHAVIOR ; OFF ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++-------------------------------+---------------------------+-------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: system:inst_cpu|system_uart_0:uart_0|system_uart_0_rx:the_system_uart_0_rx|altera_std_synchronizer:the_altera_std_synchronizer ; ++----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------+ +; depth ; 2 ; Signed Integer ; ++----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo ; ++-------------------------+--------------+-----------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++-------------------------+--------------+-----------------------------------------------------------------------------------------------------------------------------+ +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; lpm_width ; 8 ; Signed Integer ; +; LPM_NUMWORDS ; 64 ; Signed Integer ; +; LPM_WIDTHU ; 6 ; Signed Integer ; +; LPM_SHOWAHEAD ; OFF ; Untyped ; +; UNDERFLOW_CHECKING ; OFF ; Untyped ; +; OVERFLOW_CHECKING ; OFF ; Untyped ; +; ALLOW_RWCYCLE_WHEN_FULL ; OFF ; Untyped ; +; ADD_RAM_OUTPUT_REGISTER ; OFF ; Untyped ; +; ALMOST_FULL_VALUE ; 0 ; Untyped ; +; ALMOST_EMPTY_VALUE ; 0 ; Untyped ; +; USE_EAB ; ON ; Untyped ; +; MAXIMIZE_SPEED ; 5 ; Untyped ; +; DEVICE_FAMILY ; Cyclone IV E ; Untyped ; +; OPTIMIZE_FOR_SPEED ; 5 ; Untyped ; +; CBXI_PARAMETER ; scfifo_jr21 ; Untyped ; ++-------------------------+--------------+-----------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo ; ++-------------------------+--------------+-----------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++-------------------------+--------------+-----------------------------------------------------------------------------------------------------------------------------+ +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; lpm_width ; 8 ; Signed Integer ; +; LPM_NUMWORDS ; 64 ; Signed Integer ; +; LPM_WIDTHU ; 6 ; Signed Integer ; +; LPM_SHOWAHEAD ; OFF ; Untyped ; +; UNDERFLOW_CHECKING ; OFF ; Untyped ; +; OVERFLOW_CHECKING ; OFF ; Untyped ; +; ALLOW_RWCYCLE_WHEN_FULL ; OFF ; Untyped ; +; ADD_RAM_OUTPUT_REGISTER ; OFF ; Untyped ; +; ALMOST_FULL_VALUE ; 0 ; Untyped ; +; ALMOST_EMPTY_VALUE ; 0 ; Untyped ; +; USE_EAB ; ON ; Untyped ; +; MAXIMIZE_SPEED ; 5 ; Untyped ; +; DEVICE_FAMILY ; Cyclone IV E ; Untyped ; +; OPTIMIZE_FOR_SPEED ; 5 ; Untyped ; +; CBXI_PARAMETER ; scfifo_jr21 ; Untyped ; ++-------------------------+--------------+-----------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: system:inst_cpu|system_rs232_motor:rs232_motor ; ++----------------------+-------+--------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------------+-------+--------------------------------------------------------------+ +; CW ; 14 ; Signed Integer ; +; BAUD_TICK_COUNT ; 10416 ; Signed Integer ; +; HALF_BAUD_TICK_COUNT ; 5208 ; Signed Integer ; +; TDW ; 10 ; Signed Integer ; +; DW ; 8 ; Signed Integer ; +; ODD_PARITY ; 0 ; Unsigned Binary ; ++----------------------+-------+--------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer ; ++----------------------+-------+--------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------------+-------+--------------------------------------------------------------------------------------------------------------------+ +; CW ; 14 ; Signed Integer ; +; BAUD_TICK_COUNT ; 10416 ; Signed Integer ; +; HALF_BAUD_TICK_COUNT ; 5208 ; Signed Integer ; +; TDW ; 10 ; Signed Integer ; +; DW ; 7 ; Signed Integer ; ++----------------------+-------+--------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_rs232_counters:RS232_In_Counters ; ++----------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; CW ; 14 ; Signed Integer ; +; BAUD_TICK_COUNT ; 10416 ; Signed Integer ; +; HALF_BAUD_TICK_COUNT ; 5208 ; Signed Integer ; +; TDW ; 10 ; Signed Integer ; ++----------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO ; ++----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; DW ; 7 ; Signed Integer ; +; DATA_DEPTH ; 128 ; Signed Integer ; +; AW ; 6 ; Signed Integer ; ++----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO ; ++-------------------------+--------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++-------------------------+--------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; lpm_width ; 8 ; Signed Integer ; +; LPM_NUMWORDS ; 128 ; Signed Integer ; +; LPM_WIDTHU ; 7 ; Signed Integer ; +; LPM_SHOWAHEAD ; ON ; Untyped ; +; UNDERFLOW_CHECKING ; OFF ; Untyped ; +; OVERFLOW_CHECKING ; OFF ; Untyped ; +; ALLOW_RWCYCLE_WHEN_FULL ; OFF ; Untyped ; +; ADD_RAM_OUTPUT_REGISTER ; OFF ; Untyped ; +; ALMOST_FULL_VALUE ; 0 ; Untyped ; +; ALMOST_EMPTY_VALUE ; 0 ; Untyped ; +; USE_EAB ; ON ; Untyped ; +; MAXIMIZE_SPEED ; 5 ; Untyped ; +; DEVICE_FAMILY ; Cyclone IV E ; Untyped ; +; OPTIMIZE_FOR_SPEED ; 5 ; Untyped ; +; CBXI_PARAMETER ; scfifo_a341 ; Untyped ; ++-------------------------+--------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer ; ++----------------------+-------+------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------------+-------+------------------------------------------------------------------------------------------------------------------+ +; CW ; 14 ; Signed Integer ; +; BAUD_TICK_COUNT ; 10416 ; Signed Integer ; +; HALF_BAUD_TICK_COUNT ; 5208 ; Signed Integer ; +; TDW ; 10 ; Signed Integer ; +; DW ; 7 ; Signed Integer ; ++----------------------+-------+------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_rs232_counters:RS232_Out_Counters ; ++----------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; CW ; 14 ; Signed Integer ; +; BAUD_TICK_COUNT ; 10416 ; Signed Integer ; +; HALF_BAUD_TICK_COUNT ; 5208 ; Signed Integer ; +; TDW ; 10 ; Signed Integer ; ++----------------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO ; ++----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+ +; DW ; 7 ; Signed Integer ; +; DATA_DEPTH ; 128 ; Signed Integer ; +; AW ; 6 ; Signed Integer ; ++----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO ; ++-------------------------+--------------+------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++-------------------------+--------------+------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; lpm_width ; 8 ; Signed Integer ; +; LPM_NUMWORDS ; 128 ; Signed Integer ; +; LPM_WIDTHU ; 7 ; Signed Integer ; +; LPM_SHOWAHEAD ; ON ; Untyped ; +; UNDERFLOW_CHECKING ; OFF ; Untyped ; +; OVERFLOW_CHECKING ; OFF ; Untyped ; +; ALLOW_RWCYCLE_WHEN_FULL ; OFF ; Untyped ; +; ADD_RAM_OUTPUT_REGISTER ; OFF ; Untyped ; +; ALMOST_FULL_VALUE ; 0 ; Untyped ; +; ALMOST_EMPTY_VALUE ; 0 ; Untyped ; +; USE_EAB ; ON ; Untyped ; +; MAXIMIZE_SPEED ; 5 ; Untyped ; +; DEVICE_FAMILY ; Cyclone IV E ; Untyped ; +; OPTIMIZE_FOR_SPEED ; 5 ; Untyped ; +; CBXI_PARAMETER ; scfifo_a341 ; Untyped ; ++-------------------------+--------------+------------------------------------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: system:inst_cpu|altera_merlin_master_translator:cpu_instruction_master_translator ; ++-----------------------------+-------+------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++-----------------------------+-------+------------------------------------------------------------------------------------------+ +; AV_ADDRESS_W ; 26 ; Signed Integer ; +; AV_DATA_W ; 32 ; Signed Integer ; +; AV_BURSTCOUNT_W ; 1 ; Signed Integer ; +; AV_BYTEENABLE_W ; 4 ; Signed Integer ; +; USE_BURSTCOUNT ; 0 ; Signed Integer ; +; USE_BEGINBURSTTRANSFER ; 0 ; Signed Integer ; +; USE_BEGINTRANSFER ; 0 ; Signed Integer ; +; USE_CHIPSELECT ; 0 ; Signed Integer ; +; USE_READ ; 1 ; Signed Integer ; +; USE_READDATAVALID ; 1 ; Signed Integer ; +; USE_WRITE ; 0 ; Signed Integer ; +; USE_WAITREQUEST ; 1 ; Signed Integer ; +; AV_REGISTERINCOMINGSIGNALS ; 0 ; Signed Integer ; +; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ; +; AV_ADDRESS_SYMBOLS ; 1 ; Signed Integer ; +; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; +; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ; +; AV_LINEWRAPBURSTS ; 1 ; Signed Integer ; +; UAV_ADDRESS_W ; 26 ; Signed Integer ; +; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ; +; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; ++-----------------------------+-------+------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: system:inst_cpu|altera_merlin_master_translator:cpu_data_master_translator ; ++-----------------------------+-------+-----------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++-----------------------------+-------+-----------------------------------------------------------------------------------+ +; AV_ADDRESS_W ; 26 ; Signed Integer ; +; AV_DATA_W ; 32 ; Signed Integer ; +; AV_BURSTCOUNT_W ; 1 ; Signed Integer ; +; AV_BYTEENABLE_W ; 4 ; Signed Integer ; +; USE_BURSTCOUNT ; 0 ; Signed Integer ; +; USE_BEGINBURSTTRANSFER ; 0 ; Signed Integer ; +; USE_BEGINTRANSFER ; 0 ; Signed Integer ; +; USE_CHIPSELECT ; 0 ; Signed Integer ; +; USE_READ ; 1 ; Signed Integer ; +; USE_READDATAVALID ; 1 ; Signed Integer ; +; USE_WRITE ; 1 ; Signed Integer ; +; USE_WAITREQUEST ; 1 ; Signed Integer ; +; AV_REGISTERINCOMINGSIGNALS ; 0 ; Signed Integer ; +; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ; +; AV_ADDRESS_SYMBOLS ; 1 ; Signed Integer ; +; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; +; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ; +; AV_LINEWRAPBURSTS ; 0 ; Signed Integer ; +; UAV_ADDRESS_W ; 26 ; Signed Integer ; +; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ; +; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; ++-----------------------------+-------+-----------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: system:inst_cpu|altera_merlin_slave_translator:cpu_jtag_debug_module_translator ; ++--------------------------------+-------+-------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++--------------------------------+-------+-------------------------------------------------------------------------------------+ +; AV_ADDRESS_W ; 9 ; Signed Integer ; +; AV_DATA_W ; 32 ; Signed Integer ; +; AV_BURSTCOUNT_W ; 1 ; Signed Integer ; +; AV_BYTEENABLE_W ; 4 ; Signed Integer ; +; UAV_BYTEENABLE_W ; 4 ; Signed Integer ; +; AV_READLATENCY ; 0 ; Signed Integer ; +; AV_READ_WAIT_CYCLES ; 1 ; Signed Integer ; +; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ; +; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ; +; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ; +; USE_READDATAVALID ; 0 ; Signed Integer ; +; USE_WAITREQUEST ; 0 ; Signed Integer ; +; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ; +; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ; +; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ; +; BITS_PER_WORD ; 2 ; Signed Integer ; +; UAV_ADDRESS_W ; 26 ; Signed Integer ; +; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ; +; UAV_DATA_W ; 32 ; Signed Integer ; +; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; +; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; +; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ; +; USE_UAV_CLKEN ; 0 ; Signed Integer ; +; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ; ++--------------------------------+-------+-------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-----------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: system:inst_cpu|altera_merlin_slave_translator:sdram_s1_translator ; ++--------------------------------+-------+------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++--------------------------------+-------+------------------------------------------------------------------------+ +; AV_ADDRESS_W ; 23 ; Signed Integer ; +; AV_DATA_W ; 16 ; Signed Integer ; +; AV_BURSTCOUNT_W ; 1 ; Signed Integer ; +; AV_BYTEENABLE_W ; 2 ; Signed Integer ; +; UAV_BYTEENABLE_W ; 2 ; Signed Integer ; +; AV_READLATENCY ; 0 ; Signed Integer ; +; AV_READ_WAIT_CYCLES ; 1 ; Signed Integer ; +; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ; +; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ; +; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ; +; USE_READDATAVALID ; 1 ; Signed Integer ; +; USE_WAITREQUEST ; 1 ; Signed Integer ; +; AV_SYMBOLS_PER_WORD ; 2 ; Signed Integer ; +; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ; +; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ; +; BITS_PER_WORD ; 1 ; Signed Integer ; +; UAV_ADDRESS_W ; 26 ; Signed Integer ; +; UAV_BURSTCOUNT_W ; 2 ; Signed Integer ; +; UAV_DATA_W ; 16 ; Signed Integer ; +; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; +; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; +; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ; +; USE_UAV_CLKEN ; 0 ; Signed Integer ; +; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ; ++--------------------------------+-------+------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++----------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: system:inst_cpu|altera_merlin_slave_translator:sysid_control_slave_translator ; ++--------------------------------+-------+-----------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++--------------------------------+-------+-----------------------------------------------------------------------------------+ +; AV_ADDRESS_W ; 1 ; Signed Integer ; +; AV_DATA_W ; 32 ; Signed Integer ; +; AV_BURSTCOUNT_W ; 1 ; Signed Integer ; +; AV_BYTEENABLE_W ; 4 ; Signed Integer ; +; UAV_BYTEENABLE_W ; 4 ; Signed Integer ; +; AV_READLATENCY ; 0 ; Signed Integer ; +; AV_READ_WAIT_CYCLES ; 1 ; Signed Integer ; +; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ; +; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ; +; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ; +; USE_READDATAVALID ; 0 ; Signed Integer ; +; USE_WAITREQUEST ; 0 ; Signed Integer ; +; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ; +; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ; +; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ; +; BITS_PER_WORD ; 2 ; Signed Integer ; +; UAV_ADDRESS_W ; 26 ; Signed Integer ; +; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ; +; UAV_DATA_W ; 32 ; Signed Integer ; +; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; +; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; +; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ; +; USE_UAV_CLKEN ; 0 ; Signed Integer ; +; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ; ++--------------------------------+-------+-----------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: system:inst_cpu|altera_merlin_slave_translator:sys_clk_timer_s1_translator ; ++--------------------------------+-------+--------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++--------------------------------+-------+--------------------------------------------------------------------------------+ +; AV_ADDRESS_W ; 3 ; Signed Integer ; +; AV_DATA_W ; 16 ; Signed Integer ; +; AV_BURSTCOUNT_W ; 1 ; Signed Integer ; +; AV_BYTEENABLE_W ; 1 ; Signed Integer ; +; UAV_BYTEENABLE_W ; 4 ; Signed Integer ; +; AV_READLATENCY ; 0 ; Signed Integer ; +; AV_READ_WAIT_CYCLES ; 1 ; Signed Integer ; +; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ; +; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ; +; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ; +; USE_READDATAVALID ; 0 ; Signed Integer ; +; USE_WAITREQUEST ; 0 ; Signed Integer ; +; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ; +; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ; +; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ; +; BITS_PER_WORD ; 2 ; Signed Integer ; +; UAV_ADDRESS_W ; 26 ; Signed Integer ; +; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ; +; UAV_DATA_W ; 32 ; Signed Integer ; +; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; +; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; +; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ; +; USE_UAV_CLKEN ; 0 ; Signed Integer ; +; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ; ++--------------------------------+-------+--------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: system:inst_cpu|altera_merlin_slave_translator:uart_0_s1_translator ; ++--------------------------------+-------+-------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++--------------------------------+-------+-------------------------------------------------------------------------+ +; AV_ADDRESS_W ; 3 ; Signed Integer ; +; AV_DATA_W ; 16 ; Signed Integer ; +; AV_BURSTCOUNT_W ; 1 ; Signed Integer ; +; AV_BYTEENABLE_W ; 1 ; Signed Integer ; +; UAV_BYTEENABLE_W ; 4 ; Signed Integer ; +; AV_READLATENCY ; 0 ; Signed Integer ; +; AV_READ_WAIT_CYCLES ; 1 ; Signed Integer ; +; AV_WRITE_WAIT_CYCLES ; 1 ; Signed Integer ; +; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ; +; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ; +; USE_READDATAVALID ; 0 ; Signed Integer ; +; USE_WAITREQUEST ; 0 ; Signed Integer ; +; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ; +; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ; +; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ; +; BITS_PER_WORD ; 2 ; Signed Integer ; +; UAV_ADDRESS_W ; 26 ; Signed Integer ; +; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ; +; UAV_DATA_W ; 32 ; Signed Integer ; +; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; +; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; +; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ; +; USE_UAV_CLKEN ; 0 ; Signed Integer ; +; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ; ++--------------------------------+-------+-------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: system:inst_cpu|altera_merlin_slave_translator:pio_led_s1_translator ; ++--------------------------------+-------+--------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++--------------------------------+-------+--------------------------------------------------------------------------+ +; AV_ADDRESS_W ; 3 ; Signed Integer ; +; AV_DATA_W ; 32 ; Signed Integer ; +; AV_BURSTCOUNT_W ; 1 ; Signed Integer ; +; AV_BYTEENABLE_W ; 1 ; Signed Integer ; +; UAV_BYTEENABLE_W ; 4 ; Signed Integer ; +; AV_READLATENCY ; 0 ; Signed Integer ; +; AV_READ_WAIT_CYCLES ; 1 ; Signed Integer ; +; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ; +; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ; +; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ; +; USE_READDATAVALID ; 0 ; Signed Integer ; +; USE_WAITREQUEST ; 0 ; Signed Integer ; +; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ; +; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ; +; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ; +; BITS_PER_WORD ; 2 ; Signed Integer ; +; UAV_ADDRESS_W ; 26 ; Signed Integer ; +; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ; +; UAV_DATA_W ; 32 ; Signed Integer ; +; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; +; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; +; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ; +; USE_UAV_CLKEN ; 0 ; Signed Integer ; +; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ; ++--------------------------------+-------+--------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: system:inst_cpu|altera_merlin_slave_translator:pio_key_s1_translator ; ++--------------------------------+-------+--------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++--------------------------------+-------+--------------------------------------------------------------------------+ +; AV_ADDRESS_W ; 2 ; Signed Integer ; +; AV_DATA_W ; 32 ; Signed Integer ; +; AV_BURSTCOUNT_W ; 1 ; Signed Integer ; +; AV_BYTEENABLE_W ; 1 ; Signed Integer ; +; UAV_BYTEENABLE_W ; 4 ; Signed Integer ; +; AV_READLATENCY ; 0 ; Signed Integer ; +; AV_READ_WAIT_CYCLES ; 1 ; Signed Integer ; +; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ; +; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ; +; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ; +; USE_READDATAVALID ; 0 ; Signed Integer ; +; USE_WAITREQUEST ; 0 ; Signed Integer ; +; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ; +; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ; +; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ; +; BITS_PER_WORD ; 2 ; Signed Integer ; +; UAV_ADDRESS_W ; 26 ; Signed Integer ; +; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ; +; UAV_DATA_W ; 32 ; Signed Integer ; +; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; +; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; +; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ; +; USE_UAV_CLKEN ; 0 ; Signed Integer ; +; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ; ++--------------------------------+-------+--------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: system:inst_cpu|altera_merlin_slave_translator:pio_sw_s1_translator ; ++--------------------------------+-------+-------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++--------------------------------+-------+-------------------------------------------------------------------------+ +; AV_ADDRESS_W ; 2 ; Signed Integer ; +; AV_DATA_W ; 32 ; Signed Integer ; +; AV_BURSTCOUNT_W ; 1 ; Signed Integer ; +; AV_BYTEENABLE_W ; 1 ; Signed Integer ; +; UAV_BYTEENABLE_W ; 4 ; Signed Integer ; +; AV_READLATENCY ; 0 ; Signed Integer ; +; AV_READ_WAIT_CYCLES ; 1 ; Signed Integer ; +; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ; +; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ; +; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ; +; USE_READDATAVALID ; 0 ; Signed Integer ; +; USE_WAITREQUEST ; 0 ; Signed Integer ; +; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ; +; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ; +; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ; +; BITS_PER_WORD ; 2 ; Signed Integer ; +; UAV_ADDRESS_W ; 26 ; Signed Integer ; +; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ; +; UAV_DATA_W ; 32 ; Signed Integer ; +; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; +; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; +; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ; +; USE_UAV_CLKEN ; 0 ; Signed Integer ; +; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ; ++--------------------------------+-------+-------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: system:inst_cpu|altera_merlin_slave_translator:jtag_uart_0_avalon_jtag_slave_translator ; ++--------------------------------+-------+---------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++--------------------------------+-------+---------------------------------------------------------------------------------------------+ +; AV_ADDRESS_W ; 1 ; Signed Integer ; +; AV_DATA_W ; 32 ; Signed Integer ; +; AV_BURSTCOUNT_W ; 1 ; Signed Integer ; +; AV_BYTEENABLE_W ; 1 ; Signed Integer ; +; UAV_BYTEENABLE_W ; 4 ; Signed Integer ; +; AV_READLATENCY ; 0 ; Signed Integer ; +; AV_READ_WAIT_CYCLES ; 1 ; Signed Integer ; +; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ; +; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ; +; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ; +; USE_READDATAVALID ; 0 ; Signed Integer ; +; USE_WAITREQUEST ; 1 ; Signed Integer ; +; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ; +; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ; +; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ; +; BITS_PER_WORD ; 2 ; Signed Integer ; +; UAV_ADDRESS_W ; 26 ; Signed Integer ; +; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ; +; UAV_DATA_W ; 32 ; Signed Integer ; +; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; +; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; +; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ; +; USE_UAV_CLKEN ; 0 ; Signed Integer ; +; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ; ++--------------------------------+-------+---------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: system:inst_cpu|altera_merlin_slave_translator:pio_motor_rst_s1_translator ; ++--------------------------------+-------+--------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++--------------------------------+-------+--------------------------------------------------------------------------------+ +; AV_ADDRESS_W ; 2 ; Signed Integer ; +; AV_DATA_W ; 32 ; Signed Integer ; +; AV_BURSTCOUNT_W ; 1 ; Signed Integer ; +; AV_BYTEENABLE_W ; 1 ; Signed Integer ; +; UAV_BYTEENABLE_W ; 4 ; Signed Integer ; +; AV_READLATENCY ; 0 ; Signed Integer ; +; AV_READ_WAIT_CYCLES ; 1 ; Signed Integer ; +; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ; +; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ; +; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ; +; USE_READDATAVALID ; 0 ; Signed Integer ; +; USE_WAITREQUEST ; 0 ; Signed Integer ; +; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ; +; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ; +; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ; +; BITS_PER_WORD ; 2 ; Signed Integer ; +; UAV_ADDRESS_W ; 26 ; Signed Integer ; +; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ; +; UAV_DATA_W ; 32 ; Signed Integer ; +; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; +; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; +; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ; +; USE_UAV_CLKEN ; 0 ; Signed Integer ; +; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ; ++--------------------------------+-------+--------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: system:inst_cpu|altera_merlin_slave_translator:rs232_motor_avalon_rs232_slave_translator ; ++--------------------------------+-------+----------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++--------------------------------+-------+----------------------------------------------------------------------------------------------+ +; AV_ADDRESS_W ; 1 ; Signed Integer ; +; AV_DATA_W ; 32 ; Signed Integer ; +; AV_BURSTCOUNT_W ; 1 ; Signed Integer ; +; AV_BYTEENABLE_W ; 4 ; Signed Integer ; +; UAV_BYTEENABLE_W ; 4 ; Signed Integer ; +; AV_READLATENCY ; 1 ; Signed Integer ; +; AV_READ_WAIT_CYCLES ; 0 ; Signed Integer ; +; AV_WRITE_WAIT_CYCLES ; 0 ; Signed Integer ; +; AV_SETUP_WAIT_CYCLES ; 0 ; Signed Integer ; +; AV_DATA_HOLD_CYCLES ; 0 ; Signed Integer ; +; USE_READDATAVALID ; 0 ; Signed Integer ; +; USE_WAITREQUEST ; 0 ; Signed Integer ; +; AV_SYMBOLS_PER_WORD ; 4 ; Signed Integer ; +; AV_ADDRESS_SYMBOLS ; 0 ; Signed Integer ; +; AV_BURSTCOUNT_SYMBOLS ; 0 ; Signed Integer ; +; BITS_PER_WORD ; 2 ; Signed Integer ; +; UAV_ADDRESS_W ; 26 ; Signed Integer ; +; UAV_BURSTCOUNT_W ; 3 ; Signed Integer ; +; UAV_DATA_W ; 32 ; Signed Integer ; +; AV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; +; UAV_CONSTANT_BURST_BEHAVIOR ; 0 ; Signed Integer ; +; CHIPSELECT_THROUGH_READLATENCY ; 0 ; Signed Integer ; +; USE_UAV_CLKEN ; 0 ; Signed Integer ; +; AV_REQUIRE_UNALIGNED_ADDRESSES ; 0 ; Signed Integer ; ++--------------------------------+-------+----------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: system:inst_cpu|altera_merlin_master_agent:cpu_instruction_master_translator_avalon_universal_master_0_agent ; ++---------------------------+-------+-----------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++---------------------------+-------+-----------------------------------------------------------------------------------------------------------------------+ +; PKT_QOS_H ; 82 ; Signed Integer ; +; PKT_QOS_L ; 82 ; Signed Integer ; +; PKT_DATA_SIDEBAND_H ; 80 ; Signed Integer ; +; PKT_DATA_SIDEBAND_L ; 80 ; Signed Integer ; +; PKT_ADDR_SIDEBAND_H ; 79 ; Signed Integer ; +; PKT_ADDR_SIDEBAND_L ; 79 ; Signed Integer ; +; PKT_CACHE_H ; 98 ; Signed Integer ; +; PKT_CACHE_L ; 95 ; Signed Integer ; +; PKT_THREAD_ID_H ; 91 ; Signed Integer ; +; PKT_THREAD_ID_L ; 91 ; Signed Integer ; +; PKT_BEGIN_BURST ; 81 ; Signed Integer ; +; PKT_PROTECTION_H ; 94 ; Signed Integer ; +; PKT_PROTECTION_L ; 92 ; Signed Integer ; +; PKT_BURSTWRAP_H ; 73 ; Signed Integer ; +; PKT_BURSTWRAP_L ; 71 ; Signed Integer ; +; PKT_BYTE_CNT_H ; 70 ; Signed Integer ; +; PKT_BYTE_CNT_L ; 68 ; Signed Integer ; +; PKT_ADDR_H ; 61 ; Signed Integer ; +; PKT_ADDR_L ; 36 ; Signed Integer ; +; PKT_BURST_SIZE_H ; 76 ; Signed Integer ; +; PKT_BURST_SIZE_L ; 74 ; Signed Integer ; +; PKT_BURST_TYPE_H ; 78 ; Signed Integer ; +; PKT_BURST_TYPE_L ; 77 ; Signed Integer ; +; PKT_TRANS_EXCLUSIVE ; 67 ; Signed Integer ; +; PKT_TRANS_LOCK ; 66 ; Signed Integer ; +; PKT_TRANS_COMPRESSED_READ ; 62 ; Signed Integer ; +; PKT_TRANS_POSTED ; 63 ; Signed Integer ; +; PKT_TRANS_WRITE ; 64 ; Signed Integer ; +; PKT_TRANS_READ ; 65 ; Signed Integer ; +; PKT_DATA_H ; 31 ; Signed Integer ; +; PKT_DATA_L ; 0 ; Signed Integer ; +; PKT_BYTEEN_H ; 35 ; Signed Integer ; +; PKT_BYTEEN_L ; 32 ; Signed Integer ; +; PKT_SRC_ID_H ; 86 ; Signed Integer ; +; PKT_SRC_ID_L ; 83 ; Signed Integer ; +; PKT_DEST_ID_H ; 90 ; Signed Integer ; +; PKT_DEST_ID_L ; 87 ; Signed Integer ; +; ST_DATA_W ; 101 ; Signed Integer ; +; ST_CHANNEL_W ; 11 ; Signed Integer ; +; AV_BURSTCOUNT_W ; 3 ; Signed Integer ; +; ID ; 0 ; Signed Integer ; +; SUPPRESS_0_BYTEEN_RSP ; 0 ; Signed Integer ; +; BURSTWRAP_VALUE ; 3 ; Signed Integer ; +; CACHE_VALUE ; 0000 ; Unsigned Binary ; +; PKT_BURSTWRAP_W ; 3 ; Signed Integer ; +; PKT_BYTE_CNT_W ; 3 ; Signed Integer ; +; PKT_ADDR_W ; 26 ; Signed Integer ; +; PKT_DATA_W ; 32 ; Signed Integer ; +; PKT_BYTEEN_W ; 4 ; Signed Integer ; +; PKT_SRC_ID_W ; 4 ; Signed Integer ; +; PKT_DEST_ID_W ; 4 ; Signed Integer ; ++---------------------------+-------+-----------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: system:inst_cpu|altera_merlin_master_agent:cpu_data_master_translator_avalon_universal_master_0_agent ; ++---------------------------+-------+----------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++---------------------------+-------+----------------------------------------------------------------------------------------------------------------+ +; PKT_QOS_H ; 82 ; Signed Integer ; +; PKT_QOS_L ; 82 ; Signed Integer ; +; PKT_DATA_SIDEBAND_H ; 80 ; Signed Integer ; +; PKT_DATA_SIDEBAND_L ; 80 ; Signed Integer ; +; PKT_ADDR_SIDEBAND_H ; 79 ; Signed Integer ; +; PKT_ADDR_SIDEBAND_L ; 79 ; Signed Integer ; +; PKT_CACHE_H ; 98 ; Signed Integer ; +; PKT_CACHE_L ; 95 ; Signed Integer ; +; PKT_THREAD_ID_H ; 91 ; Signed Integer ; +; PKT_THREAD_ID_L ; 91 ; Signed Integer ; +; PKT_BEGIN_BURST ; 81 ; Signed Integer ; +; PKT_PROTECTION_H ; 94 ; Signed Integer ; +; PKT_PROTECTION_L ; 92 ; Signed Integer ; +; PKT_BURSTWRAP_H ; 73 ; Signed Integer ; +; PKT_BURSTWRAP_L ; 71 ; Signed Integer ; +; PKT_BYTE_CNT_H ; 70 ; Signed Integer ; +; PKT_BYTE_CNT_L ; 68 ; Signed Integer ; +; PKT_ADDR_H ; 61 ; Signed Integer ; +; PKT_ADDR_L ; 36 ; Signed Integer ; +; PKT_BURST_SIZE_H ; 76 ; Signed Integer ; +; PKT_BURST_SIZE_L ; 74 ; Signed Integer ; +; PKT_BURST_TYPE_H ; 78 ; Signed Integer ; +; PKT_BURST_TYPE_L ; 77 ; Signed Integer ; +; PKT_TRANS_EXCLUSIVE ; 67 ; Signed Integer ; +; PKT_TRANS_LOCK ; 66 ; Signed Integer ; +; PKT_TRANS_COMPRESSED_READ ; 62 ; Signed Integer ; +; PKT_TRANS_POSTED ; 63 ; Signed Integer ; +; PKT_TRANS_WRITE ; 64 ; Signed Integer ; +; PKT_TRANS_READ ; 65 ; Signed Integer ; +; PKT_DATA_H ; 31 ; Signed Integer ; +; PKT_DATA_L ; 0 ; Signed Integer ; +; PKT_BYTEEN_H ; 35 ; Signed Integer ; +; PKT_BYTEEN_L ; 32 ; Signed Integer ; +; PKT_SRC_ID_H ; 86 ; Signed Integer ; +; PKT_SRC_ID_L ; 83 ; Signed Integer ; +; PKT_DEST_ID_H ; 90 ; Signed Integer ; +; PKT_DEST_ID_L ; 87 ; Signed Integer ; +; ST_DATA_W ; 101 ; Signed Integer ; +; ST_CHANNEL_W ; 11 ; Signed Integer ; +; AV_BURSTCOUNT_W ; 3 ; Signed Integer ; +; ID ; 1 ; Signed Integer ; +; SUPPRESS_0_BYTEEN_RSP ; 0 ; Signed Integer ; +; BURSTWRAP_VALUE ; 7 ; Signed Integer ; +; CACHE_VALUE ; 0000 ; Unsigned Binary ; +; PKT_BURSTWRAP_W ; 3 ; Signed Integer ; +; PKT_BYTE_CNT_W ; 3 ; Signed Integer ; +; PKT_ADDR_W ; 26 ; Signed Integer ; +; PKT_DATA_W ; 32 ; Signed Integer ; +; PKT_BYTEEN_W ; 4 ; Signed Integer ; +; PKT_SRC_ID_W ; 4 ; Signed Integer ; +; PKT_DEST_ID_W ; 4 ; Signed Integer ; ++---------------------------+-------+----------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: system:inst_cpu|altera_merlin_slave_agent:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent ; ++---------------------------+-------+--------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++---------------------------+-------+--------------------------------------------------------------------------------------------------------------------+ +; PKT_BEGIN_BURST ; 81 ; Signed Integer ; +; PKT_DATA_H ; 31 ; Signed Integer ; +; PKT_DATA_L ; 0 ; Signed Integer ; +; PKT_SYMBOL_W ; 8 ; Signed Integer ; +; PKT_BYTEEN_H ; 35 ; Signed Integer ; +; PKT_BYTEEN_L ; 32 ; Signed Integer ; +; PKT_ADDR_H ; 61 ; Signed Integer ; +; PKT_ADDR_L ; 36 ; Signed Integer ; +; PKT_TRANS_LOCK ; 66 ; Signed Integer ; +; PKT_TRANS_COMPRESSED_READ ; 62 ; Signed Integer ; +; PKT_TRANS_POSTED ; 63 ; Signed Integer ; +; PKT_TRANS_WRITE ; 64 ; Signed Integer ; +; PKT_TRANS_READ ; 65 ; Signed Integer ; +; PKT_SRC_ID_H ; 86 ; Signed Integer ; +; PKT_SRC_ID_L ; 83 ; Signed Integer ; +; PKT_DEST_ID_H ; 90 ; Signed Integer ; +; PKT_DEST_ID_L ; 87 ; Signed Integer ; +; PKT_BURSTWRAP_H ; 73 ; Signed Integer ; +; PKT_BURSTWRAP_L ; 71 ; Signed Integer ; +; PKT_BYTE_CNT_H ; 70 ; Signed Integer ; +; PKT_BYTE_CNT_L ; 68 ; Signed Integer ; +; PKT_PROTECTION_H ; 94 ; Signed Integer ; +; PKT_PROTECTION_L ; 92 ; Signed Integer ; +; PKT_RESPONSE_STATUS_H ; 100 ; Signed Integer ; +; PKT_RESPONSE_STATUS_L ; 99 ; Signed Integer ; +; PKT_BURST_SIZE_H ; 76 ; Signed Integer ; +; PKT_BURST_SIZE_L ; 74 ; Signed Integer ; +; ST_DATA_W ; 101 ; Signed Integer ; +; ST_CHANNEL_W ; 11 ; Signed Integer ; +; ADDR_W ; 26 ; Signed Integer ; +; AVS_DATA_W ; 32 ; Signed Integer ; +; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ; +; PKT_SYMBOLS ; 4 ; Signed Integer ; +; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ; +; SUPPRESS_0_BYTEEN_CMD ; 0 ; Signed Integer ; +; AVS_BE_W ; 4 ; Signed Integer ; +; BURST_SIZE_W ; 3 ; Signed Integer ; +; FIFO_DATA_W ; 102 ; Signed Integer ; ++---------------------------+-------+--------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: system:inst_cpu|altera_merlin_slave_agent:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor ; ++----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; ADDR_W ; 26 ; Signed Integer ; +; BURSTWRAP_W ; 3 ; Signed Integer ; +; BYTE_CNT_W ; 3 ; Signed Integer ; +; PKT_SYMBOLS ; 4 ; Signed Integer ; +; BURST_SIZE_W ; 3 ; Signed Integer ; ++----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: system:inst_cpu|altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo ; ++---------------------+-------+-------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++---------------------+-------+-------------------------------------------------------------------------------------------------------------------------------+ +; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; +; BITS_PER_SYMBOL ; 102 ; Signed Integer ; +; FIFO_DEPTH ; 2 ; Signed Integer ; +; CHANNEL_WIDTH ; 0 ; Signed Integer ; +; ERROR_WIDTH ; 0 ; Signed Integer ; +; USE_PACKETS ; 1 ; Signed Integer ; +; USE_FILL_LEVEL ; 0 ; Signed Integer ; +; USE_STORE_FORWARD ; 0 ; Signed Integer ; +; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ; +; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ; +; EMPTY_LATENCY ; 1 ; Signed Integer ; +; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ; +; DATA_WIDTH ; 102 ; Signed Integer ; +; EMPTY_WIDTH ; 0 ; Signed Integer ; ++---------------------+-------+-------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent ; ++---------------------------+-------+-------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++---------------------------+-------+-------------------------------------------------------------------------------------------------------+ +; PKT_BEGIN_BURST ; 63 ; Signed Integer ; +; PKT_DATA_H ; 15 ; Signed Integer ; +; PKT_DATA_L ; 0 ; Signed Integer ; +; PKT_SYMBOL_W ; 8 ; Signed Integer ; +; PKT_BYTEEN_H ; 17 ; Signed Integer ; +; PKT_BYTEEN_L ; 16 ; Signed Integer ; +; PKT_ADDR_H ; 43 ; Signed Integer ; +; PKT_ADDR_L ; 18 ; Signed Integer ; +; PKT_TRANS_LOCK ; 48 ; Signed Integer ; +; PKT_TRANS_COMPRESSED_READ ; 44 ; Signed Integer ; +; PKT_TRANS_POSTED ; 45 ; Signed Integer ; +; PKT_TRANS_WRITE ; 46 ; Signed Integer ; +; PKT_TRANS_READ ; 47 ; Signed Integer ; +; PKT_SRC_ID_H ; 68 ; Signed Integer ; +; PKT_SRC_ID_L ; 65 ; Signed Integer ; +; PKT_DEST_ID_H ; 72 ; Signed Integer ; +; PKT_DEST_ID_L ; 69 ; Signed Integer ; +; PKT_BURSTWRAP_H ; 55 ; Signed Integer ; +; PKT_BURSTWRAP_L ; 53 ; Signed Integer ; +; PKT_BYTE_CNT_H ; 52 ; Signed Integer ; +; PKT_BYTE_CNT_L ; 50 ; Signed Integer ; +; PKT_PROTECTION_H ; 76 ; Signed Integer ; +; PKT_PROTECTION_L ; 74 ; Signed Integer ; +; PKT_RESPONSE_STATUS_H ; 82 ; Signed Integer ; +; PKT_RESPONSE_STATUS_L ; 81 ; Signed Integer ; +; PKT_BURST_SIZE_H ; 58 ; Signed Integer ; +; PKT_BURST_SIZE_L ; 56 ; Signed Integer ; +; ST_DATA_W ; 83 ; Signed Integer ; +; ST_CHANNEL_W ; 11 ; Signed Integer ; +; ADDR_W ; 26 ; Signed Integer ; +; AVS_DATA_W ; 16 ; Signed Integer ; +; AVS_BURSTCOUNT_W ; 2 ; Signed Integer ; +; PKT_SYMBOLS ; 2 ; Signed Integer ; +; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ; +; SUPPRESS_0_BYTEEN_CMD ; 1 ; Signed Integer ; +; AVS_BE_W ; 2 ; Signed Integer ; +; BURST_SIZE_W ; 3 ; Signed Integer ; +; FIFO_DATA_W ; 84 ; Signed Integer ; ++---------------------------+-------+-------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor ; ++----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; ADDR_W ; 26 ; Signed Integer ; +; BURSTWRAP_W ; 3 ; Signed Integer ; +; BYTE_CNT_W ; 3 ; Signed Integer ; +; PKT_SYMBOLS ; 2 ; Signed Integer ; +; BURST_SIZE_W ; 3 ; Signed Integer ; ++----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; ++---------------------+-------+------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++---------------------+-------+------------------------------------------------------------------------------------------------------------------+ +; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; +; BITS_PER_SYMBOL ; 84 ; Signed Integer ; +; FIFO_DEPTH ; 8 ; Signed Integer ; +; CHANNEL_WIDTH ; 0 ; Signed Integer ; +; ERROR_WIDTH ; 0 ; Signed Integer ; +; USE_PACKETS ; 1 ; Signed Integer ; +; USE_FILL_LEVEL ; 0 ; Signed Integer ; +; USE_STORE_FORWARD ; 0 ; Signed Integer ; +; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ; +; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ; +; EMPTY_LATENCY ; 1 ; Signed Integer ; +; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ; +; DATA_WIDTH ; 84 ; Signed Integer ; +; EMPTY_WIDTH ; 0 ; Signed Integer ; ++---------------------+-------+------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: system:inst_cpu|altera_merlin_slave_agent:sysid_control_slave_translator_avalon_universal_slave_0_agent ; ++---------------------------+-------+------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++---------------------------+-------+------------------------------------------------------------------------------------------------------------------+ +; PKT_BEGIN_BURST ; 81 ; Signed Integer ; +; PKT_DATA_H ; 31 ; Signed Integer ; +; PKT_DATA_L ; 0 ; Signed Integer ; +; PKT_SYMBOL_W ; 8 ; Signed Integer ; +; PKT_BYTEEN_H ; 35 ; Signed Integer ; +; PKT_BYTEEN_L ; 32 ; Signed Integer ; +; PKT_ADDR_H ; 61 ; Signed Integer ; +; PKT_ADDR_L ; 36 ; Signed Integer ; +; PKT_TRANS_LOCK ; 66 ; Signed Integer ; +; PKT_TRANS_COMPRESSED_READ ; 62 ; Signed Integer ; +; PKT_TRANS_POSTED ; 63 ; Signed Integer ; +; PKT_TRANS_WRITE ; 64 ; Signed Integer ; +; PKT_TRANS_READ ; 65 ; Signed Integer ; +; PKT_SRC_ID_H ; 86 ; Signed Integer ; +; PKT_SRC_ID_L ; 83 ; Signed Integer ; +; PKT_DEST_ID_H ; 90 ; Signed Integer ; +; PKT_DEST_ID_L ; 87 ; Signed Integer ; +; PKT_BURSTWRAP_H ; 73 ; Signed Integer ; +; PKT_BURSTWRAP_L ; 71 ; Signed Integer ; +; PKT_BYTE_CNT_H ; 70 ; Signed Integer ; +; PKT_BYTE_CNT_L ; 68 ; Signed Integer ; +; PKT_PROTECTION_H ; 94 ; Signed Integer ; +; PKT_PROTECTION_L ; 92 ; Signed Integer ; +; PKT_RESPONSE_STATUS_H ; 100 ; Signed Integer ; +; PKT_RESPONSE_STATUS_L ; 99 ; Signed Integer ; +; PKT_BURST_SIZE_H ; 76 ; Signed Integer ; +; PKT_BURST_SIZE_L ; 74 ; Signed Integer ; +; ST_DATA_W ; 101 ; Signed Integer ; +; ST_CHANNEL_W ; 11 ; Signed Integer ; +; ADDR_W ; 26 ; Signed Integer ; +; AVS_DATA_W ; 32 ; Signed Integer ; +; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ; +; PKT_SYMBOLS ; 4 ; Signed Integer ; +; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ; +; SUPPRESS_0_BYTEEN_CMD ; 0 ; Signed Integer ; +; AVS_BE_W ; 4 ; Signed Integer ; +; BURST_SIZE_W ; 3 ; Signed Integer ; +; FIFO_DATA_W ; 102 ; Signed Integer ; ++---------------------------+-------+------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: system:inst_cpu|altera_merlin_slave_agent:sysid_control_slave_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor ; ++----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; ADDR_W ; 26 ; Signed Integer ; +; BURSTWRAP_W ; 3 ; Signed Integer ; +; BYTE_CNT_W ; 3 ; Signed Integer ; +; PKT_SYMBOLS ; 4 ; Signed Integer ; +; BURST_SIZE_W ; 3 ; Signed Integer ; ++----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: system:inst_cpu|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo ; ++---------------------+-------+-----------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++---------------------+-------+-----------------------------------------------------------------------------------------------------------------------------+ +; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; +; BITS_PER_SYMBOL ; 102 ; Signed Integer ; +; FIFO_DEPTH ; 2 ; Signed Integer ; +; CHANNEL_WIDTH ; 0 ; Signed Integer ; +; ERROR_WIDTH ; 0 ; Signed Integer ; +; USE_PACKETS ; 1 ; Signed Integer ; +; USE_FILL_LEVEL ; 0 ; Signed Integer ; +; USE_STORE_FORWARD ; 0 ; Signed Integer ; +; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ; +; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ; +; EMPTY_LATENCY ; 1 ; Signed Integer ; +; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ; +; DATA_WIDTH ; 102 ; Signed Integer ; +; EMPTY_WIDTH ; 0 ; Signed Integer ; ++---------------------+-------+-----------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: system:inst_cpu|altera_merlin_slave_agent:sys_clk_timer_s1_translator_avalon_universal_slave_0_agent ; ++---------------------------+-------+---------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++---------------------------+-------+---------------------------------------------------------------------------------------------------------------+ +; PKT_BEGIN_BURST ; 81 ; Signed Integer ; +; PKT_DATA_H ; 31 ; Signed Integer ; +; PKT_DATA_L ; 0 ; Signed Integer ; +; PKT_SYMBOL_W ; 8 ; Signed Integer ; +; PKT_BYTEEN_H ; 35 ; Signed Integer ; +; PKT_BYTEEN_L ; 32 ; Signed Integer ; +; PKT_ADDR_H ; 61 ; Signed Integer ; +; PKT_ADDR_L ; 36 ; Signed Integer ; +; PKT_TRANS_LOCK ; 66 ; Signed Integer ; +; PKT_TRANS_COMPRESSED_READ ; 62 ; Signed Integer ; +; PKT_TRANS_POSTED ; 63 ; Signed Integer ; +; PKT_TRANS_WRITE ; 64 ; Signed Integer ; +; PKT_TRANS_READ ; 65 ; Signed Integer ; +; PKT_SRC_ID_H ; 86 ; Signed Integer ; +; PKT_SRC_ID_L ; 83 ; Signed Integer ; +; PKT_DEST_ID_H ; 90 ; Signed Integer ; +; PKT_DEST_ID_L ; 87 ; Signed Integer ; +; PKT_BURSTWRAP_H ; 73 ; Signed Integer ; +; PKT_BURSTWRAP_L ; 71 ; Signed Integer ; +; PKT_BYTE_CNT_H ; 70 ; Signed Integer ; +; PKT_BYTE_CNT_L ; 68 ; Signed Integer ; +; PKT_PROTECTION_H ; 94 ; Signed Integer ; +; PKT_PROTECTION_L ; 92 ; Signed Integer ; +; PKT_RESPONSE_STATUS_H ; 100 ; Signed Integer ; +; PKT_RESPONSE_STATUS_L ; 99 ; Signed Integer ; +; PKT_BURST_SIZE_H ; 76 ; Signed Integer ; +; PKT_BURST_SIZE_L ; 74 ; Signed Integer ; +; ST_DATA_W ; 101 ; Signed Integer ; +; ST_CHANNEL_W ; 11 ; Signed Integer ; +; ADDR_W ; 26 ; Signed Integer ; +; AVS_DATA_W ; 32 ; Signed Integer ; +; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ; +; PKT_SYMBOLS ; 4 ; Signed Integer ; +; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ; +; SUPPRESS_0_BYTEEN_CMD ; 0 ; Signed Integer ; +; AVS_BE_W ; 4 ; Signed Integer ; +; BURST_SIZE_W ; 3 ; Signed Integer ; +; FIFO_DATA_W ; 102 ; Signed Integer ; ++---------------------------+-------+---------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: system:inst_cpu|altera_merlin_slave_agent:sys_clk_timer_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor ; ++----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; ADDR_W ; 26 ; Signed Integer ; +; BURSTWRAP_W ; 3 ; Signed Integer ; +; BYTE_CNT_W ; 3 ; Signed Integer ; +; PKT_SYMBOLS ; 4 ; Signed Integer ; +; BURST_SIZE_W ; 3 ; Signed Integer ; ++----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: system:inst_cpu|altera_avalon_sc_fifo:sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; ++---------------------+-------+--------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++---------------------+-------+--------------------------------------------------------------------------------------------------------------------------+ +; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; +; BITS_PER_SYMBOL ; 102 ; Signed Integer ; +; FIFO_DEPTH ; 2 ; Signed Integer ; +; CHANNEL_WIDTH ; 0 ; Signed Integer ; +; ERROR_WIDTH ; 0 ; Signed Integer ; +; USE_PACKETS ; 1 ; Signed Integer ; +; USE_FILL_LEVEL ; 0 ; Signed Integer ; +; USE_STORE_FORWARD ; 0 ; Signed Integer ; +; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ; +; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ; +; EMPTY_LATENCY ; 1 ; Signed Integer ; +; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ; +; DATA_WIDTH ; 102 ; Signed Integer ; +; EMPTY_WIDTH ; 0 ; Signed Integer ; ++---------------------+-------+--------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: system:inst_cpu|altera_merlin_slave_agent:uart_0_s1_translator_avalon_universal_slave_0_agent ; ++---------------------------+-------+--------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++---------------------------+-------+--------------------------------------------------------------------------------------------------------+ +; PKT_BEGIN_BURST ; 81 ; Signed Integer ; +; PKT_DATA_H ; 31 ; Signed Integer ; +; PKT_DATA_L ; 0 ; Signed Integer ; +; PKT_SYMBOL_W ; 8 ; Signed Integer ; +; PKT_BYTEEN_H ; 35 ; Signed Integer ; +; PKT_BYTEEN_L ; 32 ; Signed Integer ; +; PKT_ADDR_H ; 61 ; Signed Integer ; +; PKT_ADDR_L ; 36 ; Signed Integer ; +; PKT_TRANS_LOCK ; 66 ; Signed Integer ; +; PKT_TRANS_COMPRESSED_READ ; 62 ; Signed Integer ; +; PKT_TRANS_POSTED ; 63 ; Signed Integer ; +; PKT_TRANS_WRITE ; 64 ; Signed Integer ; +; PKT_TRANS_READ ; 65 ; Signed Integer ; +; PKT_SRC_ID_H ; 86 ; Signed Integer ; +; PKT_SRC_ID_L ; 83 ; Signed Integer ; +; PKT_DEST_ID_H ; 90 ; Signed Integer ; +; PKT_DEST_ID_L ; 87 ; Signed Integer ; +; PKT_BURSTWRAP_H ; 73 ; Signed Integer ; +; PKT_BURSTWRAP_L ; 71 ; Signed Integer ; +; PKT_BYTE_CNT_H ; 70 ; Signed Integer ; +; PKT_BYTE_CNT_L ; 68 ; Signed Integer ; +; PKT_PROTECTION_H ; 94 ; Signed Integer ; +; PKT_PROTECTION_L ; 92 ; Signed Integer ; +; PKT_RESPONSE_STATUS_H ; 100 ; Signed Integer ; +; PKT_RESPONSE_STATUS_L ; 99 ; Signed Integer ; +; PKT_BURST_SIZE_H ; 76 ; Signed Integer ; +; PKT_BURST_SIZE_L ; 74 ; Signed Integer ; +; ST_DATA_W ; 101 ; Signed Integer ; +; ST_CHANNEL_W ; 11 ; Signed Integer ; +; ADDR_W ; 26 ; Signed Integer ; +; AVS_DATA_W ; 32 ; Signed Integer ; +; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ; +; PKT_SYMBOLS ; 4 ; Signed Integer ; +; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ; +; SUPPRESS_0_BYTEEN_CMD ; 0 ; Signed Integer ; +; AVS_BE_W ; 4 ; Signed Integer ; +; BURST_SIZE_W ; 3 ; Signed Integer ; +; FIFO_DATA_W ; 102 ; Signed Integer ; ++---------------------------+-------+--------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: system:inst_cpu|altera_merlin_slave_agent:uart_0_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor ; ++----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; ADDR_W ; 26 ; Signed Integer ; +; BURSTWRAP_W ; 3 ; Signed Integer ; +; BYTE_CNT_W ; 3 ; Signed Integer ; +; PKT_SYMBOLS ; 4 ; Signed Integer ; +; BURST_SIZE_W ; 3 ; Signed Integer ; ++----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: system:inst_cpu|altera_avalon_sc_fifo:uart_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; ++---------------------+-------+-------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++---------------------+-------+-------------------------------------------------------------------------------------------------------------------+ +; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; +; BITS_PER_SYMBOL ; 102 ; Signed Integer ; +; FIFO_DEPTH ; 2 ; Signed Integer ; +; CHANNEL_WIDTH ; 0 ; Signed Integer ; +; ERROR_WIDTH ; 0 ; Signed Integer ; +; USE_PACKETS ; 1 ; Signed Integer ; +; USE_FILL_LEVEL ; 0 ; Signed Integer ; +; USE_STORE_FORWARD ; 0 ; Signed Integer ; +; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ; +; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ; +; EMPTY_LATENCY ; 1 ; Signed Integer ; +; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ; +; DATA_WIDTH ; 102 ; Signed Integer ; +; EMPTY_WIDTH ; 0 ; Signed Integer ; ++---------------------+-------+-------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: system:inst_cpu|altera_merlin_slave_agent:pio_led_s1_translator_avalon_universal_slave_0_agent ; ++---------------------------+-------+---------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++---------------------------+-------+---------------------------------------------------------------------------------------------------------+ +; PKT_BEGIN_BURST ; 81 ; Signed Integer ; +; PKT_DATA_H ; 31 ; Signed Integer ; +; PKT_DATA_L ; 0 ; Signed Integer ; +; PKT_SYMBOL_W ; 8 ; Signed Integer ; +; PKT_BYTEEN_H ; 35 ; Signed Integer ; +; PKT_BYTEEN_L ; 32 ; Signed Integer ; +; PKT_ADDR_H ; 61 ; Signed Integer ; +; PKT_ADDR_L ; 36 ; Signed Integer ; +; PKT_TRANS_LOCK ; 66 ; Signed Integer ; +; PKT_TRANS_COMPRESSED_READ ; 62 ; Signed Integer ; +; PKT_TRANS_POSTED ; 63 ; Signed Integer ; +; PKT_TRANS_WRITE ; 64 ; Signed Integer ; +; PKT_TRANS_READ ; 65 ; Signed Integer ; +; PKT_SRC_ID_H ; 86 ; Signed Integer ; +; PKT_SRC_ID_L ; 83 ; Signed Integer ; +; PKT_DEST_ID_H ; 90 ; Signed Integer ; +; PKT_DEST_ID_L ; 87 ; Signed Integer ; +; PKT_BURSTWRAP_H ; 73 ; Signed Integer ; +; PKT_BURSTWRAP_L ; 71 ; Signed Integer ; +; PKT_BYTE_CNT_H ; 70 ; Signed Integer ; +; PKT_BYTE_CNT_L ; 68 ; Signed Integer ; +; PKT_PROTECTION_H ; 94 ; Signed Integer ; +; PKT_PROTECTION_L ; 92 ; Signed Integer ; +; PKT_RESPONSE_STATUS_H ; 100 ; Signed Integer ; +; PKT_RESPONSE_STATUS_L ; 99 ; Signed Integer ; +; PKT_BURST_SIZE_H ; 76 ; Signed Integer ; +; PKT_BURST_SIZE_L ; 74 ; Signed Integer ; +; ST_DATA_W ; 101 ; Signed Integer ; +; ST_CHANNEL_W ; 11 ; Signed Integer ; +; ADDR_W ; 26 ; Signed Integer ; +; AVS_DATA_W ; 32 ; Signed Integer ; +; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ; +; PKT_SYMBOLS ; 4 ; Signed Integer ; +; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ; +; SUPPRESS_0_BYTEEN_CMD ; 0 ; Signed Integer ; +; AVS_BE_W ; 4 ; Signed Integer ; +; BURST_SIZE_W ; 3 ; Signed Integer ; +; FIFO_DATA_W ; 102 ; Signed Integer ; ++---------------------------+-------+---------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: system:inst_cpu|altera_merlin_slave_agent:pio_led_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor ; ++----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; ADDR_W ; 26 ; Signed Integer ; +; BURSTWRAP_W ; 3 ; Signed Integer ; +; BYTE_CNT_W ; 3 ; Signed Integer ; +; PKT_SYMBOLS ; 4 ; Signed Integer ; +; BURST_SIZE_W ; 3 ; Signed Integer ; ++----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: system:inst_cpu|altera_avalon_sc_fifo:pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; ++---------------------+-------+--------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++---------------------+-------+--------------------------------------------------------------------------------------------------------------------+ +; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; +; BITS_PER_SYMBOL ; 102 ; Signed Integer ; +; FIFO_DEPTH ; 2 ; Signed Integer ; +; CHANNEL_WIDTH ; 0 ; Signed Integer ; +; ERROR_WIDTH ; 0 ; Signed Integer ; +; USE_PACKETS ; 1 ; Signed Integer ; +; USE_FILL_LEVEL ; 0 ; Signed Integer ; +; USE_STORE_FORWARD ; 0 ; Signed Integer ; +; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ; +; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ; +; EMPTY_LATENCY ; 1 ; Signed Integer ; +; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ; +; DATA_WIDTH ; 102 ; Signed Integer ; +; EMPTY_WIDTH ; 0 ; Signed Integer ; ++---------------------+-------+--------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: system:inst_cpu|altera_merlin_slave_agent:pio_key_s1_translator_avalon_universal_slave_0_agent ; ++---------------------------+-------+---------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++---------------------------+-------+---------------------------------------------------------------------------------------------------------+ +; PKT_BEGIN_BURST ; 81 ; Signed Integer ; +; PKT_DATA_H ; 31 ; Signed Integer ; +; PKT_DATA_L ; 0 ; Signed Integer ; +; PKT_SYMBOL_W ; 8 ; Signed Integer ; +; PKT_BYTEEN_H ; 35 ; Signed Integer ; +; PKT_BYTEEN_L ; 32 ; Signed Integer ; +; PKT_ADDR_H ; 61 ; Signed Integer ; +; PKT_ADDR_L ; 36 ; Signed Integer ; +; PKT_TRANS_LOCK ; 66 ; Signed Integer ; +; PKT_TRANS_COMPRESSED_READ ; 62 ; Signed Integer ; +; PKT_TRANS_POSTED ; 63 ; Signed Integer ; +; PKT_TRANS_WRITE ; 64 ; Signed Integer ; +; PKT_TRANS_READ ; 65 ; Signed Integer ; +; PKT_SRC_ID_H ; 86 ; Signed Integer ; +; PKT_SRC_ID_L ; 83 ; Signed Integer ; +; PKT_DEST_ID_H ; 90 ; Signed Integer ; +; PKT_DEST_ID_L ; 87 ; Signed Integer ; +; PKT_BURSTWRAP_H ; 73 ; Signed Integer ; +; PKT_BURSTWRAP_L ; 71 ; Signed Integer ; +; PKT_BYTE_CNT_H ; 70 ; Signed Integer ; +; PKT_BYTE_CNT_L ; 68 ; Signed Integer ; +; PKT_PROTECTION_H ; 94 ; Signed Integer ; +; PKT_PROTECTION_L ; 92 ; Signed Integer ; +; PKT_RESPONSE_STATUS_H ; 100 ; Signed Integer ; +; PKT_RESPONSE_STATUS_L ; 99 ; Signed Integer ; +; PKT_BURST_SIZE_H ; 76 ; Signed Integer ; +; PKT_BURST_SIZE_L ; 74 ; Signed Integer ; +; ST_DATA_W ; 101 ; Signed Integer ; +; ST_CHANNEL_W ; 11 ; Signed Integer ; +; ADDR_W ; 26 ; Signed Integer ; +; AVS_DATA_W ; 32 ; Signed Integer ; +; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ; +; PKT_SYMBOLS ; 4 ; Signed Integer ; +; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ; +; SUPPRESS_0_BYTEEN_CMD ; 0 ; Signed Integer ; +; AVS_BE_W ; 4 ; Signed Integer ; +; BURST_SIZE_W ; 3 ; Signed Integer ; +; FIFO_DATA_W ; 102 ; Signed Integer ; ++---------------------------+-------+---------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: system:inst_cpu|altera_merlin_slave_agent:pio_key_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor ; ++----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; ADDR_W ; 26 ; Signed Integer ; +; BURSTWRAP_W ; 3 ; Signed Integer ; +; BYTE_CNT_W ; 3 ; Signed Integer ; +; PKT_SYMBOLS ; 4 ; Signed Integer ; +; BURST_SIZE_W ; 3 ; Signed Integer ; ++----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: system:inst_cpu|altera_avalon_sc_fifo:pio_key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; ++---------------------+-------+--------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++---------------------+-------+--------------------------------------------------------------------------------------------------------------------+ +; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; +; BITS_PER_SYMBOL ; 102 ; Signed Integer ; +; FIFO_DEPTH ; 2 ; Signed Integer ; +; CHANNEL_WIDTH ; 0 ; Signed Integer ; +; ERROR_WIDTH ; 0 ; Signed Integer ; +; USE_PACKETS ; 1 ; Signed Integer ; +; USE_FILL_LEVEL ; 0 ; Signed Integer ; +; USE_STORE_FORWARD ; 0 ; Signed Integer ; +; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ; +; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ; +; EMPTY_LATENCY ; 1 ; Signed Integer ; +; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ; +; DATA_WIDTH ; 102 ; Signed Integer ; +; EMPTY_WIDTH ; 0 ; Signed Integer ; ++---------------------+-------+--------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: system:inst_cpu|altera_merlin_slave_agent:pio_sw_s1_translator_avalon_universal_slave_0_agent ; ++---------------------------+-------+--------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++---------------------------+-------+--------------------------------------------------------------------------------------------------------+ +; PKT_BEGIN_BURST ; 81 ; Signed Integer ; +; PKT_DATA_H ; 31 ; Signed Integer ; +; PKT_DATA_L ; 0 ; Signed Integer ; +; PKT_SYMBOL_W ; 8 ; Signed Integer ; +; PKT_BYTEEN_H ; 35 ; Signed Integer ; +; PKT_BYTEEN_L ; 32 ; Signed Integer ; +; PKT_ADDR_H ; 61 ; Signed Integer ; +; PKT_ADDR_L ; 36 ; Signed Integer ; +; PKT_TRANS_LOCK ; 66 ; Signed Integer ; +; PKT_TRANS_COMPRESSED_READ ; 62 ; Signed Integer ; +; PKT_TRANS_POSTED ; 63 ; Signed Integer ; +; PKT_TRANS_WRITE ; 64 ; Signed Integer ; +; PKT_TRANS_READ ; 65 ; Signed Integer ; +; PKT_SRC_ID_H ; 86 ; Signed Integer ; +; PKT_SRC_ID_L ; 83 ; Signed Integer ; +; PKT_DEST_ID_H ; 90 ; Signed Integer ; +; PKT_DEST_ID_L ; 87 ; Signed Integer ; +; PKT_BURSTWRAP_H ; 73 ; Signed Integer ; +; PKT_BURSTWRAP_L ; 71 ; Signed Integer ; +; PKT_BYTE_CNT_H ; 70 ; Signed Integer ; +; PKT_BYTE_CNT_L ; 68 ; Signed Integer ; +; PKT_PROTECTION_H ; 94 ; Signed Integer ; +; PKT_PROTECTION_L ; 92 ; Signed Integer ; +; PKT_RESPONSE_STATUS_H ; 100 ; Signed Integer ; +; PKT_RESPONSE_STATUS_L ; 99 ; Signed Integer ; +; PKT_BURST_SIZE_H ; 76 ; Signed Integer ; +; PKT_BURST_SIZE_L ; 74 ; Signed Integer ; +; ST_DATA_W ; 101 ; Signed Integer ; +; ST_CHANNEL_W ; 11 ; Signed Integer ; +; ADDR_W ; 26 ; Signed Integer ; +; AVS_DATA_W ; 32 ; Signed Integer ; +; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ; +; PKT_SYMBOLS ; 4 ; Signed Integer ; +; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ; +; SUPPRESS_0_BYTEEN_CMD ; 0 ; Signed Integer ; +; AVS_BE_W ; 4 ; Signed Integer ; +; BURST_SIZE_W ; 3 ; Signed Integer ; +; FIFO_DATA_W ; 102 ; Signed Integer ; ++---------------------------+-------+--------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: system:inst_cpu|altera_merlin_slave_agent:pio_sw_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor ; ++----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; ADDR_W ; 26 ; Signed Integer ; +; BURSTWRAP_W ; 3 ; Signed Integer ; +; BYTE_CNT_W ; 3 ; Signed Integer ; +; PKT_SYMBOLS ; 4 ; Signed Integer ; +; BURST_SIZE_W ; 3 ; Signed Integer ; ++----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: system:inst_cpu|altera_avalon_sc_fifo:pio_sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; ++---------------------+-------+-------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++---------------------+-------+-------------------------------------------------------------------------------------------------------------------+ +; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; +; BITS_PER_SYMBOL ; 102 ; Signed Integer ; +; FIFO_DEPTH ; 2 ; Signed Integer ; +; CHANNEL_WIDTH ; 0 ; Signed Integer ; +; ERROR_WIDTH ; 0 ; Signed Integer ; +; USE_PACKETS ; 1 ; Signed Integer ; +; USE_FILL_LEVEL ; 0 ; Signed Integer ; +; USE_STORE_FORWARD ; 0 ; Signed Integer ; +; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ; +; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ; +; EMPTY_LATENCY ; 1 ; Signed Integer ; +; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ; +; DATA_WIDTH ; 102 ; Signed Integer ; +; EMPTY_WIDTH ; 0 ; Signed Integer ; ++---------------------+-------+-------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: system:inst_cpu|altera_merlin_slave_agent:jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent ; ++---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------+ +; PKT_BEGIN_BURST ; 81 ; Signed Integer ; +; PKT_DATA_H ; 31 ; Signed Integer ; +; PKT_DATA_L ; 0 ; Signed Integer ; +; PKT_SYMBOL_W ; 8 ; Signed Integer ; +; PKT_BYTEEN_H ; 35 ; Signed Integer ; +; PKT_BYTEEN_L ; 32 ; Signed Integer ; +; PKT_ADDR_H ; 61 ; Signed Integer ; +; PKT_ADDR_L ; 36 ; Signed Integer ; +; PKT_TRANS_LOCK ; 66 ; Signed Integer ; +; PKT_TRANS_COMPRESSED_READ ; 62 ; Signed Integer ; +; PKT_TRANS_POSTED ; 63 ; Signed Integer ; +; PKT_TRANS_WRITE ; 64 ; Signed Integer ; +; PKT_TRANS_READ ; 65 ; Signed Integer ; +; PKT_SRC_ID_H ; 86 ; Signed Integer ; +; PKT_SRC_ID_L ; 83 ; Signed Integer ; +; PKT_DEST_ID_H ; 90 ; Signed Integer ; +; PKT_DEST_ID_L ; 87 ; Signed Integer ; +; PKT_BURSTWRAP_H ; 73 ; Signed Integer ; +; PKT_BURSTWRAP_L ; 71 ; Signed Integer ; +; PKT_BYTE_CNT_H ; 70 ; Signed Integer ; +; PKT_BYTE_CNT_L ; 68 ; Signed Integer ; +; PKT_PROTECTION_H ; 94 ; Signed Integer ; +; PKT_PROTECTION_L ; 92 ; Signed Integer ; +; PKT_RESPONSE_STATUS_H ; 100 ; Signed Integer ; +; PKT_RESPONSE_STATUS_L ; 99 ; Signed Integer ; +; PKT_BURST_SIZE_H ; 76 ; Signed Integer ; +; PKT_BURST_SIZE_L ; 74 ; Signed Integer ; +; ST_DATA_W ; 101 ; Signed Integer ; +; ST_CHANNEL_W ; 11 ; Signed Integer ; +; ADDR_W ; 26 ; Signed Integer ; +; AVS_DATA_W ; 32 ; Signed Integer ; +; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ; +; PKT_SYMBOLS ; 4 ; Signed Integer ; +; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ; +; SUPPRESS_0_BYTEEN_CMD ; 0 ; Signed Integer ; +; AVS_BE_W ; 4 ; Signed Integer ; +; BURST_SIZE_W ; 3 ; Signed Integer ; +; FIFO_DATA_W ; 102 ; Signed Integer ; ++---------------------------+-------+----------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: system:inst_cpu|altera_merlin_slave_agent:jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor ; ++----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; ADDR_W ; 26 ; Signed Integer ; +; BURSTWRAP_W ; 3 ; Signed Integer ; +; BYTE_CNT_W ; 3 ; Signed Integer ; +; PKT_SYMBOLS ; 4 ; Signed Integer ; +; BURST_SIZE_W ; 3 ; Signed Integer ; ++----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: system:inst_cpu|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo ; ++---------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++---------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------+ +; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; +; BITS_PER_SYMBOL ; 102 ; Signed Integer ; +; FIFO_DEPTH ; 2 ; Signed Integer ; +; CHANNEL_WIDTH ; 0 ; Signed Integer ; +; ERROR_WIDTH ; 0 ; Signed Integer ; +; USE_PACKETS ; 1 ; Signed Integer ; +; USE_FILL_LEVEL ; 0 ; Signed Integer ; +; USE_STORE_FORWARD ; 0 ; Signed Integer ; +; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ; +; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ; +; EMPTY_LATENCY ; 1 ; Signed Integer ; +; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ; +; DATA_WIDTH ; 102 ; Signed Integer ; +; EMPTY_WIDTH ; 0 ; Signed Integer ; ++---------------------+-------+---------------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: system:inst_cpu|altera_merlin_slave_agent:pio_motor_rst_s1_translator_avalon_universal_slave_0_agent ; ++---------------------------+-------+---------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++---------------------------+-------+---------------------------------------------------------------------------------------------------------------+ +; PKT_BEGIN_BURST ; 81 ; Signed Integer ; +; PKT_DATA_H ; 31 ; Signed Integer ; +; PKT_DATA_L ; 0 ; Signed Integer ; +; PKT_SYMBOL_W ; 8 ; Signed Integer ; +; PKT_BYTEEN_H ; 35 ; Signed Integer ; +; PKT_BYTEEN_L ; 32 ; Signed Integer ; +; PKT_ADDR_H ; 61 ; Signed Integer ; +; PKT_ADDR_L ; 36 ; Signed Integer ; +; PKT_TRANS_LOCK ; 66 ; Signed Integer ; +; PKT_TRANS_COMPRESSED_READ ; 62 ; Signed Integer ; +; PKT_TRANS_POSTED ; 63 ; Signed Integer ; +; PKT_TRANS_WRITE ; 64 ; Signed Integer ; +; PKT_TRANS_READ ; 65 ; Signed Integer ; +; PKT_SRC_ID_H ; 86 ; Signed Integer ; +; PKT_SRC_ID_L ; 83 ; Signed Integer ; +; PKT_DEST_ID_H ; 90 ; Signed Integer ; +; PKT_DEST_ID_L ; 87 ; Signed Integer ; +; PKT_BURSTWRAP_H ; 73 ; Signed Integer ; +; PKT_BURSTWRAP_L ; 71 ; Signed Integer ; +; PKT_BYTE_CNT_H ; 70 ; Signed Integer ; +; PKT_BYTE_CNT_L ; 68 ; Signed Integer ; +; PKT_PROTECTION_H ; 94 ; Signed Integer ; +; PKT_PROTECTION_L ; 92 ; Signed Integer ; +; PKT_RESPONSE_STATUS_H ; 100 ; Signed Integer ; +; PKT_RESPONSE_STATUS_L ; 99 ; Signed Integer ; +; PKT_BURST_SIZE_H ; 76 ; Signed Integer ; +; PKT_BURST_SIZE_L ; 74 ; Signed Integer ; +; ST_DATA_W ; 101 ; Signed Integer ; +; ST_CHANNEL_W ; 11 ; Signed Integer ; +; ADDR_W ; 26 ; Signed Integer ; +; AVS_DATA_W ; 32 ; Signed Integer ; +; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ; +; PKT_SYMBOLS ; 4 ; Signed Integer ; +; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ; +; SUPPRESS_0_BYTEEN_CMD ; 0 ; Signed Integer ; +; AVS_BE_W ; 4 ; Signed Integer ; +; BURST_SIZE_W ; 3 ; Signed Integer ; +; FIFO_DATA_W ; 102 ; Signed Integer ; ++---------------------------+-------+---------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: system:inst_cpu|altera_merlin_slave_agent:pio_motor_rst_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor ; ++----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; ADDR_W ; 26 ; Signed Integer ; +; BURSTWRAP_W ; 3 ; Signed Integer ; +; BYTE_CNT_W ; 3 ; Signed Integer ; +; PKT_SYMBOLS ; 4 ; Signed Integer ; +; BURST_SIZE_W ; 3 ; Signed Integer ; ++----------------+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: system:inst_cpu|altera_avalon_sc_fifo:pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; ++---------------------+-------+--------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++---------------------+-------+--------------------------------------------------------------------------------------------------------------------------+ +; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; +; BITS_PER_SYMBOL ; 102 ; Signed Integer ; +; FIFO_DEPTH ; 2 ; Signed Integer ; +; CHANNEL_WIDTH ; 0 ; Signed Integer ; +; ERROR_WIDTH ; 0 ; Signed Integer ; +; USE_PACKETS ; 1 ; Signed Integer ; +; USE_FILL_LEVEL ; 0 ; Signed Integer ; +; USE_STORE_FORWARD ; 0 ; Signed Integer ; +; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ; +; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ; +; EMPTY_LATENCY ; 1 ; Signed Integer ; +; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ; +; DATA_WIDTH ; 102 ; Signed Integer ; +; EMPTY_WIDTH ; 0 ; Signed Integer ; ++---------------------+-------+--------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: system:inst_cpu|altera_merlin_slave_agent:rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent ; ++---------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++---------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------+ +; PKT_BEGIN_BURST ; 81 ; Signed Integer ; +; PKT_DATA_H ; 31 ; Signed Integer ; +; PKT_DATA_L ; 0 ; Signed Integer ; +; PKT_SYMBOL_W ; 8 ; Signed Integer ; +; PKT_BYTEEN_H ; 35 ; Signed Integer ; +; PKT_BYTEEN_L ; 32 ; Signed Integer ; +; PKT_ADDR_H ; 61 ; Signed Integer ; +; PKT_ADDR_L ; 36 ; Signed Integer ; +; PKT_TRANS_LOCK ; 66 ; Signed Integer ; +; PKT_TRANS_COMPRESSED_READ ; 62 ; Signed Integer ; +; PKT_TRANS_POSTED ; 63 ; Signed Integer ; +; PKT_TRANS_WRITE ; 64 ; Signed Integer ; +; PKT_TRANS_READ ; 65 ; Signed Integer ; +; PKT_SRC_ID_H ; 86 ; Signed Integer ; +; PKT_SRC_ID_L ; 83 ; Signed Integer ; +; PKT_DEST_ID_H ; 90 ; Signed Integer ; +; PKT_DEST_ID_L ; 87 ; Signed Integer ; +; PKT_BURSTWRAP_H ; 73 ; Signed Integer ; +; PKT_BURSTWRAP_L ; 71 ; Signed Integer ; +; PKT_BYTE_CNT_H ; 70 ; Signed Integer ; +; PKT_BYTE_CNT_L ; 68 ; Signed Integer ; +; PKT_PROTECTION_H ; 94 ; Signed Integer ; +; PKT_PROTECTION_L ; 92 ; Signed Integer ; +; PKT_RESPONSE_STATUS_H ; 100 ; Signed Integer ; +; PKT_RESPONSE_STATUS_L ; 99 ; Signed Integer ; +; PKT_BURST_SIZE_H ; 76 ; Signed Integer ; +; PKT_BURST_SIZE_L ; 74 ; Signed Integer ; +; ST_DATA_W ; 101 ; Signed Integer ; +; ST_CHANNEL_W ; 11 ; Signed Integer ; +; ADDR_W ; 26 ; Signed Integer ; +; AVS_DATA_W ; 32 ; Signed Integer ; +; AVS_BURSTCOUNT_W ; 3 ; Signed Integer ; +; PKT_SYMBOLS ; 4 ; Signed Integer ; +; PREVENT_FIFO_OVERFLOW ; 1 ; Signed Integer ; +; SUPPRESS_0_BYTEEN_CMD ; 0 ; Signed Integer ; +; AVS_BE_W ; 4 ; Signed Integer ; +; BURST_SIZE_W ; 3 ; Signed Integer ; +; FIFO_DATA_W ; 102 ; Signed Integer ; ++---------------------------+-------+-----------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: system:inst_cpu|altera_merlin_slave_agent:rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor ; ++----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; ADDR_W ; 26 ; Signed Integer ; +; BURSTWRAP_W ; 3 ; Signed Integer ; +; BYTE_CNT_W ; 3 ; Signed Integer ; +; PKT_SYMBOLS ; 4 ; Signed Integer ; +; BURST_SIZE_W ; 3 ; Signed Integer ; ++----------------+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: system:inst_cpu|altera_avalon_sc_fifo:rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo ; ++---------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++---------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ +; SYMBOLS_PER_BEAT ; 1 ; Signed Integer ; +; BITS_PER_SYMBOL ; 102 ; Signed Integer ; +; FIFO_DEPTH ; 2 ; Signed Integer ; +; CHANNEL_WIDTH ; 0 ; Signed Integer ; +; ERROR_WIDTH ; 0 ; Signed Integer ; +; USE_PACKETS ; 1 ; Signed Integer ; +; USE_FILL_LEVEL ; 0 ; Signed Integer ; +; USE_STORE_FORWARD ; 0 ; Signed Integer ; +; USE_ALMOST_FULL_IF ; 0 ; Signed Integer ; +; USE_ALMOST_EMPTY_IF ; 0 ; Signed Integer ; +; EMPTY_LATENCY ; 1 ; Signed Integer ; +; USE_MEMORY_BLOCKS ; 0 ; Signed Integer ; +; DATA_WIDTH ; 102 ; Signed Integer ; +; EMPTY_WIDTH ; 0 ; Signed Integer ; ++---------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: system:inst_cpu|system_addr_router:addr_router|system_addr_router_default_decode:the_default_decode ; ++-----------------+-------+------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++-----------------+-------+------------------------------------------------------------------------------------------------------------------------+ +; DEFAULT_CHANNEL ; 1 ; Signed Integer ; +; DEFAULT_DESTID ; 1 ; Signed Integer ; ++-----------------+-------+------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: system:inst_cpu|system_addr_router_001:addr_router_001|system_addr_router_001_default_decode:the_default_decode ; ++-----------------+-------+------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++-----------------+-------+------------------------------------------------------------------------------------------------------------------------------------+ +; DEFAULT_CHANNEL ; 1 ; Signed Integer ; +; DEFAULT_DESTID ; 1 ; Signed Integer ; ++-----------------+-------+------------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: system:inst_cpu|system_id_router:id_router|system_id_router_default_decode:the_default_decode ; ++-----------------+-------+------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++-----------------+-------+------------------------------------------------------------------------------------------------------------------+ +; DEFAULT_CHANNEL ; 0 ; Signed Integer ; +; DEFAULT_DESTID ; 0 ; Signed Integer ; ++-----------------+-------+------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: system:inst_cpu|system_id_router_001:id_router_001|system_id_router_001_default_decode:the_default_decode ; ++-----------------+-------+------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++-----------------+-------+------------------------------------------------------------------------------------------------------------------------------+ +; DEFAULT_CHANNEL ; 0 ; Signed Integer ; +; DEFAULT_DESTID ; 0 ; Signed Integer ; ++-----------------+-------+------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: system:inst_cpu|system_id_router_002:id_router_002|system_id_router_002_default_decode:the_default_decode ; ++-----------------+-------+------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++-----------------+-------+------------------------------------------------------------------------------------------------------------------------------+ +; DEFAULT_CHANNEL ; 0 ; Signed Integer ; +; DEFAULT_DESTID ; 1 ; Signed Integer ; ++-----------------+-------+------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: system:inst_cpu|system_id_router_002:id_router_003|system_id_router_002_default_decode:the_default_decode ; ++-----------------+-------+------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++-----------------+-------+------------------------------------------------------------------------------------------------------------------------------+ +; DEFAULT_CHANNEL ; 0 ; Signed Integer ; +; DEFAULT_DESTID ; 1 ; Signed Integer ; ++-----------------+-------+------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: system:inst_cpu|system_id_router_002:id_router_004|system_id_router_002_default_decode:the_default_decode ; ++-----------------+-------+------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++-----------------+-------+------------------------------------------------------------------------------------------------------------------------------+ +; DEFAULT_CHANNEL ; 0 ; Signed Integer ; +; DEFAULT_DESTID ; 1 ; Signed Integer ; ++-----------------+-------+------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: system:inst_cpu|system_id_router_002:id_router_005|system_id_router_002_default_decode:the_default_decode ; ++-----------------+-------+------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++-----------------+-------+------------------------------------------------------------------------------------------------------------------------------+ +; DEFAULT_CHANNEL ; 0 ; Signed Integer ; +; DEFAULT_DESTID ; 1 ; Signed Integer ; ++-----------------+-------+------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: system:inst_cpu|system_id_router_002:id_router_006|system_id_router_002_default_decode:the_default_decode ; ++-----------------+-------+------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++-----------------+-------+------------------------------------------------------------------------------------------------------------------------------+ +; DEFAULT_CHANNEL ; 0 ; Signed Integer ; +; DEFAULT_DESTID ; 1 ; Signed Integer ; ++-----------------+-------+------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: system:inst_cpu|system_id_router_002:id_router_007|system_id_router_002_default_decode:the_default_decode ; ++-----------------+-------+------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++-----------------+-------+------------------------------------------------------------------------------------------------------------------------------+ +; DEFAULT_CHANNEL ; 0 ; Signed Integer ; +; DEFAULT_DESTID ; 1 ; Signed Integer ; ++-----------------+-------+------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: system:inst_cpu|system_id_router_002:id_router_008|system_id_router_002_default_decode:the_default_decode ; ++-----------------+-------+------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++-----------------+-------+------------------------------------------------------------------------------------------------------------------------------+ +; DEFAULT_CHANNEL ; 0 ; Signed Integer ; +; DEFAULT_DESTID ; 1 ; Signed Integer ; ++-----------------+-------+------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: system:inst_cpu|system_id_router_002:id_router_009|system_id_router_002_default_decode:the_default_decode ; ++-----------------+-------+------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++-----------------+-------+------------------------------------------------------------------------------------------------------------------------------+ +; DEFAULT_CHANNEL ; 0 ; Signed Integer ; +; DEFAULT_DESTID ; 1 ; Signed Integer ; ++-----------------+-------+------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: system:inst_cpu|system_id_router_002:id_router_010|system_id_router_002_default_decode:the_default_decode ; ++-----------------+-------+------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++-----------------+-------+------------------------------------------------------------------------------------------------------------------------------+ +; DEFAULT_CHANNEL ; 0 ; Signed Integer ; +; DEFAULT_DESTID ; 1 ; Signed Integer ; ++-----------------+-------+------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++----------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: system:inst_cpu|altera_merlin_traffic_limiter:limiter ; ++---------------------------+-------+----------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++---------------------------+-------+----------------------------------------------------------------+ +; PKT_TRANS_POSTED ; 63 ; Signed Integer ; +; PKT_DEST_ID_H ; 90 ; Signed Integer ; +; PKT_DEST_ID_L ; 87 ; Signed Integer ; +; ST_DATA_W ; 101 ; Signed Integer ; +; ST_CHANNEL_W ; 11 ; Signed Integer ; +; MAX_OUTSTANDING_RESPONSES ; 9 ; Signed Integer ; +; PIPELINED ; 0 ; Signed Integer ; +; ENFORCE_ORDER ; 1 ; Signed Integer ; +; PKT_BYTE_CNT_H ; 70 ; Signed Integer ; +; PKT_BYTE_CNT_L ; 68 ; Signed Integer ; +; PKT_BYTEEN_H ; 35 ; Signed Integer ; +; PKT_BYTEEN_L ; 32 ; Signed Integer ; +; PKT_TRANS_WRITE ; 64 ; Signed Integer ; +; PKT_TRANS_READ ; 0 ; Signed Integer ; +; VALID_WIDTH ; 11 ; Signed Integer ; +; PREVENT_HAZARDS ; 0 ; Signed Integer ; ++---------------------------+-------+----------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: system:inst_cpu|altera_merlin_traffic_limiter:limiter_001 ; ++---------------------------+-------+--------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++---------------------------+-------+--------------------------------------------------------------------+ +; PKT_TRANS_POSTED ; 63 ; Signed Integer ; +; PKT_DEST_ID_H ; 90 ; Signed Integer ; +; PKT_DEST_ID_L ; 87 ; Signed Integer ; +; ST_DATA_W ; 101 ; Signed Integer ; +; ST_CHANNEL_W ; 11 ; Signed Integer ; +; MAX_OUTSTANDING_RESPONSES ; 9 ; Signed Integer ; +; PIPELINED ; 0 ; Signed Integer ; +; ENFORCE_ORDER ; 1 ; Signed Integer ; +; PKT_BYTE_CNT_H ; 70 ; Signed Integer ; +; PKT_BYTE_CNT_L ; 68 ; Signed Integer ; +; PKT_BYTEEN_H ; 35 ; Signed Integer ; +; PKT_BYTEEN_L ; 32 ; Signed Integer ; +; PKT_TRANS_WRITE ; 64 ; Signed Integer ; +; PKT_TRANS_READ ; 0 ; Signed Integer ; +; VALID_WIDTH ; 11 ; Signed Integer ; +; PREVENT_HAZARDS ; 0 ; Signed Integer ; ++---------------------------+-------+--------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: system:inst_cpu|altera_merlin_burst_adapter:burst_adapter ; ++---------------------------+-------+--------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++---------------------------+-------+--------------------------------------------------------------------+ +; PKT_BEGIN_BURST ; 63 ; Signed Integer ; +; PKT_ADDR_H ; 43 ; Signed Integer ; +; PKT_ADDR_L ; 18 ; Signed Integer ; +; PKT_BYTE_CNT_H ; 52 ; Signed Integer ; +; PKT_BYTE_CNT_L ; 50 ; Signed Integer ; +; PKT_BURSTWRAP_H ; 55 ; Signed Integer ; +; PKT_BURSTWRAP_L ; 53 ; Signed Integer ; +; PKT_TRANS_COMPRESSED_READ ; 44 ; Signed Integer ; +; PKT_TRANS_WRITE ; 46 ; Signed Integer ; +; PKT_TRANS_READ ; 47 ; Signed Integer ; +; PKT_BYTEEN_H ; 17 ; Signed Integer ; +; PKT_BYTEEN_L ; 16 ; Signed Integer ; +; PKT_BURST_TYPE_H ; 60 ; Signed Integer ; +; PKT_BURST_TYPE_L ; 59 ; Signed Integer ; +; PKT_BURST_SIZE_H ; 58 ; Signed Integer ; +; PKT_BURST_SIZE_L ; 56 ; Signed Integer ; +; IN_NARROW_SIZE ; 0 ; Signed Integer ; +; OUT_NARROW_SIZE ; 0 ; Signed Integer ; +; OUT_FIXED ; 0 ; Signed Integer ; +; OUT_COMPLETE_WRAP ; 0 ; Signed Integer ; +; ST_DATA_W ; 83 ; Signed Integer ; +; ST_CHANNEL_W ; 11 ; Signed Integer ; +; BYTEENABLE_SYNTHESIS ; 0 ; Signed Integer ; +; BURSTWRAP_CONST_MASK ; 3 ; Signed Integer ; +; BURSTWRAP_CONST_VALUE ; 3 ; Signed Integer ; +; NO_WRAP_SUPPORT ; 0 ; Signed Integer ; +; PIPE_INPUTS ; 0 ; Signed Integer ; +; OUT_BYTE_CNT_H ; 51 ; Signed Integer ; +; OUT_BURSTWRAP_H ; 55 ; Signed Integer ; +; COMPRESSED_READ_SUPPORT ; 0 ; Signed Integer ; ++---------------------------+-------+--------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: system:inst_cpu|altera_merlin_burst_adapter:burst_adapter|altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba ; ++----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; PKT_BYTE_CNT_H ; 52 ; Signed Integer ; +; PKT_BYTE_CNT_L ; 50 ; Signed Integer ; +; PKT_BYTEEN_H ; 17 ; Signed Integer ; +; PKT_BYTEEN_L ; 16 ; Signed Integer ; +; ST_DATA_W ; 83 ; Signed Integer ; +; ST_CHANNEL_W ; 11 ; Signed Integer ; ++----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-----------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: system:inst_cpu|altera_reset_controller:rst_controller ; ++-------------------------+----------+----------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++-------------------------+----------+----------------------------------------------------------------+ +; NUM_RESET_INPUTS ; 2 ; Signed Integer ; +; OUTPUT_RESET_SYNC_EDGES ; deassert ; String ; +; SYNC_DEPTH ; 2 ; Signed Integer ; ++-------------------------+----------+----------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1 ; ++----------------+-------+-----------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+-----------------------------------------------------------------------------------------------------------------------+ +; ASYNC_RESET ; 1 ; Unsigned Binary ; +; DEPTH ; 2 ; Signed Integer ; ++----------------+-------+-----------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++----------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux|altera_merlin_arbitrator:arb ; ++----------------+-------------+---------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------------+---------------------------------------------------------------------------------------------+ +; NUM_REQUESTERS ; 2 ; Signed Integer ; +; SCHEME ; round-robin ; String ; +; PIPELINE ; 1 ; Signed Integer ; ++----------------+-------------+---------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder ; ++----------------+-------+---------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+---------------------------------------------------------------------------------------------------------------------------------+ +; WIDTH ; 4 ; Signed Integer ; ++----------------+-------+---------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux_001|altera_merlin_arbitrator:arb ; ++----------------+-------------+-------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------------+-------------------------------------------------------------------------------------------------+ +; NUM_REQUESTERS ; 2 ; Signed Integer ; +; SCHEME ; round-robin ; String ; +; PIPELINE ; 1 ; Signed Integer ; ++----------------+-------------+-------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux_001|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder ; ++----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------+ +; WIDTH ; 4 ; Signed Integer ; ++----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++----------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: system:inst_cpu|system_rsp_xbar_mux:rsp_xbar_mux|altera_merlin_arbitrator:arb ; ++----------------+--------+--------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+--------+--------------------------------------------------------------------------------------------------+ +; NUM_REQUESTERS ; 2 ; Signed Integer ; +; SCHEME ; no-arb ; String ; +; PIPELINE ; 0 ; Signed Integer ; ++----------------+--------+--------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: system:inst_cpu|system_rsp_xbar_mux:rsp_xbar_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder ; ++----------------+-------+---------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+---------------------------------------------------------------------------------------------------------------------------------+ +; WIDTH ; 4 ; Signed Integer ; ++----------------+-------+---------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: system:inst_cpu|system_rsp_xbar_mux_001:rsp_xbar_mux_001|altera_merlin_arbitrator:arb ; ++----------------+--------+----------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+--------+----------------------------------------------------------------------------------------------------------+ +; NUM_REQUESTERS ; 11 ; Signed Integer ; +; SCHEME ; no-arb ; String ; +; PIPELINE ; 0 ; Signed Integer ; ++----------------+--------+----------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: system:inst_cpu|system_rsp_xbar_mux_001:rsp_xbar_mux_001|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder ; ++----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------+ +; WIDTH ; 22 ; Signed Integer ; ++----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: system:inst_cpu|altera_merlin_width_adapter:width_adapter ; ++-------------------------------+-------+----------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++-------------------------------+-------+----------------------------------------------------------------+ +; IN_PKT_ADDR_L ; 36 ; Signed Integer ; +; IN_PKT_ADDR_H ; 61 ; Signed Integer ; +; IN_PKT_DATA_L ; 0 ; Signed Integer ; +; IN_PKT_DATA_H ; 31 ; Signed Integer ; +; IN_PKT_BYTEEN_L ; 32 ; Signed Integer ; +; IN_PKT_BYTEEN_H ; 35 ; Signed Integer ; +; IN_PKT_TRANS_COMPRESSED_READ ; 62 ; Signed Integer ; +; IN_PKT_BYTE_CNT_L ; 68 ; Signed Integer ; +; IN_PKT_BYTE_CNT_H ; 70 ; Signed Integer ; +; IN_PKT_BURSTWRAP_L ; 71 ; Signed Integer ; +; IN_PKT_BURSTWRAP_H ; 73 ; Signed Integer ; +; IN_PKT_BURST_SIZE_L ; 74 ; Signed Integer ; +; IN_PKT_BURST_SIZE_H ; 76 ; Signed Integer ; +; IN_PKT_RESPONSE_STATUS_L ; 99 ; Signed Integer ; +; IN_PKT_RESPONSE_STATUS_H ; 100 ; Signed Integer ; +; IN_PKT_TRANS_EXCLUSIVE ; 67 ; Signed Integer ; +; IN_PKT_BURST_TYPE_L ; 77 ; Signed Integer ; +; IN_PKT_BURST_TYPE_H ; 78 ; Signed Integer ; +; IN_ST_DATA_W ; 101 ; Signed Integer ; +; OUT_PKT_ADDR_L ; 18 ; Signed Integer ; +; OUT_PKT_ADDR_H ; 43 ; Signed Integer ; +; OUT_PKT_DATA_L ; 0 ; Signed Integer ; +; OUT_PKT_DATA_H ; 15 ; Signed Integer ; +; OUT_PKT_BYTEEN_L ; 16 ; Signed Integer ; +; OUT_PKT_BYTEEN_H ; 17 ; Signed Integer ; +; OUT_PKT_TRANS_COMPRESSED_READ ; 44 ; Signed Integer ; +; OUT_PKT_BYTE_CNT_L ; 50 ; Signed Integer ; +; OUT_PKT_BYTE_CNT_H ; 52 ; Signed Integer ; +; OUT_PKT_BURST_SIZE_L ; 56 ; Signed Integer ; +; OUT_PKT_BURST_SIZE_H ; 58 ; Signed Integer ; +; OUT_PKT_RESPONSE_STATUS_L ; 81 ; Signed Integer ; +; OUT_PKT_RESPONSE_STATUS_H ; 82 ; Signed Integer ; +; OUT_PKT_TRANS_EXCLUSIVE ; 49 ; Signed Integer ; +; OUT_PKT_BURST_TYPE_L ; 59 ; Signed Integer ; +; OUT_PKT_BURST_TYPE_H ; 60 ; Signed Integer ; +; OUT_ST_DATA_W ; 83 ; Signed Integer ; +; ST_CHANNEL_W ; 11 ; Signed Integer ; +; OPTIMIZE_FOR_RSP ; 0 ; Signed Integer ; +; PACKING ; 1 ; Signed Integer ; +; CONSTANT_BURST_SIZE ; 1 ; Signed Integer ; +; RESPONSE_PATH ; 0 ; Signed Integer ; ++-------------------------------+-------+----------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: system:inst_cpu|altera_merlin_width_adapter:width_adapter_001 ; ++-------------------------------+-------+--------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++-------------------------------+-------+--------------------------------------------------------------------+ +; IN_PKT_ADDR_L ; 18 ; Signed Integer ; +; IN_PKT_ADDR_H ; 43 ; Signed Integer ; +; IN_PKT_DATA_L ; 0 ; Signed Integer ; +; IN_PKT_DATA_H ; 15 ; Signed Integer ; +; IN_PKT_BYTEEN_L ; 16 ; Signed Integer ; +; IN_PKT_BYTEEN_H ; 17 ; Signed Integer ; +; IN_PKT_TRANS_COMPRESSED_READ ; 44 ; Signed Integer ; +; IN_PKT_BYTE_CNT_L ; 50 ; Signed Integer ; +; IN_PKT_BYTE_CNT_H ; 52 ; Signed Integer ; +; IN_PKT_BURSTWRAP_L ; 53 ; Signed Integer ; +; IN_PKT_BURSTWRAP_H ; 55 ; Signed Integer ; +; IN_PKT_BURST_SIZE_L ; 56 ; Signed Integer ; +; IN_PKT_BURST_SIZE_H ; 58 ; Signed Integer ; +; IN_PKT_RESPONSE_STATUS_L ; 81 ; Signed Integer ; +; IN_PKT_RESPONSE_STATUS_H ; 82 ; Signed Integer ; +; IN_PKT_TRANS_EXCLUSIVE ; 49 ; Signed Integer ; +; IN_PKT_BURST_TYPE_L ; 59 ; Signed Integer ; +; IN_PKT_BURST_TYPE_H ; 60 ; Signed Integer ; +; IN_ST_DATA_W ; 83 ; Signed Integer ; +; OUT_PKT_ADDR_L ; 36 ; Signed Integer ; +; OUT_PKT_ADDR_H ; 61 ; Signed Integer ; +; OUT_PKT_DATA_L ; 0 ; Signed Integer ; +; OUT_PKT_DATA_H ; 31 ; Signed Integer ; +; OUT_PKT_BYTEEN_L ; 32 ; Signed Integer ; +; OUT_PKT_BYTEEN_H ; 35 ; Signed Integer ; +; OUT_PKT_TRANS_COMPRESSED_READ ; 62 ; Signed Integer ; +; OUT_PKT_BYTE_CNT_L ; 68 ; Signed Integer ; +; OUT_PKT_BYTE_CNT_H ; 70 ; Signed Integer ; +; OUT_PKT_BURST_SIZE_L ; 74 ; Signed Integer ; +; OUT_PKT_BURST_SIZE_H ; 76 ; Signed Integer ; +; OUT_PKT_RESPONSE_STATUS_L ; 99 ; Signed Integer ; +; OUT_PKT_RESPONSE_STATUS_H ; 100 ; Signed Integer ; +; OUT_PKT_TRANS_EXCLUSIVE ; 67 ; Signed Integer ; +; OUT_PKT_BURST_TYPE_L ; 77 ; Signed Integer ; +; OUT_PKT_BURST_TYPE_H ; 78 ; Signed Integer ; +; OUT_ST_DATA_W ; 101 ; Signed Integer ; +; ST_CHANNEL_W ; 11 ; Signed Integer ; +; OPTIMIZE_FOR_RSP ; 1 ; Signed Integer ; +; PACKING ; 1 ; Signed Integer ; +; CONSTANT_BURST_SIZE ; 1 ; Signed Integer ; +; RESPONSE_PATH ; 0 ; Signed Integer ; ++-------------------------------+-------+--------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|altera_merlin_burst_uncompressor:uncompressor ; ++----------------+-------+---------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+---------------------------------------------------------------------------------------------------------------------------------+ +; ADDR_W ; 26 ; Signed Integer ; +; BURSTWRAP_W ; 3 ; Signed Integer ; +; BYTE_CNT_W ; 3 ; Signed Integer ; +; PKT_SYMBOLS ; 2 ; Signed Integer ; +; BURST_SIZE_W ; 3 ; Signed Integer ; ++----------------+-------+---------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------+ +; altpll Parameter Settings by Entity Instance ; ++-------------------------------+----------------------------------------------+ +; Name ; Value ; ++-------------------------------+----------------------------------------------+ +; Number of entity instances ; 1 ; +; Entity Instance ; pll_sys:inst_pll_sys|altpll:altpll_component ; +; -- OPERATION_MODE ; NORMAL ; +; -- PLL_TYPE ; AUTO ; +; -- PRIMARY_CLOCK ; INCLK0 ; +; -- INCLK0_INPUT_FREQUENCY ; 20000 ; +; -- INCLK1_INPUT_FREQUENCY ; 0 ; +; -- VCO_MULTIPLY_BY ; 0 ; +; -- VCO_DIVIDE_BY ; 0 ; ++-------------------------------+----------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; scfifo Parameter Settings by Entity Instance ; ++----------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Name ; Value ; ++----------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Number of entity instances ; 4 ; +; Entity Instance ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo ; +; -- FIFO Type ; Single Clock ; +; -- lpm_width ; 8 ; +; -- LPM_NUMWORDS ; 64 ; +; -- LPM_SHOWAHEAD ; OFF ; +; -- USE_EAB ; ON ; +; Entity Instance ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo ; +; -- FIFO Type ; Single Clock ; +; -- lpm_width ; 8 ; +; -- LPM_NUMWORDS ; 64 ; +; -- LPM_SHOWAHEAD ; OFF ; +; -- USE_EAB ; ON ; +; Entity Instance ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO ; +; -- FIFO Type ; Single Clock ; +; -- lpm_width ; 8 ; +; -- LPM_NUMWORDS ; 128 ; +; -- LPM_SHOWAHEAD ; ON ; +; -- USE_EAB ; ON ; +; Entity Instance ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO ; +; -- FIFO Type ; Single Clock ; +; -- lpm_width ; 8 ; +; -- LPM_NUMWORDS ; 128 ; +; -- LPM_SHOWAHEAD ; ON ; +; -- USE_EAB ; ON ; ++----------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|altera_merlin_burst_uncompressor:uncompressor" ; ++----------------------+--------+----------+----------------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++----------------------+--------+----------+----------------------------------------------------------------------------------------------+ +; sink_ready ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; sink_is_compressed ; Input ; Info ; Stuck at VCC ; +; sink_burstsize[2..1] ; Input ; Info ; Stuck at GND ; +; sink_burstsize[0] ; Input ; Info ; Stuck at VCC ; +; source_burstwrap ; Output ; Info ; Explicitly unconnected ; +; source_is_compressed ; Output ; Info ; Explicitly unconnected ; +; source_burstsize ; Output ; Info ; Explicitly unconnected ; ++----------------------+--------+----------+----------------------------------------------------------------------------------------------+ + + ++-------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "system:inst_cpu|altera_merlin_width_adapter:width_adapter_001" ; ++----------------------+-------+----------+-------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++----------------------+-------+----------+-------------------------------------------------+ +; in_command_size_data ; Input ; Info ; Stuck at GND ; ++----------------------+-------+----------+-------------------------------------------------+ + + ++---------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "system:inst_cpu|altera_merlin_width_adapter:width_adapter" ; ++----------------------+-------+----------+---------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++----------------------+-------+----------+---------------------------------------------+ +; in_command_size_data ; Input ; Info ; Stuck at GND ; ++----------------------+-------+----------+---------------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "system:inst_cpu|system_rsp_xbar_mux_001:rsp_xbar_mux_001|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder" ; ++----------+--------+----------+------------------------------------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++----------+--------+----------+------------------------------------------------------------------------------------------------------------------+ +; b[21..1] ; Input ; Info ; Stuck at GND ; +; b[0] ; Input ; Info ; Stuck at VCC ; +; sum ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ++----------+--------+----------+------------------------------------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "system:inst_cpu|system_rsp_xbar_mux:rsp_xbar_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder" ; ++---------+--------+----------+-----------------------------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++---------+--------+----------+-----------------------------------------------------------------------------------------------------------+ +; b[3..1] ; Input ; Info ; Stuck at GND ; +; b[0] ; Input ; Info ; Stuck at VCC ; +; sum ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ++---------+--------+----------+-----------------------------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder" ; ++---------+-------+----------+------------------------------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++---------+-------+----------+------------------------------------------------------------------------------------------------------------+ +; b[3..2] ; Input ; Info ; Stuck at GND ; ++---------+-------+----------+------------------------------------------------------------------------------------------------------------+ + + ++------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "system:inst_cpu|altera_reset_controller:rst_controller" ; ++------------+-------+----------+----------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++------------+-------+----------+----------------------------------------------------+ +; reset_in2 ; Input ; Info ; Stuck at GND ; +; reset_in3 ; Input ; Info ; Stuck at GND ; +; reset_in4 ; Input ; Info ; Stuck at GND ; +; reset_in5 ; Input ; Info ; Stuck at GND ; +; reset_in6 ; Input ; Info ; Stuck at GND ; +; reset_in7 ; Input ; Info ; Stuck at GND ; +; reset_in8 ; Input ; Info ; Stuck at GND ; +; reset_in9 ; Input ; Info ; Stuck at GND ; +; reset_in10 ; Input ; Info ; Stuck at GND ; +; reset_in11 ; Input ; Info ; Stuck at GND ; +; reset_in12 ; Input ; Info ; Stuck at GND ; +; reset_in13 ; Input ; Info ; Stuck at GND ; +; reset_in14 ; Input ; Info ; Stuck at GND ; +; reset_in15 ; Input ; Info ; Stuck at GND ; ++------------+-------+----------+----------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "system:inst_cpu|system_id_router_002:id_router_002|system_id_router_002_default_decode:the_default_decode" ; ++------------------------+--------+----------+------------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++------------------------+--------+----------+------------------------------------------------------------------------------------------+ +; default_destination_id ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ++------------------------+--------+----------+------------------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "system:inst_cpu|system_id_router_001:id_router_001|system_id_router_001_default_decode:the_default_decode" ; ++------------------------+--------+----------+------------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++------------------------+--------+----------+------------------------------------------------------------------------------------------+ +; default_destination_id ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ++------------------------+--------+----------+------------------------------------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "system:inst_cpu|system_id_router:id_router|system_id_router_default_decode:the_default_decode" ; ++------------------------+--------+----------+-------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++------------------------+--------+----------+-------------------------------------------------------------------------------------+ +; default_destination_id ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ++------------------------+--------+----------+-------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "system:inst_cpu|altera_avalon_sc_fifo:rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo" ; ++-------------------+--------+----------+-------------------------------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++-------------------+--------+----------+-------------------------------------------------------------------------------------------------------------+ +; csr_address ; Input ; Info ; Stuck at GND ; +; csr_read ; Input ; Info ; Stuck at GND ; +; csr_write ; Input ; Info ; Stuck at GND ; +; csr_readdata ; Output ; Info ; Explicitly unconnected ; +; csr_writedata ; Input ; Info ; Stuck at GND ; +; almost_full_data ; Output ; Info ; Explicitly unconnected ; +; almost_empty_data ; Output ; Info ; Explicitly unconnected ; +; in_empty ; Input ; Info ; Stuck at GND ; +; out_empty ; Output ; Info ; Explicitly unconnected ; +; in_error ; Input ; Info ; Stuck at GND ; +; out_error ; Output ; Info ; Explicitly unconnected ; +; in_channel ; Input ; Info ; Stuck at GND ; +; out_channel ; Output ; Info ; Explicitly unconnected ; ++-------------------+--------+----------+-------------------------------------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "system:inst_cpu|altera_avalon_sc_fifo:pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" ; ++-------------------+--------+----------+-----------------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++-------------------+--------+----------+-----------------------------------------------------------------------------------------------+ +; csr_address ; Input ; Info ; Stuck at GND ; +; csr_read ; Input ; Info ; Stuck at GND ; +; csr_write ; Input ; Info ; Stuck at GND ; +; csr_readdata ; Output ; Info ; Explicitly unconnected ; +; csr_writedata ; Input ; Info ; Stuck at GND ; +; almost_full_data ; Output ; Info ; Explicitly unconnected ; +; almost_empty_data ; Output ; Info ; Explicitly unconnected ; +; in_empty ; Input ; Info ; Stuck at GND ; +; out_empty ; Output ; Info ; Explicitly unconnected ; +; in_error ; Input ; Info ; Stuck at GND ; +; out_error ; Output ; Info ; Explicitly unconnected ; +; in_channel ; Input ; Info ; Stuck at GND ; +; out_channel ; Output ; Info ; Explicitly unconnected ; ++-------------------+--------+----------+-----------------------------------------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "system:inst_cpu|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo" ; ++-------------------+--------+----------+------------------------------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++-------------------+--------+----------+------------------------------------------------------------------------------------------------------------+ +; csr_address ; Input ; Info ; Stuck at GND ; +; csr_read ; Input ; Info ; Stuck at GND ; +; csr_write ; Input ; Info ; Stuck at GND ; +; csr_readdata ; Output ; Info ; Explicitly unconnected ; +; csr_writedata ; Input ; Info ; Stuck at GND ; +; almost_full_data ; Output ; Info ; Explicitly unconnected ; +; almost_empty_data ; Output ; Info ; Explicitly unconnected ; +; in_empty ; Input ; Info ; Stuck at GND ; +; out_empty ; Output ; Info ; Explicitly unconnected ; +; in_error ; Input ; Info ; Stuck at GND ; +; out_error ; Output ; Info ; Explicitly unconnected ; +; in_channel ; Input ; Info ; Stuck at GND ; +; out_channel ; Output ; Info ; Explicitly unconnected ; ++-------------------+--------+----------+------------------------------------------------------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "system:inst_cpu|altera_avalon_sc_fifo:pio_sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" ; ++-------------------+--------+----------+----------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++-------------------+--------+----------+----------------------------------------------------------------------------------------+ +; csr_address ; Input ; Info ; Stuck at GND ; +; csr_read ; Input ; Info ; Stuck at GND ; +; csr_write ; Input ; Info ; Stuck at GND ; +; csr_readdata ; Output ; Info ; Explicitly unconnected ; +; csr_writedata ; Input ; Info ; Stuck at GND ; +; almost_full_data ; Output ; Info ; Explicitly unconnected ; +; almost_empty_data ; Output ; Info ; Explicitly unconnected ; +; in_empty ; Input ; Info ; Stuck at GND ; +; out_empty ; Output ; Info ; Explicitly unconnected ; +; in_error ; Input ; Info ; Stuck at GND ; +; out_error ; Output ; Info ; Explicitly unconnected ; +; in_channel ; Input ; Info ; Stuck at GND ; +; out_channel ; Output ; Info ; Explicitly unconnected ; ++-------------------+--------+----------+----------------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "system:inst_cpu|altera_avalon_sc_fifo:pio_key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" ; ++-------------------+--------+----------+-----------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++-------------------+--------+----------+-----------------------------------------------------------------------------------------+ +; csr_address ; Input ; Info ; Stuck at GND ; +; csr_read ; Input ; Info ; Stuck at GND ; +; csr_write ; Input ; Info ; Stuck at GND ; +; csr_readdata ; Output ; Info ; Explicitly unconnected ; +; csr_writedata ; Input ; Info ; Stuck at GND ; +; almost_full_data ; Output ; Info ; Explicitly unconnected ; +; almost_empty_data ; Output ; Info ; Explicitly unconnected ; +; in_empty ; Input ; Info ; Stuck at GND ; +; out_empty ; Output ; Info ; Explicitly unconnected ; +; in_error ; Input ; Info ; Stuck at GND ; +; out_error ; Output ; Info ; Explicitly unconnected ; +; in_channel ; Input ; Info ; Stuck at GND ; +; out_channel ; Output ; Info ; Explicitly unconnected ; ++-------------------+--------+----------+-----------------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "system:inst_cpu|altera_avalon_sc_fifo:pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" ; ++-------------------+--------+----------+-----------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++-------------------+--------+----------+-----------------------------------------------------------------------------------------+ +; csr_address ; Input ; Info ; Stuck at GND ; +; csr_read ; Input ; Info ; Stuck at GND ; +; csr_write ; Input ; Info ; Stuck at GND ; +; csr_readdata ; Output ; Info ; Explicitly unconnected ; +; csr_writedata ; Input ; Info ; Stuck at GND ; +; almost_full_data ; Output ; Info ; Explicitly unconnected ; +; almost_empty_data ; Output ; Info ; Explicitly unconnected ; +; in_empty ; Input ; Info ; Stuck at GND ; +; out_empty ; Output ; Info ; Explicitly unconnected ; +; in_error ; Input ; Info ; Stuck at GND ; +; out_error ; Output ; Info ; Explicitly unconnected ; +; in_channel ; Input ; Info ; Stuck at GND ; +; out_channel ; Output ; Info ; Explicitly unconnected ; ++-------------------+--------+----------+-----------------------------------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "system:inst_cpu|altera_avalon_sc_fifo:uart_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" ; ++-------------------+--------+----------+----------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++-------------------+--------+----------+----------------------------------------------------------------------------------------+ +; csr_address ; Input ; Info ; Stuck at GND ; +; csr_read ; Input ; Info ; Stuck at GND ; +; csr_write ; Input ; Info ; Stuck at GND ; +; csr_readdata ; Output ; Info ; Explicitly unconnected ; +; csr_writedata ; Input ; Info ; Stuck at GND ; +; almost_full_data ; Output ; Info ; Explicitly unconnected ; +; almost_empty_data ; Output ; Info ; Explicitly unconnected ; +; in_empty ; Input ; Info ; Stuck at GND ; +; out_empty ; Output ; Info ; Explicitly unconnected ; +; in_error ; Input ; Info ; Stuck at GND ; +; out_error ; Output ; Info ; Explicitly unconnected ; +; in_channel ; Input ; Info ; Stuck at GND ; +; out_channel ; Output ; Info ; Explicitly unconnected ; ++-------------------+--------+----------+----------------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "system:inst_cpu|altera_avalon_sc_fifo:sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" ; ++-------------------+--------+----------+-----------------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++-------------------+--------+----------+-----------------------------------------------------------------------------------------------+ +; csr_address ; Input ; Info ; Stuck at GND ; +; csr_read ; Input ; Info ; Stuck at GND ; +; csr_write ; Input ; Info ; Stuck at GND ; +; csr_readdata ; Output ; Info ; Explicitly unconnected ; +; csr_writedata ; Input ; Info ; Stuck at GND ; +; almost_full_data ; Output ; Info ; Explicitly unconnected ; +; almost_empty_data ; Output ; Info ; Explicitly unconnected ; +; in_empty ; Input ; Info ; Stuck at GND ; +; out_empty ; Output ; Info ; Explicitly unconnected ; +; in_error ; Input ; Info ; Stuck at GND ; +; out_error ; Output ; Info ; Explicitly unconnected ; +; in_channel ; Input ; Info ; Stuck at GND ; +; out_channel ; Output ; Info ; Explicitly unconnected ; ++-------------------+--------+----------+-----------------------------------------------------------------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "system:inst_cpu|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo" ; ++-------------------+--------+----------+--------------------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++-------------------+--------+----------+--------------------------------------------------------------------------------------------------+ +; csr_address ; Input ; Info ; Stuck at GND ; +; csr_read ; Input ; Info ; Stuck at GND ; +; csr_write ; Input ; Info ; Stuck at GND ; +; csr_readdata ; Output ; Info ; Explicitly unconnected ; +; csr_writedata ; Input ; Info ; Stuck at GND ; +; almost_full_data ; Output ; Info ; Explicitly unconnected ; +; almost_empty_data ; Output ; Info ; Explicitly unconnected ; +; in_empty ; Input ; Info ; Stuck at GND ; +; out_empty ; Output ; Info ; Explicitly unconnected ; +; in_error ; Input ; Info ; Stuck at GND ; +; out_error ; Output ; Info ; Explicitly unconnected ; +; in_channel ; Input ; Info ; Stuck at GND ; +; out_channel ; Output ; Info ; Explicitly unconnected ; ++-------------------+--------+----------+--------------------------------------------------------------------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" ; ++-------------------+--------+----------+---------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++-------------------+--------+----------+---------------------------------------------------------------------------------------+ +; csr_address ; Input ; Info ; Stuck at GND ; +; csr_read ; Input ; Info ; Stuck at GND ; +; csr_write ; Input ; Info ; Stuck at GND ; +; csr_readdata ; Output ; Info ; Explicitly unconnected ; +; csr_writedata ; Input ; Info ; Stuck at GND ; +; almost_full_data ; Output ; Info ; Explicitly unconnected ; +; almost_empty_data ; Output ; Info ; Explicitly unconnected ; +; in_empty ; Input ; Info ; Stuck at GND ; +; out_empty ; Output ; Info ; Explicitly unconnected ; +; in_error ; Input ; Info ; Stuck at GND ; +; out_error ; Output ; Info ; Explicitly unconnected ; +; in_channel ; Input ; Info ; Stuck at GND ; +; out_channel ; Output ; Info ; Explicitly unconnected ; ++-------------------+--------+----------+---------------------------------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "system:inst_cpu|altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo" ; ++-------------------+--------+----------+----------------------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++-------------------+--------+----------+----------------------------------------------------------------------------------------------------+ +; csr_address ; Input ; Info ; Stuck at GND ; +; csr_read ; Input ; Info ; Stuck at GND ; +; csr_write ; Input ; Info ; Stuck at GND ; +; csr_readdata ; Output ; Info ; Explicitly unconnected ; +; csr_writedata ; Input ; Info ; Stuck at GND ; +; almost_full_data ; Output ; Info ; Explicitly unconnected ; +; almost_empty_data ; Output ; Info ; Explicitly unconnected ; +; in_empty ; Input ; Info ; Stuck at GND ; +; out_empty ; Output ; Info ; Explicitly unconnected ; +; in_error ; Input ; Info ; Stuck at GND ; +; out_error ; Output ; Info ; Explicitly unconnected ; +; in_channel ; Input ; Info ; Stuck at GND ; +; out_channel ; Output ; Info ; Explicitly unconnected ; ++-------------------+--------+----------+----------------------------------------------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "system:inst_cpu|altera_merlin_slave_translator:rs232_motor_avalon_rs232_slave_translator" ; ++-----------------------+--------+----------+--------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++-----------------------+--------+----------+--------------------------------------------------------------------------+ +; av_begintransfer ; Output ; Info ; Explicitly unconnected ; +; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ; +; av_burstcount ; Output ; Info ; Explicitly unconnected ; +; av_readdatavalid ; Input ; Info ; Stuck at GND ; +; av_waitrequest ; Input ; Info ; Stuck at GND ; +; av_writebyteenable ; Output ; Info ; Explicitly unconnected ; +; av_lock ; Output ; Info ; Explicitly unconnected ; +; av_clken ; Output ; Info ; Explicitly unconnected ; +; uav_clken ; Input ; Info ; Stuck at GND ; +; av_debugaccess ; Output ; Info ; Explicitly unconnected ; +; av_outputenable ; Output ; Info ; Explicitly unconnected ; ++-----------------------+--------+----------+--------------------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "system:inst_cpu|altera_merlin_slave_translator:pio_motor_rst_s1_translator" ; ++-----------------------+--------+----------+------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++-----------------------+--------+----------+------------------------------------------------------------+ +; av_read ; Output ; Info ; Explicitly unconnected ; +; av_begintransfer ; Output ; Info ; Explicitly unconnected ; +; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ; +; av_burstcount ; Output ; Info ; Explicitly unconnected ; +; av_byteenable ; Output ; Info ; Explicitly unconnected ; +; av_readdatavalid ; Input ; Info ; Stuck at GND ; +; av_waitrequest ; Input ; Info ; Stuck at GND ; +; av_writebyteenable ; Output ; Info ; Explicitly unconnected ; +; av_lock ; Output ; Info ; Explicitly unconnected ; +; av_clken ; Output ; Info ; Explicitly unconnected ; +; uav_clken ; Input ; Info ; Stuck at GND ; +; av_debugaccess ; Output ; Info ; Explicitly unconnected ; +; av_outputenable ; Output ; Info ; Explicitly unconnected ; ++-----------------------+--------+----------+------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "system:inst_cpu|altera_merlin_slave_translator:jtag_uart_0_avalon_jtag_slave_translator" ; ++-----------------------+--------+----------+-------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++-----------------------+--------+----------+-------------------------------------------------------------------------+ +; av_begintransfer ; Output ; Info ; Explicitly unconnected ; +; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ; +; av_burstcount ; Output ; Info ; Explicitly unconnected ; +; av_byteenable ; Output ; Info ; Explicitly unconnected ; +; av_readdatavalid ; Input ; Info ; Stuck at GND ; +; av_writebyteenable ; Output ; Info ; Explicitly unconnected ; +; av_lock ; Output ; Info ; Explicitly unconnected ; +; av_clken ; Output ; Info ; Explicitly unconnected ; +; uav_clken ; Input ; Info ; Stuck at GND ; +; av_debugaccess ; Output ; Info ; Explicitly unconnected ; +; av_outputenable ; Output ; Info ; Explicitly unconnected ; ++-----------------------+--------+----------+-------------------------------------------------------------------------+ + + ++-------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "system:inst_cpu|altera_merlin_slave_translator:pio_sw_s1_translator" ; ++-----------------------+--------+----------+-----------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++-----------------------+--------+----------+-----------------------------------------------------+ +; av_write ; Output ; Info ; Explicitly unconnected ; +; av_read ; Output ; Info ; Explicitly unconnected ; +; av_writedata ; Output ; Info ; Explicitly unconnected ; +; av_begintransfer ; Output ; Info ; Explicitly unconnected ; +; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ; +; av_burstcount ; Output ; Info ; Explicitly unconnected ; +; av_byteenable ; Output ; Info ; Explicitly unconnected ; +; av_readdatavalid ; Input ; Info ; Stuck at GND ; +; av_waitrequest ; Input ; Info ; Stuck at GND ; +; av_writebyteenable ; Output ; Info ; Explicitly unconnected ; +; av_lock ; Output ; Info ; Explicitly unconnected ; +; av_chipselect ; Output ; Info ; Explicitly unconnected ; +; av_clken ; Output ; Info ; Explicitly unconnected ; +; uav_clken ; Input ; Info ; Stuck at GND ; +; av_debugaccess ; Output ; Info ; Explicitly unconnected ; +; av_outputenable ; Output ; Info ; Explicitly unconnected ; ++-----------------------+--------+----------+-----------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "system:inst_cpu|altera_merlin_slave_translator:pio_key_s1_translator" ; ++-----------------------+--------+----------+------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++-----------------------+--------+----------+------------------------------------------------------+ +; av_write ; Output ; Info ; Explicitly unconnected ; +; av_read ; Output ; Info ; Explicitly unconnected ; +; av_writedata ; Output ; Info ; Explicitly unconnected ; +; av_begintransfer ; Output ; Info ; Explicitly unconnected ; +; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ; +; av_burstcount ; Output ; Info ; Explicitly unconnected ; +; av_byteenable ; Output ; Info ; Explicitly unconnected ; +; av_readdatavalid ; Input ; Info ; Stuck at GND ; +; av_waitrequest ; Input ; Info ; Stuck at GND ; +; av_writebyteenable ; Output ; Info ; Explicitly unconnected ; +; av_lock ; Output ; Info ; Explicitly unconnected ; +; av_chipselect ; Output ; Info ; Explicitly unconnected ; +; av_clken ; Output ; Info ; Explicitly unconnected ; +; uav_clken ; Input ; Info ; Stuck at GND ; +; av_debugaccess ; Output ; Info ; Explicitly unconnected ; +; av_outputenable ; Output ; Info ; Explicitly unconnected ; ++-----------------------+--------+----------+------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "system:inst_cpu|altera_merlin_slave_translator:pio_led_s1_translator" ; ++-----------------------+--------+----------+------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++-----------------------+--------+----------+------------------------------------------------------+ +; av_read ; Output ; Info ; Explicitly unconnected ; +; av_begintransfer ; Output ; Info ; Explicitly unconnected ; +; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ; +; av_burstcount ; Output ; Info ; Explicitly unconnected ; +; av_byteenable ; Output ; Info ; Explicitly unconnected ; +; av_readdatavalid ; Input ; Info ; Stuck at GND ; +; av_waitrequest ; Input ; Info ; Stuck at GND ; +; av_writebyteenable ; Output ; Info ; Explicitly unconnected ; +; av_lock ; Output ; Info ; Explicitly unconnected ; +; av_clken ; Output ; Info ; Explicitly unconnected ; +; uav_clken ; Input ; Info ; Stuck at GND ; +; av_debugaccess ; Output ; Info ; Explicitly unconnected ; +; av_outputenable ; Output ; Info ; Explicitly unconnected ; ++-----------------------+--------+----------+------------------------------------------------------+ + + ++-------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "system:inst_cpu|altera_merlin_slave_translator:uart_0_s1_translator" ; ++-----------------------+--------+----------+-----------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++-----------------------+--------+----------+-----------------------------------------------------+ +; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ; +; av_burstcount ; Output ; Info ; Explicitly unconnected ; +; av_byteenable ; Output ; Info ; Explicitly unconnected ; +; av_readdatavalid ; Input ; Info ; Stuck at GND ; +; av_waitrequest ; Input ; Info ; Stuck at GND ; +; av_writebyteenable ; Output ; Info ; Explicitly unconnected ; +; av_lock ; Output ; Info ; Explicitly unconnected ; +; av_clken ; Output ; Info ; Explicitly unconnected ; +; uav_clken ; Input ; Info ; Stuck at GND ; +; av_debugaccess ; Output ; Info ; Explicitly unconnected ; +; av_outputenable ; Output ; Info ; Explicitly unconnected ; ++-----------------------+--------+----------+-----------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "system:inst_cpu|altera_merlin_slave_translator:sys_clk_timer_s1_translator" ; ++-----------------------+--------+----------+------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++-----------------------+--------+----------+------------------------------------------------------------+ +; av_read ; Output ; Info ; Explicitly unconnected ; +; av_begintransfer ; Output ; Info ; Explicitly unconnected ; +; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ; +; av_burstcount ; Output ; Info ; Explicitly unconnected ; +; av_byteenable ; Output ; Info ; Explicitly unconnected ; +; av_readdatavalid ; Input ; Info ; Stuck at GND ; +; av_waitrequest ; Input ; Info ; Stuck at GND ; +; av_writebyteenable ; Output ; Info ; Explicitly unconnected ; +; av_lock ; Output ; Info ; Explicitly unconnected ; +; av_clken ; Output ; Info ; Explicitly unconnected ; +; uav_clken ; Input ; Info ; Stuck at GND ; +; av_debugaccess ; Output ; Info ; Explicitly unconnected ; +; av_outputenable ; Output ; Info ; Explicitly unconnected ; ++-----------------------+--------+----------+------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "system:inst_cpu|altera_merlin_slave_translator:sysid_control_slave_translator" ; ++-----------------------+--------+----------+---------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++-----------------------+--------+----------+---------------------------------------------------------------+ +; av_write ; Output ; Info ; Explicitly unconnected ; +; av_read ; Output ; Info ; Explicitly unconnected ; +; av_writedata ; Output ; Info ; Explicitly unconnected ; +; av_begintransfer ; Output ; Info ; Explicitly unconnected ; +; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ; +; av_burstcount ; Output ; Info ; Explicitly unconnected ; +; av_byteenable ; Output ; Info ; Explicitly unconnected ; +; av_readdatavalid ; Input ; Info ; Stuck at GND ; +; av_waitrequest ; Input ; Info ; Stuck at GND ; +; av_writebyteenable ; Output ; Info ; Explicitly unconnected ; +; av_lock ; Output ; Info ; Explicitly unconnected ; +; av_chipselect ; Output ; Info ; Explicitly unconnected ; +; av_clken ; Output ; Info ; Explicitly unconnected ; +; uav_clken ; Input ; Info ; Stuck at GND ; +; av_debugaccess ; Output ; Info ; Explicitly unconnected ; +; av_outputenable ; Output ; Info ; Explicitly unconnected ; ++-----------------------+--------+----------+---------------------------------------------------------------+ + + ++------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "system:inst_cpu|altera_merlin_slave_translator:sdram_s1_translator" ; ++-----------------------+--------+----------+----------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++-----------------------+--------+----------+----------------------------------------------------+ +; av_begintransfer ; Output ; Info ; Explicitly unconnected ; +; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ; +; av_burstcount ; Output ; Info ; Explicitly unconnected ; +; av_writebyteenable ; Output ; Info ; Explicitly unconnected ; +; av_lock ; Output ; Info ; Explicitly unconnected ; +; av_clken ; Output ; Info ; Explicitly unconnected ; +; uav_clken ; Input ; Info ; Stuck at GND ; +; av_debugaccess ; Output ; Info ; Explicitly unconnected ; +; av_outputenable ; Output ; Info ; Explicitly unconnected ; ++-----------------------+--------+----------+----------------------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "system:inst_cpu|altera_merlin_slave_translator:cpu_jtag_debug_module_translator" ; ++-----------------------+--------+----------+-----------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++-----------------------+--------+----------+-----------------------------------------------------------------+ +; av_read ; Output ; Info ; Explicitly unconnected ; +; av_beginbursttransfer ; Output ; Info ; Explicitly unconnected ; +; av_burstcount ; Output ; Info ; Explicitly unconnected ; +; av_readdatavalid ; Input ; Info ; Stuck at GND ; +; av_waitrequest ; Input ; Info ; Stuck at GND ; +; av_writebyteenable ; Output ; Info ; Explicitly unconnected ; +; av_lock ; Output ; Info ; Explicitly unconnected ; +; av_clken ; Output ; Info ; Explicitly unconnected ; +; uav_clken ; Input ; Info ; Stuck at GND ; +; av_outputenable ; Output ; Info ; Explicitly unconnected ; ++-----------------------+--------+----------+-----------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "system:inst_cpu|altera_merlin_master_translator:cpu_data_master_translator" ; ++-----------------------+--------+----------+------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++-----------------------+--------+----------+------------------------------------------------------------+ +; av_burstcount ; Input ; Info ; Stuck at VCC ; +; av_beginbursttransfer ; Input ; Info ; Stuck at GND ; +; av_begintransfer ; Input ; Info ; Stuck at GND ; +; av_chipselect ; Input ; Info ; Stuck at GND ; +; av_lock ; Input ; Info ; Stuck at GND ; +; uav_clken ; Output ; Info ; Explicitly unconnected ; +; av_clken ; Input ; Info ; Stuck at VCC ; ++-----------------------+--------+----------+------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "system:inst_cpu|altera_merlin_master_translator:cpu_instruction_master_translator" ; ++-----------------------+--------+----------+-------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++-----------------------+--------+----------+-------------------------------------------------------------------+ +; av_burstcount ; Input ; Info ; Stuck at VCC ; +; av_byteenable ; Input ; Info ; Stuck at VCC ; +; av_beginbursttransfer ; Input ; Info ; Stuck at GND ; +; av_begintransfer ; Input ; Info ; Stuck at GND ; +; av_chipselect ; Input ; Info ; Stuck at GND ; +; av_write ; Input ; Info ; Stuck at GND ; +; av_writedata ; Input ; Info ; Stuck at GND ; +; av_lock ; Input ; Info ; Stuck at GND ; +; av_debugaccess ; Input ; Info ; Stuck at GND ; +; uav_clken ; Output ; Info ; Explicitly unconnected ; +; av_clken ; Input ; Info ; Stuck at VCC ; ++-----------------------+--------+----------+-------------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_rs232_counters:RS232_Out_Counters" ; ++-------------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++-------------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------+ +; baud_clock_falling_edge ; Output ; Info ; Explicitly unconnected ; ++-------------------------+--------+----------+------------------------------------------------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_rs232_counters:RS232_In_Counters" ; ++------------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++------------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------+ +; baud_clock_rising_edge ; Output ; Info ; Explicitly unconnected ; ++------------------------+--------+----------+--------------------------------------------------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic" ; ++----------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++----------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+ +; raw_tck ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ; +; tck ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ; +; tdi ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ; +; rti ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ; +; shift ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ; +; update ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ; +; usr1 ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ; +; clr ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ; +; ena ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ; +; ir_in ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ; +; tdo ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; +; irq ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; +; ir_out ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; +; jtag_state_cdr ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ; +; jtag_state_sdr ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ; +; jtag_state_udr ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ; ++----------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "system:inst_cpu|system_jtag_uart_0:jtag_uart_0" ; ++---------------+--------+----------+----------------------------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++---------------+--------+----------+----------------------------------------------------------------------------------------------------------+ +; dataavailable ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; +; readyfordata ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; ++---------------+--------+----------+----------------------------------------------------------------------------------------------------------+ + + ++------------------------------------------------------------------+ +; Port Connectivity Checks: "system:inst_cpu|system_uart_0:uart_0" ; ++---------------+--------+----------+------------------------------+ +; Port ; Type ; Severity ; Details ; ++---------------+--------+----------+------------------------------+ +; dataavailable ; Output ; Info ; Explicitly unconnected ; +; readyfordata ; Output ; Info ; Explicitly unconnected ; ++---------------+--------+----------+------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module" ; ++--------------+--------+----------+-------------------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++--------------+--------+----------+-------------------------------------------------------------------------------------------------+ +; almost_empty ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; almost_full ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ++--------------+--------+----------+-------------------------------------------------------------------------------------------------+ + + ++------------------------------------------------------------+ +; Port Connectivity Checks: "system:inst_cpu|system_cpu:cpu" ; ++--------------+--------+----------+-------------------------+ +; Port ; Type ; Severity ; Details ; ++--------------+--------+----------+-------------------------+ +; no_ci_readra ; Output ; Info ; Explicitly unconnected ; ++--------------+--------+----------+-------------------------+ + + ++-------------------------------+ +; Elapsed Time Per Partition ; ++----------------+--------------+ +; Partition Name ; Elapsed Time ; ++----------------+--------------+ +; Top ; 00:00:11 ; ++----------------+--------------+ + + ++-------------------------------+ +; Analysis & Synthesis Messages ; ++-------------------------------+ +Info: ******************************************************************* +Info: Running Quartus II 64-Bit Analysis & Synthesis + Info: Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Full Version + Info: Processing started: Fri Mar 14 16:48:29 2014 +Info: Command: quartus_map --read_settings_files=on --write_settings_files=off de0_nano_system -c de0_nano_system +Info (11104): Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead. +Info (12021): Found 2 design units, including 1 entities, in source file de0_nano_system.vhd + Info (12022): Found design unit 1: de0_nano_system-syn + Info (12023): Found entity 1: de0_nano_system +Info (12021): Found 2 design units, including 1 entities, in source file heartbeat.vhd + Info (12022): Found design unit 1: heartbeat-syn + Info (12023): Found entity 1: heartbeat +Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/system.v + Info (12023): Found entity 1: system +Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_irq_mapper.sv + Info (12023): Found entity 1: system_irq_mapper +Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_width_adapter.sv + Info (12023): Found entity 1: altera_merlin_width_adapter +Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_burst_uncompressor.sv + Info (12023): Found entity 1: altera_merlin_burst_uncompressor +Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_address_alignment.sv + Info (12023): Found entity 1: altera_merlin_address_alignment +Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/altera_merlin_arbitrator.sv + Info (12023): Found entity 1: altera_merlin_arbitrator + Info (12023): Found entity 2: altera_merlin_arb_adder +Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_rsp_xbar_mux_001.sv + Info (12023): Found entity 1: system_rsp_xbar_mux_001 +Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_rsp_xbar_mux.sv + Info (12023): Found entity 1: system_rsp_xbar_mux +Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_rsp_xbar_demux_002.sv + Info (12023): Found entity 1: system_rsp_xbar_demux_002 +Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_rsp_xbar_demux.sv + Info (12023): Found entity 1: system_rsp_xbar_demux +Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_cmd_xbar_mux.sv + Info (12023): Found entity 1: system_cmd_xbar_mux +Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_cmd_xbar_demux_001.sv + Info (12023): Found entity 1: system_cmd_xbar_demux_001 +Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_cmd_xbar_demux.sv + Info (12023): Found entity 1: system_cmd_xbar_demux +Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_reset_controller.v + Info (12023): Found entity 1: altera_reset_controller +Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_reset_synchronizer.v + Info (12023): Found entity 1: altera_reset_synchronizer +Info (12021): Found 7 design units, including 7 entities, in source file system/synthesis/submodules/altera_merlin_burst_adapter.sv + Info (12023): Found entity 1: altera_merlin_burst_adapter_burstwrap_increment + Info (12023): Found entity 2: altera_merlin_burst_adapter_adder + Info (12023): Found entity 3: altera_merlin_burst_adapter_subtractor + Info (12023): Found entity 4: altera_merlin_burst_adapter_min + Info (12023): Found entity 5: altera_merlin_burst_adapter + Info (12023): Found entity 6: altera_merlin_burst_adapter_uncompressed_only + Info (12023): Found entity 7: altera_merlin_burst_adapter_full +Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_traffic_limiter.sv + Info (12023): Found entity 1: altera_merlin_traffic_limiter +Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_avalon_st_pipeline_base.v + Info (12023): Found entity 1: altera_avalon_st_pipeline_base +Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_id_router_002.sv + Info (12023): Found entity 1: system_id_router_002_default_decode + Info (12023): Found entity 2: system_id_router_002 +Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_id_router_001.sv + Info (12023): Found entity 1: system_id_router_001_default_decode + Info (12023): Found entity 2: system_id_router_001 +Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_id_router.sv + Info (12023): Found entity 1: system_id_router_default_decode + Info (12023): Found entity 2: system_id_router +Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_addr_router_001.sv + Info (12023): Found entity 1: system_addr_router_001_default_decode + Info (12023): Found entity 2: system_addr_router_001 +Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_addr_router.sv + Info (12023): Found entity 1: system_addr_router_default_decode + Info (12023): Found entity 2: system_addr_router +Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_avalon_sc_fifo.v + Info (12023): Found entity 1: altera_avalon_sc_fifo +Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_slave_agent.sv + Info (12023): Found entity 1: altera_merlin_slave_agent +Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_master_agent.sv + Info (12023): Found entity 1: altera_merlin_master_agent +Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_slave_translator.sv + Info (12023): Found entity 1: altera_merlin_slave_translator +Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_master_translator.sv + Info (12023): Found entity 1: altera_merlin_master_translator +Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_up_rs232_counters.v + Info (12023): Found entity 1: altera_up_rs232_counters +Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_up_rs232_in_deserializer.v + Info (12023): Found entity 1: altera_up_rs232_in_deserializer +Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_up_rs232_out_serializer.v + Info (12023): Found entity 1: altera_up_rs232_out_serializer +Warning (10275): Verilog HDL Module Instantiation warning at altera_up_sync_fifo.v(157): ignored dangling comma in List of Port Connections +Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_up_sync_fifo.v + Info (12023): Found entity 1: altera_up_sync_fifo +Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_rs232_motor.v + Info (12023): Found entity 1: system_rs232_motor +Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_pio_motor_rst.v + Info (12023): Found entity 1: system_pio_motor_rst +Info (12021): Found 7 design units, including 7 entities, in source file system/synthesis/submodules/system_jtag_uart_0.v + Info (12023): Found entity 1: system_jtag_uart_0_log_module + Info (12023): Found entity 2: system_jtag_uart_0_sim_scfifo_w + Info (12023): Found entity 3: system_jtag_uart_0_scfifo_w + Info (12023): Found entity 4: system_jtag_uart_0_drom_module + Info (12023): Found entity 5: system_jtag_uart_0_sim_scfifo_r + Info (12023): Found entity 6: system_jtag_uart_0_scfifo_r + Info (12023): Found entity 7: system_jtag_uart_0 +Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_pio_sw.v + Info (12023): Found entity 1: system_pio_sw +Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_pio_key.v + Info (12023): Found entity 1: system_pio_key +Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_pio_led.v + Info (12023): Found entity 1: system_pio_led +Info (12021): Found 7 design units, including 7 entities, in source file system/synthesis/submodules/system_uart_0.v + Info (12023): Found entity 1: system_uart_0_log_module + Info (12023): Found entity 2: system_uart_0_tx + Info (12023): Found entity 3: system_uart_0_rx_stimulus_source_character_source_rom_module + Info (12023): Found entity 4: system_uart_0_rx_stimulus_source + Info (12023): Found entity 5: system_uart_0_rx + Info (12023): Found entity 6: system_uart_0_regs + Info (12023): Found entity 7: system_uart_0 +Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_sys_clk_timer.v + Info (12023): Found entity 1: system_sys_clk_timer +Info (12021): Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_sdram.v + Info (12023): Found entity 1: system_sdram_input_efifo_module + Info (12023): Found entity 2: system_sdram +Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_sysid.v + Info (12023): Found entity 1: system_sysid +Info (12021): Found 28 design units, including 28 entities, in source file system/synthesis/submodules/system_cpu.v + Info (12023): Found entity 1: system_cpu_ic_data_module + Info (12023): Found entity 2: system_cpu_ic_tag_module + Info (12023): Found entity 3: system_cpu_bht_module + Info (12023): Found entity 4: system_cpu_register_bank_a_module + Info (12023): Found entity 5: system_cpu_register_bank_b_module + Info (12023): Found entity 6: system_cpu_dc_tag_module + Info (12023): Found entity 7: system_cpu_dc_data_module + Info (12023): Found entity 8: system_cpu_dc_victim_module + Info (12023): Found entity 9: system_cpu_nios2_oci_debug + Info (12023): Found entity 10: system_cpu_ociram_lpm_dram_bdp_component_module + Info (12023): Found entity 11: system_cpu_nios2_ocimem + Info (12023): Found entity 12: system_cpu_nios2_avalon_reg + Info (12023): Found entity 13: system_cpu_nios2_oci_break + Info (12023): Found entity 14: system_cpu_nios2_oci_xbrk + Info (12023): Found entity 15: system_cpu_nios2_oci_dbrk + Info (12023): Found entity 16: system_cpu_nios2_oci_itrace + Info (12023): Found entity 17: system_cpu_nios2_oci_td_mode + Info (12023): Found entity 18: system_cpu_nios2_oci_dtrace + Info (12023): Found entity 19: system_cpu_nios2_oci_compute_tm_count + Info (12023): Found entity 20: system_cpu_nios2_oci_fifowp_inc + Info (12023): Found entity 21: system_cpu_nios2_oci_fifocount_inc + Info (12023): Found entity 22: system_cpu_nios2_oci_fifo + Info (12023): Found entity 23: system_cpu_nios2_oci_pib + Info (12023): Found entity 24: system_cpu_traceram_lpm_dram_bdp_component_module + Info (12023): Found entity 25: system_cpu_nios2_oci_im + Info (12023): Found entity 26: system_cpu_nios2_performance_monitors + Info (12023): Found entity 27: system_cpu_nios2_oci + Info (12023): Found entity 28: system_cpu +Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_cpu_jtag_debug_module_sysclk.v + Info (12023): Found entity 1: system_cpu_jtag_debug_module_sysclk +Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_cpu_jtag_debug_module_tck.v + Info (12023): Found entity 1: system_cpu_jtag_debug_module_tck +Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v + Info (12023): Found entity 1: system_cpu_jtag_debug_module_wrapper +Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_cpu_mult_cell.v + Info (12023): Found entity 1: system_cpu_mult_cell +Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_cpu_oci_test_bench.v + Info (12023): Found entity 1: system_cpu_oci_test_bench +Info (12021): Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_cpu_test_bench.v + Info (12023): Found entity 1: system_cpu_test_bench +Info (12021): Found 2 design units, including 1 entities, in source file pll_sys.vhd + Info (12022): Found design unit 1: pll_sys-SYN + Info (12023): Found entity 1: pll_sys +Warning (10037): Verilog HDL or VHDL warning at system_cpu.v(2066): conditional expression evaluates to a constant +Warning (10037): Verilog HDL or VHDL warning at system_cpu.v(2068): conditional expression evaluates to a constant +Warning (10037): Verilog HDL or VHDL warning at system_cpu.v(2224): conditional expression evaluates to a constant +Warning (10037): Verilog HDL or VHDL warning at system_cpu.v(3143): conditional expression evaluates to a constant +Warning (10037): Verilog HDL or VHDL warning at system_sdram.v(316): conditional expression evaluates to a constant +Warning (10037): Verilog HDL or VHDL warning at system_sdram.v(326): conditional expression evaluates to a constant +Warning (10037): Verilog HDL or VHDL warning at system_sdram.v(336): conditional expression evaluates to a constant +Warning (10037): Verilog HDL or VHDL warning at system_sdram.v(680): conditional expression evaluates to a constant +Info (12127): Elaborating entity "de0_nano_system" for the top level hierarchy +Info (12128): Elaborating entity "pll_sys" for hierarchy "pll_sys:inst_pll_sys" +Info (12128): Elaborating entity "altpll" for hierarchy "pll_sys:inst_pll_sys|altpll:altpll_component" +Info (12130): Elaborated megafunction instantiation "pll_sys:inst_pll_sys|altpll:altpll_component" +Info (12133): Instantiated megafunction "pll_sys:inst_pll_sys|altpll:altpll_component" with the following parameter: + Info (12134): Parameter "bandwidth_type" = "AUTO" + Info (12134): Parameter "clk0_divide_by" = "1" + Info (12134): Parameter "clk0_duty_cycle" = "50" + Info (12134): Parameter "clk0_multiply_by" = "2" + Info (12134): Parameter "clk0_phase_shift" = "0" + Info (12134): Parameter "clk1_divide_by" = "1" + Info (12134): Parameter "clk1_duty_cycle" = "50" + Info (12134): Parameter "clk1_multiply_by" = "2" + Info (12134): Parameter "clk1_phase_shift" = "-1500" + Info (12134): Parameter "clk2_divide_by" = "5" + Info (12134): Parameter "clk2_duty_cycle" = "50" + Info (12134): Parameter "clk2_multiply_by" = "1" + Info (12134): Parameter "clk2_phase_shift" = "0" + Info (12134): Parameter "compensate_clock" = "CLK0" + Info (12134): Parameter "inclk0_input_frequency" = "20000" + Info (12134): Parameter "intended_device_family" = "Cyclone IV E" + Info (12134): Parameter "lpm_hint" = "CBX_MODULE_PREFIX=pll_sys" + Info (12134): Parameter "lpm_type" = "altpll" + Info (12134): Parameter "operation_mode" = "NORMAL" + Info (12134): Parameter "pll_type" = "AUTO" + Info (12134): Parameter "port_activeclock" = "PORT_UNUSED" + Info (12134): Parameter "port_areset" = "PORT_UNUSED" + Info (12134): Parameter "port_clkbad0" = "PORT_UNUSED" + Info (12134): Parameter "port_clkbad1" = "PORT_UNUSED" + Info (12134): Parameter "port_clkloss" = "PORT_UNUSED" + Info (12134): Parameter "port_clkswitch" = "PORT_UNUSED" + Info (12134): Parameter "port_configupdate" = "PORT_UNUSED" + Info (12134): Parameter "port_fbin" = "PORT_UNUSED" + Info (12134): Parameter "port_inclk0" = "PORT_USED" + Info (12134): Parameter "port_inclk1" = "PORT_UNUSED" + Info (12134): Parameter "port_locked" = "PORT_USED" + Info (12134): Parameter "port_pfdena" = "PORT_UNUSED" + Info (12134): Parameter "port_phasecounterselect" = "PORT_UNUSED" + Info (12134): Parameter "port_phasedone" = "PORT_UNUSED" + Info (12134): Parameter "port_phasestep" = "PORT_UNUSED" + Info (12134): Parameter "port_phaseupdown" = "PORT_UNUSED" + Info (12134): Parameter "port_pllena" = "PORT_UNUSED" + Info (12134): Parameter "port_scanaclr" = "PORT_UNUSED" + Info (12134): Parameter "port_scanclk" = "PORT_UNUSED" + Info (12134): Parameter "port_scanclkena" = "PORT_UNUSED" + Info (12134): Parameter "port_scandata" = "PORT_UNUSED" + Info (12134): Parameter "port_scandataout" = "PORT_UNUSED" + Info (12134): Parameter "port_scandone" = "PORT_UNUSED" + Info (12134): Parameter "port_scanread" = "PORT_UNUSED" + Info (12134): Parameter "port_scanwrite" = "PORT_UNUSED" + Info (12134): Parameter "port_clk0" = "PORT_USED" + Info (12134): Parameter "port_clk1" = "PORT_USED" + Info (12134): Parameter "port_clk2" = "PORT_USED" + Info (12134): Parameter "port_clk3" = "PORT_UNUSED" + Info (12134): Parameter "port_clk4" = "PORT_UNUSED" + Info (12134): Parameter "port_clk5" = "PORT_UNUSED" + Info (12134): Parameter "port_clkena0" = "PORT_UNUSED" + Info (12134): Parameter "port_clkena1" = "PORT_UNUSED" + Info (12134): Parameter "port_clkena2" = "PORT_UNUSED" + Info (12134): Parameter "port_clkena3" = "PORT_UNUSED" + Info (12134): Parameter "port_clkena4" = "PORT_UNUSED" + Info (12134): Parameter "port_clkena5" = "PORT_UNUSED" + Info (12134): Parameter "port_extclk0" = "PORT_UNUSED" + Info (12134): Parameter "port_extclk1" = "PORT_UNUSED" + Info (12134): Parameter "port_extclk2" = "PORT_UNUSED" + Info (12134): Parameter "port_extclk3" = "PORT_UNUSED" + Info (12134): Parameter "self_reset_on_loss_lock" = "ON" + Info (12134): Parameter "width_clock" = "5" +Info (12021): Found 1 design units, including 1 entities, in source file db/pll_sys_altpll.v + Info (12023): Found entity 1: pll_sys_altpll +Info (12128): Elaborating entity "pll_sys_altpll" for hierarchy "pll_sys:inst_pll_sys|altpll:altpll_component|pll_sys_altpll:auto_generated" +Info (12128): Elaborating entity "heartbeat" for hierarchy "heartbeat:inst_heartbeat" +Info (12128): Elaborating entity "system" for hierarchy "system:inst_cpu" +Info (12128): Elaborating entity "system_cpu" for hierarchy "system:inst_cpu|system_cpu:cpu" +Info (12128): Elaborating entity "system_cpu_test_bench" for hierarchy "system:inst_cpu|system_cpu:cpu|system_cpu_test_bench:the_system_cpu_test_bench" +Info (12128): Elaborating entity "system_cpu_ic_data_module" for hierarchy "system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data" +Info (12128): Elaborating entity "altsyncram" for hierarchy "system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram" +Info (12130): Elaborated megafunction instantiation "system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram" +Info (12133): Instantiated megafunction "system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram" with the following parameter: + Info (12134): Parameter "address_reg_b" = "CLOCK0" + Info (12134): Parameter "maximum_depth" = "0" + Info (12134): Parameter "numwords_a" = "2048" + Info (12134): Parameter "numwords_b" = "2048" + Info (12134): Parameter "operation_mode" = "DUAL_PORT" + Info (12134): Parameter "outdata_reg_b" = "UNREGISTERED" + Info (12134): Parameter "ram_block_type" = "AUTO" + Info (12134): Parameter "rdcontrol_reg_b" = "CLOCK0" + Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE" + Info (12134): Parameter "width_a" = "32" + Info (12134): Parameter "width_b" = "32" + Info (12134): Parameter "widthad_a" = "11" + Info (12134): Parameter "widthad_b" = "11" +Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_sjd1.tdf + Info (12023): Found entity 1: altsyncram_sjd1 +Info (12128): Elaborating entity "altsyncram_sjd1" for hierarchy "system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated" +Info (12128): Elaborating entity "system_cpu_ic_tag_module" for hierarchy "system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag" +Info (12128): Elaborating entity "altsyncram" for hierarchy "system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram" +Info (12130): Elaborated megafunction instantiation "system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram" +Info (12133): Instantiated megafunction "system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram" with the following parameter: + Info (12134): Parameter "address_reg_b" = "CLOCK0" + Info (12134): Parameter "init_file" = "system_cpu_ic_tag_ram.mif" + Info (12134): Parameter "maximum_depth" = "0" + Info (12134): Parameter "numwords_a" = "256" + Info (12134): Parameter "numwords_b" = "256" + Info (12134): Parameter "operation_mode" = "DUAL_PORT" + Info (12134): Parameter "outdata_reg_b" = "UNREGISTERED" + Info (12134): Parameter "ram_block_type" = "AUTO" + Info (12134): Parameter "rdcontrol_reg_b" = "CLOCK0" + Info (12134): Parameter "read_during_write_mode_mixed_ports" = "OLD_DATA" + Info (12134): Parameter "width_a" = "21" + Info (12134): Parameter "width_b" = "21" + Info (12134): Parameter "widthad_a" = "8" + Info (12134): Parameter "widthad_b" = "8" +Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_qtg1.tdf + Info (12023): Found entity 1: altsyncram_qtg1 +Info (12128): Elaborating entity "altsyncram_qtg1" for hierarchy "system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated" +Info (12128): Elaborating entity "system_cpu_bht_module" for hierarchy "system:inst_cpu|system_cpu:cpu|system_cpu_bht_module:system_cpu_bht" +Info (12128): Elaborating entity "altsyncram" for hierarchy "system:inst_cpu|system_cpu:cpu|system_cpu_bht_module:system_cpu_bht|altsyncram:the_altsyncram" +Info (12130): Elaborated megafunction instantiation "system:inst_cpu|system_cpu:cpu|system_cpu_bht_module:system_cpu_bht|altsyncram:the_altsyncram" +Info (12133): Instantiated megafunction "system:inst_cpu|system_cpu:cpu|system_cpu_bht_module:system_cpu_bht|altsyncram:the_altsyncram" with the following parameter: + Info (12134): Parameter "address_reg_b" = "CLOCK0" + Info (12134): Parameter "init_file" = "system_cpu_bht_ram.mif" + Info (12134): Parameter "maximum_depth" = "0" + Info (12134): Parameter "numwords_a" = "256" + Info (12134): Parameter "numwords_b" = "256" + Info (12134): Parameter "operation_mode" = "DUAL_PORT" + Info (12134): Parameter "outdata_reg_b" = "UNREGISTERED" + Info (12134): Parameter "ram_block_type" = "AUTO" + Info (12134): Parameter "rdcontrol_reg_b" = "CLOCK0" + Info (12134): Parameter "read_during_write_mode_mixed_ports" = "OLD_DATA" + Info (12134): Parameter "width_a" = "2" + Info (12134): Parameter "width_b" = "2" + Info (12134): Parameter "widthad_a" = "8" + Info (12134): Parameter "widthad_b" = "8" +Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_fhg1.tdf + Info (12023): Found entity 1: altsyncram_fhg1 +Info (12128): Elaborating entity "altsyncram_fhg1" for hierarchy "system:inst_cpu|system_cpu:cpu|system_cpu_bht_module:system_cpu_bht|altsyncram:the_altsyncram|altsyncram_fhg1:auto_generated" +Info (12128): Elaborating entity "system_cpu_register_bank_a_module" for hierarchy "system:inst_cpu|system_cpu:cpu|system_cpu_register_bank_a_module:system_cpu_register_bank_a" +Info (12128): Elaborating entity "altsyncram" for hierarchy "system:inst_cpu|system_cpu:cpu|system_cpu_register_bank_a_module:system_cpu_register_bank_a|altsyncram:the_altsyncram" +Info (12130): Elaborated megafunction instantiation "system:inst_cpu|system_cpu:cpu|system_cpu_register_bank_a_module:system_cpu_register_bank_a|altsyncram:the_altsyncram" +Info (12133): Instantiated megafunction "system:inst_cpu|system_cpu:cpu|system_cpu_register_bank_a_module:system_cpu_register_bank_a|altsyncram:the_altsyncram" with the following parameter: + Info (12134): Parameter "address_reg_b" = "CLOCK0" + Info (12134): Parameter "init_file" = "system_cpu_rf_ram_a.mif" + Info (12134): Parameter "maximum_depth" = "0" + Info (12134): Parameter "numwords_a" = "32" + Info (12134): Parameter "numwords_b" = "32" + Info (12134): Parameter "operation_mode" = "DUAL_PORT" + Info (12134): Parameter "outdata_reg_b" = "UNREGISTERED" + Info (12134): Parameter "ram_block_type" = "AUTO" + Info (12134): Parameter "rdcontrol_reg_b" = "CLOCK0" + Info (12134): Parameter "read_during_write_mode_mixed_ports" = "OLD_DATA" + Info (12134): Parameter "width_a" = "32" + Info (12134): Parameter "width_b" = "32" + Info (12134): Parameter "widthad_a" = "5" + Info (12134): Parameter "widthad_b" = "5" +Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_fvf1.tdf + Info (12023): Found entity 1: altsyncram_fvf1 +Info (12128): Elaborating entity "altsyncram_fvf1" for hierarchy "system:inst_cpu|system_cpu:cpu|system_cpu_register_bank_a_module:system_cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_fvf1:auto_generated" +Info (12128): Elaborating entity "system_cpu_register_bank_b_module" for hierarchy "system:inst_cpu|system_cpu:cpu|system_cpu_register_bank_b_module:system_cpu_register_bank_b" +Info (12128): Elaborating entity "altsyncram" for hierarchy "system:inst_cpu|system_cpu:cpu|system_cpu_register_bank_b_module:system_cpu_register_bank_b|altsyncram:the_altsyncram" +Info (12130): Elaborated megafunction instantiation "system:inst_cpu|system_cpu:cpu|system_cpu_register_bank_b_module:system_cpu_register_bank_b|altsyncram:the_altsyncram" +Info (12133): Instantiated megafunction "system:inst_cpu|system_cpu:cpu|system_cpu_register_bank_b_module:system_cpu_register_bank_b|altsyncram:the_altsyncram" with the following parameter: + Info (12134): Parameter "address_reg_b" = "CLOCK0" + Info (12134): Parameter "init_file" = "system_cpu_rf_ram_b.mif" + Info (12134): Parameter "maximum_depth" = "0" + Info (12134): Parameter "numwords_a" = "32" + Info (12134): Parameter "numwords_b" = "32" + Info (12134): Parameter "operation_mode" = "DUAL_PORT" + Info (12134): Parameter "outdata_reg_b" = "UNREGISTERED" + Info (12134): Parameter "ram_block_type" = "AUTO" + Info (12134): Parameter "rdcontrol_reg_b" = "CLOCK0" + Info (12134): Parameter "read_during_write_mode_mixed_ports" = "OLD_DATA" + Info (12134): Parameter "width_a" = "32" + Info (12134): Parameter "width_b" = "32" + Info (12134): Parameter "widthad_a" = "5" + Info (12134): Parameter "widthad_b" = "5" +Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_gvf1.tdf + Info (12023): Found entity 1: altsyncram_gvf1 +Info (12128): Elaborating entity "altsyncram_gvf1" for hierarchy "system:inst_cpu|system_cpu:cpu|system_cpu_register_bank_b_module:system_cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_gvf1:auto_generated" +Info (12128): Elaborating entity "system_cpu_dc_tag_module" for hierarchy "system:inst_cpu|system_cpu:cpu|system_cpu_dc_tag_module:system_cpu_dc_tag" +Info (12128): Elaborating entity "altsyncram" for hierarchy "system:inst_cpu|system_cpu:cpu|system_cpu_dc_tag_module:system_cpu_dc_tag|altsyncram:the_altsyncram" +Info (12130): Elaborated megafunction instantiation "system:inst_cpu|system_cpu:cpu|system_cpu_dc_tag_module:system_cpu_dc_tag|altsyncram:the_altsyncram" +Info (12133): Instantiated megafunction "system:inst_cpu|system_cpu:cpu|system_cpu_dc_tag_module:system_cpu_dc_tag|altsyncram:the_altsyncram" with the following parameter: + Info (12134): Parameter "address_reg_b" = "CLOCK0" + Info (12134): Parameter "init_file" = "system_cpu_dc_tag_ram.mif" + Info (12134): Parameter "maximum_depth" = "0" + Info (12134): Parameter "numwords_a" = "128" + Info (12134): Parameter "numwords_b" = "128" + Info (12134): Parameter "operation_mode" = "DUAL_PORT" + Info (12134): Parameter "outdata_reg_b" = "UNREGISTERED" + Info (12134): Parameter "ram_block_type" = "AUTO" + Info (12134): Parameter "rdcontrol_reg_b" = "CLOCK0" + Info (12134): Parameter "read_during_write_mode_mixed_ports" = "OLD_DATA" + Info (12134): Parameter "width_a" = "16" + Info (12134): Parameter "width_b" = "16" + Info (12134): Parameter "widthad_a" = "7" + Info (12134): Parameter "widthad_b" = "7" +Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_d9g1.tdf + Info (12023): Found entity 1: altsyncram_d9g1 +Info (12128): Elaborating entity "altsyncram_d9g1" for hierarchy "system:inst_cpu|system_cpu:cpu|system_cpu_dc_tag_module:system_cpu_dc_tag|altsyncram:the_altsyncram|altsyncram_d9g1:auto_generated" +Info (12128): Elaborating entity "system_cpu_dc_data_module" for hierarchy "system:inst_cpu|system_cpu:cpu|system_cpu_dc_data_module:system_cpu_dc_data" +Info (12128): Elaborating entity "altsyncram" for hierarchy "system:inst_cpu|system_cpu:cpu|system_cpu_dc_data_module:system_cpu_dc_data|altsyncram:the_altsyncram" +Info (12130): Elaborated megafunction instantiation "system:inst_cpu|system_cpu:cpu|system_cpu_dc_data_module:system_cpu_dc_data|altsyncram:the_altsyncram" +Info (12133): Instantiated megafunction "system:inst_cpu|system_cpu:cpu|system_cpu_dc_data_module:system_cpu_dc_data|altsyncram:the_altsyncram" with the following parameter: + Info (12134): Parameter "address_reg_b" = "CLOCK0" + Info (12134): Parameter "maximum_depth" = "0" + Info (12134): Parameter "numwords_a" = "1024" + Info (12134): Parameter "numwords_b" = "1024" + Info (12134): Parameter "operation_mode" = "DUAL_PORT" + Info (12134): Parameter "outdata_reg_b" = "UNREGISTERED" + Info (12134): Parameter "ram_block_type" = "AUTO" + Info (12134): Parameter "rdcontrol_reg_b" = "CLOCK0" + Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE" + Info (12134): Parameter "width_a" = "32" + Info (12134): Parameter "width_b" = "32" + Info (12134): Parameter "width_byteena_a" = "4" + Info (12134): Parameter "widthad_a" = "10" + Info (12134): Parameter "widthad_b" = "10" +Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_2jf1.tdf + Info (12023): Found entity 1: altsyncram_2jf1 +Info (12128): Elaborating entity "altsyncram_2jf1" for hierarchy "system:inst_cpu|system_cpu:cpu|system_cpu_dc_data_module:system_cpu_dc_data|altsyncram:the_altsyncram|altsyncram_2jf1:auto_generated" +Info (12128): Elaborating entity "system_cpu_dc_victim_module" for hierarchy "system:inst_cpu|system_cpu:cpu|system_cpu_dc_victim_module:system_cpu_dc_victim" +Info (12128): Elaborating entity "altsyncram" for hierarchy "system:inst_cpu|system_cpu:cpu|system_cpu_dc_victim_module:system_cpu_dc_victim|altsyncram:the_altsyncram" +Info (12130): Elaborated megafunction instantiation "system:inst_cpu|system_cpu:cpu|system_cpu_dc_victim_module:system_cpu_dc_victim|altsyncram:the_altsyncram" +Info (12133): Instantiated megafunction "system:inst_cpu|system_cpu:cpu|system_cpu_dc_victim_module:system_cpu_dc_victim|altsyncram:the_altsyncram" with the following parameter: + Info (12134): Parameter "address_reg_b" = "CLOCK0" + Info (12134): Parameter "maximum_depth" = "0" + Info (12134): Parameter "numwords_a" = "8" + Info (12134): Parameter "numwords_b" = "8" + Info (12134): Parameter "operation_mode" = "DUAL_PORT" + Info (12134): Parameter "outdata_reg_b" = "UNREGISTERED" + Info (12134): Parameter "ram_block_type" = "AUTO" + Info (12134): Parameter "rdcontrol_reg_b" = "CLOCK0" + Info (12134): Parameter "read_during_write_mode_mixed_ports" = "OLD_DATA" + Info (12134): Parameter "width_a" = "32" + Info (12134): Parameter "width_b" = "32" + Info (12134): Parameter "widthad_a" = "3" + Info (12134): Parameter "widthad_b" = "3" +Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_r3d1.tdf + Info (12023): Found entity 1: altsyncram_r3d1 +Info (12128): Elaborating entity "altsyncram_r3d1" for hierarchy "system:inst_cpu|system_cpu:cpu|system_cpu_dc_victim_module:system_cpu_dc_victim|altsyncram:the_altsyncram|altsyncram_r3d1:auto_generated" +Info (12128): Elaborating entity "system_cpu_mult_cell" for hierarchy "system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell" +Info (12128): Elaborating entity "altmult_add" for hierarchy "system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1" +Info (12130): Elaborated megafunction instantiation "system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1" +Info (12133): Instantiated megafunction "system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1" with the following parameter: + Info (12134): Parameter "addnsub_multiplier_pipeline_aclr1" = "ACLR0" + Info (12134): Parameter "addnsub_multiplier_pipeline_register1" = "CLOCK0" + Info (12134): Parameter "addnsub_multiplier_register1" = "UNREGISTERED" + Info (12134): Parameter "dedicated_multiplier_circuitry" = "YES" + Info (12134): Parameter "input_register_a0" = "UNREGISTERED" + Info (12134): Parameter "input_register_b0" = "UNREGISTERED" + Info (12134): Parameter "input_source_a0" = "DATAA" + Info (12134): Parameter "input_source_b0" = "DATAB" + Info (12134): Parameter "intended_device_family" = "CYCLONEIVE" + Info (12134): Parameter "lpm_type" = "altmult_add" + Info (12134): Parameter "multiplier1_direction" = "ADD" + Info (12134): Parameter "multiplier_aclr0" = "ACLR0" + Info (12134): Parameter "multiplier_register0" = "CLOCK0" + Info (12134): Parameter "number_of_multipliers" = "1" + Info (12134): Parameter "output_register" = "UNREGISTERED" + Info (12134): Parameter "port_addnsub1" = "PORT_UNUSED" + Info (12134): Parameter "port_addnsub3" = "PORT_UNUSED" + Info (12134): Parameter "port_signa" = "PORT_UNUSED" + Info (12134): Parameter "port_signb" = "PORT_UNUSED" + Info (12134): Parameter "representation_a" = "UNSIGNED" + Info (12134): Parameter "representation_b" = "UNSIGNED" + Info (12134): Parameter "signed_pipeline_aclr_a" = "ACLR0" + Info (12134): Parameter "signed_pipeline_aclr_b" = "ACLR0" + Info (12134): Parameter "signed_pipeline_register_a" = "CLOCK0" + Info (12134): Parameter "signed_pipeline_register_b" = "CLOCK0" + Info (12134): Parameter "signed_register_a" = "UNREGISTERED" + Info (12134): Parameter "signed_register_b" = "UNREGISTERED" + Info (12134): Parameter "width_a" = "16" + Info (12134): Parameter "width_b" = "16" + Info (12134): Parameter "width_result" = "32" +Info (12021): Found 1 design units, including 1 entities, in source file db/mult_add_75u2.tdf + Info (12023): Found entity 1: mult_add_75u2 +Info (12128): Elaborating entity "mult_add_75u2" for hierarchy "system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated" +Info (12021): Found 1 design units, including 1 entities, in source file db/ded_mult_ks81.tdf + Info (12023): Found entity 1: ded_mult_ks81 +Info (12128): Elaborating entity "ded_mult_ks81" for hierarchy "system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1" +Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_93c.tdf + Info (12023): Found entity 1: dffpipe_93c +Info (12128): Elaborating entity "dffpipe_93c" for hierarchy "system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|dffpipe_93c:pre_result" +Info (12128): Elaborating entity "altmult_add" for hierarchy "system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2" +Info (12130): Elaborated megafunction instantiation "system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2" +Info (12133): Instantiated megafunction "system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2" with the following parameter: + Info (12134): Parameter "addnsub_multiplier_pipeline_aclr1" = "ACLR0" + Info (12134): Parameter "addnsub_multiplier_pipeline_register1" = "CLOCK0" + Info (12134): Parameter "addnsub_multiplier_register1" = "UNREGISTERED" + Info (12134): Parameter "dedicated_multiplier_circuitry" = "YES" + Info (12134): Parameter "input_register_a0" = "UNREGISTERED" + Info (12134): Parameter "input_register_b0" = "UNREGISTERED" + Info (12134): Parameter "input_source_a0" = "DATAA" + Info (12134): Parameter "input_source_b0" = "DATAB" + Info (12134): Parameter "intended_device_family" = "CYCLONEIVE" + Info (12134): Parameter "lpm_type" = "altmult_add" + Info (12134): Parameter "multiplier1_direction" = "ADD" + Info (12134): Parameter "multiplier_aclr0" = "ACLR0" + Info (12134): Parameter "multiplier_register0" = "CLOCK0" + Info (12134): Parameter "number_of_multipliers" = "1" + Info (12134): Parameter "output_register" = "UNREGISTERED" + Info (12134): Parameter "port_addnsub1" = "PORT_UNUSED" + Info (12134): Parameter "port_addnsub3" = "PORT_UNUSED" + Info (12134): Parameter "port_signa" = "PORT_UNUSED" + Info (12134): Parameter "port_signb" = "PORT_UNUSED" + Info (12134): Parameter "representation_a" = "UNSIGNED" + Info (12134): Parameter "representation_b" = "UNSIGNED" + Info (12134): Parameter "signed_pipeline_aclr_a" = "ACLR0" + Info (12134): Parameter "signed_pipeline_aclr_b" = "ACLR0" + Info (12134): Parameter "signed_pipeline_register_a" = "CLOCK0" + Info (12134): Parameter "signed_pipeline_register_b" = "CLOCK0" + Info (12134): Parameter "signed_register_a" = "UNREGISTERED" + Info (12134): Parameter "signed_register_b" = "UNREGISTERED" + Info (12134): Parameter "width_a" = "16" + Info (12134): Parameter "width_b" = "16" + Info (12134): Parameter "width_result" = "16" +Info (12021): Found 1 design units, including 1 entities, in source file db/mult_add_95u2.tdf + Info (12023): Found entity 1: mult_add_95u2 +Info (12128): Elaborating entity "mult_add_95u2" for hierarchy "system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated" +Info (12128): Elaborating entity "system_cpu_nios2_oci" for hierarchy "system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci" +Info (12128): Elaborating entity "system_cpu_nios2_oci_debug" for hierarchy "system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_debug:the_system_cpu_nios2_oci_debug" +Info (12128): Elaborating entity "system_cpu_nios2_ocimem" for hierarchy "system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem" +Info (12128): Elaborating entity "system_cpu_ociram_lpm_dram_bdp_component_module" for hierarchy "system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component" +Info (12128): Elaborating entity "altsyncram" for hierarchy "system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram" +Info (12130): Elaborated megafunction instantiation "system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram" +Info (12133): Instantiated megafunction "system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram" with the following parameter: + Info (12134): Parameter "address_aclr_a" = "NONE" + Info (12134): Parameter "address_aclr_b" = "NONE" + Info (12134): Parameter "address_reg_b" = "CLOCK1" + Info (12134): Parameter "indata_aclr_a" = "NONE" + Info (12134): Parameter "indata_aclr_b" = "NONE" + Info (12134): Parameter "init_file" = "system_cpu_ociram_default_contents.mif" + Info (12134): Parameter "intended_device_family" = "CYCLONEIVE" + Info (12134): Parameter "lpm_type" = "altsyncram" + Info (12134): Parameter "numwords_a" = "256" + Info (12134): Parameter "numwords_b" = "256" + Info (12134): Parameter "operation_mode" = "BIDIR_DUAL_PORT" + Info (12134): Parameter "outdata_aclr_a" = "NONE" + Info (12134): Parameter "outdata_aclr_b" = "NONE" + Info (12134): Parameter "outdata_reg_a" = "UNREGISTERED" + Info (12134): Parameter "outdata_reg_b" = "UNREGISTERED" + Info (12134): Parameter "ram_block_type" = "AUTO" + Info (12134): Parameter "read_during_write_mode_mixed_ports" = "OLD_DATA" + Info (12134): Parameter "width_a" = "32" + Info (12134): Parameter "width_b" = "32" + Info (12134): Parameter "width_byteena_a" = "4" + Info (12134): Parameter "widthad_a" = "8" + Info (12134): Parameter "widthad_b" = "8" + Info (12134): Parameter "wrcontrol_aclr_a" = "NONE" + Info (12134): Parameter "wrcontrol_aclr_b" = "NONE" +Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_jt72.tdf + Info (12023): Found entity 1: altsyncram_jt72 +Info (12128): Elaborating entity "altsyncram_jt72" for hierarchy "system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated" +Info (12128): Elaborating entity "system_cpu_nios2_avalon_reg" for hierarchy "system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg" +Info (12128): Elaborating entity "system_cpu_nios2_oci_break" for hierarchy "system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_break:the_system_cpu_nios2_oci_break" +Info (12128): Elaborating entity "system_cpu_nios2_oci_xbrk" for hierarchy "system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_xbrk:the_system_cpu_nios2_oci_xbrk" +Info (12128): Elaborating entity "system_cpu_nios2_oci_dbrk" for hierarchy "system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_dbrk:the_system_cpu_nios2_oci_dbrk" +Info (12128): Elaborating entity "system_cpu_nios2_oci_itrace" for hierarchy "system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_itrace:the_system_cpu_nios2_oci_itrace" +Info (12128): Elaborating entity "system_cpu_nios2_oci_dtrace" for hierarchy "system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_dtrace:the_system_cpu_nios2_oci_dtrace" +Info (12128): Elaborating entity "system_cpu_nios2_oci_td_mode" for hierarchy "system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_dtrace:the_system_cpu_nios2_oci_dtrace|system_cpu_nios2_oci_td_mode:system_cpu_nios2_oci_trc_ctrl_td_mode" +Info (12128): Elaborating entity "system_cpu_nios2_oci_fifo" for hierarchy "system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_fifo:the_system_cpu_nios2_oci_fifo" +Info (12128): Elaborating entity "system_cpu_nios2_oci_compute_tm_count" for hierarchy "system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_fifo:the_system_cpu_nios2_oci_fifo|system_cpu_nios2_oci_compute_tm_count:system_cpu_nios2_oci_compute_tm_count_tm_count" +Info (12128): Elaborating entity "system_cpu_nios2_oci_fifowp_inc" for hierarchy "system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_fifo:the_system_cpu_nios2_oci_fifo|system_cpu_nios2_oci_fifowp_inc:system_cpu_nios2_oci_fifowp_inc_fifowp" +Info (12128): Elaborating entity "system_cpu_nios2_oci_fifocount_inc" for hierarchy "system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_fifo:the_system_cpu_nios2_oci_fifo|system_cpu_nios2_oci_fifocount_inc:system_cpu_nios2_oci_fifocount_inc_fifocount" +Info (12128): Elaborating entity "system_cpu_oci_test_bench" for hierarchy "system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_fifo:the_system_cpu_nios2_oci_fifo|system_cpu_oci_test_bench:the_system_cpu_oci_test_bench" +Info (12128): Elaborating entity "system_cpu_nios2_oci_pib" for hierarchy "system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_pib:the_system_cpu_nios2_oci_pib" +Info (12128): Elaborating entity "system_cpu_nios2_oci_im" for hierarchy "system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im" +Info (12128): Elaborating entity "system_cpu_traceram_lpm_dram_bdp_component_module" for hierarchy "system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component" +Info (12128): Elaborating entity "altsyncram" for hierarchy "system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram" +Info (12130): Elaborated megafunction instantiation "system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram" +Info (12133): Instantiated megafunction "system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram" with the following parameter: + Info (12134): Parameter "address_aclr_a" = "NONE" + Info (12134): Parameter "address_aclr_b" = "NONE" + Info (12134): Parameter "address_reg_b" = "CLOCK1" + Info (12134): Parameter "indata_aclr_a" = "NONE" + Info (12134): Parameter "indata_aclr_b" = "NONE" + Info (12134): Parameter "init_file" = "UNUSED" + Info (12134): Parameter "intended_device_family" = "CYCLONEIVE" + Info (12134): Parameter "lpm_type" = "altsyncram" + Info (12134): Parameter "numwords_a" = "128" + Info (12134): Parameter "numwords_b" = "128" + Info (12134): Parameter "operation_mode" = "BIDIR_DUAL_PORT" + Info (12134): Parameter "outdata_aclr_a" = "NONE" + Info (12134): Parameter "outdata_aclr_b" = "NONE" + Info (12134): Parameter "outdata_reg_a" = "UNREGISTERED" + Info (12134): Parameter "outdata_reg_b" = "UNREGISTERED" + Info (12134): Parameter "ram_block_type" = "AUTO" + Info (12134): Parameter "read_during_write_mode_mixed_ports" = "OLD_DATA" + Info (12134): Parameter "width_a" = "36" + Info (12134): Parameter "width_b" = "36" + Info (12134): Parameter "widthad_a" = "7" + Info (12134): Parameter "widthad_b" = "7" + Info (12134): Parameter "wrcontrol_aclr_a" = "NONE" + Info (12134): Parameter "wrcontrol_aclr_b" = "NONE" +Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_0a02.tdf + Info (12023): Found entity 1: altsyncram_0a02 +Info (12128): Elaborating entity "altsyncram_0a02" for hierarchy "system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated" +Info (12128): Elaborating entity "system_cpu_jtag_debug_module_wrapper" for hierarchy "system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper" +Info (12128): Elaborating entity "system_cpu_jtag_debug_module_tck" for hierarchy "system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck" +Info (12128): Elaborating entity "altera_std_synchronizer" for hierarchy "system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer" +Info (12130): Elaborated megafunction instantiation "system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer" +Info (12133): Instantiated megafunction "system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer" with the following parameter: + Info (12134): Parameter "depth" = "2" +Info (12128): Elaborating entity "system_cpu_jtag_debug_module_sysclk" for hierarchy "system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk" +Info (12128): Elaborating entity "sld_virtual_jtag_basic" for hierarchy "system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy" +Info (12130): Elaborated megafunction instantiation "system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy" +Info (12133): Instantiated megafunction "system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy" with the following parameter: + Info (12134): Parameter "sld_auto_instance_index" = "YES" + Info (12134): Parameter "sld_instance_index" = "0" + Info (12134): Parameter "sld_ir_width" = "2" + Info (12134): Parameter "sld_mfg_id" = "70" + Info (12134): Parameter "sld_sim_action" = "" + Info (12134): Parameter "sld_sim_n_scan" = "0" + Info (12134): Parameter "sld_sim_total_length" = "0" + Info (12134): Parameter "sld_type_id" = "34" + Info (12134): Parameter "sld_version" = "3" +Info (12128): Elaborating entity "sld_virtual_jtag_impl" for hierarchy "system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst" +Info (12131): Elaborated megafunction instantiation "system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst", which is child of megafunction instantiation "system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy" +Info (12128): Elaborating entity "system_sysid" for hierarchy "system:inst_cpu|system_sysid:sysid" +Info (12128): Elaborating entity "system_sdram" for hierarchy "system:inst_cpu|system_sdram:sdram" +Info (12128): Elaborating entity "system_sdram_input_efifo_module" for hierarchy "system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module" +Info (12128): Elaborating entity "system_sys_clk_timer" for hierarchy "system:inst_cpu|system_sys_clk_timer:sys_clk_timer" +Info (12128): Elaborating entity "system_uart_0" for hierarchy "system:inst_cpu|system_uart_0:uart_0" +Info (12128): Elaborating entity "system_uart_0_tx" for hierarchy "system:inst_cpu|system_uart_0:uart_0|system_uart_0_tx:the_system_uart_0_tx" +Info (12128): Elaborating entity "system_uart_0_rx" for hierarchy "system:inst_cpu|system_uart_0:uart_0|system_uart_0_rx:the_system_uart_0_rx" +Info (12128): Elaborating entity "system_uart_0_rx_stimulus_source" for hierarchy "system:inst_cpu|system_uart_0:uart_0|system_uart_0_rx:the_system_uart_0_rx|system_uart_0_rx_stimulus_source:the_system_uart_0_rx_stimulus_source" +Info (12128): Elaborating entity "system_uart_0_regs" for hierarchy "system:inst_cpu|system_uart_0:uart_0|system_uart_0_regs:the_system_uart_0_regs" +Info (12128): Elaborating entity "system_pio_led" for hierarchy "system:inst_cpu|system_pio_led:pio_led" +Info (12128): Elaborating entity "system_pio_key" for hierarchy "system:inst_cpu|system_pio_key:pio_key" +Info (12128): Elaborating entity "system_pio_sw" for hierarchy "system:inst_cpu|system_pio_sw:pio_sw" +Info (12128): Elaborating entity "system_jtag_uart_0" for hierarchy "system:inst_cpu|system_jtag_uart_0:jtag_uart_0" +Info (12128): Elaborating entity "system_jtag_uart_0_scfifo_w" for hierarchy "system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w" +Info (12128): Elaborating entity "scfifo" for hierarchy "system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo" +Info (12130): Elaborated megafunction instantiation "system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo" +Info (12133): Instantiated megafunction "system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo" with the following parameter: + Info (12134): Parameter "lpm_hint" = "RAM_BLOCK_TYPE=AUTO" + Info (12134): Parameter "lpm_numwords" = "64" + Info (12134): Parameter "lpm_showahead" = "OFF" + Info (12134): Parameter "lpm_type" = "scfifo" + Info (12134): Parameter "lpm_width" = "8" + Info (12134): Parameter "lpm_widthu" = "6" + Info (12134): Parameter "overflow_checking" = "OFF" + Info (12134): Parameter "underflow_checking" = "OFF" + Info (12134): Parameter "use_eab" = "ON" +Info (12021): Found 1 design units, including 1 entities, in source file db/scfifo_jr21.tdf + Info (12023): Found entity 1: scfifo_jr21 +Info (12128): Elaborating entity "scfifo_jr21" for hierarchy "system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated" +Info (12021): Found 1 design units, including 1 entities, in source file db/a_dpfifo_q131.tdf + Info (12023): Found entity 1: a_dpfifo_q131 +Info (12128): Elaborating entity "a_dpfifo_q131" for hierarchy "system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo" +Info (12021): Found 1 design units, including 1 entities, in source file db/a_fefifo_7cf.tdf + Info (12023): Found entity 1: a_fefifo_7cf +Info (12128): Elaborating entity "a_fefifo_7cf" for hierarchy "system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state" +Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_do7.tdf + Info (12023): Found entity 1: cntr_do7 +Info (12128): Elaborating entity "cntr_do7" for hierarchy "system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw" +Info (12021): Found 1 design units, including 1 entities, in source file db/dpram_nl21.tdf + Info (12023): Found entity 1: dpram_nl21 +Info (12128): Elaborating entity "dpram_nl21" for hierarchy "system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram" +Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_r1m1.tdf + Info (12023): Found entity 1: altsyncram_r1m1 +Info (12128): Elaborating entity "altsyncram_r1m1" for hierarchy "system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1" +Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_1ob.tdf + Info (12023): Found entity 1: cntr_1ob +Info (12128): Elaborating entity "cntr_1ob" for hierarchy "system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:rd_ptr_count" +Info (12128): Elaborating entity "system_jtag_uart_0_scfifo_r" for hierarchy "system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r" +Info (12128): Elaborating entity "alt_jtag_atlantic" for hierarchy "system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic" +Info (12130): Elaborated megafunction instantiation "system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic" +Info (12133): Instantiated megafunction "system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic" with the following parameter: + Info (12134): Parameter "INSTANCE_ID" = "0" + Info (12134): Parameter "LOG2_RXFIFO_DEPTH" = "6" + Info (12134): Parameter "LOG2_TXFIFO_DEPTH" = "6" + Info (12134): Parameter "SLD_AUTO_INSTANCE_INDEX" = "YES" +Info (12128): Elaborating entity "system_pio_motor_rst" for hierarchy "system:inst_cpu|system_pio_motor_rst:pio_motor_rst" +Info (12128): Elaborating entity "system_rs232_motor" for hierarchy "system:inst_cpu|system_rs232_motor:rs232_motor" +Warning (10036): Verilog HDL or VHDL warning at system_rs232_motor.v(123): object "write_data_parity" assigned a value but never read +Info (12128): Elaborating entity "altera_up_rs232_in_deserializer" for hierarchy "system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer" +Info (12128): Elaborating entity "altera_up_rs232_counters" for hierarchy "system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_rs232_counters:RS232_In_Counters" +Warning (10230): Verilog HDL assignment warning at altera_up_rs232_counters.v(124): truncated value with size 32 to match size of target (14) +Info (12128): Elaborating entity "altera_up_sync_fifo" for hierarchy "system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO" +Info (12128): Elaborating entity "scfifo" for hierarchy "system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO" +Info (12130): Elaborated megafunction instantiation "system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO" +Info (12133): Instantiated megafunction "system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO" with the following parameter: + Info (12134): Parameter "add_ram_output_register" = "OFF" + Info (12134): Parameter "intended_device_family" = "Cyclone II" + Info (12134): Parameter "lpm_numwords" = "128" + Info (12134): Parameter "lpm_showahead" = "ON" + Info (12134): Parameter "lpm_type" = "scfifo" + Info (12134): Parameter "lpm_width" = "8" + Info (12134): Parameter "lpm_widthu" = "7" + Info (12134): Parameter "overflow_checking" = "OFF" + Info (12134): Parameter "underflow_checking" = "OFF" + Info (12134): Parameter "use_eab" = "ON" +Info (12021): Found 1 design units, including 1 entities, in source file db/scfifo_a341.tdf + Info (12023): Found entity 1: scfifo_a341 +Info (12128): Elaborating entity "scfifo_a341" for hierarchy "system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated" +Info (12021): Found 1 design units, including 1 entities, in source file db/a_dpfifo_tq31.tdf + Info (12023): Found entity 1: a_dpfifo_tq31 +Info (12128): Elaborating entity "a_dpfifo_tq31" for hierarchy "system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo" +Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_je81.tdf + Info (12023): Found entity 1: altsyncram_je81 +Info (12128): Elaborating entity "altsyncram_je81" for hierarchy "system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram" +Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_ks8.tdf + Info (12023): Found entity 1: cmpr_ks8 +Info (12128): Elaborating entity "cmpr_ks8" for hierarchy "system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cmpr_ks8:almost_full_comparer" +Info (12128): Elaborating entity "cmpr_ks8" for hierarchy "system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cmpr_ks8:three_comparison" +Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_v9b.tdf + Info (12023): Found entity 1: cntr_v9b +Info (12128): Elaborating entity "cntr_v9b" for hierarchy "system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_v9b:rd_ptr_msb" +Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_ca7.tdf + Info (12023): Found entity 1: cntr_ca7 +Info (12128): Elaborating entity "cntr_ca7" for hierarchy "system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_ca7:usedw_counter" +Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_0ab.tdf + Info (12023): Found entity 1: cntr_0ab +Info (12128): Elaborating entity "cntr_0ab" for hierarchy "system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr" +Info (12128): Elaborating entity "altera_up_rs232_out_serializer" for hierarchy "system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer" +Info (12128): Elaborating entity "altera_merlin_master_translator" for hierarchy "system:inst_cpu|altera_merlin_master_translator:cpu_instruction_master_translator" +Info (12128): Elaborating entity "altera_merlin_master_translator" for hierarchy "system:inst_cpu|altera_merlin_master_translator:cpu_data_master_translator" +Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "system:inst_cpu|altera_merlin_slave_translator:cpu_jtag_debug_module_translator" +Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "system:inst_cpu|altera_merlin_slave_translator:sdram_s1_translator" +Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "system:inst_cpu|altera_merlin_slave_translator:sysid_control_slave_translator" +Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "system:inst_cpu|altera_merlin_slave_translator:sys_clk_timer_s1_translator" +Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "system:inst_cpu|altera_merlin_slave_translator:uart_0_s1_translator" +Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "system:inst_cpu|altera_merlin_slave_translator:pio_led_s1_translator" +Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "system:inst_cpu|altera_merlin_slave_translator:pio_key_s1_translator" +Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "system:inst_cpu|altera_merlin_slave_translator:jtag_uart_0_avalon_jtag_slave_translator" +Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "system:inst_cpu|altera_merlin_slave_translator:rs232_motor_avalon_rs232_slave_translator" +Info (12128): Elaborating entity "altera_merlin_master_agent" for hierarchy "system:inst_cpu|altera_merlin_master_agent:cpu_instruction_master_translator_avalon_universal_master_0_agent" +Info (12128): Elaborating entity "altera_merlin_master_agent" for hierarchy "system:inst_cpu|altera_merlin_master_agent:cpu_data_master_translator_avalon_universal_master_0_agent" +Info (12128): Elaborating entity "altera_merlin_slave_agent" for hierarchy "system:inst_cpu|altera_merlin_slave_agent:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent" +Info (12128): Elaborating entity "altera_merlin_burst_uncompressor" for hierarchy "system:inst_cpu|altera_merlin_slave_agent:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor" +Info (12128): Elaborating entity "altera_avalon_sc_fifo" for hierarchy "system:inst_cpu|altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo" +Info (12128): Elaborating entity "altera_merlin_slave_agent" for hierarchy "system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent" +Info (12128): Elaborating entity "altera_merlin_burst_uncompressor" for hierarchy "system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor" +Info (12128): Elaborating entity "altera_avalon_sc_fifo" for hierarchy "system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" +Info (12128): Elaborating entity "system_addr_router" for hierarchy "system:inst_cpu|system_addr_router:addr_router" +Info (12128): Elaborating entity "system_addr_router_default_decode" for hierarchy "system:inst_cpu|system_addr_router:addr_router|system_addr_router_default_decode:the_default_decode" +Info (12128): Elaborating entity "system_addr_router_001" for hierarchy "system:inst_cpu|system_addr_router_001:addr_router_001" +Info (12128): Elaborating entity "system_addr_router_001_default_decode" for hierarchy "system:inst_cpu|system_addr_router_001:addr_router_001|system_addr_router_001_default_decode:the_default_decode" +Info (12128): Elaborating entity "system_id_router" for hierarchy "system:inst_cpu|system_id_router:id_router" +Info (12128): Elaborating entity "system_id_router_default_decode" for hierarchy "system:inst_cpu|system_id_router:id_router|system_id_router_default_decode:the_default_decode" +Info (12128): Elaborating entity "system_id_router_001" for hierarchy "system:inst_cpu|system_id_router_001:id_router_001" +Info (12128): Elaborating entity "system_id_router_001_default_decode" for hierarchy "system:inst_cpu|system_id_router_001:id_router_001|system_id_router_001_default_decode:the_default_decode" +Info (12128): Elaborating entity "system_id_router_002" for hierarchy "system:inst_cpu|system_id_router_002:id_router_002" +Info (12128): Elaborating entity "system_id_router_002_default_decode" for hierarchy "system:inst_cpu|system_id_router_002:id_router_002|system_id_router_002_default_decode:the_default_decode" +Info (12128): Elaborating entity "altera_merlin_traffic_limiter" for hierarchy "system:inst_cpu|altera_merlin_traffic_limiter:limiter" +Info (12128): Elaborating entity "altera_merlin_burst_adapter" for hierarchy "system:inst_cpu|altera_merlin_burst_adapter:burst_adapter" +Info (12128): Elaborating entity "altera_merlin_burst_adapter_uncompressed_only" for hierarchy "system:inst_cpu|altera_merlin_burst_adapter:burst_adapter|altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba" +Info (12128): Elaborating entity "altera_reset_controller" for hierarchy "system:inst_cpu|altera_reset_controller:rst_controller" +Info (12128): Elaborating entity "altera_reset_synchronizer" for hierarchy "system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1" +Info (12128): Elaborating entity "system_cmd_xbar_demux" for hierarchy "system:inst_cpu|system_cmd_xbar_demux:cmd_xbar_demux" +Info (12128): Elaborating entity "system_cmd_xbar_demux_001" for hierarchy "system:inst_cpu|system_cmd_xbar_demux_001:cmd_xbar_demux_001" +Info (12128): Elaborating entity "system_cmd_xbar_mux" for hierarchy "system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux" +Info (12128): Elaborating entity "altera_merlin_arbitrator" for hierarchy "system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux|altera_merlin_arbitrator:arb" +Info (12128): Elaborating entity "altera_merlin_arb_adder" for hierarchy "system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder" +Info (12128): Elaborating entity "system_rsp_xbar_demux" for hierarchy "system:inst_cpu|system_rsp_xbar_demux:rsp_xbar_demux" +Info (12128): Elaborating entity "system_rsp_xbar_demux_002" for hierarchy "system:inst_cpu|system_rsp_xbar_demux_002:rsp_xbar_demux_002" +Info (12128): Elaborating entity "system_rsp_xbar_mux" for hierarchy "system:inst_cpu|system_rsp_xbar_mux:rsp_xbar_mux" +Info (12128): Elaborating entity "altera_merlin_arbitrator" for hierarchy "system:inst_cpu|system_rsp_xbar_mux:rsp_xbar_mux|altera_merlin_arbitrator:arb" +Info (12128): Elaborating entity "system_rsp_xbar_mux_001" for hierarchy "system:inst_cpu|system_rsp_xbar_mux_001:rsp_xbar_mux_001" +Info (12128): Elaborating entity "altera_merlin_arbitrator" for hierarchy "system:inst_cpu|system_rsp_xbar_mux_001:rsp_xbar_mux_001|altera_merlin_arbitrator:arb" +Info (12128): Elaborating entity "altera_merlin_arb_adder" for hierarchy "system:inst_cpu|system_rsp_xbar_mux_001:rsp_xbar_mux_001|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder" +Info (12128): Elaborating entity "altera_merlin_width_adapter" for hierarchy "system:inst_cpu|altera_merlin_width_adapter:width_adapter" +Info (12128): Elaborating entity "altera_merlin_width_adapter" for hierarchy "system:inst_cpu|altera_merlin_width_adapter:width_adapter_001" +Info (12128): Elaborating entity "system_irq_mapper" for hierarchy "system:inst_cpu|system_irq_mapper:irq_mapper" +Warning (12020): Port "address_b" on the entity instantiation of "system_cpu_traceram_lpm_dram_bdp_component" is connected to a signal of width 17. The formal width of the signal in the module is 7. The extra bits will be ignored. +Warning (12020): Port "jdo" on the entity instantiation of "the_system_cpu_nios2_oci_itrace" is connected to a signal of width 38. The formal width of the signal in the module is 16. The extra bits will be ignored. +Warning (14284): Synthesized away the following node(s): + Warning (14285): Synthesized away the following RAM node(s): + Warning (14320): Synthesized away node "system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|q_a[0]" + Warning (14320): Synthesized away node "system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|q_a[1]" + Warning (14320): Synthesized away node "system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|q_a[2]" + Warning (14320): Synthesized away node "system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|q_a[3]" + Warning (14320): Synthesized away node "system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|q_a[4]" + Warning (14320): Synthesized away node "system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|q_a[5]" + Warning (14320): Synthesized away node "system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|q_a[6]" + Warning (14320): Synthesized away node "system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|q_a[7]" + Warning (14320): Synthesized away node "system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|q_a[8]" + Warning (14320): Synthesized away node "system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|q_a[9]" + Warning (14320): Synthesized away node "system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|q_a[10]" + Warning (14320): Synthesized away node "system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|q_a[11]" + Warning (14320): Synthesized away node "system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|q_a[12]" + Warning (14320): Synthesized away node "system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|q_a[13]" + Warning (14320): Synthesized away node "system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|q_a[14]" + Warning (14320): Synthesized away node "system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|q_a[15]" + Warning (14320): Synthesized away node "system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|q_a[16]" + Warning (14320): Synthesized away node "system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|q_a[17]" + Warning (14320): Synthesized away node "system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|q_a[18]" + Warning (14320): Synthesized away node "system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|q_a[19]" + Warning (14320): Synthesized away node "system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|q_a[20]" + Warning (14320): Synthesized away node "system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|q_a[21]" + Warning (14320): Synthesized away node "system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|q_a[22]" + Warning (14320): Synthesized away node "system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|q_a[23]" + Warning (14320): Synthesized away node "system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|q_a[24]" + Warning (14320): Synthesized away node "system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|q_a[25]" + Warning (14320): Synthesized away node "system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|q_a[26]" + Warning (14320): Synthesized away node "system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|q_a[27]" + Warning (14320): Synthesized away node "system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|q_a[28]" + Warning (14320): Synthesized away node "system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|q_a[29]" + Warning (14320): Synthesized away node "system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|q_a[30]" + Warning (14320): Synthesized away node "system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|q_a[31]" + Warning (14320): Synthesized away node "system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|q_a[32]" + Warning (14320): Synthesized away node "system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|q_a[33]" + Warning (14320): Synthesized away node "system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|q_a[34]" + Warning (14320): Synthesized away node "system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|q_a[35]" +Info (278001): Inferred 1 megafunctions from design logic + Info (278002): Inferred adder/subtractor megafunction ("lpm_add_sub") from the following logic: "system:inst_cpu|system_cpu:cpu|Add17" +Info (12130): Elaborated megafunction instantiation "system:inst_cpu|system_cpu:cpu|lpm_add_sub:Add17" +Info (12133): Instantiated megafunction "system:inst_cpu|system_cpu:cpu|lpm_add_sub:Add17" with the following parameter: + Info (12134): Parameter "LPM_WIDTH" = "33" + Info (12134): Parameter "LPM_DIRECTION" = "DEFAULT" + Info (12134): Parameter "LPM_REPRESENTATION" = "UNSIGNED" + Info (12134): Parameter "ONE_INPUT_IS_CONSTANT" = "NO" +Info (12021): Found 1 design units, including 1 entities, in source file db/add_sub_qvi.tdf + Info (12023): Found entity 1: add_sub_qvi +Warning (12241): 2 hierarchies have connectivity warnings - see the Connectivity Checks report folder +Warning (13034): The following nodes have both tri-state and non-tri-state drivers + Warning (13035): Inserted always-enabled tri-state buffer between "GPIO_0[0]" and its non-tri-state driver. + Warning (13035): Inserted always-enabled tri-state buffer between "GPIO_1[12]" and its non-tri-state driver. + Warning (13035): Inserted always-enabled tri-state buffer between "GPIO_1[26]" and its non-tri-state driver. +Warning (13039): The following bidir pins have no drivers + Warning (13040): Bidir "GPIO_0[2]" has no driver + Warning (13040): Bidir "GPIO_0[3]" has no driver + Warning (13040): Bidir "GPIO_0[4]" has no driver + Warning (13040): Bidir "GPIO_0[5]" has no driver + Warning (13040): Bidir "GPIO_0[6]" has no driver + Warning (13040): Bidir "GPIO_0[7]" has no driver + Warning (13040): Bidir "GPIO_0[8]" has no driver + Warning (13040): Bidir "GPIO_0[9]" has no driver + Warning (13040): Bidir "GPIO_0[10]" has no driver + Warning (13040): Bidir "GPIO_0[11]" has no driver + Warning (13040): Bidir "GPIO_0[12]" has no driver + Warning (13040): Bidir "GPIO_0[13]" has no driver + Warning (13040): Bidir "GPIO_0[14]" has no driver + Warning (13040): Bidir "GPIO_0[15]" has no driver + Warning (13040): Bidir "GPIO_0[16]" has no driver + Warning (13040): Bidir "GPIO_0[17]" has no driver + Warning (13040): Bidir "GPIO_0[18]" has no driver + Warning (13040): Bidir "GPIO_0[19]" has no driver + Warning (13040): Bidir "GPIO_0[20]" has no driver + Warning (13040): Bidir "GPIO_0[21]" has no driver + Warning (13040): Bidir "GPIO_0[22]" has no driver + Warning (13040): Bidir "GPIO_0[23]" has no driver + Warning (13040): Bidir "GPIO_0[24]" has no driver + Warning (13040): Bidir "GPIO_0[25]" has no driver + Warning (13040): Bidir "GPIO_0[26]" has no driver + Warning (13040): Bidir "GPIO_0[27]" has no driver + Warning (13040): Bidir "GPIO_0[28]" has no driver + Warning (13040): Bidir "GPIO_0[29]" has no driver + Warning (13040): Bidir "GPIO_0[30]" has no driver + Warning (13040): Bidir "GPIO_0[31]" has no driver + Warning (13040): Bidir "GPIO_0[32]" has no driver + Warning (13040): Bidir "GPIO_0[33]" has no driver + Warning (13040): Bidir "GPIO_1[0]" has no driver + Warning (13040): Bidir "GPIO_1[1]" has no driver + Warning (13040): Bidir "GPIO_1[2]" has no driver + Warning (13040): Bidir "GPIO_1[3]" has no driver + Warning (13040): Bidir "GPIO_1[4]" has no driver + Warning (13040): Bidir "GPIO_1[5]" has no driver + Warning (13040): Bidir "GPIO_1[6]" has no driver + Warning (13040): Bidir "GPIO_1[7]" has no driver + Warning (13040): Bidir "GPIO_1[8]" has no driver + Warning (13040): Bidir "GPIO_1[9]" has no driver + Warning (13040): Bidir "GPIO_1[10]" has no driver + Warning (13040): Bidir "GPIO_1[11]" has no driver + Warning (13040): Bidir "GPIO_1[13]" has no driver + Warning (13040): Bidir "GPIO_1[14]" has no driver + Warning (13040): Bidir "GPIO_1[15]" has no driver + Warning (13040): Bidir "GPIO_1[16]" has no driver + Warning (13040): Bidir "GPIO_1[17]" has no driver + Warning (13040): Bidir "GPIO_1[18]" has no driver + Warning (13040): Bidir "GPIO_1[19]" has no driver + Warning (13040): Bidir "GPIO_1[20]" has no driver + Warning (13040): Bidir "GPIO_1[21]" has no driver + Warning (13040): Bidir "GPIO_1[22]" has no driver + Warning (13040): Bidir "GPIO_1[23]" has no driver + Warning (13040): Bidir "GPIO_1[25]" has no driver + Warning (13040): Bidir "GPIO_1[27]" has no driver + Warning (13040): Bidir "GPIO_1[28]" has no driver + Warning (13040): Bidir "GPIO_1[29]" has no driver + Warning (13040): Bidir "GPIO_1[30]" has no driver + Warning (13040): Bidir "GPIO_1[31]" has no driver + Warning (13040): Bidir "GPIO_1[32]" has no driver + Warning (13040): Bidir "GPIO_1[33]" has no driver + Warning (13040): Bidir "GPIO_0[1]" has no driver + Warning (13040): Bidir "GPIO_1[24]" has no driver +Info (13000): Registers with preset signals will power-up high +Info (13003): DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back +Warning (13009): TRI or OPNDRN buffers permanently enabled + Warning (13010): Node "GPIO_0[0]~synth" + Warning (13010): Node "GPIO_1[12]~synth" + Warning (13010): Node "GPIO_1[26]~synth" +Warning (13024): Output pins are stuck at VCC or GND + Warning (13410): Pin "DRAM_CKE" is stuck at VCC +Info (286031): Timing-Driven Synthesis is running on partition "Top" +Info (17049): 370 registers lost all their fanouts during netlist optimizations. +Info (16010): Generating hard_block partition "hard_block:auto_generated_inst" + Info (16011): Adding 1 node(s), including 0 DDIO, 1 PLL, 0 transceiver and 0 LCELL +Info (21057): Implemented 5525 device resources after synthesis - the final resource count might be different + Info (21058): Implemented 10 input pins + Info (21059): Implemented 32 output pins + Info (21060): Implemented 84 bidirectional pins + Info (21061): Implemented 5130 logic cells + Info (21064): Implemented 263 RAM segments + Info (21065): Implemented 1 PLLs + Info (21062): Implemented 4 DSP elements +Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 128 warnings + Info: Peak virtual memory: 644 megabytes + Info: Processing ended: Fri Mar 14 16:48:51 2014 + Info: Elapsed time: 00:00:22 + Info: Total CPU time (on all processors): 00:00:21 + + diff --git a/MCTEST/DE0-nano-HD/output_files/de0_nano_system.map.summary b/MCTEST/DE0-nano-HD/output_files/de0_nano_system.map.summary new file mode 100644 index 00000000..dc27467f --- /dev/null +++ b/MCTEST/DE0-nano-HD/output_files/de0_nano_system.map.summary @@ -0,0 +1,14 @@ +Analysis & Synthesis Status : Successful - Fri Mar 14 16:48:51 2014 +Quartus II 64-Bit Version : 12.1 Build 243 01/31/2013 SP 1.33 SJ Full Version +Revision Name : de0_nano_system +Top-level Entity Name : de0_nano_system +Family : Cyclone IV E +Total logic elements : 4,696 + Total combinational functions : 3,932 + Dedicated logic registers : 2,867 +Total registers : 2867 +Total pins : 122 +Total virtual pins : 0 +Total memory bits : 119,808 +Embedded Multiplier 9-bit elements : 4 +Total PLLs : 1 diff --git a/MCTEST/DE0-nano-HD/output_files/de0_nano_system.pin b/MCTEST/DE0-nano-HD/output_files/de0_nano_system.pin new file mode 100644 index 00000000..39b6799f --- /dev/null +++ b/MCTEST/DE0-nano-HD/output_files/de0_nano_system.pin @@ -0,0 +1,326 @@ + -- Copyright (C) 1991-2012 Altera Corporation + -- Your use of Altera Corporation's design tools, logic functions + -- and other software and tools, and its AMPP partner logic + -- functions, and any output files from any of the foregoing + -- (including device programming or simulation files), and any + -- associated documentation or information are expressly subject + -- to the terms and conditions of the Altera Program License + -- Subscription Agreement, Altera MegaCore Function License + -- Agreement, or other applicable license agreement, including, + -- without limitation, that your use is for the sole purpose of + -- programming logic devices manufactured by Altera and sold by + -- Altera or its authorized distributors. Please refer to the + -- applicable agreement for further details. + -- + -- This is a Quartus II output file. It is for reporting purposes only, and is + -- not intended for use as a Quartus II input file. This file cannot be used + -- to make Quartus II pin assignments - for instructions on how to make pin + -- assignments, please see Quartus II help. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- NC : No Connect. This pin has no internal connection to the device. + -- DNU : Do Not Use. This pin MUST NOT be connected. + -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V). + -- VCCIO : Dedicated power pin, which MUST be connected to VCC + -- of its bank. + -- Bank 1: 2.5V + -- Bank 2: 2.5V + -- Bank 3: 2.5V + -- Bank 4: 2.5V + -- Bank 5: 2.5V + -- Bank 6: 2.5V + -- Bank 7: 2.5V + -- Bank 8: 2.5V + -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND. + -- It can also be used to report unused dedicated pins. The connection + -- on the board for unused dedicated pins depends on whether this will + -- be used in a future design. One example is device migration. When + -- using device migration, refer to the device pin-tables. If it is a + -- GND pin in the pin table or if it will not be used in a future design + -- for another purpose the it MUST be connected to GND. If it is an unused + -- dedicated pin, then it can be connected to a valid signal on the board + -- (low, high, or toggling) if that signal is required for a different + -- revision of the design. + -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins. + -- This pin should be connected to GND. It may also be connected to a + -- valid signal on the board (low, high, or toggling) if that signal + -- is required for a different revision of the design. + -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND + -- or leave it unconnected. + -- RESERVED : Unused I/O pin, which MUST be left unconnected. + -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board. + -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor. + -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry. + -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- Pin directions (input, output or bidir) are based on device operating in user mode. + --------------------------------------------------------------------------------- + +Quartus II 64-Bit Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Full Version +CHIP "de0_nano_system" ASSIGNED TO AN: EP4CE22F17C6 + +Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment +------------------------------------------------------------------------------------------------------------- +VCCIO8 : A1 : power : : 2.5V : 8 : +GPIO_0[2] : A2 : bidir : 2.5 V : : 8 : Y +GPIO_0[3] : A3 : bidir : 2.5 V : : 8 : Y +GPIO_0[6] : A4 : bidir : 2.5 V : : 8 : Y +GPIO_0[8] : A5 : bidir : 2.5 V : : 8 : Y +GPIO_0[11] : A6 : bidir : 2.5 V : : 8 : Y +GPIO_0[14] : A7 : bidir : 2.5 V : : 8 : Y +GND+ : A8 : : : : 8 : +GND+ : A9 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A10 : : : : 7 : +LED[3] : A11 : output : 2.5 V : : 7 : Y +GPIO_0[30] : A12 : bidir : 2.5 V : : 7 : Y +LED[1] : A13 : output : 2.5 V : : 7 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : A14 : : : : 7 : +LED[0] : A15 : output : 2.5 V : : 7 : Y +VCCIO7 : A16 : power : : 2.5V : 7 : +LED[6] : B1 : output : 2.5 V : : 1 : Y +GND : B2 : gnd : : : : +GPIO_0[4] : B3 : bidir : 2.5 V : : 8 : Y +GPIO_0[5] : B4 : bidir : 2.5 V : : 8 : Y +GPIO_0[7] : B5 : bidir : 2.5 V : : 8 : Y +GPIO_0[10] : B6 : bidir : 2.5 V : : 8 : Y +GPIO_0[12] : B7 : bidir : 2.5 V : : 8 : Y +GND+ : B8 : : : : 8 : +SW[2] : B9 : input : 2.5 V : : 7 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : B10 : : : : 7 : +GPIO_0[29] : B11 : bidir : 2.5 V : : 7 : Y +GPIO_0[33] : B12 : bidir : 2.5 V : : 7 : Y +LED[2] : B13 : output : 2.5 V : : 7 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : B14 : : : : 7 : +GND : B15 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B16 : : : : 6 : +~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP : C1 : input : 2.5 V : : 1 : N +DRAM_WE_N : C2 : output : 2.5 V : : 1 : Y +GPIO_0[1] : C3 : bidir : 2.5 V : : 8 : Y +VCCIO8 : C4 : power : : 2.5V : 8 : +GND : C5 : gnd : : : : +GPIO_0[15] : C6 : bidir : 2.5 V : : 8 : Y +VCCIO8 : C7 : power : : 2.5V : 8 : +GPIO_0[16] : C8 : bidir : 2.5 V : : 8 : Y +GPIO_0[24] : C9 : bidir : 2.5 V : : 7 : Y +VCCIO7 : C10 : power : : 2.5V : 7 : +GPIO_0[28] : C11 : bidir : 2.5 V : : 7 : Y +GND : C12 : gnd : : : : +VCCIO7 : C13 : power : : 2.5V : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C14 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C15 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : C16 : : : : 6 : +LED[4] : D1 : output : 2.5 V : : 1 : Y +~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : D2 : input : 2.5 V : : 1 : N +GPIO_0[0] : D3 : bidir : 2.5 V : : 8 : Y +VCCD_PLL3 : D4 : power : : 1.2V : : +GPIO_0[9] : D5 : bidir : 2.5 V : : 8 : Y +GPIO_0[13] : D6 : bidir : 2.5 V : : 8 : Y +GND : D7 : gnd : : : : +GPIO_0[19] : D8 : bidir : 2.5 V : : 8 : Y +GPIO_0[25] : D9 : bidir : 2.5 V : : 7 : Y +GND : D10 : gnd : : : : +GPIO_0[31] : D11 : bidir : 2.5 V : : 7 : Y +GPIO_0[32] : D12 : bidir : 2.5 V : : 7 : Y +VCCD_PLL2 : D13 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : D14 : : : : 7 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D15 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D16 : : : : 6 : +KEY[1] : E1 : input : 2.5 V : : 1 : Y +GND : E2 : gnd : : : : +VCCIO1 : E3 : power : : 2.5V : 1 : +GND : E4 : gnd : : : : +GNDA3 : E5 : gnd : : : : +GPIO_0[17] : E6 : bidir : 2.5 V : : 8 : Y +GPIO_0[18] : E7 : bidir : 2.5 V : : 8 : Y +GPIO_0[20] : E8 : bidir : 2.5 V : : 8 : Y +GPIO_0[23] : E9 : bidir : 2.5 V : : 7 : Y +GPIO_0[27] : E10 : bidir : 2.5 V : : 7 : Y +GPIO_0[26] : E11 : bidir : 2.5 V : : 7 : Y +GNDA2 : E12 : gnd : : : : +GND : E13 : gnd : : : : +VCCIO6 : E14 : power : : 2.5V : 6 : +GND+ : E15 : : : : 6 : +GND+ : E16 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F1 : : : : 1 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F2 : : : : 1 : +LED[5] : F3 : output : 2.5 V : : 1 : Y +nSTATUS : F4 : : : : 1 : +VCCA3 : F5 : power : : 2.5V : : +GND : F6 : gnd : : : : +VCCINT : F7 : power : : 1.2V : : +GPIO_0[21] : F8 : bidir : 2.5 V : : 8 : Y +GPIO_0[22] : F9 : bidir : 2.5 V : : 7 : Y +GND : F10 : gnd : : : : +VCCINT : F11 : power : : 1.2V : : +VCCA2 : F12 : power : : 2.5V : : +GPIO_1[0] : F13 : bidir : 2.5 V : : 6 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : F14 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F15 : : : : 6 : +~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN : F16 : output : 2.5 V : : 6 : N +DRAM_DQ[1] : G1 : bidir : 2.5 V : : 1 : Y +DRAM_DQ[0] : G2 : bidir : 2.5 V : : 1 : Y +VCCIO1 : G3 : power : : 2.5V : 1 : +GND : G4 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : G5 : : : : 1 : +VCCINT : G6 : power : : 1.2V : : +VCCINT : G7 : power : : 1.2V : : +VCCINT : G8 : power : : 1.2V : : +VCCINT : G9 : power : : 1.2V : : +VCCINT : G10 : power : : 1.2V : : +GND : G11 : gnd : : : : +MSEL2 : G12 : : : : 6 : +GND : G13 : gnd : : : : +VCCIO6 : G14 : power : : 2.5V : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G15 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G16 : : : : 6 : +~ALTERA_DCLK~ : H1 : output : 2.5 V : : 1 : N +~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP : H2 : input : 2.5 V : : 1 : N +altera_reserved_tck : H3 : input : 2.5 V : : 1 : N +altera_reserved_tdi : H4 : input : 2.5 V : : 1 : N +nCONFIG : H5 : : : : 1 : +VCCINT : H6 : power : : 1.2V : : +GND : H7 : gnd : : : : +GND : H8 : gnd : : : : +GND : H9 : gnd : : : : +GND : H10 : gnd : : : : +VCCINT : H11 : power : : 1.2V : : +MSEL1 : H12 : : : : 6 : +MSEL0 : H13 : : : : 6 : +CONF_DONE : H14 : : : : 6 : +GND : H15 : gnd : : : : +GND : H16 : gnd : : : : +DRAM_DQ[6] : J1 : bidir : 2.5 V : : 2 : Y +DRAM_DQ[5] : J2 : bidir : 2.5 V : : 2 : Y +nCE : J3 : : : : 1 : +altera_reserved_tdo : J4 : output : 2.5 V : : 1 : N +altera_reserved_tms : J5 : input : 2.5 V : : 1 : N +VCCINT : J6 : power : : 1.2V : : +GND : J7 : gnd : : : : +GND : J8 : gnd : : : : +GND : J9 : gnd : : : : +GND : J10 : gnd : : : : +GND : J11 : gnd : : : : +VCCINT : J12 : power : : 1.2V : : +GPIO_1[32] : J13 : bidir : 2.5 V : : 5 : Y +GPIO_1[33] : J14 : bidir : 2.5 V : : 5 : Y +KEY[0] : J15 : input : 2.5 V : : 5 : Y +GPIO_1[30] : J16 : bidir : 2.5 V : : 5 : Y +DRAM_DQ[15] : K1 : bidir : 2.5 V : : 2 : Y +DRAM_DQ[4] : K2 : bidir : 2.5 V : : 2 : Y +VCCIO2 : K3 : power : : 2.5V : 2 : +GND : K4 : gnd : : : : +DRAM_DQ[3] : K5 : bidir : 2.5 V : : 2 : Y +GND : K6 : gnd : : : : +VCCINT : K7 : power : : 1.2V : : +GND : K8 : gnd : : : : +VCCINT : K9 : power : : 1.2V : : +VCCINT : K10 : power : : 1.2V : : +VCCINT : K11 : power : : 1.2V : : +GND : K12 : gnd : : : : +GND : K13 : gnd : : : : +VCCIO5 : K14 : power : : 2.5V : 5 : +GPIO_1[31] : K15 : bidir : 2.5 V : : 5 : Y +GPIO_1[17] : K16 : bidir : 2.5 V : : 5 : Y +DRAM_CAS_N : L1 : output : 2.5 V : : 2 : Y +DRAM_RAS_N : L2 : output : 2.5 V : : 2 : Y +LED[7] : L3 : output : 2.5 V : : 2 : Y +DRAM_ADDR[12] : L4 : output : 2.5 V : : 2 : Y +VCCA1 : L5 : power : : 2.5V : : +VCCINT : L6 : power : : 1.2V : : +DRAM_CKE : L7 : output : 2.5 V : : 3 : Y +DRAM_DQ[2] : L8 : bidir : 2.5 V : : 3 : Y +GND : L9 : gnd : : : : +GND : L10 : gnd : : : : +GND : L11 : gnd : : : : +VCCA4 : L12 : power : : 2.5V : : +GPIO_1[29] : L13 : bidir : 2.5 V : : 5 : Y +GPIO_1[26] : L14 : bidir : 2.5 V : : 5 : Y +GPIO_1[19] : L15 : bidir : 2.5 V : : 5 : Y +GPIO_1[16] : L16 : bidir : 2.5 V : : 5 : Y +SW[0] : M1 : input : 2.5 V : : 2 : Y +GND+ : M2 : : : : 2 : +VCCIO2 : M3 : power : : 2.5V : 2 : +GND : M4 : gnd : : : : +GNDA1 : M5 : gnd : : : : +DRAM_BA[1] : M6 : output : 2.5 V : : 3 : Y +DRAM_BA[0] : M7 : output : 2.5 V : : 3 : Y +DRAM_ADDR[3] : M8 : output : 2.5 V : : 3 : Y +VCCINT : M9 : power : : 1.2V : : +GPIO_1[28] : M10 : bidir : 2.5 V : : 4 : Y +VCCINT : M11 : power : : 1.2V : : +GNDA4 : M12 : gnd : : : : +GND : M13 : gnd : : : : +VCCIO5 : M14 : power : : 2.5V : 5 : +SW[3] : M15 : input : 2.5 V : : 5 : Y +GND+ : M16 : : : : 5 : +DRAM_ADDR[11] : N1 : output : 2.5 V : : 2 : Y +DRAM_ADDR[10] : N2 : output : 2.5 V : : 2 : Y +DRAM_DQ[14] : N3 : bidir : 2.5 V : : 3 : Y +VCCD_PLL1 : N4 : power : : 1.2V : : +DRAM_ADDR[1] : N5 : output : 2.5 V : : 3 : Y +DRAM_ADDR[2] : N6 : output : 2.5 V : : 3 : Y +GND : N7 : gnd : : : : +DRAM_ADDR[6] : N8 : output : 2.5 V : : 3 : Y +GPIO_1[14] : N9 : bidir : 2.5 V : : 4 : Y +GND : N10 : gnd : : : : +GPIO_1[15] : N11 : bidir : 2.5 V : : 4 : Y +GPIO_1[12] : N12 : bidir : 2.5 V : : 4 : Y +VCCD_PLL4 : N13 : power : : 1.2V : : +GPIO_1[27] : N14 : bidir : 2.5 V : : 5 : Y +GPIO_1[24] : N15 : bidir : 2.5 V : : 5 : Y +GPIO_1[23] : N16 : bidir : 2.5 V : : 5 : Y +DRAM_ADDR[9] : P1 : output : 2.5 V : : 2 : Y +DRAM_ADDR[0] : P2 : output : 2.5 V : : 2 : Y +DRAM_DQ[13] : P3 : bidir : 2.5 V : : 3 : Y +VCCIO3 : P4 : power : : 2.5V : 3 : +GND : P5 : gnd : : : : +DRAM_CS_N : P6 : output : 2.5 V : : 3 : Y +VCCIO3 : P7 : power : : 2.5V : 3 : +DRAM_ADDR[4] : P8 : output : 2.5 V : : 3 : Y +GPIO_1[13] : P9 : bidir : 2.5 V : : 4 : Y +VCCIO4 : P10 : power : : 2.5V : 4 : +GPIO_1[10] : P11 : bidir : 2.5 V : : 4 : Y +GND : P12 : gnd : : : : +VCCIO4 : P13 : power : : 2.5V : 4 : +GPIO_1[25] : P14 : bidir : 2.5 V : : 4 : Y +GPIO_1[20] : P15 : bidir : 2.5 V : : 5 : Y +GPIO_1[21] : P16 : bidir : 2.5 V : : 5 : Y +DRAM_ADDR[8] : R1 : output : 2.5 V : : 2 : Y +GND : R2 : gnd : : : : +DRAM_DQ[11] : R3 : bidir : 2.5 V : : 3 : Y +DRAM_CLK : R4 : output : 2.5 V : : 3 : Y +DRAM_DQ[12] : R5 : bidir : 2.5 V : : 3 : Y +DRAM_DQM[0] : R6 : output : 2.5 V : : 3 : Y +DRAM_DQ[7] : R7 : bidir : 2.5 V : : 3 : Y +CLOCK_50 : R8 : input : 2.5 V : : 3 : Y +GND+ : R9 : : : : 4 : +GPIO_1[11] : R10 : bidir : 2.5 V : : 4 : Y +GPIO_1[9] : R11 : bidir : 2.5 V : : 4 : Y +GPIO_1[6] : R12 : bidir : 2.5 V : : 4 : Y +GPIO_1[4] : R13 : bidir : 2.5 V : : 4 : Y +GPIO_1[22] : R14 : bidir : 2.5 V : : 4 : Y +GND : R15 : gnd : : : : +GPIO_1[18] : R16 : bidir : 2.5 V : : 5 : Y +VCCIO3 : T1 : power : : 2.5V : 3 : +DRAM_DQ[9] : T2 : bidir : 2.5 V : : 3 : Y +DRAM_DQ[10] : T3 : bidir : 2.5 V : : 3 : Y +DRAM_DQ[8] : T4 : bidir : 2.5 V : : 3 : Y +DRAM_DQM[1] : T5 : output : 2.5 V : : 3 : Y +DRAM_ADDR[7] : T6 : output : 2.5 V : : 3 : Y +DRAM_ADDR[5] : T7 : output : 2.5 V : : 3 : Y +SW[1] : T8 : input : 2.5 V : : 3 : Y +GND+ : T9 : : : : 4 : +GPIO_1[8] : T10 : bidir : 2.5 V : : 4 : Y +GPIO_1[7] : T11 : bidir : 2.5 V : : 4 : Y +GPIO_1[5] : T12 : bidir : 2.5 V : : 4 : Y +GPIO_1[3] : T13 : bidir : 2.5 V : : 4 : Y +GPIO_1[2] : T14 : bidir : 2.5 V : : 4 : Y +GPIO_1[1] : T15 : bidir : 2.5 V : : 4 : Y +VCCIO4 : T16 : power : : 2.5V : 4 : diff --git a/MCTEST/DE0-nano-HD/output_files/de0_nano_system.sof b/MCTEST/DE0-nano-HD/output_files/de0_nano_system.sof new file mode 100644 index 00000000..28b2a6bd Binary files /dev/null and b/MCTEST/DE0-nano-HD/output_files/de0_nano_system.sof differ diff --git a/MCTEST/DE0-nano-HD/output_files/de0_nano_system.sta.rpt b/MCTEST/DE0-nano-HD/output_files/de0_nano_system.sta.rpt new file mode 100644 index 00000000..e85df179 --- /dev/null +++ b/MCTEST/DE0-nano-HD/output_files/de0_nano_system.sta.rpt @@ -0,0 +1,6006 @@ +TimeQuest Timing Analyzer report for de0_nano_system +Fri Mar 14 16:49:42 2014 +Quartus II 64-Bit Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Full Version + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. TimeQuest Timing Analyzer Summary + 3. Parallel Compilation + 4. SDC File List + 5. Clocks + 6. Slow 1200mV 85C Model Fmax Summary + 7. Slow 1200mV 85C Model Setup Summary + 8. Slow 1200mV 85C Model Hold Summary + 9. Slow 1200mV 85C Model Recovery Summary + 10. Slow 1200mV 85C Model Removal Summary + 11. Slow 1200mV 85C Model Minimum Pulse Width Summary + 12. Slow 1200mV 85C Model Setup: 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[0]' + 13. Slow 1200mV 85C Model Setup: 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[2]' + 14. Slow 1200mV 85C Model Hold: 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[0]' + 15. Slow 1200mV 85C Model Hold: 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[2]' + 16. Slow 1200mV 85C Model Recovery: 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[0]' + 17. Slow 1200mV 85C Model Removal: 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[0]' + 18. Slow 1200mV 85C Model Minimum Pulse Width: 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[0]' + 19. Slow 1200mV 85C Model Minimum Pulse Width: 'CLOCK_50' + 20. Slow 1200mV 85C Model Minimum Pulse Width: 'altera_reserved_tck' + 21. Slow 1200mV 85C Model Minimum Pulse Width: 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[2]' + 22. Setup Times + 23. Hold Times + 24. Clock to Output Times + 25. Minimum Clock to Output Times + 26. Output Enable Times + 27. Minimum Output Enable Times + 28. Output Disable Times + 29. Minimum Output Disable Times + 30. MTBF Summary + 31. Synchronizer Summary + 32. Synchronizer Chain #1: Typical MTBF is Greater than 1 Billion Years + 33. Synchronizer Chain #2: Typical MTBF is Greater than 1 Billion Years + 34. Synchronizer Chain #3: Typical MTBF is Greater than 1 Billion Years + 35. Synchronizer Chain #4: Typical MTBF is n/a Years + 36. Synchronizer Chain #5: Typical MTBF is n/a Years + 37. Slow 1200mV 0C Model Fmax Summary + 38. Slow 1200mV 0C Model Setup Summary + 39. Slow 1200mV 0C Model Hold Summary + 40. Slow 1200mV 0C Model Recovery Summary + 41. Slow 1200mV 0C Model Removal Summary + 42. Slow 1200mV 0C Model Minimum Pulse Width Summary + 43. Slow 1200mV 0C Model Setup: 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[0]' + 44. Slow 1200mV 0C Model Setup: 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[2]' + 45. Slow 1200mV 0C Model Hold: 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[0]' + 46. Slow 1200mV 0C Model Hold: 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[2]' + 47. Slow 1200mV 0C Model Recovery: 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[0]' + 48. Slow 1200mV 0C Model Removal: 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[0]' + 49. Slow 1200mV 0C Model Minimum Pulse Width: 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[0]' + 50. Slow 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50' + 51. Slow 1200mV 0C Model Minimum Pulse Width: 'altera_reserved_tck' + 52. Slow 1200mV 0C Model Minimum Pulse Width: 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[2]' + 53. Setup Times + 54. Hold Times + 55. Clock to Output Times + 56. Minimum Clock to Output Times + 57. Output Enable Times + 58. Minimum Output Enable Times + 59. Output Disable Times + 60. Minimum Output Disable Times + 61. MTBF Summary + 62. Synchronizer Summary + 63. Synchronizer Chain #1: Typical MTBF is Greater than 1 Billion Years + 64. Synchronizer Chain #2: Typical MTBF is Greater than 1 Billion Years + 65. Synchronizer Chain #3: Typical MTBF is Greater than 1 Billion Years + 66. Synchronizer Chain #4: Typical MTBF is n/a Years + 67. Synchronizer Chain #5: Typical MTBF is n/a Years + 68. Fast 1200mV 0C Model Setup Summary + 69. Fast 1200mV 0C Model Hold Summary + 70. Fast 1200mV 0C Model Recovery Summary + 71. Fast 1200mV 0C Model Removal Summary + 72. Fast 1200mV 0C Model Minimum Pulse Width Summary + 73. Fast 1200mV 0C Model Setup: 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[0]' + 74. Fast 1200mV 0C Model Setup: 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[2]' + 75. Fast 1200mV 0C Model Hold: 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[0]' + 76. Fast 1200mV 0C Model Hold: 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[2]' + 77. Fast 1200mV 0C Model Recovery: 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[0]' + 78. Fast 1200mV 0C Model Removal: 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[0]' + 79. Fast 1200mV 0C Model Minimum Pulse Width: 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[0]' + 80. Fast 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50' + 81. Fast 1200mV 0C Model Minimum Pulse Width: 'altera_reserved_tck' + 82. Fast 1200mV 0C Model Minimum Pulse Width: 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[2]' + 83. Setup Times + 84. Hold Times + 85. Clock to Output Times + 86. Minimum Clock to Output Times + 87. Output Enable Times + 88. Minimum Output Enable Times + 89. Output Disable Times + 90. Minimum Output Disable Times + 91. MTBF Summary + 92. Synchronizer Summary + 93. Synchronizer Chain #1: Typical MTBF is Greater than 1 Billion Years + 94. Synchronizer Chain #2: Typical MTBF is Greater than 1 Billion Years + 95. Synchronizer Chain #3: Typical MTBF is Greater than 1 Billion Years + 96. Synchronizer Chain #4: Typical MTBF is n/a Years + 97. Synchronizer Chain #5: Typical MTBF is n/a Years + 98. Multicorner Timing Analysis Summary + 99. Setup Times +100. Hold Times +101. Clock to Output Times +102. Minimum Clock to Output Times +103. Board Trace Model Assignments +104. Input Transition Times +105. Signal Integrity Metrics (Slow 1200mv 0c Model) +106. Signal Integrity Metrics (Slow 1200mv 85c Model) +107. Signal Integrity Metrics (Fast 1200mv 0c Model) +108. Setup Transfers +109. Hold Transfers +110. Recovery Transfers +111. Removal Transfers +112. Report TCCS +113. Report RSKM +114. Unconstrained Paths +115. TimeQuest Timing Analyzer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2012 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++------------------------------------------------------------------------------------------+ +; TimeQuest Timing Analyzer Summary ; ++--------------------+---------------------------------------------------------------------+ +; Quartus II Version ; Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Full Version ; +; Revision Name ; de0_nano_system ; +; Device Family ; Cyclone IV E ; +; Device Name ; EP4CE22F17C6 ; +; Timing Models ; Final ; +; Delay Model ; Combined ; +; Rise/Fall Delays ; Enabled ; ++--------------------+---------------------------------------------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 8 ; +; Maximum allowed ; 4 ; +; ; ; +; Average used ; 3.18 ; +; Maximum used ; 4 ; +; ; ; +; Usage by Processor ; % Time Used ; +; 1 processor ; 100.0% ; +; 2-4 processors ; 40.0% ; +; 5-8 processors ; 0.0% ; ++----------------------------+-------------+ + + ++---------------------------------------------------------------------------------------------+ +; SDC File List ; ++---------------------------------------------------------+--------+--------------------------+ +; SDC File Path ; Status ; Read at ; ++---------------------------------------------------------+--------+--------------------------+ +; de0_nano_system.sdc ; OK ; Fri Mar 14 16:49:38 2014 ; +; system/synthesis/submodules/altera_reset_controller.sdc ; OK ; Fri Mar 14 16:49:38 2014 ; +; system/synthesis/submodules/system_cpu.sdc ; OK ; Fri Mar 14 16:49:38 2014 ; ++---------------------------------------------------------+--------+--------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clocks ; ++----------------------------------------------------------+-----------+---------+-----------+--------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+----------+------------------------------------------------------------+--------------------------------------------------------------+ +; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ; ++----------------------------------------------------------+-----------+---------+-----------+--------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+----------+------------------------------------------------------------+--------------------------------------------------------------+ +; altera_reserved_tck ; Base ; 100.000 ; 10.0 MHz ; 0.000 ; 50.000 ; ; ; ; ; ; ; ; ; ; ; { altera_reserved_tck } ; +; CLOCK_50 ; Base ; 20.000 ; 50.0 MHz ; 0.000 ; 10.000 ; ; ; ; ; ; ; ; ; ; ; { CLOCK_50 } ; +; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Generated ; 10.000 ; 100.0 MHz ; 0.000 ; 5.000 ; 50.00 ; 1 ; 2 ; ; ; ; ; false ; CLOCK_50 ; inst_pll_sys|altpll_component|auto_generated|pll1|inclk[0] ; { inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] } ; +; inst_pll_sys|altpll_component|auto_generated|pll1|clk[1] ; Generated ; 10.000 ; 100.0 MHz ; -1.500 ; 3.500 ; 50.00 ; 1 ; 2 ; -54.0 ; ; ; ; false ; CLOCK_50 ; inst_pll_sys|altpll_component|auto_generated|pll1|inclk[0] ; { inst_pll_sys|altpll_component|auto_generated|pll1|clk[1] } ; +; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Generated ; 100.000 ; 10.0 MHz ; 0.000 ; 50.000 ; 50.00 ; 5 ; 1 ; ; ; ; ; false ; CLOCK_50 ; inst_pll_sys|altpll_component|auto_generated|pll1|inclk[0] ; { inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] } ; ++----------------------------------------------------------+-----------+---------+-----------+--------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+----------+------------------------------------------------------------+--------------------------------------------------------------+ + + ++------------------------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Fmax Summary ; ++------------+-----------------+----------------------------------------------------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++------------+-----------------+----------------------------------------------------------+------+ +; 130.8 MHz ; 130.8 MHz ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; +; 382.85 MHz ; 382.85 MHz ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; ; ++------------+-----------------+----------------------------------------------------------+------+ +This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. + + ++-----------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Setup Summary ; ++----------------------------------------------------------+--------+---------------+ +; Clock ; Slack ; End Point TNS ; ++----------------------------------------------------------+--------+---------------+ +; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 2.020 ; 0.000 ; +; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 97.388 ; 0.000 ; ++----------------------------------------------------------+--------+---------------+ + + ++----------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Hold Summary ; ++----------------------------------------------------------+-------+---------------+ +; Clock ; Slack ; End Point TNS ; ++----------------------------------------------------------+-------+---------------+ +; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.228 ; 0.000 ; +; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.361 ; 0.000 ; ++----------------------------------------------------------+-------+---------------+ + + ++----------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Recovery Summary ; ++----------------------------------------------------------+-------+---------------+ +; Clock ; Slack ; End Point TNS ; ++----------------------------------------------------------+-------+---------------+ +; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 1.948 ; 0.000 ; ++----------------------------------------------------------+-------+---------------+ + + ++----------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Removal Summary ; ++----------------------------------------------------------+-------+---------------+ +; Clock ; Slack ; End Point TNS ; ++----------------------------------------------------------+-------+---------------+ +; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 2.209 ; 0.000 ; ++----------------------------------------------------------+-------+---------------+ + + ++-----------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Minimum Pulse Width Summary ; ++----------------------------------------------------------+--------+---------------+ +; Clock ; Slack ; End Point TNS ; ++----------------------------------------------------------+--------+---------------+ +; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 4.693 ; 0.000 ; +; CLOCK_50 ; 9.835 ; 0.000 ; +; altera_reserved_tck ; 49.624 ; 0.000 ; +; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 49.747 ; 0.000 ; ++----------------------------------------------------------+--------+---------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Setup: 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[0]' ; ++-------+-------------------------------------------------------+-------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+-------------------------------------------------------+-------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ +; 2.020 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[29] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.095 ; 2.880 ; +; 2.244 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[18] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.068 ; 2.683 ; +; 2.321 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[27] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.097 ; 2.577 ; +; 2.339 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[14] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.068 ; 2.588 ; +; 2.350 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[26] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.068 ; 2.577 ; +; 2.355 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[4] ; system:inst_cpu|system_cpu:cpu|A_mem_stall ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.067 ; 7.573 ; +; 2.363 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[3] ; system:inst_cpu|system_cpu:cpu|A_mem_stall ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.067 ; 7.565 ; +; 2.374 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[25] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.095 ; 2.526 ; +; 2.376 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[27] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.097 ; 2.522 ; +; 2.390 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[24] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.084 ; 2.521 ; +; 2.399 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.068 ; 2.528 ; +; 2.404 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.084 ; 2.507 ; +; 2.404 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[26] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.081 ; 2.510 ; +; 2.405 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[22] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.068 ; 2.522 ; +; 2.406 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[6] ; system:inst_cpu|system_cpu:cpu|A_mem_stall ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.062 ; 7.527 ; +; 2.414 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[8] ; system:inst_cpu|system_cpu:cpu|A_mem_stall ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.062 ; 7.519 ; +; 2.419 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[29] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.095 ; 2.481 ; +; 2.431 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[23] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.084 ; 2.480 ; +; 2.433 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.084 ; 2.478 ; +; 2.436 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.084 ; 2.475 ; +; 2.436 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[31] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.084 ; 2.475 ; +; 2.443 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[3] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[24] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.084 ; 2.468 ; +; 2.443 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[3] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.084 ; 2.468 ; +; 2.443 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[27] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.084 ; 2.468 ; +; 2.443 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[3] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.084 ; 2.468 ; +; 2.443 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[3] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[20] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.084 ; 2.468 ; +; 2.443 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[3] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.084 ; 2.468 ; +; 2.443 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[3] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[16] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.084 ; 2.468 ; +; 2.443 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[28] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.084 ; 2.468 ; +; 2.443 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[3] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[28] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.084 ; 2.468 ; +; 2.443 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[3] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.084 ; 2.468 ; +; 2.446 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.084 ; 2.465 ; +; 2.456 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.084 ; 2.455 ; +; 2.476 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[4] ; system:inst_cpu|system_cpu:cpu|d_writedata[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.060 ; 7.459 ; +; 2.476 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[4] ; system:inst_cpu|system_cpu:cpu|d_writedata[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.060 ; 7.459 ; +; 2.476 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[4] ; system:inst_cpu|system_cpu:cpu|d_writedata[22] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.060 ; 7.459 ; +; 2.476 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[4] ; system:inst_cpu|system_cpu:cpu|d_writedata[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.060 ; 7.459 ; +; 2.476 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[4] ; system:inst_cpu|system_cpu:cpu|d_writedata[17] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.060 ; 7.459 ; +; 2.476 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[4] ; system:inst_cpu|system_cpu:cpu|d_writedata[28] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.060 ; 7.459 ; +; 2.476 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[4] ; system:inst_cpu|system_cpu:cpu|d_writedata[25] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.060 ; 7.459 ; +; 2.476 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[4] ; system:inst_cpu|system_cpu:cpu|d_writedata[24] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.060 ; 7.459 ; +; 2.484 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[3] ; system:inst_cpu|system_cpu:cpu|d_writedata[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.060 ; 7.451 ; +; 2.484 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[3] ; system:inst_cpu|system_cpu:cpu|d_writedata[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.060 ; 7.451 ; +; 2.484 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[3] ; system:inst_cpu|system_cpu:cpu|d_writedata[22] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.060 ; 7.451 ; +; 2.484 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[3] ; system:inst_cpu|system_cpu:cpu|d_writedata[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.060 ; 7.451 ; +; 2.484 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[3] ; system:inst_cpu|system_cpu:cpu|d_writedata[17] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.060 ; 7.451 ; +; 2.484 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[3] ; system:inst_cpu|system_cpu:cpu|d_writedata[28] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.060 ; 7.451 ; +; 2.484 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[3] ; system:inst_cpu|system_cpu:cpu|d_writedata[25] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.060 ; 7.451 ; +; 2.484 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[3] ; system:inst_cpu|system_cpu:cpu|d_writedata[24] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.060 ; 7.451 ; +; 2.492 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[4] ; system:inst_cpu|system_cpu:cpu|d_writedata[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.060 ; 7.443 ; +; 2.492 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[4] ; system:inst_cpu|system_cpu:cpu|d_writedata[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.060 ; 7.443 ; +; 2.492 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[4] ; system:inst_cpu|system_cpu:cpu|d_writedata[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.060 ; 7.443 ; +; 2.492 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[4] ; system:inst_cpu|system_cpu:cpu|d_writedata[14] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.060 ; 7.443 ; +; 2.492 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[4] ; system:inst_cpu|system_cpu:cpu|d_writedata[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.060 ; 7.443 ; +; 2.492 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[4] ; system:inst_cpu|system_cpu:cpu|d_writedata[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.060 ; 7.443 ; +; 2.492 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[4] ; system:inst_cpu|system_cpu:cpu|d_writedata[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.060 ; 7.443 ; +; 2.492 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[4] ; system:inst_cpu|system_cpu:cpu|d_writedata[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.060 ; 7.443 ; +; 2.492 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[4] ; system:inst_cpu|system_cpu:cpu|d_writedata[20] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.060 ; 7.443 ; +; 2.492 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[4] ; system:inst_cpu|system_cpu:cpu|d_writedata[18] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.060 ; 7.443 ; +; 2.492 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[4] ; system:inst_cpu|system_cpu:cpu|d_writedata[30] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.060 ; 7.443 ; +; 2.492 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[4] ; system:inst_cpu|system_cpu:cpu|d_writedata[29] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.060 ; 7.443 ; +; 2.495 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[6] ; system:inst_cpu|system_cpu:cpu|d_writedata[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.087 ; 7.413 ; +; 2.495 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[6] ; system:inst_cpu|system_cpu:cpu|d_writedata[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.087 ; 7.413 ; +; 2.495 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[6] ; system:inst_cpu|system_cpu:cpu|d_writedata[22] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.087 ; 7.413 ; +; 2.495 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[6] ; system:inst_cpu|system_cpu:cpu|d_writedata[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.087 ; 7.413 ; +; 2.495 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[6] ; system:inst_cpu|system_cpu:cpu|d_writedata[17] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.087 ; 7.413 ; +; 2.495 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[6] ; system:inst_cpu|system_cpu:cpu|d_writedata[28] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.087 ; 7.413 ; +; 2.495 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[6] ; system:inst_cpu|system_cpu:cpu|d_writedata[25] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.087 ; 7.413 ; +; 2.495 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[6] ; system:inst_cpu|system_cpu:cpu|d_writedata[24] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.087 ; 7.413 ; +; 2.497 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[21] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[29] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.081 ; 2.417 ; +; 2.500 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[3] ; system:inst_cpu|system_cpu:cpu|d_writedata[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.060 ; 7.435 ; +; 2.500 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[3] ; system:inst_cpu|system_cpu:cpu|d_writedata[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.060 ; 7.435 ; +; 2.500 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[3] ; system:inst_cpu|system_cpu:cpu|d_writedata[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.060 ; 7.435 ; +; 2.500 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[3] ; system:inst_cpu|system_cpu:cpu|d_writedata[14] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.060 ; 7.435 ; +; 2.500 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[3] ; system:inst_cpu|system_cpu:cpu|d_writedata[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.060 ; 7.435 ; +; 2.500 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[3] ; system:inst_cpu|system_cpu:cpu|d_writedata[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.060 ; 7.435 ; +; 2.500 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[3] ; system:inst_cpu|system_cpu:cpu|d_writedata[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.060 ; 7.435 ; +; 2.500 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[3] ; system:inst_cpu|system_cpu:cpu|d_writedata[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.060 ; 7.435 ; +; 2.500 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[3] ; system:inst_cpu|system_cpu:cpu|d_writedata[20] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.060 ; 7.435 ; +; 2.500 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[3] ; system:inst_cpu|system_cpu:cpu|d_writedata[18] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.060 ; 7.435 ; +; 2.500 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[3] ; system:inst_cpu|system_cpu:cpu|d_writedata[30] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.060 ; 7.435 ; +; 2.500 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[3] ; system:inst_cpu|system_cpu:cpu|d_writedata[29] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.060 ; 7.435 ; +; 2.503 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[8] ; system:inst_cpu|system_cpu:cpu|d_writedata[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.087 ; 7.405 ; +; 2.503 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[8] ; system:inst_cpu|system_cpu:cpu|d_writedata[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.087 ; 7.405 ; +; 2.503 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[8] ; system:inst_cpu|system_cpu:cpu|d_writedata[22] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.087 ; 7.405 ; +; 2.503 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[8] ; system:inst_cpu|system_cpu:cpu|d_writedata[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.087 ; 7.405 ; +; 2.503 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[8] ; system:inst_cpu|system_cpu:cpu|d_writedata[17] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.087 ; 7.405 ; +; 2.503 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[8] ; system:inst_cpu|system_cpu:cpu|d_writedata[28] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.087 ; 7.405 ; +; 2.503 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[8] ; system:inst_cpu|system_cpu:cpu|d_writedata[25] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.087 ; 7.405 ; +; 2.503 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[8] ; system:inst_cpu|system_cpu:cpu|d_writedata[24] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.087 ; 7.405 ; +; 2.507 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[4] ; system:inst_cpu|system_cpu:cpu|d_writedata[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.060 ; 7.428 ; +; 2.507 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[4] ; system:inst_cpu|system_cpu:cpu|d_writedata[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.060 ; 7.428 ; +; 2.507 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[4] ; system:inst_cpu|system_cpu:cpu|d_writedata[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.060 ; 7.428 ; +; 2.507 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[4] ; system:inst_cpu|system_cpu:cpu|d_writedata[6] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.060 ; 7.428 ; +; 2.507 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[4] ; system:inst_cpu|system_cpu:cpu|d_writedata[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.060 ; 7.428 ; +; 2.507 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[4] ; system:inst_cpu|system_cpu:cpu|d_writedata[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.060 ; 7.428 ; +; 2.507 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[4] ; system:inst_cpu|system_cpu:cpu|d_writedata[16] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.060 ; 7.428 ; +; 2.507 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[4] ; system:inst_cpu|system_cpu:cpu|d_writedata[31] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.060 ; 7.428 ; +; 2.507 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[4] ; system:inst_cpu|system_cpu:cpu|d_writedata[27] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.060 ; 7.428 ; +; 2.507 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[4] ; system:inst_cpu|system_cpu:cpu|d_writedata[26] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.060 ; 7.428 ; ++-------+-------------------------------------------------------+-------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Setup: 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[2]' ; ++--------+-------------------------------------------+-------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++--------+-------------------------------------------+-------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ +; 97.388 ; heartbeat:inst_heartbeat|counter_data[2] ; heartbeat:inst_heartbeat|counter_data[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.064 ; 2.543 ; +; 97.469 ; heartbeat:inst_heartbeat|counter_data[1] ; heartbeat:inst_heartbeat|counter_data[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.064 ; 2.462 ; +; 97.471 ; heartbeat:inst_heartbeat|counter_data[0] ; heartbeat:inst_heartbeat|counter_data[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.064 ; 2.460 ; +; 97.504 ; heartbeat:inst_heartbeat|counter_data[2] ; heartbeat:inst_heartbeat|counter_data[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.064 ; 2.427 ; +; 97.504 ; heartbeat:inst_heartbeat|counter_data[4] ; heartbeat:inst_heartbeat|counter_data[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.064 ; 2.427 ; +; 97.507 ; heartbeat:inst_heartbeat|counter_data[0] ; heartbeat:inst_heartbeat|counter_data[20] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.064 ; 2.424 ; +; 97.510 ; heartbeat:inst_heartbeat|counter_data[1] ; heartbeat:inst_heartbeat|counter_data[20] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.064 ; 2.421 ; +; 97.510 ; heartbeat:inst_heartbeat|counter_data[2] ; heartbeat:inst_heartbeat|counter_data[20] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.064 ; 2.421 ; +; 97.585 ; heartbeat:inst_heartbeat|counter_data[1] ; heartbeat:inst_heartbeat|counter_data[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.064 ; 2.346 ; +; 97.587 ; heartbeat:inst_heartbeat|counter_data[3] ; heartbeat:inst_heartbeat|counter_data[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.064 ; 2.344 ; +; 97.587 ; heartbeat:inst_heartbeat|counter_data[0] ; heartbeat:inst_heartbeat|counter_data[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.064 ; 2.344 ; +; 97.620 ; heartbeat:inst_heartbeat|counter_data[2] ; heartbeat:inst_heartbeat|counter_data[17] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.064 ; 2.311 ; +; 97.620 ; heartbeat:inst_heartbeat|counter_data[4] ; heartbeat:inst_heartbeat|counter_data[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.064 ; 2.311 ; +; 97.622 ; heartbeat:inst_heartbeat|counter_data[3] ; heartbeat:inst_heartbeat|counter_data[20] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.064 ; 2.309 ; +; 97.623 ; heartbeat:inst_heartbeat|counter_data[0] ; heartbeat:inst_heartbeat|counter_data[18] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.064 ; 2.308 ; +; 97.625 ; heartbeat:inst_heartbeat|counter_data[6] ; heartbeat:inst_heartbeat|counter_data[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.064 ; 2.306 ; +; 97.626 ; heartbeat:inst_heartbeat|counter_data[4] ; heartbeat:inst_heartbeat|counter_data[20] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.064 ; 2.305 ; +; 97.626 ; heartbeat:inst_heartbeat|counter_data[1] ; heartbeat:inst_heartbeat|counter_data[18] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.064 ; 2.305 ; +; 97.626 ; heartbeat:inst_heartbeat|counter_data[2] ; heartbeat:inst_heartbeat|counter_data[18] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.064 ; 2.305 ; +; 97.701 ; heartbeat:inst_heartbeat|counter_data[1] ; heartbeat:inst_heartbeat|counter_data[17] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.064 ; 2.230 ; +; 97.703 ; heartbeat:inst_heartbeat|counter_data[5] ; heartbeat:inst_heartbeat|counter_data[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.064 ; 2.228 ; +; 97.703 ; heartbeat:inst_heartbeat|counter_data[3] ; heartbeat:inst_heartbeat|counter_data[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.064 ; 2.228 ; +; 97.703 ; heartbeat:inst_heartbeat|counter_data[0] ; heartbeat:inst_heartbeat|counter_data[17] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.064 ; 2.228 ; +; 97.736 ; heartbeat:inst_heartbeat|counter_data[2] ; heartbeat:inst_heartbeat|counter_data[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.064 ; 2.195 ; +; 97.736 ; heartbeat:inst_heartbeat|counter_data[4] ; heartbeat:inst_heartbeat|counter_data[17] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.064 ; 2.195 ; +; 97.738 ; heartbeat:inst_heartbeat|counter_data[5] ; heartbeat:inst_heartbeat|counter_data[20] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.064 ; 2.193 ; +; 97.738 ; heartbeat:inst_heartbeat|counter_data[3] ; heartbeat:inst_heartbeat|counter_data[18] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.064 ; 2.193 ; +; 97.739 ; heartbeat:inst_heartbeat|counter_data[0] ; heartbeat:inst_heartbeat|counter_data[16] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.064 ; 2.192 ; +; 97.741 ; heartbeat:inst_heartbeat|counter_data[6] ; heartbeat:inst_heartbeat|counter_data[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.064 ; 2.190 ; +; 97.742 ; heartbeat:inst_heartbeat|counter_data[8] ; heartbeat:inst_heartbeat|counter_data[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.064 ; 2.189 ; +; 97.742 ; heartbeat:inst_heartbeat|counter_data[4] ; heartbeat:inst_heartbeat|counter_data[18] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.064 ; 2.189 ; +; 97.742 ; heartbeat:inst_heartbeat|counter_data[1] ; heartbeat:inst_heartbeat|counter_data[16] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.064 ; 2.189 ; +; 97.742 ; heartbeat:inst_heartbeat|counter_data[2] ; heartbeat:inst_heartbeat|counter_data[16] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.064 ; 2.189 ; +; 97.747 ; heartbeat:inst_heartbeat|counter_data[6] ; heartbeat:inst_heartbeat|counter_data[20] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.064 ; 2.184 ; +; 97.817 ; heartbeat:inst_heartbeat|counter_data[1] ; heartbeat:inst_heartbeat|counter_data[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.064 ; 2.114 ; +; 97.819 ; heartbeat:inst_heartbeat|counter_data[5] ; heartbeat:inst_heartbeat|counter_data[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.064 ; 2.112 ; +; 97.819 ; heartbeat:inst_heartbeat|counter_data[3] ; heartbeat:inst_heartbeat|counter_data[17] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.064 ; 2.112 ; +; 97.819 ; heartbeat:inst_heartbeat|counter_data[0] ; heartbeat:inst_heartbeat|counter_data[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.064 ; 2.112 ; +; 97.821 ; heartbeat:inst_heartbeat|counter_data[7] ; heartbeat:inst_heartbeat|counter_data[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.064 ; 2.110 ; +; 97.852 ; heartbeat:inst_heartbeat|counter_data[2] ; heartbeat:inst_heartbeat|counter_data[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.064 ; 2.079 ; +; 97.852 ; heartbeat:inst_heartbeat|counter_data[4] ; heartbeat:inst_heartbeat|counter_data[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.064 ; 2.079 ; +; 97.854 ; heartbeat:inst_heartbeat|counter_data[5] ; heartbeat:inst_heartbeat|counter_data[18] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.064 ; 2.077 ; +; 97.854 ; heartbeat:inst_heartbeat|counter_data[3] ; heartbeat:inst_heartbeat|counter_data[16] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.064 ; 2.077 ; +; 97.855 ; heartbeat:inst_heartbeat|counter_data[0] ; heartbeat:inst_heartbeat|counter_data[14] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.064 ; 2.076 ; +; 97.855 ; heartbeat:inst_heartbeat|counter_data[7] ; heartbeat:inst_heartbeat|counter_data[20] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.064 ; 2.076 ; +; 97.857 ; heartbeat:inst_heartbeat|counter_data[10] ; heartbeat:inst_heartbeat|counter_data[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.064 ; 2.074 ; +; 97.857 ; heartbeat:inst_heartbeat|counter_data[6] ; heartbeat:inst_heartbeat|counter_data[17] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.064 ; 2.074 ; +; 97.858 ; heartbeat:inst_heartbeat|counter_data[8] ; heartbeat:inst_heartbeat|counter_data[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.064 ; 2.073 ; +; 97.858 ; heartbeat:inst_heartbeat|counter_data[4] ; heartbeat:inst_heartbeat|counter_data[16] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.064 ; 2.073 ; +; 97.858 ; heartbeat:inst_heartbeat|counter_data[1] ; heartbeat:inst_heartbeat|counter_data[14] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.064 ; 2.073 ; +; 97.858 ; heartbeat:inst_heartbeat|counter_data[2] ; heartbeat:inst_heartbeat|counter_data[14] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.064 ; 2.073 ; +; 97.863 ; heartbeat:inst_heartbeat|counter_data[6] ; heartbeat:inst_heartbeat|counter_data[18] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.064 ; 2.068 ; +; 97.864 ; heartbeat:inst_heartbeat|counter_data[8] ; heartbeat:inst_heartbeat|counter_data[20] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.064 ; 2.067 ; +; 97.933 ; heartbeat:inst_heartbeat|counter_data[1] ; heartbeat:inst_heartbeat|counter_data[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.064 ; 1.998 ; +; 97.935 ; heartbeat:inst_heartbeat|counter_data[5] ; heartbeat:inst_heartbeat|counter_data[17] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.064 ; 1.996 ; +; 97.935 ; heartbeat:inst_heartbeat|counter_data[3] ; heartbeat:inst_heartbeat|counter_data[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.064 ; 1.996 ; +; 97.935 ; heartbeat:inst_heartbeat|counter_data[0] ; heartbeat:inst_heartbeat|counter_data[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.064 ; 1.996 ; +; 97.937 ; heartbeat:inst_heartbeat|counter_data[9] ; heartbeat:inst_heartbeat|counter_data[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.064 ; 1.994 ; +; 97.937 ; heartbeat:inst_heartbeat|counter_data[7] ; heartbeat:inst_heartbeat|counter_data[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.064 ; 1.994 ; +; 97.968 ; heartbeat:inst_heartbeat|counter_data[2] ; heartbeat:inst_heartbeat|counter_data[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.064 ; 1.963 ; +; 97.968 ; heartbeat:inst_heartbeat|counter_data[4] ; heartbeat:inst_heartbeat|counter_data[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.064 ; 1.963 ; +; 97.970 ; heartbeat:inst_heartbeat|counter_data[5] ; heartbeat:inst_heartbeat|counter_data[16] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.064 ; 1.961 ; +; 97.970 ; heartbeat:inst_heartbeat|counter_data[3] ; heartbeat:inst_heartbeat|counter_data[14] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.064 ; 1.961 ; +; 97.971 ; heartbeat:inst_heartbeat|counter_data[0] ; heartbeat:inst_heartbeat|counter_data[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.064 ; 1.960 ; +; 97.971 ; heartbeat:inst_heartbeat|counter_data[12] ; heartbeat:inst_heartbeat|counter_data[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.063 ; 1.961 ; +; 97.971 ; heartbeat:inst_heartbeat|counter_data[7] ; heartbeat:inst_heartbeat|counter_data[18] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.064 ; 1.960 ; +; 97.972 ; heartbeat:inst_heartbeat|counter_data[9] ; heartbeat:inst_heartbeat|counter_data[20] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.064 ; 1.959 ; +; 97.973 ; heartbeat:inst_heartbeat|counter_data[10] ; heartbeat:inst_heartbeat|counter_data[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.064 ; 1.958 ; +; 97.973 ; heartbeat:inst_heartbeat|counter_data[6] ; heartbeat:inst_heartbeat|counter_data[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.064 ; 1.958 ; +; 97.974 ; heartbeat:inst_heartbeat|counter_data[8] ; heartbeat:inst_heartbeat|counter_data[17] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.064 ; 1.957 ; +; 97.974 ; heartbeat:inst_heartbeat|counter_data[4] ; heartbeat:inst_heartbeat|counter_data[14] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.064 ; 1.957 ; +; 97.974 ; heartbeat:inst_heartbeat|counter_data[1] ; heartbeat:inst_heartbeat|counter_data[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.064 ; 1.957 ; +; 97.974 ; heartbeat:inst_heartbeat|counter_data[2] ; heartbeat:inst_heartbeat|counter_data[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.064 ; 1.957 ; +; 97.979 ; heartbeat:inst_heartbeat|counter_data[10] ; heartbeat:inst_heartbeat|counter_data[20] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.064 ; 1.952 ; +; 97.979 ; heartbeat:inst_heartbeat|counter_data[6] ; heartbeat:inst_heartbeat|counter_data[16] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.064 ; 1.952 ; +; 97.980 ; heartbeat:inst_heartbeat|counter_data[8] ; heartbeat:inst_heartbeat|counter_data[18] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.064 ; 1.951 ; +; 98.049 ; heartbeat:inst_heartbeat|counter_data[1] ; heartbeat:inst_heartbeat|counter_data[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.064 ; 1.882 ; +; 98.051 ; heartbeat:inst_heartbeat|counter_data[5] ; heartbeat:inst_heartbeat|counter_data[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.064 ; 1.880 ; +; 98.051 ; heartbeat:inst_heartbeat|counter_data[3] ; heartbeat:inst_heartbeat|counter_data[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.064 ; 1.880 ; +; 98.051 ; heartbeat:inst_heartbeat|counter_data[0] ; heartbeat:inst_heartbeat|counter_data[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.064 ; 1.880 ; +; 98.053 ; heartbeat:inst_heartbeat|counter_data[9] ; heartbeat:inst_heartbeat|counter_data[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.064 ; 1.878 ; +; 98.053 ; heartbeat:inst_heartbeat|counter_data[7] ; heartbeat:inst_heartbeat|counter_data[17] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.064 ; 1.878 ; +; 98.055 ; heartbeat:inst_heartbeat|counter_data[11] ; heartbeat:inst_heartbeat|counter_data[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.063 ; 1.877 ; +; 98.084 ; heartbeat:inst_heartbeat|counter_data[4] ; heartbeat:inst_heartbeat|counter_data[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.064 ; 1.847 ; +; 98.086 ; heartbeat:inst_heartbeat|counter_data[2] ; heartbeat:inst_heartbeat|counter_data[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.062 ; 1.847 ; +; 98.086 ; heartbeat:inst_heartbeat|counter_data[5] ; heartbeat:inst_heartbeat|counter_data[14] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.064 ; 1.845 ; +; 98.086 ; heartbeat:inst_heartbeat|counter_data[3] ; heartbeat:inst_heartbeat|counter_data[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.064 ; 1.845 ; +; 98.087 ; heartbeat:inst_heartbeat|counter_data[12] ; heartbeat:inst_heartbeat|counter_data[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.063 ; 1.845 ; +; 98.087 ; heartbeat:inst_heartbeat|counter_data[7] ; heartbeat:inst_heartbeat|counter_data[16] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.064 ; 1.844 ; +; 98.088 ; heartbeat:inst_heartbeat|counter_data[9] ; heartbeat:inst_heartbeat|counter_data[18] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.064 ; 1.843 ; +; 98.089 ; heartbeat:inst_heartbeat|counter_data[0] ; heartbeat:inst_heartbeat|counter_data[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.062 ; 1.844 ; +; 98.089 ; heartbeat:inst_heartbeat|counter_data[10] ; heartbeat:inst_heartbeat|counter_data[17] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.064 ; 1.842 ; +; 98.089 ; heartbeat:inst_heartbeat|counter_data[6] ; heartbeat:inst_heartbeat|counter_data[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.064 ; 1.842 ; +; 98.090 ; heartbeat:inst_heartbeat|counter_data[14] ; heartbeat:inst_heartbeat|counter_data[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.063 ; 1.842 ; +; 98.090 ; heartbeat:inst_heartbeat|counter_data[11] ; heartbeat:inst_heartbeat|counter_data[20] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.063 ; 1.842 ; +; 98.090 ; heartbeat:inst_heartbeat|counter_data[8] ; heartbeat:inst_heartbeat|counter_data[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.064 ; 1.841 ; +; 98.090 ; heartbeat:inst_heartbeat|counter_data[4] ; heartbeat:inst_heartbeat|counter_data[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.064 ; 1.841 ; +; 98.092 ; heartbeat:inst_heartbeat|counter_data[1] ; heartbeat:inst_heartbeat|counter_data[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.062 ; 1.841 ; +; 98.092 ; heartbeat:inst_heartbeat|counter_data[2] ; heartbeat:inst_heartbeat|counter_data[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.062 ; 1.841 ; +; 98.093 ; heartbeat:inst_heartbeat|counter_data[12] ; heartbeat:inst_heartbeat|counter_data[20] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.063 ; 1.839 ; ++--------+-------------------------------------------+-------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Hold: 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[0]' ; ++-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ +; 0.228 ; system:inst_cpu|system_cpu:cpu|i_readdata_d1[11] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a11~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.386 ; 0.801 ; +; 0.230 ; system:inst_cpu|system_cpu:cpu|ic_fill_valid_bits[6] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.381 ; 0.798 ; +; 0.232 ; system:inst_cpu|system_cpu:cpu|ic_fill_valid_bits[0] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.381 ; 0.800 ; +; 0.290 ; system:inst_cpu|system_cpu:cpu|ic_tag_wraddress[3] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.377 ; 0.854 ; +; 0.292 ; system:inst_cpu|system_cpu:cpu|M_bht_ptr_unfiltered[2] ; system:inst_cpu|system_cpu:cpu|system_cpu_bht_module:system_cpu_bht|altsyncram:the_altsyncram|altsyncram_fhg1:auto_generated|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.377 ; 0.856 ; +; 0.294 ; system:inst_cpu|system_cpu:cpu|ic_tag_wraddress[7] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.377 ; 0.858 ; +; 0.295 ; system:inst_cpu|system_cpu:cpu|i_readdata_d1[15] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a11~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.384 ; 0.866 ; +; 0.299 ; system:inst_cpu|system_cpu:cpu|ic_fill_valid_bits[4] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.381 ; 0.867 ; +; 0.300 ; system:inst_cpu|system_cpu:cpu|i_readdata_d1[0] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.381 ; 0.868 ; +; 0.302 ; system:inst_cpu|system_cpu:cpu|ic_tag_wraddress[2] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.377 ; 0.866 ; +; 0.305 ; system:inst_cpu|system_cpu:cpu|ic_tag_wraddress[1] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.377 ; 0.869 ; +; 0.305 ; system:inst_cpu|system_cpu:cpu|ic_tag_wraddress[5] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.377 ; 0.869 ; +; 0.305 ; system:inst_cpu|system_cpu:cpu|ic_fill_valid_bits[7] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.381 ; 0.873 ; +; 0.305 ; system:inst_cpu|system_cpu:cpu|i_readdata_d1[14] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a11~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.384 ; 0.876 ; +; 0.306 ; system:inst_cpu|system_cpu:cpu|ic_fill_valid_bits[2] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.381 ; 0.874 ; +; 0.309 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[28] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.386 ; 0.882 ; +; 0.309 ; system:inst_cpu|system_cpu:cpu|i_readdata_d1[3] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.381 ; 0.877 ; +; 0.312 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[30] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.386 ; 0.885 ; +; 0.313 ; system:inst_cpu|system_cpu:cpu|ic_tag_wraddress[4] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.377 ; 0.877 ; +; 0.315 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[27] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.386 ; 0.888 ; +; 0.317 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[25] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.386 ; 0.890 ; +; 0.317 ; system:inst_cpu|system_rs232_motor:rs232_motor|data_to_uart[7] ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.381 ; 0.885 ; +; 0.318 ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|data_in_shift_reg[3] ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.383 ; 0.888 ; +; 0.318 ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[6] ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.377 ; 0.882 ; +; 0.320 ; system:inst_cpu|system_rs232_motor:rs232_motor|data_to_uart[3] ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.381 ; 0.888 ; +; 0.320 ; system:inst_cpu|system_cpu:cpu|M_bht_ptr_unfiltered[4] ; system:inst_cpu|system_cpu:cpu|system_cpu_bht_module:system_cpu_bht|altsyncram:the_altsyncram|altsyncram_fhg1:auto_generated|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.383 ; 0.890 ; +; 0.321 ; system:inst_cpu|system_cpu:cpu|ic_fill_valid_bits[1] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.381 ; 0.889 ; +; 0.321 ; system:inst_cpu|system_cpu:cpu|ic_fill_tag[8] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.382 ; 0.890 ; +; 0.323 ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[0] ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.380 ; 0.890 ; +; 0.323 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[13] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.386 ; 0.896 ; +; 0.323 ; system:inst_cpu|system_cpu:cpu|M_bht_ptr_unfiltered[3] ; system:inst_cpu|system_cpu:cpu|system_cpu_bht_module:system_cpu_bht|altsyncram:the_altsyncram|altsyncram_fhg1:auto_generated|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.381 ; 0.891 ; +; 0.324 ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[3] ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.378 ; 0.889 ; +; 0.324 ; system:inst_cpu|system_cpu:cpu|i_readdata_d1[2] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.381 ; 0.892 ; +; 0.325 ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[1] ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.377 ; 0.889 ; +; 0.325 ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[3] ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.377 ; 0.889 ; +; 0.326 ; system:inst_cpu|system_cpu:cpu|M_bht_ptr_unfiltered[1] ; system:inst_cpu|system_cpu:cpu|system_cpu_bht_module:system_cpu_bht|altsyncram:the_altsyncram|altsyncram_fhg1:auto_generated|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.377 ; 0.890 ; +; 0.326 ; system:inst_cpu|system_cpu:cpu|M_bht_ptr_unfiltered[7] ; system:inst_cpu|system_cpu:cpu|system_cpu_bht_module:system_cpu_bht|altsyncram:the_altsyncram|altsyncram_fhg1:auto_generated|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.381 ; 0.894 ; +; 0.326 ; system:inst_cpu|system_cpu:cpu|i_readdata_d1[1] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.385 ; 0.898 ; +; 0.329 ; system:inst_cpu|system_cpu:cpu|ic_fill_tag[1] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.382 ; 0.898 ; +; 0.332 ; system:inst_cpu|system_rs232_motor:rs232_motor|data_to_uart[1] ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.382 ; 0.901 ; +; 0.332 ; system:inst_cpu|system_cpu:cpu|ic_fill_valid_bits[3] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.381 ; 0.900 ; +; 0.333 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[15] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.386 ; 0.906 ; +; 0.333 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[4] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a0~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.410 ; 0.930 ; +; 0.334 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[31] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.386 ; 0.907 ; +; 0.337 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[12] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.388 ; 0.912 ; +; 0.338 ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[1] ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.380 ; 0.905 ; +; 0.338 ; system:inst_cpu|system_cpu:cpu|ic_tag_wraddress[0] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.377 ; 0.902 ; +; 0.341 ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[6] ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.380 ; 0.908 ; +; 0.341 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[29] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.386 ; 0.914 ; +; 0.342 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[26] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.386 ; 0.915 ; +; 0.343 ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[5] ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.380 ; 0.910 ; +; 0.343 ; system:inst_cpu|system_cpu:cpu|M_bht_ptr_unfiltered[6] ; system:inst_cpu|system_cpu:cpu|system_cpu_bht_module:system_cpu_bht|altsyncram:the_altsyncram|altsyncram_fhg1:auto_generated|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.377 ; 0.907 ; +; 0.345 ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[3] ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.380 ; 0.912 ; +; 0.345 ; system:inst_cpu|system_cpu:cpu|i_readdata_d1[31] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a22~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.384 ; 0.916 ; +; 0.346 ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[0] ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.377 ; 0.910 ; +; 0.348 ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[2] ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.377 ; 0.912 ; +; 0.349 ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[2] ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.380 ; 0.916 ; +; 0.349 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[9] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.388 ; 0.924 ; +; 0.350 ; system:inst_cpu|system_cpu:cpu|ic_tag_wraddress[6] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.377 ; 0.914 ; +; 0.350 ; system:inst_cpu|system_cpu:cpu|ic_fill_tag[6] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.382 ; 0.919 ; +; 0.351 ; system:inst_cpu|system_cpu:cpu|ic_fill_tag[5] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.382 ; 0.920 ; +; 0.355 ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[1] ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.378 ; 0.920 ; +; 0.357 ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[1] ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.377 ; 0.921 ; +; 0.357 ; system:inst_cpu|system_cpu:cpu|A_mul_cnt[1] ; system:inst_cpu|system_cpu:cpu|A_mul_cnt[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.063 ; 0.577 ; +; 0.357 ; system:inst_cpu|system_cpu:cpu|A_mul_cnt[2] ; system:inst_cpu|system_cpu:cpu|A_mul_cnt[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.063 ; 0.577 ; +; 0.357 ; system:inst_cpu|system_cpu:cpu|A_dc_xfer_rd_addr_has_started ; system:inst_cpu|system_cpu:cpu|A_dc_xfer_rd_addr_has_started ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.063 ; 0.577 ; +; 0.357 ; system:inst_cpu|system_cpu:cpu|A_dc_xfer_rd_addr_offset[1] ; system:inst_cpu|system_cpu:cpu|A_dc_xfer_rd_addr_offset[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.063 ; 0.577 ; +; 0.357 ; system:inst_cpu|system_cpu:cpu|A_dc_xfer_rd_addr_offset[2] ; system:inst_cpu|system_cpu:cpu|A_dc_xfer_rd_addr_offset[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.063 ; 0.577 ; +; 0.357 ; system:inst_cpu|system_cpu:cpu|A_dc_xfer_rd_addr_active ; system:inst_cpu|system_cpu:cpu|A_dc_xfer_rd_addr_active ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.063 ; 0.577 ; +; 0.357 ; system:inst_cpu|system_cpu:cpu|A_dc_fill_active ; system:inst_cpu|system_cpu:cpu|A_dc_fill_active ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.063 ; 0.577 ; +; 0.357 ; system:inst_cpu|system_cpu:cpu|ic_fill_valid_bits[5] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.381 ; 0.925 ; +; 0.357 ; system:inst_cpu|system_cpu:cpu|A_st_bypass_delayed_started ; system:inst_cpu|system_cpu:cpu|A_st_bypass_delayed_started ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.063 ; 0.577 ; +; 0.357 ; system:inst_cpu|system_cpu:cpu|A_shift_rot_stall ; system:inst_cpu|system_cpu:cpu|A_shift_rot_stall ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.063 ; 0.577 ; +; 0.357 ; system:inst_cpu|system_cpu:cpu|A_dc_fill_dp_offset[1] ; system:inst_cpu|system_cpu:cpu|A_dc_fill_dp_offset[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.063 ; 0.577 ; +; 0.357 ; system:inst_cpu|system_cpu:cpu|A_dc_fill_dp_offset[2] ; system:inst_cpu|system_cpu:cpu|A_dc_fill_dp_offset[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.063 ; 0.577 ; +; 0.357 ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|woverflow ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|woverflow ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.063 ; 0.577 ; +; 0.357 ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|ac ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|ac ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.063 ; 0.577 ; +; 0.357 ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[8] ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.063 ; 0.577 ; +; 0.357 ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[4] ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.063 ; 0.577 ; +; 0.357 ; system:inst_cpu|system_cpu:cpu|A_dc_rd_data_cnt[1] ; system:inst_cpu|system_cpu:cpu|A_dc_rd_data_cnt[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.063 ; 0.577 ; +; 0.357 ; system:inst_cpu|system_cpu:cpu|A_dc_rd_data_cnt[2] ; system:inst_cpu|system_cpu:cpu|A_dc_rd_data_cnt[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.063 ; 0.577 ; +; 0.357 ; system:inst_cpu|system_sdram:sdram|m_state.000100000 ; system:inst_cpu|system_sdram:sdram|m_state.000100000 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.063 ; 0.577 ; +; 0.357 ; system:inst_cpu|system_sdram:sdram|m_state.000000100 ; system:inst_cpu|system_sdram:sdram|m_state.000000100 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.063 ; 0.577 ; +; 0.357 ; system:inst_cpu|system_sdram:sdram|ack_refresh_request ; system:inst_cpu|system_sdram:sdram|ack_refresh_request ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.063 ; 0.577 ; +; 0.357 ; system:inst_cpu|system_sdram:sdram|refresh_request ; system:inst_cpu|system_sdram:sdram|refresh_request ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.063 ; 0.577 ; +; 0.358 ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|full_dff ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|full_dff ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.577 ; +; 0.358 ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|receiving_data ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|receiving_data ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.577 ; +; 0.358 ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_rs232_counters:RS232_In_Counters|bit_counter[0] ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_rs232_counters:RS232_In_Counters|bit_counter[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.577 ; +; 0.358 ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_rs232_counters:RS232_In_Counters|bit_counter[1] ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_rs232_counters:RS232_In_Counters|bit_counter[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.577 ; +; 0.358 ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_rs232_counters:RS232_In_Counters|bit_counter[2] ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_rs232_counters:RS232_In_Counters|bit_counter[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.577 ; +; 0.358 ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_rs232_counters:RS232_In_Counters|bit_counter[3] ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_rs232_counters:RS232_In_Counters|bit_counter[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.577 ; +; 0.358 ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|full_dff ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|full_dff ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.577 ; +; 0.358 ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|low_addressa[6] ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|low_addressa[6] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.577 ; +; 0.358 ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|low_addressa[5] ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|low_addressa[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.577 ; +; 0.358 ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|low_addressa[4] ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|low_addressa[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.577 ; +; 0.358 ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|low_addressa[3] ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|low_addressa[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.577 ; +; 0.358 ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|low_addressa[2] ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|low_addressa[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.577 ; +; 0.358 ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|low_addressa[1] ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|low_addressa[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.577 ; +; 0.358 ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|low_addressa[0] ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|low_addressa[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.577 ; +; 0.358 ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|b_full ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|b_full ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.577 ; ++-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Hold: 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[2]' ; ++-------+-------------------------------------------+-------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+-------------------------------------------+-------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ +; 0.361 ; heartbeat:inst_heartbeat|counter_data[0] ; heartbeat:inst_heartbeat|counter_data[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.062 ; 0.580 ; +; 0.390 ; heartbeat:inst_heartbeat|counter_data[21] ; heartbeat:inst_heartbeat|counter_data[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.063 ; 0.610 ; +; 0.548 ; heartbeat:inst_heartbeat|counter_data[8] ; heartbeat:inst_heartbeat|counter_data[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.062 ; 0.767 ; +; 0.548 ; heartbeat:inst_heartbeat|counter_data[10] ; heartbeat:inst_heartbeat|counter_data[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.062 ; 0.767 ; +; 0.548 ; heartbeat:inst_heartbeat|counter_data[14] ; heartbeat:inst_heartbeat|counter_data[14] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.063 ; 0.768 ; +; 0.549 ; heartbeat:inst_heartbeat|counter_data[6] ; heartbeat:inst_heartbeat|counter_data[6] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.062 ; 0.768 ; +; 0.549 ; heartbeat:inst_heartbeat|counter_data[12] ; heartbeat:inst_heartbeat|counter_data[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.063 ; 0.769 ; +; 0.549 ; heartbeat:inst_heartbeat|counter_data[16] ; heartbeat:inst_heartbeat|counter_data[16] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.063 ; 0.769 ; +; 0.550 ; heartbeat:inst_heartbeat|counter_data[17] ; heartbeat:inst_heartbeat|counter_data[17] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.063 ; 0.770 ; +; 0.551 ; heartbeat:inst_heartbeat|counter_data[11] ; heartbeat:inst_heartbeat|counter_data[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.063 ; 0.771 ; +; 0.552 ; heartbeat:inst_heartbeat|counter_data[2] ; heartbeat:inst_heartbeat|counter_data[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.062 ; 0.771 ; +; 0.552 ; heartbeat:inst_heartbeat|counter_data[4] ; heartbeat:inst_heartbeat|counter_data[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.062 ; 0.771 ; +; 0.552 ; heartbeat:inst_heartbeat|counter_data[9] ; heartbeat:inst_heartbeat|counter_data[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.062 ; 0.771 ; +; 0.552 ; heartbeat:inst_heartbeat|counter_data[13] ; heartbeat:inst_heartbeat|counter_data[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.063 ; 0.772 ; +; 0.552 ; heartbeat:inst_heartbeat|counter_data[18] ; heartbeat:inst_heartbeat|counter_data[18] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.063 ; 0.772 ; +; 0.552 ; heartbeat:inst_heartbeat|counter_data[20] ; heartbeat:inst_heartbeat|counter_data[20] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.063 ; 0.772 ; +; 0.553 ; heartbeat:inst_heartbeat|counter_data[7] ; heartbeat:inst_heartbeat|counter_data[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.062 ; 0.772 ; +; 0.553 ; heartbeat:inst_heartbeat|counter_data[15] ; heartbeat:inst_heartbeat|counter_data[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.063 ; 0.773 ; +; 0.554 ; heartbeat:inst_heartbeat|counter_data[3] ; heartbeat:inst_heartbeat|counter_data[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.062 ; 0.773 ; +; 0.554 ; heartbeat:inst_heartbeat|counter_data[5] ; heartbeat:inst_heartbeat|counter_data[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.062 ; 0.773 ; +; 0.554 ; heartbeat:inst_heartbeat|counter_data[19] ; heartbeat:inst_heartbeat|counter_data[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.063 ; 0.774 ; +; 0.562 ; heartbeat:inst_heartbeat|counter_data[0] ; heartbeat:inst_heartbeat|counter_data[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.062 ; 0.781 ; +; 0.564 ; heartbeat:inst_heartbeat|counter_data[1] ; heartbeat:inst_heartbeat|counter_data[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.062 ; 0.783 ; +; 0.823 ; heartbeat:inst_heartbeat|counter_data[8] ; heartbeat:inst_heartbeat|counter_data[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.062 ; 1.042 ; +; 0.823 ; heartbeat:inst_heartbeat|counter_data[12] ; heartbeat:inst_heartbeat|counter_data[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.063 ; 1.043 ; +; 0.823 ; heartbeat:inst_heartbeat|counter_data[14] ; heartbeat:inst_heartbeat|counter_data[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.063 ; 1.043 ; +; 0.824 ; heartbeat:inst_heartbeat|counter_data[16] ; heartbeat:inst_heartbeat|counter_data[17] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.063 ; 1.044 ; +; 0.824 ; heartbeat:inst_heartbeat|counter_data[10] ; heartbeat:inst_heartbeat|counter_data[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.061 ; 1.042 ; +; 0.824 ; heartbeat:inst_heartbeat|counter_data[6] ; heartbeat:inst_heartbeat|counter_data[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.062 ; 1.043 ; +; 0.826 ; heartbeat:inst_heartbeat|counter_data[20] ; heartbeat:inst_heartbeat|counter_data[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.063 ; 1.046 ; +; 0.826 ; heartbeat:inst_heartbeat|counter_data[2] ; heartbeat:inst_heartbeat|counter_data[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.062 ; 1.045 ; +; 0.826 ; heartbeat:inst_heartbeat|counter_data[4] ; heartbeat:inst_heartbeat|counter_data[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.062 ; 1.045 ; +; 0.826 ; heartbeat:inst_heartbeat|counter_data[18] ; heartbeat:inst_heartbeat|counter_data[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.063 ; 1.046 ; +; 0.838 ; heartbeat:inst_heartbeat|counter_data[11] ; heartbeat:inst_heartbeat|counter_data[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.063 ; 1.058 ; +; 0.838 ; heartbeat:inst_heartbeat|counter_data[1] ; heartbeat:inst_heartbeat|counter_data[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.062 ; 1.057 ; +; 0.838 ; heartbeat:inst_heartbeat|counter_data[17] ; heartbeat:inst_heartbeat|counter_data[18] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.063 ; 1.058 ; +; 0.839 ; heartbeat:inst_heartbeat|counter_data[9] ; heartbeat:inst_heartbeat|counter_data[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.062 ; 1.058 ; +; 0.839 ; heartbeat:inst_heartbeat|counter_data[13] ; heartbeat:inst_heartbeat|counter_data[14] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.063 ; 1.059 ; +; 0.840 ; heartbeat:inst_heartbeat|counter_data[7] ; heartbeat:inst_heartbeat|counter_data[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.062 ; 1.059 ; +; 0.840 ; heartbeat:inst_heartbeat|counter_data[15] ; heartbeat:inst_heartbeat|counter_data[16] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.063 ; 1.060 ; +; 0.840 ; heartbeat:inst_heartbeat|counter_data[11] ; heartbeat:inst_heartbeat|counter_data[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.063 ; 1.060 ; +; 0.840 ; heartbeat:inst_heartbeat|counter_data[1] ; heartbeat:inst_heartbeat|counter_data[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.062 ; 1.059 ; +; 0.840 ; heartbeat:inst_heartbeat|counter_data[17] ; heartbeat:inst_heartbeat|counter_data[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.063 ; 1.060 ; +; 0.840 ; heartbeat:inst_heartbeat|counter_data[0] ; heartbeat:inst_heartbeat|counter_data[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.062 ; 1.059 ; +; 0.841 ; heartbeat:inst_heartbeat|counter_data[5] ; heartbeat:inst_heartbeat|counter_data[6] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.062 ; 1.060 ; +; 0.841 ; heartbeat:inst_heartbeat|counter_data[3] ; heartbeat:inst_heartbeat|counter_data[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.062 ; 1.060 ; +; 0.841 ; heartbeat:inst_heartbeat|counter_data[19] ; heartbeat:inst_heartbeat|counter_data[20] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.063 ; 1.061 ; +; 0.841 ; heartbeat:inst_heartbeat|counter_data[13] ; heartbeat:inst_heartbeat|counter_data[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.063 ; 1.061 ; +; 0.842 ; heartbeat:inst_heartbeat|counter_data[7] ; heartbeat:inst_heartbeat|counter_data[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.062 ; 1.061 ; +; 0.842 ; heartbeat:inst_heartbeat|counter_data[15] ; heartbeat:inst_heartbeat|counter_data[17] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.063 ; 1.062 ; +; 0.842 ; heartbeat:inst_heartbeat|counter_data[9] ; heartbeat:inst_heartbeat|counter_data[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.061 ; 1.060 ; +; 0.842 ; heartbeat:inst_heartbeat|counter_data[0] ; heartbeat:inst_heartbeat|counter_data[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.062 ; 1.061 ; +; 0.843 ; heartbeat:inst_heartbeat|counter_data[5] ; heartbeat:inst_heartbeat|counter_data[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.062 ; 1.062 ; +; 0.843 ; heartbeat:inst_heartbeat|counter_data[19] ; heartbeat:inst_heartbeat|counter_data[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.063 ; 1.063 ; +; 0.843 ; heartbeat:inst_heartbeat|counter_data[3] ; heartbeat:inst_heartbeat|counter_data[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.062 ; 1.062 ; +; 0.933 ; heartbeat:inst_heartbeat|counter_data[8] ; heartbeat:inst_heartbeat|counter_data[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.062 ; 1.152 ; +; 0.933 ; heartbeat:inst_heartbeat|counter_data[12] ; heartbeat:inst_heartbeat|counter_data[14] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.063 ; 1.153 ; +; 0.933 ; heartbeat:inst_heartbeat|counter_data[14] ; heartbeat:inst_heartbeat|counter_data[16] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.063 ; 1.153 ; +; 0.934 ; heartbeat:inst_heartbeat|counter_data[10] ; heartbeat:inst_heartbeat|counter_data[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.061 ; 1.152 ; +; 0.934 ; heartbeat:inst_heartbeat|counter_data[16] ; heartbeat:inst_heartbeat|counter_data[18] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.063 ; 1.154 ; +; 0.934 ; heartbeat:inst_heartbeat|counter_data[6] ; heartbeat:inst_heartbeat|counter_data[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.062 ; 1.153 ; +; 0.935 ; heartbeat:inst_heartbeat|counter_data[12] ; heartbeat:inst_heartbeat|counter_data[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.063 ; 1.155 ; +; 0.935 ; heartbeat:inst_heartbeat|counter_data[14] ; heartbeat:inst_heartbeat|counter_data[17] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.063 ; 1.155 ; +; 0.936 ; heartbeat:inst_heartbeat|counter_data[10] ; heartbeat:inst_heartbeat|counter_data[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.061 ; 1.154 ; +; 0.936 ; heartbeat:inst_heartbeat|counter_data[16] ; heartbeat:inst_heartbeat|counter_data[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.063 ; 1.156 ; +; 0.936 ; heartbeat:inst_heartbeat|counter_data[4] ; heartbeat:inst_heartbeat|counter_data[6] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.062 ; 1.155 ; +; 0.936 ; heartbeat:inst_heartbeat|counter_data[2] ; heartbeat:inst_heartbeat|counter_data[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.062 ; 1.155 ; +; 0.936 ; heartbeat:inst_heartbeat|counter_data[18] ; heartbeat:inst_heartbeat|counter_data[20] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.063 ; 1.156 ; +; 0.936 ; heartbeat:inst_heartbeat|counter_data[6] ; heartbeat:inst_heartbeat|counter_data[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.062 ; 1.155 ; +; 0.936 ; heartbeat:inst_heartbeat|counter_data[8] ; heartbeat:inst_heartbeat|counter_data[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.061 ; 1.154 ; +; 0.938 ; heartbeat:inst_heartbeat|counter_data[4] ; heartbeat:inst_heartbeat|counter_data[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.062 ; 1.157 ; +; 0.938 ; heartbeat:inst_heartbeat|counter_data[18] ; heartbeat:inst_heartbeat|counter_data[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.063 ; 1.158 ; +; 0.938 ; heartbeat:inst_heartbeat|counter_data[2] ; heartbeat:inst_heartbeat|counter_data[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.062 ; 1.157 ; +; 0.950 ; heartbeat:inst_heartbeat|counter_data[11] ; heartbeat:inst_heartbeat|counter_data[14] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.063 ; 1.170 ; +; 0.950 ; heartbeat:inst_heartbeat|counter_data[1] ; heartbeat:inst_heartbeat|counter_data[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.062 ; 1.169 ; +; 0.950 ; heartbeat:inst_heartbeat|counter_data[17] ; heartbeat:inst_heartbeat|counter_data[20] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.063 ; 1.170 ; +; 0.951 ; heartbeat:inst_heartbeat|counter_data[13] ; heartbeat:inst_heartbeat|counter_data[16] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.063 ; 1.171 ; +; 0.952 ; heartbeat:inst_heartbeat|counter_data[7] ; heartbeat:inst_heartbeat|counter_data[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.062 ; 1.171 ; +; 0.952 ; heartbeat:inst_heartbeat|counter_data[9] ; heartbeat:inst_heartbeat|counter_data[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.061 ; 1.170 ; +; 0.952 ; heartbeat:inst_heartbeat|counter_data[15] ; heartbeat:inst_heartbeat|counter_data[18] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.063 ; 1.172 ; +; 0.952 ; heartbeat:inst_heartbeat|counter_data[11] ; heartbeat:inst_heartbeat|counter_data[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.063 ; 1.172 ; +; 0.952 ; heartbeat:inst_heartbeat|counter_data[17] ; heartbeat:inst_heartbeat|counter_data[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.063 ; 1.172 ; +; 0.952 ; heartbeat:inst_heartbeat|counter_data[1] ; heartbeat:inst_heartbeat|counter_data[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.062 ; 1.171 ; +; 0.952 ; heartbeat:inst_heartbeat|counter_data[0] ; heartbeat:inst_heartbeat|counter_data[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.062 ; 1.171 ; +; 0.953 ; heartbeat:inst_heartbeat|counter_data[5] ; heartbeat:inst_heartbeat|counter_data[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.062 ; 1.172 ; +; 0.953 ; heartbeat:inst_heartbeat|counter_data[13] ; heartbeat:inst_heartbeat|counter_data[17] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.063 ; 1.173 ; +; 0.953 ; heartbeat:inst_heartbeat|counter_data[3] ; heartbeat:inst_heartbeat|counter_data[6] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.062 ; 1.172 ; +; 0.954 ; heartbeat:inst_heartbeat|counter_data[9] ; heartbeat:inst_heartbeat|counter_data[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.061 ; 1.172 ; +; 0.954 ; heartbeat:inst_heartbeat|counter_data[15] ; heartbeat:inst_heartbeat|counter_data[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.063 ; 1.174 ; +; 0.954 ; heartbeat:inst_heartbeat|counter_data[0] ; heartbeat:inst_heartbeat|counter_data[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.062 ; 1.173 ; +; 0.955 ; heartbeat:inst_heartbeat|counter_data[5] ; heartbeat:inst_heartbeat|counter_data[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.062 ; 1.174 ; +; 0.955 ; heartbeat:inst_heartbeat|counter_data[7] ; heartbeat:inst_heartbeat|counter_data[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.061 ; 1.173 ; +; 0.955 ; heartbeat:inst_heartbeat|counter_data[3] ; heartbeat:inst_heartbeat|counter_data[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.062 ; 1.174 ; +; 1.045 ; heartbeat:inst_heartbeat|counter_data[12] ; heartbeat:inst_heartbeat|counter_data[16] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.063 ; 1.265 ; +; 1.045 ; heartbeat:inst_heartbeat|counter_data[14] ; heartbeat:inst_heartbeat|counter_data[18] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.063 ; 1.265 ; +; 1.046 ; heartbeat:inst_heartbeat|counter_data[10] ; heartbeat:inst_heartbeat|counter_data[14] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.061 ; 1.264 ; +; 1.046 ; heartbeat:inst_heartbeat|counter_data[16] ; heartbeat:inst_heartbeat|counter_data[20] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.063 ; 1.266 ; +; 1.046 ; heartbeat:inst_heartbeat|counter_data[6] ; heartbeat:inst_heartbeat|counter_data[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.062 ; 1.265 ; +; 1.046 ; heartbeat:inst_heartbeat|counter_data[8] ; heartbeat:inst_heartbeat|counter_data[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.061 ; 1.264 ; +; 1.047 ; heartbeat:inst_heartbeat|counter_data[12] ; heartbeat:inst_heartbeat|counter_data[17] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.063 ; 1.267 ; ++-------+-------------------------------------------+-------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Recovery: 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[0]' ; ++-------+-------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+-------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ +; 1.948 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[17] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.097 ; 2.950 ; +; 1.948 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.097 ; 2.950 ; +; 1.948 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.097 ; 2.950 ; +; 1.948 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.097 ; 2.950 ; +; 1.948 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.097 ; 2.950 ; +; 1.948 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[29] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.097 ; 2.950 ; +; 1.948 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[25] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.097 ; 2.950 ; +; 1.948 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.097 ; 2.950 ; +; 1.949 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[24] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.099 ; 2.947 ; +; 1.949 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.099 ; 2.947 ; +; 1.949 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.099 ; 2.947 ; +; 1.949 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[27] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.099 ; 2.947 ; +; 1.949 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.099 ; 2.947 ; +; 1.949 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[20] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.099 ; 2.947 ; +; 1.949 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.099 ; 2.947 ; +; 1.949 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[16] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.099 ; 2.947 ; +; 1.949 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[23] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.099 ; 2.947 ; +; 1.949 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[28] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.099 ; 2.947 ; +; 1.949 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.099 ; 2.947 ; +; 1.949 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.099 ; 2.947 ; +; 1.949 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.099 ; 2.947 ; +; 1.949 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.099 ; 2.947 ; +; 1.949 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.099 ; 2.947 ; +; 1.949 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[31] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.099 ; 2.947 ; +; 1.952 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[14] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.083 ; 2.960 ; +; 1.952 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[6] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.083 ; 2.960 ; +; 1.952 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[22] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.083 ; 2.960 ; +; 1.952 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[26] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.083 ; 2.960 ; +; 1.952 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.083 ; 2.960 ; +; 1.952 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[18] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.083 ; 2.960 ; +; 1.952 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.083 ; 2.960 ; +; 1.952 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[30] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.083 ; 2.960 ; +; 6.446 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.175 ; 3.271 ; +; 6.448 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.173 ; 3.271 ; +; 6.448 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.173 ; 3.271 ; +; 6.448 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.176 ; 3.268 ; +; 6.448 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.175 ; 3.269 ; +; 6.448 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.172 ; 3.272 ; +; 6.448 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.172 ; 3.272 ; +; 6.448 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[14] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.172 ; 3.272 ; +; 6.448 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.172 ; 3.272 ; +; 6.511 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.203 ; 3.178 ; +; 6.516 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.195 ; 3.181 ; +; 6.516 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[6] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.195 ; 3.181 ; +; 6.517 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.108 ; 3.275 ; +; 6.517 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.108 ; 3.275 ; +; 6.518 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.197 ; 3.177 ; +; 6.518 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.197 ; 3.177 ; +; 6.521 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.113 ; 3.266 ; +; 6.522 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.111 ; 3.267 ; +; 6.522 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.100 ; 3.278 ; +; 6.522 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[6] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.100 ; 3.278 ; +; 6.522 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.111 ; 3.267 ; +; 6.522 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.119 ; 3.259 ; +; 6.524 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.102 ; 3.274 ; +; 6.524 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.102 ; 3.274 ; +; 6.529 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.096 ; 3.273 ; +; 6.531 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.094 ; 3.273 ; +; 6.531 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.094 ; 3.273 ; +; 6.531 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.095 ; 3.272 ; +; 6.531 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.093 ; 3.274 ; +; 6.531 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.096 ; 3.271 ; +; 6.531 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[6] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.095 ; 3.272 ; +; 6.531 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.097 ; 3.270 ; +; 6.531 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.096 ; 3.271 ; +; 6.531 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.094 ; 3.273 ; +; 6.531 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.094 ; 3.273 ; +; 6.531 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.093 ; 3.274 ; +; 6.531 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.093 ; 3.274 ; +; 6.531 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.097 ; 3.270 ; +; 6.531 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.093 ; 3.274 ; +; 6.531 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[14] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.093 ; 3.274 ; +; 6.531 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_dqm[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.097 ; 3.270 ; +; 6.531 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_dqm[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.097 ; 3.270 ; +; 6.531 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_bank[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.094 ; 3.273 ; +; 6.532 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_bank[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.095 ; 3.271 ; +; 6.536 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.115 ; 3.249 ; +; 6.546 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.193 ; 3.153 ; +; 6.546 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.193 ; 3.153 ; +; 6.552 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.098 ; 3.250 ; +; 6.552 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.098 ; 3.250 ; +; 6.704 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_7 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.093 ; 3.082 ; +; 6.706 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_2 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.093 ; 3.080 ; +; 6.706 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_8 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.091 ; 3.082 ; +; 6.706 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_9 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.091 ; 3.082 ; +; 6.706 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_10 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.090 ; 3.083 ; +; 6.706 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_11 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.090 ; 3.083 ; +; 6.706 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_12 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.094 ; 3.079 ; +; 6.706 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_13 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.090 ; 3.083 ; +; 6.706 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_14 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.090 ; 3.083 ; +; 6.709 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_3 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.121 ; 3.050 ; +; 6.714 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_5 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.113 ; 3.053 ; +; 6.714 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_6 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.113 ; 3.053 ; +; 6.716 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_15 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.115 ; 3.049 ; +; 6.716 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_4 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.115 ; 3.049 ; +; 6.739 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_cmd[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.095 ; 3.064 ; +; 6.744 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.111 ; 3.025 ; +; 6.744 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_1 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.111 ; 3.025 ; +; 6.745 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_cmd[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.102 ; 3.053 ; +; 6.745 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_cmd[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.102 ; 3.053 ; ++-------+-------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Removal: 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[0]' ; ++-------+-------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+-------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ +; 2.209 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_uart_0:uart_0|system_uart_0_rx:the_system_uart_0_rx|altera_std_synchronizer:the_altera_std_synchronizer|dreg[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.425 ; 2.791 ; +; 2.209 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_uart_0:uart_0|system_uart_0_rx:the_system_uart_0_rx|delayed_unxsync_rxdxx1 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.425 ; 2.791 ; +; 2.209 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_uart_0:uart_0|system_uart_0_rx:the_system_uart_0_rx|do_start_rx ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.425 ; 2.791 ; +; 2.209 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_uart_0:uart_0|system_uart_0_rx:the_system_uart_0_rx|baud_rate_counter[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.425 ; 2.791 ; +; 2.209 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_uart_0:uart_0|system_uart_0_rx:the_system_uart_0_rx|baud_clk_en ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.425 ; 2.791 ; +; 2.539 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entries[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 2.758 ; +; 2.539 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][65] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 2.758 ; +; 2.539 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|use_reg ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 2.758 ; +; 2.539 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|count[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 2.758 ; +; 2.539 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|endofpacket_reg ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 2.758 ; +; 2.539 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 2.763 ; +; 2.539 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 2.763 ; +; 2.539 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 2.763 ; +; 2.539 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entries[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 2.758 ; +; 2.539 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_traffic_limiter:limiter|pending_response_count[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 2.763 ; +; 2.539 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_traffic_limiter:limiter|pending_response_count[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 2.763 ; +; 2.539 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_traffic_limiter:limiter|pending_response_count[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 2.763 ; +; 2.539 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|address_reg[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 2.758 ; +; 2.539 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 2.758 ; +; 2.539 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][54] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 2.758 ; +; 2.540 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|wr_address ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 2.759 ; +; 2.540 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|d_byteenable[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 2.759 ; +; 2.540 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|d_byteenable[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 2.759 ; +; 2.540 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|byteen_reg[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.061 ; 2.758 ; +; 2.540 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|byteen_reg[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.061 ; 2.758 ; +; 2.540 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_traffic_limiter:limiter|last_dest_id[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 2.764 ; +; 2.540 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|ic_fill_ap_offset[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 2.764 ; +; 2.540 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|ic_fill_ap_offset[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 2.764 ; +; 2.540 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|ic_fill_ap_offset[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 2.764 ; +; 2.540 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|ic_fill_line[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.066 ; 2.763 ; +; 2.540 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|ic_fill_line[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.066 ; 2.763 ; +; 2.540 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|ic_fill_ap_cnt[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 2.764 ; +; 2.540 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|ic_fill_ap_cnt[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 2.764 ; +; 2.540 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|ic_fill_ap_cnt[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 2.764 ; +; 2.540 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|ic_fill_ap_cnt[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 2.764 ; +; 2.540 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|i_read ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 2.764 ; +; 2.540 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_slave_translator:cpu_jtag_debug_module_translator|read_latency_shift_reg[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.064 ; 2.761 ; +; 2.540 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.064 ; 2.761 ; +; 2.540 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][83] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.064 ; 2.761 ; +; 2.540 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][83] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.064 ; 2.761 ; +; 2.540 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|address_reg[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.066 ; 2.763 ; +; 2.540 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|address_reg[16] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.066 ; 2.763 ; +; 2.540 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|address_reg[22] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.061 ; 2.758 ; +; 2.540 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|address_reg[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.066 ; 2.763 ; +; 2.540 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|address_reg[23] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.066 ; 2.763 ; +; 2.540 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|address_reg[14] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.066 ; 2.763 ; +; 2.540 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|address_reg[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.066 ; 2.763 ; +; 2.540 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|address_reg[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.066 ; 2.763 ; +; 2.540 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|address_reg[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.066 ; 2.763 ; +; 2.540 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|address_reg[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.066 ; 2.763 ; +; 2.540 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][102] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.064 ; 2.761 ; +; 2.540 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][102] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.064 ; 2.761 ; +; 2.540 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_traffic_limiter:limiter|pending_response_count[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 2.764 ; +; 2.540 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_traffic_limiter:limiter|has_pending_responses ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 2.764 ; +; 2.540 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux_001|packet_in_progress ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 2.759 ; +; 2.540 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux_001|saved_grant[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 2.759 ; +; 2.540 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.064 ; 2.761 ; +; 2.540 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|address_reg[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.061 ; 2.758 ; +; 2.540 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|address_reg[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.066 ; 2.763 ; +; 2.540 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|address_reg[6] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.066 ; 2.763 ; +; 2.540 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|address_reg[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.066 ; 2.763 ; +; 2.540 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|address_reg[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.066 ; 2.763 ; +; 2.540 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|data_reg[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.061 ; 2.758 ; +; 2.540 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|data_reg[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.061 ; 2.758 ; +; 2.540 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|data_reg[14] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.061 ; 2.758 ; +; 2.540 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|data_reg[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.061 ; 2.758 ; +; 2.545 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|refresh_counter[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.086 ; 2.788 ; +; 2.545 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|refresh_counter[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.086 ; 2.788 ; +; 2.545 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|refresh_counter[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.086 ; 2.788 ; +; 2.545 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|refresh_counter[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.086 ; 2.788 ; +; 2.546 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|E_pc[23] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 2.776 ; +; 2.546 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|D_iw[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.075 ; 2.778 ; +; 2.546 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|E_iw[16] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.081 ; 2.784 ; +; 2.546 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|E_iw[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.081 ; 2.784 ; +; 2.546 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|E_iw[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.081 ; 2.784 ; +; 2.546 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|E_iw[14] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.081 ; 2.784 ; +; 2.546 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|E_iw[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.081 ; 2.784 ; +; 2.546 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|M_ctrl_rdctl_inst ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.081 ; 2.784 ; +; 2.546 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|D_br_taken_waddr_partial[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.081 ; 2.784 ; +; 2.546 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|D_pc[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.075 ; 2.778 ; +; 2.546 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|E_pc[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.075 ; 2.778 ; +; 2.546 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|D_pc_plus_one[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.077 ; 2.780 ; +; 2.546 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|E_extra_pc[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.077 ; 2.780 ; +; 2.546 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|M_pipe_flush_waddr[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.071 ; 2.774 ; +; 2.546 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|F_pc[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.075 ; 2.778 ; +; 2.546 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|D_br_taken_waddr_partial[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.081 ; 2.784 ; +; 2.546 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|D_pc_plus_one[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.077 ; 2.780 ; +; 2.546 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|M_pipe_flush_waddr[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 2.776 ; +; 2.546 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|D_br_taken_waddr_partial[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.081 ; 2.784 ; +; 2.546 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|D_pc[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.081 ; 2.784 ; +; 2.546 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|D_iw[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.081 ; 2.784 ; +; 2.546 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|D_br_taken_waddr_partial[6] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.081 ; 2.784 ; +; 2.546 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|D_pc_plus_one[6] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.077 ; 2.780 ; +; 2.546 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|D_br_taken_waddr_partial[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.081 ; 2.784 ; +; 2.546 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|D_pc_plus_one[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.077 ; 2.780 ; +; 2.546 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|E_extra_pc[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.077 ; 2.780 ; +; 2.546 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|D_pc_plus_one[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.077 ; 2.780 ; +; 2.546 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|D_br_taken_waddr_partial[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.081 ; 2.784 ; +; 2.546 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|E_extra_pc[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.075 ; 2.778 ; +; 2.546 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|D_pc[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 2.776 ; ++-------+-------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Minimum Pulse Width: 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[0]' ; ++-------+--------------+----------------+-----------------+----------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; ++-------+--------------+----------------+-----------------+----------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; 4.693 ; 4.987 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[16] ; +; 4.693 ; 4.987 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[17] ; +; 4.693 ; 4.987 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[18] ; +; 4.693 ; 4.987 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[19] ; +; 4.693 ; 4.987 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[20] ; +; 4.693 ; 4.987 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[21] ; +; 4.693 ; 4.987 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[22] ; +; 4.693 ; 4.987 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[23] ; +; 4.693 ; 4.987 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[24] ; +; 4.693 ; 4.987 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[25] ; +; 4.693 ; 4.987 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[26] ; +; 4.693 ; 4.987 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[27] ; +; 4.693 ; 4.987 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[28] ; +; 4.693 ; 4.987 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[29] ; +; 4.693 ; 4.987 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[30] ; +; 4.693 ; 4.987 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[31] ; +; 4.693 ; 4.987 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[0]~_Duplicate_1 ; +; 4.693 ; 4.987 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[10]~_Duplicate_1 ; +; 4.693 ; 4.987 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[11]~_Duplicate_1 ; +; 4.693 ; 4.987 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[12]~_Duplicate_1 ; +; 4.693 ; 4.987 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[13]~_Duplicate_1 ; +; 4.693 ; 4.987 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[14]~_Duplicate_1 ; +; 4.693 ; 4.987 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[15]~_Duplicate_1 ; +; 4.693 ; 4.987 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[1]~_Duplicate_1 ; +; 4.693 ; 4.987 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[2]~_Duplicate_1 ; +; 4.693 ; 4.987 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[3]~_Duplicate_1 ; +; 4.693 ; 4.987 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[4]~_Duplicate_1 ; +; 4.693 ; 4.987 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[5]~_Duplicate_1 ; +; 4.693 ; 4.987 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[6]~_Duplicate_1 ; +; 4.693 ; 4.987 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[7]~_Duplicate_1 ; +; 4.693 ; 4.987 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[8]~_Duplicate_1 ; +; 4.693 ; 4.987 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[9]~_Duplicate_1 ; +; 4.693 ; 4.987 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3 ; +; 4.693 ; 4.987 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT1 ; +; 4.693 ; 4.987 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT10 ; +; 4.693 ; 4.987 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT11 ; +; 4.693 ; 4.987 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT12 ; +; 4.693 ; 4.987 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT13 ; +; 4.693 ; 4.987 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT14 ; +; 4.693 ; 4.987 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT15 ; +; 4.693 ; 4.987 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT2 ; +; 4.693 ; 4.987 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT3 ; +; 4.693 ; 4.987 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT4 ; +; 4.693 ; 4.987 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT5 ; +; 4.693 ; 4.987 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT6 ; +; 4.693 ; 4.987 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT7 ; +; 4.693 ; 4.987 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT8 ; +; 4.693 ; 4.987 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT9 ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[0] ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[10] ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[11] ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[12] ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[13] ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[14] ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[15] ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[1] ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[2] ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[3] ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[4] ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[5] ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[6] ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[7] ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[8] ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[9] ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[0] ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[10] ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[11] ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[12] ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[13] ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[14] ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[15] ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[1] ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[2] ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[3] ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[4] ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[5] ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[6] ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[7] ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[8] ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[9] ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3 ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT1 ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT10 ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT11 ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT12 ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT13 ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT14 ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT15 ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT16 ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT17 ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT18 ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT19 ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT2 ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT20 ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT21 ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT22 ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT23 ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT24 ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT25 ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT26 ; ++-------+--------------+----------------+-----------------+----------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Minimum Pulse Width: 'CLOCK_50' ; ++--------+--------------+----------------+------------------+----------+------------+--------------------------------------------------------------------+ +; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; ++--------+--------------+----------------+------------------+----------+------------+--------------------------------------------------------------------+ +; 9.835 ; 9.835 ; 0.000 ; Low Pulse Width ; CLOCK_50 ; Rise ; CLOCK_50~input|o ; +; 9.839 ; 9.839 ; 0.000 ; Low Pulse Width ; CLOCK_50 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; 9.839 ; 9.839 ; 0.000 ; Low Pulse Width ; CLOCK_50 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[1] ; +; 9.839 ; 9.839 ; 0.000 ; Low Pulse Width ; CLOCK_50 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; +; 9.839 ; 9.839 ; 0.000 ; Low Pulse Width ; CLOCK_50 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|observablevcoout ; +; 9.859 ; 9.859 ; 0.000 ; Low Pulse Width ; CLOCK_50 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|inclk[0] ; +; 10.000 ; 10.000 ; 0.000 ; High Pulse Width ; CLOCK_50 ; Rise ; CLOCK_50~input|i ; +; 10.000 ; 10.000 ; 0.000 ; Low Pulse Width ; CLOCK_50 ; Rise ; CLOCK_50~input|i ; +; 10.140 ; 10.140 ; 0.000 ; High Pulse Width ; CLOCK_50 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|inclk[0] ; +; 10.160 ; 10.160 ; 0.000 ; High Pulse Width ; CLOCK_50 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; 10.160 ; 10.160 ; 0.000 ; High Pulse Width ; CLOCK_50 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[1] ; +; 10.160 ; 10.160 ; 0.000 ; High Pulse Width ; CLOCK_50 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; +; 10.160 ; 10.160 ; 0.000 ; High Pulse Width ; CLOCK_50 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|observablevcoout ; +; 10.165 ; 10.165 ; 0.000 ; High Pulse Width ; CLOCK_50 ; Rise ; CLOCK_50~input|o ; +; 16.000 ; 20.000 ; 4.000 ; Port Rate ; CLOCK_50 ; Rise ; CLOCK_50 ; ++--------+--------------+----------------+------------------+----------+------------+--------------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Minimum Pulse Width: 'altera_reserved_tck' ; ++--------+--------------+----------------+------------------+---------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; ++--------+--------------+----------------+------------------+---------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; 49.624 ; 49.840 ; 0.216 ; High Pulse Width ; altera_reserved_tck ; Fall ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|tdo~reg0 ; +; 49.625 ; 49.841 ; 0.216 ; High Pulse Width ; altera_reserved_tck ; Fall ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|jupdate ; +; 49.626 ; 49.842 ; 0.216 ; High Pulse Width ; altera_reserved_tck ; Fall ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; +; 49.671 ; 49.855 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|count[0] ; +; 49.671 ; 49.855 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|count[1] ; +; 49.671 ; 49.855 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|count[5] ; +; 49.671 ; 49.855 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|count[6] ; +; 49.671 ; 49.855 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|count[7] ; +; 49.671 ; 49.855 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|count[8] ; +; 49.671 ; 49.855 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|count[9] ; +; 49.671 ; 49.855 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|read ; +; 49.671 ; 49.855 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|read_req ; +; 49.671 ; 49.855 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|state ; +; 49.671 ; 49.855 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|tck_t_dav ; +; 49.671 ; 49.855 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|td_shift[0] ; +; 49.671 ; 49.855 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|td_shift[10] ; +; 49.671 ; 49.855 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|td_shift[9] ; +; 49.671 ; 49.855 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|user_saw_rvalid ; +; 49.671 ; 49.855 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|wdata[0] ; +; 49.671 ; 49.855 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|write_stalled ; +; 49.671 ; 49.855 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|write_valid ; +; 49.672 ; 49.856 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0] ; +; 49.672 ; 49.856 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0] ; +; 49.672 ; 49.856 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1] ; +; 49.672 ; 49.856 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2] ; +; 49.672 ; 49.856 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[3] ; +; 49.672 ; 49.856 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4] ; +; 49.672 ; 49.856 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[0] ; +; 49.672 ; 49.856 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[1] ; +; 49.672 ; 49.856 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[2] ; +; 49.672 ; 49.856 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo_bypass_reg ; +; 49.672 ; 49.856 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|DRsize.000 ; +; 49.672 ; 49.856 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|DRsize.010 ; +; 49.672 ; 49.856 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|DRsize.100 ; +; 49.672 ; 49.856 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|din_s1 ; +; 49.672 ; 49.856 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|dreg[0] ; +; 49.672 ; 49.856 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 ; +; 49.672 ; 49.856 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer|dreg[0] ; +; 49.672 ; 49.856 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|ir_out[0] ; +; 49.672 ; 49.856 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|ir_out[1] ; +; 49.672 ; 49.856 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[0] ; +; 49.672 ; 49.856 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[16] ; +; 49.672 ; 49.856 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[17] ; +; 49.672 ; 49.856 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[18] ; +; 49.672 ; 49.856 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[19] ; +; 49.672 ; 49.856 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[20] ; +; 49.672 ; 49.856 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[21] ; +; 49.672 ; 49.856 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[22] ; +; 49.672 ; 49.856 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[23] ; +; 49.672 ; 49.856 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[24] ; +; 49.672 ; 49.856 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[30] ; +; 49.672 ; 49.856 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[32] ; +; 49.672 ; 49.856 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[36] ; +; 49.672 ; 49.856 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[37] ; +; 49.672 ; 49.856 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|wdata[1] ; +; 49.672 ; 49.856 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|wdata[2] ; +; 49.672 ; 49.856 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|wdata[3] ; +; 49.672 ; 49.856 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|wdata[4] ; +; 49.672 ; 49.856 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|wdata[5] ; +; 49.672 ; 49.856 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|wdata[6] ; +; 49.672 ; 49.856 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|wdata[7] ; +; 49.672 ; 49.856 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|write ; +; 49.673 ; 49.857 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; +; 49.673 ; 49.857 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[0] ; +; 49.673 ; 49.857 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[1] ; +; 49.673 ; 49.857 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[2] ; +; 49.673 ; 49.857 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[3] ; +; 49.673 ; 49.857 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[0] ; +; 49.673 ; 49.857 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[1] ; +; 49.673 ; 49.857 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[2] ; +; 49.673 ; 49.857 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[3] ; +; 49.673 ; 49.857 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1] ; +; 49.673 ; 49.857 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2] ; +; 49.673 ; 49.857 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[0] ; +; 49.673 ; 49.857 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[1] ; +; 49.673 ; 49.857 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[2] ; +; 49.673 ; 49.857 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[3] ; +; 49.673 ; 49.857 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[0] ; +; 49.673 ; 49.857 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[1] ; +; 49.673 ; 49.857 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[2] ; +; 49.673 ; 49.857 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[3] ; +; 49.673 ; 49.857 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0] ; +; 49.673 ; 49.857 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1] ; +; 49.673 ; 49.857 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2] ; +; 49.673 ; 49.857 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3] ; +; 49.673 ; 49.857 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4] ; +; 49.673 ; 49.857 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0] ; +; 49.673 ; 49.857 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1] ; +; 49.673 ; 49.857 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2] ; +; 49.673 ; 49.857 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3] ; +; 49.673 ; 49.857 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4] ; +; 49.673 ; 49.857 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; +; 49.673 ; 49.857 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6] ; +; 49.673 ; 49.857 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[0] ; +; 49.673 ; 49.857 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1] ; +; 49.673 ; 49.857 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2] ; +; 49.673 ; 49.857 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[3] ; +; 49.673 ; 49.857 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[4] ; +; 49.673 ; 49.857 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[5] ; +; 49.673 ; 49.857 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[6] ; ++--------+--------------+----------------+------------------+---------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Minimum Pulse Width: 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[2]' ; ++--------+--------------+----------------+------------------+----------------------------------------------------------+------------+--------------------------------------------------------------------------------+ +; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; ++--------+--------------+----------------+------------------+----------------------------------------------------------+------------+--------------------------------------------------------------------------------+ +; 49.747 ; 49.963 ; 0.216 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[0] ; +; 49.747 ; 49.963 ; 0.216 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[10] ; +; 49.747 ; 49.963 ; 0.216 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[11] ; +; 49.747 ; 49.963 ; 0.216 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[12] ; +; 49.747 ; 49.963 ; 0.216 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[13] ; +; 49.747 ; 49.963 ; 0.216 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[14] ; +; 49.747 ; 49.963 ; 0.216 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[15] ; +; 49.747 ; 49.963 ; 0.216 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[16] ; +; 49.747 ; 49.963 ; 0.216 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[17] ; +; 49.747 ; 49.963 ; 0.216 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[18] ; +; 49.747 ; 49.963 ; 0.216 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[19] ; +; 49.747 ; 49.963 ; 0.216 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[1] ; +; 49.747 ; 49.963 ; 0.216 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[20] ; +; 49.747 ; 49.963 ; 0.216 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[21] ; +; 49.747 ; 49.963 ; 0.216 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[2] ; +; 49.747 ; 49.963 ; 0.216 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[3] ; +; 49.747 ; 49.963 ; 0.216 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[4] ; +; 49.747 ; 49.963 ; 0.216 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[5] ; +; 49.747 ; 49.963 ; 0.216 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[6] ; +; 49.747 ; 49.963 ; 0.216 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[7] ; +; 49.747 ; 49.963 ; 0.216 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[8] ; +; 49.747 ; 49.963 ; 0.216 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[9] ; +; 49.851 ; 50.035 ; 0.184 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[0] ; +; 49.851 ; 50.035 ; 0.184 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[10] ; +; 49.851 ; 50.035 ; 0.184 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[1] ; +; 49.851 ; 50.035 ; 0.184 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[2] ; +; 49.851 ; 50.035 ; 0.184 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[3] ; +; 49.851 ; 50.035 ; 0.184 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[4] ; +; 49.851 ; 50.035 ; 0.184 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[5] ; +; 49.851 ; 50.035 ; 0.184 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[6] ; +; 49.851 ; 50.035 ; 0.184 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[7] ; +; 49.851 ; 50.035 ; 0.184 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[8] ; +; 49.851 ; 50.035 ; 0.184 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[9] ; +; 49.852 ; 50.036 ; 0.184 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[11] ; +; 49.852 ; 50.036 ; 0.184 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[12] ; +; 49.852 ; 50.036 ; 0.184 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[13] ; +; 49.852 ; 50.036 ; 0.184 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[14] ; +; 49.852 ; 50.036 ; 0.184 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[15] ; +; 49.852 ; 50.036 ; 0.184 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[16] ; +; 49.852 ; 50.036 ; 0.184 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[17] ; +; 49.852 ; 50.036 ; 0.184 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[18] ; +; 49.852 ; 50.036 ; 0.184 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[19] ; +; 49.852 ; 50.036 ; 0.184 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[20] ; +; 49.852 ; 50.036 ; 0.184 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[21] ; +; 49.982 ; 49.982 ; 0.000 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_pll_sys|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl|inclk[0] ; +; 49.982 ; 49.982 ; 0.000 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_pll_sys|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl|outclk ; +; 49.986 ; 49.986 ; 0.000 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[11]|clk ; +; 49.986 ; 49.986 ; 0.000 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[12]|clk ; +; 49.986 ; 49.986 ; 0.000 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[13]|clk ; +; 49.986 ; 49.986 ; 0.000 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[14]|clk ; +; 49.986 ; 49.986 ; 0.000 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[15]|clk ; +; 49.986 ; 49.986 ; 0.000 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[16]|clk ; +; 49.986 ; 49.986 ; 0.000 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[17]|clk ; +; 49.986 ; 49.986 ; 0.000 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[18]|clk ; +; 49.986 ; 49.986 ; 0.000 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[19]|clk ; +; 49.986 ; 49.986 ; 0.000 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[20]|clk ; +; 49.986 ; 49.986 ; 0.000 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[21]|clk ; +; 49.987 ; 49.987 ; 0.000 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[0]|clk ; +; 49.987 ; 49.987 ; 0.000 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[10]|clk ; +; 49.987 ; 49.987 ; 0.000 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[1]|clk ; +; 49.987 ; 49.987 ; 0.000 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[2]|clk ; +; 49.987 ; 49.987 ; 0.000 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[3]|clk ; +; 49.987 ; 49.987 ; 0.000 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[4]|clk ; +; 49.987 ; 49.987 ; 0.000 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[5]|clk ; +; 49.987 ; 49.987 ; 0.000 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[6]|clk ; +; 49.987 ; 49.987 ; 0.000 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[7]|clk ; +; 49.987 ; 49.987 ; 0.000 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[8]|clk ; +; 49.987 ; 49.987 ; 0.000 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[9]|clk ; +; 50.013 ; 50.013 ; 0.000 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[0]|clk ; +; 50.013 ; 50.013 ; 0.000 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[10]|clk ; +; 50.013 ; 50.013 ; 0.000 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[11]|clk ; +; 50.013 ; 50.013 ; 0.000 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[12]|clk ; +; 50.013 ; 50.013 ; 0.000 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[13]|clk ; +; 50.013 ; 50.013 ; 0.000 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[14]|clk ; +; 50.013 ; 50.013 ; 0.000 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[15]|clk ; +; 50.013 ; 50.013 ; 0.000 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[16]|clk ; +; 50.013 ; 50.013 ; 0.000 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[17]|clk ; +; 50.013 ; 50.013 ; 0.000 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[18]|clk ; +; 50.013 ; 50.013 ; 0.000 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[19]|clk ; +; 50.013 ; 50.013 ; 0.000 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[1]|clk ; +; 50.013 ; 50.013 ; 0.000 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[20]|clk ; +; 50.013 ; 50.013 ; 0.000 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[21]|clk ; +; 50.013 ; 50.013 ; 0.000 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[2]|clk ; +; 50.013 ; 50.013 ; 0.000 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[3]|clk ; +; 50.013 ; 50.013 ; 0.000 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[4]|clk ; +; 50.013 ; 50.013 ; 0.000 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[5]|clk ; +; 50.013 ; 50.013 ; 0.000 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[6]|clk ; +; 50.013 ; 50.013 ; 0.000 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[7]|clk ; +; 50.013 ; 50.013 ; 0.000 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[8]|clk ; +; 50.013 ; 50.013 ; 0.000 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[9]|clk ; +; 50.017 ; 50.017 ; 0.000 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_pll_sys|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl|inclk[0] ; +; 50.017 ; 50.017 ; 0.000 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_pll_sys|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl|outclk ; +; 98.000 ; 100.000 ; 2.000 ; Min Period ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[0] ; +; 98.000 ; 100.000 ; 2.000 ; Min Period ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[10] ; +; 98.000 ; 100.000 ; 2.000 ; Min Period ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[11] ; +; 98.000 ; 100.000 ; 2.000 ; Min Period ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[12] ; +; 98.000 ; 100.000 ; 2.000 ; Min Period ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[13] ; +; 98.000 ; 100.000 ; 2.000 ; Min Period ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[14] ; +; 98.000 ; 100.000 ; 2.000 ; Min Period ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[15] ; +; 98.000 ; 100.000 ; 2.000 ; Min Period ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[16] ; ++--------+--------------+----------------+------------------+----------------------------------------------------------+------------+--------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------+ +; Setup Times ; ++---------------------+---------------------+-------+-------+------------+----------------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++---------------------+---------------------+-------+-------+------------+----------------------------------------------------------+ +; altera_reserved_tdi ; altera_reserved_tck ; 1.540 ; 1.685 ; Rise ; altera_reserved_tck ; +; altera_reserved_tms ; altera_reserved_tck ; 6.826 ; 7.042 ; Rise ; altera_reserved_tck ; +; DRAM_DQ[*] ; CLOCK_50 ; 1.013 ; 1.177 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 1.013 ; 1.177 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 1.013 ; 1.177 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 0.978 ; 1.140 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 1.007 ; 1.171 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 1.001 ; 1.165 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 0.999 ; 1.163 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 0.999 ; 1.163 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 0.978 ; 1.140 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 0.976 ; 1.138 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 0.976 ; 1.138 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 0.975 ; 1.137 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 0.975 ; 1.137 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 0.979 ; 1.141 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 0.975 ; 1.137 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 0.975 ; 1.137 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[15] ; CLOCK_50 ; 1.001 ; 1.165 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_1[*] ; CLOCK_50 ; 5.109 ; 5.617 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_1[24] ; CLOCK_50 ; 5.109 ; 5.617 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; KEY[*] ; CLOCK_50 ; 4.087 ; 4.551 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; KEY[0] ; CLOCK_50 ; 4.087 ; 4.551 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; KEY[1] ; CLOCK_50 ; 1.744 ; 1.888 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; SW[*] ; CLOCK_50 ; 2.209 ; 2.309 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; SW[0] ; CLOCK_50 ; 1.879 ; 2.052 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; SW[1] ; CLOCK_50 ; 2.209 ; 2.309 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; SW[2] ; CLOCK_50 ; 2.186 ; 2.302 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; SW[3] ; CLOCK_50 ; 2.153 ; 2.300 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ++---------------------+---------------------+-------+-------+------------+----------------------------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------+ +; Hold Times ; ++---------------------+---------------------+--------+--------+------------+----------------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++---------------------+---------------------+--------+--------+------------+----------------------------------------------------------+ +; altera_reserved_tdi ; altera_reserved_tck ; 1.006 ; 0.867 ; Rise ; altera_reserved_tck ; +; altera_reserved_tms ; altera_reserved_tck ; -1.069 ; -1.185 ; Rise ; altera_reserved_tck ; +; DRAM_DQ[*] ; CLOCK_50 ; -0.451 ; -0.614 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; -0.486 ; -0.650 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; -0.486 ; -0.650 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; -0.453 ; -0.616 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; -0.479 ; -0.643 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; -0.474 ; -0.638 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; -0.472 ; -0.636 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; -0.472 ; -0.636 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; -0.454 ; -0.617 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; -0.452 ; -0.615 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; -0.451 ; -0.614 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; -0.451 ; -0.614 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; -0.451 ; -0.614 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; -0.455 ; -0.618 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; -0.451 ; -0.614 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; -0.451 ; -0.614 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[15] ; CLOCK_50 ; -0.474 ; -0.638 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_1[*] ; CLOCK_50 ; -4.203 ; -4.746 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_1[24] ; CLOCK_50 ; -4.203 ; -4.746 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; KEY[*] ; CLOCK_50 ; -1.141 ; -1.276 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; KEY[0] ; CLOCK_50 ; -3.386 ; -3.826 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; KEY[1] ; CLOCK_50 ; -1.141 ; -1.276 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; SW[*] ; CLOCK_50 ; -1.271 ; -1.434 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; SW[0] ; CLOCK_50 ; -1.271 ; -1.434 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; SW[1] ; CLOCK_50 ; -1.587 ; -1.680 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; SW[2] ; CLOCK_50 ; -1.566 ; -1.674 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; SW[3] ; CLOCK_50 ; -1.533 ; -1.672 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ++---------------------+---------------------+--------+--------+------------+----------------------------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------+ +; Clock to Output Times ; ++---------------------+---------------------+--------+--------+------------+----------------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++---------------------+---------------------+--------+--------+------------+----------------------------------------------------------+ +; altera_reserved_tdo ; altera_reserved_tck ; 10.799 ; 11.453 ; Fall ; altera_reserved_tck ; +; DRAM_ADDR[*] ; CLOCK_50 ; 3.074 ; 3.045 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[0] ; CLOCK_50 ; 3.070 ; 3.041 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[1] ; CLOCK_50 ; 2.995 ; 2.967 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[2] ; CLOCK_50 ; 2.995 ; 2.967 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[3] ; CLOCK_50 ; 2.994 ; 2.966 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[4] ; CLOCK_50 ; 2.997 ; 2.969 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[5] ; CLOCK_50 ; 2.994 ; 2.966 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[6] ; CLOCK_50 ; 2.994 ; 2.966 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[7] ; CLOCK_50 ; 2.992 ; 2.964 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[8] ; CLOCK_50 ; 2.974 ; 2.952 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[9] ; CLOCK_50 ; 3.070 ; 3.041 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[10] ; CLOCK_50 ; 3.061 ; 3.032 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[11] ; CLOCK_50 ; 3.074 ; 3.045 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[12] ; CLOCK_50 ; 2.972 ; 2.950 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_BA[*] ; CLOCK_50 ; 2.995 ; 2.967 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_BA[0] ; CLOCK_50 ; 2.994 ; 2.966 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_BA[1] ; CLOCK_50 ; 2.995 ; 2.967 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CAS_N ; CLOCK_50 ; 3.079 ; 3.050 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CS_N ; CLOCK_50 ; 4.281 ; 4.335 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[*] ; CLOCK_50 ; 3.081 ; 3.052 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 3.067 ; 3.038 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 3.067 ; 3.038 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 2.994 ; 2.966 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 2.980 ; 2.958 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 3.079 ; 3.050 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 3.081 ; 3.052 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 3.081 ; 3.052 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 2.993 ; 2.965 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 2.995 ; 2.967 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 2.996 ; 2.968 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 2.996 ; 2.968 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 2.996 ; 2.968 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 2.992 ; 2.964 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 2.996 ; 2.968 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 2.996 ; 2.968 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[15] ; CLOCK_50 ; 3.079 ; 3.050 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQM[*] ; CLOCK_50 ; 2.992 ; 2.964 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQM[0] ; CLOCK_50 ; 2.992 ; 2.964 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQM[1] ; CLOCK_50 ; 2.992 ; 2.964 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_RAS_N ; CLOCK_50 ; 3.079 ; 3.050 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_WE_N ; CLOCK_50 ; 3.075 ; 3.046 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_0[*] ; CLOCK_50 ; 5.512 ; 5.381 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_0[0] ; CLOCK_50 ; 5.512 ; 5.381 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_1[*] ; CLOCK_50 ; 5.981 ; 6.138 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_1[12] ; CLOCK_50 ; 4.896 ; 4.968 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_1[26] ; CLOCK_50 ; 5.981 ; 6.138 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[*] ; CLOCK_50 ; 6.466 ; 6.621 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[0] ; CLOCK_50 ; 6.006 ; 6.094 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[1] ; CLOCK_50 ; 5.468 ; 5.608 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[2] ; CLOCK_50 ; 5.578 ; 5.648 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[3] ; CLOCK_50 ; 5.786 ; 5.865 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[4] ; CLOCK_50 ; 4.558 ; 4.618 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[5] ; CLOCK_50 ; 6.466 ; 6.621 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[6] ; CLOCK_50 ; 4.768 ; 4.781 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CLK ; CLOCK_50 ; 1.192 ; ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[1] ; +; DRAM_CLK ; CLOCK_50 ; ; 1.152 ; Fall ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[1] ; +; LED[*] ; CLOCK_50 ; 4.715 ; 4.828 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; +; LED[7] ; CLOCK_50 ; 4.715 ; 4.828 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; ++---------------------+---------------------+--------+--------+------------+----------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------+ +; Minimum Clock to Output Times ; ++---------------------+---------------------+-------+-------+------------+----------------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++---------------------+---------------------+-------+-------+------------+----------------------------------------------------------+ +; altera_reserved_tdo ; altera_reserved_tck ; 8.581 ; 9.235 ; Fall ; altera_reserved_tck ; +; DRAM_ADDR[*] ; CLOCK_50 ; 2.572 ; 2.550 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[0] ; CLOCK_50 ; 2.670 ; 2.641 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[1] ; CLOCK_50 ; 2.596 ; 2.568 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[2] ; CLOCK_50 ; 2.596 ; 2.568 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[3] ; CLOCK_50 ; 2.595 ; 2.567 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[4] ; CLOCK_50 ; 2.597 ; 2.569 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[5] ; CLOCK_50 ; 2.594 ; 2.566 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[6] ; CLOCK_50 ; 2.595 ; 2.567 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[7] ; CLOCK_50 ; 2.593 ; 2.565 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[8] ; CLOCK_50 ; 2.574 ; 2.552 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[9] ; CLOCK_50 ; 2.670 ; 2.641 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[10] ; CLOCK_50 ; 2.662 ; 2.633 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[11] ; CLOCK_50 ; 2.673 ; 2.644 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[12] ; CLOCK_50 ; 2.572 ; 2.550 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_BA[*] ; CLOCK_50 ; 2.595 ; 2.567 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_BA[0] ; CLOCK_50 ; 2.595 ; 2.567 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_BA[1] ; CLOCK_50 ; 2.596 ; 2.568 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CAS_N ; CLOCK_50 ; 2.679 ; 2.650 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CS_N ; CLOCK_50 ; 3.882 ; 3.936 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[*] ; CLOCK_50 ; 2.579 ; 2.557 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 2.667 ; 2.638 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 2.667 ; 2.638 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 2.594 ; 2.566 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 2.579 ; 2.557 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 2.679 ; 2.650 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 2.681 ; 2.652 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 2.681 ; 2.652 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 2.594 ; 2.566 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 2.596 ; 2.568 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 2.596 ; 2.568 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 2.597 ; 2.569 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 2.597 ; 2.569 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 2.593 ; 2.565 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 2.597 ; 2.569 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 2.597 ; 2.569 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[15] ; CLOCK_50 ; 2.679 ; 2.650 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQM[*] ; CLOCK_50 ; 2.593 ; 2.565 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQM[0] ; CLOCK_50 ; 2.593 ; 2.565 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQM[1] ; CLOCK_50 ; 2.593 ; 2.565 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_RAS_N ; CLOCK_50 ; 2.679 ; 2.650 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_WE_N ; CLOCK_50 ; 2.675 ; 2.646 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_0[*] ; CLOCK_50 ; 4.940 ; 4.815 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_0[0] ; CLOCK_50 ; 4.940 ; 4.815 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_1[*] ; CLOCK_50 ; 4.350 ; 4.418 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_1[12] ; CLOCK_50 ; 4.350 ; 4.418 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_1[26] ; CLOCK_50 ; 5.441 ; 5.594 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[*] ; CLOCK_50 ; 4.027 ; 4.084 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[0] ; CLOCK_50 ; 5.416 ; 5.499 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[1] ; CLOCK_50 ; 4.900 ; 5.033 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[2] ; CLOCK_50 ; 5.005 ; 5.071 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[3] ; CLOCK_50 ; 5.204 ; 5.279 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[4] ; CLOCK_50 ; 4.027 ; 4.084 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[5] ; CLOCK_50 ; 5.907 ; 6.059 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[6] ; CLOCK_50 ; 4.226 ; 4.237 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CLK ; CLOCK_50 ; 0.743 ; ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[1] ; +; DRAM_CLK ; CLOCK_50 ; ; 0.704 ; Fall ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[1] ; +; LED[*] ; CLOCK_50 ; 4.224 ; 4.336 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; +; LED[7] ; CLOCK_50 ; 4.224 ; 4.336 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; ++---------------------+---------------------+-------+-------+------------+----------------------------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------+ +; Output Enable Times ; ++--------------+------------+-------+-------+------------+----------------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++--------------+------------+-------+-------+------------+----------------------------------------------------------+ +; DRAM_DQ[*] ; CLOCK_50 ; 2.812 ; 2.736 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 2.898 ; 2.825 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 2.898 ; 2.825 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 2.817 ; 2.738 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 2.812 ; 2.748 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 2.910 ; 2.837 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 2.912 ; 2.839 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 2.912 ; 2.839 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 2.816 ; 2.737 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 2.818 ; 2.739 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 2.819 ; 2.740 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 2.819 ; 2.740 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 2.819 ; 2.740 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 2.815 ; 2.736 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 2.819 ; 2.740 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 2.819 ; 2.740 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[15] ; CLOCK_50 ; 2.910 ; 2.837 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ++--------------+------------+-------+-------+------------+----------------------------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------+ +; Minimum Output Enable Times ; ++--------------+------------+-------+-------+------------+----------------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++--------------+------------+-------+-------+------------+----------------------------------------------------------+ +; DRAM_DQ[*] ; CLOCK_50 ; 2.413 ; 2.339 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 2.500 ; 2.427 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 2.500 ; 2.427 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 2.419 ; 2.340 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 2.413 ; 2.349 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 2.512 ; 2.439 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 2.514 ; 2.441 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 2.514 ; 2.441 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 2.419 ; 2.340 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 2.421 ; 2.342 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 2.421 ; 2.342 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 2.422 ; 2.343 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 2.422 ; 2.343 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 2.418 ; 2.339 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 2.422 ; 2.343 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 2.422 ; 2.343 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[15] ; CLOCK_50 ; 2.512 ; 2.439 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ++--------------+------------+-------+-------+------------+----------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------+ +; Output Disable Times ; ++--------------+------------+-----------+-----------+------------+----------------------------------------------------------+ +; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ; ++--------------+------------+-----------+-----------+------------+----------------------------------------------------------+ +; DRAM_DQ[*] ; CLOCK_50 ; 2.770 ; 2.849 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 2.883 ; 2.956 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 2.883 ; 2.956 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 2.772 ; 2.851 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 2.806 ; 2.870 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 2.895 ; 2.968 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 2.897 ; 2.970 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 2.897 ; 2.970 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 2.771 ; 2.850 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 2.773 ; 2.852 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 2.774 ; 2.853 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 2.774 ; 2.853 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 2.774 ; 2.853 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 2.770 ; 2.849 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 2.774 ; 2.853 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 2.774 ; 2.853 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[15] ; CLOCK_50 ; 2.895 ; 2.968 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ++--------------+------------+-----------+-----------+------------+----------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------+ +; Minimum Output Disable Times ; ++--------------+------------+-----------+-----------+------------+----------------------------------------------------------+ +; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ; ++--------------+------------+-----------+-----------+------------+----------------------------------------------------------+ +; DRAM_DQ[*] ; CLOCK_50 ; 2.372 ; 2.451 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 2.482 ; 2.555 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 2.482 ; 2.555 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 2.373 ; 2.452 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 2.404 ; 2.468 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 2.494 ; 2.567 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 2.496 ; 2.569 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 2.496 ; 2.569 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 2.373 ; 2.452 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 2.375 ; 2.454 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 2.375 ; 2.454 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 2.376 ; 2.455 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 2.376 ; 2.455 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 2.372 ; 2.451 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 2.376 ; 2.455 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 2.376 ; 2.455 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[15] ; CLOCK_50 ; 2.494 ; 2.567 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ++--------------+------------+-----------+-----------+------------+----------------------------------------------------------+ + + +---------------- +; MTBF Summary ; +---------------- +Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. + +Number of Synchronizer Chains Found: 5 +Shortest Synchronizer Chain: 2 Registers +Fraction of Chains for which MTBFs Could Not be Calculated: 0.400 +Worst Case Available Settling Time: 16.908 ns + +Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. + - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8 + + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Synchronizer Summary ; ++------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+-------------------------+ +; Source Node ; Synchronization Node ; Typical MTBF (Years) ; Included in Design MTBF ; ++------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+-------------------------+ +; GPIO_0[1] ; system:inst_cpu|system_uart_0:uart_0|system_uart_0_rx:the_system_uart_0_rx|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 ; Greater than 1 Billion ; Yes ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer2|din_s1 ; Greater than 1 Billion ; Yes ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3|din_s1 ; Greater than 1 Billion ; Yes ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_debug:the_system_cpu_nios2_oci_debug|monitor_ready ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|din_s1 ; n/a ; Yes ; +; system:inst_cpu|system_cpu:cpu|hbreak_enabled ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 ; n/a ; Yes ; ++------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+-------------------------+ + + +Synchronizer Chain #1: Typical MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; GPIO_0[1] ; +; Synchronization Node ; system:inst_cpu|system_uart_0:uart_0|system_uart_0_rx:the_system_uart_0_rx|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------+ + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++-----------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++-----------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 16.908 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 12.5 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; 10.000 ; 100.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; GPIO_0[1] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; system:inst_cpu|system_uart_0:uart_0|system_uart_0_rx:the_system_uart_0_rx|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 ; ; ; ; 9.229 ; +; system:inst_cpu|system_uart_0:uart_0|system_uart_0_rx:the_system_uart_0_rx|altera_std_synchronizer:the_altera_std_synchronizer|dreg[0] ; ; ; ; 7.679 ; ++-----------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #2: Typical MTBF is Greater than 1 Billion Years +=============================================================================== ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; +; Synchronization Node ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer2|din_s1 ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 18.448 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 1.25 ; ; ; ; +; Source Clock ; ; ; ; ; +; altera_reserved_tck ; ; 100.000 ; 10.0 MHz ; ; +; Synchronization Clock ; ; ; ; ; +; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; 10.000 ; 100.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; ; ; ; ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; ; ; ; ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer2|din_s1 ; ; ; ; 9.230 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer2|dreg[0] ; ; ; ; 9.218 ; ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #3: Typical MTBF is Greater than 1 Billion Years +=============================================================================== ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; +; Synchronization Node ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3|din_s1 ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 18.451 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 1.25 ; ; ; ; +; Source Clock ; ; ; ; ; +; altera_reserved_tck ; ; 100.000 ; 10.0 MHz ; ; +; Synchronization Clock ; ; ; ; ; +; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; 10.000 ; 100.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; ; ; ; ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; ; ; ; ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3|din_s1 ; ; ; ; 9.231 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3|dreg[0] ; ; ; ; 9.220 ; ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #4: Typical MTBF is n/a Years +=============================================================================== ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_debug:the_system_cpu_nios2_oci_debug|monitor_ready ; +; Synchronization Node ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|din_s1 ; +; Typical MTBF (years) ; n/a ; +; Included in Design MTBF ; Yes ; ++-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Typical MTBF (years) ; n/a ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; n/a ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 12.5 ; ; ; ; +; Source Clock ; ; ; ; ; +; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; 10.000 ; 100.0 MHz ; ; +; Synchronization Clock ; ; ; ; ; +; altera_reserved_tck ; ; 100.000 ; 10.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_debug:the_system_cpu_nios2_oci_debug|monitor_ready ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|din_s1 ; ; ; ; n/a ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|dreg[0] ; ; ; ; n/a ; ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #5: Typical MTBF is n/a Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; system:inst_cpu|system_cpu:cpu|hbreak_enabled ; +; Synchronization Node ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 ; +; Typical MTBF (years) ; n/a ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Typical MTBF (years) ; n/a ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; n/a ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 12.5 ; ; ; ; +; Source Clock ; ; ; ; ; +; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; 10.000 ; 100.0 MHz ; ; +; Synchronization Clock ; ; ; ; ; +; altera_reserved_tck ; ; 100.000 ; 10.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; system:inst_cpu|system_cpu:cpu|hbreak_enabled ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 ; ; ; ; n/a ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer|dreg[0] ; ; ; ; n/a ; ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+ + + + ++------------------------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Fmax Summary ; ++------------+-----------------+----------------------------------------------------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++------------+-----------------+----------------------------------------------------------+------+ +; 143.88 MHz ; 143.88 MHz ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; +; 436.11 MHz ; 436.11 MHz ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; ; ++------------+-----------------+----------------------------------------------------------+------+ +This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. + + ++-----------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Setup Summary ; ++----------------------------------------------------------+--------+---------------+ +; Clock ; Slack ; End Point TNS ; ++----------------------------------------------------------+--------+---------------+ +; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 2.319 ; 0.000 ; +; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 97.707 ; 0.000 ; ++----------------------------------------------------------+--------+---------------+ + + ++----------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Hold Summary ; ++----------------------------------------------------------+-------+---------------+ +; Clock ; Slack ; End Point TNS ; ++----------------------------------------------------------+-------+---------------+ +; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.224 ; 0.000 ; +; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.320 ; 0.000 ; ++----------------------------------------------------------+-------+---------------+ + + ++----------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Recovery Summary ; ++----------------------------------------------------------+-------+---------------+ +; Clock ; Slack ; End Point TNS ; ++----------------------------------------------------------+-------+---------------+ +; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 2.259 ; 0.000 ; ++----------------------------------------------------------+-------+---------------+ + + ++----------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Removal Summary ; ++----------------------------------------------------------+-------+---------------+ +; Clock ; Slack ; End Point TNS ; ++----------------------------------------------------------+-------+---------------+ +; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 1.967 ; 0.000 ; ++----------------------------------------------------------+-------+---------------+ + + ++-----------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Minimum Pulse Width Summary ; ++----------------------------------------------------------+--------+---------------+ +; Clock ; Slack ; End Point TNS ; ++----------------------------------------------------------+--------+---------------+ +; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 4.718 ; 0.000 ; +; CLOCK_50 ; 9.818 ; 0.000 ; +; altera_reserved_tck ; 49.601 ; 0.000 ; +; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 49.744 ; 0.000 ; ++----------------------------------------------------------+--------+---------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Setup: 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[0]' ; ++-------+-------------------------------------------------------+-------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+-------------------------------------------------------+-------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ +; 2.319 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[29] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.094 ; 2.582 ; +; 2.490 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[18] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.072 ; 2.433 ; +; 2.593 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[27] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.096 ; 2.306 ; +; 2.619 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[14] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.072 ; 2.304 ; +; 2.627 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[26] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.072 ; 2.296 ; +; 2.640 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[27] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.096 ; 2.259 ; +; 2.645 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[25] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.094 ; 2.256 ; +; 2.649 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[24] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.082 ; 2.264 ; +; 2.661 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.072 ; 2.262 ; +; 2.664 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[22] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.072 ; 2.259 ; +; 2.667 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.081 ; 2.247 ; +; 2.671 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[29] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.094 ; 2.230 ; +; 2.676 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[28] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.082 ; 2.237 ; +; 2.676 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[26] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.087 ; 2.232 ; +; 2.684 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[27] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.081 ; 2.230 ; +; 2.686 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.082 ; 2.227 ; +; 2.687 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.082 ; 2.226 ; +; 2.690 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.081 ; 2.224 ; +; 2.690 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[23] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.081 ; 2.224 ; +; 2.694 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.081 ; 2.220 ; +; 2.697 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[3] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[24] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.082 ; 2.216 ; +; 2.697 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[3] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.082 ; 2.216 ; +; 2.697 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[3] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.082 ; 2.216 ; +; 2.697 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[3] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[20] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.082 ; 2.216 ; +; 2.697 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[3] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.082 ; 2.216 ; +; 2.697 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[3] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[16] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.082 ; 2.216 ; +; 2.697 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[3] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[28] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.082 ; 2.216 ; +; 2.697 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[3] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.082 ; 2.216 ; +; 2.697 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[31] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.081 ; 2.217 ; +; 2.752 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[21] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[29] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.079 ; 2.164 ; +; 2.761 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[28] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.097 ; 2.137 ; +; 2.783 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[30] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.072 ; 2.140 ; +; 2.794 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[15] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[23] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.081 ; 2.120 ; +; 2.801 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[21] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.079 ; 2.115 ; +; 2.803 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[15] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[27] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.081 ; 2.111 ; +; 2.811 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.082 ; 2.102 ; +; 2.811 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[25] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.094 ; 2.090 ; +; 2.821 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.082 ; 2.092 ; +; 2.824 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[26] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[6] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.087 ; 2.084 ; +; 2.842 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[24] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.097 ; 2.056 ; +; 2.846 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[30] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.087 ; 2.062 ; +; 2.846 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[29] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.094 ; 2.055 ; +; 2.860 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.079 ; 2.056 ; +; 2.863 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.079 ; 2.053 ; +; 2.865 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[17] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.079 ; 2.051 ; +; 2.885 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[8] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[16] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.078 ; 2.032 ; +; 2.891 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[17] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[25] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.079 ; 2.025 ; +; 2.897 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[16] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.082 ; 2.016 ; +; 2.907 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[30] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[6] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.087 ; 2.001 ; +; 2.908 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[3] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.077 ; 2.010 ; +; 2.909 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[4] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[16] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.078 ; 2.008 ; +; 2.912 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[14] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[26] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.072 ; 2.011 ; +; 2.916 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.072 ; 2.007 ; +; 2.919 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[5] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[17] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.075 ; 2.001 ; +; 2.926 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[11] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.081 ; 1.988 ; +; 2.927 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[11] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[23] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.081 ; 1.987 ; +; 2.932 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[20] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.082 ; 1.981 ; +; 2.936 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[5] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.075 ; 1.984 ; +; 2.941 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.081 ; 1.973 ; +; 2.942 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[17] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[29] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.079 ; 1.974 ; +; 2.944 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[13] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[25] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.079 ; 1.972 ; +; 2.963 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[10] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[18] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.072 ; 1.960 ; +; 2.970 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[24] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.097 ; 1.928 ; +; 2.971 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[7] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.077 ; 1.947 ; +; 2.972 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[14] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[22] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.072 ; 1.951 ; +; 2.976 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[8] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[20] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.078 ; 1.941 ; +; 3.000 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[13] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.079 ; 1.916 ; +; 3.027 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[4] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.078 ; 1.890 ; +; 3.028 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[9] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.079 ; 1.888 ; +; 3.033 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[28] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.097 ; 1.865 ; +; 3.039 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[7] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.077 ; 1.879 ; +; 3.050 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[4] ; system:inst_cpu|system_cpu:cpu|A_mem_stall ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.056 ; 6.889 ; +; 3.052 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[6] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.072 ; 1.871 ; +; 3.057 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[3] ; system:inst_cpu|system_cpu:cpu|A_mem_stall ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.056 ; 6.882 ; +; 3.057 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[3] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.077 ; 1.861 ; +; 3.071 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.081 ; 1.843 ; +; 3.087 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[29] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[29] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.094 ; 1.814 ; +; 3.091 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[3] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.081 ; 1.823 ; +; 3.091 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[3] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[27] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.081 ; 1.823 ; +; 3.091 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[3] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[23] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.081 ; 1.823 ; +; 3.091 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[3] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.081 ; 1.823 ; +; 3.091 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[3] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.081 ; 1.823 ; +; 3.091 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[3] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.081 ; 1.823 ; +; 3.091 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[3] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.081 ; 1.823 ; +; 3.091 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[3] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[31] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.081 ; 1.823 ; +; 3.103 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[6] ; system:inst_cpu|system_cpu:cpu|A_mem_stall ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.053 ; 6.839 ; +; 3.103 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[12] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[24] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.082 ; 1.810 ; +; 3.104 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.079 ; 1.812 ; +; 3.105 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[8] ; system:inst_cpu|system_cpu:cpu|A_mem_stall ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.053 ; 6.837 ; +; 3.113 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[18] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[26] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.072 ; 1.810 ; +; 3.113 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[25] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.079 ; 1.803 ; +; 3.115 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[29] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.079 ; 1.801 ; +; 3.122 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[19] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[31] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.081 ; 1.792 ; +; 3.124 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[3] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[14] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.072 ; 1.799 ; +; 3.124 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[3] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[6] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.072 ; 1.799 ; +; 3.124 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[3] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[22] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.072 ; 1.799 ; +; 3.124 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[3] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[26] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.072 ; 1.799 ; +; 3.124 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[3] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.072 ; 1.799 ; +; 3.124 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[3] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[18] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.072 ; 1.799 ; +; 3.124 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[3] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.072 ; 1.799 ; ++-------+-------------------------------------------------------+-------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Setup: 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[2]' ; ++--------+-------------------------------------------+-------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++--------+-------------------------------------------+-------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ +; 97.707 ; heartbeat:inst_heartbeat|counter_data[2] ; heartbeat:inst_heartbeat|counter_data[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.058 ; 2.230 ; +; 97.772 ; heartbeat:inst_heartbeat|counter_data[1] ; heartbeat:inst_heartbeat|counter_data[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.058 ; 2.165 ; +; 97.777 ; heartbeat:inst_heartbeat|counter_data[0] ; heartbeat:inst_heartbeat|counter_data[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.058 ; 2.160 ; +; 97.806 ; heartbeat:inst_heartbeat|counter_data[4] ; heartbeat:inst_heartbeat|counter_data[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.058 ; 2.131 ; +; 97.807 ; heartbeat:inst_heartbeat|counter_data[2] ; heartbeat:inst_heartbeat|counter_data[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.058 ; 2.130 ; +; 97.807 ; heartbeat:inst_heartbeat|counter_data[0] ; heartbeat:inst_heartbeat|counter_data[20] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.058 ; 2.130 ; +; 97.811 ; heartbeat:inst_heartbeat|counter_data[1] ; heartbeat:inst_heartbeat|counter_data[20] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.058 ; 2.126 ; +; 97.825 ; heartbeat:inst_heartbeat|counter_data[2] ; heartbeat:inst_heartbeat|counter_data[20] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.058 ; 2.112 ; +; 97.872 ; heartbeat:inst_heartbeat|counter_data[1] ; heartbeat:inst_heartbeat|counter_data[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.058 ; 2.065 ; +; 97.876 ; heartbeat:inst_heartbeat|counter_data[3] ; heartbeat:inst_heartbeat|counter_data[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.058 ; 2.061 ; +; 97.877 ; heartbeat:inst_heartbeat|counter_data[0] ; heartbeat:inst_heartbeat|counter_data[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.058 ; 2.060 ; +; 97.906 ; heartbeat:inst_heartbeat|counter_data[4] ; heartbeat:inst_heartbeat|counter_data[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.058 ; 2.031 ; +; 97.906 ; heartbeat:inst_heartbeat|counter_data[3] ; heartbeat:inst_heartbeat|counter_data[20] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.058 ; 2.031 ; +; 97.907 ; heartbeat:inst_heartbeat|counter_data[2] ; heartbeat:inst_heartbeat|counter_data[17] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.058 ; 2.030 ; +; 97.907 ; heartbeat:inst_heartbeat|counter_data[0] ; heartbeat:inst_heartbeat|counter_data[18] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.058 ; 2.030 ; +; 97.911 ; heartbeat:inst_heartbeat|counter_data[1] ; heartbeat:inst_heartbeat|counter_data[18] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.058 ; 2.026 ; +; 97.912 ; heartbeat:inst_heartbeat|counter_data[6] ; heartbeat:inst_heartbeat|counter_data[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.058 ; 2.025 ; +; 97.924 ; heartbeat:inst_heartbeat|counter_data[4] ; heartbeat:inst_heartbeat|counter_data[20] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.058 ; 2.013 ; +; 97.925 ; heartbeat:inst_heartbeat|counter_data[2] ; heartbeat:inst_heartbeat|counter_data[18] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.058 ; 2.012 ; +; 97.972 ; heartbeat:inst_heartbeat|counter_data[1] ; heartbeat:inst_heartbeat|counter_data[17] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.058 ; 1.965 ; +; 97.976 ; heartbeat:inst_heartbeat|counter_data[5] ; heartbeat:inst_heartbeat|counter_data[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.058 ; 1.961 ; +; 97.976 ; heartbeat:inst_heartbeat|counter_data[3] ; heartbeat:inst_heartbeat|counter_data[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.058 ; 1.961 ; +; 97.977 ; heartbeat:inst_heartbeat|counter_data[0] ; heartbeat:inst_heartbeat|counter_data[17] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.058 ; 1.960 ; +; 98.006 ; heartbeat:inst_heartbeat|counter_data[4] ; heartbeat:inst_heartbeat|counter_data[17] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.058 ; 1.931 ; +; 98.006 ; heartbeat:inst_heartbeat|counter_data[3] ; heartbeat:inst_heartbeat|counter_data[18] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.058 ; 1.931 ; +; 98.007 ; heartbeat:inst_heartbeat|counter_data[2] ; heartbeat:inst_heartbeat|counter_data[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.058 ; 1.930 ; +; 98.007 ; heartbeat:inst_heartbeat|counter_data[0] ; heartbeat:inst_heartbeat|counter_data[16] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.058 ; 1.930 ; +; 98.007 ; heartbeat:inst_heartbeat|counter_data[5] ; heartbeat:inst_heartbeat|counter_data[20] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.058 ; 1.930 ; +; 98.011 ; heartbeat:inst_heartbeat|counter_data[1] ; heartbeat:inst_heartbeat|counter_data[16] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.058 ; 1.926 ; +; 98.012 ; heartbeat:inst_heartbeat|counter_data[8] ; heartbeat:inst_heartbeat|counter_data[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.058 ; 1.925 ; +; 98.012 ; heartbeat:inst_heartbeat|counter_data[6] ; heartbeat:inst_heartbeat|counter_data[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.058 ; 1.925 ; +; 98.024 ; heartbeat:inst_heartbeat|counter_data[4] ; heartbeat:inst_heartbeat|counter_data[18] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.058 ; 1.913 ; +; 98.025 ; heartbeat:inst_heartbeat|counter_data[2] ; heartbeat:inst_heartbeat|counter_data[16] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.058 ; 1.912 ; +; 98.030 ; heartbeat:inst_heartbeat|counter_data[6] ; heartbeat:inst_heartbeat|counter_data[20] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.058 ; 1.907 ; +; 98.072 ; heartbeat:inst_heartbeat|counter_data[1] ; heartbeat:inst_heartbeat|counter_data[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.058 ; 1.865 ; +; 98.076 ; heartbeat:inst_heartbeat|counter_data[5] ; heartbeat:inst_heartbeat|counter_data[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.058 ; 1.861 ; +; 98.076 ; heartbeat:inst_heartbeat|counter_data[3] ; heartbeat:inst_heartbeat|counter_data[17] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.058 ; 1.861 ; +; 98.077 ; heartbeat:inst_heartbeat|counter_data[0] ; heartbeat:inst_heartbeat|counter_data[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.058 ; 1.860 ; +; 98.078 ; heartbeat:inst_heartbeat|counter_data[7] ; heartbeat:inst_heartbeat|counter_data[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.058 ; 1.859 ; +; 98.106 ; heartbeat:inst_heartbeat|counter_data[4] ; heartbeat:inst_heartbeat|counter_data[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.058 ; 1.831 ; +; 98.106 ; heartbeat:inst_heartbeat|counter_data[3] ; heartbeat:inst_heartbeat|counter_data[16] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.058 ; 1.831 ; +; 98.107 ; heartbeat:inst_heartbeat|counter_data[2] ; heartbeat:inst_heartbeat|counter_data[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.058 ; 1.830 ; +; 98.107 ; heartbeat:inst_heartbeat|counter_data[0] ; heartbeat:inst_heartbeat|counter_data[14] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.058 ; 1.830 ; +; 98.107 ; heartbeat:inst_heartbeat|counter_data[7] ; heartbeat:inst_heartbeat|counter_data[20] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.058 ; 1.830 ; +; 98.107 ; heartbeat:inst_heartbeat|counter_data[5] ; heartbeat:inst_heartbeat|counter_data[18] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.058 ; 1.830 ; +; 98.111 ; heartbeat:inst_heartbeat|counter_data[1] ; heartbeat:inst_heartbeat|counter_data[14] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.058 ; 1.826 ; +; 98.112 ; heartbeat:inst_heartbeat|counter_data[10] ; heartbeat:inst_heartbeat|counter_data[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.058 ; 1.825 ; +; 98.112 ; heartbeat:inst_heartbeat|counter_data[8] ; heartbeat:inst_heartbeat|counter_data[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.058 ; 1.825 ; +; 98.112 ; heartbeat:inst_heartbeat|counter_data[6] ; heartbeat:inst_heartbeat|counter_data[17] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.058 ; 1.825 ; +; 98.124 ; heartbeat:inst_heartbeat|counter_data[4] ; heartbeat:inst_heartbeat|counter_data[16] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.058 ; 1.813 ; +; 98.125 ; heartbeat:inst_heartbeat|counter_data[2] ; heartbeat:inst_heartbeat|counter_data[14] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.058 ; 1.812 ; +; 98.130 ; heartbeat:inst_heartbeat|counter_data[8] ; heartbeat:inst_heartbeat|counter_data[20] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.058 ; 1.807 ; +; 98.130 ; heartbeat:inst_heartbeat|counter_data[6] ; heartbeat:inst_heartbeat|counter_data[18] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.058 ; 1.807 ; +; 98.172 ; heartbeat:inst_heartbeat|counter_data[1] ; heartbeat:inst_heartbeat|counter_data[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.058 ; 1.765 ; +; 98.176 ; heartbeat:inst_heartbeat|counter_data[5] ; heartbeat:inst_heartbeat|counter_data[17] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.058 ; 1.761 ; +; 98.176 ; heartbeat:inst_heartbeat|counter_data[3] ; heartbeat:inst_heartbeat|counter_data[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.058 ; 1.761 ; +; 98.177 ; heartbeat:inst_heartbeat|counter_data[0] ; heartbeat:inst_heartbeat|counter_data[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.058 ; 1.760 ; +; 98.178 ; heartbeat:inst_heartbeat|counter_data[7] ; heartbeat:inst_heartbeat|counter_data[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.058 ; 1.759 ; +; 98.179 ; heartbeat:inst_heartbeat|counter_data[9] ; heartbeat:inst_heartbeat|counter_data[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.058 ; 1.758 ; +; 98.206 ; heartbeat:inst_heartbeat|counter_data[4] ; heartbeat:inst_heartbeat|counter_data[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.058 ; 1.731 ; +; 98.206 ; heartbeat:inst_heartbeat|counter_data[3] ; heartbeat:inst_heartbeat|counter_data[14] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.058 ; 1.731 ; +; 98.207 ; heartbeat:inst_heartbeat|counter_data[2] ; heartbeat:inst_heartbeat|counter_data[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.058 ; 1.730 ; +; 98.207 ; heartbeat:inst_heartbeat|counter_data[0] ; heartbeat:inst_heartbeat|counter_data[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.058 ; 1.730 ; +; 98.207 ; heartbeat:inst_heartbeat|counter_data[7] ; heartbeat:inst_heartbeat|counter_data[18] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.058 ; 1.730 ; +; 98.207 ; heartbeat:inst_heartbeat|counter_data[5] ; heartbeat:inst_heartbeat|counter_data[16] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.058 ; 1.730 ; +; 98.208 ; heartbeat:inst_heartbeat|counter_data[9] ; heartbeat:inst_heartbeat|counter_data[20] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.058 ; 1.729 ; +; 98.211 ; heartbeat:inst_heartbeat|counter_data[1] ; heartbeat:inst_heartbeat|counter_data[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.058 ; 1.726 ; +; 98.212 ; heartbeat:inst_heartbeat|counter_data[12] ; heartbeat:inst_heartbeat|counter_data[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.055 ; 1.728 ; +; 98.212 ; heartbeat:inst_heartbeat|counter_data[10] ; heartbeat:inst_heartbeat|counter_data[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.058 ; 1.725 ; +; 98.212 ; heartbeat:inst_heartbeat|counter_data[8] ; heartbeat:inst_heartbeat|counter_data[17] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.058 ; 1.725 ; +; 98.212 ; heartbeat:inst_heartbeat|counter_data[6] ; heartbeat:inst_heartbeat|counter_data[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.058 ; 1.725 ; +; 98.224 ; heartbeat:inst_heartbeat|counter_data[4] ; heartbeat:inst_heartbeat|counter_data[14] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.058 ; 1.713 ; +; 98.225 ; heartbeat:inst_heartbeat|counter_data[2] ; heartbeat:inst_heartbeat|counter_data[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.058 ; 1.712 ; +; 98.230 ; heartbeat:inst_heartbeat|counter_data[10] ; heartbeat:inst_heartbeat|counter_data[20] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.058 ; 1.707 ; +; 98.230 ; heartbeat:inst_heartbeat|counter_data[8] ; heartbeat:inst_heartbeat|counter_data[18] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.058 ; 1.707 ; +; 98.230 ; heartbeat:inst_heartbeat|counter_data[6] ; heartbeat:inst_heartbeat|counter_data[16] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.058 ; 1.707 ; +; 98.272 ; heartbeat:inst_heartbeat|counter_data[1] ; heartbeat:inst_heartbeat|counter_data[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.058 ; 1.665 ; +; 98.276 ; heartbeat:inst_heartbeat|counter_data[5] ; heartbeat:inst_heartbeat|counter_data[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.058 ; 1.661 ; +; 98.276 ; heartbeat:inst_heartbeat|counter_data[3] ; heartbeat:inst_heartbeat|counter_data[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.058 ; 1.661 ; +; 98.277 ; heartbeat:inst_heartbeat|counter_data[0] ; heartbeat:inst_heartbeat|counter_data[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.058 ; 1.660 ; +; 98.278 ; heartbeat:inst_heartbeat|counter_data[7] ; heartbeat:inst_heartbeat|counter_data[17] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.058 ; 1.659 ; +; 98.279 ; heartbeat:inst_heartbeat|counter_data[9] ; heartbeat:inst_heartbeat|counter_data[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.058 ; 1.658 ; +; 98.282 ; heartbeat:inst_heartbeat|counter_data[11] ; heartbeat:inst_heartbeat|counter_data[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.055 ; 1.658 ; +; 98.306 ; heartbeat:inst_heartbeat|counter_data[4] ; heartbeat:inst_heartbeat|counter_data[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.058 ; 1.631 ; +; 98.306 ; heartbeat:inst_heartbeat|counter_data[3] ; heartbeat:inst_heartbeat|counter_data[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.058 ; 1.631 ; +; 98.307 ; heartbeat:inst_heartbeat|counter_data[7] ; heartbeat:inst_heartbeat|counter_data[16] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.058 ; 1.630 ; +; 98.307 ; heartbeat:inst_heartbeat|counter_data[5] ; heartbeat:inst_heartbeat|counter_data[14] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.058 ; 1.630 ; +; 98.308 ; heartbeat:inst_heartbeat|counter_data[9] ; heartbeat:inst_heartbeat|counter_data[18] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.058 ; 1.629 ; +; 98.310 ; heartbeat:inst_heartbeat|counter_data[2] ; heartbeat:inst_heartbeat|counter_data[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.055 ; 1.630 ; +; 98.310 ; heartbeat:inst_heartbeat|counter_data[0] ; heartbeat:inst_heartbeat|counter_data[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.055 ; 1.630 ; +; 98.312 ; heartbeat:inst_heartbeat|counter_data[12] ; heartbeat:inst_heartbeat|counter_data[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.055 ; 1.628 ; +; 98.312 ; heartbeat:inst_heartbeat|counter_data[11] ; heartbeat:inst_heartbeat|counter_data[20] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.055 ; 1.628 ; +; 98.312 ; heartbeat:inst_heartbeat|counter_data[10] ; heartbeat:inst_heartbeat|counter_data[17] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.058 ; 1.625 ; +; 98.312 ; heartbeat:inst_heartbeat|counter_data[8] ; heartbeat:inst_heartbeat|counter_data[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.058 ; 1.625 ; +; 98.312 ; heartbeat:inst_heartbeat|counter_data[6] ; heartbeat:inst_heartbeat|counter_data[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.058 ; 1.625 ; +; 98.314 ; heartbeat:inst_heartbeat|counter_data[14] ; heartbeat:inst_heartbeat|counter_data[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.055 ; 1.626 ; +; 98.314 ; heartbeat:inst_heartbeat|counter_data[1] ; heartbeat:inst_heartbeat|counter_data[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.055 ; 1.626 ; +; 98.324 ; heartbeat:inst_heartbeat|counter_data[4] ; heartbeat:inst_heartbeat|counter_data[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.058 ; 1.613 ; +; 98.328 ; heartbeat:inst_heartbeat|counter_data[2] ; heartbeat:inst_heartbeat|counter_data[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.055 ; 1.612 ; +; 98.330 ; heartbeat:inst_heartbeat|counter_data[12] ; heartbeat:inst_heartbeat|counter_data[20] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.055 ; 1.610 ; ++--------+-------------------------------------------+-------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Hold: 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[0]' ; ++-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ +; 0.224 ; system:inst_cpu|system_cpu:cpu|i_readdata_d1[11] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a11~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.347 ; 0.740 ; +; 0.227 ; system:inst_cpu|system_cpu:cpu|ic_fill_valid_bits[6] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.341 ; 0.737 ; +; 0.229 ; system:inst_cpu|system_cpu:cpu|ic_fill_valid_bits[0] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.341 ; 0.739 ; +; 0.285 ; system:inst_cpu|system_cpu:cpu|ic_tag_wraddress[3] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.337 ; 0.791 ; +; 0.286 ; system:inst_cpu|system_cpu:cpu|M_bht_ptr_unfiltered[2] ; system:inst_cpu|system_cpu:cpu|system_cpu_bht_module:system_cpu_bht|altsyncram:the_altsyncram|altsyncram_fhg1:auto_generated|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.338 ; 0.793 ; +; 0.289 ; system:inst_cpu|system_cpu:cpu|i_readdata_d1[15] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a11~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.345 ; 0.803 ; +; 0.292 ; system:inst_cpu|system_cpu:cpu|ic_tag_wraddress[7] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.337 ; 0.798 ; +; 0.293 ; system:inst_cpu|system_cpu:cpu|ic_fill_valid_bits[4] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.341 ; 0.803 ; +; 0.294 ; system:inst_cpu|system_cpu:cpu|i_readdata_d1[14] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a11~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.345 ; 0.808 ; +; 0.295 ; system:inst_cpu|system_cpu:cpu|i_readdata_d1[0] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.341 ; 0.805 ; +; 0.295 ; system:inst_cpu|system_cpu:cpu|ic_tag_wraddress[1] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.337 ; 0.801 ; +; 0.295 ; system:inst_cpu|system_cpu:cpu|ic_tag_wraddress[2] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.337 ; 0.801 ; +; 0.297 ; system:inst_cpu|system_cpu:cpu|ic_tag_wraddress[5] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.337 ; 0.803 ; +; 0.299 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[28] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.345 ; 0.813 ; +; 0.299 ; system:inst_cpu|system_cpu:cpu|ic_fill_valid_bits[7] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.341 ; 0.809 ; +; 0.300 ; system:inst_cpu|system_cpu:cpu|ic_fill_valid_bits[2] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.341 ; 0.810 ; +; 0.301 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[30] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.345 ; 0.815 ; +; 0.302 ; system:inst_cpu|system_cpu:cpu|ic_tag_wraddress[4] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.337 ; 0.808 ; +; 0.303 ; system:inst_cpu|system_cpu:cpu|i_readdata_d1[3] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.341 ; 0.813 ; +; 0.306 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[27] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.345 ; 0.820 ; +; 0.310 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[25] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.345 ; 0.824 ; +; 0.311 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[13] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.345 ; 0.825 ; +; 0.311 ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[6] ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.337 ; 0.817 ; +; 0.311 ; system:inst_cpu|system_rs232_motor:rs232_motor|data_to_uart[7] ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.341 ; 0.821 ; +; 0.311 ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[8] ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.511 ; +; 0.311 ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[4] ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.511 ; +; 0.311 ; system:inst_cpu|system_sdram:sdram|m_state.000100000 ; system:inst_cpu|system_sdram:sdram|m_state.000100000 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.511 ; +; 0.311 ; system:inst_cpu|system_sdram:sdram|m_state.000000100 ; system:inst_cpu|system_sdram:sdram|m_state.000000100 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.511 ; +; 0.311 ; system:inst_cpu|system_sdram:sdram|m_next.000000001 ; system:inst_cpu|system_sdram:sdram|m_next.000000001 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.511 ; +; 0.311 ; system:inst_cpu|system_sdram:sdram|m_state.000000001 ; system:inst_cpu|system_sdram:sdram|m_state.000000001 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.511 ; +; 0.311 ; system:inst_cpu|system_sdram:sdram|ack_refresh_request ; system:inst_cpu|system_sdram:sdram|ack_refresh_request ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.511 ; +; 0.311 ; system:inst_cpu|system_sdram:sdram|refresh_request ; system:inst_cpu|system_sdram:sdram|refresh_request ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.511 ; +; 0.311 ; system:inst_cpu|system_cpu:cpu|A_mul_cnt[1] ; system:inst_cpu|system_cpu:cpu|A_mul_cnt[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.511 ; +; 0.311 ; system:inst_cpu|system_cpu:cpu|A_mul_cnt[2] ; system:inst_cpu|system_cpu:cpu|A_mul_cnt[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.511 ; +; 0.311 ; system:inst_cpu|system_cpu:cpu|A_dc_xfer_rd_addr_has_started ; system:inst_cpu|system_cpu:cpu|A_dc_xfer_rd_addr_has_started ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.511 ; +; 0.311 ; system:inst_cpu|system_cpu:cpu|latched_oci_tb_hbreak_req ; system:inst_cpu|system_cpu:cpu|latched_oci_tb_hbreak_req ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.511 ; +; 0.311 ; system:inst_cpu|system_cpu:cpu|A_dc_fill_active ; system:inst_cpu|system_cpu:cpu|A_dc_fill_active ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.511 ; +; 0.311 ; system:inst_cpu|system_cpu:cpu|hbreak_enabled ; system:inst_cpu|system_cpu:cpu|hbreak_enabled ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.511 ; +; 0.311 ; system:inst_cpu|system_cpu:cpu|A_st_bypass_delayed_started ; system:inst_cpu|system_cpu:cpu|A_st_bypass_delayed_started ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.511 ; +; 0.311 ; system:inst_cpu|system_cpu:cpu|A_shift_rot_stall ; system:inst_cpu|system_cpu:cpu|A_shift_rot_stall ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.511 ; +; 0.312 ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|full_dff ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|full_dff ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|receiving_data ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|receiving_data ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_rs232_counters:RS232_In_Counters|bit_counter[0] ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_rs232_counters:RS232_In_Counters|bit_counter[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_rs232_counters:RS232_In_Counters|bit_counter[1] ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_rs232_counters:RS232_In_Counters|bit_counter[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_rs232_counters:RS232_In_Counters|bit_counter[2] ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_rs232_counters:RS232_In_Counters|bit_counter[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_rs232_counters:RS232_In_Counters|bit_counter[3] ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_rs232_counters:RS232_In_Counters|bit_counter[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|usedw_is_2_dff ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|usedw_is_2_dff ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|usedw_is_0_dff ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|usedw_is_0_dff ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|full_dff ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|full_dff ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|low_addressa[6] ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|low_addressa[6] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|low_addressa[5] ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|low_addressa[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|low_addressa[4] ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|low_addressa[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|low_addressa[3] ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|low_addressa[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|low_addressa[2] ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|low_addressa[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|low_addressa[1] ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|low_addressa[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|low_addressa[0] ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|low_addressa[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|b_full ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|b_full ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|rvalid ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|rvalid ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|pause_irq ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|pause_irq ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_debug:the_system_cpu_nios2_oci_debug|resetlatch ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_debug:the_system_cpu_nios2_oci_debug|resetlatch ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_rs232_counters:RS232_Out_Counters|bit_counter[0] ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_rs232_counters:RS232_Out_Counters|bit_counter[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_rs232_counters:RS232_Out_Counters|bit_counter[1] ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_rs232_counters:RS232_Out_Counters|bit_counter[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_rs232_counters:RS232_Out_Counters|bit_counter[2] ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_rs232_counters:RS232_Out_Counters|bit_counter[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_rs232_counters:RS232_Out_Counters|bit_counter[3] ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_rs232_counters:RS232_Out_Counters|bit_counter[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|transmitting_data ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|transmitting_data ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|low_addressa[6] ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|low_addressa[6] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|low_addressa[5] ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|low_addressa[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|low_addressa[4] ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|low_addressa[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|low_addressa[3] ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|low_addressa[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|low_addressa[2] ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|low_addressa[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|low_addressa[1] ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|low_addressa[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|low_addressa[0] ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|low_addressa[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|data_out_shift_reg[8] ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|data_out_shift_reg[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|data_out_shift_reg[0] ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|data_out_shift_reg[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|wr_address ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|wr_address ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; system:inst_cpu|altera_merlin_slave_translator:cpu_jtag_debug_module_translator|end_begintransfer ; system:inst_cpu|altera_merlin_slave_translator:cpu_jtag_debug_module_translator|end_begintransfer ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonRd ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonRd ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; system:inst_cpu|system_cpu:cpu|A_dc_fill_has_started ; system:inst_cpu|system_cpu:cpu|A_dc_fill_has_started ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; system:inst_cpu|system_cpu:cpu|A_dc_fill_dp_offset[1] ; system:inst_cpu|system_cpu:cpu|A_dc_fill_dp_offset[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; system:inst_cpu|system_cpu:cpu|A_dc_fill_dp_offset[2] ; system:inst_cpu|system_cpu:cpu|A_dc_fill_dp_offset[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; system:inst_cpu|altera_avalon_sc_fifo:rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0] ; system:inst_cpu|altera_avalon_sc_fifo:rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; system:inst_cpu|altera_avalon_sc_fifo:rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; system:inst_cpu|altera_avalon_sc_fifo:rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][84] ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][84] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[7] ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; system:inst_cpu|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0] ; system:inst_cpu|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; system:inst_cpu|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; system:inst_cpu|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; system:inst_cpu|altera_merlin_slave_translator:sys_clk_timer_s1_translator|wait_latency_counter[1] ; system:inst_cpu|altera_merlin_slave_translator:sys_clk_timer_s1_translator|wait_latency_counter[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; system:inst_cpu|altera_avalon_sc_fifo:sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0] ; system:inst_cpu|altera_avalon_sc_fifo:sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; system:inst_cpu|altera_avalon_sc_fifo:sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; system:inst_cpu|altera_avalon_sc_fifo:sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; system:inst_cpu|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; system:inst_cpu|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[9] ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; system:inst_cpu|altera_avalon_sc_fifo:uart_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0] ; system:inst_cpu|altera_avalon_sc_fifo:uart_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; system:inst_cpu|altera_avalon_sc_fifo:uart_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; system:inst_cpu|altera_avalon_sc_fifo:uart_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; system:inst_cpu|altera_merlin_slave_translator:uart_0_s1_translator|wait_latency_counter[1] ; system:inst_cpu|altera_merlin_slave_translator:uart_0_s1_translator|wait_latency_counter[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[12] ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; system:inst_cpu|system_cpu:cpu|ic_fill_ap_offset[1] ; system:inst_cpu|system_cpu:cpu|ic_fill_ap_offset[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|woverflow ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|woverflow ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[14] ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[14] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[13] ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; ++-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Hold: 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[2]' ; ++-------+-------------------------------------------+-------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+-------------------------------------------+-------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ +; 0.320 ; heartbeat:inst_heartbeat|counter_data[0] ; heartbeat:inst_heartbeat|counter_data[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.055 ; 0.519 ; +; 0.348 ; heartbeat:inst_heartbeat|counter_data[21] ; heartbeat:inst_heartbeat|counter_data[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.055 ; 0.547 ; +; 0.492 ; heartbeat:inst_heartbeat|counter_data[8] ; heartbeat:inst_heartbeat|counter_data[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.055 ; 0.691 ; +; 0.492 ; heartbeat:inst_heartbeat|counter_data[10] ; heartbeat:inst_heartbeat|counter_data[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.055 ; 0.691 ; +; 0.493 ; heartbeat:inst_heartbeat|counter_data[14] ; heartbeat:inst_heartbeat|counter_data[14] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.055 ; 0.692 ; +; 0.494 ; heartbeat:inst_heartbeat|counter_data[6] ; heartbeat:inst_heartbeat|counter_data[6] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.055 ; 0.693 ; +; 0.495 ; heartbeat:inst_heartbeat|counter_data[12] ; heartbeat:inst_heartbeat|counter_data[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.055 ; 0.694 ; +; 0.495 ; heartbeat:inst_heartbeat|counter_data[16] ; heartbeat:inst_heartbeat|counter_data[16] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.055 ; 0.694 ; +; 0.496 ; heartbeat:inst_heartbeat|counter_data[4] ; heartbeat:inst_heartbeat|counter_data[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.055 ; 0.695 ; +; 0.496 ; heartbeat:inst_heartbeat|counter_data[11] ; heartbeat:inst_heartbeat|counter_data[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.055 ; 0.695 ; +; 0.496 ; heartbeat:inst_heartbeat|counter_data[17] ; heartbeat:inst_heartbeat|counter_data[17] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.055 ; 0.695 ; +; 0.497 ; heartbeat:inst_heartbeat|counter_data[2] ; heartbeat:inst_heartbeat|counter_data[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.055 ; 0.696 ; +; 0.497 ; heartbeat:inst_heartbeat|counter_data[9] ; heartbeat:inst_heartbeat|counter_data[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.055 ; 0.696 ; +; 0.498 ; heartbeat:inst_heartbeat|counter_data[7] ; heartbeat:inst_heartbeat|counter_data[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.055 ; 0.697 ; +; 0.498 ; heartbeat:inst_heartbeat|counter_data[13] ; heartbeat:inst_heartbeat|counter_data[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.055 ; 0.697 ; +; 0.498 ; heartbeat:inst_heartbeat|counter_data[18] ; heartbeat:inst_heartbeat|counter_data[18] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.055 ; 0.697 ; +; 0.498 ; heartbeat:inst_heartbeat|counter_data[20] ; heartbeat:inst_heartbeat|counter_data[20] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.055 ; 0.697 ; +; 0.499 ; heartbeat:inst_heartbeat|counter_data[3] ; heartbeat:inst_heartbeat|counter_data[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.055 ; 0.698 ; +; 0.499 ; heartbeat:inst_heartbeat|counter_data[5] ; heartbeat:inst_heartbeat|counter_data[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.055 ; 0.698 ; +; 0.499 ; heartbeat:inst_heartbeat|counter_data[15] ; heartbeat:inst_heartbeat|counter_data[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.055 ; 0.698 ; +; 0.500 ; heartbeat:inst_heartbeat|counter_data[19] ; heartbeat:inst_heartbeat|counter_data[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.055 ; 0.699 ; +; 0.508 ; heartbeat:inst_heartbeat|counter_data[0] ; heartbeat:inst_heartbeat|counter_data[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.055 ; 0.707 ; +; 0.509 ; heartbeat:inst_heartbeat|counter_data[1] ; heartbeat:inst_heartbeat|counter_data[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.055 ; 0.708 ; +; 0.736 ; heartbeat:inst_heartbeat|counter_data[8] ; heartbeat:inst_heartbeat|counter_data[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.055 ; 0.935 ; +; 0.737 ; heartbeat:inst_heartbeat|counter_data[14] ; heartbeat:inst_heartbeat|counter_data[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.055 ; 0.936 ; +; 0.738 ; heartbeat:inst_heartbeat|counter_data[6] ; heartbeat:inst_heartbeat|counter_data[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.055 ; 0.937 ; +; 0.739 ; heartbeat:inst_heartbeat|counter_data[10] ; heartbeat:inst_heartbeat|counter_data[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.052 ; 0.935 ; +; 0.739 ; heartbeat:inst_heartbeat|counter_data[16] ; heartbeat:inst_heartbeat|counter_data[17] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.055 ; 0.938 ; +; 0.740 ; heartbeat:inst_heartbeat|counter_data[12] ; heartbeat:inst_heartbeat|counter_data[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.055 ; 0.939 ; +; 0.741 ; heartbeat:inst_heartbeat|counter_data[4] ; heartbeat:inst_heartbeat|counter_data[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.055 ; 0.940 ; +; 0.742 ; heartbeat:inst_heartbeat|counter_data[2] ; heartbeat:inst_heartbeat|counter_data[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.055 ; 0.941 ; +; 0.743 ; heartbeat:inst_heartbeat|counter_data[20] ; heartbeat:inst_heartbeat|counter_data[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.055 ; 0.942 ; +; 0.743 ; heartbeat:inst_heartbeat|counter_data[18] ; heartbeat:inst_heartbeat|counter_data[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.055 ; 0.942 ; +; 0.744 ; heartbeat:inst_heartbeat|counter_data[1] ; heartbeat:inst_heartbeat|counter_data[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.055 ; 0.943 ; +; 0.745 ; heartbeat:inst_heartbeat|counter_data[11] ; heartbeat:inst_heartbeat|counter_data[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.055 ; 0.944 ; +; 0.745 ; heartbeat:inst_heartbeat|counter_data[17] ; heartbeat:inst_heartbeat|counter_data[18] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.055 ; 0.944 ; +; 0.746 ; heartbeat:inst_heartbeat|counter_data[9] ; heartbeat:inst_heartbeat|counter_data[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.055 ; 0.945 ; +; 0.747 ; heartbeat:inst_heartbeat|counter_data[7] ; heartbeat:inst_heartbeat|counter_data[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.055 ; 0.946 ; +; 0.747 ; heartbeat:inst_heartbeat|counter_data[13] ; heartbeat:inst_heartbeat|counter_data[14] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.055 ; 0.946 ; +; 0.747 ; heartbeat:inst_heartbeat|counter_data[0] ; heartbeat:inst_heartbeat|counter_data[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.055 ; 0.946 ; +; 0.748 ; heartbeat:inst_heartbeat|counter_data[5] ; heartbeat:inst_heartbeat|counter_data[6] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.055 ; 0.947 ; +; 0.748 ; heartbeat:inst_heartbeat|counter_data[15] ; heartbeat:inst_heartbeat|counter_data[16] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.055 ; 0.947 ; +; 0.748 ; heartbeat:inst_heartbeat|counter_data[3] ; heartbeat:inst_heartbeat|counter_data[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.055 ; 0.947 ; +; 0.749 ; heartbeat:inst_heartbeat|counter_data[19] ; heartbeat:inst_heartbeat|counter_data[20] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.055 ; 0.948 ; +; 0.751 ; heartbeat:inst_heartbeat|counter_data[1] ; heartbeat:inst_heartbeat|counter_data[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.055 ; 0.950 ; +; 0.752 ; heartbeat:inst_heartbeat|counter_data[11] ; heartbeat:inst_heartbeat|counter_data[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.055 ; 0.951 ; +; 0.752 ; heartbeat:inst_heartbeat|counter_data[17] ; heartbeat:inst_heartbeat|counter_data[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.055 ; 0.951 ; +; 0.754 ; heartbeat:inst_heartbeat|counter_data[7] ; heartbeat:inst_heartbeat|counter_data[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.055 ; 0.953 ; +; 0.754 ; heartbeat:inst_heartbeat|counter_data[13] ; heartbeat:inst_heartbeat|counter_data[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.055 ; 0.953 ; +; 0.754 ; heartbeat:inst_heartbeat|counter_data[0] ; heartbeat:inst_heartbeat|counter_data[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.055 ; 0.953 ; +; 0.755 ; heartbeat:inst_heartbeat|counter_data[5] ; heartbeat:inst_heartbeat|counter_data[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.055 ; 0.954 ; +; 0.755 ; heartbeat:inst_heartbeat|counter_data[15] ; heartbeat:inst_heartbeat|counter_data[17] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.055 ; 0.954 ; +; 0.755 ; heartbeat:inst_heartbeat|counter_data[3] ; heartbeat:inst_heartbeat|counter_data[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.055 ; 0.954 ; +; 0.756 ; heartbeat:inst_heartbeat|counter_data[9] ; heartbeat:inst_heartbeat|counter_data[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.052 ; 0.952 ; +; 0.756 ; heartbeat:inst_heartbeat|counter_data[19] ; heartbeat:inst_heartbeat|counter_data[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.055 ; 0.955 ; +; 0.825 ; heartbeat:inst_heartbeat|counter_data[8] ; heartbeat:inst_heartbeat|counter_data[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.055 ; 1.024 ; +; 0.826 ; heartbeat:inst_heartbeat|counter_data[14] ; heartbeat:inst_heartbeat|counter_data[16] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.055 ; 1.025 ; +; 0.827 ; heartbeat:inst_heartbeat|counter_data[6] ; heartbeat:inst_heartbeat|counter_data[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.055 ; 1.026 ; +; 0.828 ; heartbeat:inst_heartbeat|counter_data[10] ; heartbeat:inst_heartbeat|counter_data[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.052 ; 1.024 ; +; 0.828 ; heartbeat:inst_heartbeat|counter_data[16] ; heartbeat:inst_heartbeat|counter_data[18] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.055 ; 1.027 ; +; 0.829 ; heartbeat:inst_heartbeat|counter_data[12] ; heartbeat:inst_heartbeat|counter_data[14] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.055 ; 1.028 ; +; 0.830 ; heartbeat:inst_heartbeat|counter_data[4] ; heartbeat:inst_heartbeat|counter_data[6] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.055 ; 1.029 ; +; 0.831 ; heartbeat:inst_heartbeat|counter_data[2] ; heartbeat:inst_heartbeat|counter_data[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.055 ; 1.030 ; +; 0.832 ; heartbeat:inst_heartbeat|counter_data[18] ; heartbeat:inst_heartbeat|counter_data[20] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.055 ; 1.031 ; +; 0.833 ; heartbeat:inst_heartbeat|counter_data[14] ; heartbeat:inst_heartbeat|counter_data[17] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.055 ; 1.032 ; +; 0.834 ; heartbeat:inst_heartbeat|counter_data[6] ; heartbeat:inst_heartbeat|counter_data[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.055 ; 1.033 ; +; 0.835 ; heartbeat:inst_heartbeat|counter_data[10] ; heartbeat:inst_heartbeat|counter_data[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.052 ; 1.031 ; +; 0.835 ; heartbeat:inst_heartbeat|counter_data[16] ; heartbeat:inst_heartbeat|counter_data[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.055 ; 1.034 ; +; 0.835 ; heartbeat:inst_heartbeat|counter_data[8] ; heartbeat:inst_heartbeat|counter_data[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.052 ; 1.031 ; +; 0.836 ; heartbeat:inst_heartbeat|counter_data[12] ; heartbeat:inst_heartbeat|counter_data[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.055 ; 1.035 ; +; 0.837 ; heartbeat:inst_heartbeat|counter_data[4] ; heartbeat:inst_heartbeat|counter_data[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.055 ; 1.036 ; +; 0.838 ; heartbeat:inst_heartbeat|counter_data[2] ; heartbeat:inst_heartbeat|counter_data[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.055 ; 1.037 ; +; 0.839 ; heartbeat:inst_heartbeat|counter_data[18] ; heartbeat:inst_heartbeat|counter_data[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.055 ; 1.038 ; +; 0.840 ; heartbeat:inst_heartbeat|counter_data[1] ; heartbeat:inst_heartbeat|counter_data[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.055 ; 1.039 ; +; 0.841 ; heartbeat:inst_heartbeat|counter_data[11] ; heartbeat:inst_heartbeat|counter_data[14] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.055 ; 1.040 ; +; 0.841 ; heartbeat:inst_heartbeat|counter_data[17] ; heartbeat:inst_heartbeat|counter_data[20] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.055 ; 1.040 ; +; 0.843 ; heartbeat:inst_heartbeat|counter_data[7] ; heartbeat:inst_heartbeat|counter_data[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.055 ; 1.042 ; +; 0.843 ; heartbeat:inst_heartbeat|counter_data[13] ; heartbeat:inst_heartbeat|counter_data[16] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.055 ; 1.042 ; +; 0.843 ; heartbeat:inst_heartbeat|counter_data[0] ; heartbeat:inst_heartbeat|counter_data[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.055 ; 1.042 ; +; 0.844 ; heartbeat:inst_heartbeat|counter_data[5] ; heartbeat:inst_heartbeat|counter_data[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.055 ; 1.043 ; +; 0.844 ; heartbeat:inst_heartbeat|counter_data[15] ; heartbeat:inst_heartbeat|counter_data[18] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.055 ; 1.043 ; +; 0.844 ; heartbeat:inst_heartbeat|counter_data[3] ; heartbeat:inst_heartbeat|counter_data[6] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.055 ; 1.043 ; +; 0.845 ; heartbeat:inst_heartbeat|counter_data[9] ; heartbeat:inst_heartbeat|counter_data[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.052 ; 1.041 ; +; 0.847 ; heartbeat:inst_heartbeat|counter_data[1] ; heartbeat:inst_heartbeat|counter_data[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.055 ; 1.046 ; +; 0.848 ; heartbeat:inst_heartbeat|counter_data[11] ; heartbeat:inst_heartbeat|counter_data[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.055 ; 1.047 ; +; 0.848 ; heartbeat:inst_heartbeat|counter_data[17] ; heartbeat:inst_heartbeat|counter_data[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.055 ; 1.047 ; +; 0.850 ; heartbeat:inst_heartbeat|counter_data[13] ; heartbeat:inst_heartbeat|counter_data[17] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.055 ; 1.049 ; +; 0.850 ; heartbeat:inst_heartbeat|counter_data[0] ; heartbeat:inst_heartbeat|counter_data[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.055 ; 1.049 ; +; 0.851 ; heartbeat:inst_heartbeat|counter_data[5] ; heartbeat:inst_heartbeat|counter_data[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.055 ; 1.050 ; +; 0.851 ; heartbeat:inst_heartbeat|counter_data[15] ; heartbeat:inst_heartbeat|counter_data[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.055 ; 1.050 ; +; 0.851 ; heartbeat:inst_heartbeat|counter_data[3] ; heartbeat:inst_heartbeat|counter_data[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.055 ; 1.050 ; +; 0.852 ; heartbeat:inst_heartbeat|counter_data[9] ; heartbeat:inst_heartbeat|counter_data[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.052 ; 1.048 ; +; 0.853 ; heartbeat:inst_heartbeat|counter_data[7] ; heartbeat:inst_heartbeat|counter_data[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.052 ; 1.049 ; +; 0.922 ; heartbeat:inst_heartbeat|counter_data[14] ; heartbeat:inst_heartbeat|counter_data[18] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.055 ; 1.121 ; +; 0.923 ; heartbeat:inst_heartbeat|counter_data[6] ; heartbeat:inst_heartbeat|counter_data[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.055 ; 1.122 ; +; 0.924 ; heartbeat:inst_heartbeat|counter_data[10] ; heartbeat:inst_heartbeat|counter_data[14] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.052 ; 1.120 ; +; 0.924 ; heartbeat:inst_heartbeat|counter_data[16] ; heartbeat:inst_heartbeat|counter_data[20] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.055 ; 1.123 ; +; 0.924 ; heartbeat:inst_heartbeat|counter_data[8] ; heartbeat:inst_heartbeat|counter_data[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.052 ; 1.120 ; +; 0.925 ; heartbeat:inst_heartbeat|counter_data[12] ; heartbeat:inst_heartbeat|counter_data[16] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.055 ; 1.124 ; +; 0.926 ; heartbeat:inst_heartbeat|counter_data[4] ; heartbeat:inst_heartbeat|counter_data[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.055 ; 1.125 ; ++-------+-------------------------------------------+-------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Recovery: 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[0]' ; ++-------+-------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+-------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ +; 2.259 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[17] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.096 ; 2.640 ; +; 2.259 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[24] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.099 ; 2.637 ; +; 2.259 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.099 ; 2.637 ; +; 2.259 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.096 ; 2.640 ; +; 2.259 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.096 ; 2.640 ; +; 2.259 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.099 ; 2.637 ; +; 2.259 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[20] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.099 ; 2.637 ; +; 2.259 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.096 ; 2.640 ; +; 2.259 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.099 ; 2.637 ; +; 2.259 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[16] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.099 ; 2.637 ; +; 2.259 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.096 ; 2.640 ; +; 2.259 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[29] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.096 ; 2.640 ; +; 2.259 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[28] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.099 ; 2.637 ; +; 2.259 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.099 ; 2.637 ; +; 2.259 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[25] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.096 ; 2.640 ; +; 2.259 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.096 ; 2.640 ; +; 2.260 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[14] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.089 ; 2.646 ; +; 2.260 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[6] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.089 ; 2.646 ; +; 2.260 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[22] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.089 ; 2.646 ; +; 2.260 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.098 ; 2.637 ; +; 2.260 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[27] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.098 ; 2.637 ; +; 2.260 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[26] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.089 ; 2.646 ; +; 2.260 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.089 ; 2.646 ; +; 2.260 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[18] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.089 ; 2.646 ; +; 2.260 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.089 ; 2.646 ; +; 2.260 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[30] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.089 ; 2.646 ; +; 2.260 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[23] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.098 ; 2.637 ; +; 2.260 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.098 ; 2.637 ; +; 2.260 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.098 ; 2.637 ; +; 2.260 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.098 ; 2.637 ; +; 2.260 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.098 ; 2.637 ; +; 2.260 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[31] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.098 ; 2.637 ; +; 6.822 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.164 ; 2.911 ; +; 6.824 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.161 ; 2.912 ; +; 6.824 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.161 ; 2.912 ; +; 6.824 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.161 ; 2.912 ; +; 6.824 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[14] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.161 ; 2.912 ; +; 6.824 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.161 ; 2.912 ; +; 6.825 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.161 ; 2.911 ; +; 6.825 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.164 ; 2.908 ; +; 6.825 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.163 ; 2.909 ; +; 6.885 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.189 ; 2.823 ; +; 6.892 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.183 ; 2.822 ; +; 6.892 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.183 ; 2.822 ; +; 6.893 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.180 ; 2.824 ; +; 6.893 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[6] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.180 ; 2.824 ; +; 6.898 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.089 ; 2.916 ; +; 6.900 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.085 ; 2.918 ; +; 6.900 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.086 ; 2.917 ; +; 6.900 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.086 ; 2.917 ; +; 6.900 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.086 ; 2.917 ; +; 6.900 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.086 ; 2.917 ; +; 6.900 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[14] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.086 ; 2.917 ; +; 6.900 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_bank[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.088 ; 2.915 ; +; 6.900 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_bank[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.087 ; 2.916 ; +; 6.901 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.086 ; 2.916 ; +; 6.901 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.086 ; 2.916 ; +; 6.901 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.087 ; 2.915 ; +; 6.901 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.088 ; 2.914 ; +; 6.901 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[6] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.087 ; 2.915 ; +; 6.901 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.089 ; 2.913 ; +; 6.901 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.088 ; 2.914 ; +; 6.901 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.096 ; 2.908 ; +; 6.901 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.086 ; 2.916 ; +; 6.901 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.089 ; 2.913 ; +; 6.901 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_dqm[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.089 ; 2.913 ; +; 6.901 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_dqm[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.089 ; 2.913 ; +; 6.901 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.096 ; 2.908 ; +; 6.904 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.108 ; 2.893 ; +; 6.905 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.098 ; 2.902 ; +; 6.905 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.100 ; 2.900 ; +; 6.905 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.098 ; 2.902 ; +; 6.908 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.090 ; 2.907 ; +; 6.908 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.090 ; 2.907 ; +; 6.909 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.087 ; 2.909 ; +; 6.909 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[6] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.087 ; 2.909 ; +; 6.915 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.182 ; 2.800 ; +; 6.915 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.182 ; 2.800 ; +; 6.918 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.102 ; 2.885 ; +; 6.931 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.089 ; 2.885 ; +; 6.931 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.089 ; 2.885 ; +; 7.027 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_7 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.085 ; 2.770 ; +; 7.029 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_10 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.082 ; 2.771 ; +; 7.029 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_11 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.082 ; 2.771 ; +; 7.029 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_13 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.082 ; 2.771 ; +; 7.029 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_14 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.082 ; 2.771 ; +; 7.030 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_2 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.084 ; 2.768 ; +; 7.030 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_8 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.082 ; 2.770 ; +; 7.030 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_9 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.082 ; 2.770 ; +; 7.030 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_12 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.085 ; 2.767 ; +; 7.062 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_cmd[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.088 ; 2.753 ; +; 7.069 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_3 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.108 ; 2.704 ; +; 7.076 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_15 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.102 ; 2.703 ; +; 7.076 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_4 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.102 ; 2.703 ; +; 7.079 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_5 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.099 ; 2.703 ; +; 7.079 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_6 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.099 ; 2.703 ; +; 7.097 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.101 ; 2.683 ; +; 7.097 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_1 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.101 ; 2.683 ; +; 7.112 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_cmd[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.090 ; 2.703 ; +; 7.112 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_cmd[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.090 ; 2.703 ; ++-------+-------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Removal: 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[0]' ; ++-------+-------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+-------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ +; 1.967 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_uart_0:uart_0|system_uart_0_rx:the_system_uart_0_rx|altera_std_synchronizer:the_altera_std_synchronizer|dreg[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.381 ; 2.492 ; +; 1.967 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_uart_0:uart_0|system_uart_0_rx:the_system_uart_0_rx|delayed_unxsync_rxdxx1 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.381 ; 2.492 ; +; 1.967 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_uart_0:uart_0|system_uart_0_rx:the_system_uart_0_rx|do_start_rx ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.381 ; 2.492 ; +; 1.967 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_uart_0:uart_0|system_uart_0_rx:the_system_uart_0_rx|baud_rate_counter[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.381 ; 2.492 ; +; 1.967 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_uart_0:uart_0|system_uart_0_rx:the_system_uart_0_rx|baud_clk_en ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.381 ; 2.492 ; +; 2.262 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_traffic_limiter:limiter|last_dest_id[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.058 ; 2.464 ; +; 2.262 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|i_read ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.058 ; 2.464 ; +; 2.262 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_slave_translator:cpu_jtag_debug_module_translator|read_latency_shift_reg[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 2.461 ; +; 2.262 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 2.461 ; +; 2.262 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][83] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 2.461 ; +; 2.262 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][83] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 2.461 ; +; 2.262 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][102] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 2.461 ; +; 2.262 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][102] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 2.461 ; +; 2.262 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_traffic_limiter:limiter|pending_response_count[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.058 ; 2.464 ; +; 2.262 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_traffic_limiter:limiter|has_pending_responses ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.058 ; 2.464 ; +; 2.262 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 2.461 ; +; 2.263 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entries[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.052 ; 2.459 ; +; 2.263 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|wr_address ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.053 ; 2.460 ; +; 2.263 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][65] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.052 ; 2.459 ; +; 2.263 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|d_byteenable[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.053 ; 2.460 ; +; 2.263 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|d_byteenable[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.053 ; 2.460 ; +; 2.263 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|byteen_reg[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.052 ; 2.459 ; +; 2.263 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|byteen_reg[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.052 ; 2.459 ; +; 2.263 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|use_reg ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.052 ; 2.459 ; +; 2.263 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|count[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.052 ; 2.459 ; +; 2.263 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|endofpacket_reg ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.052 ; 2.459 ; +; 2.263 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.057 ; 2.464 ; +; 2.263 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|ic_fill_ap_offset[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.058 ; 2.465 ; +; 2.263 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|ic_fill_ap_offset[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.058 ; 2.465 ; +; 2.263 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|ic_fill_ap_offset[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.058 ; 2.465 ; +; 2.263 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.057 ; 2.464 ; +; 2.263 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.057 ; 2.464 ; +; 2.263 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|ic_fill_line[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.057 ; 2.464 ; +; 2.263 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|ic_fill_line[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.057 ; 2.464 ; +; 2.263 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|ic_fill_ap_cnt[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.058 ; 2.465 ; +; 2.263 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|ic_fill_ap_cnt[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.058 ; 2.465 ; +; 2.263 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|ic_fill_ap_cnt[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.058 ; 2.465 ; +; 2.263 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|ic_fill_ap_cnt[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.058 ; 2.465 ; +; 2.263 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entries[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.052 ; 2.459 ; +; 2.263 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|address_reg[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.057 ; 2.464 ; +; 2.263 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|address_reg[16] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.057 ; 2.464 ; +; 2.263 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|address_reg[22] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.052 ; 2.459 ; +; 2.263 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|address_reg[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.057 ; 2.464 ; +; 2.263 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|address_reg[23] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.057 ; 2.464 ; +; 2.263 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|address_reg[14] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.057 ; 2.464 ; +; 2.263 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|address_reg[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.057 ; 2.464 ; +; 2.263 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|address_reg[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.057 ; 2.464 ; +; 2.263 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|address_reg[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.057 ; 2.464 ; +; 2.263 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|address_reg[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.057 ; 2.464 ; +; 2.263 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_traffic_limiter:limiter|pending_response_count[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.057 ; 2.464 ; +; 2.263 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_traffic_limiter:limiter|pending_response_count[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.057 ; 2.464 ; +; 2.263 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_traffic_limiter:limiter|pending_response_count[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.057 ; 2.464 ; +; 2.263 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux_001|packet_in_progress ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.053 ; 2.460 ; +; 2.263 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux_001|saved_grant[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.053 ; 2.460 ; +; 2.263 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|address_reg[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.052 ; 2.459 ; +; 2.263 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.052 ; 2.459 ; +; 2.263 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][54] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.052 ; 2.459 ; +; 2.263 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|address_reg[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.052 ; 2.459 ; +; 2.263 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|address_reg[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.057 ; 2.464 ; +; 2.263 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|address_reg[6] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.057 ; 2.464 ; +; 2.263 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|address_reg[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.057 ; 2.464 ; +; 2.263 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|address_reg[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.057 ; 2.464 ; +; 2.263 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|data_reg[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.052 ; 2.459 ; +; 2.263 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|data_reg[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.052 ; 2.459 ; +; 2.263 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|data_reg[14] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.052 ; 2.459 ; +; 2.263 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|data_reg[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.052 ; 2.459 ; +; 2.270 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|E_pc[6] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.054 ; 2.468 ; +; 2.270 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|D_pc[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.054 ; 2.468 ; +; 2.270 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|E_pc[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.051 ; 2.465 ; +; 2.270 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|M_pipe_flush_waddr[6] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.054 ; 2.468 ; +; 2.270 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|ic_fill_initial_offset[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.058 ; 2.472 ; +; 2.270 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|ic_fill_initial_offset[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.058 ; 2.472 ; +; 2.270 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|ic_fill_dp_offset[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.058 ; 2.472 ; +; 2.270 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|ic_fill_dp_offset[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.058 ; 2.472 ; +; 2.270 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|ic_fill_dp_offset[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.058 ; 2.472 ; +; 2.270 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|ic_fill_initial_offset[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.058 ; 2.472 ; +; 2.270 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|E_pc[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.054 ; 2.468 ; +; 2.270 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|M_pipe_flush_waddr[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.054 ; 2.468 ; +; 2.270 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sys_clk_timer:sys_clk_timer|period_l_register[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.070 ; 2.484 ; +; 2.270 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sys_clk_timer:sys_clk_timer|period_l_register[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.070 ; 2.484 ; +; 2.270 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sys_clk_timer:sys_clk_timer|period_l_register[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.070 ; 2.484 ; +; 2.270 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sys_clk_timer:sys_clk_timer|period_l_register[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.070 ; 2.484 ; +; 2.270 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sys_clk_timer:sys_clk_timer|period_l_register[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.070 ; 2.484 ; +; 2.270 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sys_clk_timer:sys_clk_timer|period_h_register[6] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.070 ; 2.484 ; +; 2.270 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sys_clk_timer:sys_clk_timer|period_h_register[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.070 ; 2.484 ; +; 2.270 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sys_clk_timer:sys_clk_timer|period_l_register[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.070 ; 2.484 ; +; 2.270 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sys_clk_timer:sys_clk_timer|period_h_register[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.070 ; 2.484 ; +; 2.270 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sys_clk_timer:sys_clk_timer|period_l_register[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.070 ; 2.484 ; +; 2.270 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sys_clk_timer:sys_clk_timer|period_h_register[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.070 ; 2.484 ; +; 2.270 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sys_clk_timer:sys_clk_timer|period_h_register[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.070 ; 2.484 ; +; 2.270 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sys_clk_timer:sys_clk_timer|period_h_register[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.070 ; 2.484 ; +; 2.270 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sys_clk_timer:sys_clk_timer|period_h_register[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.070 ; 2.484 ; +; 2.270 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sys_clk_timer:sys_clk_timer|period_h_register[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.070 ; 2.484 ; +; 2.270 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|refresh_counter[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.076 ; 2.490 ; +; 2.270 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|refresh_counter[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.076 ; 2.490 ; +; 2.270 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|refresh_counter[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.076 ; 2.490 ; +; 2.270 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|refresh_counter[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.076 ; 2.490 ; +; 2.271 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|D_iw[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.072 ; 2.487 ; +; 2.271 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|D_iw[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.072 ; 2.487 ; +; 2.271 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|E_iw[16] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.072 ; 2.487 ; ++-------+-------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Minimum Pulse Width: 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[0]' ; ++-------+--------------+----------------+-----------------+----------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; ++-------+--------------+----------------+-----------------+----------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; 4.718 ; 4.989 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[0] ; +; 4.718 ; 4.989 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[10] ; +; 4.718 ; 4.989 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[11] ; +; 4.718 ; 4.989 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[12] ; +; 4.718 ; 4.989 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[13] ; +; 4.718 ; 4.989 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[14] ; +; 4.718 ; 4.989 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[15] ; +; 4.718 ; 4.989 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[1] ; +; 4.718 ; 4.989 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[2] ; +; 4.718 ; 4.989 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[3] ; +; 4.718 ; 4.989 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[4] ; +; 4.718 ; 4.989 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[5] ; +; 4.718 ; 4.989 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[6] ; +; 4.718 ; 4.989 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[7] ; +; 4.718 ; 4.989 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[8] ; +; 4.718 ; 4.989 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[9] ; +; 4.718 ; 4.989 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[0] ; +; 4.718 ; 4.989 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[10] ; +; 4.718 ; 4.989 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[11] ; +; 4.718 ; 4.989 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[12] ; +; 4.718 ; 4.989 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[13] ; +; 4.718 ; 4.989 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[14] ; +; 4.718 ; 4.989 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[15] ; +; 4.718 ; 4.989 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[1] ; +; 4.718 ; 4.989 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[2] ; +; 4.718 ; 4.989 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[3] ; +; 4.718 ; 4.989 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[4] ; +; 4.718 ; 4.989 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[5] ; +; 4.718 ; 4.989 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[6] ; +; 4.718 ; 4.989 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[7] ; +; 4.718 ; 4.989 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[8] ; +; 4.718 ; 4.989 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[9] ; +; 4.718 ; 4.989 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3 ; +; 4.718 ; 4.989 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT1 ; +; 4.718 ; 4.989 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT10 ; +; 4.718 ; 4.989 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT11 ; +; 4.718 ; 4.989 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT12 ; +; 4.718 ; 4.989 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT13 ; +; 4.718 ; 4.989 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT14 ; +; 4.718 ; 4.989 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT15 ; +; 4.718 ; 4.989 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT16 ; +; 4.718 ; 4.989 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT17 ; +; 4.718 ; 4.989 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT18 ; +; 4.718 ; 4.989 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT19 ; +; 4.718 ; 4.989 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT2 ; +; 4.718 ; 4.989 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT20 ; +; 4.718 ; 4.989 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT21 ; +; 4.718 ; 4.989 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT22 ; +; 4.718 ; 4.989 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT23 ; +; 4.718 ; 4.989 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT24 ; +; 4.718 ; 4.989 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT25 ; +; 4.718 ; 4.989 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT26 ; +; 4.718 ; 4.989 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT27 ; +; 4.718 ; 4.989 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT28 ; +; 4.718 ; 4.989 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT29 ; +; 4.718 ; 4.989 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT3 ; +; 4.718 ; 4.989 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT30 ; +; 4.718 ; 4.989 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT31 ; +; 4.718 ; 4.989 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT4 ; +; 4.718 ; 4.989 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT5 ; +; 4.718 ; 4.989 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT6 ; +; 4.718 ; 4.989 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT7 ; +; 4.718 ; 4.989 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT8 ; +; 4.718 ; 4.989 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT9 ; +; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[16] ; +; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[17] ; +; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[18] ; +; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[19] ; +; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[20] ; +; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[21] ; +; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[22] ; +; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[23] ; +; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[24] ; +; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[25] ; +; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[26] ; +; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[27] ; +; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[28] ; +; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[29] ; +; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[30] ; +; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[31] ; +; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[0]~_Duplicate_1 ; +; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[10]~_Duplicate_1 ; +; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[11]~_Duplicate_1 ; +; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[12]~_Duplicate_1 ; +; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[13]~_Duplicate_1 ; +; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[14]~_Duplicate_1 ; +; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[15]~_Duplicate_1 ; +; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[1]~_Duplicate_1 ; +; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[2]~_Duplicate_1 ; +; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[3]~_Duplicate_1 ; +; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[4]~_Duplicate_1 ; +; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[5]~_Duplicate_1 ; +; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[6]~_Duplicate_1 ; +; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[7]~_Duplicate_1 ; +; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[8]~_Duplicate_1 ; +; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[9]~_Duplicate_1 ; +; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3 ; +; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT1 ; +; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT10 ; +; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT11 ; ++-------+--------------+----------------+-----------------+----------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50' ; ++--------+--------------+----------------+------------------+----------+------------+--------------------------------------------------------------------+ +; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; ++--------+--------------+----------------+------------------+----------+------------+--------------------------------------------------------------------+ +; 9.818 ; 9.818 ; 0.000 ; Low Pulse Width ; CLOCK_50 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; 9.818 ; 9.818 ; 0.000 ; Low Pulse Width ; CLOCK_50 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[1] ; +; 9.818 ; 9.818 ; 0.000 ; Low Pulse Width ; CLOCK_50 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; +; 9.818 ; 9.818 ; 0.000 ; Low Pulse Width ; CLOCK_50 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|observablevcoout ; +; 9.856 ; 9.856 ; 0.000 ; Low Pulse Width ; CLOCK_50 ; Rise ; CLOCK_50~input|o ; +; 9.879 ; 9.879 ; 0.000 ; Low Pulse Width ; CLOCK_50 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|inclk[0] ; +; 10.000 ; 10.000 ; 0.000 ; High Pulse Width ; CLOCK_50 ; Rise ; CLOCK_50~input|i ; +; 10.000 ; 10.000 ; 0.000 ; Low Pulse Width ; CLOCK_50 ; Rise ; CLOCK_50~input|i ; +; 10.120 ; 10.120 ; 0.000 ; High Pulse Width ; CLOCK_50 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|inclk[0] ; +; 10.144 ; 10.144 ; 0.000 ; High Pulse Width ; CLOCK_50 ; Rise ; CLOCK_50~input|o ; +; 10.179 ; 10.179 ; 0.000 ; High Pulse Width ; CLOCK_50 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; 10.179 ; 10.179 ; 0.000 ; High Pulse Width ; CLOCK_50 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[1] ; +; 10.179 ; 10.179 ; 0.000 ; High Pulse Width ; CLOCK_50 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; +; 10.179 ; 10.179 ; 0.000 ; High Pulse Width ; CLOCK_50 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|observablevcoout ; +; 16.000 ; 20.000 ; 4.000 ; Port Rate ; CLOCK_50 ; Rise ; CLOCK_50 ; ++--------+--------------+----------------+------------------+----------+------------+--------------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Minimum Pulse Width: 'altera_reserved_tck' ; ++--------+--------------+----------------+------------------+---------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; ++--------+--------------+----------------+------------------+---------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; 49.601 ; 49.817 ; 0.216 ; High Pulse Width ; altera_reserved_tck ; Fall ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|jupdate ; +; 49.602 ; 49.818 ; 0.216 ; High Pulse Width ; altera_reserved_tck ; Fall ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; +; 49.605 ; 49.821 ; 0.216 ; High Pulse Width ; altera_reserved_tck ; Fall ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|tdo~reg0 ; +; 49.641 ; 49.825 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|DRsize.010 ; +; 49.641 ; 49.825 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|din_s1 ; +; 49.641 ; 49.825 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|dreg[0] ; +; 49.641 ; 49.825 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 ; +; 49.641 ; 49.825 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer|dreg[0] ; +; 49.641 ; 49.825 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|ir_out[1] ; +; 49.641 ; 49.825 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[24] ; +; 49.641 ; 49.825 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|wdata[1] ; +; 49.641 ; 49.825 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|wdata[2] ; +; 49.641 ; 49.825 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|wdata[3] ; +; 49.641 ; 49.825 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|wdata[4] ; +; 49.641 ; 49.825 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|wdata[5] ; +; 49.641 ; 49.825 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|wdata[6] ; +; 49.641 ; 49.825 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|wdata[7] ; +; 49.641 ; 49.825 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|write ; +; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[0] ; +; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[1] ; +; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[2] ; +; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[3] ; +; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[0] ; +; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[1] ; +; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[2] ; +; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[3] ; +; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0] ; +; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[0] ; +; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[1] ; +; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[2] ; +; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[3] ; +; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[0] ; +; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[1] ; +; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[2] ; +; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[3] ; +; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0] ; +; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1] ; +; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2] ; +; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[3] ; +; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4] ; +; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; +; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6] ; +; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[0] ; +; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[1] ; +; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[2] ; +; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[3] ; +; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[4] ; +; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[0] ; +; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[1] ; +; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[2] ; +; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[3] ; +; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[0] ; +; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[1] ; +; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[2] ; +; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[3] ; +; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[4] ; +; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; +; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[10] ; +; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[11] ; +; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[12] ; +; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[13] ; +; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[14] ; +; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[15] ; +; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[1] ; +; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[2] ; +; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; +; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[9] ; +; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo_bypass_reg ; +; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|DRsize.000 ; +; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|DRsize.100 ; +; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|ir_out[0] ; +; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[0] ; +; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[10] ; +; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[11] ; +; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[12] ; +; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[13] ; +; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[14] ; +; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[15] ; +; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[16] ; +; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[17] ; +; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[18] ; +; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[19] ; +; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[1] ; +; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[20] ; +; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[21] ; +; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[22] ; +; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[23] ; +; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[25] ; +; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[26] ; +; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[27] ; +; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[28] ; +; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[29] ; +; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[2] ; +; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[30] ; +; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[31] ; +; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[32] ; +; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[33] ; +; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[34] ; +; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[35] ; +; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[3] ; ++--------+--------------+----------------+------------------+---------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Minimum Pulse Width: 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[2]' ; ++--------+--------------+----------------+------------------+----------------------------------------------------------+------------+--------------------------------------------------------------------------------+ +; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; ++--------+--------------+----------------+------------------+----------------------------------------------------------+------------+--------------------------------------------------------------------------------+ +; 49.744 ; 49.960 ; 0.216 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[0] ; +; 49.744 ; 49.960 ; 0.216 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[10] ; +; 49.744 ; 49.960 ; 0.216 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[1] ; +; 49.744 ; 49.960 ; 0.216 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[2] ; +; 49.744 ; 49.960 ; 0.216 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[3] ; +; 49.744 ; 49.960 ; 0.216 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[4] ; +; 49.744 ; 49.960 ; 0.216 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[5] ; +; 49.744 ; 49.960 ; 0.216 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[6] ; +; 49.744 ; 49.960 ; 0.216 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[7] ; +; 49.744 ; 49.960 ; 0.216 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[8] ; +; 49.744 ; 49.960 ; 0.216 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[9] ; +; 49.745 ; 49.961 ; 0.216 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[11] ; +; 49.745 ; 49.961 ; 0.216 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[12] ; +; 49.745 ; 49.961 ; 0.216 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[13] ; +; 49.745 ; 49.961 ; 0.216 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[14] ; +; 49.745 ; 49.961 ; 0.216 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[15] ; +; 49.745 ; 49.961 ; 0.216 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[16] ; +; 49.745 ; 49.961 ; 0.216 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[17] ; +; 49.745 ; 49.961 ; 0.216 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[18] ; +; 49.745 ; 49.961 ; 0.216 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[19] ; +; 49.745 ; 49.961 ; 0.216 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[20] ; +; 49.745 ; 49.961 ; 0.216 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[21] ; +; 49.855 ; 50.039 ; 0.184 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[11] ; +; 49.855 ; 50.039 ; 0.184 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[12] ; +; 49.855 ; 50.039 ; 0.184 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[13] ; +; 49.855 ; 50.039 ; 0.184 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[14] ; +; 49.855 ; 50.039 ; 0.184 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[15] ; +; 49.855 ; 50.039 ; 0.184 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[16] ; +; 49.855 ; 50.039 ; 0.184 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[17] ; +; 49.855 ; 50.039 ; 0.184 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[18] ; +; 49.855 ; 50.039 ; 0.184 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[19] ; +; 49.855 ; 50.039 ; 0.184 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[20] ; +; 49.855 ; 50.039 ; 0.184 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[21] ; +; 49.856 ; 50.040 ; 0.184 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[0] ; +; 49.856 ; 50.040 ; 0.184 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[10] ; +; 49.856 ; 50.040 ; 0.184 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[1] ; +; 49.856 ; 50.040 ; 0.184 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[2] ; +; 49.856 ; 50.040 ; 0.184 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[3] ; +; 49.856 ; 50.040 ; 0.184 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[4] ; +; 49.856 ; 50.040 ; 0.184 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[5] ; +; 49.856 ; 50.040 ; 0.184 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[6] ; +; 49.856 ; 50.040 ; 0.184 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[7] ; +; 49.856 ; 50.040 ; 0.184 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[8] ; +; 49.856 ; 50.040 ; 0.184 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[9] ; +; 49.981 ; 49.981 ; 0.000 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_pll_sys|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl|inclk[0] ; +; 49.981 ; 49.981 ; 0.000 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_pll_sys|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl|outclk ; +; 49.984 ; 49.984 ; 0.000 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[0]|clk ; +; 49.984 ; 49.984 ; 0.000 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[10]|clk ; +; 49.984 ; 49.984 ; 0.000 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[1]|clk ; +; 49.984 ; 49.984 ; 0.000 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[2]|clk ; +; 49.984 ; 49.984 ; 0.000 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[3]|clk ; +; 49.984 ; 49.984 ; 0.000 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[4]|clk ; +; 49.984 ; 49.984 ; 0.000 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[5]|clk ; +; 49.984 ; 49.984 ; 0.000 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[6]|clk ; +; 49.984 ; 49.984 ; 0.000 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[7]|clk ; +; 49.984 ; 49.984 ; 0.000 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[8]|clk ; +; 49.984 ; 49.984 ; 0.000 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[9]|clk ; +; 49.985 ; 49.985 ; 0.000 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[11]|clk ; +; 49.985 ; 49.985 ; 0.000 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[12]|clk ; +; 49.985 ; 49.985 ; 0.000 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[13]|clk ; +; 49.985 ; 49.985 ; 0.000 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[14]|clk ; +; 49.985 ; 49.985 ; 0.000 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[15]|clk ; +; 49.985 ; 49.985 ; 0.000 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[16]|clk ; +; 49.985 ; 49.985 ; 0.000 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[17]|clk ; +; 49.985 ; 49.985 ; 0.000 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[18]|clk ; +; 49.985 ; 49.985 ; 0.000 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[19]|clk ; +; 49.985 ; 49.985 ; 0.000 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[20]|clk ; +; 49.985 ; 49.985 ; 0.000 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[21]|clk ; +; 50.015 ; 50.015 ; 0.000 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[11]|clk ; +; 50.015 ; 50.015 ; 0.000 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[12]|clk ; +; 50.015 ; 50.015 ; 0.000 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[13]|clk ; +; 50.015 ; 50.015 ; 0.000 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[14]|clk ; +; 50.015 ; 50.015 ; 0.000 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[15]|clk ; +; 50.015 ; 50.015 ; 0.000 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[16]|clk ; +; 50.015 ; 50.015 ; 0.000 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[17]|clk ; +; 50.015 ; 50.015 ; 0.000 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[18]|clk ; +; 50.015 ; 50.015 ; 0.000 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[19]|clk ; +; 50.015 ; 50.015 ; 0.000 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[20]|clk ; +; 50.015 ; 50.015 ; 0.000 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[21]|clk ; +; 50.016 ; 50.016 ; 0.000 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[0]|clk ; +; 50.016 ; 50.016 ; 0.000 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[10]|clk ; +; 50.016 ; 50.016 ; 0.000 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[1]|clk ; +; 50.016 ; 50.016 ; 0.000 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[2]|clk ; +; 50.016 ; 50.016 ; 0.000 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[3]|clk ; +; 50.016 ; 50.016 ; 0.000 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[4]|clk ; +; 50.016 ; 50.016 ; 0.000 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[5]|clk ; +; 50.016 ; 50.016 ; 0.000 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[6]|clk ; +; 50.016 ; 50.016 ; 0.000 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[7]|clk ; +; 50.016 ; 50.016 ; 0.000 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[8]|clk ; +; 50.016 ; 50.016 ; 0.000 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[9]|clk ; +; 50.018 ; 50.018 ; 0.000 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_pll_sys|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl|inclk[0] ; +; 50.018 ; 50.018 ; 0.000 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_pll_sys|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl|outclk ; +; 98.000 ; 100.000 ; 2.000 ; Min Period ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[0] ; +; 98.000 ; 100.000 ; 2.000 ; Min Period ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[10] ; +; 98.000 ; 100.000 ; 2.000 ; Min Period ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[11] ; +; 98.000 ; 100.000 ; 2.000 ; Min Period ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[12] ; +; 98.000 ; 100.000 ; 2.000 ; Min Period ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[13] ; +; 98.000 ; 100.000 ; 2.000 ; Min Period ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[14] ; +; 98.000 ; 100.000 ; 2.000 ; Min Period ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[15] ; +; 98.000 ; 100.000 ; 2.000 ; Min Period ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[16] ; ++--------+--------------+----------------+------------------+----------------------------------------------------------+------------+--------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------+ +; Setup Times ; ++---------------------+---------------------+-------+-------+------------+----------------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++---------------------+---------------------+-------+-------+------------+----------------------------------------------------------+ +; altera_reserved_tdi ; altera_reserved_tck ; 1.658 ; 1.798 ; Rise ; altera_reserved_tck ; +; altera_reserved_tms ; altera_reserved_tck ; 6.738 ; 6.930 ; Rise ; altera_reserved_tck ; +; DRAM_DQ[*] ; CLOCK_50 ; 0.889 ; 1.029 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 0.889 ; 1.029 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 0.889 ; 1.029 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 0.855 ; 0.997 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 0.882 ; 1.022 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 0.876 ; 1.016 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 0.873 ; 1.013 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 0.873 ; 1.013 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 0.856 ; 0.998 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 0.853 ; 0.995 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 0.853 ; 0.995 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 0.853 ; 0.995 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 0.853 ; 0.995 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 0.856 ; 0.998 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 0.853 ; 0.995 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 0.853 ; 0.995 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[15] ; CLOCK_50 ; 0.876 ; 1.016 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_1[*] ; CLOCK_50 ; 4.480 ; 4.843 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_1[24] ; CLOCK_50 ; 4.480 ; 4.843 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; KEY[*] ; CLOCK_50 ; 3.554 ; 3.894 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; KEY[0] ; CLOCK_50 ; 3.554 ; 3.894 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; KEY[1] ; CLOCK_50 ; 1.524 ; 1.669 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; SW[*] ; CLOCK_50 ; 1.946 ; 2.064 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; SW[0] ; CLOCK_50 ; 1.663 ; 1.830 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; SW[1] ; CLOCK_50 ; 1.946 ; 2.064 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; SW[2] ; CLOCK_50 ; 1.922 ; 2.060 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; SW[3] ; CLOCK_50 ; 1.906 ; 2.052 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ++---------------------+---------------------+-------+-------+------------+----------------------------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------+ +; Hold Times ; ++---------------------+---------------------+--------+--------+------------+----------------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++---------------------+---------------------+--------+--------+------------+----------------------------------------------------------+ +; altera_reserved_tdi ; altera_reserved_tck ; 0.768 ; 0.645 ; Rise ; altera_reserved_tck ; +; altera_reserved_tms ; altera_reserved_tck ; -1.286 ; -1.415 ; Rise ; altera_reserved_tck ; +; DRAM_DQ[*] ; CLOCK_50 ; -0.383 ; -0.525 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; -0.417 ; -0.557 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; -0.417 ; -0.557 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; -0.386 ; -0.528 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; -0.409 ; -0.549 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; -0.404 ; -0.544 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; -0.401 ; -0.541 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; -0.401 ; -0.541 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; -0.387 ; -0.529 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; -0.384 ; -0.526 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; -0.384 ; -0.526 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; -0.383 ; -0.525 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; -0.383 ; -0.525 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; -0.387 ; -0.529 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; -0.383 ; -0.525 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; -0.383 ; -0.525 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[15] ; CLOCK_50 ; -0.404 ; -0.544 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_1[*] ; CLOCK_50 ; -3.688 ; -4.066 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_1[24] ; CLOCK_50 ; -3.688 ; -4.066 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; KEY[*] ; CLOCK_50 ; -0.986 ; -1.125 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; KEY[0] ; CLOCK_50 ; -2.932 ; -3.257 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; KEY[1] ; CLOCK_50 ; -0.986 ; -1.125 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; SW[*] ; CLOCK_50 ; -1.120 ; -1.280 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; SW[0] ; CLOCK_50 ; -1.120 ; -1.280 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; SW[1] ; CLOCK_50 ; -1.391 ; -1.503 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; SW[2] ; CLOCK_50 ; -1.368 ; -1.501 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; SW[3] ; CLOCK_50 ; -1.353 ; -1.491 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ++---------------------+---------------------+--------+--------+------------+----------------------------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------+ +; Clock to Output Times ; ++---------------------+---------------------+--------+--------+------------+----------------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++---------------------+---------------------+--------+--------+------------+----------------------------------------------------------+ +; altera_reserved_tdo ; altera_reserved_tck ; 10.009 ; 10.527 ; Fall ; altera_reserved_tck ; +; DRAM_ADDR[*] ; CLOCK_50 ; 2.779 ; 2.755 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[0] ; CLOCK_50 ; 2.776 ; 2.752 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[1] ; CLOCK_50 ; 2.685 ; 2.682 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[2] ; CLOCK_50 ; 2.685 ; 2.682 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[3] ; CLOCK_50 ; 2.684 ; 2.681 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[4] ; CLOCK_50 ; 2.686 ; 2.683 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[5] ; CLOCK_50 ; 2.683 ; 2.680 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[6] ; CLOCK_50 ; 2.684 ; 2.681 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[7] ; CLOCK_50 ; 2.682 ; 2.679 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[8] ; CLOCK_50 ; 2.669 ; 2.667 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[9] ; CLOCK_50 ; 2.776 ; 2.752 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[10] ; CLOCK_50 ; 2.766 ; 2.742 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[11] ; CLOCK_50 ; 2.779 ; 2.755 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[12] ; CLOCK_50 ; 2.667 ; 2.665 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_BA[*] ; CLOCK_50 ; 2.685 ; 2.682 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_BA[0] ; CLOCK_50 ; 2.683 ; 2.680 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_BA[1] ; CLOCK_50 ; 2.685 ; 2.682 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CAS_N ; CLOCK_50 ; 2.784 ; 2.760 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CS_N ; CLOCK_50 ; 3.827 ; 3.847 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[*] ; CLOCK_50 ; 2.787 ; 2.763 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 2.771 ; 2.747 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 2.771 ; 2.747 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 2.683 ; 2.680 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 2.674 ; 2.672 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 2.784 ; 2.760 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 2.787 ; 2.763 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 2.787 ; 2.763 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 2.682 ; 2.679 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 2.685 ; 2.682 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 2.685 ; 2.682 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 2.686 ; 2.683 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 2.686 ; 2.683 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 2.682 ; 2.679 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 2.686 ; 2.683 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 2.686 ; 2.683 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[15] ; CLOCK_50 ; 2.784 ; 2.760 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQM[*] ; CLOCK_50 ; 2.682 ; 2.679 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQM[0] ; CLOCK_50 ; 2.682 ; 2.679 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQM[1] ; CLOCK_50 ; 2.682 ; 2.679 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_RAS_N ; CLOCK_50 ; 2.784 ; 2.760 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_WE_N ; CLOCK_50 ; 2.781 ; 2.757 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_0[*] ; CLOCK_50 ; 4.981 ; 4.930 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_0[0] ; CLOCK_50 ; 4.981 ; 4.930 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_1[*] ; CLOCK_50 ; 5.424 ; 5.477 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_1[12] ; CLOCK_50 ; 4.458 ; 4.508 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_1[26] ; CLOCK_50 ; 5.424 ; 5.477 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[*] ; CLOCK_50 ; 5.865 ; 5.874 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[0] ; CLOCK_50 ; 5.490 ; 5.473 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[1] ; CLOCK_50 ; 4.994 ; 5.042 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[2] ; CLOCK_50 ; 5.097 ; 5.088 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[3] ; CLOCK_50 ; 5.285 ; 5.278 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[4] ; CLOCK_50 ; 4.165 ; 4.167 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[5] ; CLOCK_50 ; 5.865 ; 5.874 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[6] ; CLOCK_50 ; 4.369 ; 4.313 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CLK ; CLOCK_50 ; 0.934 ; ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[1] ; +; DRAM_CLK ; CLOCK_50 ; ; 0.897 ; Fall ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[1] ; +; LED[*] ; CLOCK_50 ; 4.247 ; 4.292 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; +; LED[7] ; CLOCK_50 ; 4.247 ; 4.292 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; ++---------------------+---------------------+--------+--------+------------+----------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------+ +; Minimum Clock to Output Times ; ++---------------------+---------------------+-------+-------+------------+----------------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++---------------------+---------------------+-------+-------+------------+----------------------------------------------------------+ +; altera_reserved_tdo ; altera_reserved_tck ; 7.805 ; 8.325 ; Fall ; altera_reserved_tck ; +; DRAM_ADDR[*] ; CLOCK_50 ; 2.312 ; 2.310 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[0] ; CLOCK_50 ; 2.421 ; 2.397 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[1] ; CLOCK_50 ; 2.332 ; 2.328 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[2] ; CLOCK_50 ; 2.332 ; 2.328 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[3] ; CLOCK_50 ; 2.331 ; 2.327 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[4] ; CLOCK_50 ; 2.333 ; 2.329 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[5] ; CLOCK_50 ; 2.330 ; 2.326 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[6] ; CLOCK_50 ; 2.331 ; 2.327 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[7] ; CLOCK_50 ; 2.329 ; 2.325 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[8] ; CLOCK_50 ; 2.314 ; 2.312 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[9] ; CLOCK_50 ; 2.421 ; 2.397 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[10] ; CLOCK_50 ; 2.411 ; 2.387 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[11] ; CLOCK_50 ; 2.423 ; 2.399 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[12] ; CLOCK_50 ; 2.312 ; 2.310 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_BA[*] ; CLOCK_50 ; 2.330 ; 2.326 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_BA[0] ; CLOCK_50 ; 2.330 ; 2.326 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_BA[1] ; CLOCK_50 ; 2.331 ; 2.327 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CAS_N ; CLOCK_50 ; 2.429 ; 2.405 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CS_N ; CLOCK_50 ; 3.474 ; 3.493 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[*] ; CLOCK_50 ; 2.318 ; 2.316 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 2.416 ; 2.392 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 2.416 ; 2.392 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 2.330 ; 2.326 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 2.318 ; 2.316 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 2.429 ; 2.405 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 2.432 ; 2.408 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 2.432 ; 2.408 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 2.329 ; 2.325 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 2.332 ; 2.328 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 2.332 ; 2.328 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 2.332 ; 2.328 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 2.332 ; 2.328 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 2.329 ; 2.325 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 2.332 ; 2.328 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 2.332 ; 2.328 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[15] ; CLOCK_50 ; 2.429 ; 2.405 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQM[*] ; CLOCK_50 ; 2.329 ; 2.325 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQM[0] ; CLOCK_50 ; 2.329 ; 2.325 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQM[1] ; CLOCK_50 ; 2.329 ; 2.325 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_RAS_N ; CLOCK_50 ; 2.429 ; 2.405 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_WE_N ; CLOCK_50 ; 2.426 ; 2.402 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_0[*] ; CLOCK_50 ; 4.461 ; 4.412 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_0[0] ; CLOCK_50 ; 4.461 ; 4.412 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_1[*] ; CLOCK_50 ; 3.959 ; 4.007 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_1[12] ; CLOCK_50 ; 3.959 ; 4.007 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_1[26] ; CLOCK_50 ; 4.930 ; 4.983 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[*] ; CLOCK_50 ; 3.681 ; 3.682 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[0] ; CLOCK_50 ; 4.951 ; 4.934 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[1] ; CLOCK_50 ; 4.474 ; 4.520 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[2] ; CLOCK_50 ; 4.573 ; 4.564 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[3] ; CLOCK_50 ; 4.754 ; 4.746 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[4] ; CLOCK_50 ; 3.681 ; 3.682 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[5] ; CLOCK_50 ; 5.355 ; 5.363 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[6] ; CLOCK_50 ; 3.872 ; 3.818 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CLK ; CLOCK_50 ; 0.524 ; ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[1] ; +; DRAM_CLK ; CLOCK_50 ; ; 0.488 ; Fall ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[1] ; +; LED[*] ; CLOCK_50 ; 3.801 ; 3.845 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; +; LED[7] ; CLOCK_50 ; 3.801 ; 3.845 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; ++---------------------+---------------------+-------+-------+------------+----------------------------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------+ +; Output Enable Times ; ++--------------+------------+-------+-------+------------+----------------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++--------------+------------+-------+-------+------------+----------------------------------------------------------+ +; DRAM_DQ[*] ; CLOCK_50 ; 2.516 ; 2.465 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 2.614 ; 2.539 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 2.614 ; 2.539 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 2.517 ; 2.466 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 2.516 ; 2.476 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 2.627 ; 2.552 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 2.630 ; 2.555 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 2.630 ; 2.555 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 2.516 ; 2.465 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 2.519 ; 2.468 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 2.519 ; 2.468 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 2.520 ; 2.469 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 2.520 ; 2.469 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 2.516 ; 2.465 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 2.520 ; 2.469 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 2.520 ; 2.469 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[15] ; CLOCK_50 ; 2.627 ; 2.552 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ++--------------+------------+-------+-------+------------+----------------------------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------+ +; Minimum Output Enable Times ; ++--------------+------------+-------+-------+------------+----------------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++--------------+------------+-------+-------+------------+----------------------------------------------------------+ +; DRAM_DQ[*] ; CLOCK_50 ; 2.162 ; 2.114 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 2.261 ; 2.186 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 2.261 ; 2.186 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 2.166 ; 2.115 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 2.162 ; 2.122 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 2.274 ; 2.199 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 2.277 ; 2.202 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 2.277 ; 2.202 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 2.165 ; 2.114 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 2.168 ; 2.117 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 2.168 ; 2.117 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 2.168 ; 2.117 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 2.168 ; 2.117 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 2.165 ; 2.114 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 2.168 ; 2.117 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 2.168 ; 2.117 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[15] ; CLOCK_50 ; 2.274 ; 2.199 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ++--------------+------------+-------+-------+------------+----------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------+ +; Output Disable Times ; ++--------------+------------+-----------+-----------+------------+----------------------------------------------------------+ +; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ; ++--------------+------------+-----------+-----------+------------+----------------------------------------------------------+ +; DRAM_DQ[*] ; CLOCK_50 ; 2.496 ; 2.547 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 2.594 ; 2.669 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 2.594 ; 2.669 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 2.497 ; 2.548 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 2.531 ; 2.571 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 2.607 ; 2.682 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 2.610 ; 2.685 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 2.610 ; 2.685 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 2.496 ; 2.547 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 2.499 ; 2.550 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 2.499 ; 2.550 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 2.500 ; 2.551 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 2.500 ; 2.551 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 2.496 ; 2.547 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 2.500 ; 2.551 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 2.500 ; 2.551 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[15] ; CLOCK_50 ; 2.607 ; 2.682 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ++--------------+------------+-----------+-----------+------------+----------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------+ +; Minimum Output Disable Times ; ++--------------+------------+-----------+-----------+------------+----------------------------------------------------------+ +; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ; ++--------------+------------+-----------+-----------+------------+----------------------------------------------------------+ +; DRAM_DQ[*] ; CLOCK_50 ; 2.144 ; 2.195 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 2.239 ; 2.314 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 2.239 ; 2.314 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 2.145 ; 2.196 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 2.175 ; 2.215 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 2.252 ; 2.327 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 2.255 ; 2.330 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 2.255 ; 2.330 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 2.144 ; 2.195 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 2.147 ; 2.198 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 2.147 ; 2.198 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 2.147 ; 2.198 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 2.147 ; 2.198 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 2.144 ; 2.195 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 2.147 ; 2.198 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 2.147 ; 2.198 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[15] ; CLOCK_50 ; 2.252 ; 2.327 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ++--------------+------------+-----------+-----------+------------+----------------------------------------------------------+ + + +---------------- +; MTBF Summary ; +---------------- +Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. + +Number of Synchronizer Chains Found: 5 +Shortest Synchronizer Chain: 2 Registers +Fraction of Chains for which MTBFs Could Not be Calculated: 0.400 +Worst Case Available Settling Time: 17.219 ns + +Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. + - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8 + + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Synchronizer Summary ; ++------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+-------------------------+ +; Source Node ; Synchronization Node ; Typical MTBF (Years) ; Included in Design MTBF ; ++------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+-------------------------+ +; GPIO_0[1] ; system:inst_cpu|system_uart_0:uart_0|system_uart_0_rx:the_system_uart_0_rx|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 ; Greater than 1 Billion ; Yes ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer2|din_s1 ; Greater than 1 Billion ; Yes ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3|din_s1 ; Greater than 1 Billion ; Yes ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_debug:the_system_cpu_nios2_oci_debug|monitor_ready ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|din_s1 ; n/a ; Yes ; +; system:inst_cpu|system_cpu:cpu|hbreak_enabled ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 ; n/a ; Yes ; ++------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+-------------------------+ + + +Synchronizer Chain #1: Typical MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; GPIO_0[1] ; +; Synchronization Node ; system:inst_cpu|system_uart_0:uart_0|system_uart_0_rx:the_system_uart_0_rx|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------+ + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++-----------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++-----------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 17.219 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 12.5 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; 10.000 ; 100.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; GPIO_0[1] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; system:inst_cpu|system_uart_0:uart_0|system_uart_0_rx:the_system_uart_0_rx|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 ; ; ; ; 9.315 ; +; system:inst_cpu|system_uart_0:uart_0|system_uart_0_rx:the_system_uart_0_rx|altera_std_synchronizer:the_altera_std_synchronizer|dreg[0] ; ; ; ; 7.904 ; ++-----------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #2: Typical MTBF is Greater than 1 Billion Years +=============================================================================== ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; +; Synchronization Node ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer2|din_s1 ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 18.622 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 1.25 ; ; ; ; +; Source Clock ; ; ; ; ; +; altera_reserved_tck ; ; 100.000 ; 10.0 MHz ; ; +; Synchronization Clock ; ; ; ; ; +; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; 10.000 ; 100.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; ; ; ; ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; ; ; ; ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer2|din_s1 ; ; ; ; 9.316 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer2|dreg[0] ; ; ; ; 9.306 ; ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #3: Typical MTBF is Greater than 1 Billion Years +=============================================================================== ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; +; Synchronization Node ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3|din_s1 ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 18.624 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 1.25 ; ; ; ; +; Source Clock ; ; ; ; ; +; altera_reserved_tck ; ; 100.000 ; 10.0 MHz ; ; +; Synchronization Clock ; ; ; ; ; +; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; 10.000 ; 100.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; ; ; ; ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; ; ; ; ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3|din_s1 ; ; ; ; 9.317 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3|dreg[0] ; ; ; ; 9.307 ; ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #4: Typical MTBF is n/a Years +=============================================================================== ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_debug:the_system_cpu_nios2_oci_debug|monitor_ready ; +; Synchronization Node ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|din_s1 ; +; Typical MTBF (years) ; n/a ; +; Included in Design MTBF ; Yes ; ++-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Typical MTBF (years) ; n/a ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; n/a ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 12.5 ; ; ; ; +; Source Clock ; ; ; ; ; +; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; 10.000 ; 100.0 MHz ; ; +; Synchronization Clock ; ; ; ; ; +; altera_reserved_tck ; ; 100.000 ; 10.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_debug:the_system_cpu_nios2_oci_debug|monitor_ready ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|din_s1 ; ; ; ; n/a ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|dreg[0] ; ; ; ; n/a ; ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #5: Typical MTBF is n/a Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; system:inst_cpu|system_cpu:cpu|hbreak_enabled ; +; Synchronization Node ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 ; +; Typical MTBF (years) ; n/a ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Typical MTBF (years) ; n/a ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; n/a ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 12.5 ; ; ; ; +; Source Clock ; ; ; ; ; +; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; 10.000 ; 100.0 MHz ; ; +; Synchronization Clock ; ; ; ; ; +; altera_reserved_tck ; ; 100.000 ; 10.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; system:inst_cpu|system_cpu:cpu|hbreak_enabled ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 ; ; ; ; n/a ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer|dreg[0] ; ; ; ; n/a ; ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+ + + + ++-----------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Setup Summary ; ++----------------------------------------------------------+--------+---------------+ +; Clock ; Slack ; End Point TNS ; ++----------------------------------------------------------+--------+---------------+ +; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 3.265 ; 0.000 ; +; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 98.512 ; 0.000 ; ++----------------------------------------------------------+--------+---------------+ + + ++----------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Hold Summary ; ++----------------------------------------------------------+-------+---------------+ +; Clock ; Slack ; End Point TNS ; ++----------------------------------------------------------+-------+---------------+ +; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.099 ; 0.000 ; +; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.193 ; 0.000 ; ++----------------------------------------------------------+-------+---------------+ + + ++----------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Recovery Summary ; ++----------------------------------------------------------+-------+---------------+ +; Clock ; Slack ; End Point TNS ; ++----------------------------------------------------------+-------+---------------+ +; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 3.217 ; 0.000 ; ++----------------------------------------------------------+-------+---------------+ + + ++----------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Removal Summary ; ++----------------------------------------------------------+-------+---------------+ +; Clock ; Slack ; End Point TNS ; ++----------------------------------------------------------+-------+---------------+ +; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 1.268 ; 0.000 ; ++----------------------------------------------------------+-------+---------------+ + + ++-----------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Minimum Pulse Width Summary ; ++----------------------------------------------------------+--------+---------------+ +; Clock ; Slack ; End Point TNS ; ++----------------------------------------------------------+--------+---------------+ +; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 4.749 ; 0.000 ; +; CLOCK_50 ; 9.587 ; 0.000 ; +; altera_reserved_tck ; 49.482 ; 0.000 ; +; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 49.782 ; 0.000 ; ++----------------------------------------------------------+--------+---------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Setup: 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[0]' ; ++-------+------------------------------------------------+-------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+------------------------------------------------+-------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ +; 3.265 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[29] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.038 ; 1.684 ; +; 3.432 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[18] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.019 ; 1.536 ; +; 3.464 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[27] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.040 ; 1.483 ; +; 3.474 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[14] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.019 ; 1.494 ; +; 3.477 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[26] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.019 ; 1.491 ; +; 3.484 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[25] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.038 ; 1.465 ; +; 3.501 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[3] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[24] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.029 ; 1.457 ; +; 3.501 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[3] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.029 ; 1.457 ; +; 3.501 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[3] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.029 ; 1.457 ; +; 3.501 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[3] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[20] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.029 ; 1.457 ; +; 3.501 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[3] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.029 ; 1.457 ; +; 3.501 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[3] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[16] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.029 ; 1.457 ; +; 3.501 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[3] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[28] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.029 ; 1.457 ; +; 3.501 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[3] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.029 ; 1.457 ; +; 3.501 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[27] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.040 ; 1.446 ; +; 3.503 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[24] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.029 ; 1.455 ; +; 3.513 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.028 ; 1.446 ; +; 3.516 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[29] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.038 ; 1.433 ; +; 3.516 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[26] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.031 ; 1.440 ; +; 3.522 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.019 ; 1.446 ; +; 3.527 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[22] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.019 ; 1.441 ; +; 3.532 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[23] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.028 ; 1.427 ; +; 3.533 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.029 ; 1.425 ; +; 3.533 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.029 ; 1.425 ; +; 3.533 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[31] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.028 ; 1.426 ; +; 3.547 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[27] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.028 ; 1.412 ; +; 3.547 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[28] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.029 ; 1.411 ; +; 3.550 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[21] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[29] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.025 ; 1.412 ; +; 3.551 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.028 ; 1.408 ; +; 3.553 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.028 ; 1.406 ; +; 3.560 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[15] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[23] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.027 ; 1.400 ; +; 3.566 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[15] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[27] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.027 ; 1.394 ; +; 3.566 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[28] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.041 ; 1.380 ; +; 3.580 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[21] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.025 ; 1.382 ; +; 3.580 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[29] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.038 ; 1.369 ; +; 3.591 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[25] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.038 ; 1.358 ; +; 3.598 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[30] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.019 ; 1.370 ; +; 3.611 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[26] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[6] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.031 ; 1.345 ; +; 3.614 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.029 ; 1.344 ; +; 3.618 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[24] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.041 ; 1.328 ; +; 3.623 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.029 ; 1.335 ; +; 3.632 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[30] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.031 ; 1.324 ; +; 3.644 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[8] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[16] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.025 ; 1.318 ; +; 3.649 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[4] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[16] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.025 ; 1.313 ; +; 3.652 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[17] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.026 ; 1.309 ; +; 3.653 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.026 ; 1.308 ; +; 3.664 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[14] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[26] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.018 ; 1.305 ; +; 3.667 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[16] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.029 ; 1.291 ; +; 3.669 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[17] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[25] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.025 ; 1.293 ; +; 3.672 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.026 ; 1.289 ; +; 3.679 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.019 ; 1.289 ; +; 3.680 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[5] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[17] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.022 ; 1.285 ; +; 3.680 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[30] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[6] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.031 ; 1.276 ; +; 3.683 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[3] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.024 ; 1.280 ; +; 3.686 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[11] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.027 ; 1.274 ; +; 3.687 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[11] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[23] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.027 ; 1.273 ; +; 3.692 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[13] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[25] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.025 ; 1.270 ; +; 3.697 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[5] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.022 ; 1.268 ; +; 3.698 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.028 ; 1.261 ; +; 3.699 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[8] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[20] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.025 ; 1.263 ; +; 3.699 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[17] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[29] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.025 ; 1.263 ; +; 3.699 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[20] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.029 ; 1.259 ; +; 3.704 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[10] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[18] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.018 ; 1.265 ; +; 3.709 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[24] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.041 ; 1.237 ; +; 3.712 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[14] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[22] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.018 ; 1.257 ; +; 3.719 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[7] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.024 ; 1.244 ; +; 3.735 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[13] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.025 ; 1.227 ; +; 3.737 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[4] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.025 ; 1.225 ; +; 3.742 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[28] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.041 ; 1.204 ; +; 3.754 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[29] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[29] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.038 ; 1.195 ; +; 3.755 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[9] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.025 ; 1.207 ; +; 3.758 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[6] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.019 ; 1.210 ; +; 3.773 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[7] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.024 ; 1.190 ; +; 3.774 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[3] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.024 ; 1.189 ; +; 3.775 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.028 ; 1.184 ; +; 3.801 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[27] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[31] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.040 ; 1.146 ; +; 3.804 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[18] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[26] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.018 ; 1.165 ; +; 3.804 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[25] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[25] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.038 ; 1.145 ; +; 3.805 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[3] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.028 ; 1.154 ; +; 3.805 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[3] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[27] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.028 ; 1.154 ; +; 3.805 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[3] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[23] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.028 ; 1.154 ; +; 3.805 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[3] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.028 ; 1.154 ; +; 3.805 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[3] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.028 ; 1.154 ; +; 3.805 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[3] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.028 ; 1.154 ; +; 3.805 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[3] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.028 ; 1.154 ; +; 3.805 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[3] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[31] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.028 ; 1.154 ; +; 3.807 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[12] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[24] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.028 ; 1.152 ; +; 3.813 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[9] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[17] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.025 ; 1.149 ; +; 3.814 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.026 ; 1.147 ; +; 3.817 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[27] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[27] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.040 ; 1.130 ; +; 3.819 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[29] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.026 ; 1.142 ; +; 3.821 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[31] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.025 ; 1.141 ; +; 3.822 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[25] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.026 ; 1.139 ; +; 3.823 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[19] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[31] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.027 ; 1.137 ; +; 3.825 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[3] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[14] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.019 ; 1.143 ; +; 3.825 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[3] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[6] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.019 ; 1.143 ; +; 3.825 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[3] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[22] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.019 ; 1.143 ; +; 3.825 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[3] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[26] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.019 ; 1.143 ; +; 3.825 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[3] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.019 ; 1.143 ; +; 3.825 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[3] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[18] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.019 ; 1.143 ; ++-------+------------------------------------------------+-------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Setup: 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[2]' ; ++--------+-------------------------------------------+-------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++--------+-------------------------------------------+-------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ +; 98.512 ; heartbeat:inst_heartbeat|counter_data[2] ; heartbeat:inst_heartbeat|counter_data[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.436 ; +; 98.559 ; heartbeat:inst_heartbeat|counter_data[0] ; heartbeat:inst_heartbeat|counter_data[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.389 ; +; 98.562 ; heartbeat:inst_heartbeat|counter_data[1] ; heartbeat:inst_heartbeat|counter_data[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.386 ; +; 98.576 ; heartbeat:inst_heartbeat|counter_data[2] ; heartbeat:inst_heartbeat|counter_data[20] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.372 ; +; 98.580 ; heartbeat:inst_heartbeat|counter_data[2] ; heartbeat:inst_heartbeat|counter_data[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.368 ; +; 98.581 ; heartbeat:inst_heartbeat|counter_data[4] ; heartbeat:inst_heartbeat|counter_data[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.367 ; +; 98.590 ; heartbeat:inst_heartbeat|counter_data[0] ; heartbeat:inst_heartbeat|counter_data[20] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.358 ; +; 98.591 ; heartbeat:inst_heartbeat|counter_data[1] ; heartbeat:inst_heartbeat|counter_data[20] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.357 ; +; 98.627 ; heartbeat:inst_heartbeat|counter_data[0] ; heartbeat:inst_heartbeat|counter_data[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.321 ; +; 98.629 ; heartbeat:inst_heartbeat|counter_data[3] ; heartbeat:inst_heartbeat|counter_data[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.319 ; +; 98.630 ; heartbeat:inst_heartbeat|counter_data[1] ; heartbeat:inst_heartbeat|counter_data[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.318 ; +; 98.644 ; heartbeat:inst_heartbeat|counter_data[2] ; heartbeat:inst_heartbeat|counter_data[18] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.304 ; +; 98.645 ; heartbeat:inst_heartbeat|counter_data[4] ; heartbeat:inst_heartbeat|counter_data[20] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.303 ; +; 98.648 ; heartbeat:inst_heartbeat|counter_data[2] ; heartbeat:inst_heartbeat|counter_data[17] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.300 ; +; 98.649 ; heartbeat:inst_heartbeat|counter_data[4] ; heartbeat:inst_heartbeat|counter_data[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.299 ; +; 98.653 ; heartbeat:inst_heartbeat|counter_data[6] ; heartbeat:inst_heartbeat|counter_data[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.295 ; +; 98.658 ; heartbeat:inst_heartbeat|counter_data[0] ; heartbeat:inst_heartbeat|counter_data[18] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.290 ; +; 98.659 ; heartbeat:inst_heartbeat|counter_data[3] ; heartbeat:inst_heartbeat|counter_data[20] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.289 ; +; 98.659 ; heartbeat:inst_heartbeat|counter_data[1] ; heartbeat:inst_heartbeat|counter_data[18] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.289 ; +; 98.695 ; heartbeat:inst_heartbeat|counter_data[0] ; heartbeat:inst_heartbeat|counter_data[17] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.253 ; +; 98.697 ; heartbeat:inst_heartbeat|counter_data[5] ; heartbeat:inst_heartbeat|counter_data[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.251 ; +; 98.697 ; heartbeat:inst_heartbeat|counter_data[3] ; heartbeat:inst_heartbeat|counter_data[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.251 ; +; 98.698 ; heartbeat:inst_heartbeat|counter_data[1] ; heartbeat:inst_heartbeat|counter_data[17] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.250 ; +; 98.712 ; heartbeat:inst_heartbeat|counter_data[2] ; heartbeat:inst_heartbeat|counter_data[16] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.236 ; +; 98.713 ; heartbeat:inst_heartbeat|counter_data[4] ; heartbeat:inst_heartbeat|counter_data[18] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.235 ; +; 98.716 ; heartbeat:inst_heartbeat|counter_data[2] ; heartbeat:inst_heartbeat|counter_data[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.232 ; +; 98.717 ; heartbeat:inst_heartbeat|counter_data[6] ; heartbeat:inst_heartbeat|counter_data[20] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.231 ; +; 98.717 ; heartbeat:inst_heartbeat|counter_data[4] ; heartbeat:inst_heartbeat|counter_data[17] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.231 ; +; 98.720 ; heartbeat:inst_heartbeat|counter_data[8] ; heartbeat:inst_heartbeat|counter_data[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.228 ; +; 98.721 ; heartbeat:inst_heartbeat|counter_data[6] ; heartbeat:inst_heartbeat|counter_data[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.227 ; +; 98.726 ; heartbeat:inst_heartbeat|counter_data[5] ; heartbeat:inst_heartbeat|counter_data[20] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.222 ; +; 98.726 ; heartbeat:inst_heartbeat|counter_data[0] ; heartbeat:inst_heartbeat|counter_data[16] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.222 ; +; 98.727 ; heartbeat:inst_heartbeat|counter_data[3] ; heartbeat:inst_heartbeat|counter_data[18] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.221 ; +; 98.727 ; heartbeat:inst_heartbeat|counter_data[1] ; heartbeat:inst_heartbeat|counter_data[16] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.221 ; +; 98.763 ; heartbeat:inst_heartbeat|counter_data[0] ; heartbeat:inst_heartbeat|counter_data[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.185 ; +; 98.765 ; heartbeat:inst_heartbeat|counter_data[7] ; heartbeat:inst_heartbeat|counter_data[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.183 ; +; 98.765 ; heartbeat:inst_heartbeat|counter_data[5] ; heartbeat:inst_heartbeat|counter_data[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.183 ; +; 98.765 ; heartbeat:inst_heartbeat|counter_data[3] ; heartbeat:inst_heartbeat|counter_data[17] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.183 ; +; 98.766 ; heartbeat:inst_heartbeat|counter_data[1] ; heartbeat:inst_heartbeat|counter_data[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.182 ; +; 98.780 ; heartbeat:inst_heartbeat|counter_data[2] ; heartbeat:inst_heartbeat|counter_data[14] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.168 ; +; 98.781 ; heartbeat:inst_heartbeat|counter_data[4] ; heartbeat:inst_heartbeat|counter_data[16] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.167 ; +; 98.784 ; heartbeat:inst_heartbeat|counter_data[2] ; heartbeat:inst_heartbeat|counter_data[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.164 ; +; 98.784 ; heartbeat:inst_heartbeat|counter_data[8] ; heartbeat:inst_heartbeat|counter_data[20] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.164 ; +; 98.785 ; heartbeat:inst_heartbeat|counter_data[6] ; heartbeat:inst_heartbeat|counter_data[18] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.163 ; +; 98.785 ; heartbeat:inst_heartbeat|counter_data[4] ; heartbeat:inst_heartbeat|counter_data[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.163 ; +; 98.788 ; heartbeat:inst_heartbeat|counter_data[8] ; heartbeat:inst_heartbeat|counter_data[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.160 ; +; 98.789 ; heartbeat:inst_heartbeat|counter_data[10] ; heartbeat:inst_heartbeat|counter_data[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.159 ; +; 98.789 ; heartbeat:inst_heartbeat|counter_data[6] ; heartbeat:inst_heartbeat|counter_data[17] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.159 ; +; 98.794 ; heartbeat:inst_heartbeat|counter_data[7] ; heartbeat:inst_heartbeat|counter_data[20] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.154 ; +; 98.794 ; heartbeat:inst_heartbeat|counter_data[5] ; heartbeat:inst_heartbeat|counter_data[18] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.154 ; +; 98.794 ; heartbeat:inst_heartbeat|counter_data[0] ; heartbeat:inst_heartbeat|counter_data[14] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.154 ; +; 98.795 ; heartbeat:inst_heartbeat|counter_data[3] ; heartbeat:inst_heartbeat|counter_data[16] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.153 ; +; 98.795 ; heartbeat:inst_heartbeat|counter_data[1] ; heartbeat:inst_heartbeat|counter_data[14] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.153 ; +; 98.831 ; heartbeat:inst_heartbeat|counter_data[0] ; heartbeat:inst_heartbeat|counter_data[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.117 ; +; 98.833 ; heartbeat:inst_heartbeat|counter_data[9] ; heartbeat:inst_heartbeat|counter_data[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.115 ; +; 98.833 ; heartbeat:inst_heartbeat|counter_data[7] ; heartbeat:inst_heartbeat|counter_data[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.115 ; +; 98.833 ; heartbeat:inst_heartbeat|counter_data[5] ; heartbeat:inst_heartbeat|counter_data[17] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.115 ; +; 98.833 ; heartbeat:inst_heartbeat|counter_data[3] ; heartbeat:inst_heartbeat|counter_data[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.115 ; +; 98.834 ; heartbeat:inst_heartbeat|counter_data[1] ; heartbeat:inst_heartbeat|counter_data[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.114 ; +; 98.848 ; heartbeat:inst_heartbeat|counter_data[2] ; heartbeat:inst_heartbeat|counter_data[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.100 ; +; 98.849 ; heartbeat:inst_heartbeat|counter_data[4] ; heartbeat:inst_heartbeat|counter_data[14] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.099 ; +; 98.852 ; heartbeat:inst_heartbeat|counter_data[2] ; heartbeat:inst_heartbeat|counter_data[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.096 ; +; 98.852 ; heartbeat:inst_heartbeat|counter_data[8] ; heartbeat:inst_heartbeat|counter_data[18] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.096 ; +; 98.853 ; heartbeat:inst_heartbeat|counter_data[10] ; heartbeat:inst_heartbeat|counter_data[20] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.095 ; +; 98.853 ; heartbeat:inst_heartbeat|counter_data[6] ; heartbeat:inst_heartbeat|counter_data[16] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.095 ; +; 98.853 ; heartbeat:inst_heartbeat|counter_data[4] ; heartbeat:inst_heartbeat|counter_data[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.095 ; +; 98.855 ; heartbeat:inst_heartbeat|counter_data[12] ; heartbeat:inst_heartbeat|counter_data[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.037 ; 1.095 ; +; 98.856 ; heartbeat:inst_heartbeat|counter_data[8] ; heartbeat:inst_heartbeat|counter_data[17] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.092 ; +; 98.857 ; heartbeat:inst_heartbeat|counter_data[10] ; heartbeat:inst_heartbeat|counter_data[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.091 ; +; 98.857 ; heartbeat:inst_heartbeat|counter_data[6] ; heartbeat:inst_heartbeat|counter_data[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.091 ; +; 98.862 ; heartbeat:inst_heartbeat|counter_data[7] ; heartbeat:inst_heartbeat|counter_data[18] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.086 ; +; 98.862 ; heartbeat:inst_heartbeat|counter_data[5] ; heartbeat:inst_heartbeat|counter_data[16] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.086 ; +; 98.862 ; heartbeat:inst_heartbeat|counter_data[0] ; heartbeat:inst_heartbeat|counter_data[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.086 ; +; 98.863 ; heartbeat:inst_heartbeat|counter_data[9] ; heartbeat:inst_heartbeat|counter_data[20] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.085 ; +; 98.863 ; heartbeat:inst_heartbeat|counter_data[3] ; heartbeat:inst_heartbeat|counter_data[14] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.085 ; +; 98.863 ; heartbeat:inst_heartbeat|counter_data[1] ; heartbeat:inst_heartbeat|counter_data[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.085 ; +; 98.899 ; heartbeat:inst_heartbeat|counter_data[0] ; heartbeat:inst_heartbeat|counter_data[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.049 ; +; 98.901 ; heartbeat:inst_heartbeat|counter_data[9] ; heartbeat:inst_heartbeat|counter_data[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.047 ; +; 98.901 ; heartbeat:inst_heartbeat|counter_data[7] ; heartbeat:inst_heartbeat|counter_data[17] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.047 ; +; 98.901 ; heartbeat:inst_heartbeat|counter_data[5] ; heartbeat:inst_heartbeat|counter_data[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.047 ; +; 98.901 ; heartbeat:inst_heartbeat|counter_data[3] ; heartbeat:inst_heartbeat|counter_data[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.047 ; +; 98.902 ; heartbeat:inst_heartbeat|counter_data[1] ; heartbeat:inst_heartbeat|counter_data[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.046 ; +; 98.903 ; heartbeat:inst_heartbeat|counter_data[11] ; heartbeat:inst_heartbeat|counter_data[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.037 ; 1.047 ; +; 98.917 ; heartbeat:inst_heartbeat|counter_data[4] ; heartbeat:inst_heartbeat|counter_data[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.031 ; +; 98.918 ; heartbeat:inst_heartbeat|counter_data[2] ; heartbeat:inst_heartbeat|counter_data[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.037 ; 1.032 ; +; 98.919 ; heartbeat:inst_heartbeat|counter_data[12] ; heartbeat:inst_heartbeat|counter_data[20] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.037 ; 1.031 ; +; 98.920 ; heartbeat:inst_heartbeat|counter_data[8] ; heartbeat:inst_heartbeat|counter_data[16] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.028 ; +; 98.921 ; heartbeat:inst_heartbeat|counter_data[10] ; heartbeat:inst_heartbeat|counter_data[18] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.027 ; +; 98.921 ; heartbeat:inst_heartbeat|counter_data[6] ; heartbeat:inst_heartbeat|counter_data[14] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.027 ; +; 98.921 ; heartbeat:inst_heartbeat|counter_data[4] ; heartbeat:inst_heartbeat|counter_data[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.027 ; +; 98.922 ; heartbeat:inst_heartbeat|counter_data[2] ; heartbeat:inst_heartbeat|counter_data[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.037 ; 1.028 ; +; 98.923 ; heartbeat:inst_heartbeat|counter_data[12] ; heartbeat:inst_heartbeat|counter_data[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.037 ; 1.027 ; +; 98.924 ; heartbeat:inst_heartbeat|counter_data[8] ; heartbeat:inst_heartbeat|counter_data[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.024 ; +; 98.925 ; heartbeat:inst_heartbeat|counter_data[14] ; heartbeat:inst_heartbeat|counter_data[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.037 ; 1.025 ; +; 98.925 ; heartbeat:inst_heartbeat|counter_data[10] ; heartbeat:inst_heartbeat|counter_data[17] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.023 ; +; 98.925 ; heartbeat:inst_heartbeat|counter_data[6] ; heartbeat:inst_heartbeat|counter_data[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.023 ; +; 98.930 ; heartbeat:inst_heartbeat|counter_data[7] ; heartbeat:inst_heartbeat|counter_data[16] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.018 ; +; 98.930 ; heartbeat:inst_heartbeat|counter_data[5] ; heartbeat:inst_heartbeat|counter_data[14] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.018 ; +; 98.931 ; heartbeat:inst_heartbeat|counter_data[9] ; heartbeat:inst_heartbeat|counter_data[18] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.017 ; +; 98.931 ; heartbeat:inst_heartbeat|counter_data[3] ; heartbeat:inst_heartbeat|counter_data[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 100.000 ; -0.039 ; 1.017 ; ++--------+-------------------------------------------+-------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Hold: 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[0]' ; ++-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ +; 0.099 ; system:inst_cpu|system_cpu:cpu|i_readdata_d1[11] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a11~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.226 ; 0.429 ; +; 0.102 ; system:inst_cpu|system_cpu:cpu|ic_fill_valid_bits[6] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.220 ; 0.426 ; +; 0.105 ; system:inst_cpu|system_cpu:cpu|ic_fill_valid_bits[0] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.220 ; 0.429 ; +; 0.139 ; system:inst_cpu|system_cpu:cpu|i_readdata_d1[15] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a11~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.225 ; 0.468 ; +; 0.140 ; system:inst_cpu|system_cpu:cpu|i_readdata_d1[0] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.222 ; 0.466 ; +; 0.143 ; system:inst_cpu|system_cpu:cpu|ic_tag_wraddress[3] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.219 ; 0.466 ; +; 0.144 ; system:inst_cpu|system_cpu:cpu|i_readdata_d1[14] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a11~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.225 ; 0.473 ; +; 0.144 ; system:inst_cpu|system_cpu:cpu|ic_fill_valid_bits[4] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.220 ; 0.468 ; +; 0.145 ; system:inst_cpu|system_cpu:cpu|i_readdata_d1[3] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.222 ; 0.471 ; +; 0.145 ; system:inst_cpu|system_cpu:cpu|ic_tag_wraddress[7] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.219 ; 0.468 ; +; 0.145 ; system:inst_cpu|system_cpu:cpu|M_bht_ptr_unfiltered[2] ; system:inst_cpu|system_cpu:cpu|system_cpu_bht_module:system_cpu_bht|altsyncram:the_altsyncram|altsyncram_fhg1:auto_generated|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.219 ; 0.468 ; +; 0.149 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[28] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.225 ; 0.478 ; +; 0.149 ; system:inst_cpu|system_cpu:cpu|ic_tag_wraddress[2] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.219 ; 0.472 ; +; 0.149 ; system:inst_cpu|system_cpu:cpu|ic_fill_valid_bits[7] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.220 ; 0.473 ; +; 0.150 ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|data_in_shift_reg[3] ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.222 ; 0.476 ; +; 0.150 ; system:inst_cpu|system_cpu:cpu|ic_fill_valid_bits[2] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.220 ; 0.474 ; +; 0.151 ; system:inst_cpu|system_cpu:cpu|ic_tag_wraddress[1] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.219 ; 0.474 ; +; 0.151 ; system:inst_cpu|system_cpu:cpu|ic_tag_wraddress[5] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.219 ; 0.474 ; +; 0.152 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[25] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.225 ; 0.481 ; +; 0.152 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[30] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.225 ; 0.481 ; +; 0.152 ; system:inst_cpu|system_rs232_motor:rs232_motor|data_to_uart[7] ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.221 ; 0.477 ; +; 0.152 ; system:inst_cpu|system_cpu:cpu|M_bht_ptr_unfiltered[4] ; system:inst_cpu|system_cpu:cpu|system_cpu_bht_module:system_cpu_bht|altsyncram:the_altsyncram|altsyncram_fhg1:auto_generated|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.224 ; 0.480 ; +; 0.154 ; system:inst_cpu|system_rs232_motor:rs232_motor|data_to_uart[3] ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.221 ; 0.479 ; +; 0.154 ; system:inst_cpu|system_cpu:cpu|M_bht_ptr_unfiltered[3] ; system:inst_cpu|system_cpu:cpu|system_cpu_bht_module:system_cpu_bht|altsyncram:the_altsyncram|altsyncram_fhg1:auto_generated|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.223 ; 0.481 ; +; 0.155 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[27] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.225 ; 0.484 ; +; 0.155 ; system:inst_cpu|system_cpu:cpu|i_readdata_d1[2] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.222 ; 0.481 ; +; 0.155 ; system:inst_cpu|system_cpu:cpu|ic_fill_tag[8] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.221 ; 0.480 ; +; 0.156 ; system:inst_cpu|system_cpu:cpu|ic_tag_wraddress[4] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.219 ; 0.479 ; +; 0.157 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[13] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.225 ; 0.486 ; +; 0.157 ; system:inst_cpu|system_cpu:cpu|M_bht_ptr_unfiltered[7] ; system:inst_cpu|system_cpu:cpu|system_cpu_bht_module:system_cpu_bht|altsyncram:the_altsyncram|altsyncram_fhg1:auto_generated|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.223 ; 0.484 ; +; 0.158 ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[1] ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.219 ; 0.481 ; +; 0.158 ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[3] ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.219 ; 0.481 ; +; 0.158 ; system:inst_cpu|system_rs232_motor:rs232_motor|data_to_uart[1] ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.222 ; 0.484 ; +; 0.159 ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[6] ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.219 ; 0.482 ; +; 0.160 ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[0] ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.222 ; 0.486 ; +; 0.160 ; system:inst_cpu|system_cpu:cpu|ic_fill_valid_bits[1] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.220 ; 0.484 ; +; 0.160 ; system:inst_cpu|system_cpu:cpu|M_bht_ptr_unfiltered[1] ; system:inst_cpu|system_cpu:cpu|system_cpu_bht_module:system_cpu_bht|altsyncram:the_altsyncram|altsyncram_fhg1:auto_generated|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.219 ; 0.483 ; +; 0.161 ; system:inst_cpu|system_cpu:cpu|ic_fill_tag[1] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.221 ; 0.486 ; +; 0.162 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[15] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.225 ; 0.491 ; +; 0.162 ; system:inst_cpu|system_cpu:cpu|i_readdata_d1[1] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.226 ; 0.492 ; +; 0.162 ; system:inst_cpu|system_cpu:cpu|ic_fill_valid_bits[3] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.220 ; 0.486 ; +; 0.163 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[4] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a0~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.243 ; 0.510 ; +; 0.163 ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[1] ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.222 ; 0.489 ; +; 0.163 ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[3] ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.219 ; 0.486 ; +; 0.164 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[31] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.225 ; 0.493 ; +; 0.166 ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[6] ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.222 ; 0.492 ; +; 0.166 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[29] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.225 ; 0.495 ; +; 0.167 ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[5] ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.222 ; 0.493 ; +; 0.167 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[12] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.226 ; 0.497 ; +; 0.168 ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[0] ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.219 ; 0.491 ; +; 0.168 ; system:inst_cpu|system_cpu:cpu|i_readdata_d1[31] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a22~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.223 ; 0.495 ; +; 0.168 ; system:inst_cpu|system_cpu:cpu|ic_tag_wraddress[0] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.219 ; 0.491 ; +; 0.169 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[26] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.225 ; 0.498 ; +; 0.170 ; system:inst_cpu|system_cpu:cpu|M_bht_ptr_unfiltered[6] ; system:inst_cpu|system_cpu:cpu|system_cpu_bht_module:system_cpu_bht|altsyncram:the_altsyncram|altsyncram_fhg1:auto_generated|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.219 ; 0.493 ; +; 0.171 ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[3] ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.222 ; 0.497 ; +; 0.171 ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[2] ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.219 ; 0.494 ; +; 0.171 ; system:inst_cpu|system_cpu:cpu|ic_fill_tag[5] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.221 ; 0.496 ; +; 0.171 ; system:inst_cpu|system_cpu:cpu|ic_fill_tag[6] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.221 ; 0.496 ; +; 0.172 ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[2] ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.222 ; 0.498 ; +; 0.172 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[9] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.226 ; 0.502 ; +; 0.172 ; system:inst_cpu|system_cpu:cpu|ic_tag_wraddress[6] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.219 ; 0.495 ; +; 0.174 ; system:inst_cpu|system_cpu:cpu|ic_fill_valid_bits[5] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.220 ; 0.498 ; +; 0.176 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[8] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.225 ; 0.505 ; +; 0.177 ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[0] ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.219 ; 0.500 ; +; 0.177 ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[1] ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.219 ; 0.500 ; +; 0.179 ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[1] ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.219 ; 0.502 ; +; 0.180 ; system:inst_cpu|system_cpu:cpu|ic_fill_tag[4] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.221 ; 0.505 ; +; 0.180 ; system:inst_cpu|system_cpu:cpu|ic_fill_tag[11] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.214 ; 0.498 ; +; 0.184 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[11] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.226 ; 0.514 ; +; 0.185 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[10] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.225 ; 0.514 ; +; 0.185 ; system:inst_cpu|system_cpu:cpu|ic_fill_tag[7] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.221 ; 0.510 ; +; 0.186 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3|din_s1 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3|dreg[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.044 ; 0.314 ; +; 0.186 ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|usedw_is_2_dff ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|usedw_is_2_dff ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.307 ; +; 0.186 ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|usedw_is_0_dff ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|usedw_is_0_dff ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.307 ; +; 0.186 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_debug:the_system_cpu_nios2_oci_debug|probepresent ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_debug:the_system_cpu_nios2_oci_debug|probepresent ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.307 ; +; 0.186 ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|transmitting_data ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|transmitting_data ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.307 ; +; 0.186 ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|low_addressa[3] ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|low_addressa[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.307 ; +; 0.186 ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|low_addressa[0] ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|low_addressa[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.307 ; +; 0.186 ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|data_out_shift_reg[8] ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|data_out_shift_reg[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.307 ; +; 0.186 ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|data_out_shift_reg[0] ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|data_out_shift_reg[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.307 ; +; 0.186 ; system:inst_cpu|altera_merlin_slave_translator:cpu_jtag_debug_module_translator|end_begintransfer ; system:inst_cpu|altera_merlin_slave_translator:cpu_jtag_debug_module_translator|end_begintransfer ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.307 ; +; 0.186 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonRd ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonRd ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.307 ; +; 0.186 ; system:inst_cpu|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; system:inst_cpu|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.307 ; +; 0.186 ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[9] ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.307 ; +; 0.186 ; system:inst_cpu|altera_merlin_slave_translator:uart_0_s1_translator|wait_latency_counter[1] ; system:inst_cpu|altera_merlin_slave_translator:uart_0_s1_translator|wait_latency_counter[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.307 ; +; 0.186 ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[12] ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.307 ; +; 0.186 ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[14] ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[14] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.307 ; +; 0.186 ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[13] ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.307 ; +; 0.186 ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[11] ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.307 ; +; 0.186 ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[10] ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.307 ; +; 0.186 ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[8] ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.307 ; +; 0.186 ; system:inst_cpu|altera_merlin_slave_translator:uart_0_s1_translator|end_begintransfer ; system:inst_cpu|altera_merlin_slave_translator:uart_0_s1_translator|end_begintransfer ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.307 ; +; 0.186 ; system:inst_cpu|system_uart_0:uart_0|system_uart_0_rx:the_system_uart_0_rx|rx_overrun ; system:inst_cpu|system_uart_0:uart_0|system_uart_0_rx:the_system_uart_0_rx|rx_overrun ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.307 ; +; 0.186 ; system:inst_cpu|system_uart_0:uart_0|system_uart_0_rx:the_system_uart_0_rx|break_detect ; system:inst_cpu|system_uart_0:uart_0|system_uart_0_rx:the_system_uart_0_rx|break_detect ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.307 ; +; 0.186 ; system:inst_cpu|system_uart_0:uart_0|system_uart_0_tx:the_system_uart_0_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[9] ; system:inst_cpu|system_uart_0:uart_0|system_uart_0_tx:the_system_uart_0_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.307 ; +; 0.186 ; system:inst_cpu|system_uart_0:uart_0|system_uart_0_tx:the_system_uart_0_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[0] ; system:inst_cpu|system_uart_0:uart_0|system_uart_0_tx:the_system_uart_0_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.307 ; +; 0.186 ; system:inst_cpu|system_uart_0:uart_0|system_uart_0_tx:the_system_uart_0_tx|tx_ready ; system:inst_cpu|system_uart_0:uart_0|system_uart_0_tx:the_system_uart_0_tx|tx_ready ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.307 ; +; 0.186 ; system:inst_cpu|altera_merlin_slave_translator:pio_led_s1_translator|wait_latency_counter[1] ; system:inst_cpu|altera_merlin_slave_translator:pio_led_s1_translator|wait_latency_counter[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.307 ; +; 0.186 ; system:inst_cpu|system_pio_led:pio_led|data_out[6] ; system:inst_cpu|system_pio_led:pio_led|data_out[6] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.307 ; +; 0.186 ; system:inst_cpu|system_pio_led:pio_led|data_out[5] ; system:inst_cpu|system_pio_led:pio_led|data_out[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.307 ; ++-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Hold: 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[2]' ; ++-------+-------------------------------------------+-------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+-------------------------------------------+-------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ +; 0.193 ; heartbeat:inst_heartbeat|counter_data[0] ; heartbeat:inst_heartbeat|counter_data[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.314 ; +; 0.204 ; heartbeat:inst_heartbeat|counter_data[21] ; heartbeat:inst_heartbeat|counter_data[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.325 ; +; 0.291 ; heartbeat:inst_heartbeat|counter_data[10] ; heartbeat:inst_heartbeat|counter_data[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.412 ; +; 0.292 ; heartbeat:inst_heartbeat|counter_data[8] ; heartbeat:inst_heartbeat|counter_data[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.413 ; +; 0.293 ; heartbeat:inst_heartbeat|counter_data[2] ; heartbeat:inst_heartbeat|counter_data[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.414 ; +; 0.293 ; heartbeat:inst_heartbeat|counter_data[6] ; heartbeat:inst_heartbeat|counter_data[6] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.414 ; +; 0.293 ; heartbeat:inst_heartbeat|counter_data[12] ; heartbeat:inst_heartbeat|counter_data[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.414 ; +; 0.293 ; heartbeat:inst_heartbeat|counter_data[14] ; heartbeat:inst_heartbeat|counter_data[14] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.414 ; +; 0.293 ; heartbeat:inst_heartbeat|counter_data[16] ; heartbeat:inst_heartbeat|counter_data[16] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.414 ; +; 0.294 ; heartbeat:inst_heartbeat|counter_data[3] ; heartbeat:inst_heartbeat|counter_data[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.415 ; +; 0.294 ; heartbeat:inst_heartbeat|counter_data[4] ; heartbeat:inst_heartbeat|counter_data[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.415 ; +; 0.294 ; heartbeat:inst_heartbeat|counter_data[9] ; heartbeat:inst_heartbeat|counter_data[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.415 ; +; 0.294 ; heartbeat:inst_heartbeat|counter_data[11] ; heartbeat:inst_heartbeat|counter_data[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.415 ; +; 0.294 ; heartbeat:inst_heartbeat|counter_data[17] ; heartbeat:inst_heartbeat|counter_data[17] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.415 ; +; 0.294 ; heartbeat:inst_heartbeat|counter_data[18] ; heartbeat:inst_heartbeat|counter_data[18] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.415 ; +; 0.294 ; heartbeat:inst_heartbeat|counter_data[20] ; heartbeat:inst_heartbeat|counter_data[20] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.415 ; +; 0.295 ; heartbeat:inst_heartbeat|counter_data[5] ; heartbeat:inst_heartbeat|counter_data[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.416 ; +; 0.295 ; heartbeat:inst_heartbeat|counter_data[7] ; heartbeat:inst_heartbeat|counter_data[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.416 ; +; 0.295 ; heartbeat:inst_heartbeat|counter_data[13] ; heartbeat:inst_heartbeat|counter_data[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.416 ; +; 0.295 ; heartbeat:inst_heartbeat|counter_data[15] ; heartbeat:inst_heartbeat|counter_data[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.416 ; +; 0.295 ; heartbeat:inst_heartbeat|counter_data[19] ; heartbeat:inst_heartbeat|counter_data[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.416 ; +; 0.299 ; heartbeat:inst_heartbeat|counter_data[1] ; heartbeat:inst_heartbeat|counter_data[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.420 ; +; 0.300 ; heartbeat:inst_heartbeat|counter_data[0] ; heartbeat:inst_heartbeat|counter_data[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.421 ; +; 0.441 ; heartbeat:inst_heartbeat|counter_data[8] ; heartbeat:inst_heartbeat|counter_data[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.562 ; +; 0.442 ; heartbeat:inst_heartbeat|counter_data[2] ; heartbeat:inst_heartbeat|counter_data[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.563 ; +; 0.442 ; heartbeat:inst_heartbeat|counter_data[10] ; heartbeat:inst_heartbeat|counter_data[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.035 ; 0.561 ; +; 0.442 ; heartbeat:inst_heartbeat|counter_data[16] ; heartbeat:inst_heartbeat|counter_data[17] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.563 ; +; 0.442 ; heartbeat:inst_heartbeat|counter_data[6] ; heartbeat:inst_heartbeat|counter_data[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.563 ; +; 0.442 ; heartbeat:inst_heartbeat|counter_data[12] ; heartbeat:inst_heartbeat|counter_data[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.563 ; +; 0.442 ; heartbeat:inst_heartbeat|counter_data[14] ; heartbeat:inst_heartbeat|counter_data[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.563 ; +; 0.443 ; heartbeat:inst_heartbeat|counter_data[20] ; heartbeat:inst_heartbeat|counter_data[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.564 ; +; 0.443 ; heartbeat:inst_heartbeat|counter_data[4] ; heartbeat:inst_heartbeat|counter_data[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.564 ; +; 0.443 ; heartbeat:inst_heartbeat|counter_data[18] ; heartbeat:inst_heartbeat|counter_data[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.564 ; +; 0.451 ; heartbeat:inst_heartbeat|counter_data[1] ; heartbeat:inst_heartbeat|counter_data[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.572 ; +; 0.452 ; heartbeat:inst_heartbeat|counter_data[9] ; heartbeat:inst_heartbeat|counter_data[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.573 ; +; 0.452 ; heartbeat:inst_heartbeat|counter_data[11] ; heartbeat:inst_heartbeat|counter_data[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.573 ; +; 0.452 ; heartbeat:inst_heartbeat|counter_data[3] ; heartbeat:inst_heartbeat|counter_data[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.573 ; +; 0.452 ; heartbeat:inst_heartbeat|counter_data[17] ; heartbeat:inst_heartbeat|counter_data[18] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.573 ; +; 0.453 ; heartbeat:inst_heartbeat|counter_data[7] ; heartbeat:inst_heartbeat|counter_data[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.574 ; +; 0.453 ; heartbeat:inst_heartbeat|counter_data[5] ; heartbeat:inst_heartbeat|counter_data[6] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.574 ; +; 0.453 ; heartbeat:inst_heartbeat|counter_data[13] ; heartbeat:inst_heartbeat|counter_data[14] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.574 ; +; 0.453 ; heartbeat:inst_heartbeat|counter_data[15] ; heartbeat:inst_heartbeat|counter_data[16] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.574 ; +; 0.453 ; heartbeat:inst_heartbeat|counter_data[19] ; heartbeat:inst_heartbeat|counter_data[20] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.574 ; +; 0.453 ; heartbeat:inst_heartbeat|counter_data[0] ; heartbeat:inst_heartbeat|counter_data[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.574 ; +; 0.454 ; heartbeat:inst_heartbeat|counter_data[1] ; heartbeat:inst_heartbeat|counter_data[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.575 ; +; 0.455 ; heartbeat:inst_heartbeat|counter_data[11] ; heartbeat:inst_heartbeat|counter_data[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.576 ; +; 0.455 ; heartbeat:inst_heartbeat|counter_data[3] ; heartbeat:inst_heartbeat|counter_data[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.576 ; +; 0.455 ; heartbeat:inst_heartbeat|counter_data[17] ; heartbeat:inst_heartbeat|counter_data[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.576 ; +; 0.456 ; heartbeat:inst_heartbeat|counter_data[7] ; heartbeat:inst_heartbeat|counter_data[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.577 ; +; 0.456 ; heartbeat:inst_heartbeat|counter_data[15] ; heartbeat:inst_heartbeat|counter_data[17] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.577 ; +; 0.456 ; heartbeat:inst_heartbeat|counter_data[5] ; heartbeat:inst_heartbeat|counter_data[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.577 ; +; 0.456 ; heartbeat:inst_heartbeat|counter_data[13] ; heartbeat:inst_heartbeat|counter_data[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.577 ; +; 0.456 ; heartbeat:inst_heartbeat|counter_data[19] ; heartbeat:inst_heartbeat|counter_data[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.577 ; +; 0.456 ; heartbeat:inst_heartbeat|counter_data[0] ; heartbeat:inst_heartbeat|counter_data[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.577 ; +; 0.457 ; heartbeat:inst_heartbeat|counter_data[9] ; heartbeat:inst_heartbeat|counter_data[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.035 ; 0.576 ; +; 0.504 ; heartbeat:inst_heartbeat|counter_data[8] ; heartbeat:inst_heartbeat|counter_data[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.625 ; +; 0.505 ; heartbeat:inst_heartbeat|counter_data[10] ; heartbeat:inst_heartbeat|counter_data[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.035 ; 0.624 ; +; 0.505 ; heartbeat:inst_heartbeat|counter_data[2] ; heartbeat:inst_heartbeat|counter_data[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.626 ; +; 0.505 ; heartbeat:inst_heartbeat|counter_data[16] ; heartbeat:inst_heartbeat|counter_data[18] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.626 ; +; 0.505 ; heartbeat:inst_heartbeat|counter_data[6] ; heartbeat:inst_heartbeat|counter_data[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.626 ; +; 0.505 ; heartbeat:inst_heartbeat|counter_data[12] ; heartbeat:inst_heartbeat|counter_data[14] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.626 ; +; 0.505 ; heartbeat:inst_heartbeat|counter_data[14] ; heartbeat:inst_heartbeat|counter_data[16] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.626 ; +; 0.506 ; heartbeat:inst_heartbeat|counter_data[4] ; heartbeat:inst_heartbeat|counter_data[6] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.627 ; +; 0.506 ; heartbeat:inst_heartbeat|counter_data[18] ; heartbeat:inst_heartbeat|counter_data[20] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.627 ; +; 0.508 ; heartbeat:inst_heartbeat|counter_data[10] ; heartbeat:inst_heartbeat|counter_data[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.035 ; 0.627 ; +; 0.508 ; heartbeat:inst_heartbeat|counter_data[2] ; heartbeat:inst_heartbeat|counter_data[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.629 ; +; 0.508 ; heartbeat:inst_heartbeat|counter_data[16] ; heartbeat:inst_heartbeat|counter_data[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.629 ; +; 0.508 ; heartbeat:inst_heartbeat|counter_data[6] ; heartbeat:inst_heartbeat|counter_data[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.629 ; +; 0.508 ; heartbeat:inst_heartbeat|counter_data[14] ; heartbeat:inst_heartbeat|counter_data[17] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.629 ; +; 0.508 ; heartbeat:inst_heartbeat|counter_data[12] ; heartbeat:inst_heartbeat|counter_data[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.629 ; +; 0.509 ; heartbeat:inst_heartbeat|counter_data[4] ; heartbeat:inst_heartbeat|counter_data[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.630 ; +; 0.509 ; heartbeat:inst_heartbeat|counter_data[18] ; heartbeat:inst_heartbeat|counter_data[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.630 ; +; 0.509 ; heartbeat:inst_heartbeat|counter_data[8] ; heartbeat:inst_heartbeat|counter_data[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.035 ; 0.628 ; +; 0.517 ; heartbeat:inst_heartbeat|counter_data[1] ; heartbeat:inst_heartbeat|counter_data[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.638 ; +; 0.518 ; heartbeat:inst_heartbeat|counter_data[11] ; heartbeat:inst_heartbeat|counter_data[14] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.639 ; +; 0.518 ; heartbeat:inst_heartbeat|counter_data[3] ; heartbeat:inst_heartbeat|counter_data[6] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.639 ; +; 0.518 ; heartbeat:inst_heartbeat|counter_data[17] ; heartbeat:inst_heartbeat|counter_data[20] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.639 ; +; 0.519 ; heartbeat:inst_heartbeat|counter_data[7] ; heartbeat:inst_heartbeat|counter_data[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.640 ; +; 0.519 ; heartbeat:inst_heartbeat|counter_data[15] ; heartbeat:inst_heartbeat|counter_data[18] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.640 ; +; 0.519 ; heartbeat:inst_heartbeat|counter_data[5] ; heartbeat:inst_heartbeat|counter_data[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.640 ; +; 0.519 ; heartbeat:inst_heartbeat|counter_data[13] ; heartbeat:inst_heartbeat|counter_data[16] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.640 ; +; 0.519 ; heartbeat:inst_heartbeat|counter_data[0] ; heartbeat:inst_heartbeat|counter_data[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.640 ; +; 0.520 ; heartbeat:inst_heartbeat|counter_data[9] ; heartbeat:inst_heartbeat|counter_data[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.035 ; 0.639 ; +; 0.520 ; heartbeat:inst_heartbeat|counter_data[1] ; heartbeat:inst_heartbeat|counter_data[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.641 ; +; 0.521 ; heartbeat:inst_heartbeat|counter_data[11] ; heartbeat:inst_heartbeat|counter_data[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.642 ; +; 0.521 ; heartbeat:inst_heartbeat|counter_data[3] ; heartbeat:inst_heartbeat|counter_data[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.642 ; +; 0.521 ; heartbeat:inst_heartbeat|counter_data[17] ; heartbeat:inst_heartbeat|counter_data[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.642 ; +; 0.522 ; heartbeat:inst_heartbeat|counter_data[15] ; heartbeat:inst_heartbeat|counter_data[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.643 ; +; 0.522 ; heartbeat:inst_heartbeat|counter_data[5] ; heartbeat:inst_heartbeat|counter_data[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.643 ; +; 0.522 ; heartbeat:inst_heartbeat|counter_data[13] ; heartbeat:inst_heartbeat|counter_data[17] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.643 ; +; 0.522 ; heartbeat:inst_heartbeat|counter_data[0] ; heartbeat:inst_heartbeat|counter_data[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.643 ; +; 0.523 ; heartbeat:inst_heartbeat|counter_data[9] ; heartbeat:inst_heartbeat|counter_data[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.035 ; 0.642 ; +; 0.524 ; heartbeat:inst_heartbeat|counter_data[7] ; heartbeat:inst_heartbeat|counter_data[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.035 ; 0.643 ; +; 0.571 ; heartbeat:inst_heartbeat|counter_data[10] ; heartbeat:inst_heartbeat|counter_data[14] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.035 ; 0.690 ; +; 0.571 ; heartbeat:inst_heartbeat|counter_data[2] ; heartbeat:inst_heartbeat|counter_data[6] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.692 ; +; 0.571 ; heartbeat:inst_heartbeat|counter_data[16] ; heartbeat:inst_heartbeat|counter_data[20] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.692 ; +; 0.571 ; heartbeat:inst_heartbeat|counter_data[6] ; heartbeat:inst_heartbeat|counter_data[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.692 ; +; 0.571 ; heartbeat:inst_heartbeat|counter_data[14] ; heartbeat:inst_heartbeat|counter_data[18] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.692 ; +; 0.571 ; heartbeat:inst_heartbeat|counter_data[12] ; heartbeat:inst_heartbeat|counter_data[16] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.692 ; +; 0.572 ; heartbeat:inst_heartbeat|counter_data[4] ; heartbeat:inst_heartbeat|counter_data[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.037 ; 0.693 ; ++-------+-------------------------------------------+-------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Recovery: 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[0]' ; ++-------+-------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+-------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ +; 3.217 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[17] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.043 ; 1.727 ; +; 3.217 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[24] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.046 ; 1.724 ; +; 3.217 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.046 ; 1.724 ; +; 3.217 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.045 ; 1.725 ; +; 3.217 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[27] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.045 ; 1.725 ; +; 3.217 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.043 ; 1.727 ; +; 3.217 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.043 ; 1.727 ; +; 3.217 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.046 ; 1.724 ; +; 3.217 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[20] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.046 ; 1.724 ; +; 3.217 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.043 ; 1.727 ; +; 3.217 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.046 ; 1.724 ; +; 3.217 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[16] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.046 ; 1.724 ; +; 3.217 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[23] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.045 ; 1.725 ; +; 3.217 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.043 ; 1.727 ; +; 3.217 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[29] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.043 ; 1.727 ; +; 3.217 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[28] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.046 ; 1.724 ; +; 3.217 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.046 ; 1.724 ; +; 3.217 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.045 ; 1.725 ; +; 3.217 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.045 ; 1.725 ; +; 3.217 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.045 ; 1.725 ; +; 3.217 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[25] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.043 ; 1.727 ; +; 3.217 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.043 ; 1.727 ; +; 3.217 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.045 ; 1.725 ; +; 3.217 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[31] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.045 ; 1.725 ; +; 3.218 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[14] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.036 ; 1.733 ; +; 3.218 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[6] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.036 ; 1.733 ; +; 3.218 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[22] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.036 ; 1.733 ; +; 3.218 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[26] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.036 ; 1.733 ; +; 3.218 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.036 ; 1.733 ; +; 3.218 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[18] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.036 ; 1.733 ; +; 3.218 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.036 ; 1.733 ; +; 3.218 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[30] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.036 ; 1.733 ; +; 7.931 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.111 ; 1.895 ; +; 7.932 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.110 ; 1.895 ; +; 7.932 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.113 ; 1.892 ; +; 7.932 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.111 ; 1.894 ; +; 7.933 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.109 ; 1.895 ; +; 7.933 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.109 ; 1.895 ; +; 7.933 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.109 ; 1.895 ; +; 7.933 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[14] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.109 ; 1.895 ; +; 7.933 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.109 ; 1.895 ; +; 7.966 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.072 ; 1.902 ; +; 7.966 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.072 ; 1.902 ; +; 7.968 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.126 ; 1.844 ; +; 7.969 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.072 ; 1.899 ; +; 7.969 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.074 ; 1.897 ; +; 7.969 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.072 ; 1.899 ; +; 7.969 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.080 ; 1.891 ; +; 7.972 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.067 ; 1.901 ; +; 7.972 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.064 ; 1.904 ; +; 7.972 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[6] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.064 ; 1.904 ; +; 7.972 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.067 ; 1.901 ; +; 7.974 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.121 ; 1.843 ; +; 7.974 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.121 ; 1.843 ; +; 7.974 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.118 ; 1.846 ; +; 7.974 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[6] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.118 ; 1.846 ; +; 7.976 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.065 ; 1.898 ; +; 7.976 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.076 ; 1.888 ; +; 7.977 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.064 ; 1.898 ; +; 7.977 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.064 ; 1.898 ; +; 7.977 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.064 ; 1.898 ; +; 7.977 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.065 ; 1.897 ; +; 7.977 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[6] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.064 ; 1.898 ; +; 7.977 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.067 ; 1.895 ; +; 7.977 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.065 ; 1.897 ; +; 7.977 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.064 ; 1.898 ; +; 7.977 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.067 ; 1.895 ; +; 7.977 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_dqm[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.067 ; 1.895 ; +; 7.977 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_dqm[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.067 ; 1.895 ; +; 7.977 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_bank[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.064 ; 1.898 ; +; 7.978 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.062 ; 1.899 ; +; 7.978 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.063 ; 1.898 ; +; 7.978 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.063 ; 1.898 ; +; 7.978 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.063 ; 1.898 ; +; 7.978 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.063 ; 1.898 ; +; 7.978 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[14] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.063 ; 1.898 ; +; 7.978 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_bank[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.065 ; 1.896 ; +; 7.987 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.066 ; 1.887 ; +; 7.987 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.066 ; 1.887 ; +; 7.989 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.120 ; 1.829 ; +; 7.989 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.120 ; 1.829 ; +; 8.065 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_7 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.064 ; 1.799 ; +; 8.066 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_2 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.064 ; 1.798 ; +; 8.066 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_8 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.063 ; 1.799 ; +; 8.066 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_12 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.066 ; 1.796 ; +; 8.067 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_3 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.080 ; 1.781 ; +; 8.067 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_9 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.062 ; 1.799 ; +; 8.067 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_10 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.062 ; 1.799 ; +; 8.067 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_11 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.062 ; 1.799 ; +; 8.067 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_13 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.062 ; 1.799 ; +; 8.067 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_14 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.062 ; 1.799 ; +; 8.073 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_15 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.075 ; 1.780 ; +; 8.073 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_4 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.075 ; 1.780 ; +; 8.073 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_5 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.072 ; 1.783 ; +; 8.073 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_6 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.072 ; 1.783 ; +; 8.088 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.074 ; 1.766 ; +; 8.088 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_1 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.074 ; 1.766 ; +; 8.088 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_cmd[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.065 ; 1.786 ; +; 8.089 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_cmd[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.068 ; 1.783 ; +; 8.089 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_cmd[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.068 ; 1.783 ; ++-------+-------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Removal: 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[0]' ; ++-------+-------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+-------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ +; 1.268 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_uart_0:uart_0|system_uart_0_rx:the_system_uart_0_rx|altera_std_synchronizer:the_altera_std_synchronizer|dreg[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.231 ; 1.583 ; +; 1.268 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_uart_0:uart_0|system_uart_0_rx:the_system_uart_0_rx|delayed_unxsync_rxdxx1 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.231 ; 1.583 ; +; 1.268 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_uart_0:uart_0|system_uart_0_rx:the_system_uart_0_rx|do_start_rx ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.231 ; 1.583 ; +; 1.268 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_uart_0:uart_0|system_uart_0_rx:the_system_uart_0_rx|baud_rate_counter[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.231 ; 1.583 ; +; 1.268 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_uart_0:uart_0|system_uart_0_rx:the_system_uart_0_rx|baud_clk_en ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.231 ; 1.583 ; +; 1.446 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|byteen_reg[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.029 ; 1.559 ; +; 1.446 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|byteen_reg[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.029 ; 1.559 ; +; 1.446 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|address_reg[22] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.029 ; 1.559 ; +; 1.446 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|address_reg[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.029 ; 1.559 ; +; 1.446 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|data_reg[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.029 ; 1.559 ; +; 1.446 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|data_reg[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.029 ; 1.559 ; +; 1.446 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|data_reg[14] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.029 ; 1.559 ; +; 1.446 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|data_reg[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.029 ; 1.559 ; +; 1.447 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entries[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.029 ; 1.560 ; +; 1.447 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|wr_address ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.030 ; 1.561 ; +; 1.447 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][65] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.029 ; 1.560 ; +; 1.447 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|d_byteenable[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.030 ; 1.561 ; +; 1.447 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|d_byteenable[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.030 ; 1.561 ; +; 1.447 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|use_reg ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.029 ; 1.560 ; +; 1.447 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|count[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.029 ; 1.560 ; +; 1.447 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|endofpacket_reg ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.029 ; 1.560 ; +; 1.447 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.034 ; 1.565 ; +; 1.447 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_traffic_limiter:limiter|last_dest_id[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.034 ; 1.565 ; +; 1.447 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|ic_fill_ap_offset[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.034 ; 1.565 ; +; 1.447 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|ic_fill_ap_offset[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.034 ; 1.565 ; +; 1.447 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|ic_fill_ap_offset[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.034 ; 1.565 ; +; 1.447 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.034 ; 1.565 ; +; 1.447 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.034 ; 1.565 ; +; 1.447 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|ic_fill_line[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.034 ; 1.565 ; +; 1.447 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|ic_fill_line[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.034 ; 1.565 ; +; 1.447 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|ic_fill_ap_cnt[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.034 ; 1.565 ; +; 1.447 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|ic_fill_ap_cnt[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.034 ; 1.565 ; +; 1.447 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|ic_fill_ap_cnt[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.034 ; 1.565 ; +; 1.447 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|ic_fill_ap_cnt[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.034 ; 1.565 ; +; 1.447 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|i_read ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.034 ; 1.565 ; +; 1.447 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_slave_translator:cpu_jtag_debug_module_translator|read_latency_shift_reg[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.031 ; 1.562 ; +; 1.447 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.031 ; 1.562 ; +; 1.447 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][83] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.031 ; 1.562 ; +; 1.447 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][83] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.031 ; 1.562 ; +; 1.447 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entries[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.029 ; 1.560 ; +; 1.447 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|address_reg[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.034 ; 1.565 ; +; 1.447 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|address_reg[16] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.034 ; 1.565 ; +; 1.447 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|address_reg[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.034 ; 1.565 ; +; 1.447 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|address_reg[23] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.034 ; 1.565 ; +; 1.447 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|address_reg[14] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.034 ; 1.565 ; +; 1.447 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|address_reg[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.034 ; 1.565 ; +; 1.447 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|address_reg[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.034 ; 1.565 ; +; 1.447 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|address_reg[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.034 ; 1.565 ; +; 1.447 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|address_reg[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.034 ; 1.565 ; +; 1.447 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][102] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.031 ; 1.562 ; +; 1.447 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][102] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.031 ; 1.562 ; +; 1.447 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_traffic_limiter:limiter|pending_response_count[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.034 ; 1.565 ; +; 1.447 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_traffic_limiter:limiter|pending_response_count[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.034 ; 1.565 ; +; 1.447 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_traffic_limiter:limiter|pending_response_count[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.034 ; 1.565 ; +; 1.447 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_traffic_limiter:limiter|pending_response_count[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.034 ; 1.565 ; +; 1.447 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_traffic_limiter:limiter|has_pending_responses ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.034 ; 1.565 ; +; 1.447 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux_001|packet_in_progress ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.030 ; 1.561 ; +; 1.447 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux_001|saved_grant[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.030 ; 1.561 ; +; 1.447 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|address_reg[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.029 ; 1.560 ; +; 1.447 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.029 ; 1.560 ; +; 1.447 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][54] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.029 ; 1.560 ; +; 1.447 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.031 ; 1.562 ; +; 1.447 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|address_reg[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.034 ; 1.565 ; +; 1.447 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|address_reg[6] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.034 ; 1.565 ; +; 1.447 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|address_reg[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.034 ; 1.565 ; +; 1.447 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|address_reg[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.034 ; 1.565 ; +; 1.450 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|D_iw[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.048 ; 1.582 ; +; 1.450 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|D_ctrl_implicit_dst_eretaddr ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.048 ; 1.582 ; +; 1.450 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|E_iw[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.048 ; 1.582 ; +; 1.450 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|E_ctrl_logic ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.048 ; 1.582 ; +; 1.450 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|E_ctrl_cmp ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.048 ; 1.582 ; +; 1.450 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|E_ctrl_break ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.048 ; 1.582 ; +; 1.450 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|E_ctrl_crst ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.048 ; 1.582 ; +; 1.450 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|M_ctrl_mem ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.048 ; 1.582 ; +; 1.450 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|A_mem_baddr[6] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.047 ; 1.581 ; +; 1.450 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|W_wr_data[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.048 ; 1.582 ; +; 1.450 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|E_src1[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.048 ; 1.582 ; +; 1.450 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|M_mem_byte_en[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.048 ; 1.582 ; +; 1.450 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|A_mem_byte_en[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.048 ; 1.582 ; +; 1.450 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|A_ctrl_ld16 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.048 ; 1.582 ; +; 1.450 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|A_mem_baddr[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.048 ; 1.582 ; +; 1.450 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|M_mem_byte_en[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.048 ; 1.582 ; +; 1.450 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|A_mem_byte_en[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.048 ; 1.582 ; +; 1.450 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|M_st_data[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.048 ; 1.582 ; +; 1.450 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|M_st_data[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.048 ; 1.582 ; +; 1.450 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|A_dc_actual_tag[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.047 ; 1.581 ; +; 1.450 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|A_dc_wb_tag[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.047 ; 1.581 ; +; 1.450 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|M_st_data[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.048 ; 1.582 ; +; 1.450 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|E_src2[23] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.048 ; 1.582 ; +; 1.450 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|M_alu_result[27] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.048 ; 1.582 ; +; 1.450 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|A_inst_result[27] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.048 ; 1.582 ; +; 1.450 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|W_wr_data[27] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.048 ; 1.582 ; +; 1.450 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|E_src2[27] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.048 ; 1.582 ; +; 1.450 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|E_src1[27] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.048 ; 1.582 ; +; 1.450 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|W_wr_data[26] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.048 ; 1.582 ; +; 1.450 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|M_alu_result[26] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.048 ; 1.582 ; +; 1.450 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|E_src1[26] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.048 ; 1.582 ; +; 1.450 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|M_alu_result[23] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.048 ; 1.582 ; +; 1.450 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|E_src1[23] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.048 ; 1.582 ; +; 1.450 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|M_st_data[14] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.048 ; 1.582 ; ++-------+-------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Minimum Pulse Width: 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[0]' ; ++-------+--------------+----------------+-----------------+----------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; ++-------+--------------+----------------+-----------------+----------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; 4.749 ; 4.979 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_bht_module:system_cpu_bht|altsyncram:the_altsyncram|altsyncram_fhg1:auto_generated|ram_block1a0~porta_address_reg0 ; +; 4.749 ; 4.979 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_bht_module:system_cpu_bht|altsyncram:the_altsyncram|altsyncram_fhg1:auto_generated|ram_block1a0~porta_we_reg ; +; 4.749 ; 4.979 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_data_module:system_cpu_dc_data|altsyncram:the_altsyncram|altsyncram_2jf1:auto_generated|ram_block1a0~porta_address_reg0 ; +; 4.749 ; 4.979 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_data_module:system_cpu_dc_data|altsyncram:the_altsyncram|altsyncram_2jf1:auto_generated|ram_block1a0~porta_we_reg ; +; 4.749 ; 4.979 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_data_module:system_cpu_dc_data|altsyncram:the_altsyncram|altsyncram_2jf1:auto_generated|ram_block1a16~porta_address_reg0 ; +; 4.749 ; 4.979 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_data_module:system_cpu_dc_data|altsyncram:the_altsyncram|altsyncram_2jf1:auto_generated|ram_block1a16~porta_we_reg ; +; 4.749 ; 4.979 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_data_module:system_cpu_dc_data|altsyncram:the_altsyncram|altsyncram_2jf1:auto_generated|ram_block1a24~porta_address_reg0 ; +; 4.749 ; 4.979 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_data_module:system_cpu_dc_data|altsyncram:the_altsyncram|altsyncram_2jf1:auto_generated|ram_block1a24~porta_we_reg ; +; 4.749 ; 4.979 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a18~porta_address_reg0 ; +; 4.749 ; 4.979 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a18~porta_we_reg ; +; 4.749 ; 4.979 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a22~porta_address_reg0 ; +; 4.749 ; 4.979 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a22~porta_we_reg ; +; 4.749 ; 4.979 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a27~porta_address_reg0 ; +; 4.749 ; 4.979 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a27~porta_we_reg ; +; 4.749 ; 4.979 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a4~porta_address_reg0 ; +; 4.749 ; 4.979 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a4~porta_we_reg ; +; 4.749 ; 4.979 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a6~porta_address_reg0 ; +; 4.749 ; 4.979 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a6~porta_we_reg ; +; 4.749 ; 4.979 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a9~porta_address_reg0 ; +; 4.749 ; 4.979 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a9~porta_we_reg ; +; 4.749 ; 4.979 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_register_bank_a_module:system_cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_fvf1:auto_generated|ram_block1a0~porta_address_reg0 ; +; 4.749 ; 4.979 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_register_bank_a_module:system_cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_fvf1:auto_generated|ram_block1a0~porta_we_reg ; +; 4.749 ; 4.979 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_register_bank_b_module:system_cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_gvf1:auto_generated|ram_block1a0~porta_address_reg0 ; +; 4.749 ; 4.979 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_register_bank_b_module:system_cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_gvf1:auto_generated|ram_block1a0~porta_we_reg ; +; 4.750 ; 4.980 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|D_bht_data[0] ; +; 4.750 ; 4.980 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|D_bht_data[1] ; +; 4.750 ; 4.980 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_bht_module:system_cpu_bht|altsyncram:the_altsyncram|altsyncram_fhg1:auto_generated|ram_block1a0~portb_address_reg0 ; +; 4.750 ; 4.980 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_bht_module:system_cpu_bht|altsyncram:the_altsyncram|altsyncram_fhg1:auto_generated|ram_block1a0~portb_re_reg ; +; 4.750 ; 4.980 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_data_module:system_cpu_dc_data|altsyncram:the_altsyncram|altsyncram_2jf1:auto_generated|ram_block1a8~porta_address_reg0 ; +; 4.750 ; 4.980 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_data_module:system_cpu_dc_data|altsyncram:the_altsyncram|altsyncram_2jf1:auto_generated|ram_block1a8~porta_we_reg ; +; 4.750 ; 4.980 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_tag_module:system_cpu_dc_tag|altsyncram:the_altsyncram|altsyncram_d9g1:auto_generated|ram_block1a0~porta_address_reg0 ; +; 4.750 ; 4.980 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_tag_module:system_cpu_dc_tag|altsyncram:the_altsyncram|altsyncram_d9g1:auto_generated|ram_block1a0~porta_we_reg ; +; 4.750 ; 4.980 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_victim_module:system_cpu_dc_victim|altsyncram:the_altsyncram|altsyncram_r3d1:auto_generated|ram_block1a0~porta_address_reg0 ; +; 4.750 ; 4.980 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_victim_module:system_cpu_dc_victim|altsyncram:the_altsyncram|altsyncram_r3d1:auto_generated|ram_block1a0~porta_we_reg ; +; 4.750 ; 4.980 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a0~porta_address_reg0 ; +; 4.750 ; 4.980 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a0~porta_we_reg ; +; 4.750 ; 4.980 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a11~porta_address_reg0 ; +; 4.750 ; 4.980 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a11~porta_we_reg ; +; 4.750 ; 4.980 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a0~porta_address_reg0 ; +; 4.750 ; 4.980 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a0~porta_we_reg ; +; 4.750 ; 4.980 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_register_bank_a_module:system_cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_fvf1:auto_generated|ram_block1a0~portb_address_reg0 ; +; 4.750 ; 4.980 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_register_bank_b_module:system_cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_gvf1:auto_generated|ram_block1a0~portb_address_reg0 ; +; 4.751 ; 4.981 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_bht_module:system_cpu_bht|altsyncram:the_altsyncram|altsyncram_fhg1:auto_generated|ram_block1a0~porta_datain_reg0 ; +; 4.751 ; 4.981 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_data_module:system_cpu_dc_data|altsyncram:the_altsyncram|altsyncram_2jf1:auto_generated|ram_block1a0~porta_bytena_reg0 ; +; 4.751 ; 4.981 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_data_module:system_cpu_dc_data|altsyncram:the_altsyncram|altsyncram_2jf1:auto_generated|ram_block1a0~porta_datain_reg0 ; +; 4.751 ; 4.981 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_data_module:system_cpu_dc_data|altsyncram:the_altsyncram|altsyncram_2jf1:auto_generated|ram_block1a16~porta_bytena_reg0 ; +; 4.751 ; 4.981 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_data_module:system_cpu_dc_data|altsyncram:the_altsyncram|altsyncram_2jf1:auto_generated|ram_block1a16~porta_datain_reg0 ; +; 4.751 ; 4.981 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_data_module:system_cpu_dc_data|altsyncram:the_altsyncram|altsyncram_2jf1:auto_generated|ram_block1a24~porta_bytena_reg0 ; +; 4.751 ; 4.981 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_data_module:system_cpu_dc_data|altsyncram:the_altsyncram|altsyncram_2jf1:auto_generated|ram_block1a24~porta_datain_reg0 ; +; 4.751 ; 4.981 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_tag_module:system_cpu_dc_tag|altsyncram:the_altsyncram|altsyncram_d9g1:auto_generated|ram_block1a0~portb_address_reg0 ; +; 4.751 ; 4.981 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_victim_module:system_cpu_dc_victim|altsyncram:the_altsyncram|altsyncram_r3d1:auto_generated|ram_block1a0~portb_address_reg0 ; +; 4.751 ; 4.981 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_victim_module:system_cpu_dc_victim|altsyncram:the_altsyncram|altsyncram_r3d1:auto_generated|ram_block1a0~portb_re_reg ; +; 4.751 ; 4.981 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a18~porta_datain_reg0 ; +; 4.751 ; 4.981 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a22~porta_datain_reg0 ; +; 4.751 ; 4.981 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a27~porta_datain_reg0 ; +; 4.751 ; 4.981 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a4~porta_datain_reg0 ; +; 4.751 ; 4.981 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a6~porta_datain_reg0 ; +; 4.751 ; 4.981 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a9~porta_datain_reg0 ; +; 4.751 ; 4.981 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a0~portb_address_reg0 ; +; 4.751 ; 4.981 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a0~portb_we_reg ; +; 4.751 ; 4.981 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_register_bank_a_module:system_cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_fvf1:auto_generated|ram_block1a0~porta_datain_reg0 ; +; 4.751 ; 4.981 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_register_bank_b_module:system_cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_gvf1:auto_generated|ram_block1a0~porta_datain_reg0 ; +; 4.752 ; 4.982 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_data_module:system_cpu_dc_data|altsyncram:the_altsyncram|altsyncram_2jf1:auto_generated|ram_block1a16~portb_address_reg0 ; +; 4.752 ; 4.982 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_data_module:system_cpu_dc_data|altsyncram:the_altsyncram|altsyncram_2jf1:auto_generated|ram_block1a8~porta_bytena_reg0 ; +; 4.752 ; 4.982 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_data_module:system_cpu_dc_data|altsyncram:the_altsyncram|altsyncram_2jf1:auto_generated|ram_block1a8~porta_datain_reg0 ; +; 4.752 ; 4.982 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_tag_module:system_cpu_dc_tag|altsyncram:the_altsyncram|altsyncram_d9g1:auto_generated|ram_block1a0~porta_datain_reg0 ; +; 4.752 ; 4.982 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_victim_module:system_cpu_dc_victim|altsyncram:the_altsyncram|altsyncram_r3d1:auto_generated|ram_block1a0~porta_datain_reg0 ; +; 4.752 ; 4.982 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a0~porta_datain_reg0 ; +; 4.752 ; 4.982 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a11~porta_datain_reg0 ; +; 4.752 ; 4.982 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a18~portb_address_reg0 ; +; 4.752 ; 4.982 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a18~portb_re_reg ; +; 4.752 ; 4.982 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a27~portb_address_reg0 ; +; 4.752 ; 4.982 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a27~portb_re_reg ; +; 4.752 ; 4.982 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a9~portb_address_reg0 ; +; 4.752 ; 4.982 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a9~portb_re_reg ; +; 4.752 ; 4.982 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_address_reg0 ; +; 4.752 ; 4.982 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_we_reg ; +; 4.752 ; 4.982 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a0~porta_bytena_reg0 ; +; 4.752 ; 4.982 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a0~porta_datain_reg0 ; +; 4.752 ; 4.982 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~porta_address_reg0 ; +; 4.752 ; 4.982 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~porta_we_reg ; +; 4.752 ; 4.982 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_address_reg0 ; +; 4.752 ; 4.982 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_we_reg ; +; 4.752 ; 4.982 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_address_reg0 ; +; 4.752 ; 4.982 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_rs232_motor:rs232_motor|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_we_reg ; +; 4.753 ; 4.983 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_data_module:system_cpu_dc_data|altsyncram:the_altsyncram|altsyncram_2jf1:auto_generated|ram_block1a0~portb_address_reg0 ; +; 4.753 ; 4.983 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_data_module:system_cpu_dc_data|altsyncram:the_altsyncram|altsyncram_2jf1:auto_generated|ram_block1a24~portb_address_reg0 ; +; 4.753 ; 4.983 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_data_module:system_cpu_dc_data|altsyncram:the_altsyncram|altsyncram_2jf1:auto_generated|ram_block1a8~portb_address_reg0 ; +; 4.753 ; 4.983 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a0~portb_address_reg0 ; +; 4.753 ; 4.983 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a0~portb_re_reg ; +; 4.753 ; 4.983 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a22~portb_address_reg0 ; +; 4.753 ; 4.983 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a22~portb_re_reg ; +; 4.753 ; 4.983 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a4~portb_address_reg0 ; +; 4.753 ; 4.983 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a4~portb_re_reg ; +; 4.753 ; 4.983 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a6~portb_address_reg0 ; +; 4.753 ; 4.983 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a6~portb_re_reg ; +; 4.753 ; 4.983 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~portb_address_reg0 ; +; 4.753 ; 4.983 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~portb_re_reg ; +; 4.753 ; 4.983 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a0~portb_datain_reg0 ; +; 4.753 ; 4.983 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_address_reg0 ; ++-------+--------------+----------------+-----------------+----------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50' ; ++--------+--------------+----------------+------------------+----------+------------+--------------------------------------------------------------------+ +; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; ++--------+--------------+----------------+------------------+----------+------------+--------------------------------------------------------------------+ +; 9.587 ; 9.587 ; 0.000 ; Low Pulse Width ; CLOCK_50 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; 9.587 ; 9.587 ; 0.000 ; Low Pulse Width ; CLOCK_50 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[1] ; +; 9.587 ; 9.587 ; 0.000 ; Low Pulse Width ; CLOCK_50 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; +; 9.587 ; 9.587 ; 0.000 ; Low Pulse Width ; CLOCK_50 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|observablevcoout ; +; 9.621 ; 9.621 ; 0.000 ; Low Pulse Width ; CLOCK_50 ; Rise ; CLOCK_50~input|o ; +; 9.631 ; 9.631 ; 0.000 ; Low Pulse Width ; CLOCK_50 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|inclk[0] ; +; 10.000 ; 10.000 ; 0.000 ; High Pulse Width ; CLOCK_50 ; Rise ; CLOCK_50~input|i ; +; 10.000 ; 10.000 ; 0.000 ; Low Pulse Width ; CLOCK_50 ; Rise ; CLOCK_50~input|i ; +; 10.369 ; 10.369 ; 0.000 ; High Pulse Width ; CLOCK_50 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|inclk[0] ; +; 10.379 ; 10.379 ; 0.000 ; High Pulse Width ; CLOCK_50 ; Rise ; CLOCK_50~input|o ; +; 10.412 ; 10.412 ; 0.000 ; High Pulse Width ; CLOCK_50 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; 10.412 ; 10.412 ; 0.000 ; High Pulse Width ; CLOCK_50 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[1] ; +; 10.412 ; 10.412 ; 0.000 ; High Pulse Width ; CLOCK_50 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; +; 10.412 ; 10.412 ; 0.000 ; High Pulse Width ; CLOCK_50 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|observablevcoout ; +; 16.000 ; 20.000 ; 4.000 ; Port Rate ; CLOCK_50 ; Rise ; CLOCK_50 ; ++--------+--------------+----------------+------------------+----------+------------+--------------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Minimum Pulse Width: 'altera_reserved_tck' ; ++--------+--------------+----------------+------------------+---------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; ++--------+--------------+----------------+------------------+---------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; 49.482 ; 49.698 ; 0.216 ; High Pulse Width ; altera_reserved_tck ; Fall ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; +; 49.483 ; 49.699 ; 0.216 ; High Pulse Width ; altera_reserved_tck ; Fall ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|jupdate ; +; 49.483 ; 49.699 ; 0.216 ; High Pulse Width ; altera_reserved_tck ; Fall ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|tdo~reg0 ; +; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[0] ; +; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[1] ; +; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[2] ; +; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[3] ; +; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[0] ; +; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1] ; +; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2] ; +; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[3] ; +; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[4] ; +; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[5] ; +; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[6] ; +; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[7] ; +; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[8] ; +; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[9] ; +; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[0] ; +; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[1] ; +; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[2] ; +; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[3] ; +; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[4] ; +; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[0] ; +; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[1] ; +; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[2] ; +; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[3] ; +; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[0] ; +; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[1] ; +; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[2] ; +; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[3] ; +; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[4] ; +; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_dr_scan_reg ; +; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; +; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[10] ; +; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[11] ; +; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[12] ; +; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[13] ; +; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[14] ; +; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[15] ; +; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[16] ; +; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[17] ; +; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[18] ; +; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[19] ; +; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[1] ; +; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[20] ; +; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[21] ; +; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[22] ; +; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[23] ; +; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[2] ; +; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[31] ; +; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[35] ; +; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[3] ; +; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[4] ; +; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[5] ; +; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[6] ; +; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[7] ; +; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[8] ; +; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[9] ; +; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|read ; +; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|read_req ; +; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|tck_t_dav ; +; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|wdata[0] ; +; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|write_stalled ; +; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|write_valid ; +; 49.527 ; 49.711 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; +; 49.527 ; 49.711 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[0] ; +; 49.527 ; 49.711 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[1] ; +; 49.527 ; 49.711 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[2] ; +; 49.527 ; 49.711 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[3] ; +; 49.527 ; 49.711 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[0] ; +; 49.527 ; 49.711 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[1] ; +; 49.527 ; 49.711 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[2] ; +; 49.527 ; 49.711 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[3] ; +; 49.527 ; 49.711 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0] ; +; 49.527 ; 49.711 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1] ; +; 49.527 ; 49.711 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2] ; +; 49.527 ; 49.711 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[0] ; +; 49.527 ; 49.711 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[1] ; +; 49.527 ; 49.711 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[2] ; +; 49.527 ; 49.711 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[3] ; +; 49.527 ; 49.711 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0] ; +; 49.527 ; 49.711 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][1] ; +; 49.527 ; 49.711 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2] ; +; 49.527 ; 49.711 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][3] ; +; 49.527 ; 49.711 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4] ; +; 49.527 ; 49.711 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0] ; +; 49.527 ; 49.711 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1] ; +; 49.527 ; 49.711 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2] ; +; 49.527 ; 49.711 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3] ; +; 49.527 ; 49.711 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4] ; +; 49.527 ; 49.711 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0] ; +; 49.527 ; 49.711 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1] ; +; 49.527 ; 49.711 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2] ; +; 49.527 ; 49.711 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[3] ; +; 49.527 ; 49.711 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4] ; +; 49.527 ; 49.711 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; +; 49.527 ; 49.711 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6] ; +; 49.527 ; 49.711 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; +; 49.527 ; 49.711 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0 ; +; 49.527 ; 49.711 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|reset_ena_reg ; ++--------+--------------+----------------+------------------+---------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Minimum Pulse Width: 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[2]' ; ++--------+--------------+----------------+------------------+----------------------------------------------------------+------------+--------------------------------------------------------------------------------+ +; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; ++--------+--------------+----------------+------------------+----------------------------------------------------------+------------+--------------------------------------------------------------------------------+ +; 49.782 ; 49.998 ; 0.216 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[0] ; +; 49.782 ; 49.998 ; 0.216 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[10] ; +; 49.782 ; 49.998 ; 0.216 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[1] ; +; 49.782 ; 49.998 ; 0.216 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[2] ; +; 49.782 ; 49.998 ; 0.216 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[3] ; +; 49.782 ; 49.998 ; 0.216 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[4] ; +; 49.782 ; 49.998 ; 0.216 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[5] ; +; 49.782 ; 49.998 ; 0.216 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[6] ; +; 49.782 ; 49.998 ; 0.216 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[7] ; +; 49.782 ; 49.998 ; 0.216 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[8] ; +; 49.782 ; 49.998 ; 0.216 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[9] ; +; 49.783 ; 49.999 ; 0.216 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[11] ; +; 49.783 ; 49.999 ; 0.216 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[12] ; +; 49.783 ; 49.999 ; 0.216 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[13] ; +; 49.783 ; 49.999 ; 0.216 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[14] ; +; 49.783 ; 49.999 ; 0.216 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[15] ; +; 49.783 ; 49.999 ; 0.216 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[16] ; +; 49.783 ; 49.999 ; 0.216 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[17] ; +; 49.783 ; 49.999 ; 0.216 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[18] ; +; 49.783 ; 49.999 ; 0.216 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[19] ; +; 49.783 ; 49.999 ; 0.216 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[20] ; +; 49.783 ; 49.999 ; 0.216 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[21] ; +; 49.816 ; 50.000 ; 0.184 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[0] ; +; 49.816 ; 50.000 ; 0.184 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[10] ; +; 49.816 ; 50.000 ; 0.184 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[11] ; +; 49.816 ; 50.000 ; 0.184 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[12] ; +; 49.816 ; 50.000 ; 0.184 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[13] ; +; 49.816 ; 50.000 ; 0.184 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[14] ; +; 49.816 ; 50.000 ; 0.184 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[15] ; +; 49.816 ; 50.000 ; 0.184 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[16] ; +; 49.816 ; 50.000 ; 0.184 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[17] ; +; 49.816 ; 50.000 ; 0.184 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[18] ; +; 49.816 ; 50.000 ; 0.184 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[19] ; +; 49.816 ; 50.000 ; 0.184 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[1] ; +; 49.816 ; 50.000 ; 0.184 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[20] ; +; 49.816 ; 50.000 ; 0.184 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[21] ; +; 49.816 ; 50.000 ; 0.184 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[2] ; +; 49.816 ; 50.000 ; 0.184 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[3] ; +; 49.816 ; 50.000 ; 0.184 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[4] ; +; 49.816 ; 50.000 ; 0.184 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[5] ; +; 49.816 ; 50.000 ; 0.184 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[6] ; +; 49.816 ; 50.000 ; 0.184 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[7] ; +; 49.816 ; 50.000 ; 0.184 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[8] ; +; 49.816 ; 50.000 ; 0.184 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[9] ; +; 49.995 ; 49.995 ; 0.000 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[11]|clk ; +; 49.995 ; 49.995 ; 0.000 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[12]|clk ; +; 49.995 ; 49.995 ; 0.000 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[13]|clk ; +; 49.995 ; 49.995 ; 0.000 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[14]|clk ; +; 49.995 ; 49.995 ; 0.000 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[15]|clk ; +; 49.995 ; 49.995 ; 0.000 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[16]|clk ; +; 49.995 ; 49.995 ; 0.000 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[17]|clk ; +; 49.995 ; 49.995 ; 0.000 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[18]|clk ; +; 49.995 ; 49.995 ; 0.000 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[19]|clk ; +; 49.995 ; 49.995 ; 0.000 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[20]|clk ; +; 49.995 ; 49.995 ; 0.000 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[21]|clk ; +; 49.995 ; 49.995 ; 0.000 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_pll_sys|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl|inclk[0] ; +; 49.995 ; 49.995 ; 0.000 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_pll_sys|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl|outclk ; +; 49.996 ; 49.996 ; 0.000 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[0]|clk ; +; 49.996 ; 49.996 ; 0.000 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[10]|clk ; +; 49.996 ; 49.996 ; 0.000 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[1]|clk ; +; 49.996 ; 49.996 ; 0.000 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[2]|clk ; +; 49.996 ; 49.996 ; 0.000 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[3]|clk ; +; 49.996 ; 49.996 ; 0.000 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[4]|clk ; +; 49.996 ; 49.996 ; 0.000 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[5]|clk ; +; 49.996 ; 49.996 ; 0.000 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[6]|clk ; +; 49.996 ; 49.996 ; 0.000 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[7]|clk ; +; 49.996 ; 49.996 ; 0.000 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[8]|clk ; +; 49.996 ; 49.996 ; 0.000 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[9]|clk ; +; 50.004 ; 50.004 ; 0.000 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[0]|clk ; +; 50.004 ; 50.004 ; 0.000 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[10]|clk ; +; 50.004 ; 50.004 ; 0.000 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[11]|clk ; +; 50.004 ; 50.004 ; 0.000 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[12]|clk ; +; 50.004 ; 50.004 ; 0.000 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[13]|clk ; +; 50.004 ; 50.004 ; 0.000 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[14]|clk ; +; 50.004 ; 50.004 ; 0.000 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[15]|clk ; +; 50.004 ; 50.004 ; 0.000 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[16]|clk ; +; 50.004 ; 50.004 ; 0.000 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[17]|clk ; +; 50.004 ; 50.004 ; 0.000 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[18]|clk ; +; 50.004 ; 50.004 ; 0.000 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[19]|clk ; +; 50.004 ; 50.004 ; 0.000 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[1]|clk ; +; 50.004 ; 50.004 ; 0.000 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[20]|clk ; +; 50.004 ; 50.004 ; 0.000 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[21]|clk ; +; 50.004 ; 50.004 ; 0.000 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[2]|clk ; +; 50.004 ; 50.004 ; 0.000 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[3]|clk ; +; 50.004 ; 50.004 ; 0.000 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[4]|clk ; +; 50.004 ; 50.004 ; 0.000 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[5]|clk ; +; 50.004 ; 50.004 ; 0.000 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[6]|clk ; +; 50.004 ; 50.004 ; 0.000 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[7]|clk ; +; 50.004 ; 50.004 ; 0.000 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[8]|clk ; +; 50.004 ; 50.004 ; 0.000 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_heartbeat|counter_data[9]|clk ; +; 50.004 ; 50.004 ; 0.000 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_pll_sys|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl|inclk[0] ; +; 50.004 ; 50.004 ; 0.000 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; inst_pll_sys|altpll_component|auto_generated|wire_pll1_clk[2]~clkctrl|outclk ; +; 98.000 ; 100.000 ; 2.000 ; Min Period ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[0] ; +; 98.000 ; 100.000 ; 2.000 ; Min Period ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[10] ; +; 98.000 ; 100.000 ; 2.000 ; Min Period ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[11] ; +; 98.000 ; 100.000 ; 2.000 ; Min Period ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[12] ; +; 98.000 ; 100.000 ; 2.000 ; Min Period ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[13] ; +; 98.000 ; 100.000 ; 2.000 ; Min Period ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[14] ; +; 98.000 ; 100.000 ; 2.000 ; Min Period ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[15] ; +; 98.000 ; 100.000 ; 2.000 ; Min Period ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; Rise ; heartbeat:inst_heartbeat|counter_data[16] ; ++--------+--------------+----------------+------------------+----------------------------------------------------------+------------+--------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------+ +; Setup Times ; ++---------------------+---------------------+-------+-------+------------+----------------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++---------------------+---------------------+-------+-------+------------+----------------------------------------------------------+ +; altera_reserved_tdi ; altera_reserved_tck ; 0.399 ; 0.707 ; Rise ; altera_reserved_tck ; +; altera_reserved_tms ; altera_reserved_tck ; 2.875 ; 3.238 ; Rise ; altera_reserved_tck ; +; DRAM_DQ[*] ; CLOCK_50 ; 0.582 ; 0.961 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 0.582 ; 0.961 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 0.582 ; 0.961 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 0.566 ; 0.943 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 0.578 ; 0.957 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 0.573 ; 0.952 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 0.570 ; 0.949 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 0.570 ; 0.949 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 0.566 ; 0.943 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 0.565 ; 0.942 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 0.564 ; 0.941 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 0.564 ; 0.941 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 0.564 ; 0.941 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 0.568 ; 0.945 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 0.564 ; 0.941 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 0.564 ; 0.941 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[15] ; CLOCK_50 ; 0.573 ; 0.952 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_1[*] ; CLOCK_50 ; 2.966 ; 3.656 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_1[24] ; CLOCK_50 ; 2.966 ; 3.656 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; KEY[*] ; CLOCK_50 ; 2.369 ; 3.007 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; KEY[0] ; CLOCK_50 ; 2.369 ; 3.007 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; KEY[1] ; CLOCK_50 ; 1.048 ; 1.374 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; SW[*] ; CLOCK_50 ; 1.348 ; 1.623 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; SW[0] ; CLOCK_50 ; 1.133 ; 1.454 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; SW[1] ; CLOCK_50 ; 1.348 ; 1.623 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; SW[2] ; CLOCK_50 ; 1.325 ; 1.599 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; SW[3] ; CLOCK_50 ; 1.307 ; 1.603 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ++---------------------+---------------------+-------+-------+------------+----------------------------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------+ +; Hold Times ; ++---------------------+---------------------+--------+--------+------------+----------------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++---------------------+---------------------+--------+--------+------------+----------------------------------------------------------+ +; altera_reserved_tdi ; altera_reserved_tck ; 0.904 ; 0.609 ; Rise ; altera_reserved_tck ; +; altera_reserved_tms ; altera_reserved_tck ; 0.009 ; -0.290 ; Rise ; altera_reserved_tck ; +; DRAM_DQ[*] ; CLOCK_50 ; -0.259 ; -0.636 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; -0.276 ; -0.655 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; -0.276 ; -0.655 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; -0.260 ; -0.637 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; -0.271 ; -0.650 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; -0.266 ; -0.645 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; -0.263 ; -0.642 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; -0.263 ; -0.642 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; -0.261 ; -0.638 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; -0.259 ; -0.636 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; -0.259 ; -0.636 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; -0.259 ; -0.636 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; -0.259 ; -0.636 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; -0.262 ; -0.639 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; -0.259 ; -0.636 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; -0.259 ; -0.636 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[15] ; CLOCK_50 ; -0.266 ; -0.645 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_1[*] ; CLOCK_50 ; -2.447 ; -3.142 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_1[24] ; CLOCK_50 ; -2.447 ; -3.142 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; KEY[*] ; CLOCK_50 ; -0.694 ; -1.016 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; KEY[0] ; CLOCK_50 ; -1.958 ; -2.580 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; KEY[1] ; CLOCK_50 ; -0.694 ; -1.016 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; SW[*] ; CLOCK_50 ; -0.775 ; -1.092 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; SW[0] ; CLOCK_50 ; -0.775 ; -1.092 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; SW[1] ; CLOCK_50 ; -0.982 ; -1.255 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; SW[2] ; CLOCK_50 ; -0.961 ; -1.232 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; SW[3] ; CLOCK_50 ; -0.943 ; -1.235 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ++---------------------+---------------------+--------+--------+------------+----------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------+ +; Clock to Output Times ; ++---------------------+---------------------+-------+-------+------------+----------------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++---------------------+---------------------+-------+-------+------------+----------------------------------------------------------+ +; altera_reserved_tdo ; altera_reserved_tck ; 6.185 ; 6.609 ; Fall ; altera_reserved_tck ; +; DRAM_ADDR[*] ; CLOCK_50 ; 1.813 ; 1.832 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[0] ; CLOCK_50 ; 1.812 ; 1.831 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[1] ; CLOCK_50 ; 1.768 ; 1.771 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[2] ; CLOCK_50 ; 1.768 ; 1.771 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[3] ; CLOCK_50 ; 1.767 ; 1.770 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[4] ; CLOCK_50 ; 1.769 ; 1.772 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[5] ; CLOCK_50 ; 1.767 ; 1.770 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[6] ; CLOCK_50 ; 1.767 ; 1.770 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[7] ; CLOCK_50 ; 1.765 ; 1.768 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[8] ; CLOCK_50 ; 1.757 ; 1.756 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[9] ; CLOCK_50 ; 1.812 ; 1.831 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[10] ; CLOCK_50 ; 1.804 ; 1.823 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[11] ; CLOCK_50 ; 1.813 ; 1.832 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[12] ; CLOCK_50 ; 1.755 ; 1.754 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_BA[*] ; CLOCK_50 ; 1.767 ; 1.770 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_BA[0] ; CLOCK_50 ; 1.766 ; 1.769 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_BA[1] ; CLOCK_50 ; 1.767 ; 1.770 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CAS_N ; CLOCK_50 ; 1.817 ; 1.836 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CS_N ; CLOCK_50 ; 2.699 ; 2.758 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[*] ; CLOCK_50 ; 1.821 ; 1.840 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 1.808 ; 1.827 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 1.808 ; 1.827 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 1.767 ; 1.770 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 1.759 ; 1.758 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 1.818 ; 1.837 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 1.821 ; 1.840 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 1.821 ; 1.840 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 1.766 ; 1.769 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 1.768 ; 1.771 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 1.768 ; 1.771 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 1.768 ; 1.771 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 1.768 ; 1.771 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 1.765 ; 1.768 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 1.768 ; 1.771 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 1.768 ; 1.771 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[15] ; CLOCK_50 ; 1.818 ; 1.837 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQM[*] ; CLOCK_50 ; 1.765 ; 1.768 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQM[0] ; CLOCK_50 ; 1.765 ; 1.768 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQM[1] ; CLOCK_50 ; 1.765 ; 1.768 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_RAS_N ; CLOCK_50 ; 1.817 ; 1.836 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_WE_N ; CLOCK_50 ; 1.816 ; 1.835 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_0[*] ; CLOCK_50 ; 3.321 ; 3.118 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_0[0] ; CLOCK_50 ; 3.321 ; 3.118 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_1[*] ; CLOCK_50 ; 3.658 ; 3.853 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_1[12] ; CLOCK_50 ; 2.827 ; 2.988 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_1[26] ; CLOCK_50 ; 3.658 ; 3.853 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[*] ; CLOCK_50 ; 3.918 ; 4.140 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[0] ; CLOCK_50 ; 3.481 ; 3.694 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[1] ; CLOCK_50 ; 3.172 ; 3.390 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[2] ; CLOCK_50 ; 3.213 ; 3.410 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[3] ; CLOCK_50 ; 3.333 ; 3.544 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[4] ; CLOCK_50 ; 2.626 ; 2.773 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[5] ; CLOCK_50 ; 3.918 ; 4.140 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[6] ; CLOCK_50 ; 2.710 ; 2.845 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CLK ; CLOCK_50 ; 0.078 ; ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[1] ; +; DRAM_CLK ; CLOCK_50 ; ; 0.107 ; Fall ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[1] ; +; LED[*] ; CLOCK_50 ; 2.917 ; 3.016 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; +; LED[7] ; CLOCK_50 ; 2.917 ; 3.016 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; ++---------------------+---------------------+-------+-------+------------+----------------------------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------+ +; Minimum Clock to Output Times ; ++---------------------+---------------------+--------+--------+------------+----------------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++---------------------+---------------------+--------+--------+------------+----------------------------------------------------------+ +; altera_reserved_tdo ; altera_reserved_tck ; 5.012 ; 5.437 ; Fall ; altera_reserved_tck ; +; DRAM_ADDR[*] ; CLOCK_50 ; 1.513 ; 1.513 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[0] ; CLOCK_50 ; 1.571 ; 1.591 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[1] ; CLOCK_50 ; 1.526 ; 1.529 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[2] ; CLOCK_50 ; 1.526 ; 1.529 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[3] ; CLOCK_50 ; 1.526 ; 1.529 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[4] ; CLOCK_50 ; 1.528 ; 1.531 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[5] ; CLOCK_50 ; 1.525 ; 1.528 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[6] ; CLOCK_50 ; 1.526 ; 1.529 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[7] ; CLOCK_50 ; 1.523 ; 1.526 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[8] ; CLOCK_50 ; 1.515 ; 1.515 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[9] ; CLOCK_50 ; 1.571 ; 1.591 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[10] ; CLOCK_50 ; 1.563 ; 1.583 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[11] ; CLOCK_50 ; 1.571 ; 1.591 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[12] ; CLOCK_50 ; 1.513 ; 1.513 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_BA[*] ; CLOCK_50 ; 1.525 ; 1.528 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_BA[0] ; CLOCK_50 ; 1.525 ; 1.528 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_BA[1] ; CLOCK_50 ; 1.526 ; 1.529 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CAS_N ; CLOCK_50 ; 1.575 ; 1.595 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CS_N ; CLOCK_50 ; 2.458 ; 2.517 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[*] ; CLOCK_50 ; 1.517 ; 1.517 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 1.567 ; 1.587 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 1.567 ; 1.587 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 1.525 ; 1.528 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 1.517 ; 1.517 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 1.576 ; 1.596 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 1.579 ; 1.599 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 1.579 ; 1.599 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 1.525 ; 1.528 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 1.526 ; 1.529 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 1.527 ; 1.530 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 1.527 ; 1.530 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 1.527 ; 1.530 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 1.523 ; 1.526 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 1.527 ; 1.530 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 1.527 ; 1.530 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[15] ; CLOCK_50 ; 1.576 ; 1.596 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQM[*] ; CLOCK_50 ; 1.523 ; 1.526 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQM[0] ; CLOCK_50 ; 1.523 ; 1.526 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQM[1] ; CLOCK_50 ; 1.523 ; 1.526 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_RAS_N ; CLOCK_50 ; 1.575 ; 1.595 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_WE_N ; CLOCK_50 ; 1.574 ; 1.594 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_0[*] ; CLOCK_50 ; 2.972 ; 2.777 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_0[0] ; CLOCK_50 ; 2.972 ; 2.777 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_1[*] ; CLOCK_50 ; 2.498 ; 2.652 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_1[12] ; CLOCK_50 ; 2.498 ; 2.652 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_1[26] ; CLOCK_50 ; 3.334 ; 3.524 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[*] ; CLOCK_50 ; 2.309 ; 2.451 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[0] ; CLOCK_50 ; 3.127 ; 3.330 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[1] ; CLOCK_50 ; 2.830 ; 3.039 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[2] ; CLOCK_50 ; 2.869 ; 3.058 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[3] ; CLOCK_50 ; 2.984 ; 3.186 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[4] ; CLOCK_50 ; 2.309 ; 2.451 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[5] ; CLOCK_50 ; 3.584 ; 3.800 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[6] ; CLOCK_50 ; 2.387 ; 2.517 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CLK ; CLOCK_50 ; -0.195 ; ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[1] ; +; DRAM_CLK ; CLOCK_50 ; ; -0.166 ; Fall ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[1] ; +; LED[*] ; CLOCK_50 ; 2.623 ; 2.720 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; +; LED[7] ; CLOCK_50 ; 2.623 ; 2.720 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; ++---------------------+---------------------+--------+--------+------------+----------------------------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------+ +; Output Enable Times ; ++--------------+------------+-------+-------+------------+----------------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++--------------+------------+-------+-------+------------+----------------------------------------------------------+ +; DRAM_DQ[*] ; CLOCK_50 ; 1.639 ; 1.626 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 1.689 ; 1.688 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 1.689 ; 1.688 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 1.644 ; 1.630 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 1.639 ; 1.626 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 1.699 ; 1.698 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 1.702 ; 1.701 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 1.702 ; 1.701 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 1.643 ; 1.629 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 1.645 ; 1.631 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 1.645 ; 1.631 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 1.645 ; 1.631 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 1.645 ; 1.631 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 1.642 ; 1.628 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 1.645 ; 1.631 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 1.645 ; 1.631 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[15] ; CLOCK_50 ; 1.699 ; 1.698 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ++--------------+------------+-------+-------+------------+----------------------------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------+ +; Minimum Output Enable Times ; ++--------------+------------+-------+-------+------------+----------------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++--------------+------------+-------+-------+------------+----------------------------------------------------------+ +; DRAM_DQ[*] ; CLOCK_50 ; 1.398 ; 1.385 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 1.449 ; 1.448 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 1.449 ; 1.448 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 1.403 ; 1.389 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 1.398 ; 1.385 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 1.458 ; 1.457 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 1.461 ; 1.460 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 1.461 ; 1.460 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 1.403 ; 1.389 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 1.404 ; 1.390 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 1.405 ; 1.391 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 1.405 ; 1.391 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 1.405 ; 1.391 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 1.401 ; 1.387 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 1.405 ; 1.391 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 1.405 ; 1.391 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[15] ; CLOCK_50 ; 1.458 ; 1.457 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ++--------------+------------+-------+-------+------------+----------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------+ +; Output Disable Times ; ++--------------+------------+-----------+-----------+------------+----------------------------------------------------------+ +; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ; ++--------------+------------+-----------+-----------+------------+----------------------------------------------------------+ +; DRAM_DQ[*] ; CLOCK_50 ; 1.647 ; 1.661 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 1.720 ; 1.721 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 1.720 ; 1.721 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 1.649 ; 1.663 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 1.658 ; 1.671 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 1.730 ; 1.731 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 1.733 ; 1.734 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 1.733 ; 1.734 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 1.648 ; 1.662 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 1.650 ; 1.664 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 1.650 ; 1.664 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 1.650 ; 1.664 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 1.650 ; 1.664 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 1.647 ; 1.661 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 1.650 ; 1.664 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 1.650 ; 1.664 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[15] ; CLOCK_50 ; 1.730 ; 1.731 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ++--------------+------------+-----------+-----------+------------+----------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------+ +; Minimum Output Disable Times ; ++--------------+------------+-----------+-----------+------------+----------------------------------------------------------+ +; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference ; ++--------------+------------+-----------+-----------+------------+----------------------------------------------------------+ +; DRAM_DQ[*] ; CLOCK_50 ; 1.406 ; 1.420 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 1.479 ; 1.480 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 1.479 ; 1.480 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 1.408 ; 1.422 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 1.416 ; 1.429 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 1.488 ; 1.489 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 1.491 ; 1.492 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 1.491 ; 1.492 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 1.408 ; 1.422 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 1.409 ; 1.423 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 1.410 ; 1.424 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 1.410 ; 1.424 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 1.410 ; 1.424 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 1.406 ; 1.420 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 1.410 ; 1.424 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 1.410 ; 1.424 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[15] ; CLOCK_50 ; 1.488 ; 1.489 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ++--------------+------------+-----------+-----------+------------+----------------------------------------------------------+ + + +---------------- +; MTBF Summary ; +---------------- +Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. + +Number of Synchronizer Chains Found: 5 +Shortest Synchronizer Chain: 2 Registers +Fraction of Chains for which MTBFs Could Not be Calculated: 0.400 +Worst Case Available Settling Time: 18.290 ns + +Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. + - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8 + + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Synchronizer Summary ; ++------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+-------------------------+ +; Source Node ; Synchronization Node ; Typical MTBF (Years) ; Included in Design MTBF ; ++------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+-------------------------+ +; GPIO_0[1] ; system:inst_cpu|system_uart_0:uart_0|system_uart_0_rx:the_system_uart_0_rx|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 ; Greater than 1 Billion ; Yes ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer2|din_s1 ; Greater than 1 Billion ; Yes ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3|din_s1 ; Greater than 1 Billion ; Yes ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_debug:the_system_cpu_nios2_oci_debug|monitor_ready ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|din_s1 ; n/a ; Yes ; +; system:inst_cpu|system_cpu:cpu|hbreak_enabled ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 ; n/a ; Yes ; ++------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+-------------------------+ + + +Synchronizer Chain #1: Typical MTBF is Greater than 1 Billion Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; GPIO_0[1] ; +; Synchronization Node ; system:inst_cpu|system_uart_0:uart_0|system_uart_0_rx:the_system_uart_0_rx|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------+ + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++-----------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++-----------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 18.290 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 12.5 ; ; ; ; +; Source Clock ; ; ; ; ; +; Unknown ; ; ; ; ; +; Synchronization Clock ; ; ; ; ; +; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; 10.000 ; 100.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; GPIO_0[1] ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; system:inst_cpu|system_uart_0:uart_0|system_uart_0_rx:the_system_uart_0_rx|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 ; ; ; ; 9.568 ; +; system:inst_cpu|system_uart_0:uart_0|system_uart_0_rx:the_system_uart_0_rx|altera_std_synchronizer:the_altera_std_synchronizer|dreg[0] ; ; ; ; 8.722 ; ++-----------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #2: Typical MTBF is Greater than 1 Billion Years +=============================================================================== ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; +; Synchronization Node ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer2|din_s1 ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 19.130 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 1.25 ; ; ; ; +; Source Clock ; ; ; ; ; +; altera_reserved_tck ; ; 100.000 ; 10.0 MHz ; ; +; Synchronization Clock ; ; ; ; ; +; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; 10.000 ; 100.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; ; ; ; ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; ; ; ; ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer2|din_s1 ; ; ; ; 9.569 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer2|dreg[0] ; ; ; ; 9.561 ; ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #3: Typical MTBF is Greater than 1 Billion Years +=============================================================================== ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; +; Synchronization Node ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3|din_s1 ; +; Typical MTBF (years) ; Greater than 1 Billion ; +; Included in Design MTBF ; Yes ; ++-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; 19.133 ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 1.25 ; ; ; ; +; Source Clock ; ; ; ; ; +; altera_reserved_tck ; ; 100.000 ; 10.0 MHz ; ; +; Synchronization Clock ; ; ; ; ; +; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; 10.000 ; 100.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; ; ; ; ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; ; ; ; ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3|din_s1 ; ; ; ; 9.570 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3|dreg[0] ; ; ; ; 9.563 ; ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #4: Typical MTBF is n/a Years +=============================================================================== ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_debug:the_system_cpu_nios2_oci_debug|monitor_ready ; +; Synchronization Node ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|din_s1 ; +; Typical MTBF (years) ; n/a ; +; Included in Design MTBF ; Yes ; ++-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Typical MTBF (years) ; n/a ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; n/a ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 12.5 ; ; ; ; +; Source Clock ; ; ; ; ; +; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; 10.000 ; 100.0 MHz ; ; +; Synchronization Clock ; ; ; ; ; +; altera_reserved_tck ; ; 100.000 ; 10.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_debug:the_system_cpu_nios2_oci_debug|monitor_ready ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|din_s1 ; ; ; ; n/a ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|dreg[0] ; ; ; ; n/a ; ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+ + + + +Synchronizer Chain #5: Typical MTBF is n/a Years +=============================================================================== ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Chain Summary ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Property ; Value ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source Node ; system:inst_cpu|system_cpu:cpu|hbreak_enabled ; +; Synchronization Node ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 ; +; Typical MTBF (years) ; n/a ; +; Included in Design MTBF ; Yes ; ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Statistics ; ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+ +; Property ; Value ; Clock Period ; Active Edge Rate ; Output Slack ; ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+ +; Method of Synchronizer Identification ; User Specified ; ; ; ; +; Typical MTBF (years) ; n/a ; ; ; ; +; Number of Synchronization Registers in Chain ; 2 ; ; ; ; +; Available Settling Time (ns) ; n/a ; ; ; ; +; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 12.5 ; ; ; ; +; Source Clock ; ; ; ; ; +; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; 10.000 ; 100.0 MHz ; ; +; Synchronization Clock ; ; ; ; ; +; altera_reserved_tck ; ; 100.000 ; 10.0 MHz ; ; +; Asynchronous Source ; ; ; ; ; +; system:inst_cpu|system_cpu:cpu|hbreak_enabled ; ; ; ; ; +; Synchronization Registers ; ; ; ; ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 ; ; ; ; n/a ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer|dreg[0] ; ; ; ; n/a ; ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+--------------+------------------+--------------+ + + + ++-----------------------------------------------------------------------------------------------------------------------+ +; Multicorner Timing Analysis Summary ; ++-----------------------------------------------------------+--------+-------+----------+---------+---------------------+ +; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ; ++-----------------------------------------------------------+--------+-------+----------+---------+---------------------+ +; Worst-case Slack ; 2.020 ; 0.099 ; 1.948 ; 1.268 ; 4.693 ; +; CLOCK_50 ; N/A ; N/A ; N/A ; N/A ; 9.587 ; +; altera_reserved_tck ; N/A ; N/A ; N/A ; N/A ; 49.482 ; +; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 2.020 ; 0.099 ; 1.948 ; 1.268 ; 4.693 ; +; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 97.388 ; 0.193 ; N/A ; N/A ; 49.744 ; +; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; +; CLOCK_50 ; N/A ; N/A ; N/A ; N/A ; 0.000 ; +; altera_reserved_tck ; N/A ; N/A ; N/A ; N/A ; 0.000 ; +; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.000 ; 0.000 ; 0.000 ; 0.000 ; +; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.000 ; 0.000 ; N/A ; N/A ; 0.000 ; ++-----------------------------------------------------------+--------+-------+----------+---------+---------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------+ +; Setup Times ; ++---------------------+---------------------+-------+-------+------------+----------------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++---------------------+---------------------+-------+-------+------------+----------------------------------------------------------+ +; altera_reserved_tdi ; altera_reserved_tck ; 1.658 ; 1.798 ; Rise ; altera_reserved_tck ; +; altera_reserved_tms ; altera_reserved_tck ; 6.826 ; 7.042 ; Rise ; altera_reserved_tck ; +; DRAM_DQ[*] ; CLOCK_50 ; 1.013 ; 1.177 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 1.013 ; 1.177 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 1.013 ; 1.177 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 0.978 ; 1.140 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 1.007 ; 1.171 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 1.001 ; 1.165 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 0.999 ; 1.163 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 0.999 ; 1.163 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 0.978 ; 1.140 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 0.976 ; 1.138 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 0.976 ; 1.138 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 0.975 ; 1.137 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 0.975 ; 1.137 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 0.979 ; 1.141 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 0.975 ; 1.137 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 0.975 ; 1.137 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[15] ; CLOCK_50 ; 1.001 ; 1.165 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_1[*] ; CLOCK_50 ; 5.109 ; 5.617 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_1[24] ; CLOCK_50 ; 5.109 ; 5.617 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; KEY[*] ; CLOCK_50 ; 4.087 ; 4.551 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; KEY[0] ; CLOCK_50 ; 4.087 ; 4.551 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; KEY[1] ; CLOCK_50 ; 1.744 ; 1.888 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; SW[*] ; CLOCK_50 ; 2.209 ; 2.309 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; SW[0] ; CLOCK_50 ; 1.879 ; 2.052 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; SW[1] ; CLOCK_50 ; 2.209 ; 2.309 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; SW[2] ; CLOCK_50 ; 2.186 ; 2.302 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; SW[3] ; CLOCK_50 ; 2.153 ; 2.300 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ++---------------------+---------------------+-------+-------+------------+----------------------------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------+ +; Hold Times ; ++---------------------+---------------------+--------+--------+------------+----------------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++---------------------+---------------------+--------+--------+------------+----------------------------------------------------------+ +; altera_reserved_tdi ; altera_reserved_tck ; 1.006 ; 0.867 ; Rise ; altera_reserved_tck ; +; altera_reserved_tms ; altera_reserved_tck ; 0.009 ; -0.290 ; Rise ; altera_reserved_tck ; +; DRAM_DQ[*] ; CLOCK_50 ; -0.259 ; -0.525 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; -0.276 ; -0.557 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; -0.276 ; -0.557 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; -0.260 ; -0.528 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; -0.271 ; -0.549 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; -0.266 ; -0.544 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; -0.263 ; -0.541 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; -0.263 ; -0.541 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; -0.261 ; -0.529 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; -0.259 ; -0.526 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; -0.259 ; -0.526 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; -0.259 ; -0.525 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; -0.259 ; -0.525 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; -0.262 ; -0.529 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; -0.259 ; -0.525 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; -0.259 ; -0.525 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[15] ; CLOCK_50 ; -0.266 ; -0.544 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_1[*] ; CLOCK_50 ; -2.447 ; -3.142 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_1[24] ; CLOCK_50 ; -2.447 ; -3.142 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; KEY[*] ; CLOCK_50 ; -0.694 ; -1.016 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; KEY[0] ; CLOCK_50 ; -1.958 ; -2.580 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; KEY[1] ; CLOCK_50 ; -0.694 ; -1.016 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; SW[*] ; CLOCK_50 ; -0.775 ; -1.092 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; SW[0] ; CLOCK_50 ; -0.775 ; -1.092 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; SW[1] ; CLOCK_50 ; -0.982 ; -1.255 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; SW[2] ; CLOCK_50 ; -0.961 ; -1.232 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; SW[3] ; CLOCK_50 ; -0.943 ; -1.235 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ++---------------------+---------------------+--------+--------+------------+----------------------------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------+ +; Clock to Output Times ; ++---------------------+---------------------+--------+--------+------------+----------------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++---------------------+---------------------+--------+--------+------------+----------------------------------------------------------+ +; altera_reserved_tdo ; altera_reserved_tck ; 10.799 ; 11.453 ; Fall ; altera_reserved_tck ; +; DRAM_ADDR[*] ; CLOCK_50 ; 3.074 ; 3.045 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[0] ; CLOCK_50 ; 3.070 ; 3.041 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[1] ; CLOCK_50 ; 2.995 ; 2.967 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[2] ; CLOCK_50 ; 2.995 ; 2.967 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[3] ; CLOCK_50 ; 2.994 ; 2.966 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[4] ; CLOCK_50 ; 2.997 ; 2.969 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[5] ; CLOCK_50 ; 2.994 ; 2.966 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[6] ; CLOCK_50 ; 2.994 ; 2.966 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[7] ; CLOCK_50 ; 2.992 ; 2.964 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[8] ; CLOCK_50 ; 2.974 ; 2.952 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[9] ; CLOCK_50 ; 3.070 ; 3.041 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[10] ; CLOCK_50 ; 3.061 ; 3.032 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[11] ; CLOCK_50 ; 3.074 ; 3.045 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[12] ; CLOCK_50 ; 2.972 ; 2.950 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_BA[*] ; CLOCK_50 ; 2.995 ; 2.967 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_BA[0] ; CLOCK_50 ; 2.994 ; 2.966 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_BA[1] ; CLOCK_50 ; 2.995 ; 2.967 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CAS_N ; CLOCK_50 ; 3.079 ; 3.050 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CS_N ; CLOCK_50 ; 4.281 ; 4.335 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[*] ; CLOCK_50 ; 3.081 ; 3.052 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 3.067 ; 3.038 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 3.067 ; 3.038 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 2.994 ; 2.966 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 2.980 ; 2.958 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 3.079 ; 3.050 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 3.081 ; 3.052 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 3.081 ; 3.052 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 2.993 ; 2.965 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 2.995 ; 2.967 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 2.996 ; 2.968 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 2.996 ; 2.968 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 2.996 ; 2.968 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 2.992 ; 2.964 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 2.996 ; 2.968 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 2.996 ; 2.968 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[15] ; CLOCK_50 ; 3.079 ; 3.050 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQM[*] ; CLOCK_50 ; 2.992 ; 2.964 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQM[0] ; CLOCK_50 ; 2.992 ; 2.964 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQM[1] ; CLOCK_50 ; 2.992 ; 2.964 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_RAS_N ; CLOCK_50 ; 3.079 ; 3.050 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_WE_N ; CLOCK_50 ; 3.075 ; 3.046 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_0[*] ; CLOCK_50 ; 5.512 ; 5.381 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_0[0] ; CLOCK_50 ; 5.512 ; 5.381 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_1[*] ; CLOCK_50 ; 5.981 ; 6.138 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_1[12] ; CLOCK_50 ; 4.896 ; 4.968 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_1[26] ; CLOCK_50 ; 5.981 ; 6.138 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[*] ; CLOCK_50 ; 6.466 ; 6.621 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[0] ; CLOCK_50 ; 6.006 ; 6.094 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[1] ; CLOCK_50 ; 5.468 ; 5.608 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[2] ; CLOCK_50 ; 5.578 ; 5.648 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[3] ; CLOCK_50 ; 5.786 ; 5.865 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[4] ; CLOCK_50 ; 4.558 ; 4.618 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[5] ; CLOCK_50 ; 6.466 ; 6.621 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[6] ; CLOCK_50 ; 4.768 ; 4.781 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CLK ; CLOCK_50 ; 1.192 ; ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[1] ; +; DRAM_CLK ; CLOCK_50 ; ; 1.152 ; Fall ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[1] ; +; LED[*] ; CLOCK_50 ; 4.715 ; 4.828 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; +; LED[7] ; CLOCK_50 ; 4.715 ; 4.828 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; ++---------------------+---------------------+--------+--------+------------+----------------------------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------+ +; Minimum Clock to Output Times ; ++---------------------+---------------------+--------+--------+------------+----------------------------------------------------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++---------------------+---------------------+--------+--------+------------+----------------------------------------------------------+ +; altera_reserved_tdo ; altera_reserved_tck ; 5.012 ; 5.437 ; Fall ; altera_reserved_tck ; +; DRAM_ADDR[*] ; CLOCK_50 ; 1.513 ; 1.513 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[0] ; CLOCK_50 ; 1.571 ; 1.591 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[1] ; CLOCK_50 ; 1.526 ; 1.529 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[2] ; CLOCK_50 ; 1.526 ; 1.529 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[3] ; CLOCK_50 ; 1.526 ; 1.529 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[4] ; CLOCK_50 ; 1.528 ; 1.531 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[5] ; CLOCK_50 ; 1.525 ; 1.528 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[6] ; CLOCK_50 ; 1.526 ; 1.529 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[7] ; CLOCK_50 ; 1.523 ; 1.526 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[8] ; CLOCK_50 ; 1.515 ; 1.515 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[9] ; CLOCK_50 ; 1.571 ; 1.591 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[10] ; CLOCK_50 ; 1.563 ; 1.583 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[11] ; CLOCK_50 ; 1.571 ; 1.591 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_ADDR[12] ; CLOCK_50 ; 1.513 ; 1.513 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_BA[*] ; CLOCK_50 ; 1.525 ; 1.528 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_BA[0] ; CLOCK_50 ; 1.525 ; 1.528 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_BA[1] ; CLOCK_50 ; 1.526 ; 1.529 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CAS_N ; CLOCK_50 ; 1.575 ; 1.595 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CS_N ; CLOCK_50 ; 2.458 ; 2.517 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[*] ; CLOCK_50 ; 1.517 ; 1.517 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[0] ; CLOCK_50 ; 1.567 ; 1.587 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[1] ; CLOCK_50 ; 1.567 ; 1.587 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[2] ; CLOCK_50 ; 1.525 ; 1.528 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[3] ; CLOCK_50 ; 1.517 ; 1.517 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[4] ; CLOCK_50 ; 1.576 ; 1.596 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[5] ; CLOCK_50 ; 1.579 ; 1.599 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[6] ; CLOCK_50 ; 1.579 ; 1.599 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[7] ; CLOCK_50 ; 1.525 ; 1.528 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[8] ; CLOCK_50 ; 1.526 ; 1.529 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[9] ; CLOCK_50 ; 1.527 ; 1.530 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[10] ; CLOCK_50 ; 1.527 ; 1.530 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[11] ; CLOCK_50 ; 1.527 ; 1.530 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[12] ; CLOCK_50 ; 1.523 ; 1.526 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[13] ; CLOCK_50 ; 1.527 ; 1.530 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[14] ; CLOCK_50 ; 1.527 ; 1.530 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQ[15] ; CLOCK_50 ; 1.576 ; 1.596 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQM[*] ; CLOCK_50 ; 1.523 ; 1.526 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQM[0] ; CLOCK_50 ; 1.523 ; 1.526 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_DQM[1] ; CLOCK_50 ; 1.523 ; 1.526 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_RAS_N ; CLOCK_50 ; 1.575 ; 1.595 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_WE_N ; CLOCK_50 ; 1.574 ; 1.594 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_0[*] ; CLOCK_50 ; 2.972 ; 2.777 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_0[0] ; CLOCK_50 ; 2.972 ; 2.777 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_1[*] ; CLOCK_50 ; 2.498 ; 2.652 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_1[12] ; CLOCK_50 ; 2.498 ; 2.652 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_1[26] ; CLOCK_50 ; 3.334 ; 3.524 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[*] ; CLOCK_50 ; 2.309 ; 2.451 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[0] ; CLOCK_50 ; 3.127 ; 3.330 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[1] ; CLOCK_50 ; 2.830 ; 3.039 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[2] ; CLOCK_50 ; 2.869 ; 3.058 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[3] ; CLOCK_50 ; 2.984 ; 3.186 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[4] ; CLOCK_50 ; 2.309 ; 2.451 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[5] ; CLOCK_50 ; 3.584 ; 3.800 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[6] ; CLOCK_50 ; 2.387 ; 2.517 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_CLK ; CLOCK_50 ; -0.195 ; ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[1] ; +; DRAM_CLK ; CLOCK_50 ; ; -0.166 ; Fall ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[1] ; +; LED[*] ; CLOCK_50 ; 2.623 ; 2.720 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; +; LED[7] ; CLOCK_50 ; 2.623 ; 2.720 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; ++---------------------+---------------------+--------+--------+------------+----------------------------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Board Trace Model Assignments ; ++---------------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ; ++---------------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +; DRAM_CLK ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_CKE ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_CS_N ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_RAS_N ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_CAS_N ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_WE_N ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_DQM[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_DQM[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_ADDR[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_ADDR[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_ADDR[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_ADDR[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_ADDR[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_ADDR[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_ADDR[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_ADDR[7] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_ADDR[8] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_ADDR[9] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_ADDR[10] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_ADDR[11] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_ADDR[12] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_BA[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_BA[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LED[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LED[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LED[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LED[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LED[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LED[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LED[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; LED[7] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_0[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_0[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_0[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_0[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_0[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_0[7] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_0[8] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_0[9] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_0[10] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_0[11] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_0[12] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_0[13] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_0[14] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_0[15] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_0[16] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_0[17] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_0[18] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_0[19] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_0[20] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_0[21] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_0[22] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_0[23] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_0[24] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_0[25] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_0[26] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_0[27] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_0[28] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_0[29] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_0[30] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_0[31] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_0[32] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_0[33] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[7] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[8] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[9] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[10] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[11] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[13] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[14] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[15] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[16] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[17] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[18] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[19] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[20] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[21] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[22] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[23] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[25] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[27] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[28] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[29] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[30] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[31] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[32] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[33] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_DQ[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_DQ[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_DQ[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_DQ[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_DQ[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_DQ[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_DQ[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_DQ[7] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_DQ[8] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_DQ[9] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_DQ[10] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_DQ[11] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_DQ[12] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_DQ[13] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_DQ[14] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; DRAM_DQ[15] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_0[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_0[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[12] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[24] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; GPIO_1[26] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; altera_reserved_tdo ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; ~ALTERA_DCLK~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +; ~ALTERA_nCEO~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ++---------------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ + + ++----------------------------------------------------------------------------+ +; Input Transition Times ; ++-------------------------+--------------+-----------------+-----------------+ +; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ; ++-------------------------+--------------+-----------------+-----------------+ +; GPIO_0[2] ; 2.5 V ; 2000 ps ; 2000 ps ; +; GPIO_0[3] ; 2.5 V ; 2000 ps ; 2000 ps ; +; GPIO_0[4] ; 2.5 V ; 2000 ps ; 2000 ps ; +; GPIO_0[5] ; 2.5 V ; 2000 ps ; 2000 ps ; +; GPIO_0[6] ; 2.5 V ; 2000 ps ; 2000 ps ; +; GPIO_0[7] ; 2.5 V ; 2000 ps ; 2000 ps ; +; GPIO_0[8] ; 2.5 V ; 2000 ps ; 2000 ps ; +; GPIO_0[9] ; 2.5 V ; 2000 ps ; 2000 ps ; +; GPIO_0[10] ; 2.5 V ; 2000 ps ; 2000 ps ; +; GPIO_0[11] ; 2.5 V ; 2000 ps ; 2000 ps ; +; GPIO_0[12] ; 2.5 V ; 2000 ps ; 2000 ps ; +; GPIO_0[13] ; 2.5 V ; 2000 ps ; 2000 ps ; +; GPIO_0[14] ; 2.5 V ; 2000 ps ; 2000 ps ; +; GPIO_0[15] ; 2.5 V ; 2000 ps ; 2000 ps ; +; GPIO_0[16] ; 2.5 V ; 2000 ps ; 2000 ps ; +; GPIO_0[17] ; 2.5 V ; 2000 ps ; 2000 ps ; +; GPIO_0[18] ; 2.5 V ; 2000 ps ; 2000 ps ; +; GPIO_0[19] ; 2.5 V ; 2000 ps ; 2000 ps ; +; GPIO_0[20] ; 2.5 V ; 2000 ps ; 2000 ps ; +; GPIO_0[21] ; 2.5 V ; 2000 ps ; 2000 ps ; +; GPIO_0[22] ; 2.5 V ; 2000 ps ; 2000 ps ; +; GPIO_0[23] ; 2.5 V ; 2000 ps ; 2000 ps ; +; GPIO_0[24] ; 2.5 V ; 2000 ps ; 2000 ps ; +; GPIO_0[25] ; 2.5 V ; 2000 ps ; 2000 ps ; +; GPIO_0[26] ; 2.5 V ; 2000 ps ; 2000 ps ; +; GPIO_0[27] ; 2.5 V ; 2000 ps ; 2000 ps ; +; GPIO_0[28] ; 2.5 V ; 2000 ps ; 2000 ps ; +; GPIO_0[29] ; 2.5 V ; 2000 ps ; 2000 ps ; +; GPIO_0[30] ; 2.5 V ; 2000 ps ; 2000 ps ; +; GPIO_0[31] ; 2.5 V ; 2000 ps ; 2000 ps ; +; GPIO_0[32] ; 2.5 V ; 2000 ps ; 2000 ps ; +; GPIO_0[33] ; 2.5 V ; 2000 ps ; 2000 ps ; +; GPIO_1[0] ; 2.5 V ; 2000 ps ; 2000 ps ; +; GPIO_1[1] ; 2.5 V ; 2000 ps ; 2000 ps ; +; GPIO_1[2] ; 2.5 V ; 2000 ps ; 2000 ps ; +; GPIO_1[3] ; 2.5 V ; 2000 ps ; 2000 ps ; +; GPIO_1[4] ; 2.5 V ; 2000 ps ; 2000 ps ; +; GPIO_1[5] ; 2.5 V ; 2000 ps ; 2000 ps ; +; GPIO_1[6] ; 2.5 V ; 2000 ps ; 2000 ps ; +; GPIO_1[7] ; 2.5 V ; 2000 ps ; 2000 ps ; +; GPIO_1[8] ; 2.5 V ; 2000 ps ; 2000 ps ; +; GPIO_1[9] ; 2.5 V ; 2000 ps ; 2000 ps ; +; GPIO_1[10] ; 2.5 V ; 2000 ps ; 2000 ps ; +; GPIO_1[11] ; 2.5 V ; 2000 ps ; 2000 ps ; +; GPIO_1[13] ; 2.5 V ; 2000 ps ; 2000 ps ; +; GPIO_1[14] ; 2.5 V ; 2000 ps ; 2000 ps ; +; GPIO_1[15] ; 2.5 V ; 2000 ps ; 2000 ps ; +; GPIO_1[16] ; 2.5 V ; 2000 ps ; 2000 ps ; +; GPIO_1[17] ; 2.5 V ; 2000 ps ; 2000 ps ; +; GPIO_1[18] ; 2.5 V ; 2000 ps ; 2000 ps ; +; GPIO_1[19] ; 2.5 V ; 2000 ps ; 2000 ps ; +; GPIO_1[20] ; 2.5 V ; 2000 ps ; 2000 ps ; +; GPIO_1[21] ; 2.5 V ; 2000 ps ; 2000 ps ; +; GPIO_1[22] ; 2.5 V ; 2000 ps ; 2000 ps ; +; GPIO_1[23] ; 2.5 V ; 2000 ps ; 2000 ps ; +; GPIO_1[25] ; 2.5 V ; 2000 ps ; 2000 ps ; +; GPIO_1[27] ; 2.5 V ; 2000 ps ; 2000 ps ; +; GPIO_1[28] ; 2.5 V ; 2000 ps ; 2000 ps ; +; GPIO_1[29] ; 2.5 V ; 2000 ps ; 2000 ps ; +; GPIO_1[30] ; 2.5 V ; 2000 ps ; 2000 ps ; +; GPIO_1[31] ; 2.5 V ; 2000 ps ; 2000 ps ; +; GPIO_1[32] ; 2.5 V ; 2000 ps ; 2000 ps ; +; GPIO_1[33] ; 2.5 V ; 2000 ps ; 2000 ps ; +; DRAM_DQ[0] ; 2.5 V ; 2000 ps ; 2000 ps ; +; DRAM_DQ[1] ; 2.5 V ; 2000 ps ; 2000 ps ; +; DRAM_DQ[2] ; 2.5 V ; 2000 ps ; 2000 ps ; +; DRAM_DQ[3] ; 2.5 V ; 2000 ps ; 2000 ps ; +; DRAM_DQ[4] ; 2.5 V ; 2000 ps ; 2000 ps ; +; DRAM_DQ[5] ; 2.5 V ; 2000 ps ; 2000 ps ; +; DRAM_DQ[6] ; 2.5 V ; 2000 ps ; 2000 ps ; +; DRAM_DQ[7] ; 2.5 V ; 2000 ps ; 2000 ps ; +; DRAM_DQ[8] ; 2.5 V ; 2000 ps ; 2000 ps ; +; DRAM_DQ[9] ; 2.5 V ; 2000 ps ; 2000 ps ; +; DRAM_DQ[10] ; 2.5 V ; 2000 ps ; 2000 ps ; +; DRAM_DQ[11] ; 2.5 V ; 2000 ps ; 2000 ps ; +; DRAM_DQ[12] ; 2.5 V ; 2000 ps ; 2000 ps ; +; DRAM_DQ[13] ; 2.5 V ; 2000 ps ; 2000 ps ; +; DRAM_DQ[14] ; 2.5 V ; 2000 ps ; 2000 ps ; +; DRAM_DQ[15] ; 2.5 V ; 2000 ps ; 2000 ps ; +; GPIO_0[0] ; 2.5 V ; 2000 ps ; 2000 ps ; +; GPIO_0[1] ; 2.5 V ; 2000 ps ; 2000 ps ; +; GPIO_1[12] ; 2.5 V ; 2000 ps ; 2000 ps ; +; GPIO_1[24] ; 2.5 V ; 2000 ps ; 2000 ps ; +; GPIO_1[26] ; 2.5 V ; 2000 ps ; 2000 ps ; +; CLOCK_50 ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[3] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[2] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[1] ; 2.5 V ; 2000 ps ; 2000 ps ; +; KEY[1] ; 2.5 V ; 2000 ps ; 2000 ps ; +; KEY[0] ; 2.5 V ; 2000 ps ; 2000 ps ; +; SW[0] ; 2.5 V ; 2000 ps ; 2000 ps ; +; altera_reserved_tms ; 2.5 V ; 2000 ps ; 2000 ps ; +; altera_reserved_tck ; 2.5 V ; 2000 ps ; 2000 ps ; +; altera_reserved_tdi ; 2.5 V ; 2000 ps ; 2000 ps ; +; ~ALTERA_ASDO_DATA1~ ; 2.5 V ; 2000 ps ; 2000 ps ; +; ~ALTERA_FLASH_nCE_nCSO~ ; 2.5 V ; 2000 ps ; 2000 ps ; +; ~ALTERA_DATA0~ ; 2.5 V ; 2000 ps ; 2000 ps ; ++-------------------------+--------------+-----------------+-----------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Slow 1200mv 0c Model) ; ++---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; DRAM_CLK ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; +; DRAM_CKE ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; +; DRAM_CS_N ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.33 V ; -0.00616 V ; 0.191 V ; 0.099 V ; 2.83e-09 s ; 2.56e-09 s ; No ; Yes ; 2.32 V ; 5.95e-09 V ; 2.33 V ; -0.00616 V ; 0.191 V ; 0.099 V ; 2.83e-09 s ; 2.56e-09 s ; No ; Yes ; +; DRAM_RAS_N ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; +; DRAM_CAS_N ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; +; DRAM_WE_N ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; +; DRAM_DQM[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; +; DRAM_DQM[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; +; DRAM_ADDR[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; +; DRAM_ADDR[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; +; DRAM_ADDR[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; +; DRAM_ADDR[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; +; DRAM_ADDR[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; +; DRAM_ADDR[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; +; DRAM_ADDR[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; +; DRAM_ADDR[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; +; DRAM_ADDR[8] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.39 V ; -0.0265 V ; 0.2 V ; 0.033 V ; 2.94e-10 s ; 3.12e-10 s ; Yes ; Yes ; 2.32 V ; 4.44e-09 V ; 2.39 V ; -0.0265 V ; 0.2 V ; 0.033 V ; 2.94e-10 s ; 3.12e-10 s ; Yes ; Yes ; +; DRAM_ADDR[9] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; +; DRAM_ADDR[10] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; +; DRAM_ADDR[11] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; +; DRAM_ADDR[12] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.39 V ; -0.0265 V ; 0.2 V ; 0.033 V ; 2.94e-10 s ; 3.12e-10 s ; Yes ; Yes ; 2.32 V ; 4.44e-09 V ; 2.39 V ; -0.0265 V ; 0.2 V ; 0.033 V ; 2.94e-10 s ; 3.12e-10 s ; Yes ; Yes ; +; DRAM_BA[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; +; DRAM_BA[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; +; LED[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; +; LED[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; +; LED[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; +; LED[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; +; LED[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; +; LED[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.33 V ; -0.00624 V ; 0.185 V ; 0.097 V ; 2.82e-09 s ; 2.56e-09 s ; No ; Yes ; 2.32 V ; 4.44e-09 V ; 2.33 V ; -0.00624 V ; 0.185 V ; 0.097 V ; 2.82e-09 s ; 2.56e-09 s ; No ; Yes ; +; LED[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.39 V ; -0.0265 V ; 0.2 V ; 0.033 V ; 2.94e-10 s ; 3.12e-10 s ; Yes ; Yes ; 2.32 V ; 4.44e-09 V ; 2.39 V ; -0.0265 V ; 0.2 V ; 0.033 V ; 2.94e-10 s ; 3.12e-10 s ; Yes ; Yes ; +; LED[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.33 V ; -0.00624 V ; 0.185 V ; 0.097 V ; 2.82e-09 s ; 2.56e-09 s ; No ; Yes ; 2.32 V ; 4.44e-09 V ; 2.33 V ; -0.00624 V ; 0.185 V ; 0.097 V ; 2.82e-09 s ; 2.56e-09 s ; No ; Yes ; +; GPIO_0[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; +; GPIO_0[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; +; GPIO_0[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; +; GPIO_0[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; +; GPIO_0[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; +; GPIO_0[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; +; GPIO_0[8] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; +; GPIO_0[9] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; +; GPIO_0[10] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; +; GPIO_0[11] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; +; GPIO_0[12] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; +; GPIO_0[13] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; +; GPIO_0[14] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; +; GPIO_0[15] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.33 V ; -0.00616 V ; 0.191 V ; 0.099 V ; 2.83e-09 s ; 2.56e-09 s ; No ; Yes ; 2.32 V ; 5.95e-09 V ; 2.33 V ; -0.00616 V ; 0.191 V ; 0.099 V ; 2.83e-09 s ; 2.56e-09 s ; No ; Yes ; +; GPIO_0[16] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; +; GPIO_0[17] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; +; GPIO_0[18] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; +; GPIO_0[19] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; +; GPIO_0[20] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; +; GPIO_0[21] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; +; GPIO_0[22] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; +; GPIO_0[23] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; +; GPIO_0[24] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; +; GPIO_0[25] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; +; GPIO_0[26] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; +; GPIO_0[27] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; +; GPIO_0[28] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.33 V ; -0.00616 V ; 0.191 V ; 0.099 V ; 2.83e-09 s ; 2.56e-09 s ; No ; Yes ; 2.32 V ; 5.95e-09 V ; 2.33 V ; -0.00616 V ; 0.191 V ; 0.099 V ; 2.83e-09 s ; 2.56e-09 s ; No ; Yes ; +; GPIO_0[29] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; +; GPIO_0[30] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; +; GPIO_0[31] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; +; GPIO_0[32] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; +; GPIO_0[33] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; +; GPIO_1[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.39 V ; -0.0265 V ; 0.2 V ; 0.033 V ; 2.94e-10 s ; 3.12e-10 s ; Yes ; Yes ; 2.32 V ; 4.44e-09 V ; 2.39 V ; -0.0265 V ; 0.2 V ; 0.033 V ; 2.94e-10 s ; 3.12e-10 s ; Yes ; Yes ; +; GPIO_1[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; +; GPIO_1[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; +; GPIO_1[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; +; GPIO_1[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; +; GPIO_1[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; +; GPIO_1[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; +; GPIO_1[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; +; GPIO_1[8] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; +; GPIO_1[9] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; +; GPIO_1[10] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.33 V ; -0.00616 V ; 0.191 V ; 0.099 V ; 2.83e-09 s ; 2.56e-09 s ; No ; Yes ; 2.32 V ; 5.95e-09 V ; 2.33 V ; -0.00616 V ; 0.191 V ; 0.099 V ; 2.83e-09 s ; 2.56e-09 s ; No ; Yes ; +; GPIO_1[11] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; +; GPIO_1[13] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; +; GPIO_1[14] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; +; GPIO_1[15] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; +; GPIO_1[16] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; +; GPIO_1[17] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; +; GPIO_1[18] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; +; GPIO_1[19] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; +; GPIO_1[20] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.39 V ; -0.0265 V ; 0.2 V ; 0.033 V ; 2.94e-10 s ; 3.12e-10 s ; Yes ; Yes ; 2.32 V ; 4.44e-09 V ; 2.39 V ; -0.0265 V ; 0.2 V ; 0.033 V ; 2.94e-10 s ; 3.12e-10 s ; Yes ; Yes ; +; GPIO_1[21] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; +; GPIO_1[22] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; +; GPIO_1[23] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; +; GPIO_1[25] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; +; GPIO_1[27] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.39 V ; -0.0265 V ; 0.2 V ; 0.033 V ; 2.94e-10 s ; 3.12e-10 s ; Yes ; Yes ; 2.32 V ; 4.44e-09 V ; 2.39 V ; -0.0265 V ; 0.2 V ; 0.033 V ; 2.94e-10 s ; 3.12e-10 s ; Yes ; Yes ; +; GPIO_1[28] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; +; GPIO_1[29] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; +; GPIO_1[30] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; +; GPIO_1[31] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; +; GPIO_1[32] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; +; GPIO_1[33] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; +; DRAM_DQ[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; +; DRAM_DQ[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; +; DRAM_DQ[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; +; DRAM_DQ[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.39 V ; -0.0265 V ; 0.2 V ; 0.033 V ; 2.94e-10 s ; 3.12e-10 s ; Yes ; Yes ; 2.32 V ; 4.44e-09 V ; 2.39 V ; -0.0265 V ; 0.2 V ; 0.033 V ; 2.94e-10 s ; 3.12e-10 s ; Yes ; Yes ; +; DRAM_DQ[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; +; DRAM_DQ[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; +; DRAM_DQ[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; +; DRAM_DQ[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; +; DRAM_DQ[8] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; +; DRAM_DQ[9] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; +; DRAM_DQ[10] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; +; DRAM_DQ[11] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; +; DRAM_DQ[12] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; +; DRAM_DQ[13] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; +; DRAM_DQ[14] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; +; DRAM_DQ[15] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; +; GPIO_0[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; +; GPIO_0[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; +; GPIO_1[12] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; 2.32 V ; 5.95e-09 V ; 2.38 V ; -0.016 V ; 0.22 V ; 0.025 V ; 3.06e-10 s ; 3.3e-10 s ; Yes ; Yes ; +; GPIO_1[24] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; 2.32 V ; 4.44e-09 V ; 2.38 V ; -0.0145 V ; 0.169 V ; 0.026 V ; 4.83e-10 s ; 4.71e-10 s ; Yes ; Yes ; +; GPIO_1[26] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.44e-09 V ; 2.33 V ; -0.00624 V ; 0.185 V ; 0.097 V ; 2.82e-09 s ; 2.56e-09 s ; No ; Yes ; 2.32 V ; 4.44e-09 V ; 2.33 V ; -0.00624 V ; 0.185 V ; 0.097 V ; 2.82e-09 s ; 2.56e-09 s ; No ; Yes ; +; altera_reserved_tdo ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.78e-08 V ; 2.33 V ; -0.00528 V ; 0.066 V ; 0.115 V ; 8.41e-10 s ; 1.83e-09 s ; Yes ; Yes ; 2.32 V ; 2.78e-08 V ; 2.33 V ; -0.00528 V ; 0.066 V ; 0.115 V ; 8.41e-10 s ; 1.83e-09 s ; Yes ; Yes ; +; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.45e-09 V ; 2.38 V ; -0.0609 V ; 0.148 V ; 0.095 V ; 2.82e-10 s ; 2.59e-10 s ; Yes ; Yes ; 2.32 V ; 3.45e-09 V ; 2.38 V ; -0.0609 V ; 0.148 V ; 0.095 V ; 2.82e-10 s ; 2.59e-10 s ; Yes ; Yes ; +; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.61e-09 V ; 2.38 V ; -0.00274 V ; 0.141 V ; 0.006 V ; 4.7e-10 s ; 6.02e-10 s ; Yes ; Yes ; 2.32 V ; 5.61e-09 V ; 2.38 V ; -0.00274 V ; 0.141 V ; 0.006 V ; 4.7e-10 s ; 6.02e-10 s ; Yes ; Yes ; ++---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Slow 1200mv 85c Model) ; ++---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; DRAM_CLK ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; +; DRAM_CKE ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; +; DRAM_CS_N ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.33 V ; -0.00344 V ; 0.134 V ; 0.075 V ; 3.33e-09 s ; 3.16e-09 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.33 V ; -0.00344 V ; 0.134 V ; 0.075 V ; 3.33e-09 s ; 3.16e-09 s ; Yes ; Yes ; +; DRAM_RAS_N ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; +; DRAM_CAS_N ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; +; DRAM_WE_N ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; +; DRAM_DQM[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; +; DRAM_DQM[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; +; DRAM_ADDR[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; +; DRAM_ADDR[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; +; DRAM_ADDR[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; +; DRAM_ADDR[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; +; DRAM_ADDR[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; +; DRAM_ADDR[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; +; DRAM_ADDR[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; +; DRAM_ADDR[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; +; DRAM_ADDR[8] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.36 V ; -0.00476 V ; 0.096 V ; 0.013 V ; 4.39e-10 s ; 4.15e-10 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.36 V ; -0.00476 V ; 0.096 V ; 0.013 V ; 4.39e-10 s ; 4.15e-10 s ; Yes ; Yes ; +; DRAM_ADDR[9] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; +; DRAM_ADDR[10] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; +; DRAM_ADDR[11] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; +; DRAM_ADDR[12] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.36 V ; -0.00476 V ; 0.096 V ; 0.013 V ; 4.39e-10 s ; 4.15e-10 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.36 V ; -0.00476 V ; 0.096 V ; 0.013 V ; 4.39e-10 s ; 4.15e-10 s ; Yes ; Yes ; +; DRAM_BA[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; +; DRAM_BA[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; +; LED[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; +; LED[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; +; LED[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; +; LED[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; +; LED[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; +; LED[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.33 V ; -0.00349 V ; 0.163 V ; 0.074 V ; 3.33e-09 s ; 3.14e-09 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.33 V ; -0.00349 V ; 0.163 V ; 0.074 V ; 3.33e-09 s ; 3.14e-09 s ; Yes ; Yes ; +; LED[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.36 V ; -0.00476 V ; 0.096 V ; 0.013 V ; 4.39e-10 s ; 4.15e-10 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.36 V ; -0.00476 V ; 0.096 V ; 0.013 V ; 4.39e-10 s ; 4.15e-10 s ; Yes ; Yes ; +; LED[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.33 V ; -0.00349 V ; 0.163 V ; 0.074 V ; 3.33e-09 s ; 3.14e-09 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.33 V ; -0.00349 V ; 0.163 V ; 0.074 V ; 3.33e-09 s ; 3.14e-09 s ; Yes ; Yes ; +; GPIO_0[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; +; GPIO_0[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; +; GPIO_0[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; +; GPIO_0[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; +; GPIO_0[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; +; GPIO_0[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; +; GPIO_0[8] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; +; GPIO_0[9] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; +; GPIO_0[10] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; +; GPIO_0[11] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; +; GPIO_0[12] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; +; GPIO_0[13] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; +; GPIO_0[14] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; +; GPIO_0[15] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.33 V ; -0.00344 V ; 0.134 V ; 0.075 V ; 3.33e-09 s ; 3.16e-09 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.33 V ; -0.00344 V ; 0.134 V ; 0.075 V ; 3.33e-09 s ; 3.16e-09 s ; Yes ; Yes ; +; GPIO_0[16] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; +; GPIO_0[17] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; +; GPIO_0[18] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; +; GPIO_0[19] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; +; GPIO_0[20] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; +; GPIO_0[21] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; +; GPIO_0[22] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; +; GPIO_0[23] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; +; GPIO_0[24] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; +; GPIO_0[25] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; +; GPIO_0[26] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; +; GPIO_0[27] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; +; GPIO_0[28] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.33 V ; -0.00344 V ; 0.134 V ; 0.075 V ; 3.33e-09 s ; 3.16e-09 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.33 V ; -0.00344 V ; 0.134 V ; 0.075 V ; 3.33e-09 s ; 3.16e-09 s ; Yes ; Yes ; +; GPIO_0[29] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; +; GPIO_0[30] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; +; GPIO_0[31] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; +; GPIO_0[32] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; +; GPIO_0[33] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; +; GPIO_1[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.36 V ; -0.00476 V ; 0.096 V ; 0.013 V ; 4.39e-10 s ; 4.15e-10 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.36 V ; -0.00476 V ; 0.096 V ; 0.013 V ; 4.39e-10 s ; 4.15e-10 s ; Yes ; Yes ; +; GPIO_1[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; +; GPIO_1[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; +; GPIO_1[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; +; GPIO_1[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; +; GPIO_1[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; +; GPIO_1[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; +; GPIO_1[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; +; GPIO_1[8] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; +; GPIO_1[9] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; +; GPIO_1[10] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.33 V ; -0.00344 V ; 0.134 V ; 0.075 V ; 3.33e-09 s ; 3.16e-09 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.33 V ; -0.00344 V ; 0.134 V ; 0.075 V ; 3.33e-09 s ; 3.16e-09 s ; Yes ; Yes ; +; GPIO_1[11] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; +; GPIO_1[13] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; +; GPIO_1[14] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; +; GPIO_1[15] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; +; GPIO_1[16] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; +; GPIO_1[17] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; +; GPIO_1[18] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; +; GPIO_1[19] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; +; GPIO_1[20] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.36 V ; -0.00476 V ; 0.096 V ; 0.013 V ; 4.39e-10 s ; 4.15e-10 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.36 V ; -0.00476 V ; 0.096 V ; 0.013 V ; 4.39e-10 s ; 4.15e-10 s ; Yes ; Yes ; +; GPIO_1[21] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; +; GPIO_1[22] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; +; GPIO_1[23] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; +; GPIO_1[25] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; +; GPIO_1[27] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.36 V ; -0.00476 V ; 0.096 V ; 0.013 V ; 4.39e-10 s ; 4.15e-10 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.36 V ; -0.00476 V ; 0.096 V ; 0.013 V ; 4.39e-10 s ; 4.15e-10 s ; Yes ; Yes ; +; GPIO_1[28] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; +; GPIO_1[29] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; +; GPIO_1[30] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; +; GPIO_1[31] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; +; GPIO_1[32] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; +; GPIO_1[33] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; +; DRAM_DQ[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; +; DRAM_DQ[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; +; DRAM_DQ[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; +; DRAM_DQ[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.36 V ; -0.00476 V ; 0.096 V ; 0.013 V ; 4.39e-10 s ; 4.15e-10 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.36 V ; -0.00476 V ; 0.096 V ; 0.013 V ; 4.39e-10 s ; 4.15e-10 s ; Yes ; Yes ; +; DRAM_DQ[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; +; DRAM_DQ[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; +; DRAM_DQ[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; +; DRAM_DQ[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; +; DRAM_DQ[8] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; +; DRAM_DQ[9] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; +; DRAM_DQ[10] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; +; DRAM_DQ[11] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; +; DRAM_DQ[12] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; +; DRAM_DQ[13] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; +; DRAM_DQ[14] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; +; DRAM_DQ[15] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; +; GPIO_0[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; +; GPIO_0[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; +; GPIO_1[12] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; 2.32 V ; 1.06e-06 V ; 2.36 V ; -0.00724 V ; 0.107 V ; 0.02 V ; 4.5e-10 s ; 4.25e-10 s ; Yes ; Yes ; +; GPIO_1[24] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.35 V ; -0.00832 V ; 0.101 V ; 0.024 V ; 6.39e-10 s ; 6e-10 s ; Yes ; Yes ; +; GPIO_1[26] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 7.16e-07 V ; 2.33 V ; -0.00349 V ; 0.163 V ; 0.074 V ; 3.33e-09 s ; 3.14e-09 s ; Yes ; Yes ; 2.32 V ; 7.16e-07 V ; 2.33 V ; -0.00349 V ; 0.163 V ; 0.074 V ; 3.33e-09 s ; 3.14e-09 s ; Yes ; Yes ; +; altera_reserved_tdo ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 4.86e-06 V ; 2.33 V ; 4.86e-06 V ; 0.037 V ; 0.055 V ; 1.03e-09 s ; 2.37e-09 s ; Yes ; Yes ; 2.32 V ; 4.86e-06 V ; 2.33 V ; 4.86e-06 V ; 0.037 V ; 0.055 V ; 1.03e-09 s ; 2.37e-09 s ; Yes ; Yes ; +; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 5.74e-07 V ; 2.36 V ; -0.0201 V ; 0.072 V ; 0.033 V ; 4.04e-10 s ; 3.29e-10 s ; Yes ; Yes ; 2.32 V ; 5.74e-07 V ; 2.36 V ; -0.0201 V ; 0.072 V ; 0.033 V ; 4.04e-10 s ; 3.29e-10 s ; Yes ; Yes ; +; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.45e-07 V ; 2.35 V ; -0.00643 V ; 0.081 V ; 0.031 V ; 5.31e-10 s ; 7.59e-10 s ; Yes ; Yes ; 2.32 V ; 9.45e-07 V ; 2.35 V ; -0.00643 V ; 0.081 V ; 0.031 V ; 5.31e-10 s ; 7.59e-10 s ; Yes ; Yes ; ++---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Signal Integrity Metrics (Fast 1200mv 0c Model) ; ++---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; DRAM_CLK ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; DRAM_CKE ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; DRAM_CS_N ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.64 V ; -0.0113 V ; 0.208 V ; 0.179 V ; 2.38e-09 s ; 2.23e-09 s ; No ; Yes ; 2.62 V ; 4.05e-08 V ; 2.64 V ; -0.0113 V ; 0.208 V ; 0.179 V ; 2.38e-09 s ; 2.23e-09 s ; No ; Yes ; +; DRAM_RAS_N ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; +; DRAM_CAS_N ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; +; DRAM_WE_N ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; +; DRAM_DQM[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; DRAM_DQM[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; DRAM_ADDR[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; +; DRAM_ADDR[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; DRAM_ADDR[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; DRAM_ADDR[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; DRAM_ADDR[4] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; DRAM_ADDR[5] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; DRAM_ADDR[6] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; DRAM_ADDR[7] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; DRAM_ADDR[8] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ; +; DRAM_ADDR[9] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; +; DRAM_ADDR[10] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; +; DRAM_ADDR[11] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; +; DRAM_ADDR[12] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ; +; DRAM_BA[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; DRAM_BA[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; LED[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; LED[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; LED[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; LED[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; LED[4] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; +; LED[5] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.64 V ; -0.0117 V ; 0.202 V ; 0.176 V ; 2.38e-09 s ; 2.22e-09 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.64 V ; -0.0117 V ; 0.202 V ; 0.176 V ; 2.38e-09 s ; 2.22e-09 s ; No ; Yes ; +; LED[6] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ; +; LED[7] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.64 V ; -0.0117 V ; 0.202 V ; 0.176 V ; 2.38e-09 s ; 2.22e-09 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.64 V ; -0.0117 V ; 0.202 V ; 0.176 V ; 2.38e-09 s ; 2.22e-09 s ; No ; Yes ; +; GPIO_0[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; GPIO_0[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; GPIO_0[4] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; GPIO_0[5] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; GPIO_0[6] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; GPIO_0[7] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; GPIO_0[8] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; GPIO_0[9] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; GPIO_0[10] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; GPIO_0[11] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; GPIO_0[12] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; GPIO_0[13] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; GPIO_0[14] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; GPIO_0[15] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.64 V ; -0.0113 V ; 0.208 V ; 0.179 V ; 2.38e-09 s ; 2.23e-09 s ; No ; Yes ; 2.62 V ; 4.05e-08 V ; 2.64 V ; -0.0113 V ; 0.208 V ; 0.179 V ; 2.38e-09 s ; 2.23e-09 s ; No ; Yes ; +; GPIO_0[16] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; GPIO_0[17] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; GPIO_0[18] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; GPIO_0[19] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; GPIO_0[20] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; GPIO_0[21] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; GPIO_0[22] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; GPIO_0[23] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; GPIO_0[24] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; GPIO_0[25] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; GPIO_0[26] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; GPIO_0[27] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; GPIO_0[28] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.64 V ; -0.0113 V ; 0.208 V ; 0.179 V ; 2.38e-09 s ; 2.23e-09 s ; No ; Yes ; 2.62 V ; 4.05e-08 V ; 2.64 V ; -0.0113 V ; 0.208 V ; 0.179 V ; 2.38e-09 s ; 2.23e-09 s ; No ; Yes ; +; GPIO_0[29] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; GPIO_0[30] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; GPIO_0[31] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; GPIO_0[32] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; GPIO_0[33] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; GPIO_1[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ; +; GPIO_1[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; GPIO_1[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; GPIO_1[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; GPIO_1[4] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; GPIO_1[5] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; GPIO_1[6] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; GPIO_1[7] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; GPIO_1[8] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; GPIO_1[9] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; GPIO_1[10] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.64 V ; -0.0113 V ; 0.208 V ; 0.179 V ; 2.38e-09 s ; 2.23e-09 s ; No ; Yes ; 2.62 V ; 4.05e-08 V ; 2.64 V ; -0.0113 V ; 0.208 V ; 0.179 V ; 2.38e-09 s ; 2.23e-09 s ; No ; Yes ; +; GPIO_1[11] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; GPIO_1[13] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; GPIO_1[14] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; GPIO_1[15] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; GPIO_1[16] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; +; GPIO_1[17] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; +; GPIO_1[18] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; +; GPIO_1[19] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; +; GPIO_1[20] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ; +; GPIO_1[21] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; +; GPIO_1[22] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; GPIO_1[23] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; +; GPIO_1[25] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; GPIO_1[27] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ; +; GPIO_1[28] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; GPIO_1[29] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; +; GPIO_1[30] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; +; GPIO_1[31] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; +; GPIO_1[32] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; +; GPIO_1[33] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; +; DRAM_DQ[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; +; DRAM_DQ[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; +; DRAM_DQ[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; DRAM_DQ[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ; 2.62 V ; 2.74e-08 V ; 2.73 V ; -0.0384 V ; 0.169 V ; 0.089 V ; 2.7e-10 s ; 2.62e-10 s ; Yes ; Yes ; +; DRAM_DQ[4] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; +; DRAM_DQ[5] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; +; DRAM_DQ[6] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; +; DRAM_DQ[7] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; DRAM_DQ[8] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; DRAM_DQ[9] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; DRAM_DQ[10] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; DRAM_DQ[11] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; DRAM_DQ[12] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; DRAM_DQ[13] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; DRAM_DQ[14] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; DRAM_DQ[15] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; +; GPIO_0[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; GPIO_0[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; GPIO_1[12] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; 2.62 V ; 4.05e-08 V ; 2.72 V ; -0.0349 V ; 0.173 V ; 0.1 V ; 2.72e-10 s ; 2.69e-10 s ; Yes ; Yes ; +; GPIO_1[24] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.71 V ; -0.0317 V ; 0.148 V ; 0.064 V ; 4.51e-10 s ; 4.15e-10 s ; No ; Yes ; +; GPIO_1[26] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.74e-08 V ; 2.64 V ; -0.0117 V ; 0.202 V ; 0.176 V ; 2.38e-09 s ; 2.22e-09 s ; No ; Yes ; 2.62 V ; 2.74e-08 V ; 2.64 V ; -0.0117 V ; 0.202 V ; 0.176 V ; 2.38e-09 s ; 2.22e-09 s ; No ; Yes ; +; altera_reserved_tdo ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 1.77e-07 V ; 2.65 V ; -0.0108 V ; 0.18 V ; 0.17 V ; 6.63e-10 s ; 1.56e-09 s ; Yes ; Yes ; 2.62 V ; 1.77e-07 V ; 2.65 V ; -0.0108 V ; 0.18 V ; 0.17 V ; 6.63e-10 s ; 1.56e-09 s ; Yes ; Yes ; +; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.22e-08 V ; 2.74 V ; -0.06 V ; 0.158 V ; 0.08 V ; 2.68e-10 s ; 2.19e-10 s ; Yes ; Yes ; 2.62 V ; 2.22e-08 V ; 2.74 V ; -0.06 V ; 0.158 V ; 0.08 V ; 2.68e-10 s ; 2.19e-10 s ; Yes ; Yes ; +; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.54e-08 V ; 2.7 V ; -0.00943 V ; 0.276 V ; 0.035 V ; 3.19e-10 s ; 4.99e-10 s ; No ; Yes ; 2.62 V ; 3.54e-08 V ; 2.7 V ; -0.00943 V ; 0.276 V ; 0.035 V ; 3.19e-10 s ; 4.99e-10 s ; No ; Yes ; ++---------------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Setup Transfers ; ++----------------------------------------------------------+----------------------------------------------------------+------------+------------+------------+------------+ +; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; ++----------------------------------------------------------+----------------------------------------------------------+------------+------------+------------+------------+ +; altera_reserved_tck ; altera_reserved_tck ; false path ; 0 ; false path ; false path ; +; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; altera_reserved_tck ; false path ; 0 ; 0 ; 0 ; +; altera_reserved_tck ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; false path ; false path ; 0 ; 0 ; +; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 251344 ; 64 ; 224 ; 0 ; +; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 253 ; 0 ; 0 ; 0 ; ++----------------------------------------------------------+----------------------------------------------------------+------------+------------+------------+------------+ +Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Hold Transfers ; ++----------------------------------------------------------+----------------------------------------------------------+------------+------------+------------+------------+ +; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; ++----------------------------------------------------------+----------------------------------------------------------+------------+------------+------------+------------+ +; altera_reserved_tck ; altera_reserved_tck ; false path ; 0 ; false path ; false path ; +; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; altera_reserved_tck ; false path ; 0 ; 0 ; 0 ; +; altera_reserved_tck ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; false path ; false path ; 0 ; 0 ; +; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 251344 ; 64 ; 224 ; 0 ; +; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 253 ; 0 ; 0 ; 0 ; ++----------------------------------------------------------+----------------------------------------------------------+------------+------------+------------+------------+ +Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Recovery Transfers ; ++----------------------------------------------------------+----------------------------------------------------------+------------+----------+------------+----------+ +; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; ++----------------------------------------------------------+----------------------------------------------------------+------------+----------+------------+----------+ +; altera_reserved_tck ; altera_reserved_tck ; false path ; 0 ; false path ; 0 ; +; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 2305 ; 0 ; 32 ; 0 ; ++----------------------------------------------------------+----------------------------------------------------------+------------+----------+------------+----------+ +Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Removal Transfers ; ++----------------------------------------------------------+----------------------------------------------------------+------------+----------+------------+----------+ +; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; ++----------------------------------------------------------+----------------------------------------------------------+------------+----------+------------+----------+ +; altera_reserved_tck ; altera_reserved_tck ; false path ; 0 ; false path ; 0 ; +; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 2305 ; 0 ; 32 ; 0 ; ++----------------------------------------------------------+----------------------------------------------------------+------------+----------+------------+----------+ +Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. + + +--------------- +; Report TCCS ; +--------------- +No dedicated SERDES Transmitter circuitry present in device or used in design + + +--------------- +; Report RSKM ; +--------------- +No dedicated SERDES Receiver circuitry present in device or used in design + + ++------------------------------------------------+ +; Unconstrained Paths ; ++---------------------------------+-------+------+ +; Property ; Setup ; Hold ; ++---------------------------------+-------+------+ +; Illegal Clocks ; 0 ; 0 ; +; Unconstrained Clocks ; 0 ; 0 ; +; Unconstrained Input Ports ; 25 ; 25 ; +; Unconstrained Input Port Paths ; 90 ; 90 ; +; Unconstrained Output Ports ; 50 ; 50 ; +; Unconstrained Output Port Paths ; 66 ; 66 ; ++---------------------------------+-------+------+ + + ++------------------------------------+ +; TimeQuest Timing Analyzer Messages ; ++------------------------------------+ +Info: ******************************************************************* +Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer + Info: Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Full Version + Info: Processing started: Fri Mar 14 16:49:36 2014 +Info: Command: quartus_sta de0_nano_system -c de0_nano_system +Info: qsta_default_script.tcl version: #1 +Info (11104): Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead. +Info (21077): Core supply voltage is 1.2V +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Info (332164): Evaluating HDL-embedded SDC commands + Info (332165): Entity alt_jtag_atlantic + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|jupdate}] -to [get_registers {*|alt_jtag_atlantic:*|jupdate1*}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rdata[*]}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|read}] -to [get_registers {*|alt_jtag_atlantic:*|read1*}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|read_req}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|rvalid}] -to [get_registers {*|alt_jtag_atlantic*|td_shift[*]}] + Info (332166): set_false_path -from [get_registers {*|t_dav}] -to [get_registers {*|alt_jtag_atlantic:*|tck_t_dav}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|user_saw_rvalid}] -to [get_registers {*|alt_jtag_atlantic:*|rvalid0*}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|wdata[*]}] -to [get_registers {*}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write}] -to [get_registers {*|alt_jtag_atlantic:*|write1*}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write_stalled}] -to [get_registers {*|alt_jtag_atlantic:*|t_ena*}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write_stalled}] -to [get_registers {*|alt_jtag_atlantic:*|t_pause*}] + Info (332166): set_false_path -from [get_registers {*|alt_jtag_atlantic:*|write_valid}] + Info (332165): Entity altera_std_synchronizer + Info (332166): set_false_path -to [get_keepers {*altera_std_synchronizer:*|din_s1}] + Info (332165): Entity sld_jtag_hub + Info (332166): create_clock -period 10MHz -name altera_reserved_tck [get_ports {altera_reserved_tck}] + Info (332166): set_clock_groups -asynchronous -group {altera_reserved_tck} +Info (332104): Reading SDC File: 'de0_nano_system.sdc' +Warning (332043): Overwriting existing clock: altera_reserved_tck +Info (332110): Deriving PLL clocks + Info (332110): create_generated_clock -source {inst_pll_sys|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 2 -duty_cycle 50.00 -name {inst_pll_sys|altpll_component|auto_generated|pll1|clk[0]} {inst_pll_sys|altpll_component|auto_generated|pll1|clk[0]} + Info (332110): create_generated_clock -source {inst_pll_sys|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 2 -phase -54.00 -duty_cycle 50.00 -name {inst_pll_sys|altpll_component|auto_generated|pll1|clk[1]} {inst_pll_sys|altpll_component|auto_generated|pll1|clk[1]} + Info (332110): create_generated_clock -source {inst_pll_sys|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 5 -duty_cycle 50.00 -name {inst_pll_sys|altpll_component|auto_generated|pll1|clk[2]} {inst_pll_sys|altpll_component|auto_generated|pll1|clk[2]} +Info (332151): Clock uncertainty is not calculated until you update the timing netlist. +Info (332104): Reading SDC File: 'system/synthesis/submodules/altera_reset_controller.sdc' +Info (332104): Reading SDC File: 'system/synthesis/submodules/system_cpu.sdc' +Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. +Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON +Info: Analyzing Slow 1200mV 85C Model +Info (332146): Worst-case setup slack is 2.020 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= ============= ===================== + Info (332119): 2.020 0.000 inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] + Info (332119): 97.388 0.000 inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] +Info (332146): Worst-case hold slack is 0.228 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= ============= ===================== + Info (332119): 0.228 0.000 inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] + Info (332119): 0.361 0.000 inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] +Info (332146): Worst-case recovery slack is 1.948 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= ============= ===================== + Info (332119): 1.948 0.000 inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] +Info (332146): Worst-case removal slack is 2.209 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= ============= ===================== + Info (332119): 2.209 0.000 inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] +Info (332146): Worst-case minimum pulse width slack is 4.693 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= ============= ===================== + Info (332119): 4.693 0.000 inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] + Info (332119): 9.835 0.000 CLOCK_50 + Info (332119): 49.624 0.000 altera_reserved_tck + Info (332119): 49.747 0.000 inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] +Info (332114): Report Metastability: Found 5 synchronizer chains. + Info (332114): Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. + + Info (332114): Number of Synchronizer Chains Found: 5 + Info (332114): Shortest Synchronizer Chain: 2 Registers + Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 0.400 + Info (332114): Worst Case Available Settling Time: 16.908 ns + Info (332114): + Info (332114): Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. + Info (332114): - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8 +Info: Analyzing Slow 1200mV 0C Model +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. +Info (332146): Worst-case setup slack is 2.319 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= ============= ===================== + Info (332119): 2.319 0.000 inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] + Info (332119): 97.707 0.000 inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] +Info (332146): Worst-case hold slack is 0.224 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= ============= ===================== + Info (332119): 0.224 0.000 inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] + Info (332119): 0.320 0.000 inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] +Info (332146): Worst-case recovery slack is 2.259 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= ============= ===================== + Info (332119): 2.259 0.000 inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] +Info (332146): Worst-case removal slack is 1.967 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= ============= ===================== + Info (332119): 1.967 0.000 inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] +Info (332146): Worst-case minimum pulse width slack is 4.718 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= ============= ===================== + Info (332119): 4.718 0.000 inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] + Info (332119): 9.818 0.000 CLOCK_50 + Info (332119): 49.601 0.000 altera_reserved_tck + Info (332119): 49.744 0.000 inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] +Info (332114): Report Metastability: Found 5 synchronizer chains. + Info (332114): Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. + + Info (332114): Number of Synchronizer Chains Found: 5 + Info (332114): Shortest Synchronizer Chain: 2 Registers + Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 0.400 + Info (332114): Worst Case Available Settling Time: 17.219 ns + Info (332114): + Info (332114): Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. + Info (332114): - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8 +Info: Analyzing Fast 1200mV 0C Model +Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. +Info (332146): Worst-case setup slack is 3.265 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= ============= ===================== + Info (332119): 3.265 0.000 inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] + Info (332119): 98.512 0.000 inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] +Info (332146): Worst-case hold slack is 0.099 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= ============= ===================== + Info (332119): 0.099 0.000 inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] + Info (332119): 0.193 0.000 inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] +Info (332146): Worst-case recovery slack is 3.217 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= ============= ===================== + Info (332119): 3.217 0.000 inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] +Info (332146): Worst-case removal slack is 1.268 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= ============= ===================== + Info (332119): 1.268 0.000 inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] +Info (332146): Worst-case minimum pulse width slack is 4.749 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= ============= ===================== + Info (332119): 4.749 0.000 inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] + Info (332119): 9.587 0.000 CLOCK_50 + Info (332119): 49.482 0.000 altera_reserved_tck + Info (332119): 49.782 0.000 inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] +Info (332114): Report Metastability: Found 5 synchronizer chains. + Info (332114): Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. + + Info (332114): Number of Synchronizer Chains Found: 5 + Info (332114): Shortest Synchronizer Chain: 2 Registers + Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 0.400 + Info (332114): Worst Case Available Settling Time: 18.290 ns + Info (332114): + Info (332114): Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. + Info (332114): - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8 +Info (332102): Design is not fully constrained for setup requirements +Info (332102): Design is not fully constrained for hold requirements +Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 1 warning + Info: Peak virtual memory: 567 megabytes + Info: Processing ended: Fri Mar 14 16:49:42 2014 + Info: Elapsed time: 00:00:06 + Info: Total CPU time (on all processors): 00:00:06 + + diff --git a/MCTEST/DE0-nano-HD/output_files/de0_nano_system.sta.summary b/MCTEST/DE0-nano-HD/output_files/de0_nano_system.sta.summary new file mode 100644 index 00000000..73134d85 --- /dev/null +++ b/MCTEST/DE0-nano-HD/output_files/de0_nano_system.sta.summary @@ -0,0 +1,125 @@ +------------------------------------------------------------ +TimeQuest Timing Analyzer Summary +------------------------------------------------------------ + +Type : Slow 1200mV 85C Model Setup 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[0]' +Slack : 2.020 +TNS : 0.000 + +Type : Slow 1200mV 85C Model Setup 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[2]' +Slack : 97.388 +TNS : 0.000 + +Type : Slow 1200mV 85C Model Hold 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[0]' +Slack : 0.228 +TNS : 0.000 + +Type : Slow 1200mV 85C Model Hold 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[2]' +Slack : 0.361 +TNS : 0.000 + +Type : Slow 1200mV 85C Model Recovery 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[0]' +Slack : 1.948 +TNS : 0.000 + +Type : Slow 1200mV 85C Model Removal 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[0]' +Slack : 2.209 +TNS : 0.000 + +Type : Slow 1200mV 85C Model Minimum Pulse Width 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[0]' +Slack : 4.693 +TNS : 0.000 + +Type : Slow 1200mV 85C Model Minimum Pulse Width 'CLOCK_50' +Slack : 9.835 +TNS : 0.000 + +Type : Slow 1200mV 85C Model Minimum Pulse Width 'altera_reserved_tck' +Slack : 49.624 +TNS : 0.000 + +Type : Slow 1200mV 85C Model Minimum Pulse Width 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[2]' +Slack : 49.747 +TNS : 0.000 + +Type : Slow 1200mV 0C Model Setup 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[0]' +Slack : 2.319 +TNS : 0.000 + +Type : Slow 1200mV 0C Model Setup 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[2]' +Slack : 97.707 +TNS : 0.000 + +Type : Slow 1200mV 0C Model Hold 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[0]' +Slack : 0.224 +TNS : 0.000 + +Type : Slow 1200mV 0C Model Hold 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[2]' +Slack : 0.320 +TNS : 0.000 + +Type : Slow 1200mV 0C Model Recovery 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[0]' +Slack : 2.259 +TNS : 0.000 + +Type : Slow 1200mV 0C Model Removal 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[0]' +Slack : 1.967 +TNS : 0.000 + +Type : Slow 1200mV 0C Model Minimum Pulse Width 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[0]' +Slack : 4.718 +TNS : 0.000 + +Type : Slow 1200mV 0C Model Minimum Pulse Width 'CLOCK_50' +Slack : 9.818 +TNS : 0.000 + +Type : Slow 1200mV 0C Model Minimum Pulse Width 'altera_reserved_tck' +Slack : 49.601 +TNS : 0.000 + +Type : Slow 1200mV 0C Model Minimum Pulse Width 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[2]' +Slack : 49.744 +TNS : 0.000 + +Type : Fast 1200mV 0C Model Setup 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[0]' +Slack : 3.265 +TNS : 0.000 + +Type : Fast 1200mV 0C Model Setup 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[2]' +Slack : 98.512 +TNS : 0.000 + +Type : Fast 1200mV 0C Model Hold 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[0]' +Slack : 0.099 +TNS : 0.000 + +Type : Fast 1200mV 0C Model Hold 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[2]' +Slack : 0.193 +TNS : 0.000 + +Type : Fast 1200mV 0C Model Recovery 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[0]' +Slack : 3.217 +TNS : 0.000 + +Type : Fast 1200mV 0C Model Removal 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[0]' +Slack : 1.268 +TNS : 0.000 + +Type : Fast 1200mV 0C Model Minimum Pulse Width 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[0]' +Slack : 4.749 +TNS : 0.000 + +Type : Fast 1200mV 0C Model Minimum Pulse Width 'CLOCK_50' +Slack : 9.587 +TNS : 0.000 + +Type : Fast 1200mV 0C Model Minimum Pulse Width 'altera_reserved_tck' +Slack : 49.482 +TNS : 0.000 + +Type : Fast 1200mV 0C Model Minimum Pulse Width 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[2]' +Slack : 49.782 +TNS : 0.000 + +------------------------------------------------------------ diff --git a/MCTEST/DE0-nano-HD/pll_sys.cmp b/MCTEST/DE0-nano-HD/pll_sys.cmp new file mode 100644 index 00000000..515e63c6 --- /dev/null +++ b/MCTEST/DE0-nano-HD/pll_sys.cmp @@ -0,0 +1,25 @@ +--Copyright (C) 1991-2012 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component pll_sys + PORT + ( + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + c1 : OUT STD_LOGIC ; + c2 : OUT STD_LOGIC ; + locked : OUT STD_LOGIC + ); +end component; diff --git a/MCTEST/DE0-nano-HD/pll_sys.ppf b/MCTEST/DE0-nano-HD/pll_sys.ppf new file mode 100644 index 00000000..dc3b30bf --- /dev/null +++ b/MCTEST/DE0-nano-HD/pll_sys.ppf @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/MCTEST/DE0-nano-HD/pll_sys.qip b/MCTEST/DE0-nano-HD/pll_sys.qip new file mode 100644 index 00000000..e151d2e0 --- /dev/null +++ b/MCTEST/DE0-nano-HD/pll_sys.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "12.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll_sys.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_sys.cmp"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_sys.ppf"] diff --git a/MCTEST/DE0-nano-HD/pll_sys.vhd b/MCTEST/DE0-nano-HD/pll_sys.vhd new file mode 100644 index 00000000..686a1c28 --- /dev/null +++ b/MCTEST/DE0-nano-HD/pll_sys.vhd @@ -0,0 +1,424 @@ +-- megafunction wizard: %ALTPLL% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altpll + +-- ============================================================ +-- File Name: pll_sys.vhd +-- Megafunction Name(s): +-- altpll +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 12.1 Build 243 01/31/2013 SP 1.33 SJ Full Version +-- ************************************************************ + + +--Copyright (C) 1991-2012 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY pll_sys IS + PORT + ( + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + c1 : OUT STD_LOGIC ; + c2 : OUT STD_LOGIC ; + locked : OUT STD_LOGIC + ); +END pll_sys; + + +ARCHITECTURE SYN OF pll_sys IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3 : STD_LOGIC ; + SIGNAL sub_wire4 : STD_LOGIC ; + SIGNAL sub_wire5 : STD_LOGIC ; + SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0); + + + + COMPONENT altpll + GENERIC ( + bandwidth_type : STRING; + clk0_divide_by : NATURAL; + clk0_duty_cycle : NATURAL; + clk0_multiply_by : NATURAL; + clk0_phase_shift : STRING; + clk1_divide_by : NATURAL; + clk1_duty_cycle : NATURAL; + clk1_multiply_by : NATURAL; + clk1_phase_shift : STRING; + clk2_divide_by : NATURAL; + clk2_duty_cycle : NATURAL; + clk2_multiply_by : NATURAL; + clk2_phase_shift : STRING; + compensate_clock : STRING; + inclk0_input_frequency : NATURAL; + intended_device_family : STRING; + lpm_hint : STRING; + lpm_type : STRING; + operation_mode : STRING; + pll_type : STRING; + port_activeclock : STRING; + port_areset : STRING; + port_clkbad0 : STRING; + port_clkbad1 : STRING; + port_clkloss : STRING; + port_clkswitch : STRING; + port_configupdate : STRING; + port_fbin : STRING; + port_inclk0 : STRING; + port_inclk1 : STRING; + port_locked : STRING; + port_pfdena : STRING; + port_phasecounterselect : STRING; + port_phasedone : STRING; + port_phasestep : STRING; + port_phaseupdown : STRING; + port_pllena : STRING; + port_scanaclr : STRING; + port_scanclk : STRING; + port_scanclkena : STRING; + port_scandata : STRING; + port_scandataout : STRING; + port_scandone : STRING; + port_scanread : STRING; + port_scanwrite : STRING; + port_clk0 : STRING; + port_clk1 : STRING; + port_clk2 : STRING; + port_clk3 : STRING; + port_clk4 : STRING; + port_clk5 : STRING; + port_clkena0 : STRING; + port_clkena1 : STRING; + port_clkena2 : STRING; + port_clkena3 : STRING; + port_clkena4 : STRING; + port_clkena5 : STRING; + port_extclk0 : STRING; + port_extclk1 : STRING; + port_extclk2 : STRING; + port_extclk3 : STRING; + self_reset_on_loss_lock : STRING; + width_clock : NATURAL + ); + PORT ( + clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); + inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + locked : OUT STD_LOGIC + ); + END COMPONENT; + +BEGIN + sub_wire7_bv(0 DOWNTO 0) <= "0"; + sub_wire7 <= To_stdlogicvector(sub_wire7_bv); + sub_wire4 <= sub_wire0(2); + sub_wire3 <= sub_wire0(0); + sub_wire1 <= sub_wire0(1); + c1 <= sub_wire1; + locked <= sub_wire2; + c0 <= sub_wire3; + c2 <= sub_wire4; + sub_wire5 <= inclk0; + sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5; + + altpll_component : altpll + GENERIC MAP ( + bandwidth_type => "AUTO", + clk0_divide_by => 1, + clk0_duty_cycle => 50, + clk0_multiply_by => 2, + clk0_phase_shift => "0", + clk1_divide_by => 1, + clk1_duty_cycle => 50, + clk1_multiply_by => 2, + clk1_phase_shift => "-1500", + clk2_divide_by => 5, + clk2_duty_cycle => 50, + clk2_multiply_by => 1, + clk2_phase_shift => "0", + compensate_clock => "CLK0", + inclk0_input_frequency => 20000, + intended_device_family => "Cyclone IV E", + lpm_hint => "CBX_MODULE_PREFIX=pll_sys", + lpm_type => "altpll", + operation_mode => "NORMAL", + pll_type => "AUTO", + port_activeclock => "PORT_UNUSED", + port_areset => "PORT_UNUSED", + port_clkbad0 => "PORT_UNUSED", + port_clkbad1 => "PORT_UNUSED", + port_clkloss => "PORT_UNUSED", + port_clkswitch => "PORT_UNUSED", + port_configupdate => "PORT_UNUSED", + port_fbin => "PORT_UNUSED", + port_inclk0 => "PORT_USED", + port_inclk1 => "PORT_UNUSED", + port_locked => "PORT_USED", + port_pfdena => "PORT_UNUSED", + port_phasecounterselect => "PORT_UNUSED", + port_phasedone => "PORT_UNUSED", + port_phasestep => "PORT_UNUSED", + port_phaseupdown => "PORT_UNUSED", + port_pllena => "PORT_UNUSED", + port_scanaclr => "PORT_UNUSED", + port_scanclk => "PORT_UNUSED", + port_scanclkena => "PORT_UNUSED", + port_scandata => "PORT_UNUSED", + port_scandataout => "PORT_UNUSED", + port_scandone => "PORT_UNUSED", + port_scanread => "PORT_UNUSED", + port_scanwrite => "PORT_UNUSED", + port_clk0 => "PORT_USED", + port_clk1 => "PORT_USED", + port_clk2 => "PORT_USED", + port_clk3 => "PORT_UNUSED", + port_clk4 => "PORT_UNUSED", + port_clk5 => "PORT_UNUSED", + port_clkena0 => "PORT_UNUSED", + port_clkena1 => "PORT_UNUSED", + port_clkena2 => "PORT_UNUSED", + port_clkena3 => "PORT_UNUSED", + port_clkena4 => "PORT_UNUSED", + port_clkena5 => "PORT_UNUSED", + port_extclk0 => "PORT_UNUSED", + port_extclk1 => "PORT_UNUSED", + port_extclk2 => "PORT_UNUSED", + port_extclk3 => "PORT_UNUSED", + self_reset_on_loss_lock => "ON", + width_clock => 5 + ) + PORT MAP ( + inclk => sub_wire6, + clk => sub_wire0, + locked => sub_wire2 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" +-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1" +-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1" +-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "100.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "10.000000" +-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000" +-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg" +-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" +-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1" +-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1" +-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "10.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "-54.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg" +-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_sys.mif" +-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "1" +-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +-- Retrieval info: PRIVATE: SPREAD_USE STRING "0" +-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" +-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_CLK0 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK1 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK2 STRING "1" +-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" +-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1" +-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2" +-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1" +-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2" +-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "-1500" +-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "5" +-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "1" +-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "ON" +-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" +-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" +-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 +-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_sys.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_sys.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_sys.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_sys.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_sys.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_sys_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf +-- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/MCTEST/DE0-nano-HD/system.bsf b/MCTEST/DE0-nano-HD/system.bsf new file mode 100644 index 00000000..1b8557d0 --- /dev/null +++ b/MCTEST/DE0-nano-HD/system.bsf @@ -0,0 +1,216 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2012 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 320 584) + (text "system" (rect 139 -1 169 11)(font "Arial" (font_size 10))) + (text "inst" (rect 8 568 20 580)(font "Arial" )) + (port + (pt 0 72) + (input) + (text "clk_clk" (rect 0 0 27 12)(font "Arial" (font_size 8))) + (text "clk_clk" (rect 4 61 46 72)(font "Arial" (font_size 8))) + (line (pt 0 72)(pt 128 72)(line_width 1)) + ) + (port + (pt 0 112) + (input) + (text "reset_reset_n" (rect 0 0 56 12)(font "Arial" (font_size 8))) + (text "reset_reset_n" (rect 4 101 82 112)(font "Arial" (font_size 8))) + (line (pt 0 112)(pt 128 112)(line_width 1)) + ) + (port + (pt 0 320) + (input) + (text "uart_0_rxd" (rect 0 0 44 12)(font "Arial" (font_size 8))) + (text "uart_0_rxd" (rect 4 309 64 320)(font "Arial" (font_size 8))) + (line (pt 0 320)(pt 128 320)(line_width 1)) + ) + (port + (pt 0 416) + (input) + (text "pio_key_export[1..0]" (rect 0 0 81 12)(font "Arial" (font_size 8))) + (text "pio_key_export[1..0]" (rect 4 405 124 416)(font "Arial" (font_size 8))) + (line (pt 0 416)(pt 128 416)(line_width 3)) + ) + (port + (pt 0 456) + (input) + (text "pio_sw_export[3..0]" (rect 0 0 77 12)(font "Arial" (font_size 8))) + (text "pio_sw_export[3..0]" (rect 4 445 118 456)(font "Arial" (font_size 8))) + (line (pt 0 456)(pt 128 456)(line_width 3)) + ) + (port + (pt 0 536) + (input) + (text "rs232_motor_RXD" (rect 0 0 79 12)(font "Arial" (font_size 8))) + (text "rs232_motor_RXD" (rect 4 525 94 536)(font "Arial" (font_size 8))) + (line (pt 0 536)(pt 128 536)(line_width 1)) + ) + (port + (pt 0 152) + (output) + (text "sdram_addr[12..0]" (rect 0 0 73 12)(font "Arial" (font_size 8))) + (text "sdram_addr[12..0]" (rect 4 141 106 152)(font "Arial" (font_size 8))) + (line (pt 0 152)(pt 128 152)(line_width 3)) + ) + (port + (pt 0 168) + (output) + (text "sdram_ba[1..0]" (rect 0 0 60 12)(font "Arial" (font_size 8))) + (text "sdram_ba[1..0]" (rect 4 157 88 168)(font "Arial" (font_size 8))) + (line (pt 0 168)(pt 128 168)(line_width 3)) + ) + (port + (pt 0 184) + (output) + (text "sdram_cas_n" (rect 0 0 56 12)(font "Arial" (font_size 8))) + (text "sdram_cas_n" (rect 4 173 70 184)(font "Arial" (font_size 8))) + (line (pt 0 184)(pt 128 184)(line_width 1)) + ) + (port + (pt 0 200) + (output) + (text "sdram_cke" (rect 0 0 46 12)(font "Arial" (font_size 8))) + (text "sdram_cke" (rect 4 189 58 200)(font "Arial" (font_size 8))) + (line (pt 0 200)(pt 128 200)(line_width 1)) + ) + (port + (pt 0 216) + (output) + (text "sdram_cs_n" (rect 0 0 51 12)(font "Arial" (font_size 8))) + (text "sdram_cs_n" (rect 4 205 64 216)(font "Arial" (font_size 8))) + (line (pt 0 216)(pt 128 216)(line_width 1)) + ) + (port + (pt 0 248) + (output) + (text "sdram_dqm[1..0]" (rect 0 0 68 12)(font "Arial" (font_size 8))) + (text "sdram_dqm[1..0]" (rect 4 237 94 248)(font "Arial" (font_size 8))) + (line (pt 0 248)(pt 128 248)(line_width 3)) + ) + (port + (pt 0 264) + (output) + (text "sdram_ras_n" (rect 0 0 55 12)(font "Arial" (font_size 8))) + (text "sdram_ras_n" (rect 4 253 70 264)(font "Arial" (font_size 8))) + (line (pt 0 264)(pt 128 264)(line_width 1)) + ) + (port + (pt 0 280) + (output) + (text "sdram_we_n" (rect 0 0 53 12)(font "Arial" (font_size 8))) + (text "sdram_we_n" (rect 4 269 64 280)(font "Arial" (font_size 8))) + (line (pt 0 280)(pt 128 280)(line_width 1)) + ) + (port + (pt 0 336) + (output) + (text "uart_0_txd" (rect 0 0 43 12)(font "Arial" (font_size 8))) + (text "uart_0_txd" (rect 4 325 64 336)(font "Arial" (font_size 8))) + (line (pt 0 336)(pt 128 336)(line_width 1)) + ) + (port + (pt 0 376) + (output) + (text "pio_led_export[6..0]" (rect 0 0 77 12)(font "Arial" (font_size 8))) + (text "pio_led_export[6..0]" (rect 4 365 124 376)(font "Arial" (font_size 8))) + (line (pt 0 376)(pt 128 376)(line_width 3)) + ) + (port + (pt 0 496) + (output) + (text "pio_motor_rst_export" (rect 0 0 87 12)(font "Arial" (font_size 8))) + (text "pio_motor_rst_export" (rect 4 485 124 496)(font "Arial" (font_size 8))) + (line (pt 0 496)(pt 128 496)(line_width 1)) + ) + (port + (pt 0 552) + (output) + (text "rs232_motor_TXD" (rect 0 0 76 12)(font "Arial" (font_size 8))) + (text "rs232_motor_TXD" (rect 4 541 94 552)(font "Arial" (font_size 8))) + (line (pt 0 552)(pt 128 552)(line_width 1)) + ) + (port + (pt 0 232) + (bidir) + (text "sdram_dq[15..0]" (rect 0 0 64 12)(font "Arial" (font_size 8))) + (text "sdram_dq[15..0]" (rect 4 221 94 232)(font "Arial" (font_size 8))) + (line (pt 0 232)(pt 128 232)(line_width 3)) + ) + (drawing + (text "clk" (rect 113 43 244 99)(font "Arial" (color 128 0 0)(font_size 9))) + (text "clk" (rect 133 67 284 144)(font "Arial" (color 0 0 0))) + (text "reset" (rect 99 83 228 179)(font "Arial" (color 128 0 0)(font_size 9))) + (text "reset_n" (rect 133 107 308 224)(font "Arial" (color 0 0 0))) + (text "sdram" (rect 92 123 214 259)(font "Arial" (color 128 0 0)(font_size 9))) + (text "addr" (rect 133 147 290 304)(font "Arial" (color 0 0 0))) + (text "ba" (rect 133 163 278 336)(font "Arial" (color 0 0 0))) + (text "cas_n" (rect 133 179 296 368)(font "Arial" (color 0 0 0))) + (text "cke" (rect 133 195 284 400)(font "Arial" (color 0 0 0))) + (text "cs_n" (rect 133 211 290 432)(font "Arial" (color 0 0 0))) + (text "dq" (rect 133 227 278 464)(font "Arial" (color 0 0 0))) + (text "dqm" (rect 133 243 284 496)(font "Arial" (color 0 0 0))) + (text "ras_n" (rect 133 259 296 528)(font "Arial" (color 0 0 0))) + (text "we_n" (rect 133 275 290 560)(font "Arial" (color 0 0 0))) + (text "uart_0" (rect 91 291 218 595)(font "Arial" (color 128 0 0)(font_size 9))) + (text "rxd" (rect 133 315 284 640)(font "Arial" (color 0 0 0))) + (text "txd" (rect 133 331 284 672)(font "Arial" (color 0 0 0))) + (text "pio_led" (rect 87 347 216 707)(font "Arial" (color 128 0 0)(font_size 9))) + (text "export" (rect 133 371 302 752)(font "Arial" (color 0 0 0))) + (text "pio_key" (rect 84 387 210 787)(font "Arial" (color 128 0 0)(font_size 9))) + (text "export" (rect 133 411 302 832)(font "Arial" (color 0 0 0))) + (text "pio_sw" (rect 87 427 210 867)(font "Arial" (color 128 0 0)(font_size 9))) + (text "export" (rect 133 451 302 912)(font "Arial" (color 0 0 0))) + (text "pio_motor_rst" (rect 46 467 170 947)(font "Arial" (color 128 0 0)(font_size 9))) + (text "export" (rect 133 491 302 992)(font "Arial" (color 0 0 0))) + (text "rs232_motor" (rect 54 507 174 1027)(font "Arial" (color 128 0 0)(font_size 9))) + (text "RXD" (rect 133 531 284 1072)(font "Arial" (color 0 0 0))) + (text "TXD" (rect 133 547 284 1104)(font "Arial" (color 0 0 0))) + (text " system " (rect 285 568 618 1146)(font "Arial" )) + (line (pt 129 52)(pt 129 76)(line_width 1)) + (line (pt 130 52)(pt 130 76)(line_width 1)) + (line (pt 129 92)(pt 129 116)(line_width 1)) + (line (pt 130 92)(pt 130 116)(line_width 1)) + (line (pt 129 132)(pt 129 284)(line_width 1)) + (line (pt 130 132)(pt 130 284)(line_width 1)) + (line (pt 129 300)(pt 129 340)(line_width 1)) + (line (pt 130 300)(pt 130 340)(line_width 1)) + (line (pt 129 356)(pt 129 380)(line_width 1)) + (line (pt 130 356)(pt 130 380)(line_width 1)) + (line (pt 129 396)(pt 129 420)(line_width 1)) + (line (pt 130 396)(pt 130 420)(line_width 1)) + (line (pt 129 436)(pt 129 460)(line_width 1)) + (line (pt 130 436)(pt 130 460)(line_width 1)) + (line (pt 129 476)(pt 129 500)(line_width 1)) + (line (pt 130 476)(pt 130 500)(line_width 1)) + (line (pt 129 516)(pt 129 556)(line_width 1)) + (line (pt 130 516)(pt 130 556)(line_width 1)) + (line (pt 128 32)(pt 192 32)(line_width 1)) + (line (pt 192 32)(pt 192 568)(line_width 1)) + (line (pt 128 568)(pt 192 568)(line_width 1)) + (line (pt 128 32)(pt 128 568)(line_width 1)) + (line (pt 0 0)(pt 320 0)(line_width 1)) + (line (pt 320 0)(pt 320 584)(line_width 1)) + (line (pt 0 584)(pt 320 584)(line_width 1)) + (line (pt 0 0)(pt 0 584)(line_width 1)) + ) +) diff --git a/MCTEST/DE0-nano-HD/system.cmp b/MCTEST/DE0-nano-HD/system.cmp new file mode 100644 index 00000000..d4cfdf72 --- /dev/null +++ b/MCTEST/DE0-nano-HD/system.cmp @@ -0,0 +1,24 @@ + component system is + port ( + clk_clk : in std_logic := 'X'; -- clk + reset_reset_n : in std_logic := 'X'; -- reset_n + sdram_addr : out std_logic_vector(12 downto 0); -- addr + sdram_ba : out std_logic_vector(1 downto 0); -- ba + sdram_cas_n : out std_logic; -- cas_n + sdram_cke : out std_logic; -- cke + sdram_cs_n : out std_logic; -- cs_n + sdram_dq : inout std_logic_vector(15 downto 0) := (others => 'X'); -- dq + sdram_dqm : out std_logic_vector(1 downto 0); -- dqm + sdram_ras_n : out std_logic; -- ras_n + sdram_we_n : out std_logic; -- we_n + uart_0_rxd : in std_logic := 'X'; -- rxd + uart_0_txd : out std_logic; -- txd + pio_led_export : out std_logic_vector(6 downto 0); -- export + pio_key_export : in std_logic_vector(1 downto 0) := (others => 'X'); -- export + pio_sw_export : in std_logic_vector(3 downto 0) := (others => 'X'); -- export + pio_motor_rst_export : out std_logic; -- export + rs232_motor_RXD : in std_logic := 'X'; -- RXD + rs232_motor_TXD : out std_logic -- TXD + ); + end component system; + diff --git a/MCTEST/DE0-nano-HD/system.html b/MCTEST/DE0-nano-HD/system.html new file mode 100644 index 00000000..29733bf5 --- /dev/null +++ b/MCTEST/DE0-nano-HD/system.html @@ -0,0 +1,2950 @@ + + + + + datasheet for system + + + + + + + + +
system +
+
+
+ + + + + +
2014.03.06.09:42:55Datasheet
+
+
Overview
+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
  clk_sys system
   + uart_0 + +
 rxd  
 txd  
 out_port  
 in_port  
 in_port  
 out_port  
+
+
Processor +
   + cpu + Nios II 12.1 +
All Components +
   + cpu + altera_nios2_qsys 12.1 +
   + sysid + altera_avalon_sysid_qsys 12.1 +
   + sdram + altera_avalon_new_sdram_controller 12.1 +
   + sys_clk_timer + altera_avalon_timer 12.1 +
   + uart_0 + altera_avalon_uart 12.1 +
   + pio_led + altera_avalon_pio 12.1 +
   + pio_key + altera_avalon_pio 12.1 +
   + pio_sw + altera_avalon_pio 12.1 +
   + jtag_uart_0 + altera_avalon_jtag_uart 12.1 +
   + pio_motor_rst + altera_avalon_pio 12.1 +
   + rs232_motor + altera_up_avalon_rs232 12.0 +
+
+
+
Memory Map
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ cpu + +
 data_master instruction_master
  + cpu + +
jtag_debug_module 0x020008000x02000800
  + sysid + +
control_slave 0x020010a0
  + sdram + +
s1 0x010000000x01000000
  + sys_clk_timer + +
s1 0x02001040
  + uart_0 + +
s1 0x02001020
  + pio_led + +
s1 0x02001000
  + pio_key + +
s1 0x02001080
  + pio_sw + +
s1 0x02001070
  + jtag_uart_0 + +
avalon_jtag_slave 0x02001098
  + pio_motor_rst + +
s1 0x02001060
  + rs232_motor + +
avalon_rs232_slave 0x02001090
+ +
+
+

clk_sys

clock_source v12.1 +
+
+
+ + + + +
+

Parameters

+ + + + + + + + + + + + + + + + + + + + + + + + + +
clockFrequency100000000
clockFrequencyKnowntrue
inputClockFrequency0
resetSynchronousEdgesDEASSERT
deviceFamilyUNKNOWN
generateLegacySimfalse
+
   + + + + +
+

Software Assignments

(none)
+
+ +
+
+

cpu

altera_nios2_qsys v12.1 +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ clk_sys + clk_reset  cpu
  reset_n
clk  
  clk
jtag_debug_module_reset   + sysid +
  reset
data_master  
  control_slave
jtag_debug_module_reset   + sdram +
  reset
data_master  
  s1
instruction_master  
  s1
jtag_debug_module_reset   + sys_clk_timer +
  reset
data_master  
  s1
d_irq  
  irq
jtag_debug_module_reset   + uart_0 +
  reset
data_master  
  s1
d_irq  
  irq
jtag_debug_module_reset   + pio_led +
  reset
data_master  
  s1
jtag_debug_module_reset   + pio_key +
  reset
data_master  
  s1
jtag_debug_module_reset   + pio_sw +
  reset
data_master  
  s1
d_irq   + jtag_uart_0 +
  irq
data_master  
  avalon_jtag_slave
jtag_debug_module_reset  
  reset
jtag_debug_module_reset   + pio_motor_rst +
  reset
data_master  
  s1
jtag_debug_module_reset   + rs232_motor +
  clock_reset_reset
data_master  
  avalon_rs232_slave
d_irq  
  interrupt
+
+
+
+ + + + +
+

Parameters

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
setting_showUnpublishedSettingsfalse
setting_showInternalSettingsfalse
setting_preciseSlaveAccessErrorExceptionfalse
setting_preciseIllegalMemAccessExceptionfalse
setting_preciseDivisionErrorExceptionfalse
setting_performanceCounterfalse
setting_illegalMemAccessDetectionfalse
setting_illegalInstructionsTrapfalse
setting_fullWaveformSignalsfalse
setting_extraExceptionInfofalse
setting_exportPCBfalse
setting_debugSimGenfalse
setting_clearXBitsLDNonBypasstrue
setting_bit31BypassDCachetrue
setting_bigEndianfalse
setting_export_large_RAMsfalse
setting_asic_enabledfalse
setting_asic_synopsys_translate_on_offfalse
setting_oci_export_jtag_signalsfalse
setting_bhtIndexPcOnlyfalse
setting_avalonDebugPortPresentfalse
setting_alwaysEncrypttrue
setting_allowFullAddressRangefalse
setting_activateTracetrue
setting_activateTestEndCheckerfalse
setting_activateMonitorstrue
setting_activateModelCheckerfalse
setting_HDLSimCachesClearedtrue
setting_HBreakTestfalse
muldiv_dividerfalse
mpu_useLimitfalse
mpu_enabledfalse
mmu_enabledfalse
mmu_autoAssignTlbPtrSztrue
manuallyAssignCpuIDtrue
debug_triggerArmingtrue
debug_embeddedPLLtrue
debug_debugReqSignalsfalse
debug_assignJtagInstanceIDfalse
dcache_omitDataMasterfalse
cpuResetfalse
is_hardcopy_compatiblefalse
setting_shadowRegisterSets0
mpu_numOfInstRegion8
mpu_numOfDataRegion8
mmu_TLBMissExcOffset0
debug_jtagInstanceID0
resetOffset0
exceptionOffset32
cpuID0
cpuID_stored0
breakOffset32
userDefinedSettings
resetSlavesdram.s1
mmu_TLBMissExcSlave
exceptionSlavesdram.s1
breakSlavecpu.jtag_debug_module
setting_perfCounterWidth32
setting_interruptControllerTypeInternal
setting_branchPredictionTypeAutomatic
setting_bhtPtrSz8
muldiv_multiplierTypeEmbeddedMulFast
mpu_minInstRegionSize12
mpu_minDataRegionSize12
mmu_uitlbNumEntries4
mmu_udtlbNumEntries6
mmu_tlbPtrSz7
mmu_tlbNumWays16
mmu_processIDNumBits8
implFast
icache_size8192
icache_ramBlockTypeAutomatic
icache_numTCIM0
icache_burstTypeNone
dcache_burstsfalse
debug_levelLevel1
debug_OCIOnchipTrace_128
dcache_size4096
dcache_ramBlockTypeAutomatic
dcache_numTCDM0
dcache_lineSize32
regfile_ramBlockTypeAutomatic
mmu_ramBlockTypeAutomatic
bht_ramBlockTypeAutomatic
resetAbsoluteAddr16777216
exceptionAbsoluteAddr16777248
breakAbsoluteAddr33556512
mmu_TLBMissExcAbsAddr0
translate_on "synthesis translate_on"
translate_off "synthesis translate_off"
instAddrWidth26
dataAddrWidth26
tightlyCoupledDataMaster0AddrWidth1
tightlyCoupledDataMaster1AddrWidth1
tightlyCoupledDataMaster2AddrWidth1
tightlyCoupledDataMaster3AddrWidth1
tightlyCoupledInstructionMaster0AddrWidth1
tightlyCoupledInstructionMaster1AddrWidth1
tightlyCoupledInstructionMaster2AddrWidth1
tightlyCoupledInstructionMaster3AddrWidth1
instSlaveMapParam<address-map><slave name='sdram.s1' start='0x1000000' end='0x2000000' /><slave name='cpu.jtag_debug_module' start='0x2000800' end='0x2001000' /></address-map>
dataSlaveMapParam<address-map><slave name='sdram.s1' start='0x1000000' end='0x2000000' /><slave name='cpu.jtag_debug_module' start='0x2000800' end='0x2001000' /><slave name='pio_led.s1' start='0x2001000' end='0x2001020' /><slave name='uart_0.s1' start='0x2001020' end='0x2001040' /><slave name='sys_clk_timer.s1' start='0x2001040' end='0x2001060' /><slave name='pio_motor_rst.s1' start='0x2001060' end='0x2001070' /><slave name='pio_sw.s1' start='0x2001070' end='0x2001080' /><slave name='pio_key.s1' start='0x2001080' end='0x2001090' /><slave name='rs232_motor.avalon_rs232_slave' start='0x2001090' end='0x2001098' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x2001098' end='0x20010A0' /><slave name='sysid.control_slave' start='0x20010A0' end='0x20010A8' /></address-map>
clockFrequency100000000
deviceFamilyNameCYCLONEIVE
internalIrqMaskSystemInfo16434
customInstSlavesSystemInfo<info/>
deviceFeaturesSystemInfoNOT_LISTED 0 INSTALLED 1 IS_DEFAULT_FAMILY 0 ADDRESS_STALL 1 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FITTER_USE_FALLING_EDGE_DELAY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 1 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 1 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_EARLY_TIMING_ESTIMATE_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 0 HAS_IBISO_WRITER_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 1 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 IS_CONFIG_ROM 0 IS_HARDCOPY_FAMILY 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_SUPPORT 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1
tightlyCoupledDataMaster0MapParam
tightlyCoupledDataMaster1MapParam
tightlyCoupledDataMaster2MapParam
tightlyCoupledDataMaster3MapParam
tightlyCoupledInstructionMaster0MapParam
tightlyCoupledInstructionMaster1MapParam
tightlyCoupledInstructionMaster2MapParam
tightlyCoupledInstructionMaster3MapParam
deviceFamilyUNKNOWN
generateLegacySimfalse
+
   + + + + +
+

Software Assignments

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BIG_ENDIAN0
BREAK_ADDR0x02000820
CPU_FREQ100000000u
CPU_ID_SIZE1
CPU_ID_VALUE0x00000000
CPU_IMPLEMENTATION"fast"
DATA_ADDR_WIDTH26
DCACHE_LINE_SIZE32
DCACHE_LINE_SIZE_LOG25
DCACHE_SIZE4096
EXCEPTION_ADDR0x01000020
FLUSHDA_SUPPORTED
HARDWARE_DIVIDE_PRESENT0
HARDWARE_MULTIPLY_PRESENT1
HARDWARE_MULX_PRESENT0
HAS_DEBUG_CORE1
HAS_DEBUG_STUB
HAS_JMPI_INSTRUCTION
ICACHE_LINE_SIZE32
ICACHE_LINE_SIZE_LOG25
ICACHE_SIZE8192
INITDA_SUPPORTED
INST_ADDR_WIDTH26
NUM_OF_SHADOW_REG_SETS0
RESET_ADDR0x01000000
+
+
+ +
+
+

sysid

altera_avalon_sysid_qsys v12.1 +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ clk_sys + clk_reset  sysid
  reset
clk  
  clk
+ cpu + jtag_debug_module_reset  
  reset
data_master  
  control_slave
+
+
+
+ + + + +
+

Parameters

+ + + + + + + + + + + + + + + + + + + + + + + + + +
id0
timestamp1394124174
AUTO_CLK_CLOCK_RATE100000000
AUTO_DEVICE_FAMILYCYCLONEIVE
deviceFamilyCyclone IV E
generateLegacySimfalse
+
   + + + + +
+

Software Assignments

+ + + + + + + + + +
ID0
TIMESTAMP1394124174
+
+
+ +
+
+

sdram

altera_avalon_new_sdram_controller v12.1 +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ clk_sys + clk_reset  sdram
  reset
clk  
  clk
+ cpu + jtag_debug_module_reset  
  reset
data_master  
  s1
instruction_master  
  s1
+
+
+
+ + + + +
+

Parameters

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
TAC5.5
TMRD3
TRCD20.0
TRFC70.0
TRP20.0
TWR14.0
casLatency3
clockRate100000000
columnWidth8
dataWidth16
generateSimulationModelfalse
initNOPDelay0.0
initRefreshCommands8
masteredTristateBridgeSlave
modelcustom
numberOfBanks4
numberOfChipSelects1
pinsSharedViaTriStatefalse
powerUpDelay200.0
refreshPeriod7.8125
registerDataIntrue
rowWidth13
size16777216
deviceFamilyUNKNOWN
generateLegacySimfalse
+
   + + + + +
+

Software Assignments

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
REGISTER_DATA_IN1
SIM_MODEL_BASE0
SDRAM_DATA_WIDTH16
SDRAM_ADDR_WIDTH23
SDRAM_ROW_WIDTH13
SDRAM_COL_WIDTH8
SDRAM_NUM_CHIPSELECTS1
SDRAM_NUM_BANKS4
REFRESH_PERIOD7.8125
POWERUP_DELAY200.0
CAS_LATENCY3
T_RFC70.0
T_RP20.0
T_MRD3
T_RCD20.0
T_AC5.5
T_WR14.0
INIT_REFRESH_COMMANDS8
INIT_NOP_DELAY0.0
SHARED_DATA0
STARVATION_INDICATOR0
TRISTATE_BRIDGE_SLAVE""
IS_INITIALIZED1
SDRAM_BANK_WIDTH2
CONTENTS_INFO""
+
+
+ +
+
+

sys_clk_timer

altera_avalon_timer v12.1 +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ clk_sys + clk_reset  sys_clk_timer
  reset
clk  
  clk
+ cpu + jtag_debug_module_reset  
  reset
data_master  
  s1
d_irq  
  irq
+
+
+
+ + + + +
+

Parameters

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
alwaysRunfalse
counterSize32
fixedPeriodfalse
period1
periodUnitsMSEC
resetOutputfalse
snapshottrue
systemFrequency100000000
timeoutPulseOutputfalse
timerPresetCUSTOM
deviceFamilyUNKNOWN
generateLegacySimfalse
+
   + + + + +
+

Software Assignments

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
ALWAYS_RUN0
FIXED_PERIOD0
SNAPSHOT1
PERIOD1
PERIOD_UNITS"ms"
RESET_OUTPUT0
TIMEOUT_PULSE_OUTPUT0
FREQ100000000u
LOAD_VALUE99999ULL
COUNTER_SIZE32
MULT0.0010
TICKS_PER_SEC1000u
+
+
+ +
+
+

uart_0

altera_avalon_uart v12.1 +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ clk_sys + clk_reset  uart_0
  reset
clk  
  clk
+ cpu + jtag_debug_module_reset  
  reset
data_master  
  s1
d_irq  
  irq
+
+
+
+ + + + +
+

Parameters

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
baud115200
baudError0.01
clockRate100000000
dataBits8
fixedBaudfalse
parityNONE
simCharStream
simInteractiveInputEnablefalse
simInteractiveOutputEnablefalse
simTrueBaudfalse
stopBits1
syncRegDepth2
useCtsRtsfalse
useEopRegisterfalse
useRelativePathForSimFilefalse
deviceFamilyUNKNOWN
generateLegacySimfalse
+
   + + + + +
+

Software Assignments

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BAUD115200
DATA_BITS8
FIXED_BAUD0
PARITY'N'
STOP_BITS1
SYNC_REG_DEPTH2
USE_CTS_RTS0
USE_EOP_REGISTER0
SIM_TRUE_BAUD0
SIM_CHAR_STREAM""
FREQ100000000u
+
+
+ +
+
+

pio_led

altera_avalon_pio v12.1 +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ clk_sys + clk_reset  pio_led
  reset
clk  
  clk
+ cpu + jtag_debug_module_reset  
  reset
data_master  
  s1
+
+
+
+ + + + +
+

Parameters

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
bitClearingEdgeCapRegfalse
bitModifyingOutRegtrue
captureEdgefalse
clockRate100000000
directionOutput
edgeTypeRISING
generateIRQfalse
irqTypeLEVEL
resetValue0
simDoTestBenchWiringfalse
simDrivenValue0
width7
deviceFamilyUNKNOWN
generateLegacySimfalse
+
   + + + + +
+

Software Assignments

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
DO_TEST_BENCH_WIRING0
DRIVEN_SIM_VALUE0x0
HAS_TRI0
HAS_OUT1
HAS_IN0
CAPTURE0
BIT_CLEARING_EDGE_REGISTER0
BIT_MODIFYING_OUTPUT_REGISTER1
DATA_WIDTH7
RESET_VALUE0x0
EDGE_TYPE"NONE"
IRQ_TYPE"NONE"
FREQ100000000u
+
+
+ +
+
+

pio_key

altera_avalon_pio v12.1 +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ clk_sys + clk_reset  pio_key
  reset
clk  
  clk
+ cpu + jtag_debug_module_reset  
  reset
data_master  
  s1
+
+
+
+ + + + +
+

Parameters

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
bitClearingEdgeCapRegfalse
bitModifyingOutRegfalse
captureEdgefalse
clockRate100000000
directionInput
edgeTypeRISING
generateIRQfalse
irqTypeLEVEL
resetValue0
simDoTestBenchWiringfalse
simDrivenValue0
width2
deviceFamilyUNKNOWN
generateLegacySimfalse
+
   + + + + +
+

Software Assignments

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
DO_TEST_BENCH_WIRING0
DRIVEN_SIM_VALUE0x0
HAS_TRI0
HAS_OUT0
HAS_IN1
CAPTURE0
BIT_CLEARING_EDGE_REGISTER0
BIT_MODIFYING_OUTPUT_REGISTER0
DATA_WIDTH2
RESET_VALUE0x0
EDGE_TYPE"NONE"
IRQ_TYPE"NONE"
FREQ100000000u
+
+
+ +
+
+

pio_sw

altera_avalon_pio v12.1 +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ clk_sys + clk_reset  pio_sw
  reset
clk  
  clk
+ cpu + jtag_debug_module_reset  
  reset
data_master  
  s1
+
+
+
+ + + + +
+

Parameters

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
bitClearingEdgeCapRegfalse
bitModifyingOutRegfalse
captureEdgefalse
clockRate100000000
directionInput
edgeTypeRISING
generateIRQfalse
irqTypeLEVEL
resetValue0
simDoTestBenchWiringfalse
simDrivenValue0
width4
deviceFamilyUNKNOWN
generateLegacySimfalse
+
   + + + + +
+

Software Assignments

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
DO_TEST_BENCH_WIRING0
DRIVEN_SIM_VALUE0x0
HAS_TRI0
HAS_OUT0
HAS_IN1
CAPTURE0
BIT_CLEARING_EDGE_REGISTER0
BIT_MODIFYING_OUTPUT_REGISTER0
DATA_WIDTH4
RESET_VALUE0x0
EDGE_TYPE"NONE"
IRQ_TYPE"NONE"
FREQ100000000u
+
+
+ +
+
+

jtag_uart_0

altera_avalon_jtag_uart v12.1 +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ clk_sys + clk  jtag_uart_0
  clk
clk_reset  
  reset
+ cpu + d_irq  
  irq
data_master  
  avalon_jtag_slave
jtag_debug_module_reset  
  reset
+
+
+
+ + + + +
+

Parameters

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
allowMultipleConnectionsfalse
avalonSpec2.0
hubInstanceID0
legacySignalAllowfalse
readBufferDepth64
readIRQThreshold8
simInputCharacterStream
simInteractiveOptionsINTERACTIVE_INPUT_OUTPUT
useRegistersForReadBufferfalse
useRegistersForWriteBufferfalse
useRelativePathForSimFilefalse
writeBufferDepth64
writeIRQThreshold8
deviceFamilyUNKNOWN
generateLegacySimfalse
+
   + + + + +
+

Software Assignments

+ + + + + + + + + + + + + + + + + +
WRITE_DEPTH64
READ_DEPTH64
WRITE_THRESHOLD8
READ_THRESHOLD8
+
+
+ +
+
+

pio_motor_rst

altera_avalon_pio v12.1 +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ clk_sys + clk_reset  pio_motor_rst
  reset
clk  
  clk
+ cpu + jtag_debug_module_reset  
  reset
data_master  
  s1
+
+
+
+ + + + +
+

Parameters

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
bitClearingEdgeCapRegfalse
bitModifyingOutRegfalse
captureEdgefalse
clockRate100000000
directionOutput
edgeTypeRISING
generateIRQfalse
irqTypeLEVEL
resetValue0
simDoTestBenchWiringfalse
simDrivenValue0
width1
deviceFamilyUNKNOWN
generateLegacySimfalse
+
   + + + + +
+

Software Assignments

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
DO_TEST_BENCH_WIRING0
DRIVEN_SIM_VALUE0x0
HAS_TRI0
HAS_OUT1
HAS_IN0
CAPTURE0
BIT_CLEARING_EDGE_REGISTER0
BIT_MODIFYING_OUTPUT_REGISTER0
DATA_WIDTH1
RESET_VALUE0x0
EDGE_TYPE"NONE"
IRQ_TYPE"NONE"
FREQ100000000u
+
+
+ +
+
+

rs232_motor

altera_up_avalon_rs232 v12.0 +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ clk_sys + clk_reset  rs232_motor
  clock_reset_reset
clk  
  clock_reset
+ cpu + jtag_debug_module_reset  
  clock_reset_reset
data_master  
  avalon_rs232_slave
d_irq  
  interrupt
+
+
+
+ + + + +
+

Parameters

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
avalon_bus_typeMemory Mapped
clk_rate100000000
baud9600
parityNone
data_bits8
stop_bits1
AUTO_CLOCK_RESET_CLOCK_RATE100000000
AUTO_DEVICE_FAMILYCYCLONEIVE
deviceFamilyCyclone IV E
generateLegacySimfalse
+
   + + + + +
+

Software Assignments

(none)
+
+ + + + + +
generation took 0.00 secondsrendering took 0.11 seconds
+ + diff --git a/MCTEST/DE0-nano-HD/system.qsys b/MCTEST/DE0-nano-HD/system.qsys new file mode 100644 index 00000000..b08c4192 --- /dev/null +++ b/MCTEST/DE0-nano-HD/system.qsys @@ -0,0 +1,780 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + cpu.jtag_debug_module + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ]]> + ]]> + + + + + NOT_LISTED 0 INSTALLED 1 IS_DEFAULT_FAMILY 0 ADDRESS_STALL 1 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FITTER_USE_FALLING_EDGE_DELAY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 1 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 1 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_EARLY_TIMING_ESTIMATE_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 0 HAS_IBISO_WRITER_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 1 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 IS_CONFIG_ROM 0 IS_HARDCOPY_FAMILY 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_SUPPORT 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + INTERACTIVE_INPUT_OUTPUT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/MCTEST/DE0-nano-HD/system.sopcinfo b/MCTEST/DE0-nano-HD/system.sopcinfo new file mode 100644 index 00000000..1a5303d6 --- /dev/null +++ b/MCTEST/DE0-nano-HD/system.sopcinfo @@ -0,0 +1,11520 @@ + + + + + + + java.lang.Integer + 1394124174 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + CYCLONEIVE + false + true + false + true + + + java.lang.String + EP4CE22F17C6 + false + true + false + true + + + java.lang.Long + -1 + false + true + false + true + + + java.lang.Integer + -1 + false + true + false + true + + + java.lang.Integer + -1 + false + true + false + true + + + java.lang.String + Cyclone IV E + false + true + false + true + + + boolean + false + false + true + true + true + + + + + long + 100000000 + false + true + true + true + + + boolean + true + false + true + true + true + + + long + 0 + false + true + false + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + qsys.ui.export_name + clk + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.Boolean + true + true + true + false + true + + + java.lang.Long + 100000000 + true + true + false + true + + clock + false + + in_clk + Input + 1 + clk + + + + + + qsys.ui.export_name + reset + + + java.lang.String + clk_in + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + reset_n + Input + 1 + reset_n + + + + + + java.lang.String + clk_in + false + true + true + true + + + long + 100000000 + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + true + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + true + + clk_out + Output + 1 + clk + + + false + cpu + clk + cpu.clk + + + false + sysid + clk + sysid.clk + + + false + sdram + clk + sdram.clk + + + false + sys_clk_timer + clk + sys_clk_timer.clk + + + false + uart_0 + clk + uart_0.clk + + + false + pio_led + clk + pio_led.clk + + + false + pio_key + clk + pio_key.clk + + + false + pio_sw + clk + pio_sw.clk + + + false + jtag_uart_0 + clk + jtag_uart_0.clk + + + false + pio_motor_rst + clk + pio_motor_rst.clk + + + false + rs232_motor + clock_reset + rs232_motor.clock_reset + + + + + + java.lang.String + clk + false + true + true + true + + + java.lang.String + clk_in_reset + false + true + true + true + + + [Ljava.lang.String; + clk_in_reset + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + true + + reset_n_out + Output + 1 + reset_n + + + + + + + debug.hostConnection + type jtag id 70:34|110:135 + + + embeddedsw.CMacro.BIG_ENDIAN + 0 + + + embeddedsw.CMacro.BREAK_ADDR + 0x02000820 + + + embeddedsw.CMacro.CPU_FREQ + 100000000u + + + embeddedsw.CMacro.CPU_ID_SIZE + 1 + + + embeddedsw.CMacro.CPU_ID_VALUE + 0x00000000 + + + embeddedsw.CMacro.CPU_IMPLEMENTATION + "fast" + + + embeddedsw.CMacro.DATA_ADDR_WIDTH + 26 + + + embeddedsw.CMacro.DCACHE_LINE_SIZE + 32 + + + embeddedsw.CMacro.DCACHE_LINE_SIZE_LOG2 + 5 + + + embeddedsw.CMacro.DCACHE_SIZE + 4096 + + + embeddedsw.CMacro.EXCEPTION_ADDR + 0x01000020 + + + embeddedsw.CMacro.FLUSHDA_SUPPORTED + + + + embeddedsw.CMacro.HARDWARE_DIVIDE_PRESENT + 0 + + + embeddedsw.CMacro.HARDWARE_MULTIPLY_PRESENT + 1 + + + embeddedsw.CMacro.HARDWARE_MULX_PRESENT + 0 + + + embeddedsw.CMacro.HAS_DEBUG_CORE + 1 + + + embeddedsw.CMacro.HAS_DEBUG_STUB + + + + embeddedsw.CMacro.HAS_JMPI_INSTRUCTION + + + + embeddedsw.CMacro.ICACHE_LINE_SIZE + 32 + + + embeddedsw.CMacro.ICACHE_LINE_SIZE_LOG2 + 5 + + + embeddedsw.CMacro.ICACHE_SIZE + 8192 + + + embeddedsw.CMacro.INITDA_SUPPORTED + + + + embeddedsw.CMacro.INST_ADDR_WIDTH + 26 + + + embeddedsw.CMacro.NUM_OF_SHADOW_REG_SETS + 0 + + + embeddedsw.CMacro.RESET_ADDR + 0x01000000 + + + embeddedsw.configuration.HDLSimCachesCleared + 1 + + + embeddedsw.configuration.breakOffset + 32 + + + embeddedsw.configuration.breakSlave + cpu.jtag_debug_module + + + embeddedsw.configuration.cpuArchitecture + Nios II + + + embeddedsw.configuration.exceptionOffset + 32 + + + embeddedsw.configuration.exceptionSlave + sdram.s1 + + + embeddedsw.configuration.resetOffset + 0 + + + embeddedsw.configuration.resetSlave + sdram.s1 + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + boolean + false + false + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + boolean + false + false + false + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + true + false + false + true + true + + + boolean + true + false + true + true + true + + + boolean + true + false + true + false + true + + + boolean + true + false + false + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 8 + false + false + true + true + + + int + 8 + false + false + true + true + + + int + 0 + false + false + true + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 32 + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + false + true + + + int + 32 + false + false + true + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + sdram.s1 + false + true + true + true + + + java.lang.String + + false + false + true + true + + + java.lang.String + sdram.s1 + false + true + true + true + + + java.lang.String + cpu.jtag_debug_module + false + false + true + true + + + int + 32 + false + true + false + true + + + java.lang.String + Internal + false + true + true + true + + + java.lang.String + Automatic + false + true + false + true + + + int + 8 + false + true + false + true + + + java.lang.String + EmbeddedMulFast + false + true + true + true + + + int + 12 + false + false + true + true + + + int + 12 + false + false + true + true + + + int + 4 + false + false + true + true + + + int + 6 + false + false + true + true + + + int + 7 + false + false + true + true + + + int + 16 + false + false + true + true + + + int + 8 + false + false + true + true + + + java.lang.String + Fast + false + true + true + true + + + int + 8192 + false + true + true + true + + + java.lang.String + Automatic + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + None + false + true + true + true + + + java.lang.String + false + false + true + true + true + + + java.lang.String + Level1 + false + true + true + true + + + java.lang.String + _128 + false + false + true + true + + + int + 4096 + false + true + true + true + + + java.lang.String + Automatic + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 32 + false + true + true + true + + + java.lang.String + Automatic + false + true + false + true + + + java.lang.String + Automatic + false + true + false + true + + + java.lang.String + Automatic + false + true + false + true + + + int + 16777216 + true + true + true + true + + + int + 16777248 + true + true + true + true + + + int + 33556512 + true + true + true + true + + + int + 0 + true + true + true + true + + + java.lang.String + "synthesis translate_on" + true + true + false + true + + + java.lang.String + "synthesis translate_off" + true + true + false + true + + + int + 26 + false + true + false + true + + + int + 26 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + false + true + + + java.lang.String + ]]> + false + true + false + true + + + java.lang.String + ]]> + false + true + false + true + + + long + 100000000 + false + true + false + true + + + java.lang.String + CYCLONEIVE + false + true + false + true + + + long + 16434 + false + true + false + true + + + java.lang.String + ]]> + false + true + false + true + + + java.lang.String + NOT_LISTED 0 INSTALLED 1 IS_DEFAULT_FAMILY 0 ADDRESS_STALL 1 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FITTER_USE_FALLING_EDGE_DELAY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 1 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 1 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_EARLY_TIMING_ESTIMATE_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 0 HAS_IBISO_WRITER_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 1 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 IS_CONFIG_ROM 0 IS_HARDCOPY_FAMILY 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_SUPPORT 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.Boolean + true + true + true + false + true + + + java.lang.Long + 100000000 + true + true + false + true + + clock + false + + clk + Input + 1 + clk + + + + + + java.lang.String + clk + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + reset_n + Input + 1 + reset_n + + + + + + debug.providesServices + master + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + int + 1 + false + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + SYMBOLS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + true + true + + + java.lang.String + reset_n + false + true + true + true + + + int + 8 + false + true + true + true + + + boolean + true + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 32 + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + true + + d_address + Output + 26 + address + + + d_byteenable + Output + 4 + byteenable + + + d_read + Output + 1 + read + + + d_readdata + Input + 32 + readdata + + + d_waitrequest + Input + 1 + waitrequest + + + d_write + Output + 1 + write + + + d_writedata + Output + 32 + writedata + + + d_readdatavalid + Input + 1 + readdatavalid + + + jtag_debug_module_debugaccess_to_roms + Output + 1 + debugaccess + + + false + cpu + jtag_debug_module + cpu.jtag_debug_module + 33556480 + 2048 + + + false + sysid + control_slave + sysid.control_slave + 33558688 + 8 + + + false + sdram + s1 + sdram.s1 + 16777216 + 16777216 + + + false + sys_clk_timer + s1 + sys_clk_timer.s1 + 33558592 + 32 + + + false + uart_0 + s1 + uart_0.s1 + 33558560 + 32 + + + false + pio_led + s1 + pio_led.s1 + 33558528 + 32 + + + false + pio_key + s1 + pio_key.s1 + 33558656 + 16 + + + false + pio_sw + s1 + pio_sw.s1 + 33558640 + 16 + + + false + jtag_uart_0 + avalon_jtag_slave + jtag_uart_0.avalon_jtag_slave + 33558680 + 8 + + + false + pio_motor_rst + s1 + pio_motor_rst.s1 + 33558624 + 16 + + + false + rs232_motor + avalon_rs232_slave + rs232_motor.avalon_rs232_slave + 33558672 + 8 + + + + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + int + 1 + false + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + SYMBOLS + false + true + true + true + + + boolean + true + false + true + false + true + + + java.lang.String + clk + false + true + true + true + + + java.lang.String + reset_n + false + true + true + true + + + int + 8 + false + true + true + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + true + true + + + int + 32 + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + true + + i_address + Output + 26 + address + + + i_read + Output + 1 + read + + + i_readdata + Input + 32 + readdata + + + i_waitrequest + Input + 1 + waitrequest + + + i_readdatavalid + Input + 1 + readdatavalid + + + false + cpu + jtag_debug_module + cpu.jtag_debug_module + 33556480 + 2048 + + + false + sdram + s1 + sdram.s1 + 16777216 + 16777216 + + + + + + com.altera.entityinterfaces.IConnectionPoint + cpu.data_master + false + true + true + true + + + java.lang.String + clk + false + true + false + true + + + java.lang.String + reset_n + false + true + false + true + + + com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme + INDIVIDUAL_REQUESTS + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + interrupt + true + + d_irq + Input + 32 + irq + + + false + sys_clk_timer + irq + sys_clk_timer.irq + 1 + + + false + uart_0 + irq + uart_0.irq + 4 + + + false + jtag_uart_0 + irq + jtag_uart_0.irq + 14 + + + false + rs232_motor + interrupt + rs232_motor.interrupt + 5 + + + + + + java.lang.String + clk + false + true + true + true + + + java.lang.String + + false + true + true + true + + + [Ljava.lang.String; + none + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + true + + jtag_debug_module_resetrequest + Output + 1 + reset + + + + + + embeddedsw.configuration.hideDevice + 1 + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 1 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + qsys.ui.connect + instruction_master,data_master + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + DYNAMIC + false + true + false + true + + + int + 0 + false + true + false + true + + + java.math.BigInteger + 2048 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + true + true + + + java.lang.String + reset_n + false + true + true + true + + + int + 8 + false + true + true + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.math.BigInteger + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + true + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + jtag_debug_module_address + Input + 9 + address + + + jtag_debug_module_begintransfer + Input + 1 + begintransfer + + + jtag_debug_module_byteenable + Input + 4 + byteenable + + + jtag_debug_module_debugaccess + Input + 1 + debugaccess + + + jtag_debug_module_readdata + Output + 32 + readdata + + + jtag_debug_module_select + Input + 1 + chipselect + + + jtag_debug_module_write + Input + 1 + write + + + jtag_debug_module_writedata + Input + 32 + writedata + + + + + + java.lang.String + + true + true + false + true + + + int + 8 + false + true + false + true + + + int + 0 + false + false + true + true + + + boolean + false + false + true + false + true + + + int + 8 + false + true + false + true + + + int + 0 + true + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + nios_custom_instruction + true + + no_ci_readra + Output + 1 + readra + + + + + + + embeddedsw.CMacro.ID + 0 + + + embeddedsw.CMacro.TIMESTAMP + 1394124174 + + + int + 0 + false + true + true + true + + + int + 1394124174 + false + false + false + true + + + java.lang.Long + 100000000 + false + true + false + true + + + java.lang.String + CYCLONEIVE + false + true + false + true + + + java.lang.String + Cyclone IV E + false + true + false + true + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.Boolean + true + true + true + false + true + + + java.lang.Long + 100000000 + true + true + false + true + + clock + false + + clock + Input + 1 + clk + + + + + + java.lang.String + clk + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + reset_n + Input + 1 + reset_n + + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 0 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + DYNAMIC + false + true + false + true + + + int + 0 + false + true + false + true + + + java.math.BigInteger + 8 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + true + true + + + java.lang.String + reset + false + true + true + true + + + int + 8 + false + true + true + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.math.BigInteger + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + readdata + Output + 32 + readdata + + + address + Input + 1 + address + + + + + + + embeddedsw.CMacro.REGISTER_DATA_IN + 1 + + + embeddedsw.CMacro.SIM_MODEL_BASE + 0 + + + embeddedsw.CMacro.SDRAM_DATA_WIDTH + 16 + + + embeddedsw.CMacro.SDRAM_ADDR_WIDTH + 23 + + + embeddedsw.CMacro.SDRAM_ROW_WIDTH + 13 + + + embeddedsw.CMacro.SDRAM_COL_WIDTH + 8 + + + embeddedsw.CMacro.SDRAM_NUM_CHIPSELECTS + 1 + + + embeddedsw.CMacro.SDRAM_NUM_BANKS + 4 + + + embeddedsw.CMacro.REFRESH_PERIOD + 7.8125 + + + embeddedsw.CMacro.POWERUP_DELAY + 200.0 + + + embeddedsw.CMacro.CAS_LATENCY + 3 + + + embeddedsw.CMacro.T_RFC + 70.0 + + + embeddedsw.CMacro.T_RP + 20.0 + + + embeddedsw.CMacro.T_MRD + 3 + + + embeddedsw.CMacro.T_RCD + 20.0 + + + embeddedsw.CMacro.T_AC + 5.5 + + + embeddedsw.CMacro.T_WR + 14.0 + + + embeddedsw.CMacro.INIT_REFRESH_COMMANDS + 8 + + + embeddedsw.CMacro.INIT_NOP_DELAY + 0.0 + + + embeddedsw.CMacro.SHARED_DATA + 0 + + + embeddedsw.CMacro.STARVATION_INDICATOR + 0 + + + embeddedsw.CMacro.TRISTATE_BRIDGE_SLAVE + "" + + + embeddedsw.CMacro.IS_INITIALIZED + 1 + + + embeddedsw.CMacro.SDRAM_BANK_WIDTH + 2 + + + embeddedsw.CMacro.CONTENTS_INFO + "" + + + embeddedsw.memoryInfo.MEM_INIT_DATA_WIDTH + 16 + + + embeddedsw.memoryInfo.GENERATE_DAT_SYM + 1 + + + embeddedsw.memoryInfo.DAT_SYM_INSTALL_DIR + SIM_DIR + + + double + 5.5 + false + true + true + true + + + long + 3 + false + true + true + true + + + double + 20.0 + false + true + true + true + + + double + 70.0 + false + true + true + true + + + double + 20.0 + false + true + true + true + + + double + 14.0 + false + true + true + true + + + int + 3 + false + true + true + true + + + long + 100000000 + false + true + true + true + + + int + 8 + false + true + true + true + + + int + 16 + false + true + true + true + + + boolean + false + false + true + true + true + + + double + 0.0 + false + true + true + true + + + int + 8 + false + true + true + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + false + true + true + + + com.altera.sopcmodel.components.avalon.AlteraAvalonSDRAMController.ModelMangler$PresetModels + custom + false + true + true + true + + + int + 4 + false + true + true + true + + + int + 1 + false + true + true + true + + + boolean + false + false + true + true + true + + + double + 200.0 + false + true + true + true + + + double + 7.8125 + false + true + true + true + + + boolean + true + false + true + true + true + + + int + 13 + false + true + true + true + + + long + 16777216 + true + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.Boolean + true + true + true + false + true + + + java.lang.Long + 100000000 + true + true + false + true + + clock + false + + clk + Input + 1 + clk + + + + + + java.lang.String + clk + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + reset_n + Input + 1 + reset_n + + + + + + embeddedsw.configuration.isMemoryDevice + 1 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + DYNAMIC + false + true + false + true + + + int + 0 + false + true + false + true + + + java.math.BigInteger + 16777216 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + true + true + + + java.lang.String + reset + false + true + true + true + + + int + 8 + false + true + true + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.math.BigInteger + 0 + false + true + true + true + + + int + 0 + false + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 7 + false + true + true + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + false + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + false + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + az_addr + Input + 23 + address + + + az_be_n + Input + 2 + byteenable_n + + + az_cs + Input + 1 + chipselect + + + az_data + Input + 16 + writedata + + + az_rd_n + Input + 1 + read_n + + + az_wr_n + Input + 1 + write_n + + + za_data + Output + 16 + readdata + + + za_valid + Output + 1 + readdatavalid + + + za_waitrequest + Output + 1 + waitrequest + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + zs_addr + Output + 13 + export + + + zs_ba + Output + 2 + export + + + zs_cas_n + Output + 1 + export + + + zs_cke + Output + 1 + export + + + zs_cs_n + Output + 1 + export + + + zs_dq + Bidir + 16 + export + + + zs_dqm + Output + 2 + export + + + zs_ras_n + Output + 1 + export + + + zs_we_n + Output + 1 + export + + + + + + + embeddedsw.CMacro.ALWAYS_RUN + 0 + + + embeddedsw.CMacro.FIXED_PERIOD + 0 + + + embeddedsw.CMacro.SNAPSHOT + 1 + + + embeddedsw.CMacro.PERIOD + 1 + + + embeddedsw.CMacro.PERIOD_UNITS + "ms" + + + embeddedsw.CMacro.RESET_OUTPUT + 0 + + + embeddedsw.CMacro.TIMEOUT_PULSE_OUTPUT + 0 + + + embeddedsw.CMacro.FREQ + 100000000u + + + embeddedsw.CMacro.LOAD_VALUE + 99999ULL + + + embeddedsw.CMacro.COUNTER_SIZE + 32 + + + embeddedsw.CMacro.MULT + 0.0010 + + + embeddedsw.CMacro.TICKS_PER_SEC + 1000u + + + boolean + false + false + true + true + true + + + int + 32 + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + 1 + false + true + true + true + + + com.altera.sopcmodel.components.avalon.AlteraAvalonTimer.AlteraAvalonTimer$TimerPeriodUnit + MSEC + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + true + false + true + true + true + + + long + 100000000 + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.components.avalon.AlteraAvalonTimer.TimerPresets + CUSTOM + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.Boolean + true + true + true + false + true + + + java.lang.Long + 100000000 + true + true + false + true + + clock + false + + clk + Input + 1 + clk + + + + + + java.lang.String + clk + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + reset_n + Input + 1 + reset_n + + + + + + embeddedsw.configuration.isTimerDevice + 1 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + NATIVE + false + true + false + true + + + int + 0 + false + true + false + true + + + java.math.BigInteger + 8 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + true + true + + + java.lang.String + reset + false + true + true + true + + + int + 8 + false + true + true + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.math.BigInteger + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + address + Input + 3 + address + + + writedata + Input + 16 + writedata + + + readdata + Output + 16 + readdata + + + chipselect + Input + 1 + chipselect + + + write_n + Input + 1 + write_n + + + + + + com.altera.entityinterfaces.IConnectionPoint + sys_clk_timer.s1 + false + true + true + true + + + java.lang.String + clk + false + true + false + true + + + java.lang.String + reset + false + true + false + true + + + com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme + NONE + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + interrupt + false + + irq + Output + 1 + irq + + + + + + + embeddedsw.CMacro.BAUD + 115200 + + + embeddedsw.CMacro.DATA_BITS + 8 + + + embeddedsw.CMacro.FIXED_BAUD + 0 + + + embeddedsw.CMacro.PARITY + 'N' + + + embeddedsw.CMacro.STOP_BITS + 1 + + + embeddedsw.CMacro.SYNC_REG_DEPTH + 2 + + + embeddedsw.CMacro.USE_CTS_RTS + 0 + + + embeddedsw.CMacro.USE_EOP_REGISTER + 0 + + + embeddedsw.CMacro.SIM_TRUE_BAUD + 0 + + + embeddedsw.CMacro.SIM_CHAR_STREAM + "" + + + embeddedsw.CMacro.FREQ + 100000000u + + + int + 115200 + false + true + true + true + + + double + 0.01 + true + true + true + true + + + long + 100000000 + false + true + false + true + + + int + 8 + false + true + true + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.components.avalon.AlteraAvalonUART.AlteraAvalonUART$UartParity + NONE + false + true + true + true + + + java.lang.String + + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + int + 1 + false + true + true + true + + + int + 2 + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.Boolean + true + true + true + false + true + + + java.lang.Long + 100000000 + true + true + false + true + + clock + false + + clk + Input + 1 + clk + + + + + + java.lang.String + clk + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + reset_n + Input + 1 + reset_n + + + + + + embeddedsw.configuration.isPrintableDevice + 1 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + NATIVE + false + true + false + true + + + int + 0 + false + true + false + true + + + java.math.BigInteger + 8 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + true + true + + + java.lang.String + reset + false + true + true + true + + + int + 8 + false + true + true + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.math.BigInteger + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + address + Input + 3 + address + + + begintransfer + Input + 1 + begintransfer + + + chipselect + Input + 1 + chipselect + + + read_n + Input + 1 + read_n + + + write_n + Input + 1 + write_n + + + writedata + Input + 16 + writedata + + + readdata + Output + 16 + readdata + + + dataavailable + Output + 1 + dataavailable + + + readyfordata + Output + 1 + readyfordata + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + rxd + Input + 1 + export + + + txd + Output + 1 + export + + + + + + com.altera.entityinterfaces.IConnectionPoint + uart_0.s1 + false + true + true + true + + + java.lang.String + clk + false + true + false + true + + + java.lang.String + reset + false + true + false + true + + + com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme + NONE + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + interrupt + false + + irq + Output + 1 + irq + + + + + + + embeddedsw.CMacro.DO_TEST_BENCH_WIRING + 0 + + + embeddedsw.CMacro.DRIVEN_SIM_VALUE + 0x0 + + + embeddedsw.CMacro.HAS_TRI + 0 + + + embeddedsw.CMacro.HAS_OUT + 1 + + + embeddedsw.CMacro.HAS_IN + 0 + + + embeddedsw.CMacro.CAPTURE + 0 + + + embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER + 0 + + + embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER + 1 + + + embeddedsw.CMacro.DATA_WIDTH + 7 + + + embeddedsw.CMacro.RESET_VALUE + 0x0 + + + embeddedsw.CMacro.EDGE_TYPE + "NONE" + + + embeddedsw.CMacro.IRQ_TYPE + "NONE" + + + embeddedsw.CMacro.FREQ + 100000000u + + + boolean + false + false + false + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + false + true + true + + + long + 100000000 + false + true + false + true + + + com.altera.sopcmodel.components.avalon.AlteraAvalonPIO.AlteraAvalonPIO$Direction + Output + false + true + true + true + + + com.altera.sopcmodel.components.avalon.AlteraAvalonPIO.AlteraAvalonPIO$EdgeType + RISING + false + false + true + true + + + boolean + false + false + false + true + true + + + com.altera.sopcmodel.components.avalon.AlteraAvalonPIO.AlteraAvalonPIO$IrqType + LEVEL + false + false + true + true + + + long + 0 + false + true + true + true + + + boolean + false + false + false + true + true + + + long + 0 + false + false + true + true + + + int + 7 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.Boolean + true + true + true + false + true + + + java.lang.Long + 100000000 + true + true + false + true + + clock + false + + clk + Input + 1 + clk + + + + + + java.lang.String + clk + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + reset_n + Input + 1 + reset_n + + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 0 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + NATIVE + false + true + false + true + + + int + 0 + false + true + false + true + + + java.math.BigInteger + 8 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + true + true + + + java.lang.String + reset + false + true + true + true + + + int + 8 + false + true + true + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.math.BigInteger + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + address + Input + 3 + address + + + write_n + Input + 1 + write_n + + + writedata + Input + 32 + writedata + + + chipselect + Input + 1 + chipselect + + + readdata + Output + 32 + readdata + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + out_port + Output + 7 + export + + + + + + + embeddedsw.CMacro.DO_TEST_BENCH_WIRING + 0 + + + embeddedsw.CMacro.DRIVEN_SIM_VALUE + 0x0 + + + embeddedsw.CMacro.HAS_TRI + 0 + + + embeddedsw.CMacro.HAS_OUT + 0 + + + embeddedsw.CMacro.HAS_IN + 1 + + + embeddedsw.CMacro.CAPTURE + 0 + + + embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER + 0 + + + embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER + 0 + + + embeddedsw.CMacro.DATA_WIDTH + 2 + + + embeddedsw.CMacro.RESET_VALUE + 0x0 + + + embeddedsw.CMacro.EDGE_TYPE + "NONE" + + + embeddedsw.CMacro.IRQ_TYPE + "NONE" + + + embeddedsw.CMacro.FREQ + 100000000u + + + boolean + false + false + false + true + true + + + boolean + false + false + false + true + true + + + boolean + false + false + true + true + true + + + long + 100000000 + false + true + false + true + + + com.altera.sopcmodel.components.avalon.AlteraAvalonPIO.AlteraAvalonPIO$Direction + Input + false + true + true + true + + + com.altera.sopcmodel.components.avalon.AlteraAvalonPIO.AlteraAvalonPIO$EdgeType + RISING + false + false + true + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.components.avalon.AlteraAvalonPIO.AlteraAvalonPIO$IrqType + LEVEL + false + false + true + true + + + long + 0 + false + false + true + true + + + boolean + false + false + true + true + true + + + long + 0 + false + false + true + true + + + int + 2 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.Boolean + true + true + true + false + true + + + java.lang.Long + 100000000 + true + true + false + true + + clock + false + + clk + Input + 1 + clk + + + + + + java.lang.String + clk + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + reset_n + Input + 1 + reset_n + + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 0 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + NATIVE + false + true + false + true + + + int + 0 + false + true + false + true + + + java.math.BigInteger + 4 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + true + true + + + java.lang.String + reset + false + true + true + true + + + int + 8 + false + true + true + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.math.BigInteger + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + address + Input + 2 + address + + + readdata + Output + 32 + readdata + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + in_port + Input + 2 + export + + + + + + + embeddedsw.CMacro.DO_TEST_BENCH_WIRING + 0 + + + embeddedsw.CMacro.DRIVEN_SIM_VALUE + 0x0 + + + embeddedsw.CMacro.HAS_TRI + 0 + + + embeddedsw.CMacro.HAS_OUT + 0 + + + embeddedsw.CMacro.HAS_IN + 1 + + + embeddedsw.CMacro.CAPTURE + 0 + + + embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER + 0 + + + embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER + 0 + + + embeddedsw.CMacro.DATA_WIDTH + 4 + + + embeddedsw.CMacro.RESET_VALUE + 0x0 + + + embeddedsw.CMacro.EDGE_TYPE + "NONE" + + + embeddedsw.CMacro.IRQ_TYPE + "NONE" + + + embeddedsw.CMacro.FREQ + 100000000u + + + boolean + false + false + false + true + true + + + boolean + false + false + false + true + true + + + boolean + false + false + true + true + true + + + long + 100000000 + false + true + false + true + + + com.altera.sopcmodel.components.avalon.AlteraAvalonPIO.AlteraAvalonPIO$Direction + Input + false + true + true + true + + + com.altera.sopcmodel.components.avalon.AlteraAvalonPIO.AlteraAvalonPIO$EdgeType + RISING + false + false + true + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.components.avalon.AlteraAvalonPIO.AlteraAvalonPIO$IrqType + LEVEL + false + false + true + true + + + long + 0 + false + false + true + true + + + boolean + false + false + true + true + true + + + long + 0 + false + false + true + true + + + int + 4 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.Boolean + true + true + true + false + true + + + java.lang.Long + 100000000 + true + true + false + true + + clock + false + + clk + Input + 1 + clk + + + + + + java.lang.String + clk + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + reset_n + Input + 1 + reset_n + + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 0 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + NATIVE + false + true + false + true + + + int + 0 + false + true + false + true + + + java.math.BigInteger + 4 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + true + true + + + java.lang.String + reset + false + true + true + true + + + int + 8 + false + true + true + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.math.BigInteger + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + address + Input + 2 + address + + + readdata + Output + 32 + readdata + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + in_port + Input + 4 + export + + + + + + + embeddedsw.CMacro.WRITE_DEPTH + 64 + + + embeddedsw.CMacro.READ_DEPTH + 64 + + + embeddedsw.CMacro.WRITE_THRESHOLD + 8 + + + embeddedsw.CMacro.READ_THRESHOLD + 8 + + + boolean + false + false + true + true + true + + + java.lang.String + 2.0 + false + true + false + true + + + int + 0 + false + true + false + true + + + boolean + false + true + true + true + true + + + int + 64 + false + true + true + true + + + int + 8 + false + true + true + true + + + java.lang.String + + false + true + true + true + + + com.altera.sopcmodel.components.avalon.AlteraAvalonJtagUART.AlteraAvalonJtagUART$JtagSimulationOptions + INTERACTIVE_INPUT_OUTPUT + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + false + true + + + int + 64 + false + true + true + true + + + int + 8 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + false + + clk + Input + 1 + clk + + + + + + java.lang.String + clk + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + rst_n + Input + 1 + reset_n + + + + + + embeddedsw.configuration.isPrintableDevice + 1 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + NATIVE + false + true + false + true + + + int + 0 + false + true + false + true + + + java.math.BigInteger + 2 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + true + true + + + java.lang.String + reset + false + true + true + true + + + int + 8 + false + true + true + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.math.BigInteger + 0 + false + true + true + true + + + int + 0 + false + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + false + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + false + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + av_chipselect + Input + 1 + chipselect + + + av_address + Input + 1 + address + + + av_read_n + Input + 1 + read_n + + + av_readdata + Output + 32 + readdata + + + av_write_n + Input + 1 + write_n + + + av_writedata + Input + 32 + writedata + + + av_waitrequest + Output + 1 + waitrequest + + + + + + com.altera.entityinterfaces.IConnectionPoint + jtag_uart_0.avalon_jtag_slave + false + true + true + true + + + java.lang.String + clk + false + true + false + true + + + java.lang.String + reset + false + true + false + true + + + com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme + NONE + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + interrupt + false + + av_irq + Output + 1 + irq + + + + + + + embeddedsw.CMacro.DO_TEST_BENCH_WIRING + 0 + + + embeddedsw.CMacro.DRIVEN_SIM_VALUE + 0x0 + + + embeddedsw.CMacro.HAS_TRI + 0 + + + embeddedsw.CMacro.HAS_OUT + 1 + + + embeddedsw.CMacro.HAS_IN + 0 + + + embeddedsw.CMacro.CAPTURE + 0 + + + embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER + 0 + + + embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER + 0 + + + embeddedsw.CMacro.DATA_WIDTH + 1 + + + embeddedsw.CMacro.RESET_VALUE + 0x0 + + + embeddedsw.CMacro.EDGE_TYPE + "NONE" + + + embeddedsw.CMacro.IRQ_TYPE + "NONE" + + + embeddedsw.CMacro.FREQ + 100000000u + + + boolean + false + false + false + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + false + true + true + + + long + 100000000 + false + true + false + true + + + com.altera.sopcmodel.components.avalon.AlteraAvalonPIO.AlteraAvalonPIO$Direction + Output + false + true + true + true + + + com.altera.sopcmodel.components.avalon.AlteraAvalonPIO.AlteraAvalonPIO$EdgeType + RISING + false + false + true + true + + + boolean + false + false + false + true + true + + + com.altera.sopcmodel.components.avalon.AlteraAvalonPIO.AlteraAvalonPIO$IrqType + LEVEL + false + false + true + true + + + long + 0 + false + true + true + true + + + boolean + false + false + false + true + true + + + long + 0 + false + false + true + true + + + int + 1 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.Boolean + true + true + true + false + true + + + java.lang.Long + 100000000 + true + true + false + true + + clock + false + + clk + Input + 1 + clk + + + + + + java.lang.String + clk + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + reset_n + Input + 1 + reset_n + + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 0 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + NATIVE + false + true + false + true + + + int + 0 + false + true + false + true + + + java.math.BigInteger + 4 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + true + true + + + java.lang.String + reset + false + true + true + true + + + int + 8 + false + true + true + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.math.BigInteger + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + address + Input + 2 + address + + + write_n + Input + 1 + write_n + + + writedata + Input + 32 + writedata + + + chipselect + Input + 1 + chipselect + + + readdata + Output + 32 + readdata + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + out_port + Output + 1 + export + + + + + + + java.lang.String + Memory Mapped + false + true + true + true + + + int + 100000000 + false + true + false + true + + + int + 9600 + false + true + true + true + + + java.lang.String + None + false + true + true + true + + + int + 8 + false + true + true + true + + + int + 1 + false + true + true + true + + + java.lang.Long + 100000000 + false + true + false + true + + + java.lang.String + CYCLONEIVE + false + true + false + true + + + java.lang.String + Cyclone IV E + false + true + false + true + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.Boolean + true + true + true + false + true + + + java.lang.Long + 100000000 + true + true + false + true + + clock + false + + clk + Input + 1 + clk + + + + + + java.lang.String + clock_reset + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + reset + Input + 1 + reset + + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 0 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + DYNAMIC + false + true + false + true + + + int + 0 + false + true + false + true + + + java.math.BigInteger + 8 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + clock_reset + false + true + true + true + + + java.lang.String + clock_reset_reset + false + true + true + true + + + int + 8 + false + true + true + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.math.BigInteger + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 1 + false + true + true + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + address + Input + 1 + address + + + chipselect + Input + 1 + chipselect + + + byteenable + Input + 4 + byteenable + + + read + Input + 1 + read + + + write + Input + 1 + write + + + writedata + Input + 32 + writedata + + + readdata + Output + 32 + readdata + + + + + + com.altera.entityinterfaces.IConnectionPoint + rs232_motor.avalon_rs232_slave + false + true + true + true + + + java.lang.String + clock_reset + false + true + false + true + + + java.lang.String + clock_reset_reset + false + true + false + true + + + com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme + NONE + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + interrupt + false + + irq + Output + 1 + irq + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + UART_RXD + Input + 1 + export + + + UART_TXD + Output + 1 + export + + + + + + int + 1 + false + true + true + true + + + java.math.BigInteger + 0x02000800 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + instruction_master + cpu + jtag_debug_module + + + + int + 1 + false + true + true + true + + + java.math.BigInteger + 0x02000800 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + data_master + cpu + jtag_debug_module + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_sys + clk_reset + cpu + reset_n + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + jtag_debug_module_reset + cpu + reset_n + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_sys + clk_reset + sysid + reset + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + jtag_debug_module_reset + sysid + reset + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_sys + clk_reset + sdram + reset + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + jtag_debug_module_reset + sdram + reset + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_sys + clk_reset + sys_clk_timer + reset + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + jtag_debug_module_reset + sys_clk_timer + reset + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_sys + clk_reset + uart_0 + reset + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + jtag_debug_module_reset + uart_0 + reset + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_sys + clk_reset + pio_led + reset + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + jtag_debug_module_reset + pio_led + reset + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_sys + clk_reset + pio_key + reset + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + jtag_debug_module_reset + pio_key + reset + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_sys + clk_reset + pio_sw + reset + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + jtag_debug_module_reset + pio_sw + reset + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_sys + clk + cpu + clk + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_sys + clk + sysid + clk + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_sys + clk + sdram + clk + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_sys + clk + sys_clk_timer + clk + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_sys + clk + uart_0 + clk + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_sys + clk + pio_led + clk + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_sys + clk + pio_key + clk + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_sys + clk + pio_sw + clk + + + + int + 1 + false + true + true + true + + + java.math.BigInteger + 0x020010a0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + data_master + sysid + control_slave + + + + int + 1 + false + true + true + true + + + java.math.BigInteger + 0x01000000 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + data_master + sdram + s1 + + + + int + 1 + false + true + true + true + + + java.math.BigInteger + 0x02001040 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + data_master + sys_clk_timer + s1 + + + + int + 1 + false + true + true + true + + + java.math.BigInteger + 0x02001020 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + data_master + uart_0 + s1 + + + + int + 1 + false + true + true + true + + + java.math.BigInteger + 0x02001000 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + data_master + pio_led + s1 + + + + int + 1 + false + true + true + true + + + java.math.BigInteger + 0x02001080 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + data_master + pio_key + s1 + + + + int + 1 + false + true + true + true + + + java.math.BigInteger + 0x02001070 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + data_master + pio_sw + s1 + + + + int + 1 + false + true + true + true + + + java.math.BigInteger + 0x01000000 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + instruction_master + sdram + s1 + + + + int + 1 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + d_irq + sys_clk_timer + irq + + + + int + 4 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + d_irq + uart_0 + irq + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_sys + clk + jtag_uart_0 + clk + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_sys + clk_reset + jtag_uart_0 + reset + + + + int + 14 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + d_irq + jtag_uart_0 + irq + + + + int + 1 + false + true + true + true + + + java.math.BigInteger + 0x02001098 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + data_master + jtag_uart_0 + avalon_jtag_slave + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + jtag_debug_module_reset + jtag_uart_0 + reset + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_sys + clk_reset + pio_motor_rst + reset + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + jtag_debug_module_reset + pio_motor_rst + reset + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_sys + clk + pio_motor_rst + clk + + + + int + 1 + false + true + true + true + + + java.math.BigInteger + 0x02001060 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + data_master + pio_motor_rst + s1 + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_sys + clk_reset + rs232_motor + clock_reset_reset + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + jtag_debug_module_reset + rs232_motor + clock_reset_reset + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_sys + clk + rs232_motor + clock_reset + + + + int + 1 + false + true + true + true + + + java.math.BigInteger + 0x02001090 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + data_master + rs232_motor + avalon_rs232_slave + + + + int + 5 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + d_irq + rs232_motor + interrupt + + + 1 + altera_up_avalon_rs232 + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + RS232 UART + 12.0 + + + 3 + reset_sink + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Reset Input + 12.1 + + + 1 + interrupt_receiver + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Interrupt Receiver + 12.1 + + + 1 + reset_source + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Reset Output + 12.1 + + + 1 + altera_nios2_qsys + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + Nios II Processor + 12.1 + + + 9 + clock_sink + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Clock Input + 12.1 + + + 1 + altera_avalon_timer + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + Interval Timer + 12.1 + + + 11 + clock + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IConnection + Clock Connection + 12.1 + + + 2 + avalon_master + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Avalon Memory Mapped Master + 12.1 + + + 1 + clock_source + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Clock Output + 12.1 + + + 1 + altera_avalon_new_sdram_controller + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + SDRAM Controller + 12.1 + + + 1 + altera_avalon_uart + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + UART (RS-232 Serial Port) + 12.1 + + + 1 + nios_custom_instruction_master + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Custom Instruction Master + 12.1 + + + 1 + reset_source + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Reset Output + 12.1 + + + 1 + conduit_end + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Conduit + 12.1 + + + 13 + avalon + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IConnection + Avalon Memory Mapped Connection + 12.1 + + + 4 + altera_avalon_pio + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + PIO (Parallel I/O) + 12.1 + + + 1 + interrupt_sender + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Interrupt Sender + 12.1 + + + 3 + interrupt_sender + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Interrupt Sender + 12.1 + + + 8 + avalon_slave + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Avalon Memory Mapped Slave + 12.1 + + + 1 + altera_avalon_jtag_uart + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + JTAG UART + 12.1 + + + 3 + avalon_slave + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Avalon Memory Mapped Slave + 12.1 + + + 9 + reset_sink + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Reset Input + 12.1 + + + 1 + clock_source + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + Clock Source + 12.1 + + + 22 + reset + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IConnection + Reset Connection + 12.1 + + + 3 + clock_sink + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Clock Input + 12.1 + + + 4 + interrupt + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IConnection + Interrupt Connection + 12.1 + + + 1 + altera_avalon_sysid_qsys + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + System ID Peripheral + 12.1 + + + 1 + conduit_end + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Conduit + 12.1 + + + 5 + conduit + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Conduit Endpoint + 7.1 + + 12.1sp1 243 + + diff --git a/MCTEST/DE0-nano-HD/system/synthesis/greybox_tmp/cbx_args.txt b/MCTEST/DE0-nano-HD/system/synthesis/greybox_tmp/cbx_args.txt new file mode 100644 index 00000000..d915da54 --- /dev/null +++ b/MCTEST/DE0-nano-HD/system/synthesis/greybox_tmp/cbx_args.txt @@ -0,0 +1,70 @@ +BANDWIDTH_TYPE=AUTO +CLK0_DIVIDE_BY=1 +CLK0_DUTY_CYCLE=50 +CLK0_MULTIPLY_BY=2 +CLK0_PHASE_SHIFT=0 +CLK1_DIVIDE_BY=1 +CLK1_DUTY_CYCLE=50 +CLK1_MULTIPLY_BY=2 +CLK1_PHASE_SHIFT=-1500 +CLK2_DIVIDE_BY=5 +CLK2_DUTY_CYCLE=50 +CLK2_MULTIPLY_BY=1 +CLK2_PHASE_SHIFT=0 +COMPENSATE_CLOCK=CLK0 +INCLK0_INPUT_FREQUENCY=20000 +INTENDED_DEVICE_FAMILY="Cyclone IV E" +LPM_TYPE=altpll +OPERATION_MODE=NORMAL +PLL_TYPE=AUTO +PORT_ACTIVECLOCK=PORT_UNUSED +PORT_ARESET=PORT_UNUSED +PORT_CLKBAD0=PORT_UNUSED +PORT_CLKBAD1=PORT_UNUSED +PORT_CLKLOSS=PORT_UNUSED +PORT_CLKSWITCH=PORT_UNUSED +PORT_CONFIGUPDATE=PORT_UNUSED +PORT_FBIN=PORT_UNUSED +PORT_INCLK0=PORT_USED +PORT_INCLK1=PORT_UNUSED +PORT_LOCKED=PORT_USED +PORT_PFDENA=PORT_UNUSED +PORT_PHASECOUNTERSELECT=PORT_UNUSED +PORT_PHASEDONE=PORT_UNUSED +PORT_PHASESTEP=PORT_UNUSED +PORT_PHASEUPDOWN=PORT_UNUSED +PORT_PLLENA=PORT_UNUSED +PORT_SCANACLR=PORT_UNUSED +PORT_SCANCLK=PORT_UNUSED +PORT_SCANCLKENA=PORT_UNUSED +PORT_SCANDATA=PORT_UNUSED +PORT_SCANDATAOUT=PORT_UNUSED +PORT_SCANDONE=PORT_UNUSED +PORT_SCANREAD=PORT_UNUSED +PORT_SCANWRITE=PORT_UNUSED +PORT_clk0=PORT_USED +PORT_clk1=PORT_USED +PORT_clk2=PORT_USED +PORT_clk3=PORT_UNUSED +PORT_clk4=PORT_UNUSED +PORT_clk5=PORT_UNUSED +PORT_clkena0=PORT_UNUSED +PORT_clkena1=PORT_UNUSED +PORT_clkena2=PORT_UNUSED +PORT_clkena3=PORT_UNUSED +PORT_clkena4=PORT_UNUSED +PORT_clkena5=PORT_UNUSED +PORT_extclk0=PORT_UNUSED +PORT_extclk1=PORT_UNUSED +PORT_extclk2=PORT_UNUSED +PORT_extclk3=PORT_UNUSED +SELF_RESET_ON_LOSS_LOCK=ON +WIDTH_CLOCK=5 +DEVICE_FAMILY="Cyclone IV E" +CBX_AUTO_BLACKBOX=ALL +inclk +inclk +clk +clk +clk +locked diff --git a/MCTEST/DE0-nano-HD/system/synthesis/pll_sys.qip b/MCTEST/DE0-nano-HD/system/synthesis/pll_sys.qip new file mode 100644 index 00000000..e69de29b diff --git a/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_avalon_sc_fifo.v b/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_avalon_sc_fifo.v new file mode 100644 index 00000000..32d01214 --- /dev/null +++ b/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_avalon_sc_fifo.v @@ -0,0 +1,879 @@ +// ----------------------------------------------------------- +// Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your +// use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any +// output files any of the foregoing (including device programming or +// simulation files), and any associated documentation or information are +// expressly subject to the terms and conditions of the Altera Program +// License Subscription Agreement or other applicable license agreement, +// including, without limitation, that your use is for the sole purpose +// of programming logic devices manufactured by Altera and sold by Altera +// or its authorized distributors. Please refer to the applicable +// agreement for further details. +// +// Description: Single clock Avalon-ST FIFO. +// ----------------------------------------------------------- + +`timescale 1 ns / 1 ns + + +//altera message_off 10036 +module altera_avalon_sc_fifo +#( + // -------------------------------------------------- + // Parameters + // -------------------------------------------------- + parameter SYMBOLS_PER_BEAT = 1, + parameter BITS_PER_SYMBOL = 8, + parameter FIFO_DEPTH = 16, + parameter CHANNEL_WIDTH = 0, + parameter ERROR_WIDTH = 0, + parameter USE_PACKETS = 0, + parameter USE_FILL_LEVEL = 0, + parameter USE_STORE_FORWARD = 0, + parameter USE_ALMOST_FULL_IF = 0, + parameter USE_ALMOST_EMPTY_IF = 0, + + // -------------------------------------------------- + // Empty latency is defined as the number of cycles + // required for a write to deassert the empty flag. + // For example, a latency of 1 means that the empty + // flag is deasserted on the cycle after a write. + // + // Another way to think of it is the latency for a + // write to propagate to the output. + // + // An empty latency of 0 implies lookahead, which is + // only implemented for the register-based FIFO. + // -------------------------------------------------- + parameter EMPTY_LATENCY = 3, + parameter USE_MEMORY_BLOCKS = 1, + + // -------------------------------------------------- + // Internal Parameters + // -------------------------------------------------- + parameter DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL, + parameter EMPTY_WIDTH = log2ceil(SYMBOLS_PER_BEAT) +) +( + // -------------------------------------------------- + // Ports + // -------------------------------------------------- + input clk, + input reset, + + input [DATA_WIDTH-1: 0] in_data, + input in_valid, + input in_startofpacket, + input in_endofpacket, + input [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] in_empty, + input [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] in_error, + input [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] in_channel, + output in_ready, + + output [DATA_WIDTH-1 : 0] out_data, + output reg out_valid, + output out_startofpacket, + output out_endofpacket, + output [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] out_empty, + output [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] out_error, + output [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] out_channel, + input out_ready, + + input [(USE_STORE_FORWARD ? 2 : 1) : 0] csr_address, + input csr_write, + input csr_read, + input [31 : 0] csr_writedata, + output reg [31 : 0] csr_readdata, + + output wire almost_full_data, + output wire almost_empty_data +); + + // -------------------------------------------------- + // Local Parameters + // -------------------------------------------------- + localparam ADDR_WIDTH = log2ceil(FIFO_DEPTH); + localparam DEPTH = FIFO_DEPTH; + localparam PKT_SIGNALS_WIDTH = 2 + EMPTY_WIDTH; + localparam PAYLOAD_WIDTH = (USE_PACKETS == 1) ? + 2 + EMPTY_WIDTH + DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH: + DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH; + + // -------------------------------------------------- + // Internal Signals + // -------------------------------------------------- + genvar i; + + reg [PAYLOAD_WIDTH-1 : 0] mem [DEPTH-1 : 0]; + reg [ADDR_WIDTH-1 : 0] wr_ptr; + reg [ADDR_WIDTH-1 : 0] rd_ptr; + reg [DEPTH-1 : 0] mem_used; + + wire [ADDR_WIDTH-1 : 0] next_wr_ptr; + wire [ADDR_WIDTH-1 : 0] next_rd_ptr; + wire [ADDR_WIDTH-1 : 0] incremented_wr_ptr; + wire [ADDR_WIDTH-1 : 0] incremented_rd_ptr; + + wire [ADDR_WIDTH-1 : 0] mem_rd_ptr; + + wire read; + wire write; + + reg empty; + reg next_empty; + reg full; + reg next_full; + + wire [PKT_SIGNALS_WIDTH-1 : 0] in_packet_signals; + wire [PKT_SIGNALS_WIDTH-1 : 0] out_packet_signals; + wire [PAYLOAD_WIDTH-1 : 0] in_payload; + reg [PAYLOAD_WIDTH-1 : 0] internal_out_payload; + reg [PAYLOAD_WIDTH-1 : 0] out_payload; + + reg internal_out_valid; + wire internal_out_ready; + + reg [ADDR_WIDTH : 0] fifo_fill_level; + reg [ADDR_WIDTH : 0] fill_level; + + reg [ADDR_WIDTH-1 : 0] sop_ptr = 0; + reg [23:0] almost_full_threshold; + reg [23:0] almost_empty_threshold; + reg [23:0] cut_through_threshold; + reg [15:0] pkt_cnt; + reg [15:0] pkt_cnt_r; + reg [15:0] pkt_cnt_plusone; + reg [15:0] pkt_cnt_minusone; + reg drop_on_error_en; + reg error_in_pkt; + reg pkt_has_started; + reg sop_has_left_fifo; + reg fifo_too_small_r; + reg pkt_cnt_eq_zero; + reg pkt_cnt_eq_one; + reg pkt_cnt_changed; + + wire wait_for_threshold; + reg pkt_mode; + wire wait_for_pkt; + wire ok_to_forward; + wire in_pkt_eop_arrive; + wire out_pkt_leave; + wire in_pkt_start; + wire in_pkt_error; + wire drop_on_error; + wire fifo_too_small; + wire out_pkt_sop_leave; + wire [31:0] max_fifo_size; + reg fifo_fill_level_lt_cut_through_threshold; + + // -------------------------------------------------- + // Define Payload + // + // Icky part where we decide which signals form the + // payload to the FIFO with generate blocks. + // -------------------------------------------------- + generate + if (EMPTY_WIDTH > 0) begin + assign in_packet_signals = {in_startofpacket, in_endofpacket, in_empty}; + assign {out_startofpacket, out_endofpacket, out_empty} = out_packet_signals; + end + else begin + assign out_empty = in_error; + assign in_packet_signals = {in_startofpacket, in_endofpacket}; + assign {out_startofpacket, out_endofpacket} = out_packet_signals; + end + endgenerate + + generate + if (USE_PACKETS) begin + if (ERROR_WIDTH > 0) begin + if (CHANNEL_WIDTH > 0) begin + assign in_payload = {in_packet_signals, in_data, in_error, in_channel}; + assign {out_packet_signals, out_data, out_error, out_channel} = out_payload; + end + else begin + assign out_channel = in_channel; + assign in_payload = {in_packet_signals, in_data, in_error}; + assign {out_packet_signals, out_data, out_error} = out_payload; + end + end + else begin + assign out_error = in_error; + if (CHANNEL_WIDTH > 0) begin + assign in_payload = {in_packet_signals, in_data, in_channel}; + assign {out_packet_signals, out_data, out_channel} = out_payload; + end + else begin + assign out_channel = in_channel; + assign in_payload = {in_packet_signals, in_data}; + assign {out_packet_signals, out_data} = out_payload; + end + end + end + else begin + assign out_packet_signals = 0; + if (ERROR_WIDTH > 0) begin + if (CHANNEL_WIDTH > 0) begin + assign in_payload = {in_data, in_error, in_channel}; + assign {out_data, out_error, out_channel} = out_payload; + end + else begin + assign out_channel = in_channel; + assign in_payload = {in_data, in_error}; + assign {out_data, out_error} = out_payload; + end + end + else begin + assign out_error = in_error; + if (CHANNEL_WIDTH > 0) begin + assign in_payload = {in_data, in_channel}; + assign {out_data, out_channel} = out_payload; + end + else begin + assign out_channel = in_channel; + assign in_payload = in_data; + assign out_data = out_payload; + end + end + end + endgenerate + + // -------------------------------------------------- + // Memory-based FIFO storage + // + // To allow a ready latency of 0, the read index is + // obtained from the next read pointer and memory + // outputs are unregistered. + // + // If the empty latency is 1, we infer bypass logic + // around the memory so writes propagate to the + // outputs on the next cycle. + // + // Do not change the way this is coded: Quartus needs + // a perfect match to the template, and any attempt to + // refactor the two always blocks into one will break + // memory inference. + // -------------------------------------------------- + generate if (USE_MEMORY_BLOCKS == 1) begin + + if (EMPTY_LATENCY == 1) begin + + always @(posedge clk) begin + if (in_valid && in_ready) + mem[wr_ptr] = in_payload; + + internal_out_payload = mem[mem_rd_ptr]; + end + + end else begin + + always @(posedge clk) begin + if (in_valid && in_ready) + mem[wr_ptr] <= in_payload; + + internal_out_payload <= mem[mem_rd_ptr]; + end + + end + + assign mem_rd_ptr = next_rd_ptr; + + end else begin + + // -------------------------------------------------- + // Register-based FIFO storage + // + // Uses a shift register as the storage element. Each + // shift register slot has a bit which indicates if + // the slot is occupied (credit to Sam H for the idea). + // The occupancy bits are contiguous and start from the + // lsb, so 0000, 0001, 0011, 0111, 1111 for a 4-deep + // FIFO. + // + // Each slot is enabled during a read or when it + // is unoccupied. New data is always written to every + // going-to-be-empty slot (we keep track of which ones + // are actually useful with the occupancy bits). On a + // read we shift occupied slots. + // + // The exception is the last slot, which always gets + // new data when it is unoccupied. + // -------------------------------------------------- + for (i = 0; i < DEPTH-1; i = i + 1) begin : shift_reg + always @(posedge clk or posedge reset) begin + if (reset) begin + mem[i] <= 0; + end + else if (read || !mem_used[i]) begin + if (!mem_used[i+1]) + mem[i] <= in_payload; + else + mem[i] <= mem[i+1]; + end + end + end + + always @(posedge clk, posedge reset) begin + if (reset) begin + mem[DEPTH-1] <= 0; + end + else begin + if (!mem_used[DEPTH-1]) + mem[DEPTH-1] <= in_payload; + + if (DEPTH == 1) begin + if (write) + mem[DEPTH-1] <= in_payload; + end + end + end + + end + endgenerate + + assign read = internal_out_ready && internal_out_valid && ok_to_forward; + assign write = in_ready && in_valid; + + // -------------------------------------------------- + // Pointer Management + // -------------------------------------------------- + generate if (USE_MEMORY_BLOCKS == 1) begin + + assign incremented_wr_ptr = wr_ptr + 1'b1; + assign incremented_rd_ptr = rd_ptr + 1'b1; + assign next_wr_ptr = drop_on_error ? sop_ptr : write ? incremented_wr_ptr : wr_ptr; + assign next_rd_ptr = (read) ? incremented_rd_ptr : rd_ptr; + + always @(posedge clk or posedge reset) begin + if (reset) begin + wr_ptr <= 0; + rd_ptr <= 0; + end + else begin + wr_ptr <= next_wr_ptr; + rd_ptr <= next_rd_ptr; + end + end + + end else begin + + // -------------------------------------------------- + // Shift Register Occupancy Bits + // + // Consider a 4-deep FIFO with 2 entries: 0011 + // On a read and write, do not modify the bits. + // On a write, left-shift the bits to get 0111. + // On a read, right-shift the bits to get 0001. + // + // Also, on a write we set bit0 (the head), while + // clearing the tail on a read. + // -------------------------------------------------- + always @(posedge clk or posedge reset) begin + if (reset) begin + mem_used[0] <= 0; + end + else begin + if (write ^ read) begin + if (read) begin + if (DEPTH > 1) + mem_used[0] <= mem_used[1]; + else + mem_used[0] <= 0; + end + if (write) + mem_used[0] <= 1; + end + end + end + + if (DEPTH > 1) begin + always @(posedge clk or posedge reset) begin + if (reset) begin + mem_used[DEPTH-1] <= 0; + end + else begin + if (write ^ read) begin + mem_used[DEPTH-1] <= 0; + if (write) + mem_used[DEPTH-1] <= mem_used[DEPTH-2]; + end + end + end + end + + for (i = 1; i < DEPTH-1; i = i + 1) begin : storage_logic + always @(posedge clk, posedge reset) begin + if (reset) begin + mem_used[i] <= 0; + end + else begin + if (write ^ read) begin + if (read) + mem_used[i] <= mem_used[i+1]; + if (write) + mem_used[i] <= mem_used[i-1]; + end + end + end + end + + end + endgenerate + + + // -------------------------------------------------- + // Memory FIFO Status Management + // + // Generates the full and empty signals from the + // pointers. The FIFO is full when the next write + // pointer will be equal to the read pointer after + // a write. Reading from a FIFO clears full. + // + // The FIFO is empty when the next read pointer will + // be equal to the write pointer after a read. Writing + // to a FIFO clears empty. + // + // A simultaneous read and write must not change any of + // the empty or full flags unless there is a drop on error event. + // -------------------------------------------------- + generate if (USE_MEMORY_BLOCKS == 1) begin + + always @* begin + next_full = full; + next_empty = empty; + + if (read && !write) begin + next_full = 1'b0; + + if (incremented_rd_ptr == wr_ptr) + next_empty = 1'b1; + end + + if (write && !read) begin + if (!drop_on_error) + next_empty = 1'b0; + else if (sop_ptr == rd_ptr) // drop on error and only 1 pkt in fifo + next_empty = 1'b1; + + if (incremented_wr_ptr == rd_ptr && !drop_on_error) + next_full = 1'b1; + end + + if (write && read && drop_on_error) begin + if (sop_ptr == next_rd_ptr) + next_empty = 1'b1; + end + end + + always @(posedge clk or posedge reset) begin + if (reset) begin + empty <= 1; + full <= 0; + end + else begin + empty <= next_empty; + full <= next_full; + end + end + + end else begin + // -------------------------------------------------- + // Register FIFO Status Management + // + // Full when the tail occupancy bit is 1. Empty when + // the head occupancy bit is 0. + // -------------------------------------------------- + always @* begin + full = mem_used[DEPTH-1]; + empty = !mem_used[0]; + + // ------------------------------------------ + // For a single slot FIFO, reading clears the + // full status immediately. + // ------------------------------------------ + if (DEPTH == 1) + full = mem_used[0] && !read; + + internal_out_payload = mem[0]; + + // ------------------------------------------ + // Writes clear empty immediately for lookahead modes. + // Note that we use in_valid instead of write to avoid + // combinational loops (in lookahead mode, qualifying + // with in_ready is meaningless). + // + // In a 1-deep FIFO, a possible combinational loop runs + // from write -> out_valid -> out_ready -> write + // ------------------------------------------ + if (EMPTY_LATENCY == 0) begin + empty = !mem_used[0] && !in_valid; + + if (!mem_used[0] && in_valid) + internal_out_payload = in_payload; + end + end + + end + endgenerate + + // -------------------------------------------------- + // Avalon-ST Signals + // + // The in_ready signal is straightforward. + // + // To match memory latency when empty latency > 1, + // out_valid assertions must be delayed by one clock + // cycle. + // + // Note: out_valid deassertions must not be delayed or + // the FIFO will underflow. + // -------------------------------------------------- + assign in_ready = !full; + assign internal_out_ready = out_ready || !out_valid; + + generate if (EMPTY_LATENCY > 1) begin + always @(posedge clk or posedge reset) begin + if (reset) + internal_out_valid <= 0; + else begin + internal_out_valid <= !empty & ok_to_forward & ~drop_on_error; + + if (read) begin + if (incremented_rd_ptr == wr_ptr) + internal_out_valid <= 1'b0; + end + end + end + end else begin + always @* begin + internal_out_valid = !empty & ok_to_forward; + end + end + endgenerate + + // -------------------------------------------------- + // Single Output Pipeline Stage + // + // This output pipeline stage is enabled if the FIFO's + // empty latency is set to 3 (default). It is disabled + // for all other allowed latencies. + // + // Reason: The memory outputs are unregistered, so we have to + // register the output or fmax will drop if combinatorial + // logic is present on the output datapath. + // + // Q: The Avalon-ST spec says that I have to register my outputs + // But isn't the memory counted as a register? + // A: The path from the address lookup to the memory output is + // slow. Registering the memory outputs is a good idea. + // + // The registers get packed into the memory by the fitter + // which means minimal resources are consumed (the result + // is a altsyncram with registered outputs, available on + // all modern Altera devices). + // + // This output stage acts as an extra slot in the FIFO, + // and complicates the fill level. + // -------------------------------------------------- + generate if (EMPTY_LATENCY == 3) begin + always @(posedge clk or posedge reset) begin + if (reset) begin + out_valid <= 0; + out_payload <= 0; + end + else begin + if (internal_out_ready) begin + out_valid <= internal_out_valid & ok_to_forward; + out_payload <= internal_out_payload; + end + end + end + end + else begin + always @* begin + out_valid = internal_out_valid; + out_payload = internal_out_payload; + end + end + endgenerate + + // -------------------------------------------------- + // Fill Level + // + // The fill level is calculated from the next write + // and read pointers to avoid unnecessary latency. + // + // If the output pipeline is enabled, the fill level + // must account for it, or we'll always be off by one. + // This may, or may not be important depending on the + // application. + // + // For now, we'll always calculate the exact fill level + // at the cost of an extra adder when the output stage + // is enabled. + // -------------------------------------------------- + generate if (USE_FILL_LEVEL) begin + wire [31:0] depth32; + assign depth32 = DEPTH; + always @(posedge clk or posedge reset) begin + if (reset) + fifo_fill_level <= 0; + else if (next_full & !drop_on_error) + fifo_fill_level <= depth32[ADDR_WIDTH:0]; + else begin + fifo_fill_level[ADDR_WIDTH] <= 1'b0; + fifo_fill_level[ADDR_WIDTH-1 : 0] <= next_wr_ptr - next_rd_ptr; + end + end + + always @* begin + fill_level = fifo_fill_level; + + if (EMPTY_LATENCY == 3) + fill_level = fifo_fill_level + {{ADDR_WIDTH{1'b0}}, out_valid}; + end + end + else begin + always @* begin + fill_level = 0; + end + end + endgenerate + + generate if (USE_ALMOST_FULL_IF) begin + assign almost_full_data = (fill_level >= almost_full_threshold); + end + else + assign almost_full_data = 0; + endgenerate + + generate if (USE_ALMOST_EMPTY_IF) begin + assign almost_empty_data = (fill_level <= almost_empty_threshold); + end + else + assign almost_empty_data = 0; + endgenerate + + // -------------------------------------------------- + // Avalon-MM Status & Control Connection Point + // + // Register map: + // + // | Addr | RW | 31 - 0 | + // | 0 | R | Fill level | + // + // The registering of this connection point means + // that there is a cycle of latency between + // reads/writes and the updating of the fill level. + // -------------------------------------------------- + generate if (USE_STORE_FORWARD) begin + assign max_fifo_size = FIFO_DEPTH - 1; + always @(posedge clk or posedge reset) begin + if (reset) begin + almost_full_threshold <= max_fifo_size[23 : 0]; + almost_empty_threshold <= 0; + cut_through_threshold <= 0; + drop_on_error_en <= 0; + csr_readdata <= 0; + pkt_mode <= 1'b1; + end + else begin + if (csr_write) begin + if(csr_address == 3'b010) + almost_full_threshold <= csr_writedata[23:0]; + if(csr_address == 3'b011) + almost_empty_threshold <= csr_writedata[23:0]; + if(csr_address == 3'b100) begin + cut_through_threshold <= csr_writedata[23:0]; + pkt_mode <= (csr_writedata[23:0] == 0); + end + if(csr_address == 3'b101) + drop_on_error_en <= csr_writedata[0]; + end + + if (csr_read) begin + csr_readdata <= 32'b0; + if (csr_address == 0) + csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level}; + if (csr_address == 2) + csr_readdata <= {8'b0, almost_full_threshold}; + if (csr_address == 3) + csr_readdata <= {8'b0, almost_empty_threshold}; + if (csr_address == 4) + csr_readdata <= {8'b0, cut_through_threshold}; + if (csr_address == 5) + csr_readdata <= {31'b0, drop_on_error_en}; + end + end + end + end + else if (USE_ALMOST_FULL_IF || USE_ALMOST_EMPTY_IF) begin + assign max_fifo_size = FIFO_DEPTH - 1; + always @(posedge clk or posedge reset) begin + if (reset) begin + almost_full_threshold <= max_fifo_size[23 : 0]; + almost_empty_threshold <= 0; + csr_readdata <= 0; + end + else begin + if (csr_write) begin + if(csr_address == 3'b010) + almost_full_threshold <= csr_writedata[23:0]; + if(csr_address == 3'b011) + almost_empty_threshold <= csr_writedata[23:0]; + end + + if (csr_read) begin + csr_readdata <= 32'b0; + if (csr_address == 0) + csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level}; + if (csr_address == 2) + csr_readdata <= {8'b0, almost_full_threshold}; + if (csr_address == 3) + csr_readdata <= {8'b0, almost_empty_threshold}; + end + end + end + end + else begin + always @(posedge clk or posedge reset) begin + if (reset) begin + csr_readdata <= 0; + end + else if (csr_read) begin + csr_readdata <= 0; + + if (csr_address == 0) + csr_readdata <= fill_level; + end + end + end + endgenerate + + // -------------------------------------------------- + // Store and forward logic + // -------------------------------------------------- + // if the fifo gets full before the entire packet or the + // cut-threshold condition is met then start sending out + // data in order to avoid dead-lock situation + + generate if (USE_STORE_FORWARD) begin + assign wait_for_threshold = (fifo_fill_level_lt_cut_through_threshold) & wait_for_pkt ; + assign wait_for_pkt = pkt_cnt_eq_zero | (pkt_cnt_eq_one & out_pkt_leave); + assign ok_to_forward = (pkt_mode ? (~wait_for_pkt | ~pkt_has_started) : + ~wait_for_threshold) | fifo_too_small_r; + assign in_pkt_eop_arrive = in_valid & in_ready & in_endofpacket; + assign in_pkt_start = in_valid & in_ready & in_startofpacket; + assign in_pkt_error = in_valid & in_ready & |in_error; + assign out_pkt_sop_leave = out_valid & out_ready & out_startofpacket; + assign out_pkt_leave = out_valid & out_ready & out_endofpacket; + assign fifo_too_small = (pkt_mode ? wait_for_pkt : wait_for_threshold) & full & out_ready; + + // count packets coming and going into the fifo + always @(posedge clk or posedge reset) begin + if (reset) begin + pkt_cnt <= 0; + pkt_cnt_r <= 0; + pkt_cnt_plusone <= 1; + pkt_cnt_minusone <= 0; + pkt_cnt_changed <= 0; + pkt_has_started <= 0; + sop_has_left_fifo <= 0; + fifo_too_small_r <= 0; + pkt_cnt_eq_zero <= 1'b1; + pkt_cnt_eq_one <= 1'b0; + fifo_fill_level_lt_cut_through_threshold <= 1'b1; + end + else begin + fifo_fill_level_lt_cut_through_threshold <= fifo_fill_level < cut_through_threshold; + fifo_too_small_r <= fifo_too_small; + pkt_cnt_plusone <= pkt_cnt + 1'b1; + pkt_cnt_minusone <= pkt_cnt - 1'b1; + pkt_cnt_r <= pkt_cnt; + pkt_cnt_changed <= 1'b0; + + if( in_pkt_eop_arrive ) + sop_has_left_fifo <= 1'b0; + else if (out_pkt_sop_leave & pkt_cnt_eq_zero ) + sop_has_left_fifo <= 1'b1; + + if (in_pkt_eop_arrive & ~out_pkt_leave & ~drop_on_error ) begin + pkt_cnt_changed <= 1'b1; + pkt_cnt <= pkt_cnt_changed ? pkt_cnt_r : pkt_cnt_plusone; + pkt_cnt_eq_zero <= 0; + if (pkt_cnt == 0) + pkt_cnt_eq_one <= 1'b1; + else + pkt_cnt_eq_one <= 1'b0; + end + else if((~in_pkt_eop_arrive | drop_on_error) & out_pkt_leave) begin + pkt_cnt_changed <= 1'b1; + pkt_cnt <= pkt_cnt_changed ? pkt_cnt_r : pkt_cnt_minusone; + if (pkt_cnt == 1) + pkt_cnt_eq_zero <= 1'b1; + else + pkt_cnt_eq_zero <= 1'b0; + if (pkt_cnt == 2) + pkt_cnt_eq_one <= 1'b1; + else + pkt_cnt_eq_one <= 1'b0; + end + + if (in_pkt_start) + pkt_has_started <= 1'b1; + else if (in_pkt_eop_arrive) + pkt_has_started <= 1'b0; + end + end + + // drop on error logic + always @(posedge clk or posedge reset) begin + if (reset) begin + sop_ptr <= 0; + error_in_pkt <= 0; + end + else begin + // save the location of the SOP + if ( in_pkt_start ) + sop_ptr <= wr_ptr; + + // remember if error in pkt + // log error only if packet has already started + if (in_pkt_eop_arrive) + error_in_pkt <= 1'b0; + else if ( in_pkt_error & (pkt_has_started | in_pkt_start)) + error_in_pkt <= 1'b1; + end + end + assign drop_on_error = drop_on_error_en & (error_in_pkt | in_pkt_error) & in_pkt_eop_arrive & + ~sop_has_left_fifo & ~(out_pkt_sop_leave & pkt_cnt_eq_zero); + + end + else begin + assign ok_to_forward = 1'b1; + assign drop_on_error = 1'b0; + end + endgenerate + + + // -------------------------------------------------- + // Calculates the log2ceil of the input value + // -------------------------------------------------- + function integer log2ceil; + input integer val; + integer i; + + begin + i = 1; + log2ceil = 0; + + while (i < val) begin + log2ceil = log2ceil + 1; + i = i << 1; + end + end + endfunction + +endmodule diff --git a/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_avalon_st_pipeline_base.v b/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_avalon_st_pipeline_base.v new file mode 100644 index 00000000..e09fe8cc --- /dev/null +++ b/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_avalon_st_pipeline_base.v @@ -0,0 +1,142 @@ +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $File: //acds/rel/12.1sp1/ip/avalon_st/altera_avalon_st_pipeline_stage/altera_avalon_st_pipeline_base.v $ +// $Revision: #1 $ +// $Date: 2012/10/10 $ +// $Author: swbranch $ +//------------------------------------------------------------------------------ + +`timescale 1ns / 1ns + +module altera_avalon_st_pipeline_base ( + clk, + reset, + in_ready, + in_valid, + in_data, + out_ready, + out_valid, + out_data + ); + + parameter SYMBOLS_PER_BEAT = 1; + parameter BITS_PER_SYMBOL = 8; + parameter PIPELINE_READY = 1; + localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL; + + input clk; + input reset; + + output in_ready; + input in_valid; + input [DATA_WIDTH-1:0] in_data; + + input out_ready; + output out_valid; + output [DATA_WIDTH-1:0] out_data; + + reg full0; + reg full1; + reg [DATA_WIDTH-1:0] data0; + reg [DATA_WIDTH-1:0] data1; + + assign out_valid = full1; + assign out_data = data1; + + generate if (PIPELINE_READY == 1) + begin : REGISTERED_READY_PLINE + + assign in_ready = !full0; + + always @(posedge clk, posedge reset) begin + if (reset) begin + data0 <= {DATA_WIDTH{1'b0}}; + data1 <= {DATA_WIDTH{1'b0}}; + end else begin + // ---------------------------- + // always load the second slot if we can + // ---------------------------- + if (~full0) + data0 <= in_data; + // ---------------------------- + // first slot is loaded either from the second, + // or with new data + // ---------------------------- + if (~full1 || (out_ready && out_valid)) begin + if (full0) + data1 <= data0; + else + data1 <= in_data; + end + end + end + + always @(posedge clk or posedge reset) begin + if (reset) begin + full0 <= 1'b0; + full1 <= 1'b0; + end else begin + // no data in pipeline + if (~full0 & ~full1) begin + if (in_valid) begin + full1 <= 1'b1; + end + end // ~f1 & ~f0 + + // one datum in pipeline + if (full1 & ~full0) begin + if (in_valid & ~out_ready) begin + full0 <= 1'b1; + end + // back to empty + if (~in_valid & out_ready) begin + full1 <= 1'b0; + end + end // f1 & ~f0 + + // two data in pipeline + if (full1 & full0) begin + // go back to one datum state + if (out_ready) begin + full0 <= 1'b0; + end + end // end go back to one datum stage + end + end + + end + else + begin : UNREGISTERED_READY_PLINE + + // in_ready will be a pass through of the out_ready signal as it is not registered + assign in_ready = (~full1) | out_ready; + + always @(posedge clk or posedge reset) begin + if (reset) begin + data1 <= 'b0; + full1 <= 1'b0; + end + else begin + if (in_ready) begin + data1 <= in_data; + full1 <= in_valid; + end + end + end + + end + endgenerate + + +endmodule diff --git a/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_address_alignment.sv b/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_address_alignment.sv new file mode 100644 index 00000000..ab1ab0ff --- /dev/null +++ b/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_address_alignment.sv @@ -0,0 +1,261 @@ +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/main/ip/merlin/altera_merlin_axi_master_ni/address_alignment.sv#3 $ +// $Revision: #3 $ +// $Date: 2012/07/11 $ +// $Author: tgngo $ + +//----------------------------------------- +// Address alignment: +// This component will aglin input address with input size +// Support address increment with butst type and burstwrap value +//----------------------------------------- +`timescale 1 ns / 1 ns + +module altera_merlin_address_alignment +#( + parameter + ADDR_W = 12, + BURSTWRAP_W = 12, + TYPE_W = 2, + SIZE_W = 3, + INCREMENT_ADDRESS = 1, + NUMSYMBOLS = 8, + SELECT_BITS = log2(NUMSYMBOLS), + IN_DATA_W = ADDR_W + (BURSTWRAP_W-1) + TYPE_W + SIZE_W, + OUT_DATA_W = ADDR_W + SELECT_BITS +) +( + input clk, + input reset, + + input [IN_DATA_W-1:0] in_data, // in_data = {wrap_boundary, address, type, size} + input in_valid, + //output in_ready, + input in_sop, + input in_eop, + + output reg [OUT_DATA_W-1:0] out_data, + input out_ready + //output out_valid + +); +typedef enum bit [1:0] +{ + FIXED = 2'b00, + INCR = 2'b01, + WRAP = 2'b10, + RESERVED = 2'b11 +} AxiBurstType; + //---------------------------------------------------- + // AXSIZE decoding + // + // Turns the axsize value into the actual number of bytes + // being transferred. + // --------------------------------------------------- + +function reg[7:0] bytes_in_transfer; + input [2:0] axsize; + case (axsize) + 3'b000: bytes_in_transfer = 8'b00000001; + 3'b001: bytes_in_transfer = 8'b00000010; + 3'b010: bytes_in_transfer = 8'b00000100; + 3'b011: bytes_in_transfer = 8'b00001000; + 3'b100: bytes_in_transfer = 8'b00010000; + 3'b101: bytes_in_transfer = 8'b00100000; + 3'b110: bytes_in_transfer = 8'b01000000; + 3'b111: bytes_in_transfer = 8'b10000000; + default:bytes_in_transfer = 8'b00000001; + endcase +endfunction + + //-------------------------------------- + // Burst type decode + //-------------------------------------- +AxiBurstType write_burst_type; + +function AxiBurstType burst_type_decode +( + input [1:0] axburst +); + AxiBurstType burst_type; + begin + case (axburst) + 2'b00 : burst_type = FIXED; + 2'b01 : burst_type = INCR; + 2'b10 : burst_type = WRAP; + 2'b11 : burst_type = RESERVED; + default : burst_type = INCR; + endcase + return burst_type; + end +endfunction + + //---------------------------------------------------- + // Ubiquitous, familiar log2 function + //---------------------------------------------------- +function integer log2; + input integer value; + + value = value - 1; + for(log2 = 0; value > 0; log2 = log2 + 1) + value = value >> 1; + +endfunction + //------------------------------------------------------------------------ + // This component will read address and size and check + // if this is aligned or not. If not then it will align this address to the size + // of the transfer: + // Check alignment: + // - With data width, can define maximun how many lower bits of address to indicate this + // address align to the size + // - Ex: 32 bits data => size can be: 1, 2, 4 bytes + // For 4 bytes: when 2 lower bits of address equal 0, this is aligned address + // addr=00|00| (0), 01|00| (4) => align to size of 4 bytes + // addr=00|01| (1) => start addr at 1, is not aligned to size 4 byte + // For 2 bytes: use last one bit to indicate algined or not + // addr=000|0| (0), 001|0| (2) => align to size of 2 bytes + // addr=000|1| (1), 001|1| (3) => not align to 2 bytes + // As size runtime change, creat mask and change accordingly to size, can detect address alignment + // and to align to size, apply this mask with zero to the address. + //------------------------------------------------------------------------- + + // THe function return a vector which has width [(SELECT_BITS * 2) -1 : 0] + // in which the first part contains the mask to check if this address aligned or not + // second part contains the mast to mask address to align to size + + function reg[(SELECT_BITS*2)-1 : 0] mask_select_and_align_address; + input [ADDR_W-1:0] address; + input [SIZE_W-1:0] size; // size is in AXI coding: 001 -> 2 bytes + + integer i; + reg [SELECT_BITS-1:0] mask_address; + reg [SELECT_BITS-1:0] check_unaligned; // any bits =1 -> unalgined (except size = 0; 1 byte) + mask_address = '1; + check_unaligned = '0; + for(i = 0; i < SELECT_BITS ; i = i + 1) begin + if (i < size) begin + check_unaligned[i] = address[i]; + mask_address[i] = 1'b0; + end + end + mask_select_and_align_address = {check_unaligned,mask_address}; + endfunction + + + + reg [ADDR_W-1 : 0] in_address; + reg [ADDR_W-1 : 0] first_address_aligned; + reg [SIZE_W-1 : 0] in_size; + reg [(SELECT_BITS*2)-1 : 0] output_masks; + // Extract information from input data + assign in_address = in_data[SIZE_W+ADDR_W-1 : SIZE_W]; + assign in_size = in_data[SIZE_W-1 : 0]; + + // Generate the masks + always_comb + begin + output_masks = mask_select_and_align_address(in_address, in_size); + end + + // Align address if needed + + generate + // SELECT_BITS == 1: input packet has 1 NUMSYMBOLS (1 bytes), it is aligned + if (SELECT_BITS == 0) + assign first_address_aligned = in_address; + else begin + // SELECT_BITS ==1 :input packet 2 bytes (2 SYMBOLS) + wire [SELECT_BITS-1 : 0] aligned_address_bits; + if (SELECT_BITS == 1) + assign aligned_address_bits = in_address[0] & output_masks[0]; + else + assign aligned_address_bits = in_address[SELECT_BITS-1:0] & output_masks[SELECT_BITS-1:0]; + assign first_address_aligned = {in_address[ADDR_W-1 : SELECT_BITS], aligned_address_bits}; + end + endgenerate + + + + // Increment address base on size, first address keep the same + generate + if (INCREMENT_ADDRESS) + begin + reg [ADDR_W-1 : 0] increment_address; + reg [ADDR_W-1 : 0] out_aligned_address_burst; + reg [ADDR_W-1 : 0] address_burst; + reg [ADDR_W-1 : 0] base_address; + reg [7 : 0] number_bytes_transfer; + reg [ADDR_W-1 : 0] burstwrap_mask; + reg [ADDR_W-1 : 0] burst_address_high; + reg [ADDR_W-1 : 0] burst_address_low; + reg [BURSTWRAP_W-2 :0] in_burstwrap_boundary; + reg [TYPE_W-1 : 0] in_type; + //------------------------------------------------ + // Use the extended burstwrap value to split the high (constant) and + // low (changing) part of the address + //----------------------------------------------- + assign in_type = in_data[SIZE_W+ADDR_W+TYPE_W-1 : SIZE_W+ADDR_W]; + assign in_burstwrap_boundary = in_data[IN_DATA_W-1 : ADDR_W+TYPE_W+SIZE_W]; + assign burstwrap_mask = {{(ADDR_W - BURSTWRAP_W){1'b0}}, in_burstwrap_boundary}; + assign burst_address_high = out_aligned_address_burst & ~burstwrap_mask; + assign burst_address_low = out_aligned_address_burst; + assign number_bytes_transfer = bytes_in_transfer(in_size); + assign write_burst_type = burst_type_decode(in_type); + + always @* + begin + if (in_sop) + begin + out_aligned_address_burst = in_address; + base_address = first_address_aligned; + end + else + begin + out_aligned_address_burst = address_burst; + base_address = out_aligned_address_burst; + end + case (write_burst_type) + INCR: + increment_address = base_address + number_bytes_transfer; + WRAP: + increment_address = ((burst_address_low + number_bytes_transfer) & burstwrap_mask) | burst_address_high; + FIXED: + increment_address = out_aligned_address_burst; + default: + increment_address = base_address + number_bytes_transfer; + endcase // case (write_burst_type) + end // always @ * + always_ff @(posedge clk, negedge reset) + begin + if (!reset) + begin + address_burst <= '0; + end + else + begin + if (in_valid & out_ready) + address_burst <= increment_address; + end + end + // send data to output with 2 part: [mask_t0_algin][address_aligned_increment] + assign out_data = {output_masks[SELECT_BITS-1 : 0], out_aligned_address_burst}; + end // if (INCREMENT_ADDRESS) + else + begin + assign out_data = {output_masks[SELECT_BITS-1 : 0], first_address_aligned}; + end // else: !if(INCREMENT_ADDRESS) + + endgenerate +endmodule diff --git a/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_arbitrator.sv b/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_arbitrator.sv new file mode 100644 index 00000000..9edba1d5 --- /dev/null +++ b/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_arbitrator.sv @@ -0,0 +1,270 @@ +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// (C) 2001-2010 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/main/ip/merlin/altera_merlin_std_arbitrator/altera_merlin_std_arbitrator_core.sv#3 $ +// $Revision: #3 $ +// $Date: 2010/07/07 $ +// $Author: jyeap $ + +/* ----------------------------------------------------------------------- +Round-robin/fixed arbitration implementation. + +Q: how do you find the least-significant set-bit in an n-bit binary number, X? + +A: M = X & (~X + 1) + +Example: X = 101000100 + 101000100 & + 010111011 + 1 = + + 101000100 & + 010111100 = + ----------- + 000000100 + +The method can be generalized to find the first set-bit +at a bit index no lower than bit-index N, simply by adding +2**N rather than 1. + + +Q: how does this relate to round-robin arbitration? +A: +Let X be the concatenation of all request signals. +Let the number to be added to X (hereafter called the +top_priority) initialize to 1, and be assigned from the +concatenation of the previous saved-grant, left-rotated +by one position, each time arbitration occurs. The +concatenation of grants is then M. + +Problem: consider this case: + +top_priority = 010000 +request = 001001 +~request + top_priority = 000110 +next_grant = 000000 <- no one is granted! + +There was no "set bit at a bit index no lower than bit-index 4", so +the result was 0. + +We need to propagate the carry out from (~request + top_priority) to the LSB, so +that the sum becomes 000111, and next_grant is 000001. This operation could be +called a "circular add". + +A bit of experimentation on the circular add reveals a significant amount of +delay in exiting and re-entering the carry chain - this will vary with device +family. Quartus also reports a combinational loop warning. Finally, +Modelsim 6.3g has trouble with the expression, evaluating it to 'X'. But +Modelsim _doesn't_ report a combinational loop!) + +An alternate solution: concatenate the request vector with itself, and OR +corresponding bits from the top and bottom halves to determine next_grant. + +Example: + +top_priority = 010000 +{request, request} = 001001 001001 +{~request, ~request} + top_priority = 110111 000110 +result of & operation = 000001 000000 +next_grant = 000001 + +Notice that if request = 0, the sum operation will overflow, but we can ignore +this; the next_grant result is 0 (no one granted), as you might expect. +In the implementation, the last-granted value must be maintained as +a non-zero value - best probably simply not to update it when no requests +occur. + +----------------------------------------------------------------------- */ + +`timescale 1 ns / 1 ns + +module altera_merlin_arbitrator +#( + parameter NUM_REQUESTERS = 8, + // -------------------------------------- + // Implemented schemes + // "round-robin" + // "fixed-priority" + // "no-arb" + // -------------------------------------- + parameter SCHEME = "round-robin", + parameter PIPELINE = 0 +) +( + input clk, + input reset, + + // -------------------------------------- + // Requests + // -------------------------------------- + input [NUM_REQUESTERS-1:0] request, + + // -------------------------------------- + // Grants + // -------------------------------------- + output [NUM_REQUESTERS-1:0] grant, + + // -------------------------------------- + // Control Signals + // -------------------------------------- + input increment_top_priority, + input save_top_priority +); + + // -------------------------------------- + // Signals + // -------------------------------------- + wire [NUM_REQUESTERS-1:0] top_priority; + reg [NUM_REQUESTERS-1:0] top_priority_reg; + reg [NUM_REQUESTERS-1:0] last_grant; + wire [2*NUM_REQUESTERS-1:0] result; + + // -------------------------------------- + // Scheme Selection + // -------------------------------------- + generate + if (SCHEME == "round-robin" && NUM_REQUESTERS > 1) begin + assign top_priority = top_priority_reg; + end + else begin + // Fixed arbitration (or single-requester corner case) + assign top_priority = 1'b1; + end + endgenerate + + // -------------------------------------- + // Decision Logic + // -------------------------------------- + altera_merlin_arb_adder + #( + .WIDTH (2 * NUM_REQUESTERS) + ) + adder + ( + .a ({ ~request, ~request }), + .b ({{NUM_REQUESTERS{1'b0}}, top_priority}), + .sum (result) + ); + + + generate if (SCHEME == "no-arb") begin + + // -------------------------------------- + // No arbitration: just wire request directly to grant + // -------------------------------------- + assign grant = request; + + end else begin + // Do the math in double-vector domain + wire [2*NUM_REQUESTERS-1:0] grant_double_vector; + assign grant_double_vector = {request, request} & result; + + // -------------------------------------- + // Extract grant from the top and bottom halves + // of the double vector. + // -------------------------------------- + assign grant = + grant_double_vector[NUM_REQUESTERS - 1 : 0] | + grant_double_vector[2 * NUM_REQUESTERS - 1 : NUM_REQUESTERS]; + + end + endgenerate + + // -------------------------------------- + // Left-rotate the last grant vector to create top_priority. + // -------------------------------------- + always @(posedge clk or posedge reset) begin + if (reset) begin + top_priority_reg <= 1'b1; + end + else begin + if (PIPELINE) begin + if (increment_top_priority) begin + top_priority_reg <= (|request) ? {grant[NUM_REQUESTERS-2:0], + grant[NUM_REQUESTERS-1]} : top_priority_reg; + end + end else begin + if (save_top_priority) begin + top_priority_reg <= grant; + end + if (increment_top_priority) begin + if (|request) + top_priority_reg <= { grant[NUM_REQUESTERS-2:0], + grant[NUM_REQUESTERS-1] }; + else + top_priority_reg <= { top_priority_reg[NUM_REQUESTERS-2:0], top_priority_reg[NUM_REQUESTERS-1] }; + end + end + end + end + +endmodule + +// ---------------------------------------------- +// Adder for the standard arbitrator +// ---------------------------------------------- +module altera_merlin_arb_adder +#( + parameter WIDTH = 8 +) +( + input [WIDTH-1:0] a, + input [WIDTH-1:0] b, + + output [WIDTH-1:0] sum +); + + // ---------------------------------------------- + // Benchmarks indicate that for small widths, the full + // adder has higher fmax because synthesis can merge + // it with the mux, allowing partial decisions to be + // made early. + // + // The magic number is 4 requesters, which means an + // 8 bit adder. + // ---------------------------------------------- + genvar i; + generate if (WIDTH <= 8) begin : full_adder + + wire cout[WIDTH-1:0]; + + assign sum[0] = (a[0] ^ b[0]); + assign cout[0] = (a[0] & b[0]); + + for (i = 1; i < WIDTH; i = i+1) begin : arb + + assign sum[i] = (a[i] ^ b[i]) ^ cout[i-1]; + assign cout[i] = (a[i] & b[i]) | (cout[i-1] & (a[i] ^ b[i])); + + end + + end else begin : carry_chain + + assign sum = a + b; + + end + endgenerate + +endmodule diff --git a/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_burst_adapter.sv b/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_burst_adapter.sv new file mode 100644 index 00000000..14e2eee9 --- /dev/null +++ b/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_burst_adapter.sv @@ -0,0 +1,1365 @@ +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// (C) 2001-2012 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/12.1sp1/ip/merlin/altera_merlin_burst_adapter/altera_merlin_burst_adapter.sv#1 $ +// $Revision: #1 $ +// $Date: 2012/10/10 $ +// $Author: swbranch $ + +// ------------------------------------------------------- +// Merlin Burst Adapter +// ------------------------------------------------------- + +`timescale 1 ns / 1 ns + +// + 1 +// By definition, burstwrap values are of the form 2^n - 1; adding 1 is a non-ripple operation. +module altera_merlin_burst_adapter_burstwrap_increment #(parameter WIDTH = 8) + ( + input [WIDTH - 1:0] mask, + output [WIDTH - 1:0] inc + ); + genvar i; + generate begin : burstwrap_increment_gen + assign inc[0] = ~mask[0]; + for (i = 1; i < WIDTH; i = i+1) begin : burstwrap_increment_loop + assign inc[i] = mask[i - 1] & ~mask[i]; + end + end + endgenerate +endmodule + +module altera_merlin_burst_adapter_adder #(parameter WIDTH = 8) ( + input cin, + input [WIDTH-1 : 0] a, + input [WIDTH-1 : 0] b, + output [WIDTH-1 : 0] sum + ); + + genvar i; + generate begin : full_adder + wire [WIDTH-1:0] carry; + assign sum[0] = a[0] ^ b[0] ^ cin; + assign carry[0] = a[0] & b[0] | a[0] & cin | b[0] & cin; + + for (i = 1; i < WIDTH; i = i+1) begin : full_adder_loop + assign sum[i] = a[i] ^ b[i] ^ carry[i-1]; + assign carry[i] = a[i] & b[i] | a[i] & carry[i-1] | b[i] & carry[i-1]; + end + + end endgenerate +endmodule + +// a - b = a + ~b + 1 +module altera_merlin_burst_adapter_subtractor #(parameter WIDTH = 8) ( + input [WIDTH-1 : 0] a, + input [WIDTH-1 : 0] b, + output [WIDTH-1 : 0] diff + ); + + altera_merlin_burst_adapter_adder #(.WIDTH (WIDTH)) subtract ( + .cin (1'b1), + .a (a), + .b (~b), + .sum (diff) + ); +endmodule + +// Pipeline position: +// 0: register module inputs +// 1: register module output +// I would have expected that with register retiming/duplication turned on, the +// pipeline position parameter would have no effect. Not so, +// PIPELINE_POSITION=1 is significantly better than PIPELINE_POSITION=0. + +module altera_merlin_burst_adapter_min #(parameter PKT_BYTE_CNT_W=8, PKT_BURSTWRAP_W=8, PIPELINE_POSITION = 1) + ( + input clk, + input reset, + input [PKT_BYTE_CNT_W - 1 : 0] a, + input [PKT_BYTE_CNT_W - 1 : 0] b, + input [PKT_BURSTWRAP_W - 1 : 0] c, + input c_enable, + input [PKT_BYTE_CNT_W - 1 : 0] d, + output reg [PKT_BYTE_CNT_W - 1 : 0] result + ); + + wire [PKT_BYTE_CNT_W : 0] ab_diff; + wire [PKT_BYTE_CNT_W : 0] ac_diff; + wire [PKT_BYTE_CNT_W : 0] bc_diff; + wire a_lt_b; + wire a_lt_c; + wire b_lt_c; + + reg [PKT_BYTE_CNT_W - 1 : 0] a_reg; + reg [PKT_BYTE_CNT_W - 1 : 0] b_reg; + reg [PKT_BURSTWRAP_W - 1 : 0] c_reg; + reg c_enable_reg; + reg [PKT_BYTE_CNT_W - 1 : 0] d_reg; + + generate + if (PIPELINE_POSITION == 0) begin + always_ff @(posedge clk or posedge reset) begin + if (reset) begin + a_reg <= '0; + b_reg <= '0; + c_reg <= '0; + c_enable_reg <= '0; + d_reg <= '0; + end + else begin + a_reg <= a; + b_reg <= b; + c_reg <= c; + c_enable_reg <= c_enable; + d_reg <= d; + end + end + end + else begin + always @* begin + a_reg = a; + b_reg = b; + c_reg = c; + c_enable_reg = c_enable; + d_reg = d; + end + end + endgenerate + + altera_merlin_burst_adapter_subtractor #(.WIDTH (PKT_BYTE_CNT_W + 1)) ab_sub ( + .a ({1'b0, a_reg}), + .b ({1'b0, b_reg}), + .diff (ab_diff) + ); + assign a_lt_b = ab_diff[PKT_BYTE_CNT_W]; + + altera_merlin_burst_adapter_subtractor #(.WIDTH (PKT_BYTE_CNT_W + 1)) ac_sub ( + .a ({1'b0, a_reg}), + .b ({{(PKT_BYTE_CNT_W - PKT_BURSTWRAP_W + 1) {1'b0}}, c_reg}), + .diff (ac_diff) + ); + assign a_lt_c = ac_diff[PKT_BYTE_CNT_W]; + + altera_merlin_burst_adapter_subtractor #(.WIDTH (PKT_BYTE_CNT_W + 1)) bc_sub ( + .a ({1'b0, b_reg}), + .b ({ {(PKT_BYTE_CNT_W - PKT_BURSTWRAP_W + 1) {1'b0}}, c_reg}), + .diff (bc_diff) + ); + assign b_lt_c = bc_diff[PKT_BYTE_CNT_W]; + + // If d is greater than any of the values, it'll be greater than the min, + // certainly. If d is greater than the min, use d. Of course, ignore c if + // !c_enable. + + // Note: d is "number-of-symbols", of width PKT_BYTE_CNT_W. So, a constant, + // and a power of 2 (until we support non-power-of-2 symbols/interface + // here). + // wire use_d = (d > a) || (d > b) || ( (d > c) && c_enable); + // I think there's something clever I can do with masks, but my head hurts, + // so try something simpler. + // wire use_d = + // (&(~a[PKT_BYTE_CNT_W - 1:LOG2_NUMSYMBOLS])) || + // (&(~b[PKT_BYTE_CNT_W-1:LOG2_NUMSYMBOLS])) || + // ((&(~c[PKT_BURSTWRAP_W-1:LOG2_NUMSYMBOLS])) && c_enable + // ); + wire [PKT_BYTE_CNT_W : 0] da_diff; + wire [PKT_BYTE_CNT_W : 0] db_diff; + wire [PKT_BYTE_CNT_W : 0] dc_diff; + wire d_gt_a; + wire d_gt_b; + wire d_gt_c; + + altera_merlin_burst_adapter_subtractor #(.WIDTH (PKT_BYTE_CNT_W + 1)) da_sub ( + .a ({1'b0, d_reg}), + .b ({1'b0, a_reg}), + .diff (da_diff) + ); + assign d_gt_a = ~da_diff[PKT_BYTE_CNT_W]; + + altera_merlin_burst_adapter_subtractor #(.WIDTH (PKT_BYTE_CNT_W + 1)) db_sub ( + .a ({1'b0, d_reg}), + .b ({1'b0, b_reg}), + .diff (db_diff) + ); + assign d_gt_b = ~db_diff[PKT_BYTE_CNT_W]; + + altera_merlin_burst_adapter_subtractor #(.WIDTH (PKT_BYTE_CNT_W + 1)) dc_sub ( + .a ({1'b0, d_reg}), + .b ({ {(PKT_BYTE_CNT_W - PKT_BURSTWRAP_W + 1) {1'b0}}, c_reg}), + .diff (dc_diff) + ); + assign d_gt_c = ~(d_reg < c_reg); // kevtan mod ~dc_diff[PKT_BYTE_CNT_W]; + + wire use_d = d_gt_a || d_gt_b || (d_gt_c && c_enable_reg); + + wire [4:0] cmp = {a_lt_b, a_lt_c, b_lt_c, c_enable_reg, use_d}; + + reg [PKT_BYTE_CNT_W - 1 : 0] p1_result; + always @(a_reg or b_reg or c_reg or d_reg or cmp) begin + casex (cmp) + 5'b00010: p1_result = c_reg; + 5'b00110: p1_result = b_reg; + 5'b01110: p1_result = b_reg; + 5'b10010: p1_result = c_reg; + 5'b11010: p1_result = a_reg; + 5'b11110: p1_result = a_reg; + + 5'b00000: p1_result = b_reg; + 5'b00100: p1_result = b_reg; + 5'b01100: p1_result = b_reg; + 5'b10000: p1_result = a_reg; + 5'b11000: p1_result = a_reg; + 5'b11100: p1_result = a_reg; + + 5'b????1: p1_result = d_reg; + + default: p1_result = 'X; // don't-care + endcase + end + + generate + if (PIPELINE_POSITION == 1) begin + always_ff @(posedge clk or posedge reset) begin + if (reset) begin + result <= '0; + end + else begin + result <= p1_result; + end + end + end + else begin + always @* begin + result = p1_result; + end + end + endgenerate +endmodule + + +module altera_merlin_burst_adapter +#( + parameter // Merlin packet parameters + PKT_BEGIN_BURST = 81, + PKT_ADDR_H = 79, + PKT_ADDR_L = 48, + PKT_BYTE_CNT_H = 5, + PKT_BYTE_CNT_L = 0, + PKT_BURSTWRAP_H = 11, + PKT_BURSTWRAP_L = 6, + PKT_TRANS_COMPRESSED_READ = 14, + PKT_TRANS_WRITE = 13, + PKT_TRANS_READ = 12, + PKT_BYTEEN_H = 83, + PKT_BYTEEN_L = 80, + PKT_BURST_TYPE_H = 88, + PKT_BURST_TYPE_L = 87, + PKT_BURST_SIZE_H = 86, + PKT_BURST_SIZE_L = 84, + IN_NARROW_SIZE = 0, + OUT_NARROW_SIZE = 0, + OUT_FIXED = 0, + OUT_COMPLETE_WRAP = 0, + ST_DATA_W = 89, + ST_CHANNEL_W = 8, + + // Component-specific parameters + BYTEENABLE_SYNTHESIS = 0, + BURSTWRAP_CONST_MASK = 0, + BURSTWRAP_CONST_VALUE = -1, + NO_WRAP_SUPPORT = 0, + PIPE_INPUTS = 0, + OUT_BYTE_CNT_H = 5, + OUT_BURSTWRAP_H = 11, + COMPRESSED_READ_SUPPORT = 1 +) +( + input clk, + input reset, + + // ------------------- + // Command Sink (Input) + // ------------------- + input sink0_valid, + input [ST_DATA_W-1 : 0] sink0_data, + input [ST_CHANNEL_W-1 : 0] sink0_channel, + input sink0_startofpacket, + input sink0_endofpacket, + output reg sink0_ready, + + // ------------------- + // Command Source (Output) + // ------------------- + output reg source0_valid, + output reg [ST_DATA_W-1 : 0] source0_data, + output reg [ST_CHANNEL_W-1 : 0] source0_channel, + output reg source0_startofpacket, + output reg source0_endofpacket, + input source0_ready +); + localparam PKT_BURSTWRAP_W = PKT_BURSTWRAP_H - PKT_BURSTWRAP_L + 1; + + generate if (COMPRESSED_READ_SUPPORT == 1) begin : altera_merlin_burst_adapter_full + altera_merlin_burst_adapter_full #( + .PKT_BEGIN_BURST (PKT_BEGIN_BURST), + .PKT_ADDR_H (PKT_ADDR_H ), + .PKT_ADDR_L (PKT_ADDR_L), + .PKT_BYTE_CNT_H (PKT_BYTE_CNT_H), + .PKT_BYTE_CNT_L (PKT_BYTE_CNT_L ), + .PKT_BURSTWRAP_H (PKT_BURSTWRAP_H), + .PKT_BURSTWRAP_L (PKT_BURSTWRAP_L), + .PKT_TRANS_COMPRESSED_READ (PKT_TRANS_COMPRESSED_READ), + .PKT_TRANS_WRITE (PKT_TRANS_WRITE), + .PKT_TRANS_READ (PKT_TRANS_READ), + .PKT_BYTEEN_H (PKT_BYTEEN_H), + .PKT_BYTEEN_L (PKT_BYTEEN_L), + .PKT_BURST_TYPE_H (PKT_BURST_TYPE_H), + .PKT_BURST_TYPE_L (PKT_BURST_TYPE_L), + .PKT_BURST_SIZE_H (PKT_BURST_SIZE_H), + .PKT_BURST_SIZE_L (PKT_BURST_SIZE_L), + .IN_NARROW_SIZE (IN_NARROW_SIZE), + .BYTEENABLE_SYNTHESIS (BYTEENABLE_SYNTHESIS), + .OUT_NARROW_SIZE (OUT_NARROW_SIZE), + .OUT_FIXED (OUT_FIXED), + .OUT_COMPLETE_WRAP (OUT_COMPLETE_WRAP), + .ST_DATA_W (ST_DATA_W), + .ST_CHANNEL_W (ST_CHANNEL_W), + .BURSTWRAP_CONST_MASK (BURSTWRAP_CONST_MASK), + .BURSTWRAP_CONST_VALUE (BURSTWRAP_CONST_VALUE), + .PIPE_INPUTS (PIPE_INPUTS), + .NO_WRAP_SUPPORT (NO_WRAP_SUPPORT), + .OUT_BYTE_CNT_H (OUT_BYTE_CNT_H), + .OUT_BURSTWRAP_H (OUT_BURSTWRAP_H) + ) the_ba( + .clk (clk), + .reset (reset), + .sink0_valid (sink0_valid), + .sink0_data (sink0_data), + .sink0_channel (sink0_channel), + .sink0_startofpacket (sink0_startofpacket), + .sink0_endofpacket (sink0_endofpacket), + .sink0_ready (sink0_ready), + .source0_valid (source0_valid), + .source0_data (source0_data), + .source0_channel (source0_channel), + .source0_startofpacket (source0_startofpacket), + .source0_endofpacket (source0_endofpacket), + .source0_ready (source0_ready) + ); + end + else begin : altera_merlin_burst_adapter_uncompressed_only + altera_merlin_burst_adapter_uncompressed_only #( + .PKT_BYTE_CNT_H (PKT_BYTE_CNT_H), + .PKT_BYTE_CNT_L (PKT_BYTE_CNT_L ), + .PKT_BYTEEN_H (PKT_BYTEEN_H), + .PKT_BYTEEN_L (PKT_BYTEEN_L), + .ST_DATA_W (ST_DATA_W), + .ST_CHANNEL_W (ST_CHANNEL_W) + ) the_ba( + .clk (clk), + .reset (reset), + .sink0_valid (sink0_valid), + .sink0_data (sink0_data), + .sink0_channel (sink0_channel), + .sink0_startofpacket (sink0_startofpacket), + .sink0_endofpacket (sink0_endofpacket), + .sink0_ready (sink0_ready), + .source0_valid (source0_valid), + .source0_data (source0_data), + .source0_channel (source0_channel), + .source0_startofpacket (source0_startofpacket), + .source0_endofpacket (source0_endofpacket), + .source0_ready (source0_ready) + ); + end endgenerate + + // synthesis translate_off + // Check for incoming burstwrap values inconsistent with + // BURSTWRAP_CONST_MASK. + always @(posedge clk or posedge reset) begin + if (~reset && sink0_valid && + BURSTWRAP_CONST_MASK[PKT_BURSTWRAP_W - 1:0] & + (BURSTWRAP_CONST_VALUE[PKT_BURSTWRAP_W - 1:0] ^ sink0_data[PKT_BURSTWRAP_H : PKT_BURSTWRAP_L]) + ) begin + $display("%t: %m: Error: burstwrap value %X is inconsistent with BURSTWRAP_CONST_MASK value %X", $time(), sink0_data[PKT_BURSTWRAP_H : PKT_BURSTWRAP_L], BURSTWRAP_CONST_MASK[PKT_BURSTWRAP_W - 1:0]); + end + end + // synthesis translate_on +endmodule + +module altera_merlin_burst_adapter_uncompressed_only +#( + parameter // Merlin packet parameters + PKT_BYTE_CNT_H = 5, + PKT_BYTE_CNT_L = 0, + PKT_BYTEEN_H = 83, + PKT_BYTEEN_L = 80, + ST_DATA_W = 84, + ST_CHANNEL_W = 8 +) +( + input clk, + input reset, + + // ------------------- + // Command Sink (Input) + // ------------------- + input sink0_valid, + input [ST_DATA_W-1 : 0] sink0_data, + input [ST_CHANNEL_W-1 : 0] sink0_channel, + input sink0_startofpacket, + input sink0_endofpacket, + output reg sink0_ready, + + // ------------------- + // Command Source (Output) + // ------------------- + output reg source0_valid, + output reg [ST_DATA_W-1 : 0] source0_data, + output reg [ST_CHANNEL_W-1 : 0] source0_channel, + output reg source0_startofpacket, + output reg source0_endofpacket, + input source0_ready +); + localparam + PKT_BYTE_CNT_W = PKT_BYTE_CNT_H - PKT_BYTE_CNT_L + 1, + NUM_SYMBOLS = PKT_BYTEEN_H - PKT_BYTEEN_L + 1; + + wire [PKT_BYTE_CNT_W - 1 : 0] num_symbols_sig = NUM_SYMBOLS[PKT_BYTE_CNT_W - 1 : 0]; + + always_comb begin : source0_data_assignments + source0_valid = sink0_valid; + source0_channel = sink0_channel; + source0_startofpacket = sink0_startofpacket; + source0_endofpacket = sink0_endofpacket; + sink0_ready = source0_ready; + + source0_data = sink0_data; + source0_data[PKT_BYTE_CNT_H : PKT_BYTE_CNT_L] = num_symbols_sig; + end + +endmodule + + +module altera_merlin_burst_adapter_full +#( + parameter // Merlin packet parameters + PKT_BEGIN_BURST = 81, + PKT_ADDR_H = 79, + PKT_ADDR_L = 48, + PKT_BYTE_CNT_H = 5, + PKT_BYTE_CNT_L = 0, + PKT_BURSTWRAP_H = 11, + PKT_BURSTWRAP_L = 6, + PKT_TRANS_COMPRESSED_READ = 14, + PKT_TRANS_WRITE = 13, + PKT_TRANS_READ = 12, + PKT_BYTEEN_H = 83, + PKT_BYTEEN_L = 80, + PKT_BURST_TYPE_H = 88, + PKT_BURST_TYPE_L = 87, + PKT_BURST_SIZE_H = 86, + PKT_BURST_SIZE_L = 84, + IN_NARROW_SIZE = 0, + OUT_NARROW_SIZE = 0, + OUT_FIXED = 0, + OUT_COMPLETE_WRAP = 0, + ST_DATA_W = 89, + ST_CHANNEL_W = 8, + + // Component-specific parameters + BYTEENABLE_SYNTHESIS = 0, + BURSTWRAP_CONST_MASK = 0, + PIPE_INPUTS = 0, + NO_WRAP_SUPPORT = 0, + BURSTWRAP_CONST_VALUE = -1, + OUT_BYTE_CNT_H = 5, + OUT_BURSTWRAP_H = 11 +) +( + + input clk, + input reset, + + // ------------------- + // Command Sink (Input) + // ------------------- + input sink0_valid, + input [ST_DATA_W-1 : 0] sink0_data, + input [ST_CHANNEL_W-1 : 0] sink0_channel, + input sink0_startofpacket, + input sink0_endofpacket, + output reg sink0_ready, + + // ------------------- + // Command Source (Output) + // ------------------- + output reg source0_valid, + output reg [ST_DATA_W-1 : 0] source0_data, + output reg [ST_CHANNEL_W-1 : 0] source0_channel, + output reg source0_startofpacket, + output reg source0_endofpacket, + input source0_ready +); + localparam + PKT_BYTE_CNT_W = PKT_BYTE_CNT_H - PKT_BYTE_CNT_L + 1, + PKT_ADDR_W = PKT_ADDR_H - PKT_ADDR_L + 1, + PKT_BYTEEN_W = PKT_BYTEEN_H - PKT_BYTEEN_L + 1, + OUT_BYTE_CNT_W = OUT_BYTE_CNT_H - PKT_BYTE_CNT_L + 1, + OUT_BURSTWRAP_W = OUT_BURSTWRAP_H - PKT_BURSTWRAP_L + 1, + PKT_BURSTWRAP_W = PKT_BURSTWRAP_H - PKT_BURSTWRAP_L + 1, + OUT_MAX_BYTE_CNT = 1 << (OUT_BYTE_CNT_W - 1), + OUT_MAX_BURSTWRAP = (1 << OUT_BURSTWRAP_W) - 1, + NUM_SYMBOLS = PKT_BYTEEN_H - PKT_BYTEEN_L + 1, + PKT_BURST_SIZE_W = PKT_BURST_SIZE_H - PKT_BURST_SIZE_L + 1, + PKT_BURST_TYPE_W = PKT_BURST_TYPE_H - PKT_BURST_TYPE_L + 1, + LOG2_NUM_SYMBOLS = (NUM_SYMBOLS == 1) ? 1 :log2ceil(NUM_SYMBOLS); + + // "min" operation on burstwrap values is a bitwise AND. + // Todo: one input is always set to constant OUT_MAX_BURSTWRAP; this is a + // number of the form 2^n. Does this fact yield an optimization? + function [PKT_BURSTWRAP_W - 1 : 0] altera_merlin_burst_adapter_burstwrap_min( + input [PKT_BURSTWRAP_W - 1 : 0] a, b + ); + altera_merlin_burst_adapter_burstwrap_min = a & b; + endfunction + + // -------------------------------------------------- + // Ceil(log2()) function + // -------------------------------------------------- + function unsigned[63:0] log2ceil; + input reg[63:0] val; + reg [63:0] i; + + begin + i = 1; + log2ceil = 0; + + while (i < val) begin + log2ceil = log2ceil + 1; + i = i << 1; + end + end + endfunction + + //---------------------------------------------------- + // AXSIZE encoding: run-time size of the transaction. + // --------------------------------------------------- + function reg[127:0] set_byteenable_based_on_size; + input [2:0] axsize; + begin + case (axsize) + 3'b000: set_byteenable_based_on_size = 128'h00000000000000000000000000000001; + 3'b001: set_byteenable_based_on_size = 128'h00000000000000000000000000000003; + 3'b010: set_byteenable_based_on_size = 128'h0000000000000000000000000000000F; + 3'b011: set_byteenable_based_on_size = 128'h000000000000000000000000000000FF; + 3'b100: set_byteenable_based_on_size = 128'h0000000000000000000000000000FFFF; + 3'b101: set_byteenable_based_on_size = 128'h000000000000000000000000FFFFFFFF; + 3'b110: set_byteenable_based_on_size = 128'h0000000000000000FFFFFFFFFFFFFFFF; + 3'b111: set_byteenable_based_on_size = 128'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; + default:set_byteenable_based_on_size = 128'h00000000000000000000000000000001; + endcase + end + endfunction + + // --------------------------------------------------- + // STATE MACHINE DEFINITIONS + // --------------------------------------------------- + typedef enum bit [2:0] { // int unsigned { + ST_IDLE = 3'b000, + ST_COMP_TRANS = 3'b001, // This state is used for compressed transactions + // - Address and byte count needs to be calculated for every round internally + ST_UNCOMP_TRANS = 3'b010, // This state is used for uncompressed transaction where address is passthrough + // and bytecount is decremented based on max + ST_UNCOMP_WR_SUBBURST = 3'b100 + } t_state; + t_state state, next_state; + + // --------------------------------------------------- + // AXI Burst Type Encoding + // --------------------------------------------------- + typedef enum bit [1:0] + { + FIXED = 2'b00, + INCR = 2'b01, + WRAP = 2'b10, + RESERVED = 2'b11 + } AxiBurstType; + + // ------------------------------ + // Note on signal naming convention used + // in_* --> These signals are either coming directly from sink or a combi off the sink signals + // --> Timing - zero cycle + // d0_in_* --> Signals that are to be used in this block. It is off a mux between in_* signals + // and the 'saved' version of the signals + // --> Timing - zero cycle (IF PIPE_INPUTS == 0) + // d1_in_* --> Signals that are output of initial flop stage. + // --> Timing - always delayed by 1 clock. (vs the input) + + // ------------------------------ + // CONSTANTS + // ------------------------------ + wire [PKT_BYTE_CNT_W - 1 : 0] num_symbols_sig = NUM_SYMBOLS [PKT_BYTE_CNT_W - 1 : 0]; + wire [PKT_BYTE_CNT_W - 1 : 0] out_max_byte_cnt_sig = OUT_MAX_BYTE_CNT [PKT_BYTE_CNT_W - 1 : 0]; + + // quartus integration failure + wire [63:0] log2_numsymbols = log2ceil(NUM_SYMBOLS); + wire [PKT_BURST_SIZE_W - 1 : 0] encoded_numsymbols = log2_numsymbols[PKT_BURST_SIZE_W-1:0]; + + // --------------------------------------------------- + // INPUT STAGE SIGNALS CONDITIONING + // --------------------------------------------------- + + // Internal wires + reg [ST_DATA_W - 1 : 0 ] d1_in_data; + reg [ST_CHANNEL_W - 1 : 0 ] d1_in_channel; + reg [PKT_BURST_SIZE_W - 1 : 0] d1_in_size; + reg [PKT_BURST_TYPE_W - 1 : 0] d1_in_bursttype; + reg [PKT_BYTEEN_W - 1 : 0] d1_in_byteen; + reg [PKT_BURST_SIZE_W - 1 : 0] d0_in_size; + reg [PKT_BURSTWRAP_W - 1 : 0] d0_in_burstwrap; + reg [PKT_BURST_TYPE_W - 1 : 0] d0_in_bursttype; + reg [PKT_ADDR_W - 1 : 0] d0_in_addr; + reg [PKT_BYTE_CNT_W - 1 : 0] d0_in_bytecount; + reg d0_in_narrow; + reg d0_in_passthru; + reg d0_in_valid; + reg d0_in_sop; + reg d0_in_compressed_read; + reg d0_in_write; + reg d0_in_uncompressed_read; + reg d1_in_eop; + reg d1_in_uncompressed_read; + reg d1_in_narrow; + + reg [PKT_BYTE_CNT_W - 1 : 0] the_min_byte_cnt_or_num_sym; + + wire [PKT_BURSTWRAP_W - 1 : 0] wrap_mask; + wire [PKT_BURSTWRAP_W - 1 : 0] incremented_wrap_mask; + reg disable_wrap_dist_calc; + + // Input stage registers + reg [ST_DATA_W - 1 : 0] in_data_reg; + reg [ST_CHANNEL_W-1 : 0] in_channel_reg; + reg [PKT_BYTEEN_W - 1 : 0] in_byteen_reg; + reg [PKT_BURST_SIZE_W - 1 : 0] in_size_reg; + reg [PKT_BURSTWRAP_W - 1 : 0] in_burstwrap_reg; + reg [PKT_BURST_TYPE_W - 1 : 0] in_bursttype_reg; + reg [PKT_ADDR_W - 1 : 0] in_addr_reg; + reg [PKT_BYTE_CNT_W - 1 : 0] in_bytecount_reg; + reg in_compressed_read_reg; + reg in_uncompressed_read_reg; + reg in_narrow_reg; // Holds the flag until next burst command. + reg in_passthru_reg; // Holds flag until next start of packet command + reg in_eop_reg; + reg in_bytecount_reg_zero; + reg in_write_reg; + reg in_valid_reg; + reg in_sop_reg; + + + // Length coversion + reg [PKT_ADDR_W - 1 : 0] int_nxt_addr_reg; + reg [PKT_ADDR_W - 1 : 0] int_nxt_addr_reg_dly; + reg [PKT_BYTE_CNT_W - 1 : 0] int_bytes_remaining_reg; + reg [PKT_BYTE_CNT_W - 1 : 0] out_uncomp_byte_cnt_reg; + reg [PKT_BURSTWRAP_W - 1 :0] int_dist_reg; + reg new_burst_reg; + reg [PKT_BYTE_CNT_W -1:0] int_byte_cnt_narrow_reg; + + reg [PKT_ADDR_W - 1 : 0 ] nxt_addr; + reg [PKT_ADDR_W - 1 : 0 ] nxt_addr2; + reg [PKT_BYTE_CNT_W - 1 : 0] nxt_byte_cnt; + reg [PKT_BYTE_CNT_W - 1 : 0] nxt_uncomp_subburst_byte_cnt; + reg [PKT_BYTE_CNT_W - 1 : 0] nxt_byte_remaining; + reg [PKT_BURSTWRAP_W - 1 : 0] nxt_dist; + reg [PKT_ADDR_W - 1 : 0] extended_burstwrap; + + reg [PKT_BYTE_CNT_W -1 :0] d0_int_bytes_remaining; + reg [PKT_ADDR_W - 1 : 0 ] d0_int_nxt_addr; + reg [PKT_BURSTWRAP_W - 1 : 0 ] d0_int_dist; + + // Output registers + reg [PKT_ADDR_W - 1 : 0] out_addr_reg; + reg out_valid_reg; + reg out_sop_reg; + reg out_eop_reg; + reg [PKT_BURSTWRAP_W - 1 : 0] out_burstwrap_reg; + reg [PKT_BYTE_CNT_W - 1 : 0] out_byte_cnt_reg; + reg nxt_in_ready; + +// wire [PKT_ADDR_W - 1 : 0] nxt_out_addr; + wire nxt_out_valid; + wire nxt_out_sop; + wire nxt_out_eop; + wire [PKT_BURSTWRAP_W - 1 : 0] nxt_out_burstwrap; +// wire [PKT_BYTE_CNT_W - 1 : 0] nxt_bytecount; + + // ---------------- + // ALIAS INPUT MAPPINGS + // ----------------- + // cmd PKT_TRANS_COMPRESSED_READ PKT_TRANS_READ PKT_TRANS_WRITE + // read 0 1 0 + // compressed read 1 1 0 + // write 0 0 1 + // N.b. The fabric sets both PKT_TRANS_COMPRESSED_READ and PKT_TRANS_READ ??? + wire in_compressed_read = sink0_data [PKT_TRANS_COMPRESSED_READ]; + wire in_write = sink0_data [PKT_TRANS_WRITE]; + wire in_read = sink0_data [PKT_TRANS_READ]; + wire in_uncompressed_read = in_read & ~sink0_data [PKT_TRANS_COMPRESSED_READ]; + + wire [ST_DATA_W - 1 : 0] in_data = sink0_data; + wire in_valid = sink0_valid; + wire in_sop = sink0_startofpacket; + wire in_eop = sink0_endofpacket; + wire [ST_CHANNEL_W - 1 : 0] in_channel = sink0_channel; + + wire [PKT_ADDR_W - 1 : 0 ] in_addr = sink0_data[PKT_ADDR_H : PKT_ADDR_L]; + wire [PKT_BYTEEN_W - 1 : 0] in_byteen = sink0_data[PKT_BYTEEN_H : PKT_BYTEEN_L]; + wire [PKT_BYTE_CNT_W - 1 : 0] in_bytecount = sink0_data[PKT_BYTE_CNT_H : PKT_BYTE_CNT_L]; + wire [PKT_BURST_SIZE_W - 1 : 0] in_size = IN_NARROW_SIZE ? sink0_data[PKT_BURST_SIZE_H : PKT_BURST_SIZE_L] : encoded_numsymbols; + + // Signals decoded based on inputs + wire [PKT_BYTE_CNT_W - 1 : 0] in_burstcount = in_bytecount >> log2_numsymbols[PKT_BYTE_CNT_W -1 :0]; + wire in_narrow = in_size < log2_numsymbols[PKT_BYTE_CNT_W -1 :0]; + wire in_passthru = in_burstcount <= 16; + + wire [PKT_BURST_TYPE_W - 1 : 0] in_bursttype = ~(in_passthru & in_sop | !in_sop & d0_in_passthru) && OUT_NARROW_SIZE ? INCR : sink0_data[PKT_BURST_TYPE_H : PKT_BURST_TYPE_L]; + wire [PKT_BURSTWRAP_W - 1 : 0] in_burstwrap; + + genvar i; + generate begin : constant_or_variable_burstwrap + for (i = 0; i < PKT_BURSTWRAP_W; i = i + 1) begin : assign_burstwrap_bit + if (BURSTWRAP_CONST_MASK[i]) begin + assign in_burstwrap[i] = BURSTWRAP_CONST_VALUE[i]; + end + else begin + assign in_burstwrap[i] = sink0_data[PKT_BURSTWRAP_L + i]; + end + end + end endgenerate + + // ---------------------------------- + // Input Load control signals + // ---------------------------------- + +generate if (PIPE_INPUTS == 0) + begin : NON_PIPELINED_INPUTS + + // Used to capture sink signals as each incoming cycle is accepted. + wire load_next_cmd = d0_in_valid & sink0_ready; + + // Used to capture sink signals as each incoming transaction (currently only used by passthru generation) + wire load_next_pkt = d0_in_valid & sink0_ready & d0_in_sop; + + always_ff @(posedge clk or posedge reset) begin + if (reset) begin + in_channel_reg <= '0; + in_data_reg <= '0; + in_burstwrap_reg <= '0; + in_bursttype_reg <= '0; + in_byteen_reg <= '0; + in_narrow_reg <= '0; + in_size_reg <= '0; + in_passthru_reg <= '0; + in_eop_reg <= '0; + in_bytecount_reg_zero <= '0; + in_uncompressed_read_reg <= '0; + end + else begin + if (load_next_cmd) begin + in_channel_reg <= in_channel; + in_data_reg <= in_data; + in_burstwrap_reg <= in_burstwrap; + in_bursttype_reg <= in_bursttype; + in_byteen_reg <= in_byteen; + in_narrow_reg <= in_narrow; + in_size_reg <= in_size; + in_bytecount_reg_zero <= ~|in_bytecount; + in_uncompressed_read_reg <= in_uncompressed_read; + in_eop_reg <= in_eop; + end + + // Passthru is evaluated every transaction + if (load_next_pkt) begin + in_passthru_reg <= in_passthru; + end + end + end + + assign d0_in_size = new_burst_reg ? in_size : in_size_reg; + assign d0_in_addr = in_addr; + assign d0_in_bytecount = in_bytecount; + assign d0_in_burstwrap = new_burst_reg ? in_burstwrap : in_burstwrap_reg; + assign d0_in_bursttype = new_burst_reg ? in_bursttype : in_bursttype_reg; + assign d0_in_narrow = new_burst_reg ? in_narrow : in_narrow_reg; + assign d0_in_passthru = load_next_pkt ? in_passthru : in_passthru_reg; + assign d0_in_write = in_write; + assign d0_in_compressed_read = in_compressed_read; + assign d0_in_uncompressed_read = in_uncompressed_read; + assign d0_in_valid = in_valid; + assign d0_in_sop = in_sop; + assign d1_in_eop = in_eop_reg; + assign d1_in_data = in_data_reg; + assign d1_in_channel = in_channel_reg; + assign d1_in_size = in_size_reg; + assign d1_in_bursttype = in_bursttype_reg; + assign d1_in_byteen = in_byteen_reg; + assign d1_in_uncompressed_read = in_uncompressed_read_reg; + assign d1_in_narrow = in_narrow_reg; + + end : NON_PIPELINED_INPUTS + +else + begin : PIPELINED_INPUTS + + reg [PKT_BURST_SIZE_W - 1 : 0] d0_int_size; + reg [PKT_BURSTWRAP_W - 1 : 0] d0_int_burstwrap; + reg [PKT_BURST_TYPE_W - 1 : 0] d0_int_bursttype; + reg d0_int_narrow; + reg d0_int_passthru; + + always_ff @(posedge clk or posedge reset) begin + if (reset) begin + in_channel_reg <= '0; + in_data_reg <= '0; + in_burstwrap_reg <= '0; + in_bursttype_reg <= '0; + in_byteen_reg <= '0; + in_narrow_reg <= '0; + in_size_reg <= '0; + in_addr_reg <= '0; + in_passthru_reg <= '0; + in_eop_reg <= '0; + in_bytecount_reg <= '0; + in_bytecount_reg_zero <= '0; + in_uncompressed_read_reg <= '0; + in_write_reg <= '0; + in_compressed_read_reg <= '0; + in_uncompressed_read_reg <= '0; + in_sop_reg <= '0; + in_valid_reg <= '0; + d1_in_eop <= '0; + d1_in_data <= '0; + d1_in_channel <= '0; + d1_in_size <= '0; + d1_in_bursttype <= '0; + d1_in_byteen <= '0; + d1_in_uncompressed_read <= '0; + d1_in_narrow <= '0; + d0_int_size <= '0; + d0_int_burstwrap <= '0; + d0_int_bursttype <= '0; + d0_int_narrow <= '0; + d0_int_passthru <= '0; + end + else begin + if (sink0_ready & in_valid) begin + in_channel_reg <= in_channel; + in_data_reg <= in_data; + in_burstwrap_reg <= in_burstwrap; + in_bursttype_reg <= in_bursttype; + in_byteen_reg <= in_byteen; + in_narrow_reg <= in_narrow; + in_size_reg <= in_size; + in_addr_reg <= in_addr; + in_bytecount_reg <= in_bytecount; + in_bytecount_reg_zero <= ~|in_bytecount; + in_uncompressed_read_reg <= in_uncompressed_read; + in_eop_reg <= in_eop; + in_write_reg <= in_write; + in_compressed_read_reg <= in_compressed_read; + in_uncompressed_read_reg <= in_uncompressed_read; + in_sop_reg <= in_sop; + end + // Passthru is evaluated every transaction + if (sink0_ready & in_sop & in_valid) begin + in_passthru_reg <= in_passthru; + end + + if (sink0_ready) in_valid_reg <= in_valid; + + if ( ( (state != ST_COMP_TRANS) & (~source0_valid | source0_ready)) | + ( (state == ST_COMP_TRANS) & (~source0_valid | source0_ready & source0_endofpacket) ) ) begin + d1_in_eop <= in_eop_reg; + d1_in_data <= in_data_reg; + d1_in_channel <= in_channel_reg; + d1_in_size <= in_size_reg; + d1_in_bursttype <= in_bursttype_reg; + d1_in_byteen <= in_byteen_reg; + d1_in_uncompressed_read <= in_uncompressed_read_reg; + d1_in_narrow <= in_narrow_reg; + end + + if ( ( (state != ST_COMP_TRANS) & (~source0_valid | source0_ready)) | + ( (state == ST_COMP_TRANS) & (~source0_valid | source0_ready & source0_endofpacket) ) ) begin + d0_int_size <= in_size_reg; + d0_int_burstwrap <= in_burstwrap_reg; + d0_int_bursttype <= in_bursttype_reg; + d0_int_narrow <= in_narrow_reg; + d0_int_passthru <= in_passthru_reg; + end + + + end + end + + assign d0_in_size = new_burst_reg ? in_size_reg : d0_int_size; + assign d0_in_addr = in_addr_reg; + assign d0_in_bytecount = in_bytecount_reg; + assign d0_in_burstwrap = new_burst_reg ? in_burstwrap_reg : d0_int_burstwrap; + assign d0_in_bursttype = new_burst_reg ? in_bursttype_reg : d0_int_bursttype; + assign d0_in_narrow = new_burst_reg ? in_narrow_reg : d0_int_narrow; + assign d0_in_passthru = new_burst_reg ? in_passthru_reg : d0_int_passthru; + assign d0_in_write = in_write_reg; + assign d0_in_compressed_read = in_compressed_read_reg; + assign d0_in_uncompressed_read = in_uncompressed_read_reg; + assign d0_in_valid = in_valid_reg; + assign d0_in_sop = in_sop_reg; + + end : PIPELINED_INPUTS +endgenerate + + // ------------------------------- + // Length Calculation Input Staging. + // ------------------------------- + + reg [PKT_ADDR_W -1 : 0] int_nxt_addr_with_offset; + + reg [PKT_BURSTWRAP_W - 1 : 0] no_wrap_dist; + + // These 2 values are part of break up of calculation from pre-flop to post-flop for timing optimization + assign int_nxt_addr_with_offset = int_nxt_addr_reg | extended_burstwrap & (int_nxt_addr_reg_dly + int_byte_cnt_narrow_reg); + + // Unaligned address support + reg [PKT_ADDR_W + LOG2_NUM_SYMBOLS - 1 : 0 ] d0_in_addr_aligned_full; + altera_merlin_address_alignment + # ( + .ADDR_W (PKT_ADDR_W), + .BURSTWRAP_W (1), // Not used in burst adapter calculation usage of this module + .TYPE_W (0), // Not used in burst adapter calculation usage of this module + .SIZE_W (PKT_BURST_SIZE_W), + .INCREMENT_ADDRESS (0), + .NUMSYMBOLS (NUM_SYMBOLS) + ) align_address_to_size + ( + .clk(1'b0), .reset(1'b0), .in_valid(1'b0), .in_sop(1'b0), .in_eop(1'b0), .out_ready(), // Dummy. Not used in INCREMENT_ADDRESS=0 settings + // This block is purely combi + .in_data ( { d0_in_addr , d0_in_size } ), + .out_data ( d0_in_addr_aligned_full ) + ); + + // On start of every new burst, take in new input values for calculations + assign d0_int_bytes_remaining = new_burst_reg ? d0_in_bytecount: int_bytes_remaining_reg - out_byte_cnt_reg; + assign d0_int_nxt_addr = new_burst_reg ? d0_in_addr_aligned_full[PKT_ADDR_W-1:0] : int_nxt_addr_with_offset; + assign d0_int_dist = NO_WRAP_SUPPORT ? no_wrap_dist : incremented_wrap_mask - ( d0_int_nxt_addr[PKT_BURSTWRAP_W-1:0] & wrap_mask); + always_comb begin + + if (OUT_BURSTWRAP_W == 0) begin // Special case: 1-symbol, fixed-burst slave. + no_wrap_dist = ~nxt_out_burstwrap[PKT_BURSTWRAP_W] ? num_symbols_sig : '1; + end + else if (OUT_BURSTWRAP_W == 1) begin + no_wrap_dist = ~nxt_out_burstwrap[PKT_BURSTWRAP_W - 1] ? num_symbols_sig : '1; + end + else if (LOG2_NUM_SYMBOLS <= OUT_BURSTWRAP_W) begin + + no_wrap_dist = (|nxt_out_burstwrap[PKT_BURSTWRAP_W - 1: 0] & ~nxt_out_burstwrap[PKT_BURSTWRAP_W - 1]) ? + num_symbols_sig : '1; + end + else begin + no_wrap_dist = num_symbols_sig; + end + + end + + // ------------------------------- + // Output Load Control Signals + // ------------------------------- + + // Used by output flops to load in next state when: + // 1. source has taken command (or ready to accept) + // 2. if no command is pending (IDLE) + wire load_next_out_cmd = source0_ready | ~source0_valid; + //wire load_next_out_pkt = (source0_ready & source0_endofpacket) | ~source0_valid; + + // --------------------------------------------------- + // INTERMEDIATE CONTROL FLAGS / HOLDING REGISTERS + // --------------------------------------------------- + + always_comb begin + + // Default case : Unless it's a narrow transfer, take the max, else keep it at num_symbols_sig + the_min_byte_cnt_or_num_sym = d0_in_narrow ? num_symbols_sig : out_max_byte_cnt_sig; + + + if (OUT_BURSTWRAP_W == 0) begin // Special case: 1-symbol, fixed-burst slave. + disable_wrap_dist_calc = ~d0_in_burstwrap[OUT_BURSTWRAP_W]; + end + else begin + if (OUT_NARROW_SIZE || OUT_FIXED || OUT_COMPLETE_WRAP) begin //AXI Slave + // When burst type is "RESERVED" it means that a fix burst wide-to-narrow has occured + // kevtan : added highest bit of wrap mask + disable_wrap_dist_calc = (d0_in_passthru && d0_in_bursttype != RESERVED) | nxt_out_burstwrap[PKT_BURSTWRAP_W - 1]; + the_min_byte_cnt_or_num_sym = out_max_byte_cnt_sig; + end + else if (OUT_BURSTWRAP_W == PKT_BURSTWRAP_W) begin // Sequential slave + disable_wrap_dist_calc = d0_in_burstwrap[PKT_BURSTWRAP_W - 1]; + end + else begin + // Dont really have a full story here to tell "Default?" + // This assumes that OUT_BURSTWRAP_W < PKT_BURSTWRAP_W. Then looks at the slave's wrap boundary. + // If d0_in_burstwrap[OUT_BURSTWRAP_W] is set, this is sequential? + // If d0_in_burstwrap[OUT_BURSTWRAP_W - 1] is set, then it needs to be sequential to the slave? + disable_wrap_dist_calc = ~d0_in_burstwrap[OUT_BURSTWRAP_W] & d0_in_burstwrap[OUT_BURSTWRAP_W - 1]; + end + end + end + + + // ---------------------------------------------------- + // FSM : Finite State Machine + // For handling the control signals for burst adapter. + // Note: Arcs in the SM will only take effect is there's no backpressurring from the source + // --------------------------------------------------- + + always_comb begin : state_transition + // default + next_state = ST_IDLE; + + case (state) + ST_IDLE : begin + next_state = ST_IDLE; + + if (d0_in_valid) begin + if (d0_in_write | d0_in_uncompressed_read) next_state = ST_UNCOMP_TRANS; + if (d0_in_compressed_read) next_state = ST_COMP_TRANS; + end + end + + ST_UNCOMP_TRANS : begin + next_state = ST_UNCOMP_TRANS; + + if (source0_endofpacket) begin + if (~d0_in_valid) next_state = ST_IDLE; + else begin + if (d0_in_write | d0_in_uncompressed_read) next_state = ST_UNCOMP_TRANS; + if (d0_in_compressed_read) next_state = ST_COMP_TRANS; + end + end + else begin + if (|nxt_uncomp_subburst_byte_cnt) next_state = ST_UNCOMP_WR_SUBBURST; + end + end + + ST_UNCOMP_WR_SUBBURST : begin + next_state = ST_UNCOMP_WR_SUBBURST; + + if (source0_endofpacket) begin + if (~d0_in_valid) next_state = ST_IDLE; + else begin + if (d0_in_write | d0_in_uncompressed_read) next_state = ST_UNCOMP_TRANS; + if (d0_in_compressed_read) next_state = ST_COMP_TRANS; + end + end + else begin + if (~|nxt_uncomp_subburst_byte_cnt) next_state = ST_UNCOMP_TRANS; + end + end + + ST_COMP_TRANS : begin + next_state = ST_COMP_TRANS; + + if (source0_endofpacket) begin + if (~d0_in_valid) begin + next_state = ST_IDLE; + end + else begin + if (d0_in_write | d0_in_uncompressed_read) next_state = ST_UNCOMP_TRANS; + if (d0_in_compressed_read) next_state = ST_COMP_TRANS; + end + end + end + + endcase + end + + // ---------------------------------------------------- + // FSM : Controlled output control signals + // ---------------------------------------------------- + + // in_ready is asserted when: + // 1. IDLE + // 2. COMPRESSED TRANSACTION : When not being back pressured by source and sending out last cmd. + // 3. UNCOMPRESSED TRANSACTION : When not being back pressured by source + + assign nxt_in_ready = (state == ST_COMP_TRANS) ? source0_endofpacket & source0_ready | ~source0_valid : + (state == ST_UNCOMP_TRANS | state == ST_UNCOMP_WR_SUBBURST) ? source0_ready | ~source0_valid : + 1'b1; + + // out_valid is asserted: + // 1. Following sink_valid unless in ST_COMP_TRANS, where it's always one, unless it's endofpacket. + assign nxt_out_valid = ((state == ST_COMP_TRANS) & ~source0_endofpacket ) ? 1'b1 : d0_in_valid; + + // out_startofpacket + // 1. Following sink_startofpacket unless in ST_COMP_TRANS, where it's always one for first cycle before accepted. + assign nxt_out_sop = ( (state == ST_COMP_TRANS) & source0_ready & !new_burst_reg) ? 1'b0 : d0_in_sop; + + // out_endofpacket ?? + // Follows sink_endofpacket unless in ST_COMP_TRANS, where it is a compare of whether this is the last cycle + assign nxt_out_eop = (state == ST_COMP_TRANS) ? ( source0_ready? new_burst_reg : in_bytecount_reg_zero ) : d1_in_eop; + + + + always_ff @(posedge clk or posedge reset) begin + if (reset) begin + state <= ST_IDLE; + out_valid_reg <= '0; + out_sop_reg <= '0; + end + else begin + if (~source0_valid | source0_ready) begin + state <= next_state; + out_valid_reg <= nxt_out_valid; + out_sop_reg <= nxt_out_sop; + end + end + end + + assign sink0_ready = nxt_in_ready; // COMBI OUT?? + + // --------------------------------------------------- + // Converter + // --------------------------------------------------- + + // --------------------------------------------------- + // Wrap boundary distance calculation + // --------------------------------------------------- + + // Wrap mask takes in nxt_out_burstwrap to handle cases where there's a wrapping Avalon slave with boundary < PKT_BURSTWRAP_W + assign wrap_mask = disable_wrap_dist_calc ? '1 : nxt_out_burstwrap; + + // Must be valid in the cycle prior to each begin-subburst, for calculating begin_subburst_byte_cnt. + altera_merlin_burst_adapter_burstwrap_increment #(.WIDTH (PKT_BURSTWRAP_W)) the_burstwrap_increment + ( + .mask (wrap_mask), + .inc (incremented_wrap_mask) + ); + + // --------------------------------------------------- + // Length Converter + // --------------------------------------------------- + + always_comb + begin : EXT_BURSTWRAP + extended_burstwrap = { {(PKT_ADDR_W - PKT_BURSTWRAP_W) {d0_in_burstwrap[PKT_BURSTWRAP_W -1]}}, d0_in_burstwrap }; + end + + altera_merlin_burst_adapter_min #( + .PKT_BYTE_CNT_W (PKT_BYTE_CNT_W), + .PKT_BURSTWRAP_W (PKT_BURSTWRAP_W), + .PIPELINE_POSITION (2) // NO PIPELINE (ALL COMBI) + ) + the_min ( + .clk (clk), + .reset (reset), + .a (d0_int_bytes_remaining), + .b (the_min_byte_cnt_or_num_sym), + .c (d0_int_dist), + .c_enable (~wrap_mask[PKT_BURSTWRAP_W - 1]), + .d (num_symbols_sig), + .result (nxt_byte_cnt) + ); + +// synthesis translate_off + +// TEMP ASSERTION FOR OWN CHECKING +//always @(posedge clk or posedge reset) begin +// if (~reset && in_bursttype==WRAP && sink0_valid && sink0_ready && NO_WRAP_SUPPORT==1) begin +// $display ("SELF_CHK: WRAP transaction seen in no wrap support settings"); +// end +//end + +// synthesis translate_on + + // --------------------------------------- + // Next Address Calculation + // --------------------------------------- + always_comb + begin : NXT_ADDR_CALC + + nxt_addr = d0_int_nxt_addr & ~extended_burstwrap; + // this part of calculation is moved to post flop (nxt_addr2 = (extended_burstwrap & (d0_int_nxt_addr + nxt_byte_cnt_narrow)); + + end + + // --------------------------------------- + // Length Converter Registers + // --------------------------------------- + always_ff @(posedge clk or posedge reset) begin + if (reset) begin + out_byte_cnt_reg <= '0; + int_byte_cnt_narrow_reg <= '0; + int_bytes_remaining_reg <= '0; + int_nxt_addr_reg <= '0; + int_nxt_addr_reg_dly <= '0; + new_burst_reg <= '0; + out_addr_reg <= '0; + end + else begin + if (load_next_out_cmd) begin + out_byte_cnt_reg <= nxt_byte_cnt; + int_byte_cnt_narrow_reg <= (nxt_byte_cnt >> log2_numsymbols[PKT_BYTE_CNT_W -1 :0]) << d0_in_size; + int_bytes_remaining_reg <= d0_int_bytes_remaining; + int_nxt_addr_reg <= nxt_addr; + int_nxt_addr_reg_dly <= d0_int_nxt_addr; + // New burst is when next byte count is equal to bytes remaining. (Used only in COMPRESSED transaction) + new_burst_reg <= (nxt_byte_cnt == d0_int_bytes_remaining) | next_state != ST_COMP_TRANS; + // Initial address and non-COMPRESSED transaction address does not use offset. + out_addr_reg <= new_burst_reg ? d0_in_addr : int_nxt_addr_with_offset; + end + end + end + + // ---------------------------------------------------- + // Uncompressed transaction calculations + // Address : No changes, just pass through (handled in the flop in for out_addr_reg) // Make it to the output? + // Byte count : For reads, this will be just the num_symbols_sig + // : For writes, it will need to decrement for subsequent reads unless it's 0, + // in which the next calculated byte count is used. + // ---------------------------------------------------- + + always_comb + begin : UNCOMPRESSED_SUBBURST_BYTE_CNT_CALC + + // During start of uncompressed transaction, load the nxt_uncomp_subburst_byte_cnt with the "current output byte count - num_symbols_sig" + // After that, on subsequent cycles, load in the 'saved' byte count value - num_symbols_sig + // This signal is used also for transition of the state machine to ensure we will reload the byte count with the results from + // length converter if we decremented to zero. + // In essence, the wrap boundary is still observed and maintained. [Hence the use of the current output byte count when in ST_UNCOMP_TRANS. + + nxt_uncomp_subburst_byte_cnt = + (state == ST_UNCOMP_TRANS) ? + ( (source0_valid & source0_ready) ? out_byte_cnt_reg - num_symbols_sig : out_uncomp_byte_cnt_reg ) : + out_uncomp_byte_cnt_reg - ( (source0_valid & source0_ready)? num_symbols_sig : '0) ; + + end + + always_ff @(posedge clk or posedge reset) begin + if (reset) begin + out_uncomp_byte_cnt_reg <= '0; + end + else begin + if (load_next_out_cmd) begin + out_uncomp_byte_cnt_reg <= nxt_uncomp_subburst_byte_cnt; + end + end + end + + // --------------------------------------------------- + // Burst Type Generation + // AXI/Avalon masters - Avalon slave - This is pass through from packet to slave + // AXI/Avalon masters - AXI slave - It will always be converted to INCR type + // --------------------------------------------------- + reg [PKT_BURST_TYPE_W - 1 : 0 ] out_bursttype; + + // bursttype will switch to INCR if repeated wraps detected (NOTE: ??) + assign out_bursttype = (d1_in_bursttype == RESERVED) ? INCR : d1_in_bursttype; + + // --------------------------------------------------- + // Burst Wrap Generation + // Burst wrap is taken to be just the MIN between OUT_MAX_BURSTWRAP and the input burstwrap + // This is to handle cases where the slave's wrapping boundary is different from the master's + // Essentially, the master transaction characteristics are honored, but the burst wrap is modified. + // (Arguably, this can be handled by the slave) + // NOTE: Internally, this is used to generate the wrap_mask, so to calculate the correct wrapping distance. + // --------------------------------------------------- + + assign nxt_out_burstwrap = altera_merlin_burst_adapter_burstwrap_min(OUT_MAX_BURSTWRAP, d0_in_burstwrap); + + always_ff @(posedge clk or posedge reset) begin + if (reset) out_burstwrap_reg <= '0; + else + if ( ( (state != ST_COMP_TRANS) & (~source0_valid | source0_ready)) | + ( (state == ST_COMP_TRANS) & (~source0_valid | source0_ready & source0_endofpacket) ) ) begin + out_burstwrap_reg <= nxt_out_burstwrap; + end + end + + // --------------------------------------------------- + // Byte enable generation + // Follow unless : in compressed transaction. + // --------------------------------------------------- + reg [LOG2_NUM_SYMBOLS - 1 : 0 ] out_addr_masked; + wire [127:0 ] d1_initial_byteen = set_byteenable_based_on_size(d1_in_size); // To fix quartus integration error. + // Unused bits are expected to be synthesized away + reg [PKT_BYTEEN_W - 1 : 0 ] out_byteen; + + // Unaligned address changes. + // NOTE : Assumption : Byte enable is calculated for all cycles coming out from BA, and needs to be based on aligned address. + // Hence, it cannot take directly output address of BA (which sends out unaligned address for 1st cycle) + always_ff @(posedge clk or posedge reset) begin + if (reset) out_addr_masked <= '0; + else + if (load_next_out_cmd) out_addr_masked <= new_burst_reg ? d0_in_addr_aligned_full[LOG2_NUM_SYMBOLS-1:0] : int_nxt_addr_with_offset[LOG2_NUM_SYMBOLS-1:0]; + end + + always_comb begin + if (BYTEENABLE_SYNTHESIS == 1 && d1_in_narrow == 1 && (state == ST_COMP_TRANS) ) + out_byteen = d1_initial_byteen [NUM_SYMBOLS-1:0] << out_addr_masked; + else + out_byteen = d1_in_byteen; + end + + + // --------------------------------------------------- + // Mapping of output signals. This will help to see what is comb out or flop out + // --------------------------------------------------- + + always_comb begin : source0_out_assignments + + source0_valid = out_valid_reg; + source0_startofpacket = out_sop_reg; + source0_endofpacket = nxt_out_eop; // COMBI + + // Generic assign to all data + source0_data = d1_in_data; + source0_channel = d1_in_channel; + + // Override fields the component is aware of. + source0_data[PKT_BYTE_CNT_H : PKT_BYTE_CNT_L] = d1_in_uncompressed_read ? num_symbols_sig : + (state == ST_UNCOMP_WR_SUBBURST) ? out_uncomp_byte_cnt_reg : + out_byte_cnt_reg; // COMBI + source0_data[PKT_ADDR_H : PKT_ADDR_L] = out_addr_reg; + source0_data[PKT_BURSTWRAP_H : PKT_BURSTWRAP_L] = out_burstwrap_reg; + source0_data[PKT_BURST_TYPE_H : PKT_BURST_TYPE_L] = out_bursttype; // COMBI + source0_data[PKT_BYTEEN_H: PKT_BYTEEN_L] = out_byteen; // COMBI + end + + +endmodule + + diff --git a/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_burst_uncompressor.sv b/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_burst_uncompressor.sv new file mode 100644 index 00000000..77249653 --- /dev/null +++ b/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_burst_uncompressor.sv @@ -0,0 +1,286 @@ +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// (C) 2001-2012 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/12.1sp1/ip/merlin/altera_merlin_slave_agent/altera_merlin_burst_uncompressor.sv#1 $ +// $Revision: #1 $ +// $Date: 2012/10/10 $ +// $Author: swbranch $ + +// ------------------------------------------ +// Merlin Burst Uncompressor +// +// Compressed read bursts -> uncompressed +// ------------------------------------------ + +`timescale 1 ns / 1 ns + +module altera_merlin_burst_uncompressor +#( + parameter ADDR_W = 16, + parameter BURSTWRAP_W = 3, + parameter BYTE_CNT_W = 4, + parameter PKT_SYMBOLS = 4, + parameter BURST_SIZE_W = 3 +) +( + input clk, + input reset, + + // sink ST signals + input sink_startofpacket, + input sink_endofpacket, + input sink_valid, + output sink_ready, + + // sink ST "data" + input [ADDR_W - 1: 0] sink_addr, + input [BURSTWRAP_W - 1 : 0] sink_burstwrap, + input [BYTE_CNT_W - 1 : 0] sink_byte_cnt, + input sink_is_compressed, + input [BURST_SIZE_W-1 : 0] sink_burstsize, + + // source ST signals + output source_startofpacket, + output source_endofpacket, + output source_valid, + input source_ready, + + // source ST "data" + output [ADDR_W - 1: 0] source_addr, + output [BURSTWRAP_W - 1 : 0] source_burstwrap, + output [BYTE_CNT_W - 1 : 0] source_byte_cnt, + + // Note: in the slave agent, the output should always be uncompressed. In + // other applications, it may be required to leave-compressed or not. How to + // control? Seems like a simple mux - pass-through if no uncompression is + // required. + output source_is_compressed, + output [BURST_SIZE_W-1 : 0] source_burstsize +); + +//---------------------------------------------------- +// AXSIZE decoding +// +// Turns the axsize value into the actual number of bytes +// being transferred. +// --------------------------------------------------- +function reg[63:0] bytes_in_transfer; + input [2:0] axsize; + case (axsize) + 3'b000: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000001; + 3'b001: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000010; + 3'b010: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000100; + 3'b011: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000001000; + 3'b100: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000010000; + 3'b101: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000100000; + 3'b110: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000001000000; + 3'b111: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000010000000; + default:bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000001; + endcase + +endfunction + + // num_symbols is PKT_SYMBOLS, appropriately sized. + wire [31:0] int_num_symbols = PKT_SYMBOLS; + wire [BYTE_CNT_W-1:0] num_symbols = int_num_symbols[BYTE_CNT_W-1:0]; + + // def: Burst Compression. In a merlin network, a compressed burst is one + // which is transmitted in a single beat. Example: read burst. In + // constrast, an uncompressed burst (example: write burst) is transmitted in + // one beat per writedata item. + // + // For compressed bursts which require response packets, burst + // uncompression is required. Concrete example: a read burst of size 8 + // occupies one response-fifo position. When that fifo position reaches the + // front of the FIFO, the slave starts providing the required 8 readdatavalid + // pulses. The 8 return response beats must be provided in a single packet, + // with incrementing address and decrementing byte_cnt fields. Upon receipt + // of the final readdata item of the burst, the response FIFO item is + // retired. + // Burst uncompression logic provides: + // a) 2-state FSM (idle, busy) + // reset to idle state + // transition to busy state for 2nd and subsequent rdv pulses + // - a single-cycle burst (aka non-burst read) causes no transition to + // busy state. + // b) response startofpacket/endofpacket logic. The response FIFO item + // will have sop asserted, and may have eop asserted. (In the case of + // multiple read bursts transmit in the command fabric in a single packet, + // the eop assertion will come in a later FIFO item.) To support packet + // conservation, and emit a well-formed packet on the response fabric, + // i) response fabric startofpacket is asserted only for the first resp. + // beat; + // ii) response fabric endofpacket is asserted only for the last resp. + // beat. + // c) response address field. The response address field contains an + // incrementing sequence, such that each readdata item is associated with + // its slave-map location. N.b. a) computing the address correctly requires + // knowledge of burstwrap behavior b) there may be no clients of the address + // field, which makes this field a good target for optimization. See + // burst_uncompress_address_counter below. + // d) response byte_cnt field. The response byte_cnt field contains a + // decrementing sequence, such that each beat of the response contains the + // count of bytes to follow. In the case of sub-bursts in a single packet, + // the byte_cnt field may decrement down to num_symbols, then back up to + // some value, multiple times in the packet. + + reg burst_uncompress_busy; + reg [BYTE_CNT_W-1:0] burst_uncompress_byte_counter; + wire first_packet_beat; + wire last_packet_beat; + + assign first_packet_beat = sink_valid & ~burst_uncompress_busy; + + // First cycle: burst_uncompress_byte_counter isn't ready yet, mux the input to + // the output. + assign source_byte_cnt = + first_packet_beat ? sink_byte_cnt : burst_uncompress_byte_counter; + assign source_valid = sink_valid; + + // Last packet beat is set throughout receipt of an uncompressed read burst + // from the response FIFO - this forces all the burst uncompression machinery + // idle. + assign last_packet_beat = ~sink_is_compressed | + ( + burst_uncompress_busy ? + (sink_valid & (burst_uncompress_byte_counter == num_symbols)) : + sink_valid & (sink_byte_cnt == num_symbols) + ); + + always @(posedge clk or posedge reset) begin + if (reset) begin + burst_uncompress_busy <= '0; + burst_uncompress_byte_counter <= '0; + end + else begin + if (source_valid & source_ready & sink_valid) begin + // No matter what the current state, last_packet_beat leads to + // idle. + if (last_packet_beat) begin + burst_uncompress_busy <= '0; + burst_uncompress_byte_counter <= '0; + end + else begin + if (burst_uncompress_busy) begin + burst_uncompress_byte_counter <= burst_uncompress_byte_counter ? + (burst_uncompress_byte_counter - num_symbols) : + (sink_byte_cnt - num_symbols); + end + else begin // not busy, at least one more beat to go + burst_uncompress_byte_counter <= sink_byte_cnt - num_symbols; + // To do: should busy go true for numsymbols-size compressed + // bursts? + burst_uncompress_busy <= '1; + end + end + end + end + end + + wire [ADDR_W - 1 : 0 ] addr_width_burstwrap; + reg [ADDR_W - 1 : 0 ] burst_uncompress_address_base; + reg [ADDR_W - 1 : 0] burst_uncompress_address_offset; + + wire [63:0] decoded_burstsize_wire; + wire [ADDR_W-1:0] decoded_burstsize; + + // The input burstwrap value can be used as a mask against address values, + // but with one caveat: the address width may be (probably is) wider than + // the burstwrap width. The spec says: extend the msb of the burstwrap + // value out over the entire address width (but only if the address width + // actually is wider than the burstwrap width; otherwise it's a 0-width or + // negative range and concatenation multiplier). + assign addr_width_burstwrap[BURSTWRAP_W - 1 : 0] = sink_burstwrap; + generate + if (ADDR_W > BURSTWRAP_W) begin : addr_sign_extend + // Sign-extend, just wires: + assign addr_width_burstwrap[ADDR_W - 1 : BURSTWRAP_W] = + {(ADDR_W - BURSTWRAP_W) {sink_burstwrap[BURSTWRAP_W - 1]}}; + end + endgenerate + + always @(posedge clk or posedge reset) begin + if (reset) begin + burst_uncompress_address_base <= '0; + end + else if (first_packet_beat & source_ready) begin + burst_uncompress_address_base <= sink_addr & ~addr_width_burstwrap; + end + end + + assign decoded_burstsize_wire = bytes_in_transfer(sink_burstsize); //expand it to 64 bits + assign decoded_burstsize = decoded_burstsize_wire[ADDR_W-1:0]; //then take the width that is needed + + wire [ADDR_W - 1 : 0] p1_burst_uncompress_address_offset = + ( + (first_packet_beat ? + sink_addr : + burst_uncompress_address_offset) + decoded_burstsize + ) & + addr_width_burstwrap; + + always @(posedge clk or posedge reset) begin + if (reset) begin + burst_uncompress_address_offset <= '0; + end + else begin + if (source_ready & source_valid) begin + burst_uncompress_address_offset <= p1_burst_uncompress_address_offset; + // if (first_packet_beat) begin + // burst_uncompress_address_offset <= + // (sink_addr + num_symbols) & addr_width_burstwrap; + // end + // else begin + // burst_uncompress_address_offset <= + // (burst_uncompress_address_offset + num_symbols) & addr_width_burstwrap; + // end + end + end + end + + // On the first packet beat, send the input address out unchanged, + // while values are computed/registered for 2nd and subsequent beats. + assign source_addr = first_packet_beat ? sink_addr : + burst_uncompress_address_base | burst_uncompress_address_offset; + assign source_burstwrap = sink_burstwrap; + assign source_burstsize = sink_burstsize; + + //------------------------------------------------------------------- + // A single (compressed) read burst will have sop/eop in the same beat. + // A sequence of read sub-bursts emitted by a burst adapter in response to a + // single read burst will have sop on the first sub-burst, eop on the last. + // Assert eop only upon (sink_endofpacket & last_packet_beat) to preserve + // packet conservation. + assign source_startofpacket = sink_startofpacket & ~burst_uncompress_busy; + assign source_endofpacket = sink_endofpacket & last_packet_beat; + assign sink_ready = source_valid & source_ready & last_packet_beat; + + // This is correct for the slave agent usage, but won't always be true in the + // width adapter. To do: add an "please uncompress" input, and use it to + // pass-through or modify, and set source_is_compressed accordingly. + assign source_is_compressed = 1'b0; +endmodule + diff --git a/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_master_agent.sv b/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_master_agent.sv new file mode 100644 index 00000000..613cf91a --- /dev/null +++ b/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_master_agent.sv @@ -0,0 +1,279 @@ +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/12.1sp1/ip/merlin/altera_merlin_master_agent/altera_merlin_master_agent.sv#1 $ +// $Revision: #1 $ +// $Date: 2012/10/10 $ +// $Author: swbranch $ + +// -------------------------------------- +// Merlin Master Agent +// +// Converts Avalon-MM transactions into +// Merlin network packets. +// -------------------------------------- + +`timescale 1 ns / 1 ns + +module altera_merlin_master_agent +#( + // ------------------- + // Packet Format Parameters + // ------------------- + parameter PKT_QOS_H = 109, + PKT_QOS_L = 106, + PKT_DATA_SIDEBAND_H = 105, + PKT_DATA_SIDEBAND_L = 98, + PKT_ADDR_SIDEBAND_H = 97, + PKT_ADDR_SIDEBAND_L = 93, + PKT_CACHE_H = 92, + PKT_CACHE_L = 89, + PKT_THREAD_ID_H = 88, + PKT_THREAD_ID_L = 87, + PKT_BEGIN_BURST = 81, + PKT_PROTECTION_H = 80, + PKT_PROTECTION_L = 80, + PKT_BURSTWRAP_H = 79, + PKT_BURSTWRAP_L = 77, + PKT_BYTE_CNT_H = 76, + PKT_BYTE_CNT_L = 74, + PKT_ADDR_H = 73, + PKT_ADDR_L = 42, + PKT_BURST_SIZE_H = 86, + PKT_BURST_SIZE_L = 84, + PKT_BURST_TYPE_H = 94, + PKT_BURST_TYPE_L = 93, + PKT_TRANS_EXCLUSIVE = 83, + PKT_TRANS_LOCK = 82, + PKT_TRANS_COMPRESSED_READ = 41, + PKT_TRANS_POSTED = 40, + PKT_TRANS_WRITE = 39, + PKT_TRANS_READ = 38, + PKT_DATA_H = 37, + PKT_DATA_L = 6, + PKT_BYTEEN_H = 5, + PKT_BYTEEN_L = 2, + PKT_SRC_ID_H = 1, + PKT_SRC_ID_L = 1, + PKT_DEST_ID_H = 0, + PKT_DEST_ID_L = 0, + ST_DATA_W = 110, + ST_CHANNEL_W = 1, + + // ------------------- + // Agent Parameters + // ------------------- + AV_BURSTCOUNT_W = 3, + ID = 1, + SUPPRESS_0_BYTEEN_RSP = 1, + BURSTWRAP_VALUE = 4, + CACHE_VALUE = 4'b0000, + + // ------------------- + // Derived Parameters + // ------------------- + PKT_BURSTWRAP_W = PKT_BURSTWRAP_H - PKT_BURSTWRAP_L + 1, + PKT_BYTE_CNT_W = PKT_BYTE_CNT_H - PKT_BYTE_CNT_L + 1, + PKT_ADDR_W = PKT_ADDR_H - PKT_ADDR_L + 1, + PKT_DATA_W = PKT_DATA_H - PKT_DATA_L + 1, + PKT_BYTEEN_W = PKT_BYTEEN_H - PKT_BYTEEN_L + 1, + PKT_SRC_ID_W = PKT_SRC_ID_H - PKT_SRC_ID_L + 1, + PKT_DEST_ID_W = PKT_DEST_ID_H - PKT_DEST_ID_L + 1 +) +( + // ------------------- + // Clock & Reset + // ------------------- + input clk, + input reset, + + // ------------------- + // Avalon-MM Anti-Master + // ------------------- + input [PKT_ADDR_W-1 : 0] av_address, + input av_write, + input av_read, + input [PKT_DATA_W-1 : 0] av_writedata, + output reg [PKT_DATA_W-1 : 0] av_readdata, + output reg av_waitrequest, + output reg av_readdatavalid, + input [PKT_BYTEEN_W-1 : 0] av_byteenable, + input [AV_BURSTCOUNT_W-1 : 0] av_burstcount, + input av_debugaccess, + input av_lock, + + // ------------------- + // Command Source + // ------------------- + output reg cp_valid, + output reg [ST_DATA_W-1 : 0] cp_data, + output wire cp_startofpacket, + output wire cp_endofpacket, + input cp_ready, + + // ------------------- + // Response Sink + // ------------------- + input rp_valid, + input [ST_DATA_W-1 : 0] rp_data, + input [ST_CHANNEL_W-1 : 0] rp_channel, + input rp_startofpacket, + input rp_endofpacket, + output reg rp_ready +); + // ------------------------------------------------------------ + // Utility Functions + // ------------------------------------------------------------ + function integer clogb2; + input [31:0] value; + begin + for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1) + value = value >> 1; + clogb2 = clogb2 - 1; + end + endfunction // clogb2 + + localparam MAX_BURST = 1 << (AV_BURSTCOUNT_W - 1); + localparam NUMSYMBOLS = PKT_BYTEEN_W; + localparam BURSTING = (MAX_BURST > NUMSYMBOLS); + localparam BITS_TO_ZERO = clogb2(NUMSYMBOLS); + localparam BURST_SIZE = clogb2(NUMSYMBOLS); + + typedef enum bit [1:0] + { + FIXED = 2'b00, + INCR = 2'b01, + WRAP = 2'b10, + OTHER_WRAP = 2'b11 + } MerlinBurstType; + + // -------------------------------------- + // Potential optimization: compare in words to save bits? + // -------------------------------------- + wire is_burst; + assign is_burst = (BURSTING) & (av_burstcount > NUMSYMBOLS); + + wire [31:0] burstwrap_value_int = BURSTWRAP_VALUE; + wire [31:0] id_int = ID; + wire [2:0] burstsize_sig = BURST_SIZE[2:0]; + wire [1:0] bursttype_value = burstwrap_value_int[PKT_BURSTWRAP_W-1] ? INCR : WRAP; + + // -------------------------------------- + // Address alignment + // + // The packet format requires that addresses be aligned to + // the transaction size. + // -------------------------------------- + wire [PKT_ADDR_W-1 : 0] av_address_aligned; + generate + if (NUMSYMBOLS > 1) begin + assign av_address_aligned = + {av_address[PKT_ADDR_W-1 : BITS_TO_ZERO], {BITS_TO_ZERO {1'b0}}}; + end + else begin + assign av_address_aligned = av_address; + end + endgenerate + + // -------------------------------------- + // Command & Response Construction + // -------------------------------------- + always @* begin + cp_data = '0; // default assignment; override below as needed. + + cp_data[PKT_PROTECTION_H:PKT_PROTECTION_L] = av_debugaccess; + cp_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L ] = burstwrap_value_int[PKT_BURSTWRAP_W-1:0]; + cp_data[PKT_BYTE_CNT_H :PKT_BYTE_CNT_L ] = av_burstcount; + cp_data[PKT_ADDR_H :PKT_ADDR_L ] = av_address_aligned; + cp_data[PKT_TRANS_EXCLUSIVE ] = 1'b0; + cp_data[PKT_TRANS_LOCK ] = av_lock; + cp_data[PKT_TRANS_COMPRESSED_READ ] = av_read & is_burst; + cp_data[PKT_TRANS_READ ] = av_read; + cp_data[PKT_TRANS_WRITE ] = av_write; + cp_data[PKT_TRANS_POSTED ] = av_write; + cp_data[PKT_DATA_H :PKT_DATA_L ] = av_writedata; + cp_data[PKT_BYTEEN_H :PKT_BYTEEN_L ] = av_byteenable; + cp_data[PKT_BURST_SIZE_H:PKT_BURST_SIZE_L] = burstsize_sig; + cp_data[PKT_BURST_TYPE_H:PKT_BURST_TYPE_L] = bursttype_value; + cp_data[PKT_SRC_ID_H :PKT_SRC_ID_L ] = id_int[PKT_SRC_ID_W-1:0]; + cp_data[PKT_THREAD_ID_H:PKT_THREAD_ID_L ] = '0; + cp_data[PKT_CACHE_H :PKT_CACHE_L ] = CACHE_VALUE; + cp_data[PKT_QOS_H : PKT_QOS_L] = '0; + cp_data[PKT_ADDR_SIDEBAND_H:PKT_ADDR_SIDEBAND_L] = '0; + cp_data[PKT_DATA_SIDEBAND_H :PKT_DATA_SIDEBAND_L] = '0; + + av_readdata = rp_data[PKT_DATA_H : PKT_DATA_L]; + end + + // -------------------------------------- + // Command Control + // -------------------------------------- + always @* begin + cp_valid = 0; + + if (av_write || av_read) + cp_valid = 1; + end + + generate if (BURSTING) begin + reg sop_enable; + + always @(posedge clk, posedge reset) begin + if (reset) begin + sop_enable <= 1'b1; + end + else begin + if (cp_valid && cp_ready) begin + sop_enable <= 1'b0; + if (cp_endofpacket) + sop_enable <= 1'b1; + end + end + end + + assign cp_startofpacket = sop_enable; + assign cp_endofpacket = (av_read) | (av_burstcount == NUMSYMBOLS); + + end + else begin + + assign cp_startofpacket = 1'b1; + assign cp_endofpacket = 1'b1; + + end + endgenerate + + // -------------------------------------- + // Backpressure & Readdatavalid + // -------------------------------------- + always @* begin + rp_ready = 1; + av_waitrequest = 0; + av_readdatavalid = 0; + + av_waitrequest = !cp_ready; + + // -------------------------------------- + // Currently, responses are _always_ read responses because + // this Avalon agent only issues posted writes, which do + // not have responses. + // -------------------------------------- + av_readdatavalid = rp_valid; + + if (SUPPRESS_0_BYTEEN_RSP) begin + if (rp_data[PKT_BYTEEN_H:PKT_BYTEEN_L] == 0) + av_readdatavalid = 0; + end + end + +endmodule diff --git a/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_master_translator.sv b/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_master_translator.sv new file mode 100644 index 00000000..48178c09 --- /dev/null +++ b/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_master_translator.sv @@ -0,0 +1,450 @@ +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/12.1sp1/ip/merlin/altera_merlin_master_translator/altera_merlin_master_translator.sv#1 $ +// $Revision: #1 $ +// $Date: 2012/10/10 $ +// $Author: swbranch $ + +// -------------------------------------- +// Merlin Master Translator +// +// Converts Avalon-MM Master Interfaces into +// Avalon-MM Universal Master Interfaces +// -------------------------------------- + +`timescale 1 ns / 1 ns + + + +module altera_merlin_master_translator #( + parameter + AV_ADDRESS_W = 32, + AV_DATA_W = 32, + AV_BURSTCOUNT_W = 4, + AV_BYTEENABLE_W = 4, + + //Optional Port Declarations + + USE_BURSTCOUNT = 1, + USE_BEGINBURSTTRANSFER = 0, + USE_BEGINTRANSFER = 0, + USE_CHIPSELECT = 0, + USE_READ = 1, + USE_READDATAVALID = 1, + USE_WRITE = 1, + USE_WAITREQUEST = 1, + + AV_REGISTERINCOMINGSIGNALS = 0, + AV_SYMBOLS_PER_WORD = 4, + AV_ADDRESS_SYMBOLS = 0, + AV_CONSTANT_BURST_BEHAVIOR = 1, + AV_BURSTCOUNT_SYMBOLS = 0, + AV_LINEWRAPBURSTS = 0, + UAV_ADDRESS_W = 38, + UAV_BURSTCOUNT_W = 10, + UAV_CONSTANT_BURST_BEHAVIOR = 0 + )( + //Universal Avalon Master + input wire clk, + input wire reset, + output reg uav_write, + output reg uav_read, + output reg [UAV_ADDRESS_W -1 : 0] uav_address, + output reg [UAV_BURSTCOUNT_W -1 : 0] uav_burstcount, + output wire [AV_BYTEENABLE_W -1 : 0] uav_byteenable, + output wire [AV_DATA_W -1 : 0] uav_writedata, + output wire uav_lock, + output wire uav_debugaccess, + output wire uav_clken, + + input wire [ AV_DATA_W -1 : 0] uav_readdata, + input wire uav_readdatavalid, + input wire uav_waitrequest, + + //Avalon-MM !Master + input reg av_write, + input reg av_read, + input wire [AV_ADDRESS_W -1 : 0] av_address, + input wire [AV_BYTEENABLE_W -1 : 0] av_byteenable, + input wire [AV_BURSTCOUNT_W -1 : 0] av_burstcount, + input wire [AV_DATA_W -1 : 0] av_writedata, + input wire av_begintransfer, + input wire av_beginbursttransfer, + input wire av_lock, + input wire av_chipselect, + input wire av_debugaccess, + input wire av_clken, + + output wire [AV_DATA_W -1 : 0] av_readdata, + output wire av_readdatavalid, + output reg av_waitrequest + ); + + + localparam BITS_PER_WORD = clog2(AV_SYMBOLS_PER_WORD - 1); + localparam AV_MAX_SYMBOL_BURST = flog2( pow2(AV_BURSTCOUNT_W - 1) * (AV_BURSTCOUNT_SYMBOLS ? 1 : (AV_SYMBOLS_PER_WORD)) ); + localparam AV_MAX_SYMBOL_BURST_MINUS_ONE = AV_MAX_SYMBOL_BURST ? AV_MAX_SYMBOL_BURST - 1 : 0 ; + + localparam UAV_BURSTCOUNT_W_OR_32 = UAV_BURSTCOUNT_W > 32 ? 31 : UAV_BURSTCOUNT_W -1; + localparam UAV_ADDRESS_W_OR_32 = UAV_ADDRESS_W > 32 ? 31 : UAV_ADDRESS_W -1; + + + // -1 for burstcount restriction 2^(n-1) + + localparam BITS_PER_WORD_BURSTCOUNT = UAV_BURSTCOUNT_W == 1 ? 0 : BITS_PER_WORD; + localparam BITS_PER_WORD_ADDRESS = UAV_ADDRESS_W == 1 ? 0 : BITS_PER_WORD; + + localparam ADDRESS_LOW = AV_ADDRESS_SYMBOLS ? 0 : BITS_PER_WORD_ADDRESS; + localparam BURSTCOUNT_LOW = AV_BURSTCOUNT_SYMBOLS ? 0 : BITS_PER_WORD_BURSTCOUNT; + + localparam ADDRESS_HIGH = UAV_ADDRESS_W > AV_ADDRESS_W + ADDRESS_LOW ? AV_ADDRESS_W : UAV_ADDRESS_W - ADDRESS_LOW; + localparam BURSTCOUNT_HIGH = UAV_BURSTCOUNT_W > AV_BURSTCOUNT_W + BURSTCOUNT_LOW ? AV_BURSTCOUNT_W : UAV_BURSTCOUNT_W - BURSTCOUNT_LOW; + + function integer flog2; + input [31:0] Depth; + integer i; + begin + i = Depth; + if ( i <= 0 ) flog2 = 0; + else begin + for(flog2 = -1; i > 0; flog2 = flog2 + 1) + i = i >> 1; + end + end + + endfunction // flog2 + + function integer clog2; + input [31:0] Depth; + integer i; + begin + i = Depth; + for(clog2 = 0; i > 0; clog2 = clog2 + 1) + i = i >> 1; + end + + endfunction + + function integer pow2; + input [31:0] toShift; + begin + pow2=1; + pow2= pow2 << toShift; + end + endfunction // pow2 + + // ------------------------------------------------- + // Assign some constants to appropriately-sized signals to + // avoid synthesis warnings. This also helps some simulators + // with their inferred sensitivity lists. + // ------------------------------------------------- + // Calculate the symbols per word as the power of 2 extended symbols per word + wire [31:0] symbols_per_word_int = 2**(clog2(AV_SYMBOLS_PER_WORD[UAV_BURSTCOUNT_W_OR_32 : 0] - 1)); + wire [UAV_BURSTCOUNT_W_OR_32 : 0] symbols_per_word = symbols_per_word_int[UAV_BURSTCOUNT_W_OR_32 : 0]; + + + reg internal_beginbursttransfer; + reg internal_begintransfer; + reg [UAV_ADDRESS_W - 1: 0 ] uav_address_pre; + reg [UAV_BURSTCOUNT_W - 1 : 0 ] uav_burstcount_pre; + + + + reg uav_read_pre; + reg uav_write_pre; + reg read_accepted; + + //Passthru assignmenst + + assign uav_writedata = av_writedata; + assign av_readdata = uav_readdata; + assign uav_byteenable = av_byteenable; + assign uav_lock = av_lock; + assign av_readdatavalid = uav_readdatavalid; + assign uav_debugaccess = av_debugaccess; + assign uav_clken = av_clken; + + //address + burstcount assignment + + reg [UAV_ADDRESS_W - 1 : 0] address_register; + reg [UAV_BURSTCOUNT_W - 1 : 0] burstcount_register; + + always @* begin + uav_address=uav_address_pre; + uav_burstcount=uav_burstcount_pre; + + if(AV_CONSTANT_BURST_BEHAVIOR && !UAV_CONSTANT_BURST_BEHAVIOR && ~internal_beginbursttransfer) begin + uav_address=address_register; + uav_burstcount=burstcount_register; + end + end + + reg first_burst_stalled; + reg burst_stalled; + + + wire[UAV_ADDRESS_W-1:0] combi_burst_addr_reg; + wire [UAV_ADDRESS_W-1:0] combi_addr_reg; + generate + if(AV_LINEWRAPBURSTS && AV_MAX_SYMBOL_BURST!=0) begin + if(AV_MAX_SYMBOL_BURST > UAV_ADDRESS_W - 1) begin + assign combi_burst_addr_reg = { uav_address_pre[UAV_ADDRESS_W-1:0] + AV_SYMBOLS_PER_WORD[UAV_ADDRESS_W-1:0] }; + assign combi_addr_reg = { address_register[UAV_ADDRESS_W-1:0] + AV_SYMBOLS_PER_WORD[UAV_ADDRESS_W-1:0] }; + end + else begin + assign combi_burst_addr_reg = { uav_address_pre[UAV_ADDRESS_W - 1 : AV_MAX_SYMBOL_BURST], uav_address_pre[AV_MAX_SYMBOL_BURST_MINUS_ONE:0] + AV_SYMBOLS_PER_WORD[AV_MAX_SYMBOL_BURST_MINUS_ONE:0] }; + assign combi_addr_reg = { address_register[UAV_ADDRESS_W - 1 : AV_MAX_SYMBOL_BURST], address_register[AV_MAX_SYMBOL_BURST_MINUS_ONE:0] + AV_SYMBOLS_PER_WORD[AV_MAX_SYMBOL_BURST_MINUS_ONE:0] }; + end + end + else begin + assign combi_burst_addr_reg = + uav_address_pre + AV_SYMBOLS_PER_WORD[UAV_ADDRESS_W_OR_32:0]; + assign combi_addr_reg = + address_register + AV_SYMBOLS_PER_WORD[UAV_ADDRESS_W_OR_32:0]; + end + endgenerate + + always@(posedge clk, posedge reset) begin + + if(reset) begin + address_register <= '0; + burstcount_register <= '0; + first_burst_stalled <= 1'b0; + burst_stalled <= 1'b0; + end + else begin + address_register <= address_register; + burstcount_register <= burstcount_register; + + if(internal_beginbursttransfer||first_burst_stalled) begin + + if(av_waitrequest) begin + first_burst_stalled <= 1'b1; + address_register <= uav_address_pre; + burstcount_register <= uav_burstcount_pre; + end else begin + first_burst_stalled <= 1'b0; + address_register <= combi_burst_addr_reg; + burstcount_register <= uav_burstcount_pre - symbols_per_word; + end + end + + else if(internal_begintransfer || burst_stalled) begin + if(~av_waitrequest) begin + burst_stalled <= 1'b0; + address_register <= combi_addr_reg; + burstcount_register <= burstcount_register - symbols_per_word; + end else + burst_stalled<=1'b1; + end + end + + end + + //Address + always @* begin + uav_address_pre = '0; + + if(AV_ADDRESS_SYMBOLS) + uav_address_pre=av_address[ ( ADDRESS_HIGH ? ADDRESS_HIGH - 1 : 0 ) : 0 ]; + else begin + uav_address_pre[ UAV_ADDRESS_W - 1 : ADDRESS_LOW ] = av_address[( ADDRESS_HIGH ? ADDRESS_HIGH - 1 : 0) : 0 ]; + end + end + + //Burstcount + always@* begin + uav_burstcount_pre = symbols_per_word; // default to a single transfer + + if(USE_BURSTCOUNT) begin + uav_burstcount_pre = '0; + + if(AV_BURSTCOUNT_SYMBOLS) + uav_burstcount_pre = av_burstcount[( BURSTCOUNT_HIGH ? BURSTCOUNT_HIGH - 1 : 0 ) :0 ]; + else begin + uav_burstcount_pre[ UAV_BURSTCOUNT_W - 1 : BURSTCOUNT_LOW] = av_burstcount[( BURSTCOUNT_HIGH ? BURSTCOUNT_HIGH - 1 : 0 ) : 0 ]; + end + + end + + end + + + //waitrequest translation + + always@(posedge clk, posedge reset) begin + if(reset) + read_accepted <= 1'b0; + else begin + read_accepted <= read_accepted; + + if(read_accepted == 1 && uav_readdatavalid == 1) // reset acceptance only when rdv arrives + read_accepted <= 1'b0; + + if(read_accepted == 0) + read_accepted<=av_waitrequest ? uav_read_pre & ~uav_waitrequest : 1'b0; + end + + end + + reg write_accepted = 0; + generate if (AV_REGISTERINCOMINGSIGNALS) begin + always@(posedge clk, posedge reset) begin + if(reset) + write_accepted <= 1'b0; + else begin + write_accepted <= + ~av_waitrequest ? 1'b0 : + uav_write & ~uav_waitrequest? 1'b1 : + write_accepted; + end + end + end endgenerate + + always@* begin + av_waitrequest = uav_waitrequest; + + if(USE_READDATAVALID == 0 ) begin + av_waitrequest = uav_read_pre ? ~uav_readdatavalid : uav_waitrequest; + end + + if (AV_REGISTERINCOMINGSIGNALS) begin + av_waitrequest = + uav_read_pre ? ~uav_readdatavalid : + uav_write_pre ? (internal_begintransfer | uav_waitrequest) & ~write_accepted : + 1'b1; + end + + if(USE_WAITREQUEST == 0) begin + av_waitrequest = 0; + end + end + + //read/write generation + always@* begin + + uav_write = 1'b0; + uav_write_pre = 1'b0; + uav_read = 1'b0; + uav_read_pre = 1'b0; + + if(!USE_CHIPSELECT) begin + if (USE_READ) begin + uav_read_pre=av_read; + end + + if (USE_WRITE) begin + uav_write_pre=av_write; + end + end + else begin + if(!USE_WRITE && USE_READ) begin + uav_read_pre=av_read; + uav_write_pre=av_chipselect & ~av_read; + end + else if(!USE_READ && USE_WRITE) begin + uav_write_pre=av_write; + uav_read_pre = av_chipselect & ~av_write; + end + else if (USE_READ && USE_WRITE) begin + uav_write_pre=av_write; + uav_read_pre=av_read; + end + end + + if(USE_READDATAVALID == 0) + uav_read = uav_read_pre & ~read_accepted; + else + uav_read = uav_read_pre; + + if(AV_REGISTERINCOMINGSIGNALS == 0) + uav_write=uav_write_pre; + else + uav_write=uav_write_pre & ~write_accepted; + + + end + + // ------------------- + // Begintransfer Assigment + // ------------------- + + reg end_begintransfer; + + always@* begin + if(USE_BEGINTRANSFER) begin + internal_begintransfer = av_begintransfer; + end else begin + internal_begintransfer = ( uav_write | uav_read ) & ~end_begintransfer; + end + end + + always@ ( posedge clk or posedge reset ) begin + + if(reset) begin + end_begintransfer <= 1'b0; + end + else begin + + if(internal_begintransfer == 1 && uav_waitrequest) + end_begintransfer <= 1'b1; + else if(uav_waitrequest) + end_begintransfer <= end_begintransfer; + else + end_begintransfer <= 1'b0; + + end + + end + + // ------------------- + // Beginbursttransfer Assigment + // ------------------- + + reg end_beginbursttransfer; + wire last_burst_transfer_pre; + wire last_burst_transfer_reg; + wire last_burst_transfer; + + // compare values before the mux to shorten critical path; benchmark before changing + assign last_burst_transfer_pre = (uav_burstcount_pre == symbols_per_word); + assign last_burst_transfer_reg = (burstcount_register == symbols_per_word); + assign last_burst_transfer = (internal_beginbursttransfer) ? last_burst_transfer_pre : last_burst_transfer_reg; + + always@* begin + if(USE_BEGINBURSTTRANSFER) begin + internal_beginbursttransfer = av_beginbursttransfer; + end else begin + internal_beginbursttransfer = uav_read ? internal_begintransfer : internal_begintransfer && ~end_beginbursttransfer; + end + end + + always@ ( posedge clk or posedge reset ) begin + + if(reset) begin + end_beginbursttransfer <= 1'b0; + end + else begin + end_beginbursttransfer <= end_beginbursttransfer; + if( last_burst_transfer && internal_begintransfer || uav_read ) begin + end_beginbursttransfer <= 1'b0; + end + else if(uav_write && internal_begintransfer) begin + end_beginbursttransfer <= 1'b1; + end + end + + end + + endmodule diff --git a/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_slave_agent.sv b/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_slave_agent.sv new file mode 100644 index 00000000..cce3c521 --- /dev/null +++ b/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_slave_agent.sv @@ -0,0 +1,479 @@ +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// (C) 2001-2011 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/12.1sp1/ip/merlin/altera_merlin_slave_agent/altera_merlin_slave_agent.sv#1 $ +// $Revision: #1 $ +// $Date: 2012/10/10 $ +// $Author: swbranch $ + +`timescale 1 ns / 1 ns + +module altera_merlin_slave_agent +#( + // Packet parameters + parameter PKT_BEGIN_BURST = 81, + parameter PKT_DATA_H = 31, + parameter PKT_DATA_L = 0, + parameter PKT_SYMBOL_W = 8, + parameter PKT_BYTEEN_H = 71, + parameter PKT_BYTEEN_L = 68, + parameter PKT_ADDR_H = 63, + parameter PKT_ADDR_L = 32, + parameter PKT_TRANS_LOCK = 87, + parameter PKT_TRANS_COMPRESSED_READ = 67, + parameter PKT_TRANS_POSTED = 66, + parameter PKT_TRANS_WRITE = 65, + parameter PKT_TRANS_READ = 64, + parameter PKT_SRC_ID_H = 74, + parameter PKT_SRC_ID_L = 72, + parameter PKT_DEST_ID_H = 77, + parameter PKT_DEST_ID_L = 75, + parameter PKT_BURSTWRAP_H = 85, + parameter PKT_BURSTWRAP_L = 82, + parameter PKT_BYTE_CNT_H = 81, + parameter PKT_BYTE_CNT_L = 78, + parameter PKT_PROTECTION_H = 86, + parameter PKT_PROTECTION_L = 86, + parameter PKT_RESPONSE_STATUS_H = 89, + parameter PKT_RESPONSE_STATUS_L = 88, + parameter PKT_BURST_SIZE_H = 92, + parameter PKT_BURST_SIZE_L = 90, + parameter ST_DATA_W = 93, + parameter ST_CHANNEL_W = 32, + + // Slave parameters + parameter ADDR_W = PKT_ADDR_H - PKT_ADDR_L + 1, + parameter AVS_DATA_W = PKT_DATA_H - PKT_DATA_L + 1, + parameter AVS_BURSTCOUNT_W = 4, + parameter PKT_SYMBOLS = AVS_DATA_W / PKT_SYMBOL_W, + + // Slave agent parameters + parameter PREVENT_FIFO_OVERFLOW = 0, + parameter SUPPRESS_0_BYTEEN_CMD = 1, + + // Derived slave parameters + parameter AVS_BE_W = PKT_BYTEEN_H - PKT_BYTEEN_L + 1, + parameter BURST_SIZE_W = 3, + + // Derived FIFO width + parameter FIFO_DATA_W = ST_DATA_W + 1 +) +( + + input clk, + input reset, + + // Universal-Avalon anti-slave + output [ADDR_W-1:0] m0_address, + output [AVS_BURSTCOUNT_W-1:0] m0_burstcount, + output [AVS_BE_W-1:0] m0_byteenable, + output m0_read, + input [AVS_DATA_W-1:0] m0_readdata, + input m0_waitrequest, + output m0_write, + output [AVS_DATA_W-1:0] m0_writedata, + input m0_readdatavalid, + output m0_debugaccess, + output m0_lock, + + // Avalon-ST FIFO interfaces. + // Note: there's no need to include the "data" field here, at least for + // reads, since readdata is filled in from slave info. To keep life + // simple, have a data field, but fill it with 0s. + // Av-st response fifo source interface + output reg [FIFO_DATA_W-1:0] rf_source_data, + output rf_source_valid, + output rf_source_startofpacket, + output rf_source_endofpacket, + input rf_source_ready, + + // Av-st response fifo sink interface + input [FIFO_DATA_W-1:0] rf_sink_data, + input rf_sink_valid, + input rf_sink_startofpacket, + input rf_sink_endofpacket, + output rf_sink_ready, + + // Av-st readdata fifo src interface + output [AVS_DATA_W-1:0] rdata_fifo_src_data, + output rdata_fifo_src_valid, + input rdata_fifo_src_ready, + + // Av-st readdata fifo sink interface + input [AVS_DATA_W-1:0] rdata_fifo_sink_data, + input rdata_fifo_sink_valid, + output rdata_fifo_sink_ready, + + // Av-st sink command packet interface + output cp_ready, + input cp_valid, + input [ST_DATA_W-1:0] cp_data, + input [ST_CHANNEL_W-1:0] cp_channel, + input cp_startofpacket, + input cp_endofpacket, + + // Av-st source response packet interface + input rp_ready, + output rp_valid, + output reg [ST_DATA_W-1:0] rp_data, + output rp_startofpacket, + output rp_endofpacket +); + + // -------------------------------------------------- + // Ceil(log2()) function log2ceil of 4 = 2 + // -------------------------------------------------- + function integer log2ceil; + input reg[63:0] val; + reg [63:0] i; + + begin + i = 1; + log2ceil = 0; + + while (i < val) begin + log2ceil = log2ceil + 1; + i = i << 1; + end + end + endfunction + + // ------------------------------------------------ + // Local Parameters + // ------------------------------------------------ + localparam DATA_W = PKT_DATA_H - PKT_DATA_L + 1; + localparam BE_W = PKT_BYTEEN_H - PKT_BYTEEN_L + 1; + localparam MID_W = PKT_SRC_ID_H - PKT_SRC_ID_L + 1; + localparam SID_W = PKT_DEST_ID_H - PKT_DEST_ID_L + 1; + localparam BYTE_CNT_W = PKT_BYTE_CNT_H - PKT_BYTE_CNT_L + 1; + localparam BURSTWRAP_W = PKT_BURSTWRAP_H - PKT_BURSTWRAP_L + 1; + localparam BURSTSIZE_W = PKT_BURST_SIZE_H - PKT_BURST_SIZE_L + 1; + localparam RESPONSE_W = PKT_RESPONSE_STATUS_H - PKT_RESPONSE_STATUS_L + 1; + localparam BITS_TO_MASK = log2ceil(PKT_SYMBOLS); + + // ------------------------------------------------ + // Signals + // ------------------------------------------------ + wire [DATA_W-1:0] cmd_data; + wire [BE_W-1:0] cmd_byteen; + wire [ADDR_W-1:0] cmd_addr; + wire [MID_W-1:0] cmd_mid; + wire [SID_W-1:0] cmd_sid; + wire cmd_read; + wire cmd_write; + wire cmd_compressed; + wire cmd_posted; + wire [BYTE_CNT_W-1:0] cmd_byte_cnt; + wire [BURSTWRAP_W-1:0] cmd_burstwrap; + wire [BURSTSIZE_W-1:0] cmd_burstsize; + wire cmd_debugaccess; + + wire byteen_asserted; + wire needs_response_synthesis; + wire generate_response; + + // Assign command fields + assign cmd_data = cp_data[PKT_DATA_H :PKT_DATA_L ]; + assign cmd_byteen = cp_data[PKT_BYTEEN_H:PKT_BYTEEN_L]; + assign cmd_addr = cp_data[PKT_ADDR_H :PKT_ADDR_L ]; + assign cmd_compressed = cp_data[PKT_TRANS_COMPRESSED_READ]; + assign cmd_posted = cp_data[PKT_TRANS_POSTED]; + assign cmd_write = cp_data[PKT_TRANS_WRITE]; + assign cmd_read = cp_data[PKT_TRANS_READ]; + assign cmd_mid = cp_data[PKT_SRC_ID_H :PKT_SRC_ID_L]; + assign cmd_sid = cp_data[PKT_DEST_ID_H:PKT_DEST_ID_L]; + assign cmd_byte_cnt = cp_data[PKT_BYTE_CNT_H:PKT_BYTE_CNT_L]; + assign cmd_burstwrap = cp_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L]; + assign cmd_burstsize = cp_data[PKT_BURST_SIZE_H:PKT_BURST_SIZE_L]; + assign cmd_debugaccess = cp_data[PKT_PROTECTION_L]; + + // Local "ready_for_command" signal: deasserted when the agent is unable to accept + // another command, e.g. rdv FIFO is full, (local readdata storage is full && + // ~rp_ready), ... + // Say, this could depend on the type of command, for example, even if the + // rdv FIFO is full, a write request can be accepted. For later. + wire ready_for_command; + + wire local_lock = cp_valid & cp_data[PKT_TRANS_LOCK]; + wire local_write = cp_valid & cp_data[PKT_TRANS_WRITE]; + wire local_read = cp_valid & cp_data[PKT_TRANS_READ]; + wire local_compressed_read = cp_valid & cp_data[PKT_TRANS_COMPRESSED_READ]; + wire nonposted_write_endofpacket = ~cp_data[PKT_TRANS_POSTED] & local_write & cp_endofpacket; + + // num_symbols is PKT_SYMBOLS, appropriately sized. + wire [31:0] int_num_symbols = PKT_SYMBOLS; + wire [BYTE_CNT_W-1:0] num_symbols = int_num_symbols[BYTE_CNT_W-1:0]; + + generate + if (PREVENT_FIFO_OVERFLOW) begin : prevent_fifo_overflow + // --------------------------------------------------- + // Backpressure if the slave says to, or if FIFO overflow may occur. + // + // All commands are backpressured once the FIFO is full + // even if they don't need storage. This breaks a long + // combinatorial path from the master read/write through + // this logic and back to the master via the backpressure + // path. + // + // To avoid a loss of throughput the FIFO will be parameterized + // one slot deeper. The extra slot should never be used in normal + // operation, but should a slave misbehave and accept one more + // read than it should then backpressure will kick in. + // + // An example: assume a slave with MPRT = 2. It can accept a + // command sequence RRWW without backpressuring. If the FIFO is + // only 2 deep, we'd backpressure the writes leading to loss of + // throughput. If the FIFO is 3 deep, we'll only backpressure when + // RRR... which is an illegal condition anyway. + // --------------------------------------------------- + + assign ready_for_command = rf_source_ready; + assign cp_ready = (~m0_waitrequest | ~byteen_asserted) && ready_for_command; + + end else begin : no_prevent_fifo_overflow + + // Do not suppress the command or the slave will + // not be able to waitrequest + assign ready_for_command = 1'b1; + // Backpressure only if the slave says to. + assign cp_ready = ~m0_waitrequest | ~byteen_asserted; + + end + endgenerate + + generate if (SUPPRESS_0_BYTEEN_CMD) begin : suppress_0_byteen_cmd + assign byteen_asserted = |cmd_byteen; + end else begin : no_suppress_0_byteen_cmd + assign byteen_asserted = 1'b1; + end + endgenerate + + // ------------------------------------------------------------------- + // Extract avalon signals from command packet. + // ------------------------------------------------------------------- + // Mask off the lower bits of address. + // The burst adapter before this component will break narrow sized packets + // into sub-bursts of length 1. However, the packet addresses are preserved, + // which means this component may see size-aligned addresses. + // + // Masking ensures that the addresses seen by an Avalon slave are aligned to + // the full data width instead of the size. + // + // Example: + // output from burst adapter (datawidth=4, size=2 bytes): + // subburst1 addr=0, subburst2 addr=2, subburst3 addr=4, subburst4 addr=6 + // expected output from slave agent: + // subburst1 addr=0, subburst2 addr=0, subburst3 addr=4, subburst4 addr=4 + generate + if (BITS_TO_MASK > 0) begin : mask_address + + assign m0_address = { cmd_addr[ADDR_W-1:BITS_TO_MASK], {BITS_TO_MASK{1'b0}} }; + + end else begin : no_mask_address + + assign m0_address = cmd_addr; + + end + endgenerate + + assign m0_byteenable = cmd_byteen; + assign m0_writedata = cmd_data; + + // Note: no Avalon-MM slave in existence accepts uncompressed read bursts - + // this sort of burst exists only in merlin fabric ST packets. What to do + // if we see such a burst? All beats in that burst need to be transmitted + // to the slave so we have enough space-time for byteenable expression. + // + // There can be multiple bursts in a packet, but only one beat per burst + // in cases. The exception is when we've decided not to insert a + // burst adapter for efficiency reasons, in which case this agent is also + // responsible for driving burstcount to 1 on each beat of an uncompressed + // read burst. + + assign m0_read = ready_for_command & byteen_asserted & + (local_compressed_read | local_read); + + generate + begin : m0_burstcount_zero_pad + // AVS_BURSTCOUNT_W and BYTE_CNT_W may not be equal. Assign m0_burstcount + // from a sub-range, or 0-pad, as appropriate. + if (AVS_BURSTCOUNT_W > BYTE_CNT_W) begin + wire [AVS_BURSTCOUNT_W - BYTE_CNT_W - 1 : 0] zero_pad = + {(AVS_BURSTCOUNT_W - BYTE_CNT_W) {1'b0}}; + assign m0_burstcount = (local_read & ~local_compressed_read) ? + {zero_pad, num_symbols} : + {zero_pad, cmd_byte_cnt}; + end + else begin : m0_burstcount_no_pad + assign m0_burstcount = (local_read & ~local_compressed_read) ? + num_symbols[AVS_BURSTCOUNT_W-1:0] : + cmd_byte_cnt[AVS_BURSTCOUNT_W-1:0]; + end + end + endgenerate + + assign m0_write = ready_for_command & local_write & byteen_asserted; + assign m0_lock = ready_for_command & local_lock & (m0_read | m0_write); + assign m0_debugaccess = cmd_debugaccess; + + // ------------------------------------------------------------------- + // Indirection layer for response packet values. Some may always wire + // directly from the slave translator; others will no doubt emerge from + // various FIFOs. + // What to put in resp_data when a write occured? Answer: it does not + // matter, because only response status is needed for non-posted writes, + // and the packet already has a field for that. + + assign rdata_fifo_src_valid = m0_readdatavalid; + assign rdata_fifo_src_data = m0_readdata; + + // ------------------------------------------------------------------ + // Generate a token when read commands are suppressed. The token + // is stored in the response FIFO, and will be used to synthesize + // a read response. The same token is used for non-posted write + // response synthesis. + // + // Note: this token is not generated for suppressed uncompressed read cycles; + // the burst uncompression logic at the read side of the response FIFO + // generates the correct number of responses. + // ------------------------------------------------------------------ + assign needs_response_synthesis = ((local_read | local_compressed_read) & !byteen_asserted) | nonposted_write_endofpacket; + + // Avalon-ST interfaces to external response fifo: + assign rf_source_valid = (local_read | local_compressed_read | nonposted_write_endofpacket) & ready_for_command & cp_ready; + assign rf_source_startofpacket = cp_startofpacket; + assign rf_source_endofpacket = cp_endofpacket; + always @* begin + // default: assign every command packet field to the response FIFO... + rf_source_data = {1'b0, cp_data}; + + // ... and override select fields as needed. + rf_source_data[FIFO_DATA_W-1] = needs_response_synthesis; + rf_source_data[PKT_DATA_H :PKT_DATA_L] = {DATA_W {1'b0}}; + rf_source_data[PKT_BYTEEN_H :PKT_BYTEEN_L] = cmd_byteen; + rf_source_data[PKT_ADDR_H :PKT_ADDR_L] = cmd_addr; + //rf_source_data[PKT_ADDR_H :PKT_ADDR_L] = m0_address; + rf_source_data[PKT_TRANS_COMPRESSED_READ] = cmd_compressed; + rf_source_data[PKT_TRANS_POSTED] = cmd_posted; + rf_source_data[PKT_TRANS_WRITE] = cmd_write; + rf_source_data[PKT_TRANS_READ] = cmd_read; + rf_source_data[PKT_SRC_ID_H :PKT_SRC_ID_L] = cmd_mid; + rf_source_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = cmd_sid; + rf_source_data[PKT_BYTE_CNT_H:PKT_BYTE_CNT_L] = cmd_byte_cnt; + rf_source_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L] = cmd_burstwrap; + rf_source_data[PKT_BURST_SIZE_H:PKT_BURST_SIZE_L] = cmd_burstsize; + rf_source_data[PKT_PROTECTION_H:PKT_PROTECTION_L] = '0; + rf_source_data[PKT_PROTECTION_L] = cmd_debugaccess; + end + + wire uncompressor_source_valid; + wire [BURSTSIZE_W-1:0] uncompressor_burstsize; + assign rp_valid = rdata_fifo_sink_valid | uncompressor_source_valid; + assign generate_response = rf_sink_data[FIFO_DATA_W-1]; + + wire [BYTE_CNT_W-1:0] rf_sink_byte_cnt = rf_sink_data[PKT_BYTE_CNT_H:PKT_BYTE_CNT_L]; + wire rf_sink_compressed = rf_sink_data[PKT_TRANS_COMPRESSED_READ]; + wire [BURSTWRAP_W-1:0] rf_sink_burstwrap = rf_sink_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L]; + wire [BURSTSIZE_W-1:0] rf_sink_burstsize = rf_sink_data[PKT_BURST_SIZE_H:PKT_BURST_SIZE_L]; + wire [ADDR_W-1:0] rf_sink_addr = rf_sink_data[PKT_ADDR_H:PKT_ADDR_L]; + // a non posted write response is always completed in 1 cycle. Modify the startofpacket signal to 1'b1 instead of taking whatever is in the rf_fifo + wire rf_sink_startofpacket_wire = rf_sink_data[PKT_TRANS_WRITE] ? 1'b1 : rf_sink_startofpacket; + + wire [BYTE_CNT_W-1:0] burst_byte_cnt; + wire [BURSTWRAP_W-1:0] rp_burstwrap; + wire [ADDR_W-1:0] rp_address; + wire rp_is_compressed; + + // ------------------------------------------------------------------ + // Backpressure the readdata fifo if we're supposed to synthesize a response. + // This may be a read response (for suppressed reads) or a write response + // (for non-posted writes). + // ------------------------------------------------------------------ + assign rdata_fifo_sink_ready = rdata_fifo_sink_valid & rp_ready & ~(rf_sink_valid & generate_response); + + always @* begin + // By default, return all fields... + rp_data = rf_sink_data[ST_DATA_W - 1 : 0]; + + // ... and override specific fields. + rp_data[PKT_DATA_H :PKT_DATA_L] = rdata_fifo_sink_data; + // Assignments directly from the response fifo. + rp_data[PKT_TRANS_POSTED] = rf_sink_data[PKT_TRANS_POSTED]; + rp_data[PKT_TRANS_WRITE] = rf_sink_data[PKT_TRANS_WRITE]; + rp_data[PKT_SRC_ID_H :PKT_SRC_ID_L] = rf_sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L]; + rp_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = rf_sink_data[PKT_SRC_ID_H : PKT_SRC_ID_L]; + rp_data[PKT_BYTEEN_H :PKT_BYTEEN_L] = rf_sink_data[PKT_BYTEEN_H : PKT_BYTEEN_L]; + rp_data[PKT_PROTECTION_H:PKT_PROTECTION_L] = rf_sink_data[PKT_PROTECTION_H:PKT_PROTECTION_L]; + + // Burst uncompressor assignments + rp_data[PKT_ADDR_H :PKT_ADDR_L] = rp_address; + rp_data[PKT_BURSTWRAP_H:PKT_BURSTWRAP_L] = rp_burstwrap; + rp_data[PKT_BYTE_CNT_H:PKT_BYTE_CNT_L] = burst_byte_cnt; + rp_data[PKT_TRANS_READ] = rf_sink_data[PKT_TRANS_READ] | rf_sink_data[PKT_TRANS_COMPRESSED_READ]; + rp_data[PKT_TRANS_COMPRESSED_READ] = rp_is_compressed; + + // avalon slaves always respond with "okay" + rp_data[PKT_RESPONSE_STATUS_H:PKT_RESPONSE_STATUS_L] = {RESPONSE_W{ 1'b0 }}; + rp_data[PKT_BURST_SIZE_H:PKT_BURST_SIZE_L] = uncompressor_burstsize; + end + + // ------------------------------------------------------------------ + // Note: the burst uncompressor may be asked to generate responses for + // write packets; these are treated the same as single-cycle uncompressed + // reads. + // ------------------------------------------------------------------ + altera_merlin_burst_uncompressor #( + .ADDR_W (ADDR_W), + .BURSTWRAP_W (BURSTWRAP_W), + .BYTE_CNT_W (BYTE_CNT_W), + .PKT_SYMBOLS (PKT_SYMBOLS) + ) uncompressor + ( + .clk (clk), + .reset (reset), + .sink_startofpacket (rf_sink_startofpacket_wire), + .sink_endofpacket (rf_sink_endofpacket), + .sink_valid (rf_sink_valid & (rdata_fifo_sink_valid | generate_response)), + .sink_ready (rf_sink_ready), + .sink_addr (rf_sink_addr), + .sink_burstwrap (rf_sink_burstwrap), + .sink_byte_cnt (rf_sink_byte_cnt), + .sink_is_compressed (rf_sink_compressed), + .sink_burstsize (rf_sink_burstsize), + + .source_startofpacket (rp_startofpacket), + .source_endofpacket (rp_endofpacket), + .source_valid (uncompressor_source_valid), + .source_ready (rp_ready), + .source_addr (rp_address), + .source_burstwrap (rp_burstwrap), + .source_byte_cnt (burst_byte_cnt), + .source_is_compressed (rp_is_compressed), + .source_burstsize (uncompressor_burstsize) + ); + +endmodule + diff --git a/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_slave_translator.sv b/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_slave_translator.sv new file mode 100644 index 00000000..70c798f6 --- /dev/null +++ b/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_slave_translator.sv @@ -0,0 +1,514 @@ +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + + +// $Id: //acds/rel/12.1sp1/ip/merlin/altera_merlin_slave_translator/altera_merlin_slave_translator.sv#1 $ +// $Revision: #1 $ +// $Date: 2012/10/10 $ +// $Author: swbranch $ + +// ------------------------------------- +// Merlin Slave Translator +// +// Translates Universal Avalon MM Slave +// to any Avalon MM Slave +// ------------------------------------- +// +//Notable Note: 0 AV_READLATENCY is not allowed and will be converted to a 1 cycle readlatency in all cases but one +//If you declare a slave with fixed read timing requirements, the readlatency of such a slave will be allowed to be zero +//The key feature here is that no same cycle turnaround data is processed through the fabric. + +//import avalon_utilities_pkg::*; + +`timescale 1 ns / 1 ns + +module altera_merlin_slave_translator + #( + parameter + //Widths + AV_ADDRESS_W = 32, + AV_DATA_W = 32, + AV_BURSTCOUNT_W = 4, + AV_BYTEENABLE_W = 4, + UAV_BYTEENABLE_W = 4, + + //Read Latency + AV_READLATENCY = 1, + + //Timing + AV_READ_WAIT_CYCLES = 0, + AV_WRITE_WAIT_CYCLES = 0, + AV_SETUP_WAIT_CYCLES = 0, + AV_DATA_HOLD_CYCLES = 0, + + //Optional Port Declarations + USE_READDATAVALID = 1, + USE_WAITREQUEST = 1, + + //Variable Addressing + AV_SYMBOLS_PER_WORD = 4, + AV_ADDRESS_SYMBOLS = 0, + AV_BURSTCOUNT_SYMBOLS = 0, + BITS_PER_WORD = clog2(AV_SYMBOLS_PER_WORD - 1), + UAV_ADDRESS_W = 38, + UAV_BURSTCOUNT_W = 10, + UAV_DATA_W = 32, + + AV_CONSTANT_BURST_BEHAVIOR = 0, + UAV_CONSTANT_BURST_BEHAVIOR = 0, + CHIPSELECT_THROUGH_READLATENCY = 0, + + // Tightly-Coupled Options + USE_UAV_CLKEN = 0, + AV_REQUIRE_UNALIGNED_ADDRESSES = 0 + ) + ( + + // ------------------- + // Clock & Reset + // ------------------- + input wire clk, + input wire reset, + + // ------------------- + // Universal Avalon Slave + // ------------------- + + input wire [UAV_ADDRESS_W - 1 : 0] uav_address, + input wire [UAV_DATA_W - 1 : 0] uav_writedata, + input wire uav_write, + input wire uav_read, + input wire [UAV_BURSTCOUNT_W - 1 : 0] uav_burstcount, + input wire [UAV_BYTEENABLE_W - 1 : 0] uav_byteenable, + input wire uav_lock, + input wire uav_debugaccess, + input wire uav_clken, + + output logic uav_readdatavalid, + output logic uav_waitrequest, + output logic[UAV_DATA_W - 1 : 0] uav_readdata, + + // ------------------- + // Customizable Avalon Master + // ------------------- + output logic [AV_ADDRESS_W - 1 : 0] av_address, + output logic [AV_DATA_W - 1 : 0] av_writedata, + output logic av_write, + output logic av_read, + output logic[AV_BURSTCOUNT_W - 1 : 0] av_burstcount, + output logic[AV_BYTEENABLE_W - 1 : 0] av_byteenable, + output logic[AV_BYTEENABLE_W - 1 : 0] av_writebyteenable, + output logic av_begintransfer, + output wire av_chipselect, + output logic av_beginbursttransfer, + output logic av_lock, + output wire av_clken, + output wire av_debugaccess, + output wire av_outputenable, + + input logic [AV_DATA_W - 1 : 0] av_readdata, + input logic av_readdatavalid, + input logic av_waitrequest + ); + + function integer clog2; + input [31:0] Depth; + integer i; + begin + i = Depth; + for(clog2 = 0; i > 0; clog2 = clog2 + 1) + i = i >> 1; + end + + endfunction + + function integer max; + //returns the larger of two passed arguments + input [31:0] one; + input [31:0] two; + + if(one > two) + max=one; + else + max=two; + endfunction // int + + localparam AV_READ_WAIT_INDEXED = (AV_SETUP_WAIT_CYCLES + AV_READ_WAIT_CYCLES); + localparam AV_WRITE_WAIT_INDEXED = (AV_SETUP_WAIT_CYCLES + AV_WRITE_WAIT_CYCLES); + localparam AV_DATA_HOLD_INDEXED = (AV_WRITE_WAIT_INDEXED + AV_DATA_HOLD_CYCLES); + localparam LOG2_OF_LATENCY_SUM = max(clog2(AV_READ_WAIT_INDEXED + 1),clog2(AV_DATA_HOLD_INDEXED + 1)); + localparam BURSTCOUNT_SHIFT_SELECTOR = AV_BURSTCOUNT_SYMBOLS ? 0 : BITS_PER_WORD; + localparam ADDRESS_SHIFT_SELECTOR = AV_ADDRESS_SYMBOLS ? 0 : BITS_PER_WORD; + + localparam ADDRESS_HIGH = ( UAV_ADDRESS_W > AV_ADDRESS_W + ADDRESS_SHIFT_SELECTOR ) ? + AV_ADDRESS_W : + UAV_ADDRESS_W - ADDRESS_SHIFT_SELECTOR; + + localparam BURSTCOUNT_HIGH = ( UAV_BURSTCOUNT_W > AV_BURSTCOUNT_W + BURSTCOUNT_SHIFT_SELECTOR ) ? + AV_BURSTCOUNT_W : + UAV_BURSTCOUNT_W - BURSTCOUNT_SHIFT_SELECTOR; + localparam BYTEENABLE_ADDRESS_BITS = ( clog2(UAV_BYTEENABLE_W) - 1 ) >= 1 ? clog2(UAV_BYTEENABLE_W) - 1 : 1; + + + // Calculate the symbols per word as the power of 2 extended symbols per word + wire [31 : 0] symbols_per_word_int = 2**(clog2(AV_SYMBOLS_PER_WORD[UAV_BURSTCOUNT_W : 0] - 1)); + wire [UAV_BURSTCOUNT_W : 0] symbols_per_word = symbols_per_word_int[UAV_BURSTCOUNT_W : 0]; + + // +-------------------------------- + // |Backwards Compatibility Signals + // +-------------------------------- + assign av_clken = (USE_UAV_CLKEN) ? uav_clken : 1'b1; + assign av_debugaccess = uav_debugaccess; + + // +------------------- + // |Passthru Signals + // +------------------- + + + //------------------------- + //Writedata and Byteenable + //------------------------- + + always@* begin + av_byteenable = '0; + av_byteenable = uav_byteenable[AV_BYTEENABLE_W - 1 : 0]; + end + + always@* begin + av_writedata = '0; + av_writedata = uav_writedata[AV_DATA_W - 1 : 0]; + end + + // +------------------- + // |Calculated Signals + // +------------------- + + logic [UAV_ADDRESS_W - 1 : 0 ] real_uav_address; + + function [BYTEENABLE_ADDRESS_BITS - 1 : 0 ] decode_byteenable; + input [UAV_BYTEENABLE_W - 1 : 0 ] byteenable; + + for(int i = 0 ; i < UAV_BYTEENABLE_W; i++ ) begin + if(byteenable[i] == 1) begin + return i; + end + end + + return '0; + + endfunction + + reg [AV_BURSTCOUNT_W - 1 : 0] burstcount_reg; + reg [AV_ADDRESS_W - 1 : 0] address_reg; + + + always@(posedge clk, posedge reset) begin + if(reset) begin + burstcount_reg <= '0; + address_reg <= '0; + end + else begin + burstcount_reg <= burstcount_reg; + address_reg <= address_reg; + + if(av_beginbursttransfer) begin + burstcount_reg <= uav_burstcount [BURSTCOUNT_HIGH - 1 + BURSTCOUNT_SHIFT_SELECTOR : BURSTCOUNT_SHIFT_SELECTOR ]; + address_reg <= real_uav_address [ADDRESS_HIGH - 1 + ADDRESS_SHIFT_SELECTOR : ADDRESS_SHIFT_SELECTOR ]; + + end + end + end + + + logic [BYTEENABLE_ADDRESS_BITS-1:0] temp_wire; + + always@* begin + if( AV_REQUIRE_UNALIGNED_ADDRESSES == 1) begin + temp_wire = decode_byteenable(uav_byteenable); + + real_uav_address = { uav_address[UAV_ADDRESS_W - 1 : BYTEENABLE_ADDRESS_BITS ], temp_wire[BYTEENABLE_ADDRESS_BITS - 1 : 0 ] }; + end + else begin + real_uav_address = uav_address; + end + + av_address = real_uav_address[ADDRESS_HIGH - 1 + ADDRESS_SHIFT_SELECTOR : ADDRESS_SHIFT_SELECTOR ]; + + if( AV_CONSTANT_BURST_BEHAVIOR && !UAV_CONSTANT_BURST_BEHAVIOR && ~av_beginbursttransfer ) + av_address = address_reg; + end + + always@* begin + av_burstcount=uav_burstcount[BURSTCOUNT_HIGH - 1 + BURSTCOUNT_SHIFT_SELECTOR : BURSTCOUNT_SHIFT_SELECTOR ]; + + if( AV_CONSTANT_BURST_BEHAVIOR && !UAV_CONSTANT_BURST_BEHAVIOR && ~av_beginbursttransfer ) + av_burstcount = burstcount_reg; + end + + always@* begin + av_lock = uav_lock; + end + + // ------------------- + // Writebyteenable Assignment + // ------------------- + +always@* begin + av_writebyteenable = { (AV_BYTEENABLE_W){uav_write} } & uav_byteenable[AV_BYTEENABLE_W - 1 : 0]; +end + + // ------------------- + // Waitrequest Assignment + // ------------------- + + reg av_waitrequest_generated; + reg av_waitrequest_generated_read; + reg av_waitrequest_generated_write; + reg waitrequest_reset_override; + + reg [ ( LOG2_OF_LATENCY_SUM ? LOG2_OF_LATENCY_SUM - 1 : 0 ) : 0 ] wait_latency_counter; + + always@(posedge reset, posedge clk) begin + + if(reset) begin + wait_latency_counter <= '0; + waitrequest_reset_override <= 1'h1; + end + else begin + waitrequest_reset_override <= 1'h0; + + wait_latency_counter <= '0; + + if( uav_read | uav_write ) + wait_latency_counter <= wait_latency_counter + 1'h1; + + if( ~uav_waitrequest | waitrequest_reset_override ) + wait_latency_counter <= '0; + + end + + end + + + always @* begin + + av_read = uav_read; + av_write = uav_write; + + av_waitrequest_generated = 1'h1; + av_waitrequest_generated_read = 1'h1; + av_waitrequest_generated_write = 1'h1; + + if(LOG2_OF_LATENCY_SUM == 1) + av_waitrequest_generated = 0; + + if(LOG2_OF_LATENCY_SUM > 1 && !USE_WAITREQUEST) begin + av_read = wait_latency_counter >= AV_SETUP_WAIT_CYCLES && uav_read; + av_write = wait_latency_counter >= AV_SETUP_WAIT_CYCLES && uav_write && wait_latency_counter <= AV_WRITE_WAIT_INDEXED; + + av_waitrequest_generated_read = wait_latency_counter != AV_READ_WAIT_INDEXED; + av_waitrequest_generated_write = wait_latency_counter != AV_DATA_HOLD_INDEXED; + + if(uav_write) + av_waitrequest_generated = av_waitrequest_generated_write; + else + av_waitrequest_generated = av_waitrequest_generated_read; + + end + + if(USE_WAITREQUEST) begin + uav_waitrequest = av_waitrequest; + end + else begin + uav_waitrequest = av_waitrequest_generated | waitrequest_reset_override; + end + + end + + // -------------- + // Readdata Assignment + // -------------- + + reg[(AV_DATA_W ? AV_DATA_W -1 : 0 ): 0] av_readdata_pre; + + always@(posedge clk, posedge reset) begin + if(reset) + av_readdata_pre <= 'b0; + else + av_readdata_pre <= av_readdata; + end + + always@* begin + uav_readdata = '0; + + if( AV_READLATENCY != 0 || USE_READDATAVALID ) begin + uav_readdata = av_readdata; + end + else begin + uav_readdata = av_readdata_pre; + end + end + // ------------------- + // Readdatavalid Assigment + // ------------------- + + reg[(AV_READLATENCY>0 ? AV_READLATENCY-1:0) :0] read_latency_shift_reg; + reg top_read_latency_shift_reg; + + + + always@* begin + + uav_readdatavalid=top_read_latency_shift_reg; + + if(USE_READDATAVALID) begin + uav_readdatavalid = av_readdatavalid; + end + + end + + always@* begin + + top_read_latency_shift_reg = uav_read & ~uav_waitrequest & ~waitrequest_reset_override; + + if(AV_READLATENCY == 1 || AV_READLATENCY == 0 ) begin + top_read_latency_shift_reg=read_latency_shift_reg; + end + + if (AV_READLATENCY > 1) begin + top_read_latency_shift_reg = read_latency_shift_reg[(AV_READLATENCY ? AV_READLATENCY-1 : 0)]; + end + + end + + always@(posedge reset, posedge clk) begin + + if (reset) begin + read_latency_shift_reg <= '0; + end + else if (av_clken) begin + + read_latency_shift_reg <= uav_read && ~uav_waitrequest & ~waitrequest_reset_override; + + for (int i=0; i+1 < AV_READLATENCY ; i+=1 ) begin + read_latency_shift_reg[i+1] <= read_latency_shift_reg[i]; + end + + end + + end + + // ------------ + // Chipselect and OutputEnable + // ------------ + + reg av_chipselect_pre; + wire cs_extension; + reg av_outputenable_pre; + + + assign av_chipselect = (uav_read | uav_write) ? 1'b1 : av_chipselect_pre; + assign cs_extension = ( (^ read_latency_shift_reg) & ~top_read_latency_shift_reg ) | ((| read_latency_shift_reg) & ~(^ read_latency_shift_reg)); + + assign av_outputenable = uav_read ? 1'b1 : av_outputenable_pre; + + always@(posedge reset, posedge clk) begin + if(reset) + av_outputenable_pre <= 1'b0; + else if( AV_READLATENCY == 0 && AV_READ_WAIT_INDEXED != 0 ) + av_outputenable_pre <= 0; + else + av_outputenable_pre <= cs_extension | uav_read; + end + + always@(posedge reset, posedge clk) begin + if(reset) begin + av_chipselect_pre <= 1'b0; + end + else begin + av_chipselect_pre <= 1'b0; + + if(AV_READLATENCY != 0 && CHIPSELECT_THROUGH_READLATENCY == 1) begin + //The AV_READLATENCY term is only here to prevent chipselect from remaining asserted while read and write fall. + //There is no functional impact as 0 cycle transactions are treated as 1 cycle on the other side of the translator. + if(uav_read) begin + av_chipselect_pre <= 1'b1; + end + else if(cs_extension == 1) begin + av_chipselect_pre <= 1'b1; + end + + end + end + end + + // ------------------- + // Begintransfer Assigment + // ------------------- + + reg end_begintransfer; + + always@* begin + av_begintransfer = ( uav_write | uav_read ) & ~end_begintransfer; + end + + always@ ( posedge clk or posedge reset ) begin + + if(reset) begin + end_begintransfer <= 1'b0; + end + else begin + + if(av_begintransfer == 1 && uav_waitrequest && ~waitrequest_reset_override) + end_begintransfer <= 1'b1; + else if(uav_waitrequest) + end_begintransfer <= end_begintransfer; + else + end_begintransfer <= 1'b0; + + end + + end + + // ------------------- + // Beginbursttransfer Assigment + // ------------------- + + reg end_beginbursttransfer; + reg in_transfer; + + + + always@* begin + av_beginbursttransfer = uav_read ? av_begintransfer : (av_begintransfer && ~end_beginbursttransfer && ~in_transfer); + end + + always@ ( posedge clk or posedge reset ) begin + if(reset) begin + end_beginbursttransfer <= 1'b0; + in_transfer <= 1'b0; + end + else begin + + end_beginbursttransfer <= uav_write & ( uav_burstcount != symbols_per_word ); + + if(uav_write && uav_burstcount == symbols_per_word) + in_transfer <=1'b0; + else if(uav_write) + in_transfer <=1'b1; + + end + + end + +endmodule diff --git a/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_traffic_limiter.sv b/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_traffic_limiter.sv new file mode 100644 index 00000000..8d552c7a --- /dev/null +++ b/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_traffic_limiter.sv @@ -0,0 +1,386 @@ +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/12.1sp1/ip/merlin/altera_merlin_traffic_limiter/altera_merlin_traffic_limiter.sv#1 $ +// $Revision: #1 $ +// $Date: 2012/10/10 $ +// $Author: swbranch $ + +// ----------------------------------------------------- +// Merlin Traffic Limiter +// +// Ensures that non-posted transaction responses are returned +// in order of request. Out-of-order responses can happen +// when a master does a non-posted transaction on a slave +// while responses are pending from a different slave. +// Examples +// 1) read to any latent slave, followed by a read to a +// variable-latent slave +// 2) read to any fixed-latency slave, followed by a read +// to another fixed-latency slave whose fixed latency is smaller. +// +// For now, we'll backpressure to prevent a master from +// switching slaves until all outstanding read responses have +// returned. We also have to suppress the read, obviously. +// +// Note: folding this into the router may give better fmax, +// consider after profiling. If folding into router, break +// into separate components: address router and destid router. +// This only needs to be in the address router. +// ----------------------------------------------------- + +`timescale 1 ns / 1 ns +// altera message_off 10036 +module altera_merlin_traffic_limiter +#( + parameter PKT_TRANS_POSTED = 1, + PKT_DEST_ID_H = 0, + PKT_DEST_ID_L = 0, + ST_DATA_W = 72, + ST_CHANNEL_W = 32, + MAX_OUTSTANDING_RESPONSES = 1, + PIPELINED = 0, + ENFORCE_ORDER = 1, + PKT_BYTE_CNT_H = 0, + PKT_BYTE_CNT_L = 0, + PKT_BYTEEN_H = 0, + PKT_BYTEEN_L = 0, + PKT_TRANS_WRITE = 0, + PKT_TRANS_READ = 0, + + // ------------------------------------- + // internal: allows optimization between this + // component and the demux + // ------------------------------------- + VALID_WIDTH = 1, + // ------------------------------------- + // beta: prevents all RAW and WAR hazards by + // waiting for responses to return before issuing + // a command with different direction. + // + // this is intended for Avalon masters that are + // connected to AXI slaves. + // + // expect this to be replaced with a less + // restrictive scheme in the future. + // ------------------------------------- + PREVENT_HAZARDS = 0 +) +( + // ------------------- + // Clock & Reset + // ------------------- + input clk, + input reset, + + // ------------------- + // Command + // ------------------- + input cmd_sink_valid, + input [ST_DATA_W-1 : 0] cmd_sink_data, + input [ST_CHANNEL_W-1 : 0] cmd_sink_channel, + input cmd_sink_startofpacket, + input cmd_sink_endofpacket, + output cmd_sink_ready, + + output reg [VALID_WIDTH-1 : 0] cmd_src_valid, + output reg [ST_DATA_W-1 : 0] cmd_src_data, + output reg [ST_CHANNEL_W-1 : 0] cmd_src_channel, + output reg cmd_src_startofpacket, + output reg cmd_src_endofpacket, + input cmd_src_ready, + + // ------------------- + // Response + // ------------------- + input rsp_sink_valid, + input [ST_DATA_W-1 : 0] rsp_sink_data, + input [ST_CHANNEL_W-1 : 0] rsp_sink_channel, + input rsp_sink_startofpacket, + input rsp_sink_endofpacket, + output reg rsp_sink_ready, + + output reg rsp_src_valid, + output reg [ST_DATA_W-1 : 0] rsp_src_data, + output reg [ST_CHANNEL_W-1 : 0] rsp_src_channel, + output reg rsp_src_startofpacket, + output reg rsp_src_endofpacket, + input rsp_src_ready +); + + // ------------------------------------- + // Local Parameters + // ------------------------------------- + localparam DEST_ID_W = PKT_DEST_ID_H - PKT_DEST_ID_L + 1; + localparam COUNTER_W = log2ceil(MAX_OUTSTANDING_RESPONSES + 1); + localparam PAYLOAD_W = ST_DATA_W + ST_CHANNEL_W + 4; + localparam NUMSYMBOLS = PKT_BYTEEN_H - PKT_BYTEEN_L + 1; + + // ----------------------------------------------------- + // Input Stage + // + // Figure out if the destination id has changed + // ----------------------------------------------------- + wire stage1_nonposted_cmd; + wire stage1_dest_changed; + wire stage1_trans_changed; + wire [PAYLOAD_W-1 : 0] stage1_payload; + wire [DEST_ID_W-1 : 0] dest_id; + reg [DEST_ID_W-1 : 0] last_dest_id; + reg [ST_CHANNEL_W-1:0] last_channel; + reg was_write; + wire is_write; + wire suppress; + wire save_dest_id; + + assign dest_id = cmd_sink_data[PKT_DEST_ID_H:PKT_DEST_ID_L]; + + generate if (PREVENT_HAZARDS == 1) begin : stage1_nonposted_block + assign stage1_nonposted_cmd = 1'b1; + end else begin + assign stage1_nonposted_cmd = (cmd_sink_data[PKT_TRANS_POSTED] == 0); + end + endgenerate + + // ------------------------------------ + // Optimization: for the unpipelined case, we can save the destid if + // this is an unsuppressed nonposted command. This eliminates + // dependence on the backpressure signal. + // + // Not a problem for the pipelined case. + // ------------------------------------ + generate begin : pipelined_save_dest_id + if (PIPELINED) + assign save_dest_id = cmd_sink_valid & cmd_sink_ready & stage1_nonposted_cmd; + else + assign save_dest_id = cmd_sink_valid & ~suppress & stage1_nonposted_cmd; + end endgenerate + + always @(posedge clk, posedge reset) begin + if (reset) begin + last_dest_id <= 0; + last_channel <= 0; + was_write <= 0; + end + else if (save_dest_id) begin + last_dest_id <= dest_id; + last_channel <= cmd_sink_channel; + was_write <= is_write; + end + end + + assign is_write = cmd_sink_data[PKT_TRANS_WRITE]; + assign stage1_dest_changed = (last_dest_id != dest_id); + assign stage1_trans_changed = (was_write != is_write); + + assign stage1_payload = { cmd_sink_data, + cmd_sink_channel, + cmd_sink_startofpacket, + cmd_sink_endofpacket, + stage1_dest_changed, + stage1_trans_changed }; + + // ----------------------------------------------------- + // (Optional) pipeline between input and output + // ----------------------------------------------------- + wire stage2_valid; + reg stage2_ready; + wire [PAYLOAD_W-1 : 0] stage2_payload; + + generate begin : pipelined_limiter + if (PIPELINED == 1) begin + altera_avalon_st_pipeline_base + #( + .BITS_PER_SYMBOL(PAYLOAD_W) + ) stage1_pipe ( + .clk (clk), + .reset (reset), + .in_ready (cmd_sink_ready), + .in_valid (cmd_sink_valid), + .in_data (stage1_payload), + .out_valid (stage2_valid), + .out_ready (stage2_ready), + .out_data (stage2_payload) + ); + end else begin + assign stage2_valid = cmd_sink_valid; + assign stage2_payload = stage1_payload; + assign cmd_sink_ready = stage2_ready; + end + end endgenerate + + // ----------------------------------------------------- + // Output Stage + // ----------------------------------------------------- + wire [ST_DATA_W-1 : 0] stage2_data; + wire [ST_CHANNEL_W-1:0] stage2_channel; + wire stage2_startofpacket; + wire stage2_endofpacket; + wire stage2_dest_changed; + wire stage2_trans_changed; + reg has_pending_responses; + reg [COUNTER_W-1 : 0] pending_response_count; + reg [COUNTER_W-1 : 0] next_pending_response_count; + wire nonposted_cmd; + wire nonposted_cmd_accepted; + wire response_accepted; + wire count_is_1; + wire count_is_0; + reg internal_valid; + + assign { stage2_data, + stage2_channel, + stage2_startofpacket, + stage2_endofpacket, + stage2_dest_changed, + stage2_trans_changed } = stage2_payload; + + generate if (PREVENT_HAZARDS == 1) begin : stage2_nonposted_block + assign nonposted_cmd = 1'b1; + end else begin + assign nonposted_cmd = (stage2_data[PKT_TRANS_POSTED] == 0); + end + endgenerate + + assign nonposted_cmd_accepted = nonposted_cmd && internal_valid && (cmd_src_ready && cmd_src_endofpacket); + + // ----------------------------------------------------- + // Use the sink's control signals here, because write responses may be dropped + // when hazard prevention is on. + // ----------------------------------------------------- + assign response_accepted = rsp_sink_valid && rsp_sink_ready && rsp_sink_endofpacket; + + always @* begin + next_pending_response_count = pending_response_count; + + if (nonposted_cmd_accepted) + next_pending_response_count = pending_response_count + 1'b1; + if (response_accepted) + next_pending_response_count = pending_response_count - 1'b1; + if (nonposted_cmd_accepted && response_accepted) + next_pending_response_count = pending_response_count; + end + + assign count_is_1 = (pending_response_count == 1); + assign count_is_0 = (pending_response_count == 0); + + always @(posedge clk, posedge reset) begin + if (reset) begin + pending_response_count <= 0; + has_pending_responses <= 0; + end + else begin + pending_response_count <= next_pending_response_count; + // synthesis translate_off + if (count_is_0 && response_accepted) + $display("%t: %m: Error: unexpected response: pending_response_count underflow", $time()); + // synthesis translate_on + has_pending_responses <= has_pending_responses + && ~(count_is_1 && response_accepted && ~nonposted_cmd_accepted) + || (count_is_0 && nonposted_cmd_accepted && ~response_accepted); + end + end + + // ------------------------------------- + // Pass-through command and response + // ------------------------------------- + always @* begin + cmd_src_channel = stage2_channel; + cmd_src_startofpacket = stage2_startofpacket; + cmd_src_endofpacket = stage2_endofpacket; + cmd_src_data = stage2_data; + + rsp_src_valid = rsp_sink_valid; + rsp_src_data = rsp_sink_data; + rsp_src_channel = rsp_sink_channel; + rsp_src_startofpacket = rsp_sink_startofpacket; + rsp_src_endofpacket = rsp_sink_endofpacket; + rsp_sink_ready = rsp_src_ready; + + // ------------------------------------- + // Forces commands to be non-posted if hazard prevention + // is on, also drops write responses + // ------------------------------------- + if (PREVENT_HAZARDS == 1) begin + cmd_src_data[PKT_TRANS_POSTED] = 1'b0; + + if (rsp_sink_data[PKT_TRANS_WRITE] == 1'b1) begin + rsp_src_valid = 1'b0; + rsp_sink_ready = 1'b1; + end + end + end + + // ------------------------------------- + // Backpressure & Suppression + // ------------------------------------- + generate begin : enforce_order_block + if (ENFORCE_ORDER) begin + assign suppress = nonposted_cmd && has_pending_responses && + (stage2_dest_changed || (PREVENT_HAZARDS == 1 && stage2_trans_changed)); + end else begin + assign suppress = 1'b0; + end + end endgenerate + + always @* begin + stage2_ready = cmd_src_ready; + internal_valid = stage2_valid; + + if (suppress) begin + stage2_ready = 0; + internal_valid = 0; + end + + if (VALID_WIDTH == 1) begin + cmd_src_valid = internal_valid; + end else begin + // ------------------------------------- + // Use the one-hot channel to determine if the destination + // has changed. This results in a wide valid bus + // ------------------------------------- + cmd_src_valid = { VALID_WIDTH {stage2_valid} } & cmd_sink_channel; + if (nonposted_cmd & has_pending_responses) begin + cmd_src_valid = cmd_src_valid & last_channel; + // ------------------------------------- + // Mask the valid signals if the transaction type has changed + // if hazard prevention is enabled + // ------------------------------------- + if (PREVENT_HAZARDS == 1) + cmd_src_valid = cmd_src_valid & { VALID_WIDTH {!stage2_trans_changed} }; + end + end + end + + // -------------------------------------------------- + // Calculates the log2ceil of the input value. + // + // This function occurs a lot... please refactor. + // -------------------------------------------------- + function integer log2ceil; + input integer val; + integer i; + + begin + i = 1; + log2ceil = 0; + + while (i < val) begin + log2ceil = log2ceil + 1; + i = i << 1; + end + end + endfunction + +endmodule + diff --git a/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_width_adapter.sv b/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_width_adapter.sv new file mode 100644 index 00000000..96b731b6 --- /dev/null +++ b/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_width_adapter.sv @@ -0,0 +1,1133 @@ +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/12.1sp1/ip/merlin/altera_merlin_width_adapter/altera_merlin_width_adapter.sv#1 $ +// $Revision: #1 $ +// $Date: 2012/10/10 $ +// $Author: swbranch $ + +// ----------------------------------------------------- +// Merlin Width Adapter +// ----------------------------------------------------- + +`timescale 1 ns / 1 ns + +module altera_merlin_width_adapter +#( + parameter IN_PKT_ADDR_L = 0, + parameter IN_PKT_ADDR_H = 31, + parameter IN_PKT_DATA_L = 32, + parameter IN_PKT_DATA_H = 63, + parameter IN_PKT_BYTEEN_L = 64, + parameter IN_PKT_BYTEEN_H = 67, + parameter IN_PKT_TRANS_COMPRESSED_READ = 72, + parameter IN_PKT_BYTE_CNT_L = 73, + parameter IN_PKT_BYTE_CNT_H = 77, + parameter IN_PKT_BURSTWRAP_L = 78, + parameter IN_PKT_BURSTWRAP_H = 82, + parameter IN_PKT_BURST_SIZE_L = 83, + parameter IN_PKT_BURST_SIZE_H = 85, + parameter IN_PKT_RESPONSE_STATUS_L = 86, + parameter IN_PKT_RESPONSE_STATUS_H = 87, + parameter IN_PKT_TRANS_EXCLUSIVE = 88, + parameter IN_PKT_BURST_TYPE_L = 89, + parameter IN_PKT_BURST_TYPE_H = 90, + parameter IN_ST_DATA_W = 110, + + parameter OUT_PKT_ADDR_L = 0, + parameter OUT_PKT_ADDR_H = 31, + parameter OUT_PKT_DATA_L = 32, + parameter OUT_PKT_DATA_H = 47, + parameter OUT_PKT_BYTEEN_L = 48, + parameter OUT_PKT_BYTEEN_H = 49, + parameter OUT_PKT_TRANS_COMPRESSED_READ = 54, + parameter OUT_PKT_BYTE_CNT_L = 55, + parameter OUT_PKT_BYTE_CNT_H = 59, + parameter OUT_PKT_BURST_SIZE_L = 60, + parameter OUT_PKT_BURST_SIZE_H = 62, + parameter OUT_PKT_RESPONSE_STATUS_L = 63, + parameter OUT_PKT_RESPONSE_STATUS_H = 64, + parameter OUT_PKT_TRANS_EXCLUSIVE = 65, + parameter OUT_PKT_BURST_TYPE_L = 66, + parameter OUT_PKT_BURST_TYPE_H = 67, + parameter OUT_ST_DATA_W = 92, + + parameter ST_CHANNEL_W = 32, + parameter OPTIMIZE_FOR_RSP = 0, + + parameter PACKING = 1, // 1: default packing with avalon slave + parameter CONSTANT_BURST_SIZE = 1, // 1: This is to optimize for Avalon only system as Avalon always send full size transaction + parameter RESPONSE_PATH = 0 // 0: this is WA on command path or avalon system: response always merged, 1: this WA is on response path +) +( + input clk, + input reset, + output reg in_ready, + input in_valid, + input [ST_CHANNEL_W-1:0] in_channel, + input [IN_ST_DATA_W-1:0] in_data, + input in_startofpacket, + input in_endofpacket, + input out_ready, + output reg out_valid, + output reg [ST_CHANNEL_W-1:0] out_channel, + output reg [OUT_ST_DATA_W-1:0] out_data, + output reg out_startofpacket, + output reg out_endofpacket, + + input [2:0] in_command_size_data +); + + // ------------------------------------------------------------ + // Local Parameters + // ------------------------------------------------------------ + localparam IN_NUMSYMBOLS = IN_PKT_BYTEEN_H - IN_PKT_BYTEEN_L + 1; + localparam IN_DATA_W = IN_PKT_DATA_H - IN_PKT_DATA_L + 1; + localparam IN_BYTEEN_W = IN_NUMSYMBOLS; + + localparam OUT_NUMSYMBOLS = OUT_PKT_BYTEEN_H - OUT_PKT_BYTEEN_L + 1; + localparam OUT_DATA_W = OUT_PKT_DATA_H - OUT_PKT_DATA_L + 1; + localparam OUT_BYTEEN_W = OUT_NUMSYMBOLS; + + localparam BURST_TYPE_W = IN_PKT_BURST_TYPE_H - IN_PKT_BURST_TYPE_L + 1; + localparam BURST_SIZE_W = IN_PKT_BURST_SIZE_H - IN_PKT_BURST_SIZE_L + 1; + localparam RESPONSE_STATUS_W = IN_PKT_RESPONSE_STATUS_H - IN_PKT_RESPONSE_STATUS_L + 1; + localparam SYMBOL_W = IN_DATA_W / IN_NUMSYMBOLS; + localparam ADDRESS_W = IN_PKT_ADDR_H - IN_PKT_ADDR_L + 1; + localparam BYTE_CNT_W = IN_PKT_BYTE_CNT_H - IN_PKT_BYTE_CNT_L + 1; + localparam OUT_BYTE_CNT_W = OUT_PKT_BYTE_CNT_H - OUT_PKT_BYTE_CNT_L + 1; + localparam BWRAP_W = IN_PKT_BURSTWRAP_H - IN_PKT_BURSTWRAP_L + 1; + localparam SIZE_W = 2 ** BURST_SIZE_W; + + localparam RATIO = (IN_NUMSYMBOLS > OUT_NUMSYMBOLS ? + IN_NUMSYMBOLS / OUT_NUMSYMBOLS : + OUT_NUMSYMBOLS / IN_NUMSYMBOLS ); + localparam WIDE_NUMSYMBOLS = (IN_NUMSYMBOLS > OUT_NUMSYMBOLS ? + IN_NUMSYMBOLS : OUT_NUMSYMBOLS ); + localparam WIDE_DATA = (IN_NUMSYMBOLS > OUT_NUMSYMBOLS ? + IN_DATA_W - (OUT_NUMSYMBOLS*SYMBOL_W) : + OUT_DATA_W - (IN_NUMSYMBOLS*SYMBOL_W)); + localparam OUT_SEGMENT_W = OUT_NUMSYMBOLS * SYMBOL_W; + + localparam NW_BITFORSELECT_R = clogb2(IN_NUMSYMBOLS); + localparam NW_BITFORSELECT_L = clogb2(OUT_NUMSYMBOLS) - 1; + localparam ALIGNED_BITS_L = clogb2(OUT_NUMSYMBOLS) - 1; + localparam WN_ADDR_LSBS = clogb2(RATIO); + localparam WN_ADDR_SELECT = clogb2(IN_NUMSYMBOLS); + + // ------------------------------------------------------------ + // Utility Functions + // ------------------------------------------------------------ + function integer clogb2; + input [63:0] value; + begin + for (clogb2=0; value>0; clogb2=clogb2+1) + value = value >> 1; + clogb2 = clogb2 - 1; + end + endfunction // clogb2 + + function integer min; + input [31:0] a; + input [31:0] b; + begin + return (a < b) ? a : b; + end + endfunction + + function integer max; + input [31:0] a; + input [31:0] b; + begin + return (a > b) ? a : b; + end + endfunction + + function reg [clogb2(RATIO)-1:0] mask_to_select_correct_segments_for_size; + input [clogb2(RATIO)-1:0] select_output_segment; + input [7:0] size_ratio; + input int msb_select_bit; + + integer i; + mask_to_select_correct_segments_for_size = '1; + for (i=0; i < msb_select_bit; i = i +1'b1 ) begin + if (clogb2(size_ratio) > i) + mask_to_select_correct_segments_for_size[i] = select_output_segment[i]; + end + endfunction + + function reg [ADDRESS_W-1:0] choose_packed_address_base_on_size; + input [7:0] size_ratio; + input int msb_select_bit; + + integer i; + choose_packed_address_base_on_size = '1; + for (i=0; i < msb_select_bit; i = i +1'b1 ) begin + if (clogb2(size_ratio) > i) + choose_packed_address_base_on_size[i + NW_BITFORSELECT_R] = 1'b0; + end + endfunction + + function reg[7:0] bytes_in_transfer; + input [2:0] axsize; + + case (axsize) + 3'b000: bytes_in_transfer = 8'b00000001; + 3'b001: bytes_in_transfer = 8'b00000010; + 3'b010: bytes_in_transfer = 8'b00000100; + 3'b011: bytes_in_transfer = 8'b00001000; + 3'b100: bytes_in_transfer = 8'b00010000; + 3'b101: bytes_in_transfer = 8'b00100000; + 3'b110: bytes_in_transfer = 8'b01000000; + 3'b111: bytes_in_transfer = 8'b10000000; + default:bytes_in_transfer = 8'b00000001; + endcase + + endfunction + + // ------------------------------------------------------------ + // Pseudo-field Parameters + // + // The width adapter widens the data and byteenable fields in the + // output packet, thus changing the output packet format. By using + // pseudo-fields, we can avoid remapping each individual field to + // the output, which is a non-scalable solution. + // + // How? Assume the packet format is { FIRST, byteen, MID, data, LAST }, + // where byteen and data positions are interchangeable. FIRST, MID and + // LAST are pseudo-fields that represent the collection of fields in + // those positions. + // + // Not all the pseudo-fields may exist for a given packet format. A + // non-existent field has reversed indices, so we have to be careful + // when using them. + // ------------------------------------------------------------ + + localparam IN_FIRST_L = 0, + IN_FIRST_H = min(IN_PKT_BYTEEN_L, IN_PKT_DATA_L) - 1, + IN_MID_L = min(IN_PKT_DATA_H, IN_PKT_BYTEEN_H) + 1, + IN_MID_H = max(IN_PKT_DATA_L, IN_PKT_BYTEEN_L) - 1, + IN_LAST_L = max(IN_PKT_BYTEEN_H, IN_PKT_DATA_H) + 1, + IN_LAST_H = IN_ST_DATA_W - 1, + + FIRST_EXISTS = (IN_FIRST_H >= IN_FIRST_L), + MID_EXISTS = (IN_MID_H >= IN_MID_L), + LAST_EXISTS = (IN_LAST_H >= IN_LAST_L), + + FIRST_W = IN_FIRST_H - IN_FIRST_L + 1, + MID_W = IN_MID_H - IN_MID_L + 1, + LAST_W = IN_LAST_H - IN_LAST_L + 1, + + // ------------------------------------------------- + // We cannot split the output map into generate blocks as we + // do for the inputs because address and size are mapped over + // the pseudo-fields. We ensure that the indices are always + // legal, even if the field is unused later on. + + OUT_FIRST_L = 0, + OUT_FIRST_H = FIRST_EXISTS ? + min(OUT_PKT_BYTEEN_L, OUT_PKT_DATA_L) - 1 : + OUT_FIRST_L, + OUT_MID_L = min(OUT_PKT_DATA_H, OUT_PKT_BYTEEN_H) + 1, + OUT_MID_H = MID_EXISTS ? + max(OUT_PKT_DATA_L, OUT_PKT_BYTEEN_L) - 1 : + OUT_MID_L, + OUT_LAST_L = max(OUT_PKT_BYTEEN_H, OUT_PKT_DATA_H) + 1, + OUT_LAST_H = LAST_EXISTS ? + OUT_ST_DATA_W - 1 : + OUT_LAST_L; + + // ------------------------------------------------------------ + // Signals + // ------------------------------------------------------------ + reg [BURST_SIZE_W-1:0] in_size_field; + reg [IN_DATA_W-1:0] in_data_field; + reg [IN_BYTEEN_W-1:0] in_byteen_field; + reg [ADDRESS_W-1:0] in_address_field; + reg [ADDRESS_W-1:0] address_from_packet; + reg [BYTE_CNT_W-1:0] in_byte_cnt_field; + reg [BWRAP_W-1:0] in_burstwrap_field; + reg [RESPONSE_STATUS_W-1:0] in_response_status_field; + reg in_cmpr_read; + reg in_lock_field; + reg [BURST_TYPE_W-1:0] in_burst_type_field; + reg [BYTE_CNT_W-1:0] quantized_byte_cnt_field; + + reg [BURST_SIZE_W-1:0] out_size_field; + reg [OUT_DATA_W-1:0] out_data_field; + reg [OUT_BYTEEN_W-1:0] out_byteen_field; + reg [ADDRESS_W-1:0] out_address_field; + reg out_cmpr_read; + reg [BYTE_CNT_W-1:0] out_byte_cnt_field; + reg out_lock_field; + reg [BURST_TYPE_W-1:0] out_burst_type_field; + reg [RESPONSE_STATUS_W-1:0] out_response_status_field; + + reg [FIRST_W-1:0] in_first_field; + reg [FIRST_W-1:0] out_first_field; + reg [MID_W-1:0] in_mid_field; + reg [MID_W-1:0] out_mid_field; + reg [LAST_W-1:0] in_last_field; + reg [LAST_W-1:0] out_last_field; + + reg [WIDE_DATA-1:0] data_reg; + reg [WIDE_NUMSYMBOLS-1:0] byteen_reg; + reg [ADDRESS_W-1:0] address_reg; + reg [BYTE_CNT_W-1:0] byte_cnt_reg; + reg use_reg; + reg startofpacket_reg; + reg endofpacket_reg; + reg [OUT_SEGMENT_W-1:0] mask; + reg [RESPONSE_STATUS_W-1:0] response_status_reg; + + + reg [ADDRESS_W-1:0] int_output_sel; + reg [clogb2(RATIO)-1:0] output_sel; + reg [OUT_SEGMENT_W-1:0] data_array [0:RATIO-1]; + reg [OUT_NUMSYMBOLS-1:0] byteen_array [0:RATIO-1]; + + // In narrow-to-wide adaptation, each input datum/byteenable bit maps to + // one of OUT_NUMSYMBOLS/IN_NUMSYMBOLS subfields in the wider output + // packet. (Call these subfields "segments".) A subfield of the input + // address, in_bitforselect, selects the segment. Examples: + // 8-16 adaptation: in_bitforselect = in_address_field[0] + // 8-32 adaptation: in_bitforselect = in_address_field[1:0] + // 8-64 adaptation: in_bitforselect = in_address_field[2:0] + // 16-32 adaptation: in_bitforselect = in_address_field[1] + // 32-64 adaptation: in_bitforselect = in_address_field[2] + + // The width of in_bitforselect is + // log2(OUT_NUM_SYMBOLS) - log2(IN_NUM_SYMBOLS) = + // log2(RATIO) + + // The msb of in_bitforselect is driven by + // in_adress_field[log2(OUT_NUMSYMBOLS) - 1] + // The lsb of in_adress_field is driven by + // in_adress_field[log2(IN_NUMSYMBOLS)] + + + reg [clogb2(RATIO)-1:0] in_bitforselect; + integer i, j; + + // ---------------------------------------- + // Input Field Mapping + // ---------------------------------------- + reg [ADDRESS_W-1:0] address_for_adaptation; + always @* begin + in_size_field = in_data[IN_PKT_BURST_SIZE_H :IN_PKT_BURST_SIZE_L ]; + in_data_field = in_data[IN_PKT_DATA_H :IN_PKT_DATA_L ]; + in_byteen_field = in_data[IN_PKT_BYTEEN_H :IN_PKT_BYTEEN_L ]; + address_from_packet = in_data[IN_PKT_ADDR_H :IN_PKT_ADDR_L ]; + //in_address_field = in_data[IN_PKT_ADDR_H :IN_PKT_ADDR_L ]; + in_byte_cnt_field = in_data[IN_PKT_BYTE_CNT_H :IN_PKT_BYTE_CNT_L ]; + in_cmpr_read = in_data[IN_PKT_TRANS_COMPRESSED_READ]; + in_lock_field = in_data[IN_PKT_TRANS_EXCLUSIVE]; + in_burst_type_field = in_data[IN_PKT_BURST_TYPE_H :IN_PKT_BURST_TYPE_L ]; + in_response_status_field = in_data[IN_PKT_RESPONSE_STATUS_H :IN_PKT_RESPONSE_STATUS_L]; + end + // ---------------------------------------- + // Process unaligned address for first address of the burst + // ---------------------------------------- +generate + // ---------------------------------------- + // Do generate here, in case AVALON system then just bypass this + // as the address will be aligned + // ---------------------------------------- +if ((!CONSTANT_BURST_SIZE) & (IN_NUMSYMBOLS > OUT_NUMSYMBOLS)) begin // this needs for Wide-Narrow + reg [ADDRESS_W + (BWRAP_W-1) + 4:0] address_for_alignment; + reg [ADDRESS_W + clogb2(IN_NUMSYMBOLS)-1:0] address_after_aligned; + + assign address_for_alignment = {address_from_packet, in_size_field}; + assign address_for_adaptation = address_after_aligned[ADDRESS_W-1:0]; + + altera_merlin_address_alignment + #( + .ADDR_W (ADDRESS_W), + .BURSTWRAP_W (BWRAP_W), + .INCREMENT_ADDRESS (0), + .NUMSYMBOLS (IN_NUMSYMBOLS) + ) check_and_align_address_to_size + ( + .clk(clk), + .reset(reset), + .in_data(address_for_alignment), + .out_data(address_after_aligned), + .in_valid(), + .in_sop(), + .in_eop(), + .out_ready() + ); +end else begin // Narrow-Wide: it process base on address, so we dont need do alignment + assign address_for_adaptation = address_from_packet; +end +endgenerate + generate begin + if (FIRST_EXISTS) begin + always @* begin + in_first_field = in_data[IN_FIRST_H:IN_FIRST_L]; + end + end else begin + always @* begin + in_first_field = '0; + end + end + if (MID_EXISTS) begin + always @* begin + in_mid_field = in_data[IN_MID_H:IN_MID_L]; + end + end else begin + always @* begin + in_mid_field = '0; + end + end + if (LAST_EXISTS) begin + always @* begin + in_last_field = in_data[IN_LAST_H:IN_LAST_L]; + end + end + end + endgenerate + + generate + + //------------------------------------------------------- + //------------------------------------------------------- + // Wide-to-Narrow + // + // For every input cycle, we drive out a bunch'o'output + // cycles. Nothing fancier. Yes, it could be more + // optimal, but we'll leave that for another day. + //------------------------------------------------------- + //------------------------------------------------------- + if (IN_NUMSYMBOLS > OUT_NUMSYMBOLS) begin + //wire [SIZE_W-1:0] cmd_burst_size; + //assign cmd_burst_size = bytes_in_transfer(in_size_field); + // For Avalon system, it is always fullsize + wire [31:0] cmd_burst_size = CONSTANT_BURST_SIZE ? IN_NUMSYMBOLS : bytes_in_transfer(in_size_field); + + // Below mess is just to avoid Quartus warnings about mis-sized assignments. + wire [31:0] int_out_numsymbols = OUT_NUMSYMBOLS; + wire [clogb2(OUT_NUMSYMBOLS):0] sized_out_numsymbols = int_out_numsymbols[clogb2(OUT_NUMSYMBOLS):0]; + wire [31:0] int_out_size = (cmd_burst_size < OUT_NUMSYMBOLS) ? cmd_burst_size : OUT_NUMSYMBOLS; + wire [SIZE_W-1:0] sized_out_size = int_out_size[SIZE_W-1:0]; + wire [31:0] int_ratio_minus_1 = (cmd_burst_size/OUT_NUMSYMBOLS) - 1; + wire [clogb2(RATIO)-1:0] sized_ratio_minus_1 = int_ratio_minus_1[clogb2(RATIO)-1:0]; + wire [31:0] int_log2_out_numsymbols = clogb2(OUT_NUMSYMBOLS); + wire [BURST_SIZE_W-1:0] log2_out_numsymbols = int_log2_out_numsymbols[BURST_SIZE_W-1:0]; + wire [31:0] int_byte_cnt_factor = (in_size_field < log2_out_numsymbols) ? log2_out_numsymbols : in_size_field; + wire [BURST_SIZE_W-1:0] sized_byte_cnt_factor = int_byte_cnt_factor[BURST_SIZE_W-1:0]; + + reg [clogb2(RATIO)-1:0] count; + + always @(posedge clk, posedge reset) begin + if (reset) begin + address_reg <= '0; + byte_cnt_reg <= '0; + count <= '0; + use_reg <= '0; + endofpacket_reg <= '0; + data_reg <= '0; + byteen_reg <= '0; + end else begin + // If we're not working on a wide datum, + // then wait until one arrives. + if (~use_reg) begin + + if (CONSTANT_BURST_SIZE) begin // indicate when the system contains ONLY Avalon masters and slave + address_reg[ADDRESS_W -1 : WN_ADDR_SELECT] <= in_address_field[ADDRESS_W -1 : WN_ADDR_SELECT]; + address_reg[WN_ADDR_SELECT - 1 : 0] <= sized_out_numsymbols; + data_reg <= in_data_field[IN_DATA_W-1:OUT_NUMSYMBOLS*SYMBOL_W]; + byteen_reg <= in_byteen_field >> OUT_NUMSYMBOLS; + byte_cnt_reg <= in_byte_cnt_field - sized_out_numsymbols; + end else begin + address_reg <= in_address_field + sized_out_size; + byte_cnt_reg <= (in_byte_cnt_field >> clogb2(IN_NUMSYMBOLS) << sized_byte_cnt_factor) - sized_out_numsymbols; + end + + endofpacket_reg <= in_endofpacket; + + if (in_valid && out_ready && !in_cmpr_read && (cmd_burst_size > OUT_NUMSYMBOLS)) begin + // Data has arrived! + count <= sized_ratio_minus_1; + use_reg <= 1'b1; + end + + end else begin // if (count == 0) + // We have a wide datum in progress. Just wait until + // the previous datum is taken, and then set + // up the next transfer. + if (out_ready) begin + if (CONSTANT_BURST_SIZE) begin + address_reg[ADDRESS_W -1 : WN_ADDR_SELECT] <= in_address_field[ADDRESS_W -1 : WN_ADDR_SELECT]; + address_reg[WN_ADDR_SELECT - 1 : 0] <= address_reg[WN_ADDR_SELECT - 1 : 0] + sized_out_numsymbols; + data_reg <= data_reg >> (OUT_NUMSYMBOLS * SYMBOL_W); + byteen_reg <= byteen_reg >> (OUT_NUMSYMBOLS); + end else begin + address_reg <= address_reg + sized_out_size; + end + byte_cnt_reg <= byte_cnt_reg - sized_out_numsymbols; + count <= count - 1'b1; + if (count == 1'b1) + // We're at the end of this word. + use_reg <= '0; + + end // if (out_ready) + end // else: !if(count == 0) + end // if (posedge clk) + end // always @ (clk, reset) + + + always @* begin + // Calculate in_ready. + // If count is 0, then we don't have data underway, and we + // definitely won't be ready for it the first time 'round. + // If count is '1', then we're finishing a set, and we're + // ready if the output is. + // If count > 1, then we're mid set, and certainly + // not ready. + in_ready = 0; + if ( (cmd_burst_size <= OUT_NUMSYMBOLS) || count == 1 || in_cmpr_read ) + in_ready = out_ready; + + out_valid = in_valid; + out_channel = in_channel; + out_startofpacket = in_startofpacket; + out_endofpacket = 0; + + out_size_field = (cmd_burst_size < OUT_NUMSYMBOLS) ? in_size_field : log2_out_numsymbols; + if (CONSTANT_BURST_SIZE) begin // For Avalon ONlY + out_byteen_field = in_byteen_field[OUT_NUMSYMBOLS-1:0]; + out_data_field = in_data_field[OUT_NUMSYMBOLS * SYMBOL_W-1:0]; + out_byte_cnt_field = in_byte_cnt_field; + end else begin + out_byte_cnt_field = in_byte_cnt_field >> clogb2(IN_NUMSYMBOLS) << sized_byte_cnt_factor; + end + + out_first_field = in_first_field; + out_mid_field = in_mid_field; + out_last_field = in_last_field; + out_cmpr_read = in_cmpr_read; + out_lock_field = in_lock_field; + out_burst_type_field = in_burst_type_field; + out_response_status_field = in_response_status_field; + // Case when command size <= OUT_NUMSYMBOL: burst untouched and when unalgined, use address from packet + // and send this "unligned" address (if happens) to the network + if (cmd_burst_size <= OUT_NUMSYMBOLS) begin + out_endofpacket = in_endofpacket; + in_address_field = address_from_packet; + end //(cmd_burst_size <= OUT_NUMSYMBOLS) + else begin + // Case when WA need to split data, first address of the burst, the WA need align and send this align address + // to the network. + out_lock_field = 0; + // Change burst type 'FIXED' to 'Reserved' + if (in_burst_type_field == 2'b00) begin + out_burst_type_field = 2'b11; + end + in_address_field = address_for_adaptation; + end // (cmd_burst_size > OUT_NUMSYMBOLS) + + out_address_field = in_address_field; + int_output_sel = in_address_field >> log2_out_numsymbols ; + if ( in_cmpr_read ) + out_endofpacket = 1; + + if (use_reg) begin + + out_startofpacket = 0; + // If it's the Last cycle, or if there's no more data, + // we can allow an endofpacket. + + if ((count==1)) + out_endofpacket = endofpacket_reg; + + out_byte_cnt_field = byte_cnt_reg; + out_address_field = address_reg; + if (CONSTANT_BURST_SIZE) begin // Avalon system + out_data_field = data_reg[(OUT_NUMSYMBOLS * SYMBOL_W)-1:0]; + out_byteen_field = byteen_reg[OUT_NUMSYMBOLS-1:0]; + // Avoid QIS warning: used but not assgin + byteen_array = '{RATIO {0} }; + data_array = '{RATIO {0} }; + end + int_output_sel = address_reg >> log2_out_numsymbols; + end + + output_sel = int_output_sel[WN_ADDR_LSBS-1:0]; + if (!CONSTANT_BURST_SIZE) begin + out_byteen_field = byteen_array[output_sel]; + out_data_field = data_array[output_sel]; + end + + //----------------------------------------- + // Optimization for non-bursting wide-narrow response. + // + // Only one segment of the wide word will have asserted + // byteenables. Just pass that segment through and drop + // the rest. This should synthesize to an and-or mux. + //----------------------------------------- + if (OPTIMIZE_FOR_RSP) begin + out_startofpacket = in_startofpacket; + out_endofpacket = in_endofpacket; + in_ready = out_ready; + //----------------------------------------- + // Not correct, but nothing in the response path looks + // at these today (10.1). Must be corrected when we allow + // multiple width adapters on a path. + //----------------------------------------- + out_address_field = in_address_field; + out_byte_cnt_field = in_byte_cnt_field; + + out_data_field = '0; + out_byteen_field = '0; + for (i = 0; i < RATIO; i=i+1) begin + mask = '0; + for (j = 0; j < OUT_NUMSYMBOLS; j=j+1) begin + mask |= {SYMBOL_W{in_byteen_field[i*OUT_NUMSYMBOLS+j]}} << (j*SYMBOL_W); + end + + out_data_field |= mask & in_data_field[i*OUT_SEGMENT_W +: OUT_SEGMENT_W]; + out_byteen_field |= in_byteen_field[i*OUT_NUMSYMBOLS +: OUT_NUMSYMBOLS]; + end + end + + end // always @ * + + //------------------------------------------------------- + // Configuration Error Checking + //------------------------------------------------------- + // synthesis translate_off + initial begin + if (RATIO * OUT_NUMSYMBOLS != IN_NUMSYMBOLS) begin + $display("%m : The ratio of input symbols to output symbols must be an integer."); + $stop(); + end + end + // synthesis translate_on + if (!CONSTANT_BURST_SIZE) begin + integer ibyte; + always @* begin + for(ibyte=0; ibyte OUT_NUMSYMBOLS) + + //------------------------------------------------------- + //------------------------------------------------------- + // Narrow-to-Wide + //------------------------------------------------------- + //------------------------------------------------------- + if (OUT_NUMSYMBOLS > IN_NUMSYMBOLS) begin + wire p0_valid; + reg p0_startofpacket; + reg p0_endofpacket; + reg [IN_DATA_W-1:0] p0_data_field; + reg [IN_BYTEEN_W-1:0] p0_byteen_field; + reg [ADDRESS_W-1:0] p0_address_field; + reg [BWRAP_W-1:0] p0_bwrap_field; + reg [BYTE_CNT_W-1:0] p0_byte_cnt_field; + reg [clogb2(RATIO)-1:0] p0_bitforselect; + reg p0_cmpr_read; + reg [FIRST_W-1:0] p0_first_field; + reg [MID_W-1:0] p0_mid_field; + reg [LAST_W-1:0] p0_last_field; + reg p0_use_reg; + reg [ST_CHANNEL_W-1:0] p0_channel; + reg [BURST_SIZE_W-1:0] p0_burst_size; + reg p0_out_lock_field; + reg [BURST_TYPE_W-1:0] p0_burst_type_field; + + reg [RESPONSE_STATUS_W-1:0] p0_response_status_field; + reg p0_reg_startofpacket; + reg p0_reg_endofpacket; + reg [IN_DATA_W-1:0] p0_reg_data_field; + reg [IN_BYTEEN_W-1:0] p0_reg_byteen_field; + reg [ADDRESS_W-1:0] p0_reg_address_field; + reg [BWRAP_W-1:0] p0_reg_bwrap_field; + reg [BYTE_CNT_W-1:0] p0_reg_byte_cnt_field; + reg [clogb2(RATIO)-1:0] p0_reg_bitforselect; + reg p0_reg_cmpr_read; + reg [FIRST_W-1:0] p0_reg_first_field; + reg [MID_W-1:0] p0_reg_mid_field; + reg [LAST_W-1:0] p0_reg_last_field; + reg [ST_CHANNEL_W-1:0] p0_reg_channel; + reg [BURST_SIZE_W-1:0] p0_reg_burst_size; + reg [BURST_TYPE_W-1:0] p0_reg_burst_type_field; + reg [RESPONSE_STATUS_W-1:0] p0_reg_response_status_field; + reg p0_reg_out_lock_field; + wire p1_valid; + reg p1_ready; + reg p1_startofpacket; + reg p1_endofpacket; + reg [IN_DATA_W-1:0] p1_data_field; + reg [IN_BYTEEN_W-1:0] p1_byteen_field; + reg [ADDRESS_W-1:0] p1_address_field; + reg [ADDRESS_W-1:0] out_address_field_mask; + reg [BYTE_CNT_W-1:0] p1_byte_cnt_field; + + reg [BURST_SIZE_W-1:0] p1_burst_size; + reg [BYTE_CNT_W-1:0] p1_byte_cnt_unpack_field; + wire response_data_packing; + reg [clogb2(RATIO)-1:0] p1_shift_correct_ouput_segments; + reg [clogb2(RATIO)-1:0] p1_push_data_to_output; + + reg p1_cmpr_read; + reg [RESPONSE_STATUS_W-1:0] p1_response_status_field; + reg unc_sink_valid; + wire unc_sink_ready; + wire unc_src_startofpacket; + wire unc_src_endofpacket; + wire unc_src_valid; + wire [ADDRESS_W-1:0] unc_src_addr; + wire [BYTE_CNT_W-1:0] unc_src_byte_cnt; + + wire aligned_addr; + wire aligned_byte_cnt; + wire unaligned_read; + + reg [BYTE_CNT_W-1:0] count; + reg count_eq_zero; + + wire [31:0] int_in_numsymbols = IN_NUMSYMBOLS; + wire [BYTE_CNT_W-1:0] byte_cnt_sized_in_num_symbols = + int_in_numsymbols[BYTE_CNT_W-1:0]; + reg [7:0] cmd_burst_size; + reg [31:0] out_numsymbols_wire = clogb2(OUT_NUMSYMBOLS); + wire [31:0] int_encoded_burstsize = NW_BITFORSELECT_R; //NW_BITFORSELECT_R is the log2 of IN_NUMSYMBOLS + wire [BURST_SIZE_W-1:0] encoded_burstsize = int_encoded_burstsize[BURST_SIZE_W-1:0]; + + // Care about burstwrap on command path only + if (RESPONSE_PATH == 0) begin + assign in_burstwrap_field = in_data[IN_PKT_BURSTWRAP_H:IN_PKT_BURSTWRAP_L]; + end + + reg [7:0] size_ratio; + // -------------------------------------------- + // Stage 0: buffer the input cycle if read burst + // uncompression is going to happen. + // + // This avoids the possibility of a master receiving a premature + // response while its read burst is still being waitrequested. + // -------------------------------------------- + always @(posedge clk, posedge reset) begin + if (reset) begin + p0_use_reg <= 1'b0; + p0_reg_startofpacket <= 1'b0; + p0_reg_endofpacket <= 1'b0; + p0_reg_data_field <= '0; + p0_reg_bwrap_field <= '0; + p0_reg_byteen_field <= '0; + p0_reg_address_field <= '0; + p0_reg_byte_cnt_field <= '0; + p0_reg_cmpr_read <= 1'b0; + p0_reg_first_field <= '0; + p0_reg_mid_field <= '0; + p0_reg_last_field <= '0; + p0_reg_channel <= '0; + p0_reg_burst_size <= '0; + p0_reg_out_lock_field <= '0; + p0_reg_burst_type_field <= '0; + p0_reg_response_status_field <= '0; + end else begin + if (unaligned_read & in_valid) + p0_use_reg <= 1'b1; + if (unc_src_endofpacket & p1_ready) + p0_use_reg <= 1'b0; + + if (unaligned_read) begin + p0_reg_startofpacket <= p0_startofpacket; + p0_reg_endofpacket <= p0_endofpacket; + p0_reg_data_field <= p0_data_field; + p0_reg_bwrap_field <= p0_bwrap_field; + p0_reg_byteen_field <= p0_byteen_field; + p0_reg_address_field <= p0_address_field; + p0_reg_byte_cnt_field <= p0_byte_cnt_field; + p0_reg_cmpr_read <= p0_cmpr_read; + p0_reg_first_field <= p0_first_field; + p0_reg_mid_field <= p0_mid_field; + p0_reg_last_field <= p0_last_field; + p0_reg_channel <= p0_channel; + p0_reg_burst_size <= p0_burst_size; + p0_reg_out_lock_field <= p0_out_lock_field; + p0_reg_burst_type_field <= p0_burst_type_field; + p0_reg_response_status_field <= p0_response_status_field; + end + end + end + + always @* begin + in_ready = p1_ready; + + // accept on the first cycle + if (unaligned_read & in_valid & ~p0_use_reg) + in_ready = 1; + + if (p0_use_reg) + in_ready = 0; + end + + always @* begin + p0_startofpacket = in_startofpacket; + p0_endofpacket = in_endofpacket; + p0_data_field = in_data_field; + p0_bwrap_field = in_burstwrap_field; + p0_byteen_field = in_byteen_field; + //p0_address_field = in_address_field; + p0_address_field = address_for_adaptation; // read address from oacket + + p0_byte_cnt_field = in_byte_cnt_field; + p0_cmpr_read = in_cmpr_read; + p0_first_field = in_first_field; + p0_mid_field = in_mid_field; + p0_last_field = in_last_field; + p0_channel = in_channel; + p0_burst_size = in_size_field; + p0_out_lock_field = in_lock_field; + p0_burst_type_field = in_burst_type_field; + p0_response_status_field = in_response_status_field; + if (p0_use_reg) begin + p0_startofpacket = p0_reg_startofpacket; + p0_endofpacket = p0_reg_endofpacket; + p0_data_field = p0_reg_data_field; + p0_bwrap_field = p0_reg_bwrap_field; + p0_byteen_field = p0_reg_byteen_field; + p0_address_field = p0_reg_address_field; + p0_byte_cnt_field = p0_reg_byte_cnt_field; + p0_cmpr_read = p0_reg_cmpr_read; + p0_first_field = p0_reg_first_field; + p0_mid_field = p0_reg_mid_field; + p0_last_field = p0_reg_last_field; + p0_channel = p0_reg_channel; + p0_burst_size = p0_reg_burst_size; + p0_out_lock_field = p0_reg_out_lock_field; + p0_burst_type_field = p0_reg_burst_type_field; + p0_response_status_field = p0_reg_response_status_field; + end + end + + assign p0_valid = in_valid | p0_use_reg; + + // -------------------------------------------- + // Stage 1: uncompress the input packet if necessary + // -------------------------------------------- + assign p1_valid = (unaligned_read) ? unc_src_valid : p0_valid; + assign aligned_addr = (p0_address_field[ALIGNED_BITS_L:0] == 0); + assign aligned_byte_cnt = (p0_byte_cnt_field[ALIGNED_BITS_L:0] == 0); + if ((RESPONSE_PATH == 0) && (PACKING == 1)) begin // if this is avalon then checking on aligned, + assign unaligned_read = p0_cmpr_read & (~aligned_addr || ~aligned_byte_cnt); + end else begin + assign unaligned_read = '0; + end + + always @* begin + p1_data_field = p0_data_field; + p1_byteen_field = p0_byteen_field; + p1_startofpacket = p0_startofpacket; + p1_endofpacket = p0_endofpacket; + p1_address_field = p0_address_field; + p1_byte_cnt_field = p0_byte_cnt_field; + p1_cmpr_read = p0_cmpr_read; + p1_response_status_field = p0_response_status_field; + p1_burst_size = p0_burst_size; + unc_sink_valid = 0; + + if (unaligned_read) begin + unc_sink_valid = p0_valid; + + p1_startofpacket = unc_src_startofpacket; + p1_endofpacket = unc_src_endofpacket; + p1_address_field = unc_src_addr; + p1_byte_cnt_field = unc_src_byte_cnt; + p1_cmpr_read = 0; + end + end + + altera_merlin_burst_uncompressor + #( + .ADDR_W (ADDRESS_W), + .BURSTWRAP_W (BWRAP_W), + .BYTE_CNT_W (BYTE_CNT_W), + .PKT_SYMBOLS (IN_NUMSYMBOLS) + ) uncompressor ( + .clk (clk), + .reset (reset), + + .sink_startofpacket (p0_startofpacket), + .sink_endofpacket (p0_endofpacket), + .sink_valid (unc_sink_valid), + .sink_ready (unc_sink_ready), + .sink_addr (p0_address_field), + .sink_burstwrap (p0_bwrap_field), + .sink_byte_cnt (p0_byte_cnt_field), + .sink_is_compressed (1'b1), // should always be compressed + .sink_burstsize (encoded_burstsize), + + .source_startofpacket (unc_src_startofpacket), + .source_endofpacket (unc_src_endofpacket), + .source_valid (unc_src_valid), + .source_ready (p1_ready), + .source_addr (unc_src_addr), + .source_burstwrap (), + .source_byte_cnt (unc_src_byte_cnt), + .source_is_compressed (), + .source_burstsize () + ); + + // -------------------------------------------- + // Stage 2: perform narrow to wide adaptation on the beats + // -------------------------------------------- + + always @(posedge clk, posedge reset) begin + if (reset) begin + data_reg <= '0; + byteen_reg <= '0; + startofpacket_reg <= '0; + count <= '0; + count_eq_zero <= '1; + response_status_reg <= '0; + end else begin + + if (p1_valid && (out_ready || ~out_valid)) begin + // Lay input data & input byte enables into + // the temp registers + data_reg <= data_reg | (p1_data_field << (p1_shift_correct_ouput_segments *IN_NUMSYMBOLS*SYMBOL_W)); + byteen_reg <= byteen_reg | (p1_byteen_field << (p1_shift_correct_ouput_segments *IN_NUMSYMBOLS)); + response_status_reg <= out_response_status_field; + // Capture the stuff that's to be held constant + if (count_eq_zero) begin + startofpacket_reg <= p1_startofpacket; + if (~p1_endofpacket) begin + count <= p1_byte_cnt_field - byte_cnt_sized_in_num_symbols; + count_eq_zero <= + ~|(p1_byte_cnt_field - byte_cnt_sized_in_num_symbols); + end + end else begin + count <= count - byte_cnt_sized_in_num_symbols; + count_eq_zero <= ~|(count - byte_cnt_sized_in_num_symbols); + end + + //if (p1_endofpacket || (p1_shift_correct_ouput_segments == '1)) begin + if (p1_endofpacket || (p1_push_data_to_output == '1)) begin + data_reg <= '0; + byteen_reg <= '0; + response_status_reg <= '0; + end + + if (out_valid && out_ready) begin + startofpacket_reg <= '0; + end + + end // if (p1_valid && (out_ready || ~out_valid)) + end // if (posedge clk) + end // always @ (clk, reset) + + always @* begin + // Handle narrow-size transaction from the master: + // The width of in_bitforselect is + // log2(OUT_NUM_SYMBOLS) - log2(IN_NUM_SYMBOLS) = + // log2(RATIO) + // The msb of in_bitforselect is driven by: in_adress_field[log2(OUT_NUMSYMBOLS) - 1] + // The lsb of in_adress_field is driven by: in_adress_field[log2(IN_NUMSYMBOLS)] + + // The function: mask_to_select_segments_for_size: is used to build a mask that changed at run-time + // when narrow-size transaction, It recaculates the width of in_bitforselect base on size ratio + + // EX: Full-size transaction (2 bytes)N-W: in_bitforselect = in_address[1:0] + // Narrow-size transaction(1 byte)N-W: in_bitforselect = {1, in_address[0]} + + p1_shift_correct_ouput_segments = p1_address_field[NW_BITFORSELECT_L:NW_BITFORSELECT_R]; + + // size ratio betwen command size and response size + cmd_burst_size = bytes_in_transfer(in_command_size_data); + size_ratio = cmd_burst_size >> in_size_field; + + if (RESPONSE_PATH == 0) begin + // if the WA is on command path, Avalon interconnect default + // bitselectfor data packing and push out data are same, compile time + p1_push_data_to_output = p1_shift_correct_ouput_segments; + end else begin + // the WA is on reponse path and default: PACKING = 1 + // on response path, need based on size, run-time, to determinite output segment + p1_push_data_to_output = mask_to_select_correct_segments_for_size(p1_shift_correct_ouput_segments, size_ratio, clogb2(RATIO)); + out_address_field_mask = choose_packed_address_base_on_size(size_ratio, clogb2(RATIO)); + end + + // We push data to the output whenever the input is + // an endofpacket, or the input drives the most-significant + // segment of the wider output word. + out_valid = 0; + if (PACKING == 1) begin + if (p1_endofpacket || (p1_push_data_to_output == '1)) begin + out_valid = p1_valid; + end + end else begin + out_valid = p1_valid; + end + + out_startofpacket = p1_startofpacket || startofpacket_reg; + out_endofpacket = p1_endofpacket; + + // Compressed read with byte_cnt > input interface width: + // this is a read burst spanning more than the originating + // interface of data, so all byteenables must be asserted. + if (p1_cmpr_read && (p1_byte_cnt_field > IN_NUMSYMBOLS)) begin + out_byteen_field = '1; + end else begin + if (PACKING == 1) begin // byteenable only affect on command path + out_byteen_field = byteen_reg | + (p1_byteen_field << (p1_shift_correct_ouput_segments*IN_NUMSYMBOLS)); + end else begin // non-packing: shift input byteenable to correct position + out_byteen_field = (p1_byteen_field << (p1_shift_correct_ouput_segments*IN_NUMSYMBOLS)); + end + end + + // caculate bytecnt "unpack" according to OUTNUMSYMBOLS + p1_byte_cnt_unpack_field = p1_byte_cnt_field << clogb2(RATIO); + out_address_field = p1_address_field; + + if (RESPONSE_PATH == 0) begin + if (PACKING == 1) begin // if the WA is on command path, Avalon interconnect default + out_data_field = data_reg | (p1_data_field << (p1_shift_correct_ouput_segments *IN_NUMSYMBOLS*SYMBOL_W)); + out_byte_cnt_field = quantized_byte_cnt_field; + out_address_field[NW_BITFORSELECT_L:0] = 0; + out_size_field = out_numsymbols_wire[BURST_SIZE_W-1:0]; // for Avalon the size is converted to slave side + end else begin + out_data_field = (p1_data_field << (p1_shift_correct_ouput_segments *IN_NUMSYMBOLS*SYMBOL_W)); + out_byte_cnt_field = p1_byte_cnt_unpack_field; + out_size_field = p1_burst_size; + end + out_response_status_field = p1_response_status_field; + end else begin // the WA is on reponse path and default: PACKING = 1 + if (in_size_field < in_command_size_data) begin // downsize happen on command path, the response need packing + out_data_field = data_reg + | (p1_data_field << (p1_shift_correct_ouput_segments *IN_NUMSYMBOLS*SYMBOL_W)); + out_address_field = p1_address_field & out_address_field_mask; + out_size_field = p1_burst_size; + out_byte_cnt_field = p1_byte_cnt_field; + + // Response merging: rules: DECERR(11) > SLVERR (10) > OKAY (00) + // EXOKAY will not happen on merging + out_response_status_field = '0; + if (response_status_reg >= p1_response_status_field) begin + out_response_status_field = response_status_reg; + end else begin + out_response_status_field = p1_response_status_field; + end + + end else begin // narrow transaction on command path, reponse packet will not packed + out_data_field = (p1_data_field << (p1_shift_correct_ouput_segments *IN_NUMSYMBOLS*SYMBOL_W)); + out_byte_cnt_field = p1_byte_cnt_field; + out_size_field = p1_burst_size; + out_response_status_field = p1_response_status_field; + end + end + out_cmpr_read = p1_cmpr_read; + + // nothing touches these fields, so assign them + // directly from the input fields + out_first_field = p0_first_field; + out_mid_field = p0_mid_field; + out_last_field = p0_last_field; + out_lock_field = p0_out_lock_field; + out_channel = p0_channel; + out_burst_type_field = p0_burst_type_field; + end // always @ * + + //------------------------------------------------------- + // output byte_cnt, rounded up to alignment with the output-side + // address map footprint implied by the input-side access. + // + // See "option 3" in Appendix C of + // merlin_interconnect_architecture_fd_91.doc. + //------------------------------------------------------- + reg [NW_BITFORSELECT_L:0] low_addr_bits; + + always @* begin + low_addr_bits = p1_address_field[NW_BITFORSELECT_L:0]; + + quantized_byte_cnt_field = low_addr_bits + + p1_byte_cnt_field + + {clogb2(OUT_NUMSYMBOLS){1'b1}}; + quantized_byte_cnt_field[NW_BITFORSELECT_L:0] = '0; + end + + //------------------------------------------------------- + // Backpressure + //------------------------------------------------------- + always @ * begin + p1_ready = out_ready || ~out_valid; + end + + end // if (OUT_NUMSYMBOLS > IN_NUMSYMBOLS) + + //------------------------------------------------------- + //------------------------------------------------------- + // Same Width. Seems kind of silly, but let's be complete. + //------------------------------------------------------- + //------------------------------------------------------- + if (OUT_NUMSYMBOLS == IN_NUMSYMBOLS) begin + + always @* begin + in_ready = out_ready; + out_valid = in_valid; + out_channel = in_channel; + out_startofpacket = in_startofpacket; + out_endofpacket = in_endofpacket; + out_size_field = in_size_field; + out_data_field = in_data_field; + out_byteen_field = in_byteen_field; + out_address_field = in_address_field; + out_byte_cnt_field = in_byte_cnt_field; + out_response_status_field = in_response_status_field; + out_lock_field = in_lock_field; + out_burst_type_field = in_burst_type_field; + out_cmpr_read = in_cmpr_read; + out_first_field = in_first_field; + out_mid_field = in_mid_field; + out_last_field = in_last_field; + end // always @ * + + end // if (OUT_NUMSYMBOLS == IN_NUMSYMBOLS) + + endgenerate + + // --------------------------------------- + // Output Field Mapping + // + // Conditionally assign the pseudo-fields. Assign address and size + // last, because they partly override the pseudo-fields. + // --------------------------------------- + always @* begin + if (FIRST_EXISTS) + out_data[OUT_FIRST_H:OUT_FIRST_L] = out_first_field; + if (MID_EXISTS) + out_data[OUT_MID_H:OUT_MID_L] = out_mid_field; + if (LAST_EXISTS) + out_data[OUT_LAST_H:OUT_LAST_L] = out_last_field; + + out_data[OUT_PKT_BURST_SIZE_H : OUT_PKT_BURST_SIZE_L ] = out_size_field; + out_data[OUT_PKT_DATA_H : OUT_PKT_DATA_L ] = out_data_field; + out_data[OUT_PKT_BYTEEN_H : OUT_PKT_BYTEEN_L ] = out_byteen_field; + out_data[OUT_PKT_ADDR_H : OUT_PKT_ADDR_L ] = out_address_field; + out_data[OUT_PKT_BYTE_CNT_H : OUT_PKT_BYTE_CNT_L ] = out_byte_cnt_field; + out_data[OUT_PKT_TRANS_COMPRESSED_READ ] = out_cmpr_read; + out_data[OUT_PKT_TRANS_EXCLUSIVE ] = out_lock_field; + out_data[OUT_PKT_BURST_TYPE_H : OUT_PKT_BURST_TYPE_L ] = out_burst_type_field; + out_data[OUT_PKT_RESPONSE_STATUS_H : OUT_PKT_RESPONSE_STATUS_L] = out_response_status_field; + end // always @ * + +endmodule // width_adapter + diff --git a/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_reset_controller.sdc b/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_reset_controller.sdc new file mode 100644 index 00000000..28476afa --- /dev/null +++ b/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_reset_controller.sdc @@ -0,0 +1,33 @@ +# (C) 2001-2013 Altera Corporation. All rights reserved. +# Your use of Altera Corporation's design tools, logic functions and other +# software and tools, and its AMPP partner logic functions, and any output +# files any of the foregoing (including device programming or simulation +# files), and any associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License Subscription +# Agreement, Altera MegaCore Function License Agreement, or other applicable +# license agreement, including, without limitation, that your use is for the +# sole purpose of programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the applicable +# agreement for further details. + + +# +--------------------------------------------------- +# | Cut the async clear paths +# +--------------------------------------------------- +set aclr_counter 0 +set clrn_counter 0 +set aclr_collection [get_pins -compatibility_mode -nocase -nowarn *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|aclr] +set clrn_collection [get_pins -compatibility_mode -nocase -nowarn *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn] +foreach_in_collection aclr_pin $aclr_collection { + set aclr_counter [expr $aclr_counter + 1] +} +foreach_in_collection clrn_pin $clrn_collection { + set clrn_counter [expr $clrn_counter + 1] +} +if {$aclr_counter > 0} { + set_false_path -to [get_pins -compatibility_mode -nocase *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|aclr] +} + +if {$clrn_counter > 0} { + set_false_path -to [get_pins -compatibility_mode -nocase *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn] +} diff --git a/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_reset_controller.v b/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_reset_controller.v new file mode 100644 index 00000000..dacdc376 --- /dev/null +++ b/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_reset_controller.v @@ -0,0 +1,110 @@ +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/12.1sp1/ip/merlin/altera_reset_controller/altera_reset_controller.v#1 $ +// $Revision: #1 $ +// $Date: 2012/10/10 $ +// $Author: swbranch $ + +// -------------------------------------- +// Reset controller +// +// Combines all the input resets and synchronizes +// the result to the clk. +// -------------------------------------- + +`timescale 1 ns / 1 ns + +module altera_reset_controller +#( + parameter NUM_RESET_INPUTS = 6, + parameter OUTPUT_RESET_SYNC_EDGES = "deassert", + parameter SYNC_DEPTH = 2 +) +( + // -------------------------------------- + // We support up to 16 reset inputs, for now + // -------------------------------------- + input reset_in0, + input reset_in1, + input reset_in2, + input reset_in3, + input reset_in4, + input reset_in5, + input reset_in6, + input reset_in7, + input reset_in8, + input reset_in9, + input reset_in10, + input reset_in11, + input reset_in12, + input reset_in13, + input reset_in14, + input reset_in15, + + input clk, + output reset_out +); + + localparam ASYNC_RESET = (OUTPUT_RESET_SYNC_EDGES == "deassert"); + + wire merged_reset; + + // -------------------------------------- + // "Or" all the input resets together + // -------------------------------------- + assign merged_reset = ( + reset_in0 | + reset_in1 | + reset_in2 | + reset_in3 | + reset_in4 | + reset_in5 | + reset_in6 | + reset_in7 | + reset_in8 | + reset_in9 | + reset_in10 | + reset_in11 | + reset_in12 | + reset_in13 | + reset_in14 | + reset_in15 + ); + + // -------------------------------------- + // And if required, synchronize it to the required clock domain, + // with the correct synchronization type + // -------------------------------------- + generate if (OUTPUT_RESET_SYNC_EDGES == "none") begin + + assign reset_out = merged_reset; + + end else begin + + altera_reset_synchronizer + #( + .DEPTH (SYNC_DEPTH), + .ASYNC_RESET(ASYNC_RESET) + ) + alt_rst_sync_uq1 + ( + .clk (clk), + .reset_in (merged_reset), + .reset_out (reset_out) + ); + + end + endgenerate + +endmodule diff --git a/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_reset_synchronizer.v b/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_reset_synchronizer.v new file mode 100644 index 00000000..e75ca458 --- /dev/null +++ b/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_reset_synchronizer.v @@ -0,0 +1,87 @@ +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/12.1sp1/ip/merlin/altera_reset_controller/altera_reset_synchronizer.v#1 $ +// $Revision: #1 $ +// $Date: 2012/10/10 $ +// $Author: swbranch $ + +// ----------------------------------------------- +// Reset Synchronizer +// ----------------------------------------------- +`timescale 1 ns / 1 ns + +module altera_reset_synchronizer +#( + parameter ASYNC_RESET = 1, + parameter DEPTH = 2 +) +( + input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */, + + input clk, + output reset_out +); + + // ----------------------------------------------- + // Synchronizer register chain. We cannot reuse the + // standard synchronizer in this implementation + // because our timing constraints are different. + // + // Instead of cutting the timing path to the d-input + // on the first flop we need to cut the aclr input. + // + // We omit the "preserve" attribute on the final + // output register, so that the synthesis tool can + // duplicate it where needed. + // ----------------------------------------------- + (*preserve*) reg [DEPTH-1:0] altera_reset_synchronizer_int_chain; + reg altera_reset_synchronizer_int_chain_out; + + generate if (ASYNC_RESET) begin + + // ----------------------------------------------- + // Assert asynchronously, deassert synchronously. + // ----------------------------------------------- + always @(posedge clk or posedge reset_in) begin + if (reset_in) begin + altera_reset_synchronizer_int_chain <= {DEPTH{1'b1}}; + altera_reset_synchronizer_int_chain_out <= 1'b1; + end + else begin + altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1]; + altera_reset_synchronizer_int_chain[DEPTH-1] <= 0; + altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0]; + end + end + + assign reset_out = altera_reset_synchronizer_int_chain_out; + + end else begin + + // ----------------------------------------------- + // Assert synchronously, deassert synchronously. + // ----------------------------------------------- + always @(posedge clk) begin + altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1]; + altera_reset_synchronizer_int_chain[DEPTH-1] <= reset_in; + altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0]; + end + + assign reset_out = altera_reset_synchronizer_int_chain_out; + + end + endgenerate + +endmodule + diff --git a/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_up_rs232_counters.v b/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_up_rs232_counters.v new file mode 100644 index 00000000..071fcd57 --- /dev/null +++ b/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_up_rs232_counters.v @@ -0,0 +1,180 @@ +/****************************************************************************** + * License Agreement * + * * + * Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. * + * All rights reserved. * + * * + * Any megafunction design, and related net list (encrypted or decrypted), * + * support information, device programming or simulation file, and any other * + * associated documentation or information provided by Altera or a partner * + * under Altera's Megafunction Partnership Program may be used only to * + * program PLD devices (but not masked PLD devices) from Altera. Any other * + * use of such megafunction design, net list, support information, device * + * programming or simulation file, or any other related documentation or * + * information is prohibited for any other purpose, including, but not * + * limited to modification, reverse engineering, de-compiling, or use with * + * any other silicon devices, unless such use is explicitly licensed under * + * a separate agreement with Altera or a megafunction partner. Title to * + * the intellectual property, including patents, copyrights, trademarks, * + * trade secrets, or maskworks, embodied in any such megafunction design, * + * net list, support information, device programming or simulation file, or * + * any other related documentation or information provided by Altera or a * + * megafunction partner, remains with Altera, the megafunction partner, or * + * their respective licensors. No other licenses, including any licenses * + * needed under any third party's intellectual property, are provided herein.* + * Copying or modifying any file, or portion thereof, to which this notice * + * is attached violates this copyright. * + * * + * THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * + * FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS * + * IN THIS FILE. * + * * + * This agreement shall be governed in all respects by the laws of the State * + * of California and by the laws of the United States of America. * + * * + ******************************************************************************/ + +/****************************************************************************** + * * + * This module reads and writes data to the RS232 connectpr on Altera's * + * DE1 and DE2 Development and Education Boards. * + * * + ******************************************************************************/ + +module altera_up_rs232_counters ( + // Inputs + clk, + reset, + + reset_counters, + + // Bidirectionals + + // Outputs + baud_clock_rising_edge, + baud_clock_falling_edge, + all_bits_transmitted +); + +/***************************************************************************** + * Parameter Declarations * + *****************************************************************************/ + +parameter CW = 9; // BAUD COUNTER WIDTH +parameter BAUD_TICK_COUNT = 433; +parameter HALF_BAUD_TICK_COUNT = 216; + +parameter TDW = 11; // TOTAL DATA WIDTH + +/***************************************************************************** + * Port Declarations * + *****************************************************************************/ +// Inputs +input clk; +input reset; + +input reset_counters; + +// Bidirectionals + +// Outputs +output reg baud_clock_rising_edge; +output reg baud_clock_falling_edge; +output reg all_bits_transmitted; + +/***************************************************************************** + * Constant Declarations * + *****************************************************************************/ + +/***************************************************************************** + * Internal Wires and Registers Declarations * + *****************************************************************************/ + +// Internal Wires + +// Internal Registers +reg [(CW-1):0] baud_counter; +reg [ 3: 0] bit_counter; + +// State Machine Registers + + +/***************************************************************************** + * Finite State Machine(s) * + *****************************************************************************/ + + +/***************************************************************************** + * Sequential Logic * + *****************************************************************************/ + +always @(posedge clk) +begin + if (reset) + baud_counter <= {CW{1'b0}}; + else if (reset_counters) + baud_counter <= {CW{1'b0}}; + else if (baud_counter == BAUD_TICK_COUNT) + baud_counter <= {CW{1'b0}}; + else + baud_counter <= baud_counter + 1; +end + +always @(posedge clk) +begin + if (reset) + baud_clock_rising_edge <= 1'b0; + else if (baud_counter == BAUD_TICK_COUNT) + baud_clock_rising_edge <= 1'b1; + else + baud_clock_rising_edge <= 1'b0; +end + +always @(posedge clk) +begin + if (reset) + baud_clock_falling_edge <= 1'b0; + else if (baud_counter == HALF_BAUD_TICK_COUNT) + baud_clock_falling_edge <= 1'b1; + else + baud_clock_falling_edge <= 1'b0; +end + +always @(posedge clk) +begin + if (reset) + bit_counter <= 4'h0; + else if (reset_counters) + bit_counter <= 4'h0; + else if (bit_counter == TDW) + bit_counter <= 4'h0; + else if (baud_counter == BAUD_TICK_COUNT) + bit_counter <= bit_counter + 4'h1; +end + +always @(posedge clk) +begin + if (reset) + all_bits_transmitted <= 1'b0; + else if (bit_counter == TDW) + all_bits_transmitted <= 1'b1; + else + all_bits_transmitted <= 1'b0; +end + +/***************************************************************************** + * Combinational Logic * + *****************************************************************************/ + + +/***************************************************************************** + * Internal Modules * + *****************************************************************************/ + + +endmodule + diff --git a/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_up_rs232_in_deserializer.v b/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_up_rs232_in_deserializer.v new file mode 100644 index 00000000..31f17c9d --- /dev/null +++ b/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_up_rs232_in_deserializer.v @@ -0,0 +1,213 @@ +/****************************************************************************** + * License Agreement * + * * + * Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. * + * All rights reserved. * + * * + * Any megafunction design, and related net list (encrypted or decrypted), * + * support information, device programming or simulation file, and any other * + * associated documentation or information provided by Altera or a partner * + * under Altera's Megafunction Partnership Program may be used only to * + * program PLD devices (but not masked PLD devices) from Altera. Any other * + * use of such megafunction design, net list, support information, device * + * programming or simulation file, or any other related documentation or * + * information is prohibited for any other purpose, including, but not * + * limited to modification, reverse engineering, de-compiling, or use with * + * any other silicon devices, unless such use is explicitly licensed under * + * a separate agreement with Altera or a megafunction partner. Title to * + * the intellectual property, including patents, copyrights, trademarks, * + * trade secrets, or maskworks, embodied in any such megafunction design, * + * net list, support information, device programming or simulation file, or * + * any other related documentation or information provided by Altera or a * + * megafunction partner, remains with Altera, the megafunction partner, or * + * their respective licensors. No other licenses, including any licenses * + * needed under any third party's intellectual property, are provided herein.* + * Copying or modifying any file, or portion thereof, to which this notice * + * is attached violates this copyright. * + * * + * THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * + * FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS * + * IN THIS FILE. * + * * + * This agreement shall be governed in all respects by the laws of the State * + * of California and by the laws of the United States of America. * + * * + ******************************************************************************/ + +/****************************************************************************** + * * + * This module reads data to the RS232 UART Port. * + * * + ******************************************************************************/ + +module altera_up_rs232_in_deserializer ( + // Inputs + clk, + reset, + + serial_data_in, + + receive_data_en, + + // Bidirectionals + + // Outputs + fifo_read_available, + + received_data_valid, + received_data +); + +/***************************************************************************** + * Parameter Declarations * + *****************************************************************************/ + +parameter CW = 9; // Baud counter width +parameter BAUD_TICK_COUNT = 433; +parameter HALF_BAUD_TICK_COUNT = 216; + +parameter TDW = 11; // Total data width +parameter DW = 9; // Data width + +/***************************************************************************** + * Port Declarations * + *****************************************************************************/ +// Inputs +input clk; +input reset; + +input serial_data_in; + +input receive_data_en; + +// Bidirectionals + +// Outputs +output reg [ 7: 0] fifo_read_available; + +output received_data_valid; +output [DW: 0] received_data; + +/***************************************************************************** + * Constant Declarations * + *****************************************************************************/ + +/***************************************************************************** + * Internal Wires and Registers Declarations * + *****************************************************************************/ + +// Internal Wires +wire shift_data_reg_en; +wire all_bits_received; + +wire fifo_is_empty; +wire fifo_is_full; +wire [ 6: 0] fifo_used; + +// Internal Registers +reg receiving_data; + +reg [(TDW-1):0] data_in_shift_reg; + +// State Machine Registers + +/***************************************************************************** + * Finite State Machine(s) * + *****************************************************************************/ + + +/***************************************************************************** + * Sequential Logic * + *****************************************************************************/ + +always @(posedge clk) +begin + if (reset) + fifo_read_available <= 8'h00; + else + fifo_read_available <= {fifo_is_full, fifo_used}; +end + +always @(posedge clk) +begin + if (reset) + receiving_data <= 1'b0; + else if (all_bits_received) + receiving_data <= 1'b0; + else if (serial_data_in == 1'b0) + receiving_data <= 1'b1; +end + +always @(posedge clk) +begin + if (reset) + data_in_shift_reg <= {TDW{1'b0}}; + else if (shift_data_reg_en) + data_in_shift_reg <= + {serial_data_in, data_in_shift_reg[(TDW - 1):1]}; +end + +/***************************************************************************** + * Combinational Logic * + *****************************************************************************/ + +// Output assignments +assign received_data_valid = ~fifo_is_empty; + +// Input assignments + + +/***************************************************************************** + * Internal Modules * + *****************************************************************************/ + +altera_up_rs232_counters RS232_In_Counters ( + // Inputs + .clk (clk), + .reset (reset), + + .reset_counters (~receiving_data), + + // Bidirectionals + + // Outputs + .baud_clock_rising_edge (), + .baud_clock_falling_edge (shift_data_reg_en), + .all_bits_transmitted (all_bits_received) +); +defparam + RS232_In_Counters.CW = CW, + RS232_In_Counters.BAUD_TICK_COUNT = BAUD_TICK_COUNT, + RS232_In_Counters.HALF_BAUD_TICK_COUNT = HALF_BAUD_TICK_COUNT, + RS232_In_Counters.TDW = TDW; + +altera_up_sync_fifo RS232_In_FIFO ( + // Inputs + .clk (clk), + .reset (reset), + + .write_en (all_bits_received & ~fifo_is_full), + .write_data (data_in_shift_reg[(DW + 1):1]), + + .read_en (receive_data_en & ~fifo_is_empty), + + // Bidirectionals + + // Outputs + .fifo_is_empty (fifo_is_empty), + .fifo_is_full (fifo_is_full), + .words_used (fifo_used), + + .read_data (received_data) +); +defparam + RS232_In_FIFO.DW = DW, + RS232_In_FIFO.DATA_DEPTH = 128, + RS232_In_FIFO.AW = 6; + +endmodule + diff --git a/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_up_rs232_out_serializer.v b/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_up_rs232_out_serializer.v new file mode 100644 index 00000000..2caf5aa7 --- /dev/null +++ b/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_up_rs232_out_serializer.v @@ -0,0 +1,221 @@ +/****************************************************************************** + * License Agreement * + * * + * Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. * + * All rights reserved. * + * * + * Any megafunction design, and related net list (encrypted or decrypted), * + * support information, device programming or simulation file, and any other * + * associated documentation or information provided by Altera or a partner * + * under Altera's Megafunction Partnership Program may be used only to * + * program PLD devices (but not masked PLD devices) from Altera. Any other * + * use of such megafunction design, net list, support information, device * + * programming or simulation file, or any other related documentation or * + * information is prohibited for any other purpose, including, but not * + * limited to modification, reverse engineering, de-compiling, or use with * + * any other silicon devices, unless such use is explicitly licensed under * + * a separate agreement with Altera or a megafunction partner. Title to * + * the intellectual property, including patents, copyrights, trademarks, * + * trade secrets, or maskworks, embodied in any such megafunction design, * + * net list, support information, device programming or simulation file, or * + * any other related documentation or information provided by Altera or a * + * megafunction partner, remains with Altera, the megafunction partner, or * + * their respective licensors. No other licenses, including any licenses * + * needed under any third party's intellectual property, are provided herein.* + * Copying or modifying any file, or portion thereof, to which this notice * + * is attached violates this copyright. * + * * + * THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * + * FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS * + * IN THIS FILE. * + * * + * This agreement shall be governed in all respects by the laws of the State * + * of California and by the laws of the United States of America. * + * * + ******************************************************************************/ + +/****************************************************************************** + * * + * This module writes data to the RS232 UART Port. * + * * + ******************************************************************************/ + +module altera_up_rs232_out_serializer ( + // Inputs + clk, + reset, + + transmit_data, + transmit_data_en, + + // Bidirectionals + + // Outputs + fifo_write_space, + + serial_data_out +); + +/***************************************************************************** + * Parameter Declarations * + *****************************************************************************/ + +parameter CW = 9; // Baud counter width +parameter BAUD_TICK_COUNT = 433; +parameter HALF_BAUD_TICK_COUNT = 216; + +parameter TDW = 11; // Total data width +parameter DW = 9; // Data width + +/***************************************************************************** + * Port Declarations * + *****************************************************************************/ +// Inputs +input clk; +input reset; + +input [DW: 0] transmit_data; +input transmit_data_en; + +// Bidirectionals + +// Outputs +output reg [ 7: 0] fifo_write_space; + +output reg serial_data_out; + +/***************************************************************************** + * Constant Declarations * + *****************************************************************************/ + +/***************************************************************************** + * Internal Wires and Registers Declarations * + *****************************************************************************/ + +// Internal Wires +wire shift_data_reg_en; +wire all_bits_transmitted; + +wire read_fifo_en; + +wire fifo_is_empty; +wire fifo_is_full; +wire [ 6: 0] fifo_used; + +wire [DW: 0] data_from_fifo; + +// Internal Registers +reg transmitting_data; + +reg [DW+1:0] data_out_shift_reg; + +// State Machine Registers + +/***************************************************************************** + * Finite State Machine(s) * + *****************************************************************************/ + + +/***************************************************************************** + * Sequential Logic * + *****************************************************************************/ + +always @(posedge clk) +begin + if (reset) + fifo_write_space <= 8'h00; + else + fifo_write_space <= 8'h80 - {fifo_is_full, fifo_used}; +end + + +always @(posedge clk) +begin + if (reset) + serial_data_out <= 1'b1; + else + serial_data_out <= data_out_shift_reg[0]; +end + +always @(posedge clk) +begin + if (reset) + transmitting_data <= 1'b0; + else if (all_bits_transmitted) + transmitting_data <= 1'b0; + else if (fifo_is_empty == 1'b0) + transmitting_data <= 1'b1; +end + +always @(posedge clk) +begin + if (reset) + data_out_shift_reg <= {(DW + 2){1'b1}}; + else if (read_fifo_en) + data_out_shift_reg <= {data_from_fifo, 1'b0}; + else if (shift_data_reg_en) + data_out_shift_reg <= + {1'b1, data_out_shift_reg[DW+1:1]}; +end + +/***************************************************************************** + * Combinational Logic * + *****************************************************************************/ + +assign read_fifo_en = + ~transmitting_data & ~fifo_is_empty & ~all_bits_transmitted; + +/***************************************************************************** + * Internal Modules * + *****************************************************************************/ + +altera_up_rs232_counters RS232_Out_Counters ( + // Inputs + .clk (clk), + .reset (reset), + + .reset_counters (~transmitting_data), + + // Bidirectionals + + // Outputs + .baud_clock_rising_edge (shift_data_reg_en), + .baud_clock_falling_edge (), + .all_bits_transmitted (all_bits_transmitted) +); +defparam + RS232_Out_Counters.CW = CW, + RS232_Out_Counters.BAUD_TICK_COUNT = BAUD_TICK_COUNT, + RS232_Out_Counters.HALF_BAUD_TICK_COUNT = HALF_BAUD_TICK_COUNT, + RS232_Out_Counters.TDW = TDW; + +altera_up_sync_fifo RS232_Out_FIFO ( + // Inputs + .clk (clk), + .reset (reset), + + .write_en (transmit_data_en & ~fifo_is_full), + .write_data (transmit_data), + + .read_en (read_fifo_en), + + // Bidirectionals + + // Outputs + .fifo_is_empty (fifo_is_empty), + .fifo_is_full (fifo_is_full), + .words_used (fifo_used), + + .read_data (data_from_fifo) +); +defparam + RS232_Out_FIFO.DW = DW, + RS232_Out_FIFO.DATA_DEPTH = 128, + RS232_Out_FIFO.AW = 6; + +endmodule + diff --git a/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_up_sync_fifo.v b/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_up_sync_fifo.v new file mode 100644 index 00000000..f5092f0f --- /dev/null +++ b/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_up_sync_fifo.v @@ -0,0 +1,171 @@ +/****************************************************************************** + * License Agreement * + * * + * Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. * + * All rights reserved. * + * * + * Any megafunction design, and related net list (encrypted or decrypted), * + * support information, device programming or simulation file, and any other * + * associated documentation or information provided by Altera or a partner * + * under Altera's Megafunction Partnership Program may be used only to * + * program PLD devices (but not masked PLD devices) from Altera. Any other * + * use of such megafunction design, net list, support information, device * + * programming or simulation file, or any other related documentation or * + * information is prohibited for any other purpose, including, but not * + * limited to modification, reverse engineering, de-compiling, or use with * + * any other silicon devices, unless such use is explicitly licensed under * + * a separate agreement with Altera or a megafunction partner. Title to * + * the intellectual property, including patents, copyrights, trademarks, * + * trade secrets, or maskworks, embodied in any such megafunction design, * + * net list, support information, device programming or simulation file, or * + * any other related documentation or information provided by Altera or a * + * megafunction partner, remains with Altera, the megafunction partner, or * + * their respective licensors. No other licenses, including any licenses * + * needed under any third party's intellectual property, are provided herein.* + * Copying or modifying any file, or portion thereof, to which this notice * + * is attached violates this copyright. * + * * + * THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * + * FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS * + * IN THIS FILE. * + * * + * This agreement shall be governed in all respects by the laws of the State * + * of California and by the laws of the United States of America. * + * * + ******************************************************************************/ + +/****************************************************************************** + * * + * This module is a FIFO with same clock for both reads and writes. * + * * + ******************************************************************************/ + +module altera_up_sync_fifo ( + // Inputs + clk, + reset, + + write_en, + write_data, + + read_en, + + // Bidirectionals + + // Outputs + fifo_is_empty, + fifo_is_full, + words_used, + + read_data +); + +/***************************************************************************** + * Parameter Declarations * + *****************************************************************************/ + +parameter DW = 31; // Data width +parameter DATA_DEPTH = 128; +parameter AW = 6; // Address width + +/***************************************************************************** + * Port Declarations * + *****************************************************************************/ + +// Inputs +input clk; +input reset; + +input write_en; +input [DW: 0] write_data; + +input read_en; + +// Bidirectionals + +// Outputs +output fifo_is_empty; +output fifo_is_full; +output [AW: 0] words_used; + +output [DW: 0] read_data; + +/***************************************************************************** + * Constant Declarations * + *****************************************************************************/ + +/***************************************************************************** + * Internal Wires and Registers Declarations * + *****************************************************************************/ + +// Internal Wires + +// Internal Registers + +// State Machine Registers + +/***************************************************************************** + * Finite State Machine(s) * + *****************************************************************************/ + + +/***************************************************************************** + * Sequential Logic * + *****************************************************************************/ + + +/***************************************************************************** + * Combinational Logic * + *****************************************************************************/ + + +/***************************************************************************** + * Internal Modules * + *****************************************************************************/ + + +scfifo Sync_FIFO ( + // Inputs + .clock (clk), + .sclr (reset), + + .data (write_data), + .wrreq (write_en), + + .rdreq (read_en), + + // Bidirectionals + + // Outputs + .empty (fifo_is_empty), + .full (fifo_is_full), + .usedw (words_used), + + .q (read_data), + + // Unused + // synopsys translate_off + + .aclr (), + .almost_empty (), + .almost_full () + // synopsys translate_on +); +defparam + Sync_FIFO.add_ram_output_register = "OFF", + Sync_FIFO.intended_device_family = "Cyclone II", + Sync_FIFO.lpm_numwords = DATA_DEPTH, + Sync_FIFO.lpm_showahead = "ON", + Sync_FIFO.lpm_type = "scfifo", + Sync_FIFO.lpm_width = DW + 1, + Sync_FIFO.lpm_widthu = AW + 1, + Sync_FIFO.overflow_checking = "OFF", + Sync_FIFO.underflow_checking = "OFF", + Sync_FIFO.use_eab = "ON"; + +endmodule + diff --git a/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_addr_router.sv b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_addr_router.sv new file mode 100644 index 00000000..987f626d --- /dev/null +++ b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_addr_router.sv @@ -0,0 +1,187 @@ +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/12.1sp1/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2012/10/10 $ +// $Author: swbranch $ + +// ------------------------------------------------------- +// Merlin Router +// +// Asserts the appropriate one-hot encoded channel based on +// either (a) the address or (b) the dest id. The DECODER_TYPE +// parameter controls this behaviour. 0 means address decoder, +// 1 means dest id decoder. +// +// In the case of (a), it also sets the destination id. +// ------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module system_addr_router_default_decode + #( + parameter DEFAULT_CHANNEL = 1, + DEFAULT_DESTID = 1 + ) + (output [90 - 87 : 0] default_destination_id, + output [11-1 : 0] default_src_channel + ); + + assign default_destination_id = + DEFAULT_DESTID[90 - 87 : 0]; + generate begin : default_decode + if (DEFAULT_CHANNEL == -1) + assign default_src_channel = '0; + else + assign default_src_channel = 11'b1 << DEFAULT_CHANNEL; + end + endgenerate + +endmodule + + +module system_addr_router +( + // ------------------- + // Clock & Reset + // ------------------- + input clk, + input reset, + + // ------------------- + // Command Sink (Input) + // ------------------- + input sink_valid, + input [101-1 : 0] sink_data, + input sink_startofpacket, + input sink_endofpacket, + output sink_ready, + + // ------------------- + // Command Source (Output) + // ------------------- + output src_valid, + output reg [101-1 : 0] src_data, + output reg [11-1 : 0] src_channel, + output src_startofpacket, + output src_endofpacket, + input src_ready +); + + // ------------------------------------------------------- + // Local parameters and variables + // ------------------------------------------------------- + localparam PKT_ADDR_H = 61; + localparam PKT_ADDR_L = 36; + localparam PKT_DEST_ID_H = 90; + localparam PKT_DEST_ID_L = 87; + localparam ST_DATA_W = 101; + localparam ST_CHANNEL_W = 11; + localparam DECODER_TYPE = 0; + + localparam PKT_TRANS_WRITE = 64; + localparam PKT_TRANS_READ = 65; + + localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1; + localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1; + + + + + // ------------------------------------------------------- + // Figure out the number of bits to mask off for each slave span + // during address decoding + // ------------------------------------------------------- + localparam PAD0 = log2ceil(64'h2000000 - 64'h1000000); + localparam PAD1 = log2ceil(64'h2001000 - 64'h2000800); + // ------------------------------------------------------- + // Work out which address bits are significant based on the + // address range of the slaves. If the required width is too + // large or too small, we use the address field width instead. + // ------------------------------------------------------- + localparam ADDR_RANGE = 64'h2001000; + localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE); + localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) || + (RANGE_ADDR_WIDTH == 0) ? + PKT_ADDR_H : + PKT_ADDR_L + RANGE_ADDR_WIDTH - 1; + localparam RG = RANGE_ADDR_WIDTH-1; + + wire [PKT_ADDR_W-1 : 0] address = sink_data[OPTIMIZED_ADDR_H : PKT_ADDR_L]; + + // ------------------------------------------------------- + // Pass almost everything through, untouched + // ------------------------------------------------------- + assign sink_ready = src_ready; + assign src_valid = sink_valid; + assign src_startofpacket = sink_startofpacket; + assign src_endofpacket = sink_endofpacket; + + wire [PKT_DEST_ID_W-1:0] default_destid; + wire [11-1 : 0] default_src_channel; + + + + + system_addr_router_default_decode the_default_decode( + .default_destination_id (default_destid), + .default_src_channel (default_src_channel) + ); + + always @* begin + src_data = sink_data; + src_channel = default_src_channel; + + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = default_destid; + // -------------------------------------------------- + // Address Decoder + // Sets the channel and destination ID based on the address + // -------------------------------------------------- + + // ( 0x1000000 .. 0x2000000 ) + if ( {address[RG:PAD0],{PAD0{1'b0}}} == 26'h1000000 ) begin + src_channel = 11'b10; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 1; + end + + // ( 0x2000800 .. 0x2001000 ) + if ( {address[RG:PAD1],{PAD1{1'b0}}} == 26'h2000800 ) begin + src_channel = 11'b01; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 0; + end + +end + + + // -------------------------------------------------- + // Ceil(log2()) function + // -------------------------------------------------- + function integer log2ceil; + input reg[65:0] val; + reg [65:0] i; + + begin + i = 1; + log2ceil = 0; + + while (i < val) begin + log2ceil = log2ceil + 1; + i = i << 1; + end + end + endfunction + +endmodule + + diff --git a/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_addr_router_001.sv b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_addr_router_001.sv new file mode 100644 index 00000000..ab469a39 --- /dev/null +++ b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_addr_router_001.sv @@ -0,0 +1,250 @@ +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/12.1sp1/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2012/10/10 $ +// $Author: swbranch $ + +// ------------------------------------------------------- +// Merlin Router +// +// Asserts the appropriate one-hot encoded channel based on +// either (a) the address or (b) the dest id. The DECODER_TYPE +// parameter controls this behaviour. 0 means address decoder, +// 1 means dest id decoder. +// +// In the case of (a), it also sets the destination id. +// ------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module system_addr_router_001_default_decode + #( + parameter DEFAULT_CHANNEL = 1, + DEFAULT_DESTID = 1 + ) + (output [90 - 87 : 0] default_destination_id, + output [11-1 : 0] default_src_channel + ); + + assign default_destination_id = + DEFAULT_DESTID[90 - 87 : 0]; + generate begin : default_decode + if (DEFAULT_CHANNEL == -1) + assign default_src_channel = '0; + else + assign default_src_channel = 11'b1 << DEFAULT_CHANNEL; + end + endgenerate + +endmodule + + +module system_addr_router_001 +( + // ------------------- + // Clock & Reset + // ------------------- + input clk, + input reset, + + // ------------------- + // Command Sink (Input) + // ------------------- + input sink_valid, + input [101-1 : 0] sink_data, + input sink_startofpacket, + input sink_endofpacket, + output sink_ready, + + // ------------------- + // Command Source (Output) + // ------------------- + output src_valid, + output reg [101-1 : 0] src_data, + output reg [11-1 : 0] src_channel, + output src_startofpacket, + output src_endofpacket, + input src_ready +); + + // ------------------------------------------------------- + // Local parameters and variables + // ------------------------------------------------------- + localparam PKT_ADDR_H = 61; + localparam PKT_ADDR_L = 36; + localparam PKT_DEST_ID_H = 90; + localparam PKT_DEST_ID_L = 87; + localparam ST_DATA_W = 101; + localparam ST_CHANNEL_W = 11; + localparam DECODER_TYPE = 0; + + localparam PKT_TRANS_WRITE = 64; + localparam PKT_TRANS_READ = 65; + + localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1; + localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1; + + + + + // ------------------------------------------------------- + // Figure out the number of bits to mask off for each slave span + // during address decoding + // ------------------------------------------------------- + localparam PAD0 = log2ceil(64'h2000000 - 64'h1000000); + localparam PAD1 = log2ceil(64'h2001000 - 64'h2000800); + localparam PAD2 = log2ceil(64'h2001020 - 64'h2001000); + localparam PAD3 = log2ceil(64'h2001040 - 64'h2001020); + localparam PAD4 = log2ceil(64'h2001060 - 64'h2001040); + localparam PAD5 = log2ceil(64'h2001070 - 64'h2001060); + localparam PAD6 = log2ceil(64'h2001080 - 64'h2001070); + localparam PAD7 = log2ceil(64'h2001090 - 64'h2001080); + localparam PAD8 = log2ceil(64'h2001098 - 64'h2001090); + localparam PAD9 = log2ceil(64'h20010a0 - 64'h2001098); + localparam PAD10 = log2ceil(64'h20010a8 - 64'h20010a0); + // ------------------------------------------------------- + // Work out which address bits are significant based on the + // address range of the slaves. If the required width is too + // large or too small, we use the address field width instead. + // ------------------------------------------------------- + localparam ADDR_RANGE = 64'h20010a8; + localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE); + localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) || + (RANGE_ADDR_WIDTH == 0) ? + PKT_ADDR_H : + PKT_ADDR_L + RANGE_ADDR_WIDTH - 1; + localparam RG = RANGE_ADDR_WIDTH-1; + + wire [PKT_ADDR_W-1 : 0] address = sink_data[OPTIMIZED_ADDR_H : PKT_ADDR_L]; + + // ------------------------------------------------------- + // Pass almost everything through, untouched + // ------------------------------------------------------- + assign sink_ready = src_ready; + assign src_valid = sink_valid; + assign src_startofpacket = sink_startofpacket; + assign src_endofpacket = sink_endofpacket; + + wire [PKT_DEST_ID_W-1:0] default_destid; + wire [11-1 : 0] default_src_channel; + + + + + system_addr_router_001_default_decode the_default_decode( + .default_destination_id (default_destid), + .default_src_channel (default_src_channel) + ); + + always @* begin + src_data = sink_data; + src_channel = default_src_channel; + + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = default_destid; + // -------------------------------------------------- + // Address Decoder + // Sets the channel and destination ID based on the address + // -------------------------------------------------- + + // ( 0x1000000 .. 0x2000000 ) + if ( {address[RG:PAD0],{PAD0{1'b0}}} == 26'h1000000 ) begin + src_channel = 11'b00000000010; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 1; + end + + // ( 0x2000800 .. 0x2001000 ) + if ( {address[RG:PAD1],{PAD1{1'b0}}} == 26'h2000800 ) begin + src_channel = 11'b00000000001; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 0; + end + + // ( 0x2001000 .. 0x2001020 ) + if ( {address[RG:PAD2],{PAD2{1'b0}}} == 26'h2001000 ) begin + src_channel = 11'b00000100000; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 5; + end + + // ( 0x2001020 .. 0x2001040 ) + if ( {address[RG:PAD3],{PAD3{1'b0}}} == 26'h2001020 ) begin + src_channel = 11'b00000010000; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 4; + end + + // ( 0x2001040 .. 0x2001060 ) + if ( {address[RG:PAD4],{PAD4{1'b0}}} == 26'h2001040 ) begin + src_channel = 11'b00000001000; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 3; + end + + // ( 0x2001060 .. 0x2001070 ) + if ( {address[RG:PAD5],{PAD5{1'b0}}} == 26'h2001060 ) begin + src_channel = 11'b01000000000; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 9; + end + + // ( 0x2001070 .. 0x2001080 ) + if ( {address[RG:PAD6],{PAD6{1'b0}}} == 26'h2001070 ) begin + src_channel = 11'b00010000000; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 7; + end + + // ( 0x2001080 .. 0x2001090 ) + if ( {address[RG:PAD7],{PAD7{1'b0}}} == 26'h2001080 ) begin + src_channel = 11'b00001000000; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 6; + end + + // ( 0x2001090 .. 0x2001098 ) + if ( {address[RG:PAD8],{PAD8{1'b0}}} == 26'h2001090 ) begin + src_channel = 11'b10000000000; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 10; + end + + // ( 0x2001098 .. 0x20010a0 ) + if ( {address[RG:PAD9],{PAD9{1'b0}}} == 26'h2001098 ) begin + src_channel = 11'b00100000000; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 8; + end + + // ( 0x20010a0 .. 0x20010a8 ) + if ( {address[RG:PAD10],{PAD10{1'b0}}} == 26'h20010a0 ) begin + src_channel = 11'b00000000100; + src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 2; + end + +end + + + // -------------------------------------------------- + // Ceil(log2()) function + // -------------------------------------------------- + function integer log2ceil; + input reg[65:0] val; + reg [65:0] i; + + begin + i = 1; + log2ceil = 0; + + while (i < val) begin + log2ceil = log2ceil + 1; + i = i << 1; + end + end + endfunction + +endmodule + + diff --git a/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cmd_xbar_demux.sv b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cmd_xbar_demux.sv new file mode 100644 index 00000000..efb78638 --- /dev/null +++ b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cmd_xbar_demux.sv @@ -0,0 +1,116 @@ +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/12.1sp1/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2012/10/10 $ +// $Author: swbranch $ + +// ------------------------------------- +// Merlin Demultiplexer +// +// Asserts valid on the appropriate output +// given a one-hot channel signal. +// ------------------------------------- + +`timescale 1 ns / 1 ns + +// ------------------------------------------ +// Generation parameters: +// output_name: system_cmd_xbar_demux +// ST_DATA_W: 101 +// ST_CHANNEL_W: 11 +// NUM_OUTPUTS: 2 +// VALID_WIDTH: 11 +// ------------------------------------------ + +//------------------------------------------ +// Message Supression Used +// QIS Warnings +// 15610 - Warning: Design contains x input pin(s) that do not drive logic +//------------------------------------------ + +module system_cmd_xbar_demux +( + // ------------------- + // Sink + // ------------------- + input [11-1 : 0] sink_valid, + input [101-1 : 0] sink_data, // ST_DATA_W=101 + input [11-1 : 0] sink_channel, // ST_CHANNEL_W=11 + input sink_startofpacket, + input sink_endofpacket, + output sink_ready, + + // ------------------- + // Sources + // ------------------- + output reg src0_valid, + output reg [101-1 : 0] src0_data, // ST_DATA_W=101 + output reg [11-1 : 0] src0_channel, // ST_CHANNEL_W=11 + output reg src0_startofpacket, + output reg src0_endofpacket, + input src0_ready, + + output reg src1_valid, + output reg [101-1 : 0] src1_data, // ST_DATA_W=101 + output reg [11-1 : 0] src1_channel, // ST_CHANNEL_W=11 + output reg src1_startofpacket, + output reg src1_endofpacket, + input src1_ready, + + + // ------------------- + // Clock & Reset + // ------------------- + (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk + input clk, + (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset + input reset + +); + + localparam NUM_OUTPUTS = 2; + wire [NUM_OUTPUTS - 1 : 0] ready_vector; + + // ------------------- + // Demux + // ------------------- + always @* begin + src0_data = sink_data; + src0_startofpacket = sink_startofpacket; + src0_endofpacket = sink_endofpacket; + src0_channel = sink_channel >> NUM_OUTPUTS; + + src0_valid = sink_channel[0] && sink_valid[0]; + + src1_data = sink_data; + src1_startofpacket = sink_startofpacket; + src1_endofpacket = sink_endofpacket; + src1_channel = sink_channel >> NUM_OUTPUTS; + + src1_valid = sink_channel[1] && sink_valid[1]; + + end + + // ------------------- + // Backpressure + // ------------------- + assign ready_vector[0] = src0_ready; + assign ready_vector[1] = src1_ready; + + assign sink_ready = |(sink_channel & {{9{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}}); + +endmodule + + diff --git a/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cmd_xbar_demux_001.sv b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cmd_xbar_demux_001.sv new file mode 100644 index 00000000..3a8b9492 --- /dev/null +++ b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cmd_xbar_demux_001.sv @@ -0,0 +1,251 @@ +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/12.1sp1/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2012/10/10 $ +// $Author: swbranch $ + +// ------------------------------------- +// Merlin Demultiplexer +// +// Asserts valid on the appropriate output +// given a one-hot channel signal. +// ------------------------------------- + +`timescale 1 ns / 1 ns + +// ------------------------------------------ +// Generation parameters: +// output_name: system_cmd_xbar_demux_001 +// ST_DATA_W: 101 +// ST_CHANNEL_W: 11 +// NUM_OUTPUTS: 11 +// VALID_WIDTH: 11 +// ------------------------------------------ + +//------------------------------------------ +// Message Supression Used +// QIS Warnings +// 15610 - Warning: Design contains x input pin(s) that do not drive logic +//------------------------------------------ + +module system_cmd_xbar_demux_001 +( + // ------------------- + // Sink + // ------------------- + input [11-1 : 0] sink_valid, + input [101-1 : 0] sink_data, // ST_DATA_W=101 + input [11-1 : 0] sink_channel, // ST_CHANNEL_W=11 + input sink_startofpacket, + input sink_endofpacket, + output sink_ready, + + // ------------------- + // Sources + // ------------------- + output reg src0_valid, + output reg [101-1 : 0] src0_data, // ST_DATA_W=101 + output reg [11-1 : 0] src0_channel, // ST_CHANNEL_W=11 + output reg src0_startofpacket, + output reg src0_endofpacket, + input src0_ready, + + output reg src1_valid, + output reg [101-1 : 0] src1_data, // ST_DATA_W=101 + output reg [11-1 : 0] src1_channel, // ST_CHANNEL_W=11 + output reg src1_startofpacket, + output reg src1_endofpacket, + input src1_ready, + + output reg src2_valid, + output reg [101-1 : 0] src2_data, // ST_DATA_W=101 + output reg [11-1 : 0] src2_channel, // ST_CHANNEL_W=11 + output reg src2_startofpacket, + output reg src2_endofpacket, + input src2_ready, + + output reg src3_valid, + output reg [101-1 : 0] src3_data, // ST_DATA_W=101 + output reg [11-1 : 0] src3_channel, // ST_CHANNEL_W=11 + output reg src3_startofpacket, + output reg src3_endofpacket, + input src3_ready, + + output reg src4_valid, + output reg [101-1 : 0] src4_data, // ST_DATA_W=101 + output reg [11-1 : 0] src4_channel, // ST_CHANNEL_W=11 + output reg src4_startofpacket, + output reg src4_endofpacket, + input src4_ready, + + output reg src5_valid, + output reg [101-1 : 0] src5_data, // ST_DATA_W=101 + output reg [11-1 : 0] src5_channel, // ST_CHANNEL_W=11 + output reg src5_startofpacket, + output reg src5_endofpacket, + input src5_ready, + + output reg src6_valid, + output reg [101-1 : 0] src6_data, // ST_DATA_W=101 + output reg [11-1 : 0] src6_channel, // ST_CHANNEL_W=11 + output reg src6_startofpacket, + output reg src6_endofpacket, + input src6_ready, + + output reg src7_valid, + output reg [101-1 : 0] src7_data, // ST_DATA_W=101 + output reg [11-1 : 0] src7_channel, // ST_CHANNEL_W=11 + output reg src7_startofpacket, + output reg src7_endofpacket, + input src7_ready, + + output reg src8_valid, + output reg [101-1 : 0] src8_data, // ST_DATA_W=101 + output reg [11-1 : 0] src8_channel, // ST_CHANNEL_W=11 + output reg src8_startofpacket, + output reg src8_endofpacket, + input src8_ready, + + output reg src9_valid, + output reg [101-1 : 0] src9_data, // ST_DATA_W=101 + output reg [11-1 : 0] src9_channel, // ST_CHANNEL_W=11 + output reg src9_startofpacket, + output reg src9_endofpacket, + input src9_ready, + + output reg src10_valid, + output reg [101-1 : 0] src10_data, // ST_DATA_W=101 + output reg [11-1 : 0] src10_channel, // ST_CHANNEL_W=11 + output reg src10_startofpacket, + output reg src10_endofpacket, + input src10_ready, + + + // ------------------- + // Clock & Reset + // ------------------- + (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk + input clk, + (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset + input reset + +); + + localparam NUM_OUTPUTS = 11; + wire [NUM_OUTPUTS - 1 : 0] ready_vector; + + // ------------------- + // Demux + // ------------------- + always @* begin + src0_data = sink_data; + src0_startofpacket = sink_startofpacket; + src0_endofpacket = sink_endofpacket; + src0_channel = sink_channel >> NUM_OUTPUTS; + + src0_valid = sink_channel[0] && sink_valid[0]; + + src1_data = sink_data; + src1_startofpacket = sink_startofpacket; + src1_endofpacket = sink_endofpacket; + src1_channel = sink_channel >> NUM_OUTPUTS; + + src1_valid = sink_channel[1] && sink_valid[1]; + + src2_data = sink_data; + src2_startofpacket = sink_startofpacket; + src2_endofpacket = sink_endofpacket; + src2_channel = sink_channel >> NUM_OUTPUTS; + + src2_valid = sink_channel[2] && sink_valid[2]; + + src3_data = sink_data; + src3_startofpacket = sink_startofpacket; + src3_endofpacket = sink_endofpacket; + src3_channel = sink_channel >> NUM_OUTPUTS; + + src3_valid = sink_channel[3] && sink_valid[3]; + + src4_data = sink_data; + src4_startofpacket = sink_startofpacket; + src4_endofpacket = sink_endofpacket; + src4_channel = sink_channel >> NUM_OUTPUTS; + + src4_valid = sink_channel[4] && sink_valid[4]; + + src5_data = sink_data; + src5_startofpacket = sink_startofpacket; + src5_endofpacket = sink_endofpacket; + src5_channel = sink_channel >> NUM_OUTPUTS; + + src5_valid = sink_channel[5] && sink_valid[5]; + + src6_data = sink_data; + src6_startofpacket = sink_startofpacket; + src6_endofpacket = sink_endofpacket; + src6_channel = sink_channel >> NUM_OUTPUTS; + + src6_valid = sink_channel[6] && sink_valid[6]; + + src7_data = sink_data; + src7_startofpacket = sink_startofpacket; + src7_endofpacket = sink_endofpacket; + src7_channel = sink_channel >> NUM_OUTPUTS; + + src7_valid = sink_channel[7] && sink_valid[7]; + + src8_data = sink_data; + src8_startofpacket = sink_startofpacket; + src8_endofpacket = sink_endofpacket; + src8_channel = sink_channel >> NUM_OUTPUTS; + + src8_valid = sink_channel[8] && sink_valid[8]; + + src9_data = sink_data; + src9_startofpacket = sink_startofpacket; + src9_endofpacket = sink_endofpacket; + src9_channel = sink_channel >> NUM_OUTPUTS; + + src9_valid = sink_channel[9] && sink_valid[9]; + + src10_data = sink_data; + src10_startofpacket = sink_startofpacket; + src10_endofpacket = sink_endofpacket; + src10_channel = sink_channel >> NUM_OUTPUTS; + + src10_valid = sink_channel[10] && sink_valid[10]; + + end + + // ------------------- + // Backpressure + // ------------------- + assign ready_vector[0] = src0_ready; + assign ready_vector[1] = src1_ready; + assign ready_vector[2] = src2_ready; + assign ready_vector[3] = src3_ready; + assign ready_vector[4] = src4_ready; + assign ready_vector[5] = src5_ready; + assign ready_vector[6] = src6_ready; + assign ready_vector[7] = src7_ready; + assign ready_vector[8] = src8_ready; + assign ready_vector[9] = src9_ready; + assign ready_vector[10] = src10_ready; + + assign sink_ready = |(sink_channel & ready_vector); + +endmodule + + diff --git a/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cmd_xbar_mux.sv b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cmd_xbar_mux.sv new file mode 100644 index 00000000..c97ea176 --- /dev/null +++ b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cmd_xbar_mux.sv @@ -0,0 +1,308 @@ +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/12.1sp1/ip/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2012/10/10 $ +// $Author: swbranch $ + +// ------------------------------------------ +// Merlin Multiplexer +// ------------------------------------------ + +`timescale 1 ns / 1 ns + + +// ------------------------------------------ +// Generation parameters: +// output_name: system_cmd_xbar_mux +// NUM_INPUTS: 2 +// ARBITRATION_SHARES: 1 1 +// ARBITRATION_SCHEME "round-robin" +// PIPELINE_ARB: 1 +// PKT_TRANS_LOCK: 66 (arbitration locking enabled) +// ST_DATA_W: 101 +// ST_CHANNEL_W: 11 +// ------------------------------------------ + +module system_cmd_xbar_mux +( + // ---------------------- + // Sinks + // ---------------------- + input sink0_valid, + input [101-1 : 0] sink0_data, + input [11-1: 0] sink0_channel, + input sink0_startofpacket, + input sink0_endofpacket, + output sink0_ready, + + input sink1_valid, + input [101-1 : 0] sink1_data, + input [11-1: 0] sink1_channel, + input sink1_startofpacket, + input sink1_endofpacket, + output sink1_ready, + + + // ---------------------- + // Source + // ---------------------- + output src_valid, + output [101-1 : 0] src_data, + output [11-1 : 0] src_channel, + output src_startofpacket, + output src_endofpacket, + input src_ready, + + // ---------------------- + // Clock & Reset + // ---------------------- + input clk, + input reset +); + localparam PAYLOAD_W = 101 + 11 + 2; + localparam NUM_INPUTS = 2; + localparam SHARE_COUNTER_W = 1; + localparam PIPELINE_ARB = 1; + localparam ST_DATA_W = 101; + localparam ST_CHANNEL_W = 11; + localparam PKT_TRANS_LOCK = 66; + + // ------------------------------------------ + // Signals + // ------------------------------------------ + wire [NUM_INPUTS - 1 : 0] request; + wire [NUM_INPUTS - 1 : 0] valid; + wire [NUM_INPUTS - 1 : 0] grant; + wire [NUM_INPUTS - 1 : 0] next_grant; + reg [NUM_INPUTS - 1 : 0] saved_grant; + reg [PAYLOAD_W - 1 : 0] src_payload; + wire last_cycle; + reg packet_in_progress; + reg update_grant; + + wire [PAYLOAD_W - 1 : 0] sink0_payload; + wire [PAYLOAD_W - 1 : 0] sink1_payload; + + assign valid[0] = sink0_valid; + assign valid[1] = sink1_valid; + + wire [NUM_INPUTS - 1 : 0] eop; + assign eop[0] = sink0_endofpacket; + assign eop[1] = sink1_endofpacket; + + // ------------------------------------------ + // ------------------------------------------ + // Grant Logic & Updates + // ------------------------------------------ + // ------------------------------------------ + reg [NUM_INPUTS - 1 : 0] lock; + always @* begin + lock[0] = sink0_data[66]; + lock[1] = sink1_data[66]; + end + reg [NUM_INPUTS - 1 : 0] locked = '0; + always @(posedge clk or posedge reset) begin + if (reset) begin + locked <= '0; + end + else begin + locked <= next_grant & lock; + end + end + + assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant)); + + // ------------------------------------------ + // We're working on a packet at any time valid is high, except + // when this is the endofpacket. + // ------------------------------------------ + always @(posedge clk or posedge reset) begin + if (reset) begin + packet_in_progress <= 1'b0; + end + else begin + if (src_valid) + packet_in_progress <= 1'b1; + if (last_cycle) + packet_in_progress <= 1'b0; + end + end + + + // ------------------------------------------ + // Shares + // + // Special case: all-equal shares _should_ be optimized into assigning a + // constant to next_grant_share. + // Special case: all-1's shares _should_ result in the share counter + // being optimized away. + // ------------------------------------------ + // Input | arb shares | counter load value + // 0 | 1 | 0 + // 1 | 1 | 0 + wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0; + + // ------------------------------------------ + // Choose the share value corresponding to the grant. + // ------------------------------------------ + reg [SHARE_COUNTER_W - 1 : 0] next_grant_share; + always @* begin + next_grant_share = + share_0 & { SHARE_COUNTER_W {next_grant[0]} } | + share_1 & { SHARE_COUNTER_W {next_grant[1]} }; + end + + // ------------------------------------------ + // Flag to indicate first packet of an arb sequence. + // ------------------------------------------ + + // ------------------------------------------ + // Compute the next share-count value. + // ------------------------------------------ + reg [SHARE_COUNTER_W - 1 : 0] p1_share_count; + reg [SHARE_COUNTER_W - 1 : 0] share_count; + reg share_count_zero_flag; + + always @* begin + // Update the counter, but don't decrement below 0. + p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1; + end + + // ------------------------------------------ + // Update the share counter and share-counter=zero flag. + // ------------------------------------------ + always @(posedge clk or posedge reset) begin + if (reset) begin + share_count <= '0; + share_count_zero_flag <= 1'b1; + end + else begin + if (update_grant) begin + share_count <= next_grant_share; + share_count_zero_flag <= (next_grant_share == '0); + end + else if (last_cycle) begin + share_count <= p1_share_count; + share_count_zero_flag <= (p1_share_count == '0); + end + end + end + + + always @* begin + update_grant = 0; + + // ------------------------------------------ + // The pipeline delays grant by one cycle, so + // we have to calculate the update_grant signal + // one cycle ahead of time. + // + // Possible optimization: omit the first clause + // "if (!packet_in_progress & ~src_valid) ..." + // cost: one idle cycle at the the beginning of each + // grant cycle. + // benefit: save a small amount of logic. + // ------------------------------------------ + if (!packet_in_progress & !src_valid) + update_grant = 1; + if (last_cycle && share_count_zero_flag) + update_grant = 1; + end + + wire save_grant; + assign save_grant = update_grant; + assign grant = saved_grant; + + always @(posedge clk, posedge reset) begin + if (reset) + saved_grant <= '0; + else if (save_grant) + saved_grant <= next_grant; + end + + // ------------------------------------------ + // ------------------------------------------ + // Arbitrator + // ------------------------------------------ + // ------------------------------------------ + + // ------------------------------------------ + // Create a request vector that stays high during + // the packet for unpipelined arbitration. + // + // The pipelined arbitration scheme does not require + // request to be held high during the packet. + // ------------------------------------------ + reg [NUM_INPUTS - 1 : 0] prev_request; + always @(posedge clk, posedge reset) begin + if (reset) + prev_request <= '0; + else + prev_request <= request & ~(valid & eop); + end + + assign request = (PIPELINE_ARB == 1) ? valid | locked : + prev_request | valid | locked; + + + altera_merlin_arbitrator + #( + .NUM_REQUESTERS(NUM_INPUTS), + .SCHEME ("round-robin"), + .PIPELINE (1) + ) arb ( + .clk (clk), + .reset (reset), + .request (request), + .grant (next_grant), + .save_top_priority (src_valid), + .increment_top_priority (update_grant) + ); + + // ------------------------------------------ + // ------------------------------------------ + // Mux + // + // Implemented as a sum of products. + // ------------------------------------------ + // ------------------------------------------ + + assign sink0_ready = src_ready && grant[0]; + assign sink1_ready = src_ready && grant[1]; + + assign src_valid = |(grant & valid); + + always @* begin + src_payload = + sink0_payload & {PAYLOAD_W {grant[0]} } | + sink1_payload & {PAYLOAD_W {grant[1]} }; + end + + // ------------------------------------------ + // Mux Payload Mapping + // ------------------------------------------ + + assign sink0_payload = {sink0_channel,sink0_data, + sink0_startofpacket,sink0_endofpacket}; + assign sink1_payload = {sink1_channel,sink1_data, + sink1_startofpacket,sink1_endofpacket}; + + assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload; + +endmodule + + + diff --git a/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.ocp b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.ocp new file mode 100644 index 00000000..a4b7a582 Binary files /dev/null and b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.ocp differ diff --git a/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.sdc b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.sdc new file mode 100644 index 00000000..b6607ebd --- /dev/null +++ b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.sdc @@ -0,0 +1,53 @@ +# Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your +# use of Altera Corporation's design tools, logic functions and other +# software and tools, and its AMPP partner logic functions, and any +# output files any of the foregoing (including device programming or +# simulation files), and any associated documentation or information are +# expressly subject to the terms and conditions of the Altera Program +# License Subscription Agreement or other applicable license agreement, +# including, without limitation, that your use is for the sole purpose +# of programming logic devices manufactured by Altera and sold by Altera +# or its authorized distributors. Please refer to the applicable +# agreement for further details. + +#************************************************************** +# Timequest JTAG clock definition +# Uncommenting the following lines will define the JTAG +# clock in TimeQuest Timing Analyzer +#************************************************************** + +#create_clock -period 10MHz {altera_reserved_tck} +#set_clock_groups -asynchronous -group {altera_reserved_tck} + +#************************************************************** +# Set TCL Path Variables +#************************************************************** + +set system_cpu system_cpu:* +set system_cpu_oci system_cpu_nios2_oci:the_system_cpu_nios2_oci +set system_cpu_oci_break system_cpu_nios2_oci_break:the_system_cpu_nios2_oci_break +set system_cpu_ocimem system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem +set system_cpu_oci_debug system_cpu_nios2_oci_debug:the_system_cpu_nios2_oci_debug +set system_cpu_wrapper system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper +set system_cpu_jtag_tck system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck +set system_cpu_jtag_sysclk system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk +set system_cpu_oci_path [format "%s|%s" $system_cpu $system_cpu_oci] +set system_cpu_oci_break_path [format "%s|%s" $system_cpu_oci_path $system_cpu_oci_break] +set system_cpu_ocimem_path [format "%s|%s" $system_cpu_oci_path $system_cpu_ocimem] +set system_cpu_oci_debug_path [format "%s|%s" $system_cpu_oci_path $system_cpu_oci_debug] +set system_cpu_jtag_tck_path [format "%s|%s|%s" $system_cpu_oci_path $system_cpu_wrapper $system_cpu_jtag_tck] +set system_cpu_jtag_sysclk_path [format "%s|%s|%s" $system_cpu_oci_path $system_cpu_wrapper $system_cpu_jtag_sysclk] +set system_cpu_jtag_sr [format "%s|*sr" $system_cpu_jtag_tck_path] + +#************************************************************** +# Set False Paths +#************************************************************** + +set_false_path -from [get_keepers *$system_cpu_oci_break_path|break_readreg*] -to [get_keepers *$system_cpu_jtag_sr*] +set_false_path -from [get_keepers *$system_cpu_oci_debug_path|*resetlatch] -to [get_keepers *$system_cpu_jtag_sr[33]] +set_false_path -from [get_keepers *$system_cpu_oci_debug_path|monitor_ready] -to [get_keepers *$system_cpu_jtag_sr[0]] +set_false_path -from [get_keepers *$system_cpu_oci_debug_path|monitor_error] -to [get_keepers *$system_cpu_jtag_sr[34]] +set_false_path -from [get_keepers *$system_cpu_ocimem_path|*MonDReg*] -to [get_keepers *$system_cpu_jtag_sr*] +set_false_path -from *$system_cpu_jtag_sr* -to *$system_cpu_jtag_sysclk_path|*jdo* +set_false_path -from sld_hub:*|irf_reg* -to *$system_cpu_jtag_sysclk_path|ir* +set_false_path -from sld_hub:*|sld_shadow_jsm:shadow_jsm|state[1] -to *$system_cpu_oci_debug_path|monitor_go diff --git a/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v new file mode 100644 index 00000000..e79ba66a Binary files /dev/null and b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu.v differ diff --git a/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu_bht_ram.mif b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu_bht_ram.mif new file mode 100644 index 00000000..ac7dfd62 --- /dev/null +++ b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu_bht_ram.mif @@ -0,0 +1,266 @@ +WIDTH=2; +DEPTH=256; + +ADDRESS_RADIX=HEX; +DATA_RADIX=HEX; + +CONTENT BEGIN + +00 : 0; +01 : 1; +02 : 1; +03 : 0; +04 : 2; +05 : 2; +06 : 2; +07 : 1; +08 : 3; +09 : 0; +0a : 2; +0b : 1; +0c : 1; +0d : 3; +0e : 3; +0f : 1; +10 : 0; +11 : 2; +12 : 2; +13 : 1; +14 : 1; +15 : 3; +16 : 0; +17 : 3; +18 : 0; +19 : 2; +1a : 3; +1b : 3; +1c : 1; +1d : 1; +1e : 3; +1f : 1; +20 : 2; +21 : 3; +22 : 3; +23 : 0; +24 : 3; +25 : 0; +26 : 2; +27 : 2; +28 : 2; +29 : 2; +2a : 1; +2b : 1; +2c : 1; +2d : 0; +2e : 3; +2f : 2; +30 : 2; +31 : 1; +32 : 2; +33 : 2; +34 : 1; +35 : 2; +36 : 2; +37 : 3; +38 : 0; +39 : 3; +3a : 1; +3b : 0; +3c : 0; +3d : 0; +3e : 1; +3f : 3; +40 : 1; +41 : 2; +42 : 1; +43 : 3; +44 : 2; +45 : 0; +46 : 2; +47 : 3; +48 : 2; +49 : 1; +4a : 0; +4b : 3; +4c : 2; +4d : 1; +4e : 3; +4f : 3; +50 : 3; +51 : 3; +52 : 3; +53 : 2; +54 : 0; +55 : 1; +56 : 3; +57 : 0; +58 : 1; +59 : 0; +5a : 2; +5b : 3; +5c : 2; +5d : 1; +5e : 1; +5f : 0; +60 : 1; +61 : 1; +62 : 1; +63 : 2; +64 : 1; +65 : 1; +66 : 0; +67 : 3; +68 : 0; +69 : 3; +6a : 1; +6b : 1; +6c : 0; +6d : 1; +6e : 0; +6f : 1; +70 : 2; +71 : 0; +72 : 3; +73 : 3; +74 : 0; +75 : 1; +76 : 2; +77 : 1; +78 : 3; +79 : 0; +7a : 2; +7b : 3; +7c : 2; +7d : 2; +7e : 2; +7f : 2; +80 : 3; +81 : 3; +82 : 2; +83 : 3; +84 : 3; +85 : 2; +86 : 1; +87 : 1; +88 : 2; +89 : 0; +8a : 2; +8b : 1; +8c : 2; +8d : 2; +8e : 0; +8f : 0; +90 : 2; +91 : 0; +92 : 0; +93 : 1; +94 : 3; +95 : 1; +96 : 2; +97 : 3; +98 : 2; +99 : 3; +9a : 3; +9b : 2; +9c : 1; +9d : 2; +9e : 2; +9f : 2; +a0 : 3; +a1 : 1; +a2 : 0; +a3 : 3; +a4 : 1; +a5 : 0; +a6 : 2; +a7 : 3; +a8 : 2; +a9 : 0; +aa : 0; +ab : 2; +ac : 3; +ad : 0; +ae : 1; +af : 1; +b0 : 1; +b1 : 1; +b2 : 3; +b3 : 3; +b4 : 2; +b5 : 0; +b6 : 1; +b7 : 3; +b8 : 0; +b9 : 1; +ba : 0; +bb : 3; +bc : 3; +bd : 1; +be : 2; +bf : 3; +c0 : 2; +c1 : 2; +c2 : 3; +c3 : 2; +c4 : 0; +c5 : 1; +c6 : 3; +c7 : 3; +c8 : 1; +c9 : 1; +ca : 0; +cb : 3; +cc : 3; +cd : 2; +ce : 0; +cf : 1; +d0 : 3; +d1 : 3; +d2 : 1; +d3 : 2; +d4 : 3; +d5 : 3; +d6 : 1; +d7 : 3; +d8 : 1; +d9 : 1; +da : 0; +db : 1; +dc : 3; +dd : 0; +de : 2; +df : 2; +e0 : 1; +e1 : 1; +e2 : 1; +e3 : 2; +e4 : 0; +e5 : 2; +e6 : 3; +e7 : 0; +e8 : 1; +e9 : 3; +ea : 1; +eb : 0; +ec : 0; +ed : 3; +ee : 1; +ef : 0; +f0 : 1; +f1 : 2; +f2 : 2; +f3 : 2; +f4 : 1; +f5 : 3; +f6 : 1; +f7 : 0; +f8 : 0; +f9 : 3; +fa : 0; +fb : 1; +fc : 1; +fd : 1; +fe : 0; +ff : 0; + +END; diff --git a/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu_dc_tag_ram.mif b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu_dc_tag_ram.mif new file mode 100644 index 00000000..12c66d29 --- /dev/null +++ b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu_dc_tag_ram.mif @@ -0,0 +1,138 @@ +WIDTH=16; +DEPTH=128; + +ADDRESS_RADIX=HEX; +DATA_RADIX=HEX; + +CONTENT BEGIN + +00 : ac0e; +01 : 49f5; +02 : c9a5; +03 : ea76; +04 : 05b0; +05 : 4d86; +06 : b29a; +07 : c712; +08 : 4e34; +09 : 4493; +0a : d45e; +0b : de48; +0c : 3da7; +0d : e426; +0e : 4d6a; +0f : 8937; +10 : 99b5; +11 : 9bd4; +12 : 1f8a; +13 : 5751; +14 : 8b07; +15 : e64e; +16 : b4dc; +17 : d496; +18 : 42f8; +19 : 4fe6; +1a : f1d5; +1b : 952f; +1c : a2e5; +1d : a42d; +1e : 15b1; +1f : af16; +20 : 1680; +21 : 12bc; +22 : 2e27; +23 : 6612; +24 : 8991; +25 : 3eaa; +26 : c607; +27 : a1a2; +28 : fd8b; +29 : 544d; +2a : aec3; +2b : 1a53; +2c : 25f9; +2d : 58ad; +2e : 3659; +2f : 03ec; +30 : 1476; +31 : 1865; +32 : 568c; +33 : c23b; +34 : b038; +35 : 6305; +36 : fb9e; +37 : bd8a; +38 : a259; +39 : 11d4; +3a : 806e; +3b : 3fbb; +3c : 9df3; +3d : 5264; +3e : d62b; +3f : 3814; +40 : 1858; +41 : a230; +42 : 7003; +43 : d1e6; +44 : 492e; +45 : f962; +46 : adce; +47 : cd18; +48 : 1e46; +49 : cf22; +4a : a242; +4b : 8ca4; +4c : 6748; +4d : 7c7a; +4e : 9285; +4f : 48cb; +50 : 334f; +51 : 1c07; +52 : cbae; +53 : 20c4; +54 : c53e; +55 : ef2c; +56 : de18; +57 : 4173; +58 : 81de; +59 : 0d32; +5a : a8c6; +5b : 0105; +5c : 6718; +5d : e7ad; +5e : c15e; +5f : f65b; +60 : fbeb; +61 : 690a; +62 : 30e6; +63 : 130f; +64 : 6d9a; +65 : d946; +66 : e7a9; +67 : 1074; +68 : c9d7; +69 : f3aa; +6a : 9096; +6b : 183c; +6c : 0cd7; +6d : 9d14; +6e : 02d7; +6f : 3dd3; +70 : 4f63; +71 : 0412; +72 : 1fcc; +73 : 562a; +74 : c33d; +75 : c72a; +76 : ec14; +77 : 7850; +78 : 08bc; +79 : 6177; +7a : 1ce9; +7b : c11d; +7c : 2996; +7d : b07f; +7e : 9ae7; +7f : bfcb; + +END; diff --git a/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu_ic_tag_ram.mif b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu_ic_tag_ram.mif new file mode 100644 index 00000000..c6c1c6f4 --- /dev/null +++ b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu_ic_tag_ram.mif @@ -0,0 +1,266 @@ +WIDTH=21; +DEPTH=256; + +ADDRESS_RADIX=HEX; +DATA_RADIX=HEX; + +CONTENT BEGIN + +00 : 18997a; +01 : 19abaa; +02 : 159532; +03 : 1d14d1; +04 : 166193; +05 : 14c6a6; +06 : 1a090b; +07 : 03de5b; +08 : 11d930; +09 : 08bcd0; +0a : 1e2a1c; +0b : 1bae85; +0c : 111dad; +0d : 03864d; +0e : 1f6268; +0f : 001486; +10 : 01a3d8; +11 : 107af7; +12 : 139e47; +13 : 01b503; +14 : 0a976e; +15 : 049814; +16 : 00414c; +17 : 0f6471; +18 : 01dc0a; +19 : 057d48; +1a : 0ae32a; +1b : 0329f3; +1c : 04ecf4; +1d : 19dccd; +1e : 112524; +1f : 0142e9; +20 : 0b7e4b; +21 : 05bb92; +22 : 176245; +23 : 14a3c5; +24 : 1a0d94; +25 : 0f6652; +26 : 0d7c0f; +27 : 052242; +28 : 052bd5; +29 : 0dd1f4; +2a : 1d115d; +2b : 090422; +2c : 18016b; +2d : 0f9ab9; +2e : 0f0716; +2f : 1ac9b4; +30 : 1e569a; +31 : 13c6e1; +32 : 16e72f; +33 : 119932; +34 : 1eb058; +35 : 1d1dcc; +36 : 1651e1; +37 : 1b9bfb; +38 : 12f4fc; +39 : 0405d3; +3a : 084707; +3b : 0a8143; +3c : 0ce420; +3d : 0f3f3e; +3e : 0113c2; +3f : 0d2803; +40 : 1289b5; +41 : 03d16b; +42 : 1d4e57; +43 : 1841cf; +44 : 0194f7; +45 : 045c92; +46 : 0a3140; +47 : 1d6946; +48 : 1397e5; +49 : 17eada; +4a : 0553eb; +4b : 18ec01; +4c : 15b39d; +4d : 0b88af; +4e : 09a35b; +4f : 0f243e; +50 : 0f2bb4; +51 : 1a9451; +52 : 123410; +53 : 1d984d; +54 : 1d4ef4; +55 : 177fe9; +56 : 0f8b08; +57 : 1a614d; +58 : 1f2c5c; +59 : 143f90; +5a : 17a28c; +5b : 0bc774; +5c : 05dd63; +5d : 153204; +5e : 029c99; +5f : 09be0d; +60 : 1e65c9; +61 : 0b78f3; +62 : 14a43e; +63 : 18b71c; +64 : 1e9a0d; +65 : 1456db; +66 : 026be6; +67 : 169d81; +68 : 00ab06; +69 : 0205d2; +6a : 07ed1e; +6b : 1ccf12; +6c : 0e483b; +6d : 0a8e48; +6e : 1f1ef1; +6f : 1aefbf; +70 : 18335d; +71 : 03954a; +72 : 192346; +73 : 09ced6; +74 : 1e18d9; +75 : 18be57; +76 : 1b482a; +77 : 1933e3; +78 : 0f04e2; +79 : 045d11; +7a : 195865; +7b : 1da8cb; +7c : 153fe6; +7d : 04797c; +7e : 1ac8aa; +7f : 1406e5; +80 : 1785e2; +81 : 0e9551; +82 : 00775b; +83 : 0f55a3; +84 : 0a3c74; +85 : 1aa92e; +86 : 0ae6b2; +87 : 017fb0; +88 : 062a25; +89 : 0eb8c4; +8a : 1a74f6; +8b : 1070ee; +8c : 1e7f80; +8d : 188345; +8e : 08b44a; +8f : 1f6d98; +90 : 160233; +91 : 02d116; +92 : 03ed33; +93 : 13c007; +94 : 0e7f06; +95 : 1e3438; +96 : 07872e; +97 : 1fd7b0; +98 : 00d60e; +99 : 0b4953; +9a : 0c30e8; +9b : 0f5c14; +9c : 0e0c4c; +9d : 091d7b; +9e : 144a6a; +9f : 169731; +a0 : 1f8414; +a1 : 147451; +a2 : 121274; +a3 : 1de6d2; +a4 : 080eaf; +a5 : 15f210; +a6 : 02d8cc; +a7 : 0819fb; +a8 : 1993e5; +a9 : 16e20f; +aa : 0df60f; +ab : 067a65; +ac : 0a8e84; +ad : 07e7be; +ae : 056d01; +af : 1a4ca3; +b0 : 0f998e; +b1 : 0429d8; +b2 : 042014; +b3 : 1f9a73; +b4 : 043ae5; +b5 : 0e1257; +b6 : 04d36e; +b7 : 09dc21; +b8 : 0b2279; +b9 : 06360a; +ba : 137db2; +bb : 087074; +bc : 07b0bd; +bd : 1d938f; +be : 173de7; +bf : 0f501e; +c0 : 00b5b8; +c1 : 0e2a2a; +c2 : 1d8af9; +c3 : 0cc881; +c4 : 021b49; +c5 : 118691; +c6 : 000db4; +c7 : 0e1d12; +c8 : 04d964; +c9 : 0e486c; +ca : 1af938; +cb : 0acf20; +cc : 0d1384; +cd : 146245; +ce : 0f7786; +cf : 0fde20; +d0 : 006fec; +d1 : 1c94e8; +d2 : 05147b; +d3 : 1bc333; +d4 : 1faa84; +d5 : 05b117; +d6 : 0e3ae0; +d7 : 1de629; +d8 : 0f12a5; +d9 : 0d0e32; +da : 090918; +db : 084dc6; +dc : 123bcc; +dd : 00266c; +de : 1e34c8; +df : 07eaf3; +e0 : 0ae3b1; +e1 : 04038a; +e2 : 1f2ac1; +e3 : 1bc60d; +e4 : 1af787; +e5 : 1d0437; +e6 : 03a9c3; +e7 : 0c952d; +e8 : 093a36; +e9 : 0fda4b; +ea : 1e99fb; +eb : 1fdb10; +ec : 0d6365; +ed : 127123; +ee : 08e985; +ef : 1ae0fa; +f0 : 0e82a4; +f1 : 08d349; +f2 : 076873; +f3 : 1c65ec; +f4 : 03b66b; +f5 : 092214; +f6 : 0816ff; +f7 : 098322; +f8 : 026649; +f9 : 0ee26e; +fa : 1214c8; +fb : 147131; +fc : 060793; +fd : 18689f; +fe : 1d69fa; +ff : 1e340b; + +END; diff --git a/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu_jtag_debug_module_sysclk.v b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu_jtag_debug_module_sysclk.v new file mode 100644 index 00000000..5e95910c --- /dev/null +++ b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu_jtag_debug_module_sysclk.v @@ -0,0 +1,181 @@ +//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module system_cpu_jtag_debug_module_sysclk ( + // inputs: + clk, + ir_in, + sr, + vs_udr, + vs_uir, + + // outputs: + jdo, + take_action_break_a, + take_action_break_b, + take_action_break_c, + take_action_ocimem_a, + take_action_ocimem_b, + take_action_tracectrl, + take_action_tracemem_a, + take_action_tracemem_b, + take_no_action_break_a, + take_no_action_break_b, + take_no_action_break_c, + take_no_action_ocimem_a, + take_no_action_tracemem_a + ) +; + + output [ 37: 0] jdo; + output take_action_break_a; + output take_action_break_b; + output take_action_break_c; + output take_action_ocimem_a; + output take_action_ocimem_b; + output take_action_tracectrl; + output take_action_tracemem_a; + output take_action_tracemem_b; + output take_no_action_break_a; + output take_no_action_break_b; + output take_no_action_break_c; + output take_no_action_ocimem_a; + output take_no_action_tracemem_a; + input clk; + input [ 1: 0] ir_in; + input [ 37: 0] sr; + input vs_udr; + input vs_uir; + + reg enable_action_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */; + reg [ 1: 0] ir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; + reg [ 37: 0] jdo /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */; + reg jxuir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */; + reg sync2_udr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */; + reg sync2_uir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */; + wire sync_udr; + wire sync_uir; + wire take_action_break_a; + wire take_action_break_b; + wire take_action_break_c; + wire take_action_ocimem_a; + wire take_action_ocimem_b; + wire take_action_tracectrl; + wire take_action_tracemem_a; + wire take_action_tracemem_b; + wire take_no_action_break_a; + wire take_no_action_break_b; + wire take_no_action_break_c; + wire take_no_action_ocimem_a; + wire take_no_action_tracemem_a; + wire unxunused_resetxx2; + wire unxunused_resetxx3; + reg update_jdo_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */; + assign unxunused_resetxx2 = 1'b1; + altera_std_synchronizer the_altera_std_synchronizer2 + ( + .clk (clk), + .din (vs_udr), + .dout (sync_udr), + .reset_n (unxunused_resetxx2) + ); + + defparam the_altera_std_synchronizer2.depth = 2; + + assign unxunused_resetxx3 = 1'b1; + altera_std_synchronizer the_altera_std_synchronizer3 + ( + .clk (clk), + .din (vs_uir), + .dout (sync_uir), + .reset_n (unxunused_resetxx3) + ); + + defparam the_altera_std_synchronizer3.depth = 2; + + always @(posedge clk) + begin + sync2_udr <= sync_udr; + update_jdo_strobe <= sync_udr & ~sync2_udr; + enable_action_strobe <= update_jdo_strobe; + sync2_uir <= sync_uir; + jxuir <= sync_uir & ~sync2_uir; + end + + + assign take_action_ocimem_a = enable_action_strobe && (ir == 2'b00) && + ~jdo[35] && jdo[34]; + + assign take_no_action_ocimem_a = enable_action_strobe && (ir == 2'b00) && + ~jdo[35] && ~jdo[34]; + + assign take_action_ocimem_b = enable_action_strobe && (ir == 2'b00) && + jdo[35]; + + assign take_action_tracemem_a = enable_action_strobe && (ir == 2'b01) && + ~jdo[37] && + jdo[36]; + + assign take_no_action_tracemem_a = enable_action_strobe && (ir == 2'b01) && + ~jdo[37] && + ~jdo[36]; + + assign take_action_tracemem_b = enable_action_strobe && (ir == 2'b01) && + jdo[37]; + + assign take_action_break_a = enable_action_strobe && (ir == 2'b10) && + ~jdo[36] && + jdo[37]; + + assign take_no_action_break_a = enable_action_strobe && (ir == 2'b10) && + ~jdo[36] && + ~jdo[37]; + + assign take_action_break_b = enable_action_strobe && (ir == 2'b10) && + jdo[36] && ~jdo[35] && + jdo[37]; + + assign take_no_action_break_b = enable_action_strobe && (ir == 2'b10) && + jdo[36] && ~jdo[35] && + ~jdo[37]; + + assign take_action_break_c = enable_action_strobe && (ir == 2'b10) && + jdo[36] && jdo[35] && + jdo[37]; + + assign take_no_action_break_c = enable_action_strobe && (ir == 2'b10) && + jdo[36] && jdo[35] && + ~jdo[37]; + + assign take_action_tracectrl = enable_action_strobe && (ir == 2'b11) && + jdo[15]; + + always @(posedge clk) + begin + if (jxuir) + ir <= ir_in; + if (update_jdo_strobe) + jdo <= sr; + end + + + +endmodule + diff --git a/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu_jtag_debug_module_tck.v b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu_jtag_debug_module_tck.v new file mode 100644 index 00000000..cd5030b4 --- /dev/null +++ b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu_jtag_debug_module_tck.v @@ -0,0 +1,239 @@ +//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module system_cpu_jtag_debug_module_tck ( + // inputs: + MonDReg, + break_readreg, + dbrk_hit0_latch, + dbrk_hit1_latch, + dbrk_hit2_latch, + dbrk_hit3_latch, + debugack, + ir_in, + jtag_state_rti, + monitor_error, + monitor_ready, + reset_n, + resetlatch, + tck, + tdi, + tracemem_on, + tracemem_trcdata, + tracemem_tw, + trc_im_addr, + trc_on, + trc_wrap, + trigbrktype, + trigger_state_1, + vs_cdr, + vs_sdr, + vs_uir, + + // outputs: + ir_out, + jrst_n, + sr, + st_ready_test_idle, + tdo + ) +; + + output [ 1: 0] ir_out; + output jrst_n; + output [ 37: 0] sr; + output st_ready_test_idle; + output tdo; + input [ 31: 0] MonDReg; + input [ 31: 0] break_readreg; + input dbrk_hit0_latch; + input dbrk_hit1_latch; + input dbrk_hit2_latch; + input dbrk_hit3_latch; + input debugack; + input [ 1: 0] ir_in; + input jtag_state_rti; + input monitor_error; + input monitor_ready; + input reset_n; + input resetlatch; + input tck; + input tdi; + input tracemem_on; + input [ 35: 0] tracemem_trcdata; + input tracemem_tw; + input [ 6: 0] trc_im_addr; + input trc_on; + input trc_wrap; + input trigbrktype; + input trigger_state_1; + input vs_cdr; + input vs_sdr; + input vs_uir; + + reg [ 2: 0] DRsize /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; + wire debugack_sync; + reg [ 1: 0] ir_out; + wire jrst_n; + wire monitor_ready_sync; + reg [ 37: 0] sr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */; + wire st_ready_test_idle; + wire tdo; + wire unxcomplemented_resetxx0; + wire unxcomplemented_resetxx1; + always @(posedge tck) + begin + if (vs_cdr) + case (ir_in) + + 2'b00: begin + sr[35] <= debugack_sync; + sr[34] <= monitor_error; + sr[33] <= resetlatch; + sr[32 : 1] <= MonDReg; + sr[0] <= monitor_ready_sync; + end // 2'b00 + + 2'b01: begin + sr[35 : 0] <= tracemem_trcdata; + sr[37] <= tracemem_tw; + sr[36] <= tracemem_on; + end // 2'b01 + + 2'b10: begin + sr[37] <= trigger_state_1; + sr[36] <= dbrk_hit3_latch; + sr[35] <= dbrk_hit2_latch; + sr[34] <= dbrk_hit1_latch; + sr[33] <= dbrk_hit0_latch; + sr[32 : 1] <= break_readreg; + sr[0] <= trigbrktype; + end // 2'b10 + + 2'b11: begin + sr[15 : 12] <= 1'b0; + sr[11 : 2] <= trc_im_addr; + sr[1] <= trc_wrap; + sr[0] <= trc_on; + end // 2'b11 + + endcase // ir_in + if (vs_sdr) + case (DRsize) + + 3'b000: begin + sr <= {tdi, sr[37 : 2], tdi}; + end // 3'b000 + + 3'b001: begin + sr <= {tdi, sr[37 : 9], tdi, sr[7 : 1]}; + end // 3'b001 + + 3'b010: begin + sr <= {tdi, sr[37 : 17], tdi, sr[15 : 1]}; + end // 3'b010 + + 3'b011: begin + sr <= {tdi, sr[37 : 33], tdi, sr[31 : 1]}; + end // 3'b011 + + 3'b100: begin + sr <= {tdi, sr[37], tdi, sr[35 : 1]}; + end // 3'b100 + + 3'b101: begin + sr <= {tdi, sr[37 : 1]}; + end // 3'b101 + + default: begin + sr <= {tdi, sr[37 : 2], tdi}; + end // default + + endcase // DRsize + if (vs_uir) + case (ir_in) + + 2'b00: begin + DRsize <= 3'b100; + end // 2'b00 + + 2'b01: begin + DRsize <= 3'b101; + end // 2'b01 + + 2'b10: begin + DRsize <= 3'b101; + end // 2'b10 + + 2'b11: begin + DRsize <= 3'b010; + end // 2'b11 + + endcase // ir_in + end + + + assign tdo = sr[0]; + assign st_ready_test_idle = jtag_state_rti; + assign unxcomplemented_resetxx0 = jrst_n; + altera_std_synchronizer the_altera_std_synchronizer + ( + .clk (tck), + .din (debugack), + .dout (debugack_sync), + .reset_n (unxcomplemented_resetxx0) + ); + + defparam the_altera_std_synchronizer.depth = 2; + + assign unxcomplemented_resetxx1 = jrst_n; + altera_std_synchronizer the_altera_std_synchronizer1 + ( + .clk (tck), + .din (monitor_ready), + .dout (monitor_ready_sync), + .reset_n (unxcomplemented_resetxx1) + ); + + defparam the_altera_std_synchronizer1.depth = 2; + + always @(posedge tck or negedge jrst_n) + begin + if (jrst_n == 0) + ir_out <= 2'b0; + else + ir_out <= {debugack_sync, monitor_ready_sync}; + end + + + +//synthesis translate_off +//////////////// SIMULATION-ONLY CONTENTS + assign jrst_n = reset_n; + +//////////////// END SIMULATION-ONLY CONTENTS + +//synthesis translate_on +//synthesis read_comments_as_HDL on +// assign jrst_n = 1; +//synthesis read_comments_as_HDL off + +endmodule + diff --git a/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v new file mode 100644 index 00000000..f2644249 --- /dev/null +++ b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v @@ -0,0 +1,233 @@ +//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module system_cpu_jtag_debug_module_wrapper ( + // inputs: + MonDReg, + break_readreg, + clk, + dbrk_hit0_latch, + dbrk_hit1_latch, + dbrk_hit2_latch, + dbrk_hit3_latch, + debugack, + monitor_error, + monitor_ready, + reset_n, + resetlatch, + tracemem_on, + tracemem_trcdata, + tracemem_tw, + trc_im_addr, + trc_on, + trc_wrap, + trigbrktype, + trigger_state_1, + + // outputs: + jdo, + jrst_n, + st_ready_test_idle, + take_action_break_a, + take_action_break_b, + take_action_break_c, + take_action_ocimem_a, + take_action_ocimem_b, + take_action_tracectrl, + take_action_tracemem_a, + take_action_tracemem_b, + take_no_action_break_a, + take_no_action_break_b, + take_no_action_break_c, + take_no_action_ocimem_a, + take_no_action_tracemem_a + ) +; + + output [ 37: 0] jdo; + output jrst_n; + output st_ready_test_idle; + output take_action_break_a; + output take_action_break_b; + output take_action_break_c; + output take_action_ocimem_a; + output take_action_ocimem_b; + output take_action_tracectrl; + output take_action_tracemem_a; + output take_action_tracemem_b; + output take_no_action_break_a; + output take_no_action_break_b; + output take_no_action_break_c; + output take_no_action_ocimem_a; + output take_no_action_tracemem_a; + input [ 31: 0] MonDReg; + input [ 31: 0] break_readreg; + input clk; + input dbrk_hit0_latch; + input dbrk_hit1_latch; + input dbrk_hit2_latch; + input dbrk_hit3_latch; + input debugack; + input monitor_error; + input monitor_ready; + input reset_n; + input resetlatch; + input tracemem_on; + input [ 35: 0] tracemem_trcdata; + input tracemem_tw; + input [ 6: 0] trc_im_addr; + input trc_on; + input trc_wrap; + input trigbrktype; + input trigger_state_1; + + wire [ 37: 0] jdo; + wire jrst_n; + wire [ 37: 0] sr; + wire st_ready_test_idle; + wire take_action_break_a; + wire take_action_break_b; + wire take_action_break_c; + wire take_action_ocimem_a; + wire take_action_ocimem_b; + wire take_action_tracectrl; + wire take_action_tracemem_a; + wire take_action_tracemem_b; + wire take_no_action_break_a; + wire take_no_action_break_b; + wire take_no_action_break_c; + wire take_no_action_ocimem_a; + wire take_no_action_tracemem_a; + wire vji_cdr; + wire [ 1: 0] vji_ir_in; + wire [ 1: 0] vji_ir_out; + wire vji_rti; + wire vji_sdr; + wire vji_tck; + wire vji_tdi; + wire vji_tdo; + wire vji_udr; + wire vji_uir; + //Change the sld_virtual_jtag_basic's defparams to + //switch between a regular Nios II or an internally embedded Nios II. + //For a regular Nios II, sld_mfg_id = 70, sld_type_id = 34. + //For an internally embedded Nios II, slf_mfg_id = 110, sld_type_id = 135. + system_cpu_jtag_debug_module_tck the_system_cpu_jtag_debug_module_tck + ( + .MonDReg (MonDReg), + .break_readreg (break_readreg), + .dbrk_hit0_latch (dbrk_hit0_latch), + .dbrk_hit1_latch (dbrk_hit1_latch), + .dbrk_hit2_latch (dbrk_hit2_latch), + .dbrk_hit3_latch (dbrk_hit3_latch), + .debugack (debugack), + .ir_in (vji_ir_in), + .ir_out (vji_ir_out), + .jrst_n (jrst_n), + .jtag_state_rti (vji_rti), + .monitor_error (monitor_error), + .monitor_ready (monitor_ready), + .reset_n (reset_n), + .resetlatch (resetlatch), + .sr (sr), + .st_ready_test_idle (st_ready_test_idle), + .tck (vji_tck), + .tdi (vji_tdi), + .tdo (vji_tdo), + .tracemem_on (tracemem_on), + .tracemem_trcdata (tracemem_trcdata), + .tracemem_tw (tracemem_tw), + .trc_im_addr (trc_im_addr), + .trc_on (trc_on), + .trc_wrap (trc_wrap), + .trigbrktype (trigbrktype), + .trigger_state_1 (trigger_state_1), + .vs_cdr (vji_cdr), + .vs_sdr (vji_sdr), + .vs_uir (vji_uir) + ); + + system_cpu_jtag_debug_module_sysclk the_system_cpu_jtag_debug_module_sysclk + ( + .clk (clk), + .ir_in (vji_ir_in), + .jdo (jdo), + .sr (sr), + .take_action_break_a (take_action_break_a), + .take_action_break_b (take_action_break_b), + .take_action_break_c (take_action_break_c), + .take_action_ocimem_a (take_action_ocimem_a), + .take_action_ocimem_b (take_action_ocimem_b), + .take_action_tracectrl (take_action_tracectrl), + .take_action_tracemem_a (take_action_tracemem_a), + .take_action_tracemem_b (take_action_tracemem_b), + .take_no_action_break_a (take_no_action_break_a), + .take_no_action_break_b (take_no_action_break_b), + .take_no_action_break_c (take_no_action_break_c), + .take_no_action_ocimem_a (take_no_action_ocimem_a), + .take_no_action_tracemem_a (take_no_action_tracemem_a), + .vs_udr (vji_udr), + .vs_uir (vji_uir) + ); + + +//synthesis translate_off +//////////////// SIMULATION-ONLY CONTENTS + assign vji_tck = 1'b0; + assign vji_tdi = 1'b0; + assign vji_sdr = 1'b0; + assign vji_cdr = 1'b0; + assign vji_rti = 1'b0; + assign vji_uir = 1'b0; + assign vji_udr = 1'b0; + assign vji_ir_in = 2'b0; + +//////////////// END SIMULATION-ONLY CONTENTS + +//synthesis translate_on +//synthesis read_comments_as_HDL on +// sld_virtual_jtag_basic system_cpu_jtag_debug_module_phy +// ( +// .ir_in (vji_ir_in), +// .ir_out (vji_ir_out), +// .jtag_state_rti (vji_rti), +// .tck (vji_tck), +// .tdi (vji_tdi), +// .tdo (vji_tdo), +// .virtual_state_cdr (vji_cdr), +// .virtual_state_sdr (vji_sdr), +// .virtual_state_udr (vji_udr), +// .virtual_state_uir (vji_uir) +// ); +// +// defparam system_cpu_jtag_debug_module_phy.sld_auto_instance_index = "YES", +// system_cpu_jtag_debug_module_phy.sld_instance_index = 0, +// system_cpu_jtag_debug_module_phy.sld_ir_width = 2, +// system_cpu_jtag_debug_module_phy.sld_mfg_id = 70, +// system_cpu_jtag_debug_module_phy.sld_sim_action = "", +// system_cpu_jtag_debug_module_phy.sld_sim_n_scan = 0, +// system_cpu_jtag_debug_module_phy.sld_sim_total_length = 0, +// system_cpu_jtag_debug_module_phy.sld_type_id = 34, +// system_cpu_jtag_debug_module_phy.sld_version = 3; +// +//synthesis read_comments_as_HDL off + +endmodule + diff --git a/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu_mult_cell.v b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu_mult_cell.v new file mode 100644 index 00000000..67d9ab7a --- /dev/null +++ b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu_mult_cell.v @@ -0,0 +1,132 @@ +//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module system_cpu_mult_cell ( + // inputs: + A_mul_src1, + A_mul_src2, + clk, + reset_n, + + // outputs: + A_mul_cell_result + ) +; + + output [ 31: 0] A_mul_cell_result; + input [ 31: 0] A_mul_src1; + input [ 31: 0] A_mul_src2; + input clk; + input reset_n; + + wire [ 31: 0] A_mul_cell_result; + wire [ 31: 0] A_mul_cell_result_part_1; + wire [ 15: 0] A_mul_cell_result_part_2; + wire mul_clr; + assign mul_clr = ~reset_n; + altmult_add the_altmult_add_part_1 + ( + .aclr0 (mul_clr), + .clock0 (clk), + .dataa (A_mul_src1[15 : 0]), + .datab (A_mul_src2[15 : 0]), + .ena0 (1'b1), + .result (A_mul_cell_result_part_1) + ); + + defparam the_altmult_add_part_1.addnsub_multiplier_pipeline_aclr1 = "ACLR0", + the_altmult_add_part_1.addnsub_multiplier_pipeline_register1 = "CLOCK0", + the_altmult_add_part_1.addnsub_multiplier_register1 = "UNREGISTERED", + the_altmult_add_part_1.dedicated_multiplier_circuitry = "YES", + the_altmult_add_part_1.input_register_a0 = "UNREGISTERED", + the_altmult_add_part_1.input_register_b0 = "UNREGISTERED", + the_altmult_add_part_1.input_source_a0 = "DATAA", + the_altmult_add_part_1.input_source_b0 = "DATAB", + the_altmult_add_part_1.intended_device_family = "CYCLONEIVE", + the_altmult_add_part_1.lpm_type = "altmult_add", + the_altmult_add_part_1.multiplier1_direction = "ADD", + the_altmult_add_part_1.multiplier_aclr0 = "ACLR0", + the_altmult_add_part_1.multiplier_register0 = "CLOCK0", + the_altmult_add_part_1.number_of_multipliers = 1, + the_altmult_add_part_1.output_register = "UNREGISTERED", + the_altmult_add_part_1.port_addnsub1 = "PORT_UNUSED", + the_altmult_add_part_1.port_addnsub3 = "PORT_UNUSED", + the_altmult_add_part_1.port_signa = "PORT_UNUSED", + the_altmult_add_part_1.port_signb = "PORT_UNUSED", + the_altmult_add_part_1.representation_a = "UNSIGNED", + the_altmult_add_part_1.representation_b = "UNSIGNED", + the_altmult_add_part_1.signed_pipeline_aclr_a = "ACLR0", + the_altmult_add_part_1.signed_pipeline_aclr_b = "ACLR0", + the_altmult_add_part_1.signed_pipeline_register_a = "CLOCK0", + the_altmult_add_part_1.signed_pipeline_register_b = "CLOCK0", + the_altmult_add_part_1.signed_register_a = "UNREGISTERED", + the_altmult_add_part_1.signed_register_b = "UNREGISTERED", + the_altmult_add_part_1.width_a = 16, + the_altmult_add_part_1.width_b = 16, + the_altmult_add_part_1.width_result = 32; + + altmult_add the_altmult_add_part_2 + ( + .aclr0 (mul_clr), + .clock0 (clk), + .dataa (A_mul_src1[31 : 16]), + .datab (A_mul_src2[15 : 0]), + .ena0 (1'b1), + .result (A_mul_cell_result_part_2) + ); + + defparam the_altmult_add_part_2.addnsub_multiplier_pipeline_aclr1 = "ACLR0", + the_altmult_add_part_2.addnsub_multiplier_pipeline_register1 = "CLOCK0", + the_altmult_add_part_2.addnsub_multiplier_register1 = "UNREGISTERED", + the_altmult_add_part_2.dedicated_multiplier_circuitry = "YES", + the_altmult_add_part_2.input_register_a0 = "UNREGISTERED", + the_altmult_add_part_2.input_register_b0 = "UNREGISTERED", + the_altmult_add_part_2.input_source_a0 = "DATAA", + the_altmult_add_part_2.input_source_b0 = "DATAB", + the_altmult_add_part_2.intended_device_family = "CYCLONEIVE", + the_altmult_add_part_2.lpm_type = "altmult_add", + the_altmult_add_part_2.multiplier1_direction = "ADD", + the_altmult_add_part_2.multiplier_aclr0 = "ACLR0", + the_altmult_add_part_2.multiplier_register0 = "CLOCK0", + the_altmult_add_part_2.number_of_multipliers = 1, + the_altmult_add_part_2.output_register = "UNREGISTERED", + the_altmult_add_part_2.port_addnsub1 = "PORT_UNUSED", + the_altmult_add_part_2.port_addnsub3 = "PORT_UNUSED", + the_altmult_add_part_2.port_signa = "PORT_UNUSED", + the_altmult_add_part_2.port_signb = "PORT_UNUSED", + the_altmult_add_part_2.representation_a = "UNSIGNED", + the_altmult_add_part_2.representation_b = "UNSIGNED", + the_altmult_add_part_2.signed_pipeline_aclr_a = "ACLR0", + the_altmult_add_part_2.signed_pipeline_aclr_b = "ACLR0", + the_altmult_add_part_2.signed_pipeline_register_a = "CLOCK0", + the_altmult_add_part_2.signed_pipeline_register_b = "CLOCK0", + the_altmult_add_part_2.signed_register_a = "UNREGISTERED", + the_altmult_add_part_2.signed_register_b = "UNREGISTERED", + the_altmult_add_part_2.width_a = 16, + the_altmult_add_part_2.width_b = 16, + the_altmult_add_part_2.width_result = 16; + + assign A_mul_cell_result = {A_mul_cell_result_part_1[31 : 16] + + A_mul_cell_result_part_2, + A_mul_cell_result_part_1[15 : 0]}; + + +endmodule + diff --git a/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu_oci_test_bench.v b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu_oci_test_bench.v new file mode 100644 index 00000000..ca31cf47 --- /dev/null +++ b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu_oci_test_bench.v @@ -0,0 +1,37 @@ +//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module system_cpu_oci_test_bench ( + // inputs: + dct_buffer, + dct_count, + test_ending, + test_has_ended + ) +; + + input [ 29: 0] dct_buffer; + input [ 3: 0] dct_count; + input test_ending; + input test_has_ended; + + +endmodule + diff --git a/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu_ociram_default_contents.mif b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu_ociram_default_contents.mif new file mode 100644 index 00000000..9f2e380c --- /dev/null +++ b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu_ociram_default_contents.mif @@ -0,0 +1,269 @@ + + +WIDTH=32; +DEPTH=256; + +ADDRESS_RADIX=HEX; +DATA_RADIX=HEX; + +CONTENT BEGIN + + 00000000 : 01000020; + 00000001 : 00001A1A; + 00000002 : 00040000; + 00000003 : 00000000; + 00000004 : 20000C0D; + 00000005 : 01000000; + 00000006 : 00000000; + 00000007 : 00000000; + 00000008 : 0032E03A; + 00000009 : C800603A; + 0000000A : 00000006; + 0000000B : 003FFC06; + 0000000C : 003DA03A; + 0000000D : 003DA03A; + 0000000E : 003DA03A; + 0000000F : 003DA03A; + 00000010 : 003DA03A; + 00000011 : 003DA03A; + 00000012 : 003DA03A; + 00000013 : 003DA03A; + 00000014 : 003DA03A; + 00000015 : 003DA03A; + 00000016 : 003DA03A; + 00000017 : 003DA03A; + 00000018 : 003DA03A; + 00000019 : 003DA03A; + 0000001A : 003DA03A; + 0000001B : 003DA03A; + 0000001C : 003DA03A; + 0000001D : 003DA03A; + 0000001E : 003DA03A; + 0000001F : 003DA03A; + 00000020 : 003DA03A; + 00000021 : 003DA03A; + 00000022 : 003DA03A; + 00000023 : 003DA03A; + 00000024 : 003DA03A; + 00000025 : 003DA03A; + 00000026 : 003DA03A; + 00000027 : 003DA03A; + 00000028 : 003DA03A; + 00000029 : 003DA03A; + 0000002A : 003DA03A; + 0000002B : 003DA03A; + 0000002C : 003DA03A; + 0000002D : 003DA03A; + 0000002E : 003DA03A; + 0000002F : 003DA03A; + 00000030 : 003DA03A; + 00000031 : 003DA03A; + 00000032 : 003DA03A; + 00000033 : 003DA03A; + 00000034 : 003DA03A; + 00000035 : 003DA03A; + 00000036 : 003DA03A; + 00000037 : 003DA03A; + 00000038 : 003DA03A; + 00000039 : 003DA03A; + 0000003A : 003DA03A; + 0000003B : 003DA03A; + 0000003C : 003DA03A; + 0000003D : 003DA03A; + 0000003E : 003DA03A; + 0000003F : 003DA03A; + 00000040 : 003DA03A; + 00000041 : 003DA03A; + 00000042 : 003DA03A; + 00000043 : 003DA03A; + 00000044 : 003DA03A; + 00000045 : 003DA03A; + 00000046 : 003DA03A; + 00000047 : 003DA03A; + 00000048 : 003DA03A; + 00000049 : 003DA03A; + 0000004A : 003DA03A; + 0000004B : 003DA03A; + 0000004C : 003DA03A; + 0000004D : 003DA03A; + 0000004E : 003DA03A; + 0000004F : 003DA03A; + 00000050 : 003DA03A; + 00000051 : 003DA03A; + 00000052 : 003DA03A; + 00000053 : 003DA03A; + 00000054 : 003DA03A; + 00000055 : 003DA03A; + 00000056 : 003DA03A; + 00000057 : 003DA03A; + 00000058 : 003DA03A; + 00000059 : 003DA03A; + 0000005A : 003DA03A; + 0000005B : 003DA03A; + 0000005C : 003DA03A; + 0000005D : 003DA03A; + 0000005E : 003DA03A; + 0000005F : 003DA03A; + 00000060 : 003DA03A; + 00000061 : 003DA03A; + 00000062 : 003DA03A; + 00000063 : 003DA03A; + 00000064 : 003DA03A; + 00000065 : 003DA03A; + 00000066 : 003DA03A; + 00000067 : 003DA03A; + 00000068 : 003DA03A; + 00000069 : 003DA03A; + 0000006A : 003DA03A; + 0000006B : 003DA03A; + 0000006C : 003DA03A; + 0000006D : 003DA03A; + 0000006E : 003DA03A; + 0000006F : 003DA03A; + 00000070 : 003DA03A; + 00000071 : 003DA03A; + 00000072 : 003DA03A; + 00000073 : 003DA03A; + 00000074 : 003DA03A; + 00000075 : 003DA03A; + 00000076 : 003DA03A; + 00000077 : 003DA03A; + 00000078 : 003DA03A; + 00000079 : 003DA03A; + 0000007A : 003DA03A; + 0000007B : 003DA03A; + 0000007C : 003DA03A; + 0000007D : 003DA03A; + 0000007E : 003DA03A; + 0000007F : 003DA03A; + 00000080 : 003DA03A; + 00000081 : 003DA03A; + 00000082 : 003DA03A; + 00000083 : 003DA03A; + 00000084 : 003DA03A; + 00000085 : 003DA03A; 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+ 000000B2 : 003DA03A; + 000000B3 : 003DA03A; + 000000B4 : 003DA03A; + 000000B5 : 003DA03A; + 000000B6 : 003DA03A; + 000000B7 : 003DA03A; + 000000B8 : 003DA03A; + 000000B9 : 003DA03A; + 000000BA : 003DA03A; + 000000BB : 003DA03A; + 000000BC : 003DA03A; + 000000BD : 003DA03A; + 000000BE : 003DA03A; + 000000BF : 003DA03A; + 000000C0 : 003DA03A; + 000000C1 : 003DA03A; + 000000C2 : 003DA03A; + 000000C3 : 003DA03A; + 000000C4 : 003DA03A; + 000000C5 : 003DA03A; + 000000C6 : 003DA03A; + 000000C7 : 003DA03A; + 000000C8 : 003DA03A; + 000000C9 : 003DA03A; + 000000CA : 003DA03A; + 000000CB : 003DA03A; + 000000CC : 003DA03A; + 000000CD : 003DA03A; + 000000CE : 003DA03A; + 000000CF : 003DA03A; + 000000D0 : 003DA03A; + 000000D1 : 003DA03A; + 000000D2 : 003DA03A; + 000000D3 : 003DA03A; + 000000D4 : 003DA03A; + 000000D5 : 003DA03A; + 000000D6 : 003DA03A; + 000000D7 : 003DA03A; + 000000D8 : 003DA03A; + 000000D9 : 003DA03A; + 000000DA : 003DA03A; + 000000DB : 003DA03A; + 000000DC : 003DA03A; + 000000DD : 003DA03A; + 000000DE : 003DA03A; + 000000DF : 003DA03A; + 000000E0 : 003DA03A; + 000000E1 : 003DA03A; + 000000E2 : 003DA03A; + 000000E3 : 003DA03A; + 000000E4 : 003DA03A; + 000000E5 : 003DA03A; + 000000E6 : 003DA03A; + 000000E7 : 003DA03A; + 000000E8 : 003DA03A; + 000000E9 : 003DA03A; + 000000EA : 003DA03A; + 000000EB : 003DA03A; + 000000EC : 003DA03A; + 000000ED : 003DA03A; + 000000EE : 003DA03A; + 000000EF : 003DA03A; + 000000F0 : 003DA03A; + 000000F1 : 003DA03A; + 000000F2 : 003DA03A; + 000000F3 : 003DA03A; + 000000F4 : 003DA03A; + 000000F5 : 003DA03A; + 000000F6 : 003DA03A; + 000000F7 : 003DA03A; + 000000F8 : 003DA03A; + 000000F9 : 003DA03A; + 000000FA : 003DA03A; + 000000FB : 003DA03A; + 000000FC : 003DA03A; + 000000FD : 003DA03A; + 000000FE : 003DA03A; + 000000FF : 003DA03A; + +END; + diff --git a/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu_rf_ram_a.mif b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu_rf_ram_a.mif new file mode 100644 index 00000000..644013af --- /dev/null +++ b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu_rf_ram_a.mif @@ -0,0 +1,42 @@ +WIDTH=32; +DEPTH=32; + +ADDRESS_RADIX=HEX; +DATA_RADIX=HEX; + +CONTENT BEGIN + +00 : deadbeef; +01 : deadbeef; +02 : deadbeef; +03 : deadbeef; +04 : deadbeef; +05 : deadbeef; +06 : deadbeef; +07 : deadbeef; +08 : deadbeef; +09 : deadbeef; +0a : deadbeef; +0b : deadbeef; +0c : deadbeef; +0d : deadbeef; +0e : deadbeef; +0f : deadbeef; +10 : deadbeef; +11 : deadbeef; +12 : deadbeef; +13 : deadbeef; +14 : deadbeef; +15 : deadbeef; +16 : deadbeef; +17 : deadbeef; +18 : deadbeef; +19 : deadbeef; +1a : deadbeef; +1b : deadbeef; +1c : deadbeef; +1d : deadbeef; +1e : deadbeef; +1f : deadbeef; + +END; diff --git a/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu_rf_ram_b.mif b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu_rf_ram_b.mif new file mode 100644 index 00000000..644013af --- /dev/null +++ b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu_rf_ram_b.mif @@ -0,0 +1,42 @@ +WIDTH=32; +DEPTH=32; + +ADDRESS_RADIX=HEX; +DATA_RADIX=HEX; + +CONTENT BEGIN + +00 : deadbeef; +01 : deadbeef; +02 : deadbeef; +03 : deadbeef; +04 : deadbeef; +05 : deadbeef; +06 : deadbeef; +07 : deadbeef; +08 : deadbeef; +09 : deadbeef; +0a : deadbeef; +0b : deadbeef; +0c : deadbeef; +0d : deadbeef; +0e : deadbeef; +0f : deadbeef; +10 : deadbeef; +11 : deadbeef; +12 : deadbeef; +13 : deadbeef; +14 : deadbeef; +15 : deadbeef; +16 : deadbeef; +17 : deadbeef; +18 : deadbeef; +19 : deadbeef; +1a : deadbeef; +1b : deadbeef; +1c : deadbeef; +1d : deadbeef; +1e : deadbeef; +1f : deadbeef; + +END; diff --git a/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu_test_bench.v b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu_test_bench.v new file mode 100644 index 00000000..81c1fa30 --- /dev/null +++ b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_cpu_test_bench.v @@ -0,0 +1,796 @@ +//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module system_cpu_test_bench ( + // inputs: + A_bstatus_reg, + A_cmp_result, + A_ctrl_exception, + A_ctrl_ld_non_bypass, + A_dst_regnum, + A_en, + A_estatus_reg, + A_ienable_reg, + A_ipending_reg, + A_iw, + A_mem_byte_en, + A_op_hbreak, + A_op_intr, + A_pcb, + A_st_data, + A_status_reg, + A_valid, + A_wr_data_unfiltered, + A_wr_dst_reg, + E_add_br_to_taken_history_unfiltered, + E_logic_result, + E_valid, + M_bht_ptr_unfiltered, + M_bht_wr_data_unfiltered, + M_bht_wr_en_unfiltered, + M_mem_baddr, + M_target_pcb, + M_valid, + W_dst_regnum, + W_iw, + W_iw_op, + W_iw_opx, + W_pcb, + W_valid, + W_vinst, + W_wr_dst_reg, + clk, + d_address, + d_byteenable, + d_read, + d_write, + i_address, + i_read, + i_readdatavalid, + reset_n, + + // outputs: + A_wr_data_filtered, + E_add_br_to_taken_history_filtered, + E_src1_eq_src2, + M_bht_ptr_filtered, + M_bht_wr_data_filtered, + M_bht_wr_en_filtered, + test_has_ended + ) +; + + output [ 31: 0] A_wr_data_filtered; + output E_add_br_to_taken_history_filtered; + output E_src1_eq_src2; + output [ 7: 0] M_bht_ptr_filtered; + output [ 1: 0] M_bht_wr_data_filtered; + output M_bht_wr_en_filtered; + output test_has_ended; + input [ 31: 0] A_bstatus_reg; + input A_cmp_result; + input A_ctrl_exception; + input A_ctrl_ld_non_bypass; + input [ 4: 0] A_dst_regnum; + input A_en; + input [ 31: 0] A_estatus_reg; + input [ 31: 0] A_ienable_reg; + input [ 31: 0] A_ipending_reg; + input [ 31: 0] A_iw; + input [ 3: 0] A_mem_byte_en; + input A_op_hbreak; + input A_op_intr; + input [ 25: 0] A_pcb; + input [ 31: 0] A_st_data; + input [ 31: 0] A_status_reg; + input A_valid; + input [ 31: 0] A_wr_data_unfiltered; + input A_wr_dst_reg; + input E_add_br_to_taken_history_unfiltered; + input [ 31: 0] E_logic_result; + input E_valid; + input [ 7: 0] M_bht_ptr_unfiltered; + input [ 1: 0] M_bht_wr_data_unfiltered; + input M_bht_wr_en_unfiltered; + input [ 25: 0] M_mem_baddr; + input [ 25: 0] M_target_pcb; + input M_valid; + input [ 4: 0] W_dst_regnum; + input [ 31: 0] W_iw; + input [ 5: 0] W_iw_op; + input [ 5: 0] W_iw_opx; + input [ 25: 0] W_pcb; + input W_valid; + input [ 55: 0] W_vinst; + input W_wr_dst_reg; + input clk; + input [ 25: 0] d_address; + input [ 3: 0] d_byteenable; + input d_read; + input d_write; + input [ 25: 0] i_address; + input i_read; + input i_readdatavalid; + input reset_n; + + reg [ 25: 0] A_mem_baddr; + reg [ 25: 0] A_target_pcb; + wire [ 31: 0] A_wr_data_filtered; + wire A_wr_data_unfiltered_0_is_x; + wire A_wr_data_unfiltered_10_is_x; + wire A_wr_data_unfiltered_11_is_x; + wire A_wr_data_unfiltered_12_is_x; + wire A_wr_data_unfiltered_13_is_x; + wire A_wr_data_unfiltered_14_is_x; + wire A_wr_data_unfiltered_15_is_x; + wire A_wr_data_unfiltered_16_is_x; + wire A_wr_data_unfiltered_17_is_x; + wire A_wr_data_unfiltered_18_is_x; + wire A_wr_data_unfiltered_19_is_x; + wire A_wr_data_unfiltered_1_is_x; + wire A_wr_data_unfiltered_20_is_x; + wire A_wr_data_unfiltered_21_is_x; + wire A_wr_data_unfiltered_22_is_x; + wire A_wr_data_unfiltered_23_is_x; + wire A_wr_data_unfiltered_24_is_x; + wire A_wr_data_unfiltered_25_is_x; + wire A_wr_data_unfiltered_26_is_x; + wire A_wr_data_unfiltered_27_is_x; + wire A_wr_data_unfiltered_28_is_x; + wire A_wr_data_unfiltered_29_is_x; + wire A_wr_data_unfiltered_2_is_x; + wire A_wr_data_unfiltered_30_is_x; + wire A_wr_data_unfiltered_31_is_x; + wire A_wr_data_unfiltered_3_is_x; + wire A_wr_data_unfiltered_4_is_x; + wire A_wr_data_unfiltered_5_is_x; + wire A_wr_data_unfiltered_6_is_x; + wire A_wr_data_unfiltered_7_is_x; + wire A_wr_data_unfiltered_8_is_x; + wire A_wr_data_unfiltered_9_is_x; + wire E_add_br_to_taken_history_filtered; + wire E_src1_eq_src2; + wire [ 7: 0] M_bht_ptr_filtered; + wire [ 1: 0] M_bht_wr_data_filtered; + wire M_bht_wr_en_filtered; + wire W_op_add; + wire W_op_addi; + wire W_op_and; + wire W_op_andhi; + wire W_op_andi; + wire W_op_beq; + wire W_op_bge; + wire W_op_bgeu; + wire W_op_blt; + wire W_op_bltu; + wire W_op_bne; + wire W_op_br; + wire W_op_break; + wire W_op_bret; + wire W_op_call; + wire W_op_callr; + wire W_op_cmpeq; + wire W_op_cmpeqi; + wire W_op_cmpge; + wire W_op_cmpgei; + wire W_op_cmpgeu; + wire W_op_cmpgeui; + wire W_op_cmplt; + wire W_op_cmplti; + wire W_op_cmpltu; + wire W_op_cmpltui; + wire W_op_cmpne; + wire W_op_cmpnei; + wire W_op_crst; + wire W_op_custom; + wire W_op_div; + wire W_op_divu; + wire W_op_eret; + wire W_op_flushd; + wire W_op_flushda; + wire W_op_flushi; + wire W_op_flushp; + wire W_op_hbreak; + wire W_op_initd; + wire W_op_initda; + wire W_op_initi; + wire W_op_intr; + wire W_op_jmp; + wire W_op_jmpi; + wire W_op_ldb; + wire W_op_ldbio; + wire W_op_ldbu; + wire W_op_ldbuio; + wire W_op_ldh; + wire W_op_ldhio; + wire W_op_ldhu; + wire W_op_ldhuio; + wire W_op_ldl; + wire W_op_ldw; + wire W_op_ldwio; + wire W_op_mul; + wire W_op_muli; + wire W_op_mulxss; + wire W_op_mulxsu; + wire W_op_mulxuu; + wire W_op_nextpc; + wire W_op_nor; + wire W_op_opx; + wire W_op_or; + wire W_op_orhi; + wire W_op_ori; + wire W_op_rdctl; + wire W_op_rdprs; + wire W_op_ret; + wire W_op_rol; + wire W_op_roli; + wire W_op_ror; + wire W_op_rsv02; + wire W_op_rsv09; + wire W_op_rsv10; + wire W_op_rsv17; + wire W_op_rsv18; + wire W_op_rsv25; + wire W_op_rsv26; + wire W_op_rsv33; + wire W_op_rsv34; + wire W_op_rsv41; + wire W_op_rsv42; + wire W_op_rsv49; + wire W_op_rsv57; + wire W_op_rsv61; + wire W_op_rsv62; + wire W_op_rsv63; + wire W_op_rsvx00; + wire W_op_rsvx10; + wire W_op_rsvx15; + wire W_op_rsvx17; + wire W_op_rsvx21; + wire W_op_rsvx25; + wire W_op_rsvx33; + wire W_op_rsvx34; + wire W_op_rsvx35; + wire W_op_rsvx42; + wire W_op_rsvx43; + wire W_op_rsvx44; + wire W_op_rsvx47; + wire W_op_rsvx50; + wire W_op_rsvx51; + wire W_op_rsvx55; + wire W_op_rsvx56; + wire W_op_rsvx60; + wire W_op_rsvx63; + wire W_op_sll; + wire W_op_slli; + wire W_op_sra; + wire W_op_srai; + wire W_op_srl; + wire W_op_srli; + wire W_op_stb; + wire W_op_stbio; + wire W_op_stc; + wire W_op_sth; + wire W_op_sthio; + wire W_op_stw; + wire W_op_stwio; + wire W_op_sub; + wire W_op_sync; + wire W_op_trap; + wire W_op_wrctl; + wire W_op_wrprs; + wire W_op_xor; + wire W_op_xorhi; + wire W_op_xori; + wire test_has_ended; + assign W_op_call = W_iw_op == 0; + assign W_op_jmpi = W_iw_op == 1; + assign W_op_ldbu = W_iw_op == 3; + assign W_op_addi = W_iw_op == 4; + assign W_op_stb = W_iw_op == 5; + assign W_op_br = W_iw_op == 6; + assign W_op_ldb = W_iw_op == 7; + assign W_op_cmpgei = W_iw_op == 8; + assign W_op_ldhu = W_iw_op == 11; + assign W_op_andi = W_iw_op == 12; + assign W_op_sth = W_iw_op == 13; + assign W_op_bge = W_iw_op == 14; + assign W_op_ldh = W_iw_op == 15; + assign W_op_cmplti = W_iw_op == 16; + assign W_op_initda = W_iw_op == 19; + assign W_op_ori = W_iw_op == 20; + assign W_op_stw = W_iw_op == 21; + assign W_op_blt = W_iw_op == 22; + assign W_op_ldw = W_iw_op == 23; + assign W_op_cmpnei = W_iw_op == 24; + assign W_op_flushda = W_iw_op == 27; + assign W_op_xori = W_iw_op == 28; + assign W_op_stc = W_iw_op == 29; + assign W_op_bne = W_iw_op == 30; + assign W_op_ldl = W_iw_op == 31; + assign W_op_cmpeqi = W_iw_op == 32; + assign W_op_ldbuio = W_iw_op == 35; + assign W_op_muli = W_iw_op == 36; + assign W_op_stbio = W_iw_op == 37; + assign W_op_beq = W_iw_op == 38; + assign W_op_ldbio = W_iw_op == 39; + assign W_op_cmpgeui = W_iw_op == 40; + assign W_op_ldhuio = W_iw_op == 43; + assign W_op_andhi = W_iw_op == 44; + assign W_op_sthio = W_iw_op == 45; + assign W_op_bgeu = W_iw_op == 46; + assign W_op_ldhio = W_iw_op == 47; + assign W_op_cmpltui = W_iw_op == 48; + assign W_op_initd = W_iw_op == 51; + assign W_op_orhi = W_iw_op == 52; + assign W_op_stwio = W_iw_op == 53; + assign W_op_bltu = W_iw_op == 54; + assign W_op_ldwio = W_iw_op == 55; + assign W_op_rdprs = W_iw_op == 56; + assign W_op_flushd = W_iw_op == 59; + assign W_op_xorhi = W_iw_op == 60; + assign W_op_rsv02 = W_iw_op == 2; + assign W_op_rsv09 = W_iw_op == 9; + assign W_op_rsv10 = W_iw_op == 10; + assign W_op_rsv17 = W_iw_op == 17; + assign W_op_rsv18 = W_iw_op == 18; + assign W_op_rsv25 = W_iw_op == 25; + assign W_op_rsv26 = W_iw_op == 26; + assign W_op_rsv33 = W_iw_op == 33; + assign W_op_rsv34 = W_iw_op == 34; + assign W_op_rsv41 = W_iw_op == 41; + assign W_op_rsv42 = W_iw_op == 42; + assign W_op_rsv49 = W_iw_op == 49; + assign W_op_rsv57 = W_iw_op == 57; + assign W_op_rsv61 = W_iw_op == 61; + assign W_op_rsv62 = W_iw_op == 62; + assign W_op_rsv63 = W_iw_op == 63; + assign W_op_eret = W_op_opx & (W_iw_opx == 1); + assign W_op_roli = W_op_opx & (W_iw_opx == 2); + assign W_op_rol = W_op_opx & (W_iw_opx == 3); + assign W_op_flushp = W_op_opx & (W_iw_opx == 4); + assign W_op_ret = W_op_opx & (W_iw_opx == 5); + assign W_op_nor = W_op_opx & (W_iw_opx == 6); + assign W_op_mulxuu = W_op_opx & (W_iw_opx == 7); + assign W_op_cmpge = W_op_opx & (W_iw_opx == 8); + assign W_op_bret = W_op_opx & (W_iw_opx == 9); + assign W_op_ror = W_op_opx & (W_iw_opx == 11); + assign W_op_flushi = W_op_opx & (W_iw_opx == 12); + assign W_op_jmp = W_op_opx & (W_iw_opx == 13); + assign W_op_and = W_op_opx & (W_iw_opx == 14); + assign W_op_cmplt = W_op_opx & (W_iw_opx == 16); + assign W_op_slli = W_op_opx & (W_iw_opx == 18); + assign W_op_sll = W_op_opx & (W_iw_opx == 19); + assign W_op_wrprs = W_op_opx & (W_iw_opx == 20); + assign W_op_or = W_op_opx & (W_iw_opx == 22); + assign W_op_mulxsu = W_op_opx & (W_iw_opx == 23); + assign W_op_cmpne = W_op_opx & (W_iw_opx == 24); + assign W_op_srli = W_op_opx & (W_iw_opx == 26); + assign W_op_srl = W_op_opx & (W_iw_opx == 27); + assign W_op_nextpc = W_op_opx & (W_iw_opx == 28); + assign W_op_callr = W_op_opx & (W_iw_opx == 29); + assign W_op_xor = W_op_opx & (W_iw_opx == 30); + assign W_op_mulxss = W_op_opx & (W_iw_opx == 31); + assign W_op_cmpeq = W_op_opx & (W_iw_opx == 32); + assign W_op_divu = W_op_opx & (W_iw_opx == 36); + assign W_op_div = W_op_opx & (W_iw_opx == 37); + assign W_op_rdctl = W_op_opx & (W_iw_opx == 38); + assign W_op_mul = W_op_opx & (W_iw_opx == 39); + assign W_op_cmpgeu = W_op_opx & (W_iw_opx == 40); + assign W_op_initi = W_op_opx & (W_iw_opx == 41); + assign W_op_trap = W_op_opx & (W_iw_opx == 45); + assign W_op_wrctl = W_op_opx & (W_iw_opx == 46); + assign W_op_cmpltu = W_op_opx & (W_iw_opx == 48); + assign W_op_add = W_op_opx & (W_iw_opx == 49); + assign W_op_break = W_op_opx & (W_iw_opx == 52); + assign W_op_hbreak = W_op_opx & (W_iw_opx == 53); + assign W_op_sync = W_op_opx & (W_iw_opx == 54); + assign W_op_sub = W_op_opx & (W_iw_opx == 57); + assign W_op_srai = W_op_opx & (W_iw_opx == 58); + assign W_op_sra = W_op_opx & (W_iw_opx == 59); + assign W_op_intr = W_op_opx & (W_iw_opx == 61); + assign W_op_crst = W_op_opx & (W_iw_opx == 62); + assign W_op_rsvx00 = W_op_opx & (W_iw_opx == 0); + assign W_op_rsvx10 = W_op_opx & (W_iw_opx == 10); + assign W_op_rsvx15 = W_op_opx & (W_iw_opx == 15); + assign W_op_rsvx17 = W_op_opx & (W_iw_opx == 17); + assign W_op_rsvx21 = W_op_opx & (W_iw_opx == 21); + assign W_op_rsvx25 = W_op_opx & (W_iw_opx == 25); + assign W_op_rsvx33 = W_op_opx & (W_iw_opx == 33); + assign W_op_rsvx34 = W_op_opx & (W_iw_opx == 34); + assign W_op_rsvx35 = W_op_opx & (W_iw_opx == 35); + assign W_op_rsvx42 = W_op_opx & (W_iw_opx == 42); + assign W_op_rsvx43 = W_op_opx & (W_iw_opx == 43); + assign W_op_rsvx44 = W_op_opx & (W_iw_opx == 44); + assign W_op_rsvx47 = W_op_opx & (W_iw_opx == 47); + assign W_op_rsvx50 = W_op_opx & (W_iw_opx == 50); + assign W_op_rsvx51 = W_op_opx & (W_iw_opx == 51); + assign W_op_rsvx55 = W_op_opx & (W_iw_opx == 55); + assign W_op_rsvx56 = W_op_opx & (W_iw_opx == 56); + assign W_op_rsvx60 = W_op_opx & (W_iw_opx == 60); + assign W_op_rsvx63 = W_op_opx & (W_iw_opx == 63); + assign W_op_opx = W_iw_op == 58; + assign W_op_custom = W_iw_op == 50; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + A_target_pcb <= 0; + else if (A_en) + A_target_pcb <= M_target_pcb; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + A_mem_baddr <= 0; + else if (A_en) + A_mem_baddr <= M_mem_baddr; + end + + + assign E_src1_eq_src2 = E_logic_result == 0; + //Propagating 'X' data bits + assign E_add_br_to_taken_history_filtered = E_add_br_to_taken_history_unfiltered; + + //Propagating 'X' data bits + assign M_bht_wr_en_filtered = M_bht_wr_en_unfiltered; + + //Propagating 'X' data bits + assign M_bht_wr_data_filtered = M_bht_wr_data_unfiltered; + + //Propagating 'X' data bits + assign M_bht_ptr_filtered = M_bht_ptr_unfiltered; + + assign test_has_ended = 1'b0; + +//synthesis translate_off +//////////////// SIMULATION-ONLY CONTENTS + //Clearing 'X' data bits + assign A_wr_data_unfiltered_0_is_x = ^(A_wr_data_unfiltered[0]) === 1'bx; + + assign A_wr_data_filtered[0] = (A_wr_data_unfiltered_0_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[0]; + assign A_wr_data_unfiltered_1_is_x = ^(A_wr_data_unfiltered[1]) === 1'bx; + assign A_wr_data_filtered[1] = (A_wr_data_unfiltered_1_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[1]; + assign A_wr_data_unfiltered_2_is_x = ^(A_wr_data_unfiltered[2]) === 1'bx; + assign A_wr_data_filtered[2] = (A_wr_data_unfiltered_2_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[2]; + assign A_wr_data_unfiltered_3_is_x = ^(A_wr_data_unfiltered[3]) === 1'bx; + assign A_wr_data_filtered[3] = (A_wr_data_unfiltered_3_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[3]; + assign A_wr_data_unfiltered_4_is_x = ^(A_wr_data_unfiltered[4]) === 1'bx; + assign A_wr_data_filtered[4] = (A_wr_data_unfiltered_4_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[4]; + assign A_wr_data_unfiltered_5_is_x = ^(A_wr_data_unfiltered[5]) === 1'bx; + assign A_wr_data_filtered[5] = (A_wr_data_unfiltered_5_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[5]; + assign A_wr_data_unfiltered_6_is_x = ^(A_wr_data_unfiltered[6]) === 1'bx; + assign A_wr_data_filtered[6] = (A_wr_data_unfiltered_6_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[6]; + assign A_wr_data_unfiltered_7_is_x = ^(A_wr_data_unfiltered[7]) === 1'bx; + assign A_wr_data_filtered[7] = (A_wr_data_unfiltered_7_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[7]; + assign A_wr_data_unfiltered_8_is_x = ^(A_wr_data_unfiltered[8]) === 1'bx; + assign A_wr_data_filtered[8] = (A_wr_data_unfiltered_8_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[8]; + assign A_wr_data_unfiltered_9_is_x = ^(A_wr_data_unfiltered[9]) === 1'bx; + assign A_wr_data_filtered[9] = (A_wr_data_unfiltered_9_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[9]; + assign A_wr_data_unfiltered_10_is_x = ^(A_wr_data_unfiltered[10]) === 1'bx; + assign A_wr_data_filtered[10] = (A_wr_data_unfiltered_10_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[10]; + assign A_wr_data_unfiltered_11_is_x = ^(A_wr_data_unfiltered[11]) === 1'bx; + assign A_wr_data_filtered[11] = (A_wr_data_unfiltered_11_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[11]; + assign A_wr_data_unfiltered_12_is_x = ^(A_wr_data_unfiltered[12]) === 1'bx; + assign A_wr_data_filtered[12] = (A_wr_data_unfiltered_12_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[12]; + assign A_wr_data_unfiltered_13_is_x = ^(A_wr_data_unfiltered[13]) === 1'bx; + assign A_wr_data_filtered[13] = (A_wr_data_unfiltered_13_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[13]; + assign A_wr_data_unfiltered_14_is_x = ^(A_wr_data_unfiltered[14]) === 1'bx; + assign A_wr_data_filtered[14] = (A_wr_data_unfiltered_14_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[14]; + assign A_wr_data_unfiltered_15_is_x = ^(A_wr_data_unfiltered[15]) === 1'bx; + assign A_wr_data_filtered[15] = (A_wr_data_unfiltered_15_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[15]; + assign A_wr_data_unfiltered_16_is_x = ^(A_wr_data_unfiltered[16]) === 1'bx; + assign A_wr_data_filtered[16] = (A_wr_data_unfiltered_16_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[16]; + assign A_wr_data_unfiltered_17_is_x = ^(A_wr_data_unfiltered[17]) === 1'bx; + assign A_wr_data_filtered[17] = (A_wr_data_unfiltered_17_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[17]; + assign A_wr_data_unfiltered_18_is_x = ^(A_wr_data_unfiltered[18]) === 1'bx; + assign A_wr_data_filtered[18] = (A_wr_data_unfiltered_18_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[18]; + assign A_wr_data_unfiltered_19_is_x = ^(A_wr_data_unfiltered[19]) === 1'bx; + assign A_wr_data_filtered[19] = (A_wr_data_unfiltered_19_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[19]; + assign A_wr_data_unfiltered_20_is_x = ^(A_wr_data_unfiltered[20]) === 1'bx; + assign A_wr_data_filtered[20] = (A_wr_data_unfiltered_20_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[20]; + assign A_wr_data_unfiltered_21_is_x = ^(A_wr_data_unfiltered[21]) === 1'bx; + assign A_wr_data_filtered[21] = (A_wr_data_unfiltered_21_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[21]; + assign A_wr_data_unfiltered_22_is_x = ^(A_wr_data_unfiltered[22]) === 1'bx; + assign A_wr_data_filtered[22] = (A_wr_data_unfiltered_22_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[22]; + assign A_wr_data_unfiltered_23_is_x = ^(A_wr_data_unfiltered[23]) === 1'bx; + assign A_wr_data_filtered[23] = (A_wr_data_unfiltered_23_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[23]; + assign A_wr_data_unfiltered_24_is_x = ^(A_wr_data_unfiltered[24]) === 1'bx; + assign A_wr_data_filtered[24] = (A_wr_data_unfiltered_24_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[24]; + assign A_wr_data_unfiltered_25_is_x = ^(A_wr_data_unfiltered[25]) === 1'bx; + assign A_wr_data_filtered[25] = (A_wr_data_unfiltered_25_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[25]; + assign A_wr_data_unfiltered_26_is_x = ^(A_wr_data_unfiltered[26]) === 1'bx; + assign A_wr_data_filtered[26] = (A_wr_data_unfiltered_26_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[26]; + assign A_wr_data_unfiltered_27_is_x = ^(A_wr_data_unfiltered[27]) === 1'bx; + assign A_wr_data_filtered[27] = (A_wr_data_unfiltered_27_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[27]; + assign A_wr_data_unfiltered_28_is_x = ^(A_wr_data_unfiltered[28]) === 1'bx; + assign A_wr_data_filtered[28] = (A_wr_data_unfiltered_28_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[28]; + assign A_wr_data_unfiltered_29_is_x = ^(A_wr_data_unfiltered[29]) === 1'bx; + assign A_wr_data_filtered[29] = (A_wr_data_unfiltered_29_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[29]; + assign A_wr_data_unfiltered_30_is_x = ^(A_wr_data_unfiltered[30]) === 1'bx; + assign A_wr_data_filtered[30] = (A_wr_data_unfiltered_30_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[30]; + assign A_wr_data_unfiltered_31_is_x = ^(A_wr_data_unfiltered[31]) === 1'bx; + assign A_wr_data_filtered[31] = (A_wr_data_unfiltered_31_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[31]; + always @(posedge clk) + begin + if (reset_n) + if (^(W_wr_dst_reg) === 1'bx) + begin + $write("%0d ns: ERROR: system_cpu_test_bench/W_wr_dst_reg is 'x'\n", $time); + $stop; + end + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + begin + end + else if (W_wr_dst_reg) + if (^(W_dst_regnum) === 1'bx) + begin + $write("%0d ns: ERROR: system_cpu_test_bench/W_dst_regnum is 'x'\n", $time); + $stop; + end + end + + + always @(posedge clk) + begin + if (reset_n) + if (^(W_valid) === 1'bx) + begin + $write("%0d ns: ERROR: system_cpu_test_bench/W_valid is 'x'\n", $time); + $stop; + end + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + begin + end + else if (W_valid) + if (^(W_pcb) === 1'bx) + begin + $write("%0d ns: ERROR: system_cpu_test_bench/W_pcb is 'x'\n", $time); + $stop; + end + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + begin + end + else if (W_valid) + if (^(W_iw) === 1'bx) + begin + $write("%0d ns: ERROR: system_cpu_test_bench/W_iw is 'x'\n", $time); + $stop; + end + end + + + always @(posedge clk) + begin + if (reset_n) + if (^(A_en) === 1'bx) + begin + $write("%0d ns: ERROR: system_cpu_test_bench/A_en is 'x'\n", $time); + $stop; + end + end + + + always @(posedge clk) + begin + if (reset_n) + if (^(E_valid) === 1'bx) + begin + $write("%0d ns: ERROR: system_cpu_test_bench/E_valid is 'x'\n", $time); + $stop; + end + end + + + always @(posedge clk) + begin + if (reset_n) + if (^(M_valid) === 1'bx) + begin + $write("%0d ns: ERROR: system_cpu_test_bench/M_valid is 'x'\n", $time); + $stop; + end + end + + + always @(posedge clk) + begin + if (reset_n) + if (^(A_valid) === 1'bx) + begin + $write("%0d ns: ERROR: system_cpu_test_bench/A_valid is 'x'\n", $time); + $stop; + end + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + begin + end + else if (A_valid & A_en & A_wr_dst_reg) + if (^(A_wr_data_unfiltered) === 1'bx) + begin + $write("%0d ns: WARNING: system_cpu_test_bench/A_wr_data_unfiltered is 'x'\n", $time); + end + end + + + always @(posedge clk) + begin + if (reset_n) + if (^(A_status_reg) === 1'bx) + begin + $write("%0d ns: ERROR: system_cpu_test_bench/A_status_reg is 'x'\n", $time); + $stop; + end + end + + + always @(posedge clk) + begin + if (reset_n) + if (^(A_estatus_reg) === 1'bx) + begin + $write("%0d ns: ERROR: system_cpu_test_bench/A_estatus_reg is 'x'\n", $time); + $stop; + end + end + + + always @(posedge clk) + begin + if (reset_n) + if (^(A_bstatus_reg) === 1'bx) + begin + $write("%0d ns: ERROR: system_cpu_test_bench/A_bstatus_reg is 'x'\n", $time); + $stop; + end + end + + + always @(posedge clk) + begin + if (reset_n) + if (^(i_read) === 1'bx) + begin + $write("%0d ns: ERROR: system_cpu_test_bench/i_read is 'x'\n", $time); + $stop; + end + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + begin + end + else if (i_read) + if (^(i_address) === 1'bx) + begin + $write("%0d ns: ERROR: system_cpu_test_bench/i_address is 'x'\n", $time); + $stop; + end + end + + + always @(posedge clk) + begin + if (reset_n) + if (^(i_readdatavalid) === 1'bx) + begin + $write("%0d ns: ERROR: system_cpu_test_bench/i_readdatavalid is 'x'\n", $time); + $stop; + end + end + + + always @(posedge clk) + begin + if (reset_n) + if (^(d_write) === 1'bx) + begin + $write("%0d ns: ERROR: system_cpu_test_bench/d_write is 'x'\n", $time); + $stop; + end + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + begin + end + else if (d_write) + if (^(d_byteenable) === 1'bx) + begin + $write("%0d ns: ERROR: system_cpu_test_bench/d_byteenable is 'x'\n", $time); + $stop; + end + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + begin + end + else if (d_write | d_read) + if (^(d_address) === 1'bx) + begin + $write("%0d ns: ERROR: system_cpu_test_bench/d_address is 'x'\n", $time); + $stop; + end + end + + + always @(posedge clk) + begin + if (reset_n) + if (^(d_read) === 1'bx) + begin + $write("%0d ns: ERROR: system_cpu_test_bench/d_read is 'x'\n", $time); + $stop; + end + end + + + + reg [31:0] trace_handle; // for $fopen + initial + begin + trace_handle = $fopen("system_cpu.tr"); + $fwrite(trace_handle, "version 3\nnumThreads 1\n"); + end + always @(posedge clk) + begin + if ((~reset_n || (A_valid & A_en)) && ~test_has_ended) + $fwrite(trace_handle, "%0d ns: %0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h\n", $time, ~reset_n, A_pcb, 0, A_op_intr, A_op_hbreak, A_iw, ~(A_op_intr | A_op_hbreak), A_wr_dst_reg, A_dst_regnum, 0, A_wr_data_filtered, A_mem_baddr, A_st_data, A_mem_byte_en, A_cmp_result, A_target_pcb, A_status_reg, A_estatus_reg, A_bstatus_reg, A_ienable_reg, A_ipending_reg, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, A_ctrl_exception ? 1 : 0, 0, 0, 0, 0); + end + + + +//////////////// END SIMULATION-ONLY CONTENTS + +//synthesis translate_on +//synthesis read_comments_as_HDL on +// +// assign A_wr_data_filtered = A_wr_data_unfiltered; +// +//synthesis read_comments_as_HDL off + +endmodule + diff --git a/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_epcs_flash_controller.v b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_epcs_flash_controller.v new file mode 100644 index 00000000..4519491f --- /dev/null +++ b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_epcs_flash_controller.v @@ -0,0 +1,558 @@ +//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +//Register map: +//addr register type +//0 read data r +//1 write data w +//2 status r/w +//3 control r/w +//4 reserved +//5 slave-enable r/w +//6 end-of-packet-value r/w +//INPUT_CLOCK: 100000000 +//ISMASTER: 1 +//DATABITS: 8 +//TARGETCLOCK: 20000000 +//NUMSLAVES: 1 +//CPOL: 0 +//CPHA: 0 +//LSBFIRST: 0 +//EXTRADELAY: 0 +//TARGETSSDELAY: 0.0001 + +module system_epcs_flash_controller_sub ( + // inputs: + MISO, + clk, + data_from_cpu, + epcs_select, + mem_addr, + read_n, + reset_n, + write_n, + + // outputs: + MOSI, + SCLK, + SS_n, + data_to_cpu, + dataavailable, + endofpacket, + irq, + readyfordata + ) +; + + output MOSI; + output SCLK; + output SS_n; + output [ 15: 0] data_to_cpu; + output dataavailable; + output endofpacket; + output irq; + output readyfordata; + input MISO; + input clk; + input [ 15: 0] data_from_cpu; + input epcs_select; + input [ 2: 0] mem_addr; + input read_n; + input reset_n; + input write_n; + + wire E; + reg EOP; + reg MISO_reg; + wire MOSI; + reg ROE; + reg RRDY; + wire SCLK; + reg SCLK_reg; + reg SSO_reg; + wire SS_n; + wire TMT; + reg TOE; + wire TRDY; + wire control_wr_strobe; + reg data_rd_strobe; + reg [ 15: 0] data_to_cpu; + reg data_wr_strobe; + wire dataavailable; + wire ds_MISO; + wire enableSS; + wire endofpacket; + reg [ 15: 0] endofpacketvalue_reg; + wire endofpacketvalue_wr_strobe; + wire [ 10: 0] epcs_control; + reg [ 15: 0] epcs_slave_select_holding_reg; + reg [ 15: 0] epcs_slave_select_reg; + wire [ 10: 0] epcs_status; + reg iEOP_reg; + reg iE_reg; + reg iROE_reg; + reg iRRDY_reg; + reg iTMT_reg; + reg iTOE_reg; + reg iTRDY_reg; + wire irq; + reg irq_reg; + wire p1_data_rd_strobe; + wire [ 15: 0] p1_data_to_cpu; + wire p1_data_wr_strobe; + wire p1_rd_strobe; + wire [ 1: 0] p1_slowcount; + wire p1_wr_strobe; + reg rd_strobe; + wire readyfordata; + reg [ 7: 0] rx_holding_reg; + reg [ 7: 0] shift_reg; + wire slaveselect_wr_strobe; + wire slowclock; + reg [ 1: 0] slowcount; + reg [ 4: 0] state; + reg stateZero; + wire status_wr_strobe; + reg transmitting; + reg tx_holding_primed; + reg [ 7: 0] tx_holding_reg; + reg wr_strobe; + wire write_shift_reg; + wire write_tx_holding; + //epcs_control_port, which is an e_avalon_slave + assign p1_rd_strobe = ~rd_strobe & epcs_select & ~read_n; + // Read is a two-cycle event. + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + rd_strobe <= 0; + else + rd_strobe <= p1_rd_strobe; + end + + + assign p1_data_rd_strobe = p1_rd_strobe & (mem_addr == 0); + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + data_rd_strobe <= 0; + else + data_rd_strobe <= p1_data_rd_strobe; + end + + + assign p1_wr_strobe = ~wr_strobe & epcs_select & ~write_n; + // Write is a two-cycle event. + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + wr_strobe <= 0; + else + wr_strobe <= p1_wr_strobe; + end + + + assign p1_data_wr_strobe = p1_wr_strobe & (mem_addr == 1); + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + data_wr_strobe <= 0; + else + data_wr_strobe <= p1_data_wr_strobe; + end + + + assign control_wr_strobe = wr_strobe & (mem_addr == 3); + assign status_wr_strobe = wr_strobe & (mem_addr == 2); + assign slaveselect_wr_strobe = wr_strobe & (mem_addr == 5); + assign endofpacketvalue_wr_strobe = wr_strobe & (mem_addr == 6); + assign TMT = ~transmitting & ~tx_holding_primed; + assign E = ROE | TOE; + assign epcs_status = {EOP, E, RRDY, TRDY, TMT, TOE, ROE, 3'b0}; + // Streaming data ready for pickup. + assign dataavailable = RRDY; + + // Ready to accept streaming data. + assign readyfordata = TRDY; + + // Endofpacket condition detected. + assign endofpacket = EOP; + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + begin + iEOP_reg <= 0; + iE_reg <= 0; + iRRDY_reg <= 0; + iTRDY_reg <= 0; + iTMT_reg <= 0; + iTOE_reg <= 0; + iROE_reg <= 0; + SSO_reg <= 0; + end + else if (control_wr_strobe) + begin + iEOP_reg <= data_from_cpu[9]; + iE_reg <= data_from_cpu[8]; + iRRDY_reg <= data_from_cpu[7]; + iTRDY_reg <= data_from_cpu[6]; + iTMT_reg <= data_from_cpu[5]; + iTOE_reg <= data_from_cpu[4]; + iROE_reg <= data_from_cpu[3]; + SSO_reg <= data_from_cpu[10]; + end + end + + + assign epcs_control = {SSO_reg, iEOP_reg, iE_reg, iRRDY_reg, iTRDY_reg, 1'b0, iTOE_reg, iROE_reg, 3'b0}; + // IRQ output. + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + irq_reg <= 0; + else + irq_reg <= (EOP & iEOP_reg) | ((TOE | ROE) & iE_reg) | (RRDY & iRRDY_reg) | (TRDY & iTRDY_reg) | (TOE & iTOE_reg) | (ROE & iROE_reg); + end + + + assign irq = irq_reg; + // Slave select register. + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + epcs_slave_select_reg <= 1; + else if (write_shift_reg || control_wr_strobe & data_from_cpu[10] & ~SSO_reg) + epcs_slave_select_reg <= epcs_slave_select_holding_reg; + end + + + // Slave select holding register. + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + epcs_slave_select_holding_reg <= 1; + else if (slaveselect_wr_strobe) + epcs_slave_select_holding_reg <= data_from_cpu; + end + + + // slowclock is active once every 3 system clock pulses. + assign slowclock = slowcount == 2'h2; + + assign p1_slowcount = ({2 {(transmitting && !slowclock)}} & (slowcount + 1)) | + ({2 {(~((transmitting && !slowclock)))}} & 0); + + // Divide counter for SPI clock. + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + slowcount <= 0; + else + slowcount <= p1_slowcount; + end + + + // End-of-packet value register. + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + endofpacketvalue_reg <= 0; + else if (endofpacketvalue_wr_strobe) + endofpacketvalue_reg <= data_from_cpu; + end + + + assign p1_data_to_cpu = ((mem_addr == 2))? epcs_status : + ((mem_addr == 3))? epcs_control : + ((mem_addr == 6))? endofpacketvalue_reg : + ((mem_addr == 5))? epcs_slave_select_reg : + rx_holding_reg; + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + data_to_cpu <= 0; + else + // Data to cpu. + data_to_cpu <= p1_data_to_cpu; + + end + + + // 'state' counts from 0 to 17. + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + begin + state <= 0; + stateZero <= 1; + end + else if (transmitting & slowclock) + begin + stateZero <= state == 17; + if (state == 17) + state <= 0; + else + state <= state + 1; + end + end + + + assign enableSS = transmitting & ~stateZero; + assign MOSI = shift_reg[7]; + assign SS_n = (enableSS | SSO_reg) ? ~epcs_slave_select_reg : {1 {1'b1} }; + assign SCLK = SCLK_reg; + // As long as there's an empty spot somewhere, + //it's safe to write data. + assign TRDY = ~(transmitting & tx_holding_primed); + + // Enable write to tx_holding_register. + assign write_tx_holding = data_wr_strobe & TRDY; + + // Enable write to shift register. + assign write_shift_reg = tx_holding_primed & ~transmitting; + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + begin + shift_reg <= 0; + rx_holding_reg <= 0; + EOP <= 0; + RRDY <= 0; + ROE <= 0; + TOE <= 0; + tx_holding_reg <= 0; + tx_holding_primed <= 0; + transmitting <= 0; + SCLK_reg <= 0; + MISO_reg <= 0; + end + else + begin + if (write_tx_holding) + begin + tx_holding_reg <= data_from_cpu; + tx_holding_primed <= 1; + end + if (data_wr_strobe & ~TRDY) + // You wrote when I wasn't ready. + TOE <= 1; + + // EOP must be updated by the last (2nd) cycle of access. + if ((p1_data_rd_strobe && (rx_holding_reg == endofpacketvalue_reg)) || (p1_data_wr_strobe && (data_from_cpu[7 : 0] == endofpacketvalue_reg))) + EOP <= 1; + if (write_shift_reg) + begin + shift_reg <= tx_holding_reg; + transmitting <= 1; + end + if (write_shift_reg & ~write_tx_holding) + // Clear tx_holding_primed + tx_holding_primed <= 0; + + if (data_rd_strobe) + // On data read, clear the RRDY bit. + RRDY <= 0; + + if (status_wr_strobe) + begin + // On status write, clear all status bits (ignore the data). + EOP <= 0; + + RRDY <= 0; + ROE <= 0; + TOE <= 0; + end + if (slowclock) + begin + if (state == 17) + begin + transmitting <= 0; + RRDY <= 1; + rx_holding_reg <= shift_reg; + SCLK_reg <= 0; + if (RRDY) + ROE <= 1; + end + else if (state != 0) + if (transmitting) + SCLK_reg <= ~SCLK_reg; + if (SCLK_reg ^ 0 ^ 0) + begin + if (1) + shift_reg <= {shift_reg[6 : 0], MISO_reg}; + end + else + MISO_reg <= ds_MISO; + end + end + end + + + assign ds_MISO = MISO; + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module system_epcs_flash_controller ( + // inputs: + address, + chipselect, + clk, + data0, + read_n, + reset_n, + write_n, + writedata, + + // outputs: + dataavailable, + dclk, + endofpacket, + irq, + readdata, + readyfordata, + sce, + sdo + ) +; + + parameter INIT_FILE = "system_epcs_flash_controller_boot_rom.hex"; + + + output dataavailable; + output dclk; + output endofpacket; + output irq; + output [ 31: 0] readdata; + output readyfordata; + output sce; + output sdo; + input [ 8: 0] address; + input chipselect; + input clk; + input data0; + input read_n; + input reset_n; + input write_n; + input [ 31: 0] writedata; + + wire MISO; + wire MOSI; + wire SCLK; + wire SS_n; + wire [ 15: 0] data_from_cpu; + wire [ 15: 0] data_to_cpu; + wire dataavailable; + wire dclk; + wire endofpacket; + wire epcs_select; + wire irq; + wire [ 2: 0] mem_addr; + wire [ 31: 0] readdata; + wire readyfordata; + wire [ 31: 0] rom_readdata; + wire sce; + wire sdo; + system_epcs_flash_controller_sub the_system_epcs_flash_controller_sub + ( + .MISO (MISO), + .MOSI (MOSI), + .SCLK (SCLK), + .SS_n (SS_n), + .clk (clk), + .data_from_cpu (data_from_cpu), + .data_to_cpu (data_to_cpu), + .dataavailable (dataavailable), + .endofpacket (endofpacket), + .epcs_select (epcs_select), + .irq (irq), + .mem_addr (mem_addr), + .read_n (read_n), + .readyfordata (readyfordata), + .reset_n (reset_n), + .write_n (write_n) + ); + + //epcs_control_port, which is an e_avalon_slave + assign dclk = SCLK; + assign sce = SS_n; + assign sdo = MOSI; + assign MISO = data0; + assign epcs_select = chipselect && (address[8] ); + assign mem_addr = address; + assign data_from_cpu = writedata; + assign readdata = epcs_select ? data_to_cpu : rom_readdata; + +//synthesis translate_off +//////////////// SIMULATION-ONLY CONTENTS + altsyncram the_boot_copier_rom + ( + .address_a (address[7 : 0]), + .clock0 (clk), + .q_a (rom_readdata) + ); + + defparam the_boot_copier_rom.byte_size = 8, + the_boot_copier_rom.init_file = INIT_FILE, + the_boot_copier_rom.lpm_type = "altsyncram", + the_boot_copier_rom.numwords_a = 256, + the_boot_copier_rom.operation_mode = "ROM", + the_boot_copier_rom.outdata_reg_a = "UNREGISTERED", + the_boot_copier_rom.read_during_write_mode_mixed_ports = "DONT_CARE", + the_boot_copier_rom.width_a = 32, + the_boot_copier_rom.widthad_a = 8; + + +//////////////// END SIMULATION-ONLY CONTENTS + +//synthesis translate_on +//synthesis read_comments_as_HDL on +// altsyncram the_boot_copier_rom +// ( +// .address_a (address[7 : 0]), +// .clock0 (clk), +// .q_a (rom_readdata) +// ); +// +// defparam the_boot_copier_rom.byte_size = 8, +// the_boot_copier_rom.init_file = "system_epcs_flash_controller_boot_rom_synth.hex", +// the_boot_copier_rom.lpm_type = "altsyncram", +// the_boot_copier_rom.numwords_a = 256, +// the_boot_copier_rom.operation_mode = "ROM", +// the_boot_copier_rom.outdata_reg_a = "UNREGISTERED", +// the_boot_copier_rom.read_during_write_mode_mixed_ports = "DONT_CARE", +// the_boot_copier_rom.width_a = 32, +// the_boot_copier_rom.widthad_a = 8; +// +//synthesis read_comments_as_HDL off + +endmodule + diff --git a/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_epcs_flash_controller_boot_rom_synth.hex b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_epcs_flash_controller_boot_rom_synth.hex new file mode 100644 index 00000000..778300ab --- /dev/null +++ b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_epcs_flash_controller_boot_rom_synth.hex @@ -0,0 +1,258 @@ +:020000020000fc +:040000000001703a51 +:0400010004c00074c3 +:040002009801483adf +:040003009cfff80462 +:04000400983ffd1e06 +:040005000000203a9d +:04000600002ee03aae +:04000700000080066f +:04000800017fffc4b1 +:04000900002ee03aab +:04000a000000660686 +:04000b003007883af8 +:04000c00002ee03aa8 +:04000d000000630686 +:04000e003009883af3 +:04000f0018000426ab +:04001000197fff262f +:04001100002ee03aa3 +:0400120000000806dc +:04001300003ff506af +:04001400002ee03aa0 +:0400150000002906b8 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a/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_id_router.sv b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_id_router.sv new file mode 100644 index 00000000..1bce0b65 --- /dev/null +++ b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_id_router.sv @@ -0,0 +1,182 @@ +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/12.1sp1/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2012/10/10 $ +// $Author: swbranch $ + +// ------------------------------------------------------- +// Merlin Router +// +// Asserts the appropriate one-hot encoded channel based on +// either (a) the address or (b) the dest id. The DECODER_TYPE +// parameter controls this behaviour. 0 means address decoder, +// 1 means dest id decoder. +// +// In the case of (a), it also sets the destination id. +// ------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module system_id_router_default_decode + #( + parameter DEFAULT_CHANNEL = 0, + DEFAULT_DESTID = 0 + ) + (output [90 - 87 : 0] default_destination_id, + output [11-1 : 0] default_src_channel + ); + + assign default_destination_id = + DEFAULT_DESTID[90 - 87 : 0]; + generate begin : default_decode + if (DEFAULT_CHANNEL == -1) + assign default_src_channel = '0; + else + assign default_src_channel = 11'b1 << DEFAULT_CHANNEL; + end + endgenerate + +endmodule + + +module system_id_router +( + // ------------------- + // Clock & Reset + // ------------------- + input clk, + input reset, + + // ------------------- + // Command Sink (Input) + // ------------------- + input sink_valid, + input [101-1 : 0] sink_data, + input sink_startofpacket, + input sink_endofpacket, + output sink_ready, + + // ------------------- + // Command Source (Output) + // ------------------- + output src_valid, + output reg [101-1 : 0] src_data, + output reg [11-1 : 0] src_channel, + output src_startofpacket, + output src_endofpacket, + input src_ready +); + + // ------------------------------------------------------- + // Local parameters and variables + // ------------------------------------------------------- + localparam PKT_ADDR_H = 61; + localparam PKT_ADDR_L = 36; + localparam PKT_DEST_ID_H = 90; + localparam PKT_DEST_ID_L = 87; + localparam ST_DATA_W = 101; + localparam ST_CHANNEL_W = 11; + localparam DECODER_TYPE = 1; + + localparam PKT_TRANS_WRITE = 64; + localparam PKT_TRANS_READ = 65; + + localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1; + localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1; + + + + + // ------------------------------------------------------- + // Figure out the number of bits to mask off for each slave span + // during address decoding + // ------------------------------------------------------- + // ------------------------------------------------------- + // Work out which address bits are significant based on the + // address range of the slaves. If the required width is too + // large or too small, we use the address field width instead. + // ------------------------------------------------------- + localparam ADDR_RANGE = 64'h0; + localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE); + localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) || + (RANGE_ADDR_WIDTH == 0) ? + PKT_ADDR_H : + PKT_ADDR_L + RANGE_ADDR_WIDTH - 1; + localparam RG = RANGE_ADDR_WIDTH-1; + + reg [PKT_DEST_ID_W-1 : 0] destid; + + // ------------------------------------------------------- + // Pass almost everything through, untouched + // ------------------------------------------------------- + assign sink_ready = src_ready; + assign src_valid = sink_valid; + assign src_startofpacket = sink_startofpacket; + assign src_endofpacket = sink_endofpacket; + + wire [PKT_DEST_ID_W-1:0] default_destid; + wire [11-1 : 0] default_src_channel; + + + + + system_id_router_default_decode the_default_decode( + .default_destination_id (default_destid), + .default_src_channel (default_src_channel) + ); + + always @* begin + src_data = sink_data; + src_channel = default_src_channel; + + // -------------------------------------------------- + // DestinationID Decoder + // Sets the channel based on the destination ID. + // -------------------------------------------------- + destid = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L]; + + + if (destid == 0 ) begin + src_channel = 11'b01; + end + if (destid == 1 ) begin + src_channel = 11'b10; + end + + +end + + + // -------------------------------------------------- + // Ceil(log2()) function + // -------------------------------------------------- + function integer log2ceil; + input reg[65:0] val; + reg [65:0] i; + + begin + i = 1; + log2ceil = 0; + + while (i < val) begin + log2ceil = log2ceil + 1; + i = i << 1; + end + end + endfunction + +endmodule + + diff --git a/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_id_router_001.sv b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_id_router_001.sv new file mode 100644 index 00000000..d57698fb --- /dev/null +++ b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_id_router_001.sv @@ -0,0 +1,182 @@ +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/12.1sp1/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2012/10/10 $ +// $Author: swbranch $ + +// ------------------------------------------------------- +// Merlin Router +// +// Asserts the appropriate one-hot encoded channel based on +// either (a) the address or (b) the dest id. The DECODER_TYPE +// parameter controls this behaviour. 0 means address decoder, +// 1 means dest id decoder. +// +// In the case of (a), it also sets the destination id. +// ------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module system_id_router_001_default_decode + #( + parameter DEFAULT_CHANNEL = 0, + DEFAULT_DESTID = 0 + ) + (output [72 - 69 : 0] default_destination_id, + output [11-1 : 0] default_src_channel + ); + + assign default_destination_id = + DEFAULT_DESTID[72 - 69 : 0]; + generate begin : default_decode + if (DEFAULT_CHANNEL == -1) + assign default_src_channel = '0; + else + assign default_src_channel = 11'b1 << DEFAULT_CHANNEL; + end + endgenerate + +endmodule + + +module system_id_router_001 +( + // ------------------- + // Clock & Reset + // ------------------- + input clk, + input reset, + + // ------------------- + // Command Sink (Input) + // ------------------- + input sink_valid, + input [83-1 : 0] sink_data, + input sink_startofpacket, + input sink_endofpacket, + output sink_ready, + + // ------------------- + // Command Source (Output) + // ------------------- + output src_valid, + output reg [83-1 : 0] src_data, + output reg [11-1 : 0] src_channel, + output src_startofpacket, + output src_endofpacket, + input src_ready +); + + // ------------------------------------------------------- + // Local parameters and variables + // ------------------------------------------------------- + localparam PKT_ADDR_H = 43; + localparam PKT_ADDR_L = 18; + localparam PKT_DEST_ID_H = 72; + localparam PKT_DEST_ID_L = 69; + localparam ST_DATA_W = 83; + localparam ST_CHANNEL_W = 11; + localparam DECODER_TYPE = 1; + + localparam PKT_TRANS_WRITE = 46; + localparam PKT_TRANS_READ = 47; + + localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1; + localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1; + + + + + // ------------------------------------------------------- + // Figure out the number of bits to mask off for each slave span + // during address decoding + // ------------------------------------------------------- + // ------------------------------------------------------- + // Work out which address bits are significant based on the + // address range of the slaves. If the required width is too + // large or too small, we use the address field width instead. + // ------------------------------------------------------- + localparam ADDR_RANGE = 64'h0; + localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE); + localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) || + (RANGE_ADDR_WIDTH == 0) ? + PKT_ADDR_H : + PKT_ADDR_L + RANGE_ADDR_WIDTH - 1; + localparam RG = RANGE_ADDR_WIDTH-1; + + reg [PKT_DEST_ID_W-1 : 0] destid; + + // ------------------------------------------------------- + // Pass almost everything through, untouched + // ------------------------------------------------------- + assign sink_ready = src_ready; + assign src_valid = sink_valid; + assign src_startofpacket = sink_startofpacket; + assign src_endofpacket = sink_endofpacket; + + wire [PKT_DEST_ID_W-1:0] default_destid; + wire [11-1 : 0] default_src_channel; + + + + + system_id_router_001_default_decode the_default_decode( + .default_destination_id (default_destid), + .default_src_channel (default_src_channel) + ); + + always @* begin + src_data = sink_data; + src_channel = default_src_channel; + + // -------------------------------------------------- + // DestinationID Decoder + // Sets the channel based on the destination ID. + // -------------------------------------------------- + destid = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L]; + + + if (destid == 0 ) begin + src_channel = 11'b01; + end + if (destid == 1 ) begin + src_channel = 11'b10; + end + + +end + + + // -------------------------------------------------- + // Ceil(log2()) function + // -------------------------------------------------- + function integer log2ceil; + input reg[65:0] val; + reg [65:0] i; + + begin + i = 1; + log2ceil = 0; + + while (i < val) begin + log2ceil = log2ceil + 1; + i = i << 1; + end + end + endfunction + +endmodule + + diff --git a/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_id_router_002.sv b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_id_router_002.sv new file mode 100644 index 00000000..63c5f946 --- /dev/null +++ b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_id_router_002.sv @@ -0,0 +1,179 @@ +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/12.1sp1/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2012/10/10 $ +// $Author: swbranch $ + +// ------------------------------------------------------- +// Merlin Router +// +// Asserts the appropriate one-hot encoded channel based on +// either (a) the address or (b) the dest id. The DECODER_TYPE +// parameter controls this behaviour. 0 means address decoder, +// 1 means dest id decoder. +// +// In the case of (a), it also sets the destination id. +// ------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module system_id_router_002_default_decode + #( + parameter DEFAULT_CHANNEL = 0, + DEFAULT_DESTID = 1 + ) + (output [90 - 87 : 0] default_destination_id, + output [11-1 : 0] default_src_channel + ); + + assign default_destination_id = + DEFAULT_DESTID[90 - 87 : 0]; + generate begin : default_decode + if (DEFAULT_CHANNEL == -1) + assign default_src_channel = '0; + else + assign default_src_channel = 11'b1 << DEFAULT_CHANNEL; + end + endgenerate + +endmodule + + +module system_id_router_002 +( + // ------------------- + // Clock & Reset + // ------------------- + input clk, + input reset, + + // ------------------- + // Command Sink (Input) + // ------------------- + input sink_valid, + input [101-1 : 0] sink_data, + input sink_startofpacket, + input sink_endofpacket, + output sink_ready, + + // ------------------- + // Command Source (Output) + // ------------------- + output src_valid, + output reg [101-1 : 0] src_data, + output reg [11-1 : 0] src_channel, + output src_startofpacket, + output src_endofpacket, + input src_ready +); + + // ------------------------------------------------------- + // Local parameters and variables + // ------------------------------------------------------- + localparam PKT_ADDR_H = 61; + localparam PKT_ADDR_L = 36; + localparam PKT_DEST_ID_H = 90; + localparam PKT_DEST_ID_L = 87; + localparam ST_DATA_W = 101; + localparam ST_CHANNEL_W = 11; + localparam DECODER_TYPE = 1; + + localparam PKT_TRANS_WRITE = 64; + localparam PKT_TRANS_READ = 65; + + localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1; + localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1; + + + + + // ------------------------------------------------------- + // Figure out the number of bits to mask off for each slave span + // during address decoding + // ------------------------------------------------------- + // ------------------------------------------------------- + // Work out which address bits are significant based on the + // address range of the slaves. If the required width is too + // large or too small, we use the address field width instead. + // ------------------------------------------------------- + localparam ADDR_RANGE = 64'h0; + localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE); + localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) || + (RANGE_ADDR_WIDTH == 0) ? + PKT_ADDR_H : + PKT_ADDR_L + RANGE_ADDR_WIDTH - 1; + localparam RG = RANGE_ADDR_WIDTH-1; + + reg [PKT_DEST_ID_W-1 : 0] destid; + + // ------------------------------------------------------- + // Pass almost everything through, untouched + // ------------------------------------------------------- + assign sink_ready = src_ready; + assign src_valid = sink_valid; + assign src_startofpacket = sink_startofpacket; + assign src_endofpacket = sink_endofpacket; + + wire [PKT_DEST_ID_W-1:0] default_destid; + wire [11-1 : 0] default_src_channel; + + + + + system_id_router_002_default_decode the_default_decode( + .default_destination_id (default_destid), + .default_src_channel (default_src_channel) + ); + + always @* begin + src_data = sink_data; + src_channel = default_src_channel; + + // -------------------------------------------------- + // DestinationID Decoder + // Sets the channel based on the destination ID. + // -------------------------------------------------- + destid = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L]; + + + if (destid == 1 ) begin + src_channel = 11'b1; + end + + +end + + + // -------------------------------------------------- + // Ceil(log2()) function + // -------------------------------------------------- + function integer log2ceil; + input reg[65:0] val; + reg [65:0] i; + + begin + i = 1; + log2ceil = 0; + + while (i < val) begin + log2ceil = log2ceil + 1; + i = i << 1; + end + end + endfunction + +endmodule + + diff --git a/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_irq_mapper.sv b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_irq_mapper.sv new file mode 100644 index 00000000..93d40d79 --- /dev/null +++ b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_irq_mapper.sv @@ -0,0 +1,65 @@ +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/12.1sp1/ip/merlin/altera_irq_mapper/altera_irq_mapper.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2012/10/10 $ +// $Author: swbranch $ + +// ------------------------------------------------------- +// Altera IRQ Mapper +// +// Parameters +// NUM_RCVRS : 4 +// SENDER_IRW_WIDTH : 32 +// IRQ_MAP : 0:1,1:4,2:14,3:5 +// +// ------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module system_irq_mapper +( + // ------------------- + // Clock & Reset + // ------------------- + input clk, + input reset, + + // ------------------- + // IRQ Receivers + // ------------------- + input receiver0_irq, + input receiver1_irq, + input receiver2_irq, + input receiver3_irq, + + // ------------------- + // Command Source (Output) + // ------------------- + output reg [31 : 0] sender_irq +); + + + always @* begin + sender_irq = 0; + + sender_irq[1] = receiver0_irq; + sender_irq[4] = receiver1_irq; + sender_irq[14] = receiver2_irq; + sender_irq[5] = receiver3_irq; + end + +endmodule + + diff --git a/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_jtag_uart_0.v b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_jtag_uart_0.v new file mode 100644 index 00000000..b257f0c6 --- /dev/null +++ b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_jtag_uart_0.v @@ -0,0 +1,793 @@ +//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module system_jtag_uart_0_log_module ( + // inputs: + clk, + data, + strobe, + valid + ) +; + + input clk; + input [ 7: 0] data; + input strobe; + input valid; + + +//synthesis translate_off +//////////////// SIMULATION-ONLY CONTENTS + reg [31:0] text_handle; // for $fopen + initial text_handle = $fopen ("system_jtag_uart_0_output_stream.dat"); + + always @(posedge clk) begin + if (valid && strobe) begin + $fwrite (text_handle, "%b\n", data); + // non-standard; poorly documented; required to get real data stream. + $fflush (text_handle); + end + end // clk + + +//////////////// END SIMULATION-ONLY CONTENTS + +//synthesis translate_on + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module system_jtag_uart_0_sim_scfifo_w ( + // inputs: + clk, + fifo_wdata, + fifo_wr, + + // outputs: + fifo_FF, + r_dat, + wfifo_empty, + wfifo_used + ) +; + + output fifo_FF; + output [ 7: 0] r_dat; + output wfifo_empty; + output [ 5: 0] wfifo_used; + input clk; + input [ 7: 0] fifo_wdata; + input fifo_wr; + + wire fifo_FF; + wire [ 7: 0] r_dat; + wire wfifo_empty; + wire [ 5: 0] wfifo_used; + +//synthesis translate_off +//////////////// SIMULATION-ONLY CONTENTS + //system_jtag_uart_0_log, which is an e_log + system_jtag_uart_0_log_module system_jtag_uart_0_log + ( + .clk (clk), + .data (fifo_wdata), + .strobe (fifo_wr), + .valid (fifo_wr) + ); + + assign wfifo_used = {6{1'b0}}; + assign r_dat = {8{1'b0}}; + assign fifo_FF = 1'b0; + assign wfifo_empty = 1'b1; + +//////////////// END SIMULATION-ONLY CONTENTS + +//synthesis translate_on + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module system_jtag_uart_0_scfifo_w ( + // inputs: + clk, + fifo_clear, + fifo_wdata, + fifo_wr, + rd_wfifo, + + // outputs: + fifo_FF, + r_dat, + wfifo_empty, + wfifo_used + ) +; + + output fifo_FF; + output [ 7: 0] r_dat; + output wfifo_empty; + output [ 5: 0] wfifo_used; + input clk; + input fifo_clear; + input [ 7: 0] fifo_wdata; + input fifo_wr; + input rd_wfifo; + + wire fifo_FF; + wire [ 7: 0] r_dat; + wire wfifo_empty; + wire [ 5: 0] wfifo_used; + +//synthesis translate_off +//////////////// SIMULATION-ONLY CONTENTS + system_jtag_uart_0_sim_scfifo_w the_system_jtag_uart_0_sim_scfifo_w + ( + .clk (clk), + .fifo_FF (fifo_FF), + .fifo_wdata (fifo_wdata), + .fifo_wr (fifo_wr), + .r_dat (r_dat), + .wfifo_empty (wfifo_empty), + .wfifo_used (wfifo_used) + ); + + +//////////////// END SIMULATION-ONLY CONTENTS + +//synthesis translate_on +//synthesis read_comments_as_HDL on +// scfifo wfifo +// ( +// .aclr (fifo_clear), +// .clock (clk), +// .data (fifo_wdata), +// .empty (wfifo_empty), +// .full (fifo_FF), +// .q (r_dat), +// .rdreq (rd_wfifo), +// .usedw (wfifo_used), +// .wrreq (fifo_wr) +// ); +// +// defparam wfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO", +// wfifo.lpm_numwords = 64, +// wfifo.lpm_showahead = "OFF", +// wfifo.lpm_type = "scfifo", +// wfifo.lpm_width = 8, +// wfifo.lpm_widthu = 6, +// wfifo.overflow_checking = "OFF", +// wfifo.underflow_checking = "OFF", +// wfifo.use_eab = "ON"; +// +//synthesis read_comments_as_HDL off + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module system_jtag_uart_0_drom_module ( + // inputs: + clk, + incr_addr, + reset_n, + + // outputs: + new_rom, + num_bytes, + q, + safe + ) +; + + parameter POLL_RATE = 100; + + + output new_rom; + output [ 31: 0] num_bytes; + output [ 7: 0] q; + output safe; + input clk; + input incr_addr; + input reset_n; + + reg [ 11: 0] address; + reg d1_pre; + reg d2_pre; + reg d3_pre; + reg d4_pre; + reg d5_pre; + reg d6_pre; + reg d7_pre; + reg d8_pre; + reg d9_pre; + reg [ 7: 0] mem_array [2047: 0]; + reg [ 31: 0] mutex [ 1: 0]; + reg new_rom; + wire [ 31: 0] num_bytes; + reg pre; + wire [ 7: 0] q; + wire safe; + +//synthesis translate_off +//////////////// SIMULATION-ONLY CONTENTS + assign q = mem_array[address]; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + begin + d1_pre <= 0; + d2_pre <= 0; + d3_pre <= 0; + d4_pre <= 0; + d5_pre <= 0; + d6_pre <= 0; + d7_pre <= 0; + d8_pre <= 0; + d9_pre <= 0; + new_rom <= 0; + end + else + begin + d1_pre <= pre; + d2_pre <= d1_pre; + d3_pre <= d2_pre; + d4_pre <= d3_pre; + d5_pre <= d4_pre; + d6_pre <= d5_pre; + d7_pre <= d6_pre; + d8_pre <= d7_pre; + d9_pre <= d8_pre; + new_rom <= d9_pre; + end + end + + + + assign num_bytes = mutex[1]; + reg safe_delay; + reg [31:0] poll_count; + reg [31:0] mutex_handle; + wire interactive = 1'b1 ; // ' + assign safe = (address < mutex[1]); + + initial poll_count = POLL_RATE; + + always @(posedge clk or negedge reset_n) begin + if (reset_n !== 1) begin + safe_delay <= 0; + end else begin + safe_delay <= safe; + end + end // safe_delay + + always @(posedge clk or negedge reset_n) begin + if (reset_n !== 1) begin // dont worry about null _stream.dat file + address <= 0; + mem_array[0] <= 0; + mutex[0] <= 0; + mutex[1] <= 0; + pre <= 0; + end else begin // deal with the non-reset case + pre <= 0; + if (incr_addr && safe) address <= address + 1; + if (mutex[0] && !safe && safe_delay) begin + // and blast the mutex after falling edge of safe if interactive + if (interactive) begin + mutex_handle = $fopen ("system_jtag_uart_0_input_mutex.dat"); + $fdisplay (mutex_handle, "0"); + $fclose (mutex_handle); + // $display ($stime, "\t%m:\n\t\tMutex cleared!"); + end else begin + // sleep until next reset, do not bash mutex. + wait (!reset_n); + end + end // OK to bash mutex. + if (poll_count < POLL_RATE) begin // wait + poll_count = poll_count + 1; + end else begin // do the interesting stuff. + poll_count = 0; + if (mutex_handle) begin + $readmemh ("system_jtag_uart_0_input_mutex.dat", mutex); + end + if (mutex[0] && !safe) begin + // read stream into mem_array after current characters are gone! + // save mutex[0] value to compare to address (generates 'safe') + mutex[1] <= mutex[0]; + // $display ($stime, "\t%m:\n\t\tMutex hit: Trying to read %d bytes...", mutex[0]); + $readmemb("system_jtag_uart_0_input_stream.dat", mem_array); + // bash address and send pulse outside to send the char: + address <= 0; + pre <= -1; + end // else mutex miss... + end // poll_count + end // reset + end // posedge clk + + +//////////////// END SIMULATION-ONLY CONTENTS + +//synthesis translate_on + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module system_jtag_uart_0_sim_scfifo_r ( + // inputs: + clk, + fifo_rd, + rst_n, + + // outputs: + fifo_EF, + fifo_rdata, + rfifo_full, + rfifo_used + ) +; + + output fifo_EF; + output [ 7: 0] fifo_rdata; + output rfifo_full; + output [ 5: 0] rfifo_used; + input clk; + input fifo_rd; + input rst_n; + + reg [ 31: 0] bytes_left; + wire fifo_EF; + reg fifo_rd_d; + wire [ 7: 0] fifo_rdata; + wire new_rom; + wire [ 31: 0] num_bytes; + wire [ 6: 0] rfifo_entries; + wire rfifo_full; + wire [ 5: 0] rfifo_used; + wire safe; + +//synthesis translate_off +//////////////// SIMULATION-ONLY CONTENTS + //system_jtag_uart_0_drom, which is an e_drom + system_jtag_uart_0_drom_module system_jtag_uart_0_drom + ( + .clk (clk), + .incr_addr (fifo_rd_d), + .new_rom (new_rom), + .num_bytes (num_bytes), + .q (fifo_rdata), + .reset_n (rst_n), + .safe (safe) + ); + + // Generate rfifo_entries for simulation + always @(posedge clk or negedge rst_n) + begin + if (rst_n == 0) + begin + bytes_left <= 32'h0; + fifo_rd_d <= 1'b0; + end + else + begin + fifo_rd_d <= fifo_rd; + // decrement on read + if (fifo_rd_d) + bytes_left <= bytes_left - 1'b1; + // catch new contents + if (new_rom) + bytes_left <= num_bytes; + end + end + + + assign fifo_EF = bytes_left == 32'b0; + assign rfifo_full = bytes_left > 7'h40; + assign rfifo_entries = (rfifo_full) ? 7'h40 : bytes_left; + assign rfifo_used = rfifo_entries[5 : 0]; + +//////////////// END SIMULATION-ONLY CONTENTS + +//synthesis translate_on + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module system_jtag_uart_0_scfifo_r ( + // inputs: + clk, + fifo_clear, + fifo_rd, + rst_n, + t_dat, + wr_rfifo, + + // outputs: + fifo_EF, + fifo_rdata, + rfifo_full, + rfifo_used + ) +; + + output fifo_EF; + output [ 7: 0] fifo_rdata; + output rfifo_full; + output [ 5: 0] rfifo_used; + input clk; + input fifo_clear; + input fifo_rd; + input rst_n; + input [ 7: 0] t_dat; + input wr_rfifo; + + wire fifo_EF; + wire [ 7: 0] fifo_rdata; + wire rfifo_full; + wire [ 5: 0] rfifo_used; + +//synthesis translate_off +//////////////// SIMULATION-ONLY CONTENTS + system_jtag_uart_0_sim_scfifo_r the_system_jtag_uart_0_sim_scfifo_r + ( + .clk (clk), + .fifo_EF (fifo_EF), + .fifo_rd (fifo_rd), + .fifo_rdata (fifo_rdata), + .rfifo_full (rfifo_full), + .rfifo_used (rfifo_used), + .rst_n (rst_n) + ); + + +//////////////// END SIMULATION-ONLY CONTENTS + +//synthesis translate_on +//synthesis read_comments_as_HDL on +// scfifo rfifo +// ( +// .aclr (fifo_clear), +// .clock (clk), +// .data (t_dat), +// .empty (fifo_EF), +// .full (rfifo_full), +// .q (fifo_rdata), +// .rdreq (fifo_rd), +// .usedw (rfifo_used), +// .wrreq (wr_rfifo) +// ); +// +// defparam rfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO", +// rfifo.lpm_numwords = 64, +// rfifo.lpm_showahead = "OFF", +// rfifo.lpm_type = "scfifo", +// rfifo.lpm_width = 8, +// rfifo.lpm_widthu = 6, +// rfifo.overflow_checking = "OFF", +// rfifo.underflow_checking = "OFF", +// rfifo.use_eab = "ON"; +// +//synthesis read_comments_as_HDL off + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module system_jtag_uart_0 ( + // inputs: + av_address, + av_chipselect, + av_read_n, + av_write_n, + av_writedata, + clk, + rst_n, + + // outputs: + av_irq, + av_readdata, + av_waitrequest, + dataavailable, + readyfordata + ) + /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R101,C106,D101,D103\"" */ ; + + output av_irq; + output [ 31: 0] av_readdata; + output av_waitrequest; + output dataavailable; + output readyfordata; + input av_address; + input av_chipselect; + input av_read_n; + input av_write_n; + input [ 31: 0] av_writedata; + input clk; + input rst_n; + + reg ac; + wire activity; + wire av_irq; + wire [ 31: 0] av_readdata; + reg av_waitrequest; + reg dataavailable; + reg fifo_AE; + reg fifo_AF; + wire fifo_EF; + wire fifo_FF; + wire fifo_clear; + wire fifo_rd; + wire [ 7: 0] fifo_rdata; + wire [ 7: 0] fifo_wdata; + reg fifo_wr; + reg ien_AE; + reg ien_AF; + wire ipen_AE; + wire ipen_AF; + reg pause_irq; + wire [ 7: 0] r_dat; + wire r_ena; + reg r_val; + wire rd_wfifo; + reg read_0; + reg readyfordata; + wire rfifo_full; + wire [ 5: 0] rfifo_used; + reg rvalid; + reg sim_r_ena; + reg sim_t_dat; + reg sim_t_ena; + reg sim_t_pause; + wire [ 7: 0] t_dat; + reg t_dav; + wire t_ena; + wire t_pause; + wire wfifo_empty; + wire [ 5: 0] wfifo_used; + reg woverflow; + wire wr_rfifo; + //avalon_jtag_slave, which is an e_avalon_slave + assign rd_wfifo = r_ena & ~wfifo_empty; + assign wr_rfifo = t_ena & ~rfifo_full; + assign fifo_clear = ~rst_n; + system_jtag_uart_0_scfifo_w the_system_jtag_uart_0_scfifo_w + ( + .clk (clk), + .fifo_FF (fifo_FF), + .fifo_clear (fifo_clear), + .fifo_wdata (fifo_wdata), + .fifo_wr (fifo_wr), + .r_dat (r_dat), + .rd_wfifo (rd_wfifo), + .wfifo_empty (wfifo_empty), + .wfifo_used (wfifo_used) + ); + + system_jtag_uart_0_scfifo_r the_system_jtag_uart_0_scfifo_r + ( + .clk (clk), + .fifo_EF (fifo_EF), + .fifo_clear (fifo_clear), + .fifo_rd (fifo_rd), + .fifo_rdata (fifo_rdata), + .rfifo_full (rfifo_full), + .rfifo_used (rfifo_used), + .rst_n (rst_n), + .t_dat (t_dat), + .wr_rfifo (wr_rfifo) + ); + + assign ipen_AE = ien_AE & fifo_AE; + assign ipen_AF = ien_AF & (pause_irq | fifo_AF); + assign av_irq = ipen_AE | ipen_AF; + assign activity = t_pause | t_ena; + always @(posedge clk or negedge rst_n) + begin + if (rst_n == 0) + pause_irq <= 1'b0; + else // only if fifo is not empty... + if (t_pause & ~fifo_EF) + pause_irq <= 1'b1; + else if (read_0) + pause_irq <= 1'b0; + end + + + always @(posedge clk or negedge rst_n) + begin + if (rst_n == 0) + begin + r_val <= 1'b0; + t_dav <= 1'b1; + end + else + begin + r_val <= r_ena & ~wfifo_empty; + t_dav <= ~rfifo_full; + end + end + + + always @(posedge clk or negedge rst_n) + begin + if (rst_n == 0) + begin + fifo_AE <= 1'b0; + fifo_AF <= 1'b0; + fifo_wr <= 1'b0; + rvalid <= 1'b0; + read_0 <= 1'b0; + ien_AE <= 1'b0; + ien_AF <= 1'b0; + ac <= 1'b0; + woverflow <= 1'b0; + av_waitrequest <= 1'b1; + end + else + begin + fifo_AE <= {fifo_FF,wfifo_used} <= 8; + fifo_AF <= (7'h40 - {rfifo_full,rfifo_used}) <= 8; + fifo_wr <= 1'b0; + read_0 <= 1'b0; + av_waitrequest <= ~(av_chipselect & (~av_write_n | ~av_read_n) & av_waitrequest); + if (activity) + ac <= 1'b1; + // write + if (av_chipselect & ~av_write_n & av_waitrequest) + // addr 1 is control; addr 0 is data + if (av_address) + begin + ien_AF <= av_writedata[0]; + ien_AE <= av_writedata[1]; + if (av_writedata[10] & ~activity) + ac <= 1'b0; + end + else + begin + fifo_wr <= ~fifo_FF; + woverflow <= fifo_FF; + end + // read + if (av_chipselect & ~av_read_n & av_waitrequest) + begin + // addr 1 is interrupt; addr 0 is data + if (~av_address) + rvalid <= ~fifo_EF; + read_0 <= ~av_address; + end + end + end + + + assign fifo_wdata = av_writedata[7 : 0]; + assign fifo_rd = (av_chipselect & ~av_read_n & av_waitrequest & ~av_address) ? ~fifo_EF : 1'b0; + assign av_readdata = read_0 ? { {9{1'b0}},rfifo_full,rfifo_used,rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,fifo_rdata } : { {9{1'b0}},(7'h40 - {fifo_FF,wfifo_used}),rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,{6{1'b0}},ien_AE,ien_AF }; + always @(posedge clk or negedge rst_n) + begin + if (rst_n == 0) + readyfordata <= 0; + else + readyfordata <= ~fifo_FF; + end + + + +//synthesis translate_off +//////////////// SIMULATION-ONLY CONTENTS + // Tie off Atlantic Interface signals not used for simulation + always @(posedge clk) + begin + sim_t_pause <= 1'b0; + sim_t_ena <= 1'b0; + sim_t_dat <= t_dav ? r_dat : {8{r_val}}; + sim_r_ena <= 1'b0; + end + + + assign r_ena = sim_r_ena; + assign t_ena = sim_t_ena; + assign t_dat = sim_t_dat; + assign t_pause = sim_t_pause; + always @(fifo_EF) + begin + dataavailable = ~fifo_EF; + end + + + +//////////////// END SIMULATION-ONLY CONTENTS + +//synthesis translate_on +//synthesis read_comments_as_HDL on +// alt_jtag_atlantic system_jtag_uart_0_alt_jtag_atlantic +// ( +// .clk (clk), +// .r_dat (r_dat), +// .r_ena (r_ena), +// .r_val (r_val), +// .rst_n (rst_n), +// .t_dat (t_dat), +// .t_dav (t_dav), +// .t_ena (t_ena), +// .t_pause (t_pause) +// ); +// +// defparam system_jtag_uart_0_alt_jtag_atlantic.INSTANCE_ID = 0, +// system_jtag_uart_0_alt_jtag_atlantic.LOG2_RXFIFO_DEPTH = 6, +// system_jtag_uart_0_alt_jtag_atlantic.LOG2_TXFIFO_DEPTH = 6, +// system_jtag_uart_0_alt_jtag_atlantic.SLD_AUTO_INSTANCE_INDEX = "YES"; +// +// always @(posedge clk or negedge rst_n) +// begin +// if (rst_n == 0) +// dataavailable <= 0; +// else +// dataavailable <= ~fifo_EF; +// end +// +// +//synthesis read_comments_as_HDL off + +endmodule + diff --git a/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_jtag_uart_0_input_mutex.dat b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_jtag_uart_0_input_mutex.dat new file mode 100644 index 00000000..573541ac --- /dev/null +++ b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_jtag_uart_0_input_mutex.dat @@ -0,0 +1 @@ +0 diff --git a/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_jtag_uart_0_input_stream.dat b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_jtag_uart_0_input_stream.dat new file mode 100644 index 00000000..5b290d00 --- /dev/null +++ b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_jtag_uart_0_input_stream.dat @@ -0,0 +1 @@ +00000000 diff --git a/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_jtag_uart_0_output_stream.dat b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_jtag_uart_0_output_stream.dat new file mode 100644 index 00000000..e69de29b diff --git a/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_pio_int3.v b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_pio_int3.v new file mode 100644 index 00000000..39230f3a --- /dev/null +++ b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_pio_int3.v @@ -0,0 +1,115 @@ +//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module system_pio_int3 ( + // inputs: + address, + chipselect, + clk, + in_port, + reset_n, + write_n, + writedata, + + // outputs: + irq, + readdata + ) +; + + output irq; + output [ 31: 0] readdata; + input [ 1: 0] address; + input chipselect; + input clk; + input in_port; + input reset_n; + input write_n; + input [ 31: 0] writedata; + + wire clk_en; + reg d1_data_in; + reg d2_data_in; + wire data_in; + reg edge_capture; + wire edge_capture_wr_strobe; + wire edge_detect; + wire irq; + reg irq_mask; + wire read_mux_out; + reg [ 31: 0] readdata; + assign clk_en = 1; + //s1, which is an e_avalon_slave + assign read_mux_out = ({1 {(address == 0)}} & data_in) | + ({1 {(address == 2)}} & irq_mask) | + ({1 {(address == 3)}} & edge_capture); + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + readdata <= 0; + else if (clk_en) + readdata <= {32'b0 | read_mux_out}; + end + + + assign data_in = in_port; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + irq_mask <= 0; + else if (chipselect && ~write_n && (address == 2)) + irq_mask <= writedata; + end + + + assign irq = |(edge_capture & irq_mask); + assign edge_capture_wr_strobe = chipselect && ~write_n && (address == 3); + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + edge_capture <= 0; + else if (clk_en) + if (edge_capture_wr_strobe && writedata[0]) + edge_capture <= 0; + else if (edge_detect) + edge_capture <= -1; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + begin + d1_data_in <= 0; + d2_data_in <= 0; + end + else if (clk_en) + begin + d1_data_in <= data_in; + d2_data_in <= d1_data_in; + end + end + + + assign edge_detect = d1_data_in & ~d2_data_in; + +endmodule + diff --git a/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_pio_ir.v b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_pio_ir.v new file mode 100644 index 00000000..b08703c7 --- /dev/null +++ b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_pio_ir.v @@ -0,0 +1,115 @@ +//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module system_pio_ir ( + // inputs: + address, + chipselect, + clk, + in_port, + reset_n, + write_n, + writedata, + + // outputs: + irq, + readdata + ) +; + + output irq; + output [ 31: 0] readdata; + input [ 1: 0] address; + input chipselect; + input clk; + input in_port; + input reset_n; + input write_n; + input [ 31: 0] writedata; + + wire clk_en; + reg d1_data_in; + reg d2_data_in; + wire data_in; + reg edge_capture; + wire edge_capture_wr_strobe; + wire edge_detect; + wire irq; + reg irq_mask; + wire read_mux_out; + reg [ 31: 0] readdata; + assign clk_en = 1; + //s1, which is an e_avalon_slave + assign read_mux_out = ({1 {(address == 0)}} & data_in) | + ({1 {(address == 2)}} & irq_mask) | + ({1 {(address == 3)}} & edge_capture); + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + readdata <= 0; + else if (clk_en) + readdata <= {32'b0 | read_mux_out}; + end + + + assign data_in = in_port; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + irq_mask <= 0; + else if (chipselect && ~write_n && (address == 2)) + irq_mask <= writedata; + end + + + assign irq = |(edge_capture & irq_mask); + assign edge_capture_wr_strobe = chipselect && ~write_n && (address == 3); + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + edge_capture <= 0; + else if (clk_en) + if (edge_capture_wr_strobe && writedata[0]) + edge_capture <= 0; + else if (edge_detect) + edge_capture <= -1; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + begin + d1_data_in <= 0; + d2_data_in <= 0; + end + else if (clk_en) + begin + d1_data_in <= data_in; + d2_data_in <= d1_data_in; + end + end + + + assign edge_detect = d1_data_in ^ d2_data_in; + +endmodule + diff --git a/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_pio_key.v b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_pio_key.v new file mode 100644 index 00000000..d2f1c090 --- /dev/null +++ b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_pio_key.v @@ -0,0 +1,58 @@ +//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module system_pio_key ( + // inputs: + address, + clk, + in_port, + reset_n, + + // outputs: + readdata + ) +; + + output [ 31: 0] readdata; + input [ 1: 0] address; + input clk; + input [ 1: 0] in_port; + input reset_n; + + wire clk_en; + wire [ 1: 0] data_in; + wire [ 1: 0] read_mux_out; + reg [ 31: 0] readdata; + assign clk_en = 1; + //s1, which is an e_avalon_slave + assign read_mux_out = {2 {(address == 0)}} & data_in; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + readdata <= 0; + else if (clk_en) + readdata <= {32'b0 | read_mux_out}; + end + + + assign data_in = in_port; + +endmodule + diff --git a/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_pio_led.v b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_pio_led.v new file mode 100644 index 00000000..de117114 --- /dev/null +++ b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_pio_led.v @@ -0,0 +1,69 @@ +//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module system_pio_led ( + // inputs: + address, + chipselect, + clk, + reset_n, + write_n, + writedata, + + // outputs: + out_port, + readdata + ) +; + + output [ 6: 0] out_port; + output [ 31: 0] readdata; + input [ 2: 0] address; + input chipselect; + input clk; + input reset_n; + input write_n; + input [ 31: 0] writedata; + + wire clk_en; + reg [ 6: 0] data_out; + wire [ 6: 0] out_port; + wire [ 6: 0] read_mux_out; + wire [ 31: 0] readdata; + wire wr_strobe; + assign clk_en = 1; + //s1, which is an e_avalon_slave + assign read_mux_out = {7 {(address == 0)}} & data_out; + assign wr_strobe = chipselect && ~write_n; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + data_out <= 0; + else if (clk_en) + if (wr_strobe) + data_out <= (address == 5)? data_out & ~writedata[6 : 0]: (address == 4)? data_out | writedata[6 : 0]: (address == 0)? writedata[6 : 0]: data_out; + end + + + assign readdata = {32'b0 | read_mux_out}; + assign out_port = data_out; + +endmodule + diff --git a/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_pio_led_green.v b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_pio_led_green.v new file mode 100644 index 00000000..01c6631b --- /dev/null +++ b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_pio_led_green.v @@ -0,0 +1,69 @@ +//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module system_pio_led_green ( + // inputs: + address, + chipselect, + clk, + reset_n, + write_n, + writedata, + + // outputs: + out_port, + readdata + ) +; + + output [ 6: 0] out_port; + output [ 31: 0] readdata; + input [ 2: 0] address; + input chipselect; + input clk; + input reset_n; + input write_n; + input [ 31: 0] writedata; + + wire clk_en; + reg [ 6: 0] data_out; + wire [ 6: 0] out_port; + wire [ 6: 0] read_mux_out; + wire [ 31: 0] readdata; + wire wr_strobe; + assign clk_en = 1; + //s1, which is an e_avalon_slave + assign read_mux_out = {7 {(address == 0)}} & data_out; + assign wr_strobe = chipselect && ~write_n; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + data_out <= 0; + else if (clk_en) + if (wr_strobe) + data_out <= (address == 5)? data_out & ~writedata[6 : 0]: (address == 4)? data_out | writedata[6 : 0]: (address == 0)? writedata[6 : 0]: data_out; + end + + + assign readdata = {32'b0 | read_mux_out}; + assign out_port = data_out; + +endmodule + diff --git a/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_pio_motor_rst.v b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_pio_motor_rst.v new file mode 100644 index 00000000..cfc9a0f9 --- /dev/null +++ b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_pio_motor_rst.v @@ -0,0 +1,66 @@ +//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module system_pio_motor_rst ( + // inputs: + address, + chipselect, + clk, + reset_n, + write_n, + writedata, + + // outputs: + out_port, + readdata + ) +; + + output out_port; + output [ 31: 0] readdata; + input [ 1: 0] address; + input chipselect; + input clk; + input reset_n; + input write_n; + input [ 31: 0] writedata; + + wire clk_en; + reg data_out; + wire out_port; + wire read_mux_out; + wire [ 31: 0] readdata; + assign clk_en = 1; + //s1, which is an e_avalon_slave + assign read_mux_out = {1 {(address == 0)}} & data_out; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + data_out <= 0; + else if (chipselect && ~write_n && (address == 0)) + data_out <= writedata; + end + + + assign readdata = {32'b0 | read_mux_out}; + assign out_port = data_out; + +endmodule + diff --git a/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_pio_sw.v b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_pio_sw.v new file mode 100644 index 00000000..094a5870 --- /dev/null +++ b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_pio_sw.v @@ -0,0 +1,58 @@ +//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module system_pio_sw ( + // inputs: + address, + clk, + in_port, + reset_n, + + // outputs: + readdata + ) +; + + output [ 31: 0] readdata; + input [ 1: 0] address; + input clk; + input [ 3: 0] in_port; + input reset_n; + + wire clk_en; + wire [ 3: 0] data_in; + wire [ 3: 0] read_mux_out; + reg [ 31: 0] readdata; + assign clk_en = 1; + //s1, which is an e_avalon_slave + assign read_mux_out = {4 {(address == 0)}} & data_in; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + readdata <= 0; + else if (clk_en) + readdata <= {32'b0 | read_mux_out}; + end + + + assign data_in = in_port; + +endmodule + diff --git a/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_pio_vscodec.v b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_pio_vscodec.v new file mode 100644 index 00000000..7a864b57 --- /dev/null +++ b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_pio_vscodec.v @@ -0,0 +1,69 @@ +//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module system_pio_vscodec ( + // inputs: + address, + chipselect, + clk, + reset_n, + write_n, + writedata, + + // outputs: + out_port, + readdata + ) +; + + output [ 2: 0] out_port; + output [ 31: 0] readdata; + input [ 2: 0] address; + input chipselect; + input clk; + input reset_n; + input write_n; + input [ 31: 0] writedata; + + wire clk_en; + reg [ 2: 0] data_out; + wire [ 2: 0] out_port; + wire [ 2: 0] read_mux_out; + wire [ 31: 0] readdata; + wire wr_strobe; + assign clk_en = 1; + //s1, which is an e_avalon_slave + assign read_mux_out = {3 {(address == 0)}} & data_out; + assign wr_strobe = chipselect && ~write_n; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + data_out <= 0; + else if (clk_en) + if (wr_strobe) + data_out <= (address == 5)? data_out & ~writedata[2 : 0]: (address == 4)? data_out | writedata[2 : 0]: (address == 0)? writedata[2 : 0]: data_out; + end + + + assign readdata = {32'b0 | read_mux_out}; + assign out_port = data_out; + +endmodule + diff --git a/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_rs232_motor.v b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_rs232_motor.v new file mode 100644 index 00000000..a756a1e7 --- /dev/null +++ b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_rs232_motor.v @@ -0,0 +1,299 @@ +/****************************************************************************** + * License Agreement * + * * + * Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. * + * All rights reserved. * + * * + * Any megafunction design, and related net list (encrypted or decrypted), * + * support information, device programming or simulation file, and any other * + * associated documentation or information provided by Altera or a partner * + * under Altera's Megafunction Partnership Program may be used only to * + * program PLD devices (but not masked PLD devices) from Altera. Any other * + * use of such megafunction design, net list, support information, device * + * programming or simulation file, or any other related documentation or * + * information is prohibited for any other purpose, including, but not * + * limited to modification, reverse engineering, de-compiling, or use with * + * any other silicon devices, unless such use is explicitly licensed under * + * a separate agreement with Altera or a megafunction partner. Title to * + * the intellectual property, including patents, copyrights, trademarks, * + * trade secrets, or maskworks, embodied in any such megafunction design, * + * net list, support information, device programming or simulation file, or * + * any other related documentation or information provided by Altera or a * + * megafunction partner, remains with Altera, the megafunction partner, or * + * their respective licensors. No other licenses, including any licenses * + * needed under any third party's intellectual property, are provided herein.* + * Copying or modifying any file, or portion thereof, to which this notice * + * is attached violates this copyright. * + * * + * THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * + * FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS * + * IN THIS FILE. * + * * + * This agreement shall be governed in all respects by the laws of the State * + * of California and by the laws of the United States of America. * + * * + ******************************************************************************/ + +/****************************************************************************** + * * + * This module reads and writes data to the RS232 connector on Altera's * + * DE-series Development and Education Boards. * + * * + ******************************************************************************/ + +module system_rs232_motor ( + // Inputs + clk, + reset, + + address, + chipselect, + byteenable, + read, + write, + writedata, + + UART_RXD, + + // Bidirectionals + + // Outputs + irq, + readdata, + + UART_TXD +); + +/***************************************************************************** + * Parameter Declarations * + *****************************************************************************/ + +parameter CW = 14; // Baud counter width +parameter BAUD_TICK_COUNT = 10416; +parameter HALF_BAUD_TICK_COUNT = 5208; + +parameter TDW = 10; // Total data width +parameter DW = 8; // Data width +parameter ODD_PARITY = 1'b0; + +/***************************************************************************** + * Port Declarations * + *****************************************************************************/ +// Inputs +input clk; +input reset; + +input address; +input chipselect; +input [ 3: 0] byteenable; +input read; +input write; +input [31: 0] writedata; + +input UART_RXD; + +// Bidirectionals + +// Outputs +output reg irq; +output reg [31: 0] readdata; + +output UART_TXD; + +/***************************************************************************** + * Constant Declarations * + *****************************************************************************/ + +/***************************************************************************** + * Internal Wires and Registers Declarations * + *****************************************************************************/ + +// Internal Wires +wire read_fifo_read_en; +wire [ 7: 0] read_available; +wire read_data_valid; +wire [(DW-1):0] read_data; + +wire parity_error; + +wire write_data_parity; +wire [ 7: 0] write_space; + +// Internal Registers +reg read_interrupt_en; +reg write_interrupt_en; + +reg read_interrupt; +reg write_interrupt; + +reg write_fifo_write_en; +reg [(DW-1):0] data_to_uart; + +// State Machine Registers + +/***************************************************************************** + * Finite State Machine(s) * + *****************************************************************************/ + + +/***************************************************************************** + * Sequential Logic * + *****************************************************************************/ + +always @(posedge clk) +begin + if (reset) + irq <= 1'b0; + else + irq <= write_interrupt | read_interrupt; +end + +always @(posedge clk) +begin + if (reset) + readdata <= 32'h00000000; + else if (chipselect) + begin + if (address == 1'b0) + readdata <= + {8'h00, + read_available, + read_data_valid, + 5'h00, + parity_error, + 1'b0, + read_data[(DW - 1):0]}; + else + readdata <= + {8'h00, + write_space, + 6'h00, + write_interrupt, + read_interrupt, + 6'h00, + write_interrupt_en, + read_interrupt_en}; + end +end + + +always @(posedge clk) +begin + if (reset) + read_interrupt_en <= 1'b0; + else if ((chipselect) && (write) && (address) && (byteenable[0])) + read_interrupt_en <= writedata[0]; +end + +always @(posedge clk) +begin + if (reset) + write_interrupt_en <= 1'b0; + else if ((chipselect) && (write) && (address) && (byteenable[0])) + write_interrupt_en <= writedata[1]; +end + +always @(posedge clk) +begin + if (reset) + read_interrupt <= 1'b0; + else if (read_interrupt_en == 1'b0) + read_interrupt <= 1'b0; + else + read_interrupt <= (&(read_available[6:5]) | read_available[7]); +end + +always @(posedge clk) +begin + if (reset) + write_interrupt <= 1'b0; + else if (write_interrupt_en == 1'b0) + write_interrupt <= 1'b0; + else + write_interrupt <= (&(write_space[6:5]) | write_space[7]); +end + + +always @(posedge clk) +begin + if (reset) + write_fifo_write_en <= 1'b0; + else + write_fifo_write_en <= + chipselect & write & ~address & byteenable[0]; +end + +always @(posedge clk) +begin + if (reset) + data_to_uart <= 'h0; + else + data_to_uart <= writedata[(DW - 1):0]; +end + +/***************************************************************************** + * Combinational Logic * + *****************************************************************************/ + +assign parity_error = 1'b0; + +assign read_fifo_read_en = chipselect & read & ~address & byteenable[0]; + +assign write_data_parity = (^(data_to_uart)) ^ ODD_PARITY; + +/***************************************************************************** + * Internal Modules * + *****************************************************************************/ + +altera_up_rs232_in_deserializer RS232_In_Deserializer ( + // Inputs + .clk (clk), + .reset (reset), + + .serial_data_in (UART_RXD), + + .receive_data_en (read_fifo_read_en), + + // Bidirectionals + + // Outputs + .fifo_read_available (read_available), + + .received_data_valid (read_data_valid), + .received_data (read_data) +); +defparam + RS232_In_Deserializer.CW = CW, + RS232_In_Deserializer.BAUD_TICK_COUNT = BAUD_TICK_COUNT, + RS232_In_Deserializer.HALF_BAUD_TICK_COUNT = HALF_BAUD_TICK_COUNT, + RS232_In_Deserializer.TDW = TDW, + RS232_In_Deserializer.DW = (DW - 1); + +altera_up_rs232_out_serializer RS232_Out_Serializer ( + // Inputs + .clk (clk), + .reset (reset), + + .transmit_data (data_to_uart), + .transmit_data_en (write_fifo_write_en), + + // Bidirectionals + + // Outputs + .fifo_write_space (write_space), + + .serial_data_out (UART_TXD) +); +defparam + RS232_Out_Serializer.CW = CW, + RS232_Out_Serializer.BAUD_TICK_COUNT = BAUD_TICK_COUNT, + RS232_Out_Serializer.HALF_BAUD_TICK_COUNT = HALF_BAUD_TICK_COUNT, + RS232_Out_Serializer.TDW = TDW, + RS232_Out_Serializer.DW = (DW - 1); + +endmodule + diff --git a/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_rsp_xbar_demux.sv b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_rsp_xbar_demux.sv new file mode 100644 index 00000000..3da41ee9 --- /dev/null +++ b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_rsp_xbar_demux.sv @@ -0,0 +1,116 @@ +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/12.1sp1/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2012/10/10 $ +// $Author: swbranch $ + +// ------------------------------------- +// Merlin Demultiplexer +// +// Asserts valid on the appropriate output +// given a one-hot channel signal. +// ------------------------------------- + +`timescale 1 ns / 1 ns + +// ------------------------------------------ +// Generation parameters: +// output_name: system_rsp_xbar_demux +// ST_DATA_W: 101 +// ST_CHANNEL_W: 11 +// NUM_OUTPUTS: 2 +// VALID_WIDTH: 1 +// ------------------------------------------ + +//------------------------------------------ +// Message Supression Used +// QIS Warnings +// 15610 - Warning: Design contains x input pin(s) that do not drive logic +//------------------------------------------ + +module system_rsp_xbar_demux +( + // ------------------- + // Sink + // ------------------- + input [1-1 : 0] sink_valid, + input [101-1 : 0] sink_data, // ST_DATA_W=101 + input [11-1 : 0] sink_channel, // ST_CHANNEL_W=11 + input sink_startofpacket, + input sink_endofpacket, + output sink_ready, + + // ------------------- + // Sources + // ------------------- + output reg src0_valid, + output reg [101-1 : 0] src0_data, // ST_DATA_W=101 + output reg [11-1 : 0] src0_channel, // ST_CHANNEL_W=11 + output reg src0_startofpacket, + output reg src0_endofpacket, + input src0_ready, + + output reg src1_valid, + output reg [101-1 : 0] src1_data, // ST_DATA_W=101 + output reg [11-1 : 0] src1_channel, // ST_CHANNEL_W=11 + output reg src1_startofpacket, + output reg src1_endofpacket, + input src1_ready, + + + // ------------------- + // Clock & Reset + // ------------------- + (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk + input clk, + (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset + input reset + +); + + localparam NUM_OUTPUTS = 2; + wire [NUM_OUTPUTS - 1 : 0] ready_vector; + + // ------------------- + // Demux + // ------------------- + always @* begin + src0_data = sink_data; + src0_startofpacket = sink_startofpacket; + src0_endofpacket = sink_endofpacket; + src0_channel = sink_channel >> NUM_OUTPUTS; + + src0_valid = sink_channel[0] && sink_valid; + + src1_data = sink_data; + src1_startofpacket = sink_startofpacket; + src1_endofpacket = sink_endofpacket; + src1_channel = sink_channel >> NUM_OUTPUTS; + + src1_valid = sink_channel[1] && sink_valid; + + end + + // ------------------- + // Backpressure + // ------------------- + assign ready_vector[0] = src0_ready; + assign ready_vector[1] = src1_ready; + + assign sink_ready = |(sink_channel & {{9{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}}); + +endmodule + + diff --git a/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_rsp_xbar_demux_002.sv b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_rsp_xbar_demux_002.sv new file mode 100644 index 00000000..67a389be --- /dev/null +++ b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_rsp_xbar_demux_002.sv @@ -0,0 +1,101 @@ +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/12.1sp1/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2012/10/10 $ +// $Author: swbranch $ + +// ------------------------------------- +// Merlin Demultiplexer +// +// Asserts valid on the appropriate output +// given a one-hot channel signal. +// ------------------------------------- + +`timescale 1 ns / 1 ns + +// ------------------------------------------ +// Generation parameters: +// output_name: system_rsp_xbar_demux_002 +// ST_DATA_W: 101 +// ST_CHANNEL_W: 11 +// NUM_OUTPUTS: 1 +// VALID_WIDTH: 1 +// ------------------------------------------ + +//------------------------------------------ +// Message Supression Used +// QIS Warnings +// 15610 - Warning: Design contains x input pin(s) that do not drive logic +//------------------------------------------ + +module system_rsp_xbar_demux_002 +( + // ------------------- + // Sink + // ------------------- + input [1-1 : 0] sink_valid, + input [101-1 : 0] sink_data, // ST_DATA_W=101 + input [11-1 : 0] sink_channel, // ST_CHANNEL_W=11 + input sink_startofpacket, + input sink_endofpacket, + output sink_ready, + + // ------------------- + // Sources + // ------------------- + output reg src0_valid, + output reg [101-1 : 0] src0_data, // ST_DATA_W=101 + output reg [11-1 : 0] src0_channel, // ST_CHANNEL_W=11 + output reg src0_startofpacket, + output reg src0_endofpacket, + input src0_ready, + + + // ------------------- + // Clock & Reset + // ------------------- + (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk + input clk, + (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset + input reset + +); + + localparam NUM_OUTPUTS = 1; + wire [NUM_OUTPUTS - 1 : 0] ready_vector; + + // ------------------- + // Demux + // ------------------- + always @* begin + src0_data = sink_data; + src0_startofpacket = sink_startofpacket; + src0_endofpacket = sink_endofpacket; + src0_channel = sink_channel >> NUM_OUTPUTS; + + src0_valid = sink_channel[0] && sink_valid; + + end + + // ------------------- + // Backpressure + // ------------------- + assign ready_vector[0] = src0_ready; + + assign sink_ready = |(sink_channel & {{10{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}}); + +endmodule + + diff --git a/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_rsp_xbar_mux.sv b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_rsp_xbar_mux.sv new file mode 100644 index 00000000..327edec3 --- /dev/null +++ b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_rsp_xbar_mux.sv @@ -0,0 +1,331 @@ +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/12.1sp1/ip/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2012/10/10 $ +// $Author: swbranch $ + +// ------------------------------------------ +// Merlin Multiplexer +// ------------------------------------------ + +`timescale 1 ns / 1 ns + + +// ------------------------------------------ +// Generation parameters: +// output_name: system_rsp_xbar_mux +// NUM_INPUTS: 2 +// ARBITRATION_SHARES: 1 1 +// ARBITRATION_SCHEME "no-arb" +// PIPELINE_ARB: 0 +// PKT_TRANS_LOCK: 66 (arbitration locking enabled) +// ST_DATA_W: 101 +// ST_CHANNEL_W: 11 +// ------------------------------------------ + +module system_rsp_xbar_mux +( + // ---------------------- + // Sinks + // ---------------------- + input sink0_valid, + input [101-1 : 0] sink0_data, + input [11-1: 0] sink0_channel, + input sink0_startofpacket, + input sink0_endofpacket, + output sink0_ready, + + input sink1_valid, + input [101-1 : 0] sink1_data, + input [11-1: 0] sink1_channel, + input sink1_startofpacket, + input sink1_endofpacket, + output sink1_ready, + + + // ---------------------- + // Source + // ---------------------- + output src_valid, + output [101-1 : 0] src_data, + output [11-1 : 0] src_channel, + output src_startofpacket, + output src_endofpacket, + input src_ready, + + // ---------------------- + // Clock & Reset + // ---------------------- + input clk, + input reset +); + localparam PAYLOAD_W = 101 + 11 + 2; + localparam NUM_INPUTS = 2; + localparam SHARE_COUNTER_W = 1; + localparam PIPELINE_ARB = 0; + localparam ST_DATA_W = 101; + localparam ST_CHANNEL_W = 11; + localparam PKT_TRANS_LOCK = 66; + + // ------------------------------------------ + // Signals + // ------------------------------------------ + wire [NUM_INPUTS - 1 : 0] request; + wire [NUM_INPUTS - 1 : 0] valid; + wire [NUM_INPUTS - 1 : 0] grant; + wire [NUM_INPUTS - 1 : 0] next_grant; + reg [NUM_INPUTS - 1 : 0] saved_grant; + reg [PAYLOAD_W - 1 : 0] src_payload; + wire last_cycle; + reg packet_in_progress; + reg update_grant; + + wire [PAYLOAD_W - 1 : 0] sink0_payload; + wire [PAYLOAD_W - 1 : 0] sink1_payload; + + assign valid[0] = sink0_valid; + assign valid[1] = sink1_valid; + + + // ------------------------------------------ + // ------------------------------------------ + // Grant Logic & Updates + // ------------------------------------------ + // ------------------------------------------ + reg [NUM_INPUTS - 1 : 0] lock; + always @* begin + lock[0] = sink0_data[66]; + lock[1] = sink1_data[66]; + end + + assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant)); + + // ------------------------------------------ + // We're working on a packet at any time valid is high, except + // when this is the endofpacket. + // ------------------------------------------ + always @(posedge clk or posedge reset) begin + if (reset) begin + packet_in_progress <= 1'b0; + end + else begin + if (src_valid) + packet_in_progress <= 1'b1; + if (last_cycle) + packet_in_progress <= 1'b0; + end + end + + + // ------------------------------------------ + // Shares + // + // Special case: all-equal shares _should_ be optimized into assigning a + // constant to next_grant_share. + // Special case: all-1's shares _should_ result in the share counter + // being optimized away. + // ------------------------------------------ + // Input | arb shares | counter load value + // 0 | 1 | 0 + // 1 | 1 | 0 + wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0; + + // ------------------------------------------ + // Choose the share value corresponding to the grant. + // ------------------------------------------ + reg [SHARE_COUNTER_W - 1 : 0] next_grant_share; + always @* begin + next_grant_share = + share_0 & { SHARE_COUNTER_W {next_grant[0]} } | + share_1 & { SHARE_COUNTER_W {next_grant[1]} }; + end + + // ------------------------------------------ + // Flag to indicate first packet of an arb sequence. + // ------------------------------------------ + wire grant_changed = ~packet_in_progress && !(saved_grant & valid); + reg first_packet_r; + wire first_packet = grant_changed | first_packet_r; + always @(posedge clk or posedge reset) begin + if (reset) begin + first_packet_r <= 1'b0; + end + else begin + if (update_grant) + first_packet_r <= 1'b1; + else if (last_cycle) + first_packet_r <= 1'b0; + else if (grant_changed) + first_packet_r <= 1'b1; + end + end + + // ------------------------------------------ + // Compute the next share-count value. + // ------------------------------------------ + reg [SHARE_COUNTER_W - 1 : 0] p1_share_count; + reg [SHARE_COUNTER_W - 1 : 0] share_count; + reg share_count_zero_flag; + + always @* begin + if (first_packet) begin + p1_share_count = next_grant_share; + end + else begin + // Update the counter, but don't decrement below 0. + p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1; + end + end + + // ------------------------------------------ + // Update the share counter and share-counter=zero flag. + // ------------------------------------------ + always @(posedge clk or posedge reset) begin + if (reset) begin + share_count <= '0; + share_count_zero_flag <= 1'b1; + end + else begin + if (last_cycle) begin + share_count <= p1_share_count; + share_count_zero_flag <= (p1_share_count == '0); + end + end + end + + // ------------------------------------------ + // For each input, maintain a final_packet signal which goes active for the + // last packet of a full-share packet sequence. Example: if I have 4 + // shares and I'm continuously requesting, final_packet is active in the + // 4th packet. + // ------------------------------------------ + wire final_packet_0 = 1'b1; + + wire final_packet_1 = 1'b1; + + + // ------------------------------------------ + // Concatenate all final_packet signals (wire or reg) into a handy vector. + // ------------------------------------------ + wire [NUM_INPUTS - 1 : 0] final_packet = { + final_packet_1, + final_packet_0 + }; + + // ------------------------------------------ + // ------------------------------------------ + wire p1_done = |(final_packet & grant); + + // ------------------------------------------ + // Flag for the first cycle of packets within an + // arb sequence + // ------------------------------------------ + reg first_cycle; + always @(posedge clk, posedge reset) begin + if (reset) + first_cycle <= 0; + else + first_cycle <= last_cycle && ~p1_done; + end + + + always @* begin + update_grant = 0; + + // ------------------------------------------ + // No arbitration pipeline, update grant whenever + // the current arb winner has consumed all shares, + // or all requests are low + // ------------------------------------------ + update_grant = (last_cycle && p1_done) || (first_cycle && !valid); + update_grant = last_cycle; + end + + wire save_grant; + assign save_grant = 1; + assign grant = next_grant; + + always @(posedge clk, posedge reset) begin + if (reset) + saved_grant <= '0; + else if (save_grant) + saved_grant <= next_grant; + end + + // ------------------------------------------ + // ------------------------------------------ + // Arbitrator + // ------------------------------------------ + // ------------------------------------------ + + // ------------------------------------------ + // Create a request vector that stays high during + // the packet for unpipelined arbitration. + // + // The pipelined arbitration scheme does not require + // request to be held high during the packet. + // ------------------------------------------ + assign request = valid; + + + altera_merlin_arbitrator + #( + .NUM_REQUESTERS(NUM_INPUTS), + .SCHEME ("no-arb"), + .PIPELINE (0) + ) arb ( + .clk (clk), + .reset (reset), + .request (request), + .grant (next_grant), + .save_top_priority (src_valid), + .increment_top_priority (update_grant) + ); + + // ------------------------------------------ + // ------------------------------------------ + // Mux + // + // Implemented as a sum of products. + // ------------------------------------------ + // ------------------------------------------ + + assign sink0_ready = src_ready && grant[0]; + assign sink1_ready = src_ready && grant[1]; + + assign src_valid = |(grant & valid); + + always @* begin + src_payload = + sink0_payload & {PAYLOAD_W {grant[0]} } | + sink1_payload & {PAYLOAD_W {grant[1]} }; + end + + // ------------------------------------------ + // Mux Payload Mapping + // ------------------------------------------ + + assign sink0_payload = {sink0_channel,sink0_data, + sink0_startofpacket,sink0_endofpacket}; + assign sink1_payload = {sink1_channel,sink1_data, + sink1_startofpacket,sink1_endofpacket}; + + assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload; + +endmodule + + + diff --git a/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_rsp_xbar_mux_001.sv b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_rsp_xbar_mux_001.sv new file mode 100644 index 00000000..67d6f462 --- /dev/null +++ b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_rsp_xbar_mux_001.sv @@ -0,0 +1,511 @@ +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/12.1sp1/ip/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer.sv.terp#1 $ +// $Revision: #1 $ +// $Date: 2012/10/10 $ +// $Author: swbranch $ + +// ------------------------------------------ +// Merlin Multiplexer +// ------------------------------------------ + +`timescale 1 ns / 1 ns + + +// ------------------------------------------ +// Generation parameters: +// output_name: system_rsp_xbar_mux_001 +// NUM_INPUTS: 11 +// ARBITRATION_SHARES: 1 1 1 1 1 1 1 1 1 1 1 +// ARBITRATION_SCHEME "no-arb" +// PIPELINE_ARB: 0 +// PKT_TRANS_LOCK: 66 (arbitration locking enabled) +// ST_DATA_W: 101 +// ST_CHANNEL_W: 11 +// ------------------------------------------ + +module system_rsp_xbar_mux_001 +( + // ---------------------- + // Sinks + // ---------------------- + input sink0_valid, + input [101-1 : 0] sink0_data, + input [11-1: 0] sink0_channel, + input sink0_startofpacket, + input sink0_endofpacket, + output sink0_ready, + + input sink1_valid, + input [101-1 : 0] sink1_data, + input [11-1: 0] sink1_channel, + input sink1_startofpacket, + input sink1_endofpacket, + output sink1_ready, + + input sink2_valid, + input [101-1 : 0] sink2_data, + input [11-1: 0] sink2_channel, + input sink2_startofpacket, + input sink2_endofpacket, + output sink2_ready, + + input sink3_valid, + input [101-1 : 0] sink3_data, + input [11-1: 0] sink3_channel, + input sink3_startofpacket, + input sink3_endofpacket, + output sink3_ready, + + input sink4_valid, + input [101-1 : 0] sink4_data, + input [11-1: 0] sink4_channel, + input sink4_startofpacket, + input sink4_endofpacket, + output sink4_ready, + + input sink5_valid, + input [101-1 : 0] sink5_data, + input [11-1: 0] sink5_channel, + input sink5_startofpacket, + input sink5_endofpacket, + output sink5_ready, + + input sink6_valid, + input [101-1 : 0] sink6_data, + input [11-1: 0] sink6_channel, + input sink6_startofpacket, + input sink6_endofpacket, + output sink6_ready, + + input sink7_valid, + input [101-1 : 0] sink7_data, + input [11-1: 0] sink7_channel, + input sink7_startofpacket, + input sink7_endofpacket, + output sink7_ready, + + input sink8_valid, + input [101-1 : 0] sink8_data, + input [11-1: 0] sink8_channel, + input sink8_startofpacket, + input sink8_endofpacket, + output sink8_ready, + + input sink9_valid, + input [101-1 : 0] sink9_data, + input [11-1: 0] sink9_channel, + input sink9_startofpacket, + input sink9_endofpacket, + output sink9_ready, + + input sink10_valid, + input [101-1 : 0] sink10_data, + input [11-1: 0] sink10_channel, + input sink10_startofpacket, + input sink10_endofpacket, + output sink10_ready, + + + // ---------------------- + // Source + // ---------------------- + output src_valid, + output [101-1 : 0] src_data, + output [11-1 : 0] src_channel, + output src_startofpacket, + output src_endofpacket, + input src_ready, + + // ---------------------- + // Clock & Reset + // ---------------------- + input clk, + input reset +); + localparam PAYLOAD_W = 101 + 11 + 2; + localparam NUM_INPUTS = 11; + localparam SHARE_COUNTER_W = 1; + localparam PIPELINE_ARB = 0; + localparam ST_DATA_W = 101; + localparam ST_CHANNEL_W = 11; + localparam PKT_TRANS_LOCK = 66; + + // ------------------------------------------ + // Signals + // ------------------------------------------ + wire [NUM_INPUTS - 1 : 0] request; + wire [NUM_INPUTS - 1 : 0] valid; + wire [NUM_INPUTS - 1 : 0] grant; + wire [NUM_INPUTS - 1 : 0] next_grant; + reg [NUM_INPUTS - 1 : 0] saved_grant; + reg [PAYLOAD_W - 1 : 0] src_payload; + wire last_cycle; + reg packet_in_progress; + reg update_grant; + + wire [PAYLOAD_W - 1 : 0] sink0_payload; + wire [PAYLOAD_W - 1 : 0] sink1_payload; + wire [PAYLOAD_W - 1 : 0] sink2_payload; + wire [PAYLOAD_W - 1 : 0] sink3_payload; + wire [PAYLOAD_W - 1 : 0] sink4_payload; + wire [PAYLOAD_W - 1 : 0] sink5_payload; + wire [PAYLOAD_W - 1 : 0] sink6_payload; + wire [PAYLOAD_W - 1 : 0] sink7_payload; + wire [PAYLOAD_W - 1 : 0] sink8_payload; + wire [PAYLOAD_W - 1 : 0] sink9_payload; + wire [PAYLOAD_W - 1 : 0] sink10_payload; + + assign valid[0] = sink0_valid; + assign valid[1] = sink1_valid; + assign valid[2] = sink2_valid; + assign valid[3] = sink3_valid; + assign valid[4] = sink4_valid; + assign valid[5] = sink5_valid; + assign valid[6] = sink6_valid; + assign valid[7] = sink7_valid; + assign valid[8] = sink8_valid; + assign valid[9] = sink9_valid; + assign valid[10] = sink10_valid; + + + // ------------------------------------------ + // ------------------------------------------ + // Grant Logic & Updates + // ------------------------------------------ + // ------------------------------------------ + reg [NUM_INPUTS - 1 : 0] lock; + always @* begin + lock[0] = sink0_data[66]; + lock[1] = sink1_data[66]; + lock[2] = sink2_data[66]; + lock[3] = sink3_data[66]; + lock[4] = sink4_data[66]; + lock[5] = sink5_data[66]; + lock[6] = sink6_data[66]; + lock[7] = sink7_data[66]; + lock[8] = sink8_data[66]; + lock[9] = sink9_data[66]; + lock[10] = sink10_data[66]; + end + + assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant)); + + // ------------------------------------------ + // We're working on a packet at any time valid is high, except + // when this is the endofpacket. + // ------------------------------------------ + always @(posedge clk or posedge reset) begin + if (reset) begin + packet_in_progress <= 1'b0; + end + else begin + if (src_valid) + packet_in_progress <= 1'b1; + if (last_cycle) + packet_in_progress <= 1'b0; + end + end + + + // ------------------------------------------ + // Shares + // + // Special case: all-equal shares _should_ be optimized into assigning a + // constant to next_grant_share. + // Special case: all-1's shares _should_ result in the share counter + // being optimized away. + // ------------------------------------------ + // Input | arb shares | counter load value + // 0 | 1 | 0 + // 1 | 1 | 0 + // 2 | 1 | 0 + // 3 | 1 | 0 + // 4 | 1 | 0 + // 5 | 1 | 0 + // 6 | 1 | 0 + // 7 | 1 | 0 + // 8 | 1 | 0 + // 9 | 1 | 0 + // 10 | 1 | 0 + wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_2 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_3 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_4 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_5 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_6 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_7 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_8 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_9 = 1'd0; + wire [SHARE_COUNTER_W - 1 : 0] share_10 = 1'd0; + + // ------------------------------------------ + // Choose the share value corresponding to the grant. + // ------------------------------------------ + reg [SHARE_COUNTER_W - 1 : 0] next_grant_share; + always @* begin + next_grant_share = + share_0 & { SHARE_COUNTER_W {next_grant[0]} } | + share_1 & { SHARE_COUNTER_W {next_grant[1]} } | + share_2 & { SHARE_COUNTER_W {next_grant[2]} } | + share_3 & { SHARE_COUNTER_W {next_grant[3]} } | + share_4 & { SHARE_COUNTER_W {next_grant[4]} } | + share_5 & { SHARE_COUNTER_W {next_grant[5]} } | + share_6 & { SHARE_COUNTER_W {next_grant[6]} } | + share_7 & { SHARE_COUNTER_W {next_grant[7]} } | + share_8 & { SHARE_COUNTER_W {next_grant[8]} } | + share_9 & { SHARE_COUNTER_W {next_grant[9]} } | + share_10 & { SHARE_COUNTER_W {next_grant[10]} }; + end + + // ------------------------------------------ + // Flag to indicate first packet of an arb sequence. + // ------------------------------------------ + wire grant_changed = ~packet_in_progress && !(saved_grant & valid); + reg first_packet_r; + wire first_packet = grant_changed | first_packet_r; + always @(posedge clk or posedge reset) begin + if (reset) begin + first_packet_r <= 1'b0; + end + else begin + if (update_grant) + first_packet_r <= 1'b1; + else if (last_cycle) + first_packet_r <= 1'b0; + else if (grant_changed) + first_packet_r <= 1'b1; + end + end + + // ------------------------------------------ + // Compute the next share-count value. + // ------------------------------------------ + reg [SHARE_COUNTER_W - 1 : 0] p1_share_count; + reg [SHARE_COUNTER_W - 1 : 0] share_count; + reg share_count_zero_flag; + + always @* begin + if (first_packet) begin + p1_share_count = next_grant_share; + end + else begin + // Update the counter, but don't decrement below 0. + p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1; + end + end + + // ------------------------------------------ + // Update the share counter and share-counter=zero flag. + // ------------------------------------------ + always @(posedge clk or posedge reset) begin + if (reset) begin + share_count <= '0; + share_count_zero_flag <= 1'b1; + end + else begin + if (last_cycle) begin + share_count <= p1_share_count; + share_count_zero_flag <= (p1_share_count == '0); + end + end + end + + // ------------------------------------------ + // For each input, maintain a final_packet signal which goes active for the + // last packet of a full-share packet sequence. Example: if I have 4 + // shares and I'm continuously requesting, final_packet is active in the + // 4th packet. + // ------------------------------------------ + wire final_packet_0 = 1'b1; + + wire final_packet_1 = 1'b1; + + wire final_packet_2 = 1'b1; + + wire final_packet_3 = 1'b1; + + wire final_packet_4 = 1'b1; + + wire final_packet_5 = 1'b1; + + wire final_packet_6 = 1'b1; + + wire final_packet_7 = 1'b1; + + wire final_packet_8 = 1'b1; + + wire final_packet_9 = 1'b1; + + wire final_packet_10 = 1'b1; + + + // ------------------------------------------ + // Concatenate all final_packet signals (wire or reg) into a handy vector. + // ------------------------------------------ + wire [NUM_INPUTS - 1 : 0] final_packet = { + final_packet_10, + final_packet_9, + final_packet_8, + final_packet_7, + final_packet_6, + final_packet_5, + final_packet_4, + final_packet_3, + final_packet_2, + final_packet_1, + final_packet_0 + }; + + // ------------------------------------------ + // ------------------------------------------ + wire p1_done = |(final_packet & grant); + + // ------------------------------------------ + // Flag for the first cycle of packets within an + // arb sequence + // ------------------------------------------ + reg first_cycle; + always @(posedge clk, posedge reset) begin + if (reset) + first_cycle <= 0; + else + first_cycle <= last_cycle && ~p1_done; + end + + + always @* begin + update_grant = 0; + + // ------------------------------------------ + // No arbitration pipeline, update grant whenever + // the current arb winner has consumed all shares, + // or all requests are low + // ------------------------------------------ + update_grant = (last_cycle && p1_done) || (first_cycle && !valid); + update_grant = last_cycle; + end + + wire save_grant; + assign save_grant = 1; + assign grant = next_grant; + + always @(posedge clk, posedge reset) begin + if (reset) + saved_grant <= '0; + else if (save_grant) + saved_grant <= next_grant; + end + + // ------------------------------------------ + // ------------------------------------------ + // Arbitrator + // ------------------------------------------ + // ------------------------------------------ + + // ------------------------------------------ + // Create a request vector that stays high during + // the packet for unpipelined arbitration. + // + // The pipelined arbitration scheme does not require + // request to be held high during the packet. + // ------------------------------------------ + assign request = valid; + + + altera_merlin_arbitrator + #( + .NUM_REQUESTERS(NUM_INPUTS), + .SCHEME ("no-arb"), + .PIPELINE (0) + ) arb ( + .clk (clk), + .reset (reset), + .request (request), + .grant (next_grant), + .save_top_priority (src_valid), + .increment_top_priority (update_grant) + ); + + // ------------------------------------------ + // ------------------------------------------ + // Mux + // + // Implemented as a sum of products. + // ------------------------------------------ + // ------------------------------------------ + + assign sink0_ready = src_ready && grant[0]; + assign sink1_ready = src_ready && grant[1]; + assign sink2_ready = src_ready && grant[2]; + assign sink3_ready = src_ready && grant[3]; + assign sink4_ready = src_ready && grant[4]; + assign sink5_ready = src_ready && grant[5]; + assign sink6_ready = src_ready && grant[6]; + assign sink7_ready = src_ready && grant[7]; + assign sink8_ready = src_ready && grant[8]; + assign sink9_ready = src_ready && grant[9]; + assign sink10_ready = src_ready && grant[10]; + + assign src_valid = |(grant & valid); + + always @* begin + src_payload = + sink0_payload & {PAYLOAD_W {grant[0]} } | + sink1_payload & {PAYLOAD_W {grant[1]} } | + sink2_payload & {PAYLOAD_W {grant[2]} } | + sink3_payload & {PAYLOAD_W {grant[3]} } | + sink4_payload & {PAYLOAD_W {grant[4]} } | + sink5_payload & {PAYLOAD_W {grant[5]} } | + sink6_payload & {PAYLOAD_W {grant[6]} } | + sink7_payload & {PAYLOAD_W {grant[7]} } | + sink8_payload & {PAYLOAD_W {grant[8]} } | + sink9_payload & {PAYLOAD_W {grant[9]} } | + sink10_payload & {PAYLOAD_W {grant[10]} }; + end + + // ------------------------------------------ + // Mux Payload Mapping + // ------------------------------------------ + + assign sink0_payload = {sink0_channel,sink0_data, + sink0_startofpacket,sink0_endofpacket}; + assign sink1_payload = {sink1_channel,sink1_data, + sink1_startofpacket,sink1_endofpacket}; + assign sink2_payload = {sink2_channel,sink2_data, + sink2_startofpacket,sink2_endofpacket}; + assign sink3_payload = {sink3_channel,sink3_data, + sink3_startofpacket,sink3_endofpacket}; + assign sink4_payload = {sink4_channel,sink4_data, + sink4_startofpacket,sink4_endofpacket}; + assign sink5_payload = {sink5_channel,sink5_data, + sink5_startofpacket,sink5_endofpacket}; + assign sink6_payload = {sink6_channel,sink6_data, + sink6_startofpacket,sink6_endofpacket}; + assign sink7_payload = {sink7_channel,sink7_data, + sink7_startofpacket,sink7_endofpacket}; + assign sink8_payload = {sink8_channel,sink8_data, + sink8_startofpacket,sink8_endofpacket}; + assign sink9_payload = {sink9_channel,sink9_data, + sink9_startofpacket,sink9_endofpacket}; + assign sink10_payload = {sink10_channel,sink10_data, + sink10_startofpacket,sink10_endofpacket}; + + assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload; + +endmodule + + + diff --git a/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_sdram.v b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_sdram.v new file mode 100644 index 00000000..0f54691d --- /dev/null +++ b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_sdram.v @@ -0,0 +1,720 @@ +//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module system_sdram_input_efifo_module ( + // inputs: + clk, + rd, + reset_n, + wr, + wr_data, + + // outputs: + almost_empty, + almost_full, + empty, + full, + rd_data + ) +; + + output almost_empty; + output almost_full; + output empty; + output full; + output [ 41: 0] rd_data; + input clk; + input rd; + input reset_n; + input wr; + input [ 41: 0] wr_data; + + wire almost_empty; + wire almost_full; + wire empty; + reg [ 1: 0] entries; + reg [ 41: 0] entry_0; + reg [ 41: 0] entry_1; + wire full; + reg rd_address; + reg [ 41: 0] rd_data; + wire [ 1: 0] rdwr; + reg wr_address; + assign rdwr = {rd, wr}; + assign full = entries == 2; + assign almost_full = entries >= 1; + assign empty = entries == 0; + assign almost_empty = entries <= 1; + always @(entry_0 or entry_1 or rd_address) + begin + case (rd_address) // synthesis parallel_case full_case + + 1'd0: begin + rd_data = entry_0; + end // 1'd0 + + 1'd1: begin + rd_data = entry_1; + end // 1'd1 + + default: begin + end // default + + endcase // rd_address + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + begin + wr_address <= 0; + rd_address <= 0; + entries <= 0; + end + else + case (rdwr) // synthesis parallel_case full_case + + 2'd1: begin + // Write data + if (!full) + begin + entries <= entries + 1; + wr_address <= (wr_address == 1) ? 0 : (wr_address + 1); + end + end // 2'd1 + + 2'd2: begin + // Read data + if (!empty) + begin + entries <= entries - 1; + rd_address <= (rd_address == 1) ? 0 : (rd_address + 1); + end + end // 2'd2 + + 2'd3: begin + wr_address <= (wr_address == 1) ? 0 : (wr_address + 1); + rd_address <= (rd_address == 1) ? 0 : (rd_address + 1); + end // 2'd3 + + default: begin + end // default + + endcase // rdwr + end + + + always @(posedge clk) + begin + //Write data + if (wr & !full) + case (wr_address) // synthesis parallel_case full_case + + 1'd0: begin + entry_0 <= wr_data; + end // 1'd0 + + 1'd1: begin + entry_1 <= wr_data; + end // 1'd1 + + default: begin + end // default + + endcase // wr_address + end + + + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module system_sdram ( + // inputs: + az_addr, + az_be_n, + az_cs, + az_data, + az_rd_n, + az_wr_n, + clk, + reset_n, + + // outputs: + za_data, + za_valid, + za_waitrequest, + zs_addr, + zs_ba, + zs_cas_n, + zs_cke, + zs_cs_n, + zs_dq, + zs_dqm, + zs_ras_n, + zs_we_n + ) +; + + output [ 15: 0] za_data; + output za_valid; + output za_waitrequest; + output [ 12: 0] zs_addr; + output [ 1: 0] zs_ba; + output zs_cas_n; + output zs_cke; + output zs_cs_n; + inout [ 15: 0] zs_dq; + output [ 1: 0] zs_dqm; + output zs_ras_n; + output zs_we_n; + input [ 22: 0] az_addr; + input [ 1: 0] az_be_n; + input az_cs; + input [ 15: 0] az_data; + input az_rd_n; + input az_wr_n; + input clk; + input reset_n; + + wire [ 23: 0] CODE; + reg ack_refresh_request; + reg [ 22: 0] active_addr; + wire [ 1: 0] active_bank; + reg active_cs_n; + reg [ 15: 0] active_data; + reg [ 1: 0] active_dqm; + reg active_rnw; + wire almost_empty; + wire almost_full; + wire bank_match; + wire [ 7: 0] cas_addr; + wire clk_en; + wire [ 3: 0] cmd_all; + wire [ 2: 0] cmd_code; + wire cs_n; + wire csn_decode; + wire csn_match; + wire [ 22: 0] f_addr; + wire [ 1: 0] f_bank; + wire f_cs_n; + wire [ 15: 0] f_data; + wire [ 1: 0] f_dqm; + wire f_empty; + reg f_pop; + wire f_rnw; + wire f_select; + wire [ 41: 0] fifo_read_data; + reg [ 12: 0] i_addr; + reg [ 3: 0] i_cmd; + reg [ 2: 0] i_count; + reg [ 2: 0] i_next; + reg [ 2: 0] i_refs; + reg [ 2: 0] i_state; + reg init_done; + reg [ 12: 0] m_addr /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */; + reg [ 1: 0] m_bank /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */; + reg [ 3: 0] m_cmd /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */; + reg [ 2: 0] m_count; + reg [ 15: 0] m_data /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON ; FAST_OUTPUT_ENABLE_REGISTER=ON" */; + reg [ 1: 0] m_dqm /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */; + reg [ 8: 0] m_next; + reg [ 8: 0] m_state; + reg oe /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_ENABLE_REGISTER=ON" */; + wire pending; + wire rd_strobe; + reg [ 2: 0] rd_valid; + reg [ 14: 0] refresh_counter; + reg refresh_request; + wire rnw_match; + wire row_match; + wire [ 23: 0] txt_code; + reg za_cannotrefresh; + reg [ 15: 0] za_data /* synthesis ALTERA_ATTRIBUTE = "FAST_INPUT_REGISTER=ON" */; + reg za_valid; + wire za_waitrequest; + wire [ 12: 0] zs_addr; + wire [ 1: 0] zs_ba; + wire zs_cas_n; + wire zs_cke; + wire zs_cs_n; + wire [ 15: 0] zs_dq; + wire [ 1: 0] zs_dqm; + wire zs_ras_n; + wire zs_we_n; + assign clk_en = 1; + //s1, which is an e_avalon_slave + assign {zs_cs_n, zs_ras_n, zs_cas_n, zs_we_n} = m_cmd; + assign zs_addr = m_addr; + assign zs_cke = clk_en; + assign zs_dq = oe?m_data:{16{1'bz}}; + assign zs_dqm = m_dqm; + assign zs_ba = m_bank; + assign f_select = f_pop & pending; + assign f_cs_n = 1'b0; + assign cs_n = f_select ? f_cs_n : active_cs_n; + assign csn_decode = cs_n; + assign {f_rnw, f_addr, f_dqm, f_data} = fifo_read_data; + system_sdram_input_efifo_module the_system_sdram_input_efifo_module + ( + .almost_empty (almost_empty), + .almost_full (almost_full), + .clk (clk), + .empty (f_empty), + .full (za_waitrequest), + .rd (f_select), + .rd_data (fifo_read_data), + .reset_n (reset_n), + .wr ((~az_wr_n | ~az_rd_n) & !za_waitrequest), + .wr_data ({az_wr_n, az_addr, az_wr_n ? 2'b0 : az_be_n, az_data}) + ); + + assign f_bank = {f_addr[22],f_addr[8]}; + // Refresh/init counter. + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + refresh_counter <= 20000; + else if (refresh_counter == 0) + refresh_counter <= 781; + else + refresh_counter <= refresh_counter - 1'b1; + end + + + // Refresh request signal. + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + refresh_request <= 0; + else if (1) + refresh_request <= ((refresh_counter == 0) | refresh_request) & ~ack_refresh_request & init_done; + end + + + // Generate an Interrupt if two ref_reqs occur before one ack_refresh_request + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + za_cannotrefresh <= 0; + else if (1) + za_cannotrefresh <= (refresh_counter == 0) & refresh_request; + end + + + // Initialization-done flag. + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + init_done <= 0; + else if (1) + init_done <= init_done | (i_state == 3'b101); + end + + + // **** Init FSM **** + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + begin + i_state <= 3'b000; + i_next <= 3'b000; + i_cmd <= 4'b1111; + i_addr <= {13{1'b1}}; + i_count <= {3{1'b0}}; + end + else + begin + i_addr <= {13{1'b1}}; + case (i_state) // synthesis parallel_case full_case + + 3'b000: begin + i_cmd <= 4'b1111; + i_refs <= 3'b0; + //Wait for refresh count-down after reset + if (refresh_counter == 0) + i_state <= 3'b001; + end // 3'b000 + + 3'b001: begin + i_state <= 3'b011; + i_cmd <= {{1{1'b0}},3'h2}; + i_count <= 1; + i_next <= 3'b010; + end // 3'b001 + + 3'b010: begin + i_cmd <= {{1{1'b0}},3'h1}; + i_refs <= i_refs + 1'b1; + i_state <= 3'b011; + i_count <= 7; + // Count up init_refresh_commands + if (i_refs == 3'h7) + i_next <= 3'b111; + else + i_next <= 3'b010; + end // 3'b010 + + 3'b011: begin + i_cmd <= {{1{1'b0}},3'h7}; + //WAIT til safe to Proceed... + if (i_count > 1) + i_count <= i_count - 1'b1; + else + i_state <= i_next; + end // 3'b011 + + 3'b101: begin + i_state <= 3'b101; + end // 3'b101 + + 3'b111: begin + i_state <= 3'b011; + i_cmd <= {{1{1'b0}},3'h0}; + i_addr <= {{3{1'b0}},1'b0,2'b00,3'h3,4'h0}; + i_count <= 4; + i_next <= 3'b101; + end // 3'b111 + + default: begin + i_state <= 3'b000; + end // default + + endcase // i_state + end + end + + + assign active_bank = {active_addr[22],active_addr[8]}; + assign csn_match = active_cs_n == f_cs_n; + assign rnw_match = active_rnw == f_rnw; + assign bank_match = active_bank == f_bank; + assign row_match = {active_addr[21 : 9]} == {f_addr[21 : 9]}; + assign pending = csn_match && rnw_match && bank_match && row_match && !f_empty; + assign cas_addr = f_select ? { {5{1'b0}},f_addr[7 : 0] } : { {5{1'b0}},active_addr[7 : 0] }; + // **** Main FSM **** + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + begin + m_state <= 9'b000000001; + m_next <= 9'b000000001; + m_cmd <= 4'b1111; + m_bank <= 2'b00; + m_addr <= 13'b0000000000000; + m_data <= 16'b0000000000000000; + m_dqm <= 2'b00; + m_count <= 3'b000; + ack_refresh_request <= 1'b0; + f_pop <= 1'b0; + oe <= 1'b0; + end + else + begin + f_pop <= 1'b0; + oe <= 1'b0; + case (m_state) // synthesis parallel_case full_case + + 9'b000000001: begin + //Wait for init-fsm to be done... + if (init_done) + begin + //Hold bus if another cycle ended to arf. + if (refresh_request) + m_cmd <= {{1{1'b0}},3'h7}; + else + m_cmd <= 4'b1111; + ack_refresh_request <= 1'b0; + //Wait for a read/write request. + if (refresh_request) + begin + m_state <= 9'b001000000; + m_next <= 9'b010000000; + m_count <= 1; + active_cs_n <= 1'b1; + end + else if (!f_empty) + begin + f_pop <= 1'b1; + active_cs_n <= f_cs_n; + active_rnw <= f_rnw; + active_addr <= f_addr; + active_data <= f_data; + active_dqm <= f_dqm; + m_state <= 9'b000000010; + end + end + else + begin + m_addr <= i_addr; + m_state <= 9'b000000001; + m_next <= 9'b000000001; + m_cmd <= i_cmd; + end + end // 9'b000000001 + + 9'b000000010: begin + m_state <= 9'b000000100; + m_cmd <= {csn_decode,3'h3}; + m_bank <= active_bank; + m_addr <= active_addr[21 : 9]; + m_data <= active_data; + m_dqm <= active_dqm; + m_count <= 2; + m_next <= active_rnw ? 9'b000001000 : 9'b000010000; + end // 9'b000000010 + + 9'b000000100: begin + // precharge all if arf, else precharge csn_decode + if (m_next == 9'b010000000) + m_cmd <= {{1{1'b0}},3'h7}; + else + m_cmd <= {csn_decode,3'h7}; + //Count down til safe to Proceed... + if (m_count > 1) + m_count <= m_count - 1'b1; + else + m_state <= m_next; + end // 9'b000000100 + + 9'b000001000: begin + m_cmd <= {csn_decode,3'h5}; + m_bank <= f_select ? f_bank : active_bank; + m_dqm <= f_select ? f_dqm : active_dqm; + m_addr <= cas_addr; + //Do we have a transaction pending? + if (pending) + begin + //if we need to ARF, bail, else spin + if (refresh_request) + begin + m_state <= 9'b000000100; + m_next <= 9'b000000001; + m_count <= 2; + end + else + begin + f_pop <= 1'b1; + active_cs_n <= f_cs_n; + active_rnw <= f_rnw; + active_addr <= f_addr; + active_data <= f_data; + active_dqm <= f_dqm; + end + end + else + begin + //correctly end RD spin cycle if fifo mt + if (~pending & f_pop) + m_cmd <= {csn_decode,3'h7}; + m_state <= 9'b100000000; + end + end // 9'b000001000 + + 9'b000010000: begin + m_cmd <= {csn_decode,3'h4}; + oe <= 1'b1; + m_data <= f_select ? f_data : active_data; + m_dqm <= f_select ? f_dqm : active_dqm; + m_bank <= f_select ? f_bank : active_bank; + m_addr <= cas_addr; + //Do we have a transaction pending? + if (pending) + begin + //if we need to ARF, bail, else spin + if (refresh_request) + begin + m_state <= 9'b000000100; + m_next <= 9'b000000001; + m_count <= 2; + end + else + begin + f_pop <= 1'b1; + active_cs_n <= f_cs_n; + active_rnw <= f_rnw; + active_addr <= f_addr; + active_data <= f_data; + active_dqm <= f_dqm; + end + end + else + begin + //correctly end WR spin cycle if fifo empty + if (~pending & f_pop) + begin + m_cmd <= {csn_decode,3'h7}; + oe <= 1'b0; + end + m_state <= 9'b100000000; + end + end // 9'b000010000 + + 9'b000100000: begin + m_cmd <= {csn_decode,3'h7}; + //Count down til safe to Proceed... + if (m_count > 1) + m_count <= m_count - 1'b1; + else + begin + m_state <= 9'b001000000; + m_count <= 1; + end + end // 9'b000100000 + + 9'b001000000: begin + m_state <= 9'b000000100; + m_addr <= {13{1'b1}}; + // precharge all if arf, else precharge csn_decode + if (refresh_request) + m_cmd <= {{1{1'b0}},3'h2}; + else + m_cmd <= {csn_decode,3'h2}; + end // 9'b001000000 + + 9'b010000000: begin + ack_refresh_request <= 1'b1; + m_state <= 9'b000000100; + m_cmd <= {{1{1'b0}},3'h1}; + m_count <= 7; + m_next <= 9'b000000001; + end // 9'b010000000 + + 9'b100000000: begin + m_cmd <= {csn_decode,3'h7}; + //if we need to ARF, bail, else spin + if (refresh_request) + begin + m_state <= 9'b000000100; + m_next <= 9'b000000001; + m_count <= 1; + end + else //wait for fifo to have contents + if (!f_empty) + //Are we 'pending' yet? + if (csn_match && rnw_match && bank_match && row_match) + begin + m_state <= f_rnw ? 9'b000001000 : 9'b000010000; + f_pop <= 1'b1; + active_cs_n <= f_cs_n; + active_rnw <= f_rnw; + active_addr <= f_addr; + active_data <= f_data; + active_dqm <= f_dqm; + end + else + begin + m_state <= 9'b000100000; + m_next <= 9'b000000001; + m_count <= 1; + end + end // 9'b100000000 + + // synthesis translate_off + + default: begin + m_state <= m_state; + m_cmd <= 4'b1111; + f_pop <= 1'b0; + oe <= 1'b0; + end // default + + // synthesis translate_on + endcase // m_state + end + end + + + assign rd_strobe = m_cmd[2 : 0] == 3'h5; + //Track RD Req's based on cas_latency w/shift reg + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + rd_valid <= {3{1'b0}}; + else + rd_valid <= (rd_valid << 1) | { {2{1'b0}}, rd_strobe }; + end + + + // Register dq data. + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + za_data <= 0; + else + za_data <= zs_dq; + end + + + // Delay za_valid to match registered data. + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + za_valid <= 0; + else if (1) + za_valid <= rd_valid[2]; + end + + + assign cmd_code = m_cmd[2 : 0]; + assign cmd_all = m_cmd; + +//synthesis translate_off +//////////////// SIMULATION-ONLY CONTENTS +initial + begin + $write("\n"); + $write("This reference design requires a vendor simulation model.\n"); + $write("To simulate accesses to SDRAM, you must:\n"); + $write(" - Download the vendor model\n"); + $write(" - Install the model in the system_sim directory\n"); + $write(" - `include the vendor model in the the top-level system file,\n"); + $write(" - Instantiate sdram simulation models and wire them to testbench signals\n"); + $write(" - Be aware that you may have to disable some timing checks in the vendor model\n"); + $write(" (because this simulation is zero-delay based)\n"); + $write("\n"); + end + assign txt_code = (cmd_code == 3'h0)? 24'h4c4d52 : + (cmd_code == 3'h1)? 24'h415246 : + (cmd_code == 3'h2)? 24'h505245 : + (cmd_code == 3'h3)? 24'h414354 : + (cmd_code == 3'h4)? 24'h205752 : + (cmd_code == 3'h5)? 24'h205244 : + (cmd_code == 3'h6)? 24'h425354 : + (cmd_code == 3'h7)? 24'h4e4f50 : + 24'h424144; + + assign CODE = &(cmd_all|4'h7) ? 24'h494e48 : txt_code; + +//////////////// END SIMULATION-ONLY CONTENTS + +//synthesis translate_on + +endmodule + diff --git a/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_spi_0.v b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_spi_0.v new file mode 100644 index 00000000..9cef516b --- /dev/null +++ b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_spi_0.v @@ -0,0 +1,414 @@ +//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +//Register map: +//addr register type +//0 read data r +//1 write data w +//2 status r/w +//3 control r/w +//4 reserved +//5 slave-enable r/w +//6 end-of-packet-value r/w +//INPUT_CLOCK: 100000000 +//ISMASTER: 1 +//DATABITS: 8 +//TARGETCLOCK: 1536000 +//NUMSLAVES: 1 +//CPOL: 0 +//CPHA: 0 +//LSBFIRST: 0 +//EXTRADELAY: 0 +//TARGETSSDELAY: 0 + +module system_spi_0 ( + // inputs: + MISO, + clk, + data_from_cpu, + mem_addr, + read_n, + reset_n, + spi_select, + write_n, + + // outputs: + MOSI, + SCLK, + SS_n, + data_to_cpu, + dataavailable, + endofpacket, + irq, + readyfordata + ) +; + + output MOSI; + output SCLK; + output SS_n; + output [ 15: 0] data_to_cpu; + output dataavailable; + output endofpacket; + output irq; + output readyfordata; + input MISO; + input clk; + input [ 15: 0] data_from_cpu; + input [ 2: 0] mem_addr; + input read_n; + input reset_n; + input spi_select; + input write_n; + + wire E; + reg EOP; + reg MISO_reg; + wire MOSI; + reg ROE; + reg RRDY; + wire SCLK; + reg SCLK_reg; + reg SSO_reg; + wire SS_n; + wire TMT; + reg TOE; + wire TRDY; + wire control_wr_strobe; + reg data_rd_strobe; + reg [ 15: 0] data_to_cpu; + reg data_wr_strobe; + wire dataavailable; + wire ds_MISO; + wire enableSS; + wire endofpacket; + reg [ 15: 0] endofpacketvalue_reg; + wire endofpacketvalue_wr_strobe; + reg iEOP_reg; + reg iE_reg; + reg iROE_reg; + reg iRRDY_reg; + reg iTMT_reg; + reg iTOE_reg; + reg iTRDY_reg; + wire irq; + reg irq_reg; + wire p1_data_rd_strobe; + wire [ 15: 0] p1_data_to_cpu; + wire p1_data_wr_strobe; + wire p1_rd_strobe; + wire [ 5: 0] p1_slowcount; + wire p1_wr_strobe; + reg rd_strobe; + wire readyfordata; + reg [ 7: 0] rx_holding_reg; + reg [ 7: 0] shift_reg; + wire slaveselect_wr_strobe; + wire slowclock; + reg [ 5: 0] slowcount; + wire [ 10: 0] spi_control; + reg [ 15: 0] spi_slave_select_holding_reg; + reg [ 15: 0] spi_slave_select_reg; + wire [ 10: 0] spi_status; + reg [ 4: 0] state; + reg stateZero; + wire status_wr_strobe; + reg transmitting; + reg tx_holding_primed; + reg [ 7: 0] tx_holding_reg; + reg wr_strobe; + wire write_shift_reg; + wire write_tx_holding; + //spi_control_port, which is an e_avalon_slave + assign p1_rd_strobe = ~rd_strobe & spi_select & ~read_n; + // Read is a two-cycle event. + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + rd_strobe <= 0; + else + rd_strobe <= p1_rd_strobe; + end + + + assign p1_data_rd_strobe = p1_rd_strobe & (mem_addr == 0); + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + data_rd_strobe <= 0; + else + data_rd_strobe <= p1_data_rd_strobe; + end + + + assign p1_wr_strobe = ~wr_strobe & spi_select & ~write_n; + // Write is a two-cycle event. + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + wr_strobe <= 0; + else + wr_strobe <= p1_wr_strobe; + end + + + assign p1_data_wr_strobe = p1_wr_strobe & (mem_addr == 1); + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + data_wr_strobe <= 0; + else + data_wr_strobe <= p1_data_wr_strobe; + end + + + assign control_wr_strobe = wr_strobe & (mem_addr == 3); + assign status_wr_strobe = wr_strobe & (mem_addr == 2); + assign slaveselect_wr_strobe = wr_strobe & (mem_addr == 5); + assign endofpacketvalue_wr_strobe = wr_strobe & (mem_addr == 6); + assign TMT = ~transmitting & ~tx_holding_primed; + assign E = ROE | TOE; + assign spi_status = {EOP, E, RRDY, TRDY, TMT, TOE, ROE, 3'b0}; + // Streaming data ready for pickup. + assign dataavailable = RRDY; + + // Ready to accept streaming data. + assign readyfordata = TRDY; + + // Endofpacket condition detected. + assign endofpacket = EOP; + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + begin + iEOP_reg <= 0; + iE_reg <= 0; + iRRDY_reg <= 0; + iTRDY_reg <= 0; + iTMT_reg <= 0; + iTOE_reg <= 0; + iROE_reg <= 0; + SSO_reg <= 0; + end + else if (control_wr_strobe) + begin + iEOP_reg <= data_from_cpu[9]; + iE_reg <= data_from_cpu[8]; + iRRDY_reg <= data_from_cpu[7]; + iTRDY_reg <= data_from_cpu[6]; + iTMT_reg <= data_from_cpu[5]; + iTOE_reg <= data_from_cpu[4]; + iROE_reg <= data_from_cpu[3]; + SSO_reg <= data_from_cpu[10]; + end + end + + + assign spi_control = {SSO_reg, iEOP_reg, iE_reg, iRRDY_reg, iTRDY_reg, 1'b0, iTOE_reg, iROE_reg, 3'b0}; + // IRQ output. + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + irq_reg <= 0; + else + irq_reg <= (EOP & iEOP_reg) | ((TOE | ROE) & iE_reg) | (RRDY & iRRDY_reg) | (TRDY & iTRDY_reg) | (TOE & iTOE_reg) | (ROE & iROE_reg); + end + + + assign irq = irq_reg; + // Slave select register. + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + spi_slave_select_reg <= 1; + else if (write_shift_reg || control_wr_strobe & data_from_cpu[10] & ~SSO_reg) + spi_slave_select_reg <= spi_slave_select_holding_reg; + end + + + // Slave select holding register. + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + spi_slave_select_holding_reg <= 1; + else if (slaveselect_wr_strobe) + spi_slave_select_holding_reg <= data_from_cpu; + end + + + // slowclock is active once every 33 system clock pulses. + assign slowclock = slowcount == 6'h20; + + assign p1_slowcount = ({6 {(transmitting && !slowclock)}} & (slowcount + 1)) | + ({6 {(~((transmitting && !slowclock)))}} & 0); + + // Divide counter for SPI clock. + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + slowcount <= 0; + else + slowcount <= p1_slowcount; + end + + + // End-of-packet value register. + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + endofpacketvalue_reg <= 0; + else if (endofpacketvalue_wr_strobe) + endofpacketvalue_reg <= data_from_cpu; + end + + + assign p1_data_to_cpu = ((mem_addr == 2))? spi_status : + ((mem_addr == 3))? spi_control : + ((mem_addr == 6))? endofpacketvalue_reg : + ((mem_addr == 5))? spi_slave_select_reg : + rx_holding_reg; + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + data_to_cpu <= 0; + else + // Data to cpu. + data_to_cpu <= p1_data_to_cpu; + + end + + + // 'state' counts from 0 to 17. + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + begin + state <= 0; + stateZero <= 1; + end + else if (transmitting & slowclock) + begin + stateZero <= state == 17; + if (state == 17) + state <= 0; + else + state <= state + 1; + end + end + + + assign enableSS = transmitting & ~stateZero; + assign MOSI = shift_reg[7]; + assign SS_n = (enableSS | SSO_reg) ? ~spi_slave_select_reg : {1 {1'b1} }; + assign SCLK = SCLK_reg; + // As long as there's an empty spot somewhere, + //it's safe to write data. + assign TRDY = ~(transmitting & tx_holding_primed); + + // Enable write to tx_holding_register. + assign write_tx_holding = data_wr_strobe & TRDY; + + // Enable write to shift register. + assign write_shift_reg = tx_holding_primed & ~transmitting; + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + begin + shift_reg <= 0; + rx_holding_reg <= 0; + EOP <= 0; + RRDY <= 0; + ROE <= 0; + TOE <= 0; + tx_holding_reg <= 0; + tx_holding_primed <= 0; + transmitting <= 0; + SCLK_reg <= 0; + MISO_reg <= 0; + end + else + begin + if (write_tx_holding) + begin + tx_holding_reg <= data_from_cpu; + tx_holding_primed <= 1; + end + if (data_wr_strobe & ~TRDY) + // You wrote when I wasn't ready. + TOE <= 1; + + // EOP must be updated by the last (2nd) cycle of access. + if ((p1_data_rd_strobe && (rx_holding_reg == endofpacketvalue_reg)) || (p1_data_wr_strobe && (data_from_cpu[7 : 0] == endofpacketvalue_reg))) + EOP <= 1; + if (write_shift_reg) + begin + shift_reg <= tx_holding_reg; + transmitting <= 1; + end + if (write_shift_reg & ~write_tx_holding) + // Clear tx_holding_primed + tx_holding_primed <= 0; + + if (data_rd_strobe) + // On data read, clear the RRDY bit. + RRDY <= 0; + + if (status_wr_strobe) + begin + // On status write, clear all status bits (ignore the data). + EOP <= 0; + + RRDY <= 0; + ROE <= 0; + TOE <= 0; + end + if (slowclock) + begin + if (state == 17) + begin + transmitting <= 0; + RRDY <= 1; + rx_holding_reg <= shift_reg; + SCLK_reg <= 0; + if (RRDY) + ROE <= 1; + end + else if (state != 0) + if (transmitting) + SCLK_reg <= ~SCLK_reg; + if (SCLK_reg ^ 0 ^ 0) + begin + if (1) + shift_reg <= {shift_reg[6 : 0], MISO_reg}; + end + else + MISO_reg <= ds_MISO; + end + end + end + + + assign ds_MISO = MISO; + +endmodule + diff --git a/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_sys_clk_timer.v b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_sys_clk_timer.v new file mode 100644 index 00000000..cbc5f3ed --- /dev/null +++ b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_sys_clk_timer.v @@ -0,0 +1,210 @@ +//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module system_sys_clk_timer ( + // inputs: + address, + chipselect, + clk, + reset_n, + write_n, + writedata, + + // outputs: + irq, + readdata + ) +; + + output irq; + output [ 15: 0] readdata; + input [ 2: 0] address; + input chipselect; + input clk; + input reset_n; + input write_n; + input [ 15: 0] writedata; + + wire clk_en; + wire control_continuous; + wire control_interrupt_enable; + reg [ 3: 0] control_register; + wire control_wr_strobe; + reg counter_is_running; + wire counter_is_zero; + wire [ 31: 0] counter_load_value; + reg [ 31: 0] counter_snapshot; + reg delayed_unxcounter_is_zeroxx0; + wire do_start_counter; + wire do_stop_counter; + reg force_reload; + reg [ 31: 0] internal_counter; + wire irq; + reg [ 15: 0] period_h_register; + wire period_h_wr_strobe; + reg [ 15: 0] period_l_register; + wire period_l_wr_strobe; + wire [ 15: 0] read_mux_out; + reg [ 15: 0] readdata; + wire snap_h_wr_strobe; + wire snap_l_wr_strobe; + wire [ 31: 0] snap_read_value; + wire snap_strobe; + wire start_strobe; + wire status_wr_strobe; + wire stop_strobe; + wire timeout_event; + reg timeout_occurred; + assign clk_en = 1; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + internal_counter <= 32'h1869F; + else if (counter_is_running || force_reload) + if (counter_is_zero || force_reload) + internal_counter <= counter_load_value; + else + internal_counter <= internal_counter - 1; + end + + + assign counter_is_zero = internal_counter == 0; + assign counter_load_value = {period_h_register, + period_l_register}; + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + force_reload <= 0; + else if (clk_en) + force_reload <= period_h_wr_strobe || period_l_wr_strobe; + end + + + assign do_start_counter = start_strobe; + assign do_stop_counter = (stop_strobe ) || + (force_reload ) || + (counter_is_zero && ~control_continuous ); + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + counter_is_running <= 1'b0; + else if (clk_en) + if (do_start_counter) + counter_is_running <= -1; + else if (do_stop_counter) + counter_is_running <= 0; + end + + + //delayed_unxcounter_is_zeroxx0, which is an e_register + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + delayed_unxcounter_is_zeroxx0 <= 0; + else if (clk_en) + delayed_unxcounter_is_zeroxx0 <= counter_is_zero; + end + + + assign timeout_event = (counter_is_zero) & ~(delayed_unxcounter_is_zeroxx0); + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + timeout_occurred <= 0; + else if (clk_en) + if (status_wr_strobe) + timeout_occurred <= 0; + else if (timeout_event) + timeout_occurred <= -1; + end + + + assign irq = timeout_occurred && control_interrupt_enable; + //s1, which is an e_avalon_slave + assign read_mux_out = ({16 {(address == 2)}} & period_l_register) | + ({16 {(address == 3)}} & period_h_register) | + ({16 {(address == 4)}} & snap_read_value[15 : 0]) | + ({16 {(address == 5)}} & snap_read_value[31 : 16]) | + ({16 {(address == 1)}} & control_register) | + ({16 {(address == 0)}} & {counter_is_running, + timeout_occurred}); + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + readdata <= 0; + else if (clk_en) + readdata <= read_mux_out; + end + + + assign period_l_wr_strobe = chipselect && ~write_n && (address == 2); + assign period_h_wr_strobe = chipselect && ~write_n && (address == 3); + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + period_l_register <= 34463; + else if (period_l_wr_strobe) + period_l_register <= writedata; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + period_h_register <= 1; + else if (period_h_wr_strobe) + period_h_register <= writedata; + end + + + assign snap_l_wr_strobe = chipselect && ~write_n && (address == 4); + assign snap_h_wr_strobe = chipselect && ~write_n && (address == 5); + assign snap_strobe = snap_l_wr_strobe || snap_h_wr_strobe; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + counter_snapshot <= 0; + else if (snap_strobe) + counter_snapshot <= internal_counter; + end + + + assign snap_read_value = counter_snapshot; + assign control_wr_strobe = chipselect && ~write_n && (address == 1); + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + control_register <= 0; + else if (control_wr_strobe) + control_register <= writedata[3 : 0]; + end + + + assign stop_strobe = writedata[3] && control_wr_strobe; + assign start_strobe = writedata[2] && control_wr_strobe; + assign control_continuous = control_register[1]; + assign control_interrupt_enable = control_register; + assign status_wr_strobe = chipselect && ~write_n && (address == 0); + +endmodule + diff --git a/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_sysid.v b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_sysid.v new file mode 100644 index 00000000..1d3183f6 --- /dev/null +++ b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_sysid.v @@ -0,0 +1,44 @@ +//Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module system_sysid ( + // inputs: + address, + clock, + reset_n, + + // outputs: + readdata + ) +; + + output [ 31: 0] readdata; + input address; + input clock; + input reset_n; + + wire [ 31: 0] readdata; + //control_slave, which is an e_avalon_slave + assign readdata = address ? 1394124174 : 0; + +endmodule + + + diff --git a/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_uart_0.v b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_uart_0.v new file mode 100644 index 00000000..4a230927 --- /dev/null +++ b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_uart_0.v @@ -0,0 +1,1149 @@ +//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your +//use of Altera Corporation's design tools, logic functions and other +//software and tools, and its AMPP partner logic functions, and any +//output files any of the foregoing (including device programming or +//simulation files), and any associated documentation or information are +//expressly subject to the terms and conditions of the Altera Program +//License Subscription Agreement or other applicable license agreement, +//including, without limitation, that your use is for the sole purpose +//of programming logic devices manufactured by Altera and sold by Altera +//or its authorized distributors. Please refer to the applicable +//agreement for further details. + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module system_uart_0_log_module ( + // inputs: + clk, + data, + strobe, + valid + ) +; + + input clk; + input [ 7: 0] data; + input strobe; + input valid; + + +//synthesis translate_off +//////////////// SIMULATION-ONLY CONTENTS + reg [31:0] text_handle; // for $fopen + initial text_handle = $fopen ("system_uart_0_log_module.txt"); + + always @(posedge clk) begin + if (valid && strobe) begin + // Send \n (linefeed) instead of \r (^M, Carriage Return)... + $fwrite (text_handle, "%s", ((data == 8'hd) ? 8'ha : data)); + // non-standard; poorly documented; required to get real data stream. + $fflush (text_handle); + end + end // clk + + +//////////////// END SIMULATION-ONLY CONTENTS + +//synthesis translate_on + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module system_uart_0_tx ( + // inputs: + baud_divisor, + begintransfer, + clk, + clk_en, + do_force_break, + reset_n, + status_wr_strobe, + tx_data, + tx_wr_strobe, + + // outputs: + tx_overrun, + tx_ready, + tx_shift_empty, + txd + ) +; + + output tx_overrun; + output tx_ready; + output tx_shift_empty; + output txd; + input [ 15: 0] baud_divisor; + input begintransfer; + input clk; + input clk_en; + input do_force_break; + input reset_n; + input status_wr_strobe; + input [ 7: 0] tx_data; + input tx_wr_strobe; + + reg baud_clk_en; + reg [ 15: 0] baud_rate_counter; + wire baud_rate_counter_is_zero; + reg do_load_shifter; + wire do_shift; + reg pre_txd; + wire shift_done; + wire [ 9: 0] tx_load_val; + reg tx_overrun; + reg tx_ready; + reg tx_shift_empty; + wire tx_shift_reg_out; + wire [ 9: 0] tx_shift_register_contents; + wire tx_wr_strobe_onset; + reg txd; + wire [ 9: 0] unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_in; + reg [ 9: 0] unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out; + assign tx_wr_strobe_onset = tx_wr_strobe && begintransfer; + assign tx_load_val = {{1 {1'b1}}, + tx_data, + 1'b0}; + + assign shift_done = ~(|tx_shift_register_contents); + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + do_load_shifter <= 0; + else if (clk_en) + do_load_shifter <= (~tx_ready) && shift_done; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + tx_ready <= 1'b1; + else if (clk_en) + if (tx_wr_strobe_onset) + tx_ready <= 0; + else if (do_load_shifter) + tx_ready <= -1; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + tx_overrun <= 0; + else if (clk_en) + if (status_wr_strobe) + tx_overrun <= 0; + else if (~tx_ready && tx_wr_strobe_onset) + tx_overrun <= -1; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + tx_shift_empty <= 1'b1; + else if (clk_en) + tx_shift_empty <= tx_ready && shift_done; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + baud_rate_counter <= 0; + else if (clk_en) + if (baud_rate_counter_is_zero || do_load_shifter) + baud_rate_counter <= baud_divisor; + else + baud_rate_counter <= baud_rate_counter - 1; + end + + + assign baud_rate_counter_is_zero = baud_rate_counter == 0; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + baud_clk_en <= 0; + else if (clk_en) + baud_clk_en <= baud_rate_counter_is_zero; + end + + + assign do_shift = baud_clk_en && + (~shift_done) && + (~do_load_shifter); + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + pre_txd <= 1; + else if (~shift_done) + pre_txd <= tx_shift_reg_out; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + txd <= 1; + else if (clk_en) + txd <= pre_txd & ~do_force_break; + end + + + //_reg, which is an e_register + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out <= 0; + else if (clk_en) + unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out <= unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_in; + end + + + assign unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_in = (do_load_shifter)? tx_load_val : + (do_shift)? {1'b0, + unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[9 : 1]} : + unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out; + + assign tx_shift_register_contents = unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out; + assign tx_shift_reg_out = unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[0]; + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module system_uart_0_rx_stimulus_source_character_source_rom_module ( + // inputs: + clk, + incr_addr, + reset_n, + + // outputs: + new_rom, + q, + safe + ) +; + + parameter POLL_RATE = 100; + + + output new_rom; + output [ 7: 0] q; + output safe; + input clk; + input incr_addr; + input reset_n; + + reg [ 10: 0] address; + reg d1_pre; + reg d2_pre; + reg d3_pre; + reg d4_pre; + reg d5_pre; + reg d6_pre; + reg d7_pre; + reg d8_pre; + reg d9_pre; + reg [ 7: 0] mem_array [1023: 0]; + reg [ 31: 0] mutex [ 1: 0]; + reg new_rom; + reg pre; + wire [ 7: 0] q; + wire safe; + +//synthesis translate_off +//////////////// SIMULATION-ONLY CONTENTS + assign q = mem_array[address]; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + begin + d1_pre <= 0; + d2_pre <= 0; + d3_pre <= 0; + d4_pre <= 0; + d5_pre <= 0; + d6_pre <= 0; + d7_pre <= 0; + d8_pre <= 0; + d9_pre <= 0; + new_rom <= 0; + end + else + begin + d1_pre <= pre; + d2_pre <= d1_pre; + d3_pre <= d2_pre; + d4_pre <= d3_pre; + d5_pre <= d4_pre; + d6_pre <= d5_pre; + d7_pre <= d6_pre; + d8_pre <= d7_pre; + d9_pre <= d8_pre; + new_rom <= d9_pre; + end + end + + + reg safe_delay; + reg [31:0] poll_count; + reg [31:0] mutex_handle; + wire interactive = 1'b0 ; // ' + assign safe = (address < mutex[1]); + + initial poll_count = POLL_RATE; + + always @(posedge clk or negedge reset_n) begin + if (reset_n !== 1) begin + safe_delay <= 0; + end else begin + safe_delay <= safe; + end + end // safe_delay + + always @(posedge clk or negedge reset_n) begin + if (reset_n !== 1) begin // dont worry about null _stream.dat file + address <= 0; + mem_array[0] <= 0; + mutex[0] <= 0; + mutex[1] <= 0; + pre <= 0; + end else begin // deal with the non-reset case + pre <= 0; + if (incr_addr && safe) address <= address + 1; + if (mutex[0] && !safe && safe_delay) begin + // and blast the mutex after falling edge of safe if interactive + if (interactive) begin + mutex_handle = $fopen ("system_uart_0_input_data_mutex.dat"); + $fdisplay (mutex_handle, "0"); + $fclose (mutex_handle); + // $display ($stime, "\t%m:\n\t\tMutex cleared!"); + end else begin + // sleep until next reset, do not bash mutex. + wait (!reset_n); + end + end // OK to bash mutex. + if (poll_count < POLL_RATE) begin // wait + poll_count = poll_count + 1; + end else begin // do the interesting stuff. + poll_count = 0; + if (mutex_handle) begin + $readmemh ("system_uart_0_input_data_mutex.dat", mutex); + end + if (mutex[0] && !safe) begin + // read stream into mem_array after current characters are gone! + // save mutex[0] value to compare to address (generates 'safe') + mutex[1] <= mutex[0]; + // $display ($stime, "\t%m:\n\t\tMutex hit: Trying to read %d bytes...", mutex[0]); + $readmemh("system_uart_0_input_data_stream.dat", mem_array); + // bash address and send pulse outside to send the char: + address <= 0; + pre <= -1; + end // else mutex miss... + end // poll_count + end // reset + end // posedge clk + + +//////////////// END SIMULATION-ONLY CONTENTS + +//synthesis translate_on + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module system_uart_0_rx_stimulus_source ( + // inputs: + baud_divisor, + clk, + clk_en, + reset_n, + rx_char_ready, + rxd, + + // outputs: + source_rxd + ) +; + + output source_rxd; + input [ 15: 0] baud_divisor; + input clk; + input clk_en; + input reset_n; + input rx_char_ready; + input rxd; + + reg [ 7: 0] d1_stim_data; + reg delayed_unxrx_char_readyxx0; + wire do_send_stim_data; + wire new_rom_pulse; + wire pickup_pulse; + wire safe; + wire source_rxd; + wire [ 7: 0] stim_data; + wire unused_empty; + wire unused_overrun; + wire unused_ready; + +//synthesis translate_off +//////////////// SIMULATION-ONLY CONTENTS + //stimulus_transmitter, which is an e_instance + system_uart_0_tx stimulus_transmitter + ( + .baud_divisor (baud_divisor), + .begintransfer (do_send_stim_data), + .clk (clk), + .clk_en (clk_en), + .do_force_break (1'b0), + .reset_n (reset_n), + .status_wr_strobe (1'b0), + .tx_data (d1_stim_data), + .tx_overrun (unused_overrun), + .tx_ready (unused_ready), + .tx_shift_empty (unused_empty), + .tx_wr_strobe (1'b1), + .txd (source_rxd) + ); + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + d1_stim_data <= 0; + else if (do_send_stim_data) + d1_stim_data <= stim_data; + end + + + //system_uart_0_rx_stimulus_source_character_source_rom, which is an e_drom + system_uart_0_rx_stimulus_source_character_source_rom_module system_uart_0_rx_stimulus_source_character_source_rom + ( + .clk (clk), + .incr_addr (do_send_stim_data), + .new_rom (new_rom_pulse), + .q (stim_data), + .reset_n (reset_n), + .safe (safe) + ); + + //delayed_unxrx_char_readyxx0, which is an e_register + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + delayed_unxrx_char_readyxx0 <= 0; + else if (clk_en) + delayed_unxrx_char_readyxx0 <= rx_char_ready; + end + + + assign pickup_pulse = ~(rx_char_ready) & (delayed_unxrx_char_readyxx0); + assign do_send_stim_data = (pickup_pulse || new_rom_pulse) && safe; + +//////////////// END SIMULATION-ONLY CONTENTS + +//synthesis translate_on +//synthesis read_comments_as_HDL on +// assign source_rxd = rxd; +//synthesis read_comments_as_HDL off + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module system_uart_0_rx ( + // inputs: + baud_divisor, + begintransfer, + clk, + clk_en, + reset_n, + rx_rd_strobe, + rxd, + status_wr_strobe, + + // outputs: + break_detect, + framing_error, + parity_error, + rx_char_ready, + rx_data, + rx_overrun + ) +; + + output break_detect; + output framing_error; + output parity_error; + output rx_char_ready; + output [ 7: 0] rx_data; + output rx_overrun; + input [ 15: 0] baud_divisor; + input begintransfer; + input clk; + input clk_en; + input reset_n; + input rx_rd_strobe; + input rxd; + input status_wr_strobe; + + reg baud_clk_en; + wire [ 15: 0] baud_load_value; + reg [ 15: 0] baud_rate_counter; + wire baud_rate_counter_is_zero; + reg break_detect; + reg delayed_unxrx_in_processxx3; + reg delayed_unxsync_rxdxx1; + reg delayed_unxsync_rxdxx2; + reg do_start_rx; + reg framing_error; + wire got_new_char; + wire [ 14: 0] half_bit_cell_divisor; + wire is_break; + wire is_framing_error; + wire parity_error; + wire [ 7: 0] raw_data_in; + reg rx_char_ready; + reg [ 7: 0] rx_data; + wire rx_in_process; + reg rx_overrun; + wire rx_rd_strobe_onset; + wire rxd_edge; + wire rxd_falling; + wire [ 9: 0] rxd_shift_reg; + wire sample_enable; + wire shift_reg_start_bit_n; + wire source_rxd; + wire stop_bit; + wire sync_rxd; + wire unused_start_bit; + wire [ 9: 0] unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_in; + reg [ 9: 0] unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out; + system_uart_0_rx_stimulus_source the_system_uart_0_rx_stimulus_source + ( + .baud_divisor (baud_divisor), + .clk (clk), + .clk_en (clk_en), + .reset_n (reset_n), + .rx_char_ready (rx_char_ready), + .rxd (rxd), + .source_rxd (source_rxd) + ); + + altera_std_synchronizer the_altera_std_synchronizer + ( + .clk (clk), + .din (source_rxd), + .dout (sync_rxd), + .reset_n (reset_n) + ); + + defparam the_altera_std_synchronizer.depth = 2; + + //delayed_unxsync_rxdxx1, which is an e_register + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + delayed_unxsync_rxdxx1 <= 0; + else if (clk_en) + delayed_unxsync_rxdxx1 <= sync_rxd; + end + + + assign rxd_falling = ~(sync_rxd) & (delayed_unxsync_rxdxx1); + //delayed_unxsync_rxdxx2, which is an e_register + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + delayed_unxsync_rxdxx2 <= 0; + else if (clk_en) + delayed_unxsync_rxdxx2 <= sync_rxd; + end + + + assign rxd_edge = (sync_rxd) ^ (delayed_unxsync_rxdxx2); + assign rx_rd_strobe_onset = rx_rd_strobe && begintransfer; + assign half_bit_cell_divisor = baud_divisor[15 : 1]; + assign baud_load_value = (rxd_edge)? half_bit_cell_divisor : + baud_divisor; + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + baud_rate_counter <= 0; + else if (clk_en) + if (baud_rate_counter_is_zero || rxd_edge) + baud_rate_counter <= baud_load_value; + else + baud_rate_counter <= baud_rate_counter - 1; + end + + + assign baud_rate_counter_is_zero = baud_rate_counter == 0; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + baud_clk_en <= 0; + else if (clk_en) + if (rxd_edge) + baud_clk_en <= 0; + else + baud_clk_en <= baud_rate_counter_is_zero; + end + + + assign sample_enable = baud_clk_en && rx_in_process; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + do_start_rx <= 0; + else if (clk_en) + if (~rx_in_process && rxd_falling) + do_start_rx <= 1; + else + do_start_rx <= 0; + end + + + assign rx_in_process = shift_reg_start_bit_n; + assign {stop_bit, +raw_data_in, +unused_start_bit} = rxd_shift_reg; + assign is_break = ~(|rxd_shift_reg); + assign is_framing_error = ~stop_bit && ~is_break; + //delayed_unxrx_in_processxx3, which is an e_register + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + delayed_unxrx_in_processxx3 <= 0; + else if (clk_en) + delayed_unxrx_in_processxx3 <= rx_in_process; + end + + + assign got_new_char = ~(rx_in_process) & (delayed_unxrx_in_processxx3); + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + rx_data <= 0; + else if (got_new_char) + rx_data <= raw_data_in; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + framing_error <= 0; + else if (clk_en) + if (status_wr_strobe) + framing_error <= 0; + else if (got_new_char && is_framing_error) + framing_error <= -1; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + break_detect <= 0; + else if (clk_en) + if (status_wr_strobe) + break_detect <= 0; + else if (got_new_char && is_break) + break_detect <= -1; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + rx_overrun <= 0; + else if (clk_en) + if (status_wr_strobe) + rx_overrun <= 0; + else if (got_new_char && rx_char_ready) + rx_overrun <= -1; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + rx_char_ready <= 0; + else if (clk_en) + if (rx_rd_strobe_onset) + rx_char_ready <= 0; + else if (got_new_char) + rx_char_ready <= -1; + end + + + assign parity_error = 0; + //_reg, which is an e_register + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out <= 0; + else if (clk_en) + unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out <= unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_in; + end + + + assign unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_in = (do_start_rx)? {10{1'b1}} : + (sample_enable)? {sync_rxd, + unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[9 : 1]} : + unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out; + + assign rxd_shift_reg = unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out; + assign shift_reg_start_bit_n = unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[0]; + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module system_uart_0_regs ( + // inputs: + address, + break_detect, + chipselect, + clk, + clk_en, + framing_error, + parity_error, + read_n, + reset_n, + rx_char_ready, + rx_data, + rx_overrun, + tx_overrun, + tx_ready, + tx_shift_empty, + write_n, + writedata, + + // outputs: + baud_divisor, + dataavailable, + do_force_break, + irq, + readdata, + readyfordata, + rx_rd_strobe, + status_wr_strobe, + tx_data, + tx_wr_strobe + ) +; + + output [ 15: 0] baud_divisor; + output dataavailable; + output do_force_break; + output irq; + output [ 15: 0] readdata; + output readyfordata; + output rx_rd_strobe; + output status_wr_strobe; + output [ 7: 0] tx_data; + output tx_wr_strobe; + input [ 2: 0] address; + input break_detect; + input chipselect; + input clk; + input clk_en; + input framing_error; + input parity_error; + input read_n; + input reset_n; + input rx_char_ready; + input [ 7: 0] rx_data; + input rx_overrun; + input tx_overrun; + input tx_ready; + input tx_shift_empty; + input write_n; + input [ 15: 0] writedata; + + wire any_error; + reg [ 15: 0] baud_divisor; + reg [ 9: 0] control_reg; + wire control_wr_strobe; + wire cts_status_bit; + reg d1_rx_char_ready; + reg d1_tx_ready; + wire dataavailable; + wire dcts_status_bit; + reg delayed_unxtx_readyxx4; + wire [ 15: 0] divisor_constant; + wire divisor_wr_strobe; + wire do_force_break; + wire do_write_char; + wire eop_status_bit; + wire ie_any_error; + wire ie_break_detect; + wire ie_framing_error; + wire ie_parity_error; + wire ie_rx_char_ready; + wire ie_rx_overrun; + wire ie_tx_overrun; + wire ie_tx_ready; + wire ie_tx_shift_empty; + reg irq; + wire qualified_irq; + reg [ 15: 0] readdata; + wire readyfordata; + wire rx_rd_strobe; + wire [ 15: 0] selected_read_data; + wire [ 12: 0] status_reg; + wire status_wr_strobe; + reg [ 7: 0] tx_data; + wire tx_wr_strobe; + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + readdata <= 0; + else if (clk_en) + readdata <= selected_read_data; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + irq <= 0; + else if (clk_en) + irq <= qualified_irq; + end + + + assign rx_rd_strobe = chipselect && ~read_n && (address == 3'd0); + assign tx_wr_strobe = chipselect && ~write_n && (address == 3'd1); + assign status_wr_strobe = chipselect && ~write_n && (address == 3'd2); + assign control_wr_strobe = chipselect && ~write_n && (address == 3'd3); + assign divisor_wr_strobe = chipselect && ~write_n && (address == 3'd4); + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + tx_data <= 0; + else if (tx_wr_strobe) + tx_data <= writedata[7 : 0]; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + control_reg <= 0; + else if (control_wr_strobe) + control_reg <= writedata[9 : 0]; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + baud_divisor <= divisor_constant; + else if (divisor_wr_strobe) + baud_divisor <= writedata[15 : 0]; + end + + + assign cts_status_bit = 0; + assign dcts_status_bit = 0; + assign {do_force_break, +ie_any_error, +ie_rx_char_ready, +ie_tx_ready, +ie_tx_shift_empty, +ie_tx_overrun, +ie_rx_overrun, +ie_break_detect, +ie_framing_error, +ie_parity_error} = control_reg; + assign any_error = tx_overrun || + rx_overrun || + parity_error || + framing_error || + break_detect; + + assign status_reg = {eop_status_bit, + cts_status_bit, + dcts_status_bit, + 1'b0, + any_error, + rx_char_ready, + tx_ready, + tx_shift_empty, + tx_overrun, + rx_overrun, + break_detect, + framing_error, + parity_error}; + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + d1_rx_char_ready <= 0; + else if (clk_en) + d1_rx_char_ready <= rx_char_ready; + end + + + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + d1_tx_ready <= 0; + else if (clk_en) + d1_tx_ready <= tx_ready; + end + + + assign dataavailable = d1_rx_char_ready; + assign readyfordata = d1_tx_ready; + assign eop_status_bit = 1'b0; + assign selected_read_data = ({16 {(address == 3'd0)}} & rx_data) | + ({16 {(address == 3'd1)}} & tx_data) | + ({16 {(address == 3'd2)}} & status_reg) | + ({16 {(address == 3'd3)}} & control_reg) | + ({16 {(address == 3'd4)}} & baud_divisor); + + assign qualified_irq = (ie_any_error && any_error ) || + (ie_tx_shift_empty && tx_shift_empty ) || + (ie_tx_overrun && tx_overrun ) || + (ie_rx_overrun && rx_overrun ) || + (ie_break_detect && break_detect ) || + (ie_framing_error && framing_error ) || + (ie_parity_error && parity_error ) || + (ie_rx_char_ready && rx_char_ready ) || + (ie_tx_ready && tx_ready ); + + +//synthesis translate_off +//////////////// SIMULATION-ONLY CONTENTS + //delayed_unxtx_readyxx4, which is an e_register + always @(posedge clk or negedge reset_n) + begin + if (reset_n == 0) + delayed_unxtx_readyxx4 <= 0; + else if (clk_en) + delayed_unxtx_readyxx4 <= tx_ready; + end + + + assign do_write_char = (tx_ready) & ~(delayed_unxtx_readyxx4); + always @(posedge clk) + begin + if (do_write_char) + $write("%c", tx_data); + end + + + assign divisor_constant = 4; + +//////////////// END SIMULATION-ONLY CONTENTS + +//synthesis translate_on +//synthesis read_comments_as_HDL on +// assign divisor_constant = 868; +//synthesis read_comments_as_HDL off + +endmodule + + +// synthesis translate_off +`timescale 1ns / 1ps +// synthesis translate_on + +// turn off superfluous verilog processor warnings +// altera message_level Level1 +// altera message_off 10034 10035 10036 10037 10230 10240 10030 + +module system_uart_0 ( + // inputs: + address, + begintransfer, + chipselect, + clk, + read_n, + reset_n, + rxd, + write_n, + writedata, + + // outputs: + dataavailable, + irq, + readdata, + readyfordata, + txd + ) + /* synthesis altera_attribute = "-name SYNCHRONIZER_IDENTIFICATION OFF" */ ; + + output dataavailable; + output irq; + output [ 15: 0] readdata; + output readyfordata; + output txd; + input [ 2: 0] address; + input begintransfer; + input chipselect; + input clk; + input read_n; + input reset_n; + input rxd; + input write_n; + input [ 15: 0] writedata; + + wire [ 15: 0] baud_divisor; + wire break_detect; + wire clk_en; + wire dataavailable; + wire do_force_break; + wire framing_error; + wire irq; + wire parity_error; + wire [ 15: 0] readdata; + wire readyfordata; + wire rx_char_ready; + wire [ 7: 0] rx_data; + wire rx_overrun; + wire rx_rd_strobe; + wire status_wr_strobe; + wire [ 7: 0] tx_data; + wire tx_overrun; + wire tx_ready; + wire tx_shift_empty; + wire tx_wr_strobe; + wire txd; + assign clk_en = 1; + system_uart_0_tx the_system_uart_0_tx + ( + .baud_divisor (baud_divisor), + .begintransfer (begintransfer), + .clk (clk), + .clk_en (clk_en), + .do_force_break (do_force_break), + .reset_n (reset_n), + .status_wr_strobe (status_wr_strobe), + .tx_data (tx_data), + .tx_overrun (tx_overrun), + .tx_ready (tx_ready), + .tx_shift_empty (tx_shift_empty), + .tx_wr_strobe (tx_wr_strobe), + .txd (txd) + ); + + system_uart_0_rx the_system_uart_0_rx + ( + .baud_divisor (baud_divisor), + .begintransfer (begintransfer), + .break_detect (break_detect), + .clk (clk), + .clk_en (clk_en), + .framing_error (framing_error), + .parity_error (parity_error), + .reset_n (reset_n), + .rx_char_ready (rx_char_ready), + .rx_data (rx_data), + .rx_overrun (rx_overrun), + .rx_rd_strobe (rx_rd_strobe), + .rxd (rxd), + .status_wr_strobe (status_wr_strobe) + ); + + system_uart_0_regs the_system_uart_0_regs + ( + .address (address), + .baud_divisor (baud_divisor), + .break_detect (break_detect), + .chipselect (chipselect), + .clk (clk), + .clk_en (clk_en), + .dataavailable (dataavailable), + .do_force_break (do_force_break), + .framing_error (framing_error), + .irq (irq), + .parity_error (parity_error), + .read_n (read_n), + .readdata (readdata), + .readyfordata (readyfordata), + .reset_n (reset_n), + .rx_char_ready (rx_char_ready), + .rx_data (rx_data), + .rx_overrun (rx_overrun), + .rx_rd_strobe (rx_rd_strobe), + .status_wr_strobe (status_wr_strobe), + .tx_data (tx_data), + .tx_overrun (tx_overrun), + .tx_ready (tx_ready), + .tx_shift_empty (tx_shift_empty), + .tx_wr_strobe (tx_wr_strobe), + .write_n (write_n), + .writedata (writedata) + ); + + //s1, which is an e_avalon_slave + +//synthesis translate_off +//////////////// SIMULATION-ONLY CONTENTS + //system_uart_0_log, which is an e_log + system_uart_0_log_module system_uart_0_log + ( + .clk (clk), + .data (tx_data), + .strobe (tx_wr_strobe), + .valid (~tx_ready) + ); + + +//////////////// END SIMULATION-ONLY CONTENTS + +//synthesis translate_on + +endmodule + diff --git a/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_uart_0_input_data_mutex.dat b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_uart_0_input_data_mutex.dat new file mode 100644 index 00000000..573541ac --- /dev/null +++ b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_uart_0_input_data_mutex.dat @@ -0,0 +1 @@ +0 diff --git a/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_uart_0_input_data_stream.dat b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_uart_0_input_data_stream.dat new file mode 100644 index 00000000..e10d133f --- /dev/null +++ b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_uart_0_input_data_stream.dat @@ -0,0 +1,2 @@ +@0 +0 diff --git a/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_uart_0_log_module.txt b/MCTEST/DE0-nano-HD/system/synthesis/submodules/system_uart_0_log_module.txt new file mode 100644 index 00000000..e69de29b diff --git a/MCTEST/DE0-nano-HD/system/synthesis/system.qip b/MCTEST/DE0-nano-HD/system/synthesis/system.qip new file mode 100644 index 00000000..57250bda --- /dev/null +++ b/MCTEST/DE0-nano-HD/system/synthesis/system.qip @@ -0,0 +1,170 @@ +set_global_assignment -entity "system" -library "system" -name IP_TOOL_NAME "qsys" +set_global_assignment -entity "system" -library "system" -name IP_TOOL_VERSION "12.1sp1" +set_global_assignment -entity "system" -library "system" -name IP_TOOL_ENV "qsys" +set_global_assignment -library "system" -name SOPCINFO_FILE [file join $::quartus(qip_path) "../../system.sopcinfo"] +set_instance_assignment -entity "system" -library "system" -name SLD_INFO "QSYS_NAME system HAS_SOPCINFO 1 GENERATION_ID 1394124174" +set_global_assignment -library "system" -name MISC_FILE [file join $::quartus(qip_path) "../../system.cmp"] +set_global_assignment -name SYNTHESIS_ONLY_QIP ON +set_global_assignment -library "system" -name MISC_FILE [file join $::quartus(qip_path) "../../system.qsys"] + +set_global_assignment -library "system" -name VERILOG_FILE [file join $::quartus(qip_path) "system.v"] +set_global_assignment -library "system" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/system_irq_mapper.sv"] +set_global_assignment -library "system" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_merlin_width_adapter.sv"] +set_global_assignment -library "system" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_merlin_burst_uncompressor.sv"] +set_global_assignment -library "system" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_merlin_address_alignment.sv"] +set_global_assignment -library "system" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_merlin_arbitrator.sv"] +set_global_assignment -library "system" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/system_rsp_xbar_mux_001.sv"] +set_global_assignment -library "system" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/system_rsp_xbar_mux.sv"] +set_global_assignment -library "system" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/system_rsp_xbar_demux_002.sv"] +set_global_assignment -library "system" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/system_rsp_xbar_demux.sv"] +set_global_assignment -library "system" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/system_cmd_xbar_mux.sv"] +set_global_assignment -library "system" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/system_cmd_xbar_demux_001.sv"] +set_global_assignment -library "system" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/system_cmd_xbar_demux.sv"] +set_global_assignment -library "system" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_reset_controller.v"] +set_global_assignment -library "system" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_reset_synchronizer.v"] +set_global_assignment -library "system" -name SDC_FILE [file join $::quartus(qip_path) "submodules/altera_reset_controller.sdc"] +set_global_assignment -library "system" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_merlin_burst_adapter.sv"] +set_global_assignment -library "system" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_merlin_traffic_limiter.sv"] +set_global_assignment -library "system" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_avalon_st_pipeline_base.v"] +set_global_assignment -library "system" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/system_id_router_002.sv"] +set_global_assignment -library "system" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/system_id_router_001.sv"] +set_global_assignment -library "system" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/system_id_router.sv"] +set_global_assignment -library "system" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/system_addr_router_001.sv"] +set_global_assignment -library "system" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/system_addr_router.sv"] +set_global_assignment -library "system" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_avalon_sc_fifo.v"] +set_global_assignment -library "system" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_merlin_slave_agent.sv"] +set_global_assignment -library "system" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_merlin_master_agent.sv"] +set_global_assignment -library "system" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_merlin_slave_translator.sv"] +set_global_assignment -library "system" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_merlin_master_translator.sv"] +set_global_assignment -library "system" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_up_rs232_counters.v"] +set_global_assignment -library "system" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_up_rs232_in_deserializer.v"] +set_global_assignment -library "system" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_up_rs232_out_serializer.v"] +set_global_assignment -library "system" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_up_sync_fifo.v"] +set_global_assignment -library "system" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/system_rs232_motor.v"] +set_global_assignment -library "system" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/system_pio_motor_rst.v"] +set_global_assignment -library "system" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/system_jtag_uart_0.v"] +set_global_assignment -library "system" -name SOURCE_FILE [file join $::quartus(qip_path) "submodules/system_jtag_uart_0_input_mutex.dat"] +set_global_assignment -library "system" -name SOURCE_FILE [file join $::quartus(qip_path) "submodules/system_jtag_uart_0_input_stream.dat"] +set_global_assignment -library "system" -name SOURCE_FILE [file join $::quartus(qip_path) "submodules/system_jtag_uart_0_output_stream.dat"] +set_global_assignment -library "system" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/system_pio_sw.v"] +set_global_assignment -library "system" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/system_pio_key.v"] +set_global_assignment -library "system" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/system_pio_led.v"] +set_global_assignment -library "system" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/system_uart_0.v"] +set_global_assignment -library "system" -name SOURCE_FILE [file join $::quartus(qip_path) "submodules/system_uart_0_input_data_mutex.dat"] +set_global_assignment -library "system" -name SOURCE_FILE [file join $::quartus(qip_path) "submodules/system_uart_0_input_data_stream.dat"] +set_global_assignment -library "system" -name SOURCE_FILE [file join $::quartus(qip_path) "submodules/system_uart_0_log_module.txt"] +set_global_assignment -library "system" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/system_sys_clk_timer.v"] +set_global_assignment -library "system" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/system_sdram.v"] +set_global_assignment -library "system" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/system_sysid.v"] +set_global_assignment -library "system" -name SOURCE_FILE [file join $::quartus(qip_path) "submodules/system_cpu.ocp"] +set_global_assignment -library "system" -name SDC_FILE [file join $::quartus(qip_path) "submodules/system_cpu.sdc"] +set_global_assignment -library "system" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/system_cpu.v"] +set_global_assignment -library "system" -name SOURCE_FILE [file join $::quartus(qip_path) "submodules/system_cpu_bht_ram.mif"] +set_global_assignment -library "system" -name SOURCE_FILE [file join $::quartus(qip_path) "submodules/system_cpu_dc_tag_ram.mif"] +set_global_assignment -library "system" -name SOURCE_FILE [file join $::quartus(qip_path) "submodules/system_cpu_ic_tag_ram.mif"] +set_global_assignment -library "system" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/system_cpu_jtag_debug_module_sysclk.v"] +set_global_assignment -library "system" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/system_cpu_jtag_debug_module_tck.v"] +set_global_assignment -library "system" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/system_cpu_jtag_debug_module_wrapper.v"] +set_global_assignment -library "system" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/system_cpu_mult_cell.v"] +set_global_assignment -library "system" -name SOURCE_FILE [file join $::quartus(qip_path) "submodules/system_cpu_ociram_default_contents.mif"] +set_global_assignment -library "system" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/system_cpu_oci_test_bench.v"] +set_global_assignment -library "system" -name SOURCE_FILE [file join $::quartus(qip_path) "submodules/system_cpu_rf_ram_a.mif"] +set_global_assignment -library "system" -name SOURCE_FILE [file join $::quartus(qip_path) "submodules/system_cpu_rf_ram_b.mif"] +set_global_assignment -library "system" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/system_cpu_test_bench.v"] + +set_global_assignment -entity "system_irq_mapper" -library "system" -name IP_TOOL_NAME "altera_irq_mapper" +set_global_assignment -entity "system_irq_mapper" -library "system" -name IP_TOOL_VERSION "12.1" +set_global_assignment -entity "system_irq_mapper" -library "system" -name IP_TOOL_ENV "qsys" +set_global_assignment -entity "altera_merlin_width_adapter" -library "system" -name IP_TOOL_NAME "altera_merlin_width_adapter" +set_global_assignment -entity "altera_merlin_width_adapter" -library "system" -name IP_TOOL_VERSION "12.1" +set_global_assignment -entity "altera_merlin_width_adapter" -library "system" -name IP_TOOL_ENV "qsys" +set_global_assignment -entity "system_rsp_xbar_mux_001" -library "system" -name IP_TOOL_NAME "altera_merlin_multiplexer" +set_global_assignment -entity "system_rsp_xbar_mux_001" -library "system" -name IP_TOOL_VERSION "12.1" +set_global_assignment -entity "system_rsp_xbar_mux_001" -library "system" -name IP_TOOL_ENV "qsys" +set_global_assignment -entity "system_rsp_xbar_mux" -library "system" -name IP_TOOL_NAME "altera_merlin_multiplexer" +set_global_assignment -entity "system_rsp_xbar_mux" -library "system" -name IP_TOOL_VERSION "12.1" +set_global_assignment -entity "system_rsp_xbar_mux" -library "system" -name IP_TOOL_ENV "qsys" +set_global_assignment -entity "system_rsp_xbar_demux_002" -library "system" -name IP_TOOL_NAME "altera_merlin_demultiplexer" +set_global_assignment -entity "system_rsp_xbar_demux_002" -library "system" -name IP_TOOL_VERSION "12.1" +set_global_assignment -entity "system_rsp_xbar_demux_002" -library "system" -name IP_TOOL_ENV "qsys" +set_global_assignment -entity "system_rsp_xbar_demux" -library "system" -name IP_TOOL_NAME "altera_merlin_demultiplexer" +set_global_assignment -entity "system_rsp_xbar_demux" -library "system" -name IP_TOOL_VERSION "12.1" +set_global_assignment -entity "system_rsp_xbar_demux" -library "system" -name IP_TOOL_ENV "qsys" +set_global_assignment -entity "system_cmd_xbar_mux" -library "system" -name IP_TOOL_NAME "altera_merlin_multiplexer" +set_global_assignment -entity "system_cmd_xbar_mux" -library "system" -name IP_TOOL_VERSION "12.1" +set_global_assignment -entity "system_cmd_xbar_mux" -library "system" -name IP_TOOL_ENV "qsys" +set_global_assignment -entity "system_cmd_xbar_demux_001" -library "system" -name IP_TOOL_NAME "altera_merlin_demultiplexer" +set_global_assignment -entity "system_cmd_xbar_demux_001" -library "system" -name IP_TOOL_VERSION "12.1" +set_global_assignment -entity "system_cmd_xbar_demux_001" -library "system" -name IP_TOOL_ENV "qsys" +set_global_assignment -entity "system_cmd_xbar_demux" -library "system" -name IP_TOOL_NAME "altera_merlin_demultiplexer" +set_global_assignment -entity "system_cmd_xbar_demux" -library "system" -name IP_TOOL_VERSION "12.1" +set_global_assignment -entity "system_cmd_xbar_demux" -library "system" -name IP_TOOL_ENV "qsys" +set_global_assignment -entity "altera_reset_controller" -library "system" -name IP_TOOL_NAME "altera_reset_controller" +set_global_assignment -entity "altera_reset_controller" -library "system" -name IP_TOOL_VERSION "12.1" +set_global_assignment -entity "altera_reset_controller" -library "system" -name IP_TOOL_ENV "qsys" +set_global_assignment -entity "altera_merlin_burst_adapter" -library "system" -name IP_TOOL_NAME "altera_merlin_burst_adapter" +set_global_assignment -entity "altera_merlin_burst_adapter" -library "system" -name IP_TOOL_VERSION "12.1" +set_global_assignment -entity "altera_merlin_burst_adapter" -library "system" -name IP_TOOL_ENV "qsys" +set_global_assignment -entity "altera_merlin_traffic_limiter" -library "system" -name IP_TOOL_NAME "altera_merlin_traffic_limiter" +set_global_assignment -entity "altera_merlin_traffic_limiter" -library "system" -name IP_TOOL_VERSION "12.1" +set_global_assignment -entity "altera_merlin_traffic_limiter" -library "system" -name IP_TOOL_ENV "qsys" +set_global_assignment -entity "system_id_router_002" -library "system" -name IP_TOOL_NAME "altera_merlin_router" +set_global_assignment -entity "system_id_router_002" -library "system" -name IP_TOOL_VERSION "12.1" +set_global_assignment -entity "system_id_router_002" -library "system" -name IP_TOOL_ENV "qsys" +set_global_assignment -entity "system_id_router_001" -library "system" -name IP_TOOL_NAME "altera_merlin_router" +set_global_assignment -entity "system_id_router_001" -library "system" -name IP_TOOL_VERSION "12.1" +set_global_assignment -entity "system_id_router_001" -library "system" -name IP_TOOL_ENV "qsys" +set_global_assignment -entity "system_id_router" -library "system" -name IP_TOOL_NAME "altera_merlin_router" +set_global_assignment -entity "system_id_router" -library "system" -name IP_TOOL_VERSION "12.1" +set_global_assignment -entity "system_id_router" -library "system" -name IP_TOOL_ENV "qsys" +set_global_assignment -entity "system_addr_router_001" -library "system" -name IP_TOOL_NAME "altera_merlin_router" +set_global_assignment -entity "system_addr_router_001" -library "system" -name IP_TOOL_VERSION "12.1" +set_global_assignment -entity "system_addr_router_001" -library "system" -name IP_TOOL_ENV "qsys" +set_global_assignment -entity "system_addr_router" -library "system" -name IP_TOOL_NAME "altera_merlin_router" +set_global_assignment -entity "system_addr_router" -library "system" -name IP_TOOL_VERSION "12.1" +set_global_assignment -entity "system_addr_router" -library "system" -name IP_TOOL_ENV "qsys" +set_global_assignment -entity "altera_avalon_sc_fifo" -library "system" -name IP_TOOL_NAME "altera_avalon_sc_fifo" +set_global_assignment -entity "altera_avalon_sc_fifo" -library "system" -name IP_TOOL_VERSION "12.1" +set_global_assignment -entity "altera_avalon_sc_fifo" -library "system" -name IP_TOOL_ENV "qsys" +set_global_assignment -entity "altera_merlin_slave_agent" -library "system" -name IP_TOOL_NAME "altera_merlin_slave_agent" +set_global_assignment -entity "altera_merlin_slave_agent" -library "system" -name IP_TOOL_VERSION "12.1" +set_global_assignment -entity "altera_merlin_slave_agent" -library "system" -name IP_TOOL_ENV "qsys" +set_global_assignment -entity "altera_merlin_master_agent" -library "system" -name IP_TOOL_NAME "altera_merlin_master_agent" +set_global_assignment -entity "altera_merlin_master_agent" -library "system" -name IP_TOOL_VERSION "12.1" +set_global_assignment -entity "altera_merlin_master_agent" -library "system" -name IP_TOOL_ENV "qsys" +set_global_assignment -entity "altera_merlin_slave_translator" -library "system" -name IP_TOOL_NAME "altera_merlin_slave_translator" +set_global_assignment -entity "altera_merlin_slave_translator" -library "system" -name IP_TOOL_VERSION "12.1" +set_global_assignment -entity "altera_merlin_slave_translator" -library "system" -name IP_TOOL_ENV "qsys" +set_global_assignment -entity "altera_merlin_master_translator" -library "system" -name IP_TOOL_NAME "altera_merlin_master_translator" +set_global_assignment -entity "altera_merlin_master_translator" -library "system" -name IP_TOOL_VERSION "12.1" +set_global_assignment -entity "altera_merlin_master_translator" -library "system" -name IP_TOOL_ENV "qsys" +set_global_assignment -entity "system_pio_motor_rst" -library "system" -name IP_TOOL_NAME "altera_avalon_pio" +set_global_assignment -entity "system_pio_motor_rst" -library "system" -name IP_TOOL_VERSION "12.1" +set_global_assignment -entity "system_pio_motor_rst" -library "system" -name IP_TOOL_ENV "qsys" +set_global_assignment -entity "system_jtag_uart_0" -library "system" -name IP_TOOL_NAME "altera_avalon_jtag_uart" +set_global_assignment -entity "system_jtag_uart_0" -library "system" -name IP_TOOL_VERSION "12.1" +set_global_assignment -entity "system_jtag_uart_0" -library "system" -name IP_TOOL_ENV "qsys" +set_global_assignment -entity "system_pio_sw" -library "system" -name IP_TOOL_NAME "altera_avalon_pio" +set_global_assignment -entity "system_pio_sw" -library "system" -name IP_TOOL_VERSION "12.1" +set_global_assignment -entity "system_pio_sw" -library "system" -name IP_TOOL_ENV "qsys" +set_global_assignment -entity "system_pio_key" -library "system" -name IP_TOOL_NAME "altera_avalon_pio" +set_global_assignment -entity "system_pio_key" -library "system" -name IP_TOOL_VERSION "12.1" +set_global_assignment -entity "system_pio_key" -library "system" -name IP_TOOL_ENV "qsys" +set_global_assignment -entity "system_pio_led" -library "system" -name IP_TOOL_NAME "altera_avalon_pio" +set_global_assignment -entity "system_pio_led" -library "system" -name IP_TOOL_VERSION "12.1" +set_global_assignment -entity "system_pio_led" -library "system" -name IP_TOOL_ENV "qsys" +set_global_assignment -entity "system_uart_0" -library "system" -name IP_TOOL_NAME "altera_avalon_uart" +set_global_assignment -entity "system_uart_0" -library "system" -name IP_TOOL_VERSION "12.1" +set_global_assignment -entity "system_uart_0" -library "system" -name IP_TOOL_ENV "qsys" +set_global_assignment -entity "system_sys_clk_timer" -library "system" -name IP_TOOL_NAME "altera_avalon_timer" +set_global_assignment -entity "system_sys_clk_timer" -library "system" -name IP_TOOL_VERSION "12.1" +set_global_assignment -entity "system_sys_clk_timer" -library "system" -name IP_TOOL_ENV "qsys" +set_global_assignment -entity "system_sdram" -library "system" -name IP_TOOL_NAME "altera_avalon_new_sdram_controller" +set_global_assignment -entity "system_sdram" -library "system" -name IP_TOOL_VERSION "12.1" +set_global_assignment -entity "system_sdram" -library "system" -name IP_TOOL_ENV "qsys" +set_global_assignment -entity "system_sysid" -library "system" -name IP_TOOL_NAME "altera_avalon_sysid_qsys" +set_global_assignment -entity "system_sysid" -library "system" -name IP_TOOL_VERSION "12.1" +set_global_assignment -entity "system_sysid" -library "system" -name IP_TOOL_ENV "qsys" +set_global_assignment -entity "system_cpu" -library "system" -name IP_TOOL_NAME "altera_nios2_qsys" +set_global_assignment -entity "system_cpu" -library "system" -name IP_TOOL_VERSION "12.1" +set_global_assignment -entity "system_cpu" -library "system" -name IP_TOOL_ENV "qsys" diff --git a/MCTEST/DE0-nano-HD/system/synthesis/system.v b/MCTEST/DE0-nano-HD/system/synthesis/system.v new file mode 100644 index 00000000..b25380e9 --- /dev/null +++ b/MCTEST/DE0-nano-HD/system/synthesis/system.v @@ -0,0 +1,4031 @@ +// system.v + +// Generated using ACDS version 12.1sp1 243 at 2014.03.06.09:42:57 + +`timescale 1 ps / 1 ps +module system ( + output wire [12:0] sdram_addr, // sdram.addr + output wire [1:0] sdram_ba, // .ba + output wire sdram_cas_n, // .cas_n + output wire sdram_cke, // .cke + output wire sdram_cs_n, // .cs_n + inout wire [15:0] sdram_dq, // .dq + output wire [1:0] sdram_dqm, // .dqm + output wire sdram_ras_n, // .ras_n + output wire sdram_we_n, // .we_n + output wire [6:0] pio_led_export, // pio_led.export + input wire rs232_motor_RXD, // rs232_motor.RXD + output wire rs232_motor_TXD, // .TXD + input wire [3:0] pio_sw_export, // pio_sw.export + output wire pio_motor_rst_export, // pio_motor_rst.export + input wire uart_0_rxd, // uart_0.rxd + output wire uart_0_txd, // .txd + input wire reset_reset_n, // reset.reset_n + input wire clk_clk, // clk.clk + input wire [1:0] pio_key_export // pio_key.export + ); + + wire cpu_instruction_master_waitrequest; // cpu_instruction_master_translator:av_waitrequest -> cpu:i_waitrequest + wire [25:0] cpu_instruction_master_address; // cpu:i_address -> cpu_instruction_master_translator:av_address + wire cpu_instruction_master_read; // cpu:i_read -> cpu_instruction_master_translator:av_read + wire [31:0] cpu_instruction_master_readdata; // cpu_instruction_master_translator:av_readdata -> cpu:i_readdata + wire cpu_instruction_master_readdatavalid; // cpu_instruction_master_translator:av_readdatavalid -> cpu:i_readdatavalid + wire cpu_data_master_waitrequest; // cpu_data_master_translator:av_waitrequest -> cpu:d_waitrequest + wire [31:0] cpu_data_master_writedata; // cpu:d_writedata -> cpu_data_master_translator:av_writedata + wire [25:0] cpu_data_master_address; // cpu:d_address -> cpu_data_master_translator:av_address + wire cpu_data_master_write; // cpu:d_write -> cpu_data_master_translator:av_write + wire cpu_data_master_read; // cpu:d_read -> cpu_data_master_translator:av_read + wire [31:0] cpu_data_master_readdata; // cpu_data_master_translator:av_readdata -> cpu:d_readdata + wire cpu_data_master_debugaccess; // cpu:jtag_debug_module_debugaccess_to_roms -> cpu_data_master_translator:av_debugaccess + wire cpu_data_master_readdatavalid; // cpu_data_master_translator:av_readdatavalid -> cpu:d_readdatavalid + wire [3:0] cpu_data_master_byteenable; // cpu:d_byteenable -> cpu_data_master_translator:av_byteenable + wire [31:0] cpu_jtag_debug_module_translator_avalon_anti_slave_0_writedata; // cpu_jtag_debug_module_translator:av_writedata -> cpu:jtag_debug_module_writedata + wire [8:0] cpu_jtag_debug_module_translator_avalon_anti_slave_0_address; // cpu_jtag_debug_module_translator:av_address -> cpu:jtag_debug_module_address + wire cpu_jtag_debug_module_translator_avalon_anti_slave_0_chipselect; // cpu_jtag_debug_module_translator:av_chipselect -> cpu:jtag_debug_module_select + wire cpu_jtag_debug_module_translator_avalon_anti_slave_0_write; // cpu_jtag_debug_module_translator:av_write -> cpu:jtag_debug_module_write + wire [31:0] cpu_jtag_debug_module_translator_avalon_anti_slave_0_readdata; // cpu:jtag_debug_module_readdata -> cpu_jtag_debug_module_translator:av_readdata + wire cpu_jtag_debug_module_translator_avalon_anti_slave_0_begintransfer; // cpu_jtag_debug_module_translator:av_begintransfer -> cpu:jtag_debug_module_begintransfer + wire cpu_jtag_debug_module_translator_avalon_anti_slave_0_debugaccess; // cpu_jtag_debug_module_translator:av_debugaccess -> cpu:jtag_debug_module_debugaccess + wire [3:0] cpu_jtag_debug_module_translator_avalon_anti_slave_0_byteenable; // cpu_jtag_debug_module_translator:av_byteenable -> cpu:jtag_debug_module_byteenable + wire sdram_s1_translator_avalon_anti_slave_0_waitrequest; // sdram:za_waitrequest -> sdram_s1_translator:av_waitrequest + wire [15:0] sdram_s1_translator_avalon_anti_slave_0_writedata; // sdram_s1_translator:av_writedata -> sdram:az_data + wire [22:0] sdram_s1_translator_avalon_anti_slave_0_address; // sdram_s1_translator:av_address -> sdram:az_addr + wire sdram_s1_translator_avalon_anti_slave_0_chipselect; // sdram_s1_translator:av_chipselect -> sdram:az_cs + wire sdram_s1_translator_avalon_anti_slave_0_write; // sdram_s1_translator:av_write -> sdram:az_wr_n + wire sdram_s1_translator_avalon_anti_slave_0_read; // sdram_s1_translator:av_read -> sdram:az_rd_n + wire [15:0] sdram_s1_translator_avalon_anti_slave_0_readdata; // sdram:za_data -> sdram_s1_translator:av_readdata + wire sdram_s1_translator_avalon_anti_slave_0_readdatavalid; // sdram:za_valid -> sdram_s1_translator:av_readdatavalid + wire [1:0] sdram_s1_translator_avalon_anti_slave_0_byteenable; // sdram_s1_translator:av_byteenable -> sdram:az_be_n + wire [0:0] sysid_control_slave_translator_avalon_anti_slave_0_address; // sysid_control_slave_translator:av_address -> sysid:address + wire [31:0] sysid_control_slave_translator_avalon_anti_slave_0_readdata; // sysid:readdata -> sysid_control_slave_translator:av_readdata + wire [15:0] sys_clk_timer_s1_translator_avalon_anti_slave_0_writedata; // sys_clk_timer_s1_translator:av_writedata -> sys_clk_timer:writedata + wire [2:0] sys_clk_timer_s1_translator_avalon_anti_slave_0_address; // sys_clk_timer_s1_translator:av_address -> sys_clk_timer:address + wire sys_clk_timer_s1_translator_avalon_anti_slave_0_chipselect; // sys_clk_timer_s1_translator:av_chipselect -> sys_clk_timer:chipselect + wire sys_clk_timer_s1_translator_avalon_anti_slave_0_write; // sys_clk_timer_s1_translator:av_write -> sys_clk_timer:write_n + wire [15:0] sys_clk_timer_s1_translator_avalon_anti_slave_0_readdata; // sys_clk_timer:readdata -> sys_clk_timer_s1_translator:av_readdata + wire [15:0] uart_0_s1_translator_avalon_anti_slave_0_writedata; // uart_0_s1_translator:av_writedata -> uart_0:writedata + wire [2:0] uart_0_s1_translator_avalon_anti_slave_0_address; // uart_0_s1_translator:av_address -> uart_0:address + wire uart_0_s1_translator_avalon_anti_slave_0_chipselect; // uart_0_s1_translator:av_chipselect -> uart_0:chipselect + wire uart_0_s1_translator_avalon_anti_slave_0_write; // uart_0_s1_translator:av_write -> uart_0:write_n + wire uart_0_s1_translator_avalon_anti_slave_0_read; // uart_0_s1_translator:av_read -> uart_0:read_n + wire [15:0] uart_0_s1_translator_avalon_anti_slave_0_readdata; // uart_0:readdata -> uart_0_s1_translator:av_readdata + wire uart_0_s1_translator_avalon_anti_slave_0_begintransfer; // uart_0_s1_translator:av_begintransfer -> uart_0:begintransfer + wire [31:0] pio_led_s1_translator_avalon_anti_slave_0_writedata; // pio_led_s1_translator:av_writedata -> pio_led:writedata + wire [2:0] pio_led_s1_translator_avalon_anti_slave_0_address; // pio_led_s1_translator:av_address -> pio_led:address + wire pio_led_s1_translator_avalon_anti_slave_0_chipselect; // pio_led_s1_translator:av_chipselect -> pio_led:chipselect + wire pio_led_s1_translator_avalon_anti_slave_0_write; // pio_led_s1_translator:av_write -> pio_led:write_n + wire [31:0] pio_led_s1_translator_avalon_anti_slave_0_readdata; // pio_led:readdata -> pio_led_s1_translator:av_readdata + wire [1:0] pio_key_s1_translator_avalon_anti_slave_0_address; // pio_key_s1_translator:av_address -> pio_key:address + wire [31:0] pio_key_s1_translator_avalon_anti_slave_0_readdata; // pio_key:readdata -> pio_key_s1_translator:av_readdata + wire [1:0] pio_sw_s1_translator_avalon_anti_slave_0_address; // pio_sw_s1_translator:av_address -> pio_sw:address + wire [31:0] pio_sw_s1_translator_avalon_anti_slave_0_readdata; // pio_sw:readdata -> pio_sw_s1_translator:av_readdata + wire jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_waitrequest; // jtag_uart_0:av_waitrequest -> jtag_uart_0_avalon_jtag_slave_translator:av_waitrequest + wire [31:0] jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_writedata; // jtag_uart_0_avalon_jtag_slave_translator:av_writedata -> jtag_uart_0:av_writedata + wire [0:0] jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_address; // jtag_uart_0_avalon_jtag_slave_translator:av_address -> jtag_uart_0:av_address + wire jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_chipselect; // jtag_uart_0_avalon_jtag_slave_translator:av_chipselect -> jtag_uart_0:av_chipselect + wire jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_write; // jtag_uart_0_avalon_jtag_slave_translator:av_write -> jtag_uart_0:av_write_n + wire jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_read; // jtag_uart_0_avalon_jtag_slave_translator:av_read -> jtag_uart_0:av_read_n + wire [31:0] jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_readdata; // jtag_uart_0:av_readdata -> jtag_uart_0_avalon_jtag_slave_translator:av_readdata + wire [31:0] pio_motor_rst_s1_translator_avalon_anti_slave_0_writedata; // pio_motor_rst_s1_translator:av_writedata -> pio_motor_rst:writedata + wire [1:0] pio_motor_rst_s1_translator_avalon_anti_slave_0_address; // pio_motor_rst_s1_translator:av_address -> pio_motor_rst:address + wire pio_motor_rst_s1_translator_avalon_anti_slave_0_chipselect; // pio_motor_rst_s1_translator:av_chipselect -> pio_motor_rst:chipselect + wire pio_motor_rst_s1_translator_avalon_anti_slave_0_write; // pio_motor_rst_s1_translator:av_write -> pio_motor_rst:write_n + wire [31:0] pio_motor_rst_s1_translator_avalon_anti_slave_0_readdata; // pio_motor_rst:readdata -> pio_motor_rst_s1_translator:av_readdata + wire [31:0] rs232_motor_avalon_rs232_slave_translator_avalon_anti_slave_0_writedata; // rs232_motor_avalon_rs232_slave_translator:av_writedata -> rs232_motor:writedata + wire [0:0] rs232_motor_avalon_rs232_slave_translator_avalon_anti_slave_0_address; // rs232_motor_avalon_rs232_slave_translator:av_address -> rs232_motor:address + wire rs232_motor_avalon_rs232_slave_translator_avalon_anti_slave_0_chipselect; // rs232_motor_avalon_rs232_slave_translator:av_chipselect -> rs232_motor:chipselect + wire rs232_motor_avalon_rs232_slave_translator_avalon_anti_slave_0_write; // rs232_motor_avalon_rs232_slave_translator:av_write -> rs232_motor:write + wire rs232_motor_avalon_rs232_slave_translator_avalon_anti_slave_0_read; // rs232_motor_avalon_rs232_slave_translator:av_read -> rs232_motor:read + wire [31:0] rs232_motor_avalon_rs232_slave_translator_avalon_anti_slave_0_readdata; // rs232_motor:readdata -> rs232_motor_avalon_rs232_slave_translator:av_readdata + wire [3:0] rs232_motor_avalon_rs232_slave_translator_avalon_anti_slave_0_byteenable; // rs232_motor_avalon_rs232_slave_translator:av_byteenable -> rs232_motor:byteenable + wire cpu_instruction_master_translator_avalon_universal_master_0_waitrequest; // cpu_instruction_master_translator_avalon_universal_master_0_agent:av_waitrequest -> cpu_instruction_master_translator:uav_waitrequest + wire [2:0] cpu_instruction_master_translator_avalon_universal_master_0_burstcount; // cpu_instruction_master_translator:uav_burstcount -> cpu_instruction_master_translator_avalon_universal_master_0_agent:av_burstcount + wire [31:0] cpu_instruction_master_translator_avalon_universal_master_0_writedata; // cpu_instruction_master_translator:uav_writedata -> cpu_instruction_master_translator_avalon_universal_master_0_agent:av_writedata + wire [25:0] cpu_instruction_master_translator_avalon_universal_master_0_address; // cpu_instruction_master_translator:uav_address -> cpu_instruction_master_translator_avalon_universal_master_0_agent:av_address + wire cpu_instruction_master_translator_avalon_universal_master_0_lock; // cpu_instruction_master_translator:uav_lock -> cpu_instruction_master_translator_avalon_universal_master_0_agent:av_lock + wire cpu_instruction_master_translator_avalon_universal_master_0_write; // cpu_instruction_master_translator:uav_write -> cpu_instruction_master_translator_avalon_universal_master_0_agent:av_write + wire cpu_instruction_master_translator_avalon_universal_master_0_read; // cpu_instruction_master_translator:uav_read -> cpu_instruction_master_translator_avalon_universal_master_0_agent:av_read + wire [31:0] cpu_instruction_master_translator_avalon_universal_master_0_readdata; // cpu_instruction_master_translator_avalon_universal_master_0_agent:av_readdata -> cpu_instruction_master_translator:uav_readdata + wire cpu_instruction_master_translator_avalon_universal_master_0_debugaccess; // cpu_instruction_master_translator:uav_debugaccess -> cpu_instruction_master_translator_avalon_universal_master_0_agent:av_debugaccess + wire [3:0] cpu_instruction_master_translator_avalon_universal_master_0_byteenable; // cpu_instruction_master_translator:uav_byteenable -> cpu_instruction_master_translator_avalon_universal_master_0_agent:av_byteenable + wire cpu_instruction_master_translator_avalon_universal_master_0_readdatavalid; // cpu_instruction_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> cpu_instruction_master_translator:uav_readdatavalid + wire cpu_data_master_translator_avalon_universal_master_0_waitrequest; // cpu_data_master_translator_avalon_universal_master_0_agent:av_waitrequest -> cpu_data_master_translator:uav_waitrequest + wire [2:0] cpu_data_master_translator_avalon_universal_master_0_burstcount; // cpu_data_master_translator:uav_burstcount -> cpu_data_master_translator_avalon_universal_master_0_agent:av_burstcount + wire [31:0] cpu_data_master_translator_avalon_universal_master_0_writedata; // cpu_data_master_translator:uav_writedata -> cpu_data_master_translator_avalon_universal_master_0_agent:av_writedata + wire [25:0] cpu_data_master_translator_avalon_universal_master_0_address; // cpu_data_master_translator:uav_address -> cpu_data_master_translator_avalon_universal_master_0_agent:av_address + wire cpu_data_master_translator_avalon_universal_master_0_lock; // cpu_data_master_translator:uav_lock -> cpu_data_master_translator_avalon_universal_master_0_agent:av_lock + wire cpu_data_master_translator_avalon_universal_master_0_write; // cpu_data_master_translator:uav_write -> cpu_data_master_translator_avalon_universal_master_0_agent:av_write + wire cpu_data_master_translator_avalon_universal_master_0_read; // cpu_data_master_translator:uav_read -> cpu_data_master_translator_avalon_universal_master_0_agent:av_read + wire [31:0] cpu_data_master_translator_avalon_universal_master_0_readdata; // cpu_data_master_translator_avalon_universal_master_0_agent:av_readdata -> cpu_data_master_translator:uav_readdata + wire cpu_data_master_translator_avalon_universal_master_0_debugaccess; // cpu_data_master_translator:uav_debugaccess -> cpu_data_master_translator_avalon_universal_master_0_agent:av_debugaccess + wire [3:0] cpu_data_master_translator_avalon_universal_master_0_byteenable; // cpu_data_master_translator:uav_byteenable -> cpu_data_master_translator_avalon_universal_master_0_agent:av_byteenable + wire cpu_data_master_translator_avalon_universal_master_0_readdatavalid; // cpu_data_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> cpu_data_master_translator:uav_readdatavalid + wire cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_waitrequest; // cpu_jtag_debug_module_translator:uav_waitrequest -> cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_waitrequest + wire [2:0] cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_burstcount; // cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_burstcount -> cpu_jtag_debug_module_translator:uav_burstcount + wire [31:0] cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_writedata; // cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_writedata -> cpu_jtag_debug_module_translator:uav_writedata + wire [25:0] cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_address; // cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_address -> cpu_jtag_debug_module_translator:uav_address + wire cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_write; // cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_write -> cpu_jtag_debug_module_translator:uav_write + wire cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_lock; // cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_lock -> cpu_jtag_debug_module_translator:uav_lock + wire cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_read; // cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_read -> cpu_jtag_debug_module_translator:uav_read + wire [31:0] cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdata; // cpu_jtag_debug_module_translator:uav_readdata -> cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_readdata + wire cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // cpu_jtag_debug_module_translator:uav_readdatavalid -> cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_readdatavalid + wire cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_debugaccess; // cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_debugaccess -> cpu_jtag_debug_module_translator:uav_debugaccess + wire [3:0] cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_byteenable; // cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_byteenable -> cpu_jtag_debug_module_translator:uav_byteenable + wire cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket + wire cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_valid; // cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_valid -> cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid + wire cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket + wire [101:0] cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_data; // cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_data -> cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data + wire cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_ready; // cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_ready + wire cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket + wire cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_valid + wire cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket + wire [101:0] cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_data + wire cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_ready -> cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready + wire cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid + wire [31:0] cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data + wire cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready + wire sdram_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // sdram_s1_translator:uav_waitrequest -> sdram_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest + wire [1:0] sdram_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // sdram_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> sdram_s1_translator:uav_burstcount + wire [15:0] sdram_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // sdram_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> sdram_s1_translator:uav_writedata + wire [25:0] sdram_s1_translator_avalon_universal_slave_0_agent_m0_address; // sdram_s1_translator_avalon_universal_slave_0_agent:m0_address -> sdram_s1_translator:uav_address + wire sdram_s1_translator_avalon_universal_slave_0_agent_m0_write; // sdram_s1_translator_avalon_universal_slave_0_agent:m0_write -> sdram_s1_translator:uav_write + wire sdram_s1_translator_avalon_universal_slave_0_agent_m0_lock; // sdram_s1_translator_avalon_universal_slave_0_agent:m0_lock -> sdram_s1_translator:uav_lock + wire sdram_s1_translator_avalon_universal_slave_0_agent_m0_read; // sdram_s1_translator_avalon_universal_slave_0_agent:m0_read -> sdram_s1_translator:uav_read + wire [15:0] sdram_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // sdram_s1_translator:uav_readdata -> sdram_s1_translator_avalon_universal_slave_0_agent:m0_readdata + wire sdram_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // sdram_s1_translator:uav_readdatavalid -> sdram_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid + wire sdram_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // sdram_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> sdram_s1_translator:uav_debugaccess + wire [1:0] sdram_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // sdram_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> sdram_s1_translator:uav_byteenable + wire sdram_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // sdram_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket + wire sdram_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // sdram_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid + wire sdram_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // sdram_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket + wire [83:0] sdram_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // sdram_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data + wire sdram_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> sdram_s1_translator_avalon_universal_slave_0_agent:rf_source_ready + wire sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> sdram_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket + wire sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> sdram_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid + wire sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> sdram_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket + wire [83:0] sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> sdram_s1_translator_avalon_universal_slave_0_agent:rf_sink_data + wire sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // sdram_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready + wire sdram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // sdram_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> sdram_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid + wire [15:0] sdram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // sdram_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> sdram_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data + wire sdram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // sdram_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> sdram_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready + wire sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest; // sysid_control_slave_translator:uav_waitrequest -> sysid_control_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest + wire [2:0] sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount; // sysid_control_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> sysid_control_slave_translator:uav_burstcount + wire [31:0] sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata; // sysid_control_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> sysid_control_slave_translator:uav_writedata + wire [25:0] sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_address; // sysid_control_slave_translator_avalon_universal_slave_0_agent:m0_address -> sysid_control_slave_translator:uav_address + wire sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_write; // sysid_control_slave_translator_avalon_universal_slave_0_agent:m0_write -> sysid_control_slave_translator:uav_write + wire sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_lock; // sysid_control_slave_translator_avalon_universal_slave_0_agent:m0_lock -> sysid_control_slave_translator:uav_lock + wire sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_read; // sysid_control_slave_translator_avalon_universal_slave_0_agent:m0_read -> sysid_control_slave_translator:uav_read + wire [31:0] sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata; // sysid_control_slave_translator:uav_readdata -> sysid_control_slave_translator_avalon_universal_slave_0_agent:m0_readdata + wire sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // sysid_control_slave_translator:uav_readdatavalid -> sysid_control_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid + wire sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess; // sysid_control_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> sysid_control_slave_translator:uav_debugaccess + wire [3:0] sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable; // sysid_control_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> sysid_control_slave_translator:uav_byteenable + wire sysid_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // sysid_control_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket + wire sysid_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid; // sysid_control_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid + wire sysid_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // sysid_control_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket + wire [101:0] sysid_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data; // sysid_control_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data + wire sysid_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready; // sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> sysid_control_slave_translator_avalon_universal_slave_0_agent:rf_source_ready + wire sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> sysid_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket + wire sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> sysid_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid + wire sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> sysid_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket + wire [101:0] sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> sysid_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_data + wire sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // sysid_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready + wire sysid_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // sysid_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> sysid_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid + wire [31:0] sysid_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // sysid_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> sysid_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data + wire sysid_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // sysid_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> sysid_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready + wire sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // sys_clk_timer_s1_translator:uav_waitrequest -> sys_clk_timer_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest + wire [2:0] sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // sys_clk_timer_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> sys_clk_timer_s1_translator:uav_burstcount + wire [31:0] sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // sys_clk_timer_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> sys_clk_timer_s1_translator:uav_writedata + wire [25:0] sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_m0_address; // sys_clk_timer_s1_translator_avalon_universal_slave_0_agent:m0_address -> sys_clk_timer_s1_translator:uav_address + wire sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_m0_write; // sys_clk_timer_s1_translator_avalon_universal_slave_0_agent:m0_write -> sys_clk_timer_s1_translator:uav_write + wire sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_m0_lock; // sys_clk_timer_s1_translator_avalon_universal_slave_0_agent:m0_lock -> sys_clk_timer_s1_translator:uav_lock + wire sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_m0_read; // sys_clk_timer_s1_translator_avalon_universal_slave_0_agent:m0_read -> sys_clk_timer_s1_translator:uav_read + wire [31:0] sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // sys_clk_timer_s1_translator:uav_readdata -> sys_clk_timer_s1_translator_avalon_universal_slave_0_agent:m0_readdata + wire sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // sys_clk_timer_s1_translator:uav_readdatavalid -> sys_clk_timer_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid + wire sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // sys_clk_timer_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> sys_clk_timer_s1_translator:uav_debugaccess + wire [3:0] sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // sys_clk_timer_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> sys_clk_timer_s1_translator:uav_byteenable + wire sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // sys_clk_timer_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket + wire sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // sys_clk_timer_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid + wire sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // sys_clk_timer_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket + wire [101:0] sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // sys_clk_timer_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data + wire sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> sys_clk_timer_s1_translator_avalon_universal_slave_0_agent:rf_source_ready + wire sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> sys_clk_timer_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket + wire sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> sys_clk_timer_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid + wire sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> sys_clk_timer_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket + wire [101:0] sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> sys_clk_timer_s1_translator_avalon_universal_slave_0_agent:rf_sink_data + wire sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // sys_clk_timer_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready + wire sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // sys_clk_timer_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> sys_clk_timer_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid + wire [31:0] sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // sys_clk_timer_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> sys_clk_timer_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data + wire sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // sys_clk_timer_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> sys_clk_timer_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready + wire uart_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // uart_0_s1_translator:uav_waitrequest -> uart_0_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest + wire [2:0] uart_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // uart_0_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> uart_0_s1_translator:uav_burstcount + wire [31:0] uart_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // uart_0_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> uart_0_s1_translator:uav_writedata + wire [25:0] uart_0_s1_translator_avalon_universal_slave_0_agent_m0_address; // uart_0_s1_translator_avalon_universal_slave_0_agent:m0_address -> uart_0_s1_translator:uav_address + wire uart_0_s1_translator_avalon_universal_slave_0_agent_m0_write; // uart_0_s1_translator_avalon_universal_slave_0_agent:m0_write -> uart_0_s1_translator:uav_write + wire uart_0_s1_translator_avalon_universal_slave_0_agent_m0_lock; // uart_0_s1_translator_avalon_universal_slave_0_agent:m0_lock -> uart_0_s1_translator:uav_lock + wire uart_0_s1_translator_avalon_universal_slave_0_agent_m0_read; // uart_0_s1_translator_avalon_universal_slave_0_agent:m0_read -> uart_0_s1_translator:uav_read + wire [31:0] uart_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // uart_0_s1_translator:uav_readdata -> uart_0_s1_translator_avalon_universal_slave_0_agent:m0_readdata + wire uart_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // uart_0_s1_translator:uav_readdatavalid -> uart_0_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid + wire uart_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // uart_0_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> uart_0_s1_translator:uav_debugaccess + wire [3:0] uart_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // uart_0_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> uart_0_s1_translator:uav_byteenable + wire uart_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // uart_0_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> uart_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket + wire uart_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // uart_0_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> uart_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid + wire uart_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // uart_0_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> uart_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket + wire [101:0] uart_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // uart_0_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> uart_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data + wire uart_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // uart_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> uart_0_s1_translator_avalon_universal_slave_0_agent:rf_source_ready + wire uart_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // uart_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> uart_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket + wire uart_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // uart_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> uart_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid + wire uart_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // uart_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> uart_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket + wire [101:0] uart_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // uart_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> uart_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_data + wire uart_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // uart_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> uart_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready + wire uart_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // uart_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> uart_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid + wire [31:0] uart_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // uart_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> uart_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data + wire uart_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // uart_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> uart_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready + wire pio_led_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // pio_led_s1_translator:uav_waitrequest -> pio_led_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest + wire [2:0] pio_led_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // pio_led_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> pio_led_s1_translator:uav_burstcount + wire [31:0] pio_led_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // pio_led_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> pio_led_s1_translator:uav_writedata + wire [25:0] pio_led_s1_translator_avalon_universal_slave_0_agent_m0_address; // pio_led_s1_translator_avalon_universal_slave_0_agent:m0_address -> pio_led_s1_translator:uav_address + wire pio_led_s1_translator_avalon_universal_slave_0_agent_m0_write; // pio_led_s1_translator_avalon_universal_slave_0_agent:m0_write -> pio_led_s1_translator:uav_write + wire pio_led_s1_translator_avalon_universal_slave_0_agent_m0_lock; // pio_led_s1_translator_avalon_universal_slave_0_agent:m0_lock -> pio_led_s1_translator:uav_lock + wire pio_led_s1_translator_avalon_universal_slave_0_agent_m0_read; // pio_led_s1_translator_avalon_universal_slave_0_agent:m0_read -> pio_led_s1_translator:uav_read + wire [31:0] pio_led_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // pio_led_s1_translator:uav_readdata -> pio_led_s1_translator_avalon_universal_slave_0_agent:m0_readdata + wire pio_led_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // pio_led_s1_translator:uav_readdatavalid -> pio_led_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid + wire pio_led_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // pio_led_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> pio_led_s1_translator:uav_debugaccess + wire [3:0] pio_led_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // pio_led_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> pio_led_s1_translator:uav_byteenable + wire pio_led_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // pio_led_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket + wire pio_led_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // pio_led_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid + wire pio_led_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // pio_led_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket + wire [101:0] pio_led_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // pio_led_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data + wire pio_led_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> pio_led_s1_translator_avalon_universal_slave_0_agent:rf_source_ready + wire pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> pio_led_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket + wire pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> pio_led_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid + wire pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> pio_led_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket + wire [101:0] pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> pio_led_s1_translator_avalon_universal_slave_0_agent:rf_sink_data + wire pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // pio_led_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready + wire pio_led_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // pio_led_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> pio_led_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid + wire [31:0] pio_led_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // pio_led_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> pio_led_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data + wire pio_led_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // pio_led_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> pio_led_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready + wire pio_key_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // pio_key_s1_translator:uav_waitrequest -> pio_key_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest + wire [2:0] pio_key_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // pio_key_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> pio_key_s1_translator:uav_burstcount + wire [31:0] pio_key_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // pio_key_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> pio_key_s1_translator:uav_writedata + wire [25:0] pio_key_s1_translator_avalon_universal_slave_0_agent_m0_address; // pio_key_s1_translator_avalon_universal_slave_0_agent:m0_address -> pio_key_s1_translator:uav_address + wire pio_key_s1_translator_avalon_universal_slave_0_agent_m0_write; // pio_key_s1_translator_avalon_universal_slave_0_agent:m0_write -> pio_key_s1_translator:uav_write + wire pio_key_s1_translator_avalon_universal_slave_0_agent_m0_lock; // pio_key_s1_translator_avalon_universal_slave_0_agent:m0_lock -> pio_key_s1_translator:uav_lock + wire pio_key_s1_translator_avalon_universal_slave_0_agent_m0_read; // pio_key_s1_translator_avalon_universal_slave_0_agent:m0_read -> pio_key_s1_translator:uav_read + wire [31:0] pio_key_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // pio_key_s1_translator:uav_readdata -> pio_key_s1_translator_avalon_universal_slave_0_agent:m0_readdata + wire pio_key_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // pio_key_s1_translator:uav_readdatavalid -> pio_key_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid + wire pio_key_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // pio_key_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> pio_key_s1_translator:uav_debugaccess + wire [3:0] pio_key_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // pio_key_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> pio_key_s1_translator:uav_byteenable + wire pio_key_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // pio_key_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> pio_key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket + wire pio_key_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // pio_key_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> pio_key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid + wire pio_key_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // pio_key_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> pio_key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket + wire [101:0] pio_key_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // pio_key_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> pio_key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data + wire pio_key_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // pio_key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> pio_key_s1_translator_avalon_universal_slave_0_agent:rf_source_ready + wire pio_key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // pio_key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> pio_key_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket + wire pio_key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // pio_key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> pio_key_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid + wire pio_key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // pio_key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> pio_key_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket + wire [101:0] pio_key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // pio_key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> pio_key_s1_translator_avalon_universal_slave_0_agent:rf_sink_data + wire pio_key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // pio_key_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> pio_key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready + wire pio_key_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // pio_key_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> pio_key_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid + wire [31:0] pio_key_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // pio_key_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> pio_key_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data + wire pio_key_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // pio_key_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> pio_key_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready + wire pio_sw_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // pio_sw_s1_translator:uav_waitrequest -> pio_sw_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest + wire [2:0] pio_sw_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // pio_sw_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> pio_sw_s1_translator:uav_burstcount + wire [31:0] pio_sw_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // pio_sw_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> pio_sw_s1_translator:uav_writedata + wire [25:0] pio_sw_s1_translator_avalon_universal_slave_0_agent_m0_address; // pio_sw_s1_translator_avalon_universal_slave_0_agent:m0_address -> pio_sw_s1_translator:uav_address + wire pio_sw_s1_translator_avalon_universal_slave_0_agent_m0_write; // pio_sw_s1_translator_avalon_universal_slave_0_agent:m0_write -> pio_sw_s1_translator:uav_write + wire pio_sw_s1_translator_avalon_universal_slave_0_agent_m0_lock; // pio_sw_s1_translator_avalon_universal_slave_0_agent:m0_lock -> pio_sw_s1_translator:uav_lock + wire pio_sw_s1_translator_avalon_universal_slave_0_agent_m0_read; // pio_sw_s1_translator_avalon_universal_slave_0_agent:m0_read -> pio_sw_s1_translator:uav_read + wire [31:0] pio_sw_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // pio_sw_s1_translator:uav_readdata -> pio_sw_s1_translator_avalon_universal_slave_0_agent:m0_readdata + wire pio_sw_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // pio_sw_s1_translator:uav_readdatavalid -> pio_sw_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid + wire pio_sw_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // pio_sw_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> pio_sw_s1_translator:uav_debugaccess + wire [3:0] pio_sw_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // pio_sw_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> pio_sw_s1_translator:uav_byteenable + wire pio_sw_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // pio_sw_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> pio_sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket + wire pio_sw_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // pio_sw_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> pio_sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid + wire pio_sw_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // pio_sw_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> pio_sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket + wire [101:0] pio_sw_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // pio_sw_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> pio_sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data + wire pio_sw_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // pio_sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> pio_sw_s1_translator_avalon_universal_slave_0_agent:rf_source_ready + wire pio_sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // pio_sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> pio_sw_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket + wire pio_sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // pio_sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> pio_sw_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid + wire pio_sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // pio_sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> pio_sw_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket + wire [101:0] pio_sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // pio_sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> pio_sw_s1_translator_avalon_universal_slave_0_agent:rf_sink_data + wire pio_sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // pio_sw_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> pio_sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready + wire pio_sw_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // pio_sw_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> pio_sw_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid + wire [31:0] pio_sw_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // pio_sw_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> pio_sw_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data + wire pio_sw_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // pio_sw_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> pio_sw_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready + wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest; // jtag_uart_0_avalon_jtag_slave_translator:uav_waitrequest -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest + wire [2:0] jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_burstcount; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> jtag_uart_0_avalon_jtag_slave_translator:uav_burstcount + wire [31:0] jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_writedata; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> jtag_uart_0_avalon_jtag_slave_translator:uav_writedata + wire [25:0] jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_address; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_address -> jtag_uart_0_avalon_jtag_slave_translator:uav_address + wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_write; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_write -> jtag_uart_0_avalon_jtag_slave_translator:uav_write + wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_lock; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_lock -> jtag_uart_0_avalon_jtag_slave_translator:uav_lock + wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_read; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_read -> jtag_uart_0_avalon_jtag_slave_translator:uav_read + wire [31:0] jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdata; // jtag_uart_0_avalon_jtag_slave_translator:uav_readdata -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_readdata + wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // jtag_uart_0_avalon_jtag_slave_translator:uav_readdatavalid -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid + wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> jtag_uart_0_avalon_jtag_slave_translator:uav_debugaccess + wire [3:0] jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_byteenable; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> jtag_uart_0_avalon_jtag_slave_translator:uav_byteenable + wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket + wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_valid; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid + wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket + wire [101:0] jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_data; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data + wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_ready; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_ready + wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket + wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid + wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket + wire [101:0] jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_data + wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready + wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid + wire [31:0] jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data + wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready + wire pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // pio_motor_rst_s1_translator:uav_waitrequest -> pio_motor_rst_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest + wire [2:0] pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // pio_motor_rst_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> pio_motor_rst_s1_translator:uav_burstcount + wire [31:0] pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // pio_motor_rst_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> pio_motor_rst_s1_translator:uav_writedata + wire [25:0] pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_m0_address; // pio_motor_rst_s1_translator_avalon_universal_slave_0_agent:m0_address -> pio_motor_rst_s1_translator:uav_address + wire pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_m0_write; // pio_motor_rst_s1_translator_avalon_universal_slave_0_agent:m0_write -> pio_motor_rst_s1_translator:uav_write + wire pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_m0_lock; // pio_motor_rst_s1_translator_avalon_universal_slave_0_agent:m0_lock -> pio_motor_rst_s1_translator:uav_lock + wire pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_m0_read; // pio_motor_rst_s1_translator_avalon_universal_slave_0_agent:m0_read -> pio_motor_rst_s1_translator:uav_read + wire [31:0] pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // pio_motor_rst_s1_translator:uav_readdata -> pio_motor_rst_s1_translator_avalon_universal_slave_0_agent:m0_readdata + wire pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // pio_motor_rst_s1_translator:uav_readdatavalid -> pio_motor_rst_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid + wire pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // pio_motor_rst_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> pio_motor_rst_s1_translator:uav_debugaccess + wire [3:0] pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // pio_motor_rst_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> pio_motor_rst_s1_translator:uav_byteenable + wire pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // pio_motor_rst_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket + wire pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // pio_motor_rst_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid + wire pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // pio_motor_rst_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket + wire [101:0] pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // pio_motor_rst_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data + wire pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> pio_motor_rst_s1_translator_avalon_universal_slave_0_agent:rf_source_ready + wire pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> pio_motor_rst_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket + wire pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> pio_motor_rst_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid + wire pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> pio_motor_rst_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket + wire [101:0] pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> pio_motor_rst_s1_translator_avalon_universal_slave_0_agent:rf_sink_data + wire pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // pio_motor_rst_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready + wire pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // pio_motor_rst_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> pio_motor_rst_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid + wire [31:0] pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // pio_motor_rst_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> pio_motor_rst_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data + wire pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // pio_motor_rst_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> pio_motor_rst_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready + wire rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest; // rs232_motor_avalon_rs232_slave_translator:uav_waitrequest -> rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest + wire [2:0] rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_burstcount; // rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> rs232_motor_avalon_rs232_slave_translator:uav_burstcount + wire [31:0] rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_writedata; // rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> rs232_motor_avalon_rs232_slave_translator:uav_writedata + wire [25:0] rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_address; // rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:m0_address -> rs232_motor_avalon_rs232_slave_translator:uav_address + wire rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_write; // rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:m0_write -> rs232_motor_avalon_rs232_slave_translator:uav_write + wire rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_lock; // rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:m0_lock -> rs232_motor_avalon_rs232_slave_translator:uav_lock + wire rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_read; // rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:m0_read -> rs232_motor_avalon_rs232_slave_translator:uav_read + wire [31:0] rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_readdata; // rs232_motor_avalon_rs232_slave_translator:uav_readdata -> rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:m0_readdata + wire rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // rs232_motor_avalon_rs232_slave_translator:uav_readdatavalid -> rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid + wire rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess; // rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> rs232_motor_avalon_rs232_slave_translator:uav_debugaccess + wire [3:0] rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_byteenable; // rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> rs232_motor_avalon_rs232_slave_translator:uav_byteenable + wire rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket + wire rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rf_source_valid; // rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid + wire rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket + wire [101:0] rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rf_source_data; // rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data + wire rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rf_source_ready; // rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:rf_source_ready + wire rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket + wire rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid + wire rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket + wire [101:0] rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:rf_sink_data + wire rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready + wire rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid + wire [31:0] rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data + wire rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready + wire cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket; // cpu_instruction_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router:sink_endofpacket + wire cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_valid; // cpu_instruction_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router:sink_valid + wire cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket; // cpu_instruction_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router:sink_startofpacket + wire [100:0] cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_data; // cpu_instruction_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router:sink_data + wire cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_ready; // addr_router:sink_ready -> cpu_instruction_master_translator_avalon_universal_master_0_agent:cp_ready + wire cpu_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket; // cpu_data_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router_001:sink_endofpacket + wire cpu_data_master_translator_avalon_universal_master_0_agent_cp_valid; // cpu_data_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router_001:sink_valid + wire cpu_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket; // cpu_data_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router_001:sink_startofpacket + wire [100:0] cpu_data_master_translator_avalon_universal_master_0_agent_cp_data; // cpu_data_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router_001:sink_data + wire cpu_data_master_translator_avalon_universal_master_0_agent_cp_ready; // addr_router_001:sink_ready -> cpu_data_master_translator_avalon_universal_master_0_agent:cp_ready + wire cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_endofpacket; // cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router:sink_endofpacket + wire cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_valid; // cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_valid -> id_router:sink_valid + wire cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_startofpacket; // cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router:sink_startofpacket + wire [100:0] cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_data; // cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_data -> id_router:sink_data + wire cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_ready; // id_router:sink_ready -> cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_ready + wire sdram_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // sdram_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_001:sink_endofpacket + wire sdram_s1_translator_avalon_universal_slave_0_agent_rp_valid; // sdram_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_001:sink_valid + wire sdram_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // sdram_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_001:sink_startofpacket + wire [82:0] sdram_s1_translator_avalon_universal_slave_0_agent_rp_data; // sdram_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_001:sink_data + wire sdram_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_001:sink_ready -> sdram_s1_translator_avalon_universal_slave_0_agent:rp_ready + wire sysid_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket; // sysid_control_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_002:sink_endofpacket + wire sysid_control_slave_translator_avalon_universal_slave_0_agent_rp_valid; // sysid_control_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_002:sink_valid + wire sysid_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket; // sysid_control_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_002:sink_startofpacket + wire [100:0] sysid_control_slave_translator_avalon_universal_slave_0_agent_rp_data; // sysid_control_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_002:sink_data + wire sysid_control_slave_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_002:sink_ready -> sysid_control_slave_translator_avalon_universal_slave_0_agent:rp_ready + wire sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // sys_clk_timer_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_003:sink_endofpacket + wire sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rp_valid; // sys_clk_timer_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_003:sink_valid + wire sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // sys_clk_timer_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_003:sink_startofpacket + wire [100:0] sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rp_data; // sys_clk_timer_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_003:sink_data + wire sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_003:sink_ready -> sys_clk_timer_s1_translator_avalon_universal_slave_0_agent:rp_ready + wire uart_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // uart_0_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_004:sink_endofpacket + wire uart_0_s1_translator_avalon_universal_slave_0_agent_rp_valid; // uart_0_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_004:sink_valid + wire uart_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // uart_0_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_004:sink_startofpacket + wire [100:0] uart_0_s1_translator_avalon_universal_slave_0_agent_rp_data; // uart_0_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_004:sink_data + wire uart_0_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_004:sink_ready -> uart_0_s1_translator_avalon_universal_slave_0_agent:rp_ready + wire pio_led_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // pio_led_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_005:sink_endofpacket + wire pio_led_s1_translator_avalon_universal_slave_0_agent_rp_valid; // pio_led_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_005:sink_valid + wire pio_led_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // pio_led_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_005:sink_startofpacket + wire [100:0] pio_led_s1_translator_avalon_universal_slave_0_agent_rp_data; // pio_led_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_005:sink_data + wire pio_led_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_005:sink_ready -> pio_led_s1_translator_avalon_universal_slave_0_agent:rp_ready + wire pio_key_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // pio_key_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_006:sink_endofpacket + wire pio_key_s1_translator_avalon_universal_slave_0_agent_rp_valid; // pio_key_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_006:sink_valid + wire pio_key_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // pio_key_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_006:sink_startofpacket + wire [100:0] pio_key_s1_translator_avalon_universal_slave_0_agent_rp_data; // pio_key_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_006:sink_data + wire pio_key_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_006:sink_ready -> pio_key_s1_translator_avalon_universal_slave_0_agent:rp_ready + wire pio_sw_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // pio_sw_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_007:sink_endofpacket + wire pio_sw_s1_translator_avalon_universal_slave_0_agent_rp_valid; // pio_sw_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_007:sink_valid + wire pio_sw_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // pio_sw_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_007:sink_startofpacket + wire [100:0] pio_sw_s1_translator_avalon_universal_slave_0_agent_rp_data; // pio_sw_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_007:sink_data + wire pio_sw_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_007:sink_ready -> pio_sw_s1_translator_avalon_universal_slave_0_agent:rp_ready + wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_008:sink_endofpacket + wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_valid; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_008:sink_valid + wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_008:sink_startofpacket + wire [100:0] jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_data; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_008:sink_data + wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_008:sink_ready -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_ready + wire pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // pio_motor_rst_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_009:sink_endofpacket + wire pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rp_valid; // pio_motor_rst_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_009:sink_valid + wire pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // pio_motor_rst_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_009:sink_startofpacket + wire [100:0] pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rp_data; // pio_motor_rst_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_009:sink_data + wire pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_009:sink_ready -> pio_motor_rst_s1_translator_avalon_universal_slave_0_agent:rp_ready + wire rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket; // rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_010:sink_endofpacket + wire rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rp_valid; // rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_010:sink_valid + wire rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket; // rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_010:sink_startofpacket + wire [100:0] rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rp_data; // rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_010:sink_data + wire rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_010:sink_ready -> rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:rp_ready + wire addr_router_src_endofpacket; // addr_router:src_endofpacket -> limiter:cmd_sink_endofpacket + wire addr_router_src_valid; // addr_router:src_valid -> limiter:cmd_sink_valid + wire addr_router_src_startofpacket; // addr_router:src_startofpacket -> limiter:cmd_sink_startofpacket + wire [100:0] addr_router_src_data; // addr_router:src_data -> limiter:cmd_sink_data + wire [10:0] addr_router_src_channel; // addr_router:src_channel -> limiter:cmd_sink_channel + wire addr_router_src_ready; // limiter:cmd_sink_ready -> addr_router:src_ready + wire limiter_rsp_src_endofpacket; // limiter:rsp_src_endofpacket -> cpu_instruction_master_translator_avalon_universal_master_0_agent:rp_endofpacket + wire limiter_rsp_src_valid; // limiter:rsp_src_valid -> cpu_instruction_master_translator_avalon_universal_master_0_agent:rp_valid + wire limiter_rsp_src_startofpacket; // limiter:rsp_src_startofpacket -> cpu_instruction_master_translator_avalon_universal_master_0_agent:rp_startofpacket + wire [100:0] limiter_rsp_src_data; // limiter:rsp_src_data -> cpu_instruction_master_translator_avalon_universal_master_0_agent:rp_data + wire [10:0] limiter_rsp_src_channel; // limiter:rsp_src_channel -> cpu_instruction_master_translator_avalon_universal_master_0_agent:rp_channel + wire limiter_rsp_src_ready; // cpu_instruction_master_translator_avalon_universal_master_0_agent:rp_ready -> limiter:rsp_src_ready + wire addr_router_001_src_endofpacket; // addr_router_001:src_endofpacket -> limiter_001:cmd_sink_endofpacket + wire addr_router_001_src_valid; // addr_router_001:src_valid -> limiter_001:cmd_sink_valid + wire addr_router_001_src_startofpacket; // addr_router_001:src_startofpacket -> limiter_001:cmd_sink_startofpacket + wire [100:0] addr_router_001_src_data; // addr_router_001:src_data -> limiter_001:cmd_sink_data + wire [10:0] addr_router_001_src_channel; // addr_router_001:src_channel -> limiter_001:cmd_sink_channel + wire addr_router_001_src_ready; // limiter_001:cmd_sink_ready -> addr_router_001:src_ready + wire limiter_001_rsp_src_endofpacket; // limiter_001:rsp_src_endofpacket -> cpu_data_master_translator_avalon_universal_master_0_agent:rp_endofpacket + wire limiter_001_rsp_src_valid; // limiter_001:rsp_src_valid -> cpu_data_master_translator_avalon_universal_master_0_agent:rp_valid + wire limiter_001_rsp_src_startofpacket; // limiter_001:rsp_src_startofpacket -> cpu_data_master_translator_avalon_universal_master_0_agent:rp_startofpacket + wire [100:0] limiter_001_rsp_src_data; // limiter_001:rsp_src_data -> cpu_data_master_translator_avalon_universal_master_0_agent:rp_data + wire [10:0] limiter_001_rsp_src_channel; // limiter_001:rsp_src_channel -> cpu_data_master_translator_avalon_universal_master_0_agent:rp_channel + wire limiter_001_rsp_src_ready; // cpu_data_master_translator_avalon_universal_master_0_agent:rp_ready -> limiter_001:rsp_src_ready + wire burst_adapter_source0_endofpacket; // burst_adapter:source0_endofpacket -> sdram_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket + wire burst_adapter_source0_valid; // burst_adapter:source0_valid -> sdram_s1_translator_avalon_universal_slave_0_agent:cp_valid + wire burst_adapter_source0_startofpacket; // burst_adapter:source0_startofpacket -> sdram_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket + wire [82:0] burst_adapter_source0_data; // burst_adapter:source0_data -> sdram_s1_translator_avalon_universal_slave_0_agent:cp_data + wire burst_adapter_source0_ready; // sdram_s1_translator_avalon_universal_slave_0_agent:cp_ready -> burst_adapter:source0_ready + wire [10:0] burst_adapter_source0_channel; // burst_adapter:source0_channel -> sdram_s1_translator_avalon_universal_slave_0_agent:cp_channel + wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [addr_router:reset, addr_router_001:reset, burst_adapter:reset, cmd_xbar_demux:reset, cmd_xbar_demux_001:reset, cmd_xbar_mux:reset, cmd_xbar_mux_001:reset, cpu:reset_n, cpu_data_master_translator:reset, cpu_data_master_translator_avalon_universal_master_0_agent:reset, cpu_instruction_master_translator:reset, cpu_instruction_master_translator_avalon_universal_master_0_agent:reset, cpu_jtag_debug_module_translator:reset, cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent:reset, cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, id_router:reset, id_router_001:reset, id_router_002:reset, id_router_003:reset, id_router_004:reset, id_router_005:reset, id_router_006:reset, id_router_007:reset, id_router_008:reset, id_router_009:reset, id_router_010:reset, irq_mapper:reset, jtag_uart_0:rst_n, jtag_uart_0_avalon_jtag_slave_translator:reset, jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:reset, jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, limiter:reset, limiter_001:reset, pio_key:reset_n, pio_key_s1_translator:reset, pio_key_s1_translator_avalon_universal_slave_0_agent:reset, pio_key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, pio_led:reset_n, pio_led_s1_translator:reset, pio_led_s1_translator_avalon_universal_slave_0_agent:reset, pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, pio_motor_rst:reset_n, pio_motor_rst_s1_translator:reset, pio_motor_rst_s1_translator_avalon_universal_slave_0_agent:reset, pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, pio_sw:reset_n, pio_sw_s1_translator:reset, pio_sw_s1_translator_avalon_universal_slave_0_agent:reset, pio_sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, rs232_motor:reset, rs232_motor_avalon_rs232_slave_translator:reset, rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:reset, rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, rsp_xbar_demux:reset, rsp_xbar_demux_001:reset, rsp_xbar_demux_002:reset, rsp_xbar_demux_003:reset, rsp_xbar_demux_004:reset, rsp_xbar_demux_005:reset, rsp_xbar_demux_006:reset, rsp_xbar_demux_007:reset, rsp_xbar_demux_008:reset, rsp_xbar_demux_009:reset, rsp_xbar_demux_010:reset, rsp_xbar_mux:reset, rsp_xbar_mux_001:reset, sdram:reset_n, sdram_s1_translator:reset, sdram_s1_translator_avalon_universal_slave_0_agent:reset, sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, sys_clk_timer:reset_n, sys_clk_timer_s1_translator:reset, sys_clk_timer_s1_translator_avalon_universal_slave_0_agent:reset, sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, sysid:reset_n, sysid_control_slave_translator:reset, sysid_control_slave_translator_avalon_universal_slave_0_agent:reset, sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, uart_0:reset_n, uart_0_s1_translator:reset, uart_0_s1_translator_avalon_universal_slave_0_agent:reset, uart_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, width_adapter:reset, width_adapter_001:reset] + wire cpu_jtag_debug_module_reset_reset; // cpu:jtag_debug_module_resetrequest -> rst_controller:reset_in1 + wire cmd_xbar_demux_src0_endofpacket; // cmd_xbar_demux:src0_endofpacket -> cmd_xbar_mux:sink0_endofpacket + wire cmd_xbar_demux_src0_valid; // cmd_xbar_demux:src0_valid -> cmd_xbar_mux:sink0_valid + wire cmd_xbar_demux_src0_startofpacket; // cmd_xbar_demux:src0_startofpacket -> cmd_xbar_mux:sink0_startofpacket + wire [100:0] cmd_xbar_demux_src0_data; // cmd_xbar_demux:src0_data -> cmd_xbar_mux:sink0_data + wire [10:0] cmd_xbar_demux_src0_channel; // cmd_xbar_demux:src0_channel -> cmd_xbar_mux:sink0_channel + wire cmd_xbar_demux_src0_ready; // cmd_xbar_mux:sink0_ready -> cmd_xbar_demux:src0_ready + wire cmd_xbar_demux_src1_endofpacket; // cmd_xbar_demux:src1_endofpacket -> cmd_xbar_mux_001:sink0_endofpacket + wire cmd_xbar_demux_src1_valid; // cmd_xbar_demux:src1_valid -> cmd_xbar_mux_001:sink0_valid + wire cmd_xbar_demux_src1_startofpacket; // cmd_xbar_demux:src1_startofpacket -> cmd_xbar_mux_001:sink0_startofpacket + wire [100:0] cmd_xbar_demux_src1_data; // cmd_xbar_demux:src1_data -> cmd_xbar_mux_001:sink0_data + wire [10:0] cmd_xbar_demux_src1_channel; // cmd_xbar_demux:src1_channel -> cmd_xbar_mux_001:sink0_channel + wire cmd_xbar_demux_src1_ready; // cmd_xbar_mux_001:sink0_ready -> cmd_xbar_demux:src1_ready + wire cmd_xbar_demux_001_src0_endofpacket; // cmd_xbar_demux_001:src0_endofpacket -> cmd_xbar_mux:sink1_endofpacket + wire cmd_xbar_demux_001_src0_valid; // cmd_xbar_demux_001:src0_valid -> cmd_xbar_mux:sink1_valid + wire cmd_xbar_demux_001_src0_startofpacket; // cmd_xbar_demux_001:src0_startofpacket -> cmd_xbar_mux:sink1_startofpacket + wire [100:0] cmd_xbar_demux_001_src0_data; // cmd_xbar_demux_001:src0_data -> cmd_xbar_mux:sink1_data + wire [10:0] cmd_xbar_demux_001_src0_channel; // cmd_xbar_demux_001:src0_channel -> cmd_xbar_mux:sink1_channel + wire cmd_xbar_demux_001_src0_ready; // cmd_xbar_mux:sink1_ready -> cmd_xbar_demux_001:src0_ready + wire cmd_xbar_demux_001_src1_endofpacket; // cmd_xbar_demux_001:src1_endofpacket -> cmd_xbar_mux_001:sink1_endofpacket + wire cmd_xbar_demux_001_src1_valid; // cmd_xbar_demux_001:src1_valid -> cmd_xbar_mux_001:sink1_valid + wire cmd_xbar_demux_001_src1_startofpacket; // cmd_xbar_demux_001:src1_startofpacket -> cmd_xbar_mux_001:sink1_startofpacket + wire [100:0] cmd_xbar_demux_001_src1_data; // cmd_xbar_demux_001:src1_data -> cmd_xbar_mux_001:sink1_data + wire [10:0] cmd_xbar_demux_001_src1_channel; // cmd_xbar_demux_001:src1_channel -> cmd_xbar_mux_001:sink1_channel + wire cmd_xbar_demux_001_src1_ready; // cmd_xbar_mux_001:sink1_ready -> cmd_xbar_demux_001:src1_ready + wire cmd_xbar_demux_001_src2_endofpacket; // cmd_xbar_demux_001:src2_endofpacket -> sysid_control_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket + wire cmd_xbar_demux_001_src2_valid; // cmd_xbar_demux_001:src2_valid -> sysid_control_slave_translator_avalon_universal_slave_0_agent:cp_valid + wire cmd_xbar_demux_001_src2_startofpacket; // cmd_xbar_demux_001:src2_startofpacket -> sysid_control_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket + wire [100:0] cmd_xbar_demux_001_src2_data; // cmd_xbar_demux_001:src2_data -> sysid_control_slave_translator_avalon_universal_slave_0_agent:cp_data + wire [10:0] cmd_xbar_demux_001_src2_channel; // cmd_xbar_demux_001:src2_channel -> sysid_control_slave_translator_avalon_universal_slave_0_agent:cp_channel + wire cmd_xbar_demux_001_src3_endofpacket; // cmd_xbar_demux_001:src3_endofpacket -> sys_clk_timer_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket + wire cmd_xbar_demux_001_src3_valid; // cmd_xbar_demux_001:src3_valid -> sys_clk_timer_s1_translator_avalon_universal_slave_0_agent:cp_valid + wire cmd_xbar_demux_001_src3_startofpacket; // cmd_xbar_demux_001:src3_startofpacket -> sys_clk_timer_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket + wire [100:0] cmd_xbar_demux_001_src3_data; // cmd_xbar_demux_001:src3_data -> sys_clk_timer_s1_translator_avalon_universal_slave_0_agent:cp_data + wire [10:0] cmd_xbar_demux_001_src3_channel; // cmd_xbar_demux_001:src3_channel -> sys_clk_timer_s1_translator_avalon_universal_slave_0_agent:cp_channel + wire cmd_xbar_demux_001_src4_endofpacket; // cmd_xbar_demux_001:src4_endofpacket -> uart_0_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket + wire cmd_xbar_demux_001_src4_valid; // cmd_xbar_demux_001:src4_valid -> uart_0_s1_translator_avalon_universal_slave_0_agent:cp_valid + wire cmd_xbar_demux_001_src4_startofpacket; // cmd_xbar_demux_001:src4_startofpacket -> uart_0_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket + wire [100:0] cmd_xbar_demux_001_src4_data; // cmd_xbar_demux_001:src4_data -> uart_0_s1_translator_avalon_universal_slave_0_agent:cp_data + wire [10:0] cmd_xbar_demux_001_src4_channel; // cmd_xbar_demux_001:src4_channel -> uart_0_s1_translator_avalon_universal_slave_0_agent:cp_channel + wire cmd_xbar_demux_001_src5_endofpacket; // cmd_xbar_demux_001:src5_endofpacket -> pio_led_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket + wire cmd_xbar_demux_001_src5_valid; // cmd_xbar_demux_001:src5_valid -> pio_led_s1_translator_avalon_universal_slave_0_agent:cp_valid + wire cmd_xbar_demux_001_src5_startofpacket; // cmd_xbar_demux_001:src5_startofpacket -> pio_led_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket + wire [100:0] cmd_xbar_demux_001_src5_data; // cmd_xbar_demux_001:src5_data -> pio_led_s1_translator_avalon_universal_slave_0_agent:cp_data + wire [10:0] cmd_xbar_demux_001_src5_channel; // cmd_xbar_demux_001:src5_channel -> pio_led_s1_translator_avalon_universal_slave_0_agent:cp_channel + wire cmd_xbar_demux_001_src6_endofpacket; // cmd_xbar_demux_001:src6_endofpacket -> pio_key_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket + wire cmd_xbar_demux_001_src6_valid; // cmd_xbar_demux_001:src6_valid -> pio_key_s1_translator_avalon_universal_slave_0_agent:cp_valid + wire cmd_xbar_demux_001_src6_startofpacket; // cmd_xbar_demux_001:src6_startofpacket -> pio_key_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket + wire [100:0] cmd_xbar_demux_001_src6_data; // cmd_xbar_demux_001:src6_data -> pio_key_s1_translator_avalon_universal_slave_0_agent:cp_data + wire [10:0] cmd_xbar_demux_001_src6_channel; // cmd_xbar_demux_001:src6_channel -> pio_key_s1_translator_avalon_universal_slave_0_agent:cp_channel + wire cmd_xbar_demux_001_src7_endofpacket; // cmd_xbar_demux_001:src7_endofpacket -> pio_sw_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket + wire cmd_xbar_demux_001_src7_valid; // cmd_xbar_demux_001:src7_valid -> pio_sw_s1_translator_avalon_universal_slave_0_agent:cp_valid + wire cmd_xbar_demux_001_src7_startofpacket; // cmd_xbar_demux_001:src7_startofpacket -> pio_sw_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket + wire [100:0] cmd_xbar_demux_001_src7_data; // cmd_xbar_demux_001:src7_data -> pio_sw_s1_translator_avalon_universal_slave_0_agent:cp_data + wire [10:0] cmd_xbar_demux_001_src7_channel; // cmd_xbar_demux_001:src7_channel -> pio_sw_s1_translator_avalon_universal_slave_0_agent:cp_channel + wire cmd_xbar_demux_001_src8_endofpacket; // cmd_xbar_demux_001:src8_endofpacket -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket + wire cmd_xbar_demux_001_src8_valid; // cmd_xbar_demux_001:src8_valid -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_valid + wire cmd_xbar_demux_001_src8_startofpacket; // cmd_xbar_demux_001:src8_startofpacket -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket + wire [100:0] cmd_xbar_demux_001_src8_data; // cmd_xbar_demux_001:src8_data -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_data + wire [10:0] cmd_xbar_demux_001_src8_channel; // cmd_xbar_demux_001:src8_channel -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_channel + wire cmd_xbar_demux_001_src9_endofpacket; // cmd_xbar_demux_001:src9_endofpacket -> pio_motor_rst_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket + wire cmd_xbar_demux_001_src9_valid; // cmd_xbar_demux_001:src9_valid -> pio_motor_rst_s1_translator_avalon_universal_slave_0_agent:cp_valid + wire cmd_xbar_demux_001_src9_startofpacket; // cmd_xbar_demux_001:src9_startofpacket -> pio_motor_rst_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket + wire [100:0] cmd_xbar_demux_001_src9_data; // cmd_xbar_demux_001:src9_data -> pio_motor_rst_s1_translator_avalon_universal_slave_0_agent:cp_data + wire [10:0] cmd_xbar_demux_001_src9_channel; // cmd_xbar_demux_001:src9_channel -> pio_motor_rst_s1_translator_avalon_universal_slave_0_agent:cp_channel + wire cmd_xbar_demux_001_src10_endofpacket; // cmd_xbar_demux_001:src10_endofpacket -> rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket + wire cmd_xbar_demux_001_src10_valid; // cmd_xbar_demux_001:src10_valid -> rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:cp_valid + wire cmd_xbar_demux_001_src10_startofpacket; // cmd_xbar_demux_001:src10_startofpacket -> rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket + wire [100:0] cmd_xbar_demux_001_src10_data; // cmd_xbar_demux_001:src10_data -> rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:cp_data + wire [10:0] cmd_xbar_demux_001_src10_channel; // cmd_xbar_demux_001:src10_channel -> rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:cp_channel + wire rsp_xbar_demux_src0_endofpacket; // rsp_xbar_demux:src0_endofpacket -> rsp_xbar_mux:sink0_endofpacket + wire rsp_xbar_demux_src0_valid; // rsp_xbar_demux:src0_valid -> rsp_xbar_mux:sink0_valid + wire rsp_xbar_demux_src0_startofpacket; // rsp_xbar_demux:src0_startofpacket -> rsp_xbar_mux:sink0_startofpacket + wire [100:0] rsp_xbar_demux_src0_data; // rsp_xbar_demux:src0_data -> rsp_xbar_mux:sink0_data + wire [10:0] rsp_xbar_demux_src0_channel; // rsp_xbar_demux:src0_channel -> rsp_xbar_mux:sink0_channel + wire rsp_xbar_demux_src0_ready; // rsp_xbar_mux:sink0_ready -> rsp_xbar_demux:src0_ready + wire rsp_xbar_demux_src1_endofpacket; // rsp_xbar_demux:src1_endofpacket -> rsp_xbar_mux_001:sink0_endofpacket + wire rsp_xbar_demux_src1_valid; // rsp_xbar_demux:src1_valid -> rsp_xbar_mux_001:sink0_valid + wire rsp_xbar_demux_src1_startofpacket; // rsp_xbar_demux:src1_startofpacket -> rsp_xbar_mux_001:sink0_startofpacket + wire [100:0] rsp_xbar_demux_src1_data; // rsp_xbar_demux:src1_data -> rsp_xbar_mux_001:sink0_data + wire [10:0] rsp_xbar_demux_src1_channel; // rsp_xbar_demux:src1_channel -> rsp_xbar_mux_001:sink0_channel + wire rsp_xbar_demux_src1_ready; // rsp_xbar_mux_001:sink0_ready -> rsp_xbar_demux:src1_ready + wire rsp_xbar_demux_001_src0_endofpacket; // rsp_xbar_demux_001:src0_endofpacket -> rsp_xbar_mux:sink1_endofpacket + wire rsp_xbar_demux_001_src0_valid; // rsp_xbar_demux_001:src0_valid -> rsp_xbar_mux:sink1_valid + wire rsp_xbar_demux_001_src0_startofpacket; // rsp_xbar_demux_001:src0_startofpacket -> rsp_xbar_mux:sink1_startofpacket + wire [100:0] rsp_xbar_demux_001_src0_data; // rsp_xbar_demux_001:src0_data -> rsp_xbar_mux:sink1_data + wire [10:0] rsp_xbar_demux_001_src0_channel; // rsp_xbar_demux_001:src0_channel -> rsp_xbar_mux:sink1_channel + wire rsp_xbar_demux_001_src0_ready; // rsp_xbar_mux:sink1_ready -> rsp_xbar_demux_001:src0_ready + wire rsp_xbar_demux_001_src1_endofpacket; // rsp_xbar_demux_001:src1_endofpacket -> rsp_xbar_mux_001:sink1_endofpacket + wire rsp_xbar_demux_001_src1_valid; // rsp_xbar_demux_001:src1_valid -> rsp_xbar_mux_001:sink1_valid + wire rsp_xbar_demux_001_src1_startofpacket; // rsp_xbar_demux_001:src1_startofpacket -> rsp_xbar_mux_001:sink1_startofpacket + wire [100:0] rsp_xbar_demux_001_src1_data; // rsp_xbar_demux_001:src1_data -> rsp_xbar_mux_001:sink1_data + wire [10:0] rsp_xbar_demux_001_src1_channel; // rsp_xbar_demux_001:src1_channel -> rsp_xbar_mux_001:sink1_channel + wire rsp_xbar_demux_001_src1_ready; // rsp_xbar_mux_001:sink1_ready -> rsp_xbar_demux_001:src1_ready + wire rsp_xbar_demux_002_src0_endofpacket; // rsp_xbar_demux_002:src0_endofpacket -> rsp_xbar_mux_001:sink2_endofpacket + wire rsp_xbar_demux_002_src0_valid; // rsp_xbar_demux_002:src0_valid -> rsp_xbar_mux_001:sink2_valid + wire rsp_xbar_demux_002_src0_startofpacket; // rsp_xbar_demux_002:src0_startofpacket -> rsp_xbar_mux_001:sink2_startofpacket + wire [100:0] rsp_xbar_demux_002_src0_data; // rsp_xbar_demux_002:src0_data -> rsp_xbar_mux_001:sink2_data + wire [10:0] rsp_xbar_demux_002_src0_channel; // rsp_xbar_demux_002:src0_channel -> rsp_xbar_mux_001:sink2_channel + wire rsp_xbar_demux_002_src0_ready; // rsp_xbar_mux_001:sink2_ready -> rsp_xbar_demux_002:src0_ready + wire rsp_xbar_demux_003_src0_endofpacket; // rsp_xbar_demux_003:src0_endofpacket -> rsp_xbar_mux_001:sink3_endofpacket + wire rsp_xbar_demux_003_src0_valid; // rsp_xbar_demux_003:src0_valid -> rsp_xbar_mux_001:sink3_valid + wire rsp_xbar_demux_003_src0_startofpacket; // rsp_xbar_demux_003:src0_startofpacket -> rsp_xbar_mux_001:sink3_startofpacket + wire [100:0] rsp_xbar_demux_003_src0_data; // rsp_xbar_demux_003:src0_data -> rsp_xbar_mux_001:sink3_data + wire [10:0] rsp_xbar_demux_003_src0_channel; // rsp_xbar_demux_003:src0_channel -> rsp_xbar_mux_001:sink3_channel + wire rsp_xbar_demux_003_src0_ready; // rsp_xbar_mux_001:sink3_ready -> rsp_xbar_demux_003:src0_ready + wire rsp_xbar_demux_004_src0_endofpacket; // rsp_xbar_demux_004:src0_endofpacket -> rsp_xbar_mux_001:sink4_endofpacket + wire rsp_xbar_demux_004_src0_valid; // rsp_xbar_demux_004:src0_valid -> rsp_xbar_mux_001:sink4_valid + wire rsp_xbar_demux_004_src0_startofpacket; // rsp_xbar_demux_004:src0_startofpacket -> rsp_xbar_mux_001:sink4_startofpacket + wire [100:0] rsp_xbar_demux_004_src0_data; // rsp_xbar_demux_004:src0_data -> rsp_xbar_mux_001:sink4_data + wire [10:0] rsp_xbar_demux_004_src0_channel; // rsp_xbar_demux_004:src0_channel -> rsp_xbar_mux_001:sink4_channel + wire rsp_xbar_demux_004_src0_ready; // rsp_xbar_mux_001:sink4_ready -> rsp_xbar_demux_004:src0_ready + wire rsp_xbar_demux_005_src0_endofpacket; // rsp_xbar_demux_005:src0_endofpacket -> rsp_xbar_mux_001:sink5_endofpacket + wire rsp_xbar_demux_005_src0_valid; // rsp_xbar_demux_005:src0_valid -> rsp_xbar_mux_001:sink5_valid + wire rsp_xbar_demux_005_src0_startofpacket; // rsp_xbar_demux_005:src0_startofpacket -> rsp_xbar_mux_001:sink5_startofpacket + wire [100:0] rsp_xbar_demux_005_src0_data; // rsp_xbar_demux_005:src0_data -> rsp_xbar_mux_001:sink5_data + wire [10:0] rsp_xbar_demux_005_src0_channel; // rsp_xbar_demux_005:src0_channel -> rsp_xbar_mux_001:sink5_channel + wire rsp_xbar_demux_005_src0_ready; // rsp_xbar_mux_001:sink5_ready -> rsp_xbar_demux_005:src0_ready + wire rsp_xbar_demux_006_src0_endofpacket; // rsp_xbar_demux_006:src0_endofpacket -> rsp_xbar_mux_001:sink6_endofpacket + wire rsp_xbar_demux_006_src0_valid; // rsp_xbar_demux_006:src0_valid -> rsp_xbar_mux_001:sink6_valid + wire rsp_xbar_demux_006_src0_startofpacket; // rsp_xbar_demux_006:src0_startofpacket -> rsp_xbar_mux_001:sink6_startofpacket + wire [100:0] rsp_xbar_demux_006_src0_data; // rsp_xbar_demux_006:src0_data -> rsp_xbar_mux_001:sink6_data + wire [10:0] rsp_xbar_demux_006_src0_channel; // rsp_xbar_demux_006:src0_channel -> rsp_xbar_mux_001:sink6_channel + wire rsp_xbar_demux_006_src0_ready; // rsp_xbar_mux_001:sink6_ready -> rsp_xbar_demux_006:src0_ready + wire rsp_xbar_demux_007_src0_endofpacket; // rsp_xbar_demux_007:src0_endofpacket -> rsp_xbar_mux_001:sink7_endofpacket + wire rsp_xbar_demux_007_src0_valid; // rsp_xbar_demux_007:src0_valid -> rsp_xbar_mux_001:sink7_valid + wire rsp_xbar_demux_007_src0_startofpacket; // rsp_xbar_demux_007:src0_startofpacket -> rsp_xbar_mux_001:sink7_startofpacket + wire [100:0] rsp_xbar_demux_007_src0_data; // rsp_xbar_demux_007:src0_data -> rsp_xbar_mux_001:sink7_data + wire [10:0] rsp_xbar_demux_007_src0_channel; // rsp_xbar_demux_007:src0_channel -> rsp_xbar_mux_001:sink7_channel + wire rsp_xbar_demux_007_src0_ready; // rsp_xbar_mux_001:sink7_ready -> rsp_xbar_demux_007:src0_ready + wire rsp_xbar_demux_008_src0_endofpacket; // rsp_xbar_demux_008:src0_endofpacket -> rsp_xbar_mux_001:sink8_endofpacket + wire rsp_xbar_demux_008_src0_valid; // rsp_xbar_demux_008:src0_valid -> rsp_xbar_mux_001:sink8_valid + wire rsp_xbar_demux_008_src0_startofpacket; // rsp_xbar_demux_008:src0_startofpacket -> rsp_xbar_mux_001:sink8_startofpacket + wire [100:0] rsp_xbar_demux_008_src0_data; // rsp_xbar_demux_008:src0_data -> rsp_xbar_mux_001:sink8_data + wire [10:0] rsp_xbar_demux_008_src0_channel; // rsp_xbar_demux_008:src0_channel -> rsp_xbar_mux_001:sink8_channel + wire rsp_xbar_demux_008_src0_ready; // rsp_xbar_mux_001:sink8_ready -> rsp_xbar_demux_008:src0_ready + wire rsp_xbar_demux_009_src0_endofpacket; // rsp_xbar_demux_009:src0_endofpacket -> rsp_xbar_mux_001:sink9_endofpacket + wire rsp_xbar_demux_009_src0_valid; // rsp_xbar_demux_009:src0_valid -> rsp_xbar_mux_001:sink9_valid + wire rsp_xbar_demux_009_src0_startofpacket; // rsp_xbar_demux_009:src0_startofpacket -> rsp_xbar_mux_001:sink9_startofpacket + wire [100:0] rsp_xbar_demux_009_src0_data; // rsp_xbar_demux_009:src0_data -> rsp_xbar_mux_001:sink9_data + wire [10:0] rsp_xbar_demux_009_src0_channel; // rsp_xbar_demux_009:src0_channel -> rsp_xbar_mux_001:sink9_channel + wire rsp_xbar_demux_009_src0_ready; // rsp_xbar_mux_001:sink9_ready -> rsp_xbar_demux_009:src0_ready + wire rsp_xbar_demux_010_src0_endofpacket; // rsp_xbar_demux_010:src0_endofpacket -> rsp_xbar_mux_001:sink10_endofpacket + wire rsp_xbar_demux_010_src0_valid; // rsp_xbar_demux_010:src0_valid -> rsp_xbar_mux_001:sink10_valid + wire rsp_xbar_demux_010_src0_startofpacket; // rsp_xbar_demux_010:src0_startofpacket -> rsp_xbar_mux_001:sink10_startofpacket + wire [100:0] rsp_xbar_demux_010_src0_data; // rsp_xbar_demux_010:src0_data -> rsp_xbar_mux_001:sink10_data + wire [10:0] rsp_xbar_demux_010_src0_channel; // rsp_xbar_demux_010:src0_channel -> rsp_xbar_mux_001:sink10_channel + wire rsp_xbar_demux_010_src0_ready; // rsp_xbar_mux_001:sink10_ready -> rsp_xbar_demux_010:src0_ready + wire limiter_cmd_src_endofpacket; // limiter:cmd_src_endofpacket -> cmd_xbar_demux:sink_endofpacket + wire limiter_cmd_src_startofpacket; // limiter:cmd_src_startofpacket -> cmd_xbar_demux:sink_startofpacket + wire [100:0] limiter_cmd_src_data; // limiter:cmd_src_data -> cmd_xbar_demux:sink_data + wire [10:0] limiter_cmd_src_channel; // limiter:cmd_src_channel -> cmd_xbar_demux:sink_channel + wire limiter_cmd_src_ready; // cmd_xbar_demux:sink_ready -> limiter:cmd_src_ready + wire rsp_xbar_mux_src_endofpacket; // rsp_xbar_mux:src_endofpacket -> limiter:rsp_sink_endofpacket + wire rsp_xbar_mux_src_valid; // rsp_xbar_mux:src_valid -> limiter:rsp_sink_valid + wire rsp_xbar_mux_src_startofpacket; // rsp_xbar_mux:src_startofpacket -> limiter:rsp_sink_startofpacket + wire [100:0] rsp_xbar_mux_src_data; // rsp_xbar_mux:src_data -> limiter:rsp_sink_data + wire [10:0] rsp_xbar_mux_src_channel; // rsp_xbar_mux:src_channel -> limiter:rsp_sink_channel + wire rsp_xbar_mux_src_ready; // limiter:rsp_sink_ready -> rsp_xbar_mux:src_ready + wire limiter_001_cmd_src_endofpacket; // limiter_001:cmd_src_endofpacket -> cmd_xbar_demux_001:sink_endofpacket + wire limiter_001_cmd_src_startofpacket; // limiter_001:cmd_src_startofpacket -> cmd_xbar_demux_001:sink_startofpacket + wire [100:0] limiter_001_cmd_src_data; // limiter_001:cmd_src_data -> cmd_xbar_demux_001:sink_data + wire [10:0] limiter_001_cmd_src_channel; // limiter_001:cmd_src_channel -> cmd_xbar_demux_001:sink_channel + wire limiter_001_cmd_src_ready; // cmd_xbar_demux_001:sink_ready -> limiter_001:cmd_src_ready + wire rsp_xbar_mux_001_src_endofpacket; // rsp_xbar_mux_001:src_endofpacket -> limiter_001:rsp_sink_endofpacket + wire rsp_xbar_mux_001_src_valid; // rsp_xbar_mux_001:src_valid -> limiter_001:rsp_sink_valid + wire rsp_xbar_mux_001_src_startofpacket; // rsp_xbar_mux_001:src_startofpacket -> limiter_001:rsp_sink_startofpacket + wire [100:0] rsp_xbar_mux_001_src_data; // rsp_xbar_mux_001:src_data -> limiter_001:rsp_sink_data + wire [10:0] rsp_xbar_mux_001_src_channel; // rsp_xbar_mux_001:src_channel -> limiter_001:rsp_sink_channel + wire rsp_xbar_mux_001_src_ready; // limiter_001:rsp_sink_ready -> rsp_xbar_mux_001:src_ready + wire cmd_xbar_mux_src_endofpacket; // cmd_xbar_mux:src_endofpacket -> cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_endofpacket + wire cmd_xbar_mux_src_valid; // cmd_xbar_mux:src_valid -> cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_valid + wire cmd_xbar_mux_src_startofpacket; // cmd_xbar_mux:src_startofpacket -> cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_startofpacket + wire [100:0] cmd_xbar_mux_src_data; // cmd_xbar_mux:src_data -> cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_data + wire [10:0] cmd_xbar_mux_src_channel; // cmd_xbar_mux:src_channel -> cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_channel + wire cmd_xbar_mux_src_ready; // cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_mux:src_ready + wire id_router_src_endofpacket; // id_router:src_endofpacket -> rsp_xbar_demux:sink_endofpacket + wire id_router_src_valid; // id_router:src_valid -> rsp_xbar_demux:sink_valid + wire id_router_src_startofpacket; // id_router:src_startofpacket -> rsp_xbar_demux:sink_startofpacket + wire [100:0] id_router_src_data; // id_router:src_data -> rsp_xbar_demux:sink_data + wire [10:0] id_router_src_channel; // id_router:src_channel -> rsp_xbar_demux:sink_channel + wire id_router_src_ready; // rsp_xbar_demux:sink_ready -> id_router:src_ready + wire cmd_xbar_demux_001_src2_ready; // sysid_control_slave_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src2_ready + wire id_router_002_src_endofpacket; // id_router_002:src_endofpacket -> rsp_xbar_demux_002:sink_endofpacket + wire id_router_002_src_valid; // id_router_002:src_valid -> rsp_xbar_demux_002:sink_valid + wire id_router_002_src_startofpacket; // id_router_002:src_startofpacket -> rsp_xbar_demux_002:sink_startofpacket + wire [100:0] id_router_002_src_data; // id_router_002:src_data -> rsp_xbar_demux_002:sink_data + wire [10:0] id_router_002_src_channel; // id_router_002:src_channel -> rsp_xbar_demux_002:sink_channel + wire id_router_002_src_ready; // rsp_xbar_demux_002:sink_ready -> id_router_002:src_ready + wire cmd_xbar_demux_001_src3_ready; // sys_clk_timer_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src3_ready + wire id_router_003_src_endofpacket; // id_router_003:src_endofpacket -> rsp_xbar_demux_003:sink_endofpacket + wire id_router_003_src_valid; // id_router_003:src_valid -> rsp_xbar_demux_003:sink_valid + wire id_router_003_src_startofpacket; // id_router_003:src_startofpacket -> rsp_xbar_demux_003:sink_startofpacket + wire [100:0] id_router_003_src_data; // id_router_003:src_data -> rsp_xbar_demux_003:sink_data + wire [10:0] id_router_003_src_channel; // id_router_003:src_channel -> rsp_xbar_demux_003:sink_channel + wire id_router_003_src_ready; // rsp_xbar_demux_003:sink_ready -> id_router_003:src_ready + wire cmd_xbar_demux_001_src4_ready; // uart_0_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src4_ready + wire id_router_004_src_endofpacket; // id_router_004:src_endofpacket -> rsp_xbar_demux_004:sink_endofpacket + wire id_router_004_src_valid; // id_router_004:src_valid -> rsp_xbar_demux_004:sink_valid + wire id_router_004_src_startofpacket; // id_router_004:src_startofpacket -> rsp_xbar_demux_004:sink_startofpacket + wire [100:0] id_router_004_src_data; // id_router_004:src_data -> rsp_xbar_demux_004:sink_data + wire [10:0] id_router_004_src_channel; // id_router_004:src_channel -> rsp_xbar_demux_004:sink_channel + wire id_router_004_src_ready; // rsp_xbar_demux_004:sink_ready -> id_router_004:src_ready + wire cmd_xbar_demux_001_src5_ready; // pio_led_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src5_ready + wire id_router_005_src_endofpacket; // id_router_005:src_endofpacket -> rsp_xbar_demux_005:sink_endofpacket + wire id_router_005_src_valid; // id_router_005:src_valid -> rsp_xbar_demux_005:sink_valid + wire id_router_005_src_startofpacket; // id_router_005:src_startofpacket -> rsp_xbar_demux_005:sink_startofpacket + wire [100:0] id_router_005_src_data; // id_router_005:src_data -> rsp_xbar_demux_005:sink_data + wire [10:0] id_router_005_src_channel; // id_router_005:src_channel -> rsp_xbar_demux_005:sink_channel + wire id_router_005_src_ready; // rsp_xbar_demux_005:sink_ready -> id_router_005:src_ready + wire cmd_xbar_demux_001_src6_ready; // pio_key_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src6_ready + wire id_router_006_src_endofpacket; // id_router_006:src_endofpacket -> rsp_xbar_demux_006:sink_endofpacket + wire id_router_006_src_valid; // id_router_006:src_valid -> rsp_xbar_demux_006:sink_valid + wire id_router_006_src_startofpacket; // id_router_006:src_startofpacket -> rsp_xbar_demux_006:sink_startofpacket + wire [100:0] id_router_006_src_data; // id_router_006:src_data -> rsp_xbar_demux_006:sink_data + wire [10:0] id_router_006_src_channel; // id_router_006:src_channel -> rsp_xbar_demux_006:sink_channel + wire id_router_006_src_ready; // rsp_xbar_demux_006:sink_ready -> id_router_006:src_ready + wire cmd_xbar_demux_001_src7_ready; // pio_sw_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src7_ready + wire id_router_007_src_endofpacket; // id_router_007:src_endofpacket -> rsp_xbar_demux_007:sink_endofpacket + wire id_router_007_src_valid; // id_router_007:src_valid -> rsp_xbar_demux_007:sink_valid + wire id_router_007_src_startofpacket; // id_router_007:src_startofpacket -> rsp_xbar_demux_007:sink_startofpacket + wire [100:0] id_router_007_src_data; // id_router_007:src_data -> rsp_xbar_demux_007:sink_data + wire [10:0] id_router_007_src_channel; // id_router_007:src_channel -> rsp_xbar_demux_007:sink_channel + wire id_router_007_src_ready; // rsp_xbar_demux_007:sink_ready -> id_router_007:src_ready + wire cmd_xbar_demux_001_src8_ready; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src8_ready + wire id_router_008_src_endofpacket; // id_router_008:src_endofpacket -> rsp_xbar_demux_008:sink_endofpacket + wire id_router_008_src_valid; // id_router_008:src_valid -> rsp_xbar_demux_008:sink_valid + wire id_router_008_src_startofpacket; // id_router_008:src_startofpacket -> rsp_xbar_demux_008:sink_startofpacket + wire [100:0] id_router_008_src_data; // id_router_008:src_data -> rsp_xbar_demux_008:sink_data + wire [10:0] id_router_008_src_channel; // id_router_008:src_channel -> rsp_xbar_demux_008:sink_channel + wire id_router_008_src_ready; // rsp_xbar_demux_008:sink_ready -> id_router_008:src_ready + wire cmd_xbar_demux_001_src9_ready; // pio_motor_rst_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src9_ready + wire id_router_009_src_endofpacket; // id_router_009:src_endofpacket -> rsp_xbar_demux_009:sink_endofpacket + wire id_router_009_src_valid; // id_router_009:src_valid -> rsp_xbar_demux_009:sink_valid + wire id_router_009_src_startofpacket; // id_router_009:src_startofpacket -> rsp_xbar_demux_009:sink_startofpacket + wire [100:0] id_router_009_src_data; // id_router_009:src_data -> rsp_xbar_demux_009:sink_data + wire [10:0] id_router_009_src_channel; // id_router_009:src_channel -> rsp_xbar_demux_009:sink_channel + wire id_router_009_src_ready; // rsp_xbar_demux_009:sink_ready -> id_router_009:src_ready + wire cmd_xbar_demux_001_src10_ready; // rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src10_ready + wire id_router_010_src_endofpacket; // id_router_010:src_endofpacket -> rsp_xbar_demux_010:sink_endofpacket + wire id_router_010_src_valid; // id_router_010:src_valid -> rsp_xbar_demux_010:sink_valid + wire id_router_010_src_startofpacket; // id_router_010:src_startofpacket -> rsp_xbar_demux_010:sink_startofpacket + wire [100:0] id_router_010_src_data; // id_router_010:src_data -> rsp_xbar_demux_010:sink_data + wire [10:0] id_router_010_src_channel; // id_router_010:src_channel -> rsp_xbar_demux_010:sink_channel + wire id_router_010_src_ready; // rsp_xbar_demux_010:sink_ready -> id_router_010:src_ready + wire cmd_xbar_mux_001_src_endofpacket; // cmd_xbar_mux_001:src_endofpacket -> width_adapter:in_endofpacket + wire cmd_xbar_mux_001_src_valid; // cmd_xbar_mux_001:src_valid -> width_adapter:in_valid + wire cmd_xbar_mux_001_src_startofpacket; // cmd_xbar_mux_001:src_startofpacket -> width_adapter:in_startofpacket + wire [100:0] cmd_xbar_mux_001_src_data; // cmd_xbar_mux_001:src_data -> width_adapter:in_data + wire [10:0] cmd_xbar_mux_001_src_channel; // cmd_xbar_mux_001:src_channel -> width_adapter:in_channel + wire cmd_xbar_mux_001_src_ready; // width_adapter:in_ready -> cmd_xbar_mux_001:src_ready + wire width_adapter_src_endofpacket; // width_adapter:out_endofpacket -> burst_adapter:sink0_endofpacket + wire width_adapter_src_valid; // width_adapter:out_valid -> burst_adapter:sink0_valid + wire width_adapter_src_startofpacket; // width_adapter:out_startofpacket -> burst_adapter:sink0_startofpacket + wire [82:0] width_adapter_src_data; // width_adapter:out_data -> burst_adapter:sink0_data + wire width_adapter_src_ready; // burst_adapter:sink0_ready -> width_adapter:out_ready + wire [10:0] width_adapter_src_channel; // width_adapter:out_channel -> burst_adapter:sink0_channel + wire id_router_001_src_endofpacket; // id_router_001:src_endofpacket -> width_adapter_001:in_endofpacket + wire id_router_001_src_valid; // id_router_001:src_valid -> width_adapter_001:in_valid + wire id_router_001_src_startofpacket; // id_router_001:src_startofpacket -> width_adapter_001:in_startofpacket + wire [82:0] id_router_001_src_data; // id_router_001:src_data -> width_adapter_001:in_data + wire [10:0] id_router_001_src_channel; // id_router_001:src_channel -> width_adapter_001:in_channel + wire id_router_001_src_ready; // width_adapter_001:in_ready -> id_router_001:src_ready + wire width_adapter_001_src_endofpacket; // width_adapter_001:out_endofpacket -> rsp_xbar_demux_001:sink_endofpacket + wire width_adapter_001_src_valid; // width_adapter_001:out_valid -> rsp_xbar_demux_001:sink_valid + wire width_adapter_001_src_startofpacket; // width_adapter_001:out_startofpacket -> rsp_xbar_demux_001:sink_startofpacket + wire [100:0] width_adapter_001_src_data; // width_adapter_001:out_data -> rsp_xbar_demux_001:sink_data + wire width_adapter_001_src_ready; // rsp_xbar_demux_001:sink_ready -> width_adapter_001:out_ready + wire [10:0] width_adapter_001_src_channel; // width_adapter_001:out_channel -> rsp_xbar_demux_001:sink_channel + wire [10:0] limiter_cmd_valid_data; // limiter:cmd_src_valid -> cmd_xbar_demux:sink_valid + wire [10:0] limiter_001_cmd_valid_data; // limiter_001:cmd_src_valid -> cmd_xbar_demux_001:sink_valid + wire irq_mapper_receiver0_irq; // sys_clk_timer:irq -> irq_mapper:receiver0_irq + wire irq_mapper_receiver1_irq; // uart_0:irq -> irq_mapper:receiver1_irq + wire irq_mapper_receiver2_irq; // jtag_uart_0:av_irq -> irq_mapper:receiver2_irq + wire irq_mapper_receiver3_irq; // rs232_motor:irq -> irq_mapper:receiver3_irq + wire [31:0] cpu_d_irq_irq; // irq_mapper:sender_irq -> cpu:d_irq + + system_cpu cpu ( + .clk (clk_clk), // clk.clk + .reset_n (~rst_controller_reset_out_reset), // reset_n.reset_n + .d_address (cpu_data_master_address), // data_master.address + .d_byteenable (cpu_data_master_byteenable), // .byteenable + .d_read (cpu_data_master_read), // .read + .d_readdata (cpu_data_master_readdata), // .readdata + .d_waitrequest (cpu_data_master_waitrequest), // .waitrequest + .d_write (cpu_data_master_write), // .write + .d_writedata (cpu_data_master_writedata), // .writedata + .d_readdatavalid (cpu_data_master_readdatavalid), // .readdatavalid + .jtag_debug_module_debugaccess_to_roms (cpu_data_master_debugaccess), // .debugaccess + .i_address (cpu_instruction_master_address), // instruction_master.address + .i_read (cpu_instruction_master_read), // .read + .i_readdata (cpu_instruction_master_readdata), // .readdata + .i_waitrequest (cpu_instruction_master_waitrequest), // .waitrequest + .i_readdatavalid (cpu_instruction_master_readdatavalid), // .readdatavalid + .d_irq (cpu_d_irq_irq), // d_irq.irq + .jtag_debug_module_resetrequest (cpu_jtag_debug_module_reset_reset), // jtag_debug_module_reset.reset + .jtag_debug_module_address (cpu_jtag_debug_module_translator_avalon_anti_slave_0_address), // jtag_debug_module.address + .jtag_debug_module_begintransfer (cpu_jtag_debug_module_translator_avalon_anti_slave_0_begintransfer), // .begintransfer + .jtag_debug_module_byteenable (cpu_jtag_debug_module_translator_avalon_anti_slave_0_byteenable), // .byteenable + .jtag_debug_module_debugaccess (cpu_jtag_debug_module_translator_avalon_anti_slave_0_debugaccess), // .debugaccess + .jtag_debug_module_readdata (cpu_jtag_debug_module_translator_avalon_anti_slave_0_readdata), // .readdata + .jtag_debug_module_select (cpu_jtag_debug_module_translator_avalon_anti_slave_0_chipselect), // .chipselect + .jtag_debug_module_write (cpu_jtag_debug_module_translator_avalon_anti_slave_0_write), // .write + .jtag_debug_module_writedata (cpu_jtag_debug_module_translator_avalon_anti_slave_0_writedata), // .writedata + .no_ci_readra () // custom_instruction_master.readra + ); + + system_sysid sysid ( + .clock (clk_clk), // clk.clk + .reset_n (~rst_controller_reset_out_reset), // reset.reset_n + .readdata (sysid_control_slave_translator_avalon_anti_slave_0_readdata), // control_slave.readdata + .address (sysid_control_slave_translator_avalon_anti_slave_0_address) // .address + ); + + system_sdram sdram ( + .clk (clk_clk), // clk.clk + .reset_n (~rst_controller_reset_out_reset), // reset.reset_n + .az_addr (sdram_s1_translator_avalon_anti_slave_0_address), // s1.address + .az_be_n (~sdram_s1_translator_avalon_anti_slave_0_byteenable), // .byteenable_n + .az_cs (sdram_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect + .az_data (sdram_s1_translator_avalon_anti_slave_0_writedata), // .writedata + .az_rd_n (~sdram_s1_translator_avalon_anti_slave_0_read), // .read_n + .az_wr_n (~sdram_s1_translator_avalon_anti_slave_0_write), // .write_n + .za_data (sdram_s1_translator_avalon_anti_slave_0_readdata), // .readdata + .za_valid (sdram_s1_translator_avalon_anti_slave_0_readdatavalid), // .readdatavalid + .za_waitrequest (sdram_s1_translator_avalon_anti_slave_0_waitrequest), // .waitrequest + .zs_addr (sdram_addr), // wire.export + .zs_ba (sdram_ba), // .export + .zs_cas_n (sdram_cas_n), // .export + .zs_cke (sdram_cke), // .export + .zs_cs_n (sdram_cs_n), // .export + .zs_dq (sdram_dq), // .export + .zs_dqm (sdram_dqm), // .export + .zs_ras_n (sdram_ras_n), // .export + .zs_we_n (sdram_we_n) // .export + ); + + system_sys_clk_timer sys_clk_timer ( + .clk (clk_clk), // clk.clk + .reset_n (~rst_controller_reset_out_reset), // reset.reset_n + .address (sys_clk_timer_s1_translator_avalon_anti_slave_0_address), // s1.address + .writedata (sys_clk_timer_s1_translator_avalon_anti_slave_0_writedata), // .writedata + .readdata (sys_clk_timer_s1_translator_avalon_anti_slave_0_readdata), // .readdata + .chipselect (sys_clk_timer_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect + .write_n (~sys_clk_timer_s1_translator_avalon_anti_slave_0_write), // .write_n + .irq (irq_mapper_receiver0_irq) // irq.irq + ); + + system_uart_0 uart_0 ( + .clk (clk_clk), // clk.clk + .reset_n (~rst_controller_reset_out_reset), // reset.reset_n + .address (uart_0_s1_translator_avalon_anti_slave_0_address), // s1.address + .begintransfer (uart_0_s1_translator_avalon_anti_slave_0_begintransfer), // .begintransfer + .chipselect (uart_0_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect + .read_n (~uart_0_s1_translator_avalon_anti_slave_0_read), // .read_n + .write_n (~uart_0_s1_translator_avalon_anti_slave_0_write), // .write_n + .writedata (uart_0_s1_translator_avalon_anti_slave_0_writedata), // .writedata + .readdata (uart_0_s1_translator_avalon_anti_slave_0_readdata), // .readdata + .dataavailable (), // .dataavailable + .readyfordata (), // .readyfordata + .rxd (uart_0_rxd), // external_connection.export + .txd (uart_0_txd), // .export + .irq (irq_mapper_receiver1_irq) // irq.irq + ); + + system_pio_led pio_led ( + .clk (clk_clk), // clk.clk + .reset_n (~rst_controller_reset_out_reset), // reset.reset_n + .address (pio_led_s1_translator_avalon_anti_slave_0_address), // s1.address + .write_n (~pio_led_s1_translator_avalon_anti_slave_0_write), // .write_n + .writedata (pio_led_s1_translator_avalon_anti_slave_0_writedata), // .writedata + .chipselect (pio_led_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect + .readdata (pio_led_s1_translator_avalon_anti_slave_0_readdata), // .readdata + .out_port (pio_led_export) // external_connection.export + ); + + system_pio_key pio_key ( + .clk (clk_clk), // clk.clk + .reset_n (~rst_controller_reset_out_reset), // reset.reset_n + .address (pio_key_s1_translator_avalon_anti_slave_0_address), // s1.address + .readdata (pio_key_s1_translator_avalon_anti_slave_0_readdata), // .readdata + .in_port (pio_key_export) // external_connection.export + ); + + system_pio_sw pio_sw ( + .clk (clk_clk), // clk.clk + .reset_n (~rst_controller_reset_out_reset), // reset.reset_n + .address (pio_sw_s1_translator_avalon_anti_slave_0_address), // s1.address + .readdata (pio_sw_s1_translator_avalon_anti_slave_0_readdata), // .readdata + .in_port (pio_sw_export) // external_connection.export + ); + + system_jtag_uart_0 jtag_uart_0 ( + .clk (clk_clk), // clk.clk + .rst_n (~rst_controller_reset_out_reset), // reset.reset_n + .av_chipselect (jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_chipselect), // avalon_jtag_slave.chipselect + .av_address (jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_address), // .address + .av_read_n (~jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_read), // .read_n + .av_readdata (jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_readdata), // .readdata + .av_write_n (~jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_write), // .write_n + .av_writedata (jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_writedata), // .writedata + .av_waitrequest (jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_waitrequest), // .waitrequest + .av_irq (irq_mapper_receiver2_irq) // irq.irq + ); + + system_pio_motor_rst pio_motor_rst ( + .clk (clk_clk), // clk.clk + .reset_n (~rst_controller_reset_out_reset), // reset.reset_n + .address (pio_motor_rst_s1_translator_avalon_anti_slave_0_address), // s1.address + .write_n (~pio_motor_rst_s1_translator_avalon_anti_slave_0_write), // .write_n + .writedata (pio_motor_rst_s1_translator_avalon_anti_slave_0_writedata), // .writedata + .chipselect (pio_motor_rst_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect + .readdata (pio_motor_rst_s1_translator_avalon_anti_slave_0_readdata), // .readdata + .out_port (pio_motor_rst_export) // external_connection.export + ); + + system_rs232_motor rs232_motor ( + .clk (clk_clk), // clock_reset.clk + .reset (rst_controller_reset_out_reset), // clock_reset_reset.reset + .address (rs232_motor_avalon_rs232_slave_translator_avalon_anti_slave_0_address), // avalon_rs232_slave.address + .chipselect (rs232_motor_avalon_rs232_slave_translator_avalon_anti_slave_0_chipselect), // .chipselect + .byteenable (rs232_motor_avalon_rs232_slave_translator_avalon_anti_slave_0_byteenable), // .byteenable + .read (rs232_motor_avalon_rs232_slave_translator_avalon_anti_slave_0_read), // .read + .write (rs232_motor_avalon_rs232_slave_translator_avalon_anti_slave_0_write), // .write + .writedata (rs232_motor_avalon_rs232_slave_translator_avalon_anti_slave_0_writedata), // .writedata + .readdata (rs232_motor_avalon_rs232_slave_translator_avalon_anti_slave_0_readdata), // .readdata + .irq (irq_mapper_receiver3_irq), // interrupt.irq + .UART_RXD (rs232_motor_RXD), // external_interface.export + .UART_TXD (rs232_motor_TXD) // .export + ); + + altera_merlin_master_translator #( + .AV_ADDRESS_W (26), + .AV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (26), + .UAV_BURSTCOUNT_W (3), + .USE_READ (1), + .USE_WRITE (0), + .USE_BEGINBURSTTRANSFER (0), + .USE_BEGINTRANSFER (0), + .USE_CHIPSELECT (0), + .USE_BURSTCOUNT (0), + .USE_READDATAVALID (1), + .USE_WAITREQUEST (1), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (1), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_LINEWRAPBURSTS (1), + .AV_REGISTERINCOMINGSIGNALS (0) + ) cpu_instruction_master_translator ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // reset.reset + .uav_address (cpu_instruction_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address + .uav_burstcount (cpu_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount + .uav_read (cpu_instruction_master_translator_avalon_universal_master_0_read), // .read + .uav_write (cpu_instruction_master_translator_avalon_universal_master_0_write), // .write + .uav_waitrequest (cpu_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest + .uav_readdatavalid (cpu_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid + .uav_byteenable (cpu_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable + .uav_readdata (cpu_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata + .uav_writedata (cpu_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata + .uav_lock (cpu_instruction_master_translator_avalon_universal_master_0_lock), // .lock + .uav_debugaccess (cpu_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess + .av_address (cpu_instruction_master_address), // avalon_anti_master_0.address + .av_waitrequest (cpu_instruction_master_waitrequest), // .waitrequest + .av_read (cpu_instruction_master_read), // .read + .av_readdata (cpu_instruction_master_readdata), // .readdata + .av_readdatavalid (cpu_instruction_master_readdatavalid), // .readdatavalid + .av_burstcount (1'b1), // (terminated) + .av_byteenable (4'b1111), // (terminated) + .av_beginbursttransfer (1'b0), // (terminated) + .av_begintransfer (1'b0), // (terminated) + .av_chipselect (1'b0), // (terminated) + .av_write (1'b0), // (terminated) + .av_writedata (32'b00000000000000000000000000000000), // (terminated) + .av_lock (1'b0), // (terminated) + .av_debugaccess (1'b0), // (terminated) + .uav_clken (), // (terminated) + .av_clken (1'b1) // (terminated) + ); + + altera_merlin_master_translator #( + .AV_ADDRESS_W (26), + .AV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (26), + .UAV_BURSTCOUNT_W (3), + .USE_READ (1), + .USE_WRITE (1), + .USE_BEGINBURSTTRANSFER (0), + .USE_BEGINTRANSFER (0), + .USE_CHIPSELECT (0), + .USE_BURSTCOUNT (0), + .USE_READDATAVALID (1), + .USE_WAITREQUEST (1), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (1), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_LINEWRAPBURSTS (0), + .AV_REGISTERINCOMINGSIGNALS (0) + ) cpu_data_master_translator ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // reset.reset + .uav_address (cpu_data_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address + .uav_burstcount (cpu_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount + .uav_read (cpu_data_master_translator_avalon_universal_master_0_read), // .read + .uav_write (cpu_data_master_translator_avalon_universal_master_0_write), // .write + .uav_waitrequest (cpu_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest + .uav_readdatavalid (cpu_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid + .uav_byteenable (cpu_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable + .uav_readdata (cpu_data_master_translator_avalon_universal_master_0_readdata), // .readdata + .uav_writedata (cpu_data_master_translator_avalon_universal_master_0_writedata), // .writedata + .uav_lock (cpu_data_master_translator_avalon_universal_master_0_lock), // .lock + .uav_debugaccess (cpu_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess + .av_address (cpu_data_master_address), // avalon_anti_master_0.address + .av_waitrequest (cpu_data_master_waitrequest), // .waitrequest + .av_byteenable (cpu_data_master_byteenable), // .byteenable + .av_read (cpu_data_master_read), // .read + .av_readdata (cpu_data_master_readdata), // .readdata + .av_readdatavalid (cpu_data_master_readdatavalid), // .readdatavalid + .av_write (cpu_data_master_write), // .write + .av_writedata (cpu_data_master_writedata), // .writedata + .av_debugaccess (cpu_data_master_debugaccess), // .debugaccess + .av_burstcount (1'b1), // (terminated) + .av_beginbursttransfer (1'b0), // (terminated) + .av_begintransfer (1'b0), // (terminated) + .av_chipselect (1'b0), // (terminated) + .av_lock (1'b0), // (terminated) + .uav_clken (), // (terminated) + .av_clken (1'b1) // (terminated) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (9), + .AV_DATA_W (32), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (4), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (26), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (0), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (0), + .USE_UAV_CLKEN (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (1), + .AV_WRITE_WAIT_CYCLES (0), + .AV_SETUP_WAIT_CYCLES (0), + .AV_DATA_HOLD_CYCLES (0) + ) cpu_jtag_debug_module_translator ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // reset.reset + .uav_address (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address + .uav_burstcount (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .uav_read (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_read), // .read + .uav_write (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_write), // .write + .uav_waitrequest (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .uav_readdatavalid (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .uav_byteenable (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .uav_readdata (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .uav_writedata (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .uav_lock (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .uav_debugaccess (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .av_address (cpu_jtag_debug_module_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address + .av_write (cpu_jtag_debug_module_translator_avalon_anti_slave_0_write), // .write + .av_readdata (cpu_jtag_debug_module_translator_avalon_anti_slave_0_readdata), // .readdata + .av_writedata (cpu_jtag_debug_module_translator_avalon_anti_slave_0_writedata), // .writedata + .av_begintransfer (cpu_jtag_debug_module_translator_avalon_anti_slave_0_begintransfer), // .begintransfer + .av_byteenable (cpu_jtag_debug_module_translator_avalon_anti_slave_0_byteenable), // .byteenable + .av_chipselect (cpu_jtag_debug_module_translator_avalon_anti_slave_0_chipselect), // .chipselect + .av_debugaccess (cpu_jtag_debug_module_translator_avalon_anti_slave_0_debugaccess), // .debugaccess + .av_read (), // (terminated) + .av_beginbursttransfer (), // (terminated) + .av_burstcount (), // (terminated) + .av_readdatavalid (1'b0), // (terminated) + .av_waitrequest (1'b0), // (terminated) + .av_writebyteenable (), // (terminated) + .av_lock (), // (terminated) + .av_clken (), // (terminated) + .uav_clken (1'b0), // (terminated) + .av_outputenable () // (terminated) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (23), + .AV_DATA_W (16), + .UAV_DATA_W (16), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (2), + .UAV_BYTEENABLE_W (2), + .UAV_ADDRESS_W (26), + .UAV_BURSTCOUNT_W (2), + .AV_READLATENCY (0), + .USE_READDATAVALID (1), + .USE_WAITREQUEST (1), + .USE_UAV_CLKEN (0), + .AV_SYMBOLS_PER_WORD (2), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (1), + .AV_WRITE_WAIT_CYCLES (0), + .AV_SETUP_WAIT_CYCLES (0), + .AV_DATA_HOLD_CYCLES (0) + ) sdram_s1_translator ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // reset.reset + .uav_address (sdram_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address + .uav_burstcount (sdram_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .uav_read (sdram_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read + .uav_write (sdram_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write + .uav_waitrequest (sdram_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .uav_readdatavalid (sdram_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .uav_byteenable (sdram_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .uav_readdata (sdram_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .uav_writedata (sdram_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .uav_lock (sdram_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .uav_debugaccess (sdram_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .av_address (sdram_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address + .av_write (sdram_s1_translator_avalon_anti_slave_0_write), // .write + .av_read (sdram_s1_translator_avalon_anti_slave_0_read), // .read + .av_readdata (sdram_s1_translator_avalon_anti_slave_0_readdata), // .readdata + .av_writedata (sdram_s1_translator_avalon_anti_slave_0_writedata), // .writedata + .av_byteenable (sdram_s1_translator_avalon_anti_slave_0_byteenable), // .byteenable + .av_readdatavalid (sdram_s1_translator_avalon_anti_slave_0_readdatavalid), // .readdatavalid + .av_waitrequest (sdram_s1_translator_avalon_anti_slave_0_waitrequest), // .waitrequest + .av_chipselect (sdram_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect + .av_begintransfer (), // (terminated) + .av_beginbursttransfer (), // (terminated) + .av_burstcount (), // (terminated) + .av_writebyteenable (), // (terminated) + .av_lock (), // (terminated) + .av_clken (), // (terminated) + .uav_clken (1'b0), // (terminated) + .av_debugaccess (), // (terminated) + .av_outputenable () // (terminated) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (1), + .AV_DATA_W (32), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (4), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (26), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (0), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (0), + .USE_UAV_CLKEN (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (1), + .AV_WRITE_WAIT_CYCLES (0), + .AV_SETUP_WAIT_CYCLES (0), + .AV_DATA_HOLD_CYCLES (0) + ) sysid_control_slave_translator ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // reset.reset + .uav_address (sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address + .uav_burstcount (sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .uav_read (sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read + .uav_write (sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write + .uav_waitrequest (sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .uav_readdatavalid (sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .uav_byteenable (sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .uav_readdata (sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .uav_writedata (sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .uav_lock (sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .uav_debugaccess (sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .av_address (sysid_control_slave_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address + .av_readdata (sysid_control_slave_translator_avalon_anti_slave_0_readdata), // .readdata + .av_write (), // (terminated) + .av_read (), // (terminated) + .av_writedata (), // (terminated) + .av_begintransfer (), // (terminated) + .av_beginbursttransfer (), // (terminated) + .av_burstcount (), // (terminated) + .av_byteenable (), // (terminated) + .av_readdatavalid (1'b0), // (terminated) + .av_waitrequest (1'b0), // (terminated) + .av_writebyteenable (), // (terminated) + .av_lock (), // (terminated) + .av_chipselect (), // (terminated) + .av_clken (), // (terminated) + .uav_clken (1'b0), // (terminated) + .av_debugaccess (), // (terminated) + .av_outputenable () // (terminated) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (3), + .AV_DATA_W (16), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (1), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (26), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (0), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (0), + .USE_UAV_CLKEN (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (1), + .AV_WRITE_WAIT_CYCLES (0), + .AV_SETUP_WAIT_CYCLES (0), + .AV_DATA_HOLD_CYCLES (0) + ) sys_clk_timer_s1_translator ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // reset.reset + .uav_address (sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address + .uav_burstcount (sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .uav_read (sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read + .uav_write (sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write + .uav_waitrequest (sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .uav_readdatavalid (sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .uav_byteenable (sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .uav_readdata (sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .uav_writedata (sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .uav_lock (sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .uav_debugaccess (sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .av_address (sys_clk_timer_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address + .av_write (sys_clk_timer_s1_translator_avalon_anti_slave_0_write), // .write + .av_readdata (sys_clk_timer_s1_translator_avalon_anti_slave_0_readdata), // .readdata + .av_writedata (sys_clk_timer_s1_translator_avalon_anti_slave_0_writedata), // .writedata + .av_chipselect (sys_clk_timer_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect + .av_read (), // (terminated) + .av_begintransfer (), // (terminated) + .av_beginbursttransfer (), // (terminated) + .av_burstcount (), // (terminated) + .av_byteenable (), // (terminated) + .av_readdatavalid (1'b0), // (terminated) + .av_waitrequest (1'b0), // (terminated) + .av_writebyteenable (), // (terminated) + .av_lock (), // (terminated) + .av_clken (), // (terminated) + .uav_clken (1'b0), // (terminated) + .av_debugaccess (), // (terminated) + .av_outputenable () // (terminated) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (3), + .AV_DATA_W (16), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (1), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (26), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (0), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (0), + .USE_UAV_CLKEN (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (1), + .AV_WRITE_WAIT_CYCLES (1), + .AV_SETUP_WAIT_CYCLES (0), + .AV_DATA_HOLD_CYCLES (0) + ) uart_0_s1_translator ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // reset.reset + .uav_address (uart_0_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address + .uav_burstcount (uart_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .uav_read (uart_0_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read + .uav_write (uart_0_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write + .uav_waitrequest (uart_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .uav_readdatavalid (uart_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .uav_byteenable (uart_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .uav_readdata (uart_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .uav_writedata (uart_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .uav_lock (uart_0_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .uav_debugaccess (uart_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .av_address (uart_0_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address + .av_write (uart_0_s1_translator_avalon_anti_slave_0_write), // .write + .av_read (uart_0_s1_translator_avalon_anti_slave_0_read), // .read + .av_readdata (uart_0_s1_translator_avalon_anti_slave_0_readdata), // .readdata + .av_writedata (uart_0_s1_translator_avalon_anti_slave_0_writedata), // .writedata + .av_begintransfer (uart_0_s1_translator_avalon_anti_slave_0_begintransfer), // .begintransfer + .av_chipselect (uart_0_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect + .av_beginbursttransfer (), // (terminated) + .av_burstcount (), // (terminated) + .av_byteenable (), // (terminated) + .av_readdatavalid (1'b0), // (terminated) + .av_waitrequest (1'b0), // (terminated) + .av_writebyteenable (), // (terminated) + .av_lock (), // (terminated) + .av_clken (), // (terminated) + .uav_clken (1'b0), // (terminated) + .av_debugaccess (), // (terminated) + .av_outputenable () // (terminated) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (3), + .AV_DATA_W (32), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (1), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (26), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (0), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (0), + .USE_UAV_CLKEN (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (1), + .AV_WRITE_WAIT_CYCLES (0), + .AV_SETUP_WAIT_CYCLES (0), + .AV_DATA_HOLD_CYCLES (0) + ) pio_led_s1_translator ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // reset.reset + .uav_address (pio_led_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address + .uav_burstcount (pio_led_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .uav_read (pio_led_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read + .uav_write (pio_led_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write + .uav_waitrequest (pio_led_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .uav_readdatavalid (pio_led_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .uav_byteenable (pio_led_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .uav_readdata (pio_led_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .uav_writedata (pio_led_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .uav_lock (pio_led_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .uav_debugaccess (pio_led_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .av_address (pio_led_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address + .av_write (pio_led_s1_translator_avalon_anti_slave_0_write), // .write + .av_readdata (pio_led_s1_translator_avalon_anti_slave_0_readdata), // .readdata + .av_writedata (pio_led_s1_translator_avalon_anti_slave_0_writedata), // .writedata + .av_chipselect (pio_led_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect + .av_read (), // (terminated) + .av_begintransfer (), // (terminated) + .av_beginbursttransfer (), // (terminated) + .av_burstcount (), // (terminated) + .av_byteenable (), // (terminated) + .av_readdatavalid (1'b0), // (terminated) + .av_waitrequest (1'b0), // (terminated) + .av_writebyteenable (), // (terminated) + .av_lock (), // (terminated) + .av_clken (), // (terminated) + .uav_clken (1'b0), // (terminated) + .av_debugaccess (), // (terminated) + .av_outputenable () // (terminated) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (2), + .AV_DATA_W (32), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (1), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (26), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (0), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (0), + .USE_UAV_CLKEN (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (1), + .AV_WRITE_WAIT_CYCLES (0), + .AV_SETUP_WAIT_CYCLES (0), + .AV_DATA_HOLD_CYCLES (0) + ) pio_key_s1_translator ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // reset.reset + .uav_address (pio_key_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address + .uav_burstcount (pio_key_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .uav_read (pio_key_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read + .uav_write (pio_key_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write + .uav_waitrequest (pio_key_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .uav_readdatavalid (pio_key_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .uav_byteenable (pio_key_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .uav_readdata (pio_key_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .uav_writedata (pio_key_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .uav_lock (pio_key_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .uav_debugaccess (pio_key_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .av_address (pio_key_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address + .av_readdata (pio_key_s1_translator_avalon_anti_slave_0_readdata), // .readdata + .av_write (), // (terminated) + .av_read (), // (terminated) + .av_writedata (), // (terminated) + .av_begintransfer (), // (terminated) + .av_beginbursttransfer (), // (terminated) + .av_burstcount (), // (terminated) + .av_byteenable (), // (terminated) + .av_readdatavalid (1'b0), // (terminated) + .av_waitrequest (1'b0), // (terminated) + .av_writebyteenable (), // (terminated) + .av_lock (), // (terminated) + .av_chipselect (), // (terminated) + .av_clken (), // (terminated) + .uav_clken (1'b0), // (terminated) + .av_debugaccess (), // (terminated) + .av_outputenable () // (terminated) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (2), + .AV_DATA_W (32), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (1), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (26), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (0), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (0), + .USE_UAV_CLKEN (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (1), + .AV_WRITE_WAIT_CYCLES (0), + .AV_SETUP_WAIT_CYCLES (0), + .AV_DATA_HOLD_CYCLES (0) + ) pio_sw_s1_translator ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // reset.reset + .uav_address (pio_sw_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address + .uav_burstcount (pio_sw_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .uav_read (pio_sw_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read + .uav_write (pio_sw_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write + .uav_waitrequest (pio_sw_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .uav_readdatavalid (pio_sw_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .uav_byteenable (pio_sw_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .uav_readdata (pio_sw_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .uav_writedata (pio_sw_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .uav_lock (pio_sw_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .uav_debugaccess (pio_sw_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .av_address (pio_sw_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address + .av_readdata (pio_sw_s1_translator_avalon_anti_slave_0_readdata), // .readdata + .av_write (), // (terminated) + .av_read (), // (terminated) + .av_writedata (), // (terminated) + .av_begintransfer (), // (terminated) + .av_beginbursttransfer (), // (terminated) + .av_burstcount (), // (terminated) + .av_byteenable (), // (terminated) + .av_readdatavalid (1'b0), // (terminated) + .av_waitrequest (1'b0), // (terminated) + .av_writebyteenable (), // (terminated) + .av_lock (), // (terminated) + .av_chipselect (), // (terminated) + .av_clken (), // (terminated) + .uav_clken (1'b0), // (terminated) + .av_debugaccess (), // (terminated) + .av_outputenable () // (terminated) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (1), + .AV_DATA_W (32), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (1), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (26), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (0), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (1), + .USE_UAV_CLKEN (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (1), + .AV_WRITE_WAIT_CYCLES (0), + .AV_SETUP_WAIT_CYCLES (0), + .AV_DATA_HOLD_CYCLES (0) + ) jtag_uart_0_avalon_jtag_slave_translator ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // reset.reset + .uav_address (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address + .uav_burstcount (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .uav_read (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read + .uav_write (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write + .uav_waitrequest (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .uav_readdatavalid (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .uav_byteenable (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .uav_readdata (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .uav_writedata (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .uav_lock (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .uav_debugaccess (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .av_address (jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address + .av_write (jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_write), // .write + .av_read (jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_read), // .read + .av_readdata (jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_readdata), // .readdata + .av_writedata (jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_writedata), // .writedata + .av_waitrequest (jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_waitrequest), // .waitrequest + .av_chipselect (jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_chipselect), // .chipselect + .av_begintransfer (), // (terminated) + .av_beginbursttransfer (), // (terminated) + .av_burstcount (), // (terminated) + .av_byteenable (), // (terminated) + .av_readdatavalid (1'b0), // (terminated) + .av_writebyteenable (), // (terminated) + .av_lock (), // (terminated) + .av_clken (), // (terminated) + .uav_clken (1'b0), // (terminated) + .av_debugaccess (), // (terminated) + .av_outputenable () // (terminated) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (2), + .AV_DATA_W (32), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (1), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (26), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (0), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (0), + .USE_UAV_CLKEN (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (1), + .AV_WRITE_WAIT_CYCLES (0), + .AV_SETUP_WAIT_CYCLES (0), + .AV_DATA_HOLD_CYCLES (0) + ) pio_motor_rst_s1_translator ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // reset.reset + .uav_address (pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address + .uav_burstcount (pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .uav_read (pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read + .uav_write (pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write + .uav_waitrequest (pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .uav_readdatavalid (pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .uav_byteenable (pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .uav_readdata (pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .uav_writedata (pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .uav_lock (pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .uav_debugaccess (pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .av_address (pio_motor_rst_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address + .av_write (pio_motor_rst_s1_translator_avalon_anti_slave_0_write), // .write + .av_readdata (pio_motor_rst_s1_translator_avalon_anti_slave_0_readdata), // .readdata + .av_writedata (pio_motor_rst_s1_translator_avalon_anti_slave_0_writedata), // .writedata + .av_chipselect (pio_motor_rst_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect + .av_read (), // (terminated) + .av_begintransfer (), // (terminated) + .av_beginbursttransfer (), // (terminated) + .av_burstcount (), // (terminated) + .av_byteenable (), // (terminated) + .av_readdatavalid (1'b0), // (terminated) + .av_waitrequest (1'b0), // (terminated) + .av_writebyteenable (), // (terminated) + .av_lock (), // (terminated) + .av_clken (), // (terminated) + .uav_clken (1'b0), // (terminated) + .av_debugaccess (), // (terminated) + .av_outputenable () // (terminated) + ); + + altera_merlin_slave_translator #( + .AV_ADDRESS_W (1), + .AV_DATA_W (32), + .UAV_DATA_W (32), + .AV_BURSTCOUNT_W (1), + .AV_BYTEENABLE_W (4), + .UAV_BYTEENABLE_W (4), + .UAV_ADDRESS_W (26), + .UAV_BURSTCOUNT_W (3), + .AV_READLATENCY (1), + .USE_READDATAVALID (0), + .USE_WAITREQUEST (0), + .USE_UAV_CLKEN (0), + .AV_SYMBOLS_PER_WORD (4), + .AV_ADDRESS_SYMBOLS (0), + .AV_BURSTCOUNT_SYMBOLS (0), + .AV_CONSTANT_BURST_BEHAVIOR (0), + .UAV_CONSTANT_BURST_BEHAVIOR (0), + .AV_REQUIRE_UNALIGNED_ADDRESSES (0), + .CHIPSELECT_THROUGH_READLATENCY (0), + .AV_READ_WAIT_CYCLES (0), + .AV_WRITE_WAIT_CYCLES (0), + .AV_SETUP_WAIT_CYCLES (0), + .AV_DATA_HOLD_CYCLES (0) + ) rs232_motor_avalon_rs232_slave_translator ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // reset.reset + .uav_address (rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address + .uav_burstcount (rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .uav_read (rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read + .uav_write (rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write + .uav_waitrequest (rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .uav_readdatavalid (rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .uav_byteenable (rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .uav_readdata (rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .uav_writedata (rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .uav_lock (rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .uav_debugaccess (rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .av_address (rs232_motor_avalon_rs232_slave_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address + .av_write (rs232_motor_avalon_rs232_slave_translator_avalon_anti_slave_0_write), // .write + .av_read (rs232_motor_avalon_rs232_slave_translator_avalon_anti_slave_0_read), // .read + .av_readdata (rs232_motor_avalon_rs232_slave_translator_avalon_anti_slave_0_readdata), // .readdata + .av_writedata (rs232_motor_avalon_rs232_slave_translator_avalon_anti_slave_0_writedata), // .writedata + .av_byteenable (rs232_motor_avalon_rs232_slave_translator_avalon_anti_slave_0_byteenable), // .byteenable + .av_chipselect (rs232_motor_avalon_rs232_slave_translator_avalon_anti_slave_0_chipselect), // .chipselect + .av_begintransfer (), // (terminated) + .av_beginbursttransfer (), // (terminated) + .av_burstcount (), // (terminated) + .av_readdatavalid (1'b0), // (terminated) + .av_waitrequest (1'b0), // (terminated) + .av_writebyteenable (), // (terminated) + .av_lock (), // (terminated) + .av_clken (), // (terminated) + .uav_clken (1'b0), // (terminated) + .av_debugaccess (), // (terminated) + .av_outputenable () // (terminated) + ); + + altera_merlin_master_agent #( + .PKT_PROTECTION_H (94), + .PKT_PROTECTION_L (92), + .PKT_BEGIN_BURST (81), + .PKT_BURSTWRAP_H (73), + .PKT_BURSTWRAP_L (71), + .PKT_BURST_SIZE_H (76), + .PKT_BURST_SIZE_L (74), + .PKT_BURST_TYPE_H (78), + .PKT_BURST_TYPE_L (77), + .PKT_BYTE_CNT_H (70), + .PKT_BYTE_CNT_L (68), + .PKT_ADDR_H (61), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (62), + .PKT_TRANS_POSTED (63), + .PKT_TRANS_WRITE (64), + .PKT_TRANS_READ (65), + .PKT_TRANS_LOCK (66), + .PKT_TRANS_EXCLUSIVE (67), + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_SRC_ID_H (86), + .PKT_SRC_ID_L (83), + .PKT_DEST_ID_H (90), + .PKT_DEST_ID_L (87), + .PKT_THREAD_ID_H (91), + .PKT_THREAD_ID_L (91), + .PKT_CACHE_H (98), + .PKT_CACHE_L (95), + .PKT_DATA_SIDEBAND_H (80), + .PKT_DATA_SIDEBAND_L (80), + .PKT_QOS_H (82), + .PKT_QOS_L (82), + .PKT_ADDR_SIDEBAND_H (79), + .PKT_ADDR_SIDEBAND_L (79), + .ST_DATA_W (101), + .ST_CHANNEL_W (11), + .AV_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_RSP (0), + .ID (0), + .BURSTWRAP_VALUE (3), + .CACHE_VALUE (4'b0000) + ) cpu_instruction_master_translator_avalon_universal_master_0_agent ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .av_address (cpu_instruction_master_translator_avalon_universal_master_0_address), // av.address + .av_write (cpu_instruction_master_translator_avalon_universal_master_0_write), // .write + .av_read (cpu_instruction_master_translator_avalon_universal_master_0_read), // .read + .av_writedata (cpu_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata + .av_readdata (cpu_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata + .av_waitrequest (cpu_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest + .av_readdatavalid (cpu_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid + .av_byteenable (cpu_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable + .av_burstcount (cpu_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount + .av_debugaccess (cpu_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess + .av_lock (cpu_instruction_master_translator_avalon_universal_master_0_lock), // .lock + .cp_valid (cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_valid), // cp.valid + .cp_data (cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_data), // .data + .cp_startofpacket (cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket + .cp_endofpacket (cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket + .cp_ready (cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_ready), // .ready + .rp_valid (limiter_rsp_src_valid), // rp.valid + .rp_data (limiter_rsp_src_data), // .data + .rp_channel (limiter_rsp_src_channel), // .channel + .rp_startofpacket (limiter_rsp_src_startofpacket), // .startofpacket + .rp_endofpacket (limiter_rsp_src_endofpacket), // .endofpacket + .rp_ready (limiter_rsp_src_ready) // .ready + ); + + altera_merlin_master_agent #( + .PKT_PROTECTION_H (94), + .PKT_PROTECTION_L (92), + .PKT_BEGIN_BURST (81), + .PKT_BURSTWRAP_H (73), + .PKT_BURSTWRAP_L (71), + .PKT_BURST_SIZE_H (76), + .PKT_BURST_SIZE_L (74), + .PKT_BURST_TYPE_H (78), + .PKT_BURST_TYPE_L (77), + .PKT_BYTE_CNT_H (70), + .PKT_BYTE_CNT_L (68), + .PKT_ADDR_H (61), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (62), + .PKT_TRANS_POSTED (63), + .PKT_TRANS_WRITE (64), + .PKT_TRANS_READ (65), + .PKT_TRANS_LOCK (66), + .PKT_TRANS_EXCLUSIVE (67), + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_SRC_ID_H (86), + .PKT_SRC_ID_L (83), + .PKT_DEST_ID_H (90), + .PKT_DEST_ID_L (87), + .PKT_THREAD_ID_H (91), + .PKT_THREAD_ID_L (91), + .PKT_CACHE_H (98), + .PKT_CACHE_L (95), + .PKT_DATA_SIDEBAND_H (80), + .PKT_DATA_SIDEBAND_L (80), + .PKT_QOS_H (82), + .PKT_QOS_L (82), + .PKT_ADDR_SIDEBAND_H (79), + .PKT_ADDR_SIDEBAND_L (79), + .ST_DATA_W (101), + .ST_CHANNEL_W (11), + .AV_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_RSP (0), + .ID (1), + .BURSTWRAP_VALUE (7), + .CACHE_VALUE (4'b0000) + ) cpu_data_master_translator_avalon_universal_master_0_agent ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .av_address (cpu_data_master_translator_avalon_universal_master_0_address), // av.address + .av_write (cpu_data_master_translator_avalon_universal_master_0_write), // .write + .av_read (cpu_data_master_translator_avalon_universal_master_0_read), // .read + .av_writedata (cpu_data_master_translator_avalon_universal_master_0_writedata), // .writedata + .av_readdata (cpu_data_master_translator_avalon_universal_master_0_readdata), // .readdata + .av_waitrequest (cpu_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest + .av_readdatavalid (cpu_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid + .av_byteenable (cpu_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable + .av_burstcount (cpu_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount + .av_debugaccess (cpu_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess + .av_lock (cpu_data_master_translator_avalon_universal_master_0_lock), // .lock + .cp_valid (cpu_data_master_translator_avalon_universal_master_0_agent_cp_valid), // cp.valid + .cp_data (cpu_data_master_translator_avalon_universal_master_0_agent_cp_data), // .data + .cp_startofpacket (cpu_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket + .cp_endofpacket (cpu_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket + .cp_ready (cpu_data_master_translator_avalon_universal_master_0_agent_cp_ready), // .ready + .rp_valid (limiter_001_rsp_src_valid), // rp.valid + .rp_data (limiter_001_rsp_src_data), // .data + .rp_channel (limiter_001_rsp_src_channel), // .channel + .rp_startofpacket (limiter_001_rsp_src_startofpacket), // .startofpacket + .rp_endofpacket (limiter_001_rsp_src_endofpacket), // .endofpacket + .rp_ready (limiter_001_rsp_src_ready) // .ready + ); + + altera_merlin_slave_agent #( + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BEGIN_BURST (81), + .PKT_SYMBOL_W (8), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_ADDR_H (61), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (62), + .PKT_TRANS_POSTED (63), + .PKT_TRANS_WRITE (64), + .PKT_TRANS_READ (65), + .PKT_TRANS_LOCK (66), + .PKT_SRC_ID_H (86), + .PKT_SRC_ID_L (83), + .PKT_DEST_ID_H (90), + .PKT_DEST_ID_L (87), + .PKT_BURSTWRAP_H (73), + .PKT_BURSTWRAP_L (71), + .PKT_BYTE_CNT_H (70), + .PKT_BYTE_CNT_L (68), + .PKT_PROTECTION_H (94), + .PKT_PROTECTION_L (92), + .PKT_RESPONSE_STATUS_H (100), + .PKT_RESPONSE_STATUS_L (99), + .PKT_BURST_SIZE_H (76), + .PKT_BURST_SIZE_L (74), + .ST_CHANNEL_W (11), + .ST_DATA_W (101), + .AVS_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_CMD (0), + .PREVENT_FIFO_OVERFLOW (1) + ) cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .m0_address (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_address), // m0.address + .m0_burstcount (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .m0_byteenable (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .m0_debugaccess (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .m0_lock (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .m0_readdata (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .m0_readdatavalid (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .m0_read (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_read), // .read + .m0_waitrequest (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .m0_writedata (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .m0_write (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_write), // .write + .rp_endofpacket (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket + .rp_ready (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_ready), // .ready + .rp_valid (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .rp_data (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_data), // .data + .rp_startofpacket (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .cp_ready (cmd_xbar_mux_src_ready), // cp.ready + .cp_valid (cmd_xbar_mux_src_valid), // .valid + .cp_data (cmd_xbar_mux_src_data), // .data + .cp_startofpacket (cmd_xbar_mux_src_startofpacket), // .startofpacket + .cp_endofpacket (cmd_xbar_mux_src_endofpacket), // .endofpacket + .cp_channel (cmd_xbar_mux_src_channel), // .channel + .rf_sink_ready (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready + .rf_sink_valid (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .rf_sink_startofpacket (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .rf_sink_endofpacket (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .rf_sink_data (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data + .rf_source_ready (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready + .rf_source_valid (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .rf_source_startofpacket (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .rf_source_endofpacket (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .rf_source_data (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_data), // .data + .rdata_fifo_sink_ready (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready + .rdata_fifo_sink_valid (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_sink_data (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data + .rdata_fifo_src_ready (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready + .rdata_fifo_src_valid (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_src_data (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (102), + .FIFO_DEPTH (2), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) + ) cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .in_data (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data + .in_valid (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .in_ready (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready + .in_startofpacket (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .in_endofpacket (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .out_data (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data + .out_valid (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .out_ready (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready + .out_startofpacket (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .out_endofpacket (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .csr_address (2'b00), // (terminated) + .csr_read (1'b0), // (terminated) + .csr_write (1'b0), // (terminated) + .csr_readdata (), // (terminated) + .csr_writedata (32'b00000000000000000000000000000000), // (terminated) + .almost_full_data (), // (terminated) + .almost_empty_data (), // (terminated) + .in_empty (1'b0), // (terminated) + .out_empty (), // (terminated) + .in_error (1'b0), // (terminated) + .out_error (), // (terminated) + .in_channel (1'b0), // (terminated) + .out_channel () // (terminated) + ); + + altera_merlin_slave_agent #( + .PKT_DATA_H (15), + .PKT_DATA_L (0), + .PKT_BEGIN_BURST (63), + .PKT_SYMBOL_W (8), + .PKT_BYTEEN_H (17), + .PKT_BYTEEN_L (16), + .PKT_ADDR_H (43), + .PKT_ADDR_L (18), + .PKT_TRANS_COMPRESSED_READ (44), + .PKT_TRANS_POSTED (45), + .PKT_TRANS_WRITE (46), + .PKT_TRANS_READ (47), + .PKT_TRANS_LOCK (48), + .PKT_SRC_ID_H (68), + .PKT_SRC_ID_L (65), + .PKT_DEST_ID_H (72), + .PKT_DEST_ID_L (69), + .PKT_BURSTWRAP_H (55), + .PKT_BURSTWRAP_L (53), + .PKT_BYTE_CNT_H (52), + .PKT_BYTE_CNT_L (50), + .PKT_PROTECTION_H (76), + .PKT_PROTECTION_L (74), + .PKT_RESPONSE_STATUS_H (82), + .PKT_RESPONSE_STATUS_L (81), + .PKT_BURST_SIZE_H (58), + .PKT_BURST_SIZE_L (56), + .ST_CHANNEL_W (11), + .ST_DATA_W (83), + .AVS_BURSTCOUNT_W (2), + .SUPPRESS_0_BYTEEN_CMD (1), + .PREVENT_FIFO_OVERFLOW (1) + ) sdram_s1_translator_avalon_universal_slave_0_agent ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .m0_address (sdram_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address + .m0_burstcount (sdram_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .m0_byteenable (sdram_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .m0_debugaccess (sdram_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .m0_lock (sdram_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .m0_readdata (sdram_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .m0_readdatavalid (sdram_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .m0_read (sdram_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read + .m0_waitrequest (sdram_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .m0_writedata (sdram_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .m0_write (sdram_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write + .rp_endofpacket (sdram_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket + .rp_ready (sdram_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready + .rp_valid (sdram_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .rp_data (sdram_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data + .rp_startofpacket (sdram_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .cp_ready (burst_adapter_source0_ready), // cp.ready + .cp_valid (burst_adapter_source0_valid), // .valid + .cp_data (burst_adapter_source0_data), // .data + .cp_startofpacket (burst_adapter_source0_startofpacket), // .startofpacket + .cp_endofpacket (burst_adapter_source0_endofpacket), // .endofpacket + .cp_channel (burst_adapter_source0_channel), // .channel + .rf_sink_ready (sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready + .rf_sink_valid (sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .rf_sink_startofpacket (sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .rf_sink_endofpacket (sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .rf_sink_data (sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data + .rf_source_ready (sdram_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready + .rf_source_valid (sdram_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .rf_source_startofpacket (sdram_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .rf_source_endofpacket (sdram_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .rf_source_data (sdram_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data + .rdata_fifo_sink_ready (sdram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready + .rdata_fifo_sink_valid (sdram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_sink_data (sdram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data + .rdata_fifo_src_ready (sdram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready + .rdata_fifo_src_valid (sdram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_src_data (sdram_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (84), + .FIFO_DEPTH (8), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) + ) sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .in_data (sdram_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data + .in_valid (sdram_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .in_ready (sdram_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready + .in_startofpacket (sdram_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .in_endofpacket (sdram_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .out_data (sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data + .out_valid (sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .out_ready (sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready + .out_startofpacket (sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .out_endofpacket (sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .csr_address (2'b00), // (terminated) + .csr_read (1'b0), // (terminated) + .csr_write (1'b0), // (terminated) + .csr_readdata (), // (terminated) + .csr_writedata (32'b00000000000000000000000000000000), // (terminated) + .almost_full_data (), // (terminated) + .almost_empty_data (), // (terminated) + .in_empty (1'b0), // (terminated) + .out_empty (), // (terminated) + .in_error (1'b0), // (terminated) + .out_error (), // (terminated) + .in_channel (1'b0), // (terminated) + .out_channel () // (terminated) + ); + + altera_merlin_slave_agent #( + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BEGIN_BURST (81), + .PKT_SYMBOL_W (8), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_ADDR_H (61), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (62), + .PKT_TRANS_POSTED (63), + .PKT_TRANS_WRITE (64), + .PKT_TRANS_READ (65), + .PKT_TRANS_LOCK (66), + .PKT_SRC_ID_H (86), + .PKT_SRC_ID_L (83), + .PKT_DEST_ID_H (90), + .PKT_DEST_ID_L (87), + .PKT_BURSTWRAP_H (73), + .PKT_BURSTWRAP_L (71), + .PKT_BYTE_CNT_H (70), + .PKT_BYTE_CNT_L (68), + .PKT_PROTECTION_H (94), + .PKT_PROTECTION_L (92), + .PKT_RESPONSE_STATUS_H (100), + .PKT_RESPONSE_STATUS_L (99), + .PKT_BURST_SIZE_H (76), + .PKT_BURST_SIZE_L (74), + .ST_CHANNEL_W (11), + .ST_DATA_W (101), + .AVS_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_CMD (0), + .PREVENT_FIFO_OVERFLOW (1) + ) sysid_control_slave_translator_avalon_universal_slave_0_agent ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .m0_address (sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_address), // m0.address + .m0_burstcount (sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .m0_byteenable (sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .m0_debugaccess (sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .m0_lock (sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .m0_readdata (sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .m0_readdatavalid (sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .m0_read (sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read + .m0_waitrequest (sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .m0_writedata (sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .m0_write (sysid_control_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write + .rp_endofpacket (sysid_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket + .rp_ready (sysid_control_slave_translator_avalon_universal_slave_0_agent_rp_ready), // .ready + .rp_valid (sysid_control_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .rp_data (sysid_control_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data + .rp_startofpacket (sysid_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .cp_ready (cmd_xbar_demux_001_src2_ready), // cp.ready + .cp_valid (cmd_xbar_demux_001_src2_valid), // .valid + .cp_data (cmd_xbar_demux_001_src2_data), // .data + .cp_startofpacket (cmd_xbar_demux_001_src2_startofpacket), // .startofpacket + .cp_endofpacket (cmd_xbar_demux_001_src2_endofpacket), // .endofpacket + .cp_channel (cmd_xbar_demux_001_src2_channel), // .channel + .rf_sink_ready (sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready + .rf_sink_valid (sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .rf_sink_startofpacket (sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .rf_sink_endofpacket (sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .rf_sink_data (sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data + .rf_source_ready (sysid_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready + .rf_source_valid (sysid_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .rf_source_startofpacket (sysid_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .rf_source_endofpacket (sysid_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .rf_source_data (sysid_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // .data + .rdata_fifo_sink_ready (sysid_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready + .rdata_fifo_sink_valid (sysid_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_sink_data (sysid_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data + .rdata_fifo_src_ready (sysid_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready + .rdata_fifo_src_valid (sysid_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_src_data (sysid_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (102), + .FIFO_DEPTH (2), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) + ) sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .in_data (sysid_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data + .in_valid (sysid_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .in_ready (sysid_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready + .in_startofpacket (sysid_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .in_endofpacket (sysid_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .out_data (sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data + .out_valid (sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .out_ready (sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready + .out_startofpacket (sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .out_endofpacket (sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .csr_address (2'b00), // (terminated) + .csr_read (1'b0), // (terminated) + .csr_write (1'b0), // (terminated) + .csr_readdata (), // (terminated) + .csr_writedata (32'b00000000000000000000000000000000), // (terminated) + .almost_full_data (), // (terminated) + .almost_empty_data (), // (terminated) + .in_empty (1'b0), // (terminated) + .out_empty (), // (terminated) + .in_error (1'b0), // (terminated) + .out_error (), // (terminated) + .in_channel (1'b0), // (terminated) + .out_channel () // (terminated) + ); + + altera_merlin_slave_agent #( + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BEGIN_BURST (81), + .PKT_SYMBOL_W (8), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_ADDR_H (61), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (62), + .PKT_TRANS_POSTED (63), + .PKT_TRANS_WRITE (64), + .PKT_TRANS_READ (65), + .PKT_TRANS_LOCK (66), + .PKT_SRC_ID_H (86), + .PKT_SRC_ID_L (83), + .PKT_DEST_ID_H (90), + .PKT_DEST_ID_L (87), + .PKT_BURSTWRAP_H (73), + .PKT_BURSTWRAP_L (71), + .PKT_BYTE_CNT_H (70), + .PKT_BYTE_CNT_L (68), + .PKT_PROTECTION_H (94), + .PKT_PROTECTION_L (92), + .PKT_RESPONSE_STATUS_H (100), + .PKT_RESPONSE_STATUS_L (99), + .PKT_BURST_SIZE_H (76), + .PKT_BURST_SIZE_L (74), + .ST_CHANNEL_W (11), + .ST_DATA_W (101), + .AVS_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_CMD (0), + .PREVENT_FIFO_OVERFLOW (1) + ) sys_clk_timer_s1_translator_avalon_universal_slave_0_agent ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .m0_address (sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address + .m0_burstcount (sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .m0_byteenable (sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .m0_debugaccess (sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .m0_lock (sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .m0_readdata (sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .m0_readdatavalid (sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .m0_read (sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read + .m0_waitrequest (sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .m0_writedata (sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .m0_write (sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write + .rp_endofpacket (sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket + .rp_ready (sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready + .rp_valid (sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .rp_data (sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data + .rp_startofpacket (sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .cp_ready (cmd_xbar_demux_001_src3_ready), // cp.ready + .cp_valid (cmd_xbar_demux_001_src3_valid), // .valid + .cp_data (cmd_xbar_demux_001_src3_data), // .data + .cp_startofpacket (cmd_xbar_demux_001_src3_startofpacket), // .startofpacket + .cp_endofpacket (cmd_xbar_demux_001_src3_endofpacket), // .endofpacket + .cp_channel (cmd_xbar_demux_001_src3_channel), // .channel + .rf_sink_ready (sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready + .rf_sink_valid (sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .rf_sink_startofpacket (sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .rf_sink_endofpacket (sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .rf_sink_data (sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data + .rf_source_ready (sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready + .rf_source_valid (sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .rf_source_startofpacket (sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .rf_source_endofpacket (sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .rf_source_data (sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data + .rdata_fifo_sink_ready (sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready + .rdata_fifo_sink_valid (sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_sink_data (sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data + .rdata_fifo_src_ready (sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready + .rdata_fifo_src_valid (sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_src_data (sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (102), + .FIFO_DEPTH (2), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) + ) sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .in_data (sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data + .in_valid (sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .in_ready (sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready + .in_startofpacket (sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .in_endofpacket (sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .out_data (sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data + .out_valid (sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .out_ready (sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready + .out_startofpacket (sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .out_endofpacket (sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .csr_address (2'b00), // (terminated) + .csr_read (1'b0), // (terminated) + .csr_write (1'b0), // (terminated) + .csr_readdata (), // (terminated) + .csr_writedata (32'b00000000000000000000000000000000), // (terminated) + .almost_full_data (), // (terminated) + .almost_empty_data (), // (terminated) + .in_empty (1'b0), // (terminated) + .out_empty (), // (terminated) + .in_error (1'b0), // (terminated) + .out_error (), // (terminated) + .in_channel (1'b0), // (terminated) + .out_channel () // (terminated) + ); + + altera_merlin_slave_agent #( + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BEGIN_BURST (81), + .PKT_SYMBOL_W (8), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_ADDR_H (61), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (62), + .PKT_TRANS_POSTED (63), + .PKT_TRANS_WRITE (64), + .PKT_TRANS_READ (65), + .PKT_TRANS_LOCK (66), + .PKT_SRC_ID_H (86), + .PKT_SRC_ID_L (83), + .PKT_DEST_ID_H (90), + .PKT_DEST_ID_L (87), + .PKT_BURSTWRAP_H (73), + .PKT_BURSTWRAP_L (71), + .PKT_BYTE_CNT_H (70), + .PKT_BYTE_CNT_L (68), + .PKT_PROTECTION_H (94), + .PKT_PROTECTION_L (92), + .PKT_RESPONSE_STATUS_H (100), + .PKT_RESPONSE_STATUS_L (99), + .PKT_BURST_SIZE_H (76), + .PKT_BURST_SIZE_L (74), + .ST_CHANNEL_W (11), + .ST_DATA_W (101), + .AVS_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_CMD (0), + .PREVENT_FIFO_OVERFLOW (1) + ) uart_0_s1_translator_avalon_universal_slave_0_agent ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .m0_address (uart_0_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address + .m0_burstcount (uart_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .m0_byteenable (uart_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .m0_debugaccess (uart_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .m0_lock (uart_0_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .m0_readdata (uart_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .m0_readdatavalid (uart_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .m0_read (uart_0_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read + .m0_waitrequest (uart_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .m0_writedata (uart_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .m0_write (uart_0_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write + .rp_endofpacket (uart_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket + .rp_ready (uart_0_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready + .rp_valid (uart_0_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .rp_data (uart_0_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data + .rp_startofpacket (uart_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .cp_ready (cmd_xbar_demux_001_src4_ready), // cp.ready + .cp_valid (cmd_xbar_demux_001_src4_valid), // .valid + .cp_data (cmd_xbar_demux_001_src4_data), // .data + .cp_startofpacket (cmd_xbar_demux_001_src4_startofpacket), // .startofpacket + .cp_endofpacket (cmd_xbar_demux_001_src4_endofpacket), // .endofpacket + .cp_channel (cmd_xbar_demux_001_src4_channel), // .channel + .rf_sink_ready (uart_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready + .rf_sink_valid (uart_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .rf_sink_startofpacket (uart_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .rf_sink_endofpacket (uart_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .rf_sink_data (uart_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data + .rf_source_ready (uart_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready + .rf_source_valid (uart_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .rf_source_startofpacket (uart_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .rf_source_endofpacket (uart_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .rf_source_data (uart_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data + .rdata_fifo_sink_ready (uart_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready + .rdata_fifo_sink_valid (uart_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_sink_data (uart_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data + .rdata_fifo_src_ready (uart_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready + .rdata_fifo_src_valid (uart_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_src_data (uart_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (102), + .FIFO_DEPTH (2), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) + ) uart_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .in_data (uart_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data + .in_valid (uart_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .in_ready (uart_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready + .in_startofpacket (uart_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .in_endofpacket (uart_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .out_data (uart_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data + .out_valid (uart_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .out_ready (uart_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready + .out_startofpacket (uart_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .out_endofpacket (uart_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .csr_address (2'b00), // (terminated) + .csr_read (1'b0), // (terminated) + .csr_write (1'b0), // (terminated) + .csr_readdata (), // (terminated) + .csr_writedata (32'b00000000000000000000000000000000), // (terminated) + .almost_full_data (), // (terminated) + .almost_empty_data (), // (terminated) + .in_empty (1'b0), // (terminated) + .out_empty (), // (terminated) + .in_error (1'b0), // (terminated) + .out_error (), // (terminated) + .in_channel (1'b0), // (terminated) + .out_channel () // (terminated) + ); + + altera_merlin_slave_agent #( + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BEGIN_BURST (81), + .PKT_SYMBOL_W (8), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_ADDR_H (61), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (62), + .PKT_TRANS_POSTED (63), + .PKT_TRANS_WRITE (64), + .PKT_TRANS_READ (65), + .PKT_TRANS_LOCK (66), + .PKT_SRC_ID_H (86), + .PKT_SRC_ID_L (83), + .PKT_DEST_ID_H (90), + .PKT_DEST_ID_L (87), + .PKT_BURSTWRAP_H (73), + .PKT_BURSTWRAP_L (71), + .PKT_BYTE_CNT_H (70), + .PKT_BYTE_CNT_L (68), + .PKT_PROTECTION_H (94), + .PKT_PROTECTION_L (92), + .PKT_RESPONSE_STATUS_H (100), + .PKT_RESPONSE_STATUS_L (99), + .PKT_BURST_SIZE_H (76), + .PKT_BURST_SIZE_L (74), + .ST_CHANNEL_W (11), + .ST_DATA_W (101), + .AVS_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_CMD (0), + .PREVENT_FIFO_OVERFLOW (1) + ) pio_led_s1_translator_avalon_universal_slave_0_agent ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .m0_address (pio_led_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address + .m0_burstcount (pio_led_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .m0_byteenable (pio_led_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .m0_debugaccess (pio_led_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .m0_lock (pio_led_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .m0_readdata (pio_led_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .m0_readdatavalid (pio_led_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .m0_read (pio_led_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read + .m0_waitrequest (pio_led_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .m0_writedata (pio_led_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .m0_write (pio_led_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write + .rp_endofpacket (pio_led_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket + .rp_ready (pio_led_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready + .rp_valid (pio_led_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .rp_data (pio_led_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data + .rp_startofpacket (pio_led_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .cp_ready (cmd_xbar_demux_001_src5_ready), // cp.ready + .cp_valid (cmd_xbar_demux_001_src5_valid), // .valid + .cp_data (cmd_xbar_demux_001_src5_data), // .data + .cp_startofpacket (cmd_xbar_demux_001_src5_startofpacket), // .startofpacket + .cp_endofpacket (cmd_xbar_demux_001_src5_endofpacket), // .endofpacket + .cp_channel (cmd_xbar_demux_001_src5_channel), // .channel + .rf_sink_ready (pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready + .rf_sink_valid (pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .rf_sink_startofpacket (pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .rf_sink_endofpacket (pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .rf_sink_data (pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data + .rf_source_ready (pio_led_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready + .rf_source_valid (pio_led_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .rf_source_startofpacket (pio_led_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .rf_source_endofpacket (pio_led_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .rf_source_data (pio_led_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data + .rdata_fifo_sink_ready (pio_led_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready + .rdata_fifo_sink_valid (pio_led_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_sink_data (pio_led_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data + .rdata_fifo_src_ready (pio_led_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready + .rdata_fifo_src_valid (pio_led_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_src_data (pio_led_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (102), + .FIFO_DEPTH (2), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) + ) pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .in_data (pio_led_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data + .in_valid (pio_led_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .in_ready (pio_led_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready + .in_startofpacket (pio_led_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .in_endofpacket (pio_led_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .out_data (pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data + .out_valid (pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .out_ready (pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready + .out_startofpacket (pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .out_endofpacket (pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .csr_address (2'b00), // (terminated) + .csr_read (1'b0), // (terminated) + .csr_write (1'b0), // (terminated) + .csr_readdata (), // (terminated) + .csr_writedata (32'b00000000000000000000000000000000), // (terminated) + .almost_full_data (), // (terminated) + .almost_empty_data (), // (terminated) + .in_empty (1'b0), // (terminated) + .out_empty (), // (terminated) + .in_error (1'b0), // (terminated) + .out_error (), // (terminated) + .in_channel (1'b0), // (terminated) + .out_channel () // (terminated) + ); + + altera_merlin_slave_agent #( + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BEGIN_BURST (81), + .PKT_SYMBOL_W (8), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_ADDR_H (61), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (62), + .PKT_TRANS_POSTED (63), + .PKT_TRANS_WRITE (64), + .PKT_TRANS_READ (65), + .PKT_TRANS_LOCK (66), + .PKT_SRC_ID_H (86), + .PKT_SRC_ID_L (83), + .PKT_DEST_ID_H (90), + .PKT_DEST_ID_L (87), + .PKT_BURSTWRAP_H (73), + .PKT_BURSTWRAP_L (71), + .PKT_BYTE_CNT_H (70), + .PKT_BYTE_CNT_L (68), + .PKT_PROTECTION_H (94), + .PKT_PROTECTION_L (92), + .PKT_RESPONSE_STATUS_H (100), + .PKT_RESPONSE_STATUS_L (99), + .PKT_BURST_SIZE_H (76), + .PKT_BURST_SIZE_L (74), + .ST_CHANNEL_W (11), + .ST_DATA_W (101), + .AVS_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_CMD (0), + .PREVENT_FIFO_OVERFLOW (1) + ) pio_key_s1_translator_avalon_universal_slave_0_agent ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .m0_address (pio_key_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address + .m0_burstcount (pio_key_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .m0_byteenable (pio_key_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .m0_debugaccess (pio_key_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .m0_lock (pio_key_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .m0_readdata (pio_key_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .m0_readdatavalid (pio_key_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .m0_read (pio_key_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read + .m0_waitrequest (pio_key_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .m0_writedata (pio_key_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .m0_write (pio_key_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write + .rp_endofpacket (pio_key_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket + .rp_ready (pio_key_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready + .rp_valid (pio_key_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .rp_data (pio_key_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data + .rp_startofpacket (pio_key_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .cp_ready (cmd_xbar_demux_001_src6_ready), // cp.ready + .cp_valid (cmd_xbar_demux_001_src6_valid), // .valid + .cp_data (cmd_xbar_demux_001_src6_data), // .data + .cp_startofpacket (cmd_xbar_demux_001_src6_startofpacket), // .startofpacket + .cp_endofpacket (cmd_xbar_demux_001_src6_endofpacket), // .endofpacket + .cp_channel (cmd_xbar_demux_001_src6_channel), // .channel + .rf_sink_ready (pio_key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready + .rf_sink_valid (pio_key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .rf_sink_startofpacket (pio_key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .rf_sink_endofpacket (pio_key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .rf_sink_data (pio_key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data + .rf_source_ready (pio_key_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready + .rf_source_valid (pio_key_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .rf_source_startofpacket (pio_key_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .rf_source_endofpacket (pio_key_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .rf_source_data (pio_key_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data + .rdata_fifo_sink_ready (pio_key_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready + .rdata_fifo_sink_valid (pio_key_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_sink_data (pio_key_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data + .rdata_fifo_src_ready (pio_key_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready + .rdata_fifo_src_valid (pio_key_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_src_data (pio_key_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (102), + .FIFO_DEPTH (2), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) + ) pio_key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .in_data (pio_key_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data + .in_valid (pio_key_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .in_ready (pio_key_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready + .in_startofpacket (pio_key_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .in_endofpacket (pio_key_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .out_data (pio_key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data + .out_valid (pio_key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .out_ready (pio_key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready + .out_startofpacket (pio_key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .out_endofpacket (pio_key_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .csr_address (2'b00), // (terminated) + .csr_read (1'b0), // (terminated) + .csr_write (1'b0), // (terminated) + .csr_readdata (), // (terminated) + .csr_writedata (32'b00000000000000000000000000000000), // (terminated) + .almost_full_data (), // (terminated) + .almost_empty_data (), // (terminated) + .in_empty (1'b0), // (terminated) + .out_empty (), // (terminated) + .in_error (1'b0), // (terminated) + .out_error (), // (terminated) + .in_channel (1'b0), // (terminated) + .out_channel () // (terminated) + ); + + altera_merlin_slave_agent #( + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BEGIN_BURST (81), + .PKT_SYMBOL_W (8), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_ADDR_H (61), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (62), + .PKT_TRANS_POSTED (63), + .PKT_TRANS_WRITE (64), + .PKT_TRANS_READ (65), + .PKT_TRANS_LOCK (66), + .PKT_SRC_ID_H (86), + .PKT_SRC_ID_L (83), + .PKT_DEST_ID_H (90), + .PKT_DEST_ID_L (87), + .PKT_BURSTWRAP_H (73), + .PKT_BURSTWRAP_L (71), + .PKT_BYTE_CNT_H (70), + .PKT_BYTE_CNT_L (68), + .PKT_PROTECTION_H (94), + .PKT_PROTECTION_L (92), + .PKT_RESPONSE_STATUS_H (100), + .PKT_RESPONSE_STATUS_L (99), + .PKT_BURST_SIZE_H (76), + .PKT_BURST_SIZE_L (74), + .ST_CHANNEL_W (11), + .ST_DATA_W (101), + .AVS_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_CMD (0), + .PREVENT_FIFO_OVERFLOW (1) + ) pio_sw_s1_translator_avalon_universal_slave_0_agent ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .m0_address (pio_sw_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address + .m0_burstcount (pio_sw_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .m0_byteenable (pio_sw_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .m0_debugaccess (pio_sw_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .m0_lock (pio_sw_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .m0_readdata (pio_sw_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .m0_readdatavalid (pio_sw_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .m0_read (pio_sw_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read + .m0_waitrequest (pio_sw_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .m0_writedata (pio_sw_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .m0_write (pio_sw_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write + .rp_endofpacket (pio_sw_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket + .rp_ready (pio_sw_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready + .rp_valid (pio_sw_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .rp_data (pio_sw_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data + .rp_startofpacket (pio_sw_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .cp_ready (cmd_xbar_demux_001_src7_ready), // cp.ready + .cp_valid (cmd_xbar_demux_001_src7_valid), // .valid + .cp_data (cmd_xbar_demux_001_src7_data), // .data + .cp_startofpacket (cmd_xbar_demux_001_src7_startofpacket), // .startofpacket + .cp_endofpacket (cmd_xbar_demux_001_src7_endofpacket), // .endofpacket + .cp_channel (cmd_xbar_demux_001_src7_channel), // .channel + .rf_sink_ready (pio_sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready + .rf_sink_valid (pio_sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .rf_sink_startofpacket (pio_sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .rf_sink_endofpacket (pio_sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .rf_sink_data (pio_sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data + .rf_source_ready (pio_sw_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready + .rf_source_valid (pio_sw_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .rf_source_startofpacket (pio_sw_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .rf_source_endofpacket (pio_sw_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .rf_source_data (pio_sw_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data + .rdata_fifo_sink_ready (pio_sw_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready + .rdata_fifo_sink_valid (pio_sw_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_sink_data (pio_sw_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data + .rdata_fifo_src_ready (pio_sw_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready + .rdata_fifo_src_valid (pio_sw_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_src_data (pio_sw_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (102), + .FIFO_DEPTH (2), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) + ) pio_sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .in_data (pio_sw_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data + .in_valid (pio_sw_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .in_ready (pio_sw_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready + .in_startofpacket (pio_sw_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .in_endofpacket (pio_sw_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .out_data (pio_sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data + .out_valid (pio_sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .out_ready (pio_sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready + .out_startofpacket (pio_sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .out_endofpacket (pio_sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .csr_address (2'b00), // (terminated) + .csr_read (1'b0), // (terminated) + .csr_write (1'b0), // (terminated) + .csr_readdata (), // (terminated) + .csr_writedata (32'b00000000000000000000000000000000), // (terminated) + .almost_full_data (), // (terminated) + .almost_empty_data (), // (terminated) + .in_empty (1'b0), // (terminated) + .out_empty (), // (terminated) + .in_error (1'b0), // (terminated) + .out_error (), // (terminated) + .in_channel (1'b0), // (terminated) + .out_channel () // (terminated) + ); + + altera_merlin_slave_agent #( + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BEGIN_BURST (81), + .PKT_SYMBOL_W (8), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_ADDR_H (61), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (62), + .PKT_TRANS_POSTED (63), + .PKT_TRANS_WRITE (64), + .PKT_TRANS_READ (65), + .PKT_TRANS_LOCK (66), + .PKT_SRC_ID_H (86), + .PKT_SRC_ID_L (83), + .PKT_DEST_ID_H (90), + .PKT_DEST_ID_L (87), + .PKT_BURSTWRAP_H (73), + .PKT_BURSTWRAP_L (71), + .PKT_BYTE_CNT_H (70), + .PKT_BYTE_CNT_L (68), + .PKT_PROTECTION_H (94), + .PKT_PROTECTION_L (92), + .PKT_RESPONSE_STATUS_H (100), + .PKT_RESPONSE_STATUS_L (99), + .PKT_BURST_SIZE_H (76), + .PKT_BURST_SIZE_L (74), + .ST_CHANNEL_W (11), + .ST_DATA_W (101), + .AVS_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_CMD (0), + .PREVENT_FIFO_OVERFLOW (1) + ) jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .m0_address (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_address), // m0.address + .m0_burstcount (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .m0_byteenable (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .m0_debugaccess (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .m0_lock (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .m0_readdata (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .m0_readdatavalid (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .m0_read (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read + .m0_waitrequest (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .m0_writedata (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .m0_write (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write + .rp_endofpacket (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket + .rp_ready (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_ready), // .ready + .rp_valid (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .rp_data (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data + .rp_startofpacket (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .cp_ready (cmd_xbar_demux_001_src8_ready), // cp.ready + .cp_valid (cmd_xbar_demux_001_src8_valid), // .valid + .cp_data (cmd_xbar_demux_001_src8_data), // .data + .cp_startofpacket (cmd_xbar_demux_001_src8_startofpacket), // .startofpacket + .cp_endofpacket (cmd_xbar_demux_001_src8_endofpacket), // .endofpacket + .cp_channel (cmd_xbar_demux_001_src8_channel), // .channel + .rf_sink_ready (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready + .rf_sink_valid (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .rf_sink_startofpacket (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .rf_sink_endofpacket (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .rf_sink_data (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data + .rf_source_ready (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready + .rf_source_valid (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .rf_source_startofpacket (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .rf_source_endofpacket (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .rf_source_data (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // .data + .rdata_fifo_sink_ready (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready + .rdata_fifo_sink_valid (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_sink_data (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data + .rdata_fifo_src_ready (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready + .rdata_fifo_src_valid (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_src_data (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (102), + .FIFO_DEPTH (2), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) + ) jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .in_data (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data + .in_valid (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .in_ready (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready + .in_startofpacket (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .in_endofpacket (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .out_data (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data + .out_valid (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .out_ready (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready + .out_startofpacket (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .out_endofpacket (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .csr_address (2'b00), // (terminated) + .csr_read (1'b0), // (terminated) + .csr_write (1'b0), // (terminated) + .csr_readdata (), // (terminated) + .csr_writedata (32'b00000000000000000000000000000000), // (terminated) + .almost_full_data (), // (terminated) + .almost_empty_data (), // (terminated) + .in_empty (1'b0), // (terminated) + .out_empty (), // (terminated) + .in_error (1'b0), // (terminated) + .out_error (), // (terminated) + .in_channel (1'b0), // (terminated) + .out_channel () // (terminated) + ); + + altera_merlin_slave_agent #( + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BEGIN_BURST (81), + .PKT_SYMBOL_W (8), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_ADDR_H (61), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (62), + .PKT_TRANS_POSTED (63), + .PKT_TRANS_WRITE (64), + .PKT_TRANS_READ (65), + .PKT_TRANS_LOCK (66), + .PKT_SRC_ID_H (86), + .PKT_SRC_ID_L (83), + .PKT_DEST_ID_H (90), + .PKT_DEST_ID_L (87), + .PKT_BURSTWRAP_H (73), + .PKT_BURSTWRAP_L (71), + .PKT_BYTE_CNT_H (70), + .PKT_BYTE_CNT_L (68), + .PKT_PROTECTION_H (94), + .PKT_PROTECTION_L (92), + .PKT_RESPONSE_STATUS_H (100), + .PKT_RESPONSE_STATUS_L (99), + .PKT_BURST_SIZE_H (76), + .PKT_BURST_SIZE_L (74), + .ST_CHANNEL_W (11), + .ST_DATA_W (101), + .AVS_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_CMD (0), + .PREVENT_FIFO_OVERFLOW (1) + ) pio_motor_rst_s1_translator_avalon_universal_slave_0_agent ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .m0_address (pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address + .m0_burstcount (pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .m0_byteenable (pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .m0_debugaccess (pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .m0_lock (pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .m0_readdata (pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .m0_readdatavalid (pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .m0_read (pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read + .m0_waitrequest (pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .m0_writedata (pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .m0_write (pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write + .rp_endofpacket (pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket + .rp_ready (pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready + .rp_valid (pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .rp_data (pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data + .rp_startofpacket (pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .cp_ready (cmd_xbar_demux_001_src9_ready), // cp.ready + .cp_valid (cmd_xbar_demux_001_src9_valid), // .valid + .cp_data (cmd_xbar_demux_001_src9_data), // .data + .cp_startofpacket (cmd_xbar_demux_001_src9_startofpacket), // .startofpacket + .cp_endofpacket (cmd_xbar_demux_001_src9_endofpacket), // .endofpacket + .cp_channel (cmd_xbar_demux_001_src9_channel), // .channel + .rf_sink_ready (pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready + .rf_sink_valid (pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .rf_sink_startofpacket (pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .rf_sink_endofpacket (pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .rf_sink_data (pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data + .rf_source_ready (pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready + .rf_source_valid (pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .rf_source_startofpacket (pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .rf_source_endofpacket (pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .rf_source_data (pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data + .rdata_fifo_sink_ready (pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready + .rdata_fifo_sink_valid (pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_sink_data (pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data + .rdata_fifo_src_ready (pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready + .rdata_fifo_src_valid (pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_src_data (pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (102), + .FIFO_DEPTH (2), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) + ) pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .in_data (pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data + .in_valid (pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .in_ready (pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready + .in_startofpacket (pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .in_endofpacket (pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .out_data (pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data + .out_valid (pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .out_ready (pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready + .out_startofpacket (pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .out_endofpacket (pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .csr_address (2'b00), // (terminated) + .csr_read (1'b0), // (terminated) + .csr_write (1'b0), // (terminated) + .csr_readdata (), // (terminated) + .csr_writedata (32'b00000000000000000000000000000000), // (terminated) + .almost_full_data (), // (terminated) + .almost_empty_data (), // (terminated) + .in_empty (1'b0), // (terminated) + .out_empty (), // (terminated) + .in_error (1'b0), // (terminated) + .out_error (), // (terminated) + .in_channel (1'b0), // (terminated) + .out_channel () // (terminated) + ); + + altera_merlin_slave_agent #( + .PKT_DATA_H (31), + .PKT_DATA_L (0), + .PKT_BEGIN_BURST (81), + .PKT_SYMBOL_W (8), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32), + .PKT_ADDR_H (61), + .PKT_ADDR_L (36), + .PKT_TRANS_COMPRESSED_READ (62), + .PKT_TRANS_POSTED (63), + .PKT_TRANS_WRITE (64), + .PKT_TRANS_READ (65), + .PKT_TRANS_LOCK (66), + .PKT_SRC_ID_H (86), + .PKT_SRC_ID_L (83), + .PKT_DEST_ID_H (90), + .PKT_DEST_ID_L (87), + .PKT_BURSTWRAP_H (73), + .PKT_BURSTWRAP_L (71), + .PKT_BYTE_CNT_H (70), + .PKT_BYTE_CNT_L (68), + .PKT_PROTECTION_H (94), + .PKT_PROTECTION_L (92), + .PKT_RESPONSE_STATUS_H (100), + .PKT_RESPONSE_STATUS_L (99), + .PKT_BURST_SIZE_H (76), + .PKT_BURST_SIZE_L (74), + .ST_CHANNEL_W (11), + .ST_DATA_W (101), + .AVS_BURSTCOUNT_W (3), + .SUPPRESS_0_BYTEEN_CMD (0), + .PREVENT_FIFO_OVERFLOW (1) + ) rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .m0_address (rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_address), // m0.address + .m0_burstcount (rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount + .m0_byteenable (rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable + .m0_debugaccess (rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess + .m0_lock (rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock + .m0_readdata (rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata + .m0_readdatavalid (rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid + .m0_read (rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read + .m0_waitrequest (rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest + .m0_writedata (rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata + .m0_write (rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write + .rp_endofpacket (rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket + .rp_ready (rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rp_ready), // .ready + .rp_valid (rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .rp_data (rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data + .rp_startofpacket (rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .cp_ready (cmd_xbar_demux_001_src10_ready), // cp.ready + .cp_valid (cmd_xbar_demux_001_src10_valid), // .valid + .cp_data (cmd_xbar_demux_001_src10_data), // .data + .cp_startofpacket (cmd_xbar_demux_001_src10_startofpacket), // .startofpacket + .cp_endofpacket (cmd_xbar_demux_001_src10_endofpacket), // .endofpacket + .cp_channel (cmd_xbar_demux_001_src10_channel), // .channel + .rf_sink_ready (rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready + .rf_sink_valid (rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .rf_sink_startofpacket (rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .rf_sink_endofpacket (rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .rf_sink_data (rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data + .rf_source_ready (rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready + .rf_source_valid (rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .rf_source_startofpacket (rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .rf_source_endofpacket (rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .rf_source_data (rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // .data + .rdata_fifo_sink_ready (rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready + .rdata_fifo_sink_valid (rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_sink_data (rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data + .rdata_fifo_src_ready (rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready + .rdata_fifo_src_valid (rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid + .rdata_fifo_src_data (rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data) // .data + ); + + altera_avalon_sc_fifo #( + .SYMBOLS_PER_BEAT (1), + .BITS_PER_SYMBOL (102), + .FIFO_DEPTH (2), + .CHANNEL_WIDTH (0), + .ERROR_WIDTH (0), + .USE_PACKETS (1), + .USE_FILL_LEVEL (0), + .EMPTY_LATENCY (1), + .USE_MEMORY_BLOCKS (0), + .USE_STORE_FORWARD (0), + .USE_ALMOST_FULL_IF (0), + .USE_ALMOST_EMPTY_IF (0) + ) rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .in_data (rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data + .in_valid (rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid + .in_ready (rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready + .in_startofpacket (rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket + .in_endofpacket (rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket + .out_data (rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data + .out_valid (rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid + .out_ready (rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready + .out_startofpacket (rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket + .out_endofpacket (rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket + .csr_address (2'b00), // (terminated) + .csr_read (1'b0), // (terminated) + .csr_write (1'b0), // (terminated) + .csr_readdata (), // (terminated) + .csr_writedata (32'b00000000000000000000000000000000), // (terminated) + .almost_full_data (), // (terminated) + .almost_empty_data (), // (terminated) + .in_empty (1'b0), // (terminated) + .out_empty (), // (terminated) + .in_error (1'b0), // (terminated) + .out_error (), // (terminated) + .in_channel (1'b0), // (terminated) + .out_channel () // (terminated) + ); + + system_addr_router addr_router ( + .sink_ready (cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_ready), // sink.ready + .sink_valid (cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_valid), // .valid + .sink_data (cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_data), // .data + .sink_startofpacket (cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket + .sink_endofpacket (cpu_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .src_ready (addr_router_src_ready), // src.ready + .src_valid (addr_router_src_valid), // .valid + .src_data (addr_router_src_data), // .data + .src_channel (addr_router_src_channel), // .channel + .src_startofpacket (addr_router_src_startofpacket), // .startofpacket + .src_endofpacket (addr_router_src_endofpacket) // .endofpacket + ); + + system_addr_router_001 addr_router_001 ( + .sink_ready (cpu_data_master_translator_avalon_universal_master_0_agent_cp_ready), // sink.ready + .sink_valid (cpu_data_master_translator_avalon_universal_master_0_agent_cp_valid), // .valid + .sink_data (cpu_data_master_translator_avalon_universal_master_0_agent_cp_data), // .data + .sink_startofpacket (cpu_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket + .sink_endofpacket (cpu_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .src_ready (addr_router_001_src_ready), // src.ready + .src_valid (addr_router_001_src_valid), // .valid + .src_data (addr_router_001_src_data), // .data + .src_channel (addr_router_001_src_channel), // .channel + .src_startofpacket (addr_router_001_src_startofpacket), // .startofpacket + .src_endofpacket (addr_router_001_src_endofpacket) // .endofpacket + ); + + system_id_router id_router ( + .sink_ready (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready + .sink_valid (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .sink_data (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_data), // .data + .sink_startofpacket (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .sink_endofpacket (cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .src_ready (id_router_src_ready), // src.ready + .src_valid (id_router_src_valid), // .valid + .src_data (id_router_src_data), // .data + .src_channel (id_router_src_channel), // .channel + .src_startofpacket (id_router_src_startofpacket), // .startofpacket + .src_endofpacket (id_router_src_endofpacket) // .endofpacket + ); + + system_id_router_001 id_router_001 ( + .sink_ready (sdram_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready + .sink_valid (sdram_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .sink_data (sdram_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data + .sink_startofpacket (sdram_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .sink_endofpacket (sdram_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .src_ready (id_router_001_src_ready), // src.ready + .src_valid (id_router_001_src_valid), // .valid + .src_data (id_router_001_src_data), // .data + .src_channel (id_router_001_src_channel), // .channel + .src_startofpacket (id_router_001_src_startofpacket), // .startofpacket + .src_endofpacket (id_router_001_src_endofpacket) // .endofpacket + ); + + system_id_router_002 id_router_002 ( + .sink_ready (sysid_control_slave_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready + .sink_valid (sysid_control_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .sink_data (sysid_control_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data + .sink_startofpacket (sysid_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .sink_endofpacket (sysid_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .src_ready (id_router_002_src_ready), // src.ready + .src_valid (id_router_002_src_valid), // .valid + .src_data (id_router_002_src_data), // .data + .src_channel (id_router_002_src_channel), // .channel + .src_startofpacket (id_router_002_src_startofpacket), // .startofpacket + .src_endofpacket (id_router_002_src_endofpacket) // .endofpacket + ); + + system_id_router_002 id_router_003 ( + .sink_ready (sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready + .sink_valid (sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .sink_data (sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data + .sink_startofpacket (sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .sink_endofpacket (sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .src_ready (id_router_003_src_ready), // src.ready + .src_valid (id_router_003_src_valid), // .valid + .src_data (id_router_003_src_data), // .data + .src_channel (id_router_003_src_channel), // .channel + .src_startofpacket (id_router_003_src_startofpacket), // .startofpacket + .src_endofpacket (id_router_003_src_endofpacket) // .endofpacket + ); + + system_id_router_002 id_router_004 ( + .sink_ready (uart_0_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready + .sink_valid (uart_0_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .sink_data (uart_0_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data + .sink_startofpacket (uart_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .sink_endofpacket (uart_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .src_ready (id_router_004_src_ready), // src.ready + .src_valid (id_router_004_src_valid), // .valid + .src_data (id_router_004_src_data), // .data + .src_channel (id_router_004_src_channel), // .channel + .src_startofpacket (id_router_004_src_startofpacket), // .startofpacket + .src_endofpacket (id_router_004_src_endofpacket) // .endofpacket + ); + + system_id_router_002 id_router_005 ( + .sink_ready (pio_led_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready + .sink_valid (pio_led_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .sink_data (pio_led_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data + .sink_startofpacket (pio_led_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .sink_endofpacket (pio_led_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .src_ready (id_router_005_src_ready), // src.ready + .src_valid (id_router_005_src_valid), // .valid + .src_data (id_router_005_src_data), // .data + .src_channel (id_router_005_src_channel), // .channel + .src_startofpacket (id_router_005_src_startofpacket), // .startofpacket + .src_endofpacket (id_router_005_src_endofpacket) // .endofpacket + ); + + system_id_router_002 id_router_006 ( + .sink_ready (pio_key_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready + .sink_valid (pio_key_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .sink_data (pio_key_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data + .sink_startofpacket (pio_key_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .sink_endofpacket (pio_key_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .src_ready (id_router_006_src_ready), // src.ready + .src_valid (id_router_006_src_valid), // .valid + .src_data (id_router_006_src_data), // .data + .src_channel (id_router_006_src_channel), // .channel + .src_startofpacket (id_router_006_src_startofpacket), // .startofpacket + .src_endofpacket (id_router_006_src_endofpacket) // .endofpacket + ); + + system_id_router_002 id_router_007 ( + .sink_ready (pio_sw_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready + .sink_valid (pio_sw_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .sink_data (pio_sw_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data + .sink_startofpacket (pio_sw_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .sink_endofpacket (pio_sw_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .src_ready (id_router_007_src_ready), // src.ready + .src_valid (id_router_007_src_valid), // .valid + .src_data (id_router_007_src_data), // .data + .src_channel (id_router_007_src_channel), // .channel + .src_startofpacket (id_router_007_src_startofpacket), // .startofpacket + .src_endofpacket (id_router_007_src_endofpacket) // .endofpacket + ); + + system_id_router_002 id_router_008 ( + .sink_ready (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready + .sink_valid (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .sink_data (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data + .sink_startofpacket (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .sink_endofpacket (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .src_ready (id_router_008_src_ready), // src.ready + .src_valid (id_router_008_src_valid), // .valid + .src_data (id_router_008_src_data), // .data + .src_channel (id_router_008_src_channel), // .channel + .src_startofpacket (id_router_008_src_startofpacket), // .startofpacket + .src_endofpacket (id_router_008_src_endofpacket) // .endofpacket + ); + + system_id_router_002 id_router_009 ( + .sink_ready (pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready + .sink_valid (pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .sink_data (pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data + .sink_startofpacket (pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .sink_endofpacket (pio_motor_rst_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .src_ready (id_router_009_src_ready), // src.ready + .src_valid (id_router_009_src_valid), // .valid + .src_data (id_router_009_src_data), // .data + .src_channel (id_router_009_src_channel), // .channel + .src_startofpacket (id_router_009_src_startofpacket), // .startofpacket + .src_endofpacket (id_router_009_src_endofpacket) // .endofpacket + ); + + system_id_router_002 id_router_010 ( + .sink_ready (rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready + .sink_valid (rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid + .sink_data (rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data + .sink_startofpacket (rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket + .sink_endofpacket (rs232_motor_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .src_ready (id_router_010_src_ready), // src.ready + .src_valid (id_router_010_src_valid), // .valid + .src_data (id_router_010_src_data), // .data + .src_channel (id_router_010_src_channel), // .channel + .src_startofpacket (id_router_010_src_startofpacket), // .startofpacket + .src_endofpacket (id_router_010_src_endofpacket) // .endofpacket + ); + + altera_merlin_traffic_limiter #( + .PKT_DEST_ID_H (90), + .PKT_DEST_ID_L (87), + .PKT_TRANS_POSTED (63), + .PKT_TRANS_WRITE (64), + .MAX_OUTSTANDING_RESPONSES (9), + .PIPELINED (0), + .ST_DATA_W (101), + .ST_CHANNEL_W (11), + .VALID_WIDTH (11), + .ENFORCE_ORDER (1), + .PREVENT_HAZARDS (0), + .PKT_BYTE_CNT_H (70), + .PKT_BYTE_CNT_L (68), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32) + ) limiter ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .cmd_sink_ready (addr_router_src_ready), // cmd_sink.ready + .cmd_sink_valid (addr_router_src_valid), // .valid + .cmd_sink_data (addr_router_src_data), // .data + .cmd_sink_channel (addr_router_src_channel), // .channel + .cmd_sink_startofpacket (addr_router_src_startofpacket), // .startofpacket + .cmd_sink_endofpacket (addr_router_src_endofpacket), // .endofpacket + .cmd_src_ready (limiter_cmd_src_ready), // cmd_src.ready + .cmd_src_data (limiter_cmd_src_data), // .data + .cmd_src_channel (limiter_cmd_src_channel), // .channel + .cmd_src_startofpacket (limiter_cmd_src_startofpacket), // .startofpacket + .cmd_src_endofpacket (limiter_cmd_src_endofpacket), // .endofpacket + .rsp_sink_ready (rsp_xbar_mux_src_ready), // rsp_sink.ready + .rsp_sink_valid (rsp_xbar_mux_src_valid), // .valid + .rsp_sink_channel (rsp_xbar_mux_src_channel), // .channel + .rsp_sink_data (rsp_xbar_mux_src_data), // .data + .rsp_sink_startofpacket (rsp_xbar_mux_src_startofpacket), // .startofpacket + .rsp_sink_endofpacket (rsp_xbar_mux_src_endofpacket), // .endofpacket + .rsp_src_ready (limiter_rsp_src_ready), // rsp_src.ready + .rsp_src_valid (limiter_rsp_src_valid), // .valid + .rsp_src_data (limiter_rsp_src_data), // .data + .rsp_src_channel (limiter_rsp_src_channel), // .channel + .rsp_src_startofpacket (limiter_rsp_src_startofpacket), // .startofpacket + .rsp_src_endofpacket (limiter_rsp_src_endofpacket), // .endofpacket + .cmd_src_valid (limiter_cmd_valid_data) // cmd_valid.data + ); + + altera_merlin_traffic_limiter #( + .PKT_DEST_ID_H (90), + .PKT_DEST_ID_L (87), + .PKT_TRANS_POSTED (63), + .PKT_TRANS_WRITE (64), + .MAX_OUTSTANDING_RESPONSES (9), + .PIPELINED (0), + .ST_DATA_W (101), + .ST_CHANNEL_W (11), + .VALID_WIDTH (11), + .ENFORCE_ORDER (1), + .PREVENT_HAZARDS (0), + .PKT_BYTE_CNT_H (70), + .PKT_BYTE_CNT_L (68), + .PKT_BYTEEN_H (35), + .PKT_BYTEEN_L (32) + ) limiter_001 ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .cmd_sink_ready (addr_router_001_src_ready), // cmd_sink.ready + .cmd_sink_valid (addr_router_001_src_valid), // .valid + .cmd_sink_data (addr_router_001_src_data), // .data + .cmd_sink_channel (addr_router_001_src_channel), // .channel + .cmd_sink_startofpacket (addr_router_001_src_startofpacket), // .startofpacket + .cmd_sink_endofpacket (addr_router_001_src_endofpacket), // .endofpacket + .cmd_src_ready (limiter_001_cmd_src_ready), // cmd_src.ready + .cmd_src_data (limiter_001_cmd_src_data), // .data + .cmd_src_channel (limiter_001_cmd_src_channel), // .channel + .cmd_src_startofpacket (limiter_001_cmd_src_startofpacket), // .startofpacket + .cmd_src_endofpacket (limiter_001_cmd_src_endofpacket), // .endofpacket + .rsp_sink_ready (rsp_xbar_mux_001_src_ready), // rsp_sink.ready + .rsp_sink_valid (rsp_xbar_mux_001_src_valid), // .valid + .rsp_sink_channel (rsp_xbar_mux_001_src_channel), // .channel + .rsp_sink_data (rsp_xbar_mux_001_src_data), // .data + .rsp_sink_startofpacket (rsp_xbar_mux_001_src_startofpacket), // .startofpacket + .rsp_sink_endofpacket (rsp_xbar_mux_001_src_endofpacket), // .endofpacket + .rsp_src_ready (limiter_001_rsp_src_ready), // rsp_src.ready + .rsp_src_valid (limiter_001_rsp_src_valid), // .valid + .rsp_src_data (limiter_001_rsp_src_data), // .data + .rsp_src_channel (limiter_001_rsp_src_channel), // .channel + .rsp_src_startofpacket (limiter_001_rsp_src_startofpacket), // .startofpacket + .rsp_src_endofpacket (limiter_001_rsp_src_endofpacket), // .endofpacket + .cmd_src_valid (limiter_001_cmd_valid_data) // cmd_valid.data + ); + + altera_merlin_burst_adapter #( + .PKT_ADDR_H (43), + .PKT_ADDR_L (18), + .PKT_BEGIN_BURST (63), + .PKT_BYTE_CNT_H (52), + .PKT_BYTE_CNT_L (50), + .PKT_BYTEEN_H (17), + .PKT_BYTEEN_L (16), + .PKT_BURST_SIZE_H (58), + .PKT_BURST_SIZE_L (56), + .PKT_BURST_TYPE_H (60), + .PKT_BURST_TYPE_L (59), + .PKT_BURSTWRAP_H (55), + .PKT_BURSTWRAP_L (53), + .PKT_TRANS_COMPRESSED_READ (44), + .PKT_TRANS_WRITE (46), + .PKT_TRANS_READ (47), + .OUT_NARROW_SIZE (0), + .IN_NARROW_SIZE (0), + .OUT_FIXED (0), + .OUT_COMPLETE_WRAP (0), + .ST_DATA_W (83), + .ST_CHANNEL_W (11), + .OUT_BYTE_CNT_H (51), + .OUT_BURSTWRAP_H (55), + .COMPRESSED_READ_SUPPORT (0), + .BYTEENABLE_SYNTHESIS (0), + .PIPE_INPUTS (0), + .NO_WRAP_SUPPORT (0), + .BURSTWRAP_CONST_MASK (3), + .BURSTWRAP_CONST_VALUE (3) + ) burst_adapter ( + .clk (clk_clk), // cr0.clk + .reset (rst_controller_reset_out_reset), // cr0_reset.reset + .sink0_valid (width_adapter_src_valid), // sink0.valid + .sink0_data (width_adapter_src_data), // .data + .sink0_channel (width_adapter_src_channel), // .channel + .sink0_startofpacket (width_adapter_src_startofpacket), // .startofpacket + .sink0_endofpacket (width_adapter_src_endofpacket), // .endofpacket + .sink0_ready (width_adapter_src_ready), // .ready + .source0_valid (burst_adapter_source0_valid), // source0.valid + .source0_data (burst_adapter_source0_data), // .data + .source0_channel (burst_adapter_source0_channel), // .channel + .source0_startofpacket (burst_adapter_source0_startofpacket), // .startofpacket + .source0_endofpacket (burst_adapter_source0_endofpacket), // .endofpacket + .source0_ready (burst_adapter_source0_ready) // .ready + ); + + altera_reset_controller #( + .NUM_RESET_INPUTS (2), + .OUTPUT_RESET_SYNC_EDGES ("deassert"), + .SYNC_DEPTH (2) + ) rst_controller ( + .reset_in0 (~reset_reset_n), // reset_in0.reset + .reset_in1 (cpu_jtag_debug_module_reset_reset), // reset_in1.reset + .clk (clk_clk), // clk.clk + .reset_out (rst_controller_reset_out_reset), // reset_out.reset + .reset_in2 (1'b0), // (terminated) + .reset_in3 (1'b0), // (terminated) + .reset_in4 (1'b0), // (terminated) + .reset_in5 (1'b0), // (terminated) + .reset_in6 (1'b0), // (terminated) + .reset_in7 (1'b0), // (terminated) + .reset_in8 (1'b0), // (terminated) + .reset_in9 (1'b0), // (terminated) + .reset_in10 (1'b0), // (terminated) + .reset_in11 (1'b0), // (terminated) + .reset_in12 (1'b0), // (terminated) + .reset_in13 (1'b0), // (terminated) + .reset_in14 (1'b0), // (terminated) + .reset_in15 (1'b0) // (terminated) + ); + + system_cmd_xbar_demux cmd_xbar_demux ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .sink_ready (limiter_cmd_src_ready), // sink.ready + .sink_channel (limiter_cmd_src_channel), // .channel + .sink_data (limiter_cmd_src_data), // .data + .sink_startofpacket (limiter_cmd_src_startofpacket), // .startofpacket + .sink_endofpacket (limiter_cmd_src_endofpacket), // .endofpacket + .sink_valid (limiter_cmd_valid_data), // sink_valid.data + .src0_ready (cmd_xbar_demux_src0_ready), // src0.ready + .src0_valid (cmd_xbar_demux_src0_valid), // .valid + .src0_data (cmd_xbar_demux_src0_data), // .data + .src0_channel (cmd_xbar_demux_src0_channel), // .channel + .src0_startofpacket (cmd_xbar_demux_src0_startofpacket), // .startofpacket + .src0_endofpacket (cmd_xbar_demux_src0_endofpacket), // .endofpacket + .src1_ready (cmd_xbar_demux_src1_ready), // src1.ready + .src1_valid (cmd_xbar_demux_src1_valid), // .valid + .src1_data (cmd_xbar_demux_src1_data), // .data + .src1_channel (cmd_xbar_demux_src1_channel), // .channel + .src1_startofpacket (cmd_xbar_demux_src1_startofpacket), // .startofpacket + .src1_endofpacket (cmd_xbar_demux_src1_endofpacket) // .endofpacket + ); + + system_cmd_xbar_demux_001 cmd_xbar_demux_001 ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .sink_ready (limiter_001_cmd_src_ready), // sink.ready + .sink_channel (limiter_001_cmd_src_channel), // .channel + .sink_data (limiter_001_cmd_src_data), // .data + .sink_startofpacket (limiter_001_cmd_src_startofpacket), // .startofpacket + .sink_endofpacket (limiter_001_cmd_src_endofpacket), // .endofpacket + .sink_valid (limiter_001_cmd_valid_data), // sink_valid.data + .src0_ready (cmd_xbar_demux_001_src0_ready), // src0.ready + .src0_valid (cmd_xbar_demux_001_src0_valid), // .valid + .src0_data (cmd_xbar_demux_001_src0_data), // .data + .src0_channel (cmd_xbar_demux_001_src0_channel), // .channel + .src0_startofpacket (cmd_xbar_demux_001_src0_startofpacket), // .startofpacket + .src0_endofpacket (cmd_xbar_demux_001_src0_endofpacket), // .endofpacket + .src1_ready (cmd_xbar_demux_001_src1_ready), // src1.ready + .src1_valid (cmd_xbar_demux_001_src1_valid), // .valid + .src1_data (cmd_xbar_demux_001_src1_data), // .data + .src1_channel (cmd_xbar_demux_001_src1_channel), // .channel + .src1_startofpacket (cmd_xbar_demux_001_src1_startofpacket), // .startofpacket + .src1_endofpacket (cmd_xbar_demux_001_src1_endofpacket), // .endofpacket + .src2_ready (cmd_xbar_demux_001_src2_ready), // src2.ready + .src2_valid (cmd_xbar_demux_001_src2_valid), // .valid + .src2_data (cmd_xbar_demux_001_src2_data), // .data + .src2_channel (cmd_xbar_demux_001_src2_channel), // .channel + .src2_startofpacket (cmd_xbar_demux_001_src2_startofpacket), // .startofpacket + .src2_endofpacket (cmd_xbar_demux_001_src2_endofpacket), // .endofpacket + .src3_ready (cmd_xbar_demux_001_src3_ready), // src3.ready + .src3_valid (cmd_xbar_demux_001_src3_valid), // .valid + .src3_data (cmd_xbar_demux_001_src3_data), // .data + .src3_channel (cmd_xbar_demux_001_src3_channel), // .channel + .src3_startofpacket (cmd_xbar_demux_001_src3_startofpacket), // .startofpacket + .src3_endofpacket (cmd_xbar_demux_001_src3_endofpacket), // .endofpacket + .src4_ready (cmd_xbar_demux_001_src4_ready), // src4.ready + .src4_valid (cmd_xbar_demux_001_src4_valid), // .valid + .src4_data (cmd_xbar_demux_001_src4_data), // .data + .src4_channel (cmd_xbar_demux_001_src4_channel), // .channel + .src4_startofpacket (cmd_xbar_demux_001_src4_startofpacket), // .startofpacket + .src4_endofpacket (cmd_xbar_demux_001_src4_endofpacket), // .endofpacket + .src5_ready (cmd_xbar_demux_001_src5_ready), // src5.ready + .src5_valid (cmd_xbar_demux_001_src5_valid), // .valid + .src5_data (cmd_xbar_demux_001_src5_data), // .data + .src5_channel (cmd_xbar_demux_001_src5_channel), // .channel + .src5_startofpacket (cmd_xbar_demux_001_src5_startofpacket), // .startofpacket + .src5_endofpacket (cmd_xbar_demux_001_src5_endofpacket), // .endofpacket + .src6_ready (cmd_xbar_demux_001_src6_ready), // src6.ready + .src6_valid (cmd_xbar_demux_001_src6_valid), // .valid + .src6_data (cmd_xbar_demux_001_src6_data), // .data + .src6_channel (cmd_xbar_demux_001_src6_channel), // .channel + .src6_startofpacket (cmd_xbar_demux_001_src6_startofpacket), // .startofpacket + .src6_endofpacket (cmd_xbar_demux_001_src6_endofpacket), // .endofpacket + .src7_ready (cmd_xbar_demux_001_src7_ready), // src7.ready + .src7_valid (cmd_xbar_demux_001_src7_valid), // .valid + .src7_data (cmd_xbar_demux_001_src7_data), // .data + .src7_channel (cmd_xbar_demux_001_src7_channel), // .channel + .src7_startofpacket (cmd_xbar_demux_001_src7_startofpacket), // .startofpacket + .src7_endofpacket (cmd_xbar_demux_001_src7_endofpacket), // .endofpacket + .src8_ready (cmd_xbar_demux_001_src8_ready), // src8.ready + .src8_valid (cmd_xbar_demux_001_src8_valid), // .valid + .src8_data (cmd_xbar_demux_001_src8_data), // .data + .src8_channel (cmd_xbar_demux_001_src8_channel), // .channel + .src8_startofpacket (cmd_xbar_demux_001_src8_startofpacket), // .startofpacket + .src8_endofpacket (cmd_xbar_demux_001_src8_endofpacket), // .endofpacket + .src9_ready (cmd_xbar_demux_001_src9_ready), // src9.ready + .src9_valid (cmd_xbar_demux_001_src9_valid), // .valid + .src9_data (cmd_xbar_demux_001_src9_data), // .data + .src9_channel (cmd_xbar_demux_001_src9_channel), // .channel + .src9_startofpacket (cmd_xbar_demux_001_src9_startofpacket), // .startofpacket + .src9_endofpacket (cmd_xbar_demux_001_src9_endofpacket), // .endofpacket + .src10_ready (cmd_xbar_demux_001_src10_ready), // src10.ready + .src10_valid (cmd_xbar_demux_001_src10_valid), // .valid + .src10_data (cmd_xbar_demux_001_src10_data), // .data + .src10_channel (cmd_xbar_demux_001_src10_channel), // .channel + .src10_startofpacket (cmd_xbar_demux_001_src10_startofpacket), // .startofpacket + .src10_endofpacket (cmd_xbar_demux_001_src10_endofpacket) // .endofpacket + ); + + system_cmd_xbar_mux cmd_xbar_mux ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .src_ready (cmd_xbar_mux_src_ready), // src.ready + .src_valid (cmd_xbar_mux_src_valid), // .valid + .src_data (cmd_xbar_mux_src_data), // .data + .src_channel (cmd_xbar_mux_src_channel), // .channel + .src_startofpacket (cmd_xbar_mux_src_startofpacket), // .startofpacket + .src_endofpacket (cmd_xbar_mux_src_endofpacket), // .endofpacket + .sink0_ready (cmd_xbar_demux_src0_ready), // sink0.ready + .sink0_valid (cmd_xbar_demux_src0_valid), // .valid + .sink0_channel (cmd_xbar_demux_src0_channel), // .channel + .sink0_data (cmd_xbar_demux_src0_data), // .data + .sink0_startofpacket (cmd_xbar_demux_src0_startofpacket), // .startofpacket + .sink0_endofpacket (cmd_xbar_demux_src0_endofpacket), // .endofpacket + .sink1_ready (cmd_xbar_demux_001_src0_ready), // sink1.ready + .sink1_valid (cmd_xbar_demux_001_src0_valid), // .valid + .sink1_channel (cmd_xbar_demux_001_src0_channel), // .channel + .sink1_data (cmd_xbar_demux_001_src0_data), // .data + .sink1_startofpacket (cmd_xbar_demux_001_src0_startofpacket), // .startofpacket + .sink1_endofpacket (cmd_xbar_demux_001_src0_endofpacket) // .endofpacket + ); + + system_cmd_xbar_mux cmd_xbar_mux_001 ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .src_ready (cmd_xbar_mux_001_src_ready), // src.ready + .src_valid (cmd_xbar_mux_001_src_valid), // .valid + .src_data (cmd_xbar_mux_001_src_data), // .data + .src_channel (cmd_xbar_mux_001_src_channel), // .channel + .src_startofpacket (cmd_xbar_mux_001_src_startofpacket), // .startofpacket + .src_endofpacket (cmd_xbar_mux_001_src_endofpacket), // .endofpacket + .sink0_ready (cmd_xbar_demux_src1_ready), // sink0.ready + .sink0_valid (cmd_xbar_demux_src1_valid), // .valid + .sink0_channel (cmd_xbar_demux_src1_channel), // .channel + .sink0_data (cmd_xbar_demux_src1_data), // .data + .sink0_startofpacket (cmd_xbar_demux_src1_startofpacket), // .startofpacket + .sink0_endofpacket (cmd_xbar_demux_src1_endofpacket), // .endofpacket + .sink1_ready (cmd_xbar_demux_001_src1_ready), // sink1.ready + .sink1_valid (cmd_xbar_demux_001_src1_valid), // .valid + .sink1_channel (cmd_xbar_demux_001_src1_channel), // .channel + .sink1_data (cmd_xbar_demux_001_src1_data), // .data + .sink1_startofpacket (cmd_xbar_demux_001_src1_startofpacket), // .startofpacket + .sink1_endofpacket (cmd_xbar_demux_001_src1_endofpacket) // .endofpacket + ); + + system_rsp_xbar_demux rsp_xbar_demux ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .sink_ready (id_router_src_ready), // sink.ready + .sink_channel (id_router_src_channel), // .channel + .sink_data (id_router_src_data), // .data + .sink_startofpacket (id_router_src_startofpacket), // .startofpacket + .sink_endofpacket (id_router_src_endofpacket), // .endofpacket + .sink_valid (id_router_src_valid), // .valid + .src0_ready (rsp_xbar_demux_src0_ready), // src0.ready + .src0_valid (rsp_xbar_demux_src0_valid), // .valid + .src0_data (rsp_xbar_demux_src0_data), // .data + .src0_channel (rsp_xbar_demux_src0_channel), // .channel + .src0_startofpacket (rsp_xbar_demux_src0_startofpacket), // .startofpacket + .src0_endofpacket (rsp_xbar_demux_src0_endofpacket), // .endofpacket + .src1_ready (rsp_xbar_demux_src1_ready), // src1.ready + .src1_valid (rsp_xbar_demux_src1_valid), // .valid + .src1_data (rsp_xbar_demux_src1_data), // .data + .src1_channel (rsp_xbar_demux_src1_channel), // .channel + .src1_startofpacket (rsp_xbar_demux_src1_startofpacket), // .startofpacket + .src1_endofpacket (rsp_xbar_demux_src1_endofpacket) // .endofpacket + ); + + system_rsp_xbar_demux rsp_xbar_demux_001 ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .sink_ready (width_adapter_001_src_ready), // sink.ready + .sink_channel (width_adapter_001_src_channel), // .channel + .sink_data (width_adapter_001_src_data), // .data + .sink_startofpacket (width_adapter_001_src_startofpacket), // .startofpacket + .sink_endofpacket (width_adapter_001_src_endofpacket), // .endofpacket + .sink_valid (width_adapter_001_src_valid), // .valid + .src0_ready (rsp_xbar_demux_001_src0_ready), // src0.ready + .src0_valid (rsp_xbar_demux_001_src0_valid), // .valid + .src0_data (rsp_xbar_demux_001_src0_data), // .data + .src0_channel (rsp_xbar_demux_001_src0_channel), // .channel + .src0_startofpacket (rsp_xbar_demux_001_src0_startofpacket), // .startofpacket + .src0_endofpacket (rsp_xbar_demux_001_src0_endofpacket), // .endofpacket + .src1_ready (rsp_xbar_demux_001_src1_ready), // src1.ready + .src1_valid (rsp_xbar_demux_001_src1_valid), // .valid + .src1_data (rsp_xbar_demux_001_src1_data), // .data + .src1_channel (rsp_xbar_demux_001_src1_channel), // .channel + .src1_startofpacket (rsp_xbar_demux_001_src1_startofpacket), // .startofpacket + .src1_endofpacket (rsp_xbar_demux_001_src1_endofpacket) // .endofpacket + ); + + system_rsp_xbar_demux_002 rsp_xbar_demux_002 ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .sink_ready (id_router_002_src_ready), // sink.ready + .sink_channel (id_router_002_src_channel), // .channel + .sink_data (id_router_002_src_data), // .data + .sink_startofpacket (id_router_002_src_startofpacket), // .startofpacket + .sink_endofpacket (id_router_002_src_endofpacket), // .endofpacket + .sink_valid (id_router_002_src_valid), // .valid + .src0_ready (rsp_xbar_demux_002_src0_ready), // src0.ready + .src0_valid (rsp_xbar_demux_002_src0_valid), // .valid + .src0_data (rsp_xbar_demux_002_src0_data), // .data + .src0_channel (rsp_xbar_demux_002_src0_channel), // .channel + .src0_startofpacket (rsp_xbar_demux_002_src0_startofpacket), // .startofpacket + .src0_endofpacket (rsp_xbar_demux_002_src0_endofpacket) // .endofpacket + ); + + system_rsp_xbar_demux_002 rsp_xbar_demux_003 ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .sink_ready (id_router_003_src_ready), // sink.ready + .sink_channel (id_router_003_src_channel), // .channel + .sink_data (id_router_003_src_data), // .data + .sink_startofpacket (id_router_003_src_startofpacket), // .startofpacket + .sink_endofpacket (id_router_003_src_endofpacket), // .endofpacket + .sink_valid (id_router_003_src_valid), // .valid + .src0_ready (rsp_xbar_demux_003_src0_ready), // src0.ready + .src0_valid (rsp_xbar_demux_003_src0_valid), // .valid + .src0_data (rsp_xbar_demux_003_src0_data), // .data + .src0_channel (rsp_xbar_demux_003_src0_channel), // .channel + .src0_startofpacket (rsp_xbar_demux_003_src0_startofpacket), // .startofpacket + .src0_endofpacket (rsp_xbar_demux_003_src0_endofpacket) // .endofpacket + ); + + system_rsp_xbar_demux_002 rsp_xbar_demux_004 ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .sink_ready (id_router_004_src_ready), // sink.ready + .sink_channel (id_router_004_src_channel), // .channel + .sink_data (id_router_004_src_data), // .data + .sink_startofpacket (id_router_004_src_startofpacket), // .startofpacket + .sink_endofpacket (id_router_004_src_endofpacket), // .endofpacket + .sink_valid (id_router_004_src_valid), // .valid + .src0_ready (rsp_xbar_demux_004_src0_ready), // src0.ready + .src0_valid (rsp_xbar_demux_004_src0_valid), // .valid + .src0_data (rsp_xbar_demux_004_src0_data), // .data + .src0_channel (rsp_xbar_demux_004_src0_channel), // .channel + .src0_startofpacket (rsp_xbar_demux_004_src0_startofpacket), // .startofpacket + .src0_endofpacket (rsp_xbar_demux_004_src0_endofpacket) // .endofpacket + ); + + system_rsp_xbar_demux_002 rsp_xbar_demux_005 ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .sink_ready (id_router_005_src_ready), // sink.ready + .sink_channel (id_router_005_src_channel), // .channel + .sink_data (id_router_005_src_data), // .data + .sink_startofpacket (id_router_005_src_startofpacket), // .startofpacket + .sink_endofpacket (id_router_005_src_endofpacket), // .endofpacket + .sink_valid (id_router_005_src_valid), // .valid + .src0_ready (rsp_xbar_demux_005_src0_ready), // src0.ready + .src0_valid (rsp_xbar_demux_005_src0_valid), // .valid + .src0_data (rsp_xbar_demux_005_src0_data), // .data + .src0_channel (rsp_xbar_demux_005_src0_channel), // .channel + .src0_startofpacket (rsp_xbar_demux_005_src0_startofpacket), // .startofpacket + .src0_endofpacket (rsp_xbar_demux_005_src0_endofpacket) // .endofpacket + ); + + system_rsp_xbar_demux_002 rsp_xbar_demux_006 ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .sink_ready (id_router_006_src_ready), // sink.ready + .sink_channel (id_router_006_src_channel), // .channel + .sink_data (id_router_006_src_data), // .data + .sink_startofpacket (id_router_006_src_startofpacket), // .startofpacket + .sink_endofpacket (id_router_006_src_endofpacket), // .endofpacket + .sink_valid (id_router_006_src_valid), // .valid + .src0_ready (rsp_xbar_demux_006_src0_ready), // src0.ready + .src0_valid (rsp_xbar_demux_006_src0_valid), // .valid + .src0_data (rsp_xbar_demux_006_src0_data), // .data + .src0_channel (rsp_xbar_demux_006_src0_channel), // .channel + .src0_startofpacket (rsp_xbar_demux_006_src0_startofpacket), // .startofpacket + .src0_endofpacket (rsp_xbar_demux_006_src0_endofpacket) // .endofpacket + ); + + system_rsp_xbar_demux_002 rsp_xbar_demux_007 ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .sink_ready (id_router_007_src_ready), // sink.ready + .sink_channel (id_router_007_src_channel), // .channel + .sink_data (id_router_007_src_data), // .data + .sink_startofpacket (id_router_007_src_startofpacket), // .startofpacket + .sink_endofpacket (id_router_007_src_endofpacket), // .endofpacket + .sink_valid (id_router_007_src_valid), // .valid + .src0_ready (rsp_xbar_demux_007_src0_ready), // src0.ready + .src0_valid (rsp_xbar_demux_007_src0_valid), // .valid + .src0_data (rsp_xbar_demux_007_src0_data), // .data + .src0_channel (rsp_xbar_demux_007_src0_channel), // .channel + .src0_startofpacket (rsp_xbar_demux_007_src0_startofpacket), // .startofpacket + .src0_endofpacket (rsp_xbar_demux_007_src0_endofpacket) // .endofpacket + ); + + system_rsp_xbar_demux_002 rsp_xbar_demux_008 ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .sink_ready (id_router_008_src_ready), // sink.ready + .sink_channel (id_router_008_src_channel), // .channel + .sink_data (id_router_008_src_data), // .data + .sink_startofpacket (id_router_008_src_startofpacket), // .startofpacket + .sink_endofpacket (id_router_008_src_endofpacket), // .endofpacket + .sink_valid (id_router_008_src_valid), // .valid + .src0_ready (rsp_xbar_demux_008_src0_ready), // src0.ready + .src0_valid (rsp_xbar_demux_008_src0_valid), // .valid + .src0_data (rsp_xbar_demux_008_src0_data), // .data + .src0_channel (rsp_xbar_demux_008_src0_channel), // .channel + .src0_startofpacket (rsp_xbar_demux_008_src0_startofpacket), // .startofpacket + .src0_endofpacket (rsp_xbar_demux_008_src0_endofpacket) // .endofpacket + ); + + system_rsp_xbar_demux_002 rsp_xbar_demux_009 ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .sink_ready (id_router_009_src_ready), // sink.ready + .sink_channel (id_router_009_src_channel), // .channel + .sink_data (id_router_009_src_data), // .data + .sink_startofpacket (id_router_009_src_startofpacket), // .startofpacket + .sink_endofpacket (id_router_009_src_endofpacket), // .endofpacket + .sink_valid (id_router_009_src_valid), // .valid + .src0_ready (rsp_xbar_demux_009_src0_ready), // src0.ready + .src0_valid (rsp_xbar_demux_009_src0_valid), // .valid + .src0_data (rsp_xbar_demux_009_src0_data), // .data + .src0_channel (rsp_xbar_demux_009_src0_channel), // .channel + .src0_startofpacket (rsp_xbar_demux_009_src0_startofpacket), // .startofpacket + .src0_endofpacket (rsp_xbar_demux_009_src0_endofpacket) // .endofpacket + ); + + system_rsp_xbar_demux_002 rsp_xbar_demux_010 ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .sink_ready (id_router_010_src_ready), // sink.ready + .sink_channel (id_router_010_src_channel), // .channel + .sink_data (id_router_010_src_data), // .data + .sink_startofpacket (id_router_010_src_startofpacket), // .startofpacket + .sink_endofpacket (id_router_010_src_endofpacket), // .endofpacket + .sink_valid (id_router_010_src_valid), // .valid + .src0_ready (rsp_xbar_demux_010_src0_ready), // src0.ready + .src0_valid (rsp_xbar_demux_010_src0_valid), // .valid + .src0_data (rsp_xbar_demux_010_src0_data), // .data + .src0_channel (rsp_xbar_demux_010_src0_channel), // .channel + .src0_startofpacket (rsp_xbar_demux_010_src0_startofpacket), // .startofpacket + .src0_endofpacket (rsp_xbar_demux_010_src0_endofpacket) // .endofpacket + ); + + system_rsp_xbar_mux rsp_xbar_mux ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .src_ready (rsp_xbar_mux_src_ready), // src.ready + .src_valid (rsp_xbar_mux_src_valid), // .valid + .src_data (rsp_xbar_mux_src_data), // .data + .src_channel (rsp_xbar_mux_src_channel), // .channel + .src_startofpacket (rsp_xbar_mux_src_startofpacket), // .startofpacket + .src_endofpacket (rsp_xbar_mux_src_endofpacket), // .endofpacket + .sink0_ready (rsp_xbar_demux_src0_ready), // sink0.ready + .sink0_valid (rsp_xbar_demux_src0_valid), // .valid + .sink0_channel (rsp_xbar_demux_src0_channel), // .channel + .sink0_data (rsp_xbar_demux_src0_data), // .data + .sink0_startofpacket (rsp_xbar_demux_src0_startofpacket), // .startofpacket + .sink0_endofpacket (rsp_xbar_demux_src0_endofpacket), // .endofpacket + .sink1_ready (rsp_xbar_demux_001_src0_ready), // sink1.ready + .sink1_valid (rsp_xbar_demux_001_src0_valid), // .valid + .sink1_channel (rsp_xbar_demux_001_src0_channel), // .channel + .sink1_data (rsp_xbar_demux_001_src0_data), // .data + .sink1_startofpacket (rsp_xbar_demux_001_src0_startofpacket), // .startofpacket + .sink1_endofpacket (rsp_xbar_demux_001_src0_endofpacket) // .endofpacket + ); + + system_rsp_xbar_mux_001 rsp_xbar_mux_001 ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .src_ready (rsp_xbar_mux_001_src_ready), // src.ready + .src_valid (rsp_xbar_mux_001_src_valid), // .valid + .src_data (rsp_xbar_mux_001_src_data), // .data + .src_channel (rsp_xbar_mux_001_src_channel), // .channel + .src_startofpacket (rsp_xbar_mux_001_src_startofpacket), // .startofpacket + .src_endofpacket (rsp_xbar_mux_001_src_endofpacket), // .endofpacket + .sink0_ready (rsp_xbar_demux_src1_ready), // sink0.ready + .sink0_valid (rsp_xbar_demux_src1_valid), // .valid + .sink0_channel (rsp_xbar_demux_src1_channel), // .channel + .sink0_data (rsp_xbar_demux_src1_data), // .data + .sink0_startofpacket (rsp_xbar_demux_src1_startofpacket), // .startofpacket + .sink0_endofpacket (rsp_xbar_demux_src1_endofpacket), // .endofpacket + .sink1_ready (rsp_xbar_demux_001_src1_ready), // sink1.ready + .sink1_valid (rsp_xbar_demux_001_src1_valid), // .valid + .sink1_channel (rsp_xbar_demux_001_src1_channel), // .channel + .sink1_data (rsp_xbar_demux_001_src1_data), // .data + .sink1_startofpacket (rsp_xbar_demux_001_src1_startofpacket), // .startofpacket + .sink1_endofpacket (rsp_xbar_demux_001_src1_endofpacket), // .endofpacket + .sink2_ready (rsp_xbar_demux_002_src0_ready), // sink2.ready + .sink2_valid (rsp_xbar_demux_002_src0_valid), // .valid + .sink2_channel (rsp_xbar_demux_002_src0_channel), // .channel + .sink2_data (rsp_xbar_demux_002_src0_data), // .data + .sink2_startofpacket (rsp_xbar_demux_002_src0_startofpacket), // .startofpacket + .sink2_endofpacket (rsp_xbar_demux_002_src0_endofpacket), // .endofpacket + .sink3_ready (rsp_xbar_demux_003_src0_ready), // sink3.ready + .sink3_valid (rsp_xbar_demux_003_src0_valid), // .valid + .sink3_channel (rsp_xbar_demux_003_src0_channel), // .channel + .sink3_data (rsp_xbar_demux_003_src0_data), // .data + .sink3_startofpacket (rsp_xbar_demux_003_src0_startofpacket), // .startofpacket + .sink3_endofpacket (rsp_xbar_demux_003_src0_endofpacket), // .endofpacket + .sink4_ready (rsp_xbar_demux_004_src0_ready), // sink4.ready + .sink4_valid (rsp_xbar_demux_004_src0_valid), // .valid + .sink4_channel (rsp_xbar_demux_004_src0_channel), // .channel + .sink4_data (rsp_xbar_demux_004_src0_data), // .data + .sink4_startofpacket (rsp_xbar_demux_004_src0_startofpacket), // .startofpacket + .sink4_endofpacket (rsp_xbar_demux_004_src0_endofpacket), // .endofpacket + .sink5_ready (rsp_xbar_demux_005_src0_ready), // sink5.ready + .sink5_valid (rsp_xbar_demux_005_src0_valid), // .valid + .sink5_channel (rsp_xbar_demux_005_src0_channel), // .channel + .sink5_data (rsp_xbar_demux_005_src0_data), // .data + .sink5_startofpacket (rsp_xbar_demux_005_src0_startofpacket), // .startofpacket + .sink5_endofpacket (rsp_xbar_demux_005_src0_endofpacket), // .endofpacket + .sink6_ready (rsp_xbar_demux_006_src0_ready), // sink6.ready + .sink6_valid (rsp_xbar_demux_006_src0_valid), // .valid + .sink6_channel (rsp_xbar_demux_006_src0_channel), // .channel + .sink6_data (rsp_xbar_demux_006_src0_data), // .data + .sink6_startofpacket (rsp_xbar_demux_006_src0_startofpacket), // .startofpacket + .sink6_endofpacket (rsp_xbar_demux_006_src0_endofpacket), // .endofpacket + .sink7_ready (rsp_xbar_demux_007_src0_ready), // sink7.ready + .sink7_valid (rsp_xbar_demux_007_src0_valid), // .valid + .sink7_channel (rsp_xbar_demux_007_src0_channel), // .channel + .sink7_data (rsp_xbar_demux_007_src0_data), // .data + .sink7_startofpacket (rsp_xbar_demux_007_src0_startofpacket), // .startofpacket + .sink7_endofpacket (rsp_xbar_demux_007_src0_endofpacket), // .endofpacket + .sink8_ready (rsp_xbar_demux_008_src0_ready), // sink8.ready + .sink8_valid (rsp_xbar_demux_008_src0_valid), // .valid + .sink8_channel (rsp_xbar_demux_008_src0_channel), // .channel + .sink8_data (rsp_xbar_demux_008_src0_data), // .data + .sink8_startofpacket (rsp_xbar_demux_008_src0_startofpacket), // .startofpacket + .sink8_endofpacket (rsp_xbar_demux_008_src0_endofpacket), // .endofpacket + .sink9_ready (rsp_xbar_demux_009_src0_ready), // sink9.ready + .sink9_valid (rsp_xbar_demux_009_src0_valid), // .valid + .sink9_channel (rsp_xbar_demux_009_src0_channel), // .channel + .sink9_data (rsp_xbar_demux_009_src0_data), // .data + .sink9_startofpacket (rsp_xbar_demux_009_src0_startofpacket), // .startofpacket + .sink9_endofpacket (rsp_xbar_demux_009_src0_endofpacket), // .endofpacket + .sink10_ready (rsp_xbar_demux_010_src0_ready), // sink10.ready + .sink10_valid (rsp_xbar_demux_010_src0_valid), // .valid + .sink10_channel (rsp_xbar_demux_010_src0_channel), // .channel + .sink10_data (rsp_xbar_demux_010_src0_data), // .data + .sink10_startofpacket (rsp_xbar_demux_010_src0_startofpacket), // .startofpacket + .sink10_endofpacket (rsp_xbar_demux_010_src0_endofpacket) // .endofpacket + ); + + altera_merlin_width_adapter #( + .IN_PKT_ADDR_H (61), + .IN_PKT_ADDR_L (36), + .IN_PKT_DATA_H (31), + .IN_PKT_DATA_L (0), + .IN_PKT_BYTEEN_H (35), + .IN_PKT_BYTEEN_L (32), + .IN_PKT_BYTE_CNT_H (70), + .IN_PKT_BYTE_CNT_L (68), + .IN_PKT_TRANS_COMPRESSED_READ (62), + .IN_PKT_BURSTWRAP_H (73), + .IN_PKT_BURSTWRAP_L (71), + .IN_PKT_BURST_SIZE_H (76), + .IN_PKT_BURST_SIZE_L (74), + .IN_PKT_RESPONSE_STATUS_H (100), + .IN_PKT_RESPONSE_STATUS_L (99), + .IN_PKT_TRANS_EXCLUSIVE (67), + .IN_PKT_BURST_TYPE_H (78), + .IN_PKT_BURST_TYPE_L (77), + .IN_ST_DATA_W (101), + .OUT_PKT_ADDR_H (43), + .OUT_PKT_ADDR_L (18), + .OUT_PKT_DATA_H (15), + .OUT_PKT_DATA_L (0), + .OUT_PKT_BYTEEN_H (17), + .OUT_PKT_BYTEEN_L (16), + .OUT_PKT_BYTE_CNT_H (52), + .OUT_PKT_BYTE_CNT_L (50), + .OUT_PKT_TRANS_COMPRESSED_READ (44), + .OUT_PKT_BURST_SIZE_H (58), + .OUT_PKT_BURST_SIZE_L (56), + .OUT_PKT_RESPONSE_STATUS_H (82), + .OUT_PKT_RESPONSE_STATUS_L (81), + .OUT_PKT_TRANS_EXCLUSIVE (49), + .OUT_PKT_BURST_TYPE_H (60), + .OUT_PKT_BURST_TYPE_L (59), + .OUT_ST_DATA_W (83), + .ST_CHANNEL_W (11), + .OPTIMIZE_FOR_RSP (0) + ) width_adapter ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .in_valid (cmd_xbar_mux_001_src_valid), // sink.valid + .in_channel (cmd_xbar_mux_001_src_channel), // .channel + .in_startofpacket (cmd_xbar_mux_001_src_startofpacket), // .startofpacket + .in_endofpacket (cmd_xbar_mux_001_src_endofpacket), // .endofpacket + .in_ready (cmd_xbar_mux_001_src_ready), // .ready + .in_data (cmd_xbar_mux_001_src_data), // .data + .out_endofpacket (width_adapter_src_endofpacket), // src.endofpacket + .out_data (width_adapter_src_data), // .data + .out_channel (width_adapter_src_channel), // .channel + .out_valid (width_adapter_src_valid), // .valid + .out_ready (width_adapter_src_ready), // .ready + .out_startofpacket (width_adapter_src_startofpacket), // .startofpacket + .in_command_size_data (3'b000) // (terminated) + ); + + altera_merlin_width_adapter #( + .IN_PKT_ADDR_H (43), + .IN_PKT_ADDR_L (18), + .IN_PKT_DATA_H (15), + .IN_PKT_DATA_L (0), + .IN_PKT_BYTEEN_H (17), + .IN_PKT_BYTEEN_L (16), + .IN_PKT_BYTE_CNT_H (52), + .IN_PKT_BYTE_CNT_L (50), + .IN_PKT_TRANS_COMPRESSED_READ (44), + .IN_PKT_BURSTWRAP_H (55), + .IN_PKT_BURSTWRAP_L (53), + .IN_PKT_BURST_SIZE_H (58), + .IN_PKT_BURST_SIZE_L (56), + .IN_PKT_RESPONSE_STATUS_H (82), + .IN_PKT_RESPONSE_STATUS_L (81), + .IN_PKT_TRANS_EXCLUSIVE (49), + .IN_PKT_BURST_TYPE_H (60), + .IN_PKT_BURST_TYPE_L (59), + .IN_ST_DATA_W (83), + .OUT_PKT_ADDR_H (61), + .OUT_PKT_ADDR_L (36), + .OUT_PKT_DATA_H (31), + .OUT_PKT_DATA_L (0), + .OUT_PKT_BYTEEN_H (35), + .OUT_PKT_BYTEEN_L (32), + .OUT_PKT_BYTE_CNT_H (70), + .OUT_PKT_BYTE_CNT_L (68), + .OUT_PKT_TRANS_COMPRESSED_READ (62), + .OUT_PKT_BURST_SIZE_H (76), + .OUT_PKT_BURST_SIZE_L (74), + .OUT_PKT_RESPONSE_STATUS_H (100), + .OUT_PKT_RESPONSE_STATUS_L (99), + .OUT_PKT_TRANS_EXCLUSIVE (67), + .OUT_PKT_BURST_TYPE_H (78), + .OUT_PKT_BURST_TYPE_L (77), + .OUT_ST_DATA_W (101), + .ST_CHANNEL_W (11), + .OPTIMIZE_FOR_RSP (1) + ) width_adapter_001 ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .in_valid (id_router_001_src_valid), // sink.valid + .in_channel (id_router_001_src_channel), // .channel + .in_startofpacket (id_router_001_src_startofpacket), // .startofpacket + .in_endofpacket (id_router_001_src_endofpacket), // .endofpacket + .in_ready (id_router_001_src_ready), // .ready + .in_data (id_router_001_src_data), // .data + .out_endofpacket (width_adapter_001_src_endofpacket), // src.endofpacket + .out_data (width_adapter_001_src_data), // .data + .out_channel (width_adapter_001_src_channel), // .channel + .out_valid (width_adapter_001_src_valid), // .valid + .out_ready (width_adapter_001_src_ready), // .ready + .out_startofpacket (width_adapter_001_src_startofpacket), // .startofpacket + .in_command_size_data (3'b000) // (terminated) + ); + + system_irq_mapper irq_mapper ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // clk_reset.reset + .receiver0_irq (irq_mapper_receiver0_irq), // receiver0.irq + .receiver1_irq (irq_mapper_receiver1_irq), // receiver1.irq + .receiver2_irq (irq_mapper_receiver2_irq), // receiver2.irq + .receiver3_irq (irq_mapper_receiver3_irq), // receiver3.irq + .sender_irq (cpu_d_irq_irq) // sender.irq + ); + +endmodule diff --git a/MCTEST/DE0-nano-HD/system_generation.rpt b/MCTEST/DE0-nano-HD/system_generation.rpt new file mode 100644 index 00000000..a082b3be --- /dev/null +++ b/MCTEST/DE0-nano-HD/system_generation.rpt @@ -0,0 +1,377 @@ +Info: Starting: Create block symbol file (.bsf) +Info: ip-generate --project-directory=C:/Users/gongal/Desktop/DE0-nano-HD/ --output-directory=C:/Users/gongal/Desktop/DE0-nano-HD/system/ --report-file=bsf:C:/Users/gongal/Desktop/DE0-nano-HD/system.bsf --system-info=DEVICE_FAMILY="Cyclone IV E" --system-info=DEVICE=EP4CE22F17C6 --system-info=DEVICE_SPEEDGRADE=6 --component-file=C:/Users/gongal/Desktop/DE0-nano-HD/system.qsys +Progress: Loading DE0-nano-HD/system.qsys +Progress: Reading input file +Progress: Adding clk_sys [clock_source 12.1] +Progress: Parameterizing module clk_sys +Progress: Adding cpu [altera_nios2_qsys 12.1] +Progress: Parameterizing module cpu +Progress: Adding sysid [altera_avalon_sysid_qsys 12.1] +Progress: Parameterizing module sysid +Progress: Adding sdram [altera_avalon_new_sdram_controller 12.1] +Progress: Parameterizing module sdram +Progress: Adding epcs_flash_controller [altera_avalon_epcs_flash_controller 12.1] +Progress: Parameterizing module epcs_flash_controller +Progress: Adding sys_clk_timer [altera_avalon_timer 12.1] +Progress: Parameterizing module sys_clk_timer +Progress: Adding uart_0 [altera_avalon_uart 12.1] +Progress: Parameterizing module uart_0 +Progress: Adding pio_led_green [altera_avalon_pio 12.1] +Progress: Parameterizing module pio_led_green +Progress: Adding pio_key [altera_avalon_pio 12.1] +Progress: Parameterizing module pio_key +Progress: Adding pio_sw [altera_avalon_pio 12.1] +Progress: Parameterizing module pio_sw +Progress: Adding spi_0 [altera_avalon_spi 12.1] +Progress: Parameterizing module spi_0 +Progress: Adding pio_vscodec [altera_avalon_pio 12.1] +Progress: Parameterizing module pio_vscodec +Progress: Adding pio_int3 [altera_avalon_pio 12.1] +Progress: Parameterizing module pio_int3 +Progress: Building connections +Progress: Parameterizing connections +Progress: Validating +Progress: Done reading input file +Info: system.sysid: System ID is not assigned automatically. Edit the System ID parameter to provide a unique ID +Info: system.sysid: Time stamp will be automatically updated when this component is generated. +Info: system.pio_key: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. +Info: system.pio_sw: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. +Info: system.pio_int3: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. +Info: ip-generate succeeded. +Info: Finished: Create block symbol file (.bsf) +Info: +Info: Starting: Create HDL design files for synthesis +Info: ip-generate --project-directory=C:/Users/gongal/Desktop/DE0-nano-HD/ --output-directory=C:/Users/gongal/Desktop/DE0-nano-HD/system/synthesis/ --file-set=QUARTUS_SYNTH --report-file=sopcinfo:C:/Users/gongal/Desktop/DE0-nano-HD/system.sopcinfo --report-file=html:C:/Users/gongal/Desktop/DE0-nano-HD/system.html --report-file=qip:C:/Users/gongal/Desktop/DE0-nano-HD/system/synthesis/system.qip --report-file=cmp:C:/Users/gongal/Desktop/DE0-nano-HD/system.cmp --system-info=DEVICE_FAMILY="Cyclone IV E" --system-info=DEVICE=EP4CE22F17C6 --system-info=DEVICE_SPEEDGRADE=6 --component-file=C:/Users/gongal/Desktop/DE0-nano-HD/system.qsys +Progress: Loading DE0-nano-HD/system.qsys +Progress: Reading input file +Progress: Adding clk_sys [clock_source 12.1] +Progress: Parameterizing module clk_sys +Progress: Adding cpu [altera_nios2_qsys 12.1] +Progress: Parameterizing module cpu +Progress: Adding sysid [altera_avalon_sysid_qsys 12.1] +Progress: Parameterizing module sysid +Progress: Adding sdram [altera_avalon_new_sdram_controller 12.1] +Progress: Parameterizing module sdram +Progress: Adding epcs_flash_controller [altera_avalon_epcs_flash_controller 12.1] +Progress: Parameterizing module epcs_flash_controller +Progress: Adding sys_clk_timer [altera_avalon_timer 12.1] +Progress: Parameterizing module sys_clk_timer +Progress: Adding uart_0 [altera_avalon_uart 12.1] +Progress: Parameterizing module uart_0 +Progress: Adding pio_led_green [altera_avalon_pio 12.1] +Progress: Parameterizing module pio_led_green +Progress: Adding pio_key [altera_avalon_pio 12.1] +Progress: Parameterizing module pio_key +Progress: Adding pio_sw [altera_avalon_pio 12.1] +Progress: Parameterizing module pio_sw +Progress: Adding spi_0 [altera_avalon_spi 12.1] +Progress: Parameterizing module spi_0 +Progress: Adding pio_vscodec [altera_avalon_pio 12.1] +Progress: Parameterizing module pio_vscodec +Progress: Adding pio_int3 [altera_avalon_pio 12.1] +Progress: Parameterizing module pio_int3 +Progress: Building connections +Progress: Parameterizing connections +Progress: Validating +Progress: Done reading input file +Info: system.sysid: System ID is not assigned automatically. Edit the System ID parameter to provide a unique ID +Info: system.sysid: Time stamp will be automatically updated when this component is generated. +Info: system.pio_key: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. +Info: system.pio_sw: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. +Info: system.pio_int3: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. +Info: system: Generating system "system" for QUARTUS_SYNTH +Info: pipeline_bridge_swap_transform: After transform: 13 modules, 55 connections +Info: No custom instruction connections, skipping transform +Info: merlin_translator_transform: After transform: 27 modules, 111 connections +Info: merlin_domain_transform: After transform: 54 modules, 295 connections +Info: merlin_router_transform: After transform: 68 modules, 351 connections +Info: merlin_traffic_limiter_transform: After transform: 70 modules, 361 connections +Info: merlin_burst_transform: After transform: 71 modules, 365 connections +Info: reset_adaptation_transform: After transform: 72 modules, 285 connections +Info: merlin_network_to_switch_transform: After transform: 99 modules, 341 connections +Info: merlin_width_transform: After transform: 101 modules, 347 connections +Info: limiter_update_transform: After transform: 101 modules, 349 connections +Info: merlin_interrupt_mapper_transform: After transform: 102 modules, 352 connections +Warning: system: "No matching role found for epcs_flash_controller:epcs_control_port:endofpacket (endofpacket)" +Warning: system: "No matching role found for epcs_flash_controller:epcs_control_port:dataavailable (dataavailable)" +Warning: system: "No matching role found for epcs_flash_controller:epcs_control_port:readyfordata (readyfordata)" +Warning: system: "No matching role found for uart_0:s1:dataavailable (dataavailable)" +Warning: system: "No matching role found for uart_0:s1:readyfordata (readyfordata)" +Info: cpu: Starting RTL generation for module 'system_cpu' +Info: cpu: Generation command is [exec C:/altera/12.1sp1/quartus/../ip/altera/nios2_ip/altera_nios2/eperl.exe -I C:/altera/12.1sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/12.1sp1/quartus/sopc_builder/bin/europa -I C:/altera/12.1sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/12.1sp1/quartus/sopc_builder/bin -I C:/altera/12.1sp1/quartus/../ip/altera/nios2_ip/altera_nios2/cpu_lib -I C:/altera/12.1sp1/quartus/../ip/altera/nios2_ip/altera_nios2/nios_lib -I C:/altera/12.1sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -I C:/altera/12.1sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -- C:/altera/12.1sp1/quartus/../ip/altera/nios2_ip/altera_nios2/generate_rtl.epl --name=system_cpu --dir=C:/Users/gongal/AppData/Local/Temp/alt6114_8155995218952929961.dir/0001_cpu_gen/ --quartus_dir=C:/altera/12.1sp1/quartus --verilog --config=C:/Users/gongal/AppData/Local/Temp/alt6114_8155995218952929961.dir/0001_cpu_gen//system_cpu_processor_configuration.pl --do_build_sim=0 --bogus ] +Info: cpu: # 2014.02.13 10:58:06 (*) Starting Nios II generation +Info: cpu: # 2014.02.13 10:58:06 (*) Checking for plaintext license. +Info: cpu: # 2014.02.13 10:58:06 (*) Couldn't query license setup in Quartus directory C:/altera/12.1sp1/quartus +Info: cpu: # 2014.02.13 10:58:06 (*) Defaulting to contents of LM_LICENSE_FILE environment variable +Info: cpu: # 2014.02.13 10:58:06 (*) Plaintext license not found. +Info: cpu: # 2014.02.13 10:58:06 (*) Checking for encrypted license (non-evaluation). +Info: cpu: # 2014.02.13 10:58:07 (*) Couldn't query license setup in Quartus directory C:/altera/12.1sp1/quartus +Info: cpu: # 2014.02.13 10:58:07 (*) Defaulting to contents of LM_LICENSE_FILE environment variable +Info: cpu: # 2014.02.13 10:58:07 (*) Encrypted license found. SOF will not be time-limited. +Info: cpu: # 2014.02.13 10:58:07 (*) Elaborating CPU configuration settings +Info: cpu: # 2014.02.13 10:58:07 (*) Creating all objects for CPU +Info: cpu: # 2014.02.13 10:58:07 (*) Testbench +Info: cpu: # 2014.02.13 10:58:07 (*) Instruction decoding +Info: cpu: # 2014.02.13 10:58:07 (*) Instruction fields +Info: cpu: # 2014.02.13 10:58:07 (*) Instruction decodes +Info: cpu: # 2014.02.13 10:58:08 (*) Signals for RTL simulation waveforms +Info: cpu: # 2014.02.13 10:58:08 (*) Instruction controls +Info: cpu: # 2014.02.13 10:58:08 (*) Pipeline frontend +Info: cpu: # 2014.02.13 10:58:08 (*) Pipeline backend +Info: cpu: # 2014.02.13 10:58:10 (*) Generating RTL from CPU objects +Info: cpu: # 2014.02.13 10:58:13 (*) Creating encrypted RTL +Info: cpu: # 2014.02.13 10:58:15 (*) Done Nios II generation +Info: cpu: Done RTL generation for module 'system_cpu' +Info: cpu: "system" instantiated altera_nios2_qsys "cpu" +Info: sysid: "system" instantiated altera_avalon_sysid_qsys "sysid" +Info: Starting classic module elaboration. +cygwin warning: + MS-DOS style path detected: C:/altera/12.1sp1/quartus/sopc_builder/bin/nios_sh + Preferred POSIX equivalent is: /cygdrive/c/altera/12.1sp1/quartus/sopc_builder/bin/nios_sh + CYGWIN environment variable option "nodosfilewarning" turns off this warning. + Consult the user's guide for more details about POSIX paths: + http://cygwin.com/cygwin-ug-net/using.html#using-pathnames +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_8155995218952929961.dir/0003_sopclgen --no_splash --refresh C:/Users/gongal/AppData/Local/Temp/alt6114_8155995218952929961.dir/0003_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +Info: Finished elaborating classic module. +Executing: C:/altera/12.1sp1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/Users/gongal/AppData/Local/Temp/alt6114_8155995218952929961.dir/0003_sopclgen/yysystem.ptf +Info: Running sopc_builder... +cygwin warning: + MS-DOS style path detected: C:/altera/12.1sp1/quartus/sopc_builder/bin/nios_sh + Preferred POSIX equivalent is: /cygdrive/c/altera/12.1sp1/quartus/sopc_builder/bin/nios_sh + CYGWIN environment variable option "nodosfilewarning" turns off this warning. + Consult the user's guide for more details about POSIX paths: + http://cygwin.com/cygwin-ug-net/using.html#using-pathnames +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_8155995218952929961.dir/0003_sopclgen --generate C:/Users/gongal/AppData/Local/Temp/alt6114_8155995218952929961.dir/0003_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +No .sopc_builder configuration file(!) +. +. +# 2014.02.13 10:58:20 (*) Running Test Generator Program for system_sdram +# 2014.02.13 10:58:21 (*) Success: sopc_builder finished. +Info: sdram: "system" instantiated altera_avalon_new_sdram_controller "sdram" +Info: Starting classic module elaboration. +cygwin warning: + MS-DOS style path detected: C:/altera/12.1sp1/quartus/sopc_builder/bin/nios_sh + Preferred POSIX equivalent is: /cygdrive/c/altera/12.1sp1/quartus/sopc_builder/bin/nios_sh + CYGWIN environment variable option "nodosfilewarning" turns off this warning. + Consult the user's guide for more details about POSIX paths: + http://cygwin.com/cygwin-ug-net/using.html#using-pathnames +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_8155995218952929961.dir/0004_sopclgen --no_splash --refresh C:/Users/gongal/AppData/Local/Temp/alt6114_8155995218952929961.dir/0004_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +Info: Finished elaborating classic module. +Executing: C:/altera/12.1sp1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/Users/gongal/AppData/Local/Temp/alt6114_8155995218952929961.dir/0004_sopclgen/yysystem.ptf +Info: Running sopc_builder... +cygwin warning: + MS-DOS style path detected: C:/altera/12.1sp1/quartus/sopc_builder/bin/nios_sh + Preferred POSIX equivalent is: /cygdrive/c/altera/12.1sp1/quartus/sopc_builder/bin/nios_sh + CYGWIN environment variable option "nodosfilewarning" turns off this warning. + Consult the user's guide for more details about POSIX paths: + http://cygwin.com/cygwin-ug-net/using.html#using-pathnames +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_8155995218952929961.dir/0004_sopclgen --generate C:/Users/gongal/AppData/Local/Temp/alt6114_8155995218952929961.dir/0004_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +No .sopc_builder configuration file(!) +. +# 2014.02.13 10:58:26 (*) Success: sopc_builder finished. +Info: epcs_flash_controller: "system" instantiated altera_avalon_epcs_flash_controller "epcs_flash_controller" +Info: Starting classic module elaboration. +cygwin warning: + MS-DOS style path detected: C:/altera/12.1sp1/quartus/sopc_builder/bin/nios_sh + Preferred POSIX equivalent is: /cygdrive/c/altera/12.1sp1/quartus/sopc_builder/bin/nios_sh + CYGWIN environment variable option "nodosfilewarning" turns off this warning. + Consult the user's guide for more details about POSIX paths: + http://cygwin.com/cygwin-ug-net/using.html#using-pathnames +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_8155995218952929961.dir/0005_sopclgen --no_splash --refresh C:/Users/gongal/AppData/Local/Temp/alt6114_8155995218952929961.dir/0005_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +Info: Finished elaborating classic module. +Executing: C:/altera/12.1sp1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/Users/gongal/AppData/Local/Temp/alt6114_8155995218952929961.dir/0005_sopclgen/yysystem.ptf +Info: Running sopc_builder... +cygwin warning: + MS-DOS style path detected: C:/altera/12.1sp1/quartus/sopc_builder/bin/nios_sh + Preferred POSIX equivalent is: /cygdrive/c/altera/12.1sp1/quartus/sopc_builder/bin/nios_sh + CYGWIN environment variable option "nodosfilewarning" turns off this warning. + Consult the user's guide for more details about POSIX paths: + http://cygwin.com/cygwin-ug-net/using.html#using-pathnames +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_8155995218952929961.dir/0005_sopclgen --generate C:/Users/gongal/AppData/Local/Temp/alt6114_8155995218952929961.dir/0005_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +No .sopc_builder configuration file(!) +. +# 2014.02.13 10:58:30 (*) Success: sopc_builder finished. +Info: sys_clk_timer: "system" instantiated altera_avalon_timer "sys_clk_timer" +Info: Starting classic module elaboration. +cygwin warning: + MS-DOS style path detected: C:/altera/12.1sp1/quartus/sopc_builder/bin/nios_sh + Preferred POSIX equivalent is: /cygdrive/c/altera/12.1sp1/quartus/sopc_builder/bin/nios_sh + CYGWIN environment variable option "nodosfilewarning" turns off this warning. + Consult the user's guide for more details about POSIX paths: + http://cygwin.com/cygwin-ug-net/using.html#using-pathnames +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_8155995218952929961.dir/0006_sopclgen --no_splash --refresh C:/Users/gongal/AppData/Local/Temp/alt6114_8155995218952929961.dir/0006_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +Info: Finished elaborating classic module. +Executing: C:/altera/12.1sp1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/Users/gongal/AppData/Local/Temp/alt6114_8155995218952929961.dir/0006_sopclgen/yysystem.ptf +Info: Running sopc_builder... +cygwin warning: + MS-DOS style path detected: C:/altera/12.1sp1/quartus/sopc_builder/bin/nios_sh + Preferred POSIX equivalent is: /cygdrive/c/altera/12.1sp1/quartus/sopc_builder/bin/nios_sh + CYGWIN environment variable option "nodosfilewarning" turns off this warning. + Consult the user's guide for more details about POSIX paths: + http://cygwin.com/cygwin-ug-net/using.html#using-pathnames +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_8155995218952929961.dir/0006_sopclgen --generate C:/Users/gongal/AppData/Local/Temp/alt6114_8155995218952929961.dir/0006_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +No .sopc_builder configuration file(!) +. +# 2014.02.13 10:58:35 (*) Success: sopc_builder finished. +Info: uart_0: "system" instantiated altera_avalon_uart "uart_0" +Info: Starting classic module elaboration. +cygwin warning: + MS-DOS style path detected: C:/altera/12.1sp1/quartus/sopc_builder/bin/nios_sh + Preferred POSIX equivalent is: /cygdrive/c/altera/12.1sp1/quartus/sopc_builder/bin/nios_sh + CYGWIN environment variable option "nodosfilewarning" turns off this warning. + Consult the user's guide for more details about POSIX paths: + http://cygwin.com/cygwin-ug-net/using.html#using-pathnames +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_8155995218952929961.dir/0007_sopclgen --no_splash --refresh C:/Users/gongal/AppData/Local/Temp/alt6114_8155995218952929961.dir/0007_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +Info: Finished elaborating classic module. +Executing: C:/altera/12.1sp1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/Users/gongal/AppData/Local/Temp/alt6114_8155995218952929961.dir/0007_sopclgen/yysystem.ptf +Info: Running sopc_builder... +cygwin warning: + MS-DOS style path detected: C:/altera/12.1sp1/quartus/sopc_builder/bin/nios_sh + Preferred POSIX equivalent is: /cygdrive/c/altera/12.1sp1/quartus/sopc_builder/bin/nios_sh + CYGWIN environment variable option "nodosfilewarning" turns off this warning. + Consult the user's guide for more details about POSIX paths: + http://cygwin.com/cygwin-ug-net/using.html#using-pathnames +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_8155995218952929961.dir/0007_sopclgen --generate C:/Users/gongal/AppData/Local/Temp/alt6114_8155995218952929961.dir/0007_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +No .sopc_builder configuration file(!) +. +# 2014.02.13 10:58:39 (*) Success: sopc_builder finished. +Info: pio_led_green: "system" instantiated altera_avalon_pio "pio_led_green" +Info: Starting classic module elaboration. +cygwin warning: + MS-DOS style path detected: C:/altera/12.1sp1/quartus/sopc_builder/bin/nios_sh + Preferred POSIX equivalent is: /cygdrive/c/altera/12.1sp1/quartus/sopc_builder/bin/nios_sh + CYGWIN environment variable option "nodosfilewarning" turns off this warning. + Consult the user's guide for more details about POSIX paths: + http://cygwin.com/cygwin-ug-net/using.html#using-pathnames +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_8155995218952929961.dir/0008_sopclgen --no_splash --refresh C:/Users/gongal/AppData/Local/Temp/alt6114_8155995218952929961.dir/0008_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +Info: Finished elaborating classic module. +Executing: C:/altera/12.1sp1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/Users/gongal/AppData/Local/Temp/alt6114_8155995218952929961.dir/0008_sopclgen/yysystem.ptf +Info: Running sopc_builder... +cygwin warning: + MS-DOS style path detected: C:/altera/12.1sp1/quartus/sopc_builder/bin/nios_sh + Preferred POSIX equivalent is: /cygdrive/c/altera/12.1sp1/quartus/sopc_builder/bin/nios_sh + CYGWIN environment variable option "nodosfilewarning" turns off this warning. + Consult the user's guide for more details about POSIX paths: + http://cygwin.com/cygwin-ug-net/using.html#using-pathnames +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_8155995218952929961.dir/0008_sopclgen --generate C:/Users/gongal/AppData/Local/Temp/alt6114_8155995218952929961.dir/0008_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +No .sopc_builder configuration file(!) +. +# 2014.02.13 10:58:43 (*) Success: sopc_builder finished. +Info: pio_key: "system" instantiated altera_avalon_pio "pio_key" +Info: Starting classic module elaboration. +cygwin warning: + MS-DOS style path detected: C:/altera/12.1sp1/quartus/sopc_builder/bin/nios_sh + Preferred POSIX equivalent is: /cygdrive/c/altera/12.1sp1/quartus/sopc_builder/bin/nios_sh + CYGWIN environment variable option "nodosfilewarning" turns off this warning. + Consult the user's guide for more details about POSIX paths: + http://cygwin.com/cygwin-ug-net/using.html#using-pathnames +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_8155995218952929961.dir/0009_sopclgen --no_splash --refresh C:/Users/gongal/AppData/Local/Temp/alt6114_8155995218952929961.dir/0009_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +Info: Finished elaborating classic module. +Executing: C:/altera/12.1sp1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/Users/gongal/AppData/Local/Temp/alt6114_8155995218952929961.dir/0009_sopclgen/yysystem.ptf +Info: Running sopc_builder... +cygwin warning: + MS-DOS style path detected: C:/altera/12.1sp1/quartus/sopc_builder/bin/nios_sh + Preferred POSIX equivalent is: /cygdrive/c/altera/12.1sp1/quartus/sopc_builder/bin/nios_sh + CYGWIN environment variable option "nodosfilewarning" turns off this warning. + Consult the user's guide for more details about POSIX paths: + http://cygwin.com/cygwin-ug-net/using.html#using-pathnames +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_8155995218952929961.dir/0009_sopclgen --generate C:/Users/gongal/AppData/Local/Temp/alt6114_8155995218952929961.dir/0009_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +No .sopc_builder configuration file(!) +. +# 2014.02.13 10:58:47 (*) Success: sopc_builder finished. +Info: pio_sw: "system" instantiated altera_avalon_pio "pio_sw" +Info: Starting classic module elaboration. +cygwin warning: + MS-DOS style path detected: C:/altera/12.1sp1/quartus/sopc_builder/bin/nios_sh + Preferred POSIX equivalent is: /cygdrive/c/altera/12.1sp1/quartus/sopc_builder/bin/nios_sh + CYGWIN environment variable option "nodosfilewarning" turns off this warning. + Consult the user's guide for more details about POSIX paths: + http://cygwin.com/cygwin-ug-net/using.html#using-pathnames +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_8155995218952929961.dir/0010_sopclgen --no_splash --refresh C:/Users/gongal/AppData/Local/Temp/alt6114_8155995218952929961.dir/0010_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +Info: Finished elaborating classic module. +Executing: C:/altera/12.1sp1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/Users/gongal/AppData/Local/Temp/alt6114_8155995218952929961.dir/0010_sopclgen/yysystem.ptf +Info: Running sopc_builder... +cygwin warning: + MS-DOS style path detected: C:/altera/12.1sp1/quartus/sopc_builder/bin/nios_sh + Preferred POSIX equivalent is: /cygdrive/c/altera/12.1sp1/quartus/sopc_builder/bin/nios_sh + CYGWIN environment variable option "nodosfilewarning" turns off this warning. + Consult the user's guide for more details about POSIX paths: + http://cygwin.com/cygwin-ug-net/using.html#using-pathnames +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_8155995218952929961.dir/0010_sopclgen --generate C:/Users/gongal/AppData/Local/Temp/alt6114_8155995218952929961.dir/0010_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +No .sopc_builder configuration file(!) +. +# 2014.02.13 10:58:52 (*) Success: sopc_builder finished. +Info: spi_0: "system" instantiated altera_avalon_spi "spi_0" +Info: Starting classic module elaboration. +cygwin warning: + MS-DOS style path detected: C:/altera/12.1sp1/quartus/sopc_builder/bin/nios_sh + Preferred POSIX equivalent is: /cygdrive/c/altera/12.1sp1/quartus/sopc_builder/bin/nios_sh + CYGWIN environment variable option "nodosfilewarning" turns off this warning. + Consult the user's guide for more details about POSIX paths: + http://cygwin.com/cygwin-ug-net/using.html#using-pathnames +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_8155995218952929961.dir/0011_sopclgen --no_splash --refresh C:/Users/gongal/AppData/Local/Temp/alt6114_8155995218952929961.dir/0011_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +Info: Finished elaborating classic module. +Executing: C:/altera/12.1sp1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/Users/gongal/AppData/Local/Temp/alt6114_8155995218952929961.dir/0011_sopclgen/yysystem.ptf +Info: Running sopc_builder... +cygwin warning: + MS-DOS style path detected: C:/altera/12.1sp1/quartus/sopc_builder/bin/nios_sh + Preferred POSIX equivalent is: /cygdrive/c/altera/12.1sp1/quartus/sopc_builder/bin/nios_sh + CYGWIN environment variable option "nodosfilewarning" turns off this warning. + Consult the user's guide for more details about POSIX paths: + http://cygwin.com/cygwin-ug-net/using.html#using-pathnames +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_8155995218952929961.dir/0011_sopclgen --generate C:/Users/gongal/AppData/Local/Temp/alt6114_8155995218952929961.dir/0011_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +No .sopc_builder configuration file(!) +. +# 2014.02.13 10:58:56 (*) Success: sopc_builder finished. +Info: pio_vscodec: "system" instantiated altera_avalon_pio "pio_vscodec" +Info: Starting classic module elaboration. +cygwin warning: + MS-DOS style path detected: C:/altera/12.1sp1/quartus/sopc_builder/bin/nios_sh + Preferred POSIX equivalent is: /cygdrive/c/altera/12.1sp1/quartus/sopc_builder/bin/nios_sh + CYGWIN environment variable option "nodosfilewarning" turns off this warning. + Consult the user's guide for more details about POSIX paths: + http://cygwin.com/cygwin-ug-net/using.html#using-pathnames +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_8155995218952929961.dir/0012_sopclgen --no_splash --refresh C:/Users/gongal/AppData/Local/Temp/alt6114_8155995218952929961.dir/0012_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +Info: Finished elaborating classic module. +Executing: C:/altera/12.1sp1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/Users/gongal/AppData/Local/Temp/alt6114_8155995218952929961.dir/0012_sopclgen/yysystem.ptf +Info: Running sopc_builder... +cygwin warning: + MS-DOS style path detected: C:/altera/12.1sp1/quartus/sopc_builder/bin/nios_sh + Preferred POSIX equivalent is: /cygdrive/c/altera/12.1sp1/quartus/sopc_builder/bin/nios_sh + CYGWIN environment variable option "nodosfilewarning" turns off this warning. + Consult the user's guide for more details about POSIX paths: + http://cygwin.com/cygwin-ug-net/using.html#using-pathnames +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_8155995218952929961.dir/0012_sopclgen --generate C:/Users/gongal/AppData/Local/Temp/alt6114_8155995218952929961.dir/0012_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +No .sopc_builder configuration file(!) +. +# 2014.02.13 10:59:00 (*) Success: sopc_builder finished. +Info: pio_int3: "system" instantiated altera_avalon_pio "pio_int3" +Info: cpu_instruction_master_translator: "system" instantiated altera_merlin_master_translator "cpu_instruction_master_translator" +Info: cpu_jtag_debug_module_translator: "system" instantiated altera_merlin_slave_translator "cpu_jtag_debug_module_translator" +Info: cpu_instruction_master_translator_avalon_universal_master_0_agent: "system" instantiated altera_merlin_master_agent "cpu_instruction_master_translator_avalon_universal_master_0_agent" +Info: cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent: "system" instantiated altera_merlin_slave_agent "cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent" +Info: cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo: "system" instantiated altera_avalon_sc_fifo "cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo" +Info: addr_router: "system" instantiated altera_merlin_router "addr_router" +Info: addr_router_001: "system" instantiated altera_merlin_router "addr_router_001" +Info: id_router: "system" instantiated altera_merlin_router "id_router" +Info: id_router_001: "system" instantiated altera_merlin_router "id_router_001" +Info: id_router_002: "system" instantiated altera_merlin_router "id_router_002" +Info: limiter: "system" instantiated altera_merlin_traffic_limiter "limiter" +Info: burst_adapter: "system" instantiated altera_merlin_burst_adapter "burst_adapter" +Info: rst_controller: "system" instantiated altera_reset_controller "rst_controller" +Info: cmd_xbar_demux: "system" instantiated altera_merlin_demultiplexer "cmd_xbar_demux" +Info: cmd_xbar_demux_001: "system" instantiated altera_merlin_demultiplexer "cmd_xbar_demux_001" +Info: cmd_xbar_mux: "system" instantiated altera_merlin_multiplexer "cmd_xbar_mux" +Info: rsp_xbar_demux: "system" instantiated altera_merlin_demultiplexer "rsp_xbar_demux" +Info: rsp_xbar_demux_002: "system" instantiated altera_merlin_demultiplexer "rsp_xbar_demux_002" +Info: rsp_xbar_mux: "system" instantiated altera_merlin_multiplexer "rsp_xbar_mux" +Info: Reusing file C:/Users/gongal/Desktop/DE0-nano-HD/system/synthesis/submodules/altera_merlin_arbitrator.sv +Info: rsp_xbar_mux_001: "system" instantiated altera_merlin_multiplexer "rsp_xbar_mux_001" +Info: Reusing file C:/Users/gongal/Desktop/DE0-nano-HD/system/synthesis/submodules/altera_merlin_arbitrator.sv +Info: width_adapter: "system" instantiated altera_merlin_width_adapter "width_adapter" +Info: Reusing file C:/Users/gongal/Desktop/DE0-nano-HD/system/synthesis/submodules/altera_merlin_burst_uncompressor.sv +Info: Reusing file C:/Users/gongal/Desktop/DE0-nano-HD/system/synthesis/submodules/altera_merlin_address_alignment.sv +Info: irq_mapper: "system" instantiated altera_irq_mapper "irq_mapper" +Info: system: Done system" with 35 modules, 131 files, 2663776 bytes +Info: ip-generate succeeded. +Info: Finished: Create HDL design files for synthesis diff --git a/MCTEST/DE0-nano-HD/system_generation_1.rpt b/MCTEST/DE0-nano-HD/system_generation_1.rpt new file mode 100644 index 00000000..904bb1c6 --- /dev/null +++ b/MCTEST/DE0-nano-HD/system_generation_1.rpt @@ -0,0 +1,96 @@ +Info: Starting: Create block symbol file (.bsf) +Info: ip-generate --project-directory=C:/Users/gongal/Desktop/DE0-nano-HD/ --output-directory=C:/Users/gongal/Desktop/DE0-nano-HD/system/ --report-file=bsf:C:/Users/gongal/Desktop/DE0-nano-HD/system.bsf --system-info=DEVICE_FAMILY="Cyclone IV E" --system-info=DEVICE=EP4CE22F17C6 --system-info=DEVICE_SPEEDGRADE=6 --component-file=C:/Users/gongal/Desktop/DE0-nano-HD/system.qsys +Progress: Loading DE0-nano-HD/system.qsys +Progress: Reading input file +Progress: Adding clk_sys [clock_source 12.1] +Progress: Parameterizing module clk_sys +Progress: Adding cpu [altera_nios2_qsys 12.1] +Progress: Parameterizing module cpu +Progress: Adding sysid [altera_avalon_sysid_qsys 12.1] +Progress: Parameterizing module sysid +Progress: Adding sdram [altera_avalon_new_sdram_controller 12.1] +Progress: Parameterizing module sdram +Progress: Adding sys_clk_timer [altera_avalon_timer 12.1] +Progress: Parameterizing module sys_clk_timer +Progress: Adding uart_0 [altera_avalon_uart 12.1] +Progress: Parameterizing module uart_0 +Progress: Adding pio_led_green [altera_avalon_pio 12.1] +Progress: Parameterizing module pio_led_green +Progress: Adding pio_key [altera_avalon_pio 12.1] +Progress: Parameterizing module pio_key +Progress: Adding pio_sw [altera_avalon_pio 12.1] +Progress: Parameterizing module pio_sw +Progress: Adding spi_0 [altera_avalon_spi 12.1] +Progress: Parameterizing module spi_0 +Progress: Adding pio_vscodec [altera_avalon_pio 12.1] +Progress: Parameterizing module pio_vscodec +Progress: Adding pio_int3 [altera_avalon_pio 12.1] +Progress: Parameterizing module pio_int3 +Progress: Building connections +Progress: Parameterizing connections +Progress: Validating +Progress: Done reading input file +Info: system.sysid: System ID is not assigned automatically. Edit the System ID parameter to provide a unique ID +Info: system.sysid: Time stamp will be automatically updated when this component is generated. +Info: system.pio_key: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. +Info: system.pio_sw: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. +Info: system.pio_int3: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. +Info: ip-generate succeeded. +Info: Finished: Create block symbol file (.bsf) +Info: +Info: Starting: Create HDL design files for synthesis +Info: ip-generate --project-directory=C:/Users/gongal/Desktop/DE0-nano-HD/ --output-directory=C:/Users/gongal/Desktop/DE0-nano-HD/system/synthesis/ --file-set=QUARTUS_SYNTH --report-file=sopcinfo:C:/Users/gongal/Desktop/DE0-nano-HD/system.sopcinfo --report-file=html:C:/Users/gongal/Desktop/DE0-nano-HD/system.html --report-file=qip:C:/Users/gongal/Desktop/DE0-nano-HD/system/synthesis/system.qip --report-file=cmp:C:/Users/gongal/Desktop/DE0-nano-HD/system.cmp --system-info=DEVICE_FAMILY="Cyclone IV E" --system-info=DEVICE=EP4CE22F17C6 --system-info=DEVICE_SPEEDGRADE=6 --component-file=C:/Users/gongal/Desktop/DE0-nano-HD/system.qsys +Progress: Loading DE0-nano-HD/system.qsys +Progress: Reading input file +Progress: Adding clk_sys [clock_source 12.1] +Progress: Parameterizing module clk_sys +Progress: Adding cpu [altera_nios2_qsys 12.1] +Progress: Parameterizing module cpu +Progress: Adding sysid [altera_avalon_sysid_qsys 12.1] +Progress: Parameterizing module sysid +Progress: Adding sdram [altera_avalon_new_sdram_controller 12.1] +Progress: Parameterizing module sdram +Progress: Adding sys_clk_timer [altera_avalon_timer 12.1] +Progress: Parameterizing module sys_clk_timer +Progress: Adding uart_0 [altera_avalon_uart 12.1] +Progress: Parameterizing module uart_0 +Progress: Adding pio_led_green [altera_avalon_pio 12.1] +Progress: Parameterizing module pio_led_green +Progress: Adding pio_key [altera_avalon_pio 12.1] +Progress: Parameterizing module pio_key +Progress: Adding pio_sw [altera_avalon_pio 12.1] +Progress: Parameterizing module pio_sw +Progress: Adding spi_0 [altera_avalon_spi 12.1] +Progress: Parameterizing module spi_0 +Progress: Adding pio_vscodec [altera_avalon_pio 12.1] +Progress: Parameterizing module pio_vscodec +Progress: Adding pio_int3 [altera_avalon_pio 12.1] +Progress: Parameterizing module pio_int3 +Progress: Building connections +Progress: Parameterizing connections +Progress: Validating +Progress: Done reading input file +Info: system.sysid: System ID is not assigned automatically. Edit the System ID parameter to provide a unique ID +Info: system.sysid: Time stamp will be automatically updated when this component is generated. +Info: system.pio_key: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. +Info: system.pio_sw: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. +Info: system.pio_int3: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. +Info: system: Generating system "system" for QUARTUS_SYNTH +Info: pipeline_bridge_swap_transform: After transform: 12 modules, 50 connections +Info: No custom instruction connections, skipping transform +Info: merlin_translator_transform: After transform: 25 modules, 102 connections +Info: merlin_domain_transform: After transform: 50 modules, 272 connections +Info: merlin_router_transform: After transform: 63 modules, 324 connections +Info: merlin_traffic_limiter_transform: After transform: 65 modules, 334 connections +Info: merlin_burst_transform: After transform: 66 modules, 338 connections +Info: reset_adaptation_transform: After transform: 67 modules, 264 connections +Info: merlin_network_to_switch_transform: After transform: 92 modules, 316 connections +Info: merlin_width_transform: After transform: 94 modules, 322 connections +Info: limiter_update_transform: After transform: 94 modules, 324 connections +Info: merlin_interrupt_mapper_transform: After transform: 95 modules, 327 connections +Warning: system: "No matching role found for uart_0:s1:dataavailable (dataavailable)" +Warning: system: "No matching role found for uart_0:s1:readyfordata (readyfordata)" +Error: Generation stopped, 85 or more modules remaining +Info: system: Done system" with 34 modules, 1 files, 434194 bytes +Error: ip-generate failed with exit code 1: 1 Error, 2 Warnings +Info: Stopping: Create HDL design files for synthesis diff --git a/MCTEST/DE0-nano-HD/system_generation_2.rpt b/MCTEST/DE0-nano-HD/system_generation_2.rpt new file mode 100644 index 00000000..9140c96c --- /dev/null +++ b/MCTEST/DE0-nano-HD/system_generation_2.rpt @@ -0,0 +1,226 @@ +Info: Starting: Create block symbol file (.bsf) +Info: ip-generate --project-directory=C:/Users/gongal/Desktop/DE0-nano-HD/ --output-directory=C:/Users/gongal/Desktop/DE0-nano-HD/system/ --report-file=bsf:C:/Users/gongal/Desktop/DE0-nano-HD/system.bsf --system-info=DEVICE_FAMILY="Cyclone IV E" --system-info=DEVICE=EP4CE22F17C6 --system-info=DEVICE_SPEEDGRADE=6 --component-file=C:/Users/gongal/Desktop/DE0-nano-HD/system.qsys +Progress: Loading DE0-nano-HD/system.qsys +Progress: Reading input file +Progress: Adding clk_sys [clock_source 12.1] +Progress: Parameterizing module clk_sys +Progress: Adding cpu [altera_nios2_qsys 12.1] +Progress: Parameterizing module cpu +Progress: Adding sysid [altera_avalon_sysid_qsys 12.1] +Progress: Parameterizing module sysid +Progress: Adding sdram [altera_avalon_new_sdram_controller 12.1] +Progress: Parameterizing module sdram +Progress: Adding sys_clk_timer [altera_avalon_timer 12.1] +Progress: Parameterizing module sys_clk_timer +Progress: Adding uart_0 [altera_avalon_uart 12.1] +Progress: Parameterizing module uart_0 +Progress: Adding pio_led [altera_avalon_pio 12.1] +Progress: Parameterizing module pio_led +Progress: Adding pio_key [altera_avalon_pio 12.1] +Progress: Parameterizing module pio_key +Progress: Adding pio_sw [altera_avalon_pio 12.1] +Progress: Parameterizing module pio_sw +Progress: Adding spi_0 [altera_avalon_spi 12.1] +Progress: Parameterizing module spi_0 +Progress: Adding pio_ir [altera_avalon_pio 12.1] +Progress: Parameterizing module pio_ir +Progress: Building connections +Progress: Parameterizing connections +Progress: Validating +Progress: Done reading input file +Info: system.sysid: System ID is not assigned automatically. Edit the System ID parameter to provide a unique ID +Info: system.sysid: Time stamp will be automatically updated when this component is generated. +Info: system.pio_key: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. +Info: system.pio_sw: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. +Info: system.pio_ir: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. +Info: ip-generate succeeded. +Info: Finished: Create block symbol file (.bsf) +Info: +Info: Starting: Create HDL design files for synthesis +Info: ip-generate --project-directory=C:/Users/gongal/Desktop/DE0-nano-HD/ --output-directory=C:/Users/gongal/Desktop/DE0-nano-HD/system/synthesis/ --file-set=QUARTUS_SYNTH --report-file=sopcinfo:C:/Users/gongal/Desktop/DE0-nano-HD/system.sopcinfo --report-file=html:C:/Users/gongal/Desktop/DE0-nano-HD/system.html --report-file=qip:C:/Users/gongal/Desktop/DE0-nano-HD/system/synthesis/system.qip --report-file=cmp:C:/Users/gongal/Desktop/DE0-nano-HD/system.cmp --system-info=DEVICE_FAMILY="Cyclone IV E" --system-info=DEVICE=EP4CE22F17C6 --system-info=DEVICE_SPEEDGRADE=6 --component-file=C:/Users/gongal/Desktop/DE0-nano-HD/system.qsys +Progress: Loading DE0-nano-HD/system.qsys +Progress: Reading input file +Progress: Adding clk_sys [clock_source 12.1] +Progress: Parameterizing module clk_sys +Progress: Adding cpu [altera_nios2_qsys 12.1] +Progress: Parameterizing module cpu +Progress: Adding sysid [altera_avalon_sysid_qsys 12.1] +Progress: Parameterizing module sysid +Progress: Adding sdram [altera_avalon_new_sdram_controller 12.1] +Progress: Parameterizing module sdram +Progress: Adding sys_clk_timer [altera_avalon_timer 12.1] +Progress: Parameterizing module sys_clk_timer +Progress: Adding uart_0 [altera_avalon_uart 12.1] +Progress: Parameterizing module uart_0 +Progress: Adding pio_led [altera_avalon_pio 12.1] +Progress: Parameterizing module pio_led +Progress: Adding pio_key [altera_avalon_pio 12.1] +Progress: Parameterizing module pio_key +Progress: Adding pio_sw [altera_avalon_pio 12.1] +Progress: Parameterizing module pio_sw +Progress: Adding spi_0 [altera_avalon_spi 12.1] +Progress: Parameterizing module spi_0 +Progress: Adding pio_ir [altera_avalon_pio 12.1] +Progress: Parameterizing module pio_ir +Progress: Building connections +Progress: Parameterizing connections +Progress: Validating +Progress: Done reading input file +Info: system.sysid: System ID is not assigned automatically. Edit the System ID parameter to provide a unique ID +Info: system.sysid: Time stamp will be automatically updated when this component is generated. +Info: system.pio_key: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. +Info: system.pio_sw: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. +Info: system.pio_ir: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. +Info: system: Generating system "system" for QUARTUS_SYNTH +Info: pipeline_bridge_swap_transform: After transform: 11 modules, 46 connections +Info: No custom instruction connections, skipping transform +Info: merlin_translator_transform: After transform: 23 modules, 94 connections +Info: merlin_domain_transform: After transform: 46 modules, 250 connections +Info: merlin_router_transform: After transform: 58 modules, 298 connections +Info: merlin_traffic_limiter_transform: After transform: 60 modules, 308 connections +Info: merlin_burst_transform: After transform: 61 modules, 312 connections +Info: reset_adaptation_transform: After transform: 62 modules, 244 connections +Info: merlin_network_to_switch_transform: After transform: 85 modules, 292 connections +Info: merlin_width_transform: After transform: 87 modules, 298 connections +Info: limiter_update_transform: After transform: 87 modules, 300 connections +Info: merlin_interrupt_mapper_transform: After transform: 88 modules, 303 connections +Warning: system: "No matching role found for uart_0:s1:dataavailable (dataavailable)" +Warning: system: "No matching role found for uart_0:s1:readyfordata (readyfordata)" +Info: cpu: Starting RTL generation for module 'system_cpu' +Info: cpu: Generation command is [exec C:/altera/12.1sp1/quartus/../ip/altera/nios2_ip/altera_nios2/eperl.exe -I C:/altera/12.1sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/12.1sp1/quartus/sopc_builder/bin/europa -I C:/altera/12.1sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/12.1sp1/quartus/sopc_builder/bin -I C:/altera/12.1sp1/quartus/../ip/altera/nios2_ip/altera_nios2/cpu_lib -I C:/altera/12.1sp1/quartus/../ip/altera/nios2_ip/altera_nios2/nios_lib -I C:/altera/12.1sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -I C:/altera/12.1sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -- C:/altera/12.1sp1/quartus/../ip/altera/nios2_ip/altera_nios2/generate_rtl.epl --name=system_cpu --dir=C:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0001_cpu_gen/ --quartus_dir=C:/altera/12.1sp1/quartus --verilog --config=C:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0001_cpu_gen//system_cpu_processor_configuration.pl --do_build_sim=0 --bogus ] +Info: cpu: # 2014.02.13 11:57:37 (*) Starting Nios II generation +Info: cpu: # 2014.02.13 11:57:37 (*) Checking for plaintext license. +Info: cpu: # 2014.02.13 11:57:38 (*) Couldn't query license setup in Quartus directory C:/altera/12.1sp1/quartus +Info: cpu: # 2014.02.13 11:57:38 (*) Defaulting to contents of LM_LICENSE_FILE environment variable +Info: cpu: # 2014.02.13 11:57:38 (*) Plaintext license not found. +Info: cpu: # 2014.02.13 11:57:38 (*) Checking for encrypted license (non-evaluation). +Info: cpu: # 2014.02.13 11:57:38 (*) Couldn't query license setup in Quartus directory C:/altera/12.1sp1/quartus +Info: cpu: # 2014.02.13 11:57:38 (*) Defaulting to contents of LM_LICENSE_FILE environment variable +Info: cpu: # 2014.02.13 11:57:38 (*) Encrypted license found. SOF will not be time-limited. +Info: cpu: # 2014.02.13 11:57:38 (*) Elaborating CPU configuration settings +Info: cpu: # 2014.02.13 11:57:38 (*) Creating all objects for CPU +Info: cpu: # 2014.02.13 11:57:38 (*) Testbench +Info: cpu: # 2014.02.13 11:57:38 (*) Instruction decoding +Info: cpu: # 2014.02.13 11:57:38 (*) Instruction fields +Info: cpu: # 2014.02.13 11:57:38 (*) Instruction decodes +Info: cpu: # 2014.02.13 11:57:39 (*) Signals for RTL simulation waveforms +Info: cpu: # 2014.02.13 11:57:39 (*) Instruction controls +Info: cpu: # 2014.02.13 11:57:39 (*) Pipeline frontend +Info: cpu: # 2014.02.13 11:57:39 (*) Pipeline backend +Info: cpu: # 2014.02.13 11:57:41 (*) Generating RTL from CPU objects +Info: cpu: # 2014.02.13 11:57:45 (*) Creating encrypted RTL +Info: cpu: # 2014.02.13 11:57:46 (*) Done Nios II generation +Info: cpu: Done RTL generation for module 'system_cpu' +Info: cpu: "system" instantiated altera_nios2_qsys "cpu" +Info: sysid: "system" instantiated altera_avalon_sysid_qsys "sysid" +Info: Starting classic module elaboration. +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0003_sopclgen --no_splash --refresh C:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0003_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +Info: Finished elaborating classic module. +Executing: C:/altera/12.1sp1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0003_sopclgen/yysystem.ptf +Info: Running sopc_builder... +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0003_sopclgen --generate C:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0003_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +No .sopc_builder configuration file(!) +. +. +# 2014.02.13 11:57:50 (*) Running Test Generator Program for system_sdram +# 2014.02.13 11:57:51 (*) Success: sopc_builder finished. +Info: sdram: "system" instantiated altera_avalon_new_sdram_controller "sdram" +Info: Starting classic module elaboration. +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0004_sopclgen --no_splash --refresh C:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0004_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +Info: Finished elaborating classic module. +Executing: C:/altera/12.1sp1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0004_sopclgen/yysystem.ptf +Info: Running sopc_builder... +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0004_sopclgen --generate C:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0004_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +No .sopc_builder configuration file(!) +. +# 2014.02.13 11:57:55 (*) Success: sopc_builder finished. +Info: sys_clk_timer: "system" instantiated altera_avalon_timer "sys_clk_timer" +Info: Starting classic module elaboration. +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0005_sopclgen --no_splash --refresh C:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0005_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +Info: Finished elaborating classic module. +Executing: C:/altera/12.1sp1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0005_sopclgen/yysystem.ptf +Info: Running sopc_builder... +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0005_sopclgen --generate C:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0005_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +No .sopc_builder configuration file(!) +. +# 2014.02.13 11:58:00 (*) Success: sopc_builder finished. +Info: uart_0: "system" instantiated altera_avalon_uart "uart_0" +Info: Starting classic module elaboration. +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0006_sopclgen --no_splash --refresh C:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0006_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +Info: Finished elaborating classic module. +Executing: C:/altera/12.1sp1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0006_sopclgen/yysystem.ptf +Info: Running sopc_builder... +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0006_sopclgen --generate C:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0006_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +No .sopc_builder configuration file(!) +. +# 2014.02.13 11:58:04 (*) Success: sopc_builder finished. +Info: pio_led: "system" instantiated altera_avalon_pio "pio_led" +Info: Starting classic module elaboration. +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0007_sopclgen --no_splash --refresh C:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0007_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +Info: Finished elaborating classic module. +Executing: C:/altera/12.1sp1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0007_sopclgen/yysystem.ptf +Info: Running sopc_builder... +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0007_sopclgen --generate C:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0007_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +No .sopc_builder configuration file(!) +. +# 2014.02.13 11:58:08 (*) Success: sopc_builder finished. +Info: pio_key: "system" instantiated altera_avalon_pio "pio_key" +Info: Starting classic module elaboration. +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0008_sopclgen --no_splash --refresh C:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0008_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +Info: Finished elaborating classic module. +Executing: C:/altera/12.1sp1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0008_sopclgen/yysystem.ptf +Info: Running sopc_builder... +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0008_sopclgen --generate C:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0008_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +No .sopc_builder configuration file(!) +. +# 2014.02.13 11:58:12 (*) Success: sopc_builder finished. +Info: pio_sw: "system" instantiated altera_avalon_pio "pio_sw" +Info: Starting classic module elaboration. +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0009_sopclgen --no_splash --refresh C:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0009_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +Info: Finished elaborating classic module. +Executing: C:/altera/12.1sp1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0009_sopclgen/yysystem.ptf +Info: Running sopc_builder... +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0009_sopclgen --generate C:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0009_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +No .sopc_builder configuration file(!) +. +# 2014.02.13 11:58:17 (*) Success: sopc_builder finished. +Info: spi_0: "system" instantiated altera_avalon_spi "spi_0" +Info: Starting classic module elaboration. +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0010_sopclgen --no_splash --refresh C:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0010_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +Info: Finished elaborating classic module. +Executing: C:/altera/12.1sp1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0010_sopclgen/yysystem.ptf +Info: Running sopc_builder... +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0010_sopclgen --generate C:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0010_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +No .sopc_builder configuration file(!) +. +# 2014.02.13 11:58:21 (*) Success: sopc_builder finished. +Info: pio_ir: "system" instantiated altera_avalon_pio "pio_ir" +Info: cpu_instruction_master_translator: "system" instantiated altera_merlin_master_translator "cpu_instruction_master_translator" +Info: cpu_jtag_debug_module_translator: "system" instantiated altera_merlin_slave_translator "cpu_jtag_debug_module_translator" +Info: cpu_instruction_master_translator_avalon_universal_master_0_agent: "system" instantiated altera_merlin_master_agent "cpu_instruction_master_translator_avalon_universal_master_0_agent" +Info: cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent: "system" instantiated altera_merlin_slave_agent "cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent" +Info: cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo: "system" instantiated altera_avalon_sc_fifo "cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo" +Info: addr_router: "system" instantiated altera_merlin_router "addr_router" +Info: addr_router_001: "system" instantiated altera_merlin_router "addr_router_001" +Info: id_router: "system" instantiated altera_merlin_router "id_router" +Info: id_router_001: "system" instantiated altera_merlin_router "id_router_001" +Info: id_router_002: "system" instantiated altera_merlin_router "id_router_002" +Info: limiter: "system" instantiated altera_merlin_traffic_limiter "limiter" +Info: burst_adapter: "system" instantiated altera_merlin_burst_adapter "burst_adapter" +Info: rst_controller: "system" instantiated altera_reset_controller "rst_controller" +Info: cmd_xbar_demux: "system" instantiated altera_merlin_demultiplexer "cmd_xbar_demux" +Info: cmd_xbar_demux_001: "system" instantiated altera_merlin_demultiplexer "cmd_xbar_demux_001" +Info: cmd_xbar_mux: "system" instantiated altera_merlin_multiplexer "cmd_xbar_mux" +Info: rsp_xbar_demux: "system" instantiated altera_merlin_demultiplexer "rsp_xbar_demux" +Info: rsp_xbar_demux_002: "system" instantiated altera_merlin_demultiplexer "rsp_xbar_demux_002" +Info: rsp_xbar_mux: "system" instantiated altera_merlin_multiplexer "rsp_xbar_mux" +Info: Reusing file C:/Users/gongal/Desktop/DE0-nano-HD/system/synthesis/submodules/altera_merlin_arbitrator.sv +Info: rsp_xbar_mux_001: "system" instantiated altera_merlin_multiplexer "rsp_xbar_mux_001" +Info: Reusing file C:/Users/gongal/Desktop/DE0-nano-HD/system/synthesis/submodules/altera_merlin_arbitrator.sv +Info: width_adapter: "system" instantiated altera_merlin_width_adapter "width_adapter" +Info: Reusing file C:/Users/gongal/Desktop/DE0-nano-HD/system/synthesis/submodules/altera_merlin_burst_uncompressor.sv +Info: Reusing file C:/Users/gongal/Desktop/DE0-nano-HD/system/synthesis/submodules/altera_merlin_address_alignment.sv +Info: irq_mapper: "system" instantiated altera_irq_mapper "irq_mapper" +Info: system: Done system" with 33 modules, 116 files, 2360774 bytes +Info: ip-generate succeeded. +Info: Finished: Create HDL design files for synthesis diff --git a/MCTEST/DE0-nano-HD/system_generation_3.rpt b/MCTEST/DE0-nano-HD/system_generation_3.rpt new file mode 100644 index 00000000..1f37f564 --- /dev/null +++ b/MCTEST/DE0-nano-HD/system_generation_3.rpt @@ -0,0 +1,210 @@ +Info: Starting: Create block symbol file (.bsf) +Info: ip-generate --project-directory=C:/Users/gongal/Desktop/DE0-nano-HD/ --output-directory=C:/Users/gongal/Desktop/DE0-nano-HD/system/ --report-file=bsf:C:/Users/gongal/Desktop/DE0-nano-HD/system.bsf --system-info=DEVICE_FAMILY="Cyclone IV E" --system-info=DEVICE=EP4CE22F17C6 --system-info=DEVICE_SPEEDGRADE=6 --component-file=C:/Users/gongal/Desktop/DE0-nano-HD/system.qsys +Progress: Loading DE0-nano-HD/system.qsys +Progress: Reading input file +Progress: Adding clk_sys [clock_source 12.1] +Progress: Parameterizing module clk_sys +Progress: Adding cpu [altera_nios2_qsys 12.1] +Progress: Parameterizing module cpu +Progress: Adding sysid [altera_avalon_sysid_qsys 12.1] +Progress: Parameterizing module sysid +Progress: Adding sdram [altera_avalon_new_sdram_controller 12.1] +Progress: Parameterizing module sdram +Progress: Adding sys_clk_timer [altera_avalon_timer 12.1] +Progress: Parameterizing module sys_clk_timer +Progress: Adding uart_0 [altera_avalon_uart 12.1] +Progress: Parameterizing module uart_0 +Progress: Adding pio_led [altera_avalon_pio 12.1] +Progress: Parameterizing module pio_led +Progress: Adding pio_key [altera_avalon_pio 12.1] +Progress: Parameterizing module pio_key +Progress: Adding pio_sw [altera_avalon_pio 12.1] +Progress: Parameterizing module pio_sw +Progress: Adding spi_0 [altera_avalon_spi 12.1] +Progress: Parameterizing module spi_0 +Progress: Building connections +Progress: Parameterizing connections +Progress: Validating +Progress: Done reading input file +Info: system.sysid: System ID is not assigned automatically. Edit the System ID parameter to provide a unique ID +Info: system.sysid: Time stamp will be automatically updated when this component is generated. +Info: system.pio_key: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. +Info: system.pio_sw: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. +Info: ip-generate succeeded. +Info: Finished: Create block symbol file (.bsf) +Info: +Info: Starting: Create HDL design files for synthesis +Info: ip-generate --project-directory=C:/Users/gongal/Desktop/DE0-nano-HD/ --output-directory=C:/Users/gongal/Desktop/DE0-nano-HD/system/synthesis/ --file-set=QUARTUS_SYNTH --report-file=sopcinfo:C:/Users/gongal/Desktop/DE0-nano-HD/system.sopcinfo --report-file=html:C:/Users/gongal/Desktop/DE0-nano-HD/system.html --report-file=qip:C:/Users/gongal/Desktop/DE0-nano-HD/system/synthesis/system.qip --report-file=cmp:C:/Users/gongal/Desktop/DE0-nano-HD/system.cmp --system-info=DEVICE_FAMILY="Cyclone IV E" --system-info=DEVICE=EP4CE22F17C6 --system-info=DEVICE_SPEEDGRADE=6 --component-file=C:/Users/gongal/Desktop/DE0-nano-HD/system.qsys +Progress: Loading DE0-nano-HD/system.qsys +Progress: Reading input file +Progress: Adding clk_sys [clock_source 12.1] +Progress: Parameterizing module clk_sys +Progress: Adding cpu [altera_nios2_qsys 12.1] +Progress: Parameterizing module cpu +Progress: Adding sysid [altera_avalon_sysid_qsys 12.1] +Progress: Parameterizing module sysid +Progress: Adding sdram [altera_avalon_new_sdram_controller 12.1] +Progress: Parameterizing module sdram +Progress: Adding sys_clk_timer [altera_avalon_timer 12.1] +Progress: Parameterizing module sys_clk_timer +Progress: Adding uart_0 [altera_avalon_uart 12.1] +Progress: Parameterizing module uart_0 +Progress: Adding pio_led [altera_avalon_pio 12.1] +Progress: Parameterizing module pio_led +Progress: Adding pio_key [altera_avalon_pio 12.1] +Progress: Parameterizing module pio_key +Progress: Adding pio_sw [altera_avalon_pio 12.1] +Progress: Parameterizing module pio_sw +Progress: Adding spi_0 [altera_avalon_spi 12.1] +Progress: Parameterizing module spi_0 +Progress: Building connections +Progress: Parameterizing connections +Progress: Validating +Progress: Done reading input file +Info: system.sysid: System ID is not assigned automatically. Edit the System ID parameter to provide a unique ID +Info: system.sysid: Time stamp will be automatically updated when this component is generated. +Info: system.pio_key: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. +Info: system.pio_sw: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. +Info: system: Generating system "system" for QUARTUS_SYNTH +Info: pipeline_bridge_swap_transform: After transform: 10 modules, 41 connections +Info: No custom instruction connections, skipping transform +Info: merlin_translator_transform: After transform: 21 modules, 85 connections +Info: merlin_domain_transform: After transform: 42 modules, 227 connections +Info: merlin_router_transform: After transform: 53 modules, 271 connections +Info: merlin_traffic_limiter_transform: After transform: 55 modules, 281 connections +Info: merlin_burst_transform: After transform: 56 modules, 285 connections +Info: reset_adaptation_transform: After transform: 57 modules, 223 connections +Info: merlin_network_to_switch_transform: After transform: 78 modules, 267 connections +Info: merlin_width_transform: After transform: 80 modules, 273 connections +Info: limiter_update_transform: After transform: 80 modules, 275 connections +Info: merlin_interrupt_mapper_transform: After transform: 81 modules, 278 connections +Warning: system: "No matching role found for uart_0:s1:dataavailable (dataavailable)" +Warning: system: "No matching role found for uart_0:s1:readyfordata (readyfordata)" +Info: cpu: Starting RTL generation for module 'system_cpu' +Info: cpu: Generation command is [exec C:/altera/12.1sp1/quartus/../ip/altera/nios2_ip/altera_nios2/eperl.exe -I C:/altera/12.1sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/12.1sp1/quartus/sopc_builder/bin/europa -I C:/altera/12.1sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/12.1sp1/quartus/sopc_builder/bin -I C:/altera/12.1sp1/quartus/../ip/altera/nios2_ip/altera_nios2/cpu_lib -I C:/altera/12.1sp1/quartus/../ip/altera/nios2_ip/altera_nios2/nios_lib -I C:/altera/12.1sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -I C:/altera/12.1sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -- C:/altera/12.1sp1/quartus/../ip/altera/nios2_ip/altera_nios2/generate_rtl.epl --name=system_cpu --dir=C:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0025_cpu_gen/ --quartus_dir=C:/altera/12.1sp1/quartus --verilog --config=C:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0025_cpu_gen//system_cpu_processor_configuration.pl --do_build_sim=0 --bogus ] +Info: cpu: # 2014.02.13 12:02:14 (*) Starting Nios II generation +Info: cpu: # 2014.02.13 12:02:14 (*) Checking for plaintext license. +Info: cpu: # 2014.02.13 12:02:14 (*) Couldn't query license setup in Quartus directory C:/altera/12.1sp1/quartus +Info: cpu: # 2014.02.13 12:02:14 (*) Defaulting to contents of LM_LICENSE_FILE environment variable +Info: cpu: # 2014.02.13 12:02:14 (*) Plaintext license not found. +Info: cpu: # 2014.02.13 12:02:14 (*) Checking for encrypted license (non-evaluation). +Info: cpu: # 2014.02.13 12:02:15 (*) Couldn't query license setup in Quartus directory C:/altera/12.1sp1/quartus +Info: cpu: # 2014.02.13 12:02:15 (*) Defaulting to contents of LM_LICENSE_FILE environment variable +Info: cpu: # 2014.02.13 12:02:15 (*) Encrypted license found. SOF will not be time-limited. +Info: cpu: # 2014.02.13 12:02:15 (*) Elaborating CPU configuration settings +Info: cpu: # 2014.02.13 12:02:15 (*) Creating all objects for CPU +Info: cpu: # 2014.02.13 12:02:15 (*) Testbench +Info: cpu: # 2014.02.13 12:02:15 (*) Instruction decoding +Info: cpu: # 2014.02.13 12:02:15 (*) Instruction fields +Info: cpu: # 2014.02.13 12:02:15 (*) Instruction decodes +Info: cpu: # 2014.02.13 12:02:16 (*) Signals for RTL simulation waveforms +Info: cpu: # 2014.02.13 12:02:16 (*) Instruction controls +Info: cpu: # 2014.02.13 12:02:16 (*) Pipeline frontend +Info: cpu: # 2014.02.13 12:02:16 (*) Pipeline backend +Info: cpu: # 2014.02.13 12:02:18 (*) Generating RTL from CPU objects +Info: cpu: # 2014.02.13 12:02:21 (*) Creating encrypted RTL +Info: cpu: # 2014.02.13 12:02:23 (*) Done Nios II generation +Info: cpu: Done RTL generation for module 'system_cpu' +Info: cpu: "system" instantiated altera_nios2_qsys "cpu" +Info: sysid: "system" instantiated altera_avalon_sysid_qsys "sysid" +Info: Starting classic module elaboration. +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0027_sopclgen --no_splash --refresh C:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0027_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +Info: Finished elaborating classic module. +Executing: C:/altera/12.1sp1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0027_sopclgen/yysystem.ptf +Info: Running sopc_builder... +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0027_sopclgen --generate C:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0027_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +No .sopc_builder configuration file(!) +. +. +# 2014.02.13 12:02:27 (*) Running Test Generator Program for system_sdram +# 2014.02.13 12:02:28 (*) Success: sopc_builder finished. +Info: sdram: "system" instantiated altera_avalon_new_sdram_controller "sdram" +Info: Starting classic module elaboration. +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0028_sopclgen --no_splash --refresh C:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0028_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +Info: Finished elaborating classic module. +Executing: C:/altera/12.1sp1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0028_sopclgen/yysystem.ptf +Info: Running sopc_builder... +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0028_sopclgen --generate C:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0028_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +No .sopc_builder configuration file(!) +. +# 2014.02.13 12:02:32 (*) Success: sopc_builder finished. +Info: sys_clk_timer: "system" instantiated altera_avalon_timer "sys_clk_timer" +Info: Starting classic module elaboration. +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0029_sopclgen --no_splash --refresh C:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0029_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +Info: Finished elaborating classic module. +Executing: C:/altera/12.1sp1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0029_sopclgen/yysystem.ptf +Info: Running sopc_builder... +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0029_sopclgen --generate C:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0029_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +No .sopc_builder configuration file(!) +. +# 2014.02.13 12:02:37 (*) Success: sopc_builder finished. +Info: uart_0: "system" instantiated altera_avalon_uart "uart_0" +Info: Starting classic module elaboration. +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0030_sopclgen --no_splash --refresh C:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0030_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +Info: Finished elaborating classic module. +Executing: C:/altera/12.1sp1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0030_sopclgen/yysystem.ptf +Info: Running sopc_builder... +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0030_sopclgen --generate C:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0030_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +No .sopc_builder configuration file(!) +. +# 2014.02.13 12:02:41 (*) Success: sopc_builder finished. +Info: pio_led: "system" instantiated altera_avalon_pio "pio_led" +Info: Starting classic module elaboration. +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0031_sopclgen --no_splash --refresh C:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0031_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +Info: Finished elaborating classic module. +Executing: C:/altera/12.1sp1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0031_sopclgen/yysystem.ptf +Info: Running sopc_builder... +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0031_sopclgen --generate C:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0031_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +No .sopc_builder configuration file(!) +. +# 2014.02.13 12:02:45 (*) Success: sopc_builder finished. +Info: pio_key: "system" instantiated altera_avalon_pio "pio_key" +Info: Starting classic module elaboration. +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0032_sopclgen --no_splash --refresh C:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0032_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +Info: Finished elaborating classic module. +Executing: C:/altera/12.1sp1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0032_sopclgen/yysystem.ptf +Info: Running sopc_builder... +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0032_sopclgen --generate C:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0032_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +No .sopc_builder configuration file(!) +. +# 2014.02.13 12:02:49 (*) Success: sopc_builder finished. +Info: pio_sw: "system" instantiated altera_avalon_pio "pio_sw" +Info: Starting classic module elaboration. +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0033_sopclgen --no_splash --refresh C:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0033_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +Info: Finished elaborating classic module. +Executing: C:/altera/12.1sp1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0033_sopclgen/yysystem.ptf +Info: Running sopc_builder... +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0033_sopclgen --generate C:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0033_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +No .sopc_builder configuration file(!) +. +# 2014.02.13 12:02:54 (*) Success: sopc_builder finished. +Info: spi_0: "system" instantiated altera_avalon_spi "spi_0" +Info: cpu_instruction_master_translator: "system" instantiated altera_merlin_master_translator "cpu_instruction_master_translator" +Info: cpu_jtag_debug_module_translator: "system" instantiated altera_merlin_slave_translator "cpu_jtag_debug_module_translator" +Info: cpu_instruction_master_translator_avalon_universal_master_0_agent: "system" instantiated altera_merlin_master_agent "cpu_instruction_master_translator_avalon_universal_master_0_agent" +Info: cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent: "system" instantiated altera_merlin_slave_agent "cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent" +Info: cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo: "system" instantiated altera_avalon_sc_fifo "cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo" +Info: addr_router: "system" instantiated altera_merlin_router "addr_router" +Info: addr_router_001: "system" instantiated altera_merlin_router "addr_router_001" +Info: id_router: "system" instantiated altera_merlin_router "id_router" +Info: id_router_001: "system" instantiated altera_merlin_router "id_router_001" +Info: id_router_002: "system" instantiated altera_merlin_router "id_router_002" +Info: limiter: "system" instantiated altera_merlin_traffic_limiter "limiter" +Info: burst_adapter: "system" instantiated altera_merlin_burst_adapter "burst_adapter" +Info: rst_controller: "system" instantiated altera_reset_controller "rst_controller" +Info: cmd_xbar_demux: "system" instantiated altera_merlin_demultiplexer "cmd_xbar_demux" +Info: cmd_xbar_demux_001: "system" instantiated altera_merlin_demultiplexer "cmd_xbar_demux_001" +Info: cmd_xbar_mux: "system" instantiated altera_merlin_multiplexer "cmd_xbar_mux" +Info: rsp_xbar_demux: "system" instantiated altera_merlin_demultiplexer "rsp_xbar_demux" +Info: rsp_xbar_demux_002: "system" instantiated altera_merlin_demultiplexer "rsp_xbar_demux_002" +Info: rsp_xbar_mux: "system" instantiated altera_merlin_multiplexer "rsp_xbar_mux" +Info: Reusing file C:/Users/gongal/Desktop/DE0-nano-HD/system/synthesis/submodules/altera_merlin_arbitrator.sv +Info: rsp_xbar_mux_001: "system" instantiated altera_merlin_multiplexer "rsp_xbar_mux_001" +Info: Reusing file C:/Users/gongal/Desktop/DE0-nano-HD/system/synthesis/submodules/altera_merlin_arbitrator.sv +Info: width_adapter: "system" instantiated altera_merlin_width_adapter "width_adapter" +Info: Reusing file C:/Users/gongal/Desktop/DE0-nano-HD/system/synthesis/submodules/altera_merlin_burst_uncompressor.sv +Info: Reusing file C:/Users/gongal/Desktop/DE0-nano-HD/system/synthesis/submodules/altera_merlin_address_alignment.sv +Info: irq_mapper: "system" instantiated altera_irq_mapper "irq_mapper" +Info: system: Done system" with 32 modules, 109 files, 2229172 bytes +Info: ip-generate succeeded. +Info: Finished: Create HDL design files for synthesis diff --git a/MCTEST/DE0-nano-HD/system_generation_4.rpt b/MCTEST/DE0-nano-HD/system_generation_4.rpt new file mode 100644 index 00000000..4ec88ecd --- /dev/null +++ b/MCTEST/DE0-nano-HD/system_generation_4.rpt @@ -0,0 +1,196 @@ +Info: Starting: Create block symbol file (.bsf) +Info: ip-generate --project-directory=C:/Users/gongal/Desktop/DE0-nano-HD/ --output-directory=C:/Users/gongal/Desktop/DE0-nano-HD/system/ --report-file=bsf:C:/Users/gongal/Desktop/DE0-nano-HD/system.bsf --system-info=DEVICE_FAMILY="Cyclone IV E" --system-info=DEVICE=EP4CE22F17C6 --system-info=DEVICE_SPEEDGRADE=6 --component-file=C:/Users/gongal/Desktop/DE0-nano-HD/system.qsys +Progress: Loading DE0-nano-HD/system.qsys +Progress: Reading input file +Progress: Adding clk_sys [clock_source 12.1] +Progress: Parameterizing module clk_sys +Progress: Adding cpu [altera_nios2_qsys 12.1] +Progress: Parameterizing module cpu +Progress: Adding sysid [altera_avalon_sysid_qsys 12.1] +Progress: Parameterizing module sysid +Progress: Adding sdram [altera_avalon_new_sdram_controller 12.1] +Progress: Parameterizing module sdram +Progress: Adding sys_clk_timer [altera_avalon_timer 12.1] +Progress: Parameterizing module sys_clk_timer +Progress: Adding uart_0 [altera_avalon_uart 12.1] +Progress: Parameterizing module uart_0 +Progress: Adding pio_led [altera_avalon_pio 12.1] +Progress: Parameterizing module pio_led +Progress: Adding pio_key [altera_avalon_pio 12.1] +Progress: Parameterizing module pio_key +Progress: Adding pio_sw [altera_avalon_pio 12.1] +Progress: Parameterizing module pio_sw +Progress: Building connections +Progress: Parameterizing connections +Progress: Validating +Progress: Done reading input file +Info: system.sysid: System ID is not assigned automatically. Edit the System ID parameter to provide a unique ID +Info: system.sysid: Time stamp will be automatically updated when this component is generated. +Info: system.pio_key: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. +Info: system.pio_sw: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. +Info: ip-generate succeeded. +Info: Finished: Create block symbol file (.bsf) +Info: +Info: Starting: Create HDL design files for synthesis +Info: ip-generate --project-directory=C:/Users/gongal/Desktop/DE0-nano-HD/ --output-directory=C:/Users/gongal/Desktop/DE0-nano-HD/system/synthesis/ --file-set=QUARTUS_SYNTH --report-file=sopcinfo:C:/Users/gongal/Desktop/DE0-nano-HD/system.sopcinfo --report-file=html:C:/Users/gongal/Desktop/DE0-nano-HD/system.html --report-file=qip:C:/Users/gongal/Desktop/DE0-nano-HD/system/synthesis/system.qip --report-file=cmp:C:/Users/gongal/Desktop/DE0-nano-HD/system.cmp --system-info=DEVICE_FAMILY="Cyclone IV E" --system-info=DEVICE=EP4CE22F17C6 --system-info=DEVICE_SPEEDGRADE=6 --component-file=C:/Users/gongal/Desktop/DE0-nano-HD/system.qsys +Progress: Loading DE0-nano-HD/system.qsys +Progress: Reading input file +Progress: Adding clk_sys [clock_source 12.1] +Progress: Parameterizing module clk_sys +Progress: Adding cpu [altera_nios2_qsys 12.1] +Progress: Parameterizing module cpu +Progress: Adding sysid [altera_avalon_sysid_qsys 12.1] +Progress: Parameterizing module sysid +Progress: Adding sdram [altera_avalon_new_sdram_controller 12.1] +Progress: Parameterizing module sdram +Progress: Adding sys_clk_timer [altera_avalon_timer 12.1] +Progress: Parameterizing module sys_clk_timer +Progress: Adding uart_0 [altera_avalon_uart 12.1] +Progress: Parameterizing module uart_0 +Progress: Adding pio_led [altera_avalon_pio 12.1] +Progress: Parameterizing module pio_led +Progress: Adding pio_key [altera_avalon_pio 12.1] +Progress: Parameterizing module pio_key +Progress: Adding pio_sw [altera_avalon_pio 12.1] +Progress: Parameterizing module pio_sw +Progress: Building connections +Progress: Parameterizing connections +Progress: Validating +Progress: Done reading input file +Info: system.sysid: System ID is not assigned automatically. Edit the System ID parameter to provide a unique ID +Info: system.sysid: Time stamp will be automatically updated when this component is generated. +Info: system.pio_key: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. +Info: system.pio_sw: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. +Info: system: Generating system "system" for QUARTUS_SYNTH +Info: pipeline_bridge_swap_transform: After transform: 9 modules, 36 connections +Info: No custom instruction connections, skipping transform +Info: merlin_translator_transform: After transform: 19 modules, 76 connections +Info: merlin_domain_transform: After transform: 38 modules, 204 connections +Info: merlin_router_transform: After transform: 48 modules, 244 connections +Info: merlin_traffic_limiter_transform: After transform: 50 modules, 254 connections +Info: merlin_burst_transform: After transform: 51 modules, 258 connections +Info: reset_adaptation_transform: After transform: 52 modules, 202 connections +Info: merlin_network_to_switch_transform: After transform: 71 modules, 242 connections +Info: merlin_width_transform: After transform: 73 modules, 248 connections +Info: limiter_update_transform: After transform: 73 modules, 250 connections +Info: merlin_interrupt_mapper_transform: After transform: 74 modules, 253 connections +Warning: system: "No matching role found for uart_0:s1:dataavailable (dataavailable)" +Warning: system: "No matching role found for uart_0:s1:readyfordata (readyfordata)" +Info: cpu: Starting RTL generation for module 'system_cpu' +Info: cpu: Generation command is [exec C:/altera/12.1sp1/quartus/../ip/altera/nios2_ip/altera_nios2/eperl.exe -I C:/altera/12.1sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/12.1sp1/quartus/sopc_builder/bin/europa -I C:/altera/12.1sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/12.1sp1/quartus/sopc_builder/bin -I C:/altera/12.1sp1/quartus/../ip/altera/nios2_ip/altera_nios2/cpu_lib -I C:/altera/12.1sp1/quartus/../ip/altera/nios2_ip/altera_nios2/nios_lib -I C:/altera/12.1sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -I C:/altera/12.1sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -- C:/altera/12.1sp1/quartus/../ip/altera/nios2_ip/altera_nios2/generate_rtl.epl --name=system_cpu --dir=C:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0048_cpu_gen/ --quartus_dir=C:/altera/12.1sp1/quartus --verilog --config=C:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0048_cpu_gen//system_cpu_processor_configuration.pl --do_build_sim=0 --bogus ] +Info: cpu: # 2014.02.13 12:06:26 (*) Starting Nios II generation +Info: cpu: # 2014.02.13 12:06:26 (*) Checking for plaintext license. +Info: cpu: # 2014.02.13 12:06:26 (*) Couldn't query license setup in Quartus directory C:/altera/12.1sp1/quartus +Info: cpu: # 2014.02.13 12:06:26 (*) Defaulting to contents of LM_LICENSE_FILE environment variable +Info: cpu: # 2014.02.13 12:06:26 (*) Plaintext license not found. +Info: cpu: # 2014.02.13 12:06:26 (*) Checking for encrypted license (non-evaluation). +Info: cpu: # 2014.02.13 12:06:26 (*) Couldn't query license setup in Quartus directory C:/altera/12.1sp1/quartus +Info: cpu: # 2014.02.13 12:06:26 (*) Defaulting to contents of LM_LICENSE_FILE environment variable +Info: cpu: # 2014.02.13 12:06:26 (*) Encrypted license found. SOF will not be time-limited. +Info: cpu: # 2014.02.13 12:06:26 (*) Elaborating CPU configuration settings +Info: cpu: # 2014.02.13 12:06:27 (*) Creating all objects for CPU +Info: cpu: # 2014.02.13 12:06:27 (*) Testbench +Info: cpu: # 2014.02.13 12:06:27 (*) Instruction decoding +Info: cpu: # 2014.02.13 12:06:27 (*) Instruction fields +Info: cpu: # 2014.02.13 12:06:27 (*) Instruction decodes +Info: cpu: # 2014.02.13 12:06:27 (*) Signals for RTL simulation waveforms +Info: cpu: # 2014.02.13 12:06:27 (*) Instruction controls +Info: cpu: # 2014.02.13 12:06:27 (*) Pipeline frontend +Info: cpu: # 2014.02.13 12:06:27 (*) Pipeline backend +Info: cpu: # 2014.02.13 12:06:30 (*) Generating RTL from CPU objects +Info: cpu: # 2014.02.13 12:06:33 (*) Creating encrypted RTL +Info: cpu: # 2014.02.13 12:06:34 (*) Done Nios II generation +Info: cpu: Done RTL generation for module 'system_cpu' +Info: cpu: "system" instantiated altera_nios2_qsys "cpu" +Info: sysid: "system" instantiated altera_avalon_sysid_qsys "sysid" +Info: Starting classic module elaboration. +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0050_sopclgen --no_splash --refresh C:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0050_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +Info: Finished elaborating classic module. +Executing: C:/altera/12.1sp1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0050_sopclgen/yysystem.ptf +Info: Running sopc_builder... +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0050_sopclgen --generate C:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0050_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +No .sopc_builder configuration file(!) +. +. +# 2014.02.13 12:06:38 (*) Running Test Generator Program for system_sdram +# 2014.02.13 12:06:39 (*) Success: sopc_builder finished. +Info: sdram: "system" instantiated altera_avalon_new_sdram_controller "sdram" +Info: Starting classic module elaboration. +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0051_sopclgen --no_splash --refresh C:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0051_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +Info: Finished elaborating classic module. +Executing: C:/altera/12.1sp1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0051_sopclgen/yysystem.ptf +Info: Running sopc_builder... +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0051_sopclgen --generate C:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0051_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +No .sopc_builder configuration file(!) +. +# 2014.02.13 12:06:44 (*) Success: sopc_builder finished. +Info: sys_clk_timer: "system" instantiated altera_avalon_timer "sys_clk_timer" +Info: Starting classic module elaboration. +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0052_sopclgen --no_splash --refresh C:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0052_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +Info: Finished elaborating classic module. +Executing: C:/altera/12.1sp1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0052_sopclgen/yysystem.ptf +Info: Running sopc_builder... +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0052_sopclgen --generate C:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0052_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +No .sopc_builder configuration file(!) +. +# 2014.02.13 12:06:48 (*) Success: sopc_builder finished. +Info: uart_0: "system" instantiated altera_avalon_uart "uart_0" +Info: Starting classic module elaboration. +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0053_sopclgen --no_splash --refresh C:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0053_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +Info: Finished elaborating classic module. +Executing: C:/altera/12.1sp1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0053_sopclgen/yysystem.ptf +Info: Running sopc_builder... +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0053_sopclgen --generate C:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0053_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +No .sopc_builder configuration file(!) +. +# 2014.02.13 12:06:53 (*) Success: sopc_builder finished. +Info: pio_led: "system" instantiated altera_avalon_pio "pio_led" +Info: Starting classic module elaboration. +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0054_sopclgen --no_splash --refresh C:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0054_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +Info: Finished elaborating classic module. +Executing: C:/altera/12.1sp1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0054_sopclgen/yysystem.ptf +Info: Running sopc_builder... +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0054_sopclgen --generate C:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0054_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +No .sopc_builder configuration file(!) +. +# 2014.02.13 12:06:57 (*) Success: sopc_builder finished. +Info: pio_key: "system" instantiated altera_avalon_pio "pio_key" +Info: Starting classic module elaboration. +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0055_sopclgen --no_splash --refresh C:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0055_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +Info: Finished elaborating classic module. +Executing: C:/altera/12.1sp1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0055_sopclgen/yysystem.ptf +Info: Running sopc_builder... +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0055_sopclgen --generate C:/Users/gongal/AppData/Local/Temp/alt6114_4841038665180270986.dir/0055_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +No .sopc_builder configuration file(!) +. +# 2014.02.13 12:07:02 (*) Success: sopc_builder finished. +Info: pio_sw: "system" instantiated altera_avalon_pio "pio_sw" +Info: cpu_instruction_master_translator: "system" instantiated altera_merlin_master_translator "cpu_instruction_master_translator" +Info: cpu_jtag_debug_module_translator: "system" instantiated altera_merlin_slave_translator "cpu_jtag_debug_module_translator" +Info: cpu_instruction_master_translator_avalon_universal_master_0_agent: "system" instantiated altera_merlin_master_agent "cpu_instruction_master_translator_avalon_universal_master_0_agent" +Info: cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent: "system" instantiated altera_merlin_slave_agent "cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent" +Info: cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo: "system" instantiated altera_avalon_sc_fifo "cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo" +Info: addr_router: "system" instantiated altera_merlin_router "addr_router" +Info: addr_router_001: "system" instantiated altera_merlin_router "addr_router_001" +Info: id_router: "system" instantiated altera_merlin_router "id_router" +Info: id_router_001: "system" instantiated altera_merlin_router "id_router_001" +Info: id_router_002: "system" instantiated altera_merlin_router "id_router_002" +Info: limiter: "system" instantiated altera_merlin_traffic_limiter "limiter" +Info: burst_adapter: "system" instantiated altera_merlin_burst_adapter "burst_adapter" +Info: rst_controller: "system" instantiated altera_reset_controller "rst_controller" +Info: cmd_xbar_demux: "system" instantiated altera_merlin_demultiplexer "cmd_xbar_demux" +Info: cmd_xbar_demux_001: "system" instantiated altera_merlin_demultiplexer "cmd_xbar_demux_001" +Info: cmd_xbar_mux: "system" instantiated altera_merlin_multiplexer "cmd_xbar_mux" +Info: rsp_xbar_demux: "system" instantiated altera_merlin_demultiplexer "rsp_xbar_demux" +Info: rsp_xbar_demux_002: "system" instantiated altera_merlin_demultiplexer "rsp_xbar_demux_002" +Info: rsp_xbar_mux: "system" instantiated altera_merlin_multiplexer "rsp_xbar_mux" +Info: Reusing file C:/Users/gongal/Desktop/DE0-nano-HD/system/synthesis/submodules/altera_merlin_arbitrator.sv +Info: rsp_xbar_mux_001: "system" instantiated altera_merlin_multiplexer "rsp_xbar_mux_001" +Info: Reusing file C:/Users/gongal/Desktop/DE0-nano-HD/system/synthesis/submodules/altera_merlin_arbitrator.sv +Info: width_adapter: "system" instantiated altera_merlin_width_adapter "width_adapter" +Info: Reusing file C:/Users/gongal/Desktop/DE0-nano-HD/system/synthesis/submodules/altera_merlin_burst_uncompressor.sv +Info: Reusing file C:/Users/gongal/Desktop/DE0-nano-HD/system/synthesis/submodules/altera_merlin_address_alignment.sv +Info: irq_mapper: "system" instantiated altera_irq_mapper "irq_mapper" +Info: system: Done system" with 31 modules, 102 files, 2084511 bytes +Info: ip-generate succeeded. +Info: Finished: Create HDL design files for synthesis diff --git a/MCTEST/DE0-nano-HD/system_generation_5.rpt b/MCTEST/DE0-nano-HD/system_generation_5.rpt new file mode 100644 index 00000000..2f3f0ccd --- /dev/null +++ b/MCTEST/DE0-nano-HD/system_generation_5.rpt @@ -0,0 +1,196 @@ +Info: Starting: Create block symbol file (.bsf) +Info: ip-generate --project-directory=C:/Users/gongal/Desktop/DE0-nano-HD/ --output-directory=C:/Users/gongal/Desktop/DE0-nano-HD/system/ --report-file=bsf:C:/Users/gongal/Desktop/DE0-nano-HD/system.bsf --system-info=DEVICE_FAMILY="Cyclone IV E" --system-info=DEVICE=EP4CE22F17C6 --system-info=DEVICE_SPEEDGRADE=6 --component-file=C:/Users/gongal/Desktop/DE0-nano-HD/system.qsys +Progress: Loading DE0-nano-HD/system.qsys +Progress: Reading input file +Progress: Adding clk_sys [clock_source 12.1] +Progress: Parameterizing module clk_sys +Progress: Adding cpu [altera_nios2_qsys 12.1] +Progress: Parameterizing module cpu +Progress: Adding sysid [altera_avalon_sysid_qsys 12.1] +Progress: Parameterizing module sysid +Progress: Adding sdram [altera_avalon_new_sdram_controller 12.1] +Progress: Parameterizing module sdram +Progress: Adding sys_clk_timer [altera_avalon_timer 12.1] +Progress: Parameterizing module sys_clk_timer +Progress: Adding uart_0 [altera_avalon_uart 12.1] +Progress: Parameterizing module uart_0 +Progress: Adding pio_led [altera_avalon_pio 12.1] +Progress: Parameterizing module pio_led +Progress: Adding pio_key [altera_avalon_pio 12.1] +Progress: Parameterizing module pio_key +Progress: Adding pio_sw [altera_avalon_pio 12.1] +Progress: Parameterizing module pio_sw +Progress: Building connections +Progress: Parameterizing connections +Progress: Validating +Progress: Done reading input file +Info: system.sysid: System ID is not assigned automatically. Edit the System ID parameter to provide a unique ID +Info: system.sysid: Time stamp will be automatically updated when this component is generated. +Info: system.pio_key: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. +Info: system.pio_sw: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. +Info: ip-generate succeeded. +Info: Finished: Create block symbol file (.bsf) +Info: +Info: Starting: Create HDL design files for synthesis +Info: ip-generate --project-directory=C:/Users/gongal/Desktop/DE0-nano-HD/ --output-directory=C:/Users/gongal/Desktop/DE0-nano-HD/system/synthesis/ --file-set=QUARTUS_SYNTH --report-file=sopcinfo:C:/Users/gongal/Desktop/DE0-nano-HD/system.sopcinfo --report-file=html:C:/Users/gongal/Desktop/DE0-nano-HD/system.html --report-file=qip:C:/Users/gongal/Desktop/DE0-nano-HD/system/synthesis/system.qip --report-file=cmp:C:/Users/gongal/Desktop/DE0-nano-HD/system.cmp --system-info=DEVICE_FAMILY="Cyclone IV E" --system-info=DEVICE=EP4CE22F17C6 --system-info=DEVICE_SPEEDGRADE=6 --component-file=C:/Users/gongal/Desktop/DE0-nano-HD/system.qsys +Progress: Loading DE0-nano-HD/system.qsys +Progress: Reading input file +Progress: Adding clk_sys [clock_source 12.1] +Progress: Parameterizing module clk_sys +Progress: Adding cpu [altera_nios2_qsys 12.1] +Progress: Parameterizing module cpu +Progress: Adding sysid [altera_avalon_sysid_qsys 12.1] +Progress: Parameterizing module sysid +Progress: Adding sdram [altera_avalon_new_sdram_controller 12.1] +Progress: Parameterizing module sdram +Progress: Adding sys_clk_timer [altera_avalon_timer 12.1] +Progress: Parameterizing module sys_clk_timer +Progress: Adding uart_0 [altera_avalon_uart 12.1] +Progress: Parameterizing module uart_0 +Progress: Adding pio_led [altera_avalon_pio 12.1] +Progress: Parameterizing module pio_led +Progress: Adding pio_key [altera_avalon_pio 12.1] +Progress: Parameterizing module pio_key +Progress: Adding pio_sw [altera_avalon_pio 12.1] +Progress: Parameterizing module pio_sw +Progress: Building connections +Progress: Parameterizing connections +Progress: Validating +Progress: Done reading input file +Info: system.sysid: System ID is not assigned automatically. Edit the System ID parameter to provide a unique ID +Info: system.sysid: Time stamp will be automatically updated when this component is generated. +Info: system.pio_key: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. +Info: system.pio_sw: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. +Info: system: Generating system "system" for QUARTUS_SYNTH +Info: pipeline_bridge_swap_transform: After transform: 9 modules, 36 connections +Info: No custom instruction connections, skipping transform +Info: merlin_translator_transform: After transform: 19 modules, 76 connections +Info: merlin_domain_transform: After transform: 38 modules, 204 connections +Info: merlin_router_transform: After transform: 48 modules, 244 connections +Info: merlin_traffic_limiter_transform: After transform: 50 modules, 254 connections +Info: merlin_burst_transform: After transform: 51 modules, 258 connections +Info: reset_adaptation_transform: After transform: 52 modules, 202 connections +Info: merlin_network_to_switch_transform: After transform: 71 modules, 242 connections +Info: merlin_width_transform: After transform: 73 modules, 248 connections +Info: limiter_update_transform: After transform: 73 modules, 250 connections +Info: merlin_interrupt_mapper_transform: After transform: 74 modules, 253 connections +Warning: system: "No matching role found for uart_0:s1:dataavailable (dataavailable)" +Warning: system: "No matching role found for uart_0:s1:readyfordata (readyfordata)" +Info: cpu: Starting RTL generation for module 'system_cpu' +Info: cpu: Generation command is [exec C:/altera/12.1sp1/quartus/../ip/altera/nios2_ip/altera_nios2/eperl.exe -I C:/altera/12.1sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/12.1sp1/quartus/sopc_builder/bin/europa -I C:/altera/12.1sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/12.1sp1/quartus/sopc_builder/bin -I C:/altera/12.1sp1/quartus/../ip/altera/nios2_ip/altera_nios2/cpu_lib -I C:/altera/12.1sp1/quartus/../ip/altera/nios2_ip/altera_nios2/nios_lib -I C:/altera/12.1sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -I C:/altera/12.1sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -- C:/altera/12.1sp1/quartus/../ip/altera/nios2_ip/altera_nios2/generate_rtl.epl --name=system_cpu --dir=C:/Users/gongal/AppData/Local/Temp/alt6114_259841681406451450.dir/0001_cpu_gen/ --quartus_dir=C:/altera/12.1sp1/quartus --verilog --config=C:/Users/gongal/AppData/Local/Temp/alt6114_259841681406451450.dir/0001_cpu_gen//system_cpu_processor_configuration.pl --do_build_sim=0 --bogus ] +Info: cpu: # 2014.02.13 13:33:01 (*) Starting Nios II generation +Info: cpu: # 2014.02.13 13:33:01 (*) Checking for plaintext license. +Info: cpu: # 2014.02.13 13:33:01 (*) Couldn't query license setup in Quartus directory C:/altera/12.1sp1/quartus +Info: cpu: # 2014.02.13 13:33:01 (*) Defaulting to contents of LM_LICENSE_FILE environment variable +Info: cpu: # 2014.02.13 13:33:01 (*) Plaintext license not found. +Info: cpu: # 2014.02.13 13:33:01 (*) Checking for encrypted license (non-evaluation). +Info: cpu: # 2014.02.13 13:33:01 (*) Couldn't query license setup in Quartus directory C:/altera/12.1sp1/quartus +Info: cpu: # 2014.02.13 13:33:01 (*) Defaulting to contents of LM_LICENSE_FILE environment variable +Info: cpu: # 2014.02.13 13:33:02 (*) Encrypted license found. SOF will not be time-limited. +Info: cpu: # 2014.02.13 13:33:02 (*) Elaborating CPU configuration settings +Info: cpu: # 2014.02.13 13:33:02 (*) Creating all objects for CPU +Info: cpu: # 2014.02.13 13:33:02 (*) Testbench +Info: cpu: # 2014.02.13 13:33:02 (*) Instruction decoding +Info: cpu: # 2014.02.13 13:33:02 (*) Instruction fields +Info: cpu: # 2014.02.13 13:33:02 (*) Instruction decodes +Info: cpu: # 2014.02.13 13:33:02 (*) Signals for RTL simulation waveforms +Info: cpu: # 2014.02.13 13:33:03 (*) Instruction controls +Info: cpu: # 2014.02.13 13:33:03 (*) Pipeline frontend +Info: cpu: # 2014.02.13 13:33:03 (*) Pipeline backend +Info: cpu: # 2014.02.13 13:33:05 (*) Generating RTL from CPU objects +Info: cpu: # 2014.02.13 13:33:08 (*) Creating encrypted RTL +Info: cpu: # 2014.02.13 13:33:09 (*) Done Nios II generation +Info: cpu: Done RTL generation for module 'system_cpu' +Info: cpu: "system" instantiated altera_nios2_qsys "cpu" +Info: sysid: "system" instantiated altera_avalon_sysid_qsys "sysid" +Info: Starting classic module elaboration. +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_259841681406451450.dir/0003_sopclgen --no_splash --refresh C:/Users/gongal/AppData/Local/Temp/alt6114_259841681406451450.dir/0003_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +Info: Finished elaborating classic module. +Executing: C:/altera/12.1sp1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/Users/gongal/AppData/Local/Temp/alt6114_259841681406451450.dir/0003_sopclgen/yysystem.ptf +Info: Running sopc_builder... +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_259841681406451450.dir/0003_sopclgen --generate C:/Users/gongal/AppData/Local/Temp/alt6114_259841681406451450.dir/0003_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +No .sopc_builder configuration file(!) +. +. +# 2014.02.13 13:33:14 (*) Running Test Generator Program for system_sdram +# 2014.02.13 13:33:15 (*) Success: sopc_builder finished. +Info: sdram: "system" instantiated altera_avalon_new_sdram_controller "sdram" +Info: Starting classic module elaboration. +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_259841681406451450.dir/0004_sopclgen --no_splash --refresh C:/Users/gongal/AppData/Local/Temp/alt6114_259841681406451450.dir/0004_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +Info: Finished elaborating classic module. +Executing: C:/altera/12.1sp1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/Users/gongal/AppData/Local/Temp/alt6114_259841681406451450.dir/0004_sopclgen/yysystem.ptf +Info: Running sopc_builder... +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_259841681406451450.dir/0004_sopclgen --generate C:/Users/gongal/AppData/Local/Temp/alt6114_259841681406451450.dir/0004_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +No .sopc_builder configuration file(!) +. +# 2014.02.13 13:33:19 (*) Success: sopc_builder finished. +Info: sys_clk_timer: "system" instantiated altera_avalon_timer "sys_clk_timer" +Info: Starting classic module elaboration. +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_259841681406451450.dir/0005_sopclgen --no_splash --refresh C:/Users/gongal/AppData/Local/Temp/alt6114_259841681406451450.dir/0005_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +Info: Finished elaborating classic module. +Executing: C:/altera/12.1sp1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/Users/gongal/AppData/Local/Temp/alt6114_259841681406451450.dir/0005_sopclgen/yysystem.ptf +Info: Running sopc_builder... +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_259841681406451450.dir/0005_sopclgen --generate C:/Users/gongal/AppData/Local/Temp/alt6114_259841681406451450.dir/0005_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +No .sopc_builder configuration file(!) +. +# 2014.02.13 13:33:24 (*) Success: sopc_builder finished. +Info: uart_0: "system" instantiated altera_avalon_uart "uart_0" +Info: Starting classic module elaboration. +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_259841681406451450.dir/0006_sopclgen --no_splash --refresh C:/Users/gongal/AppData/Local/Temp/alt6114_259841681406451450.dir/0006_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +Info: Finished elaborating classic module. +Executing: C:/altera/12.1sp1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/Users/gongal/AppData/Local/Temp/alt6114_259841681406451450.dir/0006_sopclgen/yysystem.ptf +Info: Running sopc_builder... +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_259841681406451450.dir/0006_sopclgen --generate C:/Users/gongal/AppData/Local/Temp/alt6114_259841681406451450.dir/0006_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +No .sopc_builder configuration file(!) +. +# 2014.02.13 13:33:28 (*) Success: sopc_builder finished. +Info: pio_led: "system" instantiated altera_avalon_pio "pio_led" +Info: Starting classic module elaboration. +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_259841681406451450.dir/0007_sopclgen --no_splash --refresh C:/Users/gongal/AppData/Local/Temp/alt6114_259841681406451450.dir/0007_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +Info: Finished elaborating classic module. +Executing: C:/altera/12.1sp1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/Users/gongal/AppData/Local/Temp/alt6114_259841681406451450.dir/0007_sopclgen/yysystem.ptf +Info: Running sopc_builder... +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_259841681406451450.dir/0007_sopclgen --generate C:/Users/gongal/AppData/Local/Temp/alt6114_259841681406451450.dir/0007_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +No .sopc_builder configuration file(!) +. +# 2014.02.13 13:33:32 (*) Success: sopc_builder finished. +Info: pio_key: "system" instantiated altera_avalon_pio "pio_key" +Info: Starting classic module elaboration. +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_259841681406451450.dir/0008_sopclgen --no_splash --refresh C:/Users/gongal/AppData/Local/Temp/alt6114_259841681406451450.dir/0008_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +Info: Finished elaborating classic module. +Executing: C:/altera/12.1sp1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/Users/gongal/AppData/Local/Temp/alt6114_259841681406451450.dir/0008_sopclgen/yysystem.ptf +Info: Running sopc_builder... +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_259841681406451450.dir/0008_sopclgen --generate C:/Users/gongal/AppData/Local/Temp/alt6114_259841681406451450.dir/0008_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +No .sopc_builder configuration file(!) +. +# 2014.02.13 13:33:36 (*) Success: sopc_builder finished. +Info: pio_sw: "system" instantiated altera_avalon_pio "pio_sw" +Info: cpu_instruction_master_translator: "system" instantiated altera_merlin_master_translator "cpu_instruction_master_translator" +Info: cpu_jtag_debug_module_translator: "system" instantiated altera_merlin_slave_translator "cpu_jtag_debug_module_translator" +Info: cpu_instruction_master_translator_avalon_universal_master_0_agent: "system" instantiated altera_merlin_master_agent "cpu_instruction_master_translator_avalon_universal_master_0_agent" +Info: cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent: "system" instantiated altera_merlin_slave_agent "cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent" +Info: cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo: "system" instantiated altera_avalon_sc_fifo "cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo" +Info: addr_router: "system" instantiated altera_merlin_router "addr_router" +Info: addr_router_001: "system" instantiated altera_merlin_router "addr_router_001" +Info: id_router: "system" instantiated altera_merlin_router "id_router" +Info: id_router_001: "system" instantiated altera_merlin_router "id_router_001" +Info: id_router_002: "system" instantiated altera_merlin_router "id_router_002" +Info: limiter: "system" instantiated altera_merlin_traffic_limiter "limiter" +Info: burst_adapter: "system" instantiated altera_merlin_burst_adapter "burst_adapter" +Info: rst_controller: "system" instantiated altera_reset_controller "rst_controller" +Info: cmd_xbar_demux: "system" instantiated altera_merlin_demultiplexer "cmd_xbar_demux" +Info: cmd_xbar_demux_001: "system" instantiated altera_merlin_demultiplexer "cmd_xbar_demux_001" +Info: cmd_xbar_mux: "system" instantiated altera_merlin_multiplexer "cmd_xbar_mux" +Info: rsp_xbar_demux: "system" instantiated altera_merlin_demultiplexer "rsp_xbar_demux" +Info: rsp_xbar_demux_002: "system" instantiated altera_merlin_demultiplexer "rsp_xbar_demux_002" +Info: rsp_xbar_mux: "system" instantiated altera_merlin_multiplexer "rsp_xbar_mux" +Info: Reusing file C:/Users/gongal/Desktop/DE0-nano-HD/system/synthesis/submodules/altera_merlin_arbitrator.sv +Info: rsp_xbar_mux_001: "system" instantiated altera_merlin_multiplexer "rsp_xbar_mux_001" +Info: Reusing file C:/Users/gongal/Desktop/DE0-nano-HD/system/synthesis/submodules/altera_merlin_arbitrator.sv +Info: width_adapter: "system" instantiated altera_merlin_width_adapter "width_adapter" +Info: Reusing file C:/Users/gongal/Desktop/DE0-nano-HD/system/synthesis/submodules/altera_merlin_burst_uncompressor.sv +Info: Reusing file C:/Users/gongal/Desktop/DE0-nano-HD/system/synthesis/submodules/altera_merlin_address_alignment.sv +Info: irq_mapper: "system" instantiated altera_irq_mapper "irq_mapper" +Info: system: Done system" with 31 modules, 102 files, 2084511 bytes +Info: ip-generate succeeded. +Info: Finished: Create HDL design files for synthesis diff --git a/MCTEST/DE0-nano-HD/system_generation_6.rpt b/MCTEST/DE0-nano-HD/system_generation_6.rpt new file mode 100644 index 00000000..a8a56b57 --- /dev/null +++ b/MCTEST/DE0-nano-HD/system_generation_6.rpt @@ -0,0 +1,210 @@ +Info: Starting: Create block symbol file (.bsf) +Info: ip-generate --project-directory=C:/Users/gongal/Desktop/DE0-nano-HD/ --output-directory=C:/Users/gongal/Desktop/DE0-nano-HD/system/ --report-file=bsf:C:/Users/gongal/Desktop/DE0-nano-HD/system.bsf --system-info=DEVICE_FAMILY="Cyclone IV E" --system-info=DEVICE=EP4CE22F17C6 --system-info=DEVICE_SPEEDGRADE=6 --component-file=C:/Users/gongal/Desktop/DE0-nano-HD/system.qsys +Progress: Loading DE0-nano-HD/system.qsys +Progress: Reading input file +Progress: Adding clk_sys [clock_source 12.1] +Progress: Parameterizing module clk_sys +Progress: Adding cpu [altera_nios2_qsys 12.1] +Progress: Parameterizing module cpu +Progress: Adding sysid [altera_avalon_sysid_qsys 12.1] +Progress: Parameterizing module sysid +Progress: Adding sdram [altera_avalon_new_sdram_controller 12.1] +Progress: Parameterizing module sdram +Progress: Adding sys_clk_timer [altera_avalon_timer 12.1] +Progress: Parameterizing module sys_clk_timer +Progress: Adding uart_0 [altera_avalon_uart 12.1] +Progress: Parameterizing module uart_0 +Progress: Adding pio_led [altera_avalon_pio 12.1] +Progress: Parameterizing module pio_led +Progress: Adding pio_key [altera_avalon_pio 12.1] +Progress: Parameterizing module pio_key +Progress: Adding pio_sw [altera_avalon_pio 12.1] +Progress: Parameterizing module pio_sw +Progress: Adding jtag_uart_0 [altera_avalon_jtag_uart 12.1] +Progress: Parameterizing module jtag_uart_0 +Progress: Building connections +Progress: Parameterizing connections +Progress: Validating +Progress: Done reading input file +Info: system.sysid: System ID is not assigned automatically. Edit the System ID parameter to provide a unique ID +Info: system.sysid: Time stamp will be automatically updated when this component is generated. +Info: system.pio_key: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. +Info: system.pio_sw: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. +Info: ip-generate succeeded. +Info: Finished: Create block symbol file (.bsf) +Info: +Info: Starting: Create HDL design files for synthesis +Info: ip-generate --project-directory=C:/Users/gongal/Desktop/DE0-nano-HD/ --output-directory=C:/Users/gongal/Desktop/DE0-nano-HD/system/synthesis/ --file-set=QUARTUS_SYNTH --report-file=sopcinfo:C:/Users/gongal/Desktop/DE0-nano-HD/system.sopcinfo --report-file=html:C:/Users/gongal/Desktop/DE0-nano-HD/system.html --report-file=qip:C:/Users/gongal/Desktop/DE0-nano-HD/system/synthesis/system.qip --report-file=cmp:C:/Users/gongal/Desktop/DE0-nano-HD/system.cmp --system-info=DEVICE_FAMILY="Cyclone IV E" --system-info=DEVICE=EP4CE22F17C6 --system-info=DEVICE_SPEEDGRADE=6 --component-file=C:/Users/gongal/Desktop/DE0-nano-HD/system.qsys +Progress: Loading DE0-nano-HD/system.qsys +Progress: Reading input file +Progress: Adding clk_sys [clock_source 12.1] +Progress: Parameterizing module clk_sys +Progress: Adding cpu [altera_nios2_qsys 12.1] +Progress: Parameterizing module cpu +Progress: Adding sysid [altera_avalon_sysid_qsys 12.1] +Progress: Parameterizing module sysid +Progress: Adding sdram [altera_avalon_new_sdram_controller 12.1] +Progress: Parameterizing module sdram +Progress: Adding sys_clk_timer [altera_avalon_timer 12.1] +Progress: Parameterizing module sys_clk_timer +Progress: Adding uart_0 [altera_avalon_uart 12.1] +Progress: Parameterizing module uart_0 +Progress: Adding pio_led [altera_avalon_pio 12.1] +Progress: Parameterizing module pio_led +Progress: Adding pio_key [altera_avalon_pio 12.1] +Progress: Parameterizing module pio_key +Progress: Adding pio_sw [altera_avalon_pio 12.1] +Progress: Parameterizing module pio_sw +Progress: Adding jtag_uart_0 [altera_avalon_jtag_uart 12.1] +Progress: Parameterizing module jtag_uart_0 +Progress: Building connections +Progress: Parameterizing connections +Progress: Validating +Progress: Done reading input file +Info: system.sysid: System ID is not assigned automatically. Edit the System ID parameter to provide a unique ID +Info: system.sysid: Time stamp will be automatically updated when this component is generated. +Info: system.pio_key: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. +Info: system.pio_sw: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. +Info: system: Generating system "system" for QUARTUS_SYNTH +Info: pipeline_bridge_swap_transform: After transform: 10 modules, 40 connections +Info: No custom instruction connections, skipping transform +Info: merlin_translator_transform: After transform: 21 modules, 83 connections +Info: merlin_domain_transform: After transform: 42 modules, 222 connections +Info: merlin_router_transform: After transform: 53 modules, 265 connections +Info: merlin_traffic_limiter_transform: After transform: 55 modules, 275 connections +Info: merlin_burst_transform: After transform: 56 modules, 279 connections +Info: reset_adaptation_transform: After transform: 57 modules, 223 connections +Info: merlin_network_to_switch_transform: After transform: 78 modules, 267 connections +Info: merlin_width_transform: After transform: 80 modules, 273 connections +Info: limiter_update_transform: After transform: 80 modules, 275 connections +Info: merlin_interrupt_mapper_transform: After transform: 81 modules, 278 connections +Warning: system: "No matching role found for uart_0:s1:dataavailable (dataavailable)" +Warning: system: "No matching role found for uart_0:s1:readyfordata (readyfordata)" +Info: cpu: Starting RTL generation for module 'system_cpu' +Info: cpu: Generation command is [exec C:/altera/12.1sp1/quartus/../ip/altera/nios2_ip/altera_nios2/eperl.exe -I C:/altera/12.1sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/12.1sp1/quartus/sopc_builder/bin/europa -I C:/altera/12.1sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/12.1sp1/quartus/sopc_builder/bin -I C:/altera/12.1sp1/quartus/../ip/altera/nios2_ip/altera_nios2/cpu_lib -I C:/altera/12.1sp1/quartus/../ip/altera/nios2_ip/altera_nios2/nios_lib -I C:/altera/12.1sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -I C:/altera/12.1sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -- C:/altera/12.1sp1/quartus/../ip/altera/nios2_ip/altera_nios2/generate_rtl.epl --name=system_cpu --dir=C:/Users/gongal/AppData/Local/Temp/alt6114_4257823588356694759.dir/0001_cpu_gen/ --quartus_dir=C:/altera/12.1sp1/quartus --verilog --config=C:/Users/gongal/AppData/Local/Temp/alt6114_4257823588356694759.dir/0001_cpu_gen//system_cpu_processor_configuration.pl --do_build_sim=0 --bogus ] +Info: cpu: # 2014.02.13 14:14:15 (*) Starting Nios II generation +Info: cpu: # 2014.02.13 14:14:15 (*) Checking for plaintext license. +Info: cpu: # 2014.02.13 14:14:15 (*) Couldn't query license setup in Quartus directory C:/altera/12.1sp1/quartus +Info: cpu: # 2014.02.13 14:14:15 (*) Defaulting to contents of LM_LICENSE_FILE environment variable +Info: cpu: # 2014.02.13 14:14:15 (*) Plaintext license not found. +Info: cpu: # 2014.02.13 14:14:15 (*) Checking for encrypted license (non-evaluation). +Info: cpu: # 2014.02.13 14:14:16 (*) Couldn't query license setup in Quartus directory C:/altera/12.1sp1/quartus +Info: cpu: # 2014.02.13 14:14:16 (*) Defaulting to contents of LM_LICENSE_FILE environment variable +Info: cpu: # 2014.02.13 14:14:16 (*) Encrypted license found. SOF will not be time-limited. +Info: cpu: # 2014.02.13 14:14:16 (*) Elaborating CPU configuration settings +Info: cpu: # 2014.02.13 14:14:16 (*) Creating all objects for CPU +Info: cpu: # 2014.02.13 14:14:16 (*) Testbench +Info: cpu: # 2014.02.13 14:14:16 (*) Instruction decoding +Info: cpu: # 2014.02.13 14:14:16 (*) Instruction fields +Info: cpu: # 2014.02.13 14:14:16 (*) Instruction decodes +Info: cpu: # 2014.02.13 14:14:17 (*) Signals for RTL simulation waveforms +Info: cpu: # 2014.02.13 14:14:17 (*) Instruction controls +Info: cpu: # 2014.02.13 14:14:17 (*) Pipeline frontend +Info: cpu: # 2014.02.13 14:14:17 (*) Pipeline backend +Info: cpu: # 2014.02.13 14:14:19 (*) Generating RTL from CPU objects +Info: cpu: # 2014.02.13 14:14:22 (*) Creating encrypted RTL +Info: cpu: # 2014.02.13 14:14:24 (*) Done Nios II generation +Info: cpu: Done RTL generation for module 'system_cpu' +Info: cpu: "system" instantiated altera_nios2_qsys "cpu" +Info: sysid: "system" instantiated altera_avalon_sysid_qsys "sysid" +Info: Starting classic module elaboration. +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_4257823588356694759.dir/0003_sopclgen --no_splash --refresh C:/Users/gongal/AppData/Local/Temp/alt6114_4257823588356694759.dir/0003_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +Info: Finished elaborating classic module. +Executing: C:/altera/12.1sp1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/Users/gongal/AppData/Local/Temp/alt6114_4257823588356694759.dir/0003_sopclgen/yysystem.ptf +Info: Running sopc_builder... +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_4257823588356694759.dir/0003_sopclgen --generate C:/Users/gongal/AppData/Local/Temp/alt6114_4257823588356694759.dir/0003_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +No .sopc_builder configuration file(!) +. +. +# 2014.02.13 14:14:28 (*) Running Test Generator Program for system_sdram +# 2014.02.13 14:14:29 (*) Success: sopc_builder finished. +Info: sdram: "system" instantiated altera_avalon_new_sdram_controller "sdram" +Info: Starting classic module elaboration. +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_4257823588356694759.dir/0004_sopclgen --no_splash --refresh C:/Users/gongal/AppData/Local/Temp/alt6114_4257823588356694759.dir/0004_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +Info: Finished elaborating classic module. +Executing: C:/altera/12.1sp1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/Users/gongal/AppData/Local/Temp/alt6114_4257823588356694759.dir/0004_sopclgen/yysystem.ptf +Info: Running sopc_builder... +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_4257823588356694759.dir/0004_sopclgen --generate C:/Users/gongal/AppData/Local/Temp/alt6114_4257823588356694759.dir/0004_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +No .sopc_builder configuration file(!) +. +# 2014.02.13 14:14:33 (*) Success: sopc_builder finished. +Info: sys_clk_timer: "system" instantiated altera_avalon_timer "sys_clk_timer" +Info: Starting classic module elaboration. +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_4257823588356694759.dir/0005_sopclgen --no_splash --refresh C:/Users/gongal/AppData/Local/Temp/alt6114_4257823588356694759.dir/0005_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +Info: Finished elaborating classic module. +Executing: C:/altera/12.1sp1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/Users/gongal/AppData/Local/Temp/alt6114_4257823588356694759.dir/0005_sopclgen/yysystem.ptf +Info: Running sopc_builder... +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_4257823588356694759.dir/0005_sopclgen --generate C:/Users/gongal/AppData/Local/Temp/alt6114_4257823588356694759.dir/0005_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +No .sopc_builder configuration file(!) +. +# 2014.02.13 14:14:38 (*) Success: sopc_builder finished. +Info: uart_0: "system" instantiated altera_avalon_uart "uart_0" +Info: Starting classic module elaboration. +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_4257823588356694759.dir/0006_sopclgen --no_splash --refresh C:/Users/gongal/AppData/Local/Temp/alt6114_4257823588356694759.dir/0006_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +Info: Finished elaborating classic module. +Executing: C:/altera/12.1sp1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/Users/gongal/AppData/Local/Temp/alt6114_4257823588356694759.dir/0006_sopclgen/yysystem.ptf +Info: Running sopc_builder... +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_4257823588356694759.dir/0006_sopclgen --generate C:/Users/gongal/AppData/Local/Temp/alt6114_4257823588356694759.dir/0006_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +No .sopc_builder configuration file(!) +. +# 2014.02.13 14:14:42 (*) Success: sopc_builder finished. +Info: pio_led: "system" instantiated altera_avalon_pio "pio_led" +Info: Starting classic module elaboration. +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_4257823588356694759.dir/0007_sopclgen --no_splash --refresh C:/Users/gongal/AppData/Local/Temp/alt6114_4257823588356694759.dir/0007_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +Info: Finished elaborating classic module. +Executing: C:/altera/12.1sp1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/Users/gongal/AppData/Local/Temp/alt6114_4257823588356694759.dir/0007_sopclgen/yysystem.ptf +Info: Running sopc_builder... +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_4257823588356694759.dir/0007_sopclgen --generate C:/Users/gongal/AppData/Local/Temp/alt6114_4257823588356694759.dir/0007_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +No .sopc_builder configuration file(!) +. +# 2014.02.13 14:14:46 (*) Success: sopc_builder finished. +Info: pio_key: "system" instantiated altera_avalon_pio "pio_key" +Info: Starting classic module elaboration. +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_4257823588356694759.dir/0008_sopclgen --no_splash --refresh C:/Users/gongal/AppData/Local/Temp/alt6114_4257823588356694759.dir/0008_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +Info: Finished elaborating classic module. +Executing: C:/altera/12.1sp1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/Users/gongal/AppData/Local/Temp/alt6114_4257823588356694759.dir/0008_sopclgen/yysystem.ptf +Info: Running sopc_builder... +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_4257823588356694759.dir/0008_sopclgen --generate C:/Users/gongal/AppData/Local/Temp/alt6114_4257823588356694759.dir/0008_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +No .sopc_builder configuration file(!) +. +# 2014.02.13 14:14:51 (*) Success: sopc_builder finished. +Info: pio_sw: "system" instantiated altera_avalon_pio "pio_sw" +Info: Starting classic module elaboration. +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_4257823588356694759.dir/0009_sopclgen --no_splash --refresh C:/Users/gongal/AppData/Local/Temp/alt6114_4257823588356694759.dir/0009_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +Info: Finished elaborating classic module. +Executing: C:/altera/12.1sp1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/Users/gongal/AppData/Local/Temp/alt6114_4257823588356694759.dir/0009_sopclgen/yysystem.ptf +Info: Running sopc_builder... +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_4257823588356694759.dir/0009_sopclgen --generate C:/Users/gongal/AppData/Local/Temp/alt6114_4257823588356694759.dir/0009_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +No .sopc_builder configuration file(!) +. +# 2014.02.13 14:14:55 (*) Success: sopc_builder finished. +Info: jtag_uart_0: "system" instantiated altera_avalon_jtag_uart "jtag_uart_0" +Info: cpu_instruction_master_translator: "system" instantiated altera_merlin_master_translator "cpu_instruction_master_translator" +Info: cpu_jtag_debug_module_translator: "system" instantiated altera_merlin_slave_translator "cpu_jtag_debug_module_translator" +Info: cpu_instruction_master_translator_avalon_universal_master_0_agent: "system" instantiated altera_merlin_master_agent "cpu_instruction_master_translator_avalon_universal_master_0_agent" +Info: cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent: "system" instantiated altera_merlin_slave_agent "cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent" +Info: cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo: "system" instantiated altera_avalon_sc_fifo "cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo" +Info: addr_router: "system" instantiated altera_merlin_router "addr_router" +Info: addr_router_001: "system" instantiated altera_merlin_router "addr_router_001" +Info: id_router: "system" instantiated altera_merlin_router "id_router" +Info: id_router_001: "system" instantiated altera_merlin_router "id_router_001" +Info: id_router_002: "system" instantiated altera_merlin_router "id_router_002" +Info: limiter: "system" instantiated altera_merlin_traffic_limiter "limiter" +Info: burst_adapter: "system" instantiated altera_merlin_burst_adapter "burst_adapter" +Info: rst_controller: "system" instantiated altera_reset_controller "rst_controller" +Info: cmd_xbar_demux: "system" instantiated altera_merlin_demultiplexer "cmd_xbar_demux" +Info: cmd_xbar_demux_001: "system" instantiated altera_merlin_demultiplexer "cmd_xbar_demux_001" +Info: cmd_xbar_mux: "system" instantiated altera_merlin_multiplexer "cmd_xbar_mux" +Info: rsp_xbar_demux: "system" instantiated altera_merlin_demultiplexer "rsp_xbar_demux" +Info: rsp_xbar_demux_002: "system" instantiated altera_merlin_demultiplexer "rsp_xbar_demux_002" +Info: rsp_xbar_mux: "system" instantiated altera_merlin_multiplexer "rsp_xbar_mux" +Info: Reusing file C:/Users/gongal/Desktop/DE0-nano-HD/system/synthesis/submodules/altera_merlin_arbitrator.sv +Info: rsp_xbar_mux_001: "system" instantiated altera_merlin_multiplexer "rsp_xbar_mux_001" +Info: Reusing file C:/Users/gongal/Desktop/DE0-nano-HD/system/synthesis/submodules/altera_merlin_arbitrator.sv +Info: width_adapter: "system" instantiated altera_merlin_width_adapter "width_adapter" +Info: Reusing file C:/Users/gongal/Desktop/DE0-nano-HD/system/synthesis/submodules/altera_merlin_burst_uncompressor.sv +Info: Reusing file C:/Users/gongal/Desktop/DE0-nano-HD/system/synthesis/submodules/altera_merlin_address_alignment.sv +Info: irq_mapper: "system" instantiated altera_irq_mapper "irq_mapper" +Info: system: Done system" with 32 modules, 112 files, 2245833 bytes +Info: ip-generate succeeded. +Info: Finished: Create HDL design files for synthesis diff --git a/MCTEST/DE0-nano-HD/system_generation_7.rpt b/MCTEST/DE0-nano-HD/system_generation_7.rpt new file mode 100644 index 00000000..20102400 --- /dev/null +++ b/MCTEST/DE0-nano-HD/system_generation_7.rpt @@ -0,0 +1,210 @@ +Info: Starting: Create block symbol file (.bsf) +Info: ip-generate --project-directory=C:/Users/gongal/Desktop/DE0-nano-HD/ --output-directory=C:/Users/gongal/Desktop/DE0-nano-HD/system/ --report-file=bsf:C:/Users/gongal/Desktop/DE0-nano-HD/system.bsf --system-info=DEVICE_FAMILY="Cyclone IV E" --system-info=DEVICE=EP4CE22F17C6 --system-info=DEVICE_SPEEDGRADE=6 --component-file=C:/Users/gongal/Desktop/DE0-nano-HD/system.qsys +Progress: Loading DE0-nano-HD/system.qsys +Progress: Reading input file +Progress: Adding clk_sys [clock_source 12.1] +Progress: Parameterizing module clk_sys +Progress: Adding cpu [altera_nios2_qsys 12.1] +Progress: Parameterizing module cpu +Progress: Adding sysid [altera_avalon_sysid_qsys 12.1] +Progress: Parameterizing module sysid +Progress: Adding sdram [altera_avalon_new_sdram_controller 12.1] +Progress: Parameterizing module sdram +Progress: Adding sys_clk_timer [altera_avalon_timer 12.1] +Progress: Parameterizing module sys_clk_timer +Progress: Adding uart_0 [altera_avalon_uart 12.1] +Progress: Parameterizing module uart_0 +Progress: Adding pio_led [altera_avalon_pio 12.1] +Progress: Parameterizing module pio_led +Progress: Adding pio_key [altera_avalon_pio 12.1] +Progress: Parameterizing module pio_key +Progress: Adding pio_sw [altera_avalon_pio 12.1] +Progress: Parameterizing module pio_sw +Progress: Adding jtag_uart_0 [altera_avalon_jtag_uart 12.1] +Progress: Parameterizing module jtag_uart_0 +Progress: Building connections +Progress: Parameterizing connections +Progress: Validating +Progress: Done reading input file +Info: system.sysid: System ID is not assigned automatically. Edit the System ID parameter to provide a unique ID +Info: system.sysid: Time stamp will be automatically updated when this component is generated. +Info: system.pio_key: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. +Info: system.pio_sw: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. +Info: ip-generate succeeded. +Info: Finished: Create block symbol file (.bsf) +Info: +Info: Starting: Create HDL design files for synthesis +Info: ip-generate --project-directory=C:/Users/gongal/Desktop/DE0-nano-HD/ --output-directory=C:/Users/gongal/Desktop/DE0-nano-HD/system/synthesis/ --file-set=QUARTUS_SYNTH --report-file=sopcinfo:C:/Users/gongal/Desktop/DE0-nano-HD/system.sopcinfo --report-file=html:C:/Users/gongal/Desktop/DE0-nano-HD/system.html --report-file=qip:C:/Users/gongal/Desktop/DE0-nano-HD/system/synthesis/system.qip --report-file=cmp:C:/Users/gongal/Desktop/DE0-nano-HD/system.cmp --system-info=DEVICE_FAMILY="Cyclone IV E" --system-info=DEVICE=EP4CE22F17C6 --system-info=DEVICE_SPEEDGRADE=6 --component-file=C:/Users/gongal/Desktop/DE0-nano-HD/system.qsys +Progress: Loading DE0-nano-HD/system.qsys +Progress: Reading input file +Progress: Adding clk_sys [clock_source 12.1] +Progress: Parameterizing module clk_sys +Progress: Adding cpu [altera_nios2_qsys 12.1] +Progress: Parameterizing module cpu +Progress: Adding sysid [altera_avalon_sysid_qsys 12.1] +Progress: Parameterizing module sysid +Progress: Adding sdram [altera_avalon_new_sdram_controller 12.1] +Progress: Parameterizing module sdram +Progress: Adding sys_clk_timer [altera_avalon_timer 12.1] +Progress: Parameterizing module sys_clk_timer +Progress: Adding uart_0 [altera_avalon_uart 12.1] +Progress: Parameterizing module uart_0 +Progress: Adding pio_led [altera_avalon_pio 12.1] +Progress: Parameterizing module pio_led +Progress: Adding pio_key [altera_avalon_pio 12.1] +Progress: Parameterizing module pio_key +Progress: Adding pio_sw [altera_avalon_pio 12.1] +Progress: Parameterizing module pio_sw +Progress: Adding jtag_uart_0 [altera_avalon_jtag_uart 12.1] +Progress: Parameterizing module jtag_uart_0 +Progress: Building connections +Progress: Parameterizing connections +Progress: Validating +Progress: Done reading input file +Info: system.sysid: System ID is not assigned automatically. Edit the System ID parameter to provide a unique ID +Info: system.sysid: Time stamp will be automatically updated when this component is generated. +Info: system.pio_key: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. +Info: system.pio_sw: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. +Info: system: Generating system "system" for QUARTUS_SYNTH +Info: pipeline_bridge_swap_transform: After transform: 10 modules, 41 connections +Info: No custom instruction connections, skipping transform +Info: merlin_translator_transform: After transform: 21 modules, 85 connections +Info: merlin_domain_transform: After transform: 42 modules, 227 connections +Info: merlin_router_transform: After transform: 53 modules, 271 connections +Info: merlin_traffic_limiter_transform: After transform: 55 modules, 281 connections +Info: merlin_burst_transform: After transform: 56 modules, 285 connections +Info: reset_adaptation_transform: After transform: 57 modules, 223 connections +Info: merlin_network_to_switch_transform: After transform: 78 modules, 267 connections +Info: merlin_width_transform: After transform: 80 modules, 273 connections +Info: limiter_update_transform: After transform: 80 modules, 275 connections +Info: merlin_interrupt_mapper_transform: After transform: 81 modules, 278 connections +Warning: system: "No matching role found for uart_0:s1:dataavailable (dataavailable)" +Warning: system: "No matching role found for uart_0:s1:readyfordata (readyfordata)" +Info: cpu: Starting RTL generation for module 'system_cpu' +Info: cpu: Generation command is [exec C:/altera/12.1sp1/quartus/../ip/altera/nios2_ip/altera_nios2/eperl.exe -I C:/altera/12.1sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/12.1sp1/quartus/sopc_builder/bin/europa -I C:/altera/12.1sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/12.1sp1/quartus/sopc_builder/bin -I C:/altera/12.1sp1/quartus/../ip/altera/nios2_ip/altera_nios2/cpu_lib -I C:/altera/12.1sp1/quartus/../ip/altera/nios2_ip/altera_nios2/nios_lib -I C:/altera/12.1sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -I C:/altera/12.1sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -- C:/altera/12.1sp1/quartus/../ip/altera/nios2_ip/altera_nios2/generate_rtl.epl --name=system_cpu --dir=C:/Users/gongal/AppData/Local/Temp/alt6114_4257823588356694759.dir/0024_cpu_gen/ --quartus_dir=C:/altera/12.1sp1/quartus --verilog --config=C:/Users/gongal/AppData/Local/Temp/alt6114_4257823588356694759.dir/0024_cpu_gen//system_cpu_processor_configuration.pl --do_build_sim=0 --bogus ] +Info: cpu: # 2014.02.13 14:26:31 (*) Starting Nios II generation +Info: cpu: # 2014.02.13 14:26:31 (*) Checking for plaintext license. +Info: cpu: # 2014.02.13 14:26:32 (*) Couldn't query license setup in Quartus directory C:/altera/12.1sp1/quartus +Info: cpu: # 2014.02.13 14:26:32 (*) Defaulting to contents of LM_LICENSE_FILE environment variable +Info: cpu: # 2014.02.13 14:26:32 (*) Plaintext license not found. +Info: cpu: # 2014.02.13 14:26:32 (*) Checking for encrypted license (non-evaluation). +Info: cpu: # 2014.02.13 14:26:32 (*) Couldn't query license setup in Quartus directory C:/altera/12.1sp1/quartus +Info: cpu: # 2014.02.13 14:26:32 (*) Defaulting to contents of LM_LICENSE_FILE environment variable +Info: cpu: # 2014.02.13 14:26:32 (*) Encrypted license found. SOF will not be time-limited. +Info: cpu: # 2014.02.13 14:26:32 (*) Elaborating CPU configuration settings +Info: cpu: # 2014.02.13 14:26:32 (*) Creating all objects for CPU +Info: cpu: # 2014.02.13 14:26:32 (*) Testbench +Info: cpu: # 2014.02.13 14:26:32 (*) Instruction decoding +Info: cpu: # 2014.02.13 14:26:32 (*) Instruction fields +Info: cpu: # 2014.02.13 14:26:32 (*) Instruction decodes +Info: cpu: # 2014.02.13 14:26:33 (*) Signals for RTL simulation waveforms +Info: cpu: # 2014.02.13 14:26:33 (*) Instruction controls +Info: cpu: # 2014.02.13 14:26:33 (*) Pipeline frontend +Info: cpu: # 2014.02.13 14:26:33 (*) Pipeline backend +Info: cpu: # 2014.02.13 14:26:35 (*) Generating RTL from CPU objects +Info: cpu: # 2014.02.13 14:26:39 (*) Creating encrypted RTL +Info: cpu: # 2014.02.13 14:26:40 (*) Done Nios II generation +Info: cpu: Done RTL generation for module 'system_cpu' +Info: cpu: "system" instantiated altera_nios2_qsys "cpu" +Info: sysid: "system" instantiated altera_avalon_sysid_qsys "sysid" +Info: Starting classic module elaboration. +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_4257823588356694759.dir/0026_sopclgen --no_splash --refresh C:/Users/gongal/AppData/Local/Temp/alt6114_4257823588356694759.dir/0026_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +Info: Finished elaborating classic module. +Executing: C:/altera/12.1sp1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/Users/gongal/AppData/Local/Temp/alt6114_4257823588356694759.dir/0026_sopclgen/yysystem.ptf +Info: Running sopc_builder... +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_4257823588356694759.dir/0026_sopclgen --generate C:/Users/gongal/AppData/Local/Temp/alt6114_4257823588356694759.dir/0026_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +No .sopc_builder configuration file(!) +. +. +# 2014.02.13 14:26:44 (*) Running Test Generator Program for system_sdram +# 2014.02.13 14:26:45 (*) Success: sopc_builder finished. +Info: sdram: "system" instantiated altera_avalon_new_sdram_controller "sdram" +Info: Starting classic module elaboration. +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_4257823588356694759.dir/0027_sopclgen --no_splash --refresh C:/Users/gongal/AppData/Local/Temp/alt6114_4257823588356694759.dir/0027_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +Info: Finished elaborating classic module. +Executing: C:/altera/12.1sp1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/Users/gongal/AppData/Local/Temp/alt6114_4257823588356694759.dir/0027_sopclgen/yysystem.ptf +Info: Running sopc_builder... +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_4257823588356694759.dir/0027_sopclgen --generate C:/Users/gongal/AppData/Local/Temp/alt6114_4257823588356694759.dir/0027_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +No .sopc_builder configuration file(!) +. +# 2014.02.13 14:26:49 (*) Success: sopc_builder finished. +Info: sys_clk_timer: "system" instantiated altera_avalon_timer "sys_clk_timer" +Info: Starting classic module elaboration. +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_4257823588356694759.dir/0028_sopclgen --no_splash --refresh C:/Users/gongal/AppData/Local/Temp/alt6114_4257823588356694759.dir/0028_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +Info: Finished elaborating classic module. +Executing: C:/altera/12.1sp1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/Users/gongal/AppData/Local/Temp/alt6114_4257823588356694759.dir/0028_sopclgen/yysystem.ptf +Info: Running sopc_builder... +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_4257823588356694759.dir/0028_sopclgen --generate C:/Users/gongal/AppData/Local/Temp/alt6114_4257823588356694759.dir/0028_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +No .sopc_builder configuration file(!) +. +# 2014.02.13 14:26:54 (*) Success: sopc_builder finished. +Info: uart_0: "system" instantiated altera_avalon_uart "uart_0" +Info: Starting classic module elaboration. +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_4257823588356694759.dir/0029_sopclgen --no_splash --refresh C:/Users/gongal/AppData/Local/Temp/alt6114_4257823588356694759.dir/0029_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +Info: Finished elaborating classic module. +Executing: C:/altera/12.1sp1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/Users/gongal/AppData/Local/Temp/alt6114_4257823588356694759.dir/0029_sopclgen/yysystem.ptf +Info: Running sopc_builder... +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_4257823588356694759.dir/0029_sopclgen --generate C:/Users/gongal/AppData/Local/Temp/alt6114_4257823588356694759.dir/0029_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +No .sopc_builder configuration file(!) +. +# 2014.02.13 14:26:58 (*) Success: sopc_builder finished. +Info: pio_led: "system" instantiated altera_avalon_pio "pio_led" +Info: Starting classic module elaboration. +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_4257823588356694759.dir/0030_sopclgen --no_splash --refresh C:/Users/gongal/AppData/Local/Temp/alt6114_4257823588356694759.dir/0030_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +Info: Finished elaborating classic module. +Executing: C:/altera/12.1sp1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/Users/gongal/AppData/Local/Temp/alt6114_4257823588356694759.dir/0030_sopclgen/yysystem.ptf +Info: Running sopc_builder... +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_4257823588356694759.dir/0030_sopclgen --generate C:/Users/gongal/AppData/Local/Temp/alt6114_4257823588356694759.dir/0030_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +No .sopc_builder configuration file(!) +. +# 2014.02.13 14:27:02 (*) Success: sopc_builder finished. +Info: pio_key: "system" instantiated altera_avalon_pio "pio_key" +Info: Starting classic module elaboration. +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_4257823588356694759.dir/0031_sopclgen --no_splash --refresh C:/Users/gongal/AppData/Local/Temp/alt6114_4257823588356694759.dir/0031_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +Info: Finished elaborating classic module. +Executing: C:/altera/12.1sp1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/Users/gongal/AppData/Local/Temp/alt6114_4257823588356694759.dir/0031_sopclgen/yysystem.ptf +Info: Running sopc_builder... +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_4257823588356694759.dir/0031_sopclgen --generate C:/Users/gongal/AppData/Local/Temp/alt6114_4257823588356694759.dir/0031_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +No .sopc_builder configuration file(!) +. +# 2014.02.13 14:27:07 (*) Success: sopc_builder finished. +Info: pio_sw: "system" instantiated altera_avalon_pio "pio_sw" +Info: Starting classic module elaboration. +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_4257823588356694759.dir/0032_sopclgen --no_splash --refresh C:/Users/gongal/AppData/Local/Temp/alt6114_4257823588356694759.dir/0032_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +Info: Finished elaborating classic module. +Executing: C:/altera/12.1sp1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/Users/gongal/AppData/Local/Temp/alt6114_4257823588356694759.dir/0032_sopclgen/yysystem.ptf +Info: Running sopc_builder... +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6114_4257823588356694759.dir/0032_sopclgen --generate C:/Users/gongal/AppData/Local/Temp/alt6114_4257823588356694759.dir/0032_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +No .sopc_builder configuration file(!) +. +# 2014.02.13 14:27:11 (*) Success: sopc_builder finished. +Info: jtag_uart_0: "system" instantiated altera_avalon_jtag_uart "jtag_uart_0" +Info: cpu_instruction_master_translator: "system" instantiated altera_merlin_master_translator "cpu_instruction_master_translator" +Info: cpu_jtag_debug_module_translator: "system" instantiated altera_merlin_slave_translator "cpu_jtag_debug_module_translator" +Info: cpu_instruction_master_translator_avalon_universal_master_0_agent: "system" instantiated altera_merlin_master_agent "cpu_instruction_master_translator_avalon_universal_master_0_agent" +Info: cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent: "system" instantiated altera_merlin_slave_agent "cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent" +Info: cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo: "system" instantiated altera_avalon_sc_fifo "cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo" +Info: addr_router: "system" instantiated altera_merlin_router "addr_router" +Info: addr_router_001: "system" instantiated altera_merlin_router "addr_router_001" +Info: id_router: "system" instantiated altera_merlin_router "id_router" +Info: id_router_001: "system" instantiated altera_merlin_router "id_router_001" +Info: id_router_002: "system" instantiated altera_merlin_router "id_router_002" +Info: limiter: "system" instantiated altera_merlin_traffic_limiter "limiter" +Info: burst_adapter: "system" instantiated altera_merlin_burst_adapter "burst_adapter" +Info: rst_controller: "system" instantiated altera_reset_controller "rst_controller" +Info: cmd_xbar_demux: "system" instantiated altera_merlin_demultiplexer "cmd_xbar_demux" +Info: cmd_xbar_demux_001: "system" instantiated altera_merlin_demultiplexer "cmd_xbar_demux_001" +Info: cmd_xbar_mux: "system" instantiated altera_merlin_multiplexer "cmd_xbar_mux" +Info: rsp_xbar_demux: "system" instantiated altera_merlin_demultiplexer "rsp_xbar_demux" +Info: rsp_xbar_demux_002: "system" instantiated altera_merlin_demultiplexer "rsp_xbar_demux_002" +Info: rsp_xbar_mux: "system" instantiated altera_merlin_multiplexer "rsp_xbar_mux" +Info: Reusing file C:/Users/gongal/Desktop/DE0-nano-HD/system/synthesis/submodules/altera_merlin_arbitrator.sv +Info: rsp_xbar_mux_001: "system" instantiated altera_merlin_multiplexer "rsp_xbar_mux_001" +Info: Reusing file C:/Users/gongal/Desktop/DE0-nano-HD/system/synthesis/submodules/altera_merlin_arbitrator.sv +Info: width_adapter: "system" instantiated altera_merlin_width_adapter "width_adapter" +Info: Reusing file C:/Users/gongal/Desktop/DE0-nano-HD/system/synthesis/submodules/altera_merlin_burst_uncompressor.sv +Info: Reusing file C:/Users/gongal/Desktop/DE0-nano-HD/system/synthesis/submodules/altera_merlin_address_alignment.sv +Info: irq_mapper: "system" instantiated altera_irq_mapper "irq_mapper" +Info: system: Done system" with 32 modules, 112 files, 2246114 bytes +Info: ip-generate succeeded. +Info: Finished: Create HDL design files for synthesis diff --git a/MCTEST/DE0-nano-HD/system_generation_8.rpt b/MCTEST/DE0-nano-HD/system_generation_8.rpt new file mode 100644 index 00000000..d00abf07 --- /dev/null +++ b/MCTEST/DE0-nano-HD/system_generation_8.rpt @@ -0,0 +1,230 @@ +Info: Starting: Create block symbol file (.bsf) +Info: ip-generate --project-directory=C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/ --output-directory=C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/ --report-file=bsf:C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.bsf --system-info=DEVICE_FAMILY="Cyclone IV E" --system-info=DEVICE=EP4CE22F17C6 --system-info=DEVICE_SPEEDGRADE=6 --component-file=C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.qsys +Progress: Loading DE0-nano-HD/system.qsys +Progress: Reading input file +Progress: Adding clk_sys [clock_source 12.1] +Progress: Parameterizing module clk_sys +Progress: Adding cpu [altera_nios2_qsys 12.1] +Progress: Parameterizing module cpu +Progress: Adding sysid [altera_avalon_sysid_qsys 12.1] +Progress: Parameterizing module sysid +Progress: Adding sdram [altera_avalon_new_sdram_controller 12.1] +Progress: Parameterizing module sdram +Progress: Adding sys_clk_timer [altera_avalon_timer 12.1] +Progress: Parameterizing module sys_clk_timer +Progress: Adding uart_0 [altera_avalon_uart 12.1] +Progress: Parameterizing module uart_0 +Progress: Adding pio_led [altera_avalon_pio 12.1] +Progress: Parameterizing module pio_led +Progress: Adding pio_key [altera_avalon_pio 12.1] +Progress: Parameterizing module pio_key +Progress: Adding pio_sw [altera_avalon_pio 12.1] +Progress: Parameterizing module pio_sw +Progress: Adding jtag_uart_0 [altera_avalon_jtag_uart 12.1] +Progress: Parameterizing module jtag_uart_0 +Progress: Adding pio_motor_rst [altera_avalon_pio 12.1] +Progress: Parameterizing module pio_motor_rst +Progress: Adding rs232_motor [altera_up_avalon_rs232 12.0] +Progress: Parameterizing module rs232_motor +Progress: Building connections +Progress: Parameterizing connections +Progress: Validating +Progress: Done reading input file +Info: system.sysid: System ID is not assigned automatically. Edit the System ID parameter to provide a unique ID +Info: system.sysid: Time stamp will be automatically updated when this component is generated. +Info: system.pio_key: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. +Info: system.pio_sw: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. +Info: ip-generate succeeded. +Info: Finished: Create block symbol file (.bsf) +Info: +Info: Starting: Create HDL design files for synthesis +Info: ip-generate --project-directory=C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/ --output-directory=C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/ --file-set=QUARTUS_SYNTH --report-file=sopcinfo:C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.sopcinfo --report-file=html:C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.html --report-file=qip:C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/system.qip --report-file=cmp:C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.cmp --system-info=DEVICE_FAMILY="Cyclone IV E" --system-info=DEVICE=EP4CE22F17C6 --system-info=DEVICE_SPEEDGRADE=6 --component-file=C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system.qsys +Progress: Loading DE0-nano-HD/system.qsys +Progress: Reading input file +Progress: Adding clk_sys [clock_source 12.1] +Progress: Parameterizing module clk_sys +Progress: Adding cpu [altera_nios2_qsys 12.1] +Progress: Parameterizing module cpu +Progress: Adding sysid [altera_avalon_sysid_qsys 12.1] +Progress: Parameterizing module sysid +Progress: Adding sdram [altera_avalon_new_sdram_controller 12.1] +Progress: Parameterizing module sdram +Progress: Adding sys_clk_timer [altera_avalon_timer 12.1] +Progress: Parameterizing module sys_clk_timer +Progress: Adding uart_0 [altera_avalon_uart 12.1] +Progress: Parameterizing module uart_0 +Progress: Adding pio_led [altera_avalon_pio 12.1] +Progress: Parameterizing module pio_led +Progress: Adding pio_key [altera_avalon_pio 12.1] +Progress: Parameterizing module pio_key +Progress: Adding pio_sw [altera_avalon_pio 12.1] +Progress: Parameterizing module pio_sw +Progress: Adding jtag_uart_0 [altera_avalon_jtag_uart 12.1] +Progress: Parameterizing module jtag_uart_0 +Progress: Adding pio_motor_rst [altera_avalon_pio 12.1] +Progress: Parameterizing module pio_motor_rst +Progress: Adding rs232_motor [altera_up_avalon_rs232 12.0] +Progress: Parameterizing module rs232_motor +Progress: Building connections +Progress: Parameterizing connections +Progress: Validating +Progress: Done reading input file +Info: system.sysid: System ID is not assigned automatically. Edit the System ID parameter to provide a unique ID +Info: system.sysid: Time stamp will be automatically updated when this component is generated. +Info: system.pio_key: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. +Info: system.pio_sw: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. +Info: system: Generating system "system" for QUARTUS_SYNTH +Info: pipeline_bridge_swap_transform: After transform: 12 modules, 50 connections +Info: No custom instruction connections, skipping transform +Info: merlin_translator_transform: After transform: 25 modules, 102 connections +Info: merlin_domain_transform: After transform: 50 modules, 272 connections +Info: merlin_router_transform: After transform: 63 modules, 324 connections +Info: merlin_traffic_limiter_transform: After transform: 65 modules, 334 connections +Info: merlin_burst_transform: After transform: 66 modules, 338 connections +Info: reset_adaptation_transform: After transform: 67 modules, 264 connections +Info: merlin_network_to_switch_transform: After transform: 92 modules, 316 connections +Info: merlin_width_transform: After transform: 94 modules, 322 connections +Info: limiter_update_transform: After transform: 94 modules, 324 connections +Info: merlin_interrupt_mapper_transform: After transform: 95 modules, 327 connections +Warning: system: "No matching role found for uart_0:s1:dataavailable (dataavailable)" +Warning: system: "No matching role found for uart_0:s1:readyfordata (readyfordata)" +Info: cpu: Starting RTL generation for module 'system_cpu' +Info: cpu: Generation command is [exec C:/altera/12.1sp1/quartus/../ip/altera/nios2_ip/altera_nios2/eperl.exe -I C:/altera/12.1sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/12.1sp1/quartus/sopc_builder/bin/europa -I C:/altera/12.1sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/12.1sp1/quartus/sopc_builder/bin -I C:/altera/12.1sp1/quartus/../ip/altera/nios2_ip/altera_nios2/cpu_lib -I C:/altera/12.1sp1/quartus/../ip/altera/nios2_ip/altera_nios2/nios_lib -I C:/altera/12.1sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -I C:/altera/12.1sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -- C:/altera/12.1sp1/quartus/../ip/altera/nios2_ip/altera_nios2/generate_rtl.epl --name=system_cpu --dir=C:/Users/gongal/AppData/Local/Temp/alt6135_8889721380883385224.dir/0001_cpu_gen/ --quartus_dir=C:/altera/12.1sp1/quartus --verilog --config=C:/Users/gongal/AppData/Local/Temp/alt6135_8889721380883385224.dir/0001_cpu_gen//system_cpu_processor_configuration.pl --do_build_sim=0 --bogus ] +Info: cpu: # 2014.03.06 09:42:58 (*) Starting Nios II generation +Info: cpu: # 2014.03.06 09:42:58 (*) Checking for plaintext license. +Info: cpu: # 2014.03.06 09:42:59 (*) Couldn't query license setup in Quartus directory C:/altera/12.1sp1/quartus +Info: cpu: # 2014.03.06 09:42:59 (*) Defaulting to contents of LM_LICENSE_FILE environment variable +Info: cpu: # 2014.03.06 09:42:59 (*) Plaintext license not found. +Info: cpu: # 2014.03.06 09:42:59 (*) Checking for encrypted license (non-evaluation). +Info: cpu: # 2014.03.06 09:42:59 (*) Couldn't query license setup in Quartus directory C:/altera/12.1sp1/quartus +Info: cpu: # 2014.03.06 09:42:59 (*) Defaulting to contents of LM_LICENSE_FILE environment variable +Info: cpu: # 2014.03.06 09:42:59 (*) Encrypted license found. SOF will not be time-limited. +Info: cpu: # 2014.03.06 09:42:59 (*) Elaborating CPU configuration settings +Info: cpu: # 2014.03.06 09:42:59 (*) Creating all objects for CPU +Info: cpu: # 2014.03.06 09:42:59 (*) Testbench +Info: cpu: # 2014.03.06 09:43:00 (*) Instruction decoding +Info: cpu: # 2014.03.06 09:43:00 (*) Instruction fields +Info: cpu: # 2014.03.06 09:43:00 (*) Instruction decodes +Info: cpu: # 2014.03.06 09:43:00 (*) Signals for RTL simulation waveforms +Info: cpu: # 2014.03.06 09:43:00 (*) Instruction controls +Info: cpu: # 2014.03.06 09:43:00 (*) Pipeline frontend +Info: cpu: # 2014.03.06 09:43:00 (*) Pipeline backend +Info: cpu: # 2014.03.06 09:43:03 (*) Generating RTL from CPU objects +Info: cpu: # 2014.03.06 09:43:06 (*) Creating encrypted RTL +Info: cpu: # 2014.03.06 09:43:07 (*) Done Nios II generation +Info: cpu: Done RTL generation for module 'system_cpu' +Info: cpu: "system" instantiated altera_nios2_qsys "cpu" +Info: sysid: "system" instantiated altera_avalon_sysid_qsys "sysid" +Info: Starting classic module elaboration. +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6135_8889721380883385224.dir/0003_sopclgen --no_splash --refresh C:/Users/gongal/AppData/Local/Temp/alt6135_8889721380883385224.dir/0003_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +Info: Finished elaborating classic module. +Executing: C:/altera/12.1sp1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/Users/gongal/AppData/Local/Temp/alt6135_8889721380883385224.dir/0003_sopclgen/yysystem.ptf +Info: Running sopc_builder... +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6135_8889721380883385224.dir/0003_sopclgen --generate C:/Users/gongal/AppData/Local/Temp/alt6135_8889721380883385224.dir/0003_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +No .sopc_builder configuration file(!) +. +. +# 2014.03.06 09:43:13 (*) Running Test Generator Program for system_sdram +# 2014.03.06 09:43:14 (*) Success: sopc_builder finished. +Info: sdram: "system" instantiated altera_avalon_new_sdram_controller "sdram" +Info: Starting classic module elaboration. +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6135_8889721380883385224.dir/0004_sopclgen --no_splash --refresh C:/Users/gongal/AppData/Local/Temp/alt6135_8889721380883385224.dir/0004_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +Info: Finished elaborating classic module. +Executing: C:/altera/12.1sp1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/Users/gongal/AppData/Local/Temp/alt6135_8889721380883385224.dir/0004_sopclgen/yysystem.ptf +Info: Running sopc_builder... +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6135_8889721380883385224.dir/0004_sopclgen --generate C:/Users/gongal/AppData/Local/Temp/alt6135_8889721380883385224.dir/0004_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +No .sopc_builder configuration file(!) +. +# 2014.03.06 09:43:18 (*) Success: sopc_builder finished. +Info: sys_clk_timer: "system" instantiated altera_avalon_timer "sys_clk_timer" +Info: Starting classic module elaboration. +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6135_8889721380883385224.dir/0005_sopclgen --no_splash --refresh C:/Users/gongal/AppData/Local/Temp/alt6135_8889721380883385224.dir/0005_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +Info: Finished elaborating classic module. +Executing: C:/altera/12.1sp1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/Users/gongal/AppData/Local/Temp/alt6135_8889721380883385224.dir/0005_sopclgen/yysystem.ptf +Info: Running sopc_builder... +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6135_8889721380883385224.dir/0005_sopclgen --generate C:/Users/gongal/AppData/Local/Temp/alt6135_8889721380883385224.dir/0005_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +No .sopc_builder configuration file(!) +. +# 2014.03.06 09:43:23 (*) Success: sopc_builder finished. +Info: uart_0: "system" instantiated altera_avalon_uart "uart_0" +Info: Starting classic module elaboration. +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6135_8889721380883385224.dir/0006_sopclgen --no_splash --refresh C:/Users/gongal/AppData/Local/Temp/alt6135_8889721380883385224.dir/0006_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +Info: Finished elaborating classic module. +Executing: C:/altera/12.1sp1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/Users/gongal/AppData/Local/Temp/alt6135_8889721380883385224.dir/0006_sopclgen/yysystem.ptf +Info: Running sopc_builder... +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6135_8889721380883385224.dir/0006_sopclgen --generate C:/Users/gongal/AppData/Local/Temp/alt6135_8889721380883385224.dir/0006_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +No .sopc_builder configuration file(!) +. +# 2014.03.06 09:43:27 (*) Success: sopc_builder finished. +Info: pio_led: "system" instantiated altera_avalon_pio "pio_led" +Info: Starting classic module elaboration. +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6135_8889721380883385224.dir/0007_sopclgen --no_splash --refresh C:/Users/gongal/AppData/Local/Temp/alt6135_8889721380883385224.dir/0007_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +Info: Finished elaborating classic module. +Executing: C:/altera/12.1sp1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/Users/gongal/AppData/Local/Temp/alt6135_8889721380883385224.dir/0007_sopclgen/yysystem.ptf +Info: Running sopc_builder... +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6135_8889721380883385224.dir/0007_sopclgen --generate C:/Users/gongal/AppData/Local/Temp/alt6135_8889721380883385224.dir/0007_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +No .sopc_builder configuration file(!) +. +# 2014.03.06 09:43:31 (*) Success: sopc_builder finished. +Info: pio_key: "system" instantiated altera_avalon_pio "pio_key" +Info: Starting classic module elaboration. +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6135_8889721380883385224.dir/0008_sopclgen --no_splash --refresh C:/Users/gongal/AppData/Local/Temp/alt6135_8889721380883385224.dir/0008_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +Info: Finished elaborating classic module. +Executing: C:/altera/12.1sp1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/Users/gongal/AppData/Local/Temp/alt6135_8889721380883385224.dir/0008_sopclgen/yysystem.ptf +Info: Running sopc_builder... +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6135_8889721380883385224.dir/0008_sopclgen --generate C:/Users/gongal/AppData/Local/Temp/alt6135_8889721380883385224.dir/0008_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +No .sopc_builder configuration file(!) +. +# 2014.03.06 09:43:35 (*) Success: sopc_builder finished. +Info: pio_sw: "system" instantiated altera_avalon_pio "pio_sw" +Info: Starting classic module elaboration. +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6135_8889721380883385224.dir/0009_sopclgen --no_splash --refresh C:/Users/gongal/AppData/Local/Temp/alt6135_8889721380883385224.dir/0009_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +Info: Finished elaborating classic module. +Executing: C:/altera/12.1sp1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/Users/gongal/AppData/Local/Temp/alt6135_8889721380883385224.dir/0009_sopclgen/yysystem.ptf +Info: Running sopc_builder... +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6135_8889721380883385224.dir/0009_sopclgen --generate C:/Users/gongal/AppData/Local/Temp/alt6135_8889721380883385224.dir/0009_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +No .sopc_builder configuration file(!) +. +# 2014.03.06 09:43:39 (*) Success: sopc_builder finished. +Info: jtag_uart_0: "system" instantiated altera_avalon_jtag_uart "jtag_uart_0" +Info: Starting classic module elaboration. +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6135_8889721380883385224.dir/0010_sopclgen --no_splash --refresh C:/Users/gongal/AppData/Local/Temp/alt6135_8889721380883385224.dir/0010_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +Info: Finished elaborating classic module. +Executing: C:/altera/12.1sp1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/Users/gongal/AppData/Local/Temp/alt6135_8889721380883385224.dir/0010_sopclgen/yysystem.ptf +Info: Running sopc_builder... +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6135_8889721380883385224.dir/0010_sopclgen --generate C:/Users/gongal/AppData/Local/Temp/alt6135_8889721380883385224.dir/0010_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +No .sopc_builder configuration file(!) +. +# 2014.03.06 09:43:43 (*) Success: sopc_builder finished. +Info: pio_motor_rst: "system" instantiated altera_avalon_pio "pio_motor_rst" +Info: rs232_motor: Starting Generation of RS232 UART +Info: rs232_motor: "system" instantiated altera_up_avalon_rs232 "rs232_motor" +Info: cpu_instruction_master_translator: "system" instantiated altera_merlin_master_translator "cpu_instruction_master_translator" +Info: cpu_jtag_debug_module_translator: "system" instantiated altera_merlin_slave_translator "cpu_jtag_debug_module_translator" +Info: cpu_instruction_master_translator_avalon_universal_master_0_agent: "system" instantiated altera_merlin_master_agent "cpu_instruction_master_translator_avalon_universal_master_0_agent" +Info: cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent: "system" instantiated altera_merlin_slave_agent "cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent" +Info: cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo: "system" instantiated altera_avalon_sc_fifo "cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo" +Info: addr_router: "system" instantiated altera_merlin_router "addr_router" +Info: addr_router_001: "system" instantiated altera_merlin_router "addr_router_001" +Info: id_router: "system" instantiated altera_merlin_router "id_router" +Info: id_router_001: "system" instantiated altera_merlin_router "id_router_001" +Info: id_router_002: "system" instantiated altera_merlin_router "id_router_002" +Info: limiter: "system" instantiated altera_merlin_traffic_limiter "limiter" +Info: burst_adapter: "system" instantiated altera_merlin_burst_adapter "burst_adapter" +Info: rst_controller: "system" instantiated altera_reset_controller "rst_controller" +Info: cmd_xbar_demux: "system" instantiated altera_merlin_demultiplexer "cmd_xbar_demux" +Info: cmd_xbar_demux_001: "system" instantiated altera_merlin_demultiplexer "cmd_xbar_demux_001" +Info: cmd_xbar_mux: "system" instantiated altera_merlin_multiplexer "cmd_xbar_mux" +Info: rsp_xbar_demux: "system" instantiated altera_merlin_demultiplexer "rsp_xbar_demux" +Info: rsp_xbar_demux_002: "system" instantiated altera_merlin_demultiplexer "rsp_xbar_demux_002" +Info: rsp_xbar_mux: "system" instantiated altera_merlin_multiplexer "rsp_xbar_mux" +Info: Reusing file C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_arbitrator.sv +Info: rsp_xbar_mux_001: "system" instantiated altera_merlin_multiplexer "rsp_xbar_mux_001" +Info: Reusing file C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_arbitrator.sv +Info: width_adapter: "system" instantiated altera_merlin_width_adapter "width_adapter" +Info: Reusing file C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_burst_uncompressor.sv +Info: Reusing file C:/Users/gongal/Desktop/MCTEST/DE0-nano-HD/system/synthesis/submodules/altera_merlin_address_alignment.sv +Info: irq_mapper: "system" instantiated altera_irq_mapper "irq_mapper" +Info: system: Done system" with 34 modules, 130 files, 2551930 bytes +Info: ip-generate succeeded. +Info: Finished: Create HDL design files for synthesis diff --git a/MCandWifiTestDE0/.metadata/.lock b/MCandWifiTestDE0/.metadata/.lock new file mode 100644 index 00000000..e69de29b diff --git a/MCandWifiTestDE0/.metadata/.log b/MCandWifiTestDE0/.metadata/.log new file mode 100644 index 00000000..a2c8ccf5 --- /dev/null +++ b/MCandWifiTestDE0/.metadata/.log @@ -0,0 +1,13 @@ +!SESSION 2014-03-03 15:22:06.773 ----------------------------------------------- +eclipse.buildId=M20120208-0800 +java.version=1.6.0_23 +java.vendor=Sun Microsystems Inc. +BootLoader constants: OS=win32, ARCH=x86, WS=win32, NL=en_CA +Framework arguments: -product org.eclipse.epp.package.cpp.product -perspective com.altera.sbtgui.ui.cPerspective +Command-line arguments: -os win32 -ws win32 -arch x86 -product org.eclipse.epp.package.cpp.product -perspective com.altera.sbtgui.ui.cPerspective + +!ENTRY org.eclipse.cdt.core 1 0 2014-03-03 15:31:40.300 +!MESSAGE Indexed 'MCtest_bsp' (99 sources, 99 headers) in 1.17 sec: 3,065 declarations; 11,179 references; 95 unresolved inclusions; 6 syntax errors; 166 unresolved names (1.15%) + +!ENTRY org.eclipse.cdt.core 1 0 2014-03-03 15:31:41.015 +!MESSAGE Indexed 'MCtest' (1 sources, 13 headers) in 0.01 sec: 8 declarations; 23 references; 15 unresolved inclusions; 0 syntax errors; 6 unresolved names (16.22%) diff --git a/MCandWifiTestDE0/.metadata/.mylyn/repositories.xml.zip b/MCandWifiTestDE0/.metadata/.mylyn/repositories.xml.zip new file mode 100644 index 00000000..24c91049 Binary files /dev/null and b/MCandWifiTestDE0/.metadata/.mylyn/repositories.xml.zip differ diff --git a/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.cdt.core/.log b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.cdt.core/.log new file mode 100644 index 00000000..947e73d3 --- /dev/null +++ b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.cdt.core/.log @@ -0,0 +1 @@ +*** SESSION Mar 03, 2014 15:28:57.38 ------------------------------------------- diff --git a/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.cdt.core/MCtest.1393885901000.pdom b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.cdt.core/MCtest.1393885901000.pdom new file mode 100644 index 00000000..01077521 Binary files /dev/null and b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.cdt.core/MCtest.1393885901000.pdom differ diff --git a/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.cdt.core/MCtest_bsp.1393885898969.pdom b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.cdt.core/MCtest_bsp.1393885898969.pdom new file mode 100644 index 00000000..9dc15c1f Binary files /dev/null and b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.cdt.core/MCtest_bsp.1393885898969.pdom differ diff --git a/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.cdt.make.core/.log b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.cdt.make.core/.log new file mode 100644 index 00000000..e69de29b diff --git a/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.cdt.make.core/MCtest.sc b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.cdt.make.core/MCtest.sc new file mode 100644 index 00000000..f795578a --- /dev/null +++ b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.cdt.make.core/MCtest.sc @@ -0,0 +1,453 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.cdt.make.core/MCtest_bsp.sc b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.cdt.make.core/MCtest_bsp.sc new file mode 100644 index 00000000..b14f262e --- /dev/null +++ b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.cdt.make.core/MCtest_bsp.sc @@ -0,0 +1,437 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.cdt.make.core/specs.c b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.cdt.make.core/specs.c new file mode 100644 index 00000000..8b137891 --- /dev/null +++ b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.cdt.make.core/specs.c @@ -0,0 +1 @@ + diff --git a/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.cdt.make.core/specs.cpp b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.cdt.make.core/specs.cpp new file mode 100644 index 00000000..8b137891 --- /dev/null +++ b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.cdt.make.core/specs.cpp @@ -0,0 +1 @@ + diff --git a/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.cdt.ui/MCtest.build.log b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.cdt.ui/MCtest.build.log new file mode 100644 index 00000000..309dffab --- /dev/null +++ b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.cdt.ui/MCtest.build.log @@ -0,0 +1,10 @@ + +**** Build of configuration Nios II for project MCtest **** + +make all +Info: Building ../MCtest_bsp/ +make --no-print-directory -C ../MCtest_bsp/ +[BSP build complete] +[MCtest build complete] + +**** Build Finished **** diff --git a/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.cdt.ui/MCtest_bsp.build.log b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.cdt.ui/MCtest_bsp.build.log new file mode 100644 index 00000000..d2a33f81 --- /dev/null +++ b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.cdt.ui/MCtest_bsp.build.log @@ -0,0 +1,7 @@ + +**** Build of configuration Nios II for project MCtest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** diff --git a/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.cdt.ui/dialog_settings.xml b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.cdt.ui/dialog_settings.xml new file mode 100644 index 00000000..8e479579 --- /dev/null +++ b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.cdt.ui/dialog_settings.xml @@ -0,0 +1,7 @@ + +
+
+
+
+
+
diff --git a/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.cdt.ui/global-build.log b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.cdt.ui/global-build.log new file mode 100644 index 00000000..59c5eb9f --- /dev/null +++ b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.cdt.ui/global-build.log @@ -0,0 +1,311 @@ + +**** Clean-only build of configuration Nios II for project MCtest_bsp **** + +make clean +[BSP clean complete] + +**** Build Finished **** + +**** Clean-only build of configuration Nios II for project MCtest **** + +make clean +[MCtest clean complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCtest **** + +make all +Info: Building ../MCtest_bsp/ +make --no-print-directory -C ../MCtest_bsp/ +Compiling alt_alarm_start.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_alarm_start.o HAL/src/alt_alarm_start.c +Compiling alt_busy_sleep.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_busy_sleep.o HAL/src/alt_busy_sleep.c +Compiling alt_close.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_close.o HAL/src/alt_close.c +Compiling alt_dcache_flush.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dcache_flush.o HAL/src/alt_dcache_flush.c +Compiling alt_dcache_flush_all.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dcache_flush_all.o HAL/src/alt_dcache_flush_all.c +Compiling alt_dcache_flush_no_writeback.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dcache_flush_no_writeback.o HAL/src/alt_dcache_flush_no_writeback.c +Compiling alt_dev.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dev.o HAL/src/alt_dev.c +Compiling alt_dev_llist_insert.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dev_llist_insert.o HAL/src/alt_dev_llist_insert.c +Compiling alt_dma_rxchan_open.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dma_rxchan_open.o HAL/src/alt_dma_rxchan_open.c +Compiling alt_dma_txchan_open.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dma_txchan_open.o HAL/src/alt_dma_txchan_open.c +Compiling alt_do_ctors.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_do_ctors.o HAL/src/alt_do_ctors.c +Compiling alt_do_dtors.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_do_dtors.o HAL/src/alt_do_dtors.c +Compiling alt_environ.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_environ.o HAL/src/alt_environ.c +Compiling alt_errno.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_errno.o HAL/src/alt_errno.c +Compiling alt_exception_entry.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_exception_entry.o HAL/src/alt_exception_entry.S +Compiling alt_exception_muldiv.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_exception_muldiv.o HAL/src/alt_exception_muldiv.S +Compiling alt_exception_trap.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_exception_trap.o HAL/src/alt_exception_trap.S +Compiling alt_execve.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_execve.o HAL/src/alt_execve.c +Compiling alt_exit.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_exit.o HAL/src/alt_exit.c +Compiling alt_fcntl.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fcntl.o HAL/src/alt_fcntl.c +Compiling alt_fd_lock.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fd_lock.o HAL/src/alt_fd_lock.c +Compiling alt_fd_unlock.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fd_unlock.o HAL/src/alt_fd_unlock.c +Compiling alt_find_dev.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_find_dev.o HAL/src/alt_find_dev.c +Compiling alt_find_file.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_find_file.o HAL/src/alt_find_file.c +Compiling alt_flash_dev.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_flash_dev.o HAL/src/alt_flash_dev.c +Compiling alt_fork.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fork.o HAL/src/alt_fork.c +Compiling alt_fs_reg.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fs_reg.o HAL/src/alt_fs_reg.c +Compiling alt_fstat.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fstat.o HAL/src/alt_fstat.c +Compiling alt_get_fd.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_get_fd.o HAL/src/alt_get_fd.c +Compiling alt_getchar.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_getchar.o HAL/src/alt_getchar.c +Compiling alt_getpid.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_getpid.o HAL/src/alt_getpid.c +Compiling alt_gettod.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_gettod.o HAL/src/alt_gettod.c +Compiling alt_gmon.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_gmon.o HAL/src/alt_gmon.c +Compiling alt_icache_flush.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_icache_flush.o HAL/src/alt_icache_flush.c +Compiling alt_icache_flush_all.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_icache_flush_all.o HAL/src/alt_icache_flush_all.c +Compiling alt_iic.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_iic.o HAL/src/alt_iic.c +Compiling alt_iic_isr_register.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_iic_isr_register.o HAL/src/alt_iic_isr_register.c +Compiling alt_instruction_exception_entry.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_instruction_exception_entry.o HAL/src/alt_instruction_exception_entry.c +Compiling alt_instruction_exception_register.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_instruction_exception_register.o HAL/src/alt_instruction_exception_register.c +Compiling alt_io_redirect.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_io_redirect.o HAL/src/alt_io_redirect.c +Compiling alt_ioctl.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_ioctl.o HAL/src/alt_ioctl.c +Compiling alt_irq_entry.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_irq_entry.o HAL/src/alt_irq_entry.S +Compiling alt_irq_handler.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_irq_handler.o HAL/src/alt_irq_handler.c +Compiling alt_irq_register.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_irq_register.o HAL/src/alt_irq_register.c +Compiling alt_irq_vars.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_irq_vars.o HAL/src/alt_irq_vars.c +Compiling alt_isatty.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_isatty.o HAL/src/alt_isatty.c +Compiling alt_kill.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_kill.o HAL/src/alt_kill.c +Compiling alt_link.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_link.o HAL/src/alt_link.c +Compiling alt_load.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_load.o HAL/src/alt_load.c +Compiling alt_log_macro.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_log_macro.o HAL/src/alt_log_macro.S +Compiling alt_log_printf.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_log_printf.o HAL/src/alt_log_printf.c +Compiling alt_lseek.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_lseek.o HAL/src/alt_lseek.c +Compiling alt_main.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_main.o HAL/src/alt_main.c +Compiling alt_mcount.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_mcount.o HAL/src/alt_mcount.S +Compiling alt_open.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_open.o HAL/src/alt_open.c +Compiling alt_printf.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_printf.o HAL/src/alt_printf.c +Compiling alt_putchar.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_putchar.o HAL/src/alt_putchar.c +Compiling alt_putstr.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_putstr.o HAL/src/alt_putstr.c +Compiling alt_read.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_read.o HAL/src/alt_read.c +Compiling alt_release_fd.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_release_fd.o HAL/src/alt_release_fd.c +Compiling alt_remap_cached.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_remap_cached.o HAL/src/alt_remap_cached.c +Compiling alt_remap_uncached.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_remap_uncached.o HAL/src/alt_remap_uncached.c +Compiling alt_rename.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_rename.o HAL/src/alt_rename.c +Compiling alt_sbrk.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_sbrk.o HAL/src/alt_sbrk.c +Compiling alt_settod.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_settod.o HAL/src/alt_settod.c +Compiling alt_software_exception.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_software_exception.o HAL/src/alt_software_exception.S +Compiling alt_stat.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_stat.o HAL/src/alt_stat.c +Compiling alt_tick.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_tick.o HAL/src/alt_tick.c +Compiling alt_times.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_times.o HAL/src/alt_times.c +Compiling alt_uncached_free.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_uncached_free.o HAL/src/alt_uncached_free.c +Compiling alt_uncached_malloc.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_uncached_malloc.o HAL/src/alt_uncached_malloc.c +Compiling alt_unlink.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_unlink.o HAL/src/alt_unlink.c +Compiling alt_usleep.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_usleep.o HAL/src/alt_usleep.c +Compiling alt_wait.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_wait.o HAL/src/alt_wait.c +Compiling alt_write.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_write.o HAL/src/alt_write.c +Compiling altera_nios2_qsys_irq.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/altera_nios2_qsys_irq.o HAL/src/altera_nios2_qsys_irq.c +Compiling crt0.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/crt0.o HAL/src/crt0.S +Compiling os_cpu_a.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/os_cpu_a.o HAL/src/os_cpu_a.S +Compiling os_cpu_c.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/os_cpu_c.o HAL/src/os_cpu_c.c +Compiling alt_env_lock.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/alt_env_lock.o UCOSII/src/alt_env_lock.c +Compiling alt_malloc_lock.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/alt_malloc_lock.o UCOSII/src/alt_malloc_lock.c +Compiling os_core.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_core.o UCOSII/src/os_core.c +Compiling os_dbg.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_dbg.o UCOSII/src/os_dbg.c +Compiling os_flag.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_flag.o UCOSII/src/os_flag.c +Compiling os_mbox.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_mbox.o UCOSII/src/os_mbox.c +Compiling os_mem.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_mem.o UCOSII/src/os_mem.c +Compiling os_mutex.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_mutex.o UCOSII/src/os_mutex.c +Compiling os_q.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_q.o UCOSII/src/os_q.c +Compiling os_sem.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_sem.o UCOSII/src/os_sem.c +Compiling os_task.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_task.o UCOSII/src/os_task.c +Compiling os_time.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_time.o UCOSII/src/os_time.c +Compiling os_tmr.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_tmr.o UCOSII/src/os_tmr.c +Compiling alt_sys_init.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/alt_sys_init.o alt_sys_init.c +Compiling altera_avalon_jtag_uart_fd.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_jtag_uart_fd.o drivers/src/altera_avalon_jtag_uart_fd.c +Compiling altera_avalon_jtag_uart_init.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_jtag_uart_init.o drivers/src/altera_avalon_jtag_uart_init.c +Compiling altera_avalon_jtag_uart_ioctl.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_jtag_uart_ioctl.o drivers/src/altera_avalon_jtag_uart_ioctl.c +Compiling altera_avalon_jtag_uart_read.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_jtag_uart_read.o drivers/src/altera_avalon_jtag_uart_read.c +Compiling altera_avalon_jtag_uart_write.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_jtag_uart_write.o drivers/src/altera_avalon_jtag_uart_write.c +Compiling altera_avalon_sysid_qsys.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_sysid_qsys.o drivers/src/altera_avalon_sysid_qsys.c +Compiling altera_avalon_timer_sc.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_timer_sc.o drivers/src/altera_avalon_timer_sc.c +Compiling altera_avalon_timer_ts.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_timer_ts.o drivers/src/altera_avalon_timer_ts.c +Compiling altera_avalon_timer_vars.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_timer_vars.o drivers/src/altera_avalon_timer_vars.c +Compiling altera_avalon_uart_fd.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_uart_fd.o drivers/src/altera_avalon_uart_fd.c +Compiling altera_avalon_uart_init.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_uart_init.o drivers/src/altera_avalon_uart_init.c +Compiling altera_avalon_uart_ioctl.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_uart_ioctl.o drivers/src/altera_avalon_uart_ioctl.c +Compiling altera_avalon_uart_read.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_uart_read.o drivers/src/altera_avalon_uart_read.c +Compiling altera_avalon_uart_write.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_uart_write.o drivers/src/altera_avalon_uart_write.c +drivers/src/altera_up_avalon_rs232.c: In function 'alt_up_rs232_read_fd': +Compiling altera_up_avalon_rs232.c... +drivers/src/altera_up_avalon_rs232.c:110: warning: pointer targets in passing argument 2 of 'alt_up_rs232_read_data' differ in signedness +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_up_avalon_rs232.o drivers/src/altera_up_avalon_rs232.c +Creating libucosii_bsp.a... +rm -f -f libucosii_bsp.a +nios2-elf-ar -src libucosii_bsp.a obj/HAL/src/alt_alarm_start.o obj/HAL/src/alt_busy_sleep.o obj/HAL/src/alt_close.o obj/HAL/src/alt_dcache_flush.o obj/HAL/src/alt_dcache_flush_all.o obj/HAL/src/alt_dcache_flush_no_writeback.o obj/HAL/src/alt_dev.o obj/HAL/src/alt_dev_llist_insert.o obj/HAL/src/alt_dma_rxchan_open.o obj/HAL/src/alt_dma_txchan_open.o obj/HAL/src/alt_do_ctors.o obj/HAL/src/alt_do_dtors.o obj/HAL/src/alt_environ.o obj/HAL/src/alt_errno.o obj/HAL/src/alt_exception_entry.o obj/HAL/src/alt_exception_muldiv.o obj/HAL/src/alt_exception_trap.o obj/HAL/src/alt_execve.o obj/HAL/src/alt_exit.o obj/HAL/src/alt_fcntl.o obj/HAL/src/alt_fd_lock.o obj/HAL/src/alt_fd_unlock.o obj/HAL/src/alt_find_dev.o obj/HAL/src/alt_find_file.o obj/HAL/src/alt_flash_dev.o obj/HAL/src/alt_fork.o obj/HAL/src/alt_fs_reg.o obj/HAL/src/alt_fstat.o obj/HAL/src/alt_get_fd.o obj/HAL/src/alt_getchar.o obj/HAL/src/alt_getpid.o obj/HAL/src/alt_gettod.o obj/HAL/src/alt_gmon.o obj/HAL/src/alt_icache_flush.o obj/HAL/src/alt_icache_flush_all.o obj/HAL/src/alt_iic.o obj/HAL/src/alt_iic_isr_register.o obj/HAL/src/alt_instruction_exception_entry.o obj/HAL/src/alt_instruction_exception_register.o obj/HAL/src/alt_io_redirect.o obj/HAL/src/alt_ioctl.o obj/HAL/src/alt_irq_entry.o obj/HAL/src/alt_irq_handler.o obj/HAL/src/alt_irq_register.o obj/HAL/src/alt_irq_vars.o obj/HAL/src/alt_isatty.o obj/HAL/src/alt_kill.o obj/HAL/src/alt_link.o obj/HAL/src/alt_load.o obj/HAL/src/alt_log_macro.o obj/HAL/src/alt_log_printf.o obj/HAL/src/alt_lseek.o obj/HAL/src/alt_main.o obj/HAL/src/alt_mcount.o obj/HAL/src/alt_open.o obj/HAL/src/alt_printf.o obj/HAL/src/alt_putchar.o obj/HAL/src/alt_putstr.o obj/HAL/src/alt_read.o obj/HAL/src/alt_release_fd.o obj/HAL/src/alt_remap_cached.o obj/HAL/src/alt_remap_uncached.o obj/HAL/src/alt_rename.o obj/HAL/src/alt_sbrk.o obj/HAL/src/alt_settod.o obj/HAL/src/alt_software_exception.o obj/HAL/src/alt_stat.o obj/HAL/src/alt_tick.o obj/HAL/src/alt_times.o obj/HAL/src/alt_uncached_free.o obj/HAL/src/alt_uncached_malloc.o obj/HAL/src/alt_unlink.o obj/HAL/src/alt_usleep.o obj/HAL/src/alt_wait.o obj/HAL/src/alt_write.o obj/HAL/src/altera_nios2_qsys_irq.o obj/HAL/src/crt0.o obj/HAL/src/os_cpu_a.o obj/HAL/src/os_cpu_c.o obj/UCOSII/src/alt_env_lock.o obj/UCOSII/src/alt_malloc_lock.o obj/UCOSII/src/os_core.o obj/UCOSII/src/os_dbg.o obj/UCOSII/src/os_flag.o obj/UCOSII/src/os_mbox.o obj/UCOSII/src/os_mem.o obj/UCOSII/src/os_mutex.o obj/UCOSII/src/os_q.o obj/UCOSII/src/os_sem.o obj/UCOSII/src/os_task.o obj/UCOSII/src/os_time.o obj/UCOSII/src/os_tmr.o obj/alt_sys_init.o obj/drivers/src/altera_avalon_jtag_uart_fd.o obj/drivers/src/altera_avalon_jtag_uart_init.o obj/drivers/src/altera_avalon_jtag_uart_ioctl.o obj/drivers/src/altera_avalon_jtag_uart_read.o obj/drivers/src/altera_avalon_jtag_uart_write.o obj/drivers/src/altera_avalon_sysid_qsys.o obj/drivers/src/altera_avalon_timer_sc.o obj/drivers/src/altera_avalon_timer_ts.o obj/drivers/src/altera_avalon_timer_vars.o obj/drivers/src/altera_avalon_uart_fd.o obj/drivers/src/altera_avalon_uart_init.o obj/drivers/src/altera_avalon_uart_ioctl.o obj/drivers/src/altera_avalon_uart_read.o obj/drivers/src/altera_avalon_uart_write.o obj/drivers/src/altera_up_avalon_rs232.o +[BSP build complete] +Info: Compiling SerialHandler.cpp to obj/default/SerialHandler.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCtest_bsp//UCOSII/inc -I../MCtest_bsp//HAL/inc -I../MCtest_bsp/ -I../MCtest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/SerialHandler.o SerialHandler.cpp +Info: Compiling main.cpp to obj/default/main.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCtest_bsp//UCOSII/inc -I../MCtest_bsp//HAL/inc -I../MCtest_bsp/ -I../MCtest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/main.o main.cpp +main.cpp:61: warning: 'void isr_on_ir_pushbutton(void*)' defined but not used +Info: Linking MCtest.elf +nios2-elf-g++ -T'../MCtest_bsp//linker.x' -msys-crt0='../MCtest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCtest_bsp/ -Wl,-Map=MCtest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCtest.elf obj/default/SerialHandler.o obj/default/main.o -lm +nios2-elf-insert MCtest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010c0 --timestamp 1393885158 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0" --jdi C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.jdi --sopcinfo C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system.sopcinfo +Info: (MCtest.elf) 148 KBytes program size (code + initialized data). +Info: 16228 KBytes free for stack + heap. +Info: Creating MCtest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCtest.elf >MCtest.objdump +[MCtest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCtest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCtest **** + +make all +Info: Building ../MCtest_bsp/ +make --no-print-directory -C ../MCtest_bsp/ +[BSP build complete] +Info: Compiling main.cpp to obj/default/main.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCtest_bsp//UCOSII/inc -I../MCtest_bsp//HAL/inc -I../MCtest_bsp/ -I../MCtest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/main.o main.cpp +main.cpp:61: warning: 'void isr_on_ir_pushbutton(void*)' defined but not used +Info: Linking MCtest.elf +nios2-elf-g++ -T'../MCtest_bsp//linker.x' -msys-crt0='../MCtest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCtest_bsp/ -Wl,-Map=MCtest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCtest.elf obj/default/SerialHandler.o obj/default/main.o -lm +nios2-elf-insert MCtest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010c0 --timestamp 1393885158 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0" --jdi C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.jdi --sopcinfo C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system.sopcinfo +Info: (MCtest.elf) 148 KBytes program size (code + initialized data). +Info: 16228 KBytes free for stack + heap. +Info: Creating MCtest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCtest.elf >MCtest.objdump +[MCtest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCtest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCtest **** + +make all +Info: Building ../MCtest_bsp/ +make --no-print-directory -C ../MCtest_bsp/ +[BSP build complete] +[MCtest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCtest **** + +make all +Info: Building ../MCtest_bsp/ +make --no-print-directory -C ../MCtest_bsp/ +[BSP build complete] +[MCtest build complete] + +**** Build Finished **** diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0/main.cpp b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.resources/.history/36/10542af223a3001318a38b66e21301ed similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0/main.cpp rename to MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.resources/.history/36/10542af223a3001318a38b66e21301ed diff --git a/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.resources/.history/9e/608d5ad923a3001318a38b66e21301ed b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.resources/.history/9e/608d5ad923a3001318a38b66e21301ed new file mode 100644 index 00000000..7058cf8d --- /dev/null +++ b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.resources/.history/9e/608d5ad923a3001318a38b66e21301ed @@ -0,0 +1,119 @@ +/************************************************************************* +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. All use of this software and documentation is * +* subject to the License Agreement located at the end of this file below.* +************************************************************************** +* Description: * +* The following is a simple hello world program running MicroC/OS-II.The * +* purpose of the design is to be a very simple application that just * +* demonstrates MicroC/OS-II running on NIOS II.The design doesn't account* +* for issues such as checking system call return codes. etc. * +* * +* Requirements: * +* -Supported Example Hardware Platforms * +* Standard * +* Full Featured * +* Low Cost * +* -Supported Development Boards * +* Nios II Development Board, Stratix II Edition * +* Nios Development Board, Stratix Professional Edition * +* Nios Development Board, Stratix Edition * +* Nios Development Board, Cyclone Edition * +* -System Library Settings * +* RTOS Type - MicroC/OS-II * +* Periodic System Timer * +* -Know Issues * +* If this design is run on the ISS, terminal output will take several* +* minutes per iteration. * +**************************************************************************/ + + +#include +#include "includes.h" + +/* Definition of Task Stacks */ +#define TASK_STACKSIZE 2048 +OS_STK task1_stk[TASK_STACKSIZE]; +OS_STK task2_stk[TASK_STACKSIZE]; + +/* Definition of Task Priorities */ + +#define TASK1_PRIORITY 1 +#define TASK2_PRIORITY 2 + +/* Prints "Hello World" and sleeps for three seconds */ +void task1(void* pdata) +{ + while (1) + { + printf("Hello from task1\n"); + OSTimeDlyHMSM(0, 0, 3, 0); + } +} +/* Prints "Hello World" and sleeps for three seconds */ +void task2(void* pdata) +{ + while (1) + { + printf("Hello from task2\n"); + OSTimeDlyHMSM(0, 0, 3, 0); + } +} +/* The main function creates two task and starts multi-tasking */ +int main(void) +{ + + OSTaskCreateExt(task1, + NULL, + (void *)&task1_stk[TASK_STACKSIZE-1], + TASK1_PRIORITY, + TASK1_PRIORITY, + task1_stk, + TASK_STACKSIZE, + NULL, + 0); + + + OSTaskCreateExt(task2, + NULL, + (void *)&task2_stk[TASK_STACKSIZE-1], + TASK2_PRIORITY, + TASK2_PRIORITY, + task2_stk, + TASK_STACKSIZE, + NULL, + 0); + OSStart(); + return 0; +} + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ diff --git a/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.resources/.projects/MCtest/.indexes/history.index b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.resources/.projects/MCtest/.indexes/history.index new file mode 100644 index 00000000..014857ed Binary files /dev/null and b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.resources/.projects/MCtest/.indexes/history.index differ diff --git a/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.resources/.projects/MCtest/.indexes/properties.index b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.resources/.projects/MCtest/.indexes/properties.index new file mode 100644 index 00000000..c8397eab Binary files /dev/null and b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.resources/.projects/MCtest/.indexes/properties.index differ diff --git a/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.resources/.projects/MCtest/.location b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.resources/.projects/MCtest/.location new file mode 100644 index 00000000..483a752f Binary files /dev/null and b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.resources/.projects/MCtest/.location differ diff --git a/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.resources/.projects/MCtest/.markers b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.resources/.projects/MCtest/.markers new file mode 100644 index 00000000..9a793112 Binary files /dev/null and b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.resources/.projects/MCtest/.markers differ diff --git a/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.resources/.projects/MCtest_bsp/.indexes/properties.index b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.resources/.projects/MCtest_bsp/.indexes/properties.index new file mode 100644 index 00000000..08dfcaa8 Binary files /dev/null and b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.resources/.projects/MCtest_bsp/.indexes/properties.index differ diff --git a/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.resources/.projects/MCtest_bsp/.location b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.resources/.projects/MCtest_bsp/.location new file mode 100644 index 00000000..8aa786bc Binary files /dev/null and b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.resources/.projects/MCtest_bsp/.location differ diff --git a/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.resources/.root/.indexes/history.version b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.resources/.root/.indexes/history.version new file mode 100644 index 00000000..25cb955b --- /dev/null +++ b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.resources/.root/.indexes/history.version @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.resources/.root/.indexes/properties.index b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.resources/.root/.indexes/properties.index new file mode 100644 index 00000000..fd32bc3d Binary files /dev/null and b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.resources/.root/.indexes/properties.index differ diff --git a/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.resources/.root/.indexes/properties.version b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.resources/.root/.indexes/properties.version new file mode 100644 index 00000000..6b2aaa76 --- /dev/null +++ b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.resources/.root/.indexes/properties.version @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.resources/.root/1.tree b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.resources/.root/1.tree new file mode 100644 index 00000000..d1c46960 Binary files /dev/null and b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.resources/.root/1.tree differ diff --git a/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.resources/.safetable/org.eclipse.core.resources b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.resources/.safetable/org.eclipse.core.resources new file mode 100644 index 00000000..713f7eef Binary files /dev/null and b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.resources/.safetable/org.eclipse.core.resources differ diff --git a/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.runtime/.settings/com.altera.sbtgui.ui.prefs b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.runtime/.settings/com.altera.sbtgui.ui.prefs new file mode 100644 index 00000000..5eb947fc --- /dev/null +++ b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.runtime/.settings/com.altera.sbtgui.ui.prefs @@ -0,0 +1,4 @@ +eclipse.preferences.version=1 +newSoftwareExampleWizardPage.defaultLocation=C\:\\Users\\gongal\\NewRepARCap\\MCandWifiTestDE0\\software\\MCtest +newSoftwareExampleWizardPage.sopcinfoFile=C\:\\Users\\gongal\\NewRepARCap\\MCandWifiTestDE0\\system.sopcinfo +newSoftwareExampleWizardPage2.newBspLocation=C\:\\Users\\gongal\\NewRepARCap\\MCandWifiTestDE0\\software\\MCtest_bsp diff --git a/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.core.prj-MCtest.prefs b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.core.prj-MCtest.prefs new file mode 100644 index 00000000..9c00dc4e --- /dev/null +++ b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.core.prj-MCtest.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +indexer/preferenceScope=0 diff --git a/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.core.prj-MCtest_bsp.prefs b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.core.prj-MCtest_bsp.prefs new file mode 100644 index 00000000..9c00dc4e --- /dev/null +++ b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.core.prj-MCtest_bsp.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +indexer/preferenceScope=0 diff --git a/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.debug.core.prefs b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.debug.core.prefs new file mode 100644 index 00000000..aa2411de --- /dev/null +++ b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.debug.core.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +org.eclipse.cdt.debug.core.cDebug.default_source_containers=\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n diff --git a/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.managedbuilder.core.prefs b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.managedbuilder.core.prefs new file mode 100644 index 00000000..4df841a6 --- /dev/null +++ b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.managedbuilder.core.prefs @@ -0,0 +1,3 @@ +eclipse.preferences.version=1 +properties/MCtest.null.2059914611/preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.818579186=\#\r\n\#Mon Mar 03 15\:44\:05 MST 2014\r\ncdt.managedbuild.tool.gnu.cpp.compiler.cygwin.base.1388730101\=\\\#\\r\\n\\\#Mon Mar 03 15\\\:44\\\:05 MST 2014\\r\\nrebuildState\\\=false\\r\\n\r\ncdt.managedbuild.tool.gnu.archiver.cygwin.base.1950526765\=\\\#\\r\\n\\\#Mon Mar 03 15\\\:44\\\:05 MST 2014\\r\\nrebuildState\\\=false\\r\\n\r\norg.eclipse.cdt.build.core.prefbase.toolchain.1908067478\=\\\#\\r\\n\\\#Mon Mar 03 15\\\:33\\\:48 MST 2014\\r\\nrebuildState\\\=true\\r\\n\r\norg.eclipse.cdt.build.core.settings.holder.949663354\=\\\#\\r\\n\\\#Mon Mar 03 15\\\:33\\\:48 MST 2014\\r\\nrebuildState\\\=true\\r\\n\r\ncdt.managedbuild.tool.gnu.assembler.cygwin.base.1673173524\=\\\#\\r\\n\\\#Mon Mar 03 15\\\:44\\\:05 MST 2014\\r\\nrebuildState\\\=false\\r\\n\r\ncdt.managedbuild.tool.gnu.c.linker.cygwin.base.607140680\=\\\#\\r\\n\\\#Mon Mar 03 15\\\:44\\\:05 MST 2014\\r\\nrebuildState\\\=false\\r\\n\r\ncdt.managedbuild.tool.gnu.c.compiler.cygwin.base.840237831\=\\\#\\r\\n\\\#Mon Mar 03 15\\\:44\\\:05 MST 2014\\r\\nrebuildState\\\=false\\r\\n\r\norg.eclipse.cdt.build.core.settings.holder.1965978551\=\\\#\\r\\n\\\#Mon Mar 03 15\\\:33\\\:48 MST 2014\\r\\nrebuildState\\\=true\\r\\n\r\norg.eclipse.cdt.build.core.settings.holder.libs.482536553\=\\\#\\r\\n\\\#Mon Mar 03 15\\\:33\\\:48 MST 2014\\r\\nrebuildState\\\=true\\r\\n\r\ncdt.managedbuild.tool.gnu.cpp.linker.cygwin.base.1567069117\=\\\#\\r\\n\\\#Mon Mar 03 15\\\:44\\\:05 MST 2014\\r\\nrebuildState\\\=false\\r\\n\r\npreference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.818579186\=\\\#\\r\\n\\\#Mon Mar 03 15\\\:33\\\:48 MST 2014\\r\\nrcState\\\=0\\r\\nrebuildState\\\=false\\r\\n\r\norg.eclipse.cdt.build.core.settings.holder.2029579331\=\\\#\\r\\n\\\#Mon Mar 03 15\\\:33\\\:48 MST 2014\\r\\nrebuildState\\\=true\\r\\n\r\naltera.nios2.mingw.gcc4.379379768\=\\\#\\r\\n\\\#Mon Mar 03 15\\\:44\\\:05 MST 2014\\r\\nrebuildState\\\=false\\r\\n\r\n +properties/MCtest_bsp.null.320352856/preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.773316708=\#\r\n\#Mon Mar 03 15\:34\:20 MST 2014\r\npreference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.773316708\=\\\#\\r\\n\\\#Mon Mar 03 15\\\:34\\\:15 MST 2014\\r\\nrcState\\\=0\\r\\nrebuildState\\\=false\\r\\n\r\norg.eclipse.cdt.build.core.settings.holder.libs.1644571714\=\\\#\\r\\n\\\#Mon Mar 03 15\\\:31\\\:40 MST 2014\\r\\nrebuildState\\\=true\\r\\n\r\ncdt.managedbuild.tool.gnu.archiver.cygwin.base.1041826645\=\\\#\\r\\n\\\#Mon Mar 03 15\\\:34\\\:20 MST 2014\\r\\nrebuildState\\\=false\\r\\n\r\ncdt.managedbuild.tool.gnu.c.compiler.cygwin.base.1655804526\=\\\#\\r\\n\\\#Mon Mar 03 15\\\:34\\\:20 MST 2014\\r\\nrebuildState\\\=false\\r\\n\r\ncdt.managedbuild.tool.gnu.cpp.linker.cygwin.base.1895545563\=\\\#\\r\\n\\\#Mon Mar 03 15\\\:34\\\:20 MST 2014\\r\\nrebuildState\\\=false\\r\\n\r\naltera.nios2.mingw.gcc4.1483456498\=\\\#\\r\\n\\\#Mon Mar 03 15\\\:34\\\:20 MST 2014\\r\\nrebuildState\\\=false\\r\\n\r\ncdt.managedbuild.tool.gnu.assembler.cygwin.base.432577751\=\\\#\\r\\n\\\#Mon Mar 03 15\\\:34\\\:20 MST 2014\\r\\nrebuildState\\\=false\\r\\n\r\ncdt.managedbuild.tool.gnu.cpp.compiler.cygwin.base.1983801617\=\\\#\\r\\n\\\#Mon Mar 03 15\\\:34\\\:20 MST 2014\\r\\nrebuildState\\\=false\\r\\n\r\ncdt.managedbuild.tool.gnu.c.linker.cygwin.base.975480047\=\\\#\\r\\n\\\#Mon Mar 03 15\\\:34\\\:20 MST 2014\\r\\nrebuildState\\\=false\\r\\n\r\norg.eclipse.cdt.build.core.settings.holder.2124000363\=\\\#\\r\\n\\\#Mon Mar 03 15\\\:31\\\:40 MST 2014\\r\\nrebuildState\\\=true\\r\\n\r\norg.eclipse.cdt.build.core.settings.holder.1009342308\=\\\#\\r\\n\\\#Mon Mar 03 15\\\:31\\\:40 MST 2014\\r\\nrebuildState\\\=true\\r\\n\r\norg.eclipse.cdt.build.core.settings.holder.868947833\=\\\#\\r\\n\\\#Mon Mar 03 15\\\:31\\\:40 MST 2014\\r\\nrebuildState\\\=true\\r\\n\r\norg.eclipse.cdt.build.core.prefbase.toolchain.1794157265\=\\\#\\r\\n\\\#Mon Mar 03 15\\\:31\\\:40 MST 2014\\r\\nrebuildState\\\=true\\r\\n\r\n diff --git a/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.mylyn.ui.prefs b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.mylyn.ui.prefs new file mode 100644 index 00000000..0451f542 --- /dev/null +++ b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.mylyn.ui.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +org.eclipse.mylyn.cdt.ui.run.count.3_3_0=1 diff --git a/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.ui.prefs b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.ui.prefs new file mode 100644 index 00000000..bd28f849 --- /dev/null +++ b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.ui.prefs @@ -0,0 +1,6 @@ +content_assist_disabled_computers=org.eclipse.cdt.ui.parserProposalCategory\u0000org.eclipse.cdt.ui.textProposalCategory\u0000 +eclipse.preferences.version=1 +spelling_locale=en_GB +spelling_locale_initialized=true +useAnnotationsPrefPage=true +useQuickDiffPrefPage=true diff --git a/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.core.resources.prefs b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.core.resources.prefs new file mode 100644 index 00000000..a7fb09f3 --- /dev/null +++ b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.core.resources.prefs @@ -0,0 +1,3 @@ +description.autobuilding=false +eclipse.preferences.version=1 +version=1 diff --git a/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.debug.core.prefs b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.debug.core.prefs new file mode 100644 index 00000000..57e3b772 --- /dev/null +++ b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.debug.core.prefs @@ -0,0 +1,5 @@ +//org.eclipse.debug.core.PREFERRED_DELEGATES/org.eclipse.cdt.launch.applicationLaunchType=org.eclipse.cdt.dsf.gdb.launch.localCLaunch,debug;org.eclipse.cdt.cdi.launch.localCLaunch,run +//org.eclipse.debug.core.PREFERRED_DELEGATES/org.eclipse.cdt.launch.attachLaunchType=org.eclipse.cdt.dsf.gdb.launch.attachCLaunch,debug +//org.eclipse.debug.core.PREFERRED_DELEGATES/org.eclipse.cdt.launch.postmortemLaunchType=org.eclipse.cdt.dsf.gdb.launch.coreCLaunch,debug +//org.eclipse.debug.core.PREFERRED_DELEGATES/org.eclipse.cdt.launch.remoteApplicationLaunchType=org.eclipse.rse.remotecdt.dsf.debug,debug +eclipse.preferences.version=1 diff --git a/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.debug.ui.prefs b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.debug.ui.prefs new file mode 100644 index 00000000..4e59cdd7 --- /dev/null +++ b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.debug.ui.prefs @@ -0,0 +1,3 @@ +eclipse.preferences.version=1 +org.eclipse.debug.ui.PREF_LAUNCH_PERSPECTIVES=\r\n\r\n +preferredTargets=org.eclipse.cdt.debug.ui.toggleCBreakpointTarget\:org.eclipse.cdt.debug.ui.toggleCBreakpointTarget| diff --git a/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.epp.usagedata.recording.prefs b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.epp.usagedata.recording.prefs new file mode 100644 index 00000000..bf62cfa6 --- /dev/null +++ b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.epp.usagedata.recording.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +org.eclipse.epp.usagedata.recording.last-upload=1393885741538 diff --git a/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.mylyn.context.core.prefs b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.mylyn.context.core.prefs new file mode 100644 index 00000000..43e97e40 --- /dev/null +++ b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.mylyn.context.core.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +mylyn.attention.migrated=true diff --git a/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.mylyn.monitor.ui.prefs b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.mylyn.monitor.ui.prefs new file mode 100644 index 00000000..8d462a6c --- /dev/null +++ b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.mylyn.monitor.ui.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +org.eclipse.mylyn.monitor.activity.tracking.enabled.checked=true diff --git a/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.team.cvs.ui.prefs b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.team.cvs.ui.prefs new file mode 100644 index 00000000..f9e585ba --- /dev/null +++ b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.team.cvs.ui.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +pref_first_startup=false diff --git a/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.team.ui.prefs b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.team.ui.prefs new file mode 100644 index 00000000..56cd496f --- /dev/null +++ b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.team.ui.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +org.eclipse.team.ui.first_time=false diff --git a/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.editors.prefs b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.editors.prefs new file mode 100644 index 00000000..61f3bb8b --- /dev/null +++ b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.editors.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +overviewRuler_migration=migrated_3.1 diff --git a/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.ide.prefs b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.ide.prefs new file mode 100644 index 00000000..744ba143 --- /dev/null +++ b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.ide.prefs @@ -0,0 +1,7 @@ +IMPORT_FILES_AND_FOLDERS_RELATIVE=true +IMPORT_FILES_AND_FOLDERS_TYPE=23,1 +PROBLEMS_FILTERS_MIGRATE=true +eclipse.preferences.version=1 +platformState=1370561326246 +quickStart=false +tipsAndTricks=true diff --git a/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.prefs b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.prefs new file mode 100644 index 00000000..08076f23 --- /dev/null +++ b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +showIntro=false diff --git a/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.workbench.prefs b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.workbench.prefs new file mode 100644 index 00000000..68b875a8 --- /dev/null +++ b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.workbench.prefs @@ -0,0 +1,2 @@ +ENABLED_DECORATORS=com.altera.sbtgui.project.decorator.bsp\:true,com.altera.sbtgui.project.nios2builddecorator\:true,org.eclipse.cdt.ui.indexedFiles\:false,org.eclipse.cdt.managedbuilder.ui.excludedFile\:true,org.eclipse.egit.ui.internal.decorators.GitLightweightDecorator\:true,org.eclipse.mylyn.context.ui.decorator.interest\:true,org.eclipse.mylyn.tasks.ui.decorators.task\:true,org.eclipse.mylyn.team.ui.changeset.decorator\:true,org.eclipse.rse.core.virtualobject.decorator\:true,org.eclipse.rse.core.binary.executable.decorator\:true,org.eclipse.rse.core.script.executable.decorator\:true,org.eclipse.rse.core.java.executable.decorator\:true,org.eclipse.rse.core.library.decorator\:true,org.eclipse.rse.core.link.decorator\:true,org.eclipse.rse.subsystems.error.decorator\:true,org.eclipse.team.cvs.ui.decorator\:true,org.eclipse.ui.LinkedResourceDecorator\:true,org.eclipse.ui.VirtualResourceDecorator\:true,org.eclipse.ui.ContentTypeDecorator\:true,org.eclipse.ui.ResourceFilterDecorator\:false, +eclipse.preferences.version=1 diff --git a/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.debug.core/.launches/MCtest Nios II Hardware configuration.launch b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.debug.core/.launches/MCtest Nios II Hardware configuration.launch new file mode 100644 index 00000000..09366c3d --- /dev/null +++ b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.debug.core/.launches/MCtest Nios II Hardware configuration.launch @@ -0,0 +1,21 @@ + + + + + + + + + + + + + + + + + + + + + diff --git a/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.debug.ui/dialog_settings.xml b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.debug.ui/dialog_settings.xml new file mode 100644 index 00000000..aac92b46 --- /dev/null +++ b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.debug.ui/dialog_settings.xml @@ -0,0 +1,16 @@ + +
+
+ + + + + + +
+
+ + + +
+
diff --git a/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.debug.ui/launchConfigurationHistory.xml b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.debug.ui/launchConfigurationHistory.xml new file mode 100644 index 00000000..2290dfee --- /dev/null +++ b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.debug.ui/launchConfigurationHistory.xml @@ -0,0 +1,19 @@ + + + + + + + + + + + + + + + + + + + diff --git a/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.epp.usagedata.recording/usagedata.csv b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.epp.usagedata.recording/usagedata.csv new file mode 100644 index 00000000..30073912 --- /dev/null +++ b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.epp.usagedata.recording/usagedata.csv @@ -0,0 +1,228 @@ +what,kind,bundleId,bundleVersion,description,time +activated,perspective,com.altera.sbtgui.ui,,"com.altera.sbtgui.ui.cPerspective",1393885740456 +started,bundle,org.eclipse.osgi,3.7.2.v20120110-1415,"org.eclipse.osgi",1393885740456 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a/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/.workspace/2014/3/10/refactorings.index b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/.workspace/2014/3/10/refactorings.index new file mode 100644 index 00000000..3046855f --- /dev/null +++ b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/.workspace/2014/3/10/refactorings.index @@ -0,0 +1 @@ +1393886011714 Delete resource 'MCtest/hello_ucosii.c' diff --git a/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.ltk.ui.refactoring/dialog_settings.xml b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.ltk.ui.refactoring/dialog_settings.xml new file mode 100644 index 00000000..27eb4040 --- /dev/null +++ b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.ltk.ui.refactoring/dialog_settings.xml @@ -0,0 +1,7 @@ + +
+
+ + +
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diff --git a/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.ui.workbench/dialog_settings.xml b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.ui.workbench/dialog_settings.xml new file mode 100644 index 00000000..30f05281 --- /dev/null +++ b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.ui.workbench/dialog_settings.xml @@ -0,0 +1,8 @@ + +
+
+ + + +
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diff --git a/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.ui.workbench/workbench.xml b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.ui.workbench/workbench.xml new file mode 100644 index 00000000..3602f838 --- /dev/null +++ b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.ui.workbench/workbench.xml @@ -0,0 +1,329 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.ui.workbench/workingsets.xml b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.ui.workbench/workingsets.xml new file mode 100644 index 00000000..f61ffd6a --- /dev/null +++ b/MCandWifiTestDE0/.metadata/.plugins/org.eclipse.ui.workbench/workingsets.xml @@ -0,0 +1,4 @@ + + + + \ No newline at end of file diff --git a/MCandWifiTestDE0/.metadata/version.ini b/MCandWifiTestDE0/.metadata/version.ini new file mode 100644 index 00000000..c51ff745 --- /dev/null +++ b/MCandWifiTestDE0/.metadata/version.ini @@ -0,0 +1 @@ +org.eclipse.core.runtime=1 \ No newline at end of file diff --git a/MCandWifiTestDE0/.qsys_edit/preferences.xml b/MCandWifiTestDE0/.qsys_edit/preferences.xml index b01e73c7..d8b10e28 100644 --- a/MCandWifiTestDE0/.qsys_edit/preferences.xml +++ b/MCandWifiTestDE0/.qsys_edit/preferences.xml @@ -14,7 +14,6 @@ - - + + diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/.cproject b/MCandWifiTestDE0/NewMCWifiTest_bsp/.cproject deleted file mode 100644 index db7c1662..00000000 --- a/MCandWifiTestDE0/NewMCWifiTest_bsp/.cproject +++ /dev/null @@ -1,481 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/.project b/MCandWifiTestDE0/NewMCWifiTest_bsp/.project deleted file mode 100644 index 9d755673..00000000 --- a/MCandWifiTestDE0/NewMCWifiTest_bsp/.project +++ /dev/null @@ -1,85 +0,0 @@ - - - NewMCWifiTest_bsp - - - - - - org.eclipse.cdt.managedbuilder.core.genmakebuilder - clean,full,incremental, - - - ?name? - - - - org.eclipse.cdt.make.core.append_environment - true - - - org.eclipse.cdt.make.core.autoBuildTarget - all - - - org.eclipse.cdt.make.core.buildArguments - - - - org.eclipse.cdt.make.core.buildCommand - make - - - org.eclipse.cdt.make.core.buildLocation - ${workspace_loc://NewMCWifiTest_bsp} - - - org.eclipse.cdt.make.core.cleanBuildTarget - clean - - - org.eclipse.cdt.make.core.contents - org.eclipse.cdt.make.core.activeConfigSettings - - - org.eclipse.cdt.make.core.enableAutoBuild - false - - - org.eclipse.cdt.make.core.enableCleanBuild - true - - - org.eclipse.cdt.make.core.enableFullBuild - true - - - org.eclipse.cdt.make.core.fullBuildTarget - all - - - org.eclipse.cdt.make.core.stopOnError - true - - - org.eclipse.cdt.make.core.useDefaultBuildCmd - true - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder - full,incremental, - - - - - - org.eclipse.cdt.core.cnature - org.eclipse.cdt.managedbuilder.core.managedBuildNature - org.eclipse.cdt.managedbuilder.core.ScannerConfigNature - org.eclipse.cdt.core.ccnature - com.altera.sbtgui.project.SBTGUINature - com.altera.sbtgui.project.SBTGUIBspNature - - diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/Makefile b/MCandWifiTestDE0/NewMCWifiTest_bsp/Makefile deleted file mode 100644 index 963151fd..00000000 --- a/MCandWifiTestDE0/NewMCWifiTest_bsp/Makefile +++ /dev/null @@ -1,805 +0,0 @@ -#------------------------------------------------------------------------------ -# BSP MAKEFILE -# -# This makefile was automatically generated by the nios2-bsp-generate-files -# command. Its purpose is to build a custom Board Support Package (BSP) -# targeting a specific Nios II processor in an SOPC Builder-based design. -# -# To create an application or library Makefile which uses this BSP, try the -# nios2-app-generate-makefile or nios2-lib-generate-makefile commands. -#------------------------------------------------------------------------------ - -#------------------------------------------------------------------------------ -# TOOLS -#------------------------------------------------------------------------------ - -MKDIR := mkdir -p -ECHO := echo -SPACE := $(empty) $(empty) - -#------------------------------------------------------------------------------ -# The adjust-path macro -# -# If COMSPEC is defined, Make is launched from Windows through -# Cygwin. This adjust-path macro will call 'cygpath -u' on all -# paths to ensure they are readable by Make. -# -# If COMSPEC is not defined, Make is launched from *nix, and no adjustment -# is necessary -#------------------------------------------------------------------------------ - -ifndef COMSPEC -ifdef ComSpec -COMSPEC = $(ComSpec) -endif # ComSpec -endif # !COMSPEC - -ifdef COMSPEC - adjust-path = $(subst $(SPACE),\$(SPACE),$(shell cygpath -u "$1")) - adjust-path-mixed = $(subst $(SPACE),\$(SPACE),$(shell cygpath -m "$1")) -else - adjust-path = $(subst $(SPACE),\$(SPACE),$1) - adjust-path-mixed = $(subst $(SPACE),\$(SPACE),$1) -endif - -#------------------------------------------------------------------------------ -# DEFAULT TARGET -# -# The default target, "all", must appear before any other target in the -# Makefile. Note that extra prerequisites are added to the "all" rule later. -#------------------------------------------------------------------------------ -.PHONY: all -all: - @$(ECHO) [BSP build complete] - - -#------------------------------------------------------------------------------ -# PATHS & DIRECTORY NAMES -# -# Explicitly locate absolute path of the BSP root -#------------------------------------------------------------------------------ - -BSP_ROOT_DIR := . - -# Define absolute path to the root of the BSP. -ABS_BSP_ROOT := $(call adjust-path-mixed,$(shell pwd)) - -# Stash all BSP object files here -OBJ_DIR := ./obj - - -#------------------------------------------------------------------------------ -# MANAGED CONTENT -# -# All content between the lines "START MANAGED" and "END MANAGED" below is -# generated based on variables in the BSP settings file when the -# nios2-bsp-generate-files command is invoked. If you wish to persist any -# information pertaining to the build process, it is recomended that you -# utilize the BSP settings mechanism to do so. -# -# Note that most variable assignments in this section have a corresponding BSP -# setting that can be changed by using the nios2-bsp-create-settings or -# nios2-bsp-update-settings command before nios2-bsp-generate-files; if you -# want any variable set to a specific value when this Makefile is re-generated -# (to prevent hand-edits from being over-written), use the BSP settings -# facilities above. -#------------------------------------------------------------------------------ - -#START MANAGED - -# The following TYPE comment allows tools to identify the 'type' of target this -# makefile is associated with. -# TYPE: BSP_PRIVATE_MAKEFILE - -# This following VERSION comment indicates the version of the tool used to -# generate this makefile. A makefile variable is provided for VERSION as well. -# ACDS_VERSION: 12.1sp1 -ACDS_VERSION := 12.1sp1 - -# This following BUILD_NUMBER comment indicates the build number of the tool -# used to generate this makefile. -# BUILD_NUMBER: 243 - -SETTINGS_FILE := settings.bsp -SOPC_FILE := C:/Users/gongal/ARCap/Repository/WifiTestDE0/system.sopcinfo - -#------------------------------------------------------------------------------- -# TOOL & COMMAND DEFINITIONS -# -# The base command for each build operation are expressed here. Additional -# switches may be expressed here. They will run for all instances of the -# utility. -#------------------------------------------------------------------------------- - -# Archiver command. Creates library files. -AR = nios2-elf-ar - -# Assembler command. Note that CC is used for .S files. -AS = nios2-elf-gcc - -# Custom flags only passed to the archiver. This content of this variable is -# directly passed to the archiver rather than the more standard "ARFLAGS". The -# reason for this is that GNU Make assumes some default content in ARFLAGS. -# This setting defines the value of BSP_ARFLAGS in Makefile. -BSP_ARFLAGS = -src - -# Custom flags only passed to the assembler. This setting defines the value of -# BSP_ASFLAGS in Makefile. -BSP_ASFLAGS = -Wa,-gdwarf2 - -# C/C++ compiler debug level. '-g' provides the default set of debug symbols -# typically required to debug a typical application. Omitting '-g' removes -# debug symbols from the ELF. This setting defines the value of -# BSP_CFLAGS_DEBUG in Makefile. -BSP_CFLAGS_DEBUG = -g - -# C/C++ compiler optimization level. "-O0" = no optimization,"-O2" = "normal" -# optimization, etc. "-O0" is recommended for code that you want to debug since -# compiler optimization can remove variables and produce non-sequential -# execution of code while debugging. This setting defines the value of -# BSP_CFLAGS_OPTIMIZATION in Makefile. -BSP_CFLAGS_OPTIMIZATION = -O0 - -# C/C++ compiler warning level. "-Wall" is commonly used.This setting defines -# the value of BSP_CFLAGS_WARNINGS in Makefile. -BSP_CFLAGS_WARNINGS = -Wall - -# C compiler command. -CC = nios2-elf-gcc -xc - -# C++ compiler command. -CXX = nios2-elf-gcc -xc++ - -# Command used to remove files during 'clean' target. -RM = rm -f - - -#------------------------------------------------------------------------------- -# BUILD PRE & POST PROCESS COMMANDS -# -# The following variables are treated as shell commands in the rule -# definitions for each file-type associated with the BSP build, as well as -# commands run at the beginning and end of the entire BSP build operation. -# Pre-process commands are executed before the relevant command (for example, -# a command defined in the "CC_PRE_PROCESS" variable executes before the C -# compiler for building .c files), while post-process commands are executed -# immediately afterwards. -# -# You can view each pre/post-process command in the "Build Rules: All & -# Clean", "Pattern Rules to Build Objects", and "Library Rules" sections of -# this Makefile. -#------------------------------------------------------------------------------- - - -#------------------------------------------------------------------------------- -# BSP SOURCE BUILD SETTINGS (FLAG GENERATION) -# -# Software build settings such as compiler optimization, debug level, warning -# flags, etc., may be defined in the following variables. The variables below -# are concatenated together in the 'Flags' section of this Makefile to form -# final variables of flags passed to the build tools. -# -# These settings are considered private to the BSP and apply to all library & -# driver files in it; they do NOT automatically propagate to, for example, the -# build settings for an application. -# # For additional detail and syntax requirements, please refer to GCC help -# (example: "nios2-elf-gcc --help --verbose"). -# -# Unless indicated otherwise, multiple entries in each variable should be -# space-separated. -#------------------------------------------------------------------------------- - -# Altera HAL alt_sys_init.c generated source file -GENERATED_C_FILES := $(ABS_BSP_ROOT)/alt_sys_init.c -GENERATED_C_LIB_SRCS += alt_sys_init.c - - -#------------------------------------------------------------------------------- -# BSP SOURCE FILE LISTING -# -# All source files that comprise the BSP are listed here, along with path -# information to each file expressed relative to the BSP root. The precise -# list and location of each file is derived from the driver, operating system, -# or software package source file declarations. -# -# Following specification of the source files for each component, driver, etc., -# each source file type (C, assembly, etc.) is concatenated together and used -# to construct a list of objects. Pattern rules to build each object are then -# used to build each file. -#------------------------------------------------------------------------------- - -# altera_avalon_jtag_uart_driver sources root -altera_avalon_jtag_uart_driver_SRCS_ROOT := drivers - -# altera_avalon_jtag_uart_driver sources -altera_avalon_jtag_uart_driver_C_LIB_SRCS := \ - $(altera_avalon_jtag_uart_driver_SRCS_ROOT)/src/altera_avalon_jtag_uart_init.c \ - $(altera_avalon_jtag_uart_driver_SRCS_ROOT)/src/altera_avalon_jtag_uart_read.c \ - $(altera_avalon_jtag_uart_driver_SRCS_ROOT)/src/altera_avalon_jtag_uart_write.c \ - $(altera_avalon_jtag_uart_driver_SRCS_ROOT)/src/altera_avalon_jtag_uart_ioctl.c \ - $(altera_avalon_jtag_uart_driver_SRCS_ROOT)/src/altera_avalon_jtag_uart_fd.c - -# altera_avalon_pio_driver sources root -altera_avalon_pio_driver_SRCS_ROOT := drivers - -# altera_avalon_pio_driver sources -# altera_avalon_sysid_qsys_driver sources root -altera_avalon_sysid_qsys_driver_SRCS_ROOT := drivers - -# altera_avalon_sysid_qsys_driver sources -altera_avalon_sysid_qsys_driver_C_LIB_SRCS := \ - $(altera_avalon_sysid_qsys_driver_SRCS_ROOT)/src/altera_avalon_sysid_qsys.c - -# altera_avalon_timer_driver sources root -altera_avalon_timer_driver_SRCS_ROOT := drivers - -# altera_avalon_timer_driver sources -altera_avalon_timer_driver_C_LIB_SRCS := \ - $(altera_avalon_timer_driver_SRCS_ROOT)/src/altera_avalon_timer_sc.c \ - $(altera_avalon_timer_driver_SRCS_ROOT)/src/altera_avalon_timer_ts.c \ - $(altera_avalon_timer_driver_SRCS_ROOT)/src/altera_avalon_timer_vars.c - -# altera_avalon_uart_driver sources root -altera_avalon_uart_driver_SRCS_ROOT := drivers - -# altera_avalon_uart_driver sources -altera_avalon_uart_driver_C_LIB_SRCS := \ - $(altera_avalon_uart_driver_SRCS_ROOT)/src/altera_avalon_uart_fd.c \ - $(altera_avalon_uart_driver_SRCS_ROOT)/src/altera_avalon_uart_init.c \ - $(altera_avalon_uart_driver_SRCS_ROOT)/src/altera_avalon_uart_ioctl.c \ - $(altera_avalon_uart_driver_SRCS_ROOT)/src/altera_avalon_uart_read.c \ - $(altera_avalon_uart_driver_SRCS_ROOT)/src/altera_avalon_uart_write.c - -# altera_nios2_qsys_ucosii_driver sources root -altera_nios2_qsys_ucosii_driver_SRCS_ROOT := HAL - -# altera_nios2_qsys_ucosii_driver sources -altera_nios2_qsys_ucosii_driver_C_LIB_SRCS := \ - $(altera_nios2_qsys_ucosii_driver_SRCS_ROOT)/src/altera_nios2_qsys_irq.c \ - $(altera_nios2_qsys_ucosii_driver_SRCS_ROOT)/src/alt_busy_sleep.c \ - $(altera_nios2_qsys_ucosii_driver_SRCS_ROOT)/src/alt_irq_vars.c \ - $(altera_nios2_qsys_ucosii_driver_SRCS_ROOT)/src/alt_icache_flush.c \ - $(altera_nios2_qsys_ucosii_driver_SRCS_ROOT)/src/alt_icache_flush_all.c \ - $(altera_nios2_qsys_ucosii_driver_SRCS_ROOT)/src/alt_dcache_flush.c \ - $(altera_nios2_qsys_ucosii_driver_SRCS_ROOT)/src/alt_dcache_flush_all.c \ - $(altera_nios2_qsys_ucosii_driver_SRCS_ROOT)/src/alt_dcache_flush_no_writeback.c \ - $(altera_nios2_qsys_ucosii_driver_SRCS_ROOT)/src/alt_instruction_exception_entry.c \ - $(altera_nios2_qsys_ucosii_driver_SRCS_ROOT)/src/alt_irq_register.c \ - $(altera_nios2_qsys_ucosii_driver_SRCS_ROOT)/src/alt_iic.c \ - $(altera_nios2_qsys_ucosii_driver_SRCS_ROOT)/src/alt_remap_cached.c \ - $(altera_nios2_qsys_ucosii_driver_SRCS_ROOT)/src/alt_remap_uncached.c \ - $(altera_nios2_qsys_ucosii_driver_SRCS_ROOT)/src/alt_uncached_free.c \ - $(altera_nios2_qsys_ucosii_driver_SRCS_ROOT)/src/alt_uncached_malloc.c \ - $(altera_nios2_qsys_ucosii_driver_SRCS_ROOT)/src/alt_do_ctors.c \ - $(altera_nios2_qsys_ucosii_driver_SRCS_ROOT)/src/alt_do_dtors.c \ - $(altera_nios2_qsys_ucosii_driver_SRCS_ROOT)/src/alt_gmon.c \ - $(altera_nios2_qsys_ucosii_driver_SRCS_ROOT)/src/alt_usleep.c \ - $(altera_nios2_qsys_ucosii_driver_SRCS_ROOT)/src/os_cpu_c.c - -altera_nios2_qsys_ucosii_driver_ASM_LIB_SRCS := \ - $(altera_nios2_qsys_ucosii_driver_SRCS_ROOT)/src/alt_exception_entry.S \ - $(altera_nios2_qsys_ucosii_driver_SRCS_ROOT)/src/alt_exception_trap.S \ - $(altera_nios2_qsys_ucosii_driver_SRCS_ROOT)/src/alt_exception_muldiv.S \ - $(altera_nios2_qsys_ucosii_driver_SRCS_ROOT)/src/alt_irq_entry.S \ - $(altera_nios2_qsys_ucosii_driver_SRCS_ROOT)/src/alt_software_exception.S \ - $(altera_nios2_qsys_ucosii_driver_SRCS_ROOT)/src/alt_mcount.S \ - $(altera_nios2_qsys_ucosii_driver_SRCS_ROOT)/src/alt_log_macro.S \ - $(altera_nios2_qsys_ucosii_driver_SRCS_ROOT)/src/crt0.S \ - $(altera_nios2_qsys_ucosii_driver_SRCS_ROOT)/src/os_cpu_a.S - -# hal sources root -hal_SRCS_ROOT := HAL - -# hal sources -hal_C_LIB_SRCS := \ - $(hal_SRCS_ROOT)/src/alt_alarm_start.c \ - $(hal_SRCS_ROOT)/src/alt_close.c \ - $(hal_SRCS_ROOT)/src/alt_dev.c \ - $(hal_SRCS_ROOT)/src/alt_dev_llist_insert.c \ - $(hal_SRCS_ROOT)/src/alt_dma_rxchan_open.c \ - $(hal_SRCS_ROOT)/src/alt_dma_txchan_open.c \ - $(hal_SRCS_ROOT)/src/alt_environ.c \ - $(hal_SRCS_ROOT)/src/alt_errno.c \ - $(hal_SRCS_ROOT)/src/alt_execve.c \ - $(hal_SRCS_ROOT)/src/alt_exit.c \ - $(hal_SRCS_ROOT)/src/alt_fcntl.c \ - $(hal_SRCS_ROOT)/src/alt_fd_lock.c \ - $(hal_SRCS_ROOT)/src/alt_fd_unlock.c \ - $(hal_SRCS_ROOT)/src/alt_find_dev.c \ - $(hal_SRCS_ROOT)/src/alt_find_file.c \ - $(hal_SRCS_ROOT)/src/alt_flash_dev.c \ - $(hal_SRCS_ROOT)/src/alt_fork.c \ - $(hal_SRCS_ROOT)/src/alt_fs_reg.c \ - $(hal_SRCS_ROOT)/src/alt_fstat.c \ - $(hal_SRCS_ROOT)/src/alt_get_fd.c \ - $(hal_SRCS_ROOT)/src/alt_getchar.c \ - $(hal_SRCS_ROOT)/src/alt_getpid.c \ - $(hal_SRCS_ROOT)/src/alt_gettod.c \ - $(hal_SRCS_ROOT)/src/alt_iic_isr_register.c \ - $(hal_SRCS_ROOT)/src/alt_instruction_exception_register.c \ - $(hal_SRCS_ROOT)/src/alt_ioctl.c \ - $(hal_SRCS_ROOT)/src/alt_io_redirect.c \ - $(hal_SRCS_ROOT)/src/alt_irq_handler.c \ - $(hal_SRCS_ROOT)/src/alt_isatty.c \ - $(hal_SRCS_ROOT)/src/alt_kill.c \ - $(hal_SRCS_ROOT)/src/alt_link.c \ - $(hal_SRCS_ROOT)/src/alt_load.c \ - $(hal_SRCS_ROOT)/src/alt_log_printf.c \ - $(hal_SRCS_ROOT)/src/alt_lseek.c \ - $(hal_SRCS_ROOT)/src/alt_main.c \ - $(hal_SRCS_ROOT)/src/alt_open.c \ - $(hal_SRCS_ROOT)/src/alt_printf.c \ - $(hal_SRCS_ROOT)/src/alt_putchar.c \ - $(hal_SRCS_ROOT)/src/alt_putstr.c \ - $(hal_SRCS_ROOT)/src/alt_read.c \ - $(hal_SRCS_ROOT)/src/alt_release_fd.c \ - $(hal_SRCS_ROOT)/src/alt_rename.c \ - $(hal_SRCS_ROOT)/src/alt_sbrk.c \ - $(hal_SRCS_ROOT)/src/alt_settod.c \ - $(hal_SRCS_ROOT)/src/alt_stat.c \ - $(hal_SRCS_ROOT)/src/alt_tick.c \ - $(hal_SRCS_ROOT)/src/alt_times.c \ - $(hal_SRCS_ROOT)/src/alt_unlink.c \ - $(hal_SRCS_ROOT)/src/alt_wait.c \ - $(hal_SRCS_ROOT)/src/alt_write.c - -# ucosii sources root -ucosii_SRCS_ROOT := UCOSII - -# ucosii sources -ucosii_C_LIB_SRCS := \ - $(ucosii_SRCS_ROOT)/src/alt_env_lock.c \ - $(ucosii_SRCS_ROOT)/src/alt_malloc_lock.c \ - $(ucosii_SRCS_ROOT)/src/os_core.c \ - $(ucosii_SRCS_ROOT)/src/os_dbg.c \ - $(ucosii_SRCS_ROOT)/src/os_flag.c \ - $(ucosii_SRCS_ROOT)/src/os_mbox.c \ - $(ucosii_SRCS_ROOT)/src/os_mem.c \ - $(ucosii_SRCS_ROOT)/src/os_mutex.c \ - $(ucosii_SRCS_ROOT)/src/os_q.c \ - $(ucosii_SRCS_ROOT)/src/os_sem.c \ - $(ucosii_SRCS_ROOT)/src/os_task.c \ - $(ucosii_SRCS_ROOT)/src/os_time.c \ - $(ucosii_SRCS_ROOT)/src/os_tmr.c - - -# Assemble all component C source files -COMPONENT_C_LIB_SRCS += \ - $(altera_avalon_jtag_uart_driver_C_LIB_SRCS) \ - $(altera_avalon_sysid_qsys_driver_C_LIB_SRCS) \ - $(altera_avalon_timer_driver_C_LIB_SRCS) \ - $(altera_avalon_uart_driver_C_LIB_SRCS) \ - $(altera_nios2_qsys_ucosii_driver_C_LIB_SRCS) \ - $(hal_C_LIB_SRCS) \ - $(ucosii_C_LIB_SRCS) - -# Assemble all component assembly source files -COMPONENT_ASM_LIB_SRCS += \ - $(altera_nios2_qsys_ucosii_driver_ASM_LIB_SRCS) - -# Assemble all component C++ source files -COMPONENT_CPP_LIB_SRCS += \ - -#END MANAGED - -#------------------------------------------------------------------------------ -# PUBLIC.MK -# -# The generated public.mk file contains BSP information that is shared with -# other external makefiles, such as a Nios II application makefile. System- -# dependent information such as hardware-specific compiler flags and -# simulation file generation are stored here. -# -# In addition, public.mk contains include paths that various software, -# such as a device driver, may need for the C compiler. These paths are -# written to public.mk with respect to the BSP root. In public.mk, each -# path is prefixed with a special variable, $(ALT_LIBRARY_ROOT_DIR). The -# purpose of this variable is to allow an external Makefile to append on -# path information to precisely locate paths expressed in public.mk -# Since this is the BSP Makefile, we set ALT_LIBRARY_ROOT_DIR to point right -# here ("."), at the BSP root. -# -# ALT_LIBRARY_ROOT_DIR must always be set before public.mk is included. -#------------------------------------------------------------------------------ -ALT_LIBRARY_ROOT_DIR := . -include public.mk - - -#------------------------------------------------------------------------------ -# FLAGS -# -# Include paths for BSP files are written into the public.mk file and must -# be added to the existing list of pre-processor flags. In addition, "hooks" -# for standard flags left intentionally empty (CFLAGS, CPPFLAGS, ASFLAGS, -# and CXXFLAGS) are provided for conveniently adding to the relevant flags -# on the command-line or via script that calls make. -#------------------------------------------------------------------------------ -# Assemble final list of compiler flags from generated content -BSP_CFLAGS += \ - $(BSP_CFLAGS_DEFINED_SYMBOLS) \ - $(BSP_CFLAGS_UNDEFINED_SYMBOLS) \ - $(BSP_CFLAGS_OPTIMIZATION) \ - $(BSP_CFLAGS_DEBUG) \ - $(BSP_CFLAGS_WARNINGS) \ - $(BSP_CFLAGS_USER_FLAGS) \ - $(ALT_CFLAGS) \ - $(CFLAGS) - -# Make ready the final list of include directories and other C pre-processor -# flags. Each include path is made ready by prefixing it with "-I". -BSP_CPPFLAGS += \ - $(addprefix -I, $(BSP_INC_DIRS)) \ - $(addprefix -I, $(ALT_INCLUDE_DIRS)) \ - $(ALT_CPPFLAGS) \ - $(CPPFLAGS) - -# Finish off assembler flags with any user-provided flags -BSP_ASFLAGS += $(ASFLAGS) - -# Finish off C++ flags with any user-provided flags -BSP_CXXFLAGS += $(CXXFLAGS) - -# And finally, the ordered list -C_SRCS += $(GENERATED_C_LIB_SRCS) \ - $(COMPONENT_C_LIB_SRCS) - -CXX_SRCS += $(GENERATED_CPP_LIB_SRCS) \ - $(COMPONENT_CPP_LIB_SRCS) - -ASM_SRCS += $(GENERATED_ASM_LIB_SRCS) \ - $(COMPONENT_ASM_LIB_SRCS) - - -#------------------------------------------------------------------------------ -# LIST OF GENERATED FILES -# -# A Nios II BSP relies on the generation of several source files used -# by both the BSP and any applications referencing the BSP. -#------------------------------------------------------------------------------ - - -GENERATED_H_FILES := $(ABS_BSP_ROOT)/system.h - -GENERATED_LINKER_SCRIPT := $(ABS_BSP_ROOT)/linker.x - -GENERATED_FILES += $(GENERATED_H_FILES) \ - $(GENERATED_LINKER_SCRIPT) - - -#------------------------------------------------------------------------------ -# SETUP TO BUILD OBJECTS -# -# List of object files which are to be built. This is constructed from the input -# list of C source files (C_SRCS), C++ source files (CXX_SRCS), and assembler -# source file (ASM_SRCS). The permitted file extensions are: -# -# .c .C - for C files -# .cxx .cc .cpp .CXX .CC .CPP - for C++ files -# .S .s - for assembly files -# -# Extended description: The list of objects is a sorted list (duplicates -# removed) of all possible objects, placed beneath the ./obj directory, -# including any path information stored in the "*_SRCS" variable. The -# "patsubst" commands are used to concatenate together multiple file suffix -# types for common files (i.e. c++ as .cxx, .cc, .cpp). -# -# File extensions are case-insensitive in build rules with the exception of -# assembly sources. Nios II assembly sources with the ".S" extension are first -# run through the C preprocessor. Sources with the ".s" extension are not. -#------------------------------------------------------------------------------ -OBJS = $(sort $(addprefix $(OBJ_DIR)/, \ - $(patsubst %.c, %.o, $(patsubst %.C, %.o, $(C_SRCS))) \ - $(patsubst %.cxx, %.o, $(patsubst %.CXX, %.o, \ - $(patsubst %.cc, %.o, $(patsubst %.CC, %.o, \ - $(patsubst %.cpp, %.o, $(patsubst %.CPP, %.o, \ - $(CXX_SRCS) )))))) \ - $(patsubst %.S, %.o, $(patsubst %.s, %.o, $(ASM_SRCS))) )) - -# List of dependancy files for each object file. -DEPS = $(OBJS:.o=.d) - - -# Rules to force your project to rebuild or relink -# .force_relink file will cause any application that depends on this project to relink -# .force_rebuild file will cause this project to rebuild object files -# .force_rebuild_all file will cause this project and any project that depends on this project to rebuild object files - -FORCE_RELINK_DEP := .force_relink -FORCE_REBUILD_DEP := .force_rebuild -FORCE_REBUILD_ALL_DEP := .force_rebuild_all -FORCE_REBUILD_DEP_LIST := $(FORCE_RELINK_DEP) $(FORCE_REBUILD_DEP) $(FORCE_REBUILD_ALL_DEP) - -$(FORCE_REBUILD_DEP_LIST): - -$(OBJS): $(wildcard $(FORCE_REBUILD_DEP)) $(wildcard $(FORCE_REBUILD_ALL_DEP)) - - -#------------------------------------------------------------------------------ -# BUILD RULES: ALL & CLEAN -#------------------------------------------------------------------------------ -.DELETE_ON_ERROR: - -.PHONY: all -all: build_pre_process -all: Makefile $(GENERATED_FILES) $(BSP_LIB) $(NEWLIB_DIR) -all: build_post_process - - -# clean: remove .o/.a/.d -.PHONY: clean -clean: - @$(RM) -r $(BSP_LIB) $(OBJ_DIR) $(FORCE_REBUILD_DEP_LIST) -ifneq ($(wildcard $(NEWLIB_DIR)),) - @$(RM) -r $(NEWLIB_DIR) -endif - @$(ECHO) [BSP clean complete] - - -#------------------------------------------------------------------------------ -# BUILD PRE/POST PROCESS -#------------------------------------------------------------------------------ -build_pre_process : - $(BUILD_PRE_PROCESS) - -build_post_process : - $(BUILD_POST_PROCESS) - -.PHONY: build_pre_process build_post_process - - - -#------------------------------------------------------------------------------ -# MAKEFILE UP TO DATE? -# -# Is this very Makefile up to date? Someone may have changed the BSP settings -# file or the associated target hardware. -#------------------------------------------------------------------------------ -# Skip this check when clean is the only target -ifneq ($(MAKECMDGOALS),clean) - -ifneq ($(wildcard $(SETTINGS_FILE)),$(SETTINGS_FILE)) -$(warning Warning: BSP Settings File $(SETTINGS_FILE) could not be found.) -endif - -Makefile: $(wildcard $(SETTINGS_FILE)) - @$(ECHO) Makefile not up to date. - @$(ECHO) $(SETTINGS_FILE) has been modified since the BSP Makefile was generated. - @$(ECHO) - @$(ECHO) Generate the BSP to update the Makefile, and then build again. - @$(ECHO) - @$(ECHO) To generate from Eclipse: - @$(ECHO) " 1. Right-click the BSP project." - @$(ECHO) " 2. In the Nios II Menu, click Generate BSP." - @$(ECHO) - @$(ECHO) To generate from the command line: - @$(ECHO) " nios2-bsp-generate-files --settings= --bsp-dir=" - @$(ECHO) - @exit 1 - -ifneq ($(wildcard $(SOPC_FILE)),$(SOPC_FILE)) -$(warning Warning: SOPC File $(SOPC_FILE) could not be found.) -endif - -public.mk: $(wildcard $(SOPC_FILE)) - @$(ECHO) Makefile not up to date. - @$(ECHO) $(SOPC_FILE) has been modified since the BSP was generated. - @$(ECHO) - @$(ECHO) Generate the BSP to update the Makefile, and then build again. - @$(ECHO) - @$(ECHO) To generate from Eclipse: - @$(ECHO) " 1. Right-click the BSP project." - @$(ECHO) " 2. In the Nios II Menu, click Generate BSP." - @$(ECHO) - @$(ECHO) To generate from the command line: - @$(ECHO) " nios2-bsp-generate-files --settings= --bsp-dir=" - @$(ECHO) - @exit 1 - -endif # $(MAKECMDGOALS) != clean - -#------------------------------------------------------------------------------ -# PATTERN RULES TO BUILD OBJECTS -#------------------------------------------------------------------------------ -$(OBJ_DIR)/%.o: %.c - @$(ECHO) Compiling $( - -/* - * Device headers - */ - -#include "altera_nios2_qsys_irq.h" -#include "altera_avalon_jtag_uart.h" -#include "altera_avalon_sysid_qsys.h" -#include "altera_avalon_timer.h" -#include "altera_avalon_uart.h" - -/* - * Allocate the device storage - */ - -ALTERA_NIOS2_QSYS_IRQ_INSTANCE ( CPU, cpu); -ALTERA_AVALON_JTAG_UART_INSTANCE ( JTAG_UART_0, jtag_uart_0); -ALTERA_AVALON_SYSID_QSYS_INSTANCE ( SYSID, sysid); -ALTERA_AVALON_TIMER_INSTANCE ( SYS_CLK_TIMER, sys_clk_timer); -ALTERA_AVALON_UART_INSTANCE ( UART_MC, uart_mc); -ALTERA_AVALON_UART_INSTANCE ( UART_WIFI, uart_wifi); - -/* - * Initialize the interrupt controller devices - * and then enable interrupts in the CPU. - * Called before alt_sys_init(). - * The "base" parameter is ignored and only - * present for backwards-compatibility. - */ - -void alt_irq_init ( const void* base ) -{ - ALTERA_NIOS2_QSYS_IRQ_INIT ( CPU, cpu); - alt_irq_cpu_enable_interrupts(); -} - -/* - * Initialize the non-interrupt controller devices. - * Called after alt_irq_init(). - */ - -void alt_sys_init( void ) -{ - ALTERA_AVALON_TIMER_INIT ( SYS_CLK_TIMER, sys_clk_timer); - ALTERA_AVALON_JTAG_UART_INIT ( JTAG_UART_0, jtag_uart_0); - ALTERA_AVALON_SYSID_QSYS_INIT ( SYSID, sysid); - ALTERA_AVALON_UART_INIT ( UART_MC, uart_mc); - ALTERA_AVALON_UART_INIT ( UART_WIFI, uart_wifi); -} diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/create-this-bsp b/MCandWifiTestDE0/NewMCWifiTest_bsp/create-this-bsp deleted file mode 100644 index fcf1ace1..00000000 --- a/MCandWifiTestDE0/NewMCWifiTest_bsp/create-this-bsp +++ /dev/null @@ -1,49 +0,0 @@ -#!/bin/bash -# -# This script creates the ucosii_net_zipfs Board Support Package (BSP). - -BSP_TYPE=ucosii -BSP_DIR=. -SOPC_DIR=C:/Users/gongal/ARCap/Repository/WifiTestDE0/ -SOPC_FILE=C:/Users/gongal/ARCap/Repository/WifiTestDE0/system.sopcinfo -NIOS2_BSP_ARGS="" -CPU_NAME= - - -# Don't run make if create-this-app script is called with --no-make arg -SKIP_MAKE= -while [ $# -gt 0 ] -do - case "$1" in - --no-make) - SKIP_MAKE=1 - ;; - *) - NIOS2_BSP_ARGS="$NIOS2_BSP_ARGS $1" - ;; - esac - shift -done - - -# Run nios2-bsp utility to create a ucosii BSP in this directory -# for the system with a .sopc file in $SOPC_FILE. -# Deprecating $SOPC_DIR in 10.1. Multiple .sopcinfo files in a directory may exist. - -if [ -z "$SOPC_FILE" ]; then - echo "WARNING: Use of a directory for locating a .sopcinfo file is deprecated in 10.1. Multiple .sopcinfo files may exist. You must specify the full .sopcinfo path." - cmd="nios2-bsp $BSP_TYPE $BSP_DIR $SOPC_DIR $NIOS2_BSP_ARGS $CPU_NAME" -else - cmd="nios2-bsp $BSP_TYPE $BSP_DIR $SOPC_FILE $NIOS2_BSP_ARGS $CPU_NAME" -fi - - -echo "create-this-bsp: Running \"$cmd\"" -$cmd || { - echo "$cmd failed" - exit 1 -} -if [ -z "$SKIP_MAKE" ]; then - echo "create-this-bsp: Running make" - make -fi diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/linker.h b/MCandWifiTestDE0/NewMCWifiTest_bsp/linker.h deleted file mode 100644 index bae9a01f..00000000 --- a/MCandWifiTestDE0/NewMCWifiTest_bsp/linker.h +++ /dev/null @@ -1,101 +0,0 @@ -/* - * linker.h - Linker script mapping information - * - * Machine generated for CPU 'cpu' in SOPC Builder design 'system' - * SOPC Builder design path: C:/Users/gongal/ARCap/Repository/WifiTestDE0/system.sopcinfo - * - * Generated: Sun Mar 02 15:16:24 MST 2014 - */ - -/* - * DO NOT MODIFY THIS FILE - * - * Changing this file will have subtle consequences - * which will almost certainly lead to a nonfunctioning - * system. If you do modify this file, be aware that your - * changes will be overwritten and lost when this file - * is generated again. - * - * DO NOT MODIFY THIS FILE - */ - -/* - * License Agreement - * - * Copyright (c) 2008 - * Altera Corporation, San Jose, California, USA. - * All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - * This agreement shall be governed in all respects by the laws of the State - * of California and by the laws of the United States of America. - */ - -#ifndef __LINKER_H_ -#define __LINKER_H_ - - -/* - * BSP controls alt_load() behavior in crt0. - * - */ - -#define ALT_LOAD_EXPLICITLY_CONTROLLED - - -/* - * Base address and span (size in bytes) of each linker region - * - */ - -#define RESET_REGION_BASE 0x1000000 -#define RESET_REGION_SPAN 32 -#define SDRAM_REGION_BASE 0x1000020 -#define SDRAM_REGION_SPAN 16777184 - - -/* - * Devices associated with code sections - * - */ - -#define ALT_EXCEPTIONS_DEVICE SDRAM -#define ALT_RESET_DEVICE SDRAM -#define ALT_RODATA_DEVICE SDRAM -#define ALT_RWDATA_DEVICE SDRAM -#define ALT_TEXT_DEVICE SDRAM - - -/* - * Initialization code at the reset address is allowed (e.g. no external bootloader). - * - */ - -#define ALT_ALLOW_CODE_AT_RESET - - -/* - * The alt_load() facility is called from crt0 to copy sections into RAM. - * - */ - -#define ALT_LOAD_COPY_RWDATA - -#endif /* __LINKER_H_ */ diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/linker.x b/MCandWifiTestDE0/NewMCWifiTest_bsp/linker.x deleted file mode 100644 index 3be3aca4..00000000 --- a/MCandWifiTestDE0/NewMCWifiTest_bsp/linker.x +++ /dev/null @@ -1,385 +0,0 @@ -/* - * linker.x - Linker script - * - * Machine generated for CPU 'cpu' in SOPC Builder design 'system' - * SOPC Builder design path: C:/Users/gongal/ARCap/Repository/WifiTestDE0/system.sopcinfo - * - * Generated: Sun Mar 02 15:16:24 MST 2014 - */ - -/* - * DO NOT MODIFY THIS FILE - * - * Changing this file will have subtle consequences - * which will almost certainly lead to a nonfunctioning - * system. If you do modify this file, be aware that your - * changes will be overwritten and lost when this file - * is generated again. - * - * DO NOT MODIFY THIS FILE - */ - -/* - * License Agreement - * - * Copyright (c) 2008 - * Altera Corporation, San Jose, California, USA. - * All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - * This agreement shall be governed in all respects by the laws of the State - * of California and by the laws of the United States of America. - */ - -MEMORY -{ - reset : ORIGIN = 0x1000000, LENGTH = 32 - sdram : ORIGIN = 0x1000020, LENGTH = 16777184 -} - -/* Define symbols for each memory base-address */ -__alt_mem_sdram = 0x1000000; - -OUTPUT_FORMAT( "elf32-littlenios2", - "elf32-littlenios2", - "elf32-littlenios2" ) -OUTPUT_ARCH( nios2 ) -ENTRY( _start ) - -/* - * The alt_load() facility is enabled. This typically happens when there isn't - * an external bootloader (e.g. flash bootloader). - * The LMA (aka physical address) of each loaded section is - * set to the .text memory device. - * The HAL alt_load() routine called from crt0 copies sections from - * the .text memory to RAM as needed. - */ - -SECTIONS -{ - - /* - * Output sections associated with reset and exceptions (they have to be first) - */ - - .entry : - { - KEEP (*(.entry)) - } > reset - - .exceptions : - { - PROVIDE (__ram_exceptions_start = ABSOLUTE(.)); - . = ALIGN(0x20); - KEEP (*(.irq)); - KEEP (*(.exceptions.entry.label)); - KEEP (*(.exceptions.entry.user)); - KEEP (*(.exceptions.entry)); - KEEP (*(.exceptions.irqtest.user)); - KEEP (*(.exceptions.irqtest)); - KEEP (*(.exceptions.irqhandler.user)); - KEEP (*(.exceptions.irqhandler)); - KEEP (*(.exceptions.irqreturn.user)); - KEEP (*(.exceptions.irqreturn)); - KEEP (*(.exceptions.notirq.label)); - KEEP (*(.exceptions.notirq.user)); - KEEP (*(.exceptions.notirq)); - KEEP (*(.exceptions.soft.user)); - KEEP (*(.exceptions.soft)); - KEEP (*(.exceptions.unknown.user)); - KEEP (*(.exceptions.unknown)); - KEEP (*(.exceptions.exit.label)); - KEEP (*(.exceptions.exit.user)); - KEEP (*(.exceptions.exit)); - KEEP (*(.exceptions)); - PROVIDE (__ram_exceptions_end = ABSOLUTE(.)); - } > sdram - - PROVIDE (__flash_exceptions_start = LOADADDR(.exceptions)); - - .text : - { - /* - * All code sections are merged into the text output section, along with - * the read only data sections. - * - */ - - PROVIDE (stext = ABSOLUTE(.)); - - *(.interp) - *(.hash) - *(.dynsym) - *(.dynstr) - *(.gnu.version) - *(.gnu.version_d) - *(.gnu.version_r) - *(.rel.init) - *(.rela.init) - *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) - *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) - *(.rel.fini) - *(.rela.fini) - *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) - *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) - *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) - *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) - *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) - *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) - *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) - *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) - *(.rel.ctors) - *(.rela.ctors) - *(.rel.dtors) - *(.rela.dtors) - *(.rel.got) - *(.rela.got) - *(.rel.sdata .rel.sdata.* .rel.gnu.linkonce.s.*) - *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*) - *(.rel.sbss .rel.sbss.* .rel.gnu.linkonce.sb.*) - *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*) - *(.rel.sdata2 .rel.sdata2.* .rel.gnu.linkonce.s2.*) - *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*) - *(.rel.sbss2 .rel.sbss2.* .rel.gnu.linkonce.sb2.*) - *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*) - *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) - *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) - *(.rel.plt) - *(.rela.plt) - *(.rel.dyn) - - KEEP (*(.init)) - *(.plt) - *(.text .stub .text.* .gnu.linkonce.t.*) - - /* .gnu.warning sections are handled specially by elf32.em. */ - - *(.gnu.warning.*) - KEEP (*(.fini)) - PROVIDE (__etext = ABSOLUTE(.)); - PROVIDE (_etext = ABSOLUTE(.)); - PROVIDE (etext = ABSOLUTE(.)); - - *(.eh_frame_hdr) - /* Ensure the __preinit_array_start label is properly aligned. We - could instead move the label definition inside the section, but - the linker would then create the section even if it turns out to - be empty, which isn't pretty. */ - . = ALIGN(4); - PROVIDE (__preinit_array_start = ABSOLUTE(.)); - *(.preinit_array) - PROVIDE (__preinit_array_end = ABSOLUTE(.)); - PROVIDE (__init_array_start = ABSOLUTE(.)); - *(.init_array) - PROVIDE (__init_array_end = ABSOLUTE(.)); - PROVIDE (__fini_array_start = ABSOLUTE(.)); - *(.fini_array) - PROVIDE (__fini_array_end = ABSOLUTE(.)); - SORT(CONSTRUCTORS) - KEEP (*(.eh_frame)) - *(.gcc_except_table) - *(.dynamic) - PROVIDE (__CTOR_LIST__ = ABSOLUTE(.)); - KEEP (*(.ctors)) - KEEP (*(SORT(.ctors.*))) - PROVIDE (__CTOR_END__ = ABSOLUTE(.)); - PROVIDE (__DTOR_LIST__ = ABSOLUTE(.)); - KEEP (*(.dtors)) - KEEP (*(SORT(.dtors.*))) - PROVIDE (__DTOR_END__ = ABSOLUTE(.)); - KEEP (*(.jcr)) - . = ALIGN(4); - } > sdram = 0x3a880100 /* Nios II NOP instruction */ - - .rodata : - { - PROVIDE (__ram_rodata_start = ABSOLUTE(.)); - . = ALIGN(4); - *(.rodata .rodata.* .gnu.linkonce.r.*) - *(.rodata1) - . = ALIGN(4); - PROVIDE (__ram_rodata_end = ABSOLUTE(.)); - } > sdram - - PROVIDE (__flash_rodata_start = LOADADDR(.rodata)); - - /* - * - * This section's LMA is set to the .text region. - * crt0 will copy to this section's specified mapped region virtual memory address (VMA) - * - * .rwdata region equals the .text region, and is set to be loaded into .text region. - * This requires two copies of .rwdata in the .text region. One read writable at VMA. - * and one read-only at LMA. crt0 will copy from LMA to VMA on reset - * - */ - - .rwdata LOADADDR (.rodata) + SIZEOF (.rodata) : AT ( LOADADDR (.rodata) + SIZEOF (.rodata)+ SIZEOF (.rwdata) ) - { - PROVIDE (__ram_rwdata_start = ABSOLUTE(.)); - . = ALIGN(4); - *(.got.plt) *(.got) - *(.data1) - *(.data .data.* .gnu.linkonce.d.*) - - _gp = ABSOLUTE(. + 0x8000); - PROVIDE(gp = _gp); - - *(.rwdata .rwdata.*) - *(.sdata .sdata.* .gnu.linkonce.s.*) - *(.sdata2 .sdata2.* .gnu.linkonce.s2.*) - - . = ALIGN(4); - _edata = ABSOLUTE(.); - PROVIDE (edata = ABSOLUTE(.)); - PROVIDE (__ram_rwdata_end = ABSOLUTE(.)); - } > sdram - - PROVIDE (__flash_rwdata_start = LOADADDR(.rwdata)); - - /* - * - * This section's LMA is set to the .text region. - * crt0 will copy to this section's specified mapped region virtual memory address (VMA) - * - */ - - .bss LOADADDR (.rwdata) + SIZEOF (.rwdata) : AT ( LOADADDR (.rwdata) + SIZEOF (.rwdata) ) - { - __bss_start = ABSOLUTE(.); - PROVIDE (__sbss_start = ABSOLUTE(.)); - PROVIDE (___sbss_start = ABSOLUTE(.)); - - *(.dynsbss) - *(.sbss .sbss.* .gnu.linkonce.sb.*) - *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*) - *(.scommon) - - PROVIDE (__sbss_end = ABSOLUTE(.)); - PROVIDE (___sbss_end = ABSOLUTE(.)); - - *(.dynbss) - *(.bss .bss.* .gnu.linkonce.b.*) - *(COMMON) - - . = ALIGN(4); - __bss_end = ABSOLUTE(.); - } > sdram - - /* - * - * One output section mapped to the associated memory device for each of - * the available memory devices. These are not used by default, but can - * be used by user applications by using the .section directive. - * - * The output section used for the heap is treated in a special way, - * i.e. the symbols "end" and "_end" are added to point to the heap start. - * - * Because alt_load() is enabled, these sections have - * their LMA set to be loaded into the .text memory region. - * However, the alt_load() code will NOT automatically copy - * these sections into their mapped memory region. - * - */ - - /* - * - * This section's LMA is set to the .text region. - * crt0 will copy to this section's specified mapped region virtual memory address (VMA) - * - */ - - .sdram LOADADDR (.bss) + SIZEOF (.bss) : AT ( LOADADDR (.bss) + SIZEOF (.bss) ) - { - PROVIDE (_alt_partition_sdram_start = ABSOLUTE(.)); - *(.sdram. sdram.*) - . = ALIGN(4); - PROVIDE (_alt_partition_sdram_end = ABSOLUTE(.)); - _end = ABSOLUTE(.); - end = ABSOLUTE(.); - __alt_stack_base = ABSOLUTE(.); - } > sdram - - PROVIDE (_alt_partition_sdram_load_addr = LOADADDR(.sdram)); - - /* - * Stabs debugging sections. - * - */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - /* DWARF debug sections. - Symbols in the DWARF debugging sections are relative to the beginning - of the section so we begin them at 0. */ - /* DWARF 1 */ - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - /* GNU DWARF 1 extensions */ - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - /* DWARF 1.1 and DWARF 2 */ - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - /* DWARF 2 */ - .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - /* SGI/MIPS DWARF 2 extensions */ - .debug_weaknames 0 : { *(.debug_weaknames) } - .debug_funcnames 0 : { *(.debug_funcnames) } - .debug_typenames 0 : { *(.debug_typenames) } - .debug_varnames 0 : { *(.debug_varnames) } - - /* Altera debug extensions */ - .debug_alt_sim_info 0 : { *(.debug_alt_sim_info) } -} - -/* provide a pointer for the stack */ - -/* - * Don't override this, override the __alt_stack_* symbols instead. - */ -__alt_data_end = 0x2000000; - -/* - * The next two symbols define the location of the default stack. You can - * override them to move the stack to a different memory. - */ -PROVIDE( __alt_stack_pointer = __alt_data_end ); -PROVIDE( __alt_stack_limit = __alt_stack_base ); - -/* - * This symbol controls where the start of the heap is. If the stack is - * contiguous with the heap then the stack will contract as memory is - * allocated to the heap. - * Override this symbol to put the heap in a different memory. - */ -PROVIDE( __alt_heap_start = end ); -PROVIDE( __alt_heap_limit = 0x2000000 ); diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/memory.gdb b/MCandWifiTestDE0/NewMCWifiTest_bsp/memory.gdb deleted file mode 100644 index fb4566ef..00000000 --- a/MCandWifiTestDE0/NewMCWifiTest_bsp/memory.gdb +++ /dev/null @@ -1,50 +0,0 @@ -# memory.gdb - GDB memory region definitions -# -# Machine generated for CPU 'cpu' in SOPC Builder design 'system' -# SOPC Builder design path: C:/Users/gongal/ARCap/Repository/WifiTestDE0/system.sopcinfo -# -# Generated: Sun Mar 02 15:16:24 MST 2014 - -# DO NOT MODIFY THIS FILE -# -# Changing this file will have subtle consequences -# which will almost certainly lead to a nonfunctioning -# system. If you do modify this file, be aware that your -# changes will be overwritten and lost when this file -# is generated again. -# -# DO NOT MODIFY THIS FILE - -# License Agreement -# -# Copyright (c) 2008 -# Altera Corporation, San Jose, California, USA. -# All rights reserved. -# -# Permission is hereby granted, free of charge, to any person obtaining a -# copy of this software and associated documentation files (the "Software"), -# to deal in the Software without restriction, including without limitation -# the rights to use, copy, modify, merge, publish, distribute, sublicense, -# and/or sell copies of the Software, and to permit persons to whom the -# Software is furnished to do so, subject to the following conditions: -# -# The above copyright notice and this permission notice shall be included in -# all copies or substantial portions of the Software. -# -# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER -# DEALINGS IN THE SOFTWARE. -# -# This agreement shall be governed in all respects by the laws of the State -# of California and by the laws of the United States of America. - -# Define memory regions for each memory connected to the CPU. -# The cache attribute is specified which improves GDB performance -# by allowing GDB to cache memory contents on the host. - -# sdram -memory 0x1000000 0x2000000 cache diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/public.mk b/MCandWifiTestDE0/NewMCWifiTest_bsp/public.mk deleted file mode 100644 index 11bb9773..00000000 --- a/MCandWifiTestDE0/NewMCWifiTest_bsp/public.mk +++ /dev/null @@ -1,402 +0,0 @@ -#------------------------------------------------------------------------------ -# BSP "PUBLIC" MAKEFILE CONTENT -# -# This file is intended to be included in an application or library -# Makefile that is using this BSP. You can create such a Makefile with -# the nios2-app-generate-makefile or nios2-lib-generate-makefile -# commands. -# -# The following variables must be defined before including this file: -# -# ALT_LIBRARY_ROOT_DIR -# Contains the path to the BSP top-level (aka root) directory -#------------------------------------------------------------------------------ - -#------------------------------------------------------------------------------ -# PATHS -#------------------------------------------------------------------------------ - - - -# Path to the provided linker script. -BSP_LINKER_SCRIPT := $(ALT_LIBRARY_ROOT_DIR)/linker.x - -# Include paths: -# The path to root of all header files that a library wishes to make -# available for an application's use is specified here. Note that this -# may not be *all* folders within a hierarchy. For example, if it is -# desired that the application developer type: -# #include -# #include -# With files laid out like this: -# /inc/sockets.h -# /inc/ip/tcpip.h -# -# Then, only /inc need be added to the list of include -# directories. Alternatively, if you wish to be able to directly include -# all files in a hierarchy, separate paths to each folder in that -# hierarchy must be defined. - -# The following are the "base" set of include paths for a BSP. -# These paths are appended to the list that individual software -# components, drivers, etc., add in the generated portion of this -# file (below). -ALT_INCLUDE_DIRS_TO_APPEND += \ - $(ALT_LIBRARY_ROOT_DIR) \ - $(ALT_LIBRARY_ROOT_DIR)/drivers/inc - -# Additions to linker library search-path: -# Here we provide a path to "our self" for the application to construct a -# "-L " out of. This should contain a list of directories, -# relative to the library root, of all directories with .a files to link -# against. -ALT_LIBRARY_DIRS += $(ALT_LIBRARY_ROOT_DIR) - - -#------------------------------------------------------------------------------ -# COMPILATION FLAGS -#------------------------------------------------------------------------------ -# Default C pre-processor flags for a BSP: -ALT_CPPFLAGS += -DSYSTEM_BUS_WIDTH=32 \ - -pipe - - -#------------------------------------------------------------------------------ -# MANAGED CONTENT -# -# All content between the lines "START MANAGED" and "END MANAGED" below is -# generated based on variables in the BSP settings file when the -# nios2-bsp-generate-files command is invoked. If you wish to persist any -# information pertaining to the build process, it is recomended that you -# utilize the BSP settings mechanism to do so. -#------------------------------------------------------------------------------ -#START MANAGED - -# The following TYPE comment allows tools to identify the 'type' of target this -# makefile is associated with. -# TYPE: BSP_PUBLIC_MAKEFILE - -# This following VERSION comment indicates the version of the tool used to -# generate this makefile. A makefile variable is provided for VERSION as well. -# ACDS_VERSION: 12.1sp1 -ACDS_VERSION := 12.1sp1 - -# This following BUILD_NUMBER comment indicates the build number of the tool -# used to generate this makefile. -# BUILD_NUMBER: 243 - -# Quartus Generated JDI File. Required for resolving node instance ID's with -# design component names. -JDI_FILE := C:/Users/gongal/ARCap/Repository/WifiTestDE0/de0_nano_system.jdi - -# Qsys--generated SOPCINFO file. Required for resolving node instance ID's with -# design component names. -SOPCINFO_FILE := C:/Users/gongal/ARCap/Repository/WifiTestDE0/system.sopcinfo - -# Big-Endian operation. -# setting BIG_ENDIAN is false -ALT_CFLAGS += -EL - -# Path to the provided C language runtime initialization code. -BSP_CRT0 := $(ALT_LIBRARY_ROOT_DIR)/obj/HAL/src/crt0.o - -# Name of BSP library as provided to linker using the "-msys-lib" flag or -# linker script GROUP command. -# setting BSP_SYS_LIB is ucosii_bsp -BSP_SYS_LIB := ucosii_bsp -ELF_PATCH_FLAG += --thread_model ucosii - -# Type identifier of the BSP library -# setting BSP_TYPE is ucosii -ALT_CPPFLAGS += -D__hal__ -BSP_TYPE := ucosii - -# CPU Name -# setting CPU_NAME is cpu -CPU_NAME = cpu -ELF_PATCH_FLAG += --cpu_name $(CPU_NAME) - -# Hardware Divider present. -# setting HARDWARE_DIVIDE is false -ALT_CFLAGS += -mno-hw-div - -# Hardware Multiplier present. -# setting HARDWARE_MULTIPLY is true -ALT_CFLAGS += -mhw-mul - -# Hardware Mulx present. -# setting HARDWARE_MULX is false -ALT_CFLAGS += -mno-hw-mulx - -# Debug Core present. -# setting HAS_DEBUG_CORE is true -CPU_HAS_DEBUG_CORE = 1 - -# Qsys generated design -# setting QSYS is 1 -QSYS := 1 -ELF_PATCH_FLAG += --qsys true - -# Design Name -# setting SOPC_NAME is system -SOPC_NAME := system - -# SopcBuilder Simulation Enabled -# setting SOPC_SIMULATION_ENABLED is false -ELF_PATCH_FLAG += --simulation_enabled false - -# The SOPC System ID -# setting SOPC_SYSID is 0 -SOPC_SYSID_FLAG += --id=0 -ELF_PATCH_FLAG += --id 0 - -# The SOPC System ID Base Address -# setting SOPC_SYSID_BASE_ADDRESS is 0x20010b8 -SOPC_SYSID_FLAG += --sidp=0x20010b8 -ELF_PATCH_FLAG += --sidp 0x20010b8 - -# The SOPC Timestamp -# setting SOPC_TIMESTAMP is 1393717012 -SOPC_SYSID_FLAG += --timestamp=1393717012 -ELF_PATCH_FLAG += --timestamp 1393717012 - -# Small-footprint (polled mode) driver none -# setting altera_avalon_jtag_uart_driver.enable_small_driver is false - -# Enable driver ioctl() support. This feature is not compatible with the -# 'small' driver; ioctl() support will not be compiled if either the UART -# 'enable_small_driver' or HAL 'enable_reduced_device_drivers' settings are -# enabled. none -# setting altera_avalon_uart_driver.enable_ioctl is false - -# Small-footprint (polled mode) driver none -# setting altera_avalon_uart_driver.enable_small_driver is false - -# Build a custom version of newlib with the specified space-separated compiler -# flags. The custom newlib build will be placed in the <bsp root>/newlib -# directory, and will be used only for applications that utilize this BSP. -# setting hal.custom_newlib_flags is none - -# Enable support for a subset of the C++ language. This option increases code -# footprint by adding support for C++ constructors. Certain features, such as -# multiple inheritance and exceptions are not supported. If false, adds -# -DALT_NO_C_PLUS_PLUS to ALT_CPPFLAGS in public.mk, and reduces code -# footprint. none -# setting hal.enable_c_plus_plus is true - -# When your application exits, close file descriptors, call C++ destructors, -# etc. Code footprint can be reduced by disabling clean exit. If disabled, adds -# -DALT_NO_CLEAN_EXIT to ALT_CPPFLAGS and -Wl,--defsym, exit=_exit to -# ALT_LDFLAGS in public.mk. none -# setting hal.enable_clean_exit is true - -# Add exit() support. This option increases code footprint if your "main()" -# routine does "return" or call "exit()". If false, adds -DALT_NO_EXIT to -# ALT_CPPFLAGS in public.mk, and reduces footprint none -# setting hal.enable_exit is true - -# Causes code to be compiled with gprof profiling enabled and the application -# ELF to be linked with the GPROF library. If true, adds -DALT_PROVIDE_GMON to -# ALT_CPPFLAGS and -pg to ALT_CFLAGS in public.mk. none -# setting hal.enable_gprof is false - -# Enables lightweight device driver API. This reduces code and data footprint -# by removing the HAL layer that maps device names (e.g. /dev/uart0) to file -# descriptors. Instead, driver routines are called directly. The open(), -# close(), and lseek() routines will always fail if called. The read(), -# write(), fstat(), ioctl(), and isatty() routines only work for the stdio -# devices. If true, adds -DALT_USE_DIRECT_DRIVERS to ALT_CPPFLAGS in public.mk. -# The Altera Host and read-only ZIP file systems can't be used if -# hal.enable_lightweight_device_driver_api is true. -# setting hal.enable_lightweight_device_driver_api is false - -# Adds code to emulate multiply and divide instructions in case they are -# executed but aren't present in the CPU. Normally this isn't required because -# the compiler won't use multiply and divide instructions that aren't present -# in the CPU. If false, adds -DALT_NO_INSTRUCTION_EMULATION to ALT_CPPFLAGS in -# public.mk. none -# setting hal.enable_mul_div_emulation is false -ALT_CPPFLAGS += -DALT_NO_INSTRUCTION_EMULATION - -# Certain drivers are compiled with reduced functionality to reduce code -# footprint. Not all drivers observe this setting. The altera_avalon_uart and -# altera_avalon_jtag_uart drivers switch from interrupt-driven to polled -# operation. CAUTION: Several device drivers are disabled entirely. These -# include the altera_avalon_cfi_flash, altera_avalon_epcs_flash_controller, and -# altera_avalon_lcd_16207 drivers. This can result in certain API (HAL flash -# access routines) to fail. You can define a symbol provided by each driver to -# prevent it from being removed. If true, adds -DALT_USE_SMALL_DRIVERS to -# ALT_CPPFLAGS in public.mk. none -# setting hal.enable_reduced_device_drivers is false - -# Turns on HAL runtime stack checking feature. Enabling this setting causes -# additional code to be placed into each subroutine call to generate an -# exception if a stack collision occurs with the heap or statically allocated -# data. If true, adds -DALT_STACK_CHECK and -mstack-check to ALT_CPPFLAGS in -# public.mk. none -# setting hal.enable_runtime_stack_checking is false - -# The BSP is compiled with optimizations to speedup HDL simulation such as -# initializing the cache, clearing the .bss section, and skipping long delay -# loops. If true, adds -DALT_SIM_OPTIMIZE to ALT_CPPFLAGS in public.mk. When -# this setting is true, the BSP shouldn't be used to build applications that -# are expected to run real hardware. -# setting hal.enable_sim_optimize is false - -# Causes the small newlib (C library) to be used. This reduces code and data -# footprint at the expense of reduced functionality. Several newlib features -# are removed such as floating-point support in printf(), stdin input routines, -# and buffered I/O. The small C library is not compatible with Micrium -# MicroC/OS-II. If true, adds -msmallc to ALT_LDFLAGS in public.mk. none -# setting hal.enable_small_c_library is false - -# Enable SOPC Builder System ID. If a System ID SOPC Builder component is -# connected to the CPU associated with this BSP, it will be enabled in the -# creation of command-line arguments to download an ELF to the target. -# Otherwise, system ID and timestamp values are left out of public.mk for -# application Makefile "download-elf" target definition. With the system ID -# check disabled, the Nios II EDS tools will not automatically ensure that the -# application .elf file (and BSP it is linked against) corresponds to the -# hardware design on the target. If false, adds --accept-bad-sysid to -# SOPC_SYSID_FLAG in public.mk. none -# setting hal.enable_sopc_sysid_check is true - -# Enable BSP generation to query if SOPC system is big endian. If true ignores -# export of 'ALT_CFLAGS += -EB' to public.mk if big endian system. If true -# ignores export of 'ALT_CFLAGS += -EL' if little endian system. none -# setting hal.make.ignore_system_derived.big_endian is false - -# Enable BSP generation to query if SOPC system has a debug core present. If -# true ignores export of 'CPU_HAS_DEBUG_CORE = 1' to public.mk if a debug core -# is found in the system. If true ignores export of 'CPU_HAS_DEBUG_CORE = 0' if -# no debug core is found in the system. none -# setting hal.make.ignore_system_derived.debug_core_present is false - -# Enable BSP generation to query if SOPC system has FPU present. If true -# ignores export of 'ALT_CFLAGS += -mhard-float' to public.mk if FPU is found -# in the system. If true ignores export of 'ALT_CFLAGS += -mhard-soft' if FPU -# is not found in the system. none -# setting hal.make.ignore_system_derived.fpu_present is false - -# Enable BSP generation to query if SOPC system has hardware divide present. If -# true ignores export of 'ALT_CFLAGS += -mno-hw-div' to public.mk if no -# division is found in system. If true ignores export of 'ALT_CFLAGS += -# -mhw-div' if division is found in the system. none -# setting hal.make.ignore_system_derived.hardware_divide_present is false - -# Enable BSP generation to query if SOPC system floating point custom -# instruction with a divider is present. If true ignores export of 'ALT_CFLAGS -# += -mcustom-fpu-cfg=60-2' and 'ALT_LDFLAGS += -mcustom-fpu-cfg=60-2' to -# public.mk if the custom instruction is found in the system. none -# setting hal.make.ignore_system_derived.hardware_fp_cust_inst_divider_present is false - -# Enable BSP generation to query if SOPC system floating point custom -# instruction without a divider is present. If true ignores export of -# 'ALT_CFLAGS += -mcustom-fpu-cfg=60-1' and 'ALT_LDFLAGS += -# -mcustom-fpu-cfg=60-1' to public.mk if the custom instruction is found in the -# system. none -# setting hal.make.ignore_system_derived.hardware_fp_cust_inst_no_divider_present is false - -# Enable BSP generation to query if SOPC system has multiplier present. If true -# ignores export of 'ALT_CFLAGS += -mno-hw-mul' to public.mk if no multiplier -# is found in the system. If true ignores export of 'ALT_CFLAGS += -mhw-mul' if -# multiplier is found in the system. none -# setting hal.make.ignore_system_derived.hardware_multiplier_present is false - -# Enable BSP generation to query if SOPC system has hardware mulx present. If -# true ignores export of 'ALT_CFLAGS += -mno-hw-mulx' to public.mk if no mulx -# is found in the system. If true ignores export of 'ALT_CFLAGS += -mhw-mulx' -# if mulx is found in the system. none -# setting hal.make.ignore_system_derived.hardware_mulx_present is false - -# Enable BSP generation to query if SOPC system has simulation enabled. If true -# ignores export of 'ELF_PATCH_FLAG += --simulation_enabled' to public.mk. none -# setting hal.make.ignore_system_derived.sopc_simulation_enabled is false - -# Enable BSP generation to query SOPC system for system ID base address. If -# true ignores export of 'SOPC_SYSID_FLAG += --sidp=
' and -# 'ELF_PATCH_FLAG += --sidp=
' to public.mk. none -# setting hal.make.ignore_system_derived.sopc_system_base_address is false - -# Enable BSP generation to query SOPC system for system ID. If true ignores -# export of 'SOPC_SYSID_FLAG += --id=' and 'ELF_PATCH_FLAG += -# --id=' to public.mk. none -# setting hal.make.ignore_system_derived.sopc_system_id is false - -# Enable BSP generation to query SOPC system for system timestamp. If true -# ignores export of 'SOPC_SYSID_FLAG += --timestamp=' and -# 'ELF_PATCH_FLAG += --timestamp=' to public.mk. none -# setting hal.make.ignore_system_derived.sopc_system_timestamp is false - -# Slave descriptor of STDERR character-mode device. This setting is used by the -# ALT_STDERR family of defines in system.h. none -# setting hal.stderr is jtag_uart_0 -ELF_PATCH_FLAG += --stderr_dev jtag_uart_0 - -# Slave descriptor of STDIN character-mode device. This setting is used by the -# ALT_STDIN family of defines in system.h. none -# setting hal.stdin is jtag_uart_0 -ELF_PATCH_FLAG += --stdin_dev jtag_uart_0 - -# Slave descriptor of STDOUT character-mode device. This setting is used by the -# ALT_STDOUT family of defines in system.h. none -# setting hal.stdout is jtag_uart_0 -ELF_PATCH_FLAG += --stdout_dev jtag_uart_0 - - -#------------------------------------------------------------------------------ -# SOFTWARE COMPONENT & DRIVER INCLUDE PATHS -#------------------------------------------------------------------------------ - -ALT_INCLUDE_DIRS += $(ALT_LIBRARY_ROOT_DIR)/UCOSII/inc -ALT_INCLUDE_DIRS += $(ALT_LIBRARY_ROOT_DIR)/HAL/inc - -#------------------------------------------------------------------------------ -# SOFTWARE COMPONENT & DRIVER PRODUCED ALT_CPPFLAGS ADDITIONS -#------------------------------------------------------------------------------ - -ALT_CPPFLAGS += -D__ucosii__ - -#END MANAGED - - -#------------------------------------------------------------------------------ -# LIBRARY INFORMATION -#------------------------------------------------------------------------------ -# Assemble the name of the BSP *.a file using the BSP library name -# (BSP_SYS_LIB) in generated content above. -BSP_LIB := lib$(BSP_SYS_LIB).a - -# Additional libraries to link against: -# An application including this file will prefix each library with "-l". -# For example, to include the Newlib math library "m" is included, which -# becomes "-lm" when linking the application. -ALT_LIBRARY_NAMES += m - -# Additions to linker dependencies: -# An application Makefile will typically add these directly to the list -# of dependencies required to build the executable target(s). The BSP -# library (*.a) file is specified here. -ALT_LDDEPS += $(ALT_LIBRARY_ROOT_DIR)/$(BSP_LIB) - -# Is this library "Makeable"? -# Add to list of root library directories that support running 'make' -# to build them. Because libraries may or may not have a Makefile in their -# root, appending to this variable tells an application to run 'make' in -# the library root to build/update this library. -MAKEABLE_LIBRARY_ROOT_DIRS += $(ALT_LIBRARY_ROOT_DIR) - -# Additional Assembler Flags -# -gdwarf2 flag is required for stepping through assembly code -ALT_ASFLAGS += -gdwarf2 - -#------------------------------------------------------------------------------ -# FINAL INCLUDE PATH LIST -#------------------------------------------------------------------------------ -# Append static include paths to paths specified by OS/driver/sw package -# additions to the BSP thus giving them precedence in case a BSP addition -# is attempting to override BSP sources. -ALT_INCLUDE_DIRS += $(ALT_INCLUDE_DIRS_TO_APPEND) - - - diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/settings.bsp b/MCandWifiTestDE0/NewMCWifiTest_bsp/settings.bsp deleted file mode 100644 index bc82c1c8..00000000 --- a/MCandWifiTestDE0/NewMCWifiTest_bsp/settings.bsp +++ /dev/null @@ -1,1801 +0,0 @@ - - - ucosii - default - 2-Mar-2014 3:16:23 PM - 1393798583679 - C:\Users\gongal\NewRepARCap\MCandWifiTestDE0\NewMCWifiTest_bsp - .\settings.bsp - C:\Users\gongal\ARCap\Repository\WifiTestDE0\system.sopcinfo - default - cpu - 1.9 - - hal.sys_clk_timer - ALT_SYS_CLK - UnquotedString - sys_clk_timer - none - system_h_define - Slave descriptor of the system clock timer device. This device provides a periodic interrupt ("tick") and is typically required for RTOS use. This setting defines the value of ALT_SYS_CLK in system.h. - none - false - common - - - hal.timestamp_timer - ALT_TIMESTAMP_CLK - UnquotedString - none - none - system_h_define - Slave descriptor of timestamp timer device. This device is used by Altera HAL timestamp drivers for high-resolution time measurement. This setting defines the value of ALT_TIMESTAMP_CLK in system.h. - none - false - common - - - hal.max_file_descriptors - ALT_MAX_FD - DecimalNumber - 32 - 32 - system_h_define - Determines the number of file descriptors statically allocated. This setting defines the value of ALT_MAX_FD in system.h. - If hal.enable_lightweight_device_driver_api is true, there are no file descriptors so this setting is ignored. If hal.enable_lightweight_device_driver_api is false, this setting must be at least 4 because HAL needs a file descriptor for /dev/null, /dev/stdin, /dev/stdout, and /dev/stderr. - false - - - - hal.enable_instruction_related_exceptions_api - ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API - BooleanDefineOnly - false - false - system_h_define - Enables API for registering handlers to service instruction-related exceptions. Enabling this setting increases the size of the exception entry code. - These exception types can be generated if various processor options are enabled, such as the MMU, MPU, or other advanced exception types. - false - - - - hal.linker.allow_code_at_reset - ALT_ALLOW_CODE_AT_RESET - Boolean - 1 - 0 - none - Indicates if initialization code is allowed at the reset address. If true, defines the macro ALT_ALLOW_CODE_AT_RESET in linker.h. - If true, defines the macro ALT_ALLOW_CODE_AT_RESET in linker.h. This setting is typically false if an external bootloader (e.g. flash bootloader) is present. - false - - - - hal.linker.enable_alt_load - NONE - Boolean - 1 - 0 - none - Enables the alt_load() facility. The alt_load() facility copies sections from the .text memory into RAM. If true, this setting sets up the VMA/LMA of sections in linker.x to allow them to be loaded into the .text memory. - This setting is typically false if an external bootloader (e.g. flash bootloader) is present. - false - - - - hal.linker.enable_alt_load_copy_rodata - NONE - Boolean - 0 - 0 - none - Causes the alt_load() facility to copy the .rodata section. If true, this setting defines the macro ALT_LOAD_COPY_RODATA in linker.h. - none - false - - - - hal.linker.enable_alt_load_copy_rwdata - NONE - Boolean - 1 - 0 - none - Causes the alt_load() facility to copy the .rwdata section. If true, this setting defines the macro ALT_LOAD_COPY_RWDATA in linker.h. - none - false - - - - hal.linker.enable_alt_load_copy_exceptions - NONE - Boolean - 0 - 0 - none - Causes the alt_load() facility to copy the .exceptions section. If true, this setting defines the macro ALT_LOAD_COPY_EXCEPTIONS in linker.h. - none - false - - - - hal.linker.enable_exception_stack - NONE - Boolean - 0 - 0 - none - Enables use of a separate exception stack. If true, defines the macro ALT_EXCEPTION_STACK in linker.h, adds a memory region called exception_stack to linker.x, and provides the symbols __alt_exception_stack_pointer and __alt_exception_stack_limit in linker.x. - The hal.linker.exception_stack_size and hal.linker.exception_stack_memory_region_name settings must also be valid. This setting must be false for MicroC/OS-II BSPs. The exception stack can be used to improve interrupt and other exception performance if the EIC is *not* used. - false - common - - - hal.linker.exception_stack_size - NONE - DecimalNumber - 1024 - 1024 - none - Size of the exception stack in bytes. - Only used if hal.linker.enable_exception_stack is true. - false - common - - - hal.linker.exception_stack_memory_region_name - NONE - UnquotedString - sdram - none - none - Name of the existing memory region that will be divided up to create the 'exception_stack' memory region. The selected region name will be adjusted automatically when the BSP is generated to create the 'exception_stack' memory region. - Only used if hal.linker.enable_exception_stack is true. - false - common - - - hal.linker.enable_interrupt_stack - NONE - Boolean - 0 - 0 - none - Enables use of a separate interrupt stack. If true, defines the macro ALT_INTERRUPT_STACK in linker.h, adds a memory region called interrupt_stack to linker.x, and provides the symbols __alt_interrupt_stack_pointer and __alt_interrupt_stack_limit in linker.x. - The hal.linker.interrupt_stack_size and hal.linker.interrupt_stack_memory_region_name settings must also be valid. This setting must be false for MicroC/OS-II BSPs. Only enable if the EIC is used exclusively. The exception stack can be used to improve interrupt and other exception performance if the EIC is *not* used. - false - common - - - hal.linker.interrupt_stack_size - NONE - DecimalNumber - 1024 - 1024 - none - Size of the interrupt stack in bytes. - Only used if hal.linker.enable_interrupt_stack is true. - false - common - - - hal.linker.interrupt_stack_memory_region_name - NONE - UnquotedString - sdram - none - none - Name of the existing memory region that will be divided up to create the 'interrupt_stack' memory region. The selected region name will be adjusted automatically when the BSP is generated to create the 'interrupt_stack' memory region. - Only used if hal.linker.enable_interrupt_stack is true. - false - common - - - hal.stdin - NONE - UnquotedString - jtag_uart_0 - none - system_h_define - Slave descriptor of STDIN character-mode device. This setting is used by the ALT_STDIN family of defines in system.h. - none - false - common - - - hal.stdout - NONE - UnquotedString - jtag_uart_0 - none - system_h_define - Slave descriptor of STDOUT character-mode device. This setting is used by the ALT_STDOUT family of defines in system.h. - none - false - common - - - hal.stderr - NONE - UnquotedString - jtag_uart_0 - none - system_h_define - Slave descriptor of STDERR character-mode device. This setting is used by the ALT_STDERR family of defines in system.h. - none - false - common - - - hal.log_port - NONE - UnquotedString - none - none - public_mk_define - Slave descriptor of debug logging character-mode device. If defined, it enables extra debug messages in the HAL source. This setting is used by the ALT_LOG_PORT family of defines in system.h. - none - false - none - - - hal.make.build_pre_process - BUILD_PRE_PROCESS - UnquotedString - none - none - makefile_variable - Command executed before BSP built. - none - false - none - - - hal.make.ar_pre_process - AR_PRE_PROCESS - UnquotedString - none - none - makefile_variable - Command executed before archiver execution. - none - false - none - - - hal.make.bsp_cflags_defined_symbols - BSP_CFLAGS_DEFINED_SYMBOLS - UnquotedString - none - none - makefile_variable - Preprocessor macros to define. A macro definition in this setting has the same effect as a "#define" in source code. Adding "-DALT_DEBUG" to this setting has the same effect as "#define ALT_DEBUG" in a souce file. Adding "-DFOO=1" to this setting is equivalent to the macro "#define FOO 1" in a source file. Macros defined with this setting are applied to all .S, .c, and C++ files in the BSP. This setting defines the value of BSP_CFLAGS_DEFINED_SYMBOLS in the BSP Makefile. - none - false - none - - - hal.make.ar_post_process - AR_POST_PROCESS - UnquotedString - none - none - makefile_variable - Command executed after archiver execution. - none - false - none - - - hal.make.as - AS - UnquotedString - nios2-elf-gcc - nios2-elf-gcc - makefile_variable - Assembler command. Note that CC is used for .S files. - none - false - none - - - hal.make.build_post_process - BUILD_POST_PROCESS - UnquotedString - none - none - makefile_variable - Command executed after BSP built. - none - false - none - - - hal.make.bsp_cflags_debug - BSP_CFLAGS_DEBUG - UnquotedString - -g - -g - makefile_variable - C/C++ compiler debug level. '-g' provides the default set of debug symbols typically required to debug a typical application. Omitting '-g' removes debug symbols from the ELF. This setting defines the value of BSP_CFLAGS_DEBUG in Makefile. - none - false - common - - - hal.make.ar - AR - UnquotedString - nios2-elf-ar - nios2-elf-ar - makefile_variable - Archiver command. Creates library files. - none - false - none - - - hal.make.rm - RM - UnquotedString - rm -f - rm -f - makefile_variable - Command used to remove files during 'clean' target. - none - false - none - - - hal.make.cxx_pre_process - CXX_PRE_PROCESS - UnquotedString - none - none - makefile_variable - Command executed before each C++ file is compiled. - none - false - none - - - hal.make.bsp_cflags_warnings - BSP_CFLAGS_WARNINGS - UnquotedString - -Wall - -Wall - makefile_variable - C/C++ compiler warning level. "-Wall" is commonly used.This setting defines the value of BSP_CFLAGS_WARNINGS in Makefile. - none - false - none - - - hal.make.bsp_arflags - BSP_ARFLAGS - UnquotedString - -src - -src - makefile_variable - Custom flags only passed to the archiver. This content of this variable is directly passed to the archiver rather than the more standard "ARFLAGS". The reason for this is that GNU Make assumes some default content in ARFLAGS. This setting defines the value of BSP_ARFLAGS in Makefile. - none - false - none - - - hal.make.bsp_cflags_optimization - BSP_CFLAGS_OPTIMIZATION - UnquotedString - -O0 - -O0 - makefile_variable - C/C++ compiler optimization level. "-O0" = no optimization,"-O2" = "normal" optimization, etc. "-O0" is recommended for code that you want to debug since compiler optimization can remove variables and produce non-sequential execution of code while debugging. This setting defines the value of BSP_CFLAGS_OPTIMIZATION in Makefile. - none - false - common - - - hal.make.as_post_process - AS_POST_PROCESS - UnquotedString - none - none - makefile_variable - Command executed after each assembly file is compiled. - none - false - none - - - hal.make.cc_pre_process - CC_PRE_PROCESS - UnquotedString - none - none - makefile_variable - Command executed before each .c/.S file is compiled. - none - false - none - - - hal.make.bsp_asflags - BSP_ASFLAGS - UnquotedString - -Wa,-gdwarf2 - -Wa,-gdwarf2 - makefile_variable - Custom flags only passed to the assembler. This setting defines the value of BSP_ASFLAGS in Makefile. - none - false - none - - - hal.make.as_pre_process - AS_PRE_PROCESS - UnquotedString - none - none - makefile_variable - Command executed before each assembly file is compiled. - none - false - none - - - hal.make.bsp_cflags_undefined_symbols - BSP_CFLAGS_UNDEFINED_SYMBOLS - UnquotedString - none - none - makefile_variable - Preprocessor macros to undefine. Undefined macros are similar to defined macros, but replicate the "#undef" directive in source code. To undefine the macro FOO use the syntax "-u FOO" in this setting. This is equivalent to "#undef FOO" in a source file. Note: the syntax differs from macro definition (there is a space, i.e. "-u FOO" versus "-DFOO"). Macros defined with this setting are applied to all .S, .c, and C++ files in the BSP. This setting defines the value of BSP_CFLAGS_UNDEFINED_SYMBOLS in the BSP Makefile. - none - false - none - - - hal.make.cc_post_process - CC_POST_PROCESS - UnquotedString - none - none - makefile_variable - Command executed after each .c/.S file is compiled. - none - false - none - - - hal.make.cxx_post_process - CXX_POST_PROCESS - UnquotedString - none - none - makefile_variable - Command executed before each C++ file is compiled. - none - false - none - - - hal.make.cc - CC - UnquotedString - nios2-elf-gcc -xc - nios2-elf-gcc -xc - makefile_variable - C compiler command. - none - false - none - - - hal.make.bsp_cxx_flags - BSP_CXXFLAGS - UnquotedString - none - none - makefile_variable - Custom flags only passed to the C++ compiler. This setting defines the value of BSP_CXXFLAGS in Makefile. - none - false - none - - - hal.make.bsp_inc_dirs - BSP_INC_DIRS - UnquotedString - none - none - makefile_variable - Space separated list of extra include directories to scan for header files. Directories are relative to the top-level BSP directory. The -I prefix's added by the makefile so don't add it here. This setting defines the value of BSP_INC_DIRS in Makefile. - none - false - none - - - hal.make.cxx - CXX - UnquotedString - nios2-elf-gcc -xc++ - nios2-elf-gcc -xc++ - makefile_variable - C++ compiler command. - none - false - none - - - hal.make.bsp_cflags_user_flags - BSP_CFLAGS_USER_FLAGS - UnquotedString - none - none - makefile_variable - Custom flags passed to the compiler when compiling C, C++, and .S files. This setting defines the value of BSP_CFLAGS_USER_FLAGS in Makefile. - none - false - none - - - hal.make.ignore_system_derived.sopc_system_id - NONE - Boolean - 0 - 0 - public_mk_define - Enable BSP generation to query SOPC system for system ID. If true ignores export of 'SOPC_SYSID_FLAG += --id=<sysid>' and 'ELF_PATCH_FLAG += --id=<sysid>' to public.mk. - none - false - none - - - hal.make.ignore_system_derived.sopc_system_timestamp - NONE - Boolean - 0 - 0 - public_mk_define - Enable BSP generation to query SOPC system for system timestamp. If true ignores export of 'SOPC_SYSID_FLAG += --timestamp=<timestamp>' and 'ELF_PATCH_FLAG += --timestamp=<timestamp>' to public.mk. - none - false - none - - - hal.make.ignore_system_derived.sopc_system_base_address - NONE - Boolean - 0 - 0 - public_mk_define - Enable BSP generation to query SOPC system for system ID base address. If true ignores export of 'SOPC_SYSID_FLAG += --sidp=<address>' and 'ELF_PATCH_FLAG += --sidp=<address>' to public.mk. - none - false - none - - - hal.make.ignore_system_derived.sopc_simulation_enabled - NONE - Boolean - 0 - 0 - public_mk_define - Enable BSP generation to query if SOPC system has simulation enabled. If true ignores export of 'ELF_PATCH_FLAG += --simulation_enabled' to public.mk. - none - false - none - - - hal.make.ignore_system_derived.fpu_present - NONE - Boolean - 0 - 0 - public_mk_define - Enable BSP generation to query if SOPC system has FPU present. If true ignores export of 'ALT_CFLAGS += -mhard-float' to public.mk if FPU is found in the system. If true ignores export of 'ALT_CFLAGS += -mhard-soft' if FPU is not found in the system. - none - false - none - - - hal.make.ignore_system_derived.hardware_multiplier_present - NONE - Boolean - 0 - 0 - public_mk_define - Enable BSP generation to query if SOPC system has multiplier present. If true ignores export of 'ALT_CFLAGS += -mno-hw-mul' to public.mk if no multiplier is found in the system. If true ignores export of 'ALT_CFLAGS += -mhw-mul' if multiplier is found in the system. - none - false - none - - - hal.make.ignore_system_derived.hardware_mulx_present - NONE - Boolean - 0 - 0 - public_mk_define - Enable BSP generation to query if SOPC system has hardware mulx present. If true ignores export of 'ALT_CFLAGS += -mno-hw-mulx' to public.mk if no mulx is found in the system. If true ignores export of 'ALT_CFLAGS += -mhw-mulx' if mulx is found in the system. - none - false - none - - - hal.make.ignore_system_derived.hardware_divide_present - NONE - Boolean - 0 - 0 - public_mk_define - Enable BSP generation to query if SOPC system has hardware divide present. If true ignores export of 'ALT_CFLAGS += -mno-hw-div' to public.mk if no division is found in system. If true ignores export of 'ALT_CFLAGS += -mhw-div' if division is found in the system. - none - false - none - - - hal.make.ignore_system_derived.debug_core_present - NONE - Boolean - 0 - 0 - public_mk_define - Enable BSP generation to query if SOPC system has a debug core present. If true ignores export of 'CPU_HAS_DEBUG_CORE = 1' to public.mk if a debug core is found in the system. If true ignores export of 'CPU_HAS_DEBUG_CORE = 0' if no debug core is found in the system. - none - false - none - - - hal.make.ignore_system_derived.big_endian - NONE - Boolean - 0 - 0 - public_mk_define - Enable BSP generation to query if SOPC system is big endian. If true ignores export of 'ALT_CFLAGS += -EB' to public.mk if big endian system. If true ignores export of 'ALT_CFLAGS += -EL' if little endian system. - none - false - none - - - hal.make.ignore_system_derived.hardware_fp_cust_inst_divider_present - NONE - Boolean - 0 - 0 - public_mk_define - Enable BSP generation to query if SOPC system floating point custom instruction with a divider is present. If true ignores export of 'ALT_CFLAGS += -mcustom-fpu-cfg=60-2' and 'ALT_LDFLAGS += -mcustom-fpu-cfg=60-2' to public.mk if the custom instruction is found in the system. - none - false - none - - - hal.make.ignore_system_derived.hardware_fp_cust_inst_no_divider_present - NONE - Boolean - 0 - 0 - public_mk_define - Enable BSP generation to query if SOPC system floating point custom instruction without a divider is present. If true ignores export of 'ALT_CFLAGS += -mcustom-fpu-cfg=60-1' and 'ALT_LDFLAGS += -mcustom-fpu-cfg=60-1' to public.mk if the custom instruction is found in the system. - none - false - none - - - hal.enable_exit - ALT_NO_EXIT - Boolean - 1 - 1 - public_mk_define - Add exit() support. This option increases code footprint if your "main()" routine does "return" or call "exit()". If false, adds -DALT_NO_EXIT to ALT_CPPFLAGS in public.mk, and reduces footprint - none - false - none - - - hal.enable_small_c_library - NONE - Boolean - 0 - 0 - public_mk_define - Causes the small newlib (C library) to be used. This reduces code and data footprint at the expense of reduced functionality. Several newlib features are removed such as floating-point support in printf(), stdin input routines, and buffered I/O. The small C library is not compatible with Micrium MicroC/OS-II. If true, adds -msmallc to ALT_LDFLAGS in public.mk. - none - false - common - - - hal.enable_clean_exit - ALT_NO_CLEAN_EXIT - Boolean - 1 - 1 - public_mk_define - When your application exits, close file descriptors, call C++ destructors, etc. Code footprint can be reduced by disabling clean exit. If disabled, adds -DALT_NO_CLEAN_EXIT to ALT_CPPFLAGS and -Wl,--defsym, exit=_exit to ALT_LDFLAGS in public.mk. - none - false - none - - - hal.enable_runtime_stack_checking - ALT_STACK_CHECK - Boolean - 0 - 0 - public_mk_define - Turns on HAL runtime stack checking feature. Enabling this setting causes additional code to be placed into each subroutine call to generate an exception if a stack collision occurs with the heap or statically allocated data. If true, adds -DALT_STACK_CHECK and -mstack-check to ALT_CPPFLAGS in public.mk. - none - false - none - - - hal.enable_gprof - ALT_PROVIDE_GMON - Boolean - 0 - 0 - public_mk_define - Causes code to be compiled with gprof profiling enabled and the application ELF to be linked with the GPROF library. If true, adds -DALT_PROVIDE_GMON to ALT_CPPFLAGS and -pg to ALT_CFLAGS in public.mk. - none - false - common - - - hal.enable_c_plus_plus - ALT_NO_C_PLUS_PLUS - Boolean - 1 - 1 - public_mk_define - Enable support for a subset of the C++ language. This option increases code footprint by adding support for C++ constructors. Certain features, such as multiple inheritance and exceptions are not supported. If false, adds -DALT_NO_C_PLUS_PLUS to ALT_CPPFLAGS in public.mk, and reduces code footprint. - none - false - none - - - hal.enable_reduced_device_drivers - ALT_USE_SMALL_DRIVERS - Boolean - 0 - 0 - public_mk_define - Certain drivers are compiled with reduced functionality to reduce code footprint. Not all drivers observe this setting. The altera_avalon_uart and altera_avalon_jtag_uart drivers switch from interrupt-driven to polled operation. CAUTION: Several device drivers are disabled entirely. These include the altera_avalon_cfi_flash, altera_avalon_epcs_flash_controller, and altera_avalon_lcd_16207 drivers. This can result in certain API (HAL flash access routines) to fail. You can define a symbol provided by each driver to prevent it from being removed. If true, adds -DALT_USE_SMALL_DRIVERS to ALT_CPPFLAGS in public.mk. - none - false - common - - - hal.enable_lightweight_device_driver_api - ALT_USE_DIRECT_DRIVERS - Boolean - 0 - 0 - public_mk_define - Enables lightweight device driver API. This reduces code and data footprint by removing the HAL layer that maps device names (e.g. /dev/uart0) to file descriptors. Instead, driver routines are called directly. The open(), close(), and lseek() routines will always fail if called. The read(), write(), fstat(), ioctl(), and isatty() routines only work for the stdio devices. If true, adds -DALT_USE_DIRECT_DRIVERS to ALT_CPPFLAGS in public.mk. - The Altera Host and read-only ZIP file systems can't be used if hal.enable_lightweight_device_driver_api is true. - false - none - - - hal.enable_mul_div_emulation - ALT_NO_INSTRUCTION_EMULATION - Boolean - 0 - 0 - public_mk_define - Adds code to emulate multiply and divide instructions in case they are executed but aren't present in the CPU. Normally this isn't required because the compiler won't use multiply and divide instructions that aren't present in the CPU. If false, adds -DALT_NO_INSTRUCTION_EMULATION to ALT_CPPFLAGS in public.mk. - none - false - none - - - hal.enable_sim_optimize - ALT_SIM_OPTIMIZE - Boolean - 0 - 0 - public_mk_define - The BSP is compiled with optimizations to speedup HDL simulation such as initializing the cache, clearing the .bss section, and skipping long delay loops. If true, adds -DALT_SIM_OPTIMIZE to ALT_CPPFLAGS in public.mk. - When this setting is true, the BSP shouldn't be used to build applications that are expected to run real hardware. - false - common - - - hal.enable_sopc_sysid_check - NONE - Boolean - 1 - 1 - public_mk_define - Enable SOPC Builder System ID. If a System ID SOPC Builder component is connected to the CPU associated with this BSP, it will be enabled in the creation of command-line arguments to download an ELF to the target. Otherwise, system ID and timestamp values are left out of public.mk for application Makefile "download-elf" target definition. With the system ID check disabled, the Nios II EDS tools will not automatically ensure that the application .elf file (and BSP it is linked against) corresponds to the hardware design on the target. If false, adds --accept-bad-sysid to SOPC_SYSID_FLAG in public.mk. - none - false - none - - - hal.custom_newlib_flags - CUSTOM_NEWLIB_FLAGS - UnquotedString - none - none - public_mk_define - Build a custom version of newlib with the specified space-separated compiler flags. - The custom newlib build will be placed in the &lt;bsp root>/newlib directory, and will be used only for applications that utilize this BSP. - false - none - - - hal.log_flags - ALT_LOG_FLAGS - DecimalNumber - 0 - 0 - public_mk_define - The value is assigned to ALT_LOG_FLAGS in the generated public.mk. See hal.log_port setting description. Values can be -1 through 3. - hal.log_port must be set for this to be used. - false - none - - - ucosii.os_max_tasks - OS_MAX_TASKS - DecimalNumber - 10 - 10 - system_h_define - Maximum number of tasks - none - false - - - - ucosii.os_lowest_prio - OS_LOWEST_PRIO - DecimalNumber - 20 - 20 - system_h_define - Lowest assignable priority - none - false - - - - ucosii.os_thread_safe_newlib - OS_THREAD_SAFE_NEWLIB - Boolean - 1 - 1 - system_h_define - Thread safe C library - none - false - - - - ucosii.miscellaneous.os_arg_chk_en - OS_ARG_CHK_EN - Boolean - 1 - 1 - system_h_define - Enable argument checking - none - false - - - - ucosii.miscellaneous.os_cpu_hooks_en - OS_CPU_HOOKS_EN - Boolean - 1 - 1 - system_h_define - Enable uCOS-II hooks - none - false - - - - ucosii.miscellaneous.os_debug_en - OS_DEBUG_EN - Boolean - 1 - 1 - system_h_define - Enable debug variables - none - false - - - - ucosii.miscellaneous.os_sched_lock_en - OS_SCHED_LOCK_EN - Boolean - 1 - 1 - system_h_define - Include code for OSSchedLock() and OSSchedUnlock() - none - false - - - - ucosii.miscellaneous.os_task_stat_en - OS_TASK_STAT_EN - Boolean - 1 - 1 - system_h_define - Enable statistics task - none - false - - - - ucosii.miscellaneous.os_task_stat_stk_chk_en - OS_TASK_STAT_STK_CHK_EN - Boolean - 1 - 1 - system_h_define - Check task stacks from statistics task - none - false - - - - ucosii.miscellaneous.os_tick_step_en - OS_TICK_STEP_EN - Boolean - 1 - 1 - system_h_define - Enable tick stepping feature for uCOS-View - none - false - - - - ucosii.miscellaneous.os_event_name_size - OS_EVENT_NAME_SIZE - DecimalNumber - 32 - 32 - system_h_define - Size of name of Event Control Block groups - none - false - - - - ucosii.miscellaneous.os_max_events - OS_MAX_EVENTS - DecimalNumber - 60 - 60 - system_h_define - Maximum number of event control blocks - none - false - - - - ucosii.miscellaneous.os_task_idle_stk_size - OS_TASK_IDLE_STK_SIZE - DecimalNumber - 512 - 512 - system_h_define - Idle task stack size - none - false - - - - ucosii.miscellaneous.os_task_stat_stk_size - OS_TASK_STAT_STK_SIZE - DecimalNumber - 512 - 512 - system_h_define - Statistics task stack size - none - false - - - - ucosii.task.os_task_change_prio_en - OS_TASK_CHANGE_PRIO_EN - Boolean - 1 - 1 - system_h_define - Include code for OSTaskChangePrio() - none - false - - - - ucosii.task.os_task_create_en - OS_TASK_CREATE_EN - Boolean - 1 - 1 - system_h_define - Include code for OSTaskCreate() - none - false - - - - ucosii.task.os_task_create_ext_en - OS_TASK_CREATE_EXT_EN - Boolean - 1 - 1 - system_h_define - Include code for OSTaskCreateExt() - none - false - - - - ucosii.task.os_task_del_en - OS_TASK_DEL_EN - Boolean - 1 - 1 - system_h_define - Include code for OSTaskDel() - none - false - - - - ucosii.task.os_task_name_size - OS_TASK_NAME_SIZE - DecimalNumber - 32 - 32 - system_h_define - Size of task name - none - false - - - - ucosii.task.os_task_profile_en - OS_TASK_PROFILE_EN - Boolean - 1 - 1 - system_h_define - Include data structure for run-time task profiling - none - false - - - - ucosii.task.os_task_query_en - OS_TASK_QUERY_EN - Boolean - 1 - 1 - system_h_define - Include code for OSTaskQuery - none - false - - - - ucosii.task.os_task_suspend_en - OS_TASK_SUSPEND_EN - Boolean - 1 - 1 - system_h_define - Include code for OSTaskSuspend() and OSTaskResume() - none - false - - - - ucosii.task.os_task_sw_hook_en - OS_TASK_SW_HOOK_EN - Boolean - 1 - 1 - system_h_define - Include code for OSTaskSwHook() - none - false - - - - ucosii.time.os_time_tick_hook_en - OS_TIME_TICK_HOOK_EN - Boolean - 1 - 1 - system_h_define - Include code for OSTimeTickHook() - none - false - - - - ucosii.time.os_time_dly_resume_en - OS_TIME_DLY_RESUME_EN - Boolean - 1 - 1 - system_h_define - Include code for OSTimeDlyResume() - none - false - - - - ucosii.time.os_time_dly_hmsm_en - OS_TIME_DLY_HMSM_EN - Boolean - 1 - 1 - system_h_define - Include code for OSTimeDlyHMSM() - none - false - - - - ucosii.time.os_time_get_set_en - OS_TIME_GET_SET_EN - Boolean - 1 - 1 - system_h_define - Include code for OSTimeGet and OSTimeSet() - none - false - - - - ucosii.os_flag_en - OS_FLAG_EN - Boolean - 1 - 1 - system_h_define - Enable code for Event Flags. CAUTION: This is required by the HAL and many Altera device drivers. - none - false - - - - ucosii.event_flag.os_flag_wait_clr_en - OS_FLAG_WAIT_CLR_EN - Boolean - 1 - 1 - system_h_define - Include code for Wait on Clear Event Flags. CAUTION: This is required by the HAL and many Altera device drivers. - none - false - - - - ucosii.event_flag.os_flag_accept_en - OS_FLAG_ACCEPT_EN - Boolean - 1 - 1 - system_h_define - Include code for OSFlagAccept(). CAUTION: This is required by the HAL and many Altera device drivers. - none - false - - - - ucosii.event_flag.os_flag_del_en - OS_FLAG_DEL_EN - Boolean - 1 - 1 - system_h_define - Include code for OSFlagDel(). CAUTION: This is required by the HAL and many Altera device drivers. - none - false - - - - ucosii.event_flag.os_flag_query_en - OS_FLAG_QUERY_EN - Boolean - 1 - 1 - system_h_define - Include code for OSFlagQuery(). CAUTION: This is required by the HAL and many Altera device drivers. - none - false - - - - ucosii.event_flag.os_flag_name_size - OS_FLAG_NAME_SIZE - DecimalNumber - 32 - 32 - system_h_define - Size of name of Event Flags group. CAUTION: This is required by the HAL and many Altera device drivers; use caution in reducing this value. - none - false - - - - ucosii.event_flag.os_flags_nbits - OS_FLAGS_NBITS - DecimalNumber - 16 - 16 - system_h_define - Event Flag bits (8,16,32). CAUTION: This is required by the HAL and many Altera device drivers; use caution in changing this value. - none - false - - - - ucosii.event_flag.os_max_flags - OS_MAX_FLAGS - DecimalNumber - 20 - 20 - system_h_define - Maximum number of Event Flags groups. CAUTION: This is required by the HAL and many Altera device drivers; use caution in reducing this value. - none - false - - - - ucosii.os_mutex_en - OS_MUTEX_EN - Boolean - 1 - 1 - system_h_define - Enable code for Mutex Semaphores - none - false - - - - ucosii.mutex.os_mutex_accept_en - OS_MUTEX_ACCEPT_EN - Boolean - 1 - 1 - system_h_define - Include code for OSMutexAccept() - none - false - - - - ucosii.mutex.os_mutex_del_en - OS_MUTEX_DEL_EN - Boolean - 1 - 1 - system_h_define - Include code for OSMutexDel() - none - false - - - - ucosii.mutex.os_mutex_query_en - OS_MUTEX_QUERY_EN - Boolean - 1 - 1 - system_h_define - Include code for OSMutexQuery - none - false - - - - ucosii.os_sem_en - OS_SEM_EN - Boolean - 1 - 1 - system_h_define - Enable code for semaphores. CAUTION: This is required by the HAL and many Altera device drivers. - none - false - - - - ucosii.semaphore.os_sem_accept_en - OS_SEM_ACCEPT_EN - Boolean - 1 - 1 - system_h_define - Include code for OSSemAccept(). CAUTION: This is required by the HAL and many Altera device drivers. - none - false - - - - ucosii.semaphore.os_sem_set_en - OS_SEM_SET_EN - Boolean - 1 - 1 - system_h_define - Include code for OSSemSet(). CAUTION: This is required by the HAL and many Altera device drivers. - none - false - - - - ucosii.semaphore.os_sem_del_en - OS_SEM_DEL_EN - Boolean - 1 - 1 - system_h_define - Include code for OSSemDel(). CAUTION: This is required by the HAL and many Altera device drivers. - none - false - - - - ucosii.semaphore.os_sem_query_en - OS_SEM_QUERY_EN - Boolean - 1 - 1 - system_h_define - Include code for OSSemQuery(). CAUTION: This is required by the HAL and many Altera device drivers. - none - false - - - - ucosii.os_mbox_en - OS_MBOX_EN - Boolean - 1 - 1 - system_h_define - Enable code for mailboxes - none - false - - - - ucosii.mailbox.os_mbox_accept_en - OS_MBOX_ACCEPT_EN - Boolean - 1 - 1 - system_h_define - Include code for OSMboxAccept() - none - false - - - - ucosii.mailbox.os_mbox_del_en - OS_MBOX_DEL_EN - Boolean - 1 - 1 - system_h_define - Include code for OSMboxDel() - none - false - - - - ucosii.mailbox.os_mbox_post_en - OS_MBOX_POST_EN - Boolean - 1 - 1 - system_h_define - Include code for OSMboxPost() - none - false - - - - ucosii.mailbox.os_mbox_post_opt_en - OS_MBOX_POST_OPT_EN - Boolean - 1 - 1 - system_h_define - Include code for OSMboxPostOpt() - none - false - - - - ucosii.mailbox.os_mbox_query_en - OS_MBOX_QUERY_EN - Boolean - 1 - 1 - system_h_define - Include code for OSMboxQuery() - none - false - - - - ucosii.os_q_en - OS_Q_EN - Boolean - 1 - 1 - system_h_define - Enable code for Queues - none - false - - - - ucosii.queue.os_q_accept_en - OS_Q_ACCEPT_EN - Boolean - 1 - 1 - system_h_define - Include code for OSQAccept() - none - false - - - - ucosii.queue.os_q_del_en - OS_Q_DEL_EN - Boolean - 1 - 1 - system_h_define - Include code for OSQDel() - none - false - - - - ucosii.queue.os_q_flush_en - OS_Q_FLUSH_EN - Boolean - 1 - 1 - system_h_define - Include code for OSQFlush() - none - false - - - - ucosii.queue.os_q_post_en - OS_Q_POST_EN - Boolean - 1 - 1 - system_h_define - Include code of OSQFlush() - none - false - - - - ucosii.queue.os_q_post_front_en - OS_Q_POST_FRONT_EN - Boolean - 1 - 1 - system_h_define - Include code for OSQPostFront() - none - false - - - - ucosii.queue.os_q_post_opt_en - OS_Q_POST_OPT_EN - Boolean - 1 - 1 - system_h_define - Include code for OSQPostOpt() - none - false - - - - ucosii.queue.os_q_query_en - OS_Q_QUERY_EN - Boolean - 1 - 1 - system_h_define - Include code for OSQQuery() - none - false - - - - ucosii.queue.os_max_qs - OS_MAX_QS - DecimalNumber - 20 - 20 - system_h_define - Maximum number of Queue Control Blocks - none - false - - - - ucosii.os_mem_en - OS_MEM_EN - Boolean - 1 - 1 - system_h_define - Enable code for memory management - none - false - - - - ucosii.memory.os_mem_query_en - OS_MEM_QUERY_EN - Boolean - 1 - 1 - system_h_define - Include code for OSMemQuery() - none - false - - - - ucosii.memory.os_mem_name_size - OS_MEM_NAME_SIZE - DecimalNumber - 32 - 32 - system_h_define - Size of memory partition name - none - false - - - - ucosii.memory.os_max_mem_part - OS_MAX_MEM_PART - DecimalNumber - 60 - 60 - system_h_define - Maximum number of memory partitions - none - false - - - - ucosii.os_tmr_en - OS_TMR_EN - Boolean - 0 - 0 - system_h_define - Enable code for timers - none - false - - - - ucosii.timer.os_task_tmr_stk_size - OS_TASK_TMR_STK_SIZE - DecimalNumber - 512 - 512 - system_h_define - Stack size for timer task - none - false - - - - ucosii.timer.os_task_tmr_prio - OS_TASK_TMR_PRIO - DecimalNumber - 0 - 0 - system_h_define - Priority of timer task (0=highest) - none - false - - - - ucosii.timer.os_tmr_cfg_max - OS_TMR_CFG_MAX - DecimalNumber - 16 - 16 - system_h_define - Maximum number of timers - none - false - - - - ucosii.timer.os_tmr_cfg_name_size - OS_TMR_CFG_NAME_SIZE - DecimalNumber - 16 - 16 - system_h_define - Size of timer name - none - false - - - - ucosii.timer.os_tmr_cfg_ticks_per_sec - OS_TMR_CFG_TICKS_PER_SEC - DecimalNumber - 10 - 10 - system_h_define - Rate at which timer management task runs (Hz) - none - false - - - - ucosii.timer.os_tmr_cfg_wheel_size - OS_TMR_CFG_WHEEL_SIZE - DecimalNumber - 2 - 2 - system_h_define - Size of timer wheel (number of spokes) - none - false - - - - altera_avalon_uart_driver.enable_small_driver - ALTERA_AVALON_UART_SMALL - BooleanDefineOnly - false - false - public_mk_define - Small-footprint (polled mode) driver - none - false - - - - altera_avalon_uart_driver.enable_ioctl - ALTERA_AVALON_UART_USE_IOCTL - BooleanDefineOnly - false - false - public_mk_define - Enable driver ioctl() support. This feature is not compatible with the 'small' driver; ioctl() support will not be compiled if either the UART 'enable_small_driver' or HAL 'enable_reduced_device_drivers' settings are enabled. - none - false - - - - altera_avalon_jtag_uart_driver.enable_small_driver - ALTERA_AVALON_JTAG_UART_SMALL - BooleanDefineOnly - false - false - public_mk_define - Small-footprint (polled mode) driver - none - false - - - - sdram - 0x01000000 - 0x01FFFFFF - 16777216 - memory - - - uart_mc - 0x02001000 - 0x0200101F - 32 - printable - - - pio_led - 0x02001020 - 0x0200103F - 32 - - - - uart_wifi - 0x02001040 - 0x0200105F - 32 - printable - - - sys_clk_timer - 0x02001060 - 0x0200107F - 32 - timer - - - pio_ir_emitter - 0x02001080 - 0x0200108F - 16 - - - - pio_sw - 0x02001090 - 0x0200109F - 16 - - - - pio_key_left - 0x020010A0 - 0x020010AF - 16 - - - - jtag_uart_0 - 0x020010B0 - 0x020010B7 - 8 - printable - - - sysid - 0x020010B8 - 0x020010BF - 8 - - - - .text - sdram - - - .rodata - sdram - - - .rwdata - sdram - - - .bss - sdram - - - .heap - sdram - - - .stack - sdram - - \ No newline at end of file diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/summary.html b/MCandWifiTestDE0/NewMCWifiTest_bsp/summary.html deleted file mode 100644 index eec8ccff..00000000 --- a/MCandWifiTestDE0/NewMCWifiTest_bsp/summary.html +++ /dev/null @@ -1,3943 +0,0 @@ - -Altera Nios II BSP Summary - -

BSP Description

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BSP Type:ucosii
SOPC Design File:C:\Users\gongal\ARCap\Repository\WifiTestDE0\system.sopcinfo
Quartus JDI File:default
CPU:cpu
BSP Settings File:.\settings.bsp
BSP Version:default
BSP Generated On:2-Mar-2014 3:16:23 PM
BSP Generated Timestamp:1393798583679
BSP Generated Location:C:\Users\gongal\NewRepARCap\MCandWifiTestDE0\NewMCWifiTest_bsp
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Nios II Memory Map

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Slave DescriptorAddress RangeSizeAttributes
sysid0x020010B8 - 0x020010BF8 
jtag_uart_00x020010B0 - 0x020010B78printable
pio_key_left0x020010A0 - 0x020010AF16 
pio_sw0x02001090 - 0x0200109F16 
pio_ir_emitter0x02001080 - 0x0200108F16 
sys_clk_timer0x02001060 - 0x0200107F32timer
uart_wifi0x02001040 - 0x0200105F32printable
pio_led0x02001020 - 0x0200103F32 
uart_mc0x02001000 - 0x0200101F32printable
sdram0x01000000 - 0x01FFFFFF16777216memory
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Linker Regions

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RegionAddress RangeSizeMemoryOffset
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Linker Section Mappings

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SectionRegion
.textsdram
.rodatasdram
.rwdatasdram
.bsssdram
.heapsdram
.stacksdram
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Settings

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Setting Name:altera_avalon_jtag_uart_driver.enable_small_driver
Identifier:ALTERA_AVALON_JTAG_UART_SMALL
Default Value:false
Value:false
Type:BooleanDefineOnly
Destination:public_mk_define
Description:Small-footprint (polled mode) driver
Restrictions:none
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Setting Name:altera_avalon_uart_driver.enable_ioctl
Identifier:ALTERA_AVALON_UART_USE_IOCTL
Default Value:false
Value:false
Type:BooleanDefineOnly
Destination:public_mk_define
Description:Enable driver ioctl() support. This feature is not compatible with the 'small' driver; ioctl() support will not be compiled if either the UART 'enable_small_driver' or HAL 'enable_reduced_device_drivers' settings are enabled.
Restrictions:none
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Setting Name:altera_avalon_uart_driver.enable_small_driver
Identifier:ALTERA_AVALON_UART_SMALL
Default Value:false
Value:false
Type:BooleanDefineOnly
Destination:public_mk_define
Description:Small-footprint (polled mode) driver
Restrictions:none
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Setting Name:hal.custom_newlib_flags
Identifier:CUSTOM_NEWLIB_FLAGS
Default Value:none
Value:none
Type:UnquotedString
Destination:public_mk_define
Description:Build a custom version of newlib with the specified space-separated compiler flags.
Restrictions:The custom newlib build will be placed in the &lt;bsp root>/newlib directory, and will be used only for applications that utilize this BSP.
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Setting Name:hal.enable_c_plus_plus
Identifier:ALT_NO_C_PLUS_PLUS
Default Value:1
Value:1
Type:Boolean
Destination:public_mk_define
Description:Enable support for a subset of the C++ language. This option increases code footprint by adding support for C++ constructors. Certain features, such as multiple inheritance and exceptions are not supported. If false, adds -DALT_NO_C_PLUS_PLUS to ALT_CPPFLAGS in public.mk, and reduces code footprint.
Restrictions:none
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Setting Name:hal.enable_clean_exit
Identifier:ALT_NO_CLEAN_EXIT
Default Value:1
Value:1
Type:Boolean
Destination:public_mk_define
Description:When your application exits, close file descriptors, call C++ destructors, etc. Code footprint can be reduced by disabling clean exit. If disabled, adds -DALT_NO_CLEAN_EXIT to ALT_CPPFLAGS and -Wl,--defsym, exit=_exit to ALT_LDFLAGS in public.mk.
Restrictions:none
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Setting Name:hal.enable_exit
Identifier:ALT_NO_EXIT
Default Value:1
Value:1
Type:Boolean
Destination:public_mk_define
Description:Add exit() support. This option increases code footprint if your "main()" routine does "return" or call "exit()". If false, adds -DALT_NO_EXIT to ALT_CPPFLAGS in public.mk, and reduces footprint
Restrictions:none
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Setting Name:hal.enable_gprof
Identifier:ALT_PROVIDE_GMON
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Causes code to be compiled with gprof profiling enabled and the application ELF to be linked with the GPROF library. If true, adds -DALT_PROVIDE_GMON to ALT_CPPFLAGS and -pg to ALT_CFLAGS in public.mk.
Restrictions:none
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Setting Name:hal.enable_instruction_related_exceptions_api
Identifier:ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API
Default Value:false
Value:false
Type:BooleanDefineOnly
Destination:system_h_define
Description:Enables API for registering handlers to service instruction-related exceptions. Enabling this setting increases the size of the exception entry code.
Restrictions:These exception types can be generated if various processor options are enabled, such as the MMU, MPU, or other advanced exception types.
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Setting Name:hal.enable_lightweight_device_driver_api
Identifier:ALT_USE_DIRECT_DRIVERS
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Enables lightweight device driver API. This reduces code and data footprint by removing the HAL layer that maps device names (e.g. /dev/uart0) to file descriptors. Instead, driver routines are called directly. The open(), close(), and lseek() routines will always fail if called. The read(), write(), fstat(), ioctl(), and isatty() routines only work for the stdio devices. If true, adds -DALT_USE_DIRECT_DRIVERS to ALT_CPPFLAGS in public.mk.
Restrictions:The Altera Host and read-only ZIP file systems can't be used if hal.enable_lightweight_device_driver_api is true.
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Setting Name:hal.enable_mul_div_emulation
Identifier:ALT_NO_INSTRUCTION_EMULATION
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Adds code to emulate multiply and divide instructions in case they are executed but aren't present in the CPU. Normally this isn't required because the compiler won't use multiply and divide instructions that aren't present in the CPU. If false, adds -DALT_NO_INSTRUCTION_EMULATION to ALT_CPPFLAGS in public.mk.
Restrictions:none
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Setting Name:hal.enable_reduced_device_drivers
Identifier:ALT_USE_SMALL_DRIVERS
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Certain drivers are compiled with reduced functionality to reduce code footprint. Not all drivers observe this setting. The altera_avalon_uart and altera_avalon_jtag_uart drivers switch from interrupt-driven to polled operation. CAUTION: Several device drivers are disabled entirely. These include the altera_avalon_cfi_flash, altera_avalon_epcs_flash_controller, and altera_avalon_lcd_16207 drivers. This can result in certain API (HAL flash access routines) to fail. You can define a symbol provided by each driver to prevent it from being removed. If true, adds -DALT_USE_SMALL_DRIVERS to ALT_CPPFLAGS in public.mk.
Restrictions:none
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Setting Name:hal.enable_runtime_stack_checking
Identifier:ALT_STACK_CHECK
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Turns on HAL runtime stack checking feature. Enabling this setting causes additional code to be placed into each subroutine call to generate an exception if a stack collision occurs with the heap or statically allocated data. If true, adds -DALT_STACK_CHECK and -mstack-check to ALT_CPPFLAGS in public.mk.
Restrictions:none
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Setting Name:hal.enable_sim_optimize
Identifier:ALT_SIM_OPTIMIZE
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:The BSP is compiled with optimizations to speedup HDL simulation such as initializing the cache, clearing the .bss section, and skipping long delay loops. If true, adds -DALT_SIM_OPTIMIZE to ALT_CPPFLAGS in public.mk.
Restrictions:When this setting is true, the BSP shouldn't be used to build applications that are expected to run real hardware.
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Setting Name:hal.enable_small_c_library
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Causes the small newlib (C library) to be used. This reduces code and data footprint at the expense of reduced functionality. Several newlib features are removed such as floating-point support in printf(), stdin input routines, and buffered I/O. The small C library is not compatible with Micrium MicroC/OS-II. If true, adds -msmallc to ALT_LDFLAGS in public.mk.
Restrictions:none
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Setting Name:hal.enable_sopc_sysid_check
Identifier:NONE
Default Value:1
Value:1
Type:Boolean
Destination:public_mk_define
Description:Enable SOPC Builder System ID. If a System ID SOPC Builder component is connected to the CPU associated with this BSP, it will be enabled in the creation of command-line arguments to download an ELF to the target. Otherwise, system ID and timestamp values are left out of public.mk for application Makefile "download-elf" target definition. With the system ID check disabled, the Nios II EDS tools will not automatically ensure that the application .elf file (and BSP it is linked against) corresponds to the hardware design on the target. If false, adds --accept-bad-sysid to SOPC_SYSID_FLAG in public.mk.
Restrictions:none
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Setting Name:hal.linker.allow_code_at_reset
Identifier:ALT_ALLOW_CODE_AT_RESET
Default Value:0
Value:1
Type:Boolean
Destination:none
Description:Indicates if initialization code is allowed at the reset address. If true, defines the macro ALT_ALLOW_CODE_AT_RESET in linker.h.
Restrictions:If true, defines the macro ALT_ALLOW_CODE_AT_RESET in linker.h. This setting is typically false if an external bootloader (e.g. flash bootloader) is present.
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Setting Name:hal.linker.enable_alt_load
Identifier:NONE
Default Value:0
Value:1
Type:Boolean
Destination:none
Description:Enables the alt_load() facility. The alt_load() facility copies sections from the .text memory into RAM. If true, this setting sets up the VMA/LMA of sections in linker.x to allow them to be loaded into the .text memory.
Restrictions:This setting is typically false if an external bootloader (e.g. flash bootloader) is present.
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Setting Name:hal.linker.enable_alt_load_copy_exceptions
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:none
Description:Causes the alt_load() facility to copy the .exceptions section. If true, this setting defines the macro ALT_LOAD_COPY_EXCEPTIONS in linker.h.
Restrictions:none
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Setting Name:hal.linker.enable_alt_load_copy_rodata
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:none
Description:Causes the alt_load() facility to copy the .rodata section. If true, this setting defines the macro ALT_LOAD_COPY_RODATA in linker.h.
Restrictions:none
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Setting Name:hal.linker.enable_alt_load_copy_rwdata
Identifier:NONE
Default Value:0
Value:1
Type:Boolean
Destination:none
Description:Causes the alt_load() facility to copy the .rwdata section. If true, this setting defines the macro ALT_LOAD_COPY_RWDATA in linker.h.
Restrictions:none
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Setting Name:hal.linker.enable_exception_stack
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:none
Description:Enables use of a separate exception stack. If true, defines the macro ALT_EXCEPTION_STACK in linker.h, adds a memory region called exception_stack to linker.x, and provides the symbols __alt_exception_stack_pointer and __alt_exception_stack_limit in linker.x.
Restrictions:The hal.linker.exception_stack_size and hal.linker.exception_stack_memory_region_name settings must also be valid. This setting must be false for MicroC/OS-II BSPs. The exception stack can be used to improve interrupt and other exception performance if the EIC is *not* used.
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Setting Name:hal.linker.enable_interrupt_stack
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:none
Description:Enables use of a separate interrupt stack. If true, defines the macro ALT_INTERRUPT_STACK in linker.h, adds a memory region called interrupt_stack to linker.x, and provides the symbols __alt_interrupt_stack_pointer and __alt_interrupt_stack_limit in linker.x.
Restrictions:The hal.linker.interrupt_stack_size and hal.linker.interrupt_stack_memory_region_name settings must also be valid. This setting must be false for MicroC/OS-II BSPs. Only enable if the EIC is used exclusively. The exception stack can be used to improve interrupt and other exception performance if the EIC is *not* used.
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Setting Name:hal.linker.exception_stack_memory_region_name
Identifier:NONE
Default Value:none
Value:sdram
Type:UnquotedString
Destination:none
Description:Name of the existing memory region that will be divided up to create the 'exception_stack' memory region. The selected region name will be adjusted automatically when the BSP is generated to create the 'exception_stack' memory region.
Restrictions:Only used if hal.linker.enable_exception_stack is true.
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Setting Name:hal.linker.exception_stack_size
Identifier:NONE
Default Value:1024
Value:1024
Type:DecimalNumber
Destination:none
Description:Size of the exception stack in bytes.
Restrictions:Only used if hal.linker.enable_exception_stack is true.
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Setting Name:hal.linker.interrupt_stack_memory_region_name
Identifier:NONE
Default Value:none
Value:sdram
Type:UnquotedString
Destination:none
Description:Name of the existing memory region that will be divided up to create the 'interrupt_stack' memory region. The selected region name will be adjusted automatically when the BSP is generated to create the 'interrupt_stack' memory region.
Restrictions:Only used if hal.linker.enable_interrupt_stack is true.
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Setting Name:hal.linker.interrupt_stack_size
Identifier:NONE
Default Value:1024
Value:1024
Type:DecimalNumber
Destination:none
Description:Size of the interrupt stack in bytes.
Restrictions:Only used if hal.linker.enable_interrupt_stack is true.
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Setting Name:hal.log_flags
Identifier:ALT_LOG_FLAGS
Default Value:0
Value:0
Type:DecimalNumber
Destination:public_mk_define
Description:The value is assigned to ALT_LOG_FLAGS in the generated public.mk. See hal.log_port setting description. Values can be -1 through 3.
Restrictions:hal.log_port must be set for this to be used.
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Setting Name:hal.log_port
Identifier:NONE
Default Value:none
Value:none
Type:UnquotedString
Destination:public_mk_define
Description:Slave descriptor of debug logging character-mode device. If defined, it enables extra debug messages in the HAL source. This setting is used by the ALT_LOG_PORT family of defines in system.h.
Restrictions:none
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Setting Name:hal.make.ar
Identifier:AR
Default Value:nios2-elf-ar
Value:nios2-elf-ar
Type:UnquotedString
Destination:makefile_variable
Description:Archiver command. Creates library files.
Restrictions:none
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Setting Name:hal.make.ar_post_process
Identifier:AR_POST_PROCESS
Default Value:none
Value:none
Type:UnquotedString
Destination:makefile_variable
Description:Command executed after archiver execution.
Restrictions:none
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Setting Name:hal.make.ar_pre_process
Identifier:AR_PRE_PROCESS
Default Value:none
Value:none
Type:UnquotedString
Destination:makefile_variable
Description:Command executed before archiver execution.
Restrictions:none
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Setting Name:hal.make.as
Identifier:AS
Default Value:nios2-elf-gcc
Value:nios2-elf-gcc
Type:UnquotedString
Destination:makefile_variable
Description:Assembler command. Note that CC is used for .S files.
Restrictions:none
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Setting Name:hal.make.as_post_process
Identifier:AS_POST_PROCESS
Default Value:none
Value:none
Type:UnquotedString
Destination:makefile_variable
Description:Command executed after each assembly file is compiled.
Restrictions:none
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Setting Name:hal.make.as_pre_process
Identifier:AS_PRE_PROCESS
Default Value:none
Value:none
Type:UnquotedString
Destination:makefile_variable
Description:Command executed before each assembly file is compiled.
Restrictions:none
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Setting Name:hal.make.bsp_arflags
Identifier:BSP_ARFLAGS
Default Value:-src
Value:-src
Type:UnquotedString
Destination:makefile_variable
Description:Custom flags only passed to the archiver. This content of this variable is directly passed to the archiver rather than the more standard "ARFLAGS". The reason for this is that GNU Make assumes some default content in ARFLAGS. This setting defines the value of BSP_ARFLAGS in Makefile.
Restrictions:none
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Setting Name:hal.make.bsp_asflags
Identifier:BSP_ASFLAGS
Default Value:-Wa,-gdwarf2
Value:-Wa,-gdwarf2
Type:UnquotedString
Destination:makefile_variable
Description:Custom flags only passed to the assembler. This setting defines the value of BSP_ASFLAGS in Makefile.
Restrictions:none
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Setting Name:hal.make.bsp_cflags_debug
Identifier:BSP_CFLAGS_DEBUG
Default Value:-g
Value:-g
Type:UnquotedString
Destination:makefile_variable
Description:C/C++ compiler debug level. '-g' provides the default set of debug symbols typically required to debug a typical application. Omitting '-g' removes debug symbols from the ELF. This setting defines the value of BSP_CFLAGS_DEBUG in Makefile.
Restrictions:none
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Setting Name:hal.make.bsp_cflags_defined_symbols
Identifier:BSP_CFLAGS_DEFINED_SYMBOLS
Default Value:none
Value:none
Type:UnquotedString
Destination:makefile_variable
Description:Preprocessor macros to define. A macro definition in this setting has the same effect as a "#define" in source code. Adding "-DALT_DEBUG" to this setting has the same effect as "#define ALT_DEBUG" in a souce file. Adding "-DFOO=1" to this setting is equivalent to the macro "#define FOO 1" in a source file. Macros defined with this setting are applied to all .S, .c, and C++ files in the BSP. This setting defines the value of BSP_CFLAGS_DEFINED_SYMBOLS in the BSP Makefile.
Restrictions:none
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Setting Name:hal.make.bsp_cflags_optimization
Identifier:BSP_CFLAGS_OPTIMIZATION
Default Value:-O0
Value:-O0
Type:UnquotedString
Destination:makefile_variable
Description:C/C++ compiler optimization level. "-O0" = no optimization,"-O2" = "normal" optimization, etc. "-O0" is recommended for code that you want to debug since compiler optimization can remove variables and produce non-sequential execution of code while debugging. This setting defines the value of BSP_CFLAGS_OPTIMIZATION in Makefile.
Restrictions:none
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Setting Name:hal.make.bsp_cflags_undefined_symbols
Identifier:BSP_CFLAGS_UNDEFINED_SYMBOLS
Default Value:none
Value:none
Type:UnquotedString
Destination:makefile_variable
Description:Preprocessor macros to undefine. Undefined macros are similar to defined macros, but replicate the "#undef" directive in source code. To undefine the macro FOO use the syntax "-u FOO" in this setting. This is equivalent to "#undef FOO" in a source file. Note: the syntax differs from macro definition (there is a space, i.e. "-u FOO" versus "-DFOO"). Macros defined with this setting are applied to all .S, .c, and C++ files in the BSP. This setting defines the value of BSP_CFLAGS_UNDEFINED_SYMBOLS in the BSP Makefile.
Restrictions:none
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Setting Name:hal.make.bsp_cflags_user_flags
Identifier:BSP_CFLAGS_USER_FLAGS
Default Value:none
Value:none
Type:UnquotedString
Destination:makefile_variable
Description:Custom flags passed to the compiler when compiling C, C++, and .S files. This setting defines the value of BSP_CFLAGS_USER_FLAGS in Makefile.
Restrictions:none
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Setting Name:hal.make.bsp_cflags_warnings
Identifier:BSP_CFLAGS_WARNINGS
Default Value:-Wall
Value:-Wall
Type:UnquotedString
Destination:makefile_variable
Description:C/C++ compiler warning level. "-Wall" is commonly used.This setting defines the value of BSP_CFLAGS_WARNINGS in Makefile.
Restrictions:none
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Setting Name:hal.make.bsp_cxx_flags
Identifier:BSP_CXXFLAGS
Default Value:none
Value:none
Type:UnquotedString
Destination:makefile_variable
Description:Custom flags only passed to the C++ compiler. This setting defines the value of BSP_CXXFLAGS in Makefile.
Restrictions:none
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Setting Name:hal.make.bsp_inc_dirs
Identifier:BSP_INC_DIRS
Default Value:none
Value:none
Type:UnquotedString
Destination:makefile_variable
Description:Space separated list of extra include directories to scan for header files. Directories are relative to the top-level BSP directory. The -I prefix's added by the makefile so don't add it here. This setting defines the value of BSP_INC_DIRS in Makefile.
Restrictions:none
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Setting Name:hal.make.build_post_process
Identifier:BUILD_POST_PROCESS
Default Value:none
Value:none
Type:UnquotedString
Destination:makefile_variable
Description:Command executed after BSP built.
Restrictions:none
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Setting Name:hal.make.build_pre_process
Identifier:BUILD_PRE_PROCESS
Default Value:none
Value:none
Type:UnquotedString
Destination:makefile_variable
Description:Command executed before BSP built.
Restrictions:none
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Setting Name:hal.make.cc
Identifier:CC
Default Value:nios2-elf-gcc -xc
Value:nios2-elf-gcc -xc
Type:UnquotedString
Destination:makefile_variable
Description:C compiler command.
Restrictions:none
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Setting Name:hal.make.cc_post_process
Identifier:CC_POST_PROCESS
Default Value:none
Value:none
Type:UnquotedString
Destination:makefile_variable
Description:Command executed after each .c/.S file is compiled.
Restrictions:none
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Setting Name:hal.make.cc_pre_process
Identifier:CC_PRE_PROCESS
Default Value:none
Value:none
Type:UnquotedString
Destination:makefile_variable
Description:Command executed before each .c/.S file is compiled.
Restrictions:none
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Setting Name:hal.make.cxx
Identifier:CXX
Default Value:nios2-elf-gcc -xc++
Value:nios2-elf-gcc -xc++
Type:UnquotedString
Destination:makefile_variable
Description:C++ compiler command.
Restrictions:none
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Setting Name:hal.make.cxx_post_process
Identifier:CXX_POST_PROCESS
Default Value:none
Value:none
Type:UnquotedString
Destination:makefile_variable
Description:Command executed before each C++ file is compiled.
Restrictions:none
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Setting Name:hal.make.cxx_pre_process
Identifier:CXX_PRE_PROCESS
Default Value:none
Value:none
Type:UnquotedString
Destination:makefile_variable
Description:Command executed before each C++ file is compiled.
Restrictions:none
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Setting Name:hal.make.ignore_system_derived.big_endian
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Enable BSP generation to query if SOPC system is big endian. If true ignores export of 'ALT_CFLAGS += -EB' to public.mk if big endian system. If true ignores export of 'ALT_CFLAGS += -EL' if little endian system.
Restrictions:none
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Setting Name:hal.make.ignore_system_derived.debug_core_present
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Enable BSP generation to query if SOPC system has a debug core present. If true ignores export of 'CPU_HAS_DEBUG_CORE = 1' to public.mk if a debug core is found in the system. If true ignores export of 'CPU_HAS_DEBUG_CORE = 0' if no debug core is found in the system.
Restrictions:none
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Setting Name:hal.make.ignore_system_derived.fpu_present
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Enable BSP generation to query if SOPC system has FPU present. If true ignores export of 'ALT_CFLAGS += -mhard-float' to public.mk if FPU is found in the system. If true ignores export of 'ALT_CFLAGS += -mhard-soft' if FPU is not found in the system.
Restrictions:none
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Setting Name:hal.make.ignore_system_derived.hardware_divide_present
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Enable BSP generation to query if SOPC system has hardware divide present. If true ignores export of 'ALT_CFLAGS += -mno-hw-div' to public.mk if no division is found in system. If true ignores export of 'ALT_CFLAGS += -mhw-div' if division is found in the system.
Restrictions:none
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Setting Name:hal.make.ignore_system_derived.hardware_fp_cust_inst_divider_present
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Enable BSP generation to query if SOPC system floating point custom instruction with a divider is present. If true ignores export of 'ALT_CFLAGS += -mcustom-fpu-cfg=60-2' and 'ALT_LDFLAGS += -mcustom-fpu-cfg=60-2' to public.mk if the custom instruction is found in the system.
Restrictions:none
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Setting Name:hal.make.ignore_system_derived.hardware_fp_cust_inst_no_divider_present
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Enable BSP generation to query if SOPC system floating point custom instruction without a divider is present. If true ignores export of 'ALT_CFLAGS += -mcustom-fpu-cfg=60-1' and 'ALT_LDFLAGS += -mcustom-fpu-cfg=60-1' to public.mk if the custom instruction is found in the system.
Restrictions:none
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Setting Name:hal.make.ignore_system_derived.hardware_multiplier_present
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Enable BSP generation to query if SOPC system has multiplier present. If true ignores export of 'ALT_CFLAGS += -mno-hw-mul' to public.mk if no multiplier is found in the system. If true ignores export of 'ALT_CFLAGS += -mhw-mul' if multiplier is found in the system.
Restrictions:none
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Setting Name:hal.make.ignore_system_derived.hardware_mulx_present
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Enable BSP generation to query if SOPC system has hardware mulx present. If true ignores export of 'ALT_CFLAGS += -mno-hw-mulx' to public.mk if no mulx is found in the system. If true ignores export of 'ALT_CFLAGS += -mhw-mulx' if mulx is found in the system.
Restrictions:none
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Setting Name:hal.make.ignore_system_derived.sopc_simulation_enabled
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Enable BSP generation to query if SOPC system has simulation enabled. If true ignores export of 'ELF_PATCH_FLAG += --simulation_enabled' to public.mk.
Restrictions:none
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Setting Name:hal.make.ignore_system_derived.sopc_system_base_address
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Enable BSP generation to query SOPC system for system ID base address. If true ignores export of 'SOPC_SYSID_FLAG += --sidp=<address>' and 'ELF_PATCH_FLAG += --sidp=<address>' to public.mk.
Restrictions:none
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Setting Name:hal.make.ignore_system_derived.sopc_system_id
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Enable BSP generation to query SOPC system for system ID. If true ignores export of 'SOPC_SYSID_FLAG += --id=<sysid>' and 'ELF_PATCH_FLAG += --id=<sysid>' to public.mk.
Restrictions:none
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Setting Name:hal.make.ignore_system_derived.sopc_system_timestamp
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Enable BSP generation to query SOPC system for system timestamp. If true ignores export of 'SOPC_SYSID_FLAG += --timestamp=<timestamp>' and 'ELF_PATCH_FLAG += --timestamp=<timestamp>' to public.mk.
Restrictions:none
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Setting Name:hal.make.rm
Identifier:RM
Default Value:rm -f
Value:rm -f
Type:UnquotedString
Destination:makefile_variable
Description:Command used to remove files during 'clean' target.
Restrictions:none
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Setting Name:hal.max_file_descriptors
Identifier:ALT_MAX_FD
Default Value:32
Value:32
Type:DecimalNumber
Destination:system_h_define
Description:Determines the number of file descriptors statically allocated. This setting defines the value of ALT_MAX_FD in system.h.
Restrictions:If hal.enable_lightweight_device_driver_api is true, there are no file descriptors so this setting is ignored. If hal.enable_lightweight_device_driver_api is false, this setting must be at least 4 because HAL needs a file descriptor for /dev/null, /dev/stdin, /dev/stdout, and /dev/stderr.
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Setting Name:hal.stderr
Identifier:NONE
Default Value:none
Value:jtag_uart_0
Type:UnquotedString
Destination:system_h_define
Description:Slave descriptor of STDERR character-mode device. This setting is used by the ALT_STDERR family of defines in system.h.
Restrictions:none
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Setting Name:hal.stdin
Identifier:NONE
Default Value:none
Value:jtag_uart_0
Type:UnquotedString
Destination:system_h_define
Description:Slave descriptor of STDIN character-mode device. This setting is used by the ALT_STDIN family of defines in system.h.
Restrictions:none
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Setting Name:hal.stdout
Identifier:NONE
Default Value:none
Value:jtag_uart_0
Type:UnquotedString
Destination:system_h_define
Description:Slave descriptor of STDOUT character-mode device. This setting is used by the ALT_STDOUT family of defines in system.h.
Restrictions:none
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Setting Name:hal.sys_clk_timer
Identifier:ALT_SYS_CLK
Default Value:none
Value:sys_clk_timer
Type:UnquotedString
Destination:system_h_define
Description:Slave descriptor of the system clock timer device. This device provides a periodic interrupt ("tick") and is typically required for RTOS use. This setting defines the value of ALT_SYS_CLK in system.h.
Restrictions:none
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Setting Name:hal.timestamp_timer
Identifier:ALT_TIMESTAMP_CLK
Default Value:none
Value:none
Type:UnquotedString
Destination:system_h_define
Description:Slave descriptor of timestamp timer device. This device is used by Altera HAL timestamp drivers for high-resolution time measurement. This setting defines the value of ALT_TIMESTAMP_CLK in system.h.
Restrictions:none
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Setting Name:ucosii.event_flag.os_flag_accept_en
Identifier:OS_FLAG_ACCEPT_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSFlagAccept(). CAUTION: This is required by the HAL and many Altera device drivers.
Restrictions:none
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Setting Name:ucosii.event_flag.os_flag_del_en
Identifier:OS_FLAG_DEL_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSFlagDel(). CAUTION: This is required by the HAL and many Altera device drivers.
Restrictions:none
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Setting Name:ucosii.event_flag.os_flag_name_size
Identifier:OS_FLAG_NAME_SIZE
Default Value:32
Value:32
Type:DecimalNumber
Destination:system_h_define
Description:Size of name of Event Flags group. CAUTION: This is required by the HAL and many Altera device drivers; use caution in reducing this value.
Restrictions:none
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Setting Name:ucosii.event_flag.os_flag_query_en
Identifier:OS_FLAG_QUERY_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSFlagQuery(). CAUTION: This is required by the HAL and many Altera device drivers.
Restrictions:none
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Setting Name:ucosii.event_flag.os_flag_wait_clr_en
Identifier:OS_FLAG_WAIT_CLR_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for Wait on Clear Event Flags. CAUTION: This is required by the HAL and many Altera device drivers.
Restrictions:none
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Setting Name:ucosii.event_flag.os_flags_nbits
Identifier:OS_FLAGS_NBITS
Default Value:16
Value:16
Type:DecimalNumber
Destination:system_h_define
Description:Event Flag bits (8,16,32). CAUTION: This is required by the HAL and many Altera device drivers; use caution in changing this value.
Restrictions:none
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Setting Name:ucosii.event_flag.os_max_flags
Identifier:OS_MAX_FLAGS
Default Value:20
Value:20
Type:DecimalNumber
Destination:system_h_define
Description:Maximum number of Event Flags groups. CAUTION: This is required by the HAL and many Altera device drivers; use caution in reducing this value.
Restrictions:none
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Setting Name:ucosii.mailbox.os_mbox_accept_en
Identifier:OS_MBOX_ACCEPT_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSMboxAccept()
Restrictions:none
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Setting Name:ucosii.mailbox.os_mbox_del_en
Identifier:OS_MBOX_DEL_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSMboxDel()
Restrictions:none
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Setting Name:ucosii.mailbox.os_mbox_post_en
Identifier:OS_MBOX_POST_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSMboxPost()
Restrictions:none
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Setting Name:ucosii.mailbox.os_mbox_post_opt_en
Identifier:OS_MBOX_POST_OPT_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSMboxPostOpt()
Restrictions:none
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Setting Name:ucosii.mailbox.os_mbox_query_en
Identifier:OS_MBOX_QUERY_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSMboxQuery()
Restrictions:none
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Setting Name:ucosii.memory.os_max_mem_part
Identifier:OS_MAX_MEM_PART
Default Value:60
Value:60
Type:DecimalNumber
Destination:system_h_define
Description:Maximum number of memory partitions
Restrictions:none
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Setting Name:ucosii.memory.os_mem_name_size
Identifier:OS_MEM_NAME_SIZE
Default Value:32
Value:32
Type:DecimalNumber
Destination:system_h_define
Description:Size of memory partition name
Restrictions:none
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Setting Name:ucosii.memory.os_mem_query_en
Identifier:OS_MEM_QUERY_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSMemQuery()
Restrictions:none
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Setting Name:ucosii.miscellaneous.os_arg_chk_en
Identifier:OS_ARG_CHK_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Enable argument checking
Restrictions:none
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Setting Name:ucosii.miscellaneous.os_cpu_hooks_en
Identifier:OS_CPU_HOOKS_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Enable uCOS-II hooks
Restrictions:none
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Setting Name:ucosii.miscellaneous.os_debug_en
Identifier:OS_DEBUG_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Enable debug variables
Restrictions:none
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Setting Name:ucosii.miscellaneous.os_event_name_size
Identifier:OS_EVENT_NAME_SIZE
Default Value:32
Value:32
Type:DecimalNumber
Destination:system_h_define
Description:Size of name of Event Control Block groups
Restrictions:none
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Setting Name:ucosii.miscellaneous.os_max_events
Identifier:OS_MAX_EVENTS
Default Value:60
Value:60
Type:DecimalNumber
Destination:system_h_define
Description:Maximum number of event control blocks
Restrictions:none
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Setting Name:ucosii.miscellaneous.os_sched_lock_en
Identifier:OS_SCHED_LOCK_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSSchedLock() and OSSchedUnlock()
Restrictions:none
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Setting Name:ucosii.miscellaneous.os_task_idle_stk_size
Identifier:OS_TASK_IDLE_STK_SIZE
Default Value:512
Value:512
Type:DecimalNumber
Destination:system_h_define
Description:Idle task stack size
Restrictions:none
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Setting Name:ucosii.miscellaneous.os_task_stat_en
Identifier:OS_TASK_STAT_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Enable statistics task
Restrictions:none
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Setting Name:ucosii.miscellaneous.os_task_stat_stk_chk_en
Identifier:OS_TASK_STAT_STK_CHK_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Check task stacks from statistics task
Restrictions:none
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Setting Name:ucosii.miscellaneous.os_task_stat_stk_size
Identifier:OS_TASK_STAT_STK_SIZE
Default Value:512
Value:512
Type:DecimalNumber
Destination:system_h_define
Description:Statistics task stack size
Restrictions:none
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Setting Name:ucosii.miscellaneous.os_tick_step_en
Identifier:OS_TICK_STEP_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Enable tick stepping feature for uCOS-View
Restrictions:none
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Setting Name:ucosii.mutex.os_mutex_accept_en
Identifier:OS_MUTEX_ACCEPT_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSMutexAccept()
Restrictions:none
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Setting Name:ucosii.mutex.os_mutex_del_en
Identifier:OS_MUTEX_DEL_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSMutexDel()
Restrictions:none
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Setting Name:ucosii.mutex.os_mutex_query_en
Identifier:OS_MUTEX_QUERY_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSMutexQuery
Restrictions:none
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Setting Name:ucosii.os_flag_en
Identifier:OS_FLAG_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Enable code for Event Flags. CAUTION: This is required by the HAL and many Altera device drivers.
Restrictions:none
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Setting Name:ucosii.os_lowest_prio
Identifier:OS_LOWEST_PRIO
Default Value:20
Value:20
Type:DecimalNumber
Destination:system_h_define
Description:Lowest assignable priority
Restrictions:none
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Setting Name:ucosii.os_max_tasks
Identifier:OS_MAX_TASKS
Default Value:10
Value:10
Type:DecimalNumber
Destination:system_h_define
Description:Maximum number of tasks
Restrictions:none
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Setting Name:ucosii.os_mbox_en
Identifier:OS_MBOX_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Enable code for mailboxes
Restrictions:none
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Setting Name:ucosii.os_mem_en
Identifier:OS_MEM_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Enable code for memory management
Restrictions:none
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Setting Name:ucosii.os_mutex_en
Identifier:OS_MUTEX_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Enable code for Mutex Semaphores
Restrictions:none
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Setting Name:ucosii.os_q_en
Identifier:OS_Q_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Enable code for Queues
Restrictions:none
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Setting Name:ucosii.os_sem_en
Identifier:OS_SEM_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Enable code for semaphores. CAUTION: This is required by the HAL and many Altera device drivers.
Restrictions:none
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Setting Name:ucosii.os_thread_safe_newlib
Identifier:OS_THREAD_SAFE_NEWLIB
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Thread safe C library
Restrictions:none
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Setting Name:ucosii.os_tmr_en
Identifier:OS_TMR_EN
Default Value:0
Value:0
Type:Boolean
Destination:system_h_define
Description:Enable code for timers
Restrictions:none
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Setting Name:ucosii.queue.os_max_qs
Identifier:OS_MAX_QS
Default Value:20
Value:20
Type:DecimalNumber
Destination:system_h_define
Description:Maximum number of Queue Control Blocks
Restrictions:none
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Setting Name:ucosii.queue.os_q_accept_en
Identifier:OS_Q_ACCEPT_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSQAccept()
Restrictions:none
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Setting Name:ucosii.queue.os_q_del_en
Identifier:OS_Q_DEL_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSQDel()
Restrictions:none
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Setting Name:ucosii.queue.os_q_flush_en
Identifier:OS_Q_FLUSH_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSQFlush()
Restrictions:none
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Setting Name:ucosii.queue.os_q_post_en
Identifier:OS_Q_POST_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code of OSQFlush()
Restrictions:none
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Setting Name:ucosii.queue.os_q_post_front_en
Identifier:OS_Q_POST_FRONT_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSQPostFront()
Restrictions:none
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Setting Name:ucosii.queue.os_q_post_opt_en
Identifier:OS_Q_POST_OPT_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSQPostOpt()
Restrictions:none
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Setting Name:ucosii.queue.os_q_query_en
Identifier:OS_Q_QUERY_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSQQuery()
Restrictions:none
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Setting Name:ucosii.semaphore.os_sem_accept_en
Identifier:OS_SEM_ACCEPT_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSSemAccept(). CAUTION: This is required by the HAL and many Altera device drivers.
Restrictions:none
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Setting Name:ucosii.semaphore.os_sem_del_en
Identifier:OS_SEM_DEL_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSSemDel(). CAUTION: This is required by the HAL and many Altera device drivers.
Restrictions:none
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Setting Name:ucosii.semaphore.os_sem_query_en
Identifier:OS_SEM_QUERY_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSSemQuery(). CAUTION: This is required by the HAL and many Altera device drivers.
Restrictions:none
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Setting Name:ucosii.semaphore.os_sem_set_en
Identifier:OS_SEM_SET_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSSemSet(). CAUTION: This is required by the HAL and many Altera device drivers.
Restrictions:none
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Setting Name:ucosii.task.os_task_change_prio_en
Identifier:OS_TASK_CHANGE_PRIO_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSTaskChangePrio()
Restrictions:none
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Setting Name:ucosii.task.os_task_create_en
Identifier:OS_TASK_CREATE_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSTaskCreate()
Restrictions:none
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Setting Name:ucosii.task.os_task_create_ext_en
Identifier:OS_TASK_CREATE_EXT_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSTaskCreateExt()
Restrictions:none
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Setting Name:ucosii.task.os_task_del_en
Identifier:OS_TASK_DEL_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSTaskDel()
Restrictions:none
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Setting Name:ucosii.task.os_task_name_size
Identifier:OS_TASK_NAME_SIZE
Default Value:32
Value:32
Type:DecimalNumber
Destination:system_h_define
Description:Size of task name
Restrictions:none
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Setting Name:ucosii.task.os_task_profile_en
Identifier:OS_TASK_PROFILE_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include data structure for run-time task profiling
Restrictions:none
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Setting Name:ucosii.task.os_task_query_en
Identifier:OS_TASK_QUERY_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSTaskQuery
Restrictions:none
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Setting Name:ucosii.task.os_task_suspend_en
Identifier:OS_TASK_SUSPEND_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSTaskSuspend() and OSTaskResume()
Restrictions:none
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Setting Name:ucosii.task.os_task_sw_hook_en
Identifier:OS_TASK_SW_HOOK_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSTaskSwHook()
Restrictions:none
-
- - - - - - - - - - - - - - - - - - - - - - - - - -
Setting Name:ucosii.time.os_time_dly_hmsm_en
Identifier:OS_TIME_DLY_HMSM_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSTimeDlyHMSM()
Restrictions:none
-
- - - - - - - - - - - - - - - - - - - - - - - - - -
Setting Name:ucosii.time.os_time_dly_resume_en
Identifier:OS_TIME_DLY_RESUME_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSTimeDlyResume()
Restrictions:none
-
- - - - - - - - - - - - - - - - - - - - - - - - - -
Setting Name:ucosii.time.os_time_get_set_en
Identifier:OS_TIME_GET_SET_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSTimeGet and OSTimeSet()
Restrictions:none
-
- - - - - - - - - - - - - - - - - - - - - - - - - -
Setting Name:ucosii.time.os_time_tick_hook_en
Identifier:OS_TIME_TICK_HOOK_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSTimeTickHook()
Restrictions:none
-
- - - - - - - - - - - - - - - - - - - - - - - - - -
Setting Name:ucosii.timer.os_task_tmr_prio
Identifier:OS_TASK_TMR_PRIO
Default Value:0
Value:0
Type:DecimalNumber
Destination:system_h_define
Description:Priority of timer task (0=highest)
Restrictions:none
-
- - - - - - - - - - - - - - - - - - - - - - - - - -
Setting Name:ucosii.timer.os_task_tmr_stk_size
Identifier:OS_TASK_TMR_STK_SIZE
Default Value:512
Value:512
Type:DecimalNumber
Destination:system_h_define
Description:Stack size for timer task
Restrictions:none
-
- - - - - - - - - - - - - - - - - - - - - - - - - -
Setting Name:ucosii.timer.os_tmr_cfg_max
Identifier:OS_TMR_CFG_MAX
Default Value:16
Value:16
Type:DecimalNumber
Destination:system_h_define
Description:Maximum number of timers
Restrictions:none
-
- - - - - - - - - - - - - - - - - - - - - - - - - -
Setting Name:ucosii.timer.os_tmr_cfg_name_size
Identifier:OS_TMR_CFG_NAME_SIZE
Default Value:16
Value:16
Type:DecimalNumber
Destination:system_h_define
Description:Size of timer name
Restrictions:none
-
- - - - - - - - - - - - - - - - - - - - - - - - - -
Setting Name:ucosii.timer.os_tmr_cfg_ticks_per_sec
Identifier:OS_TMR_CFG_TICKS_PER_SEC
Default Value:10
Value:10
Type:DecimalNumber
Destination:system_h_define
Description:Rate at which timer management task runs (Hz)
Restrictions:none
-
- - - - - - - - - - - - - - - - - - - - - - - - - -
Setting Name:ucosii.timer.os_tmr_cfg_wheel_size
Identifier:OS_TMR_CFG_WHEEL_SIZE
Default Value:2
Value:2
Type:DecimalNumber
Destination:system_h_define
Description:Size of timer wheel (number of spokes)
Restrictions:none
-
-
-
- - diff --git a/MCandWifiTestDE0/NewMCWifiTest_bsp/system.h b/MCandWifiTestDE0/NewMCWifiTest_bsp/system.h deleted file mode 100644 index 03612edd..00000000 --- a/MCandWifiTestDE0/NewMCWifiTest_bsp/system.h +++ /dev/null @@ -1,519 +0,0 @@ -/* - * system.h - SOPC Builder system and BSP software package information - * - * Machine generated for CPU 'cpu' in SOPC Builder design 'system' - * SOPC Builder design path: C:/Users/gongal/ARCap/Repository/WifiTestDE0/system.sopcinfo - * - * Generated: Sun Mar 02 15:16:24 MST 2014 - */ - -/* - * DO NOT MODIFY THIS FILE - * - * Changing this file will have subtle consequences - * which will almost certainly lead to a nonfunctioning - * system. If you do modify this file, be aware that your - * changes will be overwritten and lost when this file - * is generated again. - * - * DO NOT MODIFY THIS FILE - */ - -/* - * License Agreement - * - * Copyright (c) 2008 - * Altera Corporation, San Jose, California, USA. - * All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - * This agreement shall be governed in all respects by the laws of the State - * of California and by the laws of the United States of America. - */ - -#ifndef __SYSTEM_H_ -#define __SYSTEM_H_ - -/* Include definitions from linker script generator */ -#include "linker.h" - - -/* - * CPU configuration - * - */ - -#define ALT_CPU_ARCHITECTURE "altera_nios2_qsys" -#define ALT_CPU_BIG_ENDIAN 0 -#define ALT_CPU_BREAK_ADDR 0x2000820 -#define ALT_CPU_CPU_FREQ 100000000u -#define ALT_CPU_CPU_ID_SIZE 1 -#define ALT_CPU_CPU_ID_VALUE 0x00000000 -#define ALT_CPU_CPU_IMPLEMENTATION "fast" -#define ALT_CPU_DATA_ADDR_WIDTH 0x1a -#define ALT_CPU_DCACHE_LINE_SIZE 32 -#define ALT_CPU_DCACHE_LINE_SIZE_LOG2 5 -#define ALT_CPU_DCACHE_SIZE 4096 -#define ALT_CPU_EXCEPTION_ADDR 0x1000020 -#define ALT_CPU_FLUSHDA_SUPPORTED -#define ALT_CPU_FREQ 100000000 -#define ALT_CPU_HARDWARE_DIVIDE_PRESENT 0 -#define ALT_CPU_HARDWARE_MULTIPLY_PRESENT 1 -#define ALT_CPU_HARDWARE_MULX_PRESENT 0 -#define ALT_CPU_HAS_DEBUG_CORE 1 -#define ALT_CPU_HAS_DEBUG_STUB -#define ALT_CPU_HAS_JMPI_INSTRUCTION -#define ALT_CPU_ICACHE_LINE_SIZE 32 -#define ALT_CPU_ICACHE_LINE_SIZE_LOG2 5 -#define ALT_CPU_ICACHE_SIZE 8192 -#define ALT_CPU_INITDA_SUPPORTED -#define ALT_CPU_INST_ADDR_WIDTH 0x1a -#define ALT_CPU_NAME "cpu" -#define ALT_CPU_NUM_OF_SHADOW_REG_SETS 0 -#define ALT_CPU_RESET_ADDR 0x1000000 - - -/* - * CPU configuration (with legacy prefix - don't use these anymore) - * - */ - -#define NIOS2_BIG_ENDIAN 0 -#define NIOS2_BREAK_ADDR 0x2000820 -#define NIOS2_CPU_FREQ 100000000u -#define NIOS2_CPU_ID_SIZE 1 -#define NIOS2_CPU_ID_VALUE 0x00000000 -#define NIOS2_CPU_IMPLEMENTATION "fast" -#define NIOS2_DATA_ADDR_WIDTH 0x1a -#define NIOS2_DCACHE_LINE_SIZE 32 -#define NIOS2_DCACHE_LINE_SIZE_LOG2 5 -#define NIOS2_DCACHE_SIZE 4096 -#define NIOS2_EXCEPTION_ADDR 0x1000020 -#define NIOS2_FLUSHDA_SUPPORTED -#define NIOS2_HARDWARE_DIVIDE_PRESENT 0 -#define NIOS2_HARDWARE_MULTIPLY_PRESENT 1 -#define NIOS2_HARDWARE_MULX_PRESENT 0 -#define NIOS2_HAS_DEBUG_CORE 1 -#define NIOS2_HAS_DEBUG_STUB -#define NIOS2_HAS_JMPI_INSTRUCTION -#define NIOS2_ICACHE_LINE_SIZE 32 -#define NIOS2_ICACHE_LINE_SIZE_LOG2 5 -#define NIOS2_ICACHE_SIZE 8192 -#define NIOS2_INITDA_SUPPORTED -#define NIOS2_INST_ADDR_WIDTH 0x1a -#define NIOS2_NUM_OF_SHADOW_REG_SETS 0 -#define NIOS2_RESET_ADDR 0x1000000 - - -/* - * Define for each module class mastered by the CPU - * - */ - -#define __ALTERA_AVALON_JTAG_UART -#define __ALTERA_AVALON_NEW_SDRAM_CONTROLLER -#define __ALTERA_AVALON_PIO -#define __ALTERA_AVALON_SYSID_QSYS -#define __ALTERA_AVALON_TIMER -#define __ALTERA_AVALON_UART -#define __ALTERA_NIOS2_QSYS - - -/* - * System configuration - * - */ - -#define ALT_DEVICE_FAMILY "Cyclone IV E" -#define ALT_ENHANCED_INTERRUPT_API_PRESENT -#define ALT_IRQ_BASE NULL -#define ALT_LOG_PORT "/dev/null" -#define ALT_LOG_PORT_BASE 0x0 -#define ALT_LOG_PORT_DEV null -#define ALT_LOG_PORT_TYPE "" -#define ALT_NUM_EXTERNAL_INTERRUPT_CONTROLLERS 0 -#define ALT_NUM_INTERNAL_INTERRUPT_CONTROLLERS 1 -#define ALT_NUM_INTERRUPT_CONTROLLERS 1 -#define ALT_STDERR "/dev/jtag_uart_0" -#define ALT_STDERR_BASE 0x20010b0 -#define ALT_STDERR_DEV jtag_uart_0 -#define ALT_STDERR_IS_JTAG_UART -#define ALT_STDERR_PRESENT -#define ALT_STDERR_TYPE "altera_avalon_jtag_uart" -#define ALT_STDIN "/dev/jtag_uart_0" -#define ALT_STDIN_BASE 0x20010b0 -#define ALT_STDIN_DEV jtag_uart_0 -#define ALT_STDIN_IS_JTAG_UART -#define ALT_STDIN_PRESENT -#define ALT_STDIN_TYPE "altera_avalon_jtag_uart" -#define ALT_STDOUT "/dev/jtag_uart_0" -#define ALT_STDOUT_BASE 0x20010b0 -#define ALT_STDOUT_DEV jtag_uart_0 -#define ALT_STDOUT_IS_JTAG_UART -#define ALT_STDOUT_PRESENT -#define ALT_STDOUT_TYPE "altera_avalon_jtag_uart" -#define ALT_SYSTEM_NAME "system" - - -/* - * hal configuration - * - */ - -#define ALT_MAX_FD 32 -#define ALT_SYS_CLK SYS_CLK_TIMER -#define ALT_TIMESTAMP_CLK none - - -/* - * jtag_uart_0 configuration - * - */ - -#define ALT_MODULE_CLASS_jtag_uart_0 altera_avalon_jtag_uart -#define JTAG_UART_0_BASE 0x20010b0 -#define JTAG_UART_0_IRQ 14 -#define JTAG_UART_0_IRQ_INTERRUPT_CONTROLLER_ID 0 -#define JTAG_UART_0_NAME "/dev/jtag_uart_0" -#define JTAG_UART_0_READ_DEPTH 64 -#define JTAG_UART_0_READ_THRESHOLD 8 -#define JTAG_UART_0_SPAN 8 -#define JTAG_UART_0_TYPE "altera_avalon_jtag_uart" -#define JTAG_UART_0_WRITE_DEPTH 64 -#define JTAG_UART_0_WRITE_THRESHOLD 8 - - -/* - * pio_ir_emitter configuration - * - */ - -#define ALT_MODULE_CLASS_pio_ir_emitter altera_avalon_pio -#define PIO_IR_EMITTER_BASE 0x2001080 -#define PIO_IR_EMITTER_BIT_CLEARING_EDGE_REGISTER 0 -#define PIO_IR_EMITTER_BIT_MODIFYING_OUTPUT_REGISTER 0 -#define PIO_IR_EMITTER_CAPTURE 0 -#define PIO_IR_EMITTER_DATA_WIDTH 1 -#define PIO_IR_EMITTER_DO_TEST_BENCH_WIRING 0 -#define PIO_IR_EMITTER_DRIVEN_SIM_VALUE 0x0 -#define PIO_IR_EMITTER_EDGE_TYPE "NONE" -#define PIO_IR_EMITTER_FREQ 100000000u -#define PIO_IR_EMITTER_HAS_IN 0 -#define PIO_IR_EMITTER_HAS_OUT 1 -#define PIO_IR_EMITTER_HAS_TRI 0 -#define PIO_IR_EMITTER_IRQ -1 -#define PIO_IR_EMITTER_IRQ_INTERRUPT_CONTROLLER_ID -1 -#define PIO_IR_EMITTER_IRQ_TYPE "NONE" -#define PIO_IR_EMITTER_NAME "/dev/pio_ir_emitter" -#define PIO_IR_EMITTER_RESET_VALUE 0x0 -#define PIO_IR_EMITTER_SPAN 16 -#define PIO_IR_EMITTER_TYPE "altera_avalon_pio" - - -/* - * pio_key_left configuration - * - */ - -#define ALT_MODULE_CLASS_pio_key_left altera_avalon_pio -#define PIO_KEY_LEFT_BASE 0x20010a0 -#define PIO_KEY_LEFT_BIT_CLEARING_EDGE_REGISTER 1 -#define PIO_KEY_LEFT_BIT_MODIFYING_OUTPUT_REGISTER 0 -#define PIO_KEY_LEFT_CAPTURE 1 -#define PIO_KEY_LEFT_DATA_WIDTH 1 -#define PIO_KEY_LEFT_DO_TEST_BENCH_WIRING 0 -#define PIO_KEY_LEFT_DRIVEN_SIM_VALUE 0x0 -#define PIO_KEY_LEFT_EDGE_TYPE "ANY" -#define PIO_KEY_LEFT_FREQ 100000000u -#define PIO_KEY_LEFT_HAS_IN 1 -#define PIO_KEY_LEFT_HAS_OUT 0 -#define PIO_KEY_LEFT_HAS_TRI 0 -#define PIO_KEY_LEFT_IRQ 1 -#define PIO_KEY_LEFT_IRQ_INTERRUPT_CONTROLLER_ID 0 -#define PIO_KEY_LEFT_IRQ_TYPE "EDGE" -#define PIO_KEY_LEFT_NAME "/dev/pio_key_left" -#define PIO_KEY_LEFT_RESET_VALUE 0x0 -#define PIO_KEY_LEFT_SPAN 16 -#define PIO_KEY_LEFT_TYPE "altera_avalon_pio" - - -/* - * pio_led configuration - * - */ - -#define ALT_MODULE_CLASS_pio_led altera_avalon_pio -#define PIO_LED_BASE 0x2001020 -#define PIO_LED_BIT_CLEARING_EDGE_REGISTER 0 -#define PIO_LED_BIT_MODIFYING_OUTPUT_REGISTER 1 -#define PIO_LED_CAPTURE 0 -#define PIO_LED_DATA_WIDTH 7 -#define PIO_LED_DO_TEST_BENCH_WIRING 0 -#define PIO_LED_DRIVEN_SIM_VALUE 0x0 -#define PIO_LED_EDGE_TYPE "NONE" -#define PIO_LED_FREQ 100000000u -#define PIO_LED_HAS_IN 0 -#define PIO_LED_HAS_OUT 1 -#define PIO_LED_HAS_TRI 0 -#define PIO_LED_IRQ -1 -#define PIO_LED_IRQ_INTERRUPT_CONTROLLER_ID -1 -#define PIO_LED_IRQ_TYPE "NONE" -#define PIO_LED_NAME "/dev/pio_led" -#define PIO_LED_RESET_VALUE 0x0 -#define PIO_LED_SPAN 32 -#define PIO_LED_TYPE "altera_avalon_pio" - - -/* - * pio_sw configuration - * - */ - -#define ALT_MODULE_CLASS_pio_sw altera_avalon_pio -#define PIO_SW_BASE 0x2001090 -#define PIO_SW_BIT_CLEARING_EDGE_REGISTER 0 -#define PIO_SW_BIT_MODIFYING_OUTPUT_REGISTER 0 -#define PIO_SW_CAPTURE 0 -#define PIO_SW_DATA_WIDTH 4 -#define PIO_SW_DO_TEST_BENCH_WIRING 0 -#define PIO_SW_DRIVEN_SIM_VALUE 0x0 -#define PIO_SW_EDGE_TYPE "NONE" -#define PIO_SW_FREQ 100000000u -#define PIO_SW_HAS_IN 1 -#define PIO_SW_HAS_OUT 0 -#define PIO_SW_HAS_TRI 0 -#define PIO_SW_IRQ -1 -#define PIO_SW_IRQ_INTERRUPT_CONTROLLER_ID -1 -#define PIO_SW_IRQ_TYPE "NONE" -#define PIO_SW_NAME "/dev/pio_sw" -#define PIO_SW_RESET_VALUE 0x0 -#define PIO_SW_SPAN 16 -#define PIO_SW_TYPE "altera_avalon_pio" - - -/* - * sdram configuration - * - */ - -#define ALT_MODULE_CLASS_sdram altera_avalon_new_sdram_controller -#define SDRAM_BASE 0x1000000 -#define SDRAM_CAS_LATENCY 3 -#define SDRAM_CONTENTS_INFO "" -#define SDRAM_INIT_NOP_DELAY 0.0 -#define SDRAM_INIT_REFRESH_COMMANDS 8 -#define SDRAM_IRQ -1 -#define SDRAM_IRQ_INTERRUPT_CONTROLLER_ID -1 -#define SDRAM_IS_INITIALIZED 1 -#define SDRAM_NAME "/dev/sdram" -#define SDRAM_POWERUP_DELAY 200.0 -#define SDRAM_REFRESH_PERIOD 7.8125 -#define SDRAM_REGISTER_DATA_IN 1 -#define SDRAM_SDRAM_ADDR_WIDTH 0x17 -#define SDRAM_SDRAM_BANK_WIDTH 2 -#define SDRAM_SDRAM_COL_WIDTH 8 -#define SDRAM_SDRAM_DATA_WIDTH 16 -#define SDRAM_SDRAM_NUM_BANKS 4 -#define SDRAM_SDRAM_NUM_CHIPSELECTS 1 -#define SDRAM_SDRAM_ROW_WIDTH 13 -#define SDRAM_SHARED_DATA 0 -#define SDRAM_SIM_MODEL_BASE 0 -#define SDRAM_SPAN 16777216 -#define SDRAM_STARVATION_INDICATOR 0 -#define SDRAM_TRISTATE_BRIDGE_SLAVE "" -#define SDRAM_TYPE "altera_avalon_new_sdram_controller" -#define SDRAM_T_AC 5.5 -#define SDRAM_T_MRD 3 -#define SDRAM_T_RCD 20.0 -#define SDRAM_T_RFC 70.0 -#define SDRAM_T_RP 20.0 -#define SDRAM_T_WR 14.0 - - -/* - * sys_clk_timer configuration - * - */ - -#define ALT_MODULE_CLASS_sys_clk_timer altera_avalon_timer -#define SYS_CLK_TIMER_ALWAYS_RUN 0 -#define SYS_CLK_TIMER_BASE 0x2001060 -#define SYS_CLK_TIMER_COUNTER_SIZE 32 -#define SYS_CLK_TIMER_FIXED_PERIOD 0 -#define SYS_CLK_TIMER_FREQ 100000000u -#define SYS_CLK_TIMER_IRQ 0 -#define SYS_CLK_TIMER_IRQ_INTERRUPT_CONTROLLER_ID 0 -#define SYS_CLK_TIMER_LOAD_VALUE 99999ull -#define SYS_CLK_TIMER_MULT 0.0010 -#define SYS_CLK_TIMER_NAME "/dev/sys_clk_timer" -#define SYS_CLK_TIMER_PERIOD 1 -#define SYS_CLK_TIMER_PERIOD_UNITS "ms" -#define SYS_CLK_TIMER_RESET_OUTPUT 0 -#define SYS_CLK_TIMER_SNAPSHOT 1 -#define SYS_CLK_TIMER_SPAN 32 -#define SYS_CLK_TIMER_TICKS_PER_SEC 1000u -#define SYS_CLK_TIMER_TIMEOUT_PULSE_OUTPUT 0 -#define SYS_CLK_TIMER_TYPE "altera_avalon_timer" - - -/* - * sysid configuration - * - */ - -#define ALT_MODULE_CLASS_sysid altera_avalon_sysid_qsys -#define SYSID_BASE 0x20010b8 -#define SYSID_ID 0 -#define SYSID_IRQ -1 -#define SYSID_IRQ_INTERRUPT_CONTROLLER_ID -1 -#define SYSID_NAME "/dev/sysid" -#define SYSID_SPAN 8 -#define SYSID_TIMESTAMP 1393717012 -#define SYSID_TYPE "altera_avalon_sysid_qsys" - - -/* - * uart_mc configuration - * - */ - -#define ALT_MODULE_CLASS_uart_mc altera_avalon_uart -#define UART_MC_BASE 0x2001000 -#define UART_MC_BAUD 9600 -#define UART_MC_DATA_BITS 8 -#define UART_MC_FIXED_BAUD 1 -#define UART_MC_FREQ 100000000u -#define UART_MC_IRQ 5 -#define UART_MC_IRQ_INTERRUPT_CONTROLLER_ID 0 -#define UART_MC_NAME "/dev/uart_mc" -#define UART_MC_PARITY 'N' -#define UART_MC_SIM_CHAR_STREAM "" -#define UART_MC_SIM_TRUE_BAUD 0 -#define UART_MC_SPAN 32 -#define UART_MC_STOP_BITS 1 -#define UART_MC_SYNC_REG_DEPTH 2 -#define UART_MC_TYPE "altera_avalon_uart" -#define UART_MC_USE_CTS_RTS 0 -#define UART_MC_USE_EOP_REGISTER 0 - - -/* - * uart_wifi configuration - * - */ - -#define ALT_MODULE_CLASS_uart_wifi altera_avalon_uart -#define UART_WIFI_BASE 0x2001040 -#define UART_WIFI_BAUD 9600 -#define UART_WIFI_DATA_BITS 8 -#define UART_WIFI_FIXED_BAUD 0 -#define UART_WIFI_FREQ 100000000u -#define UART_WIFI_IRQ 4 -#define UART_WIFI_IRQ_INTERRUPT_CONTROLLER_ID 0 -#define UART_WIFI_NAME "/dev/uart_wifi" -#define UART_WIFI_PARITY 'N' -#define UART_WIFI_SIM_CHAR_STREAM "" -#define UART_WIFI_SIM_TRUE_BAUD 0 -#define UART_WIFI_SPAN 32 -#define UART_WIFI_STOP_BITS 1 -#define UART_WIFI_SYNC_REG_DEPTH 2 -#define UART_WIFI_TYPE "altera_avalon_uart" -#define UART_WIFI_USE_CTS_RTS 0 -#define UART_WIFI_USE_EOP_REGISTER 0 - - -/* - * ucosii configuration - * - */ - -#define OS_ARG_CHK_EN 1 -#define OS_CPU_HOOKS_EN 1 -#define OS_DEBUG_EN 1 -#define OS_EVENT_NAME_SIZE 32 -#define OS_FLAGS_NBITS 16 -#define OS_FLAG_ACCEPT_EN 1 -#define OS_FLAG_DEL_EN 1 -#define OS_FLAG_EN 1 -#define OS_FLAG_NAME_SIZE 32 -#define OS_FLAG_QUERY_EN 1 -#define OS_FLAG_WAIT_CLR_EN 1 -#define OS_LOWEST_PRIO 20 -#define OS_MAX_EVENTS 60 -#define OS_MAX_FLAGS 20 -#define OS_MAX_MEM_PART 60 -#define OS_MAX_QS 20 -#define OS_MAX_TASKS 10 -#define OS_MBOX_ACCEPT_EN 1 -#define OS_MBOX_DEL_EN 1 -#define OS_MBOX_EN 1 -#define OS_MBOX_POST_EN 1 -#define OS_MBOX_POST_OPT_EN 1 -#define OS_MBOX_QUERY_EN 1 -#define OS_MEM_EN 1 -#define OS_MEM_NAME_SIZE 32 -#define OS_MEM_QUERY_EN 1 -#define OS_MUTEX_ACCEPT_EN 1 -#define OS_MUTEX_DEL_EN 1 -#define OS_MUTEX_EN 1 -#define OS_MUTEX_QUERY_EN 1 -#define OS_Q_ACCEPT_EN 1 -#define OS_Q_DEL_EN 1 -#define OS_Q_EN 1 -#define OS_Q_FLUSH_EN 1 -#define OS_Q_POST_EN 1 -#define OS_Q_POST_FRONT_EN 1 -#define OS_Q_POST_OPT_EN 1 -#define OS_Q_QUERY_EN 1 -#define OS_SCHED_LOCK_EN 1 -#define OS_SEM_ACCEPT_EN 1 -#define OS_SEM_DEL_EN 1 -#define OS_SEM_EN 1 -#define OS_SEM_QUERY_EN 1 -#define OS_SEM_SET_EN 1 -#define OS_TASK_CHANGE_PRIO_EN 1 -#define OS_TASK_CREATE_EN 1 -#define OS_TASK_CREATE_EXT_EN 1 -#define OS_TASK_DEL_EN 1 -#define OS_TASK_IDLE_STK_SIZE 512 -#define OS_TASK_NAME_SIZE 32 -#define OS_TASK_PROFILE_EN 1 -#define OS_TASK_QUERY_EN 1 -#define OS_TASK_STAT_EN 1 -#define OS_TASK_STAT_STK_CHK_EN 1 -#define OS_TASK_STAT_STK_SIZE 512 -#define OS_TASK_SUSPEND_EN 1 -#define OS_TASK_SW_HOOK_EN 1 -#define OS_TASK_TMR_PRIO 0 -#define OS_TASK_TMR_STK_SIZE 512 -#define OS_THREAD_SAFE_NEWLIB 1 -#define OS_TICKS_PER_SEC SYS_CLK_TIMER_TICKS_PER_SEC -#define OS_TICK_STEP_EN 1 -#define OS_TIME_DLY_HMSM_EN 1 -#define OS_TIME_DLY_RESUME_EN 1 -#define OS_TIME_GET_SET_EN 1 -#define OS_TIME_TICK_HOOK_EN 1 -#define OS_TMR_CFG_MAX 16 -#define OS_TMR_CFG_NAME_SIZE 16 -#define OS_TMR_CFG_TICKS_PER_SEC 10 -#define OS_TMR_CFG_WHEEL_SIZE 2 -#define OS_TMR_EN 0 - -#endif /* __SYSTEM_H_ */ diff --git a/MCandWifiTestDE0/Software/.metadata/.log b/MCandWifiTestDE0/Software/.metadata/.log index 84bc4164..165e4743 100644 --- a/MCandWifiTestDE0/Software/.metadata/.log +++ b/MCandWifiTestDE0/Software/.metadata/.log @@ -1,4 +1,4 @@ -!SESSION 2014-03-02 19:03:11.114 ----------------------------------------------- +!SESSION 2014-03-03 15:50:57.447 ----------------------------------------------- eclipse.buildId=M20120208-0800 java.version=1.6.0_23 java.vendor=Sun Microsystems Inc. @@ -6,8 +6,85 @@ BootLoader constants: OS=win32, ARCH=x86, WS=win32, NL=en_CA Framework arguments: -product org.eclipse.epp.package.cpp.product -perspective com.altera.sbtgui.ui.cPerspective Command-line arguments: -os win32 -ws win32 -arch x86 -product org.eclipse.epp.package.cpp.product -perspective com.altera.sbtgui.ui.cPerspective -!ENTRY org.eclipse.cdt.core 1 0 2014-03-02 19:03:52.454 -!MESSAGE Indexed 'MCandWifiTestDE0_bsp' (99 sources, 116 headers) in 1.25 sec: 3,609 declarations; 11,652 references; 100 unresolved inclusions; 4 syntax errors; 194 unresolved names (1.26%) +!ENTRY org.eclipse.cdt.core 1 0 2014-03-03 15:52:40.626 +!MESSAGE Indexed 'MCTest_bsp' (99 sources, 113 headers) in 1.18 sec: 3,369 declarations; 11,599 references; 123 unresolved inclusions; 57 syntax errors; 222 unresolved names (1.46%) -!ENTRY org.eclipse.cdt.core 1 0 2014-03-02 19:03:53.174 -!MESSAGE Indexed 'MCandWifiTestDE0' (1 sources, 13 headers) in 0.01 sec: 8 declarations; 23 references; 15 unresolved inclusions; 0 syntax errors; 6 unresolved names (16.22%) +!ENTRY org.eclipse.cdt.core 1 0 2014-03-03 15:52:41.464 +!MESSAGE Indexed 'MCTest' (1 sources, 13 headers) in 0.02 sec: 8 declarations; 23 references; 15 unresolved inclusions; 0 syntax errors; 6 unresolved names (16.22%) + +!ENTRY com.altera.sbtgui.launch 4 0 2014-03-03 16:05:25.261 +!MESSAGE Unable to validate connection settings. +!STACK 0 +java.lang.Exception: System ID mismatch - connected: "0xf0f0f0f0", expected: "0x0". + at com.altera.embeddedsw.flash.model.internal.SystemConsoleConnectionModel.assertTrue(SystemConsoleConnectionModel.java:645) + at com.altera.embeddedsw.flash.model.internal.SystemConsoleConnectionModel.validateSystemId(SystemConsoleConnectionModel.java:607) + at com.altera.embeddedsw.flash.model.internal.SystemConsoleConnectionModel.validateConnectionSettings(SystemConsoleConnectionModel.java:511) + at com.altera.sbtgui.launch.hardware.AbstractNios2CLaunchDelegate.launch(AbstractNios2CLaunchDelegate.java:115) + at com.altera.sbtgui.launch.hardware.Nios2HardwareLaunchDelegate.launch(Nios2HardwareLaunchDelegate.java:98) + at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:854) + at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:703) + at org.eclipse.debug.internal.ui.DebugUIPlugin.buildAndLaunch(DebugUIPlugin.java:937) + at org.eclipse.debug.internal.ui.DebugUIPlugin$8.run(DebugUIPlugin.java:1141) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54) + +!ENTRY com.altera.sbtgui.launch 4 0 2014-03-03 16:05:25.265 +!MESSAGE Unable to validate connection settings. +!STACK 0 +java.lang.Exception: System ID mismatch - connected: "0xf0f0f0f0", expected: "0x0". + at com.altera.embeddedsw.flash.model.internal.SystemConsoleConnectionModel.assertTrue(SystemConsoleConnectionModel.java:645) + at com.altera.embeddedsw.flash.model.internal.SystemConsoleConnectionModel.validateSystemId(SystemConsoleConnectionModel.java:607) + at com.altera.embeddedsw.flash.model.internal.SystemConsoleConnectionModel.validateConnectionSettings(SystemConsoleConnectionModel.java:511) + at com.altera.sbtgui.launch.hardware.AbstractNios2CLaunchDelegate.launch(AbstractNios2CLaunchDelegate.java:115) + at com.altera.sbtgui.launch.hardware.Nios2HardwareLaunchDelegate.launch(Nios2HardwareLaunchDelegate.java:98) + at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:854) + at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:703) + at org.eclipse.debug.internal.ui.DebugUIPlugin.buildAndLaunch(DebugUIPlugin.java:937) + at org.eclipse.debug.internal.ui.DebugUIPlugin$8.run(DebugUIPlugin.java:1141) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54) +!SESSION 2014-03-03 16:25:06.654 ----------------------------------------------- +eclipse.buildId=M20120208-0800 +java.version=1.6.0_23 +java.vendor=Sun Microsystems Inc. +BootLoader constants: OS=win32, ARCH=x86, WS=win32, NL=en_CA +Framework arguments: -product org.eclipse.epp.package.cpp.product -perspective com.altera.sbtgui.ui.cPerspective +Command-line arguments: -os win32 -ws win32 -arch x86 -product org.eclipse.epp.package.cpp.product -perspective com.altera.sbtgui.ui.cPerspective + +!ENTRY org.eclipse.ui 4 4 2014-03-03 16:25:11.711 +!MESSAGE Could not create view: 'org.eclipse.ui.internal.introview'. + +!ENTRY org.eclipse.ui 4 0 2014-03-03 16:25:13.387 +!MESSAGE Problems occurred restoring workbench. +!SUBENTRY 1 unknown 0 0 2014-03-03 16:25:13.387 +!MESSAGE OK +!SUBENTRY 1 unknown 0 0 2014-03-03 16:25:13.387 +!MESSAGE OK +!SUBENTRY 1 unknown 0 0 2014-03-03 16:25:13.387 +!MESSAGE OK +!SUBENTRY 1 unknown 0 0 2014-03-03 16:25:13.387 +!MESSAGE OK +!SUBENTRY 1 org.eclipse.ui 4 0 2014-03-03 16:25:13.387 +!MESSAGE Unable to restore perspective: Workspace - Nios II. +!SUBENTRY 2 org.eclipse.ui 0 0 2014-03-03 16:25:13.387 +!MESSAGE Problems occurred restoring perspective. +!SUBENTRY 3 org.eclipse.ui 0 0 2014-03-03 16:25:13.387 +!MESSAGE +!SUBENTRY 2 unknown 0 0 2014-03-03 16:25:13.387 +!MESSAGE OK +!SUBENTRY 2 unknown 0 0 2014-03-03 16:25:13.387 +!MESSAGE OK +!SUBENTRY 2 unknown 0 0 2014-03-03 16:25:13.387 +!MESSAGE OK +!SUBENTRY 2 unknown 0 0 2014-03-03 16:25:13.387 +!MESSAGE OK +!SUBENTRY 2 unknown 0 0 2014-03-03 16:25:13.387 +!MESSAGE OK +!SUBENTRY 2 unknown 0 0 2014-03-03 16:25:13.387 +!MESSAGE OK +!SUBENTRY 2 unknown 0 0 2014-03-03 16:25:13.387 +!MESSAGE OK +!SUBENTRY 2 unknown 0 0 2014-03-03 16:25:13.387 +!MESSAGE OK +!SUBENTRY 2 org.eclipse.ui 4 0 2014-03-03 16:25:13.387 +!MESSAGE Could not find view: org.eclipse.ui.internal.introview +!SUBENTRY 1 unknown 0 0 2014-03-03 16:25:13.387 +!MESSAGE OK diff --git a/MCandWifiTestDE0/Software/.metadata/.mylyn/repositories.xml.zip b/MCandWifiTestDE0/Software/.metadata/.mylyn/repositories.xml.zip index 0a18e5ca..1c53ef28 100644 Binary files a/MCandWifiTestDE0/Software/.metadata/.mylyn/repositories.xml.zip and b/MCandWifiTestDE0/Software/.metadata/.mylyn/repositories.xml.zip differ diff --git a/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.cdt.core/.log b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.cdt.core/.log index e8f62b88..d849569a 100644 --- a/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.cdt.core/.log +++ b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.cdt.core/.log @@ -1 +1,2 @@ -*** SESSION Mar 02, 2014 19:03:14.77 ------------------------------------------- +*** SESSION Mar 03, 2014 15:51:15.44 ------------------------------------------- +*** SESSION Mar 03, 2014 16:25:10.66 ------------------------------------------- diff --git a/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.cdt.core/MCTest.1393887161441.pdom b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.cdt.core/MCTest.1393887161441.pdom new file mode 100644 index 00000000..f892b8d0 Binary files /dev/null and b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.cdt.core/MCTest.1393887161441.pdom differ diff --git a/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.cdt.core/MCTest_bsp.1393887159289.pdom b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.cdt.core/MCTest_bsp.1393887159289.pdom new file mode 100644 index 00000000..8d808f71 Binary files /dev/null and b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.cdt.core/MCTest_bsp.1393887159289.pdom differ diff --git a/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.cdt.core/MCandWifiTestDE0.1393812233164.pdom b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.cdt.core/MCandWifiTestDE0.1393812233164.pdom deleted file mode 100644 index e911dee3..00000000 Binary files a/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.cdt.core/MCandWifiTestDE0.1393812233164.pdom and /dev/null differ diff --git a/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.cdt.core/MCandWifiTestDE0_bsp.1393812231054.pdom b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.cdt.core/MCandWifiTestDE0_bsp.1393812231054.pdom deleted file mode 100644 index 1c99c442..00000000 Binary files a/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.cdt.core/MCandWifiTestDE0_bsp.1393812231054.pdom and /dev/null differ diff --git a/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.cdt.make.core/MCTest.sc b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.cdt.make.core/MCTest.sc new file mode 100644 index 00000000..c263df74 --- /dev/null +++ b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.cdt.make.core/MCTest.sc @@ -0,0 +1,453 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.cdt.make.core/MCTest_bsp.sc new file mode 100644 index 00000000..821577c4 --- /dev/null +++ b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.cdt.make.core/MCTest_bsp.sc @@ -0,0 +1,437 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.cdt.make.core/MCandWifiTestDE0_bsp.sc b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.cdt.make.core/MCandWifiTestDE0_bsp.sc deleted file mode 100644 index 76c7d892..00000000 --- a/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.cdt.make.core/MCandWifiTestDE0_bsp.sc +++ /dev/null @@ -1,437 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.cdt.ui/MCTest.build.log b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.cdt.ui/MCTest.build.log new file mode 100644 index 00000000..626a824e --- /dev/null +++ b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.cdt.ui/MCTest.build.log @@ -0,0 +1,10 @@ + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** diff --git a/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.cdt.ui/MCTest_bsp.build.log b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.cdt.ui/MCTest_bsp.build.log new file mode 100644 index 00000000..0afb54d1 --- /dev/null +++ b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.cdt.ui/MCTest_bsp.build.log @@ -0,0 +1,7 @@ + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** diff --git a/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.cdt.ui/MCandWifiTestDE0.build.log b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.cdt.ui/MCandWifiTestDE0.build.log deleted file mode 100644 index 62d6e08e..00000000 --- a/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.cdt.ui/MCandWifiTestDE0.build.log +++ /dev/null @@ -1,10 +0,0 @@ - -**** Build of configuration Nios II for project MCandWifiTestDE0 **** - -make all -Info: Building ../MCandWifiTestDE0_bsp/ -make --no-print-directory -C ../MCandWifiTestDE0_bsp/ -[BSP build complete] -[MCandWifiTestDE0 build complete] - -**** Build Finished **** diff --git a/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.cdt.ui/MCandWifiTestDE0_bsp.build.log b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.cdt.ui/MCandWifiTestDE0_bsp.build.log deleted file mode 100644 index 38317b81..00000000 --- a/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.cdt.ui/MCandWifiTestDE0_bsp.build.log +++ /dev/null @@ -1,7 +0,0 @@ - -**** Build of configuration Nios II for project MCandWifiTestDE0_bsp **** - -make all -[BSP build complete] - -**** Build Finished **** diff --git a/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.cdt.ui/dialog_settings.xml b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.cdt.ui/dialog_settings.xml index 8e479579..06342cd2 100644 --- a/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.cdt.ui/dialog_settings.xml +++ b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.cdt.ui/dialog_settings.xml @@ -2,6 +2,16 @@
+
+ + + + + + + + +
diff --git a/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.cdt.ui/global-build.log b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.cdt.ui/global-build.log index 17d270c7..b83aa412 100644 --- a/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.cdt.ui/global-build.log +++ b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.cdt.ui/global-build.log @@ -1,23 +1,23 @@ -**** Clean-only build of configuration Nios II for project MCandWifiTestDE0_bsp **** +**** Clean-only build of configuration Nios II for project MCTest_bsp **** make clean [BSP clean complete] **** Build Finished **** -**** Clean-only build of configuration Nios II for project MCandWifiTestDE0 **** +**** Clean-only build of configuration Nios II for project MCTest **** make clean -[MCandWifiTestDE0 clean complete] +[MCTest clean complete] **** Build Finished **** -**** Build of configuration Nios II for project MCandWifiTestDE0 **** +**** Build of configuration Nios II for project MCTest **** make all -Info: Building ../MCandWifiTestDE0_bsp/ -make --no-print-directory -C ../MCandWifiTestDE0_bsp/ +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ Compiling alt_alarm_start.c... nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_alarm_start.o HAL/src/alt_alarm_start.c Compiling alt_busy_sleep.c... @@ -233,42 +233,1004 @@ nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -D Compiling altera_avalon_uart_write.c... nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_uart_write.o drivers/src/altera_avalon_uart_write.c drivers/src/altera_up_avalon_rs232.c: In function 'alt_up_rs232_read_fd': -drivers/src/altera_up_avalon_rs232.c:110: warning: pointer targets in passing argument 2 of 'alt_up_rs232_read_data' differ in signedness Compiling altera_up_avalon_rs232.c... +drivers/src/altera_up_avalon_rs232.c:110: warning: pointer targets in passing argument 2 of 'alt_up_rs232_read_data' differ in signedness nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_up_avalon_rs232.o drivers/src/altera_up_avalon_rs232.c Creating libucosii_bsp.a... rm -f -f libucosii_bsp.a nios2-elf-ar -src libucosii_bsp.a obj/HAL/src/alt_alarm_start.o obj/HAL/src/alt_busy_sleep.o obj/HAL/src/alt_close.o obj/HAL/src/alt_dcache_flush.o obj/HAL/src/alt_dcache_flush_all.o obj/HAL/src/alt_dcache_flush_no_writeback.o obj/HAL/src/alt_dev.o obj/HAL/src/alt_dev_llist_insert.o obj/HAL/src/alt_dma_rxchan_open.o obj/HAL/src/alt_dma_txchan_open.o obj/HAL/src/alt_do_ctors.o obj/HAL/src/alt_do_dtors.o obj/HAL/src/alt_environ.o obj/HAL/src/alt_errno.o obj/HAL/src/alt_exception_entry.o obj/HAL/src/alt_exception_muldiv.o obj/HAL/src/alt_exception_trap.o obj/HAL/src/alt_execve.o obj/HAL/src/alt_exit.o obj/HAL/src/alt_fcntl.o obj/HAL/src/alt_fd_lock.o obj/HAL/src/alt_fd_unlock.o obj/HAL/src/alt_find_dev.o obj/HAL/src/alt_find_file.o obj/HAL/src/alt_flash_dev.o obj/HAL/src/alt_fork.o obj/HAL/src/alt_fs_reg.o obj/HAL/src/alt_fstat.o obj/HAL/src/alt_get_fd.o obj/HAL/src/alt_getchar.o obj/HAL/src/alt_getpid.o obj/HAL/src/alt_gettod.o obj/HAL/src/alt_gmon.o obj/HAL/src/alt_icache_flush.o obj/HAL/src/alt_icache_flush_all.o obj/HAL/src/alt_iic.o obj/HAL/src/alt_iic_isr_register.o obj/HAL/src/alt_instruction_exception_entry.o obj/HAL/src/alt_instruction_exception_register.o obj/HAL/src/alt_io_redirect.o obj/HAL/src/alt_ioctl.o obj/HAL/src/alt_irq_entry.o obj/HAL/src/alt_irq_handler.o obj/HAL/src/alt_irq_register.o obj/HAL/src/alt_irq_vars.o obj/HAL/src/alt_isatty.o obj/HAL/src/alt_kill.o obj/HAL/src/alt_link.o obj/HAL/src/alt_load.o obj/HAL/src/alt_log_macro.o obj/HAL/src/alt_log_printf.o obj/HAL/src/alt_lseek.o obj/HAL/src/alt_main.o obj/HAL/src/alt_mcount.o obj/HAL/src/alt_open.o obj/HAL/src/alt_printf.o obj/HAL/src/alt_putchar.o obj/HAL/src/alt_putstr.o obj/HAL/src/alt_read.o obj/HAL/src/alt_release_fd.o obj/HAL/src/alt_remap_cached.o obj/HAL/src/alt_remap_uncached.o obj/HAL/src/alt_rename.o obj/HAL/src/alt_sbrk.o obj/HAL/src/alt_settod.o obj/HAL/src/alt_software_exception.o obj/HAL/src/alt_stat.o obj/HAL/src/alt_tick.o obj/HAL/src/alt_times.o obj/HAL/src/alt_uncached_free.o obj/HAL/src/alt_uncached_malloc.o obj/HAL/src/alt_unlink.o obj/HAL/src/alt_usleep.o obj/HAL/src/alt_wait.o obj/HAL/src/alt_write.o obj/HAL/src/altera_nios2_qsys_irq.o obj/HAL/src/crt0.o obj/HAL/src/os_cpu_a.o obj/HAL/src/os_cpu_c.o obj/UCOSII/src/alt_env_lock.o obj/UCOSII/src/alt_malloc_lock.o obj/UCOSII/src/os_core.o obj/UCOSII/src/os_dbg.o obj/UCOSII/src/os_flag.o obj/UCOSII/src/os_mbox.o obj/UCOSII/src/os_mem.o obj/UCOSII/src/os_mutex.o obj/UCOSII/src/os_q.o obj/UCOSII/src/os_sem.o obj/UCOSII/src/os_task.o obj/UCOSII/src/os_time.o obj/UCOSII/src/os_tmr.o obj/alt_sys_init.o obj/drivers/src/altera_avalon_jtag_uart_fd.o obj/drivers/src/altera_avalon_jtag_uart_init.o obj/drivers/src/altera_avalon_jtag_uart_ioctl.o obj/drivers/src/altera_avalon_jtag_uart_read.o obj/drivers/src/altera_avalon_jtag_uart_write.o obj/drivers/src/altera_avalon_sysid_qsys.o obj/drivers/src/altera_avalon_timer_sc.o obj/drivers/src/altera_avalon_timer_ts.o obj/drivers/src/altera_avalon_timer_vars.o obj/drivers/src/altera_avalon_uart_fd.o obj/drivers/src/altera_avalon_uart_init.o obj/drivers/src/altera_avalon_uart_ioctl.o obj/drivers/src/altera_avalon_uart_read.o obj/drivers/src/altera_avalon_uart_write.o obj/drivers/src/altera_up_avalon_rs232.o [BSP build complete] Info: Compiling SerialHandler.cpp to obj/default/SerialHandler.o -nios2-elf-gcc -xc++ -MP -MMD -c -I../MCandWifiTestDE0_bsp//UCOSII/inc -I../MCandWifiTestDE0_bsp//HAL/inc -I../MCandWifiTestDE0_bsp/ -I../MCandWifiTestDE0_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/SerialHandler.o SerialHandler.cpp +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/SerialHandler.o SerialHandler.cpp Info: Compiling main.cpp to obj/default/main.o -nios2-elf-gcc -xc++ -MP -MMD -c -I../MCandWifiTestDE0_bsp//UCOSII/inc -I../MCandWifiTestDE0_bsp//HAL/inc -I../MCandWifiTestDE0_bsp/ -I../MCandWifiTestDE0_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/main.o main.cpp +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/main.o main.cpp main.cpp:61: warning: 'void isr_on_ir_pushbutton(void*)' defined but not used -Info: Linking MCandWifiTestDE0.elf -nios2-elf-g++ -T'../MCandWifiTestDE0_bsp//linker.x' -msys-crt0='../MCandWifiTestDE0_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCandWifiTestDE0_bsp/ -Wl,-Map=MCandWifiTestDE0.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCandWifiTestDE0.elf obj/default/SerialHandler.o obj/default/main.o -lm -nios2-elf-insert MCandWifiTestDE0.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010c0 --timestamp 1393806947 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0" --jdi C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.jdi --sopcinfo C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system.sopcinfo -Info: (MCandWifiTestDE0.elf) 148 KBytes program size (code + initialized data). -Info: 16228 KBytes free for stack + heap. -Info: Creating MCandWifiTestDE0.objdump -nios2-elf-objdump --disassemble --syms --all-header --source MCandWifiTestDE0.elf >MCandWifiTestDE0.objdump -[MCandWifiTestDE0 build complete] +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/SerialHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010c0 --timestamp 1393886764 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0" --jdi C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.jdi --sopcinfo C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system.sopcinfo +Info: (MCTest.elf) 148 KBytes program size (code + initialized data). +Info: 16228 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Clean-only build of configuration Nios II for project MCTest **** + +make clean +[MCTest clean complete] + +**** Build Finished **** + +**** Clean-only build of configuration Nios II for project MCTest_bsp **** + +make clean +[BSP clean complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +Compiling alt_alarm_start.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_alarm_start.o HAL/src/alt_alarm_start.c +Compiling alt_busy_sleep.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_busy_sleep.o HAL/src/alt_busy_sleep.c +Compiling alt_close.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_close.o HAL/src/alt_close.c +Compiling alt_dcache_flush.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dcache_flush.o HAL/src/alt_dcache_flush.c +Compiling alt_dcache_flush_all.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dcache_flush_all.o HAL/src/alt_dcache_flush_all.c +Compiling alt_dcache_flush_no_writeback.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dcache_flush_no_writeback.o HAL/src/alt_dcache_flush_no_writeback.c +Compiling alt_dev.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dev.o HAL/src/alt_dev.c +Compiling alt_dev_llist_insert.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dev_llist_insert.o HAL/src/alt_dev_llist_insert.c +Compiling alt_dma_rxchan_open.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dma_rxchan_open.o HAL/src/alt_dma_rxchan_open.c +Compiling alt_dma_txchan_open.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dma_txchan_open.o HAL/src/alt_dma_txchan_open.c +Compiling alt_do_ctors.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_do_ctors.o HAL/src/alt_do_ctors.c +Compiling alt_do_dtors.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_do_dtors.o HAL/src/alt_do_dtors.c +Compiling alt_environ.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_environ.o HAL/src/alt_environ.c +Compiling alt_errno.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_errno.o HAL/src/alt_errno.c +Compiling alt_exception_entry.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_exception_entry.o HAL/src/alt_exception_entry.S +Compiling alt_exception_muldiv.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_exception_muldiv.o HAL/src/alt_exception_muldiv.S +Compiling alt_exception_trap.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_exception_trap.o HAL/src/alt_exception_trap.S +Compiling alt_execve.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_execve.o HAL/src/alt_execve.c +Compiling alt_exit.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_exit.o HAL/src/alt_exit.c +Compiling alt_fcntl.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fcntl.o HAL/src/alt_fcntl.c +Compiling alt_fd_lock.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fd_lock.o HAL/src/alt_fd_lock.c +Compiling alt_fd_unlock.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fd_unlock.o HAL/src/alt_fd_unlock.c +Compiling alt_find_dev.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_find_dev.o HAL/src/alt_find_dev.c +Compiling alt_find_file.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_find_file.o HAL/src/alt_find_file.c +Compiling alt_flash_dev.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_flash_dev.o HAL/src/alt_flash_dev.c +Compiling alt_fork.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fork.o HAL/src/alt_fork.c +Compiling alt_fs_reg.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fs_reg.o HAL/src/alt_fs_reg.c +Compiling alt_fstat.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fstat.o HAL/src/alt_fstat.c +Compiling alt_get_fd.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_get_fd.o HAL/src/alt_get_fd.c +Compiling alt_getchar.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_getchar.o HAL/src/alt_getchar.c +Compiling alt_getpid.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_getpid.o HAL/src/alt_getpid.c +Compiling alt_gettod.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_gettod.o HAL/src/alt_gettod.c +Compiling alt_gmon.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_gmon.o HAL/src/alt_gmon.c +Compiling alt_icache_flush.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_icache_flush.o HAL/src/alt_icache_flush.c +Compiling alt_icache_flush_all.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_icache_flush_all.o HAL/src/alt_icache_flush_all.c +Compiling alt_iic.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_iic.o HAL/src/alt_iic.c +Compiling alt_iic_isr_register.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_iic_isr_register.o HAL/src/alt_iic_isr_register.c +Compiling alt_instruction_exception_entry.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_instruction_exception_entry.o HAL/src/alt_instruction_exception_entry.c +Compiling alt_instruction_exception_register.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_instruction_exception_register.o HAL/src/alt_instruction_exception_register.c +Compiling alt_io_redirect.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_io_redirect.o HAL/src/alt_io_redirect.c +Compiling alt_ioctl.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_ioctl.o HAL/src/alt_ioctl.c +Compiling alt_irq_entry.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_irq_entry.o HAL/src/alt_irq_entry.S +Compiling alt_irq_handler.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_irq_handler.o HAL/src/alt_irq_handler.c +Compiling alt_irq_register.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_irq_register.o HAL/src/alt_irq_register.c +Compiling alt_irq_vars.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_irq_vars.o HAL/src/alt_irq_vars.c +Compiling alt_isatty.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_isatty.o HAL/src/alt_isatty.c +Compiling alt_kill.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_kill.o HAL/src/alt_kill.c +Compiling alt_link.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_link.o HAL/src/alt_link.c +Compiling alt_load.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_load.o HAL/src/alt_load.c +Compiling alt_log_macro.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_log_macro.o HAL/src/alt_log_macro.S +Compiling alt_log_printf.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_log_printf.o HAL/src/alt_log_printf.c +Compiling alt_lseek.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_lseek.o HAL/src/alt_lseek.c +Compiling alt_main.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_main.o HAL/src/alt_main.c +Compiling alt_mcount.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_mcount.o HAL/src/alt_mcount.S +Compiling alt_open.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_open.o HAL/src/alt_open.c +Compiling alt_printf.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_printf.o HAL/src/alt_printf.c +Compiling alt_putchar.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_putchar.o HAL/src/alt_putchar.c +Compiling alt_putstr.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_putstr.o HAL/src/alt_putstr.c +Compiling alt_read.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_read.o HAL/src/alt_read.c +Compiling alt_release_fd.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_release_fd.o HAL/src/alt_release_fd.c +Compiling alt_remap_cached.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_remap_cached.o HAL/src/alt_remap_cached.c +Compiling alt_remap_uncached.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_remap_uncached.o HAL/src/alt_remap_uncached.c +Compiling alt_rename.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_rename.o HAL/src/alt_rename.c +Compiling alt_sbrk.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_sbrk.o HAL/src/alt_sbrk.c +Compiling alt_settod.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_settod.o HAL/src/alt_settod.c +Compiling alt_software_exception.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_software_exception.o HAL/src/alt_software_exception.S +Compiling alt_stat.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_stat.o HAL/src/alt_stat.c +Compiling alt_tick.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_tick.o HAL/src/alt_tick.c +Compiling alt_times.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_times.o HAL/src/alt_times.c +Compiling alt_uncached_free.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_uncached_free.o HAL/src/alt_uncached_free.c +Compiling alt_uncached_malloc.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_uncached_malloc.o HAL/src/alt_uncached_malloc.c +Compiling alt_unlink.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_unlink.o HAL/src/alt_unlink.c +Compiling alt_usleep.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_usleep.o HAL/src/alt_usleep.c +Compiling alt_wait.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_wait.o HAL/src/alt_wait.c +Compiling alt_write.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_write.o HAL/src/alt_write.c +Compiling altera_nios2_qsys_irq.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/altera_nios2_qsys_irq.o HAL/src/altera_nios2_qsys_irq.c +Compiling crt0.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/crt0.o HAL/src/crt0.S +Compiling os_cpu_a.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/os_cpu_a.o HAL/src/os_cpu_a.S +Compiling os_cpu_c.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/os_cpu_c.o HAL/src/os_cpu_c.c +Compiling alt_env_lock.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/alt_env_lock.o UCOSII/src/alt_env_lock.c +Compiling alt_malloc_lock.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/alt_malloc_lock.o UCOSII/src/alt_malloc_lock.c +Compiling os_core.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_core.o UCOSII/src/os_core.c +Compiling os_dbg.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_dbg.o UCOSII/src/os_dbg.c +Compiling os_flag.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_flag.o UCOSII/src/os_flag.c +Compiling os_mbox.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_mbox.o UCOSII/src/os_mbox.c +Compiling os_mem.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_mem.o UCOSII/src/os_mem.c +Compiling os_mutex.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_mutex.o UCOSII/src/os_mutex.c +Compiling os_q.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_q.o UCOSII/src/os_q.c +Compiling os_sem.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_sem.o UCOSII/src/os_sem.c +Compiling os_task.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_task.o UCOSII/src/os_task.c +Compiling os_time.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_time.o UCOSII/src/os_time.c +Compiling os_tmr.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_tmr.o UCOSII/src/os_tmr.c +Compiling alt_sys_init.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/alt_sys_init.o alt_sys_init.c +Compiling altera_avalon_jtag_uart_fd.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_jtag_uart_fd.o drivers/src/altera_avalon_jtag_uart_fd.c +Compiling altera_avalon_jtag_uart_init.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_jtag_uart_init.o drivers/src/altera_avalon_jtag_uart_init.c +Compiling altera_avalon_jtag_uart_ioctl.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_jtag_uart_ioctl.o drivers/src/altera_avalon_jtag_uart_ioctl.c +Compiling altera_avalon_jtag_uart_read.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_jtag_uart_read.o drivers/src/altera_avalon_jtag_uart_read.c +Compiling altera_avalon_jtag_uart_write.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_jtag_uart_write.o drivers/src/altera_avalon_jtag_uart_write.c +Compiling altera_avalon_sysid_qsys.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_sysid_qsys.o drivers/src/altera_avalon_sysid_qsys.c +Compiling altera_avalon_timer_sc.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_timer_sc.o drivers/src/altera_avalon_timer_sc.c +Compiling altera_avalon_timer_ts.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_timer_ts.o drivers/src/altera_avalon_timer_ts.c +Compiling altera_avalon_timer_vars.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_timer_vars.o drivers/src/altera_avalon_timer_vars.c +Compiling altera_avalon_uart_fd.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_uart_fd.o drivers/src/altera_avalon_uart_fd.c +Compiling altera_avalon_uart_init.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_uart_init.o drivers/src/altera_avalon_uart_init.c +Compiling altera_avalon_uart_ioctl.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_uart_ioctl.o drivers/src/altera_avalon_uart_ioctl.c +Compiling altera_avalon_uart_read.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_uart_read.o drivers/src/altera_avalon_uart_read.c +Compiling altera_avalon_uart_write.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_uart_write.o drivers/src/altera_avalon_uart_write.c +drivers/src/altera_up_avalon_rs232.c: In function 'alt_up_rs232_read_fd': +Compiling altera_up_avalon_rs232.c... +drivers/src/altera_up_avalon_rs232.c:110: warning: pointer targets in passing argument 2 of 'alt_up_rs232_read_data' differ in signedness +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_up_avalon_rs232.o drivers/src/altera_up_avalon_rs232.c +Creating libucosii_bsp.a... +rm -f -f libucosii_bsp.a +nios2-elf-ar -src libucosii_bsp.a obj/HAL/src/alt_alarm_start.o obj/HAL/src/alt_busy_sleep.o obj/HAL/src/alt_close.o obj/HAL/src/alt_dcache_flush.o obj/HAL/src/alt_dcache_flush_all.o obj/HAL/src/alt_dcache_flush_no_writeback.o obj/HAL/src/alt_dev.o obj/HAL/src/alt_dev_llist_insert.o obj/HAL/src/alt_dma_rxchan_open.o obj/HAL/src/alt_dma_txchan_open.o obj/HAL/src/alt_do_ctors.o obj/HAL/src/alt_do_dtors.o obj/HAL/src/alt_environ.o obj/HAL/src/alt_errno.o obj/HAL/src/alt_exception_entry.o obj/HAL/src/alt_exception_muldiv.o obj/HAL/src/alt_exception_trap.o obj/HAL/src/alt_execve.o obj/HAL/src/alt_exit.o obj/HAL/src/alt_fcntl.o obj/HAL/src/alt_fd_lock.o obj/HAL/src/alt_fd_unlock.o obj/HAL/src/alt_find_dev.o obj/HAL/src/alt_find_file.o obj/HAL/src/alt_flash_dev.o obj/HAL/src/alt_fork.o obj/HAL/src/alt_fs_reg.o obj/HAL/src/alt_fstat.o obj/HAL/src/alt_get_fd.o obj/HAL/src/alt_getchar.o obj/HAL/src/alt_getpid.o obj/HAL/src/alt_gettod.o obj/HAL/src/alt_gmon.o obj/HAL/src/alt_icache_flush.o obj/HAL/src/alt_icache_flush_all.o obj/HAL/src/alt_iic.o obj/HAL/src/alt_iic_isr_register.o obj/HAL/src/alt_instruction_exception_entry.o obj/HAL/src/alt_instruction_exception_register.o obj/HAL/src/alt_io_redirect.o obj/HAL/src/alt_ioctl.o obj/HAL/src/alt_irq_entry.o obj/HAL/src/alt_irq_handler.o obj/HAL/src/alt_irq_register.o obj/HAL/src/alt_irq_vars.o obj/HAL/src/alt_isatty.o obj/HAL/src/alt_kill.o obj/HAL/src/alt_link.o obj/HAL/src/alt_load.o obj/HAL/src/alt_log_macro.o obj/HAL/src/alt_log_printf.o obj/HAL/src/alt_lseek.o obj/HAL/src/alt_main.o obj/HAL/src/alt_mcount.o obj/HAL/src/alt_open.o obj/HAL/src/alt_printf.o obj/HAL/src/alt_putchar.o obj/HAL/src/alt_putstr.o obj/HAL/src/alt_read.o obj/HAL/src/alt_release_fd.o obj/HAL/src/alt_remap_cached.o obj/HAL/src/alt_remap_uncached.o obj/HAL/src/alt_rename.o obj/HAL/src/alt_sbrk.o obj/HAL/src/alt_settod.o obj/HAL/src/alt_software_exception.o obj/HAL/src/alt_stat.o obj/HAL/src/alt_tick.o obj/HAL/src/alt_times.o obj/HAL/src/alt_uncached_free.o obj/HAL/src/alt_uncached_malloc.o obj/HAL/src/alt_unlink.o obj/HAL/src/alt_usleep.o obj/HAL/src/alt_wait.o obj/HAL/src/alt_write.o obj/HAL/src/altera_nios2_qsys_irq.o obj/HAL/src/crt0.o obj/HAL/src/os_cpu_a.o obj/HAL/src/os_cpu_c.o obj/UCOSII/src/alt_env_lock.o obj/UCOSII/src/alt_malloc_lock.o obj/UCOSII/src/os_core.o obj/UCOSII/src/os_dbg.o obj/UCOSII/src/os_flag.o obj/UCOSII/src/os_mbox.o obj/UCOSII/src/os_mem.o obj/UCOSII/src/os_mutex.o obj/UCOSII/src/os_q.o obj/UCOSII/src/os_sem.o obj/UCOSII/src/os_task.o obj/UCOSII/src/os_time.o obj/UCOSII/src/os_tmr.o obj/alt_sys_init.o obj/drivers/src/altera_avalon_jtag_uart_fd.o obj/drivers/src/altera_avalon_jtag_uart_init.o obj/drivers/src/altera_avalon_jtag_uart_ioctl.o obj/drivers/src/altera_avalon_jtag_uart_read.o obj/drivers/src/altera_avalon_jtag_uart_write.o obj/drivers/src/altera_avalon_sysid_qsys.o obj/drivers/src/altera_avalon_timer_sc.o obj/drivers/src/altera_avalon_timer_ts.o obj/drivers/src/altera_avalon_timer_vars.o obj/drivers/src/altera_avalon_uart_fd.o obj/drivers/src/altera_avalon_uart_init.o obj/drivers/src/altera_avalon_uart_ioctl.o obj/drivers/src/altera_avalon_uart_read.o obj/drivers/src/altera_avalon_uart_write.o obj/drivers/src/altera_up_avalon_rs232.o +[BSP build complete] +Info: Compiling SerialHandler.cpp to obj/default/SerialHandler.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/SerialHandler.o SerialHandler.cpp +Info: Compiling main.cpp to obj/default/main.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/main.o main.cpp +main.cpp: In function 'int main()': +main.cpp:252: error: 'alt_ic_isr_register' was not declared in this scope +make: *** [obj/default/main.o] Error 1 + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling main.cpp to obj/default/main.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/main.o main.cpp +main.cpp:51: warning: 'void isr_on_ir_pushbutton(void*)' defined but not used +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/SerialHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010c0 --timestamp 1393886764 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0" --jdi C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.jdi --sopcinfo C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system.sopcinfo +Info: (MCTest.elf) 148 KBytes program size (code + initialized data). +Info: 16228 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling MotorHandler.cpp to obj/default/MotorHandler.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/MotorHandler.o MotorHandler.cpp +MotorHandler.h:26: error: variable or field 'mc_backward' declared void +MotorHandler.cpp: In member function 'void MotorHandler::sendByteMC(char)': +MotorHandler.cpp:19: error: 'UART_MC_BASE' was not declared in this scope +MotorHandler.cpp:19: error: 'IOWR_ALTERA_AVALON_UART_TXDATA' was not declared in this scope +MotorHandler.cpp: At global scope: +MotorHandler.cpp:22: error: expected unqualified-id at end of input +make: *** [obj/default/MotorHandler.o] Error 1 + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling MotorHandler.cpp to obj/default/MotorHandler.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/MotorHandler.o MotorHandler.cpp +MotorHandler.cpp: In member function 'void MotorHandler::sendByteMC(char)': +MotorHandler.cpp:19: error: 'UART_MC_BASE' was not declared in this scope +MotorHandler.cpp:19: error: 'IOWR_ALTERA_AVALON_UART_TXDATA' was not declared in this scope +MotorHandler.cpp: At global scope: +MotorHandler.cpp:22: error: expected unqualified-id at end of input +make: *** [obj/default/MotorHandler.o] Error 1 + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling MotorHandler.cpp to obj/default/MotorHandler.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/MotorHandler.o MotorHandler.cpp +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/SerialHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010c0 --timestamp 1393886764 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0" --jdi C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.jdi --sopcinfo C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system.sopcinfo +Info: (MCTest.elf) 148 KBytes program size (code + initialized data). +Info: 16228 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling MotorHandler.cpp to obj/default/MotorHandler.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/MotorHandler.o MotorHandler.cpp +MotorHandler.cpp:40: error: expected constructor, destructor, or type conversion before '(' token +MotorHandler.cpp:41: error: expected constructor, destructor, or type conversion before '(' token +MotorHandler.cpp:42: error: expected constructor, destructor, or type conversion before '(' token +MotorHandler.cpp:43: error: expected constructor, destructor, or type conversion before '(' token +MotorHandler.cpp:45: error: expected constructor, destructor, or type conversion before '(' token +MotorHandler.cpp:46: error: expected constructor, destructor, or type conversion before '(' token +MotorHandler.cpp:47: error: expected constructor, destructor, or type conversion before '(' token +MotorHandler.cpp:48: error: expected constructor, destructor, or type conversion before '(' token +MotorHandler.cpp:49: error: expected declaration before '}' token +make: *** [obj/default/MotorHandler.o] Error 1 + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling MotorHandler.cpp to obj/default/MotorHandler.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/MotorHandler.o MotorHandler.cpp +MotorHandler.cpp:40: error: expected constructor, destructor, or type conversion before '(' token +MotorHandler.cpp:41: error: expected constructor, destructor, or type conversion before '(' token +MotorHandler.cpp:42: error: expected constructor, destructor, or type conversion before '(' token +MotorHandler.cpp:43: error: expected constructor, destructor, or type conversion before '(' token +MotorHandler.cpp:45: error: expected constructor, destructor, or type conversion before '(' token +MotorHandler.cpp:46: error: expected constructor, destructor, or type conversion before '(' token +MotorHandler.cpp:47: error: expected constructor, destructor, or type conversion before '(' token +MotorHandler.cpp:48: error: expected constructor, destructor, or type conversion before '(' token +MotorHandler.cpp:49: error: expected declaration before '}' token +make: *** [obj/default/MotorHandler.o] Error 1 + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling MotorHandler.cpp to obj/default/MotorHandler.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/MotorHandler.o MotorHandler.cpp +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/SerialHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010c0 --timestamp 1393886764 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0" --jdi C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.jdi --sopcinfo C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system.sopcinfo +Info: (MCTest.elf) 148 KBytes program size (code + initialized data). +Info: 16228 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling MotorHandler.cpp to obj/default/MotorHandler.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/MotorHandler.o MotorHandler.cpp +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/SerialHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010c0 --timestamp 1393886764 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0" --jdi C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.jdi --sopcinfo C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system.sopcinfo +Info: (MCTest.elf) 148 KBytes program size (code + initialized data). +Info: 16228 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling MotorHandler.cpp to obj/default/MotorHandler.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/MotorHandler.o MotorHandler.cpp +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/SerialHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010c0 --timestamp 1393886764 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0" --jdi C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.jdi --sopcinfo C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system.sopcinfo +Info: (MCTest.elf) 149 KBytes program size (code + initialized data). +Info: 16227 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling main.cpp to obj/default/main.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/main.o main.cpp +main.cpp: In function 'void mc_task(void*)': +main.cpp:119: error: 'mc_forward' was not declared in this scope +main.cpp: At global scope: +main.cpp:52: warning: 'void isr_on_ir_pushbutton(void*)' defined but not used +make: *** [obj/default/main.o] Error 1 + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling MotorHandler.cpp to obj/default/MotorHandler.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/MotorHandler.o MotorHandler.cpp +Info: Compiling main.cpp to obj/default/main.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/main.o main.cpp +main.cpp:52: warning: 'void isr_on_ir_pushbutton(void*)' defined but not used +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/SerialHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010c0 --timestamp 1393886764 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0" --jdi C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.jdi --sopcinfo C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system.sopcinfo +Info: (MCTest.elf) 147 KBytes program size (code + initialized data). +Info: 16229 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Compiling main.cpp to obj/default/main.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/main.o main.cpp +main.cpp:51: warning: 'void isr_on_ir_pushbutton(void*)' defined but not used +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/SerialHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010c0 --timestamp 1393886764 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0" --jdi C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.jdi --sopcinfo C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system.sopcinfo +Info: (MCTest.elf) 147 KBytes program size (code + initialized data). +Info: 16229 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010c0 --timestamp 1393886764 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0" --jdi C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.jdi --sopcinfo C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system.sopcinfo +Info: (MCTest.elf) 147 KBytes program size (code + initialized data). +Info: 16229 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +[BSP build complete] +[MCTest build complete] + +**** Build Finished **** + +**** Clean-only build of configuration Nios II for project MCTest **** + +make clean +[MCTest clean complete] + +**** Build Finished **** + +**** Clean-only build of configuration Nios II for project MCTest_bsp **** + +make clean +[BSP clean complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest **** + +make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ +Compiling alt_alarm_start.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_alarm_start.o HAL/src/alt_alarm_start.c +Compiling alt_busy_sleep.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_busy_sleep.o HAL/src/alt_busy_sleep.c +Compiling alt_close.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_close.o HAL/src/alt_close.c +Compiling alt_dcache_flush.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dcache_flush.o HAL/src/alt_dcache_flush.c +Compiling alt_dcache_flush_all.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dcache_flush_all.o HAL/src/alt_dcache_flush_all.c +Compiling alt_dcache_flush_no_writeback.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dcache_flush_no_writeback.o HAL/src/alt_dcache_flush_no_writeback.c +Compiling alt_dev.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dev.o HAL/src/alt_dev.c +Compiling alt_dev_llist_insert.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dev_llist_insert.o HAL/src/alt_dev_llist_insert.c +Compiling alt_dma_rxchan_open.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dma_rxchan_open.o HAL/src/alt_dma_rxchan_open.c +Compiling alt_dma_txchan_open.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_dma_txchan_open.o HAL/src/alt_dma_txchan_open.c +Compiling alt_do_ctors.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_do_ctors.o HAL/src/alt_do_ctors.c +Compiling alt_do_dtors.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_do_dtors.o HAL/src/alt_do_dtors.c +Compiling alt_environ.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_environ.o HAL/src/alt_environ.c +Compiling alt_errno.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_errno.o HAL/src/alt_errno.c +Compiling alt_exception_entry.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_exception_entry.o HAL/src/alt_exception_entry.S +Compiling alt_exception_muldiv.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_exception_muldiv.o HAL/src/alt_exception_muldiv.S +Compiling alt_exception_trap.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_exception_trap.o HAL/src/alt_exception_trap.S +Compiling alt_execve.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_execve.o HAL/src/alt_execve.c +Compiling alt_exit.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_exit.o HAL/src/alt_exit.c +Compiling alt_fcntl.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fcntl.o HAL/src/alt_fcntl.c +Compiling alt_fd_lock.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fd_lock.o HAL/src/alt_fd_lock.c +Compiling alt_fd_unlock.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fd_unlock.o HAL/src/alt_fd_unlock.c +Compiling alt_find_dev.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_find_dev.o HAL/src/alt_find_dev.c +Compiling alt_find_file.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_find_file.o HAL/src/alt_find_file.c +Compiling alt_flash_dev.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_flash_dev.o HAL/src/alt_flash_dev.c +Compiling alt_fork.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fork.o HAL/src/alt_fork.c +Compiling alt_fs_reg.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fs_reg.o HAL/src/alt_fs_reg.c +Compiling alt_fstat.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_fstat.o HAL/src/alt_fstat.c +Compiling alt_get_fd.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_get_fd.o HAL/src/alt_get_fd.c +Compiling alt_getchar.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_getchar.o HAL/src/alt_getchar.c +Compiling alt_getpid.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_getpid.o HAL/src/alt_getpid.c +Compiling alt_gettod.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_gettod.o HAL/src/alt_gettod.c +Compiling alt_gmon.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_gmon.o HAL/src/alt_gmon.c +Compiling alt_icache_flush.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_icache_flush.o HAL/src/alt_icache_flush.c +Compiling alt_icache_flush_all.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_icache_flush_all.o HAL/src/alt_icache_flush_all.c +Compiling alt_iic.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_iic.o HAL/src/alt_iic.c +Compiling alt_iic_isr_register.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_iic_isr_register.o HAL/src/alt_iic_isr_register.c +Compiling alt_instruction_exception_entry.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_instruction_exception_entry.o HAL/src/alt_instruction_exception_entry.c +Compiling alt_instruction_exception_register.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_instruction_exception_register.o HAL/src/alt_instruction_exception_register.c +Compiling alt_io_redirect.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_io_redirect.o HAL/src/alt_io_redirect.c +Compiling alt_ioctl.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_ioctl.o HAL/src/alt_ioctl.c +Compiling alt_irq_entry.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_irq_entry.o HAL/src/alt_irq_entry.S +Compiling alt_irq_handler.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_irq_handler.o HAL/src/alt_irq_handler.c +Compiling alt_irq_register.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_irq_register.o HAL/src/alt_irq_register.c +Compiling alt_irq_vars.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_irq_vars.o HAL/src/alt_irq_vars.c +Compiling alt_isatty.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_isatty.o HAL/src/alt_isatty.c +Compiling alt_kill.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_kill.o HAL/src/alt_kill.c +Compiling alt_link.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_link.o HAL/src/alt_link.c +Compiling alt_load.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_load.o HAL/src/alt_load.c +Compiling alt_log_macro.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_log_macro.o HAL/src/alt_log_macro.S +Compiling alt_log_printf.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_log_printf.o HAL/src/alt_log_printf.c +Compiling alt_lseek.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_lseek.o HAL/src/alt_lseek.c +Compiling alt_main.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_main.o HAL/src/alt_main.c +Compiling alt_mcount.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_mcount.o HAL/src/alt_mcount.S +Compiling alt_open.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_open.o HAL/src/alt_open.c +Compiling alt_printf.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_printf.o HAL/src/alt_printf.c +Compiling alt_putchar.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_putchar.o HAL/src/alt_putchar.c +Compiling alt_putstr.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_putstr.o HAL/src/alt_putstr.c +Compiling alt_read.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_read.o HAL/src/alt_read.c +Compiling alt_release_fd.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_release_fd.o HAL/src/alt_release_fd.c +Compiling alt_remap_cached.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_remap_cached.o HAL/src/alt_remap_cached.c +Compiling alt_remap_uncached.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_remap_uncached.o HAL/src/alt_remap_uncached.c +Compiling alt_rename.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_rename.o HAL/src/alt_rename.c +Compiling alt_sbrk.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_sbrk.o HAL/src/alt_sbrk.c +Compiling alt_settod.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_settod.o HAL/src/alt_settod.c +Compiling alt_software_exception.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/alt_software_exception.o HAL/src/alt_software_exception.S +Compiling alt_stat.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_stat.o HAL/src/alt_stat.c +Compiling alt_tick.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_tick.o HAL/src/alt_tick.c +Compiling alt_times.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_times.o HAL/src/alt_times.c +Compiling alt_uncached_free.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_uncached_free.o HAL/src/alt_uncached_free.c +Compiling alt_uncached_malloc.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_uncached_malloc.o HAL/src/alt_uncached_malloc.c +Compiling alt_unlink.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_unlink.o HAL/src/alt_unlink.c +Compiling alt_usleep.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_usleep.o HAL/src/alt_usleep.c +Compiling alt_wait.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_wait.o HAL/src/alt_wait.c +Compiling alt_write.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/alt_write.o HAL/src/alt_write.c +Compiling altera_nios2_qsys_irq.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/altera_nios2_qsys_irq.o HAL/src/altera_nios2_qsys_irq.c +Compiling crt0.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/crt0.o HAL/src/crt0.S +Compiling os_cpu_a.S... +nios2-elf-gcc -MP -MMD -c -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -Wa,-gdwarf2 -o obj/HAL/src/os_cpu_a.o HAL/src/os_cpu_a.S +Compiling os_cpu_c.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/HAL/src/os_cpu_c.o HAL/src/os_cpu_c.c +Compiling alt_env_lock.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/alt_env_lock.o UCOSII/src/alt_env_lock.c +Compiling alt_malloc_lock.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/alt_malloc_lock.o UCOSII/src/alt_malloc_lock.c +Compiling os_core.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_core.o UCOSII/src/os_core.c +Compiling os_dbg.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_dbg.o UCOSII/src/os_dbg.c +Compiling os_flag.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_flag.o UCOSII/src/os_flag.c +Compiling os_mbox.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_mbox.o UCOSII/src/os_mbox.c +Compiling os_mem.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_mem.o UCOSII/src/os_mem.c +Compiling os_mutex.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_mutex.o UCOSII/src/os_mutex.c +Compiling os_q.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_q.o UCOSII/src/os_q.c +Compiling os_sem.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_sem.o UCOSII/src/os_sem.c +Compiling os_task.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_task.o UCOSII/src/os_task.c +Compiling os_time.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_time.o UCOSII/src/os_time.c +Compiling os_tmr.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/UCOSII/src/os_tmr.o UCOSII/src/os_tmr.c +Compiling alt_sys_init.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/alt_sys_init.o alt_sys_init.c +Compiling altera_avalon_jtag_uart_fd.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_jtag_uart_fd.o drivers/src/altera_avalon_jtag_uart_fd.c +Compiling altera_avalon_jtag_uart_init.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_jtag_uart_init.o drivers/src/altera_avalon_jtag_uart_init.c +Compiling altera_avalon_jtag_uart_ioctl.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_jtag_uart_ioctl.o drivers/src/altera_avalon_jtag_uart_ioctl.c +Compiling altera_avalon_jtag_uart_read.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_jtag_uart_read.o drivers/src/altera_avalon_jtag_uart_read.c +Compiling altera_avalon_jtag_uart_write.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_jtag_uart_write.o drivers/src/altera_avalon_jtag_uart_write.c +Compiling altera_avalon_sysid_qsys.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_sysid_qsys.o drivers/src/altera_avalon_sysid_qsys.c +Compiling altera_avalon_timer_sc.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_timer_sc.o drivers/src/altera_avalon_timer_sc.c +Compiling altera_avalon_timer_ts.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_timer_ts.o drivers/src/altera_avalon_timer_ts.c +Compiling altera_avalon_timer_vars.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_timer_vars.o drivers/src/altera_avalon_timer_vars.c +Compiling altera_avalon_uart_fd.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_uart_fd.o drivers/src/altera_avalon_uart_fd.c +Compiling altera_avalon_uart_init.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_uart_init.o drivers/src/altera_avalon_uart_init.c +Compiling altera_avalon_uart_ioctl.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_uart_ioctl.o drivers/src/altera_avalon_uart_ioctl.c +Compiling altera_avalon_uart_read.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_uart_read.o drivers/src/altera_avalon_uart_read.c +Compiling altera_avalon_uart_write.c... +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_avalon_uart_write.o drivers/src/altera_avalon_uart_write.c +drivers/src/altera_up_avalon_rs232.c: In function 'alt_up_rs232_read_fd': +Compiling altera_up_avalon_rs232.c... +drivers/src/altera_up_avalon_rs232.c:110: warning: pointer targets in passing argument 2 of 'alt_up_rs232_read_data' differ in signedness +nios2-elf-gcc -xc -MP -MMD -c -I./UCOSII/inc -I./HAL/inc -I. -I./drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/drivers/src/altera_up_avalon_rs232.o drivers/src/altera_up_avalon_rs232.c +Creating libucosii_bsp.a... +rm -f -f libucosii_bsp.a +nios2-elf-ar -src libucosii_bsp.a obj/HAL/src/alt_alarm_start.o obj/HAL/src/alt_busy_sleep.o obj/HAL/src/alt_close.o obj/HAL/src/alt_dcache_flush.o obj/HAL/src/alt_dcache_flush_all.o obj/HAL/src/alt_dcache_flush_no_writeback.o obj/HAL/src/alt_dev.o obj/HAL/src/alt_dev_llist_insert.o obj/HAL/src/alt_dma_rxchan_open.o obj/HAL/src/alt_dma_txchan_open.o obj/HAL/src/alt_do_ctors.o obj/HAL/src/alt_do_dtors.o obj/HAL/src/alt_environ.o obj/HAL/src/alt_errno.o obj/HAL/src/alt_exception_entry.o obj/HAL/src/alt_exception_muldiv.o obj/HAL/src/alt_exception_trap.o obj/HAL/src/alt_execve.o obj/HAL/src/alt_exit.o obj/HAL/src/alt_fcntl.o obj/HAL/src/alt_fd_lock.o obj/HAL/src/alt_fd_unlock.o obj/HAL/src/alt_find_dev.o obj/HAL/src/alt_find_file.o obj/HAL/src/alt_flash_dev.o obj/HAL/src/alt_fork.o obj/HAL/src/alt_fs_reg.o obj/HAL/src/alt_fstat.o obj/HAL/src/alt_get_fd.o obj/HAL/src/alt_getchar.o obj/HAL/src/alt_getpid.o obj/HAL/src/alt_gettod.o obj/HAL/src/alt_gmon.o obj/HAL/src/alt_icache_flush.o obj/HAL/src/alt_icache_flush_all.o obj/HAL/src/alt_iic.o obj/HAL/src/alt_iic_isr_register.o obj/HAL/src/alt_instruction_exception_entry.o obj/HAL/src/alt_instruction_exception_register.o obj/HAL/src/alt_io_redirect.o obj/HAL/src/alt_ioctl.o obj/HAL/src/alt_irq_entry.o obj/HAL/src/alt_irq_handler.o obj/HAL/src/alt_irq_register.o obj/HAL/src/alt_irq_vars.o obj/HAL/src/alt_isatty.o obj/HAL/src/alt_kill.o obj/HAL/src/alt_link.o obj/HAL/src/alt_load.o obj/HAL/src/alt_log_macro.o obj/HAL/src/alt_log_printf.o obj/HAL/src/alt_lseek.o obj/HAL/src/alt_main.o obj/HAL/src/alt_mcount.o obj/HAL/src/alt_open.o obj/HAL/src/alt_printf.o obj/HAL/src/alt_putchar.o obj/HAL/src/alt_putstr.o obj/HAL/src/alt_read.o obj/HAL/src/alt_release_fd.o obj/HAL/src/alt_remap_cached.o obj/HAL/src/alt_remap_uncached.o obj/HAL/src/alt_rename.o obj/HAL/src/alt_sbrk.o obj/HAL/src/alt_settod.o obj/HAL/src/alt_software_exception.o obj/HAL/src/alt_stat.o obj/HAL/src/alt_tick.o obj/HAL/src/alt_times.o obj/HAL/src/alt_uncached_free.o obj/HAL/src/alt_uncached_malloc.o obj/HAL/src/alt_unlink.o obj/HAL/src/alt_usleep.o obj/HAL/src/alt_wait.o obj/HAL/src/alt_write.o obj/HAL/src/altera_nios2_qsys_irq.o obj/HAL/src/crt0.o obj/HAL/src/os_cpu_a.o obj/HAL/src/os_cpu_c.o obj/UCOSII/src/alt_env_lock.o obj/UCOSII/src/alt_malloc_lock.o obj/UCOSII/src/os_core.o obj/UCOSII/src/os_dbg.o obj/UCOSII/src/os_flag.o obj/UCOSII/src/os_mbox.o obj/UCOSII/src/os_mem.o obj/UCOSII/src/os_mutex.o obj/UCOSII/src/os_q.o obj/UCOSII/src/os_sem.o obj/UCOSII/src/os_task.o obj/UCOSII/src/os_time.o obj/UCOSII/src/os_tmr.o obj/alt_sys_init.o obj/drivers/src/altera_avalon_jtag_uart_fd.o obj/drivers/src/altera_avalon_jtag_uart_init.o obj/drivers/src/altera_avalon_jtag_uart_ioctl.o obj/drivers/src/altera_avalon_jtag_uart_read.o obj/drivers/src/altera_avalon_jtag_uart_write.o obj/drivers/src/altera_avalon_sysid_qsys.o obj/drivers/src/altera_avalon_timer_sc.o obj/drivers/src/altera_avalon_timer_ts.o obj/drivers/src/altera_avalon_timer_vars.o obj/drivers/src/altera_avalon_uart_fd.o obj/drivers/src/altera_avalon_uart_init.o obj/drivers/src/altera_avalon_uart_ioctl.o obj/drivers/src/altera_avalon_uart_read.o obj/drivers/src/altera_avalon_uart_write.o obj/drivers/src/altera_up_avalon_rs232.o +[BSP build complete] +Info: Compiling MotorHandler.cpp to obj/default/MotorHandler.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/MotorHandler.o MotorHandler.cpp +Info: Compiling main.cpp to obj/default/main.o +nios2-elf-gcc -xc++ -MP -MMD -c -I../MCTest_bsp//UCOSII/inc -I../MCTest_bsp//HAL/inc -I../MCTest_bsp/ -I../MCTest_bsp//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -D__ucosii__ -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o obj/default/main.o main.cpp +main.cpp:51: warning: 'void isr_on_ir_pushbutton(void*)' defined but not used +Info: Linking MCTest.elf +nios2-elf-g++ -T'../MCTest_bsp//linker.x' -msys-crt0='../MCTest_bsp//obj/HAL/src/crt0.o' -msys-lib=ucosii_bsp -L../MCTest_bsp/ -Wl,-Map=MCTest.map -O0 -g -Wall -EL -mno-hw-div -mhw-mul -mno-hw-mulx -o MCTest.elf obj/default/MotorHandler.o obj/default/main.o -lm +nios2-elf-insert MCTest.elf --thread_model ucosii --cpu_name cpu --qsys true --simulation_enabled false --id 0 --sidp 0x20010c0 --timestamp 1393886764 --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name system --quartus_project_dir "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0" --jdi C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.jdi --sopcinfo C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system.sopcinfo +Info: (MCTest.elf) 147 KBytes program size (code + initialized data). +Info: 16229 KBytes free for stack + heap. +Info: Creating MCTest.objdump +nios2-elf-objdump --disassemble --syms --all-header --source MCTest.elf >MCTest.objdump +[MCTest build complete] + +**** Build Finished **** + +**** Build of configuration Nios II for project MCTest_bsp **** + +make all +[BSP build complete] **** Build Finished **** -**** Build of configuration Nios II for project MCandWifiTestDE0_bsp **** +**** Build of configuration Nios II for project MCTest **** make all +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ [BSP build complete] +[MCTest build complete] **** Build Finished **** -**** Build of configuration Nios II for project MCandWifiTestDE0 **** +**** Build of configuration Nios II for project MCTest **** make all -Info: Building ../MCandWifiTestDE0_bsp/ -make --no-print-directory -C ../MCandWifiTestDE0_bsp/ +Info: Building ../MCTest_bsp/ +make --no-print-directory -C ../MCTest_bsp/ [BSP build complete] -[MCandWifiTestDE0 build complete] +[MCTest build complete] **** Build Finished **** diff --git a/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.resources/.history/24/101bcf0f27a3001313d3adfc59d1f782 b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.resources/.history/24/101bcf0f27a3001313d3adfc59d1f782 new file mode 100644 index 00000000..2e91f09b --- /dev/null +++ b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.resources/.history/24/101bcf0f27a3001313d3adfc59d1f782 @@ -0,0 +1,294 @@ +/************************************************************************* + * ARCap + * Amshu Gongal, Kenan Kigunda + * February 18, 2014 + ************************************************************************** + * Description: * + * Prototype testing for infrared and wifi. + **************************************************************************/ + +#include +#include "includes.h" +#include "altera_avalon_pio_regs.h" +#include "altera_avalon_uart_regs.h" +#include "sys/alt_irq.h" +#include "alt_types.h" +#include "SerialHandler.h" + + +/* Task stacks */ +#define TASK_STACKSIZE 2048 +OS_STK ir_task_stk[TASK_STACKSIZE]; +OS_STK wifi_task_stk[TASK_STACKSIZE]; +OS_STK mc_task_stk[TASK_STACKSIZE]; +/* Task priorities */ +#define IR_TASK_PRIORITY 1 +#define WIFI_TASK_PRIORITY 2 +#define MC_TASK_PRIORITY 2 + + +/* Error status */ +#define OK 0 + +/* Message queues */ +#define WAIT_FOREVER 0 + +// ==== INFRARED ==== + +/* Infrared message queue */ +#define IR_MAX_MESSAGES 4 +int ir_messages[IR_MAX_MESSAGES]; +OS_EVENT *ir_queue; + +/* Infrared messages */ +// Together these avoid passing 0 to the queue (which is not allowed since queue messages cannot be null) +// and invert pushbutton input (since the pushbutton returns 0 when it is pushed down). +#define IR_QUEUE_SEND_BASE 1 // Use: IR_QUEUE_SEND_BASE + IORD +#define IR_QUEUE_RECEIVE_BASE 2 // Use: IR_QUEUE_RECEIVE_BASE - OSQPend + + +/* Interrupt service routine triggered whenever the status of the IR emitter pushbutton changes. */ +static void isr_on_ir_pushbutton(void * context) { + // Read the state of the pushbutton and post it to the queue. + //printf("Pressed\n"); + int message = IR_QUEUE_SEND_BASE + IORD_ALTERA_AVALON_PIO_DATA(PIO_KEY_LEFT_BASE); + OSQPost(ir_queue, (void*)message); + // Mask to mark the end of the ISR. + IOWR_ALTERA_AVALON_PIO_EDGE_CAP(PIO_KEY_LEFT_BASE, PIO_KEY_LEFT_BIT_CLEARING_EDGE_REGISTER); +} + +/* Controllers the IR emitter based on the value of the pushbutton. */ +void ir_task(void* pdata) +{ + INT8U err; + while (1) + { + // Read the value from the queue. + int status = IR_QUEUE_RECEIVE_BASE - (int)OSQPend(ir_queue, WAIT_FOREVER, &err); + if (err == OS_NO_ERR) { + // Print the result and send it to the emitter. + printf("IR: %d\n", status); + IOWR_ALTERA_AVALON_PIO_DATA(PIO_IR_EMITTER_BASE, status); + } + } +} + +// ==== WIFI + +#define WIFI_GUARD_TIME 1 + +void wifi_wait() { + OSTimeDlyHMSM(0, 0, WIFI_GUARD_TIME, 0); +} + +void wifi_write(char *message, int length) { + int i; + for (i = 0; i < length; i++) { + IOWR_ALTERA_AVALON_UART_TXDATA(UART_WIFI_BASE, message[i]); + } +} + +void wifi_read() { + int status = IORD_ALTERA_AVALON_UART_STATUS(UART_WIFI_BASE); + printf("Wifi status: %d\n", status); + char c = IORD_ALTERA_AVALON_UART_RXDATA(UART_WIFI_BASE); + printf("Wifi: %c\n", c); +} + +void wifi_task(void *pdata) +{ + printf("Started wifi task\n"); + wifi_wait(); + wifi_write("+++", 3); + wifi_wait(); + wifi_read(); +} + + + +// ==== MC + +void mc_stop(){ + SerialHandler *serial = new SerialHandler(); + //motor 1 + serial->sendByteMC(SERIAL_START_BYTE); + serial->sendByteMC(SERIAL_DEVICE_TYPE); + serial->sendByteMC(SERIAL_MOTOR2_FORWARD); + serial->sendByteMC(SERIAL_STOP_SPEED); + //motor 2 + serial->sendByteMC(SERIAL_START_BYTE); + serial->sendByteMC(SERIAL_DEVICE_TYPE); + serial->sendByteMC(SERIAL_MOTOR3_FORWARD); + serial->sendByteMC(SERIAL_STOP_SPEED); +} +/* + * Moves the rover forward enabling equal drive strength on both motors + */ +void mc_forward(){ + SerialHandler *serial = new SerialHandler(); + //motor 1 + serial->sendByteMC(SERIAL_START_BYTE); + serial->sendByteMC(SERIAL_DEVICE_TYPE); + serial->sendByteMC(SERIAL_MOTOR2_FORWARD); + serial->sendByteMC(SERIAL_CONST_SPEED); + //motor 2 + serial->sendByteMC(SERIAL_START_BYTE); + serial->sendByteMC(SERIAL_DEVICE_TYPE); + serial->sendByteMC(SERIAL_MOTOR3_FORWARD); + serial->sendByteMC(SERIAL_CONST_SPEED); + +} +/* + * Moves the rover backward enabling equal drive strength on both motors + */ +void mc_backward(){ + SerialHandler *serial = new SerialHandler(); + + //motor 1 + serial->sendByteMC(SERIAL_START_BYTE); + serial->sendByteMC(SERIAL_DEVICE_TYPE); + serial->sendByteMC(SERIAL_MOTOR2_BACKWARD); + serial->sendByteMC(SERIAL_CONST_SPEED); + //motor 2 + serial->sendByteMC(SERIAL_START_BYTE); + serial->sendByteMC(SERIAL_DEVICE_TYPE); + serial->sendByteMC(SERIAL_MOTOR3_BACKWARD); + serial->sendByteMC(SERIAL_CONST_SPEED); +} +/* + * Moves the rover left, enabling left drive strength higher than right + */ +void mc_left(){ + SerialHandler *serial = new SerialHandler(); + + //Turn Left by driving the left motor only + + //motor 1 + serial->sendByteMC(SERIAL_START_BYTE); + serial->sendByteMC(SERIAL_DEVICE_TYPE); + serial->sendByteMC(SERIAL_MOTOR2_FORWARD); + serial->sendByteMC(SERIAL_CONST_SPEED); + +} +/* + * Moves the rover right, enabling right drive strength higher than left + */ +void mc_right(){ + SerialHandler *serial = new SerialHandler(); + + //Turn Right by driving right motor only + + //motor 1 + serial->sendByteMC(SERIAL_START_BYTE); + serial->sendByteMC(SERIAL_DEVICE_TYPE); + serial->sendByteMC(SERIAL_MOTOR3_FORWARD); + serial->sendByteMC(SERIAL_CONST_SPEED); +} + +//====MotorContoller +void mc_task(void *pdata) +{ + printf("Started Motor task\n"); + //mc_configure(); + while(1){ + mc_forward(); + + } + +} + +// ==== GENERAL + +void queue_init() { + ir_queue = OSQCreate((void**)&ir_messages, IR_MAX_MESSAGES); +} + +/* The main function creates the LCD task, registers the edge counter polling interrupt, + * and starts the OS. */ +int main(void) +{ + int status; + // Initialize components. + queue_init(); + + // Create the IR task. + OSTaskCreateExt(ir_task, + NULL, + &ir_task_stk[TASK_STACKSIZE - 1], + IR_TASK_PRIORITY, + IR_TASK_PRIORITY, + ir_task_stk, + TASK_STACKSIZE, + NULL, + 0); + + // Create the Wifi task. + OSTaskCreateExt(wifi_task, + NULL, + &wifi_task_stk[TASK_STACKSIZE - 1], + WIFI_TASK_PRIORITY, + WIFI_TASK_PRIORITY, + wifi_task_stk, + TASK_STACKSIZE, + NULL, + 0); + + // Create the MC task. + OSTaskCreateExt(mc_task, + NULL, + &mc_task_stk[TASK_STACKSIZE - 1], + MC_TASK_PRIORITY, + MC_TASK_PRIORITY, + mc_task_stk, + TASK_STACKSIZE, + NULL, + 0); + + // Register the IR pushbutton interrupt. + status = alt_ic_isr_register(PIO_KEY_LEFT_IRQ_INTERRUPT_CONTROLLER_ID, + PIO_KEY_LEFT_IRQ, + isr_on_ir_pushbutton, + NULL, + NULL); + + // Enable key interrupts. + IOWR_ALTERA_AVALON_PIO_IRQ_MASK(PIO_KEY_LEFT_BASE, PIO_KEY_LEFT_CAPTURE); + + // Start. + if (status == OK) { + OSStart(); + } + + return 0; +} + +/****************************************************************************** + * * + * License Agreement * + * * + * Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * + * All rights reserved. * + * * + * Permission is hereby granted, free of charge, to any person obtaining a * + * copy of this software and associated documentation files (the "Software"), * + * to deal in the Software without restriction, including without limitation * + * the rights to use, copy, modify, merge, publish, distribute, sublicense, * + * and/or sell copies of the Software, and to permit persons to whom the * + * Software is furnished to do so, subject to the following conditions: * + * * + * The above copyright notice and this permission notice shall be included in * + * all copies or substantial portions of the Software. * + * * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * + * DEALINGS IN THE SOFTWARE. * + * * + * This agreement shall be governed in all respects by the laws of the State * + * of California and by the laws of the United States of America. * + * Altera does not recommend, suggest or require that this reference design * + * file be used in conjunction or combination with any other product. * + ******************************************************************************/ diff --git a/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.resources/.history/36/c0fcfa4628a3001313d3adfc59d1f782 b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.resources/.history/36/c0fcfa4628a3001313d3adfc59d1f782 new file mode 100644 index 00000000..4adea63a --- /dev/null +++ b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.resources/.history/36/c0fcfa4628a3001313d3adfc59d1f782 @@ -0,0 +1,26 @@ +/* + * MotorHandler.cpp + * + * Created on: 2014-03-03 + * Author: gongal + */ + +#include "MotorHandler.h" +#include "includes.h" +#include "altera_avalon_uart_regs.h" + +MotorHandler::MotorHandler() { + // TODO Auto-generated constructor stub + +} + +MotorHandler::~MotorHandler() { + // TODO Auto-generated destructor stub +} +void MotorHandler::sendByteMC(char msg){ + IOWR_ALTERA_AVALON_UART_TXDATA(UART_MC_BASE, msg); +} + +void MotorHandler::mc_forward(){ + +} diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0/SerialHandler.h b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.resources/.history/42/b0bc36cd29a3001313d3adfc59d1f782 similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0/SerialHandler.h rename to MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.resources/.history/42/b0bc36cd29a3001313d3adfc59d1f782 diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0/SerialHandler.cpp b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.resources/.history/5a/a07704fd26a3001313d3adfc59d1f782 similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0/SerialHandler.cpp rename to MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.resources/.history/5a/a07704fd26a3001313d3adfc59d1f782 diff --git a/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.resources/.history/61/90e8cab627a3001313d3adfc59d1f782 b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.resources/.history/61/90e8cab627a3001313d3adfc59d1f782 new file mode 100644 index 00000000..445707b0 --- /dev/null +++ b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.resources/.history/61/90e8cab627a3001313d3adfc59d1f782 @@ -0,0 +1,17 @@ +/* + * MotorHandler.h + * + * Created on: 2014-03-03 + * Author: gongal + */ + +#ifndef MOTORHANDLER_H_ +#define MOTORHANDLER_H_ + +class MotorHandler { +public: + MotorHandler(); + virtual ~MotorHandler(); +}; + +#endif /* MOTORHANDLER_H_ */ diff --git a/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.resources/.history/61/d0ec04fd26a3001313d3adfc59d1f782 b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.resources/.history/61/d0ec04fd26a3001313d3adfc59d1f782 new file mode 100644 index 00000000..d9f6b87d --- /dev/null +++ b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.resources/.history/61/d0ec04fd26a3001313d3adfc59d1f782 @@ -0,0 +1,29 @@ +/* + * SerialHandler.h + * + * Created on: 2014-03-01 + * Author: gongal + */ + +#ifndef SERIALHANDLER_H_ +#define SERIALHANDLER_H_ + +#define SERIAL_START_BYTE 0x80 + +#define SERIAL_DEVICE_TYPE 0x00 +#define SERIAL_MOTOR2_BACKWARD 0x04 // motor 2 backward +#define SERIAL_MOTOR3_BACKWARD 0x06 //motor 3 backward +#define SERIAL_MOTOR2_FORWARD 0x05 // motor 2 forward +#define SERIAL_MOTOR3_FORWARD 0x07 // motor 3 forward +#define SERIAL_CONST_SPEED 0x5F +#define SERIAL_STOP_SPEED 0x00 + +class SerialHandler { +public: + SerialHandler(); + virtual ~SerialHandler(); + void sendByteMC(char msg); + void sendDataWifi(char * msg, int length); +}; + +#endif /* SERIALHANDLER_H_ */ diff --git a/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.resources/.history/62/50d840d727a3001313d3adfc59d1f782 b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.resources/.history/62/50d840d727a3001313d3adfc59d1f782 new file mode 100644 index 00000000..9be477a9 --- /dev/null +++ b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.resources/.history/62/50d840d727a3001313d3adfc59d1f782 @@ -0,0 +1,22 @@ +/* + * MotorHandler.cpp + * + * Created on: 2014-03-03 + * Author: gongal + */ + +#include "MotorHandler.h" + +MotorHandler::MotorHandler() { + // TODO Auto-generated constructor stub + +} + +MotorHandler::~MotorHandler() { + // TODO Auto-generated destructor stub +} +void MotorHandler::sendByteMC(char msg){ + IOWR_ALTERA_AVALON_UART_TXDATA(UART_MC_BASE, msg); +} + +void MotorHandler:: diff --git a/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.resources/.history/62/e0cc247c29a3001313d3adfc59d1f782 b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.resources/.history/62/e0cc247c29a3001313d3adfc59d1f782 new file mode 100644 index 00000000..210f1162 --- /dev/null +++ b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.resources/.history/62/e0cc247c29a3001313d3adfc59d1f782 @@ -0,0 +1,79 @@ +/* + * MotorHandler.cpp + * + * Created on: 2014-03-03 + * Author: gongal + */ + +#include "MotorHandler.h" +#include "includes.h" +#include "altera_avalon_uart_regs.h" + +MotorHandler::MotorHandler() { + // TODO Auto-generated constructor stub + +} + +MotorHandler::~MotorHandler() { + // TODO Auto-generated destructor stub +} +void MotorHandler::sendByteMC(char msg){ + IOWR_ALTERA_AVALON_UART_TXDATA(UART_MC_BASE, msg); +} + +void MotorHandler::mc_forward(){ + //motor 1 + sendByteMC(MOTOR_START_BYTE); + sendByteMC(MOTOR_DEVICE_TYPE); + sendByteMC(MOTOR_MOTOR2_FORWARD); + sendByteMC(MOTOR_CONST_SPEED); + //motor 2 + sendByteMC(MOTOR_START_BYTE); + sendByteMC(MOTOR_DEVICE_TYPE); + sendByteMC(MOTOR_MOTOR3_FORWARD); + sendByteMC(MOTOR_CONST_SPEED); +} + +void MotorHandler::mc_backward(){ + //motor 1 + sendByteMC(MOTOR_START_BYTE); + sendByteMC(MOTOR_DEVICE_TYPE); + sendByteMC(MOTOR_MOTOR2_BACKWARD); + sendByteMC(MOTOR_CONST_SPEED); + //motor 2 + sendByteMC(MOTOR_START_BYTE); + sendByteMC(MOTOR_DEVICE_TYPE); + sendByteMC(MOTOR_MOTOR3_BACKWARD); + sendByteMC(MOTOR_CONST_SPEED); +} + +void MotorHandler::mc_left(){ + //Turn Left by driving the left motor only + + //motor 1 + sendByteMC(MOTOR_START_BYTE); + sendByteMC(MOTOR_DEVICE_TYPE); + sendByteMC(MOTOR_MOTOR2_FORWARD); + sendByteMC(MOTOR_CONST_SPEED); +} + +void MotorHandler::mc_right(){ + //Turn Right by driving right motor only + + //motor 1 + sendByteMC(MOTOR_START_BYTE); + sendByteMC(MOTOR_DEVICE_TYPE); + sendByteMC(MOTOR_MOTOR3_FORWARD); + sendByteMC(MOTOR_CONST_SPEED); +} +void MotorHandler::mc_stop(){ + sendByteMC(MOTOR_START_BYTE); + sendByteMC(MOTOR_DEVICE_TYPE); + sendByteMC(MOTOR_MOTOR2_FORWARD); + sendByteMC(MOTOR_STOP_SPEED); + //motor 2 + sendByteMC(MOTOR_START_BYTE); + sendByteMC(MOTOR_DEVICE_TYPE); + sendByteMC(MOTOR_MOTOR3_FORWARD); + sendByteMC(MOTOR_STOP_SPEED); +} diff --git a/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.resources/.history/74/505fde7929a3001313d3adfc59d1f782 b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.resources/.history/74/505fde7929a3001313d3adfc59d1f782 new file mode 100644 index 00000000..9ed4851f --- /dev/null +++ b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.resources/.history/74/505fde7929a3001313d3adfc59d1f782 @@ -0,0 +1,219 @@ +/************************************************************************* + * ARCap + * Amshu Gongal, Kenan Kigunda + * February 18, 2014 + ************************************************************************** + * Description: * + * Prototype testing for infrared and wifi. + **************************************************************************/ + +#include +#include "includes.h" +#include "altera_avalon_pio_regs.h" +#include "altera_avalon_uart_regs.h" +#include "sys/alt_irq.h" +#include "alt_types.h" +#include "SerialHandler.h" +#include "MotorHandler.h" + + +/* Task stacks */ +#define TASK_STACKSIZE 2048 +OS_STK ir_task_stk[TASK_STACKSIZE]; +OS_STK wifi_task_stk[TASK_STACKSIZE]; +OS_STK mc_task_stk[TASK_STACKSIZE]; +/* Task priorities */ +#define IR_TASK_PRIORITY 1 +#define WIFI_TASK_PRIORITY 2 +#define MC_TASK_PRIORITY 2 + + +/* Error status */ +#define OK 0 + +/* Message queues */ +#define WAIT_FOREVER 0 + +// ==== INFRARED ==== + +/* Infrared message queue */ +#define IR_MAX_MESSAGES 4 +int ir_messages[IR_MAX_MESSAGES]; +OS_EVENT *ir_queue; + +/* Infrared messages */ +// Together these avoid passing 0 to the queue (which is not allowed since queue messages cannot be null) +// and invert pushbutton input (since the pushbutton returns 0 when it is pushed down). +#define IR_QUEUE_SEND_BASE 1 // Use: IR_QUEUE_SEND_BASE + IORD +#define IR_QUEUE_RECEIVE_BASE 2 // Use: IR_QUEUE_RECEIVE_BASE - OSQPend + + +/* Interrupt service routine triggered whenever the status of the IR emitter pushbutton changes. */ +static void isr_on_ir_pushbutton(void * context) { + // Read the state of the pushbutton and post it to the queue. + //printf("Pressed\n"); + int message = IR_QUEUE_SEND_BASE + IORD_ALTERA_AVALON_PIO_DATA(PIO_KEY_LEFT_BASE); + OSQPost(ir_queue, (void*)message); + // Mask to mark the end of the ISR. + IOWR_ALTERA_AVALON_PIO_EDGE_CAP(PIO_KEY_LEFT_BASE, PIO_KEY_LEFT_BIT_CLEARING_EDGE_REGISTER); +} + +/* Controllers the IR emitter based on the value of the pushbutton. */ +void ir_task(void* pdata) +{ + INT8U err; + while (1) + { + // Read the value from the queue. + int status = IR_QUEUE_RECEIVE_BASE - (int)OSQPend(ir_queue, WAIT_FOREVER, &err); + if (err == OS_NO_ERR) { + // Print the result and send it to the emitter. + printf("IR: %d\n", status); + IOWR_ALTERA_AVALON_PIO_DATA(PIO_IR_EMITTER_BASE, status); + } + } +} + +// ==== WIFI + +#define WIFI_GUARD_TIME 1 + +void wifi_wait() { + OSTimeDlyHMSM(0, 0, WIFI_GUARD_TIME, 0); +} + +void wifi_write(char *message, int length) { + int i; + for (i = 0; i < length; i++) { + IOWR_ALTERA_AVALON_UART_TXDATA(UART_WIFI_BASE, message[i]); + } +} + +void wifi_read() { + int status = IORD_ALTERA_AVALON_UART_STATUS(UART_WIFI_BASE); + printf("Wifi status: %d\n", status); + char c = IORD_ALTERA_AVALON_UART_RXDATA(UART_WIFI_BASE); + printf("Wifi: %c\n", c); +} + +void wifi_task(void *pdata) +{ + printf("Started wifi task\n"); + wifi_wait(); + wifi_write("+++", 3); + wifi_wait(); + wifi_read(); +} + + + +// ==== MC + + +//====MotorContoller +void mc_task(void *pdata) +{ + printf("Started Motor task\n"); + //mc_configure(); + while(1){ + mc_forward(); + + } + +} + +// ==== GENERAL + +void queue_init() { + ir_queue = OSQCreate((void**)&ir_messages, IR_MAX_MESSAGES); +} + +/* The main function creates the LCD task, registers the edge counter polling interrupt, + * and starts the OS. */ +int main(void) +{ + int status; + // Initialize components. + queue_init(); + + // Create the IR task. + OSTaskCreateExt(ir_task, + NULL, + &ir_task_stk[TASK_STACKSIZE - 1], + IR_TASK_PRIORITY, + IR_TASK_PRIORITY, + ir_task_stk, + TASK_STACKSIZE, + NULL, + 0); + + // Create the Wifi task. + OSTaskCreateExt(wifi_task, + NULL, + &wifi_task_stk[TASK_STACKSIZE - 1], + WIFI_TASK_PRIORITY, + WIFI_TASK_PRIORITY, + wifi_task_stk, + TASK_STACKSIZE, + NULL, + 0); + + // Create the MC task. + OSTaskCreateExt(mc_task, + NULL, + &mc_task_stk[TASK_STACKSIZE - 1], + MC_TASK_PRIORITY, + MC_TASK_PRIORITY, + mc_task_stk, + TASK_STACKSIZE, + NULL, + 0); + + // Register the IR pushbutton interrupt. + /*status = alt_ic_isr_register(PIO_KEY_LEFT_IRQ_INTERRUPT_CONTROLLER_ID, + PIO_KEY_LEFT_IRQ, + isr_on_ir_pushbutton, + NULL, + NULL);*/ + + // Enable key interrupts. + IOWR_ALTERA_AVALON_PIO_IRQ_MASK(PIO_KEY_LEFT_BASE, PIO_KEY_LEFT_CAPTURE); + + // Start. + if (status == OK) { + OSStart(); + } + + return 0; +} + +/****************************************************************************** + * * + * License Agreement * + * * + * Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * + * All rights reserved. * + * * + * Permission is hereby granted, free of charge, to any person obtaining a * + * copy of this software and associated documentation files (the "Software"), * + * to deal in the Software without restriction, including without limitation * + * the rights to use, copy, modify, merge, publish, distribute, sublicense, * + * and/or sell copies of the Software, and to permit persons to whom the * + * Software is furnished to do so, subject to the following conditions: * + * * + * The above copyright notice and this permission notice shall be included in * + * all copies or substantial portions of the Software. * + * * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * + * DEALINGS IN THE SOFTWARE. * + * * + * This agreement shall be governed in all respects by the laws of the State * + * of California and by the laws of the United States of America. * + * Altera does not recommend, suggest or require that this reference design * + * file be used in conjunction or combination with any other product. * + ******************************************************************************/ diff --git a/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.resources/.history/86/b03ea6b527a3001313d3adfc59d1f782 b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.resources/.history/86/b03ea6b527a3001313d3adfc59d1f782 new file mode 100644 index 00000000..2cb64e34 --- /dev/null +++ b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.resources/.history/86/b03ea6b527a3001313d3adfc59d1f782 @@ -0,0 +1,18 @@ +/* + * MotorHandler.cpp + * + * Created on: 2014-03-03 + * Author: gongal + */ + +#include "MotorHandler.h" + +MotorHandler::MotorHandler() { + // TODO Auto-generated constructor stub + +} + +MotorHandler::~MotorHandler() { + // TODO Auto-generated destructor stub +} + diff --git a/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.resources/.history/89/6033f7c729a3001313d3adfc59d1f782 b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.resources/.history/89/6033f7c729a3001313d3adfc59d1f782 new file mode 100644 index 00000000..de4e522a --- /dev/null +++ b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.resources/.history/89/6033f7c729a3001313d3adfc59d1f782 @@ -0,0 +1,215 @@ +/************************************************************************* + * ARCap + * Amshu Gongal, Kenan Kigunda + * February 18, 2014 + ************************************************************************** + * Description: * + * Prototype testing for infrared and wifi. + **************************************************************************/ + +#include +#include "includes.h" +#include "altera_avalon_pio_regs.h" +#include "altera_avalon_uart_regs.h" +#include "sys/alt_irq.h" +#include "alt_types.h" +#include "SerialHandler.h" +#include "MotorHandler.h" + +MotorHandler * motorHandler = new MotorHandler(); +/* Task stacks */ +#define TASK_STACKSIZE 2048 +OS_STK ir_task_stk[TASK_STACKSIZE]; +OS_STK wifi_task_stk[TASK_STACKSIZE]; +OS_STK mc_task_stk[TASK_STACKSIZE]; +/* Task priorities */ +#define IR_TASK_PRIORITY 1 +#define WIFI_TASK_PRIORITY 2 +#define MC_TASK_PRIORITY 2 + + +/* Error status */ +#define OK 0 + +/* Message queues */ +#define WAIT_FOREVER 0 + +// ==== INFRARED ==== + +/* Infrared message queue */ +#define IR_MAX_MESSAGES 4 +int ir_messages[IR_MAX_MESSAGES]; +OS_EVENT *ir_queue; + +/* Infrared messages */ +// Together these avoid passing 0 to the queue (which is not allowed since queue messages cannot be null) +// and invert pushbutton input (since the pushbutton returns 0 when it is pushed down). +#define IR_QUEUE_SEND_BASE 1 // Use: IR_QUEUE_SEND_BASE + IORD +#define IR_QUEUE_RECEIVE_BASE 2 // Use: IR_QUEUE_RECEIVE_BASE - OSQPend + + +/* Interrupt service routine triggered whenever the status of the IR emitter pushbutton changes. */ +static void isr_on_ir_pushbutton(void * context) { + // Read the state of the pushbutton and post it to the queue. + //printf("Pressed\n"); + int message = IR_QUEUE_SEND_BASE + IORD_ALTERA_AVALON_PIO_DATA(PIO_KEY_LEFT_BASE); + OSQPost(ir_queue, (void*)message); + // Mask to mark the end of the ISR. + IOWR_ALTERA_AVALON_PIO_EDGE_CAP(PIO_KEY_LEFT_BASE, PIO_KEY_LEFT_BIT_CLEARING_EDGE_REGISTER); +} + +/* Controllers the IR emitter based on the value of the pushbutton. */ +void ir_task(void* pdata) +{ + INT8U err; + while (1) + { + // Read the value from the queue. + int status = IR_QUEUE_RECEIVE_BASE - (int)OSQPend(ir_queue, WAIT_FOREVER, &err); + if (err == OS_NO_ERR) { + // Print the result and send it to the emitter. + printf("IR: %d\n", status); + IOWR_ALTERA_AVALON_PIO_DATA(PIO_IR_EMITTER_BASE, status); + } + } +} + +// ==== WIFI + +#define WIFI_GUARD_TIME 1 + +void wifi_wait() { + OSTimeDlyHMSM(0, 0, WIFI_GUARD_TIME, 0); +} + +void wifi_write(char *message, int length) { + int i; + for (i = 0; i < length; i++) { + IOWR_ALTERA_AVALON_UART_TXDATA(UART_WIFI_BASE, message[i]); + } +} + +void wifi_read() { + int status = IORD_ALTERA_AVALON_UART_STATUS(UART_WIFI_BASE); + printf("Wifi status: %d\n", status); + char c = IORD_ALTERA_AVALON_UART_RXDATA(UART_WIFI_BASE); + printf("Wifi: %c\n", c); +} + +void wifi_task(void *pdata) +{ + printf("Started wifi task\n"); + wifi_wait(); + wifi_write("+++", 3); + wifi_wait(); + wifi_read(); +} + + + +// ==== MC + + +//====MotorContoller +void mc_task(void *pdata) +{ + motorHandler->mc_forward(); + OSTimeDlyHMSM(0, 0, 4, 0); + motorHandler->mc_stop(); +} + +// ==== GENERAL + +void queue_init() { + ir_queue = OSQCreate((void**)&ir_messages, IR_MAX_MESSAGES); +} + +/* The main function creates the LCD task, registers the edge counter polling interrupt, + * and starts the OS. */ +int main(void) +{ + int status; + // Initialize components. + queue_init(); + + // Create the IR task. + OSTaskCreateExt(ir_task, + NULL, + &ir_task_stk[TASK_STACKSIZE - 1], + IR_TASK_PRIORITY, + IR_TASK_PRIORITY, + ir_task_stk, + TASK_STACKSIZE, + NULL, + 0); + + // Create the Wifi task. + OSTaskCreateExt(wifi_task, + NULL, + &wifi_task_stk[TASK_STACKSIZE - 1], + WIFI_TASK_PRIORITY, + WIFI_TASK_PRIORITY, + wifi_task_stk, + TASK_STACKSIZE, + NULL, + 0); + + // Create the MC task. + OSTaskCreateExt(mc_task, + NULL, + &mc_task_stk[TASK_STACKSIZE - 1], + MC_TASK_PRIORITY, + MC_TASK_PRIORITY, + mc_task_stk, + TASK_STACKSIZE, + NULL, + 0); + + // Register the IR pushbutton interrupt. + /*status = alt_ic_isr_register(PIO_KEY_LEFT_IRQ_INTERRUPT_CONTROLLER_ID, + PIO_KEY_LEFT_IRQ, + isr_on_ir_pushbutton, + NULL, + NULL);*/ + + // Enable key interrupts. + IOWR_ALTERA_AVALON_PIO_IRQ_MASK(PIO_KEY_LEFT_BASE, PIO_KEY_LEFT_CAPTURE); + + // Start. + if (status == OK) { + OSStart(); + } + + return 0; +} + +/****************************************************************************** + * * + * License Agreement * + * * + * Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * + * All rights reserved. * + * * + * Permission is hereby granted, free of charge, to any person obtaining a * + * copy of this software and associated documentation files (the "Software"), * + * to deal in the Software without restriction, including without limitation * + * the rights to use, copy, modify, merge, publish, distribute, sublicense, * + * and/or sell copies of the Software, and to permit persons to whom the * + * Software is furnished to do so, subject to the following conditions: * + * * + * The above copyright notice and this permission notice shall be included in * + * all copies or substantial portions of the Software. * + * * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * + * DEALINGS IN THE SOFTWARE. * + * * + * This agreement shall be governed in all respects by the laws of the State * + * of California and by the laws of the United States of America. * + * Altera does not recommend, suggest or require that this reference design * + * file be used in conjunction or combination with any other product. * + ******************************************************************************/ diff --git a/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.resources/.history/8d/702036cd29a3001313d3adfc59d1f782 b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.resources/.history/8d/702036cd29a3001313d3adfc59d1f782 new file mode 100644 index 00000000..09aecfa9 --- /dev/null +++ b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.resources/.history/8d/702036cd29a3001313d3adfc59d1f782 @@ -0,0 +1,31 @@ +/* + * SerialHandler.cpp + * + * Created on: 2014-03-01 + * Author: gongal + */ + +#include "SerialHandler.h" +#include "includes.h" +#include "altera_avalon_uart_regs.h" + +SerialHandler::SerialHandler() { + // TODO Auto-generated constructor stub + +} + +SerialHandler::~SerialHandler() { + // TODO Auto-generated destructor stub +} + +void SerialHandler::sendByteMC(char msg){ + IOWR_ALTERA_AVALON_UART_TXDATA(UART_MC_BASE, msg); +} + +void SerialHandler::sendDataWifi(char * msg, int length){ + int i; + for(i = 0; i +#include "includes.h" +#include "altera_avalon_pio_regs.h" +#include "altera_avalon_uart_regs.h" +#include "sys/alt_irq.h" +#include "alt_types.h" +#include "SerialHandler.h" + + +/* Task stacks */ +#define TASK_STACKSIZE 2048 +OS_STK ir_task_stk[TASK_STACKSIZE]; +OS_STK wifi_task_stk[TASK_STACKSIZE]; +OS_STK mc_task_stk[TASK_STACKSIZE]; +/* Task priorities */ +#define IR_TASK_PRIORITY 1 +#define WIFI_TASK_PRIORITY 2 +#define MC_TASK_PRIORITY 2 + + +/* Error status */ +#define OK 0 + +/* Message queues */ +#define WAIT_FOREVER 0 + +// ==== INFRARED ==== + +/* Infrared message queue */ +#define IR_MAX_MESSAGES 4 +int ir_messages[IR_MAX_MESSAGES]; +OS_EVENT *ir_queue; + +/* Infrared messages */ +// Together these avoid passing 0 to the queue (which is not allowed since queue messages cannot be null) +// and invert pushbutton input (since the pushbutton returns 0 when it is pushed down). +#define IR_QUEUE_SEND_BASE 1 // Use: IR_QUEUE_SEND_BASE + IORD +#define IR_QUEUE_RECEIVE_BASE 2 // Use: IR_QUEUE_RECEIVE_BASE - OSQPend + + +/* Interrupt service routine triggered whenever the status of the IR emitter pushbutton changes. */ +static void isr_on_ir_pushbutton(void * context) { + // Read the state of the pushbutton and post it to the queue. + //printf("Pressed\n"); + int message = IR_QUEUE_SEND_BASE + IORD_ALTERA_AVALON_PIO_DATA(PIO_KEY_LEFT_BASE); + OSQPost(ir_queue, (void*)message); + // Mask to mark the end of the ISR. + IOWR_ALTERA_AVALON_PIO_EDGE_CAP(PIO_KEY_LEFT_BASE, PIO_KEY_LEFT_BIT_CLEARING_EDGE_REGISTER); +} + +/* Controllers the IR emitter based on the value of the pushbutton. */ +void ir_task(void* pdata) +{ + INT8U err; + while (1) + { + // Read the value from the queue. + int status = IR_QUEUE_RECEIVE_BASE - (int)OSQPend(ir_queue, WAIT_FOREVER, &err); + if (err == OS_NO_ERR) { + // Print the result and send it to the emitter. + printf("IR: %d\n", status); + IOWR_ALTERA_AVALON_PIO_DATA(PIO_IR_EMITTER_BASE, status); + } + } +} + +// ==== WIFI + +#define WIFI_GUARD_TIME 1 + +void wifi_wait() { + OSTimeDlyHMSM(0, 0, WIFI_GUARD_TIME, 0); +} + +void wifi_write(char *message, int length) { + int i; + for (i = 0; i < length; i++) { + IOWR_ALTERA_AVALON_UART_TXDATA(UART_WIFI_BASE, message[i]); + } +} + +void wifi_read() { + int status = IORD_ALTERA_AVALON_UART_STATUS(UART_WIFI_BASE); + printf("Wifi status: %d\n", status); + char c = IORD_ALTERA_AVALON_UART_RXDATA(UART_WIFI_BASE); + printf("Wifi: %c\n", c); +} + +void wifi_task(void *pdata) +{ + printf("Started wifi task\n"); + wifi_wait(); + wifi_write("+++", 3); + wifi_wait(); + wifi_read(); +} + + + +// ==== MC + +void mc_stop(){ + SerialHandler *serial = new SerialHandler(); + //motor 1 + serial->sendByteMC(SERIAL_START_BYTE); + serial->sendByteMC(SERIAL_DEVICE_TYPE); + serial->sendByteMC(SERIAL_MOTOR2_FORWARD); + serial->sendByteMC(SERIAL_STOP_SPEED); + //motor 2 + serial->sendByteMC(SERIAL_START_BYTE); + serial->sendByteMC(SERIAL_DEVICE_TYPE); + serial->sendByteMC(SERIAL_MOTOR3_FORWARD); + serial->sendByteMC(SERIAL_STOP_SPEED); +} +/* + * Moves the rover forward enabling equal drive strength on both motors + */ +void mc_forward(){ + SerialHandler *serial = new SerialHandler(); + //motor 1 + serial->sendByteMC(SERIAL_START_BYTE); + serial->sendByteMC(SERIAL_DEVICE_TYPE); + serial->sendByteMC(SERIAL_MOTOR2_FORWARD); + serial->sendByteMC(SERIAL_CONST_SPEED); + //motor 2 + serial->sendByteMC(SERIAL_START_BYTE); + serial->sendByteMC(SERIAL_DEVICE_TYPE); + serial->sendByteMC(SERIAL_MOTOR3_FORWARD); + serial->sendByteMC(SERIAL_CONST_SPEED); + +} +/* + * Moves the rover backward enabling equal drive strength on both motors + */ +void mc_backward(){ + SerialHandler *serial = new SerialHandler(); + + //motor 1 + serial->sendByteMC(SERIAL_START_BYTE); + serial->sendByteMC(SERIAL_DEVICE_TYPE); + serial->sendByteMC(SERIAL_MOTOR2_BACKWARD); + serial->sendByteMC(SERIAL_CONST_SPEED); + //motor 2 + serial->sendByteMC(SERIAL_START_BYTE); + serial->sendByteMC(SERIAL_DEVICE_TYPE); + serial->sendByteMC(SERIAL_MOTOR3_BACKWARD); + serial->sendByteMC(SERIAL_CONST_SPEED); +} +/* + * Moves the rover left, enabling left drive strength higher than right + */ +void mc_left(){ + SerialHandler *serial = new SerialHandler(); + + //Turn Left by driving the left motor only + + //motor 1 + serial->sendByteMC(SERIAL_START_BYTE); + serial->sendByteMC(SERIAL_DEVICE_TYPE); + serial->sendByteMC(SERIAL_MOTOR2_FORWARD); + serial->sendByteMC(SERIAL_CONST_SPEED); + +} +/* + * Moves the rover right, enabling right drive strength higher than left + */ +void mc_right(){ + SerialHandler *serial = new SerialHandler(); + + //Turn Right by driving right motor only + + //motor 1 + serial->sendByteMC(SERIAL_START_BYTE); + serial->sendByteMC(SERIAL_DEVICE_TYPE); + serial->sendByteMC(SERIAL_MOTOR3_FORWARD); + serial->sendByteMC(SERIAL_CONST_SPEED); +} + +//====MotorContoller +void mc_task(void *pdata) +{ + printf("Started Motor task\n"); + //mc_configure(); + while(1){ + mc_forward(); + + } + +} + +// ==== GENERAL + +void queue_init() { + ir_queue = OSQCreate((void**)&ir_messages, IR_MAX_MESSAGES); +} + +/* The main function creates the LCD task, registers the edge counter polling interrupt, + * and starts the OS. */ +int main(void) +{ + int status; + // Initialize components. + queue_init(); + + // Create the IR task. + OSTaskCreateExt(ir_task, + NULL, + &ir_task_stk[TASK_STACKSIZE - 1], + IR_TASK_PRIORITY, + IR_TASK_PRIORITY, + ir_task_stk, + TASK_STACKSIZE, + NULL, + 0); + + // Create the Wifi task. + OSTaskCreateExt(wifi_task, + NULL, + &wifi_task_stk[TASK_STACKSIZE - 1], + WIFI_TASK_PRIORITY, + WIFI_TASK_PRIORITY, + wifi_task_stk, + TASK_STACKSIZE, + NULL, + 0); + + // Create the MC task. + OSTaskCreateExt(mc_task, + NULL, + &mc_task_stk[TASK_STACKSIZE - 1], + MC_TASK_PRIORITY, + MC_TASK_PRIORITY, + mc_task_stk, + TASK_STACKSIZE, + NULL, + 0); + + // Register the IR pushbutton interrupt. + /*status = alt_ic_isr_register(PIO_KEY_LEFT_IRQ_INTERRUPT_CONTROLLER_ID, + PIO_KEY_LEFT_IRQ, + isr_on_ir_pushbutton, + NULL, + NULL);*/ + + // Enable key interrupts. + IOWR_ALTERA_AVALON_PIO_IRQ_MASK(PIO_KEY_LEFT_BASE, PIO_KEY_LEFT_CAPTURE); + + // Start. + if (status == OK) { + OSStart(); + } + + return 0; +} + +/****************************************************************************** + * * + * License Agreement * + * * + * Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * + * All rights reserved. * + * * + * Permission is hereby granted, free of charge, to any person obtaining a * + * copy of this software and associated documentation files (the "Software"), * + * to deal in the Software without restriction, including without limitation * + * the rights to use, copy, modify, merge, publish, distribute, sublicense, * + * and/or sell copies of the Software, and to permit persons to whom the * + * Software is furnished to do so, subject to the following conditions: * + * * + * The above copyright notice and this permission notice shall be included in * + * all copies or substantial portions of the Software. * + * * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * + * DEALINGS IN THE SOFTWARE. * + * * + * This agreement shall be governed in all respects by the laws of the State * + * of California and by the laws of the United States of America. * + * Altera does not recommend, suggest or require that this reference design * + * file be used in conjunction or combination with any other product. * + ******************************************************************************/ diff --git a/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.resources/.history/b1/3050599526a3001313d3adfc59d1f782 b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.resources/.history/b1/3050599526a3001313d3adfc59d1f782 new file mode 100644 index 00000000..7058cf8d --- /dev/null +++ b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.resources/.history/b1/3050599526a3001313d3adfc59d1f782 @@ -0,0 +1,119 @@ +/************************************************************************* +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. All use of this software and documentation is * +* subject to the License Agreement located at the end of this file below.* +************************************************************************** +* Description: * +* The following is a simple hello world program running MicroC/OS-II.The * +* purpose of the design is to be a very simple application that just * +* demonstrates MicroC/OS-II running on NIOS II.The design doesn't account* +* for issues such as checking system call return codes. etc. * +* * +* Requirements: * +* -Supported Example Hardware Platforms * +* Standard * +* Full Featured * +* Low Cost * +* -Supported Development Boards * +* Nios II Development Board, Stratix II Edition * +* Nios Development Board, Stratix Professional Edition * +* Nios Development Board, Stratix Edition * +* Nios Development Board, Cyclone Edition * +* -System Library Settings * +* RTOS Type - MicroC/OS-II * +* Periodic System Timer * +* -Know Issues * +* If this design is run on the ISS, terminal output will take several* +* minutes per iteration. * +**************************************************************************/ + + +#include +#include "includes.h" + +/* Definition of Task Stacks */ +#define TASK_STACKSIZE 2048 +OS_STK task1_stk[TASK_STACKSIZE]; +OS_STK task2_stk[TASK_STACKSIZE]; + +/* Definition of Task Priorities */ + +#define TASK1_PRIORITY 1 +#define TASK2_PRIORITY 2 + +/* Prints "Hello World" and sleeps for three seconds */ +void task1(void* pdata) +{ + while (1) + { + printf("Hello from task1\n"); + OSTimeDlyHMSM(0, 0, 3, 0); + } +} +/* Prints "Hello World" and sleeps for three seconds */ +void task2(void* pdata) +{ + while (1) + { + printf("Hello from task2\n"); + OSTimeDlyHMSM(0, 0, 3, 0); + } +} +/* The main function creates two task and starts multi-tasking */ +int main(void) +{ + + OSTaskCreateExt(task1, + NULL, + (void *)&task1_stk[TASK_STACKSIZE-1], + TASK1_PRIORITY, + TASK1_PRIORITY, + task1_stk, + TASK_STACKSIZE, + NULL, + 0); + + + OSTaskCreateExt(task2, + NULL, + (void *)&task2_stk[TASK_STACKSIZE-1], + TASK2_PRIORITY, + TASK2_PRIORITY, + task2_stk, + TASK_STACKSIZE, + NULL, + 0); + OSStart(); + return 0; +} + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ diff --git a/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.resources/.history/b6/5019524427a3001313d3adfc59d1f782 b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.resources/.history/b6/5019524427a3001313d3adfc59d1f782 new file mode 100644 index 00000000..e69de29b diff --git a/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.resources/.history/cb/9054c4c328a3001313d3adfc59d1f782 b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.resources/.history/cb/9054c4c328a3001313d3adfc59d1f782 new file mode 100644 index 00000000..97496df4 --- /dev/null +++ b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.resources/.history/cb/9054c4c328a3001313d3adfc59d1f782 @@ -0,0 +1,48 @@ +/* + * MotorHandler.cpp + * + * Created on: 2014-03-03 + * Author: gongal + */ + +#include "MotorHandler.h" +#include "includes.h" +#include "altera_avalon_uart_regs.h" + +MotorHandler::MotorHandler() { + // TODO Auto-generated constructor stub + +} + +MotorHandler::~MotorHandler() { + // TODO Auto-generated destructor stub +} +void MotorHandler::sendByteMC(char msg){ + IOWR_ALTERA_AVALON_UART_TXDATA(UART_MC_BASE, msg); +} + +void MotorHandler::mc_forward(){ + +} + +void MotorHandler::mc_backward(){ + +} + +void MotorHandler::mc_left(){ + +} + +void MotorHandler::mc_right(){ +} +void MotorHandler::mc_stop(){ + sendByteMC(MOTOR_START_BYTE); + sendByteMC(MOTOR_DEVICE_TYPE); + sendByteMC(MOTOR_MOTOR2_FORWARD); + sendByteMC(MOTOR_STOP_SPEED); + //motor 2 + sendByteMC(MOTOR_START_BYTE); + sendByteMC(MOTOR_DEVICE_TYPE); + sendByteMC(MOTOR_MOTOR3_FORWARD); + sendByteMC(MOTOR_STOP_SPEED); +} diff --git a/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.resources/.history/d6/20334f4427a3001313d3adfc59d1f782 b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.resources/.history/d6/20334f4427a3001313d3adfc59d1f782 new file mode 100644 index 00000000..e69de29b diff --git a/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.resources/.history/e4/10086dbe29a3001313d3adfc59d1f782 b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.resources/.history/e4/10086dbe29a3001313d3adfc59d1f782 new file mode 100644 index 00000000..13f666a5 --- /dev/null +++ b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.resources/.history/e4/10086dbe29a3001313d3adfc59d1f782 @@ -0,0 +1,219 @@ +/************************************************************************* + * ARCap + * Amshu Gongal, Kenan Kigunda + * February 18, 2014 + ************************************************************************** + * Description: * + * Prototype testing for infrared and wifi. + **************************************************************************/ + +#include +#include "includes.h" +#include "altera_avalon_pio_regs.h" +#include "altera_avalon_uart_regs.h" +#include "sys/alt_irq.h" +#include "alt_types.h" +#include "SerialHandler.h" +#include "MotorHandler.h" + +MotorHandler * motorHandler = new MotorHandler(); +/* Task stacks */ +#define TASK_STACKSIZE 2048 +OS_STK ir_task_stk[TASK_STACKSIZE]; +OS_STK wifi_task_stk[TASK_STACKSIZE]; +OS_STK mc_task_stk[TASK_STACKSIZE]; +/* Task priorities */ +#define IR_TASK_PRIORITY 1 +#define WIFI_TASK_PRIORITY 2 +#define MC_TASK_PRIORITY 2 + + +/* Error status */ +#define OK 0 + +/* Message queues */ +#define WAIT_FOREVER 0 + +// ==== INFRARED ==== + +/* Infrared message queue */ +#define IR_MAX_MESSAGES 4 +int ir_messages[IR_MAX_MESSAGES]; +OS_EVENT *ir_queue; + +/* Infrared messages */ +// Together these avoid passing 0 to the queue (which is not allowed since queue messages cannot be null) +// and invert pushbutton input (since the pushbutton returns 0 when it is pushed down). +#define IR_QUEUE_SEND_BASE 1 // Use: IR_QUEUE_SEND_BASE + IORD +#define IR_QUEUE_RECEIVE_BASE 2 // Use: IR_QUEUE_RECEIVE_BASE - OSQPend + + +/* Interrupt service routine triggered whenever the status of the IR emitter pushbutton changes. */ +static void isr_on_ir_pushbutton(void * context) { + // Read the state of the pushbutton and post it to the queue. + //printf("Pressed\n"); + int message = IR_QUEUE_SEND_BASE + IORD_ALTERA_AVALON_PIO_DATA(PIO_KEY_LEFT_BASE); + OSQPost(ir_queue, (void*)message); + // Mask to mark the end of the ISR. + IOWR_ALTERA_AVALON_PIO_EDGE_CAP(PIO_KEY_LEFT_BASE, PIO_KEY_LEFT_BIT_CLEARING_EDGE_REGISTER); +} + +/* Controllers the IR emitter based on the value of the pushbutton. */ +void ir_task(void* pdata) +{ + INT8U err; + while (1) + { + // Read the value from the queue. + int status = IR_QUEUE_RECEIVE_BASE - (int)OSQPend(ir_queue, WAIT_FOREVER, &err); + if (err == OS_NO_ERR) { + // Print the result and send it to the emitter. + printf("IR: %d\n", status); + IOWR_ALTERA_AVALON_PIO_DATA(PIO_IR_EMITTER_BASE, status); + } + } +} + +// ==== WIFI + +#define WIFI_GUARD_TIME 1 + +void wifi_wait() { + OSTimeDlyHMSM(0, 0, WIFI_GUARD_TIME, 0); +} + +void wifi_write(char *message, int length) { + int i; + for (i = 0; i < length; i++) { + IOWR_ALTERA_AVALON_UART_TXDATA(UART_WIFI_BASE, message[i]); + } +} + +void wifi_read() { + int status = IORD_ALTERA_AVALON_UART_STATUS(UART_WIFI_BASE); + printf("Wifi status: %d\n", status); + char c = IORD_ALTERA_AVALON_UART_RXDATA(UART_WIFI_BASE); + printf("Wifi: %c\n", c); +} + +void wifi_task(void *pdata) +{ + printf("Started wifi task\n"); + wifi_wait(); + wifi_write("+++", 3); + wifi_wait(); + wifi_read(); +} + + + +// ==== MC + + +//====MotorContoller +void mc_task(void *pdata) +{ + printf("Started Motor task\n"); + //mc_configure(); + while(1){ + mc_forward(); + + } + +} + +// ==== GENERAL + +void queue_init() { + ir_queue = OSQCreate((void**)&ir_messages, IR_MAX_MESSAGES); +} + +/* The main function creates the LCD task, registers the edge counter polling interrupt, + * and starts the OS. */ +int main(void) +{ + int status; + // Initialize components. + queue_init(); + + // Create the IR task. + OSTaskCreateExt(ir_task, + NULL, + &ir_task_stk[TASK_STACKSIZE - 1], + IR_TASK_PRIORITY, + IR_TASK_PRIORITY, + ir_task_stk, + TASK_STACKSIZE, + NULL, + 0); + + // Create the Wifi task. + OSTaskCreateExt(wifi_task, + NULL, + &wifi_task_stk[TASK_STACKSIZE - 1], + WIFI_TASK_PRIORITY, + WIFI_TASK_PRIORITY, + wifi_task_stk, + TASK_STACKSIZE, + NULL, + 0); + + // Create the MC task. + OSTaskCreateExt(mc_task, + NULL, + &mc_task_stk[TASK_STACKSIZE - 1], + MC_TASK_PRIORITY, + MC_TASK_PRIORITY, + mc_task_stk, + TASK_STACKSIZE, + NULL, + 0); + + // Register the IR pushbutton interrupt. + /*status = alt_ic_isr_register(PIO_KEY_LEFT_IRQ_INTERRUPT_CONTROLLER_ID, + PIO_KEY_LEFT_IRQ, + isr_on_ir_pushbutton, + NULL, + NULL);*/ + + // Enable key interrupts. + IOWR_ALTERA_AVALON_PIO_IRQ_MASK(PIO_KEY_LEFT_BASE, PIO_KEY_LEFT_CAPTURE); + + // Start. + if (status == OK) { + OSStart(); + } + + return 0; +} + +/****************************************************************************** + * * + * License Agreement * + * * + * Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * + * All rights reserved. * + * * + * Permission is hereby granted, free of charge, to any person obtaining a * + * copy of this software and associated documentation files (the "Software"), * + * to deal in the Software without restriction, including without limitation * + * the rights to use, copy, modify, merge, publish, distribute, sublicense, * + * and/or sell copies of the Software, and to permit persons to whom the * + * Software is furnished to do so, subject to the following conditions: * + * * + * The above copyright notice and this permission notice shall be included in * + * all copies or substantial portions of the Software. * + * * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * + * DEALINGS IN THE SOFTWARE. * + * * + * This agreement shall be governed in all respects by the laws of the State * + * of California and by the laws of the United States of America. * + * Altera does not recommend, suggest or require that this reference design * + * file be used in conjunction or combination with any other product. * + ******************************************************************************/ diff --git a/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.resources/.history/ef/403adbbd27a3001313d3adfc59d1f782 b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.resources/.history/ef/403adbbd27a3001313d3adfc59d1f782 new file mode 100644 index 00000000..34b19fa9 --- /dev/null +++ b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.resources/.history/ef/403adbbd27a3001313d3adfc59d1f782 @@ -0,0 +1,32 @@ +/* + * MotorHandler.h + * + * Created on: 2014-03-03 + * Author: gongal + */ + +#ifndef MOTORHANDLER_H_ +#define MOTORHANDLER_H_ +#define MOTOR_START_BYTE 0x80 + +#define MOTOR_DEVICE_TYPE 0x00 +#define MOTOR_MOTOR2_BACKWARD 0x04 // motor 2 backward +#define MOTOR_MOTOR3_BACKWARD 0x06 //motor 3 backward +#define MOTOR_MOTOR2_FORWARD 0x05 // motor 2 forward +#define MOTOR_MOTOR3_FORWARD 0x07 // motor 3 forward +#define MOTOR_CONST_SPEED 0x5F +#define MOTOR_STOP_SPEED 0x00 + +class MotorHandler { +public: + MotorHandler(); + virtual ~MotorHandler(); + void sendByteMC(char msg); + void mc_forward(); + void mc_backward; + void mc_right(); + void mc_left(); + void mc_stop(); +}; + +#endif /* MOTORHANDLER_H_ */ diff --git a/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.resources/.history/fb/f0ab07fd26a3001313d3adfc59d1f782 b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.resources/.history/fb/f0ab07fd26a3001313d3adfc59d1f782 new file mode 100644 index 00000000..00da470d --- /dev/null +++ b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.resources/.history/fb/f0ab07fd26a3001313d3adfc59d1f782 @@ -0,0 +1,382 @@ +/************************************************************************* + * ARCap + * Amshu Gongal, Kenan Kigunda + * February 18, 2014 + ************************************************************************** + * Description: * + * Prototype testing for infrared and wifi. + **************************************************************************/ + +#include +#include "includes.h" +#include "altera_avalon_pio_regs.h" +#include "altera_avalon_uart_regs.h" +#include "sys/alt_irq.h" +#include "alt_types.h" +#include "altera_up_avalon_rs232.h" +#include "altera_up_avalon_rs232_regs.h" +#include "SerialHandler.h" + + +/* Task stacks */ +#define TASK_STACKSIZE 2048 +OS_STK ir_task_stk[TASK_STACKSIZE]; +OS_STK wifi_task_stk[TASK_STACKSIZE]; +OS_STK mc_task_stk[TASK_STACKSIZE]; +/* Task priorities */ +#define IR_TASK_PRIORITY 1 +#define WIFI_TASK_PRIORITY 2 +#define MC_TASK_PRIORITY 2 + +#define SW_READ 1 +#define SW_WRITE 2 +#define WRITE_FIFO_EMPTY 0x80 +#define READ_FIFO_EMPTY 0x0 +OS_EVENT *SWQ; +OS_EVENT *RS232Q; +INT8U err; + + +/* Error status */ +#define OK 0 + +/* Message queues */ +#define WAIT_FOREVER 0 + +// ==== INFRARED ==== + +/* Infrared message queue */ +#define IR_MAX_MESSAGES 4 +int ir_messages[IR_MAX_MESSAGES]; +OS_EVENT *ir_queue; + +/* Infrared messages */ +// Together these avoid passing 0 to the queue (which is not allowed since queue messages cannot be null) +// and invert pushbutton input (since the pushbutton returns 0 when it is pushed down). +#define IR_QUEUE_SEND_BASE 1 // Use: IR_QUEUE_SEND_BASE + IORD +#define IR_QUEUE_RECEIVE_BASE 2 // Use: IR_QUEUE_RECEIVE_BASE - OSQPend + + +/* Interrupt service routine triggered whenever the status of the IR emitter pushbutton changes. */ +static void isr_on_ir_pushbutton(void * context) { + // Read the state of the pushbutton and post it to the queue. + //printf("Pressed\n"); + int message = IR_QUEUE_SEND_BASE + IORD_ALTERA_AVALON_PIO_DATA(PIO_KEY_LEFT_BASE); + OSQPost(ir_queue, (void*)message); + // Mask to mark the end of the ISR. + IOWR_ALTERA_AVALON_PIO_EDGE_CAP(PIO_KEY_LEFT_BASE, PIO_KEY_LEFT_BIT_CLEARING_EDGE_REGISTER); +} + +/* Controllers the IR emitter based on the value of the pushbutton. */ +void ir_task(void* pdata) +{ + INT8U err; + while (1) + { + // Read the value from the queue. + int status = IR_QUEUE_RECEIVE_BASE - (int)OSQPend(ir_queue, WAIT_FOREVER, &err); + if (err == OS_NO_ERR) { + // Print the result and send it to the emitter. + printf("IR: %d\n", status); + IOWR_ALTERA_AVALON_PIO_DATA(PIO_IR_EMITTER_BASE, status); + } + } +} + +// ==== WIFI + +#define WIFI_GUARD_TIME 1 + +void wifi_wait() { + OSTimeDlyHMSM(0, 0, WIFI_GUARD_TIME, 0); +} + +void wifi_write(char *message, int length) { + int i; + for (i = 0; i < length; i++) { + IOWR_ALTERA_AVALON_UART_TXDATA(UART_WIFI_BASE, message[i]); + } +} + +void wifi_read() { + //int status = IORD_ALTERA_AVALON_UART_STATUS(UART_WIFI_BASE); + //printf("Wifi status: %d\n", status); + char c = IORD_ALTERA_AVALON_UART_RXDATA(UART_WIFI_BASE); + + printf("Wifi: %c NE\n", c); +} + +void wifi_task(void *pdata) +{ + /*printf("Started wifi task\n"); + wifi_write("X", 1); + wifi_wait(); + wifi_write("+++", 3); + wifi_wait(); + wifi_read(); + wifi_wait(); + while(1){ + wifi_read(); + wifi_wait(); + }*/ + alt_u32 write_FIFO_space; + alt_u16 read_FIFO_used; + alt_u8 data_W8; + alt_u8 data_R8; + //int enter = 0; + alt_u8 p_error; + alt_up_rs232_dev* rs232_dev; + // open the RS232 UART port + rs232_dev = alt_up_rs232_open_dev("/dev/rs232_0"); + if (rs232_dev == NULL) + printf("Error: could not open RS232 UART\n"); + else + printf("Opened RS232 UART device\n"); + alt_up_rs232_disable_read_interrupt(rs232_dev); + data_W8 = 'X'; + alt_up_rs232_write_data(rs232_dev, data_W8); + OSTimeDlyHMSM(0, 0, 3, 0); + int i; + data_W8 = '+'; + for (i = 0; i<3; i++ ){ + write_FIFO_space = + alt_up_rs232_get_available_space_in_write_FIFO( + rs232_dev); + if (write_FIFO_space >= WRITE_FIFO_EMPTY) { + alt_up_rs232_write_data(rs232_dev, data_W8); + printf("write %c to RS232 UART\n", data_W8); + OSTimeDlyHMSM(0, 0, 1, 0); + } + } + alt_up_rs232_enable_read_interrupt(rs232_dev); + while(1){ + read_FIFO_used = alt_up_rs232_get_used_space_in_read_FIFO( + rs232_dev); + if (read_FIFO_used > READ_FIFO_EMPTY) { + printf("char stored in read_FIFO: %x\n", + read_FIFO_used); + alt_up_rs232_read_data(rs232_dev, &data_R8, &p_error); + printf("read %c from RS232 UART\n", data_R8); + } OSTimeDlyHMSM(0, 0, 1, 0); + } + /*while (1) { + int sw = (int) OSQPend(SWQ, 0, &err); + if (sw == SW_WRITE) { + alt_up_rs232_disable_read_interrupt(rs232_dev); + if (enter == 0) { + data_W8 = 'A'; + enter = 1; + } else if (enter == 1) { + data_W8 = '\n'; + enter = 0; + } write_FIFO_space = + alt_up_rs232_get_available_space_in_write_FIFO( + rs232_dev); + if (write_FIFO_space >= WRITE_FIFO_EMPTY) { + alt_up_rs232_write_data(rs232_dev, data_W8); + printf("write %c to RS232 UART\n", data_W8); + } OSTimeDlyHMSM(0, 0, 1, 0); + alt_up_rs232_enable_read_interrupt(rs232_dev); + } if ( + sw == SW_READ) { + read_FIFO_used = alt_up_rs232_get_used_space_in_read_FIFO( + rs232_dev); + if (read_FIFO_used > READ_FIFO_EMPTY) { + printf("char stored in read_FIFO: %x\n", + read_FIFO_used); + alt_up_rs232_read_data(rs232_dev, &data_R8, &p_error); + printf("read %c from RS232 UART\n", data_R8); + } OSTimeDlyHMSM(0, 0, 1, 0); + } + }*/ + +} + + + +// ==== MC + +void mc_stop(){ + SerialHandler *serial = new SerialHandler(); + //motor 1 + serial->sendByteMC(SERIAL_START_BYTE); + serial->sendByteMC(SERIAL_DEVICE_TYPE); + serial->sendByteMC(SERIAL_MOTOR2_FORWARD); + serial->sendByteMC(SERIAL_STOP_SPEED); + //motor 2 + serial->sendByteMC(SERIAL_START_BYTE); + serial->sendByteMC(SERIAL_DEVICE_TYPE); + serial->sendByteMC(SERIAL_MOTOR3_FORWARD); + serial->sendByteMC(SERIAL_STOP_SPEED); +} +/* + * Moves the rover forward enabling equal drive strength on both motors + */ +void mc_forward(){ + SerialHandler *serial = new SerialHandler(); + //motor 1 + serial->sendByteMC(SERIAL_START_BYTE); + serial->sendByteMC(SERIAL_DEVICE_TYPE); + serial->sendByteMC(SERIAL_MOTOR2_FORWARD); + serial->sendByteMC(SERIAL_CONST_SPEED); + //motor 2 + serial->sendByteMC(SERIAL_START_BYTE); + serial->sendByteMC(SERIAL_DEVICE_TYPE); + serial->sendByteMC(SERIAL_MOTOR3_FORWARD); + serial->sendByteMC(SERIAL_CONST_SPEED); + +} +/* + * Moves the rover backward enabling equal drive strength on both motors + */ +void mc_backward(){ + SerialHandler *serial = new SerialHandler(); + + //motor 1 + serial->sendByteMC(SERIAL_START_BYTE); + serial->sendByteMC(SERIAL_DEVICE_TYPE); + serial->sendByteMC(SERIAL_MOTOR2_BACKWARD); + serial->sendByteMC(SERIAL_CONST_SPEED); + //motor 2 + serial->sendByteMC(SERIAL_START_BYTE); + serial->sendByteMC(SERIAL_DEVICE_TYPE); + serial->sendByteMC(SERIAL_MOTOR3_BACKWARD); + serial->sendByteMC(SERIAL_CONST_SPEED); +} +/* + * Moves the rover left, enabling left drive strength higher than right + */ +void mc_left(){ + SerialHandler *serial = new SerialHandler(); + + //Turn Left by driving the left motor only + + //motor 1 + serial->sendByteMC(SERIAL_START_BYTE); + serial->sendByteMC(SERIAL_DEVICE_TYPE); + serial->sendByteMC(SERIAL_MOTOR2_FORWARD); + serial->sendByteMC(SERIAL_CONST_SPEED); + +} +/* + * Moves the rover right, enabling right drive strength higher than left + */ +void mc_right(){ + SerialHandler *serial = new SerialHandler(); + + //Turn Right by driving right motor only + + //motor 1 + serial->sendByteMC(SERIAL_START_BYTE); + serial->sendByteMC(SERIAL_DEVICE_TYPE); + serial->sendByteMC(SERIAL_MOTOR3_FORWARD); + serial->sendByteMC(SERIAL_CONST_SPEED); +} + +//====MotorContoller +void mc_task(void *pdata) +{ + printf("Started Motor task\n"); + //mc_configure(); + while(1){ + mc_forward(); + + } + +} + +// ==== GENERAL + +void queue_init() { + ir_queue = OSQCreate((void**)&ir_messages, IR_MAX_MESSAGES); +} + +/* The main function creates the LCD task, registers the edge counter polling interrupt, + * and starts the OS. */ +int main(void) +{ + int status; + // Initialize components. + queue_init(); + + // Create the IR task. + OSTaskCreateExt(ir_task, + NULL, + &ir_task_stk[TASK_STACKSIZE - 1], + IR_TASK_PRIORITY, + IR_TASK_PRIORITY, + ir_task_stk, + TASK_STACKSIZE, + NULL, + 0); + + // Create the Wifi task. + OSTaskCreateExt(wifi_task, + NULL, + &wifi_task_stk[TASK_STACKSIZE - 1], + WIFI_TASK_PRIORITY, + WIFI_TASK_PRIORITY, + wifi_task_stk, + TASK_STACKSIZE, + NULL, + 0); + + // Create the MC task. + OSTaskCreateExt(mc_task, + NULL, + &mc_task_stk[TASK_STACKSIZE - 1], + MC_TASK_PRIORITY, + MC_TASK_PRIORITY, + mc_task_stk, + TASK_STACKSIZE, + NULL, + 0); + + // Register the IR pushbutton interrupt. + /*status = alt_ic_isr_register(PIO_KEY_LEFT_IRQ_INTERRUPT_CONTROLLER_ID, + PIO_KEY_LEFT_IRQ, + isr_on_ir_pushbutton, + NULL, + NULL);*/ + + // Enable key interrupts. + IOWR_ALTERA_AVALON_PIO_IRQ_MASK(PIO_KEY_LEFT_BASE, PIO_KEY_LEFT_CAPTURE); + + // Start. + if (status == OK) { + OSStart(); + } + + return 0; +} + +/****************************************************************************** + * * + * License Agreement * + * * + * Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * + * All rights reserved. * + * * + * Permission is hereby granted, free of charge, to any person obtaining a * + * copy of this software and associated documentation files (the "Software"), * + * to deal in the Software without restriction, including without limitation * + * the rights to use, copy, modify, merge, publish, distribute, sublicense, * + * and/or sell copies of the Software, and to permit persons to whom the * + * Software is furnished to do so, subject to the following conditions: * + * * + * The above copyright notice and this permission notice shall be included in * + * all copies or substantial portions of the Software. * + * * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * + * DEALINGS IN THE SOFTWARE. * + * * + * This agreement shall be governed in all respects by the laws of the State * + * of California and by the laws of the United States of America. * + * Altera does not recommend, suggest or require that this reference design * + * file be used in conjunction or combination with any other product. * + ******************************************************************************/ diff --git a/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.resources/.projects/MCTest/.indexes/history.index b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.resources/.projects/MCTest/.indexes/history.index new file mode 100644 index 00000000..12566347 Binary files /dev/null and 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a/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.resources/.projects/MCandWifiTestDE0/.markers b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.resources/.projects/MCandWifiTestDE0/.markers deleted file mode 100644 index f760e06e..00000000 Binary files a/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.resources/.projects/MCandWifiTestDE0/.markers and /dev/null differ diff --git a/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.resources/.projects/MCandWifiTestDE0_bsp/.indexes/properties.index b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.resources/.projects/MCandWifiTestDE0_bsp/.indexes/properties.index deleted file mode 100644 index 32725d96..00000000 Binary files a/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.resources/.projects/MCandWifiTestDE0_bsp/.indexes/properties.index and /dev/null differ diff --git a/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.resources/.root/1.tree b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.resources/.root/1.tree deleted file mode 100644 index bee1da99..00000000 Binary files a/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.resources/.root/1.tree and /dev/null differ diff --git a/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.resources/.root/2.tree b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.resources/.root/2.tree new file mode 100644 index 00000000..25f5efd0 Binary files /dev/null and b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.resources/.root/2.tree differ diff --git a/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.resources/.safetable/org.eclipse.core.resources b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.resources/.safetable/org.eclipse.core.resources index 8582b60f..df572ee9 100644 Binary files a/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.resources/.safetable/org.eclipse.core.resources and b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.resources/.safetable/org.eclipse.core.resources differ diff --git a/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.runtime/.settings/com.altera.sbtgui.ui.prefs b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.runtime/.settings/com.altera.sbtgui.ui.prefs index 5017c9ce..c1bda6de 100644 --- a/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.runtime/.settings/com.altera.sbtgui.ui.prefs +++ b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.runtime/.settings/com.altera.sbtgui.ui.prefs @@ -1,4 +1,4 @@ eclipse.preferences.version=1 -newSoftwareExampleWizardPage.defaultLocation=C\:\\Users\\gongal\\NewRepARCap\\MCandWifiTestDE0\\software\\MCandWifiTestDE0 +newSoftwareExampleWizardPage.defaultLocation=C\:\\Users\\gongal\\NewRepARCap\\MCandWifiTestDE0\\software\\MCTest newSoftwareExampleWizardPage.sopcinfoFile=C\:\\Users\\gongal\\NewRepARCap\\MCandWifiTestDE0\\system.sopcinfo -newSoftwareExampleWizardPage2.newBspLocation=C\:\\Users\\gongal\\NewRepARCap\\MCandWifiTestDE0\\software\\MCandWifiTestDE0_bsp +newSoftwareExampleWizardPage2.newBspLocation=C\:\\Users\\gongal\\NewRepARCap\\MCandWifiTestDE0\\software\\MCTest_bsp diff --git a/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.core.prj-MCTest.prefs b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.core.prj-MCTest.prefs new file mode 100644 index 00000000..9c00dc4e --- /dev/null +++ b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.core.prj-MCTest.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +indexer/preferenceScope=0 diff --git a/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.core.prj-MCTest_bsp.prefs b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.core.prj-MCTest_bsp.prefs new file mode 100644 index 00000000..9c00dc4e --- /dev/null +++ b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.core.prj-MCTest_bsp.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +indexer/preferenceScope=0 diff --git a/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.managedbuilder.core.prefs b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.managedbuilder.core.prefs index 596de9b9..3cbe6f2d 100644 --- a/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.managedbuilder.core.prefs +++ b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.managedbuilder.core.prefs @@ -1,3 +1,3 @@ eclipse.preferences.version=1 -properties/MCandWifiTestDE0.null.2048604785/preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.459540740=\#\r\n\#Sun Mar 02 19\:05\:30 MST 2014\r\norg.eclipse.cdt.build.core.settings.holder.libs.451701326\=\\\#\\r\\n\\\#Sun Mar 02 19\\\:05\\\:07 MST 2014\\r\\nrebuildState\\\=true\\r\\n\r\npreference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.459540740\=\\\#\\r\\n\\\#Sun Mar 02 19\\\:05\\\:07 MST 2014\\r\\nrcState\\\=0\\r\\nrebuildState\\\=false\\r\\n\r\norg.eclipse.cdt.build.core.settings.holder.690456977\=\\\#\\r\\n\\\#Sun Mar 02 19\\\:05\\\:07 MST 2014\\r\\nrebuildState\\\=true\\r\\n\r\ncdt.managedbuild.tool.gnu.c.compiler.cygwin.base.1487972840\=\\\#\\r\\n\\\#Sun Mar 02 19\\\:05\\\:30 MST 2014\\r\\nrebuildState\\\=false\\r\\n\r\norg.eclipse.cdt.build.core.settings.holder.1255428628\=\\\#\\r\\n\\\#Sun Mar 02 19\\\:05\\\:07 MST 2014\\r\\nrebuildState\\\=true\\r\\n\r\ncdt.managedbuild.tool.gnu.cpp.linker.cygwin.base.371287252\=\\\#\\r\\n\\\#Sun Mar 02 19\\\:05\\\:30 MST 2014\\r\\nrebuildState\\\=false\\r\\n\r\ncdt.managedbuild.tool.gnu.c.linker.cygwin.base.1992340947\=\\\#\\r\\n\\\#Sun Mar 02 19\\\:05\\\:30 MST 2014\\r\\nrebuildState\\\=false\\r\\n\r\naltera.nios2.mingw.gcc4.424500458\=\\\#\\r\\n\\\#Sun Mar 02 19\\\:05\\\:30 MST 2014\\r\\nrebuildState\\\=false\\r\\n\r\ncdt.managedbuild.tool.gnu.cpp.compiler.cygwin.base.1646161981\=\\\#\\r\\n\\\#Sun Mar 02 19\\\:05\\\:30 MST 2014\\r\\nrebuildState\\\=false\\r\\n\r\norg.eclipse.cdt.build.core.prefbase.toolchain.328453478\=\\\#\\r\\n\\\#Sun Mar 02 19\\\:05\\\:07 MST 2014\\r\\nrebuildState\\\=true\\r\\n\r\norg.eclipse.cdt.build.core.settings.holder.1830629771\=\\\#\\r\\n\\\#Sun Mar 02 19\\\:05\\\:07 MST 2014\\r\\nrebuildState\\\=true\\r\\n\r\ncdt.managedbuild.tool.gnu.assembler.cygwin.base.585441518\=\\\#\\r\\n\\\#Sun Mar 02 19\\\:05\\\:30 MST 2014\\r\\nrebuildState\\\=false\\r\\n\r\ncdt.managedbuild.tool.gnu.archiver.cygwin.base.547399205\=\\\#\\r\\n\\\#Sun Mar 02 19\\\:05\\\:30 MST 2014\\r\\nrebuildState\\\=false\\r\\n\r\n -properties/MCandWifiTestDE0_bsp.null.749359776/preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.752639680=\#\r\n\#Sun Mar 02 19\:05\:30 MST 2014\r\norg.eclipse.cdt.build.core.prefbase.toolchain.372835622\=\\\#\\r\\n\\\#Sun Mar 02 19\\\:03\\\:53 MST 2014\\r\\nrebuildState\\\=true\\r\\n\r\ncdt.managedbuild.tool.gnu.assembler.cygwin.base.917599007\=\\\#\\r\\n\\\#Sun Mar 02 19\\\:05\\\:30 MST 2014\\r\\nrebuildState\\\=false\\r\\n\r\naltera.nios2.mingw.gcc4.118178447\=\\\#\\r\\n\\\#Sun Mar 02 19\\\:05\\\:30 MST 2014\\r\\nrebuildState\\\=false\\r\\n\r\ncdt.managedbuild.tool.gnu.archiver.cygwin.base.1165260459\=\\\#\\r\\n\\\#Sun Mar 02 19\\\:05\\\:30 MST 2014\\r\\nrebuildState\\\=false\\r\\n\r\ncdt.managedbuild.tool.gnu.cpp.compiler.cygwin.base.626732464\=\\\#\\r\\n\\\#Sun Mar 02 19\\\:05\\\:30 MST 2014\\r\\nrebuildState\\\=false\\r\\n\r\ncdt.managedbuild.tool.gnu.c.compiler.cygwin.base.2047966330\=\\\#\\r\\n\\\#Sun Mar 02 19\\\:05\\\:30 MST 2014\\r\\nrebuildState\\\=false\\r\\n\r\npreference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.752639680\=\\\#\\r\\n\\\#Sun Mar 02 19\\\:05\\\:30 MST 2014\\r\\nrcState\\\=0\\r\\nrebuildState\\\=false\\r\\n\r\ncdt.managedbuild.tool.gnu.cpp.linker.cygwin.base.515288906\=\\\#\\r\\n\\\#Sun Mar 02 19\\\:05\\\:30 MST 2014\\r\\nrebuildState\\\=false\\r\\n\r\norg.eclipse.cdt.build.core.settings.holder.1602105706\=\\\#\\r\\n\\\#Sun Mar 02 19\\\:03\\\:53 MST 2014\\r\\nrebuildState\\\=true\\r\\n\r\norg.eclipse.cdt.build.core.settings.holder.1619183613\=\\\#\\r\\n\\\#Sun Mar 02 19\\\:03\\\:53 MST 2014\\r\\nrebuildState\\\=true\\r\\n\r\norg.eclipse.cdt.build.core.settings.holder.libs.434744816\=\\\#\\r\\n\\\#Sun Mar 02 19\\\:03\\\:53 MST 2014\\r\\nrebuildState\\\=true\\r\\n\r\ncdt.managedbuild.tool.gnu.c.linker.cygwin.base.1366324204\=\\\#\\r\\n\\\#Sun Mar 02 19\\\:05\\\:30 MST 2014\\r\\nrebuildState\\\=false\\r\\n\r\norg.eclipse.cdt.build.core.settings.holder.1222645464\=\\\#\\r\\n\\\#Sun Mar 02 19\\\:03\\\:53 MST 2014\\r\\nrebuildState\\\=true\\r\\n\r\n +properties/MCTest.null.6599381/preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1672650292=\#\r\n\#Mon Mar 03 16\:28\:34 MST 2014\r\ncdt.managedbuild.tool.gnu.c.compiler.cygwin.base.2135636462\=\\\#\\r\\n\\\#Mon Mar 03 16\\\:28\\\:34 MST 2014\\r\\nrebuildState\\\=false\\r\\n\r\ncdt.managedbuild.tool.gnu.cpp.linker.cygwin.base.1544796675\=\\\#\\r\\n\\\#Mon Mar 03 16\\\:28\\\:34 MST 2014\\r\\nrebuildState\\\=false\\r\\n\r\ncdt.managedbuild.tool.gnu.cpp.compiler.cygwin.base.1586168093\=\\\#\\r\\n\\\#Mon Mar 03 16\\\:28\\\:34 MST 2014\\r\\nrebuildState\\\=false\\r\\n\r\ncdt.managedbuild.tool.gnu.c.linker.cygwin.base.610709070\=\\\#\\r\\n\\\#Mon Mar 03 16\\\:28\\\:34 MST 2014\\r\\nrebuildState\\\=false\\r\\n\r\norg.eclipse.cdt.build.core.settings.holder.1527117319\=\\\#\\r\\n\\\#Mon Mar 03 15\\\:53\\\:23 MST 2014\\r\\nrebuildState\\\=true\\r\\n\r\ncdt.managedbuild.tool.gnu.archiver.cygwin.base.1030107572\=\\\#\\r\\n\\\#Mon Mar 03 16\\\:28\\\:34 MST 2014\\r\\nrebuildState\\\=false\\r\\n\r\norg.eclipse.cdt.build.core.settings.holder.libs.42402407\=\\\#\\r\\n\\\#Mon Mar 03 15\\\:53\\\:23 MST 2014\\r\\nrebuildState\\\=true\\r\\n\r\norg.eclipse.cdt.build.core.settings.holder.893551288\=\\\#\\r\\n\\\#Mon Mar 03 15\\\:53\\\:23 MST 2014\\r\\nrebuildState\\\=true\\r\\n\r\npreference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1672650292\=\\\#\\r\\n\\\#Mon Mar 03 16\\\:25\\\:20 MST 2014\\r\\nrcState\\\=0\\r\\nrebuildState\\\=false\\r\\n\r\norg.eclipse.cdt.build.core.settings.holder.852731332\=\\\#\\r\\n\\\#Mon Mar 03 15\\\:53\\\:23 MST 2014\\r\\nrebuildState\\\=true\\r\\n\r\ncdt.managedbuild.tool.gnu.assembler.cygwin.base.262382352\=\\\#\\r\\n\\\#Mon Mar 03 16\\\:28\\\:34 MST 2014\\r\\nrebuildState\\\=false\\r\\n\r\norg.eclipse.cdt.build.core.prefbase.toolchain.1703072789\=\\\#\\r\\n\\\#Mon Mar 03 15\\\:53\\\:23 MST 2014\\r\\nrebuildState\\\=true\\r\\n\r\naltera.nios2.mingw.gcc4.1152019966\=\\\#\\r\\n\\\#Mon Mar 03 16\\\:28\\\:34 MST 2014\\r\\nrebuildState\\\=false\\r\\n\r\n +properties/MCTest_bsp.null.366760473/preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.384331160=\#\r\n\#Mon Mar 03 16\:26\:33 MST 2014\r\norg.eclipse.cdt.build.core.settings.holder.993149497\=\\\#\\r\\n\\\#Mon Mar 03 15\\\:52\\\:41 MST 2014\\r\\nrebuildState\\\=true\\r\\n\r\ncdt.managedbuild.tool.gnu.cpp.linker.cygwin.base.789358110\=\\\#\\r\\n\\\#Mon Mar 03 16\\\:26\\\:33 MST 2014\\r\\nrebuildState\\\=false\\r\\n\r\ncdt.managedbuild.tool.gnu.c.compiler.cygwin.base.365106348\=\\\#\\r\\n\\\#Mon Mar 03 16\\\:26\\\:33 MST 2014\\r\\nrebuildState\\\=false\\r\\n\r\ncdt.managedbuild.tool.gnu.cpp.compiler.cygwin.base.647937411\=\\\#\\r\\n\\\#Mon Mar 03 16\\\:26\\\:33 MST 2014\\r\\nrebuildState\\\=false\\r\\n\r\ncdt.managedbuild.tool.gnu.archiver.cygwin.base.408906753\=\\\#\\r\\n\\\#Mon Mar 03 16\\\:26\\\:33 MST 2014\\r\\nrebuildState\\\=false\\r\\n\r\naltera.nios2.mingw.gcc4.593727225\=\\\#\\r\\n\\\#Mon Mar 03 16\\\:26\\\:33 MST 2014\\r\\nrebuildState\\\=false\\r\\n\r\norg.eclipse.cdt.build.core.settings.holder.683608666\=\\\#\\r\\n\\\#Mon Mar 03 15\\\:52\\\:41 MST 2014\\r\\nrebuildState\\\=true\\r\\n\r\norg.eclipse.cdt.build.core.settings.holder.1281151653\=\\\#\\r\\n\\\#Mon Mar 03 15\\\:52\\\:41 MST 2014\\r\\nrebuildState\\\=true\\r\\n\r\ncdt.managedbuild.tool.gnu.c.linker.cygwin.base.594178246\=\\\#\\r\\n\\\#Mon Mar 03 16\\\:26\\\:33 MST 2014\\r\\nrebuildState\\\=false\\r\\n\r\npreference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.384331160\=\\\#\\r\\n\\\#Mon Mar 03 16\\\:25\\\:41 MST 2014\\r\\nrcState\\\=0\\r\\nrebuildState\\\=false\\r\\n\r\ncdt.managedbuild.tool.gnu.assembler.cygwin.base.1612130313\=\\\#\\r\\n\\\#Mon Mar 03 16\\\:26\\\:33 MST 2014\\r\\nrebuildState\\\=false\\r\\n\r\norg.eclipse.cdt.build.core.prefbase.toolchain.2069924582\=\\\#\\r\\n\\\#Mon Mar 03 15\\\:52\\\:41 MST 2014\\r\\nrebuildState\\\=true\\r\\n\r\norg.eclipse.cdt.build.core.settings.holder.libs.1800971593\=\\\#\\r\\n\\\#Mon Mar 03 15\\\:52\\\:41 MST 2014\\r\\nrebuildState\\\=true\\r\\n\r\n diff --git a/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.debug.ui.prefs b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.debug.ui.prefs index 98d8634a..4e59cdd7 100644 --- a/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.debug.ui.prefs +++ b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.debug.ui.prefs @@ -1,2 +1,3 @@ eclipse.preferences.version=1 org.eclipse.debug.ui.PREF_LAUNCH_PERSPECTIVES=\r\n\r\n +preferredTargets=org.eclipse.cdt.debug.ui.toggleCBreakpointTarget\:org.eclipse.cdt.debug.ui.toggleCBreakpointTarget| diff --git a/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.epp.usagedata.recording.prefs b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.epp.usagedata.recording.prefs index 76298396..62a774d1 100644 --- a/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.epp.usagedata.recording.prefs +++ b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.epp.usagedata.recording.prefs @@ -1,2 +1,2 @@ eclipse.preferences.version=1 -org.eclipse.epp.usagedata.recording.last-upload=1393812198904 +org.eclipse.epp.usagedata.recording.last-upload=1393887079586 diff --git a/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.ide.prefs b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.ide.prefs index 97d74754..744ba143 100644 --- a/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.ide.prefs +++ b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.ide.prefs @@ -1,3 +1,5 @@ +IMPORT_FILES_AND_FOLDERS_RELATIVE=true +IMPORT_FILES_AND_FOLDERS_TYPE=23,1 PROBLEMS_FILTERS_MIGRATE=true eclipse.preferences.version=1 platformState=1370561326246 diff --git a/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.debug.core/.launches/MCTest Nios II Hardware configuration.launch b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.debug.core/.launches/MCTest Nios II Hardware configuration.launch new file mode 100644 index 00000000..63693e87 --- /dev/null +++ b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.debug.core/.launches/MCTest Nios II Hardware configuration.launch @@ -0,0 +1,17 @@ + + + + + + + + + + + + + + + + + diff --git a/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.debug.core/.launches/MCandWifiTestDE0 Nios II Hardware configuration.launch b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.debug.core/.launches/MCandWifiTestDE0 Nios II Hardware configuration.launch deleted file mode 100644 index a17c7aad..00000000 --- a/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.debug.core/.launches/MCandWifiTestDE0 Nios II Hardware configuration.launch +++ /dev/null @@ -1,17 +0,0 @@ - - - - - - - - - - - - - - - - - diff --git a/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.debug.ui/dialog_settings.xml b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.debug.ui/dialog_settings.xml index 0c8f5ee7..59e636de 100644 --- a/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.debug.ui/dialog_settings.xml +++ b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.debug.ui/dialog_settings.xml @@ -1,11 +1,11 @@
- + - + - +
diff --git a/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.epp.usagedata.recording/upload0.csv b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.epp.usagedata.recording/upload0.csv new file mode 100644 index 00000000..f27f8ffb --- /dev/null +++ b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.epp.usagedata.recording/upload0.csv @@ -0,0 +1,276 @@ +what,kind,bundleId,bundleVersion,description,time +activated,perspective,com.altera.sbtgui.ui,,"com.altera.sbtgui.ui.cPerspective",1393887078502 +started,bundle,org.eclipse.osgi,3.7.2.v20120110-1415,"org.eclipse.osgi",1393887078503 +started,bundle,org.eclipse.equinox.simpleconfigurator,1.0.200.v20110815-1438,"org.eclipse.equinox.simpleconfigurator",1393887078504 +started,bundle,com.ibm.icu,4.4.2.v20110823,"com.ibm.icu",1393887078504 +started,bundle,org.eclipse.cdt.codan.checkers,1.0.1.201202111925,"org.eclipse.cdt.codan.checkers",1393887078504 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a/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/.workspace/2014/3/10/refactorings.index b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/.workspace/2014/3/10/refactorings.index new file mode 100644 index 00000000..26c9bf14 --- /dev/null +++ b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/.workspace/2014/3/10/refactorings.index @@ -0,0 +1,2 @@ +1393887186110 Delete resource 'MCTest/hello_ucosii.c' +1393888568322 Delete 2 resources diff --git a/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.ltk.ui.refactoring/dialog_settings.xml b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.ltk.ui.refactoring/dialog_settings.xml new file mode 100644 index 00000000..27eb4040 --- /dev/null +++ b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.ltk.ui.refactoring/dialog_settings.xml @@ -0,0 +1,7 @@ + +
+
+ + +
+
diff --git a/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.ui.ide/dialog_settings.xml b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.ui.ide/dialog_settings.xml new file mode 100644 index 00000000..7d61333c --- /dev/null +++ b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.ui.ide/dialog_settings.xml @@ -0,0 +1,12 @@ + +
+
+ + + + + + + +
+
diff --git a/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.ui.workbench.texteditor/dialog_settings.xml b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.ui.workbench.texteditor/dialog_settings.xml new file mode 100644 index 00000000..6dfc7a30 --- /dev/null +++ b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.ui.workbench.texteditor/dialog_settings.xml @@ -0,0 +1,27 @@ + +
+
+ + + + + +
+
+ + + + + + + + + + + + + + + +
+
diff --git a/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.ui.workbench/dialog_settings.xml b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.ui.workbench/dialog_settings.xml index 5ca0b776..30f05281 100644 --- a/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.ui.workbench/dialog_settings.xml +++ b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.ui.workbench/dialog_settings.xml @@ -1,3 +1,8 @@
+
+ + + +
diff --git a/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.ui.workbench/workbench.xml b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.ui.workbench/workbench.xml index e9ee58a5..d8de7f75 100644 --- a/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.ui.workbench/workbench.xml +++ b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.ui.workbench/workbench.xml @@ -1,7 +1,7 @@ - + - + @@ -23,20 +23,30 @@ - + + + - - - + + + + + + + + + + + @@ -47,9 +57,6 @@ - - - @@ -143,52 +150,38 @@ - - - - - + - - + - - - + - - + - - - + - - + - - - + - - + @@ -231,25 +224,17 @@ + + + + + - - - - - - + - - - - - - - - @@ -264,7 +249,7 @@ - + @@ -274,20 +259,27 @@ - - - - + + + + + - - + + + + + + - - - - + + + + + + @@ -297,10 +289,161 @@ - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - + @@ -309,8 +452,7 @@ - - + @@ -320,13 +462,24 @@ - - - + + + + + + + + + + + + + + \ No newline at end of file diff --git a/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.ui.workbench/workingsets.xml b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.ui.workbench/workingsets.xml index 041b417d..8047a80c 100644 --- a/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.ui.workbench/workingsets.xml +++ b/MCandWifiTestDE0/Software/.metadata/.plugins/org.eclipse.ui.workbench/workingsets.xml @@ -1,4 +1,4 @@ - + \ No newline at end of file diff --git a/MCandWifiTestDE0/Software/Archive/MCTest/.cproject b/MCandWifiTestDE0/Software/Archive/MCTest/.cproject new file mode 100644 index 00000000..60e18a6c --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest/.cproject @@ -0,0 +1,508 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + make + + mem_init_install + true + false + false + + + make + + mem_init_generate + true + false + false + + + make + + help + true + false + false + + + + diff --git a/MCandWifiTestDE0/Software/Archive/MCTest/.force_relink b/MCandWifiTestDE0/Software/Archive/MCTest/.force_relink new file mode 100644 index 00000000..e69de29b diff --git a/MCandWifiTestDE0/Software/Archive/MCTest/.project b/MCandWifiTestDE0/Software/Archive/MCTest/.project new file mode 100644 index 00000000..40854e92 --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest/.project @@ -0,0 +1,96 @@ + + + MCTest + + + + + + com.altera.sbtgui.project.makefileBuilder + + + + + com.altera.sbtgui.project.makefileBuilder + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + + + + org.eclipse.cdt.make.core.buildCommand + make + + + org.eclipse.cdt.make.core.buildLocation + ${workspace_loc://MCTest} + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + org.eclipse.cdt.core.ccnature + com.altera.sbtgui.project.SBTGUINature + com.altera.sbtgui.project.SBTGUIAppNature + com.altera.sbtgui.project.SBTGUIManagedNature + + diff --git a/MCandWifiTestDE0/Software/Archive/MCTest/MCTest.elf b/MCandWifiTestDE0/Software/Archive/MCTest/MCTest.elf new file mode 100644 index 00000000..88e5dc8b Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest/MCTest.elf differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest/MCTest.map b/MCandWifiTestDE0/Software/Archive/MCTest/MCTest.map new file mode 100644 index 00000000..c74964d5 --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest/MCTest.map @@ -0,0 +1,3339 @@ +Archive member included because of file (symbol) + +c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(class_type_info.o) + obj/default/MotorHandler.o (vtable for __cxxabiv1::__class_type_info) +c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(eh_personality.o) + obj/default/main.o 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c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-signalr.o) (kill) +../MCTest_bsp/\libucosii_bsp.a(alt_load.o) + ../MCTest_bsp//obj/HAL/src/crt0.o (alt_load) +../MCTest_bsp/\libucosii_bsp.a(alt_lseek.o) + c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-lseekr.o) (lseek) +../MCTest_bsp/\libucosii_bsp.a(alt_main.o) + ../MCTest_bsp//obj/HAL/src/crt0.o (alt_main) +../MCTest_bsp/\libucosii_bsp.a(alt_read.o) + c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-readr.o) (read) +../MCTest_bsp/\libucosii_bsp.a(alt_release_fd.o) + ../MCTest_bsp/\libucosii_bsp.a(alt_close.o) (alt_release_fd) +../MCTest_bsp/\libucosii_bsp.a(alt_sbrk.o) + c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-sbrkr.o) (sbrk) +../MCTest_bsp/\libucosii_bsp.a(alt_write.o) + c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-writer.o) (write) +../MCTest_bsp/\libucosii_bsp.a(alt_env_lock.o) + ../MCTest_bsp/\libucosii_bsp.a(alt_main.o) (alt_envsem) +../MCTest_bsp/\libucosii_bsp.a(alt_malloc_lock.o) + c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-mallocr.o) (__malloc_lock) +../MCTest_bsp/\libucosii_bsp.a(os_core.o) + ../MCTest_bsp/\libucosii_bsp.a(alt_main.o) (OSInit) +../MCTest_bsp/\libucosii_bsp.a(os_dbg.o) + ../MCTest_bsp/\libucosii_bsp.a(os_core.o) (OSDebugInit) +../MCTest_bsp/\libucosii_bsp.a(os_flag.o) + ../MCTest_bsp/\libucosii_bsp.a(os_core.o) (OS_FlagInit) +../MCTest_bsp/\libucosii_bsp.a(os_mem.o) + ../MCTest_bsp/\libucosii_bsp.a(os_core.o) (OS_MemInit) +../MCTest_bsp/\libucosii_bsp.a(os_q.o) + obj/default/main.o (OSQCreate) +../MCTest_bsp/\libucosii_bsp.a(os_sem.o) + ../MCTest_bsp/\libucosii_bsp.a(alt_main.o) (OSSemCreate) +../MCTest_bsp/\libucosii_bsp.a(os_task.o) + obj/default/main.o (OSTaskCreateExt) +../MCTest_bsp/\libucosii_bsp.a(os_time.o) + ../MCTest_bsp/\libucosii_bsp.a(os_core.o) (OSTimeDly) +../MCTest_bsp/\libucosii_bsp.a(alt_sys_init.o) + ../MCTest_bsp/\libucosii_bsp.a(alt_main.o) (alt_irq_init) +../MCTest_bsp/\libucosii_bsp.a(altera_avalon_jtag_uart_fd.o) + ../MCTest_bsp/\libucosii_bsp.a(alt_sys_init.o) (altera_avalon_jtag_uart_read_fd) +../MCTest_bsp/\libucosii_bsp.a(altera_avalon_jtag_uart_init.o) + ../MCTest_bsp/\libucosii_bsp.a(alt_sys_init.o) (altera_avalon_jtag_uart_init) +../MCTest_bsp/\libucosii_bsp.a(altera_avalon_jtag_uart_ioctl.o) + ../MCTest_bsp/\libucosii_bsp.a(altera_avalon_jtag_uart_fd.o) (altera_avalon_jtag_uart_ioctl) +../MCTest_bsp/\libucosii_bsp.a(altera_avalon_jtag_uart_read.o) + ../MCTest_bsp/\libucosii_bsp.a(altera_avalon_jtag_uart_fd.o) (altera_avalon_jtag_uart_read) +../MCTest_bsp/\libucosii_bsp.a(altera_avalon_jtag_uart_write.o) + ../MCTest_bsp/\libucosii_bsp.a(altera_avalon_jtag_uart_fd.o) (altera_avalon_jtag_uart_write) +../MCTest_bsp/\libucosii_bsp.a(altera_avalon_timer_sc.o) + ../MCTest_bsp/\libucosii_bsp.a(alt_sys_init.o) (alt_avalon_timer_sc_init) +../MCTest_bsp/\libucosii_bsp.a(altera_avalon_uart_fd.o) + ../MCTest_bsp/\libucosii_bsp.a(alt_sys_init.o) (altera_avalon_uart_read_fd) +../MCTest_bsp/\libucosii_bsp.a(altera_avalon_uart_init.o) + ../MCTest_bsp/\libucosii_bsp.a(alt_sys_init.o) (altera_avalon_uart_init) +../MCTest_bsp/\libucosii_bsp.a(altera_avalon_uart_read.o) + ../MCTest_bsp/\libucosii_bsp.a(altera_avalon_uart_fd.o) (altera_avalon_uart_read) +../MCTest_bsp/\libucosii_bsp.a(altera_avalon_uart_write.o) + ../MCTest_bsp/\libucosii_bsp.a(altera_avalon_uart_fd.o) (altera_avalon_uart_write) +../MCTest_bsp/\libucosii_bsp.a(altera_up_avalon_rs232.o) + ../MCTest_bsp/\libucosii_bsp.a(alt_sys_init.o) (alt_up_rs232_read_fd) +../MCTest_bsp/\libucosii_bsp.a(alt_alarm_start.o) + ../MCTest_bsp/\libucosii_bsp.a(altera_avalon_jtag_uart_init.o) (alt_alarm_start) +../MCTest_bsp/\libucosii_bsp.a(alt_dcache_flush_all.o) + ../MCTest_bsp/\libucosii_bsp.a(alt_load.o) (alt_dcache_flush_all) +../MCTest_bsp/\libucosii_bsp.a(alt_dev_llist_insert.o) + ../MCTest_bsp/\libucosii_bsp.a(alt_sys_init.o) (alt_dev_llist_insert) +../MCTest_bsp/\libucosii_bsp.a(alt_do_ctors.o) + ../MCTest_bsp/\libucosii_bsp.a(alt_main.o) (_do_ctors) +../MCTest_bsp/\libucosii_bsp.a(alt_do_dtors.o) + ../MCTest_bsp/\libucosii_bsp.a(alt_main.o) (_do_dtors) +../MCTest_bsp/\libucosii_bsp.a(alt_find_dev.o) + ../MCTest_bsp/\libucosii_bsp.a(altera_up_avalon_rs232.o) (alt_find_dev) +../MCTest_bsp/\libucosii_bsp.a(alt_icache_flush_all.o) + ../MCTest_bsp/\libucosii_bsp.a(alt_load.o) (alt_icache_flush_all) +../MCTest_bsp/\libucosii_bsp.a(alt_io_redirect.o) + ../MCTest_bsp/\libucosii_bsp.a(alt_main.o) (alt_io_redirect) +../MCTest_bsp/\libucosii_bsp.a(alt_irq_register.o) + ../MCTest_bsp/\libucosii_bsp.a(altera_avalon_jtag_uart_init.o) (alt_irq_register) +../MCTest_bsp/\libucosii_bsp.a(alt_irq_vars.o) + ../MCTest_bsp/\libucosii_bsp.a(alt_irq_register.o) (alt_irq_active) +../MCTest_bsp/\libucosii_bsp.a(alt_open.o) + ../MCTest_bsp/\libucosii_bsp.a(alt_io_redirect.o) (open) +../MCTest_bsp/\libucosii_bsp.a(alt_tick.o) + ../MCTest_bsp/\libucosii_bsp.a(altera_avalon_jtag_uart_init.o) (_alt_tick_rate) +../MCTest_bsp/\libucosii_bsp.a(altera_nios2_qsys_irq.o) + ../MCTest_bsp/\libucosii_bsp.a(alt_sys_init.o) (altera_nios2_qsys_irq_init) +../MCTest_bsp/\libucosii_bsp.a(os_cpu_a.o) + ../MCTest_bsp/\libucosii_bsp.a(os_core.o) (OSIntCtxSw) +../MCTest_bsp/\libucosii_bsp.a(os_cpu_c.o) + ../MCTest_bsp/\libucosii_bsp.a(os_task.o) (OSTaskStkInit) +../MCTest_bsp/\libucosii_bsp.a(alt_find_file.o) + ../MCTest_bsp/\libucosii_bsp.a(alt_open.o) (alt_find_file) +../MCTest_bsp/\libucosii_bsp.a(alt_get_fd.o) + ../MCTest_bsp/\libucosii_bsp.a(alt_open.o) (alt_get_fd) +../MCTest_bsp/\libucosii_bsp.a(alt_icache_flush.o) + ../MCTest_bsp/\libucosii_bsp.a(alt_icache_flush_all.o) (alt_icache_flush) +../MCTest_bsp/\libucosii_bsp.a(alt_irq_entry.o) + ../MCTest_bsp/\libucosii_bsp.a(alt_irq_register.o) (alt_irq_entry) +../MCTest_bsp/\libucosii_bsp.a(alt_irq_handler.o) + ../MCTest_bsp/\libucosii_bsp.a(alt_irq_register.o) (alt_irq_handler) +../MCTest_bsp/\libucosii_bsp.a(alt_exception_entry.o) + ../MCTest_bsp/\libucosii_bsp.a(alt_irq_entry.o) (alt_exception) +c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-atexit.o) + ../MCTest_bsp/\libucosii_bsp.a(alt_main.o) (atexit) +c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-exit.o) + ../MCTest_bsp/\libucosii_bsp.a(alt_main.o) (exit) +c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-memcmp.o) + ../MCTest_bsp/\libucosii_bsp.a(alt_find_dev.o) (memcmp) +c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-__atexit.o) + c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-atexit.o) (__register_exitproc) +c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-__call_atexit.o) + c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-exit.o) (__call_exitprocs) + +Allocating common symbols +Common symbol size file + +alt_irq 0x100 ../MCTest_bsp/\libucosii_bsp.a(alt_irq_handler.o) +OSLockNesting 0x1 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +OSRunning 0x1 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +OSIdleCtr 0x4 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +OSPrioHighRdy 0x1 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +errno 0x4 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-int_errno.o) +alt_heapsem 0x4 ../MCTest_bsp/\libucosii_bsp.a(alt_malloc_lock.o) +OSFlagTbl 0x370 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +OSPrioCur 0x1 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +OSTCBList 0x4 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +alt_fd_list_lock 0x4 ../MCTest_bsp/\libucosii_bsp.a(alt_dev.o) +OSMemTbl 0xc30 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +OSTickStepState 0x1 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +OSTaskStatStk 0x800 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +OSCtxSwCtr 0x4 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +OSIdleCtrMax 0x4 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +OSTCBFreeList 0x4 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +OSCPUUsage 0x1 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +OSTaskCtr 0x1 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +OSMemFreeList 0x4 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +OSQTbl 0x1e0 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +OSTCBHighRdy 0x4 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +OSQFreeList 0x4 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +OSRdyGrp 0x1 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +_atexit0 0x190 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-atexit.o) +OSRdyTbl 0x3 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +OSEventFreeList 0x4 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +OSIntNesting 0x1 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +OSTCBCur 0x4 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +OSTime 0x4 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +OSTaskIdleStk 0x800 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +OSEventTbl 0xb40 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +OSTCBTbl 0x510 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +OSFlagFreeList 0x4 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +OSStatRdy 0x1 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +OSTCBPrioTbl 0x54 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +alt_envsem 0x4 ../MCTest_bsp/\libucosii_bsp.a(alt_env_lock.o) +OSIdleCtrRun 0x4 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) + +Discarded input sections + + .group 0x00000000 0x8 obj/default/MotorHandler.o + .group 0x00000000 0x8 obj/default/MotorHandler.o + .group 0x00000000 0x8 obj/default/MotorHandler.o + .group 0x00000000 0x8 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(class_type_info.o) + .group 0x00000000 0x8 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(class_type_info.o) + .group 0x00000000 0x8 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(class_type_info.o) + .group 0x00000000 0x8 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(si_class_type_info.o) + .group 0x00000000 0x8 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(si_class_type_info.o) + .group 0x00000000 0x8 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(si_class_type_info.o) + .group 0x00000000 0x8 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(tinfo.o) + .group 0x00000000 0x8 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(tinfo.o) + .group 0x00000000 0x8 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(tinfo.o) + .group 0x00000000 0x8 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(eh_exception.o) + .group 0x00000000 0x8 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(eh_exception.o) + .group 0x00000000 0x8 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(eh_exception.o) + .group 0x00000000 0x8 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(eh_exception.o) + .group 0x00000000 0x8 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(eh_exception.o) + .group 0x00000000 0x8 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(eh_exception.o) + .group 0x00000000 0x8 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(new_handler.o) + .group 0x00000000 0x8 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(new_handler.o) + .group 0x00000000 0x8 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(new_handler.o) + +Memory Configuration + +Name Origin Length Attributes +reset 0x01000000 0x00000020 +sdram 0x01000020 0x00ffffe0 +*default* 0x00000000 0xffffffff + +Linker script and memory map + +LOAD ../MCTest_bsp//obj/HAL/src/crt0.o +LOAD obj/default/MotorHandler.o +LOAD obj/default/main.o +LOAD c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a +LOAD c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libm.a +LOAD c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a +START GROUP +LOAD c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a +LOAD c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a +LOAD ../MCTest_bsp/\libucosii_bsp.a +END GROUP +LOAD c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a + 0x01000000 __alt_mem_sdram = 0x1000000 + +.entry 0x01000000 0x20 + *(.entry) + .entry 0x01000000 0x20 ../MCTest_bsp//obj/HAL/src/crt0.o + 0x01000000 __reset + +.exceptions 0x01000020 0x1a0 + 0x01000020 PROVIDE (__ram_exceptions_start, ABSOLUTE (.)) + 0x01000020 . = ALIGN (0x20) + *(.irq) + *(.exceptions.entry.label) + .exceptions.entry.label + 0x01000020 0x0 ../MCTest_bsp/\libucosii_bsp.a(alt_irq_entry.o) + 0x01000020 alt_irq_entry + .exceptions.entry.label + 0x01000020 0x0 ../MCTest_bsp/\libucosii_bsp.a(alt_exception_entry.o) + 0x01000020 alt_exception + *(.exceptions.entry.user) + *(.exceptions.entry) + .exceptions.entry + 0x01000020 0x54 ../MCTest_bsp/\libucosii_bsp.a(alt_exception_entry.o) + *(.exceptions.irqtest.user) + *(.exceptions.irqtest) + .exceptions.irqtest + 0x01000074 0x10 ../MCTest_bsp/\libucosii_bsp.a(alt_irq_entry.o) + *(.exceptions.irqhandler.user) + *(.exceptions.irqhandler) + .exceptions.irqhandler + 0x01000084 0x4 ../MCTest_bsp/\libucosii_bsp.a(alt_irq_entry.o) + *(.exceptions.irqreturn.user) + *(.exceptions.irqreturn) + .exceptions.irqreturn + 0x01000088 0x4 ../MCTest_bsp/\libucosii_bsp.a(alt_irq_entry.o) + *(.exceptions.notirq.label) + .exceptions.notirq.label + 0x0100008c 0x0 ../MCTest_bsp/\libucosii_bsp.a(alt_irq_entry.o) + *(.exceptions.notirq.user) + *(.exceptions.notirq) + .exceptions.notirq + 0x0100008c 0x8 ../MCTest_bsp/\libucosii_bsp.a(alt_exception_entry.o) + *(.exceptions.soft.user) + *(.exceptions.soft) + *(.exceptions.unknown.user) + *(.exceptions.unknown) + .exceptions.unknown + 0x01000094 0x4 ../MCTest_bsp/\libucosii_bsp.a(alt_exception_entry.o) + *(.exceptions.exit.label) + .exceptions.exit.label + 0x01000098 0x0 ../MCTest_bsp/\libucosii_bsp.a(alt_irq_entry.o) + .exceptions.exit.label + 0x01000098 0x0 ../MCTest_bsp/\libucosii_bsp.a(alt_exception_entry.o) + *(.exceptions.exit.user) + *(.exceptions.exit) + .exceptions.exit + 0x01000098 0x54 ../MCTest_bsp/\libucosii_bsp.a(alt_exception_entry.o) + *(.exceptions) + .exceptions 0x010000ec 0xd4 ../MCTest_bsp/\libucosii_bsp.a(alt_irq_handler.o) + 0x010000ec alt_irq_handler + 0x010001c0 PROVIDE (__ram_exceptions_end, ABSOLUTE (.)) + 0x01000020 PROVIDE (__flash_exceptions_start, LOADADDR (.exceptions)) + +.text 0x010001c0 0x18a14 + 0x010001c0 PROVIDE (stext, ABSOLUTE (.)) + *(.interp) + *(.hash) + *(.dynsym) + *(.dynstr) + *(.gnu.version) + *(.gnu.version_d) + *(.gnu.version_r) + *(.rel.init) + *(.rela.init) + *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) + *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) + *(.rel.fini) + *(.rela.fini) + *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) + *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) + *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) + *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) + *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) + *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) + *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) + *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) + *(.rel.ctors) + *(.rela.ctors) + *(.rel.dtors) + *(.rela.dtors) + *(.rel.got) + *(.rela.got) + *(.rel.sdata .rel.sdata.* .rel.gnu.linkonce.s.*) + *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*) + *(.rel.sbss .rel.sbss.* .rel.gnu.linkonce.sb.*) + *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*) + *(.rel.sdata2 .rel.sdata2.* .rel.gnu.linkonce.s2.*) + *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*) + *(.rel.sbss2 .rel.sbss2.* .rel.gnu.linkonce.sb2.*) + *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*) + *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) + *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) + *(.rel.plt) + *(.rela.plt) + *(.rel.dyn) + *(.init) + *(.plt) + *(.text .stub .text.* .gnu.linkonce.t.*) + .text 0x010001c0 0x4c ../MCTest_bsp//obj/HAL/src/crt0.o + 0x010001c0 _start + .text 0x0100020c 0x3cc obj/default/MotorHandler.o + 0x0100020c MotorHandler::MotorHandler() + 0x0100023c MotorHandler::MotorHandler() + 0x0100026c MotorHandler::sendByteMC(char) + 0x010002a0 MotorHandler::mc_stop() + 0x01000328 MotorHandler::mc_right() + 0x01000380 MotorHandler::mc_left() + 0x010003d8 MotorHandler::mc_backward() + 0x01000460 MotorHandler::mc_forward() + 0x010004e8 MotorHandler::~MotorHandler() + 0x01000538 MotorHandler::~MotorHandler() + 0x01000588 MotorHandler::~MotorHandler() + .text 0x010005d8 0x4b4 obj/default/main.o + 0x01000734 wifi_write(char*, int) + 0x010007a4 queue_init() + 0x010007dc main + 0x010008e8 wifi_wait() + 0x01000920 mc_task(void*) + 0x0100096c wifi_read() + 0x010009d0 wifi_task(void*) + 0x01000a20 ir_task(void*) + .text 0x01000a8c 0x1bc c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(class_type_info.o) + 0x01000a8c __cxxabiv1::__class_type_info::__do_upcast(__cxxabiv1::__class_type_info const*, void**) const + 0x01000af8 __cxxabiv1::__class_type_info::__do_find_public_src(long, void const*, __cxxabiv1::__class_type_info const*, void const*) const + 0x01000b18 __cxxabiv1::__class_type_info::~__class_type_info() + 0x01000b4c __cxxabiv1::__class_type_info::~__class_type_info() + 0x01000b5c __cxxabiv1::__class_type_info::~__class_type_info() + 0x01000b6c __cxxabiv1::__class_type_info::__do_catch(std::type_info const*, void**, unsigned int) const + 0x01000bcc __cxxabiv1::__class_type_info::__do_upcast(__cxxabiv1::__class_type_info const*, void const*, __cxxabiv1::__class_type_info::__upcast_result&) const + 0x01000bfc __cxxabiv1::__class_type_info::__do_dyncast(long, __cxxabiv1::__class_type_info::__sub_kind, __cxxabiv1::__class_type_info const*, void const*, __cxxabiv1::__class_type_info const*, void const*, __cxxabiv1::__class_type_info::__dyncast_result&) const + .text 0x01000c48 0xbec c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(eh_personality.o) + 0x010011d4 __cxa_call_unexpected + 0x01001354 __gxx_personality_sj0 + .text 0x01001834 0x10c c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(eh_terminate.o) + 0x01001834 std::set_terminate(void (*)()) + 0x01001848 std::set_unexpected(void (*)()) + 0x0100185c __cxxabiv1::__terminate(void (*)()) + 0x01001900 std::terminate() + 0x01001918 __cxxabiv1::__unexpected(void (*)()) + 0x01001928 std::unexpected() + .text 0x01001940 0x0 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(eh_term_handler.o) + .text 0x01001940 0x1e4 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(eh_catch.o) + 0x01001940 __cxa_get_exception_ptr + 0x01001948 std::uncaught_exception() + 0x01001968 __cxa_end_catch + 0x01001a0c __cxa_begin_catch + .text 0x01001b24 0xc c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(del_op.o) + 0x01001b24 operator delete(void*) + .text 0x01001b30 0x148 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(eh_throw.o) + 0x01001b30 __cxa_rethrow + 0x01001ba4 __cxa_throw + .text 0x01001c78 0x1c8 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(si_class_type_info.o) + 0x01001c78 __cxxabiv1::__si_class_type_info::__do_upcast(__cxxabiv1::__class_type_info const*, void const*, __cxxabiv1::__class_type_info::__upcast_result&) const + 0x01001cf0 __cxxabiv1::__si_class_type_info::~__si_class_type_info() + 0x01001d24 __cxxabiv1::__si_class_type_info::~__si_class_type_info() + 0x01001d34 __cxxabiv1::__si_class_type_info::~__si_class_type_info() + 0x01001d44 __cxxabiv1::__si_class_type_info::__do_find_public_src(long, void const*, __cxxabiv1::__class_type_info const*, void const*) const + 0x01001d78 __cxxabiv1::__si_class_type_info::__do_dyncast(long, __cxxabiv1::__class_type_info::__sub_kind, __cxxabiv1::__class_type_info const*, void const*, __cxxabiv1::__class_type_info const*, void const*, __cxxabiv1::__class_type_info::__dyncast_result&) const + .text 0x01001e40 0x58 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(tinfo.o) + 0x01001e40 std::type_info::__is_pointer_p() const + 0x01001e48 std::type_info::__is_function_p() const + 0x01001e50 std::type_info::__do_catch(std::type_info const*, void**, unsigned int) const + 0x01001e60 std::type_info::__do_upcast(__cxxabiv1::__class_type_info const*, void**) const + 0x01001e68 std::type_info::~type_info() + 0x01001e78 std::type_info::~type_info() + 0x01001e88 std::type_info::~type_info() + .text 0x01001e98 0x174 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(eh_alloc.o) + 0x01001e98 __cxa_free_exception + 0x01001ed8 __cxa_allocate_exception + .text 0x0100200c 0x100 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(new_op.o) + 0x0100200c operator new(unsigned long) + .text 0x0100210c 0x94 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(eh_exception.o) + 0x0100210c std::exception::what() const + 0x0100211c std::exception::~exception() + 0x0100212c std::exception::~exception() + 0x0100213c std::exception::~exception() + 0x0100214c std::bad_exception::~bad_exception() + 0x01002180 std::bad_exception::~bad_exception() + 0x01002190 std::bad_exception::~bad_exception() + .text 0x010021a0 0x44 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(eh_call.o) + 0x010021a0 __cxa_call_terminate + .text 0x010021e4 0x60 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(new_handler.o) + 0x010021e4 std::set_new_handler(void (*)()) + 0x010021f0 std::bad_alloc::~bad_alloc() + 0x01002224 std::bad_alloc::~bad_alloc() + 0x01002234 std::bad_alloc::~bad_alloc() + .text 0x01002244 0x10 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(eh_globals.o) + 0x01002244 __cxa_get_globals_fast + 0x0100224c __cxa_get_globals + .text 0x01002254 0x0 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(eh_unex_handler.o) + .text 0x01002254 0x548 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(unwind-sjlj.o) + 0x01002254 _Unwind_SjLj_Register + 0x01002264 _Unwind_SjLj_Unregister + 0x01002270 _Unwind_GetGR + 0x01002288 _Unwind_GetCFA + 0x0100229c _Unwind_SetGR + 0x010022b4 _Unwind_GetIP + 0x010022c4 _Unwind_GetIPInfo + 0x010022d8 _Unwind_SetIP + 0x010022e8 _Unwind_GetLanguageSpecificData + 0x010022f4 _Unwind_GetRegionStart + 0x010022fc _Unwind_FindEnclosingFunction + 0x01002304 _Unwind_GetDataRelBase + 0x0100230c _Unwind_GetTextRelBase + 0x01002414 _Unwind_DeleteException + 0x01002520 _Unwind_SjLj_Resume + 0x0100257c _Unwind_SjLj_RaiseException + 0x01002674 _Unwind_SjLj_ForcedUnwind + 0x010026c4 _Unwind_Backtrace + 0x01002744 _Unwind_SjLj_Resume_or_Rethrow + .text 0x0100279c 0x18 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-abort.o) + 0x0100279c abort + .text 0x010027b4 0x28 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-malloc.o) + 0x010027b4 free + 0x010027c8 malloc + .text 0x010027dc 0x740 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-mallocr.o) + 0x010027dc _malloc_r + .text 0x01002f1c 0x98 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-memset.o) + 0x01002f1c memset + .text 0x01002fb4 0x78 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-printf.o) + 0x01002fb4 printf + 0x01002ff8 _printf_r + .text 0x0100302c 0xb4 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-puts.o) + 0x0100302c _puts_r + 0x010030cc puts + .text 0x010030e0 0x70 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-sbrkr.o) + 0x010030e0 _sbrk_r + .text 0x01003150 0x2d8 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-signal.o) + 0x01003150 _raise_r + 0x0100321c raise + 0x01003230 _init_signal_r + 0x01003294 _init_signal + 0x010032a4 __sigtramp_r + 0x01003358 __sigtramp + 0x0100336c _signal_r + 0x0100340c signal + .text 0x01003428 0x78 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-signalr.o) + 0x01003428 _getpid_r + 0x0100342c _kill_r + .text 0x010034a0 0x74 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-strlen.o) + 0x010034a0 strlen + .text 0x01003514 0x1f28 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-vfprintf.o) + 0x0100356c ___vfprintf_internal_r + 0x01005418 __vfprintf_internal + .text 0x0100543c 0x13c c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-wsetup.o) + 0x0100543c __swsetup_r + .text 0x01005578 0x17cc c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-dtoa.o) + 0x01005790 _dtoa_r + .text 0x01006d44 0x230 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-fflush.o) + 0x01006d44 _fflush_r + 0x01006f40 fflush + .text 0x01006f74 0x2c0 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-findfp.o) + 0x01006fcc __sfp_lock_acquire + 0x01006fd0 __sfp_lock_release + 0x01006fd4 __sinit_lock_acquire + 0x01006fd8 __sinit_lock_release + 0x01006fdc __sinit + 0x01007090 __fp_unlock_all + 0x010070a8 __fp_lock_all + 0x010070c0 _cleanup_r + 0x010070cc _cleanup + 0x010070dc __sfmoreglue + 0x01007144 __sfp + .text 0x01007234 0x440 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-freer.o) + 0x01007234 _malloc_trim_r + 0x01007360 _free_r + .text 0x01007674 0x49c c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-fvwrite.o) + 0x01007674 __sfvwrite_r + .text 0x01007b10 0x180 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-fwalk.o) + 0x01007b10 _fwalk_reent + 0x01007bd8 _fwalk + .text 0x01007c90 0x0 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-impure.o) + .text 0x01007c90 0x0 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-int_errno.o) + .text 0x01007c90 0xc4 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-locale.o) + 0x01007c90 __locale_charset + 0x01007c98 _localeconv_r + 0x01007ca4 localeconv + 0x01007cb4 _setlocale_r + 0x01007d38 setlocale + .text 0x01007d54 0x194 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-makebuf.o) + 0x01007d54 __smakebuf_r + .text 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0x01008dc4 __i2b + 0x01008e00 __multadd + 0x01008f00 __pow5mult + 0x01009020 __s2b + .text 0x01009140 0x5f4 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-reallocr.o) + 0x01009140 _realloc_r + .text 0x01009734 0x40 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-s_isinfd.o) + 0x01009734 __isinfd + .text 0x01009774 0x30 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-s_isnand.o) + 0x01009774 __isnand + .text 0x010097a4 0x14c c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-stdio.o) + 0x010097a4 __sclose + 0x010097ac __sseek + 0x01009814 __swrite + 0x01009890 __sread + .text 0x010098f0 0xbc c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-strcmp.o) + 0x010098f0 strcmp + .text 0x010099ac 0x78 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-writer.o) + 0x010099ac _write_r + .text 0x01009a24 0xb4 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-callocr.o) + 0x01009a24 _calloc_r + .text 0x01009ad8 0x70 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-closer.o) + 0x01009ad8 _close_r + .text 0x01009b48 0x124 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-fclose.o) + 0x01009b48 _fclose_r + 0x01009c58 fclose + .text 0x01009c6c 0x74 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-fstatr.o) + 0x01009c6c _fstat_r + .text 0x01009ce0 0x70 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-isattyr.o) + 0x01009ce0 _isatty_r + .text 0x01009d50 0x78 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-lseekr.o) + 0x01009d50 _lseek_r + .text 0x01009dc8 0x78 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-readr.o) + 0x01009dc8 _read_r + .text 0x01009e40 0x5dc c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_udivdi3.o) + 0x01009e40 __udivdi3 + .text 0x0100a41c 0x5b0 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_umoddi3.o) + 0x0100a41c __umoddi3 + .text 0x0100a9cc 0x504 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_addsub_df.o) + 0x0100addc __subdf3 + 0x0100ae5c __adddf3 + .text 0x0100aed0 0x3c4 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_mul_df.o) + 0x0100aed0 __muldf3 + .text 0x0100b294 0x258 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_div_df.o) + 0x0100b294 __divdf3 + .text 0x0100b4ec 0x88 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_eq_df.o) + 0x0100b4ec __eqdf2 + .text 0x0100b574 0x88 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_ne_df.o) + 0x0100b574 __nedf2 + .text 0x0100b5fc 0x88 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_gt_df.o) + 0x0100b5fc __gtdf2 + .text 0x0100b684 0x88 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_ge_df.o) + 0x0100b684 __gedf2 + .text 0x0100b70c 0x88 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_lt_df.o) + 0x0100b70c __ltdf2 + .text 0x0100b794 0xf8 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_si_to_df.o) + 0x0100b794 __floatsidf + .text 0x0100b88c 0xd8 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_df_to_si.o) + 0x0100b88c __fixdfsi + .text 0x0100b964 0x0 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_thenan_df.o) + .text 0x0100b964 0x194 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_usi_to_df.o) + 0x0100b964 __floatunsidf + .text 0x0100baf8 0x14c c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(lib2-divmod.o) + 0x0100bb74 __divsi3 + 0x0100bbd4 __modsi3 + 0x0100bc34 __udivsi3 + 0x0100bc3c __umodsi3 + .text 0x0100bc44 0x98 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_muldi3.o) + 0x0100bc44 __muldi3 + .text 0x0100bcdc 0x0 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_clz.o) + .text 0x0100bcdc 0x80 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_clzsi2.o) + 0x0100bcdc __clzsi2 + .text 0x0100bd5c 0x314 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_pack_df.o) + 0x0100bd5c __pack_d + .text 0x0100c070 0x138 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_unpack_df.o) + 0x0100c070 __unpack_d + .text 0x0100c1a8 0xc8 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_fpcmp_parts_df.o) + 0x0100c1a8 __fpcmp_parts_d + .text 0x0100c270 0x15c ../MCTest_bsp/\libucosii_bsp.a(alt_close.o) + 0x0100c270 close + .text 0x0100c3cc 0x2c ../MCTest_bsp/\libucosii_bsp.a(alt_dev.o) + .text 0x0100c3f8 0x0 ../MCTest_bsp/\libucosii_bsp.a(alt_errno.o) + .text 0x0100c3f8 0x6c ../MCTest_bsp/\libucosii_bsp.a(alt_exit.o) + 0x0100c438 _exit + .text 0x0100c464 0x134 ../MCTest_bsp/\libucosii_bsp.a(alt_fstat.o) + 0x0100c464 fstat + .text 0x0100c598 0x20 ../MCTest_bsp/\libucosii_bsp.a(alt_getpid.o) + 0x0100c598 getpid + .text 0x0100c5b8 0x120 ../MCTest_bsp/\libucosii_bsp.a(alt_isatty.o) + 0x0100c5b8 isatty + .text 0x0100c6d8 0x1a0 ../MCTest_bsp/\libucosii_bsp.a(alt_kill.o) + 0x0100c6d8 kill + .text 0x0100c878 0xec ../MCTest_bsp/\libucosii_bsp.a(alt_load.o) + 0x0100c878 alt_load + .text 0x0100c964 0x150 ../MCTest_bsp/\libucosii_bsp.a(alt_lseek.o) + 0x0100c964 lseek + .text 0x0100cab4 0xc8 ../MCTest_bsp/\libucosii_bsp.a(alt_main.o) + 0x0100cab4 alt_main + .text 0x0100cb7c 0x180 ../MCTest_bsp/\libucosii_bsp.a(alt_read.o) + 0x0100cb7c read + .text 0x0100ccfc 0x60 ../MCTest_bsp/\libucosii_bsp.a(alt_release_fd.o) + 0x0100ccfc alt_release_fd + .text 0x0100cd5c 0xbc ../MCTest_bsp/\libucosii_bsp.a(alt_sbrk.o) + 0x0100cd5c sbrk + .text 0x0100ce18 0x180 ../MCTest_bsp/\libucosii_bsp.a(alt_write.o) + 0x0100ce18 write + .text 0x0100cf98 0x108 ../MCTest_bsp/\libucosii_bsp.a(alt_env_lock.o) + 0x0100cf98 __env_lock + 0x0100d044 __env_unlock + .text 0x0100d0a0 0x1d8 ../MCTest_bsp/\libucosii_bsp.a(alt_malloc_lock.o) + 0x0100d0a0 __malloc_lock + 0x0100d1a8 __malloc_unlock + .text 0x0100d278 0x2128 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) + 0x0100d278 OSEventNameGet + 0x0100d3a8 OSEventNameSet + 0x0100d4ec OSEventPendMulti + 0x0100dba0 OSInit + 0x0100dbf4 OSIntEnter + 0x0100dc70 OSIntExit + 0x0100dd70 OSSchedLock + 0x0100ddfc OSSchedUnlock + 0x0100dee0 OSStart + 0x0100df50 OSStatInit + 0x0100dffc OSTimeTick + 0x0100e23c OSVersion + 0x0100e25c OS_Dummy + 0x0100e278 OS_EventTaskRdy + 0x0100e40c OS_EventTaskWait + 0x0100e51c OS_EventTaskWaitMulti + 0x0100e670 OS_EventTaskRemove + 0x0100e728 OS_EventTaskRemoveMulti + 0x0100e82c OS_EventWaitListInit + 0x0100ebf8 OS_MemClr + 0x0100ec4c OS_MemCopy + 0x0100ecb8 OS_Sched + 0x0100edfc OS_StrCopy + 0x0100ee7c OS_StrLen + 0x0100eed4 OS_TaskIdle + 0x0100ef30 OS_TaskStat + 0x0100eff8 OS_TaskStatStkChk + 0x0100f0c0 OS_TCBInit + .text 0x0100f3a0 0x18c ../MCTest_bsp/\libucosii_bsp.a(os_dbg.o) + 0x0100f3a0 OSDebugInit + .text 0x0100f52c 0x193c ../MCTest_bsp/\libucosii_bsp.a(os_flag.o) + 0x0100f52c OSFlagAccept + 0x0100f860 OSFlagCreate + 0x0100f99c OSFlagDel + 0x0100fc44 OSFlagNameGet + 0x0100fd88 OSFlagNameSet + 0x0100fedc OSFlagPend + 0x01010520 OSFlagPendGetFlagsRdy + 0x01010588 OSFlagPost + 0x01010930 OSFlagQuery + 0x01010bc8 OS_FlagInit + 0x01010dbc OS_FlagUnlink + .text 0x01010e68 0x808 ../MCTest_bsp/\libucosii_bsp.a(os_mem.o) + 0x01010e68 OSMemCreate + 0x01011084 OSMemGet + 0x01011188 OSMemNameGet + 0x01011294 OSMemNameSet + 0x010113b4 OSMemPut + 0x010114a4 OSMemQuery + 0x010115a0 OS_MemInit + .text 0x01011670 0x1334 ../MCTest_bsp/\libucosii_bsp.a(os_q.o) + 0x01011670 OSQAccept + 0x010117c4 OSQCreate + 0x010119d8 OSQDel + 0x01011cd8 OSQFlush + 0x01011da0 OSQPend + 0x010120c0 OSQPendAbort + 0x0101223c OSQPost + 0x010123bc OSQPostFront + 0x01012544 OSQPostOpt + 0x01012778 OSQQuery + 0x010128f8 OS_QInit + .text 0x010129a4 0xbc8 ../MCTest_bsp/\libucosii_bsp.a(os_sem.o) + 0x010129a4 OSSemAccept + 0x01012a64 OSSemCreate + 0x01012b78 OSSemDel + 0x01012e18 OSSemPend + 0x01013094 OSSemPendAbort + 0x01013210 OSSemPost + 0x01013338 OSSemQuery + 0x01013468 OSSemSet + .text 0x0101356c 0x1a40 ../MCTest_bsp/\libucosii_bsp.a(os_task.o) + 0x0101356c OSTaskChangePrio + 0x01013ae0 OSTaskCreate + 0x01013cb4 OSTaskCreateExt + 0x01013eb4 OSTaskDel + 0x010142c0 OSTaskDelReq + 0x01014430 OSTaskNameGet + 0x010145e8 OSTaskNameSet + 0x010147ac OSTaskResume + 0x010149c4 OSTaskStkChk + 0x01014bc0 OSTaskSuspend + 0x01014dec OSTaskQuery + 0x01014f30 OS_TaskStkClr + .text 0x01014fac 0x598 ../MCTest_bsp/\libucosii_bsp.a(os_time.o) + 0x01014fac OSTimeDly + 0x010150f8 OSTimeDlyHMSM + 0x0101526c OSTimeDlyResume + 0x0101547c OSTimeGet + 0x010154e0 OSTimeSet + .text 0x01015544 0x114 ../MCTest_bsp/\libucosii_bsp.a(alt_sys_init.o) + 0x01015544 alt_irq_init + 0x01015578 alt_sys_init + .text 0x01015658 0x148 ../MCTest_bsp/\libucosii_bsp.a(altera_avalon_jtag_uart_fd.o) + 0x01015658 altera_avalon_jtag_uart_read_fd + 0x010156b0 altera_avalon_jtag_uart_write_fd + 0x01015708 altera_avalon_jtag_uart_close_fd + 0x01015750 altera_avalon_jtag_uart_ioctl_fd + .text 0x010157a0 0x580 ../MCTest_bsp/\libucosii_bsp.a(altera_avalon_jtag_uart_init.o) + 0x010157a0 altera_avalon_jtag_uart_init + 0x01015cac altera_avalon_jtag_uart_close + .text 0x01015d20 0xf4 ../MCTest_bsp/\libucosii_bsp.a(altera_avalon_jtag_uart_ioctl.o) + 0x01015d20 altera_avalon_jtag_uart_ioctl + .text 0x01015e14 0x2c0 ../MCTest_bsp/\libucosii_bsp.a(altera_avalon_jtag_uart_read.o) + 0x01015e14 altera_avalon_jtag_uart_read + .text 0x010160d4 0x2dc ../MCTest_bsp/\libucosii_bsp.a(altera_avalon_jtag_uart_write.o) + 0x010160d4 altera_avalon_jtag_uart_write + .text 0x010163b0 0xfc ../MCTest_bsp/\libucosii_bsp.a(altera_avalon_timer_sc.o) + 0x01016424 alt_avalon_timer_sc_init + .text 0x010164ac 0xf8 ../MCTest_bsp/\libucosii_bsp.a(altera_avalon_uart_fd.o) + 0x010164ac altera_avalon_uart_read_fd + 0x01016504 altera_avalon_uart_write_fd + 0x0101655c altera_avalon_uart_close_fd + .text 0x010165a4 0x578 ../MCTest_bsp/\libucosii_bsp.a(altera_avalon_uart_init.o) + 0x010165a4 altera_avalon_uart_init + 0x01016abc altera_avalon_uart_close + .text 0x01016b1c 0x310 ../MCTest_bsp/\libucosii_bsp.a(altera_avalon_uart_read.o) + 0x01016b1c altera_avalon_uart_read + .text 0x01016e2c 0x2a8 ../MCTest_bsp/\libucosii_bsp.a(altera_avalon_uart_write.o) + 0x01016e2c altera_avalon_uart_write + .text 0x010170d4 0x398 ../MCTest_bsp/\libucosii_bsp.a(altera_up_avalon_rs232.o) + 0x010170d4 alt_up_rs232_enable_read_interrupt + 0x01017128 alt_up_rs232_disable_read_interrupt + 0x01017180 alt_up_rs232_get_used_space_in_read_FIFO + 0x010171bc alt_up_rs232_get_available_space_in_write_FIFO + 0x010171fc alt_up_rs232_check_parity + 0x0101724c alt_up_rs232_write_data + 0x01017294 alt_up_rs232_read_data + 0x01017308 alt_up_rs232_read_fd + 0x01017398 alt_up_rs232_write_fd + 0x0101742c alt_up_rs232_open_dev + .text 0x0101746c 0x154 ../MCTest_bsp/\libucosii_bsp.a(alt_alarm_start.o) + 0x0101746c alt_alarm_start + .text 0x010175c0 0x44 ../MCTest_bsp/\libucosii_bsp.a(alt_dcache_flush_all.o) + 0x010175c0 alt_dcache_flush_all + .text 0x01017604 0x114 ../MCTest_bsp/\libucosii_bsp.a(alt_dev_llist_insert.o) + 0x01017604 alt_dev_llist_insert + .text 0x01017718 0x64 ../MCTest_bsp/\libucosii_bsp.a(alt_do_ctors.o) + 0x01017718 _do_ctors + .text 0x0101777c 0x64 ../MCTest_bsp/\libucosii_bsp.a(alt_do_dtors.o) + 0x0101777c _do_dtors + .text 0x010177e0 0x94 ../MCTest_bsp/\libucosii_bsp.a(alt_find_dev.o) + 0x010177e0 alt_find_dev + .text 0x01017874 0x30 ../MCTest_bsp/\libucosii_bsp.a(alt_icache_flush_all.o) + 0x01017874 alt_icache_flush_all + .text 0x010178a4 0x13c ../MCTest_bsp/\libucosii_bsp.a(alt_io_redirect.o) + 0x01017968 alt_io_redirect + .text 0x010179e0 0x1c0 ../MCTest_bsp/\libucosii_bsp.a(alt_irq_register.o) + 0x010179e0 alt_irq_register + .text 0x01017ba0 0x0 ../MCTest_bsp/\libucosii_bsp.a(alt_irq_vars.o) + .text 0x01017ba0 0x2c4 ../MCTest_bsp/\libucosii_bsp.a(alt_open.o) + 0x01017c7c open + .text 0x01017e64 0x1a8 ../MCTest_bsp/\libucosii_bsp.a(alt_tick.o) + 0x01017e64 alt_alarm_stop + 0x01017efc alt_tick + .text 0x0101800c 0x20 ../MCTest_bsp/\libucosii_bsp.a(altera_nios2_qsys_irq.o) + 0x0101800c altera_nios2_qsys_irq_init + .text 0x0101802c 0xd0 ../MCTest_bsp/\libucosii_bsp.a(os_cpu_a.o) + 0x0101802c OSCtxSw + 0x0101802c OSIntCtxSw + 0x010180b8 OSStartHighRdy + 0x010180d8 OSStartTsk + .text 0x010180fc 0x418 ../MCTest_bsp/\libucosii_bsp.a(os_cpu_c.o) + 0x010180fc OSTaskStkInit + 0x0101840c OSTaskCreateHook + 0x0101842c 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c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_pack_df.o) + .debug_ranges 0x00000b80 0x18 ../MCTest_bsp/\libucosii_bsp.a(altera_avalon_jtag_uart_init.o) + .debug_ranges 0x00000b98 0x18 ../MCTest_bsp/\libucosii_bsp.a(altera_avalon_uart_init.o) + .debug_ranges 0x00000bb0 0x28 ../MCTest_bsp/\libucosii_bsp.a(alt_irq_entry.o) + .debug_ranges 0x00000bd8 0x30 ../MCTest_bsp/\libucosii_bsp.a(alt_exception_entry.o) + .debug_ranges 0x00000c08 0x18 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-__call_atexit.o) diff --git a/MCandWifiTestDE0/Software/Archive/MCTest/MCTest.objdump b/MCandWifiTestDE0/Software/Archive/MCTest/MCTest.objdump new file mode 100644 index 00000000..ec9f64b9 --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest/MCTest.objdump @@ -0,0 +1,36201 @@ + +MCTest.elf: file format elf32-littlenios2 +MCTest.elf +architecture: nios2, flags 0x00000112: +EXEC_P, HAS_SYMS, D_PAGED +start address 0x010001c0 + +Program Header: + LOAD off 0x00001000 vaddr 0x01000000 paddr 0x01000000 align 2**12 + filesz 0x00000020 memsz 0x00000020 flags r-x + LOAD off 0x00001020 vaddr 0x01000020 paddr 0x01000020 align 2**12 + filesz 0x00019220 memsz 0x00019220 flags r-x + LOAD off 0x0001a240 vaddr 0x01019240 paddr 0x0101af14 align 2**12 + filesz 0x00001cd4 memsz 0x00001cd4 flags rw- + LOAD off 0x0001cbe8 vaddr 0x0101cbe8 paddr 0x0101cbe8 align 2**12 + filesz 0x00000000 memsz 0x00009da0 flags rw- + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .entry 00000020 01000000 01000000 00001000 2**5 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 1 .exceptions 000001a0 01000020 01000020 00001020 2**2 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 2 .text 00018a14 010001c0 010001c0 000011c0 2**2 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 3 .rodata 0000066c 01018bd4 01018bd4 00019bd4 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 4 .rwdata 00001cd4 01019240 0101af14 0001a240 2**2 + CONTENTS, ALLOC, LOAD, DATA, SMALL_DATA + 5 .bss 00009da0 0101cbe8 0101cbe8 0001cbe8 2**2 + ALLOC, SMALL_DATA + 6 .comment 00000026 00000000 00000000 0001bf14 2**0 + CONTENTS, READONLY + 7 .debug_aranges 00001118 00000000 00000000 0001bf40 2**3 + CONTENTS, READONLY, DEBUGGING + 8 .debug_pubnames 00002f7c 00000000 00000000 0001d058 2**0 + CONTENTS, READONLY, DEBUGGING + 9 .debug_info 0003da89 00000000 00000000 0001ffd4 2**0 + CONTENTS, READONLY, DEBUGGING + 10 .debug_abbrev 0000d180 00000000 00000000 0005da5d 2**0 + CONTENTS, READONLY, DEBUGGING + 11 .debug_line 00022121 00000000 00000000 0006abdd 2**0 + CONTENTS, READONLY, DEBUGGING + 12 .debug_frame 00003230 00000000 00000000 0008cd00 2**2 + CONTENTS, READONLY, DEBUGGING + 13 .debug_str 00004097 00000000 00000000 0008ff30 2**0 + CONTENTS, READONLY, DEBUGGING + 14 .debug_loc 0000f916 00000000 00000000 00093fc7 2**0 + CONTENTS, READONLY, DEBUGGING + 15 .debug_alt_sim_info 00000030 00000000 00000000 000a38e0 2**2 + CONTENTS, READONLY, DEBUGGING + 16 .debug_ranges 00000c20 00000000 00000000 000a3910 2**3 + CONTENTS, READONLY, DEBUGGING + 17 .thread_model 00000006 00000000 00000000 000aac33 2**0 + CONTENTS, READONLY + 18 .cpu 00000003 00000000 00000000 000aac39 2**0 + CONTENTS, READONLY + 19 .qsys 00000001 00000000 00000000 000aac3c 2**0 + CONTENTS, READONLY + 20 .simulation_enabled 00000001 00000000 00000000 000aac3d 2**0 + CONTENTS, READONLY + 21 .sysid_hash 00000004 00000000 00000000 000aac3e 2**0 + CONTENTS, READONLY + 22 .sysid_base 00000004 00000000 00000000 000aac42 2**0 + CONTENTS, READONLY + 23 .sysid_time 00000004 00000000 00000000 000aac46 2**0 + CONTENTS, READONLY + 24 .stderr_dev 0000000b 00000000 00000000 000aac4a 2**0 + CONTENTS, READONLY + 25 .stdin_dev 0000000b 00000000 00000000 000aac55 2**0 + CONTENTS, READONLY + 26 .stdout_dev 0000000b 00000000 00000000 000aac60 2**0 + CONTENTS, READONLY + 27 .sopc_system_name 00000006 00000000 00000000 000aac6b 2**0 + CONTENTS, READONLY + 28 .quartus_project_dir 0000002c 00000000 00000000 000aac71 2**0 + CONTENTS, READONLY + 29 .jdi 000046ad 00000000 00000000 000aac9d 2**0 + CONTENTS, READONLY + 30 .sopcinfo 000569df 00000000 00000000 000af34a 2**0 + CONTENTS, READONLY +SYMBOL TABLE: +01000000 l d .entry 00000000 .entry +01000020 l d .exceptions 00000000 .exceptions +010001c0 l d .text 00000000 .text +01018bd4 l d .rodata 00000000 .rodata +01019240 l d .rwdata 00000000 .rwdata +0101cbe8 l d .bss 00000000 .bss +00000000 l d .comment 00000000 .comment +00000000 l d .debug_aranges 00000000 .debug_aranges +00000000 l d .debug_pubnames 00000000 .debug_pubnames +00000000 l d .debug_info 00000000 .debug_info +00000000 l d .debug_abbrev 00000000 .debug_abbrev +00000000 l d .debug_line 00000000 .debug_line +00000000 l d .debug_frame 00000000 .debug_frame +00000000 l d .debug_str 00000000 .debug_str +00000000 l d .debug_loc 00000000 .debug_loc +00000000 l d .debug_alt_sim_info 00000000 .debug_alt_sim_info +00000000 l d .debug_ranges 00000000 .debug_ranges +01000208 l .text 00000000 alt_after_alt_main +00000000 l df *ABS* 00000000 alt_irq_handler.c +00000000 l df *ABS* 00000000 MotorHandler.cpp +00000000 l df *ABS* 00000000 main.cpp +01000704 l F .text 00000030 _GLOBAL__I_motorHandler +010005d8 l F .text 0000012c _Z41__static_initialization_and_destruction_0ii +00000000 l df *ABS* 00000000 class_type_info.cc +00000000 l df *ABS* 00000000 eh_personality.cc +01000c48 l F .text 00000030 _Z12read_uleb128PKhPj +01000c78 l F .text 00000054 _Z12read_sleb128PKhPi +01000ccc l F .text 0000009c _Z16get_adjusted_ptrPKSt9type_infoS1_PPv +01000d68 l F .text 000001d4 _Z28read_encoded_value_with_basehjPKhPj +01000f3c l F .text 00000090 _Z21base_of_encoded_valuehP15_Unwind_Context +01000fcc l F .text 00000100 _Z17parse_lsda_headerP15_Unwind_ContextPKhP16lsda_header_info +010010cc l F .text 00000084 _Z15get_ttype_entryP16lsda_header_infoj +01001150 l F .text 00000084 _Z20check_exception_specP16lsda_header_infoPKSt9type_infoPvi +00000000 l df *ABS* 00000000 eh_terminate.cc +00000000 l df *ABS* 00000000 eh_term_handler.cc +00000000 l df *ABS* 00000000 eh_catch.cc +00000000 l df *ABS* 00000000 del_op.cc +00000000 l df *ABS* 00000000 eh_throw.cc +01001c18 l F .text 00000060 _Z23__gxx_exception_cleanup19_Unwind_Reason_CodeP17_Unwind_Exception +00000000 l df *ABS* 00000000 si_class_type_info.cc +00000000 l df *ABS* 00000000 tinfo.cc +00000000 l df *ABS* 00000000 eh_alloc.cc +01022cac l O .bss 00000800 emergency_buffer +0101cbf0 l O .bss 00000004 emergency_used +00000000 l df *ABS* 00000000 new_op.cc +00000000 l df *ABS* 00000000 eh_exception.cc +00000000 l df *ABS* 00000000 eh_call.cc +00000000 l df *ABS* 00000000 new_handler.cc +00000000 l df *ABS* 00000000 eh_globals.cc +0101cbf8 l O .bss 00000008 eh_globals +00000000 l df *ABS* 00000000 eh_unex_handler.cc +00000000 l df *ABS* 00000000 unwind-sjlj.c +0101cc00 l O .bss 00000004 fc_static +01002314 l F .text 00000100 _Unwind_ForcedUnwind_Phase2 +0100242c l F .text 000000cc _Unwind_RaiseException_Phase2 +010024f8 l F .text 00000028 uw_install_context +00000000 l df *ABS* 00000000 abort.c +00000000 l df *ABS* 00000000 malloc.c +00000000 l df *ABS* 00000000 mallocr.c +00000000 l df *ABS* 00000000 memset.c +00000000 l df *ABS* 00000000 printf.c +00000000 l df *ABS* 00000000 puts.c +00000000 l df *ABS* 00000000 sbrkr.c +00000000 l df *ABS* 00000000 signal.c +00000000 l df *ABS* 00000000 signalr.c +00000000 l df *ABS* 00000000 strlen.c +00000000 l df *ABS* 00000000 vfprintf.c +01003514 l F .text 00000058 __sprint_r +01018e1a l O .rodata 00000010 blanks.3452 +01018e0a l O .rodata 00000010 zeroes.3453 +00000000 l df *ABS* 00000000 wsetup.c +00000000 l df *ABS* 00000000 dtoa.c +01005578 l F .text 00000218 quorem +00000000 l df *ABS* 00000000 fflush.c +00000000 l df *ABS* 00000000 findfp.c +01006f74 l F .text 00000058 std +01007080 l F .text 00000008 __fp_lock +01007088 l F .text 00000008 __fp_unlock +00000000 l df *ABS* 00000000 mallocr.c +00000000 l df *ABS* 00000000 fvwrite.c +00000000 l df *ABS* 00000000 fwalk.c +00000000 l df *ABS* 00000000 impure.c +01019648 l O .rwdata 00000400 impure_data +00000000 l df *ABS* 00000000 int_errno.c +00000000 l df *ABS* 00000000 locale.c +0101ae6c l O .rwdata 00000004 charset +01018e50 l O .rodata 00000030 lconv +00000000 l df *ABS* 00000000 makebuf.c +00000000 l df *ABS* 00000000 memchr.c +00000000 l df *ABS* 00000000 memcpy.c +00000000 l df *ABS* 00000000 memmove.c +00000000 l df *ABS* 00000000 mprec.c +01018f98 l O .rodata 0000000c p05.2458 +00000000 l df *ABS* 00000000 mallocr.c +00000000 l df *ABS* 00000000 s_isinfd.c +00000000 l df *ABS* 00000000 s_isnand.c +00000000 l df *ABS* 00000000 stdio.c +00000000 l df *ABS* 00000000 strcmp.c +00000000 l df *ABS* 00000000 writer.c +00000000 l df *ABS* 00000000 mallocr.c +00000000 l df *ABS* 00000000 closer.c +00000000 l df *ABS* 00000000 fclose.c +00000000 l df *ABS* 00000000 fstatr.c +00000000 l df *ABS* 00000000 isattyr.c +00000000 l df *ABS* 00000000 lseekr.c +00000000 l df *ABS* 00000000 readr.c +00000000 l df *ABS* 00000000 libgcc2.c +00000000 l df *ABS* 00000000 libgcc2.c +00000000 l df *ABS* 00000000 dp-bit.c +0100a9cc l F .text 00000410 _fpadd_parts +00000000 l df *ABS* 00000000 dp-bit.c +00000000 l df *ABS* 00000000 dp-bit.c +00000000 l df *ABS* 00000000 dp-bit.c +00000000 l df *ABS* 00000000 dp-bit.c +00000000 l df *ABS* 00000000 dp-bit.c +00000000 l df *ABS* 00000000 dp-bit.c +00000000 l df *ABS* 00000000 dp-bit.c +00000000 l df *ABS* 00000000 dp-bit.c +00000000 l df *ABS* 00000000 dp-bit.c +00000000 l df *ABS* 00000000 dp-bit.c +00000000 l df *ABS* 00000000 dp-bit.c +00000000 l df *ABS* 00000000 lib2-divmod.c +0100baf8 l F .text 0000007c udivmodsi4 +00000000 l df *ABS* 00000000 libgcc2.c +00000000 l df *ABS* 00000000 libgcc2.c +00000000 l df *ABS* 00000000 libgcc2.c +00000000 l df *ABS* 00000000 dp-bit.c +00000000 l df *ABS* 00000000 dp-bit.c +00000000 l df *ABS* 00000000 dp-bit.c +00000000 l df *ABS* 00000000 alt_close.c +0100c36c l F .text 00000060 alt_get_errno +00000000 l df *ABS* 00000000 alt_dev.c +0100c3cc l F .text 0000002c alt_dev_null_write +00000000 l df *ABS* 00000000 alt_errno.c +00000000 l df *ABS* 00000000 alt_exit.c +0100c3f8 l F .text 00000040 alt_sim_halt +00000000 l df *ABS* 00000000 alt_fstat.c +0100c538 l F .text 00000060 alt_get_errno +00000000 l df *ABS* 00000000 alt_getpid.c +00000000 l df *ABS* 00000000 alt_isatty.c +0100c678 l F .text 00000060 alt_get_errno +00000000 l df *ABS* 00000000 alt_kill.c +0100c818 l F .text 00000060 alt_get_errno +00000000 l df *ABS* 00000000 alt_load.c +0100c8f8 l F .text 0000006c alt_load_section +00000000 l df *ABS* 00000000 alt_lseek.c +0100ca54 l F .text 00000060 alt_get_errno +00000000 l df *ABS* 00000000 alt_main.c +00000000 l df *ABS* 00000000 alt_read.c +0100cc9c l F .text 00000060 alt_get_errno +00000000 l df *ABS* 00000000 alt_release_fd.c +00000000 l df *ABS* 00000000 alt_sbrk.c +0101ae88 l O .rwdata 00000004 heap_end +00000000 l df *ABS* 00000000 alt_write.c +0100cf38 l F .text 00000060 alt_get_errno +00000000 l df *ABS* 00000000 alt_env_lock.c +0101ae8c l O .rwdata 00000004 lockid +0101cc30 l O .bss 00000004 locks +00000000 l df *ABS* 00000000 alt_malloc_lock.c +0101ae90 l O .rwdata 00000004 lockid +0101cc38 l O .bss 00000004 locks +00000000 l df *ABS* 00000000 os_core.c +0100e970 l F .text 00000044 OS_InitMisc +0100e9b4 l F .text 0000006c OS_InitRdyList +0100eb18 l F .text 000000e0 OS_InitTCBList +0100e894 l F .text 000000dc OS_InitEventList +0100ea20 l F .text 0000007c OS_InitTaskIdle +0100ea9c l F .text 0000007c OS_InitTaskStat +0100ed8c l F .text 00000070 OS_SchedNew +00000000 l df *ABS* 00000000 os_dbg.c +00000000 l df *ABS* 00000000 os_flag.c +01010cac l F .text 00000110 OS_FlagTaskRdy +01010a04 l F .text 000001c4 OS_FlagBlock +00000000 l df *ABS* 00000000 os_mem.c +00000000 l df *ABS* 00000000 os_q.c +00000000 l df *ABS* 00000000 os_sem.c +00000000 l df *ABS* 00000000 os_task.c +00000000 l df *ABS* 00000000 os_time.c +00000000 l df *ABS* 00000000 alt_sys_init.c +01019bfc l O .rwdata 0000106c jtag_uart_0 +0101ac68 l O .rwdata 000000d0 uart_mc +0101ad38 l O .rwdata 000000d0 uart_wifi +0101ae08 l O .rwdata 0000002c rs232_wifi +01015620 l F .text 00000038 alt_dev_reg +00000000 l df *ABS* 00000000 altera_avalon_jtag_uart_fd.c +00000000 l df *ABS* 00000000 altera_avalon_jtag_uart_init.c +010158d0 l F .text 000002c8 altera_avalon_jtag_uart_irq +01015b98 l F .text 00000114 altera_avalon_jtag_uart_timeout +00000000 l df *ABS* 00000000 altera_avalon_jtag_uart_ioctl.c +00000000 l df *ABS* 00000000 altera_avalon_jtag_uart_read.c +00000000 l df *ABS* 00000000 altera_avalon_jtag_uart_write.c +00000000 l df *ABS* 00000000 altera_avalon_timer_sc.c +010163b0 l F .text 00000074 alt_avalon_timer_sc_irq +00000000 l df *ABS* 00000000 altera_avalon_uart_fd.c +00000000 l df *ABS* 00000000 altera_avalon_uart_init.c +01016720 l F .text 000000a0 altera_avalon_uart_irq +010167c0 l F .text 0000013c altera_avalon_uart_rxirq +010168fc l F .text 000001c0 altera_avalon_uart_txirq +00000000 l df *ABS* 00000000 altera_avalon_uart_read.c +01016dcc l F .text 00000060 alt_get_errno +00000000 l df *ABS* 00000000 altera_avalon_uart_write.c +01017074 l F .text 00000060 alt_get_errno +00000000 l df *ABS* 00000000 altera_up_avalon_rs232.c +00000000 l df *ABS* 00000000 alt_alarm_start.c +00000000 l df *ABS* 00000000 alt_dcache_flush_all.c +00000000 l df *ABS* 00000000 alt_dev_llist_insert.c +010176b8 l F .text 00000060 alt_get_errno +00000000 l df *ABS* 00000000 alt_do_ctors.c +00000000 l df *ABS* 00000000 alt_do_dtors.c +00000000 l df *ABS* 00000000 alt_find_dev.c +00000000 l df *ABS* 00000000 alt_icache_flush_all.c +00000000 l df *ABS* 00000000 alt_io_redirect.c +010178a4 l F .text 000000c4 alt_open_fd +00000000 l df *ABS* 00000000 alt_irq_register.c +00000000 l df *ABS* 00000000 alt_irq_vars.c +00000000 l df *ABS* 00000000 alt_open.c +01017ba0 l F .text 000000dc alt_file_locked +01017e04 l F .text 00000060 alt_get_errno +00000000 l df *ABS* 00000000 alt_tick.c +00000000 l df *ABS* 00000000 altera_nios2_qsys_irq.c +00000040 l *ABS* 00000000 OSCtxSw_SWITCH_PC +00000000 l df *ABS* 00000000 os_cpu_c.c +00000014 l *ABS* 00000000 OSTCBNext_OFFSET +00000032 l *ABS* 00000000 OSTCBPrio_OFFSET +00000000 l *ABS* 00000000 OSTCBStkPtr_OFFSET +00000000 l df *ABS* 00000000 alt_find_file.c +00000000 l df *ABS* 00000000 alt_get_fd.c +00000000 l df *ABS* 00000000 alt_icache_flush.c +00000000 l df *ABS* 00000000 atexit.c +00000000 l df *ABS* 00000000 exit.c +00000000 l df *ABS* 00000000 memcmp.c +00000000 l df *ABS* 00000000 __atexit.c +00000000 l df *ABS* 00000000 __call_atexit.c +010189ac l F .text 00000004 register_fini +01001e98 g F .text 00000040 __cxa_free_exception +01001e48 g F .text 00000008 _ZNKSt9type_info15__is_function_pEv +01008558 g F .text 00000094 _mprec_log10 +010004e8 g F .text 00000050 _ZN12MotorHandlerD0Ev +01001928 g F .text 00000018 _ZSt10unexpectedv +0101aede g O .rwdata 00000002 OSTaskNameSize +01008644 g F .text 00000088 __any_on +01009ce0 g F .text 00000070 _isatty_r +01018f70 g O .rodata 00000028 __mprec_tinytens +0100cab4 g F .text 000000c8 alt_main +0100302c g F .text 000000a0 _puts_r +010266f8 g O .bss 00000100 alt_irq +01009d50 g F .text 00000078 _lseek_r +010115a0 g F .text 000000d0 OS_MemInit +010022c4 g F .text 00000014 _Unwind_GetIPInfo +0101af14 g *ABS* 00000000 __flash_rwdata_start +010154e0 g F .text 00000064 OSTimeSet +0100b4ec g F .text 00000088 __eqdf2 +01001b30 g F .text 00000074 __cxa_rethrow +01002264 g F .text 0000000c _Unwind_SjLj_Unregister +01001848 g F .text 00000014 _ZSt14set_unexpectedPFvvE +0100d4ec g F .text 000006b4 OSEventPendMulti +010022b4 g F .text 00000010 _Unwind_GetIP +01026988 g *ABS* 00000000 __alt_heap_start +0101840c g F .text 00000020 OSTaskCreateHook +0100342c g F .text 00000074 _kill_r +01002234 g F .text 00000010 _ZNSt9bad_allocD2Ev +0101ec9c g O .bss 00002000 wifi_task_stk +01002fb4 g F .text 00000044 printf +0101aeb6 g O .rwdata 00000002 OSMboxEn +0100dbf4 g F .text 0000007c OSIntEnter +01001d44 g F .text 00000034 _ZNK10__cxxabiv120__si_class_type_info20__do_find_public_srcElPKvPKNS_17__class_type_infoES2_ +0100336c g F .text 000000a0 _signal_r +010097ac g F .text 00000068 __sseek +01006fdc g F .text 000000a4 __sinit +010007a4 g F .text 00000038 _Z10queue_initv +0101aec6 g O .rwdata 00000002 OSQEn +01001d34 g F .text 00000010 _ZN10__cxxabiv120__si_class_type_infoD2Ev +01007cb4 g F .text 00000084 _setlocale_r +01018cbc w O .rodata 00000025 _ZTSN10__cxxabiv120__si_class_type_infoE +010070dc g F .text 00000068 __sfmoreglue +0100d1a8 g F .text 000000d0 __malloc_unlock +01018468 g F .text 0000001c OSTaskStatHook +01017308 g F .text 00000090 alt_up_rs232_read_fd +0101ae34 w O .rwdata 00000008 _ZTI12MotorHandler +0101cc40 g O .bss 00000001 OSLockNesting +01001948 g F .text 00000020 _ZSt18uncaught_exceptionv +0101af04 g O .rwdata 00000002 OSDataSize +0101cc41 g O .bss 00000001 OSRunning +0100806c g F .text 000000e0 memmove +010184a0 g F .text 0000001c OSInitHookBegin +0101aefc g O .rwdata 00000002 OSTmrSize +0100213c g F .text 00000010 _ZNSt9exceptionD2Ev +010070cc g F .text 00000010 _cleanup +0100096c g F .text 00000064 _Z9wifi_readv +010086cc g F .text 000000bc _Balloc +01000920 g F .text 0000004c _Z7mc_taskPv +0101cc44 g O .bss 00000004 OSIdleCtr +0100b5fc g F .text 00000088 __gtdf2 +01018d20 w O .rodata 00000014 _ZTVSt13bad_exception +010180d8 g .text 00000000 OSStartTsk +00000000 w *UND* 00000000 __errno +0100f0c0 g F .text 000002e0 OS_TCBInit +01000000 g F .entry 0000001c __reset +010022f4 g F .text 00000008 _Unwind_GetRegionStart +0101af02 g O .rwdata 00000002 OSTmrWheelTblSize +01000020 g *ABS* 00000000 __flash_exceptions_start +0101aea2 g O .rwdata 00000002 OSEventSize +0101cc48 g O .bss 00000001 OSPrioHighRdy +01009c6c g F .text 00000074 _fstat_r +0101842c g F .text 00000020 OSTaskDelHook +0100200c g F .text 00000100 _Znwm +0101cc10 g O .bss 00000004 errno +010180b8 g .text 00000000 OSStartHighRdy +01013cb4 g F .text 00000200 OSTaskCreateExt +01010520 g F .text 00000068 OSFlagPendGetFlagsRdy +0101aee2 g O .rwdata 00000002 OSTaskStatStkSize +010026c4 g F .text 00000080 _Unwind_Backtrace +0100f52c g F .text 00000334 OSFlagAccept +01011cd8 g F .text 000000c8 OSQFlush +01011670 g F .text 00000154 OSQAccept +0101cc28 g O .bss 00000004 alt_argv +01022e34 g *ABS* 00000000 _gp +01013ae0 g F .text 000001d4 OSTaskCreate +0101356c g F .text 00000574 OSTaskChangePrio +0101cc3c g O .bss 00000004 alt_heapsem +0100c598 g F .text 00000020 getpid +0100f3a0 g F .text 0000018c OSDebugInit +010011d4 g F .text 00000180 __cxa_call_unexpected +01013eb4 g F .text 0000040c OSTaskDel +01001940 g F .text 00000008 __cxa_get_exception_ptr +01019a7c g O .rwdata 00000180 alt_fd_list +010234d4 g O .bss 00000370 OSFlagTbl +01002674 g F .text 00000050 _Unwind_SjLj_ForcedUnwind +0100e670 g F .text 000000b8 OS_EventTaskRemove +01002288 g F .text 00000014 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+010128f8 g F .text 000000ac OS_QInit +0100ee7c g F .text 00000058 OS_StrLen +01011294 g F .text 00000120 OSMemNameSet +010002a0 g F .text 00000088 _ZN12MotorHandler7mc_stopEv +0101aeda g O .rwdata 00000002 OSTaskProfileEn +0101cc80 g O .bss 00000004 OSTime +01016abc g F .text 00000060 altera_avalon_uart_close +01024e54 g O .bss 00000800 OSTaskIdleStk +01009774 g F .text 00000030 __isnand +0100c438 g F .text 0000002c _exit +0101746c g F .text 00000154 alt_alarm_start +0100fc44 g F .text 00000144 OSFlagNameGet +0101547c g F .text 00000064 OSTimeGet +0100bc44 g F .text 00000098 __muldi3 +01002270 g F .text 00000018 _Unwind_GetGR +0100224c g F .text 00000008 __cxa_get_globals +01007d54 g F .text 00000194 __smakebuf_r +0101ae54 g O .rwdata 00000004 _ZN10__cxxabiv120__unexpected_handlerE +010034a0 g F .text 00000074 strlen +01003230 g F .text 00000064 _init_signal_r +0101ae40 w O .rwdata 00000008 _ZTISt9type_info +0101844c g F .text 0000001c OSTaskSwHook +01017c7c g F .text 00000188 open +01025654 g O .bss 00000b40 OSEventTbl +0100b684 g F .text 00000088 __gedf2 +01018d68 w O .rodata 0000000d _ZTSSt9exception +01026194 g O .bss 00000510 OSTCBTbl +01013468 g F .text 00000104 OSSemSet +0100211c g F .text 00000010 _ZNSt9exceptionD0Ev +01017874 g F .text 00000030 alt_icache_flush_all +01002304 g F .text 00000008 _Unwind_GetDataRelBase +0101af08 g O .rwdata 00000004 alt_priority_mask +01012b78 g F .text 000002a0 OSSemDel +0101cc84 g O .bss 00000004 OSFlagFreeList +0101aea0 g O .rwdata 00000002 OSEventNameSize +01005418 g F .text 00000024 __vfprintf_internal +0101cc88 g O .bss 00000001 OSStatRdy +010266a4 g O .bss 00000054 OSTCBPrioTbl +01016b1c g F .text 000002b0 altera_avalon_uart_read +0100cf98 g F .text 000000ac __env_lock +0101aee6 g O .rwdata 00000002 OSTaskSwHookEn +0100addc g F .text 00000080 __subdf3 +010081e4 g F .text 000000c4 __lo0bits +0101af0c g O .rwdata 00000008 alt_alarm_list +0101aeae g O .rwdata 00000002 OSFlagWidth +01017718 g F .text 00000064 _do_ctors +01003358 g F .text 00000014 __sigtramp +01017180 g F .text 0000003c alt_up_rs232_get_used_space_in_read_FIFO +0100c270 g F .text 000000fc close +0101cc34 g O .bss 00000004 alt_envsem +0101cc8c g O .bss 00000004 OSIdleCtrRun +0100e23c g F .text 00000020 OSVersion +0101aef8 g O .rwdata 00000002 OSTmrCfgWheelSize +0100c878 g F .text 00000080 alt_load +01014f30 g F .text 0000007c OS_TaskStkClr +0100bd5c g F .text 00000314 __pack_d +0101aed2 g O .rwdata 00000002 OSTaskCreateEn +01001e50 g F .text 00000010 _ZNKSt9type_info10__do_catchEPKS_PPvj +0100e82c g F .text 00000068 OS_EventWaitListInit +0100321c g F .text 00000014 raise +010184d8 g F .text 0000001c OSTaskIdleHook +010027b4 g F .text 00000014 free +01006fd4 g F .text 00000004 __sinit_lock_acquire +01008e00 g F .text 00000100 __multadd +01000b18 g F .text 00000034 _ZN10__cxxabiv117__class_type_infoD0Ev +01014bc0 g F .text 0000022c OSTaskSuspend +0100814c g F .text 00000028 _Bfree +0100eed4 g F .text 0000005c OS_TaskIdle +0101aefe g O .rwdata 00000002 OSTmrTblSize +01012778 g F .text 00000180 OSQQuery + + + +Disassembly of section .entry: + +01000000 <__reset>: +#if NIOS2_ICACHE_SIZE > 0 && defined(ALT_ALLOW_CODE_AT_RESET) && !defined(ALT_SIM_OPTIMIZE) + /* Assume the instruction cache size is always a power of two. */ +#if NIOS2_ICACHE_SIZE > 0x8000 + movhi r2, %hi(NIOS2_ICACHE_SIZE) +#else + movui r2, NIOS2_ICACHE_SIZE + 1000000: 00880014 movui r2,8192 +#endif + +0: + initi r2 + 1000004: 1001483a initi r2 + addi r2, r2, -NIOS2_ICACHE_LINE_SIZE + 1000008: 10bff804 addi r2,r2,-32 + bgt r2, zero, 0b + 100000c: 00bffd16 blt zero,r2,1000004 <__reset+0x4> + * Jump to the _start entry point in the .text section if reset code + * is allowed or if optimizing for RTL simulation. + */ +#if defined(ALT_ALLOW_CODE_AT_RESET) || defined(ALT_SIM_OPTIMIZE) + /* Jump to the _start entry point in the .text section. */ + movhi r1, %hi(_start) + 1000010: 00404034 movhi at,256 + ori r1, r1, %lo(_start) + 1000014: 08407014 ori at,at,448 + jmp r1 + 1000018: 0800683a jmp at + 100001c: 00000000 call 0 + +Disassembly of section .exceptions: + +01000020 : + * Process an exception. For all exceptions we must preserve all + * caller saved registers on the stack (See the Nios2 ABI + * documentation for details). + */ + + addi sp, sp, -76 + 1000020: deffed04 addi sp,sp,-76 + +#endif + +#endif + + stw ra, 0(sp) + 1000024: dfc00015 stw ra,0(sp) + /* + * Leave a gap in the stack frame at 4(sp) for the muldiv handler to + * store zero into. + */ + + stw r1, 8(sp) + 1000028: d8400215 stw at,8(sp) + stw r2, 12(sp) + 100002c: d8800315 stw r2,12(sp) + stw r3, 16(sp) + 1000030: d8c00415 stw r3,16(sp) + stw r4, 20(sp) + 1000034: d9000515 stw r4,20(sp) + stw r5, 24(sp) + 1000038: d9400615 stw r5,24(sp) + stw r6, 28(sp) + 100003c: d9800715 stw r6,28(sp) + stw r7, 32(sp) + 1000040: d9c00815 stw r7,32(sp) + + rdctl r5, estatus + 1000044: 000b307a rdctl r5,estatus + + stw r8, 36(sp) + 1000048: da000915 stw r8,36(sp) + stw r9, 40(sp) + 100004c: da400a15 stw r9,40(sp) + stw r10, 44(sp) + 1000050: da800b15 stw r10,44(sp) + stw r11, 48(sp) + 1000054: dac00c15 stw r11,48(sp) + stw r12, 52(sp) + 1000058: db000d15 stw r12,52(sp) + stw r13, 56(sp) + 100005c: db400e15 stw r13,56(sp) + stw r14, 60(sp) + 1000060: db800f15 stw r14,60(sp) + stw r15, 64(sp) + 1000064: dbc01015 stw r15,64(sp) + /* + * ea-4 contains the address of the instruction being executed + * when the exception occured. For interrupt exceptions, we will + * will be re-issue the isntruction. Store it in 72(sp) + */ + stw r5, 68(sp) /* estatus */ + 1000068: d9401115 stw r5,68(sp) + addi r15, ea, -4 /* instruction that caused exception */ + 100006c: ebffff04 addi r15,ea,-4 + stw r15, 72(sp) + 1000070: dbc01215 stw r15,72(sp) +#else + /* + * Test to see if the exception was a software exception or caused + * by an external interrupt, and vector accordingly. + */ + rdctl r4, ipending + 1000074: 0009313a rdctl r4,ipending + andi r2, r5, 1 + 1000078: 2880004c andi r2,r5,1 + beq r2, zero, .Lnot_irq + 100007c: 10000326 beq r2,zero,100008c + beq r4, zero, .Lnot_irq + 1000080: 20000226 beq r4,zero,100008c + /* + * Now that all necessary registers have been preserved, call + * alt_irq_handler() to process the interrupts. + */ + + call alt_irq_handler + 1000084: 10000ec0 call 10000ec + + .section .exceptions.irqreturn, "xa" + + br .Lexception_exit + 1000088: 00000306 br 1000098 + * upon completion, so we write ea (address of instruction *after* + * the one where the exception occured) into 72(sp). The actual + * instruction that caused the exception is written in r2, which these + * handlers will utilize. + */ + stw ea, 72(sp) /* Don't re-issue */ + 100008c: df401215 stw ea,72(sp) + ldw r2, -4(ea) /* Instruction that caused exception */ + 1000090: e8bfff17 ldw r2,-4(ea) +#ifdef NIOS2_HAS_DEBUG_STUB + /* + * Either tell the user now (if there is a debugger attached) or go into + * the debug monitor which will loop until a debugger is attached. + */ + break + 1000094: 003da03a break 0 + /* + * Restore the saved registers, so that all general purpose registers + * have been restored to their state at the time the interrupt occured. + */ + + ldw r5, 68(sp) + 1000098: d9401117 ldw r5,68(sp) + ldw ea, 72(sp) /* This becomes the PC once eret is executed */ + 100009c: df401217 ldw ea,72(sp) + ldw ra, 0(sp) + 10000a0: dfc00017 ldw ra,0(sp) + + wrctl estatus, r5 + 10000a4: 2801707a wrctl estatus,r5 + + ldw r1, 8(sp) + 10000a8: d8400217 ldw at,8(sp) + ldw r2, 12(sp) + 10000ac: d8800317 ldw r2,12(sp) + ldw r3, 16(sp) + 10000b0: d8c00417 ldw r3,16(sp) + ldw r4, 20(sp) + 10000b4: d9000517 ldw r4,20(sp) + ldw r5, 24(sp) + 10000b8: d9400617 ldw r5,24(sp) + ldw r6, 28(sp) + 10000bc: d9800717 ldw r6,28(sp) + ldw r7, 32(sp) + 10000c0: d9c00817 ldw r7,32(sp) +#ifdef ALT_STACK_CHECK + ldw et, %gprel(alt_exception_old_stack_limit)(gp) +#endif +#endif + + ldw r8, 36(sp) + 10000c4: da000917 ldw r8,36(sp) + ldw r9, 40(sp) + 10000c8: da400a17 ldw r9,40(sp) + ldw r10, 44(sp) + 10000cc: da800b17 ldw r10,44(sp) + ldw r11, 48(sp) + 10000d0: dac00c17 ldw r11,48(sp) + ldw r12, 52(sp) + 10000d4: db000d17 ldw r12,52(sp) + ldw r13, 56(sp) + 10000d8: db400e17 ldw r13,56(sp) + ldw r14, 60(sp) + 10000dc: db800f17 ldw r14,60(sp) + ldw r15, 64(sp) + 10000e0: dbc01017 ldw r15,64(sp) +#endif + + ldw sp, 76(sp) + +#else + addi sp, sp, 76 + 10000e4: dec01304 addi sp,sp,76 + + /* + * Return to the interrupted instruction. + */ + + eret + 10000e8: ef80083a eret + +010000ec : + * instruction is present if the macro ALT_CI_INTERRUPT_VECTOR defined. + */ + +void alt_irq_handler (void) __attribute__ ((section (".exceptions"))); +void alt_irq_handler (void) +{ + 10000ec: defff904 addi sp,sp,-28 + 10000f0: dfc00615 stw ra,24(sp) + 10000f4: df000515 stw fp,20(sp) + 10000f8: df000504 addi fp,sp,20 + + /* + * Notify the operating system that we are at interrupt level. + */ + + ALT_OS_INT_ENTER(); + 10000fc: 100dbf40 call 100dbf4 +#ifndef NIOS2_EIC_PRESENT +static ALT_INLINE alt_u32 ALT_ALWAYS_INLINE alt_irq_pending (void) +{ + alt_u32 active; + + NIOS2_READ_IPENDING (active); + 1000100: 0005313a rdctl r2,ipending + 1000104: e0bffc15 stw r2,-16(fp) + + return active; + 1000108: e0bffc17 ldw r2,-16(fp) + * Consider the case where the high priority interupt is asserted during + * the interrupt entry sequence for a lower priority interrupt to see why + * this is the case. + */ + + active = alt_irq_pending (); + 100010c: e0bfff15 stw r2,-4(fp) + + do + { + i = 0; + 1000110: e03ffd15 stw zero,-12(fp) + mask = 1; + 1000114: 00800044 movi r2,1 + 1000118: e0bffe15 stw r2,-8(fp) + * called to clear the interrupt condition. + */ + + do + { + if (active & mask) + 100011c: e0ffff17 ldw r3,-4(fp) + 1000120: e0bffe17 ldw r2,-8(fp) + 1000124: 1884703a and r2,r3,r2 + 1000128: 1005003a cmpeq r2,r2,zero + 100012c: 1000171e bne r2,zero,100018c + { +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT + alt_irq[i].handler(alt_irq[i].context); +#else + alt_irq[i].handler(alt_irq[i].context, i); + 1000130: e0bffd17 ldw r2,-12(fp) + 1000134: 00c040b4 movhi r3,258 + 1000138: 18d9be04 addi r3,r3,26360 + 100013c: 100490fa slli r2,r2,3 + 1000140: 10c5883a add r2,r2,r3 + 1000144: 11800017 ldw r6,0(r2) + 1000148: e0bffd17 ldw r2,-12(fp) + 100014c: 00c040b4 movhi r3,258 + 1000150: 18d9be04 addi r3,r3,26360 + 1000154: 100490fa slli r2,r2,3 + 1000158: 10c5883a add r2,r2,r3 + 100015c: 10800104 addi r2,r2,4 + 1000160: 11000017 ldw r4,0(r2) + 1000164: e17ffd17 ldw r5,-12(fp) + 1000168: 303ee83a callr r6 +#ifndef NIOS2_EIC_PRESENT +static ALT_INLINE alt_u32 ALT_ALWAYS_INLINE alt_irq_pending (void) +{ + alt_u32 active; + + NIOS2_READ_IPENDING (active); + 100016c: 0005313a rdctl r2,ipending + 1000170: e0bffb15 stw r2,-20(fp) + + return active; + 1000174: e0bffb17 ldw r2,-20(fp) + mask <<= 1; + i++; + + } while (1); + + active = alt_irq_pending (); + 1000178: e0bfff15 stw r2,-4(fp) + + } while (active); + 100017c: e0bfff17 ldw r2,-4(fp) + 1000180: 1004c03a cmpne r2,r2,zero + 1000184: 103fe21e bne r2,zero,1000110 + 1000188: 00000706 br 10001a8 +#else + alt_irq[i].handler(alt_irq[i].context, i); +#endif + break; + } + mask <<= 1; + 100018c: e0bffe17 ldw r2,-8(fp) + 1000190: 1085883a add r2,r2,r2 + 1000194: e0bffe15 stw r2,-8(fp) + i++; + 1000198: e0bffd17 ldw r2,-12(fp) + 100019c: 10800044 addi r2,r2,1 + 10001a0: e0bffd15 stw r2,-12(fp) + + } while (1); + 10001a4: 003fdd06 br 100011c + + /* + * Notify the operating system that interrupt processing is complete. + */ + + ALT_OS_INT_EXIT(); + 10001a8: 100dc700 call 100dc70 +} + 10001ac: e037883a mov sp,fp + 10001b0: dfc00117 ldw ra,4(sp) + 10001b4: df000017 ldw fp,0(sp) + 10001b8: dec00204 addi sp,sp,8 + 10001bc: f800283a ret + +Disassembly of section .text: + +010001c0 <_start>: + + /* Assume the data cache size is always a power of two. */ +#if NIOS2_DCACHE_SIZE > 0x8000 + movhi r2, %hi(NIOS2_DCACHE_SIZE) +#else + movui r2, NIOS2_DCACHE_SIZE + 10001c0: 00840014 movui r2,4096 +#endif + +0: + initd 0(r2) + 10001c4: 10000033 initd 0(r2) + addi r2, r2, -NIOS2_DCACHE_LINE_SIZE + 10001c8: 10bff804 addi r2,r2,-32 + bgt r2, zero, 0b + 10001cc: 00bffd16 blt zero,r2,10001c4 <_start+0x4> +#if (NIOS2_NUM_OF_SHADOW_REG_SETS == 0) + /* + * Now that the caches are initialized, set up the stack pointer. + * The value provided by the linker is assumed to be correctly aligned. + */ + movhi sp, %hi(__alt_stack_pointer) + 10001d0: 06c08034 movhi sp,512 + ori sp, sp, %lo(__alt_stack_pointer) + 10001d4: dec00014 ori sp,sp,0 + + /* Set up the global pointer. */ + movhi gp, %hi(_gp) + 10001d8: 068040b4 movhi gp,258 + ori gp, gp, %lo(_gp) + 10001dc: d68b8d14 ori gp,gp,11828 + */ +#ifndef ALT_SIM_OPTIMIZE + /* Log that the BSS is about to be cleared. */ + ALT_LOG_PUTS(alt_log_msg_bss) + + movhi r2, %hi(__bss_start) + 10001e0: 00804074 movhi r2,257 + ori r2, r2, %lo(__bss_start) + 10001e4: 10b2fa14 ori r2,r2,52200 + + movhi r3, %hi(__bss_end) + 10001e8: 00c040b4 movhi r3,258 + ori r3, r3, %lo(__bss_end) + 10001ec: 18da6214 ori r3,r3,27016 + + beq r2, r3, 1f + 10001f0: 10c00326 beq r2,r3,1000200 <_start+0x40> + +0: + stw zero, (r2) + 10001f4: 10000015 stw zero,0(r2) + addi r2, r2, 4 + 10001f8: 10800104 addi r2,r2,4 + bltu r2, r3, 0b + 10001fc: 10fffd36 bltu r2,r3,10001f4 <_start+0x34> + * section aren't defined until alt_load() has been called). + */ + mov et, zero +#endif + + call alt_load + 1000200: 100c8780 call 100c878 + + /* Log that alt_main is about to be called. */ + ALT_LOG_PUTS(alt_log_msg_alt_main) + + /* Call the C entry point. It should never return. */ + call alt_main + 1000204: 100cab40 call 100cab4 + +01000208 : + + /* Wait in infinite loop in case alt_main does return. */ +alt_after_alt_main: + br alt_after_alt_main + 1000208: 003fff06 br 1000208 + +0100020c <_ZN12MotorHandlerC2Ev>: + +#include "MotorHandler.h" +#include "includes.h" +#include "altera_avalon_uart_regs.h" + +MotorHandler::MotorHandler() { + 100020c: defffe04 addi sp,sp,-8 + 1000210: df000115 stw fp,4(sp) + 1000214: df000104 addi fp,sp,4 + 1000218: e13fff15 stw r4,-4(fp) + 100021c: 00c040b4 movhi r3,258 + 1000220: 18e2f704 addi r3,r3,-29732 + 1000224: e0bfff17 ldw r2,-4(fp) + 1000228: 10c00015 stw r3,0(r2) + // TODO Auto-generated constructor stub + +} + 100022c: e037883a mov sp,fp + 1000230: df000017 ldw fp,0(sp) + 1000234: dec00104 addi sp,sp,4 + 1000238: f800283a ret + +0100023c <_ZN12MotorHandlerC1Ev>: + +#include "MotorHandler.h" +#include "includes.h" +#include "altera_avalon_uart_regs.h" + +MotorHandler::MotorHandler() { + 100023c: defffe04 addi sp,sp,-8 + 1000240: df000115 stw fp,4(sp) + 1000244: df000104 addi fp,sp,4 + 1000248: e13fff15 stw r4,-4(fp) + 100024c: 00c040b4 movhi r3,258 + 1000250: 18e2f704 addi r3,r3,-29732 + 1000254: e0bfff17 ldw r2,-4(fp) + 1000258: 10c00015 stw r3,0(r2) + // TODO Auto-generated constructor stub + +} + 100025c: e037883a mov sp,fp + 1000260: df000017 ldw fp,0(sp) + 1000264: dec00104 addi sp,sp,4 + 1000268: f800283a ret + +0100026c <_ZN12MotorHandler10sendByteMCEc>: + +MotorHandler::~MotorHandler() { + // TODO Auto-generated destructor stub +} +void MotorHandler::sendByteMC(char msg){ + 100026c: defffd04 addi sp,sp,-12 + 1000270: df000215 stw fp,8(sp) + 1000274: df000204 addi fp,sp,8 + 1000278: e13ffe15 stw r4,-8(fp) + 100027c: e17fff05 stb r5,-4(fp) + IOWR_ALTERA_AVALON_UART_TXDATA(UART_MC_BASE, msg); + 1000280: e0ffff07 ldb r3,-4(fp) + 1000284: 00808034 movhi r2,512 + 1000288: 10840104 addi r2,r2,4100 + 100028c: 10c00035 stwio r3,0(r2) +} + 1000290: e037883a mov sp,fp + 1000294: df000017 ldw fp,0(sp) + 1000298: dec00104 addi sp,sp,4 + 100029c: f800283a ret + +010002a0 <_ZN12MotorHandler7mc_stopEv>: + sendByteMC(MOTOR_START_BYTE); + sendByteMC(MOTOR_DEVICE_TYPE); + sendByteMC(MOTOR_MOTOR3_FORWARD); + sendByteMC(MOTOR_CONST_SPEED); +} +void MotorHandler::mc_stop(){ + 10002a0: defffd04 addi sp,sp,-12 + 10002a4: dfc00215 stw ra,8(sp) + 10002a8: df000115 stw fp,4(sp) + 10002ac: df000104 addi fp,sp,4 + 10002b0: e13fff15 stw r4,-4(fp) + //motor1 + sendByteMC(MOTOR_START_BYTE); + 10002b4: e13fff17 ldw r4,-4(fp) + 10002b8: 017fe004 movi r5,-128 + 10002bc: 100026c0 call 100026c <_ZN12MotorHandler10sendByteMCEc> + sendByteMC(MOTOR_DEVICE_TYPE); + 10002c0: e13fff17 ldw r4,-4(fp) + 10002c4: 000b883a mov r5,zero + 10002c8: 100026c0 call 100026c <_ZN12MotorHandler10sendByteMCEc> + sendByteMC(MOTOR_MOTOR2_FORWARD); + 10002cc: e13fff17 ldw r4,-4(fp) + 10002d0: 01400144 movi r5,5 + 10002d4: 100026c0 call 100026c <_ZN12MotorHandler10sendByteMCEc> + sendByteMC(MOTOR_STOP_SPEED); + 10002d8: e13fff17 ldw r4,-4(fp) + 10002dc: 000b883a mov r5,zero + 10002e0: 100026c0 call 100026c <_ZN12MotorHandler10sendByteMCEc> + //motor 2 + sendByteMC(MOTOR_START_BYTE); + 10002e4: e13fff17 ldw r4,-4(fp) + 10002e8: 017fe004 movi r5,-128 + 10002ec: 100026c0 call 100026c <_ZN12MotorHandler10sendByteMCEc> + sendByteMC(MOTOR_DEVICE_TYPE); + 10002f0: e13fff17 ldw r4,-4(fp) + 10002f4: 000b883a mov r5,zero + 10002f8: 100026c0 call 100026c <_ZN12MotorHandler10sendByteMCEc> + sendByteMC(MOTOR_MOTOR3_FORWARD); + 10002fc: e13fff17 ldw r4,-4(fp) + 1000300: 014001c4 movi r5,7 + 1000304: 100026c0 call 100026c <_ZN12MotorHandler10sendByteMCEc> + sendByteMC(MOTOR_STOP_SPEED); + 1000308: e13fff17 ldw r4,-4(fp) + 100030c: 000b883a mov r5,zero + 1000310: 100026c0 call 100026c <_ZN12MotorHandler10sendByteMCEc> +} + 1000314: e037883a mov sp,fp + 1000318: dfc00117 ldw ra,4(sp) + 100031c: df000017 ldw fp,0(sp) + 1000320: dec00204 addi sp,sp,8 + 1000324: f800283a ret + +01000328 <_ZN12MotorHandler8mc_rightEv>: + sendByteMC(MOTOR_DEVICE_TYPE); + sendByteMC(MOTOR_MOTOR2_FORWARD); + sendByteMC(MOTOR_CONST_SPEED); +} + +void MotorHandler::mc_right(){ + 1000328: defffd04 addi sp,sp,-12 + 100032c: dfc00215 stw ra,8(sp) + 1000330: df000115 stw fp,4(sp) + 1000334: df000104 addi fp,sp,4 + 1000338: e13fff15 stw r4,-4(fp) + //Turn Right by driving right motor only + + //motor 1 + sendByteMC(MOTOR_START_BYTE); + 100033c: e13fff17 ldw r4,-4(fp) + 1000340: 017fe004 movi r5,-128 + 1000344: 100026c0 call 100026c <_ZN12MotorHandler10sendByteMCEc> + sendByteMC(MOTOR_DEVICE_TYPE); + 1000348: e13fff17 ldw r4,-4(fp) + 100034c: 000b883a mov r5,zero + 1000350: 100026c0 call 100026c <_ZN12MotorHandler10sendByteMCEc> + sendByteMC(MOTOR_MOTOR3_FORWARD); + 1000354: e13fff17 ldw r4,-4(fp) + 1000358: 014001c4 movi r5,7 + 100035c: 100026c0 call 100026c <_ZN12MotorHandler10sendByteMCEc> + sendByteMC(MOTOR_CONST_SPEED); + 1000360: e13fff17 ldw r4,-4(fp) + 1000364: 014017c4 movi r5,95 + 1000368: 100026c0 call 100026c <_ZN12MotorHandler10sendByteMCEc> +} + 100036c: e037883a mov sp,fp + 1000370: dfc00117 ldw ra,4(sp) + 1000374: df000017 ldw fp,0(sp) + 1000378: dec00204 addi sp,sp,8 + 100037c: f800283a ret + +01000380 <_ZN12MotorHandler7mc_leftEv>: + sendByteMC(MOTOR_CONST_SPEED); +} +/* + * Turn rover left + */ +void MotorHandler::mc_left(){ + 1000380: defffd04 addi sp,sp,-12 + 1000384: dfc00215 stw ra,8(sp) + 1000388: df000115 stw fp,4(sp) + 100038c: df000104 addi fp,sp,4 + 1000390: e13fff15 stw r4,-4(fp) + //Turn Left by driving the left motor only + + //motor 1 + sendByteMC(MOTOR_START_BYTE); + 1000394: e13fff17 ldw r4,-4(fp) + 1000398: 017fe004 movi r5,-128 + 100039c: 100026c0 call 100026c <_ZN12MotorHandler10sendByteMCEc> + sendByteMC(MOTOR_DEVICE_TYPE); + 10003a0: e13fff17 ldw r4,-4(fp) + 10003a4: 000b883a mov r5,zero + 10003a8: 100026c0 call 100026c <_ZN12MotorHandler10sendByteMCEc> + sendByteMC(MOTOR_MOTOR2_FORWARD); + 10003ac: e13fff17 ldw r4,-4(fp) + 10003b0: 01400144 movi r5,5 + 10003b4: 100026c0 call 100026c <_ZN12MotorHandler10sendByteMCEc> + sendByteMC(MOTOR_CONST_SPEED); + 10003b8: e13fff17 ldw r4,-4(fp) + 10003bc: 014017c4 movi r5,95 + 10003c0: 100026c0 call 100026c <_ZN12MotorHandler10sendByteMCEc> +} + 10003c4: e037883a mov sp,fp + 10003c8: dfc00117 ldw ra,4(sp) + 10003cc: df000017 ldw fp,0(sp) + 10003d0: dec00204 addi sp,sp,8 + 10003d4: f800283a ret + +010003d8 <_ZN12MotorHandler11mc_backwardEv>: + sendByteMC(MOTOR_CONST_SPEED); +} +/* + * Move rover backward by activating both motor backwards + */ +void MotorHandler::mc_backward(){ + 10003d8: defffd04 addi sp,sp,-12 + 10003dc: dfc00215 stw ra,8(sp) + 10003e0: df000115 stw fp,4(sp) + 10003e4: df000104 addi fp,sp,4 + 10003e8: e13fff15 stw r4,-4(fp) + //motor 1 + sendByteMC(MOTOR_START_BYTE); + 10003ec: e13fff17 ldw r4,-4(fp) + 10003f0: 017fe004 movi r5,-128 + 10003f4: 100026c0 call 100026c <_ZN12MotorHandler10sendByteMCEc> + sendByteMC(MOTOR_DEVICE_TYPE); + 10003f8: e13fff17 ldw r4,-4(fp) + 10003fc: 000b883a mov r5,zero + 1000400: 100026c0 call 100026c <_ZN12MotorHandler10sendByteMCEc> + sendByteMC(MOTOR_MOTOR2_BACKWARD); + 1000404: e13fff17 ldw r4,-4(fp) + 1000408: 01400104 movi r5,4 + 100040c: 100026c0 call 100026c <_ZN12MotorHandler10sendByteMCEc> + sendByteMC(MOTOR_CONST_SPEED); + 1000410: e13fff17 ldw r4,-4(fp) + 1000414: 014017c4 movi r5,95 + 1000418: 100026c0 call 100026c <_ZN12MotorHandler10sendByteMCEc> + //motor 2 + sendByteMC(MOTOR_START_BYTE); + 100041c: e13fff17 ldw r4,-4(fp) + 1000420: 017fe004 movi r5,-128 + 1000424: 100026c0 call 100026c <_ZN12MotorHandler10sendByteMCEc> + sendByteMC(MOTOR_DEVICE_TYPE); + 1000428: e13fff17 ldw r4,-4(fp) + 100042c: 000b883a mov r5,zero + 1000430: 100026c0 call 100026c <_ZN12MotorHandler10sendByteMCEc> + sendByteMC(MOTOR_MOTOR3_BACKWARD); + 1000434: e13fff17 ldw r4,-4(fp) + 1000438: 01400184 movi r5,6 + 100043c: 100026c0 call 100026c <_ZN12MotorHandler10sendByteMCEc> + sendByteMC(MOTOR_CONST_SPEED); + 1000440: e13fff17 ldw r4,-4(fp) + 1000444: 014017c4 movi r5,95 + 1000448: 100026c0 call 100026c <_ZN12MotorHandler10sendByteMCEc> +} + 100044c: e037883a mov sp,fp + 1000450: dfc00117 ldw ra,4(sp) + 1000454: df000017 ldw fp,0(sp) + 1000458: dec00204 addi sp,sp,8 + 100045c: f800283a ret + +01000460 <_ZN12MotorHandler10mc_forwardEv>: + IOWR_ALTERA_AVALON_UART_TXDATA(UART_MC_BASE, msg); +} +/* + * Move rover forward by activating both motors + */ +void MotorHandler::mc_forward(){ + 1000460: defffd04 addi sp,sp,-12 + 1000464: dfc00215 stw ra,8(sp) + 1000468: df000115 stw fp,4(sp) + 100046c: df000104 addi fp,sp,4 + 1000470: e13fff15 stw r4,-4(fp) + //motor 1 + sendByteMC(MOTOR_START_BYTE); + 1000474: e13fff17 ldw r4,-4(fp) + 1000478: 017fe004 movi r5,-128 + 100047c: 100026c0 call 100026c <_ZN12MotorHandler10sendByteMCEc> + sendByteMC(MOTOR_DEVICE_TYPE); + 1000480: e13fff17 ldw r4,-4(fp) + 1000484: 000b883a mov r5,zero + 1000488: 100026c0 call 100026c <_ZN12MotorHandler10sendByteMCEc> + sendByteMC(MOTOR_MOTOR2_FORWARD); + 100048c: e13fff17 ldw r4,-4(fp) + 1000490: 01400144 movi r5,5 + 1000494: 100026c0 call 100026c <_ZN12MotorHandler10sendByteMCEc> + sendByteMC(MOTOR_CONST_SPEED); + 1000498: e13fff17 ldw r4,-4(fp) + 100049c: 014017c4 movi r5,95 + 10004a0: 100026c0 call 100026c <_ZN12MotorHandler10sendByteMCEc> + //motor 2 + sendByteMC(MOTOR_START_BYTE); + 10004a4: e13fff17 ldw r4,-4(fp) + 10004a8: 017fe004 movi r5,-128 + 10004ac: 100026c0 call 100026c <_ZN12MotorHandler10sendByteMCEc> + sendByteMC(MOTOR_DEVICE_TYPE); + 10004b0: e13fff17 ldw r4,-4(fp) + 10004b4: 000b883a mov r5,zero + 10004b8: 100026c0 call 100026c <_ZN12MotorHandler10sendByteMCEc> + sendByteMC(MOTOR_MOTOR3_FORWARD); + 10004bc: e13fff17 ldw r4,-4(fp) + 10004c0: 014001c4 movi r5,7 + 10004c4: 100026c0 call 100026c <_ZN12MotorHandler10sendByteMCEc> + sendByteMC(MOTOR_CONST_SPEED); + 10004c8: e13fff17 ldw r4,-4(fp) + 10004cc: 014017c4 movi r5,95 + 10004d0: 100026c0 call 100026c <_ZN12MotorHandler10sendByteMCEc> +} + 10004d4: e037883a mov sp,fp + 10004d8: dfc00117 ldw ra,4(sp) + 10004dc: df000017 ldw fp,0(sp) + 10004e0: dec00204 addi sp,sp,8 + 10004e4: f800283a ret + +010004e8 <_ZN12MotorHandlerD0Ev>: +MotorHandler::MotorHandler() { + // TODO Auto-generated constructor stub + +} + +MotorHandler::~MotorHandler() { + 10004e8: defffd04 addi sp,sp,-12 + 10004ec: dfc00215 stw ra,8(sp) + 10004f0: df000115 stw fp,4(sp) + 10004f4: df000104 addi fp,sp,4 + 10004f8: e13fff15 stw r4,-4(fp) + 10004fc: 00c040b4 movhi r3,258 + 1000500: 18e2f704 addi r3,r3,-29732 + 1000504: e0bfff17 ldw r2,-4(fp) + 1000508: 10c00015 stw r3,0(r2) + // TODO Auto-generated destructor stub +} + 100050c: 00800044 movi r2,1 + 1000510: 10803fcc andi r2,r2,255 + 1000514: 1005003a cmpeq r2,r2,zero + 1000518: 1000021e bne r2,zero,1000524 <_ZN12MotorHandlerD0Ev+0x3c> + 100051c: e13fff17 ldw r4,-4(fp) + 1000520: 1001b240 call 1001b24 <_ZdlPv> + 1000524: e037883a mov sp,fp + 1000528: dfc00117 ldw ra,4(sp) + 100052c: df000017 ldw fp,0(sp) + 1000530: dec00204 addi sp,sp,8 + 1000534: f800283a ret + +01000538 <_ZN12MotorHandlerD1Ev>: +MotorHandler::MotorHandler() { + // TODO Auto-generated constructor stub + +} + +MotorHandler::~MotorHandler() { + 1000538: defffd04 addi sp,sp,-12 + 100053c: dfc00215 stw ra,8(sp) + 1000540: df000115 stw fp,4(sp) + 1000544: df000104 addi fp,sp,4 + 1000548: e13fff15 stw r4,-4(fp) + 100054c: 00c040b4 movhi r3,258 + 1000550: 18e2f704 addi r3,r3,-29732 + 1000554: e0bfff17 ldw r2,-4(fp) + 1000558: 10c00015 stw r3,0(r2) + // TODO Auto-generated destructor stub +} + 100055c: 0005883a mov r2,zero + 1000560: 10803fcc andi r2,r2,255 + 1000564: 1005003a cmpeq r2,r2,zero + 1000568: 1000021e bne r2,zero,1000574 <_ZN12MotorHandlerD1Ev+0x3c> + 100056c: e13fff17 ldw r4,-4(fp) + 1000570: 1001b240 call 1001b24 <_ZdlPv> + 1000574: e037883a mov sp,fp + 1000578: dfc00117 ldw ra,4(sp) + 100057c: df000017 ldw fp,0(sp) + 1000580: dec00204 addi sp,sp,8 + 1000584: f800283a ret + +01000588 <_ZN12MotorHandlerD2Ev>: +MotorHandler::MotorHandler() { + // TODO Auto-generated constructor stub + +} + +MotorHandler::~MotorHandler() { + 1000588: defffd04 addi sp,sp,-12 + 100058c: dfc00215 stw ra,8(sp) + 1000590: df000115 stw fp,4(sp) + 1000594: df000104 addi fp,sp,4 + 1000598: e13fff15 stw r4,-4(fp) + 100059c: 00c040b4 movhi r3,258 + 10005a0: 18e2f704 addi r3,r3,-29732 + 10005a4: e0bfff17 ldw r2,-4(fp) + 10005a8: 10c00015 stw r3,0(r2) + // TODO Auto-generated destructor stub +} + 10005ac: 0005883a mov r2,zero + 10005b0: 10803fcc andi r2,r2,255 + 10005b4: 1005003a cmpeq r2,r2,zero + 10005b8: 1000021e bne r2,zero,10005c4 <_ZN12MotorHandlerD2Ev+0x3c> + 10005bc: e13fff17 ldw r4,-4(fp) + 10005c0: 1001b240 call 1001b24 <_ZdlPv> + 10005c4: e037883a mov sp,fp + 10005c8: dfc00117 ldw ra,4(sp) + 10005cc: df000017 ldw fp,0(sp) + 10005d0: dec00204 addi sp,sp,8 + 10005d4: f800283a ret + +010005d8 <_Z41__static_initialization_and_destruction_0ii>: + if (status == OK) { + OSStart(); + } + + return 0; +} + 10005d8: deffe404 addi sp,sp,-112 + 10005dc: dfc01b15 stw ra,108(sp) + 10005e0: df001a15 stw fp,104(sp) + 10005e4: ddc01915 stw r23,100(sp) + 10005e8: dd801815 stw r22,96(sp) + 10005ec: dd401715 stw r21,92(sp) + 10005f0: dd001615 stw r20,88(sp) + 10005f4: dcc01515 stw r19,84(sp) + 10005f8: dc801415 stw r18,80(sp) + 10005fc: dc401315 stw r17,76(sp) + 1000600: dc001215 stw r16,72(sp) + 1000604: df001204 addi fp,sp,72 + 1000608: e13fee15 stw r4,-72(fp) + 100060c: e17fef15 stw r5,-68(fp) + 1000610: 00804034 movhi r2,256 + 1000614: 1084d504 addi r2,r2,4948 + 1000618: e0bff615 stw r2,-40(fp) + 100061c: 008040b4 movhi r2,258 + 1000620: 10a2d804 addi r2,r2,-29856 + 1000624: e0bff715 stw r2,-36(fp) + 1000628: e0bff804 addi r2,fp,-32 + 100062c: e0ffee04 addi r3,fp,-72 + 1000630: 10c00015 stw r3,0(r2) + 1000634: 00c04034 movhi r3,256 + 1000638: 18c1a504 addi r3,r3,1684 + 100063c: 10c00115 stw r3,4(r2) + 1000640: 16c00215 stw sp,8(r2) + 1000644: e13ff004 addi r4,fp,-64 + 1000648: 10022540 call 1002254 <_Unwind_SjLj_Register> + 100064c: e0bfee17 ldw r2,-72(fp) + 1000650: 10800058 cmpnei r2,r2,1 + 1000654: 10001c1e bne r2,zero,10006c8 <_Z41__static_initialization_and_destruction_0ii+0xf0> + 1000658: e0ffef17 ldw r3,-68(fp) + 100065c: 00bfffd4 movui r2,65535 + 1000660: 1880191e bne r3,r2,10006c8 <_Z41__static_initialization_and_destruction_0ii+0xf0> +#include "altera_avalon_uart_regs.h" +#include "sys/alt_irq.h" +#include "alt_types.h" +#include "MotorHandler.h" + +MotorHandler * motorHandler = new MotorHandler(); + 1000664: 00bfffc4 movi r2,-1 + 1000668: e0bff115 stw r2,-60(fp) + 100066c: 01000104 movi r4,4 + 1000670: 100200c0 call 100200c <_Znwm> + 1000674: e0bffe15 stw r2,-8(fp) + 1000678: 00800044 movi r2,1 + 100067c: e0bff115 stw r2,-60(fp) + 1000680: e13ffe17 ldw r4,-8(fp) + 1000684: 100023c0 call 100023c <_ZN12MotorHandlerC1Ev> + 1000688: e0bffe17 ldw r2,-8(fp) + 100068c: d0a76d15 stw r2,-25164(gp) + 1000690: 00000d06 br 10006c8 <_Z41__static_initialization_and_destruction_0ii+0xf0> + 1000694: e7001204 addi fp,fp,72 + 1000698: e0fff217 ldw r3,-56(fp) + 100069c: e0ffff15 stw r3,-4(fp) + 10006a0: e0bfff17 ldw r2,-4(fp) + 10006a4: e0bffd15 stw r2,-12(fp) + 10006a8: e13ffe17 ldw r4,-8(fp) + 10006ac: 1001b240 call 1001b24 <_ZdlPv> + 10006b0: e0fffd17 ldw r3,-12(fp) + 10006b4: e0ffff15 stw r3,-4(fp) + 10006b8: 00bfffc4 movi r2,-1 + 10006bc: e0bff115 stw r2,-60(fp) + 10006c0: e13fff17 ldw r4,-4(fp) + 10006c4: 10025200 call 1002520 <_Unwind_SjLj_Resume> + 10006c8: e13ff004 addi r4,fp,-64 + 10006cc: 10022640 call 1002264 <_Unwind_SjLj_Unregister> + if (status == OK) { + OSStart(); + } + + return 0; +} + 10006d0: e037883a mov sp,fp + 10006d4: dfc00917 ldw ra,36(sp) + 10006d8: df000817 ldw fp,32(sp) + 10006dc: ddc00717 ldw r23,28(sp) + 10006e0: dd800617 ldw r22,24(sp) + 10006e4: dd400517 ldw r21,20(sp) + 10006e8: dd000417 ldw r20,16(sp) + 10006ec: dcc00317 ldw r19,12(sp) + 10006f0: dc800217 ldw r18,8(sp) + 10006f4: dc400117 ldw r17,4(sp) + 10006f8: dc000017 ldw r16,0(sp) + 10006fc: dec00a04 addi sp,sp,40 + 1000700: f800283a ret + +01000704 <_GLOBAL__I_motorHandler>: + + 1000704: defffe04 addi sp,sp,-8 + 1000708: dfc00115 stw ra,4(sp) + 100070c: df000015 stw fp,0(sp) + 1000710: d839883a mov fp,sp + 1000714: 01000044 movi r4,1 + 1000718: 017fffd4 movui r5,65535 + 100071c: 10005d80 call 10005d8 <_Z41__static_initialization_and_destruction_0ii> + 1000720: e037883a mov sp,fp + 1000724: dfc00117 ldw ra,4(sp) + 1000728: df000017 ldw fp,0(sp) + 100072c: dec00204 addi sp,sp,8 + 1000730: f800283a ret + +01000734 <_Z10wifi_writePci>: + +void wifi_wait() { + OSTimeDlyHMSM(0, 0, WIFI_GUARD_TIME, 0); +} + +void wifi_write(char *message, int length) { + 1000734: defffc04 addi sp,sp,-16 + 1000738: df000315 stw fp,12(sp) + 100073c: df000304 addi fp,sp,12 + 1000740: e13ffe15 stw r4,-8(fp) + 1000744: e17fff15 stw r5,-4(fp) + int i; + for (i = 0; i < length; i++) { + 1000748: e03ffd15 stw zero,-12(fp) + 100074c: 00000e06 br 1000788 <_Z10wifi_writePci+0x54> + IOWR_ALTERA_AVALON_UART_TXDATA(UART_WIFI_BASE, message[i]); + 1000750: e0bffd17 ldw r2,-12(fp) + 1000754: 1007883a mov r3,r2 + 1000758: e0bffe17 ldw r2,-8(fp) + 100075c: 1885883a add r2,r3,r2 + 1000760: 10800003 ldbu r2,0(r2) + 1000764: 10c03fcc andi r3,r2,255 + 1000768: 18c0201c xori r3,r3,128 + 100076c: 18ffe004 addi r3,r3,-128 + 1000770: 00808034 movhi r2,512 + 1000774: 10841104 addi r2,r2,4164 + 1000778: 10c00035 stwio r3,0(r2) + OSTimeDlyHMSM(0, 0, WIFI_GUARD_TIME, 0); +} + +void wifi_write(char *message, int length) { + int i; + for (i = 0; i < length; i++) { + 100077c: e0bffd17 ldw r2,-12(fp) + 1000780: 10800044 addi r2,r2,1 + 1000784: e0bffd15 stw r2,-12(fp) + 1000788: e0fffd17 ldw r3,-12(fp) + 100078c: e0bfff17 ldw r2,-4(fp) + 1000790: 18bfef16 blt r3,r2,1000750 <_Z10wifi_writePci+0x1c> + IOWR_ALTERA_AVALON_UART_TXDATA(UART_WIFI_BASE, message[i]); + } +} + 1000794: e037883a mov sp,fp + 1000798: df000017 ldw fp,0(sp) + 100079c: dec00104 addi sp,sp,4 + 10007a0: f800283a ret + +010007a4 <_Z10queue_initv>: + motorHandler->mc_stop(); +} + +// ==== GENERAL + +void queue_init() { + 10007a4: defffe04 addi sp,sp,-8 + 10007a8: dfc00115 stw ra,4(sp) + 10007ac: df000015 stw fp,0(sp) + 10007b0: d839883a mov fp,sp + ir_queue = OSQCreate((void**)&ir_messages, IR_MAX_MESSAGES); + 10007b4: 010040b4 movhi r4,258 + 10007b8: 210b2704 addi r4,r4,11420 + 10007bc: 01400104 movi r5,4 + 10007c0: 10117c40 call 10117c4 + 10007c4: d0a76e15 stw r2,-25160(gp) +} + 10007c8: e037883a mov sp,fp + 10007cc: dfc00117 ldw ra,4(sp) + 10007d0: df000017 ldw fp,0(sp) + 10007d4: dec00204 addi sp,sp,8 + 10007d8: f800283a ret + +010007dc
: + +/* The main function creates the LCD task, registers the edge counter polling interrupt, + * and starts the OS. */ +int main(void) + 10007dc: defff804 addi sp,sp,-32 + 10007e0: dfc00715 stw ra,28(sp) + 10007e4: df000615 stw fp,24(sp) + 10007e8: df000604 addi fp,sp,24 +{ + int status; + // Initialize components. + queue_init(); + 10007ec: 10007a40 call 10007a4 <_Z10queue_initv> + IR_TASK_PRIORITY, + IR_TASK_PRIORITY, + ir_task_stk, + TASK_STACKSIZE, + NULL, + 0); + 10007f0: 00800044 movi r2,1 + 10007f4: d8800015 stw r2,0(sp) + 10007f8: 008040b4 movhi r2,258 + 10007fc: 10b32704 addi r2,r2,-13156 + 1000800: d8800115 stw r2,4(sp) + 1000804: 00820004 movi r2,2048 + 1000808: d8800215 stw r2,8(sp) + 100080c: d8000315 stw zero,12(sp) + 1000810: d8000415 stw zero,16(sp) + 1000814: 01004034 movhi r4,256 + 1000818: 21028804 addi r4,r4,2592 + 100081c: 000b883a mov r5,zero + 1000820: 018040b4 movhi r6,258 + 1000824: 31bb2604 addi r6,r6,-4968 + 1000828: 01c00044 movi r7,1 + 100082c: 1013cb40 call 1013cb4 + WIFI_TASK_PRIORITY, + WIFI_TASK_PRIORITY, + wifi_task_stk, + TASK_STACKSIZE, + NULL, + 0); + 1000830: 00800084 movi r2,2 + 1000834: d8800015 stw r2,0(sp) + 1000838: 008040b4 movhi r2,258 + 100083c: 10bb2704 addi r2,r2,-4964 + 1000840: d8800115 stw r2,4(sp) + 1000844: 00820004 movi r2,2048 + 1000848: d8800215 stw r2,8(sp) + 100084c: d8000315 stw zero,12(sp) + 1000850: d8000415 stw zero,16(sp) + 1000854: 01004034 movhi r4,256 + 1000858: 21027404 addi r4,r4,2512 + 100085c: 000b883a mov r5,zero + 1000860: 018040b4 movhi r6,258 + 1000864: 31832604 addi r6,r6,3224 + 1000868: 01c00084 movi r7,2 + 100086c: 1013cb40 call 1013cb4 + MC_TASK_PRIORITY, + MC_TASK_PRIORITY, + mc_task_stk, + TASK_STACKSIZE, + NULL, + 0); + 1000870: 00800084 movi r2,2 + 1000874: d8800015 stw r2,0(sp) + 1000878: 008040b4 movhi r2,258 + 100087c: 10832704 addi r2,r2,3228 + 1000880: d8800115 stw r2,4(sp) + 1000884: 00820004 movi r2,2048 + 1000888: d8800215 stw r2,8(sp) + 100088c: d8000315 stw zero,12(sp) + 1000890: d8000415 stw zero,16(sp) + 1000894: 01004034 movhi r4,256 + 1000898: 21024804 addi r4,r4,2336 + 100089c: 000b883a mov r5,zero + 10008a0: 018040b4 movhi r6,258 + 10008a4: 318b2604 addi r6,r6,11416 + 10008a8: 01c00084 movi r7,2 + 10008ac: 1013cb40 call 1013cb4 + isr_on_ir_pushbutton, + NULL, + NULL);*/ + + // Enable key interrupts. + IOWR_ALTERA_AVALON_PIO_IRQ_MASK(PIO_KEY_LEFT_BASE, PIO_KEY_LEFT_CAPTURE); + 10008b0: 00c08034 movhi r3,512 + 10008b4: 18c42a04 addi r3,r3,4264 + 10008b8: 00800044 movi r2,1 + 10008bc: 18800035 stwio r2,0(r3) + + // Start. + if (status == OK) { + 10008c0: e0bfff17 ldw r2,-4(fp) + 10008c4: 1004c03a cmpne r2,r2,zero + 10008c8: 1000011e bne r2,zero,10008d0 + OSStart(); + 10008cc: 100dee00 call 100dee0 + } + + return 0; + 10008d0: 0005883a mov r2,zero +} + 10008d4: e037883a mov sp,fp + 10008d8: dfc00117 ldw ra,4(sp) + 10008dc: df000017 ldw fp,0(sp) + 10008e0: dec00204 addi sp,sp,8 + 10008e4: f800283a ret + +010008e8 <_Z9wifi_waitv>: + +// ==== WIFI + +#define WIFI_GUARD_TIME 1 + +void wifi_wait() { + 10008e8: defffe04 addi sp,sp,-8 + 10008ec: dfc00115 stw ra,4(sp) + 10008f0: df000015 stw fp,0(sp) + 10008f4: d839883a mov fp,sp + OSTimeDlyHMSM(0, 0, WIFI_GUARD_TIME, 0); + 10008f8: 0009883a mov r4,zero + 10008fc: 000b883a mov r5,zero + 1000900: 01800044 movi r6,1 + 1000904: 000f883a mov r7,zero + 1000908: 10150f80 call 10150f8 +} + 100090c: e037883a mov sp,fp + 1000910: dfc00117 ldw ra,4(sp) + 1000914: df000017 ldw fp,0(sp) + 1000918: dec00204 addi sp,sp,8 + 100091c: f800283a ret + +01000920 <_Z7mc_taskPv>: + +// ==== MC + + +//====MotorContoller +void mc_task(void *pdata) + 1000920: defffd04 addi sp,sp,-12 + 1000924: dfc00215 stw ra,8(sp) + 1000928: df000115 stw fp,4(sp) + 100092c: df000104 addi fp,sp,4 + 1000930: e13fff15 stw r4,-4(fp) +{ + motorHandler->mc_forward(); + 1000934: d1276d17 ldw r4,-25164(gp) + 1000938: 10004600 call 1000460 <_ZN12MotorHandler10mc_forwardEv> + OSTimeDlyHMSM(0, 0, 4, 0); + 100093c: 0009883a mov r4,zero + 1000940: 000b883a mov r5,zero + 1000944: 01800104 movi r6,4 + 1000948: 000f883a mov r7,zero + 100094c: 10150f80 call 10150f8 + motorHandler->mc_stop(); + 1000950: d1276d17 ldw r4,-25164(gp) + 1000954: 10002a00 call 10002a0 <_ZN12MotorHandler7mc_stopEv> +} + 1000958: e037883a mov sp,fp + 100095c: dfc00117 ldw ra,4(sp) + 1000960: df000017 ldw fp,0(sp) + 1000964: dec00204 addi sp,sp,8 + 1000968: f800283a ret + +0100096c <_Z9wifi_readv>: + for (i = 0; i < length; i++) { + IOWR_ALTERA_AVALON_UART_TXDATA(UART_WIFI_BASE, message[i]); + } +} + +void wifi_read() { + 100096c: defffc04 addi sp,sp,-16 + 1000970: dfc00315 stw ra,12(sp) + 1000974: df000215 stw fp,8(sp) + 1000978: df000204 addi fp,sp,8 + int status = IORD_ALTERA_AVALON_UART_STATUS(UART_WIFI_BASE); + 100097c: 00808034 movhi r2,512 + 1000980: 10841204 addi r2,r2,4168 + 1000984: 10800037 ldwio r2,0(r2) + 1000988: e0bfff15 stw r2,-4(fp) + printf("Wifi status: %d\n", status); + 100098c: 010040b4 movhi r4,258 + 1000990: 2122fd04 addi r4,r4,-29708 + 1000994: e17fff17 ldw r5,-4(fp) + 1000998: 1002fb40 call 1002fb4 + char c = IORD_ALTERA_AVALON_UART_RXDATA(UART_WIFI_BASE); + 100099c: 00808034 movhi r2,512 + 10009a0: 10841004 addi r2,r2,4160 + 10009a4: 10800037 ldwio r2,0(r2) + 10009a8: e0bffe05 stb r2,-8(fp) + printf("Wifi: %c\n", c); + 10009ac: e17ffe07 ldb r5,-8(fp) + 10009b0: 010040b4 movhi r4,258 + 10009b4: 21230204 addi r4,r4,-29688 + 10009b8: 1002fb40 call 1002fb4 +} + 10009bc: e037883a mov sp,fp + 10009c0: dfc00117 ldw ra,4(sp) + 10009c4: df000017 ldw fp,0(sp) + 10009c8: dec00204 addi sp,sp,8 + 10009cc: f800283a ret + +010009d0 <_Z9wifi_taskPv>: + +void wifi_task(void *pdata) + 10009d0: defffd04 addi sp,sp,-12 + 10009d4: dfc00215 stw ra,8(sp) + 10009d8: df000115 stw fp,4(sp) + 10009dc: df000104 addi fp,sp,4 + 10009e0: e13fff15 stw r4,-4(fp) +{ + printf("Started wifi task\n"); + 10009e4: 010040b4 movhi r4,258 + 10009e8: 21230504 addi r4,r4,-29676 + 10009ec: 10030cc0 call 10030cc + wifi_wait(); + 10009f0: 10008e80 call 10008e8 <_Z9wifi_waitv> + wifi_write("+++", 3); + 10009f4: 010040b4 movhi r4,258 + 10009f8: 21230a04 addi r4,r4,-29656 + 10009fc: 014000c4 movi r5,3 + 1000a00: 10007340 call 1000734 <_Z10wifi_writePci> + wifi_wait(); + 1000a04: 10008e80 call 10008e8 <_Z9wifi_waitv> + wifi_read(); + 1000a08: 100096c0 call 100096c <_Z9wifi_readv> +} + 1000a0c: e037883a mov sp,fp + 1000a10: dfc00117 ldw ra,4(sp) + 1000a14: df000017 ldw fp,0(sp) + 1000a18: dec00204 addi sp,sp,8 + 1000a1c: f800283a ret + +01000a20 <_Z7ir_taskPv>: + // Mask to mark the end of the ISR. + IOWR_ALTERA_AVALON_PIO_EDGE_CAP(PIO_KEY_LEFT_BASE, PIO_KEY_LEFT_BIT_CLEARING_EDGE_REGISTER); +} + +/* Controllers the IR emitter based on the value of the pushbutton. */ +void ir_task(void* pdata) + 1000a20: defffb04 addi sp,sp,-20 + 1000a24: dfc00415 stw ra,16(sp) + 1000a28: df000315 stw fp,12(sp) + 1000a2c: df000304 addi fp,sp,12 + 1000a30: e13fff15 stw r4,-4(fp) + 1000a34: 00000006 br 1000a38 <_Z7ir_taskPv+0x18> +{ + INT8U err; + while (1) + { + // Read the value from the queue. + int status = IR_QUEUE_RECEIVE_BASE - (int)OSQPend(ir_queue, WAIT_FOREVER, &err); + 1000a38: d1276e17 ldw r4,-25160(gp) + 1000a3c: e1bffe04 addi r6,fp,-8 + 1000a40: 000b883a mov r5,zero + 1000a44: 1011da00 call 1011da0 + 1000a48: 1007883a mov r3,r2 + 1000a4c: 00800084 movi r2,2 + 1000a50: 10c5c83a sub r2,r2,r3 + 1000a54: e0bffd15 stw r2,-12(fp) + if (err == OS_NO_ERR) { + 1000a58: e0bffe03 ldbu r2,-8(fp) + 1000a5c: 10803fcc andi r2,r2,255 + 1000a60: 1004c03a cmpne r2,r2,zero + 1000a64: 103ff41e bne r2,zero,1000a38 <_Z7ir_taskPv+0x18> + // Print the result and send it to the emitter. + printf("IR: %d\n", status); + 1000a68: 010040b4 movhi r4,258 + 1000a6c: 21230b04 addi r4,r4,-29652 + 1000a70: e17ffd17 ldw r5,-12(fp) + 1000a74: 1002fb40 call 1002fb4 + IOWR_ALTERA_AVALON_PIO_DATA(PIO_IR_EMITTER_BASE, status); + 1000a78: 00c08034 movhi r3,512 + 1000a7c: 18c42004 addi r3,r3,4224 + 1000a80: e0bffd17 ldw r2,-12(fp) + 1000a84: 18800035 stwio r2,0(r3) + +/* Controllers the IR emitter based on the value of the pushbutton. */ +void ir_task(void* pdata) +{ + INT8U err; + while (1) + 1000a88: 003feb06 br 1000a38 <_Z7ir_taskPv+0x18> + +01000a8c <_ZNK10__cxxabiv117__class_type_info11__do_upcastEPKS0_PPv>: + 1000a8c: 20c00017 ldw r3,0(r4) + 1000a90: defffa04 addi sp,sp,-24 + 1000a94: dc000415 stw r16,16(sp) + 1000a98: 1a000617 ldw r8,24(r3) + 1000a9c: 3021883a mov r16,r6 + 1000aa0: 31800017 ldw r6,0(r6) + 1000aa4: 00800404 movi r2,16 + 1000aa8: dfc00515 stw ra,20(sp) + 1000aac: d8800215 stw r2,8(sp) + 1000ab0: d8000015 stw zero,0(sp) + 1000ab4: d8000115 stw zero,4(sp) + 1000ab8: d8000315 stw zero,12(sp) + 1000abc: d80f883a mov r7,sp + 1000ac0: 403ee83a callr r8 + 1000ac4: d8800117 ldw r2,4(sp) + 1000ac8: 00c00184 movi r3,6 + 1000acc: 0009883a mov r4,zero + 1000ad0: 1080018c andi r2,r2,6 + 1000ad4: 10c0031e bne r2,r3,1000ae4 <_ZNK10__cxxabiv117__class_type_info11__do_upcastEPKS0_PPv+0x58> + 1000ad8: d8800017 ldw r2,0(sp) + 1000adc: 01000044 movi r4,1 + 1000ae0: 80800015 stw r2,0(r16) + 1000ae4: 2005883a mov r2,r4 + 1000ae8: dfc00517 ldw ra,20(sp) + 1000aec: dc000417 ldw r16,16(sp) + 1000af0: dec00604 addi sp,sp,24 + 1000af4: f800283a ret + +01000af8 <_ZNK10__cxxabiv117__class_type_info20__do_find_public_srcElPKvPKS0_S2_>: + 1000af8: d8800017 ldw r2,0(sp) + 1000afc: 00c00184 movi r3,6 + 1000b00: 1180021e bne r2,r6,1000b0c <_ZNK10__cxxabiv117__class_type_info20__do_find_public_srcElPKvPKS0_S2_+0x14> + 1000b04: 1805883a mov r2,r3 + 1000b08: f800283a ret + 1000b0c: 00c00044 movi r3,1 + 1000b10: 1805883a mov r2,r3 + 1000b14: f800283a ret + +01000b18 <_ZN10__cxxabiv117__class_type_infoD0Ev>: + 1000b18: defffe04 addi sp,sp,-8 + 1000b1c: 008040b4 movhi r2,258 + 1000b20: 10a30f04 addi r2,r2,-29636 + 1000b24: dc400015 stw r17,0(sp) + 1000b28: 20800015 stw r2,0(r4) + 1000b2c: 2023883a mov r17,r4 + 1000b30: dfc00115 stw ra,4(sp) + 1000b34: 1001e880 call 1001e88 <_ZNSt9type_infoD2Ev> + 1000b38: 8809883a mov r4,r17 + 1000b3c: dfc00117 ldw ra,4(sp) + 1000b40: dc400017 ldw r17,0(sp) + 1000b44: dec00204 addi sp,sp,8 + 1000b48: 1001b241 jmpi 1001b24 <_ZdlPv> + +01000b4c <_ZN10__cxxabiv117__class_type_infoD1Ev>: + 1000b4c: 008040b4 movhi r2,258 + 1000b50: 10a30f04 addi r2,r2,-29636 + 1000b54: 20800015 stw r2,0(r4) + 1000b58: 1001e881 jmpi 1001e88 <_ZNSt9type_infoD2Ev> + +01000b5c <_ZN10__cxxabiv117__class_type_infoD2Ev>: + 1000b5c: 008040b4 movhi r2,258 + 1000b60: 10a30f04 addi r2,r2,-29636 + 1000b64: 20800015 stw r2,0(r4) + 1000b68: 1001e881 jmpi 1001e88 <_ZNSt9type_infoD2Ev> + +01000b6c <_ZNK10__cxxabiv117__class_type_info10__do_catchEPKSt9type_infoPPvj>: + 1000b6c: 2811883a mov r8,r5 + 1000b70: 20c00117 ldw r3,4(r4) + 1000b74: 40800117 ldw r2,4(r8) + 1000b78: deffff04 addi sp,sp,-4 + 1000b7c: dfc00015 stw ra,0(sp) + 1000b80: 200b883a mov r5,r4 + 1000b84: 02400044 movi r9,1 + 1000b88: 18800426 beq r3,r2,1000b9c <_ZNK10__cxxabiv117__class_type_info10__do_catchEPKSt9type_infoPPvj+0x30> + 1000b8c: 008000c4 movi r2,3 + 1000b90: 4009883a mov r4,r8 + 1000b94: 0013883a mov r9,zero + 1000b98: 11c0042e bgeu r2,r7,1000bac <_ZNK10__cxxabiv117__class_type_info10__do_catchEPKSt9type_infoPPvj+0x40> + 1000b9c: 4805883a mov r2,r9 + 1000ba0: dfc00017 ldw ra,0(sp) + 1000ba4: dec00104 addi sp,sp,4 + 1000ba8: f800283a ret + 1000bac: 40800017 ldw r2,0(r8) + 1000bb0: 10c00517 ldw r3,20(r2) + 1000bb4: 183ee83a callr r3 + 1000bb8: 12403fcc andi r9,r2,255 + 1000bbc: 4805883a mov r2,r9 + 1000bc0: dfc00017 ldw ra,0(sp) + 1000bc4: dec00104 addi sp,sp,4 + 1000bc8: f800283a ret + +01000bcc <_ZNK10__cxxabiv117__class_type_info11__do_upcastEPKS0_PKvRNS0_15__upcast_resultE>: + 1000bcc: 20c00117 ldw r3,4(r4) + 1000bd0: 28800117 ldw r2,4(r5) + 1000bd4: 0009883a mov r4,zero + 1000bd8: 1880061e bne r3,r2,1000bf4 <_ZNK10__cxxabiv117__class_type_info11__do_upcastEPKS0_PKvRNS0_15__upcast_resultE+0x28> + 1000bdc: 00800184 movi r2,6 + 1000be0: 38800115 stw r2,4(r7) + 1000be4: 00800204 movi r2,8 + 1000be8: 39800015 stw r6,0(r7) + 1000bec: 38800315 stw r2,12(r7) + 1000bf0: 01000044 movi r4,1 + 1000bf4: 2005883a mov r2,r4 + 1000bf8: f800283a ret + +01000bfc <_ZNK10__cxxabiv117__class_type_info12__do_dyncastElNS0_10__sub_kindEPKS0_PKvS3_S5_RNS0_16__dyncast_resultE>: + 1000bfc: da000017 ldw r8,0(sp) + 1000c00: d8800217 ldw r2,8(sp) + 1000c04: d9400317 ldw r5,12(sp) + 1000c08: 40800926 beq r8,r2,1000c30 <_ZNK10__cxxabiv117__class_type_info12__do_dyncastElNS0_10__sub_kindEPKS0_PKvS3_S5_RNS0_16__dyncast_resultE+0x34> + 1000c0c: 21000117 ldw r4,4(r4) + 1000c10: 38800117 ldw r2,4(r7) + 1000c14: 2080041e bne r4,r2,1000c28 <_ZNK10__cxxabiv117__class_type_info12__do_dyncastElNS0_10__sub_kindEPKS0_PKvS3_S5_RNS0_16__dyncast_resultE+0x2c> + 1000c18: 00800044 movi r2,1 + 1000c1c: 28800315 stw r2,12(r5) + 1000c20: 2a000015 stw r8,0(r5) + 1000c24: 29800115 stw r6,4(r5) + 1000c28: 0005883a mov r2,zero + 1000c2c: f800283a ret + 1000c30: d8800117 ldw r2,4(sp) + 1000c34: 21000117 ldw r4,4(r4) + 1000c38: 10c00117 ldw r3,4(r2) + 1000c3c: 20fff41e bne r4,r3,1000c10 <_ZNK10__cxxabiv117__class_type_info12__do_dyncastElNS0_10__sub_kindEPKS0_PKvS3_S5_RNS0_16__dyncast_resultE+0x14> + 1000c40: 29800215 stw r6,8(r5) + 1000c44: 003ff806 br 1000c28 <_ZNK10__cxxabiv117__class_type_info12__do_dyncastElNS0_10__sub_kindEPKS0_PKvS3_S5_RNS0_16__dyncast_resultE+0x2c> + +01000c48 <_Z12read_uleb128PKhPj>: + 1000c48: 000d883a mov r6,zero + 1000c4c: 000f883a mov r7,zero + 1000c50: 20c00007 ldb r3,0(r4) + 1000c54: 21000044 addi r4,r4,1 + 1000c58: 18801fcc andi r2,r3,127 + 1000c5c: 1184983a sll r2,r2,r6 + 1000c60: 318001c4 addi r6,r6,7 + 1000c64: 388eb03a or r7,r7,r2 + 1000c68: 183ff916 blt r3,zero,1000c50 <_Z12read_uleb128PKhPj+0x8> + 1000c6c: 2005883a mov r2,r4 + 1000c70: 29c00015 stw r7,0(r5) + 1000c74: f800283a ret + +01000c78 <_Z12read_sleb128PKhPi>: + 1000c78: 000f883a mov r7,zero + 1000c7c: 0011883a mov r8,zero + 1000c80: 20c00007 ldb r3,0(r4) + 1000c84: 21000044 addi r4,r4,1 + 1000c88: 19803fcc andi r6,r3,255 + 1000c8c: 30801fcc andi r2,r6,127 + 1000c90: 11c4983a sll r2,r2,r7 + 1000c94: 39c001c4 addi r7,r7,7 + 1000c98: 4090b03a or r8,r8,r2 + 1000c9c: 183ff816 blt r3,zero,1000c80 <_Z12read_sleb128PKhPi+0x8> + 1000ca0: 008007c4 movi r2,31 + 1000ca4: 11c00636 bltu r2,r7,1000cc0 <_Z12read_sleb128PKhPi+0x48> + 1000ca8: 3080100c andi r2,r6,64 + 1000cac: 10000426 beq r2,zero,1000cc0 <_Z12read_sleb128PKhPi+0x48> + 1000cb0: 00800044 movi r2,1 + 1000cb4: 11c4983a sll r2,r2,r7 + 1000cb8: 0085c83a sub r2,zero,r2 + 1000cbc: 4090b03a or r8,r8,r2 + 1000cc0: 2005883a mov r2,r4 + 1000cc4: 2a000015 stw r8,0(r5) + 1000cc8: f800283a ret + +01000ccc <_Z16get_adjusted_ptrPKSt9type_infoS1_PPv>: + 1000ccc: 28800017 ldw r2,0(r5) + 1000cd0: defffb04 addi sp,sp,-20 + 1000cd4: 30c00017 ldw r3,0(r6) + 1000cd8: dc400215 stw r17,8(sp) + 1000cdc: 2823883a mov r17,r5 + 1000ce0: 11400217 ldw r5,8(r2) + 1000ce4: dc800315 stw r18,12(sp) + 1000ce8: dc000115 stw r16,4(sp) + 1000cec: dfc00415 stw ra,16(sp) + 1000cf0: 2021883a mov r16,r4 + 1000cf4: d8c00015 stw r3,0(sp) + 1000cf8: 8809883a mov r4,r17 + 1000cfc: 3025883a mov r18,r6 + 1000d00: 283ee83a callr r5 + 1000d04: 10803fcc andi r2,r2,255 + 1000d08: 880b883a mov r5,r17 + 1000d0c: 8009883a mov r4,r16 + 1000d10: d80d883a mov r6,sp + 1000d14: 01c00044 movi r7,1 + 1000d18: 10000326 beq r2,zero,1000d28 <_Z16get_adjusted_ptrPKSt9type_infoS1_PPv+0x5c> + 1000d1c: d8800017 ldw r2,0(sp) + 1000d20: 10c00017 ldw r3,0(r2) + 1000d24: d8c00015 stw r3,0(sp) + 1000d28: 80800017 ldw r2,0(r16) + 1000d2c: 10c00417 ldw r3,16(r2) + 1000d30: 183ee83a callr r3 + 1000d34: 10803fcc andi r2,r2,255 + 1000d38: 0007883a mov r3,zero + 1000d3c: 10000326 beq r2,zero,1000d4c <_Z16get_adjusted_ptrPKSt9type_infoS1_PPv+0x80> + 1000d40: d8800017 ldw r2,0(sp) + 1000d44: 00c00044 movi r3,1 + 1000d48: 90800015 stw r2,0(r18) + 1000d4c: 1805883a mov r2,r3 + 1000d50: dfc00417 ldw ra,16(sp) + 1000d54: dc800317 ldw r18,12(sp) + 1000d58: dc400217 ldw r17,8(sp) + 1000d5c: dc000117 ldw r16,4(sp) + 1000d60: dec00504 addi sp,sp,20 + 1000d64: f800283a ret + +01000d68 <_Z28read_encoded_value_with_basehjPKhPj>: + 1000d68: defff904 addi sp,sp,-28 + 1000d6c: dc400215 stw r17,8(sp) + 1000d70: 00801404 movi r2,80 + 1000d74: 24403fcc andi r17,r4,255 + 1000d78: dd000515 stw r20,20(sp) + 1000d7c: dcc00415 stw r19,16(sp) + 1000d80: dc800315 stw r18,12(sp) + 1000d84: dc000115 stw r16,4(sp) + 1000d88: dfc00615 stw ra,24(sp) + 1000d8c: 2025883a mov r18,r4 + 1000d90: 2829883a mov r20,r5 + 1000d94: 3021883a mov r16,r6 + 1000d98: 3827883a mov r19,r7 + 1000d9c: 88801826 beq r17,r2,1000e00 <_Z28read_encoded_value_with_basehjPKhPj+0x98> + 1000da0: 88c003cc andi r3,r17,15 + 1000da4: 00800304 movi r2,12 + 1000da8: 10c0012e bgeu r2,r3,1000db0 <_Z28read_encoded_value_with_basehjPKhPj+0x48> + 1000dac: 100279c0 call 100279c + 1000db0: 18c5883a add r2,r3,r3 + 1000db4: 1085883a add r2,r2,r2 + 1000db8: 00c04034 movhi r3,256 + 1000dbc: 18c37304 addi r3,r3,3532 + 1000dc0: 10c5883a add r2,r2,r3 + 1000dc4: 11000017 ldw r4,0(r2) + 1000dc8: 2000683a jmp r4 + 1000dcc: 01000e3c xorhi r4,zero,56 + 1000dd0: 01000f24 muli r4,zero,60 + 1000dd4: 01000ed0 cmplti r4,zero,59 + 1000dd8: 01000e3c xorhi r4,zero,56 + 1000ddc: 01000e94 movui r4,58 + 1000de0: 01000dac andhi r4,zero,54 + 1000de4: 01000dac andhi r4,zero,54 + 1000de8: 01000dac andhi r4,zero,54 + 1000dec: 01000dac andhi r4,zero,54 + 1000df0: 01000f0c andi r4,zero,60 + 1000df4: 01000ee8 cmpgeui r4,zero,59 + 1000df8: 01000e3c xorhi r4,zero,56 + 1000dfc: 01000e94 movui r4,58 + 1000e00: 308000c4 addi r2,r6,3 + 1000e04: 00ffff04 movi r3,-4 + 1000e08: 10c4703a and r2,r2,r3 + 1000e0c: 11000017 ldw r4,0(r2) + 1000e10: 11400104 addi r5,r2,4 + 1000e14: 2805883a mov r2,r5 + 1000e18: 99000015 stw r4,0(r19) + 1000e1c: dfc00617 ldw ra,24(sp) + 1000e20: dd000517 ldw r20,20(sp) + 1000e24: dcc00417 ldw r19,16(sp) + 1000e28: dc800317 ldw r18,12(sp) + 1000e2c: dc400217 ldw r17,8(sp) + 1000e30: dc000117 ldw r16,4(sp) + 1000e34: dec00704 addi sp,sp,28 + 1000e38: f800283a ret + 1000e3c: 30800043 ldbu r2,1(r6) + 1000e40: 30c00083 ldbu r3,2(r6) + 1000e44: 310000c3 ldbu r4,3(r6) + 1000e48: 31400003 ldbu r5,0(r6) + 1000e4c: 1004923a slli r2,r2,8 + 1000e50: 1806943a slli r3,r3,16 + 1000e54: 2008963a slli r4,r4,24 + 1000e58: 1144b03a or r2,r2,r5 + 1000e5c: 1886b03a or r3,r3,r2 + 1000e60: 20c8b03a or r4,r4,r3 + 1000e64: 31400104 addi r5,r6,4 + 1000e68: 203fea26 beq r4,zero,1000e14 <_Z28read_encoded_value_with_basehjPKhPj+0xac> + 1000e6c: 88c01c0c andi r3,r17,112 + 1000e70: 00800404 movi r2,16 + 1000e74: 18801426 beq r3,r2,1000ec8 <_Z28read_encoded_value_with_basehjPKhPj+0x160> + 1000e78: 90803fcc andi r2,r18,255 + 1000e7c: 1080201c xori r2,r2,128 + 1000e80: 10bfe004 addi r2,r2,-128 + 1000e84: 2509883a add r4,r4,r20 + 1000e88: 103fe20e bge r2,zero,1000e14 <_Z28read_encoded_value_with_basehjPKhPj+0xac> + 1000e8c: 21000017 ldw r4,0(r4) + 1000e90: 003fe006 br 1000e14 <_Z28read_encoded_value_with_basehjPKhPj+0xac> + 1000e94: 30800043 ldbu r2,1(r6) + 1000e98: 31800083 ldbu r6,2(r6) + 1000e9c: 820000c3 ldbu r8,3(r16) + 1000ea0: 1004923a slli r2,r2,8 + 1000ea4: 82400003 ldbu r9,0(r16) + 1000ea8: 300c943a slli r6,r6,16 + 1000eac: 4010963a slli r8,r8,24 + 1000eb0: 1244b03a or r2,r2,r9 + 1000eb4: 308cb03a or r6,r6,r2 + 1000eb8: 4184b03a or r2,r8,r6 + 1000ebc: 1009883a mov r4,r2 + 1000ec0: 81400204 addi r5,r16,8 + 1000ec4: 003fe806 br 1000e68 <_Z28read_encoded_value_with_basehjPKhPj+0x100> + 1000ec8: 8029883a mov r20,r16 + 1000ecc: 003fea06 br 1000e78 <_Z28read_encoded_value_with_basehjPKhPj+0x110> + 1000ed0: 30800043 ldbu r2,1(r6) + 1000ed4: 30c00003 ldbu r3,0(r6) + 1000ed8: 31400084 addi r5,r6,2 + 1000edc: 1004923a slli r2,r2,8 + 1000ee0: 10c8b03a or r4,r2,r3 + 1000ee4: 003fe006 br 1000e68 <_Z28read_encoded_value_with_basehjPKhPj+0x100> + 1000ee8: 30800043 ldbu r2,1(r6) + 1000eec: 30c00003 ldbu r3,0(r6) + 1000ef0: 31400084 addi r5,r6,2 + 1000ef4: 1004923a slli r2,r2,8 + 1000ef8: 10c4b03a or r2,r2,r3 + 1000efc: 113fffcc andi r4,r2,65535 + 1000f00: 2120001c xori r4,r4,32768 + 1000f04: 21200004 addi r4,r4,-32768 + 1000f08: 003fd706 br 1000e68 <_Z28read_encoded_value_with_basehjPKhPj+0x100> + 1000f0c: 3009883a mov r4,r6 + 1000f10: d80b883a mov r5,sp + 1000f14: 1000c780 call 1000c78 <_Z12read_sleb128PKhPi> + 1000f18: d9000017 ldw r4,0(sp) + 1000f1c: 100b883a mov r5,r2 + 1000f20: 003fd106 br 1000e68 <_Z28read_encoded_value_with_basehjPKhPj+0x100> + 1000f24: 3009883a mov r4,r6 + 1000f28: d80b883a mov r5,sp + 1000f2c: 1000c480 call 1000c48 <_Z12read_uleb128PKhPj> + 1000f30: d9000017 ldw r4,0(sp) + 1000f34: 100b883a mov r5,r2 + 1000f38: 003fcb06 br 1000e68 <_Z28read_encoded_value_with_basehjPKhPj+0x100> + +01000f3c <_Z21base_of_encoded_valuehP15_Unwind_Context>: + 1000f3c: deffff04 addi sp,sp,-4 + 1000f40: 21003fcc andi r4,r4,255 + 1000f44: 00803fc4 movi r2,255 + 1000f48: dfc00015 stw ra,0(sp) + 1000f4c: 20800c26 beq r4,r2,1000f80 <_Z21base_of_encoded_valuehP15_Unwind_Context+0x44> + 1000f50: 21001c0c andi r4,r4,112 + 1000f54: 00800804 movi r2,32 + 1000f58: 20800d26 beq r4,r2,1000f90 <_Z21base_of_encoded_valuehP15_Unwind_Context+0x54> + 1000f5c: 1100070e bge r2,r4,1000f7c <_Z21base_of_encoded_valuehP15_Unwind_Context+0x40> + 1000f60: 00801004 movi r2,64 + 1000f64: 20801126 beq r4,r2,1000fac <_Z21base_of_encoded_valuehP15_Unwind_Context+0x70> + 1000f68: 00801404 movi r2,80 + 1000f6c: 20800426 beq r4,r2,1000f80 <_Z21base_of_encoded_valuehP15_Unwind_Context+0x44> + 1000f70: 00800c04 movi r2,48 + 1000f74: 20801126 beq r4,r2,1000fbc <_Z21base_of_encoded_valuehP15_Unwind_Context+0x80> + 1000f78: 100279c0 call 100279c + 1000f7c: 2000081e bne r4,zero,1000fa0 <_Z21base_of_encoded_valuehP15_Unwind_Context+0x64> + 1000f80: 0005883a mov r2,zero + 1000f84: dfc00017 ldw ra,0(sp) + 1000f88: dec00104 addi sp,sp,4 + 1000f8c: f800283a ret + 1000f90: 2809883a mov r4,r5 + 1000f94: dfc00017 ldw ra,0(sp) + 1000f98: dec00104 addi sp,sp,4 + 1000f9c: 100230c1 jmpi 100230c <_Unwind_GetTextRelBase> + 1000fa0: 00800404 movi r2,16 + 1000fa4: 20bff626 beq r4,r2,1000f80 <_Z21base_of_encoded_valuehP15_Unwind_Context+0x44> + 1000fa8: 100279c0 call 100279c + 1000fac: 2809883a mov r4,r5 + 1000fb0: dfc00017 ldw ra,0(sp) + 1000fb4: dec00104 addi sp,sp,4 + 1000fb8: 10022f41 jmpi 10022f4 <_Unwind_GetRegionStart> + 1000fbc: 2809883a mov r4,r5 + 1000fc0: dfc00017 ldw ra,0(sp) + 1000fc4: dec00104 addi sp,sp,4 + 1000fc8: 10023041 jmpi 1002304 <_Unwind_GetDataRelBase> + +01000fcc <_Z17parse_lsda_headerP15_Unwind_ContextPKhP16lsda_header_info>: + 1000fcc: defffa04 addi sp,sp,-24 + 1000fd0: dc800415 stw r18,16(sp) + 1000fd4: dc400315 stw r17,12(sp) + 1000fd8: dc000215 stw r16,8(sp) + 1000fdc: dfc00515 stw ra,20(sp) + 1000fe0: 2021883a mov r16,r4 + 1000fe4: 000f883a mov r7,zero + 1000fe8: 3023883a mov r17,r6 + 1000fec: 2825883a mov r18,r5 + 1000ff0: 20000226 beq r4,zero,1000ffc <_Z17parse_lsda_headerP15_Unwind_ContextPKhP16lsda_header_info+0x30> + 1000ff4: 10022f40 call 10022f4 <_Unwind_GetRegionStart> + 1000ff8: 100f883a mov r7,r2 + 1000ffc: 89c00015 stw r7,0(r17) + 1001000: 90c00003 ldbu r3,0(r18) + 1001004: 800b883a mov r5,r16 + 1001008: 00803fc4 movi r2,255 + 100100c: 1c003fcc andi r16,r3,255 + 1001010: 91800044 addi r6,r18,1 + 1001014: 8009883a mov r4,r16 + 1001018: 18802226 beq r3,r2,10010a4 <_Z17parse_lsda_headerP15_Unwind_ContextPKhP16lsda_header_info+0xd8> + 100101c: d9800115 stw r6,4(sp) + 1001020: 1000f3c0 call 1000f3c <_Z21base_of_encoded_valuehP15_Unwind_Context> + 1001024: d9800117 ldw r6,4(sp) + 1001028: 8009883a mov r4,r16 + 100102c: 100b883a mov r5,r2 + 1001030: 89c00104 addi r7,r17,4 + 1001034: 1000d680 call 1000d68 <_Z28read_encoded_value_with_basehjPKhPj> + 1001038: 100d883a mov r6,r2 + 100103c: 30800003 ldbu r2,0(r6) + 1001040: 31c00044 addi r7,r6,1 + 1001044: 00c03fc4 movi r3,255 + 1001048: d80b883a mov r5,sp + 100104c: 3809883a mov r4,r7 + 1001050: 88800505 stb r2,20(r17) + 1001054: 10c01b26 beq r2,r3,10010c4 <_Z17parse_lsda_headerP15_Unwind_ContextPKhP16lsda_header_info+0xf8> + 1001058: 1000c480 call 1000c48 <_Z12read_uleb128PKhPj> + 100105c: 100f883a mov r7,r2 + 1001060: d8800017 ldw r2,0(sp) + 1001064: 3885883a add r2,r7,r2 + 1001068: 88800315 stw r2,12(r17) + 100106c: 38800003 ldbu r2,0(r7) + 1001070: 39000044 addi r4,r7,1 + 1001074: d80b883a mov r5,sp + 1001078: 88800545 stb r2,21(r17) + 100107c: 1000c480 call 1000c48 <_Z12read_uleb128PKhPj> + 1001080: d8c00017 ldw r3,0(sp) + 1001084: 10c9883a add r4,r2,r3 + 1001088: 89000415 stw r4,16(r17) + 100108c: dfc00517 ldw ra,20(sp) + 1001090: dc800417 ldw r18,16(sp) + 1001094: dc400317 ldw r17,12(sp) + 1001098: dc000217 ldw r16,8(sp) + 100109c: dec00604 addi sp,sp,24 + 10010a0: f800283a ret + 10010a4: 89c00115 stw r7,4(r17) + 10010a8: 30800003 ldbu r2,0(r6) + 10010ac: 31c00044 addi r7,r6,1 + 10010b0: 00c03fc4 movi r3,255 + 10010b4: d80b883a mov r5,sp + 10010b8: 3809883a mov r4,r7 + 10010bc: 88800505 stb r2,20(r17) + 10010c0: 10ffe51e bne r2,r3,1001058 <_Z17parse_lsda_headerP15_Unwind_ContextPKhP16lsda_header_info+0x8c> + 10010c4: 88000315 stw zero,12(r17) + 10010c8: 003fe806 br 100106c <_Z17parse_lsda_headerP15_Unwind_ContextPKhP16lsda_header_info+0xa0> + +010010cc <_Z15get_ttype_entryP16lsda_header_infoj>: + 10010cc: defffe04 addi sp,sp,-8 + 10010d0: dfc00115 stw ra,4(sp) + 10010d4: 21c00503 ldbu r7,20(r4) + 10010d8: 00803fc4 movi r2,255 + 10010dc: 38801a26 beq r7,r2,1001148 <_Z15get_ttype_entryP16lsda_header_infoj+0x7c> + 10010e0: 38c001cc andi r3,r7,7 + 10010e4: 00800084 movi r2,2 + 10010e8: 18801326 beq r3,r2,1001138 <_Z15get_ttype_entryP16lsda_header_infoj+0x6c> + 10010ec: 10c0050e bge r2,r3,1001104 <_Z15get_ttype_entryP16lsda_header_infoj+0x38> + 10010f0: 008000c4 movi r2,3 + 10010f4: 18800426 beq r3,r2,1001108 <_Z15get_ttype_entryP16lsda_header_infoj+0x3c> + 10010f8: 00800104 movi r2,4 + 10010fc: 18801026 beq r3,r2,1001140 <_Z15get_ttype_entryP16lsda_header_infoj+0x74> + 1001100: 100279c0 call 100279c + 1001104: 183ffe1e bne r3,zero,1001100 <_Z15get_ttype_entryP16lsda_header_infoj+0x34> + 1001108: 2945883a add r2,r5,r5 + 100110c: 1085883a add r2,r2,r2 + 1001110: 21800317 ldw r6,12(r4) + 1001114: 21400217 ldw r5,8(r4) + 1001118: 3809883a mov r4,r7 + 100111c: 308dc83a sub r6,r6,r2 + 1001120: d80f883a mov r7,sp + 1001124: 1000d680 call 1000d68 <_Z28read_encoded_value_with_basehjPKhPj> + 1001128: d8800017 ldw r2,0(sp) + 100112c: dfc00117 ldw ra,4(sp) + 1001130: dec00204 addi sp,sp,8 + 1001134: f800283a ret + 1001138: 2945883a add r2,r5,r5 + 100113c: 003ff406 br 1001110 <_Z15get_ttype_entryP16lsda_header_infoj+0x44> + 1001140: 280490fa slli r2,r5,3 + 1001144: 003ff206 br 1001110 <_Z15get_ttype_entryP16lsda_header_infoj+0x44> + 1001148: 0005883a mov r2,zero + 100114c: 003ff006 br 1001110 <_Z15get_ttype_entryP16lsda_header_infoj+0x44> + +01001150 <_Z20check_exception_specP16lsda_header_infoPKSt9type_infoPvi>: + 1001150: 20800317 ldw r2,12(r4) + 1001154: defffa04 addi sp,sp,-24 + 1001158: dc800415 stw r18,16(sp) + 100115c: 11c5c83a sub r2,r2,r7 + 1001160: dc400315 stw r17,12(sp) + 1001164: dc000215 stw r16,8(sp) + 1001168: dfc00515 stw ra,20(sp) + 100116c: 2023883a mov r17,r4 + 1001170: d9800115 stw r6,4(sp) + 1001174: 2825883a mov r18,r5 + 1001178: 143fffc4 addi r16,r2,-1 + 100117c: 8009883a mov r4,r16 + 1001180: d80b883a mov r5,sp + 1001184: 1000c480 call 1000c48 <_Z12read_uleb128PKhPj> + 1001188: 1021883a mov r16,r2 + 100118c: d8800017 ldw r2,0(sp) + 1001190: 8809883a mov r4,r17 + 1001194: 100b883a mov r5,r2 + 1001198: 10000826 beq r2,zero,10011bc <_Z20check_exception_specP16lsda_header_infoPKSt9type_infoPvi+0x6c> + 100119c: 10010cc0 call 10010cc <_Z15get_ttype_entryP16lsda_header_infoj> + 10011a0: 1009883a mov r4,r2 + 10011a4: 900b883a mov r5,r18 + 10011a8: d9800104 addi r6,sp,4 + 10011ac: 1000ccc0 call 1000ccc <_Z16get_adjusted_ptrPKSt9type_infoS1_PPv> + 10011b0: 10803fcc andi r2,r2,255 + 10011b4: 103ff126 beq r2,zero,100117c <_Z20check_exception_specP16lsda_header_infoPKSt9type_infoPvi+0x2c> + 10011b8: 00800044 movi r2,1 + 10011bc: dfc00517 ldw ra,20(sp) + 10011c0: dc800417 ldw r18,16(sp) + 10011c4: dc400317 ldw r17,12(sp) + 10011c8: dc000217 ldw r16,8(sp) + 10011cc: dec00604 addi sp,sp,24 + 10011d0: f800283a ret + +010011d4 <__cxa_call_unexpected>: + 10011d4: deffe204 addi sp,sp,-120 + 10011d8: 00804034 movhi r2,256 + 10011dc: 1084d504 addi r2,r2,4948 + 10011e0: 00c040b4 movhi r3,258 + 10011e4: 18e2da04 addi r3,r3,-29848 + 10011e8: d8800c15 stw r2,48(sp) + 10011ec: d9001815 stw r4,96(sp) + 10011f0: 00804034 movhi r2,256 + 10011f4: 10849704 addi r2,r2,4700 + 10011f8: d9000604 addi r4,sp,24 + 10011fc: d8c00d15 stw r3,52(sp) + 1001200: dfc01d15 stw ra,116(sp) + 1001204: d8800f15 stw r2,60(sp) + 1001208: df001c15 stw fp,112(sp) + 100120c: ddc01b15 stw r23,108(sp) + 1001210: dec00e15 stw sp,56(sp) + 1001214: dec01015 stw sp,64(sp) + 1001218: 10022540 call 1002254 <_Unwind_SjLj_Register> + 100121c: d9001817 ldw r4,96(sp) + 1001220: 1001a0c0 call 1001a0c <__cxa_begin_catch> + 1001224: d8801817 ldw r2,96(sp) + 1001228: 10fff504 addi r3,r2,-44 + 100122c: 18800917 ldw r2,36(r3) + 1001230: 19400617 ldw r5,24(r3) + 1001234: 19000217 ldw r4,8(r3) + 1001238: d8800215 stw r2,8(sp) + 100123c: 18800817 ldw r2,32(r3) + 1001240: 18c00317 ldw r3,12(r3) + 1001244: d9401615 stw r5,88(sp) + 1001248: d8801715 stw r2,92(sp) + 100124c: 00800084 movi r2,2 + 1001250: d8c01515 stw r3,84(sp) + 1001254: d8800715 stw r2,28(sp) + 1001258: 10019180 call 1001918 <_ZN10__cxxabiv112__unexpectedEPFvvE> + 100125c: d8800717 ldw r2,28(sp) + 1001260: d8c00817 ldw r3,32(sp) + 1001264: d8801a15 stw r2,104(sp) + 1001268: d9401a17 ldw r5,104(sp) + 100126c: 00800044 movi r2,1 + 1001270: d8c01915 stw r3,100(sp) + 1001274: 28800826 beq r5,r2,1001298 <__cxa_call_unexpected+0xc4> + 1001278: d8000715 stw zero,28(sp) + 100127c: 10019680 call 1001968 <__cxa_end_catch> + 1001280: d8000715 stw zero,28(sp) + 1001284: 10019680 call 1001968 <__cxa_end_catch> + 1001288: d9001917 ldw r4,100(sp) + 100128c: 00bfffc4 movi r2,-1 + 1001290: d8800715 stw r2,28(sp) + 1001294: 10025200 call 1002520 <_Unwind_SjLj_Resume> + 1001298: d9001917 ldw r4,100(sp) + 100129c: 1001a0c0 call 1001a0c <__cxa_begin_catch> + 10012a0: 10022440 call 1002244 <__cxa_get_globals_fast> + 10012a4: 10800017 ldw r2,0(r2) + 10012a8: d8c01a17 ldw r3,104(sp) + 10012ac: 0009883a mov r4,zero + 10012b0: 11401004 addi r5,r2,64 + 10012b4: d9401315 stw r5,76(sp) + 10012b8: d8801415 stw r2,80(sp) + 10012bc: d8c00715 stw r3,28(sp) + 10012c0: d9401717 ldw r5,92(sp) + 10012c4: d80d883a mov r6,sp + 10012c8: 1000fcc0 call 1000fcc <_Z17parse_lsda_headerP15_Unwind_ContextPKhP16lsda_header_info> + 10012cc: d8801417 ldw r2,80(sp) + 10012d0: d809883a mov r4,sp + 10012d4: d9801317 ldw r6,76(sp) + 10012d8: 11400017 ldw r5,0(r2) + 10012dc: d9c01617 ldw r7,88(sp) + 10012e0: 10011500 call 1001150 <_Z20check_exception_specP16lsda_header_infoPKSt9type_infoPvi> + 10012e4: 10803fcc andi r2,r2,255 + 10012e8: 1000151e bne r2,zero,1001340 <__cxa_call_unexpected+0x16c> + 10012ec: d8c01a17 ldw r3,104(sp) + 10012f0: d809883a mov r4,sp + 10012f4: 014040b4 movhi r5,258 + 10012f8: 29635704 addi r5,r5,-29348 + 10012fc: d8c00715 stw r3,28(sp) + 1001300: 000d883a mov r6,zero + 1001304: d9c01617 ldw r7,88(sp) + 1001308: 10011500 call 1001150 <_Z20check_exception_specP16lsda_header_infoPKSt9type_infoPvi> + 100130c: 10803fcc andi r2,r2,255 + 1001310: 10000c26 beq r2,zero,1001344 <__cxa_call_unexpected+0x170> + 1001314: 01000104 movi r4,4 + 1001318: 1001ed80 call 1001ed8 <__cxa_allocate_exception> + 100131c: 1009883a mov r4,r2 + 1001320: 008040b4 movhi r2,258 + 1001324: 10a34a04 addi r2,r2,-29400 + 1001328: 20800015 stw r2,0(r4) + 100132c: 014040b4 movhi r5,258 + 1001330: 29635704 addi r5,r5,-29348 + 1001334: 01804034 movhi r6,256 + 1001338: 31886004 addi r6,r6,8576 + 100133c: 1001ba40 call 1001ba4 <__cxa_throw> + 1001340: 1001b300 call 1001b30 <__cxa_rethrow> + 1001344: d9401a17 ldw r5,104(sp) + 1001348: d9001517 ldw r4,84(sp) + 100134c: d9400715 stw r5,28(sp) + 1001350: 100185c0 call 100185c <_ZN10__cxxabiv111__terminateEPFvvE> + +01001354 <__gxx_personality_sj0>: + 1001354: deffd304 addi sp,sp,-180 + 1001358: 00804034 movhi r2,256 + 100135c: 1085fc04 addi r2,r2,6128 + 1001360: 00c040b4 movhi r3,258 + 1001364: 18e2de04 addi r3,r3,-29832 + 1001368: d8801315 stw r2,76(sp) + 100136c: d9002315 stw r4,140(sp) + 1001370: 00804034 movhi r2,256 + 1001374: 1084d504 addi r2,r2,4948 + 1001378: d9000a04 addi r4,sp,40 + 100137c: d8801015 stw r2,64(sp) + 1001380: d8c01115 stw r3,68(sp) + 1001384: dfc02c15 stw ra,176(sp) + 1001388: df002b15 stw fp,172(sp) + 100138c: ddc02a15 stw r23,168(sp) + 1001390: dec01215 stw sp,72(sp) + 1001394: dec01415 stw sp,80(sp) + 1001398: d9802515 stw r6,148(sp) + 100139c: d9402415 stw r5,144(sp) + 10013a0: d9c02615 stw r7,152(sp) + 10013a4: 10022540 call 1002254 <_Unwind_SjLj_Register> + 10013a8: d8c02317 ldw r3,140(sp) + 10013ac: 00800044 movi r2,1 + 10013b0: 18800a26 beq r3,r2,10013dc <__gxx_personality_sj0+0x88> + 10013b4: 010000c4 movi r4,3 + 10013b8: d9002215 stw r4,136(sp) + 10013bc: d9000a04 addi r4,sp,40 + 10013c0: 10022640 call 1002264 <_Unwind_SjLj_Unregister> + 10013c4: d8802217 ldw r2,136(sp) + 10013c8: dfc02c17 ldw ra,176(sp) + 10013cc: df002b17 ldw fp,172(sp) + 10013d0: ddc02a17 ldw r23,168(sp) + 10013d4: dec02d04 addi sp,sp,180 + 10013d8: f800283a ret + 10013dc: d9402d17 ldw r5,180(sp) + 10013e0: d9002517 ldw r4,148(sp) + 10013e4: 0007883a mov r3,zero + 10013e8: 28800504 addi r2,r5,20 + 10013ec: d8800015 stw r2,0(sp) + 10013f0: 28bff504 addi r2,r5,-44 + 10013f4: d8801a15 stw r2,104(sp) + 10013f8: 0090caf4 movhi r2,17195 + 10013fc: 108ac004 addi r2,r2,11008 + 1001400: 2080ad26 beq r4,r2,10016b8 <__gxx_personality_sj0+0x364> + 1001404: d8c02105 stb r3,132(sp) + 1001408: d8c02417 ldw r3,144(sp) + 100140c: 00800184 movi r2,6 + 1001410: 1880281e bne r3,r2,10014b4 <__gxx_personality_sj0+0x160> + 1001414: d8802103 ldbu r2,132(sp) + 1001418: 10002626 beq r2,zero,10014b4 <__gxx_personality_sj0+0x160> + 100141c: d9001a17 ldw r4,104(sp) + 1001420: d9401a17 ldw r5,104(sp) + 1001424: d8801a17 ldw r2,104(sp) + 1001428: 21000917 ldw r4,36(r4) + 100142c: 29400617 ldw r5,24(r5) + 1001430: 10800817 ldw r2,32(r2) + 1001434: d9001d15 stw r4,116(sp) + 1001438: d9401b15 stw r5,108(sp) + 100143c: d8802015 stw r2,128(sp) + 1001440: 2000ad1e bne r4,zero,10016f8 <__gxx_personality_sj0+0x3a4> + 1001444: 01000044 movi r4,1 + 1001448: 00800044 movi r2,1 + 100144c: 2080e126 beq r4,r2,10017d4 <__gxx_personality_sj0+0x480> + 1001450: d8801b17 ldw r2,108(sp) + 1001454: 1000d316 blt r2,zero,10017a4 <__gxx_personality_sj0+0x450> + 1001458: d9802d17 ldw r6,180(sp) + 100145c: d9002e17 ldw r4,184(sp) + 1001460: 00bfffc4 movi r2,-1 + 1001464: 000b883a mov r5,zero + 1001468: d8800b15 stw r2,44(sp) + 100146c: 100229c0 call 100229c <_Unwind_SetGR> + 1001470: d9801b17 ldw r6,108(sp) + 1001474: d9002e17 ldw r4,184(sp) + 1001478: 01400044 movi r5,1 + 100147c: 100229c0 call 100229c <_Unwind_SetGR> + 1001480: d9002e17 ldw r4,184(sp) + 1001484: d9401d17 ldw r5,116(sp) + 1001488: 10022d80 call 10022d8 <_Unwind_SetIP> + 100148c: 010001c4 movi r4,7 + 1001490: d9002215 stw r4,136(sp) + 1001494: d9000a04 addi r4,sp,40 + 1001498: 10022640 call 1002264 <_Unwind_SjLj_Unregister> + 100149c: d8802217 ldw r2,136(sp) + 10014a0: dfc02c17 ldw ra,176(sp) + 10014a4: df002b17 ldw fp,172(sp) + 10014a8: ddc02a17 ldw r23,168(sp) + 10014ac: dec02d04 addi sp,sp,180 + 10014b0: f800283a ret + 10014b4: d9002e17 ldw r4,184(sp) + 10014b8: 00ffffc4 movi r3,-1 + 10014bc: d8c00b15 stw r3,44(sp) + 10014c0: 10022e80 call 10022e8 <_Unwind_GetLanguageSpecificData> + 10014c4: 10007226 beq r2,zero,1001690 <__gxx_personality_sj0+0x33c> + 10014c8: d9002e17 ldw r4,184(sp) + 10014cc: d9800404 addi r6,sp,16 + 10014d0: 100b883a mov r5,r2 + 10014d4: d8802015 stw r2,128(sp) + 10014d8: 1000fcc0 call 1000fcc <_Z17parse_lsda_headerP15_Unwind_ContextPKhP16lsda_header_info> + 10014dc: d9000903 ldbu r4,36(sp) + 10014e0: d9402e17 ldw r5,184(sp) + 10014e4: d8801e15 stw r2,120(sp) + 10014e8: 1000f3c0 call 1000f3c <_Z21base_of_encoded_valuehP15_Unwind_Context> + 10014ec: d9002e17 ldw r4,184(sp) + 10014f0: d8800615 stw r2,24(sp) + 10014f4: 10022b40 call 10022b4 <_Unwind_GetIP> + 10014f8: 10bfffc4 addi r2,r2,-1 + 10014fc: d8801c15 stw r2,112(sp) + 1001500: 10006316 blt r2,zero,1001690 <__gxx_personality_sj0+0x33c> + 1001504: 10001b1e bne r2,zero,1001574 <__gxx_personality_sj0+0x220> + 1001508: 01000044 movi r4,1 + 100150c: d8001f15 stw zero,124(sp) + 1001510: d8001d15 stw zero,116(sp) + 1001514: d8001b15 stw zero,108(sp) + 1001518: d9402417 ldw r5,144(sp) + 100151c: 00c00044 movi r3,1 + 1001520: 28c4703a and r2,r5,r3 + 1001524: 1005003a cmpeq r2,r2,zero + 1001528: 10006a1e bne r2,zero,10016d4 <__gxx_personality_sj0+0x380> + 100152c: 00800084 movi r2,2 + 1001530: 20805726 beq r4,r2,1001690 <__gxx_personality_sj0+0x33c> + 1001534: d8802103 ldbu r2,132(sp) + 1001538: 10008626 beq r2,zero,1001754 <__gxx_personality_sj0+0x400> + 100153c: d9001a17 ldw r4,104(sp) + 1001540: d9401d17 ldw r5,116(sp) + 1001544: d8801b17 ldw r2,108(sp) + 1001548: 00c00184 movi r3,6 + 100154c: d8c02215 stw r3,136(sp) + 1001550: 21400915 stw r5,36(r4) + 1001554: 20800615 stw r2,24(r4) + 1001558: d8c01f17 ldw r3,124(sp) + 100155c: d9402017 ldw r5,128(sp) + 1001560: d8800017 ldw r2,0(sp) + 1001564: 20c00715 stw r3,28(r4) + 1001568: 21400815 stw r5,32(r4) + 100156c: 20800a15 stw r2,40(r4) + 1001570: 003f9206 br 10013bc <__gxx_personality_sj0+0x68> + 1001574: d9001e17 ldw r4,120(sp) + 1001578: d9400204 addi r5,sp,8 + 100157c: 1000c480 call 1000c48 <_Z12read_uleb128PKhPj> + 1001580: d9401c17 ldw r5,112(sp) + 1001584: 1009883a mov r4,r2 + 1001588: 297fffc4 addi r5,r5,-1 + 100158c: d9401c15 stw r5,112(sp) + 1001590: d9400104 addi r5,sp,4 + 1001594: 1000c480 call 1000c48 <_Z12read_uleb128PKhPj> + 1001598: d8801e15 stw r2,120(sp) + 100159c: d8801c17 ldw r2,112(sp) + 10015a0: 103ff41e bne r2,zero,1001574 <__gxx_personality_sj0+0x220> + 10015a4: d8800217 ldw r2,8(sp) + 10015a8: d8c00117 ldw r3,4(sp) + 10015ac: 01000044 movi r4,1 + 10015b0: 1105883a add r2,r2,r4 + 10015b4: d8801d15 stw r2,116(sp) + 10015b8: 1800541e bne r3,zero,100170c <__gxx_personality_sj0+0x3b8> + 10015bc: d8001f15 stw zero,124(sp) + 10015c0: d8c01d17 ldw r3,116(sp) + 10015c4: 18003226 beq r3,zero,1001690 <__gxx_personality_sj0+0x33c> + 10015c8: d9001f17 ldw r4,124(sp) + 10015cc: 20007226 beq r4,zero,1001798 <__gxx_personality_sj0+0x444> + 10015d0: d9402417 ldw r5,144(sp) + 10015d4: 2880020c andi r2,r5,8 + 10015d8: 10006a1e bne r2,zero,1001784 <__gxx_personality_sj0+0x430> + 10015dc: d8802103 ldbu r2,132(sp) + 10015e0: 10006826 beq r2,zero,1001784 <__gxx_personality_sj0+0x430> + 10015e4: d8801a17 ldw r2,104(sp) + 10015e8: 10800017 ldw r2,0(r2) + 10015ec: d8801915 stw r2,100(sp) + 10015f0: d8c01917 ldw r3,100(sp) + 10015f4: d8001805 stb zero,96(sp) + 10015f8: 1807003a cmpeq r3,r3,zero + 10015fc: d8c02715 stw r3,156(sp) + 1001600: 00000706 br 1001620 <__gxx_personality_sj0+0x2cc> + 1001604: 01000044 movi r4,1 + 1001608: d9001805 stb r4,96(sp) + 100160c: d8800217 ldw r2,8(sp) + 1001610: 10005e26 beq r2,zero,100178c <__gxx_personality_sj0+0x438> + 1001614: d8c01717 ldw r3,92(sp) + 1001618: 1885883a add r2,r3,r2 + 100161c: d8801f15 stw r2,124(sp) + 1001620: d9001f17 ldw r4,124(sp) + 1001624: d9400104 addi r5,sp,4 + 1001628: 1000c780 call 1000c78 <_Z12read_sleb128PKhPi> + 100162c: 1009883a mov r4,r2 + 1001630: d9400204 addi r5,sp,8 + 1001634: d8801715 stw r2,92(sp) + 1001638: 1000c780 call 1000c78 <_Z12read_sleb128PKhPi> + 100163c: d8800117 ldw r2,4(sp) + 1001640: 103ff026 beq r2,zero,1001604 <__gxx_personality_sj0+0x2b0> + 1001644: 0080360e bge zero,r2,1001720 <__gxx_personality_sj0+0x3cc> + 1001648: 017fffc4 movi r5,-1 + 100164c: d9400b15 stw r5,44(sp) + 1001650: d9000404 addi r4,sp,16 + 1001654: 100b883a mov r5,r2 + 1001658: 10010cc0 call 10010cc <_Z15get_ttype_entryP16lsda_header_infoj> + 100165c: 10000826 beq r2,zero,1001680 <__gxx_personality_sj0+0x32c> + 1001660: d8c02717 ldw r3,156(sp) + 1001664: 183fe91e bne r3,zero,100160c <__gxx_personality_sj0+0x2b8> + 1001668: d9401917 ldw r5,100(sp) + 100166c: 1009883a mov r4,r2 + 1001670: d80d883a mov r6,sp + 1001674: 1000ccc0 call 1000ccc <_Z16get_adjusted_ptrPKSt9type_infoS1_PPv> + 1001678: 10803fcc andi r2,r2,255 + 100167c: 103fe326 beq r2,zero,100160c <__gxx_personality_sj0+0x2b8> + 1001680: d9000117 ldw r4,4(sp) + 1001684: d9001b15 stw r4,108(sp) + 1001688: 010000c4 movi r4,3 + 100168c: 003fa206 br 1001518 <__gxx_personality_sj0+0x1c4> + 1001690: 01400204 movi r5,8 + 1001694: d9000a04 addi r4,sp,40 + 1001698: d9402215 stw r5,136(sp) + 100169c: 10022640 call 1002264 <_Unwind_SjLj_Unregister> + 10016a0: d8802217 ldw r2,136(sp) + 10016a4: dfc02c17 ldw ra,176(sp) + 10016a8: df002b17 ldw fp,172(sp) + 10016ac: ddc02a17 ldw r23,168(sp) + 10016b0: dec02d04 addi sp,sp,180 + 10016b4: f800283a ret + 10016b8: d9402617 ldw r5,152(sp) + 10016bc: 0091d3b4 movhi r2,18254 + 10016c0: 109550c4 addi r2,r2,21827 + 10016c4: 28bf4f1e bne r5,r2,1001404 <__gxx_personality_sj0+0xb0> + 10016c8: d8802317 ldw r2,140(sp) + 10016cc: 1007883a mov r3,r2 + 10016d0: 003f4c06 br 1001404 <__gxx_personality_sj0+0xb0> + 10016d4: d9402417 ldw r5,144(sp) + 10016d8: 2880020c andi r2,r5,8 + 10016dc: 10000826 beq r2,zero,1001700 <__gxx_personality_sj0+0x3ac> + 10016e0: 20c04026 beq r4,r3,10017e4 <__gxx_personality_sj0+0x490> + 10016e4: d8801b17 ldw r2,108(sp) + 10016e8: 103f5b0e bge r2,zero,1001458 <__gxx_personality_sj0+0x104> + 10016ec: 00800084 movi r2,2 + 10016f0: d8800b15 stw r2,44(sp) + 10016f4: 10019280 call 1001928 <_ZSt10unexpectedv> + 10016f8: 010000c4 movi r4,3 + 10016fc: 003f5206 br 1001448 <__gxx_personality_sj0+0xf4> + 1001700: d8802103 ldbu r2,132(sp) + 1001704: 103f501e bne r2,zero,1001448 <__gxx_personality_sj0+0xf4> + 1001708: 003ff506 br 10016e0 <__gxx_personality_sj0+0x38c> + 100170c: d8800817 ldw r2,32(sp) + 1001710: 1885883a add r2,r3,r2 + 1001714: 1105c83a sub r2,r2,r4 + 1001718: d8801f15 stw r2,124(sp) + 100171c: 003fa806 br 10015c0 <__gxx_personality_sj0+0x26c> + 1001720: d9002717 ldw r4,156(sp) + 1001724: 20000e1e bne r4,zero,1001760 <__gxx_personality_sj0+0x40c> + 1001728: 017fffc4 movi r5,-1 + 100172c: d9400b15 stw r5,44(sp) + 1001730: d9800017 ldw r6,0(sp) + 1001734: d9401917 ldw r5,100(sp) + 1001738: 100f883a mov r7,r2 + 100173c: d9000404 addi r4,sp,16 + 1001740: 10011500 call 1001150 <_Z20check_exception_specP16lsda_header_infoPKSt9type_infoPvi> + 1001744: 1080005c xori r2,r2,1 + 1001748: 10803fcc andi r2,r2,255 + 100174c: 103faf26 beq r2,zero,100160c <__gxx_personality_sj0+0x2b8> + 1001750: 003fcb06 br 1001680 <__gxx_personality_sj0+0x32c> + 1001754: 00800184 movi r2,6 + 1001758: d8802215 stw r2,136(sp) + 100175c: 003f1706 br 10013bc <__gxx_personality_sj0+0x68> + 1001760: d9000717 ldw r4,28(sp) + 1001764: d9400304 addi r5,sp,12 + 1001768: 2089c83a sub r4,r4,r2 + 100176c: 213fffc4 addi r4,r4,-1 + 1001770: 1000c480 call 1000c48 <_Z12read_uleb128PKhPj> + 1001774: d8c00317 ldw r3,12(sp) + 1001778: 1807003a cmpeq r3,r3,zero + 100177c: 1805883a mov r2,r3 + 1001780: 003ff106 br 1001748 <__gxx_personality_sj0+0x3f4> + 1001784: d8001915 stw zero,100(sp) + 1001788: 003f9906 br 10015f0 <__gxx_personality_sj0+0x29c> + 100178c: d8801803 ldbu r2,96(sp) + 1001790: 1004c03a cmpne r2,r2,zero + 1001794: 103fbe26 beq r2,zero,1001690 <__gxx_personality_sj0+0x33c> + 1001798: 01000084 movi r4,2 + 100179c: d8001b15 stw zero,108(sp) + 10017a0: 003f5d06 br 1001518 <__gxx_personality_sj0+0x1c4> + 10017a4: d9402017 ldw r5,128(sp) + 10017a8: d9002e17 ldw r4,184(sp) + 10017ac: 00bfffc4 movi r2,-1 + 10017b0: d9800404 addi r6,sp,16 + 10017b4: d8800b15 stw r2,44(sp) + 10017b8: 1000fcc0 call 1000fcc <_Z17parse_lsda_headerP15_Unwind_ContextPKhP16lsda_header_info> + 10017bc: d9000903 ldbu r4,36(sp) + 10017c0: d9402e17 ldw r5,184(sp) + 10017c4: 1000f3c0 call 1000f3c <_Z21base_of_encoded_valuehP15_Unwind_Context> + 10017c8: d8c01a17 ldw r3,104(sp) + 10017cc: 18800915 stw r2,36(r3) + 10017d0: 003f2106 br 1001458 <__gxx_personality_sj0+0x104> + 10017d4: d9002d17 ldw r4,180(sp) + 10017d8: 00bfffc4 movi r2,-1 + 10017dc: d8800b15 stw r2,44(sp) + 10017e0: 10021a00 call 10021a0 <__cxa_call_terminate> + 10017e4: 00bfffc4 movi r2,-1 + 10017e8: d8800b15 stw r2,44(sp) + 10017ec: 10019000 call 1001900 <_ZSt9terminatev> + 10017f0: d9000b17 ldw r4,44(sp) + 10017f4: d9400c17 ldw r5,48(sp) + 10017f8: 00800044 movi r2,1 + 10017fc: d9002915 stw r4,164(sp) + 1001800: d9402815 stw r5,160(sp) + 1001804: 20800626 beq r4,r2,1001820 <__gxx_personality_sj0+0x4cc> + 1001808: d8000b15 stw zero,44(sp) + 100180c: 10019680 call 1001968 <__cxa_end_catch> + 1001810: d9002817 ldw r4,160(sp) + 1001814: 00bfffc4 movi r2,-1 + 1001818: d8800b15 stw r2,44(sp) + 100181c: 10025200 call 1002520 <_Unwind_SjLj_Resume> + 1001820: d9002817 ldw r4,160(sp) + 1001824: 1001a0c0 call 1001a0c <__cxa_begin_catch> + 1001828: d8c02917 ldw r3,164(sp) + 100182c: d8c00b15 stw r3,44(sp) + 1001830: 10019000 call 1001900 <_ZSt9terminatev> + +01001834 <_ZSt13set_terminatePFvvE>: + 1001834: 00c040b4 movhi r3,258 + 1001838: 18eb8f04 addi r3,r3,-20932 + 100183c: 18800017 ldw r2,0(r3) + 1001840: 19000015 stw r4,0(r3) + 1001844: f800283a ret + +01001848 <_ZSt14set_unexpectedPFvvE>: + 1001848: 00c040b4 movhi r3,258 + 100184c: 18eb9504 addi r3,r3,-20908 + 1001850: 18800017 ldw r2,0(r3) + 1001854: 19000015 stw r4,0(r3) + 1001858: f800283a ret + +0100185c <_ZN10__cxxabiv111__terminateEPFvvE>: + 100185c: deffed04 addi sp,sp,-76 + 1001860: 00804034 movhi r2,256 + 1001864: 1084d504 addi r2,r2,4948 + 1001868: d8800615 stw r2,24(sp) + 100186c: 00c040b4 movhi r3,258 + 1001870: 18e2e204 addi r3,r3,-29816 + 1001874: 00804034 movhi r2,256 + 1001878: 10862e04 addi r2,r2,6328 + 100187c: d9000d15 stw r4,52(sp) + 1001880: d809883a mov r4,sp + 1001884: d8800915 stw r2,36(sp) + 1001888: dfc01215 stw ra,72(sp) + 100188c: df001115 stw fp,68(sp) + 1001890: ddc01015 stw r23,64(sp) + 1001894: d8c00715 stw r3,28(sp) + 1001898: dec00815 stw sp,32(sp) + 100189c: dec00a15 stw sp,40(sp) + 10018a0: 10022540 call 1002254 <_Unwind_SjLj_Register> + 10018a4: 00800084 movi r2,2 + 10018a8: d8800115 stw r2,4(sp) + 10018ac: d8800d17 ldw r2,52(sp) + 10018b0: 103ee83a callr r2 + 10018b4: 100279c0 call 100279c + 10018b8: d8800117 ldw r2,4(sp) + 10018bc: d8c00217 ldw r3,8(sp) + 10018c0: d8800f15 stw r2,60(sp) + 10018c4: d8c00e15 stw r3,56(sp) + 10018c8: d8c00f17 ldw r3,60(sp) + 10018cc: 00800044 movi r2,1 + 10018d0: 18800626 beq r3,r2,10018ec <_ZN10__cxxabiv111__terminateEPFvvE+0x90> + 10018d4: d8000115 stw zero,4(sp) + 10018d8: 10019680 call 1001968 <__cxa_end_catch> + 10018dc: d9000e17 ldw r4,56(sp) + 10018e0: 00bfffc4 movi r2,-1 + 10018e4: d8800115 stw r2,4(sp) + 10018e8: 10025200 call 1002520 <_Unwind_SjLj_Resume> + 10018ec: d9000e17 ldw r4,56(sp) + 10018f0: 1001a0c0 call 1001a0c <__cxa_begin_catch> + 10018f4: d8c00f17 ldw r3,60(sp) + 10018f8: d8c00115 stw r3,4(sp) + 10018fc: 100279c0 call 100279c + +01001900 <_ZSt9terminatev>: + 1001900: 008040b4 movhi r2,258 + 1001904: 10ab8f04 addi r2,r2,-20932 + 1001908: 11000017 ldw r4,0(r2) + 100190c: deffff04 addi sp,sp,-4 + 1001910: dfc00015 stw ra,0(sp) + 1001914: 100185c0 call 100185c <_ZN10__cxxabiv111__terminateEPFvvE> + +01001918 <_ZN10__cxxabiv112__unexpectedEPFvvE>: + 1001918: deffff04 addi sp,sp,-4 + 100191c: dfc00015 stw ra,0(sp) + 1001920: 203ee83a callr r4 + 1001924: 10019000 call 1001900 <_ZSt9terminatev> + +01001928 <_ZSt10unexpectedv>: + 1001928: 008040b4 movhi r2,258 + 100192c: 10ab9504 addi r2,r2,-20908 + 1001930: 11000017 ldw r4,0(r2) + 1001934: deffff04 addi sp,sp,-4 + 1001938: dfc00015 stw ra,0(sp) + 100193c: 10019180 call 1001918 <_ZN10__cxxabiv112__unexpectedEPFvvE> + +01001940 <__cxa_get_exception_ptr>: + 1001940: 20bfff17 ldw r2,-4(r4) + 1001944: f800283a ret + +01001948 <_ZSt18uncaught_exceptionv>: + 1001948: deffff04 addi sp,sp,-4 + 100194c: dfc00015 stw ra,0(sp) + 1001950: 100224c0 call 100224c <__cxa_get_globals> + 1001954: 10800117 ldw r2,4(r2) + 1001958: 1004c03a cmpne r2,r2,zero + 100195c: dfc00017 ldw ra,0(sp) + 1001960: dec00104 addi sp,sp,4 + 1001964: f800283a ret + +01001968 <__cxa_end_catch>: + 1001968: deffff04 addi sp,sp,-4 + 100196c: dfc00015 stw ra,0(sp) + 1001970: 10022440 call 1002244 <__cxa_get_globals_fast> + 1001974: 11000017 ldw r4,0(r2) + 1001978: 1007883a mov r3,r2 + 100197c: 20001326 beq r4,zero,10019cc <__cxa_end_catch+0x64> + 1001980: 21400b17 ldw r5,44(r4) + 1001984: 0090caf4 movhi r2,17195 + 1001988: 108ac004 addi r2,r2,11008 + 100198c: 21800c17 ldw r6,48(r4) + 1001990: 28800526 beq r5,r2,10019a8 <__cxa_end_catch+0x40> + 1001994: 21000b04 addi r4,r4,44 + 1001998: 18000015 stw zero,0(r3) + 100199c: dfc00017 ldw ra,0(sp) + 10019a0: dec00104 addi sp,sp,4 + 10019a4: 10024141 jmpi 1002414 <_Unwind_DeleteException> + 10019a8: 0091d3b4 movhi r2,18254 + 10019ac: 109550c4 addi r2,r2,21827 + 10019b0: 30bff81e bne r6,r2,1001994 <__cxa_end_catch+0x2c> + 10019b4: 20800517 ldw r2,20(r4) + 10019b8: 10000e16 blt r2,zero,10019f4 <__cxa_end_catch+0x8c> + 10019bc: 117fffc4 addi r5,r2,-1 + 10019c0: 28000526 beq r5,zero,10019d8 <__cxa_end_catch+0x70> + 10019c4: 28000a16 blt r5,zero,10019f0 <__cxa_end_catch+0x88> + 10019c8: 21400515 stw r5,20(r4) + 10019cc: dfc00017 ldw ra,0(sp) + 10019d0: dec00104 addi sp,sp,4 + 10019d4: f800283a ret + 10019d8: 20800417 ldw r2,16(r4) + 10019dc: 21000b04 addi r4,r4,44 + 10019e0: 18800015 stw r2,0(r3) + 10019e4: dfc00017 ldw ra,0(sp) + 10019e8: dec00104 addi sp,sp,4 + 10019ec: 10024141 jmpi 1002414 <_Unwind_DeleteException> + 10019f0: 10019000 call 1001900 <_ZSt9terminatev> + 10019f4: 11400044 addi r5,r2,1 + 10019f8: 283ff31e bne r5,zero,10019c8 <__cxa_end_catch+0x60> + 10019fc: 20800417 ldw r2,16(r4) + 1001a00: 21400515 stw r5,20(r4) + 1001a04: 18800015 stw r2,0(r3) + 1001a08: 003ff006 br 10019cc <__cxa_end_catch+0x64> + +01001a0c <__cxa_begin_catch>: + 1001a0c: deffee04 addi sp,sp,-72 + 1001a10: 00804034 movhi r2,256 + 1001a14: 1084d504 addi r2,r2,4948 + 1001a18: 00c040b4 movhi r3,258 + 1001a1c: 18e2e604 addi r3,r3,-29800 + 1001a20: d8800615 stw r2,24(sp) + 1001a24: d9000e15 stw r4,56(sp) + 1001a28: 00804034 movhi r2,256 + 1001a2c: 1086c004 addi r2,r2,6912 + 1001a30: d809883a mov r4,sp + 1001a34: d8c00715 stw r3,28(sp) + 1001a38: dfc01115 stw ra,68(sp) + 1001a3c: d8800915 stw r2,36(sp) + 1001a40: df001015 stw fp,64(sp) + 1001a44: ddc00f15 stw r23,60(sp) + 1001a48: dec00815 stw sp,32(sp) + 1001a4c: dec00a15 stw sp,40(sp) + 1001a50: 10022540 call 1002254 <_Unwind_SjLj_Register> + 1001a54: 100224c0 call 100224c <__cxa_get_globals> + 1001a58: 100d883a mov r6,r2 + 1001a5c: d8800e17 ldw r2,56(sp) + 1001a60: 31c00017 ldw r7,0(r6) + 1001a64: 117ff504 addi r5,r2,-44 + 1001a68: 28c00b17 ldw r3,44(r5) + 1001a6c: 0090caf4 movhi r2,17195 + 1001a70: 108ac004 addi r2,r2,11008 + 1001a74: 29000c17 ldw r4,48(r5) + 1001a78: 18800b26 beq r3,r2,1001aa8 <__cxa_begin_catch+0x9c> + 1001a7c: 38001d1e bne r7,zero,1001af4 <__cxa_begin_catch+0xe8> + 1001a80: d8000d15 stw zero,52(sp) + 1001a84: 31400015 stw r5,0(r6) + 1001a88: d809883a mov r4,sp + 1001a8c: 10022640 call 1002264 <_Unwind_SjLj_Unregister> + 1001a90: d8800d17 ldw r2,52(sp) + 1001a94: dfc01117 ldw ra,68(sp) + 1001a98: df001017 ldw fp,64(sp) + 1001a9c: ddc00f17 ldw r23,60(sp) + 1001aa0: dec01204 addi sp,sp,72 + 1001aa4: f800283a ret + 1001aa8: 0091d3b4 movhi r2,18254 + 1001aac: 109550c4 addi r2,r2,21827 + 1001ab0: 20bff21e bne r4,r2,1001a7c <__cxa_begin_catch+0x70> + 1001ab4: 28c00517 ldw r3,20(r5) + 1001ab8: 18000b16 blt r3,zero,1001ae8 <__cxa_begin_catch+0xdc> + 1001abc: 18800044 addi r2,r3,1 + 1001ac0: 28800515 stw r2,20(r5) + 1001ac4: 30800117 ldw r2,4(r6) + 1001ac8: 10bfffc4 addi r2,r2,-1 + 1001acc: 30800115 stw r2,4(r6) + 1001ad0: 39400226 beq r7,r5,1001adc <__cxa_begin_catch+0xd0> + 1001ad4: 29c00415 stw r7,16(r5) + 1001ad8: 31400015 stw r5,0(r6) + 1001adc: 29400a17 ldw r5,40(r5) + 1001ae0: d9400d15 stw r5,52(sp) + 1001ae4: 003fe806 br 1001a88 <__cxa_begin_catch+0x7c> + 1001ae8: 00800044 movi r2,1 + 1001aec: 10c5c83a sub r2,r2,r3 + 1001af0: 003ff306 br 1001ac0 <__cxa_begin_catch+0xb4> + 1001af4: 00800044 movi r2,1 + 1001af8: d8800115 stw r2,4(sp) + 1001afc: 10019000 call 1001900 <_ZSt9terminatev> + 1001b00: d8800317 ldw r2,12(sp) + 1001b04: 00ffffc4 movi r3,-1 + 1001b08: d9000217 ldw r4,8(sp) + 1001b0c: 10c00226 beq r2,r3,1001b18 <__cxa_begin_catch+0x10c> + 1001b10: d8c00115 stw r3,4(sp) + 1001b14: 10025200 call 1002520 <_Unwind_SjLj_Resume> + 1001b18: 00bfffc4 movi r2,-1 + 1001b1c: d8800115 stw r2,4(sp) + 1001b20: 10011d40 call 10011d4 <__cxa_call_unexpected> + +01001b24 <_ZdlPv>: + 1001b24: 20000126 beq r4,zero,1001b2c <_ZdlPv+0x8> + 1001b28: 10027b41 jmpi 10027b4 + 1001b2c: f800283a ret + +01001b30 <__cxa_rethrow>: + 1001b30: defffe04 addi sp,sp,-8 + 1001b34: dc400015 stw r17,0(sp) + 1001b38: dfc00115 stw ra,4(sp) + 1001b3c: 100224c0 call 100224c <__cxa_get_globals> + 1001b40: 100b883a mov r5,r2 + 1001b44: 10800117 ldw r2,4(r2) + 1001b48: 2c400017 ldw r17,0(r5) + 1001b4c: 10800044 addi r2,r2,1 + 1001b50: 28800115 stw r2,4(r5) + 1001b54: 88000b26 beq r17,zero,1001b84 <__cxa_rethrow+0x54> + 1001b58: 88c00b17 ldw r3,44(r17) + 1001b5c: 0090caf4 movhi r2,17195 + 1001b60: 108ac004 addi r2,r2,11008 + 1001b64: 89000c17 ldw r4,48(r17) + 1001b68: 18800726 beq r3,r2,1001b88 <__cxa_rethrow+0x58> + 1001b6c: 28000015 stw zero,0(r5) + 1001b70: 8c400b04 addi r17,r17,44 + 1001b74: 8809883a mov r4,r17 + 1001b78: 10027440 call 1002744 <_Unwind_SjLj_Resume_or_Rethrow> + 1001b7c: 8809883a mov r4,r17 + 1001b80: 1001a0c0 call 1001a0c <__cxa_begin_catch> + 1001b84: 10019000 call 1001900 <_ZSt9terminatev> + 1001b88: 0091d3b4 movhi r2,18254 + 1001b8c: 109550c4 addi r2,r2,21827 + 1001b90: 20bff61e bne r4,r2,1001b6c <__cxa_rethrow+0x3c> + 1001b94: 88800517 ldw r2,20(r17) + 1001b98: 0085c83a sub r2,zero,r2 + 1001b9c: 88800515 stw r2,20(r17) + 1001ba0: 003ff306 br 1001b70 <__cxa_rethrow+0x40> + +01001ba4 <__cxa_throw>: + 1001ba4: 008040b4 movhi r2,258 + 1001ba8: 10ab9504 addi r2,r2,-20908 + 1001bac: 00c040b4 movhi r3,258 + 1001bb0: 18eb8f04 addi r3,r3,-20932 + 1001bb4: 12000017 ldw r8,0(r2) + 1001bb8: 19c00017 ldw r7,0(r3) + 1001bbc: defffe04 addi sp,sp,-8 + 1001bc0: 213ff004 addi r4,r4,-64 + 1001bc4: dfc00115 stw ra,4(sp) + 1001bc8: dc400015 stw r17,0(sp) + 1001bcc: 0090caf4 movhi r2,17195 + 1001bd0: 108ac004 addi r2,r2,11008 + 1001bd4: 20800b15 stw r2,44(r4) + 1001bd8: 00d1d3b4 movhi r3,18254 + 1001bdc: 18d550c4 addi r3,r3,21827 + 1001be0: 24400b04 addi r17,r4,44 + 1001be4: 00804034 movhi r2,256 + 1001be8: 10870604 addi r2,r2,7192 + 1001bec: 21400015 stw r5,0(r4) + 1001bf0: 21800115 stw r6,4(r4) + 1001bf4: 22000215 stw r8,8(r4) + 1001bf8: 21c00315 stw r7,12(r4) + 1001bfc: 20c00c15 stw r3,48(r4) + 1001c00: 20800d15 stw r2,52(r4) + 1001c04: 8809883a mov r4,r17 + 1001c08: 100257c0 call 100257c <_Unwind_SjLj_RaiseException> + 1001c0c: 8809883a mov r4,r17 + 1001c10: 1001a0c0 call 1001a0c <__cxa_begin_catch> + 1001c14: 10019000 call 1001900 <_ZSt9terminatev> + +01001c18 <_Z23__gxx_exception_cleanup19_Unwind_Reason_CodeP17_Unwind_Exception>: + 1001c18: defffe04 addi sp,sp,-8 + 1001c1c: 00800044 movi r2,1 + 1001c20: dfc00115 stw ra,4(sp) + 1001c24: dc000015 stw r16,0(sp) + 1001c28: 28fff504 addi r3,r5,-44 + 1001c2c: 11001036 bltu r2,r4,1001c70 <_Z23__gxx_exception_cleanup19_Unwind_Reason_CodeP17_Unwind_Exception+0x58> + 1001c30: 18800117 ldw r2,4(r3) + 1001c34: 10000826 beq r2,zero,1001c58 <_Z23__gxx_exception_cleanup19_Unwind_Reason_CodeP17_Unwind_Exception+0x40> + 1001c38: 2c000504 addi r16,r5,20 + 1001c3c: 8009883a mov r4,r16 + 1001c40: 103ee83a callr r2 + 1001c44: 8009883a mov r4,r16 + 1001c48: dfc00117 ldw ra,4(sp) + 1001c4c: dc000017 ldw r16,0(sp) + 1001c50: dec00204 addi sp,sp,8 + 1001c54: 1001e981 jmpi 1001e98 <__cxa_free_exception> + 1001c58: 2c000504 addi r16,r5,20 + 1001c5c: 8009883a mov r4,r16 + 1001c60: dfc00117 ldw ra,4(sp) + 1001c64: dc000017 ldw r16,0(sp) + 1001c68: dec00204 addi sp,sp,8 + 1001c6c: 1001e981 jmpi 1001e98 <__cxa_free_exception> + 1001c70: 19000317 ldw r4,12(r3) + 1001c74: 100185c0 call 100185c <_ZN10__cxxabiv111__terminateEPFvvE> + +01001c78 <_ZNK10__cxxabiv120__si_class_type_info11__do_upcastEPKNS_17__class_type_infoEPKvRNS1_15__upcast_resultE>: + 1001c78: defffb04 addi sp,sp,-20 + 1001c7c: dd400315 stw r21,12(sp) + 1001c80: dcc00215 stw r19,8(sp) + 1001c84: dc400115 stw r17,4(sp) + 1001c88: dc000015 stw r16,0(sp) + 1001c8c: 2823883a mov r17,r5 + 1001c90: 3027883a mov r19,r6 + 1001c94: 382b883a mov r21,r7 + 1001c98: dfc00415 stw ra,16(sp) + 1001c9c: 2021883a mov r16,r4 + 1001ca0: 1000bcc0 call 1000bcc <_ZNK10__cxxabiv117__class_type_info11__do_upcastEPKS0_PKvRNS0_15__upcast_resultE> + 1001ca4: 10803fcc andi r2,r2,255 + 1001ca8: 880b883a mov r5,r17 + 1001cac: 980d883a mov r6,r19 + 1001cb0: a80f883a mov r7,r21 + 1001cb4: 00c00044 movi r3,1 + 1001cb8: 1000051e bne r2,zero,1001cd0 <_ZNK10__cxxabiv120__si_class_type_info11__do_upcastEPKNS_17__class_type_infoEPKvRNS1_15__upcast_resultE+0x58> + 1001cbc: 81000217 ldw r4,8(r16) + 1001cc0: 20800017 ldw r2,0(r4) + 1001cc4: 10c00617 ldw r3,24(r2) + 1001cc8: 183ee83a callr r3 + 1001ccc: 10c03fcc andi r3,r2,255 + 1001cd0: 1805883a mov r2,r3 + 1001cd4: dfc00417 ldw ra,16(sp) + 1001cd8: dd400317 ldw r21,12(sp) + 1001cdc: dcc00217 ldw r19,8(sp) + 1001ce0: dc400117 ldw r17,4(sp) + 1001ce4: dc000017 ldw r16,0(sp) + 1001ce8: dec00504 addi sp,sp,20 + 1001cec: f800283a ret + +01001cf0 <_ZN10__cxxabiv120__si_class_type_infoD0Ev>: + 1001cf0: defffe04 addi sp,sp,-8 + 1001cf4: 008040b4 movhi r2,258 + 1001cf8: 10a32604 addi r2,r2,-29544 + 1001cfc: dc400015 stw r17,0(sp) + 1001d00: 20800015 stw r2,0(r4) + 1001d04: 2023883a mov r17,r4 + 1001d08: dfc00115 stw ra,4(sp) + 1001d0c: 1000b5c0 call 1000b5c <_ZN10__cxxabiv117__class_type_infoD2Ev> + 1001d10: 8809883a mov r4,r17 + 1001d14: dfc00117 ldw ra,4(sp) + 1001d18: dc400017 ldw r17,0(sp) + 1001d1c: dec00204 addi sp,sp,8 + 1001d20: 1001b241 jmpi 1001b24 <_ZdlPv> + +01001d24 <_ZN10__cxxabiv120__si_class_type_infoD1Ev>: + 1001d24: 008040b4 movhi r2,258 + 1001d28: 10a32604 addi r2,r2,-29544 + 1001d2c: 20800015 stw r2,0(r4) + 1001d30: 1000b5c1 jmpi 1000b5c <_ZN10__cxxabiv117__class_type_infoD2Ev> + +01001d34 <_ZN10__cxxabiv120__si_class_type_infoD2Ev>: + 1001d34: 008040b4 movhi r2,258 + 1001d38: 10a32604 addi r2,r2,-29544 + 1001d3c: 20800015 stw r2,0(r4) + 1001d40: 1000b5c1 jmpi 1000b5c <_ZN10__cxxabiv117__class_type_infoD2Ev> + +01001d44 <_ZNK10__cxxabiv120__si_class_type_info20__do_find_public_srcElPKvPKNS_17__class_type_infoES2_>: + 1001d44: da400017 ldw r9,0(sp) + 1001d48: 2011883a mov r8,r4 + 1001d4c: 49800526 beq r9,r6,1001d64 <_ZNK10__cxxabiv120__si_class_type_info20__do_find_public_srcElPKvPKNS_17__class_type_infoES2_+0x20> + 1001d50: 41000217 ldw r4,8(r8) + 1001d54: 20800017 ldw r2,0(r4) + 1001d58: da400015 stw r9,0(sp) + 1001d5c: 10c00817 ldw r3,32(r2) + 1001d60: 1800683a jmp r3 + 1001d64: 39000117 ldw r4,4(r7) + 1001d68: 40c00117 ldw r3,4(r8) + 1001d6c: 00800184 movi r2,6 + 1001d70: 193ff71e bne r3,r4,1001d50 <_ZNK10__cxxabiv120__si_class_type_info20__do_find_public_srcElPKvPKNS_17__class_type_infoES2_+0xc> + 1001d74: f800283a ret + +01001d78 <_ZNK10__cxxabiv120__si_class_type_info12__do_dyncastElNS_17__class_type_info10__sub_kindEPKS1_PKvS4_S6_RNS1_16__dyncast_resultE>: + 1001d78: 20c00117 ldw r3,4(r4) + 1001d7c: 38800117 ldw r2,4(r7) + 1001d80: defffb04 addi sp,sp,-20 + 1001d84: dfc00415 stw ra,16(sp) + 1001d88: da000517 ldw r8,20(sp) + 1001d8c: dac00617 ldw r11,24(sp) + 1001d90: da400717 ldw r9,28(sp) + 1001d94: da800817 ldw r10,32(sp) + 1001d98: 18800c1e bne r3,r2,1001dcc <_ZNK10__cxxabiv120__si_class_type_info12__do_dyncastElNS_17__class_type_info10__sub_kindEPKS1_PKvS4_S6_RNS1_16__dyncast_resultE+0x54> + 1001d9c: 51800115 stw r6,4(r10) + 1001da0: 52000015 stw r8,0(r10) + 1001da4: 28001c16 blt r5,zero,1001e18 <_ZNK10__cxxabiv120__si_class_type_info12__do_dyncastElNS_17__class_type_info10__sub_kindEPKS1_PKvS4_S6_RNS1_16__dyncast_resultE+0xa0> + 1001da8: 4145883a add r2,r8,r5 + 1001dac: 48801e26 beq r9,r2,1001e28 <_ZNK10__cxxabiv120__si_class_type_info12__do_dyncastElNS_17__class_type_info10__sub_kindEPKS1_PKvS4_S6_RNS1_16__dyncast_resultE+0xb0> + 1001db0: 00800044 movi r2,1 + 1001db4: 0007883a mov r3,zero + 1001db8: 50800315 stw r2,12(r10) + 1001dbc: 1805883a mov r2,r3 + 1001dc0: dfc00417 ldw ra,16(sp) + 1001dc4: dec00504 addi sp,sp,20 + 1001dc8: f800283a ret + 1001dcc: 42400d26 beq r8,r9,1001e04 <_ZNK10__cxxabiv120__si_class_type_info12__do_dyncastElNS_17__class_type_info10__sub_kindEPKS1_PKvS4_S6_RNS1_16__dyncast_resultE+0x8c> + 1001dd0: 21000217 ldw r4,8(r4) + 1001dd4: 20800017 ldw r2,0(r4) + 1001dd8: da000015 stw r8,0(sp) + 1001ddc: dac00115 stw r11,4(sp) + 1001de0: da400215 stw r9,8(sp) + 1001de4: da800315 stw r10,12(sp) + 1001de8: 10c00717 ldw r3,28(r2) + 1001dec: 183ee83a callr r3 + 1001df0: 10c03fcc andi r3,r2,255 + 1001df4: 1805883a mov r2,r3 + 1001df8: dfc00417 ldw ra,16(sp) + 1001dfc: dec00504 addi sp,sp,20 + 1001e00: f800283a ret + 1001e04: 58800117 ldw r2,4(r11) + 1001e08: 18bff11e bne r3,r2,1001dd0 <_ZNK10__cxxabiv120__si_class_type_info12__do_dyncastElNS_17__class_type_info10__sub_kindEPKS1_PKvS4_S6_RNS1_16__dyncast_resultE+0x58> + 1001e0c: 0007883a mov r3,zero + 1001e10: 51800215 stw r6,8(r10) + 1001e14: 003fe906 br 1001dbc <_ZNK10__cxxabiv120__si_class_type_info12__do_dyncastElNS_17__class_type_info10__sub_kindEPKS1_PKvS4_S6_RNS1_16__dyncast_resultE+0x44> + 1001e18: 00bfff84 movi r2,-2 + 1001e1c: 28800426 beq r5,r2,1001e30 <_ZNK10__cxxabiv120__si_class_type_info12__do_dyncastElNS_17__class_type_info10__sub_kindEPKS1_PKvS4_S6_RNS1_16__dyncast_resultE+0xb8> + 1001e20: 0007883a mov r3,zero + 1001e24: 003fe506 br 1001dbc <_ZNK10__cxxabiv120__si_class_type_info12__do_dyncastElNS_17__class_type_info10__sub_kindEPKS1_PKvS4_S6_RNS1_16__dyncast_resultE+0x44> + 1001e28: 00800184 movi r2,6 + 1001e2c: 003fe106 br 1001db4 <_ZNK10__cxxabiv120__si_class_type_info12__do_dyncastElNS_17__class_type_info10__sub_kindEPKS1_PKvS4_S6_RNS1_16__dyncast_resultE+0x3c> + 1001e30: 00800044 movi r2,1 + 1001e34: 0007883a mov r3,zero + 1001e38: 50800315 stw r2,12(r10) + 1001e3c: 003fdf06 br 1001dbc <_ZNK10__cxxabiv120__si_class_type_info12__do_dyncastElNS_17__class_type_info10__sub_kindEPKS1_PKvS4_S6_RNS1_16__dyncast_resultE+0x44> + +01001e40 <_ZNKSt9type_info14__is_pointer_pEv>: + 1001e40: 0005883a mov r2,zero + 1001e44: f800283a ret + +01001e48 <_ZNKSt9type_info15__is_function_pEv>: + 1001e48: 0005883a mov r2,zero + 1001e4c: f800283a ret + +01001e50 <_ZNKSt9type_info10__do_catchEPKS_PPvj>: + 1001e50: 20c00117 ldw r3,4(r4) + 1001e54: 28800117 ldw r2,4(r5) + 1001e58: 1885003a cmpeq r2,r3,r2 + 1001e5c: f800283a ret + +01001e60 <_ZNKSt9type_info11__do_upcastEPKN10__cxxabiv117__class_type_infoEPPv>: + 1001e60: 0005883a mov r2,zero + 1001e64: f800283a ret + +01001e68 <_ZNSt9type_infoD0Ev>: + 1001e68: 008040b4 movhi r2,258 + 1001e6c: 10a33e04 addi r2,r2,-29448 + 1001e70: 20800015 stw r2,0(r4) + 1001e74: 1001b241 jmpi 1001b24 <_ZdlPv> + +01001e78 <_ZNSt9type_infoD1Ev>: + 1001e78: 008040b4 movhi r2,258 + 1001e7c: 10a33e04 addi r2,r2,-29448 + 1001e80: 20800015 stw r2,0(r4) + 1001e84: f800283a ret + +01001e88 <_ZNSt9type_infoD2Ev>: + 1001e88: 008040b4 movhi r2,258 + 1001e8c: 10a33e04 addi r2,r2,-29448 + 1001e90: 20800015 stw r2,0(r4) + 1001e94: f800283a ret + +01001e98 <__cxa_free_exception>: + 1001e98: 2007883a mov r3,r4 + 1001e9c: 008040b4 movhi r2,258 + 1001ea0: 108b2b04 addi r2,r2,11436 + 1001ea4: 213ff004 addi r4,r4,-64 + 1001ea8: 11420004 addi r5,r2,2048 + 1001eac: 18800336 bltu r3,r2,1001ebc <__cxa_free_exception+0x24> + 1001eb0: 1885c83a sub r2,r3,r2 + 1001eb4: 1004d27a srli r2,r2,9 + 1001eb8: 19400136 bltu r3,r5,1001ec0 <__cxa_free_exception+0x28> + 1001ebc: 10027b41 jmpi 10027b4 + 1001ec0: 00ffff84 movi r3,-2 + 1001ec4: 1886183a rol r3,r3,r2 + 1001ec8: d0a76f17 ldw r2,-25156(gp) + 1001ecc: 10c4703a and r2,r2,r3 + 1001ed0: d0a76f15 stw r2,-25156(gp) + 1001ed4: f800283a ret + +01001ed8 <__cxa_allocate_exception>: + 1001ed8: deffed04 addi sp,sp,-76 + 1001edc: 00804034 movhi r2,256 + 1001ee0: 1084d504 addi r2,r2,4948 + 1001ee4: 21001004 addi r4,r4,64 + 1001ee8: 00c040b4 movhi r3,258 + 1001eec: 18e2ea04 addi r3,r3,-29784 + 1001ef0: d8800615 stw r2,24(sp) + 1001ef4: d9000d15 stw r4,52(sp) + 1001ef8: 00804034 movhi r2,256 + 1001efc: 1087fa04 addi r2,r2,8168 + 1001f00: d809883a mov r4,sp + 1001f04: dfc01215 stw ra,72(sp) + 1001f08: d8c00715 stw r3,28(sp) + 1001f0c: d8800915 stw r2,36(sp) + 1001f10: df001115 stw fp,68(sp) + 1001f14: ddc01015 stw r23,64(sp) + 1001f18: dec00815 stw sp,32(sp) + 1001f1c: dec00a15 stw sp,40(sp) + 1001f20: 10022540 call 1002254 <_Unwind_SjLj_Register> + 1001f24: d9000d17 ldw r4,52(sp) + 1001f28: 10027c80 call 10027c8 + 1001f2c: d8800e15 stw r2,56(sp) + 1001f30: 1000171e bne r2,zero,1001f90 <__cxa_allocate_exception+0xb8> + 1001f34: d8c00d17 ldw r3,52(sp) + 1001f38: 00808004 movi r2,512 + 1001f3c: d1e76f17 ldw r7,-25156(gp) + 1001f40: 10c02636 bltu r2,r3,1001fdc <__cxa_allocate_exception+0x104> + 1001f44: 3807883a mov r3,r7 + 1001f48: 01400044 movi r5,1 + 1001f4c: 1944703a and r2,r3,r5 + 1001f50: 0009883a mov r4,zero + 1001f54: 01800104 movi r6,4 + 1001f58: 10000526 beq r2,zero,1001f70 <__cxa_allocate_exception+0x98> + 1001f5c: 2149883a add r4,r4,r5 + 1001f60: 21801e26 beq r4,r6,1001fdc <__cxa_allocate_exception+0x104> + 1001f64: 1806d07a srli r3,r3,1 + 1001f68: 1944703a and r2,r3,r5 + 1001f6c: 103ffb1e bne r2,zero,1001f5c <__cxa_allocate_exception+0x84> + 1001f70: 2904983a sll r2,r5,r4 + 1001f74: 2008927a slli r4,r4,9 + 1001f78: 00c040b4 movhi r3,258 + 1001f7c: 18cb2b04 addi r3,r3,11436 + 1001f80: 3884b03a or r2,r7,r2 + 1001f84: 20c9883a add r4,r4,r3 + 1001f88: d9000e15 stw r4,56(sp) + 1001f8c: d0a76f15 stw r2,-25156(gp) + 1001f90: 100224c0 call 100224c <__cxa_get_globals> + 1001f94: 10c00117 ldw r3,4(r2) + 1001f98: d9000e17 ldw r4,56(sp) + 1001f9c: 000b883a mov r5,zero + 1001fa0: 18c00044 addi r3,r3,1 + 1001fa4: 10c00115 stw r3,4(r2) + 1001fa8: 01801004 movi r6,64 + 1001fac: 1002f1c0 call 1002f1c + 1001fb0: d8800e17 ldw r2,56(sp) + 1001fb4: d809883a mov r4,sp + 1001fb8: 10801004 addi r2,r2,64 + 1001fbc: d8800f15 stw r2,60(sp) + 1001fc0: 10022640 call 1002264 <_Unwind_SjLj_Unregister> + 1001fc4: d8800f17 ldw r2,60(sp) + 1001fc8: dfc01217 ldw ra,72(sp) + 1001fcc: df001117 ldw fp,68(sp) + 1001fd0: ddc01017 ldw r23,64(sp) + 1001fd4: dec01304 addi sp,sp,76 + 1001fd8: f800283a ret + 1001fdc: 00800044 movi r2,1 + 1001fe0: d8800115 stw r2,4(sp) + 1001fe4: 10019000 call 1001900 <_ZSt9terminatev> + 1001fe8: d8800317 ldw r2,12(sp) + 1001fec: 00ffffc4 movi r3,-1 + 1001ff0: d9000217 ldw r4,8(sp) + 1001ff4: 10c00226 beq r2,r3,1002000 <__cxa_allocate_exception+0x128> + 1001ff8: d8c00115 stw r3,4(sp) + 1001ffc: 10025200 call 1002520 <_Unwind_SjLj_Resume> + 1002000: 00bfffc4 movi r2,-1 + 1002004: d8800115 stw r2,4(sp) + 1002008: 10011d40 call 10011d4 <__cxa_call_unexpected> + +0100200c <_Znwm>: + 100200c: deffee04 addi sp,sp,-72 + 1002010: 00804034 movhi r2,256 + 1002014: 1084d504 addi r2,r2,4948 + 1002018: d8800615 stw r2,24(sp) + 100201c: 00c040b4 movhi r3,258 + 1002020: 18e2ee04 addi r3,r3,-29768 + 1002024: 00804034 movhi r2,256 + 1002028: 10883a04 addi r2,r2,8424 + 100202c: d9000e15 stw r4,56(sp) + 1002030: d809883a mov r4,sp + 1002034: d8800915 stw r2,36(sp) + 1002038: dfc01115 stw ra,68(sp) + 100203c: df001015 stw fp,64(sp) + 1002040: ddc00f15 stw r23,60(sp) + 1002044: d8c00715 stw r3,28(sp) + 1002048: dec00815 stw sp,32(sp) + 100204c: dec00a15 stw sp,40(sp) + 1002050: 10022540 call 1002254 <_Unwind_SjLj_Register> + 1002054: d8800e17 ldw r2,56(sp) + 1002058: 10000a1e bne r2,zero,1002084 <_Znwm+0x78> + 100205c: 00800044 movi r2,1 + 1002060: d8800e15 stw r2,56(sp) + 1002064: 00000706 br 1002084 <_Znwm+0x78> + 1002068: 008040b4 movhi r2,258 + 100206c: 10b2fd04 addi r2,r2,-13324 + 1002070: 10c00017 ldw r3,0(r2) + 1002074: 18000f26 beq r3,zero,10020b4 <_Znwm+0xa8> + 1002078: 00800044 movi r2,1 + 100207c: d8800115 stw r2,4(sp) + 1002080: 183ee83a callr r3 + 1002084: d9000e17 ldw r4,56(sp) + 1002088: 10027c80 call 10027c8 + 100208c: d8800d15 stw r2,52(sp) + 1002090: 103ff526 beq r2,zero,1002068 <_Znwm+0x5c> + 1002094: d809883a mov r4,sp + 1002098: 10022640 call 1002264 <_Unwind_SjLj_Unregister> + 100209c: d8800d17 ldw r2,52(sp) + 10020a0: dfc01117 ldw ra,68(sp) + 10020a4: df001017 ldw fp,64(sp) + 10020a8: ddc00f17 ldw r23,60(sp) + 10020ac: dec01204 addi sp,sp,72 + 10020b0: f800283a ret + 10020b4: 01000104 movi r4,4 + 10020b8: 1001ed80 call 1001ed8 <__cxa_allocate_exception> + 10020bc: 1009883a mov r4,r2 + 10020c0: 008040b4 movhi r2,258 + 10020c4: 10a36004 addi r2,r2,-29312 + 10020c8: 20800015 stw r2,0(r4) + 10020cc: 00c00044 movi r3,1 + 10020d0: d8c00115 stw r3,4(sp) + 10020d4: 014040b4 movhi r5,258 + 10020d8: 29636704 addi r5,r5,-29284 + 10020dc: 01804034 movhi r6,256 + 10020e0: 31888904 addi r6,r6,8740 + 10020e4: 1001ba40 call 1001ba4 <__cxa_throw> + 10020e8: d8800317 ldw r2,12(sp) + 10020ec: 00ffffc4 movi r3,-1 + 10020f0: d9000217 ldw r4,8(sp) + 10020f4: 10c00226 beq r2,r3,1002100 <_Znwm+0xf4> + 10020f8: d8c00115 stw r3,4(sp) + 10020fc: 10025200 call 1002520 <_Unwind_SjLj_Resume> + 1002100: 00bfffc4 movi r2,-1 + 1002104: d8800115 stw r2,4(sp) + 1002108: 10011d40 call 10011d4 <__cxa_call_unexpected> + +0100210c <_ZNKSt9exception4whatEv>: + 100210c: 20800017 ldw r2,0(r4) + 1002110: 10ffff17 ldw r3,-4(r2) + 1002114: 18800117 ldw r2,4(r3) + 1002118: f800283a ret + +0100211c <_ZNSt9exceptionD0Ev>: + 100211c: 008040b4 movhi r2,258 + 1002120: 10a34f04 addi r2,r2,-29380 + 1002124: 20800015 stw r2,0(r4) + 1002128: 1001b241 jmpi 1001b24 <_ZdlPv> + +0100212c <_ZNSt9exceptionD1Ev>: + 100212c: 008040b4 movhi r2,258 + 1002130: 10a34f04 addi r2,r2,-29380 + 1002134: 20800015 stw r2,0(r4) + 1002138: f800283a ret + +0100213c <_ZNSt9exceptionD2Ev>: + 100213c: 008040b4 movhi r2,258 + 1002140: 10a34f04 addi r2,r2,-29380 + 1002144: 20800015 stw r2,0(r4) + 1002148: f800283a ret + +0100214c <_ZNSt13bad_exceptionD0Ev>: + 100214c: defffe04 addi sp,sp,-8 + 1002150: 008040b4 movhi r2,258 + 1002154: 10a34a04 addi r2,r2,-29400 + 1002158: dc400015 stw r17,0(sp) + 100215c: 20800015 stw r2,0(r4) + 1002160: 2023883a mov r17,r4 + 1002164: dfc00115 stw ra,4(sp) + 1002168: 100213c0 call 100213c <_ZNSt9exceptionD2Ev> + 100216c: 8809883a mov r4,r17 + 1002170: dfc00117 ldw ra,4(sp) + 1002174: dc400017 ldw r17,0(sp) + 1002178: dec00204 addi sp,sp,8 + 100217c: 1001b241 jmpi 1001b24 <_ZdlPv> + +01002180 <_ZNSt13bad_exceptionD1Ev>: + 1002180: 008040b4 movhi r2,258 + 1002184: 10a34a04 addi r2,r2,-29400 + 1002188: 20800015 stw r2,0(r4) + 100218c: 100213c1 jmpi 100213c <_ZNSt9exceptionD2Ev> + +01002190 <_ZNSt13bad_exceptionD2Ev>: + 1002190: 008040b4 movhi r2,258 + 1002194: 10a34a04 addi r2,r2,-29400 + 1002198: 20800015 stw r2,0(r4) + 100219c: 100213c1 jmpi 100213c <_ZNSt9exceptionD2Ev> + +010021a0 <__cxa_call_terminate>: + 10021a0: defffe04 addi sp,sp,-8 + 10021a4: dc000015 stw r16,0(sp) + 10021a8: dfc00115 stw ra,4(sp) + 10021ac: 2021883a mov r16,r4 + 10021b0: 20000626 beq r4,zero,10021cc <__cxa_call_terminate+0x2c> + 10021b4: 1001a0c0 call 1001a0c <__cxa_begin_catch> + 10021b8: 80c00017 ldw r3,0(r16) + 10021bc: 0090caf4 movhi r2,17195 + 10021c0: 108ac004 addi r2,r2,11008 + 10021c4: 81000117 ldw r4,4(r16) + 10021c8: 18800126 beq r3,r2,10021d0 <__cxa_call_terminate+0x30> + 10021cc: 10019000 call 1001900 <_ZSt9terminatev> + 10021d0: 0091d3b4 movhi r2,18254 + 10021d4: 109550c4 addi r2,r2,21827 + 10021d8: 20bffc1e bne r4,r2,10021cc <__cxa_call_terminate+0x2c> + 10021dc: 813ff817 ldw r4,-32(r16) + 10021e0: 100185c0 call 100185c <_ZN10__cxxabiv111__terminateEPFvvE> + +010021e4 <_ZSt15set_new_handlerPFvvE>: + 10021e4: d0a77017 ldw r2,-25152(gp) + 10021e8: d1277015 stw r4,-25152(gp) + 10021ec: f800283a ret + +010021f0 <_ZNSt9bad_allocD0Ev>: + 10021f0: defffe04 addi sp,sp,-8 + 10021f4: 008040b4 movhi r2,258 + 10021f8: 10a36004 addi r2,r2,-29312 + 10021fc: dc400015 stw r17,0(sp) + 1002200: 20800015 stw r2,0(r4) + 1002204: 2023883a mov r17,r4 + 1002208: dfc00115 stw ra,4(sp) + 100220c: 100213c0 call 100213c <_ZNSt9exceptionD2Ev> + 1002210: 8809883a mov r4,r17 + 1002214: dfc00117 ldw ra,4(sp) + 1002218: dc400017 ldw r17,0(sp) + 100221c: dec00204 addi sp,sp,8 + 1002220: 1001b241 jmpi 1001b24 <_ZdlPv> + +01002224 <_ZNSt9bad_allocD1Ev>: + 1002224: 008040b4 movhi r2,258 + 1002228: 10a36004 addi r2,r2,-29312 + 100222c: 20800015 stw r2,0(r4) + 1002230: 100213c1 jmpi 100213c <_ZNSt9exceptionD2Ev> + +01002234 <_ZNSt9bad_allocD2Ev>: + 1002234: 008040b4 movhi r2,258 + 1002238: 10a36004 addi r2,r2,-29312 + 100223c: 20800015 stw r2,0(r4) + 1002240: 100213c1 jmpi 100213c <_ZNSt9exceptionD2Ev> + +01002244 <__cxa_get_globals_fast>: + 1002244: d0a77104 addi r2,gp,-25148 + 1002248: f800283a ret + +0100224c <__cxa_get_globals>: + 100224c: d0a77104 addi r2,gp,-25148 + 1002250: f800283a ret + +01002254 <_Unwind_SjLj_Register>: + 1002254: d0a77317 ldw r2,-25140(gp) + 1002258: 20800015 stw r2,0(r4) + 100225c: d1277315 stw r4,-25140(gp) + 1002260: f800283a ret + +01002264 <_Unwind_SjLj_Unregister>: + 1002264: 20800017 ldw r2,0(r4) + 1002268: d0a77315 stw r2,-25140(gp) + 100226c: f800283a ret + +01002270 <_Unwind_GetGR>: + 1002270: 20800017 ldw r2,0(r4) + 1002274: 294b883a add r5,r5,r5 + 1002278: 294b883a add r5,r5,r5 + 100227c: 288b883a add r5,r5,r2 + 1002280: 28800217 ldw r2,8(r5) + 1002284: f800283a ret + +01002288 <_Unwind_GetCFA>: + 1002288: 21000017 ldw r4,0(r4) + 100228c: 0005883a mov r2,zero + 1002290: 20000126 beq r4,zero,1002298 <_Unwind_GetCFA+0x10> + 1002294: 20800a17 ldw r2,40(r4) + 1002298: f800283a ret + +0100229c <_Unwind_SetGR>: + 100229c: 20800017 ldw r2,0(r4) + 10022a0: 294b883a add r5,r5,r5 + 10022a4: 294b883a add r5,r5,r5 + 10022a8: 288b883a add r5,r5,r2 + 10022ac: 29800215 stw r6,8(r5) + 10022b0: f800283a ret + +010022b4 <_Unwind_GetIP>: + 10022b4: 20c00017 ldw r3,0(r4) + 10022b8: 18800117 ldw r2,4(r3) + 10022bc: 10800044 addi r2,r2,1 + 10022c0: f800283a ret + +010022c4 <_Unwind_GetIPInfo>: + 10022c4: 20c00017 ldw r3,0(r4) + 10022c8: 28000015 stw zero,0(r5) + 10022cc: 18800117 ldw r2,4(r3) + 10022d0: 10800044 addi r2,r2,1 + 10022d4: f800283a ret + +010022d8 <_Unwind_SetIP>: + 10022d8: 20800017 ldw r2,0(r4) + 10022dc: 297fffc4 addi r5,r5,-1 + 10022e0: 11400115 stw r5,4(r2) + 10022e4: f800283a ret + +010022e8 <_Unwind_GetLanguageSpecificData>: + 10022e8: 20c00017 ldw r3,0(r4) + 10022ec: 18800717 ldw r2,28(r3) + 10022f0: f800283a ret + +010022f4 <_Unwind_GetRegionStart>: + 10022f4: 0005883a mov r2,zero + 10022f8: f800283a ret + +010022fc <_Unwind_FindEnclosingFunction>: + 10022fc: 0005883a mov r2,zero + 1002300: f800283a ret + +01002304 <_Unwind_GetDataRelBase>: + 1002304: 0005883a mov r2,zero + 1002308: f800283a ret + +0100230c <_Unwind_GetTextRelBase>: + 100230c: 0005883a mov r2,zero + 1002310: f800283a ret + +01002314 <_Unwind_ForcedUnwind_Phase2>: + 1002314: defff604 addi sp,sp,-40 + 1002318: dd400815 stw r21,32(sp) + 100231c: dd000715 stw r20,28(sp) + 1002320: 25400317 ldw r21,12(r4) + 1002324: 25000417 ldw r20,16(r4) + 1002328: 28800017 ldw r2,0(r5) + 100232c: dc800515 stw r18,20(sp) + 1002330: dc000315 stw r16,12(sp) + 1002334: 2825883a mov r18,r5 + 1002338: 2021883a mov r16,r4 + 100233c: dfc00915 stw ra,36(sp) + 1002340: dcc00615 stw r19,24(sp) + 1002344: dc400415 stw r17,16(sp) + 1002348: 00001406 br 100239c <_Unwind_ForcedUnwind_Phase2+0x88> + 100234c: 00800144 movi r2,5 + 1002350: 88802626 beq r17,r2,10023ec <_Unwind_ForcedUnwind_Phase2+0xd8> + 1002354: 98000c26 beq r19,zero,1002388 <_Unwind_ForcedUnwind_Phase2+0x74> + 1002358: 82000017 ldw r8,0(r16) + 100235c: dc000015 stw r16,0(sp) + 1002360: dc800115 stw r18,4(sp) + 1002364: 82400117 ldw r9,4(r16) + 1002368: 400d883a mov r6,r8 + 100236c: 480f883a mov r7,r9 + 1002370: 983ee83a callr r19 + 1002374: 1023883a mov r17,r2 + 1002378: 008001c4 movi r2,7 + 100237c: 88801b26 beq r17,r2,10023ec <_Unwind_ForcedUnwind_Phase2+0xd8> + 1002380: 00800204 movi r2,8 + 1002384: 8880181e bne r17,r2,10023e8 <_Unwind_ForcedUnwind_Phase2+0xd4> + 1002388: 91000017 ldw r4,0(r18) + 100238c: 10022640 call 1002264 <_Unwind_SjLj_Unregister> + 1002390: 90800017 ldw r2,0(r18) + 1002394: 10800017 ldw r2,0(r2) + 1002398: 90800015 stw r2,0(r18) + 100239c: 01400684 movi r5,26 + 10023a0: 04400144 movi r17,5 + 10023a4: 0027883a mov r19,zero + 10023a8: 10000326 beq r2,zero,10023b8 <_Unwind_ForcedUnwind_Phase2+0xa4> + 10023ac: 14c00617 ldw r19,24(r2) + 10023b0: 0023883a mov r17,zero + 10023b4: 01400284 movi r5,10 + 10023b8: dc000015 stw r16,0(sp) + 10023bc: dc800115 stw r18,4(sp) + 10023c0: 80800017 ldw r2,0(r16) + 10023c4: dd000215 stw r20,8(sp) + 10023c8: 80c00117 ldw r3,4(r16) + 10023cc: 01000044 movi r4,1 + 10023d0: 100d883a mov r6,r2 + 10023d4: 180f883a mov r7,r3 + 10023d8: a83ee83a callr r21 + 10023dc: 01400284 movi r5,10 + 10023e0: 01000044 movi r4,1 + 10023e4: 103fd926 beq r2,zero,100234c <_Unwind_ForcedUnwind_Phase2+0x38> + 10023e8: 04400084 movi r17,2 + 10023ec: 8805883a mov r2,r17 + 10023f0: dfc00917 ldw ra,36(sp) + 10023f4: dd400817 ldw r21,32(sp) + 10023f8: dd000717 ldw r20,28(sp) + 10023fc: dcc00617 ldw r19,24(sp) + 1002400: dc800517 ldw r18,20(sp) + 1002404: dc400417 ldw r17,16(sp) + 1002408: dc000317 ldw r16,12(sp) + 100240c: dec00a04 addi sp,sp,40 + 1002410: f800283a ret + +01002414 <_Unwind_DeleteException>: + 1002414: 20800217 ldw r2,8(r4) + 1002418: 200b883a mov r5,r4 + 100241c: 01000044 movi r4,1 + 1002420: 10000126 beq r2,zero,1002428 <_Unwind_DeleteException+0x14> + 1002424: 1000683a jmp r2 + 1002428: f800283a ret + +0100242c <_Unwind_RaiseException_Phase2>: + 100242c: defffa04 addi sp,sp,-24 + 1002430: dc800415 stw r18,16(sp) + 1002434: 2825883a mov r18,r5 + 1002438: 29400017 ldw r5,0(r5) + 100243c: dc400315 stw r17,12(sp) + 1002440: dfc00515 stw ra,20(sp) + 1002444: dc000215 stw r16,8(sp) + 1002448: 2023883a mov r17,r4 + 100244c: 28001b26 beq r5,zero,10024bc <_Unwind_RaiseException_Phase2+0x90> + 1002450: 88800417 ldw r2,16(r17) + 1002454: 0007883a mov r3,zero + 1002458: 2a000617 ldw r8,24(r5) + 100245c: 28a1003a cmpeq r16,r5,r2 + 1002460: 802090ba slli r16,r16,2 + 1002464: 18001b1e bne r3,zero,10024d4 <_Unwind_RaiseException_Phase2+0xa8> + 1002468: 40000e26 beq r8,zero,10024a4 <_Unwind_RaiseException_Phase2+0x78> + 100246c: 88800017 ldw r2,0(r17) + 1002470: dc400015 stw r17,0(sp) + 1002474: dc800115 stw r18,4(sp) + 1002478: 88c00117 ldw r3,4(r17) + 100247c: 01000044 movi r4,1 + 1002480: 81400094 ori r5,r16,2 + 1002484: 180f883a mov r7,r3 + 1002488: 100d883a mov r6,r2 + 100248c: 403ee83a callr r8 + 1002490: 1007883a mov r3,r2 + 1002494: 008001c4 movi r2,7 + 1002498: 18800f26 beq r3,r2,10024d8 <_Unwind_RaiseException_Phase2+0xac> + 100249c: 00800204 movi r2,8 + 10024a0: 18800c1e bne r3,r2,10024d4 <_Unwind_RaiseException_Phase2+0xa8> + 10024a4: 8000131e bne r16,zero,10024f4 <_Unwind_RaiseException_Phase2+0xc8> + 10024a8: 91400017 ldw r5,0(r18) + 10024ac: 28800017 ldw r2,0(r5) + 10024b0: 100b883a mov r5,r2 + 10024b4: 90800015 stw r2,0(r18) + 10024b8: 283fe51e bne r5,zero,1002450 <_Unwind_RaiseException_Phase2+0x24> + 10024bc: 88800417 ldw r2,16(r17) + 10024c0: 00c00144 movi r3,5 + 10024c4: 0011883a mov r8,zero + 10024c8: 28a1003a cmpeq r16,r5,r2 + 10024cc: 802090ba slli r16,r16,2 + 10024d0: 183fe526 beq r3,zero,1002468 <_Unwind_RaiseException_Phase2+0x3c> + 10024d4: 00c00084 movi r3,2 + 10024d8: 1805883a mov r2,r3 + 10024dc: dfc00517 ldw ra,20(sp) + 10024e0: dc800417 ldw r18,16(sp) + 10024e4: dc400317 ldw r17,12(sp) + 10024e8: dc000217 ldw r16,8(sp) + 10024ec: dec00604 addi sp,sp,24 + 10024f0: f800283a ret + 10024f4: 100279c0 call 100279c + +010024f8 : + 10024f8: 28800017 ldw r2,0(r5) + 10024fc: deffff04 addi sp,sp,-4 + 1002500: df000015 stw fp,0(sp) + 1002504: 10c00804 addi r3,r2,32 + 1002508: d839883a mov fp,sp + 100250c: d0a77315 stw r2,-25140(gp) + 1002510: 19000117 ldw r4,4(r3) + 1002514: 1f000017 ldw fp,0(r3) + 1002518: 1ec00217 ldw sp,8(r3) + 100251c: 2000683a jmp r4 + +01002520 <_Unwind_SjLj_Resume>: + 1002520: d0e77317 ldw r3,-25140(gp) + 1002524: 20800317 ldw r2,12(r4) + 1002528: defffc04 addi sp,sp,-16 + 100252c: dfc00315 stw ra,12(sp) + 1002530: dc000215 stw r16,8(sp) + 1002534: d8c00015 stw r3,0(sp) + 1002538: d8c00115 stw r3,4(sp) + 100253c: 1000071e bne r2,zero,100255c <_Unwind_SjLj_Resume+0x3c> + 1002540: dc000104 addi r16,sp,4 + 1002544: 800b883a mov r5,r16 + 1002548: 100242c0 call 100242c <_Unwind_RaiseException_Phase2> + 100254c: 1007883a mov r3,r2 + 1002550: 008001c4 movi r2,7 + 1002554: 18800626 beq r3,r2,1002570 <_Unwind_SjLj_Resume+0x50> + 1002558: 100279c0 call 100279c + 100255c: dc000104 addi r16,sp,4 + 1002560: 800b883a mov r5,r16 + 1002564: 10023140 call 1002314 <_Unwind_ForcedUnwind_Phase2> + 1002568: 1007883a mov r3,r2 + 100256c: 003ff806 br 1002550 <_Unwind_SjLj_Resume+0x30> + 1002570: 800b883a mov r5,r16 + 1002574: d809883a mov r4,sp + 1002578: 10024f80 call 10024f8 + +0100257c <_Unwind_SjLj_RaiseException>: + 100257c: d0a77317 ldw r2,-25140(gp) + 1002580: defff804 addi sp,sp,-32 + 1002584: dc000415 stw r16,16(sp) + 1002588: dfc00715 stw ra,28(sp) + 100258c: dc800615 stw r18,24(sp) + 1002590: dc400515 stw r17,20(sp) + 1002594: 2021883a mov r16,r4 + 1002598: d8800215 stw r2,8(sp) + 100259c: d8800315 stw r2,12(sp) + 10025a0: 10001626 beq r2,zero,10025fc <_Unwind_SjLj_RaiseException+0x80> + 10025a4: dc400304 addi r17,sp,12 + 10025a8: 04800184 movi r18,6 + 10025ac: 00000106 br 10025b4 <_Unwind_SjLj_RaiseException+0x38> + 10025b0: d8800315 stw r2,12(sp) + 10025b4: 12000617 ldw r8,24(r2) + 10025b8: 40000d26 beq r8,zero,10025f0 <_Unwind_SjLj_RaiseException+0x74> + 10025bc: 80800017 ldw r2,0(r16) + 10025c0: dc000015 stw r16,0(sp) + 10025c4: 80c00117 ldw r3,4(r16) + 10025c8: 01000044 movi r4,1 + 10025cc: dc400115 stw r17,4(sp) + 10025d0: 180f883a mov r7,r3 + 10025d4: 200b883a mov r5,r4 + 10025d8: 100d883a mov r6,r2 + 10025dc: 403ee83a callr r8 + 10025e0: 1007883a mov r3,r2 + 10025e4: 14800d26 beq r2,r18,100261c <_Unwind_SjLj_RaiseException+0xa0> + 10025e8: 00800204 movi r2,8 + 10025ec: 1880191e bne r3,r2,1002654 <_Unwind_SjLj_RaiseException+0xd8> + 10025f0: d8800317 ldw r2,12(sp) + 10025f4: 10800017 ldw r2,0(r2) + 10025f8: 103fed1e bne r2,zero,10025b0 <_Unwind_SjLj_RaiseException+0x34> + 10025fc: 00c00144 movi r3,5 + 1002600: 1805883a mov r2,r3 + 1002604: dfc00717 ldw ra,28(sp) + 1002608: dc800617 ldw r18,24(sp) + 100260c: dc400517 ldw r17,20(sp) + 1002610: dc000417 ldw r16,16(sp) + 1002614: dec00804 addi sp,sp,32 + 1002618: f800283a ret + 100261c: d8800317 ldw r2,12(sp) + 1002620: 80000315 stw zero,12(r16) + 1002624: 8009883a mov r4,r16 + 1002628: 80800415 stw r2,16(r16) + 100262c: d8800217 ldw r2,8(sp) + 1002630: 880b883a mov r5,r17 + 1002634: d8800315 stw r2,12(sp) + 1002638: 100242c0 call 100242c <_Unwind_RaiseException_Phase2> + 100263c: 1007883a mov r3,r2 + 1002640: 008001c4 movi r2,7 + 1002644: 18bfee1e bne r3,r2,1002600 <_Unwind_SjLj_RaiseException+0x84> + 1002648: 880b883a mov r5,r17 + 100264c: d9000204 addi r4,sp,8 + 1002650: 10024f80 call 10024f8 + 1002654: 00c000c4 movi r3,3 + 1002658: 1805883a mov r2,r3 + 100265c: dfc00717 ldw ra,28(sp) + 1002660: dc800617 ldw r18,24(sp) + 1002664: dc400517 ldw r17,20(sp) + 1002668: dc000417 ldw r16,16(sp) + 100266c: dec00804 addi sp,sp,32 + 1002670: f800283a ret + +01002674 <_Unwind_SjLj_ForcedUnwind>: + 1002674: defffc04 addi sp,sp,-16 + 1002678: d0a77317 ldw r2,-25140(gp) + 100267c: dc000215 stw r16,8(sp) + 1002680: dc000104 addi r16,sp,4 + 1002684: 21400315 stw r5,12(r4) + 1002688: 21800415 stw r6,16(r4) + 100268c: 800b883a mov r5,r16 + 1002690: dfc00315 stw ra,12(sp) + 1002694: d8800015 stw r2,0(sp) + 1002698: d8800115 stw r2,4(sp) + 100269c: 10023140 call 1002314 <_Unwind_ForcedUnwind_Phase2> + 10026a0: 00c001c4 movi r3,7 + 10026a4: 10c00426 beq r2,r3,10026b8 <_Unwind_SjLj_ForcedUnwind+0x44> + 10026a8: dfc00317 ldw ra,12(sp) + 10026ac: dc000217 ldw r16,8(sp) + 10026b0: dec00404 addi sp,sp,16 + 10026b4: f800283a ret + 10026b8: 800b883a mov r5,r16 + 10026bc: d809883a mov r4,sp + 10026c0: 10024f80 call 10024f8 + +010026c4 <_Unwind_Backtrace>: + 10026c4: d0a77317 ldw r2,-25140(gp) + 10026c8: defffa04 addi sp,sp,-24 + 10026cc: dcc00415 stw r19,16(sp) + 10026d0: dc800315 stw r18,12(sp) + 10026d4: dc400215 stw r17,8(sp) + 10026d8: 2025883a mov r18,r4 + 10026dc: 2823883a mov r17,r5 + 10026e0: 04c00144 movi r19,5 + 10026e4: dfc00515 stw ra,20(sp) + 10026e8: dc000115 stw r16,4(sp) + 10026ec: d8800015 stw r2,0(sp) + 10026f0: 00000406 br 1002704 <_Unwind_Backtrace+0x40> + 10026f4: 84c00b26 beq r16,r19,1002724 <_Unwind_Backtrace+0x60> + 10026f8: d8800017 ldw r2,0(sp) + 10026fc: 10800017 ldw r2,0(r2) + 1002700: d8800015 stw r2,0(sp) + 1002704: 04000144 movi r16,5 + 1002708: 10000126 beq r2,zero,1002710 <_Unwind_Backtrace+0x4c> + 100270c: 0021883a mov r16,zero + 1002710: d809883a mov r4,sp + 1002714: 880b883a mov r5,r17 + 1002718: 903ee83a callr r18 + 100271c: 103ff526 beq r2,zero,10026f4 <_Unwind_Backtrace+0x30> + 1002720: 040000c4 movi r16,3 + 1002724: 8005883a mov r2,r16 + 1002728: dfc00517 ldw ra,20(sp) + 100272c: dcc00417 ldw r19,16(sp) + 1002730: dc800317 ldw r18,12(sp) + 1002734: dc400217 ldw r17,8(sp) + 1002738: dc000117 ldw r16,4(sp) + 100273c: dec00604 addi sp,sp,24 + 1002740: f800283a ret + +01002744 <_Unwind_SjLj_Resume_or_Rethrow>: + 1002744: 20800317 ldw r2,12(r4) + 1002748: defffc04 addi sp,sp,-16 + 100274c: dfc00315 stw ra,12(sp) + 1002750: dc000215 stw r16,8(sp) + 1002754: 10000926 beq r2,zero,100277c <_Unwind_SjLj_Resume_or_Rethrow+0x38> + 1002758: d0a77317 ldw r2,-25140(gp) + 100275c: dc000104 addi r16,sp,4 + 1002760: 800b883a mov r5,r16 + 1002764: d8800015 stw r2,0(sp) + 1002768: d8800115 stw r2,4(sp) + 100276c: 10023140 call 1002314 <_Unwind_ForcedUnwind_Phase2> + 1002770: 00c001c4 movi r3,7 + 1002774: 10c00626 beq r2,r3,1002790 <_Unwind_SjLj_Resume_or_Rethrow+0x4c> + 1002778: 100279c0 call 100279c + 100277c: 100257c0 call 100257c <_Unwind_SjLj_RaiseException> + 1002780: dfc00317 ldw ra,12(sp) + 1002784: dc000217 ldw r16,8(sp) + 1002788: dec00404 addi sp,sp,16 + 100278c: f800283a ret + 1002790: 800b883a mov r5,r16 + 1002794: d809883a mov r4,sp + 1002798: 10024f80 call 10024f8 + +0100279c : + 100279c: deffff04 addi sp,sp,-4 + 10027a0: 01000184 movi r4,6 + 10027a4: dfc00015 stw ra,0(sp) + 10027a8: 100321c0 call 100321c + 10027ac: 01000044 movi r4,1 + 10027b0: 100c4380 call 100c438 <_exit> + +010027b4 : + 10027b4: 008040b4 movhi r2,258 + 10027b8: 10ab9804 addi r2,r2,-20896 + 10027bc: 200b883a mov r5,r4 + 10027c0: 11000017 ldw r4,0(r2) + 10027c4: 10073601 jmpi 1007360 <_free_r> + +010027c8 : + 10027c8: 008040b4 movhi r2,258 + 10027cc: 10ab9804 addi r2,r2,-20896 + 10027d0: 200b883a mov r5,r4 + 10027d4: 11000017 ldw r4,0(r2) + 10027d8: 10027dc1 jmpi 10027dc <_malloc_r> + +010027dc <_malloc_r>: + 10027dc: defff604 addi sp,sp,-40 + 10027e0: 28c002c4 addi r3,r5,11 + 10027e4: 00800584 movi r2,22 + 10027e8: dc800215 stw r18,8(sp) + 10027ec: dfc00915 stw ra,36(sp) + 10027f0: df000815 stw fp,32(sp) + 10027f4: ddc00715 stw r23,28(sp) + 10027f8: dd800615 stw r22,24(sp) + 10027fc: dd400515 stw r21,20(sp) + 1002800: dd000415 stw r20,16(sp) + 1002804: dcc00315 stw r19,12(sp) + 1002808: dc400115 stw r17,4(sp) + 100280c: dc000015 stw r16,0(sp) + 1002810: 2025883a mov r18,r4 + 1002814: 10c01236 bltu r2,r3,1002860 <_malloc_r+0x84> + 1002818: 04400404 movi r17,16 + 100281c: 8940142e bgeu r17,r5,1002870 <_malloc_r+0x94> + 1002820: 00800304 movi r2,12 + 1002824: 0007883a mov r3,zero + 1002828: 90800015 stw r2,0(r18) + 100282c: 1805883a mov r2,r3 + 1002830: dfc00917 ldw ra,36(sp) + 1002834: df000817 ldw fp,32(sp) + 1002838: ddc00717 ldw r23,28(sp) + 100283c: dd800617 ldw r22,24(sp) + 1002840: dd400517 ldw r21,20(sp) + 1002844: dd000417 ldw r20,16(sp) + 1002848: dcc00317 ldw r19,12(sp) + 100284c: dc800217 ldw r18,8(sp) + 1002850: dc400117 ldw r17,4(sp) + 1002854: dc000017 ldw r16,0(sp) + 1002858: dec00a04 addi sp,sp,40 + 100285c: f800283a ret + 1002860: 00bffe04 movi r2,-8 + 1002864: 18a2703a and r17,r3,r2 + 1002868: 883fed16 blt r17,zero,1002820 <_malloc_r+0x44> + 100286c: 897fec36 bltu r17,r5,1002820 <_malloc_r+0x44> + 1002870: 9009883a mov r4,r18 + 1002874: 100d0a00 call 100d0a0 <__malloc_lock> + 1002878: 00807dc4 movi r2,503 + 100287c: 14402b2e bgeu r2,r17,100292c <_malloc_r+0x150> + 1002880: 8806d27a srli r3,r17,9 + 1002884: 18003f1e bne r3,zero,1002984 <_malloc_r+0x1a8> + 1002888: 880cd0fa srli r6,r17,3 + 100288c: 300490fa slli r2,r6,3 + 1002890: 02c040b4 movhi r11,258 + 1002894: 5ae49004 addi r11,r11,-28096 + 1002898: 12cb883a add r5,r2,r11 + 100289c: 2c000317 ldw r16,12(r5) + 10028a0: 580f883a mov r7,r11 + 10028a4: 2c00041e bne r5,r16,10028b8 <_malloc_r+0xdc> + 10028a8: 00000a06 br 10028d4 <_malloc_r+0xf8> + 10028ac: 1800860e bge r3,zero,1002ac8 <_malloc_r+0x2ec> + 10028b0: 84000317 ldw r16,12(r16) + 10028b4: 2c000726 beq r5,r16,10028d4 <_malloc_r+0xf8> + 10028b8: 80800117 ldw r2,4(r16) + 10028bc: 00ffff04 movi r3,-4 + 10028c0: 10c8703a and r4,r2,r3 + 10028c4: 2447c83a sub r3,r4,r17 + 10028c8: 008003c4 movi r2,15 + 10028cc: 10fff70e bge r2,r3,10028ac <_malloc_r+0xd0> + 10028d0: 31bfffc4 addi r6,r6,-1 + 10028d4: 32400044 addi r9,r6,1 + 10028d8: 028040b4 movhi r10,258 + 10028dc: 52a49204 addi r10,r10,-28088 + 10028e0: 54000217 ldw r16,8(r10) + 10028e4: 8280a026 beq r16,r10,1002b68 <_malloc_r+0x38c> + 10028e8: 80800117 ldw r2,4(r16) + 10028ec: 00ffff04 movi r3,-4 + 10028f0: 10ca703a and r5,r2,r3 + 10028f4: 2c4dc83a sub r6,r5,r17 + 10028f8: 008003c4 movi r2,15 + 10028fc: 11808316 blt r2,r6,1002b0c <_malloc_r+0x330> + 1002900: 52800315 stw r10,12(r10) + 1002904: 52800215 stw r10,8(r10) + 1002908: 30002916 blt r6,zero,10029b0 <_malloc_r+0x1d4> + 100290c: 8147883a add r3,r16,r5 + 1002910: 18800117 ldw r2,4(r3) + 1002914: 9009883a mov r4,r18 + 1002918: 10800054 ori r2,r2,1 + 100291c: 18800115 stw r2,4(r3) + 1002920: 100d1a80 call 100d1a8 <__malloc_unlock> + 1002924: 80c00204 addi r3,r16,8 + 1002928: 003fc006 br 100282c <_malloc_r+0x50> + 100292c: 02c040b4 movhi r11,258 + 1002930: 5ae49004 addi r11,r11,-28096 + 1002934: 8ac5883a add r2,r17,r11 + 1002938: 14000317 ldw r16,12(r2) + 100293c: 580f883a mov r7,r11 + 1002940: 8806d0fa srli r3,r17,3 + 1002944: 14006c26 beq r2,r16,1002af8 <_malloc_r+0x31c> + 1002948: 80c00117 ldw r3,4(r16) + 100294c: 00bfff04 movi r2,-4 + 1002950: 81800317 ldw r6,12(r16) + 1002954: 1886703a and r3,r3,r2 + 1002958: 80c7883a add r3,r16,r3 + 100295c: 18800117 ldw r2,4(r3) + 1002960: 81400217 ldw r5,8(r16) + 1002964: 9009883a mov r4,r18 + 1002968: 10800054 ori r2,r2,1 + 100296c: 18800115 stw r2,4(r3) + 1002970: 31400215 stw r5,8(r6) + 1002974: 29800315 stw r6,12(r5) + 1002978: 100d1a80 call 100d1a8 <__malloc_unlock> + 100297c: 80c00204 addi r3,r16,8 + 1002980: 003faa06 br 100282c <_malloc_r+0x50> + 1002984: 00800104 movi r2,4 + 1002988: 10c0052e bgeu r2,r3,10029a0 <_malloc_r+0x1c4> + 100298c: 00800504 movi r2,20 + 1002990: 10c07836 bltu r2,r3,1002b74 <_malloc_r+0x398> + 1002994: 198016c4 addi r6,r3,91 + 1002998: 300490fa slli r2,r6,3 + 100299c: 003fbc06 br 1002890 <_malloc_r+0xb4> + 10029a0: 8804d1ba srli r2,r17,6 + 10029a4: 11800e04 addi r6,r2,56 + 10029a8: 300490fa slli r2,r6,3 + 10029ac: 003fb806 br 1002890 <_malloc_r+0xb4> + 10029b0: 00807fc4 movi r2,511 + 10029b4: 1140bb36 bltu r2,r5,1002ca4 <_malloc_r+0x4c8> + 10029b8: 2806d0fa srli r3,r5,3 + 10029bc: 573ffe04 addi fp,r10,-8 + 10029c0: 00800044 movi r2,1 + 10029c4: 180890fa slli r4,r3,3 + 10029c8: 1807d0ba srai r3,r3,2 + 10029cc: e1c00117 ldw r7,4(fp) + 10029d0: 5909883a add r4,r11,r4 + 10029d4: 21400217 ldw r5,8(r4) + 10029d8: 10c4983a sll r2,r2,r3 + 10029dc: 81000315 stw r4,12(r16) + 10029e0: 81400215 stw r5,8(r16) + 10029e4: 388eb03a or r7,r7,r2 + 10029e8: 2c000315 stw r16,12(r5) + 10029ec: 24000215 stw r16,8(r4) + 10029f0: e1c00115 stw r7,4(fp) + 10029f4: 4807883a mov r3,r9 + 10029f8: 4800cd16 blt r9,zero,1002d30 <_malloc_r+0x554> + 10029fc: 1807d0ba srai r3,r3,2 + 1002a00: 00800044 movi r2,1 + 1002a04: 10c8983a sll r4,r2,r3 + 1002a08: 39004436 bltu r7,r4,1002b1c <_malloc_r+0x340> + 1002a0c: 21c4703a and r2,r4,r7 + 1002a10: 10000a1e bne r2,zero,1002a3c <_malloc_r+0x260> + 1002a14: 2109883a add r4,r4,r4 + 1002a18: 00bfff04 movi r2,-4 + 1002a1c: 4884703a and r2,r9,r2 + 1002a20: 3906703a and r3,r7,r4 + 1002a24: 12400104 addi r9,r2,4 + 1002a28: 1800041e bne r3,zero,1002a3c <_malloc_r+0x260> + 1002a2c: 2109883a add r4,r4,r4 + 1002a30: 3904703a and r2,r7,r4 + 1002a34: 4a400104 addi r9,r9,4 + 1002a38: 103ffc26 beq r2,zero,1002a2c <_malloc_r+0x250> + 1002a3c: 480490fa slli r2,r9,3 + 1002a40: 4819883a mov r12,r9 + 1002a44: 023fff04 movi r8,-4 + 1002a48: 589b883a add r13,r11,r2 + 1002a4c: 6807883a mov r3,r13 + 1002a50: 014003c4 movi r5,15 + 1002a54: 1c000317 ldw r16,12(r3) + 1002a58: 1c00041e bne r3,r16,1002a6c <_malloc_r+0x290> + 1002a5c: 0000a706 br 1002cfc <_malloc_r+0x520> + 1002a60: 3000ab0e bge r6,zero,1002d10 <_malloc_r+0x534> + 1002a64: 84000317 ldw r16,12(r16) + 1002a68: 1c00a426 beq r3,r16,1002cfc <_malloc_r+0x520> + 1002a6c: 80800117 ldw r2,4(r16) + 1002a70: 1204703a and r2,r2,r8 + 1002a74: 144dc83a sub r6,r2,r17 + 1002a78: 29bff90e bge r5,r6,1002a60 <_malloc_r+0x284> + 1002a7c: 81000317 ldw r4,12(r16) + 1002a80: 80c00217 ldw r3,8(r16) + 1002a84: 89400054 ori r5,r17,1 + 1002a88: 8445883a add r2,r16,r17 + 1002a8c: 20c00215 stw r3,8(r4) + 1002a90: 19000315 stw r4,12(r3) + 1002a94: 81400115 stw r5,4(r16) + 1002a98: 1187883a add r3,r2,r6 + 1002a9c: 31000054 ori r4,r6,1 + 1002aa0: 50800315 stw r2,12(r10) + 1002aa4: 50800215 stw r2,8(r10) + 1002aa8: 19800015 stw r6,0(r3) + 1002aac: 11000115 stw r4,4(r2) + 1002ab0: 12800215 stw r10,8(r2) + 1002ab4: 12800315 stw r10,12(r2) + 1002ab8: 9009883a mov r4,r18 + 1002abc: 100d1a80 call 100d1a8 <__malloc_unlock> + 1002ac0: 80c00204 addi r3,r16,8 + 1002ac4: 003f5906 br 100282c <_malloc_r+0x50> + 1002ac8: 8109883a add r4,r16,r4 + 1002acc: 20800117 ldw r2,4(r4) + 1002ad0: 80c00217 ldw r3,8(r16) + 1002ad4: 81400317 ldw r5,12(r16) + 1002ad8: 10800054 ori r2,r2,1 + 1002adc: 20800115 stw r2,4(r4) + 1002ae0: 28c00215 stw r3,8(r5) + 1002ae4: 19400315 stw r5,12(r3) + 1002ae8: 9009883a mov r4,r18 + 1002aec: 100d1a80 call 100d1a8 <__malloc_unlock> + 1002af0: 80c00204 addi r3,r16,8 + 1002af4: 003f4d06 br 100282c <_malloc_r+0x50> + 1002af8: 80800204 addi r2,r16,8 + 1002afc: 14000317 ldw r16,12(r2) + 1002b00: 143f911e bne r2,r16,1002948 <_malloc_r+0x16c> + 1002b04: 1a400084 addi r9,r3,2 + 1002b08: 003f7306 br 10028d8 <_malloc_r+0xfc> + 1002b0c: 88c00054 ori r3,r17,1 + 1002b10: 8445883a add r2,r16,r17 + 1002b14: 80c00115 stw r3,4(r16) + 1002b18: 003fdf06 br 1002a98 <_malloc_r+0x2bc> + 1002b1c: e4000217 ldw r16,8(fp) + 1002b20: 00bfff04 movi r2,-4 + 1002b24: 80c00117 ldw r3,4(r16) + 1002b28: 802d883a mov r22,r16 + 1002b2c: 18aa703a and r21,r3,r2 + 1002b30: ac401636 bltu r21,r17,1002b8c <_malloc_r+0x3b0> + 1002b34: ac49c83a sub r4,r21,r17 + 1002b38: 008003c4 movi r2,15 + 1002b3c: 1100130e bge r2,r4,1002b8c <_malloc_r+0x3b0> + 1002b40: 88800054 ori r2,r17,1 + 1002b44: 8447883a add r3,r16,r17 + 1002b48: 80800115 stw r2,4(r16) + 1002b4c: 20800054 ori r2,r4,1 + 1002b50: 18800115 stw r2,4(r3) + 1002b54: e0c00215 stw r3,8(fp) + 1002b58: 9009883a mov r4,r18 + 1002b5c: 100d1a80 call 100d1a8 <__malloc_unlock> + 1002b60: 80c00204 addi r3,r16,8 + 1002b64: 003f3106 br 100282c <_malloc_r+0x50> + 1002b68: 39c00117 ldw r7,4(r7) + 1002b6c: 573ffe04 addi fp,r10,-8 + 1002b70: 003fa006 br 10029f4 <_malloc_r+0x218> + 1002b74: 00801504 movi r2,84 + 1002b78: 10c06736 bltu r2,r3,1002d18 <_malloc_r+0x53c> + 1002b7c: 8804d33a srli r2,r17,12 + 1002b80: 11801b84 addi r6,r2,110 + 1002b84: 300490fa slli r2,r6,3 + 1002b88: 003f4106 br 1002890 <_malloc_r+0xb4> + 1002b8c: d0a77417 ldw r2,-25136(gp) + 1002b90: d0e00a17 ldw r3,-32728(gp) + 1002b94: 053fffc4 movi r20,-1 + 1002b98: 10800404 addi r2,r2,16 + 1002b9c: 88a7883a add r19,r17,r2 + 1002ba0: 1d000326 beq r3,r20,1002bb0 <_malloc_r+0x3d4> + 1002ba4: 98c3ffc4 addi r3,r19,4095 + 1002ba8: 00bc0004 movi r2,-4096 + 1002bac: 18a6703a and r19,r3,r2 + 1002bb0: 9009883a mov r4,r18 + 1002bb4: 980b883a mov r5,r19 + 1002bb8: 10030e00 call 10030e0 <_sbrk_r> + 1002bbc: 1009883a mov r4,r2 + 1002bc0: 15000426 beq r2,r20,1002bd4 <_malloc_r+0x3f8> + 1002bc4: 854b883a add r5,r16,r21 + 1002bc8: 1029883a mov r20,r2 + 1002bcc: 11405a2e bgeu r2,r5,1002d38 <_malloc_r+0x55c> + 1002bd0: 87000c26 beq r16,fp,1002c04 <_malloc_r+0x428> + 1002bd4: e4000217 ldw r16,8(fp) + 1002bd8: 80c00117 ldw r3,4(r16) + 1002bdc: 00bfff04 movi r2,-4 + 1002be0: 1884703a and r2,r3,r2 + 1002be4: 14400336 bltu r2,r17,1002bf4 <_malloc_r+0x418> + 1002be8: 1449c83a sub r4,r2,r17 + 1002bec: 008003c4 movi r2,15 + 1002bf0: 113fd316 blt r2,r4,1002b40 <_malloc_r+0x364> + 1002bf4: 9009883a mov r4,r18 + 1002bf8: 100d1a80 call 100d1a8 <__malloc_unlock> + 1002bfc: 0007883a mov r3,zero + 1002c00: 003f0a06 br 100282c <_malloc_r+0x50> + 1002c04: 05c040b4 movhi r23,258 + 1002c08: bdcd2b04 addi r23,r23,13484 + 1002c0c: b8800017 ldw r2,0(r23) + 1002c10: 988d883a add r6,r19,r2 + 1002c14: b9800015 stw r6,0(r23) + 1002c18: d0e00a17 ldw r3,-32728(gp) + 1002c1c: 00bfffc4 movi r2,-1 + 1002c20: 18808e26 beq r3,r2,1002e5c <_malloc_r+0x680> + 1002c24: 2145c83a sub r2,r4,r5 + 1002c28: 3085883a add r2,r6,r2 + 1002c2c: b8800015 stw r2,0(r23) + 1002c30: 20c001cc andi r3,r4,7 + 1002c34: 18005f1e bne r3,zero,1002db4 <_malloc_r+0x5d8> + 1002c38: 000b883a mov r5,zero + 1002c3c: a4c5883a add r2,r20,r19 + 1002c40: 1083ffcc andi r2,r2,4095 + 1002c44: 00c40004 movi r3,4096 + 1002c48: 1887c83a sub r3,r3,r2 + 1002c4c: 28e7883a add r19,r5,r3 + 1002c50: 9009883a mov r4,r18 + 1002c54: 980b883a mov r5,r19 + 1002c58: 10030e00 call 10030e0 <_sbrk_r> + 1002c5c: 1007883a mov r3,r2 + 1002c60: 00bfffc4 movi r2,-1 + 1002c64: 18807a26 beq r3,r2,1002e50 <_malloc_r+0x674> + 1002c68: 1d05c83a sub r2,r3,r20 + 1002c6c: 9885883a add r2,r19,r2 + 1002c70: 10c00054 ori r3,r2,1 + 1002c74: b8800017 ldw r2,0(r23) + 1002c78: a021883a mov r16,r20 + 1002c7c: a0c00115 stw r3,4(r20) + 1002c80: 9885883a add r2,r19,r2 + 1002c84: b8800015 stw r2,0(r23) + 1002c88: e5000215 stw r20,8(fp) + 1002c8c: b7003626 beq r22,fp,1002d68 <_malloc_r+0x58c> + 1002c90: 018003c4 movi r6,15 + 1002c94: 35404b36 bltu r6,r21,1002dc4 <_malloc_r+0x5e8> + 1002c98: 00800044 movi r2,1 + 1002c9c: a0800115 stw r2,4(r20) + 1002ca0: 003fcd06 br 1002bd8 <_malloc_r+0x3fc> + 1002ca4: 2808d27a srli r4,r5,9 + 1002ca8: 2000371e bne r4,zero,1002d88 <_malloc_r+0x5ac> + 1002cac: 2808d0fa srli r4,r5,3 + 1002cb0: 200690fa slli r3,r4,3 + 1002cb4: 1ad1883a add r8,r3,r11 + 1002cb8: 41800217 ldw r6,8(r8) + 1002cbc: 41805b26 beq r8,r6,1002e2c <_malloc_r+0x650> + 1002cc0: 30800117 ldw r2,4(r6) + 1002cc4: 00ffff04 movi r3,-4 + 1002cc8: 10c4703a and r2,r2,r3 + 1002ccc: 2880022e bgeu r5,r2,1002cd8 <_malloc_r+0x4fc> + 1002cd0: 31800217 ldw r6,8(r6) + 1002cd4: 41bffa1e bne r8,r6,1002cc0 <_malloc_r+0x4e4> + 1002cd8: 32000317 ldw r8,12(r6) + 1002cdc: 39c00117 ldw r7,4(r7) + 1002ce0: 82000315 stw r8,12(r16) + 1002ce4: 81800215 stw r6,8(r16) + 1002ce8: 070040b4 movhi fp,258 + 1002cec: e7249004 addi fp,fp,-28096 + 1002cf0: 34000315 stw r16,12(r6) + 1002cf4: 44000215 stw r16,8(r8) + 1002cf8: 003f3e06 br 10029f4 <_malloc_r+0x218> + 1002cfc: 63000044 addi r12,r12,1 + 1002d00: 608000cc andi r2,r12,3 + 1002d04: 10005d26 beq r2,zero,1002e7c <_malloc_r+0x6a0> + 1002d08: 18c00204 addi r3,r3,8 + 1002d0c: 003f5106 br 1002a54 <_malloc_r+0x278> + 1002d10: 8089883a add r4,r16,r2 + 1002d14: 003f6d06 br 1002acc <_malloc_r+0x2f0> + 1002d18: 00805504 movi r2,340 + 1002d1c: 10c02036 bltu r2,r3,1002da0 <_malloc_r+0x5c4> + 1002d20: 8804d3fa srli r2,r17,15 + 1002d24: 11801dc4 addi r6,r2,119 + 1002d28: 300490fa slli r2,r6,3 + 1002d2c: 003ed806 br 1002890 <_malloc_r+0xb4> + 1002d30: 48c000c4 addi r3,r9,3 + 1002d34: 003f3106 br 10029fc <_malloc_r+0x220> + 1002d38: 05c040b4 movhi r23,258 + 1002d3c: bdcd2b04 addi r23,r23,13484 + 1002d40: b8800017 ldw r2,0(r23) + 1002d44: 988d883a add r6,r19,r2 + 1002d48: b9800015 stw r6,0(r23) + 1002d4c: 293fb21e bne r5,r4,1002c18 <_malloc_r+0x43c> + 1002d50: 2083ffcc andi r2,r4,4095 + 1002d54: 103fb01e bne r2,zero,1002c18 <_malloc_r+0x43c> + 1002d58: e4000217 ldw r16,8(fp) + 1002d5c: 9d45883a add r2,r19,r21 + 1002d60: 10800054 ori r2,r2,1 + 1002d64: 80800115 stw r2,4(r16) + 1002d68: b8c00017 ldw r3,0(r23) + 1002d6c: d0a77517 ldw r2,-25132(gp) + 1002d70: 10c0012e bgeu r2,r3,1002d78 <_malloc_r+0x59c> + 1002d74: d0e77515 stw r3,-25132(gp) + 1002d78: d0a77617 ldw r2,-25128(gp) + 1002d7c: 10ff962e bgeu r2,r3,1002bd8 <_malloc_r+0x3fc> + 1002d80: d0e77615 stw r3,-25128(gp) + 1002d84: 003f9406 br 1002bd8 <_malloc_r+0x3fc> + 1002d88: 00800104 movi r2,4 + 1002d8c: 11001e36 bltu r2,r4,1002e08 <_malloc_r+0x62c> + 1002d90: 2804d1ba srli r2,r5,6 + 1002d94: 11000e04 addi r4,r2,56 + 1002d98: 200690fa slli r3,r4,3 + 1002d9c: 003fc506 br 1002cb4 <_malloc_r+0x4d8> + 1002da0: 00815504 movi r2,1364 + 1002da4: 10c01d2e bgeu r2,r3,1002e1c <_malloc_r+0x640> + 1002da8: 01801f84 movi r6,126 + 1002dac: 0080fc04 movi r2,1008 + 1002db0: 003eb706 br 1002890 <_malloc_r+0xb4> + 1002db4: 00800204 movi r2,8 + 1002db8: 10cbc83a sub r5,r2,r3 + 1002dbc: 2169883a add r20,r4,r5 + 1002dc0: 003f9e06 br 1002c3c <_malloc_r+0x460> + 1002dc4: 00bffe04 movi r2,-8 + 1002dc8: a93ffd04 addi r4,r21,-12 + 1002dcc: 2088703a and r4,r4,r2 + 1002dd0: b10b883a add r5,r22,r4 + 1002dd4: 00c00144 movi r3,5 + 1002dd8: 28c00215 stw r3,8(r5) + 1002ddc: 28c00115 stw r3,4(r5) + 1002de0: b0800117 ldw r2,4(r22) + 1002de4: 1080004c andi r2,r2,1 + 1002de8: 2084b03a or r2,r4,r2 + 1002dec: b0800115 stw r2,4(r22) + 1002df0: 313fdd2e bgeu r6,r4,1002d68 <_malloc_r+0x58c> + 1002df4: b1400204 addi r5,r22,8 + 1002df8: 9009883a mov r4,r18 + 1002dfc: 10073600 call 1007360 <_free_r> + 1002e00: e4000217 ldw r16,8(fp) + 1002e04: 003fd806 br 1002d68 <_malloc_r+0x58c> + 1002e08: 00800504 movi r2,20 + 1002e0c: 11001536 bltu r2,r4,1002e64 <_malloc_r+0x688> + 1002e10: 210016c4 addi r4,r4,91 + 1002e14: 200690fa slli r3,r4,3 + 1002e18: 003fa606 br 1002cb4 <_malloc_r+0x4d8> + 1002e1c: 8804d4ba srli r2,r17,18 + 1002e20: 11801f04 addi r6,r2,124 + 1002e24: 300490fa slli r2,r6,3 + 1002e28: 003e9906 br 1002890 <_malloc_r+0xb4> + 1002e2c: 2009d0ba srai r4,r4,2 + 1002e30: 014040b4 movhi r5,258 + 1002e34: 29649004 addi r5,r5,-28096 + 1002e38: 00c00044 movi r3,1 + 1002e3c: 28800117 ldw r2,4(r5) + 1002e40: 1906983a sll r3,r3,r4 + 1002e44: 10c4b03a or r2,r2,r3 + 1002e48: 28800115 stw r2,4(r5) + 1002e4c: 003fa306 br 1002cdc <_malloc_r+0x500> + 1002e50: 0027883a mov r19,zero + 1002e54: 00c00044 movi r3,1 + 1002e58: 003f8606 br 1002c74 <_malloc_r+0x498> + 1002e5c: d1200a15 stw r4,-32728(gp) + 1002e60: 003f7306 br 1002c30 <_malloc_r+0x454> + 1002e64: 00801504 movi r2,84 + 1002e68: 11001936 bltu r2,r4,1002ed0 <_malloc_r+0x6f4> + 1002e6c: 2804d33a srli r2,r5,12 + 1002e70: 11001b84 addi r4,r2,110 + 1002e74: 200690fa slli r3,r4,3 + 1002e78: 003f8e06 br 1002cb4 <_malloc_r+0x4d8> + 1002e7c: 480b883a mov r5,r9 + 1002e80: 6807883a mov r3,r13 + 1002e84: 288000cc andi r2,r5,3 + 1002e88: 18fffe04 addi r3,r3,-8 + 1002e8c: 297fffc4 addi r5,r5,-1 + 1002e90: 10001526 beq r2,zero,1002ee8 <_malloc_r+0x70c> + 1002e94: 18800217 ldw r2,8(r3) + 1002e98: 10fffa26 beq r2,r3,1002e84 <_malloc_r+0x6a8> + 1002e9c: 2109883a add r4,r4,r4 + 1002ea0: 393f1e36 bltu r7,r4,1002b1c <_malloc_r+0x340> + 1002ea4: 203f1d26 beq r4,zero,1002b1c <_malloc_r+0x340> + 1002ea8: 21c4703a and r2,r4,r7 + 1002eac: 10000226 beq r2,zero,1002eb8 <_malloc_r+0x6dc> + 1002eb0: 6013883a mov r9,r12 + 1002eb4: 003ee106 br 1002a3c <_malloc_r+0x260> + 1002eb8: 2109883a add r4,r4,r4 + 1002ebc: 3904703a and r2,r7,r4 + 1002ec0: 63000104 addi r12,r12,4 + 1002ec4: 103ffc26 beq r2,zero,1002eb8 <_malloc_r+0x6dc> + 1002ec8: 6013883a mov r9,r12 + 1002ecc: 003edb06 br 1002a3c <_malloc_r+0x260> + 1002ed0: 00805504 movi r2,340 + 1002ed4: 11000836 bltu r2,r4,1002ef8 <_malloc_r+0x71c> + 1002ed8: 2804d3fa srli r2,r5,15 + 1002edc: 11001dc4 addi r4,r2,119 + 1002ee0: 200690fa slli r3,r4,3 + 1002ee4: 003f7306 br 1002cb4 <_malloc_r+0x4d8> + 1002ee8: 0104303a nor r2,zero,r4 + 1002eec: 388e703a and r7,r7,r2 + 1002ef0: e1c00115 stw r7,4(fp) + 1002ef4: 003fe906 br 1002e9c <_malloc_r+0x6c0> + 1002ef8: 00815504 movi r2,1364 + 1002efc: 1100032e bgeu r2,r4,1002f0c <_malloc_r+0x730> + 1002f00: 01001f84 movi r4,126 + 1002f04: 00c0fc04 movi r3,1008 + 1002f08: 003f6a06 br 1002cb4 <_malloc_r+0x4d8> + 1002f0c: 2804d4ba srli r2,r5,18 + 1002f10: 11001f04 addi r4,r2,124 + 1002f14: 200690fa slli r3,r4,3 + 1002f18: 003f6606 br 1002cb4 <_malloc_r+0x4d8> + +01002f1c : + 1002f1c: 008000c4 movi r2,3 + 1002f20: 29403fcc andi r5,r5,255 + 1002f24: 2007883a mov r3,r4 + 1002f28: 1180022e bgeu r2,r6,1002f34 + 1002f2c: 2084703a and r2,r4,r2 + 1002f30: 10000826 beq r2,zero,1002f54 + 1002f34: 30000526 beq r6,zero,1002f4c + 1002f38: 2805883a mov r2,r5 + 1002f3c: 30cd883a add r6,r6,r3 + 1002f40: 18800005 stb r2,0(r3) + 1002f44: 18c00044 addi r3,r3,1 + 1002f48: 19bffd1e bne r3,r6,1002f40 + 1002f4c: 2005883a mov r2,r4 + 1002f50: f800283a ret + 1002f54: 2804923a slli r2,r5,8 + 1002f58: 020003c4 movi r8,15 + 1002f5c: 200f883a mov r7,r4 + 1002f60: 2884b03a or r2,r5,r2 + 1002f64: 1006943a slli r3,r2,16 + 1002f68: 10c6b03a or r3,r2,r3 + 1002f6c: 41800a2e bgeu r8,r6,1002f98 + 1002f70: 4005883a mov r2,r8 + 1002f74: 31bffc04 addi r6,r6,-16 + 1002f78: 38c00015 stw r3,0(r7) + 1002f7c: 38c00115 stw r3,4(r7) + 1002f80: 38c00215 stw r3,8(r7) + 1002f84: 38c00315 stw r3,12(r7) + 1002f88: 39c00404 addi r7,r7,16 + 1002f8c: 11bff936 bltu r2,r6,1002f74 + 1002f90: 008000c4 movi r2,3 + 1002f94: 1180052e bgeu r2,r6,1002fac + 1002f98: 31bfff04 addi r6,r6,-4 + 1002f9c: 008000c4 movi r2,3 + 1002fa0: 38c00015 stw r3,0(r7) + 1002fa4: 39c00104 addi r7,r7,4 + 1002fa8: 11bffb36 bltu r2,r6,1002f98 + 1002fac: 3807883a mov r3,r7 + 1002fb0: 003fe006 br 1002f34 + +01002fb4 : + 1002fb4: defffb04 addi sp,sp,-20 + 1002fb8: dfc00115 stw ra,4(sp) + 1002fbc: d9400215 stw r5,8(sp) + 1002fc0: d9800315 stw r6,12(sp) + 1002fc4: d9c00415 stw r7,16(sp) + 1002fc8: 008040b4 movhi r2,258 + 1002fcc: 10ab9804 addi r2,r2,-20896 + 1002fd0: 10c00017 ldw r3,0(r2) + 1002fd4: 200b883a mov r5,r4 + 1002fd8: d8800204 addi r2,sp,8 + 1002fdc: 19000217 ldw r4,8(r3) + 1002fe0: 100d883a mov r6,r2 + 1002fe4: d8800015 stw r2,0(sp) + 1002fe8: 10054180 call 1005418 <__vfprintf_internal> + 1002fec: dfc00117 ldw ra,4(sp) + 1002ff0: dec00504 addi sp,sp,20 + 1002ff4: f800283a ret + +01002ff8 <_printf_r>: + 1002ff8: defffc04 addi sp,sp,-16 + 1002ffc: dfc00115 stw ra,4(sp) + 1003000: d9800215 stw r6,8(sp) + 1003004: d9c00315 stw r7,12(sp) + 1003008: 280d883a mov r6,r5 + 100300c: 21400217 ldw r5,8(r4) + 1003010: d8c00204 addi r3,sp,8 + 1003014: 180f883a mov r7,r3 + 1003018: d8c00015 stw r3,0(sp) + 100301c: 100356c0 call 100356c <___vfprintf_internal_r> + 1003020: dfc00117 ldw ra,4(sp) + 1003024: dec00404 addi sp,sp,16 + 1003028: f800283a ret + +0100302c <_puts_r>: + 100302c: defff604 addi sp,sp,-40 + 1003030: dc400715 stw r17,28(sp) + 1003034: 2023883a mov r17,r4 + 1003038: 2809883a mov r4,r5 + 100303c: dfc00915 stw ra,36(sp) + 1003040: dcc00815 stw r19,32(sp) + 1003044: 2827883a mov r19,r5 + 1003048: 10034a00 call 10034a0 + 100304c: 89400217 ldw r5,8(r17) + 1003050: 00c040b4 movhi r3,258 + 1003054: 18e36a04 addi r3,r3,-29272 + 1003058: 01c00044 movi r7,1 + 100305c: 12000044 addi r8,r2,1 + 1003060: d8c00515 stw r3,20(sp) + 1003064: d9c00615 stw r7,24(sp) + 1003068: d8c00304 addi r3,sp,12 + 100306c: 01c00084 movi r7,2 + 1003070: 8809883a mov r4,r17 + 1003074: d80d883a mov r6,sp + 1003078: d8c00015 stw r3,0(sp) + 100307c: dcc00315 stw r19,12(sp) + 1003080: da000215 stw r8,8(sp) + 1003084: d9c00115 stw r7,4(sp) + 1003088: d8800415 stw r2,16(sp) + 100308c: 10076740 call 1007674 <__sfvwrite_r> + 1003090: 00ffffc4 movi r3,-1 + 1003094: 10000626 beq r2,zero,10030b0 <_puts_r+0x84> + 1003098: 1805883a mov r2,r3 + 100309c: dfc00917 ldw ra,36(sp) + 10030a0: dcc00817 ldw r19,32(sp) + 10030a4: dc400717 ldw r17,28(sp) + 10030a8: dec00a04 addi sp,sp,40 + 10030ac: f800283a ret + 10030b0: 00c00284 movi r3,10 + 10030b4: 1805883a mov r2,r3 + 10030b8: dfc00917 ldw ra,36(sp) + 10030bc: dcc00817 ldw r19,32(sp) + 10030c0: dc400717 ldw r17,28(sp) + 10030c4: dec00a04 addi sp,sp,40 + 10030c8: f800283a ret + +010030cc : + 10030cc: 008040b4 movhi r2,258 + 10030d0: 10ab9804 addi r2,r2,-20896 + 10030d4: 200b883a mov r5,r4 + 10030d8: 11000017 ldw r4,0(r2) + 10030dc: 100302c1 jmpi 100302c <_puts_r> + +010030e0 <_sbrk_r>: + 10030e0: defffd04 addi sp,sp,-12 + 10030e4: dc000015 stw r16,0(sp) + 10030e8: 040040b4 movhi r16,258 + 10030ec: 84330404 addi r16,r16,-13296 + 10030f0: dc400115 stw r17,4(sp) + 10030f4: 80000015 stw zero,0(r16) + 10030f8: 2023883a mov r17,r4 + 10030fc: 2809883a mov r4,r5 + 1003100: dfc00215 stw ra,8(sp) + 1003104: 100cd5c0 call 100cd5c + 1003108: 1007883a mov r3,r2 + 100310c: 00bfffc4 movi r2,-1 + 1003110: 18800626 beq r3,r2,100312c <_sbrk_r+0x4c> + 1003114: 1805883a mov r2,r3 + 1003118: dfc00217 ldw ra,8(sp) + 100311c: dc400117 ldw r17,4(sp) + 1003120: dc000017 ldw r16,0(sp) + 1003124: dec00304 addi sp,sp,12 + 1003128: f800283a ret + 100312c: 80800017 ldw r2,0(r16) + 1003130: 103ff826 beq r2,zero,1003114 <_sbrk_r+0x34> + 1003134: 88800015 stw r2,0(r17) + 1003138: 1805883a mov r2,r3 + 100313c: dfc00217 ldw ra,8(sp) + 1003140: dc400117 ldw r17,4(sp) + 1003144: dc000017 ldw r16,0(sp) + 1003148: dec00304 addi sp,sp,12 + 100314c: f800283a ret + +01003150 <_raise_r>: + 1003150: defffd04 addi sp,sp,-12 + 1003154: 008007c4 movi r2,31 + 1003158: dc400115 stw r17,4(sp) + 100315c: dc000015 stw r16,0(sp) + 1003160: dfc00215 stw ra,8(sp) + 1003164: 2821883a mov r16,r5 + 1003168: 2023883a mov r17,r4 + 100316c: 11402736 bltu r2,r5,100320c <_raise_r+0xbc> + 1003170: 20c0b717 ldw r3,732(r4) + 1003174: 18001326 beq r3,zero,10031c4 <_raise_r+0x74> + 1003178: 2945883a add r2,r5,r5 + 100317c: 1085883a add r2,r2,r2 + 1003180: 188b883a add r5,r3,r2 + 1003184: 28c00017 ldw r3,0(r5) + 1003188: 18000e26 beq r3,zero,10031c4 <_raise_r+0x74> + 100318c: 01000044 movi r4,1 + 1003190: 19000526 beq r3,r4,10031a8 <_raise_r+0x58> + 1003194: 00bfffc4 movi r2,-1 + 1003198: 18801326 beq r3,r2,10031e8 <_raise_r+0x98> + 100319c: 28000015 stw zero,0(r5) + 10031a0: 8009883a mov r4,r16 + 10031a4: 183ee83a callr r3 + 10031a8: 0007883a mov r3,zero + 10031ac: 1805883a mov r2,r3 + 10031b0: dfc00217 ldw ra,8(sp) + 10031b4: dc400117 ldw r17,4(sp) + 10031b8: dc000017 ldw r16,0(sp) + 10031bc: dec00304 addi sp,sp,12 + 10031c0: f800283a ret + 10031c4: 10034280 call 1003428 <_getpid_r> + 10031c8: 100b883a mov r5,r2 + 10031cc: 8809883a mov r4,r17 + 10031d0: 800d883a mov r6,r16 + 10031d4: dfc00217 ldw ra,8(sp) + 10031d8: dc400117 ldw r17,4(sp) + 10031dc: dc000017 ldw r16,0(sp) + 10031e0: dec00304 addi sp,sp,12 + 10031e4: 100342c1 jmpi 100342c <_kill_r> + 10031e8: 2007883a mov r3,r4 + 10031ec: 00800584 movi r2,22 + 10031f0: 88800015 stw r2,0(r17) + 10031f4: 1805883a mov r2,r3 + 10031f8: dfc00217 ldw ra,8(sp) + 10031fc: dc400117 ldw r17,4(sp) + 1003200: dc000017 ldw r16,0(sp) + 1003204: dec00304 addi sp,sp,12 + 1003208: f800283a ret + 100320c: 00800584 movi r2,22 + 1003210: 00ffffc4 movi r3,-1 + 1003214: 20800015 stw r2,0(r4) + 1003218: 003fe406 br 10031ac <_raise_r+0x5c> + +0100321c : + 100321c: 008040b4 movhi r2,258 + 1003220: 10ab9804 addi r2,r2,-20896 + 1003224: 200b883a mov r5,r4 + 1003228: 11000017 ldw r4,0(r2) + 100322c: 10031501 jmpi 1003150 <_raise_r> + +01003230 <_init_signal_r>: + 1003230: 2080b717 ldw r2,732(r4) + 1003234: defffe04 addi sp,sp,-8 + 1003238: dc000015 stw r16,0(sp) + 100323c: dfc00115 stw ra,4(sp) + 1003240: 2021883a mov r16,r4 + 1003244: 10000526 beq r2,zero,100325c <_init_signal_r+0x2c> + 1003248: 0005883a mov r2,zero + 100324c: dfc00117 ldw ra,4(sp) + 1003250: dc000017 ldw r16,0(sp) + 1003254: dec00204 addi sp,sp,8 + 1003258: f800283a ret + 100325c: 01402004 movi r5,128 + 1003260: 10027dc0 call 10027dc <_malloc_r> + 1003264: 1009883a mov r4,r2 + 1003268: 8080b715 stw r2,732(r16) + 100326c: 10000726 beq r2,zero,100328c <_init_signal_r+0x5c> + 1003270: 0007883a mov r3,zero + 1003274: 01402004 movi r5,128 + 1003278: 20c5883a add r2,r4,r3 + 100327c: 18c00104 addi r3,r3,4 + 1003280: 10000015 stw zero,0(r2) + 1003284: 197ffc1e bne r3,r5,1003278 <_init_signal_r+0x48> + 1003288: 003fef06 br 1003248 <_init_signal_r+0x18> + 100328c: 00bfffc4 movi r2,-1 + 1003290: 003fee06 br 100324c <_init_signal_r+0x1c> + +01003294 <_init_signal>: + 1003294: 008040b4 movhi r2,258 + 1003298: 10ab9804 addi r2,r2,-20896 + 100329c: 11000017 ldw r4,0(r2) + 10032a0: 10032301 jmpi 1003230 <_init_signal_r> + +010032a4 <__sigtramp_r>: + 10032a4: defffd04 addi sp,sp,-12 + 10032a8: 008007c4 movi r2,31 + 10032ac: dc000115 stw r16,4(sp) + 10032b0: dfc00215 stw ra,8(sp) + 10032b4: 2021883a mov r16,r4 + 10032b8: 11401336 bltu r2,r5,1003308 <__sigtramp_r+0x64> + 10032bc: 20c0b717 ldw r3,732(r4) + 10032c0: 18001f26 beq r3,zero,1003340 <__sigtramp_r+0x9c> + 10032c4: 2945883a add r2,r5,r5 + 10032c8: 1085883a add r2,r2,r2 + 10032cc: 10c9883a add r4,r2,r3 + 10032d0: 20c00017 ldw r3,0(r4) + 10032d4: 18001626 beq r3,zero,1003330 <__sigtramp_r+0x8c> + 10032d8: 00bfffc4 movi r2,-1 + 10032dc: 18801626 beq r3,r2,1003338 <__sigtramp_r+0x94> + 10032e0: 00800044 movi r2,1 + 10032e4: 18800d26 beq r3,r2,100331c <__sigtramp_r+0x78> + 10032e8: 20000015 stw zero,0(r4) + 10032ec: 2809883a mov r4,r5 + 10032f0: 183ee83a callr r3 + 10032f4: 0005883a mov r2,zero + 10032f8: dfc00217 ldw ra,8(sp) + 10032fc: dc000117 ldw r16,4(sp) + 1003300: dec00304 addi sp,sp,12 + 1003304: f800283a ret + 1003308: 00bfffc4 movi r2,-1 + 100330c: dfc00217 ldw ra,8(sp) + 1003310: dc000117 ldw r16,4(sp) + 1003314: dec00304 addi sp,sp,12 + 1003318: f800283a ret + 100331c: 008000c4 movi r2,3 + 1003320: dfc00217 ldw ra,8(sp) + 1003324: dc000117 ldw r16,4(sp) + 1003328: dec00304 addi sp,sp,12 + 100332c: f800283a ret + 1003330: 00800044 movi r2,1 + 1003334: 003ff006 br 10032f8 <__sigtramp_r+0x54> + 1003338: 00800084 movi r2,2 + 100333c: 003fee06 br 10032f8 <__sigtramp_r+0x54> + 1003340: d9400015 stw r5,0(sp) + 1003344: 10032300 call 1003230 <_init_signal_r> + 1003348: d9400017 ldw r5,0(sp) + 100334c: 103fee1e bne r2,zero,1003308 <__sigtramp_r+0x64> + 1003350: 80c0b717 ldw r3,732(r16) + 1003354: 003fdb06 br 10032c4 <__sigtramp_r+0x20> + +01003358 <__sigtramp>: + 1003358: 008040b4 movhi r2,258 + 100335c: 10ab9804 addi r2,r2,-20896 + 1003360: 200b883a mov r5,r4 + 1003364: 11000017 ldw r4,0(r2) + 1003368: 10032a41 jmpi 10032a4 <__sigtramp_r> + +0100336c <_signal_r>: + 100336c: defffc04 addi sp,sp,-16 + 1003370: 008007c4 movi r2,31 + 1003374: dc800215 stw r18,8(sp) + 1003378: dc400115 stw r17,4(sp) + 100337c: dc000015 stw r16,0(sp) + 1003380: dfc00315 stw ra,12(sp) + 1003384: 2823883a mov r17,r5 + 1003388: 00ffffc4 movi r3,-1 + 100338c: 3025883a mov r18,r6 + 1003390: 2021883a mov r16,r4 + 1003394: 1140092e bgeu r2,r5,10033bc <_signal_r+0x50> + 1003398: 00800584 movi r2,22 + 100339c: 20800015 stw r2,0(r4) + 10033a0: 1805883a mov r2,r3 + 10033a4: dfc00317 ldw ra,12(sp) + 10033a8: dc800217 ldw r18,8(sp) + 10033ac: dc400117 ldw r17,4(sp) + 10033b0: dc000017 ldw r16,0(sp) + 10033b4: dec00404 addi sp,sp,16 + 10033b8: f800283a ret + 10033bc: 2140b717 ldw r5,732(r4) + 10033c0: 28000c26 beq r5,zero,10033f4 <_signal_r+0x88> + 10033c4: 8c45883a add r2,r17,r17 + 10033c8: 1085883a add r2,r2,r2 + 10033cc: 1145883a add r2,r2,r5 + 10033d0: 10c00017 ldw r3,0(r2) + 10033d4: 14800015 stw r18,0(r2) + 10033d8: 1805883a mov r2,r3 + 10033dc: dfc00317 ldw ra,12(sp) + 10033e0: dc800217 ldw r18,8(sp) + 10033e4: dc400117 ldw r17,4(sp) + 10033e8: dc000017 ldw r16,0(sp) + 10033ec: dec00404 addi sp,sp,16 + 10033f0: f800283a ret + 10033f4: 10032300 call 1003230 <_init_signal_r> + 10033f8: 1000021e bne r2,zero,1003404 <_signal_r+0x98> + 10033fc: 8140b717 ldw r5,732(r16) + 1003400: 003ff006 br 10033c4 <_signal_r+0x58> + 1003404: 00ffffc4 movi r3,-1 + 1003408: 003fe506 br 10033a0 <_signal_r+0x34> + +0100340c : + 100340c: 018040b4 movhi r6,258 + 1003410: 31ab9804 addi r6,r6,-20896 + 1003414: 2007883a mov r3,r4 + 1003418: 31000017 ldw r4,0(r6) + 100341c: 280d883a mov r6,r5 + 1003420: 180b883a mov r5,r3 + 1003424: 100336c1 jmpi 100336c <_signal_r> + +01003428 <_getpid_r>: + 1003428: 100c5981 jmpi 100c598 + +0100342c <_kill_r>: + 100342c: defffd04 addi sp,sp,-12 + 1003430: dc000015 stw r16,0(sp) + 1003434: 040040b4 movhi r16,258 + 1003438: 84330404 addi r16,r16,-13296 + 100343c: dc400115 stw r17,4(sp) + 1003440: 80000015 stw zero,0(r16) + 1003444: 2023883a mov r17,r4 + 1003448: 2809883a mov r4,r5 + 100344c: 300b883a mov r5,r6 + 1003450: dfc00215 stw ra,8(sp) + 1003454: 100c6d80 call 100c6d8 + 1003458: 1007883a mov r3,r2 + 100345c: 00bfffc4 movi r2,-1 + 1003460: 18800626 beq r3,r2,100347c <_kill_r+0x50> + 1003464: 1805883a mov r2,r3 + 1003468: dfc00217 ldw ra,8(sp) + 100346c: dc400117 ldw r17,4(sp) + 1003470: dc000017 ldw r16,0(sp) + 1003474: dec00304 addi sp,sp,12 + 1003478: f800283a ret + 100347c: 80800017 ldw r2,0(r16) + 1003480: 103ff826 beq r2,zero,1003464 <_kill_r+0x38> + 1003484: 88800015 stw r2,0(r17) + 1003488: 1805883a mov r2,r3 + 100348c: dfc00217 ldw ra,8(sp) + 1003490: dc400117 ldw r17,4(sp) + 1003494: dc000017 ldw r16,0(sp) + 1003498: dec00304 addi sp,sp,12 + 100349c: f800283a ret + +010034a0 : + 10034a0: 208000cc andi r2,r4,3 + 10034a4: 2011883a mov r8,r4 + 10034a8: 1000161e bne r2,zero,1003504 + 10034ac: 20c00017 ldw r3,0(r4) + 10034b0: 017fbff4 movhi r5,65279 + 10034b4: 297fbfc4 addi r5,r5,-257 + 10034b8: 01e02074 movhi r7,32897 + 10034bc: 39e02004 addi r7,r7,-32640 + 10034c0: 1945883a add r2,r3,r5 + 10034c4: 11c4703a and r2,r2,r7 + 10034c8: 00c6303a nor r3,zero,r3 + 10034cc: 1886703a and r3,r3,r2 + 10034d0: 18000c1e bne r3,zero,1003504 + 10034d4: 280d883a mov r6,r5 + 10034d8: 380b883a mov r5,r7 + 10034dc: 21000104 addi r4,r4,4 + 10034e0: 20800017 ldw r2,0(r4) + 10034e4: 1187883a add r3,r2,r6 + 10034e8: 1946703a and r3,r3,r5 + 10034ec: 0084303a nor r2,zero,r2 + 10034f0: 10c4703a and r2,r2,r3 + 10034f4: 103ff926 beq r2,zero,10034dc + 10034f8: 20800007 ldb r2,0(r4) + 10034fc: 10000326 beq r2,zero,100350c + 1003500: 21000044 addi r4,r4,1 + 1003504: 20800007 ldb r2,0(r4) + 1003508: 103ffd1e bne r2,zero,1003500 + 100350c: 2205c83a sub r2,r4,r8 + 1003510: f800283a ret + +01003514 <__sprint_r>: + 1003514: 30800217 ldw r2,8(r6) + 1003518: defffe04 addi sp,sp,-8 + 100351c: dc000015 stw r16,0(sp) + 1003520: dfc00115 stw ra,4(sp) + 1003524: 3021883a mov r16,r6 + 1003528: 0007883a mov r3,zero + 100352c: 1000061e bne r2,zero,1003548 <__sprint_r+0x34> + 1003530: 1805883a mov r2,r3 + 1003534: 30000115 stw zero,4(r6) + 1003538: dfc00117 ldw ra,4(sp) + 100353c: dc000017 ldw r16,0(sp) + 1003540: dec00204 addi sp,sp,8 + 1003544: f800283a ret + 1003548: 10076740 call 1007674 <__sfvwrite_r> + 100354c: 1007883a mov r3,r2 + 1003550: 1805883a mov r2,r3 + 1003554: 80000115 stw zero,4(r16) + 1003558: 80000215 stw zero,8(r16) + 100355c: dfc00117 ldw ra,4(sp) + 1003560: dc000017 ldw r16,0(sp) + 1003564: dec00204 addi sp,sp,8 + 1003568: f800283a ret + +0100356c <___vfprintf_internal_r>: + 100356c: defea404 addi sp,sp,-1392 + 1003570: dd815815 stw r22,1376(sp) + 1003574: dc015215 stw r16,1352(sp) + 1003578: d9c15115 stw r7,1348(sp) + 100357c: dfc15b15 stw ra,1388(sp) + 1003580: df015a15 stw fp,1384(sp) + 1003584: ddc15915 stw r23,1380(sp) + 1003588: dd415715 stw r21,1372(sp) + 100358c: dd015615 stw r20,1368(sp) + 1003590: dcc15515 stw r19,1364(sp) + 1003594: dc815415 stw r18,1360(sp) + 1003598: dc415315 stw r17,1356(sp) + 100359c: 282d883a mov r22,r5 + 10035a0: 3021883a mov r16,r6 + 10035a4: d9014f15 stw r4,1340(sp) + 10035a8: 1007c980 call 1007c98 <_localeconv_r> + 10035ac: 10800017 ldw r2,0(r2) + 10035b0: d9c15117 ldw r7,1348(sp) + 10035b4: d8814915 stw r2,1316(sp) + 10035b8: d8814f17 ldw r2,1340(sp) + 10035bc: 10000226 beq r2,zero,10035c8 <___vfprintf_internal_r+0x5c> + 10035c0: 10800e17 ldw r2,56(r2) + 10035c4: 10020d26 beq r2,zero,1003dfc <___vfprintf_internal_r+0x890> + 10035c8: b080030b ldhu r2,12(r22) + 10035cc: 1080020c andi r2,r2,8 + 10035d0: 10020e26 beq r2,zero,1003e0c <___vfprintf_internal_r+0x8a0> + 10035d4: b0800417 ldw r2,16(r22) + 10035d8: 10020c26 beq r2,zero,1003e0c <___vfprintf_internal_r+0x8a0> + 10035dc: b200030b ldhu r8,12(r22) + 10035e0: 00800284 movi r2,10 + 10035e4: 40c0068c andi r3,r8,26 + 10035e8: 18802f1e bne r3,r2,10036a8 <___vfprintf_internal_r+0x13c> + 10035ec: b080038f ldh r2,14(r22) + 10035f0: 10002d16 blt r2,zero,10036a8 <___vfprintf_internal_r+0x13c> + 10035f4: b240038b ldhu r9,14(r22) + 10035f8: b2800717 ldw r10,28(r22) + 10035fc: b2c00917 ldw r11,36(r22) + 1003600: d9014f17 ldw r4,1340(sp) + 1003604: dc402904 addi r17,sp,164 + 1003608: d8804004 addi r2,sp,256 + 100360c: 00c10004 movi r3,1024 + 1003610: 423fff4c andi r8,r8,65533 + 1003614: 800d883a mov r6,r16 + 1003618: 880b883a mov r5,r17 + 100361c: da002c0d sth r8,176(sp) + 1003620: da402c8d sth r9,178(sp) + 1003624: da803015 stw r10,192(sp) + 1003628: dac03215 stw r11,200(sp) + 100362c: d8802d15 stw r2,180(sp) + 1003630: d8c02e15 stw r3,184(sp) + 1003634: d8802915 stw r2,164(sp) + 1003638: d8c02b15 stw r3,172(sp) + 100363c: d8002f15 stw zero,188(sp) + 1003640: 100356c0 call 100356c <___vfprintf_internal_r> + 1003644: d8814b15 stw r2,1324(sp) + 1003648: 10000416 blt r2,zero,100365c <___vfprintf_internal_r+0xf0> + 100364c: d9014f17 ldw r4,1340(sp) + 1003650: 880b883a mov r5,r17 + 1003654: 1006d440 call 1006d44 <_fflush_r> + 1003658: 1002321e bne r2,zero,1003f24 <___vfprintf_internal_r+0x9b8> + 100365c: d8802c0b ldhu r2,176(sp) + 1003660: 1080100c andi r2,r2,64 + 1003664: 10000326 beq r2,zero,1003674 <___vfprintf_internal_r+0x108> + 1003668: b080030b ldhu r2,12(r22) + 100366c: 10801014 ori r2,r2,64 + 1003670: b080030d sth r2,12(r22) + 1003674: d8814b17 ldw r2,1324(sp) + 1003678: dfc15b17 ldw ra,1388(sp) + 100367c: df015a17 ldw fp,1384(sp) + 1003680: ddc15917 ldw r23,1380(sp) + 1003684: dd815817 ldw r22,1376(sp) + 1003688: dd415717 ldw r21,1372(sp) + 100368c: dd015617 ldw r20,1368(sp) + 1003690: dcc15517 ldw r19,1364(sp) + 1003694: dc815417 ldw r18,1360(sp) + 1003698: dc415317 ldw r17,1356(sp) + 100369c: dc015217 ldw r16,1352(sp) + 10036a0: dec15c04 addi sp,sp,1392 + 10036a4: f800283a ret + 10036a8: 0005883a mov r2,zero + 10036ac: 0007883a mov r3,zero + 10036b0: dd401904 addi r21,sp,100 + 10036b4: d8814215 stw r2,1288(sp) + 10036b8: 802f883a mov r23,r16 + 10036bc: d8c14315 stw r3,1292(sp) + 10036c0: d8014b15 stw zero,1324(sp) + 10036c4: d8014815 stw zero,1312(sp) + 10036c8: d8014415 stw zero,1296(sp) + 10036cc: d8014715 stw zero,1308(sp) + 10036d0: dd400c15 stw r21,48(sp) + 10036d4: d8000e15 stw zero,56(sp) + 10036d8: d8000d15 stw zero,52(sp) + 10036dc: b8800007 ldb r2,0(r23) + 10036e0: 10001926 beq r2,zero,1003748 <___vfprintf_internal_r+0x1dc> + 10036e4: 00c00944 movi r3,37 + 10036e8: 10c01726 beq r2,r3,1003748 <___vfprintf_internal_r+0x1dc> + 10036ec: b821883a mov r16,r23 + 10036f0: 00000106 br 10036f8 <___vfprintf_internal_r+0x18c> + 10036f4: 10c00326 beq r2,r3,1003704 <___vfprintf_internal_r+0x198> + 10036f8: 84000044 addi r16,r16,1 + 10036fc: 80800007 ldb r2,0(r16) + 1003700: 103ffc1e bne r2,zero,10036f4 <___vfprintf_internal_r+0x188> + 1003704: 85e7c83a sub r19,r16,r23 + 1003708: 98000e26 beq r19,zero,1003744 <___vfprintf_internal_r+0x1d8> + 100370c: dc800e17 ldw r18,56(sp) + 1003710: dc400d17 ldw r17,52(sp) + 1003714: 008001c4 movi r2,7 + 1003718: 94e5883a add r18,r18,r19 + 100371c: 8c400044 addi r17,r17,1 + 1003720: adc00015 stw r23,0(r21) + 1003724: dc800e15 stw r18,56(sp) + 1003728: acc00115 stw r19,4(r21) + 100372c: dc400d15 stw r17,52(sp) + 1003730: 14428b16 blt r2,r17,1004160 <___vfprintf_internal_r+0xbf4> + 1003734: ad400204 addi r21,r21,8 + 1003738: d9014b17 ldw r4,1324(sp) + 100373c: 24c9883a add r4,r4,r19 + 1003740: d9014b15 stw r4,1324(sp) + 1003744: 802f883a mov r23,r16 + 1003748: b8800007 ldb r2,0(r23) + 100374c: 10013c26 beq r2,zero,1003c40 <___vfprintf_internal_r+0x6d4> + 1003750: bdc00044 addi r23,r23,1 + 1003754: d8000405 stb zero,16(sp) + 1003758: b8c00007 ldb r3,0(r23) + 100375c: 04ffffc4 movi r19,-1 + 1003760: d8014c15 stw zero,1328(sp) + 1003764: d8014a15 stw zero,1320(sp) + 1003768: d8c14d15 stw r3,1332(sp) + 100376c: bdc00044 addi r23,r23,1 + 1003770: d9414d17 ldw r5,1332(sp) + 1003774: 00801604 movi r2,88 + 1003778: 28fff804 addi r3,r5,-32 + 100377c: 10c06036 bltu r2,r3,1003900 <___vfprintf_internal_r+0x394> + 1003780: 18c5883a add r2,r3,r3 + 1003784: 1085883a add r2,r2,r2 + 1003788: 00c04034 movhi r3,256 + 100378c: 18cde704 addi r3,r3,14236 + 1003790: 10c5883a add r2,r2,r3 + 1003794: 11000017 ldw r4,0(r2) + 1003798: 2000683a jmp r4 + 100379c: 01004710 cmplti r4,zero,284 + 10037a0: 01003900 call 100390 + 10037a4: 01003900 call 100390 + 10037a8: 010046fc xorhi r4,zero,283 + 10037ac: 01003900 call 100390 + 10037b0: 01003900 call 100390 + 10037b4: 01003900 call 100390 + 10037b8: 01003900 call 100390 + 10037bc: 01003900 call 100390 + 10037c0: 01003900 call 100390 + 10037c4: 010044dc xori r4,zero,275 + 10037c8: 010046ec andhi r4,zero,283 + 10037cc: 01003900 call 100390 + 10037d0: 010044f4 movhi r4,275 + 10037d4: 01004788 cmpgei r4,zero,286 + 10037d8: 01003900 call 100390 + 10037dc: 01004774 movhi r4,285 + 10037e0: 0100473c xorhi r4,zero,284 + 10037e4: 0100473c xorhi r4,zero,284 + 10037e8: 0100473c xorhi r4,zero,284 + 10037ec: 0100473c xorhi r4,zero,284 + 10037f0: 0100473c xorhi r4,zero,284 + 10037f4: 0100473c xorhi r4,zero,284 + 10037f8: 0100473c xorhi r4,zero,284 + 10037fc: 0100473c xorhi r4,zero,284 + 1003800: 0100473c xorhi r4,zero,284 + 1003804: 01003900 call 100390 + 1003808: 01003900 call 100390 + 100380c: 01003900 call 100390 + 1003810: 01003900 call 100390 + 1003814: 01003900 call 100390 + 1003818: 01003900 call 100390 + 100381c: 01003900 call 100390 + 1003820: 01003900 call 100390 + 1003824: 01003900 call 100390 + 1003828: 01003900 call 100390 + 100382c: 01003f58 cmpnei r4,zero,253 + 1003830: 010045c4 movi r4,279 + 1003834: 01003900 call 100390 + 1003838: 010045c4 movi r4,279 + 100383c: 01003900 call 100390 + 1003840: 01003900 call 100390 + 1003844: 01003900 call 100390 + 1003848: 01003900 call 100390 + 100384c: 01004728 cmpgeui r4,zero,284 + 1003850: 01003900 call 100390 + 1003854: 01003900 call 100390 + 1003858: 0100400c andi r4,zero,256 + 100385c: 01003900 call 100390 + 1003860: 01003900 call 100390 + 1003864: 01003900 call 100390 + 1003868: 01003900 call 100390 + 100386c: 01003900 call 100390 + 1003870: 01004058 cmpnei r4,zero,257 + 1003874: 01003900 call 100390 + 1003878: 01003900 call 100390 + 100387c: 01004678 rdprs r4,zero,281 + 1003880: 01003900 call 100390 + 1003884: 01003900 call 100390 + 1003888: 01003900 call 100390 + 100388c: 01003900 call 100390 + 1003890: 01003900 call 100390 + 1003894: 01003900 call 100390 + 1003898: 01003900 call 100390 + 100389c: 01003900 call 100390 + 10038a0: 01003900 call 100390 + 10038a4: 01003900 call 100390 + 10038a8: 0100464c andi r4,zero,281 + 10038ac: 01003f64 muli r4,zero,253 + 10038b0: 010045c4 movi r4,279 + 10038b4: 010045c4 movi r4,279 + 10038b8: 010045c4 movi r4,279 + 10038bc: 010045b0 cmpltui r4,zero,278 + 10038c0: 01003f64 muli r4,zero,253 + 10038c4: 01003900 call 100390 + 10038c8: 01003900 call 100390 + 10038cc: 01004538 rdprs r4,zero,276 + 10038d0: 01003900 call 100390 + 10038d4: 01004508 cmpgei r4,zero,276 + 10038d8: 01004018 cmpnei r4,zero,256 + 10038dc: 01004568 cmpgeui r4,zero,277 + 10038e0: 01004554 movui r4,277 + 10038e4: 01003900 call 100390 + 10038e8: 010047e4 muli r4,zero,287 + 10038ec: 01003900 call 100390 + 10038f0: 01004064 muli r4,zero,257 + 10038f4: 01003900 call 100390 + 10038f8: 01003900 call 100390 + 10038fc: 010046dc xori r4,zero,283 + 1003900: d9014d17 ldw r4,1332(sp) + 1003904: 2000ce26 beq r4,zero,1003c40 <___vfprintf_internal_r+0x6d4> + 1003908: 01400044 movi r5,1 + 100390c: d9800f04 addi r6,sp,60 + 1003910: d9c14015 stw r7,1280(sp) + 1003914: d9414515 stw r5,1300(sp) + 1003918: d9814115 stw r6,1284(sp) + 100391c: 280f883a mov r7,r5 + 1003920: d9000f05 stb r4,60(sp) + 1003924: d8000405 stb zero,16(sp) + 1003928: d8014615 stw zero,1304(sp) + 100392c: d8c14c17 ldw r3,1328(sp) + 1003930: 1880008c andi r2,r3,2 + 1003934: 1005003a cmpeq r2,r2,zero + 1003938: d8815015 stw r2,1344(sp) + 100393c: 1000031e bne r2,zero,100394c <___vfprintf_internal_r+0x3e0> + 1003940: d9014517 ldw r4,1300(sp) + 1003944: 21000084 addi r4,r4,2 + 1003948: d9014515 stw r4,1300(sp) + 100394c: d9414c17 ldw r5,1328(sp) + 1003950: 2940210c andi r5,r5,132 + 1003954: d9414e15 stw r5,1336(sp) + 1003958: 28002d1e bne r5,zero,1003a10 <___vfprintf_internal_r+0x4a4> + 100395c: d9814a17 ldw r6,1320(sp) + 1003960: d8814517 ldw r2,1300(sp) + 1003964: 30a1c83a sub r16,r6,r2 + 1003968: 0400290e bge zero,r16,1003a10 <___vfprintf_internal_r+0x4a4> + 100396c: 00800404 movi r2,16 + 1003970: 1404580e bge r2,r16,1004ad4 <___vfprintf_internal_r+0x1568> + 1003974: dc800e17 ldw r18,56(sp) + 1003978: dc400d17 ldw r17,52(sp) + 100397c: 1027883a mov r19,r2 + 1003980: 070040b4 movhi fp,258 + 1003984: e7238684 addi fp,fp,-29158 + 1003988: 050001c4 movi r20,7 + 100398c: 00000306 br 100399c <___vfprintf_internal_r+0x430> + 1003990: 843ffc04 addi r16,r16,-16 + 1003994: ad400204 addi r21,r21,8 + 1003998: 9c00130e bge r19,r16,10039e8 <___vfprintf_internal_r+0x47c> + 100399c: 94800404 addi r18,r18,16 + 10039a0: 8c400044 addi r17,r17,1 + 10039a4: af000015 stw fp,0(r21) + 10039a8: acc00115 stw r19,4(r21) + 10039ac: dc800e15 stw r18,56(sp) + 10039b0: dc400d15 stw r17,52(sp) + 10039b4: a47ff60e bge r20,r17,1003990 <___vfprintf_internal_r+0x424> + 10039b8: d9014f17 ldw r4,1340(sp) + 10039bc: b00b883a mov r5,r22 + 10039c0: d9800c04 addi r6,sp,48 + 10039c4: d9c15115 stw r7,1348(sp) + 10039c8: 10035140 call 1003514 <__sprint_r> + 10039cc: d9c15117 ldw r7,1348(sp) + 10039d0: 10009e1e bne r2,zero,1003c4c <___vfprintf_internal_r+0x6e0> + 10039d4: 843ffc04 addi r16,r16,-16 + 10039d8: dc800e17 ldw r18,56(sp) + 10039dc: dc400d17 ldw r17,52(sp) + 10039e0: dd401904 addi r21,sp,100 + 10039e4: 9c3fed16 blt r19,r16,100399c <___vfprintf_internal_r+0x430> + 10039e8: 9425883a add r18,r18,r16 + 10039ec: 8c400044 addi r17,r17,1 + 10039f0: 008001c4 movi r2,7 + 10039f4: af000015 stw fp,0(r21) + 10039f8: ac000115 stw r16,4(r21) + 10039fc: dc800e15 stw r18,56(sp) + 1003a00: dc400d15 stw r17,52(sp) + 1003a04: 1441f516 blt r2,r17,10041dc <___vfprintf_internal_r+0xc70> + 1003a08: ad400204 addi r21,r21,8 + 1003a0c: 00000206 br 1003a18 <___vfprintf_internal_r+0x4ac> + 1003a10: dc800e17 ldw r18,56(sp) + 1003a14: dc400d17 ldw r17,52(sp) + 1003a18: d8800407 ldb r2,16(sp) + 1003a1c: 10000b26 beq r2,zero,1003a4c <___vfprintf_internal_r+0x4e0> + 1003a20: 00800044 movi r2,1 + 1003a24: 94800044 addi r18,r18,1 + 1003a28: 8c400044 addi r17,r17,1 + 1003a2c: a8800115 stw r2,4(r21) + 1003a30: d8c00404 addi r3,sp,16 + 1003a34: 008001c4 movi r2,7 + 1003a38: a8c00015 stw r3,0(r21) + 1003a3c: dc800e15 stw r18,56(sp) + 1003a40: dc400d15 stw r17,52(sp) + 1003a44: 1441da16 blt r2,r17,10041b0 <___vfprintf_internal_r+0xc44> + 1003a48: ad400204 addi r21,r21,8 + 1003a4c: d9015017 ldw r4,1344(sp) + 1003a50: 20000b1e bne r4,zero,1003a80 <___vfprintf_internal_r+0x514> + 1003a54: d8800444 addi r2,sp,17 + 1003a58: 94800084 addi r18,r18,2 + 1003a5c: 8c400044 addi r17,r17,1 + 1003a60: a8800015 stw r2,0(r21) + 1003a64: 00c00084 movi r3,2 + 1003a68: 008001c4 movi r2,7 + 1003a6c: a8c00115 stw r3,4(r21) + 1003a70: dc800e15 stw r18,56(sp) + 1003a74: dc400d15 stw r17,52(sp) + 1003a78: 1441c216 blt r2,r17,1004184 <___vfprintf_internal_r+0xc18> + 1003a7c: ad400204 addi r21,r21,8 + 1003a80: d9414e17 ldw r5,1336(sp) + 1003a84: 00802004 movi r2,128 + 1003a88: 2880b126 beq r5,r2,1003d50 <___vfprintf_internal_r+0x7e4> + 1003a8c: d8c14617 ldw r3,1304(sp) + 1003a90: 19e1c83a sub r16,r3,r7 + 1003a94: 0400260e bge zero,r16,1003b30 <___vfprintf_internal_r+0x5c4> + 1003a98: 00800404 movi r2,16 + 1003a9c: 1403c90e bge r2,r16,10049c4 <___vfprintf_internal_r+0x1458> + 1003aa0: 1027883a mov r19,r2 + 1003aa4: 070040b4 movhi fp,258 + 1003aa8: e7238284 addi fp,fp,-29174 + 1003aac: 050001c4 movi r20,7 + 1003ab0: 00000306 br 1003ac0 <___vfprintf_internal_r+0x554> + 1003ab4: 843ffc04 addi r16,r16,-16 + 1003ab8: ad400204 addi r21,r21,8 + 1003abc: 9c00130e bge r19,r16,1003b0c <___vfprintf_internal_r+0x5a0> + 1003ac0: 94800404 addi r18,r18,16 + 1003ac4: 8c400044 addi r17,r17,1 + 1003ac8: af000015 stw fp,0(r21) + 1003acc: acc00115 stw r19,4(r21) + 1003ad0: dc800e15 stw r18,56(sp) + 1003ad4: dc400d15 stw r17,52(sp) + 1003ad8: a47ff60e bge r20,r17,1003ab4 <___vfprintf_internal_r+0x548> + 1003adc: d9014f17 ldw r4,1340(sp) + 1003ae0: b00b883a mov r5,r22 + 1003ae4: d9800c04 addi r6,sp,48 + 1003ae8: d9c15115 stw r7,1348(sp) + 1003aec: 10035140 call 1003514 <__sprint_r> + 1003af0: d9c15117 ldw r7,1348(sp) + 1003af4: 1000551e bne r2,zero,1003c4c <___vfprintf_internal_r+0x6e0> + 1003af8: 843ffc04 addi r16,r16,-16 + 1003afc: dc800e17 ldw r18,56(sp) + 1003b00: dc400d17 ldw r17,52(sp) + 1003b04: dd401904 addi r21,sp,100 + 1003b08: 9c3fed16 blt r19,r16,1003ac0 <___vfprintf_internal_r+0x554> + 1003b0c: 9425883a add r18,r18,r16 + 1003b10: 8c400044 addi r17,r17,1 + 1003b14: 008001c4 movi r2,7 + 1003b18: af000015 stw fp,0(r21) + 1003b1c: ac000115 stw r16,4(r21) + 1003b20: dc800e15 stw r18,56(sp) + 1003b24: dc400d15 stw r17,52(sp) + 1003b28: 14418216 blt r2,r17,1004134 <___vfprintf_internal_r+0xbc8> + 1003b2c: ad400204 addi r21,r21,8 + 1003b30: d9014c17 ldw r4,1328(sp) + 1003b34: 2080400c andi r2,r4,256 + 1003b38: 10004a1e bne r2,zero,1003c64 <___vfprintf_internal_r+0x6f8> + 1003b3c: d9414117 ldw r5,1284(sp) + 1003b40: 91e5883a add r18,r18,r7 + 1003b44: 8c400044 addi r17,r17,1 + 1003b48: 008001c4 movi r2,7 + 1003b4c: a9400015 stw r5,0(r21) + 1003b50: a9c00115 stw r7,4(r21) + 1003b54: dc800e15 stw r18,56(sp) + 1003b58: dc400d15 stw r17,52(sp) + 1003b5c: 14416716 blt r2,r17,10040fc <___vfprintf_internal_r+0xb90> + 1003b60: a8c00204 addi r3,r21,8 + 1003b64: d9814c17 ldw r6,1328(sp) + 1003b68: 3080010c andi r2,r6,4 + 1003b6c: 10002826 beq r2,zero,1003c10 <___vfprintf_internal_r+0x6a4> + 1003b70: d8814a17 ldw r2,1320(sp) + 1003b74: d9014517 ldw r4,1300(sp) + 1003b78: 1121c83a sub r16,r2,r4 + 1003b7c: 0400240e bge zero,r16,1003c10 <___vfprintf_internal_r+0x6a4> + 1003b80: 00800404 movi r2,16 + 1003b84: 14044f0e bge r2,r16,1004cc4 <___vfprintf_internal_r+0x1758> + 1003b88: dc400d17 ldw r17,52(sp) + 1003b8c: 1027883a mov r19,r2 + 1003b90: 070040b4 movhi fp,258 + 1003b94: e7238684 addi fp,fp,-29158 + 1003b98: 050001c4 movi r20,7 + 1003b9c: 00000306 br 1003bac <___vfprintf_internal_r+0x640> + 1003ba0: 843ffc04 addi r16,r16,-16 + 1003ba4: 18c00204 addi r3,r3,8 + 1003ba8: 9c00110e bge r19,r16,1003bf0 <___vfprintf_internal_r+0x684> + 1003bac: 94800404 addi r18,r18,16 + 1003bb0: 8c400044 addi r17,r17,1 + 1003bb4: 1f000015 stw fp,0(r3) + 1003bb8: 1cc00115 stw r19,4(r3) + 1003bbc: dc800e15 stw r18,56(sp) + 1003bc0: dc400d15 stw r17,52(sp) + 1003bc4: a47ff60e bge r20,r17,1003ba0 <___vfprintf_internal_r+0x634> + 1003bc8: d9014f17 ldw r4,1340(sp) + 1003bcc: b00b883a mov r5,r22 + 1003bd0: d9800c04 addi r6,sp,48 + 1003bd4: 10035140 call 1003514 <__sprint_r> + 1003bd8: 10001c1e bne r2,zero,1003c4c <___vfprintf_internal_r+0x6e0> + 1003bdc: 843ffc04 addi r16,r16,-16 + 1003be0: dc800e17 ldw r18,56(sp) + 1003be4: dc400d17 ldw r17,52(sp) + 1003be8: d8c01904 addi r3,sp,100 + 1003bec: 9c3fef16 blt r19,r16,1003bac <___vfprintf_internal_r+0x640> + 1003bf0: 9425883a add r18,r18,r16 + 1003bf4: 8c400044 addi r17,r17,1 + 1003bf8: 008001c4 movi r2,7 + 1003bfc: 1f000015 stw fp,0(r3) + 1003c00: 1c000115 stw r16,4(r3) + 1003c04: dc800e15 stw r18,56(sp) + 1003c08: dc400d15 stw r17,52(sp) + 1003c0c: 1440cb16 blt r2,r17,1003f3c <___vfprintf_internal_r+0x9d0> + 1003c10: d8814a17 ldw r2,1320(sp) + 1003c14: d9414517 ldw r5,1300(sp) + 1003c18: 1140010e bge r2,r5,1003c20 <___vfprintf_internal_r+0x6b4> + 1003c1c: 2805883a mov r2,r5 + 1003c20: d9814b17 ldw r6,1324(sp) + 1003c24: 308d883a add r6,r6,r2 + 1003c28: d9814b15 stw r6,1324(sp) + 1003c2c: 90013b1e bne r18,zero,100411c <___vfprintf_internal_r+0xbb0> + 1003c30: d9c14017 ldw r7,1280(sp) + 1003c34: dd401904 addi r21,sp,100 + 1003c38: d8000d15 stw zero,52(sp) + 1003c3c: 003ea706 br 10036dc <___vfprintf_internal_r+0x170> + 1003c40: d8800e17 ldw r2,56(sp) + 1003c44: 10053f1e bne r2,zero,1005144 <___vfprintf_internal_r+0x1bd8> + 1003c48: d8000d15 stw zero,52(sp) + 1003c4c: b080030b ldhu r2,12(r22) + 1003c50: 1080100c andi r2,r2,64 + 1003c54: 103e8726 beq r2,zero,1003674 <___vfprintf_internal_r+0x108> + 1003c58: 00bfffc4 movi r2,-1 + 1003c5c: d8814b15 stw r2,1324(sp) + 1003c60: 003e8406 br 1003674 <___vfprintf_internal_r+0x108> + 1003c64: d9814d17 ldw r6,1332(sp) + 1003c68: 00801944 movi r2,101 + 1003c6c: 11806e16 blt r2,r6,1003e28 <___vfprintf_internal_r+0x8bc> + 1003c70: d9414717 ldw r5,1308(sp) + 1003c74: 00c00044 movi r3,1 + 1003c78: 1943430e bge r3,r5,1004988 <___vfprintf_internal_r+0x141c> + 1003c7c: d8814117 ldw r2,1284(sp) + 1003c80: 94800044 addi r18,r18,1 + 1003c84: 8c400044 addi r17,r17,1 + 1003c88: a8800015 stw r2,0(r21) + 1003c8c: 008001c4 movi r2,7 + 1003c90: a8c00115 stw r3,4(r21) + 1003c94: dc800e15 stw r18,56(sp) + 1003c98: dc400d15 stw r17,52(sp) + 1003c9c: 1441ca16 blt r2,r17,10043c8 <___vfprintf_internal_r+0xe5c> + 1003ca0: a8c00204 addi r3,r21,8 + 1003ca4: d9014917 ldw r4,1316(sp) + 1003ca8: 00800044 movi r2,1 + 1003cac: 94800044 addi r18,r18,1 + 1003cb0: 8c400044 addi r17,r17,1 + 1003cb4: 18800115 stw r2,4(r3) + 1003cb8: 008001c4 movi r2,7 + 1003cbc: 19000015 stw r4,0(r3) + 1003cc0: dc800e15 stw r18,56(sp) + 1003cc4: dc400d15 stw r17,52(sp) + 1003cc8: 1441b616 blt r2,r17,10043a4 <___vfprintf_internal_r+0xe38> + 1003ccc: 1cc00204 addi r19,r3,8 + 1003cd0: d9014217 ldw r4,1288(sp) + 1003cd4: d9414317 ldw r5,1292(sp) + 1003cd8: 000d883a mov r6,zero + 1003cdc: 000f883a mov r7,zero + 1003ce0: 100b5740 call 100b574 <__nedf2> + 1003ce4: 10017426 beq r2,zero,10042b8 <___vfprintf_internal_r+0xd4c> + 1003ce8: d9414717 ldw r5,1308(sp) + 1003cec: d9814117 ldw r6,1284(sp) + 1003cf0: 8c400044 addi r17,r17,1 + 1003cf4: 2c85883a add r2,r5,r18 + 1003cf8: 14bfffc4 addi r18,r2,-1 + 1003cfc: 28bfffc4 addi r2,r5,-1 + 1003d00: 30c00044 addi r3,r6,1 + 1003d04: 98800115 stw r2,4(r19) + 1003d08: 008001c4 movi r2,7 + 1003d0c: 98c00015 stw r3,0(r19) + 1003d10: dc800e15 stw r18,56(sp) + 1003d14: dc400d15 stw r17,52(sp) + 1003d18: 14418e16 blt r2,r17,1004354 <___vfprintf_internal_r+0xde8> + 1003d1c: 9cc00204 addi r19,r19,8 + 1003d20: d9414817 ldw r5,1312(sp) + 1003d24: d8800804 addi r2,sp,32 + 1003d28: 8c400044 addi r17,r17,1 + 1003d2c: 9165883a add r18,r18,r5 + 1003d30: 98800015 stw r2,0(r19) + 1003d34: 008001c4 movi r2,7 + 1003d38: 99400115 stw r5,4(r19) + 1003d3c: dc800e15 stw r18,56(sp) + 1003d40: dc400d15 stw r17,52(sp) + 1003d44: 1440ed16 blt r2,r17,10040fc <___vfprintf_internal_r+0xb90> + 1003d48: 98c00204 addi r3,r19,8 + 1003d4c: 003f8506 br 1003b64 <___vfprintf_internal_r+0x5f8> + 1003d50: d9814a17 ldw r6,1320(sp) + 1003d54: d8814517 ldw r2,1300(sp) + 1003d58: 30a1c83a sub r16,r6,r2 + 1003d5c: 043f4b0e bge zero,r16,1003a8c <___vfprintf_internal_r+0x520> + 1003d60: 00800404 movi r2,16 + 1003d64: 1404340e bge r2,r16,1004e38 <___vfprintf_internal_r+0x18cc> + 1003d68: 1027883a mov r19,r2 + 1003d6c: 070040b4 movhi fp,258 + 1003d70: e7238284 addi fp,fp,-29174 + 1003d74: 050001c4 movi r20,7 + 1003d78: 00000306 br 1003d88 <___vfprintf_internal_r+0x81c> + 1003d7c: 843ffc04 addi r16,r16,-16 + 1003d80: ad400204 addi r21,r21,8 + 1003d84: 9c00130e bge r19,r16,1003dd4 <___vfprintf_internal_r+0x868> + 1003d88: 94800404 addi r18,r18,16 + 1003d8c: 8c400044 addi r17,r17,1 + 1003d90: af000015 stw fp,0(r21) + 1003d94: acc00115 stw r19,4(r21) + 1003d98: dc800e15 stw r18,56(sp) + 1003d9c: dc400d15 stw r17,52(sp) + 1003da0: a47ff60e bge r20,r17,1003d7c <___vfprintf_internal_r+0x810> + 1003da4: d9014f17 ldw r4,1340(sp) + 1003da8: b00b883a mov r5,r22 + 1003dac: d9800c04 addi r6,sp,48 + 1003db0: d9c15115 stw r7,1348(sp) + 1003db4: 10035140 call 1003514 <__sprint_r> + 1003db8: d9c15117 ldw r7,1348(sp) + 1003dbc: 103fa31e bne r2,zero,1003c4c <___vfprintf_internal_r+0x6e0> + 1003dc0: 843ffc04 addi r16,r16,-16 + 1003dc4: dc800e17 ldw r18,56(sp) + 1003dc8: dc400d17 ldw r17,52(sp) + 1003dcc: dd401904 addi r21,sp,100 + 1003dd0: 9c3fed16 blt r19,r16,1003d88 <___vfprintf_internal_r+0x81c> + 1003dd4: 9425883a add r18,r18,r16 + 1003dd8: 8c400044 addi r17,r17,1 + 1003ddc: 008001c4 movi r2,7 + 1003de0: af000015 stw fp,0(r21) + 1003de4: ac000115 stw r16,4(r21) + 1003de8: dc800e15 stw r18,56(sp) + 1003dec: dc400d15 stw r17,52(sp) + 1003df0: 14416116 blt r2,r17,1004378 <___vfprintf_internal_r+0xe0c> + 1003df4: ad400204 addi r21,r21,8 + 1003df8: 003f2406 br 1003a8c <___vfprintf_internal_r+0x520> + 1003dfc: d9014f17 ldw r4,1340(sp) + 1003e00: 1006fdc0 call 1006fdc <__sinit> + 1003e04: d9c15117 ldw r7,1348(sp) + 1003e08: 003def06 br 10035c8 <___vfprintf_internal_r+0x5c> + 1003e0c: d9014f17 ldw r4,1340(sp) + 1003e10: b00b883a mov r5,r22 + 1003e14: d9c15115 stw r7,1348(sp) + 1003e18: 100543c0 call 100543c <__swsetup_r> + 1003e1c: d9c15117 ldw r7,1348(sp) + 1003e20: 103dee26 beq r2,zero,10035dc <___vfprintf_internal_r+0x70> + 1003e24: 003f8c06 br 1003c58 <___vfprintf_internal_r+0x6ec> + 1003e28: d9014217 ldw r4,1288(sp) + 1003e2c: d9414317 ldw r5,1292(sp) + 1003e30: 000d883a mov r6,zero + 1003e34: 000f883a mov r7,zero + 1003e38: 100b4ec0 call 100b4ec <__eqdf2> + 1003e3c: 1000f21e bne r2,zero,1004208 <___vfprintf_internal_r+0xc9c> + 1003e40: 008040b4 movhi r2,258 + 1003e44: 10a38204 addi r2,r2,-29176 + 1003e48: 94800044 addi r18,r18,1 + 1003e4c: 8c400044 addi r17,r17,1 + 1003e50: a8800015 stw r2,0(r21) + 1003e54: 00c00044 movi r3,1 + 1003e58: 008001c4 movi r2,7 + 1003e5c: a8c00115 stw r3,4(r21) + 1003e60: dc800e15 stw r18,56(sp) + 1003e64: dc400d15 stw r17,52(sp) + 1003e68: 1442fa16 blt r2,r17,1004a54 <___vfprintf_internal_r+0x14e8> + 1003e6c: a8c00204 addi r3,r21,8 + 1003e70: d8800517 ldw r2,20(sp) + 1003e74: d9014717 ldw r4,1308(sp) + 1003e78: 11015c0e bge r2,r4,10043ec <___vfprintf_internal_r+0xe80> + 1003e7c: dc400d17 ldw r17,52(sp) + 1003e80: d9814917 ldw r6,1316(sp) + 1003e84: 00800044 movi r2,1 + 1003e88: 94800044 addi r18,r18,1 + 1003e8c: 8c400044 addi r17,r17,1 + 1003e90: 18800115 stw r2,4(r3) + 1003e94: 008001c4 movi r2,7 + 1003e98: 19800015 stw r6,0(r3) + 1003e9c: dc800e15 stw r18,56(sp) + 1003ea0: dc400d15 stw r17,52(sp) + 1003ea4: 14431016 blt r2,r17,1004ae8 <___vfprintf_internal_r+0x157c> + 1003ea8: 18c00204 addi r3,r3,8 + 1003eac: d8814717 ldw r2,1308(sp) + 1003eb0: 143fffc4 addi r16,r2,-1 + 1003eb4: 043f2b0e bge zero,r16,1003b64 <___vfprintf_internal_r+0x5f8> + 1003eb8: 00800404 movi r2,16 + 1003ebc: 1402a20e bge r2,r16,1004948 <___vfprintf_internal_r+0x13dc> + 1003ec0: dc400d17 ldw r17,52(sp) + 1003ec4: 1027883a mov r19,r2 + 1003ec8: 070040b4 movhi fp,258 + 1003ecc: e7238284 addi fp,fp,-29174 + 1003ed0: 050001c4 movi r20,7 + 1003ed4: 00000306 br 1003ee4 <___vfprintf_internal_r+0x978> + 1003ed8: 18c00204 addi r3,r3,8 + 1003edc: 843ffc04 addi r16,r16,-16 + 1003ee0: 9c029c0e bge r19,r16,1004954 <___vfprintf_internal_r+0x13e8> + 1003ee4: 94800404 addi r18,r18,16 + 1003ee8: 8c400044 addi r17,r17,1 + 1003eec: 1f000015 stw fp,0(r3) + 1003ef0: 1cc00115 stw r19,4(r3) + 1003ef4: dc800e15 stw r18,56(sp) + 1003ef8: dc400d15 stw r17,52(sp) + 1003efc: a47ff60e bge r20,r17,1003ed8 <___vfprintf_internal_r+0x96c> + 1003f00: d9014f17 ldw r4,1340(sp) + 1003f04: b00b883a mov r5,r22 + 1003f08: d9800c04 addi r6,sp,48 + 1003f0c: 10035140 call 1003514 <__sprint_r> + 1003f10: 103f4e1e bne r2,zero,1003c4c <___vfprintf_internal_r+0x6e0> + 1003f14: dc800e17 ldw r18,56(sp) + 1003f18: dc400d17 ldw r17,52(sp) + 1003f1c: d8c01904 addi r3,sp,100 + 1003f20: 003fee06 br 1003edc <___vfprintf_internal_r+0x970> + 1003f24: d8802c0b ldhu r2,176(sp) + 1003f28: 00ffffc4 movi r3,-1 + 1003f2c: d8c14b15 stw r3,1324(sp) + 1003f30: 1080100c andi r2,r2,64 + 1003f34: 103dcc1e bne r2,zero,1003668 <___vfprintf_internal_r+0xfc> + 1003f38: 003dce06 br 1003674 <___vfprintf_internal_r+0x108> + 1003f3c: d9014f17 ldw r4,1340(sp) + 1003f40: b00b883a mov r5,r22 + 1003f44: d9800c04 addi r6,sp,48 + 1003f48: 10035140 call 1003514 <__sprint_r> + 1003f4c: 103f3f1e bne r2,zero,1003c4c <___vfprintf_internal_r+0x6e0> + 1003f50: dc800e17 ldw r18,56(sp) + 1003f54: 003f2e06 br 1003c10 <___vfprintf_internal_r+0x6a4> + 1003f58: d9414c17 ldw r5,1328(sp) + 1003f5c: 29400414 ori r5,r5,16 + 1003f60: d9414c15 stw r5,1328(sp) + 1003f64: d9814c17 ldw r6,1328(sp) + 1003f68: 3080080c andi r2,r6,32 + 1003f6c: 10014f1e bne r2,zero,10044ac <___vfprintf_internal_r+0xf40> + 1003f70: d8c14c17 ldw r3,1328(sp) + 1003f74: 1880040c andi r2,r3,16 + 1003f78: 1002ea1e bne r2,zero,1004b24 <___vfprintf_internal_r+0x15b8> + 1003f7c: d9014c17 ldw r4,1328(sp) + 1003f80: 2080100c andi r2,r4,64 + 1003f84: 1002e726 beq r2,zero,1004b24 <___vfprintf_internal_r+0x15b8> + 1003f88: 3880000f ldh r2,0(r7) + 1003f8c: 39c00104 addi r7,r7,4 + 1003f90: d9c14015 stw r7,1280(sp) + 1003f94: 1023d7fa srai r17,r2,31 + 1003f98: 1021883a mov r16,r2 + 1003f9c: 88037216 blt r17,zero,1004d68 <___vfprintf_internal_r+0x17fc> + 1003fa0: 01000044 movi r4,1 + 1003fa4: 98000416 blt r19,zero,1003fb8 <___vfprintf_internal_r+0xa4c> + 1003fa8: d8c14c17 ldw r3,1328(sp) + 1003fac: 00bfdfc4 movi r2,-129 + 1003fb0: 1886703a and r3,r3,r2 + 1003fb4: d8c14c15 stw r3,1328(sp) + 1003fb8: 8444b03a or r2,r16,r17 + 1003fbc: 1002261e bne r2,zero,1004858 <___vfprintf_internal_r+0x12ec> + 1003fc0: 9802251e bne r19,zero,1004858 <___vfprintf_internal_r+0x12ec> + 1003fc4: 20803fcc andi r2,r4,255 + 1003fc8: 10029b26 beq r2,zero,1004a38 <___vfprintf_internal_r+0x14cc> + 1003fcc: d8c01904 addi r3,sp,100 + 1003fd0: dd000f04 addi r20,sp,60 + 1003fd4: d8c14115 stw r3,1284(sp) + 1003fd8: d8c14117 ldw r3,1284(sp) + 1003fdc: dcc14515 stw r19,1300(sp) + 1003fe0: a0c5c83a sub r2,r20,r3 + 1003fe4: 11c00a04 addi r7,r2,40 + 1003fe8: 99c0010e bge r19,r7,1003ff0 <___vfprintf_internal_r+0xa84> + 1003fec: d9c14515 stw r7,1300(sp) + 1003ff0: dcc14615 stw r19,1304(sp) + 1003ff4: d8800407 ldb r2,16(sp) + 1003ff8: 103e4c26 beq r2,zero,100392c <___vfprintf_internal_r+0x3c0> + 1003ffc: d8814517 ldw r2,1300(sp) + 1004000: 10800044 addi r2,r2,1 + 1004004: d8814515 stw r2,1300(sp) + 1004008: 003e4806 br 100392c <___vfprintf_internal_r+0x3c0> + 100400c: d9814c17 ldw r6,1328(sp) + 1004010: 31800414 ori r6,r6,16 + 1004014: d9814c15 stw r6,1328(sp) + 1004018: d8c14c17 ldw r3,1328(sp) + 100401c: 1880080c andi r2,r3,32 + 1004020: 1001271e bne r2,zero,10044c0 <___vfprintf_internal_r+0xf54> + 1004024: d9414c17 ldw r5,1328(sp) + 1004028: 2880040c andi r2,r5,16 + 100402c: 1002b61e bne r2,zero,1004b08 <___vfprintf_internal_r+0x159c> + 1004030: d9814c17 ldw r6,1328(sp) + 1004034: 3080100c andi r2,r6,64 + 1004038: 1002b326 beq r2,zero,1004b08 <___vfprintf_internal_r+0x159c> + 100403c: 3c00000b ldhu r16,0(r7) + 1004040: 0009883a mov r4,zero + 1004044: 39c00104 addi r7,r7,4 + 1004048: 0023883a mov r17,zero + 100404c: d9c14015 stw r7,1280(sp) + 1004050: d8000405 stb zero,16(sp) + 1004054: 003fd306 br 1003fa4 <___vfprintf_internal_r+0xa38> + 1004058: d9014c17 ldw r4,1328(sp) + 100405c: 21000414 ori r4,r4,16 + 1004060: d9014c15 stw r4,1328(sp) + 1004064: d9414c17 ldw r5,1328(sp) + 1004068: 2880080c andi r2,r5,32 + 100406c: 1001081e bne r2,zero,1004490 <___vfprintf_internal_r+0xf24> + 1004070: d8c14c17 ldw r3,1328(sp) + 1004074: 1880040c andi r2,r3,16 + 1004078: 1002b01e bne r2,zero,1004b3c <___vfprintf_internal_r+0x15d0> + 100407c: d9014c17 ldw r4,1328(sp) + 1004080: 2080100c andi r2,r4,64 + 1004084: 1002ad26 beq r2,zero,1004b3c <___vfprintf_internal_r+0x15d0> + 1004088: 3c00000b ldhu r16,0(r7) + 100408c: 01000044 movi r4,1 + 1004090: 39c00104 addi r7,r7,4 + 1004094: 0023883a mov r17,zero + 1004098: d9c14015 stw r7,1280(sp) + 100409c: d8000405 stb zero,16(sp) + 10040a0: 003fc006 br 1003fa4 <___vfprintf_internal_r+0xa38> + 10040a4: d9014f17 ldw r4,1340(sp) + 10040a8: b00b883a mov r5,r22 + 10040ac: d9800c04 addi r6,sp,48 + 10040b0: 10035140 call 1003514 <__sprint_r> + 10040b4: 103ee51e bne r2,zero,1003c4c <___vfprintf_internal_r+0x6e0> + 10040b8: dc800e17 ldw r18,56(sp) + 10040bc: d8c01904 addi r3,sp,100 + 10040c0: d9814c17 ldw r6,1328(sp) + 10040c4: 3080004c andi r2,r6,1 + 10040c8: 1005003a cmpeq r2,r2,zero + 10040cc: 103ea51e bne r2,zero,1003b64 <___vfprintf_internal_r+0x5f8> + 10040d0: 00800044 movi r2,1 + 10040d4: dc400d17 ldw r17,52(sp) + 10040d8: 18800115 stw r2,4(r3) + 10040dc: d8814917 ldw r2,1316(sp) + 10040e0: 94800044 addi r18,r18,1 + 10040e4: 8c400044 addi r17,r17,1 + 10040e8: 18800015 stw r2,0(r3) + 10040ec: 008001c4 movi r2,7 + 10040f0: dc800e15 stw r18,56(sp) + 10040f4: dc400d15 stw r17,52(sp) + 10040f8: 14421e0e bge r2,r17,1004974 <___vfprintf_internal_r+0x1408> + 10040fc: d9014f17 ldw r4,1340(sp) + 1004100: b00b883a mov r5,r22 + 1004104: d9800c04 addi r6,sp,48 + 1004108: 10035140 call 1003514 <__sprint_r> + 100410c: 103ecf1e bne r2,zero,1003c4c <___vfprintf_internal_r+0x6e0> + 1004110: dc800e17 ldw r18,56(sp) + 1004114: d8c01904 addi r3,sp,100 + 1004118: 003e9206 br 1003b64 <___vfprintf_internal_r+0x5f8> + 100411c: d9014f17 ldw r4,1340(sp) + 1004120: b00b883a mov r5,r22 + 1004124: d9800c04 addi r6,sp,48 + 1004128: 10035140 call 1003514 <__sprint_r> + 100412c: 103ec026 beq r2,zero,1003c30 <___vfprintf_internal_r+0x6c4> + 1004130: 003ec606 br 1003c4c <___vfprintf_internal_r+0x6e0> + 1004134: d9014f17 ldw r4,1340(sp) + 1004138: b00b883a mov r5,r22 + 100413c: d9800c04 addi r6,sp,48 + 1004140: d9c15115 stw r7,1348(sp) + 1004144: 10035140 call 1003514 <__sprint_r> + 1004148: d9c15117 ldw r7,1348(sp) + 100414c: 103ebf1e bne r2,zero,1003c4c <___vfprintf_internal_r+0x6e0> + 1004150: dc800e17 ldw r18,56(sp) + 1004154: dc400d17 ldw r17,52(sp) + 1004158: dd401904 addi r21,sp,100 + 100415c: 003e7406 br 1003b30 <___vfprintf_internal_r+0x5c4> + 1004160: d9014f17 ldw r4,1340(sp) + 1004164: b00b883a mov r5,r22 + 1004168: d9800c04 addi r6,sp,48 + 100416c: d9c15115 stw r7,1348(sp) + 1004170: 10035140 call 1003514 <__sprint_r> + 1004174: d9c15117 ldw r7,1348(sp) + 1004178: 103eb41e bne r2,zero,1003c4c <___vfprintf_internal_r+0x6e0> + 100417c: dd401904 addi r21,sp,100 + 1004180: 003d6d06 br 1003738 <___vfprintf_internal_r+0x1cc> + 1004184: d9014f17 ldw r4,1340(sp) + 1004188: b00b883a mov r5,r22 + 100418c: d9800c04 addi r6,sp,48 + 1004190: d9c15115 stw r7,1348(sp) + 1004194: 10035140 call 1003514 <__sprint_r> + 1004198: d9c15117 ldw r7,1348(sp) + 100419c: 103eab1e bne r2,zero,1003c4c <___vfprintf_internal_r+0x6e0> + 10041a0: dc800e17 ldw r18,56(sp) + 10041a4: dc400d17 ldw r17,52(sp) + 10041a8: dd401904 addi r21,sp,100 + 10041ac: 003e3406 br 1003a80 <___vfprintf_internal_r+0x514> + 10041b0: d9014f17 ldw r4,1340(sp) + 10041b4: b00b883a mov r5,r22 + 10041b8: d9800c04 addi r6,sp,48 + 10041bc: d9c15115 stw r7,1348(sp) + 10041c0: 10035140 call 1003514 <__sprint_r> + 10041c4: d9c15117 ldw r7,1348(sp) + 10041c8: 103ea01e bne r2,zero,1003c4c <___vfprintf_internal_r+0x6e0> + 10041cc: dc800e17 ldw r18,56(sp) + 10041d0: dc400d17 ldw r17,52(sp) + 10041d4: dd401904 addi r21,sp,100 + 10041d8: 003e1c06 br 1003a4c <___vfprintf_internal_r+0x4e0> + 10041dc: d9014f17 ldw r4,1340(sp) + 10041e0: b00b883a mov r5,r22 + 10041e4: d9800c04 addi r6,sp,48 + 10041e8: d9c15115 stw r7,1348(sp) + 10041ec: 10035140 call 1003514 <__sprint_r> + 10041f0: d9c15117 ldw r7,1348(sp) + 10041f4: 103e951e bne r2,zero,1003c4c <___vfprintf_internal_r+0x6e0> + 10041f8: dc800e17 ldw r18,56(sp) + 10041fc: dc400d17 ldw r17,52(sp) + 1004200: dd401904 addi r21,sp,100 + 1004204: 003e0406 br 1003a18 <___vfprintf_internal_r+0x4ac> + 1004208: d9000517 ldw r4,20(sp) + 100420c: 0102520e bge zero,r4,1004b58 <___vfprintf_internal_r+0x15ec> + 1004210: d9814717 ldw r6,1308(sp) + 1004214: 21807a16 blt r4,r6,1004400 <___vfprintf_internal_r+0xe94> + 1004218: d8814117 ldw r2,1284(sp) + 100421c: 91a5883a add r18,r18,r6 + 1004220: 8c400044 addi r17,r17,1 + 1004224: a8800015 stw r2,0(r21) + 1004228: 008001c4 movi r2,7 + 100422c: a9800115 stw r6,4(r21) + 1004230: dc800e15 stw r18,56(sp) + 1004234: dc400d15 stw r17,52(sp) + 1004238: 1442f616 blt r2,r17,1004e14 <___vfprintf_internal_r+0x18a8> + 100423c: a8c00204 addi r3,r21,8 + 1004240: d9414717 ldw r5,1308(sp) + 1004244: 2161c83a sub r16,r4,r5 + 1004248: 043f9d0e bge zero,r16,10040c0 <___vfprintf_internal_r+0xb54> + 100424c: 00800404 movi r2,16 + 1004250: 1402130e bge r2,r16,1004aa0 <___vfprintf_internal_r+0x1534> + 1004254: dc400d17 ldw r17,52(sp) + 1004258: 1027883a mov r19,r2 + 100425c: 070040b4 movhi fp,258 + 1004260: e7238284 addi fp,fp,-29174 + 1004264: 050001c4 movi r20,7 + 1004268: 00000306 br 1004278 <___vfprintf_internal_r+0xd0c> + 100426c: 18c00204 addi r3,r3,8 + 1004270: 843ffc04 addi r16,r16,-16 + 1004274: 9c020d0e bge r19,r16,1004aac <___vfprintf_internal_r+0x1540> + 1004278: 94800404 addi r18,r18,16 + 100427c: 8c400044 addi r17,r17,1 + 1004280: 1f000015 stw fp,0(r3) + 1004284: 1cc00115 stw r19,4(r3) + 1004288: dc800e15 stw r18,56(sp) + 100428c: dc400d15 stw r17,52(sp) + 1004290: a47ff60e bge r20,r17,100426c <___vfprintf_internal_r+0xd00> + 1004294: d9014f17 ldw r4,1340(sp) + 1004298: b00b883a mov r5,r22 + 100429c: d9800c04 addi r6,sp,48 + 10042a0: 10035140 call 1003514 <__sprint_r> + 10042a4: 103e691e bne r2,zero,1003c4c <___vfprintf_internal_r+0x6e0> + 10042a8: dc800e17 ldw r18,56(sp) + 10042ac: dc400d17 ldw r17,52(sp) + 10042b0: d8c01904 addi r3,sp,100 + 10042b4: 003fee06 br 1004270 <___vfprintf_internal_r+0xd04> + 10042b8: d8814717 ldw r2,1308(sp) + 10042bc: 143fffc4 addi r16,r2,-1 + 10042c0: 043e970e bge zero,r16,1003d20 <___vfprintf_internal_r+0x7b4> + 10042c4: 00800404 movi r2,16 + 10042c8: 1400180e bge r2,r16,100432c <___vfprintf_internal_r+0xdc0> + 10042cc: 1029883a mov r20,r2 + 10042d0: 070040b4 movhi fp,258 + 10042d4: e7238284 addi fp,fp,-29174 + 10042d8: 054001c4 movi r21,7 + 10042dc: 00000306 br 10042ec <___vfprintf_internal_r+0xd80> + 10042e0: 9cc00204 addi r19,r19,8 + 10042e4: 843ffc04 addi r16,r16,-16 + 10042e8: a400120e bge r20,r16,1004334 <___vfprintf_internal_r+0xdc8> + 10042ec: 94800404 addi r18,r18,16 + 10042f0: 8c400044 addi r17,r17,1 + 10042f4: 9f000015 stw fp,0(r19) + 10042f8: 9d000115 stw r20,4(r19) + 10042fc: dc800e15 stw r18,56(sp) + 1004300: dc400d15 stw r17,52(sp) + 1004304: ac7ff60e bge r21,r17,10042e0 <___vfprintf_internal_r+0xd74> + 1004308: d9014f17 ldw r4,1340(sp) + 100430c: b00b883a mov r5,r22 + 1004310: d9800c04 addi r6,sp,48 + 1004314: 10035140 call 1003514 <__sprint_r> + 1004318: 103e4c1e bne r2,zero,1003c4c <___vfprintf_internal_r+0x6e0> + 100431c: dc800e17 ldw r18,56(sp) + 1004320: dc400d17 ldw r17,52(sp) + 1004324: dcc01904 addi r19,sp,100 + 1004328: 003fee06 br 10042e4 <___vfprintf_internal_r+0xd78> + 100432c: 070040b4 movhi fp,258 + 1004330: e7238284 addi fp,fp,-29174 + 1004334: 9425883a add r18,r18,r16 + 1004338: 8c400044 addi r17,r17,1 + 100433c: 008001c4 movi r2,7 + 1004340: 9f000015 stw fp,0(r19) + 1004344: 9c000115 stw r16,4(r19) + 1004348: dc800e15 stw r18,56(sp) + 100434c: dc400d15 stw r17,52(sp) + 1004350: 147e720e bge r2,r17,1003d1c <___vfprintf_internal_r+0x7b0> + 1004354: d9014f17 ldw r4,1340(sp) + 1004358: b00b883a mov r5,r22 + 100435c: d9800c04 addi r6,sp,48 + 1004360: 10035140 call 1003514 <__sprint_r> + 1004364: 103e391e bne r2,zero,1003c4c <___vfprintf_internal_r+0x6e0> + 1004368: dc800e17 ldw r18,56(sp) + 100436c: dc400d17 ldw r17,52(sp) + 1004370: dcc01904 addi r19,sp,100 + 1004374: 003e6a06 br 1003d20 <___vfprintf_internal_r+0x7b4> + 1004378: d9014f17 ldw r4,1340(sp) + 100437c: b00b883a mov r5,r22 + 1004380: d9800c04 addi r6,sp,48 + 1004384: d9c15115 stw r7,1348(sp) + 1004388: 10035140 call 1003514 <__sprint_r> + 100438c: d9c15117 ldw r7,1348(sp) + 1004390: 103e2e1e bne r2,zero,1003c4c <___vfprintf_internal_r+0x6e0> + 1004394: dc800e17 ldw r18,56(sp) + 1004398: dc400d17 ldw r17,52(sp) + 100439c: dd401904 addi r21,sp,100 + 10043a0: 003dba06 br 1003a8c <___vfprintf_internal_r+0x520> + 10043a4: d9014f17 ldw r4,1340(sp) + 10043a8: b00b883a mov r5,r22 + 10043ac: d9800c04 addi r6,sp,48 + 10043b0: 10035140 call 1003514 <__sprint_r> + 10043b4: 103e251e bne r2,zero,1003c4c <___vfprintf_internal_r+0x6e0> + 10043b8: dc800e17 ldw r18,56(sp) + 10043bc: dc400d17 ldw r17,52(sp) + 10043c0: dcc01904 addi r19,sp,100 + 10043c4: 003e4206 br 1003cd0 <___vfprintf_internal_r+0x764> + 10043c8: d9014f17 ldw r4,1340(sp) + 10043cc: b00b883a mov r5,r22 + 10043d0: d9800c04 addi r6,sp,48 + 10043d4: 10035140 call 1003514 <__sprint_r> + 10043d8: 103e1c1e bne r2,zero,1003c4c <___vfprintf_internal_r+0x6e0> + 10043dc: dc800e17 ldw r18,56(sp) + 10043e0: dc400d17 ldw r17,52(sp) + 10043e4: d8c01904 addi r3,sp,100 + 10043e8: 003e2e06 br 1003ca4 <___vfprintf_internal_r+0x738> + 10043ec: d9414c17 ldw r5,1328(sp) + 10043f0: 2880004c andi r2,r5,1 + 10043f4: 1005003a cmpeq r2,r2,zero + 10043f8: 103dda1e bne r2,zero,1003b64 <___vfprintf_internal_r+0x5f8> + 10043fc: 003e9f06 br 1003e7c <___vfprintf_internal_r+0x910> + 1004400: d8c14117 ldw r3,1284(sp) + 1004404: 9125883a add r18,r18,r4 + 1004408: 8c400044 addi r17,r17,1 + 100440c: 008001c4 movi r2,7 + 1004410: a8c00015 stw r3,0(r21) + 1004414: a9000115 stw r4,4(r21) + 1004418: dc800e15 stw r18,56(sp) + 100441c: dc400d15 stw r17,52(sp) + 1004420: 14426616 blt r2,r17,1004dbc <___vfprintf_internal_r+0x1850> + 1004424: a8c00204 addi r3,r21,8 + 1004428: d9414917 ldw r5,1316(sp) + 100442c: 00800044 movi r2,1 + 1004430: 94800044 addi r18,r18,1 + 1004434: 8c400044 addi r17,r17,1 + 1004438: 18800115 stw r2,4(r3) + 100443c: 008001c4 movi r2,7 + 1004440: 19400015 stw r5,0(r3) + 1004444: dc800e15 stw r18,56(sp) + 1004448: dc400d15 stw r17,52(sp) + 100444c: 2021883a mov r16,r4 + 1004450: 14425016 blt r2,r17,1004d94 <___vfprintf_internal_r+0x1828> + 1004454: 19400204 addi r5,r3,8 + 1004458: d9814717 ldw r6,1308(sp) + 100445c: 8c400044 addi r17,r17,1 + 1004460: dc400d15 stw r17,52(sp) + 1004464: 3107c83a sub r3,r6,r4 + 1004468: d9014117 ldw r4,1284(sp) + 100446c: 90e5883a add r18,r18,r3 + 1004470: 28c00115 stw r3,4(r5) + 1004474: 8105883a add r2,r16,r4 + 1004478: 28800015 stw r2,0(r5) + 100447c: 008001c4 movi r2,7 + 1004480: dc800e15 stw r18,56(sp) + 1004484: 147f1d16 blt r2,r17,10040fc <___vfprintf_internal_r+0xb90> + 1004488: 28c00204 addi r3,r5,8 + 100448c: 003db506 br 1003b64 <___vfprintf_internal_r+0x5f8> + 1004490: 3c000017 ldw r16,0(r7) + 1004494: 3c400117 ldw r17,4(r7) + 1004498: 39800204 addi r6,r7,8 + 100449c: 01000044 movi r4,1 + 10044a0: d9814015 stw r6,1280(sp) + 10044a4: d8000405 stb zero,16(sp) + 10044a8: 003ebe06 br 1003fa4 <___vfprintf_internal_r+0xa38> + 10044ac: 3c000017 ldw r16,0(r7) + 10044b0: 3c400117 ldw r17,4(r7) + 10044b4: 38800204 addi r2,r7,8 + 10044b8: d8814015 stw r2,1280(sp) + 10044bc: 003eb706 br 1003f9c <___vfprintf_internal_r+0xa30> + 10044c0: 3c000017 ldw r16,0(r7) + 10044c4: 3c400117 ldw r17,4(r7) + 10044c8: 39000204 addi r4,r7,8 + 10044cc: d9014015 stw r4,1280(sp) + 10044d0: 0009883a mov r4,zero + 10044d4: d8000405 stb zero,16(sp) + 10044d8: 003eb206 br 1003fa4 <___vfprintf_internal_r+0xa38> + 10044dc: 38c00017 ldw r3,0(r7) + 10044e0: 39c00104 addi r7,r7,4 + 10044e4: d8c14a15 stw r3,1320(sp) + 10044e8: 1800d10e bge r3,zero,1004830 <___vfprintf_internal_r+0x12c4> + 10044ec: 00c7c83a sub r3,zero,r3 + 10044f0: d8c14a15 stw r3,1320(sp) + 10044f4: d9014c17 ldw r4,1328(sp) + 10044f8: b8c00007 ldb r3,0(r23) + 10044fc: 21000114 ori r4,r4,4 + 1004500: d9014c15 stw r4,1328(sp) + 1004504: 003c9806 br 1003768 <___vfprintf_internal_r+0x1fc> + 1004508: d9814c17 ldw r6,1328(sp) + 100450c: 3080080c andi r2,r6,32 + 1004510: 1001f026 beq r2,zero,1004cd4 <___vfprintf_internal_r+0x1768> + 1004514: d9014b17 ldw r4,1324(sp) + 1004518: 38800017 ldw r2,0(r7) + 100451c: 39c00104 addi r7,r7,4 + 1004520: d9c14015 stw r7,1280(sp) + 1004524: 2007d7fa srai r3,r4,31 + 1004528: d9c14017 ldw r7,1280(sp) + 100452c: 11000015 stw r4,0(r2) + 1004530: 10c00115 stw r3,4(r2) + 1004534: 003c6906 br 10036dc <___vfprintf_internal_r+0x170> + 1004538: b8c00007 ldb r3,0(r23) + 100453c: 00801b04 movi r2,108 + 1004540: 18824f26 beq r3,r2,1004e80 <___vfprintf_internal_r+0x1914> + 1004544: d9414c17 ldw r5,1328(sp) + 1004548: 29400414 ori r5,r5,16 + 100454c: d9414c15 stw r5,1328(sp) + 1004550: 003c8506 br 1003768 <___vfprintf_internal_r+0x1fc> + 1004554: d9814c17 ldw r6,1328(sp) + 1004558: b8c00007 ldb r3,0(r23) + 100455c: 31800814 ori r6,r6,32 + 1004560: d9814c15 stw r6,1328(sp) + 1004564: 003c8006 br 1003768 <___vfprintf_internal_r+0x1fc> + 1004568: d8814c17 ldw r2,1328(sp) + 100456c: 3c000017 ldw r16,0(r7) + 1004570: 00c01e04 movi r3,120 + 1004574: 10800094 ori r2,r2,2 + 1004578: d8814c15 stw r2,1328(sp) + 100457c: 39c00104 addi r7,r7,4 + 1004580: 014040b4 movhi r5,258 + 1004584: 29636b04 addi r5,r5,-29268 + 1004588: 00800c04 movi r2,48 + 100458c: 0023883a mov r17,zero + 1004590: 01000084 movi r4,2 + 1004594: d9c14015 stw r7,1280(sp) + 1004598: d8c14d15 stw r3,1332(sp) + 100459c: d9414415 stw r5,1296(sp) + 10045a0: d8800445 stb r2,17(sp) + 10045a4: d8c00485 stb r3,18(sp) + 10045a8: d8000405 stb zero,16(sp) + 10045ac: 003e7d06 br 1003fa4 <___vfprintf_internal_r+0xa38> + 10045b0: d8814c17 ldw r2,1328(sp) + 10045b4: b8c00007 ldb r3,0(r23) + 10045b8: 10801014 ori r2,r2,64 + 10045bc: d8814c15 stw r2,1328(sp) + 10045c0: 003c6906 br 1003768 <___vfprintf_internal_r+0x1fc> + 10045c4: d9414c17 ldw r5,1328(sp) + 10045c8: 2880020c andi r2,r5,8 + 10045cc: 1001df26 beq r2,zero,1004d4c <___vfprintf_internal_r+0x17e0> + 10045d0: 39800017 ldw r6,0(r7) + 10045d4: 38800204 addi r2,r7,8 + 10045d8: d8814015 stw r2,1280(sp) + 10045dc: d9814215 stw r6,1288(sp) + 10045e0: 39c00117 ldw r7,4(r7) + 10045e4: d9c14315 stw r7,1292(sp) + 10045e8: d9014217 ldw r4,1288(sp) + 10045ec: d9414317 ldw r5,1292(sp) + 10045f0: 10097340 call 1009734 <__isinfd> + 10045f4: 10021726 beq r2,zero,1004e54 <___vfprintf_internal_r+0x18e8> + 10045f8: d9014217 ldw r4,1288(sp) + 10045fc: d9414317 ldw r5,1292(sp) + 1004600: 000d883a mov r6,zero + 1004604: 000f883a mov r7,zero + 1004608: 100b70c0 call 100b70c <__ltdf2> + 100460c: 1002ca16 blt r2,zero,1005138 <___vfprintf_internal_r+0x1bcc> + 1004610: d9414d17 ldw r5,1332(sp) + 1004614: 008011c4 movi r2,71 + 1004618: 11420a16 blt r2,r5,1004e44 <___vfprintf_internal_r+0x18d8> + 100461c: 018040b4 movhi r6,258 + 1004620: 31a37004 addi r6,r6,-29248 + 1004624: d9814115 stw r6,1284(sp) + 1004628: d9014c17 ldw r4,1328(sp) + 100462c: 00c000c4 movi r3,3 + 1004630: 00bfdfc4 movi r2,-129 + 1004634: 2088703a and r4,r4,r2 + 1004638: 180f883a mov r7,r3 + 100463c: d8c14515 stw r3,1300(sp) + 1004640: d9014c15 stw r4,1328(sp) + 1004644: d8014615 stw zero,1304(sp) + 1004648: 003e6a06 br 1003ff4 <___vfprintf_internal_r+0xa88> + 100464c: 38800017 ldw r2,0(r7) + 1004650: 00c00044 movi r3,1 + 1004654: 39c00104 addi r7,r7,4 + 1004658: d9c14015 stw r7,1280(sp) + 100465c: d9000f04 addi r4,sp,60 + 1004660: 180f883a mov r7,r3 + 1004664: d8c14515 stw r3,1300(sp) + 1004668: d9014115 stw r4,1284(sp) + 100466c: d8800f05 stb r2,60(sp) + 1004670: d8000405 stb zero,16(sp) + 1004674: 003cac06 br 1003928 <___vfprintf_internal_r+0x3bc> + 1004678: 014040b4 movhi r5,258 + 100467c: 29637604 addi r5,r5,-29224 + 1004680: d9414415 stw r5,1296(sp) + 1004684: d9814c17 ldw r6,1328(sp) + 1004688: 3080080c andi r2,r6,32 + 100468c: 1000f926 beq r2,zero,1004a74 <___vfprintf_internal_r+0x1508> + 1004690: 3c000017 ldw r16,0(r7) + 1004694: 3c400117 ldw r17,4(r7) + 1004698: 38800204 addi r2,r7,8 + 100469c: d8814015 stw r2,1280(sp) + 10046a0: d9414c17 ldw r5,1328(sp) + 10046a4: 2880004c andi r2,r5,1 + 10046a8: 1005003a cmpeq r2,r2,zero + 10046ac: 1000b31e bne r2,zero,100497c <___vfprintf_internal_r+0x1410> + 10046b0: 8444b03a or r2,r16,r17 + 10046b4: 1000b126 beq r2,zero,100497c <___vfprintf_internal_r+0x1410> + 10046b8: d9814d17 ldw r6,1332(sp) + 10046bc: 29400094 ori r5,r5,2 + 10046c0: 00800c04 movi r2,48 + 10046c4: 01000084 movi r4,2 + 10046c8: d9414c15 stw r5,1328(sp) + 10046cc: d8800445 stb r2,17(sp) + 10046d0: d9800485 stb r6,18(sp) + 10046d4: d8000405 stb zero,16(sp) + 10046d8: 003e3206 br 1003fa4 <___vfprintf_internal_r+0xa38> + 10046dc: 018040b4 movhi r6,258 + 10046e0: 31a36b04 addi r6,r6,-29268 + 10046e4: d9814415 stw r6,1296(sp) + 10046e8: 003fe606 br 1004684 <___vfprintf_internal_r+0x1118> + 10046ec: 00800ac4 movi r2,43 + 10046f0: d8800405 stb r2,16(sp) + 10046f4: b8c00007 ldb r3,0(r23) + 10046f8: 003c1b06 br 1003768 <___vfprintf_internal_r+0x1fc> + 10046fc: d8814c17 ldw r2,1328(sp) + 1004700: b8c00007 ldb r3,0(r23) + 1004704: 10800054 ori r2,r2,1 + 1004708: d8814c15 stw r2,1328(sp) + 100470c: 003c1606 br 1003768 <___vfprintf_internal_r+0x1fc> + 1004710: d8800407 ldb r2,16(sp) + 1004714: 1000461e bne r2,zero,1004830 <___vfprintf_internal_r+0x12c4> + 1004718: 00800804 movi r2,32 + 100471c: d8800405 stb r2,16(sp) + 1004720: b8c00007 ldb r3,0(r23) + 1004724: 003c1006 br 1003768 <___vfprintf_internal_r+0x1fc> + 1004728: d9814c17 ldw r6,1328(sp) + 100472c: b8c00007 ldb r3,0(r23) + 1004730: 31800214 ori r6,r6,8 + 1004734: d9814c15 stw r6,1328(sp) + 1004738: 003c0b06 br 1003768 <___vfprintf_internal_r+0x1fc> + 100473c: 0007883a mov r3,zero + 1004740: 01000244 movi r4,9 + 1004744: 188002a4 muli r2,r3,10 + 1004748: b8c00007 ldb r3,0(r23) + 100474c: d9814d17 ldw r6,1332(sp) + 1004750: bdc00044 addi r23,r23,1 + 1004754: d8c14d15 stw r3,1332(sp) + 1004758: d9414d17 ldw r5,1332(sp) + 100475c: 3085883a add r2,r6,r2 + 1004760: 10fff404 addi r3,r2,-48 + 1004764: 28bff404 addi r2,r5,-48 + 1004768: 20bff62e bgeu r4,r2,1004744 <___vfprintf_internal_r+0x11d8> + 100476c: d8c14a15 stw r3,1320(sp) + 1004770: 003bff06 br 1003770 <___vfprintf_internal_r+0x204> + 1004774: d9414c17 ldw r5,1328(sp) + 1004778: b8c00007 ldb r3,0(r23) + 100477c: 29402014 ori r5,r5,128 + 1004780: d9414c15 stw r5,1328(sp) + 1004784: 003bf806 br 1003768 <___vfprintf_internal_r+0x1fc> + 1004788: b8c00007 ldb r3,0(r23) + 100478c: 00800a84 movi r2,42 + 1004790: bdc00044 addi r23,r23,1 + 1004794: 18831526 beq r3,r2,10053ec <___vfprintf_internal_r+0x1e80> + 1004798: d8c14d15 stw r3,1332(sp) + 100479c: 18bff404 addi r2,r3,-48 + 10047a0: 00c00244 movi r3,9 + 10047a4: 18827836 bltu r3,r2,1005188 <___vfprintf_internal_r+0x1c1c> + 10047a8: 000d883a mov r6,zero + 10047ac: 308002a4 muli r2,r6,10 + 10047b0: b9800007 ldb r6,0(r23) + 10047b4: d9414d17 ldw r5,1332(sp) + 10047b8: bdc00044 addi r23,r23,1 + 10047bc: d9814d15 stw r6,1332(sp) + 10047c0: d9014d17 ldw r4,1332(sp) + 10047c4: 1145883a add r2,r2,r5 + 10047c8: 11bff404 addi r6,r2,-48 + 10047cc: 20bff404 addi r2,r4,-48 + 10047d0: 18bff62e bgeu r3,r2,10047ac <___vfprintf_internal_r+0x1240> + 10047d4: 3027883a mov r19,r6 + 10047d8: 303be50e bge r6,zero,1003770 <___vfprintf_internal_r+0x204> + 10047dc: 04ffffc4 movi r19,-1 + 10047e0: 003be306 br 1003770 <___vfprintf_internal_r+0x204> + 10047e4: d8000405 stb zero,16(sp) + 10047e8: 39800017 ldw r6,0(r7) + 10047ec: 39c00104 addi r7,r7,4 + 10047f0: d9c14015 stw r7,1280(sp) + 10047f4: d9814115 stw r6,1284(sp) + 10047f8: 3001c926 beq r6,zero,1004f20 <___vfprintf_internal_r+0x19b4> + 10047fc: 98000e16 blt r19,zero,1004838 <___vfprintf_internal_r+0x12cc> + 1004800: d9014117 ldw r4,1284(sp) + 1004804: 000b883a mov r5,zero + 1004808: 980d883a mov r6,r19 + 100480c: 1007ee80 call 1007ee8 + 1004810: 10025926 beq r2,zero,1005178 <___vfprintf_internal_r+0x1c0c> + 1004814: d8c14117 ldw r3,1284(sp) + 1004818: 10cfc83a sub r7,r2,r3 + 100481c: 99c19e16 blt r19,r7,1004e98 <___vfprintf_internal_r+0x192c> + 1004820: d9c14515 stw r7,1300(sp) + 1004824: 38000916 blt r7,zero,100484c <___vfprintf_internal_r+0x12e0> + 1004828: d8014615 stw zero,1304(sp) + 100482c: 003df106 br 1003ff4 <___vfprintf_internal_r+0xa88> + 1004830: b8c00007 ldb r3,0(r23) + 1004834: 003bcc06 br 1003768 <___vfprintf_internal_r+0x1fc> + 1004838: d9014117 ldw r4,1284(sp) + 100483c: 10034a00 call 10034a0 + 1004840: d8814515 stw r2,1300(sp) + 1004844: 100f883a mov r7,r2 + 1004848: 103ff70e bge r2,zero,1004828 <___vfprintf_internal_r+0x12bc> + 100484c: d8014515 stw zero,1300(sp) + 1004850: d8014615 stw zero,1304(sp) + 1004854: 003de706 br 1003ff4 <___vfprintf_internal_r+0xa88> + 1004858: 20c03fcc andi r3,r4,255 + 100485c: 00800044 movi r2,1 + 1004860: 18802d26 beq r3,r2,1004918 <___vfprintf_internal_r+0x13ac> + 1004864: 18800e36 bltu r3,r2,10048a0 <___vfprintf_internal_r+0x1334> + 1004868: 00800084 movi r2,2 + 100486c: 1880fa26 beq r3,r2,1004c58 <___vfprintf_internal_r+0x16ec> + 1004870: 010040b4 movhi r4,258 + 1004874: 21237b04 addi r4,r4,-29204 + 1004878: 10034a00 call 10034a0 + 100487c: 100f883a mov r7,r2 + 1004880: dcc14515 stw r19,1300(sp) + 1004884: 9880010e bge r19,r2,100488c <___vfprintf_internal_r+0x1320> + 1004888: d8814515 stw r2,1300(sp) + 100488c: 008040b4 movhi r2,258 + 1004890: 10a37b04 addi r2,r2,-29204 + 1004894: dcc14615 stw r19,1304(sp) + 1004898: d8814115 stw r2,1284(sp) + 100489c: 003dd506 br 1003ff4 <___vfprintf_internal_r+0xa88> + 10048a0: d9401904 addi r5,sp,100 + 10048a4: dd000f04 addi r20,sp,60 + 10048a8: d9414115 stw r5,1284(sp) + 10048ac: 880a977a slli r5,r17,29 + 10048b0: d9814117 ldw r6,1284(sp) + 10048b4: 8004d0fa srli r2,r16,3 + 10048b8: 8806d0fa srli r3,r17,3 + 10048bc: 810001cc andi r4,r16,7 + 10048c0: 2884b03a or r2,r5,r2 + 10048c4: 31bfffc4 addi r6,r6,-1 + 10048c8: 21000c04 addi r4,r4,48 + 10048cc: d9814115 stw r6,1284(sp) + 10048d0: 10cab03a or r5,r2,r3 + 10048d4: 31000005 stb r4,0(r6) + 10048d8: 1021883a mov r16,r2 + 10048dc: 1823883a mov r17,r3 + 10048e0: 283ff21e bne r5,zero,10048ac <___vfprintf_internal_r+0x1340> + 10048e4: d8c14c17 ldw r3,1328(sp) + 10048e8: 1880004c andi r2,r3,1 + 10048ec: 1005003a cmpeq r2,r2,zero + 10048f0: 103db91e bne r2,zero,1003fd8 <___vfprintf_internal_r+0xa6c> + 10048f4: 20803fcc andi r2,r4,255 + 10048f8: 1080201c xori r2,r2,128 + 10048fc: 10bfe004 addi r2,r2,-128 + 1004900: 00c00c04 movi r3,48 + 1004904: 10fdb426 beq r2,r3,1003fd8 <___vfprintf_internal_r+0xa6c> + 1004908: 31bfffc4 addi r6,r6,-1 + 100490c: d9814115 stw r6,1284(sp) + 1004910: 30c00005 stb r3,0(r6) + 1004914: 003db006 br 1003fd8 <___vfprintf_internal_r+0xa6c> + 1004918: 88800068 cmpgeui r2,r17,1 + 100491c: 10002c1e bne r2,zero,10049d0 <___vfprintf_internal_r+0x1464> + 1004920: 8800021e bne r17,zero,100492c <___vfprintf_internal_r+0x13c0> + 1004924: 00800244 movi r2,9 + 1004928: 14002936 bltu r2,r16,10049d0 <___vfprintf_internal_r+0x1464> + 100492c: d90018c4 addi r4,sp,99 + 1004930: dd000f04 addi r20,sp,60 + 1004934: d9014115 stw r4,1284(sp) + 1004938: d9014117 ldw r4,1284(sp) + 100493c: 80800c04 addi r2,r16,48 + 1004940: 20800005 stb r2,0(r4) + 1004944: 003da406 br 1003fd8 <___vfprintf_internal_r+0xa6c> + 1004948: dc400d17 ldw r17,52(sp) + 100494c: 070040b4 movhi fp,258 + 1004950: e7238284 addi fp,fp,-29174 + 1004954: 9425883a add r18,r18,r16 + 1004958: 8c400044 addi r17,r17,1 + 100495c: 008001c4 movi r2,7 + 1004960: 1f000015 stw fp,0(r3) + 1004964: 1c000115 stw r16,4(r3) + 1004968: dc800e15 stw r18,56(sp) + 100496c: dc400d15 stw r17,52(sp) + 1004970: 147de216 blt r2,r17,10040fc <___vfprintf_internal_r+0xb90> + 1004974: 18c00204 addi r3,r3,8 + 1004978: 003c7a06 br 1003b64 <___vfprintf_internal_r+0x5f8> + 100497c: 01000084 movi r4,2 + 1004980: d8000405 stb zero,16(sp) + 1004984: 003d8706 br 1003fa4 <___vfprintf_internal_r+0xa38> + 1004988: d9814c17 ldw r6,1328(sp) + 100498c: 30c4703a and r2,r6,r3 + 1004990: 1005003a cmpeq r2,r2,zero + 1004994: 103cb926 beq r2,zero,1003c7c <___vfprintf_internal_r+0x710> + 1004998: d9014117 ldw r4,1284(sp) + 100499c: 94800044 addi r18,r18,1 + 10049a0: 8c400044 addi r17,r17,1 + 10049a4: 008001c4 movi r2,7 + 10049a8: a9000015 stw r4,0(r21) + 10049ac: a8c00115 stw r3,4(r21) + 10049b0: dc800e15 stw r18,56(sp) + 10049b4: dc400d15 stw r17,52(sp) + 10049b8: 147e6616 blt r2,r17,1004354 <___vfprintf_internal_r+0xde8> + 10049bc: acc00204 addi r19,r21,8 + 10049c0: 003cd706 br 1003d20 <___vfprintf_internal_r+0x7b4> + 10049c4: 070040b4 movhi fp,258 + 10049c8: e7238284 addi fp,fp,-29174 + 10049cc: 003c4f06 br 1003b0c <___vfprintf_internal_r+0x5a0> + 10049d0: dd000f04 addi r20,sp,60 + 10049d4: dc801904 addi r18,sp,100 + 10049d8: 8009883a mov r4,r16 + 10049dc: 880b883a mov r5,r17 + 10049e0: 01800284 movi r6,10 + 10049e4: 000f883a mov r7,zero + 10049e8: 100a41c0 call 100a41c <__umoddi3> + 10049ec: 12000c04 addi r8,r2,48 + 10049f0: 94bfffc4 addi r18,r18,-1 + 10049f4: 8009883a mov r4,r16 + 10049f8: 880b883a mov r5,r17 + 10049fc: 01800284 movi r6,10 + 1004a00: 000f883a mov r7,zero + 1004a04: 92000005 stb r8,0(r18) + 1004a08: 1009e400 call 1009e40 <__udivdi3> + 1004a0c: 1009883a mov r4,r2 + 1004a10: 1021883a mov r16,r2 + 1004a14: 18800068 cmpgeui r2,r3,1 + 1004a18: 1823883a mov r17,r3 + 1004a1c: 103fee1e bne r2,zero,10049d8 <___vfprintf_internal_r+0x146c> + 1004a20: 1800021e bne r3,zero,1004a2c <___vfprintf_internal_r+0x14c0> + 1004a24: 00800244 movi r2,9 + 1004a28: 113feb36 bltu r2,r4,10049d8 <___vfprintf_internal_r+0x146c> + 1004a2c: 94bfffc4 addi r18,r18,-1 + 1004a30: dc814115 stw r18,1284(sp) + 1004a34: 003fc006 br 1004938 <___vfprintf_internal_r+0x13cc> + 1004a38: d9014c17 ldw r4,1328(sp) + 1004a3c: 2080004c andi r2,r4,1 + 1004a40: 10009a1e bne r2,zero,1004cac <___vfprintf_internal_r+0x1740> + 1004a44: d9401904 addi r5,sp,100 + 1004a48: dd000f04 addi r20,sp,60 + 1004a4c: d9414115 stw r5,1284(sp) + 1004a50: 003d6106 br 1003fd8 <___vfprintf_internal_r+0xa6c> + 1004a54: d9014f17 ldw r4,1340(sp) + 1004a58: b00b883a mov r5,r22 + 1004a5c: d9800c04 addi r6,sp,48 + 1004a60: 10035140 call 1003514 <__sprint_r> + 1004a64: 103c791e bne r2,zero,1003c4c <___vfprintf_internal_r+0x6e0> + 1004a68: dc800e17 ldw r18,56(sp) + 1004a6c: d8c01904 addi r3,sp,100 + 1004a70: 003cff06 br 1003e70 <___vfprintf_internal_r+0x904> + 1004a74: d8c14c17 ldw r3,1328(sp) + 1004a78: 1880040c andi r2,r3,16 + 1004a7c: 1000711e bne r2,zero,1004c44 <___vfprintf_internal_r+0x16d8> + 1004a80: d9014c17 ldw r4,1328(sp) + 1004a84: 2080100c andi r2,r4,64 + 1004a88: 10006e26 beq r2,zero,1004c44 <___vfprintf_internal_r+0x16d8> + 1004a8c: 3c00000b ldhu r16,0(r7) + 1004a90: 0023883a mov r17,zero + 1004a94: 39c00104 addi r7,r7,4 + 1004a98: d9c14015 stw r7,1280(sp) + 1004a9c: 003f0006 br 10046a0 <___vfprintf_internal_r+0x1134> + 1004aa0: dc400d17 ldw r17,52(sp) + 1004aa4: 070040b4 movhi fp,258 + 1004aa8: e7238284 addi fp,fp,-29174 + 1004aac: 9425883a add r18,r18,r16 + 1004ab0: 8c400044 addi r17,r17,1 + 1004ab4: 008001c4 movi r2,7 + 1004ab8: 1f000015 stw fp,0(r3) + 1004abc: 1c000115 stw r16,4(r3) + 1004ac0: dc800e15 stw r18,56(sp) + 1004ac4: dc400d15 stw r17,52(sp) + 1004ac8: 147d7616 blt r2,r17,10040a4 <___vfprintf_internal_r+0xb38> + 1004acc: 18c00204 addi r3,r3,8 + 1004ad0: 003d7b06 br 10040c0 <___vfprintf_internal_r+0xb54> + 1004ad4: dc800e17 ldw r18,56(sp) + 1004ad8: dc400d17 ldw r17,52(sp) + 1004adc: 070040b4 movhi fp,258 + 1004ae0: e7238684 addi fp,fp,-29158 + 1004ae4: 003bc006 br 10039e8 <___vfprintf_internal_r+0x47c> + 1004ae8: d9014f17 ldw r4,1340(sp) + 1004aec: b00b883a mov r5,r22 + 1004af0: d9800c04 addi r6,sp,48 + 1004af4: 10035140 call 1003514 <__sprint_r> + 1004af8: 103c541e bne r2,zero,1003c4c <___vfprintf_internal_r+0x6e0> + 1004afc: dc800e17 ldw r18,56(sp) + 1004b00: d8c01904 addi r3,sp,100 + 1004b04: 003ce906 br 1003eac <___vfprintf_internal_r+0x940> + 1004b08: 3c000017 ldw r16,0(r7) + 1004b0c: 0009883a mov r4,zero + 1004b10: 39c00104 addi r7,r7,4 + 1004b14: 0023883a mov r17,zero + 1004b18: d9c14015 stw r7,1280(sp) + 1004b1c: d8000405 stb zero,16(sp) + 1004b20: 003d2006 br 1003fa4 <___vfprintf_internal_r+0xa38> + 1004b24: 38800017 ldw r2,0(r7) + 1004b28: 39c00104 addi r7,r7,4 + 1004b2c: d9c14015 stw r7,1280(sp) + 1004b30: 1023d7fa srai r17,r2,31 + 1004b34: 1021883a mov r16,r2 + 1004b38: 003d1806 br 1003f9c <___vfprintf_internal_r+0xa30> + 1004b3c: 3c000017 ldw r16,0(r7) + 1004b40: 01000044 movi r4,1 + 1004b44: 39c00104 addi r7,r7,4 + 1004b48: 0023883a mov r17,zero + 1004b4c: d9c14015 stw r7,1280(sp) + 1004b50: d8000405 stb zero,16(sp) + 1004b54: 003d1306 br 1003fa4 <___vfprintf_internal_r+0xa38> + 1004b58: 008040b4 movhi r2,258 + 1004b5c: 10a38204 addi r2,r2,-29176 + 1004b60: 94800044 addi r18,r18,1 + 1004b64: 8c400044 addi r17,r17,1 + 1004b68: a8800015 stw r2,0(r21) + 1004b6c: 00c00044 movi r3,1 + 1004b70: 008001c4 movi r2,7 + 1004b74: a8c00115 stw r3,4(r21) + 1004b78: dc800e15 stw r18,56(sp) + 1004b7c: dc400d15 stw r17,52(sp) + 1004b80: 1440ca16 blt r2,r17,1004eac <___vfprintf_internal_r+0x1940> + 1004b84: a8c00204 addi r3,r21,8 + 1004b88: 2000061e bne r4,zero,1004ba4 <___vfprintf_internal_r+0x1638> + 1004b8c: d9414717 ldw r5,1308(sp) + 1004b90: 2800041e bne r5,zero,1004ba4 <___vfprintf_internal_r+0x1638> + 1004b94: d9814c17 ldw r6,1328(sp) + 1004b98: 3080004c andi r2,r6,1 + 1004b9c: 1005003a cmpeq r2,r2,zero + 1004ba0: 103bf01e bne r2,zero,1003b64 <___vfprintf_internal_r+0x5f8> + 1004ba4: 00800044 movi r2,1 + 1004ba8: dc400d17 ldw r17,52(sp) + 1004bac: 18800115 stw r2,4(r3) + 1004bb0: d8814917 ldw r2,1316(sp) + 1004bb4: 94800044 addi r18,r18,1 + 1004bb8: 8c400044 addi r17,r17,1 + 1004bbc: 18800015 stw r2,0(r3) + 1004bc0: 008001c4 movi r2,7 + 1004bc4: dc800e15 stw r18,56(sp) + 1004bc8: dc400d15 stw r17,52(sp) + 1004bcc: 1440ca16 blt r2,r17,1004ef8 <___vfprintf_internal_r+0x198c> + 1004bd0: 18c00204 addi r3,r3,8 + 1004bd4: 0121c83a sub r16,zero,r4 + 1004bd8: 0400500e bge zero,r16,1004d1c <___vfprintf_internal_r+0x17b0> + 1004bdc: 00800404 movi r2,16 + 1004be0: 1400800e bge r2,r16,1004de4 <___vfprintf_internal_r+0x1878> + 1004be4: 1027883a mov r19,r2 + 1004be8: 070040b4 movhi fp,258 + 1004bec: e7238284 addi fp,fp,-29174 + 1004bf0: 050001c4 movi r20,7 + 1004bf4: 00000306 br 1004c04 <___vfprintf_internal_r+0x1698> + 1004bf8: 18c00204 addi r3,r3,8 + 1004bfc: 843ffc04 addi r16,r16,-16 + 1004c00: 9c007a0e bge r19,r16,1004dec <___vfprintf_internal_r+0x1880> + 1004c04: 94800404 addi r18,r18,16 + 1004c08: 8c400044 addi r17,r17,1 + 1004c0c: 1f000015 stw fp,0(r3) + 1004c10: 1cc00115 stw r19,4(r3) + 1004c14: dc800e15 stw r18,56(sp) + 1004c18: dc400d15 stw r17,52(sp) + 1004c1c: a47ff60e bge r20,r17,1004bf8 <___vfprintf_internal_r+0x168c> + 1004c20: d9014f17 ldw r4,1340(sp) + 1004c24: b00b883a mov r5,r22 + 1004c28: d9800c04 addi r6,sp,48 + 1004c2c: 10035140 call 1003514 <__sprint_r> + 1004c30: 103c061e bne r2,zero,1003c4c <___vfprintf_internal_r+0x6e0> + 1004c34: dc800e17 ldw r18,56(sp) + 1004c38: dc400d17 ldw r17,52(sp) + 1004c3c: d8c01904 addi r3,sp,100 + 1004c40: 003fee06 br 1004bfc <___vfprintf_internal_r+0x1690> + 1004c44: 3c000017 ldw r16,0(r7) + 1004c48: 0023883a mov r17,zero + 1004c4c: 39c00104 addi r7,r7,4 + 1004c50: d9c14015 stw r7,1280(sp) + 1004c54: 003e9206 br 10046a0 <___vfprintf_internal_r+0x1134> + 1004c58: d9401904 addi r5,sp,100 + 1004c5c: dd000f04 addi r20,sp,60 + 1004c60: d9414115 stw r5,1284(sp) + 1004c64: d9814417 ldw r6,1296(sp) + 1004c68: 880a973a slli r5,r17,28 + 1004c6c: 8004d13a srli r2,r16,4 + 1004c70: 810003cc andi r4,r16,15 + 1004c74: 3109883a add r4,r6,r4 + 1004c78: 2884b03a or r2,r5,r2 + 1004c7c: 21400003 ldbu r5,0(r4) + 1004c80: d9014117 ldw r4,1284(sp) + 1004c84: 8806d13a srli r3,r17,4 + 1004c88: 1021883a mov r16,r2 + 1004c8c: 213fffc4 addi r4,r4,-1 + 1004c90: d9014115 stw r4,1284(sp) + 1004c94: d9814117 ldw r6,1284(sp) + 1004c98: 10c8b03a or r4,r2,r3 + 1004c9c: 1823883a mov r17,r3 + 1004ca0: 31400005 stb r5,0(r6) + 1004ca4: 203fef1e bne r4,zero,1004c64 <___vfprintf_internal_r+0x16f8> + 1004ca8: 003ccb06 br 1003fd8 <___vfprintf_internal_r+0xa6c> + 1004cac: 00800c04 movi r2,48 + 1004cb0: d98018c4 addi r6,sp,99 + 1004cb4: dd000f04 addi r20,sp,60 + 1004cb8: d88018c5 stb r2,99(sp) + 1004cbc: d9814115 stw r6,1284(sp) + 1004cc0: 003cc506 br 1003fd8 <___vfprintf_internal_r+0xa6c> + 1004cc4: dc400d17 ldw r17,52(sp) + 1004cc8: 070040b4 movhi fp,258 + 1004ccc: e7238684 addi fp,fp,-29158 + 1004cd0: 003bc706 br 1003bf0 <___vfprintf_internal_r+0x684> + 1004cd4: d9414c17 ldw r5,1328(sp) + 1004cd8: 2880040c andi r2,r5,16 + 1004cdc: 10007c26 beq r2,zero,1004ed0 <___vfprintf_internal_r+0x1964> + 1004ce0: 38800017 ldw r2,0(r7) + 1004ce4: 39c00104 addi r7,r7,4 + 1004ce8: d9c14015 stw r7,1280(sp) + 1004cec: d9814b17 ldw r6,1324(sp) + 1004cf0: d9c14017 ldw r7,1280(sp) + 1004cf4: 11800015 stw r6,0(r2) + 1004cf8: 003a7806 br 10036dc <___vfprintf_internal_r+0x170> + 1004cfc: d9014f17 ldw r4,1340(sp) + 1004d00: b00b883a mov r5,r22 + 1004d04: d9800c04 addi r6,sp,48 + 1004d08: 10035140 call 1003514 <__sprint_r> + 1004d0c: 103bcf1e bne r2,zero,1003c4c <___vfprintf_internal_r+0x6e0> + 1004d10: dc800e17 ldw r18,56(sp) + 1004d14: dc400d17 ldw r17,52(sp) + 1004d18: d8c01904 addi r3,sp,100 + 1004d1c: d9014717 ldw r4,1308(sp) + 1004d20: d9414117 ldw r5,1284(sp) + 1004d24: 8c400044 addi r17,r17,1 + 1004d28: 9125883a add r18,r18,r4 + 1004d2c: 008001c4 movi r2,7 + 1004d30: 19400015 stw r5,0(r3) + 1004d34: 19000115 stw r4,4(r3) + 1004d38: dc800e15 stw r18,56(sp) + 1004d3c: dc400d15 stw r17,52(sp) + 1004d40: 147cee16 blt r2,r17,10040fc <___vfprintf_internal_r+0xb90> + 1004d44: 18c00204 addi r3,r3,8 + 1004d48: 003b8606 br 1003b64 <___vfprintf_internal_r+0x5f8> + 1004d4c: 38c00017 ldw r3,0(r7) + 1004d50: 39000204 addi r4,r7,8 + 1004d54: d9014015 stw r4,1280(sp) + 1004d58: d8c14215 stw r3,1288(sp) + 1004d5c: 39c00117 ldw r7,4(r7) + 1004d60: d9c14315 stw r7,1292(sp) + 1004d64: 003e2006 br 10045e8 <___vfprintf_internal_r+0x107c> + 1004d68: 0005883a mov r2,zero + 1004d6c: 1409c83a sub r4,r2,r16 + 1004d70: 1105803a cmpltu r2,r2,r4 + 1004d74: 044bc83a sub r5,zero,r17 + 1004d78: 2885c83a sub r2,r5,r2 + 1004d7c: 2021883a mov r16,r4 + 1004d80: 1023883a mov r17,r2 + 1004d84: 01000044 movi r4,1 + 1004d88: 00800b44 movi r2,45 + 1004d8c: d8800405 stb r2,16(sp) + 1004d90: 003c8406 br 1003fa4 <___vfprintf_internal_r+0xa38> + 1004d94: d9014f17 ldw r4,1340(sp) + 1004d98: b00b883a mov r5,r22 + 1004d9c: d9800c04 addi r6,sp,48 + 1004da0: 10035140 call 1003514 <__sprint_r> + 1004da4: 103ba91e bne r2,zero,1003c4c <___vfprintf_internal_r+0x6e0> + 1004da8: dc800e17 ldw r18,56(sp) + 1004dac: dc400d17 ldw r17,52(sp) + 1004db0: d9000517 ldw r4,20(sp) + 1004db4: d9401904 addi r5,sp,100 + 1004db8: 003da706 br 1004458 <___vfprintf_internal_r+0xeec> + 1004dbc: d9014f17 ldw r4,1340(sp) + 1004dc0: b00b883a mov r5,r22 + 1004dc4: d9800c04 addi r6,sp,48 + 1004dc8: 10035140 call 1003514 <__sprint_r> + 1004dcc: 103b9f1e bne r2,zero,1003c4c <___vfprintf_internal_r+0x6e0> + 1004dd0: dc800e17 ldw r18,56(sp) + 1004dd4: dc400d17 ldw r17,52(sp) + 1004dd8: d9000517 ldw r4,20(sp) + 1004ddc: d8c01904 addi r3,sp,100 + 1004de0: 003d9106 br 1004428 <___vfprintf_internal_r+0xebc> + 1004de4: 070040b4 movhi fp,258 + 1004de8: e7238284 addi fp,fp,-29174 + 1004dec: 9425883a add r18,r18,r16 + 1004df0: 8c400044 addi r17,r17,1 + 1004df4: 008001c4 movi r2,7 + 1004df8: 1f000015 stw fp,0(r3) + 1004dfc: 1c000115 stw r16,4(r3) + 1004e00: dc800e15 stw r18,56(sp) + 1004e04: dc400d15 stw r17,52(sp) + 1004e08: 147fbc16 blt r2,r17,1004cfc <___vfprintf_internal_r+0x1790> + 1004e0c: 18c00204 addi r3,r3,8 + 1004e10: 003fc206 br 1004d1c <___vfprintf_internal_r+0x17b0> + 1004e14: d9014f17 ldw r4,1340(sp) + 1004e18: b00b883a mov r5,r22 + 1004e1c: d9800c04 addi r6,sp,48 + 1004e20: 10035140 call 1003514 <__sprint_r> + 1004e24: 103b891e bne r2,zero,1003c4c <___vfprintf_internal_r+0x6e0> + 1004e28: dc800e17 ldw r18,56(sp) + 1004e2c: d9000517 ldw r4,20(sp) + 1004e30: d8c01904 addi r3,sp,100 + 1004e34: 003d0206 br 1004240 <___vfprintf_internal_r+0xcd4> + 1004e38: 070040b4 movhi fp,258 + 1004e3c: e7238284 addi fp,fp,-29174 + 1004e40: 003be406 br 1003dd4 <___vfprintf_internal_r+0x868> + 1004e44: 008040b4 movhi r2,258 + 1004e48: 10a37104 addi r2,r2,-29244 + 1004e4c: d8814115 stw r2,1284(sp) + 1004e50: 003df506 br 1004628 <___vfprintf_internal_r+0x10bc> + 1004e54: d9014217 ldw r4,1288(sp) + 1004e58: d9414317 ldw r5,1292(sp) + 1004e5c: 10097740 call 1009774 <__isnand> + 1004e60: 10003926 beq r2,zero,1004f48 <___vfprintf_internal_r+0x19dc> + 1004e64: d9414d17 ldw r5,1332(sp) + 1004e68: 008011c4 movi r2,71 + 1004e6c: 1140ce16 blt r2,r5,10051a8 <___vfprintf_internal_r+0x1c3c> + 1004e70: 018040b4 movhi r6,258 + 1004e74: 31a37204 addi r6,r6,-29240 + 1004e78: d9814115 stw r6,1284(sp) + 1004e7c: 003dea06 br 1004628 <___vfprintf_internal_r+0x10bc> + 1004e80: d9014c17 ldw r4,1328(sp) + 1004e84: bdc00044 addi r23,r23,1 + 1004e88: b8c00007 ldb r3,0(r23) + 1004e8c: 21000814 ori r4,r4,32 + 1004e90: d9014c15 stw r4,1328(sp) + 1004e94: 003a3406 br 1003768 <___vfprintf_internal_r+0x1fc> + 1004e98: dcc14515 stw r19,1300(sp) + 1004e9c: 98011016 blt r19,zero,10052e0 <___vfprintf_internal_r+0x1d74> + 1004ea0: 980f883a mov r7,r19 + 1004ea4: d8014615 stw zero,1304(sp) + 1004ea8: 003c5206 br 1003ff4 <___vfprintf_internal_r+0xa88> + 1004eac: d9014f17 ldw r4,1340(sp) + 1004eb0: b00b883a mov r5,r22 + 1004eb4: d9800c04 addi r6,sp,48 + 1004eb8: 10035140 call 1003514 <__sprint_r> + 1004ebc: 103b631e bne r2,zero,1003c4c <___vfprintf_internal_r+0x6e0> + 1004ec0: dc800e17 ldw r18,56(sp) + 1004ec4: d9000517 ldw r4,20(sp) + 1004ec8: d8c01904 addi r3,sp,100 + 1004ecc: 003f2e06 br 1004b88 <___vfprintf_internal_r+0x161c> + 1004ed0: d8c14c17 ldw r3,1328(sp) + 1004ed4: 1880100c andi r2,r3,64 + 1004ed8: 1000a026 beq r2,zero,100515c <___vfprintf_internal_r+0x1bf0> + 1004edc: 38800017 ldw r2,0(r7) + 1004ee0: 39c00104 addi r7,r7,4 + 1004ee4: d9c14015 stw r7,1280(sp) + 1004ee8: d9014b17 ldw r4,1324(sp) + 1004eec: d9c14017 ldw r7,1280(sp) + 1004ef0: 1100000d sth r4,0(r2) + 1004ef4: 0039f906 br 10036dc <___vfprintf_internal_r+0x170> + 1004ef8: d9014f17 ldw r4,1340(sp) + 1004efc: b00b883a mov r5,r22 + 1004f00: d9800c04 addi r6,sp,48 + 1004f04: 10035140 call 1003514 <__sprint_r> + 1004f08: 103b501e bne r2,zero,1003c4c <___vfprintf_internal_r+0x6e0> + 1004f0c: dc800e17 ldw r18,56(sp) + 1004f10: dc400d17 ldw r17,52(sp) + 1004f14: d9000517 ldw r4,20(sp) + 1004f18: d8c01904 addi r3,sp,100 + 1004f1c: 003f2d06 br 1004bd4 <___vfprintf_internal_r+0x1668> + 1004f20: 00800184 movi r2,6 + 1004f24: 14c09a36 bltu r2,r19,1005190 <___vfprintf_internal_r+0x1c24> + 1004f28: dcc14515 stw r19,1300(sp) + 1004f2c: 9800010e bge r19,zero,1004f34 <___vfprintf_internal_r+0x19c8> + 1004f30: d8014515 stw zero,1300(sp) + 1004f34: 008040b4 movhi r2,258 + 1004f38: 10a37404 addi r2,r2,-29232 + 1004f3c: 980f883a mov r7,r19 + 1004f40: d8814115 stw r2,1284(sp) + 1004f44: 003a7806 br 1003928 <___vfprintf_internal_r+0x3bc> + 1004f48: 00bfffc4 movi r2,-1 + 1004f4c: 9880e226 beq r19,r2,10052d8 <___vfprintf_internal_r+0x1d6c> + 1004f50: d9414d17 ldw r5,1332(sp) + 1004f54: 008019c4 movi r2,103 + 1004f58: 2880dc26 beq r5,r2,10052cc <___vfprintf_internal_r+0x1d60> + 1004f5c: 008011c4 movi r2,71 + 1004f60: 2880da26 beq r5,r2,10052cc <___vfprintf_internal_r+0x1d60> + 1004f64: d9414c17 ldw r5,1328(sp) + 1004f68: d9014317 ldw r4,1292(sp) + 1004f6c: d9814217 ldw r6,1288(sp) + 1004f70: 29404014 ori r5,r5,256 + 1004f74: d9414c15 stw r5,1328(sp) + 1004f78: 2000cc16 blt r4,zero,10052ac <___vfprintf_internal_r+0x1d40> + 1004f7c: 3021883a mov r16,r6 + 1004f80: 2023883a mov r17,r4 + 1004f84: 0039883a mov fp,zero + 1004f88: d9414d17 ldw r5,1332(sp) + 1004f8c: 00801984 movi r2,102 + 1004f90: 2880b726 beq r5,r2,1005270 <___vfprintf_internal_r+0x1d04> + 1004f94: 00801184 movi r2,70 + 1004f98: 2880b526 beq r5,r2,1005270 <___vfprintf_internal_r+0x1d04> + 1004f9c: 00801944 movi r2,101 + 1004fa0: 2880c826 beq r5,r2,10052c4 <___vfprintf_internal_r+0x1d58> + 1004fa4: 00801144 movi r2,69 + 1004fa8: 2880c626 beq r5,r2,10052c4 <___vfprintf_internal_r+0x1d58> + 1004fac: 9829883a mov r20,r19 + 1004fb0: d9014f17 ldw r4,1340(sp) + 1004fb4: d8800504 addi r2,sp,20 + 1004fb8: 880d883a mov r6,r17 + 1004fbc: d8800115 stw r2,4(sp) + 1004fc0: d8c00604 addi r3,sp,24 + 1004fc4: d8800704 addi r2,sp,28 + 1004fc8: 800b883a mov r5,r16 + 1004fcc: 01c00084 movi r7,2 + 1004fd0: d8c00215 stw r3,8(sp) + 1004fd4: d8800315 stw r2,12(sp) + 1004fd8: dd000015 stw r20,0(sp) + 1004fdc: 10057900 call 1005790 <_dtoa_r> + 1004fe0: d9814d17 ldw r6,1332(sp) + 1004fe4: d8814115 stw r2,1284(sp) + 1004fe8: 008019c4 movi r2,103 + 1004fec: 30809526 beq r6,r2,1005244 <___vfprintf_internal_r+0x1cd8> + 1004ff0: d8c14d17 ldw r3,1332(sp) + 1004ff4: 008011c4 movi r2,71 + 1004ff8: 18809226 beq r3,r2,1005244 <___vfprintf_internal_r+0x1cd8> + 1004ffc: d9414117 ldw r5,1284(sp) + 1005000: d9814d17 ldw r6,1332(sp) + 1005004: 00801984 movi r2,102 + 1005008: 2d25883a add r18,r5,r20 + 100500c: 30808626 beq r6,r2,1005228 <___vfprintf_internal_r+0x1cbc> + 1005010: 00801184 movi r2,70 + 1005014: 30808426 beq r6,r2,1005228 <___vfprintf_internal_r+0x1cbc> + 1005018: 000d883a mov r6,zero + 100501c: 000f883a mov r7,zero + 1005020: 880b883a mov r5,r17 + 1005024: 8009883a mov r4,r16 + 1005028: 100b4ec0 call 100b4ec <__eqdf2> + 100502c: 1000751e bne r2,zero,1005204 <___vfprintf_internal_r+0x1c98> + 1005030: 9005883a mov r2,r18 + 1005034: dc800715 stw r18,28(sp) + 1005038: d9014117 ldw r4,1284(sp) + 100503c: d9414d17 ldw r5,1332(sp) + 1005040: 00c019c4 movi r3,103 + 1005044: 1125c83a sub r18,r2,r4 + 1005048: 28c06826 beq r5,r3,10051ec <___vfprintf_internal_r+0x1c80> + 100504c: 008011c4 movi r2,71 + 1005050: 28806626 beq r5,r2,10051ec <___vfprintf_internal_r+0x1c80> + 1005054: d9000517 ldw r4,20(sp) + 1005058: d8c14d17 ldw r3,1332(sp) + 100505c: 00801944 movi r2,101 + 1005060: 10c05516 blt r2,r3,10051b8 <___vfprintf_internal_r+0x1c4c> + 1005064: 213fffc4 addi r4,r4,-1 + 1005068: d9000515 stw r4,20(sp) + 100506c: d8c00805 stb r3,32(sp) + 1005070: 2021883a mov r16,r4 + 1005074: 2000c116 blt r4,zero,100537c <___vfprintf_internal_r+0x1e10> + 1005078: 00800ac4 movi r2,43 + 100507c: d8800845 stb r2,33(sp) + 1005080: 00800244 movi r2,9 + 1005084: 1400af0e bge r2,r16,1005344 <___vfprintf_internal_r+0x1dd8> + 1005088: 1027883a mov r19,r2 + 100508c: dc400b84 addi r17,sp,46 + 1005090: 8009883a mov r4,r16 + 1005094: 01400284 movi r5,10 + 1005098: 100bbd40 call 100bbd4 <__modsi3> + 100509c: 10800c04 addi r2,r2,48 + 10050a0: 8c7fffc4 addi r17,r17,-1 + 10050a4: 8009883a mov r4,r16 + 10050a8: 01400284 movi r5,10 + 10050ac: 88800005 stb r2,0(r17) + 10050b0: 100bb740 call 100bb74 <__divsi3> + 10050b4: 1021883a mov r16,r2 + 10050b8: 98bff516 blt r19,r2,1005090 <___vfprintf_internal_r+0x1b24> + 10050bc: 10c00c04 addi r3,r2,48 + 10050c0: d88009c4 addi r2,sp,39 + 10050c4: 108001c4 addi r2,r2,7 + 10050c8: 897fffc4 addi r5,r17,-1 + 10050cc: 88ffffc5 stb r3,-1(r17) + 10050d0: 2880a72e bgeu r5,r2,1005370 <___vfprintf_internal_r+0x1e04> + 10050d4: 1009883a mov r4,r2 + 10050d8: d9800804 addi r6,sp,32 + 10050dc: d8c00884 addi r3,sp,34 + 10050e0: 28800003 ldbu r2,0(r5) + 10050e4: 29400044 addi r5,r5,1 + 10050e8: 18800005 stb r2,0(r3) + 10050ec: 18c00044 addi r3,r3,1 + 10050f0: 293ffb36 bltu r5,r4,10050e0 <___vfprintf_internal_r+0x1b74> + 10050f4: 1987c83a sub r3,r3,r6 + 10050f8: 00800044 movi r2,1 + 10050fc: d8c14815 stw r3,1312(sp) + 1005100: 90cf883a add r7,r18,r3 + 1005104: 1480960e bge r2,r18,1005360 <___vfprintf_internal_r+0x1df4> + 1005108: 39c00044 addi r7,r7,1 + 100510c: d9c14515 stw r7,1300(sp) + 1005110: 38003416 blt r7,zero,10051e4 <___vfprintf_internal_r+0x1c78> + 1005114: e0803fcc andi r2,fp,255 + 1005118: 1080201c xori r2,r2,128 + 100511c: 10bfe004 addi r2,r2,-128 + 1005120: 10004e26 beq r2,zero,100525c <___vfprintf_internal_r+0x1cf0> + 1005124: 00800b44 movi r2,45 + 1005128: dc814715 stw r18,1308(sp) + 100512c: d8014615 stw zero,1304(sp) + 1005130: d8800405 stb r2,16(sp) + 1005134: 003bb106 br 1003ffc <___vfprintf_internal_r+0xa90> + 1005138: 00800b44 movi r2,45 + 100513c: d8800405 stb r2,16(sp) + 1005140: 003d3306 br 1004610 <___vfprintf_internal_r+0x10a4> + 1005144: d9014f17 ldw r4,1340(sp) + 1005148: b00b883a mov r5,r22 + 100514c: d9800c04 addi r6,sp,48 + 1005150: 10035140 call 1003514 <__sprint_r> + 1005154: 103abd1e bne r2,zero,1003c4c <___vfprintf_internal_r+0x6e0> + 1005158: 003abb06 br 1003c48 <___vfprintf_internal_r+0x6dc> + 100515c: 38800017 ldw r2,0(r7) + 1005160: 39c00104 addi r7,r7,4 + 1005164: d9c14015 stw r7,1280(sp) + 1005168: d9414b17 ldw r5,1324(sp) + 100516c: d9c14017 ldw r7,1280(sp) + 1005170: 11400015 stw r5,0(r2) + 1005174: 00395906 br 10036dc <___vfprintf_internal_r+0x170> + 1005178: 980f883a mov r7,r19 + 100517c: dcc14515 stw r19,1300(sp) + 1005180: d8014615 stw zero,1304(sp) + 1005184: 003b9b06 br 1003ff4 <___vfprintf_internal_r+0xa88> + 1005188: 0027883a mov r19,zero + 100518c: 00397806 br 1003770 <___vfprintf_internal_r+0x204> + 1005190: 00c040b4 movhi r3,258 + 1005194: 18e37404 addi r3,r3,-29232 + 1005198: 100f883a mov r7,r2 + 100519c: d8814515 stw r2,1300(sp) + 10051a0: d8c14115 stw r3,1284(sp) + 10051a4: 0039e006 br 1003928 <___vfprintf_internal_r+0x3bc> + 10051a8: 008040b4 movhi r2,258 + 10051ac: 10a37304 addi r2,r2,-29236 + 10051b0: d8814115 stw r2,1284(sp) + 10051b4: 003d1c06 br 1004628 <___vfprintf_internal_r+0x10bc> + 10051b8: d9414d17 ldw r5,1332(sp) + 10051bc: 00801984 movi r2,102 + 10051c0: 28804926 beq r5,r2,10052e8 <___vfprintf_internal_r+0x1d7c> + 10051c4: 200f883a mov r7,r4 + 10051c8: 24805716 blt r4,r18,1005328 <___vfprintf_internal_r+0x1dbc> + 10051cc: d9414c17 ldw r5,1328(sp) + 10051d0: 2880004c andi r2,r5,1 + 10051d4: 10000126 beq r2,zero,10051dc <___vfprintf_internal_r+0x1c70> + 10051d8: 21c00044 addi r7,r4,1 + 10051dc: d9c14515 stw r7,1300(sp) + 10051e0: 383fcc0e bge r7,zero,1005114 <___vfprintf_internal_r+0x1ba8> + 10051e4: d8014515 stw zero,1300(sp) + 10051e8: 003fca06 br 1005114 <___vfprintf_internal_r+0x1ba8> + 10051ec: d9000517 ldw r4,20(sp) + 10051f0: 00bfff04 movi r2,-4 + 10051f4: 1100480e bge r2,r4,1005318 <___vfprintf_internal_r+0x1dac> + 10051f8: 99004716 blt r19,r4,1005318 <___vfprintf_internal_r+0x1dac> + 10051fc: d8c14d15 stw r3,1332(sp) + 1005200: 003ff006 br 10051c4 <___vfprintf_internal_r+0x1c58> + 1005204: d8800717 ldw r2,28(sp) + 1005208: 14bf8b2e bgeu r2,r18,1005038 <___vfprintf_internal_r+0x1acc> + 100520c: 9007883a mov r3,r18 + 1005210: 01000c04 movi r4,48 + 1005214: 11000005 stb r4,0(r2) + 1005218: 10800044 addi r2,r2,1 + 100521c: d8800715 stw r2,28(sp) + 1005220: 18bffc1e bne r3,r2,1005214 <___vfprintf_internal_r+0x1ca8> + 1005224: 003f8406 br 1005038 <___vfprintf_internal_r+0x1acc> + 1005228: d8814117 ldw r2,1284(sp) + 100522c: 10c00007 ldb r3,0(r2) + 1005230: 00800c04 movi r2,48 + 1005234: 18805b26 beq r3,r2,10053a4 <___vfprintf_internal_r+0x1e38> + 1005238: d9000517 ldw r4,20(sp) + 100523c: 9125883a add r18,r18,r4 + 1005240: 003f7506 br 1005018 <___vfprintf_internal_r+0x1aac> + 1005244: d9014c17 ldw r4,1328(sp) + 1005248: 2080004c andi r2,r4,1 + 100524c: 1005003a cmpeq r2,r2,zero + 1005250: 103f6a26 beq r2,zero,1004ffc <___vfprintf_internal_r+0x1a90> + 1005254: d8800717 ldw r2,28(sp) + 1005258: 003f7706 br 1005038 <___vfprintf_internal_r+0x1acc> + 100525c: d9c14515 stw r7,1300(sp) + 1005260: 38004d16 blt r7,zero,1005398 <___vfprintf_internal_r+0x1e2c> + 1005264: dc814715 stw r18,1308(sp) + 1005268: d8014615 stw zero,1304(sp) + 100526c: 003b6106 br 1003ff4 <___vfprintf_internal_r+0xa88> + 1005270: d9014f17 ldw r4,1340(sp) + 1005274: d8800504 addi r2,sp,20 + 1005278: d8800115 stw r2,4(sp) + 100527c: d8c00604 addi r3,sp,24 + 1005280: d8800704 addi r2,sp,28 + 1005284: 800b883a mov r5,r16 + 1005288: 880d883a mov r6,r17 + 100528c: 01c000c4 movi r7,3 + 1005290: d8c00215 stw r3,8(sp) + 1005294: d8800315 stw r2,12(sp) + 1005298: dcc00015 stw r19,0(sp) + 100529c: 9829883a mov r20,r19 + 10052a0: 10057900 call 1005790 <_dtoa_r> + 10052a4: d8814115 stw r2,1284(sp) + 10052a8: 003f5106 br 1004ff0 <___vfprintf_internal_r+0x1a84> + 10052ac: d8c14217 ldw r3,1288(sp) + 10052b0: d9014317 ldw r4,1292(sp) + 10052b4: 07000b44 movi fp,45 + 10052b8: 1821883a mov r16,r3 + 10052bc: 2460003c xorhi r17,r4,32768 + 10052c0: 003f3106 br 1004f88 <___vfprintf_internal_r+0x1a1c> + 10052c4: 9d000044 addi r20,r19,1 + 10052c8: 003f3906 br 1004fb0 <___vfprintf_internal_r+0x1a44> + 10052cc: 983f251e bne r19,zero,1004f64 <___vfprintf_internal_r+0x19f8> + 10052d0: 04c00044 movi r19,1 + 10052d4: 003f2306 br 1004f64 <___vfprintf_internal_r+0x19f8> + 10052d8: 04c00184 movi r19,6 + 10052dc: 003f2106 br 1004f64 <___vfprintf_internal_r+0x19f8> + 10052e0: d8014515 stw zero,1300(sp) + 10052e4: 003eee06 br 1004ea0 <___vfprintf_internal_r+0x1934> + 10052e8: 200f883a mov r7,r4 + 10052ec: 0100370e bge zero,r4,10053cc <___vfprintf_internal_r+0x1e60> + 10052f0: 9800031e bne r19,zero,1005300 <___vfprintf_internal_r+0x1d94> + 10052f4: d9814c17 ldw r6,1328(sp) + 10052f8: 3080004c andi r2,r6,1 + 10052fc: 103fb726 beq r2,zero,10051dc <___vfprintf_internal_r+0x1c70> + 1005300: 20800044 addi r2,r4,1 + 1005304: 98a7883a add r19,r19,r2 + 1005308: dcc14515 stw r19,1300(sp) + 100530c: 980f883a mov r7,r19 + 1005310: 983f800e bge r19,zero,1005114 <___vfprintf_internal_r+0x1ba8> + 1005314: 003fb306 br 10051e4 <___vfprintf_internal_r+0x1c78> + 1005318: d9814d17 ldw r6,1332(sp) + 100531c: 31bfff84 addi r6,r6,-2 + 1005320: d9814d15 stw r6,1332(sp) + 1005324: 003f4c06 br 1005058 <___vfprintf_internal_r+0x1aec> + 1005328: 0100180e bge zero,r4,100538c <___vfprintf_internal_r+0x1e20> + 100532c: 00800044 movi r2,1 + 1005330: 1485883a add r2,r2,r18 + 1005334: d8814515 stw r2,1300(sp) + 1005338: 100f883a mov r7,r2 + 100533c: 103f750e bge r2,zero,1005114 <___vfprintf_internal_r+0x1ba8> + 1005340: 003fa806 br 10051e4 <___vfprintf_internal_r+0x1c78> + 1005344: 80c00c04 addi r3,r16,48 + 1005348: 00800c04 movi r2,48 + 100534c: d8c008c5 stb r3,35(sp) + 1005350: d9800804 addi r6,sp,32 + 1005354: d8c00904 addi r3,sp,36 + 1005358: d8800885 stb r2,34(sp) + 100535c: 003f6506 br 10050f4 <___vfprintf_internal_r+0x1b88> + 1005360: d9014c17 ldw r4,1328(sp) + 1005364: 2084703a and r2,r4,r2 + 1005368: 103f9c26 beq r2,zero,10051dc <___vfprintf_internal_r+0x1c70> + 100536c: 003f6606 br 1005108 <___vfprintf_internal_r+0x1b9c> + 1005370: d9800804 addi r6,sp,32 + 1005374: d8c00884 addi r3,sp,34 + 1005378: 003f5e06 br 10050f4 <___vfprintf_internal_r+0x1b88> + 100537c: 00800b44 movi r2,45 + 1005380: 0121c83a sub r16,zero,r4 + 1005384: d8800845 stb r2,33(sp) + 1005388: 003f3d06 br 1005080 <___vfprintf_internal_r+0x1b14> + 100538c: 00800084 movi r2,2 + 1005390: 1105c83a sub r2,r2,r4 + 1005394: 003fe606 br 1005330 <___vfprintf_internal_r+0x1dc4> + 1005398: d8014515 stw zero,1300(sp) + 100539c: dc814715 stw r18,1308(sp) + 10053a0: 003fb106 br 1005268 <___vfprintf_internal_r+0x1cfc> + 10053a4: 000d883a mov r6,zero + 10053a8: 000f883a mov r7,zero + 10053ac: 8009883a mov r4,r16 + 10053b0: 880b883a mov r5,r17 + 10053b4: 100b5740 call 100b574 <__nedf2> + 10053b8: 103f9f26 beq r2,zero,1005238 <___vfprintf_internal_r+0x1ccc> + 10053bc: 00800044 movi r2,1 + 10053c0: 1509c83a sub r4,r2,r20 + 10053c4: d9000515 stw r4,20(sp) + 10053c8: 003f9b06 br 1005238 <___vfprintf_internal_r+0x1ccc> + 10053cc: 98000d1e bne r19,zero,1005404 <___vfprintf_internal_r+0x1e98> + 10053d0: d8c14c17 ldw r3,1328(sp) + 10053d4: 1880004c andi r2,r3,1 + 10053d8: 10000a1e bne r2,zero,1005404 <___vfprintf_internal_r+0x1e98> + 10053dc: 01000044 movi r4,1 + 10053e0: 200f883a mov r7,r4 + 10053e4: d9014515 stw r4,1300(sp) + 10053e8: 003f4a06 br 1005114 <___vfprintf_internal_r+0x1ba8> + 10053ec: 3cc00017 ldw r19,0(r7) + 10053f0: 39c00104 addi r7,r7,4 + 10053f4: 983d0e0e bge r19,zero,1004830 <___vfprintf_internal_r+0x12c4> + 10053f8: b8c00007 ldb r3,0(r23) + 10053fc: 04ffffc4 movi r19,-1 + 1005400: 0038d906 br 1003768 <___vfprintf_internal_r+0x1fc> + 1005404: 9cc00084 addi r19,r19,2 + 1005408: dcc14515 stw r19,1300(sp) + 100540c: 980f883a mov r7,r19 + 1005410: 983f400e bge r19,zero,1005114 <___vfprintf_internal_r+0x1ba8> + 1005414: 003f7306 br 10051e4 <___vfprintf_internal_r+0x1c78> + +01005418 <__vfprintf_internal>: + 1005418: 008040b4 movhi r2,258 + 100541c: 10ab9804 addi r2,r2,-20896 + 1005420: 2013883a mov r9,r4 + 1005424: 11000017 ldw r4,0(r2) + 1005428: 2805883a mov r2,r5 + 100542c: 300f883a mov r7,r6 + 1005430: 480b883a mov r5,r9 + 1005434: 100d883a mov r6,r2 + 1005438: 100356c1 jmpi 100356c <___vfprintf_internal_r> + +0100543c <__swsetup_r>: + 100543c: 008040b4 movhi r2,258 + 1005440: 10ab9804 addi r2,r2,-20896 + 1005444: 10c00017 ldw r3,0(r2) + 1005448: defffd04 addi sp,sp,-12 + 100544c: dc400115 stw r17,4(sp) + 1005450: dc000015 stw r16,0(sp) + 1005454: dfc00215 stw ra,8(sp) + 1005458: 2023883a mov r17,r4 + 100545c: 2821883a mov r16,r5 + 1005460: 18000226 beq r3,zero,100546c <__swsetup_r+0x30> + 1005464: 18800e17 ldw r2,56(r3) + 1005468: 10001f26 beq r2,zero,10054e8 <__swsetup_r+0xac> + 100546c: 8100030b ldhu r4,12(r16) + 1005470: 2080020c andi r2,r4,8 + 1005474: 10002826 beq r2,zero,1005518 <__swsetup_r+0xdc> + 1005478: 81400417 ldw r5,16(r16) + 100547c: 28001d26 beq r5,zero,10054f4 <__swsetup_r+0xb8> + 1005480: 2080004c andi r2,r4,1 + 1005484: 1005003a cmpeq r2,r2,zero + 1005488: 10000b26 beq r2,zero,10054b8 <__swsetup_r+0x7c> + 100548c: 2080008c andi r2,r4,2 + 1005490: 10001226 beq r2,zero,10054dc <__swsetup_r+0xa0> + 1005494: 0005883a mov r2,zero + 1005498: 80800215 stw r2,8(r16) + 100549c: 28000b26 beq r5,zero,10054cc <__swsetup_r+0x90> + 10054a0: 0005883a mov r2,zero + 10054a4: dfc00217 ldw ra,8(sp) + 10054a8: dc400117 ldw r17,4(sp) + 10054ac: dc000017 ldw r16,0(sp) + 10054b0: dec00304 addi sp,sp,12 + 10054b4: f800283a ret + 10054b8: 80800517 ldw r2,20(r16) + 10054bc: 80000215 stw zero,8(r16) + 10054c0: 0085c83a sub r2,zero,r2 + 10054c4: 80800615 stw r2,24(r16) + 10054c8: 283ff51e bne r5,zero,10054a0 <__swsetup_r+0x64> + 10054cc: 2080200c andi r2,r4,128 + 10054d0: 103ff326 beq r2,zero,10054a0 <__swsetup_r+0x64> + 10054d4: 00bfffc4 movi r2,-1 + 10054d8: 003ff206 br 10054a4 <__swsetup_r+0x68> + 10054dc: 80800517 ldw r2,20(r16) + 10054e0: 80800215 stw r2,8(r16) + 10054e4: 003fed06 br 100549c <__swsetup_r+0x60> + 10054e8: 1809883a mov r4,r3 + 10054ec: 1006fdc0 call 1006fdc <__sinit> + 10054f0: 003fde06 br 100546c <__swsetup_r+0x30> + 10054f4: 20c0a00c andi r3,r4,640 + 10054f8: 00808004 movi r2,512 + 10054fc: 18bfe026 beq r3,r2,1005480 <__swsetup_r+0x44> + 1005500: 8809883a mov r4,r17 + 1005504: 800b883a mov r5,r16 + 1005508: 1007d540 call 1007d54 <__smakebuf_r> + 100550c: 8100030b ldhu r4,12(r16) + 1005510: 81400417 ldw r5,16(r16) + 1005514: 003fda06 br 1005480 <__swsetup_r+0x44> + 1005518: 2080040c andi r2,r4,16 + 100551c: 103fed26 beq r2,zero,10054d4 <__swsetup_r+0x98> + 1005520: 2080010c andi r2,r4,4 + 1005524: 10001226 beq r2,zero,1005570 <__swsetup_r+0x134> + 1005528: 81400c17 ldw r5,48(r16) + 100552c: 28000526 beq r5,zero,1005544 <__swsetup_r+0x108> + 1005530: 80801004 addi r2,r16,64 + 1005534: 28800226 beq r5,r2,1005540 <__swsetup_r+0x104> + 1005538: 8809883a mov r4,r17 + 100553c: 10073600 call 1007360 <_free_r> + 1005540: 80000c15 stw zero,48(r16) + 1005544: 8080030b ldhu r2,12(r16) + 1005548: 81400417 ldw r5,16(r16) + 100554c: 80000115 stw zero,4(r16) + 1005550: 10bff6cc andi r2,r2,65499 + 1005554: 8080030d sth r2,12(r16) + 1005558: 81400015 stw r5,0(r16) + 100555c: 8080030b ldhu r2,12(r16) + 1005560: 10800214 ori r2,r2,8 + 1005564: 113fffcc andi r4,r2,65535 + 1005568: 8080030d sth r2,12(r16) + 100556c: 003fc306 br 100547c <__swsetup_r+0x40> + 1005570: 81400417 ldw r5,16(r16) + 1005574: 003ff906 br 100555c <__swsetup_r+0x120> + +01005578 : + 1005578: 28c00417 ldw r3,16(r5) + 100557c: 20800417 ldw r2,16(r4) + 1005580: defff604 addi sp,sp,-40 + 1005584: ddc00715 stw r23,28(sp) + 1005588: dd400515 stw r21,20(sp) + 100558c: dfc00915 stw ra,36(sp) + 1005590: df000815 stw fp,32(sp) + 1005594: dd800615 stw r22,24(sp) + 1005598: dd000415 stw r20,16(sp) + 100559c: dcc00315 stw r19,12(sp) + 10055a0: dc800215 stw r18,8(sp) + 10055a4: dc400115 stw r17,4(sp) + 10055a8: dc000015 stw r16,0(sp) + 10055ac: 202f883a mov r23,r4 + 10055b0: 282b883a mov r21,r5 + 10055b4: 10c07416 blt r2,r3,1005788 + 10055b8: 1c7fffc4 addi r17,r3,-1 + 10055bc: 8c45883a add r2,r17,r17 + 10055c0: 1085883a add r2,r2,r2 + 10055c4: 2c000504 addi r16,r5,20 + 10055c8: 24c00504 addi r19,r4,20 + 10055cc: 14ed883a add r22,r2,r19 + 10055d0: 80a5883a add r18,r16,r2 + 10055d4: b7000017 ldw fp,0(r22) + 10055d8: 91400017 ldw r5,0(r18) + 10055dc: e009883a mov r4,fp + 10055e0: 29400044 addi r5,r5,1 + 10055e4: 100bc340 call 100bc34 <__udivsi3> + 10055e8: 1029883a mov r20,r2 + 10055ec: 10003c1e bne r2,zero,10056e0 + 10055f0: a80b883a mov r5,r21 + 10055f4: b809883a mov r4,r23 + 10055f8: 10082a80 call 10082a8 <__mcmp> + 10055fc: 10002b16 blt r2,zero,10056ac + 1005600: a5000044 addi r20,r20,1 + 1005604: 980f883a mov r7,r19 + 1005608: 0011883a mov r8,zero + 100560c: 0009883a mov r4,zero + 1005610: 81400017 ldw r5,0(r16) + 1005614: 38c00017 ldw r3,0(r7) + 1005618: 84000104 addi r16,r16,4 + 100561c: 28bfffcc andi r2,r5,65535 + 1005620: 2085883a add r2,r4,r2 + 1005624: 11bfffcc andi r6,r2,65535 + 1005628: 193fffcc andi r4,r3,65535 + 100562c: 1004d43a srli r2,r2,16 + 1005630: 280ad43a srli r5,r5,16 + 1005634: 2189c83a sub r4,r4,r6 + 1005638: 2209883a add r4,r4,r8 + 100563c: 1806d43a srli r3,r3,16 + 1005640: 288b883a add r5,r5,r2 + 1005644: 200dd43a srai r6,r4,16 + 1005648: 28bfffcc andi r2,r5,65535 + 100564c: 1887c83a sub r3,r3,r2 + 1005650: 1987883a add r3,r3,r6 + 1005654: 3900000d sth r4,0(r7) + 1005658: 38c0008d sth r3,2(r7) + 100565c: 2808d43a srli r4,r5,16 + 1005660: 39c00104 addi r7,r7,4 + 1005664: 1811d43a srai r8,r3,16 + 1005668: 943fe92e bgeu r18,r16,1005610 + 100566c: 8c45883a add r2,r17,r17 + 1005670: 1085883a add r2,r2,r2 + 1005674: 9885883a add r2,r19,r2 + 1005678: 10c00017 ldw r3,0(r2) + 100567c: 18000b1e bne r3,zero,10056ac + 1005680: 113fff04 addi r4,r2,-4 + 1005684: 9900082e bgeu r19,r4,10056a8 + 1005688: 10bfff17 ldw r2,-4(r2) + 100568c: 10000326 beq r2,zero,100569c + 1005690: 00000506 br 10056a8 + 1005694: 20800017 ldw r2,0(r4) + 1005698: 1000031e bne r2,zero,10056a8 + 100569c: 213fff04 addi r4,r4,-4 + 10056a0: 8c7fffc4 addi r17,r17,-1 + 10056a4: 993ffb36 bltu r19,r4,1005694 + 10056a8: bc400415 stw r17,16(r23) + 10056ac: a005883a mov r2,r20 + 10056b0: dfc00917 ldw ra,36(sp) + 10056b4: df000817 ldw fp,32(sp) + 10056b8: ddc00717 ldw r23,28(sp) + 10056bc: dd800617 ldw r22,24(sp) + 10056c0: dd400517 ldw r21,20(sp) + 10056c4: dd000417 ldw r20,16(sp) + 10056c8: dcc00317 ldw r19,12(sp) + 10056cc: dc800217 ldw r18,8(sp) + 10056d0: dc400117 ldw r17,4(sp) + 10056d4: dc000017 ldw r16,0(sp) + 10056d8: dec00a04 addi sp,sp,40 + 10056dc: f800283a ret + 10056e0: 980f883a mov r7,r19 + 10056e4: 8011883a mov r8,r16 + 10056e8: 0013883a mov r9,zero + 10056ec: 000d883a mov r6,zero + 10056f0: 40c00017 ldw r3,0(r8) + 10056f4: 39000017 ldw r4,0(r7) + 10056f8: 42000104 addi r8,r8,4 + 10056fc: 18bfffcc andi r2,r3,65535 + 1005700: a085383a mul r2,r20,r2 + 1005704: 1806d43a srli r3,r3,16 + 1005708: 217fffcc andi r5,r4,65535 + 100570c: 3085883a add r2,r6,r2 + 1005710: 11bfffcc andi r6,r2,65535 + 1005714: a0c7383a mul r3,r20,r3 + 1005718: 1004d43a srli r2,r2,16 + 100571c: 298bc83a sub r5,r5,r6 + 1005720: 2a4b883a add r5,r5,r9 + 1005724: 2008d43a srli r4,r4,16 + 1005728: 1887883a add r3,r3,r2 + 100572c: 280dd43a srai r6,r5,16 + 1005730: 18bfffcc andi r2,r3,65535 + 1005734: 2089c83a sub r4,r4,r2 + 1005738: 2189883a add r4,r4,r6 + 100573c: 3900008d sth r4,2(r7) + 1005740: 3940000d sth r5,0(r7) + 1005744: 180cd43a srli r6,r3,16 + 1005748: 39c00104 addi r7,r7,4 + 100574c: 2013d43a srai r9,r4,16 + 1005750: 923fe72e bgeu r18,r8,10056f0 + 1005754: e03fa61e bne fp,zero,10055f0 + 1005758: b0ffff04 addi r3,r22,-4 + 100575c: 98c0082e bgeu r19,r3,1005780 + 1005760: b0bfff17 ldw r2,-4(r22) + 1005764: 10000326 beq r2,zero,1005774 + 1005768: 00000506 br 1005780 + 100576c: 18800017 ldw r2,0(r3) + 1005770: 1000031e bne r2,zero,1005780 + 1005774: 18ffff04 addi r3,r3,-4 + 1005778: 8c7fffc4 addi r17,r17,-1 + 100577c: 98fffb36 bltu r19,r3,100576c + 1005780: bc400415 stw r17,16(r23) + 1005784: 003f9a06 br 10055f0 + 1005788: 0005883a mov r2,zero + 100578c: 003fc806 br 10056b0 + +01005790 <_dtoa_r>: + 1005790: 22001017 ldw r8,64(r4) + 1005794: deffda04 addi sp,sp,-152 + 1005798: dd402115 stw r21,132(sp) + 100579c: dd002015 stw r20,128(sp) + 10057a0: dc801e15 stw r18,120(sp) + 10057a4: dc401d15 stw r17,116(sp) + 10057a8: dfc02515 stw ra,148(sp) + 10057ac: df002415 stw fp,144(sp) + 10057b0: ddc02315 stw r23,140(sp) + 10057b4: dd802215 stw r22,136(sp) + 10057b8: dcc01f15 stw r19,124(sp) + 10057bc: dc001c15 stw r16,112(sp) + 10057c0: d9001615 stw r4,88(sp) + 10057c4: 3023883a mov r17,r6 + 10057c8: 2829883a mov r20,r5 + 10057cc: d9c01715 stw r7,92(sp) + 10057d0: dc802817 ldw r18,160(sp) + 10057d4: 302b883a mov r21,r6 + 10057d8: 40000a26 beq r8,zero,1005804 <_dtoa_r+0x74> + 10057dc: 20801117 ldw r2,68(r4) + 10057e0: 400b883a mov r5,r8 + 10057e4: 40800115 stw r2,4(r8) + 10057e8: 20c01117 ldw r3,68(r4) + 10057ec: 00800044 movi r2,1 + 10057f0: 10c4983a sll r2,r2,r3 + 10057f4: 40800215 stw r2,8(r8) + 10057f8: 100814c0 call 100814c <_Bfree> + 10057fc: d8c01617 ldw r3,88(sp) + 1005800: 18001015 stw zero,64(r3) + 1005804: 8800a316 blt r17,zero,1005a94 <_dtoa_r+0x304> + 1005808: 90000015 stw zero,0(r18) + 100580c: a8dffc2c andhi r3,r21,32752 + 1005810: 009ffc34 movhi r2,32752 + 1005814: 18809126 beq r3,r2,1005a5c <_dtoa_r+0x2cc> + 1005818: 000d883a mov r6,zero + 100581c: 000f883a mov r7,zero + 1005820: a009883a mov r4,r20 + 1005824: a80b883a mov r5,r21 + 1005828: dd001215 stw r20,72(sp) + 100582c: dd401315 stw r21,76(sp) + 1005830: 100b5740 call 100b574 <__nedf2> + 1005834: 1000171e bne r2,zero,1005894 <_dtoa_r+0x104> + 1005838: d9802717 ldw r6,156(sp) + 100583c: 00800044 movi r2,1 + 1005840: 30800015 stw r2,0(r6) + 1005844: d8802917 ldw r2,164(sp) + 1005848: 10029b26 beq r2,zero,10062b8 <_dtoa_r+0xb28> + 100584c: d9002917 ldw r4,164(sp) + 1005850: 008040b4 movhi r2,258 + 1005854: 10a38244 addi r2,r2,-29175 + 1005858: 10ffffc4 addi r3,r2,-1 + 100585c: 20800015 stw r2,0(r4) + 1005860: 1805883a mov r2,r3 + 1005864: dfc02517 ldw ra,148(sp) + 1005868: df002417 ldw fp,144(sp) + 100586c: ddc02317 ldw r23,140(sp) + 1005870: dd802217 ldw r22,136(sp) + 1005874: dd402117 ldw r21,132(sp) + 1005878: dd002017 ldw r20,128(sp) + 100587c: dcc01f17 ldw r19,124(sp) + 1005880: dc801e17 ldw r18,120(sp) + 1005884: dc401d17 ldw r17,116(sp) + 1005888: dc001c17 ldw r16,112(sp) + 100588c: dec02604 addi sp,sp,152 + 1005890: f800283a ret + 1005894: d9001617 ldw r4,88(sp) + 1005898: d9401217 ldw r5,72(sp) + 100589c: d8800104 addi r2,sp,4 + 10058a0: a80d883a mov r6,r21 + 10058a4: d9c00204 addi r7,sp,8 + 10058a8: d8800015 stw r2,0(sp) + 10058ac: 10087880 call 1008788 <__d2b> + 10058b0: d8800715 stw r2,28(sp) + 10058b4: a804d53a srli r2,r21,20 + 10058b8: 1101ffcc andi r4,r2,2047 + 10058bc: 20008626 beq r4,zero,1005ad8 <_dtoa_r+0x348> + 10058c0: d8c01217 ldw r3,72(sp) + 10058c4: 00800434 movhi r2,16 + 10058c8: 10bfffc4 addi r2,r2,-1 + 10058cc: ddc00117 ldw r23,4(sp) + 10058d0: a884703a and r2,r21,r2 + 10058d4: 1811883a mov r8,r3 + 10058d8: 124ffc34 orhi r9,r2,16368 + 10058dc: 25bf0044 addi r22,r4,-1023 + 10058e0: d8000815 stw zero,32(sp) + 10058e4: 0005883a mov r2,zero + 10058e8: 00cffe34 movhi r3,16376 + 10058ec: 480b883a mov r5,r9 + 10058f0: 4009883a mov r4,r8 + 10058f4: 180f883a mov r7,r3 + 10058f8: 100d883a mov r6,r2 + 10058fc: 100addc0 call 100addc <__subdf3> + 1005900: 0218dbf4 movhi r8,25455 + 1005904: 4210d844 addi r8,r8,17249 + 1005908: 024ff4f4 movhi r9,16339 + 100590c: 4a61e9c4 addi r9,r9,-30809 + 1005910: 480f883a mov r7,r9 + 1005914: 400d883a mov r6,r8 + 1005918: 180b883a mov r5,r3 + 100591c: 1009883a mov r4,r2 + 1005920: 100aed00 call 100aed0 <__muldf3> + 1005924: 0222d874 movhi r8,35681 + 1005928: 42322cc4 addi r8,r8,-14157 + 100592c: 024ff1f4 movhi r9,16327 + 1005930: 4a628a04 addi r9,r9,-30168 + 1005934: 480f883a mov r7,r9 + 1005938: 400d883a mov r6,r8 + 100593c: 180b883a mov r5,r3 + 1005940: 1009883a mov r4,r2 + 1005944: 100ae5c0 call 100ae5c <__adddf3> + 1005948: b009883a mov r4,r22 + 100594c: 1021883a mov r16,r2 + 1005950: 1823883a mov r17,r3 + 1005954: 100b7940 call 100b794 <__floatsidf> + 1005958: 021427f4 movhi r8,20639 + 100595c: 421e7ec4 addi r8,r8,31227 + 1005960: 024ff4f4 movhi r9,16339 + 1005964: 4a5104c4 addi r9,r9,17427 + 1005968: 480f883a mov r7,r9 + 100596c: 400d883a mov r6,r8 + 1005970: 180b883a mov r5,r3 + 1005974: 1009883a mov r4,r2 + 1005978: 100aed00 call 100aed0 <__muldf3> + 100597c: 180f883a mov r7,r3 + 1005980: 880b883a mov r5,r17 + 1005984: 100d883a mov r6,r2 + 1005988: 8009883a mov r4,r16 + 100598c: 100ae5c0 call 100ae5c <__adddf3> + 1005990: 1009883a mov r4,r2 + 1005994: 180b883a mov r5,r3 + 1005998: 1021883a mov r16,r2 + 100599c: 1823883a mov r17,r3 + 10059a0: 100b88c0 call 100b88c <__fixdfsi> + 10059a4: 000d883a mov r6,zero + 10059a8: 000f883a mov r7,zero + 10059ac: 8009883a mov r4,r16 + 10059b0: 880b883a mov r5,r17 + 10059b4: d8800d15 stw r2,52(sp) + 10059b8: 100b70c0 call 100b70c <__ltdf2> + 10059bc: 10031716 blt r2,zero,100661c <_dtoa_r+0xe8c> + 10059c0: d8c00d17 ldw r3,52(sp) + 10059c4: 00800584 movi r2,22 + 10059c8: 10c1482e bgeu r2,r3,1005eec <_dtoa_r+0x75c> + 10059cc: 01000044 movi r4,1 + 10059d0: d9000c15 stw r4,48(sp) + 10059d4: bd85c83a sub r2,r23,r22 + 10059d8: 11bfffc4 addi r6,r2,-1 + 10059dc: 30030b16 blt r6,zero,100660c <_dtoa_r+0xe7c> + 10059e0: d9800a15 stw r6,40(sp) + 10059e4: d8001115 stw zero,68(sp) + 10059e8: d8c00d17 ldw r3,52(sp) + 10059ec: 1802ff16 blt r3,zero,10065ec <_dtoa_r+0xe5c> + 10059f0: d9000a17 ldw r4,40(sp) + 10059f4: d8c00915 stw r3,36(sp) + 10059f8: d8001015 stw zero,64(sp) + 10059fc: 20c9883a add r4,r4,r3 + 1005a00: d9000a15 stw r4,40(sp) + 1005a04: d9001717 ldw r4,92(sp) + 1005a08: 00800244 movi r2,9 + 1005a0c: 11004636 bltu r2,r4,1005b28 <_dtoa_r+0x398> + 1005a10: 00800144 movi r2,5 + 1005a14: 11020416 blt r2,r4,1006228 <_dtoa_r+0xa98> + 1005a18: 04400044 movi r17,1 + 1005a1c: d8c01717 ldw r3,92(sp) + 1005a20: 00800144 movi r2,5 + 1005a24: 10c1ed36 bltu r2,r3,10061dc <_dtoa_r+0xa4c> + 1005a28: 18c5883a add r2,r3,r3 + 1005a2c: 1085883a add r2,r2,r2 + 1005a30: 00c04034 movhi r3,256 + 1005a34: 18d69104 addi r3,r3,23108 + 1005a38: 10c5883a add r2,r2,r3 + 1005a3c: 11000017 ldw r4,0(r2) + 1005a40: 2000683a jmp r4 + 1005a44: 01005b30 cmpltui r4,zero,364 + 1005a48: 01005b30 cmpltui r4,zero,364 + 1005a4c: 01006530 cmpltui r4,zero,404 + 1005a50: 01006508 cmpgei r4,zero,404 + 1005a54: 0100654c andi r4,zero,405 + 1005a58: 01006558 cmpnei r4,zero,405 + 1005a5c: d9002717 ldw r4,156(sp) + 1005a60: 0089c3c4 movi r2,9999 + 1005a64: 20800015 stw r2,0(r4) + 1005a68: a0001026 beq r20,zero,1005aac <_dtoa_r+0x31c> + 1005a6c: 00c040b4 movhi r3,258 + 1005a70: 18e38e04 addi r3,r3,-29128 + 1005a74: d9802917 ldw r6,164(sp) + 1005a78: 303f7926 beq r6,zero,1005860 <_dtoa_r+0xd0> + 1005a7c: 188000c7 ldb r2,3(r3) + 1005a80: 190000c4 addi r4,r3,3 + 1005a84: 1000101e bne r2,zero,1005ac8 <_dtoa_r+0x338> + 1005a88: d8802917 ldw r2,164(sp) + 1005a8c: 11000015 stw r4,0(r2) + 1005a90: 003f7306 br 1005860 <_dtoa_r+0xd0> + 1005a94: 00a00034 movhi r2,32768 + 1005a98: 10bfffc4 addi r2,r2,-1 + 1005a9c: 00c00044 movi r3,1 + 1005aa0: 88aa703a and r21,r17,r2 + 1005aa4: 90c00015 stw r3,0(r18) + 1005aa8: 003f5806 br 100580c <_dtoa_r+0x7c> + 1005aac: 00800434 movhi r2,16 + 1005ab0: 10bfffc4 addi r2,r2,-1 + 1005ab4: a884703a and r2,r21,r2 + 1005ab8: 103fec1e bne r2,zero,1005a6c <_dtoa_r+0x2dc> + 1005abc: 00c040b4 movhi r3,258 + 1005ac0: 18e38b04 addi r3,r3,-29140 + 1005ac4: 003feb06 br 1005a74 <_dtoa_r+0x2e4> + 1005ac8: d8802917 ldw r2,164(sp) + 1005acc: 19000204 addi r4,r3,8 + 1005ad0: 11000015 stw r4,0(r2) + 1005ad4: 003f6206 br 1005860 <_dtoa_r+0xd0> + 1005ad8: ddc00117 ldw r23,4(sp) + 1005adc: d8800217 ldw r2,8(sp) + 1005ae0: 01000804 movi r4,32 + 1005ae4: b8c10c84 addi r3,r23,1074 + 1005ae8: 18a3883a add r17,r3,r2 + 1005aec: 2441b80e bge r4,r17,10061d0 <_dtoa_r+0xa40> + 1005af0: 00c01004 movi r3,64 + 1005af4: 1c47c83a sub r3,r3,r17 + 1005af8: 88bff804 addi r2,r17,-32 + 1005afc: a8c6983a sll r3,r21,r3 + 1005b00: a084d83a srl r2,r20,r2 + 1005b04: 1888b03a or r4,r3,r2 + 1005b08: 100b9640 call 100b964 <__floatunsidf> + 1005b0c: 1011883a mov r8,r2 + 1005b10: 00bf8434 movhi r2,65040 + 1005b14: 01000044 movi r4,1 + 1005b18: 10d3883a add r9,r2,r3 + 1005b1c: 8dbef344 addi r22,r17,-1075 + 1005b20: d9000815 stw r4,32(sp) + 1005b24: 003f6f06 br 10058e4 <_dtoa_r+0x154> + 1005b28: d8001715 stw zero,92(sp) + 1005b2c: 04400044 movi r17,1 + 1005b30: 00bfffc4 movi r2,-1 + 1005b34: 00c00044 movi r3,1 + 1005b38: d8800e15 stw r2,56(sp) + 1005b3c: d8002615 stw zero,152(sp) + 1005b40: d8800f15 stw r2,60(sp) + 1005b44: d8c00b15 stw r3,44(sp) + 1005b48: 1021883a mov r16,r2 + 1005b4c: d8801617 ldw r2,88(sp) + 1005b50: 10001115 stw zero,68(r2) + 1005b54: d8801617 ldw r2,88(sp) + 1005b58: 11401117 ldw r5,68(r2) + 1005b5c: 1009883a mov r4,r2 + 1005b60: 10086cc0 call 10086cc <_Balloc> + 1005b64: d8c01617 ldw r3,88(sp) + 1005b68: d8800515 stw r2,20(sp) + 1005b6c: 18801015 stw r2,64(r3) + 1005b70: 00800384 movi r2,14 + 1005b74: 14006836 bltu r2,r16,1005d18 <_dtoa_r+0x588> + 1005b78: 8805003a cmpeq r2,r17,zero + 1005b7c: 1000661e bne r2,zero,1005d18 <_dtoa_r+0x588> + 1005b80: d9000d17 ldw r4,52(sp) + 1005b84: 0102300e bge zero,r4,1006448 <_dtoa_r+0xcb8> + 1005b88: 208003cc andi r2,r4,15 + 1005b8c: 100490fa slli r2,r2,3 + 1005b90: 2025d13a srai r18,r4,4 + 1005b94: 00c040b4 movhi r3,258 + 1005b98: 18e3a004 addi r3,r3,-29056 + 1005b9c: 10c5883a add r2,r2,r3 + 1005ba0: 90c0040c andi r3,r18,16 + 1005ba4: 14000017 ldw r16,0(r2) + 1005ba8: 14400117 ldw r17,4(r2) + 1005bac: 18036a1e bne r3,zero,1006958 <_dtoa_r+0x11c8> + 1005bb0: 05800084 movi r22,2 + 1005bb4: 90001026 beq r18,zero,1005bf8 <_dtoa_r+0x468> + 1005bb8: 04c040b4 movhi r19,258 + 1005bbc: 9ce3d204 addi r19,r19,-28856 + 1005bc0: 9080004c andi r2,r18,1 + 1005bc4: 1005003a cmpeq r2,r2,zero + 1005bc8: 1000081e bne r2,zero,1005bec <_dtoa_r+0x45c> + 1005bcc: 99800017 ldw r6,0(r19) + 1005bd0: 99c00117 ldw r7,4(r19) + 1005bd4: 880b883a mov r5,r17 + 1005bd8: 8009883a mov r4,r16 + 1005bdc: 100aed00 call 100aed0 <__muldf3> + 1005be0: 1021883a mov r16,r2 + 1005be4: b5800044 addi r22,r22,1 + 1005be8: 1823883a mov r17,r3 + 1005bec: 9025d07a srai r18,r18,1 + 1005bf0: 9cc00204 addi r19,r19,8 + 1005bf4: 903ff21e bne r18,zero,1005bc0 <_dtoa_r+0x430> + 1005bf8: a80b883a mov r5,r21 + 1005bfc: a009883a mov r4,r20 + 1005c00: 880f883a mov r7,r17 + 1005c04: 800d883a mov r6,r16 + 1005c08: 100b2940 call 100b294 <__divdf3> + 1005c0c: 1029883a mov r20,r2 + 1005c10: 182b883a mov r21,r3 + 1005c14: d8c00c17 ldw r3,48(sp) + 1005c18: 1805003a cmpeq r2,r3,zero + 1005c1c: 1000081e bne r2,zero,1005c40 <_dtoa_r+0x4b0> + 1005c20: 0005883a mov r2,zero + 1005c24: 00cffc34 movhi r3,16368 + 1005c28: 180f883a mov r7,r3 + 1005c2c: a009883a mov r4,r20 + 1005c30: a80b883a mov r5,r21 + 1005c34: 100d883a mov r6,r2 + 1005c38: 100b70c0 call 100b70c <__ltdf2> + 1005c3c: 1003fe16 blt r2,zero,1006c38 <_dtoa_r+0x14a8> + 1005c40: b009883a mov r4,r22 + 1005c44: 100b7940 call 100b794 <__floatsidf> + 1005c48: 180b883a mov r5,r3 + 1005c4c: 1009883a mov r4,r2 + 1005c50: a00d883a mov r6,r20 + 1005c54: a80f883a mov r7,r21 + 1005c58: 100aed00 call 100aed0 <__muldf3> + 1005c5c: 0011883a mov r8,zero + 1005c60: 02500734 movhi r9,16412 + 1005c64: 1009883a mov r4,r2 + 1005c68: 180b883a mov r5,r3 + 1005c6c: 480f883a mov r7,r9 + 1005c70: 400d883a mov r6,r8 + 1005c74: 100ae5c0 call 100ae5c <__adddf3> + 1005c78: d9000f17 ldw r4,60(sp) + 1005c7c: 102d883a mov r22,r2 + 1005c80: 00bf3034 movhi r2,64704 + 1005c84: 18b9883a add fp,r3,r2 + 1005c88: e02f883a mov r23,fp + 1005c8c: 20028f1e bne r4,zero,10066cc <_dtoa_r+0xf3c> + 1005c90: 0005883a mov r2,zero + 1005c94: 00d00534 movhi r3,16404 + 1005c98: a009883a mov r4,r20 + 1005c9c: a80b883a mov r5,r21 + 1005ca0: 180f883a mov r7,r3 + 1005ca4: 100d883a mov r6,r2 + 1005ca8: 100addc0 call 100addc <__subdf3> + 1005cac: 1009883a mov r4,r2 + 1005cb0: e00f883a mov r7,fp + 1005cb4: 180b883a mov r5,r3 + 1005cb8: b00d883a mov r6,r22 + 1005cbc: 1025883a mov r18,r2 + 1005cc0: 1827883a mov r19,r3 + 1005cc4: 100b5fc0 call 100b5fc <__gtdf2> + 1005cc8: 00834f16 blt zero,r2,1006a08 <_dtoa_r+0x1278> + 1005ccc: e0e0003c xorhi r3,fp,32768 + 1005cd0: 9009883a mov r4,r18 + 1005cd4: 980b883a mov r5,r19 + 1005cd8: 180f883a mov r7,r3 + 1005cdc: b00d883a mov r6,r22 + 1005ce0: 100b70c0 call 100b70c <__ltdf2> + 1005ce4: 1000080e bge r2,zero,1005d08 <_dtoa_r+0x578> + 1005ce8: 0027883a mov r19,zero + 1005cec: 0025883a mov r18,zero + 1005cf0: d8802617 ldw r2,152(sp) + 1005cf4: df000517 ldw fp,20(sp) + 1005cf8: d8000615 stw zero,24(sp) + 1005cfc: 0084303a nor r2,zero,r2 + 1005d00: d8800d15 stw r2,52(sp) + 1005d04: 00019b06 br 1006374 <_dtoa_r+0xbe4> + 1005d08: d9801217 ldw r6,72(sp) + 1005d0c: d8801317 ldw r2,76(sp) + 1005d10: 3029883a mov r20,r6 + 1005d14: 102b883a mov r21,r2 + 1005d18: d8c00217 ldw r3,8(sp) + 1005d1c: 18008516 blt r3,zero,1005f34 <_dtoa_r+0x7a4> + 1005d20: d9000d17 ldw r4,52(sp) + 1005d24: 00800384 movi r2,14 + 1005d28: 11008216 blt r2,r4,1005f34 <_dtoa_r+0x7a4> + 1005d2c: 200490fa slli r2,r4,3 + 1005d30: d9802617 ldw r6,152(sp) + 1005d34: 00c040b4 movhi r3,258 + 1005d38: 18e3a004 addi r3,r3,-29056 + 1005d3c: 10c5883a add r2,r2,r3 + 1005d40: 14800017 ldw r18,0(r2) + 1005d44: 14c00117 ldw r19,4(r2) + 1005d48: 30031e16 blt r6,zero,10069c4 <_dtoa_r+0x1234> + 1005d4c: d9000517 ldw r4,20(sp) + 1005d50: d8c00f17 ldw r3,60(sp) + 1005d54: a823883a mov r17,r21 + 1005d58: a021883a mov r16,r20 + 1005d5c: 192b883a add r21,r3,r4 + 1005d60: 2039883a mov fp,r4 + 1005d64: 00000f06 br 1005da4 <_dtoa_r+0x614> + 1005d68: 0005883a mov r2,zero + 1005d6c: 00d00934 movhi r3,16420 + 1005d70: 5009883a mov r4,r10 + 1005d74: 580b883a mov r5,r11 + 1005d78: 180f883a mov r7,r3 + 1005d7c: 100d883a mov r6,r2 + 1005d80: 100aed00 call 100aed0 <__muldf3> + 1005d84: 180b883a mov r5,r3 + 1005d88: 000d883a mov r6,zero + 1005d8c: 000f883a mov r7,zero + 1005d90: 1009883a mov r4,r2 + 1005d94: 1021883a mov r16,r2 + 1005d98: 1823883a mov r17,r3 + 1005d9c: 100b5740 call 100b574 <__nedf2> + 1005da0: 10004526 beq r2,zero,1005eb8 <_dtoa_r+0x728> + 1005da4: 900d883a mov r6,r18 + 1005da8: 980f883a mov r7,r19 + 1005dac: 8009883a mov r4,r16 + 1005db0: 880b883a mov r5,r17 + 1005db4: 100b2940 call 100b294 <__divdf3> + 1005db8: 180b883a mov r5,r3 + 1005dbc: 1009883a mov r4,r2 + 1005dc0: 100b88c0 call 100b88c <__fixdfsi> + 1005dc4: 1009883a mov r4,r2 + 1005dc8: 1029883a mov r20,r2 + 1005dcc: 100b7940 call 100b794 <__floatsidf> + 1005dd0: 180f883a mov r7,r3 + 1005dd4: 9009883a mov r4,r18 + 1005dd8: 980b883a mov r5,r19 + 1005ddc: 100d883a mov r6,r2 + 1005de0: 100aed00 call 100aed0 <__muldf3> + 1005de4: 180f883a mov r7,r3 + 1005de8: 880b883a mov r5,r17 + 1005dec: 8009883a mov r4,r16 + 1005df0: 100d883a mov r6,r2 + 1005df4: 100addc0 call 100addc <__subdf3> + 1005df8: 1015883a mov r10,r2 + 1005dfc: a0800c04 addi r2,r20,48 + 1005e00: e0800005 stb r2,0(fp) + 1005e04: e7000044 addi fp,fp,1 + 1005e08: 1817883a mov r11,r3 + 1005e0c: e57fd61e bne fp,r21,1005d68 <_dtoa_r+0x5d8> + 1005e10: 500d883a mov r6,r10 + 1005e14: 180f883a mov r7,r3 + 1005e18: 5009883a mov r4,r10 + 1005e1c: 180b883a mov r5,r3 + 1005e20: 100ae5c0 call 100ae5c <__adddf3> + 1005e24: 100d883a mov r6,r2 + 1005e28: 9009883a mov r4,r18 + 1005e2c: 980b883a mov r5,r19 + 1005e30: 180f883a mov r7,r3 + 1005e34: 1021883a mov r16,r2 + 1005e38: 1823883a mov r17,r3 + 1005e3c: 100b70c0 call 100b70c <__ltdf2> + 1005e40: 10000816 blt r2,zero,1005e64 <_dtoa_r+0x6d4> + 1005e44: 980b883a mov r5,r19 + 1005e48: 800d883a mov r6,r16 + 1005e4c: 880f883a mov r7,r17 + 1005e50: 9009883a mov r4,r18 + 1005e54: 100b4ec0 call 100b4ec <__eqdf2> + 1005e58: 1000171e bne r2,zero,1005eb8 <_dtoa_r+0x728> + 1005e5c: a080004c andi r2,r20,1 + 1005e60: 10001526 beq r2,zero,1005eb8 <_dtoa_r+0x728> + 1005e64: d8800d17 ldw r2,52(sp) + 1005e68: d8800415 stw r2,16(sp) + 1005e6c: e009883a mov r4,fp + 1005e70: 213fffc4 addi r4,r4,-1 + 1005e74: 20c00007 ldb r3,0(r4) + 1005e78: 00800e44 movi r2,57 + 1005e7c: 1880081e bne r3,r2,1005ea0 <_dtoa_r+0x710> + 1005e80: d8800517 ldw r2,20(sp) + 1005e84: 113ffa1e bne r2,r4,1005e70 <_dtoa_r+0x6e0> + 1005e88: d8c00417 ldw r3,16(sp) + 1005e8c: d9800517 ldw r6,20(sp) + 1005e90: 00800c04 movi r2,48 + 1005e94: 18c00044 addi r3,r3,1 + 1005e98: d8c00415 stw r3,16(sp) + 1005e9c: 30800005 stb r2,0(r6) + 1005ea0: 20800003 ldbu r2,0(r4) + 1005ea4: d8c00417 ldw r3,16(sp) + 1005ea8: 27000044 addi fp,r4,1 + 1005eac: 10800044 addi r2,r2,1 + 1005eb0: d8c00d15 stw r3,52(sp) + 1005eb4: 20800005 stb r2,0(r4) + 1005eb8: d9001617 ldw r4,88(sp) + 1005ebc: d9400717 ldw r5,28(sp) + 1005ec0: 100814c0 call 100814c <_Bfree> + 1005ec4: e0000005 stb zero,0(fp) + 1005ec8: d9800d17 ldw r6,52(sp) + 1005ecc: d8c02717 ldw r3,156(sp) + 1005ed0: d9002917 ldw r4,164(sp) + 1005ed4: 30800044 addi r2,r6,1 + 1005ed8: 18800015 stw r2,0(r3) + 1005edc: 20029c26 beq r4,zero,1006950 <_dtoa_r+0x11c0> + 1005ee0: d8c00517 ldw r3,20(sp) + 1005ee4: 27000015 stw fp,0(r4) + 1005ee8: 003e5d06 br 1005860 <_dtoa_r+0xd0> + 1005eec: d9800d17 ldw r6,52(sp) + 1005ef0: 00c040b4 movhi r3,258 + 1005ef4: 18e3a004 addi r3,r3,-29056 + 1005ef8: d9001217 ldw r4,72(sp) + 1005efc: 300490fa slli r2,r6,3 + 1005f00: d9401317 ldw r5,76(sp) + 1005f04: 10c5883a add r2,r2,r3 + 1005f08: 12000017 ldw r8,0(r2) + 1005f0c: 12400117 ldw r9,4(r2) + 1005f10: 400d883a mov r6,r8 + 1005f14: 480f883a mov r7,r9 + 1005f18: 100b70c0 call 100b70c <__ltdf2> + 1005f1c: 1000030e bge r2,zero,1005f2c <_dtoa_r+0x79c> + 1005f20: d8800d17 ldw r2,52(sp) + 1005f24: 10bfffc4 addi r2,r2,-1 + 1005f28: d8800d15 stw r2,52(sp) + 1005f2c: d8000c15 stw zero,48(sp) + 1005f30: 003ea806 br 10059d4 <_dtoa_r+0x244> + 1005f34: d9000b17 ldw r4,44(sp) + 1005f38: 202cc03a cmpne r22,r4,zero + 1005f3c: b000c71e bne r22,zero,100625c <_dtoa_r+0xacc> + 1005f40: dc001117 ldw r16,68(sp) + 1005f44: dc801017 ldw r18,64(sp) + 1005f48: 0027883a mov r19,zero + 1005f4c: 04000b0e bge zero,r16,1005f7c <_dtoa_r+0x7ec> + 1005f50: d8c00a17 ldw r3,40(sp) + 1005f54: 00c0090e bge zero,r3,1005f7c <_dtoa_r+0x7ec> + 1005f58: 8005883a mov r2,r16 + 1005f5c: 1c011316 blt r3,r16,10063ac <_dtoa_r+0xc1c> + 1005f60: d9000a17 ldw r4,40(sp) + 1005f64: d9801117 ldw r6,68(sp) + 1005f68: 80a1c83a sub r16,r16,r2 + 1005f6c: 2089c83a sub r4,r4,r2 + 1005f70: 308dc83a sub r6,r6,r2 + 1005f74: d9000a15 stw r4,40(sp) + 1005f78: d9801115 stw r6,68(sp) + 1005f7c: d8801017 ldw r2,64(sp) + 1005f80: 0080150e bge zero,r2,1005fd8 <_dtoa_r+0x848> + 1005f84: d8c00b17 ldw r3,44(sp) + 1005f88: 1805003a cmpeq r2,r3,zero + 1005f8c: 1001c91e bne r2,zero,10066b4 <_dtoa_r+0xf24> + 1005f90: 04800e0e bge zero,r18,1005fcc <_dtoa_r+0x83c> + 1005f94: d9001617 ldw r4,88(sp) + 1005f98: 980b883a mov r5,r19 + 1005f9c: 900d883a mov r6,r18 + 1005fa0: 1008f000 call 1008f00 <__pow5mult> + 1005fa4: d9001617 ldw r4,88(sp) + 1005fa8: d9800717 ldw r6,28(sp) + 1005fac: 100b883a mov r5,r2 + 1005fb0: 1027883a mov r19,r2 + 1005fb4: 1008bdc0 call 1008bdc <__multiply> + 1005fb8: d9001617 ldw r4,88(sp) + 1005fbc: d9400717 ldw r5,28(sp) + 1005fc0: 1023883a mov r17,r2 + 1005fc4: 100814c0 call 100814c <_Bfree> + 1005fc8: dc400715 stw r17,28(sp) + 1005fcc: d9001017 ldw r4,64(sp) + 1005fd0: 248dc83a sub r6,r4,r18 + 1005fd4: 30010e1e bne r6,zero,1006410 <_dtoa_r+0xc80> + 1005fd8: d9001617 ldw r4,88(sp) + 1005fdc: 04400044 movi r17,1 + 1005fe0: 880b883a mov r5,r17 + 1005fe4: 1008dc40 call 1008dc4 <__i2b> + 1005fe8: d9800917 ldw r6,36(sp) + 1005fec: 1025883a mov r18,r2 + 1005ff0: 0180040e bge zero,r6,1006004 <_dtoa_r+0x874> + 1005ff4: d9001617 ldw r4,88(sp) + 1005ff8: 100b883a mov r5,r2 + 1005ffc: 1008f000 call 1008f00 <__pow5mult> + 1006000: 1025883a mov r18,r2 + 1006004: d8801717 ldw r2,92(sp) + 1006008: 8880f30e bge r17,r2,10063d8 <_dtoa_r+0xc48> + 100600c: 0023883a mov r17,zero + 1006010: d9800917 ldw r6,36(sp) + 1006014: 30019e1e bne r6,zero,1006690 <_dtoa_r+0xf00> + 1006018: 00c00044 movi r3,1 + 100601c: d9000a17 ldw r4,40(sp) + 1006020: 20c5883a add r2,r4,r3 + 1006024: 10c007cc andi r3,r2,31 + 1006028: 1800841e bne r3,zero,100623c <_dtoa_r+0xaac> + 100602c: 00800704 movi r2,28 + 1006030: d9000a17 ldw r4,40(sp) + 1006034: d9801117 ldw r6,68(sp) + 1006038: 80a1883a add r16,r16,r2 + 100603c: 2089883a add r4,r4,r2 + 1006040: 308d883a add r6,r6,r2 + 1006044: d9000a15 stw r4,40(sp) + 1006048: d9801115 stw r6,68(sp) + 100604c: d8801117 ldw r2,68(sp) + 1006050: 0080050e bge zero,r2,1006068 <_dtoa_r+0x8d8> + 1006054: d9400717 ldw r5,28(sp) + 1006058: d9001617 ldw r4,88(sp) + 100605c: 100d883a mov r6,r2 + 1006060: 1008a900 call 1008a90 <__lshift> + 1006064: d8800715 stw r2,28(sp) + 1006068: d8c00a17 ldw r3,40(sp) + 100606c: 00c0050e bge zero,r3,1006084 <_dtoa_r+0x8f4> + 1006070: d9001617 ldw r4,88(sp) + 1006074: 900b883a mov r5,r18 + 1006078: 180d883a mov r6,r3 + 100607c: 1008a900 call 1008a90 <__lshift> + 1006080: 1025883a mov r18,r2 + 1006084: d9000c17 ldw r4,48(sp) + 1006088: 2005003a cmpeq r2,r4,zero + 100608c: 10016f26 beq r2,zero,100664c <_dtoa_r+0xebc> + 1006090: d9000f17 ldw r4,60(sp) + 1006094: 0102170e bge zero,r4,10068f4 <_dtoa_r+0x1164> + 1006098: d9800b17 ldw r6,44(sp) + 100609c: 3005003a cmpeq r2,r6,zero + 10060a0: 1000881e bne r2,zero,10062c4 <_dtoa_r+0xb34> + 10060a4: 0400050e bge zero,r16,10060bc <_dtoa_r+0x92c> + 10060a8: d9001617 ldw r4,88(sp) + 10060ac: 980b883a mov r5,r19 + 10060b0: 800d883a mov r6,r16 + 10060b4: 1008a900 call 1008a90 <__lshift> + 10060b8: 1027883a mov r19,r2 + 10060bc: 8804c03a cmpne r2,r17,zero + 10060c0: 1002541e bne r2,zero,1006a14 <_dtoa_r+0x1284> + 10060c4: 980b883a mov r5,r19 + 10060c8: dd800517 ldw r22,20(sp) + 10060cc: dcc00615 stw r19,24(sp) + 10060d0: a700004c andi fp,r20,1 + 10060d4: 2827883a mov r19,r5 + 10060d8: d9000717 ldw r4,28(sp) + 10060dc: 900b883a mov r5,r18 + 10060e0: 10055780 call 1005578 + 10060e4: d9000717 ldw r4,28(sp) + 10060e8: d9400617 ldw r5,24(sp) + 10060ec: 1023883a mov r17,r2 + 10060f0: 8dc00c04 addi r23,r17,48 + 10060f4: 10082a80 call 10082a8 <__mcmp> + 10060f8: d9001617 ldw r4,88(sp) + 10060fc: 900b883a mov r5,r18 + 1006100: 980d883a mov r6,r19 + 1006104: 1029883a mov r20,r2 + 1006108: 10089040 call 1008904 <__mdiff> + 100610c: 102b883a mov r21,r2 + 1006110: 10800317 ldw r2,12(r2) + 1006114: 1001281e bne r2,zero,10065b8 <_dtoa_r+0xe28> + 1006118: d9000717 ldw r4,28(sp) + 100611c: a80b883a mov r5,r21 + 1006120: 10082a80 call 10082a8 <__mcmp> + 1006124: d9001617 ldw r4,88(sp) + 1006128: 1021883a mov r16,r2 + 100612c: a80b883a mov r5,r21 + 1006130: 100814c0 call 100814c <_Bfree> + 1006134: 8000041e bne r16,zero,1006148 <_dtoa_r+0x9b8> + 1006138: d8801717 ldw r2,92(sp) + 100613c: 1000021e bne r2,zero,1006148 <_dtoa_r+0x9b8> + 1006140: e004c03a cmpne r2,fp,zero + 1006144: 10011726 beq r2,zero,10065a4 <_dtoa_r+0xe14> + 1006148: a0010616 blt r20,zero,1006564 <_dtoa_r+0xdd4> + 100614c: a000041e bne r20,zero,1006160 <_dtoa_r+0x9d0> + 1006150: d8c01717 ldw r3,92(sp) + 1006154: 1800021e bne r3,zero,1006160 <_dtoa_r+0x9d0> + 1006158: e004c03a cmpne r2,fp,zero + 100615c: 10010126 beq r2,zero,1006564 <_dtoa_r+0xdd4> + 1006160: 04023d16 blt zero,r16,1006a58 <_dtoa_r+0x12c8> + 1006164: b5c00005 stb r23,0(r22) + 1006168: d9800517 ldw r6,20(sp) + 100616c: d9000f17 ldw r4,60(sp) + 1006170: b5800044 addi r22,r22,1 + 1006174: 3105883a add r2,r6,r4 + 1006178: b0806526 beq r22,r2,1006310 <_dtoa_r+0xb80> + 100617c: d9400717 ldw r5,28(sp) + 1006180: d9001617 ldw r4,88(sp) + 1006184: 01800284 movi r6,10 + 1006188: 000f883a mov r7,zero + 100618c: 1008e000 call 1008e00 <__multadd> + 1006190: d8800715 stw r2,28(sp) + 1006194: d8800617 ldw r2,24(sp) + 1006198: 14c10c26 beq r2,r19,10065cc <_dtoa_r+0xe3c> + 100619c: d9400617 ldw r5,24(sp) + 10061a0: d9001617 ldw r4,88(sp) + 10061a4: 01800284 movi r6,10 + 10061a8: 000f883a mov r7,zero + 10061ac: 1008e000 call 1008e00 <__multadd> + 10061b0: d9001617 ldw r4,88(sp) + 10061b4: 980b883a mov r5,r19 + 10061b8: 01800284 movi r6,10 + 10061bc: 000f883a mov r7,zero + 10061c0: d8800615 stw r2,24(sp) + 10061c4: 1008e000 call 1008e00 <__multadd> + 10061c8: 1027883a mov r19,r2 + 10061cc: 003fc206 br 10060d8 <_dtoa_r+0x948> + 10061d0: 2445c83a sub r2,r4,r17 + 10061d4: a088983a sll r4,r20,r2 + 10061d8: 003e4b06 br 1005b08 <_dtoa_r+0x378> + 10061dc: 01bfffc4 movi r6,-1 + 10061e0: 00800044 movi r2,1 + 10061e4: d9800e15 stw r6,56(sp) + 10061e8: d9800f15 stw r6,60(sp) + 10061ec: d8800b15 stw r2,44(sp) + 10061f0: d8c01617 ldw r3,88(sp) + 10061f4: 008005c4 movi r2,23 + 10061f8: 18001115 stw zero,68(r3) + 10061fc: 1580082e bgeu r2,r22,1006220 <_dtoa_r+0xa90> + 1006200: 00c00104 movi r3,4 + 1006204: 0009883a mov r4,zero + 1006208: 18c7883a add r3,r3,r3 + 100620c: 18800504 addi r2,r3,20 + 1006210: 21000044 addi r4,r4,1 + 1006214: b0bffc2e bgeu r22,r2,1006208 <_dtoa_r+0xa78> + 1006218: d9801617 ldw r6,88(sp) + 100621c: 31001115 stw r4,68(r6) + 1006220: dc000f17 ldw r16,60(sp) + 1006224: 003e4b06 br 1005b54 <_dtoa_r+0x3c4> + 1006228: d9801717 ldw r6,92(sp) + 100622c: 0023883a mov r17,zero + 1006230: 31bfff04 addi r6,r6,-4 + 1006234: d9801715 stw r6,92(sp) + 1006238: 003df806 br 1005a1c <_dtoa_r+0x28c> + 100623c: 00800804 movi r2,32 + 1006240: 10c9c83a sub r4,r2,r3 + 1006244: 00c00104 movi r3,4 + 1006248: 19005a16 blt r3,r4,10063b4 <_dtoa_r+0xc24> + 100624c: 008000c4 movi r2,3 + 1006250: 113f7e16 blt r2,r4,100604c <_dtoa_r+0x8bc> + 1006254: 20800704 addi r2,r4,28 + 1006258: 003f7506 br 1006030 <_dtoa_r+0x8a0> + 100625c: d9801717 ldw r6,92(sp) + 1006260: 00800044 movi r2,1 + 1006264: 1180a10e bge r2,r6,10064ec <_dtoa_r+0xd5c> + 1006268: d9800f17 ldw r6,60(sp) + 100626c: d8c01017 ldw r3,64(sp) + 1006270: 30bfffc4 addi r2,r6,-1 + 1006274: 1881c616 blt r3,r2,1006990 <_dtoa_r+0x1200> + 1006278: 18a5c83a sub r18,r3,r2 + 100627c: d8800f17 ldw r2,60(sp) + 1006280: 10026216 blt r2,zero,1006c0c <_dtoa_r+0x147c> + 1006284: dc001117 ldw r16,68(sp) + 1006288: 1007883a mov r3,r2 + 100628c: d9800a17 ldw r6,40(sp) + 1006290: d8801117 ldw r2,68(sp) + 1006294: d9001617 ldw r4,88(sp) + 1006298: 30cd883a add r6,r6,r3 + 100629c: 10c5883a add r2,r2,r3 + 10062a0: 01400044 movi r5,1 + 10062a4: d9800a15 stw r6,40(sp) + 10062a8: d8801115 stw r2,68(sp) + 10062ac: 1008dc40 call 1008dc4 <__i2b> + 10062b0: 1027883a mov r19,r2 + 10062b4: 003f2506 br 1005f4c <_dtoa_r+0x7bc> + 10062b8: 00c040b4 movhi r3,258 + 10062bc: 18e38204 addi r3,r3,-29176 + 10062c0: 003d6706 br 1005860 <_dtoa_r+0xd0> + 10062c4: dd800517 ldw r22,20(sp) + 10062c8: 04000044 movi r16,1 + 10062cc: 00000706 br 10062ec <_dtoa_r+0xb5c> + 10062d0: d9400717 ldw r5,28(sp) + 10062d4: d9001617 ldw r4,88(sp) + 10062d8: 01800284 movi r6,10 + 10062dc: 000f883a mov r7,zero + 10062e0: 1008e000 call 1008e00 <__multadd> + 10062e4: d8800715 stw r2,28(sp) + 10062e8: 84000044 addi r16,r16,1 + 10062ec: d9000717 ldw r4,28(sp) + 10062f0: 900b883a mov r5,r18 + 10062f4: 10055780 call 1005578 + 10062f8: 15c00c04 addi r23,r2,48 + 10062fc: b5c00005 stb r23,0(r22) + 1006300: d8c00f17 ldw r3,60(sp) + 1006304: b5800044 addi r22,r22,1 + 1006308: 80fff116 blt r16,r3,10062d0 <_dtoa_r+0xb40> + 100630c: d8000615 stw zero,24(sp) + 1006310: d9400717 ldw r5,28(sp) + 1006314: d9001617 ldw r4,88(sp) + 1006318: 01800044 movi r6,1 + 100631c: 1008a900 call 1008a90 <__lshift> + 1006320: 1009883a mov r4,r2 + 1006324: 900b883a mov r5,r18 + 1006328: d8800715 stw r2,28(sp) + 100632c: 10082a80 call 10082a8 <__mcmp> + 1006330: 00803c0e bge zero,r2,1006424 <_dtoa_r+0xc94> + 1006334: b009883a mov r4,r22 + 1006338: 213fffc4 addi r4,r4,-1 + 100633c: 21400003 ldbu r5,0(r4) + 1006340: 00800e44 movi r2,57 + 1006344: 28c03fcc andi r3,r5,255 + 1006348: 18c0201c xori r3,r3,128 + 100634c: 18ffe004 addi r3,r3,-128 + 1006350: 1881981e bne r3,r2,10069b4 <_dtoa_r+0x1224> + 1006354: d9800517 ldw r6,20(sp) + 1006358: 21bff71e bne r4,r6,1006338 <_dtoa_r+0xba8> + 100635c: d8800d17 ldw r2,52(sp) + 1006360: 37000044 addi fp,r6,1 + 1006364: 10800044 addi r2,r2,1 + 1006368: d8800d15 stw r2,52(sp) + 100636c: 00800c44 movi r2,49 + 1006370: 30800005 stb r2,0(r6) + 1006374: d9001617 ldw r4,88(sp) + 1006378: 900b883a mov r5,r18 + 100637c: 100814c0 call 100814c <_Bfree> + 1006380: 983ecd26 beq r19,zero,1005eb8 <_dtoa_r+0x728> + 1006384: d8c00617 ldw r3,24(sp) + 1006388: 18000426 beq r3,zero,100639c <_dtoa_r+0xc0c> + 100638c: 1cc00326 beq r3,r19,100639c <_dtoa_r+0xc0c> + 1006390: d9001617 ldw r4,88(sp) + 1006394: 180b883a mov r5,r3 + 1006398: 100814c0 call 100814c <_Bfree> + 100639c: d9001617 ldw r4,88(sp) + 10063a0: 980b883a mov r5,r19 + 10063a4: 100814c0 call 100814c <_Bfree> + 10063a8: 003ec306 br 1005eb8 <_dtoa_r+0x728> + 10063ac: 1805883a mov r2,r3 + 10063b0: 003eeb06 br 1005f60 <_dtoa_r+0x7d0> + 10063b4: d9800a17 ldw r6,40(sp) + 10063b8: d8c01117 ldw r3,68(sp) + 10063bc: 20bfff04 addi r2,r4,-4 + 10063c0: 308d883a add r6,r6,r2 + 10063c4: 1887883a add r3,r3,r2 + 10063c8: 80a1883a add r16,r16,r2 + 10063cc: d9800a15 stw r6,40(sp) + 10063d0: d8c01115 stw r3,68(sp) + 10063d4: 003f1d06 br 100604c <_dtoa_r+0x8bc> + 10063d8: a03f0c1e bne r20,zero,100600c <_dtoa_r+0x87c> + 10063dc: 00800434 movhi r2,16 + 10063e0: 10bfffc4 addi r2,r2,-1 + 10063e4: a884703a and r2,r21,r2 + 10063e8: 103f081e bne r2,zero,100600c <_dtoa_r+0x87c> + 10063ec: a89ffc2c andhi r2,r21,32752 + 10063f0: 103f0626 beq r2,zero,100600c <_dtoa_r+0x87c> + 10063f4: d8c01117 ldw r3,68(sp) + 10063f8: d9000a17 ldw r4,40(sp) + 10063fc: 18c00044 addi r3,r3,1 + 1006400: 21000044 addi r4,r4,1 + 1006404: d8c01115 stw r3,68(sp) + 1006408: d9000a15 stw r4,40(sp) + 100640c: 003f0006 br 1006010 <_dtoa_r+0x880> + 1006410: d9400717 ldw r5,28(sp) + 1006414: d9001617 ldw r4,88(sp) + 1006418: 1008f000 call 1008f00 <__pow5mult> + 100641c: d8800715 stw r2,28(sp) + 1006420: 003eed06 br 1005fd8 <_dtoa_r+0x848> + 1006424: 1000021e bne r2,zero,1006430 <_dtoa_r+0xca0> + 1006428: b880004c andi r2,r23,1 + 100642c: 103fc11e bne r2,zero,1006334 <_dtoa_r+0xba4> + 1006430: b5bfffc4 addi r22,r22,-1 + 1006434: b0c00007 ldb r3,0(r22) + 1006438: 00800c04 movi r2,48 + 100643c: 18bffc26 beq r3,r2,1006430 <_dtoa_r+0xca0> + 1006440: b7000044 addi fp,r22,1 + 1006444: 003fcb06 br 1006374 <_dtoa_r+0xbe4> + 1006448: d9800d17 ldw r6,52(sp) + 100644c: 018fc83a sub r7,zero,r6 + 1006450: 3801f726 beq r7,zero,1006c30 <_dtoa_r+0x14a0> + 1006454: 398003cc andi r6,r7,15 + 1006458: 300c90fa slli r6,r6,3 + 100645c: 014040b4 movhi r5,258 + 1006460: 2963a004 addi r5,r5,-29056 + 1006464: d9001217 ldw r4,72(sp) + 1006468: 314d883a add r6,r6,r5 + 100646c: 30c00117 ldw r3,4(r6) + 1006470: 30800017 ldw r2,0(r6) + 1006474: d9401317 ldw r5,76(sp) + 1006478: 3821d13a srai r16,r7,4 + 100647c: 100d883a mov r6,r2 + 1006480: 180f883a mov r7,r3 + 1006484: 100aed00 call 100aed0 <__muldf3> + 1006488: 1011883a mov r8,r2 + 100648c: 1813883a mov r9,r3 + 1006490: 1029883a mov r20,r2 + 1006494: 182b883a mov r21,r3 + 1006498: 8001e526 beq r16,zero,1006c30 <_dtoa_r+0x14a0> + 100649c: 05800084 movi r22,2 + 10064a0: 044040b4 movhi r17,258 + 10064a4: 8c63d204 addi r17,r17,-28856 + 10064a8: 8080004c andi r2,r16,1 + 10064ac: 1005003a cmpeq r2,r2,zero + 10064b0: 1000081e bne r2,zero,10064d4 <_dtoa_r+0xd44> + 10064b4: 89800017 ldw r6,0(r17) + 10064b8: 89c00117 ldw r7,4(r17) + 10064bc: 480b883a mov r5,r9 + 10064c0: 4009883a mov r4,r8 + 10064c4: 100aed00 call 100aed0 <__muldf3> + 10064c8: 1011883a mov r8,r2 + 10064cc: b5800044 addi r22,r22,1 + 10064d0: 1813883a mov r9,r3 + 10064d4: 8021d07a srai r16,r16,1 + 10064d8: 8c400204 addi r17,r17,8 + 10064dc: 803ff21e bne r16,zero,10064a8 <_dtoa_r+0xd18> + 10064e0: 4029883a mov r20,r8 + 10064e4: 482b883a mov r21,r9 + 10064e8: 003dca06 br 1005c14 <_dtoa_r+0x484> + 10064ec: d9000817 ldw r4,32(sp) + 10064f0: 2005003a cmpeq r2,r4,zero + 10064f4: 1001f61e bne r2,zero,1006cd0 <_dtoa_r+0x1540> + 10064f8: dc001117 ldw r16,68(sp) + 10064fc: dc801017 ldw r18,64(sp) + 1006500: 18c10cc4 addi r3,r3,1075 + 1006504: 003f6106 br 100628c <_dtoa_r+0xafc> + 1006508: d8000b15 stw zero,44(sp) + 100650c: d9802617 ldw r6,152(sp) + 1006510: d8c00d17 ldw r3,52(sp) + 1006514: 30800044 addi r2,r6,1 + 1006518: 18ad883a add r22,r3,r2 + 100651c: b13fffc4 addi r4,r22,-1 + 1006520: d9000e15 stw r4,56(sp) + 1006524: 0581f60e bge zero,r22,1006d00 <_dtoa_r+0x1570> + 1006528: dd800f15 stw r22,60(sp) + 100652c: 003f3006 br 10061f0 <_dtoa_r+0xa60> + 1006530: d8000b15 stw zero,44(sp) + 1006534: d9002617 ldw r4,152(sp) + 1006538: 0101eb0e bge zero,r4,1006ce8 <_dtoa_r+0x1558> + 100653c: 202d883a mov r22,r4 + 1006540: d9000e15 stw r4,56(sp) + 1006544: d9000f15 stw r4,60(sp) + 1006548: 003f2906 br 10061f0 <_dtoa_r+0xa60> + 100654c: 01800044 movi r6,1 + 1006550: d9800b15 stw r6,44(sp) + 1006554: 003ff706 br 1006534 <_dtoa_r+0xda4> + 1006558: 01000044 movi r4,1 + 100655c: d9000b15 stw r4,44(sp) + 1006560: 003fea06 br 100650c <_dtoa_r+0xd7c> + 1006564: 04000c0e bge zero,r16,1006598 <_dtoa_r+0xe08> + 1006568: d9400717 ldw r5,28(sp) + 100656c: d9001617 ldw r4,88(sp) + 1006570: 01800044 movi r6,1 + 1006574: 1008a900 call 1008a90 <__lshift> + 1006578: 1009883a mov r4,r2 + 100657c: 900b883a mov r5,r18 + 1006580: d8800715 stw r2,28(sp) + 1006584: 10082a80 call 10082a8 <__mcmp> + 1006588: 0081e00e bge zero,r2,1006d0c <_dtoa_r+0x157c> + 100658c: bdc00044 addi r23,r23,1 + 1006590: 00800e84 movi r2,58 + 1006594: b881a226 beq r23,r2,1006c20 <_dtoa_r+0x1490> + 1006598: b7000044 addi fp,r22,1 + 100659c: b5c00005 stb r23,0(r22) + 10065a0: 003f7406 br 1006374 <_dtoa_r+0xbe4> + 10065a4: 00800e44 movi r2,57 + 10065a8: b8819d26 beq r23,r2,1006c20 <_dtoa_r+0x1490> + 10065ac: 053ffa0e bge zero,r20,1006598 <_dtoa_r+0xe08> + 10065b0: 8dc00c44 addi r23,r17,49 + 10065b4: 003ff806 br 1006598 <_dtoa_r+0xe08> + 10065b8: d9001617 ldw r4,88(sp) + 10065bc: a80b883a mov r5,r21 + 10065c0: 04000044 movi r16,1 + 10065c4: 100814c0 call 100814c <_Bfree> + 10065c8: 003edf06 br 1006148 <_dtoa_r+0x9b8> + 10065cc: d9001617 ldw r4,88(sp) + 10065d0: 980b883a mov r5,r19 + 10065d4: 01800284 movi r6,10 + 10065d8: 000f883a mov r7,zero + 10065dc: 1008e000 call 1008e00 <__multadd> + 10065e0: 1027883a mov r19,r2 + 10065e4: d8800615 stw r2,24(sp) + 10065e8: 003ebb06 br 10060d8 <_dtoa_r+0x948> + 10065ec: d9801117 ldw r6,68(sp) + 10065f0: d8800d17 ldw r2,52(sp) + 10065f4: d8000915 stw zero,36(sp) + 10065f8: 308dc83a sub r6,r6,r2 + 10065fc: 0087c83a sub r3,zero,r2 + 1006600: d9801115 stw r6,68(sp) + 1006604: d8c01015 stw r3,64(sp) + 1006608: 003cfe06 br 1005a04 <_dtoa_r+0x274> + 100660c: 018dc83a sub r6,zero,r6 + 1006610: d9801115 stw r6,68(sp) + 1006614: d8000a15 stw zero,40(sp) + 1006618: 003cf306 br 10059e8 <_dtoa_r+0x258> + 100661c: d9000d17 ldw r4,52(sp) + 1006620: 100b7940 call 100b794 <__floatsidf> + 1006624: 880b883a mov r5,r17 + 1006628: 8009883a mov r4,r16 + 100662c: 180f883a mov r7,r3 + 1006630: 100d883a mov r6,r2 + 1006634: 100b5740 call 100b574 <__nedf2> + 1006638: 103ce126 beq r2,zero,10059c0 <_dtoa_r+0x230> + 100663c: d9800d17 ldw r6,52(sp) + 1006640: 31bfffc4 addi r6,r6,-1 + 1006644: d9800d15 stw r6,52(sp) + 1006648: 003cdd06 br 10059c0 <_dtoa_r+0x230> + 100664c: d9000717 ldw r4,28(sp) + 1006650: 900b883a mov r5,r18 + 1006654: 10082a80 call 10082a8 <__mcmp> + 1006658: 103e8d0e bge r2,zero,1006090 <_dtoa_r+0x900> + 100665c: d9400717 ldw r5,28(sp) + 1006660: d9001617 ldw r4,88(sp) + 1006664: 01800284 movi r6,10 + 1006668: 000f883a mov r7,zero + 100666c: 1008e000 call 1008e00 <__multadd> + 1006670: d9800d17 ldw r6,52(sp) + 1006674: d8800715 stw r2,28(sp) + 1006678: 31bfffc4 addi r6,r6,-1 + 100667c: d9800d15 stw r6,52(sp) + 1006680: b001a71e bne r22,zero,1006d20 <_dtoa_r+0x1590> + 1006684: d8800e17 ldw r2,56(sp) + 1006688: d8800f15 stw r2,60(sp) + 100668c: 003e8006 br 1006090 <_dtoa_r+0x900> + 1006690: 90800417 ldw r2,16(r18) + 1006694: 1085883a add r2,r2,r2 + 1006698: 1085883a add r2,r2,r2 + 100669c: 1485883a add r2,r2,r18 + 10066a0: 11000417 ldw r4,16(r2) + 10066a4: 10081740 call 1008174 <__hi0bits> + 10066a8: 00c00804 movi r3,32 + 10066ac: 1887c83a sub r3,r3,r2 + 10066b0: 003e5a06 br 100601c <_dtoa_r+0x88c> + 10066b4: d9400717 ldw r5,28(sp) + 10066b8: d9801017 ldw r6,64(sp) + 10066bc: d9001617 ldw r4,88(sp) + 10066c0: 1008f000 call 1008f00 <__pow5mult> + 10066c4: d8800715 stw r2,28(sp) + 10066c8: 003e4306 br 1005fd8 <_dtoa_r+0x848> + 10066cc: d9800f17 ldw r6,60(sp) + 10066d0: d8800d17 ldw r2,52(sp) + 10066d4: d9800315 stw r6,12(sp) + 10066d8: d8800415 stw r2,16(sp) + 10066dc: d8c00b17 ldw r3,44(sp) + 10066e0: 1805003a cmpeq r2,r3,zero + 10066e4: 1000e21e bne r2,zero,1006a70 <_dtoa_r+0x12e0> + 10066e8: d9000317 ldw r4,12(sp) + 10066ec: 0005883a mov r2,zero + 10066f0: 00cff834 movhi r3,16352 + 10066f4: 200c90fa slli r6,r4,3 + 10066f8: 010040b4 movhi r4,258 + 10066fc: 2123a004 addi r4,r4,-29056 + 1006700: 180b883a mov r5,r3 + 1006704: 310d883a add r6,r6,r4 + 1006708: 327fff17 ldw r9,-4(r6) + 100670c: 323ffe17 ldw r8,-8(r6) + 1006710: 1009883a mov r4,r2 + 1006714: 480f883a mov r7,r9 + 1006718: 400d883a mov r6,r8 + 100671c: 100b2940 call 100b294 <__divdf3> + 1006720: 180b883a mov r5,r3 + 1006724: b00d883a mov r6,r22 + 1006728: b80f883a mov r7,r23 + 100672c: 1009883a mov r4,r2 + 1006730: 100addc0 call 100addc <__subdf3> + 1006734: a80b883a mov r5,r21 + 1006738: a009883a mov r4,r20 + 100673c: d8c01915 stw r3,100(sp) + 1006740: d8801815 stw r2,96(sp) + 1006744: 100b88c0 call 100b88c <__fixdfsi> + 1006748: 1009883a mov r4,r2 + 100674c: 1027883a mov r19,r2 + 1006750: 100b7940 call 100b794 <__floatsidf> + 1006754: a80b883a mov r5,r21 + 1006758: a009883a mov r4,r20 + 100675c: 180f883a mov r7,r3 + 1006760: 100d883a mov r6,r2 + 1006764: 100addc0 call 100addc <__subdf3> + 1006768: d9801817 ldw r6,96(sp) + 100676c: 1823883a mov r17,r3 + 1006770: d8801415 stw r2,80(sp) + 1006774: 302d883a mov r22,r6 + 1006778: d9800517 ldw r6,20(sp) + 100677c: 9cc00c04 addi r19,r19,48 + 1006780: dc401515 stw r17,84(sp) + 1006784: d8c01917 ldw r3,100(sp) + 1006788: 34c00005 stb r19,0(r6) + 100678c: d8800517 ldw r2,20(sp) + 1006790: d9401917 ldw r5,100(sp) + 1006794: d9801417 ldw r6,80(sp) + 1006798: b009883a mov r4,r22 + 100679c: 880f883a mov r7,r17 + 10067a0: 182f883a mov r23,r3 + 10067a4: 17000044 addi fp,r2,1 + 10067a8: 100b5fc0 call 100b5fc <__gtdf2> + 10067ac: 00804e16 blt zero,r2,10068e8 <_dtoa_r+0x1158> + 10067b0: d9801417 ldw r6,80(sp) + 10067b4: 0005883a mov r2,zero + 10067b8: 00cffc34 movhi r3,16368 + 10067bc: 180b883a mov r5,r3 + 10067c0: 880f883a mov r7,r17 + 10067c4: 1009883a mov r4,r2 + 10067c8: 100addc0 call 100addc <__subdf3> + 10067cc: d9401917 ldw r5,100(sp) + 10067d0: 180f883a mov r7,r3 + 10067d4: b009883a mov r4,r22 + 10067d8: 100d883a mov r6,r2 + 10067dc: 100b5fc0 call 100b5fc <__gtdf2> + 10067e0: 00bda216 blt zero,r2,1005e6c <_dtoa_r+0x6dc> + 10067e4: d8c00317 ldw r3,12(sp) + 10067e8: 00800044 movi r2,1 + 10067ec: 10c01216 blt r2,r3,1006838 <_dtoa_r+0x10a8> + 10067f0: 003d4506 br 1005d08 <_dtoa_r+0x578> + 10067f4: d9801417 ldw r6,80(sp) + 10067f8: 0005883a mov r2,zero + 10067fc: 00cffc34 movhi r3,16368 + 1006800: 180b883a mov r5,r3 + 1006804: 880f883a mov r7,r17 + 1006808: 1009883a mov r4,r2 + 100680c: 100addc0 call 100addc <__subdf3> + 1006810: d9c01b17 ldw r7,108(sp) + 1006814: 180b883a mov r5,r3 + 1006818: 1009883a mov r4,r2 + 100681c: b00d883a mov r6,r22 + 1006820: 100b70c0 call 100b70c <__ltdf2> + 1006824: 103d9116 blt r2,zero,1005e6c <_dtoa_r+0x6dc> + 1006828: d9800517 ldw r6,20(sp) + 100682c: d9000317 ldw r4,12(sp) + 1006830: 3105883a add r2,r6,r4 + 1006834: e0bd3426 beq fp,r2,1005d08 <_dtoa_r+0x578> + 1006838: 04500934 movhi r17,16420 + 100683c: 0021883a mov r16,zero + 1006840: b80b883a mov r5,r23 + 1006844: b009883a mov r4,r22 + 1006848: 800d883a mov r6,r16 + 100684c: 880f883a mov r7,r17 + 1006850: 100aed00 call 100aed0 <__muldf3> + 1006854: d9401517 ldw r5,84(sp) + 1006858: d9001417 ldw r4,80(sp) + 100685c: 880f883a mov r7,r17 + 1006860: 000d883a mov r6,zero + 1006864: d8801a15 stw r2,104(sp) + 1006868: d8c01b15 stw r3,108(sp) + 100686c: 100aed00 call 100aed0 <__muldf3> + 1006870: 180b883a mov r5,r3 + 1006874: 1009883a mov r4,r2 + 1006878: 1823883a mov r17,r3 + 100687c: 1021883a mov r16,r2 + 1006880: 100b88c0 call 100b88c <__fixdfsi> + 1006884: 1009883a mov r4,r2 + 1006888: 102b883a mov r21,r2 + 100688c: 100b7940 call 100b794 <__floatsidf> + 1006890: 880b883a mov r5,r17 + 1006894: 8009883a mov r4,r16 + 1006898: 180f883a mov r7,r3 + 100689c: 100d883a mov r6,r2 + 10068a0: 100addc0 call 100addc <__subdf3> + 10068a4: 1021883a mov r16,r2 + 10068a8: d9001b17 ldw r4,108(sp) + 10068ac: 1823883a mov r17,r3 + 10068b0: dc001415 stw r16,80(sp) + 10068b4: ad400c04 addi r21,r21,48 + 10068b8: dc401515 stw r17,84(sp) + 10068bc: d8801a17 ldw r2,104(sp) + 10068c0: e5400005 stb r21,0(fp) + 10068c4: 202f883a mov r23,r4 + 10068c8: d9c01b17 ldw r7,108(sp) + 10068cc: d9001417 ldw r4,80(sp) + 10068d0: 880b883a mov r5,r17 + 10068d4: 100d883a mov r6,r2 + 10068d8: 102d883a mov r22,r2 + 10068dc: e7000044 addi fp,fp,1 + 10068e0: 100b70c0 call 100b70c <__ltdf2> + 10068e4: 103fc30e bge r2,zero,10067f4 <_dtoa_r+0x1064> + 10068e8: d9000417 ldw r4,16(sp) + 10068ec: d9000d15 stw r4,52(sp) + 10068f0: 003d7106 br 1005eb8 <_dtoa_r+0x728> + 10068f4: d9801717 ldw r6,92(sp) + 10068f8: 00800084 movi r2,2 + 10068fc: 11bde60e bge r2,r6,1006098 <_dtoa_r+0x908> + 1006900: 203cfb1e bne r4,zero,1005cf0 <_dtoa_r+0x560> + 1006904: d9001617 ldw r4,88(sp) + 1006908: 900b883a mov r5,r18 + 100690c: 01800144 movi r6,5 + 1006910: 000f883a mov r7,zero + 1006914: 1008e000 call 1008e00 <__multadd> + 1006918: d9000717 ldw r4,28(sp) + 100691c: 100b883a mov r5,r2 + 1006920: 1025883a mov r18,r2 + 1006924: 10082a80 call 10082a8 <__mcmp> + 1006928: 00bcf10e bge zero,r2,1005cf0 <_dtoa_r+0x560> + 100692c: d8c00d17 ldw r3,52(sp) + 1006930: d9000517 ldw r4,20(sp) + 1006934: d8000615 stw zero,24(sp) + 1006938: 18c00044 addi r3,r3,1 + 100693c: d8c00d15 stw r3,52(sp) + 1006940: 00800c44 movi r2,49 + 1006944: 27000044 addi fp,r4,1 + 1006948: 20800005 stb r2,0(r4) + 100694c: 003e8906 br 1006374 <_dtoa_r+0xbe4> + 1006950: d8c00517 ldw r3,20(sp) + 1006954: 003bc206 br 1005860 <_dtoa_r+0xd0> + 1006958: 018040b4 movhi r6,258 + 100695c: 31a3d204 addi r6,r6,-28856 + 1006960: 30c00917 ldw r3,36(r6) + 1006964: 30800817 ldw r2,32(r6) + 1006968: d9001217 ldw r4,72(sp) + 100696c: d9401317 ldw r5,76(sp) + 1006970: 180f883a mov r7,r3 + 1006974: 100d883a mov r6,r2 + 1006978: 100b2940 call 100b294 <__divdf3> + 100697c: 948003cc andi r18,r18,15 + 1006980: 058000c4 movi r22,3 + 1006984: 1029883a mov r20,r2 + 1006988: 182b883a mov r21,r3 + 100698c: 003c8906 br 1005bb4 <_dtoa_r+0x424> + 1006990: d9001017 ldw r4,64(sp) + 1006994: d9800917 ldw r6,36(sp) + 1006998: 0025883a mov r18,zero + 100699c: 1105c83a sub r2,r2,r4 + 10069a0: 2089883a add r4,r4,r2 + 10069a4: 308d883a add r6,r6,r2 + 10069a8: d9001015 stw r4,64(sp) + 10069ac: d9800915 stw r6,36(sp) + 10069b0: 003e3206 br 100627c <_dtoa_r+0xaec> + 10069b4: 28800044 addi r2,r5,1 + 10069b8: 27000044 addi fp,r4,1 + 10069bc: 20800005 stb r2,0(r4) + 10069c0: 003e6c06 br 1006374 <_dtoa_r+0xbe4> + 10069c4: d8800f17 ldw r2,60(sp) + 10069c8: 00bce016 blt zero,r2,1005d4c <_dtoa_r+0x5bc> + 10069cc: d9800f17 ldw r6,60(sp) + 10069d0: 303cc51e bne r6,zero,1005ce8 <_dtoa_r+0x558> + 10069d4: 0005883a mov r2,zero + 10069d8: 00d00534 movhi r3,16404 + 10069dc: 980b883a mov r5,r19 + 10069e0: 180f883a mov r7,r3 + 10069e4: 9009883a mov r4,r18 + 10069e8: 100d883a mov r6,r2 + 10069ec: 100aed00 call 100aed0 <__muldf3> + 10069f0: 180b883a mov r5,r3 + 10069f4: a80f883a mov r7,r21 + 10069f8: 1009883a mov r4,r2 + 10069fc: a00d883a mov r6,r20 + 1006a00: 100b6840 call 100b684 <__gedf2> + 1006a04: 103cb80e bge r2,zero,1005ce8 <_dtoa_r+0x558> + 1006a08: 0027883a mov r19,zero + 1006a0c: 0025883a mov r18,zero + 1006a10: 003fc606 br 100692c <_dtoa_r+0x119c> + 1006a14: 99400117 ldw r5,4(r19) + 1006a18: d9001617 ldw r4,88(sp) + 1006a1c: 10086cc0 call 10086cc <_Balloc> + 1006a20: 99800417 ldw r6,16(r19) + 1006a24: 11000304 addi r4,r2,12 + 1006a28: 99400304 addi r5,r19,12 + 1006a2c: 318d883a add r6,r6,r6 + 1006a30: 318d883a add r6,r6,r6 + 1006a34: 31800204 addi r6,r6,8 + 1006a38: 1023883a mov r17,r2 + 1006a3c: 1007fcc0 call 1007fcc + 1006a40: d9001617 ldw r4,88(sp) + 1006a44: 880b883a mov r5,r17 + 1006a48: 01800044 movi r6,1 + 1006a4c: 1008a900 call 1008a90 <__lshift> + 1006a50: 100b883a mov r5,r2 + 1006a54: 003d9c06 br 10060c8 <_dtoa_r+0x938> + 1006a58: 00800e44 movi r2,57 + 1006a5c: b8807026 beq r23,r2,1006c20 <_dtoa_r+0x1490> + 1006a60: b8800044 addi r2,r23,1 + 1006a64: b7000044 addi fp,r22,1 + 1006a68: b0800005 stb r2,0(r22) + 1006a6c: 003e4106 br 1006374 <_dtoa_r+0xbe4> + 1006a70: d8800317 ldw r2,12(sp) + 1006a74: 018040b4 movhi r6,258 + 1006a78: 31a3a004 addi r6,r6,-29056 + 1006a7c: b009883a mov r4,r22 + 1006a80: 100e90fa slli r7,r2,3 + 1006a84: b80b883a mov r5,r23 + 1006a88: 398f883a add r7,r7,r6 + 1006a8c: 38bffe17 ldw r2,-8(r7) + 1006a90: d9800517 ldw r6,20(sp) + 1006a94: 38ffff17 ldw r3,-4(r7) + 1006a98: 37000044 addi fp,r6,1 + 1006a9c: 180f883a mov r7,r3 + 1006aa0: 100d883a mov r6,r2 + 1006aa4: 100aed00 call 100aed0 <__muldf3> + 1006aa8: a80b883a mov r5,r21 + 1006aac: a009883a mov r4,r20 + 1006ab0: 182f883a mov r23,r3 + 1006ab4: 102d883a mov r22,r2 + 1006ab8: 100b88c0 call 100b88c <__fixdfsi> + 1006abc: 1009883a mov r4,r2 + 1006ac0: 1027883a mov r19,r2 + 1006ac4: 100b7940 call 100b794 <__floatsidf> + 1006ac8: a80b883a mov r5,r21 + 1006acc: a009883a mov r4,r20 + 1006ad0: 180f883a mov r7,r3 + 1006ad4: 100d883a mov r6,r2 + 1006ad8: 100addc0 call 100addc <__subdf3> + 1006adc: 180b883a mov r5,r3 + 1006ae0: d8c00517 ldw r3,20(sp) + 1006ae4: 9cc00c04 addi r19,r19,48 + 1006ae8: 1009883a mov r4,r2 + 1006aec: 1cc00005 stb r19,0(r3) + 1006af0: 2021883a mov r16,r4 + 1006af4: d9000317 ldw r4,12(sp) + 1006af8: 00800044 movi r2,1 + 1006afc: 2823883a mov r17,r5 + 1006b00: 20802226 beq r4,r2,1006b8c <_dtoa_r+0x13fc> + 1006b04: 1029883a mov r20,r2 + 1006b08: 0005883a mov r2,zero + 1006b0c: 00d00934 movhi r3,16420 + 1006b10: 180f883a mov r7,r3 + 1006b14: 100d883a mov r6,r2 + 1006b18: 880b883a mov r5,r17 + 1006b1c: 8009883a mov r4,r16 + 1006b20: 100aed00 call 100aed0 <__muldf3> + 1006b24: 180b883a mov r5,r3 + 1006b28: 1009883a mov r4,r2 + 1006b2c: 1823883a mov r17,r3 + 1006b30: 1021883a mov r16,r2 + 1006b34: 100b88c0 call 100b88c <__fixdfsi> + 1006b38: 1009883a mov r4,r2 + 1006b3c: 102b883a mov r21,r2 + 1006b40: 100b7940 call 100b794 <__floatsidf> + 1006b44: 880b883a mov r5,r17 + 1006b48: 8009883a mov r4,r16 + 1006b4c: 180f883a mov r7,r3 + 1006b50: 100d883a mov r6,r2 + 1006b54: 100addc0 call 100addc <__subdf3> + 1006b58: 180b883a mov r5,r3 + 1006b5c: d8c00517 ldw r3,20(sp) + 1006b60: 1009883a mov r4,r2 + 1006b64: ad400c04 addi r21,r21,48 + 1006b68: 1d05883a add r2,r3,r20 + 1006b6c: 15400005 stb r21,0(r2) + 1006b70: 2021883a mov r16,r4 + 1006b74: d9000317 ldw r4,12(sp) + 1006b78: a5000044 addi r20,r20,1 + 1006b7c: 2823883a mov r17,r5 + 1006b80: a13fe11e bne r20,r4,1006b08 <_dtoa_r+0x1378> + 1006b84: e505883a add r2,fp,r20 + 1006b88: 173fffc4 addi fp,r2,-1 + 1006b8c: 0025883a mov r18,zero + 1006b90: 04cff834 movhi r19,16352 + 1006b94: b009883a mov r4,r22 + 1006b98: b80b883a mov r5,r23 + 1006b9c: 900d883a mov r6,r18 + 1006ba0: 980f883a mov r7,r19 + 1006ba4: 100ae5c0 call 100ae5c <__adddf3> + 1006ba8: 180b883a mov r5,r3 + 1006bac: 1009883a mov r4,r2 + 1006bb0: 800d883a mov r6,r16 + 1006bb4: 880f883a mov r7,r17 + 1006bb8: 100b70c0 call 100b70c <__ltdf2> + 1006bbc: 103cab16 blt r2,zero,1005e6c <_dtoa_r+0x6dc> + 1006bc0: 0009883a mov r4,zero + 1006bc4: 980b883a mov r5,r19 + 1006bc8: b80f883a mov r7,r23 + 1006bcc: b00d883a mov r6,r22 + 1006bd0: 100addc0 call 100addc <__subdf3> + 1006bd4: 180b883a mov r5,r3 + 1006bd8: 880f883a mov r7,r17 + 1006bdc: 1009883a mov r4,r2 + 1006be0: 800d883a mov r6,r16 + 1006be4: 100b5fc0 call 100b5fc <__gtdf2> + 1006be8: 00bc470e bge zero,r2,1005d08 <_dtoa_r+0x578> + 1006bec: 00c00c04 movi r3,48 + 1006bf0: e73fffc4 addi fp,fp,-1 + 1006bf4: e0800007 ldb r2,0(fp) + 1006bf8: 10fffd26 beq r2,r3,1006bf0 <_dtoa_r+0x1460> + 1006bfc: d9800417 ldw r6,16(sp) + 1006c00: e7000044 addi fp,fp,1 + 1006c04: d9800d15 stw r6,52(sp) + 1006c08: 003cab06 br 1005eb8 <_dtoa_r+0x728> + 1006c0c: d8c00f17 ldw r3,60(sp) + 1006c10: d9001117 ldw r4,68(sp) + 1006c14: 20e1c83a sub r16,r4,r3 + 1006c18: 0007883a mov r3,zero + 1006c1c: 003d9b06 br 100628c <_dtoa_r+0xafc> + 1006c20: 00800e44 movi r2,57 + 1006c24: b0800005 stb r2,0(r22) + 1006c28: b5800044 addi r22,r22,1 + 1006c2c: 003dc106 br 1006334 <_dtoa_r+0xba4> + 1006c30: 05800084 movi r22,2 + 1006c34: 003bf706 br 1005c14 <_dtoa_r+0x484> + 1006c38: d9000f17 ldw r4,60(sp) + 1006c3c: 013c000e bge zero,r4,1005c40 <_dtoa_r+0x4b0> + 1006c40: d9800e17 ldw r6,56(sp) + 1006c44: 01bc300e bge zero,r6,1005d08 <_dtoa_r+0x578> + 1006c48: 0005883a mov r2,zero + 1006c4c: 00d00934 movhi r3,16420 + 1006c50: a80b883a mov r5,r21 + 1006c54: 180f883a mov r7,r3 + 1006c58: a009883a mov r4,r20 + 1006c5c: 100d883a mov r6,r2 + 1006c60: 100aed00 call 100aed0 <__muldf3> + 1006c64: b1000044 addi r4,r22,1 + 1006c68: 1021883a mov r16,r2 + 1006c6c: 1823883a mov r17,r3 + 1006c70: 100b7940 call 100b794 <__floatsidf> + 1006c74: 880b883a mov r5,r17 + 1006c78: 8009883a mov r4,r16 + 1006c7c: 180f883a mov r7,r3 + 1006c80: 100d883a mov r6,r2 + 1006c84: 100aed00 call 100aed0 <__muldf3> + 1006c88: 0011883a mov r8,zero + 1006c8c: 02500734 movhi r9,16412 + 1006c90: 180b883a mov r5,r3 + 1006c94: 480f883a mov r7,r9 + 1006c98: 1009883a mov r4,r2 + 1006c9c: 400d883a mov r6,r8 + 1006ca0: 100ae5c0 call 100ae5c <__adddf3> + 1006ca4: 102d883a mov r22,r2 + 1006ca8: 00bf3034 movhi r2,64704 + 1006cac: 10ef883a add r23,r2,r3 + 1006cb0: d8800d17 ldw r2,52(sp) + 1006cb4: d8c00e17 ldw r3,56(sp) + 1006cb8: 8029883a mov r20,r16 + 1006cbc: 10bfffc4 addi r2,r2,-1 + 1006cc0: 882b883a mov r21,r17 + 1006cc4: d8800415 stw r2,16(sp) + 1006cc8: d8c00315 stw r3,12(sp) + 1006ccc: 003e8306 br 10066dc <_dtoa_r+0xf4c> + 1006cd0: d8800117 ldw r2,4(sp) + 1006cd4: dc001117 ldw r16,68(sp) + 1006cd8: dc801017 ldw r18,64(sp) + 1006cdc: 00c00d84 movi r3,54 + 1006ce0: 1887c83a sub r3,r3,r2 + 1006ce4: 003d6906 br 100628c <_dtoa_r+0xafc> + 1006ce8: 01800044 movi r6,1 + 1006cec: 3021883a mov r16,r6 + 1006cf0: d9800f15 stw r6,60(sp) + 1006cf4: d9802615 stw r6,152(sp) + 1006cf8: d9800e15 stw r6,56(sp) + 1006cfc: 003b9306 br 1005b4c <_dtoa_r+0x3bc> + 1006d00: b021883a mov r16,r22 + 1006d04: dd800f15 stw r22,60(sp) + 1006d08: 003b9006 br 1005b4c <_dtoa_r+0x3bc> + 1006d0c: 103e221e bne r2,zero,1006598 <_dtoa_r+0xe08> + 1006d10: b880004c andi r2,r23,1 + 1006d14: 1005003a cmpeq r2,r2,zero + 1006d18: 103e1f1e bne r2,zero,1006598 <_dtoa_r+0xe08> + 1006d1c: 003e1b06 br 100658c <_dtoa_r+0xdfc> + 1006d20: d9001617 ldw r4,88(sp) + 1006d24: 980b883a mov r5,r19 + 1006d28: 01800284 movi r6,10 + 1006d2c: 000f883a mov r7,zero + 1006d30: 1008e000 call 1008e00 <__multadd> + 1006d34: d8c00e17 ldw r3,56(sp) + 1006d38: 1027883a mov r19,r2 + 1006d3c: d8c00f15 stw r3,60(sp) + 1006d40: 003cd306 br 1006090 <_dtoa_r+0x900> + +01006d44 <_fflush_r>: + 1006d44: defffb04 addi sp,sp,-20 + 1006d48: dcc00315 stw r19,12(sp) + 1006d4c: dc800215 stw r18,8(sp) + 1006d50: dfc00415 stw ra,16(sp) + 1006d54: dc400115 stw r17,4(sp) + 1006d58: dc000015 stw r16,0(sp) + 1006d5c: 2027883a mov r19,r4 + 1006d60: 2825883a mov r18,r5 + 1006d64: 20000226 beq r4,zero,1006d70 <_fflush_r+0x2c> + 1006d68: 20800e17 ldw r2,56(r4) + 1006d6c: 10005626 beq r2,zero,1006ec8 <_fflush_r+0x184> + 1006d70: 9100030b ldhu r4,12(r18) + 1006d74: 20ffffcc andi r3,r4,65535 + 1006d78: 18e0001c xori r3,r3,32768 + 1006d7c: 18e00004 addi r3,r3,-32768 + 1006d80: 1880020c andi r2,r3,8 + 1006d84: 1000261e bne r2,zero,1006e20 <_fflush_r+0xdc> + 1006d88: 90c00117 ldw r3,4(r18) + 1006d8c: 20820014 ori r2,r4,2048 + 1006d90: 9080030d sth r2,12(r18) + 1006d94: 1009883a mov r4,r2 + 1006d98: 00c0400e bge zero,r3,1006e9c <_fflush_r+0x158> + 1006d9c: 92000a17 ldw r8,40(r18) + 1006da0: 40004026 beq r8,zero,1006ea4 <_fflush_r+0x160> + 1006da4: 2084000c andi r2,r4,4096 + 1006da8: 10005326 beq r2,zero,1006ef8 <_fflush_r+0x1b4> + 1006dac: 94001417 ldw r16,80(r18) + 1006db0: 9080030b ldhu r2,12(r18) + 1006db4: 1080010c andi r2,r2,4 + 1006db8: 1000481e bne r2,zero,1006edc <_fflush_r+0x198> + 1006dbc: 91400717 ldw r5,28(r18) + 1006dc0: 9809883a mov r4,r19 + 1006dc4: 800d883a mov r6,r16 + 1006dc8: 000f883a mov r7,zero + 1006dcc: 403ee83a callr r8 + 1006dd0: 8080261e bne r16,r2,1006e6c <_fflush_r+0x128> + 1006dd4: 9080030b ldhu r2,12(r18) + 1006dd8: 91000417 ldw r4,16(r18) + 1006ddc: 90000115 stw zero,4(r18) + 1006de0: 10bdffcc andi r2,r2,63487 + 1006de4: 10ffffcc andi r3,r2,65535 + 1006de8: 18c4000c andi r3,r3,4096 + 1006dec: 9080030d sth r2,12(r18) + 1006df0: 91000015 stw r4,0(r18) + 1006df4: 18002b26 beq r3,zero,1006ea4 <_fflush_r+0x160> + 1006df8: 0007883a mov r3,zero + 1006dfc: 1805883a mov r2,r3 + 1006e00: 94001415 stw r16,80(r18) + 1006e04: dfc00417 ldw ra,16(sp) + 1006e08: dcc00317 ldw r19,12(sp) + 1006e0c: dc800217 ldw r18,8(sp) + 1006e10: dc400117 ldw r17,4(sp) + 1006e14: dc000017 ldw r16,0(sp) + 1006e18: dec00504 addi sp,sp,20 + 1006e1c: f800283a ret + 1006e20: 94400417 ldw r17,16(r18) + 1006e24: 88001f26 beq r17,zero,1006ea4 <_fflush_r+0x160> + 1006e28: 90800017 ldw r2,0(r18) + 1006e2c: 18c000cc andi r3,r3,3 + 1006e30: 94400015 stw r17,0(r18) + 1006e34: 1461c83a sub r16,r2,r17 + 1006e38: 18002526 beq r3,zero,1006ed0 <_fflush_r+0x18c> + 1006e3c: 0005883a mov r2,zero + 1006e40: 90800215 stw r2,8(r18) + 1006e44: 0400170e bge zero,r16,1006ea4 <_fflush_r+0x160> + 1006e48: 90c00917 ldw r3,36(r18) + 1006e4c: 91400717 ldw r5,28(r18) + 1006e50: 880d883a mov r6,r17 + 1006e54: 800f883a mov r7,r16 + 1006e58: 9809883a mov r4,r19 + 1006e5c: 183ee83a callr r3 + 1006e60: 88a3883a add r17,r17,r2 + 1006e64: 80a1c83a sub r16,r16,r2 + 1006e68: 00bff616 blt zero,r2,1006e44 <_fflush_r+0x100> + 1006e6c: 9080030b ldhu r2,12(r18) + 1006e70: 00ffffc4 movi r3,-1 + 1006e74: 10801014 ori r2,r2,64 + 1006e78: 9080030d sth r2,12(r18) + 1006e7c: 1805883a mov r2,r3 + 1006e80: dfc00417 ldw ra,16(sp) + 1006e84: dcc00317 ldw r19,12(sp) + 1006e88: dc800217 ldw r18,8(sp) + 1006e8c: dc400117 ldw r17,4(sp) + 1006e90: dc000017 ldw r16,0(sp) + 1006e94: dec00504 addi sp,sp,20 + 1006e98: f800283a ret + 1006e9c: 90800f17 ldw r2,60(r18) + 1006ea0: 00bfbe16 blt zero,r2,1006d9c <_fflush_r+0x58> + 1006ea4: 0007883a mov r3,zero + 1006ea8: 1805883a mov r2,r3 + 1006eac: dfc00417 ldw ra,16(sp) + 1006eb0: dcc00317 ldw r19,12(sp) + 1006eb4: dc800217 ldw r18,8(sp) + 1006eb8: dc400117 ldw r17,4(sp) + 1006ebc: dc000017 ldw r16,0(sp) + 1006ec0: dec00504 addi sp,sp,20 + 1006ec4: f800283a ret + 1006ec8: 1006fdc0 call 1006fdc <__sinit> + 1006ecc: 003fa806 br 1006d70 <_fflush_r+0x2c> + 1006ed0: 90800517 ldw r2,20(r18) + 1006ed4: 90800215 stw r2,8(r18) + 1006ed8: 003fda06 br 1006e44 <_fflush_r+0x100> + 1006edc: 90800117 ldw r2,4(r18) + 1006ee0: 90c00c17 ldw r3,48(r18) + 1006ee4: 80a1c83a sub r16,r16,r2 + 1006ee8: 183fb426 beq r3,zero,1006dbc <_fflush_r+0x78> + 1006eec: 90800f17 ldw r2,60(r18) + 1006ef0: 80a1c83a sub r16,r16,r2 + 1006ef4: 003fb106 br 1006dbc <_fflush_r+0x78> + 1006ef8: 91400717 ldw r5,28(r18) + 1006efc: 9809883a mov r4,r19 + 1006f00: 000d883a mov r6,zero + 1006f04: 01c00044 movi r7,1 + 1006f08: 403ee83a callr r8 + 1006f0c: 1021883a mov r16,r2 + 1006f10: 00bfffc4 movi r2,-1 + 1006f14: 80800226 beq r16,r2,1006f20 <_fflush_r+0x1dc> + 1006f18: 92000a17 ldw r8,40(r18) + 1006f1c: 003fa406 br 1006db0 <_fflush_r+0x6c> + 1006f20: 98c00017 ldw r3,0(r19) + 1006f24: 00800744 movi r2,29 + 1006f28: 18bfde26 beq r3,r2,1006ea4 <_fflush_r+0x160> + 1006f2c: 9080030b ldhu r2,12(r18) + 1006f30: 8007883a mov r3,r16 + 1006f34: 10801014 ori r2,r2,64 + 1006f38: 9080030d sth r2,12(r18) + 1006f3c: 003fcf06 br 1006e7c <_fflush_r+0x138> + +01006f40 : + 1006f40: 01404034 movhi r5,256 + 1006f44: 295b5104 addi r5,r5,27972 + 1006f48: 2007883a mov r3,r4 + 1006f4c: 20000526 beq r4,zero,1006f64 + 1006f50: 008040b4 movhi r2,258 + 1006f54: 10ab9804 addi r2,r2,-20896 + 1006f58: 11000017 ldw r4,0(r2) + 1006f5c: 180b883a mov r5,r3 + 1006f60: 1006d441 jmpi 1006d44 <_fflush_r> + 1006f64: 008040b4 movhi r2,258 + 1006f68: 10ab9904 addi r2,r2,-20892 + 1006f6c: 11000017 ldw r4,0(r2) + 1006f70: 1007b101 jmpi 1007b10 <_fwalk_reent> + +01006f74 : + 1006f74: 00804074 movhi r2,257 + 1006f78: 10a5e904 addi r2,r2,-26716 + 1006f7c: 20800b15 stw r2,44(r4) + 1006f80: 00804074 movhi r2,257 + 1006f84: 10a62404 addi r2,r2,-26480 + 1006f88: 20800815 stw r2,32(r4) + 1006f8c: 00c04074 movhi r3,257 + 1006f90: 18e60504 addi r3,r3,-26604 + 1006f94: 00804074 movhi r2,257 + 1006f98: 10a5eb04 addi r2,r2,-26708 + 1006f9c: 2140030d sth r5,12(r4) + 1006fa0: 2180038d sth r6,14(r4) + 1006fa4: 20c00915 stw r3,36(r4) + 1006fa8: 20800a15 stw r2,40(r4) + 1006fac: 20000015 stw zero,0(r4) + 1006fb0: 20000115 stw zero,4(r4) + 1006fb4: 20000215 stw zero,8(r4) + 1006fb8: 20000415 stw zero,16(r4) + 1006fbc: 20000515 stw zero,20(r4) + 1006fc0: 20000615 stw zero,24(r4) + 1006fc4: 21000715 stw r4,28(r4) + 1006fc8: f800283a ret + +01006fcc <__sfp_lock_acquire>: + 1006fcc: f800283a ret + +01006fd0 <__sfp_lock_release>: + 1006fd0: f800283a ret + +01006fd4 <__sinit_lock_acquire>: + 1006fd4: f800283a ret + +01006fd8 <__sinit_lock_release>: + 1006fd8: f800283a ret + +01006fdc <__sinit>: + 1006fdc: 20800e17 ldw r2,56(r4) + 1006fe0: defffd04 addi sp,sp,-12 + 1006fe4: dc400115 stw r17,4(sp) + 1006fe8: dc000015 stw r16,0(sp) + 1006fec: dfc00215 stw ra,8(sp) + 1006ff0: 04400044 movi r17,1 + 1006ff4: 01400104 movi r5,4 + 1006ff8: 000d883a mov r6,zero + 1006ffc: 2021883a mov r16,r4 + 1007000: 2200bb04 addi r8,r4,748 + 1007004: 200f883a mov r7,r4 + 1007008: 10000526 beq r2,zero,1007020 <__sinit+0x44> + 100700c: dfc00217 ldw ra,8(sp) + 1007010: dc400117 ldw r17,4(sp) + 1007014: dc000017 ldw r16,0(sp) + 1007018: dec00304 addi sp,sp,12 + 100701c: f800283a ret + 1007020: 21000117 ldw r4,4(r4) + 1007024: 00804034 movhi r2,256 + 1007028: 109c3004 addi r2,r2,28864 + 100702c: 00c000c4 movi r3,3 + 1007030: 80800f15 stw r2,60(r16) + 1007034: 80c0b915 stw r3,740(r16) + 1007038: 8200ba15 stw r8,744(r16) + 100703c: 84400e15 stw r17,56(r16) + 1007040: 8000b815 stw zero,736(r16) + 1007044: 1006f740 call 1006f74 + 1007048: 81000217 ldw r4,8(r16) + 100704c: 880d883a mov r6,r17 + 1007050: 800f883a mov r7,r16 + 1007054: 01400284 movi r5,10 + 1007058: 1006f740 call 1006f74 + 100705c: 81000317 ldw r4,12(r16) + 1007060: 800f883a mov r7,r16 + 1007064: 01400484 movi r5,18 + 1007068: 01800084 movi r6,2 + 100706c: dfc00217 ldw ra,8(sp) + 1007070: dc400117 ldw r17,4(sp) + 1007074: dc000017 ldw r16,0(sp) + 1007078: dec00304 addi sp,sp,12 + 100707c: 1006f741 jmpi 1006f74 + +01007080 <__fp_lock>: + 1007080: 0005883a mov r2,zero + 1007084: f800283a ret + +01007088 <__fp_unlock>: + 1007088: 0005883a mov r2,zero + 100708c: f800283a ret + +01007090 <__fp_unlock_all>: + 1007090: 008040b4 movhi r2,258 + 1007094: 10ab9804 addi r2,r2,-20896 + 1007098: 11000017 ldw r4,0(r2) + 100709c: 01404034 movhi r5,256 + 10070a0: 295c2204 addi r5,r5,28808 + 10070a4: 1007bd81 jmpi 1007bd8 <_fwalk> + +010070a8 <__fp_lock_all>: + 10070a8: 008040b4 movhi r2,258 + 10070ac: 10ab9804 addi r2,r2,-20896 + 10070b0: 11000017 ldw r4,0(r2) + 10070b4: 01404034 movhi r5,256 + 10070b8: 295c2004 addi r5,r5,28800 + 10070bc: 1007bd81 jmpi 1007bd8 <_fwalk> + +010070c0 <_cleanup_r>: + 10070c0: 01404074 movhi r5,257 + 10070c4: 29671604 addi r5,r5,-25512 + 10070c8: 1007bd81 jmpi 1007bd8 <_fwalk> + +010070cc <_cleanup>: + 10070cc: 008040b4 movhi r2,258 + 10070d0: 10ab9904 addi r2,r2,-20892 + 10070d4: 11000017 ldw r4,0(r2) + 10070d8: 10070c01 jmpi 10070c0 <_cleanup_r> + +010070dc <__sfmoreglue>: + 10070dc: defffc04 addi sp,sp,-16 + 10070e0: dc400115 stw r17,4(sp) + 10070e4: 2c401724 muli r17,r5,92 + 10070e8: dc800215 stw r18,8(sp) + 10070ec: 2825883a mov r18,r5 + 10070f0: 89400304 addi r5,r17,12 + 10070f4: dc000015 stw r16,0(sp) + 10070f8: dfc00315 stw ra,12(sp) + 10070fc: 10027dc0 call 10027dc <_malloc_r> + 1007100: 0021883a mov r16,zero + 1007104: 880d883a mov r6,r17 + 1007108: 000b883a mov r5,zero + 100710c: 10000626 beq r2,zero,1007128 <__sfmoreglue+0x4c> + 1007110: 11000304 addi r4,r2,12 + 1007114: 14800115 stw r18,4(r2) + 1007118: 10000015 stw zero,0(r2) + 100711c: 11000215 stw r4,8(r2) + 1007120: 1021883a mov r16,r2 + 1007124: 1002f1c0 call 1002f1c + 1007128: 8005883a mov r2,r16 + 100712c: dfc00317 ldw ra,12(sp) + 1007130: dc800217 ldw r18,8(sp) + 1007134: dc400117 ldw r17,4(sp) + 1007138: dc000017 ldw r16,0(sp) + 100713c: dec00404 addi sp,sp,16 + 1007140: f800283a ret + +01007144 <__sfp>: + 1007144: defffd04 addi sp,sp,-12 + 1007148: 008040b4 movhi r2,258 + 100714c: 10ab9904 addi r2,r2,-20892 + 1007150: dc000015 stw r16,0(sp) + 1007154: 14000017 ldw r16,0(r2) + 1007158: dc400115 stw r17,4(sp) + 100715c: dfc00215 stw ra,8(sp) + 1007160: 80800e17 ldw r2,56(r16) + 1007164: 2023883a mov r17,r4 + 1007168: 10002626 beq r2,zero,1007204 <__sfp+0xc0> + 100716c: 8400b804 addi r16,r16,736 + 1007170: 80800117 ldw r2,4(r16) + 1007174: 81000217 ldw r4,8(r16) + 1007178: 10ffffc4 addi r3,r2,-1 + 100717c: 18000916 blt r3,zero,10071a4 <__sfp+0x60> + 1007180: 2080030f ldh r2,12(r4) + 1007184: 10000b26 beq r2,zero,10071b4 <__sfp+0x70> + 1007188: 017fffc4 movi r5,-1 + 100718c: 00000206 br 1007198 <__sfp+0x54> + 1007190: 2080030f ldh r2,12(r4) + 1007194: 10000726 beq r2,zero,10071b4 <__sfp+0x70> + 1007198: 18ffffc4 addi r3,r3,-1 + 100719c: 21001704 addi r4,r4,92 + 10071a0: 197ffb1e bne r3,r5,1007190 <__sfp+0x4c> + 10071a4: 80800017 ldw r2,0(r16) + 10071a8: 10001926 beq r2,zero,1007210 <__sfp+0xcc> + 10071ac: 1021883a mov r16,r2 + 10071b0: 003fef06 br 1007170 <__sfp+0x2c> + 10071b4: 00bfffc4 movi r2,-1 + 10071b8: 00c00044 movi r3,1 + 10071bc: 2080038d sth r2,14(r4) + 10071c0: 20c0030d sth r3,12(r4) + 10071c4: 20000015 stw zero,0(r4) + 10071c8: 20000215 stw zero,8(r4) + 10071cc: 20000115 stw zero,4(r4) + 10071d0: 20000415 stw zero,16(r4) + 10071d4: 20000515 stw zero,20(r4) + 10071d8: 20000615 stw zero,24(r4) + 10071dc: 20000c15 stw zero,48(r4) + 10071e0: 20000d15 stw zero,52(r4) + 10071e4: 20001115 stw zero,68(r4) + 10071e8: 20001215 stw zero,72(r4) + 10071ec: 2005883a mov r2,r4 + 10071f0: dfc00217 ldw ra,8(sp) + 10071f4: dc400117 ldw r17,4(sp) + 10071f8: dc000017 ldw r16,0(sp) + 10071fc: dec00304 addi sp,sp,12 + 1007200: f800283a ret + 1007204: 8009883a mov r4,r16 + 1007208: 1006fdc0 call 1006fdc <__sinit> + 100720c: 003fd706 br 100716c <__sfp+0x28> + 1007210: 8809883a mov r4,r17 + 1007214: 01400104 movi r5,4 + 1007218: 10070dc0 call 10070dc <__sfmoreglue> + 100721c: 80800015 stw r2,0(r16) + 1007220: 103fe21e bne r2,zero,10071ac <__sfp+0x68> + 1007224: 00800304 movi r2,12 + 1007228: 0009883a mov r4,zero + 100722c: 88800015 stw r2,0(r17) + 1007230: 003fee06 br 10071ec <__sfp+0xa8> + +01007234 <_malloc_trim_r>: + 1007234: defffb04 addi sp,sp,-20 + 1007238: dcc00315 stw r19,12(sp) + 100723c: 04c040b4 movhi r19,258 + 1007240: 9ce49004 addi r19,r19,-28096 + 1007244: dc800215 stw r18,8(sp) + 1007248: dc400115 stw r17,4(sp) + 100724c: dc000015 stw r16,0(sp) + 1007250: 2823883a mov r17,r5 + 1007254: 2025883a mov r18,r4 + 1007258: dfc00415 stw ra,16(sp) + 100725c: 100d0a00 call 100d0a0 <__malloc_lock> + 1007260: 98800217 ldw r2,8(r19) + 1007264: 9009883a mov r4,r18 + 1007268: 000b883a mov r5,zero + 100726c: 10c00117 ldw r3,4(r2) + 1007270: 00bfff04 movi r2,-4 + 1007274: 18a0703a and r16,r3,r2 + 1007278: 8463c83a sub r17,r16,r17 + 100727c: 8c43fbc4 addi r17,r17,4079 + 1007280: 8822d33a srli r17,r17,12 + 1007284: 0083ffc4 movi r2,4095 + 1007288: 8c7fffc4 addi r17,r17,-1 + 100728c: 8822933a slli r17,r17,12 + 1007290: 1440060e bge r2,r17,10072ac <_malloc_trim_r+0x78> + 1007294: 10030e00 call 10030e0 <_sbrk_r> + 1007298: 98c00217 ldw r3,8(r19) + 100729c: 9009883a mov r4,r18 + 10072a0: 044bc83a sub r5,zero,r17 + 10072a4: 80c7883a add r3,r16,r3 + 10072a8: 10c00926 beq r2,r3,10072d0 <_malloc_trim_r+0x9c> + 10072ac: 100d1a80 call 100d1a8 <__malloc_unlock> + 10072b0: 0005883a mov r2,zero + 10072b4: dfc00417 ldw ra,16(sp) + 10072b8: dcc00317 ldw r19,12(sp) + 10072bc: dc800217 ldw r18,8(sp) + 10072c0: dc400117 ldw r17,4(sp) + 10072c4: dc000017 ldw r16,0(sp) + 10072c8: dec00504 addi sp,sp,20 + 10072cc: f800283a ret + 10072d0: 9009883a mov r4,r18 + 10072d4: 10030e00 call 10030e0 <_sbrk_r> + 10072d8: 844dc83a sub r6,r16,r17 + 10072dc: 00ffffc4 movi r3,-1 + 10072e0: 9009883a mov r4,r18 + 10072e4: 000b883a mov r5,zero + 10072e8: 01c040b4 movhi r7,258 + 10072ec: 39cd2b04 addi r7,r7,13484 + 10072f0: 31800054 ori r6,r6,1 + 10072f4: 10c00926 beq r2,r3,100731c <_malloc_trim_r+0xe8> + 10072f8: 38800017 ldw r2,0(r7) + 10072fc: 98c00217 ldw r3,8(r19) + 1007300: 9009883a mov r4,r18 + 1007304: 1445c83a sub r2,r2,r17 + 1007308: 38800015 stw r2,0(r7) + 100730c: 19800115 stw r6,4(r3) + 1007310: 100d1a80 call 100d1a8 <__malloc_unlock> + 1007314: 00800044 movi r2,1 + 1007318: 003fe606 br 10072b4 <_malloc_trim_r+0x80> + 100731c: 10030e00 call 10030e0 <_sbrk_r> + 1007320: 99800217 ldw r6,8(r19) + 1007324: 100f883a mov r7,r2 + 1007328: 9009883a mov r4,r18 + 100732c: 1187c83a sub r3,r2,r6 + 1007330: 008003c4 movi r2,15 + 1007334: 19400054 ori r5,r3,1 + 1007338: 10ffdc0e bge r2,r3,10072ac <_malloc_trim_r+0x78> + 100733c: 008040b4 movhi r2,258 + 1007340: 10ab9704 addi r2,r2,-20900 + 1007344: 10c00017 ldw r3,0(r2) + 1007348: 008040b4 movhi r2,258 + 100734c: 108d2b04 addi r2,r2,13484 + 1007350: 31400115 stw r5,4(r6) + 1007354: 38c7c83a sub r3,r7,r3 + 1007358: 10c00015 stw r3,0(r2) + 100735c: 003fd306 br 10072ac <_malloc_trim_r+0x78> + +01007360 <_free_r>: + 1007360: defffd04 addi sp,sp,-12 + 1007364: dc400115 stw r17,4(sp) + 1007368: dc000015 stw r16,0(sp) + 100736c: dfc00215 stw ra,8(sp) + 1007370: 2821883a mov r16,r5 + 1007374: 2023883a mov r17,r4 + 1007378: 28005a26 beq r5,zero,10074e4 <_free_r+0x184> + 100737c: 100d0a00 call 100d0a0 <__malloc_lock> + 1007380: 823ffe04 addi r8,r16,-8 + 1007384: 41400117 ldw r5,4(r8) + 1007388: 00bfff84 movi r2,-2 + 100738c: 028040b4 movhi r10,258 + 1007390: 52a49004 addi r10,r10,-28096 + 1007394: 288e703a and r7,r5,r2 + 1007398: 41cd883a add r6,r8,r7 + 100739c: 30c00117 ldw r3,4(r6) + 10073a0: 51000217 ldw r4,8(r10) + 10073a4: 00bfff04 movi r2,-4 + 10073a8: 1892703a and r9,r3,r2 + 10073ac: 5017883a mov r11,r10 + 10073b0: 31006726 beq r6,r4,1007550 <_free_r+0x1f0> + 10073b4: 2880004c andi r2,r5,1 + 10073b8: 1005003a cmpeq r2,r2,zero + 10073bc: 32400115 stw r9,4(r6) + 10073c0: 10001a1e bne r2,zero,100742c <_free_r+0xcc> + 10073c4: 000b883a mov r5,zero + 10073c8: 3247883a add r3,r6,r9 + 10073cc: 18800117 ldw r2,4(r3) + 10073d0: 1080004c andi r2,r2,1 + 10073d4: 1000231e bne r2,zero,1007464 <_free_r+0x104> + 10073d8: 280ac03a cmpne r5,r5,zero + 10073dc: 3a4f883a add r7,r7,r9 + 10073e0: 2800451e bne r5,zero,10074f8 <_free_r+0x198> + 10073e4: 31000217 ldw r4,8(r6) + 10073e8: 008040b4 movhi r2,258 + 10073ec: 10a49204 addi r2,r2,-28088 + 10073f0: 20807b26 beq r4,r2,10075e0 <_free_r+0x280> + 10073f4: 30800317 ldw r2,12(r6) + 10073f8: 3a07883a add r3,r7,r8 + 10073fc: 19c00015 stw r7,0(r3) + 1007400: 11000215 stw r4,8(r2) + 1007404: 20800315 stw r2,12(r4) + 1007408: 38800054 ori r2,r7,1 + 100740c: 40800115 stw r2,4(r8) + 1007410: 28001a26 beq r5,zero,100747c <_free_r+0x11c> + 1007414: 8809883a mov r4,r17 + 1007418: dfc00217 ldw ra,8(sp) + 100741c: dc400117 ldw r17,4(sp) + 1007420: dc000017 ldw r16,0(sp) + 1007424: dec00304 addi sp,sp,12 + 1007428: 100d1a81 jmpi 100d1a8 <__malloc_unlock> + 100742c: 80bffe17 ldw r2,-8(r16) + 1007430: 50c00204 addi r3,r10,8 + 1007434: 4091c83a sub r8,r8,r2 + 1007438: 41000217 ldw r4,8(r8) + 100743c: 388f883a add r7,r7,r2 + 1007440: 20c06126 beq r4,r3,10075c8 <_free_r+0x268> + 1007444: 40800317 ldw r2,12(r8) + 1007448: 3247883a add r3,r6,r9 + 100744c: 000b883a mov r5,zero + 1007450: 11000215 stw r4,8(r2) + 1007454: 20800315 stw r2,12(r4) + 1007458: 18800117 ldw r2,4(r3) + 100745c: 1080004c andi r2,r2,1 + 1007460: 103fdd26 beq r2,zero,10073d8 <_free_r+0x78> + 1007464: 38800054 ori r2,r7,1 + 1007468: 3a07883a add r3,r7,r8 + 100746c: 280ac03a cmpne r5,r5,zero + 1007470: 40800115 stw r2,4(r8) + 1007474: 19c00015 stw r7,0(r3) + 1007478: 283fe61e bne r5,zero,1007414 <_free_r+0xb4> + 100747c: 00807fc4 movi r2,511 + 1007480: 11c01f2e bgeu r2,r7,1007500 <_free_r+0x1a0> + 1007484: 3806d27a srli r3,r7,9 + 1007488: 1800481e bne r3,zero,10075ac <_free_r+0x24c> + 100748c: 3804d0fa srli r2,r7,3 + 1007490: 100690fa slli r3,r2,3 + 1007494: 1acd883a add r6,r3,r11 + 1007498: 31400217 ldw r5,8(r6) + 100749c: 31405926 beq r6,r5,1007604 <_free_r+0x2a4> + 10074a0: 28800117 ldw r2,4(r5) + 10074a4: 00ffff04 movi r3,-4 + 10074a8: 10c4703a and r2,r2,r3 + 10074ac: 3880022e bgeu r7,r2,10074b8 <_free_r+0x158> + 10074b0: 29400217 ldw r5,8(r5) + 10074b4: 317ffa1e bne r6,r5,10074a0 <_free_r+0x140> + 10074b8: 29800317 ldw r6,12(r5) + 10074bc: 41800315 stw r6,12(r8) + 10074c0: 41400215 stw r5,8(r8) + 10074c4: 8809883a mov r4,r17 + 10074c8: 2a000315 stw r8,12(r5) + 10074cc: 32000215 stw r8,8(r6) + 10074d0: dfc00217 ldw ra,8(sp) + 10074d4: dc400117 ldw r17,4(sp) + 10074d8: dc000017 ldw r16,0(sp) + 10074dc: dec00304 addi sp,sp,12 + 10074e0: 100d1a81 jmpi 100d1a8 <__malloc_unlock> + 10074e4: dfc00217 ldw ra,8(sp) + 10074e8: dc400117 ldw r17,4(sp) + 10074ec: dc000017 ldw r16,0(sp) + 10074f0: dec00304 addi sp,sp,12 + 10074f4: f800283a ret + 10074f8: 31000217 ldw r4,8(r6) + 10074fc: 003fbd06 br 10073f4 <_free_r+0x94> + 1007500: 3806d0fa srli r3,r7,3 + 1007504: 00800044 movi r2,1 + 1007508: 51400117 ldw r5,4(r10) + 100750c: 180890fa slli r4,r3,3 + 1007510: 1807d0ba srai r3,r3,2 + 1007514: 22c9883a add r4,r4,r11 + 1007518: 21800217 ldw r6,8(r4) + 100751c: 10c4983a sll r2,r2,r3 + 1007520: 41000315 stw r4,12(r8) + 1007524: 41800215 stw r6,8(r8) + 1007528: 288ab03a or r5,r5,r2 + 100752c: 22000215 stw r8,8(r4) + 1007530: 8809883a mov r4,r17 + 1007534: 51400115 stw r5,4(r10) + 1007538: 32000315 stw r8,12(r6) + 100753c: dfc00217 ldw ra,8(sp) + 1007540: dc400117 ldw r17,4(sp) + 1007544: dc000017 ldw r16,0(sp) + 1007548: dec00304 addi sp,sp,12 + 100754c: 100d1a81 jmpi 100d1a8 <__malloc_unlock> + 1007550: 2880004c andi r2,r5,1 + 1007554: 3a4d883a add r6,r7,r9 + 1007558: 1000071e bne r2,zero,1007578 <_free_r+0x218> + 100755c: 80bffe17 ldw r2,-8(r16) + 1007560: 4091c83a sub r8,r8,r2 + 1007564: 41000317 ldw r4,12(r8) + 1007568: 40c00217 ldw r3,8(r8) + 100756c: 308d883a add r6,r6,r2 + 1007570: 20c00215 stw r3,8(r4) + 1007574: 19000315 stw r4,12(r3) + 1007578: 008040b4 movhi r2,258 + 100757c: 10ab9604 addi r2,r2,-20904 + 1007580: 11000017 ldw r4,0(r2) + 1007584: 30c00054 ori r3,r6,1 + 1007588: 52000215 stw r8,8(r10) + 100758c: 40c00115 stw r3,4(r8) + 1007590: 313fa036 bltu r6,r4,1007414 <_free_r+0xb4> + 1007594: 008040b4 movhi r2,258 + 1007598: 10b30104 addi r2,r2,-13308 + 100759c: 11400017 ldw r5,0(r2) + 10075a0: 8809883a mov r4,r17 + 10075a4: 10072340 call 1007234 <_malloc_trim_r> + 10075a8: 003f9a06 br 1007414 <_free_r+0xb4> + 10075ac: 00800104 movi r2,4 + 10075b0: 10c0072e bgeu r2,r3,10075d0 <_free_r+0x270> + 10075b4: 00800504 movi r2,20 + 10075b8: 10c01936 bltu r2,r3,1007620 <_free_r+0x2c0> + 10075bc: 188016c4 addi r2,r3,91 + 10075c0: 100690fa slli r3,r2,3 + 10075c4: 003fb306 br 1007494 <_free_r+0x134> + 10075c8: 01400044 movi r5,1 + 10075cc: 003f7e06 br 10073c8 <_free_r+0x68> + 10075d0: 3804d1ba srli r2,r7,6 + 10075d4: 10800e04 addi r2,r2,56 + 10075d8: 100690fa slli r3,r2,3 + 10075dc: 003fad06 br 1007494 <_free_r+0x134> + 10075e0: 22000315 stw r8,12(r4) + 10075e4: 22000215 stw r8,8(r4) + 10075e8: 3a05883a add r2,r7,r8 + 10075ec: 38c00054 ori r3,r7,1 + 10075f0: 11c00015 stw r7,0(r2) + 10075f4: 41000215 stw r4,8(r8) + 10075f8: 40c00115 stw r3,4(r8) + 10075fc: 41000315 stw r4,12(r8) + 1007600: 003f8406 br 1007414 <_free_r+0xb4> + 1007604: 1005d0ba srai r2,r2,2 + 1007608: 00c00044 movi r3,1 + 100760c: 51000117 ldw r4,4(r10) + 1007610: 1886983a sll r3,r3,r2 + 1007614: 20c8b03a or r4,r4,r3 + 1007618: 51000115 stw r4,4(r10) + 100761c: 003fa706 br 10074bc <_free_r+0x15c> + 1007620: 00801504 movi r2,84 + 1007624: 10c00436 bltu r2,r3,1007638 <_free_r+0x2d8> + 1007628: 3804d33a srli r2,r7,12 + 100762c: 10801b84 addi r2,r2,110 + 1007630: 100690fa slli r3,r2,3 + 1007634: 003f9706 br 1007494 <_free_r+0x134> + 1007638: 00805504 movi r2,340 + 100763c: 10c00436 bltu r2,r3,1007650 <_free_r+0x2f0> + 1007640: 3804d3fa srli r2,r7,15 + 1007644: 10801dc4 addi r2,r2,119 + 1007648: 100690fa slli r3,r2,3 + 100764c: 003f9106 br 1007494 <_free_r+0x134> + 1007650: 00815504 movi r2,1364 + 1007654: 10c0032e bgeu r2,r3,1007664 <_free_r+0x304> + 1007658: 00801f84 movi r2,126 + 100765c: 00c0fc04 movi r3,1008 + 1007660: 003f8c06 br 1007494 <_free_r+0x134> + 1007664: 3804d4ba srli r2,r7,18 + 1007668: 10801f04 addi r2,r2,124 + 100766c: 100690fa slli r3,r2,3 + 1007670: 003f8806 br 1007494 <_free_r+0x134> + +01007674 <__sfvwrite_r>: + 1007674: 30800217 ldw r2,8(r6) + 1007678: defff504 addi sp,sp,-44 + 100767c: df000915 stw fp,36(sp) + 1007680: dd800715 stw r22,28(sp) + 1007684: dc800315 stw r18,12(sp) + 1007688: dfc00a15 stw ra,40(sp) + 100768c: ddc00815 stw r23,32(sp) + 1007690: dd400615 stw r21,24(sp) + 1007694: dd000515 stw r20,20(sp) + 1007698: dcc00415 stw r19,16(sp) + 100769c: dc400215 stw r17,8(sp) + 10076a0: dc000115 stw r16,4(sp) + 10076a4: 302d883a mov r22,r6 + 10076a8: 2039883a mov fp,r4 + 10076ac: 2825883a mov r18,r5 + 10076b0: 10001c26 beq r2,zero,1007724 <__sfvwrite_r+0xb0> + 10076b4: 29c0030b ldhu r7,12(r5) + 10076b8: 3880020c andi r2,r7,8 + 10076bc: 10002726 beq r2,zero,100775c <__sfvwrite_r+0xe8> + 10076c0: 28800417 ldw r2,16(r5) + 10076c4: 10002526 beq r2,zero,100775c <__sfvwrite_r+0xe8> + 10076c8: 3880008c andi r2,r7,2 + 10076cc: b5400017 ldw r21,0(r22) + 10076d0: 10002826 beq r2,zero,1007774 <__sfvwrite_r+0x100> + 10076d4: 0021883a mov r16,zero + 10076d8: 0023883a mov r17,zero + 10076dc: 880d883a mov r6,r17 + 10076e0: e009883a mov r4,fp + 10076e4: 00810004 movi r2,1024 + 10076e8: 80006e26 beq r16,zero,10078a4 <__sfvwrite_r+0x230> + 10076ec: 800f883a mov r7,r16 + 10076f0: 91400717 ldw r5,28(r18) + 10076f4: 1400012e bgeu r2,r16,10076fc <__sfvwrite_r+0x88> + 10076f8: 100f883a mov r7,r2 + 10076fc: 90c00917 ldw r3,36(r18) + 1007700: 183ee83a callr r3 + 1007704: 1007883a mov r3,r2 + 1007708: 80a1c83a sub r16,r16,r2 + 100770c: 88a3883a add r17,r17,r2 + 1007710: 00806d0e bge zero,r2,10078c8 <__sfvwrite_r+0x254> + 1007714: b0800217 ldw r2,8(r22) + 1007718: 10c5c83a sub r2,r2,r3 + 100771c: b0800215 stw r2,8(r22) + 1007720: 103fee1e bne r2,zero,10076dc <__sfvwrite_r+0x68> + 1007724: 0009883a mov r4,zero + 1007728: 2005883a mov r2,r4 + 100772c: dfc00a17 ldw ra,40(sp) + 1007730: df000917 ldw fp,36(sp) + 1007734: ddc00817 ldw r23,32(sp) + 1007738: dd800717 ldw r22,28(sp) + 100773c: dd400617 ldw r21,24(sp) + 1007740: dd000517 ldw r20,20(sp) + 1007744: dcc00417 ldw r19,16(sp) + 1007748: dc800317 ldw r18,12(sp) + 100774c: dc400217 ldw r17,8(sp) + 1007750: dc000117 ldw r16,4(sp) + 1007754: dec00b04 addi sp,sp,44 + 1007758: f800283a ret + 100775c: 100543c0 call 100543c <__swsetup_r> + 1007760: 1000e41e bne r2,zero,1007af4 <__sfvwrite_r+0x480> + 1007764: 91c0030b ldhu r7,12(r18) + 1007768: b5400017 ldw r21,0(r22) + 100776c: 3880008c andi r2,r7,2 + 1007770: 103fd81e bne r2,zero,10076d4 <__sfvwrite_r+0x60> + 1007774: 3880004c andi r2,r7,1 + 1007778: 1005003a cmpeq r2,r2,zero + 100777c: 10005726 beq r2,zero,10078dc <__sfvwrite_r+0x268> + 1007780: 0029883a mov r20,zero + 1007784: 002f883a mov r23,zero + 1007788: a0004226 beq r20,zero,1007894 <__sfvwrite_r+0x220> + 100778c: 3880800c andi r2,r7,512 + 1007790: 94000217 ldw r16,8(r18) + 1007794: 10008b26 beq r2,zero,10079c4 <__sfvwrite_r+0x350> + 1007798: 800d883a mov r6,r16 + 100779c: a400a536 bltu r20,r16,1007a34 <__sfvwrite_r+0x3c0> + 10077a0: 3881200c andi r2,r7,1152 + 10077a4: 10002726 beq r2,zero,1007844 <__sfvwrite_r+0x1d0> + 10077a8: 90800517 ldw r2,20(r18) + 10077ac: 92000417 ldw r8,16(r18) + 10077b0: 91400017 ldw r5,0(r18) + 10077b4: 1087883a add r3,r2,r2 + 10077b8: 1887883a add r3,r3,r2 + 10077bc: 1808d7fa srli r4,r3,31 + 10077c0: 2a21c83a sub r16,r5,r8 + 10077c4: 80800044 addi r2,r16,1 + 10077c8: 20c9883a add r4,r4,r3 + 10077cc: 2027d07a srai r19,r4,1 + 10077d0: a085883a add r2,r20,r2 + 10077d4: 980d883a mov r6,r19 + 10077d8: 9880022e bgeu r19,r2,10077e4 <__sfvwrite_r+0x170> + 10077dc: 1027883a mov r19,r2 + 10077e0: 100d883a mov r6,r2 + 10077e4: 3881000c andi r2,r7,1024 + 10077e8: 1000b826 beq r2,zero,1007acc <__sfvwrite_r+0x458> + 10077ec: 300b883a mov r5,r6 + 10077f0: e009883a mov r4,fp + 10077f4: 10027dc0 call 10027dc <_malloc_r> + 10077f8: 10003126 beq r2,zero,10078c0 <__sfvwrite_r+0x24c> + 10077fc: 91400417 ldw r5,16(r18) + 1007800: 1009883a mov r4,r2 + 1007804: 800d883a mov r6,r16 + 1007808: 1023883a mov r17,r2 + 100780c: 1007fcc0 call 1007fcc + 1007810: 90c0030b ldhu r3,12(r18) + 1007814: 00beffc4 movi r2,-1025 + 1007818: 1886703a and r3,r3,r2 + 100781c: 18c02014 ori r3,r3,128 + 1007820: 90c0030d sth r3,12(r18) + 1007824: 9c07c83a sub r3,r19,r16 + 1007828: 8c05883a add r2,r17,r16 + 100782c: a00d883a mov r6,r20 + 1007830: a021883a mov r16,r20 + 1007834: 90800015 stw r2,0(r18) + 1007838: 90c00215 stw r3,8(r18) + 100783c: 94400415 stw r17,16(r18) + 1007840: 94c00515 stw r19,20(r18) + 1007844: 91000017 ldw r4,0(r18) + 1007848: b80b883a mov r5,r23 + 100784c: a023883a mov r17,r20 + 1007850: 100806c0 call 100806c + 1007854: 90c00217 ldw r3,8(r18) + 1007858: 90800017 ldw r2,0(r18) + 100785c: a027883a mov r19,r20 + 1007860: 1c07c83a sub r3,r3,r16 + 1007864: 1405883a add r2,r2,r16 + 1007868: 90c00215 stw r3,8(r18) + 100786c: a021883a mov r16,r20 + 1007870: 90800015 stw r2,0(r18) + 1007874: b0800217 ldw r2,8(r22) + 1007878: 1405c83a sub r2,r2,r16 + 100787c: b0800215 stw r2,8(r22) + 1007880: 103fa826 beq r2,zero,1007724 <__sfvwrite_r+0xb0> + 1007884: a469c83a sub r20,r20,r17 + 1007888: 91c0030b ldhu r7,12(r18) + 100788c: bcef883a add r23,r23,r19 + 1007890: a03fbe1e bne r20,zero,100778c <__sfvwrite_r+0x118> + 1007894: adc00017 ldw r23,0(r21) + 1007898: ad000117 ldw r20,4(r21) + 100789c: ad400204 addi r21,r21,8 + 10078a0: 003fb906 br 1007788 <__sfvwrite_r+0x114> + 10078a4: ac400017 ldw r17,0(r21) + 10078a8: ac000117 ldw r16,4(r21) + 10078ac: ad400204 addi r21,r21,8 + 10078b0: 003f8a06 br 10076dc <__sfvwrite_r+0x68> + 10078b4: 91400417 ldw r5,16(r18) + 10078b8: e009883a mov r4,fp + 10078bc: 10073600 call 1007360 <_free_r> + 10078c0: 00800304 movi r2,12 + 10078c4: e0800015 stw r2,0(fp) + 10078c8: 9080030b ldhu r2,12(r18) + 10078cc: 013fffc4 movi r4,-1 + 10078d0: 10801014 ori r2,r2,64 + 10078d4: 9080030d sth r2,12(r18) + 10078d8: 003f9306 br 1007728 <__sfvwrite_r+0xb4> + 10078dc: 0027883a mov r19,zero + 10078e0: 002f883a mov r23,zero + 10078e4: d8000015 stw zero,0(sp) + 10078e8: 0029883a mov r20,zero + 10078ec: 98001e26 beq r19,zero,1007968 <__sfvwrite_r+0x2f4> + 10078f0: d8c00017 ldw r3,0(sp) + 10078f4: 1804c03a cmpne r2,r3,zero + 10078f8: 10005e26 beq r2,zero,1007a74 <__sfvwrite_r+0x400> + 10078fc: 9821883a mov r16,r19 + 1007900: a4c0012e bgeu r20,r19,1007908 <__sfvwrite_r+0x294> + 1007904: a021883a mov r16,r20 + 1007908: 91000017 ldw r4,0(r18) + 100790c: 90800417 ldw r2,16(r18) + 1007910: 91800217 ldw r6,8(r18) + 1007914: 91c00517 ldw r7,20(r18) + 1007918: 1100022e bgeu r2,r4,1007924 <__sfvwrite_r+0x2b0> + 100791c: 31e3883a add r17,r6,r7 + 1007920: 8c001616 blt r17,r16,100797c <__sfvwrite_r+0x308> + 1007924: 81c03816 blt r16,r7,1007a08 <__sfvwrite_r+0x394> + 1007928: 90c00917 ldw r3,36(r18) + 100792c: 91400717 ldw r5,28(r18) + 1007930: e009883a mov r4,fp + 1007934: b80d883a mov r6,r23 + 1007938: 183ee83a callr r3 + 100793c: 1023883a mov r17,r2 + 1007940: 00bfe10e bge zero,r2,10078c8 <__sfvwrite_r+0x254> + 1007944: a469c83a sub r20,r20,r17 + 1007948: a0001826 beq r20,zero,10079ac <__sfvwrite_r+0x338> + 100794c: b0800217 ldw r2,8(r22) + 1007950: 1445c83a sub r2,r2,r17 + 1007954: b0800215 stw r2,8(r22) + 1007958: 103f7226 beq r2,zero,1007724 <__sfvwrite_r+0xb0> + 100795c: 9c67c83a sub r19,r19,r17 + 1007960: bc6f883a add r23,r23,r17 + 1007964: 983fe21e bne r19,zero,10078f0 <__sfvwrite_r+0x27c> + 1007968: adc00017 ldw r23,0(r21) + 100796c: acc00117 ldw r19,4(r21) + 1007970: ad400204 addi r21,r21,8 + 1007974: d8000015 stw zero,0(sp) + 1007978: 003fdc06 br 10078ec <__sfvwrite_r+0x278> + 100797c: b80b883a mov r5,r23 + 1007980: 880d883a mov r6,r17 + 1007984: 100806c0 call 100806c + 1007988: 90c00017 ldw r3,0(r18) + 100798c: e009883a mov r4,fp + 1007990: 900b883a mov r5,r18 + 1007994: 1c47883a add r3,r3,r17 + 1007998: 90c00015 stw r3,0(r18) + 100799c: 1006d440 call 1006d44 <_fflush_r> + 10079a0: 103fc91e bne r2,zero,10078c8 <__sfvwrite_r+0x254> + 10079a4: a469c83a sub r20,r20,r17 + 10079a8: a03fe81e bne r20,zero,100794c <__sfvwrite_r+0x2d8> + 10079ac: e009883a mov r4,fp + 10079b0: 900b883a mov r5,r18 + 10079b4: 1006d440 call 1006d44 <_fflush_r> + 10079b8: 103fc31e bne r2,zero,10078c8 <__sfvwrite_r+0x254> + 10079bc: d8000015 stw zero,0(sp) + 10079c0: 003fe206 br 100794c <__sfvwrite_r+0x2d8> + 10079c4: 91000017 ldw r4,0(r18) + 10079c8: 90800417 ldw r2,16(r18) + 10079cc: 1100022e bgeu r2,r4,10079d8 <__sfvwrite_r+0x364> + 10079d0: 8023883a mov r17,r16 + 10079d4: 85003136 bltu r16,r20,1007a9c <__sfvwrite_r+0x428> + 10079d8: 91c00517 ldw r7,20(r18) + 10079dc: a1c01836 bltu r20,r7,1007a40 <__sfvwrite_r+0x3cc> + 10079e0: 90c00917 ldw r3,36(r18) + 10079e4: 91400717 ldw r5,28(r18) + 10079e8: e009883a mov r4,fp + 10079ec: b80d883a mov r6,r23 + 10079f0: 183ee83a callr r3 + 10079f4: 1021883a mov r16,r2 + 10079f8: 00bfb30e bge zero,r2,10078c8 <__sfvwrite_r+0x254> + 10079fc: 1023883a mov r17,r2 + 1007a00: 1027883a mov r19,r2 + 1007a04: 003f9b06 br 1007874 <__sfvwrite_r+0x200> + 1007a08: b80b883a mov r5,r23 + 1007a0c: 800d883a mov r6,r16 + 1007a10: 100806c0 call 100806c + 1007a14: 90c00217 ldw r3,8(r18) + 1007a18: 90800017 ldw r2,0(r18) + 1007a1c: 8023883a mov r17,r16 + 1007a20: 1c07c83a sub r3,r3,r16 + 1007a24: 1405883a add r2,r2,r16 + 1007a28: 90c00215 stw r3,8(r18) + 1007a2c: 90800015 stw r2,0(r18) + 1007a30: 003fc406 br 1007944 <__sfvwrite_r+0x2d0> + 1007a34: a00d883a mov r6,r20 + 1007a38: a021883a mov r16,r20 + 1007a3c: 003f8106 br 1007844 <__sfvwrite_r+0x1d0> + 1007a40: b80b883a mov r5,r23 + 1007a44: a00d883a mov r6,r20 + 1007a48: 100806c0 call 100806c + 1007a4c: 90c00217 ldw r3,8(r18) + 1007a50: 90800017 ldw r2,0(r18) + 1007a54: a021883a mov r16,r20 + 1007a58: 1d07c83a sub r3,r3,r20 + 1007a5c: 1505883a add r2,r2,r20 + 1007a60: a023883a mov r17,r20 + 1007a64: a027883a mov r19,r20 + 1007a68: 90c00215 stw r3,8(r18) + 1007a6c: 90800015 stw r2,0(r18) + 1007a70: 003f8006 br 1007874 <__sfvwrite_r+0x200> + 1007a74: b809883a mov r4,r23 + 1007a78: 01400284 movi r5,10 + 1007a7c: 980d883a mov r6,r19 + 1007a80: 1007ee80 call 1007ee8 + 1007a84: 10001726 beq r2,zero,1007ae4 <__sfvwrite_r+0x470> + 1007a88: 15c5c83a sub r2,r2,r23 + 1007a8c: 15000044 addi r20,r2,1 + 1007a90: 00800044 movi r2,1 + 1007a94: d8800015 stw r2,0(sp) + 1007a98: 003f9806 br 10078fc <__sfvwrite_r+0x288> + 1007a9c: b80b883a mov r5,r23 + 1007aa0: 800d883a mov r6,r16 + 1007aa4: 100806c0 call 100806c + 1007aa8: 90c00017 ldw r3,0(r18) + 1007aac: e009883a mov r4,fp + 1007ab0: 900b883a mov r5,r18 + 1007ab4: 1c07883a add r3,r3,r16 + 1007ab8: 90c00015 stw r3,0(r18) + 1007abc: 8027883a mov r19,r16 + 1007ac0: 1006d440 call 1006d44 <_fflush_r> + 1007ac4: 103f6b26 beq r2,zero,1007874 <__sfvwrite_r+0x200> + 1007ac8: 003f7f06 br 10078c8 <__sfvwrite_r+0x254> + 1007acc: 400b883a mov r5,r8 + 1007ad0: e009883a mov r4,fp + 1007ad4: 10091400 call 1009140 <_realloc_r> + 1007ad8: 103f7626 beq r2,zero,10078b4 <__sfvwrite_r+0x240> + 1007adc: 1023883a mov r17,r2 + 1007ae0: 003f5006 br 1007824 <__sfvwrite_r+0x1b0> + 1007ae4: 00c00044 movi r3,1 + 1007ae8: 9d000044 addi r20,r19,1 + 1007aec: d8c00015 stw r3,0(sp) + 1007af0: 003f8206 br 10078fc <__sfvwrite_r+0x288> + 1007af4: 9080030b ldhu r2,12(r18) + 1007af8: 00c00244 movi r3,9 + 1007afc: 013fffc4 movi r4,-1 + 1007b00: 10801014 ori r2,r2,64 + 1007b04: 9080030d sth r2,12(r18) + 1007b08: e0c00015 stw r3,0(fp) + 1007b0c: 003f0606 br 1007728 <__sfvwrite_r+0xb4> + +01007b10 <_fwalk_reent>: + 1007b10: defff704 addi sp,sp,-36 + 1007b14: dcc00315 stw r19,12(sp) + 1007b18: 24c0b804 addi r19,r4,736 + 1007b1c: dd800615 stw r22,24(sp) + 1007b20: dd400515 stw r21,20(sp) + 1007b24: dfc00815 stw ra,32(sp) + 1007b28: ddc00715 stw r23,28(sp) + 1007b2c: dd000415 stw r20,16(sp) + 1007b30: dc800215 stw r18,8(sp) + 1007b34: dc400115 stw r17,4(sp) + 1007b38: dc000015 stw r16,0(sp) + 1007b3c: 202b883a mov r21,r4 + 1007b40: 282d883a mov r22,r5 + 1007b44: 1006fcc0 call 1006fcc <__sfp_lock_acquire> + 1007b48: 98002126 beq r19,zero,1007bd0 <_fwalk_reent+0xc0> + 1007b4c: 002f883a mov r23,zero + 1007b50: 9c800117 ldw r18,4(r19) + 1007b54: 9c000217 ldw r16,8(r19) + 1007b58: 90bfffc4 addi r2,r18,-1 + 1007b5c: 10000d16 blt r2,zero,1007b94 <_fwalk_reent+0x84> + 1007b60: 0023883a mov r17,zero + 1007b64: 053fffc4 movi r20,-1 + 1007b68: 8080030f ldh r2,12(r16) + 1007b6c: 8c400044 addi r17,r17,1 + 1007b70: 10000626 beq r2,zero,1007b8c <_fwalk_reent+0x7c> + 1007b74: 8080038f ldh r2,14(r16) + 1007b78: 800b883a mov r5,r16 + 1007b7c: a809883a mov r4,r21 + 1007b80: 15000226 beq r2,r20,1007b8c <_fwalk_reent+0x7c> + 1007b84: b03ee83a callr r22 + 1007b88: b8aeb03a or r23,r23,r2 + 1007b8c: 84001704 addi r16,r16,92 + 1007b90: 947ff51e bne r18,r17,1007b68 <_fwalk_reent+0x58> + 1007b94: 9cc00017 ldw r19,0(r19) + 1007b98: 983fed1e bne r19,zero,1007b50 <_fwalk_reent+0x40> + 1007b9c: 1006fd00 call 1006fd0 <__sfp_lock_release> + 1007ba0: b805883a mov r2,r23 + 1007ba4: dfc00817 ldw ra,32(sp) + 1007ba8: ddc00717 ldw r23,28(sp) + 1007bac: dd800617 ldw r22,24(sp) + 1007bb0: dd400517 ldw r21,20(sp) + 1007bb4: dd000417 ldw r20,16(sp) + 1007bb8: dcc00317 ldw r19,12(sp) + 1007bbc: dc800217 ldw r18,8(sp) + 1007bc0: dc400117 ldw r17,4(sp) + 1007bc4: dc000017 ldw r16,0(sp) + 1007bc8: dec00904 addi sp,sp,36 + 1007bcc: f800283a ret + 1007bd0: 002f883a mov r23,zero + 1007bd4: 003ff106 br 1007b9c <_fwalk_reent+0x8c> + +01007bd8 <_fwalk>: + 1007bd8: defff804 addi sp,sp,-32 + 1007bdc: dcc00315 stw r19,12(sp) + 1007be0: 24c0b804 addi r19,r4,736 + 1007be4: dd400515 stw r21,20(sp) + 1007be8: dfc00715 stw ra,28(sp) + 1007bec: dd800615 stw r22,24(sp) + 1007bf0: dd000415 stw r20,16(sp) + 1007bf4: dc800215 stw r18,8(sp) + 1007bf8: dc400115 stw r17,4(sp) + 1007bfc: dc000015 stw r16,0(sp) + 1007c00: 282b883a mov r21,r5 + 1007c04: 1006fcc0 call 1006fcc <__sfp_lock_acquire> + 1007c08: 98001f26 beq r19,zero,1007c88 <_fwalk+0xb0> + 1007c0c: 002d883a mov r22,zero + 1007c10: 9c800117 ldw r18,4(r19) + 1007c14: 9c000217 ldw r16,8(r19) + 1007c18: 90bfffc4 addi r2,r18,-1 + 1007c1c: 10000c16 blt r2,zero,1007c50 <_fwalk+0x78> + 1007c20: 0023883a mov r17,zero + 1007c24: 053fffc4 movi r20,-1 + 1007c28: 8080030f ldh r2,12(r16) + 1007c2c: 8c400044 addi r17,r17,1 + 1007c30: 10000526 beq r2,zero,1007c48 <_fwalk+0x70> + 1007c34: 8080038f ldh r2,14(r16) + 1007c38: 8009883a mov r4,r16 + 1007c3c: 15000226 beq r2,r20,1007c48 <_fwalk+0x70> + 1007c40: a83ee83a callr r21 + 1007c44: b0acb03a or r22,r22,r2 + 1007c48: 84001704 addi r16,r16,92 + 1007c4c: 947ff61e bne r18,r17,1007c28 <_fwalk+0x50> + 1007c50: 9cc00017 ldw r19,0(r19) + 1007c54: 983fee1e bne r19,zero,1007c10 <_fwalk+0x38> + 1007c58: 1006fd00 call 1006fd0 <__sfp_lock_release> + 1007c5c: b005883a mov r2,r22 + 1007c60: dfc00717 ldw ra,28(sp) + 1007c64: dd800617 ldw r22,24(sp) + 1007c68: dd400517 ldw r21,20(sp) + 1007c6c: dd000417 ldw r20,16(sp) + 1007c70: dcc00317 ldw r19,12(sp) + 1007c74: dc800217 ldw r18,8(sp) + 1007c78: dc400117 ldw r17,4(sp) + 1007c7c: dc000017 ldw r16,0(sp) + 1007c80: dec00804 addi sp,sp,32 + 1007c84: f800283a ret + 1007c88: 002d883a mov r22,zero + 1007c8c: 003ff206 br 1007c58 <_fwalk+0x80> + +01007c90 <__locale_charset>: + 1007c90: d0a00e17 ldw r2,-32712(gp) + 1007c94: f800283a ret + +01007c98 <_localeconv_r>: + 1007c98: 008040b4 movhi r2,258 + 1007c9c: 10a39404 addi r2,r2,-29104 + 1007ca0: f800283a ret + +01007ca4 : + 1007ca4: 008040b4 movhi r2,258 + 1007ca8: 10ab9804 addi r2,r2,-20896 + 1007cac: 11000017 ldw r4,0(r2) + 1007cb0: 1007c981 jmpi 1007c98 <_localeconv_r> + +01007cb4 <_setlocale_r>: + 1007cb4: defffc04 addi sp,sp,-16 + 1007cb8: 00c040b4 movhi r3,258 + 1007cbc: 18e38f04 addi r3,r3,-29124 + 1007cc0: dc800215 stw r18,8(sp) + 1007cc4: dc400115 stw r17,4(sp) + 1007cc8: dc000015 stw r16,0(sp) + 1007ccc: 2023883a mov r17,r4 + 1007cd0: 2825883a mov r18,r5 + 1007cd4: dfc00315 stw ra,12(sp) + 1007cd8: 3021883a mov r16,r6 + 1007cdc: 3009883a mov r4,r6 + 1007ce0: 180b883a mov r5,r3 + 1007ce4: 30000926 beq r6,zero,1007d0c <_setlocale_r+0x58> + 1007ce8: 10098f00 call 10098f0 + 1007cec: 8009883a mov r4,r16 + 1007cf0: 014040b4 movhi r5,258 + 1007cf4: 29637a04 addi r5,r5,-29208 + 1007cf8: 10000b1e bne r2,zero,1007d28 <_setlocale_r+0x74> + 1007cfc: 8c000d15 stw r16,52(r17) + 1007d00: 8c800c15 stw r18,48(r17) + 1007d04: 00c040b4 movhi r3,258 + 1007d08: 18e38f04 addi r3,r3,-29124 + 1007d0c: 1805883a mov r2,r3 + 1007d10: dfc00317 ldw ra,12(sp) + 1007d14: dc800217 ldw r18,8(sp) + 1007d18: dc400117 ldw r17,4(sp) + 1007d1c: dc000017 ldw r16,0(sp) + 1007d20: dec00404 addi sp,sp,16 + 1007d24: f800283a ret + 1007d28: 10098f00 call 10098f0 + 1007d2c: 0007883a mov r3,zero + 1007d30: 103ff226 beq r2,zero,1007cfc <_setlocale_r+0x48> + 1007d34: 003ff506 br 1007d0c <_setlocale_r+0x58> + +01007d38 : + 1007d38: 018040b4 movhi r6,258 + 1007d3c: 31ab9804 addi r6,r6,-20896 + 1007d40: 2007883a mov r3,r4 + 1007d44: 31000017 ldw r4,0(r6) + 1007d48: 280d883a mov r6,r5 + 1007d4c: 180b883a mov r5,r3 + 1007d50: 1007cb41 jmpi 1007cb4 <_setlocale_r> + +01007d54 <__smakebuf_r>: + 1007d54: 2880030b ldhu r2,12(r5) + 1007d58: deffed04 addi sp,sp,-76 + 1007d5c: dc401015 stw r17,64(sp) + 1007d60: 1080008c andi r2,r2,2 + 1007d64: dc000f15 stw r16,60(sp) + 1007d68: dfc01215 stw ra,72(sp) + 1007d6c: dc801115 stw r18,68(sp) + 1007d70: 2821883a mov r16,r5 + 1007d74: 2023883a mov r17,r4 + 1007d78: 10000b26 beq r2,zero,1007da8 <__smakebuf_r+0x54> + 1007d7c: 28c010c4 addi r3,r5,67 + 1007d80: 00800044 movi r2,1 + 1007d84: 28800515 stw r2,20(r5) + 1007d88: 28c00415 stw r3,16(r5) + 1007d8c: 28c00015 stw r3,0(r5) + 1007d90: dfc01217 ldw ra,72(sp) + 1007d94: dc801117 ldw r18,68(sp) + 1007d98: dc401017 ldw r17,64(sp) + 1007d9c: dc000f17 ldw r16,60(sp) + 1007da0: dec01304 addi sp,sp,76 + 1007da4: f800283a ret + 1007da8: 2940038f ldh r5,14(r5) + 1007dac: 28002116 blt r5,zero,1007e34 <__smakebuf_r+0xe0> + 1007db0: d80d883a mov r6,sp + 1007db4: 1009c6c0 call 1009c6c <_fstat_r> + 1007db8: 10001e16 blt r2,zero,1007e34 <__smakebuf_r+0xe0> + 1007dbc: d8800117 ldw r2,4(sp) + 1007dc0: 00e00014 movui r3,32768 + 1007dc4: 113c000c andi r4,r2,61440 + 1007dc8: 20c03126 beq r4,r3,1007e90 <__smakebuf_r+0x13c> + 1007dcc: 8080030b ldhu r2,12(r16) + 1007dd0: 00c80004 movi r3,8192 + 1007dd4: 10820014 ori r2,r2,2048 + 1007dd8: 8080030d sth r2,12(r16) + 1007ddc: 20c01e26 beq r4,r3,1007e58 <__smakebuf_r+0x104> + 1007de0: 04810004 movi r18,1024 + 1007de4: 8809883a mov r4,r17 + 1007de8: 900b883a mov r5,r18 + 1007dec: 10027dc0 call 10027dc <_malloc_r> + 1007df0: 1009883a mov r4,r2 + 1007df4: 10003126 beq r2,zero,1007ebc <__smakebuf_r+0x168> + 1007df8: 80c0030b ldhu r3,12(r16) + 1007dfc: 00804034 movhi r2,256 + 1007e00: 109c3004 addi r2,r2,28864 + 1007e04: 88800f15 stw r2,60(r17) + 1007e08: 18c02014 ori r3,r3,128 + 1007e0c: 84800515 stw r18,20(r16) + 1007e10: 80c0030d sth r3,12(r16) + 1007e14: 81000415 stw r4,16(r16) + 1007e18: 81000015 stw r4,0(r16) + 1007e1c: dfc01217 ldw ra,72(sp) + 1007e20: dc801117 ldw r18,68(sp) + 1007e24: dc401017 ldw r17,64(sp) + 1007e28: dc000f17 ldw r16,60(sp) + 1007e2c: dec01304 addi sp,sp,76 + 1007e30: f800283a ret + 1007e34: 80c0030b ldhu r3,12(r16) + 1007e38: 1880200c andi r2,r3,128 + 1007e3c: 10000426 beq r2,zero,1007e50 <__smakebuf_r+0xfc> + 1007e40: 04801004 movi r18,64 + 1007e44: 18820014 ori r2,r3,2048 + 1007e48: 8080030d sth r2,12(r16) + 1007e4c: 003fe506 br 1007de4 <__smakebuf_r+0x90> + 1007e50: 04810004 movi r18,1024 + 1007e54: 003ffb06 br 1007e44 <__smakebuf_r+0xf0> + 1007e58: 8140038f ldh r5,14(r16) + 1007e5c: 8809883a mov r4,r17 + 1007e60: 1009ce00 call 1009ce0 <_isatty_r> + 1007e64: 103fde26 beq r2,zero,1007de0 <__smakebuf_r+0x8c> + 1007e68: 8080030b ldhu r2,12(r16) + 1007e6c: 80c010c4 addi r3,r16,67 + 1007e70: 04810004 movi r18,1024 + 1007e74: 10800054 ori r2,r2,1 + 1007e78: 8080030d sth r2,12(r16) + 1007e7c: 00800044 movi r2,1 + 1007e80: 80c00415 stw r3,16(r16) + 1007e84: 80800515 stw r2,20(r16) + 1007e88: 80c00015 stw r3,0(r16) + 1007e8c: 003fd506 br 1007de4 <__smakebuf_r+0x90> + 1007e90: 80c00a17 ldw r3,40(r16) + 1007e94: 00804074 movhi r2,257 + 1007e98: 10a5eb04 addi r2,r2,-26708 + 1007e9c: 18bfcb1e bne r3,r2,1007dcc <__smakebuf_r+0x78> + 1007ea0: 8080030b ldhu r2,12(r16) + 1007ea4: 00c10004 movi r3,1024 + 1007ea8: 1825883a mov r18,r3 + 1007eac: 10c4b03a or r2,r2,r3 + 1007eb0: 8080030d sth r2,12(r16) + 1007eb4: 80c01315 stw r3,76(r16) + 1007eb8: 003fca06 br 1007de4 <__smakebuf_r+0x90> + 1007ebc: 8100030b ldhu r4,12(r16) + 1007ec0: 2080800c andi r2,r4,512 + 1007ec4: 103fb21e bne r2,zero,1007d90 <__smakebuf_r+0x3c> + 1007ec8: 80c010c4 addi r3,r16,67 + 1007ecc: 21000094 ori r4,r4,2 + 1007ed0: 00800044 movi r2,1 + 1007ed4: 80800515 stw r2,20(r16) + 1007ed8: 8100030d sth r4,12(r16) + 1007edc: 80c00415 stw r3,16(r16) + 1007ee0: 80c00015 stw r3,0(r16) + 1007ee4: 003faa06 br 1007d90 <__smakebuf_r+0x3c> + +01007ee8 : + 1007ee8: 008000c4 movi r2,3 + 1007eec: 29403fcc andi r5,r5,255 + 1007ef0: 2007883a mov r3,r4 + 1007ef4: 1180022e bgeu r2,r6,1007f00 + 1007ef8: 2084703a and r2,r4,r2 + 1007efc: 10000b26 beq r2,zero,1007f2c + 1007f00: 313fffc4 addi r4,r6,-1 + 1007f04: 3000051e bne r6,zero,1007f1c + 1007f08: 00002c06 br 1007fbc + 1007f0c: 213fffc4 addi r4,r4,-1 + 1007f10: 00bfffc4 movi r2,-1 + 1007f14: 18c00044 addi r3,r3,1 + 1007f18: 20802826 beq r4,r2,1007fbc + 1007f1c: 18800003 ldbu r2,0(r3) + 1007f20: 28bffa1e bne r5,r2,1007f0c + 1007f24: 1805883a mov r2,r3 + 1007f28: f800283a ret + 1007f2c: 0011883a mov r8,zero + 1007f30: 0007883a mov r3,zero + 1007f34: 01c00104 movi r7,4 + 1007f38: 4004923a slli r2,r8,8 + 1007f3c: 18c00044 addi r3,r3,1 + 1007f40: 1151883a add r8,r2,r5 + 1007f44: 19fffc1e bne r3,r7,1007f38 + 1007f48: 02bfbff4 movhi r10,65279 + 1007f4c: 52bfbfc4 addi r10,r10,-257 + 1007f50: 02602074 movhi r9,32897 + 1007f54: 4a602004 addi r9,r9,-32640 + 1007f58: 02c000c4 movi r11,3 + 1007f5c: 20800017 ldw r2,0(r4) + 1007f60: 31bfff04 addi r6,r6,-4 + 1007f64: 200f883a mov r7,r4 + 1007f68: 1204f03a xor r2,r2,r8 + 1007f6c: 1287883a add r3,r2,r10 + 1007f70: 1a46703a and r3,r3,r9 + 1007f74: 0084303a nor r2,zero,r2 + 1007f78: 10c4703a and r2,r2,r3 + 1007f7c: 10000b26 beq r2,zero,1007fac + 1007f80: 20800003 ldbu r2,0(r4) + 1007f84: 28800f26 beq r5,r2,1007fc4 + 1007f88: 20800043 ldbu r2,1(r4) + 1007f8c: 21c00044 addi r7,r4,1 + 1007f90: 28800c26 beq r5,r2,1007fc4 + 1007f94: 20800083 ldbu r2,2(r4) + 1007f98: 21c00084 addi r7,r4,2 + 1007f9c: 28800926 beq r5,r2,1007fc4 + 1007fa0: 208000c3 ldbu r2,3(r4) + 1007fa4: 21c000c4 addi r7,r4,3 + 1007fa8: 28800626 beq r5,r2,1007fc4 + 1007fac: 21000104 addi r4,r4,4 + 1007fb0: 59bfea36 bltu r11,r6,1007f5c + 1007fb4: 2007883a mov r3,r4 + 1007fb8: 003fd106 br 1007f00 + 1007fbc: 0005883a mov r2,zero + 1007fc0: f800283a ret + 1007fc4: 3805883a mov r2,r7 + 1007fc8: f800283a ret + +01007fcc : + 1007fcc: 01c003c4 movi r7,15 + 1007fd0: 2007883a mov r3,r4 + 1007fd4: 3980032e bgeu r7,r6,1007fe4 + 1007fd8: 2904b03a or r2,r5,r4 + 1007fdc: 108000cc andi r2,r2,3 + 1007fe0: 10000926 beq r2,zero,1008008 + 1007fe4: 30000626 beq r6,zero,1008000 + 1007fe8: 30cd883a add r6,r6,r3 + 1007fec: 28800003 ldbu r2,0(r5) + 1007ff0: 29400044 addi r5,r5,1 + 1007ff4: 18800005 stb r2,0(r3) + 1007ff8: 18c00044 addi r3,r3,1 + 1007ffc: 30fffb1e bne r6,r3,1007fec + 1008000: 2005883a mov r2,r4 + 1008004: f800283a ret + 1008008: 3811883a mov r8,r7 + 100800c: 200f883a mov r7,r4 + 1008010: 28c00017 ldw r3,0(r5) + 1008014: 31bffc04 addi r6,r6,-16 + 1008018: 38c00015 stw r3,0(r7) + 100801c: 28800117 ldw r2,4(r5) + 1008020: 38800115 stw r2,4(r7) + 1008024: 28c00217 ldw r3,8(r5) + 1008028: 38c00215 stw r3,8(r7) + 100802c: 28800317 ldw r2,12(r5) + 1008030: 29400404 addi r5,r5,16 + 1008034: 38800315 stw r2,12(r7) + 1008038: 39c00404 addi r7,r7,16 + 100803c: 41bff436 bltu r8,r6,1008010 + 1008040: 008000c4 movi r2,3 + 1008044: 1180072e bgeu r2,r6,1008064 + 1008048: 1007883a mov r3,r2 + 100804c: 28800017 ldw r2,0(r5) + 1008050: 31bfff04 addi r6,r6,-4 + 1008054: 29400104 addi r5,r5,4 + 1008058: 38800015 stw r2,0(r7) + 100805c: 39c00104 addi r7,r7,4 + 1008060: 19bffa36 bltu r3,r6,100804c + 1008064: 3807883a mov r3,r7 + 1008068: 003fde06 br 1007fe4 + +0100806c : + 100806c: 2807883a mov r3,r5 + 1008070: 2011883a mov r8,r4 + 1008074: 29000c2e bgeu r5,r4,10080a8 + 1008078: 298f883a add r7,r5,r6 + 100807c: 21c00a2e bgeu r4,r7,10080a8 + 1008080: 30000726 beq r6,zero,10080a0 + 1008084: 2187883a add r3,r4,r6 + 1008088: 198dc83a sub r6,r3,r6 + 100808c: 39ffffc4 addi r7,r7,-1 + 1008090: 38800003 ldbu r2,0(r7) + 1008094: 18ffffc4 addi r3,r3,-1 + 1008098: 18800005 stb r2,0(r3) + 100809c: 19bffb1e bne r3,r6,100808c + 10080a0: 2005883a mov r2,r4 + 10080a4: f800283a ret + 10080a8: 01c003c4 movi r7,15 + 10080ac: 39800a36 bltu r7,r6,10080d8 + 10080b0: 303ffb26 beq r6,zero,10080a0 + 10080b4: 400f883a mov r7,r8 + 10080b8: 320d883a add r6,r6,r8 + 10080bc: 28800003 ldbu r2,0(r5) + 10080c0: 29400044 addi r5,r5,1 + 10080c4: 38800005 stb r2,0(r7) + 10080c8: 39c00044 addi r7,r7,1 + 10080cc: 39bffb1e bne r7,r6,10080bc + 10080d0: 2005883a mov r2,r4 + 10080d4: f800283a ret + 10080d8: 1904b03a or r2,r3,r4 + 10080dc: 108000cc andi r2,r2,3 + 10080e0: 103ff31e bne r2,zero,10080b0 + 10080e4: 3811883a mov r8,r7 + 10080e8: 180b883a mov r5,r3 + 10080ec: 200f883a mov r7,r4 + 10080f0: 28c00017 ldw r3,0(r5) + 10080f4: 31bffc04 addi r6,r6,-16 + 10080f8: 38c00015 stw r3,0(r7) + 10080fc: 28800117 ldw r2,4(r5) + 1008100: 38800115 stw r2,4(r7) + 1008104: 28c00217 ldw r3,8(r5) + 1008108: 38c00215 stw r3,8(r7) + 100810c: 28800317 ldw r2,12(r5) + 1008110: 29400404 addi r5,r5,16 + 1008114: 38800315 stw r2,12(r7) + 1008118: 39c00404 addi r7,r7,16 + 100811c: 41bff436 bltu r8,r6,10080f0 + 1008120: 008000c4 movi r2,3 + 1008124: 1180072e bgeu r2,r6,1008144 + 1008128: 1007883a mov r3,r2 + 100812c: 28800017 ldw r2,0(r5) + 1008130: 31bfff04 addi r6,r6,-4 + 1008134: 29400104 addi r5,r5,4 + 1008138: 38800015 stw r2,0(r7) + 100813c: 39c00104 addi r7,r7,4 + 1008140: 19bffa36 bltu r3,r6,100812c + 1008144: 3811883a mov r8,r7 + 1008148: 003fd906 br 10080b0 + +0100814c <_Bfree>: + 100814c: 28000826 beq r5,zero,1008170 <_Bfree+0x24> + 1008150: 28800117 ldw r2,4(r5) + 1008154: 21001317 ldw r4,76(r4) + 1008158: 1085883a add r2,r2,r2 + 100815c: 1085883a add r2,r2,r2 + 1008160: 1105883a add r2,r2,r4 + 1008164: 10c00017 ldw r3,0(r2) + 1008168: 28c00015 stw r3,0(r5) + 100816c: 11400015 stw r5,0(r2) + 1008170: f800283a ret + +01008174 <__hi0bits>: + 1008174: 20bfffec andhi r2,r4,65535 + 1008178: 10001426 beq r2,zero,10081cc <__hi0bits+0x58> + 100817c: 0007883a mov r3,zero + 1008180: 20bfc02c andhi r2,r4,65280 + 1008184: 1000021e bne r2,zero,1008190 <__hi0bits+0x1c> + 1008188: 2008923a slli r4,r4,8 + 100818c: 18c00204 addi r3,r3,8 + 1008190: 20bc002c andhi r2,r4,61440 + 1008194: 1000021e bne r2,zero,10081a0 <__hi0bits+0x2c> + 1008198: 2008913a slli r4,r4,4 + 100819c: 18c00104 addi r3,r3,4 + 10081a0: 20b0002c andhi r2,r4,49152 + 10081a4: 1000031e bne r2,zero,10081b4 <__hi0bits+0x40> + 10081a8: 2105883a add r2,r4,r4 + 10081ac: 18c00084 addi r3,r3,2 + 10081b0: 1089883a add r4,r2,r2 + 10081b4: 20000316 blt r4,zero,10081c4 <__hi0bits+0x50> + 10081b8: 2090002c andhi r2,r4,16384 + 10081bc: 10000626 beq r2,zero,10081d8 <__hi0bits+0x64> + 10081c0: 18c00044 addi r3,r3,1 + 10081c4: 1805883a mov r2,r3 + 10081c8: f800283a ret + 10081cc: 2008943a slli r4,r4,16 + 10081d0: 00c00404 movi r3,16 + 10081d4: 003fea06 br 1008180 <__hi0bits+0xc> + 10081d8: 00c00804 movi r3,32 + 10081dc: 1805883a mov r2,r3 + 10081e0: f800283a ret + +010081e4 <__lo0bits>: + 10081e4: 20c00017 ldw r3,0(r4) + 10081e8: 188001cc andi r2,r3,7 + 10081ec: 10000a26 beq r2,zero,1008218 <__lo0bits+0x34> + 10081f0: 1880004c andi r2,r3,1 + 10081f4: 1005003a cmpeq r2,r2,zero + 10081f8: 10002126 beq r2,zero,1008280 <__lo0bits+0x9c> + 10081fc: 1880008c andi r2,r3,2 + 1008200: 1000251e bne r2,zero,1008298 <__lo0bits+0xb4> + 1008204: 1804d0ba srli r2,r3,2 + 1008208: 01400084 movi r5,2 + 100820c: 20800015 stw r2,0(r4) + 1008210: 2805883a mov r2,r5 + 1008214: f800283a ret + 1008218: 18bfffcc andi r2,r3,65535 + 100821c: 10001526 beq r2,zero,1008274 <__lo0bits+0x90> + 1008220: 000b883a mov r5,zero + 1008224: 18803fcc andi r2,r3,255 + 1008228: 1000021e bne r2,zero,1008234 <__lo0bits+0x50> + 100822c: 1806d23a srli r3,r3,8 + 1008230: 29400204 addi r5,r5,8 + 1008234: 188003cc andi r2,r3,15 + 1008238: 1000021e bne r2,zero,1008244 <__lo0bits+0x60> + 100823c: 1806d13a srli r3,r3,4 + 1008240: 29400104 addi r5,r5,4 + 1008244: 188000cc andi r2,r3,3 + 1008248: 1000021e bne r2,zero,1008254 <__lo0bits+0x70> + 100824c: 1806d0ba srli r3,r3,2 + 1008250: 29400084 addi r5,r5,2 + 1008254: 1880004c andi r2,r3,1 + 1008258: 1000031e bne r2,zero,1008268 <__lo0bits+0x84> + 100825c: 1806d07a srli r3,r3,1 + 1008260: 18000a26 beq r3,zero,100828c <__lo0bits+0xa8> + 1008264: 29400044 addi r5,r5,1 + 1008268: 2805883a mov r2,r5 + 100826c: 20c00015 stw r3,0(r4) + 1008270: f800283a ret + 1008274: 1806d43a srli r3,r3,16 + 1008278: 01400404 movi r5,16 + 100827c: 003fe906 br 1008224 <__lo0bits+0x40> + 1008280: 000b883a mov r5,zero + 1008284: 2805883a mov r2,r5 + 1008288: f800283a ret + 100828c: 01400804 movi r5,32 + 1008290: 2805883a mov r2,r5 + 1008294: f800283a ret + 1008298: 1804d07a srli r2,r3,1 + 100829c: 01400044 movi r5,1 + 10082a0: 20800015 stw r2,0(r4) + 10082a4: 003fda06 br 1008210 <__lo0bits+0x2c> + +010082a8 <__mcmp>: + 10082a8: 20800417 ldw r2,16(r4) + 10082ac: 28c00417 ldw r3,16(r5) + 10082b0: 10cfc83a sub r7,r2,r3 + 10082b4: 38000c1e bne r7,zero,10082e8 <__mcmp+0x40> + 10082b8: 18c5883a add r2,r3,r3 + 10082bc: 1085883a add r2,r2,r2 + 10082c0: 10c00504 addi r3,r2,20 + 10082c4: 21000504 addi r4,r4,20 + 10082c8: 28cb883a add r5,r5,r3 + 10082cc: 2085883a add r2,r4,r2 + 10082d0: 10bfff04 addi r2,r2,-4 + 10082d4: 297fff04 addi r5,r5,-4 + 10082d8: 11800017 ldw r6,0(r2) + 10082dc: 28c00017 ldw r3,0(r5) + 10082e0: 30c0031e bne r6,r3,10082f0 <__mcmp+0x48> + 10082e4: 20bffa36 bltu r4,r2,10082d0 <__mcmp+0x28> + 10082e8: 3805883a mov r2,r7 + 10082ec: f800283a ret + 10082f0: 30c00336 bltu r6,r3,1008300 <__mcmp+0x58> + 10082f4: 01c00044 movi r7,1 + 10082f8: 3805883a mov r2,r7 + 10082fc: f800283a ret + 1008300: 01ffffc4 movi r7,-1 + 1008304: 003ff806 br 10082e8 <__mcmp+0x40> + +01008308 <__ulp>: + 1008308: 295ffc2c andhi r5,r5,32752 + 100830c: 013f3034 movhi r4,64704 + 1008310: 290b883a add r5,r5,r4 + 1008314: 0145c83a sub r2,zero,r5 + 1008318: 1007d53a srai r3,r2,20 + 100831c: 000d883a mov r6,zero + 1008320: 0140040e bge zero,r5,1008334 <__ulp+0x2c> + 1008324: 280f883a mov r7,r5 + 1008328: 3807883a mov r3,r7 + 100832c: 3005883a mov r2,r6 + 1008330: f800283a ret + 1008334: 008004c4 movi r2,19 + 1008338: 193ffb04 addi r4,r3,-20 + 100833c: 10c00c0e bge r2,r3,1008370 <__ulp+0x68> + 1008340: 008007c4 movi r2,31 + 1008344: 1107c83a sub r3,r2,r4 + 1008348: 00800784 movi r2,30 + 100834c: 01400044 movi r5,1 + 1008350: 11000216 blt r2,r4,100835c <__ulp+0x54> + 1008354: 00800044 movi r2,1 + 1008358: 10ca983a sll r5,r2,r3 + 100835c: 000f883a mov r7,zero + 1008360: 280d883a mov r6,r5 + 1008364: 3807883a mov r3,r7 + 1008368: 3005883a mov r2,r6 + 100836c: f800283a ret + 1008370: 00800234 movhi r2,8 + 1008374: 10cfd83a sra r7,r2,r3 + 1008378: 000d883a mov r6,zero + 100837c: 3005883a mov r2,r6 + 1008380: 3807883a mov r3,r7 + 1008384: f800283a ret + +01008388 <__b2d>: + 1008388: 20800417 ldw r2,16(r4) + 100838c: defff904 addi sp,sp,-28 + 1008390: dd000415 stw r20,16(sp) + 1008394: 1085883a add r2,r2,r2 + 1008398: 25000504 addi r20,r4,20 + 100839c: 1085883a add r2,r2,r2 + 10083a0: dc000015 stw r16,0(sp) + 10083a4: a0a1883a add r16,r20,r2 + 10083a8: dd400515 stw r21,20(sp) + 10083ac: 857fff17 ldw r21,-4(r16) + 10083b0: dc400115 stw r17,4(sp) + 10083b4: dfc00615 stw ra,24(sp) + 10083b8: a809883a mov r4,r21 + 10083bc: 2823883a mov r17,r5 + 10083c0: dcc00315 stw r19,12(sp) + 10083c4: dc800215 stw r18,8(sp) + 10083c8: 10081740 call 1008174 <__hi0bits> + 10083cc: 100b883a mov r5,r2 + 10083d0: 00800804 movi r2,32 + 10083d4: 1145c83a sub r2,r2,r5 + 10083d8: 88800015 stw r2,0(r17) + 10083dc: 00800284 movi r2,10 + 10083e0: 80ffff04 addi r3,r16,-4 + 10083e4: 11401416 blt r2,r5,1008438 <__b2d+0xb0> + 10083e8: 008002c4 movi r2,11 + 10083ec: 1149c83a sub r4,r2,r5 + 10083f0: a0c02736 bltu r20,r3,1008490 <__b2d+0x108> + 10083f4: 000d883a mov r6,zero + 10083f8: 28800544 addi r2,r5,21 + 10083fc: a906d83a srl r3,r21,r4 + 1008400: a884983a sll r2,r21,r2 + 1008404: 1ccffc34 orhi r19,r3,16368 + 1008408: 11a4b03a or r18,r2,r6 + 100840c: 9005883a mov r2,r18 + 1008410: 9807883a mov r3,r19 + 1008414: dfc00617 ldw ra,24(sp) + 1008418: dd400517 ldw r21,20(sp) + 100841c: dd000417 ldw r20,16(sp) + 1008420: dcc00317 ldw r19,12(sp) + 1008424: dc800217 ldw r18,8(sp) + 1008428: dc400117 ldw r17,4(sp) + 100842c: dc000017 ldw r16,0(sp) + 1008430: dec00704 addi sp,sp,28 + 1008434: f800283a ret + 1008438: a0c00e36 bltu r20,r3,1008474 <__b2d+0xec> + 100843c: 293ffd44 addi r4,r5,-11 + 1008440: 000d883a mov r6,zero + 1008444: 20000f26 beq r4,zero,1008484 <__b2d+0xfc> + 1008448: 00800804 movi r2,32 + 100844c: 110bc83a sub r5,r2,r4 + 1008450: a0c01236 bltu r20,r3,100849c <__b2d+0x114> + 1008454: 000f883a mov r7,zero + 1008458: a904983a sll r2,r21,r4 + 100845c: 3146d83a srl r3,r6,r5 + 1008460: 3108983a sll r4,r6,r4 + 1008464: 108ffc34 orhi r2,r2,16368 + 1008468: 18a6b03a or r19,r3,r2 + 100846c: 3924b03a or r18,r7,r4 + 1008470: 003fe606 br 100840c <__b2d+0x84> + 1008474: 293ffd44 addi r4,r5,-11 + 1008478: 81bffe17 ldw r6,-8(r16) + 100847c: 80fffe04 addi r3,r16,-8 + 1008480: 203ff11e bne r4,zero,1008448 <__b2d+0xc0> + 1008484: accffc34 orhi r19,r21,16368 + 1008488: 3025883a mov r18,r6 + 100848c: 003fdf06 br 100840c <__b2d+0x84> + 1008490: 18bfff17 ldw r2,-4(r3) + 1008494: 110cd83a srl r6,r2,r4 + 1008498: 003fd706 br 10083f8 <__b2d+0x70> + 100849c: 18bfff17 ldw r2,-4(r3) + 10084a0: 114ed83a srl r7,r2,r5 + 10084a4: 003fec06 br 1008458 <__b2d+0xd0> + +010084a8 <__ratio>: + 10084a8: defff904 addi sp,sp,-28 + 10084ac: dc400215 stw r17,8(sp) + 10084b0: 2823883a mov r17,r5 + 10084b4: d80b883a mov r5,sp + 10084b8: dfc00615 stw ra,24(sp) + 10084bc: dd000515 stw r20,20(sp) + 10084c0: dcc00415 stw r19,16(sp) + 10084c4: dc800315 stw r18,12(sp) + 10084c8: 2025883a mov r18,r4 + 10084cc: 10083880 call 1008388 <__b2d> + 10084d0: 8809883a mov r4,r17 + 10084d4: d9400104 addi r5,sp,4 + 10084d8: 1027883a mov r19,r2 + 10084dc: 1829883a mov r20,r3 + 10084e0: 10083880 call 1008388 <__b2d> + 10084e4: 89000417 ldw r4,16(r17) + 10084e8: 91c00417 ldw r7,16(r18) + 10084ec: d9800117 ldw r6,4(sp) + 10084f0: 180b883a mov r5,r3 + 10084f4: 390fc83a sub r7,r7,r4 + 10084f8: 1009883a mov r4,r2 + 10084fc: d8800017 ldw r2,0(sp) + 1008500: 380e917a slli r7,r7,5 + 1008504: 2011883a mov r8,r4 + 1008508: 1185c83a sub r2,r2,r6 + 100850c: 11c5883a add r2,r2,r7 + 1008510: 1006953a slli r3,r2,20 + 1008514: 2813883a mov r9,r5 + 1008518: 00800d0e bge zero,r2,1008550 <__ratio+0xa8> + 100851c: 1d29883a add r20,r3,r20 + 1008520: a00b883a mov r5,r20 + 1008524: 480f883a mov r7,r9 + 1008528: 9809883a mov r4,r19 + 100852c: 400d883a mov r6,r8 + 1008530: 100b2940 call 100b294 <__divdf3> + 1008534: dfc00617 ldw ra,24(sp) + 1008538: dd000517 ldw r20,20(sp) + 100853c: dcc00417 ldw r19,16(sp) + 1008540: dc800317 ldw r18,12(sp) + 1008544: dc400217 ldw r17,8(sp) + 1008548: dec00704 addi sp,sp,28 + 100854c: f800283a ret + 1008550: 28d3c83a sub r9,r5,r3 + 1008554: 003ff206 br 1008520 <__ratio+0x78> + +01008558 <_mprec_log10>: + 1008558: defffe04 addi sp,sp,-8 + 100855c: 008005c4 movi r2,23 + 1008560: dc000015 stw r16,0(sp) + 1008564: dfc00115 stw ra,4(sp) + 1008568: 2021883a mov r16,r4 + 100856c: 11000c16 blt r2,r4,10085a0 <_mprec_log10+0x48> + 1008570: 200490fa slli r2,r4,3 + 1008574: 00c040b4 movhi r3,258 + 1008578: 18e3a004 addi r3,r3,-29056 + 100857c: 10c5883a add r2,r2,r3 + 1008580: 12400117 ldw r9,4(r2) + 1008584: 12000017 ldw r8,0(r2) + 1008588: 4807883a mov r3,r9 + 100858c: 4005883a mov r2,r8 + 1008590: dfc00117 ldw ra,4(sp) + 1008594: dc000017 ldw r16,0(sp) + 1008598: dec00204 addi sp,sp,8 + 100859c: f800283a ret + 10085a0: 0011883a mov r8,zero + 10085a4: 024ffc34 movhi r9,16368 + 10085a8: 0005883a mov r2,zero + 10085ac: 00d00934 movhi r3,16420 + 10085b0: 480b883a mov r5,r9 + 10085b4: 4009883a mov r4,r8 + 10085b8: 180f883a mov r7,r3 + 10085bc: 100d883a mov r6,r2 + 10085c0: 100aed00 call 100aed0 <__muldf3> + 10085c4: 843fffc4 addi r16,r16,-1 + 10085c8: 1011883a mov r8,r2 + 10085cc: 1813883a mov r9,r3 + 10085d0: 803ff51e bne r16,zero,10085a8 <_mprec_log10+0x50> + 10085d4: 4005883a mov r2,r8 + 10085d8: 4807883a mov r3,r9 + 10085dc: dfc00117 ldw ra,4(sp) + 10085e0: dc000017 ldw r16,0(sp) + 10085e4: dec00204 addi sp,sp,8 + 10085e8: f800283a ret + +010085ec <__copybits>: + 10085ec: 297fffc4 addi r5,r5,-1 + 10085f0: 30800417 ldw r2,16(r6) + 10085f4: 280bd17a srai r5,r5,5 + 10085f8: 31800504 addi r6,r6,20 + 10085fc: 1085883a add r2,r2,r2 + 1008600: 294b883a add r5,r5,r5 + 1008604: 294b883a add r5,r5,r5 + 1008608: 1085883a add r2,r2,r2 + 100860c: 290b883a add r5,r5,r4 + 1008610: 3087883a add r3,r6,r2 + 1008614: 29400104 addi r5,r5,4 + 1008618: 30c0052e bgeu r6,r3,1008630 <__copybits+0x44> + 100861c: 30800017 ldw r2,0(r6) + 1008620: 31800104 addi r6,r6,4 + 1008624: 20800015 stw r2,0(r4) + 1008628: 21000104 addi r4,r4,4 + 100862c: 30fffb36 bltu r6,r3,100861c <__copybits+0x30> + 1008630: 2140032e bgeu r4,r5,1008640 <__copybits+0x54> + 1008634: 20000015 stw zero,0(r4) + 1008638: 21000104 addi r4,r4,4 + 100863c: 217ffd36 bltu r4,r5,1008634 <__copybits+0x48> + 1008640: f800283a ret + +01008644 <__any_on>: + 1008644: 20800417 ldw r2,16(r4) + 1008648: 2807d17a srai r3,r5,5 + 100864c: 21000504 addi r4,r4,20 + 1008650: 10c00d0e bge r2,r3,1008688 <__any_on+0x44> + 1008654: 1085883a add r2,r2,r2 + 1008658: 1085883a add r2,r2,r2 + 100865c: 208d883a add r6,r4,r2 + 1008660: 2180182e bgeu r4,r6,10086c4 <__any_on+0x80> + 1008664: 30bfff17 ldw r2,-4(r6) + 1008668: 30ffff04 addi r3,r6,-4 + 100866c: 1000041e bne r2,zero,1008680 <__any_on+0x3c> + 1008670: 20c0142e bgeu r4,r3,10086c4 <__any_on+0x80> + 1008674: 18ffff04 addi r3,r3,-4 + 1008678: 18800017 ldw r2,0(r3) + 100867c: 103ffc26 beq r2,zero,1008670 <__any_on+0x2c> + 1008680: 00800044 movi r2,1 + 1008684: f800283a ret + 1008688: 18800a0e bge r3,r2,10086b4 <__any_on+0x70> + 100868c: 294007cc andi r5,r5,31 + 1008690: 28000826 beq r5,zero,10086b4 <__any_on+0x70> + 1008694: 18c5883a add r2,r3,r3 + 1008698: 1085883a add r2,r2,r2 + 100869c: 208d883a add r6,r4,r2 + 10086a0: 30c00017 ldw r3,0(r6) + 10086a4: 1944d83a srl r2,r3,r5 + 10086a8: 1144983a sll r2,r2,r5 + 10086ac: 18bff41e bne r3,r2,1008680 <__any_on+0x3c> + 10086b0: 003feb06 br 1008660 <__any_on+0x1c> + 10086b4: 18c5883a add r2,r3,r3 + 10086b8: 1085883a add r2,r2,r2 + 10086bc: 208d883a add r6,r4,r2 + 10086c0: 003fe706 br 1008660 <__any_on+0x1c> + 10086c4: 0005883a mov r2,zero + 10086c8: f800283a ret + +010086cc <_Balloc>: + 10086cc: 20c01317 ldw r3,76(r4) + 10086d0: defffb04 addi sp,sp,-20 + 10086d4: dcc00315 stw r19,12(sp) + 10086d8: dc800215 stw r18,8(sp) + 10086dc: dfc00415 stw ra,16(sp) + 10086e0: 2825883a mov r18,r5 + 10086e4: dc400115 stw r17,4(sp) + 10086e8: dc000015 stw r16,0(sp) + 10086ec: 2027883a mov r19,r4 + 10086f0: 01800404 movi r6,16 + 10086f4: 01400104 movi r5,4 + 10086f8: 18001726 beq r3,zero,1008758 <_Balloc+0x8c> + 10086fc: 01400044 movi r5,1 + 1008700: 9485883a add r2,r18,r18 + 1008704: 2ca2983a sll r17,r5,r18 + 1008708: 1085883a add r2,r2,r2 + 100870c: 10c7883a add r3,r2,r3 + 1008710: 1c000017 ldw r16,0(r3) + 1008714: 8c4d883a add r6,r17,r17 + 1008718: 318d883a add r6,r6,r6 + 100871c: 9809883a mov r4,r19 + 1008720: 31800504 addi r6,r6,20 + 1008724: 80001226 beq r16,zero,1008770 <_Balloc+0xa4> + 1008728: 80800017 ldw r2,0(r16) + 100872c: 18800015 stw r2,0(r3) + 1008730: 80000415 stw zero,16(r16) + 1008734: 80000315 stw zero,12(r16) + 1008738: 8005883a mov r2,r16 + 100873c: dfc00417 ldw ra,16(sp) + 1008740: dcc00317 ldw r19,12(sp) + 1008744: dc800217 ldw r18,8(sp) + 1008748: dc400117 ldw r17,4(sp) + 100874c: dc000017 ldw r16,0(sp) + 1008750: dec00504 addi sp,sp,20 + 1008754: f800283a ret + 1008758: 1009a240 call 1009a24 <_calloc_r> + 100875c: 1007883a mov r3,r2 + 1008760: 0021883a mov r16,zero + 1008764: 98801315 stw r2,76(r19) + 1008768: 103fe41e bne r2,zero,10086fc <_Balloc+0x30> + 100876c: 003ff206 br 1008738 <_Balloc+0x6c> + 1008770: 1009a240 call 1009a24 <_calloc_r> + 1008774: 103ff026 beq r2,zero,1008738 <_Balloc+0x6c> + 1008778: 1021883a mov r16,r2 + 100877c: 14800115 stw r18,4(r2) + 1008780: 14400215 stw r17,8(r2) + 1008784: 003fea06 br 1008730 <_Balloc+0x64> + +01008788 <__d2b>: + 1008788: defff504 addi sp,sp,-44 + 100878c: dcc00515 stw r19,20(sp) + 1008790: 04c00044 movi r19,1 + 1008794: dc000215 stw r16,8(sp) + 1008798: 2821883a mov r16,r5 + 100879c: 980b883a mov r5,r19 + 10087a0: ddc00915 stw r23,36(sp) + 10087a4: dd800815 stw r22,32(sp) + 10087a8: dd400715 stw r21,28(sp) + 10087ac: dd000615 stw r20,24(sp) + 10087b0: dc800415 stw r18,16(sp) + 10087b4: dc400315 stw r17,12(sp) + 10087b8: dfc00a15 stw ra,40(sp) + 10087bc: 3023883a mov r17,r6 + 10087c0: 382d883a mov r22,r7 + 10087c4: ddc00b17 ldw r23,44(sp) + 10087c8: 10086cc0 call 10086cc <_Balloc> + 10087cc: 1025883a mov r18,r2 + 10087d0: 00a00034 movhi r2,32768 + 10087d4: 10bfffc4 addi r2,r2,-1 + 10087d8: 8888703a and r4,r17,r2 + 10087dc: 202ad53a srli r21,r4,20 + 10087e0: 00800434 movhi r2,16 + 10087e4: 10bfffc4 addi r2,r2,-1 + 10087e8: 8886703a and r3,r17,r2 + 10087ec: a829003a cmpeq r20,r21,zero + 10087f0: 800b883a mov r5,r16 + 10087f4: d8c00115 stw r3,4(sp) + 10087f8: 94000504 addi r16,r18,20 + 10087fc: a000021e bne r20,zero,1008808 <__d2b+0x80> + 1008800: 18c00434 orhi r3,r3,16 + 1008804: d8c00115 stw r3,4(sp) + 1008808: 28002726 beq r5,zero,10088a8 <__d2b+0x120> + 100880c: d809883a mov r4,sp + 1008810: d9400015 stw r5,0(sp) + 1008814: 10081e40 call 10081e4 <__lo0bits> + 1008818: 100d883a mov r6,r2 + 100881c: 10003526 beq r2,zero,10088f4 <__d2b+0x16c> + 1008820: d8c00117 ldw r3,4(sp) + 1008824: 00800804 movi r2,32 + 1008828: 1185c83a sub r2,r2,r6 + 100882c: d9000017 ldw r4,0(sp) + 1008830: 1886983a sll r3,r3,r2 + 1008834: 1906b03a or r3,r3,r4 + 1008838: 90c00515 stw r3,20(r18) + 100883c: d8c00117 ldw r3,4(sp) + 1008840: 1986d83a srl r3,r3,r6 + 1008844: d8c00115 stw r3,4(sp) + 1008848: 180b003a cmpeq r5,r3,zero + 100884c: 00800084 movi r2,2 + 1008850: 114bc83a sub r5,r2,r5 + 1008854: 80c00115 stw r3,4(r16) + 1008858: 91400415 stw r5,16(r18) + 100885c: a0001a1e bne r20,zero,10088c8 <__d2b+0x140> + 1008860: 3545883a add r2,r6,r21 + 1008864: 10bef344 addi r2,r2,-1075 + 1008868: 00c00d44 movi r3,53 + 100886c: b0800015 stw r2,0(r22) + 1008870: 1987c83a sub r3,r3,r6 + 1008874: b8c00015 stw r3,0(r23) + 1008878: 9005883a mov r2,r18 + 100887c: dfc00a17 ldw ra,40(sp) + 1008880: ddc00917 ldw r23,36(sp) + 1008884: dd800817 ldw r22,32(sp) + 1008888: dd400717 ldw r21,28(sp) + 100888c: dd000617 ldw r20,24(sp) + 1008890: dcc00517 ldw r19,20(sp) + 1008894: dc800417 ldw r18,16(sp) + 1008898: dc400317 ldw r17,12(sp) + 100889c: dc000217 ldw r16,8(sp) + 10088a0: dec00b04 addi sp,sp,44 + 10088a4: f800283a ret + 10088a8: d9000104 addi r4,sp,4 + 10088ac: 10081e40 call 10081e4 <__lo0bits> + 10088b0: 11800804 addi r6,r2,32 + 10088b4: d8800117 ldw r2,4(sp) + 10088b8: 94c00415 stw r19,16(r18) + 10088bc: 980b883a mov r5,r19 + 10088c0: 90800515 stw r2,20(r18) + 10088c4: a03fe626 beq r20,zero,1008860 <__d2b+0xd8> + 10088c8: 2945883a add r2,r5,r5 + 10088cc: 1085883a add r2,r2,r2 + 10088d0: 1405883a add r2,r2,r16 + 10088d4: 113fff17 ldw r4,-4(r2) + 10088d8: 30fef384 addi r3,r6,-1074 + 10088dc: 2820917a slli r16,r5,5 + 10088e0: b0c00015 stw r3,0(r22) + 10088e4: 10081740 call 1008174 <__hi0bits> + 10088e8: 80a1c83a sub r16,r16,r2 + 10088ec: bc000015 stw r16,0(r23) + 10088f0: 003fe106 br 1008878 <__d2b+0xf0> + 10088f4: d8800017 ldw r2,0(sp) + 10088f8: 90800515 stw r2,20(r18) + 10088fc: d8c00117 ldw r3,4(sp) + 1008900: 003fd106 br 1008848 <__d2b+0xc0> + +01008904 <__mdiff>: + 1008904: defffb04 addi sp,sp,-20 + 1008908: dc000015 stw r16,0(sp) + 100890c: 2821883a mov r16,r5 + 1008910: dc800215 stw r18,8(sp) + 1008914: 300b883a mov r5,r6 + 1008918: 2025883a mov r18,r4 + 100891c: 8009883a mov r4,r16 + 1008920: dc400115 stw r17,4(sp) + 1008924: dfc00415 stw ra,16(sp) + 1008928: dcc00315 stw r19,12(sp) + 100892c: 3023883a mov r17,r6 + 1008930: 10082a80 call 10082a8 <__mcmp> + 1008934: 10004226 beq r2,zero,1008a40 <__mdiff+0x13c> + 1008938: 10005016 blt r2,zero,1008a7c <__mdiff+0x178> + 100893c: 0027883a mov r19,zero + 1008940: 81400117 ldw r5,4(r16) + 1008944: 9009883a mov r4,r18 + 1008948: 10086cc0 call 10086cc <_Balloc> + 100894c: 1019883a mov r12,r2 + 1008950: 82800417 ldw r10,16(r16) + 1008954: 88800417 ldw r2,16(r17) + 1008958: 81800504 addi r6,r16,20 + 100895c: 5287883a add r3,r10,r10 + 1008960: 1085883a add r2,r2,r2 + 1008964: 18c7883a add r3,r3,r3 + 1008968: 1085883a add r2,r2,r2 + 100896c: 8a000504 addi r8,r17,20 + 1008970: 64c00315 stw r19,12(r12) + 1008974: 30db883a add r13,r6,r3 + 1008978: 4097883a add r11,r8,r2 + 100897c: 61c00504 addi r7,r12,20 + 1008980: 0013883a mov r9,zero + 1008984: 31000017 ldw r4,0(r6) + 1008988: 41400017 ldw r5,0(r8) + 100898c: 42000104 addi r8,r8,4 + 1008990: 20bfffcc andi r2,r4,65535 + 1008994: 28ffffcc andi r3,r5,65535 + 1008998: 10c5c83a sub r2,r2,r3 + 100899c: 1245883a add r2,r2,r9 + 10089a0: 2008d43a srli r4,r4,16 + 10089a4: 280ad43a srli r5,r5,16 + 10089a8: 1007d43a srai r3,r2,16 + 10089ac: 3880000d sth r2,0(r7) + 10089b0: 2149c83a sub r4,r4,r5 + 10089b4: 20c9883a add r4,r4,r3 + 10089b8: 3900008d sth r4,2(r7) + 10089bc: 31800104 addi r6,r6,4 + 10089c0: 39c00104 addi r7,r7,4 + 10089c4: 2013d43a srai r9,r4,16 + 10089c8: 42ffee36 bltu r8,r11,1008984 <__mdiff+0x80> + 10089cc: 33400c2e bgeu r6,r13,1008a00 <__mdiff+0xfc> + 10089d0: 30800017 ldw r2,0(r6) + 10089d4: 31800104 addi r6,r6,4 + 10089d8: 10ffffcc andi r3,r2,65535 + 10089dc: 1a47883a add r3,r3,r9 + 10089e0: 1004d43a srli r2,r2,16 + 10089e4: 1809d43a srai r4,r3,16 + 10089e8: 38c0000d sth r3,0(r7) + 10089ec: 1105883a add r2,r2,r4 + 10089f0: 3880008d sth r2,2(r7) + 10089f4: 1013d43a srai r9,r2,16 + 10089f8: 39c00104 addi r7,r7,4 + 10089fc: 337ff436 bltu r6,r13,10089d0 <__mdiff+0xcc> + 1008a00: 38bfff17 ldw r2,-4(r7) + 1008a04: 38ffff04 addi r3,r7,-4 + 1008a08: 1000041e bne r2,zero,1008a1c <__mdiff+0x118> + 1008a0c: 18ffff04 addi r3,r3,-4 + 1008a10: 18800017 ldw r2,0(r3) + 1008a14: 52bfffc4 addi r10,r10,-1 + 1008a18: 103ffc26 beq r2,zero,1008a0c <__mdiff+0x108> + 1008a1c: 6005883a mov r2,r12 + 1008a20: 62800415 stw r10,16(r12) + 1008a24: dfc00417 ldw ra,16(sp) + 1008a28: dcc00317 ldw r19,12(sp) + 1008a2c: dc800217 ldw r18,8(sp) + 1008a30: dc400117 ldw r17,4(sp) + 1008a34: dc000017 ldw r16,0(sp) + 1008a38: dec00504 addi sp,sp,20 + 1008a3c: f800283a ret + 1008a40: 9009883a mov r4,r18 + 1008a44: 000b883a mov r5,zero + 1008a48: 10086cc0 call 10086cc <_Balloc> + 1008a4c: 1019883a mov r12,r2 + 1008a50: 00800044 movi r2,1 + 1008a54: 60800415 stw r2,16(r12) + 1008a58: 6005883a mov r2,r12 + 1008a5c: 60000515 stw zero,20(r12) + 1008a60: dfc00417 ldw ra,16(sp) + 1008a64: dcc00317 ldw r19,12(sp) + 1008a68: dc800217 ldw r18,8(sp) + 1008a6c: dc400117 ldw r17,4(sp) + 1008a70: dc000017 ldw r16,0(sp) + 1008a74: dec00504 addi sp,sp,20 + 1008a78: f800283a ret + 1008a7c: 880d883a mov r6,r17 + 1008a80: 04c00044 movi r19,1 + 1008a84: 8023883a mov r17,r16 + 1008a88: 3021883a mov r16,r6 + 1008a8c: 003fac06 br 1008940 <__mdiff+0x3c> + +01008a90 <__lshift>: + 1008a90: defff904 addi sp,sp,-28 + 1008a94: 28800417 ldw r2,16(r5) + 1008a98: dc000015 stw r16,0(sp) + 1008a9c: 3021d17a srai r16,r6,5 + 1008aa0: 28c00217 ldw r3,8(r5) + 1008aa4: 10800044 addi r2,r2,1 + 1008aa8: dc400115 stw r17,4(sp) + 1008aac: 80a3883a add r17,r16,r2 + 1008ab0: dd400515 stw r21,20(sp) + 1008ab4: dd000415 stw r20,16(sp) + 1008ab8: dc800215 stw r18,8(sp) + 1008abc: dfc00615 stw ra,24(sp) + 1008ac0: 2825883a mov r18,r5 + 1008ac4: dcc00315 stw r19,12(sp) + 1008ac8: 3029883a mov r20,r6 + 1008acc: 202b883a mov r21,r4 + 1008ad0: 29400117 ldw r5,4(r5) + 1008ad4: 1c40030e bge r3,r17,1008ae4 <__lshift+0x54> + 1008ad8: 18c7883a add r3,r3,r3 + 1008adc: 29400044 addi r5,r5,1 + 1008ae0: 1c7ffd16 blt r3,r17,1008ad8 <__lshift+0x48> + 1008ae4: a809883a mov r4,r21 + 1008ae8: 10086cc0 call 10086cc <_Balloc> + 1008aec: 1027883a mov r19,r2 + 1008af0: 11400504 addi r5,r2,20 + 1008af4: 0400090e bge zero,r16,1008b1c <__lshift+0x8c> + 1008af8: 2805883a mov r2,r5 + 1008afc: 0007883a mov r3,zero + 1008b00: 18c00044 addi r3,r3,1 + 1008b04: 10000015 stw zero,0(r2) + 1008b08: 10800104 addi r2,r2,4 + 1008b0c: 80fffc1e bne r16,r3,1008b00 <__lshift+0x70> + 1008b10: 8405883a add r2,r16,r16 + 1008b14: 1085883a add r2,r2,r2 + 1008b18: 288b883a add r5,r5,r2 + 1008b1c: 90800417 ldw r2,16(r18) + 1008b20: 91000504 addi r4,r18,20 + 1008b24: a18007cc andi r6,r20,31 + 1008b28: 1085883a add r2,r2,r2 + 1008b2c: 1085883a add r2,r2,r2 + 1008b30: 208f883a add r7,r4,r2 + 1008b34: 30001e26 beq r6,zero,1008bb0 <__lshift+0x120> + 1008b38: 00800804 movi r2,32 + 1008b3c: 1191c83a sub r8,r2,r6 + 1008b40: 0007883a mov r3,zero + 1008b44: 20800017 ldw r2,0(r4) + 1008b48: 1184983a sll r2,r2,r6 + 1008b4c: 1884b03a or r2,r3,r2 + 1008b50: 28800015 stw r2,0(r5) + 1008b54: 20c00017 ldw r3,0(r4) + 1008b58: 21000104 addi r4,r4,4 + 1008b5c: 29400104 addi r5,r5,4 + 1008b60: 1a06d83a srl r3,r3,r8 + 1008b64: 21fff736 bltu r4,r7,1008b44 <__lshift+0xb4> + 1008b68: 28c00015 stw r3,0(r5) + 1008b6c: 18000126 beq r3,zero,1008b74 <__lshift+0xe4> + 1008b70: 8c400044 addi r17,r17,1 + 1008b74: 88bfffc4 addi r2,r17,-1 + 1008b78: 98800415 stw r2,16(r19) + 1008b7c: a809883a mov r4,r21 + 1008b80: 900b883a mov r5,r18 + 1008b84: 100814c0 call 100814c <_Bfree> + 1008b88: 9805883a mov r2,r19 + 1008b8c: dfc00617 ldw ra,24(sp) + 1008b90: dd400517 ldw r21,20(sp) + 1008b94: dd000417 ldw r20,16(sp) + 1008b98: dcc00317 ldw r19,12(sp) + 1008b9c: dc800217 ldw r18,8(sp) + 1008ba0: dc400117 ldw r17,4(sp) + 1008ba4: dc000017 ldw r16,0(sp) + 1008ba8: dec00704 addi sp,sp,28 + 1008bac: f800283a ret + 1008bb0: 20800017 ldw r2,0(r4) + 1008bb4: 21000104 addi r4,r4,4 + 1008bb8: 28800015 stw r2,0(r5) + 1008bbc: 29400104 addi r5,r5,4 + 1008bc0: 21ffec2e bgeu r4,r7,1008b74 <__lshift+0xe4> + 1008bc4: 20800017 ldw r2,0(r4) + 1008bc8: 21000104 addi r4,r4,4 + 1008bcc: 28800015 stw r2,0(r5) + 1008bd0: 29400104 addi r5,r5,4 + 1008bd4: 21fff636 bltu r4,r7,1008bb0 <__lshift+0x120> + 1008bd8: 003fe606 br 1008b74 <__lshift+0xe4> + +01008bdc <__multiply>: + 1008bdc: defff904 addi sp,sp,-28 + 1008be0: dcc00315 stw r19,12(sp) + 1008be4: dc800215 stw r18,8(sp) + 1008be8: 2cc00417 ldw r19,16(r5) + 1008bec: 34800417 ldw r18,16(r6) + 1008bf0: dd000415 stw r20,16(sp) + 1008bf4: dc400115 stw r17,4(sp) + 1008bf8: dfc00615 stw ra,24(sp) + 1008bfc: dd400515 stw r21,20(sp) + 1008c00: dc000015 stw r16,0(sp) + 1008c04: 2823883a mov r17,r5 + 1008c08: 3029883a mov r20,r6 + 1008c0c: 9c80040e bge r19,r18,1008c20 <__multiply+0x44> + 1008c10: 9027883a mov r19,r18 + 1008c14: 2c800417 ldw r18,16(r5) + 1008c18: 2829883a mov r20,r5 + 1008c1c: 3023883a mov r17,r6 + 1008c20: 88800217 ldw r2,8(r17) + 1008c24: 9ca1883a add r16,r19,r18 + 1008c28: 89400117 ldw r5,4(r17) + 1008c2c: 1400010e bge r2,r16,1008c34 <__multiply+0x58> + 1008c30: 29400044 addi r5,r5,1 + 1008c34: 10086cc0 call 10086cc <_Balloc> + 1008c38: 102b883a mov r21,r2 + 1008c3c: 8405883a add r2,r16,r16 + 1008c40: 1085883a add r2,r2,r2 + 1008c44: a9000504 addi r4,r21,20 + 1008c48: 209d883a add r14,r4,r2 + 1008c4c: 2380042e bgeu r4,r14,1008c60 <__multiply+0x84> + 1008c50: 2005883a mov r2,r4 + 1008c54: 10000015 stw zero,0(r2) + 1008c58: 10800104 addi r2,r2,4 + 1008c5c: 13bffd36 bltu r2,r14,1008c54 <__multiply+0x78> + 1008c60: 9485883a add r2,r18,r18 + 1008c64: 9cc7883a add r3,r19,r19 + 1008c68: a1800504 addi r6,r20,20 + 1008c6c: 1085883a add r2,r2,r2 + 1008c70: 8b400504 addi r13,r17,20 + 1008c74: 18c7883a add r3,r3,r3 + 1008c78: 309f883a add r15,r6,r2 + 1008c7c: 68d7883a add r11,r13,r3 + 1008c80: 33c03b2e bgeu r6,r15,1008d70 <__multiply+0x194> + 1008c84: 2019883a mov r12,r4 + 1008c88: 30800017 ldw r2,0(r6) + 1008c8c: 127fffcc andi r9,r2,65535 + 1008c90: 48001826 beq r9,zero,1008cf4 <__multiply+0x118> + 1008c94: 6811883a mov r8,r13 + 1008c98: 600f883a mov r7,r12 + 1008c9c: 0015883a mov r10,zero + 1008ca0: 40c00017 ldw r3,0(r8) + 1008ca4: 39400017 ldw r5,0(r7) + 1008ca8: 42000104 addi r8,r8,4 + 1008cac: 193fffcc andi r4,r3,65535 + 1008cb0: 4909383a mul r4,r9,r4 + 1008cb4: 1806d43a srli r3,r3,16 + 1008cb8: 28bfffcc andi r2,r5,65535 + 1008cbc: 5085883a add r2,r10,r2 + 1008cc0: 2089883a add r4,r4,r2 + 1008cc4: 48c7383a mul r3,r9,r3 + 1008cc8: 280ad43a srli r5,r5,16 + 1008ccc: 2004d43a srli r2,r4,16 + 1008cd0: 3900000d sth r4,0(r7) + 1008cd4: 1947883a add r3,r3,r5 + 1008cd8: 10c5883a add r2,r2,r3 + 1008cdc: 3880008d sth r2,2(r7) + 1008ce0: 1014d43a srli r10,r2,16 + 1008ce4: 39c00104 addi r7,r7,4 + 1008ce8: 42ffed36 bltu r8,r11,1008ca0 <__multiply+0xc4> + 1008cec: 3a800015 stw r10,0(r7) + 1008cf0: 30800017 ldw r2,0(r6) + 1008cf4: 1012d43a srli r9,r2,16 + 1008cf8: 48001926 beq r9,zero,1008d60 <__multiply+0x184> + 1008cfc: 60800017 ldw r2,0(r12) + 1008d00: 6811883a mov r8,r13 + 1008d04: 600f883a mov r7,r12 + 1008d08: 0015883a mov r10,zero + 1008d0c: 100b883a mov r5,r2 + 1008d10: 41000017 ldw r4,0(r8) + 1008d14: 2806d43a srli r3,r5,16 + 1008d18: 3880000d sth r2,0(r7) + 1008d1c: 20bfffcc andi r2,r4,65535 + 1008d20: 4885383a mul r2,r9,r2 + 1008d24: 50c7883a add r3,r10,r3 + 1008d28: 2008d43a srli r4,r4,16 + 1008d2c: 10c5883a add r2,r2,r3 + 1008d30: 3880008d sth r2,2(r7) + 1008d34: 39c00104 addi r7,r7,4 + 1008d38: 39400017 ldw r5,0(r7) + 1008d3c: 4909383a mul r4,r9,r4 + 1008d40: 1004d43a srli r2,r2,16 + 1008d44: 28ffffcc andi r3,r5,65535 + 1008d48: 20c9883a add r4,r4,r3 + 1008d4c: 1105883a add r2,r2,r4 + 1008d50: 42000104 addi r8,r8,4 + 1008d54: 1014d43a srli r10,r2,16 + 1008d58: 42ffed36 bltu r8,r11,1008d10 <__multiply+0x134> + 1008d5c: 38800015 stw r2,0(r7) + 1008d60: 31800104 addi r6,r6,4 + 1008d64: 33c0022e bgeu r6,r15,1008d70 <__multiply+0x194> + 1008d68: 63000104 addi r12,r12,4 + 1008d6c: 003fc606 br 1008c88 <__multiply+0xac> + 1008d70: 0400090e bge zero,r16,1008d98 <__multiply+0x1bc> + 1008d74: 70bfff17 ldw r2,-4(r14) + 1008d78: 70ffff04 addi r3,r14,-4 + 1008d7c: 10000326 beq r2,zero,1008d8c <__multiply+0x1b0> + 1008d80: 00000506 br 1008d98 <__multiply+0x1bc> + 1008d84: 18800017 ldw r2,0(r3) + 1008d88: 1000031e bne r2,zero,1008d98 <__multiply+0x1bc> + 1008d8c: 843fffc4 addi r16,r16,-1 + 1008d90: 18ffff04 addi r3,r3,-4 + 1008d94: 803ffb1e bne r16,zero,1008d84 <__multiply+0x1a8> + 1008d98: a805883a mov r2,r21 + 1008d9c: ac000415 stw r16,16(r21) + 1008da0: dfc00617 ldw ra,24(sp) + 1008da4: dd400517 ldw r21,20(sp) + 1008da8: dd000417 ldw r20,16(sp) + 1008dac: dcc00317 ldw r19,12(sp) + 1008db0: dc800217 ldw r18,8(sp) + 1008db4: dc400117 ldw r17,4(sp) + 1008db8: dc000017 ldw r16,0(sp) + 1008dbc: dec00704 addi sp,sp,28 + 1008dc0: f800283a ret + +01008dc4 <__i2b>: + 1008dc4: defffd04 addi sp,sp,-12 + 1008dc8: dc000015 stw r16,0(sp) + 1008dcc: 04000044 movi r16,1 + 1008dd0: dc800115 stw r18,4(sp) + 1008dd4: 2825883a mov r18,r5 + 1008dd8: 800b883a mov r5,r16 + 1008ddc: dfc00215 stw ra,8(sp) + 1008de0: 10086cc0 call 10086cc <_Balloc> + 1008de4: 14000415 stw r16,16(r2) + 1008de8: 14800515 stw r18,20(r2) + 1008dec: dfc00217 ldw ra,8(sp) + 1008df0: dc800117 ldw r18,4(sp) + 1008df4: dc000017 ldw r16,0(sp) + 1008df8: dec00304 addi sp,sp,12 + 1008dfc: f800283a ret + +01008e00 <__multadd>: + 1008e00: defffa04 addi sp,sp,-24 + 1008e04: dc800215 stw r18,8(sp) + 1008e08: 2c800417 ldw r18,16(r5) + 1008e0c: dd000415 stw r20,16(sp) + 1008e10: dcc00315 stw r19,12(sp) + 1008e14: dc000015 stw r16,0(sp) + 1008e18: dfc00515 stw ra,20(sp) + 1008e1c: 3821883a mov r16,r7 + 1008e20: dc400115 stw r17,4(sp) + 1008e24: 2827883a mov r19,r5 + 1008e28: 2029883a mov r20,r4 + 1008e2c: 2a000504 addi r8,r5,20 + 1008e30: 000f883a mov r7,zero + 1008e34: 40800017 ldw r2,0(r8) + 1008e38: 39c00044 addi r7,r7,1 + 1008e3c: 10ffffcc andi r3,r2,65535 + 1008e40: 1987383a mul r3,r3,r6 + 1008e44: 1004d43a srli r2,r2,16 + 1008e48: 1c07883a add r3,r3,r16 + 1008e4c: 180ad43a srli r5,r3,16 + 1008e50: 1185383a mul r2,r2,r6 + 1008e54: 18ffffcc andi r3,r3,65535 + 1008e58: 1145883a add r2,r2,r5 + 1008e5c: 1008943a slli r4,r2,16 + 1008e60: 1020d43a srli r16,r2,16 + 1008e64: 20c9883a add r4,r4,r3 + 1008e68: 41000015 stw r4,0(r8) + 1008e6c: 42000104 addi r8,r8,4 + 1008e70: 3cbff016 blt r7,r18,1008e34 <__multadd+0x34> + 1008e74: 80000826 beq r16,zero,1008e98 <__multadd+0x98> + 1008e78: 98800217 ldw r2,8(r19) + 1008e7c: 90800f0e bge r18,r2,1008ebc <__multadd+0xbc> + 1008e80: 9485883a add r2,r18,r18 + 1008e84: 1085883a add r2,r2,r2 + 1008e88: 14c5883a add r2,r2,r19 + 1008e8c: 90c00044 addi r3,r18,1 + 1008e90: 14000515 stw r16,20(r2) + 1008e94: 98c00415 stw r3,16(r19) + 1008e98: 9805883a mov r2,r19 + 1008e9c: dfc00517 ldw ra,20(sp) + 1008ea0: dd000417 ldw r20,16(sp) + 1008ea4: dcc00317 ldw r19,12(sp) + 1008ea8: dc800217 ldw r18,8(sp) + 1008eac: dc400117 ldw r17,4(sp) + 1008eb0: dc000017 ldw r16,0(sp) + 1008eb4: dec00604 addi sp,sp,24 + 1008eb8: f800283a ret + 1008ebc: 99400117 ldw r5,4(r19) + 1008ec0: a009883a mov r4,r20 + 1008ec4: 29400044 addi r5,r5,1 + 1008ec8: 10086cc0 call 10086cc <_Balloc> + 1008ecc: 99800417 ldw r6,16(r19) + 1008ed0: 99400304 addi r5,r19,12 + 1008ed4: 11000304 addi r4,r2,12 + 1008ed8: 318d883a add r6,r6,r6 + 1008edc: 318d883a add r6,r6,r6 + 1008ee0: 31800204 addi r6,r6,8 + 1008ee4: 1023883a mov r17,r2 + 1008ee8: 1007fcc0 call 1007fcc + 1008eec: 980b883a mov r5,r19 + 1008ef0: a009883a mov r4,r20 + 1008ef4: 100814c0 call 100814c <_Bfree> + 1008ef8: 8827883a mov r19,r17 + 1008efc: 003fe006 br 1008e80 <__multadd+0x80> + +01008f00 <__pow5mult>: + 1008f00: defffa04 addi sp,sp,-24 + 1008f04: 308000cc andi r2,r6,3 + 1008f08: dd000415 stw r20,16(sp) + 1008f0c: dcc00315 stw r19,12(sp) + 1008f10: dc000015 stw r16,0(sp) + 1008f14: dfc00515 stw ra,20(sp) + 1008f18: dc800215 stw r18,8(sp) + 1008f1c: dc400115 stw r17,4(sp) + 1008f20: 3021883a mov r16,r6 + 1008f24: 2027883a mov r19,r4 + 1008f28: 2829883a mov r20,r5 + 1008f2c: 10002b1e bne r2,zero,1008fdc <__pow5mult+0xdc> + 1008f30: 8025d0ba srai r18,r16,2 + 1008f34: 90001b26 beq r18,zero,1008fa4 <__pow5mult+0xa4> + 1008f38: 9c001217 ldw r16,72(r19) + 1008f3c: 8000081e bne r16,zero,1008f60 <__pow5mult+0x60> + 1008f40: 00003006 br 1009004 <__pow5mult+0x104> + 1008f44: 800b883a mov r5,r16 + 1008f48: 800d883a mov r6,r16 + 1008f4c: 9809883a mov r4,r19 + 1008f50: 90001426 beq r18,zero,1008fa4 <__pow5mult+0xa4> + 1008f54: 80800017 ldw r2,0(r16) + 1008f58: 10001b26 beq r2,zero,1008fc8 <__pow5mult+0xc8> + 1008f5c: 1021883a mov r16,r2 + 1008f60: 9080004c andi r2,r18,1 + 1008f64: 1005003a cmpeq r2,r2,zero + 1008f68: 9025d07a srai r18,r18,1 + 1008f6c: 800d883a mov r6,r16 + 1008f70: 9809883a mov r4,r19 + 1008f74: a00b883a mov r5,r20 + 1008f78: 103ff21e bne r2,zero,1008f44 <__pow5mult+0x44> + 1008f7c: 1008bdc0 call 1008bdc <__multiply> + 1008f80: a00b883a mov r5,r20 + 1008f84: 9809883a mov r4,r19 + 1008f88: 1023883a mov r17,r2 + 1008f8c: 100814c0 call 100814c <_Bfree> + 1008f90: 8829883a mov r20,r17 + 1008f94: 800b883a mov r5,r16 + 1008f98: 800d883a mov r6,r16 + 1008f9c: 9809883a mov r4,r19 + 1008fa0: 903fec1e bne r18,zero,1008f54 <__pow5mult+0x54> + 1008fa4: a005883a mov r2,r20 + 1008fa8: dfc00517 ldw ra,20(sp) + 1008fac: dd000417 ldw r20,16(sp) + 1008fb0: dcc00317 ldw r19,12(sp) + 1008fb4: dc800217 ldw r18,8(sp) + 1008fb8: dc400117 ldw r17,4(sp) + 1008fbc: dc000017 ldw r16,0(sp) + 1008fc0: dec00604 addi sp,sp,24 + 1008fc4: f800283a ret + 1008fc8: 1008bdc0 call 1008bdc <__multiply> + 1008fcc: 80800015 stw r2,0(r16) + 1008fd0: 1021883a mov r16,r2 + 1008fd4: 10000015 stw zero,0(r2) + 1008fd8: 003fe106 br 1008f60 <__pow5mult+0x60> + 1008fdc: 1085883a add r2,r2,r2 + 1008fe0: 00c040b4 movhi r3,258 + 1008fe4: 18e3e604 addi r3,r3,-28776 + 1008fe8: 1085883a add r2,r2,r2 + 1008fec: 10c5883a add r2,r2,r3 + 1008ff0: 11bfff17 ldw r6,-4(r2) + 1008ff4: 000f883a mov r7,zero + 1008ff8: 1008e000 call 1008e00 <__multadd> + 1008ffc: 1029883a mov r20,r2 + 1009000: 003fcb06 br 1008f30 <__pow5mult+0x30> + 1009004: 9809883a mov r4,r19 + 1009008: 01409c44 movi r5,625 + 100900c: 1008dc40 call 1008dc4 <__i2b> + 1009010: 98801215 stw r2,72(r19) + 1009014: 1021883a mov r16,r2 + 1009018: 10000015 stw zero,0(r2) + 100901c: 003fd006 br 1008f60 <__pow5mult+0x60> + +01009020 <__s2b>: + 1009020: defff904 addi sp,sp,-28 + 1009024: dcc00315 stw r19,12(sp) + 1009028: dc800215 stw r18,8(sp) + 100902c: 2827883a mov r19,r5 + 1009030: 2025883a mov r18,r4 + 1009034: 01400244 movi r5,9 + 1009038: 39000204 addi r4,r7,8 + 100903c: dd000415 stw r20,16(sp) + 1009040: dc400115 stw r17,4(sp) + 1009044: dfc00615 stw ra,24(sp) + 1009048: dd400515 stw r21,20(sp) + 100904c: dc000015 stw r16,0(sp) + 1009050: 3829883a mov r20,r7 + 1009054: 3023883a mov r17,r6 + 1009058: 100bb740 call 100bb74 <__divsi3> + 100905c: 00c00044 movi r3,1 + 1009060: 1880350e bge r3,r2,1009138 <__s2b+0x118> + 1009064: 000b883a mov r5,zero + 1009068: 18c7883a add r3,r3,r3 + 100906c: 29400044 addi r5,r5,1 + 1009070: 18bffd16 blt r3,r2,1009068 <__s2b+0x48> + 1009074: 9009883a mov r4,r18 + 1009078: 10086cc0 call 10086cc <_Balloc> + 100907c: 1011883a mov r8,r2 + 1009080: d8800717 ldw r2,28(sp) + 1009084: 00c00044 movi r3,1 + 1009088: 01800244 movi r6,9 + 100908c: 40800515 stw r2,20(r8) + 1009090: 40c00415 stw r3,16(r8) + 1009094: 3440260e bge r6,r17,1009130 <__s2b+0x110> + 1009098: 3021883a mov r16,r6 + 100909c: 99ab883a add r21,r19,r6 + 10090a0: 9c05883a add r2,r19,r16 + 10090a4: 11c00007 ldb r7,0(r2) + 10090a8: 400b883a mov r5,r8 + 10090ac: 9009883a mov r4,r18 + 10090b0: 39fff404 addi r7,r7,-48 + 10090b4: 01800284 movi r6,10 + 10090b8: 1008e000 call 1008e00 <__multadd> + 10090bc: 84000044 addi r16,r16,1 + 10090c0: 1011883a mov r8,r2 + 10090c4: 8c3ff61e bne r17,r16,10090a0 <__s2b+0x80> + 10090c8: ac45883a add r2,r21,r17 + 10090cc: 117ffe04 addi r5,r2,-8 + 10090d0: 880d883a mov r6,r17 + 10090d4: 35000c0e bge r6,r20,1009108 <__s2b+0xe8> + 10090d8: a185c83a sub r2,r20,r6 + 10090dc: 2821883a mov r16,r5 + 10090e0: 28a3883a add r17,r5,r2 + 10090e4: 81c00007 ldb r7,0(r16) + 10090e8: 400b883a mov r5,r8 + 10090ec: 9009883a mov r4,r18 + 10090f0: 39fff404 addi r7,r7,-48 + 10090f4: 01800284 movi r6,10 + 10090f8: 1008e000 call 1008e00 <__multadd> + 10090fc: 84000044 addi r16,r16,1 + 1009100: 1011883a mov r8,r2 + 1009104: 847ff71e bne r16,r17,10090e4 <__s2b+0xc4> + 1009108: 4005883a mov r2,r8 + 100910c: dfc00617 ldw ra,24(sp) + 1009110: dd400517 ldw r21,20(sp) + 1009114: dd000417 ldw r20,16(sp) + 1009118: dcc00317 ldw r19,12(sp) + 100911c: dc800217 ldw r18,8(sp) + 1009120: dc400117 ldw r17,4(sp) + 1009124: dc000017 ldw r16,0(sp) + 1009128: dec00704 addi sp,sp,28 + 100912c: f800283a ret + 1009130: 99400284 addi r5,r19,10 + 1009134: 003fe706 br 10090d4 <__s2b+0xb4> + 1009138: 000b883a mov r5,zero + 100913c: 003fcd06 br 1009074 <__s2b+0x54> + +01009140 <_realloc_r>: + 1009140: defff404 addi sp,sp,-48 + 1009144: dd800815 stw r22,32(sp) + 1009148: dc800415 stw r18,16(sp) + 100914c: dc400315 stw r17,12(sp) + 1009150: dfc00b15 stw ra,44(sp) + 1009154: df000a15 stw fp,40(sp) + 1009158: ddc00915 stw r23,36(sp) + 100915c: dd400715 stw r21,28(sp) + 1009160: dd000615 stw r20,24(sp) + 1009164: dcc00515 stw r19,20(sp) + 1009168: dc000215 stw r16,8(sp) + 100916c: 2825883a mov r18,r5 + 1009170: 3023883a mov r17,r6 + 1009174: 202d883a mov r22,r4 + 1009178: 2800c926 beq r5,zero,10094a0 <_realloc_r+0x360> + 100917c: 100d0a00 call 100d0a0 <__malloc_lock> + 1009180: 943ffe04 addi r16,r18,-8 + 1009184: 88c002c4 addi r3,r17,11 + 1009188: 00800584 movi r2,22 + 100918c: 82000117 ldw r8,4(r16) + 1009190: 10c01b2e bgeu r2,r3,1009200 <_realloc_r+0xc0> + 1009194: 00bffe04 movi r2,-8 + 1009198: 188e703a and r7,r3,r2 + 100919c: 3839883a mov fp,r7 + 10091a0: 38001a16 blt r7,zero,100920c <_realloc_r+0xcc> + 10091a4: e4401936 bltu fp,r17,100920c <_realloc_r+0xcc> + 10091a8: 013fff04 movi r4,-4 + 10091ac: 4126703a and r19,r8,r4 + 10091b0: 99c02616 blt r19,r7,100924c <_realloc_r+0x10c> + 10091b4: 802b883a mov r21,r16 + 10091b8: 9829883a mov r20,r19 + 10091bc: 84000204 addi r16,r16,8 + 10091c0: a80f883a mov r7,r21 + 10091c4: a70dc83a sub r6,r20,fp + 10091c8: 008003c4 movi r2,15 + 10091cc: 1180c136 bltu r2,r6,10094d4 <_realloc_r+0x394> + 10091d0: 38800117 ldw r2,4(r7) + 10091d4: a549883a add r4,r20,r21 + 10091d8: 1080004c andi r2,r2,1 + 10091dc: a084b03a or r2,r20,r2 + 10091e0: 38800115 stw r2,4(r7) + 10091e4: 20c00117 ldw r3,4(r4) + 10091e8: 18c00054 ori r3,r3,1 + 10091ec: 20c00115 stw r3,4(r4) + 10091f0: b009883a mov r4,r22 + 10091f4: 100d1a80 call 100d1a8 <__malloc_unlock> + 10091f8: 8023883a mov r17,r16 + 10091fc: 00000606 br 1009218 <_realloc_r+0xd8> + 1009200: 01c00404 movi r7,16 + 1009204: 3839883a mov fp,r7 + 1009208: e47fe72e bgeu fp,r17,10091a8 <_realloc_r+0x68> + 100920c: 00800304 movi r2,12 + 1009210: 0023883a mov r17,zero + 1009214: b0800015 stw r2,0(r22) + 1009218: 8805883a mov r2,r17 + 100921c: dfc00b17 ldw ra,44(sp) + 1009220: df000a17 ldw fp,40(sp) + 1009224: ddc00917 ldw r23,36(sp) + 1009228: dd800817 ldw r22,32(sp) + 100922c: dd400717 ldw r21,28(sp) + 1009230: dd000617 ldw r20,24(sp) + 1009234: dcc00517 ldw r19,20(sp) + 1009238: dc800417 ldw r18,16(sp) + 100923c: dc400317 ldw r17,12(sp) + 1009240: dc000217 ldw r16,8(sp) + 1009244: dec00c04 addi sp,sp,48 + 1009248: f800283a ret + 100924c: 008040b4 movhi r2,258 + 1009250: 10a49004 addi r2,r2,-28096 + 1009254: 12400217 ldw r9,8(r2) + 1009258: 84cd883a add r6,r16,r19 + 100925c: 802b883a mov r21,r16 + 1009260: 3240b926 beq r6,r9,1009548 <_realloc_r+0x408> + 1009264: 31400117 ldw r5,4(r6) + 1009268: 00bfff84 movi r2,-2 + 100926c: 2884703a and r2,r5,r2 + 1009270: 1185883a add r2,r2,r6 + 1009274: 10c00117 ldw r3,4(r2) + 1009278: 18c0004c andi r3,r3,1 + 100927c: 1807003a cmpeq r3,r3,zero + 1009280: 1800a326 beq r3,zero,1009510 <_realloc_r+0x3d0> + 1009284: 2908703a and r4,r5,r4 + 1009288: 9929883a add r20,r19,r4 + 100928c: a1c0a30e bge r20,r7,100951c <_realloc_r+0x3dc> + 1009290: 4080004c andi r2,r8,1 + 1009294: 1000551e bne r2,zero,10093ec <_realloc_r+0x2ac> + 1009298: 80800017 ldw r2,0(r16) + 100929c: 80afc83a sub r23,r16,r2 + 10092a0: b8c00117 ldw r3,4(r23) + 10092a4: 00bfff04 movi r2,-4 + 10092a8: 1884703a and r2,r3,r2 + 10092ac: 30002e26 beq r6,zero,1009368 <_realloc_r+0x228> + 10092b0: 3240b926 beq r6,r9,1009598 <_realloc_r+0x458> + 10092b4: 98a9883a add r20,r19,r2 + 10092b8: 2509883a add r4,r4,r20 + 10092bc: d9000015 stw r4,0(sp) + 10092c0: 21c02a16 blt r4,r7,100936c <_realloc_r+0x22c> + 10092c4: 30800317 ldw r2,12(r6) + 10092c8: 30c00217 ldw r3,8(r6) + 10092cc: 01400904 movi r5,36 + 10092d0: 99bfff04 addi r6,r19,-4 + 10092d4: 18800315 stw r2,12(r3) + 10092d8: 10c00215 stw r3,8(r2) + 10092dc: b9000317 ldw r4,12(r23) + 10092e0: b8800217 ldw r2,8(r23) + 10092e4: b82b883a mov r21,r23 + 10092e8: bc000204 addi r16,r23,8 + 10092ec: 20800215 stw r2,8(r4) + 10092f0: 11000315 stw r4,12(r2) + 10092f4: 2980e436 bltu r5,r6,1009688 <_realloc_r+0x548> + 10092f8: 008004c4 movi r2,19 + 10092fc: 9009883a mov r4,r18 + 1009300: 8011883a mov r8,r16 + 1009304: 11800f2e bgeu r2,r6,1009344 <_realloc_r+0x204> + 1009308: 90800017 ldw r2,0(r18) + 100930c: ba000404 addi r8,r23,16 + 1009310: 91000204 addi r4,r18,8 + 1009314: b8800215 stw r2,8(r23) + 1009318: 90c00117 ldw r3,4(r18) + 100931c: 008006c4 movi r2,27 + 1009320: b8c00315 stw r3,12(r23) + 1009324: 1180072e bgeu r2,r6,1009344 <_realloc_r+0x204> + 1009328: 90c00217 ldw r3,8(r18) + 100932c: ba000604 addi r8,r23,24 + 1009330: 91000404 addi r4,r18,16 + 1009334: b8c00415 stw r3,16(r23) + 1009338: 90800317 ldw r2,12(r18) + 100933c: b8800515 stw r2,20(r23) + 1009340: 3140e726 beq r6,r5,10096e0 <_realloc_r+0x5a0> + 1009344: 20800017 ldw r2,0(r4) + 1009348: dd000017 ldw r20,0(sp) + 100934c: b80f883a mov r7,r23 + 1009350: 40800015 stw r2,0(r8) + 1009354: 20c00117 ldw r3,4(r4) + 1009358: 40c00115 stw r3,4(r8) + 100935c: 20800217 ldw r2,8(r4) + 1009360: 40800215 stw r2,8(r8) + 1009364: 003f9706 br 10091c4 <_realloc_r+0x84> + 1009368: 98a9883a add r20,r19,r2 + 100936c: a1c01f16 blt r20,r7,10093ec <_realloc_r+0x2ac> + 1009370: b8c00317 ldw r3,12(r23) + 1009374: b8800217 ldw r2,8(r23) + 1009378: 99bfff04 addi r6,r19,-4 + 100937c: 01400904 movi r5,36 + 1009380: b82b883a mov r21,r23 + 1009384: 18800215 stw r2,8(r3) + 1009388: 10c00315 stw r3,12(r2) + 100938c: bc000204 addi r16,r23,8 + 1009390: 2980c336 bltu r5,r6,10096a0 <_realloc_r+0x560> + 1009394: 008004c4 movi r2,19 + 1009398: 9009883a mov r4,r18 + 100939c: 8011883a mov r8,r16 + 10093a0: 11800f2e bgeu r2,r6,10093e0 <_realloc_r+0x2a0> + 10093a4: 90800017 ldw r2,0(r18) + 10093a8: ba000404 addi r8,r23,16 + 10093ac: 91000204 addi r4,r18,8 + 10093b0: b8800215 stw r2,8(r23) + 10093b4: 90c00117 ldw r3,4(r18) + 10093b8: 008006c4 movi r2,27 + 10093bc: b8c00315 stw r3,12(r23) + 10093c0: 1180072e bgeu r2,r6,10093e0 <_realloc_r+0x2a0> + 10093c4: 90c00217 ldw r3,8(r18) + 10093c8: ba000604 addi r8,r23,24 + 10093cc: 91000404 addi r4,r18,16 + 10093d0: b8c00415 stw r3,16(r23) + 10093d4: 90800317 ldw r2,12(r18) + 10093d8: b8800515 stw r2,20(r23) + 10093dc: 3140c726 beq r6,r5,10096fc <_realloc_r+0x5bc> + 10093e0: 20800017 ldw r2,0(r4) + 10093e4: b80f883a mov r7,r23 + 10093e8: 003fd906 br 1009350 <_realloc_r+0x210> + 10093ec: 880b883a mov r5,r17 + 10093f0: b009883a mov r4,r22 + 10093f4: 10027dc0 call 10027dc <_malloc_r> + 10093f8: 1023883a mov r17,r2 + 10093fc: 10002526 beq r2,zero,1009494 <_realloc_r+0x354> + 1009400: 80800117 ldw r2,4(r16) + 1009404: 00ffff84 movi r3,-2 + 1009408: 893ffe04 addi r4,r17,-8 + 100940c: 10c4703a and r2,r2,r3 + 1009410: 8085883a add r2,r16,r2 + 1009414: 20809526 beq r4,r2,100966c <_realloc_r+0x52c> + 1009418: 99bfff04 addi r6,r19,-4 + 100941c: 01c00904 movi r7,36 + 1009420: 39804536 bltu r7,r6,1009538 <_realloc_r+0x3f8> + 1009424: 008004c4 movi r2,19 + 1009428: 9009883a mov r4,r18 + 100942c: 880b883a mov r5,r17 + 1009430: 11800f2e bgeu r2,r6,1009470 <_realloc_r+0x330> + 1009434: 90800017 ldw r2,0(r18) + 1009438: 89400204 addi r5,r17,8 + 100943c: 91000204 addi r4,r18,8 + 1009440: 88800015 stw r2,0(r17) + 1009444: 90c00117 ldw r3,4(r18) + 1009448: 008006c4 movi r2,27 + 100944c: 88c00115 stw r3,4(r17) + 1009450: 1180072e bgeu r2,r6,1009470 <_realloc_r+0x330> + 1009454: 90c00217 ldw r3,8(r18) + 1009458: 89400404 addi r5,r17,16 + 100945c: 91000404 addi r4,r18,16 + 1009460: 88c00215 stw r3,8(r17) + 1009464: 90800317 ldw r2,12(r18) + 1009468: 88800315 stw r2,12(r17) + 100946c: 31c09126 beq r6,r7,10096b4 <_realloc_r+0x574> + 1009470: 20800017 ldw r2,0(r4) + 1009474: 28800015 stw r2,0(r5) + 1009478: 20c00117 ldw r3,4(r4) + 100947c: 28c00115 stw r3,4(r5) + 1009480: 20800217 ldw r2,8(r4) + 1009484: 28800215 stw r2,8(r5) + 1009488: 900b883a mov r5,r18 + 100948c: b009883a mov r4,r22 + 1009490: 10073600 call 1007360 <_free_r> + 1009494: b009883a mov r4,r22 + 1009498: 100d1a80 call 100d1a8 <__malloc_unlock> + 100949c: 003f5e06 br 1009218 <_realloc_r+0xd8> + 10094a0: 300b883a mov r5,r6 + 10094a4: dfc00b17 ldw ra,44(sp) + 10094a8: df000a17 ldw fp,40(sp) + 10094ac: ddc00917 ldw r23,36(sp) + 10094b0: dd800817 ldw r22,32(sp) + 10094b4: dd400717 ldw r21,28(sp) + 10094b8: dd000617 ldw r20,24(sp) + 10094bc: dcc00517 ldw r19,20(sp) + 10094c0: dc800417 ldw r18,16(sp) + 10094c4: dc400317 ldw r17,12(sp) + 10094c8: dc000217 ldw r16,8(sp) + 10094cc: dec00c04 addi sp,sp,48 + 10094d0: 10027dc1 jmpi 10027dc <_malloc_r> + 10094d4: 38800117 ldw r2,4(r7) + 10094d8: e54b883a add r5,fp,r21 + 10094dc: 31000054 ori r4,r6,1 + 10094e0: 1080004c andi r2,r2,1 + 10094e4: 1704b03a or r2,r2,fp + 10094e8: 38800115 stw r2,4(r7) + 10094ec: 29000115 stw r4,4(r5) + 10094f0: 2987883a add r3,r5,r6 + 10094f4: 18800117 ldw r2,4(r3) + 10094f8: 29400204 addi r5,r5,8 + 10094fc: b009883a mov r4,r22 + 1009500: 10800054 ori r2,r2,1 + 1009504: 18800115 stw r2,4(r3) + 1009508: 10073600 call 1007360 <_free_r> + 100950c: 003f3806 br 10091f0 <_realloc_r+0xb0> + 1009510: 000d883a mov r6,zero + 1009514: 0009883a mov r4,zero + 1009518: 003f5d06 br 1009290 <_realloc_r+0x150> + 100951c: 30c00217 ldw r3,8(r6) + 1009520: 30800317 ldw r2,12(r6) + 1009524: 800f883a mov r7,r16 + 1009528: 84000204 addi r16,r16,8 + 100952c: 10c00215 stw r3,8(r2) + 1009530: 18800315 stw r2,12(r3) + 1009534: 003f2306 br 10091c4 <_realloc_r+0x84> + 1009538: 8809883a mov r4,r17 + 100953c: 900b883a mov r5,r18 + 1009540: 100806c0 call 100806c + 1009544: 003fd006 br 1009488 <_realloc_r+0x348> + 1009548: 30800117 ldw r2,4(r6) + 100954c: e0c00404 addi r3,fp,16 + 1009550: 1108703a and r4,r2,r4 + 1009554: 9905883a add r2,r19,r4 + 1009558: 10ff4d16 blt r2,r3,1009290 <_realloc_r+0x150> + 100955c: 1705c83a sub r2,r2,fp + 1009560: 870b883a add r5,r16,fp + 1009564: 10800054 ori r2,r2,1 + 1009568: 28800115 stw r2,4(r5) + 100956c: 80c00117 ldw r3,4(r16) + 1009570: 008040b4 movhi r2,258 + 1009574: 10a49004 addi r2,r2,-28096 + 1009578: b009883a mov r4,r22 + 100957c: 18c0004c andi r3,r3,1 + 1009580: e0c6b03a or r3,fp,r3 + 1009584: 11400215 stw r5,8(r2) + 1009588: 80c00115 stw r3,4(r16) + 100958c: 100d1a80 call 100d1a8 <__malloc_unlock> + 1009590: 84400204 addi r17,r16,8 + 1009594: 003f2006 br 1009218 <_realloc_r+0xd8> + 1009598: 98a9883a add r20,r19,r2 + 100959c: 2509883a add r4,r4,r20 + 10095a0: e0800404 addi r2,fp,16 + 10095a4: d9000115 stw r4,4(sp) + 10095a8: 20bf7016 blt r4,r2,100936c <_realloc_r+0x22c> + 10095ac: b8c00317 ldw r3,12(r23) + 10095b0: b8800217 ldw r2,8(r23) + 10095b4: 99bfff04 addi r6,r19,-4 + 10095b8: 01400904 movi r5,36 + 10095bc: 18800215 stw r2,8(r3) + 10095c0: 10c00315 stw r3,12(r2) + 10095c4: bc400204 addi r17,r23,8 + 10095c8: 29804136 bltu r5,r6,10096d0 <_realloc_r+0x590> + 10095cc: 008004c4 movi r2,19 + 10095d0: 9009883a mov r4,r18 + 10095d4: 880f883a mov r7,r17 + 10095d8: 11800f2e bgeu r2,r6,1009618 <_realloc_r+0x4d8> + 10095dc: 90800017 ldw r2,0(r18) + 10095e0: b9c00404 addi r7,r23,16 + 10095e4: 91000204 addi r4,r18,8 + 10095e8: b8800215 stw r2,8(r23) + 10095ec: 90c00117 ldw r3,4(r18) + 10095f0: 008006c4 movi r2,27 + 10095f4: b8c00315 stw r3,12(r23) + 10095f8: 1180072e bgeu r2,r6,1009618 <_realloc_r+0x4d8> + 10095fc: 90c00217 ldw r3,8(r18) + 1009600: b9c00604 addi r7,r23,24 + 1009604: 91000404 addi r4,r18,16 + 1009608: b8c00415 stw r3,16(r23) + 100960c: 90800317 ldw r2,12(r18) + 1009610: b8800515 stw r2,20(r23) + 1009614: 31404026 beq r6,r5,1009718 <_realloc_r+0x5d8> + 1009618: 20800017 ldw r2,0(r4) + 100961c: 38800015 stw r2,0(r7) + 1009620: 20c00117 ldw r3,4(r4) + 1009624: 38c00115 stw r3,4(r7) + 1009628: 20800217 ldw r2,8(r4) + 100962c: 38800215 stw r2,8(r7) + 1009630: d8c00117 ldw r3,4(sp) + 1009634: bf0b883a add r5,r23,fp + 1009638: b009883a mov r4,r22 + 100963c: 1f05c83a sub r2,r3,fp + 1009640: 10800054 ori r2,r2,1 + 1009644: 28800115 stw r2,4(r5) + 1009648: b8c00117 ldw r3,4(r23) + 100964c: 008040b4 movhi r2,258 + 1009650: 10a49004 addi r2,r2,-28096 + 1009654: 11400215 stw r5,8(r2) + 1009658: 18c0004c andi r3,r3,1 + 100965c: e0c6b03a or r3,fp,r3 + 1009660: b8c00115 stw r3,4(r23) + 1009664: 100d1a80 call 100d1a8 <__malloc_unlock> + 1009668: 003eeb06 br 1009218 <_realloc_r+0xd8> + 100966c: 20800117 ldw r2,4(r4) + 1009670: 00ffff04 movi r3,-4 + 1009674: 800f883a mov r7,r16 + 1009678: 10c4703a and r2,r2,r3 + 100967c: 98a9883a add r20,r19,r2 + 1009680: 84000204 addi r16,r16,8 + 1009684: 003ecf06 br 10091c4 <_realloc_r+0x84> + 1009688: 900b883a mov r5,r18 + 100968c: 8009883a mov r4,r16 + 1009690: 100806c0 call 100806c + 1009694: dd000017 ldw r20,0(sp) + 1009698: b80f883a mov r7,r23 + 100969c: 003ec906 br 10091c4 <_realloc_r+0x84> + 10096a0: 900b883a mov r5,r18 + 10096a4: 8009883a mov r4,r16 + 10096a8: 100806c0 call 100806c + 10096ac: b80f883a mov r7,r23 + 10096b0: 003ec406 br 10091c4 <_realloc_r+0x84> + 10096b4: 90c00417 ldw r3,16(r18) + 10096b8: 89400604 addi r5,r17,24 + 10096bc: 91000604 addi r4,r18,24 + 10096c0: 88c00415 stw r3,16(r17) + 10096c4: 90800517 ldw r2,20(r18) + 10096c8: 88800515 stw r2,20(r17) + 10096cc: 003f6806 br 1009470 <_realloc_r+0x330> + 10096d0: 900b883a mov r5,r18 + 10096d4: 8809883a mov r4,r17 + 10096d8: 100806c0 call 100806c + 10096dc: 003fd406 br 1009630 <_realloc_r+0x4f0> + 10096e0: 90c00417 ldw r3,16(r18) + 10096e4: 91000604 addi r4,r18,24 + 10096e8: ba000804 addi r8,r23,32 + 10096ec: b8c00615 stw r3,24(r23) + 10096f0: 90800517 ldw r2,20(r18) + 10096f4: b8800715 stw r2,28(r23) + 10096f8: 003f1206 br 1009344 <_realloc_r+0x204> + 10096fc: 90c00417 ldw r3,16(r18) + 1009700: 91000604 addi r4,r18,24 + 1009704: ba000804 addi r8,r23,32 + 1009708: b8c00615 stw r3,24(r23) + 100970c: 90800517 ldw r2,20(r18) + 1009710: b8800715 stw r2,28(r23) + 1009714: 003f3206 br 10093e0 <_realloc_r+0x2a0> + 1009718: 90c00417 ldw r3,16(r18) + 100971c: 91000604 addi r4,r18,24 + 1009720: b9c00804 addi r7,r23,32 + 1009724: b8c00615 stw r3,24(r23) + 1009728: 90800517 ldw r2,20(r18) + 100972c: b8800715 stw r2,28(r23) + 1009730: 003fb906 br 1009618 <_realloc_r+0x4d8> + +01009734 <__isinfd>: + 1009734: 200d883a mov r6,r4 + 1009738: 0109c83a sub r4,zero,r4 + 100973c: 2188b03a or r4,r4,r6 + 1009740: 2008d7fa srli r4,r4,31 + 1009744: 00a00034 movhi r2,32768 + 1009748: 10bfffc4 addi r2,r2,-1 + 100974c: 1144703a and r2,r2,r5 + 1009750: 2088b03a or r4,r4,r2 + 1009754: 009ffc34 movhi r2,32752 + 1009758: 1105c83a sub r2,r2,r4 + 100975c: 0087c83a sub r3,zero,r2 + 1009760: 10c4b03a or r2,r2,r3 + 1009764: 1004d7fa srli r2,r2,31 + 1009768: 00c00044 movi r3,1 + 100976c: 1885c83a sub r2,r3,r2 + 1009770: f800283a ret + +01009774 <__isnand>: + 1009774: 200d883a mov r6,r4 + 1009778: 0109c83a sub r4,zero,r4 + 100977c: 2188b03a or r4,r4,r6 + 1009780: 2008d7fa srli r4,r4,31 + 1009784: 00a00034 movhi r2,32768 + 1009788: 10bfffc4 addi r2,r2,-1 + 100978c: 1144703a and r2,r2,r5 + 1009790: 2088b03a or r4,r4,r2 + 1009794: 009ffc34 movhi r2,32752 + 1009798: 1105c83a sub r2,r2,r4 + 100979c: 1004d7fa srli r2,r2,31 + 10097a0: f800283a ret + +010097a4 <__sclose>: + 10097a4: 2940038f ldh r5,14(r5) + 10097a8: 1009ad81 jmpi 1009ad8 <_close_r> + +010097ac <__sseek>: + 10097ac: defffe04 addi sp,sp,-8 + 10097b0: dc000015 stw r16,0(sp) + 10097b4: 2821883a mov r16,r5 + 10097b8: 2940038f ldh r5,14(r5) + 10097bc: dfc00115 stw ra,4(sp) + 10097c0: 1009d500 call 1009d50 <_lseek_r> + 10097c4: 1007883a mov r3,r2 + 10097c8: 00bfffc4 movi r2,-1 + 10097cc: 18800926 beq r3,r2,10097f4 <__sseek+0x48> + 10097d0: 8080030b ldhu r2,12(r16) + 10097d4: 80c01415 stw r3,80(r16) + 10097d8: 10840014 ori r2,r2,4096 + 10097dc: 8080030d sth r2,12(r16) + 10097e0: 1805883a mov r2,r3 + 10097e4: dfc00117 ldw ra,4(sp) + 10097e8: dc000017 ldw r16,0(sp) + 10097ec: dec00204 addi sp,sp,8 + 10097f0: f800283a ret + 10097f4: 8080030b ldhu r2,12(r16) + 10097f8: 10bbffcc andi r2,r2,61439 + 10097fc: 8080030d sth r2,12(r16) + 1009800: 1805883a mov r2,r3 + 1009804: dfc00117 ldw ra,4(sp) + 1009808: dc000017 ldw r16,0(sp) + 100980c: dec00204 addi sp,sp,8 + 1009810: f800283a ret + +01009814 <__swrite>: + 1009814: 2880030b ldhu r2,12(r5) + 1009818: defffb04 addi sp,sp,-20 + 100981c: dcc00315 stw r19,12(sp) + 1009820: 1080400c andi r2,r2,256 + 1009824: dc800215 stw r18,8(sp) + 1009828: dc400115 stw r17,4(sp) + 100982c: dc000015 stw r16,0(sp) + 1009830: 3027883a mov r19,r6 + 1009834: 3825883a mov r18,r7 + 1009838: dfc00415 stw ra,16(sp) + 100983c: 2821883a mov r16,r5 + 1009840: 000d883a mov r6,zero + 1009844: 01c00084 movi r7,2 + 1009848: 2023883a mov r17,r4 + 100984c: 10000226 beq r2,zero,1009858 <__swrite+0x44> + 1009850: 2940038f ldh r5,14(r5) + 1009854: 1009d500 call 1009d50 <_lseek_r> + 1009858: 8080030b ldhu r2,12(r16) + 100985c: 8140038f ldh r5,14(r16) + 1009860: 8809883a mov r4,r17 + 1009864: 10bbffcc andi r2,r2,61439 + 1009868: 980d883a mov r6,r19 + 100986c: 900f883a mov r7,r18 + 1009870: 8080030d sth r2,12(r16) + 1009874: dfc00417 ldw ra,16(sp) + 1009878: dcc00317 ldw r19,12(sp) + 100987c: dc800217 ldw r18,8(sp) + 1009880: dc400117 ldw r17,4(sp) + 1009884: dc000017 ldw r16,0(sp) + 1009888: dec00504 addi sp,sp,20 + 100988c: 10099ac1 jmpi 10099ac <_write_r> + +01009890 <__sread>: + 1009890: defffe04 addi sp,sp,-8 + 1009894: dc000015 stw r16,0(sp) + 1009898: 2821883a mov r16,r5 + 100989c: 2940038f ldh r5,14(r5) + 10098a0: dfc00115 stw ra,4(sp) + 10098a4: 1009dc80 call 1009dc8 <_read_r> + 10098a8: 1007883a mov r3,r2 + 10098ac: 10000816 blt r2,zero,10098d0 <__sread+0x40> + 10098b0: 80801417 ldw r2,80(r16) + 10098b4: 10c5883a add r2,r2,r3 + 10098b8: 80801415 stw r2,80(r16) + 10098bc: 1805883a mov r2,r3 + 10098c0: dfc00117 ldw ra,4(sp) + 10098c4: dc000017 ldw r16,0(sp) + 10098c8: dec00204 addi sp,sp,8 + 10098cc: f800283a ret + 10098d0: 8080030b ldhu r2,12(r16) + 10098d4: 10bbffcc andi r2,r2,61439 + 10098d8: 8080030d sth r2,12(r16) + 10098dc: 1805883a mov r2,r3 + 10098e0: dfc00117 ldw ra,4(sp) + 10098e4: dc000017 ldw r16,0(sp) + 10098e8: dec00204 addi sp,sp,8 + 10098ec: f800283a ret + +010098f0 : + 10098f0: 2144b03a or r2,r4,r5 + 10098f4: 108000cc andi r2,r2,3 + 10098f8: 10001d1e bne r2,zero,1009970 + 10098fc: 200f883a mov r7,r4 + 1009900: 28800017 ldw r2,0(r5) + 1009904: 21000017 ldw r4,0(r4) + 1009908: 280d883a mov r6,r5 + 100990c: 2080161e bne r4,r2,1009968 + 1009910: 023fbff4 movhi r8,65279 + 1009914: 423fbfc4 addi r8,r8,-257 + 1009918: 2207883a add r3,r4,r8 + 100991c: 01602074 movhi r5,32897 + 1009920: 29602004 addi r5,r5,-32640 + 1009924: 1946703a and r3,r3,r5 + 1009928: 0104303a nor r2,zero,r4 + 100992c: 10c4703a and r2,r2,r3 + 1009930: 10001c1e bne r2,zero,10099a4 + 1009934: 4013883a mov r9,r8 + 1009938: 2811883a mov r8,r5 + 100993c: 00000106 br 1009944 + 1009940: 1800181e bne r3,zero,10099a4 + 1009944: 39c00104 addi r7,r7,4 + 1009948: 39000017 ldw r4,0(r7) + 100994c: 31800104 addi r6,r6,4 + 1009950: 31400017 ldw r5,0(r6) + 1009954: 2245883a add r2,r4,r9 + 1009958: 1204703a and r2,r2,r8 + 100995c: 0106303a nor r3,zero,r4 + 1009960: 1886703a and r3,r3,r2 + 1009964: 217ff626 beq r4,r5,1009940 + 1009968: 3809883a mov r4,r7 + 100996c: 300b883a mov r5,r6 + 1009970: 20c00007 ldb r3,0(r4) + 1009974: 1800051e bne r3,zero,100998c + 1009978: 00000606 br 1009994 + 100997c: 21000044 addi r4,r4,1 + 1009980: 20c00007 ldb r3,0(r4) + 1009984: 29400044 addi r5,r5,1 + 1009988: 18000226 beq r3,zero,1009994 + 100998c: 28800007 ldb r2,0(r5) + 1009990: 18bffa26 beq r3,r2,100997c + 1009994: 20c00003 ldbu r3,0(r4) + 1009998: 28800003 ldbu r2,0(r5) + 100999c: 1885c83a sub r2,r3,r2 + 10099a0: f800283a ret + 10099a4: 0005883a mov r2,zero + 10099a8: f800283a ret + +010099ac <_write_r>: + 10099ac: defffd04 addi sp,sp,-12 + 10099b0: dc000015 stw r16,0(sp) + 10099b4: 040040b4 movhi r16,258 + 10099b8: 84330404 addi r16,r16,-13296 + 10099bc: dc400115 stw r17,4(sp) + 10099c0: 80000015 stw zero,0(r16) + 10099c4: 2023883a mov r17,r4 + 10099c8: 2809883a mov r4,r5 + 10099cc: 300b883a mov r5,r6 + 10099d0: 380d883a mov r6,r7 + 10099d4: dfc00215 stw ra,8(sp) + 10099d8: 100ce180 call 100ce18 + 10099dc: 1007883a mov r3,r2 + 10099e0: 00bfffc4 movi r2,-1 + 10099e4: 18800626 beq r3,r2,1009a00 <_write_r+0x54> + 10099e8: 1805883a mov r2,r3 + 10099ec: dfc00217 ldw ra,8(sp) + 10099f0: dc400117 ldw r17,4(sp) + 10099f4: dc000017 ldw r16,0(sp) + 10099f8: dec00304 addi sp,sp,12 + 10099fc: f800283a ret + 1009a00: 80800017 ldw r2,0(r16) + 1009a04: 103ff826 beq r2,zero,10099e8 <_write_r+0x3c> + 1009a08: 88800015 stw r2,0(r17) + 1009a0c: 1805883a mov r2,r3 + 1009a10: dfc00217 ldw ra,8(sp) + 1009a14: dc400117 ldw r17,4(sp) + 1009a18: dc000017 ldw r16,0(sp) + 1009a1c: dec00304 addi sp,sp,12 + 1009a20: f800283a ret + +01009a24 <_calloc_r>: + 1009a24: 298b383a mul r5,r5,r6 + 1009a28: defffe04 addi sp,sp,-8 + 1009a2c: dc000015 stw r16,0(sp) + 1009a30: dfc00115 stw ra,4(sp) + 1009a34: 10027dc0 call 10027dc <_malloc_r> + 1009a38: 1021883a mov r16,r2 + 1009a3c: 01c00904 movi r7,36 + 1009a40: 10000d26 beq r2,zero,1009a78 <_calloc_r+0x54> + 1009a44: 10ffff17 ldw r3,-4(r2) + 1009a48: 1009883a mov r4,r2 + 1009a4c: 00bfff04 movi r2,-4 + 1009a50: 1886703a and r3,r3,r2 + 1009a54: 1887883a add r3,r3,r2 + 1009a58: 180d883a mov r6,r3 + 1009a5c: 000b883a mov r5,zero + 1009a60: 38c01736 bltu r7,r3,1009ac0 <_calloc_r+0x9c> + 1009a64: 008004c4 movi r2,19 + 1009a68: 10c00836 bltu r2,r3,1009a8c <_calloc_r+0x68> + 1009a6c: 20000215 stw zero,8(r4) + 1009a70: 20000015 stw zero,0(r4) + 1009a74: 20000115 stw zero,4(r4) + 1009a78: 8005883a mov r2,r16 + 1009a7c: dfc00117 ldw ra,4(sp) + 1009a80: dc000017 ldw r16,0(sp) + 1009a84: dec00204 addi sp,sp,8 + 1009a88: f800283a ret + 1009a8c: 008006c4 movi r2,27 + 1009a90: 80000015 stw zero,0(r16) + 1009a94: 80000115 stw zero,4(r16) + 1009a98: 81000204 addi r4,r16,8 + 1009a9c: 10fff32e bgeu r2,r3,1009a6c <_calloc_r+0x48> + 1009aa0: 80000215 stw zero,8(r16) + 1009aa4: 80000315 stw zero,12(r16) + 1009aa8: 81000404 addi r4,r16,16 + 1009aac: 19ffef1e bne r3,r7,1009a6c <_calloc_r+0x48> + 1009ab0: 81000604 addi r4,r16,24 + 1009ab4: 80000415 stw zero,16(r16) + 1009ab8: 80000515 stw zero,20(r16) + 1009abc: 003feb06 br 1009a6c <_calloc_r+0x48> + 1009ac0: 1002f1c0 call 1002f1c + 1009ac4: 8005883a mov r2,r16 + 1009ac8: dfc00117 ldw ra,4(sp) + 1009acc: dc000017 ldw r16,0(sp) + 1009ad0: dec00204 addi sp,sp,8 + 1009ad4: f800283a ret + +01009ad8 <_close_r>: + 1009ad8: defffd04 addi sp,sp,-12 + 1009adc: dc000015 stw r16,0(sp) + 1009ae0: 040040b4 movhi r16,258 + 1009ae4: 84330404 addi r16,r16,-13296 + 1009ae8: dc400115 stw r17,4(sp) + 1009aec: 80000015 stw zero,0(r16) + 1009af0: 2023883a mov r17,r4 + 1009af4: 2809883a mov r4,r5 + 1009af8: dfc00215 stw ra,8(sp) + 1009afc: 100c2700 call 100c270 + 1009b00: 1007883a mov r3,r2 + 1009b04: 00bfffc4 movi r2,-1 + 1009b08: 18800626 beq r3,r2,1009b24 <_close_r+0x4c> + 1009b0c: 1805883a mov r2,r3 + 1009b10: dfc00217 ldw ra,8(sp) + 1009b14: dc400117 ldw r17,4(sp) + 1009b18: dc000017 ldw r16,0(sp) + 1009b1c: dec00304 addi sp,sp,12 + 1009b20: f800283a ret + 1009b24: 80800017 ldw r2,0(r16) + 1009b28: 103ff826 beq r2,zero,1009b0c <_close_r+0x34> + 1009b2c: 88800015 stw r2,0(r17) + 1009b30: 1805883a mov r2,r3 + 1009b34: dfc00217 ldw ra,8(sp) + 1009b38: dc400117 ldw r17,4(sp) + 1009b3c: dc000017 ldw r16,0(sp) + 1009b40: dec00304 addi sp,sp,12 + 1009b44: f800283a ret + +01009b48 <_fclose_r>: + 1009b48: defffc04 addi sp,sp,-16 + 1009b4c: dc400115 stw r17,4(sp) + 1009b50: dc000015 stw r16,0(sp) + 1009b54: dfc00315 stw ra,12(sp) + 1009b58: dc800215 stw r18,8(sp) + 1009b5c: 2821883a mov r16,r5 + 1009b60: 2023883a mov r17,r4 + 1009b64: 28002926 beq r5,zero,1009c0c <_fclose_r+0xc4> + 1009b68: 1006fcc0 call 1006fcc <__sfp_lock_acquire> + 1009b6c: 88000226 beq r17,zero,1009b78 <_fclose_r+0x30> + 1009b70: 88800e17 ldw r2,56(r17) + 1009b74: 10002d26 beq r2,zero,1009c2c <_fclose_r+0xe4> + 1009b78: 8080030f ldh r2,12(r16) + 1009b7c: 10002226 beq r2,zero,1009c08 <_fclose_r+0xc0> + 1009b80: 8809883a mov r4,r17 + 1009b84: 800b883a mov r5,r16 + 1009b88: 1006d440 call 1006d44 <_fflush_r> + 1009b8c: 1025883a mov r18,r2 + 1009b90: 80800b17 ldw r2,44(r16) + 1009b94: 10000426 beq r2,zero,1009ba8 <_fclose_r+0x60> + 1009b98: 81400717 ldw r5,28(r16) + 1009b9c: 8809883a mov r4,r17 + 1009ba0: 103ee83a callr r2 + 1009ba4: 10002a16 blt r2,zero,1009c50 <_fclose_r+0x108> + 1009ba8: 8080030b ldhu r2,12(r16) + 1009bac: 1080200c andi r2,r2,128 + 1009bb0: 1000231e bne r2,zero,1009c40 <_fclose_r+0xf8> + 1009bb4: 81400c17 ldw r5,48(r16) + 1009bb8: 28000526 beq r5,zero,1009bd0 <_fclose_r+0x88> + 1009bbc: 80801004 addi r2,r16,64 + 1009bc0: 28800226 beq r5,r2,1009bcc <_fclose_r+0x84> + 1009bc4: 8809883a mov r4,r17 + 1009bc8: 10073600 call 1007360 <_free_r> + 1009bcc: 80000c15 stw zero,48(r16) + 1009bd0: 81401117 ldw r5,68(r16) + 1009bd4: 28000326 beq r5,zero,1009be4 <_fclose_r+0x9c> + 1009bd8: 8809883a mov r4,r17 + 1009bdc: 10073600 call 1007360 <_free_r> + 1009be0: 80001115 stw zero,68(r16) + 1009be4: 8000030d sth zero,12(r16) + 1009be8: 1006fd00 call 1006fd0 <__sfp_lock_release> + 1009bec: 9005883a mov r2,r18 + 1009bf0: dfc00317 ldw ra,12(sp) + 1009bf4: dc800217 ldw r18,8(sp) + 1009bf8: dc400117 ldw r17,4(sp) + 1009bfc: dc000017 ldw r16,0(sp) + 1009c00: dec00404 addi sp,sp,16 + 1009c04: f800283a ret + 1009c08: 1006fd00 call 1006fd0 <__sfp_lock_release> + 1009c0c: 0025883a mov r18,zero + 1009c10: 9005883a mov r2,r18 + 1009c14: dfc00317 ldw ra,12(sp) + 1009c18: dc800217 ldw r18,8(sp) + 1009c1c: dc400117 ldw r17,4(sp) + 1009c20: dc000017 ldw r16,0(sp) + 1009c24: dec00404 addi sp,sp,16 + 1009c28: f800283a ret + 1009c2c: 8809883a mov r4,r17 + 1009c30: 1006fdc0 call 1006fdc <__sinit> + 1009c34: 8080030f ldh r2,12(r16) + 1009c38: 103fd11e bne r2,zero,1009b80 <_fclose_r+0x38> + 1009c3c: 003ff206 br 1009c08 <_fclose_r+0xc0> + 1009c40: 81400417 ldw r5,16(r16) + 1009c44: 8809883a mov r4,r17 + 1009c48: 10073600 call 1007360 <_free_r> + 1009c4c: 003fd906 br 1009bb4 <_fclose_r+0x6c> + 1009c50: 04bfffc4 movi r18,-1 + 1009c54: 003fd406 br 1009ba8 <_fclose_r+0x60> + +01009c58 : + 1009c58: 008040b4 movhi r2,258 + 1009c5c: 10ab9804 addi r2,r2,-20896 + 1009c60: 200b883a mov r5,r4 + 1009c64: 11000017 ldw r4,0(r2) + 1009c68: 1009b481 jmpi 1009b48 <_fclose_r> + +01009c6c <_fstat_r>: + 1009c6c: defffd04 addi sp,sp,-12 + 1009c70: dc000015 stw r16,0(sp) + 1009c74: 040040b4 movhi r16,258 + 1009c78: 84330404 addi r16,r16,-13296 + 1009c7c: dc400115 stw r17,4(sp) + 1009c80: 80000015 stw zero,0(r16) + 1009c84: 2023883a mov r17,r4 + 1009c88: 2809883a mov r4,r5 + 1009c8c: 300b883a mov r5,r6 + 1009c90: dfc00215 stw ra,8(sp) + 1009c94: 100c4640 call 100c464 + 1009c98: 1007883a mov r3,r2 + 1009c9c: 00bfffc4 movi r2,-1 + 1009ca0: 18800626 beq r3,r2,1009cbc <_fstat_r+0x50> + 1009ca4: 1805883a mov r2,r3 + 1009ca8: dfc00217 ldw ra,8(sp) + 1009cac: dc400117 ldw r17,4(sp) + 1009cb0: dc000017 ldw r16,0(sp) + 1009cb4: dec00304 addi sp,sp,12 + 1009cb8: f800283a ret + 1009cbc: 80800017 ldw r2,0(r16) + 1009cc0: 103ff826 beq r2,zero,1009ca4 <_fstat_r+0x38> + 1009cc4: 88800015 stw r2,0(r17) + 1009cc8: 1805883a mov r2,r3 + 1009ccc: dfc00217 ldw ra,8(sp) + 1009cd0: dc400117 ldw r17,4(sp) + 1009cd4: dc000017 ldw r16,0(sp) + 1009cd8: dec00304 addi sp,sp,12 + 1009cdc: f800283a ret + +01009ce0 <_isatty_r>: + 1009ce0: defffd04 addi sp,sp,-12 + 1009ce4: dc000015 stw r16,0(sp) + 1009ce8: 040040b4 movhi r16,258 + 1009cec: 84330404 addi r16,r16,-13296 + 1009cf0: dc400115 stw r17,4(sp) + 1009cf4: 80000015 stw zero,0(r16) + 1009cf8: 2023883a mov r17,r4 + 1009cfc: 2809883a mov r4,r5 + 1009d00: dfc00215 stw ra,8(sp) + 1009d04: 100c5b80 call 100c5b8 + 1009d08: 1007883a mov r3,r2 + 1009d0c: 00bfffc4 movi r2,-1 + 1009d10: 18800626 beq r3,r2,1009d2c <_isatty_r+0x4c> + 1009d14: 1805883a mov r2,r3 + 1009d18: dfc00217 ldw ra,8(sp) + 1009d1c: dc400117 ldw r17,4(sp) + 1009d20: dc000017 ldw r16,0(sp) + 1009d24: dec00304 addi sp,sp,12 + 1009d28: f800283a ret + 1009d2c: 80800017 ldw r2,0(r16) + 1009d30: 103ff826 beq r2,zero,1009d14 <_isatty_r+0x34> + 1009d34: 88800015 stw r2,0(r17) + 1009d38: 1805883a mov r2,r3 + 1009d3c: dfc00217 ldw ra,8(sp) + 1009d40: dc400117 ldw r17,4(sp) + 1009d44: dc000017 ldw r16,0(sp) + 1009d48: dec00304 addi sp,sp,12 + 1009d4c: f800283a ret + +01009d50 <_lseek_r>: + 1009d50: defffd04 addi sp,sp,-12 + 1009d54: dc000015 stw r16,0(sp) + 1009d58: 040040b4 movhi r16,258 + 1009d5c: 84330404 addi r16,r16,-13296 + 1009d60: dc400115 stw r17,4(sp) + 1009d64: 80000015 stw zero,0(r16) + 1009d68: 2023883a mov r17,r4 + 1009d6c: 2809883a mov r4,r5 + 1009d70: 300b883a mov r5,r6 + 1009d74: 380d883a mov r6,r7 + 1009d78: dfc00215 stw ra,8(sp) + 1009d7c: 100c9640 call 100c964 + 1009d80: 1007883a mov r3,r2 + 1009d84: 00bfffc4 movi r2,-1 + 1009d88: 18800626 beq r3,r2,1009da4 <_lseek_r+0x54> + 1009d8c: 1805883a mov r2,r3 + 1009d90: dfc00217 ldw ra,8(sp) + 1009d94: dc400117 ldw r17,4(sp) + 1009d98: dc000017 ldw r16,0(sp) + 1009d9c: dec00304 addi sp,sp,12 + 1009da0: f800283a ret + 1009da4: 80800017 ldw r2,0(r16) + 1009da8: 103ff826 beq r2,zero,1009d8c <_lseek_r+0x3c> + 1009dac: 88800015 stw r2,0(r17) + 1009db0: 1805883a mov r2,r3 + 1009db4: dfc00217 ldw ra,8(sp) + 1009db8: dc400117 ldw r17,4(sp) + 1009dbc: dc000017 ldw r16,0(sp) + 1009dc0: dec00304 addi sp,sp,12 + 1009dc4: f800283a ret + +01009dc8 <_read_r>: + 1009dc8: defffd04 addi sp,sp,-12 + 1009dcc: dc000015 stw r16,0(sp) + 1009dd0: 040040b4 movhi r16,258 + 1009dd4: 84330404 addi r16,r16,-13296 + 1009dd8: dc400115 stw r17,4(sp) + 1009ddc: 80000015 stw zero,0(r16) + 1009de0: 2023883a mov r17,r4 + 1009de4: 2809883a mov r4,r5 + 1009de8: 300b883a mov r5,r6 + 1009dec: 380d883a mov r6,r7 + 1009df0: dfc00215 stw ra,8(sp) + 1009df4: 100cb7c0 call 100cb7c + 1009df8: 1007883a mov r3,r2 + 1009dfc: 00bfffc4 movi r2,-1 + 1009e00: 18800626 beq r3,r2,1009e1c <_read_r+0x54> + 1009e04: 1805883a mov r2,r3 + 1009e08: dfc00217 ldw ra,8(sp) + 1009e0c: dc400117 ldw r17,4(sp) + 1009e10: dc000017 ldw r16,0(sp) + 1009e14: dec00304 addi sp,sp,12 + 1009e18: f800283a ret + 1009e1c: 80800017 ldw r2,0(r16) + 1009e20: 103ff826 beq r2,zero,1009e04 <_read_r+0x3c> + 1009e24: 88800015 stw r2,0(r17) + 1009e28: 1805883a mov r2,r3 + 1009e2c: dfc00217 ldw ra,8(sp) + 1009e30: dc400117 ldw r17,4(sp) + 1009e34: dc000017 ldw r16,0(sp) + 1009e38: dec00304 addi sp,sp,12 + 1009e3c: f800283a ret + +01009e40 <__udivdi3>: + 1009e40: defff004 addi sp,sp,-64 + 1009e44: 2005883a mov r2,r4 + 1009e48: 3011883a mov r8,r6 + 1009e4c: df000e15 stw fp,56(sp) + 1009e50: dd000a15 stw r20,40(sp) + 1009e54: dc000615 stw r16,24(sp) + 1009e58: dfc00f15 stw ra,60(sp) + 1009e5c: ddc00d15 stw r23,52(sp) + 1009e60: dd800c15 stw r22,48(sp) + 1009e64: dd400b15 stw r21,44(sp) + 1009e68: dcc00915 stw r19,36(sp) + 1009e6c: dc800815 stw r18,32(sp) + 1009e70: dc400715 stw r17,28(sp) + 1009e74: 4021883a mov r16,r8 + 1009e78: 1039883a mov fp,r2 + 1009e7c: 2829883a mov r20,r5 + 1009e80: 38003b1e bne r7,zero,1009f70 <__udivdi3+0x130> + 1009e84: 2a005c36 bltu r5,r8,1009ff8 <__udivdi3+0x1b8> + 1009e88: 4000a626 beq r8,zero,100a124 <__udivdi3+0x2e4> + 1009e8c: 00bfffd4 movui r2,65535 + 1009e90: 14009e36 bltu r2,r16,100a10c <__udivdi3+0x2cc> + 1009e94: 00803fc4 movi r2,255 + 1009e98: 14013d36 bltu r2,r16,100a390 <__udivdi3+0x550> + 1009e9c: 000b883a mov r5,zero + 1009ea0: 0005883a mov r2,zero + 1009ea4: 8084d83a srl r2,r16,r2 + 1009ea8: 010040b4 movhi r4,258 + 1009eac: 2123ee04 addi r4,r4,-28744 + 1009eb0: 01800804 movi r6,32 + 1009eb4: 1105883a add r2,r2,r4 + 1009eb8: 10c00003 ldbu r3,0(r2) + 1009ebc: 28c7883a add r3,r5,r3 + 1009ec0: 30edc83a sub r22,r6,r3 + 1009ec4: b000ee1e bne r22,zero,100a280 <__udivdi3+0x440> + 1009ec8: 802ad43a srli r21,r16,16 + 1009ecc: 00800044 movi r2,1 + 1009ed0: a423c83a sub r17,r20,r16 + 1009ed4: 85ffffcc andi r23,r16,65535 + 1009ed8: d8800315 stw r2,12(sp) + 1009edc: 8809883a mov r4,r17 + 1009ee0: a80b883a mov r5,r21 + 1009ee4: 100bc340 call 100bc34 <__udivsi3> + 1009ee8: 8809883a mov r4,r17 + 1009eec: a80b883a mov r5,r21 + 1009ef0: 102d883a mov r22,r2 + 1009ef4: 100bc3c0 call 100bc3c <__umodsi3> + 1009ef8: 1004943a slli r2,r2,16 + 1009efc: e006d43a srli r3,fp,16 + 1009f00: bda3383a mul r17,r23,r22 + 1009f04: 10c4b03a or r2,r2,r3 + 1009f08: 1440042e bgeu r2,r17,1009f1c <__udivdi3+0xdc> + 1009f0c: 1405883a add r2,r2,r16 + 1009f10: b5bfffc4 addi r22,r22,-1 + 1009f14: 14000136 bltu r2,r16,1009f1c <__udivdi3+0xdc> + 1009f18: 14413d36 bltu r2,r17,100a410 <__udivdi3+0x5d0> + 1009f1c: 1463c83a sub r17,r2,r17 + 1009f20: 8809883a mov r4,r17 + 1009f24: a80b883a mov r5,r21 + 1009f28: 100bc340 call 100bc34 <__udivsi3> + 1009f2c: 8809883a mov r4,r17 + 1009f30: a80b883a mov r5,r21 + 1009f34: 1029883a mov r20,r2 + 1009f38: 100bc3c0 call 100bc3c <__umodsi3> + 1009f3c: 1004943a slli r2,r2,16 + 1009f40: bd09383a mul r4,r23,r20 + 1009f44: e0ffffcc andi r3,fp,65535 + 1009f48: 10c4b03a or r2,r2,r3 + 1009f4c: 1100042e bgeu r2,r4,1009f60 <__udivdi3+0x120> + 1009f50: 8085883a add r2,r16,r2 + 1009f54: a53fffc4 addi r20,r20,-1 + 1009f58: 14000136 bltu r2,r16,1009f60 <__udivdi3+0x120> + 1009f5c: 11012036 bltu r2,r4,100a3e0 <__udivdi3+0x5a0> + 1009f60: b004943a slli r2,r22,16 + 1009f64: d9000317 ldw r4,12(sp) + 1009f68: a084b03a or r2,r20,r2 + 1009f6c: 00001506 br 1009fc4 <__udivdi3+0x184> + 1009f70: 380d883a mov r6,r7 + 1009f74: 29c06236 bltu r5,r7,100a100 <__udivdi3+0x2c0> + 1009f78: 00bfffd4 movui r2,65535 + 1009f7c: 11c05a36 bltu r2,r7,100a0e8 <__udivdi3+0x2a8> + 1009f80: 00803fc4 movi r2,255 + 1009f84: 11c0fc36 bltu r2,r7,100a378 <__udivdi3+0x538> + 1009f88: 000b883a mov r5,zero + 1009f8c: 0005883a mov r2,zero + 1009f90: 3084d83a srl r2,r6,r2 + 1009f94: 010040b4 movhi r4,258 + 1009f98: 2123ee04 addi r4,r4,-28744 + 1009f9c: 01c00804 movi r7,32 + 1009fa0: 1105883a add r2,r2,r4 + 1009fa4: 10c00003 ldbu r3,0(r2) + 1009fa8: 28c7883a add r3,r5,r3 + 1009fac: 38efc83a sub r23,r7,r3 + 1009fb0: b800691e bne r23,zero,100a158 <__udivdi3+0x318> + 1009fb4: 35000136 bltu r6,r20,1009fbc <__udivdi3+0x17c> + 1009fb8: e4005136 bltu fp,r16,100a100 <__udivdi3+0x2c0> + 1009fbc: 00800044 movi r2,1 + 1009fc0: 0009883a mov r4,zero + 1009fc4: 2007883a mov r3,r4 + 1009fc8: dfc00f17 ldw ra,60(sp) + 1009fcc: df000e17 ldw fp,56(sp) + 1009fd0: ddc00d17 ldw r23,52(sp) + 1009fd4: dd800c17 ldw r22,48(sp) + 1009fd8: dd400b17 ldw r21,44(sp) + 1009fdc: dd000a17 ldw r20,40(sp) + 1009fe0: dcc00917 ldw r19,36(sp) + 1009fe4: dc800817 ldw r18,32(sp) + 1009fe8: dc400717 ldw r17,28(sp) + 1009fec: dc000617 ldw r16,24(sp) + 1009ff0: dec01004 addi sp,sp,64 + 1009ff4: f800283a ret + 1009ff8: 00bfffd4 movui r2,65535 + 1009ffc: 12005036 bltu r2,r8,100a140 <__udivdi3+0x300> + 100a000: 00803fc4 movi r2,255 + 100a004: 1200e836 bltu r2,r8,100a3a8 <__udivdi3+0x568> + 100a008: 000b883a mov r5,zero + 100a00c: 0005883a mov r2,zero + 100a010: 8084d83a srl r2,r16,r2 + 100a014: 010040b4 movhi r4,258 + 100a018: 2123ee04 addi r4,r4,-28744 + 100a01c: 01800804 movi r6,32 + 100a020: 1105883a add r2,r2,r4 + 100a024: 10c00003 ldbu r3,0(r2) + 100a028: 28c7883a add r3,r5,r3 + 100a02c: 30cbc83a sub r5,r6,r3 + 100a030: 28000626 beq r5,zero,100a04c <__udivdi3+0x20c> + 100a034: 3145c83a sub r2,r6,r5 + 100a038: e084d83a srl r2,fp,r2 + 100a03c: a146983a sll r3,r20,r5 + 100a040: e178983a sll fp,fp,r5 + 100a044: 8160983a sll r16,r16,r5 + 100a048: 18a8b03a or r20,r3,r2 + 100a04c: 802ad43a srli r21,r16,16 + 100a050: a009883a mov r4,r20 + 100a054: 85ffffcc andi r23,r16,65535 + 100a058: a80b883a mov r5,r21 + 100a05c: 100bc340 call 100bc34 <__udivsi3> + 100a060: a009883a mov r4,r20 + 100a064: a80b883a mov r5,r21 + 100a068: 102d883a mov r22,r2 + 100a06c: 100bc3c0 call 100bc3c <__umodsi3> + 100a070: 1004943a slli r2,r2,16 + 100a074: e006d43a srli r3,fp,16 + 100a078: bda3383a mul r17,r23,r22 + 100a07c: 10c4b03a or r2,r2,r3 + 100a080: 1440042e bgeu r2,r17,100a094 <__udivdi3+0x254> + 100a084: 1405883a add r2,r2,r16 + 100a088: b5bfffc4 addi r22,r22,-1 + 100a08c: 14000136 bltu r2,r16,100a094 <__udivdi3+0x254> + 100a090: 1440d536 bltu r2,r17,100a3e8 <__udivdi3+0x5a8> + 100a094: 1463c83a sub r17,r2,r17 + 100a098: 8809883a mov r4,r17 + 100a09c: a80b883a mov r5,r21 + 100a0a0: 100bc340 call 100bc34 <__udivsi3> + 100a0a4: 8809883a mov r4,r17 + 100a0a8: a80b883a mov r5,r21 + 100a0ac: 1029883a mov r20,r2 + 100a0b0: 100bc3c0 call 100bc3c <__umodsi3> + 100a0b4: 1004943a slli r2,r2,16 + 100a0b8: bd09383a mul r4,r23,r20 + 100a0bc: e0ffffcc andi r3,fp,65535 + 100a0c0: 10c4b03a or r2,r2,r3 + 100a0c4: 1100042e bgeu r2,r4,100a0d8 <__udivdi3+0x298> + 100a0c8: 8085883a add r2,r16,r2 + 100a0cc: a53fffc4 addi r20,r20,-1 + 100a0d0: 14000136 bltu r2,r16,100a0d8 <__udivdi3+0x298> + 100a0d4: 1100c736 bltu r2,r4,100a3f4 <__udivdi3+0x5b4> + 100a0d8: b004943a slli r2,r22,16 + 100a0dc: 0009883a mov r4,zero + 100a0e0: a084b03a or r2,r20,r2 + 100a0e4: 003fb706 br 1009fc4 <__udivdi3+0x184> + 100a0e8: 00804034 movhi r2,256 + 100a0ec: 10bfffc4 addi r2,r2,-1 + 100a0f0: 11c0a436 bltu r2,r7,100a384 <__udivdi3+0x544> + 100a0f4: 01400404 movi r5,16 + 100a0f8: 2805883a mov r2,r5 + 100a0fc: 003fa406 br 1009f90 <__udivdi3+0x150> + 100a100: 0005883a mov r2,zero + 100a104: 0009883a mov r4,zero + 100a108: 003fae06 br 1009fc4 <__udivdi3+0x184> + 100a10c: 00804034 movhi r2,256 + 100a110: 10bfffc4 addi r2,r2,-1 + 100a114: 1400a136 bltu r2,r16,100a39c <__udivdi3+0x55c> + 100a118: 01400404 movi r5,16 + 100a11c: 2805883a mov r2,r5 + 100a120: 003f6006 br 1009ea4 <__udivdi3+0x64> + 100a124: 01000044 movi r4,1 + 100a128: 000b883a mov r5,zero + 100a12c: 100bc340 call 100bc34 <__udivsi3> + 100a130: 1021883a mov r16,r2 + 100a134: 00bfffd4 movui r2,65535 + 100a138: 143ff436 bltu r2,r16,100a10c <__udivdi3+0x2cc> + 100a13c: 003f5506 br 1009e94 <__udivdi3+0x54> + 100a140: 00804034 movhi r2,256 + 100a144: 10bfffc4 addi r2,r2,-1 + 100a148: 12009a36 bltu r2,r8,100a3b4 <__udivdi3+0x574> + 100a14c: 01400404 movi r5,16 + 100a150: 2805883a mov r2,r5 + 100a154: 003fae06 br 100a010 <__udivdi3+0x1d0> + 100a158: 3dc5c83a sub r2,r7,r23 + 100a15c: 35c8983a sll r4,r6,r23 + 100a160: 8086d83a srl r3,r16,r2 + 100a164: a0a2d83a srl r17,r20,r2 + 100a168: e084d83a srl r2,fp,r2 + 100a16c: 20eab03a or r21,r4,r3 + 100a170: a82cd43a srli r22,r21,16 + 100a174: a5c6983a sll r3,r20,r23 + 100a178: 8809883a mov r4,r17 + 100a17c: b00b883a mov r5,r22 + 100a180: 1886b03a or r3,r3,r2 + 100a184: d8c00215 stw r3,8(sp) + 100a188: 100bc340 call 100bc34 <__udivsi3> + 100a18c: 8809883a mov r4,r17 + 100a190: b00b883a mov r5,r22 + 100a194: 1029883a mov r20,r2 + 100a198: 100bc3c0 call 100bc3c <__umodsi3> + 100a19c: a8ffffcc andi r3,r21,65535 + 100a1a0: d8c00515 stw r3,20(sp) + 100a1a4: d9000217 ldw r4,8(sp) + 100a1a8: d9400517 ldw r5,20(sp) + 100a1ac: 1004943a slli r2,r2,16 + 100a1b0: 2006d43a srli r3,r4,16 + 100a1b4: 85e0983a sll r16,r16,r23 + 100a1b8: 2d23383a mul r17,r5,r20 + 100a1bc: 10c4b03a or r2,r2,r3 + 100a1c0: dc000015 stw r16,0(sp) + 100a1c4: 1440032e bgeu r2,r17,100a1d4 <__udivdi3+0x394> + 100a1c8: 1545883a add r2,r2,r21 + 100a1cc: a53fffc4 addi r20,r20,-1 + 100a1d0: 15407f2e bgeu r2,r21,100a3d0 <__udivdi3+0x590> + 100a1d4: 1463c83a sub r17,r2,r17 + 100a1d8: 8809883a mov r4,r17 + 100a1dc: b00b883a mov r5,r22 + 100a1e0: 100bc340 call 100bc34 <__udivsi3> + 100a1e4: 8809883a mov r4,r17 + 100a1e8: b00b883a mov r5,r22 + 100a1ec: 1021883a mov r16,r2 + 100a1f0: 100bc3c0 call 100bc3c <__umodsi3> + 100a1f4: d8c00517 ldw r3,20(sp) + 100a1f8: d9000217 ldw r4,8(sp) + 100a1fc: 1004943a slli r2,r2,16 + 100a200: 1c0f383a mul r7,r3,r16 + 100a204: 20ffffcc andi r3,r4,65535 + 100a208: 10e2b03a or r17,r2,r3 + 100a20c: 89c0032e bgeu r17,r7,100a21c <__udivdi3+0x3dc> + 100a210: 8d63883a add r17,r17,r21 + 100a214: 843fffc4 addi r16,r16,-1 + 100a218: 8d40692e bgeu r17,r21,100a3c0 <__udivdi3+0x580> + 100a21c: a008943a slli r4,r20,16 + 100a220: d9400017 ldw r5,0(sp) + 100a224: 89e3c83a sub r17,r17,r7 + 100a228: 8110b03a or r8,r16,r4 + 100a22c: 280cd43a srli r6,r5,16 + 100a230: 28ffffcc andi r3,r5,65535 + 100a234: 40bfffcc andi r2,r8,65535 + 100a238: 400ad43a srli r5,r8,16 + 100a23c: 10d3383a mul r9,r2,r3 + 100a240: 1185383a mul r2,r2,r6 + 100a244: 28c7383a mul r3,r5,r3 + 100a248: 4808d43a srli r4,r9,16 + 100a24c: 298b383a mul r5,r5,r6 + 100a250: 10c5883a add r2,r2,r3 + 100a254: 2089883a add r4,r4,r2 + 100a258: 20c0022e bgeu r4,r3,100a264 <__udivdi3+0x424> + 100a25c: 00800074 movhi r2,1 + 100a260: 288b883a add r5,r5,r2 + 100a264: 2004d43a srli r2,r4,16 + 100a268: 288b883a add r5,r5,r2 + 100a26c: 89403f36 bltu r17,r5,100a36c <__udivdi3+0x52c> + 100a270: 89403926 beq r17,r5,100a358 <__udivdi3+0x518> + 100a274: 4005883a mov r2,r8 + 100a278: 0009883a mov r4,zero + 100a27c: 003f5106 br 1009fc4 <__udivdi3+0x184> + 100a280: 85a0983a sll r16,r16,r22 + 100a284: 3585c83a sub r2,r6,r22 + 100a288: a0a2d83a srl r17,r20,r2 + 100a28c: 802ad43a srli r21,r16,16 + 100a290: e084d83a srl r2,fp,r2 + 100a294: a586983a sll r3,r20,r22 + 100a298: 8809883a mov r4,r17 + 100a29c: a80b883a mov r5,r21 + 100a2a0: 1886b03a or r3,r3,r2 + 100a2a4: d8c00115 stw r3,4(sp) + 100a2a8: 100bc340 call 100bc34 <__udivsi3> + 100a2ac: 8809883a mov r4,r17 + 100a2b0: a80b883a mov r5,r21 + 100a2b4: d8800415 stw r2,16(sp) + 100a2b8: 100bc3c0 call 100bc3c <__umodsi3> + 100a2bc: d9000117 ldw r4,4(sp) + 100a2c0: d9400417 ldw r5,16(sp) + 100a2c4: 1004943a slli r2,r2,16 + 100a2c8: 85ffffcc andi r23,r16,65535 + 100a2cc: 2006d43a srli r3,r4,16 + 100a2d0: b963383a mul r17,r23,r5 + 100a2d4: 10c4b03a or r2,r2,r3 + 100a2d8: 1440042e bgeu r2,r17,100a2ec <__udivdi3+0x4ac> + 100a2dc: 297fffc4 addi r5,r5,-1 + 100a2e0: 1405883a add r2,r2,r16 + 100a2e4: d9400415 stw r5,16(sp) + 100a2e8: 1400442e bgeu r2,r16,100a3fc <__udivdi3+0x5bc> + 100a2ec: 1463c83a sub r17,r2,r17 + 100a2f0: 8809883a mov r4,r17 + 100a2f4: a80b883a mov r5,r21 + 100a2f8: 100bc340 call 100bc34 <__udivsi3> + 100a2fc: 8809883a mov r4,r17 + 100a300: a80b883a mov r5,r21 + 100a304: 1029883a mov r20,r2 + 100a308: 100bc3c0 call 100bc3c <__umodsi3> + 100a30c: d9400117 ldw r5,4(sp) + 100a310: 1004943a slli r2,r2,16 + 100a314: bd09383a mul r4,r23,r20 + 100a318: 28ffffcc andi r3,r5,65535 + 100a31c: 10c6b03a or r3,r2,r3 + 100a320: 1900062e bgeu r3,r4,100a33c <__udivdi3+0x4fc> + 100a324: 1c07883a add r3,r3,r16 + 100a328: a53fffc4 addi r20,r20,-1 + 100a32c: 1c000336 bltu r3,r16,100a33c <__udivdi3+0x4fc> + 100a330: 1900022e bgeu r3,r4,100a33c <__udivdi3+0x4fc> + 100a334: a53fffc4 addi r20,r20,-1 + 100a338: 1c07883a add r3,r3,r16 + 100a33c: d9400417 ldw r5,16(sp) + 100a340: e5b8983a sll fp,fp,r22 + 100a344: 1923c83a sub r17,r3,r4 + 100a348: 2804943a slli r2,r5,16 + 100a34c: a0a8b03a or r20,r20,r2 + 100a350: dd000315 stw r20,12(sp) + 100a354: 003ee106 br 1009edc <__udivdi3+0x9c> + 100a358: 2004943a slli r2,r4,16 + 100a35c: e5c8983a sll r4,fp,r23 + 100a360: 48ffffcc andi r3,r9,65535 + 100a364: 10c5883a add r2,r2,r3 + 100a368: 20bfc22e bgeu r4,r2,100a274 <__udivdi3+0x434> + 100a36c: 40bfffc4 addi r2,r8,-1 + 100a370: 0009883a mov r4,zero + 100a374: 003f1306 br 1009fc4 <__udivdi3+0x184> + 100a378: 01400204 movi r5,8 + 100a37c: 2805883a mov r2,r5 + 100a380: 003f0306 br 1009f90 <__udivdi3+0x150> + 100a384: 01400604 movi r5,24 + 100a388: 2805883a mov r2,r5 + 100a38c: 003f0006 br 1009f90 <__udivdi3+0x150> + 100a390: 01400204 movi r5,8 + 100a394: 2805883a mov r2,r5 + 100a398: 003ec206 br 1009ea4 <__udivdi3+0x64> + 100a39c: 01400604 movi r5,24 + 100a3a0: 2805883a mov r2,r5 + 100a3a4: 003ebf06 br 1009ea4 <__udivdi3+0x64> + 100a3a8: 01400204 movi r5,8 + 100a3ac: 2805883a mov r2,r5 + 100a3b0: 003f1706 br 100a010 <__udivdi3+0x1d0> + 100a3b4: 01400604 movi r5,24 + 100a3b8: 2805883a mov r2,r5 + 100a3bc: 003f1406 br 100a010 <__udivdi3+0x1d0> + 100a3c0: 89ff962e bgeu r17,r7,100a21c <__udivdi3+0x3dc> + 100a3c4: 8d63883a add r17,r17,r21 + 100a3c8: 843fffc4 addi r16,r16,-1 + 100a3cc: 003f9306 br 100a21c <__udivdi3+0x3dc> + 100a3d0: 147f802e bgeu r2,r17,100a1d4 <__udivdi3+0x394> + 100a3d4: a53fffc4 addi r20,r20,-1 + 100a3d8: 1545883a add r2,r2,r21 + 100a3dc: 003f7d06 br 100a1d4 <__udivdi3+0x394> + 100a3e0: a53fffc4 addi r20,r20,-1 + 100a3e4: 003ede06 br 1009f60 <__udivdi3+0x120> + 100a3e8: b5bfffc4 addi r22,r22,-1 + 100a3ec: 1405883a add r2,r2,r16 + 100a3f0: 003f2806 br 100a094 <__udivdi3+0x254> + 100a3f4: a53fffc4 addi r20,r20,-1 + 100a3f8: 003f3706 br 100a0d8 <__udivdi3+0x298> + 100a3fc: 147fbb2e bgeu r2,r17,100a2ec <__udivdi3+0x4ac> + 100a400: 297fffc4 addi r5,r5,-1 + 100a404: 1405883a add r2,r2,r16 + 100a408: d9400415 stw r5,16(sp) + 100a40c: 003fb706 br 100a2ec <__udivdi3+0x4ac> + 100a410: b5bfffc4 addi r22,r22,-1 + 100a414: 1405883a add r2,r2,r16 + 100a418: 003ec006 br 1009f1c <__udivdi3+0xdc> + +0100a41c <__umoddi3>: + 100a41c: defff104 addi sp,sp,-60 + 100a420: dd800b15 stw r22,44(sp) + 100a424: dd000915 stw r20,36(sp) + 100a428: dc000515 stw r16,20(sp) + 100a42c: dfc00e15 stw ra,56(sp) + 100a430: df000d15 stw fp,52(sp) + 100a434: ddc00c15 stw r23,48(sp) + 100a438: dd400a15 stw r21,40(sp) + 100a43c: dcc00815 stw r19,32(sp) + 100a440: dc800715 stw r18,28(sp) + 100a444: dc400615 stw r17,24(sp) + 100a448: 3021883a mov r16,r6 + 100a44c: 202d883a mov r22,r4 + 100a450: 2829883a mov r20,r5 + 100a454: 38002b1e bne r7,zero,100a504 <__umoddi3+0xe8> + 100a458: 29805036 bltu r5,r6,100a59c <__umoddi3+0x180> + 100a45c: 30008a26 beq r6,zero,100a688 <__umoddi3+0x26c> + 100a460: 00bfffd4 movui r2,65535 + 100a464: 14008236 bltu r2,r16,100a670 <__umoddi3+0x254> + 100a468: 00803fc4 movi r2,255 + 100a46c: 14013636 bltu r2,r16,100a948 <__umoddi3+0x52c> + 100a470: 000b883a mov r5,zero + 100a474: 0005883a mov r2,zero + 100a478: 8084d83a srl r2,r16,r2 + 100a47c: 010040b4 movhi r4,258 + 100a480: 2123ee04 addi r4,r4,-28744 + 100a484: 01800804 movi r6,32 + 100a488: 1105883a add r2,r2,r4 + 100a48c: 10c00003 ldbu r3,0(r2) + 100a490: 28c7883a add r3,r5,r3 + 100a494: 30efc83a sub r23,r6,r3 + 100a498: b800941e bne r23,zero,100a6ec <__umoddi3+0x2d0> + 100a49c: 802ad43a srli r21,r16,16 + 100a4a0: a423c83a sub r17,r20,r16 + 100a4a4: 0039883a mov fp,zero + 100a4a8: 853fffcc andi r20,r16,65535 + 100a4ac: 8809883a mov r4,r17 + 100a4b0: a80b883a mov r5,r21 + 100a4b4: 100bc340 call 100bc34 <__udivsi3> + 100a4b8: 8809883a mov r4,r17 + 100a4bc: a80b883a mov r5,r21 + 100a4c0: a0a3383a mul r17,r20,r2 + 100a4c4: 100bc3c0 call 100bc3c <__umodsi3> + 100a4c8: 1004943a slli r2,r2,16 + 100a4cc: b006d43a srli r3,r22,16 + 100a4d0: 10c4b03a or r2,r2,r3 + 100a4d4: 1440032e bgeu r2,r17,100a4e4 <__umoddi3+0xc8> + 100a4d8: 1405883a add r2,r2,r16 + 100a4dc: 14000136 bltu r2,r16,100a4e4 <__umoddi3+0xc8> + 100a4e0: 14413536 bltu r2,r17,100a9b8 <__umoddi3+0x59c> + 100a4e4: 1463c83a sub r17,r2,r17 + 100a4e8: 8809883a mov r4,r17 + 100a4ec: a80b883a mov r5,r21 + 100a4f0: 100bc340 call 100bc34 <__udivsi3> + 100a4f4: 8809883a mov r4,r17 + 100a4f8: a0a3383a mul r17,r20,r2 + 100a4fc: a80b883a mov r5,r21 + 100a500: 00004d06 br 100a638 <__umoddi3+0x21c> + 100a504: 380d883a mov r6,r7 + 100a508: 29c0102e bgeu r5,r7,100a54c <__umoddi3+0x130> + 100a50c: 2011883a mov r8,r4 + 100a510: 2813883a mov r9,r5 + 100a514: 4005883a mov r2,r8 + 100a518: 4807883a mov r3,r9 + 100a51c: dfc00e17 ldw ra,56(sp) + 100a520: df000d17 ldw fp,52(sp) + 100a524: ddc00c17 ldw r23,48(sp) + 100a528: dd800b17 ldw r22,44(sp) + 100a52c: dd400a17 ldw r21,40(sp) + 100a530: dd000917 ldw r20,36(sp) + 100a534: dcc00817 ldw r19,32(sp) + 100a538: dc800717 ldw r18,28(sp) + 100a53c: dc400617 ldw r17,24(sp) + 100a540: dc000517 ldw r16,20(sp) + 100a544: dec00f04 addi sp,sp,60 + 100a548: f800283a ret + 100a54c: 00bfffd4 movui r2,65535 + 100a550: 11c05a36 bltu r2,r7,100a6bc <__umoddi3+0x2a0> + 100a554: 00803fc4 movi r2,255 + 100a558: 11c0fe36 bltu r2,r7,100a954 <__umoddi3+0x538> + 100a55c: 000b883a mov r5,zero + 100a560: 0005883a mov r2,zero + 100a564: 3084d83a srl r2,r6,r2 + 100a568: 010040b4 movhi r4,258 + 100a56c: 2123ee04 addi r4,r4,-28744 + 100a570: 01c00804 movi r7,32 + 100a574: 1105883a add r2,r2,r4 + 100a578: 10c00003 ldbu r3,0(r2) + 100a57c: 28c7883a add r3,r5,r3 + 100a580: 38ebc83a sub r21,r7,r3 + 100a584: a800851e bne r21,zero,100a79c <__umoddi3+0x380> + 100a588: 35005236 bltu r6,r20,100a6d4 <__umoddi3+0x2b8> + 100a58c: b400512e bgeu r22,r16,100a6d4 <__umoddi3+0x2b8> + 100a590: b011883a mov r8,r22 + 100a594: a013883a mov r9,r20 + 100a598: 003fde06 br 100a514 <__umoddi3+0xf8> + 100a59c: 00bfffd4 movui r2,65535 + 100a5a0: 11804036 bltu r2,r6,100a6a4 <__umoddi3+0x288> + 100a5a4: 00803fc4 movi r2,255 + 100a5a8: 1180ed36 bltu r2,r6,100a960 <__umoddi3+0x544> + 100a5ac: 000b883a mov r5,zero + 100a5b0: 0005883a mov r2,zero + 100a5b4: 8084d83a srl r2,r16,r2 + 100a5b8: 010040b4 movhi r4,258 + 100a5bc: 2123ee04 addi r4,r4,-28744 + 100a5c0: 01800804 movi r6,32 + 100a5c4: 1105883a add r2,r2,r4 + 100a5c8: 10c00003 ldbu r3,0(r2) + 100a5cc: 28c7883a add r3,r5,r3 + 100a5d0: 30c7c83a sub r3,r6,r3 + 100a5d4: 1800bf1e bne r3,zero,100a8d4 <__umoddi3+0x4b8> + 100a5d8: 0039883a mov fp,zero + 100a5dc: 802ad43a srli r21,r16,16 + 100a5e0: a009883a mov r4,r20 + 100a5e4: 85ffffcc andi r23,r16,65535 + 100a5e8: a80b883a mov r5,r21 + 100a5ec: 100bc340 call 100bc34 <__udivsi3> + 100a5f0: a009883a mov r4,r20 + 100a5f4: a80b883a mov r5,r21 + 100a5f8: b8a3383a mul r17,r23,r2 + 100a5fc: 100bc3c0 call 100bc3c <__umodsi3> + 100a600: 1004943a slli r2,r2,16 + 100a604: b006d43a srli r3,r22,16 + 100a608: 10c4b03a or r2,r2,r3 + 100a60c: 1440032e bgeu r2,r17,100a61c <__umoddi3+0x200> + 100a610: 1405883a add r2,r2,r16 + 100a614: 14000136 bltu r2,r16,100a61c <__umoddi3+0x200> + 100a618: 1440e536 bltu r2,r17,100a9b0 <__umoddi3+0x594> + 100a61c: 1463c83a sub r17,r2,r17 + 100a620: 8809883a mov r4,r17 + 100a624: a80b883a mov r5,r21 + 100a628: 100bc340 call 100bc34 <__udivsi3> + 100a62c: 8809883a mov r4,r17 + 100a630: b8a3383a mul r17,r23,r2 + 100a634: a80b883a mov r5,r21 + 100a638: 100bc3c0 call 100bc3c <__umodsi3> + 100a63c: 1004943a slli r2,r2,16 + 100a640: b0ffffcc andi r3,r22,65535 + 100a644: 10c4b03a or r2,r2,r3 + 100a648: 1440042e bgeu r2,r17,100a65c <__umoddi3+0x240> + 100a64c: 1405883a add r2,r2,r16 + 100a650: 14000236 bltu r2,r16,100a65c <__umoddi3+0x240> + 100a654: 1440012e bgeu r2,r17,100a65c <__umoddi3+0x240> + 100a658: 1405883a add r2,r2,r16 + 100a65c: 1445c83a sub r2,r2,r17 + 100a660: 1724d83a srl r18,r2,fp + 100a664: 0013883a mov r9,zero + 100a668: 9011883a mov r8,r18 + 100a66c: 003fa906 br 100a514 <__umoddi3+0xf8> + 100a670: 00804034 movhi r2,256 + 100a674: 10bfffc4 addi r2,r2,-1 + 100a678: 1400b036 bltu r2,r16,100a93c <__umoddi3+0x520> + 100a67c: 01400404 movi r5,16 + 100a680: 2805883a mov r2,r5 + 100a684: 003f7c06 br 100a478 <__umoddi3+0x5c> + 100a688: 01000044 movi r4,1 + 100a68c: 000b883a mov r5,zero + 100a690: 100bc340 call 100bc34 <__udivsi3> + 100a694: 1021883a mov r16,r2 + 100a698: 00bfffd4 movui r2,65535 + 100a69c: 143ff436 bltu r2,r16,100a670 <__umoddi3+0x254> + 100a6a0: 003f7106 br 100a468 <__umoddi3+0x4c> + 100a6a4: 00804034 movhi r2,256 + 100a6a8: 10bfffc4 addi r2,r2,-1 + 100a6ac: 1180af36 bltu r2,r6,100a96c <__umoddi3+0x550> + 100a6b0: 01400404 movi r5,16 + 100a6b4: 2805883a mov r2,r5 + 100a6b8: 003fbe06 br 100a5b4 <__umoddi3+0x198> + 100a6bc: 00804034 movhi r2,256 + 100a6c0: 10bfffc4 addi r2,r2,-1 + 100a6c4: 11c0ac36 bltu r2,r7,100a978 <__umoddi3+0x55c> + 100a6c8: 01400404 movi r5,16 + 100a6cc: 2805883a mov r2,r5 + 100a6d0: 003fa406 br 100a564 <__umoddi3+0x148> + 100a6d4: b409c83a sub r4,r22,r16 + 100a6d8: b105803a cmpltu r2,r22,r4 + 100a6dc: a187c83a sub r3,r20,r6 + 100a6e0: 18a9c83a sub r20,r3,r2 + 100a6e4: 202d883a mov r22,r4 + 100a6e8: 003fa906 br 100a590 <__umoddi3+0x174> + 100a6ec: 85e0983a sll r16,r16,r23 + 100a6f0: 35c5c83a sub r2,r6,r23 + 100a6f4: a0a2d83a srl r17,r20,r2 + 100a6f8: 802ad43a srli r21,r16,16 + 100a6fc: b084d83a srl r2,r22,r2 + 100a700: a5c6983a sll r3,r20,r23 + 100a704: 8809883a mov r4,r17 + 100a708: a80b883a mov r5,r21 + 100a70c: 1886b03a or r3,r3,r2 + 100a710: d8c00115 stw r3,4(sp) + 100a714: 853fffcc andi r20,r16,65535 + 100a718: 100bc340 call 100bc34 <__udivsi3> + 100a71c: 8809883a mov r4,r17 + 100a720: a80b883a mov r5,r21 + 100a724: a0a3383a mul r17,r20,r2 + 100a728: 100bc3c0 call 100bc3c <__umodsi3> + 100a72c: d9000117 ldw r4,4(sp) + 100a730: 1004943a slli r2,r2,16 + 100a734: b839883a mov fp,r23 + 100a738: 2006d43a srli r3,r4,16 + 100a73c: 10c4b03a or r2,r2,r3 + 100a740: 1440022e bgeu r2,r17,100a74c <__umoddi3+0x330> + 100a744: 1405883a add r2,r2,r16 + 100a748: 1400962e bgeu r2,r16,100a9a4 <__umoddi3+0x588> + 100a74c: 1463c83a sub r17,r2,r17 + 100a750: 8809883a mov r4,r17 + 100a754: a80b883a mov r5,r21 + 100a758: 100bc340 call 100bc34 <__udivsi3> + 100a75c: 8809883a mov r4,r17 + 100a760: a80b883a mov r5,r21 + 100a764: a0a3383a mul r17,r20,r2 + 100a768: 100bc3c0 call 100bc3c <__umodsi3> + 100a76c: d9400117 ldw r5,4(sp) + 100a770: 1004943a slli r2,r2,16 + 100a774: 28ffffcc andi r3,r5,65535 + 100a778: 10c4b03a or r2,r2,r3 + 100a77c: 1440042e bgeu r2,r17,100a790 <__umoddi3+0x374> + 100a780: 1405883a add r2,r2,r16 + 100a784: 14000236 bltu r2,r16,100a790 <__umoddi3+0x374> + 100a788: 1440012e bgeu r2,r17,100a790 <__umoddi3+0x374> + 100a78c: 1405883a add r2,r2,r16 + 100a790: b5ec983a sll r22,r22,r23 + 100a794: 1463c83a sub r17,r2,r17 + 100a798: 003f4406 br 100a4ac <__umoddi3+0x90> + 100a79c: 3d4fc83a sub r7,r7,r21 + 100a7a0: 3546983a sll r3,r6,r21 + 100a7a4: 81c4d83a srl r2,r16,r7 + 100a7a8: a1e2d83a srl r17,r20,r7 + 100a7ac: a54c983a sll r6,r20,r21 + 100a7b0: 18aeb03a or r23,r3,r2 + 100a7b4: b828d43a srli r20,r23,16 + 100a7b8: b1c4d83a srl r2,r22,r7 + 100a7bc: 8809883a mov r4,r17 + 100a7c0: a00b883a mov r5,r20 + 100a7c4: 308cb03a or r6,r6,r2 + 100a7c8: d9c00315 stw r7,12(sp) + 100a7cc: d9800215 stw r6,8(sp) + 100a7d0: 100bc340 call 100bc34 <__udivsi3> + 100a7d4: 8809883a mov r4,r17 + 100a7d8: a00b883a mov r5,r20 + 100a7dc: 1039883a mov fp,r2 + 100a7e0: 100bc3c0 call 100bc3c <__umodsi3> + 100a7e4: b8ffffcc andi r3,r23,65535 + 100a7e8: d8c00415 stw r3,16(sp) + 100a7ec: d9000217 ldw r4,8(sp) + 100a7f0: d9400417 ldw r5,16(sp) + 100a7f4: 1004943a slli r2,r2,16 + 100a7f8: 2006d43a srli r3,r4,16 + 100a7fc: 8560983a sll r16,r16,r21 + 100a800: 2f23383a mul r17,r5,fp + 100a804: 10c4b03a or r2,r2,r3 + 100a808: dc000015 stw r16,0(sp) + 100a80c: b56c983a sll r22,r22,r21 + 100a810: 1440032e bgeu r2,r17,100a820 <__umoddi3+0x404> + 100a814: 15c5883a add r2,r2,r23 + 100a818: e73fffc4 addi fp,fp,-1 + 100a81c: 15c05d2e bgeu r2,r23,100a994 <__umoddi3+0x578> + 100a820: 1463c83a sub r17,r2,r17 + 100a824: 8809883a mov r4,r17 + 100a828: a00b883a mov r5,r20 + 100a82c: 100bc340 call 100bc34 <__udivsi3> + 100a830: 8809883a mov r4,r17 + 100a834: a00b883a mov r5,r20 + 100a838: 1021883a mov r16,r2 + 100a83c: 100bc3c0 call 100bc3c <__umodsi3> + 100a840: d8c00417 ldw r3,16(sp) + 100a844: d9000217 ldw r4,8(sp) + 100a848: 1004943a slli r2,r2,16 + 100a84c: 1c23383a mul r17,r3,r16 + 100a850: 20ffffcc andi r3,r4,65535 + 100a854: 10ceb03a or r7,r2,r3 + 100a858: 3c40032e bgeu r7,r17,100a868 <__umoddi3+0x44c> + 100a85c: 3dcf883a add r7,r7,r23 + 100a860: 843fffc4 addi r16,r16,-1 + 100a864: 3dc0472e bgeu r7,r23,100a984 <__umoddi3+0x568> + 100a868: e004943a slli r2,fp,16 + 100a86c: d9400017 ldw r5,0(sp) + 100a870: 3c4fc83a sub r7,r7,r17 + 100a874: 8084b03a or r2,r16,r2 + 100a878: 28ffffcc andi r3,r5,65535 + 100a87c: 280cd43a srli r6,r5,16 + 100a880: 100ad43a srli r5,r2,16 + 100a884: 10bfffcc andi r2,r2,65535 + 100a888: 10d1383a mul r8,r2,r3 + 100a88c: 28c7383a mul r3,r5,r3 + 100a890: 1185383a mul r2,r2,r6 + 100a894: 4008d43a srli r4,r8,16 + 100a898: 298b383a mul r5,r5,r6 + 100a89c: 10c5883a add r2,r2,r3 + 100a8a0: 2089883a add r4,r4,r2 + 100a8a4: 20c0022e bgeu r4,r3,100a8b0 <__umoddi3+0x494> + 100a8a8: 00800074 movhi r2,1 + 100a8ac: 288b883a add r5,r5,r2 + 100a8b0: 2004d43a srli r2,r4,16 + 100a8b4: 2008943a slli r4,r4,16 + 100a8b8: 40ffffcc andi r3,r8,65535 + 100a8bc: 288b883a add r5,r5,r2 + 100a8c0: 20c9883a add r4,r4,r3 + 100a8c4: 39400b36 bltu r7,r5,100a8f4 <__umoddi3+0x4d8> + 100a8c8: 39403d26 beq r7,r5,100a9c0 <__umoddi3+0x5a4> + 100a8cc: 394bc83a sub r5,r7,r5 + 100a8d0: 00000f06 br 100a910 <__umoddi3+0x4f4> + 100a8d4: 30c5c83a sub r2,r6,r3 + 100a8d8: 1839883a mov fp,r3 + 100a8dc: b084d83a srl r2,r22,r2 + 100a8e0: a0c6983a sll r3,r20,r3 + 100a8e4: 8720983a sll r16,r16,fp + 100a8e8: b72c983a sll r22,r22,fp + 100a8ec: 18a8b03a or r20,r3,r2 + 100a8f0: 003f3a06 br 100a5dc <__umoddi3+0x1c0> + 100a8f4: d8c00017 ldw r3,0(sp) + 100a8f8: 20c5c83a sub r2,r4,r3 + 100a8fc: 2089803a cmpltu r4,r4,r2 + 100a900: 2dc7c83a sub r3,r5,r23 + 100a904: 1907c83a sub r3,r3,r4 + 100a908: 38cbc83a sub r5,r7,r3 + 100a90c: 1009883a mov r4,r2 + 100a910: b105c83a sub r2,r22,r4 + 100a914: b087803a cmpltu r3,r22,r2 + 100a918: 28c7c83a sub r3,r5,r3 + 100a91c: d9400317 ldw r5,12(sp) + 100a920: 1544d83a srl r2,r2,r21 + 100a924: 1948983a sll r4,r3,r5 + 100a928: 1d46d83a srl r3,r3,r21 + 100a92c: 20a4b03a or r18,r4,r2 + 100a930: 9011883a mov r8,r18 + 100a934: 1813883a mov r9,r3 + 100a938: 003ef606 br 100a514 <__umoddi3+0xf8> + 100a93c: 01400604 movi r5,24 + 100a940: 2805883a mov r2,r5 + 100a944: 003ecc06 br 100a478 <__umoddi3+0x5c> + 100a948: 01400204 movi r5,8 + 100a94c: 2805883a mov r2,r5 + 100a950: 003ec906 br 100a478 <__umoddi3+0x5c> + 100a954: 01400204 movi r5,8 + 100a958: 2805883a mov r2,r5 + 100a95c: 003f0106 br 100a564 <__umoddi3+0x148> + 100a960: 01400204 movi r5,8 + 100a964: 2805883a mov r2,r5 + 100a968: 003f1206 br 100a5b4 <__umoddi3+0x198> + 100a96c: 01400604 movi r5,24 + 100a970: 2805883a mov r2,r5 + 100a974: 003f0f06 br 100a5b4 <__umoddi3+0x198> + 100a978: 01400604 movi r5,24 + 100a97c: 2805883a mov r2,r5 + 100a980: 003ef806 br 100a564 <__umoddi3+0x148> + 100a984: 3c7fb82e bgeu r7,r17,100a868 <__umoddi3+0x44c> + 100a988: 843fffc4 addi r16,r16,-1 + 100a98c: 3dcf883a add r7,r7,r23 + 100a990: 003fb506 br 100a868 <__umoddi3+0x44c> + 100a994: 147fa22e bgeu r2,r17,100a820 <__umoddi3+0x404> + 100a998: e73fffc4 addi fp,fp,-1 + 100a99c: 15c5883a add r2,r2,r23 + 100a9a0: 003f9f06 br 100a820 <__umoddi3+0x404> + 100a9a4: 147f692e bgeu r2,r17,100a74c <__umoddi3+0x330> + 100a9a8: 1405883a add r2,r2,r16 + 100a9ac: 003f6706 br 100a74c <__umoddi3+0x330> + 100a9b0: 1405883a add r2,r2,r16 + 100a9b4: 003f1906 br 100a61c <__umoddi3+0x200> + 100a9b8: 1405883a add r2,r2,r16 + 100a9bc: 003ec906 br 100a4e4 <__umoddi3+0xc8> + 100a9c0: b13fcc36 bltu r22,r4,100a8f4 <__umoddi3+0x4d8> + 100a9c4: 000b883a mov r5,zero + 100a9c8: 003fd106 br 100a910 <__umoddi3+0x4f4> + +0100a9cc <_fpadd_parts>: + 100a9cc: defff804 addi sp,sp,-32 + 100a9d0: dcc00315 stw r19,12(sp) + 100a9d4: 2027883a mov r19,r4 + 100a9d8: 21000017 ldw r4,0(r4) + 100a9dc: 00c00044 movi r3,1 + 100a9e0: dd400515 stw r21,20(sp) + 100a9e4: dd000415 stw r20,16(sp) + 100a9e8: ddc00715 stw r23,28(sp) + 100a9ec: dd800615 stw r22,24(sp) + 100a9f0: dc800215 stw r18,8(sp) + 100a9f4: dc400115 stw r17,4(sp) + 100a9f8: dc000015 stw r16,0(sp) + 100a9fc: 282b883a mov r21,r5 + 100aa00: 3029883a mov r20,r6 + 100aa04: 1900632e bgeu r3,r4,100ab94 <_fpadd_parts+0x1c8> + 100aa08: 28800017 ldw r2,0(r5) + 100aa0c: 1880812e bgeu r3,r2,100ac14 <_fpadd_parts+0x248> + 100aa10: 00c00104 movi r3,4 + 100aa14: 20c0dc26 beq r4,r3,100ad88 <_fpadd_parts+0x3bc> + 100aa18: 10c07e26 beq r2,r3,100ac14 <_fpadd_parts+0x248> + 100aa1c: 00c00084 movi r3,2 + 100aa20: 10c06726 beq r2,r3,100abc0 <_fpadd_parts+0x1f4> + 100aa24: 20c07b26 beq r4,r3,100ac14 <_fpadd_parts+0x248> + 100aa28: 9dc00217 ldw r23,8(r19) + 100aa2c: 28c00217 ldw r3,8(r5) + 100aa30: 9c400317 ldw r17,12(r19) + 100aa34: 2bc00317 ldw r15,12(r5) + 100aa38: b8cdc83a sub r6,r23,r3 + 100aa3c: 9c800417 ldw r18,16(r19) + 100aa40: 2c000417 ldw r16,16(r5) + 100aa44: 3009883a mov r4,r6 + 100aa48: 30009716 blt r6,zero,100aca8 <_fpadd_parts+0x2dc> + 100aa4c: 00800fc4 movi r2,63 + 100aa50: 11806b16 blt r2,r6,100ac00 <_fpadd_parts+0x234> + 100aa54: 0100a40e bge zero,r4,100ace8 <_fpadd_parts+0x31c> + 100aa58: 35bff804 addi r22,r6,-32 + 100aa5c: b000bc16 blt r22,zero,100ad50 <_fpadd_parts+0x384> + 100aa60: 8596d83a srl r11,r16,r22 + 100aa64: 0019883a mov r12,zero + 100aa68: 0013883a mov r9,zero + 100aa6c: 01000044 movi r4,1 + 100aa70: 0015883a mov r10,zero + 100aa74: b000be16 blt r22,zero,100ad70 <_fpadd_parts+0x3a4> + 100aa78: 2590983a sll r8,r4,r22 + 100aa7c: 000f883a mov r7,zero + 100aa80: 00bfffc4 movi r2,-1 + 100aa84: 3889883a add r4,r7,r2 + 100aa88: 408b883a add r5,r8,r2 + 100aa8c: 21cd803a cmpltu r6,r4,r7 + 100aa90: 314b883a add r5,r6,r5 + 100aa94: 7904703a and r2,r15,r4 + 100aa98: 8146703a and r3,r16,r5 + 100aa9c: 10c4b03a or r2,r2,r3 + 100aaa0: 10000226 beq r2,zero,100aaac <_fpadd_parts+0xe0> + 100aaa4: 02400044 movi r9,1 + 100aaa8: 0015883a mov r10,zero + 100aaac: 5a5eb03a or r15,r11,r9 + 100aab0: 62a0b03a or r16,r12,r10 + 100aab4: 99400117 ldw r5,4(r19) + 100aab8: a8800117 ldw r2,4(r21) + 100aabc: 28806e26 beq r5,r2,100ac78 <_fpadd_parts+0x2ac> + 100aac0: 28006626 beq r5,zero,100ac5c <_fpadd_parts+0x290> + 100aac4: 7c45c83a sub r2,r15,r17 + 100aac8: 7889803a cmpltu r4,r15,r2 + 100aacc: 8487c83a sub r3,r16,r18 + 100aad0: 1909c83a sub r4,r3,r4 + 100aad4: 100d883a mov r6,r2 + 100aad8: 200f883a mov r7,r4 + 100aadc: 38007716 blt r7,zero,100acbc <_fpadd_parts+0x2f0> + 100aae0: a5c00215 stw r23,8(r20) + 100aae4: a1c00415 stw r7,16(r20) + 100aae8: a0000115 stw zero,4(r20) + 100aaec: a1800315 stw r6,12(r20) + 100aaf0: a2000317 ldw r8,12(r20) + 100aaf4: a2400417 ldw r9,16(r20) + 100aaf8: 00bfffc4 movi r2,-1 + 100aafc: 408b883a add r5,r8,r2 + 100ab00: 2a09803a cmpltu r4,r5,r8 + 100ab04: 488d883a add r6,r9,r2 + 100ab08: 01c40034 movhi r7,4096 + 100ab0c: 39ffffc4 addi r7,r7,-1 + 100ab10: 218d883a add r6,r4,r6 + 100ab14: 39801736 bltu r7,r6,100ab74 <_fpadd_parts+0x1a8> + 100ab18: 31c06526 beq r6,r7,100acb0 <_fpadd_parts+0x2e4> + 100ab1c: a3000217 ldw r12,8(r20) + 100ab20: 4209883a add r4,r8,r8 + 100ab24: 00bfffc4 movi r2,-1 + 100ab28: 220f803a cmpltu r7,r4,r8 + 100ab2c: 4a4b883a add r5,r9,r9 + 100ab30: 394f883a add r7,r7,r5 + 100ab34: 2095883a add r10,r4,r2 + 100ab38: 3897883a add r11,r7,r2 + 100ab3c: 510d803a cmpltu r6,r10,r4 + 100ab40: 6099883a add r12,r12,r2 + 100ab44: 32d7883a add r11,r6,r11 + 100ab48: 00840034 movhi r2,4096 + 100ab4c: 10bfffc4 addi r2,r2,-1 + 100ab50: 2011883a mov r8,r4 + 100ab54: 3813883a mov r9,r7 + 100ab58: a1000315 stw r4,12(r20) + 100ab5c: a1c00415 stw r7,16(r20) + 100ab60: a3000215 stw r12,8(r20) + 100ab64: 12c00336 bltu r2,r11,100ab74 <_fpadd_parts+0x1a8> + 100ab68: 58bfed1e bne r11,r2,100ab20 <_fpadd_parts+0x154> + 100ab6c: 00bfff84 movi r2,-2 + 100ab70: 12bfeb2e bgeu r2,r10,100ab20 <_fpadd_parts+0x154> + 100ab74: a2800417 ldw r10,16(r20) + 100ab78: 008000c4 movi r2,3 + 100ab7c: 00c80034 movhi r3,8192 + 100ab80: 18ffffc4 addi r3,r3,-1 + 100ab84: a2400317 ldw r9,12(r20) + 100ab88: a0800015 stw r2,0(r20) + 100ab8c: 1a802336 bltu r3,r10,100ac1c <_fpadd_parts+0x250> + 100ab90: a027883a mov r19,r20 + 100ab94: 9805883a mov r2,r19 + 100ab98: ddc00717 ldw r23,28(sp) + 100ab9c: dd800617 ldw r22,24(sp) + 100aba0: dd400517 ldw r21,20(sp) + 100aba4: dd000417 ldw r20,16(sp) + 100aba8: dcc00317 ldw r19,12(sp) + 100abac: dc800217 ldw r18,8(sp) + 100abb0: dc400117 ldw r17,4(sp) + 100abb4: dc000017 ldw r16,0(sp) + 100abb8: dec00804 addi sp,sp,32 + 100abbc: f800283a ret + 100abc0: 20fff41e bne r4,r3,100ab94 <_fpadd_parts+0x1c8> + 100abc4: 31000015 stw r4,0(r6) + 100abc8: 98800117 ldw r2,4(r19) + 100abcc: 30800115 stw r2,4(r6) + 100abd0: 98c00217 ldw r3,8(r19) + 100abd4: 30c00215 stw r3,8(r6) + 100abd8: 98800317 ldw r2,12(r19) + 100abdc: 30800315 stw r2,12(r6) + 100abe0: 98c00417 ldw r3,16(r19) + 100abe4: 30c00415 stw r3,16(r6) + 100abe8: 98800117 ldw r2,4(r19) + 100abec: 28c00117 ldw r3,4(r5) + 100abf0: 3027883a mov r19,r6 + 100abf4: 10c4703a and r2,r2,r3 + 100abf8: 30800115 stw r2,4(r6) + 100abfc: 003fe506 br 100ab94 <_fpadd_parts+0x1c8> + 100ac00: 1dc02616 blt r3,r23,100ac9c <_fpadd_parts+0x2d0> + 100ac04: 0023883a mov r17,zero + 100ac08: 182f883a mov r23,r3 + 100ac0c: 0025883a mov r18,zero + 100ac10: 003fa806 br 100aab4 <_fpadd_parts+0xe8> + 100ac14: a827883a mov r19,r21 + 100ac18: 003fde06 br 100ab94 <_fpadd_parts+0x1c8> + 100ac1c: 01800044 movi r6,1 + 100ac20: 500497fa slli r2,r10,31 + 100ac24: 4808d07a srli r4,r9,1 + 100ac28: 518ad83a srl r5,r10,r6 + 100ac2c: a2000217 ldw r8,8(r20) + 100ac30: 1108b03a or r4,r2,r4 + 100ac34: 0007883a mov r3,zero + 100ac38: 4984703a and r2,r9,r6 + 100ac3c: 208cb03a or r6,r4,r2 + 100ac40: 28ceb03a or r7,r5,r3 + 100ac44: 42000044 addi r8,r8,1 + 100ac48: a027883a mov r19,r20 + 100ac4c: a1c00415 stw r7,16(r20) + 100ac50: a2000215 stw r8,8(r20) + 100ac54: a1800315 stw r6,12(r20) + 100ac58: 003fce06 br 100ab94 <_fpadd_parts+0x1c8> + 100ac5c: 8bc5c83a sub r2,r17,r15 + 100ac60: 8889803a cmpltu r4,r17,r2 + 100ac64: 9407c83a sub r3,r18,r16 + 100ac68: 1909c83a sub r4,r3,r4 + 100ac6c: 100d883a mov r6,r2 + 100ac70: 200f883a mov r7,r4 + 100ac74: 003f9906 br 100aadc <_fpadd_parts+0x110> + 100ac78: 7c45883a add r2,r15,r17 + 100ac7c: 13c9803a cmpltu r4,r2,r15 + 100ac80: 8487883a add r3,r16,r18 + 100ac84: 20c9883a add r4,r4,r3 + 100ac88: a1400115 stw r5,4(r20) + 100ac8c: a5c00215 stw r23,8(r20) + 100ac90: a0800315 stw r2,12(r20) + 100ac94: a1000415 stw r4,16(r20) + 100ac98: 003fb606 br 100ab74 <_fpadd_parts+0x1a8> + 100ac9c: 001f883a mov r15,zero + 100aca0: 0021883a mov r16,zero + 100aca4: 003f8306 br 100aab4 <_fpadd_parts+0xe8> + 100aca8: 018dc83a sub r6,zero,r6 + 100acac: 003f6706 br 100aa4c <_fpadd_parts+0x80> + 100acb0: 00bfff84 movi r2,-2 + 100acb4: 117faf36 bltu r2,r5,100ab74 <_fpadd_parts+0x1a8> + 100acb8: 003f9806 br 100ab1c <_fpadd_parts+0x150> + 100acbc: 0005883a mov r2,zero + 100acc0: 1189c83a sub r4,r2,r6 + 100acc4: 1105803a cmpltu r2,r2,r4 + 100acc8: 01cbc83a sub r5,zero,r7 + 100accc: 2885c83a sub r2,r5,r2 + 100acd0: 01800044 movi r6,1 + 100acd4: a1800115 stw r6,4(r20) + 100acd8: a5c00215 stw r23,8(r20) + 100acdc: a1000315 stw r4,12(r20) + 100ace0: a0800415 stw r2,16(r20) + 100ace4: 003f8206 br 100aaf0 <_fpadd_parts+0x124> + 100ace8: 203f7226 beq r4,zero,100aab4 <_fpadd_parts+0xe8> + 100acec: 35bff804 addi r22,r6,-32 + 100acf0: b9af883a add r23,r23,r6 + 100acf4: b0003116 blt r22,zero,100adbc <_fpadd_parts+0x3f0> + 100acf8: 959ad83a srl r13,r18,r22 + 100acfc: 001d883a mov r14,zero + 100ad00: 000f883a mov r7,zero + 100ad04: 01000044 movi r4,1 + 100ad08: 0011883a mov r8,zero + 100ad0c: b0002516 blt r22,zero,100ada4 <_fpadd_parts+0x3d8> + 100ad10: 2594983a sll r10,r4,r22 + 100ad14: 0013883a mov r9,zero + 100ad18: 00bfffc4 movi r2,-1 + 100ad1c: 4889883a add r4,r9,r2 + 100ad20: 508b883a add r5,r10,r2 + 100ad24: 224d803a cmpltu r6,r4,r9 + 100ad28: 314b883a add r5,r6,r5 + 100ad2c: 8904703a and r2,r17,r4 + 100ad30: 9146703a and r3,r18,r5 + 100ad34: 10c4b03a or r2,r2,r3 + 100ad38: 10000226 beq r2,zero,100ad44 <_fpadd_parts+0x378> + 100ad3c: 01c00044 movi r7,1 + 100ad40: 0011883a mov r8,zero + 100ad44: 69e2b03a or r17,r13,r7 + 100ad48: 7224b03a or r18,r14,r8 + 100ad4c: 003f5906 br 100aab4 <_fpadd_parts+0xe8> + 100ad50: 8407883a add r3,r16,r16 + 100ad54: 008007c4 movi r2,31 + 100ad58: 1185c83a sub r2,r2,r6 + 100ad5c: 1886983a sll r3,r3,r2 + 100ad60: 7996d83a srl r11,r15,r6 + 100ad64: 8198d83a srl r12,r16,r6 + 100ad68: 1ad6b03a or r11,r3,r11 + 100ad6c: 003f3e06 br 100aa68 <_fpadd_parts+0x9c> + 100ad70: 2006d07a srli r3,r4,1 + 100ad74: 008007c4 movi r2,31 + 100ad78: 1185c83a sub r2,r2,r6 + 100ad7c: 1890d83a srl r8,r3,r2 + 100ad80: 218e983a sll r7,r4,r6 + 100ad84: 003f3e06 br 100aa80 <_fpadd_parts+0xb4> + 100ad88: 113f821e bne r2,r4,100ab94 <_fpadd_parts+0x1c8> + 100ad8c: 28c00117 ldw r3,4(r5) + 100ad90: 98800117 ldw r2,4(r19) + 100ad94: 10ff7f26 beq r2,r3,100ab94 <_fpadd_parts+0x1c8> + 100ad98: 04c040b4 movhi r19,258 + 100ad9c: 9ce3e904 addi r19,r19,-28764 + 100ada0: 003f7c06 br 100ab94 <_fpadd_parts+0x1c8> + 100ada4: 2006d07a srli r3,r4,1 + 100ada8: 008007c4 movi r2,31 + 100adac: 1185c83a sub r2,r2,r6 + 100adb0: 1894d83a srl r10,r3,r2 + 100adb4: 2192983a sll r9,r4,r6 + 100adb8: 003fd706 br 100ad18 <_fpadd_parts+0x34c> + 100adbc: 9487883a add r3,r18,r18 + 100adc0: 008007c4 movi r2,31 + 100adc4: 1185c83a sub r2,r2,r6 + 100adc8: 1886983a sll r3,r3,r2 + 100adcc: 899ad83a srl r13,r17,r6 + 100add0: 919cd83a srl r14,r18,r6 + 100add4: 1b5ab03a or r13,r3,r13 + 100add8: 003fc906 br 100ad00 <_fpadd_parts+0x334> + +0100addc <__subdf3>: + 100addc: deffea04 addi sp,sp,-88 + 100ade0: dcc01415 stw r19,80(sp) + 100ade4: dcc00404 addi r19,sp,16 + 100ade8: 2011883a mov r8,r4 + 100adec: 2813883a mov r9,r5 + 100adf0: dc401315 stw r17,76(sp) + 100adf4: d809883a mov r4,sp + 100adf8: 980b883a mov r5,r19 + 100adfc: dc400904 addi r17,sp,36 + 100ae00: dfc01515 stw ra,84(sp) + 100ae04: da400115 stw r9,4(sp) + 100ae08: d9c00315 stw r7,12(sp) + 100ae0c: da000015 stw r8,0(sp) + 100ae10: d9800215 stw r6,8(sp) + 100ae14: 100c0700 call 100c070 <__unpack_d> + 100ae18: d9000204 addi r4,sp,8 + 100ae1c: 880b883a mov r5,r17 + 100ae20: 100c0700 call 100c070 <__unpack_d> + 100ae24: d8800a17 ldw r2,40(sp) + 100ae28: 880b883a mov r5,r17 + 100ae2c: 9809883a mov r4,r19 + 100ae30: d9800e04 addi r6,sp,56 + 100ae34: 1080005c xori r2,r2,1 + 100ae38: d8800a15 stw r2,40(sp) + 100ae3c: 100a9cc0 call 100a9cc <_fpadd_parts> + 100ae40: 1009883a mov r4,r2 + 100ae44: 100bd5c0 call 100bd5c <__pack_d> + 100ae48: dfc01517 ldw ra,84(sp) + 100ae4c: dcc01417 ldw r19,80(sp) + 100ae50: dc401317 ldw r17,76(sp) + 100ae54: dec01604 addi sp,sp,88 + 100ae58: f800283a ret + +0100ae5c <__adddf3>: + 100ae5c: deffea04 addi sp,sp,-88 + 100ae60: dcc01415 stw r19,80(sp) + 100ae64: dcc00404 addi r19,sp,16 + 100ae68: 2011883a mov r8,r4 + 100ae6c: 2813883a mov r9,r5 + 100ae70: dc401315 stw r17,76(sp) + 100ae74: d809883a mov r4,sp + 100ae78: 980b883a mov r5,r19 + 100ae7c: dc400904 addi r17,sp,36 + 100ae80: dfc01515 stw ra,84(sp) + 100ae84: da400115 stw r9,4(sp) + 100ae88: d9c00315 stw r7,12(sp) + 100ae8c: da000015 stw r8,0(sp) + 100ae90: d9800215 stw r6,8(sp) + 100ae94: 100c0700 call 100c070 <__unpack_d> + 100ae98: d9000204 addi r4,sp,8 + 100ae9c: 880b883a mov r5,r17 + 100aea0: 100c0700 call 100c070 <__unpack_d> + 100aea4: d9800e04 addi r6,sp,56 + 100aea8: 9809883a mov r4,r19 + 100aeac: 880b883a mov r5,r17 + 100aeb0: 100a9cc0 call 100a9cc <_fpadd_parts> + 100aeb4: 1009883a mov r4,r2 + 100aeb8: 100bd5c0 call 100bd5c <__pack_d> + 100aebc: dfc01517 ldw ra,84(sp) + 100aec0: dcc01417 ldw r19,80(sp) + 100aec4: dc401317 ldw r17,76(sp) + 100aec8: dec01604 addi sp,sp,88 + 100aecc: f800283a ret + +0100aed0 <__muldf3>: + 100aed0: deffe004 addi sp,sp,-128 + 100aed4: dc401815 stw r17,96(sp) + 100aed8: dc400404 addi r17,sp,16 + 100aedc: 2011883a mov r8,r4 + 100aee0: 2813883a mov r9,r5 + 100aee4: dc001715 stw r16,92(sp) + 100aee8: d809883a mov r4,sp + 100aeec: 880b883a mov r5,r17 + 100aef0: dc000904 addi r16,sp,36 + 100aef4: dfc01f15 stw ra,124(sp) + 100aef8: da400115 stw r9,4(sp) + 100aefc: d9c00315 stw r7,12(sp) + 100af00: da000015 stw r8,0(sp) + 100af04: d9800215 stw r6,8(sp) + 100af08: ddc01e15 stw r23,120(sp) + 100af0c: dd801d15 stw r22,116(sp) + 100af10: dd401c15 stw r21,112(sp) + 100af14: dd001b15 stw r20,108(sp) + 100af18: dcc01a15 stw r19,104(sp) + 100af1c: dc801915 stw r18,100(sp) + 100af20: 100c0700 call 100c070 <__unpack_d> + 100af24: d9000204 addi r4,sp,8 + 100af28: 800b883a mov r5,r16 + 100af2c: 100c0700 call 100c070 <__unpack_d> + 100af30: d9000417 ldw r4,16(sp) + 100af34: 00800044 movi r2,1 + 100af38: 1100102e bgeu r2,r4,100af7c <__muldf3+0xac> + 100af3c: d8c00917 ldw r3,36(sp) + 100af40: 10c0062e bgeu r2,r3,100af5c <__muldf3+0x8c> + 100af44: 00800104 movi r2,4 + 100af48: 20800a26 beq r4,r2,100af74 <__muldf3+0xa4> + 100af4c: 1880cc26 beq r3,r2,100b280 <__muldf3+0x3b0> + 100af50: 00800084 movi r2,2 + 100af54: 20800926 beq r4,r2,100af7c <__muldf3+0xac> + 100af58: 1880191e bne r3,r2,100afc0 <__muldf3+0xf0> + 100af5c: d8c00a17 ldw r3,40(sp) + 100af60: d8800517 ldw r2,20(sp) + 100af64: 8009883a mov r4,r16 + 100af68: 10c4c03a cmpne r2,r2,r3 + 100af6c: d8800a15 stw r2,40(sp) + 100af70: 00000706 br 100af90 <__muldf3+0xc0> + 100af74: 00800084 movi r2,2 + 100af78: 1880c326 beq r3,r2,100b288 <__muldf3+0x3b8> + 100af7c: d8800517 ldw r2,20(sp) + 100af80: d8c00a17 ldw r3,40(sp) + 100af84: 8809883a mov r4,r17 + 100af88: 10c4c03a cmpne r2,r2,r3 + 100af8c: d8800515 stw r2,20(sp) + 100af90: 100bd5c0 call 100bd5c <__pack_d> + 100af94: dfc01f17 ldw ra,124(sp) + 100af98: ddc01e17 ldw r23,120(sp) + 100af9c: dd801d17 ldw r22,116(sp) + 100afa0: dd401c17 ldw r21,112(sp) + 100afa4: dd001b17 ldw r20,108(sp) + 100afa8: dcc01a17 ldw r19,104(sp) + 100afac: dc801917 ldw r18,100(sp) + 100afb0: dc401817 ldw r17,96(sp) + 100afb4: dc001717 ldw r16,92(sp) + 100afb8: dec02004 addi sp,sp,128 + 100afbc: f800283a ret + 100afc0: dd800717 ldw r22,28(sp) + 100afc4: dc800c17 ldw r18,48(sp) + 100afc8: 002b883a mov r21,zero + 100afcc: 0023883a mov r17,zero + 100afd0: a80b883a mov r5,r21 + 100afd4: b00d883a mov r6,r22 + 100afd8: 880f883a mov r7,r17 + 100afdc: ddc00817 ldw r23,32(sp) + 100afe0: dcc00d17 ldw r19,52(sp) + 100afe4: 9009883a mov r4,r18 + 100afe8: 100bc440 call 100bc44 <__muldi3> + 100afec: 001b883a mov r13,zero + 100aff0: 680f883a mov r7,r13 + 100aff4: b009883a mov r4,r22 + 100aff8: 000b883a mov r5,zero + 100affc: 980d883a mov r6,r19 + 100b000: b82d883a mov r22,r23 + 100b004: 002f883a mov r23,zero + 100b008: db401615 stw r13,88(sp) + 100b00c: d8801315 stw r2,76(sp) + 100b010: d8c01415 stw r3,80(sp) + 100b014: dcc01515 stw r19,84(sp) + 100b018: 100bc440 call 100bc44 <__muldi3> + 100b01c: b00d883a mov r6,r22 + 100b020: 000b883a mov r5,zero + 100b024: 9009883a mov r4,r18 + 100b028: b80f883a mov r7,r23 + 100b02c: 1021883a mov r16,r2 + 100b030: 1823883a mov r17,r3 + 100b034: 100bc440 call 100bc44 <__muldi3> + 100b038: 8085883a add r2,r16,r2 + 100b03c: 140d803a cmpltu r6,r2,r16 + 100b040: 88c7883a add r3,r17,r3 + 100b044: 30cd883a add r6,r6,r3 + 100b048: 1029883a mov r20,r2 + 100b04c: 302b883a mov r21,r6 + 100b050: da801317 ldw r10,76(sp) + 100b054: dac01417 ldw r11,80(sp) + 100b058: db001517 ldw r12,84(sp) + 100b05c: db401617 ldw r13,88(sp) + 100b060: 3440612e bgeu r6,r17,100b1e8 <__muldf3+0x318> + 100b064: 0009883a mov r4,zero + 100b068: 5105883a add r2,r10,r4 + 100b06c: 128d803a cmpltu r6,r2,r10 + 100b070: 5d07883a add r3,r11,r20 + 100b074: 30cd883a add r6,r6,r3 + 100b078: 0021883a mov r16,zero + 100b07c: 04400044 movi r17,1 + 100b080: 1025883a mov r18,r2 + 100b084: 3027883a mov r19,r6 + 100b088: 32c06236 bltu r6,r11,100b214 <__muldf3+0x344> + 100b08c: 59807a26 beq r11,r6,100b278 <__muldf3+0x3a8> + 100b090: 680b883a mov r5,r13 + 100b094: b80f883a mov r7,r23 + 100b098: 6009883a mov r4,r12 + 100b09c: b00d883a mov r6,r22 + 100b0a0: 100bc440 call 100bc44 <__muldi3> + 100b0a4: 1009883a mov r4,r2 + 100b0a8: 000f883a mov r7,zero + 100b0ac: 1545883a add r2,r2,r21 + 100b0b0: 1111803a cmpltu r8,r2,r4 + 100b0b4: 19c7883a add r3,r3,r7 + 100b0b8: 40c7883a add r3,r8,r3 + 100b0bc: 88cb883a add r5,r17,r3 + 100b0c0: d8c00617 ldw r3,24(sp) + 100b0c4: 8089883a add r4,r16,r2 + 100b0c8: d8800b17 ldw r2,44(sp) + 100b0cc: 18c00104 addi r3,r3,4 + 100b0d0: 240d803a cmpltu r6,r4,r16 + 100b0d4: 10c7883a add r3,r2,r3 + 100b0d8: 2013883a mov r9,r4 + 100b0dc: d8800a17 ldw r2,40(sp) + 100b0e0: d9000517 ldw r4,20(sp) + 100b0e4: 314d883a add r6,r6,r5 + 100b0e8: 3015883a mov r10,r6 + 100b0ec: 2088c03a cmpne r4,r4,r2 + 100b0f0: 00880034 movhi r2,8192 + 100b0f4: 10bfffc4 addi r2,r2,-1 + 100b0f8: d9000f15 stw r4,60(sp) + 100b0fc: d8c01015 stw r3,64(sp) + 100b100: 1180162e bgeu r2,r6,100b15c <__muldf3+0x28c> + 100b104: 1811883a mov r8,r3 + 100b108: 101f883a mov r15,r2 + 100b10c: 980497fa slli r2,r19,31 + 100b110: 9016d07a srli r11,r18,1 + 100b114: 500697fa slli r3,r10,31 + 100b118: 480cd07a srli r6,r9,1 + 100b11c: 500ed07a srli r7,r10,1 + 100b120: 12d6b03a or r11,r2,r11 + 100b124: 00800044 movi r2,1 + 100b128: 198cb03a or r6,r3,r6 + 100b12c: 4888703a and r4,r9,r2 + 100b130: 9818d07a srli r12,r19,1 + 100b134: 001b883a mov r13,zero + 100b138: 03a00034 movhi r14,32768 + 100b13c: 3013883a mov r9,r6 + 100b140: 3815883a mov r10,r7 + 100b144: 4091883a add r8,r8,r2 + 100b148: 20000226 beq r4,zero,100b154 <__muldf3+0x284> + 100b14c: 5b64b03a or r18,r11,r13 + 100b150: 63a6b03a or r19,r12,r14 + 100b154: 7abfed36 bltu r15,r10,100b10c <__muldf3+0x23c> + 100b158: da001015 stw r8,64(sp) + 100b15c: 00840034 movhi r2,4096 + 100b160: 10bfffc4 addi r2,r2,-1 + 100b164: 12801436 bltu r2,r10,100b1b8 <__muldf3+0x2e8> + 100b168: da001017 ldw r8,64(sp) + 100b16c: 101f883a mov r15,r2 + 100b170: 4a45883a add r2,r9,r9 + 100b174: 124d803a cmpltu r6,r2,r9 + 100b178: 5287883a add r3,r10,r10 + 100b17c: 9497883a add r11,r18,r18 + 100b180: 5c8f803a cmpltu r7,r11,r18 + 100b184: 9cd9883a add r12,r19,r19 + 100b188: 01000044 movi r4,1 + 100b18c: 30cd883a add r6,r6,r3 + 100b190: 3b0f883a add r7,r7,r12 + 100b194: 423fffc4 addi r8,r8,-1 + 100b198: 1013883a mov r9,r2 + 100b19c: 3015883a mov r10,r6 + 100b1a0: 111ab03a or r13,r2,r4 + 100b1a4: 98003016 blt r19,zero,100b268 <__muldf3+0x398> + 100b1a8: 5825883a mov r18,r11 + 100b1ac: 3827883a mov r19,r7 + 100b1b0: 7abfef2e bgeu r15,r10,100b170 <__muldf3+0x2a0> + 100b1b4: da001015 stw r8,64(sp) + 100b1b8: 00803fc4 movi r2,255 + 100b1bc: 488e703a and r7,r9,r2 + 100b1c0: 00802004 movi r2,128 + 100b1c4: 0007883a mov r3,zero + 100b1c8: 0011883a mov r8,zero + 100b1cc: 38801826 beq r7,r2,100b230 <__muldf3+0x360> + 100b1d0: 008000c4 movi r2,3 + 100b1d4: d9000e04 addi r4,sp,56 + 100b1d8: da801215 stw r10,72(sp) + 100b1dc: d8800e15 stw r2,56(sp) + 100b1e0: da401115 stw r9,68(sp) + 100b1e4: 003f6a06 br 100af90 <__muldf3+0xc0> + 100b1e8: 89802126 beq r17,r6,100b270 <__muldf3+0x3a0> + 100b1ec: 0009883a mov r4,zero + 100b1f0: 5105883a add r2,r10,r4 + 100b1f4: 128d803a cmpltu r6,r2,r10 + 100b1f8: 5d07883a add r3,r11,r20 + 100b1fc: 30cd883a add r6,r6,r3 + 100b200: 0021883a mov r16,zero + 100b204: 0023883a mov r17,zero + 100b208: 1025883a mov r18,r2 + 100b20c: 3027883a mov r19,r6 + 100b210: 32ff9e2e bgeu r6,r11,100b08c <__muldf3+0x1bc> + 100b214: 00800044 movi r2,1 + 100b218: 8089883a add r4,r16,r2 + 100b21c: 240d803a cmpltu r6,r4,r16 + 100b220: 344d883a add r6,r6,r17 + 100b224: 2021883a mov r16,r4 + 100b228: 3023883a mov r17,r6 + 100b22c: 003f9806 br 100b090 <__muldf3+0x1c0> + 100b230: 403fe71e bne r8,zero,100b1d0 <__muldf3+0x300> + 100b234: 01004004 movi r4,256 + 100b238: 4904703a and r2,r9,r4 + 100b23c: 10c4b03a or r2,r2,r3 + 100b240: 103fe31e bne r2,zero,100b1d0 <__muldf3+0x300> + 100b244: 94c4b03a or r2,r18,r19 + 100b248: 103fe126 beq r2,zero,100b1d0 <__muldf3+0x300> + 100b24c: 49c5883a add r2,r9,r7 + 100b250: 1251803a cmpltu r8,r2,r9 + 100b254: 4291883a add r8,r8,r10 + 100b258: 013fc004 movi r4,-256 + 100b25c: 1112703a and r9,r2,r4 + 100b260: 4015883a mov r10,r8 + 100b264: 003fda06 br 100b1d0 <__muldf3+0x300> + 100b268: 6813883a mov r9,r13 + 100b26c: 003fce06 br 100b1a8 <__muldf3+0x2d8> + 100b270: 143f7c36 bltu r2,r16,100b064 <__muldf3+0x194> + 100b274: 003fdd06 br 100b1ec <__muldf3+0x31c> + 100b278: 12bf852e bgeu r2,r10,100b090 <__muldf3+0x1c0> + 100b27c: 003fe506 br 100b214 <__muldf3+0x344> + 100b280: 00800084 movi r2,2 + 100b284: 20bf351e bne r4,r2,100af5c <__muldf3+0x8c> + 100b288: 010040b4 movhi r4,258 + 100b28c: 2123e904 addi r4,r4,-28764 + 100b290: 003f3f06 br 100af90 <__muldf3+0xc0> + +0100b294 <__divdf3>: + 100b294: deffed04 addi sp,sp,-76 + 100b298: dcc01115 stw r19,68(sp) + 100b29c: dcc00404 addi r19,sp,16 + 100b2a0: 2011883a mov r8,r4 + 100b2a4: 2813883a mov r9,r5 + 100b2a8: dc000e15 stw r16,56(sp) + 100b2ac: d809883a mov r4,sp + 100b2b0: 980b883a mov r5,r19 + 100b2b4: dc000904 addi r16,sp,36 + 100b2b8: dfc01215 stw ra,72(sp) + 100b2bc: da400115 stw r9,4(sp) + 100b2c0: d9c00315 stw r7,12(sp) + 100b2c4: da000015 stw r8,0(sp) + 100b2c8: d9800215 stw r6,8(sp) + 100b2cc: dc801015 stw r18,64(sp) + 100b2d0: dc400f15 stw r17,60(sp) + 100b2d4: 100c0700 call 100c070 <__unpack_d> + 100b2d8: d9000204 addi r4,sp,8 + 100b2dc: 800b883a mov r5,r16 + 100b2e0: 100c0700 call 100c070 <__unpack_d> + 100b2e4: d9000417 ldw r4,16(sp) + 100b2e8: 00800044 movi r2,1 + 100b2ec: 11000b2e bgeu r2,r4,100b31c <__divdf3+0x88> + 100b2f0: d9400917 ldw r5,36(sp) + 100b2f4: 1140762e bgeu r2,r5,100b4d0 <__divdf3+0x23c> + 100b2f8: d8800517 ldw r2,20(sp) + 100b2fc: d8c00a17 ldw r3,40(sp) + 100b300: 01800104 movi r6,4 + 100b304: 10c4f03a xor r2,r2,r3 + 100b308: d8800515 stw r2,20(sp) + 100b30c: 21800226 beq r4,r6,100b318 <__divdf3+0x84> + 100b310: 00800084 movi r2,2 + 100b314: 2080141e bne r4,r2,100b368 <__divdf3+0xd4> + 100b318: 29000926 beq r5,r4,100b340 <__divdf3+0xac> + 100b31c: 9809883a mov r4,r19 + 100b320: 100bd5c0 call 100bd5c <__pack_d> + 100b324: dfc01217 ldw ra,72(sp) + 100b328: dcc01117 ldw r19,68(sp) + 100b32c: dc801017 ldw r18,64(sp) + 100b330: dc400f17 ldw r17,60(sp) + 100b334: dc000e17 ldw r16,56(sp) + 100b338: dec01304 addi sp,sp,76 + 100b33c: f800283a ret + 100b340: 010040b4 movhi r4,258 + 100b344: 2123e904 addi r4,r4,-28764 + 100b348: 100bd5c0 call 100bd5c <__pack_d> + 100b34c: dfc01217 ldw ra,72(sp) + 100b350: dcc01117 ldw r19,68(sp) + 100b354: dc801017 ldw r18,64(sp) + 100b358: dc400f17 ldw r17,60(sp) + 100b35c: dc000e17 ldw r16,56(sp) + 100b360: dec01304 addi sp,sp,76 + 100b364: f800283a ret + 100b368: 29805b26 beq r5,r6,100b4d8 <__divdf3+0x244> + 100b36c: 28802d26 beq r5,r2,100b424 <__divdf3+0x190> + 100b370: d8c00617 ldw r3,24(sp) + 100b374: d8800b17 ldw r2,44(sp) + 100b378: d9c00817 ldw r7,32(sp) + 100b37c: dc400d17 ldw r17,52(sp) + 100b380: 188bc83a sub r5,r3,r2 + 100b384: d9800717 ldw r6,28(sp) + 100b388: dc000c17 ldw r16,48(sp) + 100b38c: d9400615 stw r5,24(sp) + 100b390: 3c403836 bltu r7,r17,100b474 <__divdf3+0x1e0> + 100b394: 89c03626 beq r17,r7,100b470 <__divdf3+0x1dc> + 100b398: 0015883a mov r10,zero + 100b39c: 001d883a mov r14,zero + 100b3a0: 02c40034 movhi r11,4096 + 100b3a4: 001f883a mov r15,zero + 100b3a8: 003f883a mov ra,zero + 100b3ac: 04800f44 movi r18,61 + 100b3b0: 00000f06 br 100b3f0 <__divdf3+0x15c> + 100b3b4: 601d883a mov r14,r12 + 100b3b8: 681f883a mov r15,r13 + 100b3bc: 400d883a mov r6,r8 + 100b3c0: 100f883a mov r7,r2 + 100b3c4: 3191883a add r8,r6,r6 + 100b3c8: 5808d07a srli r4,r11,1 + 100b3cc: 4185803a cmpltu r2,r8,r6 + 100b3d0: 39d3883a add r9,r7,r7 + 100b3d4: 28c6b03a or r3,r5,r3 + 100b3d8: 1245883a add r2,r2,r9 + 100b3dc: 1815883a mov r10,r3 + 100b3e0: 2017883a mov r11,r4 + 100b3e4: 400d883a mov r6,r8 + 100b3e8: 100f883a mov r7,r2 + 100b3ec: fc801726 beq ra,r18,100b44c <__divdf3+0x1b8> + 100b3f0: 580a97fa slli r5,r11,31 + 100b3f4: 5006d07a srli r3,r10,1 + 100b3f8: ffc00044 addi ra,ra,1 + 100b3fc: 3c7ff136 bltu r7,r17,100b3c4 <__divdf3+0x130> + 100b400: 3411c83a sub r8,r6,r16 + 100b404: 3205803a cmpltu r2,r6,r8 + 100b408: 3c53c83a sub r9,r7,r17 + 100b40c: 7298b03a or r12,r14,r10 + 100b410: 7adab03a or r13,r15,r11 + 100b414: 4885c83a sub r2,r9,r2 + 100b418: 89ffe61e bne r17,r7,100b3b4 <__divdf3+0x120> + 100b41c: 343fe936 bltu r6,r16,100b3c4 <__divdf3+0x130> + 100b420: 003fe406 br 100b3b4 <__divdf3+0x120> + 100b424: 9809883a mov r4,r19 + 100b428: d9800415 stw r6,16(sp) + 100b42c: 100bd5c0 call 100bd5c <__pack_d> + 100b430: dfc01217 ldw ra,72(sp) + 100b434: dcc01117 ldw r19,68(sp) + 100b438: dc801017 ldw r18,64(sp) + 100b43c: dc400f17 ldw r17,60(sp) + 100b440: dc000e17 ldw r16,56(sp) + 100b444: dec01304 addi sp,sp,76 + 100b448: f800283a ret + 100b44c: 00803fc4 movi r2,255 + 100b450: 7090703a and r8,r14,r2 + 100b454: 00802004 movi r2,128 + 100b458: 0007883a mov r3,zero + 100b45c: 0013883a mov r9,zero + 100b460: 40800d26 beq r8,r2,100b498 <__divdf3+0x204> + 100b464: dbc00815 stw r15,32(sp) + 100b468: db800715 stw r14,28(sp) + 100b46c: 003fab06 br 100b31c <__divdf3+0x88> + 100b470: 343fc92e bgeu r6,r16,100b398 <__divdf3+0x104> + 100b474: 3185883a add r2,r6,r6 + 100b478: 1189803a cmpltu r4,r2,r6 + 100b47c: 39c7883a add r3,r7,r7 + 100b480: 20c9883a add r4,r4,r3 + 100b484: 297fffc4 addi r5,r5,-1 + 100b488: 100d883a mov r6,r2 + 100b48c: 200f883a mov r7,r4 + 100b490: d9400615 stw r5,24(sp) + 100b494: 003fc006 br 100b398 <__divdf3+0x104> + 100b498: 483ff21e bne r9,zero,100b464 <__divdf3+0x1d0> + 100b49c: 01004004 movi r4,256 + 100b4a0: 7104703a and r2,r14,r4 + 100b4a4: 10c4b03a or r2,r2,r3 + 100b4a8: 103fee1e bne r2,zero,100b464 <__divdf3+0x1d0> + 100b4ac: 31c4b03a or r2,r6,r7 + 100b4b0: 103fec26 beq r2,zero,100b464 <__divdf3+0x1d0> + 100b4b4: 7205883a add r2,r14,r8 + 100b4b8: 1391803a cmpltu r8,r2,r14 + 100b4bc: 43d1883a add r8,r8,r15 + 100b4c0: 013fc004 movi r4,-256 + 100b4c4: 111c703a and r14,r2,r4 + 100b4c8: 401f883a mov r15,r8 + 100b4cc: 003fe506 br 100b464 <__divdf3+0x1d0> + 100b4d0: 8009883a mov r4,r16 + 100b4d4: 003f9206 br 100b320 <__divdf3+0x8c> + 100b4d8: 9809883a mov r4,r19 + 100b4dc: d8000715 stw zero,28(sp) + 100b4e0: d8000815 stw zero,32(sp) + 100b4e4: d8000615 stw zero,24(sp) + 100b4e8: 003f8d06 br 100b320 <__divdf3+0x8c> + +0100b4ec <__eqdf2>: + 100b4ec: deffef04 addi sp,sp,-68 + 100b4f0: dc400f15 stw r17,60(sp) + 100b4f4: dc400404 addi r17,sp,16 + 100b4f8: 2005883a mov r2,r4 + 100b4fc: 2807883a mov r3,r5 + 100b500: dc000e15 stw r16,56(sp) + 100b504: d809883a mov r4,sp + 100b508: 880b883a mov r5,r17 + 100b50c: dc000904 addi r16,sp,36 + 100b510: d8c00115 stw r3,4(sp) + 100b514: d8800015 stw r2,0(sp) + 100b518: d9800215 stw r6,8(sp) + 100b51c: dfc01015 stw ra,64(sp) + 100b520: d9c00315 stw r7,12(sp) + 100b524: 100c0700 call 100c070 <__unpack_d> + 100b528: d9000204 addi r4,sp,8 + 100b52c: 800b883a mov r5,r16 + 100b530: 100c0700 call 100c070 <__unpack_d> + 100b534: d8800417 ldw r2,16(sp) + 100b538: 00c00044 movi r3,1 + 100b53c: 180d883a mov r6,r3 + 100b540: 1880062e bgeu r3,r2,100b55c <__eqdf2+0x70> + 100b544: d8800917 ldw r2,36(sp) + 100b548: 8809883a mov r4,r17 + 100b54c: 800b883a mov r5,r16 + 100b550: 1880022e bgeu r3,r2,100b55c <__eqdf2+0x70> + 100b554: 100c1a80 call 100c1a8 <__fpcmp_parts_d> + 100b558: 100d883a mov r6,r2 + 100b55c: 3005883a mov r2,r6 + 100b560: dfc01017 ldw ra,64(sp) + 100b564: dc400f17 ldw r17,60(sp) + 100b568: dc000e17 ldw r16,56(sp) + 100b56c: dec01104 addi sp,sp,68 + 100b570: f800283a ret + +0100b574 <__nedf2>: + 100b574: deffef04 addi sp,sp,-68 + 100b578: dc400f15 stw r17,60(sp) + 100b57c: dc400404 addi r17,sp,16 + 100b580: 2005883a mov r2,r4 + 100b584: 2807883a mov r3,r5 + 100b588: dc000e15 stw r16,56(sp) + 100b58c: d809883a mov r4,sp + 100b590: 880b883a mov r5,r17 + 100b594: dc000904 addi r16,sp,36 + 100b598: d8c00115 stw r3,4(sp) + 100b59c: d8800015 stw r2,0(sp) + 100b5a0: d9800215 stw r6,8(sp) + 100b5a4: dfc01015 stw ra,64(sp) + 100b5a8: d9c00315 stw r7,12(sp) + 100b5ac: 100c0700 call 100c070 <__unpack_d> + 100b5b0: d9000204 addi r4,sp,8 + 100b5b4: 800b883a mov r5,r16 + 100b5b8: 100c0700 call 100c070 <__unpack_d> + 100b5bc: d8800417 ldw r2,16(sp) + 100b5c0: 00c00044 movi r3,1 + 100b5c4: 180d883a mov r6,r3 + 100b5c8: 1880062e bgeu r3,r2,100b5e4 <__nedf2+0x70> + 100b5cc: d8800917 ldw r2,36(sp) + 100b5d0: 8809883a mov r4,r17 + 100b5d4: 800b883a mov r5,r16 + 100b5d8: 1880022e bgeu r3,r2,100b5e4 <__nedf2+0x70> + 100b5dc: 100c1a80 call 100c1a8 <__fpcmp_parts_d> + 100b5e0: 100d883a mov r6,r2 + 100b5e4: 3005883a mov r2,r6 + 100b5e8: dfc01017 ldw ra,64(sp) + 100b5ec: dc400f17 ldw r17,60(sp) + 100b5f0: dc000e17 ldw r16,56(sp) + 100b5f4: dec01104 addi sp,sp,68 + 100b5f8: f800283a ret + +0100b5fc <__gtdf2>: + 100b5fc: deffef04 addi sp,sp,-68 + 100b600: dc400f15 stw r17,60(sp) + 100b604: dc400404 addi r17,sp,16 + 100b608: 2005883a mov r2,r4 + 100b60c: 2807883a mov r3,r5 + 100b610: dc000e15 stw r16,56(sp) + 100b614: d809883a mov r4,sp + 100b618: 880b883a mov r5,r17 + 100b61c: dc000904 addi r16,sp,36 + 100b620: d8c00115 stw r3,4(sp) + 100b624: d8800015 stw r2,0(sp) + 100b628: d9800215 stw r6,8(sp) + 100b62c: dfc01015 stw ra,64(sp) + 100b630: d9c00315 stw r7,12(sp) + 100b634: 100c0700 call 100c070 <__unpack_d> + 100b638: d9000204 addi r4,sp,8 + 100b63c: 800b883a mov r5,r16 + 100b640: 100c0700 call 100c070 <__unpack_d> + 100b644: d8800417 ldw r2,16(sp) + 100b648: 00c00044 movi r3,1 + 100b64c: 01bfffc4 movi r6,-1 + 100b650: 1880062e bgeu r3,r2,100b66c <__gtdf2+0x70> + 100b654: d8800917 ldw r2,36(sp) + 100b658: 8809883a mov r4,r17 + 100b65c: 800b883a mov r5,r16 + 100b660: 1880022e bgeu r3,r2,100b66c <__gtdf2+0x70> + 100b664: 100c1a80 call 100c1a8 <__fpcmp_parts_d> + 100b668: 100d883a mov r6,r2 + 100b66c: 3005883a mov r2,r6 + 100b670: dfc01017 ldw ra,64(sp) + 100b674: dc400f17 ldw r17,60(sp) + 100b678: dc000e17 ldw r16,56(sp) + 100b67c: dec01104 addi sp,sp,68 + 100b680: f800283a ret + +0100b684 <__gedf2>: + 100b684: deffef04 addi sp,sp,-68 + 100b688: dc400f15 stw r17,60(sp) + 100b68c: dc400404 addi r17,sp,16 + 100b690: 2005883a mov r2,r4 + 100b694: 2807883a mov r3,r5 + 100b698: dc000e15 stw r16,56(sp) + 100b69c: d809883a mov r4,sp + 100b6a0: 880b883a mov r5,r17 + 100b6a4: dc000904 addi r16,sp,36 + 100b6a8: d8c00115 stw r3,4(sp) + 100b6ac: d8800015 stw r2,0(sp) + 100b6b0: d9800215 stw r6,8(sp) + 100b6b4: dfc01015 stw ra,64(sp) + 100b6b8: d9c00315 stw r7,12(sp) + 100b6bc: 100c0700 call 100c070 <__unpack_d> + 100b6c0: d9000204 addi r4,sp,8 + 100b6c4: 800b883a mov r5,r16 + 100b6c8: 100c0700 call 100c070 <__unpack_d> + 100b6cc: d8800417 ldw r2,16(sp) + 100b6d0: 00c00044 movi r3,1 + 100b6d4: 01bfffc4 movi r6,-1 + 100b6d8: 1880062e bgeu r3,r2,100b6f4 <__gedf2+0x70> + 100b6dc: d8800917 ldw r2,36(sp) + 100b6e0: 8809883a mov r4,r17 + 100b6e4: 800b883a mov r5,r16 + 100b6e8: 1880022e bgeu r3,r2,100b6f4 <__gedf2+0x70> + 100b6ec: 100c1a80 call 100c1a8 <__fpcmp_parts_d> + 100b6f0: 100d883a mov r6,r2 + 100b6f4: 3005883a mov r2,r6 + 100b6f8: dfc01017 ldw ra,64(sp) + 100b6fc: dc400f17 ldw r17,60(sp) + 100b700: dc000e17 ldw r16,56(sp) + 100b704: dec01104 addi sp,sp,68 + 100b708: f800283a ret + +0100b70c <__ltdf2>: + 100b70c: deffef04 addi sp,sp,-68 + 100b710: dc400f15 stw r17,60(sp) + 100b714: dc400404 addi r17,sp,16 + 100b718: 2005883a mov r2,r4 + 100b71c: 2807883a mov r3,r5 + 100b720: dc000e15 stw r16,56(sp) + 100b724: d809883a mov r4,sp + 100b728: 880b883a mov r5,r17 + 100b72c: dc000904 addi r16,sp,36 + 100b730: d8c00115 stw r3,4(sp) + 100b734: d8800015 stw r2,0(sp) + 100b738: d9800215 stw r6,8(sp) + 100b73c: dfc01015 stw ra,64(sp) + 100b740: d9c00315 stw r7,12(sp) + 100b744: 100c0700 call 100c070 <__unpack_d> + 100b748: d9000204 addi r4,sp,8 + 100b74c: 800b883a mov r5,r16 + 100b750: 100c0700 call 100c070 <__unpack_d> + 100b754: d8800417 ldw r2,16(sp) + 100b758: 00c00044 movi r3,1 + 100b75c: 180d883a mov r6,r3 + 100b760: 1880062e bgeu r3,r2,100b77c <__ltdf2+0x70> + 100b764: d8800917 ldw r2,36(sp) + 100b768: 8809883a mov r4,r17 + 100b76c: 800b883a mov r5,r16 + 100b770: 1880022e bgeu r3,r2,100b77c <__ltdf2+0x70> + 100b774: 100c1a80 call 100c1a8 <__fpcmp_parts_d> + 100b778: 100d883a mov r6,r2 + 100b77c: 3005883a mov r2,r6 + 100b780: dfc01017 ldw ra,64(sp) + 100b784: dc400f17 ldw r17,60(sp) + 100b788: dc000e17 ldw r16,56(sp) + 100b78c: dec01104 addi sp,sp,68 + 100b790: f800283a ret + +0100b794 <__floatsidf>: + 100b794: 2006d7fa srli r3,r4,31 + 100b798: defff604 addi sp,sp,-40 + 100b79c: 008000c4 movi r2,3 + 100b7a0: dfc00915 stw ra,36(sp) + 100b7a4: dcc00815 stw r19,32(sp) + 100b7a8: dc800715 stw r18,28(sp) + 100b7ac: dc400615 stw r17,24(sp) + 100b7b0: dc000515 stw r16,20(sp) + 100b7b4: d8800015 stw r2,0(sp) + 100b7b8: d8c00115 stw r3,4(sp) + 100b7bc: 20000f1e bne r4,zero,100b7fc <__floatsidf+0x68> + 100b7c0: 00800084 movi r2,2 + 100b7c4: d8800015 stw r2,0(sp) + 100b7c8: d809883a mov r4,sp + 100b7cc: 100bd5c0 call 100bd5c <__pack_d> + 100b7d0: 1009883a mov r4,r2 + 100b7d4: 180b883a mov r5,r3 + 100b7d8: 2005883a mov r2,r4 + 100b7dc: 2807883a mov r3,r5 + 100b7e0: dfc00917 ldw ra,36(sp) + 100b7e4: dcc00817 ldw r19,32(sp) + 100b7e8: dc800717 ldw r18,28(sp) + 100b7ec: dc400617 ldw r17,24(sp) + 100b7f0: dc000517 ldw r16,20(sp) + 100b7f4: dec00a04 addi sp,sp,40 + 100b7f8: f800283a ret + 100b7fc: 00800f04 movi r2,60 + 100b800: 1807003a cmpeq r3,r3,zero + 100b804: d8800215 stw r2,8(sp) + 100b808: 18001126 beq r3,zero,100b850 <__floatsidf+0xbc> + 100b80c: 0027883a mov r19,zero + 100b810: 2025883a mov r18,r4 + 100b814: d9000315 stw r4,12(sp) + 100b818: dcc00415 stw r19,16(sp) + 100b81c: 100bcdc0 call 100bcdc <__clzsi2> + 100b820: 11000744 addi r4,r2,29 + 100b824: 013fe80e bge zero,r4,100b7c8 <__floatsidf+0x34> + 100b828: 10bfff44 addi r2,r2,-3 + 100b82c: 10000c16 blt r2,zero,100b860 <__floatsidf+0xcc> + 100b830: 90a2983a sll r17,r18,r2 + 100b834: 0021883a mov r16,zero + 100b838: d8800217 ldw r2,8(sp) + 100b83c: dc400415 stw r17,16(sp) + 100b840: dc000315 stw r16,12(sp) + 100b844: 1105c83a sub r2,r2,r4 + 100b848: d8800215 stw r2,8(sp) + 100b84c: 003fde06 br 100b7c8 <__floatsidf+0x34> + 100b850: 00a00034 movhi r2,32768 + 100b854: 20800a26 beq r4,r2,100b880 <__floatsidf+0xec> + 100b858: 0109c83a sub r4,zero,r4 + 100b85c: 003feb06 br 100b80c <__floatsidf+0x78> + 100b860: 9006d07a srli r3,r18,1 + 100b864: 008007c4 movi r2,31 + 100b868: 1105c83a sub r2,r2,r4 + 100b86c: 1886d83a srl r3,r3,r2 + 100b870: 9922983a sll r17,r19,r4 + 100b874: 9120983a sll r16,r18,r4 + 100b878: 1c62b03a or r17,r3,r17 + 100b87c: 003fee06 br 100b838 <__floatsidf+0xa4> + 100b880: 0009883a mov r4,zero + 100b884: 01707834 movhi r5,49632 + 100b888: 003fd306 br 100b7d8 <__floatsidf+0x44> + +0100b88c <__fixdfsi>: + 100b88c: defff804 addi sp,sp,-32 + 100b890: 2005883a mov r2,r4 + 100b894: 2807883a mov r3,r5 + 100b898: d809883a mov r4,sp + 100b89c: d9400204 addi r5,sp,8 + 100b8a0: d8c00115 stw r3,4(sp) + 100b8a4: d8800015 stw r2,0(sp) + 100b8a8: dfc00715 stw ra,28(sp) + 100b8ac: 100c0700 call 100c070 <__unpack_d> + 100b8b0: d8c00217 ldw r3,8(sp) + 100b8b4: 00800084 movi r2,2 + 100b8b8: 1880051e bne r3,r2,100b8d0 <__fixdfsi+0x44> + 100b8bc: 0007883a mov r3,zero + 100b8c0: 1805883a mov r2,r3 + 100b8c4: dfc00717 ldw ra,28(sp) + 100b8c8: dec00804 addi sp,sp,32 + 100b8cc: f800283a ret + 100b8d0: 00800044 movi r2,1 + 100b8d4: 10fff92e bgeu r2,r3,100b8bc <__fixdfsi+0x30> + 100b8d8: 00800104 movi r2,4 + 100b8dc: 18800426 beq r3,r2,100b8f0 <__fixdfsi+0x64> + 100b8e0: d8c00417 ldw r3,16(sp) + 100b8e4: 183ff516 blt r3,zero,100b8bc <__fixdfsi+0x30> + 100b8e8: 00800784 movi r2,30 + 100b8ec: 10c0080e bge r2,r3,100b910 <__fixdfsi+0x84> + 100b8f0: d8800317 ldw r2,12(sp) + 100b8f4: 1000121e bne r2,zero,100b940 <__fixdfsi+0xb4> + 100b8f8: 00e00034 movhi r3,32768 + 100b8fc: 18ffffc4 addi r3,r3,-1 + 100b900: 1805883a mov r2,r3 + 100b904: dfc00717 ldw ra,28(sp) + 100b908: dec00804 addi sp,sp,32 + 100b90c: f800283a ret + 100b910: 00800f04 movi r2,60 + 100b914: 10d1c83a sub r8,r2,r3 + 100b918: 40bff804 addi r2,r8,-32 + 100b91c: d9800517 ldw r6,20(sp) + 100b920: d9c00617 ldw r7,24(sp) + 100b924: 10000816 blt r2,zero,100b948 <__fixdfsi+0xbc> + 100b928: 3888d83a srl r4,r7,r2 + 100b92c: d8800317 ldw r2,12(sp) + 100b930: 2007883a mov r3,r4 + 100b934: 103fe226 beq r2,zero,100b8c0 <__fixdfsi+0x34> + 100b938: 0107c83a sub r3,zero,r4 + 100b93c: 003fe006 br 100b8c0 <__fixdfsi+0x34> + 100b940: 00e00034 movhi r3,32768 + 100b944: 003fde06 br 100b8c0 <__fixdfsi+0x34> + 100b948: 39c7883a add r3,r7,r7 + 100b94c: 008007c4 movi r2,31 + 100b950: 1205c83a sub r2,r2,r8 + 100b954: 1886983a sll r3,r3,r2 + 100b958: 3208d83a srl r4,r6,r8 + 100b95c: 1908b03a or r4,r3,r4 + 100b960: 003ff206 br 100b92c <__fixdfsi+0xa0> + +0100b964 <__floatunsidf>: + 100b964: defff204 addi sp,sp,-56 + 100b968: dfc00d15 stw ra,52(sp) + 100b96c: ddc00c15 stw r23,48(sp) + 100b970: dd800b15 stw r22,44(sp) + 100b974: dd400a15 stw r21,40(sp) + 100b978: dd000915 stw r20,36(sp) + 100b97c: dcc00815 stw r19,32(sp) + 100b980: dc800715 stw r18,28(sp) + 100b984: dc400615 stw r17,24(sp) + 100b988: dc000515 stw r16,20(sp) + 100b98c: d8000115 stw zero,4(sp) + 100b990: 20000f1e bne r4,zero,100b9d0 <__floatunsidf+0x6c> + 100b994: 00800084 movi r2,2 + 100b998: d8800015 stw r2,0(sp) + 100b99c: d809883a mov r4,sp + 100b9a0: 100bd5c0 call 100bd5c <__pack_d> + 100b9a4: dfc00d17 ldw ra,52(sp) + 100b9a8: ddc00c17 ldw r23,48(sp) + 100b9ac: dd800b17 ldw r22,44(sp) + 100b9b0: dd400a17 ldw r21,40(sp) + 100b9b4: dd000917 ldw r20,36(sp) + 100b9b8: dcc00817 ldw r19,32(sp) + 100b9bc: dc800717 ldw r18,28(sp) + 100b9c0: dc400617 ldw r17,24(sp) + 100b9c4: dc000517 ldw r16,20(sp) + 100b9c8: dec00e04 addi sp,sp,56 + 100b9cc: f800283a ret + 100b9d0: 008000c4 movi r2,3 + 100b9d4: 00c00f04 movi r3,60 + 100b9d8: 002f883a mov r23,zero + 100b9dc: 202d883a mov r22,r4 + 100b9e0: d8800015 stw r2,0(sp) + 100b9e4: d8c00215 stw r3,8(sp) + 100b9e8: d9000315 stw r4,12(sp) + 100b9ec: ddc00415 stw r23,16(sp) + 100b9f0: 100bcdc0 call 100bcdc <__clzsi2> + 100b9f4: 12400744 addi r9,r2,29 + 100b9f8: 48000b16 blt r9,zero,100ba28 <__floatunsidf+0xc4> + 100b9fc: 483fe726 beq r9,zero,100b99c <__floatunsidf+0x38> + 100ba00: 10bfff44 addi r2,r2,-3 + 100ba04: 10002e16 blt r2,zero,100bac0 <__floatunsidf+0x15c> + 100ba08: b0a2983a sll r17,r22,r2 + 100ba0c: 0021883a mov r16,zero + 100ba10: d8800217 ldw r2,8(sp) + 100ba14: dc400415 stw r17,16(sp) + 100ba18: dc000315 stw r16,12(sp) + 100ba1c: 1245c83a sub r2,r2,r9 + 100ba20: d8800215 stw r2,8(sp) + 100ba24: 003fdd06 br 100b99c <__floatunsidf+0x38> + 100ba28: 0255c83a sub r10,zero,r9 + 100ba2c: 51bff804 addi r6,r10,-32 + 100ba30: 30001b16 blt r6,zero,100baa0 <__floatunsidf+0x13c> + 100ba34: b9a8d83a srl r20,r23,r6 + 100ba38: 002b883a mov r21,zero + 100ba3c: 000f883a mov r7,zero + 100ba40: 01000044 movi r4,1 + 100ba44: 0011883a mov r8,zero + 100ba48: 30002516 blt r6,zero,100bae0 <__floatunsidf+0x17c> + 100ba4c: 21a6983a sll r19,r4,r6 + 100ba50: 0025883a mov r18,zero + 100ba54: 00bfffc4 movi r2,-1 + 100ba58: 9089883a add r4,r18,r2 + 100ba5c: 988b883a add r5,r19,r2 + 100ba60: 248d803a cmpltu r6,r4,r18 + 100ba64: 314b883a add r5,r6,r5 + 100ba68: b104703a and r2,r22,r4 + 100ba6c: b946703a and r3,r23,r5 + 100ba70: 10c4b03a or r2,r2,r3 + 100ba74: 10000226 beq r2,zero,100ba80 <__floatunsidf+0x11c> + 100ba78: 01c00044 movi r7,1 + 100ba7c: 0011883a mov r8,zero + 100ba80: d9000217 ldw r4,8(sp) + 100ba84: a1c4b03a or r2,r20,r7 + 100ba88: aa06b03a or r3,r21,r8 + 100ba8c: 2249c83a sub r4,r4,r9 + 100ba90: d8c00415 stw r3,16(sp) + 100ba94: d9000215 stw r4,8(sp) + 100ba98: d8800315 stw r2,12(sp) + 100ba9c: 003fbf06 br 100b99c <__floatunsidf+0x38> + 100baa0: bdc7883a add r3,r23,r23 + 100baa4: 008007c4 movi r2,31 + 100baa8: 1285c83a sub r2,r2,r10 + 100baac: 1886983a sll r3,r3,r2 + 100bab0: b2a8d83a srl r20,r22,r10 + 100bab4: baaad83a srl r21,r23,r10 + 100bab8: 1d28b03a or r20,r3,r20 + 100babc: 003fdf06 br 100ba3c <__floatunsidf+0xd8> + 100bac0: b006d07a srli r3,r22,1 + 100bac4: 008007c4 movi r2,31 + 100bac8: 1245c83a sub r2,r2,r9 + 100bacc: 1886d83a srl r3,r3,r2 + 100bad0: ba62983a sll r17,r23,r9 + 100bad4: b260983a sll r16,r22,r9 + 100bad8: 1c62b03a or r17,r3,r17 + 100badc: 003fcc06 br 100ba10 <__floatunsidf+0xac> + 100bae0: 2006d07a srli r3,r4,1 + 100bae4: 008007c4 movi r2,31 + 100bae8: 1285c83a sub r2,r2,r10 + 100baec: 18a6d83a srl r19,r3,r2 + 100baf0: 22a4983a sll r18,r4,r10 + 100baf4: 003fd706 br 100ba54 <__floatunsidf+0xf0> + +0100baf8 : + 100baf8: 29001b2e bgeu r5,r4,100bb68 + 100bafc: 28001a16 blt r5,zero,100bb68 + 100bb00: 00800044 movi r2,1 + 100bb04: 0007883a mov r3,zero + 100bb08: 01c007c4 movi r7,31 + 100bb0c: 00000306 br 100bb1c + 100bb10: 19c01326 beq r3,r7,100bb60 + 100bb14: 18c00044 addi r3,r3,1 + 100bb18: 28000416 blt r5,zero,100bb2c + 100bb1c: 294b883a add r5,r5,r5 + 100bb20: 1085883a add r2,r2,r2 + 100bb24: 293ffa36 bltu r5,r4,100bb10 + 100bb28: 10000d26 beq r2,zero,100bb60 + 100bb2c: 0007883a mov r3,zero + 100bb30: 21400236 bltu r4,r5,100bb3c + 100bb34: 2149c83a sub r4,r4,r5 + 100bb38: 1886b03a or r3,r3,r2 + 100bb3c: 1004d07a srli r2,r2,1 + 100bb40: 280ad07a srli r5,r5,1 + 100bb44: 103ffa1e bne r2,zero,100bb30 + 100bb48: 30000226 beq r6,zero,100bb54 + 100bb4c: 2005883a mov r2,r4 + 100bb50: f800283a ret + 100bb54: 1809883a mov r4,r3 + 100bb58: 2005883a mov r2,r4 + 100bb5c: f800283a ret + 100bb60: 0007883a mov r3,zero + 100bb64: 003ff806 br 100bb48 + 100bb68: 00800044 movi r2,1 + 100bb6c: 0007883a mov r3,zero + 100bb70: 003fef06 br 100bb30 + +0100bb74 <__divsi3>: + 100bb74: defffe04 addi sp,sp,-8 + 100bb78: dc000015 stw r16,0(sp) + 100bb7c: dfc00115 stw ra,4(sp) + 100bb80: 0021883a mov r16,zero + 100bb84: 20000c16 blt r4,zero,100bbb8 <__divsi3+0x44> + 100bb88: 000d883a mov r6,zero + 100bb8c: 28000e16 blt r5,zero,100bbc8 <__divsi3+0x54> + 100bb90: 100baf80 call 100baf8 + 100bb94: 1007883a mov r3,r2 + 100bb98: 8005003a cmpeq r2,r16,zero + 100bb9c: 1000011e bne r2,zero,100bba4 <__divsi3+0x30> + 100bba0: 00c7c83a sub r3,zero,r3 + 100bba4: 1805883a mov r2,r3 + 100bba8: dfc00117 ldw ra,4(sp) + 100bbac: dc000017 ldw r16,0(sp) + 100bbb0: dec00204 addi sp,sp,8 + 100bbb4: f800283a ret + 100bbb8: 0109c83a sub r4,zero,r4 + 100bbbc: 04000044 movi r16,1 + 100bbc0: 000d883a mov r6,zero + 100bbc4: 283ff20e bge r5,zero,100bb90 <__divsi3+0x1c> + 100bbc8: 014bc83a sub r5,zero,r5 + 100bbcc: 8021003a cmpeq r16,r16,zero + 100bbd0: 003fef06 br 100bb90 <__divsi3+0x1c> + +0100bbd4 <__modsi3>: + 100bbd4: deffff04 addi sp,sp,-4 + 100bbd8: dfc00015 stw ra,0(sp) + 100bbdc: 01800044 movi r6,1 + 100bbe0: 2807883a mov r3,r5 + 100bbe4: 20000416 blt r4,zero,100bbf8 <__modsi3+0x24> + 100bbe8: 28000c16 blt r5,zero,100bc1c <__modsi3+0x48> + 100bbec: dfc00017 ldw ra,0(sp) + 100bbf0: dec00104 addi sp,sp,4 + 100bbf4: 100baf81 jmpi 100baf8 + 100bbf8: 0109c83a sub r4,zero,r4 + 100bbfc: 28000b16 blt r5,zero,100bc2c <__modsi3+0x58> + 100bc00: 180b883a mov r5,r3 + 100bc04: 01800044 movi r6,1 + 100bc08: 100baf80 call 100baf8 + 100bc0c: 0085c83a sub r2,zero,r2 + 100bc10: dfc00017 ldw ra,0(sp) + 100bc14: dec00104 addi sp,sp,4 + 100bc18: f800283a ret + 100bc1c: 014bc83a sub r5,zero,r5 + 100bc20: dfc00017 ldw ra,0(sp) + 100bc24: dec00104 addi sp,sp,4 + 100bc28: 100baf81 jmpi 100baf8 + 100bc2c: 0147c83a sub r3,zero,r5 + 100bc30: 003ff306 br 100bc00 <__modsi3+0x2c> + +0100bc34 <__udivsi3>: + 100bc34: 000d883a mov r6,zero + 100bc38: 100baf81 jmpi 100baf8 + +0100bc3c <__umodsi3>: + 100bc3c: 01800044 movi r6,1 + 100bc40: 100baf81 jmpi 100baf8 + +0100bc44 <__muldi3>: + 100bc44: 2011883a mov r8,r4 + 100bc48: 427fffcc andi r9,r8,65535 + 100bc4c: 4018d43a srli r12,r8,16 + 100bc50: 32bfffcc andi r10,r6,65535 + 100bc54: 3016d43a srli r11,r6,16 + 100bc58: 4a85383a mul r2,r9,r10 + 100bc5c: 6295383a mul r10,r12,r10 + 100bc60: 4ad3383a mul r9,r9,r11 + 100bc64: 113fffcc andi r4,r2,65535 + 100bc68: 1004d43a srli r2,r2,16 + 100bc6c: 4a93883a add r9,r9,r10 + 100bc70: 3807883a mov r3,r7 + 100bc74: 1245883a add r2,r2,r9 + 100bc78: 280f883a mov r7,r5 + 100bc7c: 180b883a mov r5,r3 + 100bc80: 1006943a slli r3,r2,16 + 100bc84: defffd04 addi sp,sp,-12 + 100bc88: dc800215 stw r18,8(sp) + 100bc8c: 1907883a add r3,r3,r4 + 100bc90: dc400115 stw r17,4(sp) + 100bc94: dc000015 stw r16,0(sp) + 100bc98: 4165383a mul r18,r8,r5 + 100bc9c: 31e3383a mul r17,r6,r7 + 100bca0: 1012d43a srli r9,r2,16 + 100bca4: 62d9383a mul r12,r12,r11 + 100bca8: 181f883a mov r15,r3 + 100bcac: 1280022e bgeu r2,r10,100bcb8 <__muldi3+0x74> + 100bcb0: 00800074 movhi r2,1 + 100bcb4: 6099883a add r12,r12,r2 + 100bcb8: 624d883a add r6,r12,r9 + 100bcbc: 9187883a add r3,r18,r6 + 100bcc0: 88c7883a add r3,r17,r3 + 100bcc4: 7805883a mov r2,r15 + 100bcc8: dc800217 ldw r18,8(sp) + 100bccc: dc400117 ldw r17,4(sp) + 100bcd0: dc000017 ldw r16,0(sp) + 100bcd4: dec00304 addi sp,sp,12 + 100bcd8: f800283a ret + +0100bcdc <__clzsi2>: + 100bcdc: 00bfffd4 movui r2,65535 + 100bce0: 11000e36 bltu r2,r4,100bd1c <__clzsi2+0x40> + 100bce4: 00803fc4 movi r2,255 + 100bce8: 01400204 movi r5,8 + 100bcec: 0007883a mov r3,zero + 100bcf0: 11001036 bltu r2,r4,100bd34 <__clzsi2+0x58> + 100bcf4: 000b883a mov r5,zero + 100bcf8: 20c6d83a srl r3,r4,r3 + 100bcfc: 008040b4 movhi r2,258 + 100bd00: 10a3ee04 addi r2,r2,-28744 + 100bd04: 1887883a add r3,r3,r2 + 100bd08: 18800003 ldbu r2,0(r3) + 100bd0c: 00c00804 movi r3,32 + 100bd10: 2885883a add r2,r5,r2 + 100bd14: 1885c83a sub r2,r3,r2 + 100bd18: f800283a ret + 100bd1c: 01400404 movi r5,16 + 100bd20: 00804034 movhi r2,256 + 100bd24: 10bfffc4 addi r2,r2,-1 + 100bd28: 2807883a mov r3,r5 + 100bd2c: 113ff22e bgeu r2,r4,100bcf8 <__clzsi2+0x1c> + 100bd30: 01400604 movi r5,24 + 100bd34: 2807883a mov r3,r5 + 100bd38: 20c6d83a srl r3,r4,r3 + 100bd3c: 008040b4 movhi r2,258 + 100bd40: 10a3ee04 addi r2,r2,-28744 + 100bd44: 1887883a add r3,r3,r2 + 100bd48: 18800003 ldbu r2,0(r3) + 100bd4c: 00c00804 movi r3,32 + 100bd50: 2885883a add r2,r5,r2 + 100bd54: 1885c83a sub r2,r3,r2 + 100bd58: f800283a ret + +0100bd5c <__pack_d>: + 100bd5c: 20c00017 ldw r3,0(r4) + 100bd60: defffd04 addi sp,sp,-12 + 100bd64: dc000015 stw r16,0(sp) + 100bd68: dc800215 stw r18,8(sp) + 100bd6c: dc400115 stw r17,4(sp) + 100bd70: 00800044 movi r2,1 + 100bd74: 22000317 ldw r8,12(r4) + 100bd78: 001f883a mov r15,zero + 100bd7c: 22400417 ldw r9,16(r4) + 100bd80: 24000117 ldw r16,4(r4) + 100bd84: 10c0552e bgeu r2,r3,100bedc <__pack_d+0x180> + 100bd88: 00800104 movi r2,4 + 100bd8c: 18804f26 beq r3,r2,100becc <__pack_d+0x170> + 100bd90: 00800084 movi r2,2 + 100bd94: 18800226 beq r3,r2,100bda0 <__pack_d+0x44> + 100bd98: 4244b03a or r2,r8,r9 + 100bd9c: 10001a1e bne r2,zero,100be08 <__pack_d+0xac> + 100bda0: 000d883a mov r6,zero + 100bda4: 000f883a mov r7,zero + 100bda8: 0011883a mov r8,zero + 100bdac: 00800434 movhi r2,16 + 100bdb0: 10bfffc4 addi r2,r2,-1 + 100bdb4: 301d883a mov r14,r6 + 100bdb8: 3884703a and r2,r7,r2 + 100bdbc: 400a953a slli r5,r8,20 + 100bdc0: 79bffc2c andhi r6,r15,65520 + 100bdc4: 308cb03a or r6,r6,r2 + 100bdc8: 00e00434 movhi r3,32784 + 100bdcc: 18ffffc4 addi r3,r3,-1 + 100bdd0: 800497fa slli r2,r16,31 + 100bdd4: 30c6703a and r3,r6,r3 + 100bdd8: 1946b03a or r3,r3,r5 + 100bddc: 01600034 movhi r5,32768 + 100bde0: 297fffc4 addi r5,r5,-1 + 100bde4: 194a703a and r5,r3,r5 + 100bde8: 288ab03a or r5,r5,r2 + 100bdec: 2807883a mov r3,r5 + 100bdf0: 7005883a mov r2,r14 + 100bdf4: dc800217 ldw r18,8(sp) + 100bdf8: dc400117 ldw r17,4(sp) + 100bdfc: dc000017 ldw r16,0(sp) + 100be00: dec00304 addi sp,sp,12 + 100be04: f800283a ret + 100be08: 21000217 ldw r4,8(r4) + 100be0c: 00bf0084 movi r2,-1022 + 100be10: 20803f16 blt r4,r2,100bf10 <__pack_d+0x1b4> + 100be14: 0080ffc4 movi r2,1023 + 100be18: 11002c16 blt r2,r4,100becc <__pack_d+0x170> + 100be1c: 00803fc4 movi r2,255 + 100be20: 408c703a and r6,r8,r2 + 100be24: 00802004 movi r2,128 + 100be28: 0007883a mov r3,zero + 100be2c: 000f883a mov r7,zero + 100be30: 2280ffc4 addi r10,r4,1023 + 100be34: 30801e26 beq r6,r2,100beb0 <__pack_d+0x154> + 100be38: 00801fc4 movi r2,127 + 100be3c: 4089883a add r4,r8,r2 + 100be40: 220d803a cmpltu r6,r4,r8 + 100be44: 324d883a add r6,r6,r9 + 100be48: 2011883a mov r8,r4 + 100be4c: 3013883a mov r9,r6 + 100be50: 00880034 movhi r2,8192 + 100be54: 10bfffc4 addi r2,r2,-1 + 100be58: 12400d36 bltu r2,r9,100be90 <__pack_d+0x134> + 100be5c: 4804963a slli r2,r9,24 + 100be60: 400cd23a srli r6,r8,8 + 100be64: 480ed23a srli r7,r9,8 + 100be68: 013fffc4 movi r4,-1 + 100be6c: 118cb03a or r6,r2,r6 + 100be70: 01400434 movhi r5,16 + 100be74: 297fffc4 addi r5,r5,-1 + 100be78: 3104703a and r2,r6,r4 + 100be7c: 3946703a and r3,r7,r5 + 100be80: 5201ffcc andi r8,r10,2047 + 100be84: 100d883a mov r6,r2 + 100be88: 180f883a mov r7,r3 + 100be8c: 003fc706 br 100bdac <__pack_d+0x50> + 100be90: 480897fa slli r4,r9,31 + 100be94: 4004d07a srli r2,r8,1 + 100be98: 4806d07a srli r3,r9,1 + 100be9c: 52800044 addi r10,r10,1 + 100bea0: 2084b03a or r2,r4,r2 + 100bea4: 1011883a mov r8,r2 + 100bea8: 1813883a mov r9,r3 + 100beac: 003feb06 br 100be5c <__pack_d+0x100> + 100beb0: 383fe11e bne r7,zero,100be38 <__pack_d+0xdc> + 100beb4: 01004004 movi r4,256 + 100beb8: 4104703a and r2,r8,r4 + 100bebc: 10c4b03a or r2,r2,r3 + 100bec0: 103fe326 beq r2,zero,100be50 <__pack_d+0xf4> + 100bec4: 3005883a mov r2,r6 + 100bec8: 003fdc06 br 100be3c <__pack_d+0xe0> + 100becc: 000d883a mov r6,zero + 100bed0: 000f883a mov r7,zero + 100bed4: 0201ffc4 movi r8,2047 + 100bed8: 003fb406 br 100bdac <__pack_d+0x50> + 100bedc: 0005883a mov r2,zero + 100bee0: 00c00234 movhi r3,8 + 100bee4: 408cb03a or r6,r8,r2 + 100bee8: 48ceb03a or r7,r9,r3 + 100beec: 013fffc4 movi r4,-1 + 100bef0: 01400434 movhi r5,16 + 100bef4: 297fffc4 addi r5,r5,-1 + 100bef8: 3104703a and r2,r6,r4 + 100befc: 3946703a and r3,r7,r5 + 100bf00: 100d883a mov r6,r2 + 100bf04: 180f883a mov r7,r3 + 100bf08: 0201ffc4 movi r8,2047 + 100bf0c: 003fa706 br 100bdac <__pack_d+0x50> + 100bf10: 1109c83a sub r4,r2,r4 + 100bf14: 00800e04 movi r2,56 + 100bf18: 11004316 blt r2,r4,100c028 <__pack_d+0x2cc> + 100bf1c: 21fff804 addi r7,r4,-32 + 100bf20: 38004516 blt r7,zero,100c038 <__pack_d+0x2dc> + 100bf24: 49d8d83a srl r12,r9,r7 + 100bf28: 001b883a mov r13,zero + 100bf2c: 0023883a mov r17,zero + 100bf30: 01400044 movi r5,1 + 100bf34: 0025883a mov r18,zero + 100bf38: 38004716 blt r7,zero,100c058 <__pack_d+0x2fc> + 100bf3c: 29d6983a sll r11,r5,r7 + 100bf40: 0015883a mov r10,zero + 100bf44: 00bfffc4 movi r2,-1 + 100bf48: 5089883a add r4,r10,r2 + 100bf4c: 588b883a add r5,r11,r2 + 100bf50: 228d803a cmpltu r6,r4,r10 + 100bf54: 314b883a add r5,r6,r5 + 100bf58: 4104703a and r2,r8,r4 + 100bf5c: 4946703a and r3,r9,r5 + 100bf60: 10c4b03a or r2,r2,r3 + 100bf64: 10000226 beq r2,zero,100bf70 <__pack_d+0x214> + 100bf68: 04400044 movi r17,1 + 100bf6c: 0025883a mov r18,zero + 100bf70: 00803fc4 movi r2,255 + 100bf74: 644eb03a or r7,r12,r17 + 100bf78: 3892703a and r9,r7,r2 + 100bf7c: 00802004 movi r2,128 + 100bf80: 6c90b03a or r8,r13,r18 + 100bf84: 0015883a mov r10,zero + 100bf88: 48801626 beq r9,r2,100bfe4 <__pack_d+0x288> + 100bf8c: 01001fc4 movi r4,127 + 100bf90: 3905883a add r2,r7,r4 + 100bf94: 11cd803a cmpltu r6,r2,r7 + 100bf98: 320d883a add r6,r6,r8 + 100bf9c: 100f883a mov r7,r2 + 100bfa0: 00840034 movhi r2,4096 + 100bfa4: 10bfffc4 addi r2,r2,-1 + 100bfa8: 3011883a mov r8,r6 + 100bfac: 0007883a mov r3,zero + 100bfb0: 11801b36 bltu r2,r6,100c020 <__pack_d+0x2c4> + 100bfb4: 4004963a slli r2,r8,24 + 100bfb8: 3808d23a srli r4,r7,8 + 100bfbc: 400ad23a srli r5,r8,8 + 100bfc0: 1813883a mov r9,r3 + 100bfc4: 1108b03a or r4,r2,r4 + 100bfc8: 00bfffc4 movi r2,-1 + 100bfcc: 00c00434 movhi r3,16 + 100bfd0: 18ffffc4 addi r3,r3,-1 + 100bfd4: 208c703a and r6,r4,r2 + 100bfd8: 28ce703a and r7,r5,r3 + 100bfdc: 4a01ffcc andi r8,r9,2047 + 100bfe0: 003f7206 br 100bdac <__pack_d+0x50> + 100bfe4: 503fe91e bne r10,zero,100bf8c <__pack_d+0x230> + 100bfe8: 01004004 movi r4,256 + 100bfec: 3904703a and r2,r7,r4 + 100bff0: 0007883a mov r3,zero + 100bff4: 10c4b03a or r2,r2,r3 + 100bff8: 10000626 beq r2,zero,100c014 <__pack_d+0x2b8> + 100bffc: 3a45883a add r2,r7,r9 + 100c000: 11cd803a cmpltu r6,r2,r7 + 100c004: 320d883a add r6,r6,r8 + 100c008: 100f883a mov r7,r2 + 100c00c: 3011883a mov r8,r6 + 100c010: 0007883a mov r3,zero + 100c014: 00840034 movhi r2,4096 + 100c018: 10bfffc4 addi r2,r2,-1 + 100c01c: 123fe52e bgeu r2,r8,100bfb4 <__pack_d+0x258> + 100c020: 00c00044 movi r3,1 + 100c024: 003fe306 br 100bfb4 <__pack_d+0x258> + 100c028: 0009883a mov r4,zero + 100c02c: 0013883a mov r9,zero + 100c030: 000b883a mov r5,zero + 100c034: 003fe406 br 100bfc8 <__pack_d+0x26c> + 100c038: 4a47883a add r3,r9,r9 + 100c03c: 008007c4 movi r2,31 + 100c040: 1105c83a sub r2,r2,r4 + 100c044: 1886983a sll r3,r3,r2 + 100c048: 4118d83a srl r12,r8,r4 + 100c04c: 491ad83a srl r13,r9,r4 + 100c050: 1b18b03a or r12,r3,r12 + 100c054: 003fb506 br 100bf2c <__pack_d+0x1d0> + 100c058: 2806d07a srli r3,r5,1 + 100c05c: 008007c4 movi r2,31 + 100c060: 1105c83a sub r2,r2,r4 + 100c064: 1896d83a srl r11,r3,r2 + 100c068: 2914983a sll r10,r5,r4 + 100c06c: 003fb506 br 100bf44 <__pack_d+0x1e8> + +0100c070 <__unpack_d>: + 100c070: 20c00117 ldw r3,4(r4) + 100c074: 22400017 ldw r9,0(r4) + 100c078: 00800434 movhi r2,16 + 100c07c: 10bfffc4 addi r2,r2,-1 + 100c080: 1808d53a srli r4,r3,20 + 100c084: 180cd7fa srli r6,r3,31 + 100c088: 1894703a and r10,r3,r2 + 100c08c: 2201ffcc andi r8,r4,2047 + 100c090: 281b883a mov r13,r5 + 100c094: 4817883a mov r11,r9 + 100c098: 29800115 stw r6,4(r5) + 100c09c: 5019883a mov r12,r10 + 100c0a0: 40001e1e bne r8,zero,100c11c <__unpack_d+0xac> + 100c0a4: 4a84b03a or r2,r9,r10 + 100c0a8: 10001926 beq r2,zero,100c110 <__unpack_d+0xa0> + 100c0ac: 4804d63a srli r2,r9,24 + 100c0b0: 500c923a slli r6,r10,8 + 100c0b4: 013f0084 movi r4,-1022 + 100c0b8: 00c40034 movhi r3,4096 + 100c0bc: 18ffffc4 addi r3,r3,-1 + 100c0c0: 118cb03a or r6,r2,r6 + 100c0c4: 008000c4 movi r2,3 + 100c0c8: 480a923a slli r5,r9,8 + 100c0cc: 68800015 stw r2,0(r13) + 100c0d0: 69000215 stw r4,8(r13) + 100c0d4: 19800b36 bltu r3,r6,100c104 <__unpack_d+0x94> + 100c0d8: 200f883a mov r7,r4 + 100c0dc: 1811883a mov r8,r3 + 100c0e0: 2945883a add r2,r5,r5 + 100c0e4: 1149803a cmpltu r4,r2,r5 + 100c0e8: 3187883a add r3,r6,r6 + 100c0ec: 20c9883a add r4,r4,r3 + 100c0f0: 100b883a mov r5,r2 + 100c0f4: 200d883a mov r6,r4 + 100c0f8: 39ffffc4 addi r7,r7,-1 + 100c0fc: 413ff82e bgeu r8,r4,100c0e0 <__unpack_d+0x70> + 100c100: 69c00215 stw r7,8(r13) + 100c104: 69800415 stw r6,16(r13) + 100c108: 69400315 stw r5,12(r13) + 100c10c: f800283a ret + 100c110: 00800084 movi r2,2 + 100c114: 28800015 stw r2,0(r5) + 100c118: f800283a ret + 100c11c: 0081ffc4 movi r2,2047 + 100c120: 40800f26 beq r8,r2,100c160 <__unpack_d+0xf0> + 100c124: 480cd63a srli r6,r9,24 + 100c128: 5006923a slli r3,r10,8 + 100c12c: 4804923a slli r2,r9,8 + 100c130: 0009883a mov r4,zero + 100c134: 30c6b03a or r3,r6,r3 + 100c138: 01440034 movhi r5,4096 + 100c13c: 110cb03a or r6,r2,r4 + 100c140: 423f0044 addi r8,r8,-1023 + 100c144: 194eb03a or r7,r3,r5 + 100c148: 008000c4 movi r2,3 + 100c14c: 69c00415 stw r7,16(r13) + 100c150: 6a000215 stw r8,8(r13) + 100c154: 68800015 stw r2,0(r13) + 100c158: 69800315 stw r6,12(r13) + 100c15c: f800283a ret + 100c160: 4a84b03a or r2,r9,r10 + 100c164: 1000031e bne r2,zero,100c174 <__unpack_d+0x104> + 100c168: 00800104 movi r2,4 + 100c16c: 28800015 stw r2,0(r5) + 100c170: f800283a ret + 100c174: 0009883a mov r4,zero + 100c178: 01400234 movhi r5,8 + 100c17c: 4904703a and r2,r9,r4 + 100c180: 5146703a and r3,r10,r5 + 100c184: 10c4b03a or r2,r2,r3 + 100c188: 10000526 beq r2,zero,100c1a0 <__unpack_d+0x130> + 100c18c: 00800044 movi r2,1 + 100c190: 68800015 stw r2,0(r13) + 100c194: 6b000415 stw r12,16(r13) + 100c198: 6ac00315 stw r11,12(r13) + 100c19c: f800283a ret + 100c1a0: 68000015 stw zero,0(r13) + 100c1a4: 003ffb06 br 100c194 <__unpack_d+0x124> + +0100c1a8 <__fpcmp_parts_d>: + 100c1a8: 21800017 ldw r6,0(r4) + 100c1ac: 00c00044 movi r3,1 + 100c1b0: 19800a2e bgeu r3,r6,100c1dc <__fpcmp_parts_d+0x34> + 100c1b4: 28800017 ldw r2,0(r5) + 100c1b8: 1880082e bgeu r3,r2,100c1dc <__fpcmp_parts_d+0x34> + 100c1bc: 00c00104 movi r3,4 + 100c1c0: 30c02626 beq r6,r3,100c25c <__fpcmp_parts_d+0xb4> + 100c1c4: 10c02226 beq r2,r3,100c250 <__fpcmp_parts_d+0xa8> + 100c1c8: 00c00084 movi r3,2 + 100c1cc: 30c00526 beq r6,r3,100c1e4 <__fpcmp_parts_d+0x3c> + 100c1d0: 10c0071e bne r2,r3,100c1f0 <__fpcmp_parts_d+0x48> + 100c1d4: 20800117 ldw r2,4(r4) + 100c1d8: 1000091e bne r2,zero,100c200 <__fpcmp_parts_d+0x58> + 100c1dc: 00800044 movi r2,1 + 100c1e0: f800283a ret + 100c1e4: 10c01a1e bne r2,r3,100c250 <__fpcmp_parts_d+0xa8> + 100c1e8: 0005883a mov r2,zero + 100c1ec: f800283a ret + 100c1f0: 22000117 ldw r8,4(r4) + 100c1f4: 28800117 ldw r2,4(r5) + 100c1f8: 40800326 beq r8,r2,100c208 <__fpcmp_parts_d+0x60> + 100c1fc: 403ff726 beq r8,zero,100c1dc <__fpcmp_parts_d+0x34> + 100c200: 00bfffc4 movi r2,-1 + 100c204: f800283a ret + 100c208: 20c00217 ldw r3,8(r4) + 100c20c: 28800217 ldw r2,8(r5) + 100c210: 10fffa16 blt r2,r3,100c1fc <__fpcmp_parts_d+0x54> + 100c214: 18800916 blt r3,r2,100c23c <__fpcmp_parts_d+0x94> + 100c218: 21c00417 ldw r7,16(r4) + 100c21c: 28c00417 ldw r3,16(r5) + 100c220: 21800317 ldw r6,12(r4) + 100c224: 28800317 ldw r2,12(r5) + 100c228: 19fff436 bltu r3,r7,100c1fc <__fpcmp_parts_d+0x54> + 100c22c: 38c00526 beq r7,r3,100c244 <__fpcmp_parts_d+0x9c> + 100c230: 38c00236 bltu r7,r3,100c23c <__fpcmp_parts_d+0x94> + 100c234: 19ffec1e bne r3,r7,100c1e8 <__fpcmp_parts_d+0x40> + 100c238: 30bfeb2e bgeu r6,r2,100c1e8 <__fpcmp_parts_d+0x40> + 100c23c: 403fe71e bne r8,zero,100c1dc <__fpcmp_parts_d+0x34> + 100c240: 003fef06 br 100c200 <__fpcmp_parts_d+0x58> + 100c244: 11bffa2e bgeu r2,r6,100c230 <__fpcmp_parts_d+0x88> + 100c248: 403fe426 beq r8,zero,100c1dc <__fpcmp_parts_d+0x34> + 100c24c: 003fec06 br 100c200 <__fpcmp_parts_d+0x58> + 100c250: 28800117 ldw r2,4(r5) + 100c254: 103fe11e bne r2,zero,100c1dc <__fpcmp_parts_d+0x34> + 100c258: 003fe906 br 100c200 <__fpcmp_parts_d+0x58> + 100c25c: 11bfdd1e bne r2,r6,100c1d4 <__fpcmp_parts_d+0x2c> + 100c260: 28c00117 ldw r3,4(r5) + 100c264: 20800117 ldw r2,4(r4) + 100c268: 1885c83a sub r2,r3,r2 + 100c26c: f800283a ret + +0100c270 : + * + * ALT_CLOSE is mapped onto the close() system call in alt_syscall.h + */ + +int ALT_CLOSE (int fildes) +{ + 100c270: defff804 addi sp,sp,-32 + 100c274: dfc00715 stw ra,28(sp) + 100c278: df000615 stw fp,24(sp) + 100c27c: df000604 addi fp,sp,24 + 100c280: e13ffc15 stw r4,-16(fp) + * A common error case is that when the file descriptor was created, the call + * to open() failed resulting in a negative file descriptor. This is trapped + * below so that we don't try and process an invalid file descriptor. + */ + + fd = (fildes < 0) ? NULL : &alt_fd_list[fildes]; + 100c284: e0bffc17 ldw r2,-16(fp) + 100c288: 1004803a cmplt r2,r2,zero + 100c28c: 1000081e bne r2,zero,100c2b0 + 100c290: e0bffc17 ldw r2,-16(fp) + 100c294: 10800324 muli r2,r2,12 + 100c298: 1007883a mov r3,r2 + 100c29c: 008040b4 movhi r2,258 + 100c2a0: 10a69f04 addi r2,r2,-25988 + 100c2a4: 1887883a add r3,r3,r2 + 100c2a8: e0ffff15 stw r3,-4(fp) + 100c2ac: 00000106 br 100c2b4 + 100c2b0: e03fff15 stw zero,-4(fp) + 100c2b4: e0bfff17 ldw r2,-4(fp) + 100c2b8: e0bffb15 stw r2,-20(fp) + + if (fd) + 100c2bc: e0bffb17 ldw r2,-20(fp) + 100c2c0: 1005003a cmpeq r2,r2,zero + 100c2c4: 10001d1e bne r2,zero,100c33c + /* + * If the associated file system/device has a close function, call it so + * that any necessary cleanup code can run. + */ + + rval = (fd->dev->close) ? fd->dev->close(fd) : 0; + 100c2c8: e0bffb17 ldw r2,-20(fp) + 100c2cc: 10800017 ldw r2,0(r2) + 100c2d0: 10800417 ldw r2,16(r2) + 100c2d4: 1005003a cmpeq r2,r2,zero + 100c2d8: 1000071e bne r2,zero,100c2f8 + 100c2dc: e0bffb17 ldw r2,-20(fp) + 100c2e0: 10800017 ldw r2,0(r2) + 100c2e4: 10800417 ldw r2,16(r2) + 100c2e8: e13ffb17 ldw r4,-20(fp) + 100c2ec: 103ee83a callr r2 + 100c2f0: e0bffe15 stw r2,-8(fp) + 100c2f4: 00000106 br 100c2fc + 100c2f8: e03ffe15 stw zero,-8(fp) + 100c2fc: e0bffe17 ldw r2,-8(fp) + 100c300: e0bffa15 stw r2,-24(fp) + + /* Free the file descriptor structure and return. */ + + alt_release_fd (fildes); + 100c304: e13ffc17 ldw r4,-16(fp) + 100c308: 100ccfc0 call 100ccfc + if (rval < 0) + 100c30c: e0bffa17 ldw r2,-24(fp) + 100c310: 1004403a cmpge r2,r2,zero + 100c314: 1000071e bne r2,zero,100c334 + { + ALT_ERRNO = -rval; + 100c318: 100c36c0 call 100c36c + 100c31c: e0fffa17 ldw r3,-24(fp) + 100c320: 00c7c83a sub r3,zero,r3 + 100c324: 10c00015 stw r3,0(r2) + return -1; + 100c328: 00bfffc4 movi r2,-1 + 100c32c: e0bffd15 stw r2,-12(fp) + 100c330: 00000806 br 100c354 + } + return 0; + 100c334: e03ffd15 stw zero,-12(fp) + 100c338: 00000606 br 100c354 + } + else + { + ALT_ERRNO = EBADFD; + 100c33c: 100c36c0 call 100c36c + 100c340: 1007883a mov r3,r2 + 100c344: 00801444 movi r2,81 + 100c348: 18800015 stw r2,0(r3) + return -1; + 100c34c: 00bfffc4 movi r2,-1 + 100c350: e0bffd15 stw r2,-12(fp) + 100c354: e0bffd17 ldw r2,-12(fp) + } +} + 100c358: e037883a mov sp,fp + 100c35c: dfc00117 ldw ra,4(sp) + 100c360: df000017 ldw fp,0(sp) + 100c364: dec00204 addi sp,sp,8 + 100c368: f800283a ret + +0100c36c : +#undef errno + +extern int errno; + +static ALT_INLINE int* alt_get_errno(void) +{ + 100c36c: defffd04 addi sp,sp,-12 + 100c370: dfc00215 stw ra,8(sp) + 100c374: df000115 stw fp,4(sp) + 100c378: df000104 addi fp,sp,4 + return ((alt_errno) ? alt_errno() : &errno); + 100c37c: 008040b4 movhi r2,258 + 100c380: 10aba104 addi r2,r2,-20860 + 100c384: 10800017 ldw r2,0(r2) + 100c388: 1005003a cmpeq r2,r2,zero + 100c38c: 1000061e bne r2,zero,100c3a8 + 100c390: 008040b4 movhi r2,258 + 100c394: 10aba104 addi r2,r2,-20860 + 100c398: 10800017 ldw r2,0(r2) + 100c39c: 103ee83a callr r2 + 100c3a0: e0bfff15 stw r2,-4(fp) + 100c3a4: 00000306 br 100c3b4 + 100c3a8: 008040b4 movhi r2,258 + 100c3ac: 10b30404 addi r2,r2,-13296 + 100c3b0: e0bfff15 stw r2,-4(fp) + 100c3b4: e0bfff17 ldw r2,-4(fp) +} + 100c3b8: e037883a mov sp,fp + 100c3bc: dfc00117 ldw ra,4(sp) + 100c3c0: df000017 ldw fp,0(sp) + 100c3c4: dec00204 addi sp,sp,8 + 100c3c8: f800283a ret + +0100c3cc : + * by the alt_dev_null device. It simple discards all data passed to it, and + * indicates that the data has been successfully transmitted. + */ + +static int alt_dev_null_write (alt_fd* fd, const char* ptr, int len) +{ + 100c3cc: defffc04 addi sp,sp,-16 + 100c3d0: df000315 stw fp,12(sp) + 100c3d4: df000304 addi fp,sp,12 + 100c3d8: e13ffd15 stw r4,-12(fp) + 100c3dc: e17ffe15 stw r5,-8(fp) + 100c3e0: e1bfff15 stw r6,-4(fp) + return len; + 100c3e4: e0bfff17 ldw r2,-4(fp) +} + 100c3e8: e037883a mov sp,fp + 100c3ec: df000017 ldw fp,0(sp) + 100c3f0: dec00104 addi sp,sp,4 + 100c3f4: f800283a ret + +0100c3f8 : + +/* + * Routine called on exit. + */ +static ALT_ALWAYS_INLINE void alt_sim_halt(int exit_code) +{ + 100c3f8: defffd04 addi sp,sp,-12 + 100c3fc: df000215 stw fp,8(sp) + 100c400: df000204 addi fp,sp,8 + 100c404: e13fff15 stw r4,-4(fp) + int r2 = exit_code; + 100c408: e0bfff17 ldw r2,-4(fp) + 100c40c: e0bffe15 stw r2,-8(fp) + __asm__ volatile ("\n0:\n\taddi %0,%0, -1\n\tbgt %0,zero,0b" : : "r" (ALT_CPU_FREQ/100) ); /* Delay for >30ms */ + + __asm__ volatile ("break 2" : : "D02"(r2), "D03"(r3) ALT_GMON_DATA ); + +#else /* !DEBUG_STUB */ + if (r2) { + 100c410: e0bffe17 ldw r2,-8(fp) + 100c414: 1005003a cmpeq r2,r2,zero + 100c418: 1000021e bne r2,zero,100c424 + ALT_SIM_FAIL(); + 100c41c: 002af070 cmpltui zero,zero,43969 + 100c420: 00000106 br 100c428 + } else { + ALT_SIM_PASS(); + 100c424: 002af0b0 cmpltui zero,zero,43970 + } +#endif /* DEBUG_STUB */ +} + 100c428: e037883a mov sp,fp + 100c42c: df000017 ldw fp,0(sp) + 100c430: dec00104 addi sp,sp,4 + 100c434: f800283a ret + +0100c438 <_exit>: + * + * ALT_EXIT is mapped onto the _exit() system call in alt_syscall.h + */ + +void ALT_EXIT (int exit_code) +{ + 100c438: defffd04 addi sp,sp,-12 + 100c43c: dfc00215 stw ra,8(sp) + 100c440: df000115 stw fp,4(sp) + 100c444: df000104 addi fp,sp,4 + 100c448: e13fff15 stw r4,-4(fp) + ALT_LOG_PRINT_BOOT("[alt_exit.c] Entering _exit() function.\r\n"); + ALT_LOG_PRINT_BOOT("[alt_exit.c] Exit code from main was %d.\r\n",exit_code); + /* Stop all other threads */ + + ALT_LOG_PRINT_BOOT("[alt_exit.c] Calling ALT_OS_STOP().\r\n"); + ALT_OS_STOP(); + 100c44c: 008040b4 movhi r2,258 + 100c450: 10b31044 addi r2,r2,-13247 + 100c454: 10000005 stb zero,0(r2) + + /* Provide notification to the simulator that we've stopped */ + + ALT_LOG_PRINT_BOOT("[alt_exit.c] Calling ALT_SIM_HALT().\r\n"); + ALT_SIM_HALT(exit_code); + 100c458: e13fff17 ldw r4,-4(fp) + 100c45c: 100c3f80 call 100c3f8 + + /* spin forever, since there's no where to go back to */ + + ALT_LOG_PRINT_BOOT("[alt_exit.c] Spinning forever.\r\n"); + while (1); + 100c460: 003fff06 br 100c460 <_exit+0x28> + +0100c464 : +} + +#else /* !ALT_USE_DIRECT_DRIVERS */ + +int ALT_FSTAT (int file, struct stat *st) +{ + 100c464: defff904 addi sp,sp,-28 + 100c468: dfc00615 stw ra,24(sp) + 100c46c: df000515 stw fp,20(sp) + 100c470: df000504 addi fp,sp,20 + 100c474: e13ffc15 stw r4,-16(fp) + 100c478: e17ffd15 stw r5,-12(fp) + * A common error case is that when the file descriptor was created, the call + * to open() failed resulting in a negative file descriptor. This is trapped + * below so that we don't try and process an invalid file descriptor. + */ + + fd = (file < 0) ? NULL : &alt_fd_list[file]; + 100c47c: e0bffc17 ldw r2,-16(fp) + 100c480: 1004803a cmplt r2,r2,zero + 100c484: 1000081e bne r2,zero,100c4a8 + 100c488: e0bffc17 ldw r2,-16(fp) + 100c48c: 10800324 muli r2,r2,12 + 100c490: 1007883a mov r3,r2 + 100c494: 008040b4 movhi r2,258 + 100c498: 10a69f04 addi r2,r2,-25988 + 100c49c: 1887883a add r3,r3,r2 + 100c4a0: e0ffff15 stw r3,-4(fp) + 100c4a4: 00000106 br 100c4ac + 100c4a8: e03fff15 stw zero,-4(fp) + 100c4ac: e0bfff17 ldw r2,-4(fp) + 100c4b0: e0bffb15 stw r2,-20(fp) + + if (fd) + 100c4b4: e0bffb17 ldw r2,-20(fp) + 100c4b8: 1005003a cmpeq r2,r2,zero + 100c4bc: 1000121e bne r2,zero,100c508 + { + /* Call the drivers fstat() function to fill out the "st" structure. */ + + if (fd->dev->fstat) + 100c4c0: e0bffb17 ldw r2,-20(fp) + 100c4c4: 10800017 ldw r2,0(r2) + 100c4c8: 10800817 ldw r2,32(r2) + 100c4cc: 1005003a cmpeq r2,r2,zero + 100c4d0: 1000081e bne r2,zero,100c4f4 + { + return fd->dev->fstat(fd, st); + 100c4d4: e0bffb17 ldw r2,-20(fp) + 100c4d8: 10800017 ldw r2,0(r2) + 100c4dc: 10800817 ldw r2,32(r2) + 100c4e0: e13ffb17 ldw r4,-20(fp) + 100c4e4: e17ffd17 ldw r5,-12(fp) + 100c4e8: 103ee83a callr r2 + 100c4ec: e0bffe15 stw r2,-8(fp) + 100c4f0: 00000b06 br 100c520 + * device. + */ + + else + { + st->st_mode = _IFCHR; + 100c4f4: e0fffd17 ldw r3,-12(fp) + 100c4f8: 00880004 movi r2,8192 + 100c4fc: 18800115 stw r2,4(r3) + return 0; + 100c500: e03ffe15 stw zero,-8(fp) + 100c504: 00000606 br 100c520 + } + } + else + { + ALT_ERRNO = EBADFD; + 100c508: 100c5380 call 100c538 + 100c50c: 1007883a mov r3,r2 + 100c510: 00801444 movi r2,81 + 100c514: 18800015 stw r2,0(r3) + return -1; + 100c518: 00bfffc4 movi r2,-1 + 100c51c: e0bffe15 stw r2,-8(fp) + 100c520: e0bffe17 ldw r2,-8(fp) + } +} + 100c524: e037883a mov sp,fp + 100c528: dfc00117 ldw ra,4(sp) + 100c52c: df000017 ldw fp,0(sp) + 100c530: dec00204 addi sp,sp,8 + 100c534: f800283a ret + +0100c538 : +#undef errno + +extern int errno; + +static ALT_INLINE int* alt_get_errno(void) +{ + 100c538: defffd04 addi sp,sp,-12 + 100c53c: dfc00215 stw ra,8(sp) + 100c540: df000115 stw fp,4(sp) + 100c544: df000104 addi fp,sp,4 + return ((alt_errno) ? alt_errno() : &errno); + 100c548: 008040b4 movhi r2,258 + 100c54c: 10aba104 addi r2,r2,-20860 + 100c550: 10800017 ldw r2,0(r2) + 100c554: 1005003a cmpeq r2,r2,zero + 100c558: 1000061e bne r2,zero,100c574 + 100c55c: 008040b4 movhi r2,258 + 100c560: 10aba104 addi r2,r2,-20860 + 100c564: 10800017 ldw r2,0(r2) + 100c568: 103ee83a callr r2 + 100c56c: e0bfff15 stw r2,-4(fp) + 100c570: 00000306 br 100c580 + 100c574: 008040b4 movhi r2,258 + 100c578: 10b30404 addi r2,r2,-13296 + 100c57c: e0bfff15 stw r2,-4(fp) + 100c580: e0bfff17 ldw r2,-4(fp) +} + 100c584: e037883a mov sp,fp + 100c588: dfc00117 ldw ra,4(sp) + 100c58c: df000017 ldw fp,0(sp) + 100c590: dec00204 addi sp,sp,8 + 100c594: f800283a ret + +0100c598 : + * + * ALT_GETPID is mapped onto the getpid() system call in alt_syscall.h + */ + +int ALT_GETPID (void) +{ + 100c598: deffff04 addi sp,sp,-4 + 100c59c: df000015 stw fp,0(sp) + 100c5a0: d839883a mov fp,sp + return 0; + 100c5a4: 0005883a mov r2,zero +} + 100c5a8: e037883a mov sp,fp + 100c5ac: df000017 ldw fp,0(sp) + 100c5b0: dec00104 addi sp,sp,4 + 100c5b4: f800283a ret + +0100c5b8 : + * + * ALT_ISATTY is mapped onto the isatty() system call in alt_syscall.h + */ + +int ALT_ISATTY (int file) +{ + 100c5b8: deffeb04 addi sp,sp,-84 + 100c5bc: dfc01415 stw ra,80(sp) + 100c5c0: df001315 stw fp,76(sp) + 100c5c4: df001304 addi fp,sp,76 + 100c5c8: e13ffd15 stw r4,-12(fp) + * A common error case is that when the file descriptor was created, the call + * to open() failed resulting in a negative file descriptor. This is trapped + * below so that we don't try and process an invalid file descriptor. + */ + + fd = (file < 0) ? NULL : &alt_fd_list[file]; + 100c5cc: e0bffd17 ldw r2,-12(fp) + 100c5d0: 1004803a cmplt r2,r2,zero + 100c5d4: 1000081e bne r2,zero,100c5f8 + 100c5d8: e0bffd17 ldw r2,-12(fp) + 100c5dc: 10800324 muli r2,r2,12 + 100c5e0: 1007883a mov r3,r2 + 100c5e4: 008040b4 movhi r2,258 + 100c5e8: 10a69f04 addi r2,r2,-25988 + 100c5ec: 1887883a add r3,r3,r2 + 100c5f0: e0ffff15 stw r3,-4(fp) + 100c5f4: 00000106 br 100c5fc + 100c5f8: e03fff15 stw zero,-4(fp) + 100c5fc: e0bfff17 ldw r2,-4(fp) + 100c600: e0bfed15 stw r2,-76(fp) + + if (fd) + 100c604: e0bfed17 ldw r2,-76(fp) + 100c608: 1005003a cmpeq r2,r2,zero + 100c60c: 10000f1e bne r2,zero,100c64c + /* + * If a device driver does not provide an fstat() function, then it is + * treated as a terminal device by default. + */ + + if (!fd->dev->fstat) + 100c610: e0bfed17 ldw r2,-76(fp) + 100c614: 10800017 ldw r2,0(r2) + 100c618: 10800817 ldw r2,32(r2) + 100c61c: 1004c03a cmpne r2,r2,zero + 100c620: 1000031e bne r2,zero,100c630 + { + return 1; + 100c624: 00800044 movi r2,1 + 100c628: e0bffe15 stw r2,-8(fp) + 100c62c: 00000c06 br 100c660 + * this is called so that the device can identify itself. + */ + + else + { + fstat (file, &stat); + 100c630: e17fee04 addi r5,fp,-72 + 100c634: e13ffd17 ldw r4,-12(fp) + 100c638: 100c4640 call 100c464 + return (stat.st_mode == _IFCHR) ? 1 : 0; + 100c63c: e0bfef17 ldw r2,-68(fp) + 100c640: 10880020 cmpeqi r2,r2,8192 + 100c644: e0bffe15 stw r2,-8(fp) + 100c648: 00000506 br 100c660 + } + } + else + { + ALT_ERRNO = EBADFD; + 100c64c: 100c6780 call 100c678 + 100c650: 1007883a mov r3,r2 + 100c654: 00801444 movi r2,81 + 100c658: 18800015 stw r2,0(r3) + return 0; + 100c65c: e03ffe15 stw zero,-8(fp) + 100c660: e0bffe17 ldw r2,-8(fp) + } +} + 100c664: e037883a mov sp,fp + 100c668: dfc00117 ldw ra,4(sp) + 100c66c: df000017 ldw fp,0(sp) + 100c670: dec00204 addi sp,sp,8 + 100c674: f800283a ret + +0100c678 : +#undef errno + +extern int errno; + +static ALT_INLINE int* alt_get_errno(void) +{ + 100c678: defffd04 addi sp,sp,-12 + 100c67c: dfc00215 stw ra,8(sp) + 100c680: df000115 stw fp,4(sp) + 100c684: df000104 addi fp,sp,4 + return ((alt_errno) ? alt_errno() : &errno); + 100c688: 008040b4 movhi r2,258 + 100c68c: 10aba104 addi r2,r2,-20860 + 100c690: 10800017 ldw r2,0(r2) + 100c694: 1005003a cmpeq r2,r2,zero + 100c698: 1000061e bne r2,zero,100c6b4 + 100c69c: 008040b4 movhi r2,258 + 100c6a0: 10aba104 addi r2,r2,-20860 + 100c6a4: 10800017 ldw r2,0(r2) + 100c6a8: 103ee83a callr r2 + 100c6ac: e0bfff15 stw r2,-4(fp) + 100c6b0: 00000306 br 100c6c0 + 100c6b4: 008040b4 movhi r2,258 + 100c6b8: 10b30404 addi r2,r2,-13296 + 100c6bc: e0bfff15 stw r2,-4(fp) + 100c6c0: e0bfff17 ldw r2,-4(fp) +} + 100c6c4: e037883a mov sp,fp + 100c6c8: dfc00117 ldw ra,4(sp) + 100c6cc: df000017 ldw fp,0(sp) + 100c6d0: dec00204 addi sp,sp,8 + 100c6d4: f800283a ret + +0100c6d8 : + * + * ALT_KILL is mapped onto the kill() system call in alt_syscall.h + */ + +int ALT_KILL (int pid, int sig) +{ + 100c6d8: defffa04 addi sp,sp,-24 + 100c6dc: dfc00515 stw ra,20(sp) + 100c6e0: df000415 stw fp,16(sp) + 100c6e4: df000404 addi fp,sp,16 + 100c6e8: e13ffd15 stw r4,-12(fp) + 100c6ec: e17ffe15 stw r5,-8(fp) + int status = 0; + 100c6f0: e03ffc15 stw zero,-16(fp) + + if (pid <= 0) + 100c6f4: e0bffd17 ldw r2,-12(fp) + 100c6f8: 10800048 cmpgei r2,r2,1 + 100c6fc: 1000301e bne r2,zero,100c7c0 + { + switch (sig) + 100c700: e0bffe17 ldw r2,-8(fp) + 100c704: 10800828 cmpgeui r2,r2,32 + 100c708: 10002a1e bne r2,zero,100c7b4 + 100c70c: e0bffe17 ldw r2,-8(fp) + 100c710: 1085883a add r2,r2,r2 + 100c714: 1087883a add r3,r2,r2 + 100c718: 00804074 movhi r2,257 + 100c71c: 10b1cb04 addi r2,r2,-14548 + 100c720: 1885883a add r2,r3,r2 + 100c724: 10800017 ldw r2,0(r2) + 100c728: 1000683a jmp r2 + 100c72c: 0100c7d4 movui r4,799 + 100c730: 0100c7b4 movhi r4,798 + 100c734: 0100c7b4 movhi r4,798 + 100c738: 0100c7ac andhi r4,zero,798 + 100c73c: 0100c7ac andhi r4,zero,798 + 100c740: 0100c7ac andhi r4,zero,798 + 100c744: 0100c7ac andhi r4,zero,798 + 100c748: 0100c7b4 movhi r4,798 + 100c74c: 0100c7ac andhi r4,zero,798 + 100c750: 0100c7ac andhi r4,zero,798 + 100c754: 0100c7ac andhi r4,zero,798 + 100c758: 0100c7ac andhi r4,zero,798 + 100c75c: 0100c7ac andhi r4,zero,798 + 100c760: 0100c7ac andhi r4,zero,798 + 100c764: 0100c7ac andhi r4,zero,798 + 100c768: 0100c7ac andhi r4,zero,798 + 100c76c: 0100c7d4 movui r4,799 + 100c770: 0100c7b4 movhi r4,798 + 100c774: 0100c7b4 movhi r4,798 + 100c778: 0100c7b4 movhi r4,798 + 100c77c: 0100c7d4 movui r4,799 + 100c780: 0100c7b4 movhi r4,798 + 100c784: 0100c7b4 movhi r4,798 + 100c788: 0100c7ac andhi r4,zero,798 + 100c78c: 0100c7ac andhi r4,zero,798 + 100c790: 0100c7ac andhi r4,zero,798 + 100c794: 0100c7ac andhi r4,zero,798 + 100c798: 0100c7ac andhi r4,zero,798 + 100c79c: 0100c7b4 movhi r4,798 + 100c7a0: 0100c7b4 movhi r4,798 + 100c7a4: 0100c7ac andhi r4,zero,798 + 100c7a8: 0100c7ac andhi r4,zero,798 + * The Posix standard defines the default behaviour for all these signals + * as being eqivalent to a call to _exit(). No mechanism is provided to + * change this behaviour. + */ + + _exit(0); + 100c7ac: 0009883a mov r4,zero + 100c7b0: 100c4380 call 100c438 <_exit> + break; + default: + + /* Tried to send an unsupported signal */ + + status = EINVAL; + 100c7b4: 00800584 movi r2,22 + 100c7b8: e0bffc15 stw r2,-16(fp) + 100c7bc: 00000506 br 100c7d4 + } + } + + else if (pid > 0) + 100c7c0: e0bffd17 ldw r2,-12(fp) + 100c7c4: 10800050 cmplti r2,r2,1 + 100c7c8: 1000021e bne r2,zero,100c7d4 + { + /* Attempted to signal a non-existant process */ + + status = ESRCH; + 100c7cc: 008000c4 movi r2,3 + 100c7d0: e0bffc15 stw r2,-16(fp) + } + + if (status) + 100c7d4: e0bffc17 ldw r2,-16(fp) + 100c7d8: 1005003a cmpeq r2,r2,zero + 100c7dc: 1000071e bne r2,zero,100c7fc + { + ALT_ERRNO = status; + 100c7e0: 100c8180 call 100c818 + 100c7e4: 1007883a mov r3,r2 + 100c7e8: e0bffc17 ldw r2,-16(fp) + 100c7ec: 18800015 stw r2,0(r3) + return -1; + 100c7f0: 00bfffc4 movi r2,-1 + 100c7f4: e0bfff15 stw r2,-4(fp) + 100c7f8: 00000106 br 100c800 + } + + return 0; + 100c7fc: e03fff15 stw zero,-4(fp) + 100c800: e0bfff17 ldw r2,-4(fp) +} + 100c804: e037883a mov sp,fp + 100c808: dfc00117 ldw ra,4(sp) + 100c80c: df000017 ldw fp,0(sp) + 100c810: dec00204 addi sp,sp,8 + 100c814: f800283a ret + +0100c818 : +#undef errno + +extern int errno; + +static ALT_INLINE int* alt_get_errno(void) +{ + 100c818: defffd04 addi sp,sp,-12 + 100c81c: dfc00215 stw ra,8(sp) + 100c820: df000115 stw fp,4(sp) + 100c824: df000104 addi fp,sp,4 + return ((alt_errno) ? alt_errno() : &errno); + 100c828: 008040b4 movhi r2,258 + 100c82c: 10aba104 addi r2,r2,-20860 + 100c830: 10800017 ldw r2,0(r2) + 100c834: 1005003a cmpeq r2,r2,zero + 100c838: 1000061e bne r2,zero,100c854 + 100c83c: 008040b4 movhi r2,258 + 100c840: 10aba104 addi r2,r2,-20860 + 100c844: 10800017 ldw r2,0(r2) + 100c848: 103ee83a callr r2 + 100c84c: e0bfff15 stw r2,-4(fp) + 100c850: 00000306 br 100c860 + 100c854: 008040b4 movhi r2,258 + 100c858: 10b30404 addi r2,r2,-13296 + 100c85c: e0bfff15 stw r2,-4(fp) + 100c860: e0bfff17 ldw r2,-4(fp) +} + 100c864: e037883a mov sp,fp + 100c868: dfc00117 ldw ra,4(sp) + 100c86c: df000017 ldw fp,0(sp) + 100c870: dec00204 addi sp,sp,8 + 100c874: f800283a ret + +0100c878 : + * there is no bootloader, so this application is responsible for loading to + * RAM any sections that are required. + */ + +void alt_load (void) +{ + 100c878: defffe04 addi sp,sp,-8 + 100c87c: dfc00115 stw ra,4(sp) + 100c880: df000015 stw fp,0(sp) + 100c884: d839883a mov fp,sp + /* + * Copy the .rwdata section. + */ + + alt_load_section (&__flash_rwdata_start, + 100c888: 010040b4 movhi r4,258 + 100c88c: 212bc504 addi r4,r4,-20716 + 100c890: 014040b4 movhi r5,258 + 100c894: 29649004 addi r5,r5,-28096 + 100c898: 018040b4 movhi r6,258 + 100c89c: 31abc504 addi r6,r6,-20716 + 100c8a0: 100c8f80 call 100c8f8 + + /* + * Copy the exception handler. + */ + + alt_load_section (&__flash_exceptions_start, + 100c8a4: 01004034 movhi r4,256 + 100c8a8: 21000804 addi r4,r4,32 + 100c8ac: 01404034 movhi r5,256 + 100c8b0: 29400804 addi r5,r5,32 + 100c8b4: 01804034 movhi r6,256 + 100c8b8: 31807004 addi r6,r6,448 + 100c8bc: 100c8f80 call 100c8f8 + + /* + * Copy the .rodata section. + */ + + alt_load_section (&__flash_rodata_start, + 100c8c0: 010040b4 movhi r4,258 + 100c8c4: 2122f504 addi r4,r4,-29740 + 100c8c8: 014040b4 movhi r5,258 + 100c8cc: 2962f504 addi r5,r5,-29740 + 100c8d0: 018040b4 movhi r6,258 + 100c8d4: 31a49004 addi r6,r6,-28096 + 100c8d8: 100c8f80 call 100c8f8 + + /* + * Now ensure that the caches are in synch. + */ + + alt_dcache_flush_all(); + 100c8dc: 10175c00 call 10175c0 + alt_icache_flush_all(); + 100c8e0: 10178740 call 1017874 +} + 100c8e4: e037883a mov sp,fp + 100c8e8: dfc00117 ldw ra,4(sp) + 100c8ec: df000017 ldw fp,0(sp) + 100c8f0: dec00204 addi sp,sp,8 + 100c8f4: f800283a ret + +0100c8f8 : + */ + +static void ALT_INLINE alt_load_section (alt_u32* from, + alt_u32* to, + alt_u32* end) +{ + 100c8f8: defffc04 addi sp,sp,-16 + 100c8fc: df000315 stw fp,12(sp) + 100c900: df000304 addi fp,sp,12 + 100c904: e13ffd15 stw r4,-12(fp) + 100c908: e17ffe15 stw r5,-8(fp) + 100c90c: e1bfff15 stw r6,-4(fp) + if (to != from) + 100c910: e0fffe17 ldw r3,-8(fp) + 100c914: e0bffd17 ldw r2,-12(fp) + 100c918: 18800e26 beq r3,r2,100c954 + { + while( to != end ) + 100c91c: 00000a06 br 100c948 + { + *to++ = *from++; + 100c920: e0bffd17 ldw r2,-12(fp) + 100c924: 10c00017 ldw r3,0(r2) + 100c928: e0bffe17 ldw r2,-8(fp) + 100c92c: 10c00015 stw r3,0(r2) + 100c930: e0bffe17 ldw r2,-8(fp) + 100c934: 10800104 addi r2,r2,4 + 100c938: e0bffe15 stw r2,-8(fp) + 100c93c: e0bffd17 ldw r2,-12(fp) + 100c940: 10800104 addi r2,r2,4 + 100c944: e0bffd15 stw r2,-12(fp) + alt_u32* to, + alt_u32* end) +{ + if (to != from) + { + while( to != end ) + 100c948: e0fffe17 ldw r3,-8(fp) + 100c94c: e0bfff17 ldw r2,-4(fp) + 100c950: 18bff31e bne r3,r2,100c920 + { + *to++ = *from++; + } + } +} + 100c954: e037883a mov sp,fp + 100c958: df000017 ldw fp,0(sp) + 100c95c: dec00104 addi sp,sp,4 + 100c960: f800283a ret + +0100c964 : + * ALT_LSEEK is mapped onto the lseek() system call in alt_syscall.h + * + */ + +off_t ALT_LSEEK (int file, off_t ptr, int dir) +{ + 100c964: defff804 addi sp,sp,-32 + 100c968: dfc00715 stw ra,28(sp) + 100c96c: df000615 stw fp,24(sp) + 100c970: df000604 addi fp,sp,24 + 100c974: e13ffc15 stw r4,-16(fp) + 100c978: e17ffd15 stw r5,-12(fp) + 100c97c: e1bffe15 stw r6,-8(fp) + alt_fd* fd; + off_t rc = 0; + 100c980: e03ffa15 stw zero,-24(fp) + * A common error case is that when the file descriptor was created, the call + * to open() failed resulting in a negative file descriptor. This is trapped + * below so that we don't try and process an invalid file descriptor. + */ + + fd = (file < 0) ? NULL : &alt_fd_list[file]; + 100c984: e0bffc17 ldw r2,-16(fp) + 100c988: 1004803a cmplt r2,r2,zero + 100c98c: 1000081e bne r2,zero,100c9b0 + 100c990: e0bffc17 ldw r2,-16(fp) + 100c994: 10800324 muli r2,r2,12 + 100c998: 1007883a mov r3,r2 + 100c99c: 008040b4 movhi r2,258 + 100c9a0: 10a69f04 addi r2,r2,-25988 + 100c9a4: 1887883a add r3,r3,r2 + 100c9a8: e0ffff15 stw r3,-4(fp) + 100c9ac: 00000106 br 100c9b4 + 100c9b0: e03fff15 stw zero,-4(fp) + 100c9b4: e0bfff17 ldw r2,-4(fp) + 100c9b8: e0bffb15 stw r2,-20(fp) + + if (fd) + 100c9bc: e0bffb17 ldw r2,-20(fp) + 100c9c0: 1005003a cmpeq r2,r2,zero + 100c9c4: 1000111e bne r2,zero,100ca0c + /* + * If the device driver provides an implementation of the lseek() function, + * then call that to process the request. + */ + + if (fd->dev->lseek) + 100c9c8: e0bffb17 ldw r2,-20(fp) + 100c9cc: 10800017 ldw r2,0(r2) + 100c9d0: 10800717 ldw r2,28(r2) + 100c9d4: 1005003a cmpeq r2,r2,zero + 100c9d8: 1000091e bne r2,zero,100ca00 + { + rc = fd->dev->lseek(fd, ptr, dir); + 100c9dc: e0bffb17 ldw r2,-20(fp) + 100c9e0: 10800017 ldw r2,0(r2) + 100c9e4: 10800717 ldw r2,28(r2) + 100c9e8: e13ffb17 ldw r4,-20(fp) + 100c9ec: e17ffd17 ldw r5,-12(fp) + 100c9f0: e1bffe17 ldw r6,-8(fp) + 100c9f4: 103ee83a callr r2 + 100c9f8: e0bffa15 stw r2,-24(fp) + 100c9fc: 00000506 br 100ca14 + * Otherwise return an error. + */ + + else + { + rc = -ENOTSUP; + 100ca00: 00bfde84 movi r2,-134 + 100ca04: e0bffa15 stw r2,-24(fp) + 100ca08: 00000206 br 100ca14 + } + } + else + { + rc = -EBADFD; + 100ca0c: 00bfebc4 movi r2,-81 + 100ca10: e0bffa15 stw r2,-24(fp) + } + + if (rc < 0) + 100ca14: e0bffa17 ldw r2,-24(fp) + 100ca18: 1004403a cmpge r2,r2,zero + 100ca1c: 1000071e bne r2,zero,100ca3c + { + ALT_ERRNO = -rc; + 100ca20: 100ca540 call 100ca54 + 100ca24: 1007883a mov r3,r2 + 100ca28: e0bffa17 ldw r2,-24(fp) + 100ca2c: 0085c83a sub r2,zero,r2 + 100ca30: 18800015 stw r2,0(r3) + rc = -1; + 100ca34: 00bfffc4 movi r2,-1 + 100ca38: e0bffa15 stw r2,-24(fp) + } + + return rc; + 100ca3c: e0bffa17 ldw r2,-24(fp) +} + 100ca40: e037883a mov sp,fp + 100ca44: dfc00117 ldw ra,4(sp) + 100ca48: df000017 ldw fp,0(sp) + 100ca4c: dec00204 addi sp,sp,8 + 100ca50: f800283a ret + +0100ca54 : +#undef errno + +extern int errno; + +static ALT_INLINE int* alt_get_errno(void) +{ + 100ca54: defffd04 addi sp,sp,-12 + 100ca58: dfc00215 stw ra,8(sp) + 100ca5c: df000115 stw fp,4(sp) + 100ca60: df000104 addi fp,sp,4 + return ((alt_errno) ? alt_errno() : &errno); + 100ca64: 008040b4 movhi r2,258 + 100ca68: 10aba104 addi r2,r2,-20860 + 100ca6c: 10800017 ldw r2,0(r2) + 100ca70: 1005003a cmpeq r2,r2,zero + 100ca74: 1000061e bne r2,zero,100ca90 + 100ca78: 008040b4 movhi r2,258 + 100ca7c: 10aba104 addi r2,r2,-20860 + 100ca80: 10800017 ldw r2,0(r2) + 100ca84: 103ee83a callr r2 + 100ca88: e0bfff15 stw r2,-4(fp) + 100ca8c: 00000306 br 100ca9c + 100ca90: 008040b4 movhi r2,258 + 100ca94: 10b30404 addi r2,r2,-13296 + 100ca98: e0bfff15 stw r2,-4(fp) + 100ca9c: e0bfff17 ldw r2,-4(fp) +} + 100caa0: e037883a mov sp,fp + 100caa4: dfc00117 ldw ra,4(sp) + 100caa8: df000017 ldw fp,0(sp) + 100caac: dec00204 addi sp,sp,8 + 100cab0: f800283a ret + +0100cab4 : + * devices/filesystems/components in the system; and call the entry point for + * the users application, i.e. main(). + */ + +void alt_main (void) +{ + 100cab4: defffb04 addi sp,sp,-20 + 100cab8: dfc00415 stw ra,16(sp) + 100cabc: df000315 stw fp,12(sp) + 100cac0: df000304 addi fp,sp,12 +#endif + + /* ALT LOG - please see HAL/sys/alt_log_printf.h for details */ + ALT_LOG_PRINT_BOOT("[alt_main.c] Entering alt_main, calling alt_irq_init.\r\n"); + /* Initialize the interrupt controller. */ + alt_irq_init (NULL); + 100cac4: 0009883a mov r4,zero + 100cac8: 10155440 call 1015544 + + /* Initialize the operating system */ + ALT_LOG_PRINT_BOOT("[alt_main.c] Done alt_irq_init, calling alt_os_init.\r\n"); + ALT_OS_INIT(); + 100cacc: 100dba00 call 100dba0 + 100cad0: 01000044 movi r4,1 + 100cad4: 1012a640 call 1012a64 + 100cad8: 1007883a mov r3,r2 + 100cadc: 008040b4 movhi r2,258 + 100cae0: 10b30d04 addi r2,r2,-13260 + 100cae4: 10c00015 stw r3,0(r2) + 100cae8: 01000044 movi r4,1 + 100caec: 1012a640 call 1012a64 + 100caf0: 1007883a mov r3,r2 + 100caf4: 008040b4 movhi r2,258 + 100caf8: 10b30f04 addi r2,r2,-13252 + 100cafc: 10c00015 stw r3,0(r2) + 100cb00: 008040b4 movhi r2,258 + 100cb04: 10b30804 addi r2,r2,-13280 + 100cb08: e0bffd15 stw r2,-12(fp) + 100cb0c: 00800044 movi r2,1 + 100cb10: e0bffe0d sth r2,-8(fp) + */ + +static ALT_INLINE int ALT_ALWAYS_INLINE alt_sem_create (OS_EVENT** sem, + INT16U value) +{ + *sem = OSSemCreate (value); + 100cb14: e13ffe0b ldhu r4,-8(fp) + 100cb18: 1012a640 call 1012a64 + 100cb1c: 1007883a mov r3,r2 + 100cb20: e0bffd17 ldw r2,-12(fp) + 100cb24: 10c00015 stw r3,0(r2) + ALT_LOG_PRINT_BOOT("[alt_main.c] Done OS Init, calling alt_sem_create.\r\n"); + ALT_SEM_CREATE (&alt_fd_list_lock, 1); + + /* Initialize the device drivers/software components. */ + ALT_LOG_PRINT_BOOT("[alt_main.c] Calling alt_sys_init.\r\n"); + alt_sys_init(); + 100cb28: 10155780 call 1015578 + * devices be present (not equal to /dev/null) and if direct drivers + * aren't being used. + */ + + ALT_LOG_PRINT_BOOT("[alt_main.c] Redirecting IO.\r\n"); + alt_io_redirect(ALT_STDOUT, ALT_STDIN, ALT_STDERR); + 100cb2c: 010040b4 movhi r4,258 + 100cb30: 21243104 addi r4,r4,-28476 + 100cb34: 014040b4 movhi r5,258 + 100cb38: 29643104 addi r5,r5,-28476 + 100cb3c: 018040b4 movhi r6,258 + 100cb40: 31a43104 addi r6,r6,-28476 + 100cb44: 10179680 call 1017968 + /* + * Call the C++ constructors + */ + + ALT_LOG_PRINT_BOOT("[alt_main.c] Calling C++ constructors.\r\n"); + _do_ctors (); + 100cb48: 10177180 call 1017718 <_do_ctors> + * redefined as _exit()). This is in the interest of reducing code footprint, + * in that the atexit() overhead is removed when it's not needed. + */ + + ALT_LOG_PRINT_BOOT("[alt_main.c] Calling atexit.\r\n"); + atexit (_do_dtors); + 100cb4c: 01004074 movhi r4,257 + 100cb50: 211ddf04 addi r4,r4,30588 + 100cb54: 10187b80 call 10187b8 + ALT_LOG_PRINT_BOOT("[alt_main.c] Calling main.\r\n"); + +#ifdef ALT_NO_EXIT + main (alt_argc, alt_argv, alt_envp); +#else + result = main (alt_argc, alt_argv, alt_envp); + 100cb58: d1277c17 ldw r4,-25104(gp) + 100cb5c: d1677d17 ldw r5,-25100(gp) + 100cb60: d1a77e17 ldw r6,-25096(gp) + 100cb64: 10007dc0 call 10007dc
+ 100cb68: e0bfff15 stw r2,-4(fp) + close(STDOUT_FILENO); + 100cb6c: 01000044 movi r4,1 + 100cb70: 100c2700 call 100c270 + exit (result); + 100cb74: e13fff17 ldw r4,-4(fp) + 100cb78: 10187cc0 call 10187cc + +0100cb7c : +} + +#else /* !ALT_USE_DIRECT_DRIVERS */ + +int ALT_READ (int file, void *ptr, size_t len) +{ + 100cb7c: defff704 addi sp,sp,-36 + 100cb80: dfc00815 stw ra,32(sp) + 100cb84: df000715 stw fp,28(sp) + 100cb88: df000704 addi fp,sp,28 + 100cb8c: e13ffb15 stw r4,-20(fp) + 100cb90: e17ffc15 stw r5,-16(fp) + 100cb94: e1bffd15 stw r6,-12(fp) + * A common error case is that when the file descriptor was created, the call + * to open() failed resulting in a negative file descriptor. This is trapped + * below so that we don't try and process an invalid file descriptor. + */ + + fd = (file < 0) ? NULL : &alt_fd_list[file]; + 100cb98: e0bffb17 ldw r2,-20(fp) + 100cb9c: 1004803a cmplt r2,r2,zero + 100cba0: 1000081e bne r2,zero,100cbc4 + 100cba4: e0bffb17 ldw r2,-20(fp) + 100cba8: 10800324 muli r2,r2,12 + 100cbac: 1007883a mov r3,r2 + 100cbb0: 008040b4 movhi r2,258 + 100cbb4: 10a69f04 addi r2,r2,-25988 + 100cbb8: 1887883a add r3,r3,r2 + 100cbbc: e0ffff15 stw r3,-4(fp) + 100cbc0: 00000106 br 100cbc8 + 100cbc4: e03fff15 stw zero,-4(fp) + 100cbc8: e0bfff17 ldw r2,-4(fp) + 100cbcc: e0bffa15 stw r2,-24(fp) + + if (fd) + 100cbd0: e0bffa17 ldw r2,-24(fp) + 100cbd4: 1005003a cmpeq r2,r2,zero + 100cbd8: 1000241e bne r2,zero,100cc6c + * If the file has not been opened with read access, or if the driver does + * not provide an implementation of read(), generate an error. Otherwise + * call the drivers read() function to process the request. + */ + + if (((fd->fd_flags & O_ACCMODE) != O_WRONLY) && + 100cbdc: e0bffa17 ldw r2,-24(fp) + 100cbe0: 10800217 ldw r2,8(r2) + 100cbe4: 108000cc andi r2,r2,3 + 100cbe8: 10800060 cmpeqi r2,r2,1 + 100cbec: 10001a1e bne r2,zero,100cc58 + 100cbf0: e0bffa17 ldw r2,-24(fp) + 100cbf4: 10800017 ldw r2,0(r2) + 100cbf8: 10800517 ldw r2,20(r2) + 100cbfc: 1005003a cmpeq r2,r2,zero + 100cc00: 1000151e bne r2,zero,100cc58 + (fd->dev->read)) + { + if ((rval = fd->dev->read(fd, ptr, len)) < 0) + 100cc04: e0bffa17 ldw r2,-24(fp) + 100cc08: 10800017 ldw r2,0(r2) + 100cc0c: 10800517 ldw r2,20(r2) + 100cc10: e17ffc17 ldw r5,-16(fp) + 100cc14: e1bffd17 ldw r6,-12(fp) + 100cc18: e13ffa17 ldw r4,-24(fp) + 100cc1c: 103ee83a callr r2 + 100cc20: e0bff915 stw r2,-28(fp) + 100cc24: e0bff917 ldw r2,-28(fp) + 100cc28: 1004403a cmpge r2,r2,zero + 100cc2c: 1000071e bne r2,zero,100cc4c + { + ALT_ERRNO = -rval; + 100cc30: 100cc9c0 call 100cc9c + 100cc34: e0fff917 ldw r3,-28(fp) + 100cc38: 00c7c83a sub r3,zero,r3 + 100cc3c: 10c00015 stw r3,0(r2) + return -1; + 100cc40: 00bfffc4 movi r2,-1 + 100cc44: e0bffe15 stw r2,-8(fp) + 100cc48: 00000e06 br 100cc84 + } + return rval; + 100cc4c: e0bff917 ldw r2,-28(fp) + 100cc50: e0bffe15 stw r2,-8(fp) + 100cc54: 00000b06 br 100cc84 + } + else + { + ALT_ERRNO = EACCES; + 100cc58: 100cc9c0 call 100cc9c + 100cc5c: 1007883a mov r3,r2 + 100cc60: 00800344 movi r2,13 + 100cc64: 18800015 stw r2,0(r3) + 100cc68: 00000406 br 100cc7c + } + } + else + { + ALT_ERRNO = EBADFD; + 100cc6c: 100cc9c0 call 100cc9c + 100cc70: 1007883a mov r3,r2 + 100cc74: 00801444 movi r2,81 + 100cc78: 18800015 stw r2,0(r3) + } + return -1; + 100cc7c: 00bfffc4 movi r2,-1 + 100cc80: e0bffe15 stw r2,-8(fp) + 100cc84: e0bffe17 ldw r2,-8(fp) +} + 100cc88: e037883a mov sp,fp + 100cc8c: dfc00117 ldw ra,4(sp) + 100cc90: df000017 ldw fp,0(sp) + 100cc94: dec00204 addi sp,sp,8 + 100cc98: f800283a ret + +0100cc9c : +#undef errno + +extern int errno; + +static ALT_INLINE int* alt_get_errno(void) +{ + 100cc9c: defffd04 addi sp,sp,-12 + 100cca0: dfc00215 stw ra,8(sp) + 100cca4: df000115 stw fp,4(sp) + 100cca8: df000104 addi fp,sp,4 + return ((alt_errno) ? alt_errno() : &errno); + 100ccac: 008040b4 movhi r2,258 + 100ccb0: 10aba104 addi r2,r2,-20860 + 100ccb4: 10800017 ldw r2,0(r2) + 100ccb8: 1005003a cmpeq r2,r2,zero + 100ccbc: 1000061e bne r2,zero,100ccd8 + 100ccc0: 008040b4 movhi r2,258 + 100ccc4: 10aba104 addi r2,r2,-20860 + 100ccc8: 10800017 ldw r2,0(r2) + 100cccc: 103ee83a callr r2 + 100ccd0: e0bfff15 stw r2,-4(fp) + 100ccd4: 00000306 br 100cce4 + 100ccd8: 008040b4 movhi r2,258 + 100ccdc: 10b30404 addi r2,r2,-13296 + 100cce0: e0bfff15 stw r2,-4(fp) + 100cce4: e0bfff17 ldw r2,-4(fp) +} + 100cce8: e037883a mov sp,fp + 100ccec: dfc00117 ldw ra,4(sp) + 100ccf0: df000017 ldw fp,0(sp) + 100ccf4: dec00204 addi sp,sp,8 + 100ccf8: f800283a ret + +0100ccfc : + * File descriptors correcponding to standard in, standard out and standard + * error cannont be released backed to the pool. They are always reserved. + */ + +void alt_release_fd (int fd) +{ + 100ccfc: defffe04 addi sp,sp,-8 + 100cd00: df000115 stw fp,4(sp) + 100cd04: df000104 addi fp,sp,4 + 100cd08: e13fff15 stw r4,-4(fp) + if (fd > 2) + 100cd0c: e0bfff17 ldw r2,-4(fp) + 100cd10: 108000d0 cmplti r2,r2,3 + 100cd14: 10000d1e bne r2,zero,100cd4c + { + alt_fd_list[fd].fd_flags = 0; + 100cd18: e0bfff17 ldw r2,-4(fp) + 100cd1c: 00c040b4 movhi r3,258 + 100cd20: 18e69f04 addi r3,r3,-25988 + 100cd24: 10800324 muli r2,r2,12 + 100cd28: 10c5883a add r2,r2,r3 + 100cd2c: 10800204 addi r2,r2,8 + 100cd30: 10000015 stw zero,0(r2) + alt_fd_list[fd].dev = 0; + 100cd34: e0bfff17 ldw r2,-4(fp) + 100cd38: 00c040b4 movhi r3,258 + 100cd3c: 18e69f04 addi r3,r3,-25988 + 100cd40: 10800324 muli r2,r2,12 + 100cd44: 10c5883a add r2,r2,r3 + 100cd48: 10000015 stw zero,0(r2) + } +} + 100cd4c: e037883a mov sp,fp + 100cd50: df000017 ldw fp,0(sp) + 100cd54: dec00104 addi sp,sp,4 + 100cd58: f800283a ret + +0100cd5c : +#endif + +caddr_t ALT_SBRK (int incr) __attribute__ ((no_instrument_function )); + +caddr_t ALT_SBRK (int incr) +{ + 100cd5c: defff804 addi sp,sp,-32 + 100cd60: df000715 stw fp,28(sp) + 100cd64: df000704 addi fp,sp,28 + 100cd68: e13ffe15 stw r4,-8(fp) +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 100cd6c: 0005303a rdctl r2,status + 100cd70: e0bffb15 stw r2,-20(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 100cd74: e0fffb17 ldw r3,-20(fp) + 100cd78: 00bfff84 movi r2,-2 + 100cd7c: 1884703a and r2,r3,r2 + 100cd80: 1001703a wrctl status,r2 + + return context; + 100cd84: e0bffb17 ldw r2,-20(fp) + alt_irq_context context; + char *prev_heap_end; + + context = alt_irq_disable_all(); + 100cd88: e0bffd15 stw r2,-12(fp) + + /* Always return data aligned on a word boundary */ + heap_end = (char *)(((unsigned int)heap_end + 3) & ~3); + 100cd8c: d0a01517 ldw r2,-32684(gp) + 100cd90: 10c000c4 addi r3,r2,3 + 100cd94: 00bfff04 movi r2,-4 + 100cd98: 1884703a and r2,r3,r2 + 100cd9c: d0a01515 stw r2,-32684(gp) + if (((heap_end + incr) - __alt_heap_start) > ALT_MAX_HEAP_BYTES) { + alt_irq_enable_all(context); + return (caddr_t)-1; + } +#else + if ((heap_end + incr) > __alt_heap_limit) { + 100cda0: d0e01517 ldw r3,-32684(gp) + 100cda4: e0bffe17 ldw r2,-8(fp) + 100cda8: 1887883a add r3,r3,r2 + 100cdac: 00808034 movhi r2,512 + 100cdb0: 10800004 addi r2,r2,0 + 100cdb4: 10c0072e bgeu r2,r3,100cdd4 + 100cdb8: e0bffd17 ldw r2,-12(fp) + 100cdbc: e0bffa15 stw r2,-24(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 100cdc0: e0bffa17 ldw r2,-24(fp) + 100cdc4: 1001703a wrctl status,r2 + alt_irq_enable_all(context); + return (caddr_t)-1; + 100cdc8: 00bfffc4 movi r2,-1 + 100cdcc: e0bfff15 stw r2,-4(fp) + 100cdd0: 00000c06 br 100ce04 + } +#endif + + prev_heap_end = heap_end; + 100cdd4: d0a01517 ldw r2,-32684(gp) + 100cdd8: e0bffc15 stw r2,-16(fp) + heap_end += incr; + 100cddc: d0e01517 ldw r3,-32684(gp) + 100cde0: e0bffe17 ldw r2,-8(fp) + 100cde4: 1885883a add r2,r3,r2 + 100cde8: d0a01515 stw r2,-32684(gp) + 100cdec: e0bffd17 ldw r2,-12(fp) + 100cdf0: e0bff915 stw r2,-28(fp) + 100cdf4: e0bff917 ldw r2,-28(fp) + 100cdf8: 1001703a wrctl status,r2 + +#endif + + alt_irq_enable_all(context); + + return (caddr_t) prev_heap_end; + 100cdfc: e0bffc17 ldw r2,-16(fp) + 100ce00: e0bfff15 stw r2,-4(fp) + 100ce04: e0bfff17 ldw r2,-4(fp) +} + 100ce08: e037883a mov sp,fp + 100ce0c: df000017 ldw fp,0(sp) + 100ce10: dec00104 addi sp,sp,4 + 100ce14: f800283a ret + +0100ce18 : +} + +#else /* !ALT_USE_DIRECT_DRIVERS */ + +int ALT_WRITE (int file, const void *ptr, size_t len) +{ + 100ce18: defff704 addi sp,sp,-36 + 100ce1c: dfc00815 stw ra,32(sp) + 100ce20: df000715 stw fp,28(sp) + 100ce24: df000704 addi fp,sp,28 + 100ce28: e13ffb15 stw r4,-20(fp) + 100ce2c: e17ffc15 stw r5,-16(fp) + 100ce30: e1bffd15 stw r6,-12(fp) + * A common error case is that when the file descriptor was created, the call + * to open() failed resulting in a negative file descriptor. This is trapped + * below so that we don't try and process an invalid file descriptor. + */ + + fd = (file < 0) ? NULL : &alt_fd_list[file]; + 100ce34: e0bffb17 ldw r2,-20(fp) + 100ce38: 1004803a cmplt r2,r2,zero + 100ce3c: 1000081e bne r2,zero,100ce60 + 100ce40: e0bffb17 ldw r2,-20(fp) + 100ce44: 10800324 muli r2,r2,12 + 100ce48: 1007883a mov r3,r2 + 100ce4c: 008040b4 movhi r2,258 + 100ce50: 10a69f04 addi r2,r2,-25988 + 100ce54: 1887883a add r3,r3,r2 + 100ce58: e0ffff15 stw r3,-4(fp) + 100ce5c: 00000106 br 100ce64 + 100ce60: e03fff15 stw zero,-4(fp) + 100ce64: e0bfff17 ldw r2,-4(fp) + 100ce68: e0bffa15 stw r2,-24(fp) + + if (fd) + 100ce6c: e0bffa17 ldw r2,-24(fp) + 100ce70: 1005003a cmpeq r2,r2,zero + 100ce74: 1000241e bne r2,zero,100cf08 + * If the file has not been opened with write access, or if the driver does + * not provide an implementation of write(), generate an error. Otherwise + * call the drivers write() function to process the request. + */ + + if (((fd->fd_flags & O_ACCMODE) != O_RDONLY) && fd->dev->write) + 100ce78: e0bffa17 ldw r2,-24(fp) + 100ce7c: 10800217 ldw r2,8(r2) + 100ce80: 108000cc andi r2,r2,3 + 100ce84: 1005003a cmpeq r2,r2,zero + 100ce88: 10001a1e bne r2,zero,100cef4 + 100ce8c: e0bffa17 ldw r2,-24(fp) + 100ce90: 10800017 ldw r2,0(r2) + 100ce94: 10800617 ldw r2,24(r2) + 100ce98: 1005003a cmpeq r2,r2,zero + 100ce9c: 1000151e bne r2,zero,100cef4 + { + + /* ALT_LOG - see altera_hal/HAL/inc/sys/alt_log_printf.h */ + ALT_LOG_WRITE_FUNCTION(ptr,len); + + if ((rval = fd->dev->write(fd, ptr, len)) < 0) + 100cea0: e0bffa17 ldw r2,-24(fp) + 100cea4: 10800017 ldw r2,0(r2) + 100cea8: 10800617 ldw r2,24(r2) + 100ceac: e17ffc17 ldw r5,-16(fp) + 100ceb0: e1bffd17 ldw r6,-12(fp) + 100ceb4: e13ffa17 ldw r4,-24(fp) + 100ceb8: 103ee83a callr r2 + 100cebc: e0bff915 stw r2,-28(fp) + 100cec0: e0bff917 ldw r2,-28(fp) + 100cec4: 1004403a cmpge r2,r2,zero + 100cec8: 1000071e bne r2,zero,100cee8 + { + ALT_ERRNO = -rval; + 100cecc: 100cf380 call 100cf38 + 100ced0: e0fff917 ldw r3,-28(fp) + 100ced4: 00c7c83a sub r3,zero,r3 + 100ced8: 10c00015 stw r3,0(r2) + return -1; + 100cedc: 00bfffc4 movi r2,-1 + 100cee0: e0bffe15 stw r2,-8(fp) + 100cee4: 00000e06 br 100cf20 + } + return rval; + 100cee8: e0bff917 ldw r2,-28(fp) + 100ceec: e0bffe15 stw r2,-8(fp) + 100cef0: 00000b06 br 100cf20 + } + else + { + ALT_ERRNO = EACCES; + 100cef4: 100cf380 call 100cf38 + 100cef8: 1007883a mov r3,r2 + 100cefc: 00800344 movi r2,13 + 100cf00: 18800015 stw r2,0(r3) + 100cf04: 00000406 br 100cf18 + } + } + else + { + ALT_ERRNO = EBADFD; + 100cf08: 100cf380 call 100cf38 + 100cf0c: 1007883a mov r3,r2 + 100cf10: 00801444 movi r2,81 + 100cf14: 18800015 stw r2,0(r3) + } + return -1; + 100cf18: 00bfffc4 movi r2,-1 + 100cf1c: e0bffe15 stw r2,-8(fp) + 100cf20: e0bffe17 ldw r2,-8(fp) +} + 100cf24: e037883a mov sp,fp + 100cf28: dfc00117 ldw ra,4(sp) + 100cf2c: df000017 ldw fp,0(sp) + 100cf30: dec00204 addi sp,sp,8 + 100cf34: f800283a ret + +0100cf38 : +#undef errno + +extern int errno; + +static ALT_INLINE int* alt_get_errno(void) +{ + 100cf38: defffd04 addi sp,sp,-12 + 100cf3c: dfc00215 stw ra,8(sp) + 100cf40: df000115 stw fp,4(sp) + 100cf44: df000104 addi fp,sp,4 + return ((alt_errno) ? alt_errno() : &errno); + 100cf48: 008040b4 movhi r2,258 + 100cf4c: 10aba104 addi r2,r2,-20860 + 100cf50: 10800017 ldw r2,0(r2) + 100cf54: 1005003a cmpeq r2,r2,zero + 100cf58: 1000061e bne r2,zero,100cf74 + 100cf5c: 008040b4 movhi r2,258 + 100cf60: 10aba104 addi r2,r2,-20860 + 100cf64: 10800017 ldw r2,0(r2) + 100cf68: 103ee83a callr r2 + 100cf6c: e0bfff15 stw r2,-4(fp) + 100cf70: 00000306 br 100cf80 + 100cf74: 008040b4 movhi r2,258 + 100cf78: 10b30404 addi r2,r2,-13296 + 100cf7c: e0bfff15 stw r2,-4(fp) + 100cf80: e0bfff17 ldw r2,-4(fp) +} + 100cf84: e037883a mov sp,fp + 100cf88: dfc00117 ldw ra,4(sp) + 100cf8c: df000017 ldw fp,0(sp) + 100cf90: dec00204 addi sp,sp,8 + 100cf94: f800283a ret + +0100cf98 <__env_lock>: +/* + * + */ + +void __env_lock ( struct _reent *_r ) +{ + 100cf98: deffdf04 addi sp,sp,-132 + 100cf9c: dfc02015 stw ra,128(sp) + 100cfa0: df001f15 stw fp,124(sp) + 100cfa4: df001f04 addi fp,sp,124 + 100cfa8: e13fff15 stw r4,-4(fp) + INT8U err; + int id; + + /* use our priority as a task id */ + + err = OSTaskQuery( OS_PRIO_SELF, &tcb ); + 100cfac: e17fe204 addi r5,fp,-120 + 100cfb0: 01003fc4 movi r4,255 + 100cfb4: 1014dec0 call 1014dec + 100cfb8: e0bffe85 stb r2,-6(fp) + if (err != OS_NO_ERR) + 100cfbc: e0bffe83 ldbu r2,-6(fp) + 100cfc0: 10803fcc andi r2,r2,255 + 100cfc4: 1004c03a cmpne r2,r2,zero + 100cfc8: 1000191e bne r2,zero,100d030 <__env_lock+0x98> + return; + + id = tcb.OSTCBPrio; + 100cfcc: e0bfee83 ldbu r2,-70(fp) + 100cfd0: 10803fcc andi r2,r2,255 + 100cfd4: e0bfe115 stw r2,-124(fp) + + /* see if we own the environment already */ + + OSSemQuery( alt_envsem, &semdata ); + 100cfd8: d1278017 ldw r4,-25088(gp) + 100cfdc: e17ffd04 addi r5,fp,-12 + 100cfe0: 10133380 call 1013338 + if( semdata.OSEventGrp && id == lockid ) + 100cfe4: e0bffe43 ldbu r2,-7(fp) + 100cfe8: 10803fcc andi r2,r2,255 + 100cfec: 1005003a cmpeq r2,r2,zero + 100cff0: 1000071e bne r2,zero,100d010 <__env_lock+0x78> + 100cff4: d0e01617 ldw r3,-32680(gp) + 100cff8: e0bfe117 ldw r2,-124(fp) + 100cffc: 10c0041e bne r2,r3,100d010 <__env_lock+0x78> + { + /* we do; just count the recursion */ + + locks++; + 100d000: d0a77f17 ldw r2,-25092(gp) + 100d004: 10800044 addi r2,r2,1 + 100d008: d0a77f15 stw r2,-25092(gp) + id = tcb.OSTCBPrio; + + /* see if we own the environment already */ + + OSSemQuery( alt_envsem, &semdata ); + if( semdata.OSEventGrp && id == lockid ) + 100d00c: 00000806 br 100d030 <__env_lock+0x98> + } + else + { + /* wait on the other task to yield, then claim ownership */ + + OSSemPend( alt_envsem, 0, &err ); + 100d010: d1278017 ldw r4,-25088(gp) + 100d014: e1bffe84 addi r6,fp,-6 + 100d018: 000b883a mov r5,zero + 100d01c: 1012e180 call 1012e18 + locks = 1; + 100d020: 00800044 movi r2,1 + 100d024: d0a77f15 stw r2,-25092(gp) + lockid = id; + 100d028: e0bfe117 ldw r2,-124(fp) + 100d02c: d0a01615 stw r2,-32680(gp) + } + +#endif /* OS_THREAD_SAFE_NEWLIB */ + return; +} + 100d030: e037883a mov sp,fp + 100d034: dfc00117 ldw ra,4(sp) + 100d038: df000017 ldw fp,0(sp) + 100d03c: dec00204 addi sp,sp,8 + 100d040: f800283a ret + +0100d044 <__env_unlock>: +/* + * + */ + +void __env_unlock ( struct _reent *_r ) +{ + 100d044: defffd04 addi sp,sp,-12 + 100d048: dfc00215 stw ra,8(sp) + 100d04c: df000115 stw fp,4(sp) + 100d050: df000104 addi fp,sp,4 + 100d054: e13fff15 stw r4,-4(fp) +#if OS_THREAD_SAFE_NEWLIB + if (locks == 0) + 100d058: d0a77f17 ldw r2,-25092(gp) + 100d05c: 1005003a cmpeq r2,r2,zero + 100d060: 10000a1e bne r2,zero,100d08c <__env_unlock+0x48> + /* + * release the environment once the number of locks == the number + * of unlocks + */ + + if( (--locks) == 0 ) + 100d064: d0a77f17 ldw r2,-25092(gp) + 100d068: 10bfffc4 addi r2,r2,-1 + 100d06c: d0a77f15 stw r2,-25092(gp) + 100d070: d0a77f17 ldw r2,-25092(gp) + 100d074: 1004c03a cmpne r2,r2,zero + 100d078: 1000041e bne r2,zero,100d08c <__env_unlock+0x48> + { + lockid = -1; + 100d07c: 00bfffc4 movi r2,-1 + 100d080: d0a01615 stw r2,-32680(gp) + OSSemPost( alt_envsem ); + 100d084: d1278017 ldw r4,-25088(gp) + 100d088: 10132100 call 1013210 + } +#endif /* OS_THREAD_SAFE_NEWLIB */ +} + 100d08c: e037883a mov sp,fp + 100d090: dfc00117 ldw ra,4(sp) + 100d094: df000017 ldw fp,0(sp) + 100d098: dec00204 addi sp,sp,8 + 100d09c: f800283a ret + +0100d0a0 <__malloc_lock>: +/* + * + */ + +void __malloc_lock ( struct _reent *_r ) +{ + 100d0a0: deffdb04 addi sp,sp,-148 + 100d0a4: dfc02415 stw ra,144(sp) + 100d0a8: df002315 stw fp,140(sp) + 100d0ac: df002304 addi fp,sp,140 + 100d0b0: e13fff15 stw r4,-4(fp) + OS_TCB tcb; + OS_SEM_DATA semdata; + INT8U err; + int id; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 100d0b4: e03fe015 stw zero,-128(fp) +#endif + + if (OSRunning != OS_TRUE) + 100d0b8: 008040b4 movhi r2,258 + 100d0bc: 10b31044 addi r2,r2,-13247 + 100d0c0: 10800003 ldbu r2,0(r2) + 100d0c4: 10803fcc andi r2,r2,255 + 100d0c8: 10800058 cmpnei r2,r2,1 + 100d0cc: 1000311e bne r2,zero,100d194 <__malloc_lock+0xf4> + return; + + /* use our priority as a task id */ + + err = OSTaskQuery( OS_PRIO_SELF, &tcb ); + 100d0d0: e17fe204 addi r5,fp,-120 + 100d0d4: 01003fc4 movi r4,255 + 100d0d8: 1014dec0 call 1014dec + 100d0dc: e0bffe85 stb r2,-6(fp) + if (err != OS_NO_ERR) + 100d0e0: e0bffe83 ldbu r2,-6(fp) + 100d0e4: 10803fcc andi r2,r2,255 + 100d0e8: 1004c03a cmpne r2,r2,zero + 100d0ec: 1000291e bne r2,zero,100d194 <__malloc_lock+0xf4> + return; + + id = tcb.OSTCBPrio; + 100d0f0: e0bfee83 ldbu r2,-70(fp) + 100d0f4: 10803fcc andi r2,r2,255 + 100d0f8: e0bfe115 stw r2,-124(fp) + + /* see if we own the heap already */ + + OSSemQuery( alt_heapsem, &semdata ); + 100d0fc: d1278217 ldw r4,-25080(gp) + 100d100: e17ffd04 addi r5,fp,-12 + 100d104: 10133380 call 1013338 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 100d108: 0005303a rdctl r2,status + 100d10c: e0bfdf15 stw r2,-132(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 100d110: e0ffdf17 ldw r3,-132(fp) + 100d114: 00bfff84 movi r2,-2 + 100d118: 1884703a and r2,r3,r2 + 100d11c: 1001703a wrctl status,r2 + + return context; + 100d120: e0bfdf17 ldw r2,-132(fp) + + OS_ENTER_CRITICAL(); + 100d124: e0bfe015 stw r2,-128(fp) + + if( !semdata.OSCnt && id == lockid ) + 100d128: e0bffd0b ldhu r2,-12(fp) + 100d12c: 10bfffcc andi r2,r2,65535 + 100d130: 1004c03a cmpne r2,r2,zero + 100d134: 10000b1e bne r2,zero,100d164 <__malloc_lock+0xc4> + 100d138: d0e01717 ldw r3,-32676(gp) + 100d13c: e0bfe117 ldw r2,-124(fp) + 100d140: 10c0081e bne r2,r3,100d164 <__malloc_lock+0xc4> + { + /* we do; just count the recursion */ + locks++; + 100d144: d0a78117 ldw r2,-25084(gp) + 100d148: 10800044 addi r2,r2,1 + 100d14c: d0a78115 stw r2,-25084(gp) + 100d150: e0bfe017 ldw r2,-128(fp) + 100d154: e0bfde15 stw r2,-136(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 100d158: e0bfde17 ldw r2,-136(fp) + 100d15c: 1001703a wrctl status,r2 + + OSSemQuery( alt_heapsem, &semdata ); + + OS_ENTER_CRITICAL(); + + if( !semdata.OSCnt && id == lockid ) + 100d160: 00000c06 br 100d194 <__malloc_lock+0xf4> + 100d164: e0bfe017 ldw r2,-128(fp) + 100d168: e0bfdd15 stw r2,-140(fp) + 100d16c: e0bfdd17 ldw r2,-140(fp) + 100d170: 1001703a wrctl status,r2 + else + { + /* wait on the other task to yield the heap, then claim ownership of it */ + OS_EXIT_CRITICAL(); + + OSSemPend( alt_heapsem, 0, &err ); + 100d174: d1278217 ldw r4,-25080(gp) + 100d178: e1bffe84 addi r6,fp,-6 + 100d17c: 000b883a mov r5,zero + 100d180: 1012e180 call 1012e18 + locks = 1; + 100d184: 00800044 movi r2,1 + 100d188: d0a78115 stw r2,-25084(gp) + lockid = id; + 100d18c: e0bfe117 ldw r2,-124(fp) + 100d190: d0a01715 stw r2,-32676(gp) + } + +#endif /* OS_THREAD_SAFE_NEWLIB */ + return; +} + 100d194: e037883a mov sp,fp + 100d198: dfc00117 ldw ra,4(sp) + 100d19c: df000017 ldw fp,0(sp) + 100d1a0: dec00204 addi sp,sp,8 + 100d1a4: f800283a ret + +0100d1a8 <__malloc_unlock>: +/* + * + */ + +void __malloc_unlock ( struct _reent *_r ) +{ + 100d1a8: defff804 addi sp,sp,-32 + 100d1ac: dfc00715 stw ra,28(sp) + 100d1b0: df000615 stw fp,24(sp) + 100d1b4: df000604 addi fp,sp,24 + 100d1b8: e13fff15 stw r4,-4(fp) +#if OS_THREAD_SAFE_NEWLIB + +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 100d1bc: e03ffe15 stw zero,-8(fp) +#endif + + if (OSRunning != OS_TRUE) + 100d1c0: 008040b4 movhi r2,258 + 100d1c4: 10b31044 addi r2,r2,-13247 + 100d1c8: 10800003 ldbu r2,0(r2) + 100d1cc: 10803fcc andi r2,r2,255 + 100d1d0: 10800058 cmpnei r2,r2,1 + 100d1d4: 1000231e bne r2,zero,100d264 <__malloc_unlock+0xbc> +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 100d1d8: 0005303a rdctl r2,status + 100d1dc: e0bffd15 stw r2,-12(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 100d1e0: e0fffd17 ldw r3,-12(fp) + 100d1e4: 00bfff84 movi r2,-2 + 100d1e8: 1884703a and r2,r3,r2 + 100d1ec: 1001703a wrctl status,r2 + + return context; + 100d1f0: e0bffd17 ldw r2,-12(fp) + return; + + OS_ENTER_CRITICAL(); + 100d1f4: e0bffe15 stw r2,-8(fp) + if (locks == 0) + 100d1f8: d0a78117 ldw r2,-25084(gp) + 100d1fc: 1004c03a cmpne r2,r2,zero + 100d200: 1000051e bne r2,zero,100d218 <__malloc_unlock+0x70> + 100d204: e0bffe17 ldw r2,-8(fp) + 100d208: e0bffc15 stw r2,-16(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 100d20c: e0bffc17 ldw r2,-16(fp) + 100d210: 1001703a wrctl status,r2 + { + OS_EXIT_CRITICAL(); + return; + 100d214: 00001306 br 100d264 <__malloc_unlock+0xbc> + } + + /* release the heap once the number of locks == the number of unlocks */ + if( (--locks) == 0 ) + 100d218: d0a78117 ldw r2,-25084(gp) + 100d21c: 10bfffc4 addi r2,r2,-1 + 100d220: d0a78115 stw r2,-25084(gp) + 100d224: d0a78117 ldw r2,-25084(gp) + 100d228: 1004c03a cmpne r2,r2,zero + 100d22c: 1000091e bne r2,zero,100d254 <__malloc_unlock+0xac> + { + lockid = -1; + 100d230: 00bfffc4 movi r2,-1 + 100d234: d0a01715 stw r2,-32676(gp) + 100d238: e0bffe17 ldw r2,-8(fp) + 100d23c: e0bffb15 stw r2,-20(fp) + 100d240: e0bffb17 ldw r2,-20(fp) + 100d244: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + OSSemPost( alt_heapsem ); + 100d248: d1278217 ldw r4,-25080(gp) + 100d24c: 10132100 call 1013210 + 100d250: 00000406 br 100d264 <__malloc_unlock+0xbc> + 100d254: e0bffe17 ldw r2,-8(fp) + 100d258: e0bffa15 stw r2,-24(fp) + 100d25c: e0bffa17 ldw r2,-24(fp) + 100d260: 1001703a wrctl status,r2 + { + OS_EXIT_CRITICAL(); + } + +#endif /* OS_THREAD_SAFE_NEWLIB */ +} + 100d264: e037883a mov sp,fp + 100d268: dfc00117 ldw ra,4(sp) + 100d26c: df000017 ldw fp,0(sp) + 100d270: dec00204 addi sp,sp,8 + 100d274: f800283a ret + +0100d278 : +********************************************************************************************************* +*/ + +#if (OS_EVENT_EN) && (OS_EVENT_NAME_SIZE > 1) +INT8U OSEventNameGet (OS_EVENT *pevent, INT8U *pname, INT8U *perr) +{ + 100d278: defff604 addi sp,sp,-40 + 100d27c: dfc00915 stw ra,36(sp) + 100d280: df000815 stw fp,32(sp) + 100d284: df000804 addi fp,sp,32 + 100d288: e13ffc15 stw r4,-16(fp) + 100d28c: e17ffd15 stw r5,-12(fp) + 100d290: e1bffe15 stw r6,-8(fp) + INT8U len; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 100d294: e03ffa15 stw zero,-24(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + 100d298: e0bffe17 ldw r2,-8(fp) + 100d29c: 1004c03a cmpne r2,r2,zero + 100d2a0: 1000021e bne r2,zero,100d2ac + return (0); + 100d2a4: e03fff15 stw zero,-4(fp) + 100d2a8: 00003906 br 100d390 + } + if (pevent == (OS_EVENT *)0) { /* Is 'pevent' a NULL pointer? */ + 100d2ac: e0bffc17 ldw r2,-16(fp) + 100d2b0: 1004c03a cmpne r2,r2,zero + 100d2b4: 1000051e bne r2,zero,100d2cc + *perr = OS_ERR_PEVENT_NULL; + 100d2b8: e0fffe17 ldw r3,-8(fp) + 100d2bc: 00800104 movi r2,4 + 100d2c0: 18800005 stb r2,0(r3) + return (0); + 100d2c4: e03fff15 stw zero,-4(fp) + 100d2c8: 00003106 br 100d390 + } + if (pname == (INT8U *)0) { /* Is 'pname' a NULL pointer? */ + 100d2cc: e0bffd17 ldw r2,-12(fp) + 100d2d0: 1004c03a cmpne r2,r2,zero + 100d2d4: 1000051e bne r2,zero,100d2ec + *perr = OS_ERR_PNAME_NULL; + 100d2d8: e0fffe17 ldw r3,-8(fp) + 100d2dc: 00800304 movi r2,12 + 100d2e0: 18800005 stb r2,0(r3) + return (0); + 100d2e4: e03fff15 stw zero,-4(fp) + 100d2e8: 00002906 br 100d390 + } +#endif + if (OSIntNesting > 0) { /* See if trying to call from an ISR */ + 100d2ec: d0a79103 ldbu r2,-25020(gp) + 100d2f0: 10803fcc andi r2,r2,255 + 100d2f4: 1005003a cmpeq r2,r2,zero + 100d2f8: 1000051e bne r2,zero,100d310 + *perr = OS_ERR_NAME_GET_ISR; + 100d2fc: e0fffe17 ldw r3,-8(fp) + 100d300: 00800444 movi r2,17 + 100d304: 18800005 stb r2,0(r3) + return (0); + 100d308: e03fff15 stw zero,-4(fp) + 100d30c: 00002006 br 100d390 + } + switch (pevent->OSEventType) { + 100d310: e0bffc17 ldw r2,-16(fp) + 100d314: 10800003 ldbu r2,0(r2) + 100d318: 10803fcc andi r2,r2,255 + 100d31c: 10bfffc4 addi r2,r2,-1 + 100d320: 10800128 cmpgeui r2,r2,4 + 100d324: 1000161e bne r2,zero,100d380 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 100d328: 0005303a rdctl r2,status + 100d32c: e0bff915 stw r2,-28(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 100d330: e0fff917 ldw r3,-28(fp) + 100d334: 00bfff84 movi r2,-2 + 100d338: 1884703a and r2,r3,r2 + 100d33c: 1001703a wrctl status,r2 + + return context; + 100d340: e0bff917 ldw r2,-28(fp) + + default: + *perr = OS_ERR_EVENT_TYPE; + return (0); + } + OS_ENTER_CRITICAL(); + 100d344: e0bffa15 stw r2,-24(fp) + len = OS_StrCopy(pname, pevent->OSEventName); /* Copy name from OS_EVENT */ + 100d348: e0bffc17 ldw r2,-16(fp) + 100d34c: 11400384 addi r5,r2,14 + 100d350: e13ffd17 ldw r4,-12(fp) + 100d354: 100edfc0 call 100edfc + 100d358: e0bffb05 stb r2,-20(fp) + 100d35c: e0bffa17 ldw r2,-24(fp) + 100d360: e0bff815 stw r2,-32(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 100d364: e0bff817 ldw r2,-32(fp) + 100d368: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + 100d36c: e0bffe17 ldw r2,-8(fp) + 100d370: 10000005 stb zero,0(r2) + return (len); + 100d374: e0bffb03 ldbu r2,-20(fp) + 100d378: e0bfff15 stw r2,-4(fp) + 100d37c: 00000406 br 100d390 + case OS_EVENT_TYPE_MBOX: + case OS_EVENT_TYPE_Q: + break; + + default: + *perr = OS_ERR_EVENT_TYPE; + 100d380: e0fffe17 ldw r3,-8(fp) + 100d384: 00800044 movi r2,1 + 100d388: 18800005 stb r2,0(r3) + return (0); + 100d38c: e03fff15 stw zero,-4(fp) + 100d390: e0bfff17 ldw r2,-4(fp) + OS_ENTER_CRITICAL(); + len = OS_StrCopy(pname, pevent->OSEventName); /* Copy name from OS_EVENT */ + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + return (len); +} + 100d394: e037883a mov sp,fp + 100d398: dfc00117 ldw ra,4(sp) + 100d39c: df000017 ldw fp,0(sp) + 100d3a0: dec00204 addi sp,sp,8 + 100d3a4: f800283a ret + +0100d3a8 : +********************************************************************************************************* +*/ + +#if (OS_EVENT_EN) && (OS_EVENT_NAME_SIZE > 1) +void OSEventNameSet (OS_EVENT *pevent, INT8U *pname, INT8U *perr) +{ + 100d3a8: defff604 addi sp,sp,-40 + 100d3ac: dfc00915 stw ra,36(sp) + 100d3b0: df000815 stw fp,32(sp) + 100d3b4: df000804 addi fp,sp,32 + 100d3b8: e13ffd15 stw r4,-12(fp) + 100d3bc: e17ffe15 stw r5,-8(fp) + 100d3c0: e1bfff15 stw r6,-4(fp) + INT8U len; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 100d3c4: e03ffb15 stw zero,-20(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + 100d3c8: e0bfff17 ldw r2,-4(fp) + 100d3cc: 1005003a cmpeq r2,r2,zero + 100d3d0: 1000411e bne r2,zero,100d4d8 + return; + } + if (pevent == (OS_EVENT *)0) { /* Is 'pevent' a NULL pointer? */ + 100d3d4: e0bffd17 ldw r2,-12(fp) + 100d3d8: 1004c03a cmpne r2,r2,zero + 100d3dc: 1000041e bne r2,zero,100d3f0 + *perr = OS_ERR_PEVENT_NULL; + 100d3e0: e0ffff17 ldw r3,-4(fp) + 100d3e4: 00800104 movi r2,4 + 100d3e8: 18800005 stb r2,0(r3) + return; + 100d3ec: 00003a06 br 100d4d8 + } + if (pname == (INT8U *)0) { /* Is 'pname' a NULL pointer? */ + 100d3f0: e0bffe17 ldw r2,-8(fp) + 100d3f4: 1004c03a cmpne r2,r2,zero + 100d3f8: 1000041e bne r2,zero,100d40c + *perr = OS_ERR_PNAME_NULL; + 100d3fc: e0ffff17 ldw r3,-4(fp) + 100d400: 00800304 movi r2,12 + 100d404: 18800005 stb r2,0(r3) + return; + 100d408: 00003306 br 100d4d8 + } +#endif + if (OSIntNesting > 0) { /* See if trying to call from an ISR */ + 100d40c: d0a79103 ldbu r2,-25020(gp) + 100d410: 10803fcc andi r2,r2,255 + 100d414: 1005003a cmpeq r2,r2,zero + 100d418: 1000041e bne r2,zero,100d42c + *perr = OS_ERR_NAME_SET_ISR; + 100d41c: e0ffff17 ldw r3,-4(fp) + 100d420: 00800484 movi r2,18 + 100d424: 18800005 stb r2,0(r3) + return; + 100d428: 00002b06 br 100d4d8 + } + switch (pevent->OSEventType) { + 100d42c: e0bffd17 ldw r2,-12(fp) + 100d430: 10800003 ldbu r2,0(r2) + 100d434: 10803fcc andi r2,r2,255 + 100d438: 10bfffc4 addi r2,r2,-1 + 100d43c: 10800128 cmpgeui r2,r2,4 + 100d440: 10000f1e bne r2,zero,100d480 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 100d444: 0005303a rdctl r2,status + 100d448: e0bffa15 stw r2,-24(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 100d44c: e0fffa17 ldw r3,-24(fp) + 100d450: 00bfff84 movi r2,-2 + 100d454: 1884703a and r2,r3,r2 + 100d458: 1001703a wrctl status,r2 + + return context; + 100d45c: e0bffa17 ldw r2,-24(fp) + + default: + *perr = OS_ERR_EVENT_TYPE; + return; + } + OS_ENTER_CRITICAL(); + 100d460: e0bffb15 stw r2,-20(fp) + len = OS_StrLen(pname); /* Can we fit the string in the storage area? */ + 100d464: e13ffe17 ldw r4,-8(fp) + 100d468: 100ee7c0 call 100ee7c + 100d46c: e0bffc05 stb r2,-16(fp) + if (len > (OS_EVENT_NAME_SIZE - 1)) { /* No */ + 100d470: e0bffc03 ldbu r2,-16(fp) + 100d474: 10800828 cmpgeui r2,r2,32 + 100d478: 1000051e bne r2,zero,100d490 + 100d47c: 00000c06 br 100d4b0 + case OS_EVENT_TYPE_MBOX: + case OS_EVENT_TYPE_Q: + break; + + default: + *perr = OS_ERR_EVENT_TYPE; + 100d480: e0ffff17 ldw r3,-4(fp) + 100d484: 00800044 movi r2,1 + 100d488: 18800005 stb r2,0(r3) + return; + 100d48c: 00001206 br 100d4d8 + 100d490: e0bffb17 ldw r2,-20(fp) + 100d494: e0bff915 stw r2,-28(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 100d498: e0bff917 ldw r2,-28(fp) + 100d49c: 1001703a wrctl status,r2 + } + OS_ENTER_CRITICAL(); + len = OS_StrLen(pname); /* Can we fit the string in the storage area? */ + if (len > (OS_EVENT_NAME_SIZE - 1)) { /* No */ + OS_EXIT_CRITICAL(); + *perr = OS_ERR_EVENT_NAME_TOO_LONG; + 100d4a0: e0ffff17 ldw r3,-4(fp) + 100d4a4: 008002c4 movi r2,11 + 100d4a8: 18800005 stb r2,0(r3) + return; + 100d4ac: 00000a06 br 100d4d8 + } + (void)OS_StrCopy(pevent->OSEventName, pname); /* Yes, copy name to the event control block */ + 100d4b0: e0bffd17 ldw r2,-12(fp) + 100d4b4: 11000384 addi r4,r2,14 + 100d4b8: e17ffe17 ldw r5,-8(fp) + 100d4bc: 100edfc0 call 100edfc + 100d4c0: e0bffb17 ldw r2,-20(fp) + 100d4c4: e0bff815 stw r2,-32(fp) + 100d4c8: e0bff817 ldw r2,-32(fp) + 100d4cc: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + 100d4d0: e0bfff17 ldw r2,-4(fp) + 100d4d4: 10000005 stb zero,0(r2) +} + 100d4d8: e037883a mov sp,fp + 100d4dc: dfc00117 ldw ra,4(sp) + 100d4e0: df000017 ldw fp,0(sp) + 100d4e4: dec00204 addi sp,sp,8 + 100d4e8: f800283a ret + +0100d4ec : +********************************************************************************************************* +*/ +/*$PAGE*/ +#if ((OS_EVENT_EN) && (OS_EVENT_MULTI_EN > 0)) +INT16U OSEventPendMulti (OS_EVENT **pevents_pend, OS_EVENT **pevents_rdy, void **pmsgs_rdy, INT16U timeout, INT8U *perr) +{ + 100d4ec: deffe704 addi sp,sp,-100 + 100d4f0: dfc01815 stw ra,96(sp) + 100d4f4: df001715 stw fp,92(sp) + 100d4f8: df001704 addi fp,sp,92 + 100d4fc: e13ff615 stw r4,-40(fp) + 100d500: e17ff715 stw r5,-36(fp) + 100d504: e1bff815 stw r6,-32(fp) + 100d508: e1fff90d sth r7,-28(fp) +#endif + BOOLEAN events_rdy; + INT16U events_rdy_nbr; + INT8U events_stat; +#if (OS_CRITICAL_METHOD == 3) /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 100d50c: e03ff015 stw zero,-64(fp) +#endif + + + +#if (OS_ARG_CHK_EN > 0) + if (perr == (INT8U *)0) { /* Validate 'perr' */ + 100d510: e0800217 ldw r2,8(fp) + 100d514: 1004c03a cmpne r2,r2,zero + 100d518: 1000021e bne r2,zero,100d524 + return (0); + 100d51c: e03fff15 stw zero,-4(fp) + 100d520: 00019906 br 100db88 + } + if (pevents_pend == (OS_EVENT **)0) { /* Validate 'pevents_pend' */ + 100d524: e0bff617 ldw r2,-40(fp) + 100d528: 1004c03a cmpne r2,r2,zero + 100d52c: 1000051e bne r2,zero,100d544 + *perr = OS_ERR_PEVENT_NULL; + 100d530: e0c00217 ldw r3,8(fp) + 100d534: 00800104 movi r2,4 + 100d538: 18800005 stb r2,0(r3) + return (0); + 100d53c: e03fff15 stw zero,-4(fp) + 100d540: 00019106 br 100db88 + } + if (pevents_rdy == (OS_EVENT **)0) { /* Validate 'pevents_rdy' */ + 100d544: e0bff717 ldw r2,-36(fp) + 100d548: 1004c03a cmpne r2,r2,zero + 100d54c: 1000051e bne r2,zero,100d564 + *perr = OS_ERR_PEVENT_NULL; + 100d550: e0c00217 ldw r3,8(fp) + 100d554: 00800104 movi r2,4 + 100d558: 18800005 stb r2,0(r3) + return (0); + 100d55c: e03fff15 stw zero,-4(fp) + 100d560: 00018906 br 100db88 + } + if (pmsgs_rdy == (void **)0) { /* Validate 'pmsgs_rdy' */ + 100d564: e0bff817 ldw r2,-32(fp) + 100d568: 1004c03a cmpne r2,r2,zero + 100d56c: 1000051e bne r2,zero,100d584 + *perr = OS_ERR_PEVENT_NULL; + 100d570: e0c00217 ldw r3,8(fp) + 100d574: 00800104 movi r2,4 + 100d578: 18800005 stb r2,0(r3) + return (0); + 100d57c: e03fff15 stw zero,-4(fp) + 100d580: 00018106 br 100db88 + } +#endif + + *pevents_rdy = (OS_EVENT *)0; /* Init array to NULL in case of errors */ + 100d584: e0bff717 ldw r2,-36(fp) + 100d588: 10000015 stw zero,0(r2) + + pevents = pevents_pend; + 100d58c: e0bff617 ldw r2,-40(fp) + 100d590: e0bff515 stw r2,-44(fp) + pevent = *pevents; + 100d594: e0bff517 ldw r2,-44(fp) + 100d598: 10800017 ldw r2,0(r2) + 100d59c: e0bff415 stw r2,-48(fp) + while (pevent != (OS_EVENT *)0) { + 100d5a0: 00001806 br 100d604 + switch (pevent->OSEventType) { /* Validate event block types */ + 100d5a4: e0bff417 ldw r2,-48(fp) + 100d5a8: 10800003 ldbu r2,0(r2) + 100d5ac: 10803fcc andi r2,r2,255 + 100d5b0: e0bffe15 stw r2,-8(fp) + 100d5b4: e0fffe17 ldw r3,-8(fp) + 100d5b8: 188000a0 cmpeqi r2,r3,2 + 100d5bc: 10000b1e bne r2,zero,100d5ec + 100d5c0: e0fffe17 ldw r3,-8(fp) + 100d5c4: 188000e0 cmpeqi r2,r3,3 + 100d5c8: 1000081e bne r2,zero,100d5ec + 100d5cc: e0fffe17 ldw r3,-8(fp) + 100d5d0: 18800060 cmpeqi r2,r3,1 + 100d5d4: 1000051e bne r2,zero,100d5ec +#endif + + case OS_EVENT_TYPE_MUTEX: + case OS_EVENT_TYPE_FLAG: + default: + *perr = OS_ERR_EVENT_TYPE; + 100d5d8: e0c00217 ldw r3,8(fp) + 100d5dc: 00800044 movi r2,1 + 100d5e0: 18800005 stb r2,0(r3) + return (0); + 100d5e4: e03fff15 stw zero,-4(fp) + 100d5e8: 00016706 br 100db88 + } + pevents++; + 100d5ec: e0bff517 ldw r2,-44(fp) + 100d5f0: 10800104 addi r2,r2,4 + 100d5f4: e0bff515 stw r2,-44(fp) + pevent = *pevents; + 100d5f8: e0bff517 ldw r2,-44(fp) + 100d5fc: 10800017 ldw r2,0(r2) + 100d600: e0bff415 stw r2,-48(fp) + + *pevents_rdy = (OS_EVENT *)0; /* Init array to NULL in case of errors */ + + pevents = pevents_pend; + pevent = *pevents; + while (pevent != (OS_EVENT *)0) { + 100d604: e0bff417 ldw r2,-48(fp) + 100d608: 1004c03a cmpne r2,r2,zero + 100d60c: 103fe51e bne r2,zero,100d5a4 + } + pevents++; + pevent = *pevents; + } + + if (OSIntNesting > 0) { /* See if called from ISR ... */ + 100d610: d0a79103 ldbu r2,-25020(gp) + 100d614: 10803fcc andi r2,r2,255 + 100d618: 1005003a cmpeq r2,r2,zero + 100d61c: 1000051e bne r2,zero,100d634 + *perr = OS_ERR_PEND_ISR; /* ... can't PEND from an ISR */ + 100d620: e0c00217 ldw r3,8(fp) + 100d624: 00800084 movi r2,2 + 100d628: 18800005 stb r2,0(r3) + return (0); + 100d62c: e03fff15 stw zero,-4(fp) + 100d630: 00015506 br 100db88 + } + if (OSLockNesting > 0) { /* See if called with scheduler locked ... */ + 100d634: d0a78303 ldbu r2,-25076(gp) + 100d638: 10803fcc andi r2,r2,255 + 100d63c: 1005003a cmpeq r2,r2,zero + 100d640: 1000051e bne r2,zero,100d658 + *perr = OS_ERR_PEND_LOCKED; /* ... can't PEND when locked */ + 100d644: e0c00217 ldw r3,8(fp) + 100d648: 00800344 movi r2,13 + 100d64c: 18800005 stb r2,0(r3) + return (0); + 100d650: e03fff15 stw zero,-4(fp) + 100d654: 00014c06 br 100db88 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 100d658: 0005303a rdctl r2,status + 100d65c: e0bfef15 stw r2,-68(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 100d660: e0ffef17 ldw r3,-68(fp) + 100d664: 00bfff84 movi r2,-2 + 100d668: 1884703a and r2,r3,r2 + 100d66c: 1001703a wrctl status,r2 + + return context; + 100d670: e0bfef17 ldw r2,-68(fp) + } + +/*$PAGE*/ + OS_ENTER_CRITICAL(); + 100d674: e0bff015 stw r2,-64(fp) + events_rdy = OS_FALSE; + 100d678: e03ff205 stb zero,-56(fp) + events_rdy_nbr = 0; + 100d67c: e03ff18d sth zero,-58(fp) + events_stat = OS_STAT_RDY; + 100d680: e03ff105 stb zero,-60(fp) + pevents = pevents_pend; + 100d684: e0bff617 ldw r2,-40(fp) + 100d688: e0bff515 stw r2,-44(fp) + pevent = *pevents; + 100d68c: e0bff517 ldw r2,-44(fp) + 100d690: 10800017 ldw r2,0(r2) + 100d694: e0bff415 stw r2,-48(fp) + while (pevent != (OS_EVENT *)0) { /* See if any events already available */ + 100d698: 00008f06 br 100d8d8 + switch (pevent->OSEventType) { + 100d69c: e0bff417 ldw r2,-48(fp) + 100d6a0: 10800003 ldbu r2,0(r2) + 100d6a4: 10803fcc andi r2,r2,255 + 100d6a8: e0bffd15 stw r2,-12(fp) + 100d6ac: e0fffd17 ldw r3,-12(fp) + 100d6b0: 188000a0 cmpeqi r2,r3,2 + 100d6b4: 1000441e bne r2,zero,100d7c8 + 100d6b8: e0fffd17 ldw r3,-12(fp) + 100d6bc: 188000e0 cmpeqi r2,r3,3 + 100d6c0: 1000041e bne r2,zero,100d6d4 + 100d6c4: e0fffd17 ldw r3,-12(fp) + 100d6c8: 18800060 cmpeqi r2,r3,1 + 100d6cc: 1000211e bne r2,zero,100d754 + 100d6d0: 00006f06 br 100d890 +#if (OS_SEM_EN > 0) + case OS_EVENT_TYPE_SEM: + if (pevent->OSEventCnt > 0) { /* If semaphore count > 0, resource available; */ + 100d6d4: e0bff417 ldw r2,-48(fp) + 100d6d8: 1080020b ldhu r2,8(r2) + 100d6dc: 10bfffcc andi r2,r2,65535 + 100d6e0: 1005003a cmpeq r2,r2,zero + 100d6e4: 1000171e bne r2,zero,100d744 + pevent->OSEventCnt--; /* ... decrement semaphore, ... */ + 100d6e8: e0bff417 ldw r2,-48(fp) + 100d6ec: 1080020b ldhu r2,8(r2) + 100d6f0: 10bfffc4 addi r2,r2,-1 + 100d6f4: 1007883a mov r3,r2 + 100d6f8: e0bff417 ldw r2,-48(fp) + 100d6fc: 10c0020d sth r3,8(r2) + *pevents_rdy++ = pevent; /* ... and return available semaphore event */ + 100d700: e0fff717 ldw r3,-36(fp) + 100d704: e0bff417 ldw r2,-48(fp) + 100d708: 18800015 stw r2,0(r3) + 100d70c: e0bff717 ldw r2,-36(fp) + 100d710: 10800104 addi r2,r2,4 + 100d714: e0bff715 stw r2,-36(fp) + events_rdy = OS_TRUE; + 100d718: 00800044 movi r2,1 + 100d71c: e0bff205 stb r2,-56(fp) + *pmsgs_rdy++ = (void *)0; /* NO message returned for semaphores */ + 100d720: e0bff817 ldw r2,-32(fp) + 100d724: 10000015 stw zero,0(r2) + 100d728: e0bff817 ldw r2,-32(fp) + 100d72c: 10800104 addi r2,r2,4 + 100d730: e0bff815 stw r2,-32(fp) + events_rdy_nbr++; + 100d734: e0bff18b ldhu r2,-58(fp) + 100d738: 10800044 addi r2,r2,1 + 100d73c: e0bff18d sth r2,-58(fp) + 100d740: 00005f06 br 100d8c0 + + } else { + events_stat |= OS_STAT_SEM; /* Configure multi-pend for semaphore events */ + 100d744: e0bff103 ldbu r2,-60(fp) + 100d748: 10800054 ori r2,r2,1 + 100d74c: e0bff105 stb r2,-60(fp) + } + break; + 100d750: 00005b06 br 100d8c0 +#endif + +#if (OS_MBOX_EN > 0) + case OS_EVENT_TYPE_MBOX: + if (pevent->OSEventPtr != (void *)0) { /* If mailbox NOT empty; ... */ + 100d754: e0bff417 ldw r2,-48(fp) + 100d758: 10800117 ldw r2,4(r2) + 100d75c: 1005003a cmpeq r2,r2,zero + 100d760: 1000151e bne r2,zero,100d7b8 + /* ... return available message, ... */ + *pmsgs_rdy++ = (void *)pevent->OSEventPtr; + 100d764: e0bff417 ldw r2,-48(fp) + 100d768: 10c00117 ldw r3,4(r2) + 100d76c: e0bff817 ldw r2,-32(fp) + 100d770: 10c00015 stw r3,0(r2) + 100d774: e0bff817 ldw r2,-32(fp) + 100d778: 10800104 addi r2,r2,4 + 100d77c: e0bff815 stw r2,-32(fp) + pevent->OSEventPtr = (void *)0; + 100d780: e0bff417 ldw r2,-48(fp) + 100d784: 10000115 stw zero,4(r2) + *pevents_rdy++ = pevent; /* ... and return available mailbox event */ + 100d788: e0fff717 ldw r3,-36(fp) + 100d78c: e0bff417 ldw r2,-48(fp) + 100d790: 18800015 stw r2,0(r3) + 100d794: e0bff717 ldw r2,-36(fp) + 100d798: 10800104 addi r2,r2,4 + 100d79c: e0bff715 stw r2,-36(fp) + events_rdy = OS_TRUE; + 100d7a0: 00800044 movi r2,1 + 100d7a4: e0bff205 stb r2,-56(fp) + events_rdy_nbr++; + 100d7a8: e0bff18b ldhu r2,-58(fp) + 100d7ac: 10800044 addi r2,r2,1 + 100d7b0: e0bff18d sth r2,-58(fp) + 100d7b4: 00004206 br 100d8c0 + + } else { + events_stat |= OS_STAT_MBOX; /* Configure multi-pend for mailbox events */ + 100d7b8: e0bff103 ldbu r2,-60(fp) + 100d7bc: 10800094 ori r2,r2,2 + 100d7c0: e0bff105 stb r2,-60(fp) + } + break; + 100d7c4: 00003e06 br 100d8c0 +#endif + +#if ((OS_Q_EN > 0) && (OS_MAX_QS > 0)) + case OS_EVENT_TYPE_Q: + pq = (OS_Q *)pevent->OSEventPtr; + 100d7c8: e0bff417 ldw r2,-48(fp) + 100d7cc: 10800117 ldw r2,4(r2) + 100d7d0: e0bff315 stw r2,-52(fp) + if (pq->OSQEntries > 0) { /* If queue NOT empty; ... */ + 100d7d4: e0bff317 ldw r2,-52(fp) + 100d7d8: 1080058b ldhu r2,22(r2) + 100d7dc: 10bfffcc andi r2,r2,65535 + 100d7e0: 1005003a cmpeq r2,r2,zero + 100d7e4: 1000261e bne r2,zero,100d880 + /* ... return available message, ... */ + *pmsgs_rdy++ = (void *)*pq->OSQOut++; + 100d7e8: e0bff317 ldw r2,-52(fp) + 100d7ec: 11000417 ldw r4,16(r2) + 100d7f0: 20c00017 ldw r3,0(r4) + 100d7f4: e0bff817 ldw r2,-32(fp) + 100d7f8: 10c00015 stw r3,0(r2) + 100d7fc: e0bff817 ldw r2,-32(fp) + 100d800: 10800104 addi r2,r2,4 + 100d804: e0bff815 stw r2,-32(fp) + 100d808: 20c00104 addi r3,r4,4 + 100d80c: e0bff317 ldw r2,-52(fp) + 100d810: 10c00415 stw r3,16(r2) + if (pq->OSQOut == pq->OSQEnd) { /* If OUT ptr at queue end, ... */ + 100d814: e0bff317 ldw r2,-52(fp) + 100d818: 10c00417 ldw r3,16(r2) + 100d81c: e0bff317 ldw r2,-52(fp) + 100d820: 10800217 ldw r2,8(r2) + 100d824: 1880041e bne r3,r2,100d838 + pq->OSQOut = pq->OSQStart; /* ... wrap to queue start */ + 100d828: e0bff317 ldw r2,-52(fp) + 100d82c: 10c00117 ldw r3,4(r2) + 100d830: e0bff317 ldw r2,-52(fp) + 100d834: 10c00415 stw r3,16(r2) + } + pq->OSQEntries--; /* Update number of queue entries */ + 100d838: e0bff317 ldw r2,-52(fp) + 100d83c: 1080058b ldhu r2,22(r2) + 100d840: 10bfffc4 addi r2,r2,-1 + 100d844: 1007883a mov r3,r2 + 100d848: e0bff317 ldw r2,-52(fp) + 100d84c: 10c0058d sth r3,22(r2) + *pevents_rdy++ = pevent; /* ... and return available queue event */ + 100d850: e0fff717 ldw r3,-36(fp) + 100d854: e0bff417 ldw r2,-48(fp) + 100d858: 18800015 stw r2,0(r3) + 100d85c: e0bff717 ldw r2,-36(fp) + 100d860: 10800104 addi r2,r2,4 + 100d864: e0bff715 stw r2,-36(fp) + events_rdy = OS_TRUE; + 100d868: 00800044 movi r2,1 + 100d86c: e0bff205 stb r2,-56(fp) + events_rdy_nbr++; + 100d870: e0bff18b ldhu r2,-58(fp) + 100d874: 10800044 addi r2,r2,1 + 100d878: e0bff18d sth r2,-58(fp) + 100d87c: 00001006 br 100d8c0 + + } else { + events_stat |= OS_STAT_Q; /* Configure multi-pend for queue events */ + 100d880: e0bff103 ldbu r2,-60(fp) + 100d884: 10800114 ori r2,r2,4 + 100d888: e0bff105 stb r2,-60(fp) + } + break; + 100d88c: 00000c06 br 100d8c0 + 100d890: e0bff017 ldw r2,-64(fp) + 100d894: e0bfee15 stw r2,-72(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 100d898: e0bfee17 ldw r2,-72(fp) + 100d89c: 1001703a wrctl status,r2 + + case OS_EVENT_TYPE_MUTEX: + case OS_EVENT_TYPE_FLAG: + default: + OS_EXIT_CRITICAL(); + *pevents_rdy = (OS_EVENT *)0; /* NULL terminate return event array */ + 100d8a0: e0bff717 ldw r2,-36(fp) + 100d8a4: 10000015 stw zero,0(r2) + *perr = OS_ERR_EVENT_TYPE; + 100d8a8: e0c00217 ldw r3,8(fp) + 100d8ac: 00800044 movi r2,1 + 100d8b0: 18800005 stb r2,0(r3) + return (events_rdy_nbr); + 100d8b4: e0bff18b ldhu r2,-58(fp) + 100d8b8: e0bfff15 stw r2,-4(fp) + 100d8bc: 0000b206 br 100db88 + } + pevents++; + 100d8c0: e0bff517 ldw r2,-44(fp) + 100d8c4: 10800104 addi r2,r2,4 + 100d8c8: e0bff515 stw r2,-44(fp) + pevent = *pevents; + 100d8cc: e0bff517 ldw r2,-44(fp) + 100d8d0: 10800017 ldw r2,0(r2) + 100d8d4: e0bff415 stw r2,-48(fp) + events_rdy = OS_FALSE; + events_rdy_nbr = 0; + events_stat = OS_STAT_RDY; + pevents = pevents_pend; + pevent = *pevents; + while (pevent != (OS_EVENT *)0) { /* See if any events already available */ + 100d8d8: e0bff417 ldw r2,-48(fp) + 100d8dc: 1004c03a cmpne r2,r2,zero + 100d8e0: 103f6e1e bne r2,zero,100d69c + } + pevents++; + pevent = *pevents; + } + + if ( events_rdy == OS_TRUE) { /* Return any events already available */ + 100d8e4: e0bff203 ldbu r2,-56(fp) + 100d8e8: 10800058 cmpnei r2,r2,1 + 100d8ec: 10000b1e bne r2,zero,100d91c + *pevents_rdy = (OS_EVENT *)0; /* NULL terminate return event array */ + 100d8f0: e0bff717 ldw r2,-36(fp) + 100d8f4: 10000015 stw zero,0(r2) + 100d8f8: e0bff017 ldw r2,-64(fp) + 100d8fc: e0bfed15 stw r2,-76(fp) + 100d900: e0bfed17 ldw r2,-76(fp) + 100d904: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + 100d908: e0800217 ldw r2,8(fp) + 100d90c: 10000005 stb zero,0(r2) + return (events_rdy_nbr); + 100d910: e0fff18b ldhu r3,-58(fp) + 100d914: e0ffff15 stw r3,-4(fp) + 100d918: 00009b06 br 100db88 + } +/*$PAGE*/ + /* Otherwise, must wait until any event occurs */ + OSTCBCur->OSTCBStat |= events_stat | /* Resource not available, ... */ + 100d91c: d1279217 ldw r4,-25016(gp) + 100d920: d0a79217 ldw r2,-25016(gp) + 100d924: 10c00c03 ldbu r3,48(r2) + 100d928: e0bff103 ldbu r2,-60(fp) + 100d92c: 1884b03a or r2,r3,r2 + 100d930: 1007883a mov r3,r2 + 100d934: 00bfe004 movi r2,-128 + 100d938: 1884b03a or r2,r3,r2 + 100d93c: 20800c05 stb r2,48(r4) + OS_STAT_MULTI; /* ... pend on multiple events */ + OSTCBCur->OSTCBStatPend = OS_STAT_PEND_OK; + 100d940: d0a79217 ldw r2,-25016(gp) + 100d944: 10000c45 stb zero,49(r2) + OSTCBCur->OSTCBDly = timeout; /* Store pend timeout in TCB */ + 100d948: d0e79217 ldw r3,-25016(gp) + 100d94c: e0bff90b ldhu r2,-28(fp) + 100d950: 18800b8d sth r2,46(r3) + OS_EventTaskWaitMulti(pevents_pend); /* Suspend task until events or timeout occurs */ + 100d954: e13ff617 ldw r4,-40(fp) + 100d958: 100e51c0 call 100e51c + 100d95c: e0bff017 ldw r2,-64(fp) + 100d960: e0bfec15 stw r2,-80(fp) + 100d964: e0bfec17 ldw r2,-80(fp) + 100d968: 1001703a wrctl status,r2 + + OS_EXIT_CRITICAL(); + OS_Sched(); /* Find next highest priority task ready */ + 100d96c: 100ecb80 call 100ecb8 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 100d970: 0005303a rdctl r2,status + 100d974: e0bfeb15 stw r2,-84(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 100d978: e0ffeb17 ldw r3,-84(fp) + 100d97c: 00bfff84 movi r2,-2 + 100d980: 1884703a and r2,r3,r2 + 100d984: 1001703a wrctl status,r2 + + return context; + 100d988: e0bfeb17 ldw r2,-84(fp) + OS_ENTER_CRITICAL(); + 100d98c: e0bff015 stw r2,-64(fp) + + switch (OSTCBCur->OSTCBStatPend) { /* Handle event posted, aborted, or timed-out */ + 100d990: d0a79217 ldw r2,-25016(gp) + 100d994: 10800c43 ldbu r2,49(r2) + 100d998: 10803fcc andi r2,r2,255 + 100d99c: e0bffc15 stw r2,-16(fp) + 100d9a0: e0fffc17 ldw r3,-16(fp) + 100d9a4: 1805003a cmpeq r2,r3,zero + 100d9a8: 1000041e bne r2,zero,100d9bc + 100d9ac: e0fffc17 ldw r3,-16(fp) + 100d9b0: 188000a0 cmpeqi r2,r3,2 + 100d9b4: 1000011e bne r2,zero,100d9bc + 100d9b8: 00001906 br 100da20 + case OS_STAT_PEND_OK: + case OS_STAT_PEND_ABORT: + pevent = OSTCBCur->OSTCBEventPtr; + 100d9bc: d0a79217 ldw r2,-25016(gp) + 100d9c0: 10800717 ldw r2,28(r2) + 100d9c4: e0bff415 stw r2,-48(fp) + if (pevent != (OS_EVENT *)0) { /* If task event ptr != NULL, ... */ + 100d9c8: e0bff417 ldw r2,-48(fp) + 100d9cc: 1005003a cmpeq r2,r2,zero + 100d9d0: 10000c1e bne r2,zero,100da04 + *pevents_rdy++ = pevent; /* ... return available event ... */ + 100d9d4: e0fff717 ldw r3,-36(fp) + 100d9d8: e0bff417 ldw r2,-48(fp) + 100d9dc: 18800015 stw r2,0(r3) + 100d9e0: e0bff717 ldw r2,-36(fp) + 100d9e4: 10800104 addi r2,r2,4 + 100d9e8: e0bff715 stw r2,-36(fp) + *pevents_rdy = (OS_EVENT *)0; /* ... & NULL terminate return event array */ + 100d9ec: e0bff717 ldw r2,-36(fp) + 100d9f0: 10000015 stw zero,0(r2) + events_rdy_nbr++; + 100d9f4: e0bff18b ldhu r2,-58(fp) + 100d9f8: 10800044 addi r2,r2,1 + 100d9fc: e0bff18d sth r2,-58(fp) + 100da00: 00000a06 br 100da2c + + } else { /* Else NO event available, handle as timeout */ + OSTCBCur->OSTCBStatPend = OS_STAT_PEND_TO; + 100da04: d0a79217 ldw r2,-25016(gp) + 100da08: 00c00044 movi r3,1 + 100da0c: 10c00c45 stb r3,49(r2) + OS_EventTaskRemoveMulti(OSTCBCur, pevents_pend); + 100da10: d1279217 ldw r4,-25016(gp) + 100da14: e17ff617 ldw r5,-40(fp) + 100da18: 100e7280 call 100e728 + } + break; + 100da1c: 00000306 br 100da2c + + case OS_STAT_PEND_TO: + default: /* ... remove task from events' wait lists */ + OS_EventTaskRemoveMulti(OSTCBCur, pevents_pend); + 100da20: d1279217 ldw r4,-25016(gp) + 100da24: e17ff617 ldw r5,-40(fp) + 100da28: 100e7280 call 100e728 + break; + } + + switch (OSTCBCur->OSTCBStatPend) { + 100da2c: d0a79217 ldw r2,-25016(gp) + 100da30: 10800c43 ldbu r2,49(r2) + 100da34: 10803fcc andi r2,r2,255 + 100da38: e0bffb15 stw r2,-20(fp) + 100da3c: e0fffb17 ldw r3,-20(fp) + 100da40: 1805003a cmpeq r2,r3,zero + 100da44: 1000041e bne r2,zero,100da58 + 100da48: e0fffb17 ldw r3,-20(fp) + 100da4c: 188000a0 cmpeqi r2,r3,2 + 100da50: 10002c1e bne r2,zero,100db04 + 100da54: 00003406 br 100db28 + case OS_STAT_PEND_OK: + switch (pevent->OSEventType) { /* Return event's message */ + 100da58: e0bff417 ldw r2,-48(fp) + 100da5c: 10800003 ldbu r2,0(r2) + 100da60: 10803fcc andi r2,r2,255 + 100da64: e0bffa15 stw r2,-24(fp) + 100da68: e0fffa17 ldw r3,-24(fp) + 100da6c: 18800050 cmplti r2,r3,1 + 100da70: 1000151e bne r2,zero,100dac8 + 100da74: e0fffa17 ldw r3,-24(fp) + 100da78: 188000d0 cmplti r2,r3,3 + 100da7c: 10000a1e bne r2,zero,100daa8 + 100da80: e0fffa17 ldw r3,-24(fp) + 100da84: 188000e0 cmpeqi r2,r3,3 + 100da88: 1000011e bne r2,zero,100da90 + 100da8c: 00000e06 br 100dac8 +#if (OS_SEM_EN > 0) + case OS_EVENT_TYPE_SEM: + *pmsgs_rdy++ = (void *)0; /* NO message returned for semaphores */ + 100da90: e0bff817 ldw r2,-32(fp) + 100da94: 10000015 stw zero,0(r2) + 100da98: e0bff817 ldw r2,-32(fp) + 100da9c: 10800104 addi r2,r2,4 + 100daa0: e0bff815 stw r2,-32(fp) + break; + 100daa4: 00001406 br 100daf8 + +#if ((OS_MBOX_EN > 0) || \ + ((OS_Q_EN > 0) && (OS_MAX_QS > 0))) + case OS_EVENT_TYPE_MBOX: + case OS_EVENT_TYPE_Q: + *pmsgs_rdy++ = (void *)OSTCBCur->OSTCBMsg; /* Return received message */ + 100daa8: d0a79217 ldw r2,-25016(gp) + 100daac: 10c00917 ldw r3,36(r2) + 100dab0: e0bff817 ldw r2,-32(fp) + 100dab4: 10c00015 stw r3,0(r2) + 100dab8: e0bff817 ldw r2,-32(fp) + 100dabc: 10800104 addi r2,r2,4 + 100dac0: e0bff815 stw r2,-32(fp) + break; + 100dac4: 00000c06 br 100daf8 + 100dac8: e0bff017 ldw r2,-64(fp) + 100dacc: e0bfea15 stw r2,-88(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 100dad0: e0bfea17 ldw r2,-88(fp) + 100dad4: 1001703a wrctl status,r2 + + case OS_EVENT_TYPE_MUTEX: + case OS_EVENT_TYPE_FLAG: + default: + OS_EXIT_CRITICAL(); + *pevents_rdy = (OS_EVENT *)0; /* NULL terminate return event array */ + 100dad8: e0bff717 ldw r2,-36(fp) + 100dadc: 10000015 stw zero,0(r2) + *perr = OS_ERR_EVENT_TYPE; + 100dae0: e0c00217 ldw r3,8(fp) + 100dae4: 00800044 movi r2,1 + 100dae8: 18800005 stb r2,0(r3) + return (events_rdy_nbr); + 100daec: e0bff18b ldhu r2,-58(fp) + 100daf0: e0bfff15 stw r2,-4(fp) + 100daf4: 00002406 br 100db88 + } + *perr = OS_ERR_NONE; + 100daf8: e0800217 ldw r2,8(fp) + 100dafc: 10000005 stb zero,0(r2) + break; + 100db00: 00001106 br 100db48 + + case OS_STAT_PEND_ABORT: + *pmsgs_rdy++ = (void *)0; /* NO message returned for abort */ + 100db04: e0bff817 ldw r2,-32(fp) + 100db08: 10000015 stw zero,0(r2) + 100db0c: e0bff817 ldw r2,-32(fp) + 100db10: 10800104 addi r2,r2,4 + 100db14: e0bff815 stw r2,-32(fp) + *perr = OS_ERR_PEND_ABORT; /* Indicate that event aborted */ + 100db18: e0c00217 ldw r3,8(fp) + 100db1c: 00800384 movi r2,14 + 100db20: 18800005 stb r2,0(r3) + break; + 100db24: 00000806 br 100db48 + + case OS_STAT_PEND_TO: + default: + *pmsgs_rdy++ = (void *)0; /* NO message returned for timeout */ + 100db28: e0bff817 ldw r2,-32(fp) + 100db2c: 10000015 stw zero,0(r2) + 100db30: e0bff817 ldw r2,-32(fp) + 100db34: 10800104 addi r2,r2,4 + 100db38: e0bff815 stw r2,-32(fp) + *perr = OS_ERR_TIMEOUT; /* Indicate that events timed out */ + 100db3c: e0c00217 ldw r3,8(fp) + 100db40: 00800284 movi r2,10 + 100db44: 18800005 stb r2,0(r3) + break; + } + + OSTCBCur->OSTCBStat = OS_STAT_RDY; /* Set task status to ready */ + 100db48: d0a79217 ldw r2,-25016(gp) + 100db4c: 10000c05 stb zero,48(r2) + OSTCBCur->OSTCBStatPend = OS_STAT_PEND_OK; /* Clear pend status */ + 100db50: d0a79217 ldw r2,-25016(gp) + 100db54: 10000c45 stb zero,49(r2) + OSTCBCur->OSTCBEventPtr = (OS_EVENT *)0; /* Clear event pointers */ + 100db58: d0a79217 ldw r2,-25016(gp) + 100db5c: 10000715 stw zero,28(r2) + OSTCBCur->OSTCBEventMultiPtr = (OS_EVENT **)0; + 100db60: d0a79217 ldw r2,-25016(gp) + 100db64: 10000815 stw zero,32(r2) + OSTCBCur->OSTCBMsg = (void *)0; /* Clear task message */ + 100db68: d0a79217 ldw r2,-25016(gp) + 100db6c: 10000915 stw zero,36(r2) + 100db70: e0bff017 ldw r2,-64(fp) + 100db74: e0bfe915 stw r2,-92(fp) + 100db78: e0bfe917 ldw r2,-92(fp) + 100db7c: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + + return (events_rdy_nbr); + 100db80: e0fff18b ldhu r3,-58(fp) + 100db84: e0ffff15 stw r3,-4(fp) + 100db88: e0bfff17 ldw r2,-4(fp) +} + 100db8c: e037883a mov sp,fp + 100db90: dfc00117 ldw ra,4(sp) + 100db94: df000017 ldw fp,0(sp) + 100db98: dec00204 addi sp,sp,8 + 100db9c: f800283a ret + +0100dba0 : +* Returns : none +********************************************************************************************************* +*/ + +void OSInit (void) +{ + 100dba0: defffe04 addi sp,sp,-8 + 100dba4: dfc00115 stw ra,4(sp) + 100dba8: df000015 stw fp,0(sp) + 100dbac: d839883a mov fp,sp + OSInitHookBegin(); /* Call port specific initialization code */ + 100dbb0: 10184a00 call 10184a0 + + OS_InitMisc(); /* Initialize miscellaneous variables */ + 100dbb4: 100e9700 call 100e970 + + OS_InitRdyList(); /* Initialize the Ready List */ + 100dbb8: 100e9b40 call 100e9b4 + + OS_InitTCBList(); /* Initialize the free list of OS_TCBs */ + 100dbbc: 100eb180 call 100eb18 + + OS_InitEventList(); /* Initialize the free list of OS_EVENTs */ + 100dbc0: 100e8940 call 100e894 + +#if (OS_FLAG_EN > 0) && (OS_MAX_FLAGS > 0) + OS_FlagInit(); /* Initialize the event flag structures */ + 100dbc4: 1010bc80 call 1010bc8 +#endif + +#if (OS_MEM_EN > 0) && (OS_MAX_MEM_PART > 0) + OS_MemInit(); /* Initialize the memory manager */ + 100dbc8: 10115a00 call 10115a0 +#endif + +#if (OS_Q_EN > 0) && (OS_MAX_QS > 0) + OS_QInit(); /* Initialize the message queue structures */ + 100dbcc: 10128f80 call 10128f8 +#endif + + OS_InitTaskIdle(); /* Create the Idle Task */ + 100dbd0: 100ea200 call 100ea20 +#if OS_TASK_STAT_EN > 0 + OS_InitTaskStat(); /* Create the Statistic Task */ + 100dbd4: 100ea9c0 call 100ea9c + +#if OS_TMR_EN > 0 + OSTmr_Init(); /* Initialize the Timer Manager */ +#endif + + OSInitHookEnd(); /* Call port specific init. code */ + 100dbd8: 10184bc0 call 10184bc + +#if OS_DEBUG_EN > 0 + OSDebugInit(); + 100dbdc: 100f3a00 call 100f3a0 +#endif +} + 100dbe0: e037883a mov sp,fp + 100dbe4: dfc00117 ldw ra,4(sp) + 100dbe8: df000017 ldw fp,0(sp) + 100dbec: dec00204 addi sp,sp,8 + 100dbf0: f800283a ret + +0100dbf4 : +* 5) You are allowed to nest interrupts up to 255 levels deep. +********************************************************************************************************* +*/ + +void OSIntEnter (void) +{ + 100dbf4: defffc04 addi sp,sp,-16 + 100dbf8: df000315 stw fp,12(sp) + 100dbfc: df000304 addi fp,sp,12 +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 100dc00: e03fff15 stw zero,-4(fp) +#endif + + if (OSRunning == OS_TRUE) { + 100dc04: d0a78343 ldbu r2,-25075(gp) + 100dc08: 10803fcc andi r2,r2,255 + 100dc0c: 10800058 cmpnei r2,r2,1 + 100dc10: 1000131e bne r2,zero,100dc60 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 100dc14: 0005303a rdctl r2,status + 100dc18: e0bffe15 stw r2,-8(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 100dc1c: e0fffe17 ldw r3,-8(fp) + 100dc20: 00bfff84 movi r2,-2 + 100dc24: 1884703a and r2,r3,r2 + 100dc28: 1001703a wrctl status,r2 + + return context; + 100dc2c: e0bffe17 ldw r2,-8(fp) + OS_ENTER_CRITICAL(); + 100dc30: e0bfff15 stw r2,-4(fp) + if (OSIntNesting < 255u) { + 100dc34: d0a79103 ldbu r2,-25020(gp) + 100dc38: 10803fcc andi r2,r2,255 + 100dc3c: 10803fe0 cmpeqi r2,r2,255 + 100dc40: 1000031e bne r2,zero,100dc50 + OSIntNesting++; /* Increment ISR nesting level */ + 100dc44: d0a79103 ldbu r2,-25020(gp) + 100dc48: 10800044 addi r2,r2,1 + 100dc4c: d0a79105 stb r2,-25020(gp) + 100dc50: e0bfff17 ldw r2,-4(fp) + 100dc54: e0bffd15 stw r2,-12(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 100dc58: e0bffd17 ldw r2,-12(fp) + 100dc5c: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); + } +} + 100dc60: e037883a mov sp,fp + 100dc64: df000017 ldw fp,0(sp) + 100dc68: dec00104 addi sp,sp,4 + 100dc6c: f800283a ret + +0100dc70 : +* 2) Rescheduling is prevented when the scheduler is locked (see OS_SchedLock()) +********************************************************************************************************* +*/ + +void OSIntExit (void) +{ + 100dc70: defffb04 addi sp,sp,-20 + 100dc74: dfc00415 stw ra,16(sp) + 100dc78: df000315 stw fp,12(sp) + 100dc7c: df000304 addi fp,sp,12 +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 100dc80: e03fff15 stw zero,-4(fp) +#endif + + + + if (OSRunning == OS_TRUE) { + 100dc84: d0a78343 ldbu r2,-25075(gp) + 100dc88: 10803fcc andi r2,r2,255 + 100dc8c: 10800058 cmpnei r2,r2,1 + 100dc90: 1000321e bne r2,zero,100dd5c +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 100dc94: 0005303a rdctl r2,status + 100dc98: e0bffe15 stw r2,-8(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 100dc9c: e0fffe17 ldw r3,-8(fp) + 100dca0: 00bfff84 movi r2,-2 + 100dca4: 1884703a and r2,r3,r2 + 100dca8: 1001703a wrctl status,r2 + + return context; + 100dcac: e0bffe17 ldw r2,-8(fp) + OS_ENTER_CRITICAL(); + 100dcb0: e0bfff15 stw r2,-4(fp) + if (OSIntNesting > 0) { /* Prevent OSIntNesting from wrapping */ + 100dcb4: d0a79103 ldbu r2,-25020(gp) + 100dcb8: 10803fcc andi r2,r2,255 + 100dcbc: 1005003a cmpeq r2,r2,zero + 100dcc0: 1000031e bne r2,zero,100dcd0 + OSIntNesting--; + 100dcc4: d0a79103 ldbu r2,-25020(gp) + 100dcc8: 10bfffc4 addi r2,r2,-1 + 100dccc: d0a79105 stb r2,-25020(gp) + } + if (OSIntNesting == 0) { /* Reschedule only if all ISRs complete ... */ + 100dcd0: d0a79103 ldbu r2,-25020(gp) + 100dcd4: 10803fcc andi r2,r2,255 + 100dcd8: 1004c03a cmpne r2,r2,zero + 100dcdc: 10001b1e bne r2,zero,100dd4c + if (OSLockNesting == 0) { /* ... and not locked. */ + 100dce0: d0a78303 ldbu r2,-25076(gp) + 100dce4: 10803fcc andi r2,r2,255 + 100dce8: 1004c03a cmpne r2,r2,zero + 100dcec: 1000171e bne r2,zero,100dd4c + OS_SchedNew(); + 100dcf0: 100ed8c0 call 100ed8c + if (OSPrioHighRdy != OSPrioCur) { /* No Ctx Sw if current task is highest rdy */ + 100dcf4: d0a78503 ldbu r2,-25068(gp) + 100dcf8: d0e78543 ldbu r3,-25067(gp) + 100dcfc: 11003fcc andi r4,r2,255 + 100dd00: 18803fcc andi r2,r3,255 + 100dd04: 20801126 beq r4,r2,100dd4c + OSTCBHighRdy = OSTCBPrioTbl[OSPrioHighRdy]; + 100dd08: d0a78503 ldbu r2,-25068(gp) + 100dd0c: 10803fcc andi r2,r2,255 + 100dd10: 00c040b4 movhi r3,258 + 100dd14: 18d9a904 addi r3,r3,26276 + 100dd18: 1085883a add r2,r2,r2 + 100dd1c: 1085883a add r2,r2,r2 + 100dd20: 10c5883a add r2,r2,r3 + 100dd24: 10800017 ldw r2,0(r2) + 100dd28: d0a78d15 stw r2,-25036(gp) +#if OS_TASK_PROFILE_EN > 0 + OSTCBHighRdy->OSTCBCtxSwCtr++; /* Inc. # of context switches to this task */ + 100dd2c: d0e78d17 ldw r3,-25036(gp) + 100dd30: 18800e17 ldw r2,56(r3) + 100dd34: 10800044 addi r2,r2,1 + 100dd38: 18800e15 stw r2,56(r3) +#endif + OSCtxSwCtr++; /* Keep track of the number of ctx switches */ + 100dd3c: d0a78817 ldw r2,-25056(gp) + 100dd40: 10800044 addi r2,r2,1 + 100dd44: d0a78815 stw r2,-25056(gp) + OSIntCtxSw(); /* Perform interrupt level ctx switch */ + 100dd48: 101802c0 call 101802c + 100dd4c: e0bfff17 ldw r2,-4(fp) + 100dd50: e0bffd15 stw r2,-12(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 100dd54: e0bffd17 ldw r2,-12(fp) + 100dd58: 1001703a wrctl status,r2 + } + } + } + OS_EXIT_CRITICAL(); + } +} + 100dd5c: e037883a mov sp,fp + 100dd60: dfc00117 ldw ra,4(sp) + 100dd64: df000017 ldw fp,0(sp) + 100dd68: dec00204 addi sp,sp,8 + 100dd6c: f800283a ret + +0100dd70 : +********************************************************************************************************* +*/ + +#if OS_SCHED_LOCK_EN > 0 +void OSSchedLock (void) +{ + 100dd70: defffc04 addi sp,sp,-16 + 100dd74: df000315 stw fp,12(sp) + 100dd78: df000304 addi fp,sp,12 +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 100dd7c: e03fff15 stw zero,-4(fp) +#endif + + + + if (OSRunning == OS_TRUE) { /* Make sure multitasking is running */ + 100dd80: d0a78343 ldbu r2,-25075(gp) + 100dd84: 10803fcc andi r2,r2,255 + 100dd88: 10800058 cmpnei r2,r2,1 + 100dd8c: 1000171e bne r2,zero,100ddec +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 100dd90: 0005303a rdctl r2,status + 100dd94: e0bffe15 stw r2,-8(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 100dd98: e0fffe17 ldw r3,-8(fp) + 100dd9c: 00bfff84 movi r2,-2 + 100dda0: 1884703a and r2,r3,r2 + 100dda4: 1001703a wrctl status,r2 + + return context; + 100dda8: e0bffe17 ldw r2,-8(fp) + OS_ENTER_CRITICAL(); + 100ddac: e0bfff15 stw r2,-4(fp) + if (OSIntNesting == 0) { /* Can't call from an ISR */ + 100ddb0: d0a79103 ldbu r2,-25020(gp) + 100ddb4: 10803fcc andi r2,r2,255 + 100ddb8: 1004c03a cmpne r2,r2,zero + 100ddbc: 1000071e bne r2,zero,100dddc + if (OSLockNesting < 255u) { /* Prevent OSLockNesting from wrapping back to 0 */ + 100ddc0: d0a78303 ldbu r2,-25076(gp) + 100ddc4: 10803fcc andi r2,r2,255 + 100ddc8: 10803fe0 cmpeqi r2,r2,255 + 100ddcc: 1000031e bne r2,zero,100dddc + OSLockNesting++; /* Increment lock nesting level */ + 100ddd0: d0a78303 ldbu r2,-25076(gp) + 100ddd4: 10800044 addi r2,r2,1 + 100ddd8: d0a78305 stb r2,-25076(gp) + 100dddc: e0bfff17 ldw r2,-4(fp) + 100dde0: e0bffd15 stw r2,-12(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 100dde4: e0bffd17 ldw r2,-12(fp) + 100dde8: 1001703a wrctl status,r2 + } + } + OS_EXIT_CRITICAL(); + } +} + 100ddec: e037883a mov sp,fp + 100ddf0: df000017 ldw fp,0(sp) + 100ddf4: dec00104 addi sp,sp,4 + 100ddf8: f800283a ret + +0100ddfc : +********************************************************************************************************* +*/ + +#if OS_SCHED_LOCK_EN > 0 +void OSSchedUnlock (void) +{ + 100ddfc: defff804 addi sp,sp,-32 + 100de00: dfc00715 stw ra,28(sp) + 100de04: df000615 stw fp,24(sp) + 100de08: df000604 addi fp,sp,24 +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 100de0c: e03fff15 stw zero,-4(fp) +#endif + + + + if (OSRunning == OS_TRUE) { /* Make sure multitasking is running */ + 100de10: d0a78343 ldbu r2,-25075(gp) + 100de14: 10803fcc andi r2,r2,255 + 100de18: 10800058 cmpnei r2,r2,1 + 100de1c: 10002b1e bne r2,zero,100decc +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 100de20: 0005303a rdctl r2,status + 100de24: e0bffe15 stw r2,-8(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 100de28: e0fffe17 ldw r3,-8(fp) + 100de2c: 00bfff84 movi r2,-2 + 100de30: 1884703a and r2,r3,r2 + 100de34: 1001703a wrctl status,r2 + + return context; + 100de38: e0bffe17 ldw r2,-8(fp) + OS_ENTER_CRITICAL(); + 100de3c: e0bfff15 stw r2,-4(fp) + if (OSLockNesting > 0) { /* Do not decrement if already 0 */ + 100de40: d0a78303 ldbu r2,-25076(gp) + 100de44: 10803fcc andi r2,r2,255 + 100de48: 1005003a cmpeq r2,r2,zero + 100de4c: 10001b1e bne r2,zero,100debc + OSLockNesting--; /* Decrement lock nesting level */ + 100de50: d0a78303 ldbu r2,-25076(gp) + 100de54: 10bfffc4 addi r2,r2,-1 + 100de58: d0a78305 stb r2,-25076(gp) + if (OSLockNesting == 0) { /* See if scheduler is enabled and ... */ + 100de5c: d0a78303 ldbu r2,-25076(gp) + 100de60: 10803fcc andi r2,r2,255 + 100de64: 1004c03a cmpne r2,r2,zero + 100de68: 10000f1e bne r2,zero,100dea8 + if (OSIntNesting == 0) { /* ... not in an ISR */ + 100de6c: d0a79103 ldbu r2,-25020(gp) + 100de70: 10803fcc andi r2,r2,255 + 100de74: 1004c03a cmpne r2,r2,zero + 100de78: 1000061e bne r2,zero,100de94 + 100de7c: e0bfff17 ldw r2,-4(fp) + 100de80: e0bffd15 stw r2,-12(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 100de84: e0bffd17 ldw r2,-12(fp) + 100de88: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + OS_Sched(); /* See if a HPT is ready */ + 100de8c: 100ecb80 call 100ecb8 + 100de90: 00000e06 br 100decc + 100de94: e0bfff17 ldw r2,-4(fp) + 100de98: e0bffc15 stw r2,-16(fp) + 100de9c: e0bffc17 ldw r2,-16(fp) + 100dea0: 1001703a wrctl status,r2 + 100dea4: 00000906 br 100decc + 100dea8: e0bfff17 ldw r2,-4(fp) + 100deac: e0bffb15 stw r2,-20(fp) + 100deb0: e0bffb17 ldw r2,-20(fp) + 100deb4: 1001703a wrctl status,r2 + 100deb8: 00000406 br 100decc + 100debc: e0bfff17 ldw r2,-4(fp) + 100dec0: e0bffa15 stw r2,-24(fp) + 100dec4: e0bffa17 ldw r2,-24(fp) + 100dec8: 1001703a wrctl status,r2 + } + } else { + OS_EXIT_CRITICAL(); + } + } +} + 100decc: e037883a mov sp,fp + 100ded0: dfc00117 ldw ra,4(sp) + 100ded4: df000017 ldw fp,0(sp) + 100ded8: dec00204 addi sp,sp,8 + 100dedc: f800283a ret + +0100dee0 : +* d_ Execute the task. +********************************************************************************************************* +*/ + +void OSStart (void) +{ + 100dee0: defffe04 addi sp,sp,-8 + 100dee4: dfc00115 stw ra,4(sp) + 100dee8: df000015 stw fp,0(sp) + 100deec: d839883a mov fp,sp + if (OSRunning == OS_FALSE) { + 100def0: d0a78343 ldbu r2,-25075(gp) + 100def4: 10803fcc andi r2,r2,255 + 100def8: 1004c03a cmpne r2,r2,zero + 100defc: 10000f1e bne r2,zero,100df3c + OS_SchedNew(); /* Find highest priority's task priority number */ + 100df00: 100ed8c0 call 100ed8c + OSPrioCur = OSPrioHighRdy; + 100df04: d0a78503 ldbu r2,-25068(gp) + 100df08: d0a78545 stb r2,-25067(gp) + OSTCBHighRdy = OSTCBPrioTbl[OSPrioHighRdy]; /* Point to highest priority task ready to run */ + 100df0c: d0a78503 ldbu r2,-25068(gp) + 100df10: 10803fcc andi r2,r2,255 + 100df14: 00c040b4 movhi r3,258 + 100df18: 18d9a904 addi r3,r3,26276 + 100df1c: 1085883a add r2,r2,r2 + 100df20: 1085883a add r2,r2,r2 + 100df24: 10c5883a add r2,r2,r3 + 100df28: 10800017 ldw r2,0(r2) + 100df2c: d0a78d15 stw r2,-25036(gp) + OSTCBCur = OSTCBHighRdy; + 100df30: d0a78d17 ldw r2,-25036(gp) + 100df34: d0a79215 stw r2,-25016(gp) + OSStartHighRdy(); /* Execute target specific code to start task */ + 100df38: 10180b80 call 10180b8 + } +} + 100df3c: e037883a mov sp,fp + 100df40: dfc00117 ldw ra,4(sp) + 100df44: df000017 ldw fp,0(sp) + 100df48: dec00204 addi sp,sp,8 + 100df4c: f800283a ret + +0100df50 : +********************************************************************************************************* +*/ + +#if OS_TASK_STAT_EN > 0 +void OSStatInit (void) +{ + 100df50: defff904 addi sp,sp,-28 + 100df54: dfc00615 stw ra,24(sp) + 100df58: df000515 stw fp,20(sp) + 100df5c: df000504 addi fp,sp,20 +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 100df60: e03fff15 stw zero,-4(fp) +#endif + + + + OSTimeDly(2); /* Synchronize with clock tick */ + 100df64: 01000084 movi r4,2 + 100df68: 1014fac0 call 1014fac +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 100df6c: 0005303a rdctl r2,status + 100df70: e0bffe15 stw r2,-8(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 100df74: e0fffe17 ldw r3,-8(fp) + 100df78: 00bfff84 movi r2,-2 + 100df7c: 1884703a and r2,r3,r2 + 100df80: 1001703a wrctl status,r2 + + return context; + 100df84: e0bffe17 ldw r2,-8(fp) + OS_ENTER_CRITICAL(); + 100df88: e0bfff15 stw r2,-4(fp) + OSIdleCtr = 0L; /* Clear idle counter */ + 100df8c: d0278415 stw zero,-25072(gp) + 100df90: e0bfff17 ldw r2,-4(fp) + 100df94: e0bffd15 stw r2,-12(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 100df98: e0bffd17 ldw r2,-12(fp) + 100df9c: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + OSTimeDly(OS_TICKS_PER_SEC / 10); /* Determine MAX. idle counter value for 1/10 second */ + 100dfa0: 01001904 movi r4,100 + 100dfa4: 1014fac0 call 1014fac +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 100dfa8: 0005303a rdctl r2,status + 100dfac: e0bffc15 stw r2,-16(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 100dfb0: e0fffc17 ldw r3,-16(fp) + 100dfb4: 00bfff84 movi r2,-2 + 100dfb8: 1884703a and r2,r3,r2 + 100dfbc: 1001703a wrctl status,r2 + + return context; + 100dfc0: e0bffc17 ldw r2,-16(fp) + OS_ENTER_CRITICAL(); + 100dfc4: e0bfff15 stw r2,-4(fp) + OSIdleCtrMax = OSIdleCtr; /* Store maximum idle counter count in 1/10 second */ + 100dfc8: d0a78417 ldw r2,-25072(gp) + 100dfcc: d0a78915 stw r2,-25052(gp) + OSStatRdy = OS_TRUE; + 100dfd0: 00800044 movi r2,1 + 100dfd4: d0a79505 stb r2,-25004(gp) + 100dfd8: e0bfff17 ldw r2,-4(fp) + 100dfdc: e0bffb15 stw r2,-20(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 100dfe0: e0bffb17 ldw r2,-20(fp) + 100dfe4: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); +} + 100dfe8: e037883a mov sp,fp + 100dfec: dfc00117 ldw ra,4(sp) + 100dff0: df000017 ldw fp,0(sp) + 100dff4: dec00204 addi sp,sp,8 + 100dff8: f800283a ret + +0100dffc : +* Returns : none +********************************************************************************************************* +*/ + +void OSTimeTick (void) +{ + 100dffc: defff604 addi sp,sp,-40 + 100e000: dfc00915 stw ra,36(sp) + 100e004: df000815 stw fp,32(sp) + 100e008: df000804 addi fp,sp,32 + OS_TCB *ptcb; +#if OS_TICK_STEP_EN > 0 + BOOLEAN step; +#endif +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 100e00c: e03ffc15 stw zero,-16(fp) +#endif + + + +#if OS_TIME_TICK_HOOK_EN > 0 + OSTimeTickHook(); /* Call user definable hook */ + 100e010: 10184840 call 1018484 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 100e014: 0005303a rdctl r2,status + 100e018: e0bffb15 stw r2,-20(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 100e01c: e0fffb17 ldw r3,-20(fp) + 100e020: 00bfff84 movi r2,-2 + 100e024: 1884703a and r2,r3,r2 + 100e028: 1001703a wrctl status,r2 + + return context; + 100e02c: e0bffb17 ldw r2,-20(fp) +#endif +#if OS_TIME_GET_SET_EN > 0 + OS_ENTER_CRITICAL(); /* Update the 32-bit tick counter */ + 100e030: e0bffc15 stw r2,-16(fp) + OSTime++; + 100e034: d0a79317 ldw r2,-25012(gp) + 100e038: 10800044 addi r2,r2,1 + 100e03c: d0a79315 stw r2,-25012(gp) + 100e040: e0bffc17 ldw r2,-16(fp) + 100e044: e0bffa15 stw r2,-24(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 100e048: e0bffa17 ldw r2,-24(fp) + 100e04c: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); +#endif + if (OSRunning == OS_TRUE) { + 100e050: d0a78343 ldbu r2,-25075(gp) + 100e054: 10803fcc andi r2,r2,255 + 100e058: 10800058 cmpnei r2,r2,1 + 100e05c: 1000721e bne r2,zero,100e228 +#if OS_TICK_STEP_EN > 0 + switch (OSTickStepState) { /* Determine whether we need to process a tick */ + 100e060: d0a78703 ldbu r2,-25060(gp) + 100e064: 10803fcc andi r2,r2,255 + 100e068: e0bfff15 stw r2,-4(fp) + 100e06c: e0ffff17 ldw r3,-4(fp) + 100e070: 18800060 cmpeqi r2,r3,1 + 100e074: 10000a1e bne r2,zero,100e0a0 + 100e078: e0ffff17 ldw r3,-4(fp) + 100e07c: 188000a0 cmpeqi r2,r3,2 + 100e080: 1000091e bne r2,zero,100e0a8 + 100e084: e0ffff17 ldw r3,-4(fp) + 100e088: 1805003a cmpeq r2,r3,zero + 100e08c: 1000011e bne r2,zero,100e094 + 100e090: 00000a06 br 100e0bc + case OS_TICK_STEP_DIS: /* Yes, stepping is disabled */ + step = OS_TRUE; + 100e094: 00800044 movi r2,1 + 100e098: e0bffd05 stb r2,-12(fp) + break; + 100e09c: 00000a06 br 100e0c8 + + case OS_TICK_STEP_WAIT: /* No, waiting for uC/OS-View to set ... */ + step = OS_FALSE; /* .. OSTickStepState to OS_TICK_STEP_ONCE */ + 100e0a0: e03ffd05 stb zero,-12(fp) + break; + 100e0a4: 00000806 br 100e0c8 + + case OS_TICK_STEP_ONCE: /* Yes, process tick once and wait for next ... */ + step = OS_TRUE; /* ... step command from uC/OS-View */ + 100e0a8: 00800044 movi r2,1 + 100e0ac: e0bffd05 stb r2,-12(fp) + OSTickStepState = OS_TICK_STEP_WAIT; + 100e0b0: 00800044 movi r2,1 + 100e0b4: d0a78705 stb r2,-25060(gp) + break; + 100e0b8: 00000306 br 100e0c8 + + default: /* Invalid case, correct situation */ + step = OS_TRUE; + 100e0bc: 00800044 movi r2,1 + 100e0c0: e0bffd05 stb r2,-12(fp) + OSTickStepState = OS_TICK_STEP_DIS; + 100e0c4: d0278705 stb zero,-25060(gp) + break; + } + if (step == OS_FALSE) { /* Return if waiting for step command */ + 100e0c8: e0bffd03 ldbu r2,-12(fp) + 100e0cc: 1005003a cmpeq r2,r2,zero + 100e0d0: 1000551e bne r2,zero,100e228 + return; + } +#endif + ptcb = OSTCBList; /* Point at first TCB in TCB list */ + 100e0d4: d0a78617 ldw r2,-25064(gp) + 100e0d8: e0bffe15 stw r2,-8(fp) + while (ptcb->OSTCBPrio != OS_TASK_IDLE_PRIO) { /* Go through all TCBs in TCB list */ + 100e0dc: 00004d06 br 100e214 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 100e0e0: 0005303a rdctl r2,status + 100e0e4: e0bff915 stw r2,-28(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 100e0e8: e0fff917 ldw r3,-28(fp) + 100e0ec: 00bfff84 movi r2,-2 + 100e0f0: 1884703a and r2,r3,r2 + 100e0f4: 1001703a wrctl status,r2 + + return context; + 100e0f8: e0bff917 ldw r2,-28(fp) + OS_ENTER_CRITICAL(); + 100e0fc: e0bffc15 stw r2,-16(fp) + if (ptcb->OSTCBDly != 0) { /* No, Delayed or waiting for event with TO */ + 100e100: e0bffe17 ldw r2,-8(fp) + 100e104: 10800b8b ldhu r2,46(r2) + 100e108: 10bfffcc andi r2,r2,65535 + 100e10c: 1005003a cmpeq r2,r2,zero + 100e110: 1000391e bne r2,zero,100e1f8 + if (--ptcb->OSTCBDly == 0) { /* Decrement nbr of ticks to end of delay */ + 100e114: e0bffe17 ldw r2,-8(fp) + 100e118: 10800b8b ldhu r2,46(r2) + 100e11c: 10bfffc4 addi r2,r2,-1 + 100e120: 1007883a mov r3,r2 + 100e124: e0bffe17 ldw r2,-8(fp) + 100e128: 10c00b8d sth r3,46(r2) + 100e12c: e0bffe17 ldw r2,-8(fp) + 100e130: 10800b8b ldhu r2,46(r2) + 100e134: 10bfffcc andi r2,r2,65535 + 100e138: 1004c03a cmpne r2,r2,zero + 100e13c: 10002e1e bne r2,zero,100e1f8 + /* Check for timeout */ + if ((ptcb->OSTCBStat & OS_STAT_PEND_ANY) != OS_STAT_RDY) { + 100e140: e0bffe17 ldw r2,-8(fp) + 100e144: 10800c03 ldbu r2,48(r2) + 100e148: 10803fcc andi r2,r2,255 + 100e14c: 10800dcc andi r2,r2,55 + 100e150: 1005003a cmpeq r2,r2,zero + 100e154: 10000b1e bne r2,zero,100e184 + ptcb->OSTCBStat &= ~(INT8U)OS_STAT_PEND_ANY; /* Yes, Clear status flag */ + 100e158: e0bffe17 ldw r2,-8(fp) + 100e15c: 10c00c03 ldbu r3,48(r2) + 100e160: 00bff204 movi r2,-56 + 100e164: 1884703a and r2,r3,r2 + 100e168: 1007883a mov r3,r2 + 100e16c: e0bffe17 ldw r2,-8(fp) + 100e170: 10c00c05 stb r3,48(r2) + ptcb->OSTCBStatPend = OS_STAT_PEND_TO; /* Indicate PEND timeout */ + 100e174: e0fffe17 ldw r3,-8(fp) + 100e178: 00800044 movi r2,1 + 100e17c: 18800c45 stb r2,49(r3) + 100e180: 00000206 br 100e18c + } else { + ptcb->OSTCBStatPend = OS_STAT_PEND_OK; + 100e184: e0bffe17 ldw r2,-8(fp) + 100e188: 10000c45 stb zero,49(r2) + } + + if ((ptcb->OSTCBStat & OS_STAT_SUSPEND) == OS_STAT_RDY) { /* Is task suspended? */ + 100e18c: e0bffe17 ldw r2,-8(fp) + 100e190: 10800c03 ldbu r2,48(r2) + 100e194: 10803fcc andi r2,r2,255 + 100e198: 1080020c andi r2,r2,8 + 100e19c: 1004c03a cmpne r2,r2,zero + 100e1a0: 1000151e bne r2,zero,100e1f8 + OSRdyGrp |= ptcb->OSTCBBitY; /* No, Make ready */ + 100e1a4: e0bffe17 ldw r2,-8(fp) + 100e1a8: 10c00d83 ldbu r3,54(r2) + 100e1ac: d0a78f03 ldbu r2,-25028(gp) + 100e1b0: 1884b03a or r2,r3,r2 + 100e1b4: d0a78f05 stb r2,-25028(gp) + OSRdyTbl[ptcb->OSTCBY] |= ptcb->OSTCBBitX; + 100e1b8: e0bffe17 ldw r2,-8(fp) + 100e1bc: 10800d03 ldbu r2,52(r2) + 100e1c0: 11003fcc andi r4,r2,255 + 100e1c4: e0bffe17 ldw r2,-8(fp) + 100e1c8: 10800d03 ldbu r2,52(r2) + 100e1cc: 10c03fcc andi r3,r2,255 + 100e1d0: d0a78f44 addi r2,gp,-25027 + 100e1d4: 1885883a add r2,r3,r2 + 100e1d8: 10c00003 ldbu r3,0(r2) + 100e1dc: e0bffe17 ldw r2,-8(fp) + 100e1e0: 10800d43 ldbu r2,53(r2) + 100e1e4: 1884b03a or r2,r3,r2 + 100e1e8: 1007883a mov r3,r2 + 100e1ec: d0a78f44 addi r2,gp,-25027 + 100e1f0: 2085883a add r2,r4,r2 + 100e1f4: 10c00005 stb r3,0(r2) + } + } + } + ptcb = ptcb->OSTCBNext; /* Point at next TCB in TCB list */ + 100e1f8: e0bffe17 ldw r2,-8(fp) + 100e1fc: 10800517 ldw r2,20(r2) + 100e200: e0bffe15 stw r2,-8(fp) + 100e204: e0bffc17 ldw r2,-16(fp) + 100e208: e0bff815 stw r2,-32(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 100e20c: e0bff817 ldw r2,-32(fp) + 100e210: 1001703a wrctl status,r2 + if (step == OS_FALSE) { /* Return if waiting for step command */ + return; + } +#endif + ptcb = OSTCBList; /* Point at first TCB in TCB list */ + while (ptcb->OSTCBPrio != OS_TASK_IDLE_PRIO) { /* Go through all TCBs in TCB list */ + 100e214: e0bffe17 ldw r2,-8(fp) + 100e218: 10800c83 ldbu r2,50(r2) + 100e21c: 10803fcc andi r2,r2,255 + 100e220: 10800518 cmpnei r2,r2,20 + 100e224: 103fae1e bne r2,zero,100e0e0 + } + ptcb = ptcb->OSTCBNext; /* Point at next TCB in TCB list */ + OS_EXIT_CRITICAL(); + } + } +} + 100e228: e037883a mov sp,fp + 100e22c: dfc00117 ldw ra,4(sp) + 100e230: df000017 ldw fp,0(sp) + 100e234: dec00204 addi sp,sp,8 + 100e238: f800283a ret + +0100e23c : +* Returns : the version number of uC/OS-II multiplied by 100. +********************************************************************************************************* +*/ + +INT16U OSVersion (void) +{ + 100e23c: deffff04 addi sp,sp,-4 + 100e240: df000015 stw fp,0(sp) + 100e244: d839883a mov fp,sp + return (OS_VERSION); + 100e248: 00804784 movi r2,286 +} + 100e24c: e037883a mov sp,fp + 100e250: df000017 ldw fp,0(sp) + 100e254: dec00104 addi sp,sp,4 + 100e258: f800283a ret + +0100e25c : +********************************************************************************************************* +*/ + +#if OS_TASK_DEL_EN > 0 +void OS_Dummy (void) +{ + 100e25c: deffff04 addi sp,sp,-4 + 100e260: df000015 stw fp,0(sp) + 100e264: d839883a mov fp,sp +} + 100e268: e037883a mov sp,fp + 100e26c: df000017 ldw fp,0(sp) + 100e270: dec00104 addi sp,sp,4 + 100e274: f800283a ret + +0100e278 : +* Note : This function is INTERNAL to uC/OS-II and your application should not call it. +********************************************************************************************************* +*/ +#if (OS_EVENT_EN) +INT8U OS_EventTaskRdy (OS_EVENT *pevent, void *pmsg, INT8U msk, INT8U pend_stat) +{ + 100e278: defff804 addi sp,sp,-32 + 100e27c: dfc00715 stw ra,28(sp) + 100e280: df000615 stw fp,24(sp) + 100e284: df000604 addi fp,sp,24 + 100e288: e13ffc15 stw r4,-16(fp) + 100e28c: e17ffd15 stw r5,-12(fp) + 100e290: e1bffe05 stb r6,-8(fp) + 100e294: e1ffff05 stb r7,-4(fp) + INT16U *ptbl; +#endif + + +#if OS_LOWEST_PRIO <= 63 + y = OSUnMapTbl[pevent->OSEventGrp]; /* Find HPT waiting for message */ + 100e298: e0bffc17 ldw r2,-16(fp) + 100e29c: 10800283 ldbu r2,10(r2) + 100e2a0: 10c03fcc andi r3,r2,255 + 100e2a4: 008040b4 movhi r2,258 + 100e2a8: 10a43604 addi r2,r2,-28456 + 100e2ac: 10c5883a add r2,r2,r3 + 100e2b0: 10800003 ldbu r2,0(r2) + 100e2b4: e0bffa85 stb r2,-22(fp) + x = OSUnMapTbl[pevent->OSEventTbl[y]]; + 100e2b8: e0fffa83 ldbu r3,-22(fp) + 100e2bc: e0bffc17 ldw r2,-16(fp) + 100e2c0: 1885883a add r2,r3,r2 + 100e2c4: 10800204 addi r2,r2,8 + 100e2c8: 108000c3 ldbu r2,3(r2) + 100e2cc: 10c03fcc andi r3,r2,255 + 100e2d0: 008040b4 movhi r2,258 + 100e2d4: 10a43604 addi r2,r2,-28456 + 100e2d8: 10c5883a add r2,r2,r3 + 100e2dc: 10800003 ldbu r2,0(r2) + 100e2e0: e0bffa45 stb r2,-23(fp) + prio = (INT8U)((y << 3) + x); /* Find priority of task getting the msg */ + 100e2e4: e0bffa83 ldbu r2,-22(fp) + 100e2e8: 100490fa slli r2,r2,3 + 100e2ec: 1007883a mov r3,r2 + 100e2f0: e0bffa43 ldbu r2,-23(fp) + 100e2f4: 1885883a add r2,r3,r2 + 100e2f8: e0bffa05 stb r2,-24(fp) + x = OSUnMapTbl[(*ptbl >> 8) & 0xFF] + 8; + } + prio = (INT8U)((y << 4) + x); /* Find priority of task getting the msg */ +#endif + + ptcb = OSTCBPrioTbl[prio]; /* Point to this task's OS_TCB */ + 100e2fc: e0bffa03 ldbu r2,-24(fp) + 100e300: 00c040b4 movhi r3,258 + 100e304: 18d9a904 addi r3,r3,26276 + 100e308: 1085883a add r2,r2,r2 + 100e30c: 1085883a add r2,r2,r2 + 100e310: 10c5883a add r2,r2,r3 + 100e314: 10800017 ldw r2,0(r2) + 100e318: e0bffb15 stw r2,-20(fp) + ptcb->OSTCBDly = 0; /* Prevent OSTimeTick() from readying task */ + 100e31c: e0bffb17 ldw r2,-20(fp) + 100e320: 10000b8d sth zero,46(r2) +#if ((OS_Q_EN > 0) && (OS_MAX_QS > 0)) || (OS_MBOX_EN > 0) + ptcb->OSTCBMsg = pmsg; /* Send message directly to waiting task */ + 100e324: e0fffb17 ldw r3,-20(fp) + 100e328: e0bffd17 ldw r2,-12(fp) + 100e32c: 18800915 stw r2,36(r3) +#else + pmsg = pmsg; /* Prevent compiler warning if not used */ +#endif + ptcb->OSTCBStat &= ~msk; /* Clear bit associated with event type */ + 100e330: e0bffb17 ldw r2,-20(fp) + 100e334: 10800c03 ldbu r2,48(r2) + 100e338: 1007883a mov r3,r2 + 100e33c: e0bffe03 ldbu r2,-8(fp) + 100e340: 0084303a nor r2,zero,r2 + 100e344: 1884703a and r2,r3,r2 + 100e348: 1007883a mov r3,r2 + 100e34c: e0bffb17 ldw r2,-20(fp) + 100e350: 10c00c05 stb r3,48(r2) + ptcb->OSTCBStatPend = pend_stat; /* Set pend status of post or abort */ + 100e354: e0fffb17 ldw r3,-20(fp) + 100e358: e0bfff03 ldbu r2,-4(fp) + 100e35c: 18800c45 stb r2,49(r3) + /* See if task is ready (could be susp'd) */ + if ((ptcb->OSTCBStat & OS_STAT_SUSPEND) == OS_STAT_RDY) { + 100e360: e0bffb17 ldw r2,-20(fp) + 100e364: 10800c03 ldbu r2,48(r2) + 100e368: 10803fcc andi r2,r2,255 + 100e36c: 1080020c andi r2,r2,8 + 100e370: 1004c03a cmpne r2,r2,zero + 100e374: 1000111e bne r2,zero,100e3bc + OSRdyGrp |= ptcb->OSTCBBitY; /* Put task in the ready to run list */ + 100e378: e0bffb17 ldw r2,-20(fp) + 100e37c: 10c00d83 ldbu r3,54(r2) + 100e380: d0a78f03 ldbu r2,-25028(gp) + 100e384: 1884b03a or r2,r3,r2 + 100e388: d0a78f05 stb r2,-25028(gp) + OSRdyTbl[y] |= ptcb->OSTCBBitX; + 100e38c: e13ffa83 ldbu r4,-22(fp) + 100e390: e0fffa83 ldbu r3,-22(fp) + 100e394: d0a78f44 addi r2,gp,-25027 + 100e398: 1885883a add r2,r3,r2 + 100e39c: 10c00003 ldbu r3,0(r2) + 100e3a0: e0bffb17 ldw r2,-20(fp) + 100e3a4: 10800d43 ldbu r2,53(r2) + 100e3a8: 1884b03a or r2,r3,r2 + 100e3ac: 1007883a mov r3,r2 + 100e3b0: d0a78f44 addi r2,gp,-25027 + 100e3b4: 2085883a add r2,r4,r2 + 100e3b8: 10c00005 stb r3,0(r2) + } + + OS_EventTaskRemove(ptcb, pevent); /* Remove this task from event wait list */ + 100e3bc: e13ffb17 ldw r4,-20(fp) + 100e3c0: e17ffc17 ldw r5,-16(fp) + 100e3c4: 100e6700 call 100e670 +#if (OS_EVENT_MULTI_EN > 0) + if (ptcb->OSTCBEventMultiPtr != (OS_EVENT **)0) { /* Remove this task from events' wait lists */ + 100e3c8: e0bffb17 ldw r2,-20(fp) + 100e3cc: 10800817 ldw r2,32(r2) + 100e3d0: 1005003a cmpeq r2,r2,zero + 100e3d4: 1000071e bne r2,zero,100e3f4 + OS_EventTaskRemoveMulti(ptcb, ptcb->OSTCBEventMultiPtr); + 100e3d8: e0bffb17 ldw r2,-20(fp) + 100e3dc: 11400817 ldw r5,32(r2) + 100e3e0: e13ffb17 ldw r4,-20(fp) + 100e3e4: 100e7280 call 100e728 + ptcb->OSTCBEventPtr = (OS_EVENT *)pevent;/* Return event as first multi-pend event ready*/ + 100e3e8: e0fffb17 ldw r3,-20(fp) + 100e3ec: e0bffc17 ldw r2,-16(fp) + 100e3f0: 18800715 stw r2,28(r3) + } +#endif + + return (prio); + 100e3f4: e0bffa03 ldbu r2,-24(fp) +} + 100e3f8: e037883a mov sp,fp + 100e3fc: dfc00117 ldw ra,4(sp) + 100e400: df000017 ldw fp,0(sp) + 100e404: dec00204 addi sp,sp,8 + 100e408: f800283a ret + +0100e40c : +* Note : This function is INTERNAL to uC/OS-II and your application should not call it. +********************************************************************************************************* +*/ +#if (OS_EVENT_EN) +void OS_EventTaskWait (OS_EVENT *pevent) +{ + 100e40c: defffd04 addi sp,sp,-12 + 100e410: df000215 stw fp,8(sp) + 100e414: df000204 addi fp,sp,8 + 100e418: e13fff15 stw r4,-4(fp) + INT8U y; + + + OSTCBCur->OSTCBEventPtr = pevent; /* Store ptr to ECB in TCB */ + 100e41c: d0e79217 ldw r3,-25016(gp) + 100e420: e0bfff17 ldw r2,-4(fp) + 100e424: 18800715 stw r2,28(r3) + + pevent->OSEventTbl[OSTCBCur->OSTCBY] |= OSTCBCur->OSTCBBitX; /* Put task in waiting list */ + 100e428: d0a79217 ldw r2,-25016(gp) + 100e42c: 10800d03 ldbu r2,52(r2) + 100e430: 11003fcc andi r4,r2,255 + 100e434: d0a79217 ldw r2,-25016(gp) + 100e438: 10800d03 ldbu r2,52(r2) + 100e43c: 10c03fcc andi r3,r2,255 + 100e440: e0bfff17 ldw r2,-4(fp) + 100e444: 1885883a add r2,r3,r2 + 100e448: 10800204 addi r2,r2,8 + 100e44c: 10c000c3 ldbu r3,3(r2) + 100e450: d0a79217 ldw r2,-25016(gp) + 100e454: 10800d43 ldbu r2,53(r2) + 100e458: 1884b03a or r2,r3,r2 + 100e45c: 1007883a mov r3,r2 + 100e460: e0bfff17 ldw r2,-4(fp) + 100e464: 2085883a add r2,r4,r2 + 100e468: 10800204 addi r2,r2,8 + 100e46c: 10c000c5 stb r3,3(r2) + pevent->OSEventGrp |= OSTCBCur->OSTCBBitY; + 100e470: e0bfff17 ldw r2,-4(fp) + 100e474: 10c00283 ldbu r3,10(r2) + 100e478: d0a79217 ldw r2,-25016(gp) + 100e47c: 10800d83 ldbu r2,54(r2) + 100e480: 1884b03a or r2,r3,r2 + 100e484: 1007883a mov r3,r2 + 100e488: e0bfff17 ldw r2,-4(fp) + 100e48c: 10c00285 stb r3,10(r2) + + y = OSTCBCur->OSTCBY; /* Task no longer ready */ + 100e490: d0a79217 ldw r2,-25016(gp) + 100e494: 10800d03 ldbu r2,52(r2) + 100e498: e0bffe05 stb r2,-8(fp) + OSRdyTbl[y] &= ~OSTCBCur->OSTCBBitX; + 100e49c: e13ffe03 ldbu r4,-8(fp) + 100e4a0: e0fffe03 ldbu r3,-8(fp) + 100e4a4: d0a78f44 addi r2,gp,-25027 + 100e4a8: 1885883a add r2,r3,r2 + 100e4ac: 10800003 ldbu r2,0(r2) + 100e4b0: 1007883a mov r3,r2 + 100e4b4: d0a79217 ldw r2,-25016(gp) + 100e4b8: 10800d43 ldbu r2,53(r2) + 100e4bc: 0084303a nor r2,zero,r2 + 100e4c0: 1884703a and r2,r3,r2 + 100e4c4: 1007883a mov r3,r2 + 100e4c8: d0a78f44 addi r2,gp,-25027 + 100e4cc: 2085883a add r2,r4,r2 + 100e4d0: 10c00005 stb r3,0(r2) + if (OSRdyTbl[y] == 0) { + 100e4d4: e0fffe03 ldbu r3,-8(fp) + 100e4d8: d0a78f44 addi r2,gp,-25027 + 100e4dc: 1885883a add r2,r3,r2 + 100e4e0: 10800003 ldbu r2,0(r2) + 100e4e4: 10803fcc andi r2,r2,255 + 100e4e8: 1004c03a cmpne r2,r2,zero + 100e4ec: 1000071e bne r2,zero,100e50c + OSRdyGrp &= ~OSTCBCur->OSTCBBitY; /* Clear event grp bit if this was only task pending */ + 100e4f0: d0a79217 ldw r2,-25016(gp) + 100e4f4: 10800d83 ldbu r2,54(r2) + 100e4f8: 0084303a nor r2,zero,r2 + 100e4fc: 1007883a mov r3,r2 + 100e500: d0a78f03 ldbu r2,-25028(gp) + 100e504: 1884703a and r2,r3,r2 + 100e508: d0a78f05 stb r2,-25028(gp) + } +} + 100e50c: e037883a mov sp,fp + 100e510: df000017 ldw fp,0(sp) + 100e514: dec00104 addi sp,sp,4 + 100e518: f800283a ret + +0100e51c : +* Note : This function is INTERNAL to uC/OS-II and your application should not call it. +********************************************************************************************************* +*/ +#if ((OS_EVENT_EN) && (OS_EVENT_MULTI_EN > 0)) +void OS_EventTaskWaitMulti (OS_EVENT **pevents_wait) +{ + 100e51c: defffb04 addi sp,sp,-20 + 100e520: df000415 stw fp,16(sp) + 100e524: df000404 addi fp,sp,16 + 100e528: e13fff15 stw r4,-4(fp) + OS_EVENT **pevents; + OS_EVENT *pevent; + INT8U y; + + + OSTCBCur->OSTCBEventPtr = (OS_EVENT *)0; + 100e52c: d0a79217 ldw r2,-25016(gp) + 100e530: 10000715 stw zero,28(r2) + OSTCBCur->OSTCBEventMultiPtr = (OS_EVENT **)pevents_wait; /* Store ptr to ECBs in TCB */ + 100e534: d0e79217 ldw r3,-25016(gp) + 100e538: e0bfff17 ldw r2,-4(fp) + 100e53c: 18800815 stw r2,32(r3) + + pevents = pevents_wait; + 100e540: e0bfff17 ldw r2,-4(fp) + 100e544: e0bffe15 stw r2,-8(fp) + pevent = *pevents; + 100e548: e0bffe17 ldw r2,-8(fp) + 100e54c: 10800017 ldw r2,0(r2) + 100e550: e0bffd15 stw r2,-12(fp) + while (pevent != (OS_EVENT *)0) { /* Put task in waiting lists */ + 100e554: 00002006 br 100e5d8 + pevent->OSEventTbl[OSTCBCur->OSTCBY] |= OSTCBCur->OSTCBBitX; + 100e558: d0a79217 ldw r2,-25016(gp) + 100e55c: 10800d03 ldbu r2,52(r2) + 100e560: 11003fcc andi r4,r2,255 + 100e564: d0a79217 ldw r2,-25016(gp) + 100e568: 10800d03 ldbu r2,52(r2) + 100e56c: 10c03fcc andi r3,r2,255 + 100e570: e0bffd17 ldw r2,-12(fp) + 100e574: 1885883a add r2,r3,r2 + 100e578: 10800204 addi r2,r2,8 + 100e57c: 10c000c3 ldbu r3,3(r2) + 100e580: d0a79217 ldw r2,-25016(gp) + 100e584: 10800d43 ldbu r2,53(r2) + 100e588: 1884b03a or r2,r3,r2 + 100e58c: 1007883a mov r3,r2 + 100e590: e0bffd17 ldw r2,-12(fp) + 100e594: 2085883a add r2,r4,r2 + 100e598: 10800204 addi r2,r2,8 + 100e59c: 10c000c5 stb r3,3(r2) + pevent->OSEventGrp |= OSTCBCur->OSTCBBitY; + 100e5a0: e0bffd17 ldw r2,-12(fp) + 100e5a4: 10c00283 ldbu r3,10(r2) + 100e5a8: d0a79217 ldw r2,-25016(gp) + 100e5ac: 10800d83 ldbu r2,54(r2) + 100e5b0: 1884b03a or r2,r3,r2 + 100e5b4: 1007883a mov r3,r2 + 100e5b8: e0bffd17 ldw r2,-12(fp) + 100e5bc: 10c00285 stb r3,10(r2) + pevents++; + 100e5c0: e0bffe17 ldw r2,-8(fp) + 100e5c4: 10800104 addi r2,r2,4 + 100e5c8: e0bffe15 stw r2,-8(fp) + pevent = *pevents; + 100e5cc: e0bffe17 ldw r2,-8(fp) + 100e5d0: 10800017 ldw r2,0(r2) + 100e5d4: e0bffd15 stw r2,-12(fp) + OSTCBCur->OSTCBEventPtr = (OS_EVENT *)0; + OSTCBCur->OSTCBEventMultiPtr = (OS_EVENT **)pevents_wait; /* Store ptr to ECBs in TCB */ + + pevents = pevents_wait; + pevent = *pevents; + while (pevent != (OS_EVENT *)0) { /* Put task in waiting lists */ + 100e5d8: e0bffd17 ldw r2,-12(fp) + 100e5dc: 1004c03a cmpne r2,r2,zero + 100e5e0: 103fdd1e bne r2,zero,100e558 + pevent->OSEventGrp |= OSTCBCur->OSTCBBitY; + pevents++; + pevent = *pevents; + } + + y = OSTCBCur->OSTCBY; /* Task no longer ready */ + 100e5e4: d0a79217 ldw r2,-25016(gp) + 100e5e8: 10800d03 ldbu r2,52(r2) + 100e5ec: e0bffc05 stb r2,-16(fp) + OSRdyTbl[y] &= ~OSTCBCur->OSTCBBitX; + 100e5f0: e13ffc03 ldbu r4,-16(fp) + 100e5f4: e0fffc03 ldbu r3,-16(fp) + 100e5f8: d0a78f44 addi r2,gp,-25027 + 100e5fc: 1885883a add r2,r3,r2 + 100e600: 10800003 ldbu r2,0(r2) + 100e604: 1007883a mov r3,r2 + 100e608: d0a79217 ldw r2,-25016(gp) + 100e60c: 10800d43 ldbu r2,53(r2) + 100e610: 0084303a nor r2,zero,r2 + 100e614: 1884703a and r2,r3,r2 + 100e618: 1007883a mov r3,r2 + 100e61c: d0a78f44 addi r2,gp,-25027 + 100e620: 2085883a add r2,r4,r2 + 100e624: 10c00005 stb r3,0(r2) + if (OSRdyTbl[y] == 0) { + 100e628: e0fffc03 ldbu r3,-16(fp) + 100e62c: d0a78f44 addi r2,gp,-25027 + 100e630: 1885883a add r2,r3,r2 + 100e634: 10800003 ldbu r2,0(r2) + 100e638: 10803fcc andi r2,r2,255 + 100e63c: 1004c03a cmpne r2,r2,zero + 100e640: 1000071e bne r2,zero,100e660 + OSRdyGrp &= ~OSTCBCur->OSTCBBitY; /* Clear event grp bit if this was only task pending */ + 100e644: d0a79217 ldw r2,-25016(gp) + 100e648: 10800d83 ldbu r2,54(r2) + 100e64c: 0084303a nor r2,zero,r2 + 100e650: 1007883a mov r3,r2 + 100e654: d0a78f03 ldbu r2,-25028(gp) + 100e658: 1884703a and r2,r3,r2 + 100e65c: d0a78f05 stb r2,-25028(gp) + } +} + 100e660: e037883a mov sp,fp + 100e664: df000017 ldw fp,0(sp) + 100e668: dec00104 addi sp,sp,4 + 100e66c: f800283a ret + +0100e670 : +********************************************************************************************************* +*/ +#if (OS_EVENT_EN) +void OS_EventTaskRemove (OS_TCB *ptcb, + OS_EVENT *pevent) +{ + 100e670: defffc04 addi sp,sp,-16 + 100e674: df000315 stw fp,12(sp) + 100e678: df000304 addi fp,sp,12 + 100e67c: e13ffe15 stw r4,-8(fp) + 100e680: e17fff15 stw r5,-4(fp) + INT8U y; + + + y = ptcb->OSTCBY; + 100e684: e0bffe17 ldw r2,-8(fp) + 100e688: 10800d03 ldbu r2,52(r2) + 100e68c: e0bffd05 stb r2,-12(fp) + pevent->OSEventTbl[y] &= ~ptcb->OSTCBBitX; /* Remove task from wait list */ + 100e690: e13ffd03 ldbu r4,-12(fp) + 100e694: e0fffd03 ldbu r3,-12(fp) + 100e698: e0bfff17 ldw r2,-4(fp) + 100e69c: 1885883a add r2,r3,r2 + 100e6a0: 10800204 addi r2,r2,8 + 100e6a4: 108000c3 ldbu r2,3(r2) + 100e6a8: 1007883a mov r3,r2 + 100e6ac: e0bffe17 ldw r2,-8(fp) + 100e6b0: 10800d43 ldbu r2,53(r2) + 100e6b4: 0084303a nor r2,zero,r2 + 100e6b8: 1884703a and r2,r3,r2 + 100e6bc: 1007883a mov r3,r2 + 100e6c0: e0bfff17 ldw r2,-4(fp) + 100e6c4: 2085883a add r2,r4,r2 + 100e6c8: 10800204 addi r2,r2,8 + 100e6cc: 10c000c5 stb r3,3(r2) + if (pevent->OSEventTbl[y] == 0) { + 100e6d0: e0fffd03 ldbu r3,-12(fp) + 100e6d4: e0bfff17 ldw r2,-4(fp) + 100e6d8: 1885883a add r2,r3,r2 + 100e6dc: 10800204 addi r2,r2,8 + 100e6e0: 108000c3 ldbu r2,3(r2) + 100e6e4: 10803fcc andi r2,r2,255 + 100e6e8: 1004c03a cmpne r2,r2,zero + 100e6ec: 10000a1e bne r2,zero,100e718 + pevent->OSEventGrp &= ~ptcb->OSTCBBitY; + 100e6f0: e0bfff17 ldw r2,-4(fp) + 100e6f4: 10800283 ldbu r2,10(r2) + 100e6f8: 1007883a mov r3,r2 + 100e6fc: e0bffe17 ldw r2,-8(fp) + 100e700: 10800d83 ldbu r2,54(r2) + 100e704: 0084303a nor r2,zero,r2 + 100e708: 1884703a and r2,r3,r2 + 100e70c: 1007883a mov r3,r2 + 100e710: e0bfff17 ldw r2,-4(fp) + 100e714: 10c00285 stb r3,10(r2) + } +} + 100e718: e037883a mov sp,fp + 100e71c: df000017 ldw fp,0(sp) + 100e720: dec00104 addi sp,sp,4 + 100e724: f800283a ret + +0100e728 : +********************************************************************************************************* +*/ +#if ((OS_EVENT_EN) && (OS_EVENT_MULTI_EN > 0)) +void OS_EventTaskRemoveMulti (OS_TCB *ptcb, + OS_EVENT **pevents_multi) +{ + 100e728: defffa04 addi sp,sp,-24 + 100e72c: df000515 stw fp,20(sp) + 100e730: df000504 addi fp,sp,20 + 100e734: e13ffe15 stw r4,-8(fp) + 100e738: e17fff15 stw r5,-4(fp) + INT16U bity; + INT16U bitx; +#endif + + + y = ptcb->OSTCBY; + 100e73c: e0bffe17 ldw r2,-8(fp) + 100e740: 10800d03 ldbu r2,52(r2) + 100e744: e0bffb85 stb r2,-18(fp) + bity = ptcb->OSTCBBitY; + 100e748: e0bffe17 ldw r2,-8(fp) + 100e74c: 10800d83 ldbu r2,54(r2) + 100e750: e0bffb45 stb r2,-19(fp) + bitx = ptcb->OSTCBBitX; + 100e754: e0bffe17 ldw r2,-8(fp) + 100e758: 10800d43 ldbu r2,53(r2) + 100e75c: e0bffb05 stb r2,-20(fp) + pevents = pevents_multi; + 100e760: e0bfff17 ldw r2,-4(fp) + 100e764: e0bffd15 stw r2,-12(fp) + pevent = *pevents; + 100e768: e0bffd17 ldw r2,-12(fp) + 100e76c: 10800017 ldw r2,0(r2) + 100e770: e0bffc15 stw r2,-16(fp) + while (pevent != (OS_EVENT *)0) { /* Remove task from all events' wait lists */ + 100e774: 00002606 br 100e810 + pevent->OSEventTbl[y] &= ~bitx; + 100e778: e13ffb83 ldbu r4,-18(fp) + 100e77c: e0fffb83 ldbu r3,-18(fp) + 100e780: e0bffc17 ldw r2,-16(fp) + 100e784: 1885883a add r2,r3,r2 + 100e788: 10800204 addi r2,r2,8 + 100e78c: 108000c3 ldbu r2,3(r2) + 100e790: 1007883a mov r3,r2 + 100e794: e0bffb03 ldbu r2,-20(fp) + 100e798: 0084303a nor r2,zero,r2 + 100e79c: 1884703a and r2,r3,r2 + 100e7a0: 1007883a mov r3,r2 + 100e7a4: e0bffc17 ldw r2,-16(fp) + 100e7a8: 2085883a add r2,r4,r2 + 100e7ac: 10800204 addi r2,r2,8 + 100e7b0: 10c000c5 stb r3,3(r2) + if (pevent->OSEventTbl[y] == 0) { + 100e7b4: e0fffb83 ldbu r3,-18(fp) + 100e7b8: e0bffc17 ldw r2,-16(fp) + 100e7bc: 1885883a add r2,r3,r2 + 100e7c0: 10800204 addi r2,r2,8 + 100e7c4: 108000c3 ldbu r2,3(r2) + 100e7c8: 10803fcc andi r2,r2,255 + 100e7cc: 1004c03a cmpne r2,r2,zero + 100e7d0: 1000091e bne r2,zero,100e7f8 + pevent->OSEventGrp &= ~bity; + 100e7d4: e0bffc17 ldw r2,-16(fp) + 100e7d8: 10800283 ldbu r2,10(r2) + 100e7dc: 1007883a mov r3,r2 + 100e7e0: e0bffb43 ldbu r2,-19(fp) + 100e7e4: 0084303a nor r2,zero,r2 + 100e7e8: 1884703a and r2,r3,r2 + 100e7ec: 1007883a mov r3,r2 + 100e7f0: e0bffc17 ldw r2,-16(fp) + 100e7f4: 10c00285 stb r3,10(r2) + } + pevents++; + 100e7f8: e0bffd17 ldw r2,-12(fp) + 100e7fc: 10800104 addi r2,r2,4 + 100e800: e0bffd15 stw r2,-12(fp) + pevent = *pevents; + 100e804: e0bffd17 ldw r2,-12(fp) + 100e808: 10800017 ldw r2,0(r2) + 100e80c: e0bffc15 stw r2,-16(fp) + y = ptcb->OSTCBY; + bity = ptcb->OSTCBBitY; + bitx = ptcb->OSTCBBitX; + pevents = pevents_multi; + pevent = *pevents; + while (pevent != (OS_EVENT *)0) { /* Remove task from all events' wait lists */ + 100e810: e0bffc17 ldw r2,-16(fp) + 100e814: 1004c03a cmpne r2,r2,zero + 100e818: 103fd71e bne r2,zero,100e778 + pevent->OSEventGrp &= ~bity; + } + pevents++; + pevent = *pevents; + } +} + 100e81c: e037883a mov sp,fp + 100e820: df000017 ldw fp,0(sp) + 100e824: dec00104 addi sp,sp,4 + 100e828: f800283a ret + +0100e82c : +* Note : This function is INTERNAL to uC/OS-II and your application should not call it. +********************************************************************************************************* +*/ +#if (OS_EVENT_EN) +void OS_EventWaitListInit (OS_EVENT *pevent) +{ + 100e82c: defffc04 addi sp,sp,-16 + 100e830: df000315 stw fp,12(sp) + 100e834: df000304 addi fp,sp,12 + 100e838: e13fff15 stw r4,-4(fp) + INT16U *ptbl; +#endif + INT8U i; + + + pevent->OSEventGrp = 0; /* No task waiting on event */ + 100e83c: e0bfff17 ldw r2,-4(fp) + 100e840: 10000285 stb zero,10(r2) + ptbl = &pevent->OSEventTbl[0]; + 100e844: e0bfff17 ldw r2,-4(fp) + 100e848: 108002c4 addi r2,r2,11 + 100e84c: e0bffe15 stw r2,-8(fp) + + for (i = 0; i < OS_EVENT_TBL_SIZE; i++) { + 100e850: e03ffd05 stb zero,-12(fp) + 100e854: 00000806 br 100e878 + *ptbl++ = 0; + 100e858: e0bffe17 ldw r2,-8(fp) + 100e85c: 10000005 stb zero,0(r2) + 100e860: e0bffe17 ldw r2,-8(fp) + 100e864: 10800044 addi r2,r2,1 + 100e868: e0bffe15 stw r2,-8(fp) + + + pevent->OSEventGrp = 0; /* No task waiting on event */ + ptbl = &pevent->OSEventTbl[0]; + + for (i = 0; i < OS_EVENT_TBL_SIZE; i++) { + 100e86c: e0bffd03 ldbu r2,-12(fp) + 100e870: 10800044 addi r2,r2,1 + 100e874: e0bffd05 stb r2,-12(fp) + 100e878: e0bffd03 ldbu r2,-12(fp) + 100e87c: 108000f0 cmpltui r2,r2,3 + 100e880: 103ff51e bne r2,zero,100e858 + *ptbl++ = 0; + } +} + 100e884: e037883a mov sp,fp + 100e888: df000017 ldw fp,0(sp) + 100e88c: dec00104 addi sp,sp,4 + 100e890: f800283a ret + +0100e894 : +* Returns : none +********************************************************************************************************* +*/ + +static void OS_InitEventList (void) +{ + 100e894: defffb04 addi sp,sp,-20 + 100e898: dfc00415 stw ra,16(sp) + 100e89c: df000315 stw fp,12(sp) + 100e8a0: df000304 addi fp,sp,12 + INT16U i; + OS_EVENT *pevent1; + OS_EVENT *pevent2; + + + OS_MemClr((INT8U *)&OSEventTbl[0], sizeof(OSEventTbl)); /* Clear the event table */ + 100e8a4: 010040b4 movhi r4,258 + 100e8a8: 21159504 addi r4,r4,22100 + 100e8ac: 0142d004 movi r5,2880 + 100e8b0: 100ebf80 call 100ebf8 + pevent1 = &OSEventTbl[0]; + 100e8b4: 008040b4 movhi r2,258 + 100e8b8: 10959504 addi r2,r2,22100 + 100e8bc: e0bffe15 stw r2,-8(fp) + pevent2 = &OSEventTbl[1]; + 100e8c0: 008040b4 movhi r2,258 + 100e8c4: 1095a104 addi r2,r2,22148 + 100e8c8: e0bffd15 stw r2,-12(fp) + for (i = 0; i < (OS_MAX_EVENTS - 1); i++) { /* Init. list of free EVENT control blocks */ + 100e8cc: e03fff0d sth zero,-4(fp) + 100e8d0: 00001306 br 100e920 + pevent1->OSEventType = OS_EVENT_TYPE_UNUSED; + 100e8d4: e0bffe17 ldw r2,-8(fp) + 100e8d8: 10000005 stb zero,0(r2) + pevent1->OSEventPtr = pevent2; + 100e8dc: e0fffe17 ldw r3,-8(fp) + 100e8e0: e0bffd17 ldw r2,-12(fp) + 100e8e4: 18800115 stw r2,4(r3) +#if OS_EVENT_NAME_SIZE > 1 + pevent1->OSEventName[0] = '?'; /* Unknown name */ + 100e8e8: e0fffe17 ldw r3,-8(fp) + 100e8ec: 00800fc4 movi r2,63 + 100e8f0: 18800385 stb r2,14(r3) + pevent1->OSEventName[1] = OS_ASCII_NUL; + 100e8f4: e0bffe17 ldw r2,-8(fp) + 100e8f8: 100003c5 stb zero,15(r2) +#endif + pevent1++; + 100e8fc: e0bffe17 ldw r2,-8(fp) + 100e900: 10800c04 addi r2,r2,48 + 100e904: e0bffe15 stw r2,-8(fp) + pevent2++; + 100e908: e0bffd17 ldw r2,-12(fp) + 100e90c: 10800c04 addi r2,r2,48 + 100e910: e0bffd15 stw r2,-12(fp) + + + OS_MemClr((INT8U *)&OSEventTbl[0], sizeof(OSEventTbl)); /* Clear the event table */ + pevent1 = &OSEventTbl[0]; + pevent2 = &OSEventTbl[1]; + for (i = 0; i < (OS_MAX_EVENTS - 1); i++) { /* Init. list of free EVENT control blocks */ + 100e914: e0bfff0b ldhu r2,-4(fp) + 100e918: 10800044 addi r2,r2,1 + 100e91c: e0bfff0d sth r2,-4(fp) + 100e920: e0bfff0b ldhu r2,-4(fp) + 100e924: 10800ef0 cmpltui r2,r2,59 + 100e928: 103fea1e bne r2,zero,100e8d4 + pevent1->OSEventName[1] = OS_ASCII_NUL; +#endif + pevent1++; + pevent2++; + } + pevent1->OSEventType = OS_EVENT_TYPE_UNUSED; + 100e92c: e0bffe17 ldw r2,-8(fp) + 100e930: 10000005 stb zero,0(r2) + pevent1->OSEventPtr = (OS_EVENT *)0; + 100e934: e0bffe17 ldw r2,-8(fp) + 100e938: 10000115 stw zero,4(r2) +#if OS_EVENT_NAME_SIZE > 1 + pevent1->OSEventName[0] = '?'; + 100e93c: e0fffe17 ldw r3,-8(fp) + 100e940: 00800fc4 movi r2,63 + 100e944: 18800385 stb r2,14(r3) + pevent1->OSEventName[1] = OS_ASCII_NUL; + 100e948: e0bffe17 ldw r2,-8(fp) + 100e94c: 100003c5 stb zero,15(r2) +#endif + OSEventFreeList = &OSEventTbl[0]; + 100e950: 008040b4 movhi r2,258 + 100e954: 10959504 addi r2,r2,22100 + 100e958: d0a79015 stw r2,-25024(gp) + OSEventFreeList->OSEventName[0] = '?'; /* Unknown name */ + OSEventFreeList->OSEventName[1] = OS_ASCII_NUL; +#endif +#endif +#endif +} + 100e95c: e037883a mov sp,fp + 100e960: dfc00117 ldw ra,4(sp) + 100e964: df000017 ldw fp,0(sp) + 100e968: dec00204 addi sp,sp,8 + 100e96c: f800283a ret + +0100e970 : +* Returns : none +********************************************************************************************************* +*/ + +static void OS_InitMisc (void) +{ + 100e970: deffff04 addi sp,sp,-4 + 100e974: df000015 stw fp,0(sp) + 100e978: d839883a mov fp,sp +#if OS_TIME_GET_SET_EN > 0 + OSTime = 0L; /* Clear the 32-bit system clock */ + 100e97c: d0279315 stw zero,-25012(gp) +#endif + + OSIntNesting = 0; /* Clear the interrupt nesting counter */ + 100e980: d0279105 stb zero,-25020(gp) + OSLockNesting = 0; /* Clear the scheduling lock counter */ + 100e984: d0278305 stb zero,-25076(gp) + + OSTaskCtr = 0; /* Clear the number of tasks */ + 100e988: d0278b45 stb zero,-25043(gp) + + OSRunning = OS_FALSE; /* Indicate that multitasking not started */ + 100e98c: d0278345 stb zero,-25075(gp) + + OSCtxSwCtr = 0; /* Clear the context switch counter */ + 100e990: d0278815 stw zero,-25056(gp) + OSIdleCtr = 0L; /* Clear the 32-bit idle counter */ + 100e994: d0278415 stw zero,-25072(gp) + +#if OS_TASK_STAT_EN > 0 + OSIdleCtrRun = 0L; + 100e998: d0279615 stw zero,-25000(gp) + OSIdleCtrMax = 0L; + 100e99c: d0278915 stw zero,-25052(gp) + OSStatRdy = OS_FALSE; /* Statistic task is not ready */ + 100e9a0: d0279505 stb zero,-25004(gp) +#endif +} + 100e9a4: e037883a mov sp,fp + 100e9a8: df000017 ldw fp,0(sp) + 100e9ac: dec00104 addi sp,sp,4 + 100e9b0: f800283a ret + +0100e9b4 : +* Returns : none +********************************************************************************************************* +*/ + +static void OS_InitRdyList (void) +{ + 100e9b4: defffd04 addi sp,sp,-12 + 100e9b8: df000215 stw fp,8(sp) + 100e9bc: df000204 addi fp,sp,8 +#else + INT16U *prdytbl; +#endif + + + OSRdyGrp = 0; /* Clear the ready list */ + 100e9c0: d0278f05 stb zero,-25028(gp) + prdytbl = &OSRdyTbl[0]; + 100e9c4: d0a78f44 addi r2,gp,-25027 + 100e9c8: e0bffe15 stw r2,-8(fp) + for (i = 0; i < OS_RDY_TBL_SIZE; i++) { + 100e9cc: e03fff05 stb zero,-4(fp) + 100e9d0: 00000806 br 100e9f4 + *prdytbl++ = 0; + 100e9d4: e0bffe17 ldw r2,-8(fp) + 100e9d8: 10000005 stb zero,0(r2) + 100e9dc: e0bffe17 ldw r2,-8(fp) + 100e9e0: 10800044 addi r2,r2,1 + 100e9e4: e0bffe15 stw r2,-8(fp) +#endif + + + OSRdyGrp = 0; /* Clear the ready list */ + prdytbl = &OSRdyTbl[0]; + for (i = 0; i < OS_RDY_TBL_SIZE; i++) { + 100e9e8: e0bfff03 ldbu r2,-4(fp) + 100e9ec: 10800044 addi r2,r2,1 + 100e9f0: e0bfff05 stb r2,-4(fp) + 100e9f4: e0bfff03 ldbu r2,-4(fp) + 100e9f8: 108000f0 cmpltui r2,r2,3 + 100e9fc: 103ff51e bne r2,zero,100e9d4 + *prdytbl++ = 0; + } + + OSPrioCur = 0; + 100ea00: d0278545 stb zero,-25067(gp) + OSPrioHighRdy = 0; + 100ea04: d0278505 stb zero,-25068(gp) + + OSTCBHighRdy = (OS_TCB *)0; + 100ea08: d0278d15 stw zero,-25036(gp) + OSTCBCur = (OS_TCB *)0; + 100ea0c: d0279215 stw zero,-25016(gp) +} + 100ea10: e037883a mov sp,fp + 100ea14: df000017 ldw fp,0(sp) + 100ea18: dec00104 addi sp,sp,4 + 100ea1c: f800283a ret + +0100ea20 : +* Returns : none +********************************************************************************************************* +*/ + +static void OS_InitTaskIdle (void) +{ + 100ea20: defff804 addi sp,sp,-32 + 100ea24: dfc00715 stw ra,28(sp) + 100ea28: df000615 stw fp,24(sp) + 100ea2c: df000604 addi fp,sp,24 +#endif + + +#if OS_TASK_CREATE_EXT_EN > 0 + #if OS_STK_GROWTH == 1 + (void)OSTaskCreateExt(OS_TaskIdle, + 100ea30: 018040b4 movhi r6,258 + 100ea34: 31959404 addi r6,r6,22096 + 100ea38: 00bfffd4 movui r2,65535 + 100ea3c: d8800015 stw r2,0(sp) + 100ea40: 008040b4 movhi r2,258 + 100ea44: 10939504 addi r2,r2,20052 + 100ea48: d8800115 stw r2,4(sp) + 100ea4c: 00808004 movi r2,512 + 100ea50: d8800215 stw r2,8(sp) + 100ea54: d8000315 stw zero,12(sp) + 100ea58: 008000c4 movi r2,3 + 100ea5c: d8800415 stw r2,16(sp) + 100ea60: 01004074 movhi r4,257 + 100ea64: 213bb504 addi r4,r4,-4396 + 100ea68: 000b883a mov r5,zero + 100ea6c: 01c00504 movi r7,20 + 100ea70: 1013cb40 call 1013cb4 + OS_TASK_IDLE_PRIO); + #endif +#endif + +#if OS_TASK_NAME_SIZE > 14 + OSTaskNameSet(OS_TASK_IDLE_PRIO, (INT8U *)"uC/OS-II Idle", &err); + 100ea74: 014040b4 movhi r5,258 + 100ea78: 29647604 addi r5,r5,-28200 + 100ea7c: 01000504 movi r4,20 + 100ea80: e1bfff04 addi r6,fp,-4 + 100ea84: 10145e80 call 10145e8 +#else +#if OS_TASK_NAME_SIZE > 7 + OSTaskNameSet(OS_TASK_IDLE_PRIO, (INT8U *)"OS-Idle", &err); +#endif +#endif +} + 100ea88: e037883a mov sp,fp + 100ea8c: dfc00117 ldw ra,4(sp) + 100ea90: df000017 ldw fp,0(sp) + 100ea94: dec00204 addi sp,sp,8 + 100ea98: f800283a ret + +0100ea9c : +********************************************************************************************************* +*/ + +#if OS_TASK_STAT_EN > 0 +static void OS_InitTaskStat (void) +{ + 100ea9c: defff804 addi sp,sp,-32 + 100eaa0: dfc00715 stw ra,28(sp) + 100eaa4: df000615 stw fp,24(sp) + 100eaa8: df000604 addi fp,sp,24 +#endif + + +#if OS_TASK_CREATE_EXT_EN > 0 + #if OS_STK_GROWTH == 1 + (void)OSTaskCreateExt(OS_TaskStat, + 100eaac: 018040b4 movhi r6,258 + 100eab0: 31931c04 addi r6,r6,19568 + 100eab4: 00bfff94 movui r2,65534 + 100eab8: d8800015 stw r2,0(sp) + 100eabc: 008040b4 movhi r2,258 + 100eac0: 10911d04 addi r2,r2,17524 + 100eac4: d8800115 stw r2,4(sp) + 100eac8: 00808004 movi r2,512 + 100eacc: d8800215 stw r2,8(sp) + 100ead0: d8000315 stw zero,12(sp) + 100ead4: 008000c4 movi r2,3 + 100ead8: d8800415 stw r2,16(sp) + 100eadc: 01004074 movhi r4,257 + 100eae0: 213bcc04 addi r4,r4,-4304 + 100eae4: 000b883a mov r5,zero + 100eae8: 01c004c4 movi r7,19 + 100eaec: 1013cb40 call 1013cb4 + OS_TASK_STAT_PRIO); /* One higher than the idle task */ + #endif +#endif + +#if OS_TASK_NAME_SIZE > 14 + OSTaskNameSet(OS_TASK_STAT_PRIO, (INT8U *)"uC/OS-II Stat", &err); + 100eaf0: 014040b4 movhi r5,258 + 100eaf4: 29647a04 addi r5,r5,-28184 + 100eaf8: 010004c4 movi r4,19 + 100eafc: e1bfff04 addi r6,fp,-4 + 100eb00: 10145e80 call 10145e8 +#else +#if OS_TASK_NAME_SIZE > 7 + OSTaskNameSet(OS_TASK_STAT_PRIO, (INT8U *)"OS-Stat", &err); +#endif +#endif +} + 100eb04: e037883a mov sp,fp + 100eb08: dfc00117 ldw ra,4(sp) + 100eb0c: df000017 ldw fp,0(sp) + 100eb10: dec00204 addi sp,sp,8 + 100eb14: f800283a ret + +0100eb18 : +* Returns : none +********************************************************************************************************* +*/ + +static void OS_InitTCBList (void) +{ + 100eb18: defffb04 addi sp,sp,-20 + 100eb1c: dfc00415 stw ra,16(sp) + 100eb20: df000315 stw fp,12(sp) + 100eb24: df000304 addi fp,sp,12 + INT8U i; + OS_TCB *ptcb1; + OS_TCB *ptcb2; + + + OS_MemClr((INT8U *)&OSTCBTbl[0], sizeof(OSTCBTbl)); /* Clear all the TCBs */ + 100eb28: 010040b4 movhi r4,258 + 100eb2c: 21186504 addi r4,r4,24980 + 100eb30: 01414404 movi r5,1296 + 100eb34: 100ebf80 call 100ebf8 + OS_MemClr((INT8U *)&OSTCBPrioTbl[0], sizeof(OSTCBPrioTbl)); /* Clear the priority table */ + 100eb38: 010040b4 movhi r4,258 + 100eb3c: 2119a904 addi r4,r4,26276 + 100eb40: 01401504 movi r5,84 + 100eb44: 100ebf80 call 100ebf8 + ptcb1 = &OSTCBTbl[0]; + 100eb48: 008040b4 movhi r2,258 + 100eb4c: 10986504 addi r2,r2,24980 + 100eb50: e0bffe15 stw r2,-8(fp) + ptcb2 = &OSTCBTbl[1]; + 100eb54: 008040b4 movhi r2,258 + 100eb58: 10988004 addi r2,r2,25088 + 100eb5c: e0bffd15 stw r2,-12(fp) + for (i = 0; i < (OS_MAX_TASKS + OS_N_SYS_TASKS - 1); i++) { /* Init. list of free TCBs */ + 100eb60: e03fff05 stb zero,-4(fp) + 100eb64: 00001106 br 100ebac + ptcb1->OSTCBNext = ptcb2; + 100eb68: e0fffe17 ldw r3,-8(fp) + 100eb6c: e0bffd17 ldw r2,-12(fp) + 100eb70: 18800515 stw r2,20(r3) +#if OS_TASK_NAME_SIZE > 1 + ptcb1->OSTCBTaskName[0] = '?'; /* Unknown name */ + 100eb74: e0fffe17 ldw r3,-8(fp) + 100eb78: 00800fc4 movi r2,63 + 100eb7c: 18801305 stb r2,76(r3) + ptcb1->OSTCBTaskName[1] = OS_ASCII_NUL; + 100eb80: e0bffe17 ldw r2,-8(fp) + 100eb84: 10001345 stb zero,77(r2) +#endif + ptcb1++; + 100eb88: e0bffe17 ldw r2,-8(fp) + 100eb8c: 10801b04 addi r2,r2,108 + 100eb90: e0bffe15 stw r2,-8(fp) + ptcb2++; + 100eb94: e0bffd17 ldw r2,-12(fp) + 100eb98: 10801b04 addi r2,r2,108 + 100eb9c: e0bffd15 stw r2,-12(fp) + + OS_MemClr((INT8U *)&OSTCBTbl[0], sizeof(OSTCBTbl)); /* Clear all the TCBs */ + OS_MemClr((INT8U *)&OSTCBPrioTbl[0], sizeof(OSTCBPrioTbl)); /* Clear the priority table */ + ptcb1 = &OSTCBTbl[0]; + ptcb2 = &OSTCBTbl[1]; + for (i = 0; i < (OS_MAX_TASKS + OS_N_SYS_TASKS - 1); i++) { /* Init. list of free TCBs */ + 100eba0: e0bfff03 ldbu r2,-4(fp) + 100eba4: 10800044 addi r2,r2,1 + 100eba8: e0bfff05 stb r2,-4(fp) + 100ebac: e0bfff03 ldbu r2,-4(fp) + 100ebb0: 108002f0 cmpltui r2,r2,11 + 100ebb4: 103fec1e bne r2,zero,100eb68 + ptcb1->OSTCBTaskName[1] = OS_ASCII_NUL; +#endif + ptcb1++; + ptcb2++; + } + ptcb1->OSTCBNext = (OS_TCB *)0; /* Last OS_TCB */ + 100ebb8: e0bffe17 ldw r2,-8(fp) + 100ebbc: 10000515 stw zero,20(r2) +#if OS_TASK_NAME_SIZE > 1 + ptcb1->OSTCBTaskName[0] = '?'; /* Unknown name */ + 100ebc0: e0fffe17 ldw r3,-8(fp) + 100ebc4: 00800fc4 movi r2,63 + 100ebc8: 18801305 stb r2,76(r3) + ptcb1->OSTCBTaskName[1] = OS_ASCII_NUL; + 100ebcc: e0bffe17 ldw r2,-8(fp) + 100ebd0: 10001345 stb zero,77(r2) +#endif + OSTCBList = (OS_TCB *)0; /* TCB lists initializations */ + 100ebd4: d0278615 stw zero,-25064(gp) + OSTCBFreeList = &OSTCBTbl[0]; + 100ebd8: 008040b4 movhi r2,258 + 100ebdc: 10986504 addi r2,r2,24980 + 100ebe0: d0a78a15 stw r2,-25048(gp) +} + 100ebe4: e037883a mov sp,fp + 100ebe8: dfc00117 ldw ra,4(sp) + 100ebec: df000017 ldw fp,0(sp) + 100ebf0: dec00204 addi sp,sp,8 + 100ebf4: f800283a ret + +0100ebf8 : +* of the alignment of the destination. +********************************************************************************************************* +*/ + +void OS_MemClr (INT8U *pdest, INT16U size) +{ + 100ebf8: defffd04 addi sp,sp,-12 + 100ebfc: df000215 stw fp,8(sp) + 100ec00: df000204 addi fp,sp,8 + 100ec04: e13ffe15 stw r4,-8(fp) + 100ec08: e17fff0d sth r5,-4(fp) + while (size > 0) { + 100ec0c: 00000806 br 100ec30 + *pdest++ = (INT8U)0; + 100ec10: e0bffe17 ldw r2,-8(fp) + 100ec14: 10000005 stb zero,0(r2) + 100ec18: e0bffe17 ldw r2,-8(fp) + 100ec1c: 10800044 addi r2,r2,1 + 100ec20: e0bffe15 stw r2,-8(fp) + size--; + 100ec24: e0bfff0b ldhu r2,-4(fp) + 100ec28: 10bfffc4 addi r2,r2,-1 + 100ec2c: e0bfff0d sth r2,-4(fp) +********************************************************************************************************* +*/ + +void OS_MemClr (INT8U *pdest, INT16U size) +{ + while (size > 0) { + 100ec30: e0bfff0b ldhu r2,-4(fp) + 100ec34: 1004c03a cmpne r2,r2,zero + 100ec38: 103ff51e bne r2,zero,100ec10 + *pdest++ = (INT8U)0; + size--; + } +} + 100ec3c: e037883a mov sp,fp + 100ec40: df000017 ldw fp,0(sp) + 100ec44: dec00104 addi sp,sp,4 + 100ec48: f800283a ret + +0100ec4c : +* of the alignment of the source and destination. +********************************************************************************************************* +*/ + +void OS_MemCopy (INT8U *pdest, INT8U *psrc, INT16U size) +{ + 100ec4c: defffc04 addi sp,sp,-16 + 100ec50: df000315 stw fp,12(sp) + 100ec54: df000304 addi fp,sp,12 + 100ec58: e13ffd15 stw r4,-12(fp) + 100ec5c: e17ffe15 stw r5,-8(fp) + 100ec60: e1bfff0d sth r6,-4(fp) + while (size > 0) { + 100ec64: 00000d06 br 100ec9c + *pdest++ = *psrc++; + 100ec68: e0bffe17 ldw r2,-8(fp) + 100ec6c: 10c00003 ldbu r3,0(r2) + 100ec70: e0bffd17 ldw r2,-12(fp) + 100ec74: 10c00005 stb r3,0(r2) + 100ec78: e0bffd17 ldw r2,-12(fp) + 100ec7c: 10800044 addi r2,r2,1 + 100ec80: e0bffd15 stw r2,-12(fp) + 100ec84: e0bffe17 ldw r2,-8(fp) + 100ec88: 10800044 addi r2,r2,1 + 100ec8c: e0bffe15 stw r2,-8(fp) + size--; + 100ec90: e0bfff0b ldhu r2,-4(fp) + 100ec94: 10bfffc4 addi r2,r2,-1 + 100ec98: e0bfff0d sth r2,-4(fp) +********************************************************************************************************* +*/ + +void OS_MemCopy (INT8U *pdest, INT8U *psrc, INT16U size) +{ + while (size > 0) { + 100ec9c: e0bfff0b ldhu r2,-4(fp) + 100eca0: 1004c03a cmpne r2,r2,zero + 100eca4: 103ff01e bne r2,zero,100ec68 + *pdest++ = *psrc++; + size--; + } +} + 100eca8: e037883a mov sp,fp + 100ecac: df000017 ldw fp,0(sp) + 100ecb0: dec00104 addi sp,sp,4 + 100ecb4: f800283a ret + +0100ecb8 : +* 2) Rescheduling is prevented when the scheduler is locked (see OS_SchedLock()) +********************************************************************************************************* +*/ + +void OS_Sched (void) +{ + 100ecb8: defffb04 addi sp,sp,-20 + 100ecbc: dfc00415 stw ra,16(sp) + 100ecc0: df000315 stw fp,12(sp) + 100ecc4: df000304 addi fp,sp,12 +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 100ecc8: e03fff15 stw zero,-4(fp) +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 100eccc: 0005303a rdctl r2,status + 100ecd0: e0bffe15 stw r2,-8(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 100ecd4: e0fffe17 ldw r3,-8(fp) + 100ecd8: 00bfff84 movi r2,-2 + 100ecdc: 1884703a and r2,r3,r2 + 100ece0: 1001703a wrctl status,r2 + + return context; + 100ece4: e0bffe17 ldw r2,-8(fp) +#endif + + + + OS_ENTER_CRITICAL(); + 100ece8: e0bfff15 stw r2,-4(fp) + if (OSIntNesting == 0) { /* Schedule only if all ISRs done and ... */ + 100ecec: d0a79103 ldbu r2,-25020(gp) + 100ecf0: 10803fcc andi r2,r2,255 + 100ecf4: 1004c03a cmpne r2,r2,zero + 100ecf8: 10001b1e bne r2,zero,100ed68 + if (OSLockNesting == 0) { /* ... scheduler is not locked */ + 100ecfc: d0a78303 ldbu r2,-25076(gp) + 100ed00: 10803fcc andi r2,r2,255 + 100ed04: 1004c03a cmpne r2,r2,zero + 100ed08: 1000171e bne r2,zero,100ed68 + OS_SchedNew(); + 100ed0c: 100ed8c0 call 100ed8c + if (OSPrioHighRdy != OSPrioCur) { /* No Ctx Sw if current task is highest rdy */ + 100ed10: d0a78503 ldbu r2,-25068(gp) + 100ed14: d0e78543 ldbu r3,-25067(gp) + 100ed18: 11003fcc andi r4,r2,255 + 100ed1c: 18803fcc andi r2,r3,255 + 100ed20: 20801126 beq r4,r2,100ed68 + OSTCBHighRdy = OSTCBPrioTbl[OSPrioHighRdy]; + 100ed24: d0a78503 ldbu r2,-25068(gp) + 100ed28: 10803fcc andi r2,r2,255 + 100ed2c: 00c040b4 movhi r3,258 + 100ed30: 18d9a904 addi r3,r3,26276 + 100ed34: 1085883a add r2,r2,r2 + 100ed38: 1085883a add r2,r2,r2 + 100ed3c: 10c5883a add r2,r2,r3 + 100ed40: 10800017 ldw r2,0(r2) + 100ed44: d0a78d15 stw r2,-25036(gp) +#if OS_TASK_PROFILE_EN > 0 + OSTCBHighRdy->OSTCBCtxSwCtr++; /* Inc. # of context switches to this task */ + 100ed48: d0e78d17 ldw r3,-25036(gp) + 100ed4c: 18800e17 ldw r2,56(r3) + 100ed50: 10800044 addi r2,r2,1 + 100ed54: 18800e15 stw r2,56(r3) +#endif + OSCtxSwCtr++; /* Increment context switch counter */ + 100ed58: d0a78817 ldw r2,-25056(gp) + 100ed5c: 10800044 addi r2,r2,1 + 100ed60: d0a78815 stw r2,-25056(gp) + OS_TASK_SW(); /* Perform a context switch */ + 100ed64: 101802c0 call 101802c + 100ed68: e0bfff17 ldw r2,-4(fp) + 100ed6c: e0bffd15 stw r2,-12(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 100ed70: e0bffd17 ldw r2,-12(fp) + 100ed74: 1001703a wrctl status,r2 + } + } + } + OS_EXIT_CRITICAL(); +} + 100ed78: e037883a mov sp,fp + 100ed7c: dfc00117 ldw ra,4(sp) + 100ed80: df000017 ldw fp,0(sp) + 100ed84: dec00204 addi sp,sp,8 + 100ed88: f800283a ret + +0100ed8c : +* 2) Interrupts are assumed to be disabled when this function is called. +********************************************************************************************************* +*/ + +static void OS_SchedNew (void) +{ + 100ed8c: defffe04 addi sp,sp,-8 + 100ed90: df000115 stw fp,4(sp) + 100ed94: df000104 addi fp,sp,4 +#if OS_LOWEST_PRIO <= 63 /* See if we support up to 64 tasks */ + INT8U y; + + + y = OSUnMapTbl[OSRdyGrp]; + 100ed98: d0a78f03 ldbu r2,-25028(gp) + 100ed9c: 10c03fcc andi r3,r2,255 + 100eda0: 008040b4 movhi r2,258 + 100eda4: 10a43604 addi r2,r2,-28456 + 100eda8: 10c5883a add r2,r2,r3 + 100edac: 10800003 ldbu r2,0(r2) + 100edb0: e0bfff05 stb r2,-4(fp) + OSPrioHighRdy = (INT8U)((y << 3) + OSUnMapTbl[OSRdyTbl[y]]); + 100edb4: e0bfff03 ldbu r2,-4(fp) + 100edb8: 100490fa slli r2,r2,3 + 100edbc: 1009883a mov r4,r2 + 100edc0: e0ffff03 ldbu r3,-4(fp) + 100edc4: d0a78f44 addi r2,gp,-25027 + 100edc8: 1885883a add r2,r3,r2 + 100edcc: 10800003 ldbu r2,0(r2) + 100edd0: 10c03fcc andi r3,r2,255 + 100edd4: 008040b4 movhi r2,258 + 100edd8: 10a43604 addi r2,r2,-28456 + 100eddc: 10c5883a add r2,r2,r3 + 100ede0: 10800003 ldbu r2,0(r2) + 100ede4: 2085883a add r2,r4,r2 + 100ede8: d0a78505 stb r2,-25068(gp) + OSPrioHighRdy = (INT8U)((y << 4) + OSUnMapTbl[(*ptbl & 0xFF)]); + } else { + OSPrioHighRdy = (INT8U)((y << 4) + OSUnMapTbl[(*ptbl >> 8) & 0xFF] + 8); + } +#endif +} + 100edec: e037883a mov sp,fp + 100edf0: df000017 ldw fp,0(sp) + 100edf4: dec00104 addi sp,sp,4 + 100edf8: f800283a ret + +0100edfc : +********************************************************************************************************* +*/ + +#if (OS_EVENT_NAME_SIZE > 1) || (OS_FLAG_NAME_SIZE > 1) || (OS_MEM_NAME_SIZE > 1) || (OS_TASK_NAME_SIZE > 1) || (OS_TMR_CFG_NAME_SIZE > 1) +INT8U OS_StrCopy (INT8U *pdest, INT8U *psrc) +{ + 100edfc: defffc04 addi sp,sp,-16 + 100ee00: df000315 stw fp,12(sp) + 100ee04: df000304 addi fp,sp,12 + 100ee08: e13ffe15 stw r4,-8(fp) + 100ee0c: e17fff15 stw r5,-4(fp) + INT8U len; + + + len = 0; + 100ee10: e03ffd05 stb zero,-12(fp) + while (*psrc != OS_ASCII_NUL) { + 100ee14: 00000d06 br 100ee4c + *pdest++ = *psrc++; + 100ee18: e0bfff17 ldw r2,-4(fp) + 100ee1c: 10c00003 ldbu r3,0(r2) + 100ee20: e0bffe17 ldw r2,-8(fp) + 100ee24: 10c00005 stb r3,0(r2) + 100ee28: e0bffe17 ldw r2,-8(fp) + 100ee2c: 10800044 addi r2,r2,1 + 100ee30: e0bffe15 stw r2,-8(fp) + 100ee34: e0bfff17 ldw r2,-4(fp) + 100ee38: 10800044 addi r2,r2,1 + 100ee3c: e0bfff15 stw r2,-4(fp) + len++; + 100ee40: e0bffd03 ldbu r2,-12(fp) + 100ee44: 10800044 addi r2,r2,1 + 100ee48: e0bffd05 stb r2,-12(fp) +{ + INT8U len; + + + len = 0; + while (*psrc != OS_ASCII_NUL) { + 100ee4c: e0bfff17 ldw r2,-4(fp) + 100ee50: 10800003 ldbu r2,0(r2) + 100ee54: 10803fcc andi r2,r2,255 + 100ee58: 1004c03a cmpne r2,r2,zero + 100ee5c: 103fee1e bne r2,zero,100ee18 + *pdest++ = *psrc++; + len++; + } + *pdest = OS_ASCII_NUL; + 100ee60: e0bffe17 ldw r2,-8(fp) + 100ee64: 10000005 stb zero,0(r2) + return (len); + 100ee68: e0bffd03 ldbu r2,-12(fp) +} + 100ee6c: e037883a mov sp,fp + 100ee70: df000017 ldw fp,0(sp) + 100ee74: dec00104 addi sp,sp,4 + 100ee78: f800283a ret + +0100ee7c : +********************************************************************************************************* +*/ + +#if (OS_EVENT_NAME_SIZE > 1) || (OS_FLAG_NAME_SIZE > 1) || (OS_MEM_NAME_SIZE > 1) || (OS_TASK_NAME_SIZE > 1) || (OS_TMR_CFG_NAME_SIZE > 1) +INT8U OS_StrLen (INT8U *psrc) +{ + 100ee7c: defffd04 addi sp,sp,-12 + 100ee80: df000215 stw fp,8(sp) + 100ee84: df000204 addi fp,sp,8 + 100ee88: e13fff15 stw r4,-4(fp) + INT8U len; + + + len = 0; + 100ee8c: e03ffe05 stb zero,-8(fp) + while (*psrc != OS_ASCII_NUL) { + 100ee90: 00000606 br 100eeac + psrc++; + 100ee94: e0bfff17 ldw r2,-4(fp) + 100ee98: 10800044 addi r2,r2,1 + 100ee9c: e0bfff15 stw r2,-4(fp) + len++; + 100eea0: e0bffe03 ldbu r2,-8(fp) + 100eea4: 10800044 addi r2,r2,1 + 100eea8: e0bffe05 stb r2,-8(fp) +{ + INT8U len; + + + len = 0; + while (*psrc != OS_ASCII_NUL) { + 100eeac: e0bfff17 ldw r2,-4(fp) + 100eeb0: 10800003 ldbu r2,0(r2) + 100eeb4: 10803fcc andi r2,r2,255 + 100eeb8: 1004c03a cmpne r2,r2,zero + 100eebc: 103ff51e bne r2,zero,100ee94 + psrc++; + len++; + } + return (len); + 100eec0: e0bffe03 ldbu r2,-8(fp) +} + 100eec4: e037883a mov sp,fp + 100eec8: df000017 ldw fp,0(sp) + 100eecc: dec00104 addi sp,sp,4 + 100eed0: f800283a ret + +0100eed4 : +* power. +********************************************************************************************************* +*/ + +void OS_TaskIdle (void *p_arg) +{ + 100eed4: defffa04 addi sp,sp,-24 + 100eed8: dfc00515 stw ra,20(sp) + 100eedc: df000415 stw fp,16(sp) + 100eee0: df000404 addi fp,sp,16 + 100eee4: e13fff15 stw r4,-4(fp) +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 100eee8: e03ffe15 stw zero,-8(fp) +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 100eeec: 0005303a rdctl r2,status + 100eef0: e0bffd15 stw r2,-12(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 100eef4: e0fffd17 ldw r3,-12(fp) + 100eef8: 00bfff84 movi r2,-2 + 100eefc: 1884703a and r2,r3,r2 + 100ef00: 1001703a wrctl status,r2 + + return context; + 100ef04: e0bffd17 ldw r2,-12(fp) + + + + (void)p_arg; /* Prevent compiler warning for not using 'p_arg' */ + for (;;) { + OS_ENTER_CRITICAL(); + 100ef08: e0bffe15 stw r2,-8(fp) + OSIdleCtr++; + 100ef0c: d0a78417 ldw r2,-25072(gp) + 100ef10: 10800044 addi r2,r2,1 + 100ef14: d0a78415 stw r2,-25072(gp) + 100ef18: e0bffe17 ldw r2,-8(fp) + 100ef1c: e0bffc15 stw r2,-16(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 100ef20: e0bffc17 ldw r2,-16(fp) + 100ef24: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + OSTaskIdleHook(); /* Call user definable HOOK */ + 100ef28: 10184d80 call 10184d8 + } + 100ef2c: 003fef06 br 100eeec + +0100ef30 : +********************************************************************************************************* +*/ + +#if OS_TASK_STAT_EN > 0 +void OS_TaskStat (void *p_arg) +{ + 100ef30: defffa04 addi sp,sp,-24 + 100ef34: dfc00515 stw ra,20(sp) + 100ef38: df000415 stw fp,16(sp) + 100ef3c: df000404 addi fp,sp,16 + 100ef40: e13fff15 stw r4,-4(fp) +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 100ef44: e03ffe15 stw zero,-8(fp) +#endif + + + + (void)p_arg; /* Prevent compiler warning for not using 'p_arg' */ + while (OSStatRdy == OS_FALSE) { + 100ef48: 00000206 br 100ef54 + OSTimeDly(2 * OS_TICKS_PER_SEC / 10); /* Wait until statistic task is ready */ + 100ef4c: 01003204 movi r4,200 + 100ef50: 1014fac0 call 1014fac +#endif + + + + (void)p_arg; /* Prevent compiler warning for not using 'p_arg' */ + while (OSStatRdy == OS_FALSE) { + 100ef54: d0a79503 ldbu r2,-25004(gp) + 100ef58: 10803fcc andi r2,r2,255 + 100ef5c: 1005003a cmpeq r2,r2,zero + 100ef60: 103ffa1e bne r2,zero,100ef4c + OSTimeDly(2 * OS_TICKS_PER_SEC / 10); /* Wait until statistic task is ready */ + } + OSIdleCtrMax /= 100L; + 100ef64: d1278917 ldw r4,-25052(gp) + 100ef68: 01401904 movi r5,100 + 100ef6c: 100bc340 call 100bc34 <__udivsi3> + 100ef70: d0a78915 stw r2,-25052(gp) + if (OSIdleCtrMax == 0L) { + 100ef74: d0a78917 ldw r2,-25052(gp) + 100ef78: 1004c03a cmpne r2,r2,zero + 100ef7c: 1000031e bne r2,zero,100ef8c + OSCPUUsage = 0; + 100ef80: d0278b05 stb zero,-25044(gp) + (void)OSTaskSuspend(OS_PRIO_SELF); + 100ef84: 01003fc4 movi r4,255 + 100ef88: 1014bc00 call 1014bc0 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 100ef8c: 0005303a rdctl r2,status + 100ef90: e0bffd15 stw r2,-12(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 100ef94: e0fffd17 ldw r3,-12(fp) + 100ef98: 00bfff84 movi r2,-2 + 100ef9c: 1884703a and r2,r3,r2 + 100efa0: 1001703a wrctl status,r2 + + return context; + 100efa4: e0bffd17 ldw r2,-12(fp) + } + for (;;) { + OS_ENTER_CRITICAL(); + 100efa8: e0bffe15 stw r2,-8(fp) + OSIdleCtrRun = OSIdleCtr; /* Obtain the of the idle counter for the past second */ + 100efac: d0a78417 ldw r2,-25072(gp) + 100efb0: d0a79615 stw r2,-25000(gp) + OSIdleCtr = 0L; /* Reset the idle counter for the next second */ + 100efb4: d0278415 stw zero,-25072(gp) + 100efb8: e0bffe17 ldw r2,-8(fp) + 100efbc: e0bffc15 stw r2,-16(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 100efc0: e0bffc17 ldw r2,-16(fp) + 100efc4: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + OSCPUUsage = (INT8U)(100L - OSIdleCtrRun / OSIdleCtrMax); + 100efc8: d1279617 ldw r4,-25000(gp) + 100efcc: d1678917 ldw r5,-25052(gp) + 100efd0: 100bc340 call 100bc34 <__udivsi3> + 100efd4: 1007883a mov r3,r2 + 100efd8: 00801904 movi r2,100 + 100efdc: 10c5c83a sub r2,r2,r3 + 100efe0: d0a78b05 stb r2,-25044(gp) + OSTaskStatHook(); /* Invoke user definable hook */ + 100efe4: 10184680 call 1018468 +#if (OS_TASK_STAT_STK_CHK_EN > 0) && (OS_TASK_CREATE_EXT_EN > 0) + OS_TaskStatStkChk(); /* Check the stacks for each task */ + 100efe8: 100eff80 call 100eff8 +#endif + OSTimeDly(OS_TICKS_PER_SEC / 10); /* Accumulate OSIdleCtr for the next 1/10 second */ + 100efec: 01001904 movi r4,100 + 100eff0: 1014fac0 call 1014fac + } + 100eff4: 003fe506 br 100ef8c + +0100eff8 : +********************************************************************************************************* +*/ + +#if (OS_TASK_STAT_STK_CHK_EN > 0) && (OS_TASK_CREATE_EXT_EN > 0) +void OS_TaskStatStkChk (void) +{ + 100eff8: defffa04 addi sp,sp,-24 + 100effc: dfc00515 stw ra,20(sp) + 100f000: df000415 stw fp,16(sp) + 100f004: df000404 addi fp,sp,16 + OS_STK_DATA stk_data; + INT8U err; + INT8U prio; + + + for (prio = 0; prio <= OS_TASK_IDLE_PRIO; prio++) { + 100f008: e03ffc05 stb zero,-16(fp) + 100f00c: 00002406 br 100f0a0 + err = OSTaskStkChk(prio, &stk_data); + 100f010: e13ffc03 ldbu r4,-16(fp) + 100f014: e17ffe04 addi r5,fp,-8 + 100f018: 10149c40 call 10149c4 + 100f01c: e0bffc45 stb r2,-15(fp) + if (err == OS_ERR_NONE) { + 100f020: e0bffc43 ldbu r2,-15(fp) + 100f024: 1004c03a cmpne r2,r2,zero + 100f028: 10001a1e bne r2,zero,100f094 + ptcb = OSTCBPrioTbl[prio]; + 100f02c: e0bffc03 ldbu r2,-16(fp) + 100f030: 00c040b4 movhi r3,258 + 100f034: 18d9a904 addi r3,r3,26276 + 100f038: 1085883a add r2,r2,r2 + 100f03c: 1085883a add r2,r2,r2 + 100f040: 10c5883a add r2,r2,r3 + 100f044: 10800017 ldw r2,0(r2) + 100f048: e0bffd15 stw r2,-12(fp) + if (ptcb != (OS_TCB *)0) { /* Make sure task 'ptcb' is ... */ + 100f04c: e0bffd17 ldw r2,-12(fp) + 100f050: 1005003a cmpeq r2,r2,zero + 100f054: 10000f1e bne r2,zero,100f094 + if (ptcb != OS_TCB_RESERVED) { /* ... still valid. */ + 100f058: e0bffd17 ldw r2,-12(fp) + 100f05c: 10800060 cmpeqi r2,r2,1 + 100f060: 10000c1e bne r2,zero,100f094 +#if OS_TASK_PROFILE_EN > 0 + #if OS_STK_GROWTH == 1 + ptcb->OSTCBStkBase = ptcb->OSTCBStkBottom + ptcb->OSTCBStkSize; + 100f064: e0bffd17 ldw r2,-12(fp) + 100f068: 10c00217 ldw r3,8(r2) + 100f06c: e0bffd17 ldw r2,-12(fp) + 100f070: 10800317 ldw r2,12(r2) + 100f074: 1085883a add r2,r2,r2 + 100f078: 1085883a add r2,r2,r2 + 100f07c: 1887883a add r3,r3,r2 + 100f080: e0bffd17 ldw r2,-12(fp) + 100f084: 10c01115 stw r3,68(r2) + #else + ptcb->OSTCBStkBase = ptcb->OSTCBStkBottom - ptcb->OSTCBStkSize; + #endif + ptcb->OSTCBStkUsed = stk_data.OSUsed; /* Store the number of bytes used */ + 100f088: e0ffff17 ldw r3,-4(fp) + 100f08c: e0bffd17 ldw r2,-12(fp) + 100f090: 10c01215 stw r3,72(r2) + OS_STK_DATA stk_data; + INT8U err; + INT8U prio; + + + for (prio = 0; prio <= OS_TASK_IDLE_PRIO; prio++) { + 100f094: e0bffc03 ldbu r2,-16(fp) + 100f098: 10800044 addi r2,r2,1 + 100f09c: e0bffc05 stb r2,-16(fp) + 100f0a0: e0bffc03 ldbu r2,-16(fp) + 100f0a4: 10800570 cmpltui r2,r2,21 + 100f0a8: 103fd91e bne r2,zero,100f010 +#endif + } + } + } + } +} + 100f0ac: e037883a mov sp,fp + 100f0b0: dfc00117 ldw ra,4(sp) + 100f0b4: df000017 ldw fp,0(sp) + 100f0b8: dec00204 addi sp,sp,8 + 100f0bc: f800283a ret + +0100f0c0 : +* Note : This function is INTERNAL to uC/OS-II and your application should not call it. +********************************************************************************************************* +*/ + +INT8U OS_TCBInit (INT8U prio, OS_STK *ptos, OS_STK *pbos, INT16U id, INT32U stk_size, void *pext, INT16U opt) +{ + 100f0c0: defff104 addi sp,sp,-60 + 100f0c4: dfc00e15 stw ra,56(sp) + 100f0c8: df000d15 stw fp,52(sp) + 100f0cc: df000d04 addi fp,sp,52 + 100f0d0: e17ffb15 stw r5,-20(fp) + 100f0d4: e1bffc15 stw r6,-16(fp) + 100f0d8: e0800417 ldw r2,16(fp) + 100f0dc: e13ffa05 stb r4,-24(fp) + 100f0e0: e1fffd0d sth r7,-12(fp) + 100f0e4: e0bffe0d sth r2,-8(fp) + OS_TCB *ptcb; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 100f0e8: e03ff815 stw zero,-32(fp) +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 100f0ec: 0005303a rdctl r2,status + 100f0f0: e0bff715 stw r2,-36(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 100f0f4: e0fff717 ldw r3,-36(fp) + 100f0f8: 00bfff84 movi r2,-2 + 100f0fc: 1884703a and r2,r3,r2 + 100f100: 1001703a wrctl status,r2 + + return context; + 100f104: e0bff717 ldw r2,-36(fp) +#endif + + + + OS_ENTER_CRITICAL(); + 100f108: e0bff815 stw r2,-32(fp) + ptcb = OSTCBFreeList; /* Get a free TCB from the free TCB list */ + 100f10c: d0a78a17 ldw r2,-25048(gp) + 100f110: e0bff915 stw r2,-28(fp) + if (ptcb != (OS_TCB *)0) { + 100f114: e0bff917 ldw r2,-28(fp) + 100f118: 1005003a cmpeq r2,r2,zero + 100f11c: 1000941e bne r2,zero,100f370 + OSTCBFreeList = ptcb->OSTCBNext; /* Update pointer to free TCB list */ + 100f120: e0bff917 ldw r2,-28(fp) + 100f124: 10800517 ldw r2,20(r2) + 100f128: d0a78a15 stw r2,-25048(gp) + 100f12c: e0bff817 ldw r2,-32(fp) + 100f130: e0bff615 stw r2,-40(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 100f134: e0bff617 ldw r2,-40(fp) + 100f138: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + ptcb->OSTCBStkPtr = ptos; /* Load Stack pointer in TCB */ + 100f13c: e0fff917 ldw r3,-28(fp) + 100f140: e0bffb17 ldw r2,-20(fp) + 100f144: 18800015 stw r2,0(r3) + ptcb->OSTCBPrio = prio; /* Load task priority into TCB */ + 100f148: e0fff917 ldw r3,-28(fp) + 100f14c: e0bffa03 ldbu r2,-24(fp) + 100f150: 18800c85 stb r2,50(r3) + ptcb->OSTCBStat = OS_STAT_RDY; /* Task is ready to run */ + 100f154: e0bff917 ldw r2,-28(fp) + 100f158: 10000c05 stb zero,48(r2) + ptcb->OSTCBStatPend = OS_STAT_PEND_OK; /* Clear pend status */ + 100f15c: e0bff917 ldw r2,-28(fp) + 100f160: 10000c45 stb zero,49(r2) + ptcb->OSTCBDly = 0; /* Task is not delayed */ + 100f164: e0bff917 ldw r2,-28(fp) + 100f168: 10000b8d sth zero,46(r2) + +#if OS_TASK_CREATE_EXT_EN > 0 + ptcb->OSTCBExtPtr = pext; /* Store pointer to TCB extension */ + 100f16c: e0fff917 ldw r3,-28(fp) + 100f170: e0800317 ldw r2,12(fp) + 100f174: 18800115 stw r2,4(r3) + ptcb->OSTCBStkSize = stk_size; /* Store stack size */ + 100f178: e0fff917 ldw r3,-28(fp) + 100f17c: e0800217 ldw r2,8(fp) + 100f180: 18800315 stw r2,12(r3) + ptcb->OSTCBStkBottom = pbos; /* Store pointer to bottom of stack */ + 100f184: e0fff917 ldw r3,-28(fp) + 100f188: e0bffc17 ldw r2,-16(fp) + 100f18c: 18800215 stw r2,8(r3) + ptcb->OSTCBOpt = opt; /* Store task options */ + 100f190: e0fff917 ldw r3,-28(fp) + 100f194: e0bffe0b ldhu r2,-8(fp) + 100f198: 1880040d sth r2,16(r3) + ptcb->OSTCBId = id; /* Store task ID */ + 100f19c: e0fff917 ldw r3,-28(fp) + 100f1a0: e0bffd0b ldhu r2,-12(fp) + 100f1a4: 1880048d sth r2,18(r3) + opt = opt; + id = id; +#endif + +#if OS_TASK_DEL_EN > 0 + ptcb->OSTCBDelReq = OS_ERR_NONE; + 100f1a8: e0bff917 ldw r2,-28(fp) + 100f1ac: 10000dc5 stb zero,55(r2) +#endif + +#if OS_LOWEST_PRIO <= 63 + ptcb->OSTCBY = (INT8U)(prio >> 3); /* Pre-compute X, Y, BitX and BitY */ + 100f1b0: e0bffa03 ldbu r2,-24(fp) + 100f1b4: 1004d0fa srli r2,r2,3 + 100f1b8: 1007883a mov r3,r2 + 100f1bc: e0bff917 ldw r2,-28(fp) + 100f1c0: 10c00d05 stb r3,52(r2) + ptcb->OSTCBX = (INT8U)(prio & 0x07); + 100f1c4: e0bffa03 ldbu r2,-24(fp) + 100f1c8: 108001cc andi r2,r2,7 + 100f1cc: 1007883a mov r3,r2 + 100f1d0: e0bff917 ldw r2,-28(fp) + 100f1d4: 10c00cc5 stb r3,51(r2) + ptcb->OSTCBBitY = (INT8U)(1 << ptcb->OSTCBY); + 100f1d8: e0bff917 ldw r2,-28(fp) + 100f1dc: 10800d03 ldbu r2,52(r2) + 100f1e0: 10c03fcc andi r3,r2,255 + 100f1e4: 00800044 movi r2,1 + 100f1e8: 10c4983a sll r2,r2,r3 + 100f1ec: 1007883a mov r3,r2 + 100f1f0: e0bff917 ldw r2,-28(fp) + 100f1f4: 10c00d85 stb r3,54(r2) + ptcb->OSTCBBitX = (INT8U)(1 << ptcb->OSTCBX); + 100f1f8: e0bff917 ldw r2,-28(fp) + 100f1fc: 10800cc3 ldbu r2,51(r2) + 100f200: 10c03fcc andi r3,r2,255 + 100f204: 00800044 movi r2,1 + 100f208: 10c4983a sll r2,r2,r3 + 100f20c: 1007883a mov r3,r2 + 100f210: e0bff917 ldw r2,-28(fp) + 100f214: 10c00d45 stb r3,53(r2) + ptcb->OSTCBBitY = (INT16U)(1 << ptcb->OSTCBY); + ptcb->OSTCBBitX = (INT16U)(1 << ptcb->OSTCBX); +#endif + +#if (OS_EVENT_EN) + ptcb->OSTCBEventPtr = (OS_EVENT *)0; /* Task is not pending on an event */ + 100f218: e0bff917 ldw r2,-28(fp) + 100f21c: 10000715 stw zero,28(r2) +#if (OS_EVENT_MULTI_EN > 0) + ptcb->OSTCBEventMultiPtr = (OS_EVENT **)0; /* Task is not pending on any events */ + 100f220: e0bff917 ldw r2,-28(fp) + 100f224: 10000815 stw zero,32(r2) +#endif +#endif + +#if (OS_FLAG_EN > 0) && (OS_MAX_FLAGS > 0) && (OS_TASK_DEL_EN > 0) + ptcb->OSTCBFlagNode = (OS_FLAG_NODE *)0; /* Task is not pending on an event flag */ + 100f228: e0bff917 ldw r2,-28(fp) + 100f22c: 10000a15 stw zero,40(r2) +#endif + +#if (OS_MBOX_EN > 0) || ((OS_Q_EN > 0) && (OS_MAX_QS > 0)) + ptcb->OSTCBMsg = (void *)0; /* No message received */ + 100f230: e0bff917 ldw r2,-28(fp) + 100f234: 10000915 stw zero,36(r2) +#endif + +#if OS_TASK_PROFILE_EN > 0 + ptcb->OSTCBCtxSwCtr = 0L; /* Initialize profiling variables */ + 100f238: e0bff917 ldw r2,-28(fp) + 100f23c: 10000e15 stw zero,56(r2) + ptcb->OSTCBCyclesStart = 0L; + 100f240: e0bff917 ldw r2,-28(fp) + 100f244: 10001015 stw zero,64(r2) + ptcb->OSTCBCyclesTot = 0L; + 100f248: e0bff917 ldw r2,-28(fp) + 100f24c: 10000f15 stw zero,60(r2) + ptcb->OSTCBStkBase = (OS_STK *)0; + 100f250: e0bff917 ldw r2,-28(fp) + 100f254: 10001115 stw zero,68(r2) + ptcb->OSTCBStkUsed = 0L; + 100f258: e0bff917 ldw r2,-28(fp) + 100f25c: 10001215 stw zero,72(r2) +#endif + +#if OS_TASK_NAME_SIZE > 1 + ptcb->OSTCBTaskName[0] = '?'; /* Unknown name at task creation */ + 100f260: e0fff917 ldw r3,-28(fp) + 100f264: 00800fc4 movi r2,63 + 100f268: 18801305 stb r2,76(r3) + ptcb->OSTCBTaskName[1] = OS_ASCII_NUL; + 100f26c: e0bff917 ldw r2,-28(fp) + 100f270: 10001345 stb zero,77(r2) +#endif + + OSTCBInitHook(ptcb); + 100f274: e13ff917 ldw r4,-28(fp) + 100f278: 10184f40 call 10184f4 + + OSTaskCreateHook(ptcb); /* Call user defined hook */ + 100f27c: e13ff917 ldw r4,-28(fp) + 100f280: 101840c0 call 101840c +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 100f284: 0005303a rdctl r2,status + 100f288: e0bff515 stw r2,-44(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 100f28c: e0fff517 ldw r3,-44(fp) + 100f290: 00bfff84 movi r2,-2 + 100f294: 1884703a and r2,r3,r2 + 100f298: 1001703a wrctl status,r2 + + return context; + 100f29c: e0bff517 ldw r2,-44(fp) + + OS_ENTER_CRITICAL(); + 100f2a0: e0bff815 stw r2,-32(fp) + OSTCBPrioTbl[prio] = ptcb; + 100f2a4: e0bffa03 ldbu r2,-24(fp) + 100f2a8: 00c040b4 movhi r3,258 + 100f2ac: 18d9a904 addi r3,r3,26276 + 100f2b0: 1085883a add r2,r2,r2 + 100f2b4: 1085883a add r2,r2,r2 + 100f2b8: 10c7883a add r3,r2,r3 + 100f2bc: e0bff917 ldw r2,-28(fp) + 100f2c0: 18800015 stw r2,0(r3) + ptcb->OSTCBNext = OSTCBList; /* Link into TCB chain */ + 100f2c4: d0e78617 ldw r3,-25064(gp) + 100f2c8: e0bff917 ldw r2,-28(fp) + 100f2cc: 10c00515 stw r3,20(r2) + ptcb->OSTCBPrev = (OS_TCB *)0; + 100f2d0: e0bff917 ldw r2,-28(fp) + 100f2d4: 10000615 stw zero,24(r2) + if (OSTCBList != (OS_TCB *)0) { + 100f2d8: d0a78617 ldw r2,-25064(gp) + 100f2dc: 1005003a cmpeq r2,r2,zero + 100f2e0: 1000031e bne r2,zero,100f2f0 + OSTCBList->OSTCBPrev = ptcb; + 100f2e4: d0e78617 ldw r3,-25064(gp) + 100f2e8: e0bff917 ldw r2,-28(fp) + 100f2ec: 18800615 stw r2,24(r3) + } + OSTCBList = ptcb; + 100f2f0: e0bff917 ldw r2,-28(fp) + 100f2f4: d0a78615 stw r2,-25064(gp) + OSRdyGrp |= ptcb->OSTCBBitY; /* Make task ready to run */ + 100f2f8: e0bff917 ldw r2,-28(fp) + 100f2fc: 10c00d83 ldbu r3,54(r2) + 100f300: d0a78f03 ldbu r2,-25028(gp) + 100f304: 1884b03a or r2,r3,r2 + 100f308: d0a78f05 stb r2,-25028(gp) + OSRdyTbl[ptcb->OSTCBY] |= ptcb->OSTCBBitX; + 100f30c: e0bff917 ldw r2,-28(fp) + 100f310: 10800d03 ldbu r2,52(r2) + 100f314: 11003fcc andi r4,r2,255 + 100f318: e0bff917 ldw r2,-28(fp) + 100f31c: 10800d03 ldbu r2,52(r2) + 100f320: 10c03fcc andi r3,r2,255 + 100f324: d0a78f44 addi r2,gp,-25027 + 100f328: 1885883a add r2,r3,r2 + 100f32c: 10c00003 ldbu r3,0(r2) + 100f330: e0bff917 ldw r2,-28(fp) + 100f334: 10800d43 ldbu r2,53(r2) + 100f338: 1884b03a or r2,r3,r2 + 100f33c: 1007883a mov r3,r2 + 100f340: d0a78f44 addi r2,gp,-25027 + 100f344: 2085883a add r2,r4,r2 + 100f348: 10c00005 stb r3,0(r2) + OSTaskCtr++; /* Increment the #tasks counter */ + 100f34c: d0a78b43 ldbu r2,-25043(gp) + 100f350: 10800044 addi r2,r2,1 + 100f354: d0a78b45 stb r2,-25043(gp) + 100f358: e0bff817 ldw r2,-32(fp) + 100f35c: e0bff415 stw r2,-48(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 100f360: e0bff417 ldw r2,-48(fp) + 100f364: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_NONE); + 100f368: e03fff15 stw zero,-4(fp) + 100f36c: 00000606 br 100f388 + 100f370: e0bff817 ldw r2,-32(fp) + 100f374: e0bff315 stw r2,-52(fp) + 100f378: e0bff317 ldw r2,-52(fp) + 100f37c: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_NO_MORE_TCB); + 100f380: 00801084 movi r2,66 + 100f384: e0bfff15 stw r2,-4(fp) + 100f388: e0bfff17 ldw r2,-4(fp) +} + 100f38c: e037883a mov sp,fp + 100f390: dfc00117 ldw ra,4(sp) + 100f394: df000017 ldw fp,0(sp) + 100f398: dec00204 addi sp,sp,8 + 100f39c: f800283a ret + +0100f3a0 : +********************************************************************************************************* +*/ + +#if OS_DEBUG_EN > 0 +void OSDebugInit (void) +{ + 100f3a0: defffe04 addi sp,sp,-8 + 100f3a4: df000115 stw fp,4(sp) + 100f3a8: df000104 addi fp,sp,4 + void *ptemp; + + + ptemp = (void *)&OSDebugEn; + 100f3ac: d0a01804 addi r2,gp,-32672 + 100f3b0: e0bfff15 stw r2,-4(fp) + + ptemp = (void *)&OSEndiannessTest; + 100f3b4: d0a01904 addi r2,gp,-32668 + 100f3b8: e0bfff15 stw r2,-4(fp) + + ptemp = (void *)&OSEventMax; + 100f3bc: d0a01a84 addi r2,gp,-32662 + 100f3c0: e0bfff15 stw r2,-4(fp) + ptemp = (void *)&OSEventNameSize; + 100f3c4: d0a01b04 addi r2,gp,-32660 + 100f3c8: e0bfff15 stw r2,-4(fp) + ptemp = (void *)&OSEventEn; + 100f3cc: d0a01a04 addi r2,gp,-32664 + 100f3d0: e0bfff15 stw r2,-4(fp) + ptemp = (void *)&OSEventSize; + 100f3d4: d0a01b84 addi r2,gp,-32658 + 100f3d8: e0bfff15 stw r2,-4(fp) + ptemp = (void *)&OSEventTblSize; + 100f3dc: d0a01c04 addi r2,gp,-32656 + 100f3e0: e0bfff15 stw r2,-4(fp) + ptemp = (void *)&OSEventMultiEn; + 100f3e4: d0a01c84 addi r2,gp,-32654 + 100f3e8: e0bfff15 stw r2,-4(fp) + + ptemp = (void *)&OSFlagEn; + 100f3ec: d0a01d04 addi r2,gp,-32652 + 100f3f0: e0bfff15 stw r2,-4(fp) + ptemp = (void *)&OSFlagGrpSize; + 100f3f4: d0a01d84 addi r2,gp,-32650 + 100f3f8: e0bfff15 stw r2,-4(fp) + ptemp = (void *)&OSFlagNodeSize; + 100f3fc: d0a01e04 addi r2,gp,-32648 + 100f400: e0bfff15 stw r2,-4(fp) + ptemp = (void *)&OSFlagWidth; + 100f404: d0a01e84 addi r2,gp,-32646 + 100f408: e0bfff15 stw r2,-4(fp) + ptemp = (void *)&OSFlagMax; + 100f40c: d0a01f04 addi r2,gp,-32644 + 100f410: e0bfff15 stw r2,-4(fp) + ptemp = (void *)&OSFlagNameSize; + 100f414: d0a01f84 addi r2,gp,-32642 + 100f418: e0bfff15 stw r2,-4(fp) + + ptemp = (void *)&OSLowestPrio; + 100f41c: d0a02004 addi r2,gp,-32640 + 100f420: e0bfff15 stw r2,-4(fp) + + ptemp = (void *)&OSMboxEn; + 100f424: d0a02084 addi r2,gp,-32638 + 100f428: e0bfff15 stw r2,-4(fp) + + ptemp = (void *)&OSMemEn; + 100f42c: d0a02104 addi r2,gp,-32636 + 100f430: e0bfff15 stw r2,-4(fp) + ptemp = (void *)&OSMemMax; + 100f434: d0a02184 addi r2,gp,-32634 + 100f438: e0bfff15 stw r2,-4(fp) + ptemp = (void *)&OSMemNameSize; + 100f43c: d0a02204 addi r2,gp,-32632 + 100f440: e0bfff15 stw r2,-4(fp) + ptemp = (void *)&OSMemSize; + 100f444: d0a02284 addi r2,gp,-32630 + 100f448: e0bfff15 stw r2,-4(fp) + ptemp = (void *)&OSMemTblSize; + 100f44c: d0a02304 addi r2,gp,-32628 + 100f450: e0bfff15 stw r2,-4(fp) + + ptemp = (void *)&OSMutexEn; + 100f454: d0a02384 addi r2,gp,-32626 + 100f458: e0bfff15 stw r2,-4(fp) + + ptemp = (void *)&OSPtrSize; + 100f45c: d0a02404 addi r2,gp,-32624 + 100f460: e0bfff15 stw r2,-4(fp) + + ptemp = (void *)&OSQEn; + 100f464: d0a02484 addi r2,gp,-32622 + 100f468: e0bfff15 stw r2,-4(fp) + ptemp = (void *)&OSQMax; + 100f46c: d0a02504 addi r2,gp,-32620 + 100f470: e0bfff15 stw r2,-4(fp) + ptemp = (void *)&OSQSize; + 100f474: d0a02584 addi r2,gp,-32618 + 100f478: e0bfff15 stw r2,-4(fp) + + ptemp = (void *)&OSRdyTblSize; + 100f47c: d0a02604 addi r2,gp,-32616 + 100f480: e0bfff15 stw r2,-4(fp) + + ptemp = (void *)&OSSemEn; + 100f484: d0a02684 addi r2,gp,-32614 + 100f488: e0bfff15 stw r2,-4(fp) + + ptemp = (void *)&OSStkWidth; + 100f48c: d0a02704 addi r2,gp,-32612 + 100f490: e0bfff15 stw r2,-4(fp) + + ptemp = (void *)&OSTaskCreateEn; + 100f494: d0a02784 addi r2,gp,-32610 + 100f498: e0bfff15 stw r2,-4(fp) + ptemp = (void *)&OSTaskCreateExtEn; + 100f49c: d0a02804 addi r2,gp,-32608 + 100f4a0: e0bfff15 stw r2,-4(fp) + ptemp = (void *)&OSTaskDelEn; + 100f4a4: d0a02884 addi r2,gp,-32606 + 100f4a8: e0bfff15 stw r2,-4(fp) + ptemp = (void *)&OSTaskIdleStkSize; + 100f4ac: d0a02904 addi r2,gp,-32604 + 100f4b0: e0bfff15 stw r2,-4(fp) + ptemp = (void *)&OSTaskProfileEn; + 100f4b4: d0a02984 addi r2,gp,-32602 + 100f4b8: e0bfff15 stw r2,-4(fp) + ptemp = (void *)&OSTaskMax; + 100f4bc: d0a02a04 addi r2,gp,-32600 + 100f4c0: e0bfff15 stw r2,-4(fp) + ptemp = (void *)&OSTaskNameSize; + 100f4c4: d0a02a84 addi r2,gp,-32598 + 100f4c8: e0bfff15 stw r2,-4(fp) + ptemp = (void *)&OSTaskStatEn; + 100f4cc: d0a02b04 addi r2,gp,-32596 + 100f4d0: e0bfff15 stw r2,-4(fp) + ptemp = (void *)&OSTaskStatStkSize; + 100f4d4: d0a02b84 addi r2,gp,-32594 + 100f4d8: e0bfff15 stw r2,-4(fp) + ptemp = (void *)&OSTaskStatStkChkEn; + 100f4dc: d0a02c04 addi r2,gp,-32592 + 100f4e0: e0bfff15 stw r2,-4(fp) + ptemp = (void *)&OSTaskSwHookEn; + 100f4e4: d0a02c84 addi r2,gp,-32590 + 100f4e8: e0bfff15 stw r2,-4(fp) + + ptemp = (void *)&OSTCBPrioTblMax; + 100f4ec: d0a02d04 addi r2,gp,-32588 + 100f4f0: e0bfff15 stw r2,-4(fp) + ptemp = (void *)&OSTCBSize; + 100f4f4: d0a02d84 addi r2,gp,-32586 + 100f4f8: e0bfff15 stw r2,-4(fp) + + ptemp = (void *)&OSTicksPerSec; + 100f4fc: d0a02e04 addi r2,gp,-32584 + 100f500: e0bfff15 stw r2,-4(fp) + ptemp = (void *)&OSTimeTickHookEn; + 100f504: d0a02e84 addi r2,gp,-32582 + 100f508: e0bfff15 stw r2,-4(fp) + + ptemp = (void *)&OSTmrWheelSize; + ptemp = (void *)&OSTmrWheelTblSize; +#endif + + ptemp = (void *)&OSVersionNbr; + 100f50c: d0a02f04 addi r2,gp,-32580 + 100f510: e0bfff15 stw r2,-4(fp) + + ptemp = (void *)&OSDataSize; + 100f514: d0a03404 addi r2,gp,-32560 + 100f518: e0bfff15 stw r2,-4(fp) + + ptemp = ptemp; /* Prevent compiler warning for 'ptemp' not being used! */ +} + 100f51c: e037883a mov sp,fp + 100f520: df000017 ldw fp,0(sp) + 100f524: dec00104 addi sp,sp,4 + 100f528: f800283a ret + +0100f52c : +********************************************************************************************************* +*/ + +#if OS_FLAG_ACCEPT_EN > 0 +OS_FLAGS OSFlagAccept (OS_FLAG_GRP *pgrp, OS_FLAGS flags, INT8U wait_type, INT8U *perr) +{ + 100f52c: defff104 addi sp,sp,-60 + 100f530: df000e15 stw fp,56(sp) + 100f534: df000e04 addi fp,sp,56 + 100f538: e13ffa15 stw r4,-24(fp) + 100f53c: e1fffd15 stw r7,-12(fp) + 100f540: e17ffb0d sth r5,-20(fp) + 100f544: e1bffc05 stb r6,-16(fp) + OS_FLAGS flags_rdy; + INT8U result; + BOOLEAN consume; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 100f548: e03ff815 stw zero,-32(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + 100f54c: e0bffd17 ldw r2,-12(fp) + 100f550: 1004c03a cmpne r2,r2,zero + 100f554: 1000021e bne r2,zero,100f560 + return ((OS_FLAGS)0); + 100f558: e03fff15 stw zero,-4(fp) + 100f55c: 0000bb06 br 100f84c + } + if (pgrp == (OS_FLAG_GRP *)0) { /* Validate 'pgrp' */ + 100f560: e0bffa17 ldw r2,-24(fp) + 100f564: 1004c03a cmpne r2,r2,zero + 100f568: 1000051e bne r2,zero,100f580 + *perr = OS_ERR_FLAG_INVALID_PGRP; + 100f56c: e0fffd17 ldw r3,-12(fp) + 100f570: 00801b84 movi r2,110 + 100f574: 18800005 stb r2,0(r3) + return ((OS_FLAGS)0); + 100f578: e03fff15 stw zero,-4(fp) + 100f57c: 0000b306 br 100f84c + } +#endif + if (pgrp->OSFlagType != OS_EVENT_TYPE_FLAG) { /* Validate event block type */ + 100f580: e0bffa17 ldw r2,-24(fp) + 100f584: 10800003 ldbu r2,0(r2) + 100f588: 10803fcc andi r2,r2,255 + 100f58c: 10800160 cmpeqi r2,r2,5 + 100f590: 1000051e bne r2,zero,100f5a8 + *perr = OS_ERR_EVENT_TYPE; + 100f594: e0fffd17 ldw r3,-12(fp) + 100f598: 00800044 movi r2,1 + 100f59c: 18800005 stb r2,0(r3) + return ((OS_FLAGS)0); + 100f5a0: e03fff15 stw zero,-4(fp) + 100f5a4: 0000a906 br 100f84c + } + result = (INT8U)(wait_type & OS_FLAG_CONSUME); + 100f5a8: e0fffc03 ldbu r3,-16(fp) + 100f5ac: 00bfe004 movi r2,-128 + 100f5b0: 1884703a and r2,r3,r2 + 100f5b4: e0bff945 stb r2,-27(fp) + if (result != (INT8U)0) { /* See if we need to consume the flags */ + 100f5b8: e0bff943 ldbu r2,-27(fp) + 100f5bc: 1005003a cmpeq r2,r2,zero + 100f5c0: 1000061e bne r2,zero,100f5dc + wait_type &= ~OS_FLAG_CONSUME; + 100f5c4: e0bffc03 ldbu r2,-16(fp) + 100f5c8: 10801fcc andi r2,r2,127 + 100f5cc: e0bffc05 stb r2,-16(fp) + consume = OS_TRUE; + 100f5d0: 00800044 movi r2,1 + 100f5d4: e0bff905 stb r2,-28(fp) + 100f5d8: 00000106 br 100f5e0 + } else { + consume = OS_FALSE; + 100f5dc: e03ff905 stb zero,-28(fp) + } +/*$PAGE*/ + *perr = OS_ERR_NONE; /* Assume NO error until proven otherwise. */ + 100f5e0: e0bffd17 ldw r2,-12(fp) + 100f5e4: 10000005 stb zero,0(r2) +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 100f5e8: 0005303a rdctl r2,status + 100f5ec: e0bff715 stw r2,-36(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 100f5f0: e0fff717 ldw r3,-36(fp) + 100f5f4: 00bfff84 movi r2,-2 + 100f5f8: 1884703a and r2,r3,r2 + 100f5fc: 1001703a wrctl status,r2 + + return context; + 100f600: e0bff717 ldw r2,-36(fp) + OS_ENTER_CRITICAL(); + 100f604: e0bff815 stw r2,-32(fp) + switch (wait_type) { + 100f608: e0bffc03 ldbu r2,-16(fp) + 100f60c: e0bffe15 stw r2,-8(fp) + 100f610: e0fffe17 ldw r3,-8(fp) + 100f614: 18800060 cmpeqi r2,r3,1 + 100f618: 1000651e bne r2,zero,100f7b0 + 100f61c: e0fffe17 ldw r3,-8(fp) + 100f620: 18800088 cmpgei r2,r3,2 + 100f624: 1000041e bne r2,zero,100f638 + 100f628: e0fffe17 ldw r3,-8(fp) + 100f62c: 1805003a cmpeq r2,r3,zero + 100f630: 1000421e bne r2,zero,100f73c + 100f634: 00007b06 br 100f824 + 100f638: e0fffe17 ldw r3,-8(fp) + 100f63c: 188000a0 cmpeqi r2,r3,2 + 100f640: 1000041e bne r2,zero,100f654 + 100f644: e0fffe17 ldw r3,-8(fp) + 100f648: 188000e0 cmpeqi r2,r3,3 + 100f64c: 10001e1e bne r2,zero,100f6c8 + 100f650: 00007406 br 100f824 + case OS_FLAG_WAIT_SET_ALL: /* See if all required flags are set */ + flags_rdy = (OS_FLAGS)(pgrp->OSFlagFlags & flags); /* Extract only the bits we want */ + 100f654: e0bffa17 ldw r2,-24(fp) + 100f658: 10c0020b ldhu r3,8(r2) + 100f65c: e0bffb0b ldhu r2,-20(fp) + 100f660: 1884703a and r2,r3,r2 + 100f664: e0bff98d sth r2,-26(fp) + if (flags_rdy == flags) { /* Must match ALL the bits that we want */ + 100f668: e0fff98b ldhu r3,-26(fp) + 100f66c: e0bffb0b ldhu r2,-20(fp) + 100f670: 18800d1e bne r3,r2,100f6a8 + if (consume == OS_TRUE) { /* See if we need to consume the flags */ + 100f674: e0bff903 ldbu r2,-28(fp) + 100f678: 10800058 cmpnei r2,r2,1 + 100f67c: 10000d1e bne r2,zero,100f6b4 + pgrp->OSFlagFlags &= ~flags_rdy; /* Clear ONLY the flags that we wanted */ + 100f680: e0bffa17 ldw r2,-24(fp) + 100f684: 1080020b ldhu r2,8(r2) + 100f688: 1007883a mov r3,r2 + 100f68c: e0bff98b ldhu r2,-26(fp) + 100f690: 0084303a nor r2,zero,r2 + 100f694: 1884703a and r2,r3,r2 + 100f698: 1007883a mov r3,r2 + 100f69c: e0bffa17 ldw r2,-24(fp) + 100f6a0: 10c0020d sth r3,8(r2) + 100f6a4: 00000306 br 100f6b4 + } + } else { + *perr = OS_ERR_FLAG_NOT_RDY; + 100f6a8: e0fffd17 ldw r3,-12(fp) + 100f6ac: 00801c04 movi r2,112 + 100f6b0: 18800005 stb r2,0(r3) + 100f6b4: e0bff817 ldw r2,-32(fp) + 100f6b8: e0bff615 stw r2,-40(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 100f6bc: e0bff617 ldw r2,-40(fp) + 100f6c0: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); + break; + 100f6c4: 00005f06 br 100f844 + + case OS_FLAG_WAIT_SET_ANY: + flags_rdy = (OS_FLAGS)(pgrp->OSFlagFlags & flags); /* Extract only the bits we want */ + 100f6c8: e0bffa17 ldw r2,-24(fp) + 100f6cc: 10c0020b ldhu r3,8(r2) + 100f6d0: e0bffb0b ldhu r2,-20(fp) + 100f6d4: 1884703a and r2,r3,r2 + 100f6d8: e0bff98d sth r2,-26(fp) + if (flags_rdy != (OS_FLAGS)0) { /* See if any flag set */ + 100f6dc: e0bff98b ldhu r2,-26(fp) + 100f6e0: 1005003a cmpeq r2,r2,zero + 100f6e4: 10000d1e bne r2,zero,100f71c + if (consume == OS_TRUE) { /* See if we need to consume the flags */ + 100f6e8: e0bff903 ldbu r2,-28(fp) + 100f6ec: 10800058 cmpnei r2,r2,1 + 100f6f0: 10000d1e bne r2,zero,100f728 + pgrp->OSFlagFlags &= ~flags_rdy; /* Clear ONLY the flags that we got */ + 100f6f4: e0bffa17 ldw r2,-24(fp) + 100f6f8: 1080020b ldhu r2,8(r2) + 100f6fc: 1007883a mov r3,r2 + 100f700: e0bff98b ldhu r2,-26(fp) + 100f704: 0084303a nor r2,zero,r2 + 100f708: 1884703a and r2,r3,r2 + 100f70c: 1007883a mov r3,r2 + 100f710: e0bffa17 ldw r2,-24(fp) + 100f714: 10c0020d sth r3,8(r2) + 100f718: 00000306 br 100f728 + } + } else { + *perr = OS_ERR_FLAG_NOT_RDY; + 100f71c: e0fffd17 ldw r3,-12(fp) + 100f720: 00801c04 movi r2,112 + 100f724: 18800005 stb r2,0(r3) + 100f728: e0bff817 ldw r2,-32(fp) + 100f72c: e0bff515 stw r2,-44(fp) + 100f730: e0bff517 ldw r2,-44(fp) + 100f734: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); + break; + 100f738: 00004206 br 100f844 + +#if OS_FLAG_WAIT_CLR_EN > 0 + case OS_FLAG_WAIT_CLR_ALL: /* See if all required flags are cleared */ + flags_rdy = (OS_FLAGS)(~pgrp->OSFlagFlags & flags); /* Extract only the bits we want */ + 100f73c: e0bffa17 ldw r2,-24(fp) + 100f740: 1080020b ldhu r2,8(r2) + 100f744: 0084303a nor r2,zero,r2 + 100f748: 1007883a mov r3,r2 + 100f74c: e0bffb0b ldhu r2,-20(fp) + 100f750: 1884703a and r2,r3,r2 + 100f754: e0bff98d sth r2,-26(fp) + if (flags_rdy == flags) { /* Must match ALL the bits that we want */ + 100f758: e0fff98b ldhu r3,-26(fp) + 100f75c: e0bffb0b ldhu r2,-20(fp) + 100f760: 18800b1e bne r3,r2,100f790 + if (consume == OS_TRUE) { /* See if we need to consume the flags */ + 100f764: e0bff903 ldbu r2,-28(fp) + 100f768: 10800058 cmpnei r2,r2,1 + 100f76c: 10000b1e bne r2,zero,100f79c + pgrp->OSFlagFlags |= flags_rdy; /* Set ONLY the flags that we wanted */ + 100f770: e0bffa17 ldw r2,-24(fp) + 100f774: 10c0020b ldhu r3,8(r2) + 100f778: e0bff98b ldhu r2,-26(fp) + 100f77c: 1884b03a or r2,r3,r2 + 100f780: 1007883a mov r3,r2 + 100f784: e0bffa17 ldw r2,-24(fp) + 100f788: 10c0020d sth r3,8(r2) + 100f78c: 00000306 br 100f79c + } + } else { + *perr = OS_ERR_FLAG_NOT_RDY; + 100f790: e0fffd17 ldw r3,-12(fp) + 100f794: 00801c04 movi r2,112 + 100f798: 18800005 stb r2,0(r3) + 100f79c: e0bff817 ldw r2,-32(fp) + 100f7a0: e0bff415 stw r2,-48(fp) + 100f7a4: e0bff417 ldw r2,-48(fp) + 100f7a8: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); + break; + 100f7ac: 00002506 br 100f844 + + case OS_FLAG_WAIT_CLR_ANY: + flags_rdy = (OS_FLAGS)(~pgrp->OSFlagFlags & flags); /* Extract only the bits we want */ + 100f7b0: e0bffa17 ldw r2,-24(fp) + 100f7b4: 1080020b ldhu r2,8(r2) + 100f7b8: 0084303a nor r2,zero,r2 + 100f7bc: 1007883a mov r3,r2 + 100f7c0: e0bffb0b ldhu r2,-20(fp) + 100f7c4: 1884703a and r2,r3,r2 + 100f7c8: e0bff98d sth r2,-26(fp) + if (flags_rdy != (OS_FLAGS)0) { /* See if any flag cleared */ + 100f7cc: e0bff98b ldhu r2,-26(fp) + 100f7d0: 1005003a cmpeq r2,r2,zero + 100f7d4: 10000b1e bne r2,zero,100f804 + if (consume == OS_TRUE) { /* See if we need to consume the flags */ + 100f7d8: e0bff903 ldbu r2,-28(fp) + 100f7dc: 10800058 cmpnei r2,r2,1 + 100f7e0: 10000b1e bne r2,zero,100f810 + pgrp->OSFlagFlags |= flags_rdy; /* Set ONLY the flags that we got */ + 100f7e4: e0bffa17 ldw r2,-24(fp) + 100f7e8: 10c0020b ldhu r3,8(r2) + 100f7ec: e0bff98b ldhu r2,-26(fp) + 100f7f0: 1884b03a or r2,r3,r2 + 100f7f4: 1007883a mov r3,r2 + 100f7f8: e0bffa17 ldw r2,-24(fp) + 100f7fc: 10c0020d sth r3,8(r2) + 100f800: 00000306 br 100f810 + } + } else { + *perr = OS_ERR_FLAG_NOT_RDY; + 100f804: e0fffd17 ldw r3,-12(fp) + 100f808: 00801c04 movi r2,112 + 100f80c: 18800005 stb r2,0(r3) + 100f810: e0bff817 ldw r2,-32(fp) + 100f814: e0bff315 stw r2,-52(fp) + 100f818: e0bff317 ldw r2,-52(fp) + 100f81c: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); + break; + 100f820: 00000806 br 100f844 + 100f824: e0bff817 ldw r2,-32(fp) + 100f828: e0bff215 stw r2,-56(fp) + 100f82c: e0bff217 ldw r2,-56(fp) + 100f830: 1001703a wrctl status,r2 +#endif + + default: + OS_EXIT_CRITICAL(); + flags_rdy = (OS_FLAGS)0; + 100f834: e03ff98d sth zero,-26(fp) + *perr = OS_ERR_FLAG_WAIT_TYPE; + 100f838: e0fffd17 ldw r3,-12(fp) + 100f83c: 00801bc4 movi r2,111 + 100f840: 18800005 stb r2,0(r3) + break; + } + return (flags_rdy); + 100f844: e0bff98b ldhu r2,-26(fp) + 100f848: e0bfff15 stw r2,-4(fp) + 100f84c: e0bfff17 ldw r2,-4(fp) +} + 100f850: e037883a mov sp,fp + 100f854: df000017 ldw fp,0(sp) + 100f858: dec00104 addi sp,sp,4 + 100f85c: f800283a ret + +0100f860 : +* Called from: Task ONLY +********************************************************************************************************* +*/ + +OS_FLAG_GRP *OSFlagCreate (OS_FLAGS flags, INT8U *perr) +{ + 100f860: defff704 addi sp,sp,-36 + 100f864: df000815 stw fp,32(sp) + 100f868: df000804 addi fp,sp,32 + 100f86c: e17ffe15 stw r5,-8(fp) + 100f870: e13ffd0d sth r4,-12(fp) + OS_FLAG_GRP *pgrp; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 100f874: e03ffb15 stw zero,-20(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + 100f878: e0bffe17 ldw r2,-8(fp) + 100f87c: 1004c03a cmpne r2,r2,zero + 100f880: 1000021e bne r2,zero,100f88c + return ((OS_FLAG_GRP *)0); + 100f884: e03fff15 stw zero,-4(fp) + 100f888: 00003f06 br 100f988 + } +#endif + if (OSIntNesting > 0) { /* See if called from ISR ... */ + 100f88c: 008040b4 movhi r2,258 + 100f890: 10b31e04 addi r2,r2,-13192 + 100f894: 10800003 ldbu r2,0(r2) + 100f898: 10803fcc andi r2,r2,255 + 100f89c: 1005003a cmpeq r2,r2,zero + 100f8a0: 1000051e bne r2,zero,100f8b8 + *perr = OS_ERR_CREATE_ISR; /* ... can't CREATE from an ISR */ + 100f8a4: e0fffe17 ldw r3,-8(fp) + 100f8a8: 00800404 movi r2,16 + 100f8ac: 18800005 stb r2,0(r3) + return ((OS_FLAG_GRP *)0); + 100f8b0: e03fff15 stw zero,-4(fp) + 100f8b4: 00003406 br 100f988 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 100f8b8: 0005303a rdctl r2,status + 100f8bc: e0bffa15 stw r2,-24(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 100f8c0: e0fffa17 ldw r3,-24(fp) + 100f8c4: 00bfff84 movi r2,-2 + 100f8c8: 1884703a and r2,r3,r2 + 100f8cc: 1001703a wrctl status,r2 + + return context; + 100f8d0: e0bffa17 ldw r2,-24(fp) + } + OS_ENTER_CRITICAL(); + 100f8d4: e0bffb15 stw r2,-20(fp) + pgrp = OSFlagFreeList; /* Get next free event flag */ + 100f8d8: 008040b4 movhi r2,258 + 100f8dc: 10b32104 addi r2,r2,-13180 + 100f8e0: 10800017 ldw r2,0(r2) + 100f8e4: e0bffc15 stw r2,-16(fp) + if (pgrp != (OS_FLAG_GRP *)0) { /* See if we have event flag groups available */ + 100f8e8: e0bffc17 ldw r2,-16(fp) + 100f8ec: 1005003a cmpeq r2,r2,zero + 100f8f0: 10001c1e bne r2,zero,100f964 + /* Adjust free list */ + OSFlagFreeList = (OS_FLAG_GRP *)OSFlagFreeList->OSFlagWaitList; + 100f8f4: 008040b4 movhi r2,258 + 100f8f8: 10b32104 addi r2,r2,-13180 + 100f8fc: 10800017 ldw r2,0(r2) + 100f900: 10800117 ldw r2,4(r2) + 100f904: 1007883a mov r3,r2 + 100f908: 008040b4 movhi r2,258 + 100f90c: 10b32104 addi r2,r2,-13180 + 100f910: 10c00015 stw r3,0(r2) + pgrp->OSFlagType = OS_EVENT_TYPE_FLAG; /* Set to event flag group type */ + 100f914: e0fffc17 ldw r3,-16(fp) + 100f918: 00800144 movi r2,5 + 100f91c: 18800005 stb r2,0(r3) + pgrp->OSFlagFlags = flags; /* Set to desired initial value */ + 100f920: e0fffc17 ldw r3,-16(fp) + 100f924: e0bffd0b ldhu r2,-12(fp) + 100f928: 1880020d sth r2,8(r3) + pgrp->OSFlagWaitList = (void *)0; /* Clear list of tasks waiting on flags */ + 100f92c: e0bffc17 ldw r2,-16(fp) + 100f930: 10000115 stw zero,4(r2) +#if OS_FLAG_NAME_SIZE > 1 + pgrp->OSFlagName[0] = '?'; + 100f934: e0fffc17 ldw r3,-16(fp) + 100f938: 00800fc4 movi r2,63 + 100f93c: 18800285 stb r2,10(r3) + pgrp->OSFlagName[1] = OS_ASCII_NUL; + 100f940: e0bffc17 ldw r2,-16(fp) + 100f944: 100002c5 stb zero,11(r2) + 100f948: e0bffb17 ldw r2,-20(fp) + 100f94c: e0bff915 stw r2,-28(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 100f950: e0bff917 ldw r2,-28(fp) + 100f954: 1001703a wrctl status,r2 +#endif + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + 100f958: e0bffe17 ldw r2,-8(fp) + 100f95c: 10000005 stb zero,0(r2) + 100f960: 00000706 br 100f980 + 100f964: e0bffb17 ldw r2,-20(fp) + 100f968: e0bff815 stw r2,-32(fp) + 100f96c: e0bff817 ldw r2,-32(fp) + 100f970: 1001703a wrctl status,r2 + } else { + OS_EXIT_CRITICAL(); + *perr = OS_ERR_FLAG_GRP_DEPLETED; + 100f974: e0fffe17 ldw r3,-8(fp) + 100f978: 00801c84 movi r2,114 + 100f97c: 18800005 stb r2,0(r3) + } + return (pgrp); /* Return pointer to event flag group */ + 100f980: e0bffc17 ldw r2,-16(fp) + 100f984: e0bfff15 stw r2,-4(fp) + 100f988: e0bfff17 ldw r2,-4(fp) +} + 100f98c: e037883a mov sp,fp + 100f990: df000017 ldw fp,0(sp) + 100f994: dec00104 addi sp,sp,4 + 100f998: f800283a ret + +0100f99c : +********************************************************************************************************* +*/ + +#if OS_FLAG_DEL_EN > 0 +OS_FLAG_GRP *OSFlagDel (OS_FLAG_GRP *pgrp, INT8U opt, INT8U *perr) +{ + 100f99c: defff004 addi sp,sp,-64 + 100f9a0: dfc00f15 stw ra,60(sp) + 100f9a4: df000e15 stw fp,56(sp) + 100f9a8: df000e04 addi fp,sp,56 + 100f9ac: e13ffb15 stw r4,-20(fp) + 100f9b0: e1bffd15 stw r6,-12(fp) + 100f9b4: e17ffc05 stb r5,-16(fp) + BOOLEAN tasks_waiting; + OS_FLAG_NODE *pnode; + OS_FLAG_GRP *pgrp_return; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 100f9b8: e03ff715 stw zero,-36(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + 100f9bc: e0bffd17 ldw r2,-12(fp) + 100f9c0: 1004c03a cmpne r2,r2,zero + 100f9c4: 1000031e bne r2,zero,100f9d4 + return (pgrp); + 100f9c8: e0bffb17 ldw r2,-20(fp) + 100f9cc: e0bfff15 stw r2,-4(fp) + 100f9d0: 00009606 br 100fc2c + } + if (pgrp == (OS_FLAG_GRP *)0) { /* Validate 'pgrp' */ + 100f9d4: e0bffb17 ldw r2,-20(fp) + 100f9d8: 1004c03a cmpne r2,r2,zero + 100f9dc: 1000061e bne r2,zero,100f9f8 + *perr = OS_ERR_FLAG_INVALID_PGRP; + 100f9e0: e0fffd17 ldw r3,-12(fp) + 100f9e4: 00801b84 movi r2,110 + 100f9e8: 18800005 stb r2,0(r3) + return (pgrp); + 100f9ec: e0fffb17 ldw r3,-20(fp) + 100f9f0: e0ffff15 stw r3,-4(fp) + 100f9f4: 00008d06 br 100fc2c + } +#endif + if (OSIntNesting > 0) { /* See if called from ISR ... */ + 100f9f8: 008040b4 movhi r2,258 + 100f9fc: 10b31e04 addi r2,r2,-13192 + 100fa00: 10800003 ldbu r2,0(r2) + 100fa04: 10803fcc andi r2,r2,255 + 100fa08: 1005003a cmpeq r2,r2,zero + 100fa0c: 1000061e bne r2,zero,100fa28 + *perr = OS_ERR_DEL_ISR; /* ... can't DELETE from an ISR */ + 100fa10: e0fffd17 ldw r3,-12(fp) + 100fa14: 008003c4 movi r2,15 + 100fa18: 18800005 stb r2,0(r3) + return (pgrp); + 100fa1c: e0bffb17 ldw r2,-20(fp) + 100fa20: e0bfff15 stw r2,-4(fp) + 100fa24: 00008106 br 100fc2c + } + if (pgrp->OSFlagType != OS_EVENT_TYPE_FLAG) { /* Validate event group type */ + 100fa28: e0bffb17 ldw r2,-20(fp) + 100fa2c: 10800003 ldbu r2,0(r2) + 100fa30: 10803fcc andi r2,r2,255 + 100fa34: 10800160 cmpeqi r2,r2,5 + 100fa38: 1000061e bne r2,zero,100fa54 + *perr = OS_ERR_EVENT_TYPE; + 100fa3c: e0fffd17 ldw r3,-12(fp) + 100fa40: 00800044 movi r2,1 + 100fa44: 18800005 stb r2,0(r3) + return (pgrp); + 100fa48: e0fffb17 ldw r3,-20(fp) + 100fa4c: e0ffff15 stw r3,-4(fp) + 100fa50: 00007606 br 100fc2c +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 100fa54: 0005303a rdctl r2,status + 100fa58: e0bff615 stw r2,-40(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 100fa5c: e0fff617 ldw r3,-40(fp) + 100fa60: 00bfff84 movi r2,-2 + 100fa64: 1884703a and r2,r3,r2 + 100fa68: 1001703a wrctl status,r2 + + return context; + 100fa6c: e0bff617 ldw r2,-40(fp) + } + OS_ENTER_CRITICAL(); + 100fa70: e0bff715 stw r2,-36(fp) + if (pgrp->OSFlagWaitList != (void *)0) { /* See if any tasks waiting on event flags */ + 100fa74: e0bffb17 ldw r2,-20(fp) + 100fa78: 10800117 ldw r2,4(r2) + 100fa7c: 1005003a cmpeq r2,r2,zero + 100fa80: 1000031e bne r2,zero,100fa90 + tasks_waiting = OS_TRUE; /* Yes */ + 100fa84: 00800044 movi r2,1 + 100fa88: e0bffa05 stb r2,-24(fp) + 100fa8c: 00000106 br 100fa94 + } else { + tasks_waiting = OS_FALSE; /* No */ + 100fa90: e03ffa05 stb zero,-24(fp) + } + switch (opt) { + 100fa94: e0bffc03 ldbu r2,-16(fp) + 100fa98: e0bffe15 stw r2,-8(fp) + 100fa9c: e0fffe17 ldw r3,-8(fp) + 100faa0: 1805003a cmpeq r2,r3,zero + 100faa4: 1000041e bne r2,zero,100fab8 + 100faa8: e0fffe17 ldw r3,-8(fp) + 100faac: 18800060 cmpeqi r2,r3,1 + 100fab0: 1000281e bne r2,zero,100fb54 + 100fab4: 00005206 br 100fc00 + case OS_DEL_NO_PEND: /* Delete group if no task waiting */ + if (tasks_waiting == OS_FALSE) { + 100fab8: e0bffa03 ldbu r2,-24(fp) + 100fabc: 1004c03a cmpne r2,r2,zero + 100fac0: 10001a1e bne r2,zero,100fb2c +#if OS_FLAG_NAME_SIZE > 1 + pgrp->OSFlagName[0] = '?'; /* Unknown name */ + 100fac4: e0fffb17 ldw r3,-20(fp) + 100fac8: 00800fc4 movi r2,63 + 100facc: 18800285 stb r2,10(r3) + pgrp->OSFlagName[1] = OS_ASCII_NUL; + 100fad0: e0bffb17 ldw r2,-20(fp) + 100fad4: 100002c5 stb zero,11(r2) +#endif + pgrp->OSFlagType = OS_EVENT_TYPE_UNUSED; + 100fad8: e0bffb17 ldw r2,-20(fp) + 100fadc: 10000005 stb zero,0(r2) + pgrp->OSFlagWaitList = (void *)OSFlagFreeList; /* Return group to free list */ + 100fae0: 008040b4 movhi r2,258 + 100fae4: 10b32104 addi r2,r2,-13180 + 100fae8: 10c00017 ldw r3,0(r2) + 100faec: e0bffb17 ldw r2,-20(fp) + 100faf0: 10c00115 stw r3,4(r2) + pgrp->OSFlagFlags = (OS_FLAGS)0; + 100faf4: e0bffb17 ldw r2,-20(fp) + 100faf8: 1000020d sth zero,8(r2) + OSFlagFreeList = pgrp; + 100fafc: 00c040b4 movhi r3,258 + 100fb00: 18f32104 addi r3,r3,-13180 + 100fb04: e0bffb17 ldw r2,-20(fp) + 100fb08: 18800015 stw r2,0(r3) + 100fb0c: e0bff717 ldw r2,-36(fp) + 100fb10: e0bff515 stw r2,-44(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 100fb14: e0bff517 ldw r2,-44(fp) + 100fb18: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + 100fb1c: e0bffd17 ldw r2,-12(fp) + 100fb20: 10000005 stb zero,0(r2) + pgrp_return = (OS_FLAG_GRP *)0; /* Event Flag Group has been deleted */ + 100fb24: e03ff815 stw zero,-32(fp) + 100fb28: 00003e06 br 100fc24 + 100fb2c: e0bff717 ldw r2,-36(fp) + 100fb30: e0bff415 stw r2,-48(fp) + 100fb34: e0bff417 ldw r2,-48(fp) + 100fb38: 1001703a wrctl status,r2 + } else { + OS_EXIT_CRITICAL(); + *perr = OS_ERR_TASK_WAITING; + 100fb3c: e0fffd17 ldw r3,-12(fp) + 100fb40: 00801244 movi r2,73 + 100fb44: 18800005 stb r2,0(r3) + pgrp_return = pgrp; + 100fb48: e0bffb17 ldw r2,-20(fp) + 100fb4c: e0bff815 stw r2,-32(fp) + } + break; + 100fb50: 00003406 br 100fc24 + + case OS_DEL_ALWAYS: /* Always delete the event flag group */ + pnode = (OS_FLAG_NODE *)pgrp->OSFlagWaitList; + 100fb54: e0bffb17 ldw r2,-20(fp) + 100fb58: 10800117 ldw r2,4(r2) + 100fb5c: e0bff915 stw r2,-28(fp) + while (pnode != (OS_FLAG_NODE *)0) { /* Ready ALL tasks waiting for flags */ + 100fb60: 00000606 br 100fb7c + (void)OS_FlagTaskRdy(pnode, (OS_FLAGS)0); + 100fb64: e13ff917 ldw r4,-28(fp) + 100fb68: 000b883a mov r5,zero + 100fb6c: 1010cac0 call 1010cac + pnode = (OS_FLAG_NODE *)pnode->OSFlagNodeNext; + 100fb70: e0bff917 ldw r2,-28(fp) + 100fb74: 10800017 ldw r2,0(r2) + 100fb78: e0bff915 stw r2,-28(fp) + } + break; + + case OS_DEL_ALWAYS: /* Always delete the event flag group */ + pnode = (OS_FLAG_NODE *)pgrp->OSFlagWaitList; + while (pnode != (OS_FLAG_NODE *)0) { /* Ready ALL tasks waiting for flags */ + 100fb7c: e0bff917 ldw r2,-28(fp) + 100fb80: 1004c03a cmpne r2,r2,zero + 100fb84: 103ff71e bne r2,zero,100fb64 + (void)OS_FlagTaskRdy(pnode, (OS_FLAGS)0); + pnode = (OS_FLAG_NODE *)pnode->OSFlagNodeNext; + } +#if OS_FLAG_NAME_SIZE > 1 + pgrp->OSFlagName[0] = '?'; /* Unknown name */ + 100fb88: e0fffb17 ldw r3,-20(fp) + 100fb8c: 00800fc4 movi r2,63 + 100fb90: 18800285 stb r2,10(r3) + pgrp->OSFlagName[1] = OS_ASCII_NUL; + 100fb94: e0bffb17 ldw r2,-20(fp) + 100fb98: 100002c5 stb zero,11(r2) +#endif + pgrp->OSFlagType = OS_EVENT_TYPE_UNUSED; + 100fb9c: e0bffb17 ldw r2,-20(fp) + 100fba0: 10000005 stb zero,0(r2) + pgrp->OSFlagWaitList = (void *)OSFlagFreeList;/* Return group to free list */ + 100fba4: 008040b4 movhi r2,258 + 100fba8: 10b32104 addi r2,r2,-13180 + 100fbac: 10c00017 ldw r3,0(r2) + 100fbb0: e0bffb17 ldw r2,-20(fp) + 100fbb4: 10c00115 stw r3,4(r2) + pgrp->OSFlagFlags = (OS_FLAGS)0; + 100fbb8: e0bffb17 ldw r2,-20(fp) + 100fbbc: 1000020d sth zero,8(r2) + OSFlagFreeList = pgrp; + 100fbc0: 00c040b4 movhi r3,258 + 100fbc4: 18f32104 addi r3,r3,-13180 + 100fbc8: e0bffb17 ldw r2,-20(fp) + 100fbcc: 18800015 stw r2,0(r3) + 100fbd0: e0bff717 ldw r2,-36(fp) + 100fbd4: e0bff315 stw r2,-52(fp) + 100fbd8: e0bff317 ldw r2,-52(fp) + 100fbdc: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + if (tasks_waiting == OS_TRUE) { /* Reschedule only if task(s) were waiting */ + 100fbe0: e0bffa03 ldbu r2,-24(fp) + 100fbe4: 10800058 cmpnei r2,r2,1 + 100fbe8: 1000011e bne r2,zero,100fbf0 + OS_Sched(); /* Find highest priority task ready to run */ + 100fbec: 100ecb80 call 100ecb8 + } + *perr = OS_ERR_NONE; + 100fbf0: e0bffd17 ldw r2,-12(fp) + 100fbf4: 10000005 stb zero,0(r2) + pgrp_return = (OS_FLAG_GRP *)0; /* Event Flag Group has been deleted */ + 100fbf8: e03ff815 stw zero,-32(fp) + break; + 100fbfc: 00000906 br 100fc24 + 100fc00: e0bff717 ldw r2,-36(fp) + 100fc04: e0bff215 stw r2,-56(fp) + 100fc08: e0bff217 ldw r2,-56(fp) + 100fc0c: 1001703a wrctl status,r2 + + default: + OS_EXIT_CRITICAL(); + *perr = OS_ERR_INVALID_OPT; + 100fc10: e0fffd17 ldw r3,-12(fp) + 100fc14: 008001c4 movi r2,7 + 100fc18: 18800005 stb r2,0(r3) + pgrp_return = pgrp; + 100fc1c: e0bffb17 ldw r2,-20(fp) + 100fc20: e0bff815 stw r2,-32(fp) + break; + } + return (pgrp_return); + 100fc24: e0bff817 ldw r2,-32(fp) + 100fc28: e0bfff15 stw r2,-4(fp) + 100fc2c: e0bfff17 ldw r2,-4(fp) +} + 100fc30: e037883a mov sp,fp + 100fc34: dfc00117 ldw ra,4(sp) + 100fc38: df000017 ldw fp,0(sp) + 100fc3c: dec00204 addi sp,sp,8 + 100fc40: f800283a ret + +0100fc44 : +********************************************************************************************************* +*/ + +#if OS_FLAG_NAME_SIZE > 1 +INT8U OSFlagNameGet (OS_FLAG_GRP *pgrp, INT8U *pname, INT8U *perr) +{ + 100fc44: defff504 addi sp,sp,-44 + 100fc48: dfc00a15 stw ra,40(sp) + 100fc4c: df000915 stw fp,36(sp) + 100fc50: df000904 addi fp,sp,36 + 100fc54: e13ffc15 stw r4,-16(fp) + 100fc58: e17ffd15 stw r5,-12(fp) + 100fc5c: e1bffe15 stw r6,-8(fp) + INT8U len; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 100fc60: e03ffa15 stw zero,-24(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + 100fc64: e0bffe17 ldw r2,-8(fp) + 100fc68: 1004c03a cmpne r2,r2,zero + 100fc6c: 1000021e bne r2,zero,100fc78 + return (0); + 100fc70: e03fff15 stw zero,-4(fp) + 100fc74: 00003e06 br 100fd70 + } + if (pgrp == (OS_FLAG_GRP *)0) { /* Is 'pgrp' a NULL pointer? */ + 100fc78: e0bffc17 ldw r2,-16(fp) + 100fc7c: 1004c03a cmpne r2,r2,zero + 100fc80: 1000051e bne r2,zero,100fc98 + *perr = OS_ERR_FLAG_INVALID_PGRP; + 100fc84: e0fffe17 ldw r3,-8(fp) + 100fc88: 00801b84 movi r2,110 + 100fc8c: 18800005 stb r2,0(r3) + return (0); + 100fc90: e03fff15 stw zero,-4(fp) + 100fc94: 00003606 br 100fd70 + } + if (pname == (INT8U *)0) { /* Is 'pname' a NULL pointer? */ + 100fc98: e0bffd17 ldw r2,-12(fp) + 100fc9c: 1004c03a cmpne r2,r2,zero + 100fca0: 1000051e bne r2,zero,100fcb8 + *perr = OS_ERR_PNAME_NULL; + 100fca4: e0fffe17 ldw r3,-8(fp) + 100fca8: 00800304 movi r2,12 + 100fcac: 18800005 stb r2,0(r3) + return (0); + 100fcb0: e03fff15 stw zero,-4(fp) + 100fcb4: 00002e06 br 100fd70 + } +#endif + if (OSIntNesting > 0) { /* See if trying to call from an ISR */ + 100fcb8: 008040b4 movhi r2,258 + 100fcbc: 10b31e04 addi r2,r2,-13192 + 100fcc0: 10800003 ldbu r2,0(r2) + 100fcc4: 10803fcc andi r2,r2,255 + 100fcc8: 1005003a cmpeq r2,r2,zero + 100fccc: 1000051e bne r2,zero,100fce4 + *perr = OS_ERR_NAME_GET_ISR; + 100fcd0: e0fffe17 ldw r3,-8(fp) + 100fcd4: 00800444 movi r2,17 + 100fcd8: 18800005 stb r2,0(r3) + return (0); + 100fcdc: e03fff15 stw zero,-4(fp) + 100fce0: 00002306 br 100fd70 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 100fce4: 0005303a rdctl r2,status + 100fce8: e0bff915 stw r2,-28(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 100fcec: e0fff917 ldw r3,-28(fp) + 100fcf0: 00bfff84 movi r2,-2 + 100fcf4: 1884703a and r2,r3,r2 + 100fcf8: 1001703a wrctl status,r2 + + return context; + 100fcfc: e0bff917 ldw r2,-28(fp) + } + OS_ENTER_CRITICAL(); + 100fd00: e0bffa15 stw r2,-24(fp) + if (pgrp->OSFlagType != OS_EVENT_TYPE_FLAG) { + 100fd04: e0bffc17 ldw r2,-16(fp) + 100fd08: 10800003 ldbu r2,0(r2) + 100fd0c: 10803fcc andi r2,r2,255 + 100fd10: 10800160 cmpeqi r2,r2,5 + 100fd14: 1000091e bne r2,zero,100fd3c + 100fd18: e0bffa17 ldw r2,-24(fp) + 100fd1c: e0bff815 stw r2,-32(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 100fd20: e0bff817 ldw r2,-32(fp) + 100fd24: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + *perr = OS_ERR_EVENT_TYPE; + 100fd28: e0fffe17 ldw r3,-8(fp) + 100fd2c: 00800044 movi r2,1 + 100fd30: 18800005 stb r2,0(r3) + return (0); + 100fd34: e03fff15 stw zero,-4(fp) + 100fd38: 00000d06 br 100fd70 + } + len = OS_StrCopy(pname, pgrp->OSFlagName); /* Copy name from OS_FLAG_GRP */ + 100fd3c: e0bffc17 ldw r2,-16(fp) + 100fd40: 11400284 addi r5,r2,10 + 100fd44: e13ffd17 ldw r4,-12(fp) + 100fd48: 100edfc0 call 100edfc + 100fd4c: e0bffb05 stb r2,-20(fp) + 100fd50: e0bffa17 ldw r2,-24(fp) + 100fd54: e0bff715 stw r2,-36(fp) + 100fd58: e0bff717 ldw r2,-36(fp) + 100fd5c: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + 100fd60: e0bffe17 ldw r2,-8(fp) + 100fd64: 10000005 stb zero,0(r2) + return (len); + 100fd68: e0bffb03 ldbu r2,-20(fp) + 100fd6c: e0bfff15 stw r2,-4(fp) + 100fd70: e0bfff17 ldw r2,-4(fp) +} + 100fd74: e037883a mov sp,fp + 100fd78: dfc00117 ldw ra,4(sp) + 100fd7c: df000017 ldw fp,0(sp) + 100fd80: dec00204 addi sp,sp,8 + 100fd84: f800283a ret + +0100fd88 : +********************************************************************************************************* +*/ + +#if OS_FLAG_NAME_SIZE > 1 +void OSFlagNameSet (OS_FLAG_GRP *pgrp, INT8U *pname, INT8U *perr) +{ + 100fd88: defff504 addi sp,sp,-44 + 100fd8c: dfc00a15 stw ra,40(sp) + 100fd90: df000915 stw fp,36(sp) + 100fd94: df000904 addi fp,sp,36 + 100fd98: e13ffd15 stw r4,-12(fp) + 100fd9c: e17ffe15 stw r5,-8(fp) + 100fda0: e1bfff15 stw r6,-4(fp) + INT8U len; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 100fda4: e03ffb15 stw zero,-20(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + 100fda8: e0bfff17 ldw r2,-4(fp) + 100fdac: 1005003a cmpeq r2,r2,zero + 100fdb0: 1000451e bne r2,zero,100fec8 + return; + } + if (pgrp == (OS_FLAG_GRP *)0) { /* Is 'pgrp' a NULL pointer? */ + 100fdb4: e0bffd17 ldw r2,-12(fp) + 100fdb8: 1004c03a cmpne r2,r2,zero + 100fdbc: 1000041e bne r2,zero,100fdd0 + *perr = OS_ERR_FLAG_INVALID_PGRP; + 100fdc0: e0ffff17 ldw r3,-4(fp) + 100fdc4: 00801b84 movi r2,110 + 100fdc8: 18800005 stb r2,0(r3) + return; + 100fdcc: 00003e06 br 100fec8 + } + if (pname == (INT8U *)0) { /* Is 'pname' a NULL pointer? */ + 100fdd0: e0bffe17 ldw r2,-8(fp) + 100fdd4: 1004c03a cmpne r2,r2,zero + 100fdd8: 1000041e bne r2,zero,100fdec + *perr = OS_ERR_PNAME_NULL; + 100fddc: e0ffff17 ldw r3,-4(fp) + 100fde0: 00800304 movi r2,12 + 100fde4: 18800005 stb r2,0(r3) + return; + 100fde8: 00003706 br 100fec8 + } +#endif + if (OSIntNesting > 0) { /* See if trying to call from an ISR */ + 100fdec: 008040b4 movhi r2,258 + 100fdf0: 10b31e04 addi r2,r2,-13192 + 100fdf4: 10800003 ldbu r2,0(r2) + 100fdf8: 10803fcc andi r2,r2,255 + 100fdfc: 1005003a cmpeq r2,r2,zero + 100fe00: 1000041e bne r2,zero,100fe14 + *perr = OS_ERR_NAME_SET_ISR; + 100fe04: e0ffff17 ldw r3,-4(fp) + 100fe08: 00800484 movi r2,18 + 100fe0c: 18800005 stb r2,0(r3) + return; + 100fe10: 00002d06 br 100fec8 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 100fe14: 0005303a rdctl r2,status + 100fe18: e0bffa15 stw r2,-24(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 100fe1c: e0fffa17 ldw r3,-24(fp) + 100fe20: 00bfff84 movi r2,-2 + 100fe24: 1884703a and r2,r3,r2 + 100fe28: 1001703a wrctl status,r2 + + return context; + 100fe2c: e0bffa17 ldw r2,-24(fp) + } + OS_ENTER_CRITICAL(); + 100fe30: e0bffb15 stw r2,-20(fp) + if (pgrp->OSFlagType != OS_EVENT_TYPE_FLAG) { + 100fe34: e0bffd17 ldw r2,-12(fp) + 100fe38: 10800003 ldbu r2,0(r2) + 100fe3c: 10803fcc andi r2,r2,255 + 100fe40: 10800160 cmpeqi r2,r2,5 + 100fe44: 1000081e bne r2,zero,100fe68 + 100fe48: e0bffb17 ldw r2,-20(fp) + 100fe4c: e0bff915 stw r2,-28(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 100fe50: e0bff917 ldw r2,-28(fp) + 100fe54: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + *perr = OS_ERR_EVENT_TYPE; + 100fe58: e0ffff17 ldw r3,-4(fp) + 100fe5c: 00800044 movi r2,1 + 100fe60: 18800005 stb r2,0(r3) + return; + 100fe64: 00001806 br 100fec8 + } + len = OS_StrLen(pname); /* Can we fit the string in the storage area? */ + 100fe68: e13ffe17 ldw r4,-8(fp) + 100fe6c: 100ee7c0 call 100ee7c + 100fe70: e0bffc05 stb r2,-16(fp) + if (len > (OS_FLAG_NAME_SIZE - 1)) { /* No */ + 100fe74: e0bffc03 ldbu r2,-16(fp) + 100fe78: 10800830 cmpltui r2,r2,32 + 100fe7c: 1000081e bne r2,zero,100fea0 + 100fe80: e0bffb17 ldw r2,-20(fp) + 100fe84: e0bff815 stw r2,-32(fp) + 100fe88: e0bff817 ldw r2,-32(fp) + 100fe8c: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + *perr = OS_ERR_FLAG_NAME_TOO_LONG; + 100fe90: e0ffff17 ldw r3,-4(fp) + 100fe94: 00801cc4 movi r2,115 + 100fe98: 18800005 stb r2,0(r3) + return; + 100fe9c: 00000a06 br 100fec8 + } + (void)OS_StrCopy(pgrp->OSFlagName, pname); /* Yes, copy name from OS_FLAG_GRP */ + 100fea0: e0bffd17 ldw r2,-12(fp) + 100fea4: 11000284 addi r4,r2,10 + 100fea8: e17ffe17 ldw r5,-8(fp) + 100feac: 100edfc0 call 100edfc + 100feb0: e0bffb17 ldw r2,-20(fp) + 100feb4: e0bff715 stw r2,-36(fp) + 100feb8: e0bff717 ldw r2,-36(fp) + 100febc: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + 100fec0: e0bfff17 ldw r2,-4(fp) + 100fec4: 10000005 stb zero,0(r2) + return; +} + 100fec8: e037883a mov sp,fp + 100fecc: dfc00117 ldw ra,4(sp) + 100fed0: df000017 ldw fp,0(sp) + 100fed4: dec00204 addi sp,sp,8 + 100fed8: f800283a ret + +0100fedc : +* event flags. +********************************************************************************************************* +*/ + +OS_FLAGS OSFlagPend (OS_FLAG_GRP *pgrp, OS_FLAGS flags, INT8U wait_type, INT16U timeout, INT8U *perr) +{ + 100fedc: deffe004 addi sp,sp,-128 + 100fee0: dfc01f15 stw ra,124(sp) + 100fee4: df001e15 stw fp,120(sp) + 100fee8: df001e04 addi fp,sp,120 + 100feec: e13ff915 stw r4,-28(fp) + 100fef0: e17ffa0d sth r5,-24(fp) + 100fef4: e1bffb05 stb r6,-20(fp) + 100fef8: e1fffc0d sth r7,-16(fp) + OS_FLAGS flags_rdy; + INT8U result; + INT8U pend_stat; + BOOLEAN consume; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 100fefc: e03ff115 stw zero,-60(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + 100ff00: e0800217 ldw r2,8(fp) + 100ff04: 1004c03a cmpne r2,r2,zero + 100ff08: 1000021e bne r2,zero,100ff14 + return ((OS_FLAGS)0); + 100ff0c: e03fff15 stw zero,-4(fp) + 100ff10: 00017d06 br 1010508 + } + if (pgrp == (OS_FLAG_GRP *)0) { /* Validate 'pgrp' */ + 100ff14: e0bff917 ldw r2,-28(fp) + 100ff18: 1004c03a cmpne r2,r2,zero + 100ff1c: 1000051e bne r2,zero,100ff34 + *perr = OS_ERR_FLAG_INVALID_PGRP; + 100ff20: e0c00217 ldw r3,8(fp) + 100ff24: 00801b84 movi r2,110 + 100ff28: 18800005 stb r2,0(r3) + return ((OS_FLAGS)0); + 100ff2c: e03fff15 stw zero,-4(fp) + 100ff30: 00017506 br 1010508 + } +#endif + if (OSIntNesting > 0) { /* See if called from ISR ... */ + 100ff34: 008040b4 movhi r2,258 + 100ff38: 10b31e04 addi r2,r2,-13192 + 100ff3c: 10800003 ldbu r2,0(r2) + 100ff40: 10803fcc andi r2,r2,255 + 100ff44: 1005003a cmpeq r2,r2,zero + 100ff48: 1000051e bne r2,zero,100ff60 + *perr = OS_ERR_PEND_ISR; /* ... can't PEND from an ISR */ + 100ff4c: e0c00217 ldw r3,8(fp) + 100ff50: 00800084 movi r2,2 + 100ff54: 18800005 stb r2,0(r3) + return ((OS_FLAGS)0); + 100ff58: e03fff15 stw zero,-4(fp) + 100ff5c: 00016a06 br 1010508 + } + if (OSLockNesting > 0) { /* See if called with scheduler locked ... */ + 100ff60: 008040b4 movhi r2,258 + 100ff64: 10b31004 addi r2,r2,-13248 + 100ff68: 10800003 ldbu r2,0(r2) + 100ff6c: 10803fcc andi r2,r2,255 + 100ff70: 1005003a cmpeq r2,r2,zero + 100ff74: 1000051e bne r2,zero,100ff8c + *perr = OS_ERR_PEND_LOCKED; /* ... can't PEND when locked */ + 100ff78: e0c00217 ldw r3,8(fp) + 100ff7c: 00800344 movi r2,13 + 100ff80: 18800005 stb r2,0(r3) + return ((OS_FLAGS)0); + 100ff84: e03fff15 stw zero,-4(fp) + 100ff88: 00015f06 br 1010508 + } + if (pgrp->OSFlagType != OS_EVENT_TYPE_FLAG) { /* Validate event block type */ + 100ff8c: e0bff917 ldw r2,-28(fp) + 100ff90: 10800003 ldbu r2,0(r2) + 100ff94: 10803fcc andi r2,r2,255 + 100ff98: 10800160 cmpeqi r2,r2,5 + 100ff9c: 1000051e bne r2,zero,100ffb4 + *perr = OS_ERR_EVENT_TYPE; + 100ffa0: e0c00217 ldw r3,8(fp) + 100ffa4: 00800044 movi r2,1 + 100ffa8: 18800005 stb r2,0(r3) + return ((OS_FLAGS)0); + 100ffac: e03fff15 stw zero,-4(fp) + 100ffb0: 00015506 br 1010508 + } + result = (INT8U)(wait_type & OS_FLAG_CONSUME); + 100ffb4: e0fffb03 ldbu r3,-20(fp) + 100ffb8: 00bfe004 movi r2,-128 + 100ffbc: 1884703a and r2,r3,r2 + 100ffc0: e0bff285 stb r2,-54(fp) + if (result != (INT8U)0) { /* See if we need to consume the flags */ + 100ffc4: e0bff283 ldbu r2,-54(fp) + 100ffc8: 1005003a cmpeq r2,r2,zero + 100ffcc: 1000071e bne r2,zero,100ffec + wait_type &= ~(INT8U)OS_FLAG_CONSUME; + 100ffd0: 00c01fc4 movi r3,127 + 100ffd4: e0bffb03 ldbu r2,-20(fp) + 100ffd8: 10c4703a and r2,r2,r3 + 100ffdc: e0bffb05 stb r2,-20(fp) + consume = OS_TRUE; + 100ffe0: 00800044 movi r2,1 + 100ffe4: e0bff205 stb r2,-56(fp) + 100ffe8: 00000106 br 100fff0 + } else { + consume = OS_FALSE; + 100ffec: e03ff205 stb zero,-56(fp) +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 100fff0: 0005303a rdctl r2,status + 100fff4: e0bff015 stw r2,-64(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 100fff8: e0fff017 ldw r3,-64(fp) + 100fffc: 00bfff84 movi r2,-2 + 1010000: 1884703a and r2,r3,r2 + 1010004: 1001703a wrctl status,r2 + + return context; + 1010008: e0bff017 ldw r2,-64(fp) + } +/*$PAGE*/ + OS_ENTER_CRITICAL(); + 101000c: e0bff115 stw r2,-60(fp) + switch (wait_type) { + 1010010: e0bffb03 ldbu r2,-20(fp) + 1010014: e0bffe15 stw r2,-8(fp) + 1010018: e0fffe17 ldw r3,-8(fp) + 101001c: 18800060 cmpeqi r2,r3,1 + 1010020: 1000981e bne r2,zero,1010284 + 1010024: e0fffe17 ldw r3,-8(fp) + 1010028: 18800088 cmpgei r2,r3,2 + 101002c: 1000041e bne r2,zero,1010040 + 1010030: e0fffe17 ldw r3,-8(fp) + 1010034: 1805003a cmpeq r2,r3,zero + 1010038: 1000641e bne r2,zero,10101cc + 101003c: 0000bf06 br 101033c + 1010040: e0fffe17 ldw r3,-8(fp) + 1010044: 188000a0 cmpeqi r2,r3,2 + 1010048: 1000041e bne r2,zero,101005c + 101004c: e0fffe17 ldw r3,-8(fp) + 1010050: 188000e0 cmpeqi r2,r3,3 + 1010054: 10002f1e bne r2,zero,1010114 + 1010058: 0000b806 br 101033c + case OS_FLAG_WAIT_SET_ALL: /* See if all required flags are set */ + flags_rdy = (OS_FLAGS)(pgrp->OSFlagFlags & flags); /* Extract only the bits we want */ + 101005c: e0bff917 ldw r2,-28(fp) + 1010060: 10c0020b ldhu r3,8(r2) + 1010064: e0bffa0b ldhu r2,-24(fp) + 1010068: 1884703a and r2,r3,r2 + 101006c: e0bff30d sth r2,-52(fp) + if (flags_rdy == flags) { /* Must match ALL the bits that we want */ + 1010070: e0fff30b ldhu r3,-52(fp) + 1010074: e0bffa0b ldhu r2,-24(fp) + 1010078: 18801a1e bne r3,r2,10100e4 + if (consume == OS_TRUE) { /* See if we need to consume the flags */ + 101007c: e0bff203 ldbu r2,-56(fp) + 1010080: 10800058 cmpnei r2,r2,1 + 1010084: 1000091e bne r2,zero,10100ac + pgrp->OSFlagFlags &= ~flags_rdy; /* Clear ONLY the flags that we wanted */ + 1010088: e0bff917 ldw r2,-28(fp) + 101008c: 1080020b ldhu r2,8(r2) + 1010090: 1007883a mov r3,r2 + 1010094: e0bff30b ldhu r2,-52(fp) + 1010098: 0084303a nor r2,zero,r2 + 101009c: 1884703a and r2,r3,r2 + 10100a0: 1007883a mov r3,r2 + 10100a4: e0bff917 ldw r2,-28(fp) + 10100a8: 10c0020d sth r3,8(r2) + } + OSTCBCur->OSTCBFlagsRdy = flags_rdy; /* Save flags that were ready */ + 10100ac: 008040b4 movhi r2,258 + 10100b0: 10b31f04 addi r2,r2,-13188 + 10100b4: 10c00017 ldw r3,0(r2) + 10100b8: e0bff30b ldhu r2,-52(fp) + 10100bc: 18800b0d sth r2,44(r3) + 10100c0: e0bff117 ldw r2,-60(fp) + 10100c4: e0bfef15 stw r2,-68(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 10100c8: e0bfef17 ldw r2,-68(fp) + 10100cc: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); /* Yes, condition met, return to caller */ + *perr = OS_ERR_NONE; + 10100d0: e0800217 ldw r2,8(fp) + 10100d4: 10000005 stb zero,0(r2) + return (flags_rdy); + 10100d8: e0bff30b ldhu r2,-52(fp) + 10100dc: e0bfff15 stw r2,-4(fp) + 10100e0: 00010906 br 1010508 + } else { /* Block task until events occur or timeout */ + OS_FlagBlock(pgrp, &node, flags, wait_type, timeout); + 10100e4: e1bffa0b ldhu r6,-24(fp) + 10100e8: e1fffb03 ldbu r7,-20(fp) + 10100ec: e0bffc0b ldhu r2,-16(fp) + 10100f0: e17ff404 addi r5,fp,-48 + 10100f4: d8800015 stw r2,0(sp) + 10100f8: e13ff917 ldw r4,-28(fp) + 10100fc: 1010a040 call 1010a04 + 1010100: e0bff117 ldw r2,-60(fp) + 1010104: e0bfee15 stw r2,-72(fp) + 1010108: e0bfee17 ldw r2,-72(fp) + 101010c: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + } + break; + 1010110: 00009506 br 1010368 + + case OS_FLAG_WAIT_SET_ANY: + flags_rdy = (OS_FLAGS)(pgrp->OSFlagFlags & flags); /* Extract only the bits we want */ + 1010114: e0bff917 ldw r2,-28(fp) + 1010118: 10c0020b ldhu r3,8(r2) + 101011c: e0bffa0b ldhu r2,-24(fp) + 1010120: 1884703a and r2,r3,r2 + 1010124: e0bff30d sth r2,-52(fp) + if (flags_rdy != (OS_FLAGS)0) { /* See if any flag set */ + 1010128: e0bff30b ldhu r2,-52(fp) + 101012c: 1005003a cmpeq r2,r2,zero + 1010130: 10001a1e bne r2,zero,101019c + if (consume == OS_TRUE) { /* See if we need to consume the flags */ + 1010134: e0bff203 ldbu r2,-56(fp) + 1010138: 10800058 cmpnei r2,r2,1 + 101013c: 1000091e bne r2,zero,1010164 + pgrp->OSFlagFlags &= ~flags_rdy; /* Clear ONLY the flags that we got */ + 1010140: e0bff917 ldw r2,-28(fp) + 1010144: 1080020b ldhu r2,8(r2) + 1010148: 1007883a mov r3,r2 + 101014c: e0bff30b ldhu r2,-52(fp) + 1010150: 0084303a nor r2,zero,r2 + 1010154: 1884703a and r2,r3,r2 + 1010158: 1007883a mov r3,r2 + 101015c: e0bff917 ldw r2,-28(fp) + 1010160: 10c0020d sth r3,8(r2) + } + OSTCBCur->OSTCBFlagsRdy = flags_rdy; /* Save flags that were ready */ + 1010164: 008040b4 movhi r2,258 + 1010168: 10b31f04 addi r2,r2,-13188 + 101016c: 10c00017 ldw r3,0(r2) + 1010170: e0bff30b ldhu r2,-52(fp) + 1010174: 18800b0d sth r2,44(r3) + 1010178: e0bff117 ldw r2,-60(fp) + 101017c: e0bfed15 stw r2,-76(fp) + 1010180: e0bfed17 ldw r2,-76(fp) + 1010184: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); /* Yes, condition met, return to caller */ + *perr = OS_ERR_NONE; + 1010188: e0800217 ldw r2,8(fp) + 101018c: 10000005 stb zero,0(r2) + return (flags_rdy); + 1010190: e0fff30b ldhu r3,-52(fp) + 1010194: e0ffff15 stw r3,-4(fp) + 1010198: 0000db06 br 1010508 + } else { /* Block task until events occur or timeout */ + OS_FlagBlock(pgrp, &node, flags, wait_type, timeout); + 101019c: e1bffa0b ldhu r6,-24(fp) + 10101a0: e1fffb03 ldbu r7,-20(fp) + 10101a4: e0bffc0b ldhu r2,-16(fp) + 10101a8: e17ff404 addi r5,fp,-48 + 10101ac: d8800015 stw r2,0(sp) + 10101b0: e13ff917 ldw r4,-28(fp) + 10101b4: 1010a040 call 1010a04 + 10101b8: e0bff117 ldw r2,-60(fp) + 10101bc: e0bfec15 stw r2,-80(fp) + 10101c0: e0bfec17 ldw r2,-80(fp) + 10101c4: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + } + break; + 10101c8: 00006706 br 1010368 + +#if OS_FLAG_WAIT_CLR_EN > 0 + case OS_FLAG_WAIT_CLR_ALL: /* See if all required flags are cleared */ + flags_rdy = (OS_FLAGS)(~pgrp->OSFlagFlags & flags); /* Extract only the bits we want */ + 10101cc: e0bff917 ldw r2,-28(fp) + 10101d0: 1080020b ldhu r2,8(r2) + 10101d4: 0084303a nor r2,zero,r2 + 10101d8: 1007883a mov r3,r2 + 10101dc: e0bffa0b ldhu r2,-24(fp) + 10101e0: 1884703a and r2,r3,r2 + 10101e4: e0bff30d sth r2,-52(fp) + if (flags_rdy == flags) { /* Must match ALL the bits that we want */ + 10101e8: e0fff30b ldhu r3,-52(fp) + 10101ec: e0bffa0b ldhu r2,-24(fp) + 10101f0: 1880181e bne r3,r2,1010254 + if (consume == OS_TRUE) { /* See if we need to consume the flags */ + 10101f4: e0bff203 ldbu r2,-56(fp) + 10101f8: 10800058 cmpnei r2,r2,1 + 10101fc: 1000071e bne r2,zero,101021c + pgrp->OSFlagFlags |= flags_rdy; /* Set ONLY the flags that we wanted */ + 1010200: e0bff917 ldw r2,-28(fp) + 1010204: 10c0020b ldhu r3,8(r2) + 1010208: e0bff30b ldhu r2,-52(fp) + 101020c: 1884b03a or r2,r3,r2 + 1010210: 1007883a mov r3,r2 + 1010214: e0bff917 ldw r2,-28(fp) + 1010218: 10c0020d sth r3,8(r2) + } + OSTCBCur->OSTCBFlagsRdy = flags_rdy; /* Save flags that were ready */ + 101021c: 008040b4 movhi r2,258 + 1010220: 10b31f04 addi r2,r2,-13188 + 1010224: 10c00017 ldw r3,0(r2) + 1010228: e0bff30b ldhu r2,-52(fp) + 101022c: 18800b0d sth r2,44(r3) + 1010230: e0bff117 ldw r2,-60(fp) + 1010234: e0bfeb15 stw r2,-84(fp) + 1010238: e0bfeb17 ldw r2,-84(fp) + 101023c: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); /* Yes, condition met, return to caller */ + *perr = OS_ERR_NONE; + 1010240: e0800217 ldw r2,8(fp) + 1010244: 10000005 stb zero,0(r2) + return (flags_rdy); + 1010248: e0bff30b ldhu r2,-52(fp) + 101024c: e0bfff15 stw r2,-4(fp) + 1010250: 0000ad06 br 1010508 + } else { /* Block task until events occur or timeout */ + OS_FlagBlock(pgrp, &node, flags, wait_type, timeout); + 1010254: e1bffa0b ldhu r6,-24(fp) + 1010258: e1fffb03 ldbu r7,-20(fp) + 101025c: e0bffc0b ldhu r2,-16(fp) + 1010260: e17ff404 addi r5,fp,-48 + 1010264: d8800015 stw r2,0(sp) + 1010268: e13ff917 ldw r4,-28(fp) + 101026c: 1010a040 call 1010a04 + 1010270: e0bff117 ldw r2,-60(fp) + 1010274: e0bfea15 stw r2,-88(fp) + 1010278: e0bfea17 ldw r2,-88(fp) + 101027c: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + } + break; + 1010280: 00003906 br 1010368 + + case OS_FLAG_WAIT_CLR_ANY: + flags_rdy = (OS_FLAGS)(~pgrp->OSFlagFlags & flags); /* Extract only the bits we want */ + 1010284: e0bff917 ldw r2,-28(fp) + 1010288: 1080020b ldhu r2,8(r2) + 101028c: 0084303a nor r2,zero,r2 + 1010290: 1007883a mov r3,r2 + 1010294: e0bffa0b ldhu r2,-24(fp) + 1010298: 1884703a and r2,r3,r2 + 101029c: e0bff30d sth r2,-52(fp) + if (flags_rdy != (OS_FLAGS)0) { /* See if any flag cleared */ + 10102a0: e0bff30b ldhu r2,-52(fp) + 10102a4: 1005003a cmpeq r2,r2,zero + 10102a8: 1000181e bne r2,zero,101030c + if (consume == OS_TRUE) { /* See if we need to consume the flags */ + 10102ac: e0bff203 ldbu r2,-56(fp) + 10102b0: 10800058 cmpnei r2,r2,1 + 10102b4: 1000071e bne r2,zero,10102d4 + pgrp->OSFlagFlags |= flags_rdy; /* Set ONLY the flags that we got */ + 10102b8: e0bff917 ldw r2,-28(fp) + 10102bc: 10c0020b ldhu r3,8(r2) + 10102c0: e0bff30b ldhu r2,-52(fp) + 10102c4: 1884b03a or r2,r3,r2 + 10102c8: 1007883a mov r3,r2 + 10102cc: e0bff917 ldw r2,-28(fp) + 10102d0: 10c0020d sth r3,8(r2) + } + OSTCBCur->OSTCBFlagsRdy = flags_rdy; /* Save flags that were ready */ + 10102d4: 008040b4 movhi r2,258 + 10102d8: 10b31f04 addi r2,r2,-13188 + 10102dc: 10c00017 ldw r3,0(r2) + 10102e0: e0bff30b ldhu r2,-52(fp) + 10102e4: 18800b0d sth r2,44(r3) + 10102e8: e0bff117 ldw r2,-60(fp) + 10102ec: e0bfe915 stw r2,-92(fp) + 10102f0: e0bfe917 ldw r2,-92(fp) + 10102f4: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); /* Yes, condition met, return to caller */ + *perr = OS_ERR_NONE; + 10102f8: e0800217 ldw r2,8(fp) + 10102fc: 10000005 stb zero,0(r2) + return (flags_rdy); + 1010300: e0fff30b ldhu r3,-52(fp) + 1010304: e0ffff15 stw r3,-4(fp) + 1010308: 00007f06 br 1010508 + } else { /* Block task until events occur or timeout */ + OS_FlagBlock(pgrp, &node, flags, wait_type, timeout); + 101030c: e1bffa0b ldhu r6,-24(fp) + 1010310: e1fffb03 ldbu r7,-20(fp) + 1010314: e0bffc0b ldhu r2,-16(fp) + 1010318: e17ff404 addi r5,fp,-48 + 101031c: d8800015 stw r2,0(sp) + 1010320: e13ff917 ldw r4,-28(fp) + 1010324: 1010a040 call 1010a04 + 1010328: e0bff117 ldw r2,-60(fp) + 101032c: e0bfe815 stw r2,-96(fp) + 1010330: e0bfe817 ldw r2,-96(fp) + 1010334: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + } + break; + 1010338: 00000b06 br 1010368 + 101033c: e0bff117 ldw r2,-60(fp) + 1010340: e0bfe715 stw r2,-100(fp) + 1010344: e0bfe717 ldw r2,-100(fp) + 1010348: 1001703a wrctl status,r2 +#endif + + default: + OS_EXIT_CRITICAL(); + flags_rdy = (OS_FLAGS)0; + 101034c: e03ff30d sth zero,-52(fp) + *perr = OS_ERR_FLAG_WAIT_TYPE; + 1010350: e0c00217 ldw r3,8(fp) + 1010354: 00801bc4 movi r2,111 + 1010358: 18800005 stb r2,0(r3) + return (flags_rdy); + 101035c: e0bff30b ldhu r2,-52(fp) + 1010360: e0bfff15 stw r2,-4(fp) + 1010364: 00006806 br 1010508 + } +/*$PAGE*/ + OS_Sched(); /* Find next HPT ready to run */ + 1010368: 100ecb80 call 100ecb8 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 101036c: 0005303a rdctl r2,status + 1010370: e0bfe615 stw r2,-104(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1010374: e0ffe617 ldw r3,-104(fp) + 1010378: 00bfff84 movi r2,-2 + 101037c: 1884703a and r2,r3,r2 + 1010380: 1001703a wrctl status,r2 + + return context; + 1010384: e0bfe617 ldw r2,-104(fp) + OS_ENTER_CRITICAL(); + 1010388: e0bff115 stw r2,-60(fp) + if (OSTCBCur->OSTCBStatPend != OS_STAT_PEND_OK) { /* Have we timed-out or aborted? */ + 101038c: 008040b4 movhi r2,258 + 1010390: 10b31f04 addi r2,r2,-13188 + 1010394: 10800017 ldw r2,0(r2) + 1010398: 10800c43 ldbu r2,49(r2) + 101039c: 10803fcc andi r2,r2,255 + 10103a0: 1005003a cmpeq r2,r2,zero + 10103a4: 1000221e bne r2,zero,1010430 + pend_stat = OSTCBCur->OSTCBStatPend; + 10103a8: 008040b4 movhi r2,258 + 10103ac: 10b31f04 addi r2,r2,-13188 + 10103b0: 10800017 ldw r2,0(r2) + 10103b4: 10800c43 ldbu r2,49(r2) + 10103b8: e0bff245 stb r2,-55(fp) + OSTCBCur->OSTCBStatPend = OS_STAT_PEND_OK; + 10103bc: 008040b4 movhi r2,258 + 10103c0: 10b31f04 addi r2,r2,-13188 + 10103c4: 10800017 ldw r2,0(r2) + 10103c8: 10000c45 stb zero,49(r2) + OS_FlagUnlink(&node); + 10103cc: e13ff404 addi r4,fp,-48 + 10103d0: 1010dbc0 call 1010dbc + OSTCBCur->OSTCBStat = OS_STAT_RDY; /* Yes, make task ready-to-run */ + 10103d4: 008040b4 movhi r2,258 + 10103d8: 10b31f04 addi r2,r2,-13188 + 10103dc: 10800017 ldw r2,0(r2) + 10103e0: 10000c05 stb zero,48(r2) + 10103e4: e0bff117 ldw r2,-60(fp) + 10103e8: e0bfe515 stw r2,-108(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 10103ec: e0bfe517 ldw r2,-108(fp) + 10103f0: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + flags_rdy = (OS_FLAGS)0; + 10103f4: e03ff30d sth zero,-52(fp) + switch (pend_stat) { + 10103f8: e0bff243 ldbu r2,-55(fp) + 10103fc: 108000a0 cmpeqi r2,r2,2 + 1010400: 1000011e bne r2,zero,1010408 + 1010404: 00000406 br 1010418 + case OS_STAT_PEND_ABORT: + *perr = OS_ERR_PEND_ABORT; /* Indicate that we aborted waiting */ + 1010408: e0c00217 ldw r3,8(fp) + 101040c: 00800384 movi r2,14 + 1010410: 18800005 stb r2,0(r3) + break; + 1010414: 00000306 br 1010424 + + case OS_STAT_PEND_TO: + default: + *perr = OS_ERR_TIMEOUT; /* Indicate that we timed-out waiting */ + 1010418: e0c00217 ldw r3,8(fp) + 101041c: 00800284 movi r2,10 + 1010420: 18800005 stb r2,0(r3) + break; + } + return (flags_rdy); + 1010424: e0fff30b ldhu r3,-52(fp) + 1010428: e0ffff15 stw r3,-4(fp) + 101042c: 00003606 br 1010508 + } + flags_rdy = OSTCBCur->OSTCBFlagsRdy; + 1010430: 008040b4 movhi r2,258 + 1010434: 10b31f04 addi r2,r2,-13188 + 1010438: 10800017 ldw r2,0(r2) + 101043c: 10800b0b ldhu r2,44(r2) + 1010440: e0bff30d sth r2,-52(fp) + if (consume == OS_TRUE) { /* See if we need to consume the flags */ + 1010444: e0bff203 ldbu r2,-56(fp) + 1010448: 10800058 cmpnei r2,r2,1 + 101044c: 1000261e bne r2,zero,10104e8 + switch (wait_type) { + 1010450: e0bffb03 ldbu r2,-20(fp) + 1010454: e0bffd15 stw r2,-12(fp) + 1010458: e0fffd17 ldw r3,-12(fp) + 101045c: 1804803a cmplt r2,r3,zero + 1010460: 1000181e bne r2,zero,10104c4 + 1010464: e0fffd17 ldw r3,-12(fp) + 1010468: 18800090 cmplti r2,r3,2 + 101046c: 10000d1e bne r2,zero,10104a4 + 1010470: e0fffd17 ldw r3,-12(fp) + 1010474: 18800108 cmpgei r2,r3,4 + 1010478: 1000121e bne r2,zero,10104c4 + case OS_FLAG_WAIT_SET_ALL: + case OS_FLAG_WAIT_SET_ANY: /* Clear ONLY the flags we got */ + pgrp->OSFlagFlags &= ~flags_rdy; + 101047c: e0bff917 ldw r2,-28(fp) + 1010480: 1080020b ldhu r2,8(r2) + 1010484: 1007883a mov r3,r2 + 1010488: e0bff30b ldhu r2,-52(fp) + 101048c: 0084303a nor r2,zero,r2 + 1010490: 1884703a and r2,r3,r2 + 1010494: 1007883a mov r3,r2 + 1010498: e0bff917 ldw r2,-28(fp) + 101049c: 10c0020d sth r3,8(r2) + break; + 10104a0: 00001106 br 10104e8 + +#if OS_FLAG_WAIT_CLR_EN > 0 + case OS_FLAG_WAIT_CLR_ALL: + case OS_FLAG_WAIT_CLR_ANY: /* Set ONLY the flags we got */ + pgrp->OSFlagFlags |= flags_rdy; + 10104a4: e0bff917 ldw r2,-28(fp) + 10104a8: 10c0020b ldhu r3,8(r2) + 10104ac: e0bff30b ldhu r2,-52(fp) + 10104b0: 1884b03a or r2,r3,r2 + 10104b4: 1007883a mov r3,r2 + 10104b8: e0bff917 ldw r2,-28(fp) + 10104bc: 10c0020d sth r3,8(r2) + break; + 10104c0: 00000906 br 10104e8 + 10104c4: e0bff117 ldw r2,-60(fp) + 10104c8: e0bfe415 stw r2,-112(fp) + 10104cc: e0bfe417 ldw r2,-112(fp) + 10104d0: 1001703a wrctl status,r2 +#endif + default: + OS_EXIT_CRITICAL(); + *perr = OS_ERR_FLAG_WAIT_TYPE; + 10104d4: e0c00217 ldw r3,8(fp) + 10104d8: 00801bc4 movi r2,111 + 10104dc: 18800005 stb r2,0(r3) + return ((OS_FLAGS)0); + 10104e0: e03fff15 stw zero,-4(fp) + 10104e4: 00000806 br 1010508 + 10104e8: e0bff117 ldw r2,-60(fp) + 10104ec: e0bfe315 stw r2,-116(fp) + 10104f0: e0bfe317 ldw r2,-116(fp) + 10104f4: 1001703a wrctl status,r2 + } + } + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; /* Event(s) must have occurred */ + 10104f8: e0800217 ldw r2,8(fp) + 10104fc: 10000005 stb zero,0(r2) + return (flags_rdy); + 1010500: e0bff30b ldhu r2,-52(fp) + 1010504: e0bfff15 stw r2,-4(fp) + 1010508: e0bfff17 ldw r2,-4(fp) +} + 101050c: e037883a mov sp,fp + 1010510: dfc00117 ldw ra,4(sp) + 1010514: df000017 ldw fp,0(sp) + 1010518: dec00204 addi sp,sp,8 + 101051c: f800283a ret + +01010520 : +* Called from: Task ONLY +********************************************************************************************************* +*/ + +OS_FLAGS OSFlagPendGetFlagsRdy (void) +{ + 1010520: defffb04 addi sp,sp,-20 + 1010524: df000415 stw fp,16(sp) + 1010528: df000404 addi fp,sp,16 + OS_FLAGS flags; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 101052c: e03ffe15 stw zero,-8(fp) +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1010530: 0005303a rdctl r2,status + 1010534: e0bffd15 stw r2,-12(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1010538: e0fffd17 ldw r3,-12(fp) + 101053c: 00bfff84 movi r2,-2 + 1010540: 1884703a and r2,r3,r2 + 1010544: 1001703a wrctl status,r2 + + return context; + 1010548: e0bffd17 ldw r2,-12(fp) +#endif + + + + OS_ENTER_CRITICAL(); + 101054c: e0bffe15 stw r2,-8(fp) + flags = OSTCBCur->OSTCBFlagsRdy; + 1010550: 008040b4 movhi r2,258 + 1010554: 10b31f04 addi r2,r2,-13188 + 1010558: 10800017 ldw r2,0(r2) + 101055c: 10800b0b ldhu r2,44(r2) + 1010560: e0bfff0d sth r2,-4(fp) + 1010564: e0bffe17 ldw r2,-8(fp) + 1010568: e0bffc15 stw r2,-16(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 101056c: e0bffc17 ldw r2,-16(fp) + 1010570: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (flags); + 1010574: e0bfff0b ldhu r2,-4(fp) +} + 1010578: e037883a mov sp,fp + 101057c: df000017 ldw fp,0(sp) + 1010580: dec00104 addi sp,sp,4 + 1010584: f800283a ret + +01010588 : +* 2) The amount of time interrupts are DISABLED depends on the number of tasks waiting on +* the event flag group. +********************************************************************************************************* +*/ +OS_FLAGS OSFlagPost (OS_FLAG_GRP *pgrp, OS_FLAGS flags, INT8U opt, INT8U *perr) +{ + 1010588: deffed04 addi sp,sp,-76 + 101058c: dfc01215 stw ra,72(sp) + 1010590: df001115 stw fp,68(sp) + 1010594: df001104 addi fp,sp,68 + 1010598: e13ff915 stw r4,-28(fp) + 101059c: e1fffc15 stw r7,-16(fp) + 10105a0: e17ffa0d sth r5,-24(fp) + 10105a4: e1bffb05 stb r6,-20(fp) + BOOLEAN sched; + OS_FLAGS flags_cur; + OS_FLAGS flags_rdy; + BOOLEAN rdy; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 10105a8: e03ff515 stw zero,-44(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + 10105ac: e0bffc17 ldw r2,-16(fp) + 10105b0: 1004c03a cmpne r2,r2,zero + 10105b4: 1000021e bne r2,zero,10105c0 + return ((OS_FLAGS)0); + 10105b8: e03fff15 stw zero,-4(fp) + 10105bc: 0000d606 br 1010918 + } + if (pgrp == (OS_FLAG_GRP *)0) { /* Validate 'pgrp' */ + 10105c0: e0bff917 ldw r2,-28(fp) + 10105c4: 1004c03a cmpne r2,r2,zero + 10105c8: 1000051e bne r2,zero,10105e0 + *perr = OS_ERR_FLAG_INVALID_PGRP; + 10105cc: e0fffc17 ldw r3,-16(fp) + 10105d0: 00801b84 movi r2,110 + 10105d4: 18800005 stb r2,0(r3) + return ((OS_FLAGS)0); + 10105d8: e03fff15 stw zero,-4(fp) + 10105dc: 0000ce06 br 1010918 + } +#endif + if (pgrp->OSFlagType != OS_EVENT_TYPE_FLAG) { /* Make sure we are pointing to an event flag grp */ + 10105e0: e0bff917 ldw r2,-28(fp) + 10105e4: 10800003 ldbu r2,0(r2) + 10105e8: 10803fcc andi r2,r2,255 + 10105ec: 10800160 cmpeqi r2,r2,5 + 10105f0: 1000051e bne r2,zero,1010608 + *perr = OS_ERR_EVENT_TYPE; + 10105f4: e0fffc17 ldw r3,-16(fp) + 10105f8: 00800044 movi r2,1 + 10105fc: 18800005 stb r2,0(r3) + return ((OS_FLAGS)0); + 1010600: e03fff15 stw zero,-4(fp) + 1010604: 0000c406 br 1010918 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1010608: 0005303a rdctl r2,status + 101060c: e0bff415 stw r2,-48(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1010610: e0fff417 ldw r3,-48(fp) + 1010614: 00bfff84 movi r2,-2 + 1010618: 1884703a and r2,r3,r2 + 101061c: 1001703a wrctl status,r2 + + return context; + 1010620: e0bff417 ldw r2,-48(fp) + } +/*$PAGE*/ + OS_ENTER_CRITICAL(); + 1010624: e0bff515 stw r2,-44(fp) + switch (opt) { + 1010628: e0bffb03 ldbu r2,-20(fp) + 101062c: e0bffe15 stw r2,-8(fp) + 1010630: e0fffe17 ldw r3,-8(fp) + 1010634: 1805003a cmpeq r2,r3,zero + 1010638: 1000041e bne r2,zero,101064c + 101063c: e0fffe17 ldw r3,-8(fp) + 1010640: 18800060 cmpeqi r2,r3,1 + 1010644: 10000b1e bne r2,zero,1010674 + 1010648: 00001206 br 1010694 + case OS_FLAG_CLR: + pgrp->OSFlagFlags &= ~flags; /* Clear the flags specified in the group */ + 101064c: e0bff917 ldw r2,-28(fp) + 1010650: 1080020b ldhu r2,8(r2) + 1010654: 1007883a mov r3,r2 + 1010658: e0bffa0b ldhu r2,-24(fp) + 101065c: 0084303a nor r2,zero,r2 + 1010660: 1884703a and r2,r3,r2 + 1010664: 1007883a mov r3,r2 + 1010668: e0bff917 ldw r2,-28(fp) + 101066c: 10c0020d sth r3,8(r2) + break; + 1010670: 00001106 br 10106b8 + + case OS_FLAG_SET: + pgrp->OSFlagFlags |= flags; /* Set the flags specified in the group */ + 1010674: e0bff917 ldw r2,-28(fp) + 1010678: 10c0020b ldhu r3,8(r2) + 101067c: e0bffa0b ldhu r2,-24(fp) + 1010680: 1884b03a or r2,r3,r2 + 1010684: 1007883a mov r3,r2 + 1010688: e0bff917 ldw r2,-28(fp) + 101068c: 10c0020d sth r3,8(r2) + break; + 1010690: 00000906 br 10106b8 + 1010694: e0bff517 ldw r2,-44(fp) + 1010698: e0bff315 stw r2,-52(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 101069c: e0bff317 ldw r2,-52(fp) + 10106a0: 1001703a wrctl status,r2 + + default: + OS_EXIT_CRITICAL(); /* INVALID option */ + *perr = OS_ERR_FLAG_INVALID_OPT; + 10106a4: e0fffc17 ldw r3,-16(fp) + 10106a8: 00801c44 movi r2,113 + 10106ac: 18800005 stb r2,0(r3) + return ((OS_FLAGS)0); + 10106b0: e03fff15 stw zero,-4(fp) + 10106b4: 00009806 br 1010918 + } + sched = OS_FALSE; /* Indicate that we don't need rescheduling */ + 10106b8: e03ff785 stb zero,-34(fp) + pnode = (OS_FLAG_NODE *)pgrp->OSFlagWaitList; + 10106bc: e0bff917 ldw r2,-28(fp) + 10106c0: 10800117 ldw r2,4(r2) + 10106c4: e0bff815 stw r2,-32(fp) + while (pnode != (OS_FLAG_NODE *)0) { /* Go through all tasks waiting on event flag(s) */ + 10106c8: 00007506 br 10108a0 + switch (pnode->OSFlagNodeWaitType) { + 10106cc: e0bff817 ldw r2,-32(fp) + 10106d0: 10800483 ldbu r2,18(r2) + 10106d4: 10803fcc andi r2,r2,255 + 10106d8: e0bffd15 stw r2,-12(fp) + 10106dc: e0fffd17 ldw r3,-12(fp) + 10106e0: 18800060 cmpeqi r2,r3,1 + 10106e4: 10004d1e bne r2,zero,101081c + 10106e8: e0fffd17 ldw r3,-12(fp) + 10106ec: 18800088 cmpgei r2,r3,2 + 10106f0: 1000041e bne r2,zero,1010704 + 10106f4: e0fffd17 ldw r3,-12(fp) + 10106f8: 1805003a cmpeq r2,r3,zero + 10106fc: 1000301e bne r2,zero,10107c0 + 1010700: 00005b06 br 1010870 + 1010704: e0fffd17 ldw r3,-12(fp) + 1010708: 188000a0 cmpeqi r2,r3,2 + 101070c: 1000041e bne r2,zero,1010720 + 1010710: e0fffd17 ldw r3,-12(fp) + 1010714: 188000e0 cmpeqi r2,r3,3 + 1010718: 1000161e bne r2,zero,1010774 + 101071c: 00005406 br 1010870 + case OS_FLAG_WAIT_SET_ALL: /* See if all req. flags are set for current node */ + flags_rdy = (OS_FLAGS)(pgrp->OSFlagFlags & pnode->OSFlagNodeFlags); + 1010720: e0bff917 ldw r2,-28(fp) + 1010724: 10c0020b ldhu r3,8(r2) + 1010728: e0bff817 ldw r2,-32(fp) + 101072c: 1080040b ldhu r2,16(r2) + 1010730: 1884703a and r2,r3,r2 + 1010734: e0bff68d sth r2,-38(fp) + if (flags_rdy == pnode->OSFlagNodeFlags) { + 1010738: e0bff817 ldw r2,-32(fp) + 101073c: 1080040b ldhu r2,16(r2) + 1010740: 10ffffcc andi r3,r2,65535 + 1010744: e0bff68b ldhu r2,-38(fp) + 1010748: 1880521e bne r3,r2,1010894 + rdy = OS_FlagTaskRdy(pnode, flags_rdy); /* Make task RTR, event(s) Rx'd */ + 101074c: e17ff68b ldhu r5,-38(fp) + 1010750: e13ff817 ldw r4,-32(fp) + 1010754: 1010cac0 call 1010cac + 1010758: e0bff605 stb r2,-40(fp) + if (rdy == OS_TRUE) { + 101075c: e0bff603 ldbu r2,-40(fp) + 1010760: 10800058 cmpnei r2,r2,1 + 1010764: 10004b1e bne r2,zero,1010894 + sched = OS_TRUE; /* When done we will reschedule */ + 1010768: 00800044 movi r2,1 + 101076c: e0bff785 stb r2,-34(fp) + } + } + break; + 1010770: 00004806 br 1010894 + + case OS_FLAG_WAIT_SET_ANY: /* See if any flag set */ + flags_rdy = (OS_FLAGS)(pgrp->OSFlagFlags & pnode->OSFlagNodeFlags); + 1010774: e0bff917 ldw r2,-28(fp) + 1010778: 10c0020b ldhu r3,8(r2) + 101077c: e0bff817 ldw r2,-32(fp) + 1010780: 1080040b ldhu r2,16(r2) + 1010784: 1884703a and r2,r3,r2 + 1010788: e0bff68d sth r2,-38(fp) + if (flags_rdy != (OS_FLAGS)0) { + 101078c: e0bff68b ldhu r2,-38(fp) + 1010790: 1005003a cmpeq r2,r2,zero + 1010794: 10003f1e bne r2,zero,1010894 + rdy = OS_FlagTaskRdy(pnode, flags_rdy); /* Make task RTR, event(s) Rx'd */ + 1010798: e17ff68b ldhu r5,-38(fp) + 101079c: e13ff817 ldw r4,-32(fp) + 10107a0: 1010cac0 call 1010cac + 10107a4: e0bff605 stb r2,-40(fp) + if (rdy == OS_TRUE) { + 10107a8: e0bff603 ldbu r2,-40(fp) + 10107ac: 10800058 cmpnei r2,r2,1 + 10107b0: 1000381e bne r2,zero,1010894 + sched = OS_TRUE; /* When done we will reschedule */ + 10107b4: 00800044 movi r2,1 + 10107b8: e0bff785 stb r2,-34(fp) + } + } + break; + 10107bc: 00003506 br 1010894 + +#if OS_FLAG_WAIT_CLR_EN > 0 + case OS_FLAG_WAIT_CLR_ALL: /* See if all req. flags are set for current node */ + flags_rdy = (OS_FLAGS)(~pgrp->OSFlagFlags & pnode->OSFlagNodeFlags); + 10107c0: e0bff917 ldw r2,-28(fp) + 10107c4: 1080020b ldhu r2,8(r2) + 10107c8: 0084303a nor r2,zero,r2 + 10107cc: 1007883a mov r3,r2 + 10107d0: e0bff817 ldw r2,-32(fp) + 10107d4: 1080040b ldhu r2,16(r2) + 10107d8: 1884703a and r2,r3,r2 + 10107dc: e0bff68d sth r2,-38(fp) + if (flags_rdy == pnode->OSFlagNodeFlags) { + 10107e0: e0bff817 ldw r2,-32(fp) + 10107e4: 1080040b ldhu r2,16(r2) + 10107e8: 10ffffcc andi r3,r2,65535 + 10107ec: e0bff68b ldhu r2,-38(fp) + 10107f0: 1880281e bne r3,r2,1010894 + rdy = OS_FlagTaskRdy(pnode, flags_rdy); /* Make task RTR, event(s) Rx'd */ + 10107f4: e17ff68b ldhu r5,-38(fp) + 10107f8: e13ff817 ldw r4,-32(fp) + 10107fc: 1010cac0 call 1010cac + 1010800: e0bff605 stb r2,-40(fp) + if (rdy == OS_TRUE) { + 1010804: e0bff603 ldbu r2,-40(fp) + 1010808: 10800058 cmpnei r2,r2,1 + 101080c: 1000211e bne r2,zero,1010894 + sched = OS_TRUE; /* When done we will reschedule */ + 1010810: 00800044 movi r2,1 + 1010814: e0bff785 stb r2,-34(fp) + } + } + break; + 1010818: 00001e06 br 1010894 + + case OS_FLAG_WAIT_CLR_ANY: /* See if any flag set */ + flags_rdy = (OS_FLAGS)(~pgrp->OSFlagFlags & pnode->OSFlagNodeFlags); + 101081c: e0bff917 ldw r2,-28(fp) + 1010820: 1080020b ldhu r2,8(r2) + 1010824: 0084303a nor r2,zero,r2 + 1010828: 1007883a mov r3,r2 + 101082c: e0bff817 ldw r2,-32(fp) + 1010830: 1080040b ldhu r2,16(r2) + 1010834: 1884703a and r2,r3,r2 + 1010838: e0bff68d sth r2,-38(fp) + if (flags_rdy != (OS_FLAGS)0) { + 101083c: e0bff68b ldhu r2,-38(fp) + 1010840: 1005003a cmpeq r2,r2,zero + 1010844: 1000131e bne r2,zero,1010894 + rdy = OS_FlagTaskRdy(pnode, flags_rdy); /* Make task RTR, event(s) Rx'd */ + 1010848: e17ff68b ldhu r5,-38(fp) + 101084c: e13ff817 ldw r4,-32(fp) + 1010850: 1010cac0 call 1010cac + 1010854: e0bff605 stb r2,-40(fp) + if (rdy == OS_TRUE) { + 1010858: e0bff603 ldbu r2,-40(fp) + 101085c: 10800058 cmpnei r2,r2,1 + 1010860: 10000c1e bne r2,zero,1010894 + sched = OS_TRUE; /* When done we will reschedule */ + 1010864: 00800044 movi r2,1 + 1010868: e0bff785 stb r2,-34(fp) + } + } + break; + 101086c: 00000906 br 1010894 + 1010870: e0bff517 ldw r2,-44(fp) + 1010874: e0bff215 stw r2,-56(fp) + 1010878: e0bff217 ldw r2,-56(fp) + 101087c: 1001703a wrctl status,r2 +#endif + default: + OS_EXIT_CRITICAL(); + *perr = OS_ERR_FLAG_WAIT_TYPE; + 1010880: e0fffc17 ldw r3,-16(fp) + 1010884: 00801bc4 movi r2,111 + 1010888: 18800005 stb r2,0(r3) + return ((OS_FLAGS)0); + 101088c: e03fff15 stw zero,-4(fp) + 1010890: 00002106 br 1010918 + } + pnode = (OS_FLAG_NODE *)pnode->OSFlagNodeNext; /* Point to next task waiting for event flag(s) */ + 1010894: e0bff817 ldw r2,-32(fp) + 1010898: 10800017 ldw r2,0(r2) + 101089c: e0bff815 stw r2,-32(fp) + *perr = OS_ERR_FLAG_INVALID_OPT; + return ((OS_FLAGS)0); + } + sched = OS_FALSE; /* Indicate that we don't need rescheduling */ + pnode = (OS_FLAG_NODE *)pgrp->OSFlagWaitList; + while (pnode != (OS_FLAG_NODE *)0) { /* Go through all tasks waiting on event flag(s) */ + 10108a0: e0bff817 ldw r2,-32(fp) + 10108a4: 1004c03a cmpne r2,r2,zero + 10108a8: 103f881e bne r2,zero,10106cc + 10108ac: e0bff517 ldw r2,-44(fp) + 10108b0: e0bff115 stw r2,-60(fp) + 10108b4: e0bff117 ldw r2,-60(fp) + 10108b8: 1001703a wrctl status,r2 + return ((OS_FLAGS)0); + } + pnode = (OS_FLAG_NODE *)pnode->OSFlagNodeNext; /* Point to next task waiting for event flag(s) */ + } + OS_EXIT_CRITICAL(); + if (sched == OS_TRUE) { + 10108bc: e0bff783 ldbu r2,-34(fp) + 10108c0: 10800058 cmpnei r2,r2,1 + 10108c4: 1000011e bne r2,zero,10108cc + OS_Sched(); + 10108c8: 100ecb80 call 100ecb8 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 10108cc: 0005303a rdctl r2,status + 10108d0: e0bff015 stw r2,-64(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 10108d4: e0fff017 ldw r3,-64(fp) + 10108d8: 00bfff84 movi r2,-2 + 10108dc: 1884703a and r2,r3,r2 + 10108e0: 1001703a wrctl status,r2 + + return context; + 10108e4: e0bff017 ldw r2,-64(fp) + } + OS_ENTER_CRITICAL(); + 10108e8: e0bff515 stw r2,-44(fp) + flags_cur = pgrp->OSFlagFlags; + 10108ec: e0bff917 ldw r2,-28(fp) + 10108f0: 1080020b ldhu r2,8(r2) + 10108f4: e0bff70d sth r2,-36(fp) + 10108f8: e0bff517 ldw r2,-44(fp) + 10108fc: e0bfef15 stw r2,-68(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1010900: e0bfef17 ldw r2,-68(fp) + 1010904: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + 1010908: e0bffc17 ldw r2,-16(fp) + 101090c: 10000005 stb zero,0(r2) + return (flags_cur); + 1010910: e0bff70b ldhu r2,-36(fp) + 1010914: e0bfff15 stw r2,-4(fp) + 1010918: e0bfff17 ldw r2,-4(fp) +} + 101091c: e037883a mov sp,fp + 1010920: dfc00117 ldw ra,4(sp) + 1010924: df000017 ldw fp,0(sp) + 1010928: dec00204 addi sp,sp,8 + 101092c: f800283a ret + +01010930 : +********************************************************************************************************* +*/ + +#if OS_FLAG_QUERY_EN > 0 +OS_FLAGS OSFlagQuery (OS_FLAG_GRP *pgrp, INT8U *perr) +{ + 1010930: defff804 addi sp,sp,-32 + 1010934: df000715 stw fp,28(sp) + 1010938: df000704 addi fp,sp,28 + 101093c: e13ffd15 stw r4,-12(fp) + 1010940: e17ffe15 stw r5,-8(fp) + OS_FLAGS flags; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 1010944: e03ffb15 stw zero,-20(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + 1010948: e0bffe17 ldw r2,-8(fp) + 101094c: 1004c03a cmpne r2,r2,zero + 1010950: 1000021e bne r2,zero,101095c + return ((OS_FLAGS)0); + 1010954: e03fff15 stw zero,-4(fp) + 1010958: 00002506 br 10109f0 + } + if (pgrp == (OS_FLAG_GRP *)0) { /* Validate 'pgrp' */ + 101095c: e0bffd17 ldw r2,-12(fp) + 1010960: 1004c03a cmpne r2,r2,zero + 1010964: 1000051e bne r2,zero,101097c + *perr = OS_ERR_FLAG_INVALID_PGRP; + 1010968: e0fffe17 ldw r3,-8(fp) + 101096c: 00801b84 movi r2,110 + 1010970: 18800005 stb r2,0(r3) + return ((OS_FLAGS)0); + 1010974: e03fff15 stw zero,-4(fp) + 1010978: 00001d06 br 10109f0 + } +#endif + if (pgrp->OSFlagType != OS_EVENT_TYPE_FLAG) { /* Validate event block type */ + 101097c: e0bffd17 ldw r2,-12(fp) + 1010980: 10800003 ldbu r2,0(r2) + 1010984: 10803fcc andi r2,r2,255 + 1010988: 10800160 cmpeqi r2,r2,5 + 101098c: 1000051e bne r2,zero,10109a4 + *perr = OS_ERR_EVENT_TYPE; + 1010990: e0fffe17 ldw r3,-8(fp) + 1010994: 00800044 movi r2,1 + 1010998: 18800005 stb r2,0(r3) + return ((OS_FLAGS)0); + 101099c: e03fff15 stw zero,-4(fp) + 10109a0: 00001306 br 10109f0 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 10109a4: 0005303a rdctl r2,status + 10109a8: e0bffa15 stw r2,-24(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 10109ac: e0fffa17 ldw r3,-24(fp) + 10109b0: 00bfff84 movi r2,-2 + 10109b4: 1884703a and r2,r3,r2 + 10109b8: 1001703a wrctl status,r2 + + return context; + 10109bc: e0bffa17 ldw r2,-24(fp) + } + OS_ENTER_CRITICAL(); + 10109c0: e0bffb15 stw r2,-20(fp) + flags = pgrp->OSFlagFlags; + 10109c4: e0bffd17 ldw r2,-12(fp) + 10109c8: 1080020b ldhu r2,8(r2) + 10109cc: e0bffc0d sth r2,-16(fp) + 10109d0: e0bffb17 ldw r2,-20(fp) + 10109d4: e0bff915 stw r2,-28(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 10109d8: e0bff917 ldw r2,-28(fp) + 10109dc: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + 10109e0: e0bffe17 ldw r2,-8(fp) + 10109e4: 10000005 stb zero,0(r2) + return (flags); /* Return the current value of the event flags */ + 10109e8: e0bffc0b ldhu r2,-16(fp) + 10109ec: e0bfff15 stw r2,-4(fp) + 10109f0: e0bfff17 ldw r2,-4(fp) +} + 10109f4: e037883a mov sp,fp + 10109f8: df000017 ldw fp,0(sp) + 10109fc: dec00104 addi sp,sp,4 + 1010a00: f800283a ret + +01010a04 : +* Note(s) : This function is INTERNAL to uC/OS-II and your application should not call it. +********************************************************************************************************* +*/ + +static void OS_FlagBlock (OS_FLAG_GRP *pgrp, OS_FLAG_NODE *pnode, OS_FLAGS flags, INT8U wait_type, INT16U timeout) +{ + 1010a04: defff804 addi sp,sp,-32 + 1010a08: df000715 stw fp,28(sp) + 1010a0c: df000704 addi fp,sp,28 + 1010a10: e13ffb15 stw r4,-20(fp) + 1010a14: e17ffc15 stw r5,-16(fp) + 1010a18: e0800117 ldw r2,4(fp) + 1010a1c: e1bffd0d sth r6,-12(fp) + 1010a20: e1fffe05 stb r7,-8(fp) + 1010a24: e0bfff0d sth r2,-4(fp) + OS_FLAG_NODE *pnode_next; + INT8U y; + + + OSTCBCur->OSTCBStat |= OS_STAT_FLAG; + 1010a28: 008040b4 movhi r2,258 + 1010a2c: 10b31f04 addi r2,r2,-13188 + 1010a30: 10c00017 ldw r3,0(r2) + 1010a34: 008040b4 movhi r2,258 + 1010a38: 10b31f04 addi r2,r2,-13188 + 1010a3c: 10800017 ldw r2,0(r2) + 1010a40: 10800c03 ldbu r2,48(r2) + 1010a44: 10800814 ori r2,r2,32 + 1010a48: 18800c05 stb r2,48(r3) + OSTCBCur->OSTCBStatPend = OS_STAT_PEND_OK; + 1010a4c: 008040b4 movhi r2,258 + 1010a50: 10b31f04 addi r2,r2,-13188 + 1010a54: 10800017 ldw r2,0(r2) + 1010a58: 10000c45 stb zero,49(r2) + OSTCBCur->OSTCBDly = timeout; /* Store timeout in task's TCB */ + 1010a5c: 008040b4 movhi r2,258 + 1010a60: 10b31f04 addi r2,r2,-13188 + 1010a64: 10c00017 ldw r3,0(r2) + 1010a68: e0bfff0b ldhu r2,-4(fp) + 1010a6c: 18800b8d sth r2,46(r3) +#if OS_TASK_DEL_EN > 0 + OSTCBCur->OSTCBFlagNode = pnode; /* TCB to link to node */ + 1010a70: 008040b4 movhi r2,258 + 1010a74: 10b31f04 addi r2,r2,-13188 + 1010a78: 10c00017 ldw r3,0(r2) + 1010a7c: e0bffc17 ldw r2,-16(fp) + 1010a80: 18800a15 stw r2,40(r3) +#endif + pnode->OSFlagNodeFlags = flags; /* Save the flags that we need to wait for */ + 1010a84: e0fffc17 ldw r3,-16(fp) + 1010a88: e0bffd0b ldhu r2,-12(fp) + 1010a8c: 1880040d sth r2,16(r3) + pnode->OSFlagNodeWaitType = wait_type; /* Save the type of wait we are doing */ + 1010a90: e0fffc17 ldw r3,-16(fp) + 1010a94: e0bffe03 ldbu r2,-8(fp) + 1010a98: 18800485 stb r2,18(r3) + pnode->OSFlagNodeTCB = (void *)OSTCBCur; /* Link to task's TCB */ + 1010a9c: 008040b4 movhi r2,258 + 1010aa0: 10b31f04 addi r2,r2,-13188 + 1010aa4: 10c00017 ldw r3,0(r2) + 1010aa8: e0bffc17 ldw r2,-16(fp) + 1010aac: 10c00215 stw r3,8(r2) + pnode->OSFlagNodeNext = pgrp->OSFlagWaitList; /* Add node at beginning of event flag wait list */ + 1010ab0: e0bffb17 ldw r2,-20(fp) + 1010ab4: 10c00117 ldw r3,4(r2) + 1010ab8: e0bffc17 ldw r2,-16(fp) + 1010abc: 10c00015 stw r3,0(r2) + pnode->OSFlagNodePrev = (void *)0; + 1010ac0: e0bffc17 ldw r2,-16(fp) + 1010ac4: 10000115 stw zero,4(r2) + pnode->OSFlagNodeFlagGrp = (void *)pgrp; /* Link to Event Flag Group */ + 1010ac8: e0fffc17 ldw r3,-16(fp) + 1010acc: e0bffb17 ldw r2,-20(fp) + 1010ad0: 18800315 stw r2,12(r3) + pnode_next = (OS_FLAG_NODE *)pgrp->OSFlagWaitList; + 1010ad4: e0bffb17 ldw r2,-20(fp) + 1010ad8: 10800117 ldw r2,4(r2) + 1010adc: e0bffa15 stw r2,-24(fp) + if (pnode_next != (void *)0) { /* Is this the first NODE to insert? */ + 1010ae0: e0bffa17 ldw r2,-24(fp) + 1010ae4: 1005003a cmpeq r2,r2,zero + 1010ae8: 1000031e bne r2,zero,1010af8 + pnode_next->OSFlagNodePrev = pnode; /* No, link in doubly linked list */ + 1010aec: e0fffa17 ldw r3,-24(fp) + 1010af0: e0bffc17 ldw r2,-16(fp) + 1010af4: 18800115 stw r2,4(r3) + } + pgrp->OSFlagWaitList = (void *)pnode; + 1010af8: e0fffb17 ldw r3,-20(fp) + 1010afc: e0bffc17 ldw r2,-16(fp) + 1010b00: 18800115 stw r2,4(r3) + + y = OSTCBCur->OSTCBY; /* Suspend current task until flag(s) received */ + 1010b04: 008040b4 movhi r2,258 + 1010b08: 10b31f04 addi r2,r2,-13188 + 1010b0c: 10800017 ldw r2,0(r2) + 1010b10: 10800d03 ldbu r2,52(r2) + 1010b14: e0bff905 stb r2,-28(fp) + OSRdyTbl[y] &= ~OSTCBCur->OSTCBBitX; + 1010b18: e13ff903 ldbu r4,-28(fp) + 1010b1c: e0fff903 ldbu r3,-28(fp) + 1010b20: 008040b4 movhi r2,258 + 1010b24: 10b31c44 addi r2,r2,-13199 + 1010b28: 10c5883a add r2,r2,r3 + 1010b2c: 10800003 ldbu r2,0(r2) + 1010b30: 1007883a mov r3,r2 + 1010b34: 008040b4 movhi r2,258 + 1010b38: 10b31f04 addi r2,r2,-13188 + 1010b3c: 10800017 ldw r2,0(r2) + 1010b40: 10800d43 ldbu r2,53(r2) + 1010b44: 0084303a nor r2,zero,r2 + 1010b48: 1884703a and r2,r3,r2 + 1010b4c: 1007883a mov r3,r2 + 1010b50: 008040b4 movhi r2,258 + 1010b54: 10b31c44 addi r2,r2,-13199 + 1010b58: 1105883a add r2,r2,r4 + 1010b5c: 10c00005 stb r3,0(r2) + if (OSRdyTbl[y] == 0x00) { + 1010b60: e0fff903 ldbu r3,-28(fp) + 1010b64: 008040b4 movhi r2,258 + 1010b68: 10b31c44 addi r2,r2,-13199 + 1010b6c: 10c5883a add r2,r2,r3 + 1010b70: 10800003 ldbu r2,0(r2) + 1010b74: 10803fcc andi r2,r2,255 + 1010b78: 1004c03a cmpne r2,r2,zero + 1010b7c: 10000e1e bne r2,zero,1010bb8 + OSRdyGrp &= ~OSTCBCur->OSTCBBitY; + 1010b80: 008040b4 movhi r2,258 + 1010b84: 10b31f04 addi r2,r2,-13188 + 1010b88: 10800017 ldw r2,0(r2) + 1010b8c: 10800d83 ldbu r2,54(r2) + 1010b90: 0084303a nor r2,zero,r2 + 1010b94: 1007883a mov r3,r2 + 1010b98: 008040b4 movhi r2,258 + 1010b9c: 10b31c04 addi r2,r2,-13200 + 1010ba0: 10800003 ldbu r2,0(r2) + 1010ba4: 1884703a and r2,r3,r2 + 1010ba8: 1007883a mov r3,r2 + 1010bac: 008040b4 movhi r2,258 + 1010bb0: 10b31c04 addi r2,r2,-13200 + 1010bb4: 10c00005 stb r3,0(r2) + } +} + 1010bb8: e037883a mov sp,fp + 1010bbc: df000017 ldw fp,0(sp) + 1010bc0: dec00104 addi sp,sp,4 + 1010bc4: f800283a ret + +01010bc8 : +* WARNING : You MUST NOT call this function from your code. This is an INTERNAL function to uC/OS-II. +********************************************************************************************************* +*/ + +void OS_FlagInit (void) +{ + 1010bc8: defffb04 addi sp,sp,-20 + 1010bcc: dfc00415 stw ra,16(sp) + 1010bd0: df000315 stw fp,12(sp) + 1010bd4: df000304 addi fp,sp,12 + INT16U i; + OS_FLAG_GRP *pgrp1; + OS_FLAG_GRP *pgrp2; + + + OS_MemClr((INT8U *)&OSFlagTbl[0], sizeof(OSFlagTbl)); /* Clear the flag group table */ + 1010bd8: 010040b4 movhi r4,258 + 1010bdc: 210d3504 addi r4,r4,13524 + 1010be0: 0140dc04 movi r5,880 + 1010be4: 100ebf80 call 100ebf8 + pgrp1 = &OSFlagTbl[0]; + 1010be8: 008040b4 movhi r2,258 + 1010bec: 108d3504 addi r2,r2,13524 + 1010bf0: e0bffe15 stw r2,-8(fp) + pgrp2 = &OSFlagTbl[1]; + 1010bf4: 008040b4 movhi r2,258 + 1010bf8: 108d4004 addi r2,r2,13568 + 1010bfc: e0bffd15 stw r2,-12(fp) + for (i = 0; i < (OS_MAX_FLAGS - 1); i++) { /* Init. list of free EVENT FLAGS */ + 1010c00: e03fff0d sth zero,-4(fp) + 1010c04: 00001306 br 1010c54 + pgrp1->OSFlagType = OS_EVENT_TYPE_UNUSED; + 1010c08: e0bffe17 ldw r2,-8(fp) + 1010c0c: 10000005 stb zero,0(r2) + pgrp1->OSFlagWaitList = (void *)pgrp2; + 1010c10: e0fffe17 ldw r3,-8(fp) + 1010c14: e0bffd17 ldw r2,-12(fp) + 1010c18: 18800115 stw r2,4(r3) +#if OS_FLAG_NAME_SIZE > 1 + pgrp1->OSFlagName[0] = '?'; /* Unknown name */ + 1010c1c: e0fffe17 ldw r3,-8(fp) + 1010c20: 00800fc4 movi r2,63 + 1010c24: 18800285 stb r2,10(r3) + pgrp1->OSFlagName[1] = OS_ASCII_NUL; + 1010c28: e0bffe17 ldw r2,-8(fp) + 1010c2c: 100002c5 stb zero,11(r2) +#endif + pgrp1++; + 1010c30: e0bffe17 ldw r2,-8(fp) + 1010c34: 10800b04 addi r2,r2,44 + 1010c38: e0bffe15 stw r2,-8(fp) + pgrp2++; + 1010c3c: e0bffd17 ldw r2,-12(fp) + 1010c40: 10800b04 addi r2,r2,44 + 1010c44: e0bffd15 stw r2,-12(fp) + + + OS_MemClr((INT8U *)&OSFlagTbl[0], sizeof(OSFlagTbl)); /* Clear the flag group table */ + pgrp1 = &OSFlagTbl[0]; + pgrp2 = &OSFlagTbl[1]; + for (i = 0; i < (OS_MAX_FLAGS - 1); i++) { /* Init. list of free EVENT FLAGS */ + 1010c48: e0bfff0b ldhu r2,-4(fp) + 1010c4c: 10800044 addi r2,r2,1 + 1010c50: e0bfff0d sth r2,-4(fp) + 1010c54: e0bfff0b ldhu r2,-4(fp) + 1010c58: 108004f0 cmpltui r2,r2,19 + 1010c5c: 103fea1e bne r2,zero,1010c08 + pgrp1->OSFlagName[1] = OS_ASCII_NUL; +#endif + pgrp1++; + pgrp2++; + } + pgrp1->OSFlagType = OS_EVENT_TYPE_UNUSED; + 1010c60: e0bffe17 ldw r2,-8(fp) + 1010c64: 10000005 stb zero,0(r2) + pgrp1->OSFlagWaitList = (void *)0; + 1010c68: e0bffe17 ldw r2,-8(fp) + 1010c6c: 10000115 stw zero,4(r2) +#if OS_FLAG_NAME_SIZE > 1 + pgrp1->OSFlagName[0] = '?'; /* Unknown name */ + 1010c70: e0fffe17 ldw r3,-8(fp) + 1010c74: 00800fc4 movi r2,63 + 1010c78: 18800285 stb r2,10(r3) + pgrp1->OSFlagName[1] = OS_ASCII_NUL; + 1010c7c: e0bffe17 ldw r2,-8(fp) + 1010c80: 100002c5 stb zero,11(r2) +#endif + OSFlagFreeList = &OSFlagTbl[0]; + 1010c84: 00c040b4 movhi r3,258 + 1010c88: 18f32104 addi r3,r3,-13180 + 1010c8c: 008040b4 movhi r2,258 + 1010c90: 108d3504 addi r2,r2,13524 + 1010c94: 18800015 stw r2,0(r3) +#endif +} + 1010c98: e037883a mov sp,fp + 1010c9c: dfc00117 ldw ra,4(sp) + 1010ca0: df000017 ldw fp,0(sp) + 1010ca4: dec00204 addi sp,sp,8 + 1010ca8: f800283a ret + +01010cac : +* 2) This function is INTERNAL to uC/OS-II and your application should not call it. +********************************************************************************************************* +*/ + +static BOOLEAN OS_FlagTaskRdy (OS_FLAG_NODE *pnode, OS_FLAGS flags_rdy) +{ + 1010cac: defffa04 addi sp,sp,-24 + 1010cb0: dfc00515 stw ra,20(sp) + 1010cb4: df000415 stw fp,16(sp) + 1010cb8: df000404 addi fp,sp,16 + 1010cbc: e13ffe15 stw r4,-8(fp) + 1010cc0: e17fff0d sth r5,-4(fp) + OS_TCB *ptcb; + BOOLEAN sched; + + + ptcb = (OS_TCB *)pnode->OSFlagNodeTCB; /* Point to TCB of waiting task */ + 1010cc4: e0bffe17 ldw r2,-8(fp) + 1010cc8: 10800217 ldw r2,8(r2) + 1010ccc: e0bffd15 stw r2,-12(fp) + ptcb->OSTCBDly = 0; + 1010cd0: e0bffd17 ldw r2,-12(fp) + 1010cd4: 10000b8d sth zero,46(r2) + ptcb->OSTCBFlagsRdy = flags_rdy; + 1010cd8: e0fffd17 ldw r3,-12(fp) + 1010cdc: e0bfff0b ldhu r2,-4(fp) + 1010ce0: 18800b0d sth r2,44(r3) + ptcb->OSTCBStat &= ~(INT8U)OS_STAT_FLAG; + 1010ce4: e0bffd17 ldw r2,-12(fp) + 1010ce8: 10c00c03 ldbu r3,48(r2) + 1010cec: 00bff7c4 movi r2,-33 + 1010cf0: 1884703a and r2,r3,r2 + 1010cf4: 1007883a mov r3,r2 + 1010cf8: e0bffd17 ldw r2,-12(fp) + 1010cfc: 10c00c05 stb r3,48(r2) + ptcb->OSTCBStatPend = OS_STAT_PEND_OK; + 1010d00: e0bffd17 ldw r2,-12(fp) + 1010d04: 10000c45 stb zero,49(r2) + if (ptcb->OSTCBStat == OS_STAT_RDY) { /* Task now ready? */ + 1010d08: e0bffd17 ldw r2,-12(fp) + 1010d0c: 10800c03 ldbu r2,48(r2) + 1010d10: 10803fcc andi r2,r2,255 + 1010d14: 1004c03a cmpne r2,r2,zero + 1010d18: 10001f1e bne r2,zero,1010d98 + OSRdyGrp |= ptcb->OSTCBBitY; /* Put task into ready list */ + 1010d1c: e0bffd17 ldw r2,-12(fp) + 1010d20: 10c00d83 ldbu r3,54(r2) + 1010d24: 008040b4 movhi r2,258 + 1010d28: 10b31c04 addi r2,r2,-13200 + 1010d2c: 10800003 ldbu r2,0(r2) + 1010d30: 1884b03a or r2,r3,r2 + 1010d34: 1007883a mov r3,r2 + 1010d38: 008040b4 movhi r2,258 + 1010d3c: 10b31c04 addi r2,r2,-13200 + 1010d40: 10c00005 stb r3,0(r2) + OSRdyTbl[ptcb->OSTCBY] |= ptcb->OSTCBBitX; + 1010d44: e0bffd17 ldw r2,-12(fp) + 1010d48: 10800d03 ldbu r2,52(r2) + 1010d4c: 11003fcc andi r4,r2,255 + 1010d50: e0bffd17 ldw r2,-12(fp) + 1010d54: 10800d03 ldbu r2,52(r2) + 1010d58: 10c03fcc andi r3,r2,255 + 1010d5c: 008040b4 movhi r2,258 + 1010d60: 10b31c44 addi r2,r2,-13199 + 1010d64: 10c5883a add r2,r2,r3 + 1010d68: 10c00003 ldbu r3,0(r2) + 1010d6c: e0bffd17 ldw r2,-12(fp) + 1010d70: 10800d43 ldbu r2,53(r2) + 1010d74: 1884b03a or r2,r3,r2 + 1010d78: 1007883a mov r3,r2 + 1010d7c: 008040b4 movhi r2,258 + 1010d80: 10b31c44 addi r2,r2,-13199 + 1010d84: 1105883a add r2,r2,r4 + 1010d88: 10c00005 stb r3,0(r2) + sched = OS_TRUE; + 1010d8c: 00800044 movi r2,1 + 1010d90: e0bffc05 stb r2,-16(fp) + 1010d94: 00000106 br 1010d9c + } else { + sched = OS_FALSE; + 1010d98: e03ffc05 stb zero,-16(fp) + } + OS_FlagUnlink(pnode); + 1010d9c: e13ffe17 ldw r4,-8(fp) + 1010da0: 1010dbc0 call 1010dbc + return (sched); + 1010da4: e0bffc03 ldbu r2,-16(fp) +} + 1010da8: e037883a mov sp,fp + 1010dac: dfc00117 ldw ra,4(sp) + 1010db0: df000017 ldw fp,0(sp) + 1010db4: dec00204 addi sp,sp,8 + 1010db8: f800283a ret + +01010dbc : +* 2) This function is INTERNAL to uC/OS-II and your application should not call it. +********************************************************************************************************* +*/ + +void OS_FlagUnlink (OS_FLAG_NODE *pnode) +{ + 1010dbc: defffa04 addi sp,sp,-24 + 1010dc0: df000515 stw fp,20(sp) + 1010dc4: df000504 addi fp,sp,20 + 1010dc8: e13fff15 stw r4,-4(fp) + OS_FLAG_GRP *pgrp; + OS_FLAG_NODE *pnode_prev; + OS_FLAG_NODE *pnode_next; + + + pnode_prev = (OS_FLAG_NODE *)pnode->OSFlagNodePrev; + 1010dcc: e0bfff17 ldw r2,-4(fp) + 1010dd0: 10800117 ldw r2,4(r2) + 1010dd4: e0bffc15 stw r2,-16(fp) + pnode_next = (OS_FLAG_NODE *)pnode->OSFlagNodeNext; + 1010dd8: e0bfff17 ldw r2,-4(fp) + 1010ddc: 10800017 ldw r2,0(r2) + 1010de0: e0bffb15 stw r2,-20(fp) + if (pnode_prev == (OS_FLAG_NODE *)0) { /* Is it first node in wait list? */ + 1010de4: e0bffc17 ldw r2,-16(fp) + 1010de8: 1004c03a cmpne r2,r2,zero + 1010dec: 10000c1e bne r2,zero,1010e20 + pgrp = (OS_FLAG_GRP *)pnode->OSFlagNodeFlagGrp; + 1010df0: e0bfff17 ldw r2,-4(fp) + 1010df4: 10800317 ldw r2,12(r2) + 1010df8: e0bffd15 stw r2,-12(fp) + pgrp->OSFlagWaitList = (void *)pnode_next; /* Update list for new 1st node */ + 1010dfc: e0fffd17 ldw r3,-12(fp) + 1010e00: e0bffb17 ldw r2,-20(fp) + 1010e04: 18800115 stw r2,4(r3) + if (pnode_next != (OS_FLAG_NODE *)0) { + 1010e08: e0bffb17 ldw r2,-20(fp) + 1010e0c: 1005003a cmpeq r2,r2,zero + 1010e10: 10000c1e bne r2,zero,1010e44 + pnode_next->OSFlagNodePrev = (OS_FLAG_NODE *)0; /* Link new 1st node PREV to NULL */ + 1010e14: e0bffb17 ldw r2,-20(fp) + 1010e18: 10000115 stw zero,4(r2) + 1010e1c: 00000906 br 1010e44 + } + } else { /* No, A node somewhere in the list */ + pnode_prev->OSFlagNodeNext = pnode_next; /* Link around the node to unlink */ + 1010e20: e0fffc17 ldw r3,-16(fp) + 1010e24: e0bffb17 ldw r2,-20(fp) + 1010e28: 18800015 stw r2,0(r3) + if (pnode_next != (OS_FLAG_NODE *)0) { /* Was this the LAST node? */ + 1010e2c: e0bffb17 ldw r2,-20(fp) + 1010e30: 1005003a cmpeq r2,r2,zero + 1010e34: 1000031e bne r2,zero,1010e44 + pnode_next->OSFlagNodePrev = pnode_prev; /* No, Link around current node */ + 1010e38: e0fffb17 ldw r3,-20(fp) + 1010e3c: e0bffc17 ldw r2,-16(fp) + 1010e40: 18800115 stw r2,4(r3) + } + } +#if OS_TASK_DEL_EN > 0 + ptcb = (OS_TCB *)pnode->OSFlagNodeTCB; + 1010e44: e0bfff17 ldw r2,-4(fp) + 1010e48: 10800217 ldw r2,8(r2) + 1010e4c: e0bffe15 stw r2,-8(fp) + ptcb->OSTCBFlagNode = (OS_FLAG_NODE *)0; + 1010e50: e0bffe17 ldw r2,-8(fp) + 1010e54: 10000a15 stw zero,40(r2) +#endif +} + 1010e58: e037883a mov sp,fp + 1010e5c: df000017 ldw fp,0(sp) + 1010e60: dec00104 addi sp,sp,4 + 1010e64: f800283a ret + +01010e68 : +* free partition is available. +********************************************************************************************************* +*/ + +OS_MEM *OSMemCreate (void *addr, INT32U nblks, INT32U blksize, INT8U *perr) +{ + 1010e68: defff304 addi sp,sp,-52 + 1010e6c: df000c15 stw fp,48(sp) + 1010e70: df000c04 addi fp,sp,48 + 1010e74: e13ffb15 stw r4,-20(fp) + 1010e78: e17ffc15 stw r5,-16(fp) + 1010e7c: e1bffd15 stw r6,-12(fp) + 1010e80: e1fffe15 stw r7,-8(fp) + OS_MEM *pmem; + INT8U *pblk; + void **plink; + INT32U i; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 1010e84: e03ff615 stw zero,-40(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + 1010e88: e0bffe17 ldw r2,-8(fp) + 1010e8c: 1004c03a cmpne r2,r2,zero + 1010e90: 1000021e bne r2,zero,1010e9c + return ((OS_MEM *)0); + 1010e94: e03fff15 stw zero,-4(fp) + 1010e98: 00007506 br 1011070 + } + if (addr == (void *)0) { /* Must pass a valid address for the memory part.*/ + 1010e9c: e0bffb17 ldw r2,-20(fp) + 1010ea0: 1004c03a cmpne r2,r2,zero + 1010ea4: 1000051e bne r2,zero,1010ebc + *perr = OS_ERR_MEM_INVALID_ADDR; + 1010ea8: e0fffe17 ldw r3,-8(fp) + 1010eac: 00801884 movi r2,98 + 1010eb0: 18800005 stb r2,0(r3) + return ((OS_MEM *)0); + 1010eb4: e03fff15 stw zero,-4(fp) + 1010eb8: 00006d06 br 1011070 + } + if (((INT32U)addr & (sizeof(void *) - 1)) != 0){ /* Must be pointer size aligned */ + 1010ebc: e0bffb17 ldw r2,-20(fp) + 1010ec0: 108000cc andi r2,r2,3 + 1010ec4: 1005003a cmpeq r2,r2,zero + 1010ec8: 1000051e bne r2,zero,1010ee0 + *perr = OS_ERR_MEM_INVALID_ADDR; + 1010ecc: e0fffe17 ldw r3,-8(fp) + 1010ed0: 00801884 movi r2,98 + 1010ed4: 18800005 stb r2,0(r3) + return ((OS_MEM *)0); + 1010ed8: e03fff15 stw zero,-4(fp) + 1010edc: 00006406 br 1011070 + } + if (nblks < 2) { /* Must have at least 2 blocks per partition */ + 1010ee0: e0bffc17 ldw r2,-16(fp) + 1010ee4: 108000a8 cmpgeui r2,r2,2 + 1010ee8: 1000051e bne r2,zero,1010f00 + *perr = OS_ERR_MEM_INVALID_BLKS; + 1010eec: e0fffe17 ldw r3,-8(fp) + 1010ef0: 008016c4 movi r2,91 + 1010ef4: 18800005 stb r2,0(r3) + return ((OS_MEM *)0); + 1010ef8: e03fff15 stw zero,-4(fp) + 1010efc: 00005c06 br 1011070 + } + if (blksize < sizeof(void *)) { /* Must contain space for at least a pointer */ + 1010f00: e0bffd17 ldw r2,-12(fp) + 1010f04: 10800128 cmpgeui r2,r2,4 + 1010f08: 1000051e bne r2,zero,1010f20 + *perr = OS_ERR_MEM_INVALID_SIZE; + 1010f0c: e0fffe17 ldw r3,-8(fp) + 1010f10: 00801704 movi r2,92 + 1010f14: 18800005 stb r2,0(r3) + return ((OS_MEM *)0); + 1010f18: e03fff15 stw zero,-4(fp) + 1010f1c: 00005406 br 1011070 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1010f20: 0005303a rdctl r2,status + 1010f24: e0bff515 stw r2,-44(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1010f28: e0fff517 ldw r3,-44(fp) + 1010f2c: 00bfff84 movi r2,-2 + 1010f30: 1884703a and r2,r3,r2 + 1010f34: 1001703a wrctl status,r2 + + return context; + 1010f38: e0bff517 ldw r2,-44(fp) + } +#endif + OS_ENTER_CRITICAL(); + 1010f3c: e0bff615 stw r2,-40(fp) + pmem = OSMemFreeList; /* Get next free memory partition */ + 1010f40: 008040b4 movhi r2,258 + 1010f44: 10b31904 addi r2,r2,-13212 + 1010f48: 10800017 ldw r2,0(r2) + 1010f4c: e0bffa15 stw r2,-24(fp) + if (OSMemFreeList != (OS_MEM *)0) { /* See if pool of free partitions was empty */ + 1010f50: 008040b4 movhi r2,258 + 1010f54: 10b31904 addi r2,r2,-13212 + 1010f58: 10800017 ldw r2,0(r2) + 1010f5c: 1005003a cmpeq r2,r2,zero + 1010f60: 1000081e bne r2,zero,1010f84 + OSMemFreeList = (OS_MEM *)OSMemFreeList->OSMemFreeList; + 1010f64: 008040b4 movhi r2,258 + 1010f68: 10b31904 addi r2,r2,-13212 + 1010f6c: 10800017 ldw r2,0(r2) + 1010f70: 10800117 ldw r2,4(r2) + 1010f74: 1007883a mov r3,r2 + 1010f78: 008040b4 movhi r2,258 + 1010f7c: 10b31904 addi r2,r2,-13212 + 1010f80: 10c00015 stw r3,0(r2) + 1010f84: e0bff617 ldw r2,-40(fp) + 1010f88: e0bff415 stw r2,-48(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1010f8c: e0bff417 ldw r2,-48(fp) + 1010f90: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); + if (pmem == (OS_MEM *)0) { /* See if we have a memory partition */ + 1010f94: e0bffa17 ldw r2,-24(fp) + 1010f98: 1004c03a cmpne r2,r2,zero + 1010f9c: 1000051e bne r2,zero,1010fb4 + *perr = OS_ERR_MEM_INVALID_PART; + 1010fa0: e0fffe17 ldw r3,-8(fp) + 1010fa4: 00801684 movi r2,90 + 1010fa8: 18800005 stb r2,0(r3) + return ((OS_MEM *)0); + 1010fac: e03fff15 stw zero,-4(fp) + 1010fb0: 00002f06 br 1011070 + } + plink = (void **)addr; /* Create linked list of free memory blocks */ + 1010fb4: e0bffb17 ldw r2,-20(fp) + 1010fb8: e0bff815 stw r2,-32(fp) + pblk = (INT8U *)((INT32U)addr + blksize); + 1010fbc: e0bffb17 ldw r2,-20(fp) + 1010fc0: 1007883a mov r3,r2 + 1010fc4: e0bffd17 ldw r2,-12(fp) + 1010fc8: 1885883a add r2,r3,r2 + 1010fcc: e0bff915 stw r2,-28(fp) + for (i = 0; i < (nblks - 1); i++) { + 1010fd0: e03ff715 stw zero,-36(fp) + 1010fd4: 00000d06 br 101100c + *plink = (void *)pblk; /* Save pointer to NEXT block in CURRENT block */ + 1010fd8: e0fff817 ldw r3,-32(fp) + 1010fdc: e0bff917 ldw r2,-28(fp) + 1010fe0: 18800015 stw r2,0(r3) + plink = (void **)pblk; /* Position to NEXT block */ + 1010fe4: e0bff917 ldw r2,-28(fp) + 1010fe8: e0bff815 stw r2,-32(fp) + pblk = (INT8U *)((INT32U)pblk + blksize); /* Point to the FOLLOWING block */ + 1010fec: e0bff917 ldw r2,-28(fp) + 1010ff0: 1007883a mov r3,r2 + 1010ff4: e0bffd17 ldw r2,-12(fp) + 1010ff8: 1885883a add r2,r3,r2 + 1010ffc: e0bff915 stw r2,-28(fp) + *perr = OS_ERR_MEM_INVALID_PART; + return ((OS_MEM *)0); + } + plink = (void **)addr; /* Create linked list of free memory blocks */ + pblk = (INT8U *)((INT32U)addr + blksize); + for (i = 0; i < (nblks - 1); i++) { + 1011000: e0bff717 ldw r2,-36(fp) + 1011004: 10800044 addi r2,r2,1 + 1011008: e0bff715 stw r2,-36(fp) + 101100c: e0bffc17 ldw r2,-16(fp) + 1011010: 10ffffc4 addi r3,r2,-1 + 1011014: e0bff717 ldw r2,-36(fp) + 1011018: 10ffef36 bltu r2,r3,1010fd8 + *plink = (void *)pblk; /* Save pointer to NEXT block in CURRENT block */ + plink = (void **)pblk; /* Position to NEXT block */ + pblk = (INT8U *)((INT32U)pblk + blksize); /* Point to the FOLLOWING block */ + } + *plink = (void *)0; /* Last memory block points to NULL */ + 101101c: e0bff817 ldw r2,-32(fp) + 1011020: 10000015 stw zero,0(r2) + pmem->OSMemAddr = addr; /* Store start address of memory partition */ + 1011024: e0fffa17 ldw r3,-24(fp) + 1011028: e0bffb17 ldw r2,-20(fp) + 101102c: 18800015 stw r2,0(r3) + pmem->OSMemFreeList = addr; /* Initialize pointer to pool of free blocks */ + 1011030: e0fffa17 ldw r3,-24(fp) + 1011034: e0bffb17 ldw r2,-20(fp) + 1011038: 18800115 stw r2,4(r3) + pmem->OSMemNFree = nblks; /* Store number of free blocks in MCB */ + 101103c: e0fffa17 ldw r3,-24(fp) + 1011040: e0bffc17 ldw r2,-16(fp) + 1011044: 18800415 stw r2,16(r3) + pmem->OSMemNBlks = nblks; + 1011048: e0fffa17 ldw r3,-24(fp) + 101104c: e0bffc17 ldw r2,-16(fp) + 1011050: 18800315 stw r2,12(r3) + pmem->OSMemBlkSize = blksize; /* Store block size of each memory blocks */ + 1011054: e0fffa17 ldw r3,-24(fp) + 1011058: e0bffd17 ldw r2,-12(fp) + 101105c: 18800215 stw r2,8(r3) + *perr = OS_ERR_NONE; + 1011060: e0bffe17 ldw r2,-8(fp) + 1011064: 10000005 stb zero,0(r2) + return (pmem); + 1011068: e0bffa17 ldw r2,-24(fp) + 101106c: e0bfff15 stw r2,-4(fp) + 1011070: e0bfff17 ldw r2,-4(fp) +} + 1011074: e037883a mov sp,fp + 1011078: df000017 ldw fp,0(sp) + 101107c: dec00104 addi sp,sp,4 + 1011080: f800283a ret + +01011084 : +* A pointer to NULL if an error is detected +********************************************************************************************************* +*/ + +void *OSMemGet (OS_MEM *pmem, INT8U *perr) +{ + 1011084: defff704 addi sp,sp,-36 + 1011088: df000815 stw fp,32(sp) + 101108c: df000804 addi fp,sp,32 + 1011090: e13ffd15 stw r4,-12(fp) + 1011094: e17ffe15 stw r5,-8(fp) + void *pblk; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 1011098: e03ffb15 stw zero,-20(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + 101109c: e0bffe17 ldw r2,-8(fp) + 10110a0: 1004c03a cmpne r2,r2,zero + 10110a4: 1000021e bne r2,zero,10110b0 + return ((void *)0); + 10110a8: e03fff15 stw zero,-4(fp) + 10110ac: 00003106 br 1011174 + } + if (pmem == (OS_MEM *)0) { /* Must point to a valid memory partition */ + 10110b0: e0bffd17 ldw r2,-12(fp) + 10110b4: 1004c03a cmpne r2,r2,zero + 10110b8: 1000051e bne r2,zero,10110d0 + *perr = OS_ERR_MEM_INVALID_PMEM; + 10110bc: e0fffe17 ldw r3,-8(fp) + 10110c0: 00801804 movi r2,96 + 10110c4: 18800005 stb r2,0(r3) + return ((void *)0); + 10110c8: e03fff15 stw zero,-4(fp) + 10110cc: 00002906 br 1011174 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 10110d0: 0005303a rdctl r2,status + 10110d4: e0bffa15 stw r2,-24(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 10110d8: e0fffa17 ldw r3,-24(fp) + 10110dc: 00bfff84 movi r2,-2 + 10110e0: 1884703a and r2,r3,r2 + 10110e4: 1001703a wrctl status,r2 + + return context; + 10110e8: e0bffa17 ldw r2,-24(fp) + } +#endif + OS_ENTER_CRITICAL(); + 10110ec: e0bffb15 stw r2,-20(fp) + if (pmem->OSMemNFree > 0) { /* See if there are any free memory blocks */ + 10110f0: e0bffd17 ldw r2,-12(fp) + 10110f4: 10800417 ldw r2,16(r2) + 10110f8: 1005003a cmpeq r2,r2,zero + 10110fc: 1000151e bne r2,zero,1011154 + pblk = pmem->OSMemFreeList; /* Yes, point to next free memory block */ + 1011100: e0bffd17 ldw r2,-12(fp) + 1011104: 10800117 ldw r2,4(r2) + 1011108: e0bffc15 stw r2,-16(fp) + pmem->OSMemFreeList = *(void **)pblk; /* Adjust pointer to new free list */ + 101110c: e0bffc17 ldw r2,-16(fp) + 1011110: 10c00017 ldw r3,0(r2) + 1011114: e0bffd17 ldw r2,-12(fp) + 1011118: 10c00115 stw r3,4(r2) + pmem->OSMemNFree--; /* One less memory block in this partition */ + 101111c: e0bffd17 ldw r2,-12(fp) + 1011120: 10800417 ldw r2,16(r2) + 1011124: 10ffffc4 addi r3,r2,-1 + 1011128: e0bffd17 ldw r2,-12(fp) + 101112c: 10c00415 stw r3,16(r2) + 1011130: e0bffb17 ldw r2,-20(fp) + 1011134: e0bff915 stw r2,-28(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1011138: e0bff917 ldw r2,-28(fp) + 101113c: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; /* No error */ + 1011140: e0bffe17 ldw r2,-8(fp) + 1011144: 10000005 stb zero,0(r2) + return (pblk); /* Return memory block to caller */ + 1011148: e0bffc17 ldw r2,-16(fp) + 101114c: e0bfff15 stw r2,-4(fp) + 1011150: 00000806 br 1011174 + 1011154: e0bffb17 ldw r2,-20(fp) + 1011158: e0bff815 stw r2,-32(fp) + 101115c: e0bff817 ldw r2,-32(fp) + 1011160: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); + *perr = OS_ERR_MEM_NO_FREE_BLKS; /* No, Notify caller of empty memory partition */ + 1011164: e0fffe17 ldw r3,-8(fp) + 1011168: 00801744 movi r2,93 + 101116c: 18800005 stb r2,0(r3) + return ((void *)0); /* Return NULL pointer to caller */ + 1011170: e03fff15 stw zero,-4(fp) + 1011174: e0bfff17 ldw r2,-4(fp) +} + 1011178: e037883a mov sp,fp + 101117c: df000017 ldw fp,0(sp) + 1011180: dec00104 addi sp,sp,4 + 1011184: f800283a ret + +01011188 : +********************************************************************************************************* +*/ + +#if OS_MEM_NAME_SIZE > 1 +INT8U OSMemNameGet (OS_MEM *pmem, INT8U *pname, INT8U *perr) +{ + 1011188: defff604 addi sp,sp,-40 + 101118c: dfc00915 stw ra,36(sp) + 1011190: df000815 stw fp,32(sp) + 1011194: df000804 addi fp,sp,32 + 1011198: e13ffc15 stw r4,-16(fp) + 101119c: e17ffd15 stw r5,-12(fp) + 10111a0: e1bffe15 stw r6,-8(fp) + INT8U len; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 10111a4: e03ffa15 stw zero,-24(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + 10111a8: e0bffe17 ldw r2,-8(fp) + 10111ac: 1004c03a cmpne r2,r2,zero + 10111b0: 1000021e bne r2,zero,10111bc + return (0); + 10111b4: e03fff15 stw zero,-4(fp) + 10111b8: 00003006 br 101127c + } + if (pmem == (OS_MEM *)0) { /* Is 'pmem' a NULL pointer? */ + 10111bc: e0bffc17 ldw r2,-16(fp) + 10111c0: 1004c03a cmpne r2,r2,zero + 10111c4: 1000051e bne r2,zero,10111dc + *perr = OS_ERR_MEM_INVALID_PMEM; + 10111c8: e0fffe17 ldw r3,-8(fp) + 10111cc: 00801804 movi r2,96 + 10111d0: 18800005 stb r2,0(r3) + return (0); + 10111d4: e03fff15 stw zero,-4(fp) + 10111d8: 00002806 br 101127c + } + if (pname == (INT8U *)0) { /* Is 'pname' a NULL pointer? */ + 10111dc: e0bffd17 ldw r2,-12(fp) + 10111e0: 1004c03a cmpne r2,r2,zero + 10111e4: 1000051e bne r2,zero,10111fc + *perr = OS_ERR_PNAME_NULL; + 10111e8: e0fffe17 ldw r3,-8(fp) + 10111ec: 00800304 movi r2,12 + 10111f0: 18800005 stb r2,0(r3) + return (0); + 10111f4: e03fff15 stw zero,-4(fp) + 10111f8: 00002006 br 101127c + } +#endif + if (OSIntNesting > 0) { /* See if trying to call from an ISR */ + 10111fc: 008040b4 movhi r2,258 + 1011200: 10b31e04 addi r2,r2,-13192 + 1011204: 10800003 ldbu r2,0(r2) + 1011208: 10803fcc andi r2,r2,255 + 101120c: 1005003a cmpeq r2,r2,zero + 1011210: 1000051e bne r2,zero,1011228 + *perr = OS_ERR_NAME_GET_ISR; + 1011214: e0fffe17 ldw r3,-8(fp) + 1011218: 00800444 movi r2,17 + 101121c: 18800005 stb r2,0(r3) + return (0); + 1011220: e03fff15 stw zero,-4(fp) + 1011224: 00001506 br 101127c +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1011228: 0005303a rdctl r2,status + 101122c: e0bff915 stw r2,-28(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1011230: e0fff917 ldw r3,-28(fp) + 1011234: 00bfff84 movi r2,-2 + 1011238: 1884703a and r2,r3,r2 + 101123c: 1001703a wrctl status,r2 + + return context; + 1011240: e0bff917 ldw r2,-28(fp) + } + OS_ENTER_CRITICAL(); + 1011244: e0bffa15 stw r2,-24(fp) + len = OS_StrCopy(pname, pmem->OSMemName); /* Copy name from OS_MEM */ + 1011248: e0bffc17 ldw r2,-16(fp) + 101124c: 11400504 addi r5,r2,20 + 1011250: e13ffd17 ldw r4,-12(fp) + 1011254: 100edfc0 call 100edfc + 1011258: e0bffb05 stb r2,-20(fp) + 101125c: e0bffa17 ldw r2,-24(fp) + 1011260: e0bff815 stw r2,-32(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1011264: e0bff817 ldw r2,-32(fp) + 1011268: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + 101126c: e0bffe17 ldw r2,-8(fp) + 1011270: 10000005 stb zero,0(r2) + return (len); + 1011274: e0bffb03 ldbu r2,-20(fp) + 1011278: e0bfff15 stw r2,-4(fp) + 101127c: e0bfff17 ldw r2,-4(fp) +} + 1011280: e037883a mov sp,fp + 1011284: dfc00117 ldw ra,4(sp) + 1011288: df000017 ldw fp,0(sp) + 101128c: dec00204 addi sp,sp,8 + 1011290: f800283a ret + +01011294 : +********************************************************************************************************* +*/ + +#if OS_MEM_NAME_SIZE > 1 +void OSMemNameSet (OS_MEM *pmem, INT8U *pname, INT8U *perr) +{ + 1011294: defff604 addi sp,sp,-40 + 1011298: dfc00915 stw ra,36(sp) + 101129c: df000815 stw fp,32(sp) + 10112a0: df000804 addi fp,sp,32 + 10112a4: e13ffd15 stw r4,-12(fp) + 10112a8: e17ffe15 stw r5,-8(fp) + 10112ac: e1bfff15 stw r6,-4(fp) + INT8U len; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 10112b0: e03ffb15 stw zero,-20(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + 10112b4: e0bfff17 ldw r2,-4(fp) + 10112b8: 1005003a cmpeq r2,r2,zero + 10112bc: 1000381e bne r2,zero,10113a0 + return; + } + if (pmem == (OS_MEM *)0) { /* Is 'pmem' a NULL pointer? */ + 10112c0: e0bffd17 ldw r2,-12(fp) + 10112c4: 1004c03a cmpne r2,r2,zero + 10112c8: 1000041e bne r2,zero,10112dc + *perr = OS_ERR_MEM_INVALID_PMEM; + 10112cc: e0ffff17 ldw r3,-4(fp) + 10112d0: 00801804 movi r2,96 + 10112d4: 18800005 stb r2,0(r3) + return; + 10112d8: 00003106 br 10113a0 + } + if (pname == (INT8U *)0) { /* Is 'pname' a NULL pointer? */ + 10112dc: e0bffe17 ldw r2,-8(fp) + 10112e0: 1004c03a cmpne r2,r2,zero + 10112e4: 1000041e bne r2,zero,10112f8 + *perr = OS_ERR_PNAME_NULL; + 10112e8: e0ffff17 ldw r3,-4(fp) + 10112ec: 00800304 movi r2,12 + 10112f0: 18800005 stb r2,0(r3) + return; + 10112f4: 00002a06 br 10113a0 + } +#endif + if (OSIntNesting > 0) { /* See if trying to call from an ISR */ + 10112f8: 008040b4 movhi r2,258 + 10112fc: 10b31e04 addi r2,r2,-13192 + 1011300: 10800003 ldbu r2,0(r2) + 1011304: 10803fcc andi r2,r2,255 + 1011308: 1005003a cmpeq r2,r2,zero + 101130c: 1000041e bne r2,zero,1011320 + *perr = OS_ERR_NAME_SET_ISR; + 1011310: e0ffff17 ldw r3,-4(fp) + 1011314: 00800484 movi r2,18 + 1011318: 18800005 stb r2,0(r3) + return; + 101131c: 00002006 br 10113a0 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1011320: 0005303a rdctl r2,status + 1011324: e0bffa15 stw r2,-24(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1011328: e0fffa17 ldw r3,-24(fp) + 101132c: 00bfff84 movi r2,-2 + 1011330: 1884703a and r2,r3,r2 + 1011334: 1001703a wrctl status,r2 + + return context; + 1011338: e0bffa17 ldw r2,-24(fp) + } + OS_ENTER_CRITICAL(); + 101133c: e0bffb15 stw r2,-20(fp) + len = OS_StrLen(pname); /* Can we fit the string in the storage area? */ + 1011340: e13ffe17 ldw r4,-8(fp) + 1011344: 100ee7c0 call 100ee7c + 1011348: e0bffc05 stb r2,-16(fp) + if (len > (OS_MEM_NAME_SIZE - 1)) { /* No */ + 101134c: e0bffc03 ldbu r2,-16(fp) + 1011350: 10800830 cmpltui r2,r2,32 + 1011354: 1000081e bne r2,zero,1011378 + 1011358: e0bffb17 ldw r2,-20(fp) + 101135c: e0bff915 stw r2,-28(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1011360: e0bff917 ldw r2,-28(fp) + 1011364: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + *perr = OS_ERR_MEM_NAME_TOO_LONG; + 1011368: e0ffff17 ldw r3,-4(fp) + 101136c: 008018c4 movi r2,99 + 1011370: 18800005 stb r2,0(r3) + return; + 1011374: 00000a06 br 10113a0 + } + (void)OS_StrCopy(pmem->OSMemName, pname); /* Yes, copy name to the memory partition header */ + 1011378: e0bffd17 ldw r2,-12(fp) + 101137c: 11000504 addi r4,r2,20 + 1011380: e17ffe17 ldw r5,-8(fp) + 1011384: 100edfc0 call 100edfc + 1011388: e0bffb17 ldw r2,-20(fp) + 101138c: e0bff815 stw r2,-32(fp) + 1011390: e0bff817 ldw r2,-32(fp) + 1011394: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + 1011398: e0bfff17 ldw r2,-4(fp) + 101139c: 10000005 stb zero,0(r2) +} + 10113a0: e037883a mov sp,fp + 10113a4: dfc00117 ldw ra,4(sp) + 10113a8: df000017 ldw fp,0(sp) + 10113ac: dec00204 addi sp,sp,8 + 10113b0: f800283a ret + +010113b4 : +* OS_ERR_MEM_INVALID_PBLK if you passed a NULL pointer for the block to release. +********************************************************************************************************* +*/ + +INT8U OSMemPut (OS_MEM *pmem, void *pblk) +{ + 10113b4: defff804 addi sp,sp,-32 + 10113b8: df000715 stw fp,28(sp) + 10113bc: df000704 addi fp,sp,28 + 10113c0: e13ffd15 stw r4,-12(fp) + 10113c4: e17ffe15 stw r5,-8(fp) +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 10113c8: e03ffc15 stw zero,-16(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (pmem == (OS_MEM *)0) { /* Must point to a valid memory partition */ + 10113cc: e0bffd17 ldw r2,-12(fp) + 10113d0: 1004c03a cmpne r2,r2,zero + 10113d4: 1000031e bne r2,zero,10113e4 + return (OS_ERR_MEM_INVALID_PMEM); + 10113d8: 00801804 movi r2,96 + 10113dc: e0bfff15 stw r2,-4(fp) + 10113e0: 00002b06 br 1011490 + } + if (pblk == (void *)0) { /* Must release a valid block */ + 10113e4: e0bffe17 ldw r2,-8(fp) + 10113e8: 1004c03a cmpne r2,r2,zero + 10113ec: 1000031e bne r2,zero,10113fc + return (OS_ERR_MEM_INVALID_PBLK); + 10113f0: 008017c4 movi r2,95 + 10113f4: e0bfff15 stw r2,-4(fp) + 10113f8: 00002506 br 1011490 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 10113fc: 0005303a rdctl r2,status + 1011400: e0bffb15 stw r2,-20(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1011404: e0fffb17 ldw r3,-20(fp) + 1011408: 00bfff84 movi r2,-2 + 101140c: 1884703a and r2,r3,r2 + 1011410: 1001703a wrctl status,r2 + + return context; + 1011414: e0bffb17 ldw r2,-20(fp) + } +#endif + OS_ENTER_CRITICAL(); + 1011418: e0bffc15 stw r2,-16(fp) + if (pmem->OSMemNFree >= pmem->OSMemNBlks) { /* Make sure all blocks not already returned */ + 101141c: e0bffd17 ldw r2,-12(fp) + 1011420: 10c00417 ldw r3,16(r2) + 1011424: e0bffd17 ldw r2,-12(fp) + 1011428: 10800317 ldw r2,12(r2) + 101142c: 18800736 bltu r3,r2,101144c + 1011430: e0bffc17 ldw r2,-16(fp) + 1011434: e0bffa15 stw r2,-24(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1011438: e0bffa17 ldw r2,-24(fp) + 101143c: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_MEM_FULL); + 1011440: 00801784 movi r2,94 + 1011444: e0bfff15 stw r2,-4(fp) + 1011448: 00001106 br 1011490 + } + *(void **)pblk = pmem->OSMemFreeList; /* Insert released block into free block list */ + 101144c: e0fffe17 ldw r3,-8(fp) + 1011450: e0bffd17 ldw r2,-12(fp) + 1011454: 10800117 ldw r2,4(r2) + 1011458: 18800015 stw r2,0(r3) + pmem->OSMemFreeList = pblk; + 101145c: e0fffd17 ldw r3,-12(fp) + 1011460: e0bffe17 ldw r2,-8(fp) + 1011464: 18800115 stw r2,4(r3) + pmem->OSMemNFree++; /* One more memory block in this partition */ + 1011468: e0bffd17 ldw r2,-12(fp) + 101146c: 10800417 ldw r2,16(r2) + 1011470: 10c00044 addi r3,r2,1 + 1011474: e0bffd17 ldw r2,-12(fp) + 1011478: 10c00415 stw r3,16(r2) + 101147c: e0bffc17 ldw r2,-16(fp) + 1011480: e0bff915 stw r2,-28(fp) + 1011484: e0bff917 ldw r2,-28(fp) + 1011488: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_NONE); /* Notify caller that memory block was released */ + 101148c: e03fff15 stw zero,-4(fp) + 1011490: e0bfff17 ldw r2,-4(fp) +} + 1011494: e037883a mov sp,fp + 1011498: df000017 ldw fp,0(sp) + 101149c: dec00104 addi sp,sp,4 + 10114a0: f800283a ret + +010114a4 : +********************************************************************************************************* +*/ + +#if OS_MEM_QUERY_EN > 0 +INT8U OSMemQuery (OS_MEM *pmem, OS_MEM_DATA *p_mem_data) +{ + 10114a4: defff904 addi sp,sp,-28 + 10114a8: df000615 stw fp,24(sp) + 10114ac: df000604 addi fp,sp,24 + 10114b0: e13ffd15 stw r4,-12(fp) + 10114b4: e17ffe15 stw r5,-8(fp) +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 10114b8: e03ffc15 stw zero,-16(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (pmem == (OS_MEM *)0) { /* Must point to a valid memory partition */ + 10114bc: e0bffd17 ldw r2,-12(fp) + 10114c0: 1004c03a cmpne r2,r2,zero + 10114c4: 1000031e bne r2,zero,10114d4 + return (OS_ERR_MEM_INVALID_PMEM); + 10114c8: 00801804 movi r2,96 + 10114cc: e0bfff15 stw r2,-4(fp) + 10114d0: 00002e06 br 101158c + } + if (p_mem_data == (OS_MEM_DATA *)0) { /* Must release a valid storage area for the data */ + 10114d4: e0bffe17 ldw r2,-8(fp) + 10114d8: 1004c03a cmpne r2,r2,zero + 10114dc: 1000031e bne r2,zero,10114ec + return (OS_ERR_MEM_INVALID_PDATA); + 10114e0: 00801844 movi r2,97 + 10114e4: e0bfff15 stw r2,-4(fp) + 10114e8: 00002806 br 101158c +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 10114ec: 0005303a rdctl r2,status + 10114f0: e0bffb15 stw r2,-20(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 10114f4: e0fffb17 ldw r3,-20(fp) + 10114f8: 00bfff84 movi r2,-2 + 10114fc: 1884703a and r2,r3,r2 + 1011500: 1001703a wrctl status,r2 + + return context; + 1011504: e0bffb17 ldw r2,-20(fp) + } +#endif + OS_ENTER_CRITICAL(); + 1011508: e0bffc15 stw r2,-16(fp) + p_mem_data->OSAddr = pmem->OSMemAddr; + 101150c: e0bffd17 ldw r2,-12(fp) + 1011510: 10c00017 ldw r3,0(r2) + 1011514: e0bffe17 ldw r2,-8(fp) + 1011518: 10c00015 stw r3,0(r2) + p_mem_data->OSFreeList = pmem->OSMemFreeList; + 101151c: e0bffd17 ldw r2,-12(fp) + 1011520: 10c00117 ldw r3,4(r2) + 1011524: e0bffe17 ldw r2,-8(fp) + 1011528: 10c00115 stw r3,4(r2) + p_mem_data->OSBlkSize = pmem->OSMemBlkSize; + 101152c: e0bffd17 ldw r2,-12(fp) + 1011530: 10c00217 ldw r3,8(r2) + 1011534: e0bffe17 ldw r2,-8(fp) + 1011538: 10c00215 stw r3,8(r2) + p_mem_data->OSNBlks = pmem->OSMemNBlks; + 101153c: e0bffd17 ldw r2,-12(fp) + 1011540: 10c00317 ldw r3,12(r2) + 1011544: e0bffe17 ldw r2,-8(fp) + 1011548: 10c00315 stw r3,12(r2) + p_mem_data->OSNFree = pmem->OSMemNFree; + 101154c: e0bffd17 ldw r2,-12(fp) + 1011550: 10c00417 ldw r3,16(r2) + 1011554: e0bffe17 ldw r2,-8(fp) + 1011558: 10c00415 stw r3,16(r2) + 101155c: e0bffc17 ldw r2,-16(fp) + 1011560: e0bffa15 stw r2,-24(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1011564: e0bffa17 ldw r2,-24(fp) + 1011568: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + p_mem_data->OSNUsed = p_mem_data->OSNBlks - p_mem_data->OSNFree; + 101156c: e0bffe17 ldw r2,-8(fp) + 1011570: 10c00317 ldw r3,12(r2) + 1011574: e0bffe17 ldw r2,-8(fp) + 1011578: 10800417 ldw r2,16(r2) + 101157c: 1887c83a sub r3,r3,r2 + 1011580: e0bffe17 ldw r2,-8(fp) + 1011584: 10c00515 stw r3,20(r2) + return (OS_ERR_NONE); + 1011588: e03fff15 stw zero,-4(fp) + 101158c: e0bfff17 ldw r2,-4(fp) +} + 1011590: e037883a mov sp,fp + 1011594: df000017 ldw fp,0(sp) + 1011598: dec00104 addi sp,sp,4 + 101159c: f800283a ret + +010115a0 : +* Note(s) : This function is INTERNAL to uC/OS-II and your application should not call it. +********************************************************************************************************* +*/ + +void OS_MemInit (void) +{ + 10115a0: defffc04 addi sp,sp,-16 + 10115a4: dfc00315 stw ra,12(sp) + 10115a8: df000215 stw fp,8(sp) + 10115ac: df000204 addi fp,sp,8 +#if OS_MAX_MEM_PART >= 2 + OS_MEM *pmem; + INT16U i; + + + OS_MemClr((INT8U *)&OSMemTbl[0], sizeof(OSMemTbl)); /* Clear the memory partition table */ + 10115b0: 010040b4 movhi r4,258 + 10115b4: 210e1104 addi r4,r4,14404 + 10115b8: 01430c04 movi r5,3120 + 10115bc: 100ebf80 call 100ebf8 + pmem = &OSMemTbl[0]; /* Point to memory control block (MCB) */ + 10115c0: 008040b4 movhi r2,258 + 10115c4: 108e1104 addi r2,r2,14404 + 10115c8: e0bfff15 stw r2,-4(fp) + for (i = 0; i < (OS_MAX_MEM_PART - 1); i++) { /* Init. list of free memory partitions */ + 10115cc: e03ffe0d sth zero,-8(fp) + 10115d0: 00001306 br 1011620 + pmem->OSMemFreeList = (void *)&OSMemTbl[i+1]; /* Chain list of free partitions */ + 10115d4: e0bffe0b ldhu r2,-8(fp) + 10115d8: 10800d24 muli r2,r2,52 + 10115dc: 1007883a mov r3,r2 + 10115e0: 008040b4 movhi r2,258 + 10115e4: 108e1e04 addi r2,r2,14456 + 10115e8: 1887883a add r3,r3,r2 + 10115ec: e0bfff17 ldw r2,-4(fp) + 10115f0: 10c00115 stw r3,4(r2) +#if OS_MEM_NAME_SIZE > 1 + pmem->OSMemName[0] = '?'; /* Unknown name */ + 10115f4: e0ffff17 ldw r3,-4(fp) + 10115f8: 00800fc4 movi r2,63 + 10115fc: 18800505 stb r2,20(r3) + pmem->OSMemName[1] = OS_ASCII_NUL; + 1011600: e0bfff17 ldw r2,-4(fp) + 1011604: 10000545 stb zero,21(r2) +#endif + pmem++; + 1011608: e0bfff17 ldw r2,-4(fp) + 101160c: 10800d04 addi r2,r2,52 + 1011610: e0bfff15 stw r2,-4(fp) + INT16U i; + + + OS_MemClr((INT8U *)&OSMemTbl[0], sizeof(OSMemTbl)); /* Clear the memory partition table */ + pmem = &OSMemTbl[0]; /* Point to memory control block (MCB) */ + for (i = 0; i < (OS_MAX_MEM_PART - 1); i++) { /* Init. list of free memory partitions */ + 1011614: e0bffe0b ldhu r2,-8(fp) + 1011618: 10800044 addi r2,r2,1 + 101161c: e0bffe0d sth r2,-8(fp) + 1011620: e0bffe0b ldhu r2,-8(fp) + 1011624: 10800ef0 cmpltui r2,r2,59 + 1011628: 103fea1e bne r2,zero,10115d4 + pmem->OSMemName[0] = '?'; /* Unknown name */ + pmem->OSMemName[1] = OS_ASCII_NUL; +#endif + pmem++; + } + pmem->OSMemFreeList = (void *)0; /* Initialize last node */ + 101162c: e0bfff17 ldw r2,-4(fp) + 1011630: 10000115 stw zero,4(r2) +#if OS_MEM_NAME_SIZE > 1 + pmem->OSMemName[0] = '?'; /* Unknown name */ + 1011634: e0ffff17 ldw r3,-4(fp) + 1011638: 00800fc4 movi r2,63 + 101163c: 18800505 stb r2,20(r3) + pmem->OSMemName[1] = OS_ASCII_NUL; + 1011640: e0bfff17 ldw r2,-4(fp) + 1011644: 10000545 stb zero,21(r2) +#endif + + OSMemFreeList = &OSMemTbl[0]; /* Point to beginning of free list */ + 1011648: 00c040b4 movhi r3,258 + 101164c: 18f31904 addi r3,r3,-13212 + 1011650: 008040b4 movhi r2,258 + 1011654: 108e1104 addi r2,r2,14404 + 1011658: 18800015 stw r2,0(r3) +#endif +} + 101165c: e037883a mov sp,fp + 1011660: dfc00117 ldw ra,4(sp) + 1011664: df000017 ldw fp,0(sp) + 1011668: dec00204 addi sp,sp,8 + 101166c: f800283a ret + +01011670 : +********************************************************************************************************* +*/ + +#if OS_Q_ACCEPT_EN > 0 +void *OSQAccept (OS_EVENT *pevent, INT8U *perr) +{ + 1011670: defff704 addi sp,sp,-36 + 1011674: df000815 stw fp,32(sp) + 1011678: df000804 addi fp,sp,32 + 101167c: e13ffd15 stw r4,-12(fp) + 1011680: e17ffe15 stw r5,-8(fp) + void *pmsg; + OS_Q *pq; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 1011684: e03ffa15 stw zero,-24(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + 1011688: e0bffe17 ldw r2,-8(fp) + 101168c: 1004c03a cmpne r2,r2,zero + 1011690: 1000021e bne r2,zero,101169c + return ((void *)0); + 1011694: e03fff15 stw zero,-4(fp) + 1011698: 00004506 br 10117b0 + } + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + 101169c: e0bffd17 ldw r2,-12(fp) + 10116a0: 1004c03a cmpne r2,r2,zero + 10116a4: 1000051e bne r2,zero,10116bc + *perr = OS_ERR_PEVENT_NULL; + 10116a8: e0fffe17 ldw r3,-8(fp) + 10116ac: 00800104 movi r2,4 + 10116b0: 18800005 stb r2,0(r3) + return ((void *)0); + 10116b4: e03fff15 stw zero,-4(fp) + 10116b8: 00003d06 br 10117b0 + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_Q) {/* Validate event block type */ + 10116bc: e0bffd17 ldw r2,-12(fp) + 10116c0: 10800003 ldbu r2,0(r2) + 10116c4: 10803fcc andi r2,r2,255 + 10116c8: 108000a0 cmpeqi r2,r2,2 + 10116cc: 1000051e bne r2,zero,10116e4 + *perr = OS_ERR_EVENT_TYPE; + 10116d0: e0fffe17 ldw r3,-8(fp) + 10116d4: 00800044 movi r2,1 + 10116d8: 18800005 stb r2,0(r3) + return ((void *)0); + 10116dc: e03fff15 stw zero,-4(fp) + 10116e0: 00003306 br 10117b0 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 10116e4: 0005303a rdctl r2,status + 10116e8: e0bff915 stw r2,-28(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 10116ec: e0fff917 ldw r3,-28(fp) + 10116f0: 00bfff84 movi r2,-2 + 10116f4: 1884703a and r2,r3,r2 + 10116f8: 1001703a wrctl status,r2 + + return context; + 10116fc: e0bff917 ldw r2,-28(fp) + } + OS_ENTER_CRITICAL(); + 1011700: e0bffa15 stw r2,-24(fp) + pq = (OS_Q *)pevent->OSEventPtr; /* Point at queue control block */ + 1011704: e0bffd17 ldw r2,-12(fp) + 1011708: 10800117 ldw r2,4(r2) + 101170c: e0bffb15 stw r2,-20(fp) + if (pq->OSQEntries > 0) { /* See if any messages in the queue */ + 1011710: e0bffb17 ldw r2,-20(fp) + 1011714: 1080058b ldhu r2,22(r2) + 1011718: 10bfffcc andi r2,r2,65535 + 101171c: 1005003a cmpeq r2,r2,zero + 1011720: 1000191e bne r2,zero,1011788 + pmsg = *pq->OSQOut++; /* Yes, extract oldest message from the queue */ + 1011724: e0bffb17 ldw r2,-20(fp) + 1011728: 10c00417 ldw r3,16(r2) + 101172c: 18800017 ldw r2,0(r3) + 1011730: e0bffc15 stw r2,-16(fp) + 1011734: 18c00104 addi r3,r3,4 + 1011738: e0bffb17 ldw r2,-20(fp) + 101173c: 10c00415 stw r3,16(r2) + pq->OSQEntries--; /* Update the number of entries in the queue */ + 1011740: e0bffb17 ldw r2,-20(fp) + 1011744: 1080058b ldhu r2,22(r2) + 1011748: 10bfffc4 addi r2,r2,-1 + 101174c: 1007883a mov r3,r2 + 1011750: e0bffb17 ldw r2,-20(fp) + 1011754: 10c0058d sth r3,22(r2) + if (pq->OSQOut == pq->OSQEnd) { /* Wrap OUT pointer if we are at the end of the queue */ + 1011758: e0bffb17 ldw r2,-20(fp) + 101175c: 10c00417 ldw r3,16(r2) + 1011760: e0bffb17 ldw r2,-20(fp) + 1011764: 10800217 ldw r2,8(r2) + 1011768: 1880041e bne r3,r2,101177c + pq->OSQOut = pq->OSQStart; + 101176c: e0bffb17 ldw r2,-20(fp) + 1011770: 10c00117 ldw r3,4(r2) + 1011774: e0bffb17 ldw r2,-20(fp) + 1011778: 10c00415 stw r3,16(r2) + } + *perr = OS_ERR_NONE; + 101177c: e0bffe17 ldw r2,-8(fp) + 1011780: 10000005 stb zero,0(r2) + 1011784: 00000406 br 1011798 + } else { + *perr = OS_ERR_Q_EMPTY; + 1011788: e0fffe17 ldw r3,-8(fp) + 101178c: 008007c4 movi r2,31 + 1011790: 18800005 stb r2,0(r3) + pmsg = (void *)0; /* Queue is empty */ + 1011794: e03ffc15 stw zero,-16(fp) + 1011798: e0bffa17 ldw r2,-24(fp) + 101179c: e0bff815 stw r2,-32(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 10117a0: e0bff817 ldw r2,-32(fp) + 10117a4: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); + return (pmsg); /* Return message received (or NULL) */ + 10117a8: e0bffc17 ldw r2,-16(fp) + 10117ac: e0bfff15 stw r2,-4(fp) + 10117b0: e0bfff17 ldw r2,-4(fp) +} + 10117b4: e037883a mov sp,fp + 10117b8: df000017 ldw fp,0(sp) + 10117bc: dec00104 addi sp,sp,4 + 10117c0: f800283a ret + +010117c4 : +* == (OS_EVENT *)0 if no event control blocks were available or an error was detected +********************************************************************************************************* +*/ + +OS_EVENT *OSQCreate (void **start, INT16U size) +{ + 10117c4: defff304 addi sp,sp,-52 + 10117c8: dfc00c15 stw ra,48(sp) + 10117cc: df000b15 stw fp,44(sp) + 10117d0: df000b04 addi fp,sp,44 + 10117d4: e13ffd15 stw r4,-12(fp) + 10117d8: e17ffe0d sth r5,-8(fp) + OS_EVENT *pevent; + OS_Q *pq; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 10117dc: e03ffa15 stw zero,-24(fp) +#endif + + + + if (OSIntNesting > 0) { /* See if called from ISR ... */ + 10117e0: 008040b4 movhi r2,258 + 10117e4: 10b31e04 addi r2,r2,-13192 + 10117e8: 10800003 ldbu r2,0(r2) + 10117ec: 10803fcc andi r2,r2,255 + 10117f0: 1005003a cmpeq r2,r2,zero + 10117f4: 1000021e bne r2,zero,1011800 + return ((OS_EVENT *)0); /* ... can't CREATE from an ISR */ + 10117f8: e03fff15 stw zero,-4(fp) + 10117fc: 00007006 br 10119c0 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1011800: 0005303a rdctl r2,status + 1011804: e0bff915 stw r2,-28(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1011808: e0fff917 ldw r3,-28(fp) + 101180c: 00bfff84 movi r2,-2 + 1011810: 1884703a and r2,r3,r2 + 1011814: 1001703a wrctl status,r2 + + return context; + 1011818: e0bff917 ldw r2,-28(fp) + } + OS_ENTER_CRITICAL(); + 101181c: e0bffa15 stw r2,-24(fp) + pevent = OSEventFreeList; /* Get next free event control block */ + 1011820: 008040b4 movhi r2,258 + 1011824: 10b31d04 addi r2,r2,-13196 + 1011828: 10800017 ldw r2,0(r2) + 101182c: e0bffc15 stw r2,-16(fp) + if (OSEventFreeList != (OS_EVENT *)0) { /* See if pool of free ECB pool was empty */ + 1011830: 008040b4 movhi r2,258 + 1011834: 10b31d04 addi r2,r2,-13196 + 1011838: 10800017 ldw r2,0(r2) + 101183c: 1005003a cmpeq r2,r2,zero + 1011840: 1000081e bne r2,zero,1011864 + OSEventFreeList = (OS_EVENT *)OSEventFreeList->OSEventPtr; + 1011844: 008040b4 movhi r2,258 + 1011848: 10b31d04 addi r2,r2,-13196 + 101184c: 10800017 ldw r2,0(r2) + 1011850: 10800117 ldw r2,4(r2) + 1011854: 1007883a mov r3,r2 + 1011858: 008040b4 movhi r2,258 + 101185c: 10b31d04 addi r2,r2,-13196 + 1011860: 10c00015 stw r3,0(r2) + 1011864: e0bffa17 ldw r2,-24(fp) + 1011868: e0bff815 stw r2,-32(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 101186c: e0bff817 ldw r2,-32(fp) + 1011870: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); + if (pevent != (OS_EVENT *)0) { /* See if we have an event control block */ + 1011874: e0bffc17 ldw r2,-16(fp) + 1011878: 1005003a cmpeq r2,r2,zero + 101187c: 10004e1e bne r2,zero,10119b8 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1011880: 0005303a rdctl r2,status + 1011884: e0bff715 stw r2,-36(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1011888: e0fff717 ldw r3,-36(fp) + 101188c: 00bfff84 movi r2,-2 + 1011890: 1884703a and r2,r3,r2 + 1011894: 1001703a wrctl status,r2 + + return context; + 1011898: e0bff717 ldw r2,-36(fp) + OS_ENTER_CRITICAL(); + 101189c: e0bffa15 stw r2,-24(fp) + pq = OSQFreeList; /* Get a free queue control block */ + 10118a0: 008040b4 movhi r2,258 + 10118a4: 10b31b04 addi r2,r2,-13204 + 10118a8: 10800017 ldw r2,0(r2) + 10118ac: e0bffb15 stw r2,-20(fp) + if (pq != (OS_Q *)0) { /* Were we able to get a queue control block ? */ + 10118b0: e0bffb17 ldw r2,-20(fp) + 10118b4: 1005003a cmpeq r2,r2,zero + 10118b8: 1000311e bne r2,zero,1011980 + OSQFreeList = OSQFreeList->OSQPtr; /* Yes, Adjust free list pointer to next free*/ + 10118bc: 008040b4 movhi r2,258 + 10118c0: 10b31b04 addi r2,r2,-13204 + 10118c4: 10800017 ldw r2,0(r2) + 10118c8: 10c00017 ldw r3,0(r2) + 10118cc: 008040b4 movhi r2,258 + 10118d0: 10b31b04 addi r2,r2,-13204 + 10118d4: 10c00015 stw r3,0(r2) + 10118d8: e0bffa17 ldw r2,-24(fp) + 10118dc: e0bff615 stw r2,-40(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 10118e0: e0bff617 ldw r2,-40(fp) + 10118e4: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + pq->OSQStart = start; /* Initialize the queue */ + 10118e8: e0fffb17 ldw r3,-20(fp) + 10118ec: e0bffd17 ldw r2,-12(fp) + 10118f0: 18800115 stw r2,4(r3) + pq->OSQEnd = &start[size]; + 10118f4: e0bffe0b ldhu r2,-8(fp) + 10118f8: 1085883a add r2,r2,r2 + 10118fc: 1085883a add r2,r2,r2 + 1011900: 1007883a mov r3,r2 + 1011904: e0bffd17 ldw r2,-12(fp) + 1011908: 1887883a add r3,r3,r2 + 101190c: e0bffb17 ldw r2,-20(fp) + 1011910: 10c00215 stw r3,8(r2) + pq->OSQIn = start; + 1011914: e0fffb17 ldw r3,-20(fp) + 1011918: e0bffd17 ldw r2,-12(fp) + 101191c: 18800315 stw r2,12(r3) + pq->OSQOut = start; + 1011920: e0fffb17 ldw r3,-20(fp) + 1011924: e0bffd17 ldw r2,-12(fp) + 1011928: 18800415 stw r2,16(r3) + pq->OSQSize = size; + 101192c: e0fffb17 ldw r3,-20(fp) + 1011930: e0bffe0b ldhu r2,-8(fp) + 1011934: 1880050d sth r2,20(r3) + pq->OSQEntries = 0; + 1011938: e0bffb17 ldw r2,-20(fp) + 101193c: 1000058d sth zero,22(r2) + pevent->OSEventType = OS_EVENT_TYPE_Q; + 1011940: e0fffc17 ldw r3,-16(fp) + 1011944: 00800084 movi r2,2 + 1011948: 18800005 stb r2,0(r3) + pevent->OSEventCnt = 0; + 101194c: e0bffc17 ldw r2,-16(fp) + 1011950: 1000020d sth zero,8(r2) + pevent->OSEventPtr = pq; + 1011954: e0fffc17 ldw r3,-16(fp) + 1011958: e0bffb17 ldw r2,-20(fp) + 101195c: 18800115 stw r2,4(r3) +#if OS_EVENT_NAME_SIZE > 1 + pevent->OSEventName[0] = '?'; /* Unknown name */ + 1011960: e0fffc17 ldw r3,-16(fp) + 1011964: 00800fc4 movi r2,63 + 1011968: 18800385 stb r2,14(r3) + pevent->OSEventName[1] = OS_ASCII_NUL; + 101196c: e0bffc17 ldw r2,-16(fp) + 1011970: 100003c5 stb zero,15(r2) +#endif + OS_EventWaitListInit(pevent); /* Initalize the wait list */ + 1011974: e13ffc17 ldw r4,-16(fp) + 1011978: 100e82c0 call 100e82c + 101197c: 00000e06 br 10119b8 + } else { + pevent->OSEventPtr = (void *)OSEventFreeList; /* No, Return event control block on error */ + 1011980: 008040b4 movhi r2,258 + 1011984: 10b31d04 addi r2,r2,-13196 + 1011988: 10c00017 ldw r3,0(r2) + 101198c: e0bffc17 ldw r2,-16(fp) + 1011990: 10c00115 stw r3,4(r2) + OSEventFreeList = pevent; + 1011994: 00c040b4 movhi r3,258 + 1011998: 18f31d04 addi r3,r3,-13196 + 101199c: e0bffc17 ldw r2,-16(fp) + 10119a0: 18800015 stw r2,0(r3) + 10119a4: e0bffa17 ldw r2,-24(fp) + 10119a8: e0bff515 stw r2,-44(fp) + 10119ac: e0bff517 ldw r2,-44(fp) + 10119b0: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + pevent = (OS_EVENT *)0; + 10119b4: e03ffc15 stw zero,-16(fp) + } + } + return (pevent); + 10119b8: e0bffc17 ldw r2,-16(fp) + 10119bc: e0bfff15 stw r2,-4(fp) + 10119c0: e0bfff17 ldw r2,-4(fp) +} + 10119c4: e037883a mov sp,fp + 10119c8: dfc00117 ldw ra,4(sp) + 10119cc: df000017 ldw fp,0(sp) + 10119d0: dec00204 addi sp,sp,8 + 10119d4: f800283a ret + +010119d8 : +********************************************************************************************************* +*/ + +#if OS_Q_DEL_EN > 0 +OS_EVENT *OSQDel (OS_EVENT *pevent, INT8U opt, INT8U *perr) +{ + 10119d8: defff004 addi sp,sp,-64 + 10119dc: dfc00f15 stw ra,60(sp) + 10119e0: df000e15 stw fp,56(sp) + 10119e4: df000e04 addi fp,sp,56 + 10119e8: e13ffb15 stw r4,-20(fp) + 10119ec: e1bffd15 stw r6,-12(fp) + 10119f0: e17ffc05 stb r5,-16(fp) + BOOLEAN tasks_waiting; + OS_EVENT *pevent_return; + OS_Q *pq; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 10119f4: e03ff715 stw zero,-36(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + 10119f8: e0bffd17 ldw r2,-12(fp) + 10119fc: 1004c03a cmpne r2,r2,zero + 1011a00: 1000031e bne r2,zero,1011a10 + return (pevent); + 1011a04: e0bffb17 ldw r2,-20(fp) + 1011a08: e0bfff15 stw r2,-4(fp) + 1011a0c: 0000ac06 br 1011cc0 + } + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + 1011a10: e0bffb17 ldw r2,-20(fp) + 1011a14: 1004c03a cmpne r2,r2,zero + 1011a18: 1000061e bne r2,zero,1011a34 + *perr = OS_ERR_PEVENT_NULL; + 1011a1c: e0fffd17 ldw r3,-12(fp) + 1011a20: 00800104 movi r2,4 + 1011a24: 18800005 stb r2,0(r3) + return (pevent); + 1011a28: e0fffb17 ldw r3,-20(fp) + 1011a2c: e0ffff15 stw r3,-4(fp) + 1011a30: 0000a306 br 1011cc0 + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_Q) { /* Validate event block type */ + 1011a34: e0bffb17 ldw r2,-20(fp) + 1011a38: 10800003 ldbu r2,0(r2) + 1011a3c: 10803fcc andi r2,r2,255 + 1011a40: 108000a0 cmpeqi r2,r2,2 + 1011a44: 1000061e bne r2,zero,1011a60 + *perr = OS_ERR_EVENT_TYPE; + 1011a48: e0fffd17 ldw r3,-12(fp) + 1011a4c: 00800044 movi r2,1 + 1011a50: 18800005 stb r2,0(r3) + return (pevent); + 1011a54: e0bffb17 ldw r2,-20(fp) + 1011a58: e0bfff15 stw r2,-4(fp) + 1011a5c: 00009806 br 1011cc0 + } + if (OSIntNesting > 0) { /* See if called from ISR ... */ + 1011a60: 008040b4 movhi r2,258 + 1011a64: 10b31e04 addi r2,r2,-13192 + 1011a68: 10800003 ldbu r2,0(r2) + 1011a6c: 10803fcc andi r2,r2,255 + 1011a70: 1005003a cmpeq r2,r2,zero + 1011a74: 1000061e bne r2,zero,1011a90 + *perr = OS_ERR_DEL_ISR; /* ... can't DELETE from an ISR */ + 1011a78: e0fffd17 ldw r3,-12(fp) + 1011a7c: 008003c4 movi r2,15 + 1011a80: 18800005 stb r2,0(r3) + return (pevent); + 1011a84: e0fffb17 ldw r3,-20(fp) + 1011a88: e0ffff15 stw r3,-4(fp) + 1011a8c: 00008c06 br 1011cc0 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1011a90: 0005303a rdctl r2,status + 1011a94: e0bff615 stw r2,-40(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1011a98: e0fff617 ldw r3,-40(fp) + 1011a9c: 00bfff84 movi r2,-2 + 1011aa0: 1884703a and r2,r3,r2 + 1011aa4: 1001703a wrctl status,r2 + + return context; + 1011aa8: e0bff617 ldw r2,-40(fp) + } + OS_ENTER_CRITICAL(); + 1011aac: e0bff715 stw r2,-36(fp) + if (pevent->OSEventGrp != 0) { /* See if any tasks waiting on queue */ + 1011ab0: e0bffb17 ldw r2,-20(fp) + 1011ab4: 10800283 ldbu r2,10(r2) + 1011ab8: 10803fcc andi r2,r2,255 + 1011abc: 1005003a cmpeq r2,r2,zero + 1011ac0: 1000031e bne r2,zero,1011ad0 + tasks_waiting = OS_TRUE; /* Yes */ + 1011ac4: 00800044 movi r2,1 + 1011ac8: e0bffa05 stb r2,-24(fp) + 1011acc: 00000106 br 1011ad4 + } else { + tasks_waiting = OS_FALSE; /* No */ + 1011ad0: e03ffa05 stb zero,-24(fp) + } + switch (opt) { + 1011ad4: e0bffc03 ldbu r2,-16(fp) + 1011ad8: e0bffe15 stw r2,-8(fp) + 1011adc: e0fffe17 ldw r3,-8(fp) + 1011ae0: 1805003a cmpeq r2,r3,zero + 1011ae4: 1000041e bne r2,zero,1011af8 + 1011ae8: e0fffe17 ldw r3,-8(fp) + 1011aec: 18800060 cmpeqi r2,r3,1 + 1011af0: 1000391e bne r2,zero,1011bd8 + 1011af4: 00006706 br 1011c94 + case OS_DEL_NO_PEND: /* Delete queue only if no task waiting */ + if (tasks_waiting == OS_FALSE) { + 1011af8: e0bffa03 ldbu r2,-24(fp) + 1011afc: 1004c03a cmpne r2,r2,zero + 1011b00: 1000261e bne r2,zero,1011b9c +#if OS_EVENT_NAME_SIZE > 1 + pevent->OSEventName[0] = '?'; /* Unknown name */ + 1011b04: e0fffb17 ldw r3,-20(fp) + 1011b08: 00800fc4 movi r2,63 + 1011b0c: 18800385 stb r2,14(r3) + pevent->OSEventName[1] = OS_ASCII_NUL; + 1011b10: e0bffb17 ldw r2,-20(fp) + 1011b14: 100003c5 stb zero,15(r2) +#endif + pq = (OS_Q *)pevent->OSEventPtr; /* Return OS_Q to free list */ + 1011b18: e0bffb17 ldw r2,-20(fp) + 1011b1c: 10800117 ldw r2,4(r2) + 1011b20: e0bff815 stw r2,-32(fp) + pq->OSQPtr = OSQFreeList; + 1011b24: 008040b4 movhi r2,258 + 1011b28: 10b31b04 addi r2,r2,-13204 + 1011b2c: 10c00017 ldw r3,0(r2) + 1011b30: e0bff817 ldw r2,-32(fp) + 1011b34: 10c00015 stw r3,0(r2) + OSQFreeList = pq; + 1011b38: 00c040b4 movhi r3,258 + 1011b3c: 18f31b04 addi r3,r3,-13204 + 1011b40: e0bff817 ldw r2,-32(fp) + 1011b44: 18800015 stw r2,0(r3) + pevent->OSEventType = OS_EVENT_TYPE_UNUSED; + 1011b48: e0bffb17 ldw r2,-20(fp) + 1011b4c: 10000005 stb zero,0(r2) + pevent->OSEventPtr = OSEventFreeList; /* Return Event Control Block to free list */ + 1011b50: 008040b4 movhi r2,258 + 1011b54: 10b31d04 addi r2,r2,-13196 + 1011b58: 10c00017 ldw r3,0(r2) + 1011b5c: e0bffb17 ldw r2,-20(fp) + 1011b60: 10c00115 stw r3,4(r2) + pevent->OSEventCnt = 0; + 1011b64: e0bffb17 ldw r2,-20(fp) + 1011b68: 1000020d sth zero,8(r2) + OSEventFreeList = pevent; /* Get next free event control block */ + 1011b6c: 00c040b4 movhi r3,258 + 1011b70: 18f31d04 addi r3,r3,-13196 + 1011b74: e0bffb17 ldw r2,-20(fp) + 1011b78: 18800015 stw r2,0(r3) + 1011b7c: e0bff717 ldw r2,-36(fp) + 1011b80: e0bff515 stw r2,-44(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1011b84: e0bff517 ldw r2,-44(fp) + 1011b88: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + 1011b8c: e0bffd17 ldw r2,-12(fp) + 1011b90: 10000005 stb zero,0(r2) + pevent_return = (OS_EVENT *)0; /* Queue has been deleted */ + 1011b94: e03ff915 stw zero,-28(fp) + 1011b98: 00004706 br 1011cb8 + 1011b9c: e0bff717 ldw r2,-36(fp) + 1011ba0: e0bff415 stw r2,-48(fp) + 1011ba4: e0bff417 ldw r2,-48(fp) + 1011ba8: 1001703a wrctl status,r2 + } else { + OS_EXIT_CRITICAL(); + *perr = OS_ERR_TASK_WAITING; + 1011bac: e0fffd17 ldw r3,-12(fp) + 1011bb0: 00801244 movi r2,73 + 1011bb4: 18800005 stb r2,0(r3) + pevent_return = pevent; + 1011bb8: e0bffb17 ldw r2,-20(fp) + 1011bbc: e0bff915 stw r2,-28(fp) + } + break; + 1011bc0: 00003d06 br 1011cb8 + + case OS_DEL_ALWAYS: /* Always delete the queue */ + while (pevent->OSEventGrp != 0) { /* Ready ALL tasks waiting for queue */ + (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_Q, OS_STAT_PEND_OK); + 1011bc4: e13ffb17 ldw r4,-20(fp) + 1011bc8: 000b883a mov r5,zero + 1011bcc: 01800104 movi r6,4 + 1011bd0: 000f883a mov r7,zero + 1011bd4: 100e2780 call 100e278 + pevent_return = pevent; + } + break; + + case OS_DEL_ALWAYS: /* Always delete the queue */ + while (pevent->OSEventGrp != 0) { /* Ready ALL tasks waiting for queue */ + 1011bd8: e0bffb17 ldw r2,-20(fp) + 1011bdc: 10800283 ldbu r2,10(r2) + 1011be0: 10803fcc andi r2,r2,255 + 1011be4: 1004c03a cmpne r2,r2,zero + 1011be8: 103ff61e bne r2,zero,1011bc4 + (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_Q, OS_STAT_PEND_OK); + } +#if OS_EVENT_NAME_SIZE > 1 + pevent->OSEventName[0] = '?'; /* Unknown name */ + 1011bec: e0fffb17 ldw r3,-20(fp) + 1011bf0: 00800fc4 movi r2,63 + 1011bf4: 18800385 stb r2,14(r3) + pevent->OSEventName[1] = OS_ASCII_NUL; + 1011bf8: e0bffb17 ldw r2,-20(fp) + 1011bfc: 100003c5 stb zero,15(r2) +#endif + pq = (OS_Q *)pevent->OSEventPtr; /* Return OS_Q to free list */ + 1011c00: e0bffb17 ldw r2,-20(fp) + 1011c04: 10800117 ldw r2,4(r2) + 1011c08: e0bff815 stw r2,-32(fp) + pq->OSQPtr = OSQFreeList; + 1011c0c: 008040b4 movhi r2,258 + 1011c10: 10b31b04 addi r2,r2,-13204 + 1011c14: 10c00017 ldw r3,0(r2) + 1011c18: e0bff817 ldw r2,-32(fp) + 1011c1c: 10c00015 stw r3,0(r2) + OSQFreeList = pq; + 1011c20: 00c040b4 movhi r3,258 + 1011c24: 18f31b04 addi r3,r3,-13204 + 1011c28: e0bff817 ldw r2,-32(fp) + 1011c2c: 18800015 stw r2,0(r3) + pevent->OSEventType = OS_EVENT_TYPE_UNUSED; + 1011c30: e0bffb17 ldw r2,-20(fp) + 1011c34: 10000005 stb zero,0(r2) + pevent->OSEventPtr = OSEventFreeList; /* Return Event Control Block to free list */ + 1011c38: 008040b4 movhi r2,258 + 1011c3c: 10b31d04 addi r2,r2,-13196 + 1011c40: 10c00017 ldw r3,0(r2) + 1011c44: e0bffb17 ldw r2,-20(fp) + 1011c48: 10c00115 stw r3,4(r2) + pevent->OSEventCnt = 0; + 1011c4c: e0bffb17 ldw r2,-20(fp) + 1011c50: 1000020d sth zero,8(r2) + OSEventFreeList = pevent; /* Get next free event control block */ + 1011c54: 00c040b4 movhi r3,258 + 1011c58: 18f31d04 addi r3,r3,-13196 + 1011c5c: e0bffb17 ldw r2,-20(fp) + 1011c60: 18800015 stw r2,0(r3) + 1011c64: e0bff717 ldw r2,-36(fp) + 1011c68: e0bff315 stw r2,-52(fp) + 1011c6c: e0bff317 ldw r2,-52(fp) + 1011c70: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + if (tasks_waiting == OS_TRUE) { /* Reschedule only if task(s) were waiting */ + 1011c74: e0bffa03 ldbu r2,-24(fp) + 1011c78: 10800058 cmpnei r2,r2,1 + 1011c7c: 1000011e bne r2,zero,1011c84 + OS_Sched(); /* Find highest priority task ready to run */ + 1011c80: 100ecb80 call 100ecb8 + } + *perr = OS_ERR_NONE; + 1011c84: e0bffd17 ldw r2,-12(fp) + 1011c88: 10000005 stb zero,0(r2) + pevent_return = (OS_EVENT *)0; /* Queue has been deleted */ + 1011c8c: e03ff915 stw zero,-28(fp) + break; + 1011c90: 00000906 br 1011cb8 + 1011c94: e0bff717 ldw r2,-36(fp) + 1011c98: e0bff215 stw r2,-56(fp) + 1011c9c: e0bff217 ldw r2,-56(fp) + 1011ca0: 1001703a wrctl status,r2 + + default: + OS_EXIT_CRITICAL(); + *perr = OS_ERR_INVALID_OPT; + 1011ca4: e0fffd17 ldw r3,-12(fp) + 1011ca8: 008001c4 movi r2,7 + 1011cac: 18800005 stb r2,0(r3) + pevent_return = pevent; + 1011cb0: e0bffb17 ldw r2,-20(fp) + 1011cb4: e0bff915 stw r2,-28(fp) + break; + } + return (pevent_return); + 1011cb8: e0bff917 ldw r2,-28(fp) + 1011cbc: e0bfff15 stw r2,-4(fp) + 1011cc0: e0bfff17 ldw r2,-4(fp) +} + 1011cc4: e037883a mov sp,fp + 1011cc8: dfc00117 ldw ra,4(sp) + 1011ccc: df000017 ldw fp,0(sp) + 1011cd0: dec00204 addi sp,sp,8 + 1011cd4: f800283a ret + +01011cd8 : +********************************************************************************************************* +*/ + +#if OS_Q_FLUSH_EN > 0 +INT8U OSQFlush (OS_EVENT *pevent) +{ + 1011cd8: defff904 addi sp,sp,-28 + 1011cdc: df000615 stw fp,24(sp) + 1011ce0: df000604 addi fp,sp,24 + 1011ce4: e13ffe15 stw r4,-8(fp) + OS_Q *pq; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 1011ce8: e03ffc15 stw zero,-16(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + 1011cec: e0bffe17 ldw r2,-8(fp) + 1011cf0: 1004c03a cmpne r2,r2,zero + 1011cf4: 1000031e bne r2,zero,1011d04 + return (OS_ERR_PEVENT_NULL); + 1011cf8: 00800104 movi r2,4 + 1011cfc: e0bfff15 stw r2,-4(fp) + 1011d00: 00002206 br 1011d8c + } + if (pevent->OSEventType != OS_EVENT_TYPE_Q) { /* Validate event block type */ + 1011d04: e0bffe17 ldw r2,-8(fp) + 1011d08: 10800003 ldbu r2,0(r2) + 1011d0c: 10803fcc andi r2,r2,255 + 1011d10: 108000a0 cmpeqi r2,r2,2 + 1011d14: 1000031e bne r2,zero,1011d24 + return (OS_ERR_EVENT_TYPE); + 1011d18: 00800044 movi r2,1 + 1011d1c: e0bfff15 stw r2,-4(fp) + 1011d20: 00001a06 br 1011d8c +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1011d24: 0005303a rdctl r2,status + 1011d28: e0bffb15 stw r2,-20(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1011d2c: e0fffb17 ldw r3,-20(fp) + 1011d30: 00bfff84 movi r2,-2 + 1011d34: 1884703a and r2,r3,r2 + 1011d38: 1001703a wrctl status,r2 + + return context; + 1011d3c: e0bffb17 ldw r2,-20(fp) + } +#endif + OS_ENTER_CRITICAL(); + 1011d40: e0bffc15 stw r2,-16(fp) + pq = (OS_Q *)pevent->OSEventPtr; /* Point to queue storage structure */ + 1011d44: e0bffe17 ldw r2,-8(fp) + 1011d48: 10800117 ldw r2,4(r2) + 1011d4c: e0bffd15 stw r2,-12(fp) + pq->OSQIn = pq->OSQStart; + 1011d50: e0bffd17 ldw r2,-12(fp) + 1011d54: 10c00117 ldw r3,4(r2) + 1011d58: e0bffd17 ldw r2,-12(fp) + 1011d5c: 10c00315 stw r3,12(r2) + pq->OSQOut = pq->OSQStart; + 1011d60: e0bffd17 ldw r2,-12(fp) + 1011d64: 10c00117 ldw r3,4(r2) + 1011d68: e0bffd17 ldw r2,-12(fp) + 1011d6c: 10c00415 stw r3,16(r2) + pq->OSQEntries = 0; + 1011d70: e0bffd17 ldw r2,-12(fp) + 1011d74: 1000058d sth zero,22(r2) + 1011d78: e0bffc17 ldw r2,-16(fp) + 1011d7c: e0bffa15 stw r2,-24(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1011d80: e0bffa17 ldw r2,-24(fp) + 1011d84: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_NONE); + 1011d88: e03fff15 stw zero,-4(fp) + 1011d8c: e0bfff17 ldw r2,-4(fp) +} + 1011d90: e037883a mov sp,fp + 1011d94: df000017 ldw fp,0(sp) + 1011d98: dec00104 addi sp,sp,4 + 1011d9c: f800283a ret + +01011da0 : +* Note(s) : As of V2.60, this function allows you to receive NULL pointer messages. +********************************************************************************************************* +*/ + +void *OSQPend (OS_EVENT *pevent, INT16U timeout, INT8U *perr) +{ + 1011da0: defff104 addi sp,sp,-60 + 1011da4: dfc00e15 stw ra,56(sp) + 1011da8: df000d15 stw fp,52(sp) + 1011dac: df000d04 addi fp,sp,52 + 1011db0: e13ffb15 stw r4,-20(fp) + 1011db4: e1bffd15 stw r6,-12(fp) + 1011db8: e17ffc0d sth r5,-16(fp) + void *pmsg; + OS_Q *pq; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 1011dbc: e03ff815 stw zero,-32(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + 1011dc0: e0bffd17 ldw r2,-12(fp) + 1011dc4: 1004c03a cmpne r2,r2,zero + 1011dc8: 1000021e bne r2,zero,1011dd4 + return ((void *)0); + 1011dcc: e03fff15 stw zero,-4(fp) + 1011dd0: 0000b506 br 10120a8 + } + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + 1011dd4: e0bffb17 ldw r2,-20(fp) + 1011dd8: 1004c03a cmpne r2,r2,zero + 1011ddc: 1000051e bne r2,zero,1011df4 + *perr = OS_ERR_PEVENT_NULL; + 1011de0: e0fffd17 ldw r3,-12(fp) + 1011de4: 00800104 movi r2,4 + 1011de8: 18800005 stb r2,0(r3) + return ((void *)0); + 1011dec: e03fff15 stw zero,-4(fp) + 1011df0: 0000ad06 br 10120a8 + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_Q) {/* Validate event block type */ + 1011df4: e0bffb17 ldw r2,-20(fp) + 1011df8: 10800003 ldbu r2,0(r2) + 1011dfc: 10803fcc andi r2,r2,255 + 1011e00: 108000a0 cmpeqi r2,r2,2 + 1011e04: 1000051e bne r2,zero,1011e1c + *perr = OS_ERR_EVENT_TYPE; + 1011e08: e0fffd17 ldw r3,-12(fp) + 1011e0c: 00800044 movi r2,1 + 1011e10: 18800005 stb r2,0(r3) + return ((void *)0); + 1011e14: e03fff15 stw zero,-4(fp) + 1011e18: 0000a306 br 10120a8 + } + if (OSIntNesting > 0) { /* See if called from ISR ... */ + 1011e1c: 008040b4 movhi r2,258 + 1011e20: 10b31e04 addi r2,r2,-13192 + 1011e24: 10800003 ldbu r2,0(r2) + 1011e28: 10803fcc andi r2,r2,255 + 1011e2c: 1005003a cmpeq r2,r2,zero + 1011e30: 1000051e bne r2,zero,1011e48 + *perr = OS_ERR_PEND_ISR; /* ... can't PEND from an ISR */ + 1011e34: e0fffd17 ldw r3,-12(fp) + 1011e38: 00800084 movi r2,2 + 1011e3c: 18800005 stb r2,0(r3) + return ((void *)0); + 1011e40: e03fff15 stw zero,-4(fp) + 1011e44: 00009806 br 10120a8 + } + if (OSLockNesting > 0) { /* See if called with scheduler locked ... */ + 1011e48: 008040b4 movhi r2,258 + 1011e4c: 10b31004 addi r2,r2,-13248 + 1011e50: 10800003 ldbu r2,0(r2) + 1011e54: 10803fcc andi r2,r2,255 + 1011e58: 1005003a cmpeq r2,r2,zero + 1011e5c: 1000051e bne r2,zero,1011e74 + *perr = OS_ERR_PEND_LOCKED; /* ... can't PEND when locked */ + 1011e60: e0fffd17 ldw r3,-12(fp) + 1011e64: 00800344 movi r2,13 + 1011e68: 18800005 stb r2,0(r3) + return ((void *)0); + 1011e6c: e03fff15 stw zero,-4(fp) + 1011e70: 00008d06 br 10120a8 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1011e74: 0005303a rdctl r2,status + 1011e78: e0bff715 stw r2,-36(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1011e7c: e0fff717 ldw r3,-36(fp) + 1011e80: 00bfff84 movi r2,-2 + 1011e84: 1884703a and r2,r3,r2 + 1011e88: 1001703a wrctl status,r2 + + return context; + 1011e8c: e0bff717 ldw r2,-36(fp) + } + OS_ENTER_CRITICAL(); + 1011e90: e0bff815 stw r2,-32(fp) + pq = (OS_Q *)pevent->OSEventPtr; /* Point at queue control block */ + 1011e94: e0bffb17 ldw r2,-20(fp) + 1011e98: 10800117 ldw r2,4(r2) + 1011e9c: e0bff915 stw r2,-28(fp) + if (pq->OSQEntries > 0) { /* See if any messages in the queue */ + 1011ea0: e0bff917 ldw r2,-28(fp) + 1011ea4: 1080058b ldhu r2,22(r2) + 1011ea8: 10bfffcc andi r2,r2,65535 + 1011eac: 1005003a cmpeq r2,r2,zero + 1011eb0: 10001f1e bne r2,zero,1011f30 + pmsg = *pq->OSQOut++; /* Yes, extract oldest message from the queue */ + 1011eb4: e0bff917 ldw r2,-28(fp) + 1011eb8: 10c00417 ldw r3,16(r2) + 1011ebc: 18800017 ldw r2,0(r3) + 1011ec0: e0bffa15 stw r2,-24(fp) + 1011ec4: 18c00104 addi r3,r3,4 + 1011ec8: e0bff917 ldw r2,-28(fp) + 1011ecc: 10c00415 stw r3,16(r2) + pq->OSQEntries--; /* Update the number of entries in the queue */ + 1011ed0: e0bff917 ldw r2,-28(fp) + 1011ed4: 1080058b ldhu r2,22(r2) + 1011ed8: 10bfffc4 addi r2,r2,-1 + 1011edc: 1007883a mov r3,r2 + 1011ee0: e0bff917 ldw r2,-28(fp) + 1011ee4: 10c0058d sth r3,22(r2) + if (pq->OSQOut == pq->OSQEnd) { /* Wrap OUT pointer if we are at the end of the queue */ + 1011ee8: e0bff917 ldw r2,-28(fp) + 1011eec: 10c00417 ldw r3,16(r2) + 1011ef0: e0bff917 ldw r2,-28(fp) + 1011ef4: 10800217 ldw r2,8(r2) + 1011ef8: 1880041e bne r3,r2,1011f0c + pq->OSQOut = pq->OSQStart; + 1011efc: e0bff917 ldw r2,-28(fp) + 1011f00: 10c00117 ldw r3,4(r2) + 1011f04: e0bff917 ldw r2,-28(fp) + 1011f08: 10c00415 stw r3,16(r2) + 1011f0c: e0bff817 ldw r2,-32(fp) + 1011f10: e0bff615 stw r2,-40(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1011f14: e0bff617 ldw r2,-40(fp) + 1011f18: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + 1011f1c: e0bffd17 ldw r2,-12(fp) + 1011f20: 10000005 stb zero,0(r2) + return (pmsg); /* Return message received */ + 1011f24: e0bffa17 ldw r2,-24(fp) + 1011f28: e0bfff15 stw r2,-4(fp) + 1011f2c: 00005e06 br 10120a8 + } + OSTCBCur->OSTCBStat |= OS_STAT_Q; /* Task will have to pend for a message to be posted */ + 1011f30: 008040b4 movhi r2,258 + 1011f34: 10b31f04 addi r2,r2,-13188 + 1011f38: 10c00017 ldw r3,0(r2) + 1011f3c: 008040b4 movhi r2,258 + 1011f40: 10b31f04 addi r2,r2,-13188 + 1011f44: 10800017 ldw r2,0(r2) + 1011f48: 10800c03 ldbu r2,48(r2) + 1011f4c: 10800114 ori r2,r2,4 + 1011f50: 18800c05 stb r2,48(r3) + OSTCBCur->OSTCBStatPend = OS_STAT_PEND_OK; + 1011f54: 008040b4 movhi r2,258 + 1011f58: 10b31f04 addi r2,r2,-13188 + 1011f5c: 10800017 ldw r2,0(r2) + 1011f60: 10000c45 stb zero,49(r2) + OSTCBCur->OSTCBDly = timeout; /* Load timeout into TCB */ + 1011f64: 008040b4 movhi r2,258 + 1011f68: 10b31f04 addi r2,r2,-13188 + 1011f6c: 10c00017 ldw r3,0(r2) + 1011f70: e0bffc0b ldhu r2,-16(fp) + 1011f74: 18800b8d sth r2,46(r3) + OS_EventTaskWait(pevent); /* Suspend task until event or timeout occurs */ + 1011f78: e13ffb17 ldw r4,-20(fp) + 1011f7c: 100e40c0 call 100e40c + 1011f80: e0bff817 ldw r2,-32(fp) + 1011f84: e0bff515 stw r2,-44(fp) + 1011f88: e0bff517 ldw r2,-44(fp) + 1011f8c: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + OS_Sched(); /* Find next highest priority task ready to run */ + 1011f90: 100ecb80 call 100ecb8 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1011f94: 0005303a rdctl r2,status + 1011f98: e0bff415 stw r2,-48(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1011f9c: e0fff417 ldw r3,-48(fp) + 1011fa0: 00bfff84 movi r2,-2 + 1011fa4: 1884703a and r2,r3,r2 + 1011fa8: 1001703a wrctl status,r2 + + return context; + 1011fac: e0bff417 ldw r2,-48(fp) + OS_ENTER_CRITICAL(); + 1011fb0: e0bff815 stw r2,-32(fp) + switch (OSTCBCur->OSTCBStatPend) { /* See if we timed-out or aborted */ + 1011fb4: 008040b4 movhi r2,258 + 1011fb8: 10b31f04 addi r2,r2,-13188 + 1011fbc: 10800017 ldw r2,0(r2) + 1011fc0: 10800c43 ldbu r2,49(r2) + 1011fc4: 10803fcc andi r2,r2,255 + 1011fc8: e0bffe15 stw r2,-8(fp) + 1011fcc: e0fffe17 ldw r3,-8(fp) + 1011fd0: 1805003a cmpeq r2,r3,zero + 1011fd4: 1000041e bne r2,zero,1011fe8 + 1011fd8: e0fffe17 ldw r3,-8(fp) + 1011fdc: 188000a0 cmpeqi r2,r3,2 + 1011fe0: 1000091e bne r2,zero,1012008 + 1011fe4: 00000d06 br 101201c + case OS_STAT_PEND_OK: /* Extract message from TCB (Put there by QPost) */ + pmsg = OSTCBCur->OSTCBMsg; + 1011fe8: 008040b4 movhi r2,258 + 1011fec: 10b31f04 addi r2,r2,-13188 + 1011ff0: 10800017 ldw r2,0(r2) + 1011ff4: 10800917 ldw r2,36(r2) + 1011ff8: e0bffa15 stw r2,-24(fp) + *perr = OS_ERR_NONE; + 1011ffc: e0bffd17 ldw r2,-12(fp) + 1012000: 10000005 stb zero,0(r2) + break; + 1012004: 00000e06 br 1012040 + + case OS_STAT_PEND_ABORT: + pmsg = (void *)0; + 1012008: e03ffa15 stw zero,-24(fp) + *perr = OS_ERR_PEND_ABORT; /* Indicate that we aborted */ + 101200c: e0fffd17 ldw r3,-12(fp) + 1012010: 00800384 movi r2,14 + 1012014: 18800005 stb r2,0(r3) + break; + 1012018: 00000906 br 1012040 + + case OS_STAT_PEND_TO: + default: + OS_EventTaskRemove(OSTCBCur, pevent); + 101201c: 008040b4 movhi r2,258 + 1012020: 10b31f04 addi r2,r2,-13188 + 1012024: 11000017 ldw r4,0(r2) + 1012028: e17ffb17 ldw r5,-20(fp) + 101202c: 100e6700 call 100e670 + pmsg = (void *)0; + 1012030: e03ffa15 stw zero,-24(fp) + *perr = OS_ERR_TIMEOUT; /* Indicate that we didn't get event within TO */ + 1012034: e0fffd17 ldw r3,-12(fp) + 1012038: 00800284 movi r2,10 + 101203c: 18800005 stb r2,0(r3) + break; + } + OSTCBCur->OSTCBStat = OS_STAT_RDY; /* Set task status to ready */ + 1012040: 008040b4 movhi r2,258 + 1012044: 10b31f04 addi r2,r2,-13188 + 1012048: 10800017 ldw r2,0(r2) + 101204c: 10000c05 stb zero,48(r2) + OSTCBCur->OSTCBStatPend = OS_STAT_PEND_OK; /* Clear pend status */ + 1012050: 008040b4 movhi r2,258 + 1012054: 10b31f04 addi r2,r2,-13188 + 1012058: 10800017 ldw r2,0(r2) + 101205c: 10000c45 stb zero,49(r2) + OSTCBCur->OSTCBEventPtr = (OS_EVENT *)0; /* Clear event pointers */ + 1012060: 008040b4 movhi r2,258 + 1012064: 10b31f04 addi r2,r2,-13188 + 1012068: 10800017 ldw r2,0(r2) + 101206c: 10000715 stw zero,28(r2) +#if (OS_EVENT_MULTI_EN > 0) + OSTCBCur->OSTCBEventMultiPtr = (OS_EVENT **)0; + 1012070: 008040b4 movhi r2,258 + 1012074: 10b31f04 addi r2,r2,-13188 + 1012078: 10800017 ldw r2,0(r2) + 101207c: 10000815 stw zero,32(r2) +#endif + OSTCBCur->OSTCBMsg = (void *)0; /* Clear received message */ + 1012080: 008040b4 movhi r2,258 + 1012084: 10b31f04 addi r2,r2,-13188 + 1012088: 10800017 ldw r2,0(r2) + 101208c: 10000915 stw zero,36(r2) + 1012090: e0bff817 ldw r2,-32(fp) + 1012094: e0bff315 stw r2,-52(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1012098: e0bff317 ldw r2,-52(fp) + 101209c: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (pmsg); /* Return received message */ + 10120a0: e0bffa17 ldw r2,-24(fp) + 10120a4: e0bfff15 stw r2,-4(fp) + 10120a8: e0bfff17 ldw r2,-4(fp) +} + 10120ac: e037883a mov sp,fp + 10120b0: dfc00117 ldw ra,4(sp) + 10120b4: df000017 ldw fp,0(sp) + 10120b8: dec00204 addi sp,sp,8 + 10120bc: f800283a ret + +010120c0 : +********************************************************************************************************* +*/ + +#if OS_Q_PEND_ABORT_EN > 0 +INT8U OSQPendAbort (OS_EVENT *pevent, INT8U opt, INT8U *perr) +{ + 10120c0: defff504 addi sp,sp,-44 + 10120c4: dfc00a15 stw ra,40(sp) + 10120c8: df000915 stw fp,36(sp) + 10120cc: df000904 addi fp,sp,36 + 10120d0: e13ffc15 stw r4,-16(fp) + 10120d4: e1bffe15 stw r6,-8(fp) + 10120d8: e17ffd05 stb r5,-12(fp) + INT8U nbr_tasks; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 10120dc: e03ffa15 stw zero,-24(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + 10120e0: e0bffe17 ldw r2,-8(fp) + 10120e4: 1004c03a cmpne r2,r2,zero + 10120e8: 1000021e bne r2,zero,10120f4 + return (0); + 10120ec: e03fff15 stw zero,-4(fp) + 10120f0: 00004c06 br 1012224 + } + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + 10120f4: e0bffc17 ldw r2,-16(fp) + 10120f8: 1004c03a cmpne r2,r2,zero + 10120fc: 1000051e bne r2,zero,1012114 + *perr = OS_ERR_PEVENT_NULL; + 1012100: e0fffe17 ldw r3,-8(fp) + 1012104: 00800104 movi r2,4 + 1012108: 18800005 stb r2,0(r3) + return (0); + 101210c: e03fff15 stw zero,-4(fp) + 1012110: 00004406 br 1012224 + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_Q) { /* Validate event block type */ + 1012114: e0bffc17 ldw r2,-16(fp) + 1012118: 10800003 ldbu r2,0(r2) + 101211c: 10803fcc andi r2,r2,255 + 1012120: 108000a0 cmpeqi r2,r2,2 + 1012124: 1000051e bne r2,zero,101213c + *perr = OS_ERR_EVENT_TYPE; + 1012128: e0fffe17 ldw r3,-8(fp) + 101212c: 00800044 movi r2,1 + 1012130: 18800005 stb r2,0(r3) + return (0); + 1012134: e03fff15 stw zero,-4(fp) + 1012138: 00003a06 br 1012224 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 101213c: 0005303a rdctl r2,status + 1012140: e0bff915 stw r2,-28(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1012144: e0fff917 ldw r3,-28(fp) + 1012148: 00bfff84 movi r2,-2 + 101214c: 1884703a and r2,r3,r2 + 1012150: 1001703a wrctl status,r2 + + return context; + 1012154: e0bff917 ldw r2,-28(fp) + } + OS_ENTER_CRITICAL(); + 1012158: e0bffa15 stw r2,-24(fp) + if (pevent->OSEventGrp != 0) { /* See if any task waiting on queue? */ + 101215c: e0bffc17 ldw r2,-16(fp) + 1012160: 10800283 ldbu r2,10(r2) + 1012164: 10803fcc andi r2,r2,255 + 1012168: 1005003a cmpeq r2,r2,zero + 101216c: 1000261e bne r2,zero,1012208 + nbr_tasks = 0; + 1012170: e03ffb05 stb zero,-20(fp) + switch (opt) { + 1012174: e0bffd03 ldbu r2,-12(fp) + 1012178: 10800060 cmpeqi r2,r2,1 + 101217c: 1000091e bne r2,zero,10121a4 + 1012180: 00000e06 br 10121bc + case OS_PEND_OPT_BROADCAST: /* Do we need to abort ALL waiting tasks? */ + while (pevent->OSEventGrp != 0) { /* Yes, ready ALL tasks waiting on queue */ + (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_Q, OS_STAT_PEND_ABORT); + 1012184: e13ffc17 ldw r4,-16(fp) + 1012188: 000b883a mov r5,zero + 101218c: 01800104 movi r6,4 + 1012190: 01c00084 movi r7,2 + 1012194: 100e2780 call 100e278 + nbr_tasks++; + 1012198: e0bffb03 ldbu r2,-20(fp) + 101219c: 10800044 addi r2,r2,1 + 10121a0: e0bffb05 stb r2,-20(fp) + OS_ENTER_CRITICAL(); + if (pevent->OSEventGrp != 0) { /* See if any task waiting on queue? */ + nbr_tasks = 0; + switch (opt) { + case OS_PEND_OPT_BROADCAST: /* Do we need to abort ALL waiting tasks? */ + while (pevent->OSEventGrp != 0) { /* Yes, ready ALL tasks waiting on queue */ + 10121a4: e0bffc17 ldw r2,-16(fp) + 10121a8: 10800283 ldbu r2,10(r2) + 10121ac: 10803fcc andi r2,r2,255 + 10121b0: 1004c03a cmpne r2,r2,zero + 10121b4: 103ff31e bne r2,zero,1012184 + (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_Q, OS_STAT_PEND_ABORT); + nbr_tasks++; + } + break; + 10121b8: 00000806 br 10121dc + + case OS_PEND_OPT_NONE: + default: /* No, ready HPT waiting on queue */ + (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_Q, OS_STAT_PEND_ABORT); + 10121bc: e13ffc17 ldw r4,-16(fp) + 10121c0: 000b883a mov r5,zero + 10121c4: 01800104 movi r6,4 + 10121c8: 01c00084 movi r7,2 + 10121cc: 100e2780 call 100e278 + nbr_tasks++; + 10121d0: e0bffb03 ldbu r2,-20(fp) + 10121d4: 10800044 addi r2,r2,1 + 10121d8: e0bffb05 stb r2,-20(fp) + 10121dc: e0bffa17 ldw r2,-24(fp) + 10121e0: e0bff815 stw r2,-32(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 10121e4: e0bff817 ldw r2,-32(fp) + 10121e8: 1001703a wrctl status,r2 + break; + } + OS_EXIT_CRITICAL(); + OS_Sched(); /* Find HPT ready to run */ + 10121ec: 100ecb80 call 100ecb8 + *perr = OS_ERR_PEND_ABORT; + 10121f0: e0fffe17 ldw r3,-8(fp) + 10121f4: 00800384 movi r2,14 + 10121f8: 18800005 stb r2,0(r3) + return (nbr_tasks); + 10121fc: e0bffb03 ldbu r2,-20(fp) + 1012200: e0bfff15 stw r2,-4(fp) + 1012204: 00000706 br 1012224 + 1012208: e0bffa17 ldw r2,-24(fp) + 101220c: e0bff715 stw r2,-36(fp) + 1012210: e0bff717 ldw r2,-36(fp) + 1012214: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + 1012218: e0bffe17 ldw r2,-8(fp) + 101221c: 10000005 stb zero,0(r2) + return (0); /* No tasks waiting on queue */ + 1012220: e03fff15 stw zero,-4(fp) + 1012224: e0bfff17 ldw r2,-4(fp) +} + 1012228: e037883a mov sp,fp + 101222c: dfc00117 ldw ra,4(sp) + 1012230: df000017 ldw fp,0(sp) + 1012234: dec00204 addi sp,sp,8 + 1012238: f800283a ret + +0101223c : +********************************************************************************************************* +*/ + +#if OS_Q_POST_EN > 0 +INT8U OSQPost (OS_EVENT *pevent, void *pmsg) +{ + 101223c: defff504 addi sp,sp,-44 + 1012240: dfc00a15 stw ra,40(sp) + 1012244: df000915 stw fp,36(sp) + 1012248: df000904 addi fp,sp,36 + 101224c: e13ffd15 stw r4,-12(fp) + 1012250: e17ffe15 stw r5,-8(fp) + OS_Q *pq; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 1012254: e03ffb15 stw zero,-20(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + 1012258: e0bffd17 ldw r2,-12(fp) + 101225c: 1004c03a cmpne r2,r2,zero + 1012260: 1000031e bne r2,zero,1012270 + return (OS_ERR_PEVENT_NULL); + 1012264: 00800104 movi r2,4 + 1012268: e0bfff15 stw r2,-4(fp) + 101226c: 00004d06 br 10123a4 + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_Q) { /* Validate event block type */ + 1012270: e0bffd17 ldw r2,-12(fp) + 1012274: 10800003 ldbu r2,0(r2) + 1012278: 10803fcc andi r2,r2,255 + 101227c: 108000a0 cmpeqi r2,r2,2 + 1012280: 1000031e bne r2,zero,1012290 + return (OS_ERR_EVENT_TYPE); + 1012284: 00800044 movi r2,1 + 1012288: e0bfff15 stw r2,-4(fp) + 101228c: 00004506 br 10123a4 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1012290: 0005303a rdctl r2,status + 1012294: e0bffa15 stw r2,-24(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1012298: e0fffa17 ldw r3,-24(fp) + 101229c: 00bfff84 movi r2,-2 + 10122a0: 1884703a and r2,r3,r2 + 10122a4: 1001703a wrctl status,r2 + + return context; + 10122a8: e0bffa17 ldw r2,-24(fp) + } + OS_ENTER_CRITICAL(); + 10122ac: e0bffb15 stw r2,-20(fp) + if (pevent->OSEventGrp != 0) { /* See if any task pending on queue */ + 10122b0: e0bffd17 ldw r2,-12(fp) + 10122b4: 10800283 ldbu r2,10(r2) + 10122b8: 10803fcc andi r2,r2,255 + 10122bc: 1005003a cmpeq r2,r2,zero + 10122c0: 10000c1e bne r2,zero,10122f4 + /* Ready highest priority task waiting on event */ + (void)OS_EventTaskRdy(pevent, pmsg, OS_STAT_Q, OS_STAT_PEND_OK); + 10122c4: e13ffd17 ldw r4,-12(fp) + 10122c8: e17ffe17 ldw r5,-8(fp) + 10122cc: 01800104 movi r6,4 + 10122d0: 000f883a mov r7,zero + 10122d4: 100e2780 call 100e278 + 10122d8: e0bffb17 ldw r2,-20(fp) + 10122dc: e0bff915 stw r2,-28(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 10122e0: e0bff917 ldw r2,-28(fp) + 10122e4: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + OS_Sched(); /* Find highest priority task ready to run */ + 10122e8: 100ecb80 call 100ecb8 + return (OS_ERR_NONE); + 10122ec: e03fff15 stw zero,-4(fp) + 10122f0: 00002c06 br 10123a4 + } + pq = (OS_Q *)pevent->OSEventPtr; /* Point to queue control block */ + 10122f4: e0bffd17 ldw r2,-12(fp) + 10122f8: 10800117 ldw r2,4(r2) + 10122fc: e0bffc15 stw r2,-16(fp) + if (pq->OSQEntries >= pq->OSQSize) { /* Make sure queue is not full */ + 1012300: e0bffc17 ldw r2,-16(fp) + 1012304: 10c0058b ldhu r3,22(r2) + 1012308: e0bffc17 ldw r2,-16(fp) + 101230c: 1080050b ldhu r2,20(r2) + 1012310: 18ffffcc andi r3,r3,65535 + 1012314: 10bfffcc andi r2,r2,65535 + 1012318: 18800736 bltu r3,r2,1012338 + 101231c: e0bffb17 ldw r2,-20(fp) + 1012320: e0bff815 stw r2,-32(fp) + 1012324: e0bff817 ldw r2,-32(fp) + 1012328: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_Q_FULL); + 101232c: 00800784 movi r2,30 + 1012330: e0bfff15 stw r2,-4(fp) + 1012334: 00001b06 br 10123a4 + } + *pq->OSQIn++ = pmsg; /* Insert message into queue */ + 1012338: e0bffc17 ldw r2,-16(fp) + 101233c: 10c00317 ldw r3,12(r2) + 1012340: e0bffe17 ldw r2,-8(fp) + 1012344: 18800015 stw r2,0(r3) + 1012348: 18c00104 addi r3,r3,4 + 101234c: e0bffc17 ldw r2,-16(fp) + 1012350: 10c00315 stw r3,12(r2) + pq->OSQEntries++; /* Update the nbr of entries in the queue */ + 1012354: e0bffc17 ldw r2,-16(fp) + 1012358: 1080058b ldhu r2,22(r2) + 101235c: 10800044 addi r2,r2,1 + 1012360: 1007883a mov r3,r2 + 1012364: e0bffc17 ldw r2,-16(fp) + 1012368: 10c0058d sth r3,22(r2) + if (pq->OSQIn == pq->OSQEnd) { /* Wrap IN ptr if we are at end of queue */ + 101236c: e0bffc17 ldw r2,-16(fp) + 1012370: 10c00317 ldw r3,12(r2) + 1012374: e0bffc17 ldw r2,-16(fp) + 1012378: 10800217 ldw r2,8(r2) + 101237c: 1880041e bne r3,r2,1012390 + pq->OSQIn = pq->OSQStart; + 1012380: e0bffc17 ldw r2,-16(fp) + 1012384: 10c00117 ldw r3,4(r2) + 1012388: e0bffc17 ldw r2,-16(fp) + 101238c: 10c00315 stw r3,12(r2) + 1012390: e0bffb17 ldw r2,-20(fp) + 1012394: e0bff715 stw r2,-36(fp) + 1012398: e0bff717 ldw r2,-36(fp) + 101239c: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); + return (OS_ERR_NONE); + 10123a0: e03fff15 stw zero,-4(fp) + 10123a4: e0bfff17 ldw r2,-4(fp) +} + 10123a8: e037883a mov sp,fp + 10123ac: dfc00117 ldw ra,4(sp) + 10123b0: df000017 ldw fp,0(sp) + 10123b4: dec00204 addi sp,sp,8 + 10123b8: f800283a ret + +010123bc : +********************************************************************************************************* +*/ + +#if OS_Q_POST_FRONT_EN > 0 +INT8U OSQPostFront (OS_EVENT *pevent, void *pmsg) +{ + 10123bc: defff504 addi sp,sp,-44 + 10123c0: dfc00a15 stw ra,40(sp) + 10123c4: df000915 stw fp,36(sp) + 10123c8: df000904 addi fp,sp,36 + 10123cc: e13ffd15 stw r4,-12(fp) + 10123d0: e17ffe15 stw r5,-8(fp) + OS_Q *pq; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 10123d4: e03ffb15 stw zero,-20(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + 10123d8: e0bffd17 ldw r2,-12(fp) + 10123dc: 1004c03a cmpne r2,r2,zero + 10123e0: 1000031e bne r2,zero,10123f0 + return (OS_ERR_PEVENT_NULL); + 10123e4: 00800104 movi r2,4 + 10123e8: e0bfff15 stw r2,-4(fp) + 10123ec: 00004f06 br 101252c + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_Q) { /* Validate event block type */ + 10123f0: e0bffd17 ldw r2,-12(fp) + 10123f4: 10800003 ldbu r2,0(r2) + 10123f8: 10803fcc andi r2,r2,255 + 10123fc: 108000a0 cmpeqi r2,r2,2 + 1012400: 1000031e bne r2,zero,1012410 + return (OS_ERR_EVENT_TYPE); + 1012404: 00800044 movi r2,1 + 1012408: e0bfff15 stw r2,-4(fp) + 101240c: 00004706 br 101252c +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1012410: 0005303a rdctl r2,status + 1012414: e0bffa15 stw r2,-24(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1012418: e0fffa17 ldw r3,-24(fp) + 101241c: 00bfff84 movi r2,-2 + 1012420: 1884703a and r2,r3,r2 + 1012424: 1001703a wrctl status,r2 + + return context; + 1012428: e0bffa17 ldw r2,-24(fp) + } + OS_ENTER_CRITICAL(); + 101242c: e0bffb15 stw r2,-20(fp) + if (pevent->OSEventGrp != 0) { /* See if any task pending on queue */ + 1012430: e0bffd17 ldw r2,-12(fp) + 1012434: 10800283 ldbu r2,10(r2) + 1012438: 10803fcc andi r2,r2,255 + 101243c: 1005003a cmpeq r2,r2,zero + 1012440: 10000c1e bne r2,zero,1012474 + /* Ready highest priority task waiting on event */ + (void)OS_EventTaskRdy(pevent, pmsg, OS_STAT_Q, OS_STAT_PEND_OK); + 1012444: e13ffd17 ldw r4,-12(fp) + 1012448: e17ffe17 ldw r5,-8(fp) + 101244c: 01800104 movi r6,4 + 1012450: 000f883a mov r7,zero + 1012454: 100e2780 call 100e278 + 1012458: e0bffb17 ldw r2,-20(fp) + 101245c: e0bff915 stw r2,-28(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1012460: e0bff917 ldw r2,-28(fp) + 1012464: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + OS_Sched(); /* Find highest priority task ready to run */ + 1012468: 100ecb80 call 100ecb8 + return (OS_ERR_NONE); + 101246c: e03fff15 stw zero,-4(fp) + 1012470: 00002e06 br 101252c + } + pq = (OS_Q *)pevent->OSEventPtr; /* Point to queue control block */ + 1012474: e0bffd17 ldw r2,-12(fp) + 1012478: 10800117 ldw r2,4(r2) + 101247c: e0bffc15 stw r2,-16(fp) + if (pq->OSQEntries >= pq->OSQSize) { /* Make sure queue is not full */ + 1012480: e0bffc17 ldw r2,-16(fp) + 1012484: 10c0058b ldhu r3,22(r2) + 1012488: e0bffc17 ldw r2,-16(fp) + 101248c: 1080050b ldhu r2,20(r2) + 1012490: 18ffffcc andi r3,r3,65535 + 1012494: 10bfffcc andi r2,r2,65535 + 1012498: 18800736 bltu r3,r2,10124b8 + 101249c: e0bffb17 ldw r2,-20(fp) + 10124a0: e0bff815 stw r2,-32(fp) + 10124a4: e0bff817 ldw r2,-32(fp) + 10124a8: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_Q_FULL); + 10124ac: 00800784 movi r2,30 + 10124b0: e0bfff15 stw r2,-4(fp) + 10124b4: 00001d06 br 101252c + } + if (pq->OSQOut == pq->OSQStart) { /* Wrap OUT ptr if we are at the 1st queue entry */ + 10124b8: e0bffc17 ldw r2,-16(fp) + 10124bc: 10c00417 ldw r3,16(r2) + 10124c0: e0bffc17 ldw r2,-16(fp) + 10124c4: 10800117 ldw r2,4(r2) + 10124c8: 1880041e bne r3,r2,10124dc + pq->OSQOut = pq->OSQEnd; + 10124cc: e0bffc17 ldw r2,-16(fp) + 10124d0: 10c00217 ldw r3,8(r2) + 10124d4: e0bffc17 ldw r2,-16(fp) + 10124d8: 10c00415 stw r3,16(r2) + } + pq->OSQOut--; + 10124dc: e0bffc17 ldw r2,-16(fp) + 10124e0: 10800417 ldw r2,16(r2) + 10124e4: 10ffff04 addi r3,r2,-4 + 10124e8: e0bffc17 ldw r2,-16(fp) + 10124ec: 10c00415 stw r3,16(r2) + *pq->OSQOut = pmsg; /* Insert message into queue */ + 10124f0: e0bffc17 ldw r2,-16(fp) + 10124f4: 10c00417 ldw r3,16(r2) + 10124f8: e0bffe17 ldw r2,-8(fp) + 10124fc: 18800015 stw r2,0(r3) + pq->OSQEntries++; /* Update the nbr of entries in the queue */ + 1012500: e0bffc17 ldw r2,-16(fp) + 1012504: 1080058b ldhu r2,22(r2) + 1012508: 10800044 addi r2,r2,1 + 101250c: 1007883a mov r3,r2 + 1012510: e0bffc17 ldw r2,-16(fp) + 1012514: 10c0058d sth r3,22(r2) + 1012518: e0bffb17 ldw r2,-20(fp) + 101251c: e0bff715 stw r2,-36(fp) + 1012520: e0bff717 ldw r2,-36(fp) + 1012524: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_NONE); + 1012528: e03fff15 stw zero,-4(fp) + 101252c: e0bfff17 ldw r2,-4(fp) +} + 1012530: e037883a mov sp,fp + 1012534: dfc00117 ldw ra,4(sp) + 1012538: df000017 ldw fp,0(sp) + 101253c: dec00204 addi sp,sp,8 + 1012540: f800283a ret + +01012544 : +********************************************************************************************************* +*/ + +#if OS_Q_POST_OPT_EN > 0 +INT8U OSQPostOpt (OS_EVENT *pevent, void *pmsg, INT8U opt) +{ + 1012544: defff404 addi sp,sp,-48 + 1012548: dfc00b15 stw ra,44(sp) + 101254c: df000a15 stw fp,40(sp) + 1012550: df000a04 addi fp,sp,40 + 1012554: e13ffc15 stw r4,-16(fp) + 1012558: e17ffd15 stw r5,-12(fp) + 101255c: e1bffe05 stb r6,-8(fp) + OS_Q *pq; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 1012560: e03ffa15 stw zero,-24(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + 1012564: e0bffc17 ldw r2,-16(fp) + 1012568: 1004c03a cmpne r2,r2,zero + 101256c: 1000031e bne r2,zero,101257c + return (OS_ERR_PEVENT_NULL); + 1012570: 00800104 movi r2,4 + 1012574: e0bfff15 stw r2,-4(fp) + 1012578: 00007906 br 1012760 + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_Q) { /* Validate event block type */ + 101257c: e0bffc17 ldw r2,-16(fp) + 1012580: 10800003 ldbu r2,0(r2) + 1012584: 10803fcc andi r2,r2,255 + 1012588: 108000a0 cmpeqi r2,r2,2 + 101258c: 1000031e bne r2,zero,101259c + return (OS_ERR_EVENT_TYPE); + 1012590: 00800044 movi r2,1 + 1012594: e0bfff15 stw r2,-4(fp) + 1012598: 00007106 br 1012760 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 101259c: 0005303a rdctl r2,status + 10125a0: e0bff915 stw r2,-28(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 10125a4: e0fff917 ldw r3,-28(fp) + 10125a8: 00bfff84 movi r2,-2 + 10125ac: 1884703a and r2,r3,r2 + 10125b0: 1001703a wrctl status,r2 + + return context; + 10125b4: e0bff917 ldw r2,-28(fp) + } + OS_ENTER_CRITICAL(); + 10125b8: e0bffa15 stw r2,-24(fp) + if (pevent->OSEventGrp != 0x00) { /* See if any task pending on queue */ + 10125bc: e0bffc17 ldw r2,-16(fp) + 10125c0: 10800283 ldbu r2,10(r2) + 10125c4: 10803fcc andi r2,r2,255 + 10125c8: 1005003a cmpeq r2,r2,zero + 10125cc: 1000211e bne r2,zero,1012654 + if ((opt & OS_POST_OPT_BROADCAST) != 0x00) { /* Do we need to post msg to ALL waiting tasks ? */ + 10125d0: e0bffe03 ldbu r2,-8(fp) + 10125d4: 1080004c andi r2,r2,1 + 10125d8: 10803fcc andi r2,r2,255 + 10125dc: 1005003a cmpeq r2,r2,zero + 10125e0: 10000c1e bne r2,zero,1012614 + while (pevent->OSEventGrp != 0) { /* Yes, Post to ALL tasks waiting on queue */ + 10125e4: 00000506 br 10125fc + (void)OS_EventTaskRdy(pevent, pmsg, OS_STAT_Q, OS_STAT_PEND_OK); + 10125e8: e13ffc17 ldw r4,-16(fp) + 10125ec: e17ffd17 ldw r5,-12(fp) + 10125f0: 01800104 movi r6,4 + 10125f4: 000f883a mov r7,zero + 10125f8: 100e2780 call 100e278 + return (OS_ERR_EVENT_TYPE); + } + OS_ENTER_CRITICAL(); + if (pevent->OSEventGrp != 0x00) { /* See if any task pending on queue */ + if ((opt & OS_POST_OPT_BROADCAST) != 0x00) { /* Do we need to post msg to ALL waiting tasks ? */ + while (pevent->OSEventGrp != 0) { /* Yes, Post to ALL tasks waiting on queue */ + 10125fc: e0bffc17 ldw r2,-16(fp) + 1012600: 10800283 ldbu r2,10(r2) + 1012604: 10803fcc andi r2,r2,255 + 1012608: 1004c03a cmpne r2,r2,zero + 101260c: 103ff61e bne r2,zero,10125e8 + 1012610: 00000506 br 1012628 + (void)OS_EventTaskRdy(pevent, pmsg, OS_STAT_Q, OS_STAT_PEND_OK); + } + } else { /* No, Post to HPT waiting on queue */ + (void)OS_EventTaskRdy(pevent, pmsg, OS_STAT_Q, OS_STAT_PEND_OK); + 1012614: e13ffc17 ldw r4,-16(fp) + 1012618: e17ffd17 ldw r5,-12(fp) + 101261c: 01800104 movi r6,4 + 1012620: 000f883a mov r7,zero + 1012624: 100e2780 call 100e278 + 1012628: e0bffa17 ldw r2,-24(fp) + 101262c: e0bff815 stw r2,-32(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1012630: e0bff817 ldw r2,-32(fp) + 1012634: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); + if ((opt & OS_POST_OPT_NO_SCHED) == 0) { /* See if scheduler needs to be invoked */ + 1012638: e0bffe03 ldbu r2,-8(fp) + 101263c: 1080010c andi r2,r2,4 + 1012640: 1004c03a cmpne r2,r2,zero + 1012644: 1000011e bne r2,zero,101264c + OS_Sched(); /* Find highest priority task ready to run */ + 1012648: 100ecb80 call 100ecb8 + } + return (OS_ERR_NONE); + 101264c: e03fff15 stw zero,-4(fp) + 1012650: 00004306 br 1012760 + } + pq = (OS_Q *)pevent->OSEventPtr; /* Point to queue control block */ + 1012654: e0bffc17 ldw r2,-16(fp) + 1012658: 10800117 ldw r2,4(r2) + 101265c: e0bffb15 stw r2,-20(fp) + if (pq->OSQEntries >= pq->OSQSize) { /* Make sure queue is not full */ + 1012660: e0bffb17 ldw r2,-20(fp) + 1012664: 10c0058b ldhu r3,22(r2) + 1012668: e0bffb17 ldw r2,-20(fp) + 101266c: 1080050b ldhu r2,20(r2) + 1012670: 18ffffcc andi r3,r3,65535 + 1012674: 10bfffcc andi r2,r2,65535 + 1012678: 18800736 bltu r3,r2,1012698 + 101267c: e0bffa17 ldw r2,-24(fp) + 1012680: e0bff715 stw r2,-36(fp) + 1012684: e0bff717 ldw r2,-36(fp) + 1012688: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_Q_FULL); + 101268c: 00800784 movi r2,30 + 1012690: e0bfff15 stw r2,-4(fp) + 1012694: 00003206 br 1012760 + } + if ((opt & OS_POST_OPT_FRONT) != 0x00) { /* Do we post to the FRONT of the queue? */ + 1012698: e0bffe03 ldbu r2,-8(fp) + 101269c: 1080008c andi r2,r2,2 + 10126a0: 1005003a cmpeq r2,r2,zero + 10126a4: 1000131e bne r2,zero,10126f4 + if (pq->OSQOut == pq->OSQStart) { /* Yes, Post as LIFO, Wrap OUT pointer if we ... */ + 10126a8: e0bffb17 ldw r2,-20(fp) + 10126ac: 10c00417 ldw r3,16(r2) + 10126b0: e0bffb17 ldw r2,-20(fp) + 10126b4: 10800117 ldw r2,4(r2) + 10126b8: 1880041e bne r3,r2,10126cc + pq->OSQOut = pq->OSQEnd; /* ... are at the 1st queue entry */ + 10126bc: e0bffb17 ldw r2,-20(fp) + 10126c0: 10c00217 ldw r3,8(r2) + 10126c4: e0bffb17 ldw r2,-20(fp) + 10126c8: 10c00415 stw r3,16(r2) + } + pq->OSQOut--; + 10126cc: e0bffb17 ldw r2,-20(fp) + 10126d0: 10800417 ldw r2,16(r2) + 10126d4: 10ffff04 addi r3,r2,-4 + 10126d8: e0bffb17 ldw r2,-20(fp) + 10126dc: 10c00415 stw r3,16(r2) + *pq->OSQOut = pmsg; /* Insert message into queue */ + 10126e0: e0bffb17 ldw r2,-20(fp) + 10126e4: 10c00417 ldw r3,16(r2) + 10126e8: e0bffd17 ldw r2,-12(fp) + 10126ec: 18800015 stw r2,0(r3) + 10126f0: 00001006 br 1012734 + } else { /* No, Post as FIFO */ + *pq->OSQIn++ = pmsg; /* Insert message into queue */ + 10126f4: e0bffb17 ldw r2,-20(fp) + 10126f8: 10c00317 ldw r3,12(r2) + 10126fc: e0bffd17 ldw r2,-12(fp) + 1012700: 18800015 stw r2,0(r3) + 1012704: 18c00104 addi r3,r3,4 + 1012708: e0bffb17 ldw r2,-20(fp) + 101270c: 10c00315 stw r3,12(r2) + if (pq->OSQIn == pq->OSQEnd) { /* Wrap IN ptr if we are at end of queue */ + 1012710: e0bffb17 ldw r2,-20(fp) + 1012714: 10c00317 ldw r3,12(r2) + 1012718: e0bffb17 ldw r2,-20(fp) + 101271c: 10800217 ldw r2,8(r2) + 1012720: 1880041e bne r3,r2,1012734 + pq->OSQIn = pq->OSQStart; + 1012724: e0bffb17 ldw r2,-20(fp) + 1012728: 10c00117 ldw r3,4(r2) + 101272c: e0bffb17 ldw r2,-20(fp) + 1012730: 10c00315 stw r3,12(r2) + } + } + pq->OSQEntries++; /* Update the nbr of entries in the queue */ + 1012734: e0bffb17 ldw r2,-20(fp) + 1012738: 1080058b ldhu r2,22(r2) + 101273c: 10800044 addi r2,r2,1 + 1012740: 1007883a mov r3,r2 + 1012744: e0bffb17 ldw r2,-20(fp) + 1012748: 10c0058d sth r3,22(r2) + 101274c: e0bffa17 ldw r2,-24(fp) + 1012750: e0bff615 stw r2,-40(fp) + 1012754: e0bff617 ldw r2,-40(fp) + 1012758: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_NONE); + 101275c: e03fff15 stw zero,-4(fp) + 1012760: e0bfff17 ldw r2,-4(fp) +} + 1012764: e037883a mov sp,fp + 1012768: dfc00117 ldw ra,4(sp) + 101276c: df000017 ldw fp,0(sp) + 1012770: dec00204 addi sp,sp,8 + 1012774: f800283a ret + +01012778 : +********************************************************************************************************* +*/ + +#if OS_Q_QUERY_EN > 0 +INT8U OSQQuery (OS_EVENT *pevent, OS_Q_DATA *p_q_data) +{ + 1012778: defff504 addi sp,sp,-44 + 101277c: df000a15 stw fp,40(sp) + 1012780: df000a04 addi fp,sp,40 + 1012784: e13ffd15 stw r4,-12(fp) + 1012788: e17ffe15 stw r5,-8(fp) +#else + INT16U *psrc; + INT16U *pdest; +#endif +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 101278c: e03ff815 stw zero,-32(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + 1012790: e0bffd17 ldw r2,-12(fp) + 1012794: 1004c03a cmpne r2,r2,zero + 1012798: 1000031e bne r2,zero,10127a8 + return (OS_ERR_PEVENT_NULL); + 101279c: 00800104 movi r2,4 + 10127a0: e0bfff15 stw r2,-4(fp) + 10127a4: 00004f06 br 10128e4 + } + if (p_q_data == (OS_Q_DATA *)0) { /* Validate 'p_q_data' */ + 10127a8: e0bffe17 ldw r2,-8(fp) + 10127ac: 1004c03a cmpne r2,r2,zero + 10127b0: 1000031e bne r2,zero,10127c0 + return (OS_ERR_PDATA_NULL); + 10127b4: 00800244 movi r2,9 + 10127b8: e0bfff15 stw r2,-4(fp) + 10127bc: 00004906 br 10128e4 + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_Q) { /* Validate event block type */ + 10127c0: e0bffd17 ldw r2,-12(fp) + 10127c4: 10800003 ldbu r2,0(r2) + 10127c8: 10803fcc andi r2,r2,255 + 10127cc: 108000a0 cmpeqi r2,r2,2 + 10127d0: 1000031e bne r2,zero,10127e0 + return (OS_ERR_EVENT_TYPE); + 10127d4: 00800044 movi r2,1 + 10127d8: e0bfff15 stw r2,-4(fp) + 10127dc: 00004106 br 10128e4 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 10127e0: 0005303a rdctl r2,status + 10127e4: e0bff715 stw r2,-36(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 10127e8: e0fff717 ldw r3,-36(fp) + 10127ec: 00bfff84 movi r2,-2 + 10127f0: 1884703a and r2,r3,r2 + 10127f4: 1001703a wrctl status,r2 + + return context; + 10127f8: e0bff717 ldw r2,-36(fp) + } + OS_ENTER_CRITICAL(); + 10127fc: e0bff815 stw r2,-32(fp) + p_q_data->OSEventGrp = pevent->OSEventGrp; /* Copy message queue wait list */ + 1012800: e0bffd17 ldw r2,-12(fp) + 1012804: 10c00283 ldbu r3,10(r2) + 1012808: e0bffe17 ldw r2,-8(fp) + 101280c: 10c002c5 stb r3,11(r2) + psrc = &pevent->OSEventTbl[0]; + 1012810: e0bffd17 ldw r2,-12(fp) + 1012814: 108002c4 addi r2,r2,11 + 1012818: e0bffa15 stw r2,-24(fp) + pdest = &p_q_data->OSEventTbl[0]; + 101281c: e0bffe17 ldw r2,-8(fp) + 1012820: 10800204 addi r2,r2,8 + 1012824: e0bff915 stw r2,-28(fp) + for (i = 0; i < OS_EVENT_TBL_SIZE; i++) { + 1012828: e03ffb05 stb zero,-20(fp) + 101282c: 00000d06 br 1012864 + *pdest++ = *psrc++; + 1012830: e0bffa17 ldw r2,-24(fp) + 1012834: 10c00003 ldbu r3,0(r2) + 1012838: e0bff917 ldw r2,-28(fp) + 101283c: 10c00005 stb r3,0(r2) + 1012840: e0bff917 ldw r2,-28(fp) + 1012844: 10800044 addi r2,r2,1 + 1012848: e0bff915 stw r2,-28(fp) + 101284c: e0bffa17 ldw r2,-24(fp) + 1012850: 10800044 addi r2,r2,1 + 1012854: e0bffa15 stw r2,-24(fp) + } + OS_ENTER_CRITICAL(); + p_q_data->OSEventGrp = pevent->OSEventGrp; /* Copy message queue wait list */ + psrc = &pevent->OSEventTbl[0]; + pdest = &p_q_data->OSEventTbl[0]; + for (i = 0; i < OS_EVENT_TBL_SIZE; i++) { + 1012858: e0bffb03 ldbu r2,-20(fp) + 101285c: 10800044 addi r2,r2,1 + 1012860: e0bffb05 stb r2,-20(fp) + 1012864: e0bffb03 ldbu r2,-20(fp) + 1012868: 108000f0 cmpltui r2,r2,3 + 101286c: 103ff01e bne r2,zero,1012830 + *pdest++ = *psrc++; + } + pq = (OS_Q *)pevent->OSEventPtr; + 1012870: e0bffd17 ldw r2,-12(fp) + 1012874: 10800117 ldw r2,4(r2) + 1012878: e0bffc15 stw r2,-16(fp) + if (pq->OSQEntries > 0) { + 101287c: e0bffc17 ldw r2,-16(fp) + 1012880: 1080058b ldhu r2,22(r2) + 1012884: 10bfffcc andi r2,r2,65535 + 1012888: 1005003a cmpeq r2,r2,zero + 101288c: 1000061e bne r2,zero,10128a8 + p_q_data->OSMsg = *pq->OSQOut; /* Get next message to return if available */ + 1012890: e0bffc17 ldw r2,-16(fp) + 1012894: 10800417 ldw r2,16(r2) + 1012898: 10c00017 ldw r3,0(r2) + 101289c: e0bffe17 ldw r2,-8(fp) + 10128a0: 10c00015 stw r3,0(r2) + 10128a4: 00000206 br 10128b0 + } else { + p_q_data->OSMsg = (void *)0; + 10128a8: e0bffe17 ldw r2,-8(fp) + 10128ac: 10000015 stw zero,0(r2) + } + p_q_data->OSNMsgs = pq->OSQEntries; + 10128b0: e0bffc17 ldw r2,-16(fp) + 10128b4: 10c0058b ldhu r3,22(r2) + 10128b8: e0bffe17 ldw r2,-8(fp) + 10128bc: 10c0010d sth r3,4(r2) + p_q_data->OSQSize = pq->OSQSize; + 10128c0: e0bffc17 ldw r2,-16(fp) + 10128c4: 10c0050b ldhu r3,20(r2) + 10128c8: e0bffe17 ldw r2,-8(fp) + 10128cc: 10c0018d sth r3,6(r2) + 10128d0: e0bff817 ldw r2,-32(fp) + 10128d4: e0bff615 stw r2,-40(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 10128d8: e0bff617 ldw r2,-40(fp) + 10128dc: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_NONE); + 10128e0: e03fff15 stw zero,-4(fp) + 10128e4: e0bfff17 ldw r2,-4(fp) +} + 10128e8: e037883a mov sp,fp + 10128ec: df000017 ldw fp,0(sp) + 10128f0: dec00104 addi sp,sp,4 + 10128f4: f800283a ret + +010128f8 : +* Note(s) : This function is INTERNAL to uC/OS-II and your application should not call it. +********************************************************************************************************* +*/ + +void OS_QInit (void) +{ + 10128f8: defffb04 addi sp,sp,-20 + 10128fc: dfc00415 stw ra,16(sp) + 1012900: df000315 stw fp,12(sp) + 1012904: df000304 addi fp,sp,12 + OS_Q *pq1; + OS_Q *pq2; + + + + OS_MemClr((INT8U *)&OSQTbl[0], sizeof(OSQTbl)); /* Clear the queue table */ + 1012908: 010040b4 movhi r4,258 + 101290c: 21131d04 addi r4,r4,19572 + 1012910: 01407804 movi r5,480 + 1012914: 100ebf80 call 100ebf8 + pq1 = &OSQTbl[0]; + 1012918: 008040b4 movhi r2,258 + 101291c: 10931d04 addi r2,r2,19572 + 1012920: e0bffe15 stw r2,-8(fp) + pq2 = &OSQTbl[1]; + 1012924: 008040b4 movhi r2,258 + 1012928: 10932304 addi r2,r2,19596 + 101292c: e0bffd15 stw r2,-12(fp) + for (i = 0; i < (OS_MAX_QS - 1); i++) { /* Init. list of free QUEUE control blocks */ + 1012930: e03fff0d sth zero,-4(fp) + 1012934: 00000c06 br 1012968 + pq1->OSQPtr = pq2; + 1012938: e0fffe17 ldw r3,-8(fp) + 101293c: e0bffd17 ldw r2,-12(fp) + 1012940: 18800015 stw r2,0(r3) + pq1++; + 1012944: e0bffe17 ldw r2,-8(fp) + 1012948: 10800604 addi r2,r2,24 + 101294c: e0bffe15 stw r2,-8(fp) + pq2++; + 1012950: e0bffd17 ldw r2,-12(fp) + 1012954: 10800604 addi r2,r2,24 + 1012958: e0bffd15 stw r2,-12(fp) + + + OS_MemClr((INT8U *)&OSQTbl[0], sizeof(OSQTbl)); /* Clear the queue table */ + pq1 = &OSQTbl[0]; + pq2 = &OSQTbl[1]; + for (i = 0; i < (OS_MAX_QS - 1); i++) { /* Init. list of free QUEUE control blocks */ + 101295c: e0bfff0b ldhu r2,-4(fp) + 1012960: 10800044 addi r2,r2,1 + 1012964: e0bfff0d sth r2,-4(fp) + 1012968: e0bfff0b ldhu r2,-4(fp) + 101296c: 108004f0 cmpltui r2,r2,19 + 1012970: 103ff11e bne r2,zero,1012938 + pq1->OSQPtr = pq2; + pq1++; + pq2++; + } + pq1->OSQPtr = (OS_Q *)0; + 1012974: e0bffe17 ldw r2,-8(fp) + 1012978: 10000015 stw zero,0(r2) + OSQFreeList = &OSQTbl[0]; + 101297c: 00c040b4 movhi r3,258 + 1012980: 18f31b04 addi r3,r3,-13204 + 1012984: 008040b4 movhi r2,258 + 1012988: 10931d04 addi r2,r2,19572 + 101298c: 18800015 stw r2,0(r3) +#endif +} + 1012990: e037883a mov sp,fp + 1012994: dfc00117 ldw ra,4(sp) + 1012998: df000017 ldw fp,0(sp) + 101299c: dec00204 addi sp,sp,8 + 10129a0: f800283a ret + +010129a4 : +********************************************************************************************************* +*/ + +#if OS_SEM_ACCEPT_EN > 0 +INT16U OSSemAccept (OS_EVENT *pevent) +{ + 10129a4: defff904 addi sp,sp,-28 + 10129a8: df000615 stw fp,24(sp) + 10129ac: df000604 addi fp,sp,24 + 10129b0: e13ffe15 stw r4,-8(fp) + INT16U cnt; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 10129b4: e03ffc15 stw zero,-16(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + 10129b8: e0bffe17 ldw r2,-8(fp) + 10129bc: 1004c03a cmpne r2,r2,zero + 10129c0: 1000021e bne r2,zero,10129cc + return (0); + 10129c4: e03fff15 stw zero,-4(fp) + 10129c8: 00002106 br 1012a50 + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_SEM) { /* Validate event block type */ + 10129cc: e0bffe17 ldw r2,-8(fp) + 10129d0: 10800003 ldbu r2,0(r2) + 10129d4: 10803fcc andi r2,r2,255 + 10129d8: 108000e0 cmpeqi r2,r2,3 + 10129dc: 1000021e bne r2,zero,10129e8 + return (0); + 10129e0: e03fff15 stw zero,-4(fp) + 10129e4: 00001a06 br 1012a50 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 10129e8: 0005303a rdctl r2,status + 10129ec: e0bffb15 stw r2,-20(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 10129f0: e0fffb17 ldw r3,-20(fp) + 10129f4: 00bfff84 movi r2,-2 + 10129f8: 1884703a and r2,r3,r2 + 10129fc: 1001703a wrctl status,r2 + + return context; + 1012a00: e0bffb17 ldw r2,-20(fp) + } + OS_ENTER_CRITICAL(); + 1012a04: e0bffc15 stw r2,-16(fp) + cnt = pevent->OSEventCnt; + 1012a08: e0bffe17 ldw r2,-8(fp) + 1012a0c: 1080020b ldhu r2,8(r2) + 1012a10: e0bffd0d sth r2,-12(fp) + if (cnt > 0) { /* See if resource is available */ + 1012a14: e0bffd0b ldhu r2,-12(fp) + 1012a18: 1005003a cmpeq r2,r2,zero + 1012a1c: 1000061e bne r2,zero,1012a38 + pevent->OSEventCnt--; /* Yes, decrement semaphore and notify caller */ + 1012a20: e0bffe17 ldw r2,-8(fp) + 1012a24: 1080020b ldhu r2,8(r2) + 1012a28: 10bfffc4 addi r2,r2,-1 + 1012a2c: 1007883a mov r3,r2 + 1012a30: e0bffe17 ldw r2,-8(fp) + 1012a34: 10c0020d sth r3,8(r2) + 1012a38: e0bffc17 ldw r2,-16(fp) + 1012a3c: e0bffa15 stw r2,-24(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1012a40: e0bffa17 ldw r2,-24(fp) + 1012a44: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); + return (cnt); /* Return semaphore count */ + 1012a48: e0bffd0b ldhu r2,-12(fp) + 1012a4c: e0bfff15 stw r2,-4(fp) + 1012a50: e0bfff17 ldw r2,-4(fp) +} + 1012a54: e037883a mov sp,fp + 1012a58: df000017 ldw fp,0(sp) + 1012a5c: dec00104 addi sp,sp,4 + 1012a60: f800283a ret + +01012a64 : +* == (void *)0 if no event control blocks were available +********************************************************************************************************* +*/ + +OS_EVENT *OSSemCreate (INT16U cnt) +{ + 1012a64: defff804 addi sp,sp,-32 + 1012a68: dfc00715 stw ra,28(sp) + 1012a6c: df000615 stw fp,24(sp) + 1012a70: df000604 addi fp,sp,24 + 1012a74: e13ffe0d sth r4,-8(fp) + OS_EVENT *pevent; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 1012a78: e03ffc15 stw zero,-16(fp) +#endif + + + + if (OSIntNesting > 0) { /* See if called from ISR ... */ + 1012a7c: 008040b4 movhi r2,258 + 1012a80: 10b31e04 addi r2,r2,-13192 + 1012a84: 10800003 ldbu r2,0(r2) + 1012a88: 10803fcc andi r2,r2,255 + 1012a8c: 1005003a cmpeq r2,r2,zero + 1012a90: 1000021e bne r2,zero,1012a9c + return ((OS_EVENT *)0); /* ... can't CREATE from an ISR */ + 1012a94: e03fff15 stw zero,-4(fp) + 1012a98: 00003106 br 1012b60 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1012a9c: 0005303a rdctl r2,status + 1012aa0: e0bffb15 stw r2,-20(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1012aa4: e0fffb17 ldw r3,-20(fp) + 1012aa8: 00bfff84 movi r2,-2 + 1012aac: 1884703a and r2,r3,r2 + 1012ab0: 1001703a wrctl status,r2 + + return context; + 1012ab4: e0bffb17 ldw r2,-20(fp) + } + OS_ENTER_CRITICAL(); + 1012ab8: e0bffc15 stw r2,-16(fp) + pevent = OSEventFreeList; /* Get next free event control block */ + 1012abc: 008040b4 movhi r2,258 + 1012ac0: 10b31d04 addi r2,r2,-13196 + 1012ac4: 10800017 ldw r2,0(r2) + 1012ac8: e0bffd15 stw r2,-12(fp) + if (OSEventFreeList != (OS_EVENT *)0) { /* See if pool of free ECB pool was empty */ + 1012acc: 008040b4 movhi r2,258 + 1012ad0: 10b31d04 addi r2,r2,-13196 + 1012ad4: 10800017 ldw r2,0(r2) + 1012ad8: 1005003a cmpeq r2,r2,zero + 1012adc: 1000081e bne r2,zero,1012b00 + OSEventFreeList = (OS_EVENT *)OSEventFreeList->OSEventPtr; + 1012ae0: 008040b4 movhi r2,258 + 1012ae4: 10b31d04 addi r2,r2,-13196 + 1012ae8: 10800017 ldw r2,0(r2) + 1012aec: 10800117 ldw r2,4(r2) + 1012af0: 1007883a mov r3,r2 + 1012af4: 008040b4 movhi r2,258 + 1012af8: 10b31d04 addi r2,r2,-13196 + 1012afc: 10c00015 stw r3,0(r2) + 1012b00: e0bffc17 ldw r2,-16(fp) + 1012b04: e0bffa15 stw r2,-24(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1012b08: e0bffa17 ldw r2,-24(fp) + 1012b0c: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); + if (pevent != (OS_EVENT *)0) { /* Get an event control block */ + 1012b10: e0bffd17 ldw r2,-12(fp) + 1012b14: 1005003a cmpeq r2,r2,zero + 1012b18: 10000f1e bne r2,zero,1012b58 + pevent->OSEventType = OS_EVENT_TYPE_SEM; + 1012b1c: e0fffd17 ldw r3,-12(fp) + 1012b20: 008000c4 movi r2,3 + 1012b24: 18800005 stb r2,0(r3) + pevent->OSEventCnt = cnt; /* Set semaphore value */ + 1012b28: e0fffd17 ldw r3,-12(fp) + 1012b2c: e0bffe0b ldhu r2,-8(fp) + 1012b30: 1880020d sth r2,8(r3) + pevent->OSEventPtr = (void *)0; /* Unlink from ECB free list */ + 1012b34: e0bffd17 ldw r2,-12(fp) + 1012b38: 10000115 stw zero,4(r2) +#if OS_EVENT_NAME_SIZE > 1 + pevent->OSEventName[0] = '?'; /* Unknown name */ + 1012b3c: e0fffd17 ldw r3,-12(fp) + 1012b40: 00800fc4 movi r2,63 + 1012b44: 18800385 stb r2,14(r3) + pevent->OSEventName[1] = OS_ASCII_NUL; + 1012b48: e0bffd17 ldw r2,-12(fp) + 1012b4c: 100003c5 stb zero,15(r2) +#endif + OS_EventWaitListInit(pevent); /* Initialize to 'nobody waiting' on sem. */ + 1012b50: e13ffd17 ldw r4,-12(fp) + 1012b54: 100e82c0 call 100e82c + } + return (pevent); + 1012b58: e0bffd17 ldw r2,-12(fp) + 1012b5c: e0bfff15 stw r2,-4(fp) + 1012b60: e0bfff17 ldw r2,-4(fp) +} + 1012b64: e037883a mov sp,fp + 1012b68: dfc00117 ldw ra,4(sp) + 1012b6c: df000017 ldw fp,0(sp) + 1012b70: dec00204 addi sp,sp,8 + 1012b74: f800283a ret + +01012b78 : +********************************************************************************************************* +*/ + +#if OS_SEM_DEL_EN > 0 +OS_EVENT *OSSemDel (OS_EVENT *pevent, INT8U opt, INT8U *perr) +{ + 1012b78: defff104 addi sp,sp,-60 + 1012b7c: dfc00e15 stw ra,56(sp) + 1012b80: df000d15 stw fp,52(sp) + 1012b84: df000d04 addi fp,sp,52 + 1012b88: e13ffb15 stw r4,-20(fp) + 1012b8c: e1bffd15 stw r6,-12(fp) + 1012b90: e17ffc05 stb r5,-16(fp) + BOOLEAN tasks_waiting; + OS_EVENT *pevent_return; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 1012b94: e03ff815 stw zero,-32(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + 1012b98: e0bffd17 ldw r2,-12(fp) + 1012b9c: 1004c03a cmpne r2,r2,zero + 1012ba0: 1000031e bne r2,zero,1012bb0 + return (pevent); + 1012ba4: e0bffb17 ldw r2,-20(fp) + 1012ba8: e0bfff15 stw r2,-4(fp) + 1012bac: 00009406 br 1012e00 + } + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + 1012bb0: e0bffb17 ldw r2,-20(fp) + 1012bb4: 1004c03a cmpne r2,r2,zero + 1012bb8: 1000061e bne r2,zero,1012bd4 + *perr = OS_ERR_PEVENT_NULL; + 1012bbc: e0fffd17 ldw r3,-12(fp) + 1012bc0: 00800104 movi r2,4 + 1012bc4: 18800005 stb r2,0(r3) + return (pevent); + 1012bc8: e0fffb17 ldw r3,-20(fp) + 1012bcc: e0ffff15 stw r3,-4(fp) + 1012bd0: 00008b06 br 1012e00 + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_SEM) { /* Validate event block type */ + 1012bd4: e0bffb17 ldw r2,-20(fp) + 1012bd8: 10800003 ldbu r2,0(r2) + 1012bdc: 10803fcc andi r2,r2,255 + 1012be0: 108000e0 cmpeqi r2,r2,3 + 1012be4: 1000061e bne r2,zero,1012c00 + *perr = OS_ERR_EVENT_TYPE; + 1012be8: e0fffd17 ldw r3,-12(fp) + 1012bec: 00800044 movi r2,1 + 1012bf0: 18800005 stb r2,0(r3) + return (pevent); + 1012bf4: e0bffb17 ldw r2,-20(fp) + 1012bf8: e0bfff15 stw r2,-4(fp) + 1012bfc: 00008006 br 1012e00 + } + if (OSIntNesting > 0) { /* See if called from ISR ... */ + 1012c00: 008040b4 movhi r2,258 + 1012c04: 10b31e04 addi r2,r2,-13192 + 1012c08: 10800003 ldbu r2,0(r2) + 1012c0c: 10803fcc andi r2,r2,255 + 1012c10: 1005003a cmpeq r2,r2,zero + 1012c14: 1000061e bne r2,zero,1012c30 + *perr = OS_ERR_DEL_ISR; /* ... can't DELETE from an ISR */ + 1012c18: e0fffd17 ldw r3,-12(fp) + 1012c1c: 008003c4 movi r2,15 + 1012c20: 18800005 stb r2,0(r3) + return (pevent); + 1012c24: e0fffb17 ldw r3,-20(fp) + 1012c28: e0ffff15 stw r3,-4(fp) + 1012c2c: 00007406 br 1012e00 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1012c30: 0005303a rdctl r2,status + 1012c34: e0bff715 stw r2,-36(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1012c38: e0fff717 ldw r3,-36(fp) + 1012c3c: 00bfff84 movi r2,-2 + 1012c40: 1884703a and r2,r3,r2 + 1012c44: 1001703a wrctl status,r2 + + return context; + 1012c48: e0bff717 ldw r2,-36(fp) + } + OS_ENTER_CRITICAL(); + 1012c4c: e0bff815 stw r2,-32(fp) + if (pevent->OSEventGrp != 0) { /* See if any tasks waiting on semaphore */ + 1012c50: e0bffb17 ldw r2,-20(fp) + 1012c54: 10800283 ldbu r2,10(r2) + 1012c58: 10803fcc andi r2,r2,255 + 1012c5c: 1005003a cmpeq r2,r2,zero + 1012c60: 1000031e bne r2,zero,1012c70 + tasks_waiting = OS_TRUE; /* Yes */ + 1012c64: 00800044 movi r2,1 + 1012c68: e0bffa05 stb r2,-24(fp) + 1012c6c: 00000106 br 1012c74 + } else { + tasks_waiting = OS_FALSE; /* No */ + 1012c70: e03ffa05 stb zero,-24(fp) + } + switch (opt) { + 1012c74: e0bffc03 ldbu r2,-16(fp) + 1012c78: e0bffe15 stw r2,-8(fp) + 1012c7c: e0fffe17 ldw r3,-8(fp) + 1012c80: 1805003a cmpeq r2,r3,zero + 1012c84: 1000041e bne r2,zero,1012c98 + 1012c88: e0fffe17 ldw r3,-8(fp) + 1012c8c: 18800060 cmpeqi r2,r3,1 + 1012c90: 10002d1e bne r2,zero,1012d48 + 1012c94: 00004f06 br 1012dd4 + case OS_DEL_NO_PEND: /* Delete semaphore only if no task waiting */ + if (tasks_waiting == OS_FALSE) { + 1012c98: e0bffa03 ldbu r2,-24(fp) + 1012c9c: 1004c03a cmpne r2,r2,zero + 1012ca0: 10001a1e bne r2,zero,1012d0c +#if OS_EVENT_NAME_SIZE > 1 + pevent->OSEventName[0] = '?'; /* Unknown name */ + 1012ca4: e0fffb17 ldw r3,-20(fp) + 1012ca8: 00800fc4 movi r2,63 + 1012cac: 18800385 stb r2,14(r3) + pevent->OSEventName[1] = OS_ASCII_NUL; + 1012cb0: e0bffb17 ldw r2,-20(fp) + 1012cb4: 100003c5 stb zero,15(r2) +#endif + pevent->OSEventType = OS_EVENT_TYPE_UNUSED; + 1012cb8: e0bffb17 ldw r2,-20(fp) + 1012cbc: 10000005 stb zero,0(r2) + pevent->OSEventPtr = OSEventFreeList; /* Return Event Control Block to free list */ + 1012cc0: 008040b4 movhi r2,258 + 1012cc4: 10b31d04 addi r2,r2,-13196 + 1012cc8: 10c00017 ldw r3,0(r2) + 1012ccc: e0bffb17 ldw r2,-20(fp) + 1012cd0: 10c00115 stw r3,4(r2) + pevent->OSEventCnt = 0; + 1012cd4: e0bffb17 ldw r2,-20(fp) + 1012cd8: 1000020d sth zero,8(r2) + OSEventFreeList = pevent; /* Get next free event control block */ + 1012cdc: 00c040b4 movhi r3,258 + 1012ce0: 18f31d04 addi r3,r3,-13196 + 1012ce4: e0bffb17 ldw r2,-20(fp) + 1012ce8: 18800015 stw r2,0(r3) + 1012cec: e0bff817 ldw r2,-32(fp) + 1012cf0: e0bff615 stw r2,-40(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1012cf4: e0bff617 ldw r2,-40(fp) + 1012cf8: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + 1012cfc: e0bffd17 ldw r2,-12(fp) + 1012d00: 10000005 stb zero,0(r2) + pevent_return = (OS_EVENT *)0; /* Semaphore has been deleted */ + 1012d04: e03ff915 stw zero,-28(fp) + 1012d08: 00003b06 br 1012df8 + 1012d0c: e0bff817 ldw r2,-32(fp) + 1012d10: e0bff515 stw r2,-44(fp) + 1012d14: e0bff517 ldw r2,-44(fp) + 1012d18: 1001703a wrctl status,r2 + } else { + OS_EXIT_CRITICAL(); + *perr = OS_ERR_TASK_WAITING; + 1012d1c: e0fffd17 ldw r3,-12(fp) + 1012d20: 00801244 movi r2,73 + 1012d24: 18800005 stb r2,0(r3) + pevent_return = pevent; + 1012d28: e0bffb17 ldw r2,-20(fp) + 1012d2c: e0bff915 stw r2,-28(fp) + } + break; + 1012d30: 00003106 br 1012df8 + + case OS_DEL_ALWAYS: /* Always delete the semaphore */ + while (pevent->OSEventGrp != 0) { /* Ready ALL tasks waiting for semaphore */ + (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_SEM, OS_STAT_PEND_OK); + 1012d34: e13ffb17 ldw r4,-20(fp) + 1012d38: 000b883a mov r5,zero + 1012d3c: 01800044 movi r6,1 + 1012d40: 000f883a mov r7,zero + 1012d44: 100e2780 call 100e278 + pevent_return = pevent; + } + break; + + case OS_DEL_ALWAYS: /* Always delete the semaphore */ + while (pevent->OSEventGrp != 0) { /* Ready ALL tasks waiting for semaphore */ + 1012d48: e0bffb17 ldw r2,-20(fp) + 1012d4c: 10800283 ldbu r2,10(r2) + 1012d50: 10803fcc andi r2,r2,255 + 1012d54: 1004c03a cmpne r2,r2,zero + 1012d58: 103ff61e bne r2,zero,1012d34 + (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_SEM, OS_STAT_PEND_OK); + } +#if OS_EVENT_NAME_SIZE > 1 + pevent->OSEventName[0] = '?'; /* Unknown name */ + 1012d5c: e0fffb17 ldw r3,-20(fp) + 1012d60: 00800fc4 movi r2,63 + 1012d64: 18800385 stb r2,14(r3) + pevent->OSEventName[1] = OS_ASCII_NUL; + 1012d68: e0bffb17 ldw r2,-20(fp) + 1012d6c: 100003c5 stb zero,15(r2) +#endif + pevent->OSEventType = OS_EVENT_TYPE_UNUSED; + 1012d70: e0bffb17 ldw r2,-20(fp) + 1012d74: 10000005 stb zero,0(r2) + pevent->OSEventPtr = OSEventFreeList; /* Return Event Control Block to free list */ + 1012d78: 008040b4 movhi r2,258 + 1012d7c: 10b31d04 addi r2,r2,-13196 + 1012d80: 10c00017 ldw r3,0(r2) + 1012d84: e0bffb17 ldw r2,-20(fp) + 1012d88: 10c00115 stw r3,4(r2) + pevent->OSEventCnt = 0; + 1012d8c: e0bffb17 ldw r2,-20(fp) + 1012d90: 1000020d sth zero,8(r2) + OSEventFreeList = pevent; /* Get next free event control block */ + 1012d94: 00c040b4 movhi r3,258 + 1012d98: 18f31d04 addi r3,r3,-13196 + 1012d9c: e0bffb17 ldw r2,-20(fp) + 1012da0: 18800015 stw r2,0(r3) + 1012da4: e0bff817 ldw r2,-32(fp) + 1012da8: e0bff415 stw r2,-48(fp) + 1012dac: e0bff417 ldw r2,-48(fp) + 1012db0: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + if (tasks_waiting == OS_TRUE) { /* Reschedule only if task(s) were waiting */ + 1012db4: e0bffa03 ldbu r2,-24(fp) + 1012db8: 10800058 cmpnei r2,r2,1 + 1012dbc: 1000011e bne r2,zero,1012dc4 + OS_Sched(); /* Find highest priority task ready to run */ + 1012dc0: 100ecb80 call 100ecb8 + } + *perr = OS_ERR_NONE; + 1012dc4: e0bffd17 ldw r2,-12(fp) + 1012dc8: 10000005 stb zero,0(r2) + pevent_return = (OS_EVENT *)0; /* Semaphore has been deleted */ + 1012dcc: e03ff915 stw zero,-28(fp) + break; + 1012dd0: 00000906 br 1012df8 + 1012dd4: e0bff817 ldw r2,-32(fp) + 1012dd8: e0bff315 stw r2,-52(fp) + 1012ddc: e0bff317 ldw r2,-52(fp) + 1012de0: 1001703a wrctl status,r2 + + default: + OS_EXIT_CRITICAL(); + *perr = OS_ERR_INVALID_OPT; + 1012de4: e0fffd17 ldw r3,-12(fp) + 1012de8: 008001c4 movi r2,7 + 1012dec: 18800005 stb r2,0(r3) + pevent_return = pevent; + 1012df0: e0bffb17 ldw r2,-20(fp) + 1012df4: e0bff915 stw r2,-28(fp) + break; + } + return (pevent_return); + 1012df8: e0bff917 ldw r2,-28(fp) + 1012dfc: e0bfff15 stw r2,-4(fp) + 1012e00: e0bfff17 ldw r2,-4(fp) +} + 1012e04: e037883a mov sp,fp + 1012e08: dfc00117 ldw ra,4(sp) + 1012e0c: df000017 ldw fp,0(sp) + 1012e10: dec00204 addi sp,sp,8 + 1012e14: f800283a ret + +01012e18 : +* Returns : none +********************************************************************************************************* +*/ +/*$PAGE*/ +void OSSemPend (OS_EVENT *pevent, INT16U timeout, INT8U *perr) +{ + 1012e18: defff404 addi sp,sp,-48 + 1012e1c: dfc00b15 stw ra,44(sp) + 1012e20: df000a15 stw fp,40(sp) + 1012e24: df000a04 addi fp,sp,40 + 1012e28: e13ffc15 stw r4,-16(fp) + 1012e2c: e1bffe15 stw r6,-8(fp) + 1012e30: e17ffd0d sth r5,-12(fp) +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 1012e34: e03ffb15 stw zero,-20(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + 1012e38: e0bffe17 ldw r2,-8(fp) + 1012e3c: 1005003a cmpeq r2,r2,zero + 1012e40: 10008f1e bne r2,zero,1013080 + return; + } + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + 1012e44: e0bffc17 ldw r2,-16(fp) + 1012e48: 1004c03a cmpne r2,r2,zero + 1012e4c: 1000041e bne r2,zero,1012e60 + *perr = OS_ERR_PEVENT_NULL; + 1012e50: e0fffe17 ldw r3,-8(fp) + 1012e54: 00800104 movi r2,4 + 1012e58: 18800005 stb r2,0(r3) + return; + 1012e5c: 00008806 br 1013080 + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_SEM) { /* Validate event block type */ + 1012e60: e0bffc17 ldw r2,-16(fp) + 1012e64: 10800003 ldbu r2,0(r2) + 1012e68: 10803fcc andi r2,r2,255 + 1012e6c: 108000e0 cmpeqi r2,r2,3 + 1012e70: 1000041e bne r2,zero,1012e84 + *perr = OS_ERR_EVENT_TYPE; + 1012e74: e0fffe17 ldw r3,-8(fp) + 1012e78: 00800044 movi r2,1 + 1012e7c: 18800005 stb r2,0(r3) + return; + 1012e80: 00007f06 br 1013080 + } + if (OSIntNesting > 0) { /* See if called from ISR ... */ + 1012e84: 008040b4 movhi r2,258 + 1012e88: 10b31e04 addi r2,r2,-13192 + 1012e8c: 10800003 ldbu r2,0(r2) + 1012e90: 10803fcc andi r2,r2,255 + 1012e94: 1005003a cmpeq r2,r2,zero + 1012e98: 1000041e bne r2,zero,1012eac + *perr = OS_ERR_PEND_ISR; /* ... can't PEND from an ISR */ + 1012e9c: e0fffe17 ldw r3,-8(fp) + 1012ea0: 00800084 movi r2,2 + 1012ea4: 18800005 stb r2,0(r3) + return; + 1012ea8: 00007506 br 1013080 + } + if (OSLockNesting > 0) { /* See if called with scheduler locked ... */ + 1012eac: 008040b4 movhi r2,258 + 1012eb0: 10b31004 addi r2,r2,-13248 + 1012eb4: 10800003 ldbu r2,0(r2) + 1012eb8: 10803fcc andi r2,r2,255 + 1012ebc: 1005003a cmpeq r2,r2,zero + 1012ec0: 1000041e bne r2,zero,1012ed4 + *perr = OS_ERR_PEND_LOCKED; /* ... can't PEND when locked */ + 1012ec4: e0fffe17 ldw r3,-8(fp) + 1012ec8: 00800344 movi r2,13 + 1012ecc: 18800005 stb r2,0(r3) + return; + 1012ed0: 00006b06 br 1013080 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1012ed4: 0005303a rdctl r2,status + 1012ed8: e0bffa15 stw r2,-24(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1012edc: e0fffa17 ldw r3,-24(fp) + 1012ee0: 00bfff84 movi r2,-2 + 1012ee4: 1884703a and r2,r3,r2 + 1012ee8: 1001703a wrctl status,r2 + + return context; + 1012eec: e0bffa17 ldw r2,-24(fp) + } + OS_ENTER_CRITICAL(); + 1012ef0: e0bffb15 stw r2,-20(fp) + if (pevent->OSEventCnt > 0) { /* If sem. is positive, resource available ... */ + 1012ef4: e0bffc17 ldw r2,-16(fp) + 1012ef8: 1080020b ldhu r2,8(r2) + 1012efc: 10bfffcc andi r2,r2,65535 + 1012f00: 1005003a cmpeq r2,r2,zero + 1012f04: 10000d1e bne r2,zero,1012f3c + pevent->OSEventCnt--; /* ... decrement semaphore only if positive. */ + 1012f08: e0bffc17 ldw r2,-16(fp) + 1012f0c: 1080020b ldhu r2,8(r2) + 1012f10: 10bfffc4 addi r2,r2,-1 + 1012f14: 1007883a mov r3,r2 + 1012f18: e0bffc17 ldw r2,-16(fp) + 1012f1c: 10c0020d sth r3,8(r2) + 1012f20: e0bffb17 ldw r2,-20(fp) + 1012f24: e0bff915 stw r2,-28(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1012f28: e0bff917 ldw r2,-28(fp) + 1012f2c: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + 1012f30: e0bffe17 ldw r2,-8(fp) + 1012f34: 10000005 stb zero,0(r2) + return; + 1012f38: 00005106 br 1013080 + } + /* Otherwise, must wait until event occurs */ + OSTCBCur->OSTCBStat |= OS_STAT_SEM; /* Resource not available, pend on semaphore */ + 1012f3c: 008040b4 movhi r2,258 + 1012f40: 10b31f04 addi r2,r2,-13188 + 1012f44: 10c00017 ldw r3,0(r2) + 1012f48: 008040b4 movhi r2,258 + 1012f4c: 10b31f04 addi r2,r2,-13188 + 1012f50: 10800017 ldw r2,0(r2) + 1012f54: 10800c03 ldbu r2,48(r2) + 1012f58: 10800054 ori r2,r2,1 + 1012f5c: 18800c05 stb r2,48(r3) + OSTCBCur->OSTCBStatPend = OS_STAT_PEND_OK; + 1012f60: 008040b4 movhi r2,258 + 1012f64: 10b31f04 addi r2,r2,-13188 + 1012f68: 10800017 ldw r2,0(r2) + 1012f6c: 10000c45 stb zero,49(r2) + OSTCBCur->OSTCBDly = timeout; /* Store pend timeout in TCB */ + 1012f70: 008040b4 movhi r2,258 + 1012f74: 10b31f04 addi r2,r2,-13188 + 1012f78: 10c00017 ldw r3,0(r2) + 1012f7c: e0bffd0b ldhu r2,-12(fp) + 1012f80: 18800b8d sth r2,46(r3) + OS_EventTaskWait(pevent); /* Suspend task until event or timeout occurs */ + 1012f84: e13ffc17 ldw r4,-16(fp) + 1012f88: 100e40c0 call 100e40c + 1012f8c: e0bffb17 ldw r2,-20(fp) + 1012f90: e0bff815 stw r2,-32(fp) + 1012f94: e0bff817 ldw r2,-32(fp) + 1012f98: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + OS_Sched(); /* Find next highest priority task ready */ + 1012f9c: 100ecb80 call 100ecb8 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1012fa0: 0005303a rdctl r2,status + 1012fa4: e0bff715 stw r2,-36(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1012fa8: e0fff717 ldw r3,-36(fp) + 1012fac: 00bfff84 movi r2,-2 + 1012fb0: 1884703a and r2,r3,r2 + 1012fb4: 1001703a wrctl status,r2 + + return context; + 1012fb8: e0bff717 ldw r2,-36(fp) + OS_ENTER_CRITICAL(); + 1012fbc: e0bffb15 stw r2,-20(fp) + switch (OSTCBCur->OSTCBStatPend) { /* See if we timed-out or aborted */ + 1012fc0: 008040b4 movhi r2,258 + 1012fc4: 10b31f04 addi r2,r2,-13188 + 1012fc8: 10800017 ldw r2,0(r2) + 1012fcc: 10800c43 ldbu r2,49(r2) + 1012fd0: 10803fcc andi r2,r2,255 + 1012fd4: e0bfff15 stw r2,-4(fp) + 1012fd8: e0ffff17 ldw r3,-4(fp) + 1012fdc: 1805003a cmpeq r2,r3,zero + 1012fe0: 1000041e bne r2,zero,1012ff4 + 1012fe4: e0ffff17 ldw r3,-4(fp) + 1012fe8: 188000a0 cmpeqi r2,r3,2 + 1012fec: 1000041e bne r2,zero,1013000 + 1012ff0: 00000706 br 1013010 + case OS_STAT_PEND_OK: + *perr = OS_ERR_NONE; + 1012ff4: e0bffe17 ldw r2,-8(fp) + 1012ff8: 10000005 stb zero,0(r2) + break; + 1012ffc: 00000c06 br 1013030 + + case OS_STAT_PEND_ABORT: + *perr = OS_ERR_PEND_ABORT; /* Indicate that we aborted */ + 1013000: e0fffe17 ldw r3,-8(fp) + 1013004: 00800384 movi r2,14 + 1013008: 18800005 stb r2,0(r3) + break; + 101300c: 00000806 br 1013030 + + case OS_STAT_PEND_TO: + default: + OS_EventTaskRemove(OSTCBCur, pevent); + 1013010: 008040b4 movhi r2,258 + 1013014: 10b31f04 addi r2,r2,-13188 + 1013018: 11000017 ldw r4,0(r2) + 101301c: e17ffc17 ldw r5,-16(fp) + 1013020: 100e6700 call 100e670 + *perr = OS_ERR_TIMEOUT; /* Indicate that we didn't get event within TO */ + 1013024: e0fffe17 ldw r3,-8(fp) + 1013028: 00800284 movi r2,10 + 101302c: 18800005 stb r2,0(r3) + break; + } + OSTCBCur->OSTCBStat = OS_STAT_RDY; /* Set task status to ready */ + 1013030: 008040b4 movhi r2,258 + 1013034: 10b31f04 addi r2,r2,-13188 + 1013038: 10800017 ldw r2,0(r2) + 101303c: 10000c05 stb zero,48(r2) + OSTCBCur->OSTCBStatPend = OS_STAT_PEND_OK; /* Clear pend status */ + 1013040: 008040b4 movhi r2,258 + 1013044: 10b31f04 addi r2,r2,-13188 + 1013048: 10800017 ldw r2,0(r2) + 101304c: 10000c45 stb zero,49(r2) + OSTCBCur->OSTCBEventPtr = (OS_EVENT *)0; /* Clear event pointers */ + 1013050: 008040b4 movhi r2,258 + 1013054: 10b31f04 addi r2,r2,-13188 + 1013058: 10800017 ldw r2,0(r2) + 101305c: 10000715 stw zero,28(r2) +#if (OS_EVENT_MULTI_EN > 0) + OSTCBCur->OSTCBEventMultiPtr = (OS_EVENT **)0; + 1013060: 008040b4 movhi r2,258 + 1013064: 10b31f04 addi r2,r2,-13188 + 1013068: 10800017 ldw r2,0(r2) + 101306c: 10000815 stw zero,32(r2) + 1013070: e0bffb17 ldw r2,-20(fp) + 1013074: e0bff615 stw r2,-40(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1013078: e0bff617 ldw r2,-40(fp) + 101307c: 1001703a wrctl status,r2 +#endif + OS_EXIT_CRITICAL(); +} + 1013080: e037883a mov sp,fp + 1013084: dfc00117 ldw ra,4(sp) + 1013088: df000017 ldw fp,0(sp) + 101308c: dec00204 addi sp,sp,8 + 1013090: f800283a ret + +01013094 : +********************************************************************************************************* +*/ + +#if OS_SEM_PEND_ABORT_EN > 0 +INT8U OSSemPendAbort (OS_EVENT *pevent, INT8U opt, INT8U *perr) +{ + 1013094: defff504 addi sp,sp,-44 + 1013098: dfc00a15 stw ra,40(sp) + 101309c: df000915 stw fp,36(sp) + 10130a0: df000904 addi fp,sp,36 + 10130a4: e13ffc15 stw r4,-16(fp) + 10130a8: e1bffe15 stw r6,-8(fp) + 10130ac: e17ffd05 stb r5,-12(fp) + INT8U nbr_tasks; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 10130b0: e03ffa15 stw zero,-24(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + 10130b4: e0bffe17 ldw r2,-8(fp) + 10130b8: 1004c03a cmpne r2,r2,zero + 10130bc: 1000021e bne r2,zero,10130c8 + return (0); + 10130c0: e03fff15 stw zero,-4(fp) + 10130c4: 00004c06 br 10131f8 + } + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + 10130c8: e0bffc17 ldw r2,-16(fp) + 10130cc: 1004c03a cmpne r2,r2,zero + 10130d0: 1000051e bne r2,zero,10130e8 + *perr = OS_ERR_PEVENT_NULL; + 10130d4: e0fffe17 ldw r3,-8(fp) + 10130d8: 00800104 movi r2,4 + 10130dc: 18800005 stb r2,0(r3) + return (0); + 10130e0: e03fff15 stw zero,-4(fp) + 10130e4: 00004406 br 10131f8 + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_SEM) { /* Validate event block type */ + 10130e8: e0bffc17 ldw r2,-16(fp) + 10130ec: 10800003 ldbu r2,0(r2) + 10130f0: 10803fcc andi r2,r2,255 + 10130f4: 108000e0 cmpeqi r2,r2,3 + 10130f8: 1000051e bne r2,zero,1013110 + *perr = OS_ERR_EVENT_TYPE; + 10130fc: e0fffe17 ldw r3,-8(fp) + 1013100: 00800044 movi r2,1 + 1013104: 18800005 stb r2,0(r3) + return (0); + 1013108: e03fff15 stw zero,-4(fp) + 101310c: 00003a06 br 10131f8 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1013110: 0005303a rdctl r2,status + 1013114: e0bff915 stw r2,-28(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1013118: e0fff917 ldw r3,-28(fp) + 101311c: 00bfff84 movi r2,-2 + 1013120: 1884703a and r2,r3,r2 + 1013124: 1001703a wrctl status,r2 + + return context; + 1013128: e0bff917 ldw r2,-28(fp) + } + OS_ENTER_CRITICAL(); + 101312c: e0bffa15 stw r2,-24(fp) + if (pevent->OSEventGrp != 0) { /* See if any task waiting on semaphore? */ + 1013130: e0bffc17 ldw r2,-16(fp) + 1013134: 10800283 ldbu r2,10(r2) + 1013138: 10803fcc andi r2,r2,255 + 101313c: 1005003a cmpeq r2,r2,zero + 1013140: 1000261e bne r2,zero,10131dc + nbr_tasks = 0; + 1013144: e03ffb05 stb zero,-20(fp) + switch (opt) { + 1013148: e0bffd03 ldbu r2,-12(fp) + 101314c: 10800060 cmpeqi r2,r2,1 + 1013150: 1000091e bne r2,zero,1013178 + 1013154: 00000e06 br 1013190 + case OS_PEND_OPT_BROADCAST: /* Do we need to abort ALL waiting tasks? */ + while (pevent->OSEventGrp != 0) { /* Yes, ready ALL tasks waiting on semaphore */ + (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_SEM, OS_STAT_PEND_ABORT); + 1013158: e13ffc17 ldw r4,-16(fp) + 101315c: 000b883a mov r5,zero + 1013160: 01800044 movi r6,1 + 1013164: 01c00084 movi r7,2 + 1013168: 100e2780 call 100e278 + nbr_tasks++; + 101316c: e0bffb03 ldbu r2,-20(fp) + 1013170: 10800044 addi r2,r2,1 + 1013174: e0bffb05 stb r2,-20(fp) + OS_ENTER_CRITICAL(); + if (pevent->OSEventGrp != 0) { /* See if any task waiting on semaphore? */ + nbr_tasks = 0; + switch (opt) { + case OS_PEND_OPT_BROADCAST: /* Do we need to abort ALL waiting tasks? */ + while (pevent->OSEventGrp != 0) { /* Yes, ready ALL tasks waiting on semaphore */ + 1013178: e0bffc17 ldw r2,-16(fp) + 101317c: 10800283 ldbu r2,10(r2) + 1013180: 10803fcc andi r2,r2,255 + 1013184: 1004c03a cmpne r2,r2,zero + 1013188: 103ff31e bne r2,zero,1013158 + (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_SEM, OS_STAT_PEND_ABORT); + nbr_tasks++; + } + break; + 101318c: 00000806 br 10131b0 + + case OS_PEND_OPT_NONE: + default: /* No, ready HPT waiting on semaphore */ + (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_SEM, OS_STAT_PEND_ABORT); + 1013190: e13ffc17 ldw r4,-16(fp) + 1013194: 000b883a mov r5,zero + 1013198: 01800044 movi r6,1 + 101319c: 01c00084 movi r7,2 + 10131a0: 100e2780 call 100e278 + nbr_tasks++; + 10131a4: e0bffb03 ldbu r2,-20(fp) + 10131a8: 10800044 addi r2,r2,1 + 10131ac: e0bffb05 stb r2,-20(fp) + 10131b0: e0bffa17 ldw r2,-24(fp) + 10131b4: e0bff815 stw r2,-32(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 10131b8: e0bff817 ldw r2,-32(fp) + 10131bc: 1001703a wrctl status,r2 + break; + } + OS_EXIT_CRITICAL(); + OS_Sched(); /* Find HPT ready to run */ + 10131c0: 100ecb80 call 100ecb8 + *perr = OS_ERR_PEND_ABORT; + 10131c4: e0fffe17 ldw r3,-8(fp) + 10131c8: 00800384 movi r2,14 + 10131cc: 18800005 stb r2,0(r3) + return (nbr_tasks); + 10131d0: e0bffb03 ldbu r2,-20(fp) + 10131d4: e0bfff15 stw r2,-4(fp) + 10131d8: 00000706 br 10131f8 + 10131dc: e0bffa17 ldw r2,-24(fp) + 10131e0: e0bff715 stw r2,-36(fp) + 10131e4: e0bff717 ldw r2,-36(fp) + 10131e8: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + 10131ec: e0bffe17 ldw r2,-8(fp) + 10131f0: 10000005 stb zero,0(r2) + return (0); /* No tasks waiting on semaphore */ + 10131f4: e03fff15 stw zero,-4(fp) + 10131f8: e0bfff17 ldw r2,-4(fp) +} + 10131fc: e037883a mov sp,fp + 1013200: dfc00117 ldw ra,4(sp) + 1013204: df000017 ldw fp,0(sp) + 1013208: dec00204 addi sp,sp,8 + 101320c: f800283a ret + +01013210 : +* OS_ERR_PEVENT_NULL If 'pevent' is a NULL pointer. +********************************************************************************************************* +*/ + +INT8U OSSemPost (OS_EVENT *pevent) +{ + 1013210: defff704 addi sp,sp,-36 + 1013214: dfc00815 stw ra,32(sp) + 1013218: df000715 stw fp,28(sp) + 101321c: df000704 addi fp,sp,28 + 1013220: e13ffe15 stw r4,-8(fp) +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 1013224: e03ffd15 stw zero,-12(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + 1013228: e0bffe17 ldw r2,-8(fp) + 101322c: 1004c03a cmpne r2,r2,zero + 1013230: 1000031e bne r2,zero,1013240 + return (OS_ERR_PEVENT_NULL); + 1013234: 00800104 movi r2,4 + 1013238: e0bfff15 stw r2,-4(fp) + 101323c: 00003806 br 1013320 + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_SEM) { /* Validate event block type */ + 1013240: e0bffe17 ldw r2,-8(fp) + 1013244: 10800003 ldbu r2,0(r2) + 1013248: 10803fcc andi r2,r2,255 + 101324c: 108000e0 cmpeqi r2,r2,3 + 1013250: 1000031e bne r2,zero,1013260 + return (OS_ERR_EVENT_TYPE); + 1013254: 00800044 movi r2,1 + 1013258: e0bfff15 stw r2,-4(fp) + 101325c: 00003006 br 1013320 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1013260: 0005303a rdctl r2,status + 1013264: e0bffc15 stw r2,-16(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1013268: e0fffc17 ldw r3,-16(fp) + 101326c: 00bfff84 movi r2,-2 + 1013270: 1884703a and r2,r3,r2 + 1013274: 1001703a wrctl status,r2 + + return context; + 1013278: e0bffc17 ldw r2,-16(fp) + } + OS_ENTER_CRITICAL(); + 101327c: e0bffd15 stw r2,-12(fp) + if (pevent->OSEventGrp != 0) { /* See if any task waiting for semaphore */ + 1013280: e0bffe17 ldw r2,-8(fp) + 1013284: 10800283 ldbu r2,10(r2) + 1013288: 10803fcc andi r2,r2,255 + 101328c: 1005003a cmpeq r2,r2,zero + 1013290: 10000c1e bne r2,zero,10132c4 + /* Ready HPT waiting on event */ + (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_SEM, OS_STAT_PEND_OK); + 1013294: e13ffe17 ldw r4,-8(fp) + 1013298: 000b883a mov r5,zero + 101329c: 01800044 movi r6,1 + 10132a0: 000f883a mov r7,zero + 10132a4: 100e2780 call 100e278 + 10132a8: e0bffd17 ldw r2,-12(fp) + 10132ac: e0bffb15 stw r2,-20(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 10132b0: e0bffb17 ldw r2,-20(fp) + 10132b4: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + OS_Sched(); /* Find HPT ready to run */ + 10132b8: 100ecb80 call 100ecb8 + return (OS_ERR_NONE); + 10132bc: e03fff15 stw zero,-4(fp) + 10132c0: 00001706 br 1013320 + } + if (pevent->OSEventCnt < 65535u) { /* Make sure semaphore will not overflow */ + 10132c4: e0bffe17 ldw r2,-8(fp) + 10132c8: 1080020b ldhu r2,8(r2) + 10132cc: 10ffffcc andi r3,r2,65535 + 10132d0: 00bfffd4 movui r2,65535 + 10132d4: 18800c26 beq r3,r2,1013308 + pevent->OSEventCnt++; /* Increment semaphore count to register event */ + 10132d8: e0bffe17 ldw r2,-8(fp) + 10132dc: 1080020b ldhu r2,8(r2) + 10132e0: 10800044 addi r2,r2,1 + 10132e4: 1007883a mov r3,r2 + 10132e8: e0bffe17 ldw r2,-8(fp) + 10132ec: 10c0020d sth r3,8(r2) + 10132f0: e0bffd17 ldw r2,-12(fp) + 10132f4: e0bffa15 stw r2,-24(fp) + 10132f8: e0bffa17 ldw r2,-24(fp) + 10132fc: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_NONE); + 1013300: e03fff15 stw zero,-4(fp) + 1013304: 00000606 br 1013320 + 1013308: e0bffd17 ldw r2,-12(fp) + 101330c: e0bff915 stw r2,-28(fp) + 1013310: e0bff917 ldw r2,-28(fp) + 1013314: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); /* Semaphore value has reached its maximum */ + return (OS_ERR_SEM_OVF); + 1013318: 00800c84 movi r2,50 + 101331c: e0bfff15 stw r2,-4(fp) + 1013320: e0bfff17 ldw r2,-4(fp) +} + 1013324: e037883a mov sp,fp + 1013328: dfc00117 ldw ra,4(sp) + 101332c: df000017 ldw fp,0(sp) + 1013330: dec00204 addi sp,sp,8 + 1013334: f800283a ret + +01013338 : +********************************************************************************************************* +*/ + +#if OS_SEM_QUERY_EN > 0 +INT8U OSSemQuery (OS_EVENT *pevent, OS_SEM_DATA *p_sem_data) +{ + 1013338: defff604 addi sp,sp,-40 + 101333c: df000915 stw fp,36(sp) + 1013340: df000904 addi fp,sp,36 + 1013344: e13ffd15 stw r4,-12(fp) + 1013348: e17ffe15 stw r5,-8(fp) + INT16U *psrc; + INT16U *pdest; +#endif + INT8U i; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 101334c: e03ff915 stw zero,-28(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + 1013350: e0bffd17 ldw r2,-12(fp) + 1013354: 1004c03a cmpne r2,r2,zero + 1013358: 1000031e bne r2,zero,1013368 + return (OS_ERR_PEVENT_NULL); + 101335c: 00800104 movi r2,4 + 1013360: e0bfff15 stw r2,-4(fp) + 1013364: 00003b06 br 1013454 + } + if (p_sem_data == (OS_SEM_DATA *)0) { /* Validate 'p_sem_data' */ + 1013368: e0bffe17 ldw r2,-8(fp) + 101336c: 1004c03a cmpne r2,r2,zero + 1013370: 1000031e bne r2,zero,1013380 + return (OS_ERR_PDATA_NULL); + 1013374: 00800244 movi r2,9 + 1013378: e0bfff15 stw r2,-4(fp) + 101337c: 00003506 br 1013454 + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_SEM) { /* Validate event block type */ + 1013380: e0bffd17 ldw r2,-12(fp) + 1013384: 10800003 ldbu r2,0(r2) + 1013388: 10803fcc andi r2,r2,255 + 101338c: 108000e0 cmpeqi r2,r2,3 + 1013390: 1000031e bne r2,zero,10133a0 + return (OS_ERR_EVENT_TYPE); + 1013394: 00800044 movi r2,1 + 1013398: e0bfff15 stw r2,-4(fp) + 101339c: 00002d06 br 1013454 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 10133a0: 0005303a rdctl r2,status + 10133a4: e0bff815 stw r2,-32(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 10133a8: e0fff817 ldw r3,-32(fp) + 10133ac: 00bfff84 movi r2,-2 + 10133b0: 1884703a and r2,r3,r2 + 10133b4: 1001703a wrctl status,r2 + + return context; + 10133b8: e0bff817 ldw r2,-32(fp) + } + OS_ENTER_CRITICAL(); + 10133bc: e0bff915 stw r2,-28(fp) + p_sem_data->OSEventGrp = pevent->OSEventGrp; /* Copy message mailbox wait list */ + 10133c0: e0bffd17 ldw r2,-12(fp) + 10133c4: 10c00283 ldbu r3,10(r2) + 10133c8: e0bffe17 ldw r2,-8(fp) + 10133cc: 10c00145 stb r3,5(r2) + psrc = &pevent->OSEventTbl[0]; + 10133d0: e0bffd17 ldw r2,-12(fp) + 10133d4: 108002c4 addi r2,r2,11 + 10133d8: e0bffc15 stw r2,-16(fp) + pdest = &p_sem_data->OSEventTbl[0]; + 10133dc: e0bffe17 ldw r2,-8(fp) + 10133e0: 10800084 addi r2,r2,2 + 10133e4: e0bffb15 stw r2,-20(fp) + for (i = 0; i < OS_EVENT_TBL_SIZE; i++) { + 10133e8: e03ffa05 stb zero,-24(fp) + 10133ec: 00000d06 br 1013424 + *pdest++ = *psrc++; + 10133f0: e0bffc17 ldw r2,-16(fp) + 10133f4: 10c00003 ldbu r3,0(r2) + 10133f8: e0bffb17 ldw r2,-20(fp) + 10133fc: 10c00005 stb r3,0(r2) + 1013400: e0bffb17 ldw r2,-20(fp) + 1013404: 10800044 addi r2,r2,1 + 1013408: e0bffb15 stw r2,-20(fp) + 101340c: e0bffc17 ldw r2,-16(fp) + 1013410: 10800044 addi r2,r2,1 + 1013414: e0bffc15 stw r2,-16(fp) + } + OS_ENTER_CRITICAL(); + p_sem_data->OSEventGrp = pevent->OSEventGrp; /* Copy message mailbox wait list */ + psrc = &pevent->OSEventTbl[0]; + pdest = &p_sem_data->OSEventTbl[0]; + for (i = 0; i < OS_EVENT_TBL_SIZE; i++) { + 1013418: e0bffa03 ldbu r2,-24(fp) + 101341c: 10800044 addi r2,r2,1 + 1013420: e0bffa05 stb r2,-24(fp) + 1013424: e0bffa03 ldbu r2,-24(fp) + 1013428: 108000f0 cmpltui r2,r2,3 + 101342c: 103ff01e bne r2,zero,10133f0 + *pdest++ = *psrc++; + } + p_sem_data->OSCnt = pevent->OSEventCnt; /* Get semaphore count */ + 1013430: e0bffd17 ldw r2,-12(fp) + 1013434: 10c0020b ldhu r3,8(r2) + 1013438: e0bffe17 ldw r2,-8(fp) + 101343c: 10c0000d sth r3,0(r2) + 1013440: e0bff917 ldw r2,-28(fp) + 1013444: e0bff715 stw r2,-36(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1013448: e0bff717 ldw r2,-36(fp) + 101344c: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_NONE); + 1013450: e03fff15 stw zero,-4(fp) + 1013454: e0bfff17 ldw r2,-4(fp) +} + 1013458: e037883a mov sp,fp + 101345c: df000017 ldw fp,0(sp) + 1013460: dec00104 addi sp,sp,4 + 1013464: f800283a ret + +01013468 : +********************************************************************************************************* +*/ + +#if OS_SEM_SET_EN > 0 +void OSSemSet (OS_EVENT *pevent, INT16U cnt, INT8U *perr) +{ + 1013468: defff904 addi sp,sp,-28 + 101346c: df000615 stw fp,24(sp) + 1013470: df000604 addi fp,sp,24 + 1013474: e13ffd15 stw r4,-12(fp) + 1013478: e1bfff15 stw r6,-4(fp) + 101347c: e17ffe0d sth r5,-8(fp) +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 1013480: e03ffc15 stw zero,-16(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + 1013484: e0bfff17 ldw r2,-4(fp) + 1013488: 1005003a cmpeq r2,r2,zero + 101348c: 1000331e bne r2,zero,101355c + return; + } + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + 1013490: e0bffd17 ldw r2,-12(fp) + 1013494: 1004c03a cmpne r2,r2,zero + 1013498: 1000041e bne r2,zero,10134ac + *perr = OS_ERR_PEVENT_NULL; + 101349c: e0ffff17 ldw r3,-4(fp) + 10134a0: 00800104 movi r2,4 + 10134a4: 18800005 stb r2,0(r3) + return; + 10134a8: 00002c06 br 101355c + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_SEM) { /* Validate event block type */ + 10134ac: e0bffd17 ldw r2,-12(fp) + 10134b0: 10800003 ldbu r2,0(r2) + 10134b4: 10803fcc andi r2,r2,255 + 10134b8: 108000e0 cmpeqi r2,r2,3 + 10134bc: 1000041e bne r2,zero,10134d0 + *perr = OS_ERR_EVENT_TYPE; + 10134c0: e0ffff17 ldw r3,-4(fp) + 10134c4: 00800044 movi r2,1 + 10134c8: 18800005 stb r2,0(r3) + return; + 10134cc: 00002306 br 101355c +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 10134d0: 0005303a rdctl r2,status + 10134d4: e0bffb15 stw r2,-20(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 10134d8: e0fffb17 ldw r3,-20(fp) + 10134dc: 00bfff84 movi r2,-2 + 10134e0: 1884703a and r2,r3,r2 + 10134e4: 1001703a wrctl status,r2 + + return context; + 10134e8: e0bffb17 ldw r2,-20(fp) + } + OS_ENTER_CRITICAL(); + 10134ec: e0bffc15 stw r2,-16(fp) + *perr = OS_ERR_NONE; + 10134f0: e0bfff17 ldw r2,-4(fp) + 10134f4: 10000005 stb zero,0(r2) + if (pevent->OSEventCnt > 0) { /* See if semaphore already has a count */ + 10134f8: e0bffd17 ldw r2,-12(fp) + 10134fc: 1080020b ldhu r2,8(r2) + 1013500: 10bfffcc andi r2,r2,65535 + 1013504: 1005003a cmpeq r2,r2,zero + 1013508: 1000041e bne r2,zero,101351c + pevent->OSEventCnt = cnt; /* Yes, set it to the new value specified. */ + 101350c: e0fffd17 ldw r3,-12(fp) + 1013510: e0bffe0b ldhu r2,-8(fp) + 1013514: 1880020d sth r2,8(r3) + 1013518: 00000c06 br 101354c + } else { /* No */ + if (pevent->OSEventGrp == 0) { /* See if task(s) waiting? */ + 101351c: e0bffd17 ldw r2,-12(fp) + 1013520: 10800283 ldbu r2,10(r2) + 1013524: 10803fcc andi r2,r2,255 + 1013528: 1004c03a cmpne r2,r2,zero + 101352c: 1000041e bne r2,zero,1013540 + pevent->OSEventCnt = cnt; /* No, OK to set the value */ + 1013530: e0fffd17 ldw r3,-12(fp) + 1013534: e0bffe0b ldhu r2,-8(fp) + 1013538: 1880020d sth r2,8(r3) + 101353c: 00000306 br 101354c + } else { + *perr = OS_ERR_TASK_WAITING; + 1013540: e0ffff17 ldw r3,-4(fp) + 1013544: 00801244 movi r2,73 + 1013548: 18800005 stb r2,0(r3) + 101354c: e0bffc17 ldw r2,-16(fp) + 1013550: e0bffa15 stw r2,-24(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1013554: e0bffa17 ldw r2,-24(fp) + 1013558: 1001703a wrctl status,r2 + } + } + OS_EXIT_CRITICAL(); +} + 101355c: e037883a mov sp,fp + 1013560: df000017 ldw fp,0(sp) + 1013564: dec00104 addi sp,sp,4 + 1013568: f800283a ret + +0101356c : +********************************************************************************************************* +*/ + +#if OS_TASK_CHANGE_PRIO_EN > 0 +INT8U OSTaskChangePrio (INT8U oldprio, INT8U newprio) +{ + 101356c: defff004 addi sp,sp,-64 + 1013570: dfc00f15 stw ra,60(sp) + 1013574: df000e15 stw fp,56(sp) + 1013578: df000e04 addi fp,sp,56 + 101357c: e13ffd05 stb r4,-12(fp) + 1013580: e17ffe05 stb r5,-8(fp) + INT16U bitx_new; + INT16U bity_old; + INT16U bitx_old; +#endif +#if OS_CRITICAL_METHOD == 3 + OS_CPU_SR cpu_sr = 0; /* Storage for CPU status register */ + 1013584: e03ff715 stw zero,-36(fp) +#endif + + +/*$PAGE*/ +#if OS_ARG_CHK_EN > 0 + if (oldprio >= OS_LOWEST_PRIO) { + 1013588: e0bffd03 ldbu r2,-12(fp) + 101358c: 10800530 cmpltui r2,r2,20 + 1013590: 1000061e bne r2,zero,10135ac + if (oldprio != OS_PRIO_SELF) { + 1013594: e0bffd03 ldbu r2,-12(fp) + 1013598: 10803fe0 cmpeqi r2,r2,255 + 101359c: 1000031e bne r2,zero,10135ac + return (OS_ERR_PRIO_INVALID); + 10135a0: 00800a84 movi r2,42 + 10135a4: e0bfff15 stw r2,-4(fp) + 10135a8: 00014706 br 1013ac8 + } + } + if (newprio >= OS_LOWEST_PRIO) { + 10135ac: e0bffe03 ldbu r2,-8(fp) + 10135b0: 10800530 cmpltui r2,r2,20 + 10135b4: 1000031e bne r2,zero,10135c4 + return (OS_ERR_PRIO_INVALID); + 10135b8: 00800a84 movi r2,42 + 10135bc: e0bfff15 stw r2,-4(fp) + 10135c0: 00014106 br 1013ac8 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 10135c4: 0005303a rdctl r2,status + 10135c8: e0bff615 stw r2,-40(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 10135cc: e0fff617 ldw r3,-40(fp) + 10135d0: 00bfff84 movi r2,-2 + 10135d4: 1884703a and r2,r3,r2 + 10135d8: 1001703a wrctl status,r2 + + return context; + 10135dc: e0bff617 ldw r2,-40(fp) + } +#endif + OS_ENTER_CRITICAL(); + 10135e0: e0bff715 stw r2,-36(fp) + if (OSTCBPrioTbl[newprio] != (OS_TCB *)0) { /* New priority must not already exist */ + 10135e4: e0bffe03 ldbu r2,-8(fp) + 10135e8: 00c040b4 movhi r3,258 + 10135ec: 18d9a904 addi r3,r3,26276 + 10135f0: 1085883a add r2,r2,r2 + 10135f4: 1085883a add r2,r2,r2 + 10135f8: 10c5883a add r2,r2,r3 + 10135fc: 10800017 ldw r2,0(r2) + 1013600: 1005003a cmpeq r2,r2,zero + 1013604: 1000071e bne r2,zero,1013624 + 1013608: e0bff717 ldw r2,-36(fp) + 101360c: e0bff515 stw r2,-44(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1013610: e0bff517 ldw r2,-44(fp) + 1013614: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_PRIO_EXIST); + 1013618: 00800a04 movi r2,40 + 101361c: e0bfff15 stw r2,-4(fp) + 1013620: 00012906 br 1013ac8 + } + if (oldprio == OS_PRIO_SELF) { /* See if changing self */ + 1013624: e0bffd03 ldbu r2,-12(fp) + 1013628: 10803fd8 cmpnei r2,r2,255 + 101362c: 1000051e bne r2,zero,1013644 + oldprio = OSTCBCur->OSTCBPrio; /* Yes, get priority */ + 1013630: 008040b4 movhi r2,258 + 1013634: 10b31f04 addi r2,r2,-13188 + 1013638: 10800017 ldw r2,0(r2) + 101363c: 10800c83 ldbu r2,50(r2) + 1013640: e0bffd05 stb r2,-12(fp) + } + ptcb = OSTCBPrioTbl[oldprio]; + 1013644: e0bffd03 ldbu r2,-12(fp) + 1013648: 00c040b4 movhi r3,258 + 101364c: 18d9a904 addi r3,r3,26276 + 1013650: 1085883a add r2,r2,r2 + 1013654: 1085883a add r2,r2,r2 + 1013658: 10c5883a add r2,r2,r3 + 101365c: 10800017 ldw r2,0(r2) + 1013660: e0bffa15 stw r2,-24(fp) + if (ptcb == (OS_TCB *)0) { /* Does task to change exist? */ + 1013664: e0bffa17 ldw r2,-24(fp) + 1013668: 1004c03a cmpne r2,r2,zero + 101366c: 1000071e bne r2,zero,101368c + 1013670: e0bff717 ldw r2,-36(fp) + 1013674: e0bff415 stw r2,-48(fp) + 1013678: e0bff417 ldw r2,-48(fp) + 101367c: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); /* No, can't change its priority! */ + return (OS_ERR_PRIO); + 1013680: 00800a44 movi r2,41 + 1013684: e0bfff15 stw r2,-4(fp) + 1013688: 00010f06 br 1013ac8 + } + if (ptcb == OS_TCB_RESERVED) { /* Is task assigned to Mutex */ + 101368c: e0bffa17 ldw r2,-24(fp) + 1013690: 10800058 cmpnei r2,r2,1 + 1013694: 1000071e bne r2,zero,10136b4 + 1013698: e0bff717 ldw r2,-36(fp) + 101369c: e0bff315 stw r2,-52(fp) + 10136a0: e0bff317 ldw r2,-52(fp) + 10136a4: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); /* No, can't change its priority! */ + return (OS_ERR_TASK_NOT_EXIST); + 10136a8: 008010c4 movi r2,67 + 10136ac: e0bfff15 stw r2,-4(fp) + 10136b0: 00010506 br 1013ac8 + } +#if OS_LOWEST_PRIO <= 63 + y_new = (INT8U)(newprio >> 3); /* Yes, compute new TCB fields */ + 10136b4: e0bffe03 ldbu r2,-8(fp) + 10136b8: 1004d0fa srli r2,r2,3 + 10136bc: e0bff985 stb r2,-26(fp) + x_new = (INT8U)(newprio & 0x07); + 10136c0: e0bffe03 ldbu r2,-8(fp) + 10136c4: 108001cc andi r2,r2,7 + 10136c8: e0bff945 stb r2,-27(fp) + bity_new = (INT8U)(1 << y_new); + 10136cc: e0fff983 ldbu r3,-26(fp) + 10136d0: 00800044 movi r2,1 + 10136d4: 10c4983a sll r2,r2,r3 + 10136d8: e0bff8c5 stb r2,-29(fp) + bitx_new = (INT8U)(1 << x_new); + 10136dc: e0fff943 ldbu r3,-27(fp) + 10136e0: 00800044 movi r2,1 + 10136e4: 10c4983a sll r2,r2,r3 + 10136e8: e0bff885 stb r2,-30(fp) + x_new = (INT8U)( newprio & 0x0F); + bity_new = (INT16U)(1 << y_new); + bitx_new = (INT16U)(1 << x_new); +#endif + + OSTCBPrioTbl[oldprio] = (OS_TCB *)0; /* Remove TCB from old priority */ + 10136ec: e0bffd03 ldbu r2,-12(fp) + 10136f0: 00c040b4 movhi r3,258 + 10136f4: 18d9a904 addi r3,r3,26276 + 10136f8: 1085883a add r2,r2,r2 + 10136fc: 1085883a add r2,r2,r2 + 1013700: 10c5883a add r2,r2,r3 + 1013704: 10000015 stw zero,0(r2) + OSTCBPrioTbl[newprio] = ptcb; /* Place pointer to TCB @ new priority */ + 1013708: e0bffe03 ldbu r2,-8(fp) + 101370c: 00c040b4 movhi r3,258 + 1013710: 18d9a904 addi r3,r3,26276 + 1013714: 1085883a add r2,r2,r2 + 1013718: 1085883a add r2,r2,r2 + 101371c: 10c7883a add r3,r2,r3 + 1013720: e0bffa17 ldw r2,-24(fp) + 1013724: 18800015 stw r2,0(r3) + y_old = ptcb->OSTCBY; + 1013728: e0bffa17 ldw r2,-24(fp) + 101372c: 10800d03 ldbu r2,52(r2) + 1013730: e0bff905 stb r2,-28(fp) + bity_old = ptcb->OSTCBBitY; + 1013734: e0bffa17 ldw r2,-24(fp) + 1013738: 10800d83 ldbu r2,54(r2) + 101373c: e0bff845 stb r2,-31(fp) + bitx_old = ptcb->OSTCBBitX; + 1013740: e0bffa17 ldw r2,-24(fp) + 1013744: 10800d43 ldbu r2,53(r2) + 1013748: e0bff805 stb r2,-32(fp) + if ((OSRdyTbl[y_old] & bitx_old) != 0) { /* If task is ready make it not */ + 101374c: e0fff903 ldbu r3,-28(fp) + 1013750: 008040b4 movhi r2,258 + 1013754: 10b31c44 addi r2,r2,-13199 + 1013758: 10c5883a add r2,r2,r3 + 101375c: 10c00003 ldbu r3,0(r2) + 1013760: e0bff803 ldbu r2,-32(fp) + 1013764: 1884703a and r2,r3,r2 + 1013768: 10803fcc andi r2,r2,255 + 101376c: 1005003a cmpeq r2,r2,zero + 1013770: 1000381e bne r2,zero,1013854 + OSRdyTbl[y_old] &= ~bitx_old; + 1013774: e13ff903 ldbu r4,-28(fp) + 1013778: e0fff903 ldbu r3,-28(fp) + 101377c: 008040b4 movhi r2,258 + 1013780: 10b31c44 addi r2,r2,-13199 + 1013784: 10c5883a add r2,r2,r3 + 1013788: 10800003 ldbu r2,0(r2) + 101378c: 1007883a mov r3,r2 + 1013790: e0bff803 ldbu r2,-32(fp) + 1013794: 0084303a nor r2,zero,r2 + 1013798: 1884703a and r2,r3,r2 + 101379c: 1007883a mov r3,r2 + 10137a0: 008040b4 movhi r2,258 + 10137a4: 10b31c44 addi r2,r2,-13199 + 10137a8: 1105883a add r2,r2,r4 + 10137ac: 10c00005 stb r3,0(r2) + if (OSRdyTbl[y_old] == 0) { + 10137b0: e0fff903 ldbu r3,-28(fp) + 10137b4: 008040b4 movhi r2,258 + 10137b8: 10b31c44 addi r2,r2,-13199 + 10137bc: 10c5883a add r2,r2,r3 + 10137c0: 10800003 ldbu r2,0(r2) + 10137c4: 10803fcc andi r2,r2,255 + 10137c8: 1004c03a cmpne r2,r2,zero + 10137cc: 10000b1e bne r2,zero,10137fc + OSRdyGrp &= ~bity_old; + 10137d0: e0bff843 ldbu r2,-31(fp) + 10137d4: 0084303a nor r2,zero,r2 + 10137d8: 1007883a mov r3,r2 + 10137dc: 008040b4 movhi r2,258 + 10137e0: 10b31c04 addi r2,r2,-13200 + 10137e4: 10800003 ldbu r2,0(r2) + 10137e8: 1884703a and r2,r3,r2 + 10137ec: 1007883a mov r3,r2 + 10137f0: 008040b4 movhi r2,258 + 10137f4: 10b31c04 addi r2,r2,-13200 + 10137f8: 10c00005 stb r3,0(r2) + } + OSRdyGrp |= bity_new; /* Make new priority ready to run */ + 10137fc: 008040b4 movhi r2,258 + 1013800: 10b31c04 addi r2,r2,-13200 + 1013804: 10c00003 ldbu r3,0(r2) + 1013808: e0bff8c3 ldbu r2,-29(fp) + 101380c: 1884b03a or r2,r3,r2 + 1013810: 1007883a mov r3,r2 + 1013814: 008040b4 movhi r2,258 + 1013818: 10b31c04 addi r2,r2,-13200 + 101381c: 10c00005 stb r3,0(r2) + OSRdyTbl[y_new] |= bitx_new; + 1013820: e13ff983 ldbu r4,-26(fp) + 1013824: e0fff983 ldbu r3,-26(fp) + 1013828: 008040b4 movhi r2,258 + 101382c: 10b31c44 addi r2,r2,-13199 + 1013830: 10c5883a add r2,r2,r3 + 1013834: 10c00003 ldbu r3,0(r2) + 1013838: e0bff883 ldbu r2,-30(fp) + 101383c: 1884b03a or r2,r3,r2 + 1013840: 1007883a mov r3,r2 + 1013844: 008040b4 movhi r2,258 + 1013848: 10b31c44 addi r2,r2,-13199 + 101384c: 1105883a add r2,r2,r4 + 1013850: 10c00005 stb r3,0(r2) + } + +#if (OS_EVENT_EN) + pevent = ptcb->OSTCBEventPtr; + 1013854: e0bffa17 ldw r2,-24(fp) + 1013858: 10800717 ldw r2,28(r2) + 101385c: e0bffc15 stw r2,-16(fp) + if (pevent != (OS_EVENT *)0) { + 1013860: e0bffc17 ldw r2,-16(fp) + 1013864: 1005003a cmpeq r2,r2,zero + 1013868: 1000341e bne r2,zero,101393c + pevent->OSEventTbl[y_old] &= ~bitx_old; /* Remove old task prio from wait list */ + 101386c: e13ff903 ldbu r4,-28(fp) + 1013870: e0fff903 ldbu r3,-28(fp) + 1013874: e0bffc17 ldw r2,-16(fp) + 1013878: 1885883a add r2,r3,r2 + 101387c: 10800204 addi r2,r2,8 + 1013880: 108000c3 ldbu r2,3(r2) + 1013884: 1007883a mov r3,r2 + 1013888: e0bff803 ldbu r2,-32(fp) + 101388c: 0084303a nor r2,zero,r2 + 1013890: 1884703a and r2,r3,r2 + 1013894: 1007883a mov r3,r2 + 1013898: e0bffc17 ldw r2,-16(fp) + 101389c: 2085883a add r2,r4,r2 + 10138a0: 10800204 addi r2,r2,8 + 10138a4: 10c000c5 stb r3,3(r2) + if (pevent->OSEventTbl[y_old] == 0) { + 10138a8: e0fff903 ldbu r3,-28(fp) + 10138ac: e0bffc17 ldw r2,-16(fp) + 10138b0: 1885883a add r2,r3,r2 + 10138b4: 10800204 addi r2,r2,8 + 10138b8: 108000c3 ldbu r2,3(r2) + 10138bc: 10803fcc andi r2,r2,255 + 10138c0: 1004c03a cmpne r2,r2,zero + 10138c4: 1000091e bne r2,zero,10138ec + pevent->OSEventGrp &= ~bity_old; + 10138c8: e0bffc17 ldw r2,-16(fp) + 10138cc: 10800283 ldbu r2,10(r2) + 10138d0: 1007883a mov r3,r2 + 10138d4: e0bff843 ldbu r2,-31(fp) + 10138d8: 0084303a nor r2,zero,r2 + 10138dc: 1884703a and r2,r3,r2 + 10138e0: 1007883a mov r3,r2 + 10138e4: e0bffc17 ldw r2,-16(fp) + 10138e8: 10c00285 stb r3,10(r2) + } + pevent->OSEventGrp |= bity_new; /* Add new task prio to wait list */ + 10138ec: e0bffc17 ldw r2,-16(fp) + 10138f0: 10c00283 ldbu r3,10(r2) + 10138f4: e0bff8c3 ldbu r2,-29(fp) + 10138f8: 1884b03a or r2,r3,r2 + 10138fc: 1007883a mov r3,r2 + 1013900: e0bffc17 ldw r2,-16(fp) + 1013904: 10c00285 stb r3,10(r2) + pevent->OSEventTbl[y_new] |= bitx_new; + 1013908: e13ff983 ldbu r4,-26(fp) + 101390c: e0fff983 ldbu r3,-26(fp) + 1013910: e0bffc17 ldw r2,-16(fp) + 1013914: 1885883a add r2,r3,r2 + 1013918: 10800204 addi r2,r2,8 + 101391c: 10c000c3 ldbu r3,3(r2) + 1013920: e0bff883 ldbu r2,-30(fp) + 1013924: 1884b03a or r2,r3,r2 + 1013928: 1007883a mov r3,r2 + 101392c: e0bffc17 ldw r2,-16(fp) + 1013930: 2085883a add r2,r4,r2 + 1013934: 10800204 addi r2,r2,8 + 1013938: 10c000c5 stb r3,3(r2) + } +#if (OS_EVENT_MULTI_EN > 0) + if (ptcb->OSTCBEventMultiPtr != (OS_EVENT **)0) { + 101393c: e0bffa17 ldw r2,-24(fp) + 1013940: 10800817 ldw r2,32(r2) + 1013944: 1005003a cmpeq r2,r2,zero + 1013948: 1000441e bne r2,zero,1013a5c + pevents = ptcb->OSTCBEventMultiPtr; + 101394c: e0bffa17 ldw r2,-24(fp) + 1013950: 10800817 ldw r2,32(r2) + 1013954: e0bffb15 stw r2,-20(fp) + pevent = *pevents; + 1013958: e0bffb17 ldw r2,-20(fp) + 101395c: 10800017 ldw r2,0(r2) + 1013960: e0bffc15 stw r2,-16(fp) + while (pevent != (OS_EVENT *)0) { + 1013964: 00003a06 br 1013a50 + pevent->OSEventTbl[y_old] &= ~bitx_old; /* Remove old task prio from wait lists */ + 1013968: e13ff903 ldbu r4,-28(fp) + 101396c: e0fff903 ldbu r3,-28(fp) + 1013970: e0bffc17 ldw r2,-16(fp) + 1013974: 1885883a add r2,r3,r2 + 1013978: 10800204 addi r2,r2,8 + 101397c: 108000c3 ldbu r2,3(r2) + 1013980: 1007883a mov r3,r2 + 1013984: e0bff803 ldbu r2,-32(fp) + 1013988: 0084303a nor r2,zero,r2 + 101398c: 1884703a and r2,r3,r2 + 1013990: 1007883a mov r3,r2 + 1013994: e0bffc17 ldw r2,-16(fp) + 1013998: 2085883a add r2,r4,r2 + 101399c: 10800204 addi r2,r2,8 + 10139a0: 10c000c5 stb r3,3(r2) + if (pevent->OSEventTbl[y_old] == 0) { + 10139a4: e0fff903 ldbu r3,-28(fp) + 10139a8: e0bffc17 ldw r2,-16(fp) + 10139ac: 1885883a add r2,r3,r2 + 10139b0: 10800204 addi r2,r2,8 + 10139b4: 108000c3 ldbu r2,3(r2) + 10139b8: 10803fcc andi r2,r2,255 + 10139bc: 1004c03a cmpne r2,r2,zero + 10139c0: 1000091e bne r2,zero,10139e8 + pevent->OSEventGrp &= ~bity_old; + 10139c4: e0bffc17 ldw r2,-16(fp) + 10139c8: 10800283 ldbu r2,10(r2) + 10139cc: 1007883a mov r3,r2 + 10139d0: e0bff843 ldbu r2,-31(fp) + 10139d4: 0084303a nor r2,zero,r2 + 10139d8: 1884703a and r2,r3,r2 + 10139dc: 1007883a mov r3,r2 + 10139e0: e0bffc17 ldw r2,-16(fp) + 10139e4: 10c00285 stb r3,10(r2) + } + pevent->OSEventGrp |= bity_new; /* Add new task prio to wait lists */ + 10139e8: e0bffc17 ldw r2,-16(fp) + 10139ec: 10c00283 ldbu r3,10(r2) + 10139f0: e0bff8c3 ldbu r2,-29(fp) + 10139f4: 1884b03a or r2,r3,r2 + 10139f8: 1007883a mov r3,r2 + 10139fc: e0bffc17 ldw r2,-16(fp) + 1013a00: 10c00285 stb r3,10(r2) + pevent->OSEventTbl[y_new] |= bitx_new; + 1013a04: e13ff983 ldbu r4,-26(fp) + 1013a08: e0fff983 ldbu r3,-26(fp) + 1013a0c: e0bffc17 ldw r2,-16(fp) + 1013a10: 1885883a add r2,r3,r2 + 1013a14: 10800204 addi r2,r2,8 + 1013a18: 10c000c3 ldbu r3,3(r2) + 1013a1c: e0bff883 ldbu r2,-30(fp) + 1013a20: 1884b03a or r2,r3,r2 + 1013a24: 1007883a mov r3,r2 + 1013a28: e0bffc17 ldw r2,-16(fp) + 1013a2c: 2085883a add r2,r4,r2 + 1013a30: 10800204 addi r2,r2,8 + 1013a34: 10c000c5 stb r3,3(r2) + pevents++; + 1013a38: e0bffb17 ldw r2,-20(fp) + 1013a3c: 10800104 addi r2,r2,4 + 1013a40: e0bffb15 stw r2,-20(fp) + pevent = *pevents; + 1013a44: e0bffb17 ldw r2,-20(fp) + 1013a48: 10800017 ldw r2,0(r2) + 1013a4c: e0bffc15 stw r2,-16(fp) + } +#if (OS_EVENT_MULTI_EN > 0) + if (ptcb->OSTCBEventMultiPtr != (OS_EVENT **)0) { + pevents = ptcb->OSTCBEventMultiPtr; + pevent = *pevents; + while (pevent != (OS_EVENT *)0) { + 1013a50: e0bffc17 ldw r2,-16(fp) + 1013a54: 1004c03a cmpne r2,r2,zero + 1013a58: 103fc31e bne r2,zero,1013968 + } + } +#endif +#endif + + ptcb->OSTCBPrio = newprio; /* Set new task priority */ + 1013a5c: e0fffa17 ldw r3,-24(fp) + 1013a60: e0bffe03 ldbu r2,-8(fp) + 1013a64: 18800c85 stb r2,50(r3) + ptcb->OSTCBY = y_new; + 1013a68: e0fffa17 ldw r3,-24(fp) + 1013a6c: e0bff983 ldbu r2,-26(fp) + 1013a70: 18800d05 stb r2,52(r3) + ptcb->OSTCBX = x_new; + 1013a74: e0fffa17 ldw r3,-24(fp) + 1013a78: e0bff943 ldbu r2,-27(fp) + 1013a7c: 18800cc5 stb r2,51(r3) + ptcb->OSTCBBitY = bity_new; + 1013a80: e0fffa17 ldw r3,-24(fp) + 1013a84: e0bff8c3 ldbu r2,-29(fp) + 1013a88: 18800d85 stb r2,54(r3) + ptcb->OSTCBBitX = bitx_new; + 1013a8c: e0fffa17 ldw r3,-24(fp) + 1013a90: e0bff883 ldbu r2,-30(fp) + 1013a94: 18800d45 stb r2,53(r3) + 1013a98: e0bff717 ldw r2,-36(fp) + 1013a9c: e0bff215 stw r2,-56(fp) + 1013aa0: e0bff217 ldw r2,-56(fp) + 1013aa4: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + if (OSRunning == OS_TRUE) { + 1013aa8: 008040b4 movhi r2,258 + 1013aac: 10b31044 addi r2,r2,-13247 + 1013ab0: 10800003 ldbu r2,0(r2) + 1013ab4: 10803fcc andi r2,r2,255 + 1013ab8: 10800058 cmpnei r2,r2,1 + 1013abc: 1000011e bne r2,zero,1013ac4 + OS_Sched(); /* Find new highest priority task */ + 1013ac0: 100ecb80 call 100ecb8 + } + return (OS_ERR_NONE); + 1013ac4: e03fff15 stw zero,-4(fp) + 1013ac8: e0bfff17 ldw r2,-4(fp) +} + 1013acc: e037883a mov sp,fp + 1013ad0: dfc00117 ldw ra,4(sp) + 1013ad4: df000017 ldw fp,0(sp) + 1013ad8: dec00204 addi sp,sp,8 + 1013adc: f800283a ret + +01013ae0 : +********************************************************************************************************* +*/ + +#if OS_TASK_CREATE_EN > 0 +INT8U OSTaskCreate (void (*task)(void *p_arg), void *p_arg, OS_STK *ptos, INT8U prio) +{ + 1013ae0: deffed04 addi sp,sp,-76 + 1013ae4: dfc01215 stw ra,72(sp) + 1013ae8: df001115 stw fp,68(sp) + 1013aec: df001104 addi fp,sp,68 + 1013af0: e13ffb15 stw r4,-20(fp) + 1013af4: e17ffc15 stw r5,-16(fp) + 1013af8: e1bffd15 stw r6,-12(fp) + 1013afc: e1fffe05 stb r7,-8(fp) + OS_STK *psp; + INT8U err; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 1013b00: e03ff815 stw zero,-32(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (prio > OS_LOWEST_PRIO) { /* Make sure priority is within allowable range */ + 1013b04: e0bffe03 ldbu r2,-8(fp) + 1013b08: 10800570 cmpltui r2,r2,21 + 1013b0c: 1000031e bne r2,zero,1013b1c + return (OS_ERR_PRIO_INVALID); + 1013b10: 00800a84 movi r2,42 + 1013b14: e0bfff15 stw r2,-4(fp) + 1013b18: 00006006 br 1013c9c +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1013b1c: 0005303a rdctl r2,status + 1013b20: e0bff715 stw r2,-36(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1013b24: e0fff717 ldw r3,-36(fp) + 1013b28: 00bfff84 movi r2,-2 + 1013b2c: 1884703a and r2,r3,r2 + 1013b30: 1001703a wrctl status,r2 + + return context; + 1013b34: e0bff717 ldw r2,-36(fp) + } +#endif + OS_ENTER_CRITICAL(); + 1013b38: e0bff815 stw r2,-32(fp) + if (OSIntNesting > 0) { /* Make sure we don't create the task from within an ISR */ + 1013b3c: 008040b4 movhi r2,258 + 1013b40: 10b31e04 addi r2,r2,-13192 + 1013b44: 10800003 ldbu r2,0(r2) + 1013b48: 10803fcc andi r2,r2,255 + 1013b4c: 1005003a cmpeq r2,r2,zero + 1013b50: 1000071e bne r2,zero,1013b70 + 1013b54: e0bff817 ldw r2,-32(fp) + 1013b58: e0bff615 stw r2,-40(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1013b5c: e0bff617 ldw r2,-40(fp) + 1013b60: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_CREATE_ISR); + 1013b64: 00800f04 movi r2,60 + 1013b68: e0bfff15 stw r2,-4(fp) + 1013b6c: 00004b06 br 1013c9c + } + if (OSTCBPrioTbl[prio] == (OS_TCB *)0) { /* Make sure task doesn't already exist at this priority */ + 1013b70: e0bffe03 ldbu r2,-8(fp) + 1013b74: 00c040b4 movhi r3,258 + 1013b78: 18d9a904 addi r3,r3,26276 + 1013b7c: 1085883a add r2,r2,r2 + 1013b80: 1085883a add r2,r2,r2 + 1013b84: 10c5883a add r2,r2,r3 + 1013b88: 10800017 ldw r2,0(r2) + 1013b8c: 1004c03a cmpne r2,r2,zero + 1013b90: 10003c1e bne r2,zero,1013c84 + OSTCBPrioTbl[prio] = OS_TCB_RESERVED;/* Reserve the priority to prevent others from doing ... */ + 1013b94: e0bffe03 ldbu r2,-8(fp) + 1013b98: 00c040b4 movhi r3,258 + 1013b9c: 18d9a904 addi r3,r3,26276 + 1013ba0: 1085883a add r2,r2,r2 + 1013ba4: 1085883a add r2,r2,r2 + 1013ba8: 10c7883a add r3,r2,r3 + 1013bac: 00800044 movi r2,1 + 1013bb0: 18800015 stw r2,0(r3) + 1013bb4: e0bff817 ldw r2,-32(fp) + 1013bb8: e0bff515 stw r2,-44(fp) + 1013bbc: e0bff517 ldw r2,-44(fp) + 1013bc0: 1001703a wrctl status,r2 + /* ... the same thing until task is created. */ + OS_EXIT_CRITICAL(); + psp = OSTaskStkInit(task, p_arg, ptos, 0); /* Initialize the task's stack */ + 1013bc4: e13ffb17 ldw r4,-20(fp) + 1013bc8: e17ffc17 ldw r5,-16(fp) + 1013bcc: e1bffd17 ldw r6,-12(fp) + 1013bd0: 000f883a mov r7,zero + 1013bd4: 10180fc0 call 10180fc + 1013bd8: e0bffa15 stw r2,-24(fp) + err = OS_TCBInit(prio, psp, (OS_STK *)0, 0, 0, (void *)0, 0); + 1013bdc: e13ffe03 ldbu r4,-8(fp) + 1013be0: d8000015 stw zero,0(sp) + 1013be4: d8000115 stw zero,4(sp) + 1013be8: d8000215 stw zero,8(sp) + 1013bec: e17ffa17 ldw r5,-24(fp) + 1013bf0: 000d883a mov r6,zero + 1013bf4: 000f883a mov r7,zero + 1013bf8: 100f0c00 call 100f0c0 + 1013bfc: e0bff905 stb r2,-28(fp) + if (err == OS_ERR_NONE) { + 1013c00: e0bff903 ldbu r2,-28(fp) + 1013c04: 1004c03a cmpne r2,r2,zero + 1013c08: 1000081e bne r2,zero,1013c2c + if (OSRunning == OS_TRUE) { /* Find highest priority task if multitasking has started */ + 1013c0c: 008040b4 movhi r2,258 + 1013c10: 10b31044 addi r2,r2,-13247 + 1013c14: 10800003 ldbu r2,0(r2) + 1013c18: 10803fcc andi r2,r2,255 + 1013c1c: 10800058 cmpnei r2,r2,1 + 1013c20: 1000151e bne r2,zero,1013c78 + OS_Sched(); + 1013c24: 100ecb80 call 100ecb8 + 1013c28: 00001306 br 1013c78 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1013c2c: 0005303a rdctl r2,status + 1013c30: e0bff415 stw r2,-48(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1013c34: e0fff417 ldw r3,-48(fp) + 1013c38: 00bfff84 movi r2,-2 + 1013c3c: 1884703a and r2,r3,r2 + 1013c40: 1001703a wrctl status,r2 + + return context; + 1013c44: e0bff417 ldw r2,-48(fp) + } + } else { + OS_ENTER_CRITICAL(); + 1013c48: e0bff815 stw r2,-32(fp) + OSTCBPrioTbl[prio] = (OS_TCB *)0;/* Make this priority available to others */ + 1013c4c: e0bffe03 ldbu r2,-8(fp) + 1013c50: 00c040b4 movhi r3,258 + 1013c54: 18d9a904 addi r3,r3,26276 + 1013c58: 1085883a add r2,r2,r2 + 1013c5c: 1085883a add r2,r2,r2 + 1013c60: 10c5883a add r2,r2,r3 + 1013c64: 10000015 stw zero,0(r2) + 1013c68: e0bff817 ldw r2,-32(fp) + 1013c6c: e0bff315 stw r2,-52(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1013c70: e0bff317 ldw r2,-52(fp) + 1013c74: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + } + return (err); + 1013c78: e0bff903 ldbu r2,-28(fp) + 1013c7c: e0bfff15 stw r2,-4(fp) + 1013c80: 00000606 br 1013c9c + 1013c84: e0bff817 ldw r2,-32(fp) + 1013c88: e0bff215 stw r2,-56(fp) + 1013c8c: e0bff217 ldw r2,-56(fp) + 1013c90: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); + return (OS_ERR_PRIO_EXIST); + 1013c94: 00800a04 movi r2,40 + 1013c98: e0bfff15 stw r2,-4(fp) + 1013c9c: e0bfff17 ldw r2,-4(fp) +} + 1013ca0: e037883a mov sp,fp + 1013ca4: dfc00117 ldw ra,4(sp) + 1013ca8: df000017 ldw fp,0(sp) + 1013cac: dec00204 addi sp,sp,8 + 1013cb0: f800283a ret + +01013cb4 : + INT16U id, + OS_STK *pbos, + INT32U stk_size, + void *pext, + INT16U opt) +{ + 1013cb4: deffeb04 addi sp,sp,-84 + 1013cb8: dfc01415 stw ra,80(sp) + 1013cbc: df001315 stw fp,76(sp) + 1013cc0: df001304 addi fp,sp,76 + 1013cc4: e13ff915 stw r4,-28(fp) + 1013cc8: e17ffa15 stw r5,-24(fp) + 1013ccc: e1bffb15 stw r6,-20(fp) + 1013cd0: e0800217 ldw r2,8(fp) + 1013cd4: e0c00617 ldw r3,24(fp) + 1013cd8: e1fffc05 stb r7,-16(fp) + 1013cdc: e0bffd0d sth r2,-12(fp) + 1013ce0: e0fffe0d sth r3,-8(fp) + OS_STK *psp; + INT8U err; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 1013ce4: e03ff615 stw zero,-40(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (prio > OS_LOWEST_PRIO) { /* Make sure priority is within allowable range */ + 1013ce8: e0bffc03 ldbu r2,-16(fp) + 1013cec: 10800570 cmpltui r2,r2,21 + 1013cf0: 1000031e bne r2,zero,1013d00 + return (OS_ERR_PRIO_INVALID); + 1013cf4: 00800a84 movi r2,42 + 1013cf8: e0bfff15 stw r2,-4(fp) + 1013cfc: 00006706 br 1013e9c +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1013d00: 0005303a rdctl r2,status + 1013d04: e0bff515 stw r2,-44(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1013d08: e0fff517 ldw r3,-44(fp) + 1013d0c: 00bfff84 movi r2,-2 + 1013d10: 1884703a and r2,r3,r2 + 1013d14: 1001703a wrctl status,r2 + + return context; + 1013d18: e0bff517 ldw r2,-44(fp) + } +#endif + OS_ENTER_CRITICAL(); + 1013d1c: e0bff615 stw r2,-40(fp) + if (OSIntNesting > 0) { /* Make sure we don't create the task from within an ISR */ + 1013d20: 008040b4 movhi r2,258 + 1013d24: 10b31e04 addi r2,r2,-13192 + 1013d28: 10800003 ldbu r2,0(r2) + 1013d2c: 10803fcc andi r2,r2,255 + 1013d30: 1005003a cmpeq r2,r2,zero + 1013d34: 1000071e bne r2,zero,1013d54 + 1013d38: e0bff617 ldw r2,-40(fp) + 1013d3c: e0bff415 stw r2,-48(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1013d40: e0bff417 ldw r2,-48(fp) + 1013d44: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_CREATE_ISR); + 1013d48: 00800f04 movi r2,60 + 1013d4c: e0bfff15 stw r2,-4(fp) + 1013d50: 00005206 br 1013e9c + } + if (OSTCBPrioTbl[prio] == (OS_TCB *)0) { /* Make sure task doesn't already exist at this priority */ + 1013d54: e0bffc03 ldbu r2,-16(fp) + 1013d58: 00c040b4 movhi r3,258 + 1013d5c: 18d9a904 addi r3,r3,26276 + 1013d60: 1085883a add r2,r2,r2 + 1013d64: 1085883a add r2,r2,r2 + 1013d68: 10c5883a add r2,r2,r3 + 1013d6c: 10800017 ldw r2,0(r2) + 1013d70: 1004c03a cmpne r2,r2,zero + 1013d74: 1000431e bne r2,zero,1013e84 + OSTCBPrioTbl[prio] = OS_TCB_RESERVED;/* Reserve the priority to prevent others from doing ... */ + 1013d78: e0bffc03 ldbu r2,-16(fp) + 1013d7c: 00c040b4 movhi r3,258 + 1013d80: 18d9a904 addi r3,r3,26276 + 1013d84: 1085883a add r2,r2,r2 + 1013d88: 1085883a add r2,r2,r2 + 1013d8c: 10c7883a add r3,r2,r3 + 1013d90: 00800044 movi r2,1 + 1013d94: 18800015 stw r2,0(r3) + 1013d98: e0bff617 ldw r2,-40(fp) + 1013d9c: e0bff315 stw r2,-52(fp) + 1013da0: e0bff317 ldw r2,-52(fp) + 1013da4: 1001703a wrctl status,r2 + /* ... the same thing until task is created. */ + OS_EXIT_CRITICAL(); + +#if (OS_TASK_STAT_STK_CHK_EN > 0) + OS_TaskStkClr(pbos, stk_size, opt); /* Clear the task stack (if needed) */ + 1013da8: e1bffe0b ldhu r6,-8(fp) + 1013dac: e1000317 ldw r4,12(fp) + 1013db0: e1400417 ldw r5,16(fp) + 1013db4: 1014f300 call 1014f30 +#endif + + psp = OSTaskStkInit(task, p_arg, ptos, opt); /* Initialize the task's stack */ + 1013db8: e1fffe0b ldhu r7,-8(fp) + 1013dbc: e13ff917 ldw r4,-28(fp) + 1013dc0: e17ffa17 ldw r5,-24(fp) + 1013dc4: e1bffb17 ldw r6,-20(fp) + 1013dc8: 10180fc0 call 10180fc + 1013dcc: e0bff815 stw r2,-32(fp) + err = OS_TCBInit(prio, psp, pbos, id, stk_size, pext, opt); + 1013dd0: e13ffc03 ldbu r4,-16(fp) + 1013dd4: e1fffd0b ldhu r7,-12(fp) + 1013dd8: e0fffe0b ldhu r3,-8(fp) + 1013ddc: e0800417 ldw r2,16(fp) + 1013de0: d8800015 stw r2,0(sp) + 1013de4: e0800517 ldw r2,20(fp) + 1013de8: d8800115 stw r2,4(sp) + 1013dec: d8c00215 stw r3,8(sp) + 1013df0: e17ff817 ldw r5,-32(fp) + 1013df4: e1800317 ldw r6,12(fp) + 1013df8: 100f0c00 call 100f0c0 + 1013dfc: e0bff705 stb r2,-36(fp) + if (err == OS_ERR_NONE) { + 1013e00: e0bff703 ldbu r2,-36(fp) + 1013e04: 1004c03a cmpne r2,r2,zero + 1013e08: 1000081e bne r2,zero,1013e2c + if (OSRunning == OS_TRUE) { /* Find HPT if multitasking has started */ + 1013e0c: 008040b4 movhi r2,258 + 1013e10: 10b31044 addi r2,r2,-13247 + 1013e14: 10800003 ldbu r2,0(r2) + 1013e18: 10803fcc andi r2,r2,255 + 1013e1c: 10800058 cmpnei r2,r2,1 + 1013e20: 1000151e bne r2,zero,1013e78 + OS_Sched(); + 1013e24: 100ecb80 call 100ecb8 + 1013e28: 00001306 br 1013e78 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1013e2c: 0005303a rdctl r2,status + 1013e30: e0bff215 stw r2,-56(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1013e34: e0fff217 ldw r3,-56(fp) + 1013e38: 00bfff84 movi r2,-2 + 1013e3c: 1884703a and r2,r3,r2 + 1013e40: 1001703a wrctl status,r2 + + return context; + 1013e44: e0bff217 ldw r2,-56(fp) + } + } else { + OS_ENTER_CRITICAL(); + 1013e48: e0bff615 stw r2,-40(fp) + OSTCBPrioTbl[prio] = (OS_TCB *)0; /* Make this priority avail. to others */ + 1013e4c: e0bffc03 ldbu r2,-16(fp) + 1013e50: 00c040b4 movhi r3,258 + 1013e54: 18d9a904 addi r3,r3,26276 + 1013e58: 1085883a add r2,r2,r2 + 1013e5c: 1085883a add r2,r2,r2 + 1013e60: 10c5883a add r2,r2,r3 + 1013e64: 10000015 stw zero,0(r2) + 1013e68: e0bff617 ldw r2,-40(fp) + 1013e6c: e0bff115 stw r2,-60(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1013e70: e0bff117 ldw r2,-60(fp) + 1013e74: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + } + return (err); + 1013e78: e0bff703 ldbu r2,-36(fp) + 1013e7c: e0bfff15 stw r2,-4(fp) + 1013e80: 00000606 br 1013e9c + 1013e84: e0bff617 ldw r2,-40(fp) + 1013e88: e0bff015 stw r2,-64(fp) + 1013e8c: e0bff017 ldw r2,-64(fp) + 1013e90: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); + return (OS_ERR_PRIO_EXIST); + 1013e94: 00800a04 movi r2,40 + 1013e98: e0bfff15 stw r2,-4(fp) + 1013e9c: e0bfff17 ldw r2,-4(fp) +} + 1013ea0: e037883a mov sp,fp + 1013ea4: dfc00117 ldw ra,4(sp) + 1013ea8: df000017 ldw fp,0(sp) + 1013eac: dec00204 addi sp,sp,8 + 1013eb0: f800283a ret + +01013eb4 : +********************************************************************************************************* +*/ + +#if OS_TASK_DEL_EN > 0 +INT8U OSTaskDel (INT8U prio) +{ + 1013eb4: defff304 addi sp,sp,-52 + 1013eb8: dfc00c15 stw ra,48(sp) + 1013ebc: df000b15 stw fp,44(sp) + 1013ec0: df000b04 addi fp,sp,44 + 1013ec4: e13ffe05 stb r4,-8(fp) +#if (OS_FLAG_EN > 0) && (OS_MAX_FLAGS > 0) + OS_FLAG_NODE *pnode; +#endif + OS_TCB *ptcb; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 1013ec8: e03ffb15 stw zero,-20(fp) +#endif + + + + if (OSIntNesting > 0) { /* See if trying to delete from ISR */ + 1013ecc: 008040b4 movhi r2,258 + 1013ed0: 10b31e04 addi r2,r2,-13192 + 1013ed4: 10800003 ldbu r2,0(r2) + 1013ed8: 10803fcc andi r2,r2,255 + 1013edc: 1005003a cmpeq r2,r2,zero + 1013ee0: 1000031e bne r2,zero,1013ef0 + return (OS_ERR_TASK_DEL_ISR); + 1013ee4: 00801004 movi r2,64 + 1013ee8: e0bfff15 stw r2,-4(fp) + 1013eec: 0000ee06 br 10142a8 + } + if (prio == OS_TASK_IDLE_PRIO) { /* Not allowed to delete idle task */ + 1013ef0: e0bffe03 ldbu r2,-8(fp) + 1013ef4: 10800518 cmpnei r2,r2,20 + 1013ef8: 1000031e bne r2,zero,1013f08 + return (OS_ERR_TASK_DEL_IDLE); + 1013efc: 00800f84 movi r2,62 + 1013f00: e0bfff15 stw r2,-4(fp) + 1013f04: 0000e806 br 10142a8 + } +#if OS_ARG_CHK_EN > 0 + if (prio >= OS_LOWEST_PRIO) { /* Task priority valid ? */ + 1013f08: e0bffe03 ldbu r2,-8(fp) + 1013f0c: 10800530 cmpltui r2,r2,20 + 1013f10: 1000061e bne r2,zero,1013f2c + if (prio != OS_PRIO_SELF) { + 1013f14: e0bffe03 ldbu r2,-8(fp) + 1013f18: 10803fe0 cmpeqi r2,r2,255 + 1013f1c: 1000031e bne r2,zero,1013f2c + return (OS_ERR_PRIO_INVALID); + 1013f20: 00800a84 movi r2,42 + 1013f24: e0bfff15 stw r2,-4(fp) + 1013f28: 0000df06 br 10142a8 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1013f2c: 0005303a rdctl r2,status + 1013f30: e0bffa15 stw r2,-24(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1013f34: e0fffa17 ldw r3,-24(fp) + 1013f38: 00bfff84 movi r2,-2 + 1013f3c: 1884703a and r2,r3,r2 + 1013f40: 1001703a wrctl status,r2 + + return context; + 1013f44: e0bffa17 ldw r2,-24(fp) + } + } +#endif + +/*$PAGE*/ + OS_ENTER_CRITICAL(); + 1013f48: e0bffb15 stw r2,-20(fp) + if (prio == OS_PRIO_SELF) { /* See if requesting to delete self */ + 1013f4c: e0bffe03 ldbu r2,-8(fp) + 1013f50: 10803fd8 cmpnei r2,r2,255 + 1013f54: 1000051e bne r2,zero,1013f6c + prio = OSTCBCur->OSTCBPrio; /* Set priority to delete to current */ + 1013f58: 008040b4 movhi r2,258 + 1013f5c: 10b31f04 addi r2,r2,-13188 + 1013f60: 10800017 ldw r2,0(r2) + 1013f64: 10800c83 ldbu r2,50(r2) + 1013f68: e0bffe05 stb r2,-8(fp) + } + ptcb = OSTCBPrioTbl[prio]; + 1013f6c: e0bffe03 ldbu r2,-8(fp) + 1013f70: 00c040b4 movhi r3,258 + 1013f74: 18d9a904 addi r3,r3,26276 + 1013f78: 1085883a add r2,r2,r2 + 1013f7c: 1085883a add r2,r2,r2 + 1013f80: 10c5883a add r2,r2,r3 + 1013f84: 10800017 ldw r2,0(r2) + 1013f88: e0bffc15 stw r2,-16(fp) + if (ptcb == (OS_TCB *)0) { /* Task to delete must exist */ + 1013f8c: e0bffc17 ldw r2,-16(fp) + 1013f90: 1004c03a cmpne r2,r2,zero + 1013f94: 1000071e bne r2,zero,1013fb4 + 1013f98: e0bffb17 ldw r2,-20(fp) + 1013f9c: e0bff915 stw r2,-28(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1013fa0: e0bff917 ldw r2,-28(fp) + 1013fa4: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_NOT_EXIST); + 1013fa8: 008010c4 movi r2,67 + 1013fac: e0bfff15 stw r2,-4(fp) + 1013fb0: 0000bd06 br 10142a8 + } + if (ptcb == OS_TCB_RESERVED) { /* Must not be assigned to Mutex */ + 1013fb4: e0bffc17 ldw r2,-16(fp) + 1013fb8: 10800058 cmpnei r2,r2,1 + 1013fbc: 1000071e bne r2,zero,1013fdc + 1013fc0: e0bffb17 ldw r2,-20(fp) + 1013fc4: e0bff815 stw r2,-32(fp) + 1013fc8: e0bff817 ldw r2,-32(fp) + 1013fcc: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_DEL); + 1013fd0: 00800f44 movi r2,61 + 1013fd4: e0bfff15 stw r2,-4(fp) + 1013fd8: 0000b306 br 10142a8 + } + + OSRdyTbl[ptcb->OSTCBY] &= ~ptcb->OSTCBBitX; + 1013fdc: e0bffc17 ldw r2,-16(fp) + 1013fe0: 10800d03 ldbu r2,52(r2) + 1013fe4: 11003fcc andi r4,r2,255 + 1013fe8: e0bffc17 ldw r2,-16(fp) + 1013fec: 10800d03 ldbu r2,52(r2) + 1013ff0: 10c03fcc andi r3,r2,255 + 1013ff4: 008040b4 movhi r2,258 + 1013ff8: 10b31c44 addi r2,r2,-13199 + 1013ffc: 10c5883a add r2,r2,r3 + 1014000: 10800003 ldbu r2,0(r2) + 1014004: 1007883a mov r3,r2 + 1014008: e0bffc17 ldw r2,-16(fp) + 101400c: 10800d43 ldbu r2,53(r2) + 1014010: 0084303a nor r2,zero,r2 + 1014014: 1884703a and r2,r3,r2 + 1014018: 1007883a mov r3,r2 + 101401c: 008040b4 movhi r2,258 + 1014020: 10b31c44 addi r2,r2,-13199 + 1014024: 1105883a add r2,r2,r4 + 1014028: 10c00005 stb r3,0(r2) + if (OSRdyTbl[ptcb->OSTCBY] == 0) { /* Make task not ready */ + 101402c: e0bffc17 ldw r2,-16(fp) + 1014030: 10800d03 ldbu r2,52(r2) + 1014034: 10c03fcc andi r3,r2,255 + 1014038: 008040b4 movhi r2,258 + 101403c: 10b31c44 addi r2,r2,-13199 + 1014040: 10c5883a add r2,r2,r3 + 1014044: 10800003 ldbu r2,0(r2) + 1014048: 10803fcc andi r2,r2,255 + 101404c: 1004c03a cmpne r2,r2,zero + 1014050: 10000c1e bne r2,zero,1014084 + OSRdyGrp &= ~ptcb->OSTCBBitY; + 1014054: e0bffc17 ldw r2,-16(fp) + 1014058: 10800d83 ldbu r2,54(r2) + 101405c: 0084303a nor r2,zero,r2 + 1014060: 1007883a mov r3,r2 + 1014064: 008040b4 movhi r2,258 + 1014068: 10b31c04 addi r2,r2,-13200 + 101406c: 10800003 ldbu r2,0(r2) + 1014070: 1884703a and r2,r3,r2 + 1014074: 1007883a mov r3,r2 + 1014078: 008040b4 movhi r2,258 + 101407c: 10b31c04 addi r2,r2,-13200 + 1014080: 10c00005 stb r3,0(r2) + } + +#if (OS_EVENT_EN) + if (ptcb->OSTCBEventPtr != (OS_EVENT *)0) { + 1014084: e0bffc17 ldw r2,-16(fp) + 1014088: 10800717 ldw r2,28(r2) + 101408c: 1005003a cmpeq r2,r2,zero + 1014090: 1000041e bne r2,zero,10140a4 + OS_EventTaskRemove(ptcb, ptcb->OSTCBEventPtr); /* Remove this task from any event wait list */ + 1014094: e0bffc17 ldw r2,-16(fp) + 1014098: 11400717 ldw r5,28(r2) + 101409c: e13ffc17 ldw r4,-16(fp) + 10140a0: 100e6700 call 100e670 + } +#if (OS_EVENT_MULTI_EN > 0) + if (ptcb->OSTCBEventMultiPtr != (OS_EVENT **)0) { /* Remove this task from any events' wait lists*/ + 10140a4: e0bffc17 ldw r2,-16(fp) + 10140a8: 10800817 ldw r2,32(r2) + 10140ac: 1005003a cmpeq r2,r2,zero + 10140b0: 1000041e bne r2,zero,10140c4 + OS_EventTaskRemoveMulti(ptcb, ptcb->OSTCBEventMultiPtr); + 10140b4: e0bffc17 ldw r2,-16(fp) + 10140b8: 11400817 ldw r5,32(r2) + 10140bc: e13ffc17 ldw r4,-16(fp) + 10140c0: 100e7280 call 100e728 + } +#endif +#endif + +#if (OS_FLAG_EN > 0) && (OS_MAX_FLAGS > 0) + pnode = ptcb->OSTCBFlagNode; + 10140c4: e0bffc17 ldw r2,-16(fp) + 10140c8: 10800a17 ldw r2,40(r2) + 10140cc: e0bffd15 stw r2,-12(fp) + if (pnode != (OS_FLAG_NODE *)0) { /* If task is waiting on event flag */ + 10140d0: e0bffd17 ldw r2,-12(fp) + 10140d4: 1005003a cmpeq r2,r2,zero + 10140d8: 1000021e bne r2,zero,10140e4 + OS_FlagUnlink(pnode); /* Remove from wait list */ + 10140dc: e13ffd17 ldw r4,-12(fp) + 10140e0: 1010dbc0 call 1010dbc + } +#endif + + ptcb->OSTCBDly = 0; /* Prevent OSTimeTick() from updating */ + 10140e4: e0bffc17 ldw r2,-16(fp) + 10140e8: 10000b8d sth zero,46(r2) + ptcb->OSTCBStat = OS_STAT_RDY; /* Prevent task from being resumed */ + 10140ec: e0bffc17 ldw r2,-16(fp) + 10140f0: 10000c05 stb zero,48(r2) + ptcb->OSTCBStatPend = OS_STAT_PEND_OK; + 10140f4: e0bffc17 ldw r2,-16(fp) + 10140f8: 10000c45 stb zero,49(r2) + if (OSLockNesting < 255u) { /* Make sure we don't context switch */ + 10140fc: 008040b4 movhi r2,258 + 1014100: 10b31004 addi r2,r2,-13248 + 1014104: 10800003 ldbu r2,0(r2) + 1014108: 10803fcc andi r2,r2,255 + 101410c: 10803fe0 cmpeqi r2,r2,255 + 1014110: 1000081e bne r2,zero,1014134 + OSLockNesting++; + 1014114: 008040b4 movhi r2,258 + 1014118: 10b31004 addi r2,r2,-13248 + 101411c: 10800003 ldbu r2,0(r2) + 1014120: 10800044 addi r2,r2,1 + 1014124: 1007883a mov r3,r2 + 1014128: 008040b4 movhi r2,258 + 101412c: 10b31004 addi r2,r2,-13248 + 1014130: 10c00005 stb r3,0(r2) + 1014134: e0bffb17 ldw r2,-20(fp) + 1014138: e0bff715 stw r2,-36(fp) + 101413c: e0bff717 ldw r2,-36(fp) + 1014140: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); /* Enabling INT. ignores next instruc. */ + OS_Dummy(); /* ... Dummy ensures that INTs will be */ + 1014144: 100e25c0 call 100e25c +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1014148: 0005303a rdctl r2,status + 101414c: e0bff615 stw r2,-40(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1014150: e0fff617 ldw r3,-40(fp) + 1014154: 00bfff84 movi r2,-2 + 1014158: 1884703a and r2,r3,r2 + 101415c: 1001703a wrctl status,r2 + + return context; + 1014160: e0bff617 ldw r2,-40(fp) + OS_ENTER_CRITICAL(); /* ... disabled HERE! */ + 1014164: e0bffb15 stw r2,-20(fp) + if (OSLockNesting > 0) { /* Remove context switch lock */ + 1014168: 008040b4 movhi r2,258 + 101416c: 10b31004 addi r2,r2,-13248 + 1014170: 10800003 ldbu r2,0(r2) + 1014174: 10803fcc andi r2,r2,255 + 1014178: 1005003a cmpeq r2,r2,zero + 101417c: 1000081e bne r2,zero,10141a0 + OSLockNesting--; + 1014180: 008040b4 movhi r2,258 + 1014184: 10b31004 addi r2,r2,-13248 + 1014188: 10800003 ldbu r2,0(r2) + 101418c: 10bfffc4 addi r2,r2,-1 + 1014190: 1007883a mov r3,r2 + 1014194: 008040b4 movhi r2,258 + 1014198: 10b31004 addi r2,r2,-13248 + 101419c: 10c00005 stb r3,0(r2) + } + OSTaskDelHook(ptcb); /* Call user defined hook */ + 10141a0: e13ffc17 ldw r4,-16(fp) + 10141a4: 101842c0 call 101842c + OSTaskCtr--; /* One less task being managed */ + 10141a8: 008040b4 movhi r2,258 + 10141ac: 10b31844 addi r2,r2,-13215 + 10141b0: 10800003 ldbu r2,0(r2) + 10141b4: 10bfffc4 addi r2,r2,-1 + 10141b8: 1007883a mov r3,r2 + 10141bc: 008040b4 movhi r2,258 + 10141c0: 10b31844 addi r2,r2,-13215 + 10141c4: 10c00005 stb r3,0(r2) + OSTCBPrioTbl[prio] = (OS_TCB *)0; /* Clear old priority entry */ + 10141c8: e0bffe03 ldbu r2,-8(fp) + 10141cc: 00c040b4 movhi r3,258 + 10141d0: 18d9a904 addi r3,r3,26276 + 10141d4: 1085883a add r2,r2,r2 + 10141d8: 1085883a add r2,r2,r2 + 10141dc: 10c5883a add r2,r2,r3 + 10141e0: 10000015 stw zero,0(r2) + if (ptcb->OSTCBPrev == (OS_TCB *)0) { /* Remove from TCB chain */ + 10141e4: e0bffc17 ldw r2,-16(fp) + 10141e8: 10800617 ldw r2,24(r2) + 10141ec: 1004c03a cmpne r2,r2,zero + 10141f0: 1000091e bne r2,zero,1014218 + ptcb->OSTCBNext->OSTCBPrev = (OS_TCB *)0; + 10141f4: e0bffc17 ldw r2,-16(fp) + 10141f8: 10800517 ldw r2,20(r2) + 10141fc: 10000615 stw zero,24(r2) + OSTCBList = ptcb->OSTCBNext; + 1014200: e0bffc17 ldw r2,-16(fp) + 1014204: 10c00517 ldw r3,20(r2) + 1014208: 008040b4 movhi r2,258 + 101420c: 10b31304 addi r2,r2,-13236 + 1014210: 10c00015 stw r3,0(r2) + 1014214: 00000a06 br 1014240 + } else { + ptcb->OSTCBPrev->OSTCBNext = ptcb->OSTCBNext; + 1014218: e0bffc17 ldw r2,-16(fp) + 101421c: 10c00617 ldw r3,24(r2) + 1014220: e0bffc17 ldw r2,-16(fp) + 1014224: 10800517 ldw r2,20(r2) + 1014228: 18800515 stw r2,20(r3) + ptcb->OSTCBNext->OSTCBPrev = ptcb->OSTCBPrev; + 101422c: e0bffc17 ldw r2,-16(fp) + 1014230: 10c00517 ldw r3,20(r2) + 1014234: e0bffc17 ldw r2,-16(fp) + 1014238: 10800617 ldw r2,24(r2) + 101423c: 18800615 stw r2,24(r3) + } + ptcb->OSTCBNext = OSTCBFreeList; /* Return TCB to free TCB list */ + 1014240: 008040b4 movhi r2,258 + 1014244: 10b31704 addi r2,r2,-13220 + 1014248: 10c00017 ldw r3,0(r2) + 101424c: e0bffc17 ldw r2,-16(fp) + 1014250: 10c00515 stw r3,20(r2) + OSTCBFreeList = ptcb; + 1014254: 00c040b4 movhi r3,258 + 1014258: 18f31704 addi r3,r3,-13220 + 101425c: e0bffc17 ldw r2,-16(fp) + 1014260: 18800015 stw r2,0(r3) +#if OS_TASK_NAME_SIZE > 1 + ptcb->OSTCBTaskName[0] = '?'; /* Unknown name */ + 1014264: e0fffc17 ldw r3,-16(fp) + 1014268: 00800fc4 movi r2,63 + 101426c: 18801305 stb r2,76(r3) + ptcb->OSTCBTaskName[1] = OS_ASCII_NUL; + 1014270: e0bffc17 ldw r2,-16(fp) + 1014274: 10001345 stb zero,77(r2) + 1014278: e0bffb17 ldw r2,-20(fp) + 101427c: e0bff515 stw r2,-44(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1014280: e0bff517 ldw r2,-44(fp) + 1014284: 1001703a wrctl status,r2 +#endif + OS_EXIT_CRITICAL(); + if (OSRunning == OS_TRUE) { + 1014288: 008040b4 movhi r2,258 + 101428c: 10b31044 addi r2,r2,-13247 + 1014290: 10800003 ldbu r2,0(r2) + 1014294: 10803fcc andi r2,r2,255 + 1014298: 10800058 cmpnei r2,r2,1 + 101429c: 1000011e bne r2,zero,10142a4 + OS_Sched(); /* Find new highest priority task */ + 10142a0: 100ecb80 call 100ecb8 + } + return (OS_ERR_NONE); + 10142a4: e03fff15 stw zero,-4(fp) + 10142a8: e0bfff17 ldw r2,-4(fp) +} + 10142ac: e037883a mov sp,fp + 10142b0: dfc00117 ldw ra,4(sp) + 10142b4: df000017 ldw fp,0(sp) + 10142b8: dec00204 addi sp,sp,8 + 10142bc: f800283a ret + +010142c0 : +********************************************************************************************************* +*/ +/*$PAGE*/ +#if OS_TASK_DEL_EN > 0 +INT8U OSTaskDelReq (INT8U prio) +{ + 10142c0: defff404 addi sp,sp,-48 + 10142c4: df000b15 stw fp,44(sp) + 10142c8: df000b04 addi fp,sp,44 + 10142cc: e13ffe05 stb r4,-8(fp) + INT8U stat; + OS_TCB *ptcb; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 10142d0: e03ffb15 stw zero,-20(fp) +#endif + + + + if (prio == OS_TASK_IDLE_PRIO) { /* Not allowed to delete idle task */ + 10142d4: e0bffe03 ldbu r2,-8(fp) + 10142d8: 10800518 cmpnei r2,r2,20 + 10142dc: 1000031e bne r2,zero,10142ec + return (OS_ERR_TASK_DEL_IDLE); + 10142e0: 00800f84 movi r2,62 + 10142e4: e0bfff15 stw r2,-4(fp) + 10142e8: 00004c06 br 101441c + } +#if OS_ARG_CHK_EN > 0 + if (prio >= OS_LOWEST_PRIO) { /* Task priority valid ? */ + 10142ec: e0bffe03 ldbu r2,-8(fp) + 10142f0: 10800530 cmpltui r2,r2,20 + 10142f4: 1000061e bne r2,zero,1014310 + if (prio != OS_PRIO_SELF) { + 10142f8: e0bffe03 ldbu r2,-8(fp) + 10142fc: 10803fe0 cmpeqi r2,r2,255 + 1014300: 1000031e bne r2,zero,1014310 + return (OS_ERR_PRIO_INVALID); + 1014304: 00800a84 movi r2,42 + 1014308: e0bfff15 stw r2,-4(fp) + 101430c: 00004306 br 101441c + } + } +#endif + if (prio == OS_PRIO_SELF) { /* See if a task is requesting to ... */ + 1014310: e0bffe03 ldbu r2,-8(fp) + 1014314: 10803fd8 cmpnei r2,r2,255 + 1014318: 1000141e bne r2,zero,101436c +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 101431c: 0005303a rdctl r2,status + 1014320: e0bffa15 stw r2,-24(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1014324: e0fffa17 ldw r3,-24(fp) + 1014328: 00bfff84 movi r2,-2 + 101432c: 1884703a and r2,r3,r2 + 1014330: 1001703a wrctl status,r2 + + return context; + 1014334: e0bffa17 ldw r2,-24(fp) + OS_ENTER_CRITICAL(); /* ... this task to delete itself */ + 1014338: e0bffb15 stw r2,-20(fp) + stat = OSTCBCur->OSTCBDelReq; /* Return request status to caller */ + 101433c: 008040b4 movhi r2,258 + 1014340: 10b31f04 addi r2,r2,-13188 + 1014344: 10800017 ldw r2,0(r2) + 1014348: 10800dc3 ldbu r2,55(r2) + 101434c: e0bffd05 stb r2,-12(fp) + 1014350: e0bffb17 ldw r2,-20(fp) + 1014354: e0bff915 stw r2,-28(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1014358: e0bff917 ldw r2,-28(fp) + 101435c: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (stat); + 1014360: e0bffd03 ldbu r2,-12(fp) + 1014364: e0bfff15 stw r2,-4(fp) + 1014368: 00002c06 br 101441c +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 101436c: 0005303a rdctl r2,status + 1014370: e0bff815 stw r2,-32(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1014374: e0fff817 ldw r3,-32(fp) + 1014378: 00bfff84 movi r2,-2 + 101437c: 1884703a and r2,r3,r2 + 1014380: 1001703a wrctl status,r2 + + return context; + 1014384: e0bff817 ldw r2,-32(fp) + } + OS_ENTER_CRITICAL(); + 1014388: e0bffb15 stw r2,-20(fp) + ptcb = OSTCBPrioTbl[prio]; + 101438c: e0bffe03 ldbu r2,-8(fp) + 1014390: 00c040b4 movhi r3,258 + 1014394: 18d9a904 addi r3,r3,26276 + 1014398: 1085883a add r2,r2,r2 + 101439c: 1085883a add r2,r2,r2 + 10143a0: 10c5883a add r2,r2,r3 + 10143a4: 10800017 ldw r2,0(r2) + 10143a8: e0bffc15 stw r2,-16(fp) + if (ptcb == (OS_TCB *)0) { /* Task to delete must exist */ + 10143ac: e0bffc17 ldw r2,-16(fp) + 10143b0: 1004c03a cmpne r2,r2,zero + 10143b4: 1000071e bne r2,zero,10143d4 + 10143b8: e0bffb17 ldw r2,-20(fp) + 10143bc: e0bff715 stw r2,-36(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 10143c0: e0bff717 ldw r2,-36(fp) + 10143c4: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_NOT_EXIST); /* Task must already be deleted */ + 10143c8: 008010c4 movi r2,67 + 10143cc: e0bfff15 stw r2,-4(fp) + 10143d0: 00001206 br 101441c + } + if (ptcb == OS_TCB_RESERVED) { /* Must NOT be assigned to a Mutex */ + 10143d4: e0bffc17 ldw r2,-16(fp) + 10143d8: 10800058 cmpnei r2,r2,1 + 10143dc: 1000071e bne r2,zero,10143fc + 10143e0: e0bffb17 ldw r2,-20(fp) + 10143e4: e0bff615 stw r2,-40(fp) + 10143e8: e0bff617 ldw r2,-40(fp) + 10143ec: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_DEL); + 10143f0: 00800f44 movi r2,61 + 10143f4: e0bfff15 stw r2,-4(fp) + 10143f8: 00000806 br 101441c + } + ptcb->OSTCBDelReq = OS_ERR_TASK_DEL_REQ; /* Set flag indicating task to be DEL. */ + 10143fc: e0fffc17 ldw r3,-16(fp) + 1014400: 00800fc4 movi r2,63 + 1014404: 18800dc5 stb r2,55(r3) + 1014408: e0bffb17 ldw r2,-20(fp) + 101440c: e0bff515 stw r2,-44(fp) + 1014410: e0bff517 ldw r2,-44(fp) + 1014414: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_NONE); + 1014418: e03fff15 stw zero,-4(fp) + 101441c: e0bfff17 ldw r2,-4(fp) +} + 1014420: e037883a mov sp,fp + 1014424: df000017 ldw fp,0(sp) + 1014428: dec00104 addi sp,sp,4 + 101442c: f800283a ret + +01014430 : +********************************************************************************************************* +*/ + +#if OS_TASK_NAME_SIZE > 1 +INT8U OSTaskNameGet (INT8U prio, INT8U *pname, INT8U *perr) +{ + 1014430: defff304 addi sp,sp,-52 + 1014434: dfc00c15 stw ra,48(sp) + 1014438: df000b15 stw fp,44(sp) + 101443c: df000b04 addi fp,sp,44 + 1014440: e17ffd15 stw r5,-12(fp) + 1014444: e1bffe15 stw r6,-8(fp) + 1014448: e13ffc05 stb r4,-16(fp) + OS_TCB *ptcb; + INT8U len; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 101444c: e03ff915 stw zero,-28(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + 1014450: e0bffe17 ldw r2,-8(fp) + 1014454: 1004c03a cmpne r2,r2,zero + 1014458: 1000021e bne r2,zero,1014464 + return (0); + 101445c: e03fff15 stw zero,-4(fp) + 1014460: 00005b06 br 10145d0 + } + if (prio > OS_LOWEST_PRIO) { /* Task priority valid ? */ + 1014464: e0bffc03 ldbu r2,-16(fp) + 1014468: 10800570 cmpltui r2,r2,21 + 101446c: 1000081e bne r2,zero,1014490 + if (prio != OS_PRIO_SELF) { + 1014470: e0bffc03 ldbu r2,-16(fp) + 1014474: 10803fe0 cmpeqi r2,r2,255 + 1014478: 1000051e bne r2,zero,1014490 + *perr = OS_ERR_PRIO_INVALID; /* No */ + 101447c: e0fffe17 ldw r3,-8(fp) + 1014480: 00800a84 movi r2,42 + 1014484: 18800005 stb r2,0(r3) + return (0); + 1014488: e03fff15 stw zero,-4(fp) + 101448c: 00005006 br 10145d0 + } + } + if (pname == (INT8U *)0) { /* Is 'pname' a NULL pointer? */ + 1014490: e0bffd17 ldw r2,-12(fp) + 1014494: 1004c03a cmpne r2,r2,zero + 1014498: 1000051e bne r2,zero,10144b0 + *perr = OS_ERR_PNAME_NULL; /* Yes */ + 101449c: e0fffe17 ldw r3,-8(fp) + 10144a0: 00800304 movi r2,12 + 10144a4: 18800005 stb r2,0(r3) + return (0); + 10144a8: e03fff15 stw zero,-4(fp) + 10144ac: 00004806 br 10145d0 + } +#endif + if (OSIntNesting > 0) { /* See if trying to call from an ISR */ + 10144b0: 008040b4 movhi r2,258 + 10144b4: 10b31e04 addi r2,r2,-13192 + 10144b8: 10800003 ldbu r2,0(r2) + 10144bc: 10803fcc andi r2,r2,255 + 10144c0: 1005003a cmpeq r2,r2,zero + 10144c4: 1000051e bne r2,zero,10144dc + *perr = OS_ERR_NAME_GET_ISR; + 10144c8: e0fffe17 ldw r3,-8(fp) + 10144cc: 00800444 movi r2,17 + 10144d0: 18800005 stb r2,0(r3) + return (0); + 10144d4: e03fff15 stw zero,-4(fp) + 10144d8: 00003d06 br 10145d0 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 10144dc: 0005303a rdctl r2,status + 10144e0: e0bff815 stw r2,-32(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 10144e4: e0fff817 ldw r3,-32(fp) + 10144e8: 00bfff84 movi r2,-2 + 10144ec: 1884703a and r2,r3,r2 + 10144f0: 1001703a wrctl status,r2 + + return context; + 10144f4: e0bff817 ldw r2,-32(fp) + } + OS_ENTER_CRITICAL(); + 10144f8: e0bff915 stw r2,-28(fp) + if (prio == OS_PRIO_SELF) { /* See if caller desires it's own name */ + 10144fc: e0bffc03 ldbu r2,-16(fp) + 1014500: 10803fd8 cmpnei r2,r2,255 + 1014504: 1000051e bne r2,zero,101451c + prio = OSTCBCur->OSTCBPrio; + 1014508: 008040b4 movhi r2,258 + 101450c: 10b31f04 addi r2,r2,-13188 + 1014510: 10800017 ldw r2,0(r2) + 1014514: 10800c83 ldbu r2,50(r2) + 1014518: e0bffc05 stb r2,-16(fp) + } + ptcb = OSTCBPrioTbl[prio]; + 101451c: e0bffc03 ldbu r2,-16(fp) + 1014520: 00c040b4 movhi r3,258 + 1014524: 18d9a904 addi r3,r3,26276 + 1014528: 1085883a add r2,r2,r2 + 101452c: 1085883a add r2,r2,r2 + 1014530: 10c5883a add r2,r2,r3 + 1014534: 10800017 ldw r2,0(r2) + 1014538: e0bffb15 stw r2,-20(fp) + if (ptcb == (OS_TCB *)0) { /* Does task exist? */ + 101453c: e0bffb17 ldw r2,-20(fp) + 1014540: 1004c03a cmpne r2,r2,zero + 1014544: 1000091e bne r2,zero,101456c + 1014548: e0bff917 ldw r2,-28(fp) + 101454c: e0bff715 stw r2,-36(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1014550: e0bff717 ldw r2,-36(fp) + 1014554: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); /* No */ + *perr = OS_ERR_TASK_NOT_EXIST; + 1014558: e0fffe17 ldw r3,-8(fp) + 101455c: 008010c4 movi r2,67 + 1014560: 18800005 stb r2,0(r3) + return (0); + 1014564: e03fff15 stw zero,-4(fp) + 1014568: 00001906 br 10145d0 + } + if (ptcb == OS_TCB_RESERVED) { /* Task assigned to a Mutex? */ + 101456c: e0bffb17 ldw r2,-20(fp) + 1014570: 10800058 cmpnei r2,r2,1 + 1014574: 1000091e bne r2,zero,101459c + 1014578: e0bff917 ldw r2,-28(fp) + 101457c: e0bff615 stw r2,-40(fp) + 1014580: e0bff617 ldw r2,-40(fp) + 1014584: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); /* Yes */ + *perr = OS_ERR_TASK_NOT_EXIST; + 1014588: e0fffe17 ldw r3,-8(fp) + 101458c: 008010c4 movi r2,67 + 1014590: 18800005 stb r2,0(r3) + return (0); + 1014594: e03fff15 stw zero,-4(fp) + 1014598: 00000d06 br 10145d0 + } + len = OS_StrCopy(pname, ptcb->OSTCBTaskName); /* Yes, copy name from TCB */ + 101459c: e0bffb17 ldw r2,-20(fp) + 10145a0: 11401304 addi r5,r2,76 + 10145a4: e13ffd17 ldw r4,-12(fp) + 10145a8: 100edfc0 call 100edfc + 10145ac: e0bffa05 stb r2,-24(fp) + 10145b0: e0bff917 ldw r2,-28(fp) + 10145b4: e0bff515 stw r2,-44(fp) + 10145b8: e0bff517 ldw r2,-44(fp) + 10145bc: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + 10145c0: e0bffe17 ldw r2,-8(fp) + 10145c4: 10000005 stb zero,0(r2) + return (len); + 10145c8: e0bffa03 ldbu r2,-24(fp) + 10145cc: e0bfff15 stw r2,-4(fp) + 10145d0: e0bfff17 ldw r2,-4(fp) +} + 10145d4: e037883a mov sp,fp + 10145d8: dfc00117 ldw ra,4(sp) + 10145dc: df000017 ldw fp,0(sp) + 10145e0: dec00204 addi sp,sp,8 + 10145e4: f800283a ret + +010145e8 : +* Returns : None +********************************************************************************************************* +*/ +#if OS_TASK_NAME_SIZE > 1 +void OSTaskNameSet (INT8U prio, INT8U *pname, INT8U *perr) +{ + 10145e8: defff304 addi sp,sp,-52 + 10145ec: dfc00c15 stw ra,48(sp) + 10145f0: df000b15 stw fp,44(sp) + 10145f4: df000b04 addi fp,sp,44 + 10145f8: e17ffe15 stw r5,-8(fp) + 10145fc: e1bfff15 stw r6,-4(fp) + 1014600: e13ffd05 stb r4,-12(fp) + INT8U len; + OS_TCB *ptcb; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 1014604: e03ffa15 stw zero,-24(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + 1014608: e0bfff17 ldw r2,-4(fp) + 101460c: 1005003a cmpeq r2,r2,zero + 1014610: 1000611e bne r2,zero,1014798 + return; + } + if (prio > OS_LOWEST_PRIO) { /* Task priority valid ? */ + 1014614: e0bffd03 ldbu r2,-12(fp) + 1014618: 10800570 cmpltui r2,r2,21 + 101461c: 1000071e bne r2,zero,101463c + if (prio != OS_PRIO_SELF) { + 1014620: e0bffd03 ldbu r2,-12(fp) + 1014624: 10803fe0 cmpeqi r2,r2,255 + 1014628: 1000041e bne r2,zero,101463c + *perr = OS_ERR_PRIO_INVALID; /* No */ + 101462c: e0ffff17 ldw r3,-4(fp) + 1014630: 00800a84 movi r2,42 + 1014634: 18800005 stb r2,0(r3) + return; + 1014638: 00005706 br 1014798 + } + } + if (pname == (INT8U *)0) { /* Is 'pname' a NULL pointer? */ + 101463c: e0bffe17 ldw r2,-8(fp) + 1014640: 1004c03a cmpne r2,r2,zero + 1014644: 1000041e bne r2,zero,1014658 + *perr = OS_ERR_PNAME_NULL; /* Yes */ + 1014648: e0ffff17 ldw r3,-4(fp) + 101464c: 00800304 movi r2,12 + 1014650: 18800005 stb r2,0(r3) + return; + 1014654: 00005006 br 1014798 + } +#endif + if (OSIntNesting > 0) { /* See if trying to call from an ISR */ + 1014658: 008040b4 movhi r2,258 + 101465c: 10b31e04 addi r2,r2,-13192 + 1014660: 10800003 ldbu r2,0(r2) + 1014664: 10803fcc andi r2,r2,255 + 1014668: 1005003a cmpeq r2,r2,zero + 101466c: 1000041e bne r2,zero,1014680 + *perr = OS_ERR_NAME_SET_ISR; + 1014670: e0ffff17 ldw r3,-4(fp) + 1014674: 00800484 movi r2,18 + 1014678: 18800005 stb r2,0(r3) + return; + 101467c: 00004606 br 1014798 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1014680: 0005303a rdctl r2,status + 1014684: e0bff915 stw r2,-28(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1014688: e0fff917 ldw r3,-28(fp) + 101468c: 00bfff84 movi r2,-2 + 1014690: 1884703a and r2,r3,r2 + 1014694: 1001703a wrctl status,r2 + + return context; + 1014698: e0bff917 ldw r2,-28(fp) + } + OS_ENTER_CRITICAL(); + 101469c: e0bffa15 stw r2,-24(fp) + if (prio == OS_PRIO_SELF) { /* See if caller desires to set it's own name */ + 10146a0: e0bffd03 ldbu r2,-12(fp) + 10146a4: 10803fd8 cmpnei r2,r2,255 + 10146a8: 1000051e bne r2,zero,10146c0 + prio = OSTCBCur->OSTCBPrio; + 10146ac: 008040b4 movhi r2,258 + 10146b0: 10b31f04 addi r2,r2,-13188 + 10146b4: 10800017 ldw r2,0(r2) + 10146b8: 10800c83 ldbu r2,50(r2) + 10146bc: e0bffd05 stb r2,-12(fp) + } + ptcb = OSTCBPrioTbl[prio]; + 10146c0: e0bffd03 ldbu r2,-12(fp) + 10146c4: 00c040b4 movhi r3,258 + 10146c8: 18d9a904 addi r3,r3,26276 + 10146cc: 1085883a add r2,r2,r2 + 10146d0: 1085883a add r2,r2,r2 + 10146d4: 10c5883a add r2,r2,r3 + 10146d8: 10800017 ldw r2,0(r2) + 10146dc: e0bffb15 stw r2,-20(fp) + if (ptcb == (OS_TCB *)0) { /* Does task exist? */ + 10146e0: e0bffb17 ldw r2,-20(fp) + 10146e4: 1004c03a cmpne r2,r2,zero + 10146e8: 1000081e bne r2,zero,101470c + 10146ec: e0bffa17 ldw r2,-24(fp) + 10146f0: e0bff815 stw r2,-32(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 10146f4: e0bff817 ldw r2,-32(fp) + 10146f8: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); /* No */ + *perr = OS_ERR_TASK_NOT_EXIST; + 10146fc: e0ffff17 ldw r3,-4(fp) + 1014700: 008010c4 movi r2,67 + 1014704: 18800005 stb r2,0(r3) + return; + 1014708: 00002306 br 1014798 + } + if (ptcb == OS_TCB_RESERVED) { /* Task assigned to a Mutex? */ + 101470c: e0bffb17 ldw r2,-20(fp) + 1014710: 10800058 cmpnei r2,r2,1 + 1014714: 1000081e bne r2,zero,1014738 + 1014718: e0bffa17 ldw r2,-24(fp) + 101471c: e0bff715 stw r2,-36(fp) + 1014720: e0bff717 ldw r2,-36(fp) + 1014724: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); /* Yes */ + *perr = OS_ERR_TASK_NOT_EXIST; + 1014728: e0ffff17 ldw r3,-4(fp) + 101472c: 008010c4 movi r2,67 + 1014730: 18800005 stb r2,0(r3) + return; + 1014734: 00001806 br 1014798 + } + len = OS_StrLen(pname); /* Yes, Can we fit the string in the TCB? */ + 1014738: e13ffe17 ldw r4,-8(fp) + 101473c: 100ee7c0 call 100ee7c + 1014740: e0bffc05 stb r2,-16(fp) + if (len > (OS_TASK_NAME_SIZE - 1)) { /* No */ + 1014744: e0bffc03 ldbu r2,-16(fp) + 1014748: 10800830 cmpltui r2,r2,32 + 101474c: 1000081e bne r2,zero,1014770 + 1014750: e0bffa17 ldw r2,-24(fp) + 1014754: e0bff615 stw r2,-40(fp) + 1014758: e0bff617 ldw r2,-40(fp) + 101475c: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + *perr = OS_ERR_TASK_NAME_TOO_LONG; + 1014760: e0ffff17 ldw r3,-4(fp) + 1014764: 00801044 movi r2,65 + 1014768: 18800005 stb r2,0(r3) + return; + 101476c: 00000a06 br 1014798 + } + (void)OS_StrCopy(ptcb->OSTCBTaskName, pname); /* Yes, copy to TCB */ + 1014770: e0bffb17 ldw r2,-20(fp) + 1014774: 11001304 addi r4,r2,76 + 1014778: e17ffe17 ldw r5,-8(fp) + 101477c: 100edfc0 call 100edfc + 1014780: e0bffa17 ldw r2,-24(fp) + 1014784: e0bff515 stw r2,-44(fp) + 1014788: e0bff517 ldw r2,-44(fp) + 101478c: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + 1014790: e0bfff17 ldw r2,-4(fp) + 1014794: 10000005 stb zero,0(r2) +} + 1014798: e037883a mov sp,fp + 101479c: dfc00117 ldw ra,4(sp) + 10147a0: df000017 ldw fp,0(sp) + 10147a4: dec00204 addi sp,sp,8 + 10147a8: f800283a ret + +010147ac : +********************************************************************************************************* +*/ + +#if OS_TASK_SUSPEND_EN > 0 +INT8U OSTaskResume (INT8U prio) +{ + 10147ac: defff304 addi sp,sp,-52 + 10147b0: dfc00c15 stw ra,48(sp) + 10147b4: df000b15 stw fp,44(sp) + 10147b8: df000b04 addi fp,sp,44 + 10147bc: e13ffe05 stb r4,-8(fp) + OS_TCB *ptcb; +#if OS_CRITICAL_METHOD == 3 /* Storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 10147c0: e03ffc15 stw zero,-16(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (prio >= OS_LOWEST_PRIO) { /* Make sure task priority is valid */ + 10147c4: e0bffe03 ldbu r2,-8(fp) + 10147c8: 10800530 cmpltui r2,r2,20 + 10147cc: 1000031e bne r2,zero,10147dc + return (OS_ERR_PRIO_INVALID); + 10147d0: 00800a84 movi r2,42 + 10147d4: e0bfff15 stw r2,-4(fp) + 10147d8: 00007406 br 10149ac +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 10147dc: 0005303a rdctl r2,status + 10147e0: e0bffb15 stw r2,-20(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 10147e4: e0fffb17 ldw r3,-20(fp) + 10147e8: 00bfff84 movi r2,-2 + 10147ec: 1884703a and r2,r3,r2 + 10147f0: 1001703a wrctl status,r2 + + return context; + 10147f4: e0bffb17 ldw r2,-20(fp) + } +#endif + OS_ENTER_CRITICAL(); + 10147f8: e0bffc15 stw r2,-16(fp) + ptcb = OSTCBPrioTbl[prio]; + 10147fc: e0bffe03 ldbu r2,-8(fp) + 1014800: 00c040b4 movhi r3,258 + 1014804: 18d9a904 addi r3,r3,26276 + 1014808: 1085883a add r2,r2,r2 + 101480c: 1085883a add r2,r2,r2 + 1014810: 10c5883a add r2,r2,r3 + 1014814: 10800017 ldw r2,0(r2) + 1014818: e0bffd15 stw r2,-12(fp) + if (ptcb == (OS_TCB *)0) { /* Task to suspend must exist */ + 101481c: e0bffd17 ldw r2,-12(fp) + 1014820: 1004c03a cmpne r2,r2,zero + 1014824: 1000071e bne r2,zero,1014844 + 1014828: e0bffc17 ldw r2,-16(fp) + 101482c: e0bffa15 stw r2,-24(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1014830: e0bffa17 ldw r2,-24(fp) + 1014834: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_RESUME_PRIO); + 1014838: 00801184 movi r2,70 + 101483c: e0bfff15 stw r2,-4(fp) + 1014840: 00005a06 br 10149ac + } + if (ptcb == OS_TCB_RESERVED) { /* See if assigned to Mutex */ + 1014844: e0bffd17 ldw r2,-12(fp) + 1014848: 10800058 cmpnei r2,r2,1 + 101484c: 1000071e bne r2,zero,101486c + 1014850: e0bffc17 ldw r2,-16(fp) + 1014854: e0bff915 stw r2,-28(fp) + 1014858: e0bff917 ldw r2,-28(fp) + 101485c: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_NOT_EXIST); + 1014860: 008010c4 movi r2,67 + 1014864: e0bfff15 stw r2,-4(fp) + 1014868: 00005006 br 10149ac + } + if ((ptcb->OSTCBStat & OS_STAT_SUSPEND) != OS_STAT_RDY) { /* Task must be suspended */ + 101486c: e0bffd17 ldw r2,-12(fp) + 1014870: 10800c03 ldbu r2,48(r2) + 1014874: 10803fcc andi r2,r2,255 + 1014878: 1080020c andi r2,r2,8 + 101487c: 1005003a cmpeq r2,r2,zero + 1014880: 1000441e bne r2,zero,1014994 + ptcb->OSTCBStat &= ~(INT8U)OS_STAT_SUSPEND; /* Remove suspension */ + 1014884: e0bffd17 ldw r2,-12(fp) + 1014888: 10c00c03 ldbu r3,48(r2) + 101488c: 00bffdc4 movi r2,-9 + 1014890: 1884703a and r2,r3,r2 + 1014894: 1007883a mov r3,r2 + 1014898: e0bffd17 ldw r2,-12(fp) + 101489c: 10c00c05 stb r3,48(r2) + if (ptcb->OSTCBStat == OS_STAT_RDY) { /* See if task is now ready */ + 10148a0: e0bffd17 ldw r2,-12(fp) + 10148a4: 10800c03 ldbu r2,48(r2) + 10148a8: 10803fcc andi r2,r2,255 + 10148ac: 1004c03a cmpne r2,r2,zero + 10148b0: 1000321e bne r2,zero,101497c + if (ptcb->OSTCBDly == 0) { + 10148b4: e0bffd17 ldw r2,-12(fp) + 10148b8: 10800b8b ldhu r2,46(r2) + 10148bc: 10bfffcc andi r2,r2,65535 + 10148c0: 1004c03a cmpne r2,r2,zero + 10148c4: 1000281e bne r2,zero,1014968 + OSRdyGrp |= ptcb->OSTCBBitY; /* Yes, Make task ready to run */ + 10148c8: e0bffd17 ldw r2,-12(fp) + 10148cc: 10c00d83 ldbu r3,54(r2) + 10148d0: 008040b4 movhi r2,258 + 10148d4: 10b31c04 addi r2,r2,-13200 + 10148d8: 10800003 ldbu r2,0(r2) + 10148dc: 1884b03a or r2,r3,r2 + 10148e0: 1007883a mov r3,r2 + 10148e4: 008040b4 movhi r2,258 + 10148e8: 10b31c04 addi r2,r2,-13200 + 10148ec: 10c00005 stb r3,0(r2) + OSRdyTbl[ptcb->OSTCBY] |= ptcb->OSTCBBitX; + 10148f0: e0bffd17 ldw r2,-12(fp) + 10148f4: 10800d03 ldbu r2,52(r2) + 10148f8: 11003fcc andi r4,r2,255 + 10148fc: e0bffd17 ldw r2,-12(fp) + 1014900: 10800d03 ldbu r2,52(r2) + 1014904: 10c03fcc andi r3,r2,255 + 1014908: 008040b4 movhi r2,258 + 101490c: 10b31c44 addi r2,r2,-13199 + 1014910: 10c5883a add r2,r2,r3 + 1014914: 10c00003 ldbu r3,0(r2) + 1014918: e0bffd17 ldw r2,-12(fp) + 101491c: 10800d43 ldbu r2,53(r2) + 1014920: 1884b03a or r2,r3,r2 + 1014924: 1007883a mov r3,r2 + 1014928: 008040b4 movhi r2,258 + 101492c: 10b31c44 addi r2,r2,-13199 + 1014930: 1105883a add r2,r2,r4 + 1014934: 10c00005 stb r3,0(r2) + 1014938: e0bffc17 ldw r2,-16(fp) + 101493c: e0bff815 stw r2,-32(fp) + 1014940: e0bff817 ldw r2,-32(fp) + 1014944: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + if (OSRunning == OS_TRUE) { + 1014948: 008040b4 movhi r2,258 + 101494c: 10b31044 addi r2,r2,-13247 + 1014950: 10800003 ldbu r2,0(r2) + 1014954: 10803fcc andi r2,r2,255 + 1014958: 10800058 cmpnei r2,r2,1 + 101495c: 10000b1e bne r2,zero,101498c + OS_Sched(); /* Find new highest priority task */ + 1014960: 100ecb80 call 100ecb8 + 1014964: 00000906 br 101498c + 1014968: e0bffc17 ldw r2,-16(fp) + 101496c: e0bff715 stw r2,-36(fp) + 1014970: e0bff717 ldw r2,-36(fp) + 1014974: 1001703a wrctl status,r2 + 1014978: 00000406 br 101498c + 101497c: e0bffc17 ldw r2,-16(fp) + 1014980: e0bff615 stw r2,-40(fp) + 1014984: e0bff617 ldw r2,-40(fp) + 1014988: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + } + } else { /* Must be pending on event */ + OS_EXIT_CRITICAL(); + } + return (OS_ERR_NONE); + 101498c: e03fff15 stw zero,-4(fp) + 1014990: 00000606 br 10149ac + 1014994: e0bffc17 ldw r2,-16(fp) + 1014998: e0bff515 stw r2,-44(fp) + 101499c: e0bff517 ldw r2,-44(fp) + 10149a0: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_NOT_SUSPENDED); + 10149a4: 00801104 movi r2,68 + 10149a8: e0bfff15 stw r2,-4(fp) + 10149ac: e0bfff17 ldw r2,-4(fp) +} + 10149b0: e037883a mov sp,fp + 10149b4: dfc00117 ldw ra,4(sp) + 10149b8: df000017 ldw fp,0(sp) + 10149bc: dec00204 addi sp,sp,8 + 10149c0: f800283a ret + +010149c4 : +* OS_ERR_PDATA_NULL if 'p_stk_data' is a NULL pointer +********************************************************************************************************* +*/ +#if (OS_TASK_STAT_STK_CHK_EN > 0) && (OS_TASK_CREATE_EXT_EN > 0) +INT8U OSTaskStkChk (INT8U prio, OS_STK_DATA *p_stk_data) +{ + 10149c4: defff204 addi sp,sp,-56 + 10149c8: df000d15 stw fp,52(sp) + 10149cc: df000d04 addi fp,sp,52 + 10149d0: e17ffe15 stw r5,-8(fp) + 10149d4: e13ffd05 stb r4,-12(fp) + OS_TCB *ptcb; + OS_STK *pchk; + INT32U nfree; + INT32U size; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 10149d8: e03ff815 stw zero,-32(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (prio > OS_LOWEST_PRIO) { /* Make sure task priority is valid */ + 10149dc: e0bffd03 ldbu r2,-12(fp) + 10149e0: 10800570 cmpltui r2,r2,21 + 10149e4: 1000061e bne r2,zero,1014a00 + if (prio != OS_PRIO_SELF) { + 10149e8: e0bffd03 ldbu r2,-12(fp) + 10149ec: 10803fe0 cmpeqi r2,r2,255 + 10149f0: 1000031e bne r2,zero,1014a00 + return (OS_ERR_PRIO_INVALID); + 10149f4: 00800a84 movi r2,42 + 10149f8: e0bfff15 stw r2,-4(fp) + 10149fc: 00006b06 br 1014bac + } + } + if (p_stk_data == (OS_STK_DATA *)0) { /* Validate 'p_stk_data' */ + 1014a00: e0bffe17 ldw r2,-8(fp) + 1014a04: 1004c03a cmpne r2,r2,zero + 1014a08: 1000031e bne r2,zero,1014a18 + return (OS_ERR_PDATA_NULL); + 1014a0c: 00800244 movi r2,9 + 1014a10: e0bfff15 stw r2,-4(fp) + 1014a14: 00006506 br 1014bac + } +#endif + p_stk_data->OSFree = 0; /* Assume failure, set to 0 size */ + 1014a18: e0bffe17 ldw r2,-8(fp) + 1014a1c: 10000015 stw zero,0(r2) + p_stk_data->OSUsed = 0; + 1014a20: e0bffe17 ldw r2,-8(fp) + 1014a24: 10000115 stw zero,4(r2) +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1014a28: 0005303a rdctl r2,status + 1014a2c: e0bff715 stw r2,-36(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1014a30: e0fff717 ldw r3,-36(fp) + 1014a34: 00bfff84 movi r2,-2 + 1014a38: 1884703a and r2,r3,r2 + 1014a3c: 1001703a wrctl status,r2 + + return context; + 1014a40: e0bff717 ldw r2,-36(fp) + OS_ENTER_CRITICAL(); + 1014a44: e0bff815 stw r2,-32(fp) + if (prio == OS_PRIO_SELF) { /* See if check for SELF */ + 1014a48: e0bffd03 ldbu r2,-12(fp) + 1014a4c: 10803fd8 cmpnei r2,r2,255 + 1014a50: 1000051e bne r2,zero,1014a68 + prio = OSTCBCur->OSTCBPrio; + 1014a54: 008040b4 movhi r2,258 + 1014a58: 10b31f04 addi r2,r2,-13188 + 1014a5c: 10800017 ldw r2,0(r2) + 1014a60: 10800c83 ldbu r2,50(r2) + 1014a64: e0bffd05 stb r2,-12(fp) + } + ptcb = OSTCBPrioTbl[prio]; + 1014a68: e0bffd03 ldbu r2,-12(fp) + 1014a6c: 00c040b4 movhi r3,258 + 1014a70: 18d9a904 addi r3,r3,26276 + 1014a74: 1085883a add r2,r2,r2 + 1014a78: 1085883a add r2,r2,r2 + 1014a7c: 10c5883a add r2,r2,r3 + 1014a80: 10800017 ldw r2,0(r2) + 1014a84: e0bffc15 stw r2,-16(fp) + if (ptcb == (OS_TCB *)0) { /* Make sure task exist */ + 1014a88: e0bffc17 ldw r2,-16(fp) + 1014a8c: 1004c03a cmpne r2,r2,zero + 1014a90: 1000071e bne r2,zero,1014ab0 + 1014a94: e0bff817 ldw r2,-32(fp) + 1014a98: e0bff615 stw r2,-40(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1014a9c: e0bff617 ldw r2,-40(fp) + 1014aa0: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_NOT_EXIST); + 1014aa4: 008010c4 movi r2,67 + 1014aa8: e0bfff15 stw r2,-4(fp) + 1014aac: 00003f06 br 1014bac + } + if (ptcb == OS_TCB_RESERVED) { + 1014ab0: e0bffc17 ldw r2,-16(fp) + 1014ab4: 10800058 cmpnei r2,r2,1 + 1014ab8: 1000071e bne r2,zero,1014ad8 + 1014abc: e0bff817 ldw r2,-32(fp) + 1014ac0: e0bff515 stw r2,-44(fp) + 1014ac4: e0bff517 ldw r2,-44(fp) + 1014ac8: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_NOT_EXIST); + 1014acc: 008010c4 movi r2,67 + 1014ad0: e0bfff15 stw r2,-4(fp) + 1014ad4: 00003506 br 1014bac + } + if ((ptcb->OSTCBOpt & OS_TASK_OPT_STK_CHK) == 0) { /* Make sure stack checking option is set */ + 1014ad8: e0bffc17 ldw r2,-16(fp) + 1014adc: 1080040b ldhu r2,16(r2) + 1014ae0: 10bfffcc andi r2,r2,65535 + 1014ae4: 1080004c andi r2,r2,1 + 1014ae8: 1004c03a cmpne r2,r2,zero + 1014aec: 1000071e bne r2,zero,1014b0c + 1014af0: e0bff817 ldw r2,-32(fp) + 1014af4: e0bff415 stw r2,-48(fp) + 1014af8: e0bff417 ldw r2,-48(fp) + 1014afc: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_OPT); + 1014b00: 00801144 movi r2,69 + 1014b04: e0bfff15 stw r2,-4(fp) + 1014b08: 00002806 br 1014bac + } + nfree = 0; + 1014b0c: e03ffa15 stw zero,-24(fp) + size = ptcb->OSTCBStkSize; + 1014b10: e0bffc17 ldw r2,-16(fp) + 1014b14: 10800317 ldw r2,12(r2) + 1014b18: e0bff915 stw r2,-28(fp) + pchk = ptcb->OSTCBStkBottom; + 1014b1c: e0bffc17 ldw r2,-16(fp) + 1014b20: 10800217 ldw r2,8(r2) + 1014b24: e0bffb15 stw r2,-20(fp) + 1014b28: e0bff817 ldw r2,-32(fp) + 1014b2c: e0bff315 stw r2,-52(fp) + 1014b30: e0bff317 ldw r2,-52(fp) + 1014b34: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); +#if OS_STK_GROWTH == 1 + while (*pchk++ == (OS_STK)0) { /* Compute the number of zero entries on the stk */ + 1014b38: 00000306 br 1014b48 + nfree++; + 1014b3c: e0bffa17 ldw r2,-24(fp) + 1014b40: 10800044 addi r2,r2,1 + 1014b44: e0bffa15 stw r2,-24(fp) + nfree = 0; + size = ptcb->OSTCBStkSize; + pchk = ptcb->OSTCBStkBottom; + OS_EXIT_CRITICAL(); +#if OS_STK_GROWTH == 1 + while (*pchk++ == (OS_STK)0) { /* Compute the number of zero entries on the stk */ + 1014b48: e0bffb17 ldw r2,-20(fp) + 1014b4c: 10800017 ldw r2,0(r2) + 1014b50: 1005003a cmpeq r2,r2,zero + 1014b54: 1007883a mov r3,r2 + 1014b58: e0bffb17 ldw r2,-20(fp) + 1014b5c: 10800104 addi r2,r2,4 + 1014b60: e0bffb15 stw r2,-20(fp) + 1014b64: 18803fcc andi r2,r3,255 + 1014b68: 1004c03a cmpne r2,r2,zero + 1014b6c: 103ff31e bne r2,zero,1014b3c +#else + while (*pchk-- == (OS_STK)0) { + nfree++; + } +#endif + p_stk_data->OSFree = nfree * sizeof(OS_STK); /* Compute number of free bytes on the stack */ + 1014b70: e0bffa17 ldw r2,-24(fp) + 1014b74: 1085883a add r2,r2,r2 + 1014b78: 1085883a add r2,r2,r2 + 1014b7c: 1007883a mov r3,r2 + 1014b80: e0bffe17 ldw r2,-8(fp) + 1014b84: 10c00015 stw r3,0(r2) + p_stk_data->OSUsed = (size - nfree) * sizeof(OS_STK); /* Compute number of bytes used on the stack */ + 1014b88: e0fff917 ldw r3,-28(fp) + 1014b8c: e0bffa17 ldw r2,-24(fp) + 1014b90: 1885c83a sub r2,r3,r2 + 1014b94: 1085883a add r2,r2,r2 + 1014b98: 1085883a add r2,r2,r2 + 1014b9c: 1007883a mov r3,r2 + 1014ba0: e0bffe17 ldw r2,-8(fp) + 1014ba4: 10c00115 stw r3,4(r2) + return (OS_ERR_NONE); + 1014ba8: e03fff15 stw zero,-4(fp) + 1014bac: e0bfff17 ldw r2,-4(fp) +} + 1014bb0: e037883a mov sp,fp + 1014bb4: df000017 ldw fp,0(sp) + 1014bb8: dec00104 addi sp,sp,4 + 1014bbc: f800283a ret + +01014bc0 : +********************************************************************************************************* +*/ + +#if OS_TASK_SUSPEND_EN > 0 +INT8U OSTaskSuspend (INT8U prio) +{ + 1014bc0: defff404 addi sp,sp,-48 + 1014bc4: dfc00b15 stw ra,44(sp) + 1014bc8: df000a15 stw fp,40(sp) + 1014bcc: df000a04 addi fp,sp,40 + 1014bd0: e13ffe05 stb r4,-8(fp) + BOOLEAN self; + OS_TCB *ptcb; + INT8U y; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 1014bd4: e03ffa15 stw zero,-24(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (prio == OS_TASK_IDLE_PRIO) { /* Not allowed to suspend idle task */ + 1014bd8: e0bffe03 ldbu r2,-8(fp) + 1014bdc: 10800518 cmpnei r2,r2,20 + 1014be0: 1000031e bne r2,zero,1014bf0 + return (OS_ERR_TASK_SUSPEND_IDLE); + 1014be4: 008011c4 movi r2,71 + 1014be8: e0bfff15 stw r2,-4(fp) + 1014bec: 00007906 br 1014dd4 + } + if (prio >= OS_LOWEST_PRIO) { /* Task priority valid ? */ + 1014bf0: e0bffe03 ldbu r2,-8(fp) + 1014bf4: 10800530 cmpltui r2,r2,20 + 1014bf8: 1000061e bne r2,zero,1014c14 + if (prio != OS_PRIO_SELF) { + 1014bfc: e0bffe03 ldbu r2,-8(fp) + 1014c00: 10803fe0 cmpeqi r2,r2,255 + 1014c04: 1000031e bne r2,zero,1014c14 + return (OS_ERR_PRIO_INVALID); + 1014c08: 00800a84 movi r2,42 + 1014c0c: e0bfff15 stw r2,-4(fp) + 1014c10: 00007006 br 1014dd4 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1014c14: 0005303a rdctl r2,status + 1014c18: e0bff915 stw r2,-28(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1014c1c: e0fff917 ldw r3,-28(fp) + 1014c20: 00bfff84 movi r2,-2 + 1014c24: 1884703a and r2,r3,r2 + 1014c28: 1001703a wrctl status,r2 + + return context; + 1014c2c: e0bff917 ldw r2,-28(fp) + } + } +#endif + OS_ENTER_CRITICAL(); + 1014c30: e0bffa15 stw r2,-24(fp) + if (prio == OS_PRIO_SELF) { /* See if suspend SELF */ + 1014c34: e0bffe03 ldbu r2,-8(fp) + 1014c38: 10803fd8 cmpnei r2,r2,255 + 1014c3c: 1000081e bne r2,zero,1014c60 + prio = OSTCBCur->OSTCBPrio; + 1014c40: 008040b4 movhi r2,258 + 1014c44: 10b31f04 addi r2,r2,-13188 + 1014c48: 10800017 ldw r2,0(r2) + 1014c4c: 10800c83 ldbu r2,50(r2) + 1014c50: e0bffe05 stb r2,-8(fp) + self = OS_TRUE; + 1014c54: 00800044 movi r2,1 + 1014c58: e0bffd05 stb r2,-12(fp) + 1014c5c: 00000b06 br 1014c8c + } else if (prio == OSTCBCur->OSTCBPrio) { /* See if suspending self */ + 1014c60: 008040b4 movhi r2,258 + 1014c64: 10b31f04 addi r2,r2,-13188 + 1014c68: 10800017 ldw r2,0(r2) + 1014c6c: 10800c83 ldbu r2,50(r2) + 1014c70: 10c03fcc andi r3,r2,255 + 1014c74: e0bffe03 ldbu r2,-8(fp) + 1014c78: 1880031e bne r3,r2,1014c88 + self = OS_TRUE; + 1014c7c: 00800044 movi r2,1 + 1014c80: e0bffd05 stb r2,-12(fp) + 1014c84: 00000106 br 1014c8c + } else { + self = OS_FALSE; /* No suspending another task */ + 1014c88: e03ffd05 stb zero,-12(fp) + } + ptcb = OSTCBPrioTbl[prio]; + 1014c8c: e0bffe03 ldbu r2,-8(fp) + 1014c90: 00c040b4 movhi r3,258 + 1014c94: 18d9a904 addi r3,r3,26276 + 1014c98: 1085883a add r2,r2,r2 + 1014c9c: 1085883a add r2,r2,r2 + 1014ca0: 10c5883a add r2,r2,r3 + 1014ca4: 10800017 ldw r2,0(r2) + 1014ca8: e0bffc15 stw r2,-16(fp) + if (ptcb == (OS_TCB *)0) { /* Task to suspend must exist */ + 1014cac: e0bffc17 ldw r2,-16(fp) + 1014cb0: 1004c03a cmpne r2,r2,zero + 1014cb4: 1000071e bne r2,zero,1014cd4 + 1014cb8: e0bffa17 ldw r2,-24(fp) + 1014cbc: e0bff815 stw r2,-32(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1014cc0: e0bff817 ldw r2,-32(fp) + 1014cc4: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_SUSPEND_PRIO); + 1014cc8: 00801204 movi r2,72 + 1014ccc: e0bfff15 stw r2,-4(fp) + 1014cd0: 00004006 br 1014dd4 + } + if (ptcb == OS_TCB_RESERVED) { /* See if assigned to Mutex */ + 1014cd4: e0bffc17 ldw r2,-16(fp) + 1014cd8: 10800058 cmpnei r2,r2,1 + 1014cdc: 1000071e bne r2,zero,1014cfc + 1014ce0: e0bffa17 ldw r2,-24(fp) + 1014ce4: e0bff715 stw r2,-36(fp) + 1014ce8: e0bff717 ldw r2,-36(fp) + 1014cec: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_NOT_EXIST); + 1014cf0: 008010c4 movi r2,67 + 1014cf4: e0bfff15 stw r2,-4(fp) + 1014cf8: 00003606 br 1014dd4 + } + y = ptcb->OSTCBY; + 1014cfc: e0bffc17 ldw r2,-16(fp) + 1014d00: 10800d03 ldbu r2,52(r2) + 1014d04: e0bffb05 stb r2,-20(fp) + OSRdyTbl[y] &= ~ptcb->OSTCBBitX; /* Make task not ready */ + 1014d08: e13ffb03 ldbu r4,-20(fp) + 1014d0c: e0fffb03 ldbu r3,-20(fp) + 1014d10: 008040b4 movhi r2,258 + 1014d14: 10b31c44 addi r2,r2,-13199 + 1014d18: 10c5883a add r2,r2,r3 + 1014d1c: 10800003 ldbu r2,0(r2) + 1014d20: 1007883a mov r3,r2 + 1014d24: e0bffc17 ldw r2,-16(fp) + 1014d28: 10800d43 ldbu r2,53(r2) + 1014d2c: 0084303a nor r2,zero,r2 + 1014d30: 1884703a and r2,r3,r2 + 1014d34: 1007883a mov r3,r2 + 1014d38: 008040b4 movhi r2,258 + 1014d3c: 10b31c44 addi r2,r2,-13199 + 1014d40: 1105883a add r2,r2,r4 + 1014d44: 10c00005 stb r3,0(r2) + if (OSRdyTbl[y] == 0) { + 1014d48: e0fffb03 ldbu r3,-20(fp) + 1014d4c: 008040b4 movhi r2,258 + 1014d50: 10b31c44 addi r2,r2,-13199 + 1014d54: 10c5883a add r2,r2,r3 + 1014d58: 10800003 ldbu r2,0(r2) + 1014d5c: 10803fcc andi r2,r2,255 + 1014d60: 1004c03a cmpne r2,r2,zero + 1014d64: 10000c1e bne r2,zero,1014d98 + OSRdyGrp &= ~ptcb->OSTCBBitY; + 1014d68: e0bffc17 ldw r2,-16(fp) + 1014d6c: 10800d83 ldbu r2,54(r2) + 1014d70: 0084303a nor r2,zero,r2 + 1014d74: 1007883a mov r3,r2 + 1014d78: 008040b4 movhi r2,258 + 1014d7c: 10b31c04 addi r2,r2,-13200 + 1014d80: 10800003 ldbu r2,0(r2) + 1014d84: 1884703a and r2,r3,r2 + 1014d88: 1007883a mov r3,r2 + 1014d8c: 008040b4 movhi r2,258 + 1014d90: 10b31c04 addi r2,r2,-13200 + 1014d94: 10c00005 stb r3,0(r2) + } + ptcb->OSTCBStat |= OS_STAT_SUSPEND; /* Status of task is 'SUSPENDED' */ + 1014d98: e0bffc17 ldw r2,-16(fp) + 1014d9c: 10800c03 ldbu r2,48(r2) + 1014da0: 10800214 ori r2,r2,8 + 1014da4: 1007883a mov r3,r2 + 1014da8: e0bffc17 ldw r2,-16(fp) + 1014dac: 10c00c05 stb r3,48(r2) + 1014db0: e0bffa17 ldw r2,-24(fp) + 1014db4: e0bff615 stw r2,-40(fp) + 1014db8: e0bff617 ldw r2,-40(fp) + 1014dbc: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + if (self == OS_TRUE) { /* Context switch only if SELF */ + 1014dc0: e0bffd03 ldbu r2,-12(fp) + 1014dc4: 10800058 cmpnei r2,r2,1 + 1014dc8: 1000011e bne r2,zero,1014dd0 + OS_Sched(); /* Find new highest priority task */ + 1014dcc: 100ecb80 call 100ecb8 + } + return (OS_ERR_NONE); + 1014dd0: e03fff15 stw zero,-4(fp) + 1014dd4: e0bfff17 ldw r2,-4(fp) +} + 1014dd8: e037883a mov sp,fp + 1014ddc: dfc00117 ldw ra,4(sp) + 1014de0: df000017 ldw fp,0(sp) + 1014de4: dec00204 addi sp,sp,8 + 1014de8: f800283a ret + +01014dec : +********************************************************************************************************* +*/ + +#if OS_TASK_QUERY_EN > 0 +INT8U OSTaskQuery (INT8U prio, OS_TCB *p_task_data) +{ + 1014dec: defff504 addi sp,sp,-44 + 1014df0: dfc00a15 stw ra,40(sp) + 1014df4: df000915 stw fp,36(sp) + 1014df8: df000904 addi fp,sp,36 + 1014dfc: e17ffe15 stw r5,-8(fp) + 1014e00: e13ffd05 stb r4,-12(fp) + OS_TCB *ptcb; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 1014e04: e03ffb15 stw zero,-20(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (prio > OS_LOWEST_PRIO) { /* Task priority valid ? */ + 1014e08: e0bffd03 ldbu r2,-12(fp) + 1014e0c: 10800570 cmpltui r2,r2,21 + 1014e10: 1000061e bne r2,zero,1014e2c + if (prio != OS_PRIO_SELF) { + 1014e14: e0bffd03 ldbu r2,-12(fp) + 1014e18: 10803fe0 cmpeqi r2,r2,255 + 1014e1c: 1000031e bne r2,zero,1014e2c + return (OS_ERR_PRIO_INVALID); + 1014e20: 00800a84 movi r2,42 + 1014e24: e0bfff15 stw r2,-4(fp) + 1014e28: 00003b06 br 1014f18 + } + } + if (p_task_data == (OS_TCB *)0) { /* Validate 'p_task_data' */ + 1014e2c: e0bffe17 ldw r2,-8(fp) + 1014e30: 1004c03a cmpne r2,r2,zero + 1014e34: 1000031e bne r2,zero,1014e44 + return (OS_ERR_PDATA_NULL); + 1014e38: 00800244 movi r2,9 + 1014e3c: e0bfff15 stw r2,-4(fp) + 1014e40: 00003506 br 1014f18 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1014e44: 0005303a rdctl r2,status + 1014e48: e0bffa15 stw r2,-24(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1014e4c: e0fffa17 ldw r3,-24(fp) + 1014e50: 00bfff84 movi r2,-2 + 1014e54: 1884703a and r2,r3,r2 + 1014e58: 1001703a wrctl status,r2 + + return context; + 1014e5c: e0bffa17 ldw r2,-24(fp) + } +#endif + OS_ENTER_CRITICAL(); + 1014e60: e0bffb15 stw r2,-20(fp) + if (prio == OS_PRIO_SELF) { /* See if suspend SELF */ + 1014e64: e0bffd03 ldbu r2,-12(fp) + 1014e68: 10803fd8 cmpnei r2,r2,255 + 1014e6c: 1000051e bne r2,zero,1014e84 + prio = OSTCBCur->OSTCBPrio; + 1014e70: 008040b4 movhi r2,258 + 1014e74: 10b31f04 addi r2,r2,-13188 + 1014e78: 10800017 ldw r2,0(r2) + 1014e7c: 10800c83 ldbu r2,50(r2) + 1014e80: e0bffd05 stb r2,-12(fp) + } + ptcb = OSTCBPrioTbl[prio]; + 1014e84: e0bffd03 ldbu r2,-12(fp) + 1014e88: 00c040b4 movhi r3,258 + 1014e8c: 18d9a904 addi r3,r3,26276 + 1014e90: 1085883a add r2,r2,r2 + 1014e94: 1085883a add r2,r2,r2 + 1014e98: 10c5883a add r2,r2,r3 + 1014e9c: 10800017 ldw r2,0(r2) + 1014ea0: e0bffc15 stw r2,-16(fp) + if (ptcb == (OS_TCB *)0) { /* Task to query must exist */ + 1014ea4: e0bffc17 ldw r2,-16(fp) + 1014ea8: 1004c03a cmpne r2,r2,zero + 1014eac: 1000071e bne r2,zero,1014ecc + 1014eb0: e0bffb17 ldw r2,-20(fp) + 1014eb4: e0bff915 stw r2,-28(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1014eb8: e0bff917 ldw r2,-28(fp) + 1014ebc: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_PRIO); + 1014ec0: 00800a44 movi r2,41 + 1014ec4: e0bfff15 stw r2,-4(fp) + 1014ec8: 00001306 br 1014f18 + } + if (ptcb == OS_TCB_RESERVED) { /* Task to query must not be assigned to a Mutex */ + 1014ecc: e0bffc17 ldw r2,-16(fp) + 1014ed0: 10800058 cmpnei r2,r2,1 + 1014ed4: 1000071e bne r2,zero,1014ef4 + 1014ed8: e0bffb17 ldw r2,-20(fp) + 1014edc: e0bff815 stw r2,-32(fp) + 1014ee0: e0bff817 ldw r2,-32(fp) + 1014ee4: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_NOT_EXIST); + 1014ee8: 008010c4 movi r2,67 + 1014eec: e0bfff15 stw r2,-4(fp) + 1014ef0: 00000906 br 1014f18 + } + /* Copy TCB into user storage area */ + OS_MemCopy((INT8U *)p_task_data, (INT8U *)ptcb, sizeof(OS_TCB)); + 1014ef4: e13ffe17 ldw r4,-8(fp) + 1014ef8: e17ffc17 ldw r5,-16(fp) + 1014efc: 01801b04 movi r6,108 + 1014f00: 100ec4c0 call 100ec4c + 1014f04: e0bffb17 ldw r2,-20(fp) + 1014f08: e0bff715 stw r2,-36(fp) + 1014f0c: e0bff717 ldw r2,-36(fp) + 1014f10: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_NONE); + 1014f14: e03fff15 stw zero,-4(fp) + 1014f18: e0bfff17 ldw r2,-4(fp) +} + 1014f1c: e037883a mov sp,fp + 1014f20: dfc00117 ldw ra,4(sp) + 1014f24: df000017 ldw fp,0(sp) + 1014f28: dec00204 addi sp,sp,8 + 1014f2c: f800283a ret + +01014f30 : +* Returns : none +********************************************************************************************************* +*/ +#if (OS_TASK_STAT_STK_CHK_EN > 0) && (OS_TASK_CREATE_EXT_EN > 0) +void OS_TaskStkClr (OS_STK *pbos, INT32U size, INT16U opt) +{ + 1014f30: defffc04 addi sp,sp,-16 + 1014f34: df000315 stw fp,12(sp) + 1014f38: df000304 addi fp,sp,12 + 1014f3c: e13ffd15 stw r4,-12(fp) + 1014f40: e17ffe15 stw r5,-8(fp) + 1014f44: e1bfff0d sth r6,-4(fp) + if ((opt & OS_TASK_OPT_STK_CHK) != 0x0000) { /* See if stack checking has been enabled */ + 1014f48: e0bfff0b ldhu r2,-4(fp) + 1014f4c: 1080004c andi r2,r2,1 + 1014f50: 10803fcc andi r2,r2,255 + 1014f54: 1005003a cmpeq r2,r2,zero + 1014f58: 1000101e bne r2,zero,1014f9c + if ((opt & OS_TASK_OPT_STK_CLR) != 0x0000) { /* See if stack needs to be cleared */ + 1014f5c: e0bfff0b ldhu r2,-4(fp) + 1014f60: 1080008c andi r2,r2,2 + 1014f64: 1005003a cmpeq r2,r2,zero + 1014f68: 10000c1e bne r2,zero,1014f9c +#if OS_STK_GROWTH == 1 + while (size > 0) { /* Stack grows from HIGH to LOW memory */ + 1014f6c: 00000806 br 1014f90 + size--; + 1014f70: e0bffe17 ldw r2,-8(fp) + 1014f74: 10bfffc4 addi r2,r2,-1 + 1014f78: e0bffe15 stw r2,-8(fp) + *pbos++ = (OS_STK)0; /* Clear from bottom of stack and up! */ + 1014f7c: e0bffd17 ldw r2,-12(fp) + 1014f80: 10000015 stw zero,0(r2) + 1014f84: e0bffd17 ldw r2,-12(fp) + 1014f88: 10800104 addi r2,r2,4 + 1014f8c: e0bffd15 stw r2,-12(fp) +void OS_TaskStkClr (OS_STK *pbos, INT32U size, INT16U opt) +{ + if ((opt & OS_TASK_OPT_STK_CHK) != 0x0000) { /* See if stack checking has been enabled */ + if ((opt & OS_TASK_OPT_STK_CLR) != 0x0000) { /* See if stack needs to be cleared */ +#if OS_STK_GROWTH == 1 + while (size > 0) { /* Stack grows from HIGH to LOW memory */ + 1014f90: e0bffe17 ldw r2,-8(fp) + 1014f94: 1004c03a cmpne r2,r2,zero + 1014f98: 103ff51e bne r2,zero,1014f70 + *pbos-- = (OS_STK)0; /* Clear from bottom of stack and down */ + } +#endif + } + } +} + 1014f9c: e037883a mov sp,fp + 1014fa0: df000017 ldw fp,0(sp) + 1014fa4: dec00104 addi sp,sp,4 + 1014fa8: f800283a ret + +01014fac : +* Returns : none +********************************************************************************************************* +*/ + +void OSTimeDly (INT16U ticks) +{ + 1014fac: defff904 addi sp,sp,-28 + 1014fb0: dfc00615 stw ra,24(sp) + 1014fb4: df000515 stw fp,20(sp) + 1014fb8: df000504 addi fp,sp,20 + 1014fbc: e13fff0d sth r4,-4(fp) + INT8U y; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 1014fc0: e03ffd15 stw zero,-12(fp) +#endif + + + + if (OSIntNesting > 0) { /* See if trying to call from an ISR */ + 1014fc4: 008040b4 movhi r2,258 + 1014fc8: 10b31e04 addi r2,r2,-13192 + 1014fcc: 10800003 ldbu r2,0(r2) + 1014fd0: 10803fcc andi r2,r2,255 + 1014fd4: 1004c03a cmpne r2,r2,zero + 1014fd8: 1000421e bne r2,zero,10150e4 + return; + } + if (ticks > 0) { /* 0 means no delay! */ + 1014fdc: e0bfff0b ldhu r2,-4(fp) + 1014fe0: 1005003a cmpeq r2,r2,zero + 1014fe4: 10003f1e bne r2,zero,10150e4 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1014fe8: 0005303a rdctl r2,status + 1014fec: e0bffc15 stw r2,-16(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1014ff0: e0fffc17 ldw r3,-16(fp) + 1014ff4: 00bfff84 movi r2,-2 + 1014ff8: 1884703a and r2,r3,r2 + 1014ffc: 1001703a wrctl status,r2 + + return context; + 1015000: e0bffc17 ldw r2,-16(fp) + OS_ENTER_CRITICAL(); + 1015004: e0bffd15 stw r2,-12(fp) + y = OSTCBCur->OSTCBY; /* Delay current task */ + 1015008: 008040b4 movhi r2,258 + 101500c: 10b31f04 addi r2,r2,-13188 + 1015010: 10800017 ldw r2,0(r2) + 1015014: 10800d03 ldbu r2,52(r2) + 1015018: e0bffe05 stb r2,-8(fp) + OSRdyTbl[y] &= ~OSTCBCur->OSTCBBitX; + 101501c: e13ffe03 ldbu r4,-8(fp) + 1015020: e0fffe03 ldbu r3,-8(fp) + 1015024: 008040b4 movhi r2,258 + 1015028: 10b31c44 addi r2,r2,-13199 + 101502c: 10c5883a add r2,r2,r3 + 1015030: 10800003 ldbu r2,0(r2) + 1015034: 1007883a mov r3,r2 + 1015038: 008040b4 movhi r2,258 + 101503c: 10b31f04 addi r2,r2,-13188 + 1015040: 10800017 ldw r2,0(r2) + 1015044: 10800d43 ldbu r2,53(r2) + 1015048: 0084303a nor r2,zero,r2 + 101504c: 1884703a and r2,r3,r2 + 1015050: 1007883a mov r3,r2 + 1015054: 008040b4 movhi r2,258 + 1015058: 10b31c44 addi r2,r2,-13199 + 101505c: 1105883a add r2,r2,r4 + 1015060: 10c00005 stb r3,0(r2) + if (OSRdyTbl[y] == 0) { + 1015064: e0fffe03 ldbu r3,-8(fp) + 1015068: 008040b4 movhi r2,258 + 101506c: 10b31c44 addi r2,r2,-13199 + 1015070: 10c5883a add r2,r2,r3 + 1015074: 10800003 ldbu r2,0(r2) + 1015078: 10803fcc andi r2,r2,255 + 101507c: 1004c03a cmpne r2,r2,zero + 1015080: 10000e1e bne r2,zero,10150bc + OSRdyGrp &= ~OSTCBCur->OSTCBBitY; + 1015084: 008040b4 movhi r2,258 + 1015088: 10b31f04 addi r2,r2,-13188 + 101508c: 10800017 ldw r2,0(r2) + 1015090: 10800d83 ldbu r2,54(r2) + 1015094: 0084303a nor r2,zero,r2 + 1015098: 1007883a mov r3,r2 + 101509c: 008040b4 movhi r2,258 + 10150a0: 10b31c04 addi r2,r2,-13200 + 10150a4: 10800003 ldbu r2,0(r2) + 10150a8: 1884703a and r2,r3,r2 + 10150ac: 1007883a mov r3,r2 + 10150b0: 008040b4 movhi r2,258 + 10150b4: 10b31c04 addi r2,r2,-13200 + 10150b8: 10c00005 stb r3,0(r2) + } + OSTCBCur->OSTCBDly = ticks; /* Load ticks in TCB */ + 10150bc: 008040b4 movhi r2,258 + 10150c0: 10b31f04 addi r2,r2,-13188 + 10150c4: 10c00017 ldw r3,0(r2) + 10150c8: e0bfff0b ldhu r2,-4(fp) + 10150cc: 18800b8d sth r2,46(r3) + 10150d0: e0bffd17 ldw r2,-12(fp) + 10150d4: e0bffb15 stw r2,-20(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 10150d8: e0bffb17 ldw r2,-20(fp) + 10150dc: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + OS_Sched(); /* Find next task to run! */ + 10150e0: 100ecb80 call 100ecb8 + } +} + 10150e4: e037883a mov sp,fp + 10150e8: dfc00117 ldw ra,4(sp) + 10150ec: df000017 ldw fp,0(sp) + 10150f0: dec00204 addi sp,sp,8 + 10150f4: f800283a ret + +010150f8 : +********************************************************************************************************* +*/ + +#if OS_TIME_DLY_HMSM_EN > 0 +INT8U OSTimeDlyHMSM (INT8U hours, INT8U minutes, INT8U seconds, INT16U ms) +{ + 10150f8: defff604 addi sp,sp,-40 + 10150fc: dfc00915 stw ra,36(sp) + 1015100: df000815 stw fp,32(sp) + 1015104: dc000715 stw r16,28(sp) + 1015108: df000704 addi fp,sp,28 + 101510c: e13ffb05 stb r4,-20(fp) + 1015110: e17ffc05 stb r5,-16(fp) + 1015114: e1bffd05 stb r6,-12(fp) + 1015118: e1fffe0d sth r7,-8(fp) + INT32U ticks; + INT16U loops; + + + if (OSIntNesting > 0) { /* See if trying to call from an ISR */ + 101511c: 008040b4 movhi r2,258 + 1015120: 10b31e04 addi r2,r2,-13192 + 1015124: 10800003 ldbu r2,0(r2) + 1015128: 10803fcc andi r2,r2,255 + 101512c: 1005003a cmpeq r2,r2,zero + 1015130: 1000031e bne r2,zero,1015140 + return (OS_ERR_TIME_DLY_ISR); + 1015134: 00801544 movi r2,85 + 1015138: e0bfff15 stw r2,-4(fp) + 101513c: 00004406 br 1015250 + } +#if OS_ARG_CHK_EN > 0 + if (hours == 0) { + 1015140: e0bffb03 ldbu r2,-20(fp) + 1015144: 1004c03a cmpne r2,r2,zero + 1015148: 10000c1e bne r2,zero,101517c + if (minutes == 0) { + 101514c: e0bffc03 ldbu r2,-16(fp) + 1015150: 1004c03a cmpne r2,r2,zero + 1015154: 1000091e bne r2,zero,101517c + if (seconds == 0) { + 1015158: e0bffd03 ldbu r2,-12(fp) + 101515c: 1004c03a cmpne r2,r2,zero + 1015160: 1000061e bne r2,zero,101517c + if (ms == 0) { + 1015164: e0bffe0b ldhu r2,-8(fp) + 1015168: 1004c03a cmpne r2,r2,zero + 101516c: 1000031e bne r2,zero,101517c + return (OS_ERR_TIME_ZERO_DLY); + 1015170: 00801504 movi r2,84 + 1015174: e0bfff15 stw r2,-4(fp) + 1015178: 00003506 br 1015250 + } + } + } + } + if (minutes > 59) { + 101517c: e0bffc03 ldbu r2,-16(fp) + 1015180: 10800f30 cmpltui r2,r2,60 + 1015184: 1000031e bne r2,zero,1015194 + return (OS_ERR_TIME_INVALID_MINUTES); /* Validate arguments to be within range */ + 1015188: 00801444 movi r2,81 + 101518c: e0bfff15 stw r2,-4(fp) + 1015190: 00002f06 br 1015250 + } + if (seconds > 59) { + 1015194: e0bffd03 ldbu r2,-12(fp) + 1015198: 10800f30 cmpltui r2,r2,60 + 101519c: 1000031e bne r2,zero,10151ac + return (OS_ERR_TIME_INVALID_SECONDS); + 10151a0: 00801484 movi r2,82 + 10151a4: e0bfff15 stw r2,-4(fp) + 10151a8: 00002906 br 1015250 + } + if (ms > 999) { + 10151ac: e0bffe0b ldhu r2,-8(fp) + 10151b0: 1080fa30 cmpltui r2,r2,1000 + 10151b4: 1000031e bne r2,zero,10151c4 + return (OS_ERR_TIME_INVALID_MS); + 10151b8: 008014c4 movi r2,83 + 10151bc: e0bfff15 stw r2,-4(fp) + 10151c0: 00002306 br 1015250 + } +#endif + /* Compute the total number of clock ticks required.. */ + /* .. (rounded to the nearest tick) */ + ticks = ((INT32U)hours * 3600L + (INT32U)minutes * 60L + (INT32U)seconds) * OS_TICKS_PER_SEC + 10151c4: e0bffb03 ldbu r2,-20(fp) + 10151c8: 10c38424 muli r3,r2,3600 + 10151cc: e0bffc03 ldbu r2,-16(fp) + 10151d0: 10800f24 muli r2,r2,60 + 10151d4: 1887883a add r3,r3,r2 + 10151d8: e0bffd03 ldbu r2,-12(fp) + 10151dc: 1885883a add r2,r3,r2 + 10151e0: 1400fa24 muli r16,r2,1000 + 10151e4: e0bffe0b ldhu r2,-8(fp) + 10151e8: 1100fa24 muli r4,r2,1000 + 10151ec: 0140fa04 movi r5,1000 + 10151f0: 100bc340 call 100bc34 <__udivsi3> + 10151f4: 8085883a add r2,r16,r2 + 10151f8: e0bffa15 stw r2,-24(fp) + + OS_TICKS_PER_SEC * ((INT32U)ms + 500L / OS_TICKS_PER_SEC) / 1000L; + loops = (INT16U)(ticks >> 16); /* Compute the integral number of 65536 tick delays */ + 10151fc: e0bffa17 ldw r2,-24(fp) + 1015200: 1004d43a srli r2,r2,16 + 1015204: e0bff90d sth r2,-28(fp) + ticks = ticks & 0xFFFFL; /* Obtain the fractional number of ticks */ + 1015208: e0bffa17 ldw r2,-24(fp) + 101520c: 10bfffcc andi r2,r2,65535 + 1015210: e0bffa15 stw r2,-24(fp) + OSTimeDly((INT16U)ticks); + 1015214: e0bffa17 ldw r2,-24(fp) + 1015218: 113fffcc andi r4,r2,65535 + 101521c: 1014fac0 call 1014fac + while (loops > 0) { + 1015220: 00000706 br 1015240 + OSTimeDly((INT16U)32768u); + 1015224: 01200014 movui r4,32768 + 1015228: 1014fac0 call 1014fac + OSTimeDly((INT16U)32768u); + 101522c: 01200014 movui r4,32768 + 1015230: 1014fac0 call 1014fac + loops--; + 1015234: e0bff90b ldhu r2,-28(fp) + 1015238: 10bfffc4 addi r2,r2,-1 + 101523c: e0bff90d sth r2,-28(fp) + ticks = ((INT32U)hours * 3600L + (INT32U)minutes * 60L + (INT32U)seconds) * OS_TICKS_PER_SEC + + OS_TICKS_PER_SEC * ((INT32U)ms + 500L / OS_TICKS_PER_SEC) / 1000L; + loops = (INT16U)(ticks >> 16); /* Compute the integral number of 65536 tick delays */ + ticks = ticks & 0xFFFFL; /* Obtain the fractional number of ticks */ + OSTimeDly((INT16U)ticks); + while (loops > 0) { + 1015240: e0bff90b ldhu r2,-28(fp) + 1015244: 1004c03a cmpne r2,r2,zero + 1015248: 103ff61e bne r2,zero,1015224 + OSTimeDly((INT16U)32768u); + OSTimeDly((INT16U)32768u); + loops--; + } + return (OS_ERR_NONE); + 101524c: e03fff15 stw zero,-4(fp) + 1015250: e0bfff17 ldw r2,-4(fp) +} + 1015254: e037883a mov sp,fp + 1015258: dfc00217 ldw ra,8(sp) + 101525c: df000117 ldw fp,4(sp) + 1015260: dc000017 ldw r16,0(sp) + 1015264: dec00304 addi sp,sp,12 + 1015268: f800283a ret + +0101526c : +********************************************************************************************************* +*/ + +#if OS_TIME_DLY_RESUME_EN > 0 +INT8U OSTimeDlyResume (INT8U prio) +{ + 101526c: defff404 addi sp,sp,-48 + 1015270: dfc00b15 stw ra,44(sp) + 1015274: df000a15 stw fp,40(sp) + 1015278: df000a04 addi fp,sp,40 + 101527c: e13ffe05 stb r4,-8(fp) + OS_TCB *ptcb; +#if OS_CRITICAL_METHOD == 3 /* Storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 1015280: e03ffc15 stw zero,-16(fp) +#endif + + + + if (prio >= OS_LOWEST_PRIO) { + 1015284: e0bffe03 ldbu r2,-8(fp) + 1015288: 10800530 cmpltui r2,r2,20 + 101528c: 1000031e bne r2,zero,101529c + return (OS_ERR_PRIO_INVALID); + 1015290: 00800a84 movi r2,42 + 1015294: e0bfff15 stw r2,-4(fp) + 1015298: 00007206 br 1015464 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 101529c: 0005303a rdctl r2,status + 10152a0: e0bffb15 stw r2,-20(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 10152a4: e0fffb17 ldw r3,-20(fp) + 10152a8: 00bfff84 movi r2,-2 + 10152ac: 1884703a and r2,r3,r2 + 10152b0: 1001703a wrctl status,r2 + + return context; + 10152b4: e0bffb17 ldw r2,-20(fp) + } + OS_ENTER_CRITICAL(); + 10152b8: e0bffc15 stw r2,-16(fp) + ptcb = OSTCBPrioTbl[prio]; /* Make sure that task exist */ + 10152bc: e0bffe03 ldbu r2,-8(fp) + 10152c0: 00c040b4 movhi r3,258 + 10152c4: 18d9a904 addi r3,r3,26276 + 10152c8: 1085883a add r2,r2,r2 + 10152cc: 1085883a add r2,r2,r2 + 10152d0: 10c5883a add r2,r2,r3 + 10152d4: 10800017 ldw r2,0(r2) + 10152d8: e0bffd15 stw r2,-12(fp) + if (ptcb == (OS_TCB *)0) { + 10152dc: e0bffd17 ldw r2,-12(fp) + 10152e0: 1004c03a cmpne r2,r2,zero + 10152e4: 1000071e bne r2,zero,1015304 + 10152e8: e0bffc17 ldw r2,-16(fp) + 10152ec: e0bffa15 stw r2,-24(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 10152f0: e0bffa17 ldw r2,-24(fp) + 10152f4: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_NOT_EXIST); /* The task does not exist */ + 10152f8: 008010c4 movi r2,67 + 10152fc: e0bfff15 stw r2,-4(fp) + 1015300: 00005806 br 1015464 + } + if (ptcb == OS_TCB_RESERVED) { + 1015304: e0bffd17 ldw r2,-12(fp) + 1015308: 10800058 cmpnei r2,r2,1 + 101530c: 1000071e bne r2,zero,101532c + 1015310: e0bffc17 ldw r2,-16(fp) + 1015314: e0bff915 stw r2,-28(fp) + 1015318: e0bff917 ldw r2,-28(fp) + 101531c: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_NOT_EXIST); /* The task does not exist */ + 1015320: 008010c4 movi r2,67 + 1015324: e0bfff15 stw r2,-4(fp) + 1015328: 00004e06 br 1015464 + } + if (ptcb->OSTCBDly == 0) { /* See if task is delayed */ + 101532c: e0bffd17 ldw r2,-12(fp) + 1015330: 10800b8b ldhu r2,46(r2) + 1015334: 10bfffcc andi r2,r2,65535 + 1015338: 1004c03a cmpne r2,r2,zero + 101533c: 1000071e bne r2,zero,101535c + 1015340: e0bffc17 ldw r2,-16(fp) + 1015344: e0bff815 stw r2,-32(fp) + 1015348: e0bff817 ldw r2,-32(fp) + 101534c: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_TIME_NOT_DLY); /* Indicate that task was not delayed */ + 1015350: 00801404 movi r2,80 + 1015354: e0bfff15 stw r2,-4(fp) + 1015358: 00004206 br 1015464 + } + + ptcb->OSTCBDly = 0; /* Clear the time delay */ + 101535c: e0bffd17 ldw r2,-12(fp) + 1015360: 10000b8d sth zero,46(r2) + if ((ptcb->OSTCBStat & OS_STAT_PEND_ANY) != OS_STAT_RDY) { + 1015364: e0bffd17 ldw r2,-12(fp) + 1015368: 10800c03 ldbu r2,48(r2) + 101536c: 10803fcc andi r2,r2,255 + 1015370: 10800dcc andi r2,r2,55 + 1015374: 1005003a cmpeq r2,r2,zero + 1015378: 10000b1e bne r2,zero,10153a8 + ptcb->OSTCBStat &= ~OS_STAT_PEND_ANY; /* Yes, Clear status flag */ + 101537c: e0bffd17 ldw r2,-12(fp) + 1015380: 10c00c03 ldbu r3,48(r2) + 1015384: 00bff204 movi r2,-56 + 1015388: 1884703a and r2,r3,r2 + 101538c: 1007883a mov r3,r2 + 1015390: e0bffd17 ldw r2,-12(fp) + 1015394: 10c00c05 stb r3,48(r2) + ptcb->OSTCBStatPend = OS_STAT_PEND_TO; /* Indicate PEND timeout */ + 1015398: e0fffd17 ldw r3,-12(fp) + 101539c: 00800044 movi r2,1 + 10153a0: 18800c45 stb r2,49(r3) + 10153a4: 00000206 br 10153b0 + } else { + ptcb->OSTCBStatPend = OS_STAT_PEND_OK; + 10153a8: e0bffd17 ldw r2,-12(fp) + 10153ac: 10000c45 stb zero,49(r2) + } + if ((ptcb->OSTCBStat & OS_STAT_SUSPEND) == OS_STAT_RDY) { /* Is task suspended? */ + 10153b0: e0bffd17 ldw r2,-12(fp) + 10153b4: 10800c03 ldbu r2,48(r2) + 10153b8: 10803fcc andi r2,r2,255 + 10153bc: 1080020c andi r2,r2,8 + 10153c0: 1004c03a cmpne r2,r2,zero + 10153c4: 1000221e bne r2,zero,1015450 + OSRdyGrp |= ptcb->OSTCBBitY; /* No, Make ready */ + 10153c8: e0bffd17 ldw r2,-12(fp) + 10153cc: 10c00d83 ldbu r3,54(r2) + 10153d0: 008040b4 movhi r2,258 + 10153d4: 10b31c04 addi r2,r2,-13200 + 10153d8: 10800003 ldbu r2,0(r2) + 10153dc: 1884b03a or r2,r3,r2 + 10153e0: 1007883a mov r3,r2 + 10153e4: 008040b4 movhi r2,258 + 10153e8: 10b31c04 addi r2,r2,-13200 + 10153ec: 10c00005 stb r3,0(r2) + OSRdyTbl[ptcb->OSTCBY] |= ptcb->OSTCBBitX; + 10153f0: e0bffd17 ldw r2,-12(fp) + 10153f4: 10800d03 ldbu r2,52(r2) + 10153f8: 11003fcc andi r4,r2,255 + 10153fc: e0bffd17 ldw r2,-12(fp) + 1015400: 10800d03 ldbu r2,52(r2) + 1015404: 10c03fcc andi r3,r2,255 + 1015408: 008040b4 movhi r2,258 + 101540c: 10b31c44 addi r2,r2,-13199 + 1015410: 10c5883a add r2,r2,r3 + 1015414: 10c00003 ldbu r3,0(r2) + 1015418: e0bffd17 ldw r2,-12(fp) + 101541c: 10800d43 ldbu r2,53(r2) + 1015420: 1884b03a or r2,r3,r2 + 1015424: 1007883a mov r3,r2 + 1015428: 008040b4 movhi r2,258 + 101542c: 10b31c44 addi r2,r2,-13199 + 1015430: 1105883a add r2,r2,r4 + 1015434: 10c00005 stb r3,0(r2) + 1015438: e0bffc17 ldw r2,-16(fp) + 101543c: e0bff715 stw r2,-36(fp) + 1015440: e0bff717 ldw r2,-36(fp) + 1015444: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + OS_Sched(); /* See if this is new highest priority */ + 1015448: 100ecb80 call 100ecb8 + 101544c: 00000406 br 1015460 + 1015450: e0bffc17 ldw r2,-16(fp) + 1015454: e0bff615 stw r2,-40(fp) + 1015458: e0bff617 ldw r2,-40(fp) + 101545c: 1001703a wrctl status,r2 + } else { + OS_EXIT_CRITICAL(); /* Task may be suspended */ + } + return (OS_ERR_NONE); + 1015460: e03fff15 stw zero,-4(fp) + 1015464: e0bfff17 ldw r2,-4(fp) +} + 1015468: e037883a mov sp,fp + 101546c: dfc00117 ldw ra,4(sp) + 1015470: df000017 ldw fp,0(sp) + 1015474: dec00204 addi sp,sp,8 + 1015478: f800283a ret + +0101547c : +********************************************************************************************************* +*/ + +#if OS_TIME_GET_SET_EN > 0 +INT32U OSTimeGet (void) +{ + 101547c: defffb04 addi sp,sp,-20 + 1015480: df000415 stw fp,16(sp) + 1015484: df000404 addi fp,sp,16 + INT32U ticks; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 1015488: e03ffe15 stw zero,-8(fp) +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 101548c: 0005303a rdctl r2,status + 1015490: e0bffd15 stw r2,-12(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1015494: e0fffd17 ldw r3,-12(fp) + 1015498: 00bfff84 movi r2,-2 + 101549c: 1884703a and r2,r3,r2 + 10154a0: 1001703a wrctl status,r2 + + return context; + 10154a4: e0bffd17 ldw r2,-12(fp) +#endif + + + + OS_ENTER_CRITICAL(); + 10154a8: e0bffe15 stw r2,-8(fp) + ticks = OSTime; + 10154ac: 008040b4 movhi r2,258 + 10154b0: 10b32004 addi r2,r2,-13184 + 10154b4: 10800017 ldw r2,0(r2) + 10154b8: e0bfff15 stw r2,-4(fp) + 10154bc: e0bffe17 ldw r2,-8(fp) + 10154c0: e0bffc15 stw r2,-16(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 10154c4: e0bffc17 ldw r2,-16(fp) + 10154c8: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (ticks); + 10154cc: e0bfff17 ldw r2,-4(fp) +} + 10154d0: e037883a mov sp,fp + 10154d4: df000017 ldw fp,0(sp) + 10154d8: dec00104 addi sp,sp,4 + 10154dc: f800283a ret + +010154e0 : +********************************************************************************************************* +*/ + +#if OS_TIME_GET_SET_EN > 0 +void OSTimeSet (INT32U ticks) +{ + 10154e0: defffb04 addi sp,sp,-20 + 10154e4: df000415 stw fp,16(sp) + 10154e8: df000404 addi fp,sp,16 + 10154ec: e13fff15 stw r4,-4(fp) +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 10154f0: e03ffe15 stw zero,-8(fp) +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 10154f4: 0005303a rdctl r2,status + 10154f8: e0bffd15 stw r2,-12(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 10154fc: e0fffd17 ldw r3,-12(fp) + 1015500: 00bfff84 movi r2,-2 + 1015504: 1884703a and r2,r3,r2 + 1015508: 1001703a wrctl status,r2 + + return context; + 101550c: e0bffd17 ldw r2,-12(fp) +#endif + + + + OS_ENTER_CRITICAL(); + 1015510: e0bffe15 stw r2,-8(fp) + OSTime = ticks; + 1015514: 00c040b4 movhi r3,258 + 1015518: 18f32004 addi r3,r3,-13184 + 101551c: e0bfff17 ldw r2,-4(fp) + 1015520: 18800015 stw r2,0(r3) + 1015524: e0bffe17 ldw r2,-8(fp) + 1015528: e0bffc15 stw r2,-16(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 101552c: e0bffc17 ldw r2,-16(fp) + 1015530: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); +} + 1015534: e037883a mov sp,fp + 1015538: df000017 ldw fp,0(sp) + 101553c: dec00104 addi sp,sp,4 + 1015540: f800283a ret + +01015544 : + * The "base" parameter is ignored and only + * present for backwards-compatibility. + */ + +void alt_irq_init ( const void* base ) +{ + 1015544: defffd04 addi sp,sp,-12 + 1015548: dfc00215 stw ra,8(sp) + 101554c: df000115 stw fp,4(sp) + 1015550: df000104 addi fp,sp,4 + 1015554: e13fff15 stw r4,-4(fp) + ALTERA_NIOS2_QSYS_IRQ_INIT ( CPU, cpu); + 1015558: 101800c0 call 101800c + * alt_irq_cpu_enable_interrupts() enables the CPU to start taking interrupts. + */ +static ALT_INLINE void ALT_ALWAYS_INLINE + alt_irq_cpu_enable_interrupts () +{ + NIOS2_WRITE_STATUS(NIOS2_STATUS_PIE_MSK + 101555c: 00800044 movi r2,1 + 1015560: 1001703a wrctl status,r2 + alt_irq_cpu_enable_interrupts(); +} + 1015564: e037883a mov sp,fp + 1015568: dfc00117 ldw ra,4(sp) + 101556c: df000017 ldw fp,0(sp) + 1015570: dec00204 addi sp,sp,8 + 1015574: f800283a ret + +01015578 : + * Initialize the non-interrupt controller devices. + * Called after alt_irq_init(). + */ + +void alt_sys_init( void ) +{ + 1015578: defffe04 addi sp,sp,-8 + 101557c: dfc00115 stw ra,4(sp) + 1015580: df000015 stw fp,0(sp) + 1015584: d839883a mov fp,sp + ALTERA_AVALON_TIMER_INIT ( SYS_CLK_TIMER, sys_clk_timer); + 1015588: 01008034 movhi r4,512 + 101558c: 21041804 addi r4,r4,4192 + 1015590: 000b883a mov r5,zero + 1015594: 000d883a mov r6,zero + 1015598: 01c0fa04 movi r7,1000 + 101559c: 10164240 call 1016424 + ALTERA_AVALON_JTAG_UART_INIT ( JTAG_UART_0, jtag_uart_0); + 10155a0: 010040b4 movhi r4,258 + 10155a4: 21270904 addi r4,r4,-25564 + 10155a8: 000b883a mov r5,zero + 10155ac: 01800384 movi r6,14 + 10155b0: 10157a00 call 10157a0 + 10155b4: 010040b4 movhi r4,258 + 10155b8: 2126ff04 addi r4,r4,-25604 + 10155bc: 10156200 call 1015620 + ALTERA_AVALON_SYSID_QSYS_INIT ( SYSID, sysid); + ALTERA_AVALON_UART_INIT ( UART_MC, uart_mc); + 10155c0: 010040b4 movhi r4,258 + 10155c4: 212b2404 addi r4,r4,-21360 + 10155c8: 000b883a mov r5,zero + 10155cc: 01800144 movi r6,5 + 10155d0: 10165a40 call 10165a4 + 10155d4: 010040b4 movhi r4,258 + 10155d8: 212b1a04 addi r4,r4,-21400 + 10155dc: 10156200 call 1015620 + ALTERA_AVALON_UART_INIT ( UART_WIFI, uart_wifi); + 10155e0: 010040b4 movhi r4,258 + 10155e4: 212b5804 addi r4,r4,-21152 + 10155e8: 000b883a mov r5,zero + 10155ec: 01800104 movi r6,4 + 10155f0: 10165a40 call 10165a4 + 10155f4: 010040b4 movhi r4,258 + 10155f8: 212b4e04 addi r4,r4,-21192 + 10155fc: 10156200 call 1015620 + ALTERA_UP_AVALON_RS232_INIT ( RS232_WIFI, rs232_wifi); + 1015600: 010040b4 movhi r4,258 + 1015604: 212b8204 addi r4,r4,-20984 + 1015608: 10156200 call 1015620 +} + 101560c: e037883a mov sp,fp + 1015610: dfc00117 ldw ra,4(sp) + 1015614: df000017 ldw fp,0(sp) + 1015618: dec00204 addi sp,sp,8 + 101561c: f800283a ret + +01015620 : + */ + +extern int alt_fs_reg (alt_dev* dev); + +static ALT_INLINE int alt_dev_reg (alt_dev* dev) +{ + 1015620: defffd04 addi sp,sp,-12 + 1015624: dfc00215 stw ra,8(sp) + 1015628: df000115 stw fp,4(sp) + 101562c: df000104 addi fp,sp,4 + 1015630: e13fff15 stw r4,-4(fp) + extern alt_llist alt_dev_list; + + return alt_dev_llist_insert ((alt_dev_llist*) dev, &alt_dev_list); + 1015634: e13fff17 ldw r4,-4(fp) + 1015638: 014040b4 movhi r5,258 + 101563c: 296b9e04 addi r5,r5,-20872 + 1015640: 10176040 call 1017604 +} + 1015644: e037883a mov sp,fp + 1015648: dfc00117 ldw ra,4(sp) + 101564c: df000017 ldw fp,0(sp) + 1015650: dec00204 addi sp,sp,8 + 1015654: f800283a ret + +01015658 : + * + */ + +int +altera_avalon_jtag_uart_read_fd(alt_fd* fd, char* buffer, int space) +{ + 1015658: defffa04 addi sp,sp,-24 + 101565c: dfc00515 stw ra,20(sp) + 1015660: df000415 stw fp,16(sp) + 1015664: df000404 addi fp,sp,16 + 1015668: e13ffd15 stw r4,-12(fp) + 101566c: e17ffe15 stw r5,-8(fp) + 1015670: e1bfff15 stw r6,-4(fp) + altera_avalon_jtag_uart_dev* dev = (altera_avalon_jtag_uart_dev*) fd->dev; + 1015674: e0bffd17 ldw r2,-12(fp) + 1015678: 10800017 ldw r2,0(r2) + 101567c: e0bffc15 stw r2,-16(fp) + + return altera_avalon_jtag_uart_read(&dev->state, buffer, space, + 1015680: e0bffc17 ldw r2,-16(fp) + 1015684: 11000a04 addi r4,r2,40 + 1015688: e0bffd17 ldw r2,-12(fp) + 101568c: 11c00217 ldw r7,8(r2) + 1015690: e17ffe17 ldw r5,-8(fp) + 1015694: e1bfff17 ldw r6,-4(fp) + 1015698: 1015e140 call 1015e14 + fd->fd_flags); +} + 101569c: e037883a mov sp,fp + 10156a0: dfc00117 ldw ra,4(sp) + 10156a4: df000017 ldw fp,0(sp) + 10156a8: dec00204 addi sp,sp,8 + 10156ac: f800283a ret + +010156b0 : + +int +altera_avalon_jtag_uart_write_fd(alt_fd* fd, const char* buffer, int space) +{ + 10156b0: defffa04 addi sp,sp,-24 + 10156b4: dfc00515 stw ra,20(sp) + 10156b8: df000415 stw fp,16(sp) + 10156bc: df000404 addi fp,sp,16 + 10156c0: e13ffd15 stw r4,-12(fp) + 10156c4: e17ffe15 stw r5,-8(fp) + 10156c8: e1bfff15 stw r6,-4(fp) + altera_avalon_jtag_uart_dev* dev = (altera_avalon_jtag_uart_dev*) fd->dev; + 10156cc: e0bffd17 ldw r2,-12(fp) + 10156d0: 10800017 ldw r2,0(r2) + 10156d4: e0bffc15 stw r2,-16(fp) + + return altera_avalon_jtag_uart_write(&dev->state, buffer, space, + 10156d8: e0bffc17 ldw r2,-16(fp) + 10156dc: 11000a04 addi r4,r2,40 + 10156e0: e0bffd17 ldw r2,-12(fp) + 10156e4: 11c00217 ldw r7,8(r2) + 10156e8: e17ffe17 ldw r5,-8(fp) + 10156ec: e1bfff17 ldw r6,-4(fp) + 10156f0: 10160d40 call 10160d4 + fd->fd_flags); +} + 10156f4: e037883a mov sp,fp + 10156f8: dfc00117 ldw ra,4(sp) + 10156fc: df000017 ldw fp,0(sp) + 1015700: dec00204 addi sp,sp,8 + 1015704: f800283a ret + +01015708 : + +#ifndef ALTERA_AVALON_JTAG_UART_SMALL + +int +altera_avalon_jtag_uart_close_fd(alt_fd* fd) +{ + 1015708: defffc04 addi sp,sp,-16 + 101570c: dfc00315 stw ra,12(sp) + 1015710: df000215 stw fp,8(sp) + 1015714: df000204 addi fp,sp,8 + 1015718: e13fff15 stw r4,-4(fp) + altera_avalon_jtag_uart_dev* dev = (altera_avalon_jtag_uart_dev*) fd->dev; + 101571c: e0bfff17 ldw r2,-4(fp) + 1015720: 10800017 ldw r2,0(r2) + 1015724: e0bffe15 stw r2,-8(fp) + + return altera_avalon_jtag_uart_close(&dev->state, fd->fd_flags); + 1015728: e0bffe17 ldw r2,-8(fp) + 101572c: 11000a04 addi r4,r2,40 + 1015730: e0bfff17 ldw r2,-4(fp) + 1015734: 11400217 ldw r5,8(r2) + 1015738: 1015cac0 call 1015cac +} + 101573c: e037883a mov sp,fp + 1015740: dfc00117 ldw ra,4(sp) + 1015744: df000017 ldw fp,0(sp) + 1015748: dec00204 addi sp,sp,8 + 101574c: f800283a ret + +01015750 : + +int +altera_avalon_jtag_uart_ioctl_fd(alt_fd* fd, int req, void* arg) +{ + 1015750: defffa04 addi sp,sp,-24 + 1015754: dfc00515 stw ra,20(sp) + 1015758: df000415 stw fp,16(sp) + 101575c: df000404 addi fp,sp,16 + 1015760: e13ffd15 stw r4,-12(fp) + 1015764: e17ffe15 stw r5,-8(fp) + 1015768: e1bfff15 stw r6,-4(fp) + altera_avalon_jtag_uart_dev* dev = (altera_avalon_jtag_uart_dev*) fd->dev; + 101576c: e0bffd17 ldw r2,-12(fp) + 1015770: 10800017 ldw r2,0(r2) + 1015774: e0bffc15 stw r2,-16(fp) + + return altera_avalon_jtag_uart_ioctl(&dev->state, req, arg); + 1015778: e0bffc17 ldw r2,-16(fp) + 101577c: 11000a04 addi r4,r2,40 + 1015780: e17ffe17 ldw r5,-8(fp) + 1015784: e1bfff17 ldw r6,-4(fp) + 1015788: 1015d200 call 1015d20 +} + 101578c: e037883a mov sp,fp + 1015790: dfc00117 ldw ra,4(sp) + 1015794: df000017 ldw fp,0(sp) + 1015798: dec00204 addi sp,sp,8 + 101579c: f800283a ret + +010157a0 : + * Return 1 on sucessful IRQ register and 0 on failure. + */ + +void altera_avalon_jtag_uart_init(altera_avalon_jtag_uart_state* sp, + int irq_controller_id, int irq) +{ + 10157a0: defff504 addi sp,sp,-44 + 10157a4: dfc00a15 stw ra,40(sp) + 10157a8: df000915 stw fp,36(sp) + 10157ac: df000904 addi fp,sp,36 + 10157b0: e13ffd15 stw r4,-12(fp) + 10157b4: e17ffe15 stw r5,-8(fp) + 10157b8: e1bfff15 stw r6,-4(fp) + ALT_FLAG_CREATE(&sp->events, 0); + 10157bc: e0bffd17 ldw r2,-12(fp) + 10157c0: 10800c04 addi r2,r2,48 + 10157c4: e0bffb15 stw r2,-20(fp) + 10157c8: e03ffc0d sth zero,-16(fp) + +static ALT_INLINE int ALT_ALWAYS_INLINE alt_flag_create (OS_FLAG_GRP** pgroup, + OS_FLAGS flags) +{ + INT8U err; + *pgroup = OSFlagCreate (flags, &err); + 10157cc: e13ffc0b ldhu r4,-16(fp) + 10157d0: e17ffc84 addi r5,fp,-14 + 10157d4: 100f8600 call 100f860 + 10157d8: 1007883a mov r3,r2 + 10157dc: e0bffb17 ldw r2,-20(fp) + 10157e0: 10c00015 stw r3,0(r2) + ALT_SEM_CREATE(&sp->read_lock, 1); + 10157e4: e0bffd17 ldw r2,-12(fp) + 10157e8: 10800a04 addi r2,r2,40 + 10157ec: e0bff915 stw r2,-28(fp) + 10157f0: 00800044 movi r2,1 + 10157f4: e0bffa0d sth r2,-24(fp) + 10157f8: e13ffa0b ldhu r4,-24(fp) + 10157fc: 1012a640 call 1012a64 + 1015800: 1007883a mov r3,r2 + 1015804: e0bff917 ldw r2,-28(fp) + 1015808: 10c00015 stw r3,0(r2) + ALT_SEM_CREATE(&sp->write_lock, 1); + 101580c: e0bffd17 ldw r2,-12(fp) + 1015810: 10800b04 addi r2,r2,44 + 1015814: e0bff715 stw r2,-36(fp) + 1015818: 00800044 movi r2,1 + 101581c: e0bff80d sth r2,-32(fp) + 1015820: e13ff80b ldhu r4,-32(fp) + 1015824: 1012a640 call 1012a64 + 1015828: 1007883a mov r3,r2 + 101582c: e0bff717 ldw r2,-36(fp) + 1015830: 10c00015 stw r3,0(r2) + + /* enable read interrupts at the device */ + sp->irq_enable = ALTERA_AVALON_JTAG_UART_CONTROL_RE_MSK; + 1015834: e0fffd17 ldw r3,-12(fp) + 1015838: 00800044 movi r2,1 + 101583c: 18800815 stw r2,32(r3) + + IOWR_ALTERA_AVALON_JTAG_UART_CONTROL(sp->base, sp->irq_enable); + 1015840: e0bffd17 ldw r2,-12(fp) + 1015844: 10800017 ldw r2,0(r2) + 1015848: 11000104 addi r4,r2,4 + 101584c: e0bffd17 ldw r2,-12(fp) + 1015850: 10800817 ldw r2,32(r2) + 1015854: 1007883a mov r3,r2 + 1015858: 2005883a mov r2,r4 + 101585c: 10c00035 stwio r3,0(r2) + /* register the interrupt handler */ +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT + alt_ic_isr_register(irq_controller_id, irq, altera_avalon_jtag_uart_irq, + sp, NULL); +#else + alt_irq_register(irq, sp, altera_avalon_jtag_uart_irq); + 1015860: e13fff17 ldw r4,-4(fp) + 1015864: e17ffd17 ldw r5,-12(fp) + 1015868: 01804074 movhi r6,257 + 101586c: 31963404 addi r6,r6,22736 + 1015870: 10179e00 call 10179e0 +#endif + + /* Register an alarm to go off every second to check for presence of host */ + sp->host_inactive = 0; + 1015874: e0bffd17 ldw r2,-12(fp) + 1015878: 10000915 stw zero,36(r2) + + if (alt_alarm_start(&sp->alarm, alt_ticks_per_second(), + 101587c: e0bffd17 ldw r2,-12(fp) + 1015880: 11000204 addi r4,r2,8 + * Obtain the system clock rate in ticks/s. + */ + +static ALT_INLINE alt_u32 ALT_ALWAYS_INLINE alt_ticks_per_second (void) +{ + return _alt_tick_rate; + 1015884: 008040b4 movhi r2,258 + 1015888: 10b32504 addi r2,r2,-13164 + 101588c: 10800017 ldw r2,0(r2) + 1015890: 100b883a mov r5,r2 + 1015894: 01804074 movhi r6,257 + 1015898: 3196e604 addi r6,r6,23448 + 101589c: e1fffd17 ldw r7,-12(fp) + 10158a0: 101746c0 call 101746c + 10158a4: 1004403a cmpge r2,r2,zero + 10158a8: 1000041e bne r2,zero,10158bc + &altera_avalon_jtag_uart_timeout, sp) < 0) + { + /* If we can't set the alarm then record "don't know if host present" + * and behave as though the host is present. + */ + sp->timeout = INT_MAX; + 10158ac: e0fffd17 ldw r3,-12(fp) + 10158b0: 00a00034 movhi r2,32768 + 10158b4: 10bfffc4 addi r2,r2,-1 + 10158b8: 18800115 stw r2,4(r3) + } + + /* ALT_LOG - see altera_hal/HAL/inc/sys/alt_log_printf.h */ + ALT_LOG_JTAG_UART_ALARM_REGISTER(sp, sp->base); +} + 10158bc: e037883a mov sp,fp + 10158c0: dfc00117 ldw ra,4(sp) + 10158c4: df000017 ldw fp,0(sp) + 10158c8: dec00204 addi sp,sp,8 + 10158cc: f800283a ret + +010158d0 : +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT +static void altera_avalon_jtag_uart_irq(void* context) +#else +static void altera_avalon_jtag_uart_irq(void* context, alt_u32 id) +#endif +{ + 10158d0: defff104 addi sp,sp,-60 + 10158d4: dfc00e15 stw ra,56(sp) + 10158d8: df000d15 stw fp,52(sp) + 10158dc: df000d04 addi fp,sp,52 + 10158e0: e13ffe15 stw r4,-8(fp) + 10158e4: e17fff15 stw r5,-4(fp) + altera_avalon_jtag_uart_state* sp = (altera_avalon_jtag_uart_state*) context; + 10158e8: e0bffe17 ldw r2,-8(fp) + 10158ec: e0bffc15 stw r2,-16(fp) + unsigned int base = sp->base; + 10158f0: e0bffc17 ldw r2,-16(fp) + 10158f4: 10800017 ldw r2,0(r2) + 10158f8: e0bffb15 stw r2,-20(fp) + 10158fc: 00000006 br 1015900 + /* ALT_LOG - see altera_hal/HAL/inc/sys/alt_log_printf.h */ + ALT_LOG_JTAG_UART_ISR_FUNCTION(base, sp); + + for ( ; ; ) + { + unsigned int control = IORD_ALTERA_AVALON_JTAG_UART_CONTROL(base); + 1015900: e0bffb17 ldw r2,-20(fp) + 1015904: 10800104 addi r2,r2,4 + 1015908: 10800037 ldwio r2,0(r2) + 101590c: e0bffa15 stw r2,-24(fp) + + /* Return once nothing more to do */ + if ((control & (ALTERA_AVALON_JTAG_UART_CONTROL_RI_MSK | ALTERA_AVALON_JTAG_UART_CONTROL_WI_MSK)) == 0) + 1015910: e0bffa17 ldw r2,-24(fp) + 1015914: 1080c00c andi r2,r2,768 + 1015918: 1005003a cmpeq r2,r2,zero + 101591c: 1000991e bne r2,zero,1015b84 + break; + + if (control & ALTERA_AVALON_JTAG_UART_CONTROL_RI_MSK) + 1015920: e0bffa17 ldw r2,-24(fp) + 1015924: 1080400c andi r2,r2,256 + 1015928: 1005003a cmpeq r2,r2,zero + 101592c: 1000481e bne r2,zero,1015a50 + { + /* process a read irq. Start by assuming that there is data in the + * receive FIFO (otherwise why would we have been interrupted?) + */ + unsigned int data = 1 << ALTERA_AVALON_JTAG_UART_DATA_RAVAIL_OFST; + 1015930: 00800074 movhi r2,1 + 1015934: e0bff915 stw r2,-28(fp) + 1015938: 00000006 br 101593c + for ( ; ; ) + { + /* Check whether there is space in the buffer. If not then we must not + * read any characters from the buffer as they will be lost. + */ + unsigned int next = (sp->rx_in + 1) % ALTERA_AVALON_JTAG_UART_BUF_LEN; + 101593c: e0bffc17 ldw r2,-16(fp) + 1015940: 10800d17 ldw r2,52(r2) + 1015944: 10800044 addi r2,r2,1 + 1015948: 1081ffcc andi r2,r2,2047 + 101594c: e0bff815 stw r2,-32(fp) + if (next == sp->rx_out) + 1015950: e0bffc17 ldw r2,-16(fp) + 1015954: 10c00e17 ldw r3,56(r2) + 1015958: e0bff817 ldw r2,-32(fp) + 101595c: 18802826 beq r3,r2,1015a00 + break; + + /* Try to remove a character from the FIFO and find out whether there + * are any more characters remaining. + */ + data = IORD_ALTERA_AVALON_JTAG_UART_DATA(base); + 1015960: e0bffb17 ldw r2,-20(fp) + 1015964: 10800037 ldwio r2,0(r2) + 1015968: e0bff915 stw r2,-28(fp) + + if ((data & ALTERA_AVALON_JTAG_UART_DATA_RVALID_MSK) == 0) + 101596c: e0bff917 ldw r2,-28(fp) + 1015970: 10a0000c andi r2,r2,32768 + 1015974: 1005003a cmpeq r2,r2,zero + 1015978: 1000211e bne r2,zero,1015a00 + break; + + sp->rx_buf[sp->rx_in] = (data & ALTERA_AVALON_JTAG_UART_DATA_DATA_MSK) >> ALTERA_AVALON_JTAG_UART_DATA_DATA_OFST; + 101597c: e0bffc17 ldw r2,-16(fp) + 1015980: 10c00d17 ldw r3,52(r2) + 1015984: e0bff917 ldw r2,-28(fp) + 1015988: 1009883a mov r4,r2 + 101598c: e0bffc17 ldw r2,-16(fp) + 1015990: 1885883a add r2,r3,r2 + 1015994: 10801104 addi r2,r2,68 + 1015998: 11000005 stb r4,0(r2) + sp->rx_in = (sp->rx_in + 1) % ALTERA_AVALON_JTAG_UART_BUF_LEN; + 101599c: e0bffc17 ldw r2,-16(fp) + 10159a0: 10800d17 ldw r2,52(r2) + 10159a4: 10800044 addi r2,r2,1 + 10159a8: 10c1ffcc andi r3,r2,2047 + 10159ac: e0bffc17 ldw r2,-16(fp) + 10159b0: 10c00d15 stw r3,52(r2) + + /* Post an event to notify jtag_uart_read that a character has been read */ + ALT_FLAG_POST (sp->events, ALT_JTAG_UART_READ_RDY, OS_FLAG_SET); + 10159b4: e0bffc17 ldw r2,-16(fp) + 10159b8: 10800c17 ldw r2,48(r2) + 10159bc: e0bff515 stw r2,-44(fp) + 10159c0: 00800044 movi r2,1 + 10159c4: e0bff60d sth r2,-40(fp) + 10159c8: 00800044 movi r2,1 + 10159cc: e0bff685 stb r2,-38(fp) + OS_FLAGS flags, + INT8U opt) +{ + INT8U err; + + if (OSRunning) + 10159d0: 008040b4 movhi r2,258 + 10159d4: 10b31044 addi r2,r2,-13247 + 10159d8: 10800003 ldbu r2,0(r2) + 10159dc: 10803fcc andi r2,r2,255 + 10159e0: 1005003a cmpeq r2,r2,zero + 10159e4: 103fd51e bne r2,zero,101593c + { + OSFlagPost (group, flags, opt, &err); + 10159e8: e17ff60b ldhu r5,-40(fp) + 10159ec: e1bff683 ldbu r6,-38(fp) + 10159f0: e1fffd04 addi r7,fp,-12 + 10159f4: e13ff517 ldw r4,-44(fp) + 10159f8: 10105880 call 1010588 + return err; + 10159fc: 003fcf06 br 101593c + } + + if (data & ALTERA_AVALON_JTAG_UART_DATA_RAVAIL_MSK) + 1015a00: e0bff917 ldw r2,-28(fp) + 1015a04: 10bfffec andhi r2,r2,65535 + 1015a08: 1005003a cmpeq r2,r2,zero + 1015a0c: 1000101e bne r2,zero,1015a50 + { + /* If there is still data available here then the buffer is full + * so turn off receive interrupts until some space becomes available. + */ + sp->irq_enable &= ~ALTERA_AVALON_JTAG_UART_CONTROL_RE_MSK; + 1015a10: e0bffc17 ldw r2,-16(fp) + 1015a14: 10c00817 ldw r3,32(r2) + 1015a18: 00bfff84 movi r2,-2 + 1015a1c: 1886703a and r3,r3,r2 + 1015a20: e0bffc17 ldw r2,-16(fp) + 1015a24: 10c00815 stw r3,32(r2) + IOWR_ALTERA_AVALON_JTAG_UART_CONTROL(base, sp->irq_enable); + 1015a28: e0bffb17 ldw r2,-20(fp) + 1015a2c: 11000104 addi r4,r2,4 + 1015a30: e0bffc17 ldw r2,-16(fp) + 1015a34: 10800817 ldw r2,32(r2) + 1015a38: 1007883a mov r3,r2 + 1015a3c: 2005883a mov r2,r4 + 1015a40: 10c00035 stwio r3,0(r2) + + /* Dummy read to ensure IRQ is cleared prior to ISR completion */ + IORD_ALTERA_AVALON_JTAG_UART_CONTROL(base); + 1015a44: e0bffb17 ldw r2,-20(fp) + 1015a48: 10800104 addi r2,r2,4 + 1015a4c: 10800037 ldwio r2,0(r2) + } + } + + if (control & ALTERA_AVALON_JTAG_UART_CONTROL_WI_MSK) + 1015a50: e0bffa17 ldw r2,-24(fp) + 1015a54: 1080800c andi r2,r2,512 + 1015a58: 1005003a cmpeq r2,r2,zero + 1015a5c: 103fa81e bne r2,zero,1015900 + { + /* process a write irq */ + unsigned int space = (control & ALTERA_AVALON_JTAG_UART_CONTROL_WSPACE_MSK) >> ALTERA_AVALON_JTAG_UART_CONTROL_WSPACE_OFST; + 1015a60: e0bffa17 ldw r2,-24(fp) + 1015a64: 10bfffec andhi r2,r2,65535 + 1015a68: 1004d43a srli r2,r2,16 + 1015a6c: e0bff715 stw r2,-36(fp) + + while (space > 0 && sp->tx_out != sp->tx_in) + 1015a70: 00002706 br 1015b10 + { + IOWR_ALTERA_AVALON_JTAG_UART_DATA(base, sp->tx_buf[sp->tx_out]); + 1015a74: e13ffb17 ldw r4,-20(fp) + 1015a78: e0bffc17 ldw r2,-16(fp) + 1015a7c: 10c01017 ldw r3,64(r2) + 1015a80: e0bffc17 ldw r2,-16(fp) + 1015a84: 1885883a add r2,r3,r2 + 1015a88: 10821104 addi r2,r2,2116 + 1015a8c: 10800003 ldbu r2,0(r2) + 1015a90: 10c03fcc andi r3,r2,255 + 1015a94: 18c0201c xori r3,r3,128 + 1015a98: 18ffe004 addi r3,r3,-128 + 1015a9c: 2005883a mov r2,r4 + 1015aa0: 10c00035 stwio r3,0(r2) + + sp->tx_out = (sp->tx_out + 1) % ALTERA_AVALON_JTAG_UART_BUF_LEN; + 1015aa4: e0bffc17 ldw r2,-16(fp) + 1015aa8: 10801017 ldw r2,64(r2) + 1015aac: 10800044 addi r2,r2,1 + 1015ab0: 10c1ffcc andi r3,r2,2047 + 1015ab4: e0bffc17 ldw r2,-16(fp) + 1015ab8: 10c01015 stw r3,64(r2) + + /* Post an event to notify jtag_uart_write that a character has been written */ + ALT_FLAG_POST (sp->events, ALT_JTAG_UART_WRITE_RDY, OS_FLAG_SET); + 1015abc: e0bffc17 ldw r2,-16(fp) + 1015ac0: 10800c17 ldw r2,48(r2) + 1015ac4: e0bff315 stw r2,-52(fp) + 1015ac8: 00800084 movi r2,2 + 1015acc: e0bff40d sth r2,-48(fp) + 1015ad0: 00800044 movi r2,1 + 1015ad4: e0bff485 stb r2,-46(fp) + OS_FLAGS flags, + INT8U opt) +{ + INT8U err; + + if (OSRunning) + 1015ad8: 008040b4 movhi r2,258 + 1015adc: 10b31044 addi r2,r2,-13247 + 1015ae0: 10800003 ldbu r2,0(r2) + 1015ae4: 10803fcc andi r2,r2,255 + 1015ae8: 1005003a cmpeq r2,r2,zero + 1015aec: 1000051e bne r2,zero,1015b04 + { + OSFlagPost (group, flags, opt, &err); + 1015af0: e17ff40b ldhu r5,-48(fp) + 1015af4: e1bff483 ldbu r6,-46(fp) + 1015af8: e1fffd44 addi r7,fp,-11 + 1015afc: e13ff317 ldw r4,-52(fp) + 1015b00: 10105880 call 1010588 + + space--; + 1015b04: e0bff717 ldw r2,-36(fp) + 1015b08: 10bfffc4 addi r2,r2,-1 + 1015b0c: e0bff715 stw r2,-36(fp) + if (control & ALTERA_AVALON_JTAG_UART_CONTROL_WI_MSK) + { + /* process a write irq */ + unsigned int space = (control & ALTERA_AVALON_JTAG_UART_CONTROL_WSPACE_MSK) >> ALTERA_AVALON_JTAG_UART_CONTROL_WSPACE_OFST; + + while (space > 0 && sp->tx_out != sp->tx_in) + 1015b10: e0bff717 ldw r2,-36(fp) + 1015b14: 1005003a cmpeq r2,r2,zero + 1015b18: 1000051e bne r2,zero,1015b30 + 1015b1c: e0bffc17 ldw r2,-16(fp) + 1015b20: 10c01017 ldw r3,64(r2) + 1015b24: e0bffc17 ldw r2,-16(fp) + 1015b28: 10800f17 ldw r2,60(r2) + 1015b2c: 18bfd11e bne r3,r2,1015a74 + ALT_FLAG_POST (sp->events, ALT_JTAG_UART_WRITE_RDY, OS_FLAG_SET); + + space--; + } + + if (space > 0) + 1015b30: e0bff717 ldw r2,-36(fp) + 1015b34: 1005003a cmpeq r2,r2,zero + 1015b38: 103f711e bne r2,zero,1015900 + { + /* If we don't have any more data available then turn off the TX interrupt */ + sp->irq_enable &= ~ALTERA_AVALON_JTAG_UART_CONTROL_WE_MSK; + 1015b3c: e0bffc17 ldw r2,-16(fp) + 1015b40: 10c00817 ldw r3,32(r2) + 1015b44: 00bfff44 movi r2,-3 + 1015b48: 1886703a and r3,r3,r2 + 1015b4c: e0bffc17 ldw r2,-16(fp) + 1015b50: 10c00815 stw r3,32(r2) + IOWR_ALTERA_AVALON_JTAG_UART_CONTROL(sp->base, sp->irq_enable); + 1015b54: e0bffc17 ldw r2,-16(fp) + 1015b58: 10800017 ldw r2,0(r2) + 1015b5c: 11000104 addi r4,r2,4 + 1015b60: e0bffc17 ldw r2,-16(fp) + 1015b64: 10800817 ldw r2,32(r2) + 1015b68: 1007883a mov r3,r2 + 1015b6c: 2005883a mov r2,r4 + 1015b70: 10c00035 stwio r3,0(r2) + + /* Dummy read to ensure IRQ is cleared prior to ISR completion */ + IORD_ALTERA_AVALON_JTAG_UART_CONTROL(base); + 1015b74: e0bffb17 ldw r2,-20(fp) + 1015b78: 10800104 addi r2,r2,4 + 1015b7c: 10800037 ldwio r2,0(r2) + } + } + } + 1015b80: 003f5f06 br 1015900 +} + 1015b84: e037883a mov sp,fp + 1015b88: dfc00117 ldw ra,4(sp) + 1015b8c: df000017 ldw fp,0(sp) + 1015b90: dec00204 addi sp,sp,8 + 1015b94: f800283a ret + +01015b98 : + * Timeout routine is called every second + */ + +static alt_u32 +altera_avalon_jtag_uart_timeout(void* context) +{ + 1015b98: defff804 addi sp,sp,-32 + 1015b9c: dfc00715 stw ra,28(sp) + 1015ba0: df000615 stw fp,24(sp) + 1015ba4: df000604 addi fp,sp,24 + 1015ba8: e13fff15 stw r4,-4(fp) + altera_avalon_jtag_uart_state* sp = (altera_avalon_jtag_uart_state *) context; + 1015bac: e0bfff17 ldw r2,-4(fp) + 1015bb0: e0bffd15 stw r2,-12(fp) + + unsigned int control = IORD_ALTERA_AVALON_JTAG_UART_CONTROL(sp->base); + 1015bb4: e0bffd17 ldw r2,-12(fp) + 1015bb8: 10800017 ldw r2,0(r2) + 1015bbc: 10800104 addi r2,r2,4 + 1015bc0: 10800037 ldwio r2,0(r2) + 1015bc4: e0bffc15 stw r2,-16(fp) + + if (control & ALTERA_AVALON_JTAG_UART_CONTROL_AC_MSK) + 1015bc8: e0bffc17 ldw r2,-16(fp) + 1015bcc: 1081000c andi r2,r2,1024 + 1015bd0: 1005003a cmpeq r2,r2,zero + 1015bd4: 10000c1e bne r2,zero,1015c08 + { + IOWR_ALTERA_AVALON_JTAG_UART_CONTROL(sp->base, sp->irq_enable | ALTERA_AVALON_JTAG_UART_CONTROL_AC_MSK); + 1015bd8: e0bffd17 ldw r2,-12(fp) + 1015bdc: 10800017 ldw r2,0(r2) + 1015be0: 11000104 addi r4,r2,4 + 1015be4: e0bffd17 ldw r2,-12(fp) + 1015be8: 10800817 ldw r2,32(r2) + 1015bec: 10810014 ori r2,r2,1024 + 1015bf0: 1007883a mov r3,r2 + 1015bf4: 2005883a mov r2,r4 + 1015bf8: 10c00035 stwio r3,0(r2) + sp->host_inactive = 0; + 1015bfc: e0bffd17 ldw r2,-12(fp) + 1015c00: 10000915 stw zero,36(r2) + 1015c04: 00002106 br 1015c8c + } + else if (sp->host_inactive < INT_MAX - 2) { + 1015c08: e0bffd17 ldw r2,-12(fp) + 1015c0c: 10c00917 ldw r3,36(r2) + 1015c10: 00a00034 movhi r2,32768 + 1015c14: 10bfff04 addi r2,r2,-4 + 1015c18: 10c01c36 bltu r2,r3,1015c8c + sp->host_inactive++; + 1015c1c: e0bffd17 ldw r2,-12(fp) + 1015c20: 10800917 ldw r2,36(r2) + 1015c24: 10c00044 addi r3,r2,1 + 1015c28: e0bffd17 ldw r2,-12(fp) + 1015c2c: 10c00915 stw r3,36(r2) + + if (sp->host_inactive >= sp->timeout) { + 1015c30: e0bffd17 ldw r2,-12(fp) + 1015c34: 10c00917 ldw r3,36(r2) + 1015c38: e0bffd17 ldw r2,-12(fp) + 1015c3c: 10800117 ldw r2,4(r2) + 1015c40: 18801236 bltu r3,r2,1015c8c + /* Post an event to indicate host is inactive (for jtag_uart_read */ + ALT_FLAG_POST (sp->events, ALT_JTAG_UART_TIMEOUT, OS_FLAG_SET); + 1015c44: e0bffd17 ldw r2,-12(fp) + 1015c48: 10800c17 ldw r2,48(r2) + 1015c4c: e0bffa15 stw r2,-24(fp) + 1015c50: 00800104 movi r2,4 + 1015c54: e0bffb0d sth r2,-20(fp) + 1015c58: 00800044 movi r2,1 + 1015c5c: e0bffb85 stb r2,-18(fp) + OS_FLAGS flags, + INT8U opt) +{ + INT8U err; + + if (OSRunning) + 1015c60: 008040b4 movhi r2,258 + 1015c64: 10b31044 addi r2,r2,-13247 + 1015c68: 10800003 ldbu r2,0(r2) + 1015c6c: 10803fcc andi r2,r2,255 + 1015c70: 1005003a cmpeq r2,r2,zero + 1015c74: 1000051e bne r2,zero,1015c8c + { + OSFlagPost (group, flags, opt, &err); + 1015c78: e17ffb0b ldhu r5,-20(fp) + 1015c7c: e1bffb83 ldbu r6,-18(fp) + 1015c80: e1fffe04 addi r7,fp,-8 + 1015c84: e13ffa17 ldw r4,-24(fp) + 1015c88: 10105880 call 1010588 + 1015c8c: 008040b4 movhi r2,258 + 1015c90: 10b32504 addi r2,r2,-13164 + 1015c94: 10800017 ldw r2,0(r2) + } + } + + return alt_ticks_per_second(); +} + 1015c98: e037883a mov sp,fp + 1015c9c: dfc00117 ldw ra,4(sp) + 1015ca0: df000017 ldw fp,0(sp) + 1015ca4: dec00204 addi sp,sp,8 + 1015ca8: f800283a ret + +01015cac : + * The close routine is not implemented for the small driver; instead it will + * map to null. This is because the small driver simply waits while characters + * are transmitted; there is no interrupt-serviced buffer to empty + */ +int altera_avalon_jtag_uart_close(altera_avalon_jtag_uart_state* sp, int flags) +{ + 1015cac: defffc04 addi sp,sp,-16 + 1015cb0: df000315 stw fp,12(sp) + 1015cb4: df000304 addi fp,sp,12 + 1015cb8: e13ffd15 stw r4,-12(fp) + 1015cbc: e17ffe15 stw r5,-8(fp) + /* + * Wait for all transmit data to be emptied by the JTAG UART ISR, or + * for a host-inactivity timeout, in which case transmit data will be lost + */ + while ( (sp->tx_out != sp->tx_in) && (sp->host_inactive < sp->timeout) ) { + 1015cc0: 00000706 br 1015ce0 + if (flags & O_NONBLOCK) { + 1015cc4: e0bffe17 ldw r2,-8(fp) + 1015cc8: 1090000c andi r2,r2,16384 + 1015ccc: 1005003a cmpeq r2,r2,zero + 1015cd0: 1000031e bne r2,zero,1015ce0 + return -EWOULDBLOCK; + 1015cd4: 00bffd44 movi r2,-11 + 1015cd8: e0bfff15 stw r2,-4(fp) + 1015cdc: 00000b06 br 1015d0c +{ + /* + * Wait for all transmit data to be emptied by the JTAG UART ISR, or + * for a host-inactivity timeout, in which case transmit data will be lost + */ + while ( (sp->tx_out != sp->tx_in) && (sp->host_inactive < sp->timeout) ) { + 1015ce0: e0bffd17 ldw r2,-12(fp) + 1015ce4: 10c01017 ldw r3,64(r2) + 1015ce8: e0bffd17 ldw r2,-12(fp) + 1015cec: 10800f17 ldw r2,60(r2) + 1015cf0: 18800526 beq r3,r2,1015d08 + 1015cf4: e0bffd17 ldw r2,-12(fp) + 1015cf8: 10c00917 ldw r3,36(r2) + 1015cfc: e0bffd17 ldw r2,-12(fp) + 1015d00: 10800117 ldw r2,4(r2) + 1015d04: 18bfef36 bltu r3,r2,1015cc4 + if (flags & O_NONBLOCK) { + return -EWOULDBLOCK; + } + } + + return 0; + 1015d08: e03fff15 stw zero,-4(fp) + 1015d0c: e0bfff17 ldw r2,-4(fp) +} + 1015d10: e037883a mov sp,fp + 1015d14: df000017 ldw fp,0(sp) + 1015d18: dec00104 addi sp,sp,4 + 1015d1c: f800283a ret + +01015d20 : +/* ----------------------------------------------------------- */ + +int +altera_avalon_jtag_uart_ioctl(altera_avalon_jtag_uart_state* sp, int req, + void* arg) +{ + 1015d20: defff804 addi sp,sp,-32 + 1015d24: df000715 stw fp,28(sp) + 1015d28: df000704 addi fp,sp,28 + 1015d2c: e13ffb15 stw r4,-20(fp) + 1015d30: e17ffc15 stw r5,-16(fp) + 1015d34: e1bffd15 stw r6,-12(fp) + int rc = -ENOTTY; + 1015d38: 00bff9c4 movi r2,-25 + 1015d3c: e0bffa15 stw r2,-24(fp) + + switch (req) + 1015d40: e0bffc17 ldw r2,-16(fp) + 1015d44: e0bfff15 stw r2,-4(fp) + 1015d48: e0ffff17 ldw r3,-4(fp) + 1015d4c: 189a8060 cmpeqi r2,r3,27137 + 1015d50: 1000041e bne r2,zero,1015d64 + 1015d54: e0ffff17 ldw r3,-4(fp) + 1015d58: 189a80a0 cmpeqi r2,r3,27138 + 1015d5c: 10001b1e bne r2,zero,1015dcc + 1015d60: 00002706 br 1015e00 + { + case TIOCSTIMEOUT: + /* Set the time to wait until assuming host is not connected */ + if (sp->timeout != INT_MAX) + 1015d64: e0bffb17 ldw r2,-20(fp) + 1015d68: 10c00117 ldw r3,4(r2) + 1015d6c: 00a00034 movhi r2,32768 + 1015d70: 10bfffc4 addi r2,r2,-1 + 1015d74: 18802226 beq r3,r2,1015e00 + { + int timeout = *((int *)arg); + 1015d78: e0bffd17 ldw r2,-12(fp) + 1015d7c: 10800017 ldw r2,0(r2) + 1015d80: e0bff915 stw r2,-28(fp) + sp->timeout = (timeout >= 2 && timeout < INT_MAX) ? timeout : INT_MAX - 1; + 1015d84: e0bff917 ldw r2,-28(fp) + 1015d88: 10800090 cmplti r2,r2,2 + 1015d8c: 1000071e bne r2,zero,1015dac + 1015d90: e0fff917 ldw r3,-28(fp) + 1015d94: 00a00034 movhi r2,32768 + 1015d98: 10bfffc4 addi r2,r2,-1 + 1015d9c: 18800326 beq r3,r2,1015dac + 1015da0: e0bff917 ldw r2,-28(fp) + 1015da4: e0bffe15 stw r2,-8(fp) + 1015da8: 00000306 br 1015db8 + 1015dac: 00e00034 movhi r3,32768 + 1015db0: 18ffff84 addi r3,r3,-2 + 1015db4: e0fffe15 stw r3,-8(fp) + 1015db8: e0bffb17 ldw r2,-20(fp) + 1015dbc: e0fffe17 ldw r3,-8(fp) + 1015dc0: 10c00115 stw r3,4(r2) + rc = 0; + 1015dc4: e03ffa15 stw zero,-24(fp) + } + break; + 1015dc8: 00000d06 br 1015e00 + + case TIOCGCONNECTED: + /* Find out whether host is connected */ + if (sp->timeout != INT_MAX) + 1015dcc: e0bffb17 ldw r2,-20(fp) + 1015dd0: 10c00117 ldw r3,4(r2) + 1015dd4: 00a00034 movhi r2,32768 + 1015dd8: 10bfffc4 addi r2,r2,-1 + 1015ddc: 18800826 beq r3,r2,1015e00 + { + *((int *)arg) = (sp->host_inactive < sp->timeout) ? 1 : 0; + 1015de0: e13ffd17 ldw r4,-12(fp) + 1015de4: e0bffb17 ldw r2,-20(fp) + 1015de8: 10c00917 ldw r3,36(r2) + 1015dec: e0bffb17 ldw r2,-20(fp) + 1015df0: 10800117 ldw r2,4(r2) + 1015df4: 1885803a cmpltu r2,r3,r2 + 1015df8: 20800015 stw r2,0(r4) + rc = 0; + 1015dfc: e03ffa15 stw zero,-24(fp) + + default: + break; + } + + return rc; + 1015e00: e0bffa17 ldw r2,-24(fp) +} + 1015e04: e037883a mov sp,fp + 1015e08: df000017 ldw fp,0(sp) + 1015e0c: dec00104 addi sp,sp,4 + 1015e10: f800283a ret + +01015e14 : +/* ----------------------------------------------------------- */ + +int +altera_avalon_jtag_uart_read(altera_avalon_jtag_uart_state* sp, + char * buffer, int space, int flags) +{ + 1015e14: deffeb04 addi sp,sp,-84 + 1015e18: dfc01415 stw ra,80(sp) + 1015e1c: df001315 stw fp,76(sp) + 1015e20: df001304 addi fp,sp,76 + 1015e24: e13ffb15 stw r4,-20(fp) + 1015e28: e17ffc15 stw r5,-16(fp) + 1015e2c: e1bffd15 stw r6,-12(fp) + 1015e30: e1fffe15 stw r7,-8(fp) + char * ptr = buffer; + 1015e34: e0bffc17 ldw r2,-16(fp) + 1015e38: e0bff915 stw r2,-28(fp) + + /* + * When running in a multi threaded environment, obtain the "read_lock" + * semaphore. This ensures that reading from the device is thread-safe. + */ + ALT_SEM_PEND (sp->read_lock, 0); + 1015e3c: e0bffb17 ldw r2,-20(fp) + 1015e40: 10800a17 ldw r2,40(r2) + 1015e44: e0bff315 stw r2,-52(fp) + 1015e48: e03ff40d sth zero,-48(fp) + +static ALT_INLINE int ALT_ALWAYS_INLINE alt_sem_pend (OS_EVENT* sem, + INT16U timeout) +{ + INT8U err; + OSSemPend (sem, timeout, &err); + 1015e4c: e17ff40b ldhu r5,-48(fp) + 1015e50: e1bffa44 addi r6,fp,-23 + 1015e54: e13ff317 ldw r4,-52(fp) + 1015e58: 1012e180 call 1012e18 + + while (space > 0) + 1015e5c: 00006406 br 1015ff0 + unsigned int in, out; + + /* Read as much data as possible */ + do + { + in = sp->rx_in; + 1015e60: e0bffb17 ldw r2,-20(fp) + 1015e64: 10800d17 ldw r2,52(r2) + 1015e68: e0bff615 stw r2,-40(fp) + out = sp->rx_out; + 1015e6c: e0bffb17 ldw r2,-20(fp) + 1015e70: 10800e17 ldw r2,56(r2) + 1015e74: e0bff515 stw r2,-44(fp) + + if (in >= out) + 1015e78: e0fff617 ldw r3,-40(fp) + 1015e7c: e0bff517 ldw r2,-44(fp) + 1015e80: 18800536 bltu r3,r2,1015e98 + n = in - out; + 1015e84: e0bff617 ldw r2,-40(fp) + 1015e88: e0fff517 ldw r3,-44(fp) + 1015e8c: 10c5c83a sub r2,r2,r3 + 1015e90: e0bff715 stw r2,-36(fp) + 1015e94: 00000406 br 1015ea8 + else + n = ALTERA_AVALON_JTAG_UART_BUF_LEN - out; + 1015e98: 00820004 movi r2,2048 + 1015e9c: e0fff517 ldw r3,-44(fp) + 1015ea0: 10c5c83a sub r2,r2,r3 + 1015ea4: e0bff715 stw r2,-36(fp) + + if (n == 0) + 1015ea8: e0bff717 ldw r2,-36(fp) + 1015eac: 1005003a cmpeq r2,r2,zero + 1015eb0: 10001f1e bne r2,zero,1015f30 + break; /* No more data available */ + + if (n > space) + 1015eb4: e0fffd17 ldw r3,-12(fp) + 1015eb8: e0bff717 ldw r2,-36(fp) + 1015ebc: 1880022e bgeu r3,r2,1015ec8 + n = space; + 1015ec0: e0bffd17 ldw r2,-12(fp) + 1015ec4: e0bff715 stw r2,-36(fp) + + memcpy(ptr, sp->rx_buf + out, n); + 1015ec8: e0bffb17 ldw r2,-20(fp) + 1015ecc: 10c01104 addi r3,r2,68 + 1015ed0: e0bff517 ldw r2,-44(fp) + 1015ed4: 1887883a add r3,r3,r2 + 1015ed8: e0bff917 ldw r2,-28(fp) + 1015edc: 1009883a mov r4,r2 + 1015ee0: 180b883a mov r5,r3 + 1015ee4: e1bff717 ldw r6,-36(fp) + 1015ee8: 1007fcc0 call 1007fcc + ptr += n; + 1015eec: e0fff717 ldw r3,-36(fp) + 1015ef0: e0bff917 ldw r2,-28(fp) + 1015ef4: 10c5883a add r2,r2,r3 + 1015ef8: e0bff915 stw r2,-28(fp) + space -= n; + 1015efc: e0fffd17 ldw r3,-12(fp) + 1015f00: e0bff717 ldw r2,-36(fp) + 1015f04: 1885c83a sub r2,r3,r2 + 1015f08: e0bffd15 stw r2,-12(fp) + + sp->rx_out = (out + n) % ALTERA_AVALON_JTAG_UART_BUF_LEN; + 1015f0c: e0fff517 ldw r3,-44(fp) + 1015f10: e0bff717 ldw r2,-36(fp) + 1015f14: 1885883a add r2,r3,r2 + 1015f18: 10c1ffcc andi r3,r2,2047 + 1015f1c: e0bffb17 ldw r2,-20(fp) + 1015f20: 10c00e15 stw r3,56(r2) + } + while (space > 0); + 1015f24: e0bffd17 ldw r2,-12(fp) + 1015f28: 10800048 cmpgei r2,r2,1 + 1015f2c: 103fcc1e bne r2,zero,1015e60 + + /* If we read any data then return it */ + if (ptr != buffer) + 1015f30: e0fff917 ldw r3,-28(fp) + 1015f34: e0bffc17 ldw r2,-16(fp) + 1015f38: 1880301e bne r3,r2,1015ffc + break; + + /* If in non-blocking mode then return error */ + if (flags & O_NONBLOCK) + 1015f3c: e0bffe17 ldw r2,-8(fp) + 1015f40: 1090000c andi r2,r2,16384 + 1015f44: 1004c03a cmpne r2,r2,zero + 1015f48: 10002c1e bne r2,zero,1015ffc + break; + +#ifdef __ucosii__ + /* OS Present: Pend on a flag if the OS is running, otherwise spin */ + if(OSRunning == OS_TRUE) { + 1015f4c: 008040b4 movhi r2,258 + 1015f50: 10b31044 addi r2,r2,-13247 + 1015f54: 10800003 ldbu r2,0(r2) + 1015f58: 10803fcc andi r2,r2,255 + 1015f5c: 10800058 cmpnei r2,r2,1 + 1015f60: 1000161e bne r2,zero,1015fbc + * When running in a multi-threaded mode, we pend on the read event + * flag set and timeout event flag set in the isr. This avoids wasting CPU + * cycles waiting in this thread, when we could be doing something more + * profitable elsewhere. + */ + ALT_FLAG_PEND (sp->events, + 1015f64: e0bffb17 ldw r2,-20(fp) + 1015f68: 10800c17 ldw r2,48(r2) + 1015f6c: e0bff015 stw r2,-64(fp) + 1015f70: 00800144 movi r2,5 + 1015f74: e0bff10d sth r2,-60(fp) + 1015f78: 00bfe0c4 movi r2,-125 + 1015f7c: e0bff185 stb r2,-58(fp) + 1015f80: e03ff20d sth zero,-56(fp) + OS_FLAGS flags, + INT8U wait_type, + INT16U timeout) +{ + INT8U err; + if (OSRunning) + 1015f84: 008040b4 movhi r2,258 + 1015f88: 10b31044 addi r2,r2,-13247 + 1015f8c: 10800003 ldbu r2,0(r2) + 1015f90: 10803fcc andi r2,r2,255 + 1015f94: 1005003a cmpeq r2,r2,zero + 1015f98: 1000111e bne r2,zero,1015fe0 + { + OSFlagPend (group, flags, wait_type, timeout, &err); + 1015f9c: e17ff10b ldhu r5,-60(fp) + 1015fa0: e1bff183 ldbu r6,-58(fp) + 1015fa4: e1fff20b ldhu r7,-56(fp) + 1015fa8: e0bffa04 addi r2,fp,-24 + 1015fac: d8800015 stw r2,0(sp) + 1015fb0: e13ff017 ldw r4,-64(fp) + 1015fb4: 100fedc0 call 100fedc + return err; + 1015fb8: 00000906 br 1015fe0 + OS_FLAG_WAIT_SET_ANY + OS_FLAG_CONSUME, + 0); + } + else { + /* Spin until more data arrives or until host disconnects */ + while (in == sp->rx_in && sp->host_inactive < sp->timeout) + 1015fbc: e0bffb17 ldw r2,-20(fp) + 1015fc0: 10c00d17 ldw r3,52(r2) + 1015fc4: e0bff617 ldw r2,-40(fp) + 1015fc8: 1880051e bne r3,r2,1015fe0 + 1015fcc: e0bffb17 ldw r2,-20(fp) + 1015fd0: 10c00917 ldw r3,36(r2) + 1015fd4: e0bffb17 ldw r2,-20(fp) + 1015fd8: 10800117 ldw r2,4(r2) + 1015fdc: 18bff736 bltu r3,r2,1015fbc + /* No OS: Always spin */ + while (in == sp->rx_in && sp->host_inactive < sp->timeout) + ; +#endif /* __ucosii__ */ + + if (in == sp->rx_in) + 1015fe0: e0bffb17 ldw r2,-20(fp) + 1015fe4: 10c00d17 ldw r3,52(r2) + 1015fe8: e0bff617 ldw r2,-40(fp) + 1015fec: 18800326 beq r3,r2,1015ffc + * When running in a multi threaded environment, obtain the "read_lock" + * semaphore. This ensures that reading from the device is thread-safe. + */ + ALT_SEM_PEND (sp->read_lock, 0); + + while (space > 0) + 1015ff0: e0bffd17 ldw r2,-12(fp) + 1015ff4: 10800048 cmpgei r2,r2,1 + 1015ff8: 103f991e bne r2,zero,1015e60 + /* + * Now that access to the circular buffer is complete, release the read + * semaphore so that other threads can access the buffer. + */ + + ALT_SEM_POST (sp->read_lock); + 1015ffc: e0bffb17 ldw r2,-20(fp) + 1016000: 11000a17 ldw r4,40(r2) + 1016004: 10132100 call 1013210 + + if (ptr != buffer) + 1016008: e0fff917 ldw r3,-28(fp) + 101600c: e0bffc17 ldw r2,-16(fp) + 1016010: 18801926 beq r3,r2,1016078 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1016014: 0005303a rdctl r2,status + 1016018: e0bfef15 stw r2,-68(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 101601c: e0ffef17 ldw r3,-68(fp) + 1016020: 00bfff84 movi r2,-2 + 1016024: 1884703a and r2,r3,r2 + 1016028: 1001703a wrctl status,r2 + + return context; + 101602c: e0bfef17 ldw r2,-68(fp) + { + /* If we read any data then there is space in the buffer so enable interrupts */ + context = alt_irq_disable_all(); + 1016030: e0bff815 stw r2,-32(fp) + sp->irq_enable |= ALTERA_AVALON_JTAG_UART_CONTROL_RE_MSK; + 1016034: e0bffb17 ldw r2,-20(fp) + 1016038: 10800817 ldw r2,32(r2) + 101603c: 10c00054 ori r3,r2,1 + 1016040: e0bffb17 ldw r2,-20(fp) + 1016044: 10c00815 stw r3,32(r2) + IOWR_ALTERA_AVALON_JTAG_UART_CONTROL(sp->base, sp->irq_enable); + 1016048: e0bffb17 ldw r2,-20(fp) + 101604c: 10800017 ldw r2,0(r2) + 1016050: 11000104 addi r4,r2,4 + 1016054: e0bffb17 ldw r2,-20(fp) + 1016058: 10800817 ldw r2,32(r2) + 101605c: 1007883a mov r3,r2 + 1016060: 2005883a mov r2,r4 + 1016064: 10c00035 stwio r3,0(r2) + 1016068: e0bff817 ldw r2,-32(fp) + 101606c: e0bfee15 stw r2,-72(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1016070: e0bfee17 ldw r2,-72(fp) + 1016074: 1001703a wrctl status,r2 + alt_irq_enable_all(context); + } + + if (ptr != buffer) + 1016078: e0fff917 ldw r3,-28(fp) + 101607c: e0bffc17 ldw r2,-16(fp) + 1016080: 18800526 beq r3,r2,1016098 + return ptr - buffer; + 1016084: e0fff917 ldw r3,-28(fp) + 1016088: e0bffc17 ldw r2,-16(fp) + 101608c: 1887c83a sub r3,r3,r2 + 1016090: e0ffff15 stw r3,-4(fp) + 1016094: 00000906 br 10160bc + else if (flags & O_NONBLOCK) + 1016098: e0bffe17 ldw r2,-8(fp) + 101609c: 1090000c andi r2,r2,16384 + 10160a0: 1005003a cmpeq r2,r2,zero + 10160a4: 1000031e bne r2,zero,10160b4 + return -EWOULDBLOCK; + 10160a8: 00bffd44 movi r2,-11 + 10160ac: e0bfff15 stw r2,-4(fp) + 10160b0: 00000206 br 10160bc + else + return -EIO; + 10160b4: 00bffec4 movi r2,-5 + 10160b8: e0bfff15 stw r2,-4(fp) + 10160bc: e0bfff17 ldw r2,-4(fp) +} + 10160c0: e037883a mov sp,fp + 10160c4: dfc00117 ldw ra,4(sp) + 10160c8: df000017 ldw fp,0(sp) + 10160cc: dec00204 addi sp,sp,8 + 10160d0: f800283a ret + +010160d4 : +/* ----------------------------------------------------------- */ + +int +altera_avalon_jtag_uart_write(altera_avalon_jtag_uart_state* sp, + const char * ptr, int count, int flags) +{ + 10160d4: deffeb04 addi sp,sp,-84 + 10160d8: dfc01415 stw ra,80(sp) + 10160dc: df001315 stw fp,76(sp) + 10160e0: df001304 addi fp,sp,76 + 10160e4: e13ffb15 stw r4,-20(fp) + 10160e8: e17ffc15 stw r5,-16(fp) + 10160ec: e1bffd15 stw r6,-12(fp) + 10160f0: e1fffe15 stw r7,-8(fp) + /* Remove warning at optimisation level 03 by seting out to 0 */ + unsigned int in, out=0; + 10160f4: e03ff815 stw zero,-32(fp) + unsigned int n; + alt_irq_context context; + + const char * start = ptr; + 10160f8: e0bffc17 ldw r2,-16(fp) + 10160fc: e0bff515 stw r2,-44(fp) + + /* + * When running in a multi threaded environment, obtain the "write_lock" + * semaphore. This ensures that writing to the device is thread-safe. + */ + ALT_SEM_PEND (sp->write_lock, 0); + 1016100: e0bffb17 ldw r2,-20(fp) + 1016104: 10800b17 ldw r2,44(r2) + 1016108: e0bff315 stw r2,-52(fp) + 101610c: e03ff40d sth zero,-48(fp) + 1016110: e17ff40b ldhu r5,-48(fp) + 1016114: e1bffa04 addi r6,fp,-24 + 1016118: e13ff317 ldw r4,-52(fp) + 101611c: 1012e180 call 1012e18 + + do + { + /* Copy as much as we can into the transmit buffer */ + while (count > 0) + 1016120: 00003a06 br 101620c + { + /* We need a stable value of the out pointer to calculate the space available */ + in = sp->tx_in; + 1016124: e0bffb17 ldw r2,-20(fp) + 1016128: 10800f17 ldw r2,60(r2) + 101612c: e0bff915 stw r2,-28(fp) + out = sp->tx_out; + 1016130: e0bffb17 ldw r2,-20(fp) + 1016134: 10801017 ldw r2,64(r2) + 1016138: e0bff815 stw r2,-32(fp) + + if (in < out) + 101613c: e0fff917 ldw r3,-28(fp) + 1016140: e0bff817 ldw r2,-32(fp) + 1016144: 1880062e bgeu r3,r2,1016160 + n = out - 1 - in; + 1016148: e0fff817 ldw r3,-32(fp) + 101614c: e0bff917 ldw r2,-28(fp) + 1016150: 1885c83a sub r2,r3,r2 + 1016154: 10bfffc4 addi r2,r2,-1 + 1016158: e0bff715 stw r2,-36(fp) + 101615c: 00000c06 br 1016190 + else if (out > 0) + 1016160: e0bff817 ldw r2,-32(fp) + 1016164: 1005003a cmpeq r2,r2,zero + 1016168: 1000051e bne r2,zero,1016180 + n = ALTERA_AVALON_JTAG_UART_BUF_LEN - in; + 101616c: 00820004 movi r2,2048 + 1016170: e0fff917 ldw r3,-28(fp) + 1016174: 10c5c83a sub r2,r2,r3 + 1016178: e0bff715 stw r2,-36(fp) + 101617c: 00000406 br 1016190 + else + n = ALTERA_AVALON_JTAG_UART_BUF_LEN - 1 - in; + 1016180: 0081ffc4 movi r2,2047 + 1016184: e0fff917 ldw r3,-28(fp) + 1016188: 10c5c83a sub r2,r2,r3 + 101618c: e0bff715 stw r2,-36(fp) + + if (n == 0) + 1016190: e0bff717 ldw r2,-36(fp) + 1016194: 1005003a cmpeq r2,r2,zero + 1016198: 10001f1e bne r2,zero,1016218 + break; + + if (n > count) + 101619c: e0fffd17 ldw r3,-12(fp) + 10161a0: e0bff717 ldw r2,-36(fp) + 10161a4: 1880022e bgeu r3,r2,10161b0 + n = count; + 10161a8: e0bffd17 ldw r2,-12(fp) + 10161ac: e0bff715 stw r2,-36(fp) + + memcpy(sp->tx_buf + in, ptr, n); + 10161b0: e0bffb17 ldw r2,-20(fp) + 10161b4: 10c21104 addi r3,r2,2116 + 10161b8: e0bff917 ldw r2,-28(fp) + 10161bc: 1885883a add r2,r3,r2 + 10161c0: e0fffc17 ldw r3,-16(fp) + 10161c4: 1009883a mov r4,r2 + 10161c8: 180b883a mov r5,r3 + 10161cc: e1bff717 ldw r6,-36(fp) + 10161d0: 1007fcc0 call 1007fcc + ptr += n; + 10161d4: e0fff717 ldw r3,-36(fp) + 10161d8: e0bffc17 ldw r2,-16(fp) + 10161dc: 10c5883a add r2,r2,r3 + 10161e0: e0bffc15 stw r2,-16(fp) + count -= n; + 10161e4: e0fffd17 ldw r3,-12(fp) + 10161e8: e0bff717 ldw r2,-36(fp) + 10161ec: 1885c83a sub r2,r3,r2 + 10161f0: e0bffd15 stw r2,-12(fp) + + sp->tx_in = (in + n) % ALTERA_AVALON_JTAG_UART_BUF_LEN; + 10161f4: e0fff917 ldw r3,-28(fp) + 10161f8: e0bff717 ldw r2,-36(fp) + 10161fc: 1885883a add r2,r3,r2 + 1016200: 10c1ffcc andi r3,r2,2047 + 1016204: e0bffb17 ldw r2,-20(fp) + 1016208: 10c00f15 stw r3,60(r2) + ALT_SEM_PEND (sp->write_lock, 0); + + do + { + /* Copy as much as we can into the transmit buffer */ + while (count > 0) + 101620c: e0bffd17 ldw r2,-12(fp) + 1016210: 10800048 cmpgei r2,r2,1 + 1016214: 103fc31e bne r2,zero,1016124 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1016218: 0005303a rdctl r2,status + 101621c: e0bff215 stw r2,-56(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1016220: e0fff217 ldw r3,-56(fp) + 1016224: 00bfff84 movi r2,-2 + 1016228: 1884703a and r2,r3,r2 + 101622c: 1001703a wrctl status,r2 + + return context; + 1016230: e0bff217 ldw r2,-56(fp) + * to enable interrupts if there is no space left in the FIFO + * + * For now kick the interrupt routine every time to make it transmit + * the data + */ + context = alt_irq_disable_all(); + 1016234: e0bff615 stw r2,-40(fp) + sp->irq_enable |= ALTERA_AVALON_JTAG_UART_CONTROL_WE_MSK; + 1016238: e0bffb17 ldw r2,-20(fp) + 101623c: 10800817 ldw r2,32(r2) + 1016240: 10c00094 ori r3,r2,2 + 1016244: e0bffb17 ldw r2,-20(fp) + 1016248: 10c00815 stw r3,32(r2) + IOWR_ALTERA_AVALON_JTAG_UART_CONTROL(sp->base, sp->irq_enable); + 101624c: e0bffb17 ldw r2,-20(fp) + 1016250: 10800017 ldw r2,0(r2) + 1016254: 11000104 addi r4,r2,4 + 1016258: e0bffb17 ldw r2,-20(fp) + 101625c: 10800817 ldw r2,32(r2) + 1016260: 1007883a mov r3,r2 + 1016264: 2005883a mov r2,r4 + 1016268: 10c00035 stwio r3,0(r2) + 101626c: e0bff617 ldw r2,-40(fp) + 1016270: e0bff115 stw r2,-60(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1016274: e0bff117 ldw r2,-60(fp) + 1016278: 1001703a wrctl status,r2 + /* + * If there is any data left then either return now or block until + * some has been sent + */ + /* consider: test whether there is anything there while doing this and delay for at most 2s. */ + if (count > 0) + 101627c: e0bffd17 ldw r2,-12(fp) + 1016280: 10800050 cmplti r2,r2,1 + 1016284: 10002d1e bne r2,zero,101633c + { + if (flags & O_NONBLOCK) + 1016288: e0bffe17 ldw r2,-8(fp) + 101628c: 1090000c andi r2,r2,16384 + 1016290: 1004c03a cmpne r2,r2,zero + 1016294: 10002c1e bne r2,zero,1016348 + break; + +#ifdef __ucosii__ + /* OS Present: Pend on a flag if the OS is running, otherwise spin */ + if(OSRunning == OS_TRUE) { + 1016298: 008040b4 movhi r2,258 + 101629c: 10b31044 addi r2,r2,-13247 + 10162a0: 10800003 ldbu r2,0(r2) + 10162a4: 10803fcc andi r2,r2,255 + 10162a8: 10800058 cmpnei r2,r2,1 + 10162ac: 1000161e bne r2,zero,1016308 + * When running in a multi-threaded mode, we pend on the write event + * flag set or the timeout flag in the isr. This avoids wasting CPU + * cycles waiting in this thread, when we could be doing something + * more profitable elsewhere. + */ + ALT_FLAG_PEND (sp->events, + 10162b0: e0bffb17 ldw r2,-20(fp) + 10162b4: 10800c17 ldw r2,48(r2) + 10162b8: e0bfee15 stw r2,-72(fp) + 10162bc: 00800184 movi r2,6 + 10162c0: e0bfef0d sth r2,-68(fp) + 10162c4: 00bfe0c4 movi r2,-125 + 10162c8: e0bfef85 stb r2,-66(fp) + 10162cc: e03ff00d sth zero,-64(fp) + OS_FLAGS flags, + INT8U wait_type, + INT16U timeout) +{ + INT8U err; + if (OSRunning) + 10162d0: 008040b4 movhi r2,258 + 10162d4: 10b31044 addi r2,r2,-13247 + 10162d8: 10800003 ldbu r2,0(r2) + 10162dc: 10803fcc andi r2,r2,255 + 10162e0: 1005003a cmpeq r2,r2,zero + 10162e4: 1000111e bne r2,zero,101632c + { + OSFlagPend (group, flags, wait_type, timeout, &err); + 10162e8: e17fef0b ldhu r5,-68(fp) + 10162ec: e1bfef83 ldbu r6,-66(fp) + 10162f0: e1fff00b ldhu r7,-64(fp) + 10162f4: e0bffa44 addi r2,fp,-23 + 10162f8: d8800015 stw r2,0(sp) + 10162fc: e13fee17 ldw r4,-72(fp) + 1016300: 100fedc0 call 100fedc + return err; + 1016304: 00000906 br 101632c + /* + * OS not running: Wait for data to be removed from buffer. + * Once the interrupt routine has removed some data then we + * will be able to insert some more. + */ + while (out == sp->tx_out && sp->host_inactive < sp->timeout) + 1016308: e0bffb17 ldw r2,-20(fp) + 101630c: 10c01017 ldw r3,64(r2) + 1016310: e0bff817 ldw r2,-32(fp) + 1016314: 1880051e bne r3,r2,101632c + 1016318: e0bffb17 ldw r2,-20(fp) + 101631c: 10c00917 ldw r3,36(r2) + 1016320: e0bffb17 ldw r2,-20(fp) + 1016324: 10800117 ldw r2,4(r2) + 1016328: 18bff736 bltu r3,r2,1016308 + */ + while (out == sp->tx_out && sp->host_inactive < sp->timeout) + ; +#endif /* __ucosii__ */ + + if (out == sp->tx_out) + 101632c: e0bffb17 ldw r2,-20(fp) + 1016330: 10c01017 ldw r3,64(r2) + 1016334: e0bff817 ldw r2,-32(fp) + 1016338: 18800326 beq r3,r2,1016348 + break; + } + } + while (count > 0); + 101633c: e0bffd17 ldw r2,-12(fp) + 1016340: 10800048 cmpgei r2,r2,1 + 1016344: 103fb11e bne r2,zero,101620c + + /* + * Now that access to the circular buffer is complete, release the write + * semaphore so that other threads can access the buffer. + */ + ALT_SEM_POST (sp->write_lock); + 1016348: e0bffb17 ldw r2,-20(fp) + 101634c: 11000b17 ldw r4,44(r2) + 1016350: 10132100 call 1013210 + + if (ptr != start) + 1016354: e0fffc17 ldw r3,-16(fp) + 1016358: e0bff517 ldw r2,-44(fp) + 101635c: 18800526 beq r3,r2,1016374 + return ptr - start; + 1016360: e0fffc17 ldw r3,-16(fp) + 1016364: e0bff517 ldw r2,-44(fp) + 1016368: 1887c83a sub r3,r3,r2 + 101636c: e0ffff15 stw r3,-4(fp) + 1016370: 00000906 br 1016398 + else if (flags & O_NONBLOCK) + 1016374: e0bffe17 ldw r2,-8(fp) + 1016378: 1090000c andi r2,r2,16384 + 101637c: 1005003a cmpeq r2,r2,zero + 1016380: 1000031e bne r2,zero,1016390 + return -EWOULDBLOCK; + 1016384: 00bffd44 movi r2,-11 + 1016388: e0bfff15 stw r2,-4(fp) + 101638c: 00000206 br 1016398 + else + return -EIO; /* Host not connected */ + 1016390: 00bffec4 movi r2,-5 + 1016394: e0bfff15 stw r2,-4(fp) + 1016398: e0bfff17 ldw r2,-4(fp) +} + 101639c: e037883a mov sp,fp + 10163a0: dfc00117 ldw ra,4(sp) + 10163a4: df000017 ldw fp,0(sp) + 10163a8: dec00204 addi sp,sp,8 + 10163ac: f800283a ret + +010163b0 : +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT +static void alt_avalon_timer_sc_irq (void* base) +#else +static void alt_avalon_timer_sc_irq (void* base, alt_u32 id) +#endif +{ + 10163b0: defff904 addi sp,sp,-28 + 10163b4: dfc00615 stw ra,24(sp) + 10163b8: df000515 stw fp,20(sp) + 10163bc: df000504 addi fp,sp,20 + 10163c0: e13ffe15 stw r4,-8(fp) + 10163c4: e17fff15 stw r5,-4(fp) + alt_irq_context cpu_sr; + + /* clear the interrupt */ + IOWR_ALTERA_AVALON_TIMER_STATUS (base, 0); + 10163c8: e0bffe17 ldw r2,-8(fp) + 10163cc: 10000035 stwio zero,0(r2) + /* + * Dummy read to ensure IRQ is negated before the ISR returns. + * The control register is read because reading the status + * register has side-effects per the register map documentation. + */ + IORD_ALTERA_AVALON_TIMER_CONTROL (base); + 10163d0: e0bffe17 ldw r2,-8(fp) + 10163d4: 10800104 addi r2,r2,4 + 10163d8: 10800037 ldwio r2,0(r2) +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 10163dc: 0005303a rdctl r2,status + 10163e0: e0bffc15 stw r2,-16(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 10163e4: e0fffc17 ldw r3,-16(fp) + 10163e8: 00bfff84 movi r2,-2 + 10163ec: 1884703a and r2,r3,r2 + 10163f0: 1001703a wrctl status,r2 + + return context; + 10163f4: e0bffc17 ldw r2,-16(fp) + + /* + * Notify the system of a clock tick. disable interrupts + * during this time to safely support ISR preemption + */ + cpu_sr = alt_irq_disable_all(); + 10163f8: e0bffd15 stw r2,-12(fp) + alt_tick (); + 10163fc: 1017efc0 call 1017efc + 1016400: e0bffd17 ldw r2,-12(fp) + 1016404: e0bffb15 stw r2,-20(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1016408: e0bffb17 ldw r2,-20(fp) + 101640c: 1001703a wrctl status,r2 + alt_irq_enable_all(cpu_sr); +} + 1016410: e037883a mov sp,fp + 1016414: dfc00117 ldw ra,4(sp) + 1016418: df000017 ldw fp,0(sp) + 101641c: dec00204 addi sp,sp,8 + 1016420: f800283a ret + +01016424 : + * auto-generated alt_sys_init() function. + */ + +void alt_avalon_timer_sc_init (void* base, alt_u32 irq_controller_id, + alt_u32 irq, alt_u32 freq) +{ + 1016424: defff904 addi sp,sp,-28 + 1016428: dfc00615 stw ra,24(sp) + 101642c: df000515 stw fp,20(sp) + 1016430: df000504 addi fp,sp,20 + 1016434: e13ffc15 stw r4,-16(fp) + 1016438: e17ffd15 stw r5,-12(fp) + 101643c: e1bffe15 stw r6,-8(fp) + 1016440: e1ffff15 stw r7,-4(fp) + 1016444: e0bfff17 ldw r2,-4(fp) + 1016448: e0bffb15 stw r2,-20(fp) + * in order to initialise the value of the clock frequency. + */ + +static ALT_INLINE int ALT_ALWAYS_INLINE alt_sysclk_init (alt_u32 nticks) +{ + if (! _alt_tick_rate) + 101644c: 008040b4 movhi r2,258 + 1016450: 10b32504 addi r2,r2,-13164 + 1016454: 10800017 ldw r2,0(r2) + 1016458: 1004c03a cmpne r2,r2,zero + 101645c: 1000041e bne r2,zero,1016470 + { + _alt_tick_rate = nticks; + 1016460: 00c040b4 movhi r3,258 + 1016464: 18f32504 addi r3,r3,-13164 + 1016468: e0bffb17 ldw r2,-20(fp) + 101646c: 18800015 stw r2,0(r3) + + alt_sysclk_init (freq); + + /* set to free running mode */ + + IOWR_ALTERA_AVALON_TIMER_CONTROL (base, + 1016470: e0bffc17 ldw r2,-16(fp) + 1016474: 10800104 addi r2,r2,4 + 1016478: 1007883a mov r3,r2 + 101647c: 008001c4 movi r2,7 + 1016480: 18800035 stwio r2,0(r3) + /* register the interrupt handler, and enable the interrupt */ +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT + alt_ic_isr_register(irq_controller_id, irq, alt_avalon_timer_sc_irq, + base, NULL); +#else + alt_irq_register (irq, base, alt_avalon_timer_sc_irq); + 1016484: e13ffe17 ldw r4,-8(fp) + 1016488: e17ffc17 ldw r5,-16(fp) + 101648c: 01804074 movhi r6,257 + 1016490: 3198ec04 addi r6,r6,25520 + 1016494: 10179e00 call 10179e0 +#endif +} + 1016498: e037883a mov sp,fp + 101649c: dfc00117 ldw ra,4(sp) + 10164a0: df000017 ldw fp,0(sp) + 10164a4: dec00204 addi sp,sp,8 + 10164a8: f800283a ret + +010164ac : + * + */ + +int +altera_avalon_uart_read_fd(alt_fd* fd, char* buffer, int space) +{ + 10164ac: defffa04 addi sp,sp,-24 + 10164b0: dfc00515 stw ra,20(sp) + 10164b4: df000415 stw fp,16(sp) + 10164b8: df000404 addi fp,sp,16 + 10164bc: e13ffd15 stw r4,-12(fp) + 10164c0: e17ffe15 stw r5,-8(fp) + 10164c4: e1bfff15 stw r6,-4(fp) + altera_avalon_uart_dev* dev = (altera_avalon_uart_dev*) fd->dev; + 10164c8: e0bffd17 ldw r2,-12(fp) + 10164cc: 10800017 ldw r2,0(r2) + 10164d0: e0bffc15 stw r2,-16(fp) + + return altera_avalon_uart_read(&dev->state, buffer, space, + 10164d4: e0bffc17 ldw r2,-16(fp) + 10164d8: 11000a04 addi r4,r2,40 + 10164dc: e0bffd17 ldw r2,-12(fp) + 10164e0: 11c00217 ldw r7,8(r2) + 10164e4: e17ffe17 ldw r5,-8(fp) + 10164e8: e1bfff17 ldw r6,-4(fp) + 10164ec: 1016b1c0 call 1016b1c + fd->fd_flags); +} + 10164f0: e037883a mov sp,fp + 10164f4: dfc00117 ldw ra,4(sp) + 10164f8: df000017 ldw fp,0(sp) + 10164fc: dec00204 addi sp,sp,8 + 1016500: f800283a ret + +01016504 : + +int +altera_avalon_uart_write_fd(alt_fd* fd, const char* buffer, int space) +{ + 1016504: defffa04 addi sp,sp,-24 + 1016508: dfc00515 stw ra,20(sp) + 101650c: df000415 stw fp,16(sp) + 1016510: df000404 addi fp,sp,16 + 1016514: e13ffd15 stw r4,-12(fp) + 1016518: e17ffe15 stw r5,-8(fp) + 101651c: e1bfff15 stw r6,-4(fp) + altera_avalon_uart_dev* dev = (altera_avalon_uart_dev*) fd->dev; + 1016520: e0bffd17 ldw r2,-12(fp) + 1016524: 10800017 ldw r2,0(r2) + 1016528: e0bffc15 stw r2,-16(fp) + + return altera_avalon_uart_write(&dev->state, buffer, space, + 101652c: e0bffc17 ldw r2,-16(fp) + 1016530: 11000a04 addi r4,r2,40 + 1016534: e0bffd17 ldw r2,-12(fp) + 1016538: 11c00217 ldw r7,8(r2) + 101653c: e17ffe17 ldw r5,-8(fp) + 1016540: e1bfff17 ldw r6,-4(fp) + 1016544: 1016e2c0 call 1016e2c + fd->fd_flags); +} + 1016548: e037883a mov sp,fp + 101654c: dfc00117 ldw ra,4(sp) + 1016550: df000017 ldw fp,0(sp) + 1016554: dec00204 addi sp,sp,8 + 1016558: f800283a ret + +0101655c : + +#endif /* ALTERA_AVALON_UART_USE_IOCTL */ + +int +altera_avalon_uart_close_fd(alt_fd* fd) +{ + 101655c: defffc04 addi sp,sp,-16 + 1016560: dfc00315 stw ra,12(sp) + 1016564: df000215 stw fp,8(sp) + 1016568: df000204 addi fp,sp,8 + 101656c: e13fff15 stw r4,-4(fp) + altera_avalon_uart_dev* dev = (altera_avalon_uart_dev*) fd->dev; + 1016570: e0bfff17 ldw r2,-4(fp) + 1016574: 10800017 ldw r2,0(r2) + 1016578: e0bffe15 stw r2,-8(fp) + + return altera_avalon_uart_close(&dev->state, fd->fd_flags); + 101657c: e0bffe17 ldw r2,-8(fp) + 1016580: 11000a04 addi r4,r2,40 + 1016584: e0bfff17 ldw r2,-4(fp) + 1016588: 11400217 ldw r5,8(r2) + 101658c: 1016abc0 call 1016abc +} + 1016590: e037883a mov sp,fp + 1016594: dfc00117 ldw ra,4(sp) + 1016598: df000017 ldw fp,0(sp) + 101659c: dec00204 addi sp,sp,8 + 10165a0: f800283a ret + +010165a4 : + alt_u32 status); + +void +altera_avalon_uart_init(altera_avalon_uart_state* sp, + alt_u32 irq_controller_id, alt_u32 irq) +{ + 10165a4: deffef04 addi sp,sp,-68 + 10165a8: dfc01015 stw ra,64(sp) + 10165ac: df000f15 stw fp,60(sp) + 10165b0: df000f04 addi fp,sp,60 + 10165b4: e13ffa15 stw r4,-24(fp) + 10165b8: e17ffb15 stw r5,-20(fp) + 10165bc: e1bffc15 stw r6,-16(fp) + void* base = sp->base; + 10165c0: e0bffa17 ldw r2,-24(fp) + 10165c4: 10800017 ldw r2,0(r2) + 10165c8: e0bff815 stw r2,-32(fp) + /* + * Initialise the read and write flags and the semaphores used to + * protect access to the circular buffers when running in a multi-threaded + * environment. + */ + error = ALT_FLAG_CREATE (&sp->events, 0) || + 10165cc: e0bffa17 ldw r2,-24(fp) + 10165d0: 10800704 addi r2,r2,28 + 10165d4: e0bff515 stw r2,-44(fp) + 10165d8: e03ff60d sth zero,-40(fp) + +static ALT_INLINE int ALT_ALWAYS_INLINE alt_flag_create (OS_FLAG_GRP** pgroup, + OS_FLAGS flags) +{ + INT8U err; + *pgroup = OSFlagCreate (flags, &err); + 10165dc: e13ff60b ldhu r4,-40(fp) + 10165e0: e17ff904 addi r5,fp,-28 + 10165e4: 100f8600 call 100f860 + 10165e8: 1007883a mov r3,r2 + 10165ec: e0bff517 ldw r2,-44(fp) + 10165f0: 10c00015 stw r3,0(r2) + return err; + 10165f4: e0bff903 ldbu r2,-28(fp) + 10165f8: 10803fcc andi r2,r2,255 + 10165fc: 1004c03a cmpne r2,r2,zero + 1016600: 10002a1e bne r2,zero,10166ac + 1016604: e0bffa17 ldw r2,-24(fp) + 1016608: 10800804 addi r2,r2,32 + 101660c: e0bff315 stw r2,-52(fp) + 1016610: 00800044 movi r2,1 + 1016614: e0bff40d sth r2,-48(fp) + */ + +static ALT_INLINE int ALT_ALWAYS_INLINE alt_sem_create (OS_EVENT** sem, + INT16U value) +{ + *sem = OSSemCreate (value); + 1016618: e13ff40b ldhu r4,-48(fp) + 101661c: 1012a640 call 1012a64 + 1016620: 1007883a mov r3,r2 + 1016624: e0bff317 ldw r2,-52(fp) + 1016628: 10c00015 stw r3,0(r2) + return *sem ? 0 : -1; + 101662c: e0bff317 ldw r2,-52(fp) + 1016630: 10800017 ldw r2,0(r2) + 1016634: 1005003a cmpeq r2,r2,zero + 1016638: 1000021e bne r2,zero,1016644 + 101663c: e03ffe15 stw zero,-8(fp) + 1016640: 00000206 br 101664c + 1016644: 00bfffc4 movi r2,-1 + 1016648: e0bffe15 stw r2,-8(fp) + 101664c: e0bffe17 ldw r2,-8(fp) + 1016650: 1004c03a cmpne r2,r2,zero + 1016654: 1000151e bne r2,zero,10166ac + 1016658: e0bffa17 ldw r2,-24(fp) + 101665c: 10800904 addi r2,r2,36 + 1016660: e0bff115 stw r2,-60(fp) + 1016664: 00800044 movi r2,1 + 1016668: e0bff20d sth r2,-56(fp) + */ + +static ALT_INLINE int ALT_ALWAYS_INLINE alt_sem_create (OS_EVENT** sem, + INT16U value) +{ + *sem = OSSemCreate (value); + 101666c: e13ff20b ldhu r4,-56(fp) + 1016670: 1012a640 call 1012a64 + 1016674: 1007883a mov r3,r2 + 1016678: e0bff117 ldw r2,-60(fp) + 101667c: 10c00015 stw r3,0(r2) + return *sem ? 0 : -1; + 1016680: e0bff117 ldw r2,-60(fp) + 1016684: 10800017 ldw r2,0(r2) + 1016688: 1005003a cmpeq r2,r2,zero + 101668c: 1000021e bne r2,zero,1016698 + 1016690: e03ffd15 stw zero,-12(fp) + 1016694: 00000206 br 10166a0 + 1016698: 00bfffc4 movi r2,-1 + 101669c: e0bffd15 stw r2,-12(fp) + 10166a0: e0bffd17 ldw r2,-12(fp) + 10166a4: 1005003a cmpeq r2,r2,zero + 10166a8: 1000031e bne r2,zero,10166b8 + 10166ac: 00800044 movi r2,1 + 10166b0: e0bfff15 stw r2,-4(fp) + 10166b4: 00000106 br 10166bc + 10166b8: e03fff15 stw zero,-4(fp) + 10166bc: e0bfff17 ldw r2,-4(fp) + 10166c0: e0bff715 stw r2,-36(fp) + ALT_SEM_CREATE (&sp->read_lock, 1) || + ALT_SEM_CREATE (&sp->write_lock, 1); + + if (!error) + 10166c4: e0bff717 ldw r2,-36(fp) + 10166c8: 1004c03a cmpne r2,r2,zero + 10166cc: 10000f1e bne r2,zero,101670c + { + /* enable interrupts at the device */ + sp->ctrl = ALTERA_AVALON_UART_CONTROL_RTS_MSK | + 10166d0: e0fffa17 ldw r3,-24(fp) + 10166d4: 00832004 movi r2,3200 + 10166d8: 18800115 stw r2,4(r3) + ALTERA_AVALON_UART_CONTROL_RRDY_MSK | + ALTERA_AVALON_UART_CONTROL_DCTS_MSK; + + IOWR_ALTERA_AVALON_UART_CONTROL(base, sp->ctrl); + 10166dc: e0bff817 ldw r2,-32(fp) + 10166e0: 11000304 addi r4,r2,12 + 10166e4: e0bffa17 ldw r2,-24(fp) + 10166e8: 10800117 ldw r2,4(r2) + 10166ec: 1007883a mov r3,r2 + 10166f0: 2005883a mov r2,r4 + 10166f4: 10c00035 stwio r3,0(r2) + /* register the interrupt handler */ +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT + alt_ic_isr_register(irq_controller_id, irq, altera_avalon_uart_irq, sp, + 0x0); +#else + alt_irq_register (irq, sp, altera_avalon_uart_irq); + 10166f8: e13ffc17 ldw r4,-16(fp) + 10166fc: e17ffa17 ldw r5,-24(fp) + 1016700: 01804074 movhi r6,257 + 1016704: 3199c804 addi r6,r6,26400 + 1016708: 10179e00 call 10179e0 +#endif + } +} + 101670c: e037883a mov sp,fp + 1016710: dfc00117 ldw ra,4(sp) + 1016714: df000017 ldw fp,0(sp) + 1016718: dec00204 addi sp,sp,8 + 101671c: f800283a ret + +01016720 : +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT +static void altera_avalon_uart_irq(void* context) +#else +static void altera_avalon_uart_irq(void* context, alt_u32 id) +#endif +{ + 1016720: defff904 addi sp,sp,-28 + 1016724: dfc00615 stw ra,24(sp) + 1016728: df000515 stw fp,20(sp) + 101672c: df000504 addi fp,sp,20 + 1016730: e13ffe15 stw r4,-8(fp) + 1016734: e17fff15 stw r5,-4(fp) + alt_u32 status; + + altera_avalon_uart_state* sp = (altera_avalon_uart_state*) context; + 1016738: e0bffe17 ldw r2,-8(fp) + 101673c: e0bffc15 stw r2,-16(fp) + void* base = sp->base; + 1016740: e0bffc17 ldw r2,-16(fp) + 1016744: 10800017 ldw r2,0(r2) + 1016748: e0bffb15 stw r2,-20(fp) + /* + * Read the status register in order to determine the cause of the + * interrupt. + */ + + status = IORD_ALTERA_AVALON_UART_STATUS(base); + 101674c: e0bffb17 ldw r2,-20(fp) + 1016750: 10800204 addi r2,r2,8 + 1016754: 10800037 ldwio r2,0(r2) + 1016758: e0bffd15 stw r2,-12(fp) + + /* Clear any error flags set at the device */ + IOWR_ALTERA_AVALON_UART_STATUS(base, 0); + 101675c: e0bffb17 ldw r2,-20(fp) + 1016760: 10800204 addi r2,r2,8 + 1016764: 10000035 stwio zero,0(r2) + + /* Dummy read to ensure IRQ is negated before ISR returns */ + IORD_ALTERA_AVALON_UART_STATUS(base); + 1016768: e0bffb17 ldw r2,-20(fp) + 101676c: 10800204 addi r2,r2,8 + 1016770: 10800037 ldwio r2,0(r2) + + /* process a read irq */ + if (status & ALTERA_AVALON_UART_STATUS_RRDY_MSK) + 1016774: e0bffd17 ldw r2,-12(fp) + 1016778: 1080200c andi r2,r2,128 + 101677c: 1005003a cmpeq r2,r2,zero + 1016780: 1000031e bne r2,zero,1016790 + { + altera_avalon_uart_rxirq(sp, status); + 1016784: e13ffc17 ldw r4,-16(fp) + 1016788: e17ffd17 ldw r5,-12(fp) + 101678c: 10167c00 call 10167c0 + } + + /* process a write irq */ + if (status & (ALTERA_AVALON_UART_STATUS_TRDY_MSK | + 1016790: e0bffd17 ldw r2,-12(fp) + 1016794: 1081100c andi r2,r2,1088 + 1016798: 1005003a cmpeq r2,r2,zero + 101679c: 1000031e bne r2,zero,10167ac + ALTERA_AVALON_UART_STATUS_DCTS_MSK)) + { + altera_avalon_uart_txirq(sp, status); + 10167a0: e13ffc17 ldw r4,-16(fp) + 10167a4: e17ffd17 ldw r5,-12(fp) + 10167a8: 10168fc0 call 10168fc + } + + +} + 10167ac: e037883a mov sp,fp + 10167b0: dfc00117 ldw ra,4(sp) + 10167b4: df000017 ldw fp,0(sp) + 10167b8: dec00204 addi sp,sp,8 + 10167bc: f800283a ret + +010167c0 : + * the receive circular buffer, and sets the apropriate flags to indicate + * that there is data ready to be processed. + */ +static void +altera_avalon_uart_rxirq(altera_avalon_uart_state* sp, alt_u32 status) +{ + 10167c0: defff804 addi sp,sp,-32 + 10167c4: dfc00715 stw ra,28(sp) + 10167c8: df000615 stw fp,24(sp) + 10167cc: df000604 addi fp,sp,24 + 10167d0: e13ffe15 stw r4,-8(fp) + 10167d4: e17fff15 stw r5,-4(fp) + alt_u32 next; + + /* If there was an error, discard the data */ + + if (status & (ALTERA_AVALON_UART_STATUS_PE_MSK | + 10167d8: e0bfff17 ldw r2,-4(fp) + 10167dc: 108000cc andi r2,r2,3 + 10167e0: 1004c03a cmpne r2,r2,zero + 10167e4: 1000401e bne r2,zero,10168e8 + * In a multi-threaded environment, set the read event flag to indicate + * that there is data ready. This is only done if the circular buffer was + * previously empty. + */ + + if (sp->rx_end == sp->rx_start) + 10167e8: e0bffe17 ldw r2,-8(fp) + 10167ec: 10c00317 ldw r3,12(r2) + 10167f0: e0bffe17 ldw r2,-8(fp) + 10167f4: 10800217 ldw r2,8(r2) + 10167f8: 1880121e bne r3,r2,1016844 + { + ALT_FLAG_POST (sp->events, ALT_UART_READ_RDY, OS_FLAG_SET); + 10167fc: e0bffe17 ldw r2,-8(fp) + 1016800: 10800717 ldw r2,28(r2) + 1016804: e0bffa15 stw r2,-24(fp) + 1016808: 00800044 movi r2,1 + 101680c: e0bffb0d sth r2,-20(fp) + 1016810: 00800044 movi r2,1 + 1016814: e0bffb85 stb r2,-18(fp) + OS_FLAGS flags, + INT8U opt) +{ + INT8U err; + + if (OSRunning) + 1016818: 008040b4 movhi r2,258 + 101681c: 10b31044 addi r2,r2,-13247 + 1016820: 10800003 ldbu r2,0(r2) + 1016824: 10803fcc andi r2,r2,255 + 1016828: 1005003a cmpeq r2,r2,zero + 101682c: 1000051e bne r2,zero,1016844 + { + OSFlagPost (group, flags, opt, &err); + 1016830: e17ffb0b ldhu r5,-20(fp) + 1016834: e1bffb83 ldbu r6,-18(fp) + 1016838: e1fffd04 addi r7,fp,-12 + 101683c: e13ffa17 ldw r4,-24(fp) + 1016840: 10105880 call 1010588 + } + + /* Determine which slot to use next in the circular buffer */ + + next = (sp->rx_end + 1) & ALT_AVALON_UART_BUF_MSK; + 1016844: e0bffe17 ldw r2,-8(fp) + 1016848: 10800317 ldw r2,12(r2) + 101684c: 10800044 addi r2,r2,1 + 1016850: 10800fcc andi r2,r2,63 + 1016854: e0bffc15 stw r2,-16(fp) + + /* Transfer data from the device to the circular buffer */ + + sp->rx_buf[sp->rx_end] = IORD_ALTERA_AVALON_UART_RXDATA(sp->base); + 1016858: e0bffe17 ldw r2,-8(fp) + 101685c: 11000317 ldw r4,12(r2) + 1016860: e0bffe17 ldw r2,-8(fp) + 1016864: 10800017 ldw r2,0(r2) + 1016868: 10800037 ldwio r2,0(r2) + 101686c: 1007883a mov r3,r2 + 1016870: e0bffe17 ldw r2,-8(fp) + 1016874: 2085883a add r2,r4,r2 + 1016878: 10800a04 addi r2,r2,40 + 101687c: 10c00005 stb r3,0(r2) + + sp->rx_end = next; + 1016880: e0fffe17 ldw r3,-8(fp) + 1016884: e0bffc17 ldw r2,-16(fp) + 1016888: 18800315 stw r2,12(r3) + + next = (sp->rx_end + 1) & ALT_AVALON_UART_BUF_MSK; + 101688c: e0bffe17 ldw r2,-8(fp) + 1016890: 10800317 ldw r2,12(r2) + 1016894: 10800044 addi r2,r2,1 + 1016898: 10800fcc andi r2,r2,63 + 101689c: e0bffc15 stw r2,-16(fp) + /* + * If the cicular buffer was full, disable interrupts. Interrupts will be + * re-enabled when data is removed from the buffer. + */ + + if (next == sp->rx_start) + 10168a0: e0bffe17 ldw r2,-8(fp) + 10168a4: 10c00217 ldw r3,8(r2) + 10168a8: e0bffc17 ldw r2,-16(fp) + 10168ac: 18800e1e bne r3,r2,10168e8 + { + sp->ctrl &= ~ALTERA_AVALON_UART_CONTROL_RRDY_MSK; + 10168b0: e0bffe17 ldw r2,-8(fp) + 10168b4: 10c00117 ldw r3,4(r2) + 10168b8: 00bfdfc4 movi r2,-129 + 10168bc: 1886703a and r3,r3,r2 + 10168c0: e0bffe17 ldw r2,-8(fp) + 10168c4: 10c00115 stw r3,4(r2) + IOWR_ALTERA_AVALON_UART_CONTROL(sp->base, sp->ctrl); + 10168c8: e0bffe17 ldw r2,-8(fp) + 10168cc: 10800017 ldw r2,0(r2) + 10168d0: 11000304 addi r4,r2,12 + 10168d4: e0bffe17 ldw r2,-8(fp) + 10168d8: 10800117 ldw r2,4(r2) + 10168dc: 1007883a mov r3,r2 + 10168e0: 2005883a mov r2,r4 + 10168e4: 10c00035 stwio r3,0(r2) + } +} + 10168e8: e037883a mov sp,fp + 10168ec: dfc00117 ldw ra,4(sp) + 10168f0: df000017 ldw fp,0(sp) + 10168f4: dec00204 addi sp,sp,8 + 10168f8: f800283a ret + +010168fc : + * buffer to the device, and sets the apropriate flags to indicate that + * there is data ready to be processed. + */ +static void +altera_avalon_uart_txirq(altera_avalon_uart_state* sp, alt_u32 status) +{ + 10168fc: defffa04 addi sp,sp,-24 + 1016900: dfc00515 stw ra,20(sp) + 1016904: df000415 stw fp,16(sp) + 1016908: df000404 addi fp,sp,16 + 101690c: e13ffe15 stw r4,-8(fp) + 1016910: e17fff15 stw r5,-4(fp) + /* Transfer data if there is some ready to be transfered */ + + if (sp->tx_start != sp->tx_end) + 1016914: e0bffe17 ldw r2,-8(fp) + 1016918: 10c00417 ldw r3,16(r2) + 101691c: e0bffe17 ldw r2,-8(fp) + 1016920: 10800517 ldw r2,20(r2) + 1016924: 18804d26 beq r3,r2,1016a5c + /* + * If the device is using flow control (i.e. RTS/CTS), then the + * transmitter is required to throttle if CTS is high. + */ + + if (!(sp->flags & ALT_AVALON_UART_FC) || + 1016928: e0bffe17 ldw r2,-8(fp) + 101692c: 10800617 ldw r2,24(r2) + 1016930: 1080008c andi r2,r2,2 + 1016934: 1005003a cmpeq r2,r2,zero + 1016938: 1000041e bne r2,zero,101694c + 101693c: e0bfff17 ldw r2,-4(fp) + 1016940: 1082000c andi r2,r2,2048 + 1016944: 1005003a cmpeq r2,r2,zero + 1016948: 1000351e bne r2,zero,1016a20 + * In a multi-threaded environment, set the write event flag to indicate + * that there is space in the circular buffer. This is only done if the + * buffer was previously empty. + */ + + if (sp->tx_start == ((sp->tx_end + 1) & ALT_AVALON_UART_BUF_MSK)) + 101694c: e0bffe17 ldw r2,-8(fp) + 1016950: 10c00417 ldw r3,16(r2) + 1016954: e0bffe17 ldw r2,-8(fp) + 1016958: 10800517 ldw r2,20(r2) + 101695c: 10800044 addi r2,r2,1 + 1016960: 10800fcc andi r2,r2,63 + 1016964: 1880121e bne r3,r2,10169b0 + { + ALT_FLAG_POST (sp->events, + 1016968: e0bffe17 ldw r2,-8(fp) + 101696c: 10800717 ldw r2,28(r2) + 1016970: e0bffc15 stw r2,-16(fp) + 1016974: 00800084 movi r2,2 + 1016978: e0bffd0d sth r2,-12(fp) + 101697c: 00800044 movi r2,1 + 1016980: e0bffd85 stb r2,-10(fp) + OS_FLAGS flags, + INT8U opt) +{ + INT8U err; + + if (OSRunning) + 1016984: 008040b4 movhi r2,258 + 1016988: 10b31044 addi r2,r2,-13247 + 101698c: 10800003 ldbu r2,0(r2) + 1016990: 10803fcc andi r2,r2,255 + 1016994: 1005003a cmpeq r2,r2,zero + 1016998: 1000051e bne r2,zero,10169b0 + { + OSFlagPost (group, flags, opt, &err); + 101699c: e17ffd0b ldhu r5,-12(fp) + 10169a0: e1bffd83 ldbu r6,-10(fp) + 10169a4: e1fffdc4 addi r7,fp,-9 + 10169a8: e13ffc17 ldw r4,-16(fp) + 10169ac: 10105880 call 1010588 + OS_FLAG_SET); + } + + /* Write the data to the device */ + + IOWR_ALTERA_AVALON_UART_TXDATA(sp->base, sp->tx_buf[sp->tx_start]); + 10169b0: e0bffe17 ldw r2,-8(fp) + 10169b4: 10800017 ldw r2,0(r2) + 10169b8: 11000104 addi r4,r2,4 + 10169bc: e0bffe17 ldw r2,-8(fp) + 10169c0: 10c00417 ldw r3,16(r2) + 10169c4: e0bffe17 ldw r2,-8(fp) + 10169c8: 1885883a add r2,r3,r2 + 10169cc: 10801a04 addi r2,r2,104 + 10169d0: 10800003 ldbu r2,0(r2) + 10169d4: 10c03fcc andi r3,r2,255 + 10169d8: 2005883a mov r2,r4 + 10169dc: 10c00035 stwio r3,0(r2) + + sp->tx_start = (++sp->tx_start) & ALT_AVALON_UART_BUF_MSK; + 10169e0: e0bffe17 ldw r2,-8(fp) + 10169e4: 10800417 ldw r2,16(r2) + 10169e8: 10c00044 addi r3,r2,1 + 10169ec: e0bffe17 ldw r2,-8(fp) + 10169f0: 10c00415 stw r3,16(r2) + 10169f4: e0bffe17 ldw r2,-8(fp) + 10169f8: 10800417 ldw r2,16(r2) + 10169fc: 10c00fcc andi r3,r2,63 + 1016a00: e0bffe17 ldw r2,-8(fp) + 1016a04: 10c00415 stw r3,16(r2) + /* + * In case the tranmit interrupt had previously been disabled by + * detecting a low value on CTS, it is reenabled here. + */ + + sp->ctrl |= ALTERA_AVALON_UART_CONTROL_TRDY_MSK; + 1016a08: e0bffe17 ldw r2,-8(fp) + 1016a0c: 10800117 ldw r2,4(r2) + 1016a10: 10c01014 ori r3,r2,64 + 1016a14: e0bffe17 ldw r2,-8(fp) + 1016a18: 10c00115 stw r3,4(r2) + /* + * If the device is using flow control (i.e. RTS/CTS), then the + * transmitter is required to throttle if CTS is high. + */ + + if (!(sp->flags & ALT_AVALON_UART_FC) || + 1016a1c: 00000f06 br 1016a5c + * the last write to the status register. To avoid this resulting in + * deadlock, it's necessary to re-check the status register here + * before throttling. + */ + + status = IORD_ALTERA_AVALON_UART_STATUS(sp->base); + 1016a20: e0bffe17 ldw r2,-8(fp) + 1016a24: 10800017 ldw r2,0(r2) + 1016a28: 10800204 addi r2,r2,8 + 1016a2c: 10800037 ldwio r2,0(r2) + 1016a30: e0bfff15 stw r2,-4(fp) + + if (!(status & ALTERA_AVALON_UART_STATUS_CTS_MSK)) + 1016a34: e0bfff17 ldw r2,-4(fp) + 1016a38: 1082000c andi r2,r2,2048 + 1016a3c: 1004c03a cmpne r2,r2,zero + 1016a40: 1000061e bne r2,zero,1016a5c + { + sp->ctrl &= ~ALTERA_AVALON_UART_CONTROL_TRDY_MSK; + 1016a44: e0bffe17 ldw r2,-8(fp) + 1016a48: 10c00117 ldw r3,4(r2) + 1016a4c: 00bfefc4 movi r2,-65 + 1016a50: 1886703a and r3,r3,r2 + 1016a54: e0bffe17 ldw r2,-8(fp) + 1016a58: 10c00115 stw r3,4(r2) + /* + * If the circular buffer is empty, disable the interrupt. This will be + * re-enabled when new data is placed in the buffer. + */ + + if (sp->tx_start == sp->tx_end) + 1016a5c: e0bffe17 ldw r2,-8(fp) + 1016a60: 10c00417 ldw r3,16(r2) + 1016a64: e0bffe17 ldw r2,-8(fp) + 1016a68: 10800517 ldw r2,20(r2) + 1016a6c: 1880061e bne r3,r2,1016a88 + { + sp->ctrl &= ~(ALTERA_AVALON_UART_CONTROL_TRDY_MSK | + 1016a70: e0bffe17 ldw r2,-8(fp) + 1016a74: 10c00117 ldw r3,4(r2) + 1016a78: 00beefc4 movi r2,-1089 + 1016a7c: 1886703a and r3,r3,r2 + 1016a80: e0bffe17 ldw r2,-8(fp) + 1016a84: 10c00115 stw r3,4(r2) + ALTERA_AVALON_UART_CONTROL_DCTS_MSK); + } + + IOWR_ALTERA_AVALON_UART_CONTROL(sp->base, sp->ctrl); + 1016a88: e0bffe17 ldw r2,-8(fp) + 1016a8c: 10800017 ldw r2,0(r2) + 1016a90: 11000304 addi r4,r2,12 + 1016a94: e0bffe17 ldw r2,-8(fp) + 1016a98: 10800117 ldw r2,4(r2) + 1016a9c: 1007883a mov r3,r2 + 1016aa0: 2005883a mov r2,r4 + 1016aa4: 10c00035 stwio r3,0(r2) +} + 1016aa8: e037883a mov sp,fp + 1016aac: dfc00117 ldw ra,4(sp) + 1016ab0: df000017 ldw fp,0(sp) + 1016ab4: dec00204 addi sp,sp,8 + 1016ab8: f800283a ret + +01016abc : + * The close routine is not implemented for the small driver; instead it will + * map to null. This is because the small driver simply waits while characters + * are transmitted; there is no interrupt-serviced buffer to empty + */ +int altera_avalon_uart_close(altera_avalon_uart_state* sp, int flags) +{ + 1016abc: defffc04 addi sp,sp,-16 + 1016ac0: df000315 stw fp,12(sp) + 1016ac4: df000304 addi fp,sp,12 + 1016ac8: e13ffd15 stw r4,-12(fp) + 1016acc: e17ffe15 stw r5,-8(fp) + /* + * Wait for all transmit data to be emptied by the UART ISR. + */ + while (sp->tx_start != sp->tx_end) { + 1016ad0: 00000706 br 1016af0 + if (flags & O_NONBLOCK) { + 1016ad4: e0bffe17 ldw r2,-8(fp) + 1016ad8: 1090000c andi r2,r2,16384 + 1016adc: 1005003a cmpeq r2,r2,zero + 1016ae0: 1000031e bne r2,zero,1016af0 + return -EWOULDBLOCK; + 1016ae4: 00bffd44 movi r2,-11 + 1016ae8: e0bfff15 stw r2,-4(fp) + 1016aec: 00000606 br 1016b08 +int altera_avalon_uart_close(altera_avalon_uart_state* sp, int flags) +{ + /* + * Wait for all transmit data to be emptied by the UART ISR. + */ + while (sp->tx_start != sp->tx_end) { + 1016af0: e0bffd17 ldw r2,-12(fp) + 1016af4: 10c00417 ldw r3,16(r2) + 1016af8: e0bffd17 ldw r2,-12(fp) + 1016afc: 10800517 ldw r2,20(r2) + 1016b00: 18bff41e bne r3,r2,1016ad4 + if (flags & O_NONBLOCK) { + return -EWOULDBLOCK; + } + } + + return 0; + 1016b04: e03fff15 stw zero,-4(fp) + 1016b08: e0bfff17 ldw r2,-4(fp) +} + 1016b0c: e037883a mov sp,fp + 1016b10: df000017 ldw fp,0(sp) + 1016b14: dec00104 addi sp,sp,4 + 1016b18: f800283a ret + +01016b1c : + */ + +int +altera_avalon_uart_read(altera_avalon_uart_state* sp, char* ptr, int len, + int flags) +{ + 1016b1c: deffe904 addi sp,sp,-92 + 1016b20: dfc01615 stw ra,88(sp) + 1016b24: df001515 stw fp,84(sp) + 1016b28: df001504 addi fp,sp,84 + 1016b2c: e13ffb15 stw r4,-20(fp) + 1016b30: e17ffc15 stw r5,-16(fp) + 1016b34: e1bffd15 stw r6,-12(fp) + 1016b38: e1fffe15 stw r7,-8(fp) + alt_irq_context context; + int block; + alt_u32 next; + alt_u8 read_would_block = 0; + 1016b3c: e03ff605 stb zero,-40(fp) + int count = 0; + 1016b40: e03ff515 stw zero,-44(fp) + /* + * Construct a flag to indicate whether the device is being accessed in + * blocking or non-blocking mode. + */ + + block = !(flags & O_NONBLOCK); + 1016b44: e0bffe17 ldw r2,-8(fp) + 1016b48: 1090000c andi r2,r2,16384 + 1016b4c: 1005003a cmpeq r2,r2,zero + 1016b50: e0bff815 stw r2,-32(fp) + /* + * When running in a multi threaded environment, obtain the "read_lock" + * semaphore. This ensures that reading from the device is thread-safe. + */ + + ALT_SEM_PEND (sp->read_lock, 0); + 1016b54: e0bffb17 ldw r2,-20(fp) + 1016b58: 10800817 ldw r2,32(r2) + 1016b5c: e0bff315 stw r2,-52(fp) + 1016b60: e03ff40d sth zero,-48(fp) + +static ALT_INLINE int ALT_ALWAYS_INLINE alt_sem_pend (OS_EVENT* sem, + INT16U timeout) +{ + INT8U err; + OSSemPend (sem, timeout, &err); + 1016b64: e17ff40b ldhu r5,-48(fp) + 1016b68: e1bffa04 addi r6,fp,-24 + 1016b6c: e13ff317 ldw r4,-52(fp) + 1016b70: 1012e180 call 1012e18 + /* + * Calculate which slot in the circular buffer is the next one to read + * data from. + */ + + next = (sp->rx_start + 1) & ALT_AVALON_UART_BUF_MSK; + 1016b74: e0bffb17 ldw r2,-20(fp) + 1016b78: 10800217 ldw r2,8(r2) + 1016b7c: 10800044 addi r2,r2,1 + 1016b80: 10800fcc andi r2,r2,63 + 1016b84: e0bff715 stw r2,-36(fp) + /* + * Read the required amount of data, until the circular buffer runs + * empty + */ + + while ((count < len) && (sp->rx_start != sp->rx_end)) + 1016b88: 00001906 br 1016bf0 + { + count++; + 1016b8c: e0bff517 ldw r2,-44(fp) + 1016b90: 10800044 addi r2,r2,1 + 1016b94: e0bff515 stw r2,-44(fp) + *ptr++ = sp->rx_buf[sp->rx_start]; + 1016b98: e0bffb17 ldw r2,-20(fp) + 1016b9c: 10c00217 ldw r3,8(r2) + 1016ba0: e0bffb17 ldw r2,-20(fp) + 1016ba4: 1885883a add r2,r3,r2 + 1016ba8: 10800a04 addi r2,r2,40 + 1016bac: 10800003 ldbu r2,0(r2) + 1016bb0: 1007883a mov r3,r2 + 1016bb4: e0bffc17 ldw r2,-16(fp) + 1016bb8: 10c00005 stb r3,0(r2) + 1016bbc: e0bffc17 ldw r2,-16(fp) + 1016bc0: 10800044 addi r2,r2,1 + 1016bc4: e0bffc15 stw r2,-16(fp) + + sp->rx_start = (++sp->rx_start) & ALT_AVALON_UART_BUF_MSK; + 1016bc8: e0bffb17 ldw r2,-20(fp) + 1016bcc: 10800217 ldw r2,8(r2) + 1016bd0: 10c00044 addi r3,r2,1 + 1016bd4: e0bffb17 ldw r2,-20(fp) + 1016bd8: 10c00215 stw r3,8(r2) + 1016bdc: e0bffb17 ldw r2,-20(fp) + 1016be0: 10800217 ldw r2,8(r2) + 1016be4: 10c00fcc andi r3,r2,63 + 1016be8: e0bffb17 ldw r2,-20(fp) + 1016bec: 10c00215 stw r3,8(r2) + /* + * Read the required amount of data, until the circular buffer runs + * empty + */ + + while ((count < len) && (sp->rx_start != sp->rx_end)) + 1016bf0: e0fff517 ldw r3,-44(fp) + 1016bf4: e0bffd17 ldw r2,-12(fp) + 1016bf8: 1880050e bge r3,r2,1016c10 + 1016bfc: e0bffb17 ldw r2,-20(fp) + 1016c00: 10c00217 ldw r3,8(r2) + 1016c04: e0bffb17 ldw r2,-20(fp) + 1016c08: 10800317 ldw r2,12(r2) + 1016c0c: 18bfdf1e bne r3,r2,1016b8c + /* + * If no data has been transferred, the circular buffer is empty, and + * this is not a non-blocking access, block waiting for data to arrive. + */ + + if (!count && (sp->rx_start == sp->rx_end)) + 1016c10: e0bff517 ldw r2,-44(fp) + 1016c14: 1004c03a cmpne r2,r2,zero + 1016c18: 10003c1e bne r2,zero,1016d0c + 1016c1c: e0bffb17 ldw r2,-20(fp) + 1016c20: 10c00217 ldw r3,8(r2) + 1016c24: e0bffb17 ldw r2,-20(fp) + 1016c28: 10800317 ldw r2,12(r2) + 1016c2c: 1880371e bne r3,r2,1016d0c + { + if (!block) + 1016c30: e0bff817 ldw r2,-32(fp) + 1016c34: 1004c03a cmpne r2,r2,zero + 1016c38: 1000061e bne r2,zero,1016c54 + { + /* Set errno to indicate the reason we're not returning any data */ + + ALT_ERRNO = EWOULDBLOCK; + 1016c3c: 1016dcc0 call 1016dcc + 1016c40: 00c002c4 movi r3,11 + 1016c44: 10c00015 stw r3,0(r2) + read_would_block = 1; + 1016c48: 00800044 movi r2,1 + 1016c4c: e0bff605 stb r2,-40(fp) + break; + 1016c50: 00003406 br 1016d24 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1016c54: 0005303a rdctl r2,status + 1016c58: e0bff215 stw r2,-56(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1016c5c: e0fff217 ldw r3,-56(fp) + 1016c60: 00bfff84 movi r2,-2 + 1016c64: 1884703a and r2,r3,r2 + 1016c68: 1001703a wrctl status,r2 + + return context; + 1016c6c: e0bff217 ldw r2,-56(fp) + { + /* Block waiting for some data to arrive */ + + /* First, ensure read interrupts are enabled to avoid deadlock */ + + context = alt_irq_disable_all (); + 1016c70: e0bff915 stw r2,-28(fp) + sp->ctrl |= ALTERA_AVALON_UART_CONTROL_RRDY_MSK; + 1016c74: e0bffb17 ldw r2,-20(fp) + 1016c78: 10800117 ldw r2,4(r2) + 1016c7c: 10c02014 ori r3,r2,128 + 1016c80: e0bffb17 ldw r2,-20(fp) + 1016c84: 10c00115 stw r3,4(r2) + IOWR_ALTERA_AVALON_UART_CONTROL(sp->base, sp->ctrl); + 1016c88: e0bffb17 ldw r2,-20(fp) + 1016c8c: 10800017 ldw r2,0(r2) + 1016c90: 11000304 addi r4,r2,12 + 1016c94: e0bffb17 ldw r2,-20(fp) + 1016c98: 10800117 ldw r2,4(r2) + 1016c9c: 1007883a mov r3,r2 + 1016ca0: 2005883a mov r2,r4 + 1016ca4: 10c00035 stwio r3,0(r2) + 1016ca8: e0bff917 ldw r2,-28(fp) + 1016cac: e0bff115 stw r2,-60(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1016cb0: e0bff117 ldw r2,-60(fp) + 1016cb4: 1001703a wrctl status,r2 + * flag set in the interrupt service routine. This avoids wasting CPU + * cycles waiting in this thread, when we could be doing something more + * profitable elsewhere. + */ + + ALT_FLAG_PEND (sp->events, + 1016cb8: e0bffb17 ldw r2,-20(fp) + 1016cbc: 10800717 ldw r2,28(r2) + 1016cc0: e0bfee15 stw r2,-72(fp) + 1016cc4: 00800044 movi r2,1 + 1016cc8: e0bfef0d sth r2,-68(fp) + 1016ccc: 00bfe0c4 movi r2,-125 + 1016cd0: e0bfef85 stb r2,-66(fp) + 1016cd4: e03ff00d sth zero,-64(fp) + OS_FLAGS flags, + INT8U wait_type, + INT16U timeout) +{ + INT8U err; + if (OSRunning) + 1016cd8: 008040b4 movhi r2,258 + 1016cdc: 10b31044 addi r2,r2,-13247 + 1016ce0: 10800003 ldbu r2,0(r2) + 1016ce4: 10803fcc andi r2,r2,255 + 1016ce8: 1005003a cmpeq r2,r2,zero + 1016cec: 1000071e bne r2,zero,1016d0c + { + OSFlagPend (group, flags, wait_type, timeout, &err); + 1016cf0: e17fef0b ldhu r5,-68(fp) + 1016cf4: e1bfef83 ldbu r6,-66(fp) + 1016cf8: e1fff00b ldhu r7,-64(fp) + 1016cfc: e0bffa44 addi r2,fp,-23 + 1016d00: d8800015 stw r2,0(sp) + 1016d04: e13fee17 ldw r4,-72(fp) + 1016d08: 100fedc0 call 100fedc + OS_FLAG_WAIT_SET_ANY + OS_FLAG_CONSUME, + 0); + } + } + } + while (!count && len); + 1016d0c: e0bff517 ldw r2,-44(fp) + 1016d10: 1004c03a cmpne r2,r2,zero + 1016d14: 1000031e bne r2,zero,1016d24 + 1016d18: e0bffd17 ldw r2,-12(fp) + 1016d1c: 1004c03a cmpne r2,r2,zero + 1016d20: 103fb31e bne r2,zero,1016bf0 + /* + * Now that access to the circular buffer is complete, release the read + * semaphore so that other threads can access the buffer. + */ + + ALT_SEM_POST (sp->read_lock); + 1016d24: e0bffb17 ldw r2,-20(fp) + 1016d28: 11000817 ldw r4,32(r2) + 1016d2c: 10132100 call 1013210 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1016d30: 0005303a rdctl r2,status + 1016d34: e0bfed15 stw r2,-76(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1016d38: e0ffed17 ldw r3,-76(fp) + 1016d3c: 00bfff84 movi r2,-2 + 1016d40: 1884703a and r2,r3,r2 + 1016d44: 1001703a wrctl status,r2 + + return context; + 1016d48: e0bfed17 ldw r2,-76(fp) + /* + * Ensure that interrupts are enabled, so that the circular buffer can + * re-fill. + */ + + context = alt_irq_disable_all (); + 1016d4c: e0bff915 stw r2,-28(fp) + sp->ctrl |= ALTERA_AVALON_UART_CONTROL_RRDY_MSK; + 1016d50: e0bffb17 ldw r2,-20(fp) + 1016d54: 10800117 ldw r2,4(r2) + 1016d58: 10c02014 ori r3,r2,128 + 1016d5c: e0bffb17 ldw r2,-20(fp) + 1016d60: 10c00115 stw r3,4(r2) + IOWR_ALTERA_AVALON_UART_CONTROL(sp->base, sp->ctrl); + 1016d64: e0bffb17 ldw r2,-20(fp) + 1016d68: 10800017 ldw r2,0(r2) + 1016d6c: 11000304 addi r4,r2,12 + 1016d70: e0bffb17 ldw r2,-20(fp) + 1016d74: 10800117 ldw r2,4(r2) + 1016d78: 1007883a mov r3,r2 + 1016d7c: 2005883a mov r2,r4 + 1016d80: 10c00035 stwio r3,0(r2) + 1016d84: e0bff917 ldw r2,-28(fp) + 1016d88: e0bfec15 stw r2,-80(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1016d8c: e0bfec17 ldw r2,-80(fp) + 1016d90: 1001703a wrctl status,r2 + alt_irq_enable_all (context); + + /* Return the number of bytes read */ + if(read_would_block) { + 1016d94: e0bff603 ldbu r2,-40(fp) + 1016d98: 1005003a cmpeq r2,r2,zero + 1016d9c: 1000031e bne r2,zero,1016dac + return ~EWOULDBLOCK; + 1016da0: 00bffd04 movi r2,-12 + 1016da4: e0bfff15 stw r2,-4(fp) + 1016da8: 00000206 br 1016db4 + } + else { + return count; + 1016dac: e0bff517 ldw r2,-44(fp) + 1016db0: e0bfff15 stw r2,-4(fp) + 1016db4: e0bfff17 ldw r2,-4(fp) + } +} + 1016db8: e037883a mov sp,fp + 1016dbc: dfc00117 ldw ra,4(sp) + 1016dc0: df000017 ldw fp,0(sp) + 1016dc4: dec00204 addi sp,sp,8 + 1016dc8: f800283a ret + +01016dcc : +#undef errno + +extern int errno; + +static ALT_INLINE int* alt_get_errno(void) +{ + 1016dcc: defffd04 addi sp,sp,-12 + 1016dd0: dfc00215 stw ra,8(sp) + 1016dd4: df000115 stw fp,4(sp) + 1016dd8: df000104 addi fp,sp,4 + return ((alt_errno) ? alt_errno() : &errno); + 1016ddc: 008040b4 movhi r2,258 + 1016de0: 10aba104 addi r2,r2,-20860 + 1016de4: 10800017 ldw r2,0(r2) + 1016de8: 1005003a cmpeq r2,r2,zero + 1016dec: 1000061e bne r2,zero,1016e08 + 1016df0: 008040b4 movhi r2,258 + 1016df4: 10aba104 addi r2,r2,-20860 + 1016df8: 10800017 ldw r2,0(r2) + 1016dfc: 103ee83a callr r2 + 1016e00: e0bfff15 stw r2,-4(fp) + 1016e04: 00000306 br 1016e14 + 1016e08: 008040b4 movhi r2,258 + 1016e0c: 10b30404 addi r2,r2,-13296 + 1016e10: e0bfff15 stw r2,-4(fp) + 1016e14: e0bfff17 ldw r2,-4(fp) +} + 1016e18: e037883a mov sp,fp + 1016e1c: dfc00117 ldw ra,4(sp) + 1016e20: df000017 ldw fp,0(sp) + 1016e24: dec00204 addi sp,sp,8 + 1016e28: f800283a ret + +01016e2c : + */ + +int +altera_avalon_uart_write(altera_avalon_uart_state* sp, const char* ptr, int len, + int flags) +{ + 1016e2c: deffeb04 addi sp,sp,-84 + 1016e30: dfc01415 stw ra,80(sp) + 1016e34: df001315 stw fp,76(sp) + 1016e38: df001304 addi fp,sp,76 + 1016e3c: e13ffc15 stw r4,-16(fp) + 1016e40: e17ffd15 stw r5,-12(fp) + 1016e44: e1bffe15 stw r6,-8(fp) + 1016e48: e1ffff15 stw r7,-4(fp) + alt_irq_context context; + int no_block; + alt_u32 next; + int count = len; + 1016e4c: e0bffe17 ldw r2,-8(fp) + 1016e50: e0bff715 stw r2,-36(fp) + /* + * Construct a flag to indicate whether the device is being accessed in + * blocking or non-blocking mode. + */ + + no_block = (flags & O_NONBLOCK); + 1016e54: e0bfff17 ldw r2,-4(fp) + 1016e58: 1090000c andi r2,r2,16384 + 1016e5c: e0bff915 stw r2,-28(fp) + /* + * When running in a multi threaded environment, obtain the "write_lock" + * semaphore. This ensures that writing to the device is thread-safe. + */ + + ALT_SEM_PEND (sp->write_lock, 0); + 1016e60: e0bffc17 ldw r2,-16(fp) + 1016e64: 10800917 ldw r2,36(r2) + 1016e68: e0bff515 stw r2,-44(fp) + 1016e6c: e03ff60d sth zero,-40(fp) + 1016e70: e17ff60b ldhu r5,-40(fp) + 1016e74: e1bffb04 addi r6,fp,-20 + 1016e78: e13ff517 ldw r4,-44(fp) + 1016e7c: 1012e180 call 1012e18 + * Loop transferring data from the input buffer to the transmit circular + * buffer. The loop is terminated once all the data has been transferred, + * or, (if in non-blocking mode) the buffer becomes full. + */ + + while (count) + 1016e80: 00005506 br 1016fd8 + { + /* Determine the next slot in the buffer to access */ + + next = (sp->tx_end + 1) & ALT_AVALON_UART_BUF_MSK; + 1016e84: e0bffc17 ldw r2,-16(fp) + 1016e88: 10800517 ldw r2,20(r2) + 1016e8c: 10800044 addi r2,r2,1 + 1016e90: 10800fcc andi r2,r2,63 + 1016e94: e0bff815 stw r2,-32(fp) + + /* block waiting for space if necessary */ + + if (next == sp->tx_start) + 1016e98: e0bffc17 ldw r2,-16(fp) + 1016e9c: 10c00417 ldw r3,16(r2) + 1016ea0: e0bff817 ldw r2,-32(fp) + 1016ea4: 18803a1e bne r3,r2,1016f90 + { + if (no_block) + 1016ea8: e0bff917 ldw r2,-28(fp) + 1016eac: 1005003a cmpeq r2,r2,zero + 1016eb0: 1000051e bne r2,zero,1016ec8 + { + /* Set errno to indicate why this function returned early */ + + ALT_ERRNO = EWOULDBLOCK; + 1016eb4: 10170740 call 1017074 + 1016eb8: 1007883a mov r3,r2 + 1016ebc: 008002c4 movi r2,11 + 1016ec0: 18800015 stw r2,0(r3) + break; + 1016ec4: 00004706 br 1016fe4 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1016ec8: 0005303a rdctl r2,status + 1016ecc: e0bff415 stw r2,-48(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1016ed0: e0fff417 ldw r3,-48(fp) + 1016ed4: 00bfff84 movi r2,-2 + 1016ed8: 1884703a and r2,r3,r2 + 1016edc: 1001703a wrctl status,r2 + + return context; + 1016ee0: e0bff417 ldw r2,-48(fp) + { + /* Block waiting for space in the circular buffer */ + + /* First, ensure transmit interrupts are enabled to avoid deadlock */ + + context = alt_irq_disable_all (); + 1016ee4: e0bffa15 stw r2,-24(fp) + sp->ctrl |= (ALTERA_AVALON_UART_CONTROL_TRDY_MSK | + 1016ee8: e0bffc17 ldw r2,-16(fp) + 1016eec: 10800117 ldw r2,4(r2) + 1016ef0: 10c11014 ori r3,r2,1088 + 1016ef4: e0bffc17 ldw r2,-16(fp) + 1016ef8: 10c00115 stw r3,4(r2) + ALTERA_AVALON_UART_CONTROL_DCTS_MSK); + IOWR_ALTERA_AVALON_UART_CONTROL(sp->base, sp->ctrl); + 1016efc: e0bffc17 ldw r2,-16(fp) + 1016f00: 10800017 ldw r2,0(r2) + 1016f04: 11000304 addi r4,r2,12 + 1016f08: e0bffc17 ldw r2,-16(fp) + 1016f0c: 10800117 ldw r2,4(r2) + 1016f10: 1007883a mov r3,r2 + 1016f14: 2005883a mov r2,r4 + 1016f18: 10c00035 stwio r3,0(r2) + 1016f1c: e0bffa17 ldw r2,-24(fp) + 1016f20: e0bff315 stw r2,-52(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1016f24: e0bff317 ldw r2,-52(fp) + 1016f28: 1001703a wrctl status,r2 + * flag set in the interrupt service routine. This avoids wasting CPU + * cycles waiting in this thread, when we could be doing something + * more profitable elsewhere. + */ + + ALT_FLAG_PEND (sp->events, + 1016f2c: e0bffc17 ldw r2,-16(fp) + 1016f30: 10800717 ldw r2,28(r2) + 1016f34: e0bff015 stw r2,-64(fp) + 1016f38: 00800084 movi r2,2 + 1016f3c: e0bff10d sth r2,-60(fp) + 1016f40: 00bfe0c4 movi r2,-125 + 1016f44: e0bff185 stb r2,-58(fp) + 1016f48: e03ff20d sth zero,-56(fp) + OS_FLAGS flags, + INT8U wait_type, + INT16U timeout) +{ + INT8U err; + if (OSRunning) + 1016f4c: 008040b4 movhi r2,258 + 1016f50: 10b31044 addi r2,r2,-13247 + 1016f54: 10800003 ldbu r2,0(r2) + 1016f58: 10803fcc andi r2,r2,255 + 1016f5c: 1005003a cmpeq r2,r2,zero + 1016f60: 1000071e bne r2,zero,1016f80 + { + OSFlagPend (group, flags, wait_type, timeout, &err); + 1016f64: e17ff10b ldhu r5,-60(fp) + 1016f68: e1bff183 ldbu r6,-58(fp) + 1016f6c: e1fff20b ldhu r7,-56(fp) + 1016f70: e0bffb44 addi r2,fp,-19 + 1016f74: d8800015 stw r2,0(sp) + 1016f78: e13ff017 ldw r4,-64(fp) + 1016f7c: 100fedc0 call 100fedc + ALT_UART_WRITE_RDY, + OS_FLAG_WAIT_SET_ANY + OS_FLAG_CONSUME, + 0); + } + while ((next == sp->tx_start)); + 1016f80: e0bffc17 ldw r2,-16(fp) + 1016f84: 10c00417 ldw r3,16(r2) + 1016f88: e0bff817 ldw r2,-32(fp) + 1016f8c: 18bfe726 beq r3,r2,1016f2c + } + } + + count--; + 1016f90: e0bff717 ldw r2,-36(fp) + 1016f94: 10bfffc4 addi r2,r2,-1 + 1016f98: e0bff715 stw r2,-36(fp) + + /* Add the next character to the transmit buffer */ + + sp->tx_buf[sp->tx_end] = *ptr++; + 1016f9c: e0bffc17 ldw r2,-16(fp) + 1016fa0: 10c00517 ldw r3,20(r2) + 1016fa4: e0bffd17 ldw r2,-12(fp) + 1016fa8: 10800003 ldbu r2,0(r2) + 1016fac: 1009883a mov r4,r2 + 1016fb0: e0bffc17 ldw r2,-16(fp) + 1016fb4: 1885883a add r2,r3,r2 + 1016fb8: 10801a04 addi r2,r2,104 + 1016fbc: 11000005 stb r4,0(r2) + 1016fc0: e0bffd17 ldw r2,-12(fp) + 1016fc4: 10800044 addi r2,r2,1 + 1016fc8: e0bffd15 stw r2,-12(fp) + sp->tx_end = next; + 1016fcc: e0fffc17 ldw r3,-16(fp) + 1016fd0: e0bff817 ldw r2,-32(fp) + 1016fd4: 18800515 stw r2,20(r3) + * Loop transferring data from the input buffer to the transmit circular + * buffer. The loop is terminated once all the data has been transferred, + * or, (if in non-blocking mode) the buffer becomes full. + */ + + while (count) + 1016fd8: e0bff717 ldw r2,-36(fp) + 1016fdc: 1004c03a cmpne r2,r2,zero + 1016fe0: 103fa81e bne r2,zero,1016e84 + /* + * Now that access to the circular buffer is complete, release the write + * semaphore so that other threads can access the buffer. + */ + + ALT_SEM_POST (sp->write_lock); + 1016fe4: e0bffc17 ldw r2,-16(fp) + 1016fe8: 11000917 ldw r4,36(r2) + 1016fec: 10132100 call 1013210 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1016ff0: 0005303a rdctl r2,status + 1016ff4: e0bfef15 stw r2,-68(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1016ff8: e0ffef17 ldw r3,-68(fp) + 1016ffc: 00bfff84 movi r2,-2 + 1017000: 1884703a and r2,r3,r2 + 1017004: 1001703a wrctl status,r2 + + return context; + 1017008: e0bfef17 ldw r2,-68(fp) + /* + * Ensure that interrupts are enabled, so that the circular buffer can + * drain. + */ + + context = alt_irq_disable_all (); + 101700c: e0bffa15 stw r2,-24(fp) + sp->ctrl |= ALTERA_AVALON_UART_CONTROL_TRDY_MSK | + 1017010: e0bffc17 ldw r2,-16(fp) + 1017014: 10800117 ldw r2,4(r2) + 1017018: 10c11014 ori r3,r2,1088 + 101701c: e0bffc17 ldw r2,-16(fp) + 1017020: 10c00115 stw r3,4(r2) + ALTERA_AVALON_UART_CONTROL_DCTS_MSK; + IOWR_ALTERA_AVALON_UART_CONTROL(sp->base, sp->ctrl); + 1017024: e0bffc17 ldw r2,-16(fp) + 1017028: 10800017 ldw r2,0(r2) + 101702c: 11000304 addi r4,r2,12 + 1017030: e0bffc17 ldw r2,-16(fp) + 1017034: 10800117 ldw r2,4(r2) + 1017038: 1007883a mov r3,r2 + 101703c: 2005883a mov r2,r4 + 1017040: 10c00035 stwio r3,0(r2) + 1017044: e0bffa17 ldw r2,-24(fp) + 1017048: e0bfee15 stw r2,-72(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 101704c: e0bfee17 ldw r2,-72(fp) + 1017050: 1001703a wrctl status,r2 + alt_irq_enable_all (context); + + /* return the number of bytes written */ + + return (len - count); + 1017054: e0fffe17 ldw r3,-8(fp) + 1017058: e0bff717 ldw r2,-36(fp) + 101705c: 1885c83a sub r2,r3,r2 +} + 1017060: e037883a mov sp,fp + 1017064: dfc00117 ldw ra,4(sp) + 1017068: df000017 ldw fp,0(sp) + 101706c: dec00204 addi sp,sp,8 + 1017070: f800283a ret + +01017074 : +#undef errno + +extern int errno; + +static ALT_INLINE int* alt_get_errno(void) +{ + 1017074: defffd04 addi sp,sp,-12 + 1017078: dfc00215 stw ra,8(sp) + 101707c: df000115 stw fp,4(sp) + 1017080: df000104 addi fp,sp,4 + return ((alt_errno) ? alt_errno() : &errno); + 1017084: 008040b4 movhi r2,258 + 1017088: 10aba104 addi r2,r2,-20860 + 101708c: 10800017 ldw r2,0(r2) + 1017090: 1005003a cmpeq r2,r2,zero + 1017094: 1000061e bne r2,zero,10170b0 + 1017098: 008040b4 movhi r2,258 + 101709c: 10aba104 addi r2,r2,-20860 + 10170a0: 10800017 ldw r2,0(r2) + 10170a4: 103ee83a callr r2 + 10170a8: e0bfff15 stw r2,-4(fp) + 10170ac: 00000306 br 10170bc + 10170b0: 008040b4 movhi r2,258 + 10170b4: 10b30404 addi r2,r2,-13296 + 10170b8: e0bfff15 stw r2,-4(fp) + 10170bc: e0bfff17 ldw r2,-4(fp) +} + 10170c0: e037883a mov sp,fp + 10170c4: dfc00117 ldw ra,4(sp) + 10170c8: df000017 ldw fp,0(sp) + 10170cc: dec00204 addi sp,sp,8 + 10170d0: f800283a ret + +010170d4 : +#include "altera_up_avalon_rs232.h" +#include "altera_up_avalon_rs232_regs.h" + + +void alt_up_rs232_enable_read_interrupt(alt_up_rs232_dev *rs232) +{ + 10170d4: defffd04 addi sp,sp,-12 + 10170d8: df000215 stw fp,8(sp) + 10170dc: df000204 addi fp,sp,8 + 10170e0: e13fff15 stw r4,-4(fp) + alt_u32 ctrl_reg; + ctrl_reg = IORD_ALT_UP_RS232_CONTROL(rs232->base); + 10170e4: e0bfff17 ldw r2,-4(fp) + 10170e8: 10800a17 ldw r2,40(r2) + 10170ec: 10800104 addi r2,r2,4 + 10170f0: 10800037 ldwio r2,0(r2) + 10170f4: e0bffe15 stw r2,-8(fp) + // set RE to 1 while maintaining other bits the same + ctrl_reg |= ALT_UP_RS232_CONTROL_RE_MSK; + 10170f8: e0bffe17 ldw r2,-8(fp) + 10170fc: 10800054 ori r2,r2,1 + 1017100: e0bffe15 stw r2,-8(fp) + IOWR_ALT_UP_RS232_CONTROL(rs232->base, ctrl_reg); + 1017104: e0bfff17 ldw r2,-4(fp) + 1017108: 10800a17 ldw r2,40(r2) + 101710c: 10800104 addi r2,r2,4 + 1017110: e0fffe17 ldw r3,-8(fp) + 1017114: 10c00035 stwio r3,0(r2) +} + 1017118: e037883a mov sp,fp + 101711c: df000017 ldw fp,0(sp) + 1017120: dec00104 addi sp,sp,4 + 1017124: f800283a ret + +01017128 : + +void alt_up_rs232_disable_read_interrupt(alt_up_rs232_dev *rs232) +{ + 1017128: defffd04 addi sp,sp,-12 + 101712c: df000215 stw fp,8(sp) + 1017130: df000204 addi fp,sp,8 + 1017134: e13fff15 stw r4,-4(fp) + alt_u32 ctrl_reg; + ctrl_reg = IORD_ALT_UP_RS232_CONTROL(rs232->base); + 1017138: e0bfff17 ldw r2,-4(fp) + 101713c: 10800a17 ldw r2,40(r2) + 1017140: 10800104 addi r2,r2,4 + 1017144: 10800037 ldwio r2,0(r2) + 1017148: e0bffe15 stw r2,-8(fp) + // set RE to 0 while maintaining other bits the same + ctrl_reg &= ~ALT_UP_RS232_CONTROL_RE_MSK; + 101714c: e0fffe17 ldw r3,-8(fp) + 1017150: 00bfff84 movi r2,-2 + 1017154: 1884703a and r2,r3,r2 + 1017158: e0bffe15 stw r2,-8(fp) + IOWR_ALT_UP_RS232_CONTROL(rs232->base, ctrl_reg); + 101715c: e0bfff17 ldw r2,-4(fp) + 1017160: 10800a17 ldw r2,40(r2) + 1017164: 10800104 addi r2,r2,4 + 1017168: e0fffe17 ldw r3,-8(fp) + 101716c: 10c00035 stwio r3,0(r2) +} + 1017170: e037883a mov sp,fp + 1017174: df000017 ldw fp,0(sp) + 1017178: dec00104 addi sp,sp,4 + 101717c: f800283a ret + +01017180 : + +unsigned alt_up_rs232_get_used_space_in_read_FIFO(alt_up_rs232_dev *rs232) +{ + 1017180: defffd04 addi sp,sp,-12 + 1017184: df000215 stw fp,8(sp) + 1017188: df000204 addi fp,sp,8 + 101718c: e13fff15 stw r4,-4(fp) + alt_u16 ravail = 0; + 1017190: e03ffe0d sth zero,-8(fp) + // we can only read the 16 bits for RAVAIL --- a read of DATA will discard the data +// ravail = IORD_16DIRECT(IOADDR_ALT_UP_RS232_DATA(rs232->base), 2); + ravail = IORD_ALT_UP_RS232_RAVAIL(rs232->base); + 1017194: e0bfff17 ldw r2,-4(fp) + 1017198: 10800a17 ldw r2,40(r2) + 101719c: 10800084 addi r2,r2,2 + 10171a0: 1080002b ldhuio r2,0(r2) + 10171a4: e0bffe0d sth r2,-8(fp) +// return ravail; + return (ravail & ALT_UP_RS232_RAVAIL_MSK) >> ALT_UP_RS232_RAVAIL_OFST; + 10171a8: e0bffe0b ldhu r2,-8(fp) +} + 10171ac: e037883a mov sp,fp + 10171b0: df000017 ldw fp,0(sp) + 10171b4: dec00104 addi sp,sp,4 + 10171b8: f800283a ret + +010171bc : + +unsigned alt_up_rs232_get_available_space_in_write_FIFO(alt_up_rs232_dev *rs232) +{ + 10171bc: defffd04 addi sp,sp,-12 + 10171c0: df000215 stw fp,8(sp) + 10171c4: df000204 addi fp,sp,8 + 10171c8: e13fff15 stw r4,-4(fp) + alt_u32 ctrl_reg; + ctrl_reg = IORD_ALT_UP_RS232_CONTROL(rs232->base); + 10171cc: e0bfff17 ldw r2,-4(fp) + 10171d0: 10800a17 ldw r2,40(r2) + 10171d4: 10800104 addi r2,r2,4 + 10171d8: 10800037 ldwio r2,0(r2) + 10171dc: e0bffe15 stw r2,-8(fp) + return (ctrl_reg & ALT_UP_RS232_CONTROL_WSPACE_MSK) >> ALT_UP_RS232_CONTROL_WSPACE_OFST; + 10171e0: e0bffe17 ldw r2,-8(fp) + 10171e4: 10bfffec andhi r2,r2,65535 + 10171e8: 1004d43a srli r2,r2,16 +} + 10171ec: e037883a mov sp,fp + 10171f0: df000017 ldw fp,0(sp) + 10171f4: dec00104 addi sp,sp,4 + 10171f8: f800283a ret + +010171fc : + +int alt_up_rs232_check_parity(alt_u32 data_reg) +{ + 10171fc: defffc04 addi sp,sp,-16 + 1017200: df000315 stw fp,12(sp) + 1017204: df000304 addi fp,sp,12 + 1017208: e13ffe15 stw r4,-8(fp) + unsigned parity_error = (data_reg & ALT_UP_RS232_DATA_PE_MSK) >> ALT_UP_RS232_DATA_PE_OFST; + 101720c: e0bffe17 ldw r2,-8(fp) + 1017210: 1080800c andi r2,r2,512 + 1017214: 1004d27a srli r2,r2,9 + 1017218: e0bffd15 stw r2,-12(fp) + return (parity_error ? -1 : 0); + 101721c: e0bffd17 ldw r2,-12(fp) + 1017220: 1005003a cmpeq r2,r2,zero + 1017224: 1000031e bne r2,zero,1017234 + 1017228: 00bfffc4 movi r2,-1 + 101722c: e0bfff15 stw r2,-4(fp) + 1017230: 00000106 br 1017238 + 1017234: e03fff15 stw zero,-4(fp) + 1017238: e0bfff17 ldw r2,-4(fp) +} + 101723c: e037883a mov sp,fp + 1017240: df000017 ldw fp,0(sp) + 1017244: dec00104 addi sp,sp,4 + 1017248: f800283a ret + +0101724c : + +int alt_up_rs232_write_data(alt_up_rs232_dev *rs232, alt_u8 data) +{ + 101724c: defffc04 addi sp,sp,-16 + 1017250: df000315 stw fp,12(sp) + 1017254: df000304 addi fp,sp,12 + 1017258: e13ffe15 stw r4,-8(fp) + 101725c: e17fff05 stb r5,-4(fp) + alt_u32 data_reg; + data_reg = IORD_ALT_UP_RS232_DATA(rs232->base); + 1017260: e0bffe17 ldw r2,-8(fp) + 1017264: 10800a17 ldw r2,40(r2) + 1017268: 10800037 ldwio r2,0(r2) + 101726c: e0bffd15 stw r2,-12(fp) + + // we can write directly without thinking about other bit fields for this + // case ONLY, because only DATA field of the data register is writable + IOWR_ALT_UP_RS232_DATA(rs232->base, (data>>ALT_UP_RS232_DATA_DATA_OFST) & ALT_UP_RS232_DATA_DATA_MSK); + 1017270: e0bffe17 ldw r2,-8(fp) + 1017274: 10800a17 ldw r2,40(r2) + 1017278: e0ffff03 ldbu r3,-4(fp) + 101727c: 10c00035 stwio r3,0(r2) + return 0; + 1017280: 0005883a mov r2,zero +} + 1017284: e037883a mov sp,fp + 1017288: df000017 ldw fp,0(sp) + 101728c: dec00104 addi sp,sp,4 + 1017290: f800283a ret + +01017294 : + +int alt_up_rs232_read_data(alt_up_rs232_dev *rs232, alt_u8 *data, alt_u8 *parity_error) +{ + 1017294: defffa04 addi sp,sp,-24 + 1017298: dfc00515 stw ra,20(sp) + 101729c: df000415 stw fp,16(sp) + 10172a0: df000404 addi fp,sp,16 + 10172a4: e13ffd15 stw r4,-12(fp) + 10172a8: e17ffe15 stw r5,-8(fp) + 10172ac: e1bfff15 stw r6,-4(fp) + alt_u32 data_reg; + data_reg = IORD_ALT_UP_RS232_DATA(rs232->base); + 10172b0: e0bffd17 ldw r2,-12(fp) + 10172b4: 10800a17 ldw r2,40(r2) + 10172b8: 10800037 ldwio r2,0(r2) + 10172bc: e0bffc15 stw r2,-16(fp) + *data = (data_reg & ALT_UP_RS232_DATA_DATA_MSK) >> ALT_UP_RS232_DATA_DATA_OFST; + 10172c0: e0bffc17 ldw r2,-16(fp) + 10172c4: 1007883a mov r3,r2 + 10172c8: e0bffe17 ldw r2,-8(fp) + 10172cc: 10c00005 stb r3,0(r2) + *parity_error = alt_up_rs232_check_parity(data_reg); + 10172d0: e13ffc17 ldw r4,-16(fp) + 10172d4: 10171fc0 call 10171fc + 10172d8: 1007883a mov r3,r2 + 10172dc: e0bfff17 ldw r2,-4(fp) + 10172e0: 10c00005 stb r3,0(r2) + return (((data_reg & ALT_UP_RS232_DATA_RVALID_MSK) >> ALT_UP_RS232_DATA_RVALID_OFST) - 1); + 10172e4: e0bffc17 ldw r2,-16(fp) + 10172e8: 10a0000c andi r2,r2,32768 + 10172ec: 1004d3fa srli r2,r2,15 + 10172f0: 10bfffc4 addi r2,r2,-1 +} + 10172f4: e037883a mov sp,fp + 10172f8: dfc00117 ldw ra,4(sp) + 10172fc: df000017 ldw fp,0(sp) + 1017300: dec00204 addi sp,sp,8 + 1017304: f800283a ret + +01017308 : + +int alt_up_rs232_read_fd (alt_fd* fd, char* ptr, int len) +{ + 1017308: defff804 addi sp,sp,-32 + 101730c: dfc00715 stw ra,28(sp) + 1017310: df000615 stw fp,24(sp) + 1017314: df000604 addi fp,sp,24 + 1017318: e13ffd15 stw r4,-12(fp) + 101731c: e17ffe15 stw r5,-8(fp) + 1017320: e1bfff15 stw r6,-4(fp) + alt_up_rs232_dev *rs232 = (alt_up_rs232_dev*)fd->dev; + 1017324: e0bffd17 ldw r2,-12(fp) + 1017328: 10800017 ldw r2,0(r2) + 101732c: e0bffb15 stw r2,-20(fp) + int count = 0; + 1017330: e03ffa15 stw zero,-24(fp) + alt_u8 parity_error; + while(len--) + 1017334: 00000c06 br 1017368 + { + if (alt_up_rs232_read_data(rs232, ptr++, &parity_error)==0) + 1017338: e17ffe17 ldw r5,-8(fp) + 101733c: e0bffe17 ldw r2,-8(fp) + 1017340: 10800044 addi r2,r2,1 + 1017344: e0bffe15 stw r2,-8(fp) + 1017348: e1bffc04 addi r6,fp,-16 + 101734c: e13ffb17 ldw r4,-20(fp) + 1017350: 10172940 call 1017294 + 1017354: 1004c03a cmpne r2,r2,zero + 1017358: 1000091e bne r2,zero,1017380 + count++; + 101735c: e0bffa17 ldw r2,-24(fp) + 1017360: 10800044 addi r2,r2,1 + 1017364: e0bffa15 stw r2,-24(fp) +int alt_up_rs232_read_fd (alt_fd* fd, char* ptr, int len) +{ + alt_up_rs232_dev *rs232 = (alt_up_rs232_dev*)fd->dev; + int count = 0; + alt_u8 parity_error; + while(len--) + 1017368: e0bfff17 ldw r2,-4(fp) + 101736c: 10bfffc4 addi r2,r2,-1 + 1017370: e0bfff15 stw r2,-4(fp) + 1017374: e0bfff17 ldw r2,-4(fp) + 1017378: 10bfffd8 cmpnei r2,r2,-1 + 101737c: 103fee1e bne r2,zero,1017338 + if (alt_up_rs232_read_data(rs232, ptr++, &parity_error)==0) + count++; + else + break; + } + return count; + 1017380: e0bffa17 ldw r2,-24(fp) +} + 1017384: e037883a mov sp,fp + 1017388: dfc00117 ldw ra,4(sp) + 101738c: df000017 ldw fp,0(sp) + 1017390: dec00204 addi sp,sp,8 + 1017394: f800283a ret + +01017398 : + +int alt_up_rs232_write_fd (alt_fd* fd, const char* ptr, int len) +{ + 1017398: defff904 addi sp,sp,-28 + 101739c: dfc00615 stw ra,24(sp) + 10173a0: df000515 stw fp,20(sp) + 10173a4: df000504 addi fp,sp,20 + 10173a8: e13ffd15 stw r4,-12(fp) + 10173ac: e17ffe15 stw r5,-8(fp) + 10173b0: e1bfff15 stw r6,-4(fp) + alt_up_rs232_dev *rs232 = (alt_up_rs232_dev*)fd->dev; + 10173b4: e0bffd17 ldw r2,-12(fp) + 10173b8: 10800017 ldw r2,0(r2) + 10173bc: e0bffc15 stw r2,-16(fp) + int count = 0; + 10173c0: e03ffb15 stw zero,-20(fp) + while(len--) + 10173c4: 00000d06 br 10173fc + { + if (alt_up_rs232_write_data(rs232, *ptr)==0) + 10173c8: e0bffe17 ldw r2,-8(fp) + 10173cc: 10800003 ldbu r2,0(r2) + 10173d0: 11403fcc andi r5,r2,255 + 10173d4: e13ffc17 ldw r4,-16(fp) + 10173d8: 101724c0 call 101724c + 10173dc: 1004c03a cmpne r2,r2,zero + 10173e0: 10000c1e bne r2,zero,1017414 + { + count++; + 10173e4: e0bffb17 ldw r2,-20(fp) + 10173e8: 10800044 addi r2,r2,1 + 10173ec: e0bffb15 stw r2,-20(fp) + ptr++; + 10173f0: e0bffe17 ldw r2,-8(fp) + 10173f4: 10800044 addi r2,r2,1 + 10173f8: e0bffe15 stw r2,-8(fp) + +int alt_up_rs232_write_fd (alt_fd* fd, const char* ptr, int len) +{ + alt_up_rs232_dev *rs232 = (alt_up_rs232_dev*)fd->dev; + int count = 0; + while(len--) + 10173fc: e0bfff17 ldw r2,-4(fp) + 1017400: 10bfffc4 addi r2,r2,-1 + 1017404: e0bfff15 stw r2,-4(fp) + 1017408: e0bfff17 ldw r2,-4(fp) + 101740c: 10bfffd8 cmpnei r2,r2,-1 + 1017410: 103fed1e bne r2,zero,10173c8 + ptr++; + } + else + break; + } + return count; + 1017414: e0bffb17 ldw r2,-20(fp) +} + 1017418: e037883a mov sp,fp + 101741c: dfc00117 ldw ra,4(sp) + 1017420: df000017 ldw fp,0(sp) + 1017424: dec00204 addi sp,sp,8 + 1017428: f800283a ret + +0101742c : + +alt_up_rs232_dev* alt_up_rs232_open_dev(const char* name) +{ + 101742c: defffc04 addi sp,sp,-16 + 1017430: dfc00315 stw ra,12(sp) + 1017434: df000215 stw fp,8(sp) + 1017438: df000204 addi fp,sp,8 + 101743c: e13fff15 stw r4,-4(fp) + // find the device from the device list + // (see altera_hal/HAL/inc/priv/alt_file.h + // and altera_hal/HAL/src/alt_find_dev.c + // for details) + alt_up_rs232_dev *dev = (alt_up_rs232_dev*)alt_find_dev(name, &alt_dev_list); + 1017440: e13fff17 ldw r4,-4(fp) + 1017444: 014040b4 movhi r5,258 + 1017448: 296b9e04 addi r5,r5,-20872 + 101744c: 10177e00 call 10177e0 + 1017450: e0bffe15 stw r2,-8(fp) + + return dev; + 1017454: e0bffe17 ldw r2,-8(fp) +} + 1017458: e037883a mov sp,fp + 101745c: dfc00117 ldw ra,4(sp) + 1017460: df000017 ldw fp,0(sp) + 1017464: dec00204 addi sp,sp,8 + 1017468: f800283a ret + +0101746c : + */ + +int alt_alarm_start (alt_alarm* alarm, alt_u32 nticks, + alt_u32 (*callback) (void* context), + void* context) +{ + 101746c: defff404 addi sp,sp,-48 + 1017470: df000b15 stw fp,44(sp) + 1017474: df000b04 addi fp,sp,44 + 1017478: e13ffb15 stw r4,-20(fp) + 101747c: e17ffc15 stw r5,-16(fp) + 1017480: e1bffd15 stw r6,-12(fp) + 1017484: e1fffe15 stw r7,-8(fp) + alt_irq_context irq_context; + alt_u32 current_nticks = 0; + 1017488: e03ff915 stw zero,-28(fp) + * Obtain the system clock rate in ticks/s. + */ + +static ALT_INLINE alt_u32 ALT_ALWAYS_INLINE alt_ticks_per_second (void) +{ + return _alt_tick_rate; + 101748c: 008040b4 movhi r2,258 + 1017490: 10b32504 addi r2,r2,-13164 + 1017494: 10800017 ldw r2,0(r2) + + if (alt_ticks_per_second ()) + 1017498: 1005003a cmpeq r2,r2,zero + 101749c: 1000411e bne r2,zero,10175a4 + { + if (alarm) + 10174a0: e0bffb17 ldw r2,-20(fp) + 10174a4: 1005003a cmpeq r2,r2,zero + 10174a8: 10003b1e bne r2,zero,1017598 + { + alarm->callback = callback; + 10174ac: e0fffb17 ldw r3,-20(fp) + 10174b0: e0bffd17 ldw r2,-12(fp) + 10174b4: 18800315 stw r2,12(r3) + alarm->context = context; + 10174b8: e0fffb17 ldw r3,-20(fp) + 10174bc: e0bffe17 ldw r2,-8(fp) + 10174c0: 18800515 stw r2,20(r3) +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 10174c4: 0005303a rdctl r2,status + 10174c8: e0bff815 stw r2,-32(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 10174cc: e0fff817 ldw r3,-32(fp) + 10174d0: 00bfff84 movi r2,-2 + 10174d4: 1884703a and r2,r3,r2 + 10174d8: 1001703a wrctl status,r2 + + return context; + 10174dc: e0bff817 ldw r2,-32(fp) + + irq_context = alt_irq_disable_all (); + 10174e0: e0bffa15 stw r2,-24(fp) + * alt_nticks() returns the elapsed number of system clock ticks since reset. + */ + +static ALT_INLINE alt_u32 ALT_ALWAYS_INLINE alt_nticks (void) +{ + return _alt_nticks; + 10174e4: 008040b4 movhi r2,258 + 10174e8: 10b32604 addi r2,r2,-13160 + 10174ec: 10800017 ldw r2,0(r2) + + current_nticks = alt_nticks(); + 10174f0: e0bff915 stw r2,-28(fp) + + alarm->time = nticks + current_nticks + 1; + 10174f4: e0fffc17 ldw r3,-16(fp) + 10174f8: e0bff917 ldw r2,-28(fp) + 10174fc: 1885883a add r2,r3,r2 + 1017500: 10c00044 addi r3,r2,1 + 1017504: e0bffb17 ldw r2,-20(fp) + 1017508: 10c00215 stw r3,8(r2) + /* + * If the desired alarm time causes a roll-over, set the rollover + * flag. This will prevent the subsequent tick event from causing + * an alarm too early. + */ + if(alarm->time < current_nticks) + 101750c: e0bffb17 ldw r2,-20(fp) + 1017510: 10c00217 ldw r3,8(r2) + 1017514: e0bff917 ldw r2,-28(fp) + 1017518: 1880042e bgeu r3,r2,101752c + { + alarm->rollover = 1; + 101751c: e0fffb17 ldw r3,-20(fp) + 1017520: 00800044 movi r2,1 + 1017524: 18800405 stb r2,16(r3) + 1017528: 00000206 br 1017534 + } + else + { + alarm->rollover = 0; + 101752c: e0bffb17 ldw r2,-20(fp) + 1017530: 10000405 stb zero,16(r2) + } + + alt_llist_insert (&alt_alarm_list, &alarm->llist); + 1017534: e0fffb17 ldw r3,-20(fp) + 1017538: 008040b4 movhi r2,258 + 101753c: 10abc304 addi r2,r2,-20724 + 1017540: e0bff615 stw r2,-40(fp) + 1017544: e0fff715 stw r3,-36(fp) + */ + +static ALT_INLINE void ALT_ALWAYS_INLINE alt_llist_insert(alt_llist* list, + alt_llist* entry) +{ + entry->previous = list; + 1017548: e0fff717 ldw r3,-36(fp) + 101754c: e0bff617 ldw r2,-40(fp) + 1017550: 18800115 stw r2,4(r3) + entry->next = list->next; + 1017554: e0bff617 ldw r2,-40(fp) + 1017558: 10c00017 ldw r3,0(r2) + 101755c: e0bff717 ldw r2,-36(fp) + 1017560: 10c00015 stw r3,0(r2) + + list->next->previous = entry; + 1017564: e0bff617 ldw r2,-40(fp) + 1017568: 10c00017 ldw r3,0(r2) + 101756c: e0bff717 ldw r2,-36(fp) + 1017570: 18800115 stw r2,4(r3) + list->next = entry; + 1017574: e0fff617 ldw r3,-40(fp) + 1017578: e0bff717 ldw r2,-36(fp) + 101757c: 18800015 stw r2,0(r3) + 1017580: e0bffa17 ldw r2,-24(fp) + 1017584: e0bff515 stw r2,-44(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1017588: e0bff517 ldw r2,-44(fp) + 101758c: 1001703a wrctl status,r2 + alt_irq_enable_all (irq_context); + + return 0; + 1017590: e03fff15 stw zero,-4(fp) + 1017594: 00000506 br 10175ac + } + else + { + return -EINVAL; + 1017598: 00bffa84 movi r2,-22 + 101759c: e0bfff15 stw r2,-4(fp) + 10175a0: 00000206 br 10175ac + } + } + else + { + return -ENOTSUP; + 10175a4: 00bfde84 movi r2,-134 + 10175a8: e0bfff15 stw r2,-4(fp) + 10175ac: e0bfff17 ldw r2,-4(fp) + } +} + 10175b0: e037883a mov sp,fp + 10175b4: df000017 ldw fp,0(sp) + 10175b8: dec00104 addi sp,sp,4 + 10175bc: f800283a ret + +010175c0 : +/* + * alt_dcache_flush_all() is called to flush the entire data cache. + */ + +void alt_dcache_flush_all (void) +{ + 10175c0: defffe04 addi sp,sp,-8 + 10175c4: df000115 stw fp,4(sp) + 10175c8: df000104 addi fp,sp,4 +#if NIOS2_DCACHE_SIZE > 0 + char* i; + + for (i = (char*) 0; i < (char*) NIOS2_DCACHE_SIZE; i+= NIOS2_DCACHE_LINE_SIZE) + 10175cc: e03fff15 stw zero,-4(fp) + 10175d0: 00000506 br 10175e8 + { + __asm__ volatile ("flushd (%0)" :: "r" (i)); + 10175d4: e0bfff17 ldw r2,-4(fp) + 10175d8: 1000003b flushd 0(r2) +void alt_dcache_flush_all (void) +{ +#if NIOS2_DCACHE_SIZE > 0 + char* i; + + for (i = (char*) 0; i < (char*) NIOS2_DCACHE_SIZE; i+= NIOS2_DCACHE_LINE_SIZE) + 10175dc: e0bfff17 ldw r2,-4(fp) + 10175e0: 10800804 addi r2,r2,32 + 10175e4: e0bfff15 stw r2,-4(fp) + 10175e8: e0bfff17 ldw r2,-4(fp) + 10175ec: 10840030 cmpltui r2,r2,4096 + 10175f0: 103ff81e bne r2,zero,10175d4 + { + __asm__ volatile ("flushd (%0)" :: "r" (i)); + } +#endif /* NIOS2_DCACHE_SIZE > 0 */ +} + 10175f4: e037883a mov sp,fp + 10175f8: df000017 ldw fp,0(sp) + 10175fc: dec00104 addi sp,sp,4 + 1017600: f800283a ret + +01017604 : +/* + * + */ + +int alt_dev_llist_insert (alt_dev_llist* dev, alt_llist* list) +{ + 1017604: defff904 addi sp,sp,-28 + 1017608: dfc00615 stw ra,24(sp) + 101760c: df000515 stw fp,20(sp) + 1017610: df000504 addi fp,sp,20 + 1017614: e13ffd15 stw r4,-12(fp) + 1017618: e17ffe15 stw r5,-8(fp) + /* + * check that the device exists, and that it has a valid name. + */ + + if (!dev || !dev->name) + 101761c: e0bffd17 ldw r2,-12(fp) + 1017620: 1005003a cmpeq r2,r2,zero + 1017624: 1000041e bne r2,zero,1017638 + 1017628: e0bffd17 ldw r2,-12(fp) + 101762c: 10800217 ldw r2,8(r2) + 1017630: 1004c03a cmpne r2,r2,zero + 1017634: 1000071e bne r2,zero,1017654 + { + ALT_ERRNO = EINVAL; + 1017638: 10176b80 call 10176b8 + 101763c: 1007883a mov r3,r2 + 1017640: 00800584 movi r2,22 + 1017644: 18800015 stw r2,0(r3) + return -EINVAL; + 1017648: 00bffa84 movi r2,-22 + 101764c: e0bfff15 stw r2,-4(fp) + 1017650: 00001306 br 10176a0 + + /* + * register the device. + */ + + alt_llist_insert(list, &dev->llist); + 1017654: e0fffd17 ldw r3,-12(fp) + 1017658: e0bffe17 ldw r2,-8(fp) + 101765c: e0bffb15 stw r2,-20(fp) + 1017660: e0fffc15 stw r3,-16(fp) + */ + +static ALT_INLINE void ALT_ALWAYS_INLINE alt_llist_insert(alt_llist* list, + alt_llist* entry) +{ + entry->previous = list; + 1017664: e0fffc17 ldw r3,-16(fp) + 1017668: e0bffb17 ldw r2,-20(fp) + 101766c: 18800115 stw r2,4(r3) + entry->next = list->next; + 1017670: e0bffb17 ldw r2,-20(fp) + 1017674: 10c00017 ldw r3,0(r2) + 1017678: e0bffc17 ldw r2,-16(fp) + 101767c: 10c00015 stw r3,0(r2) + + list->next->previous = entry; + 1017680: e0bffb17 ldw r2,-20(fp) + 1017684: 10c00017 ldw r3,0(r2) + 1017688: e0bffc17 ldw r2,-16(fp) + 101768c: 18800115 stw r2,4(r3) + list->next = entry; + 1017690: e0fffb17 ldw r3,-20(fp) + 1017694: e0bffc17 ldw r2,-16(fp) + 1017698: 18800015 stw r2,0(r3) + + return 0; + 101769c: e03fff15 stw zero,-4(fp) + 10176a0: e0bfff17 ldw r2,-4(fp) +} + 10176a4: e037883a mov sp,fp + 10176a8: dfc00117 ldw ra,4(sp) + 10176ac: df000017 ldw fp,0(sp) + 10176b0: dec00204 addi sp,sp,8 + 10176b4: f800283a ret + +010176b8 : +#undef errno + +extern int errno; + +static ALT_INLINE int* alt_get_errno(void) +{ + 10176b8: defffd04 addi sp,sp,-12 + 10176bc: dfc00215 stw ra,8(sp) + 10176c0: df000115 stw fp,4(sp) + 10176c4: df000104 addi fp,sp,4 + return ((alt_errno) ? alt_errno() : &errno); + 10176c8: 008040b4 movhi r2,258 + 10176cc: 10aba104 addi r2,r2,-20860 + 10176d0: 10800017 ldw r2,0(r2) + 10176d4: 1005003a cmpeq r2,r2,zero + 10176d8: 1000061e bne r2,zero,10176f4 + 10176dc: 008040b4 movhi r2,258 + 10176e0: 10aba104 addi r2,r2,-20860 + 10176e4: 10800017 ldw r2,0(r2) + 10176e8: 103ee83a callr r2 + 10176ec: e0bfff15 stw r2,-4(fp) + 10176f0: 00000306 br 1017700 + 10176f4: 008040b4 movhi r2,258 + 10176f8: 10b30404 addi r2,r2,-13296 + 10176fc: e0bfff15 stw r2,-4(fp) + 1017700: e0bfff17 ldw r2,-4(fp) +} + 1017704: e037883a mov sp,fp + 1017708: dfc00117 ldw ra,4(sp) + 101770c: df000017 ldw fp,0(sp) + 1017710: dec00204 addi sp,sp,8 + 1017714: f800283a ret + +01017718 <_do_ctors>: +/* + * Run the C++ static constructors. + */ + +void _do_ctors(void) +{ + 1017718: defffd04 addi sp,sp,-12 + 101771c: dfc00215 stw ra,8(sp) + 1017720: df000115 stw fp,4(sp) + 1017724: df000104 addi fp,sp,4 + constructor* ctor; + + for (ctor = &__CTOR_END__[-1]; ctor >= __CTOR_LIST__; ctor--) + 1017728: 00bfff04 movi r2,-4 + 101772c: 00c040b4 movhi r3,258 + 1017730: 18e2f504 addi r3,r3,-29740 + 1017734: 1885883a add r2,r3,r2 + 1017738: e0bfff15 stw r2,-4(fp) + 101773c: 00000606 br 1017758 <_do_ctors+0x40> + (*ctor) (); + 1017740: e0bfff17 ldw r2,-4(fp) + 1017744: 10800017 ldw r2,0(r2) + 1017748: 103ee83a callr r2 + +void _do_ctors(void) +{ + constructor* ctor; + + for (ctor = &__CTOR_END__[-1]; ctor >= __CTOR_LIST__; ctor--) + 101774c: e0bfff17 ldw r2,-4(fp) + 1017750: 10bfff04 addi r2,r2,-4 + 1017754: e0bfff15 stw r2,-4(fp) + 1017758: e0ffff17 ldw r3,-4(fp) + 101775c: 008040b4 movhi r2,258 + 1017760: 10a2f304 addi r2,r2,-29748 + 1017764: 18bff62e bgeu r3,r2,1017740 <_do_ctors+0x28> + (*ctor) (); +} + 1017768: e037883a mov sp,fp + 101776c: dfc00117 ldw ra,4(sp) + 1017770: df000017 ldw fp,0(sp) + 1017774: dec00204 addi sp,sp,8 + 1017778: f800283a ret + +0101777c <_do_dtors>: +/* + * Run the C++ static destructors. + */ + +void _do_dtors(void) +{ + 101777c: defffd04 addi sp,sp,-12 + 1017780: dfc00215 stw ra,8(sp) + 1017784: df000115 stw fp,4(sp) + 1017788: df000104 addi fp,sp,4 + destructor* dtor; + + for (dtor = &__DTOR_END__[-1]; dtor >= __DTOR_LIST__; dtor--) + 101778c: 00bfff04 movi r2,-4 + 1017790: 00c040b4 movhi r3,258 + 1017794: 18e2f504 addi r3,r3,-29740 + 1017798: 1885883a add r2,r3,r2 + 101779c: e0bfff15 stw r2,-4(fp) + 10177a0: 00000606 br 10177bc <_do_dtors+0x40> + (*dtor) (); + 10177a4: e0bfff17 ldw r2,-4(fp) + 10177a8: 10800017 ldw r2,0(r2) + 10177ac: 103ee83a callr r2 + +void _do_dtors(void) +{ + destructor* dtor; + + for (dtor = &__DTOR_END__[-1]; dtor >= __DTOR_LIST__; dtor--) + 10177b0: e0bfff17 ldw r2,-4(fp) + 10177b4: 10bfff04 addi r2,r2,-4 + 10177b8: e0bfff15 stw r2,-4(fp) + 10177bc: e0ffff17 ldw r3,-4(fp) + 10177c0: 008040b4 movhi r2,258 + 10177c4: 10a2f504 addi r2,r2,-29740 + 10177c8: 18bff62e bgeu r3,r2,10177a4 <_do_dtors+0x28> + (*dtor) (); +} + 10177cc: e037883a mov sp,fp + 10177d0: dfc00117 ldw ra,4(sp) + 10177d4: df000017 ldw fp,0(sp) + 10177d8: dec00204 addi sp,sp,8 + 10177dc: f800283a ret + +010177e0 : + * "name" must be an exact match for the devices registered name for a match to + * be found. + */ + +alt_dev* alt_find_dev(const char* name, alt_llist* llist) +{ + 10177e0: defff904 addi sp,sp,-28 + 10177e4: dfc00615 stw ra,24(sp) + 10177e8: df000515 stw fp,20(sp) + 10177ec: df000504 addi fp,sp,20 + 10177f0: e13ffd15 stw r4,-12(fp) + 10177f4: e17ffe15 stw r5,-8(fp) + alt_dev* next = (alt_dev*) llist->next; + 10177f8: e0bffe17 ldw r2,-8(fp) + 10177fc: 10800017 ldw r2,0(r2) + 1017800: e0bffc15 stw r2,-16(fp) + alt_32 len; + + len = strlen(name) + 1; + 1017804: e13ffd17 ldw r4,-12(fp) + 1017808: 10034a00 call 10034a0 + 101780c: 10800044 addi r2,r2,1 + 1017810: e0bffb15 stw r2,-20(fp) + /* + * Check each list entry in turn, until a match is found, or we reach the + * end of the list (i.e. next winds up pointing back to the list head). + */ + + while (next != (alt_dev*) llist) + 1017814: 00000d06 br 101784c + /* + * memcmp() is used here rather than strcmp() in order to reduce the size + * of the executable. + */ + + if (!memcmp (next->name, name, len)) + 1017818: e0bffc17 ldw r2,-16(fp) + 101781c: 11000217 ldw r4,8(r2) + 1017820: e1bffb17 ldw r6,-20(fp) + 1017824: e17ffd17 ldw r5,-12(fp) + 1017828: 10188040 call 1018804 + 101782c: 1004c03a cmpne r2,r2,zero + 1017830: 1000031e bne r2,zero,1017840 + { + /* match found */ + + return next; + 1017834: e0bffc17 ldw r2,-16(fp) + 1017838: e0bfff15 stw r2,-4(fp) + 101783c: 00000706 br 101785c + } + next = (alt_dev*) next->llist.next; + 1017840: e0bffc17 ldw r2,-16(fp) + 1017844: 10800017 ldw r2,0(r2) + 1017848: e0bffc15 stw r2,-16(fp) + /* + * Check each list entry in turn, until a match is found, or we reach the + * end of the list (i.e. next winds up pointing back to the list head). + */ + + while (next != (alt_dev*) llist) + 101784c: e0fffe17 ldw r3,-8(fp) + 1017850: e0bffc17 ldw r2,-16(fp) + 1017854: 10fff01e bne r2,r3,1017818 + next = (alt_dev*) next->llist.next; + } + + /* No match found */ + + return NULL; + 1017858: e03fff15 stw zero,-4(fp) + 101785c: e0bfff17 ldw r2,-4(fp) +} + 1017860: e037883a mov sp,fp + 1017864: dfc00117 ldw ra,4(sp) + 1017868: df000017 ldw fp,0(sp) + 101786c: dec00204 addi sp,sp,8 + 1017870: f800283a ret + +01017874 : +/* + * alt_icache_flush_all() is called to flush the entire instruction cache. + */ + +void alt_icache_flush_all (void) +{ + 1017874: defffe04 addi sp,sp,-8 + 1017878: dfc00115 stw ra,4(sp) + 101787c: df000015 stw fp,0(sp) + 1017880: d839883a mov fp,sp +#if NIOS2_ICACHE_SIZE > 0 + alt_icache_flush (0, NIOS2_ICACHE_SIZE); + 1017884: 0009883a mov r4,zero + 1017888: 01480004 movi r5,8192 + 101788c: 10187280 call 1018728 +#endif +} + 1017890: e037883a mov sp,fp + 1017894: dfc00117 ldw ra,4(sp) + 1017898: df000017 ldw fp,0(sp) + 101789c: dec00204 addi sp,sp,8 + 10178a0: f800283a ret + +010178a4 : + * If the device can not be succesfully opened, then the input file descriptor + * remains unchanged. + */ + +static void alt_open_fd(alt_fd* fd, const char* name, int flags, int mode) +{ + 10178a4: defff904 addi sp,sp,-28 + 10178a8: dfc00615 stw ra,24(sp) + 10178ac: df000515 stw fp,20(sp) + 10178b0: df000504 addi fp,sp,20 + 10178b4: e13ffc15 stw r4,-16(fp) + 10178b8: e17ffd15 stw r5,-12(fp) + 10178bc: e1bffe15 stw r6,-8(fp) + 10178c0: e1ffff15 stw r7,-4(fp) + int old; + + old = open (name, flags, mode); + 10178c4: e13ffd17 ldw r4,-12(fp) + 10178c8: e17ffe17 ldw r5,-8(fp) + 10178cc: e1bfff17 ldw r6,-4(fp) + 10178d0: 1017c7c0 call 1017c7c + 10178d4: e0bffb15 stw r2,-20(fp) + + if (old >= 0) + 10178d8: e0bffb17 ldw r2,-20(fp) + 10178dc: 1004803a cmplt r2,r2,zero + 10178e0: 10001c1e bne r2,zero,1017954 + { + fd->dev = alt_fd_list[old].dev; + 10178e4: e0bffb17 ldw r2,-20(fp) + 10178e8: 00c040b4 movhi r3,258 + 10178ec: 18e69f04 addi r3,r3,-25988 + 10178f0: 10800324 muli r2,r2,12 + 10178f4: 10c5883a add r2,r2,r3 + 10178f8: 10c00017 ldw r3,0(r2) + 10178fc: e0bffc17 ldw r2,-16(fp) + 1017900: 10c00015 stw r3,0(r2) + fd->priv = alt_fd_list[old].priv; + 1017904: e0bffb17 ldw r2,-20(fp) + 1017908: 00c040b4 movhi r3,258 + 101790c: 18e69f04 addi r3,r3,-25988 + 1017910: 10800324 muli r2,r2,12 + 1017914: 10c5883a add r2,r2,r3 + 1017918: 10800104 addi r2,r2,4 + 101791c: 10c00017 ldw r3,0(r2) + 1017920: e0bffc17 ldw r2,-16(fp) + 1017924: 10c00115 stw r3,4(r2) + fd->fd_flags = alt_fd_list[old].fd_flags; + 1017928: e0bffb17 ldw r2,-20(fp) + 101792c: 00c040b4 movhi r3,258 + 1017930: 18e69f04 addi r3,r3,-25988 + 1017934: 10800324 muli r2,r2,12 + 1017938: 10c5883a add r2,r2,r3 + 101793c: 10800204 addi r2,r2,8 + 1017940: 10c00017 ldw r3,0(r2) + 1017944: e0bffc17 ldw r2,-16(fp) + 1017948: 10c00215 stw r3,8(r2) + + alt_release_fd (old); + 101794c: e13ffb17 ldw r4,-20(fp) + 1017950: 100ccfc0 call 100ccfc + } +} + 1017954: e037883a mov sp,fp + 1017958: dfc00117 ldw ra,4(sp) + 101795c: df000017 ldw fp,0(sp) + 1017960: dec00204 addi sp,sp,8 + 1017964: f800283a ret + +01017968 : + */ + +void alt_io_redirect(const char* stdout_dev, + const char* stdin_dev, + const char* stderr_dev) +{ + 1017968: defffb04 addi sp,sp,-20 + 101796c: dfc00415 stw ra,16(sp) + 1017970: df000315 stw fp,12(sp) + 1017974: df000304 addi fp,sp,12 + 1017978: e13ffd15 stw r4,-12(fp) + 101797c: e17ffe15 stw r5,-8(fp) + 1017980: e1bfff15 stw r6,-4(fp) + /* Redirect the channels */ + + alt_open_fd (&alt_fd_list[STDOUT_FILENO], stdout_dev, O_WRONLY, 0777); + 1017984: 010040b4 movhi r4,258 + 1017988: 2126a204 addi r4,r4,-25976 + 101798c: e17ffd17 ldw r5,-12(fp) + 1017990: 01800044 movi r6,1 + 1017994: 01c07fc4 movi r7,511 + 1017998: 10178a40 call 10178a4 + alt_open_fd (&alt_fd_list[STDIN_FILENO], stdin_dev, O_RDONLY, 0777); + 101799c: 010040b4 movhi r4,258 + 10179a0: 21269f04 addi r4,r4,-25988 + 10179a4: e17ffe17 ldw r5,-8(fp) + 10179a8: 000d883a mov r6,zero + 10179ac: 01c07fc4 movi r7,511 + 10179b0: 10178a40 call 10178a4 + alt_open_fd (&alt_fd_list[STDERR_FILENO], stderr_dev, O_WRONLY, 0777); + 10179b4: 010040b4 movhi r4,258 + 10179b8: 2126a504 addi r4,r4,-25964 + 10179bc: e17fff17 ldw r5,-4(fp) + 10179c0: 01800044 movi r6,1 + 10179c4: 01c07fc4 movi r7,511 + 10179c8: 10178a40 call 10178a4 +} + 10179cc: e037883a mov sp,fp + 10179d0: dfc00117 ldw ra,4(sp) + 10179d4: df000017 ldw fp,0(sp) + 10179d8: dec00204 addi sp,sp,8 + 10179dc: f800283a ret + +010179e0 : + */ + +int alt_irq_register (alt_u32 id, + void* context, + alt_isr_func handler) +{ + 10179e0: deffef04 addi sp,sp,-68 + 10179e4: df001015 stw fp,64(sp) + 10179e8: df001004 addi fp,sp,64 + 10179ec: e13ffc15 stw r4,-16(fp) + 10179f0: e17ffd15 stw r5,-12(fp) + 10179f4: e1bffe15 stw r6,-8(fp) + int rc = -EINVAL; + 10179f8: 00bffa84 movi r2,-22 + 10179fc: e0bffb15 stw r2,-20(fp) + alt_irq_context status; + + if (id < ALT_NIRQ) + 1017a00: e0bffc17 ldw r2,-16(fp) + 1017a04: 10800828 cmpgeui r2,r2,32 + 1017a08: 1000601e bne r2,zero,1017b8c +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1017a0c: 0005303a rdctl r2,status + 1017a10: e0bff915 stw r2,-28(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1017a14: e0fff917 ldw r3,-28(fp) + 1017a18: 00bfff84 movi r2,-2 + 1017a1c: 1884703a and r2,r3,r2 + 1017a20: 1001703a wrctl status,r2 + + return context; + 1017a24: e0bff917 ldw r2,-28(fp) + * interrupts are disabled while the handler tables are updated to ensure + * that an interrupt doesn't occur while the tables are in an inconsistant + * state. + */ + + status = alt_irq_disable_all (); + 1017a28: e0bffa15 stw r2,-24(fp) + + alt_irq[id].handler = handler; + 1017a2c: e0bffc17 ldw r2,-16(fp) + 1017a30: 00c040b4 movhi r3,258 + 1017a34: 18d9be04 addi r3,r3,26360 + 1017a38: 100490fa slli r2,r2,3 + 1017a3c: 10c7883a add r3,r2,r3 + 1017a40: e0bffe17 ldw r2,-8(fp) + 1017a44: 18800015 stw r2,0(r3) + alt_irq[id].context = context; + 1017a48: e0bffc17 ldw r2,-16(fp) + 1017a4c: 00c040b4 movhi r3,258 + 1017a50: 18d9be04 addi r3,r3,26360 + 1017a54: 100490fa slli r2,r2,3 + 1017a58: 10c5883a add r2,r2,r3 + 1017a5c: 10c00104 addi r3,r2,4 + 1017a60: e0bffd17 ldw r2,-12(fp) + 1017a64: 18800015 stw r2,0(r3) + + rc = (handler) ? alt_irq_enable (id): alt_irq_disable (id); + 1017a68: e0bffe17 ldw r2,-8(fp) + 1017a6c: 1005003a cmpeq r2,r2,zero + 1017a70: 1000201e bne r2,zero,1017af4 + 1017a74: e0bffc17 ldw r2,-16(fp) + 1017a78: e0bff715 stw r2,-36(fp) +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1017a7c: 0005303a rdctl r2,status + 1017a80: e0bff615 stw r2,-40(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1017a84: e0fff617 ldw r3,-40(fp) + 1017a88: 00bfff84 movi r2,-2 + 1017a8c: 1884703a and r2,r3,r2 + 1017a90: 1001703a wrctl status,r2 + + return context; + 1017a94: e0bff617 ldw r2,-40(fp) +static ALT_INLINE int ALT_ALWAYS_INLINE alt_irq_enable (alt_u32 id) +{ + alt_irq_context status; + extern volatile alt_u32 alt_irq_active; + + status = alt_irq_disable_all (); + 1017a98: e0bff815 stw r2,-32(fp) + + alt_irq_active |= (1 << id); + 1017a9c: e0fff717 ldw r3,-36(fp) + 1017aa0: 00800044 movi r2,1 + 1017aa4: 10c4983a sll r2,r2,r3 + 1017aa8: 1007883a mov r3,r2 + 1017aac: 008040b4 movhi r2,258 + 1017ab0: 10b32404 addi r2,r2,-13168 + 1017ab4: 10800017 ldw r2,0(r2) + 1017ab8: 1886b03a or r3,r3,r2 + 1017abc: 008040b4 movhi r2,258 + 1017ac0: 10b32404 addi r2,r2,-13168 + 1017ac4: 10c00015 stw r3,0(r2) + NIOS2_WRITE_IENABLE (alt_irq_active); + 1017ac8: 008040b4 movhi r2,258 + 1017acc: 10b32404 addi r2,r2,-13168 + 1017ad0: 10800017 ldw r2,0(r2) + 1017ad4: 100170fa wrctl ienable,r2 + 1017ad8: e0bff817 ldw r2,-32(fp) + 1017adc: e0bff515 stw r2,-44(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1017ae0: e0bff517 ldw r2,-44(fp) + 1017ae4: 1001703a wrctl status,r2 + + alt_irq_enable_all(status); + + return 0; + 1017ae8: 0005883a mov r2,zero + 1017aec: e0bfff15 stw r2,-4(fp) + 1017af0: 00002006 br 1017b74 + 1017af4: e0bffc17 ldw r2,-16(fp) + 1017af8: e0bff315 stw r2,-52(fp) +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1017afc: 0005303a rdctl r2,status + 1017b00: e0bff215 stw r2,-56(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1017b04: e0fff217 ldw r3,-56(fp) + 1017b08: 00bfff84 movi r2,-2 + 1017b0c: 1884703a and r2,r3,r2 + 1017b10: 1001703a wrctl status,r2 + + return context; + 1017b14: e0bff217 ldw r2,-56(fp) +static ALT_INLINE int ALT_ALWAYS_INLINE alt_irq_disable (alt_u32 id) +{ + alt_irq_context status; + extern volatile alt_u32 alt_irq_active; + + status = alt_irq_disable_all (); + 1017b18: e0bff415 stw r2,-48(fp) + + alt_irq_active &= ~(1 << id); + 1017b1c: e0fff317 ldw r3,-52(fp) + 1017b20: 00800044 movi r2,1 + 1017b24: 10c4983a sll r2,r2,r3 + 1017b28: 0084303a nor r2,zero,r2 + 1017b2c: 1007883a mov r3,r2 + 1017b30: 008040b4 movhi r2,258 + 1017b34: 10b32404 addi r2,r2,-13168 + 1017b38: 10800017 ldw r2,0(r2) + 1017b3c: 1886703a and r3,r3,r2 + 1017b40: 008040b4 movhi r2,258 + 1017b44: 10b32404 addi r2,r2,-13168 + 1017b48: 10c00015 stw r3,0(r2) + NIOS2_WRITE_IENABLE (alt_irq_active); + 1017b4c: 008040b4 movhi r2,258 + 1017b50: 10b32404 addi r2,r2,-13168 + 1017b54: 10800017 ldw r2,0(r2) + 1017b58: 100170fa wrctl ienable,r2 + 1017b5c: e0bff417 ldw r2,-48(fp) + 1017b60: e0bff115 stw r2,-60(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1017b64: e0bff117 ldw r2,-60(fp) + 1017b68: 1001703a wrctl status,r2 + + alt_irq_enable_all(status); + + return 0; + 1017b6c: 0005883a mov r2,zero + 1017b70: e0bfff15 stw r2,-4(fp) + 1017b74: e0bfff17 ldw r2,-4(fp) + 1017b78: e0bffb15 stw r2,-20(fp) + 1017b7c: e0bffa17 ldw r2,-24(fp) + 1017b80: e0bff015 stw r2,-64(fp) + 1017b84: e0bff017 ldw r2,-64(fp) + 1017b88: 1001703a wrctl status,r2 + + alt_irq_enable_all(status); + } + return rc; + 1017b8c: e0bffb17 ldw r2,-20(fp) +} + 1017b90: e037883a mov sp,fp + 1017b94: df000017 ldw fp,0(sp) + 1017b98: dec00104 addi sp,sp,4 + 1017b9c: f800283a ret + +01017ba0 : + * performed for devices. Filesystems are required to handle the ioctl() call + * themselves, and report the error from the filesystems open() function. + */ + +static int alt_file_locked (alt_fd* fd) +{ + 1017ba0: defffc04 addi sp,sp,-16 + 1017ba4: df000315 stw fp,12(sp) + 1017ba8: df000304 addi fp,sp,12 + 1017bac: e13ffe15 stw r4,-8(fp) + + /* + * Mark the file descriptor as belonging to a device. + */ + + fd->fd_flags |= ALT_FD_DEV; + 1017bb0: e0bffe17 ldw r2,-8(fp) + 1017bb4: 10800217 ldw r2,8(r2) + 1017bb8: 10d00034 orhi r3,r2,16384 + 1017bbc: e0bffe17 ldw r2,-8(fp) + 1017bc0: 10c00215 stw r3,8(r2) + /* + * Loop through all current file descriptors searching for one that's locked + * for exclusive access. If a match is found, generate an error. + */ + + for (i = 0; i <= alt_max_fd; i++) + 1017bc4: e03ffd15 stw zero,-12(fp) + 1017bc8: 00002006 br 1017c4c + { + if ((alt_fd_list[i].dev == fd->dev) && + 1017bcc: e0bffd17 ldw r2,-12(fp) + 1017bd0: 00c040b4 movhi r3,258 + 1017bd4: 18e69f04 addi r3,r3,-25988 + 1017bd8: 10800324 muli r2,r2,12 + 1017bdc: 10c5883a add r2,r2,r3 + 1017be0: 10c00017 ldw r3,0(r2) + 1017be4: e0bffe17 ldw r2,-8(fp) + 1017be8: 10800017 ldw r2,0(r2) + 1017bec: 1880141e bne r3,r2,1017c40 + 1017bf0: e0bffd17 ldw r2,-12(fp) + 1017bf4: 00c040b4 movhi r3,258 + 1017bf8: 18e69f04 addi r3,r3,-25988 + 1017bfc: 10800324 muli r2,r2,12 + 1017c00: 10c5883a add r2,r2,r3 + 1017c04: 10800204 addi r2,r2,8 + 1017c08: 10800017 ldw r2,0(r2) + 1017c0c: 1004403a cmpge r2,r2,zero + 1017c10: 10000b1e bne r2,zero,1017c40 + 1017c14: e0bffd17 ldw r2,-12(fp) + 1017c18: 10800324 muli r2,r2,12 + 1017c1c: 1007883a mov r3,r2 + 1017c20: 008040b4 movhi r2,258 + 1017c24: 10a69f04 addi r2,r2,-25988 + 1017c28: 1887883a add r3,r3,r2 + 1017c2c: e0bffe17 ldw r2,-8(fp) + 1017c30: 18800326 beq r3,r2,1017c40 + (alt_fd_list[i].fd_flags & ALT_FD_EXCL) && + (&alt_fd_list[i] != fd)) + { + return -EACCES; + 1017c34: 00bffcc4 movi r2,-13 + 1017c38: e0bfff15 stw r2,-4(fp) + 1017c3c: 00000a06 br 1017c68 + /* + * Loop through all current file descriptors searching for one that's locked + * for exclusive access. If a match is found, generate an error. + */ + + for (i = 0; i <= alt_max_fd; i++) + 1017c40: e0bffd17 ldw r2,-12(fp) + 1017c44: 10800044 addi r2,r2,1 + 1017c48: e0bffd15 stw r2,-12(fp) + 1017c4c: 008040b4 movhi r2,258 + 1017c50: 10aba004 addi r2,r2,-20864 + 1017c54: 10800017 ldw r2,0(r2) + 1017c58: 1007883a mov r3,r2 + 1017c5c: e0bffd17 ldw r2,-12(fp) + 1017c60: 18bfda2e bgeu r3,r2,1017bcc + } + } + + /* The device is not locked */ + + return 0; + 1017c64: e03fff15 stw zero,-4(fp) + 1017c68: e0bfff17 ldw r2,-4(fp) +} + 1017c6c: e037883a mov sp,fp + 1017c70: df000017 ldw fp,0(sp) + 1017c74: dec00104 addi sp,sp,4 + 1017c78: f800283a ret + +01017c7c : + * + * ALT_OPEN is mapped onto the open() system call in alt_syscall.h + */ + +int ALT_OPEN (const char* file, int flags, int mode) +{ + 1017c7c: defff404 addi sp,sp,-48 + 1017c80: dfc00b15 stw ra,44(sp) + 1017c84: df000a15 stw fp,40(sp) + 1017c88: df000a04 addi fp,sp,40 + 1017c8c: e13ffb15 stw r4,-20(fp) + 1017c90: e17ffc15 stw r5,-16(fp) + 1017c94: e1bffd15 stw r6,-12(fp) + alt_dev* dev; + alt_fd* fd; + int index = -1; + 1017c98: 00bfffc4 movi r2,-1 + 1017c9c: e0bff815 stw r2,-32(fp) + int status = -ENODEV; + 1017ca0: 00bffb44 movi r2,-19 + 1017ca4: e0bff715 stw r2,-36(fp) + int isafs = 0; + 1017ca8: e03ff615 stw zero,-40(fp) + /* + * Check the device list, to see if a device with a matching name is + * registered. + */ + + if (!(dev = alt_find_dev (file, &alt_dev_list))) + 1017cac: e13ffb17 ldw r4,-20(fp) + 1017cb0: 014040b4 movhi r5,258 + 1017cb4: 296b9e04 addi r5,r5,-20872 + 1017cb8: 10177e00 call 10177e0 + 1017cbc: e0bffa15 stw r2,-24(fp) + 1017cc0: e0bffa17 ldw r2,-24(fp) + 1017cc4: 1004c03a cmpne r2,r2,zero + 1017cc8: 1000051e bne r2,zero,1017ce0 + { + /* No matching device, so try the filesystem list */ + + dev = alt_find_file (file); + 1017ccc: e13ffb17 ldw r4,-20(fp) + 1017cd0: 10185140 call 1018514 + 1017cd4: e0bffa15 stw r2,-24(fp) + isafs = 1; + 1017cd8: 00800044 movi r2,1 + 1017cdc: e0bff615 stw r2,-40(fp) + + /* + * If a matching device or filesystem is found, allocate a file descriptor. + */ + + if (dev) + 1017ce0: e0bffa17 ldw r2,-24(fp) + 1017ce4: 1005003a cmpeq r2,r2,zero + 1017ce8: 1000301e bne r2,zero,1017dac + { + if ((index = alt_get_fd (dev)) < 0) + 1017cec: e13ffa17 ldw r4,-24(fp) + 1017cf0: 10186340 call 1018634 + 1017cf4: e0bff815 stw r2,-32(fp) + 1017cf8: e0bff817 ldw r2,-32(fp) + 1017cfc: 1004403a cmpge r2,r2,zero + 1017d00: 1000031e bne r2,zero,1017d10 + { + status = index; + 1017d04: e0bff817 ldw r2,-32(fp) + 1017d08: e0bff715 stw r2,-36(fp) + 1017d0c: 00002906 br 1017db4 + } + else + { + fd = &alt_fd_list[index]; + 1017d10: e0bff817 ldw r2,-32(fp) + 1017d14: 10800324 muli r2,r2,12 + 1017d18: 1007883a mov r3,r2 + 1017d1c: 008040b4 movhi r2,258 + 1017d20: 10a69f04 addi r2,r2,-25988 + 1017d24: 1885883a add r2,r3,r2 + 1017d28: e0bff915 stw r2,-28(fp) + fd->fd_flags = (flags & ~ALT_FD_FLAGS_MASK); + 1017d2c: e0fffc17 ldw r3,-16(fp) + 1017d30: 00900034 movhi r2,16384 + 1017d34: 10bfffc4 addi r2,r2,-1 + 1017d38: 1886703a and r3,r3,r2 + 1017d3c: e0bff917 ldw r2,-28(fp) + 1017d40: 10c00215 stw r3,8(r2) + + /* If this is a device, ensure it isn't already locked */ + + if (isafs || ((status = alt_file_locked (fd)) >= 0)) + 1017d44: e0bff617 ldw r2,-40(fp) + 1017d48: 1004c03a cmpne r2,r2,zero + 1017d4c: 1000061e bne r2,zero,1017d68 + 1017d50: e13ff917 ldw r4,-28(fp) + 1017d54: 1017ba00 call 1017ba0 + 1017d58: e0bff715 stw r2,-36(fp) + 1017d5c: e0bff717 ldw r2,-36(fp) + 1017d60: 1004803a cmplt r2,r2,zero + 1017d64: 1000131e bne r2,zero,1017db4 + /* + * If the device or filesystem provides an open() callback function, + * call it now to perform any device/filesystem specific operations. + */ + + status = (dev->open) ? dev->open(fd, file, flags, mode): 0; + 1017d68: e0bffa17 ldw r2,-24(fp) + 1017d6c: 10800317 ldw r2,12(r2) + 1017d70: 1005003a cmpeq r2,r2,zero + 1017d74: 1000091e bne r2,zero,1017d9c + 1017d78: e0bffa17 ldw r2,-24(fp) + 1017d7c: 10800317 ldw r2,12(r2) + 1017d80: e13ff917 ldw r4,-28(fp) + 1017d84: e17ffb17 ldw r5,-20(fp) + 1017d88: e1bffc17 ldw r6,-16(fp) + 1017d8c: e1fffd17 ldw r7,-12(fp) + 1017d90: 103ee83a callr r2 + 1017d94: e0bfff15 stw r2,-4(fp) + 1017d98: 00000106 br 1017da0 + 1017d9c: e03fff15 stw zero,-4(fp) + 1017da0: e0bfff17 ldw r2,-4(fp) + 1017da4: e0bff715 stw r2,-36(fp) + 1017da8: 00000206 br 1017db4 + } + } + } + else + { + status = -ENODEV; + 1017dac: 00bffb44 movi r2,-19 + 1017db0: e0bff715 stw r2,-36(fp) + } + + /* Allocation failed, so clean up and return an error */ + + if (status < 0) + 1017db4: e0bff717 ldw r2,-36(fp) + 1017db8: 1004403a cmpge r2,r2,zero + 1017dbc: 1000091e bne r2,zero,1017de4 + { + alt_release_fd (index); + 1017dc0: e13ff817 ldw r4,-32(fp) + 1017dc4: 100ccfc0 call 100ccfc + ALT_ERRNO = -status; + 1017dc8: 1017e040 call 1017e04 + 1017dcc: e0fff717 ldw r3,-36(fp) + 1017dd0: 00c7c83a sub r3,zero,r3 + 1017dd4: 10c00015 stw r3,0(r2) + return -1; + 1017dd8: 00bfffc4 movi r2,-1 + 1017ddc: e0bffe15 stw r2,-8(fp) + 1017de0: 00000206 br 1017dec + } + + /* return the reference upon success */ + + return index; + 1017de4: e0bff817 ldw r2,-32(fp) + 1017de8: e0bffe15 stw r2,-8(fp) + 1017dec: e0bffe17 ldw r2,-8(fp) +} + 1017df0: e037883a mov sp,fp + 1017df4: dfc00117 ldw ra,4(sp) + 1017df8: df000017 ldw fp,0(sp) + 1017dfc: dec00204 addi sp,sp,8 + 1017e00: f800283a ret + +01017e04 : +#undef errno + +extern int errno; + +static ALT_INLINE int* alt_get_errno(void) +{ + 1017e04: defffd04 addi sp,sp,-12 + 1017e08: dfc00215 stw ra,8(sp) + 1017e0c: df000115 stw fp,4(sp) + 1017e10: df000104 addi fp,sp,4 + return ((alt_errno) ? alt_errno() : &errno); + 1017e14: 008040b4 movhi r2,258 + 1017e18: 10aba104 addi r2,r2,-20860 + 1017e1c: 10800017 ldw r2,0(r2) + 1017e20: 1005003a cmpeq r2,r2,zero + 1017e24: 1000061e bne r2,zero,1017e40 + 1017e28: 008040b4 movhi r2,258 + 1017e2c: 10aba104 addi r2,r2,-20860 + 1017e30: 10800017 ldw r2,0(r2) + 1017e34: 103ee83a callr r2 + 1017e38: e0bfff15 stw r2,-4(fp) + 1017e3c: 00000306 br 1017e4c + 1017e40: 008040b4 movhi r2,258 + 1017e44: 10b30404 addi r2,r2,-13296 + 1017e48: e0bfff15 stw r2,-4(fp) + 1017e4c: e0bfff17 ldw r2,-4(fp) +} + 1017e50: e037883a mov sp,fp + 1017e54: dfc00117 ldw ra,4(sp) + 1017e58: df000017 ldw fp,0(sp) + 1017e5c: dec00204 addi sp,sp,8 + 1017e60: f800283a ret + +01017e64 : + * alarms. Alternatively an alarm can unregister itself by returning zero when + * the alarm executes. + */ + +void alt_alarm_stop (alt_alarm* alarm) +{ + 1017e64: defffa04 addi sp,sp,-24 + 1017e68: df000515 stw fp,20(sp) + 1017e6c: df000504 addi fp,sp,20 + 1017e70: e13fff15 stw r4,-4(fp) +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1017e74: 0005303a rdctl r2,status + 1017e78: e0bffd15 stw r2,-12(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1017e7c: e0fffd17 ldw r3,-12(fp) + 1017e80: 00bfff84 movi r2,-2 + 1017e84: 1884703a and r2,r3,r2 + 1017e88: 1001703a wrctl status,r2 + + return context; + 1017e8c: e0bffd17 ldw r2,-12(fp) + alt_irq_context irq_context; + + irq_context = alt_irq_disable_all(); + 1017e90: e0bffe15 stw r2,-8(fp) + alt_llist_remove (&alarm->llist); + 1017e94: e0bfff17 ldw r2,-4(fp) + 1017e98: e0bffc15 stw r2,-16(fp) + * input argument is the element to remove. + */ + +static ALT_INLINE void ALT_ALWAYS_INLINE alt_llist_remove(alt_llist* entry) +{ + entry->next->previous = entry->previous; + 1017e9c: e0bffc17 ldw r2,-16(fp) + 1017ea0: 10c00017 ldw r3,0(r2) + 1017ea4: e0bffc17 ldw r2,-16(fp) + 1017ea8: 10800117 ldw r2,4(r2) + 1017eac: 18800115 stw r2,4(r3) + entry->previous->next = entry->next; + 1017eb0: e0bffc17 ldw r2,-16(fp) + 1017eb4: 10c00117 ldw r3,4(r2) + 1017eb8: e0bffc17 ldw r2,-16(fp) + 1017ebc: 10800017 ldw r2,0(r2) + 1017ec0: 18800015 stw r2,0(r3) + /* + * Set the entry to point to itself, so that any further calls to + * alt_llist_remove() are harmless. + */ + + entry->previous = entry; + 1017ec4: e0fffc17 ldw r3,-16(fp) + 1017ec8: e0bffc17 ldw r2,-16(fp) + 1017ecc: 18800115 stw r2,4(r3) + entry->next = entry; + 1017ed0: e0fffc17 ldw r3,-16(fp) + 1017ed4: e0bffc17 ldw r2,-16(fp) + 1017ed8: 18800015 stw r2,0(r3) + 1017edc: e0bffe17 ldw r2,-8(fp) + 1017ee0: e0bffb15 stw r2,-20(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1017ee4: e0bffb17 ldw r2,-20(fp) + 1017ee8: 1001703a wrctl status,r2 + alt_irq_enable_all (irq_context); +} + 1017eec: e037883a mov sp,fp + 1017ef0: df000017 ldw fp,0(sp) + 1017ef4: dec00104 addi sp,sp,4 + 1017ef8: f800283a ret + +01017efc : + * + * alt_tick() is expected to run at interrupt level. + */ + +void alt_tick (void) +{ + 1017efc: defffb04 addi sp,sp,-20 + 1017f00: dfc00415 stw ra,16(sp) + 1017f04: df000315 stw fp,12(sp) + 1017f08: df000304 addi fp,sp,12 + alt_alarm* next; + alt_alarm* alarm = (alt_alarm*) alt_alarm_list.next; + 1017f0c: d0a03617 ldw r2,-32552(gp) + 1017f10: e0bffe15 stw r2,-8(fp) + + alt_u32 next_callback; + + /* update the tick counter */ + + _alt_nticks++; + 1017f14: d0a79917 ldw r2,-24988(gp) + 1017f18: 10800044 addi r2,r2,1 + 1017f1c: d0a79915 stw r2,-24988(gp) + + /* process the registered callbacks */ + + while (alarm != (alt_alarm*) &alt_alarm_list) + 1017f20: 00003106 br 1017fe8 + { + next = (alt_alarm*) alarm->llist.next; + 1017f24: e0bffe17 ldw r2,-8(fp) + 1017f28: 10800017 ldw r2,0(r2) + 1017f2c: e0bfff15 stw r2,-4(fp) + /* + * Upon the tick-counter rolling over it is safe to clear the + * roll-over flag; once the flag is cleared this (or subsequnt) + * tick events are enabled to generate an alarm event. + */ + if ((alarm->rollover) && (_alt_nticks == 0)) + 1017f30: e0bffe17 ldw r2,-8(fp) + 1017f34: 10800403 ldbu r2,16(r2) + 1017f38: 10803fcc andi r2,r2,255 + 1017f3c: 1005003a cmpeq r2,r2,zero + 1017f40: 1000051e bne r2,zero,1017f58 + 1017f44: d0a79917 ldw r2,-24988(gp) + 1017f48: 1004c03a cmpne r2,r2,zero + 1017f4c: 1000021e bne r2,zero,1017f58 + { + alarm->rollover = 0; + 1017f50: e0bffe17 ldw r2,-8(fp) + 1017f54: 10000405 stb zero,16(r2) + } + + /* if the alarm period has expired, make the callback */ + if ((alarm->time <= _alt_nticks) && (alarm->rollover == 0)) + 1017f58: e0bffe17 ldw r2,-8(fp) + 1017f5c: 10c00217 ldw r3,8(r2) + 1017f60: d0a79917 ldw r2,-24988(gp) + 1017f64: 10c01e36 bltu r2,r3,1017fe0 + 1017f68: e0bffe17 ldw r2,-8(fp) + 1017f6c: 10800403 ldbu r2,16(r2) + 1017f70: 10803fcc andi r2,r2,255 + 1017f74: 1004c03a cmpne r2,r2,zero + 1017f78: 1000191e bne r2,zero,1017fe0 + { + next_callback = alarm->callback (alarm->context); + 1017f7c: e0bffe17 ldw r2,-8(fp) + 1017f80: 10c00317 ldw r3,12(r2) + 1017f84: e0bffe17 ldw r2,-8(fp) + 1017f88: 11000517 ldw r4,20(r2) + 1017f8c: 183ee83a callr r3 + 1017f90: e0bffd15 stw r2,-12(fp) + + /* deactivate the alarm if the return value is zero */ + + if (next_callback == 0) + 1017f94: e0bffd17 ldw r2,-12(fp) + 1017f98: 1004c03a cmpne r2,r2,zero + 1017f9c: 1000031e bne r2,zero,1017fac + { + alt_alarm_stop (alarm); + 1017fa0: e13ffe17 ldw r4,-8(fp) + 1017fa4: 1017e640 call 1017e64 + 1017fa8: 00000d06 br 1017fe0 + } + else + { + alarm->time += next_callback; + 1017fac: e0bffe17 ldw r2,-8(fp) + 1017fb0: 10c00217 ldw r3,8(r2) + 1017fb4: e0bffd17 ldw r2,-12(fp) + 1017fb8: 1887883a add r3,r3,r2 + 1017fbc: e0bffe17 ldw r2,-8(fp) + 1017fc0: 10c00215 stw r3,8(r2) + /* + * If the desired alarm time causes a roll-over, set the rollover + * flag. This will prevent the subsequent tick event from causing + * an alarm too early. + */ + if(alarm->time < _alt_nticks) + 1017fc4: e0bffe17 ldw r2,-8(fp) + 1017fc8: 10c00217 ldw r3,8(r2) + 1017fcc: d0a79917 ldw r2,-24988(gp) + 1017fd0: 1880032e bgeu r3,r2,1017fe0 + { + alarm->rollover = 1; + 1017fd4: e0fffe17 ldw r3,-8(fp) + 1017fd8: 00800044 movi r2,1 + 1017fdc: 18800405 stb r2,16(r3) + } + } + } + alarm = next; + 1017fe0: e0bfff17 ldw r2,-4(fp) + 1017fe4: e0bffe15 stw r2,-8(fp) + + _alt_nticks++; + + /* process the registered callbacks */ + + while (alarm != (alt_alarm*) &alt_alarm_list) + 1017fe8: d0e03604 addi r3,gp,-32552 + 1017fec: e0bffe17 ldw r2,-8(fp) + 1017ff0: 10ffcc1e bne r2,r3,1017f24 + + /* + * Update the operating system specific timer facilities. + */ + + ALT_OS_TIME_TICK(); + 1017ff4: 100dffc0 call 100dffc +} + 1017ff8: e037883a mov sp,fp + 1017ffc: dfc00117 ldw ra,4(sp) + 1018000: df000017 ldw fp,0(sp) + 1018004: dec00204 addi sp,sp,8 + 1018008: f800283a ret + +0101800c : +/* + * To initialize the internal interrupt controller, just clear the IENABLE + * register so that all possible IRQs are disabled. + */ +void altera_nios2_qsys_irq_init(void) +{ + 101800c: deffff04 addi sp,sp,-4 + 1018010: df000015 stw fp,0(sp) + 1018014: d839883a mov fp,sp + NIOS2_WRITE_IENABLE(0); + 1018018: 000170fa wrctl ienable,zero +} + 101801c: e037883a mov sp,fp + 1018020: df000017 ldw fp,0(sp) + 1018024: dec00104 addi sp,sp,4 + 1018028: f800283a ret + +0101802c : + + /* + * Save the remaining registers to the stack. + */ + + addi sp, sp, -44 + 101802c: defff504 addi sp,sp,-44 + bltu sp, et, .Lstack_overflow + +#endif + +#if OS_THREAD_SAFE_NEWLIB + ldw r3, %gprel(_impure_ptr)(gp) /* load the pointer */ + 1018030: d0e00b17 ldw r3,-32724(gp) +#endif /* OS_THREAD_SAFE_NEWLIB */ + + ldw r4, %gprel(OSTCBCur)(gp) + 1018034: d1279217 ldw r4,-25016(gp) + + stw ra, 0(sp) + 1018038: dfc00015 stw ra,0(sp) + stw fp, 4(sp) + 101803c: df000115 stw fp,4(sp) + stw r23, 8(sp) + 1018040: ddc00215 stw r23,8(sp) + stw r22, 12(sp) + 1018044: dd800315 stw r22,12(sp) + stw r21, 16(sp) + 1018048: dd400415 stw r21,16(sp) + stw r20, 20(sp) + 101804c: dd000515 stw r20,20(sp) + stw r19, 24(sp) + 1018050: dcc00615 stw r19,24(sp) + stw r18, 28(sp) + 1018054: dc800715 stw r18,28(sp) + stw r17, 32(sp) + 1018058: dc400815 stw r17,32(sp) + stw r16, 36(sp) + 101805c: dc000915 stw r16,36(sp) + * store the current value of _impure_ptr so it can be restored + * later; _impure_ptr is asigned on a per task basis. It is used + * by Newlib to achieve reentrancy. + */ + + stw r3, 40(sp) /* save the impure pointer */ + 1018060: d8c00a15 stw r3,40(sp) + /* + * Save the current tasks stack pointer into the current tasks OS_TCB. + * i.e. OSTCBCur->OSTCBStkPtr = sp; + */ + + stw sp, (r4) /* save the stack pointer (OSTCBStkPtr */ + 1018064: 26c00015 stw sp,0(r4) + + /* + * Call the user definable OSTaskSWHook() + */ + + call OSTaskSwHook + 1018068: 101844c0 call 101844c + /* + * OSTCBCur = OSTCBHighRdy; + * OSPrioCur = OSPrioHighRdy; + */ + + ldw r4, %gprel(OSTCBHighRdy)(gp) + 101806c: d1278d17 ldw r4,-25036(gp) + ldb r5, %gprel(OSPrioHighRdy)(gp) + 1018070: d1678507 ldb r5,-25068(gp) + + stw r4, %gprel(OSTCBCur)(gp) /* set the current task to be the new task */ + 1018074: d1279215 stw r4,-25016(gp) + stb r5, %gprel(OSPrioCur)(gp) /* store the new task's priority as the current */ + 1018078: d1678545 stb r5,-25067(gp) + + /* + * Set the stack pointer to point to the new task's stack + */ + + ldw sp, (r4) /* the stack pointer is the first entry in the OS_TCB structure */ + 101807c: 26c00017 ldw sp,0(r4) + /* + * restore the value of _impure_ptr ; _impure_ptr is asigned on a + * per task basis. It is used by Newlib to achieve reentrancy. + */ + + ldw r3, 40(sp) /* load the new impure pointer */ + 1018080: d8c00a17 ldw r3,40(sp) + + /* + * Restore the saved registers for the new task. + */ + + ldw ra, 0(sp) + 1018084: dfc00017 ldw ra,0(sp) + ldw fp, 4(sp) + 1018088: df000117 ldw fp,4(sp) + ldw r23, 8(sp) + 101808c: ddc00217 ldw r23,8(sp) + ldw r22, 12(sp) + 1018090: dd800317 ldw r22,12(sp) + ldw r21, 16(sp) + 1018094: dd400417 ldw r21,16(sp) + ldw r20, 20(sp) + 1018098: dd000517 ldw r20,20(sp) + ldw r19, 24(sp) + 101809c: dcc00617 ldw r19,24(sp) + ldw r18, 28(sp) + 10180a0: dc800717 ldw r18,28(sp) + ldw r17, 32(sp) + 10180a4: dc400817 ldw r17,32(sp) + ldw r16, 36(sp) + 10180a8: dc000917 ldw r16,36(sp) + +#if OS_THREAD_SAFE_NEWLIB + + stw r3, %gprel(_impure_ptr)(gp) /* update _impure_ptr */ + 10180ac: d0e00b15 stw r3,-32724(gp) + + stw et, %gprel(alt_stack_limit_value)(gp) + +#endif + + addi sp, sp, 44 + 10180b0: dec00b04 addi sp,sp,44 + + /* + * resume execution of the new task. + */ + + ret + 10180b4: f800283a ret + +010180b8 : + + /* + * disable interrupts so that the scheduler doesn't run while + * we're initialising this task. + */ + rdctl r18, status + 10180b8: 0025303a rdctl r18,status + subi r17, zero, 2 /* r17 = 0xfffffffe */ + 10180bc: 047fff84 movi r17,-2 + and r18, r18, r17 + 10180c0: 9464703a and r18,r18,r17 + wrctl status, r18 + 10180c4: 9001703a wrctl status,r18 + + /* + * Call the user definable OSTaskSWHook() + */ + + call OSTaskSwHook + 10180c8: 101844c0 call 101844c + + /* + * set OSRunning = TRUE. + */ + + movi r18, 1 /* set r18 to the value 'TRUE' */ + 10180cc: 04800044 movi r18,1 + stb r18, %gprel(OSRunning)(gp) /* save this to OSRunning */ + 10180d0: d4a78345 stb r18,-25075(gp) + + /* + * start execution of the new task. + */ + + br 9b + 10180d4: 003fe506 br 101806c + +010180d8 : + +OSStartTsk: + /* This instruction is never executed. Its here to make the + * backtrace work right + */ + movi sp, 0 + 10180d8: 06c00004 movi sp,0 + + /* Enable interrupts */ + rdctl r2, status + 10180dc: 0005303a rdctl r2,status + ori r2, r2, 0x1 + 10180e0: 10800054 ori r2,r2,1 + wrctl status, r2 + 10180e4: 1001703a wrctl status,r2 + + ldw r2, 4(sp) + 10180e8: d8800117 ldw r2,4(sp) + ldw r4, 0(sp) + 10180ec: d9000017 ldw r4,0(sp) + + addi sp, sp, 8 + 10180f0: dec00204 addi sp,sp,8 + + callr r2 + 10180f4: 103ee83a callr r2 + + nop + 10180f8: 0001883a nop + +010180fc : + * been placed on the stack in the proper order. + * + ***********************************************************************************************/ + +OS_STK *OSTaskStkInit(void (*task)(void *pd), void *pdata, OS_STK *pstk, INT16U opt) +{ + 10180fc: defff704 addi sp,sp,-36 + 1018100: dfc00815 stw ra,32(sp) + 1018104: df000715 stw fp,28(sp) + 1018108: df000704 addi fp,sp,28 + 101810c: e13ffc15 stw r4,-16(fp) + 1018110: e17ffd15 stw r5,-12(fp) + 1018114: e1bffe15 stw r6,-8(fp) + 1018118: e1ffff0d sth r7,-4(fp) + * create and initialise the impure pointer used for Newlib thread local storage. + * This is only done if the C library is being used in a thread safe mode. Otherwise + * a single reent structure is used for all threads, which saves memory. + */ + + local_impure_ptr = (struct _reent*)((((INT32U)(pstk)) & ~0x3) - sizeof(struct _reent)); + 101811c: e0bffe17 ldw r2,-8(fp) + 1018120: 1007883a mov r3,r2 + 1018124: 00bfff04 movi r2,-4 + 1018128: 1884703a and r2,r3,r2 + 101812c: 10bf0004 addi r2,r2,-1024 + 1018130: e0bff915 stw r2,-28(fp) + + _REENT_INIT_PTR (local_impure_ptr); + 1018134: e0bff917 ldw r2,-28(fp) + 1018138: 10000015 stw zero,0(r2) + 101813c: e0bff917 ldw r2,-28(fp) + 1018140: 10c0bb04 addi r3,r2,748 + 1018144: e0bff917 ldw r2,-28(fp) + 1018148: 10c00115 stw r3,4(r2) + 101814c: e0bff917 ldw r2,-28(fp) + 1018150: 1080bb04 addi r2,r2,748 + 1018154: 10c01704 addi r3,r2,92 + 1018158: e0bff917 ldw r2,-28(fp) + 101815c: 10c00215 stw r3,8(r2) + 1018160: e0bff917 ldw r2,-28(fp) + 1018164: 1080bb04 addi r2,r2,748 + 1018168: 10c02e04 addi r3,r2,184 + 101816c: e0bff917 ldw r2,-28(fp) + 1018170: 10c00315 stw r3,12(r2) + 1018174: e0bff917 ldw r2,-28(fp) + 1018178: 10000415 stw zero,16(r2) + 101817c: e0bff917 ldw r2,-28(fp) + 1018180: 10800504 addi r2,r2,20 + 1018184: 1009883a mov r4,r2 + 1018188: 01800644 movi r6,25 + 101818c: 000b883a mov r5,zero + 1018190: 1002f1c0 call 1002f1c + 1018194: e0bff917 ldw r2,-28(fp) + 1018198: 10000c15 stw zero,48(r2) + 101819c: e0fff917 ldw r3,-28(fp) + 10181a0: 008040b4 movhi r2,258 + 10181a4: 10a48f04 addi r2,r2,-28100 + 10181a8: 18800d15 stw r2,52(r3) + 10181ac: e0bff917 ldw r2,-28(fp) + 10181b0: 10000e15 stw zero,56(r2) + 10181b4: e0bff917 ldw r2,-28(fp) + 10181b8: 10000f15 stw zero,60(r2) + 10181bc: e0bff917 ldw r2,-28(fp) + 10181c0: 10001015 stw zero,64(r2) + 10181c4: e0bff917 ldw r2,-28(fp) + 10181c8: 10001115 stw zero,68(r2) + 10181cc: e0bff917 ldw r2,-28(fp) + 10181d0: 10001215 stw zero,72(r2) + 10181d4: e0bff917 ldw r2,-28(fp) + 10181d8: 10001315 stw zero,76(r2) + 10181dc: e0bff917 ldw r2,-28(fp) + 10181e0: 10001415 stw zero,80(r2) + 10181e4: e0bff917 ldw r2,-28(fp) + 10181e8: 10001515 stw zero,84(r2) + 10181ec: e0bff917 ldw r2,-28(fp) + 10181f0: 10001615 stw zero,88(r2) + 10181f4: e0bff917 ldw r2,-28(fp) + 10181f8: 10001715 stw zero,92(r2) + 10181fc: e0bff917 ldw r2,-28(fp) + 1018200: 10001805 stb zero,96(r2) + 1018204: e0bff917 ldw r2,-28(fp) + 1018208: 10801f04 addi r2,r2,124 + 101820c: 10000015 stw zero,0(r2) + 1018210: 10000115 stw zero,4(r2) + 1018214: 10000215 stw zero,8(r2) + 1018218: 10000315 stw zero,12(r2) + 101821c: 10000415 stw zero,16(r2) + 1018220: 10000515 stw zero,20(r2) + 1018224: 10000615 stw zero,24(r2) + 1018228: 10000715 stw zero,28(r2) + 101822c: 10000815 stw zero,32(r2) + 1018230: e0bff917 ldw r2,-28(fp) + 1018234: 10002815 stw zero,160(r2) + 1018238: e0fff917 ldw r3,-28(fp) + 101823c: 00800044 movi r2,1 + 1018240: 18802915 stw r2,164(r3) + 1018244: 18002a15 stw zero,168(r3) + 1018248: e0fff917 ldw r3,-28(fp) + 101824c: 008cc384 movi r2,13070 + 1018250: 18802b0d sth r2,172(r3) + 1018254: e0fff917 ldw r3,-28(fp) + 1018258: 00aaf344 movi r2,-21555 + 101825c: 18802b8d sth r2,174(r3) + 1018260: e0fff917 ldw r3,-28(fp) + 1018264: 00848d04 movi r2,4660 + 1018268: 18802c0d sth r2,176(r3) + 101826c: e0fff917 ldw r3,-28(fp) + 1018270: 00b99b44 movi r2,-6547 + 1018274: 18802c8d sth r2,178(r3) + 1018278: e0fff917 ldw r3,-28(fp) + 101827c: 00b7bb04 movi r2,-8468 + 1018280: 18802d0d sth r2,180(r3) + 1018284: e0fff917 ldw r3,-28(fp) + 1018288: 00800144 movi r2,5 + 101828c: 18802d8d sth r2,182(r3) + 1018290: e0fff917 ldw r3,-28(fp) + 1018294: 008002c4 movi r2,11 + 1018298: 18802e0d sth r2,184(r3) + 101829c: e0bff917 ldw r2,-28(fp) + 10182a0: 10002f15 stw zero,188(r2) + 10182a4: e0bff917 ldw r2,-28(fp) + 10182a8: 10003015 stw zero,192(r2) + 10182ac: e0bff917 ldw r2,-28(fp) + 10182b0: 10003115 stw zero,196(r2) + 10182b4: e0bff917 ldw r2,-28(fp) + 10182b8: 10003215 stw zero,200(r2) + 10182bc: e0bff917 ldw r2,-28(fp) + 10182c0: 10003315 stw zero,204(r2) + 10182c4: e0bff917 ldw r2,-28(fp) + 10182c8: 10003415 stw zero,208(r2) + 10182cc: e0bff917 ldw r2,-28(fp) + 10182d0: 10003e15 stw zero,248(r2) + 10182d4: e0bff917 ldw r2,-28(fp) + 10182d8: 10003f15 stw zero,252(r2) + 10182dc: e0bff917 ldw r2,-28(fp) + 10182e0: 10004015 stw zero,256(r2) + 10182e4: e0bff917 ldw r2,-28(fp) + 10182e8: 10004115 stw zero,260(r2) + 10182ec: e0bff917 ldw r2,-28(fp) + 10182f0: 10004215 stw zero,264(r2) + 10182f4: e0bff917 ldw r2,-28(fp) + 10182f8: 10004315 stw zero,268(r2) + 10182fc: e0bff917 ldw r2,-28(fp) + 1018300: 10004415 stw zero,272(r2) + 1018304: e0bff917 ldw r2,-28(fp) + 1018308: 10004515 stw zero,276(r2) + 101830c: e0bff917 ldw r2,-28(fp) + 1018310: 10004615 stw zero,280(r2) + 1018314: e0bff917 ldw r2,-28(fp) + 1018318: 10004715 stw zero,284(r2) + 101831c: e0bff917 ldw r2,-28(fp) + 1018320: 10003505 stb zero,212(r2) + 1018324: e0bff917 ldw r2,-28(fp) + 1018328: 10003705 stb zero,220(r2) + 101832c: e0bff917 ldw r2,-28(fp) + 1018330: 10003d15 stw zero,244(r2) + 1018334: e0bff917 ldw r2,-28(fp) + 1018338: 10005215 stw zero,328(r2) + 101833c: e0bff917 ldw r2,-28(fp) + 1018340: 10005315 stw zero,332(r2) + 1018344: e0bff917 ldw r2,-28(fp) + 1018348: 10005415 stw zero,336(r2) + 101834c: e0bff917 ldw r2,-28(fp) + 1018350: 10005515 stw zero,340(r2) + 1018354: e0bff917 ldw r2,-28(fp) + 1018358: 1000b515 stw zero,724(r2) + 101835c: e0bff917 ldw r2,-28(fp) + 1018360: 10007515 stw zero,468(r2) + 1018364: e0bff917 ldw r2,-28(fp) + 1018368: 1000b715 stw zero,732(r2) + 101836c: e0bff917 ldw r2,-28(fp) + 1018370: 1000b815 stw zero,736(r2) + 1018374: e0bff917 ldw r2,-28(fp) + 1018378: 1000b915 stw zero,740(r2) + 101837c: e0bff917 ldw r2,-28(fp) + 1018380: 1000ba15 stw zero,744(r2) + 1018384: e0bff917 ldw r2,-28(fp) + 1018388: 1080bb04 addi r2,r2,748 + 101838c: 1009883a mov r4,r2 + 1018390: 01804504 movi r6,276 + 1018394: 000b883a mov r5,zero + 1018398: 1002f1c0 call 1002f1c + /* + * create a stack frame at the top of the stack (leaving space for the + * reentrant data structure). + */ + + frame_pointer = (INT32U*) local_impure_ptr; + 101839c: e0bff917 ldw r2,-28(fp) + 10183a0: e0bffb15 stw r2,-20(fp) +#else + frame_pointer = (INT32U*) (((INT32U)(pstk)) & ~0x3); +#endif /* OS_THREAD_SAFE_NEWLIB */ + stk = frame_pointer - 13; + 10183a4: e0bffb17 ldw r2,-20(fp) + 10183a8: 10bff304 addi r2,r2,-52 + 10183ac: e0bffa15 stw r2,-24(fp) + + /* Now fill the stack frame. */ + + stk[12] = (INT32U)task; /* task address (ra) */ + 10183b0: e0bffa17 ldw r2,-24(fp) + 10183b4: 10c00c04 addi r3,r2,48 + 10183b8: e0bffc17 ldw r2,-16(fp) + 10183bc: 18800015 stw r2,0(r3) + stk[11] = (INT32U) pdata; /* first register argument (r4) */ + 10183c0: e0bffa17 ldw r2,-24(fp) + 10183c4: 10c00b04 addi r3,r2,44 + 10183c8: e0bffd17 ldw r2,-12(fp) + 10183cc: 18800015 stw r2,0(r3) + +#if OS_THREAD_SAFE_NEWLIB + stk[10] = (INT32U) local_impure_ptr; /* value of _impure_ptr for this thread */ + 10183d0: e0bffa17 ldw r2,-24(fp) + 10183d4: 10c00a04 addi r3,r2,40 + 10183d8: e0bff917 ldw r2,-28(fp) + 10183dc: 18800015 stw r2,0(r3) +#endif /* OS_THREAD_SAFE_NEWLIB */ + stk[0] = ((INT32U)&OSStartTsk) + 4;/* exception return address (ea) */ + 10183e0: 008040b4 movhi r2,258 + 10183e4: 10a03604 addi r2,r2,-32552 + 10183e8: 10c00104 addi r3,r2,4 + 10183ec: e0bffa17 ldw r2,-24(fp) + 10183f0: 10c00015 stw r3,0(r2) + */ + __asm__ (".set OSTCBNext_OFFSET,%0" :: "i" (offsetof(OS_TCB, OSTCBNext))); + __asm__ (".set OSTCBPrio_OFFSET,%0" :: "i" (offsetof(OS_TCB, OSTCBPrio))); + __asm__ (".set OSTCBStkPtr_OFFSET,%0" :: "i" (offsetof(OS_TCB, OSTCBStkPtr))); + + return((OS_STK *)stk); + 10183f4: e0bffa17 ldw r2,-24(fp) +} + 10183f8: e037883a mov sp,fp + 10183fc: dfc00117 ldw ra,4(sp) + 1018400: df000017 ldw fp,0(sp) + 1018404: dec00204 addi sp,sp,8 + 1018408: f800283a ret + +0101840c : +* +* Note(s) : 1) Interrupts are disabled during this call. +********************************************************************************************************* +*/ +void OSTaskCreateHook (OS_TCB *ptcb) +{ + 101840c: defffe04 addi sp,sp,-8 + 1018410: df000115 stw fp,4(sp) + 1018414: df000104 addi fp,sp,4 + 1018418: e13fff15 stw r4,-4(fp) + ptcb = ptcb; /* Prevent compiler warning */ +} + 101841c: e037883a mov sp,fp + 1018420: df000017 ldw fp,0(sp) + 1018424: dec00104 addi sp,sp,4 + 1018428: f800283a ret + +0101842c : +* +* Note(s) : 1) Interrupts are disabled during this call. +********************************************************************************************************* +*/ +void OSTaskDelHook (OS_TCB *ptcb) +{ + 101842c: defffe04 addi sp,sp,-8 + 1018430: df000115 stw fp,4(sp) + 1018434: df000104 addi fp,sp,4 + 1018438: e13fff15 stw r4,-4(fp) + ptcb = ptcb; /* Prevent compiler warning */ +} + 101843c: e037883a mov sp,fp + 1018440: df000017 ldw fp,0(sp) + 1018444: dec00104 addi sp,sp,4 + 1018448: f800283a ret + +0101844c : +* will be 'switched in' (i.e. the highest priority task) and, 'OSTCBCur' points to the +* task being switched out (i.e. the preempted task). +********************************************************************************************************* +*/ +void OSTaskSwHook (void) +{ + 101844c: deffff04 addi sp,sp,-4 + 1018450: df000015 stw fp,0(sp) + 1018454: d839883a mov fp,sp +} + 1018458: e037883a mov sp,fp + 101845c: df000017 ldw fp,0(sp) + 1018460: dec00104 addi sp,sp,4 + 1018464: f800283a ret + +01018468 : +* +* Arguments : none +********************************************************************************************************* +*/ +void OSTaskStatHook (void) +{ + 1018468: deffff04 addi sp,sp,-4 + 101846c: df000015 stw fp,0(sp) + 1018470: d839883a mov fp,sp +} + 1018474: e037883a mov sp,fp + 1018478: df000017 ldw fp,0(sp) + 101847c: dec00104 addi sp,sp,4 + 1018480: f800283a ret + +01018484 : +#ifdef ALT_INICHE +void cticks_hook(void); +#endif + +void OSTimeTickHook (void) +{ + 1018484: deffff04 addi sp,sp,-4 + 1018488: df000015 stw fp,0(sp) + 101848c: d839883a mov fp,sp + +#ifdef ALT_INICHE + /* Service the Interniche timer */ + cticks_hook(); +#endif +} + 1018490: e037883a mov sp,fp + 1018494: df000017 ldw fp,0(sp) + 1018498: dec00104 addi sp,sp,4 + 101849c: f800283a ret + +010184a0 : + +void OSInitHookBegin(void) +{ + 10184a0: deffff04 addi sp,sp,-4 + 10184a4: df000015 stw fp,0(sp) + 10184a8: d839883a mov fp,sp +#if OS_TMR_EN > 0 + OSTmrCtr = 0; +#endif +} + 10184ac: e037883a mov sp,fp + 10184b0: df000017 ldw fp,0(sp) + 10184b4: dec00104 addi sp,sp,4 + 10184b8: f800283a ret + +010184bc : + +void OSInitHookEnd(void) +{ + 10184bc: deffff04 addi sp,sp,-4 + 10184c0: df000015 stw fp,0(sp) + 10184c4: d839883a mov fp,sp +} + 10184c8: e037883a mov sp,fp + 10184cc: df000017 ldw fp,0(sp) + 10184d0: dec00104 addi sp,sp,4 + 10184d4: f800283a ret + +010184d8 : + +void OSTaskIdleHook(void) +{ + 10184d8: deffff04 addi sp,sp,-4 + 10184dc: df000015 stw fp,0(sp) + 10184e0: d839883a mov fp,sp +} + 10184e4: e037883a mov sp,fp + 10184e8: df000017 ldw fp,0(sp) + 10184ec: dec00104 addi sp,sp,4 + 10184f0: f800283a ret + +010184f4 : + +void OSTCBInitHook(OS_TCB *ptcb) +{ + 10184f4: defffe04 addi sp,sp,-8 + 10184f8: df000115 stw fp,4(sp) + 10184fc: df000104 addi fp,sp,4 + 1018500: e13fff15 stw r4,-4(fp) +} + 1018504: e037883a mov sp,fp + 1018508: df000017 ldw fp,0(sp) + 101850c: dec00104 addi sp,sp,4 + 1018510: f800283a ret + +01018514 : + * either '/' or '\0' is the prefix of the filename. For example the filename: + * "/myfilesystem/junk.txt" would match: "/myfilesystem", but not: "/myfile". + */ + +alt_dev* alt_find_file (const char* name) +{ + 1018514: defffa04 addi sp,sp,-24 + 1018518: dfc00515 stw ra,20(sp) + 101851c: df000415 stw fp,16(sp) + 1018520: df000404 addi fp,sp,16 + 1018524: e13ffe15 stw r4,-8(fp) + alt_dev* next = (alt_dev*) alt_fs_list.next; + 1018528: 008040b4 movhi r2,258 + 101852c: 10ab9c04 addi r2,r2,-20880 + 1018530: 10800017 ldw r2,0(r2) + 1018534: e0bffd15 stw r2,-12(fp) + /* + * Check each list entry in turn, until a match is found, or we reach the + * end of the list (i.e. next winds up pointing back to the list head). + */ + + while (next != (alt_dev*) &alt_fs_list) + 1018538: 00003306 br 1018608 + { + len = strlen(next->name); + 101853c: e0bffd17 ldw r2,-12(fp) + 1018540: 11000217 ldw r4,8(r2) + 1018544: 10034a00 call 10034a0 + 1018548: e0bffc15 stw r2,-16(fp) + + if (next->name[len-1] == '/') + 101854c: e0bffd17 ldw r2,-12(fp) + 1018550: 10c00217 ldw r3,8(r2) + 1018554: e0bffc17 ldw r2,-16(fp) + 1018558: 1885883a add r2,r3,r2 + 101855c: 10bfffc4 addi r2,r2,-1 + 1018560: 10800003 ldbu r2,0(r2) + 1018564: 10803fcc andi r2,r2,255 + 1018568: 1080201c xori r2,r2,128 + 101856c: 10bfe004 addi r2,r2,-128 + 1018570: 10800bd8 cmpnei r2,r2,47 + 1018574: 1000031e bne r2,zero,1018584 + { + len -= 1; + 1018578: e0bffc17 ldw r2,-16(fp) + 101857c: 10bfffc4 addi r2,r2,-1 + 1018580: e0bffc15 stw r2,-16(fp) + } + + if (((name[len] == '/') || (name[len] == '\0')) && + 1018584: e0bffc17 ldw r2,-16(fp) + 1018588: 1007883a mov r3,r2 + 101858c: e0bffe17 ldw r2,-8(fp) + 1018590: 1885883a add r2,r3,r2 + 1018594: 10800003 ldbu r2,0(r2) + 1018598: 10803fcc andi r2,r2,255 + 101859c: 1080201c xori r2,r2,128 + 10185a0: 10bfe004 addi r2,r2,-128 + 10185a4: 10800be0 cmpeqi r2,r2,47 + 10185a8: 10000a1e bne r2,zero,10185d4 + 10185ac: e0bffc17 ldw r2,-16(fp) + 10185b0: 1007883a mov r3,r2 + 10185b4: e0bffe17 ldw r2,-8(fp) + 10185b8: 1885883a add r2,r3,r2 + 10185bc: 10800003 ldbu r2,0(r2) + 10185c0: 10803fcc andi r2,r2,255 + 10185c4: 1080201c xori r2,r2,128 + 10185c8: 10bfe004 addi r2,r2,-128 + 10185cc: 1004c03a cmpne r2,r2,zero + 10185d0: 10000a1e bne r2,zero,10185fc + 10185d4: e0bffd17 ldw r2,-12(fp) + 10185d8: 11000217 ldw r4,8(r2) + 10185dc: e1bffc17 ldw r6,-16(fp) + 10185e0: e17ffe17 ldw r5,-8(fp) + 10185e4: 10188040 call 1018804 + 10185e8: 1004c03a cmpne r2,r2,zero + 10185ec: 1000031e bne r2,zero,10185fc + !memcmp (next->name, name, len)) + { + /* match found */ + + return next; + 10185f0: e0bffd17 ldw r2,-12(fp) + 10185f4: e0bfff15 stw r2,-4(fp) + 10185f8: 00000806 br 101861c + } + next = (alt_dev*) next->llist.next; + 10185fc: e0bffd17 ldw r2,-12(fp) + 1018600: 10800017 ldw r2,0(r2) + 1018604: e0bffd15 stw r2,-12(fp) + /* + * Check each list entry in turn, until a match is found, or we reach the + * end of the list (i.e. next winds up pointing back to the list head). + */ + + while (next != (alt_dev*) &alt_fs_list) + 1018608: 00c040b4 movhi r3,258 + 101860c: 18eb9c04 addi r3,r3,-20880 + 1018610: e0bffd17 ldw r2,-12(fp) + 1018614: 10ffc91e bne r2,r3,101853c + next = (alt_dev*) next->llist.next; + } + + /* No match found */ + + return NULL; + 1018618: e03fff15 stw zero,-4(fp) + 101861c: e0bfff17 ldw r2,-4(fp) +} + 1018620: e037883a mov sp,fp + 1018624: dfc00117 ldw ra,4(sp) + 1018628: df000017 ldw fp,0(sp) + 101862c: dec00204 addi sp,sp,8 + 1018630: f800283a ret + +01018634 : + * the offset of the file descriptor within the file descriptor array). A + * negative value indicates failure. + */ + +int alt_get_fd (alt_dev* dev) +{ + 1018634: defff804 addi sp,sp,-32 + 1018638: dfc00715 stw ra,28(sp) + 101863c: df000615 stw fp,24(sp) + 1018640: df000604 addi fp,sp,24 + 1018644: e13fff15 stw r4,-4(fp) + alt_32 i; + int rc = -EMFILE; + 1018648: 00bffa04 movi r2,-24 + 101864c: e0bffc15 stw r2,-16(fp) + /* + * Take the alt_fd_list_lock semaphore in order to avoid races when + * accessing the file descriptor pool. + */ + + ALT_SEM_PEND(alt_fd_list_lock, 0); + 1018650: 008040b4 movhi r2,258 + 1018654: 10b30804 addi r2,r2,-13280 + 1018658: 10800017 ldw r2,0(r2) + 101865c: e0bffa15 stw r2,-24(fp) + 1018660: e03ffb0d sth zero,-20(fp) + 1018664: e17ffb0b ldhu r5,-20(fp) + 1018668: e1bffe04 addi r6,fp,-8 + 101866c: e13ffa17 ldw r4,-24(fp) + 1018670: 1012e180 call 1012e18 + * indicates the highest file descriptor ever allocated. This is used to + * improve efficency when searching the file descriptor list, and + * therefore reduce contention on the alt_fd_list_lock semaphore. + */ + + for (i = 0; i < ALT_MAX_FD; i++) + 1018674: e03ffd15 stw zero,-12(fp) + 1018678: 00001e06 br 10186f4 + { + if (!alt_fd_list[i].dev) + 101867c: e0bffd17 ldw r2,-12(fp) + 1018680: 00c040b4 movhi r3,258 + 1018684: 18e69f04 addi r3,r3,-25988 + 1018688: 10800324 muli r2,r2,12 + 101868c: 10c5883a add r2,r2,r3 + 1018690: 10800017 ldw r2,0(r2) + 1018694: 1004c03a cmpne r2,r2,zero + 1018698: 1000131e bne r2,zero,10186e8 + { + alt_fd_list[i].dev = dev; + 101869c: e0bffd17 ldw r2,-12(fp) + 10186a0: 00c040b4 movhi r3,258 + 10186a4: 18e69f04 addi r3,r3,-25988 + 10186a8: 10800324 muli r2,r2,12 + 10186ac: 10c7883a add r3,r2,r3 + 10186b0: e0bfff17 ldw r2,-4(fp) + 10186b4: 18800015 stw r2,0(r3) + if (i > alt_max_fd) + 10186b8: 008040b4 movhi r2,258 + 10186bc: 10aba004 addi r2,r2,-20864 + 10186c0: 10c00017 ldw r3,0(r2) + 10186c4: e0bffd17 ldw r2,-12(fp) + 10186c8: 1880040e bge r3,r2,10186dc + { + alt_max_fd = i; + 10186cc: 00c040b4 movhi r3,258 + 10186d0: 18eba004 addi r3,r3,-20864 + 10186d4: e0bffd17 ldw r2,-12(fp) + 10186d8: 18800015 stw r2,0(r3) + } + rc = i; + 10186dc: e0bffd17 ldw r2,-12(fp) + 10186e0: e0bffc15 stw r2,-16(fp) + goto alt_get_fd_exit; + 10186e4: 00000606 br 1018700 + * indicates the highest file descriptor ever allocated. This is used to + * improve efficency when searching the file descriptor list, and + * therefore reduce contention on the alt_fd_list_lock semaphore. + */ + + for (i = 0; i < ALT_MAX_FD; i++) + 10186e8: e0bffd17 ldw r2,-12(fp) + 10186ec: 10800044 addi r2,r2,1 + 10186f0: e0bffd15 stw r2,-12(fp) + 10186f4: e0bffd17 ldw r2,-12(fp) + 10186f8: 10800810 cmplti r2,r2,32 + 10186fc: 103fdf1e bne r2,zero,101867c + /* + * Release the alt_fd_list_lock semaphore now that we are done with the + * file descriptor pool. + */ + + ALT_SEM_POST(alt_fd_list_lock); + 1018700: 008040b4 movhi r2,258 + 1018704: 10b30804 addi r2,r2,-13280 + 1018708: 11000017 ldw r4,0(r2) + 101870c: 10132100 call 1013210 + + return rc; + 1018710: e0bffc17 ldw r2,-16(fp) +} + 1018714: e037883a mov sp,fp + 1018718: dfc00117 ldw ra,4(sp) + 101871c: df000017 ldw fp,0(sp) + 1018720: dec00204 addi sp,sp,8 + 1018724: f800283a ret + +01018728 : + * alt_icache_flush() is called to flush the instruction cache for a memory + * region of length "len" bytes, starting at address "start". + */ + +void alt_icache_flush (void* start, alt_u32 len) +{ + 1018728: defffb04 addi sp,sp,-20 + 101872c: df000415 stw fp,16(sp) + 1018730: df000404 addi fp,sp,16 + 1018734: e13ffe15 stw r4,-8(fp) + 1018738: e17fff15 stw r5,-4(fp) + + /* + * This is the most we would ever need to flush. + */ + + if (len > NIOS2_ICACHE_SIZE) + 101873c: e0bfff17 ldw r2,-4(fp) + 1018740: 10880070 cmpltui r2,r2,8193 + 1018744: 1000021e bne r2,zero,1018750 + { + len = NIOS2_ICACHE_SIZE; + 1018748: 00880004 movi r2,8192 + 101874c: e0bfff15 stw r2,-4(fp) + } + + end = ((char*) start) + len; + 1018750: e0fffe17 ldw r3,-8(fp) + 1018754: e0bfff17 ldw r2,-4(fp) + 1018758: 1885883a add r2,r3,r2 + 101875c: e0bffc15 stw r2,-16(fp) + + for (i = start; i < end; i+= NIOS2_ICACHE_LINE_SIZE) + 1018760: e0bffe17 ldw r2,-8(fp) + 1018764: e0bffd15 stw r2,-12(fp) + 1018768: 00000506 br 1018780 + { + __asm__ volatile ("flushi %0" :: "r" (i)); + 101876c: e0bffd17 ldw r2,-12(fp) + 1018770: 1000603a flushi r2 + len = NIOS2_ICACHE_SIZE; + } + + end = ((char*) start) + len; + + for (i = start; i < end; i+= NIOS2_ICACHE_LINE_SIZE) + 1018774: e0bffd17 ldw r2,-12(fp) + 1018778: 10800804 addi r2,r2,32 + 101877c: e0bffd15 stw r2,-12(fp) + 1018780: e0fffd17 ldw r3,-12(fp) + 1018784: e0bffc17 ldw r2,-16(fp) + 1018788: 18bff836 bltu r3,r2,101876c + * For an unaligned flush request, we've got one more line left. + * Note that this is dependent on NIOS2_ICACHE_LINE_SIZE to be a + * multiple of 2 (which it always is). + */ + + if (((alt_u32) start) & (NIOS2_ICACHE_LINE_SIZE - 1)) + 101878c: e0bffe17 ldw r2,-8(fp) + 1018790: 108007cc andi r2,r2,31 + 1018794: 1005003a cmpeq r2,r2,zero + 1018798: 1000021e bne r2,zero,10187a4 + { + __asm__ volatile ("flushi %0" :: "r" (i)); + 101879c: e0bffd17 ldw r2,-12(fp) + 10187a0: 1000603a flushi r2 + /* + * Having flushed the cache, flush any stale instructions in the + * pipeline + */ + + __asm__ volatile ("flushp"); + 10187a4: 0000203a flushp + +#endif /* NIOS2_ICACHE_SIZE > 0 */ +} + 10187a8: e037883a mov sp,fp + 10187ac: df000017 ldw fp,0(sp) + 10187b0: dec00104 addi sp,sp,4 + 10187b4: f800283a ret + +010187b8 : + 10187b8: 200b883a mov r5,r4 + 10187bc: 000d883a mov r6,zero + 10187c0: 0009883a mov r4,zero + 10187c4: 000f883a mov r7,zero + 10187c8: 10188781 jmpi 1018878 <__register_exitproc> + +010187cc : + 10187cc: defffe04 addi sp,sp,-8 + 10187d0: 000b883a mov r5,zero + 10187d4: dc000015 stw r16,0(sp) + 10187d8: dfc00115 stw ra,4(sp) + 10187dc: 2021883a mov r16,r4 + 10187e0: 10189b00 call 10189b0 <__call_exitprocs> + 10187e4: 008040b4 movhi r2,258 + 10187e8: 10ab9904 addi r2,r2,-20892 + 10187ec: 11000017 ldw r4,0(r2) + 10187f0: 20800f17 ldw r2,60(r4) + 10187f4: 10000126 beq r2,zero,10187fc + 10187f8: 103ee83a callr r2 + 10187fc: 8009883a mov r4,r16 + 1018800: 100c4380 call 100c438 <_exit> + +01018804 : + 1018804: 00c000c4 movi r3,3 + 1018808: 1980032e bgeu r3,r6,1018818 + 101880c: 2144b03a or r2,r4,r5 + 1018810: 10c4703a and r2,r2,r3 + 1018814: 10000f26 beq r2,zero,1018854 + 1018818: 31ffffc4 addi r7,r6,-1 + 101881c: 3000061e bne r6,zero,1018838 + 1018820: 00000a06 br 101884c + 1018824: 39ffffc4 addi r7,r7,-1 + 1018828: 00bfffc4 movi r2,-1 + 101882c: 21000044 addi r4,r4,1 + 1018830: 29400044 addi r5,r5,1 + 1018834: 38800526 beq r7,r2,101884c + 1018838: 20c00003 ldbu r3,0(r4) + 101883c: 28800003 ldbu r2,0(r5) + 1018840: 18bff826 beq r3,r2,1018824 + 1018844: 1885c83a sub r2,r3,r2 + 1018848: f800283a ret + 101884c: 0005883a mov r2,zero + 1018850: f800283a ret + 1018854: 180f883a mov r7,r3 + 1018858: 20c00017 ldw r3,0(r4) + 101885c: 28800017 ldw r2,0(r5) + 1018860: 18bfed1e bne r3,r2,1018818 + 1018864: 31bfff04 addi r6,r6,-4 + 1018868: 21000104 addi r4,r4,4 + 101886c: 29400104 addi r5,r5,4 + 1018870: 39bff936 bltu r7,r6,1018858 + 1018874: 003fe806 br 1018818 + +01018878 <__register_exitproc>: + 1018878: defffa04 addi sp,sp,-24 + 101887c: 008040b4 movhi r2,258 + 1018880: 10ab9904 addi r2,r2,-20892 + 1018884: dc000015 stw r16,0(sp) + 1018888: 14000017 ldw r16,0(r2) + 101888c: dd000415 stw r20,16(sp) + 1018890: 2829883a mov r20,r5 + 1018894: 81405217 ldw r5,328(r16) + 1018898: dcc00315 stw r19,12(sp) + 101889c: dc800215 stw r18,8(sp) + 10188a0: dc400115 stw r17,4(sp) + 10188a4: dfc00515 stw ra,20(sp) + 10188a8: 2023883a mov r17,r4 + 10188ac: 3027883a mov r19,r6 + 10188b0: 3825883a mov r18,r7 + 10188b4: 28002526 beq r5,zero,101894c <__register_exitproc+0xd4> + 10188b8: 29000117 ldw r4,4(r5) + 10188bc: 008007c4 movi r2,31 + 10188c0: 11002716 blt r2,r4,1018960 <__register_exitproc+0xe8> + 10188c4: 8800101e bne r17,zero,1018908 <__register_exitproc+0x90> + 10188c8: 2105883a add r2,r4,r4 + 10188cc: 1085883a add r2,r2,r2 + 10188d0: 20c00044 addi r3,r4,1 + 10188d4: 1145883a add r2,r2,r5 + 10188d8: 0009883a mov r4,zero + 10188dc: 15000215 stw r20,8(r2) + 10188e0: 28c00115 stw r3,4(r5) + 10188e4: 2005883a mov r2,r4 + 10188e8: dfc00517 ldw ra,20(sp) + 10188ec: dd000417 ldw r20,16(sp) + 10188f0: dcc00317 ldw r19,12(sp) + 10188f4: dc800217 ldw r18,8(sp) + 10188f8: dc400117 ldw r17,4(sp) + 10188fc: dc000017 ldw r16,0(sp) + 1018900: dec00604 addi sp,sp,24 + 1018904: f800283a ret + 1018908: 29802204 addi r6,r5,136 + 101890c: 00800044 movi r2,1 + 1018910: 110e983a sll r7,r2,r4 + 1018914: 30c04017 ldw r3,256(r6) + 1018918: 2105883a add r2,r4,r4 + 101891c: 1085883a add r2,r2,r2 + 1018920: 1185883a add r2,r2,r6 + 1018924: 19c6b03a or r3,r3,r7 + 1018928: 14802015 stw r18,128(r2) + 101892c: 14c00015 stw r19,0(r2) + 1018930: 00800084 movi r2,2 + 1018934: 30c04015 stw r3,256(r6) + 1018938: 88bfe31e bne r17,r2,10188c8 <__register_exitproc+0x50> + 101893c: 30804117 ldw r2,260(r6) + 1018940: 11c4b03a or r2,r2,r7 + 1018944: 30804115 stw r2,260(r6) + 1018948: 003fdf06 br 10188c8 <__register_exitproc+0x50> + 101894c: 008040b4 movhi r2,258 + 1018950: 1099fe04 addi r2,r2,26616 + 1018954: 100b883a mov r5,r2 + 1018958: 80805215 stw r2,328(r16) + 101895c: 003fd606 br 10188b8 <__register_exitproc+0x40> + 1018960: 00804034 movhi r2,256 + 1018964: 1089f204 addi r2,r2,10184 + 1018968: 1000021e bne r2,zero,1018974 <__register_exitproc+0xfc> + 101896c: 013fffc4 movi r4,-1 + 1018970: 003fdc06 br 10188e4 <__register_exitproc+0x6c> + 1018974: 01006404 movi r4,400 + 1018978: 103ee83a callr r2 + 101897c: 1007883a mov r3,r2 + 1018980: 103ffa26 beq r2,zero,101896c <__register_exitproc+0xf4> + 1018984: 80805217 ldw r2,328(r16) + 1018988: 180b883a mov r5,r3 + 101898c: 18000115 stw zero,4(r3) + 1018990: 18800015 stw r2,0(r3) + 1018994: 80c05215 stw r3,328(r16) + 1018998: 18006215 stw zero,392(r3) + 101899c: 18006315 stw zero,396(r3) + 10189a0: 0009883a mov r4,zero + 10189a4: 883fc826 beq r17,zero,10188c8 <__register_exitproc+0x50> + 10189a8: 003fd706 br 1018908 <__register_exitproc+0x90> + +010189ac : + 10189ac: f800283a ret + +010189b0 <__call_exitprocs>: + 10189b0: 008040b4 movhi r2,258 + 10189b4: 10ab9904 addi r2,r2,-20892 + 10189b8: 10800017 ldw r2,0(r2) + 10189bc: defff304 addi sp,sp,-52 + 10189c0: df000b15 stw fp,44(sp) + 10189c4: d8800115 stw r2,4(sp) + 10189c8: 00804034 movhi r2,256 + 10189cc: 1089ed04 addi r2,r2,10164 + 10189d0: 1005003a cmpeq r2,r2,zero + 10189d4: d8800215 stw r2,8(sp) + 10189d8: d8800117 ldw r2,4(sp) + 10189dc: dd400815 stw r21,32(sp) + 10189e0: dd000715 stw r20,28(sp) + 10189e4: 10805204 addi r2,r2,328 + 10189e8: dfc00c15 stw ra,48(sp) + 10189ec: ddc00a15 stw r23,40(sp) + 10189f0: dd800915 stw r22,36(sp) + 10189f4: dcc00615 stw r19,24(sp) + 10189f8: dc800515 stw r18,20(sp) + 10189fc: dc400415 stw r17,16(sp) + 1018a00: dc000315 stw r16,12(sp) + 1018a04: 282b883a mov r21,r5 + 1018a08: 2039883a mov fp,r4 + 1018a0c: d8800015 stw r2,0(sp) + 1018a10: 2829003a cmpeq r20,r5,zero + 1018a14: d8800117 ldw r2,4(sp) + 1018a18: 14405217 ldw r17,328(r2) + 1018a1c: 88001026 beq r17,zero,1018a60 <__call_exitprocs+0xb0> + 1018a20: ddc00017 ldw r23,0(sp) + 1018a24: 88800117 ldw r2,4(r17) + 1018a28: 8c802204 addi r18,r17,136 + 1018a2c: 143fffc4 addi r16,r2,-1 + 1018a30: 80000916 blt r16,zero,1018a58 <__call_exitprocs+0xa8> + 1018a34: 05bfffc4 movi r22,-1 + 1018a38: a000151e bne r20,zero,1018a90 <__call_exitprocs+0xe0> + 1018a3c: 8409883a add r4,r16,r16 + 1018a40: 2105883a add r2,r4,r4 + 1018a44: 1485883a add r2,r2,r18 + 1018a48: 10c02017 ldw r3,128(r2) + 1018a4c: a8c01126 beq r21,r3,1018a94 <__call_exitprocs+0xe4> + 1018a50: 843fffc4 addi r16,r16,-1 + 1018a54: 85bff81e bne r16,r22,1018a38 <__call_exitprocs+0x88> + 1018a58: d8800217 ldw r2,8(sp) + 1018a5c: 10003126 beq r2,zero,1018b24 <__call_exitprocs+0x174> + 1018a60: dfc00c17 ldw ra,48(sp) + 1018a64: df000b17 ldw fp,44(sp) + 1018a68: ddc00a17 ldw r23,40(sp) + 1018a6c: dd800917 ldw r22,36(sp) + 1018a70: dd400817 ldw r21,32(sp) + 1018a74: dd000717 ldw r20,28(sp) + 1018a78: dcc00617 ldw r19,24(sp) + 1018a7c: dc800517 ldw r18,20(sp) + 1018a80: dc400417 ldw r17,16(sp) + 1018a84: dc000317 ldw r16,12(sp) + 1018a88: dec00d04 addi sp,sp,52 + 1018a8c: f800283a ret + 1018a90: 8409883a add r4,r16,r16 + 1018a94: 88c00117 ldw r3,4(r17) + 1018a98: 2105883a add r2,r4,r4 + 1018a9c: 1445883a add r2,r2,r17 + 1018aa0: 18ffffc4 addi r3,r3,-1 + 1018aa4: 11800217 ldw r6,8(r2) + 1018aa8: 1c001526 beq r3,r16,1018b00 <__call_exitprocs+0x150> + 1018aac: 10000215 stw zero,8(r2) + 1018ab0: 303fe726 beq r6,zero,1018a50 <__call_exitprocs+0xa0> + 1018ab4: 00c00044 movi r3,1 + 1018ab8: 1c06983a sll r3,r3,r16 + 1018abc: 90804017 ldw r2,256(r18) + 1018ac0: 8cc00117 ldw r19,4(r17) + 1018ac4: 1884703a and r2,r3,r2 + 1018ac8: 10001426 beq r2,zero,1018b1c <__call_exitprocs+0x16c> + 1018acc: 90804117 ldw r2,260(r18) + 1018ad0: 1884703a and r2,r3,r2 + 1018ad4: 10000c1e bne r2,zero,1018b08 <__call_exitprocs+0x158> + 1018ad8: 2105883a add r2,r4,r4 + 1018adc: 1485883a add r2,r2,r18 + 1018ae0: 11400017 ldw r5,0(r2) + 1018ae4: e009883a mov r4,fp + 1018ae8: 303ee83a callr r6 + 1018aec: 88800117 ldw r2,4(r17) + 1018af0: 98bfc81e bne r19,r2,1018a14 <__call_exitprocs+0x64> + 1018af4: b8800017 ldw r2,0(r23) + 1018af8: 147fd526 beq r2,r17,1018a50 <__call_exitprocs+0xa0> + 1018afc: 003fc506 br 1018a14 <__call_exitprocs+0x64> + 1018b00: 8c000115 stw r16,4(r17) + 1018b04: 003fea06 br 1018ab0 <__call_exitprocs+0x100> + 1018b08: 2105883a add r2,r4,r4 + 1018b0c: 1485883a add r2,r2,r18 + 1018b10: 11000017 ldw r4,0(r2) + 1018b14: 303ee83a callr r6 + 1018b18: 003ff406 br 1018aec <__call_exitprocs+0x13c> + 1018b1c: 303ee83a callr r6 + 1018b20: 003ff206 br 1018aec <__call_exitprocs+0x13c> + 1018b24: 88800117 ldw r2,4(r17) + 1018b28: 1000081e bne r2,zero,1018b4c <__call_exitprocs+0x19c> + 1018b2c: 89000017 ldw r4,0(r17) + 1018b30: 20000726 beq r4,zero,1018b50 <__call_exitprocs+0x1a0> + 1018b34: b9000015 stw r4,0(r23) + 1018b38: 8809883a mov r4,r17 + 1018b3c: 10027b40 call 10027b4 + 1018b40: bc400017 ldw r17,0(r23) + 1018b44: 883fb71e bne r17,zero,1018a24 <__call_exitprocs+0x74> + 1018b48: 003fc506 br 1018a60 <__call_exitprocs+0xb0> + 1018b4c: 89000017 ldw r4,0(r17) + 1018b50: 882f883a mov r23,r17 + 1018b54: 2023883a mov r17,r4 + 1018b58: 883fb21e bne r17,zero,1018a24 <__call_exitprocs+0x74> + 1018b5c: 003fc006 br 1018a60 <__call_exitprocs+0xb0> + 1018b60: 0201ffff 0x201ffff + 1018b64: 883a0000 call 883a000 <__alt_data_end+0x683a000> + 1018b68: 010d0bff 0x10d0bff + 1018b6c: 01000004 movi r4,0 + 1018b70: 00000101 jmpi 10 + 1018b74: 00000000 call 0 + 1018b78: 010d0bff 0x10d0bff + 1018b7c: 01000004 movi r4,0 + 1018b80: 00000101 jmpi 10 + 1018b84: 00000000 call 0 + 1018b88: 010d0bff 0x10d0bff + 1018b8c: 01000004 movi r4,0 + 1018b90: 00000101 jmpi 10 + 1018b94: 00000000 call 0 + 1018b98: 01090bff 0x1090bff + 1018b9c: 7f010002 0x7f010002 + ... + 1018ba8: 01090bff 0x1090bff + 1018bac: 7f010002 0x7f010002 + ... + 1018bb8: 010d0bff 0x10d0bff + 1018bbc: 7f010002 0x7f010002 + 1018bc0: 00000000 call 0 + 1018bc4: 01018d9c xori r4,zero,1590 + 1018bc8: 00000001 jmpi 0 + 1018bcc: 01000704 movi r4,28 + 1018bd0: 010189ac andhi r4,zero,1574 diff --git a/MCandWifiTestDE0/Software/Archive/MCTest/Makefile b/MCandWifiTestDE0/Software/Archive/MCTest/Makefile new file mode 100644 index 00000000..9e1d6dc7 --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest/Makefile @@ -0,0 +1,1087 @@ +#------------------------------------------------------------------------------ +# VARIABLES APPENDED TO BY INCLUDED MAKEFILE FRAGMENTS +#------------------------------------------------------------------------------ + +# List of include directories for -I compiler option (-I added when used). +# Includes the BSP. +ALT_INCLUDE_DIRS := + +# List of library directories for -L linker option (-L added when used). +# Includes the BSP. +ALT_LIBRARY_DIRS := + +# List of library names for -l linker option (-l added when used). +# Includes the BSP. +ALT_LIBRARY_NAMES := + +# List of library names for -msys-lib linker option (-msys-lib added when used). +# These are libraries that might be located in the BSP and depend on the BSP +# library, or vice versa +ALT_BSP_DEP_LIBRARY_NAMES := + +# List of dependencies for the linker. This is usually the full pathname +# of each library (*.a) file. +# Includes the BSP. +ALT_LDDEPS := + +# List of root library directories that support running make to build them. +# Includes the BSP and any ALT libraries. +MAKEABLE_LIBRARY_ROOT_DIRS := + +# Generic flags passed to the compiler for different types of input files. +ALT_CFLAGS := +ALT_CXXFLAGS := +ALT_CPPFLAGS := +ALT_ASFLAGS := +ALT_LDFLAGS := + + +#------------------------------------------------------------------------------ +# The adjust-path macro +# +# If COMSPEC/ComSpec is defined, Make is launched from Windows through +# Cygwin. The adjust-path macro converts absolute windows paths into +# unix style paths (Example: c:/dir -> /c/dir). This will ensture +# paths are readable by GNU Make. +# +# If COMSPEC/ComSpec is not defined, Make is launched from linux, and no +# adjustment is necessary +# +#------------------------------------------------------------------------------ + +ifndef COMSPEC +ifdef ComSpec +COMSPEC = $(ComSpec) +endif # ComSpec +endif # COMSPEC + +ifdef COMSPEC # if Windows OS + +ifeq ($(MAKE_VERSION),3.81) +# +# adjust-path/adjust-path-mixed for Mingw Gnu Make on Windows +# +# Example Usage: +# $(call adjust-path,c:/aaa/bbb) => /c/aaa/bbb +# $(call adjust-path-mixed,/c/aaa/bbb) => c:/aaa/bbb +# $(call adjust-path-mixed,/cygdrive/c/aaa/bbb) => c:/aaa/bbb +# + +# +# adjust-path +# - converts back slash characters into forward slashes +# - if input arg ($1) is an empty string then return the empty string +# - if input arg ($1) does not contain the string ":/", then return input arg +# - using sed, convert mixed path [c:/...] into mingw path [/c/...] +define adjust-path +$(strip \ +$(if $1,\ +$(if $(findstring :/,$(subst \,/,$1)),\ +$(shell echo $(subst \,/,$1) | sed -e 's,^\([a-zA-Z]\):/,/\1/,'),\ +$(subst \,/,$1)))) +endef + +# +# adjust-path-mixed +# - converts back slash characters into forward slashes +# - if input arg ($1) is an empty string then return the empty string +# - if input arg ($1) does not begin with a forward slash '/' char, then +# return input arg +# - using sed, convert mingw path [/c/...] or cygwin path [/c/cygdrive/...] +# into a mixed path [c:/...] +define adjust-path-mixed +$(strip \ +$(if $1,\ +$(if $(findstring $(subst \,/,$1),$(patsubst /%,%,$(subst \,/,$1))),\ +$(subst \,/,$1),\ +$(shell echo $(subst \,/,$1) | sed -e 's,^/cygdrive/\([a-zA-Z]\)/,\1:/,' -e 's,^/\([a-zA-Z]\)/,\1:/,')))) +endef + +else # MAKE_VERSION != 3.81 (MAKE_VERSION == 3.80 or MAKE_VERSION == 3.79) +# +# adjust-path for Cygwin Gnu Make +# $(call adjust-path,c:/aaa/bbb) = /cygdrive/c/aaa/bbb +# $(call adjust-path-mixed,/cygdrive/c/aaa/bbb) = c:/aaa/bbb +# +adjust-path = $(if $1,$(shell cygpath -u "$1"),) +adjust-path-mixed = $(if $1,$(shell cygpath -m "$1"),) +endif + +else # !COMSPEC + +adjust-path = $1 +adjust-path-mixed = $1 + +endif # COMSPEC + + +#vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv +# GENERATED SETTINGS START v +#vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv + +#START GENERATED +ACTIVE_BUILD_CONFIG := default +BUILD_CONFIGS := default + +# The following TYPE comment allows tools to identify the 'type' of target this +# makefile is associated with. +# TYPE: APP_MAKEFILE + +# This following VERSION comment indicates the version of the tool used to +# generate this makefile. A makefile variable is provided for VERSION as well. +# ACDS_VERSION: 12.1sp1 +ACDS_VERSION := 12.1sp1 + +# This following BUILD_NUMBER comment indicates the build number of the tool +# used to generate this makefile. +# BUILD_NUMBER: 243 + +# Define path to the application ELF. +# It may be used by the makefile fragments so is defined before including them. +# +ELF := MCTest.elf + +# Paths to C, C++, and assembly source files. +C_SRCS := +CXX_SRCS += main.cpp +CXX_SRCS += MotorHandler.cpp +ASM_SRCS := + + +# Path to root of object file tree. +OBJ_ROOT_DIR := obj + +# Options to control objdump. +CREATE_OBJDUMP := 1 +OBJDUMP_INCLUDE_SOURCE := 1 +OBJDUMP_FULL_CONTENTS := 0 + +# Options to enable/disable optional files. +CREATE_ELF_DERIVED_FILES := 0 +CREATE_LINKER_MAP := 1 + +# Common arguments for ALT_CFLAGSs +APP_CFLAGS_DEFINED_SYMBOLS := +APP_CFLAGS_UNDEFINED_SYMBOLS := +APP_CFLAGS_OPTIMIZATION := -O0 +APP_CFLAGS_DEBUG_LEVEL := -g +APP_CFLAGS_WARNINGS := -Wall +APP_CFLAGS_USER_FLAGS := + +APP_ASFLAGS_USER := +APP_LDFLAGS_USER := + +# Linker options that have default values assigned later if not +# assigned here. +LINKER_SCRIPT := +CRT0 := +SYS_LIB := + +# Define path to the root of the BSP. +BSP_ROOT_DIR := ../MCTest_bsp/ + +# List of application specific include directories, library directories and library names +APP_INCLUDE_DIRS := +APP_LIBRARY_DIRS := +APP_LIBRARY_NAMES := + +# Pre- and post- processor settings. +BUILD_PRE_PROCESS := +BUILD_POST_PROCESS := + +QUARTUS_PROJECT_DIR := ../../ + + +#END GENERATED + +#^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +# GENERATED SETTINGS END ^ +#^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + + +#------------------------------------------------------------------------------ +# DEFAULT TARGET +#------------------------------------------------------------------------------ + +# Define the variable used to echo output if not already defined. +ifeq ($(ECHO),) +ECHO := echo +endif + +# Put "all" rule before included makefile fragments because they may +# define rules and we don't want one of those to become the default rule. +.PHONY : all + +all: + @$(ECHO) [$(APP_NAME) build complete] + +all : build_pre_process libs app build_post_process + + +#------------------------------------------------------------------------------ +# VARIABLES DEPENDENT ON GENERATED CONTENT +#------------------------------------------------------------------------------ + +# Define object file directory per build configuration +CONFIG_OBJ_DIR := $(OBJ_ROOT_DIR)/$(ACTIVE_BUILD_CONFIG) + +ifeq ($(BSP_ROOT_DIR),) +$(error Edit Makefile and provide a value for BSP_ROOT_DIR) +endif + +ifeq ($(wildcard $(BSP_ROOT_DIR)),) +$(error BSP directory does not exist: $(BSP_ROOT_DIR)) +endif + +# Define absolute path to the root of the BSP. +ABS_BSP_ROOT_DIR := $(call adjust-path-mixed,$(shell cd "$(BSP_ROOT_DIR)"; pwd)) + +# Include makefile fragments. Define variable ALT_LIBRARY_ROOT_DIR before +# including each makefile fragment so that it knows the path to itself. +BSP_INCLUDE_FILE := $(BSP_ROOT_DIR)/public.mk +ALT_LIBRARY_ROOT_DIR := $(BSP_ROOT_DIR) +include $(BSP_INCLUDE_FILE) +# C2H will need this to touch the BSP public.mk and avoid the sopc file +# out-of-date error during a BSP make +ABS_BSP_INCLUDE_FILE := $(ABS_BSP_ROOT_DIR)/public.mk + + +ifneq ($(WARNING.SMALL_STACK_SIZE),) +# This WARNING is here to protect you from unknowingly using a very small stack +# If the warning is set, increase your stack size or enable the BSP small stack +# setting to eliminate the warning +$(warning WARNING: $(WARNING.SMALL_STACK_SIZE)) +endif + + +# If the BSP public.mk indicates that ALT_SIM_OPTIMIZE is set, rename the ELF +# by prefixing it with RUN_ON_HDL_SIMULATOR_ONLY_. +ifneq ($(filter -DALT_SIM_OPTIMIZE,$(ALT_CPPFLAGS)),) +ELF := RUN_ON_HDL_SIMULATOR_ONLY_$(ELF) +endif + +# If the BSP public.mk indicates that ALT_PROVIDE_GMON is set, add option to +# download_elf target +ifneq ($(filter -DALT_PROVIDE_GMON,$(ALT_CPPFLAGS)),) +GMON_OUT_FILENAME := gmon.out +WRITE_GMON_OPTION := --write-gmon $(GMON_OUT_FILENAME) +endif + +# Name of ELF application. +APP_NAME := $(basename $(ELF)) + +# Set to defaults if variables not already defined in settings. +ifeq ($(LINKER_SCRIPT),) +LINKER_SCRIPT := $(BSP_LINKER_SCRIPT) +endif +ifeq ($(CRT0),) +CRT0 := $(BSP_CRT0) +endif +ifeq ($(SYS_LIB),) +SYS_LIB := $(BSP_SYS_LIB) +endif + +OBJDUMP_NAME := $(APP_NAME).objdump +OBJDUMP_FLAGS := --disassemble --syms --all-header +ifeq ($(OBJDUMP_INCLUDE_SOURCE),1) +OBJDUMP_FLAGS += --source +endif +ifeq ($(OBJDUMP_FULL_CONTENTS),1) +OBJDUMP_FLAGS += --full-contents +endif + +# Create list of linker dependencies (*.a files). +APP_LDDEPS := $(ALT_LDDEPS) $(LDDEPS) + +# Take lists and add required prefixes. +APP_INC_DIRS := $(addprefix -I, $(ALT_INCLUDE_DIRS) $(APP_INCLUDE_DIRS) $(INC_DIRS)) +ASM_INC_PREFIX := -Wa,-I +APP_ASM_INC_DIRS := $(addprefix $(ASM_INC_PREFIX), $(ALT_INCLUDE_DIRS) $(APP_INCLUDE_DIRS) $(INC_DIRS)) +APP_LIB_DIRS := $(addprefix -L, $(ALT_LIBRARY_DIRS) $(APP_LIBRARY_DIRS) $(LIB_DIRS)) +APP_LIBS := $(addprefix -l, $(ALT_LIBRARY_NAMES) $(APP_LIBRARY_NAMES) $(LIBS)) + +ifneq ($(AVOID_NIOS2_GCC3_OPTIONS),) + +# +# Avoid Nios II GCC 3.X options. +# + +# Detect if small newlib C library is requested. +# If yes, remove the -msmallc option because it is +# now handled by other means. +ifneq ($(filter -msmallc,$(ALT_LDFLAGS)),) + ALT_LDFLAGS := $(filter-out -msmallc,$(ALT_LDFLAGS)) + ALT_C_LIBRARY := smallc +else + ALT_C_LIBRARY := c +endif + +# Put each BSP dependent library in a group to avoid circular dependencies. +APP_BSP_DEP_LIBS := $(foreach l,$(ALT_BSP_DEP_LIBRARY_NAMES),-Wl,--start-group -l$(ALT_C_LIBRARY) -lgcc -l$(l) -Wl,--end-group) + +else # !AVOID_NIOS2_GCC3_OPTIONS + +# +# Use Nios II GCC 3.X options. +# +APP_BSP_DEP_LIBS := $(addprefix -msys-lib=, $(ALT_BSP_DEP_LIBRARY_NAMES)) + +endif # !AVOID_NIOS2_GCC3_OPTIONS + +# Arguments for the C preprocessor, C/C++ compiler, assembler, and linker. +APP_CFLAGS := $(APP_CFLAGS_DEFINED_SYMBOLS) \ + $(APP_CFLAGS_UNDEFINED_SYMBOLS) \ + $(APP_CFLAGS_OPTIMIZATION) \ + $(APP_CFLAGS_DEBUG_LEVEL) \ + $(APP_CFLAGS_WARNINGS) \ + $(APP_CFLAGS_USER_FLAGS) \ + $(ALT_CFLAGS) \ + $(CFLAGS) + +# Arguments only for the C++ compiler. +APP_CXXFLAGS := $(ALT_CXXFLAGS) $(CXXFLAGS) + +# Arguments only for the C preprocessor. +# Prefix each include directory with -I. +APP_CPPFLAGS := $(APP_INC_DIRS) \ + $(ALT_CPPFLAGS) \ + $(CPPFLAGS) + +# Arguments only for the assembler. +APP_ASFLAGS := $(APP_ASM_INC_DIRS) \ + $(ALT_ASFLAGS) \ + $(APP_ASFLAGS_USER) \ + $(ASFLAGS) + +# Arguments only for the linker. +APP_LDFLAGS := $(APP_LDFLAGS_USER) + +ifneq ($(LINKER_SCRIPT),) +APP_LDFLAGS += -T'$(LINKER_SCRIPT)' +endif + +ifneq ($(AVOID_NIOS2_GCC3_OPTIONS),) + +# Avoid Nios II GCC 3.x options. +ifneq ($(CRT0),) +APP_LDFLAGS += $(CRT0) +endif + +# The equivalent of the -msys-lib option is provided +# by the GROUP() command in the linker script. +# Note this means the SYS_LIB variable is now ignored. + +else # !AVOID_NIOS2_GCC3_OPTIONS + +# Use Nios II GCC 3.x options. +ifneq ($(CRT0),) +APP_LDFLAGS += -msys-crt0='$(CRT0)' +endif +ifneq ($(SYS_LIB),) +APP_LDFLAGS += -msys-lib=$(SYS_LIB) +endif + +endif # !AVOID_NIOS2_GCC3_OPTIONS + +APP_LDFLAGS += \ + $(APP_LIB_DIRS) \ + $(ALT_LDFLAGS) \ + $(LDFLAGS) + +LINKER_MAP_NAME := $(APP_NAME).map +ifeq ($(CREATE_LINKER_MAP), 1) +APP_LDFLAGS += -Wl,-Map=$(LINKER_MAP_NAME) +endif + +# QUARTUS_PROJECT_DIR and SOPC_NAME need to be defined if you want the +# mem_init_install target of the mem_init.mk (located in the associated BSP) +# to know how to copy memory initialization files (e.g. .dat, .hex) into +# directories required for Quartus compilation or RTL simulation. + +# Defining QUARTUS_PROJECT_DIR causes mem_init_install to copy memory +# initialization files into your Quartus project directory. This is required +# to provide the initial memory contents of FPGA memories that can be +# initialized by the programming file (.sof) or Hardcopy ROMs. It is also used +# for VHDL simulation of on-chip memories. + +# Defining SOPC_NAME causes the mem_init_install target to copy memory +# initialization files into your RTL simulation directory. This is required +# to provide the initial memory contents of all memories that can be +# initialized by RTL simulation. This variable should be set to the same name +# as your SOPC Builder system name. For example, if you have a system called +# "foo.sopc", this variable should be set to "foo". + +# If SOPC_NAME is not set and QUARTUS_PROJECT_DIR is set, then derive SOPC_NAME. +ifeq ($(SOPC_NAME),) +ifneq ($(QUARTUS_PROJECT_DIR),) +SOPC_NAME := $(basename $(notdir $(wildcard $(QUARTUS_PROJECT_DIR)/*.sopcinfo))) +endif +endif + +# Defining JDI_FILE is required to specify the JTAG Debug Information File +# path. This file is generated by Quartus, and is needed along with the +# .sopcinfo file to resolve processor instance ID's from names in a multi-CPU +# systems. For multi-CPU systems, the processor instance ID is used to select +# from multiple CPU's during ELF download. + +# Both JDI_FILE and SOPCINFO_FILE are provided by the BSP if they found during +# BSP creation. If JDI_FILE is not set and QUARTUS_PROJECT_DIR is set, then +# derive JDI_FILE. We do not attempt to derive SOPCINFO_FILE since there may be +# multiple .sopcinfo files in a Quartus project. +ifeq ($(JDI_FILE),) +ifneq ($(QUARTUS_PROJECT_DIR),) +JDI_FILE := $(wildcard $(QUARTUS_PROJECT_DIR)/*.jdi) +endif +endif + +# Path to root runtime directory used for hdl simulation +RUNTIME_ROOT_DIR := $(CONFIG_OBJ_DIR)/runtime + + + +#------------------------------------------------------------------------------ +# MAKEFILE INCLUDES DEPENDENT ON GENERATED CONTENT +#------------------------------------------------------------------------------ +# mem_init.mk is a generated makefile fragment. This file defines all targets +# used to generate HDL initialization simulation files and pre-initialized +# onchip memory files. +MEM_INIT_FILE := $(BSP_ROOT_DIR)/mem_init.mk +include $(MEM_INIT_FILE) + +# Create list of object files to be built using the list of source files. +# The source file hierarchy is preserved in the object tree. +# The supported file extensions are: +# +# .c - for C files +# .cxx .cc .cpp - for C++ files +# .S .s - for assembler files +# +# Handle source files specified by --src-dir & --src-rdir differently, to +# save some processing time in calling the adjust-path macro. + +OBJ_LIST_C := $(patsubst %.c,%.o,$(filter %.c,$(C_SRCS))) +OBJ_LIST_CPP := $(patsubst %.cpp,%.o,$(filter %.cpp,$(CXX_SRCS))) +OBJ_LIST_CXX := $(patsubst %.cxx,%.o,$(filter %.cxx,$(CXX_SRCS))) +OBJ_LIST_CC := $(patsubst %.cc,%.o,$(filter %.cc,$(CXX_SRCS))) +OBJ_LIST_S := $(patsubst %.S,%.o,$(filter %.S,$(ASM_SRCS))) +OBJ_LIST_SS := $(patsubst %.s,%.o,$(filter %.s,$(ASM_SRCS))) + +OBJ_LIST := $(sort $(OBJ_LIST_C) $(OBJ_LIST_CPP) $(OBJ_LIST_CXX) \ + $(OBJ_LIST_CC) $(OBJ_LIST_S) $(OBJ_LIST_SS)) + +SDIR_OBJ_LIST_C := $(patsubst %.c,%.o,$(filter %.c,$(SDIR_C_SRCS))) +SDIR_OBJ_LIST_CPP := $(patsubst %.cpp,%.o,$(filter %.cpp,$(SDIR_CXX_SRCS))) +SDIR_OBJ_LIST_CXX := $(patsubst %.cxx,%.o,$(filter %.cxx,$(SDIR_CXX_SRCS))) +SDIR_OBJ_LIST_CC := $(patsubst %.cc,%.o,$(filter %.cc,$(SDIR_CXX_SRCS))) +SDIR_OBJ_LIST_S := $(patsubst %.S,%.o,$(filter %.S,$(SDIR_ASM_SRCS))) +SDIR_OBJ_LIST_SS := $(patsubst %.s,%.o,$(filter %.s,$(SDIR_ASM_SRCS))) + +SDIR_OBJ_LIST := $(sort $(SDIR_OBJ_LIST_C) $(SDIR_OBJ_LIST_CPP) \ + $(SDIR_OBJ_LIST_CXX) $(SDIR_OBJ_LIST_CC) $(SDIR_OBJ_LIST_S) \ + $(SDIR_OBJ_LIST_SS)) + +# Relative-pathed objects that being with "../" are handled differently. +# +# Regular objects are created as +# $(CONFIG_OBJ_DIR)//.o +# where the path structure is maintained under the obj directory. This +# applies for both absolute and relative paths; in the absolute path +# case this means the entire source path will be recreated under the obj +# directory. This is done to allow two source files with the same name +# to be included as part of the project. +# +# Note: On Cygwin, the path recreated under the obj directory will be +# the cygpath -u output path. +# +# Relative-path objects that begin with "../" cause problems under this +# scheme, as $(CONFIG_OBJ_DIR)/..// can potentially put the object +# files anywhere in the system, creating clutter and polluting the source tree. +# As such, their paths are flattened - the object file created will be +# $(CONFIG_OBJ_DIR)/.o. Due to this, two files specified with +# "../" in the beginning cannot have the same name in the project. VPATH +# will be set for these sources to allow make to relocate the source file +# via %.o rules. +# +# The following lines separate the object list into the flatten and regular +# lists, and then handles them as appropriate. + +FLATTEN_OBJ_LIST := $(filter ../%,$(OBJ_LIST)) +FLATTEN_APP_OBJS := $(addprefix $(CONFIG_OBJ_DIR)/,$(notdir $(FLATTEN_OBJ_LIST))) + +REGULAR_OBJ_LIST := $(filter-out $(FLATTEN_OBJ_LIST),$(OBJ_LIST)) +REGULAR_OBJ_LIST_C := $(filter $(OBJ_LIST_C),$(REGULAR_OBJ_LIST)) +REGULAR_OBJ_LIST_CPP := $(filter $(OBJ_LIST_CPP),$(REGULAR_OBJ_LIST)) +REGULAR_OBJ_LIST_CXX := $(filter $(OBJ_LIST_CXX),$(REGULAR_OBJ_LIST)) +REGULAR_OBJ_LIST_CC := $(filter $(OBJ_LIST_CC),$(REGULAR_OBJ_LIST)) +REGULAR_OBJ_LIST_S := $(filter $(OBJ_LIST_S),$(REGULAR_OBJ_LIST)) +REGULAR_OBJ_LIST_SS := $(filter $(OBJ_LIST_SS),$(REGULAR_OBJ_LIST)) + +FLATTEN_SDIR_OBJ_LIST := $(filter ../%,$(SDIR_OBJ_LIST)) +FLATTEN_SDIR_APP_OBJS := $(addprefix $(CONFIG_OBJ_DIR)/,$(notdir $(FLATTEN_SDIR_OBJ_LIST))) + +REGULAR_SDIR_OBJ_LIST := $(filter-out $(FLATTEN_SDIR_OBJ_LIST),$(SDIR_OBJ_LIST)) +REGULAR_SDIR_OBJ_LIST_C := $(filter $(SDIR_OBJ_LIST_C),$(REGULAR_SDIR_OBJ_LIST)) +REGULAR_SDIR_OBJ_LIST_CPP := $(filter $(SDIR_OBJ_LIST_CPP),$(REGULAR_SDIR_OBJ_LIST)) +REGULAR_SDIR_OBJ_LIST_CXX := $(filter $(SDIR_OBJ_LIST_CXX),$(REGULAR_SDIR_OBJ_LIST)) +REGULAR_SDIR_OBJ_LIST_CC := $(filter $(SDIR_OBJ_LIST_CC),$(REGULAR_SDIR_OBJ_LIST)) +REGULAR_SDIR_OBJ_LIST_S := $(filter $(SDIR_OBJ_LIST_S),$(REGULAR_SDIR_OBJ_LIST)) +REGULAR_SDIR_OBJ_LIST_SS := $(filter $(SDIR_OBJ_LIST_SS),$(REGULAR_SDIR_OBJ_LIST)) + +VPATH := $(sort $(dir $(FLATTEN_OBJ_LIST)) $(dir $(FLATTEN_SDIR_OBJ_LIST))) + +APP_OBJS_C := $(addprefix $(CONFIG_OBJ_DIR)/,\ + $(REGULAR_SDIR_OBJ_LIST_C) \ + $(foreach s,$(REGULAR_OBJ_LIST_C),$(call adjust-path,$s))) + +APP_OBJS_CPP := $(addprefix $(CONFIG_OBJ_DIR)/,\ + $(REGULAR_SDIR_OBJ_LIST_CPP) \ + $(foreach s,$(REGULAR_OBJ_LIST_CPP),$(call adjust-path,$s))) + +APP_OBJS_CXX := $(addprefix $(CONFIG_OBJ_DIR)/,\ + $(REGULAR_SDIR_OBJ_LIST_CXX) \ + $(foreach s,$(REGULAR_OBJ_LIST_CXX),$(call adjust-path,$s))) + +APP_OBJS_CC := $(addprefix $(CONFIG_OBJ_DIR)/,\ + $(REGULAR_SDIR_OBJ_LIST_CC) \ + $(foreach s,$(REGULAR_OBJ_LIST_CC),$(call adjust-path,$s))) + +APP_OBJS_S := $(addprefix $(CONFIG_OBJ_DIR)/,\ + $(REGULAR_SDIR_OBJ_LIST_S) \ + $(foreach s,$(REGULAR_OBJ_LIST_S),$(call adjust-path,$s))) + +APP_OBJS_SS := $(addprefix $(CONFIG_OBJ_DIR)/,\ + $(REGULAR_SDIR_OBJ_LIST_SS) \ + $(foreach s,$(REGULAR_OBJ_LIST_SS),$(call adjust-path,$s))) + +APP_OBJS := $(APP_OBJS_C) $(APP_OBJS_CPP) $(APP_OBJS_CXX) $(APP_OBJS_CC) \ + $(APP_OBJS_S) $(APP_OBJS_SS) \ + $(FLATTEN_APP_OBJS) $(FLATTEN_SDIR_APP_OBJS) + +# Add any extra user-provided object files. +APP_OBJS += $(OBJS) + +# Create list of dependancy files for each object file. +APP_DEPS := $(APP_OBJS:.o=.d) + +# Patch the Elf file with system specific information + +# Patch the Elf with the name of the sopc system +ifneq ($(SOPC_NAME),) +ELF_PATCH_FLAG += --sopc_system_name $(SOPC_NAME) +endif + +# Patch the Elf with the absolute path to the Quartus Project Directory +ifneq ($(QUARTUS_PROJECT_DIR),) +ABS_QUARTUS_PROJECT_DIR := $(call adjust-path-mixed,$(shell cd "$(QUARTUS_PROJECT_DIR)"; pwd)) +ELF_PATCH_FLAG += --quartus_project_dir "$(ABS_QUARTUS_PROJECT_DIR)" +endif + +# Patch the Elf and download args with the JDI_FILE if specified +ifneq ($(wildcard $(JDI_FILE)),) +ELF_PATCH_FLAG += --jdi $(JDI_FILE) +DOWNLOAD_JDI_FLAG := --jdi $(JDI_FILE) +endif + +# Patch the Elf with the SOPCINFO_FILE if specified +ifneq ($(wildcard $(SOPCINFO_FILE)),) +ELF_PATCH_FLAG += --sopcinfo $(SOPCINFO_FILE) +endif + +# Use the DOWNLOAD_CABLE variable to specify which JTAG cable to use. +# This is not needed if you only have one cable. +ifneq ($(DOWNLOAD_CABLE),) +DOWNLOAD_CABLE_FLAG := --cable '$(DOWNLOAD_CABLE)' +endif + + +#------------------------------------------------------------------------------ +# BUILD PRE/POST PROCESS +#------------------------------------------------------------------------------ +build_pre_process : + $(BUILD_PRE_PROCESS) + +build_post_process : + $(BUILD_POST_PROCESS) + +.PHONY: build_pre_process build_post_process + + +#------------------------------------------------------------------------------ +# TOOLS +#------------------------------------------------------------------------------ + +# +# Set tool default variables if not already defined. +# If these are defined, they would typically be defined in an +# included makefile fragment. +# +ifeq ($(DEFAULT_CROSS_COMPILE),) +DEFAULT_CROSS_COMPILE := nios2-elf- +endif + +ifeq ($(DEFAULT_STACK_REPORT),) +DEFAULT_STACKREPORT := nios2-stackreport +endif + +ifeq ($(DEFAULT_DOWNLOAD),) +DEFAULT_DOWNLOAD := nios2-download +endif + +ifeq ($(DEFAULT_FLASHPROG),) +DEFAULT_FLASHPROG := nios2-flash-programmer +endif + +ifeq ($(DEFAULT_ELFPATCH),) +DEFAULT_ELFPATCH := nios2-elf-insert +endif + +ifeq ($(DEFAULT_RM),) +DEFAULT_RM := rm -f +endif + +ifeq ($(DEFAULT_CP),) +DEFAULT_CP := cp -f +endif + +ifeq ($(DEFAULT_MKDIR),) +DEFAULT_MKDIR := mkdir -p +endif + +# +# Set tool variables to defaults if not already defined. +# If these are defined, they would typically be defined by a +# setting in the generated portion of this makefile. +# +ifeq ($(CROSS_COMPILE),) +CROSS_COMPILE := $(DEFAULT_CROSS_COMPILE) +endif + +ifeq ($(origin CC),default) +CC := $(CROSS_COMPILE)gcc -xc +endif + +ifeq ($(origin CXX),default) +CXX := $(CROSS_COMPILE)gcc -xc++ +endif + +ifeq ($(origin AS),default) +AS := $(CROSS_COMPILE)gcc +endif + +ifeq ($(origin AR),default) +AR := $(CROSS_COMPILE)ar +endif + +ifeq ($(origin LD),default) +LD := $(CROSS_COMPILE)g++ +endif + +ifeq ($(origin NM),default) +NM := $(CROSS_COMPILE)nm +endif + +ifeq ($(origin RM),default) +RM := $(DEFAULT_RM) +endif + +ifeq ($(origin CP),default) +CP := $(DEFAULT_CP) +endif + +ifeq ($(OBJDUMP),) +OBJDUMP := $(CROSS_COMPILE)objdump +endif + +ifeq ($(OBJCOPY),) +OBJCOPY := $(CROSS_COMPILE)objcopy +endif + +ifeq ($(STACKREPORT),) +ifeq ($(CROSS_COMPILE),nios2-elf-) +STACKREPORT := $(DEFAULT_STACKREPORT) +else +DISABLE_STACKREPORT := 1 +endif +endif + +ifeq ($(DOWNLOAD),) +DOWNLOAD := $(DEFAULT_DOWNLOAD) +endif + +ifeq ($(FLASHPROG),) +FLASHPROG := $(DEFAULT_FLASHPROG) +endif + +ifeq ($(ELFPATCH),) +ELFPATCH := $(DEFAULT_ELFPATCH) +endif + +ifeq ($(MKDIR),) +MKDIR := $(DEFAULT_MKDIR) +endif + +#------------------------------------------------------------------------------ +# PATTERN RULES TO BUILD OBJECTS +#------------------------------------------------------------------------------ + +define compile.c +@$(ECHO) Info: Compiling $< to $@ +@$(MKDIR) $(@D) +$(CC) -MP -MMD -c $(APP_CPPFLAGS) $(APP_CFLAGS) -o $@ $< +$(CC_POST_PROCESS) +endef + +define compile.cpp +@$(ECHO) Info: Compiling $< to $@ +@$(MKDIR) $(@D) +$(CXX) -MP -MMD -c $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $< +$(CXX_POST_PROCESS) +endef + +# If assembling with the compiler, ensure "-Wa," is prepended to all APP_ASFLAGS +ifeq ($(AS),$(patsubst %as,%,$(AS))) +COMMA := , +APP_ASFLAGS := $(filter-out $(APP_CFLAGS),$(addprefix -Wa$(COMMA),$(patsubst -Wa$(COMMA)%,%,$(APP_ASFLAGS)))) +endif + +define compile.s +@$(ECHO) Info: Assembling $< to $@ +@$(MKDIR) $(@D) +$(AS) -MP -MMD -c $(APP_CPPFLAGS) $(APP_CFLAGS) $(APP_ASFLAGS) -o $@ $< +$(AS_POST_PROCESS) +endef + +ifeq ($(MAKE_VERSION),3.81) +.SECONDEXPANSION: + +$(APP_OBJS_C): $(CONFIG_OBJ_DIR)/%.o: $$(call adjust-path-mixed,%.c) + $(compile.c) + +$(APP_OBJS_CPP): $(CONFIG_OBJ_DIR)/%.o: $$(call adjust-path-mixed,%.cpp) + $(compile.cpp) + +$(APP_OBJS_CC): $(CONFIG_OBJ_DIR)/%.o: $$(call adjust-path-mixed,%.cc) + $(compile.cpp) + +$(APP_OBJS_CXX): $(CONFIG_OBJ_DIR)/%.o: $$(call adjust-path-mixed,%.cxx) + $(compile.cpp) + +$(APP_OBJS_S): $(CONFIG_OBJ_DIR)/%.o: $$(call adjust-path-mixed,%.S) + $(compile.s) + +$(APP_OBJS_SS): $(CONFIG_OBJ_DIR)/%.o: $$(call adjust-path-mixed,%.s) + $(compile.s) + +endif # MAKE_VERSION != 3.81 + +$(CONFIG_OBJ_DIR)/%.o: %.c + $(compile.c) + +$(CONFIG_OBJ_DIR)/%.o: %.cpp + $(compile.cpp) + +$(CONFIG_OBJ_DIR)/%.o: %.cc + $(compile.cpp) + +$(CONFIG_OBJ_DIR)/%.o: %.cxx + $(compile.cpp) + +$(CONFIG_OBJ_DIR)/%.o: %.S + $(compile.s) + +$(CONFIG_OBJ_DIR)/%.o: %.s + $(compile.s) + + +#------------------------------------------------------------------------------ +# PATTERN RULES TO INTERMEDIATE FILES +#------------------------------------------------------------------------------ + +$(CONFIG_OBJ_DIR)/%.s: %.c + @$(ECHO) Info: Compiling $< to $@ + @$(MKDIR) $(@D) + $(CC) -S $(APP_CPPFLAGS) $(APP_CFLAGS) -o $@ $< + +$(CONFIG_OBJ_DIR)/%.s: %.cpp + @$(ECHO) Info: Compiling $< to $@ + @$(MKDIR) $(@D) + $(CXX) -S $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $< + +$(CONFIG_OBJ_DIR)/%.s: %.cc + @$(ECHO) Info: Compiling $< to $@ + @$(MKDIR) $(@D) + $(CXX) -S $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $< + +$(CONFIG_OBJ_DIR)/%.s: %.cxx + @$(ECHO) Info: Compiling $< to $@ + @$(MKDIR) $(@D) + $(CXX) -S $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $< + +$(CONFIG_OBJ_DIR)/%.i: %.c + @$(ECHO) Info: Compiling $< to $@ + @$(MKDIR) $(@D) + $(CC) -E $(APP_CPPFLAGS) $(APP_CFLAGS) -o $@ $< + +$(CONFIG_OBJ_DIR)/%.i: %.cpp + @$(ECHO) Info: Compiling $< to $@ + @$(MKDIR) $(@D) + $(CXX) -E $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $< + +$(CONFIG_OBJ_DIR)/%.i: %.cc + @$(ECHO) Info: Compiling $< to $@ + @$(MKDIR) $(@D) + $(CXX) -E $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $< + +$(CONFIG_OBJ_DIR)/%.i: %.cxx + @$(ECHO) Info: Compiling $< to $@ + @$(MKDIR) $(@D) + $(CXX) -E $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $< + + +#------------------------------------------------------------------------------ +# TARGET RULES +#------------------------------------------------------------------------------ + +.PHONY : help +help : + @$(ECHO) "Summary of Makefile targets" + @$(ECHO) " Build targets:" + @$(ECHO) " all (default) - Application and all libraries (including BSP)" + @$(ECHO) " bsp - Just the BSP" + @$(ECHO) " libs - All libraries (including BSP)" + @$(ECHO) " flash - All flash files" + @$(ECHO) " mem_init_generate - All memory initialization files" +ifeq ($(QSYS),1) + @$(ECHO) " mem_init_install - This target is deprecated for QSys Systems" + @$(ECHO) " --> Use the mem_init_generate target and then" + @$(ECHO) " add the generated meminit.qip file to your" + @$(ECHO) " Quartus II Project." +else # if QSYS != 1 + @$(ECHO) " mem_init_install - Copy memory initialization files to Quartus II project" +endif # QSYS == 1 + @$(ECHO) + @$(ECHO) " Clean targets:" + @$(ECHO) " clean_all - Application and all libraries (including BSP)" + @$(ECHO) " clean - Just the application" + @$(ECHO) " clean_bsp - Just the BSP" + @$(ECHO) " clean_libs - All libraries (including BSP)" + @$(ECHO) + @$(ECHO) " Run targets:" + @$(ECHO) " download-elf - Download and run your elf executable" + @$(ECHO) " program-flash - Program flash contents to the board" + +# Handy rule to skip making libraries and just make application. +.PHONY : app +app : $(ELF) + +ifeq ($(CREATE_OBJDUMP), 1) +app : $(OBJDUMP_NAME) +endif + +ifeq ($(CREATE_ELF_DERIVED_FILES),1) +app : elf_derived_files +endif + +.PHONY: elf_derived_files +elf_derived_files: default_mem_init + +# Handy rule for making just the BSP. +.PHONY : bsp +bsp : + @$(ECHO) Info: Building $(BSP_ROOT_DIR) + @$(MAKE) --no-print-directory -C $(BSP_ROOT_DIR) + + +# Make sure all makeable libraries (including the BSP) are up-to-date. +LIB_TARGETS := $(patsubst %,%-recurs-make-lib,$(MAKEABLE_LIBRARY_ROOT_DIRS)) + +.PHONY : libs +libs : $(LIB_TARGETS) + +ifneq ($(strip $(LIB_TARGETS)),) +$(LIB_TARGETS): %-recurs-make-lib: + @$(ECHO) Info: Building $* + $(MAKE) --no-print-directory -C $* +endif + +ifneq ($(strip $(APP_LDDEPS)),) +$(APP_LDDEPS): libs + @true +endif + +# Rules to force your project to rebuild or relink +# .force_relink file will cause any application that depends on this project to relink +# .force_rebuild file will cause this project to rebuild object files +# .force_rebuild_all file will cause this project and any project that depends on this project to rebuild object files + +FORCE_RELINK_DEP := .force_relink +FORCE_REBUILD_DEP := .force_rebuild +FORCE_REBUILD_ALL_DEP := .force_rebuild_all +FORCE_REBUILD_DEP_LIST := $(CONFIG_OBJ_DIR)/$(FORCE_RELINK_DEP) $(CONFIG_OBJ_DIR)/$(FORCE_REBUILD_DEP) $(FORCE_REBUILD_ALL_DEP) + +$(FORCE_REBUILD_DEP_LIST): + +$(APP_OBJS): $(wildcard $(CONFIG_OBJ_DIR)/$(FORCE_REBUILD_DEP)) $(wildcard $(addsuffix /$(FORCE_REBUILD_ALL_DEP), . $(ALT_LIBRARY_DIRS))) + +$(ELF): $(wildcard $(addsuffix /$(FORCE_RELINK_DEP), $(CONFIG_OBJ_DIR) $(ALT_LIBRARY_DIRS))) + + +# Clean just the application. +.PHONY : clean +ifeq ($(CREATE_ELF_DERIVED_FILES),1) +clean : clean_elf_derived_files +endif + +clean : + @$(RM) -r $(ELF) $(OBJDUMP_NAME) $(LINKER_MAP_NAME) $(OBJ_ROOT_DIR) $(RUNTIME_ROOT_DIR) $(FORCE_REBUILD_DEP_LIST) + @$(ECHO) [$(APP_NAME) clean complete] + +# Clean just the BSP. +.PHONY : clean_bsp +clean_bsp : + @$(ECHO) Info: Cleaning $(BSP_ROOT_DIR) + @$(MAKE) --no-print-directory -C $(BSP_ROOT_DIR) clean + +# Clean all makeable libraries including the BSP. +LIB_CLEAN_TARGETS := $(patsubst %,%-recurs-make-clean-lib,$(MAKEABLE_LIBRARY_ROOT_DIRS)) + +.PHONY : clean_libs +clean_libs : $(LIB_CLEAN_TARGETS) + +ifneq ($(strip $(LIB_CLEAN_TARGETS)),) +$(LIB_CLEAN_TARGETS): %-recurs-make-clean-lib: + @$(ECHO) Info: Cleaning $* + $(MAKE) --no-print-directory -C $* clean +endif + +.PHONY: clean_elf_derived_files +clean_elf_derived_files: mem_init_clean + +# Clean application and all makeable libraries including the BSP. +.PHONY : clean_all +clean_all : clean mem_init_clean clean_libs + +# Include the dependency files unless the make goal is performing a clean +# of the application. +ifneq ($(firstword $(MAKECMDGOALS)),clean) +ifneq ($(firstword $(MAKECMDGOALS)),clean_all) +-include $(APP_DEPS) +endif +endif + +.PHONY : download-elf +download-elf : $(ELF) + @if [ "$(DOWNLOAD)" = "none" ]; \ + then \ + $(ECHO) Downloading $(ELF) not supported; \ + else \ + $(ECHO) Info: Downloading $(ELF); \ + $(DOWNLOAD) --go --cpu_name=$(CPU_NAME) $(DOWNLOAD_CABLE_FLAG) $(SOPC_SYSID_FLAG) $(DOWNLOAD_JDI_FLAG) $(WRITE_GMON_OPTION) $(ELF); \ + fi + +# Delete the target of a rule if it has changed and its commands exit +# with a nonzero exit status. +.DELETE_ON_ERROR: + +# Rules for flash programming commands +PROGRAM_FLASH_SUFFIX := -program +PROGRAM_FLASH_TARGET := $(addsuffix $(PROGRAM_FLASH_SUFFIX), $(FLASH_FILES)) + +.PHONY : program-flash +program-flash : $(PROGRAM_FLASH_TARGET) + +.PHONY : $(PROGRAM_FLASH_TARGET) +$(PROGRAM_FLASH_TARGET) : flash + @if [ "$(FLASHPROG)" = "none" ]; \ + then \ + $(ECHO) Programming flash not supported; \ + else \ + $(ECHO) Info: Programming $(basename $@).flash; \ + if [ -z "$($(basename $@)_EPCS_FLAGS)" ]; \ + then \ + $(ECHO) $(FLASHPROG) $(SOPC_SYSID_FLAG) --base=$($(basename $@)_START) $(basename $@).flash; \ + $(FLASHPROG) $(DOWNLOAD_CABLE_FLAG) $(SOPC_SYSID_FLAG) --base=$($(basename $@)_START) $(basename $@).flash; \ + else \ + $(ECHO) $(FLASHPROG) $(SOPC_SYSID_FLAG) --epcs --base=$($(basename $@)_START) $(basename $@).flash; \ + $(FLASHPROG) $(DOWNLOAD_CABLE_FLAG) $(SOPC_SYSID_FLAG) --epcs --base=$($(basename $@)_START) $(basename $@).flash; \ + fi \ + fi + + +# Rules for simulating with an HDL Simulator [QSYS only] +ifeq ($(QSYS),1) +IP_MAKE_SIMSCRIPT := ip-make-simscript + +ifeq ($(VSIM),) +VSIM_EXE := $(if $(VSIM_DIR),$(VSIM_DIR)/,)vsim +ifeq ($(ENABLE_VSIM_GUI),1) +VSIM := $(VSIM_EXE) -gui +else +VSIM := $(VSIM_EXE) -c +endif # ENABLE_VSIM_GUI == 1 +endif # VSIM not set + +ifeq ($(SPD),) +ifneq ($(ABS_QUARTUS_PROJECT_DIR),) +ifneq ($(SOPC_NAME),) +SPD := $(ABS_QUARTUS_PROJECT_DIR)/$(SOPC_NAME)_tb.spd +endif # SOPC_NAME set +endif # ABS_QUARTUS_PROJECT_DIR set +endif # SPD == empty string + +ifeq ($(MSIM_SCRIPT),) +SIM_SCRIPT_DIR := $(RUNTIME_ROOT_DIR)/sim +MSIM_SCRIPT := $(SIM_SCRIPT_DIR)/mentor/msim_setup.tcl +endif # MSIM_SCRIPT == empty string + +ifeq ($(MAKE_VERSION),3.81) +ABS_MEM_INIT_DESCRIPTOR_FILE := $(abspath $(MEM_INIT_DESCRIPTOR_FILE)) +else +ABS_MEM_INIT_DESCRIPTOR_FILE := $(call adjust-path-mixed,$(shell pwd))/$(MEM_INIT_DESCRIPTOR_FILE) +endif + +$(MSIM_SCRIPT): $(SPD) $(MEM_INIT_DESCRIPTOR_FILE) +ifeq ($(SPD),) + $(error No SPD file specified. Ensure QUARTUS_PROJECT_DIR variable is set) +endif + @$(MKDIR) $(SIM_SCRIPT_DIR) + $(IP_MAKE_SIMSCRIPT) --spd=$(SPD) --spd=$(MEM_INIT_DESCRIPTOR_FILE) --output-directory=$(SIM_SCRIPT_DIR) + +VSIM_COMMAND = \ + cd $(dir $(MSIM_SCRIPT)) && \ + $(VSIM) -do "do $(notdir $(MSIM_SCRIPT)); ld; $(if $(VSIM_RUN_TIME),run ${VSIM_RUN_TIME};quit;)" + +.PHONY: sim +sim: $(MSIM_SCRIPT) mem_init_generate +ifeq ($(MSIM_SCRIPT),) + $(error MSIM_SCRIPT not set) +endif + $(VSIM_COMMAND) + +endif # QSYS == 1 + + +#------------------------------------------------------------------------------ +# ELF TARGET RULE +#------------------------------------------------------------------------------ +# Rule for constructing the executable elf file. +$(ELF) : $(APP_OBJS) $(LINKER_SCRIPT) $(APP_LDDEPS) + @$(ECHO) Info: Linking $@ + $(LD) $(APP_LDFLAGS) $(APP_CFLAGS) -o $@ $(filter-out $(CRT0),$(APP_OBJS)) $(APP_LIBS) $(APP_BSP_DEP_LIBS) +ifneq ($(DISABLE_ELFPATCH),1) + $(ELFPATCH) $@ $(ELF_PATCH_FLAG) +endif +ifneq ($(DISABLE_STACKREPORT),1) + @bash -c "$(STACKREPORT) $@" +endif + +$(OBJDUMP_NAME) : $(ELF) + @$(ECHO) Info: Creating $@ + $(OBJDUMP) $(OBJDUMP_FLAGS) $< >$@ + +# Rule for printing the name of the elf file +.PHONY: print-elf-name +print-elf-name: + @$(ECHO) $(ELF) + + diff --git a/MCandWifiTestDE0/Software/Archive/MCTest/MotorHandler.cpp b/MCandWifiTestDE0/Software/Archive/MCTest/MotorHandler.cpp new file mode 100644 index 00000000..01bb7944 --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest/MotorHandler.cpp @@ -0,0 +1,86 @@ +/* + * MotorHandler.cpp + * + * Created on: 2014-03-03 + * Author: gongal + */ + +#include "MotorHandler.h" +#include "includes.h" +#include "altera_avalon_uart_regs.h" + +MotorHandler::MotorHandler() { + // TODO Auto-generated constructor stub + +} + +MotorHandler::~MotorHandler() { + // TODO Auto-generated destructor stub +} +void MotorHandler::sendByteMC(char msg){ + IOWR_ALTERA_AVALON_UART_TXDATA(UART_MC_BASE, msg); +} +/* + * Move rover forward by activating both motors + */ +void MotorHandler::mc_forward(){ + //motor 1 + sendByteMC(MOTOR_START_BYTE); + sendByteMC(MOTOR_DEVICE_TYPE); + sendByteMC(MOTOR_MOTOR2_FORWARD); + sendByteMC(MOTOR_CONST_SPEED); + //motor 2 + sendByteMC(MOTOR_START_BYTE); + sendByteMC(MOTOR_DEVICE_TYPE); + sendByteMC(MOTOR_MOTOR3_FORWARD); + sendByteMC(MOTOR_CONST_SPEED); +} +/* + * Move rover backward by activating both motor backwards + */ +void MotorHandler::mc_backward(){ + //motor 1 + sendByteMC(MOTOR_START_BYTE); + sendByteMC(MOTOR_DEVICE_TYPE); + sendByteMC(MOTOR_MOTOR2_BACKWARD); + sendByteMC(MOTOR_CONST_SPEED); + //motor 2 + sendByteMC(MOTOR_START_BYTE); + sendByteMC(MOTOR_DEVICE_TYPE); + sendByteMC(MOTOR_MOTOR3_BACKWARD); + sendByteMC(MOTOR_CONST_SPEED); +} +/* + * Turn rover left + */ +void MotorHandler::mc_left(){ + //Turn Left by driving the left motor only + + //motor 1 + sendByteMC(MOTOR_START_BYTE); + sendByteMC(MOTOR_DEVICE_TYPE); + sendByteMC(MOTOR_MOTOR2_FORWARD); + sendByteMC(MOTOR_CONST_SPEED); +} + +void MotorHandler::mc_right(){ + //Turn Right by driving right motor only + + //motor 1 + sendByteMC(MOTOR_START_BYTE); + sendByteMC(MOTOR_DEVICE_TYPE); + sendByteMC(MOTOR_MOTOR3_FORWARD); + sendByteMC(MOTOR_CONST_SPEED); +} +void MotorHandler::mc_stop(){ + //motor1 + sendByteMC(MOTOR_START_BYTE); + sendByteMC(MOTOR_DEVICE_TYPE); + sendByteMC(MOTOR_MOTOR2_FORWARD); + sendByteMC(MOTOR_STOP_SPEED); + //motor 2 + sendByteMC(MOTOR_START_BYTE); + sendByteMC(MOTOR_DEVICE_TYPE); + sendByteMC(MOTOR_MOTOR3_FORWARD); + sendByteMC(MOTOR_STOP_SPEED); +} diff --git a/MCandWifiTestDE0/Software/Archive/MCTest/MotorHandler.h b/MCandWifiTestDE0/Software/Archive/MCTest/MotorHandler.h new file mode 100644 index 00000000..873e3b97 --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest/MotorHandler.h @@ -0,0 +1,32 @@ +/* + * MotorHandler.h + * + * Created on: 2014-03-03 + * Author: gongal + */ + +#ifndef MOTORHANDLER_H_ +#define MOTORHANDLER_H_ +#define MOTOR_START_BYTE 0x80 + +#define MOTOR_DEVICE_TYPE 0x00 +#define MOTOR_MOTOR2_BACKWARD 0x04 // motor 2 backward +#define MOTOR_MOTOR3_BACKWARD 0x06 //motor 3 backward +#define MOTOR_MOTOR2_FORWARD 0x05 // motor 2 forward +#define MOTOR_MOTOR3_FORWARD 0x07 // motor 3 forward +#define MOTOR_CONST_SPEED 0x5F +#define MOTOR_STOP_SPEED 0x00 + +class MotorHandler { +public: + MotorHandler(); + virtual ~MotorHandler(); + void sendByteMC(char msg); + void mc_forward(); + void mc_backward(); + void mc_right(); + void mc_left(); + void mc_stop(); +}; + +#endif /* MOTORHANDLER_H_ */ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest/create-this-app b/MCandWifiTestDE0/Software/Archive/MCTest/create-this-app new file mode 100644 index 00000000..9dd2653f --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest/create-this-app @@ -0,0 +1,114 @@ +#!/bin/bash +# +# This script creates the hello_ucosii application in this directory. + + +BSP_DIR=../MCTest_bsp +QUARTUS_PROJECT_DIR=../../ +NIOS2_APP_GEN_ARGS="--elf-name MCTest.elf --set OBJDUMP_INCLUDE_SOURCE 1 --src-files hello_ucosii.c" + + +# First, check to see if $SOPC_KIT_NIOS2 environmental variable is set. +# This variable is required for the command line tools to execute correctly. +if [ -z "${SOPC_KIT_NIOS2}" ] +then + echo Required \$SOPC_KIT_NIOS2 Environmental Variable is not set! + exit 1 +fi + + +# Also make sure that the APP has not been created already. Check for +# existence of Makefile in the app directory +if [ -f ./Makefile ] +then + echo Application has already been created! Delete Makefile if you want to create a new application makefile + exit 1 +fi + + +# We are selecting ucosii_default bsp because it supports this application. +# Check to see if the ucosii_default has already been generated by checking for +# existence of the public.mk file. If not, we need to run +# create-this-bsp file to generate the bsp. +if [ ! -f ${BSP_DIR}/public.mk ]; then + # Since BSP doesn't exist, create the BSP + # Pass any command line arguments passed to this script to the BSP. + pushd ${BSP_DIR} >> /dev/null + ./create-this-bsp "$@" || { + echo "create-this-bsp failed" + exit 1 + } + popd >> /dev/null +fi + + +# Don't run make if create-this-app script is called with --no-make arg +SKIP_MAKE= +while [ $# -gt 0 ] +do + case "$1" in + --no-make) + SKIP_MAKE=1 + ;; + esac + shift +done + + +# Now we also need to go copy the sources for this application to the +# local directory. +find "${SOPC_KIT_NIOS2}/examples/software/hello_ucosii/" -name '*.c' -or -name '*.h' -or -name 'hostfs*' | xargs -i cp -L {} ./ || { + echo "failed during copying example source files" + exit 1 +} + +find "${SOPC_KIT_NIOS2}/examples/software/hello_ucosii/" -name 'readme.txt' -or -name 'Readme.txt' | xargs -i cp -L {} ./ || { + echo "failed copying readme file" +} + +if [ -d "${SOPC_KIT_NIOS2}/examples/software/hello_ucosii/system" ] +then + cp -RL "${SOPC_KIT_NIOS2}/examples/software/hello_ucosii/system" . || { + echo "failed during copying project support files" + exit 1 + } +fi + +chmod -R +w . || { + echo "failed during changing file permissions" + exit 1 +} + +cmd="nios2-app-generate-makefile --bsp-dir ${BSP_DIR} --set QUARTUS_PROJECT_DIR=${QUARTUS_PROJECT_DIR} ${NIOS2_APP_GEN_ARGS}" + +echo "create-this-app: Running \"${cmd}\"" +$cmd || { + echo "nios2-app-generate-makefile failed" + exit 1 +} + +if [ -z "$SKIP_MAKE" ]; then + cmd="make" + + echo "create-this-app: Running \"$cmd\"" + $cmd || { + echo "make failed" + exit 1 + } + + echo + echo "To download and run the application:" + echo " 1. Make sure the board is connected to the system." + echo " 2. Run 'nios2-configure-sof ' to configure the FPGA with the hardware design." + echo " 3. If you have a stdio device, run 'nios2-terminal' in a different shell." + echo " 4. Run 'make download-elf' from the application directory." + echo + echo "To debug the application:" + echo " Import the project into Nios II Software Build Tools for Eclipse." + echo " Refer to Nios II Software Build Tools for Eclipse Documentation for more information." + echo + echo -e "" +fi + + +exit 0 diff --git a/MCandWifiTestDE0/Software/Archive/MCTest/main.cpp b/MCandWifiTestDE0/Software/Archive/MCTest/main.cpp new file mode 100644 index 00000000..69caa508 --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest/main.cpp @@ -0,0 +1,214 @@ +/************************************************************************* + * ARCap + * Amshu Gongal, Kenan Kigunda + * February 18, 2014 + ************************************************************************** + * Description: * + * Prototype testing for infrared and wifi. + **************************************************************************/ + +#include +#include "includes.h" +#include "altera_avalon_pio_regs.h" +#include "altera_avalon_uart_regs.h" +#include "sys/alt_irq.h" +#include "alt_types.h" +#include "MotorHandler.h" + +MotorHandler * motorHandler = new MotorHandler(); +/* Task stacks */ +#define TASK_STACKSIZE 2048 +OS_STK ir_task_stk[TASK_STACKSIZE]; +OS_STK wifi_task_stk[TASK_STACKSIZE]; +OS_STK mc_task_stk[TASK_STACKSIZE]; +/* Task priorities */ +#define IR_TASK_PRIORITY 1 +#define WIFI_TASK_PRIORITY 2 +#define MC_TASK_PRIORITY 2 + + +/* Error status */ +#define OK 0 + +/* Message queues */ +#define WAIT_FOREVER 0 + +// ==== INFRARED ==== + +/* Infrared message queue */ +#define IR_MAX_MESSAGES 4 +int ir_messages[IR_MAX_MESSAGES]; +OS_EVENT *ir_queue; + +/* Infrared messages */ +// Together these avoid passing 0 to the queue (which is not allowed since queue messages cannot be null) +// and invert pushbutton input (since the pushbutton returns 0 when it is pushed down). +#define IR_QUEUE_SEND_BASE 1 // Use: IR_QUEUE_SEND_BASE + IORD +#define IR_QUEUE_RECEIVE_BASE 2 // Use: IR_QUEUE_RECEIVE_BASE - OSQPend + + +/* Interrupt service routine triggered whenever the status of the IR emitter pushbutton changes. */ +static void isr_on_ir_pushbutton(void * context) { + // Read the state of the pushbutton and post it to the queue. + //printf("Pressed\n"); + int message = IR_QUEUE_SEND_BASE + IORD_ALTERA_AVALON_PIO_DATA(PIO_KEY_LEFT_BASE); + OSQPost(ir_queue, (void*)message); + // Mask to mark the end of the ISR. + IOWR_ALTERA_AVALON_PIO_EDGE_CAP(PIO_KEY_LEFT_BASE, PIO_KEY_LEFT_BIT_CLEARING_EDGE_REGISTER); +} + +/* Controllers the IR emitter based on the value of the pushbutton. */ +void ir_task(void* pdata) +{ + INT8U err; + while (1) + { + // Read the value from the queue. + int status = IR_QUEUE_RECEIVE_BASE - (int)OSQPend(ir_queue, WAIT_FOREVER, &err); + if (err == OS_NO_ERR) { + // Print the result and send it to the emitter. + printf("IR: %d\n", status); + IOWR_ALTERA_AVALON_PIO_DATA(PIO_IR_EMITTER_BASE, status); + } + } +} + +// ==== WIFI + +#define WIFI_GUARD_TIME 1 + +void wifi_wait() { + OSTimeDlyHMSM(0, 0, WIFI_GUARD_TIME, 0); +} + +void wifi_write(char *message, int length) { + int i; + for (i = 0; i < length; i++) { + IOWR_ALTERA_AVALON_UART_TXDATA(UART_WIFI_BASE, message[i]); + } +} + +void wifi_read() { + int status = IORD_ALTERA_AVALON_UART_STATUS(UART_WIFI_BASE); + printf("Wifi status: %d\n", status); + char c = IORD_ALTERA_AVALON_UART_RXDATA(UART_WIFI_BASE); + printf("Wifi: %c\n", c); +} + +void wifi_task(void *pdata) +{ + printf("Started wifi task\n"); + wifi_wait(); + wifi_write("+++", 3); + wifi_wait(); + wifi_read(); +} + + + +// ==== MC + + +//====MotorContoller +void mc_task(void *pdata) +{ + motorHandler->mc_forward(); + OSTimeDlyHMSM(0, 0, 4, 0); + motorHandler->mc_stop(); +} + +// ==== GENERAL + +void queue_init() { + ir_queue = OSQCreate((void**)&ir_messages, IR_MAX_MESSAGES); +} + +/* The main function creates the LCD task, registers the edge counter polling interrupt, + * and starts the OS. */ +int main(void) +{ + int status; + // Initialize components. + queue_init(); + + // Create the IR task. + OSTaskCreateExt(ir_task, + NULL, + &ir_task_stk[TASK_STACKSIZE - 1], + IR_TASK_PRIORITY, + IR_TASK_PRIORITY, + ir_task_stk, + TASK_STACKSIZE, + NULL, + 0); + + // Create the Wifi task. + OSTaskCreateExt(wifi_task, + NULL, + &wifi_task_stk[TASK_STACKSIZE - 1], + WIFI_TASK_PRIORITY, + WIFI_TASK_PRIORITY, + wifi_task_stk, + TASK_STACKSIZE, + NULL, + 0); + + // Create the MC task. + OSTaskCreateExt(mc_task, + NULL, + &mc_task_stk[TASK_STACKSIZE - 1], + MC_TASK_PRIORITY, + MC_TASK_PRIORITY, + mc_task_stk, + TASK_STACKSIZE, + NULL, + 0); + + // Register the IR pushbutton interrupt. + /*status = alt_ic_isr_register(PIO_KEY_LEFT_IRQ_INTERRUPT_CONTROLLER_ID, + PIO_KEY_LEFT_IRQ, + isr_on_ir_pushbutton, + NULL, + NULL);*/ + + // Enable key interrupts. + IOWR_ALTERA_AVALON_PIO_IRQ_MASK(PIO_KEY_LEFT_BASE, PIO_KEY_LEFT_CAPTURE); + + // Start. + if (status == OK) { + OSStart(); + } + + return 0; +} + +/****************************************************************************** + * * + * License Agreement * + * * + * Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * + * All rights reserved. * + * * + * Permission is hereby granted, free of charge, to any person obtaining a * + * copy of this software and associated documentation files (the "Software"), * + * to deal in the Software without restriction, including without limitation * + * the rights to use, copy, modify, merge, publish, distribute, sublicense, * + * and/or sell copies of the Software, and to permit persons to whom the * + * Software is furnished to do so, subject to the following conditions: * + * * + * The above copyright notice and this permission notice shall be included in * + * all copies or substantial portions of the Software. * + * * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * + * DEALINGS IN THE SOFTWARE. * + * * + * This agreement shall be governed in all respects by the laws of the State * + * of California and by the laws of the United States of America. * + * Altera does not recommend, suggest or require that this reference design * + * file be used in conjunction or combination with any other product. * + ******************************************************************************/ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest/obj/default/.force_relink b/MCandWifiTestDE0/Software/Archive/MCTest/obj/default/.force_relink new file mode 100644 index 00000000..e69de29b diff --git a/MCandWifiTestDE0/Software/Archive/MCTest/obj/default/MotorHandler.d b/MCandWifiTestDE0/Software/Archive/MCTest/obj/default/MotorHandler.d new file mode 100644 index 00000000..127e673c --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest/obj/default/MotorHandler.d @@ -0,0 +1,63 @@ +obj/default/MotorHandler.o: MotorHandler.cpp MotorHandler.h \ + ../MCTest_bsp//HAL/inc/includes.h ../MCTest_bsp//HAL/inc/os_cpu.h \ + ../MCTest_bsp//HAL/inc/sys/alt_irq.h ../MCTest_bsp//HAL/inc/nios2.h \ + ../MCTest_bsp//HAL/inc/alt_types.h ../MCTest_bsp/system.h \ + ../MCTest_bsp/linker.h ../MCTest_bsp//HAL/inc/priv/alt_legacy_irq.h \ + ../MCTest_bsp/system.h ../MCTest_bsp//HAL/inc/nios2.h \ + ../MCTest_bsp//HAL/inc/alt_types.h ../MCTest_bsp//HAL/inc/sys/alt_irq.h \ + ../MCTest_bsp//UCOSII/inc/os_cfg.h \ + ../MCTest_bsp//HAL/inc/sys/alt_alarm.h \ + ../MCTest_bsp//HAL/inc/sys/alt_llist.h \ + ../MCTest_bsp//HAL/inc/priv/alt_alarm.h ../MCTest_bsp/system.h \ + ../MCTest_bsp//UCOSII/inc/ucos_ii.h ../MCTest_bsp//UCOSII/inc/os_cfg.h \ + ../MCTest_bsp//HAL/inc/os_cpu.h \ + ../MCTest_bsp//drivers/inc/altera_avalon_uart_regs.h \ + ../MCTest_bsp//HAL/inc/io.h ../MCTest_bsp//HAL/inc/alt_types.h + +MotorHandler.h: + +../MCTest_bsp//HAL/inc/includes.h: + +../MCTest_bsp//HAL/inc/os_cpu.h: + +../MCTest_bsp//HAL/inc/sys/alt_irq.h: + +../MCTest_bsp//HAL/inc/nios2.h: + +../MCTest_bsp//HAL/inc/alt_types.h: + +../MCTest_bsp/system.h: + +../MCTest_bsp/linker.h: + +../MCTest_bsp//HAL/inc/priv/alt_legacy_irq.h: + +../MCTest_bsp/system.h: + +../MCTest_bsp//HAL/inc/nios2.h: + +../MCTest_bsp//HAL/inc/alt_types.h: + +../MCTest_bsp//HAL/inc/sys/alt_irq.h: + +../MCTest_bsp//UCOSII/inc/os_cfg.h: + +../MCTest_bsp//HAL/inc/sys/alt_alarm.h: + +../MCTest_bsp//HAL/inc/sys/alt_llist.h: + +../MCTest_bsp//HAL/inc/priv/alt_alarm.h: + +../MCTest_bsp/system.h: + +../MCTest_bsp//UCOSII/inc/ucos_ii.h: + +../MCTest_bsp//UCOSII/inc/os_cfg.h: + +../MCTest_bsp//HAL/inc/os_cpu.h: + +../MCTest_bsp//drivers/inc/altera_avalon_uart_regs.h: + +../MCTest_bsp//HAL/inc/io.h: + +../MCTest_bsp//HAL/inc/alt_types.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest/obj/default/MotorHandler.o b/MCandWifiTestDE0/Software/Archive/MCTest/obj/default/MotorHandler.o new file mode 100644 index 00000000..13df8bf0 Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest/obj/default/MotorHandler.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest/obj/default/SerialHandler.d b/MCandWifiTestDE0/Software/Archive/MCTest/obj/default/SerialHandler.d new file mode 100644 index 00000000..bcfc036d --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest/obj/default/SerialHandler.d @@ -0,0 +1,63 @@ +obj/default/SerialHandler.o: SerialHandler.cpp SerialHandler.h \ + ../MCTest_bsp//HAL/inc/includes.h ../MCTest_bsp//HAL/inc/os_cpu.h \ + ../MCTest_bsp//HAL/inc/sys/alt_irq.h ../MCTest_bsp//HAL/inc/nios2.h \ + ../MCTest_bsp//HAL/inc/alt_types.h ../MCTest_bsp/system.h \ + ../MCTest_bsp/linker.h ../MCTest_bsp//HAL/inc/priv/alt_legacy_irq.h \ + ../MCTest_bsp/system.h ../MCTest_bsp//HAL/inc/nios2.h \ + ../MCTest_bsp//HAL/inc/alt_types.h ../MCTest_bsp//HAL/inc/sys/alt_irq.h \ + ../MCTest_bsp//UCOSII/inc/os_cfg.h \ + ../MCTest_bsp//HAL/inc/sys/alt_alarm.h \ + ../MCTest_bsp//HAL/inc/sys/alt_llist.h \ + ../MCTest_bsp//HAL/inc/priv/alt_alarm.h ../MCTest_bsp/system.h \ + ../MCTest_bsp//UCOSII/inc/ucos_ii.h ../MCTest_bsp//UCOSII/inc/os_cfg.h \ + ../MCTest_bsp//HAL/inc/os_cpu.h \ + ../MCTest_bsp//drivers/inc/altera_avalon_uart_regs.h \ + ../MCTest_bsp//HAL/inc/io.h ../MCTest_bsp//HAL/inc/alt_types.h + +SerialHandler.h: + +../MCTest_bsp//HAL/inc/includes.h: + +../MCTest_bsp//HAL/inc/os_cpu.h: + +../MCTest_bsp//HAL/inc/sys/alt_irq.h: + +../MCTest_bsp//HAL/inc/nios2.h: + +../MCTest_bsp//HAL/inc/alt_types.h: + +../MCTest_bsp/system.h: + +../MCTest_bsp/linker.h: + +../MCTest_bsp//HAL/inc/priv/alt_legacy_irq.h: + +../MCTest_bsp/system.h: + +../MCTest_bsp//HAL/inc/nios2.h: + +../MCTest_bsp//HAL/inc/alt_types.h: + +../MCTest_bsp//HAL/inc/sys/alt_irq.h: + +../MCTest_bsp//UCOSII/inc/os_cfg.h: + +../MCTest_bsp//HAL/inc/sys/alt_alarm.h: + +../MCTest_bsp//HAL/inc/sys/alt_llist.h: + +../MCTest_bsp//HAL/inc/priv/alt_alarm.h: + +../MCTest_bsp/system.h: + +../MCTest_bsp//UCOSII/inc/ucos_ii.h: + +../MCTest_bsp//UCOSII/inc/os_cfg.h: + +../MCTest_bsp//HAL/inc/os_cpu.h: + +../MCTest_bsp//drivers/inc/altera_avalon_uart_regs.h: + +../MCTest_bsp//HAL/inc/io.h: + +../MCTest_bsp//HAL/inc/alt_types.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest/obj/default/SerialHandler.o b/MCandWifiTestDE0/Software/Archive/MCTest/obj/default/SerialHandler.o new file mode 100644 index 00000000..4878bb19 Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest/obj/default/SerialHandler.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest/obj/default/main.d b/MCandWifiTestDE0/Software/Archive/MCTest/obj/default/main.d new file mode 100644 index 00000000..c2d7a3a3 --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest/obj/default/main.d @@ -0,0 +1,71 @@ +obj/default/main.o: main.cpp ../MCTest_bsp//HAL/inc/includes.h \ + ../MCTest_bsp//HAL/inc/os_cpu.h ../MCTest_bsp//HAL/inc/sys/alt_irq.h \ + ../MCTest_bsp//HAL/inc/nios2.h ../MCTest_bsp//HAL/inc/alt_types.h \ + ../MCTest_bsp/system.h ../MCTest_bsp/linker.h \ + ../MCTest_bsp//HAL/inc/priv/alt_legacy_irq.h ../MCTest_bsp/system.h \ + ../MCTest_bsp//HAL/inc/nios2.h ../MCTest_bsp//HAL/inc/alt_types.h \ + ../MCTest_bsp//HAL/inc/sys/alt_irq.h ../MCTest_bsp//UCOSII/inc/os_cfg.h \ + ../MCTest_bsp//HAL/inc/sys/alt_alarm.h \ + ../MCTest_bsp//HAL/inc/sys/alt_llist.h \ + ../MCTest_bsp//HAL/inc/priv/alt_alarm.h ../MCTest_bsp/system.h \ + ../MCTest_bsp//UCOSII/inc/ucos_ii.h ../MCTest_bsp//UCOSII/inc/os_cfg.h \ + ../MCTest_bsp//HAL/inc/os_cpu.h \ + ../MCTest_bsp//drivers/inc/altera_avalon_pio_regs.h \ + ../MCTest_bsp//HAL/inc/io.h ../MCTest_bsp//HAL/inc/alt_types.h \ + ../MCTest_bsp//drivers/inc/altera_avalon_uart_regs.h \ + ../MCTest_bsp//HAL/inc/sys/alt_irq.h ../MCTest_bsp//HAL/inc/alt_types.h \ + MotorHandler.h + +../MCTest_bsp//HAL/inc/includes.h: + +../MCTest_bsp//HAL/inc/os_cpu.h: + +../MCTest_bsp//HAL/inc/sys/alt_irq.h: + +../MCTest_bsp//HAL/inc/nios2.h: + +../MCTest_bsp//HAL/inc/alt_types.h: + +../MCTest_bsp/system.h: + +../MCTest_bsp/linker.h: + +../MCTest_bsp//HAL/inc/priv/alt_legacy_irq.h: + +../MCTest_bsp/system.h: + +../MCTest_bsp//HAL/inc/nios2.h: + +../MCTest_bsp//HAL/inc/alt_types.h: + +../MCTest_bsp//HAL/inc/sys/alt_irq.h: + +../MCTest_bsp//UCOSII/inc/os_cfg.h: + +../MCTest_bsp//HAL/inc/sys/alt_alarm.h: + +../MCTest_bsp//HAL/inc/sys/alt_llist.h: + +../MCTest_bsp//HAL/inc/priv/alt_alarm.h: + +../MCTest_bsp/system.h: + +../MCTest_bsp//UCOSII/inc/ucos_ii.h: + +../MCTest_bsp//UCOSII/inc/os_cfg.h: + +../MCTest_bsp//HAL/inc/os_cpu.h: + +../MCTest_bsp//drivers/inc/altera_avalon_pio_regs.h: + +../MCTest_bsp//HAL/inc/io.h: + +../MCTest_bsp//HAL/inc/alt_types.h: + +../MCTest_bsp//drivers/inc/altera_avalon_uart_regs.h: + +../MCTest_bsp//HAL/inc/sys/alt_irq.h: + +../MCTest_bsp//HAL/inc/alt_types.h: + +MotorHandler.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest/obj/default/main.o b/MCandWifiTestDE0/Software/Archive/MCTest/obj/default/main.o new file mode 100644 index 00000000..f7dec039 Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest/obj/default/main.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest/readme.txt b/MCandWifiTestDE0/Software/Archive/MCTest/readme.txt new file mode 100644 index 00000000..49e8390f --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest/readme.txt @@ -0,0 +1,7 @@ +Readme - Hello MicroC/OS-II Hello Software Example + +Hello_uosii is a simple hello world program running MicroC/OS-II. The +purpose of the design is to be a very simple application that just +demonstrates MicroC/OS-II running on NIOS II. The design doesn't account +for issues such as checking system call return codes. etc. + diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/.cproject b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/.cproject new file mode 100644 index 00000000..5141e477 --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/.cproject @@ -0,0 +1,481 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/.project b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/.project new file mode 100644 index 00000000..bebef029 --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/.project @@ -0,0 +1,85 @@ + + + MCTest_bsp + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + + + + org.eclipse.cdt.make.core.buildCommand + make + + + org.eclipse.cdt.make.core.buildLocation + ${workspace_loc://MCTest_bsp} + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + org.eclipse.cdt.core.ccnature + com.altera.sbtgui.project.SBTGUINature + com.altera.sbtgui.project.SBTGUIBspNature + + diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/HAL/inc/alt_types.h b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/HAL/inc/alt_types.h similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/HAL/inc/alt_types.h rename to MCandWifiTestDE0/Software/Archive/MCTest_bsp/HAL/inc/alt_types.h diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/HAL/inc/altera_nios2_qsys_irq.h b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/HAL/inc/altera_nios2_qsys_irq.h similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/HAL/inc/altera_nios2_qsys_irq.h rename to MCandWifiTestDE0/Software/Archive/MCTest_bsp/HAL/inc/altera_nios2_qsys_irq.h diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/HAL/inc/includes.h b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/HAL/inc/includes.h similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/HAL/inc/includes.h rename to MCandWifiTestDE0/Software/Archive/MCTest_bsp/HAL/inc/includes.h diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/HAL/inc/io.h b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/HAL/inc/io.h similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/HAL/inc/io.h rename to MCandWifiTestDE0/Software/Archive/MCTest_bsp/HAL/inc/io.h diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/HAL/inc/nios2.h b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/HAL/inc/nios2.h similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/HAL/inc/nios2.h rename to MCandWifiTestDE0/Software/Archive/MCTest_bsp/HAL/inc/nios2.h diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/HAL/inc/os/alt_syscall.h b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/HAL/inc/os/alt_syscall.h similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/HAL/inc/os/alt_syscall.h rename to MCandWifiTestDE0/Software/Archive/MCTest_bsp/HAL/inc/os/alt_syscall.h diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/HAL/inc/os_cpu.h b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/HAL/inc/os_cpu.h similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/HAL/inc/os_cpu.h rename to MCandWifiTestDE0/Software/Archive/MCTest_bsp/HAL/inc/os_cpu.h diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/HAL/inc/priv/alt_alarm.h b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/HAL/inc/priv/alt_alarm.h similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/HAL/inc/priv/alt_alarm.h rename to MCandWifiTestDE0/Software/Archive/MCTest_bsp/HAL/inc/priv/alt_alarm.h diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/HAL/inc/priv/alt_busy_sleep.h b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/HAL/inc/priv/alt_busy_sleep.h similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/HAL/inc/priv/alt_busy_sleep.h rename to MCandWifiTestDE0/Software/Archive/MCTest_bsp/HAL/inc/priv/alt_busy_sleep.h diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/HAL/inc/priv/alt_dev_llist.h b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/HAL/inc/priv/alt_dev_llist.h similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/HAL/inc/priv/alt_dev_llist.h rename to MCandWifiTestDE0/Software/Archive/MCTest_bsp/HAL/inc/priv/alt_dev_llist.h diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/HAL/inc/priv/alt_exception_handler_registry.h b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/HAL/inc/priv/alt_exception_handler_registry.h similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/HAL/inc/priv/alt_exception_handler_registry.h rename to MCandWifiTestDE0/Software/Archive/MCTest_bsp/HAL/inc/priv/alt_exception_handler_registry.h diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/HAL/inc/priv/alt_file.h b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/HAL/inc/priv/alt_file.h similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/HAL/inc/priv/alt_file.h rename to MCandWifiTestDE0/Software/Archive/MCTest_bsp/HAL/inc/priv/alt_file.h diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/HAL/inc/priv/alt_iic_isr_register.h b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/HAL/inc/priv/alt_iic_isr_register.h similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/HAL/inc/priv/alt_iic_isr_register.h rename to MCandWifiTestDE0/Software/Archive/MCTest_bsp/HAL/inc/priv/alt_iic_isr_register.h diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/HAL/inc/priv/alt_irq_table.h b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/HAL/inc/priv/alt_irq_table.h similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/HAL/inc/priv/alt_irq_table.h rename to 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similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/HAL/inc/sys/alt_debug.h rename to MCandWifiTestDE0/Software/Archive/MCTest_bsp/HAL/inc/sys/alt_debug.h diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/HAL/inc/sys/alt_dev.h b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/HAL/inc/sys/alt_dev.h similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/HAL/inc/sys/alt_dev.h rename to MCandWifiTestDE0/Software/Archive/MCTest_bsp/HAL/inc/sys/alt_dev.h diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/HAL/inc/sys/alt_dma.h b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/HAL/inc/sys/alt_dma.h similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/HAL/inc/sys/alt_dma.h rename to MCandWifiTestDE0/Software/Archive/MCTest_bsp/HAL/inc/sys/alt_dma.h diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/HAL/inc/sys/alt_dma_dev.h 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a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/HAL/inc/sys/alt_exceptions.h b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/HAL/inc/sys/alt_exceptions.h similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/HAL/inc/sys/alt_exceptions.h rename to MCandWifiTestDE0/Software/Archive/MCTest_bsp/HAL/inc/sys/alt_exceptions.h diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/HAL/inc/sys/alt_flash.h b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/HAL/inc/sys/alt_flash.h similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/HAL/inc/sys/alt_flash.h rename to MCandWifiTestDE0/Software/Archive/MCTest_bsp/HAL/inc/sys/alt_flash.h diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/HAL/inc/sys/alt_flash_dev.h b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/HAL/inc/sys/alt_flash_dev.h similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/HAL/inc/sys/alt_flash_dev.h rename to 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b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/HAL/inc/sys/alt_load.h similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/HAL/inc/sys/alt_load.h rename to MCandWifiTestDE0/Software/Archive/MCTest_bsp/HAL/inc/sys/alt_load.h diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/HAL/inc/sys/alt_log_printf.h b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/HAL/inc/sys/alt_log_printf.h similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/HAL/inc/sys/alt_log_printf.h rename to MCandWifiTestDE0/Software/Archive/MCTest_bsp/HAL/inc/sys/alt_log_printf.h diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/HAL/inc/sys/alt_set_args.h b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/HAL/inc/sys/alt_set_args.h similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/HAL/inc/sys/alt_set_args.h rename to MCandWifiTestDE0/Software/Archive/MCTest_bsp/HAL/inc/sys/alt_set_args.h diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/HAL/inc/sys/alt_sim.h b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/HAL/inc/sys/alt_sim.h similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/HAL/inc/sys/alt_sim.h rename to MCandWifiTestDE0/Software/Archive/MCTest_bsp/HAL/inc/sys/alt_sim.h diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/HAL/inc/sys/alt_stack.h b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/HAL/inc/sys/alt_stack.h similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/HAL/inc/sys/alt_stack.h rename to MCandWifiTestDE0/Software/Archive/MCTest_bsp/HAL/inc/sys/alt_stack.h diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/HAL/inc/sys/alt_stdio.h b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/HAL/inc/sys/alt_stdio.h similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/HAL/inc/sys/alt_stdio.h rename to MCandWifiTestDE0/Software/Archive/MCTest_bsp/HAL/inc/sys/alt_stdio.h diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/HAL/inc/sys/alt_sys_init.h b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/HAL/inc/sys/alt_sys_init.h similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/HAL/inc/sys/alt_sys_init.h rename to MCandWifiTestDE0/Software/Archive/MCTest_bsp/HAL/inc/sys/alt_sys_init.h diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/HAL/inc/sys/alt_sys_wrappers.h b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/HAL/inc/sys/alt_sys_wrappers.h similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/HAL/inc/sys/alt_sys_wrappers.h rename to MCandWifiTestDE0/Software/Archive/MCTest_bsp/HAL/inc/sys/alt_sys_wrappers.h diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/HAL/inc/sys/alt_timestamp.h b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/HAL/inc/sys/alt_timestamp.h similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/HAL/inc/sys/alt_timestamp.h rename to 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rename to MCandWifiTestDE0/Software/Archive/MCTest_bsp/HAL/inc/sys/termios.h diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/HAL/src/alt_alarm_start.c b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/HAL/src/alt_alarm_start.c similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/HAL/src/alt_alarm_start.c rename to MCandWifiTestDE0/Software/Archive/MCTest_bsp/HAL/src/alt_alarm_start.c diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/HAL/src/alt_busy_sleep.c b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/HAL/src/alt_busy_sleep.c similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/HAL/src/alt_busy_sleep.c rename to MCandWifiTestDE0/Software/Archive/MCTest_bsp/HAL/src/alt_busy_sleep.c diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/HAL/src/alt_close.c b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/HAL/src/alt_close.c similarity index 100% rename from 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b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/HAL/src/alt_stat.c similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/HAL/src/alt_stat.c rename to MCandWifiTestDE0/Software/Archive/MCTest_bsp/HAL/src/alt_stat.c diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/HAL/src/alt_tick.c b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/HAL/src/alt_tick.c similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/HAL/src/alt_tick.c rename to MCandWifiTestDE0/Software/Archive/MCTest_bsp/HAL/src/alt_tick.c diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/HAL/src/alt_times.c b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/HAL/src/alt_times.c similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/HAL/src/alt_times.c rename to MCandWifiTestDE0/Software/Archive/MCTest_bsp/HAL/src/alt_times.c diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/HAL/src/alt_uncached_free.c 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a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/HAL/src/alt_usleep.c b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/HAL/src/alt_usleep.c similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/HAL/src/alt_usleep.c rename to MCandWifiTestDE0/Software/Archive/MCTest_bsp/HAL/src/alt_usleep.c diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/HAL/src/alt_wait.c b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/HAL/src/alt_wait.c similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/HAL/src/alt_wait.c rename to MCandWifiTestDE0/Software/Archive/MCTest_bsp/HAL/src/alt_wait.c diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/HAL/src/alt_write.c b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/HAL/src/alt_write.c similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/HAL/src/alt_write.c rename to MCandWifiTestDE0/Software/Archive/MCTest_bsp/HAL/src/alt_write.c diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/HAL/src/altera_nios2_qsys_irq.c b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/HAL/src/altera_nios2_qsys_irq.c similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/HAL/src/altera_nios2_qsys_irq.c rename to MCandWifiTestDE0/Software/Archive/MCTest_bsp/HAL/src/altera_nios2_qsys_irq.c diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/HAL/src/crt0.S b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/HAL/src/crt0.S similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/HAL/src/crt0.S rename to MCandWifiTestDE0/Software/Archive/MCTest_bsp/HAL/src/crt0.S diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/HAL/src/os_cpu_a.S b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/HAL/src/os_cpu_a.S similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/HAL/src/os_cpu_a.S rename to MCandWifiTestDE0/Software/Archive/MCTest_bsp/HAL/src/os_cpu_a.S diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/HAL/src/os_cpu_c.c b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/HAL/src/os_cpu_c.c similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/HAL/src/os_cpu_c.c rename to MCandWifiTestDE0/Software/Archive/MCTest_bsp/HAL/src/os_cpu_c.c diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/Makefile b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/Makefile similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/Makefile rename to MCandWifiTestDE0/Software/Archive/MCTest_bsp/Makefile diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/UCOSII/inc/os/alt_flag.h b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/UCOSII/inc/os/alt_flag.h similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/UCOSII/inc/os/alt_flag.h rename to MCandWifiTestDE0/Software/Archive/MCTest_bsp/UCOSII/inc/os/alt_flag.h diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/UCOSII/inc/os/alt_hooks.h b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/UCOSII/inc/os/alt_hooks.h similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/UCOSII/inc/os/alt_hooks.h rename to MCandWifiTestDE0/Software/Archive/MCTest_bsp/UCOSII/inc/os/alt_hooks.h diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/UCOSII/inc/os/alt_sem.h b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/UCOSII/inc/os/alt_sem.h similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/UCOSII/inc/os/alt_sem.h rename to MCandWifiTestDE0/Software/Archive/MCTest_bsp/UCOSII/inc/os/alt_sem.h diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/UCOSII/inc/os_cfg.h b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/UCOSII/inc/os_cfg.h similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/UCOSII/inc/os_cfg.h rename to MCandWifiTestDE0/Software/Archive/MCTest_bsp/UCOSII/inc/os_cfg.h diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/UCOSII/inc/priv/alt_flag_ucosii.h b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/UCOSII/inc/priv/alt_flag_ucosii.h similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/UCOSII/inc/priv/alt_flag_ucosii.h rename to MCandWifiTestDE0/Software/Archive/MCTest_bsp/UCOSII/inc/priv/alt_flag_ucosii.h diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/UCOSII/inc/priv/alt_sem_ucosii.h b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/UCOSII/inc/priv/alt_sem_ucosii.h similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/UCOSII/inc/priv/alt_sem_ucosii.h rename to MCandWifiTestDE0/Software/Archive/MCTest_bsp/UCOSII/inc/priv/alt_sem_ucosii.h diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/UCOSII/inc/ucos_ii.h b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/UCOSII/inc/ucos_ii.h similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/UCOSII/inc/ucos_ii.h rename to MCandWifiTestDE0/Software/Archive/MCTest_bsp/UCOSII/inc/ucos_ii.h diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/UCOSII/src/alt_env_lock.c b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/UCOSII/src/alt_env_lock.c similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/UCOSII/src/alt_env_lock.c rename to MCandWifiTestDE0/Software/Archive/MCTest_bsp/UCOSII/src/alt_env_lock.c diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/UCOSII/src/alt_malloc_lock.c b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/UCOSII/src/alt_malloc_lock.c similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/UCOSII/src/alt_malloc_lock.c rename to MCandWifiTestDE0/Software/Archive/MCTest_bsp/UCOSII/src/alt_malloc_lock.c diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/UCOSII/src/os_core.c b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/UCOSII/src/os_core.c similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/UCOSII/src/os_core.c rename to MCandWifiTestDE0/Software/Archive/MCTest_bsp/UCOSII/src/os_core.c diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/UCOSII/src/os_dbg.c b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/UCOSII/src/os_dbg.c similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/UCOSII/src/os_dbg.c rename to MCandWifiTestDE0/Software/Archive/MCTest_bsp/UCOSII/src/os_dbg.c diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/UCOSII/src/os_flag.c b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/UCOSII/src/os_flag.c similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/UCOSII/src/os_flag.c rename to MCandWifiTestDE0/Software/Archive/MCTest_bsp/UCOSII/src/os_flag.c diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/UCOSII/src/os_mbox.c b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/UCOSII/src/os_mbox.c similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/UCOSII/src/os_mbox.c rename to MCandWifiTestDE0/Software/Archive/MCTest_bsp/UCOSII/src/os_mbox.c diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/UCOSII/src/os_mem.c b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/UCOSII/src/os_mem.c similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/UCOSII/src/os_mem.c rename to MCandWifiTestDE0/Software/Archive/MCTest_bsp/UCOSII/src/os_mem.c diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/UCOSII/src/os_mutex.c b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/UCOSII/src/os_mutex.c similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/UCOSII/src/os_mutex.c rename to MCandWifiTestDE0/Software/Archive/MCTest_bsp/UCOSII/src/os_mutex.c diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/UCOSII/src/os_q.c b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/UCOSII/src/os_q.c similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/UCOSII/src/os_q.c rename to MCandWifiTestDE0/Software/Archive/MCTest_bsp/UCOSII/src/os_q.c diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/UCOSII/src/os_sem.c b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/UCOSII/src/os_sem.c similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/UCOSII/src/os_sem.c rename to MCandWifiTestDE0/Software/Archive/MCTest_bsp/UCOSII/src/os_sem.c diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/UCOSII/src/os_task.c b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/UCOSII/src/os_task.c similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/UCOSII/src/os_task.c rename to MCandWifiTestDE0/Software/Archive/MCTest_bsp/UCOSII/src/os_task.c diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/UCOSII/src/os_time.c b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/UCOSII/src/os_time.c similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/UCOSII/src/os_time.c rename to MCandWifiTestDE0/Software/Archive/MCTest_bsp/UCOSII/src/os_time.c diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/UCOSII/src/os_tmr.c b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/UCOSII/src/os_tmr.c similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/UCOSII/src/os_tmr.c rename to MCandWifiTestDE0/Software/Archive/MCTest_bsp/UCOSII/src/os_tmr.c diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/alt_sys_init.c b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/alt_sys_init.c new file mode 100644 index 00000000..758161af --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/alt_sys_init.c @@ -0,0 +1,107 @@ +/* + * alt_sys_init.c - HAL initialization source + * + * Machine generated for CPU 'cpu' in SOPC Builder design 'system' + * SOPC Builder design path: C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system.sopcinfo + * + * Generated: Mon Mar 03 15:52:38 MST 2014 + */ + +/* + * DO NOT MODIFY THIS FILE + * + * Changing this file will have subtle consequences + * which will almost certainly lead to a nonfunctioning + * system. If you do modify this file, be aware that your + * changes will be overwritten and lost when this file + * is generated again. + * + * DO NOT MODIFY THIS FILE + */ + +/* + * License Agreement + * + * Copyright (c) 2008 + * Altera Corporation, San Jose, California, USA. + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * This agreement shall be governed in all respects by the laws of the State + * of California and by the laws of the United States of America. + */ + +#include "system.h" +#include "sys/alt_irq.h" +#include "sys/alt_sys_init.h" + +#include + +/* + * Device headers + */ + +#include "altera_nios2_qsys_irq.h" +#include "altera_avalon_jtag_uart.h" +#include "altera_avalon_sysid_qsys.h" +#include "altera_avalon_timer.h" +#include "altera_avalon_uart.h" +#include "altera_up_avalon_rs232.h" + +/* + * Allocate the device storage + */ + +ALTERA_NIOS2_QSYS_IRQ_INSTANCE ( CPU, cpu); +ALTERA_AVALON_JTAG_UART_INSTANCE ( JTAG_UART_0, jtag_uart_0); +ALTERA_AVALON_SYSID_QSYS_INSTANCE ( SYSID, sysid); +ALTERA_AVALON_TIMER_INSTANCE ( SYS_CLK_TIMER, sys_clk_timer); +ALTERA_AVALON_UART_INSTANCE ( UART_MC, uart_mc); +ALTERA_AVALON_UART_INSTANCE ( UART_WIFI, uart_wifi); +ALTERA_UP_AVALON_RS232_INSTANCE ( RS232_WIFI, rs232_wifi); + +/* + * Initialize the interrupt controller devices + * and then enable interrupts in the CPU. + * Called before alt_sys_init(). + * The "base" parameter is ignored and only + * present for backwards-compatibility. + */ + +void alt_irq_init ( const void* base ) +{ + ALTERA_NIOS2_QSYS_IRQ_INIT ( CPU, cpu); + alt_irq_cpu_enable_interrupts(); +} + +/* + * Initialize the non-interrupt controller devices. + * Called after alt_irq_init(). + */ + +void alt_sys_init( void ) +{ + ALTERA_AVALON_TIMER_INIT ( SYS_CLK_TIMER, sys_clk_timer); + ALTERA_AVALON_JTAG_UART_INIT ( JTAG_UART_0, jtag_uart_0); + ALTERA_AVALON_SYSID_QSYS_INIT ( SYSID, sysid); + ALTERA_AVALON_UART_INIT ( UART_MC, uart_mc); + ALTERA_AVALON_UART_INIT ( UART_WIFI, uart_wifi); + ALTERA_UP_AVALON_RS232_INIT ( RS232_WIFI, rs232_wifi); +} diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/create-this-bsp b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/create-this-bsp similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/create-this-bsp rename to MCandWifiTestDE0/Software/Archive/MCTest_bsp/create-this-bsp diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/drivers/inc/altera_avalon_jtag_uart.h b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/drivers/inc/altera_avalon_jtag_uart.h similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/drivers/inc/altera_avalon_jtag_uart.h rename to MCandWifiTestDE0/Software/Archive/MCTest_bsp/drivers/inc/altera_avalon_jtag_uart.h diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/drivers/inc/altera_avalon_jtag_uart_fd.h b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/drivers/inc/altera_avalon_jtag_uart_fd.h similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/drivers/inc/altera_avalon_jtag_uart_fd.h rename to MCandWifiTestDE0/Software/Archive/MCTest_bsp/drivers/inc/altera_avalon_jtag_uart_fd.h diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/drivers/inc/altera_avalon_jtag_uart_regs.h b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/drivers/inc/altera_avalon_jtag_uart_regs.h similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/drivers/inc/altera_avalon_jtag_uart_regs.h rename to MCandWifiTestDE0/Software/Archive/MCTest_bsp/drivers/inc/altera_avalon_jtag_uart_regs.h diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/drivers/inc/altera_avalon_pio_regs.h b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/drivers/inc/altera_avalon_pio_regs.h similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/drivers/inc/altera_avalon_pio_regs.h rename to MCandWifiTestDE0/Software/Archive/MCTest_bsp/drivers/inc/altera_avalon_pio_regs.h diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/drivers/inc/altera_avalon_sysid_qsys.h b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/drivers/inc/altera_avalon_sysid_qsys.h similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/drivers/inc/altera_avalon_sysid_qsys.h rename to MCandWifiTestDE0/Software/Archive/MCTest_bsp/drivers/inc/altera_avalon_sysid_qsys.h diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/drivers/inc/altera_avalon_sysid_qsys_regs.h b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/drivers/inc/altera_avalon_sysid_qsys_regs.h similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/drivers/inc/altera_avalon_sysid_qsys_regs.h rename to MCandWifiTestDE0/Software/Archive/MCTest_bsp/drivers/inc/altera_avalon_sysid_qsys_regs.h diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/drivers/inc/altera_avalon_timer.h b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/drivers/inc/altera_avalon_timer.h similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/drivers/inc/altera_avalon_timer.h rename to MCandWifiTestDE0/Software/Archive/MCTest_bsp/drivers/inc/altera_avalon_timer.h diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/drivers/inc/altera_avalon_timer_regs.h b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/drivers/inc/altera_avalon_timer_regs.h similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/drivers/inc/altera_avalon_timer_regs.h rename to MCandWifiTestDE0/Software/Archive/MCTest_bsp/drivers/inc/altera_avalon_timer_regs.h diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/drivers/inc/altera_avalon_uart.h b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/drivers/inc/altera_avalon_uart.h similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/drivers/inc/altera_avalon_uart.h rename to MCandWifiTestDE0/Software/Archive/MCTest_bsp/drivers/inc/altera_avalon_uart.h diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/drivers/inc/altera_avalon_uart_fd.h b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/drivers/inc/altera_avalon_uart_fd.h similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/drivers/inc/altera_avalon_uart_fd.h rename to MCandWifiTestDE0/Software/Archive/MCTest_bsp/drivers/inc/altera_avalon_uart_fd.h diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/drivers/inc/altera_avalon_uart_regs.h b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/drivers/inc/altera_avalon_uart_regs.h similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/drivers/inc/altera_avalon_uart_regs.h rename to MCandWifiTestDE0/Software/Archive/MCTest_bsp/drivers/inc/altera_avalon_uart_regs.h diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/drivers/inc/altera_up_avalon_rs232.h b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/drivers/inc/altera_up_avalon_rs232.h new file mode 100644 index 00000000..53b1ec3e --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/drivers/inc/altera_up_avalon_rs232.h @@ -0,0 +1,182 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2007 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +* * +******************************************************************************/ + +#ifndef __ALTERA_UP_AVALON_RS232_H__ +#define __ALTERA_UP_AVALON_RS232_H__ + +#include +#include +#include + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Device structure definition. Each instance of the driver uses one + * of these structures to hold its associated state. + */ +typedef struct alt_up_rs232_dev { + /// @brief character mode device structure + /// @sa Developing Device Drivers for the HAL in Nios II Software Developer's Handbook + alt_dev dev; + /// @brief the base address of the device + unsigned int base; +} alt_up_rs232_dev; + + +////////////////////////////////////////////////////////////////////////// +// HAL system functions + +/** + * @brief Enable the read interrupts for the RS232 UART core. + * + * @param rs232 -- the RS232 device structure + **/ +void alt_up_rs232_enable_read_interrupt(alt_up_rs232_dev *rs232); + +/** + * @brief Disable the read interrupts for the RS232 UART core. + * + * @param rs232 -- the RS232 device structure + * + **/ +void alt_up_rs232_disable_read_interrupt(alt_up_rs232_dev *rs232); + +/** + * @brief Check whether the DATA field has a parity error. + * + * @param data_reg -- the date register + * + * @return 0 for no errors, \f$-1\f$ for parity error. + **/ +int alt_up_rs232_check_parity(alt_u32 data_reg); + +/** + * @brief Gets the number of data words remaining in the read FIFO. + * + * @param rs232 -- the RS232 device structure + * + * @return The number of data words remaining. + **/ +unsigned alt_up_rs232_get_used_space_in_read_FIFO(alt_up_rs232_dev *rs232); + +/** + * @brief Gets the amount of available space remaining in the write FIFO. + * + * @param rs232 -- the RS232 device structure + * + * @return The amount of available space remaining. + **/ +unsigned alt_up_rs232_get_available_space_in_write_FIFO(alt_up_rs232_dev *rs232); + +/** + * @brief Write data to the RS232 UART core. + * + * @param rs232 -- the RS232 device structure + * @param data -- the character to be transferred to the RS232 UART Core. + * + * @note User should ensure the write FIFO is not full before writing, otherwise the character is lost. + * + * @return 0 for success or \f$-1\f$ on error. + **/ +int alt_up_rs232_write_data(alt_up_rs232_dev *rs232, alt_u8 data); + +/** + * @brief Read data from the RS232 UART core. + * + * @param rs232 -- the RS232 device structure + * @param data -- pointer to the memory where the character read from the RS232 UART core should be stored. + * @param parity_error -- pointer to the memory where the parity error should be stored. + * + * @return 0 for success or \f$-1\f$ on error. + * + * @note This function will clear the DATA field of the data register after reading and it + * uses the \c alt_up_rs232_check_parity function to check the parity for the + * DATA field. + **/ +int alt_up_rs232_read_data(alt_up_rs232_dev *rs232, alt_u8 *data, alt_u8 *parity_error); + +////////////////////////////////////////////////////////////////////////// +// file-like operation functions +int alt_up_rs232_read_fd (alt_fd* fd, char* ptr, int len); +int alt_up_rs232_write_fd (alt_fd* fd, const char* ptr, int len); + +////////////////////////////////////////////////////////////////////////// +// direct operation functions + +/** + * @brief Open the RS232 device according to device name + * + * @param name -- the device name in SOPC Builder + * + * @return the \c alt_up_rs232_dev device structure + **/ +alt_up_rs232_dev* alt_up_rs232_open_dev(const char* name); + +/* + * Macros used by alt_sys_init + */ +#define ALTERA_UP_AVALON_RS232_INSTANCE(name, device) \ + static alt_up_rs232_dev device = \ + { \ + { \ + ALT_LLIST_ENTRY, \ + name##_NAME, \ + NULL , /* open */ \ + NULL , /* close */ \ + alt_up_rs232_read_fd , /* read */ \ + alt_up_rs232_write_fd , /* write */ \ + NULL , /* lseek */ \ + NULL , /* fstat */ \ + NULL , /* ioctl */ \ + }, \ + name##_BASE, \ + } + +#define ALTERA_UP_AVALON_RS232_INIT(name, device) \ + { \ + /* make the device available to the system */ \ + alt_dev_reg(&device.dev); \ + } + + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALTERA_UP_AVALON_RS232_H__ */ + + diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/drivers/inc/altera_up_avalon_rs232_regs.h b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/drivers/inc/altera_up_avalon_rs232_regs.h new file mode 100644 index 00000000..00a1f236 --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/drivers/inc/altera_up_avalon_rs232_regs.h @@ -0,0 +1,96 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#ifndef __ALT_UP_RS232_REGS_H__ +#define __ALT_UP_RS232_REGS_H__ +#include +#include + +#define IOWR_ALT_UP_RS232_ADDR(base, addr, data) \ + IOWR(base, addr, data) +/* + * Data Register + */ +#define ALT_UP_RS232_DATA_REG 0 + +#define IOADDR_ALT_UP_RS232_DATA(base) \ + __IO_CALC_ADDRESS_NATIVE(base, ALT_UP_RS232_DATA_REG) +#define IORD_ALT_UP_RS232_DATA(base) \ + IORD(base, ALT_UP_RS232_DATA_REG) +#define IOWR_ALT_UP_RS232_DATA(base, data) \ + IOWR(base, ALT_UP_RS232_DATA_REG, data) + +#define ALT_UP_RS232_DATA_DATA_MSK (0x000001FF) +#define ALT_UP_RS232_DATA_DATA_OFST (0) +#define ALT_UP_RS232_DATA_PE_MSK (0x00000200) +#define ALT_UP_RS232_DATA_PE_OFST (9) +#define ALT_UP_RS232_DATA_RVALID_MSK (0x00008000) +#define ALT_UP_RS232_DATA_RVALID_OFST (15) +#define ALT_UP_RS232_DATA_RAVAIL_MSK (0xFFFF0000) +#define ALT_UP_RS232_DATA_RAVAIL_OFST (16) + +#define ALT_UP_RS232_DATA_REG_RAVAIL 2 +#define IORD_ALT_UP_RS232_RAVAIL(base) \ + IORD_16DIRECT(base, ALT_UP_RS232_DATA_REG_RAVAIL) +#define ALT_UP_RS232_RAVAIL_MSK (0x0000FFFF) +#define ALT_UP_RS232_RAVAIL_OFST (0) + +#define ALT_UP_RS232_DATA_VALID_MSK (ALT_UP_RS232_DATA_DATA_MSK \ + | ALT_UP_RS232_DATA_PE_MSK \ + | ALT_UP_RS232_DATA_RAVAIL_MSK) +/* + * Control Register + */ +#define ALT_UP_RS232_CONTROL_REG 1 + +#define IOADDR_ALT_UP_RS232_CONTROL(base) \ + __IO_CALC_ADDRESS_NATIVE(base, ALT_UP_RS232_CONTROL_REG) +#define IORD_ALT_UP_RS232_CONTROL(base) \ + IORD(base, ALT_UP_RS232_CONTROL_REG) +#define IOWR_ALT_UP_RS232_CONTROL(base, data) \ + IOWR(base, ALT_UP_RS232_CONTROL_REG, data) + +#define ALT_UP_RS232_CONTROL_RE_MSK (0x00000001) +#define ALT_UP_RS232_CONTROL_RE_OFST (0) +#define ALT_UP_RS232_CONTROL_WE_MSK (0x00000002) +#define ALT_UP_RS232_CONTROL_WE_OFST (1) +#define ALT_UP_RS232_CONTROL_RI_MSK (0x00000100) +#define ALT_UP_RS232_CONTROL_RI_OFST (8) +#define ALT_UP_RS232_CONTROL_WI_MSK (0x00000200) +#define ALT_UP_RS232_CONTROL_WI_OFST (9) +#define ALT_UP_RS232_CONTROL_WSPACE_MSK (0xFFFF0000) +#define ALT_UP_RS232_CONTROL_WSPACE_OFST (16) + +#define ALT_UP_RS232_CONTROL_VALID_MSK (ALT_UP_RS232_CONTROL_RE_MSK \ + | ALT_UP_RS232_CONTROL_WE_MSK \ + | ALT_UP_RS232_CONTROL_RI_MSK \ + | ALT_UP_RS232_CONTROL_WI_MSK \ + | ALT_UP_RS232_CONTROL_WSPACE_MSK) +#endif /*__ALT_UP_RS232_REGS_H__*/ diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/drivers/src/altera_avalon_jtag_uart_fd.c b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/drivers/src/altera_avalon_jtag_uart_fd.c similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/drivers/src/altera_avalon_jtag_uart_fd.c rename to MCandWifiTestDE0/Software/Archive/MCTest_bsp/drivers/src/altera_avalon_jtag_uart_fd.c diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/drivers/src/altera_avalon_jtag_uart_init.c b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/drivers/src/altera_avalon_jtag_uart_init.c similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/drivers/src/altera_avalon_jtag_uart_init.c rename to MCandWifiTestDE0/Software/Archive/MCTest_bsp/drivers/src/altera_avalon_jtag_uart_init.c diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/drivers/src/altera_avalon_jtag_uart_ioctl.c b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/drivers/src/altera_avalon_jtag_uart_ioctl.c similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/drivers/src/altera_avalon_jtag_uart_ioctl.c rename to MCandWifiTestDE0/Software/Archive/MCTest_bsp/drivers/src/altera_avalon_jtag_uart_ioctl.c diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/drivers/src/altera_avalon_jtag_uart_read.c b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/drivers/src/altera_avalon_jtag_uart_read.c similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/drivers/src/altera_avalon_jtag_uart_read.c rename to MCandWifiTestDE0/Software/Archive/MCTest_bsp/drivers/src/altera_avalon_jtag_uart_read.c diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/drivers/src/altera_avalon_jtag_uart_write.c b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/drivers/src/altera_avalon_jtag_uart_write.c similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/drivers/src/altera_avalon_jtag_uart_write.c rename to MCandWifiTestDE0/Software/Archive/MCTest_bsp/drivers/src/altera_avalon_jtag_uart_write.c diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/drivers/src/altera_avalon_sysid_qsys.c b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/drivers/src/altera_avalon_sysid_qsys.c similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/drivers/src/altera_avalon_sysid_qsys.c rename to MCandWifiTestDE0/Software/Archive/MCTest_bsp/drivers/src/altera_avalon_sysid_qsys.c diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/drivers/src/altera_avalon_timer_sc.c b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/drivers/src/altera_avalon_timer_sc.c similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/drivers/src/altera_avalon_timer_sc.c rename to MCandWifiTestDE0/Software/Archive/MCTest_bsp/drivers/src/altera_avalon_timer_sc.c diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/drivers/src/altera_avalon_timer_ts.c b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/drivers/src/altera_avalon_timer_ts.c similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/drivers/src/altera_avalon_timer_ts.c rename to MCandWifiTestDE0/Software/Archive/MCTest_bsp/drivers/src/altera_avalon_timer_ts.c diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/drivers/src/altera_avalon_timer_vars.c b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/drivers/src/altera_avalon_timer_vars.c similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/drivers/src/altera_avalon_timer_vars.c rename to MCandWifiTestDE0/Software/Archive/MCTest_bsp/drivers/src/altera_avalon_timer_vars.c diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/drivers/src/altera_avalon_uart_fd.c b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/drivers/src/altera_avalon_uart_fd.c similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/drivers/src/altera_avalon_uart_fd.c rename to MCandWifiTestDE0/Software/Archive/MCTest_bsp/drivers/src/altera_avalon_uart_fd.c diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/drivers/src/altera_avalon_uart_init.c b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/drivers/src/altera_avalon_uart_init.c similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/drivers/src/altera_avalon_uart_init.c rename to MCandWifiTestDE0/Software/Archive/MCTest_bsp/drivers/src/altera_avalon_uart_init.c diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/drivers/src/altera_avalon_uart_ioctl.c b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/drivers/src/altera_avalon_uart_ioctl.c similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/drivers/src/altera_avalon_uart_ioctl.c rename to MCandWifiTestDE0/Software/Archive/MCTest_bsp/drivers/src/altera_avalon_uart_ioctl.c diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/drivers/src/altera_avalon_uart_read.c b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/drivers/src/altera_avalon_uart_read.c similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/drivers/src/altera_avalon_uart_read.c rename to MCandWifiTestDE0/Software/Archive/MCTest_bsp/drivers/src/altera_avalon_uart_read.c diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/drivers/src/altera_avalon_uart_write.c b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/drivers/src/altera_avalon_uart_write.c similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/drivers/src/altera_avalon_uart_write.c rename to MCandWifiTestDE0/Software/Archive/MCTest_bsp/drivers/src/altera_avalon_uart_write.c diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/drivers/src/altera_up_avalon_rs232.c b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/drivers/src/altera_up_avalon_rs232.c new file mode 100644 index 00000000..3a22b7a9 --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/drivers/src/altera_up_avalon_rs232.c @@ -0,0 +1,145 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2007 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +* * +******************************************************************************/ + +#include + +#include + +#include "altera_up_avalon_rs232.h" +#include "altera_up_avalon_rs232_regs.h" + + +void alt_up_rs232_enable_read_interrupt(alt_up_rs232_dev *rs232) +{ + alt_u32 ctrl_reg; + ctrl_reg = IORD_ALT_UP_RS232_CONTROL(rs232->base); + // set RE to 1 while maintaining other bits the same + ctrl_reg |= ALT_UP_RS232_CONTROL_RE_MSK; + IOWR_ALT_UP_RS232_CONTROL(rs232->base, ctrl_reg); +} + +void alt_up_rs232_disable_read_interrupt(alt_up_rs232_dev *rs232) +{ + alt_u32 ctrl_reg; + ctrl_reg = IORD_ALT_UP_RS232_CONTROL(rs232->base); + // set RE to 0 while maintaining other bits the same + ctrl_reg &= ~ALT_UP_RS232_CONTROL_RE_MSK; + IOWR_ALT_UP_RS232_CONTROL(rs232->base, ctrl_reg); +} + +unsigned alt_up_rs232_get_used_space_in_read_FIFO(alt_up_rs232_dev *rs232) +{ + alt_u16 ravail = 0; + // we can only read the 16 bits for RAVAIL --- a read of DATA will discard the data +// ravail = IORD_16DIRECT(IOADDR_ALT_UP_RS232_DATA(rs232->base), 2); + ravail = IORD_ALT_UP_RS232_RAVAIL(rs232->base); +// return ravail; + return (ravail & ALT_UP_RS232_RAVAIL_MSK) >> ALT_UP_RS232_RAVAIL_OFST; +} + +unsigned alt_up_rs232_get_available_space_in_write_FIFO(alt_up_rs232_dev *rs232) +{ + alt_u32 ctrl_reg; + ctrl_reg = IORD_ALT_UP_RS232_CONTROL(rs232->base); + return (ctrl_reg & ALT_UP_RS232_CONTROL_WSPACE_MSK) >> ALT_UP_RS232_CONTROL_WSPACE_OFST; +} + +int alt_up_rs232_check_parity(alt_u32 data_reg) +{ + unsigned parity_error = (data_reg & ALT_UP_RS232_DATA_PE_MSK) >> ALT_UP_RS232_DATA_PE_OFST; + return (parity_error ? -1 : 0); +} + +int alt_up_rs232_write_data(alt_up_rs232_dev *rs232, alt_u8 data) +{ + alt_u32 data_reg; + data_reg = IORD_ALT_UP_RS232_DATA(rs232->base); + + // we can write directly without thinking about other bit fields for this + // case ONLY, because only DATA field of the data register is writable + IOWR_ALT_UP_RS232_DATA(rs232->base, (data>>ALT_UP_RS232_DATA_DATA_OFST) & ALT_UP_RS232_DATA_DATA_MSK); + return 0; +} + +int alt_up_rs232_read_data(alt_up_rs232_dev *rs232, alt_u8 *data, alt_u8 *parity_error) +{ + alt_u32 data_reg; + data_reg = IORD_ALT_UP_RS232_DATA(rs232->base); + *data = (data_reg & ALT_UP_RS232_DATA_DATA_MSK) >> ALT_UP_RS232_DATA_DATA_OFST; + *parity_error = alt_up_rs232_check_parity(data_reg); + return (((data_reg & ALT_UP_RS232_DATA_RVALID_MSK) >> ALT_UP_RS232_DATA_RVALID_OFST) - 1); +} + +int alt_up_rs232_read_fd (alt_fd* fd, char* ptr, int len) +{ + alt_up_rs232_dev *rs232 = (alt_up_rs232_dev*)fd->dev; + int count = 0; + alt_u8 parity_error; + while(len--) + { + if (alt_up_rs232_read_data(rs232, ptr++, &parity_error)==0) + count++; + else + break; + } + return count; +} + +int alt_up_rs232_write_fd (alt_fd* fd, const char* ptr, int len) +{ + alt_up_rs232_dev *rs232 = (alt_up_rs232_dev*)fd->dev; + int count = 0; + while(len--) + { + if (alt_up_rs232_write_data(rs232, *ptr)==0) + { + count++; + ptr++; + } + else + break; + } + return count; +} + +alt_up_rs232_dev* alt_up_rs232_open_dev(const char* name) +{ + // find the device from the device list + // (see altera_hal/HAL/inc/priv/alt_file.h + // and altera_hal/HAL/src/alt_find_dev.c + // for details) + alt_up_rs232_dev *dev = (alt_up_rs232_dev*)alt_find_dev(name, &alt_dev_list); + + return dev; +} + diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/libucosii_bsp.a b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/libucosii_bsp.a new file mode 100644 index 00000000..f17dee77 Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/libucosii_bsp.a differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/linker.h b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/linker.h new file mode 100644 index 00000000..1a4c67db --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/linker.h @@ -0,0 +1,101 @@ +/* + * linker.h - Linker script mapping information + * + * Machine generated for CPU 'cpu' in SOPC Builder design 'system' + * SOPC Builder design path: C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system.sopcinfo + * + * Generated: Mon Mar 03 15:52:38 MST 2014 + */ + +/* + * DO NOT MODIFY THIS FILE + * + * Changing this file will have subtle consequences + * which will almost certainly lead to a nonfunctioning + * system. If you do modify this file, be aware that your + * changes will be overwritten and lost when this file + * is generated again. + * + * DO NOT MODIFY THIS FILE + */ + +/* + * License Agreement + * + * Copyright (c) 2008 + * Altera Corporation, San Jose, California, USA. + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * This agreement shall be governed in all respects by the laws of the State + * of California and by the laws of the United States of America. + */ + +#ifndef __LINKER_H_ +#define __LINKER_H_ + + +/* + * BSP controls alt_load() behavior in crt0. + * + */ + +#define ALT_LOAD_EXPLICITLY_CONTROLLED + + +/* + * Base address and span (size in bytes) of each linker region + * + */ + +#define RESET_REGION_BASE 0x1000000 +#define RESET_REGION_SPAN 32 +#define SDRAM_REGION_BASE 0x1000020 +#define SDRAM_REGION_SPAN 16777184 + + +/* + * Devices associated with code sections + * + */ + +#define ALT_EXCEPTIONS_DEVICE SDRAM +#define ALT_RESET_DEVICE SDRAM +#define ALT_RODATA_DEVICE SDRAM +#define ALT_RWDATA_DEVICE SDRAM +#define ALT_TEXT_DEVICE SDRAM + + +/* + * Initialization code at the reset address is allowed (e.g. no external bootloader). + * + */ + +#define ALT_ALLOW_CODE_AT_RESET + + +/* + * The alt_load() facility is called from crt0 to copy sections into RAM. + * + */ + +#define ALT_LOAD_COPY_RWDATA + +#endif /* __LINKER_H_ */ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/linker.x b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/linker.x new file mode 100644 index 00000000..ac831e61 --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/linker.x @@ -0,0 +1,385 @@ +/* + * linker.x - Linker script + * + * Machine generated for CPU 'cpu' in SOPC Builder design 'system' + * SOPC Builder design path: C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system.sopcinfo + * + * Generated: Mon Mar 03 15:52:38 MST 2014 + */ + +/* + * DO NOT MODIFY THIS FILE + * + * Changing this file will have subtle consequences + * which will almost certainly lead to a nonfunctioning + * system. If you do modify this file, be aware that your + * changes will be overwritten and lost when this file + * is generated again. + * + * DO NOT MODIFY THIS FILE + */ + +/* + * License Agreement + * + * Copyright (c) 2008 + * Altera Corporation, San Jose, California, USA. + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * This agreement shall be governed in all respects by the laws of the State + * of California and by the laws of the United States of America. + */ + +MEMORY +{ + reset : ORIGIN = 0x1000000, LENGTH = 32 + sdram : ORIGIN = 0x1000020, LENGTH = 16777184 +} + +/* Define symbols for each memory base-address */ +__alt_mem_sdram = 0x1000000; + +OUTPUT_FORMAT( "elf32-littlenios2", + "elf32-littlenios2", + "elf32-littlenios2" ) +OUTPUT_ARCH( nios2 ) +ENTRY( _start ) + +/* + * The alt_load() facility is enabled. This typically happens when there isn't + * an external bootloader (e.g. flash bootloader). + * The LMA (aka physical address) of each loaded section is + * set to the .text memory device. + * The HAL alt_load() routine called from crt0 copies sections from + * the .text memory to RAM as needed. + */ + +SECTIONS +{ + + /* + * Output sections associated with reset and exceptions (they have to be first) + */ + + .entry : + { + KEEP (*(.entry)) + } > reset + + .exceptions : + { + PROVIDE (__ram_exceptions_start = ABSOLUTE(.)); + . = ALIGN(0x20); + KEEP (*(.irq)); + KEEP (*(.exceptions.entry.label)); + KEEP (*(.exceptions.entry.user)); + KEEP (*(.exceptions.entry)); + KEEP (*(.exceptions.irqtest.user)); + KEEP (*(.exceptions.irqtest)); + KEEP (*(.exceptions.irqhandler.user)); + KEEP (*(.exceptions.irqhandler)); + KEEP (*(.exceptions.irqreturn.user)); + KEEP (*(.exceptions.irqreturn)); + KEEP (*(.exceptions.notirq.label)); + KEEP (*(.exceptions.notirq.user)); + KEEP (*(.exceptions.notirq)); + KEEP (*(.exceptions.soft.user)); + KEEP (*(.exceptions.soft)); + KEEP (*(.exceptions.unknown.user)); + KEEP (*(.exceptions.unknown)); + KEEP (*(.exceptions.exit.label)); + KEEP (*(.exceptions.exit.user)); + KEEP (*(.exceptions.exit)); + KEEP (*(.exceptions)); + PROVIDE (__ram_exceptions_end = ABSOLUTE(.)); + } > sdram + + PROVIDE (__flash_exceptions_start = LOADADDR(.exceptions)); + + .text : + { + /* + * All code sections are merged into the text output section, along with + * the read only data sections. + * + */ + + PROVIDE (stext = ABSOLUTE(.)); + + *(.interp) + *(.hash) + *(.dynsym) + *(.dynstr) + *(.gnu.version) + *(.gnu.version_d) + *(.gnu.version_r) + *(.rel.init) + *(.rela.init) + *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) + *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) + *(.rel.fini) + *(.rela.fini) + *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) + *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) + *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) + *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) + *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) + *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) + *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) + *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) + *(.rel.ctors) + *(.rela.ctors) + *(.rel.dtors) + *(.rela.dtors) + *(.rel.got) + *(.rela.got) + *(.rel.sdata .rel.sdata.* .rel.gnu.linkonce.s.*) + *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*) + *(.rel.sbss .rel.sbss.* .rel.gnu.linkonce.sb.*) + *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*) + *(.rel.sdata2 .rel.sdata2.* .rel.gnu.linkonce.s2.*) + *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*) + *(.rel.sbss2 .rel.sbss2.* .rel.gnu.linkonce.sb2.*) + *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*) + *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) + *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) + *(.rel.plt) + *(.rela.plt) + *(.rel.dyn) + + KEEP (*(.init)) + *(.plt) + *(.text .stub .text.* .gnu.linkonce.t.*) + + /* .gnu.warning sections are handled specially by elf32.em. */ + + *(.gnu.warning.*) + KEEP (*(.fini)) + PROVIDE (__etext = ABSOLUTE(.)); + PROVIDE (_etext = ABSOLUTE(.)); + PROVIDE (etext = ABSOLUTE(.)); + + *(.eh_frame_hdr) + /* Ensure the __preinit_array_start label is properly aligned. We + could instead move the label definition inside the section, but + the linker would then create the section even if it turns out to + be empty, which isn't pretty. */ + . = ALIGN(4); + PROVIDE (__preinit_array_start = ABSOLUTE(.)); + *(.preinit_array) + PROVIDE (__preinit_array_end = ABSOLUTE(.)); + PROVIDE (__init_array_start = ABSOLUTE(.)); + *(.init_array) + PROVIDE (__init_array_end = ABSOLUTE(.)); + PROVIDE (__fini_array_start = ABSOLUTE(.)); + *(.fini_array) + PROVIDE (__fini_array_end = ABSOLUTE(.)); + SORT(CONSTRUCTORS) + KEEP (*(.eh_frame)) + *(.gcc_except_table) + *(.dynamic) + PROVIDE (__CTOR_LIST__ = ABSOLUTE(.)); + KEEP (*(.ctors)) + KEEP (*(SORT(.ctors.*))) + PROVIDE (__CTOR_END__ = ABSOLUTE(.)); + PROVIDE (__DTOR_LIST__ = ABSOLUTE(.)); + KEEP (*(.dtors)) + KEEP (*(SORT(.dtors.*))) + PROVIDE (__DTOR_END__ = ABSOLUTE(.)); + KEEP (*(.jcr)) + . = ALIGN(4); + } > sdram = 0x3a880100 /* Nios II NOP instruction */ + + .rodata : + { + PROVIDE (__ram_rodata_start = ABSOLUTE(.)); + . = ALIGN(4); + *(.rodata .rodata.* .gnu.linkonce.r.*) + *(.rodata1) + . = ALIGN(4); + PROVIDE (__ram_rodata_end = ABSOLUTE(.)); + } > sdram + + PROVIDE (__flash_rodata_start = LOADADDR(.rodata)); + + /* + * + * This section's LMA is set to the .text region. + * crt0 will copy to this section's specified mapped region virtual memory address (VMA) + * + * .rwdata region equals the .text region, and is set to be loaded into .text region. + * This requires two copies of .rwdata in the .text region. One read writable at VMA. + * and one read-only at LMA. crt0 will copy from LMA to VMA on reset + * + */ + + .rwdata LOADADDR (.rodata) + SIZEOF (.rodata) : AT ( LOADADDR (.rodata) + SIZEOF (.rodata)+ SIZEOF (.rwdata) ) + { + PROVIDE (__ram_rwdata_start = ABSOLUTE(.)); + . = ALIGN(4); + *(.got.plt) *(.got) + *(.data1) + *(.data .data.* .gnu.linkonce.d.*) + + _gp = ABSOLUTE(. + 0x8000); + PROVIDE(gp = _gp); + + *(.rwdata .rwdata.*) + *(.sdata .sdata.* .gnu.linkonce.s.*) + *(.sdata2 .sdata2.* .gnu.linkonce.s2.*) + + . = ALIGN(4); + _edata = ABSOLUTE(.); + PROVIDE (edata = ABSOLUTE(.)); + PROVIDE (__ram_rwdata_end = ABSOLUTE(.)); + } > sdram + + PROVIDE (__flash_rwdata_start = LOADADDR(.rwdata)); + + /* + * + * This section's LMA is set to the .text region. + * crt0 will copy to this section's specified mapped region virtual memory address (VMA) + * + */ + + .bss LOADADDR (.rwdata) + SIZEOF (.rwdata) : AT ( LOADADDR (.rwdata) + SIZEOF (.rwdata) ) + { + __bss_start = ABSOLUTE(.); + PROVIDE (__sbss_start = ABSOLUTE(.)); + PROVIDE (___sbss_start = ABSOLUTE(.)); + + *(.dynsbss) + *(.sbss .sbss.* .gnu.linkonce.sb.*) + *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*) + *(.scommon) + + PROVIDE (__sbss_end = ABSOLUTE(.)); + PROVIDE (___sbss_end = ABSOLUTE(.)); + + *(.dynbss) + *(.bss .bss.* .gnu.linkonce.b.*) + *(COMMON) + + . = ALIGN(4); + __bss_end = ABSOLUTE(.); + } > sdram + + /* + * + * One output section mapped to the associated memory device for each of + * the available memory devices. These are not used by default, but can + * be used by user applications by using the .section directive. + * + * The output section used for the heap is treated in a special way, + * i.e. the symbols "end" and "_end" are added to point to the heap start. + * + * Because alt_load() is enabled, these sections have + * their LMA set to be loaded into the .text memory region. + * However, the alt_load() code will NOT automatically copy + * these sections into their mapped memory region. + * + */ + + /* + * + * This section's LMA is set to the .text region. + * crt0 will copy to this section's specified mapped region virtual memory address (VMA) + * + */ + + .sdram LOADADDR (.bss) + SIZEOF (.bss) : AT ( LOADADDR (.bss) + SIZEOF (.bss) ) + { + PROVIDE (_alt_partition_sdram_start = ABSOLUTE(.)); + *(.sdram. sdram.*) + . = ALIGN(4); + PROVIDE (_alt_partition_sdram_end = ABSOLUTE(.)); + _end = ABSOLUTE(.); + end = ABSOLUTE(.); + __alt_stack_base = ABSOLUTE(.); + } > sdram + + PROVIDE (_alt_partition_sdram_load_addr = LOADADDR(.sdram)); + + /* + * Stabs debugging sections. + * + */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + + /* Altera debug extensions */ + .debug_alt_sim_info 0 : { *(.debug_alt_sim_info) } +} + +/* provide a pointer for the stack */ + +/* + * Don't override this, override the __alt_stack_* symbols instead. + */ +__alt_data_end = 0x2000000; + +/* + * The next two symbols define the location of the default stack. You can + * override them to move the stack to a different memory. + */ +PROVIDE( __alt_stack_pointer = __alt_data_end ); +PROVIDE( __alt_stack_limit = __alt_stack_base ); + +/* + * This symbol controls where the start of the heap is. If the stack is + * contiguous with the heap then the stack will contract as memory is + * allocated to the heap. + * Override this symbol to put the heap in a different memory. + */ +PROVIDE( __alt_heap_start = end ); +PROVIDE( __alt_heap_limit = 0x2000000 ); diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/mem_init.mk b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/mem_init.mk similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/mem_init.mk rename to MCandWifiTestDE0/Software/Archive/MCTest_bsp/mem_init.mk diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/memory.gdb b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/memory.gdb new file mode 100644 index 00000000..b685f21f --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/memory.gdb @@ -0,0 +1,50 @@ +# memory.gdb - GDB memory region definitions +# +# Machine generated for CPU 'cpu' in SOPC Builder design 'system' +# SOPC Builder design path: C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system.sopcinfo +# +# Generated: Mon Mar 03 15:52:38 MST 2014 + +# DO NOT MODIFY THIS FILE +# +# Changing this file will have subtle consequences +# which will almost certainly lead to a nonfunctioning +# system. If you do modify this file, be aware that your +# changes will be overwritten and lost when this file +# is generated again. +# +# DO NOT MODIFY THIS FILE + +# License Agreement +# +# Copyright (c) 2008 +# Altera Corporation, San Jose, California, USA. +# All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +# DEALINGS IN THE SOFTWARE. +# +# This agreement shall be governed in all respects by the laws of the State +# of California and by the laws of the United States of America. + +# Define memory regions for each memory connected to the CPU. +# The cache attribute is specified which improves GDB performance +# by allowing GDB to cache memory contents on the host. + +# sdram +memory 0x1000000 0x2000000 cache diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_alarm_start.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_alarm_start.d new file mode 100644 index 00000000..4db38228 --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_alarm_start.d @@ -0,0 +1,31 @@ +obj/HAL/src/alt_alarm_start.o: HAL/src/alt_alarm_start.c \ + HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \ + HAL/inc/priv/alt_alarm.h HAL/inc/alt_types.h HAL/inc/sys/alt_irq.h \ + HAL/inc/nios2.h system.h linker.h HAL/inc/priv/alt_legacy_irq.h \ + system.h HAL/inc/nios2.h HAL/inc/sys/alt_irq.h + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_alarm.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +system.h: + +linker.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/sys/alt_irq.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_alarm_start.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_alarm_start.o new file mode 100644 index 00000000..52430843 Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_alarm_start.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_busy_sleep.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_busy_sleep.d new file mode 100644 index 00000000..e93e80c4 --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_busy_sleep.d @@ -0,0 +1,10 @@ +obj/HAL/src/alt_busy_sleep.o: HAL/src/alt_busy_sleep.c system.h linker.h \ + HAL/inc/alt_types.h HAL/inc/priv/alt_busy_sleep.h + +system.h: + +linker.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_busy_sleep.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_busy_sleep.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_busy_sleep.o new file mode 100644 index 00000000..3e6c0f66 Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_busy_sleep.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_close.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_close.d new file mode 100644 index 00000000..517b93c3 --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_close.d @@ -0,0 +1,74 @@ +obj/HAL/src/alt_close.o: HAL/src/alt_close.c HAL/inc/sys/alt_errno.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_warning.h HAL/inc/priv/alt_file.h \ + HAL/inc/sys/alt_dev.h system.h linker.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h UCOSII/inc/os/alt_sem.h \ + UCOSII/inc/priv/alt_sem_ucosii.h HAL/inc/includes.h HAL/inc/os_cpu.h \ + HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/priv/alt_legacy_irq.h \ + system.h HAL/inc/nios2.h HAL/inc/sys/alt_irq.h UCOSII/inc/os_cfg.h \ + HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_alarm.h system.h UCOSII/inc/ucos_ii.h \ + UCOSII/inc/os_cfg.h HAL/inc/os_cpu.h HAL/inc/alt_types.h \ + HAL/inc/os/alt_syscall.h + +HAL/inc/sys/alt_errno.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_warning.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +UCOSII/inc/os/alt_sem.h: + +UCOSII/inc/priv/alt_sem_ucosii.h: + +HAL/inc/includes.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/sys/alt_irq.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +system.h: + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/os_cpu.h: + +HAL/inc/alt_types.h: + +HAL/inc/os/alt_syscall.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_close.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_close.o new file mode 100644 index 00000000..f0f62382 Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_close.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_dcache_flush.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_dcache_flush.d new file mode 100644 index 00000000..a0eaf8a1 --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_dcache_flush.d @@ -0,0 +1,15 @@ +obj/HAL/src/alt_dcache_flush.o: HAL/src/alt_dcache_flush.c \ + HAL/inc/nios2.h system.h linker.h HAL/inc/alt_types.h \ + HAL/inc/sys/alt_cache.h HAL/inc/alt_types.h + +HAL/inc/nios2.h: + +system.h: + +linker.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_cache.h: + +HAL/inc/alt_types.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_dcache_flush.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_dcache_flush.o new file mode 100644 index 00000000..4ad16b4e Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_dcache_flush.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_dcache_flush_all.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_dcache_flush_all.d new file mode 100644 index 00000000..792c3e4a --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_dcache_flush_all.d @@ -0,0 +1,15 @@ +obj/HAL/src/alt_dcache_flush_all.o: HAL/src/alt_dcache_flush_all.c \ + HAL/inc/nios2.h system.h linker.h HAL/inc/alt_types.h \ + HAL/inc/sys/alt_cache.h HAL/inc/alt_types.h + +HAL/inc/nios2.h: + +system.h: + +linker.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_cache.h: + +HAL/inc/alt_types.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_dcache_flush_all.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_dcache_flush_all.o new file mode 100644 index 00000000..67d647eb Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_dcache_flush_all.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_dcache_flush_no_writeback.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_dcache_flush_no_writeback.d new file mode 100644 index 00000000..867c42ba --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_dcache_flush_no_writeback.d @@ -0,0 +1,16 @@ +obj/HAL/src/alt_dcache_flush_no_writeback.o: \ + HAL/src/alt_dcache_flush_no_writeback.c HAL/inc/nios2.h system.h \ + linker.h HAL/inc/alt_types.h HAL/inc/sys/alt_cache.h \ + HAL/inc/alt_types.h + +HAL/inc/nios2.h: + +system.h: + +linker.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_cache.h: + +HAL/inc/alt_types.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_dcache_flush_no_writeback.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_dcache_flush_no_writeback.o new file mode 100644 index 00000000..aebfd4c1 Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_dcache_flush_no_writeback.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_dev.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_dev.d new file mode 100644 index 00000000..5a738e17 --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_dev.d @@ -0,0 +1,73 @@ +obj/HAL/src/alt_dev.o: HAL/src/alt_dev.c HAL/inc/sys/alt_dev.h system.h \ + linker.h HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/priv/alt_file.h HAL/inc/sys/alt_dev.h \ + UCOSII/inc/os/alt_sem.h UCOSII/inc/priv/alt_sem_ucosii.h \ + HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \ + HAL/inc/nios2.h HAL/inc/priv/alt_legacy_irq.h system.h HAL/inc/nios2.h \ + HAL/inc/sys/alt_irq.h UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h \ + HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h system.h \ + UCOSII/inc/ucos_ii.h UCOSII/inc/os_cfg.h HAL/inc/os_cpu.h \ + HAL/inc/alt_types.h HAL/inc/alt_types.h system.h + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +UCOSII/inc/os/alt_sem.h: + +UCOSII/inc/priv/alt_sem_ucosii.h: + +HAL/inc/includes.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/sys/alt_irq.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +system.h: + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/os_cpu.h: + +HAL/inc/alt_types.h: + +HAL/inc/alt_types.h: + +system.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_dev.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_dev.o new file mode 100644 index 00000000..9e467fe7 Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_dev.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_dev_llist_insert.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_dev_llist_insert.d new file mode 100644 index 00000000..344d0651 --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_dev_llist_insert.d @@ -0,0 +1,13 @@ +obj/HAL/src/alt_dev_llist_insert.o: HAL/src/alt_dev_llist_insert.c \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/alt_types.h HAL/inc/sys/alt_errno.h + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_errno.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_dev_llist_insert.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_dev_llist_insert.o new file mode 100644 index 00000000..500ae1c3 Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_dev_llist_insert.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_dma_rxchan_open.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_dma_rxchan_open.d new file mode 100644 index 00000000..1942c7da --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_dma_rxchan_open.d @@ -0,0 +1,74 @@ +obj/HAL/src/alt_dma_rxchan_open.o: HAL/src/alt_dma_rxchan_open.c \ + HAL/inc/sys/alt_dma.h HAL/inc/sys/alt_dma_dev.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/alt_types.h HAL/inc/sys/alt_errno.h \ + HAL/inc/priv/alt_file.h HAL/inc/sys/alt_dev.h system.h linker.h \ + HAL/inc/sys/alt_llist.h UCOSII/inc/os/alt_sem.h \ + UCOSII/inc/priv/alt_sem_ucosii.h HAL/inc/includes.h HAL/inc/os_cpu.h \ + HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/priv/alt_legacy_irq.h \ + system.h HAL/inc/nios2.h HAL/inc/sys/alt_irq.h UCOSII/inc/os_cfg.h \ + HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_alarm.h system.h UCOSII/inc/ucos_ii.h \ + UCOSII/inc/os_cfg.h HAL/inc/os_cpu.h HAL/inc/alt_types.h + +HAL/inc/sys/alt_dma.h: + +HAL/inc/sys/alt_dma_dev.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_errno.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +UCOSII/inc/os/alt_sem.h: + +UCOSII/inc/priv/alt_sem_ucosii.h: + +HAL/inc/includes.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/sys/alt_irq.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +system.h: + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/os_cpu.h: + +HAL/inc/alt_types.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_dma_rxchan_open.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_dma_rxchan_open.o new file mode 100644 index 00000000..765b1f35 Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_dma_rxchan_open.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_dma_txchan_open.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_dma_txchan_open.d new file mode 100644 index 00000000..91e5e694 --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_dma_txchan_open.d @@ -0,0 +1,74 @@ +obj/HAL/src/alt_dma_txchan_open.o: HAL/src/alt_dma_txchan_open.c \ + HAL/inc/sys/alt_dma.h HAL/inc/sys/alt_dma_dev.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/alt_types.h HAL/inc/sys/alt_errno.h \ + HAL/inc/priv/alt_file.h HAL/inc/sys/alt_dev.h system.h linker.h \ + HAL/inc/sys/alt_llist.h UCOSII/inc/os/alt_sem.h \ + UCOSII/inc/priv/alt_sem_ucosii.h HAL/inc/includes.h HAL/inc/os_cpu.h \ + HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/priv/alt_legacy_irq.h \ + system.h HAL/inc/nios2.h HAL/inc/sys/alt_irq.h UCOSII/inc/os_cfg.h \ + HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_alarm.h system.h UCOSII/inc/ucos_ii.h \ + UCOSII/inc/os_cfg.h HAL/inc/os_cpu.h HAL/inc/alt_types.h + +HAL/inc/sys/alt_dma.h: + +HAL/inc/sys/alt_dma_dev.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_errno.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +UCOSII/inc/os/alt_sem.h: + +UCOSII/inc/priv/alt_sem_ucosii.h: + +HAL/inc/includes.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/sys/alt_irq.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +system.h: + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/os_cpu.h: + +HAL/inc/alt_types.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_dma_txchan_open.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_dma_txchan_open.o new file mode 100644 index 00000000..f860a758 Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_dma_txchan_open.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_do_ctors.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_do_ctors.d new file mode 100644 index 00000000..daf8bafc --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_do_ctors.d @@ -0,0 +1 @@ +obj/HAL/src/alt_do_ctors.o: HAL/src/alt_do_ctors.c diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_do_ctors.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_do_ctors.o new file mode 100644 index 00000000..8c8382ad Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_do_ctors.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_do_dtors.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_do_dtors.d new file mode 100644 index 00000000..c3471ebe --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_do_dtors.d @@ -0,0 +1 @@ +obj/HAL/src/alt_do_dtors.o: HAL/src/alt_do_dtors.c diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_do_dtors.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_do_dtors.o new file mode 100644 index 00000000..408bae1c Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_do_dtors.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_environ.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_environ.d new file mode 100644 index 00000000..e9ca295b --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_environ.d @@ -0,0 +1,3 @@ +obj/HAL/src/alt_environ.o: HAL/src/alt_environ.c HAL/inc/os/alt_syscall.h + +HAL/inc/os/alt_syscall.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_environ.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_environ.o new file mode 100644 index 00000000..f4c0a55f Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_environ.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_errno.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_errno.d new file mode 100644 index 00000000..29ca5443 --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_errno.d @@ -0,0 +1,8 @@ +obj/HAL/src/alt_errno.o: HAL/src/alt_errno.c HAL/inc/sys/alt_errno.h \ + HAL/inc/alt_types.h HAL/inc/alt_types.h + +HAL/inc/sys/alt_errno.h: + +HAL/inc/alt_types.h: + +HAL/inc/alt_types.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_errno.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_errno.o new file mode 100644 index 00000000..a4bb6add Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_errno.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_exception_entry.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_exception_entry.d new file mode 100644 index 00000000..540567e6 --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_exception_entry.d @@ -0,0 +1,6 @@ +obj/HAL/src/alt_exception_entry.o: HAL/src/alt_exception_entry.S system.h \ + linker.h + +system.h: + +linker.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_exception_entry.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_exception_entry.o new file mode 100644 index 00000000..f3febed4 Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_exception_entry.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_exception_muldiv.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_exception_muldiv.d new file mode 100644 index 00000000..63d66a74 --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_exception_muldiv.d @@ -0,0 +1 @@ +obj/HAL/src/alt_exception_muldiv.o: HAL/src/alt_exception_muldiv.S diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_exception_muldiv.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_exception_muldiv.o new file mode 100644 index 00000000..1054a514 Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_exception_muldiv.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_exception_trap.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_exception_trap.d new file mode 100644 index 00000000..6e184888 --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_exception_trap.d @@ -0,0 +1 @@ +obj/HAL/src/alt_exception_trap.o: HAL/src/alt_exception_trap.S diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_exception_trap.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_exception_trap.o new file mode 100644 index 00000000..29817c56 Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_exception_trap.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_execve.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_execve.d new file mode 100644 index 00000000..9cef7d20 --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_execve.d @@ -0,0 +1,10 @@ +obj/HAL/src/alt_execve.o: HAL/src/alt_execve.c HAL/inc/sys/alt_errno.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_warning.h HAL/inc/os/alt_syscall.h + +HAL/inc/sys/alt_errno.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_warning.h: + +HAL/inc/os/alt_syscall.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_execve.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_execve.o new file mode 100644 index 00000000..4e4c5a5b Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_execve.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_exit.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_exit.d new file mode 100644 index 00000000..bab1db93 --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_exit.d @@ -0,0 +1,64 @@ +obj/HAL/src/alt_exit.o: HAL/src/alt_exit.c HAL/inc/sys/alt_irq.h \ + HAL/inc/nios2.h HAL/inc/alt_types.h system.h linker.h \ + HAL/inc/priv/alt_legacy_irq.h system.h HAL/inc/nios2.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_irq.h HAL/inc/sys/alt_sim.h \ + UCOSII/inc/os/alt_hooks.h HAL/inc/includes.h HAL/inc/os_cpu.h \ + HAL/inc/sys/alt_irq.h UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h \ + HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h system.h \ + UCOSII/inc/ucos_ii.h UCOSII/inc/os_cfg.h HAL/inc/os_cpu.h \ + HAL/inc/os/alt_syscall.h HAL/inc/alt_types.h \ + HAL/inc/sys/alt_log_printf.h system.h + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/sys/alt_sim.h: + +UCOSII/inc/os/alt_hooks.h: + +HAL/inc/includes.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +system.h: + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/os_cpu.h: + +HAL/inc/os/alt_syscall.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_log_printf.h: + +system.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_exit.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_exit.o new file mode 100644 index 00000000..32313e95 Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_exit.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_fcntl.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_fcntl.d new file mode 100644 index 00000000..aa2a44d8 --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_fcntl.d @@ -0,0 +1,73 @@ +obj/HAL/src/alt_fcntl.o: HAL/src/alt_fcntl.c HAL/inc/sys/alt_errno.h \ + HAL/inc/alt_types.h HAL/inc/priv/alt_file.h HAL/inc/sys/alt_dev.h \ + system.h linker.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_dev_llist.h \ + HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h UCOSII/inc/os/alt_sem.h \ + UCOSII/inc/priv/alt_sem_ucosii.h HAL/inc/includes.h HAL/inc/os_cpu.h \ + HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/priv/alt_legacy_irq.h \ + system.h HAL/inc/nios2.h HAL/inc/sys/alt_irq.h UCOSII/inc/os_cfg.h \ + HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_alarm.h system.h UCOSII/inc/ucos_ii.h \ + UCOSII/inc/os_cfg.h HAL/inc/os_cpu.h HAL/inc/alt_types.h \ + HAL/inc/alt_types.h HAL/inc/os/alt_syscall.h + +HAL/inc/sys/alt_errno.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +UCOSII/inc/os/alt_sem.h: + +UCOSII/inc/priv/alt_sem_ucosii.h: + +HAL/inc/includes.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/sys/alt_irq.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +system.h: + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/os_cpu.h: + +HAL/inc/alt_types.h: + +HAL/inc/alt_types.h: + +HAL/inc/os/alt_syscall.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_fcntl.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_fcntl.o new file mode 100644 index 00000000..6b2f54a2 Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_fcntl.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_fd_lock.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_fd_lock.d new file mode 100644 index 00000000..249754ea --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_fd_lock.d @@ -0,0 +1,66 @@ +obj/HAL/src/alt_fd_lock.o: HAL/src/alt_fd_lock.c HAL/inc/priv/alt_file.h \ + HAL/inc/sys/alt_dev.h system.h linker.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/priv/alt_dev_llist.h \ + HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h UCOSII/inc/os/alt_sem.h \ + UCOSII/inc/priv/alt_sem_ucosii.h HAL/inc/includes.h HAL/inc/os_cpu.h \ + HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/priv/alt_legacy_irq.h \ + system.h HAL/inc/nios2.h HAL/inc/sys/alt_irq.h UCOSII/inc/os_cfg.h \ + HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_alarm.h system.h UCOSII/inc/ucos_ii.h \ + UCOSII/inc/os_cfg.h HAL/inc/os_cpu.h HAL/inc/alt_types.h + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +UCOSII/inc/os/alt_sem.h: + +UCOSII/inc/priv/alt_sem_ucosii.h: + +HAL/inc/includes.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/sys/alt_irq.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +system.h: + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/os_cpu.h: + +HAL/inc/alt_types.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_fd_lock.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_fd_lock.o new file mode 100644 index 00000000..290532d8 Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_fd_lock.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_fd_unlock.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_fd_unlock.d new file mode 100644 index 00000000..fc9666c7 --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_fd_unlock.d @@ -0,0 +1,67 @@ +obj/HAL/src/alt_fd_unlock.o: HAL/src/alt_fd_unlock.c \ + HAL/inc/priv/alt_file.h HAL/inc/sys/alt_dev.h system.h linker.h \ + HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h UCOSII/inc/os/alt_sem.h \ + UCOSII/inc/priv/alt_sem_ucosii.h HAL/inc/includes.h HAL/inc/os_cpu.h \ + HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/priv/alt_legacy_irq.h \ + system.h HAL/inc/nios2.h HAL/inc/sys/alt_irq.h UCOSII/inc/os_cfg.h \ + HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_alarm.h system.h UCOSII/inc/ucos_ii.h \ + UCOSII/inc/os_cfg.h HAL/inc/os_cpu.h HAL/inc/alt_types.h + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +UCOSII/inc/os/alt_sem.h: + +UCOSII/inc/priv/alt_sem_ucosii.h: + +HAL/inc/includes.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/sys/alt_irq.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +system.h: + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/os_cpu.h: + +HAL/inc/alt_types.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_fd_unlock.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_fd_unlock.o new file mode 100644 index 00000000..04d1e3a5 Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_fd_unlock.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_find_dev.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_find_dev.d new file mode 100644 index 00000000..5971c9fe --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_find_dev.d @@ -0,0 +1,71 @@ +obj/HAL/src/alt_find_dev.o: HAL/src/alt_find_dev.c HAL/inc/sys/alt_dev.h \ + system.h linker.h HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/priv/alt_file.h HAL/inc/sys/alt_dev.h \ + UCOSII/inc/os/alt_sem.h UCOSII/inc/priv/alt_sem_ucosii.h \ + HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \ + HAL/inc/nios2.h HAL/inc/priv/alt_legacy_irq.h system.h HAL/inc/nios2.h \ + HAL/inc/sys/alt_irq.h UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h \ + HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h system.h \ + UCOSII/inc/ucos_ii.h UCOSII/inc/os_cfg.h HAL/inc/os_cpu.h \ + HAL/inc/alt_types.h HAL/inc/alt_types.h + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +UCOSII/inc/os/alt_sem.h: + +UCOSII/inc/priv/alt_sem_ucosii.h: + +HAL/inc/includes.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/sys/alt_irq.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +system.h: + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/os_cpu.h: + +HAL/inc/alt_types.h: + +HAL/inc/alt_types.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_find_dev.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_find_dev.o new file mode 100644 index 00000000..7886a26b Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_find_dev.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_find_file.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_find_file.d new file mode 100644 index 00000000..1b93849b --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_find_file.d @@ -0,0 +1,72 @@ +obj/HAL/src/alt_find_file.o: HAL/src/alt_find_file.c \ + HAL/inc/sys/alt_dev.h system.h linker.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/priv/alt_dev_llist.h \ + HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h HAL/inc/priv/alt_file.h \ + HAL/inc/sys/alt_dev.h UCOSII/inc/os/alt_sem.h \ + UCOSII/inc/priv/alt_sem_ucosii.h HAL/inc/includes.h HAL/inc/os_cpu.h \ + HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/priv/alt_legacy_irq.h \ + system.h HAL/inc/nios2.h HAL/inc/sys/alt_irq.h UCOSII/inc/os_cfg.h \ + HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_alarm.h system.h UCOSII/inc/ucos_ii.h \ + UCOSII/inc/os_cfg.h HAL/inc/os_cpu.h HAL/inc/alt_types.h \ + HAL/inc/alt_types.h + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +UCOSII/inc/os/alt_sem.h: + +UCOSII/inc/priv/alt_sem_ucosii.h: + +HAL/inc/includes.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/sys/alt_irq.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +system.h: + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/os_cpu.h: + +HAL/inc/alt_types.h: + +HAL/inc/alt_types.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_find_file.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_find_file.o new file mode 100644 index 00000000..344faa8a Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_find_file.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_flash_dev.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_flash_dev.d new file mode 100644 index 00000000..4592b116 --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_flash_dev.d @@ -0,0 +1,74 @@ +obj/HAL/src/alt_flash_dev.o: HAL/src/alt_flash_dev.c \ + HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h HAL/inc/sys/alt_flash_dev.h \ + HAL/inc/sys/alt_flash_types.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/priv/alt_file.h HAL/inc/sys/alt_dev.h \ + system.h linker.h UCOSII/inc/os/alt_sem.h \ + UCOSII/inc/priv/alt_sem_ucosii.h HAL/inc/includes.h HAL/inc/os_cpu.h \ + HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/priv/alt_legacy_irq.h \ + system.h HAL/inc/nios2.h HAL/inc/sys/alt_irq.h UCOSII/inc/os_cfg.h \ + HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_alarm.h system.h UCOSII/inc/ucos_ii.h \ + UCOSII/inc/os_cfg.h HAL/inc/os_cpu.h HAL/inc/alt_types.h + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_flash_dev.h: + +HAL/inc/sys/alt_flash_types.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +UCOSII/inc/os/alt_sem.h: + +UCOSII/inc/priv/alt_sem_ucosii.h: + +HAL/inc/includes.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/sys/alt_irq.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +system.h: + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/os_cpu.h: + +HAL/inc/alt_types.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_flash_dev.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_flash_dev.o new file mode 100644 index 00000000..df3a78c9 Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_flash_dev.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_fork.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_fork.d new file mode 100644 index 00000000..492be651 --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_fork.d @@ -0,0 +1,10 @@ +obj/HAL/src/alt_fork.o: HAL/src/alt_fork.c HAL/inc/sys/alt_warning.h \ + HAL/inc/sys/alt_errno.h HAL/inc/alt_types.h HAL/inc/os/alt_syscall.h + +HAL/inc/sys/alt_warning.h: + +HAL/inc/sys/alt_errno.h: + +HAL/inc/alt_types.h: + +HAL/inc/os/alt_syscall.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_fork.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_fork.o new file mode 100644 index 00000000..12538b05 Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_fork.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_fs_reg.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_fs_reg.d new file mode 100644 index 00000000..d5ccf1ad --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_fs_reg.d @@ -0,0 +1,69 @@ +obj/HAL/src/alt_fs_reg.o: HAL/src/alt_fs_reg.c HAL/inc/sys/alt_dev.h \ + system.h linker.h HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/priv/alt_file.h HAL/inc/sys/alt_dev.h \ + UCOSII/inc/os/alt_sem.h UCOSII/inc/priv/alt_sem_ucosii.h \ + HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \ + HAL/inc/nios2.h HAL/inc/priv/alt_legacy_irq.h system.h HAL/inc/nios2.h \ + HAL/inc/sys/alt_irq.h UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h \ + HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h system.h \ + UCOSII/inc/ucos_ii.h UCOSII/inc/os_cfg.h HAL/inc/os_cpu.h \ + HAL/inc/alt_types.h + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +UCOSII/inc/os/alt_sem.h: + +UCOSII/inc/priv/alt_sem_ucosii.h: + +HAL/inc/includes.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/sys/alt_irq.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +system.h: + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/os_cpu.h: + +HAL/inc/alt_types.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_fs_reg.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_fs_reg.o new file mode 100644 index 00000000..684315a3 Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_fs_reg.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_fstat.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_fstat.d new file mode 100644 index 00000000..5385b6e1 --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_fstat.d @@ -0,0 +1,76 @@ +obj/HAL/src/alt_fstat.o: HAL/src/alt_fstat.c HAL/inc/sys/alt_dev.h \ + system.h linker.h HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_warning.h HAL/inc/sys/alt_errno.h \ + HAL/inc/priv/alt_file.h HAL/inc/sys/alt_dev.h UCOSII/inc/os/alt_sem.h \ + UCOSII/inc/priv/alt_sem_ucosii.h HAL/inc/includes.h HAL/inc/os_cpu.h \ + HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/priv/alt_legacy_irq.h \ + system.h HAL/inc/nios2.h HAL/inc/sys/alt_irq.h UCOSII/inc/os_cfg.h \ + HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_alarm.h system.h UCOSII/inc/ucos_ii.h \ + UCOSII/inc/os_cfg.h HAL/inc/os_cpu.h HAL/inc/alt_types.h \ + HAL/inc/os/alt_syscall.h + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_warning.h: + +HAL/inc/sys/alt_errno.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +UCOSII/inc/os/alt_sem.h: + +UCOSII/inc/priv/alt_sem_ucosii.h: + +HAL/inc/includes.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/sys/alt_irq.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +system.h: + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/os_cpu.h: + +HAL/inc/alt_types.h: + +HAL/inc/os/alt_syscall.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_fstat.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_fstat.o new file mode 100644 index 00000000..4be1a6b7 Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_fstat.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_get_fd.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_get_fd.d new file mode 100644 index 00000000..d579fd48 --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_get_fd.d @@ -0,0 +1,73 @@ +obj/HAL/src/alt_get_fd.o: HAL/src/alt_get_fd.c HAL/inc/sys/alt_dev.h \ + system.h linker.h HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/priv/alt_file.h HAL/inc/sys/alt_dev.h \ + UCOSII/inc/os/alt_sem.h UCOSII/inc/priv/alt_sem_ucosii.h \ + HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \ + HAL/inc/nios2.h HAL/inc/priv/alt_legacy_irq.h system.h HAL/inc/nios2.h \ + HAL/inc/sys/alt_irq.h UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h \ + HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h system.h \ + UCOSII/inc/ucos_ii.h UCOSII/inc/os_cfg.h HAL/inc/os_cpu.h \ + HAL/inc/alt_types.h HAL/inc/alt_types.h system.h + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +UCOSII/inc/os/alt_sem.h: + +UCOSII/inc/priv/alt_sem_ucosii.h: + +HAL/inc/includes.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/sys/alt_irq.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +system.h: + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/os_cpu.h: + +HAL/inc/alt_types.h: + +HAL/inc/alt_types.h: + +system.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_get_fd.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_get_fd.o new file mode 100644 index 00000000..6814e93d Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_get_fd.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_getchar.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_getchar.d new file mode 100644 index 00000000..2a468def --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_getchar.d @@ -0,0 +1 @@ +obj/HAL/src/alt_getchar.o: HAL/src/alt_getchar.c diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_getchar.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_getchar.o new file mode 100644 index 00000000..f4a93d6d Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_getchar.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_getpid.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_getpid.d new file mode 100644 index 00000000..d9499b94 --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_getpid.d @@ -0,0 +1,3 @@ +obj/HAL/src/alt_getpid.o: HAL/src/alt_getpid.c HAL/inc/os/alt_syscall.h + +HAL/inc/os/alt_syscall.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_getpid.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_getpid.o new file mode 100644 index 00000000..520ee989 Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_getpid.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_gettod.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_gettod.d new file mode 100644 index 00000000..cf3cf343 --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_gettod.d @@ -0,0 +1,17 @@ +obj/HAL/src/alt_gettod.o: HAL/src/alt_gettod.c HAL/inc/sys/alt_alarm.h \ + HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h HAL/inc/priv/alt_alarm.h \ + HAL/inc/alt_types.h HAL/inc/alt_types.h HAL/inc/os/alt_syscall.h + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_alarm.h: + +HAL/inc/alt_types.h: + +HAL/inc/alt_types.h: + +HAL/inc/os/alt_syscall.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_gettod.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_gettod.o new file mode 100644 index 00000000..9f3b0d84 Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_gettod.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_gmon.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_gmon.d new file mode 100644 index 00000000..2ec2b57d --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_gmon.d @@ -0,0 +1,33 @@ +obj/HAL/src/alt_gmon.o: HAL/src/alt_gmon.c HAL/inc/priv/nios2_gmon_data.h \ + HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/alt_types.h system.h \ + linker.h HAL/inc/priv/alt_legacy_irq.h system.h HAL/inc/nios2.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_irq.h HAL/inc/sys/alt_alarm.h \ + HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h + +HAL/inc/priv/nios2_gmon_data.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_gmon.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_gmon.o new file mode 100644 index 00000000..5e31c2c3 Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_gmon.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_icache_flush.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_icache_flush.d new file mode 100644 index 00000000..2e4ddd18 --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_icache_flush.d @@ -0,0 +1,15 @@ +obj/HAL/src/alt_icache_flush.o: HAL/src/alt_icache_flush.c \ + HAL/inc/nios2.h system.h linker.h HAL/inc/alt_types.h \ + HAL/inc/sys/alt_cache.h HAL/inc/alt_types.h + +HAL/inc/nios2.h: + +system.h: + +linker.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_cache.h: + +HAL/inc/alt_types.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_icache_flush.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_icache_flush.o new file mode 100644 index 00000000..e81adc0a Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_icache_flush.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_icache_flush_all.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_icache_flush_all.d new file mode 100644 index 00000000..47cfbf38 --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_icache_flush_all.d @@ -0,0 +1,15 @@ +obj/HAL/src/alt_icache_flush_all.o: HAL/src/alt_icache_flush_all.c \ + HAL/inc/nios2.h system.h linker.h HAL/inc/alt_types.h \ + HAL/inc/sys/alt_cache.h HAL/inc/alt_types.h + +HAL/inc/nios2.h: + +system.h: + +linker.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_cache.h: + +HAL/inc/alt_types.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_icache_flush_all.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_icache_flush_all.o new file mode 100644 index 00000000..6cb7f5c9 Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_icache_flush_all.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_iic.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_iic.d new file mode 100644 index 00000000..572d1fc3 --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_iic.d @@ -0,0 +1,5 @@ +obj/HAL/src/alt_iic.o: HAL/src/alt_iic.c system.h linker.h + +system.h: + +linker.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_iic.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_iic.o new file mode 100644 index 00000000..f85a36c8 Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_iic.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_iic_isr_register.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_iic_isr_register.d new file mode 100644 index 00000000..f54a6859 --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_iic_isr_register.d @@ -0,0 +1,6 @@ +obj/HAL/src/alt_iic_isr_register.o: HAL/src/alt_iic_isr_register.c \ + system.h linker.h + +system.h: + +linker.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_iic_isr_register.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_iic_isr_register.o new file mode 100644 index 00000000..d22d465f Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_iic_isr_register.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_instruction_exception_entry.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_instruction_exception_entry.d new file mode 100644 index 00000000..6d0705f5 --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_instruction_exception_entry.d @@ -0,0 +1,18 @@ +obj/HAL/src/alt_instruction_exception_entry.o: \ + HAL/src/alt_instruction_exception_entry.c HAL/inc/sys/alt_exceptions.h \ + HAL/inc/alt_types.h system.h linker.h HAL/inc/nios2.h \ + HAL/inc/alt_types.h system.h + +HAL/inc/sys/alt_exceptions.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +system.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_instruction_exception_entry.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_instruction_exception_entry.o new file mode 100644 index 00000000..93653490 Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_instruction_exception_entry.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_instruction_exception_register.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_instruction_exception_register.d new file mode 100644 index 00000000..d4fac042 --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_instruction_exception_register.d @@ -0,0 +1,16 @@ +obj/HAL/src/alt_instruction_exception_register.o: \ + HAL/src/alt_instruction_exception_register.c \ + HAL/inc/sys/alt_exceptions.h HAL/inc/alt_types.h system.h linker.h \ + HAL/inc/alt_types.h system.h + +HAL/inc/sys/alt_exceptions.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: + +HAL/inc/alt_types.h: + +system.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_instruction_exception_register.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_instruction_exception_register.o new file mode 100644 index 00000000..0ad955be Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_instruction_exception_register.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_io_redirect.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_io_redirect.d new file mode 100644 index 00000000..d851a0e5 --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_io_redirect.d @@ -0,0 +1,69 @@ +obj/HAL/src/alt_io_redirect.o: HAL/src/alt_io_redirect.c \ + HAL/inc/sys/alt_dev.h system.h linker.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/priv/alt_dev_llist.h \ + HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h HAL/inc/priv/alt_file.h \ + HAL/inc/sys/alt_dev.h UCOSII/inc/os/alt_sem.h \ + UCOSII/inc/priv/alt_sem_ucosii.h HAL/inc/includes.h HAL/inc/os_cpu.h \ + HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/priv/alt_legacy_irq.h \ + system.h HAL/inc/nios2.h HAL/inc/sys/alt_irq.h UCOSII/inc/os_cfg.h \ + HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_alarm.h system.h UCOSII/inc/ucos_ii.h \ + UCOSII/inc/os_cfg.h HAL/inc/os_cpu.h HAL/inc/alt_types.h + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +UCOSII/inc/os/alt_sem.h: + +UCOSII/inc/priv/alt_sem_ucosii.h: + +HAL/inc/includes.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/sys/alt_irq.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +system.h: + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/os_cpu.h: + +HAL/inc/alt_types.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_io_redirect.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_io_redirect.o new file mode 100644 index 00000000..1c80d984 Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_io_redirect.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_ioctl.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_ioctl.d new file mode 100644 index 00000000..39ac3db6 --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_ioctl.d @@ -0,0 +1,76 @@ +obj/HAL/src/alt_ioctl.o: HAL/src/alt_ioctl.c HAL/inc/sys/ioctl.h \ + HAL/inc/sys/alt_errno.h HAL/inc/alt_types.h HAL/inc/sys/alt_warning.h \ + HAL/inc/priv/alt_file.h HAL/inc/sys/alt_dev.h system.h linker.h \ + HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_dev_llist.h \ + HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h UCOSII/inc/os/alt_sem.h \ + UCOSII/inc/priv/alt_sem_ucosii.h HAL/inc/includes.h HAL/inc/os_cpu.h \ + HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/priv/alt_legacy_irq.h \ + system.h HAL/inc/nios2.h HAL/inc/sys/alt_irq.h UCOSII/inc/os_cfg.h \ + HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_alarm.h system.h UCOSII/inc/ucos_ii.h \ + UCOSII/inc/os_cfg.h HAL/inc/os_cpu.h HAL/inc/alt_types.h \ + HAL/inc/os/alt_syscall.h + +HAL/inc/sys/ioctl.h: + +HAL/inc/sys/alt_errno.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_warning.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +UCOSII/inc/os/alt_sem.h: + +UCOSII/inc/priv/alt_sem_ucosii.h: + +HAL/inc/includes.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/sys/alt_irq.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +system.h: + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/os_cpu.h: + +HAL/inc/alt_types.h: + +HAL/inc/os/alt_syscall.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_ioctl.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_ioctl.o new file mode 100644 index 00000000..4e006ead Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_ioctl.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_irq_entry.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_irq_entry.d new file mode 100644 index 00000000..9ec37513 --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_irq_entry.d @@ -0,0 +1,5 @@ +obj/HAL/src/alt_irq_entry.o: HAL/src/alt_irq_entry.S system.h linker.h + +system.h: + +linker.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_irq_entry.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_irq_entry.o new file mode 100644 index 00000000..a29788a2 Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_irq_entry.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_irq_handler.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_irq_handler.d new file mode 100644 index 00000000..8ebea6c3 --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_irq_handler.d @@ -0,0 +1,56 @@ +obj/HAL/src/alt_irq_handler.o: HAL/src/alt_irq_handler.c system.h \ + linker.h HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/alt_types.h \ + system.h HAL/inc/priv/alt_legacy_irq.h system.h HAL/inc/nios2.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_irq.h UCOSII/inc/os/alt_hooks.h \ + HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \ + UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_alarm.h system.h UCOSII/inc/ucos_ii.h \ + UCOSII/inc/os_cfg.h HAL/inc/os_cpu.h HAL/inc/alt_types.h + +system.h: + +linker.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +system.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_irq.h: + +UCOSII/inc/os/alt_hooks.h: + +HAL/inc/includes.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +system.h: + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/os_cpu.h: + +HAL/inc/alt_types.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_irq_handler.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_irq_handler.o new file mode 100644 index 00000000..a260c025 Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_irq_handler.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_irq_register.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_irq_register.d new file mode 100644 index 00000000..607377ae --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_irq_register.d @@ -0,0 +1,64 @@ +obj/HAL/src/alt_irq_register.o: HAL/src/alt_irq_register.c system.h \ + linker.h HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/alt_types.h \ + system.h HAL/inc/priv/alt_legacy_irq.h system.h HAL/inc/nios2.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_irq.h HAL/inc/priv/alt_legacy_irq.h \ + UCOSII/inc/os/alt_hooks.h HAL/inc/includes.h HAL/inc/os_cpu.h \ + HAL/inc/sys/alt_irq.h UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h \ + HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h system.h \ + UCOSII/inc/ucos_ii.h UCOSII/inc/os_cfg.h HAL/inc/os_cpu.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_irq_entry.h \ + HAL/inc/priv/alt_irq_table.h + +system.h: + +linker.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +system.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/priv/alt_legacy_irq.h: + +UCOSII/inc/os/alt_hooks.h: + +HAL/inc/includes.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +system.h: + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/os_cpu.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_irq_entry.h: + +HAL/inc/priv/alt_irq_table.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_irq_register.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_irq_register.o new file mode 100644 index 00000000..addd4a6b Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_irq_register.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_irq_vars.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_irq_vars.d new file mode 100644 index 00000000..f316558a --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_irq_vars.d @@ -0,0 +1,8 @@ +obj/HAL/src/alt_irq_vars.o: HAL/src/alt_irq_vars.c HAL/inc/alt_types.h \ + system.h linker.h + +HAL/inc/alt_types.h: + +system.h: + +linker.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_irq_vars.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_irq_vars.o new file mode 100644 index 00000000..b04281c9 Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_irq_vars.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_isatty.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_isatty.d new file mode 100644 index 00000000..ead56fcc --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_isatty.d @@ -0,0 +1,76 @@ +obj/HAL/src/alt_isatty.o: HAL/src/alt_isatty.c HAL/inc/sys/alt_dev.h \ + system.h linker.h HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_errno.h HAL/inc/sys/alt_warning.h \ + HAL/inc/priv/alt_file.h HAL/inc/sys/alt_dev.h UCOSII/inc/os/alt_sem.h \ + UCOSII/inc/priv/alt_sem_ucosii.h HAL/inc/includes.h HAL/inc/os_cpu.h \ + HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/priv/alt_legacy_irq.h \ + system.h HAL/inc/nios2.h HAL/inc/sys/alt_irq.h UCOSII/inc/os_cfg.h \ + HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_alarm.h system.h UCOSII/inc/ucos_ii.h \ + UCOSII/inc/os_cfg.h HAL/inc/os_cpu.h HAL/inc/alt_types.h \ + HAL/inc/os/alt_syscall.h + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_errno.h: + +HAL/inc/sys/alt_warning.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +UCOSII/inc/os/alt_sem.h: + +UCOSII/inc/priv/alt_sem_ucosii.h: + +HAL/inc/includes.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/sys/alt_irq.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +system.h: + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/os_cpu.h: + +HAL/inc/alt_types.h: + +HAL/inc/os/alt_syscall.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_isatty.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_isatty.o new file mode 100644 index 00000000..e0051107 Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_isatty.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_kill.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_kill.d new file mode 100644 index 00000000..0c14ae80 --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_kill.d @@ -0,0 +1,8 @@ +obj/HAL/src/alt_kill.o: HAL/src/alt_kill.c HAL/inc/sys/alt_errno.h \ + HAL/inc/alt_types.h HAL/inc/os/alt_syscall.h + +HAL/inc/sys/alt_errno.h: + +HAL/inc/alt_types.h: + +HAL/inc/os/alt_syscall.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_kill.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_kill.o new file mode 100644 index 00000000..3644ce69 Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_kill.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_link.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_link.d new file mode 100644 index 00000000..dc844c6a --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_link.d @@ -0,0 +1,10 @@ +obj/HAL/src/alt_link.o: HAL/src/alt_link.c HAL/inc/sys/alt_warning.h \ + HAL/inc/sys/alt_errno.h HAL/inc/alt_types.h HAL/inc/os/alt_syscall.h + +HAL/inc/sys/alt_warning.h: + +HAL/inc/sys/alt_errno.h: + +HAL/inc/alt_types.h: + +HAL/inc/os/alt_syscall.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_link.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_link.o new file mode 100644 index 00000000..3f068d00 Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_link.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_load.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_load.d new file mode 100644 index 00000000..d496ab8d --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_load.d @@ -0,0 +1,8 @@ +obj/HAL/src/alt_load.o: HAL/src/alt_load.c HAL/inc/sys/alt_load.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_cache.h + +HAL/inc/sys/alt_load.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_cache.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_load.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_load.o new file mode 100644 index 00000000..6446076c Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_load.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_log_macro.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_log_macro.d new file mode 100644 index 00000000..9768c1fa --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_log_macro.d @@ -0,0 +1 @@ +obj/HAL/src/alt_log_macro.o: HAL/src/alt_log_macro.S diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_log_macro.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_log_macro.o new file mode 100644 index 00000000..489e2cc3 Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_log_macro.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_log_printf.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_log_printf.d new file mode 100644 index 00000000..251ff6db --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_log_printf.d @@ -0,0 +1 @@ +obj/HAL/src/alt_log_printf.o: HAL/src/alt_log_printf.c diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_log_printf.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_log_printf.o new file mode 100644 index 00000000..7a0f38c2 Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_log_printf.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_lseek.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_lseek.d new file mode 100644 index 00000000..7edaff1d --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_lseek.d @@ -0,0 +1,74 @@ +obj/HAL/src/alt_lseek.o: HAL/src/alt_lseek.c HAL/inc/sys/alt_errno.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_warning.h HAL/inc/priv/alt_file.h \ + HAL/inc/sys/alt_dev.h system.h linker.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h UCOSII/inc/os/alt_sem.h \ + UCOSII/inc/priv/alt_sem_ucosii.h HAL/inc/includes.h HAL/inc/os_cpu.h \ + HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/priv/alt_legacy_irq.h \ + system.h HAL/inc/nios2.h HAL/inc/sys/alt_irq.h UCOSII/inc/os_cfg.h \ + HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_alarm.h system.h UCOSII/inc/ucos_ii.h \ + UCOSII/inc/os_cfg.h HAL/inc/os_cpu.h HAL/inc/alt_types.h \ + HAL/inc/os/alt_syscall.h + +HAL/inc/sys/alt_errno.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_warning.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +UCOSII/inc/os/alt_sem.h: + +UCOSII/inc/priv/alt_sem_ucosii.h: + +HAL/inc/includes.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/sys/alt_irq.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +system.h: + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/os_cpu.h: + +HAL/inc/alt_types.h: + +HAL/inc/os/alt_syscall.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_lseek.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_lseek.o new file mode 100644 index 00000000..38d9e421 Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_lseek.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_main.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_main.d new file mode 100644 index 00000000..f8c2cda4 --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_main.d @@ -0,0 +1,87 @@ +obj/HAL/src/alt_main.o: HAL/src/alt_main.c HAL/inc/sys/alt_dev.h system.h \ + linker.h HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_sys_init.h HAL/inc/sys/alt_irq.h \ + HAL/inc/nios2.h HAL/inc/priv/alt_legacy_irq.h system.h HAL/inc/nios2.h \ + HAL/inc/sys/alt_irq.h UCOSII/inc/os/alt_hooks.h HAL/inc/includes.h \ + HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h UCOSII/inc/os_cfg.h \ + HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_alarm.h system.h UCOSII/inc/ucos_ii.h \ + UCOSII/inc/os_cfg.h HAL/inc/os_cpu.h HAL/inc/priv/alt_file.h \ + HAL/inc/sys/alt_dev.h UCOSII/inc/os/alt_sem.h \ + UCOSII/inc/priv/alt_sem_ucosii.h HAL/inc/includes.h HAL/inc/alt_types.h \ + HAL/inc/alt_types.h system.h HAL/inc/sys/alt_log_printf.h system.h + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_sys_init.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/sys/alt_irq.h: + +UCOSII/inc/os/alt_hooks.h: + +HAL/inc/includes.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +system.h: + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/os_cpu.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +UCOSII/inc/os/alt_sem.h: + +UCOSII/inc/priv/alt_sem_ucosii.h: + +HAL/inc/includes.h: + +HAL/inc/alt_types.h: + +HAL/inc/alt_types.h: + +system.h: + +HAL/inc/sys/alt_log_printf.h: + +system.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_main.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_main.o new file mode 100644 index 00000000..71bf5896 Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_main.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_mcount.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_mcount.d new file mode 100644 index 00000000..1203efcc --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_mcount.d @@ -0,0 +1 @@ +obj/HAL/src/alt_mcount.o: HAL/src/alt_mcount.S diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_mcount.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_mcount.o new file mode 100644 index 00000000..8a824390 Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_mcount.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_open.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_open.d new file mode 100644 index 00000000..2ff521af --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_open.d @@ -0,0 +1,76 @@ +obj/HAL/src/alt_open.o: HAL/src/alt_open.c HAL/inc/sys/alt_errno.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_warning.h HAL/inc/priv/alt_file.h \ + HAL/inc/sys/alt_dev.h system.h linker.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h UCOSII/inc/os/alt_sem.h \ + UCOSII/inc/priv/alt_sem_ucosii.h HAL/inc/includes.h HAL/inc/os_cpu.h \ + HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/priv/alt_legacy_irq.h \ + system.h HAL/inc/nios2.h HAL/inc/sys/alt_irq.h UCOSII/inc/os_cfg.h \ + HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_alarm.h system.h UCOSII/inc/ucos_ii.h \ + UCOSII/inc/os_cfg.h HAL/inc/os_cpu.h HAL/inc/alt_types.h \ + HAL/inc/alt_types.h HAL/inc/os/alt_syscall.h + +HAL/inc/sys/alt_errno.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_warning.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +UCOSII/inc/os/alt_sem.h: + +UCOSII/inc/priv/alt_sem_ucosii.h: + +HAL/inc/includes.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/sys/alt_irq.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +system.h: + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/os_cpu.h: + +HAL/inc/alt_types.h: + +HAL/inc/alt_types.h: + +HAL/inc/os/alt_syscall.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_open.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_open.o new file mode 100644 index 00000000..b8c86d91 Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_open.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_printf.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_printf.d new file mode 100644 index 00000000..3ce68a43 --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_printf.d @@ -0,0 +1,3 @@ +obj/HAL/src/alt_printf.o: HAL/src/alt_printf.c HAL/inc/sys/alt_stdio.h + +HAL/inc/sys/alt_stdio.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_printf.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_printf.o new file mode 100644 index 00000000..54fa8bc8 Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_printf.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_putchar.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_putchar.d new file mode 100644 index 00000000..0f19fb81 --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_putchar.d @@ -0,0 +1 @@ +obj/HAL/src/alt_putchar.o: HAL/src/alt_putchar.c diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_putchar.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_putchar.o new file mode 100644 index 00000000..b8d65e39 Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_putchar.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_putstr.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_putstr.d new file mode 100644 index 00000000..ed03fdc0 --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_putstr.d @@ -0,0 +1 @@ +obj/HAL/src/alt_putstr.o: HAL/src/alt_putstr.c diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_putstr.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_putstr.o new file mode 100644 index 00000000..03903265 Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_putstr.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_read.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_read.d new file mode 100644 index 00000000..a06cf466 --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_read.d @@ -0,0 +1,74 @@ +obj/HAL/src/alt_read.o: HAL/src/alt_read.c HAL/inc/sys/alt_errno.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_warning.h HAL/inc/priv/alt_file.h \ + HAL/inc/sys/alt_dev.h system.h linker.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h UCOSII/inc/os/alt_sem.h \ + UCOSII/inc/priv/alt_sem_ucosii.h HAL/inc/includes.h HAL/inc/os_cpu.h \ + HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/priv/alt_legacy_irq.h \ + system.h HAL/inc/nios2.h HAL/inc/sys/alt_irq.h UCOSII/inc/os_cfg.h \ + HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_alarm.h system.h UCOSII/inc/ucos_ii.h \ + UCOSII/inc/os_cfg.h HAL/inc/os_cpu.h HAL/inc/alt_types.h \ + HAL/inc/os/alt_syscall.h + +HAL/inc/sys/alt_errno.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_warning.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +UCOSII/inc/os/alt_sem.h: + +UCOSII/inc/priv/alt_sem_ucosii.h: + +HAL/inc/includes.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/sys/alt_irq.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +system.h: + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/os_cpu.h: + +HAL/inc/alt_types.h: + +HAL/inc/os/alt_syscall.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_read.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_read.o new file mode 100644 index 00000000..f51939fe Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_read.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_release_fd.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_release_fd.d new file mode 100644 index 00000000..adb3c578 --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_release_fd.d @@ -0,0 +1,69 @@ +obj/HAL/src/alt_release_fd.o: HAL/src/alt_release_fd.c \ + HAL/inc/sys/alt_dev.h system.h linker.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/priv/alt_dev_llist.h \ + HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h HAL/inc/priv/alt_file.h \ + HAL/inc/sys/alt_dev.h UCOSII/inc/os/alt_sem.h \ + UCOSII/inc/priv/alt_sem_ucosii.h HAL/inc/includes.h HAL/inc/os_cpu.h \ + HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/priv/alt_legacy_irq.h \ + system.h HAL/inc/nios2.h HAL/inc/sys/alt_irq.h UCOSII/inc/os_cfg.h \ + HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_alarm.h system.h UCOSII/inc/ucos_ii.h \ + UCOSII/inc/os_cfg.h HAL/inc/os_cpu.h HAL/inc/alt_types.h + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +UCOSII/inc/os/alt_sem.h: + +UCOSII/inc/priv/alt_sem_ucosii.h: + +HAL/inc/includes.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/sys/alt_irq.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +system.h: + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/os_cpu.h: + +HAL/inc/alt_types.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_release_fd.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_release_fd.o new file mode 100644 index 00000000..402edc0f Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_release_fd.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_remap_cached.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_remap_cached.d new file mode 100644 index 00000000..b5fb1513 --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_remap_cached.d @@ -0,0 +1,10 @@ +obj/HAL/src/alt_remap_cached.o: HAL/src/alt_remap_cached.c \ + HAL/inc/sys/alt_cache.h HAL/inc/alt_types.h system.h linker.h + +HAL/inc/sys/alt_cache.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_remap_cached.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_remap_cached.o new file mode 100644 index 00000000..b3494abb Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_remap_cached.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_remap_uncached.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_remap_uncached.d new file mode 100644 index 00000000..04234057 --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_remap_uncached.d @@ -0,0 +1,10 @@ +obj/HAL/src/alt_remap_uncached.o: HAL/src/alt_remap_uncached.c \ + HAL/inc/sys/alt_cache.h HAL/inc/alt_types.h system.h linker.h + +HAL/inc/sys/alt_cache.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_remap_uncached.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_remap_uncached.o new file mode 100644 index 00000000..33a3c610 Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_remap_uncached.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_rename.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_rename.d new file mode 100644 index 00000000..b7af4b26 --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_rename.d @@ -0,0 +1,10 @@ +obj/HAL/src/alt_rename.o: HAL/src/alt_rename.c HAL/inc/sys/alt_errno.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_warning.h HAL/inc/os/alt_syscall.h + +HAL/inc/sys/alt_errno.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_warning.h: + +HAL/inc/os/alt_syscall.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_rename.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_rename.o new file mode 100644 index 00000000..fa679923 Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_rename.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_sbrk.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_sbrk.d new file mode 100644 index 00000000..23a1342d --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_sbrk.d @@ -0,0 +1,31 @@ +obj/HAL/src/alt_sbrk.o: HAL/src/alt_sbrk.c HAL/inc/os/alt_syscall.h \ + HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/alt_types.h system.h \ + linker.h HAL/inc/priv/alt_legacy_irq.h system.h HAL/inc/nios2.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_irq.h HAL/inc/sys/alt_stack.h \ + system.h + +HAL/inc/os/alt_syscall.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/sys/alt_stack.h: + +system.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_sbrk.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_sbrk.o new file mode 100644 index 00000000..e0683acb Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_sbrk.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_settod.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_settod.d new file mode 100644 index 00000000..56718d55 --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_settod.d @@ -0,0 +1,17 @@ +obj/HAL/src/alt_settod.o: HAL/src/alt_settod.c HAL/inc/sys/alt_errno.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_alarm.h HAL/inc/alt_types.h HAL/inc/os/alt_syscall.h + +HAL/inc/sys/alt_errno.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +HAL/inc/alt_types.h: + +HAL/inc/os/alt_syscall.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_settod.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_settod.o new file mode 100644 index 00000000..ea6cc06c Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_settod.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_software_exception.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_software_exception.d new file mode 100644 index 00000000..fab40238 --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_software_exception.d @@ -0,0 +1,6 @@ +obj/HAL/src/alt_software_exception.o: HAL/src/alt_software_exception.S \ + system.h linker.h + +system.h: + +linker.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_software_exception.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_software_exception.o new file mode 100644 index 00000000..f9e01c24 Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_software_exception.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_stat.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_stat.d new file mode 100644 index 00000000..8a63c276 --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_stat.d @@ -0,0 +1,3 @@ +obj/HAL/src/alt_stat.o: HAL/src/alt_stat.c HAL/inc/os/alt_syscall.h + +HAL/inc/os/alt_syscall.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_stat.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_stat.o new file mode 100644 index 00000000..0033b84d Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_stat.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_tick.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_tick.d new file mode 100644 index 00000000..8bdf3df0 --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_tick.d @@ -0,0 +1,57 @@ +obj/HAL/src/alt_tick.o: HAL/src/alt_tick.c HAL/inc/sys/alt_irq.h \ + HAL/inc/nios2.h HAL/inc/alt_types.h system.h linker.h \ + HAL/inc/priv/alt_legacy_irq.h system.h HAL/inc/nios2.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_irq.h HAL/inc/sys/alt_alarm.h \ + HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \ + UCOSII/inc/os/alt_hooks.h HAL/inc/includes.h HAL/inc/os_cpu.h \ + HAL/inc/sys/alt_irq.h UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h \ + system.h UCOSII/inc/ucos_ii.h UCOSII/inc/os_cfg.h HAL/inc/os_cpu.h \ + HAL/inc/alt_types.h + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +UCOSII/inc/os/alt_hooks.h: + +HAL/inc/includes.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +system.h: + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/os_cpu.h: + +HAL/inc/alt_types.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_tick.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_tick.o new file mode 100644 index 00000000..32629c4a Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_tick.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_times.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_times.d new file mode 100644 index 00000000..4bad83d4 --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_times.d @@ -0,0 +1,17 @@ +obj/HAL/src/alt_times.o: HAL/src/alt_times.c HAL/inc/sys/alt_errno.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_alarm.h HAL/inc/alt_types.h HAL/inc/os/alt_syscall.h + +HAL/inc/sys/alt_errno.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +HAL/inc/alt_types.h: + +HAL/inc/os/alt_syscall.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_times.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_times.o new file mode 100644 index 00000000..0771677b Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_times.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_uncached_free.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_uncached_free.d new file mode 100644 index 00000000..d74ef4b9 --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_uncached_free.d @@ -0,0 +1,10 @@ +obj/HAL/src/alt_uncached_free.o: HAL/src/alt_uncached_free.c \ + HAL/inc/sys/alt_cache.h HAL/inc/alt_types.h system.h linker.h + +HAL/inc/sys/alt_cache.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_uncached_free.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_uncached_free.o new file mode 100644 index 00000000..353f720c Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_uncached_free.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_uncached_malloc.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_uncached_malloc.d new file mode 100644 index 00000000..16799fba --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_uncached_malloc.d @@ -0,0 +1,10 @@ +obj/HAL/src/alt_uncached_malloc.o: HAL/src/alt_uncached_malloc.c \ + HAL/inc/sys/alt_cache.h HAL/inc/alt_types.h system.h linker.h + +HAL/inc/sys/alt_cache.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_uncached_malloc.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_uncached_malloc.o new file mode 100644 index 00000000..5d7e8776 Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_uncached_malloc.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_unlink.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_unlink.d new file mode 100644 index 00000000..0205f86c --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_unlink.d @@ -0,0 +1,10 @@ +obj/HAL/src/alt_unlink.o: HAL/src/alt_unlink.c HAL/inc/sys/alt_errno.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_warning.h HAL/inc/os/alt_syscall.h + +HAL/inc/sys/alt_errno.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_warning.h: + +HAL/inc/os/alt_syscall.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_unlink.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_unlink.o new file mode 100644 index 00000000..411fc9ac Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_unlink.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_usleep.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_usleep.d new file mode 100644 index 00000000..e7846b46 --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_usleep.d @@ -0,0 +1,50 @@ +obj/HAL/src/alt_usleep.o: HAL/src/alt_usleep.c system.h linker.h \ + HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \ + HAL/inc/priv/alt_alarm.h HAL/inc/alt_types.h \ + HAL/inc/priv/alt_busy_sleep.h HAL/inc/os/alt_syscall.h \ + HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \ + HAL/inc/nios2.h HAL/inc/priv/alt_legacy_irq.h HAL/inc/nios2.h \ + HAL/inc/sys/alt_irq.h UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h \ + UCOSII/inc/ucos_ii.h UCOSII/inc/os_cfg.h HAL/inc/os_cpu.h + +system.h: + +linker.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_alarm.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_busy_sleep.h: + +HAL/inc/os/alt_syscall.h: + +HAL/inc/includes.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/priv/alt_legacy_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/sys/alt_irq.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/os_cpu.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_usleep.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_usleep.o new file mode 100644 index 00000000..6eb63edb Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_usleep.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_wait.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_wait.d new file mode 100644 index 00000000..f47f5df1 --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_wait.d @@ -0,0 +1,8 @@ +obj/HAL/src/alt_wait.o: HAL/src/alt_wait.c HAL/inc/sys/alt_errno.h \ + HAL/inc/alt_types.h HAL/inc/os/alt_syscall.h + +HAL/inc/sys/alt_errno.h: + +HAL/inc/alt_types.h: + +HAL/inc/os/alt_syscall.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_wait.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_wait.o new file mode 100644 index 00000000..8cd11654 Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_wait.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_write.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_write.d new file mode 100644 index 00000000..30d74a77 --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_write.d @@ -0,0 +1,78 @@ +obj/HAL/src/alt_write.o: HAL/src/alt_write.c HAL/inc/sys/alt_errno.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_warning.h HAL/inc/priv/alt_file.h \ + HAL/inc/sys/alt_dev.h system.h linker.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h UCOSII/inc/os/alt_sem.h \ + UCOSII/inc/priv/alt_sem_ucosii.h HAL/inc/includes.h HAL/inc/os_cpu.h \ + HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/priv/alt_legacy_irq.h \ + system.h HAL/inc/nios2.h HAL/inc/sys/alt_irq.h UCOSII/inc/os_cfg.h \ + HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_alarm.h system.h UCOSII/inc/ucos_ii.h \ + UCOSII/inc/os_cfg.h HAL/inc/os_cpu.h HAL/inc/alt_types.h \ + HAL/inc/os/alt_syscall.h HAL/inc/sys/alt_log_printf.h system.h + +HAL/inc/sys/alt_errno.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_warning.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +UCOSII/inc/os/alt_sem.h: + +UCOSII/inc/priv/alt_sem_ucosii.h: + +HAL/inc/includes.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/sys/alt_irq.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +system.h: + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/os_cpu.h: + +HAL/inc/alt_types.h: + +HAL/inc/os/alt_syscall.h: + +HAL/inc/sys/alt_log_printf.h: + +system.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_write.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_write.o new file mode 100644 index 00000000..6a7f93c2 Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/alt_write.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/altera_nios2_qsys_irq.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/altera_nios2_qsys_irq.d new file mode 100644 index 00000000..4c73383c --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/altera_nios2_qsys_irq.d @@ -0,0 +1,27 @@ +obj/HAL/src/altera_nios2_qsys_irq.o: HAL/src/altera_nios2_qsys_irq.c \ + HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/alt_types.h system.h \ + linker.h HAL/inc/priv/alt_legacy_irq.h system.h HAL/inc/nios2.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_irq.h \ + HAL/inc/altera_nios2_qsys_irq.h + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/altera_nios2_qsys_irq.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/altera_nios2_qsys_irq.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/altera_nios2_qsys_irq.o new file mode 100644 index 00000000..4d8b8cee Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/altera_nios2_qsys_irq.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/crt0.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/crt0.d new file mode 100644 index 00000000..3af0bb0c --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/crt0.d @@ -0,0 +1,12 @@ +obj/HAL/src/crt0.o: HAL/src/crt0.S system.h linker.h HAL/inc/nios2.h \ + HAL/inc/sys/alt_log_printf.h system.h + +system.h: + +linker.h: + +HAL/inc/nios2.h: + +HAL/inc/sys/alt_log_printf.h: + +system.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/crt0.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/crt0.o new file mode 100644 index 00000000..e7c01426 Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/crt0.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/os_cpu_a.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/os_cpu_a.d new file mode 100644 index 00000000..1c0caef5 --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/os_cpu_a.d @@ -0,0 +1,8 @@ +obj/HAL/src/os_cpu_a.o: HAL/src/os_cpu_a.S UCOSII/inc/os_cfg.h system.h \ + linker.h + +UCOSII/inc/os_cfg.h: + +system.h: + +linker.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/os_cpu_a.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/os_cpu_a.o new file mode 100644 index 00000000..aeb05fcc Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/os_cpu_a.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/os_cpu_c.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/os_cpu_c.d new file mode 100644 index 00000000..a7c2e588 --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/os_cpu_c.d @@ -0,0 +1,49 @@ +obj/HAL/src/os_cpu_c.o: HAL/src/os_cpu_c.c HAL/inc/includes.h \ + HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h HAL/inc/nios2.h \ + HAL/inc/alt_types.h system.h linker.h HAL/inc/priv/alt_legacy_irq.h \ + system.h HAL/inc/nios2.h HAL/inc/alt_types.h HAL/inc/sys/alt_irq.h \ + UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_alarm.h system.h UCOSII/inc/ucos_ii.h \ + UCOSII/inc/os_cfg.h HAL/inc/os_cpu.h system.h + +HAL/inc/includes.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_irq.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +system.h: + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/os_cpu.h: + +system.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/os_cpu_c.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/os_cpu_c.o new file mode 100644 index 00000000..156fae45 Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/HAL/src/os_cpu_c.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/UCOSII/src/alt_env_lock.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/UCOSII/src/alt_env_lock.d new file mode 100644 index 00000000..b7aff0d6 --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/UCOSII/src/alt_env_lock.d @@ -0,0 +1,50 @@ +obj/UCOSII/src/alt_env_lock.o: UCOSII/src/alt_env_lock.c \ + HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \ + HAL/inc/nios2.h HAL/inc/alt_types.h system.h linker.h \ + HAL/inc/priv/alt_legacy_irq.h system.h HAL/inc/nios2.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_irq.h UCOSII/inc/os_cfg.h \ + HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_alarm.h system.h UCOSII/inc/ucos_ii.h \ + UCOSII/inc/os_cfg.h HAL/inc/os_cpu.h system.h + +HAL/inc/includes.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_irq.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +system.h: + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/os_cpu.h: + +system.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/UCOSII/src/alt_env_lock.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/UCOSII/src/alt_env_lock.o new file mode 100644 index 00000000..db31f2dc Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/UCOSII/src/alt_env_lock.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/UCOSII/src/alt_malloc_lock.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/UCOSII/src/alt_malloc_lock.d new file mode 100644 index 00000000..bcc90128 --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/UCOSII/src/alt_malloc_lock.d @@ -0,0 +1,50 @@ +obj/UCOSII/src/alt_malloc_lock.o: UCOSII/src/alt_malloc_lock.c system.h \ + linker.h HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \ + HAL/inc/nios2.h HAL/inc/alt_types.h system.h \ + HAL/inc/priv/alt_legacy_irq.h system.h HAL/inc/nios2.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_irq.h UCOSII/inc/os_cfg.h \ + HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_alarm.h system.h UCOSII/inc/ucos_ii.h \ + UCOSII/inc/os_cfg.h HAL/inc/os_cpu.h + +system.h: + +linker.h: + +HAL/inc/includes.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +system.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_irq.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +system.h: + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/os_cpu.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/UCOSII/src/alt_malloc_lock.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/UCOSII/src/alt_malloc_lock.o new file mode 100644 index 00000000..2ce1cc0f Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/UCOSII/src/alt_malloc_lock.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/UCOSII/src/os_core.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/UCOSII/src/os_core.d new file mode 100644 index 00000000..189739ee --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/UCOSII/src/os_core.d @@ -0,0 +1,40 @@ +obj/UCOSII/src/os_core.o: UCOSII/src/os_core.c UCOSII/inc/ucos_ii.h \ + UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/priv/alt_alarm.h HAL/inc/alt_types.h \ + system.h linker.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \ + HAL/inc/nios2.h system.h HAL/inc/priv/alt_legacy_irq.h system.h \ + HAL/inc/nios2.h HAL/inc/sys/alt_irq.h + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_alarm.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +system.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/sys/alt_irq.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/UCOSII/src/os_core.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/UCOSII/src/os_core.o new file mode 100644 index 00000000..ec317ffc Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/UCOSII/src/os_core.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/UCOSII/src/os_dbg.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/UCOSII/src/os_dbg.d new file mode 100644 index 00000000..3735d257 --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/UCOSII/src/os_dbg.d @@ -0,0 +1,40 @@ +obj/UCOSII/src/os_dbg.o: UCOSII/src/os_dbg.c UCOSII/inc/ucos_ii.h \ + UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/priv/alt_alarm.h HAL/inc/alt_types.h \ + system.h linker.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \ + HAL/inc/nios2.h system.h HAL/inc/priv/alt_legacy_irq.h system.h \ + HAL/inc/nios2.h HAL/inc/sys/alt_irq.h + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_alarm.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +system.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/sys/alt_irq.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/UCOSII/src/os_dbg.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/UCOSII/src/os_dbg.o new file mode 100644 index 00000000..19276a05 Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/UCOSII/src/os_dbg.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/UCOSII/src/os_flag.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/UCOSII/src/os_flag.d new file mode 100644 index 00000000..f3072713 --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/UCOSII/src/os_flag.d @@ -0,0 +1,40 @@ +obj/UCOSII/src/os_flag.o: UCOSII/src/os_flag.c UCOSII/inc/ucos_ii.h \ + UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/priv/alt_alarm.h HAL/inc/alt_types.h \ + system.h linker.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \ + HAL/inc/nios2.h system.h HAL/inc/priv/alt_legacy_irq.h system.h \ + HAL/inc/nios2.h HAL/inc/sys/alt_irq.h + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_alarm.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +system.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/sys/alt_irq.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/UCOSII/src/os_flag.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/UCOSII/src/os_flag.o new file mode 100644 index 00000000..88721e21 Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/UCOSII/src/os_flag.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/UCOSII/src/os_mbox.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/UCOSII/src/os_mbox.d new file mode 100644 index 00000000..2cbf19c5 --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/UCOSII/src/os_mbox.d @@ -0,0 +1,40 @@ +obj/UCOSII/src/os_mbox.o: UCOSII/src/os_mbox.c UCOSII/inc/ucos_ii.h \ + UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/priv/alt_alarm.h HAL/inc/alt_types.h \ + system.h linker.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \ + HAL/inc/nios2.h system.h HAL/inc/priv/alt_legacy_irq.h system.h \ + HAL/inc/nios2.h HAL/inc/sys/alt_irq.h + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_alarm.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +system.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/sys/alt_irq.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/UCOSII/src/os_mbox.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/UCOSII/src/os_mbox.o new file mode 100644 index 00000000..60f0f88d Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/UCOSII/src/os_mbox.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/UCOSII/src/os_mem.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/UCOSII/src/os_mem.d new file mode 100644 index 00000000..33c65518 --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/UCOSII/src/os_mem.d @@ -0,0 +1,40 @@ +obj/UCOSII/src/os_mem.o: UCOSII/src/os_mem.c UCOSII/inc/ucos_ii.h \ + UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/priv/alt_alarm.h HAL/inc/alt_types.h \ + system.h linker.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \ + HAL/inc/nios2.h system.h HAL/inc/priv/alt_legacy_irq.h system.h \ + HAL/inc/nios2.h HAL/inc/sys/alt_irq.h + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_alarm.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +system.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/sys/alt_irq.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/UCOSII/src/os_mem.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/UCOSII/src/os_mem.o new file mode 100644 index 00000000..0af26e27 Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/UCOSII/src/os_mem.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/UCOSII/src/os_mutex.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/UCOSII/src/os_mutex.d new file mode 100644 index 00000000..866feaa2 --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/UCOSII/src/os_mutex.d @@ -0,0 +1,40 @@ +obj/UCOSII/src/os_mutex.o: UCOSII/src/os_mutex.c UCOSII/inc/ucos_ii.h \ + UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/priv/alt_alarm.h HAL/inc/alt_types.h \ + system.h linker.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \ + HAL/inc/nios2.h system.h HAL/inc/priv/alt_legacy_irq.h system.h \ + HAL/inc/nios2.h HAL/inc/sys/alt_irq.h + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_alarm.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +system.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/sys/alt_irq.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/UCOSII/src/os_mutex.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/UCOSII/src/os_mutex.o new file mode 100644 index 00000000..0e57cdca Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/UCOSII/src/os_mutex.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/UCOSII/src/os_q.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/UCOSII/src/os_q.d new file mode 100644 index 00000000..757ceb45 --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/UCOSII/src/os_q.d @@ -0,0 +1,40 @@ +obj/UCOSII/src/os_q.o: UCOSII/src/os_q.c UCOSII/inc/ucos_ii.h \ + UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/priv/alt_alarm.h HAL/inc/alt_types.h \ + system.h linker.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \ + HAL/inc/nios2.h system.h HAL/inc/priv/alt_legacy_irq.h system.h \ + HAL/inc/nios2.h HAL/inc/sys/alt_irq.h + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_alarm.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +system.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/sys/alt_irq.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/UCOSII/src/os_q.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/UCOSII/src/os_q.o new file mode 100644 index 00000000..aa855752 Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/UCOSII/src/os_q.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/UCOSII/src/os_sem.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/UCOSII/src/os_sem.d new file mode 100644 index 00000000..90aeefff --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/UCOSII/src/os_sem.d @@ -0,0 +1,40 @@ +obj/UCOSII/src/os_sem.o: UCOSII/src/os_sem.c UCOSII/inc/ucos_ii.h \ + UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/priv/alt_alarm.h HAL/inc/alt_types.h \ + system.h linker.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \ + HAL/inc/nios2.h system.h HAL/inc/priv/alt_legacy_irq.h system.h \ + HAL/inc/nios2.h HAL/inc/sys/alt_irq.h + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_alarm.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +system.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/sys/alt_irq.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/UCOSII/src/os_sem.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/UCOSII/src/os_sem.o new file mode 100644 index 00000000..23c87649 Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/UCOSII/src/os_sem.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/UCOSII/src/os_task.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/UCOSII/src/os_task.d new file mode 100644 index 00000000..046981a2 --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/UCOSII/src/os_task.d @@ -0,0 +1,40 @@ +obj/UCOSII/src/os_task.o: UCOSII/src/os_task.c UCOSII/inc/ucos_ii.h \ + UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/priv/alt_alarm.h HAL/inc/alt_types.h \ + system.h linker.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \ + HAL/inc/nios2.h system.h HAL/inc/priv/alt_legacy_irq.h system.h \ + HAL/inc/nios2.h HAL/inc/sys/alt_irq.h + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_alarm.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +system.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/sys/alt_irq.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/UCOSII/src/os_task.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/UCOSII/src/os_task.o new file mode 100644 index 00000000..3af950f2 Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/UCOSII/src/os_task.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/UCOSII/src/os_time.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/UCOSII/src/os_time.d new file mode 100644 index 00000000..fba03554 --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/UCOSII/src/os_time.d @@ -0,0 +1,40 @@ +obj/UCOSII/src/os_time.o: UCOSII/src/os_time.c UCOSII/inc/ucos_ii.h \ + UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/priv/alt_alarm.h HAL/inc/alt_types.h \ + system.h linker.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \ + HAL/inc/nios2.h system.h HAL/inc/priv/alt_legacy_irq.h system.h \ + HAL/inc/nios2.h HAL/inc/sys/alt_irq.h + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_alarm.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +system.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/sys/alt_irq.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/UCOSII/src/os_time.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/UCOSII/src/os_time.o new file mode 100644 index 00000000..786ea4a6 Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/UCOSII/src/os_time.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/UCOSII/src/os_tmr.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/UCOSII/src/os_tmr.d new file mode 100644 index 00000000..222d4c34 --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/UCOSII/src/os_tmr.d @@ -0,0 +1,40 @@ +obj/UCOSII/src/os_tmr.o: UCOSII/src/os_tmr.c UCOSII/inc/ucos_ii.h \ + UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/priv/alt_alarm.h HAL/inc/alt_types.h \ + system.h linker.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \ + HAL/inc/nios2.h system.h HAL/inc/priv/alt_legacy_irq.h system.h \ + HAL/inc/nios2.h HAL/inc/sys/alt_irq.h + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_alarm.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +system.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/sys/alt_irq.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/UCOSII/src/os_tmr.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/UCOSII/src/os_tmr.o new file mode 100644 index 00000000..5f4f338c Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/UCOSII/src/os_tmr.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/alt_sys_init.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/alt_sys_init.d new file mode 100644 index 00000000..744324d5 --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/alt_sys_init.d @@ -0,0 +1,113 @@ +obj/alt_sys_init.o: alt_sys_init.c system.h linker.h \ + HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/alt_types.h system.h \ + HAL/inc/priv/alt_legacy_irq.h system.h HAL/inc/nios2.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_irq.h HAL/inc/sys/alt_sys_init.h \ + HAL/inc/altera_nios2_qsys_irq.h drivers/inc/altera_avalon_jtag_uart.h \ + HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_alarm.h HAL/inc/sys/alt_warning.h \ + UCOSII/inc/os/alt_sem.h UCOSII/inc/priv/alt_sem_ucosii.h \ + HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \ + UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h system.h \ + UCOSII/inc/ucos_ii.h UCOSII/inc/os_cfg.h HAL/inc/os_cpu.h \ + HAL/inc/alt_types.h UCOSII/inc/os/alt_flag.h \ + UCOSII/inc/priv/alt_flag_ucosii.h \ + drivers/inc/altera_avalon_jtag_uart_fd.h HAL/inc/sys/alt_dev.h \ + HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_dev_llist.h \ + HAL/inc/sys/alt_llist.h drivers/inc/altera_avalon_sysid_qsys.h \ + HAL/inc/alt_types.h drivers/inc/altera_avalon_timer.h \ + drivers/inc/altera_avalon_uart.h HAL/inc/sys/termios.h \ + drivers/inc/altera_avalon_uart_fd.h \ + drivers/inc/altera_up_avalon_rs232.h HAL/inc/alt_types.h \ + HAL/inc/sys/alt_dev.h + +system.h: + +linker.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +system.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/sys/alt_sys_init.h: + +HAL/inc/altera_nios2_qsys_irq.h: + +drivers/inc/altera_avalon_jtag_uart.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +HAL/inc/sys/alt_warning.h: + +UCOSII/inc/os/alt_sem.h: + +UCOSII/inc/priv/alt_sem_ucosii.h: + +HAL/inc/includes.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +system.h: + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/os_cpu.h: + +HAL/inc/alt_types.h: + +UCOSII/inc/os/alt_flag.h: + +UCOSII/inc/priv/alt_flag_ucosii.h: + +drivers/inc/altera_avalon_jtag_uart_fd.h: + +HAL/inc/sys/alt_dev.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +drivers/inc/altera_avalon_sysid_qsys.h: + +HAL/inc/alt_types.h: + +drivers/inc/altera_avalon_timer.h: + +drivers/inc/altera_avalon_uart.h: + +HAL/inc/sys/termios.h: + +drivers/inc/altera_avalon_uart_fd.h: + +drivers/inc/altera_up_avalon_rs232.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_dev.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/alt_sys_init.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/alt_sys_init.o new file mode 100644 index 00000000..7e2eb612 Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/alt_sys_init.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/drivers/src/altera_avalon_jtag_uart_fd.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/drivers/src/altera_avalon_jtag_uart_fd.d new file mode 100644 index 00000000..d4994f53 --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/drivers/src/altera_avalon_jtag_uart_fd.d @@ -0,0 +1,85 @@ +obj/drivers/src/altera_avalon_jtag_uart_fd.o: \ + drivers/src/altera_avalon_jtag_uart_fd.c HAL/inc/alt_types.h \ + HAL/inc/sys/alt_dev.h system.h linker.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/priv/alt_dev_llist.h \ + HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \ + drivers/inc/altera_avalon_jtag_uart.h HAL/inc/sys/alt_alarm.h \ + HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \ + HAL/inc/sys/alt_warning.h UCOSII/inc/os/alt_sem.h \ + UCOSII/inc/priv/alt_sem_ucosii.h HAL/inc/includes.h HAL/inc/os_cpu.h \ + HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/priv/alt_legacy_irq.h \ + system.h HAL/inc/nios2.h HAL/inc/sys/alt_irq.h UCOSII/inc/os_cfg.h \ + HAL/inc/sys/alt_alarm.h system.h UCOSII/inc/ucos_ii.h \ + UCOSII/inc/os_cfg.h HAL/inc/os_cpu.h HAL/inc/alt_types.h \ + UCOSII/inc/os/alt_flag.h UCOSII/inc/priv/alt_flag_ucosii.h \ + drivers/inc/altera_avalon_jtag_uart_fd.h HAL/inc/sys/alt_dev.h + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +drivers/inc/altera_avalon_jtag_uart.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +HAL/inc/sys/alt_warning.h: + +UCOSII/inc/os/alt_sem.h: + +UCOSII/inc/priv/alt_sem_ucosii.h: + +HAL/inc/includes.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/sys/alt_irq.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +system.h: + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/os_cpu.h: + +HAL/inc/alt_types.h: + +UCOSII/inc/os/alt_flag.h: + +UCOSII/inc/priv/alt_flag_ucosii.h: + +drivers/inc/altera_avalon_jtag_uart_fd.h: + +HAL/inc/sys/alt_dev.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/drivers/src/altera_avalon_jtag_uart_fd.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/drivers/src/altera_avalon_jtag_uart_fd.o new file mode 100644 index 00000000..4f44a215 Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/drivers/src/altera_avalon_jtag_uart_fd.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/drivers/src/altera_avalon_jtag_uart_init.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/drivers/src/altera_avalon_jtag_uart_init.d new file mode 100644 index 00000000..553359a1 --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/drivers/src/altera_avalon_jtag_uart_init.d @@ -0,0 +1,102 @@ +obj/drivers/src/altera_avalon_jtag_uart_init.o: \ + drivers/src/altera_avalon_jtag_uart_init.c HAL/inc/sys/alt_irq.h \ + HAL/inc/nios2.h HAL/inc/alt_types.h system.h linker.h \ + HAL/inc/priv/alt_legacy_irq.h system.h HAL/inc/nios2.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_irq.h HAL/inc/sys/alt_alarm.h \ + HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h HAL/inc/sys/ioctl.h \ + HAL/inc/alt_types.h drivers/inc/altera_avalon_jtag_uart_regs.h \ + HAL/inc/io.h HAL/inc/alt_types.h drivers/inc/altera_avalon_jtag_uart.h \ + HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_warning.h \ + UCOSII/inc/os/alt_sem.h UCOSII/inc/priv/alt_sem_ucosii.h \ + HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \ + UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h system.h \ + UCOSII/inc/ucos_ii.h UCOSII/inc/os_cfg.h HAL/inc/os_cpu.h \ + HAL/inc/alt_types.h UCOSII/inc/os/alt_flag.h \ + UCOSII/inc/priv/alt_flag_ucosii.h \ + drivers/inc/altera_avalon_jtag_uart_fd.h HAL/inc/sys/alt_dev.h \ + HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_dev_llist.h \ + HAL/inc/sys/alt_llist.h HAL/inc/sys/alt_log_printf.h system.h + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +HAL/inc/sys/ioctl.h: + +HAL/inc/alt_types.h: + +drivers/inc/altera_avalon_jtag_uart_regs.h: + +HAL/inc/io.h: + +HAL/inc/alt_types.h: + +drivers/inc/altera_avalon_jtag_uart.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_warning.h: + +UCOSII/inc/os/alt_sem.h: + +UCOSII/inc/priv/alt_sem_ucosii.h: + +HAL/inc/includes.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +system.h: + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/os_cpu.h: + +HAL/inc/alt_types.h: + +UCOSII/inc/os/alt_flag.h: + +UCOSII/inc/priv/alt_flag_ucosii.h: + +drivers/inc/altera_avalon_jtag_uart_fd.h: + +HAL/inc/sys/alt_dev.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/sys/alt_log_printf.h: + +system.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/drivers/src/altera_avalon_jtag_uart_init.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/drivers/src/altera_avalon_jtag_uart_init.o new file mode 100644 index 00000000..eb9167b1 Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/drivers/src/altera_avalon_jtag_uart_init.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/drivers/src/altera_avalon_jtag_uart_ioctl.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/drivers/src/altera_avalon_jtag_uart_ioctl.d new file mode 100644 index 00000000..b29ef0f6 --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/drivers/src/altera_avalon_jtag_uart_ioctl.d @@ -0,0 +1,96 @@ +obj/drivers/src/altera_avalon_jtag_uart_ioctl.o: \ + drivers/src/altera_avalon_jtag_uart_ioctl.c HAL/inc/sys/ioctl.h \ + HAL/inc/alt_types.h drivers/inc/altera_avalon_jtag_uart_regs.h \ + HAL/inc/io.h HAL/inc/alt_types.h drivers/inc/altera_avalon_jtag_uart.h \ + HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \ + HAL/inc/priv/alt_alarm.h HAL/inc/alt_types.h HAL/inc/sys/alt_warning.h \ + UCOSII/inc/os/alt_sem.h UCOSII/inc/priv/alt_sem_ucosii.h \ + HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \ + HAL/inc/nios2.h system.h linker.h HAL/inc/priv/alt_legacy_irq.h \ + system.h HAL/inc/nios2.h HAL/inc/sys/alt_irq.h UCOSII/inc/os_cfg.h \ + HAL/inc/sys/alt_alarm.h system.h UCOSII/inc/ucos_ii.h \ + UCOSII/inc/os_cfg.h HAL/inc/os_cpu.h HAL/inc/alt_types.h \ + UCOSII/inc/os/alt_flag.h UCOSII/inc/priv/alt_flag_ucosii.h \ + drivers/inc/altera_avalon_jtag_uart_fd.h HAL/inc/sys/alt_dev.h \ + HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_dev_llist.h \ + HAL/inc/sys/alt_llist.h HAL/inc/sys/alt_log_printf.h system.h + +HAL/inc/sys/ioctl.h: + +HAL/inc/alt_types.h: + +drivers/inc/altera_avalon_jtag_uart_regs.h: + +HAL/inc/io.h: + +HAL/inc/alt_types.h: + +drivers/inc/altera_avalon_jtag_uart.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_alarm.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_warning.h: + +UCOSII/inc/os/alt_sem.h: + +UCOSII/inc/priv/alt_sem_ucosii.h: + +HAL/inc/includes.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +system.h: + +linker.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/sys/alt_irq.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +system.h: + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/os_cpu.h: + +HAL/inc/alt_types.h: + +UCOSII/inc/os/alt_flag.h: + +UCOSII/inc/priv/alt_flag_ucosii.h: + +drivers/inc/altera_avalon_jtag_uart_fd.h: + +HAL/inc/sys/alt_dev.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/sys/alt_log_printf.h: + +system.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/drivers/src/altera_avalon_jtag_uart_ioctl.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/drivers/src/altera_avalon_jtag_uart_ioctl.o new file mode 100644 index 00000000..4d649c21 Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/drivers/src/altera_avalon_jtag_uart_ioctl.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/drivers/src/altera_avalon_jtag_uart_read.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/drivers/src/altera_avalon_jtag_uart_read.d new file mode 100644 index 00000000..821f92ac --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/drivers/src/altera_avalon_jtag_uart_read.d @@ -0,0 +1,105 @@ +obj/drivers/src/altera_avalon_jtag_uart_read.o: \ + drivers/src/altera_avalon_jtag_uart_read.c HAL/inc/sys/alt_irq.h \ + HAL/inc/nios2.h HAL/inc/alt_types.h system.h linker.h \ + HAL/inc/priv/alt_legacy_irq.h system.h HAL/inc/nios2.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_irq.h HAL/inc/sys/alt_alarm.h \ + HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h HAL/inc/sys/ioctl.h \ + HAL/inc/alt_types.h drivers/inc/altera_avalon_jtag_uart_regs.h \ + HAL/inc/io.h HAL/inc/alt_types.h drivers/inc/altera_avalon_jtag_uart.h \ + HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_warning.h \ + UCOSII/inc/os/alt_sem.h UCOSII/inc/priv/alt_sem_ucosii.h \ + HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \ + UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h system.h \ + UCOSII/inc/ucos_ii.h UCOSII/inc/os_cfg.h HAL/inc/os_cpu.h \ + HAL/inc/alt_types.h UCOSII/inc/os/alt_flag.h \ + UCOSII/inc/priv/alt_flag_ucosii.h \ + drivers/inc/altera_avalon_jtag_uart_fd.h HAL/inc/sys/alt_dev.h \ + HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_dev_llist.h \ + HAL/inc/sys/alt_llist.h HAL/inc/sys/alt_log_printf.h system.h \ + HAL/inc/includes.h + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +HAL/inc/sys/ioctl.h: + +HAL/inc/alt_types.h: + +drivers/inc/altera_avalon_jtag_uart_regs.h: + +HAL/inc/io.h: + +HAL/inc/alt_types.h: + +drivers/inc/altera_avalon_jtag_uart.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_warning.h: + +UCOSII/inc/os/alt_sem.h: + +UCOSII/inc/priv/alt_sem_ucosii.h: + +HAL/inc/includes.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +system.h: + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/os_cpu.h: + +HAL/inc/alt_types.h: + +UCOSII/inc/os/alt_flag.h: + +UCOSII/inc/priv/alt_flag_ucosii.h: + +drivers/inc/altera_avalon_jtag_uart_fd.h: + +HAL/inc/sys/alt_dev.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/sys/alt_log_printf.h: + +system.h: + +HAL/inc/includes.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/drivers/src/altera_avalon_jtag_uart_read.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/drivers/src/altera_avalon_jtag_uart_read.o new file mode 100644 index 00000000..e3881b8d Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/drivers/src/altera_avalon_jtag_uart_read.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/drivers/src/altera_avalon_jtag_uart_write.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/drivers/src/altera_avalon_jtag_uart_write.d new file mode 100644 index 00000000..626796a4 --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/drivers/src/altera_avalon_jtag_uart_write.d @@ -0,0 +1,105 @@ +obj/drivers/src/altera_avalon_jtag_uart_write.o: \ + drivers/src/altera_avalon_jtag_uart_write.c HAL/inc/sys/alt_irq.h \ + HAL/inc/nios2.h HAL/inc/alt_types.h system.h linker.h \ + HAL/inc/priv/alt_legacy_irq.h system.h HAL/inc/nios2.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_irq.h HAL/inc/sys/alt_alarm.h \ + HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h HAL/inc/sys/ioctl.h \ + HAL/inc/alt_types.h drivers/inc/altera_avalon_jtag_uart_regs.h \ + HAL/inc/io.h HAL/inc/alt_types.h drivers/inc/altera_avalon_jtag_uart.h \ + HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_warning.h \ + UCOSII/inc/os/alt_sem.h UCOSII/inc/priv/alt_sem_ucosii.h \ + HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \ + UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h system.h \ + UCOSII/inc/ucos_ii.h UCOSII/inc/os_cfg.h HAL/inc/os_cpu.h \ + HAL/inc/alt_types.h UCOSII/inc/os/alt_flag.h \ + UCOSII/inc/priv/alt_flag_ucosii.h \ + drivers/inc/altera_avalon_jtag_uart_fd.h HAL/inc/sys/alt_dev.h \ + HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_dev_llist.h \ + HAL/inc/sys/alt_llist.h HAL/inc/sys/alt_log_printf.h system.h \ + HAL/inc/includes.h + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +HAL/inc/sys/ioctl.h: + +HAL/inc/alt_types.h: + +drivers/inc/altera_avalon_jtag_uart_regs.h: + +HAL/inc/io.h: + +HAL/inc/alt_types.h: + +drivers/inc/altera_avalon_jtag_uart.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_warning.h: + +UCOSII/inc/os/alt_sem.h: + +UCOSII/inc/priv/alt_sem_ucosii.h: + +HAL/inc/includes.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +system.h: + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/os_cpu.h: + +HAL/inc/alt_types.h: + +UCOSII/inc/os/alt_flag.h: + +UCOSII/inc/priv/alt_flag_ucosii.h: + +drivers/inc/altera_avalon_jtag_uart_fd.h: + +HAL/inc/sys/alt_dev.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/sys/alt_log_printf.h: + +system.h: + +HAL/inc/includes.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/drivers/src/altera_avalon_jtag_uart_write.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/drivers/src/altera_avalon_jtag_uart_write.o new file mode 100644 index 00000000..bfa458ee Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/drivers/src/altera_avalon_jtag_uart_write.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/drivers/src/altera_avalon_sysid_qsys.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/drivers/src/altera_avalon_sysid_qsys.d new file mode 100644 index 00000000..b90af16d --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/drivers/src/altera_avalon_sysid_qsys.d @@ -0,0 +1,21 @@ +obj/drivers/src/altera_avalon_sysid_qsys.o: \ + drivers/src/altera_avalon_sysid_qsys.c \ + drivers/inc/altera_avalon_sysid_qsys.h HAL/inc/alt_types.h \ + drivers/inc/altera_avalon_sysid_qsys_regs.h HAL/inc/io.h \ + HAL/inc/alt_types.h HAL/inc/alt_types.h system.h linker.h + +drivers/inc/altera_avalon_sysid_qsys.h: + +HAL/inc/alt_types.h: + +drivers/inc/altera_avalon_sysid_qsys_regs.h: + +HAL/inc/io.h: + +HAL/inc/alt_types.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/drivers/src/altera_avalon_sysid_qsys.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/drivers/src/altera_avalon_sysid_qsys.o new file mode 100644 index 00000000..a7d0e376 Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/drivers/src/altera_avalon_sysid_qsys.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/drivers/src/altera_avalon_timer_sc.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/drivers/src/altera_avalon_timer_sc.d new file mode 100644 index 00000000..12d1d652 --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/drivers/src/altera_avalon_timer_sc.d @@ -0,0 +1,63 @@ +obj/drivers/src/altera_avalon_timer_sc.o: \ + drivers/src/altera_avalon_timer_sc.c HAL/inc/sys/alt_alarm.h \ + HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h HAL/inc/priv/alt_alarm.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_irq.h HAL/inc/nios2.h system.h \ + linker.h HAL/inc/priv/alt_legacy_irq.h system.h HAL/inc/nios2.h \ + HAL/inc/sys/alt_irq.h drivers/inc/altera_avalon_timer.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_dev.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/sys/alt_warning.h drivers/inc/altera_avalon_timer_regs.h \ + HAL/inc/io.h HAL/inc/alt_types.h HAL/inc/alt_types.h \ + HAL/inc/sys/alt_log_printf.h system.h + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_alarm.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +system.h: + +linker.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/sys/alt_irq.h: + +drivers/inc/altera_avalon_timer.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_dev.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/sys/alt_warning.h: + +drivers/inc/altera_avalon_timer_regs.h: + +HAL/inc/io.h: + +HAL/inc/alt_types.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_log_printf.h: + +system.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/drivers/src/altera_avalon_timer_sc.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/drivers/src/altera_avalon_timer_sc.o new file mode 100644 index 00000000..1701280d Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/drivers/src/altera_avalon_timer_sc.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/drivers/src/altera_avalon_timer_ts.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/drivers/src/altera_avalon_timer_ts.d new file mode 100644 index 00000000..444f9465 --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/drivers/src/altera_avalon_timer_ts.d @@ -0,0 +1,46 @@ +obj/drivers/src/altera_avalon_timer_ts.o: \ + drivers/src/altera_avalon_timer_ts.c system.h linker.h \ + HAL/inc/sys/alt_timestamp.h HAL/inc/alt_types.h \ + drivers/inc/altera_avalon_timer.h HAL/inc/alt_types.h \ + HAL/inc/sys/alt_dev.h system.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_warning.h \ + drivers/inc/altera_avalon_timer.h \ + drivers/inc/altera_avalon_timer_regs.h HAL/inc/io.h HAL/inc/alt_types.h \ + HAL/inc/alt_types.h + +system.h: + +linker.h: + +HAL/inc/sys/alt_timestamp.h: + +HAL/inc/alt_types.h: + +drivers/inc/altera_avalon_timer.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_dev.h: + +system.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_warning.h: + +drivers/inc/altera_avalon_timer.h: + +drivers/inc/altera_avalon_timer_regs.h: + +HAL/inc/io.h: + +HAL/inc/alt_types.h: + +HAL/inc/alt_types.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/drivers/src/altera_avalon_timer_ts.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/drivers/src/altera_avalon_timer_ts.o new file mode 100644 index 00000000..02f9f18b Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/drivers/src/altera_avalon_timer_ts.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/drivers/src/altera_avalon_timer_vars.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/drivers/src/altera_avalon_timer_vars.d new file mode 100644 index 00000000..f478e393 --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/drivers/src/altera_avalon_timer_vars.d @@ -0,0 +1,30 @@ +obj/drivers/src/altera_avalon_timer_vars.o: \ + drivers/src/altera_avalon_timer_vars.c drivers/inc/altera_avalon_timer.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_dev.h system.h linker.h \ + HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_warning.h HAL/inc/alt_types.h + +drivers/inc/altera_avalon_timer.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_warning.h: + +HAL/inc/alt_types.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/drivers/src/altera_avalon_timer_vars.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/drivers/src/altera_avalon_timer_vars.o new file mode 100644 index 00000000..75aebf57 Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/drivers/src/altera_avalon_timer_vars.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/drivers/src/altera_avalon_uart_fd.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/drivers/src/altera_avalon_uart_fd.d new file mode 100644 index 00000000..7fb73e8d --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/drivers/src/altera_avalon_uart_fd.d @@ -0,0 +1,88 @@ +obj/drivers/src/altera_avalon_uart_fd.o: \ + drivers/src/altera_avalon_uart_fd.c HAL/inc/alt_types.h \ + HAL/inc/sys/alt_dev.h system.h linker.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/priv/alt_dev_llist.h \ + HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \ + drivers/inc/altera_avalon_uart.h HAL/inc/sys/termios.h \ + HAL/inc/sys/alt_warning.h UCOSII/inc/os/alt_sem.h \ + UCOSII/inc/priv/alt_sem_ucosii.h HAL/inc/includes.h HAL/inc/os_cpu.h \ + HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/priv/alt_legacy_irq.h \ + system.h HAL/inc/nios2.h HAL/inc/sys/alt_irq.h UCOSII/inc/os_cfg.h \ + HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_alarm.h system.h UCOSII/inc/ucos_ii.h \ + UCOSII/inc/os_cfg.h HAL/inc/os_cpu.h HAL/inc/alt_types.h \ + UCOSII/inc/os/alt_flag.h UCOSII/inc/priv/alt_flag_ucosii.h \ + HAL/inc/alt_types.h drivers/inc/altera_avalon_uart_fd.h \ + HAL/inc/sys/alt_dev.h + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +drivers/inc/altera_avalon_uart.h: + +HAL/inc/sys/termios.h: + +HAL/inc/sys/alt_warning.h: + +UCOSII/inc/os/alt_sem.h: + +UCOSII/inc/priv/alt_sem_ucosii.h: + +HAL/inc/includes.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/sys/alt_irq.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +system.h: + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/os_cpu.h: + +HAL/inc/alt_types.h: + +UCOSII/inc/os/alt_flag.h: + +UCOSII/inc/priv/alt_flag_ucosii.h: + +HAL/inc/alt_types.h: + +drivers/inc/altera_avalon_uart_fd.h: + +HAL/inc/sys/alt_dev.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/drivers/src/altera_avalon_uart_fd.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/drivers/src/altera_avalon_uart_fd.o new file mode 100644 index 00000000..c5962b44 Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/drivers/src/altera_avalon_uart_fd.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/drivers/src/altera_avalon_uart_init.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/drivers/src/altera_avalon_uart_init.d new file mode 100644 index 00000000..8e9ad772 --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/drivers/src/altera_avalon_uart_init.d @@ -0,0 +1,99 @@ +obj/drivers/src/altera_avalon_uart_init.o: \ + drivers/src/altera_avalon_uart_init.c HAL/inc/sys/alt_dev.h system.h \ + linker.h HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_irq.h HAL/inc/nios2.h \ + HAL/inc/priv/alt_legacy_irq.h system.h HAL/inc/nios2.h \ + HAL/inc/sys/alt_irq.h HAL/inc/sys/ioctl.h HAL/inc/sys/alt_errno.h \ + drivers/inc/altera_avalon_uart.h HAL/inc/sys/termios.h \ + HAL/inc/sys/alt_warning.h UCOSII/inc/os/alt_sem.h \ + UCOSII/inc/priv/alt_sem_ucosii.h HAL/inc/includes.h HAL/inc/os_cpu.h \ + HAL/inc/sys/alt_irq.h UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h \ + HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h system.h \ + UCOSII/inc/ucos_ii.h UCOSII/inc/os_cfg.h HAL/inc/os_cpu.h \ + HAL/inc/alt_types.h UCOSII/inc/os/alt_flag.h \ + UCOSII/inc/priv/alt_flag_ucosii.h HAL/inc/alt_types.h \ + drivers/inc/altera_avalon_uart_fd.h HAL/inc/sys/alt_dev.h \ + drivers/inc/altera_avalon_uart_regs.h HAL/inc/io.h HAL/inc/alt_types.h + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/sys/ioctl.h: + +HAL/inc/sys/alt_errno.h: + +drivers/inc/altera_avalon_uart.h: + +HAL/inc/sys/termios.h: + +HAL/inc/sys/alt_warning.h: + +UCOSII/inc/os/alt_sem.h: + +UCOSII/inc/priv/alt_sem_ucosii.h: + +HAL/inc/includes.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +system.h: + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/os_cpu.h: + +HAL/inc/alt_types.h: + +UCOSII/inc/os/alt_flag.h: + +UCOSII/inc/priv/alt_flag_ucosii.h: + +HAL/inc/alt_types.h: + +drivers/inc/altera_avalon_uart_fd.h: + +HAL/inc/sys/alt_dev.h: + +drivers/inc/altera_avalon_uart_regs.h: + +HAL/inc/io.h: + +HAL/inc/alt_types.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/drivers/src/altera_avalon_uart_init.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/drivers/src/altera_avalon_uart_init.o new file mode 100644 index 00000000..69b4655a Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/drivers/src/altera_avalon_uart_init.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/drivers/src/altera_avalon_uart_ioctl.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/drivers/src/altera_avalon_uart_ioctl.d new file mode 100644 index 00000000..28a0afbf --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/drivers/src/altera_avalon_uart_ioctl.d @@ -0,0 +1,97 @@ +obj/drivers/src/altera_avalon_uart_ioctl.o: \ + drivers/src/altera_avalon_uart_ioctl.c HAL/inc/sys/alt_irq.h \ + HAL/inc/nios2.h HAL/inc/alt_types.h system.h linker.h \ + HAL/inc/priv/alt_legacy_irq.h system.h HAL/inc/nios2.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_irq.h HAL/inc/sys/ioctl.h \ + HAL/inc/sys/alt_errno.h drivers/inc/altera_avalon_uart_regs.h \ + HAL/inc/io.h HAL/inc/alt_types.h drivers/inc/altera_avalon_uart.h \ + HAL/inc/sys/termios.h HAL/inc/sys/alt_warning.h UCOSII/inc/os/alt_sem.h \ + UCOSII/inc/priv/alt_sem_ucosii.h HAL/inc/includes.h HAL/inc/os_cpu.h \ + HAL/inc/sys/alt_irq.h UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h \ + HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h system.h \ + UCOSII/inc/ucos_ii.h UCOSII/inc/os_cfg.h HAL/inc/os_cpu.h \ + HAL/inc/alt_types.h UCOSII/inc/os/alt_flag.h \ + UCOSII/inc/priv/alt_flag_ucosii.h HAL/inc/alt_types.h \ + drivers/inc/altera_avalon_uart_fd.h HAL/inc/sys/alt_dev.h \ + HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_dev_llist.h \ + HAL/inc/sys/alt_llist.h + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/sys/ioctl.h: + +HAL/inc/sys/alt_errno.h: + +drivers/inc/altera_avalon_uart_regs.h: + +HAL/inc/io.h: + +HAL/inc/alt_types.h: + +drivers/inc/altera_avalon_uart.h: + +HAL/inc/sys/termios.h: + +HAL/inc/sys/alt_warning.h: + +UCOSII/inc/os/alt_sem.h: + +UCOSII/inc/priv/alt_sem_ucosii.h: + +HAL/inc/includes.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +system.h: + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/os_cpu.h: + +HAL/inc/alt_types.h: + +UCOSII/inc/os/alt_flag.h: + +UCOSII/inc/priv/alt_flag_ucosii.h: + +HAL/inc/alt_types.h: + +drivers/inc/altera_avalon_uart_fd.h: + +HAL/inc/sys/alt_dev.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/drivers/src/altera_avalon_uart_ioctl.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/drivers/src/altera_avalon_uart_ioctl.o new file mode 100644 index 00000000..89e05f1c Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/drivers/src/altera_avalon_uart_ioctl.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/drivers/src/altera_avalon_uart_read.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/drivers/src/altera_avalon_uart_read.d new file mode 100644 index 00000000..b7c7f8fc --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/drivers/src/altera_avalon_uart_read.d @@ -0,0 +1,97 @@ +obj/drivers/src/altera_avalon_uart_read.o: \ + drivers/src/altera_avalon_uart_read.c HAL/inc/sys/alt_irq.h \ + HAL/inc/nios2.h HAL/inc/alt_types.h system.h linker.h \ + HAL/inc/priv/alt_legacy_irq.h system.h HAL/inc/nios2.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_irq.h HAL/inc/sys/ioctl.h \ + HAL/inc/sys/alt_errno.h drivers/inc/altera_avalon_uart.h \ + HAL/inc/sys/termios.h HAL/inc/sys/alt_warning.h UCOSII/inc/os/alt_sem.h \ + UCOSII/inc/priv/alt_sem_ucosii.h HAL/inc/includes.h HAL/inc/os_cpu.h \ + HAL/inc/sys/alt_irq.h UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h \ + HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h system.h \ + UCOSII/inc/ucos_ii.h UCOSII/inc/os_cfg.h HAL/inc/os_cpu.h \ + HAL/inc/alt_types.h UCOSII/inc/os/alt_flag.h \ + UCOSII/inc/priv/alt_flag_ucosii.h HAL/inc/alt_types.h \ + drivers/inc/altera_avalon_uart_fd.h HAL/inc/sys/alt_dev.h \ + HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_dev_llist.h \ + HAL/inc/sys/alt_llist.h drivers/inc/altera_avalon_uart_regs.h \ + HAL/inc/io.h HAL/inc/alt_types.h + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/sys/ioctl.h: + +HAL/inc/sys/alt_errno.h: + +drivers/inc/altera_avalon_uart.h: + +HAL/inc/sys/termios.h: + +HAL/inc/sys/alt_warning.h: + +UCOSII/inc/os/alt_sem.h: + +UCOSII/inc/priv/alt_sem_ucosii.h: + +HAL/inc/includes.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +system.h: + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/os_cpu.h: + +HAL/inc/alt_types.h: + +UCOSII/inc/os/alt_flag.h: + +UCOSII/inc/priv/alt_flag_ucosii.h: + +HAL/inc/alt_types.h: + +drivers/inc/altera_avalon_uart_fd.h: + +HAL/inc/sys/alt_dev.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +drivers/inc/altera_avalon_uart_regs.h: + +HAL/inc/io.h: + +HAL/inc/alt_types.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/drivers/src/altera_avalon_uart_read.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/drivers/src/altera_avalon_uart_read.o new file mode 100644 index 00000000..a763f341 Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/drivers/src/altera_avalon_uart_read.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/drivers/src/altera_avalon_uart_write.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/drivers/src/altera_avalon_uart_write.d new file mode 100644 index 00000000..46efd14c --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/drivers/src/altera_avalon_uart_write.d @@ -0,0 +1,99 @@ +obj/drivers/src/altera_avalon_uart_write.o: \ + drivers/src/altera_avalon_uart_write.c HAL/inc/sys/alt_dev.h system.h \ + linker.h HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_irq.h HAL/inc/nios2.h \ + HAL/inc/priv/alt_legacy_irq.h system.h HAL/inc/nios2.h \ + HAL/inc/sys/alt_irq.h HAL/inc/sys/ioctl.h HAL/inc/sys/alt_errno.h \ + drivers/inc/altera_avalon_uart_regs.h HAL/inc/io.h HAL/inc/alt_types.h \ + drivers/inc/altera_avalon_uart.h HAL/inc/sys/termios.h \ + HAL/inc/sys/alt_warning.h UCOSII/inc/os/alt_sem.h \ + UCOSII/inc/priv/alt_sem_ucosii.h HAL/inc/includes.h HAL/inc/os_cpu.h \ + HAL/inc/sys/alt_irq.h UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h \ + HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h system.h \ + UCOSII/inc/ucos_ii.h UCOSII/inc/os_cfg.h HAL/inc/os_cpu.h \ + HAL/inc/alt_types.h UCOSII/inc/os/alt_flag.h \ + UCOSII/inc/priv/alt_flag_ucosii.h HAL/inc/alt_types.h \ + drivers/inc/altera_avalon_uart_fd.h HAL/inc/sys/alt_dev.h + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/sys/ioctl.h: + +HAL/inc/sys/alt_errno.h: + +drivers/inc/altera_avalon_uart_regs.h: + +HAL/inc/io.h: + +HAL/inc/alt_types.h: + +drivers/inc/altera_avalon_uart.h: + +HAL/inc/sys/termios.h: + +HAL/inc/sys/alt_warning.h: + +UCOSII/inc/os/alt_sem.h: + +UCOSII/inc/priv/alt_sem_ucosii.h: + +HAL/inc/includes.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +system.h: + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/os_cpu.h: + +HAL/inc/alt_types.h: + +UCOSII/inc/os/alt_flag.h: + +UCOSII/inc/priv/alt_flag_ucosii.h: + +HAL/inc/alt_types.h: + +drivers/inc/altera_avalon_uart_fd.h: + +HAL/inc/sys/alt_dev.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/drivers/src/altera_avalon_uart_write.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/drivers/src/altera_avalon_uart_write.o new file mode 100644 index 00000000..917861ae Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/drivers/src/altera_avalon_uart_write.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/drivers/src/altera_up_avalon_rs232.d b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/drivers/src/altera_up_avalon_rs232.d new file mode 100644 index 00000000..3f3972bf --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/drivers/src/altera_up_avalon_rs232.d @@ -0,0 +1,82 @@ +obj/drivers/src/altera_up_avalon_rs232.o: \ + drivers/src/altera_up_avalon_rs232.c HAL/inc/priv/alt_file.h \ + HAL/inc/sys/alt_dev.h system.h linker.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/priv/alt_dev_llist.h \ + HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h UCOSII/inc/os/alt_sem.h \ + UCOSII/inc/priv/alt_sem_ucosii.h HAL/inc/includes.h HAL/inc/os_cpu.h \ + HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/priv/alt_legacy_irq.h \ + system.h HAL/inc/nios2.h HAL/inc/sys/alt_irq.h UCOSII/inc/os_cfg.h \ + HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_alarm.h system.h UCOSII/inc/ucos_ii.h \ + UCOSII/inc/os_cfg.h HAL/inc/os_cpu.h HAL/inc/alt_types.h \ + drivers/inc/altera_up_avalon_rs232.h HAL/inc/alt_types.h \ + HAL/inc/sys/alt_dev.h drivers/inc/altera_up_avalon_rs232_regs.h \ + HAL/inc/io.h HAL/inc/alt_types.h + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +UCOSII/inc/os/alt_sem.h: + +UCOSII/inc/priv/alt_sem_ucosii.h: + +HAL/inc/includes.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/sys/alt_irq.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +system.h: + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/os_cpu.h: + +HAL/inc/alt_types.h: + +drivers/inc/altera_up_avalon_rs232.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_dev.h: + +drivers/inc/altera_up_avalon_rs232_regs.h: + +HAL/inc/io.h: + +HAL/inc/alt_types.h: diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/drivers/src/altera_up_avalon_rs232.o b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/drivers/src/altera_up_avalon_rs232.o new file mode 100644 index 00000000..f98d689b Binary files /dev/null and b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/obj/drivers/src/altera_up_avalon_rs232.o differ diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/public.mk b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/public.mk new file mode 100644 index 00000000..b68b630a --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/public.mk @@ -0,0 +1,402 @@ +#------------------------------------------------------------------------------ +# BSP "PUBLIC" MAKEFILE CONTENT +# +# This file is intended to be included in an application or library +# Makefile that is using this BSP. You can create such a Makefile with +# the nios2-app-generate-makefile or nios2-lib-generate-makefile +# commands. +# +# The following variables must be defined before including this file: +# +# ALT_LIBRARY_ROOT_DIR +# Contains the path to the BSP top-level (aka root) directory +#------------------------------------------------------------------------------ + +#------------------------------------------------------------------------------ +# PATHS +#------------------------------------------------------------------------------ + + + +# Path to the provided linker script. +BSP_LINKER_SCRIPT := $(ALT_LIBRARY_ROOT_DIR)/linker.x + +# Include paths: +# The path to root of all header files that a library wishes to make +# available for an application's use is specified here. Note that this +# may not be *all* folders within a hierarchy. For example, if it is +# desired that the application developer type: +# #include +# #include +# With files laid out like this: +# /inc/sockets.h +# /inc/ip/tcpip.h +# +# Then, only /inc need be added to the list of include +# directories. Alternatively, if you wish to be able to directly include +# all files in a hierarchy, separate paths to each folder in that +# hierarchy must be defined. + +# The following are the "base" set of include paths for a BSP. +# These paths are appended to the list that individual software +# components, drivers, etc., add in the generated portion of this +# file (below). +ALT_INCLUDE_DIRS_TO_APPEND += \ + $(ALT_LIBRARY_ROOT_DIR) \ + $(ALT_LIBRARY_ROOT_DIR)/drivers/inc + +# Additions to linker library search-path: +# Here we provide a path to "our self" for the application to construct a +# "-L " out of. This should contain a list of directories, +# relative to the library root, of all directories with .a files to link +# against. +ALT_LIBRARY_DIRS += $(ALT_LIBRARY_ROOT_DIR) + + +#------------------------------------------------------------------------------ +# COMPILATION FLAGS +#------------------------------------------------------------------------------ +# Default C pre-processor flags for a BSP: +ALT_CPPFLAGS += -DSYSTEM_BUS_WIDTH=32 \ + -pipe + + +#------------------------------------------------------------------------------ +# MANAGED CONTENT +# +# All content between the lines "START MANAGED" and "END MANAGED" below is +# generated based on variables in the BSP settings file when the +# nios2-bsp-generate-files command is invoked. If you wish to persist any +# information pertaining to the build process, it is recomended that you +# utilize the BSP settings mechanism to do so. +#------------------------------------------------------------------------------ +#START MANAGED + +# The following TYPE comment allows tools to identify the 'type' of target this +# makefile is associated with. +# TYPE: BSP_PUBLIC_MAKEFILE + +# This following VERSION comment indicates the version of the tool used to +# generate this makefile. A makefile variable is provided for VERSION as well. +# ACDS_VERSION: 12.1sp1 +ACDS_VERSION := 12.1sp1 + +# This following BUILD_NUMBER comment indicates the build number of the tool +# used to generate this makefile. +# BUILD_NUMBER: 243 + +# Quartus Generated JDI File. Required for resolving node instance ID's with +# design component names. +JDI_FILE := C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.jdi + +# Qsys--generated SOPCINFO file. Required for resolving node instance ID's with +# design component names. +SOPCINFO_FILE := C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system.sopcinfo + +# Big-Endian operation. +# setting BIG_ENDIAN is false +ALT_CFLAGS += -EL + +# Path to the provided C language runtime initialization code. +BSP_CRT0 := $(ALT_LIBRARY_ROOT_DIR)/obj/HAL/src/crt0.o + +# Name of BSP library as provided to linker using the "-msys-lib" flag or +# linker script GROUP command. +# setting BSP_SYS_LIB is ucosii_bsp +BSP_SYS_LIB := ucosii_bsp +ELF_PATCH_FLAG += --thread_model ucosii + +# Type identifier of the BSP library +# setting BSP_TYPE is ucosii +ALT_CPPFLAGS += -D__hal__ +BSP_TYPE := ucosii + +# CPU Name +# setting CPU_NAME is cpu +CPU_NAME = cpu +ELF_PATCH_FLAG += --cpu_name $(CPU_NAME) + +# Hardware Divider present. +# setting HARDWARE_DIVIDE is false +ALT_CFLAGS += -mno-hw-div + +# Hardware Multiplier present. +# setting HARDWARE_MULTIPLY is true +ALT_CFLAGS += -mhw-mul + +# Hardware Mulx present. +# setting HARDWARE_MULX is false +ALT_CFLAGS += -mno-hw-mulx + +# Debug Core present. +# setting HAS_DEBUG_CORE is true +CPU_HAS_DEBUG_CORE = 1 + +# Qsys generated design +# setting QSYS is 1 +QSYS := 1 +ELF_PATCH_FLAG += --qsys true + +# Design Name +# setting SOPC_NAME is system +SOPC_NAME := system + +# SopcBuilder Simulation Enabled +# setting SOPC_SIMULATION_ENABLED is false +ELF_PATCH_FLAG += --simulation_enabled false + +# The SOPC System ID +# setting SOPC_SYSID is 0 +SOPC_SYSID_FLAG += --id=0 +ELF_PATCH_FLAG += --id 0 + +# The SOPC System ID Base Address +# setting SOPC_SYSID_BASE_ADDRESS is 0x20010c0 +SOPC_SYSID_FLAG += --sidp=0x20010c0 +ELF_PATCH_FLAG += --sidp 0x20010c0 + +# The SOPC Timestamp +# setting SOPC_TIMESTAMP is 1393886764 +SOPC_SYSID_FLAG += --timestamp=1393886764 +ELF_PATCH_FLAG += --timestamp 1393886764 + +# Small-footprint (polled mode) driver none +# setting altera_avalon_jtag_uart_driver.enable_small_driver is false + +# Enable driver ioctl() support. This feature is not compatible with the +# 'small' driver; ioctl() support will not be compiled if either the UART +# 'enable_small_driver' or HAL 'enable_reduced_device_drivers' settings are +# enabled. none +# setting altera_avalon_uart_driver.enable_ioctl is false + +# Small-footprint (polled mode) driver none +# setting altera_avalon_uart_driver.enable_small_driver is false + +# Build a custom version of newlib with the specified space-separated compiler +# flags. The custom newlib build will be placed in the <bsp root>/newlib +# directory, and will be used only for applications that utilize this BSP. +# setting hal.custom_newlib_flags is none + +# Enable support for a subset of the C++ language. This option increases code +# footprint by adding support for C++ constructors. Certain features, such as +# multiple inheritance and exceptions are not supported. If false, adds +# -DALT_NO_C_PLUS_PLUS to ALT_CPPFLAGS in public.mk, and reduces code +# footprint. none +# setting hal.enable_c_plus_plus is 1 + +# When your application exits, close file descriptors, call C++ destructors, +# etc. Code footprint can be reduced by disabling clean exit. If disabled, adds +# -DALT_NO_CLEAN_EXIT to ALT_CPPFLAGS and -Wl,--defsym, exit=_exit to +# ALT_LDFLAGS in public.mk. none +# setting hal.enable_clean_exit is 1 + +# Add exit() support. This option increases code footprint if your "main()" +# routine does "return" or call "exit()". If false, adds -DALT_NO_EXIT to +# ALT_CPPFLAGS in public.mk, and reduces footprint none +# setting hal.enable_exit is 1 + +# Causes code to be compiled with gprof profiling enabled and the application +# ELF to be linked with the GPROF library. If true, adds -DALT_PROVIDE_GMON to +# ALT_CPPFLAGS and -pg to ALT_CFLAGS in public.mk. none +# setting hal.enable_gprof is 0 + +# Enables lightweight device driver API. This reduces code and data footprint +# by removing the HAL layer that maps device names (e.g. /dev/uart0) to file +# descriptors. Instead, driver routines are called directly. The open(), +# close(), and lseek() routines will always fail if called. The read(), +# write(), fstat(), ioctl(), and isatty() routines only work for the stdio +# devices. If true, adds -DALT_USE_DIRECT_DRIVERS to ALT_CPPFLAGS in public.mk. +# The Altera Host and read-only ZIP file systems can't be used if +# hal.enable_lightweight_device_driver_api is true. +# setting hal.enable_lightweight_device_driver_api is 0 + +# Adds code to emulate multiply and divide instructions in case they are +# executed but aren't present in the CPU. Normally this isn't required because +# the compiler won't use multiply and divide instructions that aren't present +# in the CPU. If false, adds -DALT_NO_INSTRUCTION_EMULATION to ALT_CPPFLAGS in +# public.mk. none +# setting hal.enable_mul_div_emulation is 0 +ALT_CPPFLAGS += -DALT_NO_INSTRUCTION_EMULATION + +# Certain drivers are compiled with reduced functionality to reduce code +# footprint. Not all drivers observe this setting. The altera_avalon_uart and +# altera_avalon_jtag_uart drivers switch from interrupt-driven to polled +# operation. CAUTION: Several device drivers are disabled entirely. These +# include the altera_avalon_cfi_flash, altera_avalon_epcs_flash_controller, and +# altera_avalon_lcd_16207 drivers. This can result in certain API (HAL flash +# access routines) to fail. You can define a symbol provided by each driver to +# prevent it from being removed. If true, adds -DALT_USE_SMALL_DRIVERS to +# ALT_CPPFLAGS in public.mk. none +# setting hal.enable_reduced_device_drivers is 0 + +# Turns on HAL runtime stack checking feature. Enabling this setting causes +# additional code to be placed into each subroutine call to generate an +# exception if a stack collision occurs with the heap or statically allocated +# data. If true, adds -DALT_STACK_CHECK and -mstack-check to ALT_CPPFLAGS in +# public.mk. none +# setting hal.enable_runtime_stack_checking is 0 + +# The BSP is compiled with optimizations to speedup HDL simulation such as +# initializing the cache, clearing the .bss section, and skipping long delay +# loops. If true, adds -DALT_SIM_OPTIMIZE to ALT_CPPFLAGS in public.mk. When +# this setting is true, the BSP shouldn't be used to build applications that +# are expected to run real hardware. +# setting hal.enable_sim_optimize is 0 + +# Causes the small newlib (C library) to be used. This reduces code and data +# footprint at the expense of reduced functionality. Several newlib features +# are removed such as floating-point support in printf(), stdin input routines, +# and buffered I/O. The small C library is not compatible with Micrium +# MicroC/OS-II. If true, adds -msmallc to ALT_LDFLAGS in public.mk. none +# setting hal.enable_small_c_library is 0 + +# Enable SOPC Builder System ID. If a System ID SOPC Builder component is +# connected to the CPU associated with this BSP, it will be enabled in the +# creation of command-line arguments to download an ELF to the target. +# Otherwise, system ID and timestamp values are left out of public.mk for +# application Makefile "download-elf" target definition. With the system ID +# check disabled, the Nios II EDS tools will not automatically ensure that the +# application .elf file (and BSP it is linked against) corresponds to the +# hardware design on the target. If false, adds --accept-bad-sysid to +# SOPC_SYSID_FLAG in public.mk. none +# setting hal.enable_sopc_sysid_check is 1 + +# Enable BSP generation to query if SOPC system is big endian. If true ignores +# export of 'ALT_CFLAGS += -EB' to public.mk if big endian system. If true +# ignores export of 'ALT_CFLAGS += -EL' if little endian system. none +# setting hal.make.ignore_system_derived.big_endian is 0 + +# Enable BSP generation to query if SOPC system has a debug core present. If +# true ignores export of 'CPU_HAS_DEBUG_CORE = 1' to public.mk if a debug core +# is found in the system. If true ignores export of 'CPU_HAS_DEBUG_CORE = 0' if +# no debug core is found in the system. none +# setting hal.make.ignore_system_derived.debug_core_present is 0 + +# Enable BSP generation to query if SOPC system has FPU present. If true +# ignores export of 'ALT_CFLAGS += -mhard-float' to public.mk if FPU is found +# in the system. If true ignores export of 'ALT_CFLAGS += -mhard-soft' if FPU +# is not found in the system. none +# setting hal.make.ignore_system_derived.fpu_present is 0 + +# Enable BSP generation to query if SOPC system has hardware divide present. If +# true ignores export of 'ALT_CFLAGS += -mno-hw-div' to public.mk if no +# division is found in system. If true ignores export of 'ALT_CFLAGS += +# -mhw-div' if division is found in the system. none +# setting hal.make.ignore_system_derived.hardware_divide_present is 0 + +# Enable BSP generation to query if SOPC system floating point custom +# instruction with a divider is present. If true ignores export of 'ALT_CFLAGS +# += -mcustom-fpu-cfg=60-2' and 'ALT_LDFLAGS += -mcustom-fpu-cfg=60-2' to +# public.mk if the custom instruction is found in the system. none +# setting hal.make.ignore_system_derived.hardware_fp_cust_inst_divider_present is 0 + +# Enable BSP generation to query if SOPC system floating point custom +# instruction without a divider is present. If true ignores export of +# 'ALT_CFLAGS += -mcustom-fpu-cfg=60-1' and 'ALT_LDFLAGS += +# -mcustom-fpu-cfg=60-1' to public.mk if the custom instruction is found in the +# system. none +# setting hal.make.ignore_system_derived.hardware_fp_cust_inst_no_divider_present is 0 + +# Enable BSP generation to query if SOPC system has multiplier present. If true +# ignores export of 'ALT_CFLAGS += -mno-hw-mul' to public.mk if no multiplier +# is found in the system. If true ignores export of 'ALT_CFLAGS += -mhw-mul' if +# multiplier is found in the system. none +# setting hal.make.ignore_system_derived.hardware_multiplier_present is 0 + +# Enable BSP generation to query if SOPC system has hardware mulx present. If +# true ignores export of 'ALT_CFLAGS += -mno-hw-mulx' to public.mk if no mulx +# is found in the system. If true ignores export of 'ALT_CFLAGS += -mhw-mulx' +# if mulx is found in the system. none +# setting hal.make.ignore_system_derived.hardware_mulx_present is 0 + +# Enable BSP generation to query if SOPC system has simulation enabled. If true +# ignores export of 'ELF_PATCH_FLAG += --simulation_enabled' to public.mk. none +# setting hal.make.ignore_system_derived.sopc_simulation_enabled is 0 + +# Enable BSP generation to query SOPC system for system ID base address. If +# true ignores export of 'SOPC_SYSID_FLAG += --sidp=
' and +# 'ELF_PATCH_FLAG += --sidp=
' to public.mk. none +# setting hal.make.ignore_system_derived.sopc_system_base_address is 0 + +# Enable BSP generation to query SOPC system for system ID. If true ignores +# export of 'SOPC_SYSID_FLAG += --id=' and 'ELF_PATCH_FLAG += +# --id=' to public.mk. none +# setting hal.make.ignore_system_derived.sopc_system_id is 0 + +# Enable BSP generation to query SOPC system for system timestamp. If true +# ignores export of 'SOPC_SYSID_FLAG += --timestamp=' and +# 'ELF_PATCH_FLAG += --timestamp=' to public.mk. none +# setting hal.make.ignore_system_derived.sopc_system_timestamp is 0 + +# Slave descriptor of STDERR character-mode device. This setting is used by the +# ALT_STDERR family of defines in system.h. none +# setting hal.stderr is jtag_uart_0 +ELF_PATCH_FLAG += --stderr_dev jtag_uart_0 + +# Slave descriptor of STDIN character-mode device. This setting is used by the +# ALT_STDIN family of defines in system.h. none +# setting hal.stdin is jtag_uart_0 +ELF_PATCH_FLAG += --stdin_dev jtag_uart_0 + +# Slave descriptor of STDOUT character-mode device. This setting is used by the +# ALT_STDOUT family of defines in system.h. none +# setting hal.stdout is jtag_uart_0 +ELF_PATCH_FLAG += --stdout_dev jtag_uart_0 + + +#------------------------------------------------------------------------------ +# SOFTWARE COMPONENT & DRIVER INCLUDE PATHS +#------------------------------------------------------------------------------ + +ALT_INCLUDE_DIRS += $(ALT_LIBRARY_ROOT_DIR)/UCOSII/inc +ALT_INCLUDE_DIRS += $(ALT_LIBRARY_ROOT_DIR)/HAL/inc + +#------------------------------------------------------------------------------ +# SOFTWARE COMPONENT & DRIVER PRODUCED ALT_CPPFLAGS ADDITIONS +#------------------------------------------------------------------------------ + +ALT_CPPFLAGS += -D__ucosii__ + +#END MANAGED + + +#------------------------------------------------------------------------------ +# LIBRARY INFORMATION +#------------------------------------------------------------------------------ +# Assemble the name of the BSP *.a file using the BSP library name +# (BSP_SYS_LIB) in generated content above. +BSP_LIB := lib$(BSP_SYS_LIB).a + +# Additional libraries to link against: +# An application including this file will prefix each library with "-l". +# For example, to include the Newlib math library "m" is included, which +# becomes "-lm" when linking the application. +ALT_LIBRARY_NAMES += m + +# Additions to linker dependencies: +# An application Makefile will typically add these directly to the list +# of dependencies required to build the executable target(s). The BSP +# library (*.a) file is specified here. +ALT_LDDEPS += $(ALT_LIBRARY_ROOT_DIR)/$(BSP_LIB) + +# Is this library "Makeable"? +# Add to list of root library directories that support running 'make' +# to build them. Because libraries may or may not have a Makefile in their +# root, appending to this variable tells an application to run 'make' in +# the library root to build/update this library. +MAKEABLE_LIBRARY_ROOT_DIRS += $(ALT_LIBRARY_ROOT_DIR) + +# Additional Assembler Flags +# -gdwarf2 flag is required for stepping through assembly code +ALT_ASFLAGS += -gdwarf2 + +#------------------------------------------------------------------------------ +# FINAL INCLUDE PATH LIST +#------------------------------------------------------------------------------ +# Append static include paths to paths specified by OS/driver/sw package +# additions to the BSP thus giving them precedence in case a BSP addition +# is attempting to override BSP sources. +ALT_INCLUDE_DIRS += $(ALT_INCLUDE_DIRS_TO_APPEND) + + + diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/settings.bsp b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/settings.bsp new file mode 100644 index 00000000..a3535add --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/settings.bsp @@ -0,0 +1,1807 @@ + + + ucosii + default + 3-Mar-2014 4:17:24 PM + 1393888644631 + C:\Users\gongal\NewRepARCap\MCandWifiTestDE0\Software\MCTest_bsp + settings.bsp + C:\Users\gongal\NewRepARCap\MCandWifiTestDE0\system.sopcinfo + default + cpu + 1.9 + + hal.sys_clk_timer + ALT_SYS_CLK + UnquotedString + sys_clk_timer + none + system_h_define + Slave descriptor of the system clock timer device. This device provides a periodic interrupt ("tick") and is typically required for RTOS use. This setting defines the value of ALT_SYS_CLK in system.h. + none + false + common + + + hal.timestamp_timer + ALT_TIMESTAMP_CLK + UnquotedString + none + none + system_h_define + Slave descriptor of timestamp timer device. This device is used by Altera HAL timestamp drivers for high-resolution time measurement. This setting defines the value of ALT_TIMESTAMP_CLK in system.h. + none + false + common + + + hal.max_file_descriptors + ALT_MAX_FD + DecimalNumber + 32 + 32 + system_h_define + Determines the number of file descriptors statically allocated. This setting defines the value of ALT_MAX_FD in system.h. + If hal.enable_lightweight_device_driver_api is true, there are no file descriptors so this setting is ignored. If hal.enable_lightweight_device_driver_api is false, this setting must be at least 4 because HAL needs a file descriptor for /dev/null, /dev/stdin, /dev/stdout, and /dev/stderr. + false + + + + hal.enable_instruction_related_exceptions_api + ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API + BooleanDefineOnly + false + false + system_h_define + Enables API for registering handlers to service instruction-related exceptions. Enabling this setting increases the size of the exception entry code. + These exception types can be generated if various processor options are enabled, such as the MMU, MPU, or other advanced exception types. + false + + + + hal.linker.allow_code_at_reset + ALT_ALLOW_CODE_AT_RESET + Boolean + 1 + 0 + none + Indicates if initialization code is allowed at the reset address. If true, defines the macro ALT_ALLOW_CODE_AT_RESET in linker.h. + If true, defines the macro ALT_ALLOW_CODE_AT_RESET in linker.h. This setting is typically false if an external bootloader (e.g. flash bootloader) is present. + false + + + + hal.linker.enable_alt_load + NONE + Boolean + 1 + 0 + none + Enables the alt_load() facility. The alt_load() facility copies sections from the .text memory into RAM. If true, this setting sets up the VMA/LMA of sections in linker.x to allow them to be loaded into the .text memory. + This setting is typically false if an external bootloader (e.g. flash bootloader) is present. + false + + + + hal.linker.enable_alt_load_copy_rodata + NONE + Boolean + 0 + 0 + none + Causes the alt_load() facility to copy the .rodata section. If true, this setting defines the macro ALT_LOAD_COPY_RODATA in linker.h. + none + false + + + + hal.linker.enable_alt_load_copy_rwdata + NONE + Boolean + 1 + 0 + none + Causes the alt_load() facility to copy the .rwdata section. If true, this setting defines the macro ALT_LOAD_COPY_RWDATA in linker.h. + none + false + + + + hal.linker.enable_alt_load_copy_exceptions + NONE + Boolean + 0 + 0 + none + Causes the alt_load() facility to copy the .exceptions section. If true, this setting defines the macro ALT_LOAD_COPY_EXCEPTIONS in linker.h. + none + false + + + + hal.linker.enable_exception_stack + NONE + Boolean + 0 + 0 + none + Enables use of a separate exception stack. If true, defines the macro ALT_EXCEPTION_STACK in linker.h, adds a memory region called exception_stack to linker.x, and provides the symbols __alt_exception_stack_pointer and __alt_exception_stack_limit in linker.x. + The hal.linker.exception_stack_size and hal.linker.exception_stack_memory_region_name settings must also be valid. This setting must be false for MicroC/OS-II BSPs. The exception stack can be used to improve interrupt and other exception performance if the EIC is *not* used. + false + common + + + hal.linker.exception_stack_size + NONE + DecimalNumber + 1024 + 1024 + none + Size of the exception stack in bytes. + Only used if hal.linker.enable_exception_stack is true. + false + common + + + hal.linker.exception_stack_memory_region_name + NONE + UnquotedString + sdram + none + none + Name of the existing memory region that will be divided up to create the 'exception_stack' memory region. The selected region name will be adjusted automatically when the BSP is generated to create the 'exception_stack' memory region. + Only used if hal.linker.enable_exception_stack is true. + false + common + + + hal.linker.enable_interrupt_stack + NONE + Boolean + 0 + 0 + none + Enables use of a separate interrupt stack. If true, defines the macro ALT_INTERRUPT_STACK in linker.h, adds a memory region called interrupt_stack to linker.x, and provides the symbols __alt_interrupt_stack_pointer and __alt_interrupt_stack_limit in linker.x. + The hal.linker.interrupt_stack_size and hal.linker.interrupt_stack_memory_region_name settings must also be valid. This setting must be false for MicroC/OS-II BSPs. Only enable if the EIC is used exclusively. The exception stack can be used to improve interrupt and other exception performance if the EIC is *not* used. + false + common + + + hal.linker.interrupt_stack_size + NONE + DecimalNumber + 1024 + 1024 + none + Size of the interrupt stack in bytes. + Only used if hal.linker.enable_interrupt_stack is true. + false + common + + + hal.linker.interrupt_stack_memory_region_name + NONE + UnquotedString + sdram + none + none + Name of the existing memory region that will be divided up to create the 'interrupt_stack' memory region. The selected region name will be adjusted automatically when the BSP is generated to create the 'interrupt_stack' memory region. + Only used if hal.linker.enable_interrupt_stack is true. + false + common + + + hal.stdin + NONE + UnquotedString + jtag_uart_0 + none + system_h_define + Slave descriptor of STDIN character-mode device. This setting is used by the ALT_STDIN family of defines in system.h. + none + false + common + + + hal.stdout + NONE + UnquotedString + jtag_uart_0 + none + system_h_define + Slave descriptor of STDOUT character-mode device. This setting is used by the ALT_STDOUT family of defines in system.h. + none + false + common + + + hal.stderr + NONE + UnquotedString + jtag_uart_0 + none + system_h_define + Slave descriptor of STDERR character-mode device. This setting is used by the ALT_STDERR family of defines in system.h. + none + false + common + + + hal.log_port + NONE + UnquotedString + none + none + public_mk_define + Slave descriptor of debug logging character-mode device. If defined, it enables extra debug messages in the HAL source. This setting is used by the ALT_LOG_PORT family of defines in system.h. + none + false + none + + + hal.make.build_pre_process + BUILD_PRE_PROCESS + UnquotedString + none + none + makefile_variable + Command executed before BSP built. + none + false + none + + + hal.make.ar_pre_process + AR_PRE_PROCESS + UnquotedString + none + none + makefile_variable + Command executed before archiver execution. + none + false + none + + + hal.make.bsp_cflags_defined_symbols + BSP_CFLAGS_DEFINED_SYMBOLS + UnquotedString + none + none + makefile_variable + Preprocessor macros to define. A macro definition in this setting has the same effect as a "#define" in source code. Adding "-DALT_DEBUG" to this setting has the same effect as "#define ALT_DEBUG" in a souce file. Adding "-DFOO=1" to this setting is equivalent to the macro "#define FOO 1" in a source file. Macros defined with this setting are applied to all .S, .c, and C++ files in the BSP. This setting defines the value of BSP_CFLAGS_DEFINED_SYMBOLS in the BSP Makefile. + none + false + none + + + hal.make.ar_post_process + AR_POST_PROCESS + UnquotedString + none + none + makefile_variable + Command executed after archiver execution. + none + false + none + + + hal.make.as + AS + UnquotedString + nios2-elf-gcc + nios2-elf-gcc + makefile_variable + Assembler command. Note that CC is used for .S files. + none + false + none + + + hal.make.build_post_process + BUILD_POST_PROCESS + UnquotedString + none + none + makefile_variable + Command executed after BSP built. + none + false + none + + + hal.make.bsp_cflags_debug + BSP_CFLAGS_DEBUG + UnquotedString + -g + -g + makefile_variable + C/C++ compiler debug level. '-g' provides the default set of debug symbols typically required to debug a typical application. Omitting '-g' removes debug symbols from the ELF. This setting defines the value of BSP_CFLAGS_DEBUG in Makefile. + none + false + common + + + hal.make.ar + AR + UnquotedString + nios2-elf-ar + nios2-elf-ar + makefile_variable + Archiver command. Creates library files. + none + false + none + + + hal.make.rm + RM + UnquotedString + rm -f + rm -f + makefile_variable + Command used to remove files during 'clean' target. + none + false + none + + + hal.make.cxx_pre_process + CXX_PRE_PROCESS + UnquotedString + none + none + makefile_variable + Command executed before each C++ file is compiled. + none + false + none + + + hal.make.bsp_cflags_warnings + BSP_CFLAGS_WARNINGS + UnquotedString + -Wall + -Wall + makefile_variable + C/C++ compiler warning level. "-Wall" is commonly used.This setting defines the value of BSP_CFLAGS_WARNINGS in Makefile. + none + false + none + + + hal.make.bsp_arflags + BSP_ARFLAGS + UnquotedString + -src + -src + makefile_variable + Custom flags only passed to the archiver. This content of this variable is directly passed to the archiver rather than the more standard "ARFLAGS". The reason for this is that GNU Make assumes some default content in ARFLAGS. This setting defines the value of BSP_ARFLAGS in Makefile. + none + false + none + + + hal.make.bsp_cflags_optimization + BSP_CFLAGS_OPTIMIZATION + UnquotedString + -O0 + -O0 + makefile_variable + C/C++ compiler optimization level. "-O0" = no optimization,"-O2" = "normal" optimization, etc. "-O0" is recommended for code that you want to debug since compiler optimization can remove variables and produce non-sequential execution of code while debugging. This setting defines the value of BSP_CFLAGS_OPTIMIZATION in Makefile. + none + false + common + + + hal.make.as_post_process + AS_POST_PROCESS + UnquotedString + none + none + makefile_variable + Command executed after each assembly file is compiled. + none + false + none + + + hal.make.cc_pre_process + CC_PRE_PROCESS + UnquotedString + none + none + makefile_variable + Command executed before each .c/.S file is compiled. + none + false + none + + + hal.make.bsp_asflags + BSP_ASFLAGS + UnquotedString + -Wa,-gdwarf2 + -Wa,-gdwarf2 + makefile_variable + Custom flags only passed to the assembler. This setting defines the value of BSP_ASFLAGS in Makefile. + none + false + none + + + hal.make.as_pre_process + AS_PRE_PROCESS + UnquotedString + none + none + makefile_variable + Command executed before each assembly file is compiled. + none + false + none + + + hal.make.bsp_cflags_undefined_symbols + BSP_CFLAGS_UNDEFINED_SYMBOLS + UnquotedString + none + none + makefile_variable + Preprocessor macros to undefine. Undefined macros are similar to defined macros, but replicate the "#undef" directive in source code. To undefine the macro FOO use the syntax "-u FOO" in this setting. This is equivalent to "#undef FOO" in a source file. Note: the syntax differs from macro definition (there is a space, i.e. "-u FOO" versus "-DFOO"). Macros defined with this setting are applied to all .S, .c, and C++ files in the BSP. This setting defines the value of BSP_CFLAGS_UNDEFINED_SYMBOLS in the BSP Makefile. + none + false + none + + + hal.make.cc_post_process + CC_POST_PROCESS + UnquotedString + none + none + makefile_variable + Command executed after each .c/.S file is compiled. + none + false + none + + + hal.make.cxx_post_process + CXX_POST_PROCESS + UnquotedString + none + none + makefile_variable + Command executed before each C++ file is compiled. + none + false + none + + + hal.make.cc + CC + UnquotedString + nios2-elf-gcc -xc + nios2-elf-gcc -xc + makefile_variable + C compiler command. + none + false + none + + + hal.make.bsp_cxx_flags + BSP_CXXFLAGS + UnquotedString + none + none + makefile_variable + Custom flags only passed to the C++ compiler. This setting defines the value of BSP_CXXFLAGS in Makefile. + none + false + none + + + hal.make.bsp_inc_dirs + BSP_INC_DIRS + UnquotedString + none + none + makefile_variable + Space separated list of extra include directories to scan for header files. Directories are relative to the top-level BSP directory. The -I prefix's added by the makefile so don't add it here. This setting defines the value of BSP_INC_DIRS in Makefile. + none + false + none + + + hal.make.cxx + CXX + UnquotedString + nios2-elf-gcc -xc++ + nios2-elf-gcc -xc++ + makefile_variable + C++ compiler command. + none + false + none + + + hal.make.bsp_cflags_user_flags + BSP_CFLAGS_USER_FLAGS + UnquotedString + none + none + makefile_variable + Custom flags passed to the compiler when compiling C, C++, and .S files. This setting defines the value of BSP_CFLAGS_USER_FLAGS in Makefile. + none + false + none + + + hal.make.ignore_system_derived.sopc_system_id + NONE + Boolean + 0 + 0 + public_mk_define + Enable BSP generation to query SOPC system for system ID. If true ignores export of 'SOPC_SYSID_FLAG += --id=<sysid>' and 'ELF_PATCH_FLAG += --id=<sysid>' to public.mk. + none + false + none + + + hal.make.ignore_system_derived.sopc_system_timestamp + NONE + Boolean + 0 + 0 + public_mk_define + Enable BSP generation to query SOPC system for system timestamp. If true ignores export of 'SOPC_SYSID_FLAG += --timestamp=<timestamp>' and 'ELF_PATCH_FLAG += --timestamp=<timestamp>' to public.mk. + none + false + none + + + hal.make.ignore_system_derived.sopc_system_base_address + NONE + Boolean + 0 + 0 + public_mk_define + Enable BSP generation to query SOPC system for system ID base address. If true ignores export of 'SOPC_SYSID_FLAG += --sidp=<address>' and 'ELF_PATCH_FLAG += --sidp=<address>' to public.mk. + none + false + none + + + hal.make.ignore_system_derived.sopc_simulation_enabled + NONE + Boolean + 0 + 0 + public_mk_define + Enable BSP generation to query if SOPC system has simulation enabled. If true ignores export of 'ELF_PATCH_FLAG += --simulation_enabled' to public.mk. + none + false + none + + + hal.make.ignore_system_derived.fpu_present + NONE + Boolean + 0 + 0 + public_mk_define + Enable BSP generation to query if SOPC system has FPU present. If true ignores export of 'ALT_CFLAGS += -mhard-float' to public.mk if FPU is found in the system. If true ignores export of 'ALT_CFLAGS += -mhard-soft' if FPU is not found in the system. + none + false + none + + + hal.make.ignore_system_derived.hardware_multiplier_present + NONE + Boolean + 0 + 0 + public_mk_define + Enable BSP generation to query if SOPC system has multiplier present. If true ignores export of 'ALT_CFLAGS += -mno-hw-mul' to public.mk if no multiplier is found in the system. If true ignores export of 'ALT_CFLAGS += -mhw-mul' if multiplier is found in the system. + none + false + none + + + hal.make.ignore_system_derived.hardware_mulx_present + NONE + Boolean + 0 + 0 + public_mk_define + Enable BSP generation to query if SOPC system has hardware mulx present. If true ignores export of 'ALT_CFLAGS += -mno-hw-mulx' to public.mk if no mulx is found in the system. If true ignores export of 'ALT_CFLAGS += -mhw-mulx' if mulx is found in the system. + none + false + none + + + hal.make.ignore_system_derived.hardware_divide_present + NONE + Boolean + 0 + 0 + public_mk_define + Enable BSP generation to query if SOPC system has hardware divide present. If true ignores export of 'ALT_CFLAGS += -mno-hw-div' to public.mk if no division is found in system. If true ignores export of 'ALT_CFLAGS += -mhw-div' if division is found in the system. + none + false + none + + + hal.make.ignore_system_derived.debug_core_present + NONE + Boolean + 0 + 0 + public_mk_define + Enable BSP generation to query if SOPC system has a debug core present. If true ignores export of 'CPU_HAS_DEBUG_CORE = 1' to public.mk if a debug core is found in the system. If true ignores export of 'CPU_HAS_DEBUG_CORE = 0' if no debug core is found in the system. + none + false + none + + + hal.make.ignore_system_derived.big_endian + NONE + Boolean + 0 + 0 + public_mk_define + Enable BSP generation to query if SOPC system is big endian. If true ignores export of 'ALT_CFLAGS += -EB' to public.mk if big endian system. If true ignores export of 'ALT_CFLAGS += -EL' if little endian system. + none + false + none + + + hal.make.ignore_system_derived.hardware_fp_cust_inst_divider_present + NONE + Boolean + 0 + 0 + public_mk_define + Enable BSP generation to query if SOPC system floating point custom instruction with a divider is present. If true ignores export of 'ALT_CFLAGS += -mcustom-fpu-cfg=60-2' and 'ALT_LDFLAGS += -mcustom-fpu-cfg=60-2' to public.mk if the custom instruction is found in the system. + none + false + none + + + hal.make.ignore_system_derived.hardware_fp_cust_inst_no_divider_present + NONE + Boolean + 0 + 0 + public_mk_define + Enable BSP generation to query if SOPC system floating point custom instruction without a divider is present. If true ignores export of 'ALT_CFLAGS += -mcustom-fpu-cfg=60-1' and 'ALT_LDFLAGS += -mcustom-fpu-cfg=60-1' to public.mk if the custom instruction is found in the system. + none + false + none + + + hal.enable_exit + ALT_NO_EXIT + Boolean + 1 + 1 + public_mk_define + Add exit() support. This option increases code footprint if your "main()" routine does "return" or call "exit()". If false, adds -DALT_NO_EXIT to ALT_CPPFLAGS in public.mk, and reduces footprint + none + false + none + + + hal.enable_small_c_library + NONE + Boolean + 0 + 0 + public_mk_define + Causes the small newlib (C library) to be used. This reduces code and data footprint at the expense of reduced functionality. Several newlib features are removed such as floating-point support in printf(), stdin input routines, and buffered I/O. The small C library is not compatible with Micrium MicroC/OS-II. If true, adds -msmallc to ALT_LDFLAGS in public.mk. + none + false + common + + + hal.enable_clean_exit + ALT_NO_CLEAN_EXIT + Boolean + 1 + 1 + public_mk_define + When your application exits, close file descriptors, call C++ destructors, etc. Code footprint can be reduced by disabling clean exit. If disabled, adds -DALT_NO_CLEAN_EXIT to ALT_CPPFLAGS and -Wl,--defsym, exit=_exit to ALT_LDFLAGS in public.mk. + none + false + none + + + hal.enable_runtime_stack_checking + ALT_STACK_CHECK + Boolean + 0 + 0 + public_mk_define + Turns on HAL runtime stack checking feature. Enabling this setting causes additional code to be placed into each subroutine call to generate an exception if a stack collision occurs with the heap or statically allocated data. If true, adds -DALT_STACK_CHECK and -mstack-check to ALT_CPPFLAGS in public.mk. + none + false + none + + + hal.enable_gprof + ALT_PROVIDE_GMON + Boolean + 0 + 0 + public_mk_define + Causes code to be compiled with gprof profiling enabled and the application ELF to be linked with the GPROF library. If true, adds -DALT_PROVIDE_GMON to ALT_CPPFLAGS and -pg to ALT_CFLAGS in public.mk. + none + false + common + + + hal.enable_c_plus_plus + ALT_NO_C_PLUS_PLUS + Boolean + 1 + 1 + public_mk_define + Enable support for a subset of the C++ language. This option increases code footprint by adding support for C++ constructors. Certain features, such as multiple inheritance and exceptions are not supported. If false, adds -DALT_NO_C_PLUS_PLUS to ALT_CPPFLAGS in public.mk, and reduces code footprint. + none + false + none + + + hal.enable_reduced_device_drivers + ALT_USE_SMALL_DRIVERS + Boolean + 0 + 0 + public_mk_define + Certain drivers are compiled with reduced functionality to reduce code footprint. Not all drivers observe this setting. The altera_avalon_uart and altera_avalon_jtag_uart drivers switch from interrupt-driven to polled operation. CAUTION: Several device drivers are disabled entirely. These include the altera_avalon_cfi_flash, altera_avalon_epcs_flash_controller, and altera_avalon_lcd_16207 drivers. This can result in certain API (HAL flash access routines) to fail. You can define a symbol provided by each driver to prevent it from being removed. If true, adds -DALT_USE_SMALL_DRIVERS to ALT_CPPFLAGS in public.mk. + none + false + common + + + hal.enable_lightweight_device_driver_api + ALT_USE_DIRECT_DRIVERS + Boolean + 0 + 0 + public_mk_define + Enables lightweight device driver API. This reduces code and data footprint by removing the HAL layer that maps device names (e.g. /dev/uart0) to file descriptors. Instead, driver routines are called directly. The open(), close(), and lseek() routines will always fail if called. The read(), write(), fstat(), ioctl(), and isatty() routines only work for the stdio devices. If true, adds -DALT_USE_DIRECT_DRIVERS to ALT_CPPFLAGS in public.mk. + The Altera Host and read-only ZIP file systems can't be used if hal.enable_lightweight_device_driver_api is true. + false + none + + + hal.enable_mul_div_emulation + ALT_NO_INSTRUCTION_EMULATION + Boolean + 0 + 0 + public_mk_define + Adds code to emulate multiply and divide instructions in case they are executed but aren't present in the CPU. Normally this isn't required because the compiler won't use multiply and divide instructions that aren't present in the CPU. If false, adds -DALT_NO_INSTRUCTION_EMULATION to ALT_CPPFLAGS in public.mk. + none + false + none + + + hal.enable_sim_optimize + ALT_SIM_OPTIMIZE + Boolean + 0 + 0 + public_mk_define + The BSP is compiled with optimizations to speedup HDL simulation such as initializing the cache, clearing the .bss section, and skipping long delay loops. If true, adds -DALT_SIM_OPTIMIZE to ALT_CPPFLAGS in public.mk. + When this setting is true, the BSP shouldn't be used to build applications that are expected to run real hardware. + false + common + + + hal.enable_sopc_sysid_check + NONE + Boolean + 1 + 1 + public_mk_define + Enable SOPC Builder System ID. If a System ID SOPC Builder component is connected to the CPU associated with this BSP, it will be enabled in the creation of command-line arguments to download an ELF to the target. Otherwise, system ID and timestamp values are left out of public.mk for application Makefile "download-elf" target definition. With the system ID check disabled, the Nios II EDS tools will not automatically ensure that the application .elf file (and BSP it is linked against) corresponds to the hardware design on the target. If false, adds --accept-bad-sysid to SOPC_SYSID_FLAG in public.mk. + none + false + none + + + hal.custom_newlib_flags + CUSTOM_NEWLIB_FLAGS + UnquotedString + none + none + public_mk_define + Build a custom version of newlib with the specified space-separated compiler flags. + The custom newlib build will be placed in the &lt;bsp root>/newlib directory, and will be used only for applications that utilize this BSP. + false + none + + + hal.log_flags + ALT_LOG_FLAGS + DecimalNumber + 0 + 0 + public_mk_define + The value is assigned to ALT_LOG_FLAGS in the generated public.mk. See hal.log_port setting description. Values can be -1 through 3. + hal.log_port must be set for this to be used. + false + none + + + ucosii.os_max_tasks + OS_MAX_TASKS + DecimalNumber + 10 + 10 + system_h_define + Maximum number of tasks + none + false + + + + ucosii.os_lowest_prio + OS_LOWEST_PRIO + DecimalNumber + 20 + 20 + system_h_define + Lowest assignable priority + none + false + + + + ucosii.os_thread_safe_newlib + OS_THREAD_SAFE_NEWLIB + Boolean + 1 + 1 + system_h_define + Thread safe C library + none + false + + + + ucosii.miscellaneous.os_arg_chk_en + OS_ARG_CHK_EN + Boolean + 1 + 1 + system_h_define + Enable argument checking + none + false + + + + ucosii.miscellaneous.os_cpu_hooks_en + OS_CPU_HOOKS_EN + Boolean + 1 + 1 + system_h_define + Enable uCOS-II hooks + none + false + + + + ucosii.miscellaneous.os_debug_en + OS_DEBUG_EN + Boolean + 1 + 1 + system_h_define + Enable debug variables + none + false + + + + ucosii.miscellaneous.os_sched_lock_en + OS_SCHED_LOCK_EN + Boolean + 1 + 1 + system_h_define + Include code for OSSchedLock() and OSSchedUnlock() + none + false + + + + ucosii.miscellaneous.os_task_stat_en + OS_TASK_STAT_EN + Boolean + 1 + 1 + system_h_define + Enable statistics task + none + false + + + + ucosii.miscellaneous.os_task_stat_stk_chk_en + OS_TASK_STAT_STK_CHK_EN + Boolean + 1 + 1 + system_h_define + Check task stacks from statistics task + none + false + + + + ucosii.miscellaneous.os_tick_step_en + OS_TICK_STEP_EN + Boolean + 1 + 1 + system_h_define + Enable tick stepping feature for uCOS-View + none + false + + + + ucosii.miscellaneous.os_event_name_size + OS_EVENT_NAME_SIZE + DecimalNumber + 32 + 32 + system_h_define + Size of name of Event Control Block groups + none + false + + + + ucosii.miscellaneous.os_max_events + OS_MAX_EVENTS + DecimalNumber + 60 + 60 + system_h_define + Maximum number of event control blocks + none + false + + + + ucosii.miscellaneous.os_task_idle_stk_size + OS_TASK_IDLE_STK_SIZE + DecimalNumber + 512 + 512 + system_h_define + Idle task stack size + none + false + + + + ucosii.miscellaneous.os_task_stat_stk_size + OS_TASK_STAT_STK_SIZE + DecimalNumber + 512 + 512 + system_h_define + Statistics task stack size + none + false + + + + ucosii.task.os_task_change_prio_en + OS_TASK_CHANGE_PRIO_EN + Boolean + 1 + 1 + system_h_define + Include code for OSTaskChangePrio() + none + false + + + + ucosii.task.os_task_create_en + OS_TASK_CREATE_EN + Boolean + 1 + 1 + system_h_define + Include code for OSTaskCreate() + none + false + + + + ucosii.task.os_task_create_ext_en + OS_TASK_CREATE_EXT_EN + Boolean + 1 + 1 + system_h_define + Include code for OSTaskCreateExt() + none + false + + + + ucosii.task.os_task_del_en + OS_TASK_DEL_EN + Boolean + 1 + 1 + system_h_define + Include code for OSTaskDel() + none + false + + + + ucosii.task.os_task_name_size + OS_TASK_NAME_SIZE + DecimalNumber + 32 + 32 + system_h_define + Size of task name + none + false + + + + ucosii.task.os_task_profile_en + OS_TASK_PROFILE_EN + Boolean + 1 + 1 + system_h_define + Include data structure for run-time task profiling + none + false + + + + ucosii.task.os_task_query_en + OS_TASK_QUERY_EN + Boolean + 1 + 1 + system_h_define + Include code for OSTaskQuery + none + false + + + + ucosii.task.os_task_suspend_en + OS_TASK_SUSPEND_EN + Boolean + 1 + 1 + system_h_define + Include code for OSTaskSuspend() and OSTaskResume() + none + false + + + + ucosii.task.os_task_sw_hook_en + OS_TASK_SW_HOOK_EN + Boolean + 1 + 1 + system_h_define + Include code for OSTaskSwHook() + none + false + + + + ucosii.time.os_time_tick_hook_en + OS_TIME_TICK_HOOK_EN + Boolean + 1 + 1 + system_h_define + Include code for OSTimeTickHook() + none + false + + + + ucosii.time.os_time_dly_resume_en + OS_TIME_DLY_RESUME_EN + Boolean + 1 + 1 + system_h_define + Include code for OSTimeDlyResume() + none + false + + + + ucosii.time.os_time_dly_hmsm_en + OS_TIME_DLY_HMSM_EN + Boolean + 1 + 1 + system_h_define + Include code for OSTimeDlyHMSM() + none + false + + + + ucosii.time.os_time_get_set_en + OS_TIME_GET_SET_EN + Boolean + 1 + 1 + system_h_define + Include code for OSTimeGet and OSTimeSet() + none + false + + + + ucosii.os_flag_en + OS_FLAG_EN + Boolean + 1 + 1 + system_h_define + Enable code for Event Flags. CAUTION: This is required by the HAL and many Altera device drivers. + none + false + + + + ucosii.event_flag.os_flag_wait_clr_en + OS_FLAG_WAIT_CLR_EN + Boolean + 1 + 1 + system_h_define + Include code for Wait on Clear Event Flags. CAUTION: This is required by the HAL and many Altera device drivers. + none + false + + + + ucosii.event_flag.os_flag_accept_en + OS_FLAG_ACCEPT_EN + Boolean + 1 + 1 + system_h_define + Include code for OSFlagAccept(). CAUTION: This is required by the HAL and many Altera device drivers. + none + false + + + + ucosii.event_flag.os_flag_del_en + OS_FLAG_DEL_EN + Boolean + 1 + 1 + system_h_define + Include code for OSFlagDel(). CAUTION: This is required by the HAL and many Altera device drivers. + none + false + + + + ucosii.event_flag.os_flag_query_en + OS_FLAG_QUERY_EN + Boolean + 1 + 1 + system_h_define + Include code for OSFlagQuery(). CAUTION: This is required by the HAL and many Altera device drivers. + none + false + + + + ucosii.event_flag.os_flag_name_size + OS_FLAG_NAME_SIZE + DecimalNumber + 32 + 32 + system_h_define + Size of name of Event Flags group. CAUTION: This is required by the HAL and many Altera device drivers; use caution in reducing this value. + none + false + + + + ucosii.event_flag.os_flags_nbits + OS_FLAGS_NBITS + DecimalNumber + 16 + 16 + system_h_define + Event Flag bits (8,16,32). CAUTION: This is required by the HAL and many Altera device drivers; use caution in changing this value. + none + false + + + + ucosii.event_flag.os_max_flags + OS_MAX_FLAGS + DecimalNumber + 20 + 20 + system_h_define + Maximum number of Event Flags groups. CAUTION: This is required by the HAL and many Altera device drivers; use caution in reducing this value. + none + false + + + + ucosii.os_mutex_en + OS_MUTEX_EN + Boolean + 1 + 1 + system_h_define + Enable code for Mutex Semaphores + none + false + + + + ucosii.mutex.os_mutex_accept_en + OS_MUTEX_ACCEPT_EN + Boolean + 1 + 1 + system_h_define + Include code for OSMutexAccept() + none + false + + + + ucosii.mutex.os_mutex_del_en + OS_MUTEX_DEL_EN + Boolean + 1 + 1 + system_h_define + Include code for OSMutexDel() + none + false + + + + ucosii.mutex.os_mutex_query_en + OS_MUTEX_QUERY_EN + Boolean + 1 + 1 + system_h_define + Include code for OSMutexQuery + none + false + + + + ucosii.os_sem_en + OS_SEM_EN + Boolean + 1 + 1 + system_h_define + Enable code for semaphores. CAUTION: This is required by the HAL and many Altera device drivers. + none + false + + + + ucosii.semaphore.os_sem_accept_en + OS_SEM_ACCEPT_EN + Boolean + 1 + 1 + system_h_define + Include code for OSSemAccept(). CAUTION: This is required by the HAL and many Altera device drivers. + none + false + + + + ucosii.semaphore.os_sem_set_en + OS_SEM_SET_EN + Boolean + 1 + 1 + system_h_define + Include code for OSSemSet(). CAUTION: This is required by the HAL and many Altera device drivers. + none + false + + + + ucosii.semaphore.os_sem_del_en + OS_SEM_DEL_EN + Boolean + 1 + 1 + system_h_define + Include code for OSSemDel(). CAUTION: This is required by the HAL and many Altera device drivers. + none + false + + + + ucosii.semaphore.os_sem_query_en + OS_SEM_QUERY_EN + Boolean + 1 + 1 + system_h_define + Include code for OSSemQuery(). CAUTION: This is required by the HAL and many Altera device drivers. + none + false + + + + ucosii.os_mbox_en + OS_MBOX_EN + Boolean + 1 + 1 + system_h_define + Enable code for mailboxes + none + false + + + + ucosii.mailbox.os_mbox_accept_en + OS_MBOX_ACCEPT_EN + Boolean + 1 + 1 + system_h_define + Include code for OSMboxAccept() + none + false + + + + ucosii.mailbox.os_mbox_del_en + OS_MBOX_DEL_EN + Boolean + 1 + 1 + system_h_define + Include code for OSMboxDel() + none + false + + + + ucosii.mailbox.os_mbox_post_en + OS_MBOX_POST_EN + Boolean + 1 + 1 + system_h_define + Include code for OSMboxPost() + none + false + + + + ucosii.mailbox.os_mbox_post_opt_en + OS_MBOX_POST_OPT_EN + Boolean + 1 + 1 + system_h_define + Include code for OSMboxPostOpt() + none + false + + + + ucosii.mailbox.os_mbox_query_en + OS_MBOX_QUERY_EN + Boolean + 1 + 1 + system_h_define + Include code for OSMboxQuery() + none + false + + + + ucosii.os_q_en + OS_Q_EN + Boolean + 1 + 1 + system_h_define + Enable code for Queues + none + false + + + + ucosii.queue.os_q_accept_en + OS_Q_ACCEPT_EN + Boolean + 1 + 1 + system_h_define + Include code for OSQAccept() + none + false + + + + ucosii.queue.os_q_del_en + OS_Q_DEL_EN + Boolean + 1 + 1 + system_h_define + Include code for OSQDel() + none + false + + + + ucosii.queue.os_q_flush_en + OS_Q_FLUSH_EN + Boolean + 1 + 1 + system_h_define + Include code for OSQFlush() + none + false + + + + ucosii.queue.os_q_post_en + OS_Q_POST_EN + Boolean + 1 + 1 + system_h_define + Include code of OSQFlush() + none + false + + + + ucosii.queue.os_q_post_front_en + OS_Q_POST_FRONT_EN + Boolean + 1 + 1 + system_h_define + Include code for OSQPostFront() + none + false + + + + ucosii.queue.os_q_post_opt_en + OS_Q_POST_OPT_EN + Boolean + 1 + 1 + system_h_define + Include code for OSQPostOpt() + none + false + + + + ucosii.queue.os_q_query_en + OS_Q_QUERY_EN + Boolean + 1 + 1 + system_h_define + Include code for OSQQuery() + none + false + + + + ucosii.queue.os_max_qs + OS_MAX_QS + DecimalNumber + 20 + 20 + system_h_define + Maximum number of Queue Control Blocks + none + false + + + + ucosii.os_mem_en + OS_MEM_EN + Boolean + 1 + 1 + system_h_define + Enable code for memory management + none + false + + + + ucosii.memory.os_mem_query_en + OS_MEM_QUERY_EN + Boolean + 1 + 1 + system_h_define + Include code for OSMemQuery() + none + false + + + + ucosii.memory.os_mem_name_size + OS_MEM_NAME_SIZE + DecimalNumber + 32 + 32 + system_h_define + Size of memory partition name + none + false + + + + ucosii.memory.os_max_mem_part + OS_MAX_MEM_PART + DecimalNumber + 60 + 60 + system_h_define + Maximum number of memory partitions + none + false + + + + ucosii.os_tmr_en + OS_TMR_EN + Boolean + 0 + 0 + system_h_define + Enable code for timers + none + false + + + + ucosii.timer.os_task_tmr_stk_size + OS_TASK_TMR_STK_SIZE + DecimalNumber + 512 + 512 + system_h_define + Stack size for timer task + none + false + + + + ucosii.timer.os_task_tmr_prio + OS_TASK_TMR_PRIO + DecimalNumber + 0 + 0 + system_h_define + Priority of timer task (0=highest) + none + false + + + + ucosii.timer.os_tmr_cfg_max + OS_TMR_CFG_MAX + DecimalNumber + 16 + 16 + system_h_define + Maximum number of timers + none + false + + + + ucosii.timer.os_tmr_cfg_name_size + OS_TMR_CFG_NAME_SIZE + DecimalNumber + 16 + 16 + system_h_define + Size of timer name + none + false + + + + ucosii.timer.os_tmr_cfg_ticks_per_sec + OS_TMR_CFG_TICKS_PER_SEC + DecimalNumber + 10 + 10 + system_h_define + Rate at which timer management task runs (Hz) + none + false + + + + ucosii.timer.os_tmr_cfg_wheel_size + OS_TMR_CFG_WHEEL_SIZE + DecimalNumber + 2 + 2 + system_h_define + Size of timer wheel (number of spokes) + none + false + + + + altera_avalon_uart_driver.enable_small_driver + ALTERA_AVALON_UART_SMALL + BooleanDefineOnly + false + false + public_mk_define + Small-footprint (polled mode) driver + none + false + + + + altera_avalon_uart_driver.enable_ioctl + ALTERA_AVALON_UART_USE_IOCTL + BooleanDefineOnly + false + false + public_mk_define + Enable driver ioctl() support. This feature is not compatible with the 'small' driver; ioctl() support will not be compiled if either the UART 'enable_small_driver' or HAL 'enable_reduced_device_drivers' settings are enabled. + none + false + + + + altera_avalon_jtag_uart_driver.enable_small_driver + ALTERA_AVALON_JTAG_UART_SMALL + BooleanDefineOnly + false + false + public_mk_define + Small-footprint (polled mode) driver + none + false + + + + sdram + 0x01000000 - 0x01FFFFFF + 16777216 + memory + + + uart_mc + 0x02001000 - 0x0200101F + 32 + printable + + + pio_led + 0x02001020 - 0x0200103F + 32 + + + + uart_wifi + 0x02001040 - 0x0200105F + 32 + printable + + + sys_clk_timer + 0x02001060 - 0x0200107F + 32 + timer + + + pio_ir_emitter + 0x02001080 - 0x0200108F + 16 + + + + pio_sw + 0x02001090 - 0x0200109F + 16 + + + + pio_key_left + 0x020010A0 - 0x020010AF + 16 + + + + rs232_wifi + 0x020010B0 - 0x020010B7 + 8 + + + + jtag_uart_0 + 0x020010B8 - 0x020010BF + 8 + printable + + + sysid + 0x020010C0 - 0x020010C7 + 8 + + + + .text + sdram + + + .rodata + sdram + + + .rwdata + sdram + + + .bss + sdram + + + .heap + sdram + + + .stack + sdram + + \ No newline at end of file diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/summary.html b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/summary.html new file mode 100644 index 00000000..96840054 --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/summary.html @@ -0,0 +1,3946 @@ + +Altera Nios II BSP Summary + +

BSP Description

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BSP Type:ucosii
SOPC Design File:C:\Users\gongal\NewRepARCap\MCandWifiTestDE0\system.sopcinfo
Quartus JDI File:default
CPU:cpu
BSP Settings File:settings.bsp
BSP Version:default
BSP Generated On:3-Mar-2014 4:17:24 PM
BSP Generated Timestamp:1393888644631
BSP Generated Location:C:\Users\gongal\NewRepARCap\MCandWifiTestDE0\Software\MCTest_bsp
+
+

Nios II Memory Map

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Slave DescriptorAddress RangeSizeAttributes
sysid0x020010C0 - 0x020010C78 
jtag_uart_00x020010B8 - 0x020010BF8printable
rs232_wifi0x020010B0 - 0x020010B78 
pio_key_left0x020010A0 - 0x020010AF16 
pio_sw0x02001090 - 0x0200109F16 
pio_ir_emitter0x02001080 - 0x0200108F16 
sys_clk_timer0x02001060 - 0x0200107F32timer
uart_wifi0x02001040 - 0x0200105F32printable
pio_led0x02001020 - 0x0200103F32 
uart_mc0x02001000 - 0x0200101F32printable
sdram0x01000000 - 0x01FFFFFF16777216memory
+
+
+

Linker Regions

+ + + + +
RegionAddress RangeSizeMemoryOffset
+
+
+

Linker Section Mappings

+ + + + + + + + + + + + + + + + + + + + + + +
SectionRegion
.textsdram
.rodatasdram
.rwdatasdram
.bsssdram
.heapsdram
.stacksdram
+

Settings

+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:altera_avalon_jtag_uart_driver.enable_small_driver
Identifier:ALTERA_AVALON_JTAG_UART_SMALL
Default Value:false
Value:false
Type:BooleanDefineOnly
Destination:public_mk_define
Description:Small-footprint (polled mode) driver
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:altera_avalon_uart_driver.enable_ioctl
Identifier:ALTERA_AVALON_UART_USE_IOCTL
Default Value:false
Value:false
Type:BooleanDefineOnly
Destination:public_mk_define
Description:Enable driver ioctl() support. This feature is not compatible with the 'small' driver; ioctl() support will not be compiled if either the UART 'enable_small_driver' or HAL 'enable_reduced_device_drivers' settings are enabled.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:altera_avalon_uart_driver.enable_small_driver
Identifier:ALTERA_AVALON_UART_SMALL
Default Value:false
Value:false
Type:BooleanDefineOnly
Destination:public_mk_define
Description:Small-footprint (polled mode) driver
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.custom_newlib_flags
Identifier:CUSTOM_NEWLIB_FLAGS
Default Value:none
Value:none
Type:UnquotedString
Destination:public_mk_define
Description:Build a custom version of newlib with the specified space-separated compiler flags.
Restrictions:The custom newlib build will be placed in the &lt;bsp root>/newlib directory, and will be used only for applications that utilize this BSP.
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.enable_c_plus_plus
Identifier:ALT_NO_C_PLUS_PLUS
Default Value:1
Value:1
Type:Boolean
Destination:public_mk_define
Description:Enable support for a subset of the C++ language. This option increases code footprint by adding support for C++ constructors. Certain features, such as multiple inheritance and exceptions are not supported. If false, adds -DALT_NO_C_PLUS_PLUS to ALT_CPPFLAGS in public.mk, and reduces code footprint.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.enable_clean_exit
Identifier:ALT_NO_CLEAN_EXIT
Default Value:1
Value:1
Type:Boolean
Destination:public_mk_define
Description:When your application exits, close file descriptors, call C++ destructors, etc. Code footprint can be reduced by disabling clean exit. If disabled, adds -DALT_NO_CLEAN_EXIT to ALT_CPPFLAGS and -Wl,--defsym, exit=_exit to ALT_LDFLAGS in public.mk.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.enable_exit
Identifier:ALT_NO_EXIT
Default Value:1
Value:1
Type:Boolean
Destination:public_mk_define
Description:Add exit() support. This option increases code footprint if your "main()" routine does "return" or call "exit()". If false, adds -DALT_NO_EXIT to ALT_CPPFLAGS in public.mk, and reduces footprint
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.enable_gprof
Identifier:ALT_PROVIDE_GMON
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Causes code to be compiled with gprof profiling enabled and the application ELF to be linked with the GPROF library. If true, adds -DALT_PROVIDE_GMON to ALT_CPPFLAGS and -pg to ALT_CFLAGS in public.mk.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.enable_instruction_related_exceptions_api
Identifier:ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API
Default Value:false
Value:false
Type:BooleanDefineOnly
Destination:system_h_define
Description:Enables API for registering handlers to service instruction-related exceptions. Enabling this setting increases the size of the exception entry code.
Restrictions:These exception types can be generated if various processor options are enabled, such as the MMU, MPU, or other advanced exception types.
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.enable_lightweight_device_driver_api
Identifier:ALT_USE_DIRECT_DRIVERS
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Enables lightweight device driver API. This reduces code and data footprint by removing the HAL layer that maps device names (e.g. /dev/uart0) to file descriptors. Instead, driver routines are called directly. The open(), close(), and lseek() routines will always fail if called. The read(), write(), fstat(), ioctl(), and isatty() routines only work for the stdio devices. If true, adds -DALT_USE_DIRECT_DRIVERS to ALT_CPPFLAGS in public.mk.
Restrictions:The Altera Host and read-only ZIP file systems can't be used if hal.enable_lightweight_device_driver_api is true.
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.enable_mul_div_emulation
Identifier:ALT_NO_INSTRUCTION_EMULATION
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Adds code to emulate multiply and divide instructions in case they are executed but aren't present in the CPU. Normally this isn't required because the compiler won't use multiply and divide instructions that aren't present in the CPU. If false, adds -DALT_NO_INSTRUCTION_EMULATION to ALT_CPPFLAGS in public.mk.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.enable_reduced_device_drivers
Identifier:ALT_USE_SMALL_DRIVERS
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Certain drivers are compiled with reduced functionality to reduce code footprint. Not all drivers observe this setting. The altera_avalon_uart and altera_avalon_jtag_uart drivers switch from interrupt-driven to polled operation. CAUTION: Several device drivers are disabled entirely. These include the altera_avalon_cfi_flash, altera_avalon_epcs_flash_controller, and altera_avalon_lcd_16207 drivers. This can result in certain API (HAL flash access routines) to fail. You can define a symbol provided by each driver to prevent it from being removed. If true, adds -DALT_USE_SMALL_DRIVERS to ALT_CPPFLAGS in public.mk.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.enable_runtime_stack_checking
Identifier:ALT_STACK_CHECK
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Turns on HAL runtime stack checking feature. Enabling this setting causes additional code to be placed into each subroutine call to generate an exception if a stack collision occurs with the heap or statically allocated data. If true, adds -DALT_STACK_CHECK and -mstack-check to ALT_CPPFLAGS in public.mk.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.enable_sim_optimize
Identifier:ALT_SIM_OPTIMIZE
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:The BSP is compiled with optimizations to speedup HDL simulation such as initializing the cache, clearing the .bss section, and skipping long delay loops. If true, adds -DALT_SIM_OPTIMIZE to ALT_CPPFLAGS in public.mk.
Restrictions:When this setting is true, the BSP shouldn't be used to build applications that are expected to run real hardware.
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.enable_small_c_library
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Causes the small newlib (C library) to be used. This reduces code and data footprint at the expense of reduced functionality. Several newlib features are removed such as floating-point support in printf(), stdin input routines, and buffered I/O. The small C library is not compatible with Micrium MicroC/OS-II. If true, adds -msmallc to ALT_LDFLAGS in public.mk.
Restrictions:none
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+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.enable_sopc_sysid_check
Identifier:NONE
Default Value:1
Value:1
Type:Boolean
Destination:public_mk_define
Description:Enable SOPC Builder System ID. If a System ID SOPC Builder component is connected to the CPU associated with this BSP, it will be enabled in the creation of command-line arguments to download an ELF to the target. Otherwise, system ID and timestamp values are left out of public.mk for application Makefile "download-elf" target definition. With the system ID check disabled, the Nios II EDS tools will not automatically ensure that the application .elf file (and BSP it is linked against) corresponds to the hardware design on the target. If false, adds --accept-bad-sysid to SOPC_SYSID_FLAG in public.mk.
Restrictions:none
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+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.linker.allow_code_at_reset
Identifier:ALT_ALLOW_CODE_AT_RESET
Default Value:0
Value:1
Type:Boolean
Destination:none
Description:Indicates if initialization code is allowed at the reset address. If true, defines the macro ALT_ALLOW_CODE_AT_RESET in linker.h.
Restrictions:If true, defines the macro ALT_ALLOW_CODE_AT_RESET in linker.h. This setting is typically false if an external bootloader (e.g. flash bootloader) is present.
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+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.linker.enable_alt_load
Identifier:NONE
Default Value:0
Value:1
Type:Boolean
Destination:none
Description:Enables the alt_load() facility. The alt_load() facility copies sections from the .text memory into RAM. If true, this setting sets up the VMA/LMA of sections in linker.x to allow them to be loaded into the .text memory.
Restrictions:This setting is typically false if an external bootloader (e.g. flash bootloader) is present.
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+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.linker.enable_alt_load_copy_exceptions
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:none
Description:Causes the alt_load() facility to copy the .exceptions section. If true, this setting defines the macro ALT_LOAD_COPY_EXCEPTIONS in linker.h.
Restrictions:none
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+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.linker.enable_alt_load_copy_rodata
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:none
Description:Causes the alt_load() facility to copy the .rodata section. If true, this setting defines the macro ALT_LOAD_COPY_RODATA in linker.h.
Restrictions:none
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+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.linker.enable_alt_load_copy_rwdata
Identifier:NONE
Default Value:0
Value:1
Type:Boolean
Destination:none
Description:Causes the alt_load() facility to copy the .rwdata section. If true, this setting defines the macro ALT_LOAD_COPY_RWDATA in linker.h.
Restrictions:none
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+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.linker.enable_exception_stack
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:none
Description:Enables use of a separate exception stack. If true, defines the macro ALT_EXCEPTION_STACK in linker.h, adds a memory region called exception_stack to linker.x, and provides the symbols __alt_exception_stack_pointer and __alt_exception_stack_limit in linker.x.
Restrictions:The hal.linker.exception_stack_size and hal.linker.exception_stack_memory_region_name settings must also be valid. This setting must be false for MicroC/OS-II BSPs. The exception stack can be used to improve interrupt and other exception performance if the EIC is *not* used.
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+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.linker.enable_interrupt_stack
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:none
Description:Enables use of a separate interrupt stack. If true, defines the macro ALT_INTERRUPT_STACK in linker.h, adds a memory region called interrupt_stack to linker.x, and provides the symbols __alt_interrupt_stack_pointer and __alt_interrupt_stack_limit in linker.x.
Restrictions:The hal.linker.interrupt_stack_size and hal.linker.interrupt_stack_memory_region_name settings must also be valid. This setting must be false for MicroC/OS-II BSPs. Only enable if the EIC is used exclusively. The exception stack can be used to improve interrupt and other exception performance if the EIC is *not* used.
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+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.linker.exception_stack_memory_region_name
Identifier:NONE
Default Value:none
Value:sdram
Type:UnquotedString
Destination:none
Description:Name of the existing memory region that will be divided up to create the 'exception_stack' memory region. The selected region name will be adjusted automatically when the BSP is generated to create the 'exception_stack' memory region.
Restrictions:Only used if hal.linker.enable_exception_stack is true.
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+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.linker.exception_stack_size
Identifier:NONE
Default Value:1024
Value:1024
Type:DecimalNumber
Destination:none
Description:Size of the exception stack in bytes.
Restrictions:Only used if hal.linker.enable_exception_stack is true.
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+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.linker.interrupt_stack_memory_region_name
Identifier:NONE
Default Value:none
Value:sdram
Type:UnquotedString
Destination:none
Description:Name of the existing memory region that will be divided up to create the 'interrupt_stack' memory region. The selected region name will be adjusted automatically when the BSP is generated to create the 'interrupt_stack' memory region.
Restrictions:Only used if hal.linker.enable_interrupt_stack is true.
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+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.linker.interrupt_stack_size
Identifier:NONE
Default Value:1024
Value:1024
Type:DecimalNumber
Destination:none
Description:Size of the interrupt stack in bytes.
Restrictions:Only used if hal.linker.enable_interrupt_stack is true.
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+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.log_flags
Identifier:ALT_LOG_FLAGS
Default Value:0
Value:0
Type:DecimalNumber
Destination:public_mk_define
Description:The value is assigned to ALT_LOG_FLAGS in the generated public.mk. See hal.log_port setting description. Values can be -1 through 3.
Restrictions:hal.log_port must be set for this to be used.
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+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.log_port
Identifier:NONE
Default Value:none
Value:none
Type:UnquotedString
Destination:public_mk_define
Description:Slave descriptor of debug logging character-mode device. If defined, it enables extra debug messages in the HAL source. This setting is used by the ALT_LOG_PORT family of defines in system.h.
Restrictions:none
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+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.ar
Identifier:AR
Default Value:nios2-elf-ar
Value:nios2-elf-ar
Type:UnquotedString
Destination:makefile_variable
Description:Archiver command. Creates library files.
Restrictions:none
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+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.ar_post_process
Identifier:AR_POST_PROCESS
Default Value:none
Value:none
Type:UnquotedString
Destination:makefile_variable
Description:Command executed after archiver execution.
Restrictions:none
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+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.ar_pre_process
Identifier:AR_PRE_PROCESS
Default Value:none
Value:none
Type:UnquotedString
Destination:makefile_variable
Description:Command executed before archiver execution.
Restrictions:none
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+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.as
Identifier:AS
Default Value:nios2-elf-gcc
Value:nios2-elf-gcc
Type:UnquotedString
Destination:makefile_variable
Description:Assembler command. Note that CC is used for .S files.
Restrictions:none
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+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.as_post_process
Identifier:AS_POST_PROCESS
Default Value:none
Value:none
Type:UnquotedString
Destination:makefile_variable
Description:Command executed after each assembly file is compiled.
Restrictions:none
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+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.as_pre_process
Identifier:AS_PRE_PROCESS
Default Value:none
Value:none
Type:UnquotedString
Destination:makefile_variable
Description:Command executed before each assembly file is compiled.
Restrictions:none
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+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.bsp_arflags
Identifier:BSP_ARFLAGS
Default Value:-src
Value:-src
Type:UnquotedString
Destination:makefile_variable
Description:Custom flags only passed to the archiver. This content of this variable is directly passed to the archiver rather than the more standard "ARFLAGS". The reason for this is that GNU Make assumes some default content in ARFLAGS. This setting defines the value of BSP_ARFLAGS in Makefile.
Restrictions:none
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+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.bsp_asflags
Identifier:BSP_ASFLAGS
Default Value:-Wa,-gdwarf2
Value:-Wa,-gdwarf2
Type:UnquotedString
Destination:makefile_variable
Description:Custom flags only passed to the assembler. This setting defines the value of BSP_ASFLAGS in Makefile.
Restrictions:none
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+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.bsp_cflags_debug
Identifier:BSP_CFLAGS_DEBUG
Default Value:-g
Value:-g
Type:UnquotedString
Destination:makefile_variable
Description:C/C++ compiler debug level. '-g' provides the default set of debug symbols typically required to debug a typical application. Omitting '-g' removes debug symbols from the ELF. This setting defines the value of BSP_CFLAGS_DEBUG in Makefile.
Restrictions:none
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+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.bsp_cflags_defined_symbols
Identifier:BSP_CFLAGS_DEFINED_SYMBOLS
Default Value:none
Value:none
Type:UnquotedString
Destination:makefile_variable
Description:Preprocessor macros to define. A macro definition in this setting has the same effect as a "#define" in source code. Adding "-DALT_DEBUG" to this setting has the same effect as "#define ALT_DEBUG" in a souce file. Adding "-DFOO=1" to this setting is equivalent to the macro "#define FOO 1" in a source file. Macros defined with this setting are applied to all .S, .c, and C++ files in the BSP. This setting defines the value of BSP_CFLAGS_DEFINED_SYMBOLS in the BSP Makefile.
Restrictions:none
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+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.bsp_cflags_optimization
Identifier:BSP_CFLAGS_OPTIMIZATION
Default Value:-O0
Value:-O0
Type:UnquotedString
Destination:makefile_variable
Description:C/C++ compiler optimization level. "-O0" = no optimization,"-O2" = "normal" optimization, etc. "-O0" is recommended for code that you want to debug since compiler optimization can remove variables and produce non-sequential execution of code while debugging. This setting defines the value of BSP_CFLAGS_OPTIMIZATION in Makefile.
Restrictions:none
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+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.bsp_cflags_undefined_symbols
Identifier:BSP_CFLAGS_UNDEFINED_SYMBOLS
Default Value:none
Value:none
Type:UnquotedString
Destination:makefile_variable
Description:Preprocessor macros to undefine. Undefined macros are similar to defined macros, but replicate the "#undef" directive in source code. To undefine the macro FOO use the syntax "-u FOO" in this setting. This is equivalent to "#undef FOO" in a source file. Note: the syntax differs from macro definition (there is a space, i.e. "-u FOO" versus "-DFOO"). Macros defined with this setting are applied to all .S, .c, and C++ files in the BSP. This setting defines the value of BSP_CFLAGS_UNDEFINED_SYMBOLS in the BSP Makefile.
Restrictions:none
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+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.bsp_cflags_user_flags
Identifier:BSP_CFLAGS_USER_FLAGS
Default Value:none
Value:none
Type:UnquotedString
Destination:makefile_variable
Description:Custom flags passed to the compiler when compiling C, C++, and .S files. This setting defines the value of BSP_CFLAGS_USER_FLAGS in Makefile.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.bsp_cflags_warnings
Identifier:BSP_CFLAGS_WARNINGS
Default Value:-Wall
Value:-Wall
Type:UnquotedString
Destination:makefile_variable
Description:C/C++ compiler warning level. "-Wall" is commonly used.This setting defines the value of BSP_CFLAGS_WARNINGS in Makefile.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.bsp_cxx_flags
Identifier:BSP_CXXFLAGS
Default Value:none
Value:none
Type:UnquotedString
Destination:makefile_variable
Description:Custom flags only passed to the C++ compiler. This setting defines the value of BSP_CXXFLAGS in Makefile.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.bsp_inc_dirs
Identifier:BSP_INC_DIRS
Default Value:none
Value:none
Type:UnquotedString
Destination:makefile_variable
Description:Space separated list of extra include directories to scan for header files. Directories are relative to the top-level BSP directory. The -I prefix's added by the makefile so don't add it here. This setting defines the value of BSP_INC_DIRS in Makefile.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.build_post_process
Identifier:BUILD_POST_PROCESS
Default Value:none
Value:none
Type:UnquotedString
Destination:makefile_variable
Description:Command executed after BSP built.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.build_pre_process
Identifier:BUILD_PRE_PROCESS
Default Value:none
Value:none
Type:UnquotedString
Destination:makefile_variable
Description:Command executed before BSP built.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.cc
Identifier:CC
Default Value:nios2-elf-gcc -xc
Value:nios2-elf-gcc -xc
Type:UnquotedString
Destination:makefile_variable
Description:C compiler command.
Restrictions:none
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+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.cc_post_process
Identifier:CC_POST_PROCESS
Default Value:none
Value:none
Type:UnquotedString
Destination:makefile_variable
Description:Command executed after each .c/.S file is compiled.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.cc_pre_process
Identifier:CC_PRE_PROCESS
Default Value:none
Value:none
Type:UnquotedString
Destination:makefile_variable
Description:Command executed before each .c/.S file is compiled.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.cxx
Identifier:CXX
Default Value:nios2-elf-gcc -xc++
Value:nios2-elf-gcc -xc++
Type:UnquotedString
Destination:makefile_variable
Description:C++ compiler command.
Restrictions:none
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+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.cxx_post_process
Identifier:CXX_POST_PROCESS
Default Value:none
Value:none
Type:UnquotedString
Destination:makefile_variable
Description:Command executed before each C++ file is compiled.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.cxx_pre_process
Identifier:CXX_PRE_PROCESS
Default Value:none
Value:none
Type:UnquotedString
Destination:makefile_variable
Description:Command executed before each C++ file is compiled.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.ignore_system_derived.big_endian
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Enable BSP generation to query if SOPC system is big endian. If true ignores export of 'ALT_CFLAGS += -EB' to public.mk if big endian system. If true ignores export of 'ALT_CFLAGS += -EL' if little endian system.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.ignore_system_derived.debug_core_present
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Enable BSP generation to query if SOPC system has a debug core present. If true ignores export of 'CPU_HAS_DEBUG_CORE = 1' to public.mk if a debug core is found in the system. If true ignores export of 'CPU_HAS_DEBUG_CORE = 0' if no debug core is found in the system.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.ignore_system_derived.fpu_present
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Enable BSP generation to query if SOPC system has FPU present. If true ignores export of 'ALT_CFLAGS += -mhard-float' to public.mk if FPU is found in the system. If true ignores export of 'ALT_CFLAGS += -mhard-soft' if FPU is not found in the system.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.ignore_system_derived.hardware_divide_present
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Enable BSP generation to query if SOPC system has hardware divide present. If true ignores export of 'ALT_CFLAGS += -mno-hw-div' to public.mk if no division is found in system. If true ignores export of 'ALT_CFLAGS += -mhw-div' if division is found in the system.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.ignore_system_derived.hardware_fp_cust_inst_divider_present
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Enable BSP generation to query if SOPC system floating point custom instruction with a divider is present. If true ignores export of 'ALT_CFLAGS += -mcustom-fpu-cfg=60-2' and 'ALT_LDFLAGS += -mcustom-fpu-cfg=60-2' to public.mk if the custom instruction is found in the system.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.ignore_system_derived.hardware_fp_cust_inst_no_divider_present
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Enable BSP generation to query if SOPC system floating point custom instruction without a divider is present. If true ignores export of 'ALT_CFLAGS += -mcustom-fpu-cfg=60-1' and 'ALT_LDFLAGS += -mcustom-fpu-cfg=60-1' to public.mk if the custom instruction is found in the system.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.ignore_system_derived.hardware_multiplier_present
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Enable BSP generation to query if SOPC system has multiplier present. If true ignores export of 'ALT_CFLAGS += -mno-hw-mul' to public.mk if no multiplier is found in the system. If true ignores export of 'ALT_CFLAGS += -mhw-mul' if multiplier is found in the system.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.ignore_system_derived.hardware_mulx_present
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Enable BSP generation to query if SOPC system has hardware mulx present. If true ignores export of 'ALT_CFLAGS += -mno-hw-mulx' to public.mk if no mulx is found in the system. If true ignores export of 'ALT_CFLAGS += -mhw-mulx' if mulx is found in the system.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.ignore_system_derived.sopc_simulation_enabled
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Enable BSP generation to query if SOPC system has simulation enabled. If true ignores export of 'ELF_PATCH_FLAG += --simulation_enabled' to public.mk.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.ignore_system_derived.sopc_system_base_address
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Enable BSP generation to query SOPC system for system ID base address. If true ignores export of 'SOPC_SYSID_FLAG += --sidp=<address>' and 'ELF_PATCH_FLAG += --sidp=<address>' to public.mk.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.ignore_system_derived.sopc_system_id
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Enable BSP generation to query SOPC system for system ID. If true ignores export of 'SOPC_SYSID_FLAG += --id=<sysid>' and 'ELF_PATCH_FLAG += --id=<sysid>' to public.mk.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.ignore_system_derived.sopc_system_timestamp
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Enable BSP generation to query SOPC system for system timestamp. If true ignores export of 'SOPC_SYSID_FLAG += --timestamp=<timestamp>' and 'ELF_PATCH_FLAG += --timestamp=<timestamp>' to public.mk.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.rm
Identifier:RM
Default Value:rm -f
Value:rm -f
Type:UnquotedString
Destination:makefile_variable
Description:Command used to remove files during 'clean' target.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.max_file_descriptors
Identifier:ALT_MAX_FD
Default Value:32
Value:32
Type:DecimalNumber
Destination:system_h_define
Description:Determines the number of file descriptors statically allocated. This setting defines the value of ALT_MAX_FD in system.h.
Restrictions:If hal.enable_lightweight_device_driver_api is true, there are no file descriptors so this setting is ignored. If hal.enable_lightweight_device_driver_api is false, this setting must be at least 4 because HAL needs a file descriptor for /dev/null, /dev/stdin, /dev/stdout, and /dev/stderr.
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.stderr
Identifier:NONE
Default Value:none
Value:jtag_uart_0
Type:UnquotedString
Destination:system_h_define
Description:Slave descriptor of STDERR character-mode device. This setting is used by the ALT_STDERR family of defines in system.h.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.stdin
Identifier:NONE
Default Value:none
Value:jtag_uart_0
Type:UnquotedString
Destination:system_h_define
Description:Slave descriptor of STDIN character-mode device. This setting is used by the ALT_STDIN family of defines in system.h.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.stdout
Identifier:NONE
Default Value:none
Value:jtag_uart_0
Type:UnquotedString
Destination:system_h_define
Description:Slave descriptor of STDOUT character-mode device. This setting is used by the ALT_STDOUT family of defines in system.h.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.sys_clk_timer
Identifier:ALT_SYS_CLK
Default Value:none
Value:sys_clk_timer
Type:UnquotedString
Destination:system_h_define
Description:Slave descriptor of the system clock timer device. This device provides a periodic interrupt ("tick") and is typically required for RTOS use. This setting defines the value of ALT_SYS_CLK in system.h.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.timestamp_timer
Identifier:ALT_TIMESTAMP_CLK
Default Value:none
Value:none
Type:UnquotedString
Destination:system_h_define
Description:Slave descriptor of timestamp timer device. This device is used by Altera HAL timestamp drivers for high-resolution time measurement. This setting defines the value of ALT_TIMESTAMP_CLK in system.h.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.event_flag.os_flag_accept_en
Identifier:OS_FLAG_ACCEPT_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSFlagAccept(). CAUTION: This is required by the HAL and many Altera device drivers.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.event_flag.os_flag_del_en
Identifier:OS_FLAG_DEL_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSFlagDel(). CAUTION: This is required by the HAL and many Altera device drivers.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.event_flag.os_flag_name_size
Identifier:OS_FLAG_NAME_SIZE
Default Value:32
Value:32
Type:DecimalNumber
Destination:system_h_define
Description:Size of name of Event Flags group. CAUTION: This is required by the HAL and many Altera device drivers; use caution in reducing this value.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.event_flag.os_flag_query_en
Identifier:OS_FLAG_QUERY_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSFlagQuery(). CAUTION: This is required by the HAL and many Altera device drivers.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.event_flag.os_flag_wait_clr_en
Identifier:OS_FLAG_WAIT_CLR_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for Wait on Clear Event Flags. CAUTION: This is required by the HAL and many Altera device drivers.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.event_flag.os_flags_nbits
Identifier:OS_FLAGS_NBITS
Default Value:16
Value:16
Type:DecimalNumber
Destination:system_h_define
Description:Event Flag bits (8,16,32). CAUTION: This is required by the HAL and many Altera device drivers; use caution in changing this value.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.event_flag.os_max_flags
Identifier:OS_MAX_FLAGS
Default Value:20
Value:20
Type:DecimalNumber
Destination:system_h_define
Description:Maximum number of Event Flags groups. CAUTION: This is required by the HAL and many Altera device drivers; use caution in reducing this value.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.mailbox.os_mbox_accept_en
Identifier:OS_MBOX_ACCEPT_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSMboxAccept()
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.mailbox.os_mbox_del_en
Identifier:OS_MBOX_DEL_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSMboxDel()
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.mailbox.os_mbox_post_en
Identifier:OS_MBOX_POST_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSMboxPost()
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.mailbox.os_mbox_post_opt_en
Identifier:OS_MBOX_POST_OPT_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSMboxPostOpt()
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.mailbox.os_mbox_query_en
Identifier:OS_MBOX_QUERY_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSMboxQuery()
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.memory.os_max_mem_part
Identifier:OS_MAX_MEM_PART
Default Value:60
Value:60
Type:DecimalNumber
Destination:system_h_define
Description:Maximum number of memory partitions
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.memory.os_mem_name_size
Identifier:OS_MEM_NAME_SIZE
Default Value:32
Value:32
Type:DecimalNumber
Destination:system_h_define
Description:Size of memory partition name
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.memory.os_mem_query_en
Identifier:OS_MEM_QUERY_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSMemQuery()
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.miscellaneous.os_arg_chk_en
Identifier:OS_ARG_CHK_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Enable argument checking
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.miscellaneous.os_cpu_hooks_en
Identifier:OS_CPU_HOOKS_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Enable uCOS-II hooks
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.miscellaneous.os_debug_en
Identifier:OS_DEBUG_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Enable debug variables
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.miscellaneous.os_event_name_size
Identifier:OS_EVENT_NAME_SIZE
Default Value:32
Value:32
Type:DecimalNumber
Destination:system_h_define
Description:Size of name of Event Control Block groups
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.miscellaneous.os_max_events
Identifier:OS_MAX_EVENTS
Default Value:60
Value:60
Type:DecimalNumber
Destination:system_h_define
Description:Maximum number of event control blocks
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.miscellaneous.os_sched_lock_en
Identifier:OS_SCHED_LOCK_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSSchedLock() and OSSchedUnlock()
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.miscellaneous.os_task_idle_stk_size
Identifier:OS_TASK_IDLE_STK_SIZE
Default Value:512
Value:512
Type:DecimalNumber
Destination:system_h_define
Description:Idle task stack size
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.miscellaneous.os_task_stat_en
Identifier:OS_TASK_STAT_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Enable statistics task
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.miscellaneous.os_task_stat_stk_chk_en
Identifier:OS_TASK_STAT_STK_CHK_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Check task stacks from statistics task
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.miscellaneous.os_task_stat_stk_size
Identifier:OS_TASK_STAT_STK_SIZE
Default Value:512
Value:512
Type:DecimalNumber
Destination:system_h_define
Description:Statistics task stack size
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.miscellaneous.os_tick_step_en
Identifier:OS_TICK_STEP_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Enable tick stepping feature for uCOS-View
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.mutex.os_mutex_accept_en
Identifier:OS_MUTEX_ACCEPT_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSMutexAccept()
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.mutex.os_mutex_del_en
Identifier:OS_MUTEX_DEL_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSMutexDel()
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.mutex.os_mutex_query_en
Identifier:OS_MUTEX_QUERY_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSMutexQuery
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.os_flag_en
Identifier:OS_FLAG_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Enable code for Event Flags. CAUTION: This is required by the HAL and many Altera device drivers.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.os_lowest_prio
Identifier:OS_LOWEST_PRIO
Default Value:20
Value:20
Type:DecimalNumber
Destination:system_h_define
Description:Lowest assignable priority
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.os_max_tasks
Identifier:OS_MAX_TASKS
Default Value:10
Value:10
Type:DecimalNumber
Destination:system_h_define
Description:Maximum number of tasks
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.os_mbox_en
Identifier:OS_MBOX_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Enable code for mailboxes
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.os_mem_en
Identifier:OS_MEM_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Enable code for memory management
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.os_mutex_en
Identifier:OS_MUTEX_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Enable code for Mutex Semaphores
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.os_q_en
Identifier:OS_Q_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Enable code for Queues
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.os_sem_en
Identifier:OS_SEM_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Enable code for semaphores. CAUTION: This is required by the HAL and many Altera device drivers.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.os_thread_safe_newlib
Identifier:OS_THREAD_SAFE_NEWLIB
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Thread safe C library
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.os_tmr_en
Identifier:OS_TMR_EN
Default Value:0
Value:0
Type:Boolean
Destination:system_h_define
Description:Enable code for timers
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.queue.os_max_qs
Identifier:OS_MAX_QS
Default Value:20
Value:20
Type:DecimalNumber
Destination:system_h_define
Description:Maximum number of Queue Control Blocks
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.queue.os_q_accept_en
Identifier:OS_Q_ACCEPT_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSQAccept()
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.queue.os_q_del_en
Identifier:OS_Q_DEL_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSQDel()
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.queue.os_q_flush_en
Identifier:OS_Q_FLUSH_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSQFlush()
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.queue.os_q_post_en
Identifier:OS_Q_POST_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code of OSQFlush()
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.queue.os_q_post_front_en
Identifier:OS_Q_POST_FRONT_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSQPostFront()
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.queue.os_q_post_opt_en
Identifier:OS_Q_POST_OPT_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSQPostOpt()
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.queue.os_q_query_en
Identifier:OS_Q_QUERY_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSQQuery()
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.semaphore.os_sem_accept_en
Identifier:OS_SEM_ACCEPT_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSSemAccept(). CAUTION: This is required by the HAL and many Altera device drivers.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.semaphore.os_sem_del_en
Identifier:OS_SEM_DEL_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSSemDel(). CAUTION: This is required by the HAL and many Altera device drivers.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.semaphore.os_sem_query_en
Identifier:OS_SEM_QUERY_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSSemQuery(). CAUTION: This is required by the HAL and many Altera device drivers.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.semaphore.os_sem_set_en
Identifier:OS_SEM_SET_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSSemSet(). CAUTION: This is required by the HAL and many Altera device drivers.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.task.os_task_change_prio_en
Identifier:OS_TASK_CHANGE_PRIO_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSTaskChangePrio()
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.task.os_task_create_en
Identifier:OS_TASK_CREATE_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSTaskCreate()
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.task.os_task_create_ext_en
Identifier:OS_TASK_CREATE_EXT_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSTaskCreateExt()
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.task.os_task_del_en
Identifier:OS_TASK_DEL_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSTaskDel()
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.task.os_task_name_size
Identifier:OS_TASK_NAME_SIZE
Default Value:32
Value:32
Type:DecimalNumber
Destination:system_h_define
Description:Size of task name
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.task.os_task_profile_en
Identifier:OS_TASK_PROFILE_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include data structure for run-time task profiling
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.task.os_task_query_en
Identifier:OS_TASK_QUERY_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSTaskQuery
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.task.os_task_suspend_en
Identifier:OS_TASK_SUSPEND_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSTaskSuspend() and OSTaskResume()
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.task.os_task_sw_hook_en
Identifier:OS_TASK_SW_HOOK_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSTaskSwHook()
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.time.os_time_dly_hmsm_en
Identifier:OS_TIME_DLY_HMSM_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSTimeDlyHMSM()
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.time.os_time_dly_resume_en
Identifier:OS_TIME_DLY_RESUME_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSTimeDlyResume()
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.time.os_time_get_set_en
Identifier:OS_TIME_GET_SET_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSTimeGet and OSTimeSet()
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.time.os_time_tick_hook_en
Identifier:OS_TIME_TICK_HOOK_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSTimeTickHook()
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.timer.os_task_tmr_prio
Identifier:OS_TASK_TMR_PRIO
Default Value:0
Value:0
Type:DecimalNumber
Destination:system_h_define
Description:Priority of timer task (0=highest)
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.timer.os_task_tmr_stk_size
Identifier:OS_TASK_TMR_STK_SIZE
Default Value:512
Value:512
Type:DecimalNumber
Destination:system_h_define
Description:Stack size for timer task
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.timer.os_tmr_cfg_max
Identifier:OS_TMR_CFG_MAX
Default Value:16
Value:16
Type:DecimalNumber
Destination:system_h_define
Description:Maximum number of timers
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.timer.os_tmr_cfg_name_size
Identifier:OS_TMR_CFG_NAME_SIZE
Default Value:16
Value:16
Type:DecimalNumber
Destination:system_h_define
Description:Size of timer name
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.timer.os_tmr_cfg_ticks_per_sec
Identifier:OS_TMR_CFG_TICKS_PER_SEC
Default Value:10
Value:10
Type:DecimalNumber
Destination:system_h_define
Description:Rate at which timer management task runs (Hz)
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.timer.os_tmr_cfg_wheel_size
Identifier:OS_TMR_CFG_WHEEL_SIZE
Default Value:2
Value:2
Type:DecimalNumber
Destination:system_h_define
Description:Size of timer wheel (number of spokes)
Restrictions:none
+
+
+
+ + diff --git a/MCandWifiTestDE0/Software/Archive/MCTest_bsp/system.h b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/system.h new file mode 100644 index 00000000..0f9ed689 --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCTest_bsp/system.h @@ -0,0 +1,534 @@ +/* + * system.h - SOPC Builder system and BSP software package information + * + * Machine generated for CPU 'cpu' in SOPC Builder design 'system' + * SOPC Builder design path: C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system.sopcinfo + * + * Generated: Mon Mar 03 15:52:38 MST 2014 + */ + +/* + * DO NOT MODIFY THIS FILE + * + * Changing this file will have subtle consequences + * which will almost certainly lead to a nonfunctioning + * system. If you do modify this file, be aware that your + * changes will be overwritten and lost when this file + * is generated again. + * + * DO NOT MODIFY THIS FILE + */ + +/* + * License Agreement + * + * Copyright (c) 2008 + * Altera Corporation, San Jose, California, USA. + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * This agreement shall be governed in all respects by the laws of the State + * of California and by the laws of the United States of America. + */ + +#ifndef __SYSTEM_H_ +#define __SYSTEM_H_ + +/* Include definitions from linker script generator */ +#include "linker.h" + + +/* + * CPU configuration + * + */ + +#define ALT_CPU_ARCHITECTURE "altera_nios2_qsys" +#define ALT_CPU_BIG_ENDIAN 0 +#define ALT_CPU_BREAK_ADDR 0x2000820 +#define ALT_CPU_CPU_FREQ 100000000u +#define ALT_CPU_CPU_ID_SIZE 1 +#define ALT_CPU_CPU_ID_VALUE 0x00000000 +#define ALT_CPU_CPU_IMPLEMENTATION "fast" +#define ALT_CPU_DATA_ADDR_WIDTH 0x1a +#define ALT_CPU_DCACHE_LINE_SIZE 32 +#define ALT_CPU_DCACHE_LINE_SIZE_LOG2 5 +#define ALT_CPU_DCACHE_SIZE 4096 +#define ALT_CPU_EXCEPTION_ADDR 0x1000020 +#define ALT_CPU_FLUSHDA_SUPPORTED +#define ALT_CPU_FREQ 100000000 +#define ALT_CPU_HARDWARE_DIVIDE_PRESENT 0 +#define ALT_CPU_HARDWARE_MULTIPLY_PRESENT 1 +#define ALT_CPU_HARDWARE_MULX_PRESENT 0 +#define ALT_CPU_HAS_DEBUG_CORE 1 +#define ALT_CPU_HAS_DEBUG_STUB +#define ALT_CPU_HAS_JMPI_INSTRUCTION +#define ALT_CPU_ICACHE_LINE_SIZE 32 +#define ALT_CPU_ICACHE_LINE_SIZE_LOG2 5 +#define ALT_CPU_ICACHE_SIZE 8192 +#define ALT_CPU_INITDA_SUPPORTED +#define ALT_CPU_INST_ADDR_WIDTH 0x1a +#define ALT_CPU_NAME "cpu" +#define ALT_CPU_NUM_OF_SHADOW_REG_SETS 0 +#define ALT_CPU_RESET_ADDR 0x1000000 + + +/* + * CPU configuration (with legacy prefix - don't use these anymore) + * + */ + +#define NIOS2_BIG_ENDIAN 0 +#define NIOS2_BREAK_ADDR 0x2000820 +#define NIOS2_CPU_FREQ 100000000u +#define NIOS2_CPU_ID_SIZE 1 +#define NIOS2_CPU_ID_VALUE 0x00000000 +#define NIOS2_CPU_IMPLEMENTATION "fast" +#define NIOS2_DATA_ADDR_WIDTH 0x1a +#define NIOS2_DCACHE_LINE_SIZE 32 +#define NIOS2_DCACHE_LINE_SIZE_LOG2 5 +#define NIOS2_DCACHE_SIZE 4096 +#define NIOS2_EXCEPTION_ADDR 0x1000020 +#define NIOS2_FLUSHDA_SUPPORTED +#define NIOS2_HARDWARE_DIVIDE_PRESENT 0 +#define NIOS2_HARDWARE_MULTIPLY_PRESENT 1 +#define NIOS2_HARDWARE_MULX_PRESENT 0 +#define NIOS2_HAS_DEBUG_CORE 1 +#define NIOS2_HAS_DEBUG_STUB +#define NIOS2_HAS_JMPI_INSTRUCTION +#define NIOS2_ICACHE_LINE_SIZE 32 +#define NIOS2_ICACHE_LINE_SIZE_LOG2 5 +#define NIOS2_ICACHE_SIZE 8192 +#define NIOS2_INITDA_SUPPORTED +#define NIOS2_INST_ADDR_WIDTH 0x1a +#define NIOS2_NUM_OF_SHADOW_REG_SETS 0 +#define NIOS2_RESET_ADDR 0x1000000 + + +/* + * Define for each module class mastered by the CPU + * + */ + +#define __ALTERA_AVALON_JTAG_UART +#define __ALTERA_AVALON_NEW_SDRAM_CONTROLLER +#define __ALTERA_AVALON_PIO +#define __ALTERA_AVALON_SYSID_QSYS +#define __ALTERA_AVALON_TIMER +#define __ALTERA_AVALON_UART +#define __ALTERA_NIOS2_QSYS +#define __ALTERA_UP_AVALON_RS232 + + +/* + * System configuration + * + */ + +#define ALT_DEVICE_FAMILY "Cyclone IV E" +#define ALT_IRQ_BASE NULL +#define ALT_LEGACY_INTERRUPT_API_PRESENT +#define ALT_LOG_PORT "/dev/null" +#define ALT_LOG_PORT_BASE 0x0 +#define ALT_LOG_PORT_DEV null +#define ALT_LOG_PORT_TYPE "" +#define ALT_NUM_EXTERNAL_INTERRUPT_CONTROLLERS 0 +#define ALT_NUM_INTERNAL_INTERRUPT_CONTROLLERS 1 +#define ALT_NUM_INTERRUPT_CONTROLLERS 1 +#define ALT_STDERR "/dev/jtag_uart_0" +#define ALT_STDERR_BASE 0x20010b8 +#define ALT_STDERR_DEV jtag_uart_0 +#define ALT_STDERR_IS_JTAG_UART +#define ALT_STDERR_PRESENT +#define ALT_STDERR_TYPE "altera_avalon_jtag_uart" +#define ALT_STDIN "/dev/jtag_uart_0" +#define ALT_STDIN_BASE 0x20010b8 +#define ALT_STDIN_DEV jtag_uart_0 +#define ALT_STDIN_IS_JTAG_UART +#define ALT_STDIN_PRESENT +#define ALT_STDIN_TYPE "altera_avalon_jtag_uart" +#define ALT_STDOUT "/dev/jtag_uart_0" +#define ALT_STDOUT_BASE 0x20010b8 +#define ALT_STDOUT_DEV jtag_uart_0 +#define ALT_STDOUT_IS_JTAG_UART +#define ALT_STDOUT_PRESENT +#define ALT_STDOUT_TYPE "altera_avalon_jtag_uart" +#define ALT_SYSTEM_NAME "system" + + +/* + * hal configuration + * + */ + +#define ALT_MAX_FD 32 +#define ALT_SYS_CLK SYS_CLK_TIMER +#define ALT_TIMESTAMP_CLK none + + +/* + * jtag_uart_0 configuration + * + */ + +#define ALT_MODULE_CLASS_jtag_uart_0 altera_avalon_jtag_uart +#define JTAG_UART_0_BASE 0x20010b8 +#define JTAG_UART_0_IRQ 14 +#define JTAG_UART_0_IRQ_INTERRUPT_CONTROLLER_ID 0 +#define JTAG_UART_0_NAME "/dev/jtag_uart_0" +#define JTAG_UART_0_READ_DEPTH 64 +#define JTAG_UART_0_READ_THRESHOLD 8 +#define JTAG_UART_0_SPAN 8 +#define JTAG_UART_0_TYPE "altera_avalon_jtag_uart" +#define JTAG_UART_0_WRITE_DEPTH 64 +#define JTAG_UART_0_WRITE_THRESHOLD 8 + + +/* + * pio_ir_emitter configuration + * + */ + +#define ALT_MODULE_CLASS_pio_ir_emitter altera_avalon_pio +#define PIO_IR_EMITTER_BASE 0x2001080 +#define PIO_IR_EMITTER_BIT_CLEARING_EDGE_REGISTER 0 +#define PIO_IR_EMITTER_BIT_MODIFYING_OUTPUT_REGISTER 0 +#define PIO_IR_EMITTER_CAPTURE 0 +#define PIO_IR_EMITTER_DATA_WIDTH 1 +#define PIO_IR_EMITTER_DO_TEST_BENCH_WIRING 0 +#define PIO_IR_EMITTER_DRIVEN_SIM_VALUE 0x0 +#define PIO_IR_EMITTER_EDGE_TYPE "NONE" +#define PIO_IR_EMITTER_FREQ 100000000u +#define PIO_IR_EMITTER_HAS_IN 0 +#define PIO_IR_EMITTER_HAS_OUT 1 +#define PIO_IR_EMITTER_HAS_TRI 0 +#define PIO_IR_EMITTER_IRQ -1 +#define PIO_IR_EMITTER_IRQ_INTERRUPT_CONTROLLER_ID -1 +#define PIO_IR_EMITTER_IRQ_TYPE "NONE" +#define PIO_IR_EMITTER_NAME "/dev/pio_ir_emitter" +#define PIO_IR_EMITTER_RESET_VALUE 0x0 +#define PIO_IR_EMITTER_SPAN 16 +#define PIO_IR_EMITTER_TYPE "altera_avalon_pio" + + +/* + * pio_key_left configuration + * + */ + +#define ALT_MODULE_CLASS_pio_key_left altera_avalon_pio +#define PIO_KEY_LEFT_BASE 0x20010a0 +#define PIO_KEY_LEFT_BIT_CLEARING_EDGE_REGISTER 1 +#define PIO_KEY_LEFT_BIT_MODIFYING_OUTPUT_REGISTER 0 +#define PIO_KEY_LEFT_CAPTURE 1 +#define PIO_KEY_LEFT_DATA_WIDTH 1 +#define PIO_KEY_LEFT_DO_TEST_BENCH_WIRING 0 +#define PIO_KEY_LEFT_DRIVEN_SIM_VALUE 0x0 +#define PIO_KEY_LEFT_EDGE_TYPE "ANY" +#define PIO_KEY_LEFT_FREQ 100000000u +#define PIO_KEY_LEFT_HAS_IN 1 +#define PIO_KEY_LEFT_HAS_OUT 0 +#define PIO_KEY_LEFT_HAS_TRI 0 +#define PIO_KEY_LEFT_IRQ 1 +#define PIO_KEY_LEFT_IRQ_INTERRUPT_CONTROLLER_ID 0 +#define PIO_KEY_LEFT_IRQ_TYPE "EDGE" +#define PIO_KEY_LEFT_NAME "/dev/pio_key_left" +#define PIO_KEY_LEFT_RESET_VALUE 0x0 +#define PIO_KEY_LEFT_SPAN 16 +#define PIO_KEY_LEFT_TYPE "altera_avalon_pio" + + +/* + * pio_led configuration + * + */ + +#define ALT_MODULE_CLASS_pio_led altera_avalon_pio +#define PIO_LED_BASE 0x2001020 +#define PIO_LED_BIT_CLEARING_EDGE_REGISTER 0 +#define PIO_LED_BIT_MODIFYING_OUTPUT_REGISTER 1 +#define PIO_LED_CAPTURE 0 +#define PIO_LED_DATA_WIDTH 7 +#define PIO_LED_DO_TEST_BENCH_WIRING 0 +#define PIO_LED_DRIVEN_SIM_VALUE 0x0 +#define PIO_LED_EDGE_TYPE "NONE" +#define PIO_LED_FREQ 100000000u +#define PIO_LED_HAS_IN 0 +#define PIO_LED_HAS_OUT 1 +#define PIO_LED_HAS_TRI 0 +#define PIO_LED_IRQ -1 +#define PIO_LED_IRQ_INTERRUPT_CONTROLLER_ID -1 +#define PIO_LED_IRQ_TYPE "NONE" +#define PIO_LED_NAME "/dev/pio_led" +#define PIO_LED_RESET_VALUE 0x0 +#define PIO_LED_SPAN 32 +#define PIO_LED_TYPE "altera_avalon_pio" + + +/* + * pio_sw configuration + * + */ + +#define ALT_MODULE_CLASS_pio_sw altera_avalon_pio +#define PIO_SW_BASE 0x2001090 +#define PIO_SW_BIT_CLEARING_EDGE_REGISTER 0 +#define PIO_SW_BIT_MODIFYING_OUTPUT_REGISTER 0 +#define PIO_SW_CAPTURE 0 +#define PIO_SW_DATA_WIDTH 4 +#define PIO_SW_DO_TEST_BENCH_WIRING 0 +#define PIO_SW_DRIVEN_SIM_VALUE 0x0 +#define PIO_SW_EDGE_TYPE "NONE" +#define PIO_SW_FREQ 100000000u +#define PIO_SW_HAS_IN 1 +#define PIO_SW_HAS_OUT 0 +#define PIO_SW_HAS_TRI 0 +#define PIO_SW_IRQ -1 +#define PIO_SW_IRQ_INTERRUPT_CONTROLLER_ID -1 +#define PIO_SW_IRQ_TYPE "NONE" +#define PIO_SW_NAME "/dev/pio_sw" +#define PIO_SW_RESET_VALUE 0x0 +#define PIO_SW_SPAN 16 +#define PIO_SW_TYPE "altera_avalon_pio" + + +/* + * rs232_wifi configuration + * + */ + +#define ALT_MODULE_CLASS_rs232_wifi altera_up_avalon_rs232 +#define RS232_WIFI_BASE 0x20010b0 +#define RS232_WIFI_IRQ 6 +#define RS232_WIFI_IRQ_INTERRUPT_CONTROLLER_ID 0 +#define RS232_WIFI_NAME "/dev/rs232_wifi" +#define RS232_WIFI_SPAN 8 +#define RS232_WIFI_TYPE "altera_up_avalon_rs232" + + +/* + * sdram configuration + * + */ + +#define ALT_MODULE_CLASS_sdram altera_avalon_new_sdram_controller +#define SDRAM_BASE 0x1000000 +#define SDRAM_CAS_LATENCY 3 +#define SDRAM_CONTENTS_INFO "" +#define SDRAM_INIT_NOP_DELAY 0.0 +#define SDRAM_INIT_REFRESH_COMMANDS 8 +#define SDRAM_IRQ -1 +#define SDRAM_IRQ_INTERRUPT_CONTROLLER_ID -1 +#define SDRAM_IS_INITIALIZED 1 +#define SDRAM_NAME "/dev/sdram" +#define SDRAM_POWERUP_DELAY 200.0 +#define SDRAM_REFRESH_PERIOD 7.8125 +#define SDRAM_REGISTER_DATA_IN 1 +#define SDRAM_SDRAM_ADDR_WIDTH 0x17 +#define SDRAM_SDRAM_BANK_WIDTH 2 +#define SDRAM_SDRAM_COL_WIDTH 8 +#define SDRAM_SDRAM_DATA_WIDTH 16 +#define SDRAM_SDRAM_NUM_BANKS 4 +#define SDRAM_SDRAM_NUM_CHIPSELECTS 1 +#define SDRAM_SDRAM_ROW_WIDTH 13 +#define SDRAM_SHARED_DATA 0 +#define SDRAM_SIM_MODEL_BASE 0 +#define SDRAM_SPAN 16777216 +#define SDRAM_STARVATION_INDICATOR 0 +#define SDRAM_TRISTATE_BRIDGE_SLAVE "" +#define SDRAM_TYPE "altera_avalon_new_sdram_controller" +#define SDRAM_T_AC 5.5 +#define SDRAM_T_MRD 3 +#define SDRAM_T_RCD 20.0 +#define SDRAM_T_RFC 70.0 +#define SDRAM_T_RP 20.0 +#define SDRAM_T_WR 14.0 + + +/* + * sys_clk_timer configuration + * + */ + +#define ALT_MODULE_CLASS_sys_clk_timer altera_avalon_timer +#define SYS_CLK_TIMER_ALWAYS_RUN 0 +#define SYS_CLK_TIMER_BASE 0x2001060 +#define SYS_CLK_TIMER_COUNTER_SIZE 32 +#define SYS_CLK_TIMER_FIXED_PERIOD 0 +#define SYS_CLK_TIMER_FREQ 100000000u +#define SYS_CLK_TIMER_IRQ 0 +#define SYS_CLK_TIMER_IRQ_INTERRUPT_CONTROLLER_ID 0 +#define SYS_CLK_TIMER_LOAD_VALUE 99999ull +#define SYS_CLK_TIMER_MULT 0.0010 +#define SYS_CLK_TIMER_NAME "/dev/sys_clk_timer" +#define SYS_CLK_TIMER_PERIOD 1 +#define SYS_CLK_TIMER_PERIOD_UNITS "ms" +#define SYS_CLK_TIMER_RESET_OUTPUT 0 +#define SYS_CLK_TIMER_SNAPSHOT 1 +#define SYS_CLK_TIMER_SPAN 32 +#define SYS_CLK_TIMER_TICKS_PER_SEC 1000u +#define SYS_CLK_TIMER_TIMEOUT_PULSE_OUTPUT 0 +#define SYS_CLK_TIMER_TYPE "altera_avalon_timer" + + +/* + * sysid configuration + * + */ + +#define ALT_MODULE_CLASS_sysid altera_avalon_sysid_qsys +#define SYSID_BASE 0x20010c0 +#define SYSID_ID 0 +#define SYSID_IRQ -1 +#define SYSID_IRQ_INTERRUPT_CONTROLLER_ID -1 +#define SYSID_NAME "/dev/sysid" +#define SYSID_SPAN 8 +#define SYSID_TIMESTAMP 1393886764 +#define SYSID_TYPE "altera_avalon_sysid_qsys" + + +/* + * uart_mc configuration + * + */ + +#define ALT_MODULE_CLASS_uart_mc altera_avalon_uart +#define UART_MC_BASE 0x2001000 +#define UART_MC_BAUD 9600 +#define UART_MC_DATA_BITS 8 +#define UART_MC_FIXED_BAUD 1 +#define UART_MC_FREQ 100000000u +#define UART_MC_IRQ 5 +#define UART_MC_IRQ_INTERRUPT_CONTROLLER_ID 0 +#define UART_MC_NAME "/dev/uart_mc" +#define UART_MC_PARITY 'N' +#define UART_MC_SIM_CHAR_STREAM "" +#define UART_MC_SIM_TRUE_BAUD 0 +#define UART_MC_SPAN 32 +#define UART_MC_STOP_BITS 1 +#define UART_MC_SYNC_REG_DEPTH 2 +#define UART_MC_TYPE "altera_avalon_uart" +#define UART_MC_USE_CTS_RTS 0 +#define UART_MC_USE_EOP_REGISTER 0 + + +/* + * uart_wifi configuration + * + */ + +#define ALT_MODULE_CLASS_uart_wifi altera_avalon_uart +#define UART_WIFI_BASE 0x2001040 +#define UART_WIFI_BAUD 9600 +#define UART_WIFI_DATA_BITS 8 +#define UART_WIFI_FIXED_BAUD 0 +#define UART_WIFI_FREQ 100000000u +#define UART_WIFI_IRQ 4 +#define UART_WIFI_IRQ_INTERRUPT_CONTROLLER_ID 0 +#define UART_WIFI_NAME "/dev/uart_wifi" +#define UART_WIFI_PARITY 'N' +#define UART_WIFI_SIM_CHAR_STREAM "" +#define UART_WIFI_SIM_TRUE_BAUD 0 +#define UART_WIFI_SPAN 32 +#define UART_WIFI_STOP_BITS 1 +#define UART_WIFI_SYNC_REG_DEPTH 2 +#define UART_WIFI_TYPE "altera_avalon_uart" +#define UART_WIFI_USE_CTS_RTS 0 +#define UART_WIFI_USE_EOP_REGISTER 0 + + +/* + * ucosii configuration + * + */ + +#define OS_ARG_CHK_EN 1 +#define OS_CPU_HOOKS_EN 1 +#define OS_DEBUG_EN 1 +#define OS_EVENT_NAME_SIZE 32 +#define OS_FLAGS_NBITS 16 +#define OS_FLAG_ACCEPT_EN 1 +#define OS_FLAG_DEL_EN 1 +#define OS_FLAG_EN 1 +#define OS_FLAG_NAME_SIZE 32 +#define OS_FLAG_QUERY_EN 1 +#define OS_FLAG_WAIT_CLR_EN 1 +#define OS_LOWEST_PRIO 20 +#define OS_MAX_EVENTS 60 +#define OS_MAX_FLAGS 20 +#define OS_MAX_MEM_PART 60 +#define OS_MAX_QS 20 +#define OS_MAX_TASKS 10 +#define OS_MBOX_ACCEPT_EN 1 +#define OS_MBOX_DEL_EN 1 +#define OS_MBOX_EN 1 +#define OS_MBOX_POST_EN 1 +#define OS_MBOX_POST_OPT_EN 1 +#define OS_MBOX_QUERY_EN 1 +#define OS_MEM_EN 1 +#define OS_MEM_NAME_SIZE 32 +#define OS_MEM_QUERY_EN 1 +#define OS_MUTEX_ACCEPT_EN 1 +#define OS_MUTEX_DEL_EN 1 +#define OS_MUTEX_EN 1 +#define OS_MUTEX_QUERY_EN 1 +#define OS_Q_ACCEPT_EN 1 +#define OS_Q_DEL_EN 1 +#define OS_Q_EN 1 +#define OS_Q_FLUSH_EN 1 +#define OS_Q_POST_EN 1 +#define OS_Q_POST_FRONT_EN 1 +#define OS_Q_POST_OPT_EN 1 +#define OS_Q_QUERY_EN 1 +#define OS_SCHED_LOCK_EN 1 +#define OS_SEM_ACCEPT_EN 1 +#define OS_SEM_DEL_EN 1 +#define OS_SEM_EN 1 +#define OS_SEM_QUERY_EN 1 +#define OS_SEM_SET_EN 1 +#define OS_TASK_CHANGE_PRIO_EN 1 +#define OS_TASK_CREATE_EN 1 +#define OS_TASK_CREATE_EXT_EN 1 +#define OS_TASK_DEL_EN 1 +#define OS_TASK_IDLE_STK_SIZE 512 +#define OS_TASK_NAME_SIZE 32 +#define OS_TASK_PROFILE_EN 1 +#define OS_TASK_QUERY_EN 1 +#define OS_TASK_STAT_EN 1 +#define OS_TASK_STAT_STK_CHK_EN 1 +#define OS_TASK_STAT_STK_SIZE 512 +#define OS_TASK_SUSPEND_EN 1 +#define OS_TASK_SW_HOOK_EN 1 +#define OS_TASK_TMR_PRIO 0 +#define OS_TASK_TMR_STK_SIZE 512 +#define OS_THREAD_SAFE_NEWLIB 1 +#define OS_TICKS_PER_SEC SYS_CLK_TIMER_TICKS_PER_SEC +#define OS_TICK_STEP_EN 1 +#define OS_TIME_DLY_HMSM_EN 1 +#define OS_TIME_DLY_RESUME_EN 1 +#define OS_TIME_GET_SET_EN 1 +#define OS_TIME_TICK_HOOK_EN 1 +#define OS_TMR_CFG_MAX 16 +#define OS_TMR_CFG_NAME_SIZE 16 +#define OS_TMR_CFG_TICKS_PER_SEC 10 +#define OS_TMR_CFG_WHEEL_SIZE 2 +#define OS_TMR_EN 0 + +#endif /* __SYSTEM_H_ */ diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0/.cproject b/MCandWifiTestDE0/Software/Archive/MCandWifiTestDE0/.cproject similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0/.cproject rename to MCandWifiTestDE0/Software/Archive/MCandWifiTestDE0/.cproject diff --git a/MCandWifiTestDE0/Software/Archive/MCandWifiTestDE0/.force_relink b/MCandWifiTestDE0/Software/Archive/MCandWifiTestDE0/.force_relink new file mode 100644 index 00000000..e69de29b diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0/.project b/MCandWifiTestDE0/Software/Archive/MCandWifiTestDE0/.project similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0/.project rename to MCandWifiTestDE0/Software/Archive/MCandWifiTestDE0/.project diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0/MCandWifiTestDE0.elf b/MCandWifiTestDE0/Software/Archive/MCandWifiTestDE0/MCandWifiTestDE0.elf similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0/MCandWifiTestDE0.elf rename to MCandWifiTestDE0/Software/Archive/MCandWifiTestDE0/MCandWifiTestDE0.elf diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0/MCandWifiTestDE0.map b/MCandWifiTestDE0/Software/Archive/MCandWifiTestDE0/MCandWifiTestDE0.map similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0/MCandWifiTestDE0.map rename to MCandWifiTestDE0/Software/Archive/MCandWifiTestDE0/MCandWifiTestDE0.map diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0/MCandWifiTestDE0.objdump b/MCandWifiTestDE0/Software/Archive/MCandWifiTestDE0/MCandWifiTestDE0.objdump similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0/MCandWifiTestDE0.objdump rename to MCandWifiTestDE0/Software/Archive/MCandWifiTestDE0/MCandWifiTestDE0.objdump diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0/Makefile b/MCandWifiTestDE0/Software/Archive/MCandWifiTestDE0/Makefile similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0/Makefile rename to MCandWifiTestDE0/Software/Archive/MCandWifiTestDE0/Makefile diff --git a/MCandWifiTestDE0/Software/Archive/MCandWifiTestDE0/SerialHandler.cpp b/MCandWifiTestDE0/Software/Archive/MCandWifiTestDE0/SerialHandler.cpp new file mode 100644 index 00000000..09aecfa9 --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCandWifiTestDE0/SerialHandler.cpp @@ -0,0 +1,31 @@ +/* + * SerialHandler.cpp + * + * Created on: 2014-03-01 + * Author: gongal + */ + +#include "SerialHandler.h" +#include "includes.h" +#include "altera_avalon_uart_regs.h" + +SerialHandler::SerialHandler() { + // TODO Auto-generated constructor stub + +} + +SerialHandler::~SerialHandler() { + // TODO Auto-generated destructor stub +} + +void SerialHandler::sendByteMC(char msg){ + IOWR_ALTERA_AVALON_UART_TXDATA(UART_MC_BASE, msg); +} + +void SerialHandler::sendDataWifi(char * msg, int length){ + int i; + for(i = 0; i +#include "includes.h" +#include "altera_avalon_pio_regs.h" +#include "altera_avalon_uart_regs.h" +#include "sys/alt_irq.h" +#include "alt_types.h" +#include "altera_up_avalon_rs232.h" +#include "altera_up_avalon_rs232_regs.h" +#include "SerialHandler.h" + + +/* Task stacks */ +#define TASK_STACKSIZE 2048 +OS_STK ir_task_stk[TASK_STACKSIZE]; +OS_STK wifi_task_stk[TASK_STACKSIZE]; +OS_STK mc_task_stk[TASK_STACKSIZE]; +/* Task priorities */ +#define IR_TASK_PRIORITY 1 +#define WIFI_TASK_PRIORITY 2 +#define MC_TASK_PRIORITY 2 + +#define SW_READ 1 +#define SW_WRITE 2 +#define WRITE_FIFO_EMPTY 0x80 +#define READ_FIFO_EMPTY 0x0 +OS_EVENT *SWQ; +OS_EVENT *RS232Q; +INT8U err; + + +/* Error status */ +#define OK 0 + +/* Message queues */ +#define WAIT_FOREVER 0 + +// ==== INFRARED ==== + +/* Infrared message queue */ +#define IR_MAX_MESSAGES 4 +int ir_messages[IR_MAX_MESSAGES]; +OS_EVENT *ir_queue; + +/* Infrared messages */ +// Together these avoid passing 0 to the queue (which is not allowed since queue messages cannot be null) +// and invert pushbutton input (since the pushbutton returns 0 when it is pushed down). +#define IR_QUEUE_SEND_BASE 1 // Use: IR_QUEUE_SEND_BASE + IORD +#define IR_QUEUE_RECEIVE_BASE 2 // Use: IR_QUEUE_RECEIVE_BASE - OSQPend + + +/* Interrupt service routine triggered whenever the status of the IR emitter pushbutton changes. */ +static void isr_on_ir_pushbutton(void * context) { + // Read the state of the pushbutton and post it to the queue. + //printf("Pressed\n"); + int message = IR_QUEUE_SEND_BASE + IORD_ALTERA_AVALON_PIO_DATA(PIO_KEY_LEFT_BASE); + OSQPost(ir_queue, (void*)message); + // Mask to mark the end of the ISR. + IOWR_ALTERA_AVALON_PIO_EDGE_CAP(PIO_KEY_LEFT_BASE, PIO_KEY_LEFT_BIT_CLEARING_EDGE_REGISTER); +} + +/* Controllers the IR emitter based on the value of the pushbutton. */ +void ir_task(void* pdata) +{ + INT8U err; + while (1) + { + // Read the value from the queue. + int status = IR_QUEUE_RECEIVE_BASE - (int)OSQPend(ir_queue, WAIT_FOREVER, &err); + if (err == OS_NO_ERR) { + // Print the result and send it to the emitter. + printf("IR: %d\n", status); + IOWR_ALTERA_AVALON_PIO_DATA(PIO_IR_EMITTER_BASE, status); + } + } +} + +// ==== WIFI + +#define WIFI_GUARD_TIME 1 + +void wifi_wait() { + OSTimeDlyHMSM(0, 0, WIFI_GUARD_TIME, 0); +} + +void wifi_write(char *message, int length) { + int i; + for (i = 0; i < length; i++) { + IOWR_ALTERA_AVALON_UART_TXDATA(UART_WIFI_BASE, message[i]); + } +} + +void wifi_read() { + //int status = IORD_ALTERA_AVALON_UART_STATUS(UART_WIFI_BASE); + //printf("Wifi status: %d\n", status); + char c = IORD_ALTERA_AVALON_UART_RXDATA(UART_WIFI_BASE); + + printf("Wifi: %c NE\n", c); +} + +void wifi_task(void *pdata) +{ + /*printf("Started wifi task\n"); + wifi_write("X", 1); + wifi_wait(); + wifi_write("+++", 3); + wifi_wait(); + wifi_read(); + wifi_wait(); + while(1){ + wifi_read(); + wifi_wait(); + }*/ + alt_u32 write_FIFO_space; + alt_u16 read_FIFO_used; + alt_u8 data_W8; + alt_u8 data_R8; + //int enter = 0; + alt_u8 p_error; + alt_up_rs232_dev* rs232_dev; + // open the RS232 UART port + rs232_dev = alt_up_rs232_open_dev("/dev/rs232_0"); + if (rs232_dev == NULL) + printf("Error: could not open RS232 UART\n"); + else + printf("Opened RS232 UART device\n"); + alt_up_rs232_disable_read_interrupt(rs232_dev); + data_W8 = 'X'; + alt_up_rs232_write_data(rs232_dev, data_W8); + OSTimeDlyHMSM(0, 0, 3, 0); + int i; + data_W8 = '+'; + for (i = 0; i<3; i++ ){ + write_FIFO_space = + alt_up_rs232_get_available_space_in_write_FIFO( + rs232_dev); + if (write_FIFO_space >= WRITE_FIFO_EMPTY) { + alt_up_rs232_write_data(rs232_dev, data_W8); + printf("write %c to RS232 UART\n", data_W8); + OSTimeDlyHMSM(0, 0, 1, 0); + } + } + alt_up_rs232_enable_read_interrupt(rs232_dev); + while(1){ + read_FIFO_used = alt_up_rs232_get_used_space_in_read_FIFO( + rs232_dev); + if (read_FIFO_used > READ_FIFO_EMPTY) { + printf("char stored in read_FIFO: %x\n", + read_FIFO_used); + alt_up_rs232_read_data(rs232_dev, &data_R8, &p_error); + printf("read %c from RS232 UART\n", data_R8); + } OSTimeDlyHMSM(0, 0, 1, 0); + } + /*while (1) { + int sw = (int) OSQPend(SWQ, 0, &err); + if (sw == SW_WRITE) { + alt_up_rs232_disable_read_interrupt(rs232_dev); + if (enter == 0) { + data_W8 = 'A'; + enter = 1; + } else if (enter == 1) { + data_W8 = '\n'; + enter = 0; + } write_FIFO_space = + alt_up_rs232_get_available_space_in_write_FIFO( + rs232_dev); + if (write_FIFO_space >= WRITE_FIFO_EMPTY) { + alt_up_rs232_write_data(rs232_dev, data_W8); + printf("write %c to RS232 UART\n", data_W8); + } OSTimeDlyHMSM(0, 0, 1, 0); + alt_up_rs232_enable_read_interrupt(rs232_dev); + } if ( + sw == SW_READ) { + read_FIFO_used = alt_up_rs232_get_used_space_in_read_FIFO( + rs232_dev); + if (read_FIFO_used > READ_FIFO_EMPTY) { + printf("char stored in read_FIFO: %x\n", + read_FIFO_used); + alt_up_rs232_read_data(rs232_dev, &data_R8, &p_error); + printf("read %c from RS232 UART\n", data_R8); + } OSTimeDlyHMSM(0, 0, 1, 0); + } + }*/ + +} + + + +// ==== MC + +void mc_stop(){ + SerialHandler *serial = new SerialHandler(); + //motor 1 + serial->sendByteMC(SERIAL_START_BYTE); + serial->sendByteMC(SERIAL_DEVICE_TYPE); + serial->sendByteMC(SERIAL_MOTOR2_FORWARD); + serial->sendByteMC(SERIAL_STOP_SPEED); + //motor 2 + serial->sendByteMC(SERIAL_START_BYTE); + serial->sendByteMC(SERIAL_DEVICE_TYPE); + serial->sendByteMC(SERIAL_MOTOR3_FORWARD); + serial->sendByteMC(SERIAL_STOP_SPEED); +} +/* + * Moves the rover forward enabling equal drive strength on both motors + */ +void mc_forward(){ + SerialHandler *serial = new SerialHandler(); + //motor 1 + serial->sendByteMC(SERIAL_START_BYTE); + serial->sendByteMC(SERIAL_DEVICE_TYPE); + serial->sendByteMC(SERIAL_MOTOR2_FORWARD); + serial->sendByteMC(SERIAL_CONST_SPEED); + //motor 2 + serial->sendByteMC(SERIAL_START_BYTE); + serial->sendByteMC(SERIAL_DEVICE_TYPE); + serial->sendByteMC(SERIAL_MOTOR3_FORWARD); + serial->sendByteMC(SERIAL_CONST_SPEED); + +} +/* + * Moves the rover backward enabling equal drive strength on both motors + */ +void mc_backward(){ + SerialHandler *serial = new SerialHandler(); + + //motor 1 + serial->sendByteMC(SERIAL_START_BYTE); + serial->sendByteMC(SERIAL_DEVICE_TYPE); + serial->sendByteMC(SERIAL_MOTOR2_BACKWARD); + serial->sendByteMC(SERIAL_CONST_SPEED); + //motor 2 + serial->sendByteMC(SERIAL_START_BYTE); + serial->sendByteMC(SERIAL_DEVICE_TYPE); + serial->sendByteMC(SERIAL_MOTOR3_BACKWARD); + serial->sendByteMC(SERIAL_CONST_SPEED); +} +/* + * Moves the rover left, enabling left drive strength higher than right + */ +void mc_left(){ + SerialHandler *serial = new SerialHandler(); + + //Turn Left by driving the left motor only + + //motor 1 + serial->sendByteMC(SERIAL_START_BYTE); + serial->sendByteMC(SERIAL_DEVICE_TYPE); + serial->sendByteMC(SERIAL_MOTOR2_FORWARD); + serial->sendByteMC(SERIAL_CONST_SPEED); + +} +/* + * Moves the rover right, enabling right drive strength higher than left + */ +void mc_right(){ + SerialHandler *serial = new SerialHandler(); + + //Turn Right by driving right motor only + + //motor 1 + serial->sendByteMC(SERIAL_START_BYTE); + serial->sendByteMC(SERIAL_DEVICE_TYPE); + serial->sendByteMC(SERIAL_MOTOR3_FORWARD); + serial->sendByteMC(SERIAL_CONST_SPEED); +} + +//====MotorContoller +void mc_task(void *pdata) +{ + printf("Started Motor task\n"); + //mc_configure(); + while(1){ + mc_forward(); + + } + +} + +// ==== GENERAL + +void queue_init() { + ir_queue = OSQCreate((void**)&ir_messages, IR_MAX_MESSAGES); +} + +/* The main function creates the LCD task, registers the edge counter polling interrupt, + * and starts the OS. */ +int main(void) +{ + int status; + // Initialize components. + queue_init(); + + // Create the IR task. + OSTaskCreateExt(ir_task, + NULL, + &ir_task_stk[TASK_STACKSIZE - 1], + IR_TASK_PRIORITY, + IR_TASK_PRIORITY, + ir_task_stk, + TASK_STACKSIZE, + NULL, + 0); + + // Create the Wifi task. + OSTaskCreateExt(wifi_task, + NULL, + &wifi_task_stk[TASK_STACKSIZE - 1], + WIFI_TASK_PRIORITY, + WIFI_TASK_PRIORITY, + wifi_task_stk, + TASK_STACKSIZE, + NULL, + 0); + + // Create the MC task. + OSTaskCreateExt(mc_task, + NULL, + &mc_task_stk[TASK_STACKSIZE - 1], + MC_TASK_PRIORITY, + MC_TASK_PRIORITY, + mc_task_stk, + TASK_STACKSIZE, + NULL, + 0); + + // Register the IR pushbutton interrupt. + /*status = alt_ic_isr_register(PIO_KEY_LEFT_IRQ_INTERRUPT_CONTROLLER_ID, + PIO_KEY_LEFT_IRQ, + isr_on_ir_pushbutton, + NULL, + NULL);*/ + + // Enable key interrupts. + IOWR_ALTERA_AVALON_PIO_IRQ_MASK(PIO_KEY_LEFT_BASE, PIO_KEY_LEFT_CAPTURE); + + // Start. + if (status == OK) { + OSStart(); + } + + return 0; +} + +/****************************************************************************** + * * + * License Agreement * + * * + * Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * + * All rights reserved. * + * * + * Permission is hereby granted, free of charge, to any person obtaining a * + * copy of this software and associated documentation files (the "Software"), * + * to deal in the Software without restriction, including without limitation * + * the rights to use, copy, modify, merge, publish, distribute, sublicense, * + * and/or sell copies of the Software, and to permit persons to whom the * + * Software is furnished to do so, subject to the following conditions: * + * * + * The above copyright notice and this permission notice shall be included in * + * all copies or substantial portions of the Software. * + * * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * + * DEALINGS IN THE SOFTWARE. * + * * + * This agreement shall be governed in all respects by the laws of the State * + * of California and by the laws of the United States of America. * + * Altera does not recommend, suggest or require that this reference design * + * file be used in conjunction or combination with any other product. * + ******************************************************************************/ diff --git a/MCandWifiTestDE0/Software/Archive/MCandWifiTestDE0/obj/default/.force_relink b/MCandWifiTestDE0/Software/Archive/MCandWifiTestDE0/obj/default/.force_relink new file mode 100644 index 00000000..e69de29b diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0/obj/default/SerialHandler.d b/MCandWifiTestDE0/Software/Archive/MCandWifiTestDE0/obj/default/SerialHandler.d similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0/obj/default/SerialHandler.d rename to MCandWifiTestDE0/Software/Archive/MCandWifiTestDE0/obj/default/SerialHandler.d diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0/obj/default/SerialHandler.o b/MCandWifiTestDE0/Software/Archive/MCandWifiTestDE0/obj/default/SerialHandler.o similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0/obj/default/SerialHandler.o rename to MCandWifiTestDE0/Software/Archive/MCandWifiTestDE0/obj/default/SerialHandler.o diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0/obj/default/main.d b/MCandWifiTestDE0/Software/Archive/MCandWifiTestDE0/obj/default/main.d similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0/obj/default/main.d rename to MCandWifiTestDE0/Software/Archive/MCandWifiTestDE0/obj/default/main.d diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0/obj/default/main.o b/MCandWifiTestDE0/Software/Archive/MCandWifiTestDE0/obj/default/main.o similarity index 100% rename from MCandWifiTestDE0/Software/MCandWifiTestDE0/obj/default/main.o rename to MCandWifiTestDE0/Software/Archive/MCandWifiTestDE0/obj/default/main.o diff --git a/MCandWifiTestDE0/Software/Archive/MCandWifiTestDE0/readme.txt b/MCandWifiTestDE0/Software/Archive/MCandWifiTestDE0/readme.txt new file mode 100644 index 00000000..49e8390f --- /dev/null +++ b/MCandWifiTestDE0/Software/Archive/MCandWifiTestDE0/readme.txt @@ -0,0 +1,7 @@ +Readme - Hello MicroC/OS-II Hello Software Example + +Hello_uosii is a simple hello world program running MicroC/OS-II. The +purpose of the design is to be a very simple application that just +demonstrates MicroC/OS-II running on NIOS II. The design doesn't account +for issues such as checking system call return codes. etc. + diff --git a/MCandWifiTestDE0/Software/MCTest/.cproject b/MCandWifiTestDE0/Software/MCTest/.cproject new file mode 100644 index 00000000..60e18a6c --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest/.cproject @@ -0,0 +1,508 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + make + + mem_init_install + true + false + false + + + make + + mem_init_generate + true + false + false + + + make + + help + true + false + false + + + + diff --git a/MCandWifiTestDE0/Software/MCTest/.force_relink b/MCandWifiTestDE0/Software/MCTest/.force_relink new file mode 100644 index 00000000..e69de29b diff --git a/MCandWifiTestDE0/Software/MCTest/.project b/MCandWifiTestDE0/Software/MCTest/.project new file mode 100644 index 00000000..40854e92 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest/.project @@ -0,0 +1,96 @@ + + + MCTest + + + + + + com.altera.sbtgui.project.makefileBuilder + + + + + com.altera.sbtgui.project.makefileBuilder + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + + + + org.eclipse.cdt.make.core.buildCommand + make + + + org.eclipse.cdt.make.core.buildLocation + ${workspace_loc://MCTest} + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + org.eclipse.cdt.core.ccnature + com.altera.sbtgui.project.SBTGUINature + com.altera.sbtgui.project.SBTGUIAppNature + com.altera.sbtgui.project.SBTGUIManagedNature + + diff --git a/MCandWifiTestDE0/Software/MCTest/MCTest.elf b/MCandWifiTestDE0/Software/MCTest/MCTest.elf new file mode 100644 index 00000000..88e5dc8b Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest/MCTest.elf differ diff --git a/MCandWifiTestDE0/Software/MCTest/MCTest.map b/MCandWifiTestDE0/Software/MCTest/MCTest.map new file mode 100644 index 00000000..c74964d5 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest/MCTest.map @@ -0,0 +1,3339 @@ +Archive member included because of file (symbol) + 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+c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_lt_df.o) + c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-vfprintf.o) (__ltdf2) +c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_si_to_df.o) + c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-dtoa.o) (__floatsidf) +c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_df_to_si.o) + c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-dtoa.o) (__fixdfsi) +c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_thenan_df.o) + c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_addsub_df.o) (__thenan_df) +c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_usi_to_df.o) + c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-dtoa.o) (__floatunsidf) +c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(lib2-divmod.o) + c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-vfprintf.o) (__divsi3) +c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_muldi3.o) + c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_mul_df.o) (__muldi3) +c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_clz.o) + c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_udivdi3.o) (__clz_tab) +c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_clzsi2.o) + c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_si_to_df.o) (__clzsi2) +c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_pack_df.o) + c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_addsub_df.o) (__pack_d) +c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_unpack_df.o) + c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_addsub_df.o) (__unpack_d) +c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_fpcmp_parts_df.o) + c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_eq_df.o) (__fpcmp_parts_d) +../MCTest_bsp/\libucosii_bsp.a(alt_close.o) + c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-closer.o) (close) +../MCTest_bsp/\libucosii_bsp.a(alt_dev.o) + ../MCTest_bsp/\libucosii_bsp.a(alt_close.o) (alt_fd_list) +../MCTest_bsp/\libucosii_bsp.a(alt_errno.o) + ../MCTest_bsp/\libucosii_bsp.a(alt_close.o) (alt_errno) +../MCTest_bsp/\libucosii_bsp.a(alt_exit.o) + c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-abort.o) (_exit) +../MCTest_bsp/\libucosii_bsp.a(alt_fstat.o) + c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-fstatr.o) (fstat) +../MCTest_bsp/\libucosii_bsp.a(alt_getpid.o) + c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-signalr.o) (getpid) +../MCTest_bsp/\libucosii_bsp.a(alt_isatty.o) + c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-isattyr.o) (isatty) +../MCTest_bsp/\libucosii_bsp.a(alt_kill.o) + c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-signalr.o) (kill) +../MCTest_bsp/\libucosii_bsp.a(alt_load.o) + ../MCTest_bsp//obj/HAL/src/crt0.o (alt_load) +../MCTest_bsp/\libucosii_bsp.a(alt_lseek.o) + c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-lseekr.o) (lseek) +../MCTest_bsp/\libucosii_bsp.a(alt_main.o) + ../MCTest_bsp//obj/HAL/src/crt0.o (alt_main) +../MCTest_bsp/\libucosii_bsp.a(alt_read.o) + c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-readr.o) (read) +../MCTest_bsp/\libucosii_bsp.a(alt_release_fd.o) + ../MCTest_bsp/\libucosii_bsp.a(alt_close.o) (alt_release_fd) +../MCTest_bsp/\libucosii_bsp.a(alt_sbrk.o) + c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-sbrkr.o) (sbrk) +../MCTest_bsp/\libucosii_bsp.a(alt_write.o) + c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-writer.o) (write) +../MCTest_bsp/\libucosii_bsp.a(alt_env_lock.o) + ../MCTest_bsp/\libucosii_bsp.a(alt_main.o) (alt_envsem) +../MCTest_bsp/\libucosii_bsp.a(alt_malloc_lock.o) + c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-mallocr.o) (__malloc_lock) +../MCTest_bsp/\libucosii_bsp.a(os_core.o) + ../MCTest_bsp/\libucosii_bsp.a(alt_main.o) (OSInit) +../MCTest_bsp/\libucosii_bsp.a(os_dbg.o) + ../MCTest_bsp/\libucosii_bsp.a(os_core.o) (OSDebugInit) +../MCTest_bsp/\libucosii_bsp.a(os_flag.o) + ../MCTest_bsp/\libucosii_bsp.a(os_core.o) (OS_FlagInit) +../MCTest_bsp/\libucosii_bsp.a(os_mem.o) + ../MCTest_bsp/\libucosii_bsp.a(os_core.o) (OS_MemInit) +../MCTest_bsp/\libucosii_bsp.a(os_q.o) + obj/default/main.o (OSQCreate) +../MCTest_bsp/\libucosii_bsp.a(os_sem.o) + ../MCTest_bsp/\libucosii_bsp.a(alt_main.o) (OSSemCreate) +../MCTest_bsp/\libucosii_bsp.a(os_task.o) + obj/default/main.o (OSTaskCreateExt) +../MCTest_bsp/\libucosii_bsp.a(os_time.o) + ../MCTest_bsp/\libucosii_bsp.a(os_core.o) (OSTimeDly) +../MCTest_bsp/\libucosii_bsp.a(alt_sys_init.o) + ../MCTest_bsp/\libucosii_bsp.a(alt_main.o) (alt_irq_init) +../MCTest_bsp/\libucosii_bsp.a(altera_avalon_jtag_uart_fd.o) + ../MCTest_bsp/\libucosii_bsp.a(alt_sys_init.o) (altera_avalon_jtag_uart_read_fd) +../MCTest_bsp/\libucosii_bsp.a(altera_avalon_jtag_uart_init.o) + ../MCTest_bsp/\libucosii_bsp.a(alt_sys_init.o) (altera_avalon_jtag_uart_init) +../MCTest_bsp/\libucosii_bsp.a(altera_avalon_jtag_uart_ioctl.o) + ../MCTest_bsp/\libucosii_bsp.a(altera_avalon_jtag_uart_fd.o) (altera_avalon_jtag_uart_ioctl) +../MCTest_bsp/\libucosii_bsp.a(altera_avalon_jtag_uart_read.o) + ../MCTest_bsp/\libucosii_bsp.a(altera_avalon_jtag_uart_fd.o) (altera_avalon_jtag_uart_read) +../MCTest_bsp/\libucosii_bsp.a(altera_avalon_jtag_uart_write.o) + ../MCTest_bsp/\libucosii_bsp.a(altera_avalon_jtag_uart_fd.o) (altera_avalon_jtag_uart_write) +../MCTest_bsp/\libucosii_bsp.a(altera_avalon_timer_sc.o) + ../MCTest_bsp/\libucosii_bsp.a(alt_sys_init.o) (alt_avalon_timer_sc_init) +../MCTest_bsp/\libucosii_bsp.a(altera_avalon_uart_fd.o) + ../MCTest_bsp/\libucosii_bsp.a(alt_sys_init.o) (altera_avalon_uart_read_fd) +../MCTest_bsp/\libucosii_bsp.a(altera_avalon_uart_init.o) + ../MCTest_bsp/\libucosii_bsp.a(alt_sys_init.o) (altera_avalon_uart_init) +../MCTest_bsp/\libucosii_bsp.a(altera_avalon_uart_read.o) + ../MCTest_bsp/\libucosii_bsp.a(altera_avalon_uart_fd.o) (altera_avalon_uart_read) +../MCTest_bsp/\libucosii_bsp.a(altera_avalon_uart_write.o) + ../MCTest_bsp/\libucosii_bsp.a(altera_avalon_uart_fd.o) (altera_avalon_uart_write) +../MCTest_bsp/\libucosii_bsp.a(altera_up_avalon_rs232.o) + ../MCTest_bsp/\libucosii_bsp.a(alt_sys_init.o) (alt_up_rs232_read_fd) +../MCTest_bsp/\libucosii_bsp.a(alt_alarm_start.o) + ../MCTest_bsp/\libucosii_bsp.a(altera_avalon_jtag_uart_init.o) (alt_alarm_start) +../MCTest_bsp/\libucosii_bsp.a(alt_dcache_flush_all.o) + ../MCTest_bsp/\libucosii_bsp.a(alt_load.o) (alt_dcache_flush_all) +../MCTest_bsp/\libucosii_bsp.a(alt_dev_llist_insert.o) + ../MCTest_bsp/\libucosii_bsp.a(alt_sys_init.o) (alt_dev_llist_insert) +../MCTest_bsp/\libucosii_bsp.a(alt_do_ctors.o) + ../MCTest_bsp/\libucosii_bsp.a(alt_main.o) (_do_ctors) +../MCTest_bsp/\libucosii_bsp.a(alt_do_dtors.o) + ../MCTest_bsp/\libucosii_bsp.a(alt_main.o) (_do_dtors) +../MCTest_bsp/\libucosii_bsp.a(alt_find_dev.o) + ../MCTest_bsp/\libucosii_bsp.a(altera_up_avalon_rs232.o) (alt_find_dev) +../MCTest_bsp/\libucosii_bsp.a(alt_icache_flush_all.o) + ../MCTest_bsp/\libucosii_bsp.a(alt_load.o) (alt_icache_flush_all) +../MCTest_bsp/\libucosii_bsp.a(alt_io_redirect.o) + ../MCTest_bsp/\libucosii_bsp.a(alt_main.o) (alt_io_redirect) +../MCTest_bsp/\libucosii_bsp.a(alt_irq_register.o) + ../MCTest_bsp/\libucosii_bsp.a(altera_avalon_jtag_uart_init.o) (alt_irq_register) +../MCTest_bsp/\libucosii_bsp.a(alt_irq_vars.o) + ../MCTest_bsp/\libucosii_bsp.a(alt_irq_register.o) (alt_irq_active) +../MCTest_bsp/\libucosii_bsp.a(alt_open.o) + ../MCTest_bsp/\libucosii_bsp.a(alt_io_redirect.o) (open) +../MCTest_bsp/\libucosii_bsp.a(alt_tick.o) + ../MCTest_bsp/\libucosii_bsp.a(altera_avalon_jtag_uart_init.o) (_alt_tick_rate) +../MCTest_bsp/\libucosii_bsp.a(altera_nios2_qsys_irq.o) + ../MCTest_bsp/\libucosii_bsp.a(alt_sys_init.o) (altera_nios2_qsys_irq_init) +../MCTest_bsp/\libucosii_bsp.a(os_cpu_a.o) + ../MCTest_bsp/\libucosii_bsp.a(os_core.o) (OSIntCtxSw) +../MCTest_bsp/\libucosii_bsp.a(os_cpu_c.o) + ../MCTest_bsp/\libucosii_bsp.a(os_task.o) (OSTaskStkInit) +../MCTest_bsp/\libucosii_bsp.a(alt_find_file.o) + ../MCTest_bsp/\libucosii_bsp.a(alt_open.o) (alt_find_file) +../MCTest_bsp/\libucosii_bsp.a(alt_get_fd.o) + ../MCTest_bsp/\libucosii_bsp.a(alt_open.o) (alt_get_fd) +../MCTest_bsp/\libucosii_bsp.a(alt_icache_flush.o) + ../MCTest_bsp/\libucosii_bsp.a(alt_icache_flush_all.o) (alt_icache_flush) +../MCTest_bsp/\libucosii_bsp.a(alt_irq_entry.o) + ../MCTest_bsp/\libucosii_bsp.a(alt_irq_register.o) (alt_irq_entry) +../MCTest_bsp/\libucosii_bsp.a(alt_irq_handler.o) + ../MCTest_bsp/\libucosii_bsp.a(alt_irq_register.o) (alt_irq_handler) +../MCTest_bsp/\libucosii_bsp.a(alt_exception_entry.o) + ../MCTest_bsp/\libucosii_bsp.a(alt_irq_entry.o) (alt_exception) +c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-atexit.o) + ../MCTest_bsp/\libucosii_bsp.a(alt_main.o) (atexit) +c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-exit.o) + ../MCTest_bsp/\libucosii_bsp.a(alt_main.o) (exit) +c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-memcmp.o) + ../MCTest_bsp/\libucosii_bsp.a(alt_find_dev.o) (memcmp) +c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-__atexit.o) + c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-atexit.o) (__register_exitproc) +c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-__call_atexit.o) + c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-exit.o) (__call_exitprocs) + +Allocating common symbols +Common symbol size file + +alt_irq 0x100 ../MCTest_bsp/\libucosii_bsp.a(alt_irq_handler.o) +OSLockNesting 0x1 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +OSRunning 0x1 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +OSIdleCtr 0x4 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +OSPrioHighRdy 0x1 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +errno 0x4 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-int_errno.o) +alt_heapsem 0x4 ../MCTest_bsp/\libucosii_bsp.a(alt_malloc_lock.o) +OSFlagTbl 0x370 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +OSPrioCur 0x1 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +OSTCBList 0x4 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +alt_fd_list_lock 0x4 ../MCTest_bsp/\libucosii_bsp.a(alt_dev.o) +OSMemTbl 0xc30 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +OSTickStepState 0x1 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +OSTaskStatStk 0x800 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +OSCtxSwCtr 0x4 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +OSIdleCtrMax 0x4 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +OSTCBFreeList 0x4 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +OSCPUUsage 0x1 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +OSTaskCtr 0x1 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +OSMemFreeList 0x4 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +OSQTbl 0x1e0 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +OSTCBHighRdy 0x4 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +OSQFreeList 0x4 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +OSRdyGrp 0x1 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +_atexit0 0x190 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-atexit.o) +OSRdyTbl 0x3 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +OSEventFreeList 0x4 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +OSIntNesting 0x1 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +OSTCBCur 0x4 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +OSTime 0x4 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +OSTaskIdleStk 0x800 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +OSEventTbl 0xb40 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +OSTCBTbl 0x510 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +OSFlagFreeList 0x4 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +OSStatRdy 0x1 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +OSTCBPrioTbl 0x54 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) +alt_envsem 0x4 ../MCTest_bsp/\libucosii_bsp.a(alt_env_lock.o) +OSIdleCtrRun 0x4 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) + +Discarded input sections + + .group 0x00000000 0x8 obj/default/MotorHandler.o + .group 0x00000000 0x8 obj/default/MotorHandler.o + .group 0x00000000 0x8 obj/default/MotorHandler.o + .group 0x00000000 0x8 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(class_type_info.o) + .group 0x00000000 0x8 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(class_type_info.o) + .group 0x00000000 0x8 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(class_type_info.o) + .group 0x00000000 0x8 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(si_class_type_info.o) + .group 0x00000000 0x8 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(si_class_type_info.o) + .group 0x00000000 0x8 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(si_class_type_info.o) + .group 0x00000000 0x8 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(tinfo.o) + .group 0x00000000 0x8 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(tinfo.o) + .group 0x00000000 0x8 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(tinfo.o) + .group 0x00000000 0x8 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(eh_exception.o) + .group 0x00000000 0x8 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(eh_exception.o) + .group 0x00000000 0x8 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(eh_exception.o) + .group 0x00000000 0x8 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(eh_exception.o) + .group 0x00000000 0x8 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(eh_exception.o) + .group 0x00000000 0x8 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(eh_exception.o) + .group 0x00000000 0x8 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(new_handler.o) + .group 0x00000000 0x8 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(new_handler.o) + .group 0x00000000 0x8 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(new_handler.o) + +Memory Configuration + +Name Origin Length Attributes +reset 0x01000000 0x00000020 +sdram 0x01000020 0x00ffffe0 +*default* 0x00000000 0xffffffff + +Linker script and memory map + +LOAD ../MCTest_bsp//obj/HAL/src/crt0.o +LOAD obj/default/MotorHandler.o +LOAD obj/default/main.o +LOAD c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a +LOAD c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libm.a +LOAD c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a +START GROUP +LOAD c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a +LOAD c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a +LOAD ../MCTest_bsp/\libucosii_bsp.a +END GROUP +LOAD c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a + 0x01000000 __alt_mem_sdram = 0x1000000 + +.entry 0x01000000 0x20 + *(.entry) + .entry 0x01000000 0x20 ../MCTest_bsp//obj/HAL/src/crt0.o + 0x01000000 __reset + +.exceptions 0x01000020 0x1a0 + 0x01000020 PROVIDE (__ram_exceptions_start, ABSOLUTE (.)) + 0x01000020 . = ALIGN (0x20) + *(.irq) + *(.exceptions.entry.label) + .exceptions.entry.label + 0x01000020 0x0 ../MCTest_bsp/\libucosii_bsp.a(alt_irq_entry.o) + 0x01000020 alt_irq_entry + .exceptions.entry.label + 0x01000020 0x0 ../MCTest_bsp/\libucosii_bsp.a(alt_exception_entry.o) + 0x01000020 alt_exception + *(.exceptions.entry.user) + *(.exceptions.entry) + .exceptions.entry + 0x01000020 0x54 ../MCTest_bsp/\libucosii_bsp.a(alt_exception_entry.o) + *(.exceptions.irqtest.user) + *(.exceptions.irqtest) + .exceptions.irqtest + 0x01000074 0x10 ../MCTest_bsp/\libucosii_bsp.a(alt_irq_entry.o) + *(.exceptions.irqhandler.user) + *(.exceptions.irqhandler) + .exceptions.irqhandler + 0x01000084 0x4 ../MCTest_bsp/\libucosii_bsp.a(alt_irq_entry.o) + *(.exceptions.irqreturn.user) + *(.exceptions.irqreturn) + .exceptions.irqreturn + 0x01000088 0x4 ../MCTest_bsp/\libucosii_bsp.a(alt_irq_entry.o) + *(.exceptions.notirq.label) + .exceptions.notirq.label + 0x0100008c 0x0 ../MCTest_bsp/\libucosii_bsp.a(alt_irq_entry.o) + *(.exceptions.notirq.user) + *(.exceptions.notirq) + .exceptions.notirq + 0x0100008c 0x8 ../MCTest_bsp/\libucosii_bsp.a(alt_exception_entry.o) + *(.exceptions.soft.user) + *(.exceptions.soft) + *(.exceptions.unknown.user) + *(.exceptions.unknown) + .exceptions.unknown + 0x01000094 0x4 ../MCTest_bsp/\libucosii_bsp.a(alt_exception_entry.o) + *(.exceptions.exit.label) + .exceptions.exit.label + 0x01000098 0x0 ../MCTest_bsp/\libucosii_bsp.a(alt_irq_entry.o) + .exceptions.exit.label + 0x01000098 0x0 ../MCTest_bsp/\libucosii_bsp.a(alt_exception_entry.o) + *(.exceptions.exit.user) + *(.exceptions.exit) + .exceptions.exit + 0x01000098 0x54 ../MCTest_bsp/\libucosii_bsp.a(alt_exception_entry.o) + *(.exceptions) + .exceptions 0x010000ec 0xd4 ../MCTest_bsp/\libucosii_bsp.a(alt_irq_handler.o) + 0x010000ec alt_irq_handler + 0x010001c0 PROVIDE (__ram_exceptions_end, ABSOLUTE (.)) + 0x01000020 PROVIDE (__flash_exceptions_start, LOADADDR (.exceptions)) + +.text 0x010001c0 0x18a14 + 0x010001c0 PROVIDE (stext, ABSOLUTE (.)) + *(.interp) + *(.hash) + *(.dynsym) + *(.dynstr) + *(.gnu.version) + *(.gnu.version_d) + *(.gnu.version_r) + *(.rel.init) + *(.rela.init) + *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) + *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) + *(.rel.fini) + *(.rela.fini) + *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) + *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) + *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) + *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) + *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) + *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) + *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) + *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) + *(.rel.ctors) + *(.rela.ctors) + *(.rel.dtors) + *(.rela.dtors) + *(.rel.got) + *(.rela.got) + *(.rel.sdata .rel.sdata.* .rel.gnu.linkonce.s.*) + *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*) + *(.rel.sbss .rel.sbss.* .rel.gnu.linkonce.sb.*) + *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*) + *(.rel.sdata2 .rel.sdata2.* .rel.gnu.linkonce.s2.*) + *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*) + *(.rel.sbss2 .rel.sbss2.* .rel.gnu.linkonce.sb2.*) + *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*) + *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) + *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) + *(.rel.plt) + *(.rela.plt) + *(.rel.dyn) + *(.init) + *(.plt) + *(.text .stub .text.* .gnu.linkonce.t.*) + .text 0x010001c0 0x4c ../MCTest_bsp//obj/HAL/src/crt0.o + 0x010001c0 _start + .text 0x0100020c 0x3cc obj/default/MotorHandler.o + 0x0100020c MotorHandler::MotorHandler() + 0x0100023c MotorHandler::MotorHandler() + 0x0100026c MotorHandler::sendByteMC(char) + 0x010002a0 MotorHandler::mc_stop() + 0x01000328 MotorHandler::mc_right() + 0x01000380 MotorHandler::mc_left() + 0x010003d8 MotorHandler::mc_backward() + 0x01000460 MotorHandler::mc_forward() + 0x010004e8 MotorHandler::~MotorHandler() + 0x01000538 MotorHandler::~MotorHandler() + 0x01000588 MotorHandler::~MotorHandler() + .text 0x010005d8 0x4b4 obj/default/main.o + 0x01000734 wifi_write(char*, int) + 0x010007a4 queue_init() + 0x010007dc main + 0x010008e8 wifi_wait() + 0x01000920 mc_task(void*) + 0x0100096c wifi_read() + 0x010009d0 wifi_task(void*) + 0x01000a20 ir_task(void*) + .text 0x01000a8c 0x1bc c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(class_type_info.o) + 0x01000a8c __cxxabiv1::__class_type_info::__do_upcast(__cxxabiv1::__class_type_info const*, void**) const + 0x01000af8 __cxxabiv1::__class_type_info::__do_find_public_src(long, void const*, __cxxabiv1::__class_type_info const*, void const*) const + 0x01000b18 __cxxabiv1::__class_type_info::~__class_type_info() + 0x01000b4c __cxxabiv1::__class_type_info::~__class_type_info() + 0x01000b5c __cxxabiv1::__class_type_info::~__class_type_info() + 0x01000b6c __cxxabiv1::__class_type_info::__do_catch(std::type_info const*, void**, unsigned int) const + 0x01000bcc __cxxabiv1::__class_type_info::__do_upcast(__cxxabiv1::__class_type_info const*, void const*, __cxxabiv1::__class_type_info::__upcast_result&) const + 0x01000bfc __cxxabiv1::__class_type_info::__do_dyncast(long, __cxxabiv1::__class_type_info::__sub_kind, __cxxabiv1::__class_type_info const*, void const*, __cxxabiv1::__class_type_info const*, void const*, __cxxabiv1::__class_type_info::__dyncast_result&) const + .text 0x01000c48 0xbec c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(eh_personality.o) + 0x010011d4 __cxa_call_unexpected + 0x01001354 __gxx_personality_sj0 + .text 0x01001834 0x10c c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(eh_terminate.o) + 0x01001834 std::set_terminate(void (*)()) + 0x01001848 std::set_unexpected(void (*)()) + 0x0100185c __cxxabiv1::__terminate(void (*)()) + 0x01001900 std::terminate() + 0x01001918 __cxxabiv1::__unexpected(void (*)()) + 0x01001928 std::unexpected() + .text 0x01001940 0x0 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(eh_term_handler.o) + .text 0x01001940 0x1e4 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(eh_catch.o) + 0x01001940 __cxa_get_exception_ptr + 0x01001948 std::uncaught_exception() + 0x01001968 __cxa_end_catch + 0x01001a0c __cxa_begin_catch + .text 0x01001b24 0xc c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(del_op.o) + 0x01001b24 operator delete(void*) + .text 0x01001b30 0x148 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(eh_throw.o) + 0x01001b30 __cxa_rethrow + 0x01001ba4 __cxa_throw + .text 0x01001c78 0x1c8 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(si_class_type_info.o) + 0x01001c78 __cxxabiv1::__si_class_type_info::__do_upcast(__cxxabiv1::__class_type_info const*, void const*, __cxxabiv1::__class_type_info::__upcast_result&) const + 0x01001cf0 __cxxabiv1::__si_class_type_info::~__si_class_type_info() + 0x01001d24 __cxxabiv1::__si_class_type_info::~__si_class_type_info() + 0x01001d34 __cxxabiv1::__si_class_type_info::~__si_class_type_info() + 0x01001d44 __cxxabiv1::__si_class_type_info::__do_find_public_src(long, void const*, __cxxabiv1::__class_type_info const*, void const*) const + 0x01001d78 __cxxabiv1::__si_class_type_info::__do_dyncast(long, __cxxabiv1::__class_type_info::__sub_kind, __cxxabiv1::__class_type_info const*, void const*, __cxxabiv1::__class_type_info const*, void const*, __cxxabiv1::__class_type_info::__dyncast_result&) const + .text 0x01001e40 0x58 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(tinfo.o) + 0x01001e40 std::type_info::__is_pointer_p() const + 0x01001e48 std::type_info::__is_function_p() const + 0x01001e50 std::type_info::__do_catch(std::type_info const*, void**, unsigned int) const + 0x01001e60 std::type_info::__do_upcast(__cxxabiv1::__class_type_info const*, void**) const + 0x01001e68 std::type_info::~type_info() + 0x01001e78 std::type_info::~type_info() + 0x01001e88 std::type_info::~type_info() + .text 0x01001e98 0x174 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(eh_alloc.o) + 0x01001e98 __cxa_free_exception + 0x01001ed8 __cxa_allocate_exception + .text 0x0100200c 0x100 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(new_op.o) + 0x0100200c operator new(unsigned long) + .text 0x0100210c 0x94 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c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_ge_df.o) + 0x0100b684 __gedf2 + .text 0x0100b70c 0x88 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_lt_df.o) + 0x0100b70c __ltdf2 + .text 0x0100b794 0xf8 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_si_to_df.o) + 0x0100b794 __floatsidf + .text 0x0100b88c 0xd8 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_df_to_si.o) + 0x0100b88c __fixdfsi + .text 0x0100b964 0x0 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_thenan_df.o) + .text 0x0100b964 0x194 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_usi_to_df.o) + 0x0100b964 __floatunsidf + .text 0x0100baf8 0x14c c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(lib2-divmod.o) + 0x0100bb74 __divsi3 + 0x0100bbd4 __modsi3 + 0x0100bc34 __udivsi3 + 0x0100bc3c __umodsi3 + .text 0x0100bc44 0x98 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_muldi3.o) + 0x0100bc44 __muldi3 + .text 0x0100bcdc 0x0 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_clz.o) + .text 0x0100bcdc 0x80 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_clzsi2.o) + 0x0100bcdc __clzsi2 + .text 0x0100bd5c 0x314 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_pack_df.o) + 0x0100bd5c __pack_d + .text 0x0100c070 0x138 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_unpack_df.o) + 0x0100c070 __unpack_d + .text 0x0100c1a8 0xc8 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_fpcmp_parts_df.o) + 0x0100c1a8 __fpcmp_parts_d + .text 0x0100c270 0x15c ../MCTest_bsp/\libucosii_bsp.a(alt_close.o) + 0x0100c270 close + .text 0x0100c3cc 0x2c ../MCTest_bsp/\libucosii_bsp.a(alt_dev.o) + .text 0x0100c3f8 0x0 ../MCTest_bsp/\libucosii_bsp.a(alt_errno.o) + .text 0x0100c3f8 0x6c ../MCTest_bsp/\libucosii_bsp.a(alt_exit.o) + 0x0100c438 _exit + .text 0x0100c464 0x134 ../MCTest_bsp/\libucosii_bsp.a(alt_fstat.o) + 0x0100c464 fstat + .text 0x0100c598 0x20 ../MCTest_bsp/\libucosii_bsp.a(alt_getpid.o) + 0x0100c598 getpid + .text 0x0100c5b8 0x120 ../MCTest_bsp/\libucosii_bsp.a(alt_isatty.o) + 0x0100c5b8 isatty + .text 0x0100c6d8 0x1a0 ../MCTest_bsp/\libucosii_bsp.a(alt_kill.o) + 0x0100c6d8 kill + .text 0x0100c878 0xec ../MCTest_bsp/\libucosii_bsp.a(alt_load.o) + 0x0100c878 alt_load + .text 0x0100c964 0x150 ../MCTest_bsp/\libucosii_bsp.a(alt_lseek.o) + 0x0100c964 lseek + .text 0x0100cab4 0xc8 ../MCTest_bsp/\libucosii_bsp.a(alt_main.o) + 0x0100cab4 alt_main + .text 0x0100cb7c 0x180 ../MCTest_bsp/\libucosii_bsp.a(alt_read.o) + 0x0100cb7c read + .text 0x0100ccfc 0x60 ../MCTest_bsp/\libucosii_bsp.a(alt_release_fd.o) + 0x0100ccfc alt_release_fd + .text 0x0100cd5c 0xbc ../MCTest_bsp/\libucosii_bsp.a(alt_sbrk.o) + 0x0100cd5c sbrk + .text 0x0100ce18 0x180 ../MCTest_bsp/\libucosii_bsp.a(alt_write.o) + 0x0100ce18 write + .text 0x0100cf98 0x108 ../MCTest_bsp/\libucosii_bsp.a(alt_env_lock.o) + 0x0100cf98 __env_lock + 0x0100d044 __env_unlock + .text 0x0100d0a0 0x1d8 ../MCTest_bsp/\libucosii_bsp.a(alt_malloc_lock.o) + 0x0100d0a0 __malloc_lock + 0x0100d1a8 __malloc_unlock + .text 0x0100d278 0x2128 ../MCTest_bsp/\libucosii_bsp.a(os_core.o) + 0x0100d278 OSEventNameGet + 0x0100d3a8 OSEventNameSet + 0x0100d4ec OSEventPendMulti + 0x0100dba0 OSInit + 0x0100dbf4 OSIntEnter + 0x0100dc70 OSIntExit + 0x0100dd70 OSSchedLock + 0x0100ddfc OSSchedUnlock + 0x0100dee0 OSStart + 0x0100df50 OSStatInit + 0x0100dffc OSTimeTick + 0x0100e23c OSVersion + 0x0100e25c OS_Dummy + 0x0100e278 OS_EventTaskRdy + 0x0100e40c OS_EventTaskWait + 0x0100e51c OS_EventTaskWaitMulti + 0x0100e670 OS_EventTaskRemove + 0x0100e728 OS_EventTaskRemoveMulti + 0x0100e82c OS_EventWaitListInit + 0x0100ebf8 OS_MemClr + 0x0100ec4c OS_MemCopy + 0x0100ecb8 OS_Sched + 0x0100edfc OS_StrCopy + 0x0100ee7c OS_StrLen + 0x0100eed4 OS_TaskIdle + 0x0100ef30 OS_TaskStat + 0x0100eff8 OS_TaskStatStkChk + 0x0100f0c0 OS_TCBInit + .text 0x0100f3a0 0x18c ../MCTest_bsp/\libucosii_bsp.a(os_dbg.o) + 0x0100f3a0 OSDebugInit + .text 0x0100f52c 0x193c ../MCTest_bsp/\libucosii_bsp.a(os_flag.o) + 0x0100f52c OSFlagAccept + 0x0100f860 OSFlagCreate + 0x0100f99c OSFlagDel + 0x0100fc44 OSFlagNameGet + 0x0100fd88 OSFlagNameSet + 0x0100fedc OSFlagPend + 0x01010520 OSFlagPendGetFlagsRdy + 0x01010588 OSFlagPost + 0x01010930 OSFlagQuery + 0x01010bc8 OS_FlagInit + 0x01010dbc OS_FlagUnlink + .text 0x01010e68 0x808 ../MCTest_bsp/\libucosii_bsp.a(os_mem.o) + 0x01010e68 OSMemCreate + 0x01011084 OSMemGet + 0x01011188 OSMemNameGet + 0x01011294 OSMemNameSet + 0x010113b4 OSMemPut + 0x010114a4 OSMemQuery + 0x010115a0 OS_MemInit + .text 0x01011670 0x1334 ../MCTest_bsp/\libucosii_bsp.a(os_q.o) + 0x01011670 OSQAccept + 0x010117c4 OSQCreate + 0x010119d8 OSQDel + 0x01011cd8 OSQFlush + 0x01011da0 OSQPend + 0x010120c0 OSQPendAbort + 0x0101223c OSQPost + 0x010123bc OSQPostFront + 0x01012544 OSQPostOpt + 0x01012778 OSQQuery + 0x010128f8 OS_QInit + .text 0x010129a4 0xbc8 ../MCTest_bsp/\libucosii_bsp.a(os_sem.o) + 0x010129a4 OSSemAccept + 0x01012a64 OSSemCreate + 0x01012b78 OSSemDel + 0x01012e18 OSSemPend + 0x01013094 OSSemPendAbort + 0x01013210 OSSemPost + 0x01013338 OSSemQuery + 0x01013468 OSSemSet + .text 0x0101356c 0x1a40 ../MCTest_bsp/\libucosii_bsp.a(os_task.o) + 0x0101356c OSTaskChangePrio + 0x01013ae0 OSTaskCreate + 0x01013cb4 OSTaskCreateExt + 0x01013eb4 OSTaskDel + 0x010142c0 OSTaskDelReq + 0x01014430 OSTaskNameGet + 0x010145e8 OSTaskNameSet + 0x010147ac OSTaskResume + 0x010149c4 OSTaskStkChk + 0x01014bc0 OSTaskSuspend + 0x01014dec OSTaskQuery + 0x01014f30 OS_TaskStkClr + .text 0x01014fac 0x598 ../MCTest_bsp/\libucosii_bsp.a(os_time.o) + 0x01014fac OSTimeDly + 0x010150f8 OSTimeDlyHMSM + 0x0101526c OSTimeDlyResume + 0x0101547c OSTimeGet + 0x010154e0 OSTimeSet + .text 0x01015544 0x114 ../MCTest_bsp/\libucosii_bsp.a(alt_sys_init.o) + 0x01015544 alt_irq_init + 0x01015578 alt_sys_init + .text 0x01015658 0x148 ../MCTest_bsp/\libucosii_bsp.a(altera_avalon_jtag_uart_fd.o) + 0x01015658 altera_avalon_jtag_uart_read_fd + 0x010156b0 altera_avalon_jtag_uart_write_fd + 0x01015708 altera_avalon_jtag_uart_close_fd + 0x01015750 altera_avalon_jtag_uart_ioctl_fd + .text 0x010157a0 0x580 ../MCTest_bsp/\libucosii_bsp.a(altera_avalon_jtag_uart_init.o) + 0x010157a0 altera_avalon_jtag_uart_init + 0x01015cac altera_avalon_jtag_uart_close + .text 0x01015d20 0xf4 ../MCTest_bsp/\libucosii_bsp.a(altera_avalon_jtag_uart_ioctl.o) + 0x01015d20 altera_avalon_jtag_uart_ioctl + .text 0x01015e14 0x2c0 ../MCTest_bsp/\libucosii_bsp.a(altera_avalon_jtag_uart_read.o) + 0x01015e14 altera_avalon_jtag_uart_read + .text 0x010160d4 0x2dc ../MCTest_bsp/\libucosii_bsp.a(altera_avalon_jtag_uart_write.o) + 0x010160d4 altera_avalon_jtag_uart_write + .text 0x010163b0 0xfc ../MCTest_bsp/\libucosii_bsp.a(altera_avalon_timer_sc.o) + 0x01016424 alt_avalon_timer_sc_init + .text 0x010164ac 0xf8 ../MCTest_bsp/\libucosii_bsp.a(altera_avalon_uart_fd.o) + 0x010164ac altera_avalon_uart_read_fd + 0x01016504 altera_avalon_uart_write_fd + 0x0101655c altera_avalon_uart_close_fd + .text 0x010165a4 0x578 ../MCTest_bsp/\libucosii_bsp.a(altera_avalon_uart_init.o) + 0x010165a4 altera_avalon_uart_init + 0x01016abc altera_avalon_uart_close + .text 0x01016b1c 0x310 ../MCTest_bsp/\libucosii_bsp.a(altera_avalon_uart_read.o) + 0x01016b1c altera_avalon_uart_read + .text 0x01016e2c 0x2a8 ../MCTest_bsp/\libucosii_bsp.a(altera_avalon_uart_write.o) + 0x01016e2c altera_avalon_uart_write + .text 0x010170d4 0x398 ../MCTest_bsp/\libucosii_bsp.a(altera_up_avalon_rs232.o) + 0x010170d4 alt_up_rs232_enable_read_interrupt + 0x01017128 alt_up_rs232_disable_read_interrupt + 0x01017180 alt_up_rs232_get_used_space_in_read_FIFO + 0x010171bc alt_up_rs232_get_available_space_in_write_FIFO + 0x010171fc alt_up_rs232_check_parity + 0x0101724c alt_up_rs232_write_data + 0x01017294 alt_up_rs232_read_data + 0x01017308 alt_up_rs232_read_fd + 0x01017398 alt_up_rs232_write_fd + 0x0101742c alt_up_rs232_open_dev + .text 0x0101746c 0x154 ../MCTest_bsp/\libucosii_bsp.a(alt_alarm_start.o) + 0x0101746c alt_alarm_start + .text 0x010175c0 0x44 ../MCTest_bsp/\libucosii_bsp.a(alt_dcache_flush_all.o) + 0x010175c0 alt_dcache_flush_all + .text 0x01017604 0x114 ../MCTest_bsp/\libucosii_bsp.a(alt_dev_llist_insert.o) + 0x01017604 alt_dev_llist_insert + .text 0x01017718 0x64 ../MCTest_bsp/\libucosii_bsp.a(alt_do_ctors.o) + 0x01017718 _do_ctors + .text 0x0101777c 0x64 ../MCTest_bsp/\libucosii_bsp.a(alt_do_dtors.o) + 0x0101777c _do_dtors + .text 0x010177e0 0x94 ../MCTest_bsp/\libucosii_bsp.a(alt_find_dev.o) + 0x010177e0 alt_find_dev + .text 0x01017874 0x30 ../MCTest_bsp/\libucosii_bsp.a(alt_icache_flush_all.o) + 0x01017874 alt_icache_flush_all + .text 0x010178a4 0x13c ../MCTest_bsp/\libucosii_bsp.a(alt_io_redirect.o) + 0x01017968 alt_io_redirect + .text 0x010179e0 0x1c0 ../MCTest_bsp/\libucosii_bsp.a(alt_irq_register.o) + 0x010179e0 alt_irq_register + .text 0x01017ba0 0x0 ../MCTest_bsp/\libucosii_bsp.a(alt_irq_vars.o) + .text 0x01017ba0 0x2c4 ../MCTest_bsp/\libucosii_bsp.a(alt_open.o) + 0x01017c7c open + .text 0x01017e64 0x1a8 ../MCTest_bsp/\libucosii_bsp.a(alt_tick.o) + 0x01017e64 alt_alarm_stop + 0x01017efc alt_tick + .text 0x0101800c 0x20 ../MCTest_bsp/\libucosii_bsp.a(altera_nios2_qsys_irq.o) + 0x0101800c altera_nios2_qsys_irq_init + .text 0x0101802c 0xd0 ../MCTest_bsp/\libucosii_bsp.a(os_cpu_a.o) + 0x0101802c OSCtxSw + 0x0101802c OSIntCtxSw + 0x010180b8 OSStartHighRdy + 0x010180d8 OSStartTsk + .text 0x010180fc 0x418 ../MCTest_bsp/\libucosii_bsp.a(os_cpu_c.o) + 0x010180fc OSTaskStkInit + 0x0101840c OSTaskCreateHook + 0x0101842c OSTaskDelHook + 0x0101844c OSTaskSwHook + 0x01018468 OSTaskStatHook + 0x01018484 OSTimeTickHook + 0x010184a0 OSInitHookBegin + 0x010184bc OSInitHookEnd + 0x010184d8 OSTaskIdleHook + 0x010184f4 OSTCBInitHook + .text 0x01018514 0x120 ../MCTest_bsp/\libucosii_bsp.a(alt_find_file.o) + 0x01018514 alt_find_file + .text 0x01018634 0xf4 ../MCTest_bsp/\libucosii_bsp.a(alt_get_fd.o) + 0x01018634 alt_get_fd + .text 0x01018728 0x90 ../MCTest_bsp/\libucosii_bsp.a(alt_icache_flush.o) + 0x01018728 alt_icache_flush + .text 0x010187b8 0x0 ../MCTest_bsp/\libucosii_bsp.a(alt_irq_entry.o) + .text 0x010187b8 0x0 ../MCTest_bsp/\libucosii_bsp.a(alt_irq_handler.o) + .text 0x010187b8 0x0 ../MCTest_bsp/\libucosii_bsp.a(alt_exception_entry.o) + .text 0x010187b8 0x14 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-atexit.o) + 0x010187b8 atexit + .text 0x010187cc 0x38 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-exit.o) + 0x010187cc exit + .text 0x01018804 0x74 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-memcmp.o) + 0x01018804 memcmp + .text 0x01018878 0x134 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-__atexit.o) + 0x01018878 __register_exitproc + .text 0x010189ac 0x1b4 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-__call_atexit.o) + 0x010189b0 __call_exitprocs + *(.gnu.warning.*) + *(.fini) + 0x01018b60 PROVIDE (__etext, ABSOLUTE (.)) + 0x01018b60 PROVIDE (_etext, ABSOLUTE (.)) + 0x01018b60 PROVIDE (etext, ABSOLUTE (.)) + *(.eh_frame_hdr) + 0x01018b60 . = ALIGN (0x4) + 0x01018b60 PROVIDE (__preinit_array_start, ABSOLUTE (.)) + *(.preinit_array) + 0x01018b60 PROVIDE (__preinit_array_end, ABSOLUTE (.)) + 0x01018b60 PROVIDE (__init_array_start, ABSOLUTE (.)) + *(.init_array) + 0x01018b60 PROVIDE (__init_array_end, ABSOLUTE (.)) + 0x01018b60 PROVIDE (__fini_array_start, ABSOLUTE (.)) + *(.fini_array) + 0x01018b60 PROVIDE (__fini_array_end, ABSOLUTE (.)) + *(.eh_frame) + *(.gcc_except_table) + .gcc_except_table + 0x01018b60 0x6 obj/default/main.o + *fill* 0x01018b66 0x2 3a880100 + .gcc_except_table + 0x01018b68 0x20 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(eh_personality.o) + .gcc_except_table + 0x01018b88 0x10 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(eh_terminate.o) + .gcc_except_table + 0x01018b98 0x10 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(eh_catch.o) + .gcc_except_table + 0x01018ba8 0x10 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(eh_alloc.o) + .gcc_except_table + 0x01018bb8 0x14 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(new_op.o) + *(.dynamic) + 0x01018bcc PROVIDE (__CTOR_LIST__, ABSOLUTE (.)) + *(.ctors) + .ctors 0x01018bcc 0x4 obj/default/main.o + *(SORT(.ctors.*)) + .ctors.65535 0x01018bd0 0x4 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-__call_atexit.o) + 0x01018bd4 PROVIDE (__CTOR_END__, ABSOLUTE (.)) + 0x01018bd4 PROVIDE (__DTOR_LIST__, ABSOLUTE (.)) + *(.dtors) + *(SORT(.dtors.*)) + 0x01018bd4 PROVIDE (__DTOR_END__, ABSOLUTE (.)) + *(.jcr) + 0x01018bd4 . = ALIGN (0x4) + +.rodata 0x01018bd4 0x66c + 0x01018bd4 PROVIDE (__ram_rodata_start, ABSOLUTE (.)) + 0x01018bd4 . = ALIGN (0x4) + *(.rodata .rodata.* .gnu.linkonce.r.*) + .rodata._ZTV12MotorHandler + 0x01018bd4 0x10 obj/default/MotorHandler.o + 0x01018bd4 vtable for MotorHandler + .rodata._ZTS12MotorHandler + 0x01018be4 0x10 obj/default/MotorHandler.o + 0x01018be4 typeinfo name for MotorHandler + .rodata 0x01018bf4 0x40 obj/default/main.o + .rodata._ZTVN10__cxxabiv117__class_type_infoE + 0x01018c34 0x2c c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(class_type_info.o) + 0x01018c34 vtable for __cxxabiv1::__class_type_info + .rodata._ZTSN10__cxxabiv117__class_type_infoE + 0x01018c60 0x24 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(class_type_info.o) + 0x01018c60 typeinfo name for __cxxabiv1::__class_type_info + .rodata._ZTIN10__cxxabiv117__class_type_infoE + 0x01018c84 0xc c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libstdc++.a(class_type_info.o) + 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c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_umoddi3.o) + .debug_ranges 0x000009a8 0x30 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_addsub_df.o) + .debug_ranges 0x000009d8 0x88 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_mul_df.o) + .debug_ranges 0x00000a60 0x50 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_div_df.o) + .debug_ranges 0x00000ab0 0x18 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_usi_to_df.o) + .debug_ranges 0x00000ac8 0x68 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_muldi3.o) + .debug_ranges 0x00000b30 0x28 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_clzsi2.o) + .debug_ranges 0x00000b58 0x28 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2\libgcc.a(_pack_df.o) + .debug_ranges 0x00000b80 0x18 ../MCTest_bsp/\libucosii_bsp.a(altera_avalon_jtag_uart_init.o) + .debug_ranges 0x00000b98 0x18 ../MCTest_bsp/\libucosii_bsp.a(altera_avalon_uart_init.o) + .debug_ranges 0x00000bb0 0x28 ../MCTest_bsp/\libucosii_bsp.a(alt_irq_entry.o) + .debug_ranges 0x00000bd8 0x30 ../MCTest_bsp/\libucosii_bsp.a(alt_exception_entry.o) + .debug_ranges 0x00000c08 0x18 c:/altera/12.1sp1/nios2eds/bin/gnu/h-i686-mingw32/bin/../lib/gcc/nios2-elf/4.1.2/../../../../nios2-elf/lib\libc.a(lib_a-__call_atexit.o) diff --git a/MCandWifiTestDE0/Software/MCTest/MCTest.objdump b/MCandWifiTestDE0/Software/MCTest/MCTest.objdump new file mode 100644 index 00000000..ec9f64b9 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest/MCTest.objdump @@ -0,0 +1,36201 @@ + +MCTest.elf: file format elf32-littlenios2 +MCTest.elf +architecture: nios2, flags 0x00000112: +EXEC_P, HAS_SYMS, D_PAGED +start address 0x010001c0 + +Program Header: + LOAD off 0x00001000 vaddr 0x01000000 paddr 0x01000000 align 2**12 + filesz 0x00000020 memsz 0x00000020 flags r-x + LOAD off 0x00001020 vaddr 0x01000020 paddr 0x01000020 align 2**12 + filesz 0x00019220 memsz 0x00019220 flags r-x + LOAD off 0x0001a240 vaddr 0x01019240 paddr 0x0101af14 align 2**12 + filesz 0x00001cd4 memsz 0x00001cd4 flags rw- + LOAD off 0x0001cbe8 vaddr 0x0101cbe8 paddr 0x0101cbe8 align 2**12 + filesz 0x00000000 memsz 0x00009da0 flags rw- + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .entry 00000020 01000000 01000000 00001000 2**5 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 1 .exceptions 000001a0 01000020 01000020 00001020 2**2 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 2 .text 00018a14 010001c0 010001c0 000011c0 2**2 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 3 .rodata 0000066c 01018bd4 01018bd4 00019bd4 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 4 .rwdata 00001cd4 01019240 0101af14 0001a240 2**2 + CONTENTS, ALLOC, LOAD, DATA, SMALL_DATA + 5 .bss 00009da0 0101cbe8 0101cbe8 0001cbe8 2**2 + ALLOC, SMALL_DATA + 6 .comment 00000026 00000000 00000000 0001bf14 2**0 + CONTENTS, READONLY + 7 .debug_aranges 00001118 00000000 00000000 0001bf40 2**3 + CONTENTS, READONLY, DEBUGGING + 8 .debug_pubnames 00002f7c 00000000 00000000 0001d058 2**0 + CONTENTS, READONLY, DEBUGGING + 9 .debug_info 0003da89 00000000 00000000 0001ffd4 2**0 + CONTENTS, READONLY, DEBUGGING + 10 .debug_abbrev 0000d180 00000000 00000000 0005da5d 2**0 + CONTENTS, READONLY, DEBUGGING + 11 .debug_line 00022121 00000000 00000000 0006abdd 2**0 + CONTENTS, READONLY, DEBUGGING + 12 .debug_frame 00003230 00000000 00000000 0008cd00 2**2 + CONTENTS, READONLY, DEBUGGING + 13 .debug_str 00004097 00000000 00000000 0008ff30 2**0 + CONTENTS, READONLY, DEBUGGING + 14 .debug_loc 0000f916 00000000 00000000 00093fc7 2**0 + CONTENTS, READONLY, DEBUGGING + 15 .debug_alt_sim_info 00000030 00000000 00000000 000a38e0 2**2 + CONTENTS, READONLY, DEBUGGING + 16 .debug_ranges 00000c20 00000000 00000000 000a3910 2**3 + CONTENTS, READONLY, DEBUGGING + 17 .thread_model 00000006 00000000 00000000 000aac33 2**0 + CONTENTS, READONLY + 18 .cpu 00000003 00000000 00000000 000aac39 2**0 + CONTENTS, READONLY + 19 .qsys 00000001 00000000 00000000 000aac3c 2**0 + CONTENTS, READONLY + 20 .simulation_enabled 00000001 00000000 00000000 000aac3d 2**0 + CONTENTS, READONLY + 21 .sysid_hash 00000004 00000000 00000000 000aac3e 2**0 + CONTENTS, READONLY + 22 .sysid_base 00000004 00000000 00000000 000aac42 2**0 + CONTENTS, READONLY + 23 .sysid_time 00000004 00000000 00000000 000aac46 2**0 + CONTENTS, READONLY + 24 .stderr_dev 0000000b 00000000 00000000 000aac4a 2**0 + CONTENTS, READONLY + 25 .stdin_dev 0000000b 00000000 00000000 000aac55 2**0 + CONTENTS, READONLY + 26 .stdout_dev 0000000b 00000000 00000000 000aac60 2**0 + CONTENTS, READONLY + 27 .sopc_system_name 00000006 00000000 00000000 000aac6b 2**0 + CONTENTS, READONLY + 28 .quartus_project_dir 0000002c 00000000 00000000 000aac71 2**0 + CONTENTS, READONLY + 29 .jdi 000046ad 00000000 00000000 000aac9d 2**0 + CONTENTS, READONLY + 30 .sopcinfo 000569df 00000000 00000000 000af34a 2**0 + CONTENTS, READONLY +SYMBOL TABLE: +01000000 l d .entry 00000000 .entry +01000020 l d .exceptions 00000000 .exceptions +010001c0 l d .text 00000000 .text +01018bd4 l d .rodata 00000000 .rodata +01019240 l d .rwdata 00000000 .rwdata +0101cbe8 l d .bss 00000000 .bss +00000000 l d .comment 00000000 .comment +00000000 l d .debug_aranges 00000000 .debug_aranges +00000000 l d .debug_pubnames 00000000 .debug_pubnames +00000000 l d .debug_info 00000000 .debug_info +00000000 l d .debug_abbrev 00000000 .debug_abbrev +00000000 l d .debug_line 00000000 .debug_line +00000000 l d .debug_frame 00000000 .debug_frame +00000000 l d .debug_str 00000000 .debug_str +00000000 l d .debug_loc 00000000 .debug_loc +00000000 l d .debug_alt_sim_info 00000000 .debug_alt_sim_info +00000000 l d .debug_ranges 00000000 .debug_ranges +01000208 l .text 00000000 alt_after_alt_main +00000000 l df *ABS* 00000000 alt_irq_handler.c +00000000 l df *ABS* 00000000 MotorHandler.cpp +00000000 l df *ABS* 00000000 main.cpp +01000704 l F .text 00000030 _GLOBAL__I_motorHandler +010005d8 l F .text 0000012c _Z41__static_initialization_and_destruction_0ii +00000000 l df *ABS* 00000000 class_type_info.cc +00000000 l df *ABS* 00000000 eh_personality.cc +01000c48 l F .text 00000030 _Z12read_uleb128PKhPj +01000c78 l F .text 00000054 _Z12read_sleb128PKhPi +01000ccc l F .text 0000009c _Z16get_adjusted_ptrPKSt9type_infoS1_PPv +01000d68 l F .text 000001d4 _Z28read_encoded_value_with_basehjPKhPj +01000f3c l F .text 00000090 _Z21base_of_encoded_valuehP15_Unwind_Context +01000fcc l F .text 00000100 _Z17parse_lsda_headerP15_Unwind_ContextPKhP16lsda_header_info +010010cc l F .text 00000084 _Z15get_ttype_entryP16lsda_header_infoj +01001150 l F .text 00000084 _Z20check_exception_specP16lsda_header_infoPKSt9type_infoPvi +00000000 l df *ABS* 00000000 eh_terminate.cc +00000000 l df *ABS* 00000000 eh_term_handler.cc +00000000 l df *ABS* 00000000 eh_catch.cc +00000000 l df *ABS* 00000000 del_op.cc +00000000 l df *ABS* 00000000 eh_throw.cc +01001c18 l F .text 00000060 _Z23__gxx_exception_cleanup19_Unwind_Reason_CodeP17_Unwind_Exception +00000000 l df *ABS* 00000000 si_class_type_info.cc +00000000 l df *ABS* 00000000 tinfo.cc +00000000 l df *ABS* 00000000 eh_alloc.cc +01022cac l O .bss 00000800 emergency_buffer +0101cbf0 l O .bss 00000004 emergency_used +00000000 l df *ABS* 00000000 new_op.cc +00000000 l df *ABS* 00000000 eh_exception.cc +00000000 l df *ABS* 00000000 eh_call.cc +00000000 l df *ABS* 00000000 new_handler.cc +00000000 l df *ABS* 00000000 eh_globals.cc +0101cbf8 l O .bss 00000008 eh_globals +00000000 l df *ABS* 00000000 eh_unex_handler.cc +00000000 l df *ABS* 00000000 unwind-sjlj.c +0101cc00 l O .bss 00000004 fc_static +01002314 l F .text 00000100 _Unwind_ForcedUnwind_Phase2 +0100242c l F .text 000000cc _Unwind_RaiseException_Phase2 +010024f8 l F .text 00000028 uw_install_context +00000000 l df *ABS* 00000000 abort.c +00000000 l df *ABS* 00000000 malloc.c +00000000 l df *ABS* 00000000 mallocr.c +00000000 l df *ABS* 00000000 memset.c +00000000 l df *ABS* 00000000 printf.c +00000000 l df *ABS* 00000000 puts.c +00000000 l df *ABS* 00000000 sbrkr.c +00000000 l df *ABS* 00000000 signal.c +00000000 l df *ABS* 00000000 signalr.c +00000000 l df *ABS* 00000000 strlen.c +00000000 l df *ABS* 00000000 vfprintf.c +01003514 l F .text 00000058 __sprint_r +01018e1a l O .rodata 00000010 blanks.3452 +01018e0a l O .rodata 00000010 zeroes.3453 +00000000 l df *ABS* 00000000 wsetup.c +00000000 l df *ABS* 00000000 dtoa.c +01005578 l F .text 00000218 quorem +00000000 l df *ABS* 00000000 fflush.c +00000000 l df *ABS* 00000000 findfp.c +01006f74 l F .text 00000058 std +01007080 l F .text 00000008 __fp_lock +01007088 l F .text 00000008 __fp_unlock +00000000 l df *ABS* 00000000 mallocr.c +00000000 l df *ABS* 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.text 00000128 OSSemPost +01001e88 g F .text 00000010 _ZNSt9type_infoD2Ev +0100ddfc g F .text 000000e4 OSSchedUnlock +01001c78 g F .text 00000078 _ZNK10__cxxabiv120__si_class_type_info11__do_upcastEPKNS_17__class_type_infoEPKvRNS1_15__upcast_resultE +01015658 g F .text 00000058 altera_avalon_jtag_uart_read_fd +01018634 g F .text 000000f4 alt_get_fd +0101cc64 g O .bss 00000004 OSMemFreeList +0100df50 g F .text 000000ac OSStatInit +01010930 g F .text 000000d4 OSFlagQuery +0100c1a8 g F .text 000000c8 __fpcmp_parts_d +0101aed4 g O .rwdata 00000002 OSTaskCreateExtEn +01009ad8 g F .text 00000070 _close_r +01018804 g F .text 00000074 memcmp +0100e25c g F .text 0000001c OS_Dummy +01015708 g F .text 00000048 altera_avalon_jtag_uart_close_fd +01026988 g *ABS* 00000000 __alt_stack_base +01015750 g F .text 00000050 altera_avalon_jtag_uart_ioctl_fd +01000460 g F .text 00000088 _ZN12MotorHandler10mc_forwardEv +010021f0 g F .text 00000034 _ZNSt9bad_allocD0Ev +01001d24 g F .text 00000010 _ZN10__cxxabiv120__si_class_type_infoD1Ev +01018be4 w O .rodata 0000000f _ZTS12MotorHandler +0100543c g F .text 0000013c __swsetup_r +01024c74 g O .bss 000001e0 OSQTbl +01002744 g F .text 00000058 _Unwind_SjLj_Resume_or_Rethrow +0100b294 g F .text 00000258 __divdf3 +01007144 g F .text 000000f0 __sfp +010085ec g F .text 00000058 __copybits +01001e40 g F .text 00000008 _ZNKSt9type_info14__is_pointer_pEv +01019240 g O .rwdata 00000408 __malloc_av_ +01006fd8 g F .text 00000004 __sinit_lock_release +0101cc68 g O .bss 00000004 OSTCBHighRdy +0100aed0 g F .text 000003c4 __muldf3 +01009890 g F .text 00000060 __sread +01018d34 w O .rodata 00000014 _ZTVSt9exception +0101cc6c g O .bss 00000004 OSQFreeList +01017128 g F .text 00000058 alt_up_rs232_disable_read_interrupt +01018514 g F .text 00000120 alt_find_file +01000af8 g F .text 00000020 _ZNK10__cxxabiv117__class_type_info20__do_find_public_srcElPKvPKS0_S2_ +01017604 g F .text 000000b4 alt_dev_llist_insert +0100d0a0 g F .text 00000108 __malloc_lock +0100cd5c g F .text 000000bc sbrk +01018c34 w O .rodata 0000002c _ZTVN10__cxxabiv117__class_type_infoE +01001ba4 g F .text 00000074 __cxa_throw +01020c9c g O .bss 00002000 mc_task_stk +0100d3a8 g F .text 00000144 OSEventNameSet +01006d44 g F .text 000001fc _fflush_r +010022d8 g F .text 00000010 _Unwind_SetIP +01009a24 g F .text 000000b4 _calloc_r +0101cc70 g O .bss 00000001 OSRdyGrp +01000380 g F .text 00000058 _ZN12MotorHandler7mc_leftEv +0101cbe8 g *ABS* 00000000 __bss_start +01002f1c g F .text 00000098 memset +010007dc g F .text 0000010c main +0101cc2c g O .bss 00000004 alt_envp +0101cc0c g O .bss 00000004 __malloc_max_total_mem +010156b0 g F .text 00000058 altera_avalon_jtag_uart_write_fd +01002244 g F .text 00000008 __cxa_get_globals_fast +010190d8 g O .rodata 00000100 OSUnMapTbl +0101aece g O .rwdata 00000002 OSSemEn +01010588 g F .text 000003a8 OSFlagPost +010097a4 g F .text 00000008 __sclose +02000000 g *ABS* 00000000 __alt_heap_limit +01009c58 g F .text 00000014 fclose +0100e40c g F .text 00000110 OS_EventTaskWait +0100eff8 g F .text 000000c8 OS_TaskStatStkChk +010267f8 g O .bss 00000190 _atexit0 +010142c0 g F .text 00000170 OSTaskDelReq +01005790 g F .text 000015b4 _dtoa_r +010027dc g F .text 00000740 _malloc_r +0101ae84 g O .rwdata 00000004 alt_errno +0100dee0 g F .text 00000070 OSStart +01003294 g F .text 00000010 _init_signal +0100d044 g F .text 0000005c __env_unlock +01018c84 w O .rodata 0000000c _ZTIN10__cxxabiv117__class_type_infoE +01007bd8 g F .text 000000b8 _fwalk +010147ac g F .text 00000218 OSTaskResume +010114a4 g F .text 000000fc OSMemQuery +0101aee0 g O .rwdata 00000002 OSTaskStatEn +0101aeba g O .rwdata 00000002 OSMemMax +010123bc g F .text 00000188 OSQPostFront +01002180 g F .text 00000010 _ZNSt13bad_exceptionD1Ev +0100bb74 g F .text 00000060 __divsi3 +01000538 g F .text 00000050 _ZN12MotorHandlerD1Ev +0101cc71 g O .bss 00000003 OSRdyTbl +0101ae94 g O .rwdata 00000002 OSDebugEn +01018fa4 g O .rodata 00000014 __thenan_df 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+01003358 g F .text 00000014 __sigtramp +01017180 g F .text 0000003c alt_up_rs232_get_used_space_in_read_FIFO +0100c270 g F .text 000000fc close +0101cc34 g O .bss 00000004 alt_envsem +0101cc8c g O .bss 00000004 OSIdleCtrRun +0100e23c g F .text 00000020 OSVersion +0101aef8 g O .rwdata 00000002 OSTmrCfgWheelSize +0100c878 g F .text 00000080 alt_load +01014f30 g F .text 0000007c OS_TaskStkClr +0100bd5c g F .text 00000314 __pack_d +0101aed2 g O .rwdata 00000002 OSTaskCreateEn +01001e50 g F .text 00000010 _ZNKSt9type_info10__do_catchEPKS_PPvj +0100e82c g F .text 00000068 OS_EventWaitListInit +0100321c g F .text 00000014 raise +010184d8 g F .text 0000001c OSTaskIdleHook +010027b4 g F .text 00000014 free +01006fd4 g F .text 00000004 __sinit_lock_acquire +01008e00 g F .text 00000100 __multadd +01000b18 g F .text 00000034 _ZN10__cxxabiv117__class_type_infoD0Ev +01014bc0 g F .text 0000022c OSTaskSuspend +0100814c g F .text 00000028 _Bfree +0100eed4 g F .text 0000005c OS_TaskIdle +0101aefe g O .rwdata 00000002 OSTmrTblSize +01012778 g F .text 00000180 OSQQuery + + + +Disassembly of section .entry: + +01000000 <__reset>: +#if NIOS2_ICACHE_SIZE > 0 && defined(ALT_ALLOW_CODE_AT_RESET) && !defined(ALT_SIM_OPTIMIZE) + /* Assume the instruction cache size is always a power of two. */ +#if NIOS2_ICACHE_SIZE > 0x8000 + movhi r2, %hi(NIOS2_ICACHE_SIZE) +#else + movui r2, NIOS2_ICACHE_SIZE + 1000000: 00880014 movui r2,8192 +#endif + +0: + initi r2 + 1000004: 1001483a initi r2 + addi r2, r2, -NIOS2_ICACHE_LINE_SIZE + 1000008: 10bff804 addi r2,r2,-32 + bgt r2, zero, 0b + 100000c: 00bffd16 blt zero,r2,1000004 <__reset+0x4> + * Jump to the _start entry point in the .text section if reset code + * is allowed or if optimizing for RTL simulation. + */ +#if defined(ALT_ALLOW_CODE_AT_RESET) || defined(ALT_SIM_OPTIMIZE) + /* Jump to the _start entry point in the .text section. */ + movhi r1, %hi(_start) + 1000010: 00404034 movhi at,256 + ori r1, r1, %lo(_start) + 1000014: 08407014 ori at,at,448 + jmp r1 + 1000018: 0800683a jmp at + 100001c: 00000000 call 0 + +Disassembly of section .exceptions: + +01000020 : + * Process an exception. For all exceptions we must preserve all + * caller saved registers on the stack (See the Nios2 ABI + * documentation for details). + */ + + addi sp, sp, -76 + 1000020: deffed04 addi sp,sp,-76 + +#endif + +#endif + + stw ra, 0(sp) + 1000024: dfc00015 stw ra,0(sp) + /* + * Leave a gap in the stack frame at 4(sp) for the muldiv handler to + * store zero into. + */ + + stw r1, 8(sp) + 1000028: d8400215 stw at,8(sp) + stw r2, 12(sp) + 100002c: d8800315 stw r2,12(sp) + stw r3, 16(sp) + 1000030: d8c00415 stw r3,16(sp) + stw r4, 20(sp) + 1000034: d9000515 stw r4,20(sp) + stw r5, 24(sp) + 1000038: d9400615 stw r5,24(sp) + stw r6, 28(sp) + 100003c: d9800715 stw r6,28(sp) + stw r7, 32(sp) + 1000040: d9c00815 stw r7,32(sp) + + rdctl r5, estatus + 1000044: 000b307a rdctl r5,estatus + + stw r8, 36(sp) + 1000048: da000915 stw r8,36(sp) + stw r9, 40(sp) + 100004c: da400a15 stw r9,40(sp) + stw r10, 44(sp) + 1000050: da800b15 stw r10,44(sp) + stw r11, 48(sp) + 1000054: dac00c15 stw r11,48(sp) + stw r12, 52(sp) + 1000058: db000d15 stw r12,52(sp) + stw r13, 56(sp) + 100005c: db400e15 stw r13,56(sp) + stw r14, 60(sp) + 1000060: db800f15 stw r14,60(sp) + stw r15, 64(sp) + 1000064: dbc01015 stw r15,64(sp) + /* + * ea-4 contains the address of the instruction being executed + * when the exception occured. For interrupt exceptions, we will + * will be re-issue the isntruction. Store it in 72(sp) + */ + stw r5, 68(sp) /* estatus */ + 1000068: d9401115 stw r5,68(sp) + addi r15, ea, -4 /* instruction that caused exception */ + 100006c: ebffff04 addi r15,ea,-4 + stw r15, 72(sp) + 1000070: dbc01215 stw r15,72(sp) +#else + /* + * Test to see if the exception was a software exception or caused + * by an external interrupt, and vector accordingly. + */ + rdctl r4, ipending + 1000074: 0009313a rdctl r4,ipending + andi r2, r5, 1 + 1000078: 2880004c andi r2,r5,1 + beq r2, zero, .Lnot_irq + 100007c: 10000326 beq r2,zero,100008c + beq r4, zero, .Lnot_irq + 1000080: 20000226 beq r4,zero,100008c + /* + * Now that all necessary registers have been preserved, call + * alt_irq_handler() to process the interrupts. + */ + + call alt_irq_handler + 1000084: 10000ec0 call 10000ec + + .section .exceptions.irqreturn, "xa" + + br .Lexception_exit + 1000088: 00000306 br 1000098 + * upon completion, so we write ea (address of instruction *after* + * the one where the exception occured) into 72(sp). The actual + * instruction that caused the exception is written in r2, which these + * handlers will utilize. + */ + stw ea, 72(sp) /* Don't re-issue */ + 100008c: df401215 stw ea,72(sp) + ldw r2, -4(ea) /* Instruction that caused exception */ + 1000090: e8bfff17 ldw r2,-4(ea) +#ifdef NIOS2_HAS_DEBUG_STUB + /* + * Either tell the user now (if there is a debugger attached) or go into + * the debug monitor which will loop until a debugger is attached. + */ + break + 1000094: 003da03a break 0 + /* + * Restore the saved registers, so that all general purpose registers + * have been restored to their state at the time the interrupt occured. + */ + + ldw r5, 68(sp) + 1000098: d9401117 ldw r5,68(sp) + ldw ea, 72(sp) /* This becomes the PC once eret is executed */ + 100009c: df401217 ldw ea,72(sp) + ldw ra, 0(sp) + 10000a0: dfc00017 ldw ra,0(sp) + + wrctl estatus, r5 + 10000a4: 2801707a wrctl estatus,r5 + + ldw r1, 8(sp) + 10000a8: d8400217 ldw at,8(sp) + ldw r2, 12(sp) + 10000ac: d8800317 ldw r2,12(sp) + ldw r3, 16(sp) + 10000b0: d8c00417 ldw r3,16(sp) + ldw r4, 20(sp) + 10000b4: d9000517 ldw r4,20(sp) + ldw r5, 24(sp) + 10000b8: d9400617 ldw r5,24(sp) + ldw r6, 28(sp) + 10000bc: d9800717 ldw r6,28(sp) + ldw r7, 32(sp) + 10000c0: d9c00817 ldw r7,32(sp) +#ifdef ALT_STACK_CHECK + ldw et, %gprel(alt_exception_old_stack_limit)(gp) +#endif +#endif + + ldw r8, 36(sp) + 10000c4: da000917 ldw r8,36(sp) + ldw r9, 40(sp) + 10000c8: da400a17 ldw r9,40(sp) + ldw r10, 44(sp) + 10000cc: da800b17 ldw r10,44(sp) + ldw r11, 48(sp) + 10000d0: dac00c17 ldw r11,48(sp) + ldw r12, 52(sp) + 10000d4: db000d17 ldw r12,52(sp) + ldw r13, 56(sp) + 10000d8: db400e17 ldw r13,56(sp) + ldw r14, 60(sp) + 10000dc: db800f17 ldw r14,60(sp) + ldw r15, 64(sp) + 10000e0: dbc01017 ldw r15,64(sp) +#endif + + ldw sp, 76(sp) + +#else + addi sp, sp, 76 + 10000e4: dec01304 addi sp,sp,76 + + /* + * Return to the interrupted instruction. + */ + + eret + 10000e8: ef80083a eret + +010000ec : + * instruction is present if the macro ALT_CI_INTERRUPT_VECTOR defined. + */ + +void alt_irq_handler (void) __attribute__ ((section (".exceptions"))); +void alt_irq_handler (void) +{ + 10000ec: defff904 addi sp,sp,-28 + 10000f0: dfc00615 stw ra,24(sp) + 10000f4: df000515 stw fp,20(sp) + 10000f8: df000504 addi fp,sp,20 + + /* + * Notify the operating system that we are at interrupt level. + */ + + ALT_OS_INT_ENTER(); + 10000fc: 100dbf40 call 100dbf4 +#ifndef NIOS2_EIC_PRESENT +static ALT_INLINE alt_u32 ALT_ALWAYS_INLINE alt_irq_pending (void) +{ + alt_u32 active; + + NIOS2_READ_IPENDING (active); + 1000100: 0005313a rdctl r2,ipending + 1000104: e0bffc15 stw r2,-16(fp) + + return active; + 1000108: e0bffc17 ldw r2,-16(fp) + * Consider the case where the high priority interupt is asserted during + * the interrupt entry sequence for a lower priority interrupt to see why + * this is the case. + */ + + active = alt_irq_pending (); + 100010c: e0bfff15 stw r2,-4(fp) + + do + { + i = 0; + 1000110: e03ffd15 stw zero,-12(fp) + mask = 1; + 1000114: 00800044 movi r2,1 + 1000118: e0bffe15 stw r2,-8(fp) + * called to clear the interrupt condition. + */ + + do + { + if (active & mask) + 100011c: e0ffff17 ldw r3,-4(fp) + 1000120: e0bffe17 ldw r2,-8(fp) + 1000124: 1884703a and r2,r3,r2 + 1000128: 1005003a cmpeq r2,r2,zero + 100012c: 1000171e bne r2,zero,100018c + { +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT + alt_irq[i].handler(alt_irq[i].context); +#else + alt_irq[i].handler(alt_irq[i].context, i); + 1000130: e0bffd17 ldw r2,-12(fp) + 1000134: 00c040b4 movhi r3,258 + 1000138: 18d9be04 addi r3,r3,26360 + 100013c: 100490fa slli r2,r2,3 + 1000140: 10c5883a add r2,r2,r3 + 1000144: 11800017 ldw r6,0(r2) + 1000148: e0bffd17 ldw r2,-12(fp) + 100014c: 00c040b4 movhi r3,258 + 1000150: 18d9be04 addi r3,r3,26360 + 1000154: 100490fa slli r2,r2,3 + 1000158: 10c5883a add r2,r2,r3 + 100015c: 10800104 addi r2,r2,4 + 1000160: 11000017 ldw r4,0(r2) + 1000164: e17ffd17 ldw r5,-12(fp) + 1000168: 303ee83a callr r6 +#ifndef NIOS2_EIC_PRESENT +static ALT_INLINE alt_u32 ALT_ALWAYS_INLINE alt_irq_pending (void) +{ + alt_u32 active; + + NIOS2_READ_IPENDING (active); + 100016c: 0005313a rdctl r2,ipending + 1000170: e0bffb15 stw r2,-20(fp) + + return active; + 1000174: e0bffb17 ldw r2,-20(fp) + mask <<= 1; + i++; + + } while (1); + + active = alt_irq_pending (); + 1000178: e0bfff15 stw r2,-4(fp) + + } while (active); + 100017c: e0bfff17 ldw r2,-4(fp) + 1000180: 1004c03a cmpne r2,r2,zero + 1000184: 103fe21e bne r2,zero,1000110 + 1000188: 00000706 br 10001a8 +#else + alt_irq[i].handler(alt_irq[i].context, i); +#endif + break; + } + mask <<= 1; + 100018c: e0bffe17 ldw r2,-8(fp) + 1000190: 1085883a add r2,r2,r2 + 1000194: e0bffe15 stw r2,-8(fp) + i++; + 1000198: e0bffd17 ldw r2,-12(fp) + 100019c: 10800044 addi r2,r2,1 + 10001a0: e0bffd15 stw r2,-12(fp) + + } while (1); + 10001a4: 003fdd06 br 100011c + + /* + * Notify the operating system that interrupt processing is complete. + */ + + ALT_OS_INT_EXIT(); + 10001a8: 100dc700 call 100dc70 +} + 10001ac: e037883a mov sp,fp + 10001b0: dfc00117 ldw ra,4(sp) + 10001b4: df000017 ldw fp,0(sp) + 10001b8: dec00204 addi sp,sp,8 + 10001bc: f800283a ret + +Disassembly of section .text: + +010001c0 <_start>: + + /* Assume the data cache size is always a power of two. */ +#if NIOS2_DCACHE_SIZE > 0x8000 + movhi r2, %hi(NIOS2_DCACHE_SIZE) +#else + movui r2, NIOS2_DCACHE_SIZE + 10001c0: 00840014 movui r2,4096 +#endif + +0: + initd 0(r2) + 10001c4: 10000033 initd 0(r2) + addi r2, r2, -NIOS2_DCACHE_LINE_SIZE + 10001c8: 10bff804 addi r2,r2,-32 + bgt r2, zero, 0b + 10001cc: 00bffd16 blt zero,r2,10001c4 <_start+0x4> +#if (NIOS2_NUM_OF_SHADOW_REG_SETS == 0) + /* + * Now that the caches are initialized, set up the stack pointer. + * The value provided by the linker is assumed to be correctly aligned. + */ + movhi sp, %hi(__alt_stack_pointer) + 10001d0: 06c08034 movhi sp,512 + ori sp, sp, %lo(__alt_stack_pointer) + 10001d4: dec00014 ori sp,sp,0 + + /* Set up the global pointer. */ + movhi gp, %hi(_gp) + 10001d8: 068040b4 movhi gp,258 + ori gp, gp, %lo(_gp) + 10001dc: d68b8d14 ori gp,gp,11828 + */ +#ifndef ALT_SIM_OPTIMIZE + /* Log that the BSS is about to be cleared. */ + ALT_LOG_PUTS(alt_log_msg_bss) + + movhi r2, %hi(__bss_start) + 10001e0: 00804074 movhi r2,257 + ori r2, r2, %lo(__bss_start) + 10001e4: 10b2fa14 ori r2,r2,52200 + + movhi r3, %hi(__bss_end) + 10001e8: 00c040b4 movhi r3,258 + ori r3, r3, %lo(__bss_end) + 10001ec: 18da6214 ori r3,r3,27016 + + beq r2, r3, 1f + 10001f0: 10c00326 beq r2,r3,1000200 <_start+0x40> + +0: + stw zero, (r2) + 10001f4: 10000015 stw zero,0(r2) + addi r2, r2, 4 + 10001f8: 10800104 addi r2,r2,4 + bltu r2, r3, 0b + 10001fc: 10fffd36 bltu r2,r3,10001f4 <_start+0x34> + * section aren't defined until alt_load() has been called). + */ + mov et, zero +#endif + + call alt_load + 1000200: 100c8780 call 100c878 + + /* Log that alt_main is about to be called. */ + ALT_LOG_PUTS(alt_log_msg_alt_main) + + /* Call the C entry point. It should never return. */ + call alt_main + 1000204: 100cab40 call 100cab4 + +01000208 : + + /* Wait in infinite loop in case alt_main does return. */ +alt_after_alt_main: + br alt_after_alt_main + 1000208: 003fff06 br 1000208 + +0100020c <_ZN12MotorHandlerC2Ev>: + +#include "MotorHandler.h" +#include "includes.h" +#include "altera_avalon_uart_regs.h" + +MotorHandler::MotorHandler() { + 100020c: defffe04 addi sp,sp,-8 + 1000210: df000115 stw fp,4(sp) + 1000214: df000104 addi fp,sp,4 + 1000218: e13fff15 stw r4,-4(fp) + 100021c: 00c040b4 movhi r3,258 + 1000220: 18e2f704 addi r3,r3,-29732 + 1000224: e0bfff17 ldw r2,-4(fp) + 1000228: 10c00015 stw r3,0(r2) + // TODO Auto-generated constructor stub + +} + 100022c: e037883a mov sp,fp + 1000230: df000017 ldw fp,0(sp) + 1000234: dec00104 addi sp,sp,4 + 1000238: f800283a ret + +0100023c <_ZN12MotorHandlerC1Ev>: + +#include "MotorHandler.h" +#include "includes.h" +#include "altera_avalon_uart_regs.h" + +MotorHandler::MotorHandler() { + 100023c: defffe04 addi sp,sp,-8 + 1000240: df000115 stw fp,4(sp) + 1000244: df000104 addi fp,sp,4 + 1000248: e13fff15 stw r4,-4(fp) + 100024c: 00c040b4 movhi r3,258 + 1000250: 18e2f704 addi r3,r3,-29732 + 1000254: e0bfff17 ldw r2,-4(fp) + 1000258: 10c00015 stw r3,0(r2) + // TODO Auto-generated constructor stub + +} + 100025c: e037883a mov sp,fp + 1000260: df000017 ldw fp,0(sp) + 1000264: dec00104 addi sp,sp,4 + 1000268: f800283a ret + +0100026c <_ZN12MotorHandler10sendByteMCEc>: + +MotorHandler::~MotorHandler() { + // TODO Auto-generated destructor stub +} +void MotorHandler::sendByteMC(char msg){ + 100026c: defffd04 addi sp,sp,-12 + 1000270: df000215 stw fp,8(sp) + 1000274: df000204 addi fp,sp,8 + 1000278: e13ffe15 stw r4,-8(fp) + 100027c: e17fff05 stb r5,-4(fp) + IOWR_ALTERA_AVALON_UART_TXDATA(UART_MC_BASE, msg); + 1000280: e0ffff07 ldb r3,-4(fp) + 1000284: 00808034 movhi r2,512 + 1000288: 10840104 addi r2,r2,4100 + 100028c: 10c00035 stwio r3,0(r2) +} + 1000290: e037883a mov sp,fp + 1000294: df000017 ldw fp,0(sp) + 1000298: dec00104 addi sp,sp,4 + 100029c: f800283a ret + +010002a0 <_ZN12MotorHandler7mc_stopEv>: + sendByteMC(MOTOR_START_BYTE); + sendByteMC(MOTOR_DEVICE_TYPE); + sendByteMC(MOTOR_MOTOR3_FORWARD); + sendByteMC(MOTOR_CONST_SPEED); +} +void MotorHandler::mc_stop(){ + 10002a0: defffd04 addi sp,sp,-12 + 10002a4: dfc00215 stw ra,8(sp) + 10002a8: df000115 stw fp,4(sp) + 10002ac: df000104 addi fp,sp,4 + 10002b0: e13fff15 stw r4,-4(fp) + //motor1 + sendByteMC(MOTOR_START_BYTE); + 10002b4: e13fff17 ldw r4,-4(fp) + 10002b8: 017fe004 movi r5,-128 + 10002bc: 100026c0 call 100026c <_ZN12MotorHandler10sendByteMCEc> + sendByteMC(MOTOR_DEVICE_TYPE); + 10002c0: e13fff17 ldw r4,-4(fp) + 10002c4: 000b883a mov r5,zero + 10002c8: 100026c0 call 100026c <_ZN12MotorHandler10sendByteMCEc> + sendByteMC(MOTOR_MOTOR2_FORWARD); + 10002cc: e13fff17 ldw r4,-4(fp) + 10002d0: 01400144 movi r5,5 + 10002d4: 100026c0 call 100026c <_ZN12MotorHandler10sendByteMCEc> + sendByteMC(MOTOR_STOP_SPEED); + 10002d8: e13fff17 ldw r4,-4(fp) + 10002dc: 000b883a mov r5,zero + 10002e0: 100026c0 call 100026c <_ZN12MotorHandler10sendByteMCEc> + //motor 2 + sendByteMC(MOTOR_START_BYTE); + 10002e4: e13fff17 ldw r4,-4(fp) + 10002e8: 017fe004 movi r5,-128 + 10002ec: 100026c0 call 100026c <_ZN12MotorHandler10sendByteMCEc> + sendByteMC(MOTOR_DEVICE_TYPE); + 10002f0: e13fff17 ldw r4,-4(fp) + 10002f4: 000b883a mov r5,zero + 10002f8: 100026c0 call 100026c <_ZN12MotorHandler10sendByteMCEc> + sendByteMC(MOTOR_MOTOR3_FORWARD); + 10002fc: e13fff17 ldw r4,-4(fp) + 1000300: 014001c4 movi r5,7 + 1000304: 100026c0 call 100026c <_ZN12MotorHandler10sendByteMCEc> + sendByteMC(MOTOR_STOP_SPEED); + 1000308: e13fff17 ldw r4,-4(fp) + 100030c: 000b883a mov r5,zero + 1000310: 100026c0 call 100026c <_ZN12MotorHandler10sendByteMCEc> +} + 1000314: e037883a mov sp,fp + 1000318: dfc00117 ldw ra,4(sp) + 100031c: df000017 ldw fp,0(sp) + 1000320: dec00204 addi sp,sp,8 + 1000324: f800283a ret + +01000328 <_ZN12MotorHandler8mc_rightEv>: + sendByteMC(MOTOR_DEVICE_TYPE); + sendByteMC(MOTOR_MOTOR2_FORWARD); + sendByteMC(MOTOR_CONST_SPEED); +} + +void MotorHandler::mc_right(){ + 1000328: defffd04 addi sp,sp,-12 + 100032c: dfc00215 stw ra,8(sp) + 1000330: df000115 stw fp,4(sp) + 1000334: df000104 addi fp,sp,4 + 1000338: e13fff15 stw r4,-4(fp) + //Turn Right by driving right motor only + + //motor 1 + sendByteMC(MOTOR_START_BYTE); + 100033c: e13fff17 ldw r4,-4(fp) + 1000340: 017fe004 movi r5,-128 + 1000344: 100026c0 call 100026c <_ZN12MotorHandler10sendByteMCEc> + sendByteMC(MOTOR_DEVICE_TYPE); + 1000348: e13fff17 ldw r4,-4(fp) + 100034c: 000b883a mov r5,zero + 1000350: 100026c0 call 100026c <_ZN12MotorHandler10sendByteMCEc> + sendByteMC(MOTOR_MOTOR3_FORWARD); + 1000354: e13fff17 ldw r4,-4(fp) + 1000358: 014001c4 movi r5,7 + 100035c: 100026c0 call 100026c <_ZN12MotorHandler10sendByteMCEc> + sendByteMC(MOTOR_CONST_SPEED); + 1000360: e13fff17 ldw r4,-4(fp) + 1000364: 014017c4 movi r5,95 + 1000368: 100026c0 call 100026c <_ZN12MotorHandler10sendByteMCEc> +} + 100036c: e037883a mov sp,fp + 1000370: dfc00117 ldw ra,4(sp) + 1000374: df000017 ldw fp,0(sp) + 1000378: dec00204 addi sp,sp,8 + 100037c: f800283a ret + +01000380 <_ZN12MotorHandler7mc_leftEv>: + sendByteMC(MOTOR_CONST_SPEED); +} +/* + * Turn rover left + */ +void MotorHandler::mc_left(){ + 1000380: defffd04 addi sp,sp,-12 + 1000384: dfc00215 stw ra,8(sp) + 1000388: df000115 stw fp,4(sp) + 100038c: df000104 addi fp,sp,4 + 1000390: e13fff15 stw r4,-4(fp) + //Turn Left by driving the left motor only + + //motor 1 + sendByteMC(MOTOR_START_BYTE); + 1000394: e13fff17 ldw r4,-4(fp) + 1000398: 017fe004 movi r5,-128 + 100039c: 100026c0 call 100026c <_ZN12MotorHandler10sendByteMCEc> + sendByteMC(MOTOR_DEVICE_TYPE); + 10003a0: e13fff17 ldw r4,-4(fp) + 10003a4: 000b883a mov r5,zero + 10003a8: 100026c0 call 100026c <_ZN12MotorHandler10sendByteMCEc> + sendByteMC(MOTOR_MOTOR2_FORWARD); + 10003ac: e13fff17 ldw r4,-4(fp) + 10003b0: 01400144 movi r5,5 + 10003b4: 100026c0 call 100026c <_ZN12MotorHandler10sendByteMCEc> + sendByteMC(MOTOR_CONST_SPEED); + 10003b8: e13fff17 ldw r4,-4(fp) + 10003bc: 014017c4 movi r5,95 + 10003c0: 100026c0 call 100026c <_ZN12MotorHandler10sendByteMCEc> +} + 10003c4: e037883a mov sp,fp + 10003c8: dfc00117 ldw ra,4(sp) + 10003cc: df000017 ldw fp,0(sp) + 10003d0: dec00204 addi sp,sp,8 + 10003d4: f800283a ret + +010003d8 <_ZN12MotorHandler11mc_backwardEv>: + sendByteMC(MOTOR_CONST_SPEED); +} +/* + * Move rover backward by activating both motor backwards + */ +void MotorHandler::mc_backward(){ + 10003d8: defffd04 addi sp,sp,-12 + 10003dc: dfc00215 stw ra,8(sp) + 10003e0: df000115 stw fp,4(sp) + 10003e4: df000104 addi fp,sp,4 + 10003e8: e13fff15 stw r4,-4(fp) + //motor 1 + sendByteMC(MOTOR_START_BYTE); + 10003ec: e13fff17 ldw r4,-4(fp) + 10003f0: 017fe004 movi r5,-128 + 10003f4: 100026c0 call 100026c <_ZN12MotorHandler10sendByteMCEc> + sendByteMC(MOTOR_DEVICE_TYPE); + 10003f8: e13fff17 ldw r4,-4(fp) + 10003fc: 000b883a mov r5,zero + 1000400: 100026c0 call 100026c <_ZN12MotorHandler10sendByteMCEc> + sendByteMC(MOTOR_MOTOR2_BACKWARD); + 1000404: e13fff17 ldw r4,-4(fp) + 1000408: 01400104 movi r5,4 + 100040c: 100026c0 call 100026c <_ZN12MotorHandler10sendByteMCEc> + sendByteMC(MOTOR_CONST_SPEED); + 1000410: e13fff17 ldw r4,-4(fp) + 1000414: 014017c4 movi r5,95 + 1000418: 100026c0 call 100026c <_ZN12MotorHandler10sendByteMCEc> + //motor 2 + sendByteMC(MOTOR_START_BYTE); + 100041c: e13fff17 ldw r4,-4(fp) + 1000420: 017fe004 movi r5,-128 + 1000424: 100026c0 call 100026c <_ZN12MotorHandler10sendByteMCEc> + sendByteMC(MOTOR_DEVICE_TYPE); + 1000428: e13fff17 ldw r4,-4(fp) + 100042c: 000b883a mov r5,zero + 1000430: 100026c0 call 100026c <_ZN12MotorHandler10sendByteMCEc> + sendByteMC(MOTOR_MOTOR3_BACKWARD); + 1000434: e13fff17 ldw r4,-4(fp) + 1000438: 01400184 movi r5,6 + 100043c: 100026c0 call 100026c <_ZN12MotorHandler10sendByteMCEc> + sendByteMC(MOTOR_CONST_SPEED); + 1000440: e13fff17 ldw r4,-4(fp) + 1000444: 014017c4 movi r5,95 + 1000448: 100026c0 call 100026c <_ZN12MotorHandler10sendByteMCEc> +} + 100044c: e037883a mov sp,fp + 1000450: dfc00117 ldw ra,4(sp) + 1000454: df000017 ldw fp,0(sp) + 1000458: dec00204 addi sp,sp,8 + 100045c: f800283a ret + +01000460 <_ZN12MotorHandler10mc_forwardEv>: + IOWR_ALTERA_AVALON_UART_TXDATA(UART_MC_BASE, msg); +} +/* + * Move rover forward by activating both motors + */ +void MotorHandler::mc_forward(){ + 1000460: defffd04 addi sp,sp,-12 + 1000464: dfc00215 stw ra,8(sp) + 1000468: df000115 stw fp,4(sp) + 100046c: df000104 addi fp,sp,4 + 1000470: e13fff15 stw r4,-4(fp) + //motor 1 + sendByteMC(MOTOR_START_BYTE); + 1000474: e13fff17 ldw r4,-4(fp) + 1000478: 017fe004 movi r5,-128 + 100047c: 100026c0 call 100026c <_ZN12MotorHandler10sendByteMCEc> + sendByteMC(MOTOR_DEVICE_TYPE); + 1000480: e13fff17 ldw r4,-4(fp) + 1000484: 000b883a mov r5,zero + 1000488: 100026c0 call 100026c <_ZN12MotorHandler10sendByteMCEc> + sendByteMC(MOTOR_MOTOR2_FORWARD); + 100048c: e13fff17 ldw r4,-4(fp) + 1000490: 01400144 movi r5,5 + 1000494: 100026c0 call 100026c <_ZN12MotorHandler10sendByteMCEc> + sendByteMC(MOTOR_CONST_SPEED); + 1000498: e13fff17 ldw r4,-4(fp) + 100049c: 014017c4 movi r5,95 + 10004a0: 100026c0 call 100026c <_ZN12MotorHandler10sendByteMCEc> + //motor 2 + sendByteMC(MOTOR_START_BYTE); + 10004a4: e13fff17 ldw r4,-4(fp) + 10004a8: 017fe004 movi r5,-128 + 10004ac: 100026c0 call 100026c <_ZN12MotorHandler10sendByteMCEc> + sendByteMC(MOTOR_DEVICE_TYPE); + 10004b0: e13fff17 ldw r4,-4(fp) + 10004b4: 000b883a mov r5,zero + 10004b8: 100026c0 call 100026c <_ZN12MotorHandler10sendByteMCEc> + sendByteMC(MOTOR_MOTOR3_FORWARD); + 10004bc: e13fff17 ldw r4,-4(fp) + 10004c0: 014001c4 movi r5,7 + 10004c4: 100026c0 call 100026c <_ZN12MotorHandler10sendByteMCEc> + sendByteMC(MOTOR_CONST_SPEED); + 10004c8: e13fff17 ldw r4,-4(fp) + 10004cc: 014017c4 movi r5,95 + 10004d0: 100026c0 call 100026c <_ZN12MotorHandler10sendByteMCEc> +} + 10004d4: e037883a mov sp,fp + 10004d8: dfc00117 ldw ra,4(sp) + 10004dc: df000017 ldw fp,0(sp) + 10004e0: dec00204 addi sp,sp,8 + 10004e4: f800283a ret + +010004e8 <_ZN12MotorHandlerD0Ev>: +MotorHandler::MotorHandler() { + // TODO Auto-generated constructor stub + +} + +MotorHandler::~MotorHandler() { + 10004e8: defffd04 addi sp,sp,-12 + 10004ec: dfc00215 stw ra,8(sp) + 10004f0: df000115 stw fp,4(sp) + 10004f4: df000104 addi fp,sp,4 + 10004f8: e13fff15 stw r4,-4(fp) + 10004fc: 00c040b4 movhi r3,258 + 1000500: 18e2f704 addi r3,r3,-29732 + 1000504: e0bfff17 ldw r2,-4(fp) + 1000508: 10c00015 stw r3,0(r2) + // TODO Auto-generated destructor stub +} + 100050c: 00800044 movi r2,1 + 1000510: 10803fcc andi r2,r2,255 + 1000514: 1005003a cmpeq r2,r2,zero + 1000518: 1000021e bne r2,zero,1000524 <_ZN12MotorHandlerD0Ev+0x3c> + 100051c: e13fff17 ldw r4,-4(fp) + 1000520: 1001b240 call 1001b24 <_ZdlPv> + 1000524: e037883a mov sp,fp + 1000528: dfc00117 ldw ra,4(sp) + 100052c: df000017 ldw fp,0(sp) + 1000530: dec00204 addi sp,sp,8 + 1000534: f800283a ret + +01000538 <_ZN12MotorHandlerD1Ev>: +MotorHandler::MotorHandler() { + // TODO Auto-generated constructor stub + +} + +MotorHandler::~MotorHandler() { + 1000538: defffd04 addi sp,sp,-12 + 100053c: dfc00215 stw ra,8(sp) + 1000540: df000115 stw fp,4(sp) + 1000544: df000104 addi fp,sp,4 + 1000548: e13fff15 stw r4,-4(fp) + 100054c: 00c040b4 movhi r3,258 + 1000550: 18e2f704 addi r3,r3,-29732 + 1000554: e0bfff17 ldw r2,-4(fp) + 1000558: 10c00015 stw r3,0(r2) + // TODO Auto-generated destructor stub +} + 100055c: 0005883a mov r2,zero + 1000560: 10803fcc andi r2,r2,255 + 1000564: 1005003a cmpeq r2,r2,zero + 1000568: 1000021e bne r2,zero,1000574 <_ZN12MotorHandlerD1Ev+0x3c> + 100056c: e13fff17 ldw r4,-4(fp) + 1000570: 1001b240 call 1001b24 <_ZdlPv> + 1000574: e037883a mov sp,fp + 1000578: dfc00117 ldw ra,4(sp) + 100057c: df000017 ldw fp,0(sp) + 1000580: dec00204 addi sp,sp,8 + 1000584: f800283a ret + +01000588 <_ZN12MotorHandlerD2Ev>: +MotorHandler::MotorHandler() { + // TODO Auto-generated constructor stub + +} + +MotorHandler::~MotorHandler() { + 1000588: defffd04 addi sp,sp,-12 + 100058c: dfc00215 stw ra,8(sp) + 1000590: df000115 stw fp,4(sp) + 1000594: df000104 addi fp,sp,4 + 1000598: e13fff15 stw r4,-4(fp) + 100059c: 00c040b4 movhi r3,258 + 10005a0: 18e2f704 addi r3,r3,-29732 + 10005a4: e0bfff17 ldw r2,-4(fp) + 10005a8: 10c00015 stw r3,0(r2) + // TODO Auto-generated destructor stub +} + 10005ac: 0005883a mov r2,zero + 10005b0: 10803fcc andi r2,r2,255 + 10005b4: 1005003a cmpeq r2,r2,zero + 10005b8: 1000021e bne r2,zero,10005c4 <_ZN12MotorHandlerD2Ev+0x3c> + 10005bc: e13fff17 ldw r4,-4(fp) + 10005c0: 1001b240 call 1001b24 <_ZdlPv> + 10005c4: e037883a mov sp,fp + 10005c8: dfc00117 ldw ra,4(sp) + 10005cc: df000017 ldw fp,0(sp) + 10005d0: dec00204 addi sp,sp,8 + 10005d4: f800283a ret + +010005d8 <_Z41__static_initialization_and_destruction_0ii>: + if (status == OK) { + OSStart(); + } + + return 0; +} + 10005d8: deffe404 addi sp,sp,-112 + 10005dc: dfc01b15 stw ra,108(sp) + 10005e0: df001a15 stw fp,104(sp) + 10005e4: ddc01915 stw r23,100(sp) + 10005e8: dd801815 stw r22,96(sp) + 10005ec: dd401715 stw r21,92(sp) + 10005f0: dd001615 stw r20,88(sp) + 10005f4: dcc01515 stw r19,84(sp) + 10005f8: dc801415 stw r18,80(sp) + 10005fc: dc401315 stw r17,76(sp) + 1000600: dc001215 stw r16,72(sp) + 1000604: df001204 addi fp,sp,72 + 1000608: e13fee15 stw r4,-72(fp) + 100060c: e17fef15 stw r5,-68(fp) + 1000610: 00804034 movhi r2,256 + 1000614: 1084d504 addi r2,r2,4948 + 1000618: e0bff615 stw r2,-40(fp) + 100061c: 008040b4 movhi r2,258 + 1000620: 10a2d804 addi r2,r2,-29856 + 1000624: e0bff715 stw r2,-36(fp) + 1000628: e0bff804 addi r2,fp,-32 + 100062c: e0ffee04 addi r3,fp,-72 + 1000630: 10c00015 stw r3,0(r2) + 1000634: 00c04034 movhi r3,256 + 1000638: 18c1a504 addi r3,r3,1684 + 100063c: 10c00115 stw r3,4(r2) + 1000640: 16c00215 stw sp,8(r2) + 1000644: e13ff004 addi r4,fp,-64 + 1000648: 10022540 call 1002254 <_Unwind_SjLj_Register> + 100064c: e0bfee17 ldw r2,-72(fp) + 1000650: 10800058 cmpnei r2,r2,1 + 1000654: 10001c1e bne r2,zero,10006c8 <_Z41__static_initialization_and_destruction_0ii+0xf0> + 1000658: e0ffef17 ldw r3,-68(fp) + 100065c: 00bfffd4 movui r2,65535 + 1000660: 1880191e bne r3,r2,10006c8 <_Z41__static_initialization_and_destruction_0ii+0xf0> +#include "altera_avalon_uart_regs.h" +#include "sys/alt_irq.h" +#include "alt_types.h" +#include "MotorHandler.h" + +MotorHandler * motorHandler = new MotorHandler(); + 1000664: 00bfffc4 movi r2,-1 + 1000668: e0bff115 stw r2,-60(fp) + 100066c: 01000104 movi r4,4 + 1000670: 100200c0 call 100200c <_Znwm> + 1000674: e0bffe15 stw r2,-8(fp) + 1000678: 00800044 movi r2,1 + 100067c: e0bff115 stw r2,-60(fp) + 1000680: e13ffe17 ldw r4,-8(fp) + 1000684: 100023c0 call 100023c <_ZN12MotorHandlerC1Ev> + 1000688: e0bffe17 ldw r2,-8(fp) + 100068c: d0a76d15 stw r2,-25164(gp) + 1000690: 00000d06 br 10006c8 <_Z41__static_initialization_and_destruction_0ii+0xf0> + 1000694: e7001204 addi fp,fp,72 + 1000698: e0fff217 ldw r3,-56(fp) + 100069c: e0ffff15 stw r3,-4(fp) + 10006a0: e0bfff17 ldw r2,-4(fp) + 10006a4: e0bffd15 stw r2,-12(fp) + 10006a8: e13ffe17 ldw r4,-8(fp) + 10006ac: 1001b240 call 1001b24 <_ZdlPv> + 10006b0: e0fffd17 ldw r3,-12(fp) + 10006b4: e0ffff15 stw r3,-4(fp) + 10006b8: 00bfffc4 movi r2,-1 + 10006bc: e0bff115 stw r2,-60(fp) + 10006c0: e13fff17 ldw r4,-4(fp) + 10006c4: 10025200 call 1002520 <_Unwind_SjLj_Resume> + 10006c8: e13ff004 addi r4,fp,-64 + 10006cc: 10022640 call 1002264 <_Unwind_SjLj_Unregister> + if (status == OK) { + OSStart(); + } + + return 0; +} + 10006d0: e037883a mov sp,fp + 10006d4: dfc00917 ldw ra,36(sp) + 10006d8: df000817 ldw fp,32(sp) + 10006dc: ddc00717 ldw r23,28(sp) + 10006e0: dd800617 ldw r22,24(sp) + 10006e4: dd400517 ldw r21,20(sp) + 10006e8: dd000417 ldw r20,16(sp) + 10006ec: dcc00317 ldw r19,12(sp) + 10006f0: dc800217 ldw r18,8(sp) + 10006f4: dc400117 ldw r17,4(sp) + 10006f8: dc000017 ldw r16,0(sp) + 10006fc: dec00a04 addi sp,sp,40 + 1000700: f800283a ret + +01000704 <_GLOBAL__I_motorHandler>: + + 1000704: defffe04 addi sp,sp,-8 + 1000708: dfc00115 stw ra,4(sp) + 100070c: df000015 stw fp,0(sp) + 1000710: d839883a mov fp,sp + 1000714: 01000044 movi r4,1 + 1000718: 017fffd4 movui r5,65535 + 100071c: 10005d80 call 10005d8 <_Z41__static_initialization_and_destruction_0ii> + 1000720: e037883a mov sp,fp + 1000724: dfc00117 ldw ra,4(sp) + 1000728: df000017 ldw fp,0(sp) + 100072c: dec00204 addi sp,sp,8 + 1000730: f800283a ret + +01000734 <_Z10wifi_writePci>: + +void wifi_wait() { + OSTimeDlyHMSM(0, 0, WIFI_GUARD_TIME, 0); +} + +void wifi_write(char *message, int length) { + 1000734: defffc04 addi sp,sp,-16 + 1000738: df000315 stw fp,12(sp) + 100073c: df000304 addi fp,sp,12 + 1000740: e13ffe15 stw r4,-8(fp) + 1000744: e17fff15 stw r5,-4(fp) + int i; + for (i = 0; i < length; i++) { + 1000748: e03ffd15 stw zero,-12(fp) + 100074c: 00000e06 br 1000788 <_Z10wifi_writePci+0x54> + IOWR_ALTERA_AVALON_UART_TXDATA(UART_WIFI_BASE, message[i]); + 1000750: e0bffd17 ldw r2,-12(fp) + 1000754: 1007883a mov r3,r2 + 1000758: e0bffe17 ldw r2,-8(fp) + 100075c: 1885883a add r2,r3,r2 + 1000760: 10800003 ldbu r2,0(r2) + 1000764: 10c03fcc andi r3,r2,255 + 1000768: 18c0201c xori r3,r3,128 + 100076c: 18ffe004 addi r3,r3,-128 + 1000770: 00808034 movhi r2,512 + 1000774: 10841104 addi r2,r2,4164 + 1000778: 10c00035 stwio r3,0(r2) + OSTimeDlyHMSM(0, 0, WIFI_GUARD_TIME, 0); +} + +void wifi_write(char *message, int length) { + int i; + for (i = 0; i < length; i++) { + 100077c: e0bffd17 ldw r2,-12(fp) + 1000780: 10800044 addi r2,r2,1 + 1000784: e0bffd15 stw r2,-12(fp) + 1000788: e0fffd17 ldw r3,-12(fp) + 100078c: e0bfff17 ldw r2,-4(fp) + 1000790: 18bfef16 blt r3,r2,1000750 <_Z10wifi_writePci+0x1c> + IOWR_ALTERA_AVALON_UART_TXDATA(UART_WIFI_BASE, message[i]); + } +} + 1000794: e037883a mov sp,fp + 1000798: df000017 ldw fp,0(sp) + 100079c: dec00104 addi sp,sp,4 + 10007a0: f800283a ret + +010007a4 <_Z10queue_initv>: + motorHandler->mc_stop(); +} + +// ==== GENERAL + +void queue_init() { + 10007a4: defffe04 addi sp,sp,-8 + 10007a8: dfc00115 stw ra,4(sp) + 10007ac: df000015 stw fp,0(sp) + 10007b0: d839883a mov fp,sp + ir_queue = OSQCreate((void**)&ir_messages, IR_MAX_MESSAGES); + 10007b4: 010040b4 movhi r4,258 + 10007b8: 210b2704 addi r4,r4,11420 + 10007bc: 01400104 movi r5,4 + 10007c0: 10117c40 call 10117c4 + 10007c4: d0a76e15 stw r2,-25160(gp) +} + 10007c8: e037883a mov sp,fp + 10007cc: dfc00117 ldw ra,4(sp) + 10007d0: df000017 ldw fp,0(sp) + 10007d4: dec00204 addi sp,sp,8 + 10007d8: f800283a ret + +010007dc
: + +/* The main function creates the LCD task, registers the edge counter polling interrupt, + * and starts the OS. */ +int main(void) + 10007dc: defff804 addi sp,sp,-32 + 10007e0: dfc00715 stw ra,28(sp) + 10007e4: df000615 stw fp,24(sp) + 10007e8: df000604 addi fp,sp,24 +{ + int status; + // Initialize components. + queue_init(); + 10007ec: 10007a40 call 10007a4 <_Z10queue_initv> + IR_TASK_PRIORITY, + IR_TASK_PRIORITY, + ir_task_stk, + TASK_STACKSIZE, + NULL, + 0); + 10007f0: 00800044 movi r2,1 + 10007f4: d8800015 stw r2,0(sp) + 10007f8: 008040b4 movhi r2,258 + 10007fc: 10b32704 addi r2,r2,-13156 + 1000800: d8800115 stw r2,4(sp) + 1000804: 00820004 movi r2,2048 + 1000808: d8800215 stw r2,8(sp) + 100080c: d8000315 stw zero,12(sp) + 1000810: d8000415 stw zero,16(sp) + 1000814: 01004034 movhi r4,256 + 1000818: 21028804 addi r4,r4,2592 + 100081c: 000b883a mov r5,zero + 1000820: 018040b4 movhi r6,258 + 1000824: 31bb2604 addi r6,r6,-4968 + 1000828: 01c00044 movi r7,1 + 100082c: 1013cb40 call 1013cb4 + WIFI_TASK_PRIORITY, + WIFI_TASK_PRIORITY, + wifi_task_stk, + TASK_STACKSIZE, + NULL, + 0); + 1000830: 00800084 movi r2,2 + 1000834: d8800015 stw r2,0(sp) + 1000838: 008040b4 movhi r2,258 + 100083c: 10bb2704 addi r2,r2,-4964 + 1000840: d8800115 stw r2,4(sp) + 1000844: 00820004 movi r2,2048 + 1000848: d8800215 stw r2,8(sp) + 100084c: d8000315 stw zero,12(sp) + 1000850: d8000415 stw zero,16(sp) + 1000854: 01004034 movhi r4,256 + 1000858: 21027404 addi r4,r4,2512 + 100085c: 000b883a mov r5,zero + 1000860: 018040b4 movhi r6,258 + 1000864: 31832604 addi r6,r6,3224 + 1000868: 01c00084 movi r7,2 + 100086c: 1013cb40 call 1013cb4 + MC_TASK_PRIORITY, + MC_TASK_PRIORITY, + mc_task_stk, + TASK_STACKSIZE, + NULL, + 0); + 1000870: 00800084 movi r2,2 + 1000874: d8800015 stw r2,0(sp) + 1000878: 008040b4 movhi r2,258 + 100087c: 10832704 addi r2,r2,3228 + 1000880: d8800115 stw r2,4(sp) + 1000884: 00820004 movi r2,2048 + 1000888: d8800215 stw r2,8(sp) + 100088c: d8000315 stw zero,12(sp) + 1000890: d8000415 stw zero,16(sp) + 1000894: 01004034 movhi r4,256 + 1000898: 21024804 addi r4,r4,2336 + 100089c: 000b883a mov r5,zero + 10008a0: 018040b4 movhi r6,258 + 10008a4: 318b2604 addi r6,r6,11416 + 10008a8: 01c00084 movi r7,2 + 10008ac: 1013cb40 call 1013cb4 + isr_on_ir_pushbutton, + NULL, + NULL);*/ + + // Enable key interrupts. + IOWR_ALTERA_AVALON_PIO_IRQ_MASK(PIO_KEY_LEFT_BASE, PIO_KEY_LEFT_CAPTURE); + 10008b0: 00c08034 movhi r3,512 + 10008b4: 18c42a04 addi r3,r3,4264 + 10008b8: 00800044 movi r2,1 + 10008bc: 18800035 stwio r2,0(r3) + + // Start. + if (status == OK) { + 10008c0: e0bfff17 ldw r2,-4(fp) + 10008c4: 1004c03a cmpne r2,r2,zero + 10008c8: 1000011e bne r2,zero,10008d0 + OSStart(); + 10008cc: 100dee00 call 100dee0 + } + + return 0; + 10008d0: 0005883a mov r2,zero +} + 10008d4: e037883a mov sp,fp + 10008d8: dfc00117 ldw ra,4(sp) + 10008dc: df000017 ldw fp,0(sp) + 10008e0: dec00204 addi sp,sp,8 + 10008e4: f800283a ret + +010008e8 <_Z9wifi_waitv>: + +// ==== WIFI + +#define WIFI_GUARD_TIME 1 + +void wifi_wait() { + 10008e8: defffe04 addi sp,sp,-8 + 10008ec: dfc00115 stw ra,4(sp) + 10008f0: df000015 stw fp,0(sp) + 10008f4: d839883a mov fp,sp + OSTimeDlyHMSM(0, 0, WIFI_GUARD_TIME, 0); + 10008f8: 0009883a mov r4,zero + 10008fc: 000b883a mov r5,zero + 1000900: 01800044 movi r6,1 + 1000904: 000f883a mov r7,zero + 1000908: 10150f80 call 10150f8 +} + 100090c: e037883a mov sp,fp + 1000910: dfc00117 ldw ra,4(sp) + 1000914: df000017 ldw fp,0(sp) + 1000918: dec00204 addi sp,sp,8 + 100091c: f800283a ret + +01000920 <_Z7mc_taskPv>: + +// ==== MC + + +//====MotorContoller +void mc_task(void *pdata) + 1000920: defffd04 addi sp,sp,-12 + 1000924: dfc00215 stw ra,8(sp) + 1000928: df000115 stw fp,4(sp) + 100092c: df000104 addi fp,sp,4 + 1000930: e13fff15 stw r4,-4(fp) +{ + motorHandler->mc_forward(); + 1000934: d1276d17 ldw r4,-25164(gp) + 1000938: 10004600 call 1000460 <_ZN12MotorHandler10mc_forwardEv> + OSTimeDlyHMSM(0, 0, 4, 0); + 100093c: 0009883a mov r4,zero + 1000940: 000b883a mov r5,zero + 1000944: 01800104 movi r6,4 + 1000948: 000f883a mov r7,zero + 100094c: 10150f80 call 10150f8 + motorHandler->mc_stop(); + 1000950: d1276d17 ldw r4,-25164(gp) + 1000954: 10002a00 call 10002a0 <_ZN12MotorHandler7mc_stopEv> +} + 1000958: e037883a mov sp,fp + 100095c: dfc00117 ldw ra,4(sp) + 1000960: df000017 ldw fp,0(sp) + 1000964: dec00204 addi sp,sp,8 + 1000968: f800283a ret + +0100096c <_Z9wifi_readv>: + for (i = 0; i < length; i++) { + IOWR_ALTERA_AVALON_UART_TXDATA(UART_WIFI_BASE, message[i]); + } +} + +void wifi_read() { + 100096c: defffc04 addi sp,sp,-16 + 1000970: dfc00315 stw ra,12(sp) + 1000974: df000215 stw fp,8(sp) + 1000978: df000204 addi fp,sp,8 + int status = IORD_ALTERA_AVALON_UART_STATUS(UART_WIFI_BASE); + 100097c: 00808034 movhi r2,512 + 1000980: 10841204 addi r2,r2,4168 + 1000984: 10800037 ldwio r2,0(r2) + 1000988: e0bfff15 stw r2,-4(fp) + printf("Wifi status: %d\n", status); + 100098c: 010040b4 movhi r4,258 + 1000990: 2122fd04 addi r4,r4,-29708 + 1000994: e17fff17 ldw r5,-4(fp) + 1000998: 1002fb40 call 1002fb4 + char c = IORD_ALTERA_AVALON_UART_RXDATA(UART_WIFI_BASE); + 100099c: 00808034 movhi r2,512 + 10009a0: 10841004 addi r2,r2,4160 + 10009a4: 10800037 ldwio r2,0(r2) + 10009a8: e0bffe05 stb r2,-8(fp) + printf("Wifi: %c\n", c); + 10009ac: e17ffe07 ldb r5,-8(fp) + 10009b0: 010040b4 movhi r4,258 + 10009b4: 21230204 addi r4,r4,-29688 + 10009b8: 1002fb40 call 1002fb4 +} + 10009bc: e037883a mov sp,fp + 10009c0: dfc00117 ldw ra,4(sp) + 10009c4: df000017 ldw fp,0(sp) + 10009c8: dec00204 addi sp,sp,8 + 10009cc: f800283a ret + +010009d0 <_Z9wifi_taskPv>: + +void wifi_task(void *pdata) + 10009d0: defffd04 addi sp,sp,-12 + 10009d4: dfc00215 stw ra,8(sp) + 10009d8: df000115 stw fp,4(sp) + 10009dc: df000104 addi fp,sp,4 + 10009e0: e13fff15 stw r4,-4(fp) +{ + printf("Started wifi task\n"); + 10009e4: 010040b4 movhi r4,258 + 10009e8: 21230504 addi r4,r4,-29676 + 10009ec: 10030cc0 call 10030cc + wifi_wait(); + 10009f0: 10008e80 call 10008e8 <_Z9wifi_waitv> + wifi_write("+++", 3); + 10009f4: 010040b4 movhi r4,258 + 10009f8: 21230a04 addi r4,r4,-29656 + 10009fc: 014000c4 movi r5,3 + 1000a00: 10007340 call 1000734 <_Z10wifi_writePci> + wifi_wait(); + 1000a04: 10008e80 call 10008e8 <_Z9wifi_waitv> + wifi_read(); + 1000a08: 100096c0 call 100096c <_Z9wifi_readv> +} + 1000a0c: e037883a mov sp,fp + 1000a10: dfc00117 ldw ra,4(sp) + 1000a14: df000017 ldw fp,0(sp) + 1000a18: dec00204 addi sp,sp,8 + 1000a1c: f800283a ret + +01000a20 <_Z7ir_taskPv>: + // Mask to mark the end of the ISR. + IOWR_ALTERA_AVALON_PIO_EDGE_CAP(PIO_KEY_LEFT_BASE, PIO_KEY_LEFT_BIT_CLEARING_EDGE_REGISTER); +} + +/* Controllers the IR emitter based on the value of the pushbutton. */ +void ir_task(void* pdata) + 1000a20: defffb04 addi sp,sp,-20 + 1000a24: dfc00415 stw ra,16(sp) + 1000a28: df000315 stw fp,12(sp) + 1000a2c: df000304 addi fp,sp,12 + 1000a30: e13fff15 stw r4,-4(fp) + 1000a34: 00000006 br 1000a38 <_Z7ir_taskPv+0x18> +{ + INT8U err; + while (1) + { + // Read the value from the queue. + int status = IR_QUEUE_RECEIVE_BASE - (int)OSQPend(ir_queue, WAIT_FOREVER, &err); + 1000a38: d1276e17 ldw r4,-25160(gp) + 1000a3c: e1bffe04 addi r6,fp,-8 + 1000a40: 000b883a mov r5,zero + 1000a44: 1011da00 call 1011da0 + 1000a48: 1007883a mov r3,r2 + 1000a4c: 00800084 movi r2,2 + 1000a50: 10c5c83a sub r2,r2,r3 + 1000a54: e0bffd15 stw r2,-12(fp) + if (err == OS_NO_ERR) { + 1000a58: e0bffe03 ldbu r2,-8(fp) + 1000a5c: 10803fcc andi r2,r2,255 + 1000a60: 1004c03a cmpne r2,r2,zero + 1000a64: 103ff41e bne r2,zero,1000a38 <_Z7ir_taskPv+0x18> + // Print the result and send it to the emitter. + printf("IR: %d\n", status); + 1000a68: 010040b4 movhi r4,258 + 1000a6c: 21230b04 addi r4,r4,-29652 + 1000a70: e17ffd17 ldw r5,-12(fp) + 1000a74: 1002fb40 call 1002fb4 + IOWR_ALTERA_AVALON_PIO_DATA(PIO_IR_EMITTER_BASE, status); + 1000a78: 00c08034 movhi r3,512 + 1000a7c: 18c42004 addi r3,r3,4224 + 1000a80: e0bffd17 ldw r2,-12(fp) + 1000a84: 18800035 stwio r2,0(r3) + +/* Controllers the IR emitter based on the value of the pushbutton. */ +void ir_task(void* pdata) +{ + INT8U err; + while (1) + 1000a88: 003feb06 br 1000a38 <_Z7ir_taskPv+0x18> + +01000a8c <_ZNK10__cxxabiv117__class_type_info11__do_upcastEPKS0_PPv>: + 1000a8c: 20c00017 ldw r3,0(r4) + 1000a90: defffa04 addi sp,sp,-24 + 1000a94: dc000415 stw r16,16(sp) + 1000a98: 1a000617 ldw r8,24(r3) + 1000a9c: 3021883a mov r16,r6 + 1000aa0: 31800017 ldw r6,0(r6) + 1000aa4: 00800404 movi r2,16 + 1000aa8: dfc00515 stw ra,20(sp) + 1000aac: d8800215 stw r2,8(sp) + 1000ab0: d8000015 stw zero,0(sp) + 1000ab4: d8000115 stw zero,4(sp) + 1000ab8: d8000315 stw zero,12(sp) + 1000abc: d80f883a mov r7,sp + 1000ac0: 403ee83a callr r8 + 1000ac4: d8800117 ldw r2,4(sp) + 1000ac8: 00c00184 movi r3,6 + 1000acc: 0009883a mov r4,zero + 1000ad0: 1080018c andi r2,r2,6 + 1000ad4: 10c0031e bne r2,r3,1000ae4 <_ZNK10__cxxabiv117__class_type_info11__do_upcastEPKS0_PPv+0x58> + 1000ad8: d8800017 ldw r2,0(sp) + 1000adc: 01000044 movi r4,1 + 1000ae0: 80800015 stw r2,0(r16) + 1000ae4: 2005883a mov r2,r4 + 1000ae8: dfc00517 ldw ra,20(sp) + 1000aec: dc000417 ldw r16,16(sp) + 1000af0: dec00604 addi sp,sp,24 + 1000af4: f800283a ret + +01000af8 <_ZNK10__cxxabiv117__class_type_info20__do_find_public_srcElPKvPKS0_S2_>: + 1000af8: d8800017 ldw r2,0(sp) + 1000afc: 00c00184 movi r3,6 + 1000b00: 1180021e bne r2,r6,1000b0c <_ZNK10__cxxabiv117__class_type_info20__do_find_public_srcElPKvPKS0_S2_+0x14> + 1000b04: 1805883a mov r2,r3 + 1000b08: f800283a ret + 1000b0c: 00c00044 movi r3,1 + 1000b10: 1805883a mov r2,r3 + 1000b14: f800283a ret + +01000b18 <_ZN10__cxxabiv117__class_type_infoD0Ev>: + 1000b18: defffe04 addi sp,sp,-8 + 1000b1c: 008040b4 movhi r2,258 + 1000b20: 10a30f04 addi r2,r2,-29636 + 1000b24: dc400015 stw r17,0(sp) + 1000b28: 20800015 stw r2,0(r4) + 1000b2c: 2023883a mov r17,r4 + 1000b30: dfc00115 stw ra,4(sp) + 1000b34: 1001e880 call 1001e88 <_ZNSt9type_infoD2Ev> + 1000b38: 8809883a mov r4,r17 + 1000b3c: dfc00117 ldw ra,4(sp) + 1000b40: dc400017 ldw r17,0(sp) + 1000b44: dec00204 addi sp,sp,8 + 1000b48: 1001b241 jmpi 1001b24 <_ZdlPv> + +01000b4c <_ZN10__cxxabiv117__class_type_infoD1Ev>: + 1000b4c: 008040b4 movhi r2,258 + 1000b50: 10a30f04 addi r2,r2,-29636 + 1000b54: 20800015 stw r2,0(r4) + 1000b58: 1001e881 jmpi 1001e88 <_ZNSt9type_infoD2Ev> + +01000b5c <_ZN10__cxxabiv117__class_type_infoD2Ev>: + 1000b5c: 008040b4 movhi r2,258 + 1000b60: 10a30f04 addi r2,r2,-29636 + 1000b64: 20800015 stw r2,0(r4) + 1000b68: 1001e881 jmpi 1001e88 <_ZNSt9type_infoD2Ev> + +01000b6c <_ZNK10__cxxabiv117__class_type_info10__do_catchEPKSt9type_infoPPvj>: + 1000b6c: 2811883a mov r8,r5 + 1000b70: 20c00117 ldw r3,4(r4) + 1000b74: 40800117 ldw r2,4(r8) + 1000b78: deffff04 addi sp,sp,-4 + 1000b7c: dfc00015 stw ra,0(sp) + 1000b80: 200b883a mov r5,r4 + 1000b84: 02400044 movi r9,1 + 1000b88: 18800426 beq r3,r2,1000b9c <_ZNK10__cxxabiv117__class_type_info10__do_catchEPKSt9type_infoPPvj+0x30> + 1000b8c: 008000c4 movi r2,3 + 1000b90: 4009883a mov r4,r8 + 1000b94: 0013883a mov r9,zero + 1000b98: 11c0042e bgeu r2,r7,1000bac <_ZNK10__cxxabiv117__class_type_info10__do_catchEPKSt9type_infoPPvj+0x40> + 1000b9c: 4805883a mov r2,r9 + 1000ba0: dfc00017 ldw ra,0(sp) + 1000ba4: dec00104 addi sp,sp,4 + 1000ba8: f800283a ret + 1000bac: 40800017 ldw r2,0(r8) + 1000bb0: 10c00517 ldw r3,20(r2) + 1000bb4: 183ee83a callr r3 + 1000bb8: 12403fcc andi r9,r2,255 + 1000bbc: 4805883a mov r2,r9 + 1000bc0: dfc00017 ldw ra,0(sp) + 1000bc4: dec00104 addi sp,sp,4 + 1000bc8: f800283a ret + +01000bcc <_ZNK10__cxxabiv117__class_type_info11__do_upcastEPKS0_PKvRNS0_15__upcast_resultE>: + 1000bcc: 20c00117 ldw r3,4(r4) + 1000bd0: 28800117 ldw r2,4(r5) + 1000bd4: 0009883a mov r4,zero + 1000bd8: 1880061e bne r3,r2,1000bf4 <_ZNK10__cxxabiv117__class_type_info11__do_upcastEPKS0_PKvRNS0_15__upcast_resultE+0x28> + 1000bdc: 00800184 movi r2,6 + 1000be0: 38800115 stw r2,4(r7) + 1000be4: 00800204 movi r2,8 + 1000be8: 39800015 stw r6,0(r7) + 1000bec: 38800315 stw r2,12(r7) + 1000bf0: 01000044 movi r4,1 + 1000bf4: 2005883a mov r2,r4 + 1000bf8: f800283a ret + +01000bfc <_ZNK10__cxxabiv117__class_type_info12__do_dyncastElNS0_10__sub_kindEPKS0_PKvS3_S5_RNS0_16__dyncast_resultE>: + 1000bfc: da000017 ldw r8,0(sp) + 1000c00: d8800217 ldw r2,8(sp) + 1000c04: d9400317 ldw r5,12(sp) + 1000c08: 40800926 beq r8,r2,1000c30 <_ZNK10__cxxabiv117__class_type_info12__do_dyncastElNS0_10__sub_kindEPKS0_PKvS3_S5_RNS0_16__dyncast_resultE+0x34> + 1000c0c: 21000117 ldw r4,4(r4) + 1000c10: 38800117 ldw r2,4(r7) + 1000c14: 2080041e bne r4,r2,1000c28 <_ZNK10__cxxabiv117__class_type_info12__do_dyncastElNS0_10__sub_kindEPKS0_PKvS3_S5_RNS0_16__dyncast_resultE+0x2c> + 1000c18: 00800044 movi r2,1 + 1000c1c: 28800315 stw r2,12(r5) + 1000c20: 2a000015 stw r8,0(r5) + 1000c24: 29800115 stw r6,4(r5) + 1000c28: 0005883a mov r2,zero + 1000c2c: f800283a ret + 1000c30: d8800117 ldw r2,4(sp) + 1000c34: 21000117 ldw r4,4(r4) + 1000c38: 10c00117 ldw r3,4(r2) + 1000c3c: 20fff41e bne r4,r3,1000c10 <_ZNK10__cxxabiv117__class_type_info12__do_dyncastElNS0_10__sub_kindEPKS0_PKvS3_S5_RNS0_16__dyncast_resultE+0x14> + 1000c40: 29800215 stw r6,8(r5) + 1000c44: 003ff806 br 1000c28 <_ZNK10__cxxabiv117__class_type_info12__do_dyncastElNS0_10__sub_kindEPKS0_PKvS3_S5_RNS0_16__dyncast_resultE+0x2c> + +01000c48 <_Z12read_uleb128PKhPj>: + 1000c48: 000d883a mov r6,zero + 1000c4c: 000f883a mov r7,zero + 1000c50: 20c00007 ldb r3,0(r4) + 1000c54: 21000044 addi r4,r4,1 + 1000c58: 18801fcc andi r2,r3,127 + 1000c5c: 1184983a sll r2,r2,r6 + 1000c60: 318001c4 addi r6,r6,7 + 1000c64: 388eb03a or r7,r7,r2 + 1000c68: 183ff916 blt r3,zero,1000c50 <_Z12read_uleb128PKhPj+0x8> + 1000c6c: 2005883a mov r2,r4 + 1000c70: 29c00015 stw r7,0(r5) + 1000c74: f800283a ret + +01000c78 <_Z12read_sleb128PKhPi>: + 1000c78: 000f883a mov r7,zero + 1000c7c: 0011883a mov r8,zero + 1000c80: 20c00007 ldb r3,0(r4) + 1000c84: 21000044 addi r4,r4,1 + 1000c88: 19803fcc andi r6,r3,255 + 1000c8c: 30801fcc andi r2,r6,127 + 1000c90: 11c4983a sll r2,r2,r7 + 1000c94: 39c001c4 addi r7,r7,7 + 1000c98: 4090b03a or r8,r8,r2 + 1000c9c: 183ff816 blt r3,zero,1000c80 <_Z12read_sleb128PKhPi+0x8> + 1000ca0: 008007c4 movi r2,31 + 1000ca4: 11c00636 bltu r2,r7,1000cc0 <_Z12read_sleb128PKhPi+0x48> + 1000ca8: 3080100c andi r2,r6,64 + 1000cac: 10000426 beq r2,zero,1000cc0 <_Z12read_sleb128PKhPi+0x48> + 1000cb0: 00800044 movi r2,1 + 1000cb4: 11c4983a sll r2,r2,r7 + 1000cb8: 0085c83a sub r2,zero,r2 + 1000cbc: 4090b03a or r8,r8,r2 + 1000cc0: 2005883a mov r2,r4 + 1000cc4: 2a000015 stw r8,0(r5) + 1000cc8: f800283a ret + +01000ccc <_Z16get_adjusted_ptrPKSt9type_infoS1_PPv>: + 1000ccc: 28800017 ldw r2,0(r5) + 1000cd0: defffb04 addi sp,sp,-20 + 1000cd4: 30c00017 ldw r3,0(r6) + 1000cd8: dc400215 stw r17,8(sp) + 1000cdc: 2823883a mov r17,r5 + 1000ce0: 11400217 ldw r5,8(r2) + 1000ce4: dc800315 stw r18,12(sp) + 1000ce8: dc000115 stw r16,4(sp) + 1000cec: dfc00415 stw ra,16(sp) + 1000cf0: 2021883a mov r16,r4 + 1000cf4: d8c00015 stw r3,0(sp) + 1000cf8: 8809883a mov r4,r17 + 1000cfc: 3025883a mov r18,r6 + 1000d00: 283ee83a callr r5 + 1000d04: 10803fcc andi r2,r2,255 + 1000d08: 880b883a mov r5,r17 + 1000d0c: 8009883a mov r4,r16 + 1000d10: d80d883a mov r6,sp + 1000d14: 01c00044 movi r7,1 + 1000d18: 10000326 beq r2,zero,1000d28 <_Z16get_adjusted_ptrPKSt9type_infoS1_PPv+0x5c> + 1000d1c: d8800017 ldw r2,0(sp) + 1000d20: 10c00017 ldw r3,0(r2) + 1000d24: d8c00015 stw r3,0(sp) + 1000d28: 80800017 ldw r2,0(r16) + 1000d2c: 10c00417 ldw r3,16(r2) + 1000d30: 183ee83a callr r3 + 1000d34: 10803fcc andi r2,r2,255 + 1000d38: 0007883a mov r3,zero + 1000d3c: 10000326 beq r2,zero,1000d4c <_Z16get_adjusted_ptrPKSt9type_infoS1_PPv+0x80> + 1000d40: d8800017 ldw r2,0(sp) + 1000d44: 00c00044 movi r3,1 + 1000d48: 90800015 stw r2,0(r18) + 1000d4c: 1805883a mov r2,r3 + 1000d50: dfc00417 ldw ra,16(sp) + 1000d54: dc800317 ldw r18,12(sp) + 1000d58: dc400217 ldw r17,8(sp) + 1000d5c: dc000117 ldw r16,4(sp) + 1000d60: dec00504 addi sp,sp,20 + 1000d64: f800283a ret + +01000d68 <_Z28read_encoded_value_with_basehjPKhPj>: + 1000d68: defff904 addi sp,sp,-28 + 1000d6c: dc400215 stw r17,8(sp) + 1000d70: 00801404 movi r2,80 + 1000d74: 24403fcc andi r17,r4,255 + 1000d78: dd000515 stw r20,20(sp) + 1000d7c: dcc00415 stw r19,16(sp) + 1000d80: dc800315 stw r18,12(sp) + 1000d84: dc000115 stw r16,4(sp) + 1000d88: dfc00615 stw ra,24(sp) + 1000d8c: 2025883a mov r18,r4 + 1000d90: 2829883a mov r20,r5 + 1000d94: 3021883a mov r16,r6 + 1000d98: 3827883a mov r19,r7 + 1000d9c: 88801826 beq r17,r2,1000e00 <_Z28read_encoded_value_with_basehjPKhPj+0x98> + 1000da0: 88c003cc andi r3,r17,15 + 1000da4: 00800304 movi r2,12 + 1000da8: 10c0012e bgeu r2,r3,1000db0 <_Z28read_encoded_value_with_basehjPKhPj+0x48> + 1000dac: 100279c0 call 100279c + 1000db0: 18c5883a add r2,r3,r3 + 1000db4: 1085883a add r2,r2,r2 + 1000db8: 00c04034 movhi r3,256 + 1000dbc: 18c37304 addi r3,r3,3532 + 1000dc0: 10c5883a add r2,r2,r3 + 1000dc4: 11000017 ldw r4,0(r2) + 1000dc8: 2000683a jmp r4 + 1000dcc: 01000e3c xorhi r4,zero,56 + 1000dd0: 01000f24 muli r4,zero,60 + 1000dd4: 01000ed0 cmplti r4,zero,59 + 1000dd8: 01000e3c xorhi r4,zero,56 + 1000ddc: 01000e94 movui r4,58 + 1000de0: 01000dac andhi r4,zero,54 + 1000de4: 01000dac andhi r4,zero,54 + 1000de8: 01000dac andhi r4,zero,54 + 1000dec: 01000dac andhi r4,zero,54 + 1000df0: 01000f0c andi r4,zero,60 + 1000df4: 01000ee8 cmpgeui r4,zero,59 + 1000df8: 01000e3c xorhi r4,zero,56 + 1000dfc: 01000e94 movui r4,58 + 1000e00: 308000c4 addi r2,r6,3 + 1000e04: 00ffff04 movi r3,-4 + 1000e08: 10c4703a and r2,r2,r3 + 1000e0c: 11000017 ldw r4,0(r2) + 1000e10: 11400104 addi r5,r2,4 + 1000e14: 2805883a mov r2,r5 + 1000e18: 99000015 stw r4,0(r19) + 1000e1c: dfc00617 ldw ra,24(sp) + 1000e20: dd000517 ldw r20,20(sp) + 1000e24: dcc00417 ldw r19,16(sp) + 1000e28: dc800317 ldw r18,12(sp) + 1000e2c: dc400217 ldw r17,8(sp) + 1000e30: dc000117 ldw r16,4(sp) + 1000e34: dec00704 addi sp,sp,28 + 1000e38: f800283a ret + 1000e3c: 30800043 ldbu r2,1(r6) + 1000e40: 30c00083 ldbu r3,2(r6) + 1000e44: 310000c3 ldbu r4,3(r6) + 1000e48: 31400003 ldbu r5,0(r6) + 1000e4c: 1004923a slli r2,r2,8 + 1000e50: 1806943a slli r3,r3,16 + 1000e54: 2008963a slli r4,r4,24 + 1000e58: 1144b03a or r2,r2,r5 + 1000e5c: 1886b03a or r3,r3,r2 + 1000e60: 20c8b03a or r4,r4,r3 + 1000e64: 31400104 addi r5,r6,4 + 1000e68: 203fea26 beq r4,zero,1000e14 <_Z28read_encoded_value_with_basehjPKhPj+0xac> + 1000e6c: 88c01c0c andi r3,r17,112 + 1000e70: 00800404 movi r2,16 + 1000e74: 18801426 beq r3,r2,1000ec8 <_Z28read_encoded_value_with_basehjPKhPj+0x160> + 1000e78: 90803fcc andi r2,r18,255 + 1000e7c: 1080201c xori r2,r2,128 + 1000e80: 10bfe004 addi r2,r2,-128 + 1000e84: 2509883a add r4,r4,r20 + 1000e88: 103fe20e bge r2,zero,1000e14 <_Z28read_encoded_value_with_basehjPKhPj+0xac> + 1000e8c: 21000017 ldw r4,0(r4) + 1000e90: 003fe006 br 1000e14 <_Z28read_encoded_value_with_basehjPKhPj+0xac> + 1000e94: 30800043 ldbu r2,1(r6) + 1000e98: 31800083 ldbu r6,2(r6) + 1000e9c: 820000c3 ldbu r8,3(r16) + 1000ea0: 1004923a slli r2,r2,8 + 1000ea4: 82400003 ldbu r9,0(r16) + 1000ea8: 300c943a slli r6,r6,16 + 1000eac: 4010963a slli r8,r8,24 + 1000eb0: 1244b03a or r2,r2,r9 + 1000eb4: 308cb03a or r6,r6,r2 + 1000eb8: 4184b03a or r2,r8,r6 + 1000ebc: 1009883a mov r4,r2 + 1000ec0: 81400204 addi r5,r16,8 + 1000ec4: 003fe806 br 1000e68 <_Z28read_encoded_value_with_basehjPKhPj+0x100> + 1000ec8: 8029883a mov r20,r16 + 1000ecc: 003fea06 br 1000e78 <_Z28read_encoded_value_with_basehjPKhPj+0x110> + 1000ed0: 30800043 ldbu r2,1(r6) + 1000ed4: 30c00003 ldbu r3,0(r6) + 1000ed8: 31400084 addi r5,r6,2 + 1000edc: 1004923a slli r2,r2,8 + 1000ee0: 10c8b03a or r4,r2,r3 + 1000ee4: 003fe006 br 1000e68 <_Z28read_encoded_value_with_basehjPKhPj+0x100> + 1000ee8: 30800043 ldbu r2,1(r6) + 1000eec: 30c00003 ldbu r3,0(r6) + 1000ef0: 31400084 addi r5,r6,2 + 1000ef4: 1004923a slli r2,r2,8 + 1000ef8: 10c4b03a or r2,r2,r3 + 1000efc: 113fffcc andi r4,r2,65535 + 1000f00: 2120001c xori r4,r4,32768 + 1000f04: 21200004 addi r4,r4,-32768 + 1000f08: 003fd706 br 1000e68 <_Z28read_encoded_value_with_basehjPKhPj+0x100> + 1000f0c: 3009883a mov r4,r6 + 1000f10: d80b883a mov r5,sp + 1000f14: 1000c780 call 1000c78 <_Z12read_sleb128PKhPi> + 1000f18: d9000017 ldw r4,0(sp) + 1000f1c: 100b883a mov r5,r2 + 1000f20: 003fd106 br 1000e68 <_Z28read_encoded_value_with_basehjPKhPj+0x100> + 1000f24: 3009883a mov r4,r6 + 1000f28: d80b883a mov r5,sp + 1000f2c: 1000c480 call 1000c48 <_Z12read_uleb128PKhPj> + 1000f30: d9000017 ldw r4,0(sp) + 1000f34: 100b883a mov r5,r2 + 1000f38: 003fcb06 br 1000e68 <_Z28read_encoded_value_with_basehjPKhPj+0x100> + +01000f3c <_Z21base_of_encoded_valuehP15_Unwind_Context>: + 1000f3c: deffff04 addi sp,sp,-4 + 1000f40: 21003fcc andi r4,r4,255 + 1000f44: 00803fc4 movi r2,255 + 1000f48: dfc00015 stw ra,0(sp) + 1000f4c: 20800c26 beq r4,r2,1000f80 <_Z21base_of_encoded_valuehP15_Unwind_Context+0x44> + 1000f50: 21001c0c andi r4,r4,112 + 1000f54: 00800804 movi r2,32 + 1000f58: 20800d26 beq r4,r2,1000f90 <_Z21base_of_encoded_valuehP15_Unwind_Context+0x54> + 1000f5c: 1100070e bge r2,r4,1000f7c <_Z21base_of_encoded_valuehP15_Unwind_Context+0x40> + 1000f60: 00801004 movi r2,64 + 1000f64: 20801126 beq r4,r2,1000fac <_Z21base_of_encoded_valuehP15_Unwind_Context+0x70> + 1000f68: 00801404 movi r2,80 + 1000f6c: 20800426 beq r4,r2,1000f80 <_Z21base_of_encoded_valuehP15_Unwind_Context+0x44> + 1000f70: 00800c04 movi r2,48 + 1000f74: 20801126 beq r4,r2,1000fbc <_Z21base_of_encoded_valuehP15_Unwind_Context+0x80> + 1000f78: 100279c0 call 100279c + 1000f7c: 2000081e bne r4,zero,1000fa0 <_Z21base_of_encoded_valuehP15_Unwind_Context+0x64> + 1000f80: 0005883a mov r2,zero + 1000f84: dfc00017 ldw ra,0(sp) + 1000f88: dec00104 addi sp,sp,4 + 1000f8c: f800283a ret + 1000f90: 2809883a mov r4,r5 + 1000f94: dfc00017 ldw ra,0(sp) + 1000f98: dec00104 addi sp,sp,4 + 1000f9c: 100230c1 jmpi 100230c <_Unwind_GetTextRelBase> + 1000fa0: 00800404 movi r2,16 + 1000fa4: 20bff626 beq r4,r2,1000f80 <_Z21base_of_encoded_valuehP15_Unwind_Context+0x44> + 1000fa8: 100279c0 call 100279c + 1000fac: 2809883a mov r4,r5 + 1000fb0: dfc00017 ldw ra,0(sp) + 1000fb4: dec00104 addi sp,sp,4 + 1000fb8: 10022f41 jmpi 10022f4 <_Unwind_GetRegionStart> + 1000fbc: 2809883a mov r4,r5 + 1000fc0: dfc00017 ldw ra,0(sp) + 1000fc4: dec00104 addi sp,sp,4 + 1000fc8: 10023041 jmpi 1002304 <_Unwind_GetDataRelBase> + +01000fcc <_Z17parse_lsda_headerP15_Unwind_ContextPKhP16lsda_header_info>: + 1000fcc: defffa04 addi sp,sp,-24 + 1000fd0: dc800415 stw r18,16(sp) + 1000fd4: dc400315 stw r17,12(sp) + 1000fd8: dc000215 stw r16,8(sp) + 1000fdc: dfc00515 stw ra,20(sp) + 1000fe0: 2021883a mov r16,r4 + 1000fe4: 000f883a mov r7,zero + 1000fe8: 3023883a mov r17,r6 + 1000fec: 2825883a mov r18,r5 + 1000ff0: 20000226 beq r4,zero,1000ffc <_Z17parse_lsda_headerP15_Unwind_ContextPKhP16lsda_header_info+0x30> + 1000ff4: 10022f40 call 10022f4 <_Unwind_GetRegionStart> + 1000ff8: 100f883a mov r7,r2 + 1000ffc: 89c00015 stw r7,0(r17) + 1001000: 90c00003 ldbu r3,0(r18) + 1001004: 800b883a mov r5,r16 + 1001008: 00803fc4 movi r2,255 + 100100c: 1c003fcc andi r16,r3,255 + 1001010: 91800044 addi r6,r18,1 + 1001014: 8009883a mov r4,r16 + 1001018: 18802226 beq r3,r2,10010a4 <_Z17parse_lsda_headerP15_Unwind_ContextPKhP16lsda_header_info+0xd8> + 100101c: d9800115 stw r6,4(sp) + 1001020: 1000f3c0 call 1000f3c <_Z21base_of_encoded_valuehP15_Unwind_Context> + 1001024: d9800117 ldw r6,4(sp) + 1001028: 8009883a mov r4,r16 + 100102c: 100b883a mov r5,r2 + 1001030: 89c00104 addi r7,r17,4 + 1001034: 1000d680 call 1000d68 <_Z28read_encoded_value_with_basehjPKhPj> + 1001038: 100d883a mov r6,r2 + 100103c: 30800003 ldbu r2,0(r6) + 1001040: 31c00044 addi r7,r6,1 + 1001044: 00c03fc4 movi r3,255 + 1001048: d80b883a mov r5,sp + 100104c: 3809883a mov r4,r7 + 1001050: 88800505 stb r2,20(r17) + 1001054: 10c01b26 beq r2,r3,10010c4 <_Z17parse_lsda_headerP15_Unwind_ContextPKhP16lsda_header_info+0xf8> + 1001058: 1000c480 call 1000c48 <_Z12read_uleb128PKhPj> + 100105c: 100f883a mov r7,r2 + 1001060: d8800017 ldw r2,0(sp) + 1001064: 3885883a add r2,r7,r2 + 1001068: 88800315 stw r2,12(r17) + 100106c: 38800003 ldbu r2,0(r7) + 1001070: 39000044 addi r4,r7,1 + 1001074: d80b883a mov r5,sp + 1001078: 88800545 stb r2,21(r17) + 100107c: 1000c480 call 1000c48 <_Z12read_uleb128PKhPj> + 1001080: d8c00017 ldw r3,0(sp) + 1001084: 10c9883a add r4,r2,r3 + 1001088: 89000415 stw r4,16(r17) + 100108c: dfc00517 ldw ra,20(sp) + 1001090: dc800417 ldw r18,16(sp) + 1001094: dc400317 ldw r17,12(sp) + 1001098: dc000217 ldw r16,8(sp) + 100109c: dec00604 addi sp,sp,24 + 10010a0: f800283a ret + 10010a4: 89c00115 stw r7,4(r17) + 10010a8: 30800003 ldbu r2,0(r6) + 10010ac: 31c00044 addi r7,r6,1 + 10010b0: 00c03fc4 movi r3,255 + 10010b4: d80b883a mov r5,sp + 10010b8: 3809883a mov r4,r7 + 10010bc: 88800505 stb r2,20(r17) + 10010c0: 10ffe51e bne r2,r3,1001058 <_Z17parse_lsda_headerP15_Unwind_ContextPKhP16lsda_header_info+0x8c> + 10010c4: 88000315 stw zero,12(r17) + 10010c8: 003fe806 br 100106c <_Z17parse_lsda_headerP15_Unwind_ContextPKhP16lsda_header_info+0xa0> + +010010cc <_Z15get_ttype_entryP16lsda_header_infoj>: + 10010cc: defffe04 addi sp,sp,-8 + 10010d0: dfc00115 stw ra,4(sp) + 10010d4: 21c00503 ldbu r7,20(r4) + 10010d8: 00803fc4 movi r2,255 + 10010dc: 38801a26 beq r7,r2,1001148 <_Z15get_ttype_entryP16lsda_header_infoj+0x7c> + 10010e0: 38c001cc andi r3,r7,7 + 10010e4: 00800084 movi r2,2 + 10010e8: 18801326 beq r3,r2,1001138 <_Z15get_ttype_entryP16lsda_header_infoj+0x6c> + 10010ec: 10c0050e bge r2,r3,1001104 <_Z15get_ttype_entryP16lsda_header_infoj+0x38> + 10010f0: 008000c4 movi r2,3 + 10010f4: 18800426 beq r3,r2,1001108 <_Z15get_ttype_entryP16lsda_header_infoj+0x3c> + 10010f8: 00800104 movi r2,4 + 10010fc: 18801026 beq r3,r2,1001140 <_Z15get_ttype_entryP16lsda_header_infoj+0x74> + 1001100: 100279c0 call 100279c + 1001104: 183ffe1e bne r3,zero,1001100 <_Z15get_ttype_entryP16lsda_header_infoj+0x34> + 1001108: 2945883a add r2,r5,r5 + 100110c: 1085883a add r2,r2,r2 + 1001110: 21800317 ldw r6,12(r4) + 1001114: 21400217 ldw r5,8(r4) + 1001118: 3809883a mov r4,r7 + 100111c: 308dc83a sub r6,r6,r2 + 1001120: d80f883a mov r7,sp + 1001124: 1000d680 call 1000d68 <_Z28read_encoded_value_with_basehjPKhPj> + 1001128: d8800017 ldw r2,0(sp) + 100112c: dfc00117 ldw ra,4(sp) + 1001130: dec00204 addi sp,sp,8 + 1001134: f800283a ret + 1001138: 2945883a add r2,r5,r5 + 100113c: 003ff406 br 1001110 <_Z15get_ttype_entryP16lsda_header_infoj+0x44> + 1001140: 280490fa slli r2,r5,3 + 1001144: 003ff206 br 1001110 <_Z15get_ttype_entryP16lsda_header_infoj+0x44> + 1001148: 0005883a mov r2,zero + 100114c: 003ff006 br 1001110 <_Z15get_ttype_entryP16lsda_header_infoj+0x44> + +01001150 <_Z20check_exception_specP16lsda_header_infoPKSt9type_infoPvi>: + 1001150: 20800317 ldw r2,12(r4) + 1001154: defffa04 addi sp,sp,-24 + 1001158: dc800415 stw r18,16(sp) + 100115c: 11c5c83a sub r2,r2,r7 + 1001160: dc400315 stw r17,12(sp) + 1001164: dc000215 stw r16,8(sp) + 1001168: dfc00515 stw ra,20(sp) + 100116c: 2023883a mov r17,r4 + 1001170: d9800115 stw r6,4(sp) + 1001174: 2825883a mov r18,r5 + 1001178: 143fffc4 addi r16,r2,-1 + 100117c: 8009883a mov r4,r16 + 1001180: d80b883a mov r5,sp + 1001184: 1000c480 call 1000c48 <_Z12read_uleb128PKhPj> + 1001188: 1021883a mov r16,r2 + 100118c: d8800017 ldw r2,0(sp) + 1001190: 8809883a mov r4,r17 + 1001194: 100b883a mov r5,r2 + 1001198: 10000826 beq r2,zero,10011bc <_Z20check_exception_specP16lsda_header_infoPKSt9type_infoPvi+0x6c> + 100119c: 10010cc0 call 10010cc <_Z15get_ttype_entryP16lsda_header_infoj> + 10011a0: 1009883a mov r4,r2 + 10011a4: 900b883a mov r5,r18 + 10011a8: d9800104 addi r6,sp,4 + 10011ac: 1000ccc0 call 1000ccc <_Z16get_adjusted_ptrPKSt9type_infoS1_PPv> + 10011b0: 10803fcc andi r2,r2,255 + 10011b4: 103ff126 beq r2,zero,100117c <_Z20check_exception_specP16lsda_header_infoPKSt9type_infoPvi+0x2c> + 10011b8: 00800044 movi r2,1 + 10011bc: dfc00517 ldw ra,20(sp) + 10011c0: dc800417 ldw r18,16(sp) + 10011c4: dc400317 ldw r17,12(sp) + 10011c8: dc000217 ldw r16,8(sp) + 10011cc: dec00604 addi sp,sp,24 + 10011d0: f800283a ret + +010011d4 <__cxa_call_unexpected>: + 10011d4: deffe204 addi sp,sp,-120 + 10011d8: 00804034 movhi r2,256 + 10011dc: 1084d504 addi r2,r2,4948 + 10011e0: 00c040b4 movhi r3,258 + 10011e4: 18e2da04 addi r3,r3,-29848 + 10011e8: d8800c15 stw r2,48(sp) + 10011ec: d9001815 stw r4,96(sp) + 10011f0: 00804034 movhi r2,256 + 10011f4: 10849704 addi r2,r2,4700 + 10011f8: d9000604 addi r4,sp,24 + 10011fc: d8c00d15 stw r3,52(sp) + 1001200: dfc01d15 stw ra,116(sp) + 1001204: d8800f15 stw r2,60(sp) + 1001208: df001c15 stw fp,112(sp) + 100120c: ddc01b15 stw r23,108(sp) + 1001210: dec00e15 stw sp,56(sp) + 1001214: dec01015 stw sp,64(sp) + 1001218: 10022540 call 1002254 <_Unwind_SjLj_Register> + 100121c: d9001817 ldw r4,96(sp) + 1001220: 1001a0c0 call 1001a0c <__cxa_begin_catch> + 1001224: d8801817 ldw r2,96(sp) + 1001228: 10fff504 addi r3,r2,-44 + 100122c: 18800917 ldw r2,36(r3) + 1001230: 19400617 ldw r5,24(r3) + 1001234: 19000217 ldw r4,8(r3) + 1001238: d8800215 stw r2,8(sp) + 100123c: 18800817 ldw r2,32(r3) + 1001240: 18c00317 ldw r3,12(r3) + 1001244: d9401615 stw r5,88(sp) + 1001248: d8801715 stw r2,92(sp) + 100124c: 00800084 movi r2,2 + 1001250: d8c01515 stw r3,84(sp) + 1001254: d8800715 stw r2,28(sp) + 1001258: 10019180 call 1001918 <_ZN10__cxxabiv112__unexpectedEPFvvE> + 100125c: d8800717 ldw r2,28(sp) + 1001260: d8c00817 ldw r3,32(sp) + 1001264: d8801a15 stw r2,104(sp) + 1001268: d9401a17 ldw r5,104(sp) + 100126c: 00800044 movi r2,1 + 1001270: d8c01915 stw r3,100(sp) + 1001274: 28800826 beq r5,r2,1001298 <__cxa_call_unexpected+0xc4> + 1001278: d8000715 stw zero,28(sp) + 100127c: 10019680 call 1001968 <__cxa_end_catch> + 1001280: d8000715 stw zero,28(sp) + 1001284: 10019680 call 1001968 <__cxa_end_catch> + 1001288: d9001917 ldw r4,100(sp) + 100128c: 00bfffc4 movi r2,-1 + 1001290: d8800715 stw r2,28(sp) + 1001294: 10025200 call 1002520 <_Unwind_SjLj_Resume> + 1001298: d9001917 ldw r4,100(sp) + 100129c: 1001a0c0 call 1001a0c <__cxa_begin_catch> + 10012a0: 10022440 call 1002244 <__cxa_get_globals_fast> + 10012a4: 10800017 ldw r2,0(r2) + 10012a8: d8c01a17 ldw r3,104(sp) + 10012ac: 0009883a mov r4,zero + 10012b0: 11401004 addi r5,r2,64 + 10012b4: d9401315 stw r5,76(sp) + 10012b8: d8801415 stw r2,80(sp) + 10012bc: d8c00715 stw r3,28(sp) + 10012c0: d9401717 ldw r5,92(sp) + 10012c4: d80d883a mov r6,sp + 10012c8: 1000fcc0 call 1000fcc <_Z17parse_lsda_headerP15_Unwind_ContextPKhP16lsda_header_info> + 10012cc: d8801417 ldw r2,80(sp) + 10012d0: d809883a mov r4,sp + 10012d4: d9801317 ldw r6,76(sp) + 10012d8: 11400017 ldw r5,0(r2) + 10012dc: d9c01617 ldw r7,88(sp) + 10012e0: 10011500 call 1001150 <_Z20check_exception_specP16lsda_header_infoPKSt9type_infoPvi> + 10012e4: 10803fcc andi r2,r2,255 + 10012e8: 1000151e bne r2,zero,1001340 <__cxa_call_unexpected+0x16c> + 10012ec: d8c01a17 ldw r3,104(sp) + 10012f0: d809883a mov r4,sp + 10012f4: 014040b4 movhi r5,258 + 10012f8: 29635704 addi r5,r5,-29348 + 10012fc: d8c00715 stw r3,28(sp) + 1001300: 000d883a mov r6,zero + 1001304: d9c01617 ldw r7,88(sp) + 1001308: 10011500 call 1001150 <_Z20check_exception_specP16lsda_header_infoPKSt9type_infoPvi> + 100130c: 10803fcc andi r2,r2,255 + 1001310: 10000c26 beq r2,zero,1001344 <__cxa_call_unexpected+0x170> + 1001314: 01000104 movi r4,4 + 1001318: 1001ed80 call 1001ed8 <__cxa_allocate_exception> + 100131c: 1009883a mov r4,r2 + 1001320: 008040b4 movhi r2,258 + 1001324: 10a34a04 addi r2,r2,-29400 + 1001328: 20800015 stw r2,0(r4) + 100132c: 014040b4 movhi r5,258 + 1001330: 29635704 addi r5,r5,-29348 + 1001334: 01804034 movhi r6,256 + 1001338: 31886004 addi r6,r6,8576 + 100133c: 1001ba40 call 1001ba4 <__cxa_throw> + 1001340: 1001b300 call 1001b30 <__cxa_rethrow> + 1001344: d9401a17 ldw r5,104(sp) + 1001348: d9001517 ldw r4,84(sp) + 100134c: d9400715 stw r5,28(sp) + 1001350: 100185c0 call 100185c <_ZN10__cxxabiv111__terminateEPFvvE> + +01001354 <__gxx_personality_sj0>: + 1001354: deffd304 addi sp,sp,-180 + 1001358: 00804034 movhi r2,256 + 100135c: 1085fc04 addi r2,r2,6128 + 1001360: 00c040b4 movhi r3,258 + 1001364: 18e2de04 addi r3,r3,-29832 + 1001368: d8801315 stw r2,76(sp) + 100136c: d9002315 stw r4,140(sp) + 1001370: 00804034 movhi r2,256 + 1001374: 1084d504 addi r2,r2,4948 + 1001378: d9000a04 addi r4,sp,40 + 100137c: d8801015 stw r2,64(sp) + 1001380: d8c01115 stw r3,68(sp) + 1001384: dfc02c15 stw ra,176(sp) + 1001388: df002b15 stw fp,172(sp) + 100138c: ddc02a15 stw r23,168(sp) + 1001390: dec01215 stw sp,72(sp) + 1001394: dec01415 stw sp,80(sp) + 1001398: d9802515 stw r6,148(sp) + 100139c: d9402415 stw r5,144(sp) + 10013a0: d9c02615 stw r7,152(sp) + 10013a4: 10022540 call 1002254 <_Unwind_SjLj_Register> + 10013a8: d8c02317 ldw r3,140(sp) + 10013ac: 00800044 movi r2,1 + 10013b0: 18800a26 beq r3,r2,10013dc <__gxx_personality_sj0+0x88> + 10013b4: 010000c4 movi r4,3 + 10013b8: d9002215 stw r4,136(sp) + 10013bc: d9000a04 addi r4,sp,40 + 10013c0: 10022640 call 1002264 <_Unwind_SjLj_Unregister> + 10013c4: d8802217 ldw r2,136(sp) + 10013c8: dfc02c17 ldw ra,176(sp) + 10013cc: df002b17 ldw fp,172(sp) + 10013d0: ddc02a17 ldw r23,168(sp) + 10013d4: dec02d04 addi sp,sp,180 + 10013d8: f800283a ret + 10013dc: d9402d17 ldw r5,180(sp) + 10013e0: d9002517 ldw r4,148(sp) + 10013e4: 0007883a mov r3,zero + 10013e8: 28800504 addi r2,r5,20 + 10013ec: d8800015 stw r2,0(sp) + 10013f0: 28bff504 addi r2,r5,-44 + 10013f4: d8801a15 stw r2,104(sp) + 10013f8: 0090caf4 movhi r2,17195 + 10013fc: 108ac004 addi r2,r2,11008 + 1001400: 2080ad26 beq r4,r2,10016b8 <__gxx_personality_sj0+0x364> + 1001404: d8c02105 stb r3,132(sp) + 1001408: d8c02417 ldw r3,144(sp) + 100140c: 00800184 movi r2,6 + 1001410: 1880281e bne r3,r2,10014b4 <__gxx_personality_sj0+0x160> + 1001414: d8802103 ldbu r2,132(sp) + 1001418: 10002626 beq r2,zero,10014b4 <__gxx_personality_sj0+0x160> + 100141c: d9001a17 ldw r4,104(sp) + 1001420: d9401a17 ldw r5,104(sp) + 1001424: d8801a17 ldw r2,104(sp) + 1001428: 21000917 ldw r4,36(r4) + 100142c: 29400617 ldw r5,24(r5) + 1001430: 10800817 ldw r2,32(r2) + 1001434: d9001d15 stw r4,116(sp) + 1001438: d9401b15 stw r5,108(sp) + 100143c: d8802015 stw r2,128(sp) + 1001440: 2000ad1e bne r4,zero,10016f8 <__gxx_personality_sj0+0x3a4> + 1001444: 01000044 movi r4,1 + 1001448: 00800044 movi r2,1 + 100144c: 2080e126 beq r4,r2,10017d4 <__gxx_personality_sj0+0x480> + 1001450: d8801b17 ldw r2,108(sp) + 1001454: 1000d316 blt r2,zero,10017a4 <__gxx_personality_sj0+0x450> + 1001458: d9802d17 ldw r6,180(sp) + 100145c: d9002e17 ldw r4,184(sp) + 1001460: 00bfffc4 movi r2,-1 + 1001464: 000b883a mov r5,zero + 1001468: d8800b15 stw r2,44(sp) + 100146c: 100229c0 call 100229c <_Unwind_SetGR> + 1001470: d9801b17 ldw r6,108(sp) + 1001474: d9002e17 ldw r4,184(sp) + 1001478: 01400044 movi r5,1 + 100147c: 100229c0 call 100229c <_Unwind_SetGR> + 1001480: d9002e17 ldw r4,184(sp) + 1001484: d9401d17 ldw r5,116(sp) + 1001488: 10022d80 call 10022d8 <_Unwind_SetIP> + 100148c: 010001c4 movi r4,7 + 1001490: d9002215 stw r4,136(sp) + 1001494: d9000a04 addi r4,sp,40 + 1001498: 10022640 call 1002264 <_Unwind_SjLj_Unregister> + 100149c: d8802217 ldw r2,136(sp) + 10014a0: dfc02c17 ldw ra,176(sp) + 10014a4: df002b17 ldw fp,172(sp) + 10014a8: ddc02a17 ldw r23,168(sp) + 10014ac: dec02d04 addi sp,sp,180 + 10014b0: f800283a ret + 10014b4: d9002e17 ldw r4,184(sp) + 10014b8: 00ffffc4 movi r3,-1 + 10014bc: d8c00b15 stw r3,44(sp) + 10014c0: 10022e80 call 10022e8 <_Unwind_GetLanguageSpecificData> + 10014c4: 10007226 beq r2,zero,1001690 <__gxx_personality_sj0+0x33c> + 10014c8: d9002e17 ldw r4,184(sp) + 10014cc: d9800404 addi r6,sp,16 + 10014d0: 100b883a mov r5,r2 + 10014d4: d8802015 stw r2,128(sp) + 10014d8: 1000fcc0 call 1000fcc <_Z17parse_lsda_headerP15_Unwind_ContextPKhP16lsda_header_info> + 10014dc: d9000903 ldbu r4,36(sp) + 10014e0: d9402e17 ldw r5,184(sp) + 10014e4: d8801e15 stw r2,120(sp) + 10014e8: 1000f3c0 call 1000f3c <_Z21base_of_encoded_valuehP15_Unwind_Context> + 10014ec: d9002e17 ldw r4,184(sp) + 10014f0: d8800615 stw r2,24(sp) + 10014f4: 10022b40 call 10022b4 <_Unwind_GetIP> + 10014f8: 10bfffc4 addi r2,r2,-1 + 10014fc: d8801c15 stw r2,112(sp) + 1001500: 10006316 blt r2,zero,1001690 <__gxx_personality_sj0+0x33c> + 1001504: 10001b1e bne r2,zero,1001574 <__gxx_personality_sj0+0x220> + 1001508: 01000044 movi r4,1 + 100150c: d8001f15 stw zero,124(sp) + 1001510: d8001d15 stw zero,116(sp) + 1001514: d8001b15 stw zero,108(sp) + 1001518: d9402417 ldw r5,144(sp) + 100151c: 00c00044 movi r3,1 + 1001520: 28c4703a and r2,r5,r3 + 1001524: 1005003a cmpeq r2,r2,zero + 1001528: 10006a1e bne r2,zero,10016d4 <__gxx_personality_sj0+0x380> + 100152c: 00800084 movi r2,2 + 1001530: 20805726 beq r4,r2,1001690 <__gxx_personality_sj0+0x33c> + 1001534: d8802103 ldbu r2,132(sp) + 1001538: 10008626 beq r2,zero,1001754 <__gxx_personality_sj0+0x400> + 100153c: d9001a17 ldw r4,104(sp) + 1001540: d9401d17 ldw r5,116(sp) + 1001544: d8801b17 ldw r2,108(sp) + 1001548: 00c00184 movi r3,6 + 100154c: d8c02215 stw r3,136(sp) + 1001550: 21400915 stw r5,36(r4) + 1001554: 20800615 stw r2,24(r4) + 1001558: d8c01f17 ldw r3,124(sp) + 100155c: d9402017 ldw r5,128(sp) + 1001560: d8800017 ldw r2,0(sp) + 1001564: 20c00715 stw r3,28(r4) + 1001568: 21400815 stw r5,32(r4) + 100156c: 20800a15 stw r2,40(r4) + 1001570: 003f9206 br 10013bc <__gxx_personality_sj0+0x68> + 1001574: d9001e17 ldw r4,120(sp) + 1001578: d9400204 addi r5,sp,8 + 100157c: 1000c480 call 1000c48 <_Z12read_uleb128PKhPj> + 1001580: d9401c17 ldw r5,112(sp) + 1001584: 1009883a mov r4,r2 + 1001588: 297fffc4 addi r5,r5,-1 + 100158c: d9401c15 stw r5,112(sp) + 1001590: d9400104 addi r5,sp,4 + 1001594: 1000c480 call 1000c48 <_Z12read_uleb128PKhPj> + 1001598: d8801e15 stw r2,120(sp) + 100159c: d8801c17 ldw r2,112(sp) + 10015a0: 103ff41e bne r2,zero,1001574 <__gxx_personality_sj0+0x220> + 10015a4: d8800217 ldw r2,8(sp) + 10015a8: d8c00117 ldw r3,4(sp) + 10015ac: 01000044 movi r4,1 + 10015b0: 1105883a add r2,r2,r4 + 10015b4: d8801d15 stw r2,116(sp) + 10015b8: 1800541e bne r3,zero,100170c <__gxx_personality_sj0+0x3b8> + 10015bc: d8001f15 stw zero,124(sp) + 10015c0: d8c01d17 ldw r3,116(sp) + 10015c4: 18003226 beq r3,zero,1001690 <__gxx_personality_sj0+0x33c> + 10015c8: d9001f17 ldw r4,124(sp) + 10015cc: 20007226 beq r4,zero,1001798 <__gxx_personality_sj0+0x444> + 10015d0: d9402417 ldw r5,144(sp) + 10015d4: 2880020c andi r2,r5,8 + 10015d8: 10006a1e bne r2,zero,1001784 <__gxx_personality_sj0+0x430> + 10015dc: d8802103 ldbu r2,132(sp) + 10015e0: 10006826 beq r2,zero,1001784 <__gxx_personality_sj0+0x430> + 10015e4: d8801a17 ldw r2,104(sp) + 10015e8: 10800017 ldw r2,0(r2) + 10015ec: d8801915 stw r2,100(sp) + 10015f0: d8c01917 ldw r3,100(sp) + 10015f4: d8001805 stb zero,96(sp) + 10015f8: 1807003a cmpeq r3,r3,zero + 10015fc: d8c02715 stw r3,156(sp) + 1001600: 00000706 br 1001620 <__gxx_personality_sj0+0x2cc> + 1001604: 01000044 movi r4,1 + 1001608: d9001805 stb r4,96(sp) + 100160c: d8800217 ldw r2,8(sp) + 1001610: 10005e26 beq r2,zero,100178c <__gxx_personality_sj0+0x438> + 1001614: d8c01717 ldw r3,92(sp) + 1001618: 1885883a add r2,r3,r2 + 100161c: d8801f15 stw r2,124(sp) + 1001620: d9001f17 ldw r4,124(sp) + 1001624: d9400104 addi r5,sp,4 + 1001628: 1000c780 call 1000c78 <_Z12read_sleb128PKhPi> + 100162c: 1009883a mov r4,r2 + 1001630: d9400204 addi r5,sp,8 + 1001634: d8801715 stw r2,92(sp) + 1001638: 1000c780 call 1000c78 <_Z12read_sleb128PKhPi> + 100163c: d8800117 ldw r2,4(sp) + 1001640: 103ff026 beq r2,zero,1001604 <__gxx_personality_sj0+0x2b0> + 1001644: 0080360e bge zero,r2,1001720 <__gxx_personality_sj0+0x3cc> + 1001648: 017fffc4 movi r5,-1 + 100164c: d9400b15 stw r5,44(sp) + 1001650: d9000404 addi r4,sp,16 + 1001654: 100b883a mov r5,r2 + 1001658: 10010cc0 call 10010cc <_Z15get_ttype_entryP16lsda_header_infoj> + 100165c: 10000826 beq r2,zero,1001680 <__gxx_personality_sj0+0x32c> + 1001660: d8c02717 ldw r3,156(sp) + 1001664: 183fe91e bne r3,zero,100160c <__gxx_personality_sj0+0x2b8> + 1001668: d9401917 ldw r5,100(sp) + 100166c: 1009883a mov r4,r2 + 1001670: d80d883a mov r6,sp + 1001674: 1000ccc0 call 1000ccc <_Z16get_adjusted_ptrPKSt9type_infoS1_PPv> + 1001678: 10803fcc andi r2,r2,255 + 100167c: 103fe326 beq r2,zero,100160c <__gxx_personality_sj0+0x2b8> + 1001680: d9000117 ldw r4,4(sp) + 1001684: d9001b15 stw r4,108(sp) + 1001688: 010000c4 movi r4,3 + 100168c: 003fa206 br 1001518 <__gxx_personality_sj0+0x1c4> + 1001690: 01400204 movi r5,8 + 1001694: d9000a04 addi r4,sp,40 + 1001698: d9402215 stw r5,136(sp) + 100169c: 10022640 call 1002264 <_Unwind_SjLj_Unregister> + 10016a0: d8802217 ldw r2,136(sp) + 10016a4: dfc02c17 ldw ra,176(sp) + 10016a8: df002b17 ldw fp,172(sp) + 10016ac: ddc02a17 ldw r23,168(sp) + 10016b0: dec02d04 addi sp,sp,180 + 10016b4: f800283a ret + 10016b8: d9402617 ldw r5,152(sp) + 10016bc: 0091d3b4 movhi r2,18254 + 10016c0: 109550c4 addi r2,r2,21827 + 10016c4: 28bf4f1e bne r5,r2,1001404 <__gxx_personality_sj0+0xb0> + 10016c8: d8802317 ldw r2,140(sp) + 10016cc: 1007883a mov r3,r2 + 10016d0: 003f4c06 br 1001404 <__gxx_personality_sj0+0xb0> + 10016d4: d9402417 ldw r5,144(sp) + 10016d8: 2880020c andi r2,r5,8 + 10016dc: 10000826 beq r2,zero,1001700 <__gxx_personality_sj0+0x3ac> + 10016e0: 20c04026 beq r4,r3,10017e4 <__gxx_personality_sj0+0x490> + 10016e4: d8801b17 ldw r2,108(sp) + 10016e8: 103f5b0e bge r2,zero,1001458 <__gxx_personality_sj0+0x104> + 10016ec: 00800084 movi r2,2 + 10016f0: d8800b15 stw r2,44(sp) + 10016f4: 10019280 call 1001928 <_ZSt10unexpectedv> + 10016f8: 010000c4 movi r4,3 + 10016fc: 003f5206 br 1001448 <__gxx_personality_sj0+0xf4> + 1001700: d8802103 ldbu r2,132(sp) + 1001704: 103f501e bne r2,zero,1001448 <__gxx_personality_sj0+0xf4> + 1001708: 003ff506 br 10016e0 <__gxx_personality_sj0+0x38c> + 100170c: d8800817 ldw r2,32(sp) + 1001710: 1885883a add r2,r3,r2 + 1001714: 1105c83a sub r2,r2,r4 + 1001718: d8801f15 stw r2,124(sp) + 100171c: 003fa806 br 10015c0 <__gxx_personality_sj0+0x26c> + 1001720: d9002717 ldw r4,156(sp) + 1001724: 20000e1e bne r4,zero,1001760 <__gxx_personality_sj0+0x40c> + 1001728: 017fffc4 movi r5,-1 + 100172c: d9400b15 stw r5,44(sp) + 1001730: d9800017 ldw r6,0(sp) + 1001734: d9401917 ldw r5,100(sp) + 1001738: 100f883a mov r7,r2 + 100173c: d9000404 addi r4,sp,16 + 1001740: 10011500 call 1001150 <_Z20check_exception_specP16lsda_header_infoPKSt9type_infoPvi> + 1001744: 1080005c xori r2,r2,1 + 1001748: 10803fcc andi r2,r2,255 + 100174c: 103faf26 beq r2,zero,100160c <__gxx_personality_sj0+0x2b8> + 1001750: 003fcb06 br 1001680 <__gxx_personality_sj0+0x32c> + 1001754: 00800184 movi r2,6 + 1001758: d8802215 stw r2,136(sp) + 100175c: 003f1706 br 10013bc <__gxx_personality_sj0+0x68> + 1001760: d9000717 ldw r4,28(sp) + 1001764: d9400304 addi r5,sp,12 + 1001768: 2089c83a sub r4,r4,r2 + 100176c: 213fffc4 addi r4,r4,-1 + 1001770: 1000c480 call 1000c48 <_Z12read_uleb128PKhPj> + 1001774: d8c00317 ldw r3,12(sp) + 1001778: 1807003a cmpeq r3,r3,zero + 100177c: 1805883a mov r2,r3 + 1001780: 003ff106 br 1001748 <__gxx_personality_sj0+0x3f4> + 1001784: d8001915 stw zero,100(sp) + 1001788: 003f9906 br 10015f0 <__gxx_personality_sj0+0x29c> + 100178c: d8801803 ldbu r2,96(sp) + 1001790: 1004c03a cmpne r2,r2,zero + 1001794: 103fbe26 beq r2,zero,1001690 <__gxx_personality_sj0+0x33c> + 1001798: 01000084 movi r4,2 + 100179c: d8001b15 stw zero,108(sp) + 10017a0: 003f5d06 br 1001518 <__gxx_personality_sj0+0x1c4> + 10017a4: d9402017 ldw r5,128(sp) + 10017a8: d9002e17 ldw r4,184(sp) + 10017ac: 00bfffc4 movi r2,-1 + 10017b0: d9800404 addi r6,sp,16 + 10017b4: d8800b15 stw r2,44(sp) + 10017b8: 1000fcc0 call 1000fcc <_Z17parse_lsda_headerP15_Unwind_ContextPKhP16lsda_header_info> + 10017bc: d9000903 ldbu r4,36(sp) + 10017c0: d9402e17 ldw r5,184(sp) + 10017c4: 1000f3c0 call 1000f3c <_Z21base_of_encoded_valuehP15_Unwind_Context> + 10017c8: d8c01a17 ldw r3,104(sp) + 10017cc: 18800915 stw r2,36(r3) + 10017d0: 003f2106 br 1001458 <__gxx_personality_sj0+0x104> + 10017d4: d9002d17 ldw r4,180(sp) + 10017d8: 00bfffc4 movi r2,-1 + 10017dc: d8800b15 stw r2,44(sp) + 10017e0: 10021a00 call 10021a0 <__cxa_call_terminate> + 10017e4: 00bfffc4 movi r2,-1 + 10017e8: d8800b15 stw r2,44(sp) + 10017ec: 10019000 call 1001900 <_ZSt9terminatev> + 10017f0: d9000b17 ldw r4,44(sp) + 10017f4: d9400c17 ldw r5,48(sp) + 10017f8: 00800044 movi r2,1 + 10017fc: d9002915 stw r4,164(sp) + 1001800: d9402815 stw r5,160(sp) + 1001804: 20800626 beq r4,r2,1001820 <__gxx_personality_sj0+0x4cc> + 1001808: d8000b15 stw zero,44(sp) + 100180c: 10019680 call 1001968 <__cxa_end_catch> + 1001810: d9002817 ldw r4,160(sp) + 1001814: 00bfffc4 movi r2,-1 + 1001818: d8800b15 stw r2,44(sp) + 100181c: 10025200 call 1002520 <_Unwind_SjLj_Resume> + 1001820: d9002817 ldw r4,160(sp) + 1001824: 1001a0c0 call 1001a0c <__cxa_begin_catch> + 1001828: d8c02917 ldw r3,164(sp) + 100182c: d8c00b15 stw r3,44(sp) + 1001830: 10019000 call 1001900 <_ZSt9terminatev> + +01001834 <_ZSt13set_terminatePFvvE>: + 1001834: 00c040b4 movhi r3,258 + 1001838: 18eb8f04 addi r3,r3,-20932 + 100183c: 18800017 ldw r2,0(r3) + 1001840: 19000015 stw r4,0(r3) + 1001844: f800283a ret + +01001848 <_ZSt14set_unexpectedPFvvE>: + 1001848: 00c040b4 movhi r3,258 + 100184c: 18eb9504 addi r3,r3,-20908 + 1001850: 18800017 ldw r2,0(r3) + 1001854: 19000015 stw r4,0(r3) + 1001858: f800283a ret + +0100185c <_ZN10__cxxabiv111__terminateEPFvvE>: + 100185c: deffed04 addi sp,sp,-76 + 1001860: 00804034 movhi r2,256 + 1001864: 1084d504 addi r2,r2,4948 + 1001868: d8800615 stw r2,24(sp) + 100186c: 00c040b4 movhi r3,258 + 1001870: 18e2e204 addi r3,r3,-29816 + 1001874: 00804034 movhi r2,256 + 1001878: 10862e04 addi r2,r2,6328 + 100187c: d9000d15 stw r4,52(sp) + 1001880: d809883a mov r4,sp + 1001884: d8800915 stw r2,36(sp) + 1001888: dfc01215 stw ra,72(sp) + 100188c: df001115 stw fp,68(sp) + 1001890: ddc01015 stw r23,64(sp) + 1001894: d8c00715 stw r3,28(sp) + 1001898: dec00815 stw sp,32(sp) + 100189c: dec00a15 stw sp,40(sp) + 10018a0: 10022540 call 1002254 <_Unwind_SjLj_Register> + 10018a4: 00800084 movi r2,2 + 10018a8: d8800115 stw r2,4(sp) + 10018ac: d8800d17 ldw r2,52(sp) + 10018b0: 103ee83a callr r2 + 10018b4: 100279c0 call 100279c + 10018b8: d8800117 ldw r2,4(sp) + 10018bc: d8c00217 ldw r3,8(sp) + 10018c0: d8800f15 stw r2,60(sp) + 10018c4: d8c00e15 stw r3,56(sp) + 10018c8: d8c00f17 ldw r3,60(sp) + 10018cc: 00800044 movi r2,1 + 10018d0: 18800626 beq r3,r2,10018ec <_ZN10__cxxabiv111__terminateEPFvvE+0x90> + 10018d4: d8000115 stw zero,4(sp) + 10018d8: 10019680 call 1001968 <__cxa_end_catch> + 10018dc: d9000e17 ldw r4,56(sp) + 10018e0: 00bfffc4 movi r2,-1 + 10018e4: d8800115 stw r2,4(sp) + 10018e8: 10025200 call 1002520 <_Unwind_SjLj_Resume> + 10018ec: d9000e17 ldw r4,56(sp) + 10018f0: 1001a0c0 call 1001a0c <__cxa_begin_catch> + 10018f4: d8c00f17 ldw r3,60(sp) + 10018f8: d8c00115 stw r3,4(sp) + 10018fc: 100279c0 call 100279c + +01001900 <_ZSt9terminatev>: + 1001900: 008040b4 movhi r2,258 + 1001904: 10ab8f04 addi r2,r2,-20932 + 1001908: 11000017 ldw r4,0(r2) + 100190c: deffff04 addi sp,sp,-4 + 1001910: dfc00015 stw ra,0(sp) + 1001914: 100185c0 call 100185c <_ZN10__cxxabiv111__terminateEPFvvE> + +01001918 <_ZN10__cxxabiv112__unexpectedEPFvvE>: + 1001918: deffff04 addi sp,sp,-4 + 100191c: dfc00015 stw ra,0(sp) + 1001920: 203ee83a callr r4 + 1001924: 10019000 call 1001900 <_ZSt9terminatev> + +01001928 <_ZSt10unexpectedv>: + 1001928: 008040b4 movhi r2,258 + 100192c: 10ab9504 addi r2,r2,-20908 + 1001930: 11000017 ldw r4,0(r2) + 1001934: deffff04 addi sp,sp,-4 + 1001938: dfc00015 stw ra,0(sp) + 100193c: 10019180 call 1001918 <_ZN10__cxxabiv112__unexpectedEPFvvE> + +01001940 <__cxa_get_exception_ptr>: + 1001940: 20bfff17 ldw r2,-4(r4) + 1001944: f800283a ret + +01001948 <_ZSt18uncaught_exceptionv>: + 1001948: deffff04 addi sp,sp,-4 + 100194c: dfc00015 stw ra,0(sp) + 1001950: 100224c0 call 100224c <__cxa_get_globals> + 1001954: 10800117 ldw r2,4(r2) + 1001958: 1004c03a cmpne r2,r2,zero + 100195c: dfc00017 ldw ra,0(sp) + 1001960: dec00104 addi sp,sp,4 + 1001964: f800283a ret + +01001968 <__cxa_end_catch>: + 1001968: deffff04 addi sp,sp,-4 + 100196c: dfc00015 stw ra,0(sp) + 1001970: 10022440 call 1002244 <__cxa_get_globals_fast> + 1001974: 11000017 ldw r4,0(r2) + 1001978: 1007883a mov r3,r2 + 100197c: 20001326 beq r4,zero,10019cc <__cxa_end_catch+0x64> + 1001980: 21400b17 ldw r5,44(r4) + 1001984: 0090caf4 movhi r2,17195 + 1001988: 108ac004 addi r2,r2,11008 + 100198c: 21800c17 ldw r6,48(r4) + 1001990: 28800526 beq r5,r2,10019a8 <__cxa_end_catch+0x40> + 1001994: 21000b04 addi r4,r4,44 + 1001998: 18000015 stw zero,0(r3) + 100199c: dfc00017 ldw ra,0(sp) + 10019a0: dec00104 addi sp,sp,4 + 10019a4: 10024141 jmpi 1002414 <_Unwind_DeleteException> + 10019a8: 0091d3b4 movhi r2,18254 + 10019ac: 109550c4 addi r2,r2,21827 + 10019b0: 30bff81e bne r6,r2,1001994 <__cxa_end_catch+0x2c> + 10019b4: 20800517 ldw r2,20(r4) + 10019b8: 10000e16 blt r2,zero,10019f4 <__cxa_end_catch+0x8c> + 10019bc: 117fffc4 addi r5,r2,-1 + 10019c0: 28000526 beq r5,zero,10019d8 <__cxa_end_catch+0x70> + 10019c4: 28000a16 blt r5,zero,10019f0 <__cxa_end_catch+0x88> + 10019c8: 21400515 stw r5,20(r4) + 10019cc: dfc00017 ldw ra,0(sp) + 10019d0: dec00104 addi sp,sp,4 + 10019d4: f800283a ret + 10019d8: 20800417 ldw r2,16(r4) + 10019dc: 21000b04 addi r4,r4,44 + 10019e0: 18800015 stw r2,0(r3) + 10019e4: dfc00017 ldw ra,0(sp) + 10019e8: dec00104 addi sp,sp,4 + 10019ec: 10024141 jmpi 1002414 <_Unwind_DeleteException> + 10019f0: 10019000 call 1001900 <_ZSt9terminatev> + 10019f4: 11400044 addi r5,r2,1 + 10019f8: 283ff31e bne r5,zero,10019c8 <__cxa_end_catch+0x60> + 10019fc: 20800417 ldw r2,16(r4) + 1001a00: 21400515 stw r5,20(r4) + 1001a04: 18800015 stw r2,0(r3) + 1001a08: 003ff006 br 10019cc <__cxa_end_catch+0x64> + +01001a0c <__cxa_begin_catch>: + 1001a0c: deffee04 addi sp,sp,-72 + 1001a10: 00804034 movhi r2,256 + 1001a14: 1084d504 addi r2,r2,4948 + 1001a18: 00c040b4 movhi r3,258 + 1001a1c: 18e2e604 addi r3,r3,-29800 + 1001a20: d8800615 stw r2,24(sp) + 1001a24: d9000e15 stw r4,56(sp) + 1001a28: 00804034 movhi r2,256 + 1001a2c: 1086c004 addi r2,r2,6912 + 1001a30: d809883a mov r4,sp + 1001a34: d8c00715 stw r3,28(sp) + 1001a38: dfc01115 stw ra,68(sp) + 1001a3c: d8800915 stw r2,36(sp) + 1001a40: df001015 stw fp,64(sp) + 1001a44: ddc00f15 stw r23,60(sp) + 1001a48: dec00815 stw sp,32(sp) + 1001a4c: dec00a15 stw sp,40(sp) + 1001a50: 10022540 call 1002254 <_Unwind_SjLj_Register> + 1001a54: 100224c0 call 100224c <__cxa_get_globals> + 1001a58: 100d883a mov r6,r2 + 1001a5c: d8800e17 ldw r2,56(sp) + 1001a60: 31c00017 ldw r7,0(r6) + 1001a64: 117ff504 addi r5,r2,-44 + 1001a68: 28c00b17 ldw r3,44(r5) + 1001a6c: 0090caf4 movhi r2,17195 + 1001a70: 108ac004 addi r2,r2,11008 + 1001a74: 29000c17 ldw r4,48(r5) + 1001a78: 18800b26 beq r3,r2,1001aa8 <__cxa_begin_catch+0x9c> + 1001a7c: 38001d1e bne r7,zero,1001af4 <__cxa_begin_catch+0xe8> + 1001a80: d8000d15 stw zero,52(sp) + 1001a84: 31400015 stw r5,0(r6) + 1001a88: d809883a mov r4,sp + 1001a8c: 10022640 call 1002264 <_Unwind_SjLj_Unregister> + 1001a90: d8800d17 ldw r2,52(sp) + 1001a94: dfc01117 ldw ra,68(sp) + 1001a98: df001017 ldw fp,64(sp) + 1001a9c: ddc00f17 ldw r23,60(sp) + 1001aa0: dec01204 addi sp,sp,72 + 1001aa4: f800283a ret + 1001aa8: 0091d3b4 movhi r2,18254 + 1001aac: 109550c4 addi r2,r2,21827 + 1001ab0: 20bff21e bne r4,r2,1001a7c <__cxa_begin_catch+0x70> + 1001ab4: 28c00517 ldw r3,20(r5) + 1001ab8: 18000b16 blt r3,zero,1001ae8 <__cxa_begin_catch+0xdc> + 1001abc: 18800044 addi r2,r3,1 + 1001ac0: 28800515 stw r2,20(r5) + 1001ac4: 30800117 ldw r2,4(r6) + 1001ac8: 10bfffc4 addi r2,r2,-1 + 1001acc: 30800115 stw r2,4(r6) + 1001ad0: 39400226 beq r7,r5,1001adc <__cxa_begin_catch+0xd0> + 1001ad4: 29c00415 stw r7,16(r5) + 1001ad8: 31400015 stw r5,0(r6) + 1001adc: 29400a17 ldw r5,40(r5) + 1001ae0: d9400d15 stw r5,52(sp) + 1001ae4: 003fe806 br 1001a88 <__cxa_begin_catch+0x7c> + 1001ae8: 00800044 movi r2,1 + 1001aec: 10c5c83a sub r2,r2,r3 + 1001af0: 003ff306 br 1001ac0 <__cxa_begin_catch+0xb4> + 1001af4: 00800044 movi r2,1 + 1001af8: d8800115 stw r2,4(sp) + 1001afc: 10019000 call 1001900 <_ZSt9terminatev> + 1001b00: d8800317 ldw r2,12(sp) + 1001b04: 00ffffc4 movi r3,-1 + 1001b08: d9000217 ldw r4,8(sp) + 1001b0c: 10c00226 beq r2,r3,1001b18 <__cxa_begin_catch+0x10c> + 1001b10: d8c00115 stw r3,4(sp) + 1001b14: 10025200 call 1002520 <_Unwind_SjLj_Resume> + 1001b18: 00bfffc4 movi r2,-1 + 1001b1c: d8800115 stw r2,4(sp) + 1001b20: 10011d40 call 10011d4 <__cxa_call_unexpected> + +01001b24 <_ZdlPv>: + 1001b24: 20000126 beq r4,zero,1001b2c <_ZdlPv+0x8> + 1001b28: 10027b41 jmpi 10027b4 + 1001b2c: f800283a ret + +01001b30 <__cxa_rethrow>: + 1001b30: defffe04 addi sp,sp,-8 + 1001b34: dc400015 stw r17,0(sp) + 1001b38: dfc00115 stw ra,4(sp) + 1001b3c: 100224c0 call 100224c <__cxa_get_globals> + 1001b40: 100b883a mov r5,r2 + 1001b44: 10800117 ldw r2,4(r2) + 1001b48: 2c400017 ldw r17,0(r5) + 1001b4c: 10800044 addi r2,r2,1 + 1001b50: 28800115 stw r2,4(r5) + 1001b54: 88000b26 beq r17,zero,1001b84 <__cxa_rethrow+0x54> + 1001b58: 88c00b17 ldw r3,44(r17) + 1001b5c: 0090caf4 movhi r2,17195 + 1001b60: 108ac004 addi r2,r2,11008 + 1001b64: 89000c17 ldw r4,48(r17) + 1001b68: 18800726 beq r3,r2,1001b88 <__cxa_rethrow+0x58> + 1001b6c: 28000015 stw zero,0(r5) + 1001b70: 8c400b04 addi r17,r17,44 + 1001b74: 8809883a mov r4,r17 + 1001b78: 10027440 call 1002744 <_Unwind_SjLj_Resume_or_Rethrow> + 1001b7c: 8809883a mov r4,r17 + 1001b80: 1001a0c0 call 1001a0c <__cxa_begin_catch> + 1001b84: 10019000 call 1001900 <_ZSt9terminatev> + 1001b88: 0091d3b4 movhi r2,18254 + 1001b8c: 109550c4 addi r2,r2,21827 + 1001b90: 20bff61e bne r4,r2,1001b6c <__cxa_rethrow+0x3c> + 1001b94: 88800517 ldw r2,20(r17) + 1001b98: 0085c83a sub r2,zero,r2 + 1001b9c: 88800515 stw r2,20(r17) + 1001ba0: 003ff306 br 1001b70 <__cxa_rethrow+0x40> + +01001ba4 <__cxa_throw>: + 1001ba4: 008040b4 movhi r2,258 + 1001ba8: 10ab9504 addi r2,r2,-20908 + 1001bac: 00c040b4 movhi r3,258 + 1001bb0: 18eb8f04 addi r3,r3,-20932 + 1001bb4: 12000017 ldw r8,0(r2) + 1001bb8: 19c00017 ldw r7,0(r3) + 1001bbc: defffe04 addi sp,sp,-8 + 1001bc0: 213ff004 addi r4,r4,-64 + 1001bc4: dfc00115 stw ra,4(sp) + 1001bc8: dc400015 stw r17,0(sp) + 1001bcc: 0090caf4 movhi r2,17195 + 1001bd0: 108ac004 addi r2,r2,11008 + 1001bd4: 20800b15 stw r2,44(r4) + 1001bd8: 00d1d3b4 movhi r3,18254 + 1001bdc: 18d550c4 addi r3,r3,21827 + 1001be0: 24400b04 addi r17,r4,44 + 1001be4: 00804034 movhi r2,256 + 1001be8: 10870604 addi r2,r2,7192 + 1001bec: 21400015 stw r5,0(r4) + 1001bf0: 21800115 stw r6,4(r4) + 1001bf4: 22000215 stw r8,8(r4) + 1001bf8: 21c00315 stw r7,12(r4) + 1001bfc: 20c00c15 stw r3,48(r4) + 1001c00: 20800d15 stw r2,52(r4) + 1001c04: 8809883a mov r4,r17 + 1001c08: 100257c0 call 100257c <_Unwind_SjLj_RaiseException> + 1001c0c: 8809883a mov r4,r17 + 1001c10: 1001a0c0 call 1001a0c <__cxa_begin_catch> + 1001c14: 10019000 call 1001900 <_ZSt9terminatev> + +01001c18 <_Z23__gxx_exception_cleanup19_Unwind_Reason_CodeP17_Unwind_Exception>: + 1001c18: defffe04 addi sp,sp,-8 + 1001c1c: 00800044 movi r2,1 + 1001c20: dfc00115 stw ra,4(sp) + 1001c24: dc000015 stw r16,0(sp) + 1001c28: 28fff504 addi r3,r5,-44 + 1001c2c: 11001036 bltu r2,r4,1001c70 <_Z23__gxx_exception_cleanup19_Unwind_Reason_CodeP17_Unwind_Exception+0x58> + 1001c30: 18800117 ldw r2,4(r3) + 1001c34: 10000826 beq r2,zero,1001c58 <_Z23__gxx_exception_cleanup19_Unwind_Reason_CodeP17_Unwind_Exception+0x40> + 1001c38: 2c000504 addi r16,r5,20 + 1001c3c: 8009883a mov r4,r16 + 1001c40: 103ee83a callr r2 + 1001c44: 8009883a mov r4,r16 + 1001c48: dfc00117 ldw ra,4(sp) + 1001c4c: dc000017 ldw r16,0(sp) + 1001c50: dec00204 addi sp,sp,8 + 1001c54: 1001e981 jmpi 1001e98 <__cxa_free_exception> + 1001c58: 2c000504 addi r16,r5,20 + 1001c5c: 8009883a mov r4,r16 + 1001c60: dfc00117 ldw ra,4(sp) + 1001c64: dc000017 ldw r16,0(sp) + 1001c68: dec00204 addi sp,sp,8 + 1001c6c: 1001e981 jmpi 1001e98 <__cxa_free_exception> + 1001c70: 19000317 ldw r4,12(r3) + 1001c74: 100185c0 call 100185c <_ZN10__cxxabiv111__terminateEPFvvE> + +01001c78 <_ZNK10__cxxabiv120__si_class_type_info11__do_upcastEPKNS_17__class_type_infoEPKvRNS1_15__upcast_resultE>: + 1001c78: defffb04 addi sp,sp,-20 + 1001c7c: dd400315 stw r21,12(sp) + 1001c80: dcc00215 stw r19,8(sp) + 1001c84: dc400115 stw r17,4(sp) + 1001c88: dc000015 stw r16,0(sp) + 1001c8c: 2823883a mov r17,r5 + 1001c90: 3027883a mov r19,r6 + 1001c94: 382b883a mov r21,r7 + 1001c98: dfc00415 stw ra,16(sp) + 1001c9c: 2021883a mov r16,r4 + 1001ca0: 1000bcc0 call 1000bcc <_ZNK10__cxxabiv117__class_type_info11__do_upcastEPKS0_PKvRNS0_15__upcast_resultE> + 1001ca4: 10803fcc andi r2,r2,255 + 1001ca8: 880b883a mov r5,r17 + 1001cac: 980d883a mov r6,r19 + 1001cb0: a80f883a mov r7,r21 + 1001cb4: 00c00044 movi r3,1 + 1001cb8: 1000051e bne r2,zero,1001cd0 <_ZNK10__cxxabiv120__si_class_type_info11__do_upcastEPKNS_17__class_type_infoEPKvRNS1_15__upcast_resultE+0x58> + 1001cbc: 81000217 ldw r4,8(r16) + 1001cc0: 20800017 ldw r2,0(r4) + 1001cc4: 10c00617 ldw r3,24(r2) + 1001cc8: 183ee83a callr r3 + 1001ccc: 10c03fcc andi r3,r2,255 + 1001cd0: 1805883a mov r2,r3 + 1001cd4: dfc00417 ldw ra,16(sp) + 1001cd8: dd400317 ldw r21,12(sp) + 1001cdc: dcc00217 ldw r19,8(sp) + 1001ce0: dc400117 ldw r17,4(sp) + 1001ce4: dc000017 ldw r16,0(sp) + 1001ce8: dec00504 addi sp,sp,20 + 1001cec: f800283a ret + +01001cf0 <_ZN10__cxxabiv120__si_class_type_infoD0Ev>: + 1001cf0: defffe04 addi sp,sp,-8 + 1001cf4: 008040b4 movhi r2,258 + 1001cf8: 10a32604 addi r2,r2,-29544 + 1001cfc: dc400015 stw r17,0(sp) + 1001d00: 20800015 stw r2,0(r4) + 1001d04: 2023883a mov r17,r4 + 1001d08: dfc00115 stw ra,4(sp) + 1001d0c: 1000b5c0 call 1000b5c <_ZN10__cxxabiv117__class_type_infoD2Ev> + 1001d10: 8809883a mov r4,r17 + 1001d14: dfc00117 ldw ra,4(sp) + 1001d18: dc400017 ldw r17,0(sp) + 1001d1c: dec00204 addi sp,sp,8 + 1001d20: 1001b241 jmpi 1001b24 <_ZdlPv> + +01001d24 <_ZN10__cxxabiv120__si_class_type_infoD1Ev>: + 1001d24: 008040b4 movhi r2,258 + 1001d28: 10a32604 addi r2,r2,-29544 + 1001d2c: 20800015 stw r2,0(r4) + 1001d30: 1000b5c1 jmpi 1000b5c <_ZN10__cxxabiv117__class_type_infoD2Ev> + +01001d34 <_ZN10__cxxabiv120__si_class_type_infoD2Ev>: + 1001d34: 008040b4 movhi r2,258 + 1001d38: 10a32604 addi r2,r2,-29544 + 1001d3c: 20800015 stw r2,0(r4) + 1001d40: 1000b5c1 jmpi 1000b5c <_ZN10__cxxabiv117__class_type_infoD2Ev> + +01001d44 <_ZNK10__cxxabiv120__si_class_type_info20__do_find_public_srcElPKvPKNS_17__class_type_infoES2_>: + 1001d44: da400017 ldw r9,0(sp) + 1001d48: 2011883a mov r8,r4 + 1001d4c: 49800526 beq r9,r6,1001d64 <_ZNK10__cxxabiv120__si_class_type_info20__do_find_public_srcElPKvPKNS_17__class_type_infoES2_+0x20> + 1001d50: 41000217 ldw r4,8(r8) + 1001d54: 20800017 ldw r2,0(r4) + 1001d58: da400015 stw r9,0(sp) + 1001d5c: 10c00817 ldw r3,32(r2) + 1001d60: 1800683a jmp r3 + 1001d64: 39000117 ldw r4,4(r7) + 1001d68: 40c00117 ldw r3,4(r8) + 1001d6c: 00800184 movi r2,6 + 1001d70: 193ff71e bne r3,r4,1001d50 <_ZNK10__cxxabiv120__si_class_type_info20__do_find_public_srcElPKvPKNS_17__class_type_infoES2_+0xc> + 1001d74: f800283a ret + +01001d78 <_ZNK10__cxxabiv120__si_class_type_info12__do_dyncastElNS_17__class_type_info10__sub_kindEPKS1_PKvS4_S6_RNS1_16__dyncast_resultE>: + 1001d78: 20c00117 ldw r3,4(r4) + 1001d7c: 38800117 ldw r2,4(r7) + 1001d80: defffb04 addi sp,sp,-20 + 1001d84: dfc00415 stw ra,16(sp) + 1001d88: da000517 ldw r8,20(sp) + 1001d8c: dac00617 ldw r11,24(sp) + 1001d90: da400717 ldw r9,28(sp) + 1001d94: da800817 ldw r10,32(sp) + 1001d98: 18800c1e bne r3,r2,1001dcc <_ZNK10__cxxabiv120__si_class_type_info12__do_dyncastElNS_17__class_type_info10__sub_kindEPKS1_PKvS4_S6_RNS1_16__dyncast_resultE+0x54> + 1001d9c: 51800115 stw r6,4(r10) + 1001da0: 52000015 stw r8,0(r10) + 1001da4: 28001c16 blt r5,zero,1001e18 <_ZNK10__cxxabiv120__si_class_type_info12__do_dyncastElNS_17__class_type_info10__sub_kindEPKS1_PKvS4_S6_RNS1_16__dyncast_resultE+0xa0> + 1001da8: 4145883a add r2,r8,r5 + 1001dac: 48801e26 beq r9,r2,1001e28 <_ZNK10__cxxabiv120__si_class_type_info12__do_dyncastElNS_17__class_type_info10__sub_kindEPKS1_PKvS4_S6_RNS1_16__dyncast_resultE+0xb0> + 1001db0: 00800044 movi r2,1 + 1001db4: 0007883a mov r3,zero + 1001db8: 50800315 stw r2,12(r10) + 1001dbc: 1805883a mov r2,r3 + 1001dc0: dfc00417 ldw ra,16(sp) + 1001dc4: dec00504 addi sp,sp,20 + 1001dc8: f800283a ret + 1001dcc: 42400d26 beq r8,r9,1001e04 <_ZNK10__cxxabiv120__si_class_type_info12__do_dyncastElNS_17__class_type_info10__sub_kindEPKS1_PKvS4_S6_RNS1_16__dyncast_resultE+0x8c> + 1001dd0: 21000217 ldw r4,8(r4) + 1001dd4: 20800017 ldw r2,0(r4) + 1001dd8: da000015 stw r8,0(sp) + 1001ddc: dac00115 stw r11,4(sp) + 1001de0: da400215 stw r9,8(sp) + 1001de4: da800315 stw r10,12(sp) + 1001de8: 10c00717 ldw r3,28(r2) + 1001dec: 183ee83a callr r3 + 1001df0: 10c03fcc andi r3,r2,255 + 1001df4: 1805883a mov r2,r3 + 1001df8: dfc00417 ldw ra,16(sp) + 1001dfc: dec00504 addi sp,sp,20 + 1001e00: f800283a ret + 1001e04: 58800117 ldw r2,4(r11) + 1001e08: 18bff11e bne r3,r2,1001dd0 <_ZNK10__cxxabiv120__si_class_type_info12__do_dyncastElNS_17__class_type_info10__sub_kindEPKS1_PKvS4_S6_RNS1_16__dyncast_resultE+0x58> + 1001e0c: 0007883a mov r3,zero + 1001e10: 51800215 stw r6,8(r10) + 1001e14: 003fe906 br 1001dbc <_ZNK10__cxxabiv120__si_class_type_info12__do_dyncastElNS_17__class_type_info10__sub_kindEPKS1_PKvS4_S6_RNS1_16__dyncast_resultE+0x44> + 1001e18: 00bfff84 movi r2,-2 + 1001e1c: 28800426 beq r5,r2,1001e30 <_ZNK10__cxxabiv120__si_class_type_info12__do_dyncastElNS_17__class_type_info10__sub_kindEPKS1_PKvS4_S6_RNS1_16__dyncast_resultE+0xb8> + 1001e20: 0007883a mov r3,zero + 1001e24: 003fe506 br 1001dbc <_ZNK10__cxxabiv120__si_class_type_info12__do_dyncastElNS_17__class_type_info10__sub_kindEPKS1_PKvS4_S6_RNS1_16__dyncast_resultE+0x44> + 1001e28: 00800184 movi r2,6 + 1001e2c: 003fe106 br 1001db4 <_ZNK10__cxxabiv120__si_class_type_info12__do_dyncastElNS_17__class_type_info10__sub_kindEPKS1_PKvS4_S6_RNS1_16__dyncast_resultE+0x3c> + 1001e30: 00800044 movi r2,1 + 1001e34: 0007883a mov r3,zero + 1001e38: 50800315 stw r2,12(r10) + 1001e3c: 003fdf06 br 1001dbc <_ZNK10__cxxabiv120__si_class_type_info12__do_dyncastElNS_17__class_type_info10__sub_kindEPKS1_PKvS4_S6_RNS1_16__dyncast_resultE+0x44> + +01001e40 <_ZNKSt9type_info14__is_pointer_pEv>: + 1001e40: 0005883a mov r2,zero + 1001e44: f800283a ret + +01001e48 <_ZNKSt9type_info15__is_function_pEv>: + 1001e48: 0005883a mov r2,zero + 1001e4c: f800283a ret + +01001e50 <_ZNKSt9type_info10__do_catchEPKS_PPvj>: + 1001e50: 20c00117 ldw r3,4(r4) + 1001e54: 28800117 ldw r2,4(r5) + 1001e58: 1885003a cmpeq r2,r3,r2 + 1001e5c: f800283a ret + +01001e60 <_ZNKSt9type_info11__do_upcastEPKN10__cxxabiv117__class_type_infoEPPv>: + 1001e60: 0005883a mov r2,zero + 1001e64: f800283a ret + +01001e68 <_ZNSt9type_infoD0Ev>: + 1001e68: 008040b4 movhi r2,258 + 1001e6c: 10a33e04 addi r2,r2,-29448 + 1001e70: 20800015 stw r2,0(r4) + 1001e74: 1001b241 jmpi 1001b24 <_ZdlPv> + +01001e78 <_ZNSt9type_infoD1Ev>: + 1001e78: 008040b4 movhi r2,258 + 1001e7c: 10a33e04 addi r2,r2,-29448 + 1001e80: 20800015 stw r2,0(r4) + 1001e84: f800283a ret + +01001e88 <_ZNSt9type_infoD2Ev>: + 1001e88: 008040b4 movhi r2,258 + 1001e8c: 10a33e04 addi r2,r2,-29448 + 1001e90: 20800015 stw r2,0(r4) + 1001e94: f800283a ret + +01001e98 <__cxa_free_exception>: + 1001e98: 2007883a mov r3,r4 + 1001e9c: 008040b4 movhi r2,258 + 1001ea0: 108b2b04 addi r2,r2,11436 + 1001ea4: 213ff004 addi r4,r4,-64 + 1001ea8: 11420004 addi r5,r2,2048 + 1001eac: 18800336 bltu r3,r2,1001ebc <__cxa_free_exception+0x24> + 1001eb0: 1885c83a sub r2,r3,r2 + 1001eb4: 1004d27a srli r2,r2,9 + 1001eb8: 19400136 bltu r3,r5,1001ec0 <__cxa_free_exception+0x28> + 1001ebc: 10027b41 jmpi 10027b4 + 1001ec0: 00ffff84 movi r3,-2 + 1001ec4: 1886183a rol r3,r3,r2 + 1001ec8: d0a76f17 ldw r2,-25156(gp) + 1001ecc: 10c4703a and r2,r2,r3 + 1001ed0: d0a76f15 stw r2,-25156(gp) + 1001ed4: f800283a ret + +01001ed8 <__cxa_allocate_exception>: + 1001ed8: deffed04 addi sp,sp,-76 + 1001edc: 00804034 movhi r2,256 + 1001ee0: 1084d504 addi r2,r2,4948 + 1001ee4: 21001004 addi r4,r4,64 + 1001ee8: 00c040b4 movhi r3,258 + 1001eec: 18e2ea04 addi r3,r3,-29784 + 1001ef0: d8800615 stw r2,24(sp) + 1001ef4: d9000d15 stw r4,52(sp) + 1001ef8: 00804034 movhi r2,256 + 1001efc: 1087fa04 addi r2,r2,8168 + 1001f00: d809883a mov r4,sp + 1001f04: dfc01215 stw ra,72(sp) + 1001f08: d8c00715 stw r3,28(sp) + 1001f0c: d8800915 stw r2,36(sp) + 1001f10: df001115 stw fp,68(sp) + 1001f14: ddc01015 stw r23,64(sp) + 1001f18: dec00815 stw sp,32(sp) + 1001f1c: dec00a15 stw sp,40(sp) + 1001f20: 10022540 call 1002254 <_Unwind_SjLj_Register> + 1001f24: d9000d17 ldw r4,52(sp) + 1001f28: 10027c80 call 10027c8 + 1001f2c: d8800e15 stw r2,56(sp) + 1001f30: 1000171e bne r2,zero,1001f90 <__cxa_allocate_exception+0xb8> + 1001f34: d8c00d17 ldw r3,52(sp) + 1001f38: 00808004 movi r2,512 + 1001f3c: d1e76f17 ldw r7,-25156(gp) + 1001f40: 10c02636 bltu r2,r3,1001fdc <__cxa_allocate_exception+0x104> + 1001f44: 3807883a mov r3,r7 + 1001f48: 01400044 movi r5,1 + 1001f4c: 1944703a and r2,r3,r5 + 1001f50: 0009883a mov r4,zero + 1001f54: 01800104 movi r6,4 + 1001f58: 10000526 beq r2,zero,1001f70 <__cxa_allocate_exception+0x98> + 1001f5c: 2149883a add r4,r4,r5 + 1001f60: 21801e26 beq r4,r6,1001fdc <__cxa_allocate_exception+0x104> + 1001f64: 1806d07a srli r3,r3,1 + 1001f68: 1944703a and r2,r3,r5 + 1001f6c: 103ffb1e bne r2,zero,1001f5c <__cxa_allocate_exception+0x84> + 1001f70: 2904983a sll r2,r5,r4 + 1001f74: 2008927a slli r4,r4,9 + 1001f78: 00c040b4 movhi r3,258 + 1001f7c: 18cb2b04 addi r3,r3,11436 + 1001f80: 3884b03a or r2,r7,r2 + 1001f84: 20c9883a add r4,r4,r3 + 1001f88: d9000e15 stw r4,56(sp) + 1001f8c: d0a76f15 stw r2,-25156(gp) + 1001f90: 100224c0 call 100224c <__cxa_get_globals> + 1001f94: 10c00117 ldw r3,4(r2) + 1001f98: d9000e17 ldw r4,56(sp) + 1001f9c: 000b883a mov r5,zero + 1001fa0: 18c00044 addi r3,r3,1 + 1001fa4: 10c00115 stw r3,4(r2) + 1001fa8: 01801004 movi r6,64 + 1001fac: 1002f1c0 call 1002f1c + 1001fb0: d8800e17 ldw r2,56(sp) + 1001fb4: d809883a mov r4,sp + 1001fb8: 10801004 addi r2,r2,64 + 1001fbc: d8800f15 stw r2,60(sp) + 1001fc0: 10022640 call 1002264 <_Unwind_SjLj_Unregister> + 1001fc4: d8800f17 ldw r2,60(sp) + 1001fc8: dfc01217 ldw ra,72(sp) + 1001fcc: df001117 ldw fp,68(sp) + 1001fd0: ddc01017 ldw r23,64(sp) + 1001fd4: dec01304 addi sp,sp,76 + 1001fd8: f800283a ret + 1001fdc: 00800044 movi r2,1 + 1001fe0: d8800115 stw r2,4(sp) + 1001fe4: 10019000 call 1001900 <_ZSt9terminatev> + 1001fe8: d8800317 ldw r2,12(sp) + 1001fec: 00ffffc4 movi r3,-1 + 1001ff0: d9000217 ldw r4,8(sp) + 1001ff4: 10c00226 beq r2,r3,1002000 <__cxa_allocate_exception+0x128> + 1001ff8: d8c00115 stw r3,4(sp) + 1001ffc: 10025200 call 1002520 <_Unwind_SjLj_Resume> + 1002000: 00bfffc4 movi r2,-1 + 1002004: d8800115 stw r2,4(sp) + 1002008: 10011d40 call 10011d4 <__cxa_call_unexpected> + +0100200c <_Znwm>: + 100200c: deffee04 addi sp,sp,-72 + 1002010: 00804034 movhi r2,256 + 1002014: 1084d504 addi r2,r2,4948 + 1002018: d8800615 stw r2,24(sp) + 100201c: 00c040b4 movhi r3,258 + 1002020: 18e2ee04 addi r3,r3,-29768 + 1002024: 00804034 movhi r2,256 + 1002028: 10883a04 addi r2,r2,8424 + 100202c: d9000e15 stw r4,56(sp) + 1002030: d809883a mov r4,sp + 1002034: d8800915 stw r2,36(sp) + 1002038: dfc01115 stw ra,68(sp) + 100203c: df001015 stw fp,64(sp) + 1002040: ddc00f15 stw r23,60(sp) + 1002044: d8c00715 stw r3,28(sp) + 1002048: dec00815 stw sp,32(sp) + 100204c: dec00a15 stw sp,40(sp) + 1002050: 10022540 call 1002254 <_Unwind_SjLj_Register> + 1002054: d8800e17 ldw r2,56(sp) + 1002058: 10000a1e bne r2,zero,1002084 <_Znwm+0x78> + 100205c: 00800044 movi r2,1 + 1002060: d8800e15 stw r2,56(sp) + 1002064: 00000706 br 1002084 <_Znwm+0x78> + 1002068: 008040b4 movhi r2,258 + 100206c: 10b2fd04 addi r2,r2,-13324 + 1002070: 10c00017 ldw r3,0(r2) + 1002074: 18000f26 beq r3,zero,10020b4 <_Znwm+0xa8> + 1002078: 00800044 movi r2,1 + 100207c: d8800115 stw r2,4(sp) + 1002080: 183ee83a callr r3 + 1002084: d9000e17 ldw r4,56(sp) + 1002088: 10027c80 call 10027c8 + 100208c: d8800d15 stw r2,52(sp) + 1002090: 103ff526 beq r2,zero,1002068 <_Znwm+0x5c> + 1002094: d809883a mov r4,sp + 1002098: 10022640 call 1002264 <_Unwind_SjLj_Unregister> + 100209c: d8800d17 ldw r2,52(sp) + 10020a0: dfc01117 ldw ra,68(sp) + 10020a4: df001017 ldw fp,64(sp) + 10020a8: ddc00f17 ldw r23,60(sp) + 10020ac: dec01204 addi sp,sp,72 + 10020b0: f800283a ret + 10020b4: 01000104 movi r4,4 + 10020b8: 1001ed80 call 1001ed8 <__cxa_allocate_exception> + 10020bc: 1009883a mov r4,r2 + 10020c0: 008040b4 movhi r2,258 + 10020c4: 10a36004 addi r2,r2,-29312 + 10020c8: 20800015 stw r2,0(r4) + 10020cc: 00c00044 movi r3,1 + 10020d0: d8c00115 stw r3,4(sp) + 10020d4: 014040b4 movhi r5,258 + 10020d8: 29636704 addi r5,r5,-29284 + 10020dc: 01804034 movhi r6,256 + 10020e0: 31888904 addi r6,r6,8740 + 10020e4: 1001ba40 call 1001ba4 <__cxa_throw> + 10020e8: d8800317 ldw r2,12(sp) + 10020ec: 00ffffc4 movi r3,-1 + 10020f0: d9000217 ldw r4,8(sp) + 10020f4: 10c00226 beq r2,r3,1002100 <_Znwm+0xf4> + 10020f8: d8c00115 stw r3,4(sp) + 10020fc: 10025200 call 1002520 <_Unwind_SjLj_Resume> + 1002100: 00bfffc4 movi r2,-1 + 1002104: d8800115 stw r2,4(sp) + 1002108: 10011d40 call 10011d4 <__cxa_call_unexpected> + +0100210c <_ZNKSt9exception4whatEv>: + 100210c: 20800017 ldw r2,0(r4) + 1002110: 10ffff17 ldw r3,-4(r2) + 1002114: 18800117 ldw r2,4(r3) + 1002118: f800283a ret + +0100211c <_ZNSt9exceptionD0Ev>: + 100211c: 008040b4 movhi r2,258 + 1002120: 10a34f04 addi r2,r2,-29380 + 1002124: 20800015 stw r2,0(r4) + 1002128: 1001b241 jmpi 1001b24 <_ZdlPv> + +0100212c <_ZNSt9exceptionD1Ev>: + 100212c: 008040b4 movhi r2,258 + 1002130: 10a34f04 addi r2,r2,-29380 + 1002134: 20800015 stw r2,0(r4) + 1002138: f800283a ret + +0100213c <_ZNSt9exceptionD2Ev>: + 100213c: 008040b4 movhi r2,258 + 1002140: 10a34f04 addi r2,r2,-29380 + 1002144: 20800015 stw r2,0(r4) + 1002148: f800283a ret + +0100214c <_ZNSt13bad_exceptionD0Ev>: + 100214c: defffe04 addi sp,sp,-8 + 1002150: 008040b4 movhi r2,258 + 1002154: 10a34a04 addi r2,r2,-29400 + 1002158: dc400015 stw r17,0(sp) + 100215c: 20800015 stw r2,0(r4) + 1002160: 2023883a mov r17,r4 + 1002164: dfc00115 stw ra,4(sp) + 1002168: 100213c0 call 100213c <_ZNSt9exceptionD2Ev> + 100216c: 8809883a mov r4,r17 + 1002170: dfc00117 ldw ra,4(sp) + 1002174: dc400017 ldw r17,0(sp) + 1002178: dec00204 addi sp,sp,8 + 100217c: 1001b241 jmpi 1001b24 <_ZdlPv> + +01002180 <_ZNSt13bad_exceptionD1Ev>: + 1002180: 008040b4 movhi r2,258 + 1002184: 10a34a04 addi r2,r2,-29400 + 1002188: 20800015 stw r2,0(r4) + 100218c: 100213c1 jmpi 100213c <_ZNSt9exceptionD2Ev> + +01002190 <_ZNSt13bad_exceptionD2Ev>: + 1002190: 008040b4 movhi r2,258 + 1002194: 10a34a04 addi r2,r2,-29400 + 1002198: 20800015 stw r2,0(r4) + 100219c: 100213c1 jmpi 100213c <_ZNSt9exceptionD2Ev> + +010021a0 <__cxa_call_terminate>: + 10021a0: defffe04 addi sp,sp,-8 + 10021a4: dc000015 stw r16,0(sp) + 10021a8: dfc00115 stw ra,4(sp) + 10021ac: 2021883a mov r16,r4 + 10021b0: 20000626 beq r4,zero,10021cc <__cxa_call_terminate+0x2c> + 10021b4: 1001a0c0 call 1001a0c <__cxa_begin_catch> + 10021b8: 80c00017 ldw r3,0(r16) + 10021bc: 0090caf4 movhi r2,17195 + 10021c0: 108ac004 addi r2,r2,11008 + 10021c4: 81000117 ldw r4,4(r16) + 10021c8: 18800126 beq r3,r2,10021d0 <__cxa_call_terminate+0x30> + 10021cc: 10019000 call 1001900 <_ZSt9terminatev> + 10021d0: 0091d3b4 movhi r2,18254 + 10021d4: 109550c4 addi r2,r2,21827 + 10021d8: 20bffc1e bne r4,r2,10021cc <__cxa_call_terminate+0x2c> + 10021dc: 813ff817 ldw r4,-32(r16) + 10021e0: 100185c0 call 100185c <_ZN10__cxxabiv111__terminateEPFvvE> + +010021e4 <_ZSt15set_new_handlerPFvvE>: + 10021e4: d0a77017 ldw r2,-25152(gp) + 10021e8: d1277015 stw r4,-25152(gp) + 10021ec: f800283a ret + +010021f0 <_ZNSt9bad_allocD0Ev>: + 10021f0: defffe04 addi sp,sp,-8 + 10021f4: 008040b4 movhi r2,258 + 10021f8: 10a36004 addi r2,r2,-29312 + 10021fc: dc400015 stw r17,0(sp) + 1002200: 20800015 stw r2,0(r4) + 1002204: 2023883a mov r17,r4 + 1002208: dfc00115 stw ra,4(sp) + 100220c: 100213c0 call 100213c <_ZNSt9exceptionD2Ev> + 1002210: 8809883a mov r4,r17 + 1002214: dfc00117 ldw ra,4(sp) + 1002218: dc400017 ldw r17,0(sp) + 100221c: dec00204 addi sp,sp,8 + 1002220: 1001b241 jmpi 1001b24 <_ZdlPv> + +01002224 <_ZNSt9bad_allocD1Ev>: + 1002224: 008040b4 movhi r2,258 + 1002228: 10a36004 addi r2,r2,-29312 + 100222c: 20800015 stw r2,0(r4) + 1002230: 100213c1 jmpi 100213c <_ZNSt9exceptionD2Ev> + +01002234 <_ZNSt9bad_allocD2Ev>: + 1002234: 008040b4 movhi r2,258 + 1002238: 10a36004 addi r2,r2,-29312 + 100223c: 20800015 stw r2,0(r4) + 1002240: 100213c1 jmpi 100213c <_ZNSt9exceptionD2Ev> + +01002244 <__cxa_get_globals_fast>: + 1002244: d0a77104 addi r2,gp,-25148 + 1002248: f800283a ret + +0100224c <__cxa_get_globals>: + 100224c: d0a77104 addi r2,gp,-25148 + 1002250: f800283a ret + +01002254 <_Unwind_SjLj_Register>: + 1002254: d0a77317 ldw r2,-25140(gp) + 1002258: 20800015 stw r2,0(r4) + 100225c: d1277315 stw r4,-25140(gp) + 1002260: f800283a ret + +01002264 <_Unwind_SjLj_Unregister>: + 1002264: 20800017 ldw r2,0(r4) + 1002268: d0a77315 stw r2,-25140(gp) + 100226c: f800283a ret + +01002270 <_Unwind_GetGR>: + 1002270: 20800017 ldw r2,0(r4) + 1002274: 294b883a add r5,r5,r5 + 1002278: 294b883a add r5,r5,r5 + 100227c: 288b883a add r5,r5,r2 + 1002280: 28800217 ldw r2,8(r5) + 1002284: f800283a ret + +01002288 <_Unwind_GetCFA>: + 1002288: 21000017 ldw r4,0(r4) + 100228c: 0005883a mov r2,zero + 1002290: 20000126 beq r4,zero,1002298 <_Unwind_GetCFA+0x10> + 1002294: 20800a17 ldw r2,40(r4) + 1002298: f800283a ret + +0100229c <_Unwind_SetGR>: + 100229c: 20800017 ldw r2,0(r4) + 10022a0: 294b883a add r5,r5,r5 + 10022a4: 294b883a add r5,r5,r5 + 10022a8: 288b883a add r5,r5,r2 + 10022ac: 29800215 stw r6,8(r5) + 10022b0: f800283a ret + +010022b4 <_Unwind_GetIP>: + 10022b4: 20c00017 ldw r3,0(r4) + 10022b8: 18800117 ldw r2,4(r3) + 10022bc: 10800044 addi r2,r2,1 + 10022c0: f800283a ret + +010022c4 <_Unwind_GetIPInfo>: + 10022c4: 20c00017 ldw r3,0(r4) + 10022c8: 28000015 stw zero,0(r5) + 10022cc: 18800117 ldw r2,4(r3) + 10022d0: 10800044 addi r2,r2,1 + 10022d4: f800283a ret + +010022d8 <_Unwind_SetIP>: + 10022d8: 20800017 ldw r2,0(r4) + 10022dc: 297fffc4 addi r5,r5,-1 + 10022e0: 11400115 stw r5,4(r2) + 10022e4: f800283a ret + +010022e8 <_Unwind_GetLanguageSpecificData>: + 10022e8: 20c00017 ldw r3,0(r4) + 10022ec: 18800717 ldw r2,28(r3) + 10022f0: f800283a ret + +010022f4 <_Unwind_GetRegionStart>: + 10022f4: 0005883a mov r2,zero + 10022f8: f800283a ret + +010022fc <_Unwind_FindEnclosingFunction>: + 10022fc: 0005883a mov r2,zero + 1002300: f800283a ret + +01002304 <_Unwind_GetDataRelBase>: + 1002304: 0005883a mov r2,zero + 1002308: f800283a ret + +0100230c <_Unwind_GetTextRelBase>: + 100230c: 0005883a mov r2,zero + 1002310: f800283a ret + +01002314 <_Unwind_ForcedUnwind_Phase2>: + 1002314: defff604 addi sp,sp,-40 + 1002318: dd400815 stw r21,32(sp) + 100231c: dd000715 stw r20,28(sp) + 1002320: 25400317 ldw r21,12(r4) + 1002324: 25000417 ldw r20,16(r4) + 1002328: 28800017 ldw r2,0(r5) + 100232c: dc800515 stw r18,20(sp) + 1002330: dc000315 stw r16,12(sp) + 1002334: 2825883a mov r18,r5 + 1002338: 2021883a mov r16,r4 + 100233c: dfc00915 stw ra,36(sp) + 1002340: dcc00615 stw r19,24(sp) + 1002344: dc400415 stw r17,16(sp) + 1002348: 00001406 br 100239c <_Unwind_ForcedUnwind_Phase2+0x88> + 100234c: 00800144 movi r2,5 + 1002350: 88802626 beq r17,r2,10023ec <_Unwind_ForcedUnwind_Phase2+0xd8> + 1002354: 98000c26 beq r19,zero,1002388 <_Unwind_ForcedUnwind_Phase2+0x74> + 1002358: 82000017 ldw r8,0(r16) + 100235c: dc000015 stw r16,0(sp) + 1002360: dc800115 stw r18,4(sp) + 1002364: 82400117 ldw r9,4(r16) + 1002368: 400d883a mov r6,r8 + 100236c: 480f883a mov r7,r9 + 1002370: 983ee83a callr r19 + 1002374: 1023883a mov r17,r2 + 1002378: 008001c4 movi r2,7 + 100237c: 88801b26 beq r17,r2,10023ec <_Unwind_ForcedUnwind_Phase2+0xd8> + 1002380: 00800204 movi r2,8 + 1002384: 8880181e bne r17,r2,10023e8 <_Unwind_ForcedUnwind_Phase2+0xd4> + 1002388: 91000017 ldw r4,0(r18) + 100238c: 10022640 call 1002264 <_Unwind_SjLj_Unregister> + 1002390: 90800017 ldw r2,0(r18) + 1002394: 10800017 ldw r2,0(r2) + 1002398: 90800015 stw r2,0(r18) + 100239c: 01400684 movi r5,26 + 10023a0: 04400144 movi r17,5 + 10023a4: 0027883a mov r19,zero + 10023a8: 10000326 beq r2,zero,10023b8 <_Unwind_ForcedUnwind_Phase2+0xa4> + 10023ac: 14c00617 ldw r19,24(r2) + 10023b0: 0023883a mov r17,zero + 10023b4: 01400284 movi r5,10 + 10023b8: dc000015 stw r16,0(sp) + 10023bc: dc800115 stw r18,4(sp) + 10023c0: 80800017 ldw r2,0(r16) + 10023c4: dd000215 stw r20,8(sp) + 10023c8: 80c00117 ldw r3,4(r16) + 10023cc: 01000044 movi r4,1 + 10023d0: 100d883a mov r6,r2 + 10023d4: 180f883a mov r7,r3 + 10023d8: a83ee83a callr r21 + 10023dc: 01400284 movi r5,10 + 10023e0: 01000044 movi r4,1 + 10023e4: 103fd926 beq r2,zero,100234c <_Unwind_ForcedUnwind_Phase2+0x38> + 10023e8: 04400084 movi r17,2 + 10023ec: 8805883a mov r2,r17 + 10023f0: dfc00917 ldw ra,36(sp) + 10023f4: dd400817 ldw r21,32(sp) + 10023f8: dd000717 ldw r20,28(sp) + 10023fc: dcc00617 ldw r19,24(sp) + 1002400: dc800517 ldw r18,20(sp) + 1002404: dc400417 ldw r17,16(sp) + 1002408: dc000317 ldw r16,12(sp) + 100240c: dec00a04 addi sp,sp,40 + 1002410: f800283a ret + +01002414 <_Unwind_DeleteException>: + 1002414: 20800217 ldw r2,8(r4) + 1002418: 200b883a mov r5,r4 + 100241c: 01000044 movi r4,1 + 1002420: 10000126 beq r2,zero,1002428 <_Unwind_DeleteException+0x14> + 1002424: 1000683a jmp r2 + 1002428: f800283a ret + +0100242c <_Unwind_RaiseException_Phase2>: + 100242c: defffa04 addi sp,sp,-24 + 1002430: dc800415 stw r18,16(sp) + 1002434: 2825883a mov r18,r5 + 1002438: 29400017 ldw r5,0(r5) + 100243c: dc400315 stw r17,12(sp) + 1002440: dfc00515 stw ra,20(sp) + 1002444: dc000215 stw r16,8(sp) + 1002448: 2023883a mov r17,r4 + 100244c: 28001b26 beq r5,zero,10024bc <_Unwind_RaiseException_Phase2+0x90> + 1002450: 88800417 ldw r2,16(r17) + 1002454: 0007883a mov r3,zero + 1002458: 2a000617 ldw r8,24(r5) + 100245c: 28a1003a cmpeq r16,r5,r2 + 1002460: 802090ba slli r16,r16,2 + 1002464: 18001b1e bne r3,zero,10024d4 <_Unwind_RaiseException_Phase2+0xa8> + 1002468: 40000e26 beq r8,zero,10024a4 <_Unwind_RaiseException_Phase2+0x78> + 100246c: 88800017 ldw r2,0(r17) + 1002470: dc400015 stw r17,0(sp) + 1002474: dc800115 stw r18,4(sp) + 1002478: 88c00117 ldw r3,4(r17) + 100247c: 01000044 movi r4,1 + 1002480: 81400094 ori r5,r16,2 + 1002484: 180f883a mov r7,r3 + 1002488: 100d883a mov r6,r2 + 100248c: 403ee83a callr r8 + 1002490: 1007883a mov r3,r2 + 1002494: 008001c4 movi r2,7 + 1002498: 18800f26 beq r3,r2,10024d8 <_Unwind_RaiseException_Phase2+0xac> + 100249c: 00800204 movi r2,8 + 10024a0: 18800c1e bne r3,r2,10024d4 <_Unwind_RaiseException_Phase2+0xa8> + 10024a4: 8000131e bne r16,zero,10024f4 <_Unwind_RaiseException_Phase2+0xc8> + 10024a8: 91400017 ldw r5,0(r18) + 10024ac: 28800017 ldw r2,0(r5) + 10024b0: 100b883a mov r5,r2 + 10024b4: 90800015 stw r2,0(r18) + 10024b8: 283fe51e bne r5,zero,1002450 <_Unwind_RaiseException_Phase2+0x24> + 10024bc: 88800417 ldw r2,16(r17) + 10024c0: 00c00144 movi r3,5 + 10024c4: 0011883a mov r8,zero + 10024c8: 28a1003a cmpeq r16,r5,r2 + 10024cc: 802090ba slli r16,r16,2 + 10024d0: 183fe526 beq r3,zero,1002468 <_Unwind_RaiseException_Phase2+0x3c> + 10024d4: 00c00084 movi r3,2 + 10024d8: 1805883a mov r2,r3 + 10024dc: dfc00517 ldw ra,20(sp) + 10024e0: dc800417 ldw r18,16(sp) + 10024e4: dc400317 ldw r17,12(sp) + 10024e8: dc000217 ldw r16,8(sp) + 10024ec: dec00604 addi sp,sp,24 + 10024f0: f800283a ret + 10024f4: 100279c0 call 100279c + +010024f8 : + 10024f8: 28800017 ldw r2,0(r5) + 10024fc: deffff04 addi sp,sp,-4 + 1002500: df000015 stw fp,0(sp) + 1002504: 10c00804 addi r3,r2,32 + 1002508: d839883a mov fp,sp + 100250c: d0a77315 stw r2,-25140(gp) + 1002510: 19000117 ldw r4,4(r3) + 1002514: 1f000017 ldw fp,0(r3) + 1002518: 1ec00217 ldw sp,8(r3) + 100251c: 2000683a jmp r4 + +01002520 <_Unwind_SjLj_Resume>: + 1002520: d0e77317 ldw r3,-25140(gp) + 1002524: 20800317 ldw r2,12(r4) + 1002528: defffc04 addi sp,sp,-16 + 100252c: dfc00315 stw ra,12(sp) + 1002530: dc000215 stw r16,8(sp) + 1002534: d8c00015 stw r3,0(sp) + 1002538: d8c00115 stw r3,4(sp) + 100253c: 1000071e bne r2,zero,100255c <_Unwind_SjLj_Resume+0x3c> + 1002540: dc000104 addi r16,sp,4 + 1002544: 800b883a mov r5,r16 + 1002548: 100242c0 call 100242c <_Unwind_RaiseException_Phase2> + 100254c: 1007883a mov r3,r2 + 1002550: 008001c4 movi r2,7 + 1002554: 18800626 beq r3,r2,1002570 <_Unwind_SjLj_Resume+0x50> + 1002558: 100279c0 call 100279c + 100255c: dc000104 addi r16,sp,4 + 1002560: 800b883a mov r5,r16 + 1002564: 10023140 call 1002314 <_Unwind_ForcedUnwind_Phase2> + 1002568: 1007883a mov r3,r2 + 100256c: 003ff806 br 1002550 <_Unwind_SjLj_Resume+0x30> + 1002570: 800b883a mov r5,r16 + 1002574: d809883a mov r4,sp + 1002578: 10024f80 call 10024f8 + +0100257c <_Unwind_SjLj_RaiseException>: + 100257c: d0a77317 ldw r2,-25140(gp) + 1002580: defff804 addi sp,sp,-32 + 1002584: dc000415 stw r16,16(sp) + 1002588: dfc00715 stw ra,28(sp) + 100258c: dc800615 stw r18,24(sp) + 1002590: dc400515 stw r17,20(sp) + 1002594: 2021883a mov r16,r4 + 1002598: d8800215 stw r2,8(sp) + 100259c: d8800315 stw r2,12(sp) + 10025a0: 10001626 beq r2,zero,10025fc <_Unwind_SjLj_RaiseException+0x80> + 10025a4: dc400304 addi r17,sp,12 + 10025a8: 04800184 movi r18,6 + 10025ac: 00000106 br 10025b4 <_Unwind_SjLj_RaiseException+0x38> + 10025b0: d8800315 stw r2,12(sp) + 10025b4: 12000617 ldw r8,24(r2) + 10025b8: 40000d26 beq r8,zero,10025f0 <_Unwind_SjLj_RaiseException+0x74> + 10025bc: 80800017 ldw r2,0(r16) + 10025c0: dc000015 stw r16,0(sp) + 10025c4: 80c00117 ldw r3,4(r16) + 10025c8: 01000044 movi r4,1 + 10025cc: dc400115 stw r17,4(sp) + 10025d0: 180f883a mov r7,r3 + 10025d4: 200b883a mov r5,r4 + 10025d8: 100d883a mov r6,r2 + 10025dc: 403ee83a callr r8 + 10025e0: 1007883a mov r3,r2 + 10025e4: 14800d26 beq r2,r18,100261c <_Unwind_SjLj_RaiseException+0xa0> + 10025e8: 00800204 movi r2,8 + 10025ec: 1880191e bne r3,r2,1002654 <_Unwind_SjLj_RaiseException+0xd8> + 10025f0: d8800317 ldw r2,12(sp) + 10025f4: 10800017 ldw r2,0(r2) + 10025f8: 103fed1e bne r2,zero,10025b0 <_Unwind_SjLj_RaiseException+0x34> + 10025fc: 00c00144 movi r3,5 + 1002600: 1805883a mov r2,r3 + 1002604: dfc00717 ldw ra,28(sp) + 1002608: dc800617 ldw r18,24(sp) + 100260c: dc400517 ldw r17,20(sp) + 1002610: dc000417 ldw r16,16(sp) + 1002614: dec00804 addi sp,sp,32 + 1002618: f800283a ret + 100261c: d8800317 ldw r2,12(sp) + 1002620: 80000315 stw zero,12(r16) + 1002624: 8009883a mov r4,r16 + 1002628: 80800415 stw r2,16(r16) + 100262c: d8800217 ldw r2,8(sp) + 1002630: 880b883a mov r5,r17 + 1002634: d8800315 stw r2,12(sp) + 1002638: 100242c0 call 100242c <_Unwind_RaiseException_Phase2> + 100263c: 1007883a mov r3,r2 + 1002640: 008001c4 movi r2,7 + 1002644: 18bfee1e bne r3,r2,1002600 <_Unwind_SjLj_RaiseException+0x84> + 1002648: 880b883a mov r5,r17 + 100264c: d9000204 addi r4,sp,8 + 1002650: 10024f80 call 10024f8 + 1002654: 00c000c4 movi r3,3 + 1002658: 1805883a mov r2,r3 + 100265c: dfc00717 ldw ra,28(sp) + 1002660: dc800617 ldw r18,24(sp) + 1002664: dc400517 ldw r17,20(sp) + 1002668: dc000417 ldw r16,16(sp) + 100266c: dec00804 addi sp,sp,32 + 1002670: f800283a ret + +01002674 <_Unwind_SjLj_ForcedUnwind>: + 1002674: defffc04 addi sp,sp,-16 + 1002678: d0a77317 ldw r2,-25140(gp) + 100267c: dc000215 stw r16,8(sp) + 1002680: dc000104 addi r16,sp,4 + 1002684: 21400315 stw r5,12(r4) + 1002688: 21800415 stw r6,16(r4) + 100268c: 800b883a mov r5,r16 + 1002690: dfc00315 stw ra,12(sp) + 1002694: d8800015 stw r2,0(sp) + 1002698: d8800115 stw r2,4(sp) + 100269c: 10023140 call 1002314 <_Unwind_ForcedUnwind_Phase2> + 10026a0: 00c001c4 movi r3,7 + 10026a4: 10c00426 beq r2,r3,10026b8 <_Unwind_SjLj_ForcedUnwind+0x44> + 10026a8: dfc00317 ldw ra,12(sp) + 10026ac: dc000217 ldw r16,8(sp) + 10026b0: dec00404 addi sp,sp,16 + 10026b4: f800283a ret + 10026b8: 800b883a mov r5,r16 + 10026bc: d809883a mov r4,sp + 10026c0: 10024f80 call 10024f8 + +010026c4 <_Unwind_Backtrace>: + 10026c4: d0a77317 ldw r2,-25140(gp) + 10026c8: defffa04 addi sp,sp,-24 + 10026cc: dcc00415 stw r19,16(sp) + 10026d0: dc800315 stw r18,12(sp) + 10026d4: dc400215 stw r17,8(sp) + 10026d8: 2025883a mov r18,r4 + 10026dc: 2823883a mov r17,r5 + 10026e0: 04c00144 movi r19,5 + 10026e4: dfc00515 stw ra,20(sp) + 10026e8: dc000115 stw r16,4(sp) + 10026ec: d8800015 stw r2,0(sp) + 10026f0: 00000406 br 1002704 <_Unwind_Backtrace+0x40> + 10026f4: 84c00b26 beq r16,r19,1002724 <_Unwind_Backtrace+0x60> + 10026f8: d8800017 ldw r2,0(sp) + 10026fc: 10800017 ldw r2,0(r2) + 1002700: d8800015 stw r2,0(sp) + 1002704: 04000144 movi r16,5 + 1002708: 10000126 beq r2,zero,1002710 <_Unwind_Backtrace+0x4c> + 100270c: 0021883a mov r16,zero + 1002710: d809883a mov r4,sp + 1002714: 880b883a mov r5,r17 + 1002718: 903ee83a callr r18 + 100271c: 103ff526 beq r2,zero,10026f4 <_Unwind_Backtrace+0x30> + 1002720: 040000c4 movi r16,3 + 1002724: 8005883a mov r2,r16 + 1002728: dfc00517 ldw ra,20(sp) + 100272c: dcc00417 ldw r19,16(sp) + 1002730: dc800317 ldw r18,12(sp) + 1002734: dc400217 ldw r17,8(sp) + 1002738: dc000117 ldw r16,4(sp) + 100273c: dec00604 addi sp,sp,24 + 1002740: f800283a ret + +01002744 <_Unwind_SjLj_Resume_or_Rethrow>: + 1002744: 20800317 ldw r2,12(r4) + 1002748: defffc04 addi sp,sp,-16 + 100274c: dfc00315 stw ra,12(sp) + 1002750: dc000215 stw r16,8(sp) + 1002754: 10000926 beq r2,zero,100277c <_Unwind_SjLj_Resume_or_Rethrow+0x38> + 1002758: d0a77317 ldw r2,-25140(gp) + 100275c: dc000104 addi r16,sp,4 + 1002760: 800b883a mov r5,r16 + 1002764: d8800015 stw r2,0(sp) + 1002768: d8800115 stw r2,4(sp) + 100276c: 10023140 call 1002314 <_Unwind_ForcedUnwind_Phase2> + 1002770: 00c001c4 movi r3,7 + 1002774: 10c00626 beq r2,r3,1002790 <_Unwind_SjLj_Resume_or_Rethrow+0x4c> + 1002778: 100279c0 call 100279c + 100277c: 100257c0 call 100257c <_Unwind_SjLj_RaiseException> + 1002780: dfc00317 ldw ra,12(sp) + 1002784: dc000217 ldw r16,8(sp) + 1002788: dec00404 addi sp,sp,16 + 100278c: f800283a ret + 1002790: 800b883a mov r5,r16 + 1002794: d809883a mov r4,sp + 1002798: 10024f80 call 10024f8 + +0100279c : + 100279c: deffff04 addi sp,sp,-4 + 10027a0: 01000184 movi r4,6 + 10027a4: dfc00015 stw ra,0(sp) + 10027a8: 100321c0 call 100321c + 10027ac: 01000044 movi r4,1 + 10027b0: 100c4380 call 100c438 <_exit> + +010027b4 : + 10027b4: 008040b4 movhi r2,258 + 10027b8: 10ab9804 addi r2,r2,-20896 + 10027bc: 200b883a mov r5,r4 + 10027c0: 11000017 ldw r4,0(r2) + 10027c4: 10073601 jmpi 1007360 <_free_r> + +010027c8 : + 10027c8: 008040b4 movhi r2,258 + 10027cc: 10ab9804 addi r2,r2,-20896 + 10027d0: 200b883a mov r5,r4 + 10027d4: 11000017 ldw r4,0(r2) + 10027d8: 10027dc1 jmpi 10027dc <_malloc_r> + +010027dc <_malloc_r>: + 10027dc: defff604 addi sp,sp,-40 + 10027e0: 28c002c4 addi r3,r5,11 + 10027e4: 00800584 movi r2,22 + 10027e8: dc800215 stw r18,8(sp) + 10027ec: dfc00915 stw ra,36(sp) + 10027f0: df000815 stw fp,32(sp) + 10027f4: ddc00715 stw r23,28(sp) + 10027f8: dd800615 stw r22,24(sp) + 10027fc: dd400515 stw r21,20(sp) + 1002800: dd000415 stw r20,16(sp) + 1002804: dcc00315 stw r19,12(sp) + 1002808: dc400115 stw r17,4(sp) + 100280c: dc000015 stw r16,0(sp) + 1002810: 2025883a mov r18,r4 + 1002814: 10c01236 bltu r2,r3,1002860 <_malloc_r+0x84> + 1002818: 04400404 movi r17,16 + 100281c: 8940142e bgeu r17,r5,1002870 <_malloc_r+0x94> + 1002820: 00800304 movi r2,12 + 1002824: 0007883a mov r3,zero + 1002828: 90800015 stw r2,0(r18) + 100282c: 1805883a mov r2,r3 + 1002830: dfc00917 ldw ra,36(sp) + 1002834: df000817 ldw fp,32(sp) + 1002838: ddc00717 ldw r23,28(sp) + 100283c: dd800617 ldw r22,24(sp) + 1002840: dd400517 ldw r21,20(sp) + 1002844: dd000417 ldw r20,16(sp) + 1002848: dcc00317 ldw r19,12(sp) + 100284c: dc800217 ldw r18,8(sp) + 1002850: dc400117 ldw r17,4(sp) + 1002854: dc000017 ldw r16,0(sp) + 1002858: dec00a04 addi sp,sp,40 + 100285c: f800283a ret + 1002860: 00bffe04 movi r2,-8 + 1002864: 18a2703a and r17,r3,r2 + 1002868: 883fed16 blt r17,zero,1002820 <_malloc_r+0x44> + 100286c: 897fec36 bltu r17,r5,1002820 <_malloc_r+0x44> + 1002870: 9009883a mov r4,r18 + 1002874: 100d0a00 call 100d0a0 <__malloc_lock> + 1002878: 00807dc4 movi r2,503 + 100287c: 14402b2e bgeu r2,r17,100292c <_malloc_r+0x150> + 1002880: 8806d27a srli r3,r17,9 + 1002884: 18003f1e bne r3,zero,1002984 <_malloc_r+0x1a8> + 1002888: 880cd0fa srli r6,r17,3 + 100288c: 300490fa slli r2,r6,3 + 1002890: 02c040b4 movhi r11,258 + 1002894: 5ae49004 addi r11,r11,-28096 + 1002898: 12cb883a add r5,r2,r11 + 100289c: 2c000317 ldw r16,12(r5) + 10028a0: 580f883a mov r7,r11 + 10028a4: 2c00041e bne r5,r16,10028b8 <_malloc_r+0xdc> + 10028a8: 00000a06 br 10028d4 <_malloc_r+0xf8> + 10028ac: 1800860e bge r3,zero,1002ac8 <_malloc_r+0x2ec> + 10028b0: 84000317 ldw r16,12(r16) + 10028b4: 2c000726 beq r5,r16,10028d4 <_malloc_r+0xf8> + 10028b8: 80800117 ldw r2,4(r16) + 10028bc: 00ffff04 movi r3,-4 + 10028c0: 10c8703a and r4,r2,r3 + 10028c4: 2447c83a sub r3,r4,r17 + 10028c8: 008003c4 movi r2,15 + 10028cc: 10fff70e bge r2,r3,10028ac <_malloc_r+0xd0> + 10028d0: 31bfffc4 addi r6,r6,-1 + 10028d4: 32400044 addi r9,r6,1 + 10028d8: 028040b4 movhi r10,258 + 10028dc: 52a49204 addi r10,r10,-28088 + 10028e0: 54000217 ldw r16,8(r10) + 10028e4: 8280a026 beq r16,r10,1002b68 <_malloc_r+0x38c> + 10028e8: 80800117 ldw r2,4(r16) + 10028ec: 00ffff04 movi r3,-4 + 10028f0: 10ca703a and r5,r2,r3 + 10028f4: 2c4dc83a sub r6,r5,r17 + 10028f8: 008003c4 movi r2,15 + 10028fc: 11808316 blt r2,r6,1002b0c <_malloc_r+0x330> + 1002900: 52800315 stw r10,12(r10) + 1002904: 52800215 stw r10,8(r10) + 1002908: 30002916 blt r6,zero,10029b0 <_malloc_r+0x1d4> + 100290c: 8147883a add r3,r16,r5 + 1002910: 18800117 ldw r2,4(r3) + 1002914: 9009883a mov r4,r18 + 1002918: 10800054 ori r2,r2,1 + 100291c: 18800115 stw r2,4(r3) + 1002920: 100d1a80 call 100d1a8 <__malloc_unlock> + 1002924: 80c00204 addi r3,r16,8 + 1002928: 003fc006 br 100282c <_malloc_r+0x50> + 100292c: 02c040b4 movhi r11,258 + 1002930: 5ae49004 addi r11,r11,-28096 + 1002934: 8ac5883a add r2,r17,r11 + 1002938: 14000317 ldw r16,12(r2) + 100293c: 580f883a mov r7,r11 + 1002940: 8806d0fa srli r3,r17,3 + 1002944: 14006c26 beq r2,r16,1002af8 <_malloc_r+0x31c> + 1002948: 80c00117 ldw r3,4(r16) + 100294c: 00bfff04 movi r2,-4 + 1002950: 81800317 ldw r6,12(r16) + 1002954: 1886703a and r3,r3,r2 + 1002958: 80c7883a add r3,r16,r3 + 100295c: 18800117 ldw r2,4(r3) + 1002960: 81400217 ldw r5,8(r16) + 1002964: 9009883a mov r4,r18 + 1002968: 10800054 ori r2,r2,1 + 100296c: 18800115 stw r2,4(r3) + 1002970: 31400215 stw r5,8(r6) + 1002974: 29800315 stw r6,12(r5) + 1002978: 100d1a80 call 100d1a8 <__malloc_unlock> + 100297c: 80c00204 addi r3,r16,8 + 1002980: 003faa06 br 100282c <_malloc_r+0x50> + 1002984: 00800104 movi r2,4 + 1002988: 10c0052e bgeu r2,r3,10029a0 <_malloc_r+0x1c4> + 100298c: 00800504 movi r2,20 + 1002990: 10c07836 bltu r2,r3,1002b74 <_malloc_r+0x398> + 1002994: 198016c4 addi r6,r3,91 + 1002998: 300490fa slli r2,r6,3 + 100299c: 003fbc06 br 1002890 <_malloc_r+0xb4> + 10029a0: 8804d1ba srli r2,r17,6 + 10029a4: 11800e04 addi r6,r2,56 + 10029a8: 300490fa slli r2,r6,3 + 10029ac: 003fb806 br 1002890 <_malloc_r+0xb4> + 10029b0: 00807fc4 movi r2,511 + 10029b4: 1140bb36 bltu r2,r5,1002ca4 <_malloc_r+0x4c8> + 10029b8: 2806d0fa srli r3,r5,3 + 10029bc: 573ffe04 addi fp,r10,-8 + 10029c0: 00800044 movi r2,1 + 10029c4: 180890fa slli r4,r3,3 + 10029c8: 1807d0ba srai r3,r3,2 + 10029cc: e1c00117 ldw r7,4(fp) + 10029d0: 5909883a add r4,r11,r4 + 10029d4: 21400217 ldw r5,8(r4) + 10029d8: 10c4983a sll r2,r2,r3 + 10029dc: 81000315 stw r4,12(r16) + 10029e0: 81400215 stw r5,8(r16) + 10029e4: 388eb03a or r7,r7,r2 + 10029e8: 2c000315 stw r16,12(r5) + 10029ec: 24000215 stw r16,8(r4) + 10029f0: e1c00115 stw r7,4(fp) + 10029f4: 4807883a mov r3,r9 + 10029f8: 4800cd16 blt r9,zero,1002d30 <_malloc_r+0x554> + 10029fc: 1807d0ba srai r3,r3,2 + 1002a00: 00800044 movi r2,1 + 1002a04: 10c8983a sll r4,r2,r3 + 1002a08: 39004436 bltu r7,r4,1002b1c <_malloc_r+0x340> + 1002a0c: 21c4703a and r2,r4,r7 + 1002a10: 10000a1e bne r2,zero,1002a3c <_malloc_r+0x260> + 1002a14: 2109883a add r4,r4,r4 + 1002a18: 00bfff04 movi r2,-4 + 1002a1c: 4884703a and r2,r9,r2 + 1002a20: 3906703a and r3,r7,r4 + 1002a24: 12400104 addi r9,r2,4 + 1002a28: 1800041e bne r3,zero,1002a3c <_malloc_r+0x260> + 1002a2c: 2109883a add r4,r4,r4 + 1002a30: 3904703a and r2,r7,r4 + 1002a34: 4a400104 addi r9,r9,4 + 1002a38: 103ffc26 beq r2,zero,1002a2c <_malloc_r+0x250> + 1002a3c: 480490fa slli r2,r9,3 + 1002a40: 4819883a mov r12,r9 + 1002a44: 023fff04 movi r8,-4 + 1002a48: 589b883a add r13,r11,r2 + 1002a4c: 6807883a mov r3,r13 + 1002a50: 014003c4 movi r5,15 + 1002a54: 1c000317 ldw r16,12(r3) + 1002a58: 1c00041e bne r3,r16,1002a6c <_malloc_r+0x290> + 1002a5c: 0000a706 br 1002cfc <_malloc_r+0x520> + 1002a60: 3000ab0e bge r6,zero,1002d10 <_malloc_r+0x534> + 1002a64: 84000317 ldw r16,12(r16) + 1002a68: 1c00a426 beq r3,r16,1002cfc <_malloc_r+0x520> + 1002a6c: 80800117 ldw r2,4(r16) + 1002a70: 1204703a and r2,r2,r8 + 1002a74: 144dc83a sub r6,r2,r17 + 1002a78: 29bff90e bge r5,r6,1002a60 <_malloc_r+0x284> + 1002a7c: 81000317 ldw r4,12(r16) + 1002a80: 80c00217 ldw r3,8(r16) + 1002a84: 89400054 ori r5,r17,1 + 1002a88: 8445883a add r2,r16,r17 + 1002a8c: 20c00215 stw r3,8(r4) + 1002a90: 19000315 stw r4,12(r3) + 1002a94: 81400115 stw r5,4(r16) + 1002a98: 1187883a add r3,r2,r6 + 1002a9c: 31000054 ori r4,r6,1 + 1002aa0: 50800315 stw r2,12(r10) + 1002aa4: 50800215 stw r2,8(r10) + 1002aa8: 19800015 stw r6,0(r3) + 1002aac: 11000115 stw r4,4(r2) + 1002ab0: 12800215 stw r10,8(r2) + 1002ab4: 12800315 stw r10,12(r2) + 1002ab8: 9009883a mov r4,r18 + 1002abc: 100d1a80 call 100d1a8 <__malloc_unlock> + 1002ac0: 80c00204 addi r3,r16,8 + 1002ac4: 003f5906 br 100282c <_malloc_r+0x50> + 1002ac8: 8109883a add r4,r16,r4 + 1002acc: 20800117 ldw r2,4(r4) + 1002ad0: 80c00217 ldw r3,8(r16) + 1002ad4: 81400317 ldw r5,12(r16) + 1002ad8: 10800054 ori r2,r2,1 + 1002adc: 20800115 stw r2,4(r4) + 1002ae0: 28c00215 stw r3,8(r5) + 1002ae4: 19400315 stw r5,12(r3) + 1002ae8: 9009883a mov r4,r18 + 1002aec: 100d1a80 call 100d1a8 <__malloc_unlock> + 1002af0: 80c00204 addi r3,r16,8 + 1002af4: 003f4d06 br 100282c <_malloc_r+0x50> + 1002af8: 80800204 addi r2,r16,8 + 1002afc: 14000317 ldw r16,12(r2) + 1002b00: 143f911e bne r2,r16,1002948 <_malloc_r+0x16c> + 1002b04: 1a400084 addi r9,r3,2 + 1002b08: 003f7306 br 10028d8 <_malloc_r+0xfc> + 1002b0c: 88c00054 ori r3,r17,1 + 1002b10: 8445883a add r2,r16,r17 + 1002b14: 80c00115 stw r3,4(r16) + 1002b18: 003fdf06 br 1002a98 <_malloc_r+0x2bc> + 1002b1c: e4000217 ldw r16,8(fp) + 1002b20: 00bfff04 movi r2,-4 + 1002b24: 80c00117 ldw r3,4(r16) + 1002b28: 802d883a mov r22,r16 + 1002b2c: 18aa703a and r21,r3,r2 + 1002b30: ac401636 bltu r21,r17,1002b8c <_malloc_r+0x3b0> + 1002b34: ac49c83a sub r4,r21,r17 + 1002b38: 008003c4 movi r2,15 + 1002b3c: 1100130e bge r2,r4,1002b8c <_malloc_r+0x3b0> + 1002b40: 88800054 ori r2,r17,1 + 1002b44: 8447883a add r3,r16,r17 + 1002b48: 80800115 stw r2,4(r16) + 1002b4c: 20800054 ori r2,r4,1 + 1002b50: 18800115 stw r2,4(r3) + 1002b54: e0c00215 stw r3,8(fp) + 1002b58: 9009883a mov r4,r18 + 1002b5c: 100d1a80 call 100d1a8 <__malloc_unlock> + 1002b60: 80c00204 addi r3,r16,8 + 1002b64: 003f3106 br 100282c <_malloc_r+0x50> + 1002b68: 39c00117 ldw r7,4(r7) + 1002b6c: 573ffe04 addi fp,r10,-8 + 1002b70: 003fa006 br 10029f4 <_malloc_r+0x218> + 1002b74: 00801504 movi r2,84 + 1002b78: 10c06736 bltu r2,r3,1002d18 <_malloc_r+0x53c> + 1002b7c: 8804d33a srli r2,r17,12 + 1002b80: 11801b84 addi r6,r2,110 + 1002b84: 300490fa slli r2,r6,3 + 1002b88: 003f4106 br 1002890 <_malloc_r+0xb4> + 1002b8c: d0a77417 ldw r2,-25136(gp) + 1002b90: d0e00a17 ldw r3,-32728(gp) + 1002b94: 053fffc4 movi r20,-1 + 1002b98: 10800404 addi r2,r2,16 + 1002b9c: 88a7883a add r19,r17,r2 + 1002ba0: 1d000326 beq r3,r20,1002bb0 <_malloc_r+0x3d4> + 1002ba4: 98c3ffc4 addi r3,r19,4095 + 1002ba8: 00bc0004 movi r2,-4096 + 1002bac: 18a6703a and r19,r3,r2 + 1002bb0: 9009883a mov r4,r18 + 1002bb4: 980b883a mov r5,r19 + 1002bb8: 10030e00 call 10030e0 <_sbrk_r> + 1002bbc: 1009883a mov r4,r2 + 1002bc0: 15000426 beq r2,r20,1002bd4 <_malloc_r+0x3f8> + 1002bc4: 854b883a add r5,r16,r21 + 1002bc8: 1029883a mov r20,r2 + 1002bcc: 11405a2e bgeu r2,r5,1002d38 <_malloc_r+0x55c> + 1002bd0: 87000c26 beq r16,fp,1002c04 <_malloc_r+0x428> + 1002bd4: e4000217 ldw r16,8(fp) + 1002bd8: 80c00117 ldw r3,4(r16) + 1002bdc: 00bfff04 movi r2,-4 + 1002be0: 1884703a and r2,r3,r2 + 1002be4: 14400336 bltu r2,r17,1002bf4 <_malloc_r+0x418> + 1002be8: 1449c83a sub r4,r2,r17 + 1002bec: 008003c4 movi r2,15 + 1002bf0: 113fd316 blt r2,r4,1002b40 <_malloc_r+0x364> + 1002bf4: 9009883a mov r4,r18 + 1002bf8: 100d1a80 call 100d1a8 <__malloc_unlock> + 1002bfc: 0007883a mov r3,zero + 1002c00: 003f0a06 br 100282c <_malloc_r+0x50> + 1002c04: 05c040b4 movhi r23,258 + 1002c08: bdcd2b04 addi r23,r23,13484 + 1002c0c: b8800017 ldw r2,0(r23) + 1002c10: 988d883a add r6,r19,r2 + 1002c14: b9800015 stw r6,0(r23) + 1002c18: d0e00a17 ldw r3,-32728(gp) + 1002c1c: 00bfffc4 movi r2,-1 + 1002c20: 18808e26 beq r3,r2,1002e5c <_malloc_r+0x680> + 1002c24: 2145c83a sub r2,r4,r5 + 1002c28: 3085883a add r2,r6,r2 + 1002c2c: b8800015 stw r2,0(r23) + 1002c30: 20c001cc andi r3,r4,7 + 1002c34: 18005f1e bne r3,zero,1002db4 <_malloc_r+0x5d8> + 1002c38: 000b883a mov r5,zero + 1002c3c: a4c5883a add r2,r20,r19 + 1002c40: 1083ffcc andi r2,r2,4095 + 1002c44: 00c40004 movi r3,4096 + 1002c48: 1887c83a sub r3,r3,r2 + 1002c4c: 28e7883a add r19,r5,r3 + 1002c50: 9009883a mov r4,r18 + 1002c54: 980b883a mov r5,r19 + 1002c58: 10030e00 call 10030e0 <_sbrk_r> + 1002c5c: 1007883a mov r3,r2 + 1002c60: 00bfffc4 movi r2,-1 + 1002c64: 18807a26 beq r3,r2,1002e50 <_malloc_r+0x674> + 1002c68: 1d05c83a sub r2,r3,r20 + 1002c6c: 9885883a add r2,r19,r2 + 1002c70: 10c00054 ori r3,r2,1 + 1002c74: b8800017 ldw r2,0(r23) + 1002c78: a021883a mov r16,r20 + 1002c7c: a0c00115 stw r3,4(r20) + 1002c80: 9885883a add r2,r19,r2 + 1002c84: b8800015 stw r2,0(r23) + 1002c88: e5000215 stw r20,8(fp) + 1002c8c: b7003626 beq r22,fp,1002d68 <_malloc_r+0x58c> + 1002c90: 018003c4 movi r6,15 + 1002c94: 35404b36 bltu r6,r21,1002dc4 <_malloc_r+0x5e8> + 1002c98: 00800044 movi r2,1 + 1002c9c: a0800115 stw r2,4(r20) + 1002ca0: 003fcd06 br 1002bd8 <_malloc_r+0x3fc> + 1002ca4: 2808d27a srli r4,r5,9 + 1002ca8: 2000371e bne r4,zero,1002d88 <_malloc_r+0x5ac> + 1002cac: 2808d0fa srli r4,r5,3 + 1002cb0: 200690fa slli r3,r4,3 + 1002cb4: 1ad1883a add r8,r3,r11 + 1002cb8: 41800217 ldw r6,8(r8) + 1002cbc: 41805b26 beq r8,r6,1002e2c <_malloc_r+0x650> + 1002cc0: 30800117 ldw r2,4(r6) + 1002cc4: 00ffff04 movi r3,-4 + 1002cc8: 10c4703a and r2,r2,r3 + 1002ccc: 2880022e bgeu r5,r2,1002cd8 <_malloc_r+0x4fc> + 1002cd0: 31800217 ldw r6,8(r6) + 1002cd4: 41bffa1e bne r8,r6,1002cc0 <_malloc_r+0x4e4> + 1002cd8: 32000317 ldw r8,12(r6) + 1002cdc: 39c00117 ldw r7,4(r7) + 1002ce0: 82000315 stw r8,12(r16) + 1002ce4: 81800215 stw r6,8(r16) + 1002ce8: 070040b4 movhi fp,258 + 1002cec: e7249004 addi fp,fp,-28096 + 1002cf0: 34000315 stw r16,12(r6) + 1002cf4: 44000215 stw r16,8(r8) + 1002cf8: 003f3e06 br 10029f4 <_malloc_r+0x218> + 1002cfc: 63000044 addi r12,r12,1 + 1002d00: 608000cc andi r2,r12,3 + 1002d04: 10005d26 beq r2,zero,1002e7c <_malloc_r+0x6a0> + 1002d08: 18c00204 addi r3,r3,8 + 1002d0c: 003f5106 br 1002a54 <_malloc_r+0x278> + 1002d10: 8089883a add r4,r16,r2 + 1002d14: 003f6d06 br 1002acc <_malloc_r+0x2f0> + 1002d18: 00805504 movi r2,340 + 1002d1c: 10c02036 bltu r2,r3,1002da0 <_malloc_r+0x5c4> + 1002d20: 8804d3fa srli r2,r17,15 + 1002d24: 11801dc4 addi r6,r2,119 + 1002d28: 300490fa slli r2,r6,3 + 1002d2c: 003ed806 br 1002890 <_malloc_r+0xb4> + 1002d30: 48c000c4 addi r3,r9,3 + 1002d34: 003f3106 br 10029fc <_malloc_r+0x220> + 1002d38: 05c040b4 movhi r23,258 + 1002d3c: bdcd2b04 addi r23,r23,13484 + 1002d40: b8800017 ldw r2,0(r23) + 1002d44: 988d883a add r6,r19,r2 + 1002d48: b9800015 stw r6,0(r23) + 1002d4c: 293fb21e bne r5,r4,1002c18 <_malloc_r+0x43c> + 1002d50: 2083ffcc andi r2,r4,4095 + 1002d54: 103fb01e bne r2,zero,1002c18 <_malloc_r+0x43c> + 1002d58: e4000217 ldw r16,8(fp) + 1002d5c: 9d45883a add r2,r19,r21 + 1002d60: 10800054 ori r2,r2,1 + 1002d64: 80800115 stw r2,4(r16) + 1002d68: b8c00017 ldw r3,0(r23) + 1002d6c: d0a77517 ldw r2,-25132(gp) + 1002d70: 10c0012e bgeu r2,r3,1002d78 <_malloc_r+0x59c> + 1002d74: d0e77515 stw r3,-25132(gp) + 1002d78: d0a77617 ldw r2,-25128(gp) + 1002d7c: 10ff962e bgeu r2,r3,1002bd8 <_malloc_r+0x3fc> + 1002d80: d0e77615 stw r3,-25128(gp) + 1002d84: 003f9406 br 1002bd8 <_malloc_r+0x3fc> + 1002d88: 00800104 movi r2,4 + 1002d8c: 11001e36 bltu r2,r4,1002e08 <_malloc_r+0x62c> + 1002d90: 2804d1ba srli r2,r5,6 + 1002d94: 11000e04 addi r4,r2,56 + 1002d98: 200690fa slli r3,r4,3 + 1002d9c: 003fc506 br 1002cb4 <_malloc_r+0x4d8> + 1002da0: 00815504 movi r2,1364 + 1002da4: 10c01d2e bgeu r2,r3,1002e1c <_malloc_r+0x640> + 1002da8: 01801f84 movi r6,126 + 1002dac: 0080fc04 movi r2,1008 + 1002db0: 003eb706 br 1002890 <_malloc_r+0xb4> + 1002db4: 00800204 movi r2,8 + 1002db8: 10cbc83a sub r5,r2,r3 + 1002dbc: 2169883a add r20,r4,r5 + 1002dc0: 003f9e06 br 1002c3c <_malloc_r+0x460> + 1002dc4: 00bffe04 movi r2,-8 + 1002dc8: a93ffd04 addi r4,r21,-12 + 1002dcc: 2088703a and r4,r4,r2 + 1002dd0: b10b883a add r5,r22,r4 + 1002dd4: 00c00144 movi r3,5 + 1002dd8: 28c00215 stw r3,8(r5) + 1002ddc: 28c00115 stw r3,4(r5) + 1002de0: b0800117 ldw r2,4(r22) + 1002de4: 1080004c andi r2,r2,1 + 1002de8: 2084b03a or r2,r4,r2 + 1002dec: b0800115 stw r2,4(r22) + 1002df0: 313fdd2e bgeu r6,r4,1002d68 <_malloc_r+0x58c> + 1002df4: b1400204 addi r5,r22,8 + 1002df8: 9009883a mov r4,r18 + 1002dfc: 10073600 call 1007360 <_free_r> + 1002e00: e4000217 ldw r16,8(fp) + 1002e04: 003fd806 br 1002d68 <_malloc_r+0x58c> + 1002e08: 00800504 movi r2,20 + 1002e0c: 11001536 bltu r2,r4,1002e64 <_malloc_r+0x688> + 1002e10: 210016c4 addi r4,r4,91 + 1002e14: 200690fa slli r3,r4,3 + 1002e18: 003fa606 br 1002cb4 <_malloc_r+0x4d8> + 1002e1c: 8804d4ba srli r2,r17,18 + 1002e20: 11801f04 addi r6,r2,124 + 1002e24: 300490fa slli r2,r6,3 + 1002e28: 003e9906 br 1002890 <_malloc_r+0xb4> + 1002e2c: 2009d0ba srai r4,r4,2 + 1002e30: 014040b4 movhi r5,258 + 1002e34: 29649004 addi r5,r5,-28096 + 1002e38: 00c00044 movi r3,1 + 1002e3c: 28800117 ldw r2,4(r5) + 1002e40: 1906983a sll r3,r3,r4 + 1002e44: 10c4b03a or r2,r2,r3 + 1002e48: 28800115 stw r2,4(r5) + 1002e4c: 003fa306 br 1002cdc <_malloc_r+0x500> + 1002e50: 0027883a mov r19,zero + 1002e54: 00c00044 movi r3,1 + 1002e58: 003f8606 br 1002c74 <_malloc_r+0x498> + 1002e5c: d1200a15 stw r4,-32728(gp) + 1002e60: 003f7306 br 1002c30 <_malloc_r+0x454> + 1002e64: 00801504 movi r2,84 + 1002e68: 11001936 bltu r2,r4,1002ed0 <_malloc_r+0x6f4> + 1002e6c: 2804d33a srli r2,r5,12 + 1002e70: 11001b84 addi r4,r2,110 + 1002e74: 200690fa slli r3,r4,3 + 1002e78: 003f8e06 br 1002cb4 <_malloc_r+0x4d8> + 1002e7c: 480b883a mov r5,r9 + 1002e80: 6807883a mov r3,r13 + 1002e84: 288000cc andi r2,r5,3 + 1002e88: 18fffe04 addi r3,r3,-8 + 1002e8c: 297fffc4 addi r5,r5,-1 + 1002e90: 10001526 beq r2,zero,1002ee8 <_malloc_r+0x70c> + 1002e94: 18800217 ldw r2,8(r3) + 1002e98: 10fffa26 beq r2,r3,1002e84 <_malloc_r+0x6a8> + 1002e9c: 2109883a add r4,r4,r4 + 1002ea0: 393f1e36 bltu r7,r4,1002b1c <_malloc_r+0x340> + 1002ea4: 203f1d26 beq r4,zero,1002b1c <_malloc_r+0x340> + 1002ea8: 21c4703a and r2,r4,r7 + 1002eac: 10000226 beq r2,zero,1002eb8 <_malloc_r+0x6dc> + 1002eb0: 6013883a mov r9,r12 + 1002eb4: 003ee106 br 1002a3c <_malloc_r+0x260> + 1002eb8: 2109883a add r4,r4,r4 + 1002ebc: 3904703a and r2,r7,r4 + 1002ec0: 63000104 addi r12,r12,4 + 1002ec4: 103ffc26 beq r2,zero,1002eb8 <_malloc_r+0x6dc> + 1002ec8: 6013883a mov r9,r12 + 1002ecc: 003edb06 br 1002a3c <_malloc_r+0x260> + 1002ed0: 00805504 movi r2,340 + 1002ed4: 11000836 bltu r2,r4,1002ef8 <_malloc_r+0x71c> + 1002ed8: 2804d3fa srli r2,r5,15 + 1002edc: 11001dc4 addi r4,r2,119 + 1002ee0: 200690fa slli r3,r4,3 + 1002ee4: 003f7306 br 1002cb4 <_malloc_r+0x4d8> + 1002ee8: 0104303a nor r2,zero,r4 + 1002eec: 388e703a and r7,r7,r2 + 1002ef0: e1c00115 stw r7,4(fp) + 1002ef4: 003fe906 br 1002e9c <_malloc_r+0x6c0> + 1002ef8: 00815504 movi r2,1364 + 1002efc: 1100032e bgeu r2,r4,1002f0c <_malloc_r+0x730> + 1002f00: 01001f84 movi r4,126 + 1002f04: 00c0fc04 movi r3,1008 + 1002f08: 003f6a06 br 1002cb4 <_malloc_r+0x4d8> + 1002f0c: 2804d4ba srli r2,r5,18 + 1002f10: 11001f04 addi r4,r2,124 + 1002f14: 200690fa slli r3,r4,3 + 1002f18: 003f6606 br 1002cb4 <_malloc_r+0x4d8> + +01002f1c : + 1002f1c: 008000c4 movi r2,3 + 1002f20: 29403fcc andi r5,r5,255 + 1002f24: 2007883a mov r3,r4 + 1002f28: 1180022e bgeu r2,r6,1002f34 + 1002f2c: 2084703a and r2,r4,r2 + 1002f30: 10000826 beq r2,zero,1002f54 + 1002f34: 30000526 beq r6,zero,1002f4c + 1002f38: 2805883a mov r2,r5 + 1002f3c: 30cd883a add r6,r6,r3 + 1002f40: 18800005 stb r2,0(r3) + 1002f44: 18c00044 addi r3,r3,1 + 1002f48: 19bffd1e bne r3,r6,1002f40 + 1002f4c: 2005883a mov r2,r4 + 1002f50: f800283a ret + 1002f54: 2804923a slli r2,r5,8 + 1002f58: 020003c4 movi r8,15 + 1002f5c: 200f883a mov r7,r4 + 1002f60: 2884b03a or r2,r5,r2 + 1002f64: 1006943a slli r3,r2,16 + 1002f68: 10c6b03a or r3,r2,r3 + 1002f6c: 41800a2e bgeu r8,r6,1002f98 + 1002f70: 4005883a mov r2,r8 + 1002f74: 31bffc04 addi r6,r6,-16 + 1002f78: 38c00015 stw r3,0(r7) + 1002f7c: 38c00115 stw r3,4(r7) + 1002f80: 38c00215 stw r3,8(r7) + 1002f84: 38c00315 stw r3,12(r7) + 1002f88: 39c00404 addi r7,r7,16 + 1002f8c: 11bff936 bltu r2,r6,1002f74 + 1002f90: 008000c4 movi r2,3 + 1002f94: 1180052e bgeu r2,r6,1002fac + 1002f98: 31bfff04 addi r6,r6,-4 + 1002f9c: 008000c4 movi r2,3 + 1002fa0: 38c00015 stw r3,0(r7) + 1002fa4: 39c00104 addi r7,r7,4 + 1002fa8: 11bffb36 bltu r2,r6,1002f98 + 1002fac: 3807883a mov r3,r7 + 1002fb0: 003fe006 br 1002f34 + +01002fb4 : + 1002fb4: defffb04 addi sp,sp,-20 + 1002fb8: dfc00115 stw ra,4(sp) + 1002fbc: d9400215 stw r5,8(sp) + 1002fc0: d9800315 stw r6,12(sp) + 1002fc4: d9c00415 stw r7,16(sp) + 1002fc8: 008040b4 movhi r2,258 + 1002fcc: 10ab9804 addi r2,r2,-20896 + 1002fd0: 10c00017 ldw r3,0(r2) + 1002fd4: 200b883a mov r5,r4 + 1002fd8: d8800204 addi r2,sp,8 + 1002fdc: 19000217 ldw r4,8(r3) + 1002fe0: 100d883a mov r6,r2 + 1002fe4: d8800015 stw r2,0(sp) + 1002fe8: 10054180 call 1005418 <__vfprintf_internal> + 1002fec: dfc00117 ldw ra,4(sp) + 1002ff0: dec00504 addi sp,sp,20 + 1002ff4: f800283a ret + +01002ff8 <_printf_r>: + 1002ff8: defffc04 addi sp,sp,-16 + 1002ffc: dfc00115 stw ra,4(sp) + 1003000: d9800215 stw r6,8(sp) + 1003004: d9c00315 stw r7,12(sp) + 1003008: 280d883a mov r6,r5 + 100300c: 21400217 ldw r5,8(r4) + 1003010: d8c00204 addi r3,sp,8 + 1003014: 180f883a mov r7,r3 + 1003018: d8c00015 stw r3,0(sp) + 100301c: 100356c0 call 100356c <___vfprintf_internal_r> + 1003020: dfc00117 ldw ra,4(sp) + 1003024: dec00404 addi sp,sp,16 + 1003028: f800283a ret + +0100302c <_puts_r>: + 100302c: defff604 addi sp,sp,-40 + 1003030: dc400715 stw r17,28(sp) + 1003034: 2023883a mov r17,r4 + 1003038: 2809883a mov r4,r5 + 100303c: dfc00915 stw ra,36(sp) + 1003040: dcc00815 stw r19,32(sp) + 1003044: 2827883a mov r19,r5 + 1003048: 10034a00 call 10034a0 + 100304c: 89400217 ldw r5,8(r17) + 1003050: 00c040b4 movhi r3,258 + 1003054: 18e36a04 addi r3,r3,-29272 + 1003058: 01c00044 movi r7,1 + 100305c: 12000044 addi r8,r2,1 + 1003060: d8c00515 stw r3,20(sp) + 1003064: d9c00615 stw r7,24(sp) + 1003068: d8c00304 addi r3,sp,12 + 100306c: 01c00084 movi r7,2 + 1003070: 8809883a mov r4,r17 + 1003074: d80d883a mov r6,sp + 1003078: d8c00015 stw r3,0(sp) + 100307c: dcc00315 stw r19,12(sp) + 1003080: da000215 stw r8,8(sp) + 1003084: d9c00115 stw r7,4(sp) + 1003088: d8800415 stw r2,16(sp) + 100308c: 10076740 call 1007674 <__sfvwrite_r> + 1003090: 00ffffc4 movi r3,-1 + 1003094: 10000626 beq r2,zero,10030b0 <_puts_r+0x84> + 1003098: 1805883a mov r2,r3 + 100309c: dfc00917 ldw ra,36(sp) + 10030a0: dcc00817 ldw r19,32(sp) + 10030a4: dc400717 ldw r17,28(sp) + 10030a8: dec00a04 addi sp,sp,40 + 10030ac: f800283a ret + 10030b0: 00c00284 movi r3,10 + 10030b4: 1805883a mov r2,r3 + 10030b8: dfc00917 ldw ra,36(sp) + 10030bc: dcc00817 ldw r19,32(sp) + 10030c0: dc400717 ldw r17,28(sp) + 10030c4: dec00a04 addi sp,sp,40 + 10030c8: f800283a ret + +010030cc : + 10030cc: 008040b4 movhi r2,258 + 10030d0: 10ab9804 addi r2,r2,-20896 + 10030d4: 200b883a mov r5,r4 + 10030d8: 11000017 ldw r4,0(r2) + 10030dc: 100302c1 jmpi 100302c <_puts_r> + +010030e0 <_sbrk_r>: + 10030e0: defffd04 addi sp,sp,-12 + 10030e4: dc000015 stw r16,0(sp) + 10030e8: 040040b4 movhi r16,258 + 10030ec: 84330404 addi r16,r16,-13296 + 10030f0: dc400115 stw r17,4(sp) + 10030f4: 80000015 stw zero,0(r16) + 10030f8: 2023883a mov r17,r4 + 10030fc: 2809883a mov r4,r5 + 1003100: dfc00215 stw ra,8(sp) + 1003104: 100cd5c0 call 100cd5c + 1003108: 1007883a mov r3,r2 + 100310c: 00bfffc4 movi r2,-1 + 1003110: 18800626 beq r3,r2,100312c <_sbrk_r+0x4c> + 1003114: 1805883a mov r2,r3 + 1003118: dfc00217 ldw ra,8(sp) + 100311c: dc400117 ldw r17,4(sp) + 1003120: dc000017 ldw r16,0(sp) + 1003124: dec00304 addi sp,sp,12 + 1003128: f800283a ret + 100312c: 80800017 ldw r2,0(r16) + 1003130: 103ff826 beq r2,zero,1003114 <_sbrk_r+0x34> + 1003134: 88800015 stw r2,0(r17) + 1003138: 1805883a mov r2,r3 + 100313c: dfc00217 ldw ra,8(sp) + 1003140: dc400117 ldw r17,4(sp) + 1003144: dc000017 ldw r16,0(sp) + 1003148: dec00304 addi sp,sp,12 + 100314c: f800283a ret + +01003150 <_raise_r>: + 1003150: defffd04 addi sp,sp,-12 + 1003154: 008007c4 movi r2,31 + 1003158: dc400115 stw r17,4(sp) + 100315c: dc000015 stw r16,0(sp) + 1003160: dfc00215 stw ra,8(sp) + 1003164: 2821883a mov r16,r5 + 1003168: 2023883a mov r17,r4 + 100316c: 11402736 bltu r2,r5,100320c <_raise_r+0xbc> + 1003170: 20c0b717 ldw r3,732(r4) + 1003174: 18001326 beq r3,zero,10031c4 <_raise_r+0x74> + 1003178: 2945883a add r2,r5,r5 + 100317c: 1085883a add r2,r2,r2 + 1003180: 188b883a add r5,r3,r2 + 1003184: 28c00017 ldw r3,0(r5) + 1003188: 18000e26 beq r3,zero,10031c4 <_raise_r+0x74> + 100318c: 01000044 movi r4,1 + 1003190: 19000526 beq r3,r4,10031a8 <_raise_r+0x58> + 1003194: 00bfffc4 movi r2,-1 + 1003198: 18801326 beq r3,r2,10031e8 <_raise_r+0x98> + 100319c: 28000015 stw zero,0(r5) + 10031a0: 8009883a mov r4,r16 + 10031a4: 183ee83a callr r3 + 10031a8: 0007883a mov r3,zero + 10031ac: 1805883a mov r2,r3 + 10031b0: dfc00217 ldw ra,8(sp) + 10031b4: dc400117 ldw r17,4(sp) + 10031b8: dc000017 ldw r16,0(sp) + 10031bc: dec00304 addi sp,sp,12 + 10031c0: f800283a ret + 10031c4: 10034280 call 1003428 <_getpid_r> + 10031c8: 100b883a mov r5,r2 + 10031cc: 8809883a mov r4,r17 + 10031d0: 800d883a mov r6,r16 + 10031d4: dfc00217 ldw ra,8(sp) + 10031d8: dc400117 ldw r17,4(sp) + 10031dc: dc000017 ldw r16,0(sp) + 10031e0: dec00304 addi sp,sp,12 + 10031e4: 100342c1 jmpi 100342c <_kill_r> + 10031e8: 2007883a mov r3,r4 + 10031ec: 00800584 movi r2,22 + 10031f0: 88800015 stw r2,0(r17) + 10031f4: 1805883a mov r2,r3 + 10031f8: dfc00217 ldw ra,8(sp) + 10031fc: dc400117 ldw r17,4(sp) + 1003200: dc000017 ldw r16,0(sp) + 1003204: dec00304 addi sp,sp,12 + 1003208: f800283a ret + 100320c: 00800584 movi r2,22 + 1003210: 00ffffc4 movi r3,-1 + 1003214: 20800015 stw r2,0(r4) + 1003218: 003fe406 br 10031ac <_raise_r+0x5c> + +0100321c : + 100321c: 008040b4 movhi r2,258 + 1003220: 10ab9804 addi r2,r2,-20896 + 1003224: 200b883a mov r5,r4 + 1003228: 11000017 ldw r4,0(r2) + 100322c: 10031501 jmpi 1003150 <_raise_r> + +01003230 <_init_signal_r>: + 1003230: 2080b717 ldw r2,732(r4) + 1003234: defffe04 addi sp,sp,-8 + 1003238: dc000015 stw r16,0(sp) + 100323c: dfc00115 stw ra,4(sp) + 1003240: 2021883a mov r16,r4 + 1003244: 10000526 beq r2,zero,100325c <_init_signal_r+0x2c> + 1003248: 0005883a mov r2,zero + 100324c: dfc00117 ldw ra,4(sp) + 1003250: dc000017 ldw r16,0(sp) + 1003254: dec00204 addi sp,sp,8 + 1003258: f800283a ret + 100325c: 01402004 movi r5,128 + 1003260: 10027dc0 call 10027dc <_malloc_r> + 1003264: 1009883a mov r4,r2 + 1003268: 8080b715 stw r2,732(r16) + 100326c: 10000726 beq r2,zero,100328c <_init_signal_r+0x5c> + 1003270: 0007883a mov r3,zero + 1003274: 01402004 movi r5,128 + 1003278: 20c5883a add r2,r4,r3 + 100327c: 18c00104 addi r3,r3,4 + 1003280: 10000015 stw zero,0(r2) + 1003284: 197ffc1e bne r3,r5,1003278 <_init_signal_r+0x48> + 1003288: 003fef06 br 1003248 <_init_signal_r+0x18> + 100328c: 00bfffc4 movi r2,-1 + 1003290: 003fee06 br 100324c <_init_signal_r+0x1c> + +01003294 <_init_signal>: + 1003294: 008040b4 movhi r2,258 + 1003298: 10ab9804 addi r2,r2,-20896 + 100329c: 11000017 ldw r4,0(r2) + 10032a0: 10032301 jmpi 1003230 <_init_signal_r> + +010032a4 <__sigtramp_r>: + 10032a4: defffd04 addi sp,sp,-12 + 10032a8: 008007c4 movi r2,31 + 10032ac: dc000115 stw r16,4(sp) + 10032b0: dfc00215 stw ra,8(sp) + 10032b4: 2021883a mov r16,r4 + 10032b8: 11401336 bltu r2,r5,1003308 <__sigtramp_r+0x64> + 10032bc: 20c0b717 ldw r3,732(r4) + 10032c0: 18001f26 beq r3,zero,1003340 <__sigtramp_r+0x9c> + 10032c4: 2945883a add r2,r5,r5 + 10032c8: 1085883a add r2,r2,r2 + 10032cc: 10c9883a add r4,r2,r3 + 10032d0: 20c00017 ldw r3,0(r4) + 10032d4: 18001626 beq r3,zero,1003330 <__sigtramp_r+0x8c> + 10032d8: 00bfffc4 movi r2,-1 + 10032dc: 18801626 beq r3,r2,1003338 <__sigtramp_r+0x94> + 10032e0: 00800044 movi r2,1 + 10032e4: 18800d26 beq r3,r2,100331c <__sigtramp_r+0x78> + 10032e8: 20000015 stw zero,0(r4) + 10032ec: 2809883a mov r4,r5 + 10032f0: 183ee83a callr r3 + 10032f4: 0005883a mov r2,zero + 10032f8: dfc00217 ldw ra,8(sp) + 10032fc: dc000117 ldw r16,4(sp) + 1003300: dec00304 addi sp,sp,12 + 1003304: f800283a ret + 1003308: 00bfffc4 movi r2,-1 + 100330c: dfc00217 ldw ra,8(sp) + 1003310: dc000117 ldw r16,4(sp) + 1003314: dec00304 addi sp,sp,12 + 1003318: f800283a ret + 100331c: 008000c4 movi r2,3 + 1003320: dfc00217 ldw ra,8(sp) + 1003324: dc000117 ldw r16,4(sp) + 1003328: dec00304 addi sp,sp,12 + 100332c: f800283a ret + 1003330: 00800044 movi r2,1 + 1003334: 003ff006 br 10032f8 <__sigtramp_r+0x54> + 1003338: 00800084 movi r2,2 + 100333c: 003fee06 br 10032f8 <__sigtramp_r+0x54> + 1003340: d9400015 stw r5,0(sp) + 1003344: 10032300 call 1003230 <_init_signal_r> + 1003348: d9400017 ldw r5,0(sp) + 100334c: 103fee1e bne r2,zero,1003308 <__sigtramp_r+0x64> + 1003350: 80c0b717 ldw r3,732(r16) + 1003354: 003fdb06 br 10032c4 <__sigtramp_r+0x20> + +01003358 <__sigtramp>: + 1003358: 008040b4 movhi r2,258 + 100335c: 10ab9804 addi r2,r2,-20896 + 1003360: 200b883a mov r5,r4 + 1003364: 11000017 ldw r4,0(r2) + 1003368: 10032a41 jmpi 10032a4 <__sigtramp_r> + +0100336c <_signal_r>: + 100336c: defffc04 addi sp,sp,-16 + 1003370: 008007c4 movi r2,31 + 1003374: dc800215 stw r18,8(sp) + 1003378: dc400115 stw r17,4(sp) + 100337c: dc000015 stw r16,0(sp) + 1003380: dfc00315 stw ra,12(sp) + 1003384: 2823883a mov r17,r5 + 1003388: 00ffffc4 movi r3,-1 + 100338c: 3025883a mov r18,r6 + 1003390: 2021883a mov r16,r4 + 1003394: 1140092e bgeu r2,r5,10033bc <_signal_r+0x50> + 1003398: 00800584 movi r2,22 + 100339c: 20800015 stw r2,0(r4) + 10033a0: 1805883a mov r2,r3 + 10033a4: dfc00317 ldw ra,12(sp) + 10033a8: dc800217 ldw r18,8(sp) + 10033ac: dc400117 ldw r17,4(sp) + 10033b0: dc000017 ldw r16,0(sp) + 10033b4: dec00404 addi sp,sp,16 + 10033b8: f800283a ret + 10033bc: 2140b717 ldw r5,732(r4) + 10033c0: 28000c26 beq r5,zero,10033f4 <_signal_r+0x88> + 10033c4: 8c45883a add r2,r17,r17 + 10033c8: 1085883a add r2,r2,r2 + 10033cc: 1145883a add r2,r2,r5 + 10033d0: 10c00017 ldw r3,0(r2) + 10033d4: 14800015 stw r18,0(r2) + 10033d8: 1805883a mov r2,r3 + 10033dc: dfc00317 ldw ra,12(sp) + 10033e0: dc800217 ldw r18,8(sp) + 10033e4: dc400117 ldw r17,4(sp) + 10033e8: dc000017 ldw r16,0(sp) + 10033ec: dec00404 addi sp,sp,16 + 10033f0: f800283a ret + 10033f4: 10032300 call 1003230 <_init_signal_r> + 10033f8: 1000021e bne r2,zero,1003404 <_signal_r+0x98> + 10033fc: 8140b717 ldw r5,732(r16) + 1003400: 003ff006 br 10033c4 <_signal_r+0x58> + 1003404: 00ffffc4 movi r3,-1 + 1003408: 003fe506 br 10033a0 <_signal_r+0x34> + +0100340c : + 100340c: 018040b4 movhi r6,258 + 1003410: 31ab9804 addi r6,r6,-20896 + 1003414: 2007883a mov r3,r4 + 1003418: 31000017 ldw r4,0(r6) + 100341c: 280d883a mov r6,r5 + 1003420: 180b883a mov r5,r3 + 1003424: 100336c1 jmpi 100336c <_signal_r> + +01003428 <_getpid_r>: + 1003428: 100c5981 jmpi 100c598 + +0100342c <_kill_r>: + 100342c: defffd04 addi sp,sp,-12 + 1003430: dc000015 stw r16,0(sp) + 1003434: 040040b4 movhi r16,258 + 1003438: 84330404 addi r16,r16,-13296 + 100343c: dc400115 stw r17,4(sp) + 1003440: 80000015 stw zero,0(r16) + 1003444: 2023883a mov r17,r4 + 1003448: 2809883a mov r4,r5 + 100344c: 300b883a mov r5,r6 + 1003450: dfc00215 stw ra,8(sp) + 1003454: 100c6d80 call 100c6d8 + 1003458: 1007883a mov r3,r2 + 100345c: 00bfffc4 movi r2,-1 + 1003460: 18800626 beq r3,r2,100347c <_kill_r+0x50> + 1003464: 1805883a mov r2,r3 + 1003468: dfc00217 ldw ra,8(sp) + 100346c: dc400117 ldw r17,4(sp) + 1003470: dc000017 ldw r16,0(sp) + 1003474: dec00304 addi sp,sp,12 + 1003478: f800283a ret + 100347c: 80800017 ldw r2,0(r16) + 1003480: 103ff826 beq r2,zero,1003464 <_kill_r+0x38> + 1003484: 88800015 stw r2,0(r17) + 1003488: 1805883a mov r2,r3 + 100348c: dfc00217 ldw ra,8(sp) + 1003490: dc400117 ldw r17,4(sp) + 1003494: dc000017 ldw r16,0(sp) + 1003498: dec00304 addi sp,sp,12 + 100349c: f800283a ret + +010034a0 : + 10034a0: 208000cc andi r2,r4,3 + 10034a4: 2011883a mov r8,r4 + 10034a8: 1000161e bne r2,zero,1003504 + 10034ac: 20c00017 ldw r3,0(r4) + 10034b0: 017fbff4 movhi r5,65279 + 10034b4: 297fbfc4 addi r5,r5,-257 + 10034b8: 01e02074 movhi r7,32897 + 10034bc: 39e02004 addi r7,r7,-32640 + 10034c0: 1945883a add r2,r3,r5 + 10034c4: 11c4703a and r2,r2,r7 + 10034c8: 00c6303a nor r3,zero,r3 + 10034cc: 1886703a and r3,r3,r2 + 10034d0: 18000c1e bne r3,zero,1003504 + 10034d4: 280d883a mov r6,r5 + 10034d8: 380b883a mov r5,r7 + 10034dc: 21000104 addi r4,r4,4 + 10034e0: 20800017 ldw r2,0(r4) + 10034e4: 1187883a add r3,r2,r6 + 10034e8: 1946703a and r3,r3,r5 + 10034ec: 0084303a nor r2,zero,r2 + 10034f0: 10c4703a and r2,r2,r3 + 10034f4: 103ff926 beq r2,zero,10034dc + 10034f8: 20800007 ldb r2,0(r4) + 10034fc: 10000326 beq r2,zero,100350c + 1003500: 21000044 addi r4,r4,1 + 1003504: 20800007 ldb r2,0(r4) + 1003508: 103ffd1e bne r2,zero,1003500 + 100350c: 2205c83a sub r2,r4,r8 + 1003510: f800283a ret + +01003514 <__sprint_r>: + 1003514: 30800217 ldw r2,8(r6) + 1003518: defffe04 addi sp,sp,-8 + 100351c: dc000015 stw r16,0(sp) + 1003520: dfc00115 stw ra,4(sp) + 1003524: 3021883a mov r16,r6 + 1003528: 0007883a mov r3,zero + 100352c: 1000061e bne r2,zero,1003548 <__sprint_r+0x34> + 1003530: 1805883a mov r2,r3 + 1003534: 30000115 stw zero,4(r6) + 1003538: dfc00117 ldw ra,4(sp) + 100353c: dc000017 ldw r16,0(sp) + 1003540: dec00204 addi sp,sp,8 + 1003544: f800283a ret + 1003548: 10076740 call 1007674 <__sfvwrite_r> + 100354c: 1007883a mov r3,r2 + 1003550: 1805883a mov r2,r3 + 1003554: 80000115 stw zero,4(r16) + 1003558: 80000215 stw zero,8(r16) + 100355c: dfc00117 ldw ra,4(sp) + 1003560: dc000017 ldw r16,0(sp) + 1003564: dec00204 addi sp,sp,8 + 1003568: f800283a ret + +0100356c <___vfprintf_internal_r>: + 100356c: defea404 addi sp,sp,-1392 + 1003570: dd815815 stw r22,1376(sp) + 1003574: dc015215 stw r16,1352(sp) + 1003578: d9c15115 stw r7,1348(sp) + 100357c: dfc15b15 stw ra,1388(sp) + 1003580: df015a15 stw fp,1384(sp) + 1003584: ddc15915 stw r23,1380(sp) + 1003588: dd415715 stw r21,1372(sp) + 100358c: dd015615 stw r20,1368(sp) + 1003590: dcc15515 stw r19,1364(sp) + 1003594: dc815415 stw r18,1360(sp) + 1003598: dc415315 stw r17,1356(sp) + 100359c: 282d883a mov r22,r5 + 10035a0: 3021883a mov r16,r6 + 10035a4: d9014f15 stw r4,1340(sp) + 10035a8: 1007c980 call 1007c98 <_localeconv_r> + 10035ac: 10800017 ldw r2,0(r2) + 10035b0: d9c15117 ldw r7,1348(sp) + 10035b4: d8814915 stw r2,1316(sp) + 10035b8: d8814f17 ldw r2,1340(sp) + 10035bc: 10000226 beq r2,zero,10035c8 <___vfprintf_internal_r+0x5c> + 10035c0: 10800e17 ldw r2,56(r2) + 10035c4: 10020d26 beq r2,zero,1003dfc <___vfprintf_internal_r+0x890> + 10035c8: b080030b ldhu r2,12(r22) + 10035cc: 1080020c andi r2,r2,8 + 10035d0: 10020e26 beq r2,zero,1003e0c <___vfprintf_internal_r+0x8a0> + 10035d4: b0800417 ldw r2,16(r22) + 10035d8: 10020c26 beq r2,zero,1003e0c <___vfprintf_internal_r+0x8a0> + 10035dc: b200030b ldhu r8,12(r22) + 10035e0: 00800284 movi r2,10 + 10035e4: 40c0068c andi r3,r8,26 + 10035e8: 18802f1e bne r3,r2,10036a8 <___vfprintf_internal_r+0x13c> + 10035ec: b080038f ldh r2,14(r22) + 10035f0: 10002d16 blt r2,zero,10036a8 <___vfprintf_internal_r+0x13c> + 10035f4: b240038b ldhu r9,14(r22) + 10035f8: b2800717 ldw r10,28(r22) + 10035fc: b2c00917 ldw r11,36(r22) + 1003600: d9014f17 ldw r4,1340(sp) + 1003604: dc402904 addi r17,sp,164 + 1003608: d8804004 addi r2,sp,256 + 100360c: 00c10004 movi r3,1024 + 1003610: 423fff4c andi r8,r8,65533 + 1003614: 800d883a mov r6,r16 + 1003618: 880b883a mov r5,r17 + 100361c: da002c0d sth r8,176(sp) + 1003620: da402c8d sth r9,178(sp) + 1003624: da803015 stw r10,192(sp) + 1003628: dac03215 stw r11,200(sp) + 100362c: d8802d15 stw r2,180(sp) + 1003630: d8c02e15 stw r3,184(sp) + 1003634: d8802915 stw r2,164(sp) + 1003638: d8c02b15 stw r3,172(sp) + 100363c: d8002f15 stw zero,188(sp) + 1003640: 100356c0 call 100356c <___vfprintf_internal_r> + 1003644: d8814b15 stw r2,1324(sp) + 1003648: 10000416 blt r2,zero,100365c <___vfprintf_internal_r+0xf0> + 100364c: d9014f17 ldw r4,1340(sp) + 1003650: 880b883a mov r5,r17 + 1003654: 1006d440 call 1006d44 <_fflush_r> + 1003658: 1002321e bne r2,zero,1003f24 <___vfprintf_internal_r+0x9b8> + 100365c: d8802c0b ldhu r2,176(sp) + 1003660: 1080100c andi r2,r2,64 + 1003664: 10000326 beq r2,zero,1003674 <___vfprintf_internal_r+0x108> + 1003668: b080030b ldhu r2,12(r22) + 100366c: 10801014 ori r2,r2,64 + 1003670: b080030d sth r2,12(r22) + 1003674: d8814b17 ldw r2,1324(sp) + 1003678: dfc15b17 ldw ra,1388(sp) + 100367c: df015a17 ldw fp,1384(sp) + 1003680: ddc15917 ldw r23,1380(sp) + 1003684: dd815817 ldw r22,1376(sp) + 1003688: dd415717 ldw r21,1372(sp) + 100368c: dd015617 ldw r20,1368(sp) + 1003690: dcc15517 ldw r19,1364(sp) + 1003694: dc815417 ldw r18,1360(sp) + 1003698: dc415317 ldw r17,1356(sp) + 100369c: dc015217 ldw r16,1352(sp) + 10036a0: dec15c04 addi sp,sp,1392 + 10036a4: f800283a ret + 10036a8: 0005883a mov r2,zero + 10036ac: 0007883a mov r3,zero + 10036b0: dd401904 addi r21,sp,100 + 10036b4: d8814215 stw r2,1288(sp) + 10036b8: 802f883a mov r23,r16 + 10036bc: d8c14315 stw r3,1292(sp) + 10036c0: d8014b15 stw zero,1324(sp) + 10036c4: d8014815 stw zero,1312(sp) + 10036c8: d8014415 stw zero,1296(sp) + 10036cc: d8014715 stw zero,1308(sp) + 10036d0: dd400c15 stw r21,48(sp) + 10036d4: d8000e15 stw zero,56(sp) + 10036d8: d8000d15 stw zero,52(sp) + 10036dc: b8800007 ldb r2,0(r23) + 10036e0: 10001926 beq r2,zero,1003748 <___vfprintf_internal_r+0x1dc> + 10036e4: 00c00944 movi r3,37 + 10036e8: 10c01726 beq r2,r3,1003748 <___vfprintf_internal_r+0x1dc> + 10036ec: b821883a mov r16,r23 + 10036f0: 00000106 br 10036f8 <___vfprintf_internal_r+0x18c> + 10036f4: 10c00326 beq r2,r3,1003704 <___vfprintf_internal_r+0x198> + 10036f8: 84000044 addi r16,r16,1 + 10036fc: 80800007 ldb r2,0(r16) + 1003700: 103ffc1e bne r2,zero,10036f4 <___vfprintf_internal_r+0x188> + 1003704: 85e7c83a sub r19,r16,r23 + 1003708: 98000e26 beq r19,zero,1003744 <___vfprintf_internal_r+0x1d8> + 100370c: dc800e17 ldw r18,56(sp) + 1003710: dc400d17 ldw r17,52(sp) + 1003714: 008001c4 movi r2,7 + 1003718: 94e5883a add r18,r18,r19 + 100371c: 8c400044 addi r17,r17,1 + 1003720: adc00015 stw r23,0(r21) + 1003724: dc800e15 stw r18,56(sp) + 1003728: acc00115 stw r19,4(r21) + 100372c: dc400d15 stw r17,52(sp) + 1003730: 14428b16 blt r2,r17,1004160 <___vfprintf_internal_r+0xbf4> + 1003734: ad400204 addi r21,r21,8 + 1003738: d9014b17 ldw r4,1324(sp) + 100373c: 24c9883a add r4,r4,r19 + 1003740: d9014b15 stw r4,1324(sp) + 1003744: 802f883a mov r23,r16 + 1003748: b8800007 ldb r2,0(r23) + 100374c: 10013c26 beq r2,zero,1003c40 <___vfprintf_internal_r+0x6d4> + 1003750: bdc00044 addi r23,r23,1 + 1003754: d8000405 stb zero,16(sp) + 1003758: b8c00007 ldb r3,0(r23) + 100375c: 04ffffc4 movi r19,-1 + 1003760: d8014c15 stw zero,1328(sp) + 1003764: d8014a15 stw zero,1320(sp) + 1003768: d8c14d15 stw r3,1332(sp) + 100376c: bdc00044 addi r23,r23,1 + 1003770: d9414d17 ldw r5,1332(sp) + 1003774: 00801604 movi r2,88 + 1003778: 28fff804 addi r3,r5,-32 + 100377c: 10c06036 bltu r2,r3,1003900 <___vfprintf_internal_r+0x394> + 1003780: 18c5883a add r2,r3,r3 + 1003784: 1085883a add r2,r2,r2 + 1003788: 00c04034 movhi r3,256 + 100378c: 18cde704 addi r3,r3,14236 + 1003790: 10c5883a add r2,r2,r3 + 1003794: 11000017 ldw r4,0(r2) + 1003798: 2000683a jmp r4 + 100379c: 01004710 cmplti r4,zero,284 + 10037a0: 01003900 call 100390 + 10037a4: 01003900 call 100390 + 10037a8: 010046fc xorhi r4,zero,283 + 10037ac: 01003900 call 100390 + 10037b0: 01003900 call 100390 + 10037b4: 01003900 call 100390 + 10037b8: 01003900 call 100390 + 10037bc: 01003900 call 100390 + 10037c0: 01003900 call 100390 + 10037c4: 010044dc xori r4,zero,275 + 10037c8: 010046ec andhi r4,zero,283 + 10037cc: 01003900 call 100390 + 10037d0: 010044f4 movhi r4,275 + 10037d4: 01004788 cmpgei r4,zero,286 + 10037d8: 01003900 call 100390 + 10037dc: 01004774 movhi r4,285 + 10037e0: 0100473c xorhi r4,zero,284 + 10037e4: 0100473c xorhi r4,zero,284 + 10037e8: 0100473c xorhi r4,zero,284 + 10037ec: 0100473c xorhi r4,zero,284 + 10037f0: 0100473c xorhi r4,zero,284 + 10037f4: 0100473c xorhi r4,zero,284 + 10037f8: 0100473c xorhi r4,zero,284 + 10037fc: 0100473c xorhi r4,zero,284 + 1003800: 0100473c xorhi r4,zero,284 + 1003804: 01003900 call 100390 + 1003808: 01003900 call 100390 + 100380c: 01003900 call 100390 + 1003810: 01003900 call 100390 + 1003814: 01003900 call 100390 + 1003818: 01003900 call 100390 + 100381c: 01003900 call 100390 + 1003820: 01003900 call 100390 + 1003824: 01003900 call 100390 + 1003828: 01003900 call 100390 + 100382c: 01003f58 cmpnei r4,zero,253 + 1003830: 010045c4 movi r4,279 + 1003834: 01003900 call 100390 + 1003838: 010045c4 movi r4,279 + 100383c: 01003900 call 100390 + 1003840: 01003900 call 100390 + 1003844: 01003900 call 100390 + 1003848: 01003900 call 100390 + 100384c: 01004728 cmpgeui r4,zero,284 + 1003850: 01003900 call 100390 + 1003854: 01003900 call 100390 + 1003858: 0100400c andi r4,zero,256 + 100385c: 01003900 call 100390 + 1003860: 01003900 call 100390 + 1003864: 01003900 call 100390 + 1003868: 01003900 call 100390 + 100386c: 01003900 call 100390 + 1003870: 01004058 cmpnei r4,zero,257 + 1003874: 01003900 call 100390 + 1003878: 01003900 call 100390 + 100387c: 01004678 rdprs r4,zero,281 + 1003880: 01003900 call 100390 + 1003884: 01003900 call 100390 + 1003888: 01003900 call 100390 + 100388c: 01003900 call 100390 + 1003890: 01003900 call 100390 + 1003894: 01003900 call 100390 + 1003898: 01003900 call 100390 + 100389c: 01003900 call 100390 + 10038a0: 01003900 call 100390 + 10038a4: 01003900 call 100390 + 10038a8: 0100464c andi r4,zero,281 + 10038ac: 01003f64 muli r4,zero,253 + 10038b0: 010045c4 movi r4,279 + 10038b4: 010045c4 movi r4,279 + 10038b8: 010045c4 movi r4,279 + 10038bc: 010045b0 cmpltui r4,zero,278 + 10038c0: 01003f64 muli r4,zero,253 + 10038c4: 01003900 call 100390 + 10038c8: 01003900 call 100390 + 10038cc: 01004538 rdprs r4,zero,276 + 10038d0: 01003900 call 100390 + 10038d4: 01004508 cmpgei r4,zero,276 + 10038d8: 01004018 cmpnei r4,zero,256 + 10038dc: 01004568 cmpgeui r4,zero,277 + 10038e0: 01004554 movui r4,277 + 10038e4: 01003900 call 100390 + 10038e8: 010047e4 muli r4,zero,287 + 10038ec: 01003900 call 100390 + 10038f0: 01004064 muli r4,zero,257 + 10038f4: 01003900 call 100390 + 10038f8: 01003900 call 100390 + 10038fc: 010046dc xori r4,zero,283 + 1003900: d9014d17 ldw r4,1332(sp) + 1003904: 2000ce26 beq r4,zero,1003c40 <___vfprintf_internal_r+0x6d4> + 1003908: 01400044 movi r5,1 + 100390c: d9800f04 addi r6,sp,60 + 1003910: d9c14015 stw r7,1280(sp) + 1003914: d9414515 stw r5,1300(sp) + 1003918: d9814115 stw r6,1284(sp) + 100391c: 280f883a mov r7,r5 + 1003920: d9000f05 stb r4,60(sp) + 1003924: d8000405 stb zero,16(sp) + 1003928: d8014615 stw zero,1304(sp) + 100392c: d8c14c17 ldw r3,1328(sp) + 1003930: 1880008c andi r2,r3,2 + 1003934: 1005003a cmpeq r2,r2,zero + 1003938: d8815015 stw r2,1344(sp) + 100393c: 1000031e bne r2,zero,100394c <___vfprintf_internal_r+0x3e0> + 1003940: d9014517 ldw r4,1300(sp) + 1003944: 21000084 addi r4,r4,2 + 1003948: d9014515 stw r4,1300(sp) + 100394c: d9414c17 ldw r5,1328(sp) + 1003950: 2940210c andi r5,r5,132 + 1003954: d9414e15 stw r5,1336(sp) + 1003958: 28002d1e bne r5,zero,1003a10 <___vfprintf_internal_r+0x4a4> + 100395c: d9814a17 ldw r6,1320(sp) + 1003960: d8814517 ldw r2,1300(sp) + 1003964: 30a1c83a sub r16,r6,r2 + 1003968: 0400290e bge zero,r16,1003a10 <___vfprintf_internal_r+0x4a4> + 100396c: 00800404 movi r2,16 + 1003970: 1404580e bge r2,r16,1004ad4 <___vfprintf_internal_r+0x1568> + 1003974: dc800e17 ldw r18,56(sp) + 1003978: dc400d17 ldw r17,52(sp) + 100397c: 1027883a mov r19,r2 + 1003980: 070040b4 movhi fp,258 + 1003984: e7238684 addi fp,fp,-29158 + 1003988: 050001c4 movi r20,7 + 100398c: 00000306 br 100399c <___vfprintf_internal_r+0x430> + 1003990: 843ffc04 addi r16,r16,-16 + 1003994: ad400204 addi r21,r21,8 + 1003998: 9c00130e bge r19,r16,10039e8 <___vfprintf_internal_r+0x47c> + 100399c: 94800404 addi r18,r18,16 + 10039a0: 8c400044 addi r17,r17,1 + 10039a4: af000015 stw fp,0(r21) + 10039a8: acc00115 stw r19,4(r21) + 10039ac: dc800e15 stw r18,56(sp) + 10039b0: dc400d15 stw r17,52(sp) + 10039b4: a47ff60e bge r20,r17,1003990 <___vfprintf_internal_r+0x424> + 10039b8: d9014f17 ldw r4,1340(sp) + 10039bc: b00b883a mov r5,r22 + 10039c0: d9800c04 addi r6,sp,48 + 10039c4: d9c15115 stw r7,1348(sp) + 10039c8: 10035140 call 1003514 <__sprint_r> + 10039cc: d9c15117 ldw r7,1348(sp) + 10039d0: 10009e1e bne r2,zero,1003c4c <___vfprintf_internal_r+0x6e0> + 10039d4: 843ffc04 addi r16,r16,-16 + 10039d8: dc800e17 ldw r18,56(sp) + 10039dc: dc400d17 ldw r17,52(sp) + 10039e0: dd401904 addi r21,sp,100 + 10039e4: 9c3fed16 blt r19,r16,100399c <___vfprintf_internal_r+0x430> + 10039e8: 9425883a add r18,r18,r16 + 10039ec: 8c400044 addi r17,r17,1 + 10039f0: 008001c4 movi r2,7 + 10039f4: af000015 stw fp,0(r21) + 10039f8: ac000115 stw r16,4(r21) + 10039fc: dc800e15 stw r18,56(sp) + 1003a00: dc400d15 stw r17,52(sp) + 1003a04: 1441f516 blt r2,r17,10041dc <___vfprintf_internal_r+0xc70> + 1003a08: ad400204 addi r21,r21,8 + 1003a0c: 00000206 br 1003a18 <___vfprintf_internal_r+0x4ac> + 1003a10: dc800e17 ldw r18,56(sp) + 1003a14: dc400d17 ldw r17,52(sp) + 1003a18: d8800407 ldb r2,16(sp) + 1003a1c: 10000b26 beq r2,zero,1003a4c <___vfprintf_internal_r+0x4e0> + 1003a20: 00800044 movi r2,1 + 1003a24: 94800044 addi r18,r18,1 + 1003a28: 8c400044 addi r17,r17,1 + 1003a2c: a8800115 stw r2,4(r21) + 1003a30: d8c00404 addi r3,sp,16 + 1003a34: 008001c4 movi r2,7 + 1003a38: a8c00015 stw r3,0(r21) + 1003a3c: dc800e15 stw r18,56(sp) + 1003a40: dc400d15 stw r17,52(sp) + 1003a44: 1441da16 blt r2,r17,10041b0 <___vfprintf_internal_r+0xc44> + 1003a48: ad400204 addi r21,r21,8 + 1003a4c: d9015017 ldw r4,1344(sp) + 1003a50: 20000b1e bne r4,zero,1003a80 <___vfprintf_internal_r+0x514> + 1003a54: d8800444 addi r2,sp,17 + 1003a58: 94800084 addi r18,r18,2 + 1003a5c: 8c400044 addi r17,r17,1 + 1003a60: a8800015 stw r2,0(r21) + 1003a64: 00c00084 movi r3,2 + 1003a68: 008001c4 movi r2,7 + 1003a6c: a8c00115 stw r3,4(r21) + 1003a70: dc800e15 stw r18,56(sp) + 1003a74: dc400d15 stw r17,52(sp) + 1003a78: 1441c216 blt r2,r17,1004184 <___vfprintf_internal_r+0xc18> + 1003a7c: ad400204 addi r21,r21,8 + 1003a80: d9414e17 ldw r5,1336(sp) + 1003a84: 00802004 movi r2,128 + 1003a88: 2880b126 beq r5,r2,1003d50 <___vfprintf_internal_r+0x7e4> + 1003a8c: d8c14617 ldw r3,1304(sp) + 1003a90: 19e1c83a sub r16,r3,r7 + 1003a94: 0400260e bge zero,r16,1003b30 <___vfprintf_internal_r+0x5c4> + 1003a98: 00800404 movi r2,16 + 1003a9c: 1403c90e bge r2,r16,10049c4 <___vfprintf_internal_r+0x1458> + 1003aa0: 1027883a mov r19,r2 + 1003aa4: 070040b4 movhi fp,258 + 1003aa8: e7238284 addi fp,fp,-29174 + 1003aac: 050001c4 movi r20,7 + 1003ab0: 00000306 br 1003ac0 <___vfprintf_internal_r+0x554> + 1003ab4: 843ffc04 addi r16,r16,-16 + 1003ab8: ad400204 addi r21,r21,8 + 1003abc: 9c00130e bge r19,r16,1003b0c <___vfprintf_internal_r+0x5a0> + 1003ac0: 94800404 addi r18,r18,16 + 1003ac4: 8c400044 addi r17,r17,1 + 1003ac8: af000015 stw fp,0(r21) + 1003acc: acc00115 stw r19,4(r21) + 1003ad0: dc800e15 stw r18,56(sp) + 1003ad4: dc400d15 stw r17,52(sp) + 1003ad8: a47ff60e bge r20,r17,1003ab4 <___vfprintf_internal_r+0x548> + 1003adc: d9014f17 ldw r4,1340(sp) + 1003ae0: b00b883a mov r5,r22 + 1003ae4: d9800c04 addi r6,sp,48 + 1003ae8: d9c15115 stw r7,1348(sp) + 1003aec: 10035140 call 1003514 <__sprint_r> + 1003af0: d9c15117 ldw r7,1348(sp) + 1003af4: 1000551e bne r2,zero,1003c4c <___vfprintf_internal_r+0x6e0> + 1003af8: 843ffc04 addi r16,r16,-16 + 1003afc: dc800e17 ldw r18,56(sp) + 1003b00: dc400d17 ldw r17,52(sp) + 1003b04: dd401904 addi r21,sp,100 + 1003b08: 9c3fed16 blt r19,r16,1003ac0 <___vfprintf_internal_r+0x554> + 1003b0c: 9425883a add r18,r18,r16 + 1003b10: 8c400044 addi r17,r17,1 + 1003b14: 008001c4 movi r2,7 + 1003b18: af000015 stw fp,0(r21) + 1003b1c: ac000115 stw r16,4(r21) + 1003b20: dc800e15 stw r18,56(sp) + 1003b24: dc400d15 stw r17,52(sp) + 1003b28: 14418216 blt r2,r17,1004134 <___vfprintf_internal_r+0xbc8> + 1003b2c: ad400204 addi r21,r21,8 + 1003b30: d9014c17 ldw r4,1328(sp) + 1003b34: 2080400c andi r2,r4,256 + 1003b38: 10004a1e bne r2,zero,1003c64 <___vfprintf_internal_r+0x6f8> + 1003b3c: d9414117 ldw r5,1284(sp) + 1003b40: 91e5883a add r18,r18,r7 + 1003b44: 8c400044 addi r17,r17,1 + 1003b48: 008001c4 movi r2,7 + 1003b4c: a9400015 stw r5,0(r21) + 1003b50: a9c00115 stw r7,4(r21) + 1003b54: dc800e15 stw r18,56(sp) + 1003b58: dc400d15 stw r17,52(sp) + 1003b5c: 14416716 blt r2,r17,10040fc <___vfprintf_internal_r+0xb90> + 1003b60: a8c00204 addi r3,r21,8 + 1003b64: d9814c17 ldw r6,1328(sp) + 1003b68: 3080010c andi r2,r6,4 + 1003b6c: 10002826 beq r2,zero,1003c10 <___vfprintf_internal_r+0x6a4> + 1003b70: d8814a17 ldw r2,1320(sp) + 1003b74: d9014517 ldw r4,1300(sp) + 1003b78: 1121c83a sub r16,r2,r4 + 1003b7c: 0400240e bge zero,r16,1003c10 <___vfprintf_internal_r+0x6a4> + 1003b80: 00800404 movi r2,16 + 1003b84: 14044f0e bge r2,r16,1004cc4 <___vfprintf_internal_r+0x1758> + 1003b88: dc400d17 ldw r17,52(sp) + 1003b8c: 1027883a mov r19,r2 + 1003b90: 070040b4 movhi fp,258 + 1003b94: e7238684 addi fp,fp,-29158 + 1003b98: 050001c4 movi r20,7 + 1003b9c: 00000306 br 1003bac <___vfprintf_internal_r+0x640> + 1003ba0: 843ffc04 addi r16,r16,-16 + 1003ba4: 18c00204 addi r3,r3,8 + 1003ba8: 9c00110e bge r19,r16,1003bf0 <___vfprintf_internal_r+0x684> + 1003bac: 94800404 addi r18,r18,16 + 1003bb0: 8c400044 addi r17,r17,1 + 1003bb4: 1f000015 stw fp,0(r3) + 1003bb8: 1cc00115 stw r19,4(r3) + 1003bbc: dc800e15 stw r18,56(sp) + 1003bc0: dc400d15 stw r17,52(sp) + 1003bc4: a47ff60e bge r20,r17,1003ba0 <___vfprintf_internal_r+0x634> + 1003bc8: d9014f17 ldw r4,1340(sp) + 1003bcc: b00b883a mov r5,r22 + 1003bd0: d9800c04 addi r6,sp,48 + 1003bd4: 10035140 call 1003514 <__sprint_r> + 1003bd8: 10001c1e bne r2,zero,1003c4c <___vfprintf_internal_r+0x6e0> + 1003bdc: 843ffc04 addi r16,r16,-16 + 1003be0: dc800e17 ldw r18,56(sp) + 1003be4: dc400d17 ldw r17,52(sp) + 1003be8: d8c01904 addi r3,sp,100 + 1003bec: 9c3fef16 blt r19,r16,1003bac <___vfprintf_internal_r+0x640> + 1003bf0: 9425883a add r18,r18,r16 + 1003bf4: 8c400044 addi r17,r17,1 + 1003bf8: 008001c4 movi r2,7 + 1003bfc: 1f000015 stw fp,0(r3) + 1003c00: 1c000115 stw r16,4(r3) + 1003c04: dc800e15 stw r18,56(sp) + 1003c08: dc400d15 stw r17,52(sp) + 1003c0c: 1440cb16 blt r2,r17,1003f3c <___vfprintf_internal_r+0x9d0> + 1003c10: d8814a17 ldw r2,1320(sp) + 1003c14: d9414517 ldw r5,1300(sp) + 1003c18: 1140010e bge r2,r5,1003c20 <___vfprintf_internal_r+0x6b4> + 1003c1c: 2805883a mov r2,r5 + 1003c20: d9814b17 ldw r6,1324(sp) + 1003c24: 308d883a add r6,r6,r2 + 1003c28: d9814b15 stw r6,1324(sp) + 1003c2c: 90013b1e bne r18,zero,100411c <___vfprintf_internal_r+0xbb0> + 1003c30: d9c14017 ldw r7,1280(sp) + 1003c34: dd401904 addi r21,sp,100 + 1003c38: d8000d15 stw zero,52(sp) + 1003c3c: 003ea706 br 10036dc <___vfprintf_internal_r+0x170> + 1003c40: d8800e17 ldw r2,56(sp) + 1003c44: 10053f1e bne r2,zero,1005144 <___vfprintf_internal_r+0x1bd8> + 1003c48: d8000d15 stw zero,52(sp) + 1003c4c: b080030b ldhu r2,12(r22) + 1003c50: 1080100c andi r2,r2,64 + 1003c54: 103e8726 beq r2,zero,1003674 <___vfprintf_internal_r+0x108> + 1003c58: 00bfffc4 movi r2,-1 + 1003c5c: d8814b15 stw r2,1324(sp) + 1003c60: 003e8406 br 1003674 <___vfprintf_internal_r+0x108> + 1003c64: d9814d17 ldw r6,1332(sp) + 1003c68: 00801944 movi r2,101 + 1003c6c: 11806e16 blt r2,r6,1003e28 <___vfprintf_internal_r+0x8bc> + 1003c70: d9414717 ldw r5,1308(sp) + 1003c74: 00c00044 movi r3,1 + 1003c78: 1943430e bge r3,r5,1004988 <___vfprintf_internal_r+0x141c> + 1003c7c: d8814117 ldw r2,1284(sp) + 1003c80: 94800044 addi r18,r18,1 + 1003c84: 8c400044 addi r17,r17,1 + 1003c88: a8800015 stw r2,0(r21) + 1003c8c: 008001c4 movi r2,7 + 1003c90: a8c00115 stw r3,4(r21) + 1003c94: dc800e15 stw r18,56(sp) + 1003c98: dc400d15 stw r17,52(sp) + 1003c9c: 1441ca16 blt r2,r17,10043c8 <___vfprintf_internal_r+0xe5c> + 1003ca0: a8c00204 addi r3,r21,8 + 1003ca4: d9014917 ldw r4,1316(sp) + 1003ca8: 00800044 movi r2,1 + 1003cac: 94800044 addi r18,r18,1 + 1003cb0: 8c400044 addi r17,r17,1 + 1003cb4: 18800115 stw r2,4(r3) + 1003cb8: 008001c4 movi r2,7 + 1003cbc: 19000015 stw r4,0(r3) + 1003cc0: dc800e15 stw r18,56(sp) + 1003cc4: dc400d15 stw r17,52(sp) + 1003cc8: 1441b616 blt r2,r17,10043a4 <___vfprintf_internal_r+0xe38> + 1003ccc: 1cc00204 addi r19,r3,8 + 1003cd0: d9014217 ldw r4,1288(sp) + 1003cd4: d9414317 ldw r5,1292(sp) + 1003cd8: 000d883a mov r6,zero + 1003cdc: 000f883a mov r7,zero + 1003ce0: 100b5740 call 100b574 <__nedf2> + 1003ce4: 10017426 beq r2,zero,10042b8 <___vfprintf_internal_r+0xd4c> + 1003ce8: d9414717 ldw r5,1308(sp) + 1003cec: d9814117 ldw r6,1284(sp) + 1003cf0: 8c400044 addi r17,r17,1 + 1003cf4: 2c85883a add r2,r5,r18 + 1003cf8: 14bfffc4 addi r18,r2,-1 + 1003cfc: 28bfffc4 addi r2,r5,-1 + 1003d00: 30c00044 addi r3,r6,1 + 1003d04: 98800115 stw r2,4(r19) + 1003d08: 008001c4 movi r2,7 + 1003d0c: 98c00015 stw r3,0(r19) + 1003d10: dc800e15 stw r18,56(sp) + 1003d14: dc400d15 stw r17,52(sp) + 1003d18: 14418e16 blt r2,r17,1004354 <___vfprintf_internal_r+0xde8> + 1003d1c: 9cc00204 addi r19,r19,8 + 1003d20: d9414817 ldw r5,1312(sp) + 1003d24: d8800804 addi r2,sp,32 + 1003d28: 8c400044 addi r17,r17,1 + 1003d2c: 9165883a add r18,r18,r5 + 1003d30: 98800015 stw r2,0(r19) + 1003d34: 008001c4 movi r2,7 + 1003d38: 99400115 stw r5,4(r19) + 1003d3c: dc800e15 stw r18,56(sp) + 1003d40: dc400d15 stw r17,52(sp) + 1003d44: 1440ed16 blt r2,r17,10040fc <___vfprintf_internal_r+0xb90> + 1003d48: 98c00204 addi r3,r19,8 + 1003d4c: 003f8506 br 1003b64 <___vfprintf_internal_r+0x5f8> + 1003d50: d9814a17 ldw r6,1320(sp) + 1003d54: d8814517 ldw r2,1300(sp) + 1003d58: 30a1c83a sub r16,r6,r2 + 1003d5c: 043f4b0e bge zero,r16,1003a8c <___vfprintf_internal_r+0x520> + 1003d60: 00800404 movi r2,16 + 1003d64: 1404340e bge r2,r16,1004e38 <___vfprintf_internal_r+0x18cc> + 1003d68: 1027883a mov r19,r2 + 1003d6c: 070040b4 movhi fp,258 + 1003d70: e7238284 addi fp,fp,-29174 + 1003d74: 050001c4 movi r20,7 + 1003d78: 00000306 br 1003d88 <___vfprintf_internal_r+0x81c> + 1003d7c: 843ffc04 addi r16,r16,-16 + 1003d80: ad400204 addi r21,r21,8 + 1003d84: 9c00130e bge r19,r16,1003dd4 <___vfprintf_internal_r+0x868> + 1003d88: 94800404 addi r18,r18,16 + 1003d8c: 8c400044 addi r17,r17,1 + 1003d90: af000015 stw fp,0(r21) + 1003d94: acc00115 stw r19,4(r21) + 1003d98: dc800e15 stw r18,56(sp) + 1003d9c: dc400d15 stw r17,52(sp) + 1003da0: a47ff60e bge r20,r17,1003d7c <___vfprintf_internal_r+0x810> + 1003da4: d9014f17 ldw r4,1340(sp) + 1003da8: b00b883a mov r5,r22 + 1003dac: d9800c04 addi r6,sp,48 + 1003db0: d9c15115 stw r7,1348(sp) + 1003db4: 10035140 call 1003514 <__sprint_r> + 1003db8: d9c15117 ldw r7,1348(sp) + 1003dbc: 103fa31e bne r2,zero,1003c4c <___vfprintf_internal_r+0x6e0> + 1003dc0: 843ffc04 addi r16,r16,-16 + 1003dc4: dc800e17 ldw r18,56(sp) + 1003dc8: dc400d17 ldw r17,52(sp) + 1003dcc: dd401904 addi r21,sp,100 + 1003dd0: 9c3fed16 blt r19,r16,1003d88 <___vfprintf_internal_r+0x81c> + 1003dd4: 9425883a add r18,r18,r16 + 1003dd8: 8c400044 addi r17,r17,1 + 1003ddc: 008001c4 movi r2,7 + 1003de0: af000015 stw fp,0(r21) + 1003de4: ac000115 stw r16,4(r21) + 1003de8: dc800e15 stw r18,56(sp) + 1003dec: dc400d15 stw r17,52(sp) + 1003df0: 14416116 blt r2,r17,1004378 <___vfprintf_internal_r+0xe0c> + 1003df4: ad400204 addi r21,r21,8 + 1003df8: 003f2406 br 1003a8c <___vfprintf_internal_r+0x520> + 1003dfc: d9014f17 ldw r4,1340(sp) + 1003e00: 1006fdc0 call 1006fdc <__sinit> + 1003e04: d9c15117 ldw r7,1348(sp) + 1003e08: 003def06 br 10035c8 <___vfprintf_internal_r+0x5c> + 1003e0c: d9014f17 ldw r4,1340(sp) + 1003e10: b00b883a mov r5,r22 + 1003e14: d9c15115 stw r7,1348(sp) + 1003e18: 100543c0 call 100543c <__swsetup_r> + 1003e1c: d9c15117 ldw r7,1348(sp) + 1003e20: 103dee26 beq r2,zero,10035dc <___vfprintf_internal_r+0x70> + 1003e24: 003f8c06 br 1003c58 <___vfprintf_internal_r+0x6ec> + 1003e28: d9014217 ldw r4,1288(sp) + 1003e2c: d9414317 ldw r5,1292(sp) + 1003e30: 000d883a mov r6,zero + 1003e34: 000f883a mov r7,zero + 1003e38: 100b4ec0 call 100b4ec <__eqdf2> + 1003e3c: 1000f21e bne r2,zero,1004208 <___vfprintf_internal_r+0xc9c> + 1003e40: 008040b4 movhi r2,258 + 1003e44: 10a38204 addi r2,r2,-29176 + 1003e48: 94800044 addi r18,r18,1 + 1003e4c: 8c400044 addi r17,r17,1 + 1003e50: a8800015 stw r2,0(r21) + 1003e54: 00c00044 movi r3,1 + 1003e58: 008001c4 movi r2,7 + 1003e5c: a8c00115 stw r3,4(r21) + 1003e60: dc800e15 stw r18,56(sp) + 1003e64: dc400d15 stw r17,52(sp) + 1003e68: 1442fa16 blt r2,r17,1004a54 <___vfprintf_internal_r+0x14e8> + 1003e6c: a8c00204 addi r3,r21,8 + 1003e70: d8800517 ldw r2,20(sp) + 1003e74: d9014717 ldw r4,1308(sp) + 1003e78: 11015c0e bge r2,r4,10043ec <___vfprintf_internal_r+0xe80> + 1003e7c: dc400d17 ldw r17,52(sp) + 1003e80: d9814917 ldw r6,1316(sp) + 1003e84: 00800044 movi r2,1 + 1003e88: 94800044 addi r18,r18,1 + 1003e8c: 8c400044 addi r17,r17,1 + 1003e90: 18800115 stw r2,4(r3) + 1003e94: 008001c4 movi r2,7 + 1003e98: 19800015 stw r6,0(r3) + 1003e9c: dc800e15 stw r18,56(sp) + 1003ea0: dc400d15 stw r17,52(sp) + 1003ea4: 14431016 blt r2,r17,1004ae8 <___vfprintf_internal_r+0x157c> + 1003ea8: 18c00204 addi r3,r3,8 + 1003eac: d8814717 ldw r2,1308(sp) + 1003eb0: 143fffc4 addi r16,r2,-1 + 1003eb4: 043f2b0e bge zero,r16,1003b64 <___vfprintf_internal_r+0x5f8> + 1003eb8: 00800404 movi r2,16 + 1003ebc: 1402a20e bge r2,r16,1004948 <___vfprintf_internal_r+0x13dc> + 1003ec0: dc400d17 ldw r17,52(sp) + 1003ec4: 1027883a mov r19,r2 + 1003ec8: 070040b4 movhi fp,258 + 1003ecc: e7238284 addi fp,fp,-29174 + 1003ed0: 050001c4 movi r20,7 + 1003ed4: 00000306 br 1003ee4 <___vfprintf_internal_r+0x978> + 1003ed8: 18c00204 addi r3,r3,8 + 1003edc: 843ffc04 addi r16,r16,-16 + 1003ee0: 9c029c0e bge r19,r16,1004954 <___vfprintf_internal_r+0x13e8> + 1003ee4: 94800404 addi r18,r18,16 + 1003ee8: 8c400044 addi r17,r17,1 + 1003eec: 1f000015 stw fp,0(r3) + 1003ef0: 1cc00115 stw r19,4(r3) + 1003ef4: dc800e15 stw r18,56(sp) + 1003ef8: dc400d15 stw r17,52(sp) + 1003efc: a47ff60e bge r20,r17,1003ed8 <___vfprintf_internal_r+0x96c> + 1003f00: d9014f17 ldw r4,1340(sp) + 1003f04: b00b883a mov r5,r22 + 1003f08: d9800c04 addi r6,sp,48 + 1003f0c: 10035140 call 1003514 <__sprint_r> + 1003f10: 103f4e1e bne r2,zero,1003c4c <___vfprintf_internal_r+0x6e0> + 1003f14: dc800e17 ldw r18,56(sp) + 1003f18: dc400d17 ldw r17,52(sp) + 1003f1c: d8c01904 addi r3,sp,100 + 1003f20: 003fee06 br 1003edc <___vfprintf_internal_r+0x970> + 1003f24: d8802c0b ldhu r2,176(sp) + 1003f28: 00ffffc4 movi r3,-1 + 1003f2c: d8c14b15 stw r3,1324(sp) + 1003f30: 1080100c andi r2,r2,64 + 1003f34: 103dcc1e bne r2,zero,1003668 <___vfprintf_internal_r+0xfc> + 1003f38: 003dce06 br 1003674 <___vfprintf_internal_r+0x108> + 1003f3c: d9014f17 ldw r4,1340(sp) + 1003f40: b00b883a mov r5,r22 + 1003f44: d9800c04 addi r6,sp,48 + 1003f48: 10035140 call 1003514 <__sprint_r> + 1003f4c: 103f3f1e bne r2,zero,1003c4c <___vfprintf_internal_r+0x6e0> + 1003f50: dc800e17 ldw r18,56(sp) + 1003f54: 003f2e06 br 1003c10 <___vfprintf_internal_r+0x6a4> + 1003f58: d9414c17 ldw r5,1328(sp) + 1003f5c: 29400414 ori r5,r5,16 + 1003f60: d9414c15 stw r5,1328(sp) + 1003f64: d9814c17 ldw r6,1328(sp) + 1003f68: 3080080c andi r2,r6,32 + 1003f6c: 10014f1e bne r2,zero,10044ac <___vfprintf_internal_r+0xf40> + 1003f70: d8c14c17 ldw r3,1328(sp) + 1003f74: 1880040c andi r2,r3,16 + 1003f78: 1002ea1e bne r2,zero,1004b24 <___vfprintf_internal_r+0x15b8> + 1003f7c: d9014c17 ldw r4,1328(sp) + 1003f80: 2080100c andi r2,r4,64 + 1003f84: 1002e726 beq r2,zero,1004b24 <___vfprintf_internal_r+0x15b8> + 1003f88: 3880000f ldh r2,0(r7) + 1003f8c: 39c00104 addi r7,r7,4 + 1003f90: d9c14015 stw r7,1280(sp) + 1003f94: 1023d7fa srai r17,r2,31 + 1003f98: 1021883a mov r16,r2 + 1003f9c: 88037216 blt r17,zero,1004d68 <___vfprintf_internal_r+0x17fc> + 1003fa0: 01000044 movi r4,1 + 1003fa4: 98000416 blt r19,zero,1003fb8 <___vfprintf_internal_r+0xa4c> + 1003fa8: d8c14c17 ldw r3,1328(sp) + 1003fac: 00bfdfc4 movi r2,-129 + 1003fb0: 1886703a and r3,r3,r2 + 1003fb4: d8c14c15 stw r3,1328(sp) + 1003fb8: 8444b03a or r2,r16,r17 + 1003fbc: 1002261e bne r2,zero,1004858 <___vfprintf_internal_r+0x12ec> + 1003fc0: 9802251e bne r19,zero,1004858 <___vfprintf_internal_r+0x12ec> + 1003fc4: 20803fcc andi r2,r4,255 + 1003fc8: 10029b26 beq r2,zero,1004a38 <___vfprintf_internal_r+0x14cc> + 1003fcc: d8c01904 addi r3,sp,100 + 1003fd0: dd000f04 addi r20,sp,60 + 1003fd4: d8c14115 stw r3,1284(sp) + 1003fd8: d8c14117 ldw r3,1284(sp) + 1003fdc: dcc14515 stw r19,1300(sp) + 1003fe0: a0c5c83a sub r2,r20,r3 + 1003fe4: 11c00a04 addi r7,r2,40 + 1003fe8: 99c0010e bge r19,r7,1003ff0 <___vfprintf_internal_r+0xa84> + 1003fec: d9c14515 stw r7,1300(sp) + 1003ff0: dcc14615 stw r19,1304(sp) + 1003ff4: d8800407 ldb r2,16(sp) + 1003ff8: 103e4c26 beq r2,zero,100392c <___vfprintf_internal_r+0x3c0> + 1003ffc: d8814517 ldw r2,1300(sp) + 1004000: 10800044 addi r2,r2,1 + 1004004: d8814515 stw r2,1300(sp) + 1004008: 003e4806 br 100392c <___vfprintf_internal_r+0x3c0> + 100400c: d9814c17 ldw r6,1328(sp) + 1004010: 31800414 ori r6,r6,16 + 1004014: d9814c15 stw r6,1328(sp) + 1004018: d8c14c17 ldw r3,1328(sp) + 100401c: 1880080c andi r2,r3,32 + 1004020: 1001271e bne r2,zero,10044c0 <___vfprintf_internal_r+0xf54> + 1004024: d9414c17 ldw r5,1328(sp) + 1004028: 2880040c andi r2,r5,16 + 100402c: 1002b61e bne r2,zero,1004b08 <___vfprintf_internal_r+0x159c> + 1004030: d9814c17 ldw r6,1328(sp) + 1004034: 3080100c andi r2,r6,64 + 1004038: 1002b326 beq r2,zero,1004b08 <___vfprintf_internal_r+0x159c> + 100403c: 3c00000b ldhu r16,0(r7) + 1004040: 0009883a mov r4,zero + 1004044: 39c00104 addi r7,r7,4 + 1004048: 0023883a mov r17,zero + 100404c: d9c14015 stw r7,1280(sp) + 1004050: d8000405 stb zero,16(sp) + 1004054: 003fd306 br 1003fa4 <___vfprintf_internal_r+0xa38> + 1004058: d9014c17 ldw r4,1328(sp) + 100405c: 21000414 ori r4,r4,16 + 1004060: d9014c15 stw r4,1328(sp) + 1004064: d9414c17 ldw r5,1328(sp) + 1004068: 2880080c andi r2,r5,32 + 100406c: 1001081e bne r2,zero,1004490 <___vfprintf_internal_r+0xf24> + 1004070: d8c14c17 ldw r3,1328(sp) + 1004074: 1880040c andi r2,r3,16 + 1004078: 1002b01e bne r2,zero,1004b3c <___vfprintf_internal_r+0x15d0> + 100407c: d9014c17 ldw r4,1328(sp) + 1004080: 2080100c andi r2,r4,64 + 1004084: 1002ad26 beq r2,zero,1004b3c <___vfprintf_internal_r+0x15d0> + 1004088: 3c00000b ldhu r16,0(r7) + 100408c: 01000044 movi r4,1 + 1004090: 39c00104 addi r7,r7,4 + 1004094: 0023883a mov r17,zero + 1004098: d9c14015 stw r7,1280(sp) + 100409c: d8000405 stb zero,16(sp) + 10040a0: 003fc006 br 1003fa4 <___vfprintf_internal_r+0xa38> + 10040a4: d9014f17 ldw r4,1340(sp) + 10040a8: b00b883a mov r5,r22 + 10040ac: d9800c04 addi r6,sp,48 + 10040b0: 10035140 call 1003514 <__sprint_r> + 10040b4: 103ee51e bne r2,zero,1003c4c <___vfprintf_internal_r+0x6e0> + 10040b8: dc800e17 ldw r18,56(sp) + 10040bc: d8c01904 addi r3,sp,100 + 10040c0: d9814c17 ldw r6,1328(sp) + 10040c4: 3080004c andi r2,r6,1 + 10040c8: 1005003a cmpeq r2,r2,zero + 10040cc: 103ea51e bne r2,zero,1003b64 <___vfprintf_internal_r+0x5f8> + 10040d0: 00800044 movi r2,1 + 10040d4: dc400d17 ldw r17,52(sp) + 10040d8: 18800115 stw r2,4(r3) + 10040dc: d8814917 ldw r2,1316(sp) + 10040e0: 94800044 addi r18,r18,1 + 10040e4: 8c400044 addi r17,r17,1 + 10040e8: 18800015 stw r2,0(r3) + 10040ec: 008001c4 movi r2,7 + 10040f0: dc800e15 stw r18,56(sp) + 10040f4: dc400d15 stw r17,52(sp) + 10040f8: 14421e0e bge r2,r17,1004974 <___vfprintf_internal_r+0x1408> + 10040fc: d9014f17 ldw r4,1340(sp) + 1004100: b00b883a mov r5,r22 + 1004104: d9800c04 addi r6,sp,48 + 1004108: 10035140 call 1003514 <__sprint_r> + 100410c: 103ecf1e bne r2,zero,1003c4c <___vfprintf_internal_r+0x6e0> + 1004110: dc800e17 ldw r18,56(sp) + 1004114: d8c01904 addi r3,sp,100 + 1004118: 003e9206 br 1003b64 <___vfprintf_internal_r+0x5f8> + 100411c: d9014f17 ldw r4,1340(sp) + 1004120: b00b883a mov r5,r22 + 1004124: d9800c04 addi r6,sp,48 + 1004128: 10035140 call 1003514 <__sprint_r> + 100412c: 103ec026 beq r2,zero,1003c30 <___vfprintf_internal_r+0x6c4> + 1004130: 003ec606 br 1003c4c <___vfprintf_internal_r+0x6e0> + 1004134: d9014f17 ldw r4,1340(sp) + 1004138: b00b883a mov r5,r22 + 100413c: d9800c04 addi r6,sp,48 + 1004140: d9c15115 stw r7,1348(sp) + 1004144: 10035140 call 1003514 <__sprint_r> + 1004148: d9c15117 ldw r7,1348(sp) + 100414c: 103ebf1e bne r2,zero,1003c4c <___vfprintf_internal_r+0x6e0> + 1004150: dc800e17 ldw r18,56(sp) + 1004154: dc400d17 ldw r17,52(sp) + 1004158: dd401904 addi r21,sp,100 + 100415c: 003e7406 br 1003b30 <___vfprintf_internal_r+0x5c4> + 1004160: d9014f17 ldw r4,1340(sp) + 1004164: b00b883a mov r5,r22 + 1004168: d9800c04 addi r6,sp,48 + 100416c: d9c15115 stw r7,1348(sp) + 1004170: 10035140 call 1003514 <__sprint_r> + 1004174: d9c15117 ldw r7,1348(sp) + 1004178: 103eb41e bne r2,zero,1003c4c <___vfprintf_internal_r+0x6e0> + 100417c: dd401904 addi r21,sp,100 + 1004180: 003d6d06 br 1003738 <___vfprintf_internal_r+0x1cc> + 1004184: d9014f17 ldw r4,1340(sp) + 1004188: b00b883a mov r5,r22 + 100418c: d9800c04 addi r6,sp,48 + 1004190: d9c15115 stw r7,1348(sp) + 1004194: 10035140 call 1003514 <__sprint_r> + 1004198: d9c15117 ldw r7,1348(sp) + 100419c: 103eab1e bne r2,zero,1003c4c <___vfprintf_internal_r+0x6e0> + 10041a0: dc800e17 ldw r18,56(sp) + 10041a4: dc400d17 ldw r17,52(sp) + 10041a8: dd401904 addi r21,sp,100 + 10041ac: 003e3406 br 1003a80 <___vfprintf_internal_r+0x514> + 10041b0: d9014f17 ldw r4,1340(sp) + 10041b4: b00b883a mov r5,r22 + 10041b8: d9800c04 addi r6,sp,48 + 10041bc: d9c15115 stw r7,1348(sp) + 10041c0: 10035140 call 1003514 <__sprint_r> + 10041c4: d9c15117 ldw r7,1348(sp) + 10041c8: 103ea01e bne r2,zero,1003c4c <___vfprintf_internal_r+0x6e0> + 10041cc: dc800e17 ldw r18,56(sp) + 10041d0: dc400d17 ldw r17,52(sp) + 10041d4: dd401904 addi r21,sp,100 + 10041d8: 003e1c06 br 1003a4c <___vfprintf_internal_r+0x4e0> + 10041dc: d9014f17 ldw r4,1340(sp) + 10041e0: b00b883a mov r5,r22 + 10041e4: d9800c04 addi r6,sp,48 + 10041e8: d9c15115 stw r7,1348(sp) + 10041ec: 10035140 call 1003514 <__sprint_r> + 10041f0: d9c15117 ldw r7,1348(sp) + 10041f4: 103e951e bne r2,zero,1003c4c <___vfprintf_internal_r+0x6e0> + 10041f8: dc800e17 ldw r18,56(sp) + 10041fc: dc400d17 ldw r17,52(sp) + 1004200: dd401904 addi r21,sp,100 + 1004204: 003e0406 br 1003a18 <___vfprintf_internal_r+0x4ac> + 1004208: d9000517 ldw r4,20(sp) + 100420c: 0102520e bge zero,r4,1004b58 <___vfprintf_internal_r+0x15ec> + 1004210: d9814717 ldw r6,1308(sp) + 1004214: 21807a16 blt r4,r6,1004400 <___vfprintf_internal_r+0xe94> + 1004218: d8814117 ldw r2,1284(sp) + 100421c: 91a5883a add r18,r18,r6 + 1004220: 8c400044 addi r17,r17,1 + 1004224: a8800015 stw r2,0(r21) + 1004228: 008001c4 movi r2,7 + 100422c: a9800115 stw r6,4(r21) + 1004230: dc800e15 stw r18,56(sp) + 1004234: dc400d15 stw r17,52(sp) + 1004238: 1442f616 blt r2,r17,1004e14 <___vfprintf_internal_r+0x18a8> + 100423c: a8c00204 addi r3,r21,8 + 1004240: d9414717 ldw r5,1308(sp) + 1004244: 2161c83a sub r16,r4,r5 + 1004248: 043f9d0e bge zero,r16,10040c0 <___vfprintf_internal_r+0xb54> + 100424c: 00800404 movi r2,16 + 1004250: 1402130e bge r2,r16,1004aa0 <___vfprintf_internal_r+0x1534> + 1004254: dc400d17 ldw r17,52(sp) + 1004258: 1027883a mov r19,r2 + 100425c: 070040b4 movhi fp,258 + 1004260: e7238284 addi fp,fp,-29174 + 1004264: 050001c4 movi r20,7 + 1004268: 00000306 br 1004278 <___vfprintf_internal_r+0xd0c> + 100426c: 18c00204 addi r3,r3,8 + 1004270: 843ffc04 addi r16,r16,-16 + 1004274: 9c020d0e bge r19,r16,1004aac <___vfprintf_internal_r+0x1540> + 1004278: 94800404 addi r18,r18,16 + 100427c: 8c400044 addi r17,r17,1 + 1004280: 1f000015 stw fp,0(r3) + 1004284: 1cc00115 stw r19,4(r3) + 1004288: dc800e15 stw r18,56(sp) + 100428c: dc400d15 stw r17,52(sp) + 1004290: a47ff60e bge r20,r17,100426c <___vfprintf_internal_r+0xd00> + 1004294: d9014f17 ldw r4,1340(sp) + 1004298: b00b883a mov r5,r22 + 100429c: d9800c04 addi r6,sp,48 + 10042a0: 10035140 call 1003514 <__sprint_r> + 10042a4: 103e691e bne r2,zero,1003c4c <___vfprintf_internal_r+0x6e0> + 10042a8: dc800e17 ldw r18,56(sp) + 10042ac: dc400d17 ldw r17,52(sp) + 10042b0: d8c01904 addi r3,sp,100 + 10042b4: 003fee06 br 1004270 <___vfprintf_internal_r+0xd04> + 10042b8: d8814717 ldw r2,1308(sp) + 10042bc: 143fffc4 addi r16,r2,-1 + 10042c0: 043e970e bge zero,r16,1003d20 <___vfprintf_internal_r+0x7b4> + 10042c4: 00800404 movi r2,16 + 10042c8: 1400180e bge r2,r16,100432c <___vfprintf_internal_r+0xdc0> + 10042cc: 1029883a mov r20,r2 + 10042d0: 070040b4 movhi fp,258 + 10042d4: e7238284 addi fp,fp,-29174 + 10042d8: 054001c4 movi r21,7 + 10042dc: 00000306 br 10042ec <___vfprintf_internal_r+0xd80> + 10042e0: 9cc00204 addi r19,r19,8 + 10042e4: 843ffc04 addi r16,r16,-16 + 10042e8: a400120e bge r20,r16,1004334 <___vfprintf_internal_r+0xdc8> + 10042ec: 94800404 addi r18,r18,16 + 10042f0: 8c400044 addi r17,r17,1 + 10042f4: 9f000015 stw fp,0(r19) + 10042f8: 9d000115 stw r20,4(r19) + 10042fc: dc800e15 stw r18,56(sp) + 1004300: dc400d15 stw r17,52(sp) + 1004304: ac7ff60e bge r21,r17,10042e0 <___vfprintf_internal_r+0xd74> + 1004308: d9014f17 ldw r4,1340(sp) + 100430c: b00b883a mov r5,r22 + 1004310: d9800c04 addi r6,sp,48 + 1004314: 10035140 call 1003514 <__sprint_r> + 1004318: 103e4c1e bne r2,zero,1003c4c <___vfprintf_internal_r+0x6e0> + 100431c: dc800e17 ldw r18,56(sp) + 1004320: dc400d17 ldw r17,52(sp) + 1004324: dcc01904 addi r19,sp,100 + 1004328: 003fee06 br 10042e4 <___vfprintf_internal_r+0xd78> + 100432c: 070040b4 movhi fp,258 + 1004330: e7238284 addi fp,fp,-29174 + 1004334: 9425883a add r18,r18,r16 + 1004338: 8c400044 addi r17,r17,1 + 100433c: 008001c4 movi r2,7 + 1004340: 9f000015 stw fp,0(r19) + 1004344: 9c000115 stw r16,4(r19) + 1004348: dc800e15 stw r18,56(sp) + 100434c: dc400d15 stw r17,52(sp) + 1004350: 147e720e bge r2,r17,1003d1c <___vfprintf_internal_r+0x7b0> + 1004354: d9014f17 ldw r4,1340(sp) + 1004358: b00b883a mov r5,r22 + 100435c: d9800c04 addi r6,sp,48 + 1004360: 10035140 call 1003514 <__sprint_r> + 1004364: 103e391e bne r2,zero,1003c4c <___vfprintf_internal_r+0x6e0> + 1004368: dc800e17 ldw r18,56(sp) + 100436c: dc400d17 ldw r17,52(sp) + 1004370: dcc01904 addi r19,sp,100 + 1004374: 003e6a06 br 1003d20 <___vfprintf_internal_r+0x7b4> + 1004378: d9014f17 ldw r4,1340(sp) + 100437c: b00b883a mov r5,r22 + 1004380: d9800c04 addi r6,sp,48 + 1004384: d9c15115 stw r7,1348(sp) + 1004388: 10035140 call 1003514 <__sprint_r> + 100438c: d9c15117 ldw r7,1348(sp) + 1004390: 103e2e1e bne r2,zero,1003c4c <___vfprintf_internal_r+0x6e0> + 1004394: dc800e17 ldw r18,56(sp) + 1004398: dc400d17 ldw r17,52(sp) + 100439c: dd401904 addi r21,sp,100 + 10043a0: 003dba06 br 1003a8c <___vfprintf_internal_r+0x520> + 10043a4: d9014f17 ldw r4,1340(sp) + 10043a8: b00b883a mov r5,r22 + 10043ac: d9800c04 addi r6,sp,48 + 10043b0: 10035140 call 1003514 <__sprint_r> + 10043b4: 103e251e bne r2,zero,1003c4c <___vfprintf_internal_r+0x6e0> + 10043b8: dc800e17 ldw r18,56(sp) + 10043bc: dc400d17 ldw r17,52(sp) + 10043c0: dcc01904 addi r19,sp,100 + 10043c4: 003e4206 br 1003cd0 <___vfprintf_internal_r+0x764> + 10043c8: d9014f17 ldw r4,1340(sp) + 10043cc: b00b883a mov r5,r22 + 10043d0: d9800c04 addi r6,sp,48 + 10043d4: 10035140 call 1003514 <__sprint_r> + 10043d8: 103e1c1e bne r2,zero,1003c4c <___vfprintf_internal_r+0x6e0> + 10043dc: dc800e17 ldw r18,56(sp) + 10043e0: dc400d17 ldw r17,52(sp) + 10043e4: d8c01904 addi r3,sp,100 + 10043e8: 003e2e06 br 1003ca4 <___vfprintf_internal_r+0x738> + 10043ec: d9414c17 ldw r5,1328(sp) + 10043f0: 2880004c andi r2,r5,1 + 10043f4: 1005003a cmpeq r2,r2,zero + 10043f8: 103dda1e bne r2,zero,1003b64 <___vfprintf_internal_r+0x5f8> + 10043fc: 003e9f06 br 1003e7c <___vfprintf_internal_r+0x910> + 1004400: d8c14117 ldw r3,1284(sp) + 1004404: 9125883a add r18,r18,r4 + 1004408: 8c400044 addi r17,r17,1 + 100440c: 008001c4 movi r2,7 + 1004410: a8c00015 stw r3,0(r21) + 1004414: a9000115 stw r4,4(r21) + 1004418: dc800e15 stw r18,56(sp) + 100441c: dc400d15 stw r17,52(sp) + 1004420: 14426616 blt r2,r17,1004dbc <___vfprintf_internal_r+0x1850> + 1004424: a8c00204 addi r3,r21,8 + 1004428: d9414917 ldw r5,1316(sp) + 100442c: 00800044 movi r2,1 + 1004430: 94800044 addi r18,r18,1 + 1004434: 8c400044 addi r17,r17,1 + 1004438: 18800115 stw r2,4(r3) + 100443c: 008001c4 movi r2,7 + 1004440: 19400015 stw r5,0(r3) + 1004444: dc800e15 stw r18,56(sp) + 1004448: dc400d15 stw r17,52(sp) + 100444c: 2021883a mov r16,r4 + 1004450: 14425016 blt r2,r17,1004d94 <___vfprintf_internal_r+0x1828> + 1004454: 19400204 addi r5,r3,8 + 1004458: d9814717 ldw r6,1308(sp) + 100445c: 8c400044 addi r17,r17,1 + 1004460: dc400d15 stw r17,52(sp) + 1004464: 3107c83a sub r3,r6,r4 + 1004468: d9014117 ldw r4,1284(sp) + 100446c: 90e5883a add r18,r18,r3 + 1004470: 28c00115 stw r3,4(r5) + 1004474: 8105883a add r2,r16,r4 + 1004478: 28800015 stw r2,0(r5) + 100447c: 008001c4 movi r2,7 + 1004480: dc800e15 stw r18,56(sp) + 1004484: 147f1d16 blt r2,r17,10040fc <___vfprintf_internal_r+0xb90> + 1004488: 28c00204 addi r3,r5,8 + 100448c: 003db506 br 1003b64 <___vfprintf_internal_r+0x5f8> + 1004490: 3c000017 ldw r16,0(r7) + 1004494: 3c400117 ldw r17,4(r7) + 1004498: 39800204 addi r6,r7,8 + 100449c: 01000044 movi r4,1 + 10044a0: d9814015 stw r6,1280(sp) + 10044a4: d8000405 stb zero,16(sp) + 10044a8: 003ebe06 br 1003fa4 <___vfprintf_internal_r+0xa38> + 10044ac: 3c000017 ldw r16,0(r7) + 10044b0: 3c400117 ldw r17,4(r7) + 10044b4: 38800204 addi r2,r7,8 + 10044b8: d8814015 stw r2,1280(sp) + 10044bc: 003eb706 br 1003f9c <___vfprintf_internal_r+0xa30> + 10044c0: 3c000017 ldw r16,0(r7) + 10044c4: 3c400117 ldw r17,4(r7) + 10044c8: 39000204 addi r4,r7,8 + 10044cc: d9014015 stw r4,1280(sp) + 10044d0: 0009883a mov r4,zero + 10044d4: d8000405 stb zero,16(sp) + 10044d8: 003eb206 br 1003fa4 <___vfprintf_internal_r+0xa38> + 10044dc: 38c00017 ldw r3,0(r7) + 10044e0: 39c00104 addi r7,r7,4 + 10044e4: d8c14a15 stw r3,1320(sp) + 10044e8: 1800d10e bge r3,zero,1004830 <___vfprintf_internal_r+0x12c4> + 10044ec: 00c7c83a sub r3,zero,r3 + 10044f0: d8c14a15 stw r3,1320(sp) + 10044f4: d9014c17 ldw r4,1328(sp) + 10044f8: b8c00007 ldb r3,0(r23) + 10044fc: 21000114 ori r4,r4,4 + 1004500: d9014c15 stw r4,1328(sp) + 1004504: 003c9806 br 1003768 <___vfprintf_internal_r+0x1fc> + 1004508: d9814c17 ldw r6,1328(sp) + 100450c: 3080080c andi r2,r6,32 + 1004510: 1001f026 beq r2,zero,1004cd4 <___vfprintf_internal_r+0x1768> + 1004514: d9014b17 ldw r4,1324(sp) + 1004518: 38800017 ldw r2,0(r7) + 100451c: 39c00104 addi r7,r7,4 + 1004520: d9c14015 stw r7,1280(sp) + 1004524: 2007d7fa srai r3,r4,31 + 1004528: d9c14017 ldw r7,1280(sp) + 100452c: 11000015 stw r4,0(r2) + 1004530: 10c00115 stw r3,4(r2) + 1004534: 003c6906 br 10036dc <___vfprintf_internal_r+0x170> + 1004538: b8c00007 ldb r3,0(r23) + 100453c: 00801b04 movi r2,108 + 1004540: 18824f26 beq r3,r2,1004e80 <___vfprintf_internal_r+0x1914> + 1004544: d9414c17 ldw r5,1328(sp) + 1004548: 29400414 ori r5,r5,16 + 100454c: d9414c15 stw r5,1328(sp) + 1004550: 003c8506 br 1003768 <___vfprintf_internal_r+0x1fc> + 1004554: d9814c17 ldw r6,1328(sp) + 1004558: b8c00007 ldb r3,0(r23) + 100455c: 31800814 ori r6,r6,32 + 1004560: d9814c15 stw r6,1328(sp) + 1004564: 003c8006 br 1003768 <___vfprintf_internal_r+0x1fc> + 1004568: d8814c17 ldw r2,1328(sp) + 100456c: 3c000017 ldw r16,0(r7) + 1004570: 00c01e04 movi r3,120 + 1004574: 10800094 ori r2,r2,2 + 1004578: d8814c15 stw r2,1328(sp) + 100457c: 39c00104 addi r7,r7,4 + 1004580: 014040b4 movhi r5,258 + 1004584: 29636b04 addi r5,r5,-29268 + 1004588: 00800c04 movi r2,48 + 100458c: 0023883a mov r17,zero + 1004590: 01000084 movi r4,2 + 1004594: d9c14015 stw r7,1280(sp) + 1004598: d8c14d15 stw r3,1332(sp) + 100459c: d9414415 stw r5,1296(sp) + 10045a0: d8800445 stb r2,17(sp) + 10045a4: d8c00485 stb r3,18(sp) + 10045a8: d8000405 stb zero,16(sp) + 10045ac: 003e7d06 br 1003fa4 <___vfprintf_internal_r+0xa38> + 10045b0: d8814c17 ldw r2,1328(sp) + 10045b4: b8c00007 ldb r3,0(r23) + 10045b8: 10801014 ori r2,r2,64 + 10045bc: d8814c15 stw r2,1328(sp) + 10045c0: 003c6906 br 1003768 <___vfprintf_internal_r+0x1fc> + 10045c4: d9414c17 ldw r5,1328(sp) + 10045c8: 2880020c andi r2,r5,8 + 10045cc: 1001df26 beq r2,zero,1004d4c <___vfprintf_internal_r+0x17e0> + 10045d0: 39800017 ldw r6,0(r7) + 10045d4: 38800204 addi r2,r7,8 + 10045d8: d8814015 stw r2,1280(sp) + 10045dc: d9814215 stw r6,1288(sp) + 10045e0: 39c00117 ldw r7,4(r7) + 10045e4: d9c14315 stw r7,1292(sp) + 10045e8: d9014217 ldw r4,1288(sp) + 10045ec: d9414317 ldw r5,1292(sp) + 10045f0: 10097340 call 1009734 <__isinfd> + 10045f4: 10021726 beq r2,zero,1004e54 <___vfprintf_internal_r+0x18e8> + 10045f8: d9014217 ldw r4,1288(sp) + 10045fc: d9414317 ldw r5,1292(sp) + 1004600: 000d883a mov r6,zero + 1004604: 000f883a mov r7,zero + 1004608: 100b70c0 call 100b70c <__ltdf2> + 100460c: 1002ca16 blt r2,zero,1005138 <___vfprintf_internal_r+0x1bcc> + 1004610: d9414d17 ldw r5,1332(sp) + 1004614: 008011c4 movi r2,71 + 1004618: 11420a16 blt r2,r5,1004e44 <___vfprintf_internal_r+0x18d8> + 100461c: 018040b4 movhi r6,258 + 1004620: 31a37004 addi r6,r6,-29248 + 1004624: d9814115 stw r6,1284(sp) + 1004628: d9014c17 ldw r4,1328(sp) + 100462c: 00c000c4 movi r3,3 + 1004630: 00bfdfc4 movi r2,-129 + 1004634: 2088703a and r4,r4,r2 + 1004638: 180f883a mov r7,r3 + 100463c: d8c14515 stw r3,1300(sp) + 1004640: d9014c15 stw r4,1328(sp) + 1004644: d8014615 stw zero,1304(sp) + 1004648: 003e6a06 br 1003ff4 <___vfprintf_internal_r+0xa88> + 100464c: 38800017 ldw r2,0(r7) + 1004650: 00c00044 movi r3,1 + 1004654: 39c00104 addi r7,r7,4 + 1004658: d9c14015 stw r7,1280(sp) + 100465c: d9000f04 addi r4,sp,60 + 1004660: 180f883a mov r7,r3 + 1004664: d8c14515 stw r3,1300(sp) + 1004668: d9014115 stw r4,1284(sp) + 100466c: d8800f05 stb r2,60(sp) + 1004670: d8000405 stb zero,16(sp) + 1004674: 003cac06 br 1003928 <___vfprintf_internal_r+0x3bc> + 1004678: 014040b4 movhi r5,258 + 100467c: 29637604 addi r5,r5,-29224 + 1004680: d9414415 stw r5,1296(sp) + 1004684: d9814c17 ldw r6,1328(sp) + 1004688: 3080080c andi r2,r6,32 + 100468c: 1000f926 beq r2,zero,1004a74 <___vfprintf_internal_r+0x1508> + 1004690: 3c000017 ldw r16,0(r7) + 1004694: 3c400117 ldw r17,4(r7) + 1004698: 38800204 addi r2,r7,8 + 100469c: d8814015 stw r2,1280(sp) + 10046a0: d9414c17 ldw r5,1328(sp) + 10046a4: 2880004c andi r2,r5,1 + 10046a8: 1005003a cmpeq r2,r2,zero + 10046ac: 1000b31e bne r2,zero,100497c <___vfprintf_internal_r+0x1410> + 10046b0: 8444b03a or r2,r16,r17 + 10046b4: 1000b126 beq r2,zero,100497c <___vfprintf_internal_r+0x1410> + 10046b8: d9814d17 ldw r6,1332(sp) + 10046bc: 29400094 ori r5,r5,2 + 10046c0: 00800c04 movi r2,48 + 10046c4: 01000084 movi r4,2 + 10046c8: d9414c15 stw r5,1328(sp) + 10046cc: d8800445 stb r2,17(sp) + 10046d0: d9800485 stb r6,18(sp) + 10046d4: d8000405 stb zero,16(sp) + 10046d8: 003e3206 br 1003fa4 <___vfprintf_internal_r+0xa38> + 10046dc: 018040b4 movhi r6,258 + 10046e0: 31a36b04 addi r6,r6,-29268 + 10046e4: d9814415 stw r6,1296(sp) + 10046e8: 003fe606 br 1004684 <___vfprintf_internal_r+0x1118> + 10046ec: 00800ac4 movi r2,43 + 10046f0: d8800405 stb r2,16(sp) + 10046f4: b8c00007 ldb r3,0(r23) + 10046f8: 003c1b06 br 1003768 <___vfprintf_internal_r+0x1fc> + 10046fc: d8814c17 ldw r2,1328(sp) + 1004700: b8c00007 ldb r3,0(r23) + 1004704: 10800054 ori r2,r2,1 + 1004708: d8814c15 stw r2,1328(sp) + 100470c: 003c1606 br 1003768 <___vfprintf_internal_r+0x1fc> + 1004710: d8800407 ldb r2,16(sp) + 1004714: 1000461e bne r2,zero,1004830 <___vfprintf_internal_r+0x12c4> + 1004718: 00800804 movi r2,32 + 100471c: d8800405 stb r2,16(sp) + 1004720: b8c00007 ldb r3,0(r23) + 1004724: 003c1006 br 1003768 <___vfprintf_internal_r+0x1fc> + 1004728: d9814c17 ldw r6,1328(sp) + 100472c: b8c00007 ldb r3,0(r23) + 1004730: 31800214 ori r6,r6,8 + 1004734: d9814c15 stw r6,1328(sp) + 1004738: 003c0b06 br 1003768 <___vfprintf_internal_r+0x1fc> + 100473c: 0007883a mov r3,zero + 1004740: 01000244 movi r4,9 + 1004744: 188002a4 muli r2,r3,10 + 1004748: b8c00007 ldb r3,0(r23) + 100474c: d9814d17 ldw r6,1332(sp) + 1004750: bdc00044 addi r23,r23,1 + 1004754: d8c14d15 stw r3,1332(sp) + 1004758: d9414d17 ldw r5,1332(sp) + 100475c: 3085883a add r2,r6,r2 + 1004760: 10fff404 addi r3,r2,-48 + 1004764: 28bff404 addi r2,r5,-48 + 1004768: 20bff62e bgeu r4,r2,1004744 <___vfprintf_internal_r+0x11d8> + 100476c: d8c14a15 stw r3,1320(sp) + 1004770: 003bff06 br 1003770 <___vfprintf_internal_r+0x204> + 1004774: d9414c17 ldw r5,1328(sp) + 1004778: b8c00007 ldb r3,0(r23) + 100477c: 29402014 ori r5,r5,128 + 1004780: d9414c15 stw r5,1328(sp) + 1004784: 003bf806 br 1003768 <___vfprintf_internal_r+0x1fc> + 1004788: b8c00007 ldb r3,0(r23) + 100478c: 00800a84 movi r2,42 + 1004790: bdc00044 addi r23,r23,1 + 1004794: 18831526 beq r3,r2,10053ec <___vfprintf_internal_r+0x1e80> + 1004798: d8c14d15 stw r3,1332(sp) + 100479c: 18bff404 addi r2,r3,-48 + 10047a0: 00c00244 movi r3,9 + 10047a4: 18827836 bltu r3,r2,1005188 <___vfprintf_internal_r+0x1c1c> + 10047a8: 000d883a mov r6,zero + 10047ac: 308002a4 muli r2,r6,10 + 10047b0: b9800007 ldb r6,0(r23) + 10047b4: d9414d17 ldw r5,1332(sp) + 10047b8: bdc00044 addi r23,r23,1 + 10047bc: d9814d15 stw r6,1332(sp) + 10047c0: d9014d17 ldw r4,1332(sp) + 10047c4: 1145883a add r2,r2,r5 + 10047c8: 11bff404 addi r6,r2,-48 + 10047cc: 20bff404 addi r2,r4,-48 + 10047d0: 18bff62e bgeu r3,r2,10047ac <___vfprintf_internal_r+0x1240> + 10047d4: 3027883a mov r19,r6 + 10047d8: 303be50e bge r6,zero,1003770 <___vfprintf_internal_r+0x204> + 10047dc: 04ffffc4 movi r19,-1 + 10047e0: 003be306 br 1003770 <___vfprintf_internal_r+0x204> + 10047e4: d8000405 stb zero,16(sp) + 10047e8: 39800017 ldw r6,0(r7) + 10047ec: 39c00104 addi r7,r7,4 + 10047f0: d9c14015 stw r7,1280(sp) + 10047f4: d9814115 stw r6,1284(sp) + 10047f8: 3001c926 beq r6,zero,1004f20 <___vfprintf_internal_r+0x19b4> + 10047fc: 98000e16 blt r19,zero,1004838 <___vfprintf_internal_r+0x12cc> + 1004800: d9014117 ldw r4,1284(sp) + 1004804: 000b883a mov r5,zero + 1004808: 980d883a mov r6,r19 + 100480c: 1007ee80 call 1007ee8 + 1004810: 10025926 beq r2,zero,1005178 <___vfprintf_internal_r+0x1c0c> + 1004814: d8c14117 ldw r3,1284(sp) + 1004818: 10cfc83a sub r7,r2,r3 + 100481c: 99c19e16 blt r19,r7,1004e98 <___vfprintf_internal_r+0x192c> + 1004820: d9c14515 stw r7,1300(sp) + 1004824: 38000916 blt r7,zero,100484c <___vfprintf_internal_r+0x12e0> + 1004828: d8014615 stw zero,1304(sp) + 100482c: 003df106 br 1003ff4 <___vfprintf_internal_r+0xa88> + 1004830: b8c00007 ldb r3,0(r23) + 1004834: 003bcc06 br 1003768 <___vfprintf_internal_r+0x1fc> + 1004838: d9014117 ldw r4,1284(sp) + 100483c: 10034a00 call 10034a0 + 1004840: d8814515 stw r2,1300(sp) + 1004844: 100f883a mov r7,r2 + 1004848: 103ff70e bge r2,zero,1004828 <___vfprintf_internal_r+0x12bc> + 100484c: d8014515 stw zero,1300(sp) + 1004850: d8014615 stw zero,1304(sp) + 1004854: 003de706 br 1003ff4 <___vfprintf_internal_r+0xa88> + 1004858: 20c03fcc andi r3,r4,255 + 100485c: 00800044 movi r2,1 + 1004860: 18802d26 beq r3,r2,1004918 <___vfprintf_internal_r+0x13ac> + 1004864: 18800e36 bltu r3,r2,10048a0 <___vfprintf_internal_r+0x1334> + 1004868: 00800084 movi r2,2 + 100486c: 1880fa26 beq r3,r2,1004c58 <___vfprintf_internal_r+0x16ec> + 1004870: 010040b4 movhi r4,258 + 1004874: 21237b04 addi r4,r4,-29204 + 1004878: 10034a00 call 10034a0 + 100487c: 100f883a mov r7,r2 + 1004880: dcc14515 stw r19,1300(sp) + 1004884: 9880010e bge r19,r2,100488c <___vfprintf_internal_r+0x1320> + 1004888: d8814515 stw r2,1300(sp) + 100488c: 008040b4 movhi r2,258 + 1004890: 10a37b04 addi r2,r2,-29204 + 1004894: dcc14615 stw r19,1304(sp) + 1004898: d8814115 stw r2,1284(sp) + 100489c: 003dd506 br 1003ff4 <___vfprintf_internal_r+0xa88> + 10048a0: d9401904 addi r5,sp,100 + 10048a4: dd000f04 addi r20,sp,60 + 10048a8: d9414115 stw r5,1284(sp) + 10048ac: 880a977a slli r5,r17,29 + 10048b0: d9814117 ldw r6,1284(sp) + 10048b4: 8004d0fa srli r2,r16,3 + 10048b8: 8806d0fa srli r3,r17,3 + 10048bc: 810001cc andi r4,r16,7 + 10048c0: 2884b03a or r2,r5,r2 + 10048c4: 31bfffc4 addi r6,r6,-1 + 10048c8: 21000c04 addi r4,r4,48 + 10048cc: d9814115 stw r6,1284(sp) + 10048d0: 10cab03a or r5,r2,r3 + 10048d4: 31000005 stb r4,0(r6) + 10048d8: 1021883a mov r16,r2 + 10048dc: 1823883a mov r17,r3 + 10048e0: 283ff21e bne r5,zero,10048ac <___vfprintf_internal_r+0x1340> + 10048e4: d8c14c17 ldw r3,1328(sp) + 10048e8: 1880004c andi r2,r3,1 + 10048ec: 1005003a cmpeq r2,r2,zero + 10048f0: 103db91e bne r2,zero,1003fd8 <___vfprintf_internal_r+0xa6c> + 10048f4: 20803fcc andi r2,r4,255 + 10048f8: 1080201c xori r2,r2,128 + 10048fc: 10bfe004 addi r2,r2,-128 + 1004900: 00c00c04 movi r3,48 + 1004904: 10fdb426 beq r2,r3,1003fd8 <___vfprintf_internal_r+0xa6c> + 1004908: 31bfffc4 addi r6,r6,-1 + 100490c: d9814115 stw r6,1284(sp) + 1004910: 30c00005 stb r3,0(r6) + 1004914: 003db006 br 1003fd8 <___vfprintf_internal_r+0xa6c> + 1004918: 88800068 cmpgeui r2,r17,1 + 100491c: 10002c1e bne r2,zero,10049d0 <___vfprintf_internal_r+0x1464> + 1004920: 8800021e bne r17,zero,100492c <___vfprintf_internal_r+0x13c0> + 1004924: 00800244 movi r2,9 + 1004928: 14002936 bltu r2,r16,10049d0 <___vfprintf_internal_r+0x1464> + 100492c: d90018c4 addi r4,sp,99 + 1004930: dd000f04 addi r20,sp,60 + 1004934: d9014115 stw r4,1284(sp) + 1004938: d9014117 ldw r4,1284(sp) + 100493c: 80800c04 addi r2,r16,48 + 1004940: 20800005 stb r2,0(r4) + 1004944: 003da406 br 1003fd8 <___vfprintf_internal_r+0xa6c> + 1004948: dc400d17 ldw r17,52(sp) + 100494c: 070040b4 movhi fp,258 + 1004950: e7238284 addi fp,fp,-29174 + 1004954: 9425883a add r18,r18,r16 + 1004958: 8c400044 addi r17,r17,1 + 100495c: 008001c4 movi r2,7 + 1004960: 1f000015 stw fp,0(r3) + 1004964: 1c000115 stw r16,4(r3) + 1004968: dc800e15 stw r18,56(sp) + 100496c: dc400d15 stw r17,52(sp) + 1004970: 147de216 blt r2,r17,10040fc <___vfprintf_internal_r+0xb90> + 1004974: 18c00204 addi r3,r3,8 + 1004978: 003c7a06 br 1003b64 <___vfprintf_internal_r+0x5f8> + 100497c: 01000084 movi r4,2 + 1004980: d8000405 stb zero,16(sp) + 1004984: 003d8706 br 1003fa4 <___vfprintf_internal_r+0xa38> + 1004988: d9814c17 ldw r6,1328(sp) + 100498c: 30c4703a and r2,r6,r3 + 1004990: 1005003a cmpeq r2,r2,zero + 1004994: 103cb926 beq r2,zero,1003c7c <___vfprintf_internal_r+0x710> + 1004998: d9014117 ldw r4,1284(sp) + 100499c: 94800044 addi r18,r18,1 + 10049a0: 8c400044 addi r17,r17,1 + 10049a4: 008001c4 movi r2,7 + 10049a8: a9000015 stw r4,0(r21) + 10049ac: a8c00115 stw r3,4(r21) + 10049b0: dc800e15 stw r18,56(sp) + 10049b4: dc400d15 stw r17,52(sp) + 10049b8: 147e6616 blt r2,r17,1004354 <___vfprintf_internal_r+0xde8> + 10049bc: acc00204 addi r19,r21,8 + 10049c0: 003cd706 br 1003d20 <___vfprintf_internal_r+0x7b4> + 10049c4: 070040b4 movhi fp,258 + 10049c8: e7238284 addi fp,fp,-29174 + 10049cc: 003c4f06 br 1003b0c <___vfprintf_internal_r+0x5a0> + 10049d0: dd000f04 addi r20,sp,60 + 10049d4: dc801904 addi r18,sp,100 + 10049d8: 8009883a mov r4,r16 + 10049dc: 880b883a mov r5,r17 + 10049e0: 01800284 movi r6,10 + 10049e4: 000f883a mov r7,zero + 10049e8: 100a41c0 call 100a41c <__umoddi3> + 10049ec: 12000c04 addi r8,r2,48 + 10049f0: 94bfffc4 addi r18,r18,-1 + 10049f4: 8009883a mov r4,r16 + 10049f8: 880b883a mov r5,r17 + 10049fc: 01800284 movi r6,10 + 1004a00: 000f883a mov r7,zero + 1004a04: 92000005 stb r8,0(r18) + 1004a08: 1009e400 call 1009e40 <__udivdi3> + 1004a0c: 1009883a mov r4,r2 + 1004a10: 1021883a mov r16,r2 + 1004a14: 18800068 cmpgeui r2,r3,1 + 1004a18: 1823883a mov r17,r3 + 1004a1c: 103fee1e bne r2,zero,10049d8 <___vfprintf_internal_r+0x146c> + 1004a20: 1800021e bne r3,zero,1004a2c <___vfprintf_internal_r+0x14c0> + 1004a24: 00800244 movi r2,9 + 1004a28: 113feb36 bltu r2,r4,10049d8 <___vfprintf_internal_r+0x146c> + 1004a2c: 94bfffc4 addi r18,r18,-1 + 1004a30: dc814115 stw r18,1284(sp) + 1004a34: 003fc006 br 1004938 <___vfprintf_internal_r+0x13cc> + 1004a38: d9014c17 ldw r4,1328(sp) + 1004a3c: 2080004c andi r2,r4,1 + 1004a40: 10009a1e bne r2,zero,1004cac <___vfprintf_internal_r+0x1740> + 1004a44: d9401904 addi r5,sp,100 + 1004a48: dd000f04 addi r20,sp,60 + 1004a4c: d9414115 stw r5,1284(sp) + 1004a50: 003d6106 br 1003fd8 <___vfprintf_internal_r+0xa6c> + 1004a54: d9014f17 ldw r4,1340(sp) + 1004a58: b00b883a mov r5,r22 + 1004a5c: d9800c04 addi r6,sp,48 + 1004a60: 10035140 call 1003514 <__sprint_r> + 1004a64: 103c791e bne r2,zero,1003c4c <___vfprintf_internal_r+0x6e0> + 1004a68: dc800e17 ldw r18,56(sp) + 1004a6c: d8c01904 addi r3,sp,100 + 1004a70: 003cff06 br 1003e70 <___vfprintf_internal_r+0x904> + 1004a74: d8c14c17 ldw r3,1328(sp) + 1004a78: 1880040c andi r2,r3,16 + 1004a7c: 1000711e bne r2,zero,1004c44 <___vfprintf_internal_r+0x16d8> + 1004a80: d9014c17 ldw r4,1328(sp) + 1004a84: 2080100c andi r2,r4,64 + 1004a88: 10006e26 beq r2,zero,1004c44 <___vfprintf_internal_r+0x16d8> + 1004a8c: 3c00000b ldhu r16,0(r7) + 1004a90: 0023883a mov r17,zero + 1004a94: 39c00104 addi r7,r7,4 + 1004a98: d9c14015 stw r7,1280(sp) + 1004a9c: 003f0006 br 10046a0 <___vfprintf_internal_r+0x1134> + 1004aa0: dc400d17 ldw r17,52(sp) + 1004aa4: 070040b4 movhi fp,258 + 1004aa8: e7238284 addi fp,fp,-29174 + 1004aac: 9425883a add r18,r18,r16 + 1004ab0: 8c400044 addi r17,r17,1 + 1004ab4: 008001c4 movi r2,7 + 1004ab8: 1f000015 stw fp,0(r3) + 1004abc: 1c000115 stw r16,4(r3) + 1004ac0: dc800e15 stw r18,56(sp) + 1004ac4: dc400d15 stw r17,52(sp) + 1004ac8: 147d7616 blt r2,r17,10040a4 <___vfprintf_internal_r+0xb38> + 1004acc: 18c00204 addi r3,r3,8 + 1004ad0: 003d7b06 br 10040c0 <___vfprintf_internal_r+0xb54> + 1004ad4: dc800e17 ldw r18,56(sp) + 1004ad8: dc400d17 ldw r17,52(sp) + 1004adc: 070040b4 movhi fp,258 + 1004ae0: e7238684 addi fp,fp,-29158 + 1004ae4: 003bc006 br 10039e8 <___vfprintf_internal_r+0x47c> + 1004ae8: d9014f17 ldw r4,1340(sp) + 1004aec: b00b883a mov r5,r22 + 1004af0: d9800c04 addi r6,sp,48 + 1004af4: 10035140 call 1003514 <__sprint_r> + 1004af8: 103c541e bne r2,zero,1003c4c <___vfprintf_internal_r+0x6e0> + 1004afc: dc800e17 ldw r18,56(sp) + 1004b00: d8c01904 addi r3,sp,100 + 1004b04: 003ce906 br 1003eac <___vfprintf_internal_r+0x940> + 1004b08: 3c000017 ldw r16,0(r7) + 1004b0c: 0009883a mov r4,zero + 1004b10: 39c00104 addi r7,r7,4 + 1004b14: 0023883a mov r17,zero + 1004b18: d9c14015 stw r7,1280(sp) + 1004b1c: d8000405 stb zero,16(sp) + 1004b20: 003d2006 br 1003fa4 <___vfprintf_internal_r+0xa38> + 1004b24: 38800017 ldw r2,0(r7) + 1004b28: 39c00104 addi r7,r7,4 + 1004b2c: d9c14015 stw r7,1280(sp) + 1004b30: 1023d7fa srai r17,r2,31 + 1004b34: 1021883a mov r16,r2 + 1004b38: 003d1806 br 1003f9c <___vfprintf_internal_r+0xa30> + 1004b3c: 3c000017 ldw r16,0(r7) + 1004b40: 01000044 movi r4,1 + 1004b44: 39c00104 addi r7,r7,4 + 1004b48: 0023883a mov r17,zero + 1004b4c: d9c14015 stw r7,1280(sp) + 1004b50: d8000405 stb zero,16(sp) + 1004b54: 003d1306 br 1003fa4 <___vfprintf_internal_r+0xa38> + 1004b58: 008040b4 movhi r2,258 + 1004b5c: 10a38204 addi r2,r2,-29176 + 1004b60: 94800044 addi r18,r18,1 + 1004b64: 8c400044 addi r17,r17,1 + 1004b68: a8800015 stw r2,0(r21) + 1004b6c: 00c00044 movi r3,1 + 1004b70: 008001c4 movi r2,7 + 1004b74: a8c00115 stw r3,4(r21) + 1004b78: dc800e15 stw r18,56(sp) + 1004b7c: dc400d15 stw r17,52(sp) + 1004b80: 1440ca16 blt r2,r17,1004eac <___vfprintf_internal_r+0x1940> + 1004b84: a8c00204 addi r3,r21,8 + 1004b88: 2000061e bne r4,zero,1004ba4 <___vfprintf_internal_r+0x1638> + 1004b8c: d9414717 ldw r5,1308(sp) + 1004b90: 2800041e bne r5,zero,1004ba4 <___vfprintf_internal_r+0x1638> + 1004b94: d9814c17 ldw r6,1328(sp) + 1004b98: 3080004c andi r2,r6,1 + 1004b9c: 1005003a cmpeq r2,r2,zero + 1004ba0: 103bf01e bne r2,zero,1003b64 <___vfprintf_internal_r+0x5f8> + 1004ba4: 00800044 movi r2,1 + 1004ba8: dc400d17 ldw r17,52(sp) + 1004bac: 18800115 stw r2,4(r3) + 1004bb0: d8814917 ldw r2,1316(sp) + 1004bb4: 94800044 addi r18,r18,1 + 1004bb8: 8c400044 addi r17,r17,1 + 1004bbc: 18800015 stw r2,0(r3) + 1004bc0: 008001c4 movi r2,7 + 1004bc4: dc800e15 stw r18,56(sp) + 1004bc8: dc400d15 stw r17,52(sp) + 1004bcc: 1440ca16 blt r2,r17,1004ef8 <___vfprintf_internal_r+0x198c> + 1004bd0: 18c00204 addi r3,r3,8 + 1004bd4: 0121c83a sub r16,zero,r4 + 1004bd8: 0400500e bge zero,r16,1004d1c <___vfprintf_internal_r+0x17b0> + 1004bdc: 00800404 movi r2,16 + 1004be0: 1400800e bge r2,r16,1004de4 <___vfprintf_internal_r+0x1878> + 1004be4: 1027883a mov r19,r2 + 1004be8: 070040b4 movhi fp,258 + 1004bec: e7238284 addi fp,fp,-29174 + 1004bf0: 050001c4 movi r20,7 + 1004bf4: 00000306 br 1004c04 <___vfprintf_internal_r+0x1698> + 1004bf8: 18c00204 addi r3,r3,8 + 1004bfc: 843ffc04 addi r16,r16,-16 + 1004c00: 9c007a0e bge r19,r16,1004dec <___vfprintf_internal_r+0x1880> + 1004c04: 94800404 addi r18,r18,16 + 1004c08: 8c400044 addi r17,r17,1 + 1004c0c: 1f000015 stw fp,0(r3) + 1004c10: 1cc00115 stw r19,4(r3) + 1004c14: dc800e15 stw r18,56(sp) + 1004c18: dc400d15 stw r17,52(sp) + 1004c1c: a47ff60e bge r20,r17,1004bf8 <___vfprintf_internal_r+0x168c> + 1004c20: d9014f17 ldw r4,1340(sp) + 1004c24: b00b883a mov r5,r22 + 1004c28: d9800c04 addi r6,sp,48 + 1004c2c: 10035140 call 1003514 <__sprint_r> + 1004c30: 103c061e bne r2,zero,1003c4c <___vfprintf_internal_r+0x6e0> + 1004c34: dc800e17 ldw r18,56(sp) + 1004c38: dc400d17 ldw r17,52(sp) + 1004c3c: d8c01904 addi r3,sp,100 + 1004c40: 003fee06 br 1004bfc <___vfprintf_internal_r+0x1690> + 1004c44: 3c000017 ldw r16,0(r7) + 1004c48: 0023883a mov r17,zero + 1004c4c: 39c00104 addi r7,r7,4 + 1004c50: d9c14015 stw r7,1280(sp) + 1004c54: 003e9206 br 10046a0 <___vfprintf_internal_r+0x1134> + 1004c58: d9401904 addi r5,sp,100 + 1004c5c: dd000f04 addi r20,sp,60 + 1004c60: d9414115 stw r5,1284(sp) + 1004c64: d9814417 ldw r6,1296(sp) + 1004c68: 880a973a slli r5,r17,28 + 1004c6c: 8004d13a srli r2,r16,4 + 1004c70: 810003cc andi r4,r16,15 + 1004c74: 3109883a add r4,r6,r4 + 1004c78: 2884b03a or r2,r5,r2 + 1004c7c: 21400003 ldbu r5,0(r4) + 1004c80: d9014117 ldw r4,1284(sp) + 1004c84: 8806d13a srli r3,r17,4 + 1004c88: 1021883a mov r16,r2 + 1004c8c: 213fffc4 addi r4,r4,-1 + 1004c90: d9014115 stw r4,1284(sp) + 1004c94: d9814117 ldw r6,1284(sp) + 1004c98: 10c8b03a or r4,r2,r3 + 1004c9c: 1823883a mov r17,r3 + 1004ca0: 31400005 stb r5,0(r6) + 1004ca4: 203fef1e bne r4,zero,1004c64 <___vfprintf_internal_r+0x16f8> + 1004ca8: 003ccb06 br 1003fd8 <___vfprintf_internal_r+0xa6c> + 1004cac: 00800c04 movi r2,48 + 1004cb0: d98018c4 addi r6,sp,99 + 1004cb4: dd000f04 addi r20,sp,60 + 1004cb8: d88018c5 stb r2,99(sp) + 1004cbc: d9814115 stw r6,1284(sp) + 1004cc0: 003cc506 br 1003fd8 <___vfprintf_internal_r+0xa6c> + 1004cc4: dc400d17 ldw r17,52(sp) + 1004cc8: 070040b4 movhi fp,258 + 1004ccc: e7238684 addi fp,fp,-29158 + 1004cd0: 003bc706 br 1003bf0 <___vfprintf_internal_r+0x684> + 1004cd4: d9414c17 ldw r5,1328(sp) + 1004cd8: 2880040c andi r2,r5,16 + 1004cdc: 10007c26 beq r2,zero,1004ed0 <___vfprintf_internal_r+0x1964> + 1004ce0: 38800017 ldw r2,0(r7) + 1004ce4: 39c00104 addi r7,r7,4 + 1004ce8: d9c14015 stw r7,1280(sp) + 1004cec: d9814b17 ldw r6,1324(sp) + 1004cf0: d9c14017 ldw r7,1280(sp) + 1004cf4: 11800015 stw r6,0(r2) + 1004cf8: 003a7806 br 10036dc <___vfprintf_internal_r+0x170> + 1004cfc: d9014f17 ldw r4,1340(sp) + 1004d00: b00b883a mov r5,r22 + 1004d04: d9800c04 addi r6,sp,48 + 1004d08: 10035140 call 1003514 <__sprint_r> + 1004d0c: 103bcf1e bne r2,zero,1003c4c <___vfprintf_internal_r+0x6e0> + 1004d10: dc800e17 ldw r18,56(sp) + 1004d14: dc400d17 ldw r17,52(sp) + 1004d18: d8c01904 addi r3,sp,100 + 1004d1c: d9014717 ldw r4,1308(sp) + 1004d20: d9414117 ldw r5,1284(sp) + 1004d24: 8c400044 addi r17,r17,1 + 1004d28: 9125883a add r18,r18,r4 + 1004d2c: 008001c4 movi r2,7 + 1004d30: 19400015 stw r5,0(r3) + 1004d34: 19000115 stw r4,4(r3) + 1004d38: dc800e15 stw r18,56(sp) + 1004d3c: dc400d15 stw r17,52(sp) + 1004d40: 147cee16 blt r2,r17,10040fc <___vfprintf_internal_r+0xb90> + 1004d44: 18c00204 addi r3,r3,8 + 1004d48: 003b8606 br 1003b64 <___vfprintf_internal_r+0x5f8> + 1004d4c: 38c00017 ldw r3,0(r7) + 1004d50: 39000204 addi r4,r7,8 + 1004d54: d9014015 stw r4,1280(sp) + 1004d58: d8c14215 stw r3,1288(sp) + 1004d5c: 39c00117 ldw r7,4(r7) + 1004d60: d9c14315 stw r7,1292(sp) + 1004d64: 003e2006 br 10045e8 <___vfprintf_internal_r+0x107c> + 1004d68: 0005883a mov r2,zero + 1004d6c: 1409c83a sub r4,r2,r16 + 1004d70: 1105803a cmpltu r2,r2,r4 + 1004d74: 044bc83a sub r5,zero,r17 + 1004d78: 2885c83a sub r2,r5,r2 + 1004d7c: 2021883a mov r16,r4 + 1004d80: 1023883a mov r17,r2 + 1004d84: 01000044 movi r4,1 + 1004d88: 00800b44 movi r2,45 + 1004d8c: d8800405 stb r2,16(sp) + 1004d90: 003c8406 br 1003fa4 <___vfprintf_internal_r+0xa38> + 1004d94: d9014f17 ldw r4,1340(sp) + 1004d98: b00b883a mov r5,r22 + 1004d9c: d9800c04 addi r6,sp,48 + 1004da0: 10035140 call 1003514 <__sprint_r> + 1004da4: 103ba91e bne r2,zero,1003c4c <___vfprintf_internal_r+0x6e0> + 1004da8: dc800e17 ldw r18,56(sp) + 1004dac: dc400d17 ldw r17,52(sp) + 1004db0: d9000517 ldw r4,20(sp) + 1004db4: d9401904 addi r5,sp,100 + 1004db8: 003da706 br 1004458 <___vfprintf_internal_r+0xeec> + 1004dbc: d9014f17 ldw r4,1340(sp) + 1004dc0: b00b883a mov r5,r22 + 1004dc4: d9800c04 addi r6,sp,48 + 1004dc8: 10035140 call 1003514 <__sprint_r> + 1004dcc: 103b9f1e bne r2,zero,1003c4c <___vfprintf_internal_r+0x6e0> + 1004dd0: dc800e17 ldw r18,56(sp) + 1004dd4: dc400d17 ldw r17,52(sp) + 1004dd8: d9000517 ldw r4,20(sp) + 1004ddc: d8c01904 addi r3,sp,100 + 1004de0: 003d9106 br 1004428 <___vfprintf_internal_r+0xebc> + 1004de4: 070040b4 movhi fp,258 + 1004de8: e7238284 addi fp,fp,-29174 + 1004dec: 9425883a add r18,r18,r16 + 1004df0: 8c400044 addi r17,r17,1 + 1004df4: 008001c4 movi r2,7 + 1004df8: 1f000015 stw fp,0(r3) + 1004dfc: 1c000115 stw r16,4(r3) + 1004e00: dc800e15 stw r18,56(sp) + 1004e04: dc400d15 stw r17,52(sp) + 1004e08: 147fbc16 blt r2,r17,1004cfc <___vfprintf_internal_r+0x1790> + 1004e0c: 18c00204 addi r3,r3,8 + 1004e10: 003fc206 br 1004d1c <___vfprintf_internal_r+0x17b0> + 1004e14: d9014f17 ldw r4,1340(sp) + 1004e18: b00b883a mov r5,r22 + 1004e1c: d9800c04 addi r6,sp,48 + 1004e20: 10035140 call 1003514 <__sprint_r> + 1004e24: 103b891e bne r2,zero,1003c4c <___vfprintf_internal_r+0x6e0> + 1004e28: dc800e17 ldw r18,56(sp) + 1004e2c: d9000517 ldw r4,20(sp) + 1004e30: d8c01904 addi r3,sp,100 + 1004e34: 003d0206 br 1004240 <___vfprintf_internal_r+0xcd4> + 1004e38: 070040b4 movhi fp,258 + 1004e3c: e7238284 addi fp,fp,-29174 + 1004e40: 003be406 br 1003dd4 <___vfprintf_internal_r+0x868> + 1004e44: 008040b4 movhi r2,258 + 1004e48: 10a37104 addi r2,r2,-29244 + 1004e4c: d8814115 stw r2,1284(sp) + 1004e50: 003df506 br 1004628 <___vfprintf_internal_r+0x10bc> + 1004e54: d9014217 ldw r4,1288(sp) + 1004e58: d9414317 ldw r5,1292(sp) + 1004e5c: 10097740 call 1009774 <__isnand> + 1004e60: 10003926 beq r2,zero,1004f48 <___vfprintf_internal_r+0x19dc> + 1004e64: d9414d17 ldw r5,1332(sp) + 1004e68: 008011c4 movi r2,71 + 1004e6c: 1140ce16 blt r2,r5,10051a8 <___vfprintf_internal_r+0x1c3c> + 1004e70: 018040b4 movhi r6,258 + 1004e74: 31a37204 addi r6,r6,-29240 + 1004e78: d9814115 stw r6,1284(sp) + 1004e7c: 003dea06 br 1004628 <___vfprintf_internal_r+0x10bc> + 1004e80: d9014c17 ldw r4,1328(sp) + 1004e84: bdc00044 addi r23,r23,1 + 1004e88: b8c00007 ldb r3,0(r23) + 1004e8c: 21000814 ori r4,r4,32 + 1004e90: d9014c15 stw r4,1328(sp) + 1004e94: 003a3406 br 1003768 <___vfprintf_internal_r+0x1fc> + 1004e98: dcc14515 stw r19,1300(sp) + 1004e9c: 98011016 blt r19,zero,10052e0 <___vfprintf_internal_r+0x1d74> + 1004ea0: 980f883a mov r7,r19 + 1004ea4: d8014615 stw zero,1304(sp) + 1004ea8: 003c5206 br 1003ff4 <___vfprintf_internal_r+0xa88> + 1004eac: d9014f17 ldw r4,1340(sp) + 1004eb0: b00b883a mov r5,r22 + 1004eb4: d9800c04 addi r6,sp,48 + 1004eb8: 10035140 call 1003514 <__sprint_r> + 1004ebc: 103b631e bne r2,zero,1003c4c <___vfprintf_internal_r+0x6e0> + 1004ec0: dc800e17 ldw r18,56(sp) + 1004ec4: d9000517 ldw r4,20(sp) + 1004ec8: d8c01904 addi r3,sp,100 + 1004ecc: 003f2e06 br 1004b88 <___vfprintf_internal_r+0x161c> + 1004ed0: d8c14c17 ldw r3,1328(sp) + 1004ed4: 1880100c andi r2,r3,64 + 1004ed8: 1000a026 beq r2,zero,100515c <___vfprintf_internal_r+0x1bf0> + 1004edc: 38800017 ldw r2,0(r7) + 1004ee0: 39c00104 addi r7,r7,4 + 1004ee4: d9c14015 stw r7,1280(sp) + 1004ee8: d9014b17 ldw r4,1324(sp) + 1004eec: d9c14017 ldw r7,1280(sp) + 1004ef0: 1100000d sth r4,0(r2) + 1004ef4: 0039f906 br 10036dc <___vfprintf_internal_r+0x170> + 1004ef8: d9014f17 ldw r4,1340(sp) + 1004efc: b00b883a mov r5,r22 + 1004f00: d9800c04 addi r6,sp,48 + 1004f04: 10035140 call 1003514 <__sprint_r> + 1004f08: 103b501e bne r2,zero,1003c4c <___vfprintf_internal_r+0x6e0> + 1004f0c: dc800e17 ldw r18,56(sp) + 1004f10: dc400d17 ldw r17,52(sp) + 1004f14: d9000517 ldw r4,20(sp) + 1004f18: d8c01904 addi r3,sp,100 + 1004f1c: 003f2d06 br 1004bd4 <___vfprintf_internal_r+0x1668> + 1004f20: 00800184 movi r2,6 + 1004f24: 14c09a36 bltu r2,r19,1005190 <___vfprintf_internal_r+0x1c24> + 1004f28: dcc14515 stw r19,1300(sp) + 1004f2c: 9800010e bge r19,zero,1004f34 <___vfprintf_internal_r+0x19c8> + 1004f30: d8014515 stw zero,1300(sp) + 1004f34: 008040b4 movhi r2,258 + 1004f38: 10a37404 addi r2,r2,-29232 + 1004f3c: 980f883a mov r7,r19 + 1004f40: d8814115 stw r2,1284(sp) + 1004f44: 003a7806 br 1003928 <___vfprintf_internal_r+0x3bc> + 1004f48: 00bfffc4 movi r2,-1 + 1004f4c: 9880e226 beq r19,r2,10052d8 <___vfprintf_internal_r+0x1d6c> + 1004f50: d9414d17 ldw r5,1332(sp) + 1004f54: 008019c4 movi r2,103 + 1004f58: 2880dc26 beq r5,r2,10052cc <___vfprintf_internal_r+0x1d60> + 1004f5c: 008011c4 movi r2,71 + 1004f60: 2880da26 beq r5,r2,10052cc <___vfprintf_internal_r+0x1d60> + 1004f64: d9414c17 ldw r5,1328(sp) + 1004f68: d9014317 ldw r4,1292(sp) + 1004f6c: d9814217 ldw r6,1288(sp) + 1004f70: 29404014 ori r5,r5,256 + 1004f74: d9414c15 stw r5,1328(sp) + 1004f78: 2000cc16 blt r4,zero,10052ac <___vfprintf_internal_r+0x1d40> + 1004f7c: 3021883a mov r16,r6 + 1004f80: 2023883a mov r17,r4 + 1004f84: 0039883a mov fp,zero + 1004f88: d9414d17 ldw r5,1332(sp) + 1004f8c: 00801984 movi r2,102 + 1004f90: 2880b726 beq r5,r2,1005270 <___vfprintf_internal_r+0x1d04> + 1004f94: 00801184 movi r2,70 + 1004f98: 2880b526 beq r5,r2,1005270 <___vfprintf_internal_r+0x1d04> + 1004f9c: 00801944 movi r2,101 + 1004fa0: 2880c826 beq r5,r2,10052c4 <___vfprintf_internal_r+0x1d58> + 1004fa4: 00801144 movi r2,69 + 1004fa8: 2880c626 beq r5,r2,10052c4 <___vfprintf_internal_r+0x1d58> + 1004fac: 9829883a mov r20,r19 + 1004fb0: d9014f17 ldw r4,1340(sp) + 1004fb4: d8800504 addi r2,sp,20 + 1004fb8: 880d883a mov r6,r17 + 1004fbc: d8800115 stw r2,4(sp) + 1004fc0: d8c00604 addi r3,sp,24 + 1004fc4: d8800704 addi r2,sp,28 + 1004fc8: 800b883a mov r5,r16 + 1004fcc: 01c00084 movi r7,2 + 1004fd0: d8c00215 stw r3,8(sp) + 1004fd4: d8800315 stw r2,12(sp) + 1004fd8: dd000015 stw r20,0(sp) + 1004fdc: 10057900 call 1005790 <_dtoa_r> + 1004fe0: d9814d17 ldw r6,1332(sp) + 1004fe4: d8814115 stw r2,1284(sp) + 1004fe8: 008019c4 movi r2,103 + 1004fec: 30809526 beq r6,r2,1005244 <___vfprintf_internal_r+0x1cd8> + 1004ff0: d8c14d17 ldw r3,1332(sp) + 1004ff4: 008011c4 movi r2,71 + 1004ff8: 18809226 beq r3,r2,1005244 <___vfprintf_internal_r+0x1cd8> + 1004ffc: d9414117 ldw r5,1284(sp) + 1005000: d9814d17 ldw r6,1332(sp) + 1005004: 00801984 movi r2,102 + 1005008: 2d25883a add r18,r5,r20 + 100500c: 30808626 beq r6,r2,1005228 <___vfprintf_internal_r+0x1cbc> + 1005010: 00801184 movi r2,70 + 1005014: 30808426 beq r6,r2,1005228 <___vfprintf_internal_r+0x1cbc> + 1005018: 000d883a mov r6,zero + 100501c: 000f883a mov r7,zero + 1005020: 880b883a mov r5,r17 + 1005024: 8009883a mov r4,r16 + 1005028: 100b4ec0 call 100b4ec <__eqdf2> + 100502c: 1000751e bne r2,zero,1005204 <___vfprintf_internal_r+0x1c98> + 1005030: 9005883a mov r2,r18 + 1005034: dc800715 stw r18,28(sp) + 1005038: d9014117 ldw r4,1284(sp) + 100503c: d9414d17 ldw r5,1332(sp) + 1005040: 00c019c4 movi r3,103 + 1005044: 1125c83a sub r18,r2,r4 + 1005048: 28c06826 beq r5,r3,10051ec <___vfprintf_internal_r+0x1c80> + 100504c: 008011c4 movi r2,71 + 1005050: 28806626 beq r5,r2,10051ec <___vfprintf_internal_r+0x1c80> + 1005054: d9000517 ldw r4,20(sp) + 1005058: d8c14d17 ldw r3,1332(sp) + 100505c: 00801944 movi r2,101 + 1005060: 10c05516 blt r2,r3,10051b8 <___vfprintf_internal_r+0x1c4c> + 1005064: 213fffc4 addi r4,r4,-1 + 1005068: d9000515 stw r4,20(sp) + 100506c: d8c00805 stb r3,32(sp) + 1005070: 2021883a mov r16,r4 + 1005074: 2000c116 blt r4,zero,100537c <___vfprintf_internal_r+0x1e10> + 1005078: 00800ac4 movi r2,43 + 100507c: d8800845 stb r2,33(sp) + 1005080: 00800244 movi r2,9 + 1005084: 1400af0e bge r2,r16,1005344 <___vfprintf_internal_r+0x1dd8> + 1005088: 1027883a mov r19,r2 + 100508c: dc400b84 addi r17,sp,46 + 1005090: 8009883a mov r4,r16 + 1005094: 01400284 movi r5,10 + 1005098: 100bbd40 call 100bbd4 <__modsi3> + 100509c: 10800c04 addi r2,r2,48 + 10050a0: 8c7fffc4 addi r17,r17,-1 + 10050a4: 8009883a mov r4,r16 + 10050a8: 01400284 movi r5,10 + 10050ac: 88800005 stb r2,0(r17) + 10050b0: 100bb740 call 100bb74 <__divsi3> + 10050b4: 1021883a mov r16,r2 + 10050b8: 98bff516 blt r19,r2,1005090 <___vfprintf_internal_r+0x1b24> + 10050bc: 10c00c04 addi r3,r2,48 + 10050c0: d88009c4 addi r2,sp,39 + 10050c4: 108001c4 addi r2,r2,7 + 10050c8: 897fffc4 addi r5,r17,-1 + 10050cc: 88ffffc5 stb r3,-1(r17) + 10050d0: 2880a72e bgeu r5,r2,1005370 <___vfprintf_internal_r+0x1e04> + 10050d4: 1009883a mov r4,r2 + 10050d8: d9800804 addi r6,sp,32 + 10050dc: d8c00884 addi r3,sp,34 + 10050e0: 28800003 ldbu r2,0(r5) + 10050e4: 29400044 addi r5,r5,1 + 10050e8: 18800005 stb r2,0(r3) + 10050ec: 18c00044 addi r3,r3,1 + 10050f0: 293ffb36 bltu r5,r4,10050e0 <___vfprintf_internal_r+0x1b74> + 10050f4: 1987c83a sub r3,r3,r6 + 10050f8: 00800044 movi r2,1 + 10050fc: d8c14815 stw r3,1312(sp) + 1005100: 90cf883a add r7,r18,r3 + 1005104: 1480960e bge r2,r18,1005360 <___vfprintf_internal_r+0x1df4> + 1005108: 39c00044 addi r7,r7,1 + 100510c: d9c14515 stw r7,1300(sp) + 1005110: 38003416 blt r7,zero,10051e4 <___vfprintf_internal_r+0x1c78> + 1005114: e0803fcc andi r2,fp,255 + 1005118: 1080201c xori r2,r2,128 + 100511c: 10bfe004 addi r2,r2,-128 + 1005120: 10004e26 beq r2,zero,100525c <___vfprintf_internal_r+0x1cf0> + 1005124: 00800b44 movi r2,45 + 1005128: dc814715 stw r18,1308(sp) + 100512c: d8014615 stw zero,1304(sp) + 1005130: d8800405 stb r2,16(sp) + 1005134: 003bb106 br 1003ffc <___vfprintf_internal_r+0xa90> + 1005138: 00800b44 movi r2,45 + 100513c: d8800405 stb r2,16(sp) + 1005140: 003d3306 br 1004610 <___vfprintf_internal_r+0x10a4> + 1005144: d9014f17 ldw r4,1340(sp) + 1005148: b00b883a mov r5,r22 + 100514c: d9800c04 addi r6,sp,48 + 1005150: 10035140 call 1003514 <__sprint_r> + 1005154: 103abd1e bne r2,zero,1003c4c <___vfprintf_internal_r+0x6e0> + 1005158: 003abb06 br 1003c48 <___vfprintf_internal_r+0x6dc> + 100515c: 38800017 ldw r2,0(r7) + 1005160: 39c00104 addi r7,r7,4 + 1005164: d9c14015 stw r7,1280(sp) + 1005168: d9414b17 ldw r5,1324(sp) + 100516c: d9c14017 ldw r7,1280(sp) + 1005170: 11400015 stw r5,0(r2) + 1005174: 00395906 br 10036dc <___vfprintf_internal_r+0x170> + 1005178: 980f883a mov r7,r19 + 100517c: dcc14515 stw r19,1300(sp) + 1005180: d8014615 stw zero,1304(sp) + 1005184: 003b9b06 br 1003ff4 <___vfprintf_internal_r+0xa88> + 1005188: 0027883a mov r19,zero + 100518c: 00397806 br 1003770 <___vfprintf_internal_r+0x204> + 1005190: 00c040b4 movhi r3,258 + 1005194: 18e37404 addi r3,r3,-29232 + 1005198: 100f883a mov r7,r2 + 100519c: d8814515 stw r2,1300(sp) + 10051a0: d8c14115 stw r3,1284(sp) + 10051a4: 0039e006 br 1003928 <___vfprintf_internal_r+0x3bc> + 10051a8: 008040b4 movhi r2,258 + 10051ac: 10a37304 addi r2,r2,-29236 + 10051b0: d8814115 stw r2,1284(sp) + 10051b4: 003d1c06 br 1004628 <___vfprintf_internal_r+0x10bc> + 10051b8: d9414d17 ldw r5,1332(sp) + 10051bc: 00801984 movi r2,102 + 10051c0: 28804926 beq r5,r2,10052e8 <___vfprintf_internal_r+0x1d7c> + 10051c4: 200f883a mov r7,r4 + 10051c8: 24805716 blt r4,r18,1005328 <___vfprintf_internal_r+0x1dbc> + 10051cc: d9414c17 ldw r5,1328(sp) + 10051d0: 2880004c andi r2,r5,1 + 10051d4: 10000126 beq r2,zero,10051dc <___vfprintf_internal_r+0x1c70> + 10051d8: 21c00044 addi r7,r4,1 + 10051dc: d9c14515 stw r7,1300(sp) + 10051e0: 383fcc0e bge r7,zero,1005114 <___vfprintf_internal_r+0x1ba8> + 10051e4: d8014515 stw zero,1300(sp) + 10051e8: 003fca06 br 1005114 <___vfprintf_internal_r+0x1ba8> + 10051ec: d9000517 ldw r4,20(sp) + 10051f0: 00bfff04 movi r2,-4 + 10051f4: 1100480e bge r2,r4,1005318 <___vfprintf_internal_r+0x1dac> + 10051f8: 99004716 blt r19,r4,1005318 <___vfprintf_internal_r+0x1dac> + 10051fc: d8c14d15 stw r3,1332(sp) + 1005200: 003ff006 br 10051c4 <___vfprintf_internal_r+0x1c58> + 1005204: d8800717 ldw r2,28(sp) + 1005208: 14bf8b2e bgeu r2,r18,1005038 <___vfprintf_internal_r+0x1acc> + 100520c: 9007883a mov r3,r18 + 1005210: 01000c04 movi r4,48 + 1005214: 11000005 stb r4,0(r2) + 1005218: 10800044 addi r2,r2,1 + 100521c: d8800715 stw r2,28(sp) + 1005220: 18bffc1e bne r3,r2,1005214 <___vfprintf_internal_r+0x1ca8> + 1005224: 003f8406 br 1005038 <___vfprintf_internal_r+0x1acc> + 1005228: d8814117 ldw r2,1284(sp) + 100522c: 10c00007 ldb r3,0(r2) + 1005230: 00800c04 movi r2,48 + 1005234: 18805b26 beq r3,r2,10053a4 <___vfprintf_internal_r+0x1e38> + 1005238: d9000517 ldw r4,20(sp) + 100523c: 9125883a add r18,r18,r4 + 1005240: 003f7506 br 1005018 <___vfprintf_internal_r+0x1aac> + 1005244: d9014c17 ldw r4,1328(sp) + 1005248: 2080004c andi r2,r4,1 + 100524c: 1005003a cmpeq r2,r2,zero + 1005250: 103f6a26 beq r2,zero,1004ffc <___vfprintf_internal_r+0x1a90> + 1005254: d8800717 ldw r2,28(sp) + 1005258: 003f7706 br 1005038 <___vfprintf_internal_r+0x1acc> + 100525c: d9c14515 stw r7,1300(sp) + 1005260: 38004d16 blt r7,zero,1005398 <___vfprintf_internal_r+0x1e2c> + 1005264: dc814715 stw r18,1308(sp) + 1005268: d8014615 stw zero,1304(sp) + 100526c: 003b6106 br 1003ff4 <___vfprintf_internal_r+0xa88> + 1005270: d9014f17 ldw r4,1340(sp) + 1005274: d8800504 addi r2,sp,20 + 1005278: d8800115 stw r2,4(sp) + 100527c: d8c00604 addi r3,sp,24 + 1005280: d8800704 addi r2,sp,28 + 1005284: 800b883a mov r5,r16 + 1005288: 880d883a mov r6,r17 + 100528c: 01c000c4 movi r7,3 + 1005290: d8c00215 stw r3,8(sp) + 1005294: d8800315 stw r2,12(sp) + 1005298: dcc00015 stw r19,0(sp) + 100529c: 9829883a mov r20,r19 + 10052a0: 10057900 call 1005790 <_dtoa_r> + 10052a4: d8814115 stw r2,1284(sp) + 10052a8: 003f5106 br 1004ff0 <___vfprintf_internal_r+0x1a84> + 10052ac: d8c14217 ldw r3,1288(sp) + 10052b0: d9014317 ldw r4,1292(sp) + 10052b4: 07000b44 movi fp,45 + 10052b8: 1821883a mov r16,r3 + 10052bc: 2460003c xorhi r17,r4,32768 + 10052c0: 003f3106 br 1004f88 <___vfprintf_internal_r+0x1a1c> + 10052c4: 9d000044 addi r20,r19,1 + 10052c8: 003f3906 br 1004fb0 <___vfprintf_internal_r+0x1a44> + 10052cc: 983f251e bne r19,zero,1004f64 <___vfprintf_internal_r+0x19f8> + 10052d0: 04c00044 movi r19,1 + 10052d4: 003f2306 br 1004f64 <___vfprintf_internal_r+0x19f8> + 10052d8: 04c00184 movi r19,6 + 10052dc: 003f2106 br 1004f64 <___vfprintf_internal_r+0x19f8> + 10052e0: d8014515 stw zero,1300(sp) + 10052e4: 003eee06 br 1004ea0 <___vfprintf_internal_r+0x1934> + 10052e8: 200f883a mov r7,r4 + 10052ec: 0100370e bge zero,r4,10053cc <___vfprintf_internal_r+0x1e60> + 10052f0: 9800031e bne r19,zero,1005300 <___vfprintf_internal_r+0x1d94> + 10052f4: d9814c17 ldw r6,1328(sp) + 10052f8: 3080004c andi r2,r6,1 + 10052fc: 103fb726 beq r2,zero,10051dc <___vfprintf_internal_r+0x1c70> + 1005300: 20800044 addi r2,r4,1 + 1005304: 98a7883a add r19,r19,r2 + 1005308: dcc14515 stw r19,1300(sp) + 100530c: 980f883a mov r7,r19 + 1005310: 983f800e bge r19,zero,1005114 <___vfprintf_internal_r+0x1ba8> + 1005314: 003fb306 br 10051e4 <___vfprintf_internal_r+0x1c78> + 1005318: d9814d17 ldw r6,1332(sp) + 100531c: 31bfff84 addi r6,r6,-2 + 1005320: d9814d15 stw r6,1332(sp) + 1005324: 003f4c06 br 1005058 <___vfprintf_internal_r+0x1aec> + 1005328: 0100180e bge zero,r4,100538c <___vfprintf_internal_r+0x1e20> + 100532c: 00800044 movi r2,1 + 1005330: 1485883a add r2,r2,r18 + 1005334: d8814515 stw r2,1300(sp) + 1005338: 100f883a mov r7,r2 + 100533c: 103f750e bge r2,zero,1005114 <___vfprintf_internal_r+0x1ba8> + 1005340: 003fa806 br 10051e4 <___vfprintf_internal_r+0x1c78> + 1005344: 80c00c04 addi r3,r16,48 + 1005348: 00800c04 movi r2,48 + 100534c: d8c008c5 stb r3,35(sp) + 1005350: d9800804 addi r6,sp,32 + 1005354: d8c00904 addi r3,sp,36 + 1005358: d8800885 stb r2,34(sp) + 100535c: 003f6506 br 10050f4 <___vfprintf_internal_r+0x1b88> + 1005360: d9014c17 ldw r4,1328(sp) + 1005364: 2084703a and r2,r4,r2 + 1005368: 103f9c26 beq r2,zero,10051dc <___vfprintf_internal_r+0x1c70> + 100536c: 003f6606 br 1005108 <___vfprintf_internal_r+0x1b9c> + 1005370: d9800804 addi r6,sp,32 + 1005374: d8c00884 addi r3,sp,34 + 1005378: 003f5e06 br 10050f4 <___vfprintf_internal_r+0x1b88> + 100537c: 00800b44 movi r2,45 + 1005380: 0121c83a sub r16,zero,r4 + 1005384: d8800845 stb r2,33(sp) + 1005388: 003f3d06 br 1005080 <___vfprintf_internal_r+0x1b14> + 100538c: 00800084 movi r2,2 + 1005390: 1105c83a sub r2,r2,r4 + 1005394: 003fe606 br 1005330 <___vfprintf_internal_r+0x1dc4> + 1005398: d8014515 stw zero,1300(sp) + 100539c: dc814715 stw r18,1308(sp) + 10053a0: 003fb106 br 1005268 <___vfprintf_internal_r+0x1cfc> + 10053a4: 000d883a mov r6,zero + 10053a8: 000f883a mov r7,zero + 10053ac: 8009883a mov r4,r16 + 10053b0: 880b883a mov r5,r17 + 10053b4: 100b5740 call 100b574 <__nedf2> + 10053b8: 103f9f26 beq r2,zero,1005238 <___vfprintf_internal_r+0x1ccc> + 10053bc: 00800044 movi r2,1 + 10053c0: 1509c83a sub r4,r2,r20 + 10053c4: d9000515 stw r4,20(sp) + 10053c8: 003f9b06 br 1005238 <___vfprintf_internal_r+0x1ccc> + 10053cc: 98000d1e bne r19,zero,1005404 <___vfprintf_internal_r+0x1e98> + 10053d0: d8c14c17 ldw r3,1328(sp) + 10053d4: 1880004c andi r2,r3,1 + 10053d8: 10000a1e bne r2,zero,1005404 <___vfprintf_internal_r+0x1e98> + 10053dc: 01000044 movi r4,1 + 10053e0: 200f883a mov r7,r4 + 10053e4: d9014515 stw r4,1300(sp) + 10053e8: 003f4a06 br 1005114 <___vfprintf_internal_r+0x1ba8> + 10053ec: 3cc00017 ldw r19,0(r7) + 10053f0: 39c00104 addi r7,r7,4 + 10053f4: 983d0e0e bge r19,zero,1004830 <___vfprintf_internal_r+0x12c4> + 10053f8: b8c00007 ldb r3,0(r23) + 10053fc: 04ffffc4 movi r19,-1 + 1005400: 0038d906 br 1003768 <___vfprintf_internal_r+0x1fc> + 1005404: 9cc00084 addi r19,r19,2 + 1005408: dcc14515 stw r19,1300(sp) + 100540c: 980f883a mov r7,r19 + 1005410: 983f400e bge r19,zero,1005114 <___vfprintf_internal_r+0x1ba8> + 1005414: 003f7306 br 10051e4 <___vfprintf_internal_r+0x1c78> + +01005418 <__vfprintf_internal>: + 1005418: 008040b4 movhi r2,258 + 100541c: 10ab9804 addi r2,r2,-20896 + 1005420: 2013883a mov r9,r4 + 1005424: 11000017 ldw r4,0(r2) + 1005428: 2805883a mov r2,r5 + 100542c: 300f883a mov r7,r6 + 1005430: 480b883a mov r5,r9 + 1005434: 100d883a mov r6,r2 + 1005438: 100356c1 jmpi 100356c <___vfprintf_internal_r> + +0100543c <__swsetup_r>: + 100543c: 008040b4 movhi r2,258 + 1005440: 10ab9804 addi r2,r2,-20896 + 1005444: 10c00017 ldw r3,0(r2) + 1005448: defffd04 addi sp,sp,-12 + 100544c: dc400115 stw r17,4(sp) + 1005450: dc000015 stw r16,0(sp) + 1005454: dfc00215 stw ra,8(sp) + 1005458: 2023883a mov r17,r4 + 100545c: 2821883a mov r16,r5 + 1005460: 18000226 beq r3,zero,100546c <__swsetup_r+0x30> + 1005464: 18800e17 ldw r2,56(r3) + 1005468: 10001f26 beq r2,zero,10054e8 <__swsetup_r+0xac> + 100546c: 8100030b ldhu r4,12(r16) + 1005470: 2080020c andi r2,r4,8 + 1005474: 10002826 beq r2,zero,1005518 <__swsetup_r+0xdc> + 1005478: 81400417 ldw r5,16(r16) + 100547c: 28001d26 beq r5,zero,10054f4 <__swsetup_r+0xb8> + 1005480: 2080004c andi r2,r4,1 + 1005484: 1005003a cmpeq r2,r2,zero + 1005488: 10000b26 beq r2,zero,10054b8 <__swsetup_r+0x7c> + 100548c: 2080008c andi r2,r4,2 + 1005490: 10001226 beq r2,zero,10054dc <__swsetup_r+0xa0> + 1005494: 0005883a mov r2,zero + 1005498: 80800215 stw r2,8(r16) + 100549c: 28000b26 beq r5,zero,10054cc <__swsetup_r+0x90> + 10054a0: 0005883a mov r2,zero + 10054a4: dfc00217 ldw ra,8(sp) + 10054a8: dc400117 ldw r17,4(sp) + 10054ac: dc000017 ldw r16,0(sp) + 10054b0: dec00304 addi sp,sp,12 + 10054b4: f800283a ret + 10054b8: 80800517 ldw r2,20(r16) + 10054bc: 80000215 stw zero,8(r16) + 10054c0: 0085c83a sub r2,zero,r2 + 10054c4: 80800615 stw r2,24(r16) + 10054c8: 283ff51e bne r5,zero,10054a0 <__swsetup_r+0x64> + 10054cc: 2080200c andi r2,r4,128 + 10054d0: 103ff326 beq r2,zero,10054a0 <__swsetup_r+0x64> + 10054d4: 00bfffc4 movi r2,-1 + 10054d8: 003ff206 br 10054a4 <__swsetup_r+0x68> + 10054dc: 80800517 ldw r2,20(r16) + 10054e0: 80800215 stw r2,8(r16) + 10054e4: 003fed06 br 100549c <__swsetup_r+0x60> + 10054e8: 1809883a mov r4,r3 + 10054ec: 1006fdc0 call 1006fdc <__sinit> + 10054f0: 003fde06 br 100546c <__swsetup_r+0x30> + 10054f4: 20c0a00c andi r3,r4,640 + 10054f8: 00808004 movi r2,512 + 10054fc: 18bfe026 beq r3,r2,1005480 <__swsetup_r+0x44> + 1005500: 8809883a mov r4,r17 + 1005504: 800b883a mov r5,r16 + 1005508: 1007d540 call 1007d54 <__smakebuf_r> + 100550c: 8100030b ldhu r4,12(r16) + 1005510: 81400417 ldw r5,16(r16) + 1005514: 003fda06 br 1005480 <__swsetup_r+0x44> + 1005518: 2080040c andi r2,r4,16 + 100551c: 103fed26 beq r2,zero,10054d4 <__swsetup_r+0x98> + 1005520: 2080010c andi r2,r4,4 + 1005524: 10001226 beq r2,zero,1005570 <__swsetup_r+0x134> + 1005528: 81400c17 ldw r5,48(r16) + 100552c: 28000526 beq r5,zero,1005544 <__swsetup_r+0x108> + 1005530: 80801004 addi r2,r16,64 + 1005534: 28800226 beq r5,r2,1005540 <__swsetup_r+0x104> + 1005538: 8809883a mov r4,r17 + 100553c: 10073600 call 1007360 <_free_r> + 1005540: 80000c15 stw zero,48(r16) + 1005544: 8080030b ldhu r2,12(r16) + 1005548: 81400417 ldw r5,16(r16) + 100554c: 80000115 stw zero,4(r16) + 1005550: 10bff6cc andi r2,r2,65499 + 1005554: 8080030d sth r2,12(r16) + 1005558: 81400015 stw r5,0(r16) + 100555c: 8080030b ldhu r2,12(r16) + 1005560: 10800214 ori r2,r2,8 + 1005564: 113fffcc andi r4,r2,65535 + 1005568: 8080030d sth r2,12(r16) + 100556c: 003fc306 br 100547c <__swsetup_r+0x40> + 1005570: 81400417 ldw r5,16(r16) + 1005574: 003ff906 br 100555c <__swsetup_r+0x120> + +01005578 : + 1005578: 28c00417 ldw r3,16(r5) + 100557c: 20800417 ldw r2,16(r4) + 1005580: defff604 addi sp,sp,-40 + 1005584: ddc00715 stw r23,28(sp) + 1005588: dd400515 stw r21,20(sp) + 100558c: dfc00915 stw ra,36(sp) + 1005590: df000815 stw fp,32(sp) + 1005594: dd800615 stw r22,24(sp) + 1005598: dd000415 stw r20,16(sp) + 100559c: dcc00315 stw r19,12(sp) + 10055a0: dc800215 stw r18,8(sp) + 10055a4: dc400115 stw r17,4(sp) + 10055a8: dc000015 stw r16,0(sp) + 10055ac: 202f883a mov r23,r4 + 10055b0: 282b883a mov r21,r5 + 10055b4: 10c07416 blt r2,r3,1005788 + 10055b8: 1c7fffc4 addi r17,r3,-1 + 10055bc: 8c45883a add r2,r17,r17 + 10055c0: 1085883a add r2,r2,r2 + 10055c4: 2c000504 addi r16,r5,20 + 10055c8: 24c00504 addi r19,r4,20 + 10055cc: 14ed883a add r22,r2,r19 + 10055d0: 80a5883a add r18,r16,r2 + 10055d4: b7000017 ldw fp,0(r22) + 10055d8: 91400017 ldw r5,0(r18) + 10055dc: e009883a mov r4,fp + 10055e0: 29400044 addi r5,r5,1 + 10055e4: 100bc340 call 100bc34 <__udivsi3> + 10055e8: 1029883a mov r20,r2 + 10055ec: 10003c1e bne r2,zero,10056e0 + 10055f0: a80b883a mov r5,r21 + 10055f4: b809883a mov r4,r23 + 10055f8: 10082a80 call 10082a8 <__mcmp> + 10055fc: 10002b16 blt r2,zero,10056ac + 1005600: a5000044 addi r20,r20,1 + 1005604: 980f883a mov r7,r19 + 1005608: 0011883a mov r8,zero + 100560c: 0009883a mov r4,zero + 1005610: 81400017 ldw r5,0(r16) + 1005614: 38c00017 ldw r3,0(r7) + 1005618: 84000104 addi r16,r16,4 + 100561c: 28bfffcc andi r2,r5,65535 + 1005620: 2085883a add r2,r4,r2 + 1005624: 11bfffcc andi r6,r2,65535 + 1005628: 193fffcc andi r4,r3,65535 + 100562c: 1004d43a srli r2,r2,16 + 1005630: 280ad43a srli r5,r5,16 + 1005634: 2189c83a sub r4,r4,r6 + 1005638: 2209883a add r4,r4,r8 + 100563c: 1806d43a srli r3,r3,16 + 1005640: 288b883a add r5,r5,r2 + 1005644: 200dd43a srai r6,r4,16 + 1005648: 28bfffcc andi r2,r5,65535 + 100564c: 1887c83a sub r3,r3,r2 + 1005650: 1987883a add r3,r3,r6 + 1005654: 3900000d sth r4,0(r7) + 1005658: 38c0008d sth r3,2(r7) + 100565c: 2808d43a srli r4,r5,16 + 1005660: 39c00104 addi r7,r7,4 + 1005664: 1811d43a srai r8,r3,16 + 1005668: 943fe92e bgeu r18,r16,1005610 + 100566c: 8c45883a add r2,r17,r17 + 1005670: 1085883a add r2,r2,r2 + 1005674: 9885883a add r2,r19,r2 + 1005678: 10c00017 ldw r3,0(r2) + 100567c: 18000b1e bne r3,zero,10056ac + 1005680: 113fff04 addi r4,r2,-4 + 1005684: 9900082e bgeu r19,r4,10056a8 + 1005688: 10bfff17 ldw r2,-4(r2) + 100568c: 10000326 beq r2,zero,100569c + 1005690: 00000506 br 10056a8 + 1005694: 20800017 ldw r2,0(r4) + 1005698: 1000031e bne r2,zero,10056a8 + 100569c: 213fff04 addi r4,r4,-4 + 10056a0: 8c7fffc4 addi r17,r17,-1 + 10056a4: 993ffb36 bltu r19,r4,1005694 + 10056a8: bc400415 stw r17,16(r23) + 10056ac: a005883a mov r2,r20 + 10056b0: dfc00917 ldw ra,36(sp) + 10056b4: df000817 ldw fp,32(sp) + 10056b8: ddc00717 ldw r23,28(sp) + 10056bc: dd800617 ldw r22,24(sp) + 10056c0: dd400517 ldw r21,20(sp) + 10056c4: dd000417 ldw r20,16(sp) + 10056c8: dcc00317 ldw r19,12(sp) + 10056cc: dc800217 ldw r18,8(sp) + 10056d0: dc400117 ldw r17,4(sp) + 10056d4: dc000017 ldw r16,0(sp) + 10056d8: dec00a04 addi sp,sp,40 + 10056dc: f800283a ret + 10056e0: 980f883a mov r7,r19 + 10056e4: 8011883a mov r8,r16 + 10056e8: 0013883a mov r9,zero + 10056ec: 000d883a mov r6,zero + 10056f0: 40c00017 ldw r3,0(r8) + 10056f4: 39000017 ldw r4,0(r7) + 10056f8: 42000104 addi r8,r8,4 + 10056fc: 18bfffcc andi r2,r3,65535 + 1005700: a085383a mul r2,r20,r2 + 1005704: 1806d43a srli r3,r3,16 + 1005708: 217fffcc andi r5,r4,65535 + 100570c: 3085883a add r2,r6,r2 + 1005710: 11bfffcc andi r6,r2,65535 + 1005714: a0c7383a mul r3,r20,r3 + 1005718: 1004d43a srli r2,r2,16 + 100571c: 298bc83a sub r5,r5,r6 + 1005720: 2a4b883a add r5,r5,r9 + 1005724: 2008d43a srli r4,r4,16 + 1005728: 1887883a add r3,r3,r2 + 100572c: 280dd43a srai r6,r5,16 + 1005730: 18bfffcc andi r2,r3,65535 + 1005734: 2089c83a sub r4,r4,r2 + 1005738: 2189883a add r4,r4,r6 + 100573c: 3900008d sth r4,2(r7) + 1005740: 3940000d sth r5,0(r7) + 1005744: 180cd43a srli r6,r3,16 + 1005748: 39c00104 addi r7,r7,4 + 100574c: 2013d43a srai r9,r4,16 + 1005750: 923fe72e bgeu r18,r8,10056f0 + 1005754: e03fa61e bne fp,zero,10055f0 + 1005758: b0ffff04 addi r3,r22,-4 + 100575c: 98c0082e bgeu r19,r3,1005780 + 1005760: b0bfff17 ldw r2,-4(r22) + 1005764: 10000326 beq r2,zero,1005774 + 1005768: 00000506 br 1005780 + 100576c: 18800017 ldw r2,0(r3) + 1005770: 1000031e bne r2,zero,1005780 + 1005774: 18ffff04 addi r3,r3,-4 + 1005778: 8c7fffc4 addi r17,r17,-1 + 100577c: 98fffb36 bltu r19,r3,100576c + 1005780: bc400415 stw r17,16(r23) + 1005784: 003f9a06 br 10055f0 + 1005788: 0005883a mov r2,zero + 100578c: 003fc806 br 10056b0 + +01005790 <_dtoa_r>: + 1005790: 22001017 ldw r8,64(r4) + 1005794: deffda04 addi sp,sp,-152 + 1005798: dd402115 stw r21,132(sp) + 100579c: dd002015 stw r20,128(sp) + 10057a0: dc801e15 stw r18,120(sp) + 10057a4: dc401d15 stw r17,116(sp) + 10057a8: dfc02515 stw ra,148(sp) + 10057ac: df002415 stw fp,144(sp) + 10057b0: ddc02315 stw r23,140(sp) + 10057b4: dd802215 stw r22,136(sp) + 10057b8: dcc01f15 stw r19,124(sp) + 10057bc: dc001c15 stw r16,112(sp) + 10057c0: d9001615 stw r4,88(sp) + 10057c4: 3023883a mov r17,r6 + 10057c8: 2829883a mov r20,r5 + 10057cc: d9c01715 stw r7,92(sp) + 10057d0: dc802817 ldw r18,160(sp) + 10057d4: 302b883a mov r21,r6 + 10057d8: 40000a26 beq r8,zero,1005804 <_dtoa_r+0x74> + 10057dc: 20801117 ldw r2,68(r4) + 10057e0: 400b883a mov r5,r8 + 10057e4: 40800115 stw r2,4(r8) + 10057e8: 20c01117 ldw r3,68(r4) + 10057ec: 00800044 movi r2,1 + 10057f0: 10c4983a sll r2,r2,r3 + 10057f4: 40800215 stw r2,8(r8) + 10057f8: 100814c0 call 100814c <_Bfree> + 10057fc: d8c01617 ldw r3,88(sp) + 1005800: 18001015 stw zero,64(r3) + 1005804: 8800a316 blt r17,zero,1005a94 <_dtoa_r+0x304> + 1005808: 90000015 stw zero,0(r18) + 100580c: a8dffc2c andhi r3,r21,32752 + 1005810: 009ffc34 movhi r2,32752 + 1005814: 18809126 beq r3,r2,1005a5c <_dtoa_r+0x2cc> + 1005818: 000d883a mov r6,zero + 100581c: 000f883a mov r7,zero + 1005820: a009883a mov r4,r20 + 1005824: a80b883a mov r5,r21 + 1005828: dd001215 stw r20,72(sp) + 100582c: dd401315 stw r21,76(sp) + 1005830: 100b5740 call 100b574 <__nedf2> + 1005834: 1000171e bne r2,zero,1005894 <_dtoa_r+0x104> + 1005838: d9802717 ldw r6,156(sp) + 100583c: 00800044 movi r2,1 + 1005840: 30800015 stw r2,0(r6) + 1005844: d8802917 ldw r2,164(sp) + 1005848: 10029b26 beq r2,zero,10062b8 <_dtoa_r+0xb28> + 100584c: d9002917 ldw r4,164(sp) + 1005850: 008040b4 movhi r2,258 + 1005854: 10a38244 addi r2,r2,-29175 + 1005858: 10ffffc4 addi r3,r2,-1 + 100585c: 20800015 stw r2,0(r4) + 1005860: 1805883a mov r2,r3 + 1005864: dfc02517 ldw ra,148(sp) + 1005868: df002417 ldw fp,144(sp) + 100586c: ddc02317 ldw r23,140(sp) + 1005870: dd802217 ldw r22,136(sp) + 1005874: dd402117 ldw r21,132(sp) + 1005878: dd002017 ldw r20,128(sp) + 100587c: dcc01f17 ldw r19,124(sp) + 1005880: dc801e17 ldw r18,120(sp) + 1005884: dc401d17 ldw r17,116(sp) + 1005888: dc001c17 ldw r16,112(sp) + 100588c: dec02604 addi sp,sp,152 + 1005890: f800283a ret + 1005894: d9001617 ldw r4,88(sp) + 1005898: d9401217 ldw r5,72(sp) + 100589c: d8800104 addi r2,sp,4 + 10058a0: a80d883a mov r6,r21 + 10058a4: d9c00204 addi r7,sp,8 + 10058a8: d8800015 stw r2,0(sp) + 10058ac: 10087880 call 1008788 <__d2b> + 10058b0: d8800715 stw r2,28(sp) + 10058b4: a804d53a srli r2,r21,20 + 10058b8: 1101ffcc andi r4,r2,2047 + 10058bc: 20008626 beq r4,zero,1005ad8 <_dtoa_r+0x348> + 10058c0: d8c01217 ldw r3,72(sp) + 10058c4: 00800434 movhi r2,16 + 10058c8: 10bfffc4 addi r2,r2,-1 + 10058cc: ddc00117 ldw r23,4(sp) + 10058d0: a884703a and r2,r21,r2 + 10058d4: 1811883a mov r8,r3 + 10058d8: 124ffc34 orhi r9,r2,16368 + 10058dc: 25bf0044 addi r22,r4,-1023 + 10058e0: d8000815 stw zero,32(sp) + 10058e4: 0005883a mov r2,zero + 10058e8: 00cffe34 movhi r3,16376 + 10058ec: 480b883a mov r5,r9 + 10058f0: 4009883a mov r4,r8 + 10058f4: 180f883a mov r7,r3 + 10058f8: 100d883a mov r6,r2 + 10058fc: 100addc0 call 100addc <__subdf3> + 1005900: 0218dbf4 movhi r8,25455 + 1005904: 4210d844 addi r8,r8,17249 + 1005908: 024ff4f4 movhi r9,16339 + 100590c: 4a61e9c4 addi r9,r9,-30809 + 1005910: 480f883a mov r7,r9 + 1005914: 400d883a mov r6,r8 + 1005918: 180b883a mov r5,r3 + 100591c: 1009883a mov r4,r2 + 1005920: 100aed00 call 100aed0 <__muldf3> + 1005924: 0222d874 movhi r8,35681 + 1005928: 42322cc4 addi r8,r8,-14157 + 100592c: 024ff1f4 movhi r9,16327 + 1005930: 4a628a04 addi r9,r9,-30168 + 1005934: 480f883a mov r7,r9 + 1005938: 400d883a mov r6,r8 + 100593c: 180b883a mov r5,r3 + 1005940: 1009883a mov r4,r2 + 1005944: 100ae5c0 call 100ae5c <__adddf3> + 1005948: b009883a mov r4,r22 + 100594c: 1021883a mov r16,r2 + 1005950: 1823883a mov r17,r3 + 1005954: 100b7940 call 100b794 <__floatsidf> + 1005958: 021427f4 movhi r8,20639 + 100595c: 421e7ec4 addi r8,r8,31227 + 1005960: 024ff4f4 movhi r9,16339 + 1005964: 4a5104c4 addi r9,r9,17427 + 1005968: 480f883a mov r7,r9 + 100596c: 400d883a mov r6,r8 + 1005970: 180b883a mov r5,r3 + 1005974: 1009883a mov r4,r2 + 1005978: 100aed00 call 100aed0 <__muldf3> + 100597c: 180f883a mov r7,r3 + 1005980: 880b883a mov r5,r17 + 1005984: 100d883a mov r6,r2 + 1005988: 8009883a mov r4,r16 + 100598c: 100ae5c0 call 100ae5c <__adddf3> + 1005990: 1009883a mov r4,r2 + 1005994: 180b883a mov r5,r3 + 1005998: 1021883a mov r16,r2 + 100599c: 1823883a mov r17,r3 + 10059a0: 100b88c0 call 100b88c <__fixdfsi> + 10059a4: 000d883a mov r6,zero + 10059a8: 000f883a mov r7,zero + 10059ac: 8009883a mov r4,r16 + 10059b0: 880b883a mov r5,r17 + 10059b4: d8800d15 stw r2,52(sp) + 10059b8: 100b70c0 call 100b70c <__ltdf2> + 10059bc: 10031716 blt r2,zero,100661c <_dtoa_r+0xe8c> + 10059c0: d8c00d17 ldw r3,52(sp) + 10059c4: 00800584 movi r2,22 + 10059c8: 10c1482e bgeu r2,r3,1005eec <_dtoa_r+0x75c> + 10059cc: 01000044 movi r4,1 + 10059d0: d9000c15 stw r4,48(sp) + 10059d4: bd85c83a sub r2,r23,r22 + 10059d8: 11bfffc4 addi r6,r2,-1 + 10059dc: 30030b16 blt r6,zero,100660c <_dtoa_r+0xe7c> + 10059e0: d9800a15 stw r6,40(sp) + 10059e4: d8001115 stw zero,68(sp) + 10059e8: d8c00d17 ldw r3,52(sp) + 10059ec: 1802ff16 blt r3,zero,10065ec <_dtoa_r+0xe5c> + 10059f0: d9000a17 ldw r4,40(sp) + 10059f4: d8c00915 stw r3,36(sp) + 10059f8: d8001015 stw zero,64(sp) + 10059fc: 20c9883a add r4,r4,r3 + 1005a00: d9000a15 stw r4,40(sp) + 1005a04: d9001717 ldw r4,92(sp) + 1005a08: 00800244 movi r2,9 + 1005a0c: 11004636 bltu r2,r4,1005b28 <_dtoa_r+0x398> + 1005a10: 00800144 movi r2,5 + 1005a14: 11020416 blt r2,r4,1006228 <_dtoa_r+0xa98> + 1005a18: 04400044 movi r17,1 + 1005a1c: d8c01717 ldw r3,92(sp) + 1005a20: 00800144 movi r2,5 + 1005a24: 10c1ed36 bltu r2,r3,10061dc <_dtoa_r+0xa4c> + 1005a28: 18c5883a add r2,r3,r3 + 1005a2c: 1085883a add r2,r2,r2 + 1005a30: 00c04034 movhi r3,256 + 1005a34: 18d69104 addi r3,r3,23108 + 1005a38: 10c5883a add r2,r2,r3 + 1005a3c: 11000017 ldw r4,0(r2) + 1005a40: 2000683a jmp r4 + 1005a44: 01005b30 cmpltui r4,zero,364 + 1005a48: 01005b30 cmpltui r4,zero,364 + 1005a4c: 01006530 cmpltui r4,zero,404 + 1005a50: 01006508 cmpgei r4,zero,404 + 1005a54: 0100654c andi r4,zero,405 + 1005a58: 01006558 cmpnei r4,zero,405 + 1005a5c: d9002717 ldw r4,156(sp) + 1005a60: 0089c3c4 movi r2,9999 + 1005a64: 20800015 stw r2,0(r4) + 1005a68: a0001026 beq r20,zero,1005aac <_dtoa_r+0x31c> + 1005a6c: 00c040b4 movhi r3,258 + 1005a70: 18e38e04 addi r3,r3,-29128 + 1005a74: d9802917 ldw r6,164(sp) + 1005a78: 303f7926 beq r6,zero,1005860 <_dtoa_r+0xd0> + 1005a7c: 188000c7 ldb r2,3(r3) + 1005a80: 190000c4 addi r4,r3,3 + 1005a84: 1000101e bne r2,zero,1005ac8 <_dtoa_r+0x338> + 1005a88: d8802917 ldw r2,164(sp) + 1005a8c: 11000015 stw r4,0(r2) + 1005a90: 003f7306 br 1005860 <_dtoa_r+0xd0> + 1005a94: 00a00034 movhi r2,32768 + 1005a98: 10bfffc4 addi r2,r2,-1 + 1005a9c: 00c00044 movi r3,1 + 1005aa0: 88aa703a and r21,r17,r2 + 1005aa4: 90c00015 stw r3,0(r18) + 1005aa8: 003f5806 br 100580c <_dtoa_r+0x7c> + 1005aac: 00800434 movhi r2,16 + 1005ab0: 10bfffc4 addi r2,r2,-1 + 1005ab4: a884703a and r2,r21,r2 + 1005ab8: 103fec1e bne r2,zero,1005a6c <_dtoa_r+0x2dc> + 1005abc: 00c040b4 movhi r3,258 + 1005ac0: 18e38b04 addi r3,r3,-29140 + 1005ac4: 003feb06 br 1005a74 <_dtoa_r+0x2e4> + 1005ac8: d8802917 ldw r2,164(sp) + 1005acc: 19000204 addi r4,r3,8 + 1005ad0: 11000015 stw r4,0(r2) + 1005ad4: 003f6206 br 1005860 <_dtoa_r+0xd0> + 1005ad8: ddc00117 ldw r23,4(sp) + 1005adc: d8800217 ldw r2,8(sp) + 1005ae0: 01000804 movi r4,32 + 1005ae4: b8c10c84 addi r3,r23,1074 + 1005ae8: 18a3883a add r17,r3,r2 + 1005aec: 2441b80e bge r4,r17,10061d0 <_dtoa_r+0xa40> + 1005af0: 00c01004 movi r3,64 + 1005af4: 1c47c83a sub r3,r3,r17 + 1005af8: 88bff804 addi r2,r17,-32 + 1005afc: a8c6983a sll r3,r21,r3 + 1005b00: a084d83a srl r2,r20,r2 + 1005b04: 1888b03a or r4,r3,r2 + 1005b08: 100b9640 call 100b964 <__floatunsidf> + 1005b0c: 1011883a mov r8,r2 + 1005b10: 00bf8434 movhi r2,65040 + 1005b14: 01000044 movi r4,1 + 1005b18: 10d3883a add r9,r2,r3 + 1005b1c: 8dbef344 addi r22,r17,-1075 + 1005b20: d9000815 stw r4,32(sp) + 1005b24: 003f6f06 br 10058e4 <_dtoa_r+0x154> + 1005b28: d8001715 stw zero,92(sp) + 1005b2c: 04400044 movi r17,1 + 1005b30: 00bfffc4 movi r2,-1 + 1005b34: 00c00044 movi r3,1 + 1005b38: d8800e15 stw r2,56(sp) + 1005b3c: d8002615 stw zero,152(sp) + 1005b40: d8800f15 stw r2,60(sp) + 1005b44: d8c00b15 stw r3,44(sp) + 1005b48: 1021883a mov r16,r2 + 1005b4c: d8801617 ldw r2,88(sp) + 1005b50: 10001115 stw zero,68(r2) + 1005b54: d8801617 ldw r2,88(sp) + 1005b58: 11401117 ldw r5,68(r2) + 1005b5c: 1009883a mov r4,r2 + 1005b60: 10086cc0 call 10086cc <_Balloc> + 1005b64: d8c01617 ldw r3,88(sp) + 1005b68: d8800515 stw r2,20(sp) + 1005b6c: 18801015 stw r2,64(r3) + 1005b70: 00800384 movi r2,14 + 1005b74: 14006836 bltu r2,r16,1005d18 <_dtoa_r+0x588> + 1005b78: 8805003a cmpeq r2,r17,zero + 1005b7c: 1000661e bne r2,zero,1005d18 <_dtoa_r+0x588> + 1005b80: d9000d17 ldw r4,52(sp) + 1005b84: 0102300e bge zero,r4,1006448 <_dtoa_r+0xcb8> + 1005b88: 208003cc andi r2,r4,15 + 1005b8c: 100490fa slli r2,r2,3 + 1005b90: 2025d13a srai r18,r4,4 + 1005b94: 00c040b4 movhi r3,258 + 1005b98: 18e3a004 addi r3,r3,-29056 + 1005b9c: 10c5883a add r2,r2,r3 + 1005ba0: 90c0040c andi r3,r18,16 + 1005ba4: 14000017 ldw r16,0(r2) + 1005ba8: 14400117 ldw r17,4(r2) + 1005bac: 18036a1e bne r3,zero,1006958 <_dtoa_r+0x11c8> + 1005bb0: 05800084 movi r22,2 + 1005bb4: 90001026 beq r18,zero,1005bf8 <_dtoa_r+0x468> + 1005bb8: 04c040b4 movhi r19,258 + 1005bbc: 9ce3d204 addi r19,r19,-28856 + 1005bc0: 9080004c andi r2,r18,1 + 1005bc4: 1005003a cmpeq r2,r2,zero + 1005bc8: 1000081e bne r2,zero,1005bec <_dtoa_r+0x45c> + 1005bcc: 99800017 ldw r6,0(r19) + 1005bd0: 99c00117 ldw r7,4(r19) + 1005bd4: 880b883a mov r5,r17 + 1005bd8: 8009883a mov r4,r16 + 1005bdc: 100aed00 call 100aed0 <__muldf3> + 1005be0: 1021883a mov r16,r2 + 1005be4: b5800044 addi r22,r22,1 + 1005be8: 1823883a mov r17,r3 + 1005bec: 9025d07a srai r18,r18,1 + 1005bf0: 9cc00204 addi r19,r19,8 + 1005bf4: 903ff21e bne r18,zero,1005bc0 <_dtoa_r+0x430> + 1005bf8: a80b883a mov r5,r21 + 1005bfc: a009883a mov r4,r20 + 1005c00: 880f883a mov r7,r17 + 1005c04: 800d883a mov r6,r16 + 1005c08: 100b2940 call 100b294 <__divdf3> + 1005c0c: 1029883a mov r20,r2 + 1005c10: 182b883a mov r21,r3 + 1005c14: d8c00c17 ldw r3,48(sp) + 1005c18: 1805003a cmpeq r2,r3,zero + 1005c1c: 1000081e bne r2,zero,1005c40 <_dtoa_r+0x4b0> + 1005c20: 0005883a mov r2,zero + 1005c24: 00cffc34 movhi r3,16368 + 1005c28: 180f883a mov r7,r3 + 1005c2c: a009883a mov r4,r20 + 1005c30: a80b883a mov r5,r21 + 1005c34: 100d883a mov r6,r2 + 1005c38: 100b70c0 call 100b70c <__ltdf2> + 1005c3c: 1003fe16 blt r2,zero,1006c38 <_dtoa_r+0x14a8> + 1005c40: b009883a mov r4,r22 + 1005c44: 100b7940 call 100b794 <__floatsidf> + 1005c48: 180b883a mov r5,r3 + 1005c4c: 1009883a mov r4,r2 + 1005c50: a00d883a mov r6,r20 + 1005c54: a80f883a mov r7,r21 + 1005c58: 100aed00 call 100aed0 <__muldf3> + 1005c5c: 0011883a mov r8,zero + 1005c60: 02500734 movhi r9,16412 + 1005c64: 1009883a mov r4,r2 + 1005c68: 180b883a mov r5,r3 + 1005c6c: 480f883a mov r7,r9 + 1005c70: 400d883a mov r6,r8 + 1005c74: 100ae5c0 call 100ae5c <__adddf3> + 1005c78: d9000f17 ldw r4,60(sp) + 1005c7c: 102d883a mov r22,r2 + 1005c80: 00bf3034 movhi r2,64704 + 1005c84: 18b9883a add fp,r3,r2 + 1005c88: e02f883a mov r23,fp + 1005c8c: 20028f1e bne r4,zero,10066cc <_dtoa_r+0xf3c> + 1005c90: 0005883a mov r2,zero + 1005c94: 00d00534 movhi r3,16404 + 1005c98: a009883a mov r4,r20 + 1005c9c: a80b883a mov r5,r21 + 1005ca0: 180f883a mov r7,r3 + 1005ca4: 100d883a mov r6,r2 + 1005ca8: 100addc0 call 100addc <__subdf3> + 1005cac: 1009883a mov r4,r2 + 1005cb0: e00f883a mov r7,fp + 1005cb4: 180b883a mov r5,r3 + 1005cb8: b00d883a mov r6,r22 + 1005cbc: 1025883a mov r18,r2 + 1005cc0: 1827883a mov r19,r3 + 1005cc4: 100b5fc0 call 100b5fc <__gtdf2> + 1005cc8: 00834f16 blt zero,r2,1006a08 <_dtoa_r+0x1278> + 1005ccc: e0e0003c xorhi r3,fp,32768 + 1005cd0: 9009883a mov r4,r18 + 1005cd4: 980b883a mov r5,r19 + 1005cd8: 180f883a mov r7,r3 + 1005cdc: b00d883a mov r6,r22 + 1005ce0: 100b70c0 call 100b70c <__ltdf2> + 1005ce4: 1000080e bge r2,zero,1005d08 <_dtoa_r+0x578> + 1005ce8: 0027883a mov r19,zero + 1005cec: 0025883a mov r18,zero + 1005cf0: d8802617 ldw r2,152(sp) + 1005cf4: df000517 ldw fp,20(sp) + 1005cf8: d8000615 stw zero,24(sp) + 1005cfc: 0084303a nor r2,zero,r2 + 1005d00: d8800d15 stw r2,52(sp) + 1005d04: 00019b06 br 1006374 <_dtoa_r+0xbe4> + 1005d08: d9801217 ldw r6,72(sp) + 1005d0c: d8801317 ldw r2,76(sp) + 1005d10: 3029883a mov r20,r6 + 1005d14: 102b883a mov r21,r2 + 1005d18: d8c00217 ldw r3,8(sp) + 1005d1c: 18008516 blt r3,zero,1005f34 <_dtoa_r+0x7a4> + 1005d20: d9000d17 ldw r4,52(sp) + 1005d24: 00800384 movi r2,14 + 1005d28: 11008216 blt r2,r4,1005f34 <_dtoa_r+0x7a4> + 1005d2c: 200490fa slli r2,r4,3 + 1005d30: d9802617 ldw r6,152(sp) + 1005d34: 00c040b4 movhi r3,258 + 1005d38: 18e3a004 addi r3,r3,-29056 + 1005d3c: 10c5883a add r2,r2,r3 + 1005d40: 14800017 ldw r18,0(r2) + 1005d44: 14c00117 ldw r19,4(r2) + 1005d48: 30031e16 blt r6,zero,10069c4 <_dtoa_r+0x1234> + 1005d4c: d9000517 ldw r4,20(sp) + 1005d50: d8c00f17 ldw r3,60(sp) + 1005d54: a823883a mov r17,r21 + 1005d58: a021883a mov r16,r20 + 1005d5c: 192b883a add r21,r3,r4 + 1005d60: 2039883a mov fp,r4 + 1005d64: 00000f06 br 1005da4 <_dtoa_r+0x614> + 1005d68: 0005883a mov r2,zero + 1005d6c: 00d00934 movhi r3,16420 + 1005d70: 5009883a mov r4,r10 + 1005d74: 580b883a mov r5,r11 + 1005d78: 180f883a mov r7,r3 + 1005d7c: 100d883a mov r6,r2 + 1005d80: 100aed00 call 100aed0 <__muldf3> + 1005d84: 180b883a mov r5,r3 + 1005d88: 000d883a mov r6,zero + 1005d8c: 000f883a mov r7,zero + 1005d90: 1009883a mov r4,r2 + 1005d94: 1021883a mov r16,r2 + 1005d98: 1823883a mov r17,r3 + 1005d9c: 100b5740 call 100b574 <__nedf2> + 1005da0: 10004526 beq r2,zero,1005eb8 <_dtoa_r+0x728> + 1005da4: 900d883a mov r6,r18 + 1005da8: 980f883a mov r7,r19 + 1005dac: 8009883a mov r4,r16 + 1005db0: 880b883a mov r5,r17 + 1005db4: 100b2940 call 100b294 <__divdf3> + 1005db8: 180b883a mov r5,r3 + 1005dbc: 1009883a mov r4,r2 + 1005dc0: 100b88c0 call 100b88c <__fixdfsi> + 1005dc4: 1009883a mov r4,r2 + 1005dc8: 1029883a mov r20,r2 + 1005dcc: 100b7940 call 100b794 <__floatsidf> + 1005dd0: 180f883a mov r7,r3 + 1005dd4: 9009883a mov r4,r18 + 1005dd8: 980b883a mov r5,r19 + 1005ddc: 100d883a mov r6,r2 + 1005de0: 100aed00 call 100aed0 <__muldf3> + 1005de4: 180f883a mov r7,r3 + 1005de8: 880b883a mov r5,r17 + 1005dec: 8009883a mov r4,r16 + 1005df0: 100d883a mov r6,r2 + 1005df4: 100addc0 call 100addc <__subdf3> + 1005df8: 1015883a mov r10,r2 + 1005dfc: a0800c04 addi r2,r20,48 + 1005e00: e0800005 stb r2,0(fp) + 1005e04: e7000044 addi fp,fp,1 + 1005e08: 1817883a mov r11,r3 + 1005e0c: e57fd61e bne fp,r21,1005d68 <_dtoa_r+0x5d8> + 1005e10: 500d883a mov r6,r10 + 1005e14: 180f883a mov r7,r3 + 1005e18: 5009883a mov r4,r10 + 1005e1c: 180b883a mov r5,r3 + 1005e20: 100ae5c0 call 100ae5c <__adddf3> + 1005e24: 100d883a mov r6,r2 + 1005e28: 9009883a mov r4,r18 + 1005e2c: 980b883a mov r5,r19 + 1005e30: 180f883a mov r7,r3 + 1005e34: 1021883a mov r16,r2 + 1005e38: 1823883a mov r17,r3 + 1005e3c: 100b70c0 call 100b70c <__ltdf2> + 1005e40: 10000816 blt r2,zero,1005e64 <_dtoa_r+0x6d4> + 1005e44: 980b883a mov r5,r19 + 1005e48: 800d883a mov r6,r16 + 1005e4c: 880f883a mov r7,r17 + 1005e50: 9009883a mov r4,r18 + 1005e54: 100b4ec0 call 100b4ec <__eqdf2> + 1005e58: 1000171e bne r2,zero,1005eb8 <_dtoa_r+0x728> + 1005e5c: a080004c andi r2,r20,1 + 1005e60: 10001526 beq r2,zero,1005eb8 <_dtoa_r+0x728> + 1005e64: d8800d17 ldw r2,52(sp) + 1005e68: d8800415 stw r2,16(sp) + 1005e6c: e009883a mov r4,fp + 1005e70: 213fffc4 addi r4,r4,-1 + 1005e74: 20c00007 ldb r3,0(r4) + 1005e78: 00800e44 movi r2,57 + 1005e7c: 1880081e bne r3,r2,1005ea0 <_dtoa_r+0x710> + 1005e80: d8800517 ldw r2,20(sp) + 1005e84: 113ffa1e bne r2,r4,1005e70 <_dtoa_r+0x6e0> + 1005e88: d8c00417 ldw r3,16(sp) + 1005e8c: d9800517 ldw r6,20(sp) + 1005e90: 00800c04 movi r2,48 + 1005e94: 18c00044 addi r3,r3,1 + 1005e98: d8c00415 stw r3,16(sp) + 1005e9c: 30800005 stb r2,0(r6) + 1005ea0: 20800003 ldbu r2,0(r4) + 1005ea4: d8c00417 ldw r3,16(sp) + 1005ea8: 27000044 addi fp,r4,1 + 1005eac: 10800044 addi r2,r2,1 + 1005eb0: d8c00d15 stw r3,52(sp) + 1005eb4: 20800005 stb r2,0(r4) + 1005eb8: d9001617 ldw r4,88(sp) + 1005ebc: d9400717 ldw r5,28(sp) + 1005ec0: 100814c0 call 100814c <_Bfree> + 1005ec4: e0000005 stb zero,0(fp) + 1005ec8: d9800d17 ldw r6,52(sp) + 1005ecc: d8c02717 ldw r3,156(sp) + 1005ed0: d9002917 ldw r4,164(sp) + 1005ed4: 30800044 addi r2,r6,1 + 1005ed8: 18800015 stw r2,0(r3) + 1005edc: 20029c26 beq r4,zero,1006950 <_dtoa_r+0x11c0> + 1005ee0: d8c00517 ldw r3,20(sp) + 1005ee4: 27000015 stw fp,0(r4) + 1005ee8: 003e5d06 br 1005860 <_dtoa_r+0xd0> + 1005eec: d9800d17 ldw r6,52(sp) + 1005ef0: 00c040b4 movhi r3,258 + 1005ef4: 18e3a004 addi r3,r3,-29056 + 1005ef8: d9001217 ldw r4,72(sp) + 1005efc: 300490fa slli r2,r6,3 + 1005f00: d9401317 ldw r5,76(sp) + 1005f04: 10c5883a add r2,r2,r3 + 1005f08: 12000017 ldw r8,0(r2) + 1005f0c: 12400117 ldw r9,4(r2) + 1005f10: 400d883a mov r6,r8 + 1005f14: 480f883a mov r7,r9 + 1005f18: 100b70c0 call 100b70c <__ltdf2> + 1005f1c: 1000030e bge r2,zero,1005f2c <_dtoa_r+0x79c> + 1005f20: d8800d17 ldw r2,52(sp) + 1005f24: 10bfffc4 addi r2,r2,-1 + 1005f28: d8800d15 stw r2,52(sp) + 1005f2c: d8000c15 stw zero,48(sp) + 1005f30: 003ea806 br 10059d4 <_dtoa_r+0x244> + 1005f34: d9000b17 ldw r4,44(sp) + 1005f38: 202cc03a cmpne r22,r4,zero + 1005f3c: b000c71e bne r22,zero,100625c <_dtoa_r+0xacc> + 1005f40: dc001117 ldw r16,68(sp) + 1005f44: dc801017 ldw r18,64(sp) + 1005f48: 0027883a mov r19,zero + 1005f4c: 04000b0e bge zero,r16,1005f7c <_dtoa_r+0x7ec> + 1005f50: d8c00a17 ldw r3,40(sp) + 1005f54: 00c0090e bge zero,r3,1005f7c <_dtoa_r+0x7ec> + 1005f58: 8005883a mov r2,r16 + 1005f5c: 1c011316 blt r3,r16,10063ac <_dtoa_r+0xc1c> + 1005f60: d9000a17 ldw r4,40(sp) + 1005f64: d9801117 ldw r6,68(sp) + 1005f68: 80a1c83a sub r16,r16,r2 + 1005f6c: 2089c83a sub r4,r4,r2 + 1005f70: 308dc83a sub r6,r6,r2 + 1005f74: d9000a15 stw r4,40(sp) + 1005f78: d9801115 stw r6,68(sp) + 1005f7c: d8801017 ldw r2,64(sp) + 1005f80: 0080150e bge zero,r2,1005fd8 <_dtoa_r+0x848> + 1005f84: d8c00b17 ldw r3,44(sp) + 1005f88: 1805003a cmpeq r2,r3,zero + 1005f8c: 1001c91e bne r2,zero,10066b4 <_dtoa_r+0xf24> + 1005f90: 04800e0e bge zero,r18,1005fcc <_dtoa_r+0x83c> + 1005f94: d9001617 ldw r4,88(sp) + 1005f98: 980b883a mov r5,r19 + 1005f9c: 900d883a mov r6,r18 + 1005fa0: 1008f000 call 1008f00 <__pow5mult> + 1005fa4: d9001617 ldw r4,88(sp) + 1005fa8: d9800717 ldw r6,28(sp) + 1005fac: 100b883a mov r5,r2 + 1005fb0: 1027883a mov r19,r2 + 1005fb4: 1008bdc0 call 1008bdc <__multiply> + 1005fb8: d9001617 ldw r4,88(sp) + 1005fbc: d9400717 ldw r5,28(sp) + 1005fc0: 1023883a mov r17,r2 + 1005fc4: 100814c0 call 100814c <_Bfree> + 1005fc8: dc400715 stw r17,28(sp) + 1005fcc: d9001017 ldw r4,64(sp) + 1005fd0: 248dc83a sub r6,r4,r18 + 1005fd4: 30010e1e bne r6,zero,1006410 <_dtoa_r+0xc80> + 1005fd8: d9001617 ldw r4,88(sp) + 1005fdc: 04400044 movi r17,1 + 1005fe0: 880b883a mov r5,r17 + 1005fe4: 1008dc40 call 1008dc4 <__i2b> + 1005fe8: d9800917 ldw r6,36(sp) + 1005fec: 1025883a mov r18,r2 + 1005ff0: 0180040e bge zero,r6,1006004 <_dtoa_r+0x874> + 1005ff4: d9001617 ldw r4,88(sp) + 1005ff8: 100b883a mov r5,r2 + 1005ffc: 1008f000 call 1008f00 <__pow5mult> + 1006000: 1025883a mov r18,r2 + 1006004: d8801717 ldw r2,92(sp) + 1006008: 8880f30e bge r17,r2,10063d8 <_dtoa_r+0xc48> + 100600c: 0023883a mov r17,zero + 1006010: d9800917 ldw r6,36(sp) + 1006014: 30019e1e bne r6,zero,1006690 <_dtoa_r+0xf00> + 1006018: 00c00044 movi r3,1 + 100601c: d9000a17 ldw r4,40(sp) + 1006020: 20c5883a add r2,r4,r3 + 1006024: 10c007cc andi r3,r2,31 + 1006028: 1800841e bne r3,zero,100623c <_dtoa_r+0xaac> + 100602c: 00800704 movi r2,28 + 1006030: d9000a17 ldw r4,40(sp) + 1006034: d9801117 ldw r6,68(sp) + 1006038: 80a1883a add r16,r16,r2 + 100603c: 2089883a add r4,r4,r2 + 1006040: 308d883a add r6,r6,r2 + 1006044: d9000a15 stw r4,40(sp) + 1006048: d9801115 stw r6,68(sp) + 100604c: d8801117 ldw r2,68(sp) + 1006050: 0080050e bge zero,r2,1006068 <_dtoa_r+0x8d8> + 1006054: d9400717 ldw r5,28(sp) + 1006058: d9001617 ldw r4,88(sp) + 100605c: 100d883a mov r6,r2 + 1006060: 1008a900 call 1008a90 <__lshift> + 1006064: d8800715 stw r2,28(sp) + 1006068: d8c00a17 ldw r3,40(sp) + 100606c: 00c0050e bge zero,r3,1006084 <_dtoa_r+0x8f4> + 1006070: d9001617 ldw r4,88(sp) + 1006074: 900b883a mov r5,r18 + 1006078: 180d883a mov r6,r3 + 100607c: 1008a900 call 1008a90 <__lshift> + 1006080: 1025883a mov r18,r2 + 1006084: d9000c17 ldw r4,48(sp) + 1006088: 2005003a cmpeq r2,r4,zero + 100608c: 10016f26 beq r2,zero,100664c <_dtoa_r+0xebc> + 1006090: d9000f17 ldw r4,60(sp) + 1006094: 0102170e bge zero,r4,10068f4 <_dtoa_r+0x1164> + 1006098: d9800b17 ldw r6,44(sp) + 100609c: 3005003a cmpeq r2,r6,zero + 10060a0: 1000881e bne r2,zero,10062c4 <_dtoa_r+0xb34> + 10060a4: 0400050e bge zero,r16,10060bc <_dtoa_r+0x92c> + 10060a8: d9001617 ldw r4,88(sp) + 10060ac: 980b883a mov r5,r19 + 10060b0: 800d883a mov r6,r16 + 10060b4: 1008a900 call 1008a90 <__lshift> + 10060b8: 1027883a mov r19,r2 + 10060bc: 8804c03a cmpne r2,r17,zero + 10060c0: 1002541e bne r2,zero,1006a14 <_dtoa_r+0x1284> + 10060c4: 980b883a mov r5,r19 + 10060c8: dd800517 ldw r22,20(sp) + 10060cc: dcc00615 stw r19,24(sp) + 10060d0: a700004c andi fp,r20,1 + 10060d4: 2827883a mov r19,r5 + 10060d8: d9000717 ldw r4,28(sp) + 10060dc: 900b883a mov r5,r18 + 10060e0: 10055780 call 1005578 + 10060e4: d9000717 ldw r4,28(sp) + 10060e8: d9400617 ldw r5,24(sp) + 10060ec: 1023883a mov r17,r2 + 10060f0: 8dc00c04 addi r23,r17,48 + 10060f4: 10082a80 call 10082a8 <__mcmp> + 10060f8: d9001617 ldw r4,88(sp) + 10060fc: 900b883a mov r5,r18 + 1006100: 980d883a mov r6,r19 + 1006104: 1029883a mov r20,r2 + 1006108: 10089040 call 1008904 <__mdiff> + 100610c: 102b883a mov r21,r2 + 1006110: 10800317 ldw r2,12(r2) + 1006114: 1001281e bne r2,zero,10065b8 <_dtoa_r+0xe28> + 1006118: d9000717 ldw r4,28(sp) + 100611c: a80b883a mov r5,r21 + 1006120: 10082a80 call 10082a8 <__mcmp> + 1006124: d9001617 ldw r4,88(sp) + 1006128: 1021883a mov r16,r2 + 100612c: a80b883a mov r5,r21 + 1006130: 100814c0 call 100814c <_Bfree> + 1006134: 8000041e bne r16,zero,1006148 <_dtoa_r+0x9b8> + 1006138: d8801717 ldw r2,92(sp) + 100613c: 1000021e bne r2,zero,1006148 <_dtoa_r+0x9b8> + 1006140: e004c03a cmpne r2,fp,zero + 1006144: 10011726 beq r2,zero,10065a4 <_dtoa_r+0xe14> + 1006148: a0010616 blt r20,zero,1006564 <_dtoa_r+0xdd4> + 100614c: a000041e bne r20,zero,1006160 <_dtoa_r+0x9d0> + 1006150: d8c01717 ldw r3,92(sp) + 1006154: 1800021e bne r3,zero,1006160 <_dtoa_r+0x9d0> + 1006158: e004c03a cmpne r2,fp,zero + 100615c: 10010126 beq r2,zero,1006564 <_dtoa_r+0xdd4> + 1006160: 04023d16 blt zero,r16,1006a58 <_dtoa_r+0x12c8> + 1006164: b5c00005 stb r23,0(r22) + 1006168: d9800517 ldw r6,20(sp) + 100616c: d9000f17 ldw r4,60(sp) + 1006170: b5800044 addi r22,r22,1 + 1006174: 3105883a add r2,r6,r4 + 1006178: b0806526 beq r22,r2,1006310 <_dtoa_r+0xb80> + 100617c: d9400717 ldw r5,28(sp) + 1006180: d9001617 ldw r4,88(sp) + 1006184: 01800284 movi r6,10 + 1006188: 000f883a mov r7,zero + 100618c: 1008e000 call 1008e00 <__multadd> + 1006190: d8800715 stw r2,28(sp) + 1006194: d8800617 ldw r2,24(sp) + 1006198: 14c10c26 beq r2,r19,10065cc <_dtoa_r+0xe3c> + 100619c: d9400617 ldw r5,24(sp) + 10061a0: d9001617 ldw r4,88(sp) + 10061a4: 01800284 movi r6,10 + 10061a8: 000f883a mov r7,zero + 10061ac: 1008e000 call 1008e00 <__multadd> + 10061b0: d9001617 ldw r4,88(sp) + 10061b4: 980b883a mov r5,r19 + 10061b8: 01800284 movi r6,10 + 10061bc: 000f883a mov r7,zero + 10061c0: d8800615 stw r2,24(sp) + 10061c4: 1008e000 call 1008e00 <__multadd> + 10061c8: 1027883a mov r19,r2 + 10061cc: 003fc206 br 10060d8 <_dtoa_r+0x948> + 10061d0: 2445c83a sub r2,r4,r17 + 10061d4: a088983a sll r4,r20,r2 + 10061d8: 003e4b06 br 1005b08 <_dtoa_r+0x378> + 10061dc: 01bfffc4 movi r6,-1 + 10061e0: 00800044 movi r2,1 + 10061e4: d9800e15 stw r6,56(sp) + 10061e8: d9800f15 stw r6,60(sp) + 10061ec: d8800b15 stw r2,44(sp) + 10061f0: d8c01617 ldw r3,88(sp) + 10061f4: 008005c4 movi r2,23 + 10061f8: 18001115 stw zero,68(r3) + 10061fc: 1580082e bgeu r2,r22,1006220 <_dtoa_r+0xa90> + 1006200: 00c00104 movi r3,4 + 1006204: 0009883a mov r4,zero + 1006208: 18c7883a add r3,r3,r3 + 100620c: 18800504 addi r2,r3,20 + 1006210: 21000044 addi r4,r4,1 + 1006214: b0bffc2e bgeu r22,r2,1006208 <_dtoa_r+0xa78> + 1006218: d9801617 ldw r6,88(sp) + 100621c: 31001115 stw r4,68(r6) + 1006220: dc000f17 ldw r16,60(sp) + 1006224: 003e4b06 br 1005b54 <_dtoa_r+0x3c4> + 1006228: d9801717 ldw r6,92(sp) + 100622c: 0023883a mov r17,zero + 1006230: 31bfff04 addi r6,r6,-4 + 1006234: d9801715 stw r6,92(sp) + 1006238: 003df806 br 1005a1c <_dtoa_r+0x28c> + 100623c: 00800804 movi r2,32 + 1006240: 10c9c83a sub r4,r2,r3 + 1006244: 00c00104 movi r3,4 + 1006248: 19005a16 blt r3,r4,10063b4 <_dtoa_r+0xc24> + 100624c: 008000c4 movi r2,3 + 1006250: 113f7e16 blt r2,r4,100604c <_dtoa_r+0x8bc> + 1006254: 20800704 addi r2,r4,28 + 1006258: 003f7506 br 1006030 <_dtoa_r+0x8a0> + 100625c: d9801717 ldw r6,92(sp) + 1006260: 00800044 movi r2,1 + 1006264: 1180a10e bge r2,r6,10064ec <_dtoa_r+0xd5c> + 1006268: d9800f17 ldw r6,60(sp) + 100626c: d8c01017 ldw r3,64(sp) + 1006270: 30bfffc4 addi r2,r6,-1 + 1006274: 1881c616 blt r3,r2,1006990 <_dtoa_r+0x1200> + 1006278: 18a5c83a sub r18,r3,r2 + 100627c: d8800f17 ldw r2,60(sp) + 1006280: 10026216 blt r2,zero,1006c0c <_dtoa_r+0x147c> + 1006284: dc001117 ldw r16,68(sp) + 1006288: 1007883a mov r3,r2 + 100628c: d9800a17 ldw r6,40(sp) + 1006290: d8801117 ldw r2,68(sp) + 1006294: d9001617 ldw r4,88(sp) + 1006298: 30cd883a add r6,r6,r3 + 100629c: 10c5883a add r2,r2,r3 + 10062a0: 01400044 movi r5,1 + 10062a4: d9800a15 stw r6,40(sp) + 10062a8: d8801115 stw r2,68(sp) + 10062ac: 1008dc40 call 1008dc4 <__i2b> + 10062b0: 1027883a mov r19,r2 + 10062b4: 003f2506 br 1005f4c <_dtoa_r+0x7bc> + 10062b8: 00c040b4 movhi r3,258 + 10062bc: 18e38204 addi r3,r3,-29176 + 10062c0: 003d6706 br 1005860 <_dtoa_r+0xd0> + 10062c4: dd800517 ldw r22,20(sp) + 10062c8: 04000044 movi r16,1 + 10062cc: 00000706 br 10062ec <_dtoa_r+0xb5c> + 10062d0: d9400717 ldw r5,28(sp) + 10062d4: d9001617 ldw r4,88(sp) + 10062d8: 01800284 movi r6,10 + 10062dc: 000f883a mov r7,zero + 10062e0: 1008e000 call 1008e00 <__multadd> + 10062e4: d8800715 stw r2,28(sp) + 10062e8: 84000044 addi r16,r16,1 + 10062ec: d9000717 ldw r4,28(sp) + 10062f0: 900b883a mov r5,r18 + 10062f4: 10055780 call 1005578 + 10062f8: 15c00c04 addi r23,r2,48 + 10062fc: b5c00005 stb r23,0(r22) + 1006300: d8c00f17 ldw r3,60(sp) + 1006304: b5800044 addi r22,r22,1 + 1006308: 80fff116 blt r16,r3,10062d0 <_dtoa_r+0xb40> + 100630c: d8000615 stw zero,24(sp) + 1006310: d9400717 ldw r5,28(sp) + 1006314: d9001617 ldw r4,88(sp) + 1006318: 01800044 movi r6,1 + 100631c: 1008a900 call 1008a90 <__lshift> + 1006320: 1009883a mov r4,r2 + 1006324: 900b883a mov r5,r18 + 1006328: d8800715 stw r2,28(sp) + 100632c: 10082a80 call 10082a8 <__mcmp> + 1006330: 00803c0e bge zero,r2,1006424 <_dtoa_r+0xc94> + 1006334: b009883a mov r4,r22 + 1006338: 213fffc4 addi r4,r4,-1 + 100633c: 21400003 ldbu r5,0(r4) + 1006340: 00800e44 movi r2,57 + 1006344: 28c03fcc andi r3,r5,255 + 1006348: 18c0201c xori r3,r3,128 + 100634c: 18ffe004 addi r3,r3,-128 + 1006350: 1881981e bne r3,r2,10069b4 <_dtoa_r+0x1224> + 1006354: d9800517 ldw r6,20(sp) + 1006358: 21bff71e bne r4,r6,1006338 <_dtoa_r+0xba8> + 100635c: d8800d17 ldw r2,52(sp) + 1006360: 37000044 addi fp,r6,1 + 1006364: 10800044 addi r2,r2,1 + 1006368: d8800d15 stw r2,52(sp) + 100636c: 00800c44 movi r2,49 + 1006370: 30800005 stb r2,0(r6) + 1006374: d9001617 ldw r4,88(sp) + 1006378: 900b883a mov r5,r18 + 100637c: 100814c0 call 100814c <_Bfree> + 1006380: 983ecd26 beq r19,zero,1005eb8 <_dtoa_r+0x728> + 1006384: d8c00617 ldw r3,24(sp) + 1006388: 18000426 beq r3,zero,100639c <_dtoa_r+0xc0c> + 100638c: 1cc00326 beq r3,r19,100639c <_dtoa_r+0xc0c> + 1006390: d9001617 ldw r4,88(sp) + 1006394: 180b883a mov r5,r3 + 1006398: 100814c0 call 100814c <_Bfree> + 100639c: d9001617 ldw r4,88(sp) + 10063a0: 980b883a mov r5,r19 + 10063a4: 100814c0 call 100814c <_Bfree> + 10063a8: 003ec306 br 1005eb8 <_dtoa_r+0x728> + 10063ac: 1805883a mov r2,r3 + 10063b0: 003eeb06 br 1005f60 <_dtoa_r+0x7d0> + 10063b4: d9800a17 ldw r6,40(sp) + 10063b8: d8c01117 ldw r3,68(sp) + 10063bc: 20bfff04 addi r2,r4,-4 + 10063c0: 308d883a add r6,r6,r2 + 10063c4: 1887883a add r3,r3,r2 + 10063c8: 80a1883a add r16,r16,r2 + 10063cc: d9800a15 stw r6,40(sp) + 10063d0: d8c01115 stw r3,68(sp) + 10063d4: 003f1d06 br 100604c <_dtoa_r+0x8bc> + 10063d8: a03f0c1e bne r20,zero,100600c <_dtoa_r+0x87c> + 10063dc: 00800434 movhi r2,16 + 10063e0: 10bfffc4 addi r2,r2,-1 + 10063e4: a884703a and r2,r21,r2 + 10063e8: 103f081e bne r2,zero,100600c <_dtoa_r+0x87c> + 10063ec: a89ffc2c andhi r2,r21,32752 + 10063f0: 103f0626 beq r2,zero,100600c <_dtoa_r+0x87c> + 10063f4: d8c01117 ldw r3,68(sp) + 10063f8: d9000a17 ldw r4,40(sp) + 10063fc: 18c00044 addi r3,r3,1 + 1006400: 21000044 addi r4,r4,1 + 1006404: d8c01115 stw r3,68(sp) + 1006408: d9000a15 stw r4,40(sp) + 100640c: 003f0006 br 1006010 <_dtoa_r+0x880> + 1006410: d9400717 ldw r5,28(sp) + 1006414: d9001617 ldw r4,88(sp) + 1006418: 1008f000 call 1008f00 <__pow5mult> + 100641c: d8800715 stw r2,28(sp) + 1006420: 003eed06 br 1005fd8 <_dtoa_r+0x848> + 1006424: 1000021e bne r2,zero,1006430 <_dtoa_r+0xca0> + 1006428: b880004c andi r2,r23,1 + 100642c: 103fc11e bne r2,zero,1006334 <_dtoa_r+0xba4> + 1006430: b5bfffc4 addi r22,r22,-1 + 1006434: b0c00007 ldb r3,0(r22) + 1006438: 00800c04 movi r2,48 + 100643c: 18bffc26 beq r3,r2,1006430 <_dtoa_r+0xca0> + 1006440: b7000044 addi fp,r22,1 + 1006444: 003fcb06 br 1006374 <_dtoa_r+0xbe4> + 1006448: d9800d17 ldw r6,52(sp) + 100644c: 018fc83a sub r7,zero,r6 + 1006450: 3801f726 beq r7,zero,1006c30 <_dtoa_r+0x14a0> + 1006454: 398003cc andi r6,r7,15 + 1006458: 300c90fa slli r6,r6,3 + 100645c: 014040b4 movhi r5,258 + 1006460: 2963a004 addi r5,r5,-29056 + 1006464: d9001217 ldw r4,72(sp) + 1006468: 314d883a add r6,r6,r5 + 100646c: 30c00117 ldw r3,4(r6) + 1006470: 30800017 ldw r2,0(r6) + 1006474: d9401317 ldw r5,76(sp) + 1006478: 3821d13a srai r16,r7,4 + 100647c: 100d883a mov r6,r2 + 1006480: 180f883a mov r7,r3 + 1006484: 100aed00 call 100aed0 <__muldf3> + 1006488: 1011883a mov r8,r2 + 100648c: 1813883a mov r9,r3 + 1006490: 1029883a mov r20,r2 + 1006494: 182b883a mov r21,r3 + 1006498: 8001e526 beq r16,zero,1006c30 <_dtoa_r+0x14a0> + 100649c: 05800084 movi r22,2 + 10064a0: 044040b4 movhi r17,258 + 10064a4: 8c63d204 addi r17,r17,-28856 + 10064a8: 8080004c andi r2,r16,1 + 10064ac: 1005003a cmpeq r2,r2,zero + 10064b0: 1000081e bne r2,zero,10064d4 <_dtoa_r+0xd44> + 10064b4: 89800017 ldw r6,0(r17) + 10064b8: 89c00117 ldw r7,4(r17) + 10064bc: 480b883a mov r5,r9 + 10064c0: 4009883a mov r4,r8 + 10064c4: 100aed00 call 100aed0 <__muldf3> + 10064c8: 1011883a mov r8,r2 + 10064cc: b5800044 addi r22,r22,1 + 10064d0: 1813883a mov r9,r3 + 10064d4: 8021d07a srai r16,r16,1 + 10064d8: 8c400204 addi r17,r17,8 + 10064dc: 803ff21e bne r16,zero,10064a8 <_dtoa_r+0xd18> + 10064e0: 4029883a mov r20,r8 + 10064e4: 482b883a mov r21,r9 + 10064e8: 003dca06 br 1005c14 <_dtoa_r+0x484> + 10064ec: d9000817 ldw r4,32(sp) + 10064f0: 2005003a cmpeq r2,r4,zero + 10064f4: 1001f61e bne r2,zero,1006cd0 <_dtoa_r+0x1540> + 10064f8: dc001117 ldw r16,68(sp) + 10064fc: dc801017 ldw r18,64(sp) + 1006500: 18c10cc4 addi r3,r3,1075 + 1006504: 003f6106 br 100628c <_dtoa_r+0xafc> + 1006508: d8000b15 stw zero,44(sp) + 100650c: d9802617 ldw r6,152(sp) + 1006510: d8c00d17 ldw r3,52(sp) + 1006514: 30800044 addi r2,r6,1 + 1006518: 18ad883a add r22,r3,r2 + 100651c: b13fffc4 addi r4,r22,-1 + 1006520: d9000e15 stw r4,56(sp) + 1006524: 0581f60e bge zero,r22,1006d00 <_dtoa_r+0x1570> + 1006528: dd800f15 stw r22,60(sp) + 100652c: 003f3006 br 10061f0 <_dtoa_r+0xa60> + 1006530: d8000b15 stw zero,44(sp) + 1006534: d9002617 ldw r4,152(sp) + 1006538: 0101eb0e bge zero,r4,1006ce8 <_dtoa_r+0x1558> + 100653c: 202d883a mov r22,r4 + 1006540: d9000e15 stw r4,56(sp) + 1006544: d9000f15 stw r4,60(sp) + 1006548: 003f2906 br 10061f0 <_dtoa_r+0xa60> + 100654c: 01800044 movi r6,1 + 1006550: d9800b15 stw r6,44(sp) + 1006554: 003ff706 br 1006534 <_dtoa_r+0xda4> + 1006558: 01000044 movi r4,1 + 100655c: d9000b15 stw r4,44(sp) + 1006560: 003fea06 br 100650c <_dtoa_r+0xd7c> + 1006564: 04000c0e bge zero,r16,1006598 <_dtoa_r+0xe08> + 1006568: d9400717 ldw r5,28(sp) + 100656c: d9001617 ldw r4,88(sp) + 1006570: 01800044 movi r6,1 + 1006574: 1008a900 call 1008a90 <__lshift> + 1006578: 1009883a mov r4,r2 + 100657c: 900b883a mov r5,r18 + 1006580: d8800715 stw r2,28(sp) + 1006584: 10082a80 call 10082a8 <__mcmp> + 1006588: 0081e00e bge zero,r2,1006d0c <_dtoa_r+0x157c> + 100658c: bdc00044 addi r23,r23,1 + 1006590: 00800e84 movi r2,58 + 1006594: b881a226 beq r23,r2,1006c20 <_dtoa_r+0x1490> + 1006598: b7000044 addi fp,r22,1 + 100659c: b5c00005 stb r23,0(r22) + 10065a0: 003f7406 br 1006374 <_dtoa_r+0xbe4> + 10065a4: 00800e44 movi r2,57 + 10065a8: b8819d26 beq r23,r2,1006c20 <_dtoa_r+0x1490> + 10065ac: 053ffa0e bge zero,r20,1006598 <_dtoa_r+0xe08> + 10065b0: 8dc00c44 addi r23,r17,49 + 10065b4: 003ff806 br 1006598 <_dtoa_r+0xe08> + 10065b8: d9001617 ldw r4,88(sp) + 10065bc: a80b883a mov r5,r21 + 10065c0: 04000044 movi r16,1 + 10065c4: 100814c0 call 100814c <_Bfree> + 10065c8: 003edf06 br 1006148 <_dtoa_r+0x9b8> + 10065cc: d9001617 ldw r4,88(sp) + 10065d0: 980b883a mov r5,r19 + 10065d4: 01800284 movi r6,10 + 10065d8: 000f883a mov r7,zero + 10065dc: 1008e000 call 1008e00 <__multadd> + 10065e0: 1027883a mov r19,r2 + 10065e4: d8800615 stw r2,24(sp) + 10065e8: 003ebb06 br 10060d8 <_dtoa_r+0x948> + 10065ec: d9801117 ldw r6,68(sp) + 10065f0: d8800d17 ldw r2,52(sp) + 10065f4: d8000915 stw zero,36(sp) + 10065f8: 308dc83a sub r6,r6,r2 + 10065fc: 0087c83a sub r3,zero,r2 + 1006600: d9801115 stw r6,68(sp) + 1006604: d8c01015 stw r3,64(sp) + 1006608: 003cfe06 br 1005a04 <_dtoa_r+0x274> + 100660c: 018dc83a sub r6,zero,r6 + 1006610: d9801115 stw r6,68(sp) + 1006614: d8000a15 stw zero,40(sp) + 1006618: 003cf306 br 10059e8 <_dtoa_r+0x258> + 100661c: d9000d17 ldw r4,52(sp) + 1006620: 100b7940 call 100b794 <__floatsidf> + 1006624: 880b883a mov r5,r17 + 1006628: 8009883a mov r4,r16 + 100662c: 180f883a mov r7,r3 + 1006630: 100d883a mov r6,r2 + 1006634: 100b5740 call 100b574 <__nedf2> + 1006638: 103ce126 beq r2,zero,10059c0 <_dtoa_r+0x230> + 100663c: d9800d17 ldw r6,52(sp) + 1006640: 31bfffc4 addi r6,r6,-1 + 1006644: d9800d15 stw r6,52(sp) + 1006648: 003cdd06 br 10059c0 <_dtoa_r+0x230> + 100664c: d9000717 ldw r4,28(sp) + 1006650: 900b883a mov r5,r18 + 1006654: 10082a80 call 10082a8 <__mcmp> + 1006658: 103e8d0e bge r2,zero,1006090 <_dtoa_r+0x900> + 100665c: d9400717 ldw r5,28(sp) + 1006660: d9001617 ldw r4,88(sp) + 1006664: 01800284 movi r6,10 + 1006668: 000f883a mov r7,zero + 100666c: 1008e000 call 1008e00 <__multadd> + 1006670: d9800d17 ldw r6,52(sp) + 1006674: d8800715 stw r2,28(sp) + 1006678: 31bfffc4 addi r6,r6,-1 + 100667c: d9800d15 stw r6,52(sp) + 1006680: b001a71e bne r22,zero,1006d20 <_dtoa_r+0x1590> + 1006684: d8800e17 ldw r2,56(sp) + 1006688: d8800f15 stw r2,60(sp) + 100668c: 003e8006 br 1006090 <_dtoa_r+0x900> + 1006690: 90800417 ldw r2,16(r18) + 1006694: 1085883a add r2,r2,r2 + 1006698: 1085883a add r2,r2,r2 + 100669c: 1485883a add r2,r2,r18 + 10066a0: 11000417 ldw r4,16(r2) + 10066a4: 10081740 call 1008174 <__hi0bits> + 10066a8: 00c00804 movi r3,32 + 10066ac: 1887c83a sub r3,r3,r2 + 10066b0: 003e5a06 br 100601c <_dtoa_r+0x88c> + 10066b4: d9400717 ldw r5,28(sp) + 10066b8: d9801017 ldw r6,64(sp) + 10066bc: d9001617 ldw r4,88(sp) + 10066c0: 1008f000 call 1008f00 <__pow5mult> + 10066c4: d8800715 stw r2,28(sp) + 10066c8: 003e4306 br 1005fd8 <_dtoa_r+0x848> + 10066cc: d9800f17 ldw r6,60(sp) + 10066d0: d8800d17 ldw r2,52(sp) + 10066d4: d9800315 stw r6,12(sp) + 10066d8: d8800415 stw r2,16(sp) + 10066dc: d8c00b17 ldw r3,44(sp) + 10066e0: 1805003a cmpeq r2,r3,zero + 10066e4: 1000e21e bne r2,zero,1006a70 <_dtoa_r+0x12e0> + 10066e8: d9000317 ldw r4,12(sp) + 10066ec: 0005883a mov r2,zero + 10066f0: 00cff834 movhi r3,16352 + 10066f4: 200c90fa slli r6,r4,3 + 10066f8: 010040b4 movhi r4,258 + 10066fc: 2123a004 addi r4,r4,-29056 + 1006700: 180b883a mov r5,r3 + 1006704: 310d883a add r6,r6,r4 + 1006708: 327fff17 ldw r9,-4(r6) + 100670c: 323ffe17 ldw r8,-8(r6) + 1006710: 1009883a mov r4,r2 + 1006714: 480f883a mov r7,r9 + 1006718: 400d883a mov r6,r8 + 100671c: 100b2940 call 100b294 <__divdf3> + 1006720: 180b883a mov r5,r3 + 1006724: b00d883a mov r6,r22 + 1006728: b80f883a mov r7,r23 + 100672c: 1009883a mov r4,r2 + 1006730: 100addc0 call 100addc <__subdf3> + 1006734: a80b883a mov r5,r21 + 1006738: a009883a mov r4,r20 + 100673c: d8c01915 stw r3,100(sp) + 1006740: d8801815 stw r2,96(sp) + 1006744: 100b88c0 call 100b88c <__fixdfsi> + 1006748: 1009883a mov r4,r2 + 100674c: 1027883a mov r19,r2 + 1006750: 100b7940 call 100b794 <__floatsidf> + 1006754: a80b883a mov r5,r21 + 1006758: a009883a mov r4,r20 + 100675c: 180f883a mov r7,r3 + 1006760: 100d883a mov r6,r2 + 1006764: 100addc0 call 100addc <__subdf3> + 1006768: d9801817 ldw r6,96(sp) + 100676c: 1823883a mov r17,r3 + 1006770: d8801415 stw r2,80(sp) + 1006774: 302d883a mov r22,r6 + 1006778: d9800517 ldw r6,20(sp) + 100677c: 9cc00c04 addi r19,r19,48 + 1006780: dc401515 stw r17,84(sp) + 1006784: d8c01917 ldw r3,100(sp) + 1006788: 34c00005 stb r19,0(r6) + 100678c: d8800517 ldw r2,20(sp) + 1006790: d9401917 ldw r5,100(sp) + 1006794: d9801417 ldw r6,80(sp) + 1006798: b009883a mov r4,r22 + 100679c: 880f883a mov r7,r17 + 10067a0: 182f883a mov r23,r3 + 10067a4: 17000044 addi fp,r2,1 + 10067a8: 100b5fc0 call 100b5fc <__gtdf2> + 10067ac: 00804e16 blt zero,r2,10068e8 <_dtoa_r+0x1158> + 10067b0: d9801417 ldw r6,80(sp) + 10067b4: 0005883a mov r2,zero + 10067b8: 00cffc34 movhi r3,16368 + 10067bc: 180b883a mov r5,r3 + 10067c0: 880f883a mov r7,r17 + 10067c4: 1009883a mov r4,r2 + 10067c8: 100addc0 call 100addc <__subdf3> + 10067cc: d9401917 ldw r5,100(sp) + 10067d0: 180f883a mov r7,r3 + 10067d4: b009883a mov r4,r22 + 10067d8: 100d883a mov r6,r2 + 10067dc: 100b5fc0 call 100b5fc <__gtdf2> + 10067e0: 00bda216 blt zero,r2,1005e6c <_dtoa_r+0x6dc> + 10067e4: d8c00317 ldw r3,12(sp) + 10067e8: 00800044 movi r2,1 + 10067ec: 10c01216 blt r2,r3,1006838 <_dtoa_r+0x10a8> + 10067f0: 003d4506 br 1005d08 <_dtoa_r+0x578> + 10067f4: d9801417 ldw r6,80(sp) + 10067f8: 0005883a mov r2,zero + 10067fc: 00cffc34 movhi r3,16368 + 1006800: 180b883a mov r5,r3 + 1006804: 880f883a mov r7,r17 + 1006808: 1009883a mov r4,r2 + 100680c: 100addc0 call 100addc <__subdf3> + 1006810: d9c01b17 ldw r7,108(sp) + 1006814: 180b883a mov r5,r3 + 1006818: 1009883a mov r4,r2 + 100681c: b00d883a mov r6,r22 + 1006820: 100b70c0 call 100b70c <__ltdf2> + 1006824: 103d9116 blt r2,zero,1005e6c <_dtoa_r+0x6dc> + 1006828: d9800517 ldw r6,20(sp) + 100682c: d9000317 ldw r4,12(sp) + 1006830: 3105883a add r2,r6,r4 + 1006834: e0bd3426 beq fp,r2,1005d08 <_dtoa_r+0x578> + 1006838: 04500934 movhi r17,16420 + 100683c: 0021883a mov r16,zero + 1006840: b80b883a mov r5,r23 + 1006844: b009883a mov r4,r22 + 1006848: 800d883a mov r6,r16 + 100684c: 880f883a mov r7,r17 + 1006850: 100aed00 call 100aed0 <__muldf3> + 1006854: d9401517 ldw r5,84(sp) + 1006858: d9001417 ldw r4,80(sp) + 100685c: 880f883a mov r7,r17 + 1006860: 000d883a mov r6,zero + 1006864: d8801a15 stw r2,104(sp) + 1006868: d8c01b15 stw r3,108(sp) + 100686c: 100aed00 call 100aed0 <__muldf3> + 1006870: 180b883a mov r5,r3 + 1006874: 1009883a mov r4,r2 + 1006878: 1823883a mov r17,r3 + 100687c: 1021883a mov r16,r2 + 1006880: 100b88c0 call 100b88c <__fixdfsi> + 1006884: 1009883a mov r4,r2 + 1006888: 102b883a mov r21,r2 + 100688c: 100b7940 call 100b794 <__floatsidf> + 1006890: 880b883a mov r5,r17 + 1006894: 8009883a mov r4,r16 + 1006898: 180f883a mov r7,r3 + 100689c: 100d883a mov r6,r2 + 10068a0: 100addc0 call 100addc <__subdf3> + 10068a4: 1021883a mov r16,r2 + 10068a8: d9001b17 ldw r4,108(sp) + 10068ac: 1823883a mov r17,r3 + 10068b0: dc001415 stw r16,80(sp) + 10068b4: ad400c04 addi r21,r21,48 + 10068b8: dc401515 stw r17,84(sp) + 10068bc: d8801a17 ldw r2,104(sp) + 10068c0: e5400005 stb r21,0(fp) + 10068c4: 202f883a mov r23,r4 + 10068c8: d9c01b17 ldw r7,108(sp) + 10068cc: d9001417 ldw r4,80(sp) + 10068d0: 880b883a mov r5,r17 + 10068d4: 100d883a mov r6,r2 + 10068d8: 102d883a mov r22,r2 + 10068dc: e7000044 addi fp,fp,1 + 10068e0: 100b70c0 call 100b70c <__ltdf2> + 10068e4: 103fc30e bge r2,zero,10067f4 <_dtoa_r+0x1064> + 10068e8: d9000417 ldw r4,16(sp) + 10068ec: d9000d15 stw r4,52(sp) + 10068f0: 003d7106 br 1005eb8 <_dtoa_r+0x728> + 10068f4: d9801717 ldw r6,92(sp) + 10068f8: 00800084 movi r2,2 + 10068fc: 11bde60e bge r2,r6,1006098 <_dtoa_r+0x908> + 1006900: 203cfb1e bne r4,zero,1005cf0 <_dtoa_r+0x560> + 1006904: d9001617 ldw r4,88(sp) + 1006908: 900b883a mov r5,r18 + 100690c: 01800144 movi r6,5 + 1006910: 000f883a mov r7,zero + 1006914: 1008e000 call 1008e00 <__multadd> + 1006918: d9000717 ldw r4,28(sp) + 100691c: 100b883a mov r5,r2 + 1006920: 1025883a mov r18,r2 + 1006924: 10082a80 call 10082a8 <__mcmp> + 1006928: 00bcf10e bge zero,r2,1005cf0 <_dtoa_r+0x560> + 100692c: d8c00d17 ldw r3,52(sp) + 1006930: d9000517 ldw r4,20(sp) + 1006934: d8000615 stw zero,24(sp) + 1006938: 18c00044 addi r3,r3,1 + 100693c: d8c00d15 stw r3,52(sp) + 1006940: 00800c44 movi r2,49 + 1006944: 27000044 addi fp,r4,1 + 1006948: 20800005 stb r2,0(r4) + 100694c: 003e8906 br 1006374 <_dtoa_r+0xbe4> + 1006950: d8c00517 ldw r3,20(sp) + 1006954: 003bc206 br 1005860 <_dtoa_r+0xd0> + 1006958: 018040b4 movhi r6,258 + 100695c: 31a3d204 addi r6,r6,-28856 + 1006960: 30c00917 ldw r3,36(r6) + 1006964: 30800817 ldw r2,32(r6) + 1006968: d9001217 ldw r4,72(sp) + 100696c: d9401317 ldw r5,76(sp) + 1006970: 180f883a mov r7,r3 + 1006974: 100d883a mov r6,r2 + 1006978: 100b2940 call 100b294 <__divdf3> + 100697c: 948003cc andi r18,r18,15 + 1006980: 058000c4 movi r22,3 + 1006984: 1029883a mov r20,r2 + 1006988: 182b883a mov r21,r3 + 100698c: 003c8906 br 1005bb4 <_dtoa_r+0x424> + 1006990: d9001017 ldw r4,64(sp) + 1006994: d9800917 ldw r6,36(sp) + 1006998: 0025883a mov r18,zero + 100699c: 1105c83a sub r2,r2,r4 + 10069a0: 2089883a add r4,r4,r2 + 10069a4: 308d883a add r6,r6,r2 + 10069a8: d9001015 stw r4,64(sp) + 10069ac: d9800915 stw r6,36(sp) + 10069b0: 003e3206 br 100627c <_dtoa_r+0xaec> + 10069b4: 28800044 addi r2,r5,1 + 10069b8: 27000044 addi fp,r4,1 + 10069bc: 20800005 stb r2,0(r4) + 10069c0: 003e6c06 br 1006374 <_dtoa_r+0xbe4> + 10069c4: d8800f17 ldw r2,60(sp) + 10069c8: 00bce016 blt zero,r2,1005d4c <_dtoa_r+0x5bc> + 10069cc: d9800f17 ldw r6,60(sp) + 10069d0: 303cc51e bne r6,zero,1005ce8 <_dtoa_r+0x558> + 10069d4: 0005883a mov r2,zero + 10069d8: 00d00534 movhi r3,16404 + 10069dc: 980b883a mov r5,r19 + 10069e0: 180f883a mov r7,r3 + 10069e4: 9009883a mov r4,r18 + 10069e8: 100d883a mov r6,r2 + 10069ec: 100aed00 call 100aed0 <__muldf3> + 10069f0: 180b883a mov r5,r3 + 10069f4: a80f883a mov r7,r21 + 10069f8: 1009883a mov r4,r2 + 10069fc: a00d883a mov r6,r20 + 1006a00: 100b6840 call 100b684 <__gedf2> + 1006a04: 103cb80e bge r2,zero,1005ce8 <_dtoa_r+0x558> + 1006a08: 0027883a mov r19,zero + 1006a0c: 0025883a mov r18,zero + 1006a10: 003fc606 br 100692c <_dtoa_r+0x119c> + 1006a14: 99400117 ldw r5,4(r19) + 1006a18: d9001617 ldw r4,88(sp) + 1006a1c: 10086cc0 call 10086cc <_Balloc> + 1006a20: 99800417 ldw r6,16(r19) + 1006a24: 11000304 addi r4,r2,12 + 1006a28: 99400304 addi r5,r19,12 + 1006a2c: 318d883a add r6,r6,r6 + 1006a30: 318d883a add r6,r6,r6 + 1006a34: 31800204 addi r6,r6,8 + 1006a38: 1023883a mov r17,r2 + 1006a3c: 1007fcc0 call 1007fcc + 1006a40: d9001617 ldw r4,88(sp) + 1006a44: 880b883a mov r5,r17 + 1006a48: 01800044 movi r6,1 + 1006a4c: 1008a900 call 1008a90 <__lshift> + 1006a50: 100b883a mov r5,r2 + 1006a54: 003d9c06 br 10060c8 <_dtoa_r+0x938> + 1006a58: 00800e44 movi r2,57 + 1006a5c: b8807026 beq r23,r2,1006c20 <_dtoa_r+0x1490> + 1006a60: b8800044 addi r2,r23,1 + 1006a64: b7000044 addi fp,r22,1 + 1006a68: b0800005 stb r2,0(r22) + 1006a6c: 003e4106 br 1006374 <_dtoa_r+0xbe4> + 1006a70: d8800317 ldw r2,12(sp) + 1006a74: 018040b4 movhi r6,258 + 1006a78: 31a3a004 addi r6,r6,-29056 + 1006a7c: b009883a mov r4,r22 + 1006a80: 100e90fa slli r7,r2,3 + 1006a84: b80b883a mov r5,r23 + 1006a88: 398f883a add r7,r7,r6 + 1006a8c: 38bffe17 ldw r2,-8(r7) + 1006a90: d9800517 ldw r6,20(sp) + 1006a94: 38ffff17 ldw r3,-4(r7) + 1006a98: 37000044 addi fp,r6,1 + 1006a9c: 180f883a mov r7,r3 + 1006aa0: 100d883a mov r6,r2 + 1006aa4: 100aed00 call 100aed0 <__muldf3> + 1006aa8: a80b883a mov r5,r21 + 1006aac: a009883a mov r4,r20 + 1006ab0: 182f883a mov r23,r3 + 1006ab4: 102d883a mov r22,r2 + 1006ab8: 100b88c0 call 100b88c <__fixdfsi> + 1006abc: 1009883a mov r4,r2 + 1006ac0: 1027883a mov r19,r2 + 1006ac4: 100b7940 call 100b794 <__floatsidf> + 1006ac8: a80b883a mov r5,r21 + 1006acc: a009883a mov r4,r20 + 1006ad0: 180f883a mov r7,r3 + 1006ad4: 100d883a mov r6,r2 + 1006ad8: 100addc0 call 100addc <__subdf3> + 1006adc: 180b883a mov r5,r3 + 1006ae0: d8c00517 ldw r3,20(sp) + 1006ae4: 9cc00c04 addi r19,r19,48 + 1006ae8: 1009883a mov r4,r2 + 1006aec: 1cc00005 stb r19,0(r3) + 1006af0: 2021883a mov r16,r4 + 1006af4: d9000317 ldw r4,12(sp) + 1006af8: 00800044 movi r2,1 + 1006afc: 2823883a mov r17,r5 + 1006b00: 20802226 beq r4,r2,1006b8c <_dtoa_r+0x13fc> + 1006b04: 1029883a mov r20,r2 + 1006b08: 0005883a mov r2,zero + 1006b0c: 00d00934 movhi r3,16420 + 1006b10: 180f883a mov r7,r3 + 1006b14: 100d883a mov r6,r2 + 1006b18: 880b883a mov r5,r17 + 1006b1c: 8009883a mov r4,r16 + 1006b20: 100aed00 call 100aed0 <__muldf3> + 1006b24: 180b883a mov r5,r3 + 1006b28: 1009883a mov r4,r2 + 1006b2c: 1823883a mov r17,r3 + 1006b30: 1021883a mov r16,r2 + 1006b34: 100b88c0 call 100b88c <__fixdfsi> + 1006b38: 1009883a mov r4,r2 + 1006b3c: 102b883a mov r21,r2 + 1006b40: 100b7940 call 100b794 <__floatsidf> + 1006b44: 880b883a mov r5,r17 + 1006b48: 8009883a mov r4,r16 + 1006b4c: 180f883a mov r7,r3 + 1006b50: 100d883a mov r6,r2 + 1006b54: 100addc0 call 100addc <__subdf3> + 1006b58: 180b883a mov r5,r3 + 1006b5c: d8c00517 ldw r3,20(sp) + 1006b60: 1009883a mov r4,r2 + 1006b64: ad400c04 addi r21,r21,48 + 1006b68: 1d05883a add r2,r3,r20 + 1006b6c: 15400005 stb r21,0(r2) + 1006b70: 2021883a mov r16,r4 + 1006b74: d9000317 ldw r4,12(sp) + 1006b78: a5000044 addi r20,r20,1 + 1006b7c: 2823883a mov r17,r5 + 1006b80: a13fe11e bne r20,r4,1006b08 <_dtoa_r+0x1378> + 1006b84: e505883a add r2,fp,r20 + 1006b88: 173fffc4 addi fp,r2,-1 + 1006b8c: 0025883a mov r18,zero + 1006b90: 04cff834 movhi r19,16352 + 1006b94: b009883a mov r4,r22 + 1006b98: b80b883a mov r5,r23 + 1006b9c: 900d883a mov r6,r18 + 1006ba0: 980f883a mov r7,r19 + 1006ba4: 100ae5c0 call 100ae5c <__adddf3> + 1006ba8: 180b883a mov r5,r3 + 1006bac: 1009883a mov r4,r2 + 1006bb0: 800d883a mov r6,r16 + 1006bb4: 880f883a mov r7,r17 + 1006bb8: 100b70c0 call 100b70c <__ltdf2> + 1006bbc: 103cab16 blt r2,zero,1005e6c <_dtoa_r+0x6dc> + 1006bc0: 0009883a mov r4,zero + 1006bc4: 980b883a mov r5,r19 + 1006bc8: b80f883a mov r7,r23 + 1006bcc: b00d883a mov r6,r22 + 1006bd0: 100addc0 call 100addc <__subdf3> + 1006bd4: 180b883a mov r5,r3 + 1006bd8: 880f883a mov r7,r17 + 1006bdc: 1009883a mov r4,r2 + 1006be0: 800d883a mov r6,r16 + 1006be4: 100b5fc0 call 100b5fc <__gtdf2> + 1006be8: 00bc470e bge zero,r2,1005d08 <_dtoa_r+0x578> + 1006bec: 00c00c04 movi r3,48 + 1006bf0: e73fffc4 addi fp,fp,-1 + 1006bf4: e0800007 ldb r2,0(fp) + 1006bf8: 10fffd26 beq r2,r3,1006bf0 <_dtoa_r+0x1460> + 1006bfc: d9800417 ldw r6,16(sp) + 1006c00: e7000044 addi fp,fp,1 + 1006c04: d9800d15 stw r6,52(sp) + 1006c08: 003cab06 br 1005eb8 <_dtoa_r+0x728> + 1006c0c: d8c00f17 ldw r3,60(sp) + 1006c10: d9001117 ldw r4,68(sp) + 1006c14: 20e1c83a sub r16,r4,r3 + 1006c18: 0007883a mov r3,zero + 1006c1c: 003d9b06 br 100628c <_dtoa_r+0xafc> + 1006c20: 00800e44 movi r2,57 + 1006c24: b0800005 stb r2,0(r22) + 1006c28: b5800044 addi r22,r22,1 + 1006c2c: 003dc106 br 1006334 <_dtoa_r+0xba4> + 1006c30: 05800084 movi r22,2 + 1006c34: 003bf706 br 1005c14 <_dtoa_r+0x484> + 1006c38: d9000f17 ldw r4,60(sp) + 1006c3c: 013c000e bge zero,r4,1005c40 <_dtoa_r+0x4b0> + 1006c40: d9800e17 ldw r6,56(sp) + 1006c44: 01bc300e bge zero,r6,1005d08 <_dtoa_r+0x578> + 1006c48: 0005883a mov r2,zero + 1006c4c: 00d00934 movhi r3,16420 + 1006c50: a80b883a mov r5,r21 + 1006c54: 180f883a mov r7,r3 + 1006c58: a009883a mov r4,r20 + 1006c5c: 100d883a mov r6,r2 + 1006c60: 100aed00 call 100aed0 <__muldf3> + 1006c64: b1000044 addi r4,r22,1 + 1006c68: 1021883a mov r16,r2 + 1006c6c: 1823883a mov r17,r3 + 1006c70: 100b7940 call 100b794 <__floatsidf> + 1006c74: 880b883a mov r5,r17 + 1006c78: 8009883a mov r4,r16 + 1006c7c: 180f883a mov r7,r3 + 1006c80: 100d883a mov r6,r2 + 1006c84: 100aed00 call 100aed0 <__muldf3> + 1006c88: 0011883a mov r8,zero + 1006c8c: 02500734 movhi r9,16412 + 1006c90: 180b883a mov r5,r3 + 1006c94: 480f883a mov r7,r9 + 1006c98: 1009883a mov r4,r2 + 1006c9c: 400d883a mov r6,r8 + 1006ca0: 100ae5c0 call 100ae5c <__adddf3> + 1006ca4: 102d883a mov r22,r2 + 1006ca8: 00bf3034 movhi r2,64704 + 1006cac: 10ef883a add r23,r2,r3 + 1006cb0: d8800d17 ldw r2,52(sp) + 1006cb4: d8c00e17 ldw r3,56(sp) + 1006cb8: 8029883a mov r20,r16 + 1006cbc: 10bfffc4 addi r2,r2,-1 + 1006cc0: 882b883a mov r21,r17 + 1006cc4: d8800415 stw r2,16(sp) + 1006cc8: d8c00315 stw r3,12(sp) + 1006ccc: 003e8306 br 10066dc <_dtoa_r+0xf4c> + 1006cd0: d8800117 ldw r2,4(sp) + 1006cd4: dc001117 ldw r16,68(sp) + 1006cd8: dc801017 ldw r18,64(sp) + 1006cdc: 00c00d84 movi r3,54 + 1006ce0: 1887c83a sub r3,r3,r2 + 1006ce4: 003d6906 br 100628c <_dtoa_r+0xafc> + 1006ce8: 01800044 movi r6,1 + 1006cec: 3021883a mov r16,r6 + 1006cf0: d9800f15 stw r6,60(sp) + 1006cf4: d9802615 stw r6,152(sp) + 1006cf8: d9800e15 stw r6,56(sp) + 1006cfc: 003b9306 br 1005b4c <_dtoa_r+0x3bc> + 1006d00: b021883a mov r16,r22 + 1006d04: dd800f15 stw r22,60(sp) + 1006d08: 003b9006 br 1005b4c <_dtoa_r+0x3bc> + 1006d0c: 103e221e bne r2,zero,1006598 <_dtoa_r+0xe08> + 1006d10: b880004c andi r2,r23,1 + 1006d14: 1005003a cmpeq r2,r2,zero + 1006d18: 103e1f1e bne r2,zero,1006598 <_dtoa_r+0xe08> + 1006d1c: 003e1b06 br 100658c <_dtoa_r+0xdfc> + 1006d20: d9001617 ldw r4,88(sp) + 1006d24: 980b883a mov r5,r19 + 1006d28: 01800284 movi r6,10 + 1006d2c: 000f883a mov r7,zero + 1006d30: 1008e000 call 1008e00 <__multadd> + 1006d34: d8c00e17 ldw r3,56(sp) + 1006d38: 1027883a mov r19,r2 + 1006d3c: d8c00f15 stw r3,60(sp) + 1006d40: 003cd306 br 1006090 <_dtoa_r+0x900> + +01006d44 <_fflush_r>: + 1006d44: defffb04 addi sp,sp,-20 + 1006d48: dcc00315 stw r19,12(sp) + 1006d4c: dc800215 stw r18,8(sp) + 1006d50: dfc00415 stw ra,16(sp) + 1006d54: dc400115 stw r17,4(sp) + 1006d58: dc000015 stw r16,0(sp) + 1006d5c: 2027883a mov r19,r4 + 1006d60: 2825883a mov r18,r5 + 1006d64: 20000226 beq r4,zero,1006d70 <_fflush_r+0x2c> + 1006d68: 20800e17 ldw r2,56(r4) + 1006d6c: 10005626 beq r2,zero,1006ec8 <_fflush_r+0x184> + 1006d70: 9100030b ldhu r4,12(r18) + 1006d74: 20ffffcc andi r3,r4,65535 + 1006d78: 18e0001c xori r3,r3,32768 + 1006d7c: 18e00004 addi r3,r3,-32768 + 1006d80: 1880020c andi r2,r3,8 + 1006d84: 1000261e bne r2,zero,1006e20 <_fflush_r+0xdc> + 1006d88: 90c00117 ldw r3,4(r18) + 1006d8c: 20820014 ori r2,r4,2048 + 1006d90: 9080030d sth r2,12(r18) + 1006d94: 1009883a mov r4,r2 + 1006d98: 00c0400e bge zero,r3,1006e9c <_fflush_r+0x158> + 1006d9c: 92000a17 ldw r8,40(r18) + 1006da0: 40004026 beq r8,zero,1006ea4 <_fflush_r+0x160> + 1006da4: 2084000c andi r2,r4,4096 + 1006da8: 10005326 beq r2,zero,1006ef8 <_fflush_r+0x1b4> + 1006dac: 94001417 ldw r16,80(r18) + 1006db0: 9080030b ldhu r2,12(r18) + 1006db4: 1080010c andi r2,r2,4 + 1006db8: 1000481e bne r2,zero,1006edc <_fflush_r+0x198> + 1006dbc: 91400717 ldw r5,28(r18) + 1006dc0: 9809883a mov r4,r19 + 1006dc4: 800d883a mov r6,r16 + 1006dc8: 000f883a mov r7,zero + 1006dcc: 403ee83a callr r8 + 1006dd0: 8080261e bne r16,r2,1006e6c <_fflush_r+0x128> + 1006dd4: 9080030b ldhu r2,12(r18) + 1006dd8: 91000417 ldw r4,16(r18) + 1006ddc: 90000115 stw zero,4(r18) + 1006de0: 10bdffcc andi r2,r2,63487 + 1006de4: 10ffffcc andi r3,r2,65535 + 1006de8: 18c4000c andi r3,r3,4096 + 1006dec: 9080030d sth r2,12(r18) + 1006df0: 91000015 stw r4,0(r18) + 1006df4: 18002b26 beq r3,zero,1006ea4 <_fflush_r+0x160> + 1006df8: 0007883a mov r3,zero + 1006dfc: 1805883a mov r2,r3 + 1006e00: 94001415 stw r16,80(r18) + 1006e04: dfc00417 ldw ra,16(sp) + 1006e08: dcc00317 ldw r19,12(sp) + 1006e0c: dc800217 ldw r18,8(sp) + 1006e10: dc400117 ldw r17,4(sp) + 1006e14: dc000017 ldw r16,0(sp) + 1006e18: dec00504 addi sp,sp,20 + 1006e1c: f800283a ret + 1006e20: 94400417 ldw r17,16(r18) + 1006e24: 88001f26 beq r17,zero,1006ea4 <_fflush_r+0x160> + 1006e28: 90800017 ldw r2,0(r18) + 1006e2c: 18c000cc andi r3,r3,3 + 1006e30: 94400015 stw r17,0(r18) + 1006e34: 1461c83a sub r16,r2,r17 + 1006e38: 18002526 beq r3,zero,1006ed0 <_fflush_r+0x18c> + 1006e3c: 0005883a mov r2,zero + 1006e40: 90800215 stw r2,8(r18) + 1006e44: 0400170e bge zero,r16,1006ea4 <_fflush_r+0x160> + 1006e48: 90c00917 ldw r3,36(r18) + 1006e4c: 91400717 ldw r5,28(r18) + 1006e50: 880d883a mov r6,r17 + 1006e54: 800f883a mov r7,r16 + 1006e58: 9809883a mov r4,r19 + 1006e5c: 183ee83a callr r3 + 1006e60: 88a3883a add r17,r17,r2 + 1006e64: 80a1c83a sub r16,r16,r2 + 1006e68: 00bff616 blt zero,r2,1006e44 <_fflush_r+0x100> + 1006e6c: 9080030b ldhu r2,12(r18) + 1006e70: 00ffffc4 movi r3,-1 + 1006e74: 10801014 ori r2,r2,64 + 1006e78: 9080030d sth r2,12(r18) + 1006e7c: 1805883a mov r2,r3 + 1006e80: dfc00417 ldw ra,16(sp) + 1006e84: dcc00317 ldw r19,12(sp) + 1006e88: dc800217 ldw r18,8(sp) + 1006e8c: dc400117 ldw r17,4(sp) + 1006e90: dc000017 ldw r16,0(sp) + 1006e94: dec00504 addi sp,sp,20 + 1006e98: f800283a ret + 1006e9c: 90800f17 ldw r2,60(r18) + 1006ea0: 00bfbe16 blt zero,r2,1006d9c <_fflush_r+0x58> + 1006ea4: 0007883a mov r3,zero + 1006ea8: 1805883a mov r2,r3 + 1006eac: dfc00417 ldw ra,16(sp) + 1006eb0: dcc00317 ldw r19,12(sp) + 1006eb4: dc800217 ldw r18,8(sp) + 1006eb8: dc400117 ldw r17,4(sp) + 1006ebc: dc000017 ldw r16,0(sp) + 1006ec0: dec00504 addi sp,sp,20 + 1006ec4: f800283a ret + 1006ec8: 1006fdc0 call 1006fdc <__sinit> + 1006ecc: 003fa806 br 1006d70 <_fflush_r+0x2c> + 1006ed0: 90800517 ldw r2,20(r18) + 1006ed4: 90800215 stw r2,8(r18) + 1006ed8: 003fda06 br 1006e44 <_fflush_r+0x100> + 1006edc: 90800117 ldw r2,4(r18) + 1006ee0: 90c00c17 ldw r3,48(r18) + 1006ee4: 80a1c83a sub r16,r16,r2 + 1006ee8: 183fb426 beq r3,zero,1006dbc <_fflush_r+0x78> + 1006eec: 90800f17 ldw r2,60(r18) + 1006ef0: 80a1c83a sub r16,r16,r2 + 1006ef4: 003fb106 br 1006dbc <_fflush_r+0x78> + 1006ef8: 91400717 ldw r5,28(r18) + 1006efc: 9809883a mov r4,r19 + 1006f00: 000d883a mov r6,zero + 1006f04: 01c00044 movi r7,1 + 1006f08: 403ee83a callr r8 + 1006f0c: 1021883a mov r16,r2 + 1006f10: 00bfffc4 movi r2,-1 + 1006f14: 80800226 beq r16,r2,1006f20 <_fflush_r+0x1dc> + 1006f18: 92000a17 ldw r8,40(r18) + 1006f1c: 003fa406 br 1006db0 <_fflush_r+0x6c> + 1006f20: 98c00017 ldw r3,0(r19) + 1006f24: 00800744 movi r2,29 + 1006f28: 18bfde26 beq r3,r2,1006ea4 <_fflush_r+0x160> + 1006f2c: 9080030b ldhu r2,12(r18) + 1006f30: 8007883a mov r3,r16 + 1006f34: 10801014 ori r2,r2,64 + 1006f38: 9080030d sth r2,12(r18) + 1006f3c: 003fcf06 br 1006e7c <_fflush_r+0x138> + +01006f40 : + 1006f40: 01404034 movhi r5,256 + 1006f44: 295b5104 addi r5,r5,27972 + 1006f48: 2007883a mov r3,r4 + 1006f4c: 20000526 beq r4,zero,1006f64 + 1006f50: 008040b4 movhi r2,258 + 1006f54: 10ab9804 addi r2,r2,-20896 + 1006f58: 11000017 ldw r4,0(r2) + 1006f5c: 180b883a mov r5,r3 + 1006f60: 1006d441 jmpi 1006d44 <_fflush_r> + 1006f64: 008040b4 movhi r2,258 + 1006f68: 10ab9904 addi r2,r2,-20892 + 1006f6c: 11000017 ldw r4,0(r2) + 1006f70: 1007b101 jmpi 1007b10 <_fwalk_reent> + +01006f74 : + 1006f74: 00804074 movhi r2,257 + 1006f78: 10a5e904 addi r2,r2,-26716 + 1006f7c: 20800b15 stw r2,44(r4) + 1006f80: 00804074 movhi r2,257 + 1006f84: 10a62404 addi r2,r2,-26480 + 1006f88: 20800815 stw r2,32(r4) + 1006f8c: 00c04074 movhi r3,257 + 1006f90: 18e60504 addi r3,r3,-26604 + 1006f94: 00804074 movhi r2,257 + 1006f98: 10a5eb04 addi r2,r2,-26708 + 1006f9c: 2140030d sth r5,12(r4) + 1006fa0: 2180038d sth r6,14(r4) + 1006fa4: 20c00915 stw r3,36(r4) + 1006fa8: 20800a15 stw r2,40(r4) + 1006fac: 20000015 stw zero,0(r4) + 1006fb0: 20000115 stw zero,4(r4) + 1006fb4: 20000215 stw zero,8(r4) + 1006fb8: 20000415 stw zero,16(r4) + 1006fbc: 20000515 stw zero,20(r4) + 1006fc0: 20000615 stw zero,24(r4) + 1006fc4: 21000715 stw r4,28(r4) + 1006fc8: f800283a ret + +01006fcc <__sfp_lock_acquire>: + 1006fcc: f800283a ret + +01006fd0 <__sfp_lock_release>: + 1006fd0: f800283a ret + +01006fd4 <__sinit_lock_acquire>: + 1006fd4: f800283a ret + +01006fd8 <__sinit_lock_release>: + 1006fd8: f800283a ret + +01006fdc <__sinit>: + 1006fdc: 20800e17 ldw r2,56(r4) + 1006fe0: defffd04 addi sp,sp,-12 + 1006fe4: dc400115 stw r17,4(sp) + 1006fe8: dc000015 stw r16,0(sp) + 1006fec: dfc00215 stw ra,8(sp) + 1006ff0: 04400044 movi r17,1 + 1006ff4: 01400104 movi r5,4 + 1006ff8: 000d883a mov r6,zero + 1006ffc: 2021883a mov r16,r4 + 1007000: 2200bb04 addi r8,r4,748 + 1007004: 200f883a mov r7,r4 + 1007008: 10000526 beq r2,zero,1007020 <__sinit+0x44> + 100700c: dfc00217 ldw ra,8(sp) + 1007010: dc400117 ldw r17,4(sp) + 1007014: dc000017 ldw r16,0(sp) + 1007018: dec00304 addi sp,sp,12 + 100701c: f800283a ret + 1007020: 21000117 ldw r4,4(r4) + 1007024: 00804034 movhi r2,256 + 1007028: 109c3004 addi r2,r2,28864 + 100702c: 00c000c4 movi r3,3 + 1007030: 80800f15 stw r2,60(r16) + 1007034: 80c0b915 stw r3,740(r16) + 1007038: 8200ba15 stw r8,744(r16) + 100703c: 84400e15 stw r17,56(r16) + 1007040: 8000b815 stw zero,736(r16) + 1007044: 1006f740 call 1006f74 + 1007048: 81000217 ldw r4,8(r16) + 100704c: 880d883a mov r6,r17 + 1007050: 800f883a mov r7,r16 + 1007054: 01400284 movi r5,10 + 1007058: 1006f740 call 1006f74 + 100705c: 81000317 ldw r4,12(r16) + 1007060: 800f883a mov r7,r16 + 1007064: 01400484 movi r5,18 + 1007068: 01800084 movi r6,2 + 100706c: dfc00217 ldw ra,8(sp) + 1007070: dc400117 ldw r17,4(sp) + 1007074: dc000017 ldw r16,0(sp) + 1007078: dec00304 addi sp,sp,12 + 100707c: 1006f741 jmpi 1006f74 + +01007080 <__fp_lock>: + 1007080: 0005883a mov r2,zero + 1007084: f800283a ret + +01007088 <__fp_unlock>: + 1007088: 0005883a mov r2,zero + 100708c: f800283a ret + +01007090 <__fp_unlock_all>: + 1007090: 008040b4 movhi r2,258 + 1007094: 10ab9804 addi r2,r2,-20896 + 1007098: 11000017 ldw r4,0(r2) + 100709c: 01404034 movhi r5,256 + 10070a0: 295c2204 addi r5,r5,28808 + 10070a4: 1007bd81 jmpi 1007bd8 <_fwalk> + +010070a8 <__fp_lock_all>: + 10070a8: 008040b4 movhi r2,258 + 10070ac: 10ab9804 addi r2,r2,-20896 + 10070b0: 11000017 ldw r4,0(r2) + 10070b4: 01404034 movhi r5,256 + 10070b8: 295c2004 addi r5,r5,28800 + 10070bc: 1007bd81 jmpi 1007bd8 <_fwalk> + +010070c0 <_cleanup_r>: + 10070c0: 01404074 movhi r5,257 + 10070c4: 29671604 addi r5,r5,-25512 + 10070c8: 1007bd81 jmpi 1007bd8 <_fwalk> + +010070cc <_cleanup>: + 10070cc: 008040b4 movhi r2,258 + 10070d0: 10ab9904 addi r2,r2,-20892 + 10070d4: 11000017 ldw r4,0(r2) + 10070d8: 10070c01 jmpi 10070c0 <_cleanup_r> + +010070dc <__sfmoreglue>: + 10070dc: defffc04 addi sp,sp,-16 + 10070e0: dc400115 stw r17,4(sp) + 10070e4: 2c401724 muli r17,r5,92 + 10070e8: dc800215 stw r18,8(sp) + 10070ec: 2825883a mov r18,r5 + 10070f0: 89400304 addi r5,r17,12 + 10070f4: dc000015 stw r16,0(sp) + 10070f8: dfc00315 stw ra,12(sp) + 10070fc: 10027dc0 call 10027dc <_malloc_r> + 1007100: 0021883a mov r16,zero + 1007104: 880d883a mov r6,r17 + 1007108: 000b883a mov r5,zero + 100710c: 10000626 beq r2,zero,1007128 <__sfmoreglue+0x4c> + 1007110: 11000304 addi r4,r2,12 + 1007114: 14800115 stw r18,4(r2) + 1007118: 10000015 stw zero,0(r2) + 100711c: 11000215 stw r4,8(r2) + 1007120: 1021883a mov r16,r2 + 1007124: 1002f1c0 call 1002f1c + 1007128: 8005883a mov r2,r16 + 100712c: dfc00317 ldw ra,12(sp) + 1007130: dc800217 ldw r18,8(sp) + 1007134: dc400117 ldw r17,4(sp) + 1007138: dc000017 ldw r16,0(sp) + 100713c: dec00404 addi sp,sp,16 + 1007140: f800283a ret + +01007144 <__sfp>: + 1007144: defffd04 addi sp,sp,-12 + 1007148: 008040b4 movhi r2,258 + 100714c: 10ab9904 addi r2,r2,-20892 + 1007150: dc000015 stw r16,0(sp) + 1007154: 14000017 ldw r16,0(r2) + 1007158: dc400115 stw r17,4(sp) + 100715c: dfc00215 stw ra,8(sp) + 1007160: 80800e17 ldw r2,56(r16) + 1007164: 2023883a mov r17,r4 + 1007168: 10002626 beq r2,zero,1007204 <__sfp+0xc0> + 100716c: 8400b804 addi r16,r16,736 + 1007170: 80800117 ldw r2,4(r16) + 1007174: 81000217 ldw r4,8(r16) + 1007178: 10ffffc4 addi r3,r2,-1 + 100717c: 18000916 blt r3,zero,10071a4 <__sfp+0x60> + 1007180: 2080030f ldh r2,12(r4) + 1007184: 10000b26 beq r2,zero,10071b4 <__sfp+0x70> + 1007188: 017fffc4 movi r5,-1 + 100718c: 00000206 br 1007198 <__sfp+0x54> + 1007190: 2080030f ldh r2,12(r4) + 1007194: 10000726 beq r2,zero,10071b4 <__sfp+0x70> + 1007198: 18ffffc4 addi r3,r3,-1 + 100719c: 21001704 addi r4,r4,92 + 10071a0: 197ffb1e bne r3,r5,1007190 <__sfp+0x4c> + 10071a4: 80800017 ldw r2,0(r16) + 10071a8: 10001926 beq r2,zero,1007210 <__sfp+0xcc> + 10071ac: 1021883a mov r16,r2 + 10071b0: 003fef06 br 1007170 <__sfp+0x2c> + 10071b4: 00bfffc4 movi r2,-1 + 10071b8: 00c00044 movi r3,1 + 10071bc: 2080038d sth r2,14(r4) + 10071c0: 20c0030d sth r3,12(r4) + 10071c4: 20000015 stw zero,0(r4) + 10071c8: 20000215 stw zero,8(r4) + 10071cc: 20000115 stw zero,4(r4) + 10071d0: 20000415 stw zero,16(r4) + 10071d4: 20000515 stw zero,20(r4) + 10071d8: 20000615 stw zero,24(r4) + 10071dc: 20000c15 stw zero,48(r4) + 10071e0: 20000d15 stw zero,52(r4) + 10071e4: 20001115 stw zero,68(r4) + 10071e8: 20001215 stw zero,72(r4) + 10071ec: 2005883a mov r2,r4 + 10071f0: dfc00217 ldw ra,8(sp) + 10071f4: dc400117 ldw r17,4(sp) + 10071f8: dc000017 ldw r16,0(sp) + 10071fc: dec00304 addi sp,sp,12 + 1007200: f800283a ret + 1007204: 8009883a mov r4,r16 + 1007208: 1006fdc0 call 1006fdc <__sinit> + 100720c: 003fd706 br 100716c <__sfp+0x28> + 1007210: 8809883a mov r4,r17 + 1007214: 01400104 movi r5,4 + 1007218: 10070dc0 call 10070dc <__sfmoreglue> + 100721c: 80800015 stw r2,0(r16) + 1007220: 103fe21e bne r2,zero,10071ac <__sfp+0x68> + 1007224: 00800304 movi r2,12 + 1007228: 0009883a mov r4,zero + 100722c: 88800015 stw r2,0(r17) + 1007230: 003fee06 br 10071ec <__sfp+0xa8> + +01007234 <_malloc_trim_r>: + 1007234: defffb04 addi sp,sp,-20 + 1007238: dcc00315 stw r19,12(sp) + 100723c: 04c040b4 movhi r19,258 + 1007240: 9ce49004 addi r19,r19,-28096 + 1007244: dc800215 stw r18,8(sp) + 1007248: dc400115 stw r17,4(sp) + 100724c: dc000015 stw r16,0(sp) + 1007250: 2823883a mov r17,r5 + 1007254: 2025883a mov r18,r4 + 1007258: dfc00415 stw ra,16(sp) + 100725c: 100d0a00 call 100d0a0 <__malloc_lock> + 1007260: 98800217 ldw r2,8(r19) + 1007264: 9009883a mov r4,r18 + 1007268: 000b883a mov r5,zero + 100726c: 10c00117 ldw r3,4(r2) + 1007270: 00bfff04 movi r2,-4 + 1007274: 18a0703a and r16,r3,r2 + 1007278: 8463c83a sub r17,r16,r17 + 100727c: 8c43fbc4 addi r17,r17,4079 + 1007280: 8822d33a srli r17,r17,12 + 1007284: 0083ffc4 movi r2,4095 + 1007288: 8c7fffc4 addi r17,r17,-1 + 100728c: 8822933a slli r17,r17,12 + 1007290: 1440060e bge r2,r17,10072ac <_malloc_trim_r+0x78> + 1007294: 10030e00 call 10030e0 <_sbrk_r> + 1007298: 98c00217 ldw r3,8(r19) + 100729c: 9009883a mov r4,r18 + 10072a0: 044bc83a sub r5,zero,r17 + 10072a4: 80c7883a add r3,r16,r3 + 10072a8: 10c00926 beq r2,r3,10072d0 <_malloc_trim_r+0x9c> + 10072ac: 100d1a80 call 100d1a8 <__malloc_unlock> + 10072b0: 0005883a mov r2,zero + 10072b4: dfc00417 ldw ra,16(sp) + 10072b8: dcc00317 ldw r19,12(sp) + 10072bc: dc800217 ldw r18,8(sp) + 10072c0: dc400117 ldw r17,4(sp) + 10072c4: dc000017 ldw r16,0(sp) + 10072c8: dec00504 addi sp,sp,20 + 10072cc: f800283a ret + 10072d0: 9009883a mov r4,r18 + 10072d4: 10030e00 call 10030e0 <_sbrk_r> + 10072d8: 844dc83a sub r6,r16,r17 + 10072dc: 00ffffc4 movi r3,-1 + 10072e0: 9009883a mov r4,r18 + 10072e4: 000b883a mov r5,zero + 10072e8: 01c040b4 movhi r7,258 + 10072ec: 39cd2b04 addi r7,r7,13484 + 10072f0: 31800054 ori r6,r6,1 + 10072f4: 10c00926 beq r2,r3,100731c <_malloc_trim_r+0xe8> + 10072f8: 38800017 ldw r2,0(r7) + 10072fc: 98c00217 ldw r3,8(r19) + 1007300: 9009883a mov r4,r18 + 1007304: 1445c83a sub r2,r2,r17 + 1007308: 38800015 stw r2,0(r7) + 100730c: 19800115 stw r6,4(r3) + 1007310: 100d1a80 call 100d1a8 <__malloc_unlock> + 1007314: 00800044 movi r2,1 + 1007318: 003fe606 br 10072b4 <_malloc_trim_r+0x80> + 100731c: 10030e00 call 10030e0 <_sbrk_r> + 1007320: 99800217 ldw r6,8(r19) + 1007324: 100f883a mov r7,r2 + 1007328: 9009883a mov r4,r18 + 100732c: 1187c83a sub r3,r2,r6 + 1007330: 008003c4 movi r2,15 + 1007334: 19400054 ori r5,r3,1 + 1007338: 10ffdc0e bge r2,r3,10072ac <_malloc_trim_r+0x78> + 100733c: 008040b4 movhi r2,258 + 1007340: 10ab9704 addi r2,r2,-20900 + 1007344: 10c00017 ldw r3,0(r2) + 1007348: 008040b4 movhi r2,258 + 100734c: 108d2b04 addi r2,r2,13484 + 1007350: 31400115 stw r5,4(r6) + 1007354: 38c7c83a sub r3,r7,r3 + 1007358: 10c00015 stw r3,0(r2) + 100735c: 003fd306 br 10072ac <_malloc_trim_r+0x78> + +01007360 <_free_r>: + 1007360: defffd04 addi sp,sp,-12 + 1007364: dc400115 stw r17,4(sp) + 1007368: dc000015 stw r16,0(sp) + 100736c: dfc00215 stw ra,8(sp) + 1007370: 2821883a mov r16,r5 + 1007374: 2023883a mov r17,r4 + 1007378: 28005a26 beq r5,zero,10074e4 <_free_r+0x184> + 100737c: 100d0a00 call 100d0a0 <__malloc_lock> + 1007380: 823ffe04 addi r8,r16,-8 + 1007384: 41400117 ldw r5,4(r8) + 1007388: 00bfff84 movi r2,-2 + 100738c: 028040b4 movhi r10,258 + 1007390: 52a49004 addi r10,r10,-28096 + 1007394: 288e703a and r7,r5,r2 + 1007398: 41cd883a add r6,r8,r7 + 100739c: 30c00117 ldw r3,4(r6) + 10073a0: 51000217 ldw r4,8(r10) + 10073a4: 00bfff04 movi r2,-4 + 10073a8: 1892703a and r9,r3,r2 + 10073ac: 5017883a mov r11,r10 + 10073b0: 31006726 beq r6,r4,1007550 <_free_r+0x1f0> + 10073b4: 2880004c andi r2,r5,1 + 10073b8: 1005003a cmpeq r2,r2,zero + 10073bc: 32400115 stw r9,4(r6) + 10073c0: 10001a1e bne r2,zero,100742c <_free_r+0xcc> + 10073c4: 000b883a mov r5,zero + 10073c8: 3247883a add r3,r6,r9 + 10073cc: 18800117 ldw r2,4(r3) + 10073d0: 1080004c andi r2,r2,1 + 10073d4: 1000231e bne r2,zero,1007464 <_free_r+0x104> + 10073d8: 280ac03a cmpne r5,r5,zero + 10073dc: 3a4f883a add r7,r7,r9 + 10073e0: 2800451e bne r5,zero,10074f8 <_free_r+0x198> + 10073e4: 31000217 ldw r4,8(r6) + 10073e8: 008040b4 movhi r2,258 + 10073ec: 10a49204 addi r2,r2,-28088 + 10073f0: 20807b26 beq r4,r2,10075e0 <_free_r+0x280> + 10073f4: 30800317 ldw r2,12(r6) + 10073f8: 3a07883a add r3,r7,r8 + 10073fc: 19c00015 stw r7,0(r3) + 1007400: 11000215 stw r4,8(r2) + 1007404: 20800315 stw r2,12(r4) + 1007408: 38800054 ori r2,r7,1 + 100740c: 40800115 stw r2,4(r8) + 1007410: 28001a26 beq r5,zero,100747c <_free_r+0x11c> + 1007414: 8809883a mov r4,r17 + 1007418: dfc00217 ldw ra,8(sp) + 100741c: dc400117 ldw r17,4(sp) + 1007420: dc000017 ldw r16,0(sp) + 1007424: dec00304 addi sp,sp,12 + 1007428: 100d1a81 jmpi 100d1a8 <__malloc_unlock> + 100742c: 80bffe17 ldw r2,-8(r16) + 1007430: 50c00204 addi r3,r10,8 + 1007434: 4091c83a sub r8,r8,r2 + 1007438: 41000217 ldw r4,8(r8) + 100743c: 388f883a add r7,r7,r2 + 1007440: 20c06126 beq r4,r3,10075c8 <_free_r+0x268> + 1007444: 40800317 ldw r2,12(r8) + 1007448: 3247883a add r3,r6,r9 + 100744c: 000b883a mov r5,zero + 1007450: 11000215 stw r4,8(r2) + 1007454: 20800315 stw r2,12(r4) + 1007458: 18800117 ldw r2,4(r3) + 100745c: 1080004c andi r2,r2,1 + 1007460: 103fdd26 beq r2,zero,10073d8 <_free_r+0x78> + 1007464: 38800054 ori r2,r7,1 + 1007468: 3a07883a add r3,r7,r8 + 100746c: 280ac03a cmpne r5,r5,zero + 1007470: 40800115 stw r2,4(r8) + 1007474: 19c00015 stw r7,0(r3) + 1007478: 283fe61e bne r5,zero,1007414 <_free_r+0xb4> + 100747c: 00807fc4 movi r2,511 + 1007480: 11c01f2e bgeu r2,r7,1007500 <_free_r+0x1a0> + 1007484: 3806d27a srli r3,r7,9 + 1007488: 1800481e bne r3,zero,10075ac <_free_r+0x24c> + 100748c: 3804d0fa srli r2,r7,3 + 1007490: 100690fa slli r3,r2,3 + 1007494: 1acd883a add r6,r3,r11 + 1007498: 31400217 ldw r5,8(r6) + 100749c: 31405926 beq r6,r5,1007604 <_free_r+0x2a4> + 10074a0: 28800117 ldw r2,4(r5) + 10074a4: 00ffff04 movi r3,-4 + 10074a8: 10c4703a and r2,r2,r3 + 10074ac: 3880022e bgeu r7,r2,10074b8 <_free_r+0x158> + 10074b0: 29400217 ldw r5,8(r5) + 10074b4: 317ffa1e bne r6,r5,10074a0 <_free_r+0x140> + 10074b8: 29800317 ldw r6,12(r5) + 10074bc: 41800315 stw r6,12(r8) + 10074c0: 41400215 stw r5,8(r8) + 10074c4: 8809883a mov r4,r17 + 10074c8: 2a000315 stw r8,12(r5) + 10074cc: 32000215 stw r8,8(r6) + 10074d0: dfc00217 ldw ra,8(sp) + 10074d4: dc400117 ldw r17,4(sp) + 10074d8: dc000017 ldw r16,0(sp) + 10074dc: dec00304 addi sp,sp,12 + 10074e0: 100d1a81 jmpi 100d1a8 <__malloc_unlock> + 10074e4: dfc00217 ldw ra,8(sp) + 10074e8: dc400117 ldw r17,4(sp) + 10074ec: dc000017 ldw r16,0(sp) + 10074f0: dec00304 addi sp,sp,12 + 10074f4: f800283a ret + 10074f8: 31000217 ldw r4,8(r6) + 10074fc: 003fbd06 br 10073f4 <_free_r+0x94> + 1007500: 3806d0fa srli r3,r7,3 + 1007504: 00800044 movi r2,1 + 1007508: 51400117 ldw r5,4(r10) + 100750c: 180890fa slli r4,r3,3 + 1007510: 1807d0ba srai r3,r3,2 + 1007514: 22c9883a add r4,r4,r11 + 1007518: 21800217 ldw r6,8(r4) + 100751c: 10c4983a sll r2,r2,r3 + 1007520: 41000315 stw r4,12(r8) + 1007524: 41800215 stw r6,8(r8) + 1007528: 288ab03a or r5,r5,r2 + 100752c: 22000215 stw r8,8(r4) + 1007530: 8809883a mov r4,r17 + 1007534: 51400115 stw r5,4(r10) + 1007538: 32000315 stw r8,12(r6) + 100753c: dfc00217 ldw ra,8(sp) + 1007540: dc400117 ldw r17,4(sp) + 1007544: dc000017 ldw r16,0(sp) + 1007548: dec00304 addi sp,sp,12 + 100754c: 100d1a81 jmpi 100d1a8 <__malloc_unlock> + 1007550: 2880004c andi r2,r5,1 + 1007554: 3a4d883a add r6,r7,r9 + 1007558: 1000071e bne r2,zero,1007578 <_free_r+0x218> + 100755c: 80bffe17 ldw r2,-8(r16) + 1007560: 4091c83a sub r8,r8,r2 + 1007564: 41000317 ldw r4,12(r8) + 1007568: 40c00217 ldw r3,8(r8) + 100756c: 308d883a add r6,r6,r2 + 1007570: 20c00215 stw r3,8(r4) + 1007574: 19000315 stw r4,12(r3) + 1007578: 008040b4 movhi r2,258 + 100757c: 10ab9604 addi r2,r2,-20904 + 1007580: 11000017 ldw r4,0(r2) + 1007584: 30c00054 ori r3,r6,1 + 1007588: 52000215 stw r8,8(r10) + 100758c: 40c00115 stw r3,4(r8) + 1007590: 313fa036 bltu r6,r4,1007414 <_free_r+0xb4> + 1007594: 008040b4 movhi r2,258 + 1007598: 10b30104 addi r2,r2,-13308 + 100759c: 11400017 ldw r5,0(r2) + 10075a0: 8809883a mov r4,r17 + 10075a4: 10072340 call 1007234 <_malloc_trim_r> + 10075a8: 003f9a06 br 1007414 <_free_r+0xb4> + 10075ac: 00800104 movi r2,4 + 10075b0: 10c0072e bgeu r2,r3,10075d0 <_free_r+0x270> + 10075b4: 00800504 movi r2,20 + 10075b8: 10c01936 bltu r2,r3,1007620 <_free_r+0x2c0> + 10075bc: 188016c4 addi r2,r3,91 + 10075c0: 100690fa slli r3,r2,3 + 10075c4: 003fb306 br 1007494 <_free_r+0x134> + 10075c8: 01400044 movi r5,1 + 10075cc: 003f7e06 br 10073c8 <_free_r+0x68> + 10075d0: 3804d1ba srli r2,r7,6 + 10075d4: 10800e04 addi r2,r2,56 + 10075d8: 100690fa slli r3,r2,3 + 10075dc: 003fad06 br 1007494 <_free_r+0x134> + 10075e0: 22000315 stw r8,12(r4) + 10075e4: 22000215 stw r8,8(r4) + 10075e8: 3a05883a add r2,r7,r8 + 10075ec: 38c00054 ori r3,r7,1 + 10075f0: 11c00015 stw r7,0(r2) + 10075f4: 41000215 stw r4,8(r8) + 10075f8: 40c00115 stw r3,4(r8) + 10075fc: 41000315 stw r4,12(r8) + 1007600: 003f8406 br 1007414 <_free_r+0xb4> + 1007604: 1005d0ba srai r2,r2,2 + 1007608: 00c00044 movi r3,1 + 100760c: 51000117 ldw r4,4(r10) + 1007610: 1886983a sll r3,r3,r2 + 1007614: 20c8b03a or r4,r4,r3 + 1007618: 51000115 stw r4,4(r10) + 100761c: 003fa706 br 10074bc <_free_r+0x15c> + 1007620: 00801504 movi r2,84 + 1007624: 10c00436 bltu r2,r3,1007638 <_free_r+0x2d8> + 1007628: 3804d33a srli r2,r7,12 + 100762c: 10801b84 addi r2,r2,110 + 1007630: 100690fa slli r3,r2,3 + 1007634: 003f9706 br 1007494 <_free_r+0x134> + 1007638: 00805504 movi r2,340 + 100763c: 10c00436 bltu r2,r3,1007650 <_free_r+0x2f0> + 1007640: 3804d3fa srli r2,r7,15 + 1007644: 10801dc4 addi r2,r2,119 + 1007648: 100690fa slli r3,r2,3 + 100764c: 003f9106 br 1007494 <_free_r+0x134> + 1007650: 00815504 movi r2,1364 + 1007654: 10c0032e bgeu r2,r3,1007664 <_free_r+0x304> + 1007658: 00801f84 movi r2,126 + 100765c: 00c0fc04 movi r3,1008 + 1007660: 003f8c06 br 1007494 <_free_r+0x134> + 1007664: 3804d4ba srli r2,r7,18 + 1007668: 10801f04 addi r2,r2,124 + 100766c: 100690fa slli r3,r2,3 + 1007670: 003f8806 br 1007494 <_free_r+0x134> + +01007674 <__sfvwrite_r>: + 1007674: 30800217 ldw r2,8(r6) + 1007678: defff504 addi sp,sp,-44 + 100767c: df000915 stw fp,36(sp) + 1007680: dd800715 stw r22,28(sp) + 1007684: dc800315 stw r18,12(sp) + 1007688: dfc00a15 stw ra,40(sp) + 100768c: ddc00815 stw r23,32(sp) + 1007690: dd400615 stw r21,24(sp) + 1007694: dd000515 stw r20,20(sp) + 1007698: dcc00415 stw r19,16(sp) + 100769c: dc400215 stw r17,8(sp) + 10076a0: dc000115 stw r16,4(sp) + 10076a4: 302d883a mov r22,r6 + 10076a8: 2039883a mov fp,r4 + 10076ac: 2825883a mov r18,r5 + 10076b0: 10001c26 beq r2,zero,1007724 <__sfvwrite_r+0xb0> + 10076b4: 29c0030b ldhu r7,12(r5) + 10076b8: 3880020c andi r2,r7,8 + 10076bc: 10002726 beq r2,zero,100775c <__sfvwrite_r+0xe8> + 10076c0: 28800417 ldw r2,16(r5) + 10076c4: 10002526 beq r2,zero,100775c <__sfvwrite_r+0xe8> + 10076c8: 3880008c andi r2,r7,2 + 10076cc: b5400017 ldw r21,0(r22) + 10076d0: 10002826 beq r2,zero,1007774 <__sfvwrite_r+0x100> + 10076d4: 0021883a mov r16,zero + 10076d8: 0023883a mov r17,zero + 10076dc: 880d883a mov r6,r17 + 10076e0: e009883a mov r4,fp + 10076e4: 00810004 movi r2,1024 + 10076e8: 80006e26 beq r16,zero,10078a4 <__sfvwrite_r+0x230> + 10076ec: 800f883a mov r7,r16 + 10076f0: 91400717 ldw r5,28(r18) + 10076f4: 1400012e bgeu r2,r16,10076fc <__sfvwrite_r+0x88> + 10076f8: 100f883a mov r7,r2 + 10076fc: 90c00917 ldw r3,36(r18) + 1007700: 183ee83a callr r3 + 1007704: 1007883a mov r3,r2 + 1007708: 80a1c83a sub r16,r16,r2 + 100770c: 88a3883a add r17,r17,r2 + 1007710: 00806d0e bge zero,r2,10078c8 <__sfvwrite_r+0x254> + 1007714: b0800217 ldw r2,8(r22) + 1007718: 10c5c83a sub r2,r2,r3 + 100771c: b0800215 stw r2,8(r22) + 1007720: 103fee1e bne r2,zero,10076dc <__sfvwrite_r+0x68> + 1007724: 0009883a mov r4,zero + 1007728: 2005883a mov r2,r4 + 100772c: dfc00a17 ldw ra,40(sp) + 1007730: df000917 ldw fp,36(sp) + 1007734: ddc00817 ldw r23,32(sp) + 1007738: dd800717 ldw r22,28(sp) + 100773c: dd400617 ldw r21,24(sp) + 1007740: dd000517 ldw r20,20(sp) + 1007744: dcc00417 ldw r19,16(sp) + 1007748: dc800317 ldw r18,12(sp) + 100774c: dc400217 ldw r17,8(sp) + 1007750: dc000117 ldw r16,4(sp) + 1007754: dec00b04 addi sp,sp,44 + 1007758: f800283a ret + 100775c: 100543c0 call 100543c <__swsetup_r> + 1007760: 1000e41e bne r2,zero,1007af4 <__sfvwrite_r+0x480> + 1007764: 91c0030b ldhu r7,12(r18) + 1007768: b5400017 ldw r21,0(r22) + 100776c: 3880008c andi r2,r7,2 + 1007770: 103fd81e bne r2,zero,10076d4 <__sfvwrite_r+0x60> + 1007774: 3880004c andi r2,r7,1 + 1007778: 1005003a cmpeq r2,r2,zero + 100777c: 10005726 beq r2,zero,10078dc <__sfvwrite_r+0x268> + 1007780: 0029883a mov r20,zero + 1007784: 002f883a mov r23,zero + 1007788: a0004226 beq r20,zero,1007894 <__sfvwrite_r+0x220> + 100778c: 3880800c andi r2,r7,512 + 1007790: 94000217 ldw r16,8(r18) + 1007794: 10008b26 beq r2,zero,10079c4 <__sfvwrite_r+0x350> + 1007798: 800d883a mov r6,r16 + 100779c: a400a536 bltu r20,r16,1007a34 <__sfvwrite_r+0x3c0> + 10077a0: 3881200c andi r2,r7,1152 + 10077a4: 10002726 beq r2,zero,1007844 <__sfvwrite_r+0x1d0> + 10077a8: 90800517 ldw r2,20(r18) + 10077ac: 92000417 ldw r8,16(r18) + 10077b0: 91400017 ldw r5,0(r18) + 10077b4: 1087883a add r3,r2,r2 + 10077b8: 1887883a add r3,r3,r2 + 10077bc: 1808d7fa srli r4,r3,31 + 10077c0: 2a21c83a sub r16,r5,r8 + 10077c4: 80800044 addi r2,r16,1 + 10077c8: 20c9883a add r4,r4,r3 + 10077cc: 2027d07a srai r19,r4,1 + 10077d0: a085883a add r2,r20,r2 + 10077d4: 980d883a mov r6,r19 + 10077d8: 9880022e bgeu r19,r2,10077e4 <__sfvwrite_r+0x170> + 10077dc: 1027883a mov r19,r2 + 10077e0: 100d883a mov r6,r2 + 10077e4: 3881000c andi r2,r7,1024 + 10077e8: 1000b826 beq r2,zero,1007acc <__sfvwrite_r+0x458> + 10077ec: 300b883a mov r5,r6 + 10077f0: e009883a mov r4,fp + 10077f4: 10027dc0 call 10027dc <_malloc_r> + 10077f8: 10003126 beq r2,zero,10078c0 <__sfvwrite_r+0x24c> + 10077fc: 91400417 ldw r5,16(r18) + 1007800: 1009883a mov r4,r2 + 1007804: 800d883a mov r6,r16 + 1007808: 1023883a mov r17,r2 + 100780c: 1007fcc0 call 1007fcc + 1007810: 90c0030b ldhu r3,12(r18) + 1007814: 00beffc4 movi r2,-1025 + 1007818: 1886703a and r3,r3,r2 + 100781c: 18c02014 ori r3,r3,128 + 1007820: 90c0030d sth r3,12(r18) + 1007824: 9c07c83a sub r3,r19,r16 + 1007828: 8c05883a add r2,r17,r16 + 100782c: a00d883a mov r6,r20 + 1007830: a021883a mov r16,r20 + 1007834: 90800015 stw r2,0(r18) + 1007838: 90c00215 stw r3,8(r18) + 100783c: 94400415 stw r17,16(r18) + 1007840: 94c00515 stw r19,20(r18) + 1007844: 91000017 ldw r4,0(r18) + 1007848: b80b883a mov r5,r23 + 100784c: a023883a mov r17,r20 + 1007850: 100806c0 call 100806c + 1007854: 90c00217 ldw r3,8(r18) + 1007858: 90800017 ldw r2,0(r18) + 100785c: a027883a mov r19,r20 + 1007860: 1c07c83a sub r3,r3,r16 + 1007864: 1405883a add r2,r2,r16 + 1007868: 90c00215 stw r3,8(r18) + 100786c: a021883a mov r16,r20 + 1007870: 90800015 stw r2,0(r18) + 1007874: b0800217 ldw r2,8(r22) + 1007878: 1405c83a sub r2,r2,r16 + 100787c: b0800215 stw r2,8(r22) + 1007880: 103fa826 beq r2,zero,1007724 <__sfvwrite_r+0xb0> + 1007884: a469c83a sub r20,r20,r17 + 1007888: 91c0030b ldhu r7,12(r18) + 100788c: bcef883a add r23,r23,r19 + 1007890: a03fbe1e bne r20,zero,100778c <__sfvwrite_r+0x118> + 1007894: adc00017 ldw r23,0(r21) + 1007898: ad000117 ldw r20,4(r21) + 100789c: ad400204 addi r21,r21,8 + 10078a0: 003fb906 br 1007788 <__sfvwrite_r+0x114> + 10078a4: ac400017 ldw r17,0(r21) + 10078a8: ac000117 ldw r16,4(r21) + 10078ac: ad400204 addi r21,r21,8 + 10078b0: 003f8a06 br 10076dc <__sfvwrite_r+0x68> + 10078b4: 91400417 ldw r5,16(r18) + 10078b8: e009883a mov r4,fp + 10078bc: 10073600 call 1007360 <_free_r> + 10078c0: 00800304 movi r2,12 + 10078c4: e0800015 stw r2,0(fp) + 10078c8: 9080030b ldhu r2,12(r18) + 10078cc: 013fffc4 movi r4,-1 + 10078d0: 10801014 ori r2,r2,64 + 10078d4: 9080030d sth r2,12(r18) + 10078d8: 003f9306 br 1007728 <__sfvwrite_r+0xb4> + 10078dc: 0027883a mov r19,zero + 10078e0: 002f883a mov r23,zero + 10078e4: d8000015 stw zero,0(sp) + 10078e8: 0029883a mov r20,zero + 10078ec: 98001e26 beq r19,zero,1007968 <__sfvwrite_r+0x2f4> + 10078f0: d8c00017 ldw r3,0(sp) + 10078f4: 1804c03a cmpne r2,r3,zero + 10078f8: 10005e26 beq r2,zero,1007a74 <__sfvwrite_r+0x400> + 10078fc: 9821883a mov r16,r19 + 1007900: a4c0012e bgeu r20,r19,1007908 <__sfvwrite_r+0x294> + 1007904: a021883a mov r16,r20 + 1007908: 91000017 ldw r4,0(r18) + 100790c: 90800417 ldw r2,16(r18) + 1007910: 91800217 ldw r6,8(r18) + 1007914: 91c00517 ldw r7,20(r18) + 1007918: 1100022e bgeu r2,r4,1007924 <__sfvwrite_r+0x2b0> + 100791c: 31e3883a add r17,r6,r7 + 1007920: 8c001616 blt r17,r16,100797c <__sfvwrite_r+0x308> + 1007924: 81c03816 blt r16,r7,1007a08 <__sfvwrite_r+0x394> + 1007928: 90c00917 ldw r3,36(r18) + 100792c: 91400717 ldw r5,28(r18) + 1007930: e009883a mov r4,fp + 1007934: b80d883a mov r6,r23 + 1007938: 183ee83a callr r3 + 100793c: 1023883a mov r17,r2 + 1007940: 00bfe10e bge zero,r2,10078c8 <__sfvwrite_r+0x254> + 1007944: a469c83a sub r20,r20,r17 + 1007948: a0001826 beq r20,zero,10079ac <__sfvwrite_r+0x338> + 100794c: b0800217 ldw r2,8(r22) + 1007950: 1445c83a sub r2,r2,r17 + 1007954: b0800215 stw r2,8(r22) + 1007958: 103f7226 beq r2,zero,1007724 <__sfvwrite_r+0xb0> + 100795c: 9c67c83a sub r19,r19,r17 + 1007960: bc6f883a add r23,r23,r17 + 1007964: 983fe21e bne r19,zero,10078f0 <__sfvwrite_r+0x27c> + 1007968: adc00017 ldw r23,0(r21) + 100796c: acc00117 ldw r19,4(r21) + 1007970: ad400204 addi r21,r21,8 + 1007974: d8000015 stw zero,0(sp) + 1007978: 003fdc06 br 10078ec <__sfvwrite_r+0x278> + 100797c: b80b883a mov r5,r23 + 1007980: 880d883a mov r6,r17 + 1007984: 100806c0 call 100806c + 1007988: 90c00017 ldw r3,0(r18) + 100798c: e009883a mov r4,fp + 1007990: 900b883a mov r5,r18 + 1007994: 1c47883a add r3,r3,r17 + 1007998: 90c00015 stw r3,0(r18) + 100799c: 1006d440 call 1006d44 <_fflush_r> + 10079a0: 103fc91e bne r2,zero,10078c8 <__sfvwrite_r+0x254> + 10079a4: a469c83a sub r20,r20,r17 + 10079a8: a03fe81e bne r20,zero,100794c <__sfvwrite_r+0x2d8> + 10079ac: e009883a mov r4,fp + 10079b0: 900b883a mov r5,r18 + 10079b4: 1006d440 call 1006d44 <_fflush_r> + 10079b8: 103fc31e bne r2,zero,10078c8 <__sfvwrite_r+0x254> + 10079bc: d8000015 stw zero,0(sp) + 10079c0: 003fe206 br 100794c <__sfvwrite_r+0x2d8> + 10079c4: 91000017 ldw r4,0(r18) + 10079c8: 90800417 ldw r2,16(r18) + 10079cc: 1100022e bgeu r2,r4,10079d8 <__sfvwrite_r+0x364> + 10079d0: 8023883a mov r17,r16 + 10079d4: 85003136 bltu r16,r20,1007a9c <__sfvwrite_r+0x428> + 10079d8: 91c00517 ldw r7,20(r18) + 10079dc: a1c01836 bltu r20,r7,1007a40 <__sfvwrite_r+0x3cc> + 10079e0: 90c00917 ldw r3,36(r18) + 10079e4: 91400717 ldw r5,28(r18) + 10079e8: e009883a mov r4,fp + 10079ec: b80d883a mov r6,r23 + 10079f0: 183ee83a callr r3 + 10079f4: 1021883a mov r16,r2 + 10079f8: 00bfb30e bge zero,r2,10078c8 <__sfvwrite_r+0x254> + 10079fc: 1023883a mov r17,r2 + 1007a00: 1027883a mov r19,r2 + 1007a04: 003f9b06 br 1007874 <__sfvwrite_r+0x200> + 1007a08: b80b883a mov r5,r23 + 1007a0c: 800d883a mov r6,r16 + 1007a10: 100806c0 call 100806c + 1007a14: 90c00217 ldw r3,8(r18) + 1007a18: 90800017 ldw r2,0(r18) + 1007a1c: 8023883a mov r17,r16 + 1007a20: 1c07c83a sub r3,r3,r16 + 1007a24: 1405883a add r2,r2,r16 + 1007a28: 90c00215 stw r3,8(r18) + 1007a2c: 90800015 stw r2,0(r18) + 1007a30: 003fc406 br 1007944 <__sfvwrite_r+0x2d0> + 1007a34: a00d883a mov r6,r20 + 1007a38: a021883a mov r16,r20 + 1007a3c: 003f8106 br 1007844 <__sfvwrite_r+0x1d0> + 1007a40: b80b883a mov r5,r23 + 1007a44: a00d883a mov r6,r20 + 1007a48: 100806c0 call 100806c + 1007a4c: 90c00217 ldw r3,8(r18) + 1007a50: 90800017 ldw r2,0(r18) + 1007a54: a021883a mov r16,r20 + 1007a58: 1d07c83a sub r3,r3,r20 + 1007a5c: 1505883a add r2,r2,r20 + 1007a60: a023883a mov r17,r20 + 1007a64: a027883a mov r19,r20 + 1007a68: 90c00215 stw r3,8(r18) + 1007a6c: 90800015 stw r2,0(r18) + 1007a70: 003f8006 br 1007874 <__sfvwrite_r+0x200> + 1007a74: b809883a mov r4,r23 + 1007a78: 01400284 movi r5,10 + 1007a7c: 980d883a mov r6,r19 + 1007a80: 1007ee80 call 1007ee8 + 1007a84: 10001726 beq r2,zero,1007ae4 <__sfvwrite_r+0x470> + 1007a88: 15c5c83a sub r2,r2,r23 + 1007a8c: 15000044 addi r20,r2,1 + 1007a90: 00800044 movi r2,1 + 1007a94: d8800015 stw r2,0(sp) + 1007a98: 003f9806 br 10078fc <__sfvwrite_r+0x288> + 1007a9c: b80b883a mov r5,r23 + 1007aa0: 800d883a mov r6,r16 + 1007aa4: 100806c0 call 100806c + 1007aa8: 90c00017 ldw r3,0(r18) + 1007aac: e009883a mov r4,fp + 1007ab0: 900b883a mov r5,r18 + 1007ab4: 1c07883a add r3,r3,r16 + 1007ab8: 90c00015 stw r3,0(r18) + 1007abc: 8027883a mov r19,r16 + 1007ac0: 1006d440 call 1006d44 <_fflush_r> + 1007ac4: 103f6b26 beq r2,zero,1007874 <__sfvwrite_r+0x200> + 1007ac8: 003f7f06 br 10078c8 <__sfvwrite_r+0x254> + 1007acc: 400b883a mov r5,r8 + 1007ad0: e009883a mov r4,fp + 1007ad4: 10091400 call 1009140 <_realloc_r> + 1007ad8: 103f7626 beq r2,zero,10078b4 <__sfvwrite_r+0x240> + 1007adc: 1023883a mov r17,r2 + 1007ae0: 003f5006 br 1007824 <__sfvwrite_r+0x1b0> + 1007ae4: 00c00044 movi r3,1 + 1007ae8: 9d000044 addi r20,r19,1 + 1007aec: d8c00015 stw r3,0(sp) + 1007af0: 003f8206 br 10078fc <__sfvwrite_r+0x288> + 1007af4: 9080030b ldhu r2,12(r18) + 1007af8: 00c00244 movi r3,9 + 1007afc: 013fffc4 movi r4,-1 + 1007b00: 10801014 ori r2,r2,64 + 1007b04: 9080030d sth r2,12(r18) + 1007b08: e0c00015 stw r3,0(fp) + 1007b0c: 003f0606 br 1007728 <__sfvwrite_r+0xb4> + +01007b10 <_fwalk_reent>: + 1007b10: defff704 addi sp,sp,-36 + 1007b14: dcc00315 stw r19,12(sp) + 1007b18: 24c0b804 addi r19,r4,736 + 1007b1c: dd800615 stw r22,24(sp) + 1007b20: dd400515 stw r21,20(sp) + 1007b24: dfc00815 stw ra,32(sp) + 1007b28: ddc00715 stw r23,28(sp) + 1007b2c: dd000415 stw r20,16(sp) + 1007b30: dc800215 stw r18,8(sp) + 1007b34: dc400115 stw r17,4(sp) + 1007b38: dc000015 stw r16,0(sp) + 1007b3c: 202b883a mov r21,r4 + 1007b40: 282d883a mov r22,r5 + 1007b44: 1006fcc0 call 1006fcc <__sfp_lock_acquire> + 1007b48: 98002126 beq r19,zero,1007bd0 <_fwalk_reent+0xc0> + 1007b4c: 002f883a mov r23,zero + 1007b50: 9c800117 ldw r18,4(r19) + 1007b54: 9c000217 ldw r16,8(r19) + 1007b58: 90bfffc4 addi r2,r18,-1 + 1007b5c: 10000d16 blt r2,zero,1007b94 <_fwalk_reent+0x84> + 1007b60: 0023883a mov r17,zero + 1007b64: 053fffc4 movi r20,-1 + 1007b68: 8080030f ldh r2,12(r16) + 1007b6c: 8c400044 addi r17,r17,1 + 1007b70: 10000626 beq r2,zero,1007b8c <_fwalk_reent+0x7c> + 1007b74: 8080038f ldh r2,14(r16) + 1007b78: 800b883a mov r5,r16 + 1007b7c: a809883a mov r4,r21 + 1007b80: 15000226 beq r2,r20,1007b8c <_fwalk_reent+0x7c> + 1007b84: b03ee83a callr r22 + 1007b88: b8aeb03a or r23,r23,r2 + 1007b8c: 84001704 addi r16,r16,92 + 1007b90: 947ff51e bne r18,r17,1007b68 <_fwalk_reent+0x58> + 1007b94: 9cc00017 ldw r19,0(r19) + 1007b98: 983fed1e bne r19,zero,1007b50 <_fwalk_reent+0x40> + 1007b9c: 1006fd00 call 1006fd0 <__sfp_lock_release> + 1007ba0: b805883a mov r2,r23 + 1007ba4: dfc00817 ldw ra,32(sp) + 1007ba8: ddc00717 ldw r23,28(sp) + 1007bac: dd800617 ldw r22,24(sp) + 1007bb0: dd400517 ldw r21,20(sp) + 1007bb4: dd000417 ldw r20,16(sp) + 1007bb8: dcc00317 ldw r19,12(sp) + 1007bbc: dc800217 ldw r18,8(sp) + 1007bc0: dc400117 ldw r17,4(sp) + 1007bc4: dc000017 ldw r16,0(sp) + 1007bc8: dec00904 addi sp,sp,36 + 1007bcc: f800283a ret + 1007bd0: 002f883a mov r23,zero + 1007bd4: 003ff106 br 1007b9c <_fwalk_reent+0x8c> + +01007bd8 <_fwalk>: + 1007bd8: defff804 addi sp,sp,-32 + 1007bdc: dcc00315 stw r19,12(sp) + 1007be0: 24c0b804 addi r19,r4,736 + 1007be4: dd400515 stw r21,20(sp) + 1007be8: dfc00715 stw ra,28(sp) + 1007bec: dd800615 stw r22,24(sp) + 1007bf0: dd000415 stw r20,16(sp) + 1007bf4: dc800215 stw r18,8(sp) + 1007bf8: dc400115 stw r17,4(sp) + 1007bfc: dc000015 stw r16,0(sp) + 1007c00: 282b883a mov r21,r5 + 1007c04: 1006fcc0 call 1006fcc <__sfp_lock_acquire> + 1007c08: 98001f26 beq r19,zero,1007c88 <_fwalk+0xb0> + 1007c0c: 002d883a mov r22,zero + 1007c10: 9c800117 ldw r18,4(r19) + 1007c14: 9c000217 ldw r16,8(r19) + 1007c18: 90bfffc4 addi r2,r18,-1 + 1007c1c: 10000c16 blt r2,zero,1007c50 <_fwalk+0x78> + 1007c20: 0023883a mov r17,zero + 1007c24: 053fffc4 movi r20,-1 + 1007c28: 8080030f ldh r2,12(r16) + 1007c2c: 8c400044 addi r17,r17,1 + 1007c30: 10000526 beq r2,zero,1007c48 <_fwalk+0x70> + 1007c34: 8080038f ldh r2,14(r16) + 1007c38: 8009883a mov r4,r16 + 1007c3c: 15000226 beq r2,r20,1007c48 <_fwalk+0x70> + 1007c40: a83ee83a callr r21 + 1007c44: b0acb03a or r22,r22,r2 + 1007c48: 84001704 addi r16,r16,92 + 1007c4c: 947ff61e bne r18,r17,1007c28 <_fwalk+0x50> + 1007c50: 9cc00017 ldw r19,0(r19) + 1007c54: 983fee1e bne r19,zero,1007c10 <_fwalk+0x38> + 1007c58: 1006fd00 call 1006fd0 <__sfp_lock_release> + 1007c5c: b005883a mov r2,r22 + 1007c60: dfc00717 ldw ra,28(sp) + 1007c64: dd800617 ldw r22,24(sp) + 1007c68: dd400517 ldw r21,20(sp) + 1007c6c: dd000417 ldw r20,16(sp) + 1007c70: dcc00317 ldw r19,12(sp) + 1007c74: dc800217 ldw r18,8(sp) + 1007c78: dc400117 ldw r17,4(sp) + 1007c7c: dc000017 ldw r16,0(sp) + 1007c80: dec00804 addi sp,sp,32 + 1007c84: f800283a ret + 1007c88: 002d883a mov r22,zero + 1007c8c: 003ff206 br 1007c58 <_fwalk+0x80> + +01007c90 <__locale_charset>: + 1007c90: d0a00e17 ldw r2,-32712(gp) + 1007c94: f800283a ret + +01007c98 <_localeconv_r>: + 1007c98: 008040b4 movhi r2,258 + 1007c9c: 10a39404 addi r2,r2,-29104 + 1007ca0: f800283a ret + +01007ca4 : + 1007ca4: 008040b4 movhi r2,258 + 1007ca8: 10ab9804 addi r2,r2,-20896 + 1007cac: 11000017 ldw r4,0(r2) + 1007cb0: 1007c981 jmpi 1007c98 <_localeconv_r> + +01007cb4 <_setlocale_r>: + 1007cb4: defffc04 addi sp,sp,-16 + 1007cb8: 00c040b4 movhi r3,258 + 1007cbc: 18e38f04 addi r3,r3,-29124 + 1007cc0: dc800215 stw r18,8(sp) + 1007cc4: dc400115 stw r17,4(sp) + 1007cc8: dc000015 stw r16,0(sp) + 1007ccc: 2023883a mov r17,r4 + 1007cd0: 2825883a mov r18,r5 + 1007cd4: dfc00315 stw ra,12(sp) + 1007cd8: 3021883a mov r16,r6 + 1007cdc: 3009883a mov r4,r6 + 1007ce0: 180b883a mov r5,r3 + 1007ce4: 30000926 beq r6,zero,1007d0c <_setlocale_r+0x58> + 1007ce8: 10098f00 call 10098f0 + 1007cec: 8009883a mov r4,r16 + 1007cf0: 014040b4 movhi r5,258 + 1007cf4: 29637a04 addi r5,r5,-29208 + 1007cf8: 10000b1e bne r2,zero,1007d28 <_setlocale_r+0x74> + 1007cfc: 8c000d15 stw r16,52(r17) + 1007d00: 8c800c15 stw r18,48(r17) + 1007d04: 00c040b4 movhi r3,258 + 1007d08: 18e38f04 addi r3,r3,-29124 + 1007d0c: 1805883a mov r2,r3 + 1007d10: dfc00317 ldw ra,12(sp) + 1007d14: dc800217 ldw r18,8(sp) + 1007d18: dc400117 ldw r17,4(sp) + 1007d1c: dc000017 ldw r16,0(sp) + 1007d20: dec00404 addi sp,sp,16 + 1007d24: f800283a ret + 1007d28: 10098f00 call 10098f0 + 1007d2c: 0007883a mov r3,zero + 1007d30: 103ff226 beq r2,zero,1007cfc <_setlocale_r+0x48> + 1007d34: 003ff506 br 1007d0c <_setlocale_r+0x58> + +01007d38 : + 1007d38: 018040b4 movhi r6,258 + 1007d3c: 31ab9804 addi r6,r6,-20896 + 1007d40: 2007883a mov r3,r4 + 1007d44: 31000017 ldw r4,0(r6) + 1007d48: 280d883a mov r6,r5 + 1007d4c: 180b883a mov r5,r3 + 1007d50: 1007cb41 jmpi 1007cb4 <_setlocale_r> + +01007d54 <__smakebuf_r>: + 1007d54: 2880030b ldhu r2,12(r5) + 1007d58: deffed04 addi sp,sp,-76 + 1007d5c: dc401015 stw r17,64(sp) + 1007d60: 1080008c andi r2,r2,2 + 1007d64: dc000f15 stw r16,60(sp) + 1007d68: dfc01215 stw ra,72(sp) + 1007d6c: dc801115 stw r18,68(sp) + 1007d70: 2821883a mov r16,r5 + 1007d74: 2023883a mov r17,r4 + 1007d78: 10000b26 beq r2,zero,1007da8 <__smakebuf_r+0x54> + 1007d7c: 28c010c4 addi r3,r5,67 + 1007d80: 00800044 movi r2,1 + 1007d84: 28800515 stw r2,20(r5) + 1007d88: 28c00415 stw r3,16(r5) + 1007d8c: 28c00015 stw r3,0(r5) + 1007d90: dfc01217 ldw ra,72(sp) + 1007d94: dc801117 ldw r18,68(sp) + 1007d98: dc401017 ldw r17,64(sp) + 1007d9c: dc000f17 ldw r16,60(sp) + 1007da0: dec01304 addi sp,sp,76 + 1007da4: f800283a ret + 1007da8: 2940038f ldh r5,14(r5) + 1007dac: 28002116 blt r5,zero,1007e34 <__smakebuf_r+0xe0> + 1007db0: d80d883a mov r6,sp + 1007db4: 1009c6c0 call 1009c6c <_fstat_r> + 1007db8: 10001e16 blt r2,zero,1007e34 <__smakebuf_r+0xe0> + 1007dbc: d8800117 ldw r2,4(sp) + 1007dc0: 00e00014 movui r3,32768 + 1007dc4: 113c000c andi r4,r2,61440 + 1007dc8: 20c03126 beq r4,r3,1007e90 <__smakebuf_r+0x13c> + 1007dcc: 8080030b ldhu r2,12(r16) + 1007dd0: 00c80004 movi r3,8192 + 1007dd4: 10820014 ori r2,r2,2048 + 1007dd8: 8080030d sth r2,12(r16) + 1007ddc: 20c01e26 beq r4,r3,1007e58 <__smakebuf_r+0x104> + 1007de0: 04810004 movi r18,1024 + 1007de4: 8809883a mov r4,r17 + 1007de8: 900b883a mov r5,r18 + 1007dec: 10027dc0 call 10027dc <_malloc_r> + 1007df0: 1009883a mov r4,r2 + 1007df4: 10003126 beq r2,zero,1007ebc <__smakebuf_r+0x168> + 1007df8: 80c0030b ldhu r3,12(r16) + 1007dfc: 00804034 movhi r2,256 + 1007e00: 109c3004 addi r2,r2,28864 + 1007e04: 88800f15 stw r2,60(r17) + 1007e08: 18c02014 ori r3,r3,128 + 1007e0c: 84800515 stw r18,20(r16) + 1007e10: 80c0030d sth r3,12(r16) + 1007e14: 81000415 stw r4,16(r16) + 1007e18: 81000015 stw r4,0(r16) + 1007e1c: dfc01217 ldw ra,72(sp) + 1007e20: dc801117 ldw r18,68(sp) + 1007e24: dc401017 ldw r17,64(sp) + 1007e28: dc000f17 ldw r16,60(sp) + 1007e2c: dec01304 addi sp,sp,76 + 1007e30: f800283a ret + 1007e34: 80c0030b ldhu r3,12(r16) + 1007e38: 1880200c andi r2,r3,128 + 1007e3c: 10000426 beq r2,zero,1007e50 <__smakebuf_r+0xfc> + 1007e40: 04801004 movi r18,64 + 1007e44: 18820014 ori r2,r3,2048 + 1007e48: 8080030d sth r2,12(r16) + 1007e4c: 003fe506 br 1007de4 <__smakebuf_r+0x90> + 1007e50: 04810004 movi r18,1024 + 1007e54: 003ffb06 br 1007e44 <__smakebuf_r+0xf0> + 1007e58: 8140038f ldh r5,14(r16) + 1007e5c: 8809883a mov r4,r17 + 1007e60: 1009ce00 call 1009ce0 <_isatty_r> + 1007e64: 103fde26 beq r2,zero,1007de0 <__smakebuf_r+0x8c> + 1007e68: 8080030b ldhu r2,12(r16) + 1007e6c: 80c010c4 addi r3,r16,67 + 1007e70: 04810004 movi r18,1024 + 1007e74: 10800054 ori r2,r2,1 + 1007e78: 8080030d sth r2,12(r16) + 1007e7c: 00800044 movi r2,1 + 1007e80: 80c00415 stw r3,16(r16) + 1007e84: 80800515 stw r2,20(r16) + 1007e88: 80c00015 stw r3,0(r16) + 1007e8c: 003fd506 br 1007de4 <__smakebuf_r+0x90> + 1007e90: 80c00a17 ldw r3,40(r16) + 1007e94: 00804074 movhi r2,257 + 1007e98: 10a5eb04 addi r2,r2,-26708 + 1007e9c: 18bfcb1e bne r3,r2,1007dcc <__smakebuf_r+0x78> + 1007ea0: 8080030b ldhu r2,12(r16) + 1007ea4: 00c10004 movi r3,1024 + 1007ea8: 1825883a mov r18,r3 + 1007eac: 10c4b03a or r2,r2,r3 + 1007eb0: 8080030d sth r2,12(r16) + 1007eb4: 80c01315 stw r3,76(r16) + 1007eb8: 003fca06 br 1007de4 <__smakebuf_r+0x90> + 1007ebc: 8100030b ldhu r4,12(r16) + 1007ec0: 2080800c andi r2,r4,512 + 1007ec4: 103fb21e bne r2,zero,1007d90 <__smakebuf_r+0x3c> + 1007ec8: 80c010c4 addi r3,r16,67 + 1007ecc: 21000094 ori r4,r4,2 + 1007ed0: 00800044 movi r2,1 + 1007ed4: 80800515 stw r2,20(r16) + 1007ed8: 8100030d sth r4,12(r16) + 1007edc: 80c00415 stw r3,16(r16) + 1007ee0: 80c00015 stw r3,0(r16) + 1007ee4: 003faa06 br 1007d90 <__smakebuf_r+0x3c> + +01007ee8 : + 1007ee8: 008000c4 movi r2,3 + 1007eec: 29403fcc andi r5,r5,255 + 1007ef0: 2007883a mov r3,r4 + 1007ef4: 1180022e bgeu r2,r6,1007f00 + 1007ef8: 2084703a and r2,r4,r2 + 1007efc: 10000b26 beq r2,zero,1007f2c + 1007f00: 313fffc4 addi r4,r6,-1 + 1007f04: 3000051e bne r6,zero,1007f1c + 1007f08: 00002c06 br 1007fbc + 1007f0c: 213fffc4 addi r4,r4,-1 + 1007f10: 00bfffc4 movi r2,-1 + 1007f14: 18c00044 addi r3,r3,1 + 1007f18: 20802826 beq r4,r2,1007fbc + 1007f1c: 18800003 ldbu r2,0(r3) + 1007f20: 28bffa1e bne r5,r2,1007f0c + 1007f24: 1805883a mov r2,r3 + 1007f28: f800283a ret + 1007f2c: 0011883a mov r8,zero + 1007f30: 0007883a mov r3,zero + 1007f34: 01c00104 movi r7,4 + 1007f38: 4004923a slli r2,r8,8 + 1007f3c: 18c00044 addi r3,r3,1 + 1007f40: 1151883a add r8,r2,r5 + 1007f44: 19fffc1e bne r3,r7,1007f38 + 1007f48: 02bfbff4 movhi r10,65279 + 1007f4c: 52bfbfc4 addi r10,r10,-257 + 1007f50: 02602074 movhi r9,32897 + 1007f54: 4a602004 addi r9,r9,-32640 + 1007f58: 02c000c4 movi r11,3 + 1007f5c: 20800017 ldw r2,0(r4) + 1007f60: 31bfff04 addi r6,r6,-4 + 1007f64: 200f883a mov r7,r4 + 1007f68: 1204f03a xor r2,r2,r8 + 1007f6c: 1287883a add r3,r2,r10 + 1007f70: 1a46703a and r3,r3,r9 + 1007f74: 0084303a nor r2,zero,r2 + 1007f78: 10c4703a and r2,r2,r3 + 1007f7c: 10000b26 beq r2,zero,1007fac + 1007f80: 20800003 ldbu r2,0(r4) + 1007f84: 28800f26 beq r5,r2,1007fc4 + 1007f88: 20800043 ldbu r2,1(r4) + 1007f8c: 21c00044 addi r7,r4,1 + 1007f90: 28800c26 beq r5,r2,1007fc4 + 1007f94: 20800083 ldbu r2,2(r4) + 1007f98: 21c00084 addi r7,r4,2 + 1007f9c: 28800926 beq r5,r2,1007fc4 + 1007fa0: 208000c3 ldbu r2,3(r4) + 1007fa4: 21c000c4 addi r7,r4,3 + 1007fa8: 28800626 beq r5,r2,1007fc4 + 1007fac: 21000104 addi r4,r4,4 + 1007fb0: 59bfea36 bltu r11,r6,1007f5c + 1007fb4: 2007883a mov r3,r4 + 1007fb8: 003fd106 br 1007f00 + 1007fbc: 0005883a mov r2,zero + 1007fc0: f800283a ret + 1007fc4: 3805883a mov r2,r7 + 1007fc8: f800283a ret + +01007fcc : + 1007fcc: 01c003c4 movi r7,15 + 1007fd0: 2007883a mov r3,r4 + 1007fd4: 3980032e bgeu r7,r6,1007fe4 + 1007fd8: 2904b03a or r2,r5,r4 + 1007fdc: 108000cc andi r2,r2,3 + 1007fe0: 10000926 beq r2,zero,1008008 + 1007fe4: 30000626 beq r6,zero,1008000 + 1007fe8: 30cd883a add r6,r6,r3 + 1007fec: 28800003 ldbu r2,0(r5) + 1007ff0: 29400044 addi r5,r5,1 + 1007ff4: 18800005 stb r2,0(r3) + 1007ff8: 18c00044 addi r3,r3,1 + 1007ffc: 30fffb1e bne r6,r3,1007fec + 1008000: 2005883a mov r2,r4 + 1008004: f800283a ret + 1008008: 3811883a mov r8,r7 + 100800c: 200f883a mov r7,r4 + 1008010: 28c00017 ldw r3,0(r5) + 1008014: 31bffc04 addi r6,r6,-16 + 1008018: 38c00015 stw r3,0(r7) + 100801c: 28800117 ldw r2,4(r5) + 1008020: 38800115 stw r2,4(r7) + 1008024: 28c00217 ldw r3,8(r5) + 1008028: 38c00215 stw r3,8(r7) + 100802c: 28800317 ldw r2,12(r5) + 1008030: 29400404 addi r5,r5,16 + 1008034: 38800315 stw r2,12(r7) + 1008038: 39c00404 addi r7,r7,16 + 100803c: 41bff436 bltu r8,r6,1008010 + 1008040: 008000c4 movi r2,3 + 1008044: 1180072e bgeu r2,r6,1008064 + 1008048: 1007883a mov r3,r2 + 100804c: 28800017 ldw r2,0(r5) + 1008050: 31bfff04 addi r6,r6,-4 + 1008054: 29400104 addi r5,r5,4 + 1008058: 38800015 stw r2,0(r7) + 100805c: 39c00104 addi r7,r7,4 + 1008060: 19bffa36 bltu r3,r6,100804c + 1008064: 3807883a mov r3,r7 + 1008068: 003fde06 br 1007fe4 + +0100806c : + 100806c: 2807883a mov r3,r5 + 1008070: 2011883a mov r8,r4 + 1008074: 29000c2e bgeu r5,r4,10080a8 + 1008078: 298f883a add r7,r5,r6 + 100807c: 21c00a2e bgeu r4,r7,10080a8 + 1008080: 30000726 beq r6,zero,10080a0 + 1008084: 2187883a add r3,r4,r6 + 1008088: 198dc83a sub r6,r3,r6 + 100808c: 39ffffc4 addi r7,r7,-1 + 1008090: 38800003 ldbu r2,0(r7) + 1008094: 18ffffc4 addi r3,r3,-1 + 1008098: 18800005 stb r2,0(r3) + 100809c: 19bffb1e bne r3,r6,100808c + 10080a0: 2005883a mov r2,r4 + 10080a4: f800283a ret + 10080a8: 01c003c4 movi r7,15 + 10080ac: 39800a36 bltu r7,r6,10080d8 + 10080b0: 303ffb26 beq r6,zero,10080a0 + 10080b4: 400f883a mov r7,r8 + 10080b8: 320d883a add r6,r6,r8 + 10080bc: 28800003 ldbu r2,0(r5) + 10080c0: 29400044 addi r5,r5,1 + 10080c4: 38800005 stb r2,0(r7) + 10080c8: 39c00044 addi r7,r7,1 + 10080cc: 39bffb1e bne r7,r6,10080bc + 10080d0: 2005883a mov r2,r4 + 10080d4: f800283a ret + 10080d8: 1904b03a or r2,r3,r4 + 10080dc: 108000cc andi r2,r2,3 + 10080e0: 103ff31e bne r2,zero,10080b0 + 10080e4: 3811883a mov r8,r7 + 10080e8: 180b883a mov r5,r3 + 10080ec: 200f883a mov r7,r4 + 10080f0: 28c00017 ldw r3,0(r5) + 10080f4: 31bffc04 addi r6,r6,-16 + 10080f8: 38c00015 stw r3,0(r7) + 10080fc: 28800117 ldw r2,4(r5) + 1008100: 38800115 stw r2,4(r7) + 1008104: 28c00217 ldw r3,8(r5) + 1008108: 38c00215 stw r3,8(r7) + 100810c: 28800317 ldw r2,12(r5) + 1008110: 29400404 addi r5,r5,16 + 1008114: 38800315 stw r2,12(r7) + 1008118: 39c00404 addi r7,r7,16 + 100811c: 41bff436 bltu r8,r6,10080f0 + 1008120: 008000c4 movi r2,3 + 1008124: 1180072e bgeu r2,r6,1008144 + 1008128: 1007883a mov r3,r2 + 100812c: 28800017 ldw r2,0(r5) + 1008130: 31bfff04 addi r6,r6,-4 + 1008134: 29400104 addi r5,r5,4 + 1008138: 38800015 stw r2,0(r7) + 100813c: 39c00104 addi r7,r7,4 + 1008140: 19bffa36 bltu r3,r6,100812c + 1008144: 3811883a mov r8,r7 + 1008148: 003fd906 br 10080b0 + +0100814c <_Bfree>: + 100814c: 28000826 beq r5,zero,1008170 <_Bfree+0x24> + 1008150: 28800117 ldw r2,4(r5) + 1008154: 21001317 ldw r4,76(r4) + 1008158: 1085883a add r2,r2,r2 + 100815c: 1085883a add r2,r2,r2 + 1008160: 1105883a add r2,r2,r4 + 1008164: 10c00017 ldw r3,0(r2) + 1008168: 28c00015 stw r3,0(r5) + 100816c: 11400015 stw r5,0(r2) + 1008170: f800283a ret + +01008174 <__hi0bits>: + 1008174: 20bfffec andhi r2,r4,65535 + 1008178: 10001426 beq r2,zero,10081cc <__hi0bits+0x58> + 100817c: 0007883a mov r3,zero + 1008180: 20bfc02c andhi r2,r4,65280 + 1008184: 1000021e bne r2,zero,1008190 <__hi0bits+0x1c> + 1008188: 2008923a slli r4,r4,8 + 100818c: 18c00204 addi r3,r3,8 + 1008190: 20bc002c andhi r2,r4,61440 + 1008194: 1000021e bne r2,zero,10081a0 <__hi0bits+0x2c> + 1008198: 2008913a slli r4,r4,4 + 100819c: 18c00104 addi r3,r3,4 + 10081a0: 20b0002c andhi r2,r4,49152 + 10081a4: 1000031e bne r2,zero,10081b4 <__hi0bits+0x40> + 10081a8: 2105883a add r2,r4,r4 + 10081ac: 18c00084 addi r3,r3,2 + 10081b0: 1089883a add r4,r2,r2 + 10081b4: 20000316 blt r4,zero,10081c4 <__hi0bits+0x50> + 10081b8: 2090002c andhi r2,r4,16384 + 10081bc: 10000626 beq r2,zero,10081d8 <__hi0bits+0x64> + 10081c0: 18c00044 addi r3,r3,1 + 10081c4: 1805883a mov r2,r3 + 10081c8: f800283a ret + 10081cc: 2008943a slli r4,r4,16 + 10081d0: 00c00404 movi r3,16 + 10081d4: 003fea06 br 1008180 <__hi0bits+0xc> + 10081d8: 00c00804 movi r3,32 + 10081dc: 1805883a mov r2,r3 + 10081e0: f800283a ret + +010081e4 <__lo0bits>: + 10081e4: 20c00017 ldw r3,0(r4) + 10081e8: 188001cc andi r2,r3,7 + 10081ec: 10000a26 beq r2,zero,1008218 <__lo0bits+0x34> + 10081f0: 1880004c andi r2,r3,1 + 10081f4: 1005003a cmpeq r2,r2,zero + 10081f8: 10002126 beq r2,zero,1008280 <__lo0bits+0x9c> + 10081fc: 1880008c andi r2,r3,2 + 1008200: 1000251e bne r2,zero,1008298 <__lo0bits+0xb4> + 1008204: 1804d0ba srli r2,r3,2 + 1008208: 01400084 movi r5,2 + 100820c: 20800015 stw r2,0(r4) + 1008210: 2805883a mov r2,r5 + 1008214: f800283a ret + 1008218: 18bfffcc andi r2,r3,65535 + 100821c: 10001526 beq r2,zero,1008274 <__lo0bits+0x90> + 1008220: 000b883a mov r5,zero + 1008224: 18803fcc andi r2,r3,255 + 1008228: 1000021e bne r2,zero,1008234 <__lo0bits+0x50> + 100822c: 1806d23a srli r3,r3,8 + 1008230: 29400204 addi r5,r5,8 + 1008234: 188003cc andi r2,r3,15 + 1008238: 1000021e bne r2,zero,1008244 <__lo0bits+0x60> + 100823c: 1806d13a srli r3,r3,4 + 1008240: 29400104 addi r5,r5,4 + 1008244: 188000cc andi r2,r3,3 + 1008248: 1000021e bne r2,zero,1008254 <__lo0bits+0x70> + 100824c: 1806d0ba srli r3,r3,2 + 1008250: 29400084 addi r5,r5,2 + 1008254: 1880004c andi r2,r3,1 + 1008258: 1000031e bne r2,zero,1008268 <__lo0bits+0x84> + 100825c: 1806d07a srli r3,r3,1 + 1008260: 18000a26 beq r3,zero,100828c <__lo0bits+0xa8> + 1008264: 29400044 addi r5,r5,1 + 1008268: 2805883a mov r2,r5 + 100826c: 20c00015 stw r3,0(r4) + 1008270: f800283a ret + 1008274: 1806d43a srli r3,r3,16 + 1008278: 01400404 movi r5,16 + 100827c: 003fe906 br 1008224 <__lo0bits+0x40> + 1008280: 000b883a mov r5,zero + 1008284: 2805883a mov r2,r5 + 1008288: f800283a ret + 100828c: 01400804 movi r5,32 + 1008290: 2805883a mov r2,r5 + 1008294: f800283a ret + 1008298: 1804d07a srli r2,r3,1 + 100829c: 01400044 movi r5,1 + 10082a0: 20800015 stw r2,0(r4) + 10082a4: 003fda06 br 1008210 <__lo0bits+0x2c> + +010082a8 <__mcmp>: + 10082a8: 20800417 ldw r2,16(r4) + 10082ac: 28c00417 ldw r3,16(r5) + 10082b0: 10cfc83a sub r7,r2,r3 + 10082b4: 38000c1e bne r7,zero,10082e8 <__mcmp+0x40> + 10082b8: 18c5883a add r2,r3,r3 + 10082bc: 1085883a add r2,r2,r2 + 10082c0: 10c00504 addi r3,r2,20 + 10082c4: 21000504 addi r4,r4,20 + 10082c8: 28cb883a add r5,r5,r3 + 10082cc: 2085883a add r2,r4,r2 + 10082d0: 10bfff04 addi r2,r2,-4 + 10082d4: 297fff04 addi r5,r5,-4 + 10082d8: 11800017 ldw r6,0(r2) + 10082dc: 28c00017 ldw r3,0(r5) + 10082e0: 30c0031e bne r6,r3,10082f0 <__mcmp+0x48> + 10082e4: 20bffa36 bltu r4,r2,10082d0 <__mcmp+0x28> + 10082e8: 3805883a mov r2,r7 + 10082ec: f800283a ret + 10082f0: 30c00336 bltu r6,r3,1008300 <__mcmp+0x58> + 10082f4: 01c00044 movi r7,1 + 10082f8: 3805883a mov r2,r7 + 10082fc: f800283a ret + 1008300: 01ffffc4 movi r7,-1 + 1008304: 003ff806 br 10082e8 <__mcmp+0x40> + +01008308 <__ulp>: + 1008308: 295ffc2c andhi r5,r5,32752 + 100830c: 013f3034 movhi r4,64704 + 1008310: 290b883a add r5,r5,r4 + 1008314: 0145c83a sub r2,zero,r5 + 1008318: 1007d53a srai r3,r2,20 + 100831c: 000d883a mov r6,zero + 1008320: 0140040e bge zero,r5,1008334 <__ulp+0x2c> + 1008324: 280f883a mov r7,r5 + 1008328: 3807883a mov r3,r7 + 100832c: 3005883a mov r2,r6 + 1008330: f800283a ret + 1008334: 008004c4 movi r2,19 + 1008338: 193ffb04 addi r4,r3,-20 + 100833c: 10c00c0e bge r2,r3,1008370 <__ulp+0x68> + 1008340: 008007c4 movi r2,31 + 1008344: 1107c83a sub r3,r2,r4 + 1008348: 00800784 movi r2,30 + 100834c: 01400044 movi r5,1 + 1008350: 11000216 blt r2,r4,100835c <__ulp+0x54> + 1008354: 00800044 movi r2,1 + 1008358: 10ca983a sll r5,r2,r3 + 100835c: 000f883a mov r7,zero + 1008360: 280d883a mov r6,r5 + 1008364: 3807883a mov r3,r7 + 1008368: 3005883a mov r2,r6 + 100836c: f800283a ret + 1008370: 00800234 movhi r2,8 + 1008374: 10cfd83a sra r7,r2,r3 + 1008378: 000d883a mov r6,zero + 100837c: 3005883a mov r2,r6 + 1008380: 3807883a mov r3,r7 + 1008384: f800283a ret + +01008388 <__b2d>: + 1008388: 20800417 ldw r2,16(r4) + 100838c: defff904 addi sp,sp,-28 + 1008390: dd000415 stw r20,16(sp) + 1008394: 1085883a add r2,r2,r2 + 1008398: 25000504 addi r20,r4,20 + 100839c: 1085883a add r2,r2,r2 + 10083a0: dc000015 stw r16,0(sp) + 10083a4: a0a1883a add r16,r20,r2 + 10083a8: dd400515 stw r21,20(sp) + 10083ac: 857fff17 ldw r21,-4(r16) + 10083b0: dc400115 stw r17,4(sp) + 10083b4: dfc00615 stw ra,24(sp) + 10083b8: a809883a mov r4,r21 + 10083bc: 2823883a mov r17,r5 + 10083c0: dcc00315 stw r19,12(sp) + 10083c4: dc800215 stw r18,8(sp) + 10083c8: 10081740 call 1008174 <__hi0bits> + 10083cc: 100b883a mov r5,r2 + 10083d0: 00800804 movi r2,32 + 10083d4: 1145c83a sub r2,r2,r5 + 10083d8: 88800015 stw r2,0(r17) + 10083dc: 00800284 movi r2,10 + 10083e0: 80ffff04 addi r3,r16,-4 + 10083e4: 11401416 blt r2,r5,1008438 <__b2d+0xb0> + 10083e8: 008002c4 movi r2,11 + 10083ec: 1149c83a sub r4,r2,r5 + 10083f0: a0c02736 bltu r20,r3,1008490 <__b2d+0x108> + 10083f4: 000d883a mov r6,zero + 10083f8: 28800544 addi r2,r5,21 + 10083fc: a906d83a srl r3,r21,r4 + 1008400: a884983a sll r2,r21,r2 + 1008404: 1ccffc34 orhi r19,r3,16368 + 1008408: 11a4b03a or r18,r2,r6 + 100840c: 9005883a mov r2,r18 + 1008410: 9807883a mov r3,r19 + 1008414: dfc00617 ldw ra,24(sp) + 1008418: dd400517 ldw r21,20(sp) + 100841c: dd000417 ldw r20,16(sp) + 1008420: dcc00317 ldw r19,12(sp) + 1008424: dc800217 ldw r18,8(sp) + 1008428: dc400117 ldw r17,4(sp) + 100842c: dc000017 ldw r16,0(sp) + 1008430: dec00704 addi sp,sp,28 + 1008434: f800283a ret + 1008438: a0c00e36 bltu r20,r3,1008474 <__b2d+0xec> + 100843c: 293ffd44 addi r4,r5,-11 + 1008440: 000d883a mov r6,zero + 1008444: 20000f26 beq r4,zero,1008484 <__b2d+0xfc> + 1008448: 00800804 movi r2,32 + 100844c: 110bc83a sub r5,r2,r4 + 1008450: a0c01236 bltu r20,r3,100849c <__b2d+0x114> + 1008454: 000f883a mov r7,zero + 1008458: a904983a sll r2,r21,r4 + 100845c: 3146d83a srl r3,r6,r5 + 1008460: 3108983a sll r4,r6,r4 + 1008464: 108ffc34 orhi r2,r2,16368 + 1008468: 18a6b03a or r19,r3,r2 + 100846c: 3924b03a or r18,r7,r4 + 1008470: 003fe606 br 100840c <__b2d+0x84> + 1008474: 293ffd44 addi r4,r5,-11 + 1008478: 81bffe17 ldw r6,-8(r16) + 100847c: 80fffe04 addi r3,r16,-8 + 1008480: 203ff11e bne r4,zero,1008448 <__b2d+0xc0> + 1008484: accffc34 orhi r19,r21,16368 + 1008488: 3025883a mov r18,r6 + 100848c: 003fdf06 br 100840c <__b2d+0x84> + 1008490: 18bfff17 ldw r2,-4(r3) + 1008494: 110cd83a srl r6,r2,r4 + 1008498: 003fd706 br 10083f8 <__b2d+0x70> + 100849c: 18bfff17 ldw r2,-4(r3) + 10084a0: 114ed83a srl r7,r2,r5 + 10084a4: 003fec06 br 1008458 <__b2d+0xd0> + +010084a8 <__ratio>: + 10084a8: defff904 addi sp,sp,-28 + 10084ac: dc400215 stw r17,8(sp) + 10084b0: 2823883a mov r17,r5 + 10084b4: d80b883a mov r5,sp + 10084b8: dfc00615 stw ra,24(sp) + 10084bc: dd000515 stw r20,20(sp) + 10084c0: dcc00415 stw r19,16(sp) + 10084c4: dc800315 stw r18,12(sp) + 10084c8: 2025883a mov r18,r4 + 10084cc: 10083880 call 1008388 <__b2d> + 10084d0: 8809883a mov r4,r17 + 10084d4: d9400104 addi r5,sp,4 + 10084d8: 1027883a mov r19,r2 + 10084dc: 1829883a mov r20,r3 + 10084e0: 10083880 call 1008388 <__b2d> + 10084e4: 89000417 ldw r4,16(r17) + 10084e8: 91c00417 ldw r7,16(r18) + 10084ec: d9800117 ldw r6,4(sp) + 10084f0: 180b883a mov r5,r3 + 10084f4: 390fc83a sub r7,r7,r4 + 10084f8: 1009883a mov r4,r2 + 10084fc: d8800017 ldw r2,0(sp) + 1008500: 380e917a slli r7,r7,5 + 1008504: 2011883a mov r8,r4 + 1008508: 1185c83a sub r2,r2,r6 + 100850c: 11c5883a add r2,r2,r7 + 1008510: 1006953a slli r3,r2,20 + 1008514: 2813883a mov r9,r5 + 1008518: 00800d0e bge zero,r2,1008550 <__ratio+0xa8> + 100851c: 1d29883a add r20,r3,r20 + 1008520: a00b883a mov r5,r20 + 1008524: 480f883a mov r7,r9 + 1008528: 9809883a mov r4,r19 + 100852c: 400d883a mov r6,r8 + 1008530: 100b2940 call 100b294 <__divdf3> + 1008534: dfc00617 ldw ra,24(sp) + 1008538: dd000517 ldw r20,20(sp) + 100853c: dcc00417 ldw r19,16(sp) + 1008540: dc800317 ldw r18,12(sp) + 1008544: dc400217 ldw r17,8(sp) + 1008548: dec00704 addi sp,sp,28 + 100854c: f800283a ret + 1008550: 28d3c83a sub r9,r5,r3 + 1008554: 003ff206 br 1008520 <__ratio+0x78> + +01008558 <_mprec_log10>: + 1008558: defffe04 addi sp,sp,-8 + 100855c: 008005c4 movi r2,23 + 1008560: dc000015 stw r16,0(sp) + 1008564: dfc00115 stw ra,4(sp) + 1008568: 2021883a mov r16,r4 + 100856c: 11000c16 blt r2,r4,10085a0 <_mprec_log10+0x48> + 1008570: 200490fa slli r2,r4,3 + 1008574: 00c040b4 movhi r3,258 + 1008578: 18e3a004 addi r3,r3,-29056 + 100857c: 10c5883a add r2,r2,r3 + 1008580: 12400117 ldw r9,4(r2) + 1008584: 12000017 ldw r8,0(r2) + 1008588: 4807883a mov r3,r9 + 100858c: 4005883a mov r2,r8 + 1008590: dfc00117 ldw ra,4(sp) + 1008594: dc000017 ldw r16,0(sp) + 1008598: dec00204 addi sp,sp,8 + 100859c: f800283a ret + 10085a0: 0011883a mov r8,zero + 10085a4: 024ffc34 movhi r9,16368 + 10085a8: 0005883a mov r2,zero + 10085ac: 00d00934 movhi r3,16420 + 10085b0: 480b883a mov r5,r9 + 10085b4: 4009883a mov r4,r8 + 10085b8: 180f883a mov r7,r3 + 10085bc: 100d883a mov r6,r2 + 10085c0: 100aed00 call 100aed0 <__muldf3> + 10085c4: 843fffc4 addi r16,r16,-1 + 10085c8: 1011883a mov r8,r2 + 10085cc: 1813883a mov r9,r3 + 10085d0: 803ff51e bne r16,zero,10085a8 <_mprec_log10+0x50> + 10085d4: 4005883a mov r2,r8 + 10085d8: 4807883a mov r3,r9 + 10085dc: dfc00117 ldw ra,4(sp) + 10085e0: dc000017 ldw r16,0(sp) + 10085e4: dec00204 addi sp,sp,8 + 10085e8: f800283a ret + +010085ec <__copybits>: + 10085ec: 297fffc4 addi r5,r5,-1 + 10085f0: 30800417 ldw r2,16(r6) + 10085f4: 280bd17a srai r5,r5,5 + 10085f8: 31800504 addi r6,r6,20 + 10085fc: 1085883a add r2,r2,r2 + 1008600: 294b883a add r5,r5,r5 + 1008604: 294b883a add r5,r5,r5 + 1008608: 1085883a add r2,r2,r2 + 100860c: 290b883a add r5,r5,r4 + 1008610: 3087883a add r3,r6,r2 + 1008614: 29400104 addi r5,r5,4 + 1008618: 30c0052e bgeu r6,r3,1008630 <__copybits+0x44> + 100861c: 30800017 ldw r2,0(r6) + 1008620: 31800104 addi r6,r6,4 + 1008624: 20800015 stw r2,0(r4) + 1008628: 21000104 addi r4,r4,4 + 100862c: 30fffb36 bltu r6,r3,100861c <__copybits+0x30> + 1008630: 2140032e bgeu r4,r5,1008640 <__copybits+0x54> + 1008634: 20000015 stw zero,0(r4) + 1008638: 21000104 addi r4,r4,4 + 100863c: 217ffd36 bltu r4,r5,1008634 <__copybits+0x48> + 1008640: f800283a ret + +01008644 <__any_on>: + 1008644: 20800417 ldw r2,16(r4) + 1008648: 2807d17a srai r3,r5,5 + 100864c: 21000504 addi r4,r4,20 + 1008650: 10c00d0e bge r2,r3,1008688 <__any_on+0x44> + 1008654: 1085883a add r2,r2,r2 + 1008658: 1085883a add r2,r2,r2 + 100865c: 208d883a add r6,r4,r2 + 1008660: 2180182e bgeu r4,r6,10086c4 <__any_on+0x80> + 1008664: 30bfff17 ldw r2,-4(r6) + 1008668: 30ffff04 addi r3,r6,-4 + 100866c: 1000041e bne r2,zero,1008680 <__any_on+0x3c> + 1008670: 20c0142e bgeu r4,r3,10086c4 <__any_on+0x80> + 1008674: 18ffff04 addi r3,r3,-4 + 1008678: 18800017 ldw r2,0(r3) + 100867c: 103ffc26 beq r2,zero,1008670 <__any_on+0x2c> + 1008680: 00800044 movi r2,1 + 1008684: f800283a ret + 1008688: 18800a0e bge r3,r2,10086b4 <__any_on+0x70> + 100868c: 294007cc andi r5,r5,31 + 1008690: 28000826 beq r5,zero,10086b4 <__any_on+0x70> + 1008694: 18c5883a add r2,r3,r3 + 1008698: 1085883a add r2,r2,r2 + 100869c: 208d883a add r6,r4,r2 + 10086a0: 30c00017 ldw r3,0(r6) + 10086a4: 1944d83a srl r2,r3,r5 + 10086a8: 1144983a sll r2,r2,r5 + 10086ac: 18bff41e bne r3,r2,1008680 <__any_on+0x3c> + 10086b0: 003feb06 br 1008660 <__any_on+0x1c> + 10086b4: 18c5883a add r2,r3,r3 + 10086b8: 1085883a add r2,r2,r2 + 10086bc: 208d883a add r6,r4,r2 + 10086c0: 003fe706 br 1008660 <__any_on+0x1c> + 10086c4: 0005883a mov r2,zero + 10086c8: f800283a ret + +010086cc <_Balloc>: + 10086cc: 20c01317 ldw r3,76(r4) + 10086d0: defffb04 addi sp,sp,-20 + 10086d4: dcc00315 stw r19,12(sp) + 10086d8: dc800215 stw r18,8(sp) + 10086dc: dfc00415 stw ra,16(sp) + 10086e0: 2825883a mov r18,r5 + 10086e4: dc400115 stw r17,4(sp) + 10086e8: dc000015 stw r16,0(sp) + 10086ec: 2027883a mov r19,r4 + 10086f0: 01800404 movi r6,16 + 10086f4: 01400104 movi r5,4 + 10086f8: 18001726 beq r3,zero,1008758 <_Balloc+0x8c> + 10086fc: 01400044 movi r5,1 + 1008700: 9485883a add r2,r18,r18 + 1008704: 2ca2983a sll r17,r5,r18 + 1008708: 1085883a add r2,r2,r2 + 100870c: 10c7883a add r3,r2,r3 + 1008710: 1c000017 ldw r16,0(r3) + 1008714: 8c4d883a add r6,r17,r17 + 1008718: 318d883a add r6,r6,r6 + 100871c: 9809883a mov r4,r19 + 1008720: 31800504 addi r6,r6,20 + 1008724: 80001226 beq r16,zero,1008770 <_Balloc+0xa4> + 1008728: 80800017 ldw r2,0(r16) + 100872c: 18800015 stw r2,0(r3) + 1008730: 80000415 stw zero,16(r16) + 1008734: 80000315 stw zero,12(r16) + 1008738: 8005883a mov r2,r16 + 100873c: dfc00417 ldw ra,16(sp) + 1008740: dcc00317 ldw r19,12(sp) + 1008744: dc800217 ldw r18,8(sp) + 1008748: dc400117 ldw r17,4(sp) + 100874c: dc000017 ldw r16,0(sp) + 1008750: dec00504 addi sp,sp,20 + 1008754: f800283a ret + 1008758: 1009a240 call 1009a24 <_calloc_r> + 100875c: 1007883a mov r3,r2 + 1008760: 0021883a mov r16,zero + 1008764: 98801315 stw r2,76(r19) + 1008768: 103fe41e bne r2,zero,10086fc <_Balloc+0x30> + 100876c: 003ff206 br 1008738 <_Balloc+0x6c> + 1008770: 1009a240 call 1009a24 <_calloc_r> + 1008774: 103ff026 beq r2,zero,1008738 <_Balloc+0x6c> + 1008778: 1021883a mov r16,r2 + 100877c: 14800115 stw r18,4(r2) + 1008780: 14400215 stw r17,8(r2) + 1008784: 003fea06 br 1008730 <_Balloc+0x64> + +01008788 <__d2b>: + 1008788: defff504 addi sp,sp,-44 + 100878c: dcc00515 stw r19,20(sp) + 1008790: 04c00044 movi r19,1 + 1008794: dc000215 stw r16,8(sp) + 1008798: 2821883a mov r16,r5 + 100879c: 980b883a mov r5,r19 + 10087a0: ddc00915 stw r23,36(sp) + 10087a4: dd800815 stw r22,32(sp) + 10087a8: dd400715 stw r21,28(sp) + 10087ac: dd000615 stw r20,24(sp) + 10087b0: dc800415 stw r18,16(sp) + 10087b4: dc400315 stw r17,12(sp) + 10087b8: dfc00a15 stw ra,40(sp) + 10087bc: 3023883a mov r17,r6 + 10087c0: 382d883a mov r22,r7 + 10087c4: ddc00b17 ldw r23,44(sp) + 10087c8: 10086cc0 call 10086cc <_Balloc> + 10087cc: 1025883a mov r18,r2 + 10087d0: 00a00034 movhi r2,32768 + 10087d4: 10bfffc4 addi r2,r2,-1 + 10087d8: 8888703a and r4,r17,r2 + 10087dc: 202ad53a srli r21,r4,20 + 10087e0: 00800434 movhi r2,16 + 10087e4: 10bfffc4 addi r2,r2,-1 + 10087e8: 8886703a and r3,r17,r2 + 10087ec: a829003a cmpeq r20,r21,zero + 10087f0: 800b883a mov r5,r16 + 10087f4: d8c00115 stw r3,4(sp) + 10087f8: 94000504 addi r16,r18,20 + 10087fc: a000021e bne r20,zero,1008808 <__d2b+0x80> + 1008800: 18c00434 orhi r3,r3,16 + 1008804: d8c00115 stw r3,4(sp) + 1008808: 28002726 beq r5,zero,10088a8 <__d2b+0x120> + 100880c: d809883a mov r4,sp + 1008810: d9400015 stw r5,0(sp) + 1008814: 10081e40 call 10081e4 <__lo0bits> + 1008818: 100d883a mov r6,r2 + 100881c: 10003526 beq r2,zero,10088f4 <__d2b+0x16c> + 1008820: d8c00117 ldw r3,4(sp) + 1008824: 00800804 movi r2,32 + 1008828: 1185c83a sub r2,r2,r6 + 100882c: d9000017 ldw r4,0(sp) + 1008830: 1886983a sll r3,r3,r2 + 1008834: 1906b03a or r3,r3,r4 + 1008838: 90c00515 stw r3,20(r18) + 100883c: d8c00117 ldw r3,4(sp) + 1008840: 1986d83a srl r3,r3,r6 + 1008844: d8c00115 stw r3,4(sp) + 1008848: 180b003a cmpeq r5,r3,zero + 100884c: 00800084 movi r2,2 + 1008850: 114bc83a sub r5,r2,r5 + 1008854: 80c00115 stw r3,4(r16) + 1008858: 91400415 stw r5,16(r18) + 100885c: a0001a1e bne r20,zero,10088c8 <__d2b+0x140> + 1008860: 3545883a add r2,r6,r21 + 1008864: 10bef344 addi r2,r2,-1075 + 1008868: 00c00d44 movi r3,53 + 100886c: b0800015 stw r2,0(r22) + 1008870: 1987c83a sub r3,r3,r6 + 1008874: b8c00015 stw r3,0(r23) + 1008878: 9005883a mov r2,r18 + 100887c: dfc00a17 ldw ra,40(sp) + 1008880: ddc00917 ldw r23,36(sp) + 1008884: dd800817 ldw r22,32(sp) + 1008888: dd400717 ldw r21,28(sp) + 100888c: dd000617 ldw r20,24(sp) + 1008890: dcc00517 ldw r19,20(sp) + 1008894: dc800417 ldw r18,16(sp) + 1008898: dc400317 ldw r17,12(sp) + 100889c: dc000217 ldw r16,8(sp) + 10088a0: dec00b04 addi sp,sp,44 + 10088a4: f800283a ret + 10088a8: d9000104 addi r4,sp,4 + 10088ac: 10081e40 call 10081e4 <__lo0bits> + 10088b0: 11800804 addi r6,r2,32 + 10088b4: d8800117 ldw r2,4(sp) + 10088b8: 94c00415 stw r19,16(r18) + 10088bc: 980b883a mov r5,r19 + 10088c0: 90800515 stw r2,20(r18) + 10088c4: a03fe626 beq r20,zero,1008860 <__d2b+0xd8> + 10088c8: 2945883a add r2,r5,r5 + 10088cc: 1085883a add r2,r2,r2 + 10088d0: 1405883a add r2,r2,r16 + 10088d4: 113fff17 ldw r4,-4(r2) + 10088d8: 30fef384 addi r3,r6,-1074 + 10088dc: 2820917a slli r16,r5,5 + 10088e0: b0c00015 stw r3,0(r22) + 10088e4: 10081740 call 1008174 <__hi0bits> + 10088e8: 80a1c83a sub r16,r16,r2 + 10088ec: bc000015 stw r16,0(r23) + 10088f0: 003fe106 br 1008878 <__d2b+0xf0> + 10088f4: d8800017 ldw r2,0(sp) + 10088f8: 90800515 stw r2,20(r18) + 10088fc: d8c00117 ldw r3,4(sp) + 1008900: 003fd106 br 1008848 <__d2b+0xc0> + +01008904 <__mdiff>: + 1008904: defffb04 addi sp,sp,-20 + 1008908: dc000015 stw r16,0(sp) + 100890c: 2821883a mov r16,r5 + 1008910: dc800215 stw r18,8(sp) + 1008914: 300b883a mov r5,r6 + 1008918: 2025883a mov r18,r4 + 100891c: 8009883a mov r4,r16 + 1008920: dc400115 stw r17,4(sp) + 1008924: dfc00415 stw ra,16(sp) + 1008928: dcc00315 stw r19,12(sp) + 100892c: 3023883a mov r17,r6 + 1008930: 10082a80 call 10082a8 <__mcmp> + 1008934: 10004226 beq r2,zero,1008a40 <__mdiff+0x13c> + 1008938: 10005016 blt r2,zero,1008a7c <__mdiff+0x178> + 100893c: 0027883a mov r19,zero + 1008940: 81400117 ldw r5,4(r16) + 1008944: 9009883a mov r4,r18 + 1008948: 10086cc0 call 10086cc <_Balloc> + 100894c: 1019883a mov r12,r2 + 1008950: 82800417 ldw r10,16(r16) + 1008954: 88800417 ldw r2,16(r17) + 1008958: 81800504 addi r6,r16,20 + 100895c: 5287883a add r3,r10,r10 + 1008960: 1085883a add r2,r2,r2 + 1008964: 18c7883a add r3,r3,r3 + 1008968: 1085883a add r2,r2,r2 + 100896c: 8a000504 addi r8,r17,20 + 1008970: 64c00315 stw r19,12(r12) + 1008974: 30db883a add r13,r6,r3 + 1008978: 4097883a add r11,r8,r2 + 100897c: 61c00504 addi r7,r12,20 + 1008980: 0013883a mov r9,zero + 1008984: 31000017 ldw r4,0(r6) + 1008988: 41400017 ldw r5,0(r8) + 100898c: 42000104 addi r8,r8,4 + 1008990: 20bfffcc andi r2,r4,65535 + 1008994: 28ffffcc andi r3,r5,65535 + 1008998: 10c5c83a sub r2,r2,r3 + 100899c: 1245883a add r2,r2,r9 + 10089a0: 2008d43a srli r4,r4,16 + 10089a4: 280ad43a srli r5,r5,16 + 10089a8: 1007d43a srai r3,r2,16 + 10089ac: 3880000d sth r2,0(r7) + 10089b0: 2149c83a sub r4,r4,r5 + 10089b4: 20c9883a add r4,r4,r3 + 10089b8: 3900008d sth r4,2(r7) + 10089bc: 31800104 addi r6,r6,4 + 10089c0: 39c00104 addi r7,r7,4 + 10089c4: 2013d43a srai r9,r4,16 + 10089c8: 42ffee36 bltu r8,r11,1008984 <__mdiff+0x80> + 10089cc: 33400c2e bgeu r6,r13,1008a00 <__mdiff+0xfc> + 10089d0: 30800017 ldw r2,0(r6) + 10089d4: 31800104 addi r6,r6,4 + 10089d8: 10ffffcc andi r3,r2,65535 + 10089dc: 1a47883a add r3,r3,r9 + 10089e0: 1004d43a srli r2,r2,16 + 10089e4: 1809d43a srai r4,r3,16 + 10089e8: 38c0000d sth r3,0(r7) + 10089ec: 1105883a add r2,r2,r4 + 10089f0: 3880008d sth r2,2(r7) + 10089f4: 1013d43a srai r9,r2,16 + 10089f8: 39c00104 addi r7,r7,4 + 10089fc: 337ff436 bltu r6,r13,10089d0 <__mdiff+0xcc> + 1008a00: 38bfff17 ldw r2,-4(r7) + 1008a04: 38ffff04 addi r3,r7,-4 + 1008a08: 1000041e bne r2,zero,1008a1c <__mdiff+0x118> + 1008a0c: 18ffff04 addi r3,r3,-4 + 1008a10: 18800017 ldw r2,0(r3) + 1008a14: 52bfffc4 addi r10,r10,-1 + 1008a18: 103ffc26 beq r2,zero,1008a0c <__mdiff+0x108> + 1008a1c: 6005883a mov r2,r12 + 1008a20: 62800415 stw r10,16(r12) + 1008a24: dfc00417 ldw ra,16(sp) + 1008a28: dcc00317 ldw r19,12(sp) + 1008a2c: dc800217 ldw r18,8(sp) + 1008a30: dc400117 ldw r17,4(sp) + 1008a34: dc000017 ldw r16,0(sp) + 1008a38: dec00504 addi sp,sp,20 + 1008a3c: f800283a ret + 1008a40: 9009883a mov r4,r18 + 1008a44: 000b883a mov r5,zero + 1008a48: 10086cc0 call 10086cc <_Balloc> + 1008a4c: 1019883a mov r12,r2 + 1008a50: 00800044 movi r2,1 + 1008a54: 60800415 stw r2,16(r12) + 1008a58: 6005883a mov r2,r12 + 1008a5c: 60000515 stw zero,20(r12) + 1008a60: dfc00417 ldw ra,16(sp) + 1008a64: dcc00317 ldw r19,12(sp) + 1008a68: dc800217 ldw r18,8(sp) + 1008a6c: dc400117 ldw r17,4(sp) + 1008a70: dc000017 ldw r16,0(sp) + 1008a74: dec00504 addi sp,sp,20 + 1008a78: f800283a ret + 1008a7c: 880d883a mov r6,r17 + 1008a80: 04c00044 movi r19,1 + 1008a84: 8023883a mov r17,r16 + 1008a88: 3021883a mov r16,r6 + 1008a8c: 003fac06 br 1008940 <__mdiff+0x3c> + +01008a90 <__lshift>: + 1008a90: defff904 addi sp,sp,-28 + 1008a94: 28800417 ldw r2,16(r5) + 1008a98: dc000015 stw r16,0(sp) + 1008a9c: 3021d17a srai r16,r6,5 + 1008aa0: 28c00217 ldw r3,8(r5) + 1008aa4: 10800044 addi r2,r2,1 + 1008aa8: dc400115 stw r17,4(sp) + 1008aac: 80a3883a add r17,r16,r2 + 1008ab0: dd400515 stw r21,20(sp) + 1008ab4: dd000415 stw r20,16(sp) + 1008ab8: dc800215 stw r18,8(sp) + 1008abc: dfc00615 stw ra,24(sp) + 1008ac0: 2825883a mov r18,r5 + 1008ac4: dcc00315 stw r19,12(sp) + 1008ac8: 3029883a mov r20,r6 + 1008acc: 202b883a mov r21,r4 + 1008ad0: 29400117 ldw r5,4(r5) + 1008ad4: 1c40030e bge r3,r17,1008ae4 <__lshift+0x54> + 1008ad8: 18c7883a add r3,r3,r3 + 1008adc: 29400044 addi r5,r5,1 + 1008ae0: 1c7ffd16 blt r3,r17,1008ad8 <__lshift+0x48> + 1008ae4: a809883a mov r4,r21 + 1008ae8: 10086cc0 call 10086cc <_Balloc> + 1008aec: 1027883a mov r19,r2 + 1008af0: 11400504 addi r5,r2,20 + 1008af4: 0400090e bge zero,r16,1008b1c <__lshift+0x8c> + 1008af8: 2805883a mov r2,r5 + 1008afc: 0007883a mov r3,zero + 1008b00: 18c00044 addi r3,r3,1 + 1008b04: 10000015 stw zero,0(r2) + 1008b08: 10800104 addi r2,r2,4 + 1008b0c: 80fffc1e bne r16,r3,1008b00 <__lshift+0x70> + 1008b10: 8405883a add r2,r16,r16 + 1008b14: 1085883a add r2,r2,r2 + 1008b18: 288b883a add r5,r5,r2 + 1008b1c: 90800417 ldw r2,16(r18) + 1008b20: 91000504 addi r4,r18,20 + 1008b24: a18007cc andi r6,r20,31 + 1008b28: 1085883a add r2,r2,r2 + 1008b2c: 1085883a add r2,r2,r2 + 1008b30: 208f883a add r7,r4,r2 + 1008b34: 30001e26 beq r6,zero,1008bb0 <__lshift+0x120> + 1008b38: 00800804 movi r2,32 + 1008b3c: 1191c83a sub r8,r2,r6 + 1008b40: 0007883a mov r3,zero + 1008b44: 20800017 ldw r2,0(r4) + 1008b48: 1184983a sll r2,r2,r6 + 1008b4c: 1884b03a or r2,r3,r2 + 1008b50: 28800015 stw r2,0(r5) + 1008b54: 20c00017 ldw r3,0(r4) + 1008b58: 21000104 addi r4,r4,4 + 1008b5c: 29400104 addi r5,r5,4 + 1008b60: 1a06d83a srl r3,r3,r8 + 1008b64: 21fff736 bltu r4,r7,1008b44 <__lshift+0xb4> + 1008b68: 28c00015 stw r3,0(r5) + 1008b6c: 18000126 beq r3,zero,1008b74 <__lshift+0xe4> + 1008b70: 8c400044 addi r17,r17,1 + 1008b74: 88bfffc4 addi r2,r17,-1 + 1008b78: 98800415 stw r2,16(r19) + 1008b7c: a809883a mov r4,r21 + 1008b80: 900b883a mov r5,r18 + 1008b84: 100814c0 call 100814c <_Bfree> + 1008b88: 9805883a mov r2,r19 + 1008b8c: dfc00617 ldw ra,24(sp) + 1008b90: dd400517 ldw r21,20(sp) + 1008b94: dd000417 ldw r20,16(sp) + 1008b98: dcc00317 ldw r19,12(sp) + 1008b9c: dc800217 ldw r18,8(sp) + 1008ba0: dc400117 ldw r17,4(sp) + 1008ba4: dc000017 ldw r16,0(sp) + 1008ba8: dec00704 addi sp,sp,28 + 1008bac: f800283a ret + 1008bb0: 20800017 ldw r2,0(r4) + 1008bb4: 21000104 addi r4,r4,4 + 1008bb8: 28800015 stw r2,0(r5) + 1008bbc: 29400104 addi r5,r5,4 + 1008bc0: 21ffec2e bgeu r4,r7,1008b74 <__lshift+0xe4> + 1008bc4: 20800017 ldw r2,0(r4) + 1008bc8: 21000104 addi r4,r4,4 + 1008bcc: 28800015 stw r2,0(r5) + 1008bd0: 29400104 addi r5,r5,4 + 1008bd4: 21fff636 bltu r4,r7,1008bb0 <__lshift+0x120> + 1008bd8: 003fe606 br 1008b74 <__lshift+0xe4> + +01008bdc <__multiply>: + 1008bdc: defff904 addi sp,sp,-28 + 1008be0: dcc00315 stw r19,12(sp) + 1008be4: dc800215 stw r18,8(sp) + 1008be8: 2cc00417 ldw r19,16(r5) + 1008bec: 34800417 ldw r18,16(r6) + 1008bf0: dd000415 stw r20,16(sp) + 1008bf4: dc400115 stw r17,4(sp) + 1008bf8: dfc00615 stw ra,24(sp) + 1008bfc: dd400515 stw r21,20(sp) + 1008c00: dc000015 stw r16,0(sp) + 1008c04: 2823883a mov r17,r5 + 1008c08: 3029883a mov r20,r6 + 1008c0c: 9c80040e bge r19,r18,1008c20 <__multiply+0x44> + 1008c10: 9027883a mov r19,r18 + 1008c14: 2c800417 ldw r18,16(r5) + 1008c18: 2829883a mov r20,r5 + 1008c1c: 3023883a mov r17,r6 + 1008c20: 88800217 ldw r2,8(r17) + 1008c24: 9ca1883a add r16,r19,r18 + 1008c28: 89400117 ldw r5,4(r17) + 1008c2c: 1400010e bge r2,r16,1008c34 <__multiply+0x58> + 1008c30: 29400044 addi r5,r5,1 + 1008c34: 10086cc0 call 10086cc <_Balloc> + 1008c38: 102b883a mov r21,r2 + 1008c3c: 8405883a add r2,r16,r16 + 1008c40: 1085883a add r2,r2,r2 + 1008c44: a9000504 addi r4,r21,20 + 1008c48: 209d883a add r14,r4,r2 + 1008c4c: 2380042e bgeu r4,r14,1008c60 <__multiply+0x84> + 1008c50: 2005883a mov r2,r4 + 1008c54: 10000015 stw zero,0(r2) + 1008c58: 10800104 addi r2,r2,4 + 1008c5c: 13bffd36 bltu r2,r14,1008c54 <__multiply+0x78> + 1008c60: 9485883a add r2,r18,r18 + 1008c64: 9cc7883a add r3,r19,r19 + 1008c68: a1800504 addi r6,r20,20 + 1008c6c: 1085883a add r2,r2,r2 + 1008c70: 8b400504 addi r13,r17,20 + 1008c74: 18c7883a add r3,r3,r3 + 1008c78: 309f883a add r15,r6,r2 + 1008c7c: 68d7883a add r11,r13,r3 + 1008c80: 33c03b2e bgeu r6,r15,1008d70 <__multiply+0x194> + 1008c84: 2019883a mov r12,r4 + 1008c88: 30800017 ldw r2,0(r6) + 1008c8c: 127fffcc andi r9,r2,65535 + 1008c90: 48001826 beq r9,zero,1008cf4 <__multiply+0x118> + 1008c94: 6811883a mov r8,r13 + 1008c98: 600f883a mov r7,r12 + 1008c9c: 0015883a mov r10,zero + 1008ca0: 40c00017 ldw r3,0(r8) + 1008ca4: 39400017 ldw r5,0(r7) + 1008ca8: 42000104 addi r8,r8,4 + 1008cac: 193fffcc andi r4,r3,65535 + 1008cb0: 4909383a mul r4,r9,r4 + 1008cb4: 1806d43a srli r3,r3,16 + 1008cb8: 28bfffcc andi r2,r5,65535 + 1008cbc: 5085883a add r2,r10,r2 + 1008cc0: 2089883a add r4,r4,r2 + 1008cc4: 48c7383a mul r3,r9,r3 + 1008cc8: 280ad43a srli r5,r5,16 + 1008ccc: 2004d43a srli r2,r4,16 + 1008cd0: 3900000d sth r4,0(r7) + 1008cd4: 1947883a add r3,r3,r5 + 1008cd8: 10c5883a add r2,r2,r3 + 1008cdc: 3880008d sth r2,2(r7) + 1008ce0: 1014d43a srli r10,r2,16 + 1008ce4: 39c00104 addi r7,r7,4 + 1008ce8: 42ffed36 bltu r8,r11,1008ca0 <__multiply+0xc4> + 1008cec: 3a800015 stw r10,0(r7) + 1008cf0: 30800017 ldw r2,0(r6) + 1008cf4: 1012d43a srli r9,r2,16 + 1008cf8: 48001926 beq r9,zero,1008d60 <__multiply+0x184> + 1008cfc: 60800017 ldw r2,0(r12) + 1008d00: 6811883a mov r8,r13 + 1008d04: 600f883a mov r7,r12 + 1008d08: 0015883a mov r10,zero + 1008d0c: 100b883a mov r5,r2 + 1008d10: 41000017 ldw r4,0(r8) + 1008d14: 2806d43a srli r3,r5,16 + 1008d18: 3880000d sth r2,0(r7) + 1008d1c: 20bfffcc andi r2,r4,65535 + 1008d20: 4885383a mul r2,r9,r2 + 1008d24: 50c7883a add r3,r10,r3 + 1008d28: 2008d43a srli r4,r4,16 + 1008d2c: 10c5883a add r2,r2,r3 + 1008d30: 3880008d sth r2,2(r7) + 1008d34: 39c00104 addi r7,r7,4 + 1008d38: 39400017 ldw r5,0(r7) + 1008d3c: 4909383a mul r4,r9,r4 + 1008d40: 1004d43a srli r2,r2,16 + 1008d44: 28ffffcc andi r3,r5,65535 + 1008d48: 20c9883a add r4,r4,r3 + 1008d4c: 1105883a add r2,r2,r4 + 1008d50: 42000104 addi r8,r8,4 + 1008d54: 1014d43a srli r10,r2,16 + 1008d58: 42ffed36 bltu r8,r11,1008d10 <__multiply+0x134> + 1008d5c: 38800015 stw r2,0(r7) + 1008d60: 31800104 addi r6,r6,4 + 1008d64: 33c0022e bgeu r6,r15,1008d70 <__multiply+0x194> + 1008d68: 63000104 addi r12,r12,4 + 1008d6c: 003fc606 br 1008c88 <__multiply+0xac> + 1008d70: 0400090e bge zero,r16,1008d98 <__multiply+0x1bc> + 1008d74: 70bfff17 ldw r2,-4(r14) + 1008d78: 70ffff04 addi r3,r14,-4 + 1008d7c: 10000326 beq r2,zero,1008d8c <__multiply+0x1b0> + 1008d80: 00000506 br 1008d98 <__multiply+0x1bc> + 1008d84: 18800017 ldw r2,0(r3) + 1008d88: 1000031e bne r2,zero,1008d98 <__multiply+0x1bc> + 1008d8c: 843fffc4 addi r16,r16,-1 + 1008d90: 18ffff04 addi r3,r3,-4 + 1008d94: 803ffb1e bne r16,zero,1008d84 <__multiply+0x1a8> + 1008d98: a805883a mov r2,r21 + 1008d9c: ac000415 stw r16,16(r21) + 1008da0: dfc00617 ldw ra,24(sp) + 1008da4: dd400517 ldw r21,20(sp) + 1008da8: dd000417 ldw r20,16(sp) + 1008dac: dcc00317 ldw r19,12(sp) + 1008db0: dc800217 ldw r18,8(sp) + 1008db4: dc400117 ldw r17,4(sp) + 1008db8: dc000017 ldw r16,0(sp) + 1008dbc: dec00704 addi sp,sp,28 + 1008dc0: f800283a ret + +01008dc4 <__i2b>: + 1008dc4: defffd04 addi sp,sp,-12 + 1008dc8: dc000015 stw r16,0(sp) + 1008dcc: 04000044 movi r16,1 + 1008dd0: dc800115 stw r18,4(sp) + 1008dd4: 2825883a mov r18,r5 + 1008dd8: 800b883a mov r5,r16 + 1008ddc: dfc00215 stw ra,8(sp) + 1008de0: 10086cc0 call 10086cc <_Balloc> + 1008de4: 14000415 stw r16,16(r2) + 1008de8: 14800515 stw r18,20(r2) + 1008dec: dfc00217 ldw ra,8(sp) + 1008df0: dc800117 ldw r18,4(sp) + 1008df4: dc000017 ldw r16,0(sp) + 1008df8: dec00304 addi sp,sp,12 + 1008dfc: f800283a ret + +01008e00 <__multadd>: + 1008e00: defffa04 addi sp,sp,-24 + 1008e04: dc800215 stw r18,8(sp) + 1008e08: 2c800417 ldw r18,16(r5) + 1008e0c: dd000415 stw r20,16(sp) + 1008e10: dcc00315 stw r19,12(sp) + 1008e14: dc000015 stw r16,0(sp) + 1008e18: dfc00515 stw ra,20(sp) + 1008e1c: 3821883a mov r16,r7 + 1008e20: dc400115 stw r17,4(sp) + 1008e24: 2827883a mov r19,r5 + 1008e28: 2029883a mov r20,r4 + 1008e2c: 2a000504 addi r8,r5,20 + 1008e30: 000f883a mov r7,zero + 1008e34: 40800017 ldw r2,0(r8) + 1008e38: 39c00044 addi r7,r7,1 + 1008e3c: 10ffffcc andi r3,r2,65535 + 1008e40: 1987383a mul r3,r3,r6 + 1008e44: 1004d43a srli r2,r2,16 + 1008e48: 1c07883a add r3,r3,r16 + 1008e4c: 180ad43a srli r5,r3,16 + 1008e50: 1185383a mul r2,r2,r6 + 1008e54: 18ffffcc andi r3,r3,65535 + 1008e58: 1145883a add r2,r2,r5 + 1008e5c: 1008943a slli r4,r2,16 + 1008e60: 1020d43a srli r16,r2,16 + 1008e64: 20c9883a add r4,r4,r3 + 1008e68: 41000015 stw r4,0(r8) + 1008e6c: 42000104 addi r8,r8,4 + 1008e70: 3cbff016 blt r7,r18,1008e34 <__multadd+0x34> + 1008e74: 80000826 beq r16,zero,1008e98 <__multadd+0x98> + 1008e78: 98800217 ldw r2,8(r19) + 1008e7c: 90800f0e bge r18,r2,1008ebc <__multadd+0xbc> + 1008e80: 9485883a add r2,r18,r18 + 1008e84: 1085883a add r2,r2,r2 + 1008e88: 14c5883a add r2,r2,r19 + 1008e8c: 90c00044 addi r3,r18,1 + 1008e90: 14000515 stw r16,20(r2) + 1008e94: 98c00415 stw r3,16(r19) + 1008e98: 9805883a mov r2,r19 + 1008e9c: dfc00517 ldw ra,20(sp) + 1008ea0: dd000417 ldw r20,16(sp) + 1008ea4: dcc00317 ldw r19,12(sp) + 1008ea8: dc800217 ldw r18,8(sp) + 1008eac: dc400117 ldw r17,4(sp) + 1008eb0: dc000017 ldw r16,0(sp) + 1008eb4: dec00604 addi sp,sp,24 + 1008eb8: f800283a ret + 1008ebc: 99400117 ldw r5,4(r19) + 1008ec0: a009883a mov r4,r20 + 1008ec4: 29400044 addi r5,r5,1 + 1008ec8: 10086cc0 call 10086cc <_Balloc> + 1008ecc: 99800417 ldw r6,16(r19) + 1008ed0: 99400304 addi r5,r19,12 + 1008ed4: 11000304 addi r4,r2,12 + 1008ed8: 318d883a add r6,r6,r6 + 1008edc: 318d883a add r6,r6,r6 + 1008ee0: 31800204 addi r6,r6,8 + 1008ee4: 1023883a mov r17,r2 + 1008ee8: 1007fcc0 call 1007fcc + 1008eec: 980b883a mov r5,r19 + 1008ef0: a009883a mov r4,r20 + 1008ef4: 100814c0 call 100814c <_Bfree> + 1008ef8: 8827883a mov r19,r17 + 1008efc: 003fe006 br 1008e80 <__multadd+0x80> + +01008f00 <__pow5mult>: + 1008f00: defffa04 addi sp,sp,-24 + 1008f04: 308000cc andi r2,r6,3 + 1008f08: dd000415 stw r20,16(sp) + 1008f0c: dcc00315 stw r19,12(sp) + 1008f10: dc000015 stw r16,0(sp) + 1008f14: dfc00515 stw ra,20(sp) + 1008f18: dc800215 stw r18,8(sp) + 1008f1c: dc400115 stw r17,4(sp) + 1008f20: 3021883a mov r16,r6 + 1008f24: 2027883a mov r19,r4 + 1008f28: 2829883a mov r20,r5 + 1008f2c: 10002b1e bne r2,zero,1008fdc <__pow5mult+0xdc> + 1008f30: 8025d0ba srai r18,r16,2 + 1008f34: 90001b26 beq r18,zero,1008fa4 <__pow5mult+0xa4> + 1008f38: 9c001217 ldw r16,72(r19) + 1008f3c: 8000081e bne r16,zero,1008f60 <__pow5mult+0x60> + 1008f40: 00003006 br 1009004 <__pow5mult+0x104> + 1008f44: 800b883a mov r5,r16 + 1008f48: 800d883a mov r6,r16 + 1008f4c: 9809883a mov r4,r19 + 1008f50: 90001426 beq r18,zero,1008fa4 <__pow5mult+0xa4> + 1008f54: 80800017 ldw r2,0(r16) + 1008f58: 10001b26 beq r2,zero,1008fc8 <__pow5mult+0xc8> + 1008f5c: 1021883a mov r16,r2 + 1008f60: 9080004c andi r2,r18,1 + 1008f64: 1005003a cmpeq r2,r2,zero + 1008f68: 9025d07a srai r18,r18,1 + 1008f6c: 800d883a mov r6,r16 + 1008f70: 9809883a mov r4,r19 + 1008f74: a00b883a mov r5,r20 + 1008f78: 103ff21e bne r2,zero,1008f44 <__pow5mult+0x44> + 1008f7c: 1008bdc0 call 1008bdc <__multiply> + 1008f80: a00b883a mov r5,r20 + 1008f84: 9809883a mov r4,r19 + 1008f88: 1023883a mov r17,r2 + 1008f8c: 100814c0 call 100814c <_Bfree> + 1008f90: 8829883a mov r20,r17 + 1008f94: 800b883a mov r5,r16 + 1008f98: 800d883a mov r6,r16 + 1008f9c: 9809883a mov r4,r19 + 1008fa0: 903fec1e bne r18,zero,1008f54 <__pow5mult+0x54> + 1008fa4: a005883a mov r2,r20 + 1008fa8: dfc00517 ldw ra,20(sp) + 1008fac: dd000417 ldw r20,16(sp) + 1008fb0: dcc00317 ldw r19,12(sp) + 1008fb4: dc800217 ldw r18,8(sp) + 1008fb8: dc400117 ldw r17,4(sp) + 1008fbc: dc000017 ldw r16,0(sp) + 1008fc0: dec00604 addi sp,sp,24 + 1008fc4: f800283a ret + 1008fc8: 1008bdc0 call 1008bdc <__multiply> + 1008fcc: 80800015 stw r2,0(r16) + 1008fd0: 1021883a mov r16,r2 + 1008fd4: 10000015 stw zero,0(r2) + 1008fd8: 003fe106 br 1008f60 <__pow5mult+0x60> + 1008fdc: 1085883a add r2,r2,r2 + 1008fe0: 00c040b4 movhi r3,258 + 1008fe4: 18e3e604 addi r3,r3,-28776 + 1008fe8: 1085883a add r2,r2,r2 + 1008fec: 10c5883a add r2,r2,r3 + 1008ff0: 11bfff17 ldw r6,-4(r2) + 1008ff4: 000f883a mov r7,zero + 1008ff8: 1008e000 call 1008e00 <__multadd> + 1008ffc: 1029883a mov r20,r2 + 1009000: 003fcb06 br 1008f30 <__pow5mult+0x30> + 1009004: 9809883a mov r4,r19 + 1009008: 01409c44 movi r5,625 + 100900c: 1008dc40 call 1008dc4 <__i2b> + 1009010: 98801215 stw r2,72(r19) + 1009014: 1021883a mov r16,r2 + 1009018: 10000015 stw zero,0(r2) + 100901c: 003fd006 br 1008f60 <__pow5mult+0x60> + +01009020 <__s2b>: + 1009020: defff904 addi sp,sp,-28 + 1009024: dcc00315 stw r19,12(sp) + 1009028: dc800215 stw r18,8(sp) + 100902c: 2827883a mov r19,r5 + 1009030: 2025883a mov r18,r4 + 1009034: 01400244 movi r5,9 + 1009038: 39000204 addi r4,r7,8 + 100903c: dd000415 stw r20,16(sp) + 1009040: dc400115 stw r17,4(sp) + 1009044: dfc00615 stw ra,24(sp) + 1009048: dd400515 stw r21,20(sp) + 100904c: dc000015 stw r16,0(sp) + 1009050: 3829883a mov r20,r7 + 1009054: 3023883a mov r17,r6 + 1009058: 100bb740 call 100bb74 <__divsi3> + 100905c: 00c00044 movi r3,1 + 1009060: 1880350e bge r3,r2,1009138 <__s2b+0x118> + 1009064: 000b883a mov r5,zero + 1009068: 18c7883a add r3,r3,r3 + 100906c: 29400044 addi r5,r5,1 + 1009070: 18bffd16 blt r3,r2,1009068 <__s2b+0x48> + 1009074: 9009883a mov r4,r18 + 1009078: 10086cc0 call 10086cc <_Balloc> + 100907c: 1011883a mov r8,r2 + 1009080: d8800717 ldw r2,28(sp) + 1009084: 00c00044 movi r3,1 + 1009088: 01800244 movi r6,9 + 100908c: 40800515 stw r2,20(r8) + 1009090: 40c00415 stw r3,16(r8) + 1009094: 3440260e bge r6,r17,1009130 <__s2b+0x110> + 1009098: 3021883a mov r16,r6 + 100909c: 99ab883a add r21,r19,r6 + 10090a0: 9c05883a add r2,r19,r16 + 10090a4: 11c00007 ldb r7,0(r2) + 10090a8: 400b883a mov r5,r8 + 10090ac: 9009883a mov r4,r18 + 10090b0: 39fff404 addi r7,r7,-48 + 10090b4: 01800284 movi r6,10 + 10090b8: 1008e000 call 1008e00 <__multadd> + 10090bc: 84000044 addi r16,r16,1 + 10090c0: 1011883a mov r8,r2 + 10090c4: 8c3ff61e bne r17,r16,10090a0 <__s2b+0x80> + 10090c8: ac45883a add r2,r21,r17 + 10090cc: 117ffe04 addi r5,r2,-8 + 10090d0: 880d883a mov r6,r17 + 10090d4: 35000c0e bge r6,r20,1009108 <__s2b+0xe8> + 10090d8: a185c83a sub r2,r20,r6 + 10090dc: 2821883a mov r16,r5 + 10090e0: 28a3883a add r17,r5,r2 + 10090e4: 81c00007 ldb r7,0(r16) + 10090e8: 400b883a mov r5,r8 + 10090ec: 9009883a mov r4,r18 + 10090f0: 39fff404 addi r7,r7,-48 + 10090f4: 01800284 movi r6,10 + 10090f8: 1008e000 call 1008e00 <__multadd> + 10090fc: 84000044 addi r16,r16,1 + 1009100: 1011883a mov r8,r2 + 1009104: 847ff71e bne r16,r17,10090e4 <__s2b+0xc4> + 1009108: 4005883a mov r2,r8 + 100910c: dfc00617 ldw ra,24(sp) + 1009110: dd400517 ldw r21,20(sp) + 1009114: dd000417 ldw r20,16(sp) + 1009118: dcc00317 ldw r19,12(sp) + 100911c: dc800217 ldw r18,8(sp) + 1009120: dc400117 ldw r17,4(sp) + 1009124: dc000017 ldw r16,0(sp) + 1009128: dec00704 addi sp,sp,28 + 100912c: f800283a ret + 1009130: 99400284 addi r5,r19,10 + 1009134: 003fe706 br 10090d4 <__s2b+0xb4> + 1009138: 000b883a mov r5,zero + 100913c: 003fcd06 br 1009074 <__s2b+0x54> + +01009140 <_realloc_r>: + 1009140: defff404 addi sp,sp,-48 + 1009144: dd800815 stw r22,32(sp) + 1009148: dc800415 stw r18,16(sp) + 100914c: dc400315 stw r17,12(sp) + 1009150: dfc00b15 stw ra,44(sp) + 1009154: df000a15 stw fp,40(sp) + 1009158: ddc00915 stw r23,36(sp) + 100915c: dd400715 stw r21,28(sp) + 1009160: dd000615 stw r20,24(sp) + 1009164: dcc00515 stw r19,20(sp) + 1009168: dc000215 stw r16,8(sp) + 100916c: 2825883a mov r18,r5 + 1009170: 3023883a mov r17,r6 + 1009174: 202d883a mov r22,r4 + 1009178: 2800c926 beq r5,zero,10094a0 <_realloc_r+0x360> + 100917c: 100d0a00 call 100d0a0 <__malloc_lock> + 1009180: 943ffe04 addi r16,r18,-8 + 1009184: 88c002c4 addi r3,r17,11 + 1009188: 00800584 movi r2,22 + 100918c: 82000117 ldw r8,4(r16) + 1009190: 10c01b2e bgeu r2,r3,1009200 <_realloc_r+0xc0> + 1009194: 00bffe04 movi r2,-8 + 1009198: 188e703a and r7,r3,r2 + 100919c: 3839883a mov fp,r7 + 10091a0: 38001a16 blt r7,zero,100920c <_realloc_r+0xcc> + 10091a4: e4401936 bltu fp,r17,100920c <_realloc_r+0xcc> + 10091a8: 013fff04 movi r4,-4 + 10091ac: 4126703a and r19,r8,r4 + 10091b0: 99c02616 blt r19,r7,100924c <_realloc_r+0x10c> + 10091b4: 802b883a mov r21,r16 + 10091b8: 9829883a mov r20,r19 + 10091bc: 84000204 addi r16,r16,8 + 10091c0: a80f883a mov r7,r21 + 10091c4: a70dc83a sub r6,r20,fp + 10091c8: 008003c4 movi r2,15 + 10091cc: 1180c136 bltu r2,r6,10094d4 <_realloc_r+0x394> + 10091d0: 38800117 ldw r2,4(r7) + 10091d4: a549883a add r4,r20,r21 + 10091d8: 1080004c andi r2,r2,1 + 10091dc: a084b03a or r2,r20,r2 + 10091e0: 38800115 stw r2,4(r7) + 10091e4: 20c00117 ldw r3,4(r4) + 10091e8: 18c00054 ori r3,r3,1 + 10091ec: 20c00115 stw r3,4(r4) + 10091f0: b009883a mov r4,r22 + 10091f4: 100d1a80 call 100d1a8 <__malloc_unlock> + 10091f8: 8023883a mov r17,r16 + 10091fc: 00000606 br 1009218 <_realloc_r+0xd8> + 1009200: 01c00404 movi r7,16 + 1009204: 3839883a mov fp,r7 + 1009208: e47fe72e bgeu fp,r17,10091a8 <_realloc_r+0x68> + 100920c: 00800304 movi r2,12 + 1009210: 0023883a mov r17,zero + 1009214: b0800015 stw r2,0(r22) + 1009218: 8805883a mov r2,r17 + 100921c: dfc00b17 ldw ra,44(sp) + 1009220: df000a17 ldw fp,40(sp) + 1009224: ddc00917 ldw r23,36(sp) + 1009228: dd800817 ldw r22,32(sp) + 100922c: dd400717 ldw r21,28(sp) + 1009230: dd000617 ldw r20,24(sp) + 1009234: dcc00517 ldw r19,20(sp) + 1009238: dc800417 ldw r18,16(sp) + 100923c: dc400317 ldw r17,12(sp) + 1009240: dc000217 ldw r16,8(sp) + 1009244: dec00c04 addi sp,sp,48 + 1009248: f800283a ret + 100924c: 008040b4 movhi r2,258 + 1009250: 10a49004 addi r2,r2,-28096 + 1009254: 12400217 ldw r9,8(r2) + 1009258: 84cd883a add r6,r16,r19 + 100925c: 802b883a mov r21,r16 + 1009260: 3240b926 beq r6,r9,1009548 <_realloc_r+0x408> + 1009264: 31400117 ldw r5,4(r6) + 1009268: 00bfff84 movi r2,-2 + 100926c: 2884703a and r2,r5,r2 + 1009270: 1185883a add r2,r2,r6 + 1009274: 10c00117 ldw r3,4(r2) + 1009278: 18c0004c andi r3,r3,1 + 100927c: 1807003a cmpeq r3,r3,zero + 1009280: 1800a326 beq r3,zero,1009510 <_realloc_r+0x3d0> + 1009284: 2908703a and r4,r5,r4 + 1009288: 9929883a add r20,r19,r4 + 100928c: a1c0a30e bge r20,r7,100951c <_realloc_r+0x3dc> + 1009290: 4080004c andi r2,r8,1 + 1009294: 1000551e bne r2,zero,10093ec <_realloc_r+0x2ac> + 1009298: 80800017 ldw r2,0(r16) + 100929c: 80afc83a sub r23,r16,r2 + 10092a0: b8c00117 ldw r3,4(r23) + 10092a4: 00bfff04 movi r2,-4 + 10092a8: 1884703a and r2,r3,r2 + 10092ac: 30002e26 beq r6,zero,1009368 <_realloc_r+0x228> + 10092b0: 3240b926 beq r6,r9,1009598 <_realloc_r+0x458> + 10092b4: 98a9883a add r20,r19,r2 + 10092b8: 2509883a add r4,r4,r20 + 10092bc: d9000015 stw r4,0(sp) + 10092c0: 21c02a16 blt r4,r7,100936c <_realloc_r+0x22c> + 10092c4: 30800317 ldw r2,12(r6) + 10092c8: 30c00217 ldw r3,8(r6) + 10092cc: 01400904 movi r5,36 + 10092d0: 99bfff04 addi r6,r19,-4 + 10092d4: 18800315 stw r2,12(r3) + 10092d8: 10c00215 stw r3,8(r2) + 10092dc: b9000317 ldw r4,12(r23) + 10092e0: b8800217 ldw r2,8(r23) + 10092e4: b82b883a mov r21,r23 + 10092e8: bc000204 addi r16,r23,8 + 10092ec: 20800215 stw r2,8(r4) + 10092f0: 11000315 stw r4,12(r2) + 10092f4: 2980e436 bltu r5,r6,1009688 <_realloc_r+0x548> + 10092f8: 008004c4 movi r2,19 + 10092fc: 9009883a mov r4,r18 + 1009300: 8011883a mov r8,r16 + 1009304: 11800f2e bgeu r2,r6,1009344 <_realloc_r+0x204> + 1009308: 90800017 ldw r2,0(r18) + 100930c: ba000404 addi r8,r23,16 + 1009310: 91000204 addi r4,r18,8 + 1009314: b8800215 stw r2,8(r23) + 1009318: 90c00117 ldw r3,4(r18) + 100931c: 008006c4 movi r2,27 + 1009320: b8c00315 stw r3,12(r23) + 1009324: 1180072e bgeu r2,r6,1009344 <_realloc_r+0x204> + 1009328: 90c00217 ldw r3,8(r18) + 100932c: ba000604 addi r8,r23,24 + 1009330: 91000404 addi r4,r18,16 + 1009334: b8c00415 stw r3,16(r23) + 1009338: 90800317 ldw r2,12(r18) + 100933c: b8800515 stw r2,20(r23) + 1009340: 3140e726 beq r6,r5,10096e0 <_realloc_r+0x5a0> + 1009344: 20800017 ldw r2,0(r4) + 1009348: dd000017 ldw r20,0(sp) + 100934c: b80f883a mov r7,r23 + 1009350: 40800015 stw r2,0(r8) + 1009354: 20c00117 ldw r3,4(r4) + 1009358: 40c00115 stw r3,4(r8) + 100935c: 20800217 ldw r2,8(r4) + 1009360: 40800215 stw r2,8(r8) + 1009364: 003f9706 br 10091c4 <_realloc_r+0x84> + 1009368: 98a9883a add r20,r19,r2 + 100936c: a1c01f16 blt r20,r7,10093ec <_realloc_r+0x2ac> + 1009370: b8c00317 ldw r3,12(r23) + 1009374: b8800217 ldw r2,8(r23) + 1009378: 99bfff04 addi r6,r19,-4 + 100937c: 01400904 movi r5,36 + 1009380: b82b883a mov r21,r23 + 1009384: 18800215 stw r2,8(r3) + 1009388: 10c00315 stw r3,12(r2) + 100938c: bc000204 addi r16,r23,8 + 1009390: 2980c336 bltu r5,r6,10096a0 <_realloc_r+0x560> + 1009394: 008004c4 movi r2,19 + 1009398: 9009883a mov r4,r18 + 100939c: 8011883a mov r8,r16 + 10093a0: 11800f2e bgeu r2,r6,10093e0 <_realloc_r+0x2a0> + 10093a4: 90800017 ldw r2,0(r18) + 10093a8: ba000404 addi r8,r23,16 + 10093ac: 91000204 addi r4,r18,8 + 10093b0: b8800215 stw r2,8(r23) + 10093b4: 90c00117 ldw r3,4(r18) + 10093b8: 008006c4 movi r2,27 + 10093bc: b8c00315 stw r3,12(r23) + 10093c0: 1180072e bgeu r2,r6,10093e0 <_realloc_r+0x2a0> + 10093c4: 90c00217 ldw r3,8(r18) + 10093c8: ba000604 addi r8,r23,24 + 10093cc: 91000404 addi r4,r18,16 + 10093d0: b8c00415 stw r3,16(r23) + 10093d4: 90800317 ldw r2,12(r18) + 10093d8: b8800515 stw r2,20(r23) + 10093dc: 3140c726 beq r6,r5,10096fc <_realloc_r+0x5bc> + 10093e0: 20800017 ldw r2,0(r4) + 10093e4: b80f883a mov r7,r23 + 10093e8: 003fd906 br 1009350 <_realloc_r+0x210> + 10093ec: 880b883a mov r5,r17 + 10093f0: b009883a mov r4,r22 + 10093f4: 10027dc0 call 10027dc <_malloc_r> + 10093f8: 1023883a mov r17,r2 + 10093fc: 10002526 beq r2,zero,1009494 <_realloc_r+0x354> + 1009400: 80800117 ldw r2,4(r16) + 1009404: 00ffff84 movi r3,-2 + 1009408: 893ffe04 addi r4,r17,-8 + 100940c: 10c4703a and r2,r2,r3 + 1009410: 8085883a add r2,r16,r2 + 1009414: 20809526 beq r4,r2,100966c <_realloc_r+0x52c> + 1009418: 99bfff04 addi r6,r19,-4 + 100941c: 01c00904 movi r7,36 + 1009420: 39804536 bltu r7,r6,1009538 <_realloc_r+0x3f8> + 1009424: 008004c4 movi r2,19 + 1009428: 9009883a mov r4,r18 + 100942c: 880b883a mov r5,r17 + 1009430: 11800f2e bgeu r2,r6,1009470 <_realloc_r+0x330> + 1009434: 90800017 ldw r2,0(r18) + 1009438: 89400204 addi r5,r17,8 + 100943c: 91000204 addi r4,r18,8 + 1009440: 88800015 stw r2,0(r17) + 1009444: 90c00117 ldw r3,4(r18) + 1009448: 008006c4 movi r2,27 + 100944c: 88c00115 stw r3,4(r17) + 1009450: 1180072e bgeu r2,r6,1009470 <_realloc_r+0x330> + 1009454: 90c00217 ldw r3,8(r18) + 1009458: 89400404 addi r5,r17,16 + 100945c: 91000404 addi r4,r18,16 + 1009460: 88c00215 stw r3,8(r17) + 1009464: 90800317 ldw r2,12(r18) + 1009468: 88800315 stw r2,12(r17) + 100946c: 31c09126 beq r6,r7,10096b4 <_realloc_r+0x574> + 1009470: 20800017 ldw r2,0(r4) + 1009474: 28800015 stw r2,0(r5) + 1009478: 20c00117 ldw r3,4(r4) + 100947c: 28c00115 stw r3,4(r5) + 1009480: 20800217 ldw r2,8(r4) + 1009484: 28800215 stw r2,8(r5) + 1009488: 900b883a mov r5,r18 + 100948c: b009883a mov r4,r22 + 1009490: 10073600 call 1007360 <_free_r> + 1009494: b009883a mov r4,r22 + 1009498: 100d1a80 call 100d1a8 <__malloc_unlock> + 100949c: 003f5e06 br 1009218 <_realloc_r+0xd8> + 10094a0: 300b883a mov r5,r6 + 10094a4: dfc00b17 ldw ra,44(sp) + 10094a8: df000a17 ldw fp,40(sp) + 10094ac: ddc00917 ldw r23,36(sp) + 10094b0: dd800817 ldw r22,32(sp) + 10094b4: dd400717 ldw r21,28(sp) + 10094b8: dd000617 ldw r20,24(sp) + 10094bc: dcc00517 ldw r19,20(sp) + 10094c0: dc800417 ldw r18,16(sp) + 10094c4: dc400317 ldw r17,12(sp) + 10094c8: dc000217 ldw r16,8(sp) + 10094cc: dec00c04 addi sp,sp,48 + 10094d0: 10027dc1 jmpi 10027dc <_malloc_r> + 10094d4: 38800117 ldw r2,4(r7) + 10094d8: e54b883a add r5,fp,r21 + 10094dc: 31000054 ori r4,r6,1 + 10094e0: 1080004c andi r2,r2,1 + 10094e4: 1704b03a or r2,r2,fp + 10094e8: 38800115 stw r2,4(r7) + 10094ec: 29000115 stw r4,4(r5) + 10094f0: 2987883a add r3,r5,r6 + 10094f4: 18800117 ldw r2,4(r3) + 10094f8: 29400204 addi r5,r5,8 + 10094fc: b009883a mov r4,r22 + 1009500: 10800054 ori r2,r2,1 + 1009504: 18800115 stw r2,4(r3) + 1009508: 10073600 call 1007360 <_free_r> + 100950c: 003f3806 br 10091f0 <_realloc_r+0xb0> + 1009510: 000d883a mov r6,zero + 1009514: 0009883a mov r4,zero + 1009518: 003f5d06 br 1009290 <_realloc_r+0x150> + 100951c: 30c00217 ldw r3,8(r6) + 1009520: 30800317 ldw r2,12(r6) + 1009524: 800f883a mov r7,r16 + 1009528: 84000204 addi r16,r16,8 + 100952c: 10c00215 stw r3,8(r2) + 1009530: 18800315 stw r2,12(r3) + 1009534: 003f2306 br 10091c4 <_realloc_r+0x84> + 1009538: 8809883a mov r4,r17 + 100953c: 900b883a mov r5,r18 + 1009540: 100806c0 call 100806c + 1009544: 003fd006 br 1009488 <_realloc_r+0x348> + 1009548: 30800117 ldw r2,4(r6) + 100954c: e0c00404 addi r3,fp,16 + 1009550: 1108703a and r4,r2,r4 + 1009554: 9905883a add r2,r19,r4 + 1009558: 10ff4d16 blt r2,r3,1009290 <_realloc_r+0x150> + 100955c: 1705c83a sub r2,r2,fp + 1009560: 870b883a add r5,r16,fp + 1009564: 10800054 ori r2,r2,1 + 1009568: 28800115 stw r2,4(r5) + 100956c: 80c00117 ldw r3,4(r16) + 1009570: 008040b4 movhi r2,258 + 1009574: 10a49004 addi r2,r2,-28096 + 1009578: b009883a mov r4,r22 + 100957c: 18c0004c andi r3,r3,1 + 1009580: e0c6b03a or r3,fp,r3 + 1009584: 11400215 stw r5,8(r2) + 1009588: 80c00115 stw r3,4(r16) + 100958c: 100d1a80 call 100d1a8 <__malloc_unlock> + 1009590: 84400204 addi r17,r16,8 + 1009594: 003f2006 br 1009218 <_realloc_r+0xd8> + 1009598: 98a9883a add r20,r19,r2 + 100959c: 2509883a add r4,r4,r20 + 10095a0: e0800404 addi r2,fp,16 + 10095a4: d9000115 stw r4,4(sp) + 10095a8: 20bf7016 blt r4,r2,100936c <_realloc_r+0x22c> + 10095ac: b8c00317 ldw r3,12(r23) + 10095b0: b8800217 ldw r2,8(r23) + 10095b4: 99bfff04 addi r6,r19,-4 + 10095b8: 01400904 movi r5,36 + 10095bc: 18800215 stw r2,8(r3) + 10095c0: 10c00315 stw r3,12(r2) + 10095c4: bc400204 addi r17,r23,8 + 10095c8: 29804136 bltu r5,r6,10096d0 <_realloc_r+0x590> + 10095cc: 008004c4 movi r2,19 + 10095d0: 9009883a mov r4,r18 + 10095d4: 880f883a mov r7,r17 + 10095d8: 11800f2e bgeu r2,r6,1009618 <_realloc_r+0x4d8> + 10095dc: 90800017 ldw r2,0(r18) + 10095e0: b9c00404 addi r7,r23,16 + 10095e4: 91000204 addi r4,r18,8 + 10095e8: b8800215 stw r2,8(r23) + 10095ec: 90c00117 ldw r3,4(r18) + 10095f0: 008006c4 movi r2,27 + 10095f4: b8c00315 stw r3,12(r23) + 10095f8: 1180072e bgeu r2,r6,1009618 <_realloc_r+0x4d8> + 10095fc: 90c00217 ldw r3,8(r18) + 1009600: b9c00604 addi r7,r23,24 + 1009604: 91000404 addi r4,r18,16 + 1009608: b8c00415 stw r3,16(r23) + 100960c: 90800317 ldw r2,12(r18) + 1009610: b8800515 stw r2,20(r23) + 1009614: 31404026 beq r6,r5,1009718 <_realloc_r+0x5d8> + 1009618: 20800017 ldw r2,0(r4) + 100961c: 38800015 stw r2,0(r7) + 1009620: 20c00117 ldw r3,4(r4) + 1009624: 38c00115 stw r3,4(r7) + 1009628: 20800217 ldw r2,8(r4) + 100962c: 38800215 stw r2,8(r7) + 1009630: d8c00117 ldw r3,4(sp) + 1009634: bf0b883a add r5,r23,fp + 1009638: b009883a mov r4,r22 + 100963c: 1f05c83a sub r2,r3,fp + 1009640: 10800054 ori r2,r2,1 + 1009644: 28800115 stw r2,4(r5) + 1009648: b8c00117 ldw r3,4(r23) + 100964c: 008040b4 movhi r2,258 + 1009650: 10a49004 addi r2,r2,-28096 + 1009654: 11400215 stw r5,8(r2) + 1009658: 18c0004c andi r3,r3,1 + 100965c: e0c6b03a or r3,fp,r3 + 1009660: b8c00115 stw r3,4(r23) + 1009664: 100d1a80 call 100d1a8 <__malloc_unlock> + 1009668: 003eeb06 br 1009218 <_realloc_r+0xd8> + 100966c: 20800117 ldw r2,4(r4) + 1009670: 00ffff04 movi r3,-4 + 1009674: 800f883a mov r7,r16 + 1009678: 10c4703a and r2,r2,r3 + 100967c: 98a9883a add r20,r19,r2 + 1009680: 84000204 addi r16,r16,8 + 1009684: 003ecf06 br 10091c4 <_realloc_r+0x84> + 1009688: 900b883a mov r5,r18 + 100968c: 8009883a mov r4,r16 + 1009690: 100806c0 call 100806c + 1009694: dd000017 ldw r20,0(sp) + 1009698: b80f883a mov r7,r23 + 100969c: 003ec906 br 10091c4 <_realloc_r+0x84> + 10096a0: 900b883a mov r5,r18 + 10096a4: 8009883a mov r4,r16 + 10096a8: 100806c0 call 100806c + 10096ac: b80f883a mov r7,r23 + 10096b0: 003ec406 br 10091c4 <_realloc_r+0x84> + 10096b4: 90c00417 ldw r3,16(r18) + 10096b8: 89400604 addi r5,r17,24 + 10096bc: 91000604 addi r4,r18,24 + 10096c0: 88c00415 stw r3,16(r17) + 10096c4: 90800517 ldw r2,20(r18) + 10096c8: 88800515 stw r2,20(r17) + 10096cc: 003f6806 br 1009470 <_realloc_r+0x330> + 10096d0: 900b883a mov r5,r18 + 10096d4: 8809883a mov r4,r17 + 10096d8: 100806c0 call 100806c + 10096dc: 003fd406 br 1009630 <_realloc_r+0x4f0> + 10096e0: 90c00417 ldw r3,16(r18) + 10096e4: 91000604 addi r4,r18,24 + 10096e8: ba000804 addi r8,r23,32 + 10096ec: b8c00615 stw r3,24(r23) + 10096f0: 90800517 ldw r2,20(r18) + 10096f4: b8800715 stw r2,28(r23) + 10096f8: 003f1206 br 1009344 <_realloc_r+0x204> + 10096fc: 90c00417 ldw r3,16(r18) + 1009700: 91000604 addi r4,r18,24 + 1009704: ba000804 addi r8,r23,32 + 1009708: b8c00615 stw r3,24(r23) + 100970c: 90800517 ldw r2,20(r18) + 1009710: b8800715 stw r2,28(r23) + 1009714: 003f3206 br 10093e0 <_realloc_r+0x2a0> + 1009718: 90c00417 ldw r3,16(r18) + 100971c: 91000604 addi r4,r18,24 + 1009720: b9c00804 addi r7,r23,32 + 1009724: b8c00615 stw r3,24(r23) + 1009728: 90800517 ldw r2,20(r18) + 100972c: b8800715 stw r2,28(r23) + 1009730: 003fb906 br 1009618 <_realloc_r+0x4d8> + +01009734 <__isinfd>: + 1009734: 200d883a mov r6,r4 + 1009738: 0109c83a sub r4,zero,r4 + 100973c: 2188b03a or r4,r4,r6 + 1009740: 2008d7fa srli r4,r4,31 + 1009744: 00a00034 movhi r2,32768 + 1009748: 10bfffc4 addi r2,r2,-1 + 100974c: 1144703a and r2,r2,r5 + 1009750: 2088b03a or r4,r4,r2 + 1009754: 009ffc34 movhi r2,32752 + 1009758: 1105c83a sub r2,r2,r4 + 100975c: 0087c83a sub r3,zero,r2 + 1009760: 10c4b03a or r2,r2,r3 + 1009764: 1004d7fa srli r2,r2,31 + 1009768: 00c00044 movi r3,1 + 100976c: 1885c83a sub r2,r3,r2 + 1009770: f800283a ret + +01009774 <__isnand>: + 1009774: 200d883a mov r6,r4 + 1009778: 0109c83a sub r4,zero,r4 + 100977c: 2188b03a or r4,r4,r6 + 1009780: 2008d7fa srli r4,r4,31 + 1009784: 00a00034 movhi r2,32768 + 1009788: 10bfffc4 addi r2,r2,-1 + 100978c: 1144703a and r2,r2,r5 + 1009790: 2088b03a or r4,r4,r2 + 1009794: 009ffc34 movhi r2,32752 + 1009798: 1105c83a sub r2,r2,r4 + 100979c: 1004d7fa srli r2,r2,31 + 10097a0: f800283a ret + +010097a4 <__sclose>: + 10097a4: 2940038f ldh r5,14(r5) + 10097a8: 1009ad81 jmpi 1009ad8 <_close_r> + +010097ac <__sseek>: + 10097ac: defffe04 addi sp,sp,-8 + 10097b0: dc000015 stw r16,0(sp) + 10097b4: 2821883a mov r16,r5 + 10097b8: 2940038f ldh r5,14(r5) + 10097bc: dfc00115 stw ra,4(sp) + 10097c0: 1009d500 call 1009d50 <_lseek_r> + 10097c4: 1007883a mov r3,r2 + 10097c8: 00bfffc4 movi r2,-1 + 10097cc: 18800926 beq r3,r2,10097f4 <__sseek+0x48> + 10097d0: 8080030b ldhu r2,12(r16) + 10097d4: 80c01415 stw r3,80(r16) + 10097d8: 10840014 ori r2,r2,4096 + 10097dc: 8080030d sth r2,12(r16) + 10097e0: 1805883a mov r2,r3 + 10097e4: dfc00117 ldw ra,4(sp) + 10097e8: dc000017 ldw r16,0(sp) + 10097ec: dec00204 addi sp,sp,8 + 10097f0: f800283a ret + 10097f4: 8080030b ldhu r2,12(r16) + 10097f8: 10bbffcc andi r2,r2,61439 + 10097fc: 8080030d sth r2,12(r16) + 1009800: 1805883a mov r2,r3 + 1009804: dfc00117 ldw ra,4(sp) + 1009808: dc000017 ldw r16,0(sp) + 100980c: dec00204 addi sp,sp,8 + 1009810: f800283a ret + +01009814 <__swrite>: + 1009814: 2880030b ldhu r2,12(r5) + 1009818: defffb04 addi sp,sp,-20 + 100981c: dcc00315 stw r19,12(sp) + 1009820: 1080400c andi r2,r2,256 + 1009824: dc800215 stw r18,8(sp) + 1009828: dc400115 stw r17,4(sp) + 100982c: dc000015 stw r16,0(sp) + 1009830: 3027883a mov r19,r6 + 1009834: 3825883a mov r18,r7 + 1009838: dfc00415 stw ra,16(sp) + 100983c: 2821883a mov r16,r5 + 1009840: 000d883a mov r6,zero + 1009844: 01c00084 movi r7,2 + 1009848: 2023883a mov r17,r4 + 100984c: 10000226 beq r2,zero,1009858 <__swrite+0x44> + 1009850: 2940038f ldh r5,14(r5) + 1009854: 1009d500 call 1009d50 <_lseek_r> + 1009858: 8080030b ldhu r2,12(r16) + 100985c: 8140038f ldh r5,14(r16) + 1009860: 8809883a mov r4,r17 + 1009864: 10bbffcc andi r2,r2,61439 + 1009868: 980d883a mov r6,r19 + 100986c: 900f883a mov r7,r18 + 1009870: 8080030d sth r2,12(r16) + 1009874: dfc00417 ldw ra,16(sp) + 1009878: dcc00317 ldw r19,12(sp) + 100987c: dc800217 ldw r18,8(sp) + 1009880: dc400117 ldw r17,4(sp) + 1009884: dc000017 ldw r16,0(sp) + 1009888: dec00504 addi sp,sp,20 + 100988c: 10099ac1 jmpi 10099ac <_write_r> + +01009890 <__sread>: + 1009890: defffe04 addi sp,sp,-8 + 1009894: dc000015 stw r16,0(sp) + 1009898: 2821883a mov r16,r5 + 100989c: 2940038f ldh r5,14(r5) + 10098a0: dfc00115 stw ra,4(sp) + 10098a4: 1009dc80 call 1009dc8 <_read_r> + 10098a8: 1007883a mov r3,r2 + 10098ac: 10000816 blt r2,zero,10098d0 <__sread+0x40> + 10098b0: 80801417 ldw r2,80(r16) + 10098b4: 10c5883a add r2,r2,r3 + 10098b8: 80801415 stw r2,80(r16) + 10098bc: 1805883a mov r2,r3 + 10098c0: dfc00117 ldw ra,4(sp) + 10098c4: dc000017 ldw r16,0(sp) + 10098c8: dec00204 addi sp,sp,8 + 10098cc: f800283a ret + 10098d0: 8080030b ldhu r2,12(r16) + 10098d4: 10bbffcc andi r2,r2,61439 + 10098d8: 8080030d sth r2,12(r16) + 10098dc: 1805883a mov r2,r3 + 10098e0: dfc00117 ldw ra,4(sp) + 10098e4: dc000017 ldw r16,0(sp) + 10098e8: dec00204 addi sp,sp,8 + 10098ec: f800283a ret + +010098f0 : + 10098f0: 2144b03a or r2,r4,r5 + 10098f4: 108000cc andi r2,r2,3 + 10098f8: 10001d1e bne r2,zero,1009970 + 10098fc: 200f883a mov r7,r4 + 1009900: 28800017 ldw r2,0(r5) + 1009904: 21000017 ldw r4,0(r4) + 1009908: 280d883a mov r6,r5 + 100990c: 2080161e bne r4,r2,1009968 + 1009910: 023fbff4 movhi r8,65279 + 1009914: 423fbfc4 addi r8,r8,-257 + 1009918: 2207883a add r3,r4,r8 + 100991c: 01602074 movhi r5,32897 + 1009920: 29602004 addi r5,r5,-32640 + 1009924: 1946703a and r3,r3,r5 + 1009928: 0104303a nor r2,zero,r4 + 100992c: 10c4703a and r2,r2,r3 + 1009930: 10001c1e bne r2,zero,10099a4 + 1009934: 4013883a mov r9,r8 + 1009938: 2811883a mov r8,r5 + 100993c: 00000106 br 1009944 + 1009940: 1800181e bne r3,zero,10099a4 + 1009944: 39c00104 addi r7,r7,4 + 1009948: 39000017 ldw r4,0(r7) + 100994c: 31800104 addi r6,r6,4 + 1009950: 31400017 ldw r5,0(r6) + 1009954: 2245883a add r2,r4,r9 + 1009958: 1204703a and r2,r2,r8 + 100995c: 0106303a nor r3,zero,r4 + 1009960: 1886703a and r3,r3,r2 + 1009964: 217ff626 beq r4,r5,1009940 + 1009968: 3809883a mov r4,r7 + 100996c: 300b883a mov r5,r6 + 1009970: 20c00007 ldb r3,0(r4) + 1009974: 1800051e bne r3,zero,100998c + 1009978: 00000606 br 1009994 + 100997c: 21000044 addi r4,r4,1 + 1009980: 20c00007 ldb r3,0(r4) + 1009984: 29400044 addi r5,r5,1 + 1009988: 18000226 beq r3,zero,1009994 + 100998c: 28800007 ldb r2,0(r5) + 1009990: 18bffa26 beq r3,r2,100997c + 1009994: 20c00003 ldbu r3,0(r4) + 1009998: 28800003 ldbu r2,0(r5) + 100999c: 1885c83a sub r2,r3,r2 + 10099a0: f800283a ret + 10099a4: 0005883a mov r2,zero + 10099a8: f800283a ret + +010099ac <_write_r>: + 10099ac: defffd04 addi sp,sp,-12 + 10099b0: dc000015 stw r16,0(sp) + 10099b4: 040040b4 movhi r16,258 + 10099b8: 84330404 addi r16,r16,-13296 + 10099bc: dc400115 stw r17,4(sp) + 10099c0: 80000015 stw zero,0(r16) + 10099c4: 2023883a mov r17,r4 + 10099c8: 2809883a mov r4,r5 + 10099cc: 300b883a mov r5,r6 + 10099d0: 380d883a mov r6,r7 + 10099d4: dfc00215 stw ra,8(sp) + 10099d8: 100ce180 call 100ce18 + 10099dc: 1007883a mov r3,r2 + 10099e0: 00bfffc4 movi r2,-1 + 10099e4: 18800626 beq r3,r2,1009a00 <_write_r+0x54> + 10099e8: 1805883a mov r2,r3 + 10099ec: dfc00217 ldw ra,8(sp) + 10099f0: dc400117 ldw r17,4(sp) + 10099f4: dc000017 ldw r16,0(sp) + 10099f8: dec00304 addi sp,sp,12 + 10099fc: f800283a ret + 1009a00: 80800017 ldw r2,0(r16) + 1009a04: 103ff826 beq r2,zero,10099e8 <_write_r+0x3c> + 1009a08: 88800015 stw r2,0(r17) + 1009a0c: 1805883a mov r2,r3 + 1009a10: dfc00217 ldw ra,8(sp) + 1009a14: dc400117 ldw r17,4(sp) + 1009a18: dc000017 ldw r16,0(sp) + 1009a1c: dec00304 addi sp,sp,12 + 1009a20: f800283a ret + +01009a24 <_calloc_r>: + 1009a24: 298b383a mul r5,r5,r6 + 1009a28: defffe04 addi sp,sp,-8 + 1009a2c: dc000015 stw r16,0(sp) + 1009a30: dfc00115 stw ra,4(sp) + 1009a34: 10027dc0 call 10027dc <_malloc_r> + 1009a38: 1021883a mov r16,r2 + 1009a3c: 01c00904 movi r7,36 + 1009a40: 10000d26 beq r2,zero,1009a78 <_calloc_r+0x54> + 1009a44: 10ffff17 ldw r3,-4(r2) + 1009a48: 1009883a mov r4,r2 + 1009a4c: 00bfff04 movi r2,-4 + 1009a50: 1886703a and r3,r3,r2 + 1009a54: 1887883a add r3,r3,r2 + 1009a58: 180d883a mov r6,r3 + 1009a5c: 000b883a mov r5,zero + 1009a60: 38c01736 bltu r7,r3,1009ac0 <_calloc_r+0x9c> + 1009a64: 008004c4 movi r2,19 + 1009a68: 10c00836 bltu r2,r3,1009a8c <_calloc_r+0x68> + 1009a6c: 20000215 stw zero,8(r4) + 1009a70: 20000015 stw zero,0(r4) + 1009a74: 20000115 stw zero,4(r4) + 1009a78: 8005883a mov r2,r16 + 1009a7c: dfc00117 ldw ra,4(sp) + 1009a80: dc000017 ldw r16,0(sp) + 1009a84: dec00204 addi sp,sp,8 + 1009a88: f800283a ret + 1009a8c: 008006c4 movi r2,27 + 1009a90: 80000015 stw zero,0(r16) + 1009a94: 80000115 stw zero,4(r16) + 1009a98: 81000204 addi r4,r16,8 + 1009a9c: 10fff32e bgeu r2,r3,1009a6c <_calloc_r+0x48> + 1009aa0: 80000215 stw zero,8(r16) + 1009aa4: 80000315 stw zero,12(r16) + 1009aa8: 81000404 addi r4,r16,16 + 1009aac: 19ffef1e bne r3,r7,1009a6c <_calloc_r+0x48> + 1009ab0: 81000604 addi r4,r16,24 + 1009ab4: 80000415 stw zero,16(r16) + 1009ab8: 80000515 stw zero,20(r16) + 1009abc: 003feb06 br 1009a6c <_calloc_r+0x48> + 1009ac0: 1002f1c0 call 1002f1c + 1009ac4: 8005883a mov r2,r16 + 1009ac8: dfc00117 ldw ra,4(sp) + 1009acc: dc000017 ldw r16,0(sp) + 1009ad0: dec00204 addi sp,sp,8 + 1009ad4: f800283a ret + +01009ad8 <_close_r>: + 1009ad8: defffd04 addi sp,sp,-12 + 1009adc: dc000015 stw r16,0(sp) + 1009ae0: 040040b4 movhi r16,258 + 1009ae4: 84330404 addi r16,r16,-13296 + 1009ae8: dc400115 stw r17,4(sp) + 1009aec: 80000015 stw zero,0(r16) + 1009af0: 2023883a mov r17,r4 + 1009af4: 2809883a mov r4,r5 + 1009af8: dfc00215 stw ra,8(sp) + 1009afc: 100c2700 call 100c270 + 1009b00: 1007883a mov r3,r2 + 1009b04: 00bfffc4 movi r2,-1 + 1009b08: 18800626 beq r3,r2,1009b24 <_close_r+0x4c> + 1009b0c: 1805883a mov r2,r3 + 1009b10: dfc00217 ldw ra,8(sp) + 1009b14: dc400117 ldw r17,4(sp) + 1009b18: dc000017 ldw r16,0(sp) + 1009b1c: dec00304 addi sp,sp,12 + 1009b20: f800283a ret + 1009b24: 80800017 ldw r2,0(r16) + 1009b28: 103ff826 beq r2,zero,1009b0c <_close_r+0x34> + 1009b2c: 88800015 stw r2,0(r17) + 1009b30: 1805883a mov r2,r3 + 1009b34: dfc00217 ldw ra,8(sp) + 1009b38: dc400117 ldw r17,4(sp) + 1009b3c: dc000017 ldw r16,0(sp) + 1009b40: dec00304 addi sp,sp,12 + 1009b44: f800283a ret + +01009b48 <_fclose_r>: + 1009b48: defffc04 addi sp,sp,-16 + 1009b4c: dc400115 stw r17,4(sp) + 1009b50: dc000015 stw r16,0(sp) + 1009b54: dfc00315 stw ra,12(sp) + 1009b58: dc800215 stw r18,8(sp) + 1009b5c: 2821883a mov r16,r5 + 1009b60: 2023883a mov r17,r4 + 1009b64: 28002926 beq r5,zero,1009c0c <_fclose_r+0xc4> + 1009b68: 1006fcc0 call 1006fcc <__sfp_lock_acquire> + 1009b6c: 88000226 beq r17,zero,1009b78 <_fclose_r+0x30> + 1009b70: 88800e17 ldw r2,56(r17) + 1009b74: 10002d26 beq r2,zero,1009c2c <_fclose_r+0xe4> + 1009b78: 8080030f ldh r2,12(r16) + 1009b7c: 10002226 beq r2,zero,1009c08 <_fclose_r+0xc0> + 1009b80: 8809883a mov r4,r17 + 1009b84: 800b883a mov r5,r16 + 1009b88: 1006d440 call 1006d44 <_fflush_r> + 1009b8c: 1025883a mov r18,r2 + 1009b90: 80800b17 ldw r2,44(r16) + 1009b94: 10000426 beq r2,zero,1009ba8 <_fclose_r+0x60> + 1009b98: 81400717 ldw r5,28(r16) + 1009b9c: 8809883a mov r4,r17 + 1009ba0: 103ee83a callr r2 + 1009ba4: 10002a16 blt r2,zero,1009c50 <_fclose_r+0x108> + 1009ba8: 8080030b ldhu r2,12(r16) + 1009bac: 1080200c andi r2,r2,128 + 1009bb0: 1000231e bne r2,zero,1009c40 <_fclose_r+0xf8> + 1009bb4: 81400c17 ldw r5,48(r16) + 1009bb8: 28000526 beq r5,zero,1009bd0 <_fclose_r+0x88> + 1009bbc: 80801004 addi r2,r16,64 + 1009bc0: 28800226 beq r5,r2,1009bcc <_fclose_r+0x84> + 1009bc4: 8809883a mov r4,r17 + 1009bc8: 10073600 call 1007360 <_free_r> + 1009bcc: 80000c15 stw zero,48(r16) + 1009bd0: 81401117 ldw r5,68(r16) + 1009bd4: 28000326 beq r5,zero,1009be4 <_fclose_r+0x9c> + 1009bd8: 8809883a mov r4,r17 + 1009bdc: 10073600 call 1007360 <_free_r> + 1009be0: 80001115 stw zero,68(r16) + 1009be4: 8000030d sth zero,12(r16) + 1009be8: 1006fd00 call 1006fd0 <__sfp_lock_release> + 1009bec: 9005883a mov r2,r18 + 1009bf0: dfc00317 ldw ra,12(sp) + 1009bf4: dc800217 ldw r18,8(sp) + 1009bf8: dc400117 ldw r17,4(sp) + 1009bfc: dc000017 ldw r16,0(sp) + 1009c00: dec00404 addi sp,sp,16 + 1009c04: f800283a ret + 1009c08: 1006fd00 call 1006fd0 <__sfp_lock_release> + 1009c0c: 0025883a mov r18,zero + 1009c10: 9005883a mov r2,r18 + 1009c14: dfc00317 ldw ra,12(sp) + 1009c18: dc800217 ldw r18,8(sp) + 1009c1c: dc400117 ldw r17,4(sp) + 1009c20: dc000017 ldw r16,0(sp) + 1009c24: dec00404 addi sp,sp,16 + 1009c28: f800283a ret + 1009c2c: 8809883a mov r4,r17 + 1009c30: 1006fdc0 call 1006fdc <__sinit> + 1009c34: 8080030f ldh r2,12(r16) + 1009c38: 103fd11e bne r2,zero,1009b80 <_fclose_r+0x38> + 1009c3c: 003ff206 br 1009c08 <_fclose_r+0xc0> + 1009c40: 81400417 ldw r5,16(r16) + 1009c44: 8809883a mov r4,r17 + 1009c48: 10073600 call 1007360 <_free_r> + 1009c4c: 003fd906 br 1009bb4 <_fclose_r+0x6c> + 1009c50: 04bfffc4 movi r18,-1 + 1009c54: 003fd406 br 1009ba8 <_fclose_r+0x60> + +01009c58 : + 1009c58: 008040b4 movhi r2,258 + 1009c5c: 10ab9804 addi r2,r2,-20896 + 1009c60: 200b883a mov r5,r4 + 1009c64: 11000017 ldw r4,0(r2) + 1009c68: 1009b481 jmpi 1009b48 <_fclose_r> + +01009c6c <_fstat_r>: + 1009c6c: defffd04 addi sp,sp,-12 + 1009c70: dc000015 stw r16,0(sp) + 1009c74: 040040b4 movhi r16,258 + 1009c78: 84330404 addi r16,r16,-13296 + 1009c7c: dc400115 stw r17,4(sp) + 1009c80: 80000015 stw zero,0(r16) + 1009c84: 2023883a mov r17,r4 + 1009c88: 2809883a mov r4,r5 + 1009c8c: 300b883a mov r5,r6 + 1009c90: dfc00215 stw ra,8(sp) + 1009c94: 100c4640 call 100c464 + 1009c98: 1007883a mov r3,r2 + 1009c9c: 00bfffc4 movi r2,-1 + 1009ca0: 18800626 beq r3,r2,1009cbc <_fstat_r+0x50> + 1009ca4: 1805883a mov r2,r3 + 1009ca8: dfc00217 ldw ra,8(sp) + 1009cac: dc400117 ldw r17,4(sp) + 1009cb0: dc000017 ldw r16,0(sp) + 1009cb4: dec00304 addi sp,sp,12 + 1009cb8: f800283a ret + 1009cbc: 80800017 ldw r2,0(r16) + 1009cc0: 103ff826 beq r2,zero,1009ca4 <_fstat_r+0x38> + 1009cc4: 88800015 stw r2,0(r17) + 1009cc8: 1805883a mov r2,r3 + 1009ccc: dfc00217 ldw ra,8(sp) + 1009cd0: dc400117 ldw r17,4(sp) + 1009cd4: dc000017 ldw r16,0(sp) + 1009cd8: dec00304 addi sp,sp,12 + 1009cdc: f800283a ret + +01009ce0 <_isatty_r>: + 1009ce0: defffd04 addi sp,sp,-12 + 1009ce4: dc000015 stw r16,0(sp) + 1009ce8: 040040b4 movhi r16,258 + 1009cec: 84330404 addi r16,r16,-13296 + 1009cf0: dc400115 stw r17,4(sp) + 1009cf4: 80000015 stw zero,0(r16) + 1009cf8: 2023883a mov r17,r4 + 1009cfc: 2809883a mov r4,r5 + 1009d00: dfc00215 stw ra,8(sp) + 1009d04: 100c5b80 call 100c5b8 + 1009d08: 1007883a mov r3,r2 + 1009d0c: 00bfffc4 movi r2,-1 + 1009d10: 18800626 beq r3,r2,1009d2c <_isatty_r+0x4c> + 1009d14: 1805883a mov r2,r3 + 1009d18: dfc00217 ldw ra,8(sp) + 1009d1c: dc400117 ldw r17,4(sp) + 1009d20: dc000017 ldw r16,0(sp) + 1009d24: dec00304 addi sp,sp,12 + 1009d28: f800283a ret + 1009d2c: 80800017 ldw r2,0(r16) + 1009d30: 103ff826 beq r2,zero,1009d14 <_isatty_r+0x34> + 1009d34: 88800015 stw r2,0(r17) + 1009d38: 1805883a mov r2,r3 + 1009d3c: dfc00217 ldw ra,8(sp) + 1009d40: dc400117 ldw r17,4(sp) + 1009d44: dc000017 ldw r16,0(sp) + 1009d48: dec00304 addi sp,sp,12 + 1009d4c: f800283a ret + +01009d50 <_lseek_r>: + 1009d50: defffd04 addi sp,sp,-12 + 1009d54: dc000015 stw r16,0(sp) + 1009d58: 040040b4 movhi r16,258 + 1009d5c: 84330404 addi r16,r16,-13296 + 1009d60: dc400115 stw r17,4(sp) + 1009d64: 80000015 stw zero,0(r16) + 1009d68: 2023883a mov r17,r4 + 1009d6c: 2809883a mov r4,r5 + 1009d70: 300b883a mov r5,r6 + 1009d74: 380d883a mov r6,r7 + 1009d78: dfc00215 stw ra,8(sp) + 1009d7c: 100c9640 call 100c964 + 1009d80: 1007883a mov r3,r2 + 1009d84: 00bfffc4 movi r2,-1 + 1009d88: 18800626 beq r3,r2,1009da4 <_lseek_r+0x54> + 1009d8c: 1805883a mov r2,r3 + 1009d90: dfc00217 ldw ra,8(sp) + 1009d94: dc400117 ldw r17,4(sp) + 1009d98: dc000017 ldw r16,0(sp) + 1009d9c: dec00304 addi sp,sp,12 + 1009da0: f800283a ret + 1009da4: 80800017 ldw r2,0(r16) + 1009da8: 103ff826 beq r2,zero,1009d8c <_lseek_r+0x3c> + 1009dac: 88800015 stw r2,0(r17) + 1009db0: 1805883a mov r2,r3 + 1009db4: dfc00217 ldw ra,8(sp) + 1009db8: dc400117 ldw r17,4(sp) + 1009dbc: dc000017 ldw r16,0(sp) + 1009dc0: dec00304 addi sp,sp,12 + 1009dc4: f800283a ret + +01009dc8 <_read_r>: + 1009dc8: defffd04 addi sp,sp,-12 + 1009dcc: dc000015 stw r16,0(sp) + 1009dd0: 040040b4 movhi r16,258 + 1009dd4: 84330404 addi r16,r16,-13296 + 1009dd8: dc400115 stw r17,4(sp) + 1009ddc: 80000015 stw zero,0(r16) + 1009de0: 2023883a mov r17,r4 + 1009de4: 2809883a mov r4,r5 + 1009de8: 300b883a mov r5,r6 + 1009dec: 380d883a mov r6,r7 + 1009df0: dfc00215 stw ra,8(sp) + 1009df4: 100cb7c0 call 100cb7c + 1009df8: 1007883a mov r3,r2 + 1009dfc: 00bfffc4 movi r2,-1 + 1009e00: 18800626 beq r3,r2,1009e1c <_read_r+0x54> + 1009e04: 1805883a mov r2,r3 + 1009e08: dfc00217 ldw ra,8(sp) + 1009e0c: dc400117 ldw r17,4(sp) + 1009e10: dc000017 ldw r16,0(sp) + 1009e14: dec00304 addi sp,sp,12 + 1009e18: f800283a ret + 1009e1c: 80800017 ldw r2,0(r16) + 1009e20: 103ff826 beq r2,zero,1009e04 <_read_r+0x3c> + 1009e24: 88800015 stw r2,0(r17) + 1009e28: 1805883a mov r2,r3 + 1009e2c: dfc00217 ldw ra,8(sp) + 1009e30: dc400117 ldw r17,4(sp) + 1009e34: dc000017 ldw r16,0(sp) + 1009e38: dec00304 addi sp,sp,12 + 1009e3c: f800283a ret + +01009e40 <__udivdi3>: + 1009e40: defff004 addi sp,sp,-64 + 1009e44: 2005883a mov r2,r4 + 1009e48: 3011883a mov r8,r6 + 1009e4c: df000e15 stw fp,56(sp) + 1009e50: dd000a15 stw r20,40(sp) + 1009e54: dc000615 stw r16,24(sp) + 1009e58: dfc00f15 stw ra,60(sp) + 1009e5c: ddc00d15 stw r23,52(sp) + 1009e60: dd800c15 stw r22,48(sp) + 1009e64: dd400b15 stw r21,44(sp) + 1009e68: dcc00915 stw r19,36(sp) + 1009e6c: dc800815 stw r18,32(sp) + 1009e70: dc400715 stw r17,28(sp) + 1009e74: 4021883a mov r16,r8 + 1009e78: 1039883a mov fp,r2 + 1009e7c: 2829883a mov r20,r5 + 1009e80: 38003b1e bne r7,zero,1009f70 <__udivdi3+0x130> + 1009e84: 2a005c36 bltu r5,r8,1009ff8 <__udivdi3+0x1b8> + 1009e88: 4000a626 beq r8,zero,100a124 <__udivdi3+0x2e4> + 1009e8c: 00bfffd4 movui r2,65535 + 1009e90: 14009e36 bltu r2,r16,100a10c <__udivdi3+0x2cc> + 1009e94: 00803fc4 movi r2,255 + 1009e98: 14013d36 bltu r2,r16,100a390 <__udivdi3+0x550> + 1009e9c: 000b883a mov r5,zero + 1009ea0: 0005883a mov r2,zero + 1009ea4: 8084d83a srl r2,r16,r2 + 1009ea8: 010040b4 movhi r4,258 + 1009eac: 2123ee04 addi r4,r4,-28744 + 1009eb0: 01800804 movi r6,32 + 1009eb4: 1105883a add r2,r2,r4 + 1009eb8: 10c00003 ldbu r3,0(r2) + 1009ebc: 28c7883a add r3,r5,r3 + 1009ec0: 30edc83a sub r22,r6,r3 + 1009ec4: b000ee1e bne r22,zero,100a280 <__udivdi3+0x440> + 1009ec8: 802ad43a srli r21,r16,16 + 1009ecc: 00800044 movi r2,1 + 1009ed0: a423c83a sub r17,r20,r16 + 1009ed4: 85ffffcc andi r23,r16,65535 + 1009ed8: d8800315 stw r2,12(sp) + 1009edc: 8809883a mov r4,r17 + 1009ee0: a80b883a mov r5,r21 + 1009ee4: 100bc340 call 100bc34 <__udivsi3> + 1009ee8: 8809883a mov r4,r17 + 1009eec: a80b883a mov r5,r21 + 1009ef0: 102d883a mov r22,r2 + 1009ef4: 100bc3c0 call 100bc3c <__umodsi3> + 1009ef8: 1004943a slli r2,r2,16 + 1009efc: e006d43a srli r3,fp,16 + 1009f00: bda3383a mul r17,r23,r22 + 1009f04: 10c4b03a or r2,r2,r3 + 1009f08: 1440042e bgeu r2,r17,1009f1c <__udivdi3+0xdc> + 1009f0c: 1405883a add r2,r2,r16 + 1009f10: b5bfffc4 addi r22,r22,-1 + 1009f14: 14000136 bltu r2,r16,1009f1c <__udivdi3+0xdc> + 1009f18: 14413d36 bltu r2,r17,100a410 <__udivdi3+0x5d0> + 1009f1c: 1463c83a sub r17,r2,r17 + 1009f20: 8809883a mov r4,r17 + 1009f24: a80b883a mov r5,r21 + 1009f28: 100bc340 call 100bc34 <__udivsi3> + 1009f2c: 8809883a mov r4,r17 + 1009f30: a80b883a mov r5,r21 + 1009f34: 1029883a mov r20,r2 + 1009f38: 100bc3c0 call 100bc3c <__umodsi3> + 1009f3c: 1004943a slli r2,r2,16 + 1009f40: bd09383a mul r4,r23,r20 + 1009f44: e0ffffcc andi r3,fp,65535 + 1009f48: 10c4b03a or r2,r2,r3 + 1009f4c: 1100042e bgeu r2,r4,1009f60 <__udivdi3+0x120> + 1009f50: 8085883a add r2,r16,r2 + 1009f54: a53fffc4 addi r20,r20,-1 + 1009f58: 14000136 bltu r2,r16,1009f60 <__udivdi3+0x120> + 1009f5c: 11012036 bltu r2,r4,100a3e0 <__udivdi3+0x5a0> + 1009f60: b004943a slli r2,r22,16 + 1009f64: d9000317 ldw r4,12(sp) + 1009f68: a084b03a or r2,r20,r2 + 1009f6c: 00001506 br 1009fc4 <__udivdi3+0x184> + 1009f70: 380d883a mov r6,r7 + 1009f74: 29c06236 bltu r5,r7,100a100 <__udivdi3+0x2c0> + 1009f78: 00bfffd4 movui r2,65535 + 1009f7c: 11c05a36 bltu r2,r7,100a0e8 <__udivdi3+0x2a8> + 1009f80: 00803fc4 movi r2,255 + 1009f84: 11c0fc36 bltu r2,r7,100a378 <__udivdi3+0x538> + 1009f88: 000b883a mov r5,zero + 1009f8c: 0005883a mov r2,zero + 1009f90: 3084d83a srl r2,r6,r2 + 1009f94: 010040b4 movhi r4,258 + 1009f98: 2123ee04 addi r4,r4,-28744 + 1009f9c: 01c00804 movi r7,32 + 1009fa0: 1105883a add r2,r2,r4 + 1009fa4: 10c00003 ldbu r3,0(r2) + 1009fa8: 28c7883a add r3,r5,r3 + 1009fac: 38efc83a sub r23,r7,r3 + 1009fb0: b800691e bne r23,zero,100a158 <__udivdi3+0x318> + 1009fb4: 35000136 bltu r6,r20,1009fbc <__udivdi3+0x17c> + 1009fb8: e4005136 bltu fp,r16,100a100 <__udivdi3+0x2c0> + 1009fbc: 00800044 movi r2,1 + 1009fc0: 0009883a mov r4,zero + 1009fc4: 2007883a mov r3,r4 + 1009fc8: dfc00f17 ldw ra,60(sp) + 1009fcc: df000e17 ldw fp,56(sp) + 1009fd0: ddc00d17 ldw r23,52(sp) + 1009fd4: dd800c17 ldw r22,48(sp) + 1009fd8: dd400b17 ldw r21,44(sp) + 1009fdc: dd000a17 ldw r20,40(sp) + 1009fe0: dcc00917 ldw r19,36(sp) + 1009fe4: dc800817 ldw r18,32(sp) + 1009fe8: dc400717 ldw r17,28(sp) + 1009fec: dc000617 ldw r16,24(sp) + 1009ff0: dec01004 addi sp,sp,64 + 1009ff4: f800283a ret + 1009ff8: 00bfffd4 movui r2,65535 + 1009ffc: 12005036 bltu r2,r8,100a140 <__udivdi3+0x300> + 100a000: 00803fc4 movi r2,255 + 100a004: 1200e836 bltu r2,r8,100a3a8 <__udivdi3+0x568> + 100a008: 000b883a mov r5,zero + 100a00c: 0005883a mov r2,zero + 100a010: 8084d83a srl r2,r16,r2 + 100a014: 010040b4 movhi r4,258 + 100a018: 2123ee04 addi r4,r4,-28744 + 100a01c: 01800804 movi r6,32 + 100a020: 1105883a add r2,r2,r4 + 100a024: 10c00003 ldbu r3,0(r2) + 100a028: 28c7883a add r3,r5,r3 + 100a02c: 30cbc83a sub r5,r6,r3 + 100a030: 28000626 beq r5,zero,100a04c <__udivdi3+0x20c> + 100a034: 3145c83a sub r2,r6,r5 + 100a038: e084d83a srl r2,fp,r2 + 100a03c: a146983a sll r3,r20,r5 + 100a040: e178983a sll fp,fp,r5 + 100a044: 8160983a sll r16,r16,r5 + 100a048: 18a8b03a or r20,r3,r2 + 100a04c: 802ad43a srli r21,r16,16 + 100a050: a009883a mov r4,r20 + 100a054: 85ffffcc andi r23,r16,65535 + 100a058: a80b883a mov r5,r21 + 100a05c: 100bc340 call 100bc34 <__udivsi3> + 100a060: a009883a mov r4,r20 + 100a064: a80b883a mov r5,r21 + 100a068: 102d883a mov r22,r2 + 100a06c: 100bc3c0 call 100bc3c <__umodsi3> + 100a070: 1004943a slli r2,r2,16 + 100a074: e006d43a srli r3,fp,16 + 100a078: bda3383a mul r17,r23,r22 + 100a07c: 10c4b03a or r2,r2,r3 + 100a080: 1440042e bgeu r2,r17,100a094 <__udivdi3+0x254> + 100a084: 1405883a add r2,r2,r16 + 100a088: b5bfffc4 addi r22,r22,-1 + 100a08c: 14000136 bltu r2,r16,100a094 <__udivdi3+0x254> + 100a090: 1440d536 bltu r2,r17,100a3e8 <__udivdi3+0x5a8> + 100a094: 1463c83a sub r17,r2,r17 + 100a098: 8809883a mov r4,r17 + 100a09c: a80b883a mov r5,r21 + 100a0a0: 100bc340 call 100bc34 <__udivsi3> + 100a0a4: 8809883a mov r4,r17 + 100a0a8: a80b883a mov r5,r21 + 100a0ac: 1029883a mov r20,r2 + 100a0b0: 100bc3c0 call 100bc3c <__umodsi3> + 100a0b4: 1004943a slli r2,r2,16 + 100a0b8: bd09383a mul r4,r23,r20 + 100a0bc: e0ffffcc andi r3,fp,65535 + 100a0c0: 10c4b03a or r2,r2,r3 + 100a0c4: 1100042e bgeu r2,r4,100a0d8 <__udivdi3+0x298> + 100a0c8: 8085883a add r2,r16,r2 + 100a0cc: a53fffc4 addi r20,r20,-1 + 100a0d0: 14000136 bltu r2,r16,100a0d8 <__udivdi3+0x298> + 100a0d4: 1100c736 bltu r2,r4,100a3f4 <__udivdi3+0x5b4> + 100a0d8: b004943a slli r2,r22,16 + 100a0dc: 0009883a mov r4,zero + 100a0e0: a084b03a or r2,r20,r2 + 100a0e4: 003fb706 br 1009fc4 <__udivdi3+0x184> + 100a0e8: 00804034 movhi r2,256 + 100a0ec: 10bfffc4 addi r2,r2,-1 + 100a0f0: 11c0a436 bltu r2,r7,100a384 <__udivdi3+0x544> + 100a0f4: 01400404 movi r5,16 + 100a0f8: 2805883a mov r2,r5 + 100a0fc: 003fa406 br 1009f90 <__udivdi3+0x150> + 100a100: 0005883a mov r2,zero + 100a104: 0009883a mov r4,zero + 100a108: 003fae06 br 1009fc4 <__udivdi3+0x184> + 100a10c: 00804034 movhi r2,256 + 100a110: 10bfffc4 addi r2,r2,-1 + 100a114: 1400a136 bltu r2,r16,100a39c <__udivdi3+0x55c> + 100a118: 01400404 movi r5,16 + 100a11c: 2805883a mov r2,r5 + 100a120: 003f6006 br 1009ea4 <__udivdi3+0x64> + 100a124: 01000044 movi r4,1 + 100a128: 000b883a mov r5,zero + 100a12c: 100bc340 call 100bc34 <__udivsi3> + 100a130: 1021883a mov r16,r2 + 100a134: 00bfffd4 movui r2,65535 + 100a138: 143ff436 bltu r2,r16,100a10c <__udivdi3+0x2cc> + 100a13c: 003f5506 br 1009e94 <__udivdi3+0x54> + 100a140: 00804034 movhi r2,256 + 100a144: 10bfffc4 addi r2,r2,-1 + 100a148: 12009a36 bltu r2,r8,100a3b4 <__udivdi3+0x574> + 100a14c: 01400404 movi r5,16 + 100a150: 2805883a mov r2,r5 + 100a154: 003fae06 br 100a010 <__udivdi3+0x1d0> + 100a158: 3dc5c83a sub r2,r7,r23 + 100a15c: 35c8983a sll r4,r6,r23 + 100a160: 8086d83a srl r3,r16,r2 + 100a164: a0a2d83a srl r17,r20,r2 + 100a168: e084d83a srl r2,fp,r2 + 100a16c: 20eab03a or r21,r4,r3 + 100a170: a82cd43a srli r22,r21,16 + 100a174: a5c6983a sll r3,r20,r23 + 100a178: 8809883a mov r4,r17 + 100a17c: b00b883a mov r5,r22 + 100a180: 1886b03a or r3,r3,r2 + 100a184: d8c00215 stw r3,8(sp) + 100a188: 100bc340 call 100bc34 <__udivsi3> + 100a18c: 8809883a mov r4,r17 + 100a190: b00b883a mov r5,r22 + 100a194: 1029883a mov r20,r2 + 100a198: 100bc3c0 call 100bc3c <__umodsi3> + 100a19c: a8ffffcc andi r3,r21,65535 + 100a1a0: d8c00515 stw r3,20(sp) + 100a1a4: d9000217 ldw r4,8(sp) + 100a1a8: d9400517 ldw r5,20(sp) + 100a1ac: 1004943a slli r2,r2,16 + 100a1b0: 2006d43a srli r3,r4,16 + 100a1b4: 85e0983a sll r16,r16,r23 + 100a1b8: 2d23383a mul r17,r5,r20 + 100a1bc: 10c4b03a or r2,r2,r3 + 100a1c0: dc000015 stw r16,0(sp) + 100a1c4: 1440032e bgeu r2,r17,100a1d4 <__udivdi3+0x394> + 100a1c8: 1545883a add r2,r2,r21 + 100a1cc: a53fffc4 addi r20,r20,-1 + 100a1d0: 15407f2e bgeu r2,r21,100a3d0 <__udivdi3+0x590> + 100a1d4: 1463c83a sub r17,r2,r17 + 100a1d8: 8809883a mov r4,r17 + 100a1dc: b00b883a mov r5,r22 + 100a1e0: 100bc340 call 100bc34 <__udivsi3> + 100a1e4: 8809883a mov r4,r17 + 100a1e8: b00b883a mov r5,r22 + 100a1ec: 1021883a mov r16,r2 + 100a1f0: 100bc3c0 call 100bc3c <__umodsi3> + 100a1f4: d8c00517 ldw r3,20(sp) + 100a1f8: d9000217 ldw r4,8(sp) + 100a1fc: 1004943a slli r2,r2,16 + 100a200: 1c0f383a mul r7,r3,r16 + 100a204: 20ffffcc andi r3,r4,65535 + 100a208: 10e2b03a or r17,r2,r3 + 100a20c: 89c0032e bgeu r17,r7,100a21c <__udivdi3+0x3dc> + 100a210: 8d63883a add r17,r17,r21 + 100a214: 843fffc4 addi r16,r16,-1 + 100a218: 8d40692e bgeu r17,r21,100a3c0 <__udivdi3+0x580> + 100a21c: a008943a slli r4,r20,16 + 100a220: d9400017 ldw r5,0(sp) + 100a224: 89e3c83a sub r17,r17,r7 + 100a228: 8110b03a or r8,r16,r4 + 100a22c: 280cd43a srli r6,r5,16 + 100a230: 28ffffcc andi r3,r5,65535 + 100a234: 40bfffcc andi r2,r8,65535 + 100a238: 400ad43a srli r5,r8,16 + 100a23c: 10d3383a mul r9,r2,r3 + 100a240: 1185383a mul r2,r2,r6 + 100a244: 28c7383a mul r3,r5,r3 + 100a248: 4808d43a srli r4,r9,16 + 100a24c: 298b383a mul r5,r5,r6 + 100a250: 10c5883a add r2,r2,r3 + 100a254: 2089883a add r4,r4,r2 + 100a258: 20c0022e bgeu r4,r3,100a264 <__udivdi3+0x424> + 100a25c: 00800074 movhi r2,1 + 100a260: 288b883a add r5,r5,r2 + 100a264: 2004d43a srli r2,r4,16 + 100a268: 288b883a add r5,r5,r2 + 100a26c: 89403f36 bltu r17,r5,100a36c <__udivdi3+0x52c> + 100a270: 89403926 beq r17,r5,100a358 <__udivdi3+0x518> + 100a274: 4005883a mov r2,r8 + 100a278: 0009883a mov r4,zero + 100a27c: 003f5106 br 1009fc4 <__udivdi3+0x184> + 100a280: 85a0983a sll r16,r16,r22 + 100a284: 3585c83a sub r2,r6,r22 + 100a288: a0a2d83a srl r17,r20,r2 + 100a28c: 802ad43a srli r21,r16,16 + 100a290: e084d83a srl r2,fp,r2 + 100a294: a586983a sll r3,r20,r22 + 100a298: 8809883a mov r4,r17 + 100a29c: a80b883a mov r5,r21 + 100a2a0: 1886b03a or r3,r3,r2 + 100a2a4: d8c00115 stw r3,4(sp) + 100a2a8: 100bc340 call 100bc34 <__udivsi3> + 100a2ac: 8809883a mov r4,r17 + 100a2b0: a80b883a mov r5,r21 + 100a2b4: d8800415 stw r2,16(sp) + 100a2b8: 100bc3c0 call 100bc3c <__umodsi3> + 100a2bc: d9000117 ldw r4,4(sp) + 100a2c0: d9400417 ldw r5,16(sp) + 100a2c4: 1004943a slli r2,r2,16 + 100a2c8: 85ffffcc andi r23,r16,65535 + 100a2cc: 2006d43a srli r3,r4,16 + 100a2d0: b963383a mul r17,r23,r5 + 100a2d4: 10c4b03a or r2,r2,r3 + 100a2d8: 1440042e bgeu r2,r17,100a2ec <__udivdi3+0x4ac> + 100a2dc: 297fffc4 addi r5,r5,-1 + 100a2e0: 1405883a add r2,r2,r16 + 100a2e4: d9400415 stw r5,16(sp) + 100a2e8: 1400442e bgeu r2,r16,100a3fc <__udivdi3+0x5bc> + 100a2ec: 1463c83a sub r17,r2,r17 + 100a2f0: 8809883a mov r4,r17 + 100a2f4: a80b883a mov r5,r21 + 100a2f8: 100bc340 call 100bc34 <__udivsi3> + 100a2fc: 8809883a mov r4,r17 + 100a300: a80b883a mov r5,r21 + 100a304: 1029883a mov r20,r2 + 100a308: 100bc3c0 call 100bc3c <__umodsi3> + 100a30c: d9400117 ldw r5,4(sp) + 100a310: 1004943a slli r2,r2,16 + 100a314: bd09383a mul r4,r23,r20 + 100a318: 28ffffcc andi r3,r5,65535 + 100a31c: 10c6b03a or r3,r2,r3 + 100a320: 1900062e bgeu r3,r4,100a33c <__udivdi3+0x4fc> + 100a324: 1c07883a add r3,r3,r16 + 100a328: a53fffc4 addi r20,r20,-1 + 100a32c: 1c000336 bltu r3,r16,100a33c <__udivdi3+0x4fc> + 100a330: 1900022e bgeu r3,r4,100a33c <__udivdi3+0x4fc> + 100a334: a53fffc4 addi r20,r20,-1 + 100a338: 1c07883a add r3,r3,r16 + 100a33c: d9400417 ldw r5,16(sp) + 100a340: e5b8983a sll fp,fp,r22 + 100a344: 1923c83a sub r17,r3,r4 + 100a348: 2804943a slli r2,r5,16 + 100a34c: a0a8b03a or r20,r20,r2 + 100a350: dd000315 stw r20,12(sp) + 100a354: 003ee106 br 1009edc <__udivdi3+0x9c> + 100a358: 2004943a slli r2,r4,16 + 100a35c: e5c8983a sll r4,fp,r23 + 100a360: 48ffffcc andi r3,r9,65535 + 100a364: 10c5883a add r2,r2,r3 + 100a368: 20bfc22e bgeu r4,r2,100a274 <__udivdi3+0x434> + 100a36c: 40bfffc4 addi r2,r8,-1 + 100a370: 0009883a mov r4,zero + 100a374: 003f1306 br 1009fc4 <__udivdi3+0x184> + 100a378: 01400204 movi r5,8 + 100a37c: 2805883a mov r2,r5 + 100a380: 003f0306 br 1009f90 <__udivdi3+0x150> + 100a384: 01400604 movi r5,24 + 100a388: 2805883a mov r2,r5 + 100a38c: 003f0006 br 1009f90 <__udivdi3+0x150> + 100a390: 01400204 movi r5,8 + 100a394: 2805883a mov r2,r5 + 100a398: 003ec206 br 1009ea4 <__udivdi3+0x64> + 100a39c: 01400604 movi r5,24 + 100a3a0: 2805883a mov r2,r5 + 100a3a4: 003ebf06 br 1009ea4 <__udivdi3+0x64> + 100a3a8: 01400204 movi r5,8 + 100a3ac: 2805883a mov r2,r5 + 100a3b0: 003f1706 br 100a010 <__udivdi3+0x1d0> + 100a3b4: 01400604 movi r5,24 + 100a3b8: 2805883a mov r2,r5 + 100a3bc: 003f1406 br 100a010 <__udivdi3+0x1d0> + 100a3c0: 89ff962e bgeu r17,r7,100a21c <__udivdi3+0x3dc> + 100a3c4: 8d63883a add r17,r17,r21 + 100a3c8: 843fffc4 addi r16,r16,-1 + 100a3cc: 003f9306 br 100a21c <__udivdi3+0x3dc> + 100a3d0: 147f802e bgeu r2,r17,100a1d4 <__udivdi3+0x394> + 100a3d4: a53fffc4 addi r20,r20,-1 + 100a3d8: 1545883a add r2,r2,r21 + 100a3dc: 003f7d06 br 100a1d4 <__udivdi3+0x394> + 100a3e0: a53fffc4 addi r20,r20,-1 + 100a3e4: 003ede06 br 1009f60 <__udivdi3+0x120> + 100a3e8: b5bfffc4 addi r22,r22,-1 + 100a3ec: 1405883a add r2,r2,r16 + 100a3f0: 003f2806 br 100a094 <__udivdi3+0x254> + 100a3f4: a53fffc4 addi r20,r20,-1 + 100a3f8: 003f3706 br 100a0d8 <__udivdi3+0x298> + 100a3fc: 147fbb2e bgeu r2,r17,100a2ec <__udivdi3+0x4ac> + 100a400: 297fffc4 addi r5,r5,-1 + 100a404: 1405883a add r2,r2,r16 + 100a408: d9400415 stw r5,16(sp) + 100a40c: 003fb706 br 100a2ec <__udivdi3+0x4ac> + 100a410: b5bfffc4 addi r22,r22,-1 + 100a414: 1405883a add r2,r2,r16 + 100a418: 003ec006 br 1009f1c <__udivdi3+0xdc> + +0100a41c <__umoddi3>: + 100a41c: defff104 addi sp,sp,-60 + 100a420: dd800b15 stw r22,44(sp) + 100a424: dd000915 stw r20,36(sp) + 100a428: dc000515 stw r16,20(sp) + 100a42c: dfc00e15 stw ra,56(sp) + 100a430: df000d15 stw fp,52(sp) + 100a434: ddc00c15 stw r23,48(sp) + 100a438: dd400a15 stw r21,40(sp) + 100a43c: dcc00815 stw r19,32(sp) + 100a440: dc800715 stw r18,28(sp) + 100a444: dc400615 stw r17,24(sp) + 100a448: 3021883a mov r16,r6 + 100a44c: 202d883a mov r22,r4 + 100a450: 2829883a mov r20,r5 + 100a454: 38002b1e bne r7,zero,100a504 <__umoddi3+0xe8> + 100a458: 29805036 bltu r5,r6,100a59c <__umoddi3+0x180> + 100a45c: 30008a26 beq r6,zero,100a688 <__umoddi3+0x26c> + 100a460: 00bfffd4 movui r2,65535 + 100a464: 14008236 bltu r2,r16,100a670 <__umoddi3+0x254> + 100a468: 00803fc4 movi r2,255 + 100a46c: 14013636 bltu r2,r16,100a948 <__umoddi3+0x52c> + 100a470: 000b883a mov r5,zero + 100a474: 0005883a mov r2,zero + 100a478: 8084d83a srl r2,r16,r2 + 100a47c: 010040b4 movhi r4,258 + 100a480: 2123ee04 addi r4,r4,-28744 + 100a484: 01800804 movi r6,32 + 100a488: 1105883a add r2,r2,r4 + 100a48c: 10c00003 ldbu r3,0(r2) + 100a490: 28c7883a add r3,r5,r3 + 100a494: 30efc83a sub r23,r6,r3 + 100a498: b800941e bne r23,zero,100a6ec <__umoddi3+0x2d0> + 100a49c: 802ad43a srli r21,r16,16 + 100a4a0: a423c83a sub r17,r20,r16 + 100a4a4: 0039883a mov fp,zero + 100a4a8: 853fffcc andi r20,r16,65535 + 100a4ac: 8809883a mov r4,r17 + 100a4b0: a80b883a mov r5,r21 + 100a4b4: 100bc340 call 100bc34 <__udivsi3> + 100a4b8: 8809883a mov r4,r17 + 100a4bc: a80b883a mov r5,r21 + 100a4c0: a0a3383a mul r17,r20,r2 + 100a4c4: 100bc3c0 call 100bc3c <__umodsi3> + 100a4c8: 1004943a slli r2,r2,16 + 100a4cc: b006d43a srli r3,r22,16 + 100a4d0: 10c4b03a or r2,r2,r3 + 100a4d4: 1440032e bgeu r2,r17,100a4e4 <__umoddi3+0xc8> + 100a4d8: 1405883a add r2,r2,r16 + 100a4dc: 14000136 bltu r2,r16,100a4e4 <__umoddi3+0xc8> + 100a4e0: 14413536 bltu r2,r17,100a9b8 <__umoddi3+0x59c> + 100a4e4: 1463c83a sub r17,r2,r17 + 100a4e8: 8809883a mov r4,r17 + 100a4ec: a80b883a mov r5,r21 + 100a4f0: 100bc340 call 100bc34 <__udivsi3> + 100a4f4: 8809883a mov r4,r17 + 100a4f8: a0a3383a mul r17,r20,r2 + 100a4fc: a80b883a mov r5,r21 + 100a500: 00004d06 br 100a638 <__umoddi3+0x21c> + 100a504: 380d883a mov r6,r7 + 100a508: 29c0102e bgeu r5,r7,100a54c <__umoddi3+0x130> + 100a50c: 2011883a mov r8,r4 + 100a510: 2813883a mov r9,r5 + 100a514: 4005883a mov r2,r8 + 100a518: 4807883a mov r3,r9 + 100a51c: dfc00e17 ldw ra,56(sp) + 100a520: df000d17 ldw fp,52(sp) + 100a524: ddc00c17 ldw r23,48(sp) + 100a528: dd800b17 ldw r22,44(sp) + 100a52c: dd400a17 ldw r21,40(sp) + 100a530: dd000917 ldw r20,36(sp) + 100a534: dcc00817 ldw r19,32(sp) + 100a538: dc800717 ldw r18,28(sp) + 100a53c: dc400617 ldw r17,24(sp) + 100a540: dc000517 ldw r16,20(sp) + 100a544: dec00f04 addi sp,sp,60 + 100a548: f800283a ret + 100a54c: 00bfffd4 movui r2,65535 + 100a550: 11c05a36 bltu r2,r7,100a6bc <__umoddi3+0x2a0> + 100a554: 00803fc4 movi r2,255 + 100a558: 11c0fe36 bltu r2,r7,100a954 <__umoddi3+0x538> + 100a55c: 000b883a mov r5,zero + 100a560: 0005883a mov r2,zero + 100a564: 3084d83a srl r2,r6,r2 + 100a568: 010040b4 movhi r4,258 + 100a56c: 2123ee04 addi r4,r4,-28744 + 100a570: 01c00804 movi r7,32 + 100a574: 1105883a add r2,r2,r4 + 100a578: 10c00003 ldbu r3,0(r2) + 100a57c: 28c7883a add r3,r5,r3 + 100a580: 38ebc83a sub r21,r7,r3 + 100a584: a800851e bne r21,zero,100a79c <__umoddi3+0x380> + 100a588: 35005236 bltu r6,r20,100a6d4 <__umoddi3+0x2b8> + 100a58c: b400512e bgeu r22,r16,100a6d4 <__umoddi3+0x2b8> + 100a590: b011883a mov r8,r22 + 100a594: a013883a mov r9,r20 + 100a598: 003fde06 br 100a514 <__umoddi3+0xf8> + 100a59c: 00bfffd4 movui r2,65535 + 100a5a0: 11804036 bltu r2,r6,100a6a4 <__umoddi3+0x288> + 100a5a4: 00803fc4 movi r2,255 + 100a5a8: 1180ed36 bltu r2,r6,100a960 <__umoddi3+0x544> + 100a5ac: 000b883a mov r5,zero + 100a5b0: 0005883a mov r2,zero + 100a5b4: 8084d83a srl r2,r16,r2 + 100a5b8: 010040b4 movhi r4,258 + 100a5bc: 2123ee04 addi r4,r4,-28744 + 100a5c0: 01800804 movi r6,32 + 100a5c4: 1105883a add r2,r2,r4 + 100a5c8: 10c00003 ldbu r3,0(r2) + 100a5cc: 28c7883a add r3,r5,r3 + 100a5d0: 30c7c83a sub r3,r6,r3 + 100a5d4: 1800bf1e bne r3,zero,100a8d4 <__umoddi3+0x4b8> + 100a5d8: 0039883a mov fp,zero + 100a5dc: 802ad43a srli r21,r16,16 + 100a5e0: a009883a mov r4,r20 + 100a5e4: 85ffffcc andi r23,r16,65535 + 100a5e8: a80b883a mov r5,r21 + 100a5ec: 100bc340 call 100bc34 <__udivsi3> + 100a5f0: a009883a mov r4,r20 + 100a5f4: a80b883a mov r5,r21 + 100a5f8: b8a3383a mul r17,r23,r2 + 100a5fc: 100bc3c0 call 100bc3c <__umodsi3> + 100a600: 1004943a slli r2,r2,16 + 100a604: b006d43a srli r3,r22,16 + 100a608: 10c4b03a or r2,r2,r3 + 100a60c: 1440032e bgeu r2,r17,100a61c <__umoddi3+0x200> + 100a610: 1405883a add r2,r2,r16 + 100a614: 14000136 bltu r2,r16,100a61c <__umoddi3+0x200> + 100a618: 1440e536 bltu r2,r17,100a9b0 <__umoddi3+0x594> + 100a61c: 1463c83a sub r17,r2,r17 + 100a620: 8809883a mov r4,r17 + 100a624: a80b883a mov r5,r21 + 100a628: 100bc340 call 100bc34 <__udivsi3> + 100a62c: 8809883a mov r4,r17 + 100a630: b8a3383a mul r17,r23,r2 + 100a634: a80b883a mov r5,r21 + 100a638: 100bc3c0 call 100bc3c <__umodsi3> + 100a63c: 1004943a slli r2,r2,16 + 100a640: b0ffffcc andi r3,r22,65535 + 100a644: 10c4b03a or r2,r2,r3 + 100a648: 1440042e bgeu r2,r17,100a65c <__umoddi3+0x240> + 100a64c: 1405883a add r2,r2,r16 + 100a650: 14000236 bltu r2,r16,100a65c <__umoddi3+0x240> + 100a654: 1440012e bgeu r2,r17,100a65c <__umoddi3+0x240> + 100a658: 1405883a add r2,r2,r16 + 100a65c: 1445c83a sub r2,r2,r17 + 100a660: 1724d83a srl r18,r2,fp + 100a664: 0013883a mov r9,zero + 100a668: 9011883a mov r8,r18 + 100a66c: 003fa906 br 100a514 <__umoddi3+0xf8> + 100a670: 00804034 movhi r2,256 + 100a674: 10bfffc4 addi r2,r2,-1 + 100a678: 1400b036 bltu r2,r16,100a93c <__umoddi3+0x520> + 100a67c: 01400404 movi r5,16 + 100a680: 2805883a mov r2,r5 + 100a684: 003f7c06 br 100a478 <__umoddi3+0x5c> + 100a688: 01000044 movi r4,1 + 100a68c: 000b883a mov r5,zero + 100a690: 100bc340 call 100bc34 <__udivsi3> + 100a694: 1021883a mov r16,r2 + 100a698: 00bfffd4 movui r2,65535 + 100a69c: 143ff436 bltu r2,r16,100a670 <__umoddi3+0x254> + 100a6a0: 003f7106 br 100a468 <__umoddi3+0x4c> + 100a6a4: 00804034 movhi r2,256 + 100a6a8: 10bfffc4 addi r2,r2,-1 + 100a6ac: 1180af36 bltu r2,r6,100a96c <__umoddi3+0x550> + 100a6b0: 01400404 movi r5,16 + 100a6b4: 2805883a mov r2,r5 + 100a6b8: 003fbe06 br 100a5b4 <__umoddi3+0x198> + 100a6bc: 00804034 movhi r2,256 + 100a6c0: 10bfffc4 addi r2,r2,-1 + 100a6c4: 11c0ac36 bltu r2,r7,100a978 <__umoddi3+0x55c> + 100a6c8: 01400404 movi r5,16 + 100a6cc: 2805883a mov r2,r5 + 100a6d0: 003fa406 br 100a564 <__umoddi3+0x148> + 100a6d4: b409c83a sub r4,r22,r16 + 100a6d8: b105803a cmpltu r2,r22,r4 + 100a6dc: a187c83a sub r3,r20,r6 + 100a6e0: 18a9c83a sub r20,r3,r2 + 100a6e4: 202d883a mov r22,r4 + 100a6e8: 003fa906 br 100a590 <__umoddi3+0x174> + 100a6ec: 85e0983a sll r16,r16,r23 + 100a6f0: 35c5c83a sub r2,r6,r23 + 100a6f4: a0a2d83a srl r17,r20,r2 + 100a6f8: 802ad43a srli r21,r16,16 + 100a6fc: b084d83a srl r2,r22,r2 + 100a700: a5c6983a sll r3,r20,r23 + 100a704: 8809883a mov r4,r17 + 100a708: a80b883a mov r5,r21 + 100a70c: 1886b03a or r3,r3,r2 + 100a710: d8c00115 stw r3,4(sp) + 100a714: 853fffcc andi r20,r16,65535 + 100a718: 100bc340 call 100bc34 <__udivsi3> + 100a71c: 8809883a mov r4,r17 + 100a720: a80b883a mov r5,r21 + 100a724: a0a3383a mul r17,r20,r2 + 100a728: 100bc3c0 call 100bc3c <__umodsi3> + 100a72c: d9000117 ldw r4,4(sp) + 100a730: 1004943a slli r2,r2,16 + 100a734: b839883a mov fp,r23 + 100a738: 2006d43a srli r3,r4,16 + 100a73c: 10c4b03a or r2,r2,r3 + 100a740: 1440022e bgeu r2,r17,100a74c <__umoddi3+0x330> + 100a744: 1405883a add r2,r2,r16 + 100a748: 1400962e bgeu r2,r16,100a9a4 <__umoddi3+0x588> + 100a74c: 1463c83a sub r17,r2,r17 + 100a750: 8809883a mov r4,r17 + 100a754: a80b883a mov r5,r21 + 100a758: 100bc340 call 100bc34 <__udivsi3> + 100a75c: 8809883a mov r4,r17 + 100a760: a80b883a mov r5,r21 + 100a764: a0a3383a mul r17,r20,r2 + 100a768: 100bc3c0 call 100bc3c <__umodsi3> + 100a76c: d9400117 ldw r5,4(sp) + 100a770: 1004943a slli r2,r2,16 + 100a774: 28ffffcc andi r3,r5,65535 + 100a778: 10c4b03a or r2,r2,r3 + 100a77c: 1440042e bgeu r2,r17,100a790 <__umoddi3+0x374> + 100a780: 1405883a add r2,r2,r16 + 100a784: 14000236 bltu r2,r16,100a790 <__umoddi3+0x374> + 100a788: 1440012e bgeu r2,r17,100a790 <__umoddi3+0x374> + 100a78c: 1405883a add r2,r2,r16 + 100a790: b5ec983a sll r22,r22,r23 + 100a794: 1463c83a sub r17,r2,r17 + 100a798: 003f4406 br 100a4ac <__umoddi3+0x90> + 100a79c: 3d4fc83a sub r7,r7,r21 + 100a7a0: 3546983a sll r3,r6,r21 + 100a7a4: 81c4d83a srl r2,r16,r7 + 100a7a8: a1e2d83a srl r17,r20,r7 + 100a7ac: a54c983a sll r6,r20,r21 + 100a7b0: 18aeb03a or r23,r3,r2 + 100a7b4: b828d43a srli r20,r23,16 + 100a7b8: b1c4d83a srl r2,r22,r7 + 100a7bc: 8809883a mov r4,r17 + 100a7c0: a00b883a mov r5,r20 + 100a7c4: 308cb03a or r6,r6,r2 + 100a7c8: d9c00315 stw r7,12(sp) + 100a7cc: d9800215 stw r6,8(sp) + 100a7d0: 100bc340 call 100bc34 <__udivsi3> + 100a7d4: 8809883a mov r4,r17 + 100a7d8: a00b883a mov r5,r20 + 100a7dc: 1039883a mov fp,r2 + 100a7e0: 100bc3c0 call 100bc3c <__umodsi3> + 100a7e4: b8ffffcc andi r3,r23,65535 + 100a7e8: d8c00415 stw r3,16(sp) + 100a7ec: d9000217 ldw r4,8(sp) + 100a7f0: d9400417 ldw r5,16(sp) + 100a7f4: 1004943a slli r2,r2,16 + 100a7f8: 2006d43a srli r3,r4,16 + 100a7fc: 8560983a sll r16,r16,r21 + 100a800: 2f23383a mul r17,r5,fp + 100a804: 10c4b03a or r2,r2,r3 + 100a808: dc000015 stw r16,0(sp) + 100a80c: b56c983a sll r22,r22,r21 + 100a810: 1440032e bgeu r2,r17,100a820 <__umoddi3+0x404> + 100a814: 15c5883a add r2,r2,r23 + 100a818: e73fffc4 addi fp,fp,-1 + 100a81c: 15c05d2e bgeu r2,r23,100a994 <__umoddi3+0x578> + 100a820: 1463c83a sub r17,r2,r17 + 100a824: 8809883a mov r4,r17 + 100a828: a00b883a mov r5,r20 + 100a82c: 100bc340 call 100bc34 <__udivsi3> + 100a830: 8809883a mov r4,r17 + 100a834: a00b883a mov r5,r20 + 100a838: 1021883a mov r16,r2 + 100a83c: 100bc3c0 call 100bc3c <__umodsi3> + 100a840: d8c00417 ldw r3,16(sp) + 100a844: d9000217 ldw r4,8(sp) + 100a848: 1004943a slli r2,r2,16 + 100a84c: 1c23383a mul r17,r3,r16 + 100a850: 20ffffcc andi r3,r4,65535 + 100a854: 10ceb03a or r7,r2,r3 + 100a858: 3c40032e bgeu r7,r17,100a868 <__umoddi3+0x44c> + 100a85c: 3dcf883a add r7,r7,r23 + 100a860: 843fffc4 addi r16,r16,-1 + 100a864: 3dc0472e bgeu r7,r23,100a984 <__umoddi3+0x568> + 100a868: e004943a slli r2,fp,16 + 100a86c: d9400017 ldw r5,0(sp) + 100a870: 3c4fc83a sub r7,r7,r17 + 100a874: 8084b03a or r2,r16,r2 + 100a878: 28ffffcc andi r3,r5,65535 + 100a87c: 280cd43a srli r6,r5,16 + 100a880: 100ad43a srli r5,r2,16 + 100a884: 10bfffcc andi r2,r2,65535 + 100a888: 10d1383a mul r8,r2,r3 + 100a88c: 28c7383a mul r3,r5,r3 + 100a890: 1185383a mul r2,r2,r6 + 100a894: 4008d43a srli r4,r8,16 + 100a898: 298b383a mul r5,r5,r6 + 100a89c: 10c5883a add r2,r2,r3 + 100a8a0: 2089883a add r4,r4,r2 + 100a8a4: 20c0022e bgeu r4,r3,100a8b0 <__umoddi3+0x494> + 100a8a8: 00800074 movhi r2,1 + 100a8ac: 288b883a add r5,r5,r2 + 100a8b0: 2004d43a srli r2,r4,16 + 100a8b4: 2008943a slli r4,r4,16 + 100a8b8: 40ffffcc andi r3,r8,65535 + 100a8bc: 288b883a add r5,r5,r2 + 100a8c0: 20c9883a add r4,r4,r3 + 100a8c4: 39400b36 bltu r7,r5,100a8f4 <__umoddi3+0x4d8> + 100a8c8: 39403d26 beq r7,r5,100a9c0 <__umoddi3+0x5a4> + 100a8cc: 394bc83a sub r5,r7,r5 + 100a8d0: 00000f06 br 100a910 <__umoddi3+0x4f4> + 100a8d4: 30c5c83a sub r2,r6,r3 + 100a8d8: 1839883a mov fp,r3 + 100a8dc: b084d83a srl r2,r22,r2 + 100a8e0: a0c6983a sll r3,r20,r3 + 100a8e4: 8720983a sll r16,r16,fp + 100a8e8: b72c983a sll r22,r22,fp + 100a8ec: 18a8b03a or r20,r3,r2 + 100a8f0: 003f3a06 br 100a5dc <__umoddi3+0x1c0> + 100a8f4: d8c00017 ldw r3,0(sp) + 100a8f8: 20c5c83a sub r2,r4,r3 + 100a8fc: 2089803a cmpltu r4,r4,r2 + 100a900: 2dc7c83a sub r3,r5,r23 + 100a904: 1907c83a sub r3,r3,r4 + 100a908: 38cbc83a sub r5,r7,r3 + 100a90c: 1009883a mov r4,r2 + 100a910: b105c83a sub r2,r22,r4 + 100a914: b087803a cmpltu r3,r22,r2 + 100a918: 28c7c83a sub r3,r5,r3 + 100a91c: d9400317 ldw r5,12(sp) + 100a920: 1544d83a srl r2,r2,r21 + 100a924: 1948983a sll r4,r3,r5 + 100a928: 1d46d83a srl r3,r3,r21 + 100a92c: 20a4b03a or r18,r4,r2 + 100a930: 9011883a mov r8,r18 + 100a934: 1813883a mov r9,r3 + 100a938: 003ef606 br 100a514 <__umoddi3+0xf8> + 100a93c: 01400604 movi r5,24 + 100a940: 2805883a mov r2,r5 + 100a944: 003ecc06 br 100a478 <__umoddi3+0x5c> + 100a948: 01400204 movi r5,8 + 100a94c: 2805883a mov r2,r5 + 100a950: 003ec906 br 100a478 <__umoddi3+0x5c> + 100a954: 01400204 movi r5,8 + 100a958: 2805883a mov r2,r5 + 100a95c: 003f0106 br 100a564 <__umoddi3+0x148> + 100a960: 01400204 movi r5,8 + 100a964: 2805883a mov r2,r5 + 100a968: 003f1206 br 100a5b4 <__umoddi3+0x198> + 100a96c: 01400604 movi r5,24 + 100a970: 2805883a mov r2,r5 + 100a974: 003f0f06 br 100a5b4 <__umoddi3+0x198> + 100a978: 01400604 movi r5,24 + 100a97c: 2805883a mov r2,r5 + 100a980: 003ef806 br 100a564 <__umoddi3+0x148> + 100a984: 3c7fb82e bgeu r7,r17,100a868 <__umoddi3+0x44c> + 100a988: 843fffc4 addi r16,r16,-1 + 100a98c: 3dcf883a add r7,r7,r23 + 100a990: 003fb506 br 100a868 <__umoddi3+0x44c> + 100a994: 147fa22e bgeu r2,r17,100a820 <__umoddi3+0x404> + 100a998: e73fffc4 addi fp,fp,-1 + 100a99c: 15c5883a add r2,r2,r23 + 100a9a0: 003f9f06 br 100a820 <__umoddi3+0x404> + 100a9a4: 147f692e bgeu r2,r17,100a74c <__umoddi3+0x330> + 100a9a8: 1405883a add r2,r2,r16 + 100a9ac: 003f6706 br 100a74c <__umoddi3+0x330> + 100a9b0: 1405883a add r2,r2,r16 + 100a9b4: 003f1906 br 100a61c <__umoddi3+0x200> + 100a9b8: 1405883a add r2,r2,r16 + 100a9bc: 003ec906 br 100a4e4 <__umoddi3+0xc8> + 100a9c0: b13fcc36 bltu r22,r4,100a8f4 <__umoddi3+0x4d8> + 100a9c4: 000b883a mov r5,zero + 100a9c8: 003fd106 br 100a910 <__umoddi3+0x4f4> + +0100a9cc <_fpadd_parts>: + 100a9cc: defff804 addi sp,sp,-32 + 100a9d0: dcc00315 stw r19,12(sp) + 100a9d4: 2027883a mov r19,r4 + 100a9d8: 21000017 ldw r4,0(r4) + 100a9dc: 00c00044 movi r3,1 + 100a9e0: dd400515 stw r21,20(sp) + 100a9e4: dd000415 stw r20,16(sp) + 100a9e8: ddc00715 stw r23,28(sp) + 100a9ec: dd800615 stw r22,24(sp) + 100a9f0: dc800215 stw r18,8(sp) + 100a9f4: dc400115 stw r17,4(sp) + 100a9f8: dc000015 stw r16,0(sp) + 100a9fc: 282b883a mov r21,r5 + 100aa00: 3029883a mov r20,r6 + 100aa04: 1900632e bgeu r3,r4,100ab94 <_fpadd_parts+0x1c8> + 100aa08: 28800017 ldw r2,0(r5) + 100aa0c: 1880812e bgeu r3,r2,100ac14 <_fpadd_parts+0x248> + 100aa10: 00c00104 movi r3,4 + 100aa14: 20c0dc26 beq r4,r3,100ad88 <_fpadd_parts+0x3bc> + 100aa18: 10c07e26 beq r2,r3,100ac14 <_fpadd_parts+0x248> + 100aa1c: 00c00084 movi r3,2 + 100aa20: 10c06726 beq r2,r3,100abc0 <_fpadd_parts+0x1f4> + 100aa24: 20c07b26 beq r4,r3,100ac14 <_fpadd_parts+0x248> + 100aa28: 9dc00217 ldw r23,8(r19) + 100aa2c: 28c00217 ldw r3,8(r5) + 100aa30: 9c400317 ldw r17,12(r19) + 100aa34: 2bc00317 ldw r15,12(r5) + 100aa38: b8cdc83a sub r6,r23,r3 + 100aa3c: 9c800417 ldw r18,16(r19) + 100aa40: 2c000417 ldw r16,16(r5) + 100aa44: 3009883a mov r4,r6 + 100aa48: 30009716 blt r6,zero,100aca8 <_fpadd_parts+0x2dc> + 100aa4c: 00800fc4 movi r2,63 + 100aa50: 11806b16 blt r2,r6,100ac00 <_fpadd_parts+0x234> + 100aa54: 0100a40e bge zero,r4,100ace8 <_fpadd_parts+0x31c> + 100aa58: 35bff804 addi r22,r6,-32 + 100aa5c: b000bc16 blt r22,zero,100ad50 <_fpadd_parts+0x384> + 100aa60: 8596d83a srl r11,r16,r22 + 100aa64: 0019883a mov r12,zero + 100aa68: 0013883a mov r9,zero + 100aa6c: 01000044 movi r4,1 + 100aa70: 0015883a mov r10,zero + 100aa74: b000be16 blt r22,zero,100ad70 <_fpadd_parts+0x3a4> + 100aa78: 2590983a sll r8,r4,r22 + 100aa7c: 000f883a mov r7,zero + 100aa80: 00bfffc4 movi r2,-1 + 100aa84: 3889883a add r4,r7,r2 + 100aa88: 408b883a add r5,r8,r2 + 100aa8c: 21cd803a cmpltu r6,r4,r7 + 100aa90: 314b883a add r5,r6,r5 + 100aa94: 7904703a and r2,r15,r4 + 100aa98: 8146703a and r3,r16,r5 + 100aa9c: 10c4b03a or r2,r2,r3 + 100aaa0: 10000226 beq r2,zero,100aaac <_fpadd_parts+0xe0> + 100aaa4: 02400044 movi r9,1 + 100aaa8: 0015883a mov r10,zero + 100aaac: 5a5eb03a or r15,r11,r9 + 100aab0: 62a0b03a or r16,r12,r10 + 100aab4: 99400117 ldw r5,4(r19) + 100aab8: a8800117 ldw r2,4(r21) + 100aabc: 28806e26 beq r5,r2,100ac78 <_fpadd_parts+0x2ac> + 100aac0: 28006626 beq r5,zero,100ac5c <_fpadd_parts+0x290> + 100aac4: 7c45c83a sub r2,r15,r17 + 100aac8: 7889803a cmpltu r4,r15,r2 + 100aacc: 8487c83a sub r3,r16,r18 + 100aad0: 1909c83a sub r4,r3,r4 + 100aad4: 100d883a mov r6,r2 + 100aad8: 200f883a mov r7,r4 + 100aadc: 38007716 blt r7,zero,100acbc <_fpadd_parts+0x2f0> + 100aae0: a5c00215 stw r23,8(r20) + 100aae4: a1c00415 stw r7,16(r20) + 100aae8: a0000115 stw zero,4(r20) + 100aaec: a1800315 stw r6,12(r20) + 100aaf0: a2000317 ldw r8,12(r20) + 100aaf4: a2400417 ldw r9,16(r20) + 100aaf8: 00bfffc4 movi r2,-1 + 100aafc: 408b883a add r5,r8,r2 + 100ab00: 2a09803a cmpltu r4,r5,r8 + 100ab04: 488d883a add r6,r9,r2 + 100ab08: 01c40034 movhi r7,4096 + 100ab0c: 39ffffc4 addi r7,r7,-1 + 100ab10: 218d883a add r6,r4,r6 + 100ab14: 39801736 bltu r7,r6,100ab74 <_fpadd_parts+0x1a8> + 100ab18: 31c06526 beq r6,r7,100acb0 <_fpadd_parts+0x2e4> + 100ab1c: a3000217 ldw r12,8(r20) + 100ab20: 4209883a add r4,r8,r8 + 100ab24: 00bfffc4 movi r2,-1 + 100ab28: 220f803a cmpltu r7,r4,r8 + 100ab2c: 4a4b883a add r5,r9,r9 + 100ab30: 394f883a add r7,r7,r5 + 100ab34: 2095883a add r10,r4,r2 + 100ab38: 3897883a add r11,r7,r2 + 100ab3c: 510d803a cmpltu r6,r10,r4 + 100ab40: 6099883a add r12,r12,r2 + 100ab44: 32d7883a add r11,r6,r11 + 100ab48: 00840034 movhi r2,4096 + 100ab4c: 10bfffc4 addi r2,r2,-1 + 100ab50: 2011883a mov r8,r4 + 100ab54: 3813883a mov r9,r7 + 100ab58: a1000315 stw r4,12(r20) + 100ab5c: a1c00415 stw r7,16(r20) + 100ab60: a3000215 stw r12,8(r20) + 100ab64: 12c00336 bltu r2,r11,100ab74 <_fpadd_parts+0x1a8> + 100ab68: 58bfed1e bne r11,r2,100ab20 <_fpadd_parts+0x154> + 100ab6c: 00bfff84 movi r2,-2 + 100ab70: 12bfeb2e bgeu r2,r10,100ab20 <_fpadd_parts+0x154> + 100ab74: a2800417 ldw r10,16(r20) + 100ab78: 008000c4 movi r2,3 + 100ab7c: 00c80034 movhi r3,8192 + 100ab80: 18ffffc4 addi r3,r3,-1 + 100ab84: a2400317 ldw r9,12(r20) + 100ab88: a0800015 stw r2,0(r20) + 100ab8c: 1a802336 bltu r3,r10,100ac1c <_fpadd_parts+0x250> + 100ab90: a027883a mov r19,r20 + 100ab94: 9805883a mov r2,r19 + 100ab98: ddc00717 ldw r23,28(sp) + 100ab9c: dd800617 ldw r22,24(sp) + 100aba0: dd400517 ldw r21,20(sp) + 100aba4: dd000417 ldw r20,16(sp) + 100aba8: dcc00317 ldw r19,12(sp) + 100abac: dc800217 ldw r18,8(sp) + 100abb0: dc400117 ldw r17,4(sp) + 100abb4: dc000017 ldw r16,0(sp) + 100abb8: dec00804 addi sp,sp,32 + 100abbc: f800283a ret + 100abc0: 20fff41e bne r4,r3,100ab94 <_fpadd_parts+0x1c8> + 100abc4: 31000015 stw r4,0(r6) + 100abc8: 98800117 ldw r2,4(r19) + 100abcc: 30800115 stw r2,4(r6) + 100abd0: 98c00217 ldw r3,8(r19) + 100abd4: 30c00215 stw r3,8(r6) + 100abd8: 98800317 ldw r2,12(r19) + 100abdc: 30800315 stw r2,12(r6) + 100abe0: 98c00417 ldw r3,16(r19) + 100abe4: 30c00415 stw r3,16(r6) + 100abe8: 98800117 ldw r2,4(r19) + 100abec: 28c00117 ldw r3,4(r5) + 100abf0: 3027883a mov r19,r6 + 100abf4: 10c4703a and r2,r2,r3 + 100abf8: 30800115 stw r2,4(r6) + 100abfc: 003fe506 br 100ab94 <_fpadd_parts+0x1c8> + 100ac00: 1dc02616 blt r3,r23,100ac9c <_fpadd_parts+0x2d0> + 100ac04: 0023883a mov r17,zero + 100ac08: 182f883a mov r23,r3 + 100ac0c: 0025883a mov r18,zero + 100ac10: 003fa806 br 100aab4 <_fpadd_parts+0xe8> + 100ac14: a827883a mov r19,r21 + 100ac18: 003fde06 br 100ab94 <_fpadd_parts+0x1c8> + 100ac1c: 01800044 movi r6,1 + 100ac20: 500497fa slli r2,r10,31 + 100ac24: 4808d07a srli r4,r9,1 + 100ac28: 518ad83a srl r5,r10,r6 + 100ac2c: a2000217 ldw r8,8(r20) + 100ac30: 1108b03a or r4,r2,r4 + 100ac34: 0007883a mov r3,zero + 100ac38: 4984703a and r2,r9,r6 + 100ac3c: 208cb03a or r6,r4,r2 + 100ac40: 28ceb03a or r7,r5,r3 + 100ac44: 42000044 addi r8,r8,1 + 100ac48: a027883a mov r19,r20 + 100ac4c: a1c00415 stw r7,16(r20) + 100ac50: a2000215 stw r8,8(r20) + 100ac54: a1800315 stw r6,12(r20) + 100ac58: 003fce06 br 100ab94 <_fpadd_parts+0x1c8> + 100ac5c: 8bc5c83a sub r2,r17,r15 + 100ac60: 8889803a cmpltu r4,r17,r2 + 100ac64: 9407c83a sub r3,r18,r16 + 100ac68: 1909c83a sub r4,r3,r4 + 100ac6c: 100d883a mov r6,r2 + 100ac70: 200f883a mov r7,r4 + 100ac74: 003f9906 br 100aadc <_fpadd_parts+0x110> + 100ac78: 7c45883a add r2,r15,r17 + 100ac7c: 13c9803a cmpltu r4,r2,r15 + 100ac80: 8487883a add r3,r16,r18 + 100ac84: 20c9883a add r4,r4,r3 + 100ac88: a1400115 stw r5,4(r20) + 100ac8c: a5c00215 stw r23,8(r20) + 100ac90: a0800315 stw r2,12(r20) + 100ac94: a1000415 stw r4,16(r20) + 100ac98: 003fb606 br 100ab74 <_fpadd_parts+0x1a8> + 100ac9c: 001f883a mov r15,zero + 100aca0: 0021883a mov r16,zero + 100aca4: 003f8306 br 100aab4 <_fpadd_parts+0xe8> + 100aca8: 018dc83a sub r6,zero,r6 + 100acac: 003f6706 br 100aa4c <_fpadd_parts+0x80> + 100acb0: 00bfff84 movi r2,-2 + 100acb4: 117faf36 bltu r2,r5,100ab74 <_fpadd_parts+0x1a8> + 100acb8: 003f9806 br 100ab1c <_fpadd_parts+0x150> + 100acbc: 0005883a mov r2,zero + 100acc0: 1189c83a sub r4,r2,r6 + 100acc4: 1105803a cmpltu r2,r2,r4 + 100acc8: 01cbc83a sub r5,zero,r7 + 100accc: 2885c83a sub r2,r5,r2 + 100acd0: 01800044 movi r6,1 + 100acd4: a1800115 stw r6,4(r20) + 100acd8: a5c00215 stw r23,8(r20) + 100acdc: a1000315 stw r4,12(r20) + 100ace0: a0800415 stw r2,16(r20) + 100ace4: 003f8206 br 100aaf0 <_fpadd_parts+0x124> + 100ace8: 203f7226 beq r4,zero,100aab4 <_fpadd_parts+0xe8> + 100acec: 35bff804 addi r22,r6,-32 + 100acf0: b9af883a add r23,r23,r6 + 100acf4: b0003116 blt r22,zero,100adbc <_fpadd_parts+0x3f0> + 100acf8: 959ad83a srl r13,r18,r22 + 100acfc: 001d883a mov r14,zero + 100ad00: 000f883a mov r7,zero + 100ad04: 01000044 movi r4,1 + 100ad08: 0011883a mov r8,zero + 100ad0c: b0002516 blt r22,zero,100ada4 <_fpadd_parts+0x3d8> + 100ad10: 2594983a sll r10,r4,r22 + 100ad14: 0013883a mov r9,zero + 100ad18: 00bfffc4 movi r2,-1 + 100ad1c: 4889883a add r4,r9,r2 + 100ad20: 508b883a add r5,r10,r2 + 100ad24: 224d803a cmpltu r6,r4,r9 + 100ad28: 314b883a add r5,r6,r5 + 100ad2c: 8904703a and r2,r17,r4 + 100ad30: 9146703a and r3,r18,r5 + 100ad34: 10c4b03a or r2,r2,r3 + 100ad38: 10000226 beq r2,zero,100ad44 <_fpadd_parts+0x378> + 100ad3c: 01c00044 movi r7,1 + 100ad40: 0011883a mov r8,zero + 100ad44: 69e2b03a or r17,r13,r7 + 100ad48: 7224b03a or r18,r14,r8 + 100ad4c: 003f5906 br 100aab4 <_fpadd_parts+0xe8> + 100ad50: 8407883a add r3,r16,r16 + 100ad54: 008007c4 movi r2,31 + 100ad58: 1185c83a sub r2,r2,r6 + 100ad5c: 1886983a sll r3,r3,r2 + 100ad60: 7996d83a srl r11,r15,r6 + 100ad64: 8198d83a srl r12,r16,r6 + 100ad68: 1ad6b03a or r11,r3,r11 + 100ad6c: 003f3e06 br 100aa68 <_fpadd_parts+0x9c> + 100ad70: 2006d07a srli r3,r4,1 + 100ad74: 008007c4 movi r2,31 + 100ad78: 1185c83a sub r2,r2,r6 + 100ad7c: 1890d83a srl r8,r3,r2 + 100ad80: 218e983a sll r7,r4,r6 + 100ad84: 003f3e06 br 100aa80 <_fpadd_parts+0xb4> + 100ad88: 113f821e bne r2,r4,100ab94 <_fpadd_parts+0x1c8> + 100ad8c: 28c00117 ldw r3,4(r5) + 100ad90: 98800117 ldw r2,4(r19) + 100ad94: 10ff7f26 beq r2,r3,100ab94 <_fpadd_parts+0x1c8> + 100ad98: 04c040b4 movhi r19,258 + 100ad9c: 9ce3e904 addi r19,r19,-28764 + 100ada0: 003f7c06 br 100ab94 <_fpadd_parts+0x1c8> + 100ada4: 2006d07a srli r3,r4,1 + 100ada8: 008007c4 movi r2,31 + 100adac: 1185c83a sub r2,r2,r6 + 100adb0: 1894d83a srl r10,r3,r2 + 100adb4: 2192983a sll r9,r4,r6 + 100adb8: 003fd706 br 100ad18 <_fpadd_parts+0x34c> + 100adbc: 9487883a add r3,r18,r18 + 100adc0: 008007c4 movi r2,31 + 100adc4: 1185c83a sub r2,r2,r6 + 100adc8: 1886983a sll r3,r3,r2 + 100adcc: 899ad83a srl r13,r17,r6 + 100add0: 919cd83a srl r14,r18,r6 + 100add4: 1b5ab03a or r13,r3,r13 + 100add8: 003fc906 br 100ad00 <_fpadd_parts+0x334> + +0100addc <__subdf3>: + 100addc: deffea04 addi sp,sp,-88 + 100ade0: dcc01415 stw r19,80(sp) + 100ade4: dcc00404 addi r19,sp,16 + 100ade8: 2011883a mov r8,r4 + 100adec: 2813883a mov r9,r5 + 100adf0: dc401315 stw r17,76(sp) + 100adf4: d809883a mov r4,sp + 100adf8: 980b883a mov r5,r19 + 100adfc: dc400904 addi r17,sp,36 + 100ae00: dfc01515 stw ra,84(sp) + 100ae04: da400115 stw r9,4(sp) + 100ae08: d9c00315 stw r7,12(sp) + 100ae0c: da000015 stw r8,0(sp) + 100ae10: d9800215 stw r6,8(sp) + 100ae14: 100c0700 call 100c070 <__unpack_d> + 100ae18: d9000204 addi r4,sp,8 + 100ae1c: 880b883a mov r5,r17 + 100ae20: 100c0700 call 100c070 <__unpack_d> + 100ae24: d8800a17 ldw r2,40(sp) + 100ae28: 880b883a mov r5,r17 + 100ae2c: 9809883a mov r4,r19 + 100ae30: d9800e04 addi r6,sp,56 + 100ae34: 1080005c xori r2,r2,1 + 100ae38: d8800a15 stw r2,40(sp) + 100ae3c: 100a9cc0 call 100a9cc <_fpadd_parts> + 100ae40: 1009883a mov r4,r2 + 100ae44: 100bd5c0 call 100bd5c <__pack_d> + 100ae48: dfc01517 ldw ra,84(sp) + 100ae4c: dcc01417 ldw r19,80(sp) + 100ae50: dc401317 ldw r17,76(sp) + 100ae54: dec01604 addi sp,sp,88 + 100ae58: f800283a ret + +0100ae5c <__adddf3>: + 100ae5c: deffea04 addi sp,sp,-88 + 100ae60: dcc01415 stw r19,80(sp) + 100ae64: dcc00404 addi r19,sp,16 + 100ae68: 2011883a mov r8,r4 + 100ae6c: 2813883a mov r9,r5 + 100ae70: dc401315 stw r17,76(sp) + 100ae74: d809883a mov r4,sp + 100ae78: 980b883a mov r5,r19 + 100ae7c: dc400904 addi r17,sp,36 + 100ae80: dfc01515 stw ra,84(sp) + 100ae84: da400115 stw r9,4(sp) + 100ae88: d9c00315 stw r7,12(sp) + 100ae8c: da000015 stw r8,0(sp) + 100ae90: d9800215 stw r6,8(sp) + 100ae94: 100c0700 call 100c070 <__unpack_d> + 100ae98: d9000204 addi r4,sp,8 + 100ae9c: 880b883a mov r5,r17 + 100aea0: 100c0700 call 100c070 <__unpack_d> + 100aea4: d9800e04 addi r6,sp,56 + 100aea8: 9809883a mov r4,r19 + 100aeac: 880b883a mov r5,r17 + 100aeb0: 100a9cc0 call 100a9cc <_fpadd_parts> + 100aeb4: 1009883a mov r4,r2 + 100aeb8: 100bd5c0 call 100bd5c <__pack_d> + 100aebc: dfc01517 ldw ra,84(sp) + 100aec0: dcc01417 ldw r19,80(sp) + 100aec4: dc401317 ldw r17,76(sp) + 100aec8: dec01604 addi sp,sp,88 + 100aecc: f800283a ret + +0100aed0 <__muldf3>: + 100aed0: deffe004 addi sp,sp,-128 + 100aed4: dc401815 stw r17,96(sp) + 100aed8: dc400404 addi r17,sp,16 + 100aedc: 2011883a mov r8,r4 + 100aee0: 2813883a mov r9,r5 + 100aee4: dc001715 stw r16,92(sp) + 100aee8: d809883a mov r4,sp + 100aeec: 880b883a mov r5,r17 + 100aef0: dc000904 addi r16,sp,36 + 100aef4: dfc01f15 stw ra,124(sp) + 100aef8: da400115 stw r9,4(sp) + 100aefc: d9c00315 stw r7,12(sp) + 100af00: da000015 stw r8,0(sp) + 100af04: d9800215 stw r6,8(sp) + 100af08: ddc01e15 stw r23,120(sp) + 100af0c: dd801d15 stw r22,116(sp) + 100af10: dd401c15 stw r21,112(sp) + 100af14: dd001b15 stw r20,108(sp) + 100af18: dcc01a15 stw r19,104(sp) + 100af1c: dc801915 stw r18,100(sp) + 100af20: 100c0700 call 100c070 <__unpack_d> + 100af24: d9000204 addi r4,sp,8 + 100af28: 800b883a mov r5,r16 + 100af2c: 100c0700 call 100c070 <__unpack_d> + 100af30: d9000417 ldw r4,16(sp) + 100af34: 00800044 movi r2,1 + 100af38: 1100102e bgeu r2,r4,100af7c <__muldf3+0xac> + 100af3c: d8c00917 ldw r3,36(sp) + 100af40: 10c0062e bgeu r2,r3,100af5c <__muldf3+0x8c> + 100af44: 00800104 movi r2,4 + 100af48: 20800a26 beq r4,r2,100af74 <__muldf3+0xa4> + 100af4c: 1880cc26 beq r3,r2,100b280 <__muldf3+0x3b0> + 100af50: 00800084 movi r2,2 + 100af54: 20800926 beq r4,r2,100af7c <__muldf3+0xac> + 100af58: 1880191e bne r3,r2,100afc0 <__muldf3+0xf0> + 100af5c: d8c00a17 ldw r3,40(sp) + 100af60: d8800517 ldw r2,20(sp) + 100af64: 8009883a mov r4,r16 + 100af68: 10c4c03a cmpne r2,r2,r3 + 100af6c: d8800a15 stw r2,40(sp) + 100af70: 00000706 br 100af90 <__muldf3+0xc0> + 100af74: 00800084 movi r2,2 + 100af78: 1880c326 beq r3,r2,100b288 <__muldf3+0x3b8> + 100af7c: d8800517 ldw r2,20(sp) + 100af80: d8c00a17 ldw r3,40(sp) + 100af84: 8809883a mov r4,r17 + 100af88: 10c4c03a cmpne r2,r2,r3 + 100af8c: d8800515 stw r2,20(sp) + 100af90: 100bd5c0 call 100bd5c <__pack_d> + 100af94: dfc01f17 ldw ra,124(sp) + 100af98: ddc01e17 ldw r23,120(sp) + 100af9c: dd801d17 ldw r22,116(sp) + 100afa0: dd401c17 ldw r21,112(sp) + 100afa4: dd001b17 ldw r20,108(sp) + 100afa8: dcc01a17 ldw r19,104(sp) + 100afac: dc801917 ldw r18,100(sp) + 100afb0: dc401817 ldw r17,96(sp) + 100afb4: dc001717 ldw r16,92(sp) + 100afb8: dec02004 addi sp,sp,128 + 100afbc: f800283a ret + 100afc0: dd800717 ldw r22,28(sp) + 100afc4: dc800c17 ldw r18,48(sp) + 100afc8: 002b883a mov r21,zero + 100afcc: 0023883a mov r17,zero + 100afd0: a80b883a mov r5,r21 + 100afd4: b00d883a mov r6,r22 + 100afd8: 880f883a mov r7,r17 + 100afdc: ddc00817 ldw r23,32(sp) + 100afe0: dcc00d17 ldw r19,52(sp) + 100afe4: 9009883a mov r4,r18 + 100afe8: 100bc440 call 100bc44 <__muldi3> + 100afec: 001b883a mov r13,zero + 100aff0: 680f883a mov r7,r13 + 100aff4: b009883a mov r4,r22 + 100aff8: 000b883a mov r5,zero + 100affc: 980d883a mov r6,r19 + 100b000: b82d883a mov r22,r23 + 100b004: 002f883a mov r23,zero + 100b008: db401615 stw r13,88(sp) + 100b00c: d8801315 stw r2,76(sp) + 100b010: d8c01415 stw r3,80(sp) + 100b014: dcc01515 stw r19,84(sp) + 100b018: 100bc440 call 100bc44 <__muldi3> + 100b01c: b00d883a mov r6,r22 + 100b020: 000b883a mov r5,zero + 100b024: 9009883a mov r4,r18 + 100b028: b80f883a mov r7,r23 + 100b02c: 1021883a mov r16,r2 + 100b030: 1823883a mov r17,r3 + 100b034: 100bc440 call 100bc44 <__muldi3> + 100b038: 8085883a add r2,r16,r2 + 100b03c: 140d803a cmpltu r6,r2,r16 + 100b040: 88c7883a add r3,r17,r3 + 100b044: 30cd883a add r6,r6,r3 + 100b048: 1029883a mov r20,r2 + 100b04c: 302b883a mov r21,r6 + 100b050: da801317 ldw r10,76(sp) + 100b054: dac01417 ldw r11,80(sp) + 100b058: db001517 ldw r12,84(sp) + 100b05c: db401617 ldw r13,88(sp) + 100b060: 3440612e bgeu r6,r17,100b1e8 <__muldf3+0x318> + 100b064: 0009883a mov r4,zero + 100b068: 5105883a add r2,r10,r4 + 100b06c: 128d803a cmpltu r6,r2,r10 + 100b070: 5d07883a add r3,r11,r20 + 100b074: 30cd883a add r6,r6,r3 + 100b078: 0021883a mov r16,zero + 100b07c: 04400044 movi r17,1 + 100b080: 1025883a mov r18,r2 + 100b084: 3027883a mov r19,r6 + 100b088: 32c06236 bltu r6,r11,100b214 <__muldf3+0x344> + 100b08c: 59807a26 beq r11,r6,100b278 <__muldf3+0x3a8> + 100b090: 680b883a mov r5,r13 + 100b094: b80f883a mov r7,r23 + 100b098: 6009883a mov r4,r12 + 100b09c: b00d883a mov r6,r22 + 100b0a0: 100bc440 call 100bc44 <__muldi3> + 100b0a4: 1009883a mov r4,r2 + 100b0a8: 000f883a mov r7,zero + 100b0ac: 1545883a add r2,r2,r21 + 100b0b0: 1111803a cmpltu r8,r2,r4 + 100b0b4: 19c7883a add r3,r3,r7 + 100b0b8: 40c7883a add r3,r8,r3 + 100b0bc: 88cb883a add r5,r17,r3 + 100b0c0: d8c00617 ldw r3,24(sp) + 100b0c4: 8089883a add r4,r16,r2 + 100b0c8: d8800b17 ldw r2,44(sp) + 100b0cc: 18c00104 addi r3,r3,4 + 100b0d0: 240d803a cmpltu r6,r4,r16 + 100b0d4: 10c7883a add r3,r2,r3 + 100b0d8: 2013883a mov r9,r4 + 100b0dc: d8800a17 ldw r2,40(sp) + 100b0e0: d9000517 ldw r4,20(sp) + 100b0e4: 314d883a add r6,r6,r5 + 100b0e8: 3015883a mov r10,r6 + 100b0ec: 2088c03a cmpne r4,r4,r2 + 100b0f0: 00880034 movhi r2,8192 + 100b0f4: 10bfffc4 addi r2,r2,-1 + 100b0f8: d9000f15 stw r4,60(sp) + 100b0fc: d8c01015 stw r3,64(sp) + 100b100: 1180162e bgeu r2,r6,100b15c <__muldf3+0x28c> + 100b104: 1811883a mov r8,r3 + 100b108: 101f883a mov r15,r2 + 100b10c: 980497fa slli r2,r19,31 + 100b110: 9016d07a srli r11,r18,1 + 100b114: 500697fa slli r3,r10,31 + 100b118: 480cd07a srli r6,r9,1 + 100b11c: 500ed07a srli r7,r10,1 + 100b120: 12d6b03a or r11,r2,r11 + 100b124: 00800044 movi r2,1 + 100b128: 198cb03a or r6,r3,r6 + 100b12c: 4888703a and r4,r9,r2 + 100b130: 9818d07a srli r12,r19,1 + 100b134: 001b883a mov r13,zero + 100b138: 03a00034 movhi r14,32768 + 100b13c: 3013883a mov r9,r6 + 100b140: 3815883a mov r10,r7 + 100b144: 4091883a add r8,r8,r2 + 100b148: 20000226 beq r4,zero,100b154 <__muldf3+0x284> + 100b14c: 5b64b03a or r18,r11,r13 + 100b150: 63a6b03a or r19,r12,r14 + 100b154: 7abfed36 bltu r15,r10,100b10c <__muldf3+0x23c> + 100b158: da001015 stw r8,64(sp) + 100b15c: 00840034 movhi r2,4096 + 100b160: 10bfffc4 addi r2,r2,-1 + 100b164: 12801436 bltu r2,r10,100b1b8 <__muldf3+0x2e8> + 100b168: da001017 ldw r8,64(sp) + 100b16c: 101f883a mov r15,r2 + 100b170: 4a45883a add r2,r9,r9 + 100b174: 124d803a cmpltu r6,r2,r9 + 100b178: 5287883a add r3,r10,r10 + 100b17c: 9497883a add r11,r18,r18 + 100b180: 5c8f803a cmpltu r7,r11,r18 + 100b184: 9cd9883a add r12,r19,r19 + 100b188: 01000044 movi r4,1 + 100b18c: 30cd883a add r6,r6,r3 + 100b190: 3b0f883a add r7,r7,r12 + 100b194: 423fffc4 addi r8,r8,-1 + 100b198: 1013883a mov r9,r2 + 100b19c: 3015883a mov r10,r6 + 100b1a0: 111ab03a or r13,r2,r4 + 100b1a4: 98003016 blt r19,zero,100b268 <__muldf3+0x398> + 100b1a8: 5825883a mov r18,r11 + 100b1ac: 3827883a mov r19,r7 + 100b1b0: 7abfef2e bgeu r15,r10,100b170 <__muldf3+0x2a0> + 100b1b4: da001015 stw r8,64(sp) + 100b1b8: 00803fc4 movi r2,255 + 100b1bc: 488e703a and r7,r9,r2 + 100b1c0: 00802004 movi r2,128 + 100b1c4: 0007883a mov r3,zero + 100b1c8: 0011883a mov r8,zero + 100b1cc: 38801826 beq r7,r2,100b230 <__muldf3+0x360> + 100b1d0: 008000c4 movi r2,3 + 100b1d4: d9000e04 addi r4,sp,56 + 100b1d8: da801215 stw r10,72(sp) + 100b1dc: d8800e15 stw r2,56(sp) + 100b1e0: da401115 stw r9,68(sp) + 100b1e4: 003f6a06 br 100af90 <__muldf3+0xc0> + 100b1e8: 89802126 beq r17,r6,100b270 <__muldf3+0x3a0> + 100b1ec: 0009883a mov r4,zero + 100b1f0: 5105883a add r2,r10,r4 + 100b1f4: 128d803a cmpltu r6,r2,r10 + 100b1f8: 5d07883a add r3,r11,r20 + 100b1fc: 30cd883a add r6,r6,r3 + 100b200: 0021883a mov r16,zero + 100b204: 0023883a mov r17,zero + 100b208: 1025883a mov r18,r2 + 100b20c: 3027883a mov r19,r6 + 100b210: 32ff9e2e bgeu r6,r11,100b08c <__muldf3+0x1bc> + 100b214: 00800044 movi r2,1 + 100b218: 8089883a add r4,r16,r2 + 100b21c: 240d803a cmpltu r6,r4,r16 + 100b220: 344d883a add r6,r6,r17 + 100b224: 2021883a mov r16,r4 + 100b228: 3023883a mov r17,r6 + 100b22c: 003f9806 br 100b090 <__muldf3+0x1c0> + 100b230: 403fe71e bne r8,zero,100b1d0 <__muldf3+0x300> + 100b234: 01004004 movi r4,256 + 100b238: 4904703a and r2,r9,r4 + 100b23c: 10c4b03a or r2,r2,r3 + 100b240: 103fe31e bne r2,zero,100b1d0 <__muldf3+0x300> + 100b244: 94c4b03a or r2,r18,r19 + 100b248: 103fe126 beq r2,zero,100b1d0 <__muldf3+0x300> + 100b24c: 49c5883a add r2,r9,r7 + 100b250: 1251803a cmpltu r8,r2,r9 + 100b254: 4291883a add r8,r8,r10 + 100b258: 013fc004 movi r4,-256 + 100b25c: 1112703a and r9,r2,r4 + 100b260: 4015883a mov r10,r8 + 100b264: 003fda06 br 100b1d0 <__muldf3+0x300> + 100b268: 6813883a mov r9,r13 + 100b26c: 003fce06 br 100b1a8 <__muldf3+0x2d8> + 100b270: 143f7c36 bltu r2,r16,100b064 <__muldf3+0x194> + 100b274: 003fdd06 br 100b1ec <__muldf3+0x31c> + 100b278: 12bf852e bgeu r2,r10,100b090 <__muldf3+0x1c0> + 100b27c: 003fe506 br 100b214 <__muldf3+0x344> + 100b280: 00800084 movi r2,2 + 100b284: 20bf351e bne r4,r2,100af5c <__muldf3+0x8c> + 100b288: 010040b4 movhi r4,258 + 100b28c: 2123e904 addi r4,r4,-28764 + 100b290: 003f3f06 br 100af90 <__muldf3+0xc0> + +0100b294 <__divdf3>: + 100b294: deffed04 addi sp,sp,-76 + 100b298: dcc01115 stw r19,68(sp) + 100b29c: dcc00404 addi r19,sp,16 + 100b2a0: 2011883a mov r8,r4 + 100b2a4: 2813883a mov r9,r5 + 100b2a8: dc000e15 stw r16,56(sp) + 100b2ac: d809883a mov r4,sp + 100b2b0: 980b883a mov r5,r19 + 100b2b4: dc000904 addi r16,sp,36 + 100b2b8: dfc01215 stw ra,72(sp) + 100b2bc: da400115 stw r9,4(sp) + 100b2c0: d9c00315 stw r7,12(sp) + 100b2c4: da000015 stw r8,0(sp) + 100b2c8: d9800215 stw r6,8(sp) + 100b2cc: dc801015 stw r18,64(sp) + 100b2d0: dc400f15 stw r17,60(sp) + 100b2d4: 100c0700 call 100c070 <__unpack_d> + 100b2d8: d9000204 addi r4,sp,8 + 100b2dc: 800b883a mov r5,r16 + 100b2e0: 100c0700 call 100c070 <__unpack_d> + 100b2e4: d9000417 ldw r4,16(sp) + 100b2e8: 00800044 movi r2,1 + 100b2ec: 11000b2e bgeu r2,r4,100b31c <__divdf3+0x88> + 100b2f0: d9400917 ldw r5,36(sp) + 100b2f4: 1140762e bgeu r2,r5,100b4d0 <__divdf3+0x23c> + 100b2f8: d8800517 ldw r2,20(sp) + 100b2fc: d8c00a17 ldw r3,40(sp) + 100b300: 01800104 movi r6,4 + 100b304: 10c4f03a xor r2,r2,r3 + 100b308: d8800515 stw r2,20(sp) + 100b30c: 21800226 beq r4,r6,100b318 <__divdf3+0x84> + 100b310: 00800084 movi r2,2 + 100b314: 2080141e bne r4,r2,100b368 <__divdf3+0xd4> + 100b318: 29000926 beq r5,r4,100b340 <__divdf3+0xac> + 100b31c: 9809883a mov r4,r19 + 100b320: 100bd5c0 call 100bd5c <__pack_d> + 100b324: dfc01217 ldw ra,72(sp) + 100b328: dcc01117 ldw r19,68(sp) + 100b32c: dc801017 ldw r18,64(sp) + 100b330: dc400f17 ldw r17,60(sp) + 100b334: dc000e17 ldw r16,56(sp) + 100b338: dec01304 addi sp,sp,76 + 100b33c: f800283a ret + 100b340: 010040b4 movhi r4,258 + 100b344: 2123e904 addi r4,r4,-28764 + 100b348: 100bd5c0 call 100bd5c <__pack_d> + 100b34c: dfc01217 ldw ra,72(sp) + 100b350: dcc01117 ldw r19,68(sp) + 100b354: dc801017 ldw r18,64(sp) + 100b358: dc400f17 ldw r17,60(sp) + 100b35c: dc000e17 ldw r16,56(sp) + 100b360: dec01304 addi sp,sp,76 + 100b364: f800283a ret + 100b368: 29805b26 beq r5,r6,100b4d8 <__divdf3+0x244> + 100b36c: 28802d26 beq r5,r2,100b424 <__divdf3+0x190> + 100b370: d8c00617 ldw r3,24(sp) + 100b374: d8800b17 ldw r2,44(sp) + 100b378: d9c00817 ldw r7,32(sp) + 100b37c: dc400d17 ldw r17,52(sp) + 100b380: 188bc83a sub r5,r3,r2 + 100b384: d9800717 ldw r6,28(sp) + 100b388: dc000c17 ldw r16,48(sp) + 100b38c: d9400615 stw r5,24(sp) + 100b390: 3c403836 bltu r7,r17,100b474 <__divdf3+0x1e0> + 100b394: 89c03626 beq r17,r7,100b470 <__divdf3+0x1dc> + 100b398: 0015883a mov r10,zero + 100b39c: 001d883a mov r14,zero + 100b3a0: 02c40034 movhi r11,4096 + 100b3a4: 001f883a mov r15,zero + 100b3a8: 003f883a mov ra,zero + 100b3ac: 04800f44 movi r18,61 + 100b3b0: 00000f06 br 100b3f0 <__divdf3+0x15c> + 100b3b4: 601d883a mov r14,r12 + 100b3b8: 681f883a mov r15,r13 + 100b3bc: 400d883a mov r6,r8 + 100b3c0: 100f883a mov r7,r2 + 100b3c4: 3191883a add r8,r6,r6 + 100b3c8: 5808d07a srli r4,r11,1 + 100b3cc: 4185803a cmpltu r2,r8,r6 + 100b3d0: 39d3883a add r9,r7,r7 + 100b3d4: 28c6b03a or r3,r5,r3 + 100b3d8: 1245883a add r2,r2,r9 + 100b3dc: 1815883a mov r10,r3 + 100b3e0: 2017883a mov r11,r4 + 100b3e4: 400d883a mov r6,r8 + 100b3e8: 100f883a mov r7,r2 + 100b3ec: fc801726 beq ra,r18,100b44c <__divdf3+0x1b8> + 100b3f0: 580a97fa slli r5,r11,31 + 100b3f4: 5006d07a srli r3,r10,1 + 100b3f8: ffc00044 addi ra,ra,1 + 100b3fc: 3c7ff136 bltu r7,r17,100b3c4 <__divdf3+0x130> + 100b400: 3411c83a sub r8,r6,r16 + 100b404: 3205803a cmpltu r2,r6,r8 + 100b408: 3c53c83a sub r9,r7,r17 + 100b40c: 7298b03a or r12,r14,r10 + 100b410: 7adab03a or r13,r15,r11 + 100b414: 4885c83a sub r2,r9,r2 + 100b418: 89ffe61e bne r17,r7,100b3b4 <__divdf3+0x120> + 100b41c: 343fe936 bltu r6,r16,100b3c4 <__divdf3+0x130> + 100b420: 003fe406 br 100b3b4 <__divdf3+0x120> + 100b424: 9809883a mov r4,r19 + 100b428: d9800415 stw r6,16(sp) + 100b42c: 100bd5c0 call 100bd5c <__pack_d> + 100b430: dfc01217 ldw ra,72(sp) + 100b434: dcc01117 ldw r19,68(sp) + 100b438: dc801017 ldw r18,64(sp) + 100b43c: dc400f17 ldw r17,60(sp) + 100b440: dc000e17 ldw r16,56(sp) + 100b444: dec01304 addi sp,sp,76 + 100b448: f800283a ret + 100b44c: 00803fc4 movi r2,255 + 100b450: 7090703a and r8,r14,r2 + 100b454: 00802004 movi r2,128 + 100b458: 0007883a mov r3,zero + 100b45c: 0013883a mov r9,zero + 100b460: 40800d26 beq r8,r2,100b498 <__divdf3+0x204> + 100b464: dbc00815 stw r15,32(sp) + 100b468: db800715 stw r14,28(sp) + 100b46c: 003fab06 br 100b31c <__divdf3+0x88> + 100b470: 343fc92e bgeu r6,r16,100b398 <__divdf3+0x104> + 100b474: 3185883a add r2,r6,r6 + 100b478: 1189803a cmpltu r4,r2,r6 + 100b47c: 39c7883a add r3,r7,r7 + 100b480: 20c9883a add r4,r4,r3 + 100b484: 297fffc4 addi r5,r5,-1 + 100b488: 100d883a mov r6,r2 + 100b48c: 200f883a mov r7,r4 + 100b490: d9400615 stw r5,24(sp) + 100b494: 003fc006 br 100b398 <__divdf3+0x104> + 100b498: 483ff21e bne r9,zero,100b464 <__divdf3+0x1d0> + 100b49c: 01004004 movi r4,256 + 100b4a0: 7104703a and r2,r14,r4 + 100b4a4: 10c4b03a or r2,r2,r3 + 100b4a8: 103fee1e bne r2,zero,100b464 <__divdf3+0x1d0> + 100b4ac: 31c4b03a or r2,r6,r7 + 100b4b0: 103fec26 beq r2,zero,100b464 <__divdf3+0x1d0> + 100b4b4: 7205883a add r2,r14,r8 + 100b4b8: 1391803a cmpltu r8,r2,r14 + 100b4bc: 43d1883a add r8,r8,r15 + 100b4c0: 013fc004 movi r4,-256 + 100b4c4: 111c703a and r14,r2,r4 + 100b4c8: 401f883a mov r15,r8 + 100b4cc: 003fe506 br 100b464 <__divdf3+0x1d0> + 100b4d0: 8009883a mov r4,r16 + 100b4d4: 003f9206 br 100b320 <__divdf3+0x8c> + 100b4d8: 9809883a mov r4,r19 + 100b4dc: d8000715 stw zero,28(sp) + 100b4e0: d8000815 stw zero,32(sp) + 100b4e4: d8000615 stw zero,24(sp) + 100b4e8: 003f8d06 br 100b320 <__divdf3+0x8c> + +0100b4ec <__eqdf2>: + 100b4ec: deffef04 addi sp,sp,-68 + 100b4f0: dc400f15 stw r17,60(sp) + 100b4f4: dc400404 addi r17,sp,16 + 100b4f8: 2005883a mov r2,r4 + 100b4fc: 2807883a mov r3,r5 + 100b500: dc000e15 stw r16,56(sp) + 100b504: d809883a mov r4,sp + 100b508: 880b883a mov r5,r17 + 100b50c: dc000904 addi r16,sp,36 + 100b510: d8c00115 stw r3,4(sp) + 100b514: d8800015 stw r2,0(sp) + 100b518: d9800215 stw r6,8(sp) + 100b51c: dfc01015 stw ra,64(sp) + 100b520: d9c00315 stw r7,12(sp) + 100b524: 100c0700 call 100c070 <__unpack_d> + 100b528: d9000204 addi r4,sp,8 + 100b52c: 800b883a mov r5,r16 + 100b530: 100c0700 call 100c070 <__unpack_d> + 100b534: d8800417 ldw r2,16(sp) + 100b538: 00c00044 movi r3,1 + 100b53c: 180d883a mov r6,r3 + 100b540: 1880062e bgeu r3,r2,100b55c <__eqdf2+0x70> + 100b544: d8800917 ldw r2,36(sp) + 100b548: 8809883a mov r4,r17 + 100b54c: 800b883a mov r5,r16 + 100b550: 1880022e bgeu r3,r2,100b55c <__eqdf2+0x70> + 100b554: 100c1a80 call 100c1a8 <__fpcmp_parts_d> + 100b558: 100d883a mov r6,r2 + 100b55c: 3005883a mov r2,r6 + 100b560: dfc01017 ldw ra,64(sp) + 100b564: dc400f17 ldw r17,60(sp) + 100b568: dc000e17 ldw r16,56(sp) + 100b56c: dec01104 addi sp,sp,68 + 100b570: f800283a ret + +0100b574 <__nedf2>: + 100b574: deffef04 addi sp,sp,-68 + 100b578: dc400f15 stw r17,60(sp) + 100b57c: dc400404 addi r17,sp,16 + 100b580: 2005883a mov r2,r4 + 100b584: 2807883a mov r3,r5 + 100b588: dc000e15 stw r16,56(sp) + 100b58c: d809883a mov r4,sp + 100b590: 880b883a mov r5,r17 + 100b594: dc000904 addi r16,sp,36 + 100b598: d8c00115 stw r3,4(sp) + 100b59c: d8800015 stw r2,0(sp) + 100b5a0: d9800215 stw r6,8(sp) + 100b5a4: dfc01015 stw ra,64(sp) + 100b5a8: d9c00315 stw r7,12(sp) + 100b5ac: 100c0700 call 100c070 <__unpack_d> + 100b5b0: d9000204 addi r4,sp,8 + 100b5b4: 800b883a mov r5,r16 + 100b5b8: 100c0700 call 100c070 <__unpack_d> + 100b5bc: d8800417 ldw r2,16(sp) + 100b5c0: 00c00044 movi r3,1 + 100b5c4: 180d883a mov r6,r3 + 100b5c8: 1880062e bgeu r3,r2,100b5e4 <__nedf2+0x70> + 100b5cc: d8800917 ldw r2,36(sp) + 100b5d0: 8809883a mov r4,r17 + 100b5d4: 800b883a mov r5,r16 + 100b5d8: 1880022e bgeu r3,r2,100b5e4 <__nedf2+0x70> + 100b5dc: 100c1a80 call 100c1a8 <__fpcmp_parts_d> + 100b5e0: 100d883a mov r6,r2 + 100b5e4: 3005883a mov r2,r6 + 100b5e8: dfc01017 ldw ra,64(sp) + 100b5ec: dc400f17 ldw r17,60(sp) + 100b5f0: dc000e17 ldw r16,56(sp) + 100b5f4: dec01104 addi sp,sp,68 + 100b5f8: f800283a ret + +0100b5fc <__gtdf2>: + 100b5fc: deffef04 addi sp,sp,-68 + 100b600: dc400f15 stw r17,60(sp) + 100b604: dc400404 addi r17,sp,16 + 100b608: 2005883a mov r2,r4 + 100b60c: 2807883a mov r3,r5 + 100b610: dc000e15 stw r16,56(sp) + 100b614: d809883a mov r4,sp + 100b618: 880b883a mov r5,r17 + 100b61c: dc000904 addi r16,sp,36 + 100b620: d8c00115 stw r3,4(sp) + 100b624: d8800015 stw r2,0(sp) + 100b628: d9800215 stw r6,8(sp) + 100b62c: dfc01015 stw ra,64(sp) + 100b630: d9c00315 stw r7,12(sp) + 100b634: 100c0700 call 100c070 <__unpack_d> + 100b638: d9000204 addi r4,sp,8 + 100b63c: 800b883a mov r5,r16 + 100b640: 100c0700 call 100c070 <__unpack_d> + 100b644: d8800417 ldw r2,16(sp) + 100b648: 00c00044 movi r3,1 + 100b64c: 01bfffc4 movi r6,-1 + 100b650: 1880062e bgeu r3,r2,100b66c <__gtdf2+0x70> + 100b654: d8800917 ldw r2,36(sp) + 100b658: 8809883a mov r4,r17 + 100b65c: 800b883a mov r5,r16 + 100b660: 1880022e bgeu r3,r2,100b66c <__gtdf2+0x70> + 100b664: 100c1a80 call 100c1a8 <__fpcmp_parts_d> + 100b668: 100d883a mov r6,r2 + 100b66c: 3005883a mov r2,r6 + 100b670: dfc01017 ldw ra,64(sp) + 100b674: dc400f17 ldw r17,60(sp) + 100b678: dc000e17 ldw r16,56(sp) + 100b67c: dec01104 addi sp,sp,68 + 100b680: f800283a ret + +0100b684 <__gedf2>: + 100b684: deffef04 addi sp,sp,-68 + 100b688: dc400f15 stw r17,60(sp) + 100b68c: dc400404 addi r17,sp,16 + 100b690: 2005883a mov r2,r4 + 100b694: 2807883a mov r3,r5 + 100b698: dc000e15 stw r16,56(sp) + 100b69c: d809883a mov r4,sp + 100b6a0: 880b883a mov r5,r17 + 100b6a4: dc000904 addi r16,sp,36 + 100b6a8: d8c00115 stw r3,4(sp) + 100b6ac: d8800015 stw r2,0(sp) + 100b6b0: d9800215 stw r6,8(sp) + 100b6b4: dfc01015 stw ra,64(sp) + 100b6b8: d9c00315 stw r7,12(sp) + 100b6bc: 100c0700 call 100c070 <__unpack_d> + 100b6c0: d9000204 addi r4,sp,8 + 100b6c4: 800b883a mov r5,r16 + 100b6c8: 100c0700 call 100c070 <__unpack_d> + 100b6cc: d8800417 ldw r2,16(sp) + 100b6d0: 00c00044 movi r3,1 + 100b6d4: 01bfffc4 movi r6,-1 + 100b6d8: 1880062e bgeu r3,r2,100b6f4 <__gedf2+0x70> + 100b6dc: d8800917 ldw r2,36(sp) + 100b6e0: 8809883a mov r4,r17 + 100b6e4: 800b883a mov r5,r16 + 100b6e8: 1880022e bgeu r3,r2,100b6f4 <__gedf2+0x70> + 100b6ec: 100c1a80 call 100c1a8 <__fpcmp_parts_d> + 100b6f0: 100d883a mov r6,r2 + 100b6f4: 3005883a mov r2,r6 + 100b6f8: dfc01017 ldw ra,64(sp) + 100b6fc: dc400f17 ldw r17,60(sp) + 100b700: dc000e17 ldw r16,56(sp) + 100b704: dec01104 addi sp,sp,68 + 100b708: f800283a ret + +0100b70c <__ltdf2>: + 100b70c: deffef04 addi sp,sp,-68 + 100b710: dc400f15 stw r17,60(sp) + 100b714: dc400404 addi r17,sp,16 + 100b718: 2005883a mov r2,r4 + 100b71c: 2807883a mov r3,r5 + 100b720: dc000e15 stw r16,56(sp) + 100b724: d809883a mov r4,sp + 100b728: 880b883a mov r5,r17 + 100b72c: dc000904 addi r16,sp,36 + 100b730: d8c00115 stw r3,4(sp) + 100b734: d8800015 stw r2,0(sp) + 100b738: d9800215 stw r6,8(sp) + 100b73c: dfc01015 stw ra,64(sp) + 100b740: d9c00315 stw r7,12(sp) + 100b744: 100c0700 call 100c070 <__unpack_d> + 100b748: d9000204 addi r4,sp,8 + 100b74c: 800b883a mov r5,r16 + 100b750: 100c0700 call 100c070 <__unpack_d> + 100b754: d8800417 ldw r2,16(sp) + 100b758: 00c00044 movi r3,1 + 100b75c: 180d883a mov r6,r3 + 100b760: 1880062e bgeu r3,r2,100b77c <__ltdf2+0x70> + 100b764: d8800917 ldw r2,36(sp) + 100b768: 8809883a mov r4,r17 + 100b76c: 800b883a mov r5,r16 + 100b770: 1880022e bgeu r3,r2,100b77c <__ltdf2+0x70> + 100b774: 100c1a80 call 100c1a8 <__fpcmp_parts_d> + 100b778: 100d883a mov r6,r2 + 100b77c: 3005883a mov r2,r6 + 100b780: dfc01017 ldw ra,64(sp) + 100b784: dc400f17 ldw r17,60(sp) + 100b788: dc000e17 ldw r16,56(sp) + 100b78c: dec01104 addi sp,sp,68 + 100b790: f800283a ret + +0100b794 <__floatsidf>: + 100b794: 2006d7fa srli r3,r4,31 + 100b798: defff604 addi sp,sp,-40 + 100b79c: 008000c4 movi r2,3 + 100b7a0: dfc00915 stw ra,36(sp) + 100b7a4: dcc00815 stw r19,32(sp) + 100b7a8: dc800715 stw r18,28(sp) + 100b7ac: dc400615 stw r17,24(sp) + 100b7b0: dc000515 stw r16,20(sp) + 100b7b4: d8800015 stw r2,0(sp) + 100b7b8: d8c00115 stw r3,4(sp) + 100b7bc: 20000f1e bne r4,zero,100b7fc <__floatsidf+0x68> + 100b7c0: 00800084 movi r2,2 + 100b7c4: d8800015 stw r2,0(sp) + 100b7c8: d809883a mov r4,sp + 100b7cc: 100bd5c0 call 100bd5c <__pack_d> + 100b7d0: 1009883a mov r4,r2 + 100b7d4: 180b883a mov r5,r3 + 100b7d8: 2005883a mov r2,r4 + 100b7dc: 2807883a mov r3,r5 + 100b7e0: dfc00917 ldw ra,36(sp) + 100b7e4: dcc00817 ldw r19,32(sp) + 100b7e8: dc800717 ldw r18,28(sp) + 100b7ec: dc400617 ldw r17,24(sp) + 100b7f0: dc000517 ldw r16,20(sp) + 100b7f4: dec00a04 addi sp,sp,40 + 100b7f8: f800283a ret + 100b7fc: 00800f04 movi r2,60 + 100b800: 1807003a cmpeq r3,r3,zero + 100b804: d8800215 stw r2,8(sp) + 100b808: 18001126 beq r3,zero,100b850 <__floatsidf+0xbc> + 100b80c: 0027883a mov r19,zero + 100b810: 2025883a mov r18,r4 + 100b814: d9000315 stw r4,12(sp) + 100b818: dcc00415 stw r19,16(sp) + 100b81c: 100bcdc0 call 100bcdc <__clzsi2> + 100b820: 11000744 addi r4,r2,29 + 100b824: 013fe80e bge zero,r4,100b7c8 <__floatsidf+0x34> + 100b828: 10bfff44 addi r2,r2,-3 + 100b82c: 10000c16 blt r2,zero,100b860 <__floatsidf+0xcc> + 100b830: 90a2983a sll r17,r18,r2 + 100b834: 0021883a mov r16,zero + 100b838: d8800217 ldw r2,8(sp) + 100b83c: dc400415 stw r17,16(sp) + 100b840: dc000315 stw r16,12(sp) + 100b844: 1105c83a sub r2,r2,r4 + 100b848: d8800215 stw r2,8(sp) + 100b84c: 003fde06 br 100b7c8 <__floatsidf+0x34> + 100b850: 00a00034 movhi r2,32768 + 100b854: 20800a26 beq r4,r2,100b880 <__floatsidf+0xec> + 100b858: 0109c83a sub r4,zero,r4 + 100b85c: 003feb06 br 100b80c <__floatsidf+0x78> + 100b860: 9006d07a srli r3,r18,1 + 100b864: 008007c4 movi r2,31 + 100b868: 1105c83a sub r2,r2,r4 + 100b86c: 1886d83a srl r3,r3,r2 + 100b870: 9922983a sll r17,r19,r4 + 100b874: 9120983a sll r16,r18,r4 + 100b878: 1c62b03a or r17,r3,r17 + 100b87c: 003fee06 br 100b838 <__floatsidf+0xa4> + 100b880: 0009883a mov r4,zero + 100b884: 01707834 movhi r5,49632 + 100b888: 003fd306 br 100b7d8 <__floatsidf+0x44> + +0100b88c <__fixdfsi>: + 100b88c: defff804 addi sp,sp,-32 + 100b890: 2005883a mov r2,r4 + 100b894: 2807883a mov r3,r5 + 100b898: d809883a mov r4,sp + 100b89c: d9400204 addi r5,sp,8 + 100b8a0: d8c00115 stw r3,4(sp) + 100b8a4: d8800015 stw r2,0(sp) + 100b8a8: dfc00715 stw ra,28(sp) + 100b8ac: 100c0700 call 100c070 <__unpack_d> + 100b8b0: d8c00217 ldw r3,8(sp) + 100b8b4: 00800084 movi r2,2 + 100b8b8: 1880051e bne r3,r2,100b8d0 <__fixdfsi+0x44> + 100b8bc: 0007883a mov r3,zero + 100b8c0: 1805883a mov r2,r3 + 100b8c4: dfc00717 ldw ra,28(sp) + 100b8c8: dec00804 addi sp,sp,32 + 100b8cc: f800283a ret + 100b8d0: 00800044 movi r2,1 + 100b8d4: 10fff92e bgeu r2,r3,100b8bc <__fixdfsi+0x30> + 100b8d8: 00800104 movi r2,4 + 100b8dc: 18800426 beq r3,r2,100b8f0 <__fixdfsi+0x64> + 100b8e0: d8c00417 ldw r3,16(sp) + 100b8e4: 183ff516 blt r3,zero,100b8bc <__fixdfsi+0x30> + 100b8e8: 00800784 movi r2,30 + 100b8ec: 10c0080e bge r2,r3,100b910 <__fixdfsi+0x84> + 100b8f0: d8800317 ldw r2,12(sp) + 100b8f4: 1000121e bne r2,zero,100b940 <__fixdfsi+0xb4> + 100b8f8: 00e00034 movhi r3,32768 + 100b8fc: 18ffffc4 addi r3,r3,-1 + 100b900: 1805883a mov r2,r3 + 100b904: dfc00717 ldw ra,28(sp) + 100b908: dec00804 addi sp,sp,32 + 100b90c: f800283a ret + 100b910: 00800f04 movi r2,60 + 100b914: 10d1c83a sub r8,r2,r3 + 100b918: 40bff804 addi r2,r8,-32 + 100b91c: d9800517 ldw r6,20(sp) + 100b920: d9c00617 ldw r7,24(sp) + 100b924: 10000816 blt r2,zero,100b948 <__fixdfsi+0xbc> + 100b928: 3888d83a srl r4,r7,r2 + 100b92c: d8800317 ldw r2,12(sp) + 100b930: 2007883a mov r3,r4 + 100b934: 103fe226 beq r2,zero,100b8c0 <__fixdfsi+0x34> + 100b938: 0107c83a sub r3,zero,r4 + 100b93c: 003fe006 br 100b8c0 <__fixdfsi+0x34> + 100b940: 00e00034 movhi r3,32768 + 100b944: 003fde06 br 100b8c0 <__fixdfsi+0x34> + 100b948: 39c7883a add r3,r7,r7 + 100b94c: 008007c4 movi r2,31 + 100b950: 1205c83a sub r2,r2,r8 + 100b954: 1886983a sll r3,r3,r2 + 100b958: 3208d83a srl r4,r6,r8 + 100b95c: 1908b03a or r4,r3,r4 + 100b960: 003ff206 br 100b92c <__fixdfsi+0xa0> + +0100b964 <__floatunsidf>: + 100b964: defff204 addi sp,sp,-56 + 100b968: dfc00d15 stw ra,52(sp) + 100b96c: ddc00c15 stw r23,48(sp) + 100b970: dd800b15 stw r22,44(sp) + 100b974: dd400a15 stw r21,40(sp) + 100b978: dd000915 stw r20,36(sp) + 100b97c: dcc00815 stw r19,32(sp) + 100b980: dc800715 stw r18,28(sp) + 100b984: dc400615 stw r17,24(sp) + 100b988: dc000515 stw r16,20(sp) + 100b98c: d8000115 stw zero,4(sp) + 100b990: 20000f1e bne r4,zero,100b9d0 <__floatunsidf+0x6c> + 100b994: 00800084 movi r2,2 + 100b998: d8800015 stw r2,0(sp) + 100b99c: d809883a mov r4,sp + 100b9a0: 100bd5c0 call 100bd5c <__pack_d> + 100b9a4: dfc00d17 ldw ra,52(sp) + 100b9a8: ddc00c17 ldw r23,48(sp) + 100b9ac: dd800b17 ldw r22,44(sp) + 100b9b0: dd400a17 ldw r21,40(sp) + 100b9b4: dd000917 ldw r20,36(sp) + 100b9b8: dcc00817 ldw r19,32(sp) + 100b9bc: dc800717 ldw r18,28(sp) + 100b9c0: dc400617 ldw r17,24(sp) + 100b9c4: dc000517 ldw r16,20(sp) + 100b9c8: dec00e04 addi sp,sp,56 + 100b9cc: f800283a ret + 100b9d0: 008000c4 movi r2,3 + 100b9d4: 00c00f04 movi r3,60 + 100b9d8: 002f883a mov r23,zero + 100b9dc: 202d883a mov r22,r4 + 100b9e0: d8800015 stw r2,0(sp) + 100b9e4: d8c00215 stw r3,8(sp) + 100b9e8: d9000315 stw r4,12(sp) + 100b9ec: ddc00415 stw r23,16(sp) + 100b9f0: 100bcdc0 call 100bcdc <__clzsi2> + 100b9f4: 12400744 addi r9,r2,29 + 100b9f8: 48000b16 blt r9,zero,100ba28 <__floatunsidf+0xc4> + 100b9fc: 483fe726 beq r9,zero,100b99c <__floatunsidf+0x38> + 100ba00: 10bfff44 addi r2,r2,-3 + 100ba04: 10002e16 blt r2,zero,100bac0 <__floatunsidf+0x15c> + 100ba08: b0a2983a sll r17,r22,r2 + 100ba0c: 0021883a mov r16,zero + 100ba10: d8800217 ldw r2,8(sp) + 100ba14: dc400415 stw r17,16(sp) + 100ba18: dc000315 stw r16,12(sp) + 100ba1c: 1245c83a sub r2,r2,r9 + 100ba20: d8800215 stw r2,8(sp) + 100ba24: 003fdd06 br 100b99c <__floatunsidf+0x38> + 100ba28: 0255c83a sub r10,zero,r9 + 100ba2c: 51bff804 addi r6,r10,-32 + 100ba30: 30001b16 blt r6,zero,100baa0 <__floatunsidf+0x13c> + 100ba34: b9a8d83a srl r20,r23,r6 + 100ba38: 002b883a mov r21,zero + 100ba3c: 000f883a mov r7,zero + 100ba40: 01000044 movi r4,1 + 100ba44: 0011883a mov r8,zero + 100ba48: 30002516 blt r6,zero,100bae0 <__floatunsidf+0x17c> + 100ba4c: 21a6983a sll r19,r4,r6 + 100ba50: 0025883a mov r18,zero + 100ba54: 00bfffc4 movi r2,-1 + 100ba58: 9089883a add r4,r18,r2 + 100ba5c: 988b883a add r5,r19,r2 + 100ba60: 248d803a cmpltu r6,r4,r18 + 100ba64: 314b883a add r5,r6,r5 + 100ba68: b104703a and r2,r22,r4 + 100ba6c: b946703a and r3,r23,r5 + 100ba70: 10c4b03a or r2,r2,r3 + 100ba74: 10000226 beq r2,zero,100ba80 <__floatunsidf+0x11c> + 100ba78: 01c00044 movi r7,1 + 100ba7c: 0011883a mov r8,zero + 100ba80: d9000217 ldw r4,8(sp) + 100ba84: a1c4b03a or r2,r20,r7 + 100ba88: aa06b03a or r3,r21,r8 + 100ba8c: 2249c83a sub r4,r4,r9 + 100ba90: d8c00415 stw r3,16(sp) + 100ba94: d9000215 stw r4,8(sp) + 100ba98: d8800315 stw r2,12(sp) + 100ba9c: 003fbf06 br 100b99c <__floatunsidf+0x38> + 100baa0: bdc7883a add r3,r23,r23 + 100baa4: 008007c4 movi r2,31 + 100baa8: 1285c83a sub r2,r2,r10 + 100baac: 1886983a sll r3,r3,r2 + 100bab0: b2a8d83a srl r20,r22,r10 + 100bab4: baaad83a srl r21,r23,r10 + 100bab8: 1d28b03a or r20,r3,r20 + 100babc: 003fdf06 br 100ba3c <__floatunsidf+0xd8> + 100bac0: b006d07a srli r3,r22,1 + 100bac4: 008007c4 movi r2,31 + 100bac8: 1245c83a sub r2,r2,r9 + 100bacc: 1886d83a srl r3,r3,r2 + 100bad0: ba62983a sll r17,r23,r9 + 100bad4: b260983a sll r16,r22,r9 + 100bad8: 1c62b03a or r17,r3,r17 + 100badc: 003fcc06 br 100ba10 <__floatunsidf+0xac> + 100bae0: 2006d07a srli r3,r4,1 + 100bae4: 008007c4 movi r2,31 + 100bae8: 1285c83a sub r2,r2,r10 + 100baec: 18a6d83a srl r19,r3,r2 + 100baf0: 22a4983a sll r18,r4,r10 + 100baf4: 003fd706 br 100ba54 <__floatunsidf+0xf0> + +0100baf8 : + 100baf8: 29001b2e bgeu r5,r4,100bb68 + 100bafc: 28001a16 blt r5,zero,100bb68 + 100bb00: 00800044 movi r2,1 + 100bb04: 0007883a mov r3,zero + 100bb08: 01c007c4 movi r7,31 + 100bb0c: 00000306 br 100bb1c + 100bb10: 19c01326 beq r3,r7,100bb60 + 100bb14: 18c00044 addi r3,r3,1 + 100bb18: 28000416 blt r5,zero,100bb2c + 100bb1c: 294b883a add r5,r5,r5 + 100bb20: 1085883a add r2,r2,r2 + 100bb24: 293ffa36 bltu r5,r4,100bb10 + 100bb28: 10000d26 beq r2,zero,100bb60 + 100bb2c: 0007883a mov r3,zero + 100bb30: 21400236 bltu r4,r5,100bb3c + 100bb34: 2149c83a sub r4,r4,r5 + 100bb38: 1886b03a or r3,r3,r2 + 100bb3c: 1004d07a srli r2,r2,1 + 100bb40: 280ad07a srli r5,r5,1 + 100bb44: 103ffa1e bne r2,zero,100bb30 + 100bb48: 30000226 beq r6,zero,100bb54 + 100bb4c: 2005883a mov r2,r4 + 100bb50: f800283a ret + 100bb54: 1809883a mov r4,r3 + 100bb58: 2005883a mov r2,r4 + 100bb5c: f800283a ret + 100bb60: 0007883a mov r3,zero + 100bb64: 003ff806 br 100bb48 + 100bb68: 00800044 movi r2,1 + 100bb6c: 0007883a mov r3,zero + 100bb70: 003fef06 br 100bb30 + +0100bb74 <__divsi3>: + 100bb74: defffe04 addi sp,sp,-8 + 100bb78: dc000015 stw r16,0(sp) + 100bb7c: dfc00115 stw ra,4(sp) + 100bb80: 0021883a mov r16,zero + 100bb84: 20000c16 blt r4,zero,100bbb8 <__divsi3+0x44> + 100bb88: 000d883a mov r6,zero + 100bb8c: 28000e16 blt r5,zero,100bbc8 <__divsi3+0x54> + 100bb90: 100baf80 call 100baf8 + 100bb94: 1007883a mov r3,r2 + 100bb98: 8005003a cmpeq r2,r16,zero + 100bb9c: 1000011e bne r2,zero,100bba4 <__divsi3+0x30> + 100bba0: 00c7c83a sub r3,zero,r3 + 100bba4: 1805883a mov r2,r3 + 100bba8: dfc00117 ldw ra,4(sp) + 100bbac: dc000017 ldw r16,0(sp) + 100bbb0: dec00204 addi sp,sp,8 + 100bbb4: f800283a ret + 100bbb8: 0109c83a sub r4,zero,r4 + 100bbbc: 04000044 movi r16,1 + 100bbc0: 000d883a mov r6,zero + 100bbc4: 283ff20e bge r5,zero,100bb90 <__divsi3+0x1c> + 100bbc8: 014bc83a sub r5,zero,r5 + 100bbcc: 8021003a cmpeq r16,r16,zero + 100bbd0: 003fef06 br 100bb90 <__divsi3+0x1c> + +0100bbd4 <__modsi3>: + 100bbd4: deffff04 addi sp,sp,-4 + 100bbd8: dfc00015 stw ra,0(sp) + 100bbdc: 01800044 movi r6,1 + 100bbe0: 2807883a mov r3,r5 + 100bbe4: 20000416 blt r4,zero,100bbf8 <__modsi3+0x24> + 100bbe8: 28000c16 blt r5,zero,100bc1c <__modsi3+0x48> + 100bbec: dfc00017 ldw ra,0(sp) + 100bbf0: dec00104 addi sp,sp,4 + 100bbf4: 100baf81 jmpi 100baf8 + 100bbf8: 0109c83a sub r4,zero,r4 + 100bbfc: 28000b16 blt r5,zero,100bc2c <__modsi3+0x58> + 100bc00: 180b883a mov r5,r3 + 100bc04: 01800044 movi r6,1 + 100bc08: 100baf80 call 100baf8 + 100bc0c: 0085c83a sub r2,zero,r2 + 100bc10: dfc00017 ldw ra,0(sp) + 100bc14: dec00104 addi sp,sp,4 + 100bc18: f800283a ret + 100bc1c: 014bc83a sub r5,zero,r5 + 100bc20: dfc00017 ldw ra,0(sp) + 100bc24: dec00104 addi sp,sp,4 + 100bc28: 100baf81 jmpi 100baf8 + 100bc2c: 0147c83a sub r3,zero,r5 + 100bc30: 003ff306 br 100bc00 <__modsi3+0x2c> + +0100bc34 <__udivsi3>: + 100bc34: 000d883a mov r6,zero + 100bc38: 100baf81 jmpi 100baf8 + +0100bc3c <__umodsi3>: + 100bc3c: 01800044 movi r6,1 + 100bc40: 100baf81 jmpi 100baf8 + +0100bc44 <__muldi3>: + 100bc44: 2011883a mov r8,r4 + 100bc48: 427fffcc andi r9,r8,65535 + 100bc4c: 4018d43a srli r12,r8,16 + 100bc50: 32bfffcc andi r10,r6,65535 + 100bc54: 3016d43a srli r11,r6,16 + 100bc58: 4a85383a mul r2,r9,r10 + 100bc5c: 6295383a mul r10,r12,r10 + 100bc60: 4ad3383a mul r9,r9,r11 + 100bc64: 113fffcc andi r4,r2,65535 + 100bc68: 1004d43a srli r2,r2,16 + 100bc6c: 4a93883a add r9,r9,r10 + 100bc70: 3807883a mov r3,r7 + 100bc74: 1245883a add r2,r2,r9 + 100bc78: 280f883a mov r7,r5 + 100bc7c: 180b883a mov r5,r3 + 100bc80: 1006943a slli r3,r2,16 + 100bc84: defffd04 addi sp,sp,-12 + 100bc88: dc800215 stw r18,8(sp) + 100bc8c: 1907883a add r3,r3,r4 + 100bc90: dc400115 stw r17,4(sp) + 100bc94: dc000015 stw r16,0(sp) + 100bc98: 4165383a mul r18,r8,r5 + 100bc9c: 31e3383a mul r17,r6,r7 + 100bca0: 1012d43a srli r9,r2,16 + 100bca4: 62d9383a mul r12,r12,r11 + 100bca8: 181f883a mov r15,r3 + 100bcac: 1280022e bgeu r2,r10,100bcb8 <__muldi3+0x74> + 100bcb0: 00800074 movhi r2,1 + 100bcb4: 6099883a add r12,r12,r2 + 100bcb8: 624d883a add r6,r12,r9 + 100bcbc: 9187883a add r3,r18,r6 + 100bcc0: 88c7883a add r3,r17,r3 + 100bcc4: 7805883a mov r2,r15 + 100bcc8: dc800217 ldw r18,8(sp) + 100bccc: dc400117 ldw r17,4(sp) + 100bcd0: dc000017 ldw r16,0(sp) + 100bcd4: dec00304 addi sp,sp,12 + 100bcd8: f800283a ret + +0100bcdc <__clzsi2>: + 100bcdc: 00bfffd4 movui r2,65535 + 100bce0: 11000e36 bltu r2,r4,100bd1c <__clzsi2+0x40> + 100bce4: 00803fc4 movi r2,255 + 100bce8: 01400204 movi r5,8 + 100bcec: 0007883a mov r3,zero + 100bcf0: 11001036 bltu r2,r4,100bd34 <__clzsi2+0x58> + 100bcf4: 000b883a mov r5,zero + 100bcf8: 20c6d83a srl r3,r4,r3 + 100bcfc: 008040b4 movhi r2,258 + 100bd00: 10a3ee04 addi r2,r2,-28744 + 100bd04: 1887883a add r3,r3,r2 + 100bd08: 18800003 ldbu r2,0(r3) + 100bd0c: 00c00804 movi r3,32 + 100bd10: 2885883a add r2,r5,r2 + 100bd14: 1885c83a sub r2,r3,r2 + 100bd18: f800283a ret + 100bd1c: 01400404 movi r5,16 + 100bd20: 00804034 movhi r2,256 + 100bd24: 10bfffc4 addi r2,r2,-1 + 100bd28: 2807883a mov r3,r5 + 100bd2c: 113ff22e bgeu r2,r4,100bcf8 <__clzsi2+0x1c> + 100bd30: 01400604 movi r5,24 + 100bd34: 2807883a mov r3,r5 + 100bd38: 20c6d83a srl r3,r4,r3 + 100bd3c: 008040b4 movhi r2,258 + 100bd40: 10a3ee04 addi r2,r2,-28744 + 100bd44: 1887883a add r3,r3,r2 + 100bd48: 18800003 ldbu r2,0(r3) + 100bd4c: 00c00804 movi r3,32 + 100bd50: 2885883a add r2,r5,r2 + 100bd54: 1885c83a sub r2,r3,r2 + 100bd58: f800283a ret + +0100bd5c <__pack_d>: + 100bd5c: 20c00017 ldw r3,0(r4) + 100bd60: defffd04 addi sp,sp,-12 + 100bd64: dc000015 stw r16,0(sp) + 100bd68: dc800215 stw r18,8(sp) + 100bd6c: dc400115 stw r17,4(sp) + 100bd70: 00800044 movi r2,1 + 100bd74: 22000317 ldw r8,12(r4) + 100bd78: 001f883a mov r15,zero + 100bd7c: 22400417 ldw r9,16(r4) + 100bd80: 24000117 ldw r16,4(r4) + 100bd84: 10c0552e bgeu r2,r3,100bedc <__pack_d+0x180> + 100bd88: 00800104 movi r2,4 + 100bd8c: 18804f26 beq r3,r2,100becc <__pack_d+0x170> + 100bd90: 00800084 movi r2,2 + 100bd94: 18800226 beq r3,r2,100bda0 <__pack_d+0x44> + 100bd98: 4244b03a or r2,r8,r9 + 100bd9c: 10001a1e bne r2,zero,100be08 <__pack_d+0xac> + 100bda0: 000d883a mov r6,zero + 100bda4: 000f883a mov r7,zero + 100bda8: 0011883a mov r8,zero + 100bdac: 00800434 movhi r2,16 + 100bdb0: 10bfffc4 addi r2,r2,-1 + 100bdb4: 301d883a mov r14,r6 + 100bdb8: 3884703a and r2,r7,r2 + 100bdbc: 400a953a slli r5,r8,20 + 100bdc0: 79bffc2c andhi r6,r15,65520 + 100bdc4: 308cb03a or r6,r6,r2 + 100bdc8: 00e00434 movhi r3,32784 + 100bdcc: 18ffffc4 addi r3,r3,-1 + 100bdd0: 800497fa slli r2,r16,31 + 100bdd4: 30c6703a and r3,r6,r3 + 100bdd8: 1946b03a or r3,r3,r5 + 100bddc: 01600034 movhi r5,32768 + 100bde0: 297fffc4 addi r5,r5,-1 + 100bde4: 194a703a and r5,r3,r5 + 100bde8: 288ab03a or r5,r5,r2 + 100bdec: 2807883a mov r3,r5 + 100bdf0: 7005883a mov r2,r14 + 100bdf4: dc800217 ldw r18,8(sp) + 100bdf8: dc400117 ldw r17,4(sp) + 100bdfc: dc000017 ldw r16,0(sp) + 100be00: dec00304 addi sp,sp,12 + 100be04: f800283a ret + 100be08: 21000217 ldw r4,8(r4) + 100be0c: 00bf0084 movi r2,-1022 + 100be10: 20803f16 blt r4,r2,100bf10 <__pack_d+0x1b4> + 100be14: 0080ffc4 movi r2,1023 + 100be18: 11002c16 blt r2,r4,100becc <__pack_d+0x170> + 100be1c: 00803fc4 movi r2,255 + 100be20: 408c703a and r6,r8,r2 + 100be24: 00802004 movi r2,128 + 100be28: 0007883a mov r3,zero + 100be2c: 000f883a mov r7,zero + 100be30: 2280ffc4 addi r10,r4,1023 + 100be34: 30801e26 beq r6,r2,100beb0 <__pack_d+0x154> + 100be38: 00801fc4 movi r2,127 + 100be3c: 4089883a add r4,r8,r2 + 100be40: 220d803a cmpltu r6,r4,r8 + 100be44: 324d883a add r6,r6,r9 + 100be48: 2011883a mov r8,r4 + 100be4c: 3013883a mov r9,r6 + 100be50: 00880034 movhi r2,8192 + 100be54: 10bfffc4 addi r2,r2,-1 + 100be58: 12400d36 bltu r2,r9,100be90 <__pack_d+0x134> + 100be5c: 4804963a slli r2,r9,24 + 100be60: 400cd23a srli r6,r8,8 + 100be64: 480ed23a srli r7,r9,8 + 100be68: 013fffc4 movi r4,-1 + 100be6c: 118cb03a or r6,r2,r6 + 100be70: 01400434 movhi r5,16 + 100be74: 297fffc4 addi r5,r5,-1 + 100be78: 3104703a and r2,r6,r4 + 100be7c: 3946703a and r3,r7,r5 + 100be80: 5201ffcc andi r8,r10,2047 + 100be84: 100d883a mov r6,r2 + 100be88: 180f883a mov r7,r3 + 100be8c: 003fc706 br 100bdac <__pack_d+0x50> + 100be90: 480897fa slli r4,r9,31 + 100be94: 4004d07a srli r2,r8,1 + 100be98: 4806d07a srli r3,r9,1 + 100be9c: 52800044 addi r10,r10,1 + 100bea0: 2084b03a or r2,r4,r2 + 100bea4: 1011883a mov r8,r2 + 100bea8: 1813883a mov r9,r3 + 100beac: 003feb06 br 100be5c <__pack_d+0x100> + 100beb0: 383fe11e bne r7,zero,100be38 <__pack_d+0xdc> + 100beb4: 01004004 movi r4,256 + 100beb8: 4104703a and r2,r8,r4 + 100bebc: 10c4b03a or r2,r2,r3 + 100bec0: 103fe326 beq r2,zero,100be50 <__pack_d+0xf4> + 100bec4: 3005883a mov r2,r6 + 100bec8: 003fdc06 br 100be3c <__pack_d+0xe0> + 100becc: 000d883a mov r6,zero + 100bed0: 000f883a mov r7,zero + 100bed4: 0201ffc4 movi r8,2047 + 100bed8: 003fb406 br 100bdac <__pack_d+0x50> + 100bedc: 0005883a mov r2,zero + 100bee0: 00c00234 movhi r3,8 + 100bee4: 408cb03a or r6,r8,r2 + 100bee8: 48ceb03a or r7,r9,r3 + 100beec: 013fffc4 movi r4,-1 + 100bef0: 01400434 movhi r5,16 + 100bef4: 297fffc4 addi r5,r5,-1 + 100bef8: 3104703a and r2,r6,r4 + 100befc: 3946703a and r3,r7,r5 + 100bf00: 100d883a mov r6,r2 + 100bf04: 180f883a mov r7,r3 + 100bf08: 0201ffc4 movi r8,2047 + 100bf0c: 003fa706 br 100bdac <__pack_d+0x50> + 100bf10: 1109c83a sub r4,r2,r4 + 100bf14: 00800e04 movi r2,56 + 100bf18: 11004316 blt r2,r4,100c028 <__pack_d+0x2cc> + 100bf1c: 21fff804 addi r7,r4,-32 + 100bf20: 38004516 blt r7,zero,100c038 <__pack_d+0x2dc> + 100bf24: 49d8d83a srl r12,r9,r7 + 100bf28: 001b883a mov r13,zero + 100bf2c: 0023883a mov r17,zero + 100bf30: 01400044 movi r5,1 + 100bf34: 0025883a mov r18,zero + 100bf38: 38004716 blt r7,zero,100c058 <__pack_d+0x2fc> + 100bf3c: 29d6983a sll r11,r5,r7 + 100bf40: 0015883a mov r10,zero + 100bf44: 00bfffc4 movi r2,-1 + 100bf48: 5089883a add r4,r10,r2 + 100bf4c: 588b883a add r5,r11,r2 + 100bf50: 228d803a cmpltu r6,r4,r10 + 100bf54: 314b883a add r5,r6,r5 + 100bf58: 4104703a and r2,r8,r4 + 100bf5c: 4946703a and r3,r9,r5 + 100bf60: 10c4b03a or r2,r2,r3 + 100bf64: 10000226 beq r2,zero,100bf70 <__pack_d+0x214> + 100bf68: 04400044 movi r17,1 + 100bf6c: 0025883a mov r18,zero + 100bf70: 00803fc4 movi r2,255 + 100bf74: 644eb03a or r7,r12,r17 + 100bf78: 3892703a and r9,r7,r2 + 100bf7c: 00802004 movi r2,128 + 100bf80: 6c90b03a or r8,r13,r18 + 100bf84: 0015883a mov r10,zero + 100bf88: 48801626 beq r9,r2,100bfe4 <__pack_d+0x288> + 100bf8c: 01001fc4 movi r4,127 + 100bf90: 3905883a add r2,r7,r4 + 100bf94: 11cd803a cmpltu r6,r2,r7 + 100bf98: 320d883a add r6,r6,r8 + 100bf9c: 100f883a mov r7,r2 + 100bfa0: 00840034 movhi r2,4096 + 100bfa4: 10bfffc4 addi r2,r2,-1 + 100bfa8: 3011883a mov r8,r6 + 100bfac: 0007883a mov r3,zero + 100bfb0: 11801b36 bltu r2,r6,100c020 <__pack_d+0x2c4> + 100bfb4: 4004963a slli r2,r8,24 + 100bfb8: 3808d23a srli r4,r7,8 + 100bfbc: 400ad23a srli r5,r8,8 + 100bfc0: 1813883a mov r9,r3 + 100bfc4: 1108b03a or r4,r2,r4 + 100bfc8: 00bfffc4 movi r2,-1 + 100bfcc: 00c00434 movhi r3,16 + 100bfd0: 18ffffc4 addi r3,r3,-1 + 100bfd4: 208c703a and r6,r4,r2 + 100bfd8: 28ce703a and r7,r5,r3 + 100bfdc: 4a01ffcc andi r8,r9,2047 + 100bfe0: 003f7206 br 100bdac <__pack_d+0x50> + 100bfe4: 503fe91e bne r10,zero,100bf8c <__pack_d+0x230> + 100bfe8: 01004004 movi r4,256 + 100bfec: 3904703a and r2,r7,r4 + 100bff0: 0007883a mov r3,zero + 100bff4: 10c4b03a or r2,r2,r3 + 100bff8: 10000626 beq r2,zero,100c014 <__pack_d+0x2b8> + 100bffc: 3a45883a add r2,r7,r9 + 100c000: 11cd803a cmpltu r6,r2,r7 + 100c004: 320d883a add r6,r6,r8 + 100c008: 100f883a mov r7,r2 + 100c00c: 3011883a mov r8,r6 + 100c010: 0007883a mov r3,zero + 100c014: 00840034 movhi r2,4096 + 100c018: 10bfffc4 addi r2,r2,-1 + 100c01c: 123fe52e bgeu r2,r8,100bfb4 <__pack_d+0x258> + 100c020: 00c00044 movi r3,1 + 100c024: 003fe306 br 100bfb4 <__pack_d+0x258> + 100c028: 0009883a mov r4,zero + 100c02c: 0013883a mov r9,zero + 100c030: 000b883a mov r5,zero + 100c034: 003fe406 br 100bfc8 <__pack_d+0x26c> + 100c038: 4a47883a add r3,r9,r9 + 100c03c: 008007c4 movi r2,31 + 100c040: 1105c83a sub r2,r2,r4 + 100c044: 1886983a sll r3,r3,r2 + 100c048: 4118d83a srl r12,r8,r4 + 100c04c: 491ad83a srl r13,r9,r4 + 100c050: 1b18b03a or r12,r3,r12 + 100c054: 003fb506 br 100bf2c <__pack_d+0x1d0> + 100c058: 2806d07a srli r3,r5,1 + 100c05c: 008007c4 movi r2,31 + 100c060: 1105c83a sub r2,r2,r4 + 100c064: 1896d83a srl r11,r3,r2 + 100c068: 2914983a sll r10,r5,r4 + 100c06c: 003fb506 br 100bf44 <__pack_d+0x1e8> + +0100c070 <__unpack_d>: + 100c070: 20c00117 ldw r3,4(r4) + 100c074: 22400017 ldw r9,0(r4) + 100c078: 00800434 movhi r2,16 + 100c07c: 10bfffc4 addi r2,r2,-1 + 100c080: 1808d53a srli r4,r3,20 + 100c084: 180cd7fa srli r6,r3,31 + 100c088: 1894703a and r10,r3,r2 + 100c08c: 2201ffcc andi r8,r4,2047 + 100c090: 281b883a mov r13,r5 + 100c094: 4817883a mov r11,r9 + 100c098: 29800115 stw r6,4(r5) + 100c09c: 5019883a mov r12,r10 + 100c0a0: 40001e1e bne r8,zero,100c11c <__unpack_d+0xac> + 100c0a4: 4a84b03a or r2,r9,r10 + 100c0a8: 10001926 beq r2,zero,100c110 <__unpack_d+0xa0> + 100c0ac: 4804d63a srli r2,r9,24 + 100c0b0: 500c923a slli r6,r10,8 + 100c0b4: 013f0084 movi r4,-1022 + 100c0b8: 00c40034 movhi r3,4096 + 100c0bc: 18ffffc4 addi r3,r3,-1 + 100c0c0: 118cb03a or r6,r2,r6 + 100c0c4: 008000c4 movi r2,3 + 100c0c8: 480a923a slli r5,r9,8 + 100c0cc: 68800015 stw r2,0(r13) + 100c0d0: 69000215 stw r4,8(r13) + 100c0d4: 19800b36 bltu r3,r6,100c104 <__unpack_d+0x94> + 100c0d8: 200f883a mov r7,r4 + 100c0dc: 1811883a mov r8,r3 + 100c0e0: 2945883a add r2,r5,r5 + 100c0e4: 1149803a cmpltu r4,r2,r5 + 100c0e8: 3187883a add r3,r6,r6 + 100c0ec: 20c9883a add r4,r4,r3 + 100c0f0: 100b883a mov r5,r2 + 100c0f4: 200d883a mov r6,r4 + 100c0f8: 39ffffc4 addi r7,r7,-1 + 100c0fc: 413ff82e bgeu r8,r4,100c0e0 <__unpack_d+0x70> + 100c100: 69c00215 stw r7,8(r13) + 100c104: 69800415 stw r6,16(r13) + 100c108: 69400315 stw r5,12(r13) + 100c10c: f800283a ret + 100c110: 00800084 movi r2,2 + 100c114: 28800015 stw r2,0(r5) + 100c118: f800283a ret + 100c11c: 0081ffc4 movi r2,2047 + 100c120: 40800f26 beq r8,r2,100c160 <__unpack_d+0xf0> + 100c124: 480cd63a srli r6,r9,24 + 100c128: 5006923a slli r3,r10,8 + 100c12c: 4804923a slli r2,r9,8 + 100c130: 0009883a mov r4,zero + 100c134: 30c6b03a or r3,r6,r3 + 100c138: 01440034 movhi r5,4096 + 100c13c: 110cb03a or r6,r2,r4 + 100c140: 423f0044 addi r8,r8,-1023 + 100c144: 194eb03a or r7,r3,r5 + 100c148: 008000c4 movi r2,3 + 100c14c: 69c00415 stw r7,16(r13) + 100c150: 6a000215 stw r8,8(r13) + 100c154: 68800015 stw r2,0(r13) + 100c158: 69800315 stw r6,12(r13) + 100c15c: f800283a ret + 100c160: 4a84b03a or r2,r9,r10 + 100c164: 1000031e bne r2,zero,100c174 <__unpack_d+0x104> + 100c168: 00800104 movi r2,4 + 100c16c: 28800015 stw r2,0(r5) + 100c170: f800283a ret + 100c174: 0009883a mov r4,zero + 100c178: 01400234 movhi r5,8 + 100c17c: 4904703a and r2,r9,r4 + 100c180: 5146703a and r3,r10,r5 + 100c184: 10c4b03a or r2,r2,r3 + 100c188: 10000526 beq r2,zero,100c1a0 <__unpack_d+0x130> + 100c18c: 00800044 movi r2,1 + 100c190: 68800015 stw r2,0(r13) + 100c194: 6b000415 stw r12,16(r13) + 100c198: 6ac00315 stw r11,12(r13) + 100c19c: f800283a ret + 100c1a0: 68000015 stw zero,0(r13) + 100c1a4: 003ffb06 br 100c194 <__unpack_d+0x124> + +0100c1a8 <__fpcmp_parts_d>: + 100c1a8: 21800017 ldw r6,0(r4) + 100c1ac: 00c00044 movi r3,1 + 100c1b0: 19800a2e bgeu r3,r6,100c1dc <__fpcmp_parts_d+0x34> + 100c1b4: 28800017 ldw r2,0(r5) + 100c1b8: 1880082e bgeu r3,r2,100c1dc <__fpcmp_parts_d+0x34> + 100c1bc: 00c00104 movi r3,4 + 100c1c0: 30c02626 beq r6,r3,100c25c <__fpcmp_parts_d+0xb4> + 100c1c4: 10c02226 beq r2,r3,100c250 <__fpcmp_parts_d+0xa8> + 100c1c8: 00c00084 movi r3,2 + 100c1cc: 30c00526 beq r6,r3,100c1e4 <__fpcmp_parts_d+0x3c> + 100c1d0: 10c0071e bne r2,r3,100c1f0 <__fpcmp_parts_d+0x48> + 100c1d4: 20800117 ldw r2,4(r4) + 100c1d8: 1000091e bne r2,zero,100c200 <__fpcmp_parts_d+0x58> + 100c1dc: 00800044 movi r2,1 + 100c1e0: f800283a ret + 100c1e4: 10c01a1e bne r2,r3,100c250 <__fpcmp_parts_d+0xa8> + 100c1e8: 0005883a mov r2,zero + 100c1ec: f800283a ret + 100c1f0: 22000117 ldw r8,4(r4) + 100c1f4: 28800117 ldw r2,4(r5) + 100c1f8: 40800326 beq r8,r2,100c208 <__fpcmp_parts_d+0x60> + 100c1fc: 403ff726 beq r8,zero,100c1dc <__fpcmp_parts_d+0x34> + 100c200: 00bfffc4 movi r2,-1 + 100c204: f800283a ret + 100c208: 20c00217 ldw r3,8(r4) + 100c20c: 28800217 ldw r2,8(r5) + 100c210: 10fffa16 blt r2,r3,100c1fc <__fpcmp_parts_d+0x54> + 100c214: 18800916 blt r3,r2,100c23c <__fpcmp_parts_d+0x94> + 100c218: 21c00417 ldw r7,16(r4) + 100c21c: 28c00417 ldw r3,16(r5) + 100c220: 21800317 ldw r6,12(r4) + 100c224: 28800317 ldw r2,12(r5) + 100c228: 19fff436 bltu r3,r7,100c1fc <__fpcmp_parts_d+0x54> + 100c22c: 38c00526 beq r7,r3,100c244 <__fpcmp_parts_d+0x9c> + 100c230: 38c00236 bltu r7,r3,100c23c <__fpcmp_parts_d+0x94> + 100c234: 19ffec1e bne r3,r7,100c1e8 <__fpcmp_parts_d+0x40> + 100c238: 30bfeb2e bgeu r6,r2,100c1e8 <__fpcmp_parts_d+0x40> + 100c23c: 403fe71e bne r8,zero,100c1dc <__fpcmp_parts_d+0x34> + 100c240: 003fef06 br 100c200 <__fpcmp_parts_d+0x58> + 100c244: 11bffa2e bgeu r2,r6,100c230 <__fpcmp_parts_d+0x88> + 100c248: 403fe426 beq r8,zero,100c1dc <__fpcmp_parts_d+0x34> + 100c24c: 003fec06 br 100c200 <__fpcmp_parts_d+0x58> + 100c250: 28800117 ldw r2,4(r5) + 100c254: 103fe11e bne r2,zero,100c1dc <__fpcmp_parts_d+0x34> + 100c258: 003fe906 br 100c200 <__fpcmp_parts_d+0x58> + 100c25c: 11bfdd1e bne r2,r6,100c1d4 <__fpcmp_parts_d+0x2c> + 100c260: 28c00117 ldw r3,4(r5) + 100c264: 20800117 ldw r2,4(r4) + 100c268: 1885c83a sub r2,r3,r2 + 100c26c: f800283a ret + +0100c270 : + * + * ALT_CLOSE is mapped onto the close() system call in alt_syscall.h + */ + +int ALT_CLOSE (int fildes) +{ + 100c270: defff804 addi sp,sp,-32 + 100c274: dfc00715 stw ra,28(sp) + 100c278: df000615 stw fp,24(sp) + 100c27c: df000604 addi fp,sp,24 + 100c280: e13ffc15 stw r4,-16(fp) + * A common error case is that when the file descriptor was created, the call + * to open() failed resulting in a negative file descriptor. This is trapped + * below so that we don't try and process an invalid file descriptor. + */ + + fd = (fildes < 0) ? NULL : &alt_fd_list[fildes]; + 100c284: e0bffc17 ldw r2,-16(fp) + 100c288: 1004803a cmplt r2,r2,zero + 100c28c: 1000081e bne r2,zero,100c2b0 + 100c290: e0bffc17 ldw r2,-16(fp) + 100c294: 10800324 muli r2,r2,12 + 100c298: 1007883a mov r3,r2 + 100c29c: 008040b4 movhi r2,258 + 100c2a0: 10a69f04 addi r2,r2,-25988 + 100c2a4: 1887883a add r3,r3,r2 + 100c2a8: e0ffff15 stw r3,-4(fp) + 100c2ac: 00000106 br 100c2b4 + 100c2b0: e03fff15 stw zero,-4(fp) + 100c2b4: e0bfff17 ldw r2,-4(fp) + 100c2b8: e0bffb15 stw r2,-20(fp) + + if (fd) + 100c2bc: e0bffb17 ldw r2,-20(fp) + 100c2c0: 1005003a cmpeq r2,r2,zero + 100c2c4: 10001d1e bne r2,zero,100c33c + /* + * If the associated file system/device has a close function, call it so + * that any necessary cleanup code can run. + */ + + rval = (fd->dev->close) ? fd->dev->close(fd) : 0; + 100c2c8: e0bffb17 ldw r2,-20(fp) + 100c2cc: 10800017 ldw r2,0(r2) + 100c2d0: 10800417 ldw r2,16(r2) + 100c2d4: 1005003a cmpeq r2,r2,zero + 100c2d8: 1000071e bne r2,zero,100c2f8 + 100c2dc: e0bffb17 ldw r2,-20(fp) + 100c2e0: 10800017 ldw r2,0(r2) + 100c2e4: 10800417 ldw r2,16(r2) + 100c2e8: e13ffb17 ldw r4,-20(fp) + 100c2ec: 103ee83a callr r2 + 100c2f0: e0bffe15 stw r2,-8(fp) + 100c2f4: 00000106 br 100c2fc + 100c2f8: e03ffe15 stw zero,-8(fp) + 100c2fc: e0bffe17 ldw r2,-8(fp) + 100c300: e0bffa15 stw r2,-24(fp) + + /* Free the file descriptor structure and return. */ + + alt_release_fd (fildes); + 100c304: e13ffc17 ldw r4,-16(fp) + 100c308: 100ccfc0 call 100ccfc + if (rval < 0) + 100c30c: e0bffa17 ldw r2,-24(fp) + 100c310: 1004403a cmpge r2,r2,zero + 100c314: 1000071e bne r2,zero,100c334 + { + ALT_ERRNO = -rval; + 100c318: 100c36c0 call 100c36c + 100c31c: e0fffa17 ldw r3,-24(fp) + 100c320: 00c7c83a sub r3,zero,r3 + 100c324: 10c00015 stw r3,0(r2) + return -1; + 100c328: 00bfffc4 movi r2,-1 + 100c32c: e0bffd15 stw r2,-12(fp) + 100c330: 00000806 br 100c354 + } + return 0; + 100c334: e03ffd15 stw zero,-12(fp) + 100c338: 00000606 br 100c354 + } + else + { + ALT_ERRNO = EBADFD; + 100c33c: 100c36c0 call 100c36c + 100c340: 1007883a mov r3,r2 + 100c344: 00801444 movi r2,81 + 100c348: 18800015 stw r2,0(r3) + return -1; + 100c34c: 00bfffc4 movi r2,-1 + 100c350: e0bffd15 stw r2,-12(fp) + 100c354: e0bffd17 ldw r2,-12(fp) + } +} + 100c358: e037883a mov sp,fp + 100c35c: dfc00117 ldw ra,4(sp) + 100c360: df000017 ldw fp,0(sp) + 100c364: dec00204 addi sp,sp,8 + 100c368: f800283a ret + +0100c36c : +#undef errno + +extern int errno; + +static ALT_INLINE int* alt_get_errno(void) +{ + 100c36c: defffd04 addi sp,sp,-12 + 100c370: dfc00215 stw ra,8(sp) + 100c374: df000115 stw fp,4(sp) + 100c378: df000104 addi fp,sp,4 + return ((alt_errno) ? alt_errno() : &errno); + 100c37c: 008040b4 movhi r2,258 + 100c380: 10aba104 addi r2,r2,-20860 + 100c384: 10800017 ldw r2,0(r2) + 100c388: 1005003a cmpeq r2,r2,zero + 100c38c: 1000061e bne r2,zero,100c3a8 + 100c390: 008040b4 movhi r2,258 + 100c394: 10aba104 addi r2,r2,-20860 + 100c398: 10800017 ldw r2,0(r2) + 100c39c: 103ee83a callr r2 + 100c3a0: e0bfff15 stw r2,-4(fp) + 100c3a4: 00000306 br 100c3b4 + 100c3a8: 008040b4 movhi r2,258 + 100c3ac: 10b30404 addi r2,r2,-13296 + 100c3b0: e0bfff15 stw r2,-4(fp) + 100c3b4: e0bfff17 ldw r2,-4(fp) +} + 100c3b8: e037883a mov sp,fp + 100c3bc: dfc00117 ldw ra,4(sp) + 100c3c0: df000017 ldw fp,0(sp) + 100c3c4: dec00204 addi sp,sp,8 + 100c3c8: f800283a ret + +0100c3cc : + * by the alt_dev_null device. It simple discards all data passed to it, and + * indicates that the data has been successfully transmitted. + */ + +static int alt_dev_null_write (alt_fd* fd, const char* ptr, int len) +{ + 100c3cc: defffc04 addi sp,sp,-16 + 100c3d0: df000315 stw fp,12(sp) + 100c3d4: df000304 addi fp,sp,12 + 100c3d8: e13ffd15 stw r4,-12(fp) + 100c3dc: e17ffe15 stw r5,-8(fp) + 100c3e0: e1bfff15 stw r6,-4(fp) + return len; + 100c3e4: e0bfff17 ldw r2,-4(fp) +} + 100c3e8: e037883a mov sp,fp + 100c3ec: df000017 ldw fp,0(sp) + 100c3f0: dec00104 addi sp,sp,4 + 100c3f4: f800283a ret + +0100c3f8 : + +/* + * Routine called on exit. + */ +static ALT_ALWAYS_INLINE void alt_sim_halt(int exit_code) +{ + 100c3f8: defffd04 addi sp,sp,-12 + 100c3fc: df000215 stw fp,8(sp) + 100c400: df000204 addi fp,sp,8 + 100c404: e13fff15 stw r4,-4(fp) + int r2 = exit_code; + 100c408: e0bfff17 ldw r2,-4(fp) + 100c40c: e0bffe15 stw r2,-8(fp) + __asm__ volatile ("\n0:\n\taddi %0,%0, -1\n\tbgt %0,zero,0b" : : "r" (ALT_CPU_FREQ/100) ); /* Delay for >30ms */ + + __asm__ volatile ("break 2" : : "D02"(r2), "D03"(r3) ALT_GMON_DATA ); + +#else /* !DEBUG_STUB */ + if (r2) { + 100c410: e0bffe17 ldw r2,-8(fp) + 100c414: 1005003a cmpeq r2,r2,zero + 100c418: 1000021e bne r2,zero,100c424 + ALT_SIM_FAIL(); + 100c41c: 002af070 cmpltui zero,zero,43969 + 100c420: 00000106 br 100c428 + } else { + ALT_SIM_PASS(); + 100c424: 002af0b0 cmpltui zero,zero,43970 + } +#endif /* DEBUG_STUB */ +} + 100c428: e037883a mov sp,fp + 100c42c: df000017 ldw fp,0(sp) + 100c430: dec00104 addi sp,sp,4 + 100c434: f800283a ret + +0100c438 <_exit>: + * + * ALT_EXIT is mapped onto the _exit() system call in alt_syscall.h + */ + +void ALT_EXIT (int exit_code) +{ + 100c438: defffd04 addi sp,sp,-12 + 100c43c: dfc00215 stw ra,8(sp) + 100c440: df000115 stw fp,4(sp) + 100c444: df000104 addi fp,sp,4 + 100c448: e13fff15 stw r4,-4(fp) + ALT_LOG_PRINT_BOOT("[alt_exit.c] Entering _exit() function.\r\n"); + ALT_LOG_PRINT_BOOT("[alt_exit.c] Exit code from main was %d.\r\n",exit_code); + /* Stop all other threads */ + + ALT_LOG_PRINT_BOOT("[alt_exit.c] Calling ALT_OS_STOP().\r\n"); + ALT_OS_STOP(); + 100c44c: 008040b4 movhi r2,258 + 100c450: 10b31044 addi r2,r2,-13247 + 100c454: 10000005 stb zero,0(r2) + + /* Provide notification to the simulator that we've stopped */ + + ALT_LOG_PRINT_BOOT("[alt_exit.c] Calling ALT_SIM_HALT().\r\n"); + ALT_SIM_HALT(exit_code); + 100c458: e13fff17 ldw r4,-4(fp) + 100c45c: 100c3f80 call 100c3f8 + + /* spin forever, since there's no where to go back to */ + + ALT_LOG_PRINT_BOOT("[alt_exit.c] Spinning forever.\r\n"); + while (1); + 100c460: 003fff06 br 100c460 <_exit+0x28> + +0100c464 : +} + +#else /* !ALT_USE_DIRECT_DRIVERS */ + +int ALT_FSTAT (int file, struct stat *st) +{ + 100c464: defff904 addi sp,sp,-28 + 100c468: dfc00615 stw ra,24(sp) + 100c46c: df000515 stw fp,20(sp) + 100c470: df000504 addi fp,sp,20 + 100c474: e13ffc15 stw r4,-16(fp) + 100c478: e17ffd15 stw r5,-12(fp) + * A common error case is that when the file descriptor was created, the call + * to open() failed resulting in a negative file descriptor. This is trapped + * below so that we don't try and process an invalid file descriptor. + */ + + fd = (file < 0) ? NULL : &alt_fd_list[file]; + 100c47c: e0bffc17 ldw r2,-16(fp) + 100c480: 1004803a cmplt r2,r2,zero + 100c484: 1000081e bne r2,zero,100c4a8 + 100c488: e0bffc17 ldw r2,-16(fp) + 100c48c: 10800324 muli r2,r2,12 + 100c490: 1007883a mov r3,r2 + 100c494: 008040b4 movhi r2,258 + 100c498: 10a69f04 addi r2,r2,-25988 + 100c49c: 1887883a add r3,r3,r2 + 100c4a0: e0ffff15 stw r3,-4(fp) + 100c4a4: 00000106 br 100c4ac + 100c4a8: e03fff15 stw zero,-4(fp) + 100c4ac: e0bfff17 ldw r2,-4(fp) + 100c4b0: e0bffb15 stw r2,-20(fp) + + if (fd) + 100c4b4: e0bffb17 ldw r2,-20(fp) + 100c4b8: 1005003a cmpeq r2,r2,zero + 100c4bc: 1000121e bne r2,zero,100c508 + { + /* Call the drivers fstat() function to fill out the "st" structure. */ + + if (fd->dev->fstat) + 100c4c0: e0bffb17 ldw r2,-20(fp) + 100c4c4: 10800017 ldw r2,0(r2) + 100c4c8: 10800817 ldw r2,32(r2) + 100c4cc: 1005003a cmpeq r2,r2,zero + 100c4d0: 1000081e bne r2,zero,100c4f4 + { + return fd->dev->fstat(fd, st); + 100c4d4: e0bffb17 ldw r2,-20(fp) + 100c4d8: 10800017 ldw r2,0(r2) + 100c4dc: 10800817 ldw r2,32(r2) + 100c4e0: e13ffb17 ldw r4,-20(fp) + 100c4e4: e17ffd17 ldw r5,-12(fp) + 100c4e8: 103ee83a callr r2 + 100c4ec: e0bffe15 stw r2,-8(fp) + 100c4f0: 00000b06 br 100c520 + * device. + */ + + else + { + st->st_mode = _IFCHR; + 100c4f4: e0fffd17 ldw r3,-12(fp) + 100c4f8: 00880004 movi r2,8192 + 100c4fc: 18800115 stw r2,4(r3) + return 0; + 100c500: e03ffe15 stw zero,-8(fp) + 100c504: 00000606 br 100c520 + } + } + else + { + ALT_ERRNO = EBADFD; + 100c508: 100c5380 call 100c538 + 100c50c: 1007883a mov r3,r2 + 100c510: 00801444 movi r2,81 + 100c514: 18800015 stw r2,0(r3) + return -1; + 100c518: 00bfffc4 movi r2,-1 + 100c51c: e0bffe15 stw r2,-8(fp) + 100c520: e0bffe17 ldw r2,-8(fp) + } +} + 100c524: e037883a mov sp,fp + 100c528: dfc00117 ldw ra,4(sp) + 100c52c: df000017 ldw fp,0(sp) + 100c530: dec00204 addi sp,sp,8 + 100c534: f800283a ret + +0100c538 : +#undef errno + +extern int errno; + +static ALT_INLINE int* alt_get_errno(void) +{ + 100c538: defffd04 addi sp,sp,-12 + 100c53c: dfc00215 stw ra,8(sp) + 100c540: df000115 stw fp,4(sp) + 100c544: df000104 addi fp,sp,4 + return ((alt_errno) ? alt_errno() : &errno); + 100c548: 008040b4 movhi r2,258 + 100c54c: 10aba104 addi r2,r2,-20860 + 100c550: 10800017 ldw r2,0(r2) + 100c554: 1005003a cmpeq r2,r2,zero + 100c558: 1000061e bne r2,zero,100c574 + 100c55c: 008040b4 movhi r2,258 + 100c560: 10aba104 addi r2,r2,-20860 + 100c564: 10800017 ldw r2,0(r2) + 100c568: 103ee83a callr r2 + 100c56c: e0bfff15 stw r2,-4(fp) + 100c570: 00000306 br 100c580 + 100c574: 008040b4 movhi r2,258 + 100c578: 10b30404 addi r2,r2,-13296 + 100c57c: e0bfff15 stw r2,-4(fp) + 100c580: e0bfff17 ldw r2,-4(fp) +} + 100c584: e037883a mov sp,fp + 100c588: dfc00117 ldw ra,4(sp) + 100c58c: df000017 ldw fp,0(sp) + 100c590: dec00204 addi sp,sp,8 + 100c594: f800283a ret + +0100c598 : + * + * ALT_GETPID is mapped onto the getpid() system call in alt_syscall.h + */ + +int ALT_GETPID (void) +{ + 100c598: deffff04 addi sp,sp,-4 + 100c59c: df000015 stw fp,0(sp) + 100c5a0: d839883a mov fp,sp + return 0; + 100c5a4: 0005883a mov r2,zero +} + 100c5a8: e037883a mov sp,fp + 100c5ac: df000017 ldw fp,0(sp) + 100c5b0: dec00104 addi sp,sp,4 + 100c5b4: f800283a ret + +0100c5b8 : + * + * ALT_ISATTY is mapped onto the isatty() system call in alt_syscall.h + */ + +int ALT_ISATTY (int file) +{ + 100c5b8: deffeb04 addi sp,sp,-84 + 100c5bc: dfc01415 stw ra,80(sp) + 100c5c0: df001315 stw fp,76(sp) + 100c5c4: df001304 addi fp,sp,76 + 100c5c8: e13ffd15 stw r4,-12(fp) + * A common error case is that when the file descriptor was created, the call + * to open() failed resulting in a negative file descriptor. This is trapped + * below so that we don't try and process an invalid file descriptor. + */ + + fd = (file < 0) ? NULL : &alt_fd_list[file]; + 100c5cc: e0bffd17 ldw r2,-12(fp) + 100c5d0: 1004803a cmplt r2,r2,zero + 100c5d4: 1000081e bne r2,zero,100c5f8 + 100c5d8: e0bffd17 ldw r2,-12(fp) + 100c5dc: 10800324 muli r2,r2,12 + 100c5e0: 1007883a mov r3,r2 + 100c5e4: 008040b4 movhi r2,258 + 100c5e8: 10a69f04 addi r2,r2,-25988 + 100c5ec: 1887883a add r3,r3,r2 + 100c5f0: e0ffff15 stw r3,-4(fp) + 100c5f4: 00000106 br 100c5fc + 100c5f8: e03fff15 stw zero,-4(fp) + 100c5fc: e0bfff17 ldw r2,-4(fp) + 100c600: e0bfed15 stw r2,-76(fp) + + if (fd) + 100c604: e0bfed17 ldw r2,-76(fp) + 100c608: 1005003a cmpeq r2,r2,zero + 100c60c: 10000f1e bne r2,zero,100c64c + /* + * If a device driver does not provide an fstat() function, then it is + * treated as a terminal device by default. + */ + + if (!fd->dev->fstat) + 100c610: e0bfed17 ldw r2,-76(fp) + 100c614: 10800017 ldw r2,0(r2) + 100c618: 10800817 ldw r2,32(r2) + 100c61c: 1004c03a cmpne r2,r2,zero + 100c620: 1000031e bne r2,zero,100c630 + { + return 1; + 100c624: 00800044 movi r2,1 + 100c628: e0bffe15 stw r2,-8(fp) + 100c62c: 00000c06 br 100c660 + * this is called so that the device can identify itself. + */ + + else + { + fstat (file, &stat); + 100c630: e17fee04 addi r5,fp,-72 + 100c634: e13ffd17 ldw r4,-12(fp) + 100c638: 100c4640 call 100c464 + return (stat.st_mode == _IFCHR) ? 1 : 0; + 100c63c: e0bfef17 ldw r2,-68(fp) + 100c640: 10880020 cmpeqi r2,r2,8192 + 100c644: e0bffe15 stw r2,-8(fp) + 100c648: 00000506 br 100c660 + } + } + else + { + ALT_ERRNO = EBADFD; + 100c64c: 100c6780 call 100c678 + 100c650: 1007883a mov r3,r2 + 100c654: 00801444 movi r2,81 + 100c658: 18800015 stw r2,0(r3) + return 0; + 100c65c: e03ffe15 stw zero,-8(fp) + 100c660: e0bffe17 ldw r2,-8(fp) + } +} + 100c664: e037883a mov sp,fp + 100c668: dfc00117 ldw ra,4(sp) + 100c66c: df000017 ldw fp,0(sp) + 100c670: dec00204 addi sp,sp,8 + 100c674: f800283a ret + +0100c678 : +#undef errno + +extern int errno; + +static ALT_INLINE int* alt_get_errno(void) +{ + 100c678: defffd04 addi sp,sp,-12 + 100c67c: dfc00215 stw ra,8(sp) + 100c680: df000115 stw fp,4(sp) + 100c684: df000104 addi fp,sp,4 + return ((alt_errno) ? alt_errno() : &errno); + 100c688: 008040b4 movhi r2,258 + 100c68c: 10aba104 addi r2,r2,-20860 + 100c690: 10800017 ldw r2,0(r2) + 100c694: 1005003a cmpeq r2,r2,zero + 100c698: 1000061e bne r2,zero,100c6b4 + 100c69c: 008040b4 movhi r2,258 + 100c6a0: 10aba104 addi r2,r2,-20860 + 100c6a4: 10800017 ldw r2,0(r2) + 100c6a8: 103ee83a callr r2 + 100c6ac: e0bfff15 stw r2,-4(fp) + 100c6b0: 00000306 br 100c6c0 + 100c6b4: 008040b4 movhi r2,258 + 100c6b8: 10b30404 addi r2,r2,-13296 + 100c6bc: e0bfff15 stw r2,-4(fp) + 100c6c0: e0bfff17 ldw r2,-4(fp) +} + 100c6c4: e037883a mov sp,fp + 100c6c8: dfc00117 ldw ra,4(sp) + 100c6cc: df000017 ldw fp,0(sp) + 100c6d0: dec00204 addi sp,sp,8 + 100c6d4: f800283a ret + +0100c6d8 : + * + * ALT_KILL is mapped onto the kill() system call in alt_syscall.h + */ + +int ALT_KILL (int pid, int sig) +{ + 100c6d8: defffa04 addi sp,sp,-24 + 100c6dc: dfc00515 stw ra,20(sp) + 100c6e0: df000415 stw fp,16(sp) + 100c6e4: df000404 addi fp,sp,16 + 100c6e8: e13ffd15 stw r4,-12(fp) + 100c6ec: e17ffe15 stw r5,-8(fp) + int status = 0; + 100c6f0: e03ffc15 stw zero,-16(fp) + + if (pid <= 0) + 100c6f4: e0bffd17 ldw r2,-12(fp) + 100c6f8: 10800048 cmpgei r2,r2,1 + 100c6fc: 1000301e bne r2,zero,100c7c0 + { + switch (sig) + 100c700: e0bffe17 ldw r2,-8(fp) + 100c704: 10800828 cmpgeui r2,r2,32 + 100c708: 10002a1e bne r2,zero,100c7b4 + 100c70c: e0bffe17 ldw r2,-8(fp) + 100c710: 1085883a add r2,r2,r2 + 100c714: 1087883a add r3,r2,r2 + 100c718: 00804074 movhi r2,257 + 100c71c: 10b1cb04 addi r2,r2,-14548 + 100c720: 1885883a add r2,r3,r2 + 100c724: 10800017 ldw r2,0(r2) + 100c728: 1000683a jmp r2 + 100c72c: 0100c7d4 movui r4,799 + 100c730: 0100c7b4 movhi r4,798 + 100c734: 0100c7b4 movhi r4,798 + 100c738: 0100c7ac andhi r4,zero,798 + 100c73c: 0100c7ac andhi r4,zero,798 + 100c740: 0100c7ac andhi r4,zero,798 + 100c744: 0100c7ac andhi r4,zero,798 + 100c748: 0100c7b4 movhi r4,798 + 100c74c: 0100c7ac andhi r4,zero,798 + 100c750: 0100c7ac andhi r4,zero,798 + 100c754: 0100c7ac andhi r4,zero,798 + 100c758: 0100c7ac andhi r4,zero,798 + 100c75c: 0100c7ac andhi r4,zero,798 + 100c760: 0100c7ac andhi r4,zero,798 + 100c764: 0100c7ac andhi r4,zero,798 + 100c768: 0100c7ac andhi r4,zero,798 + 100c76c: 0100c7d4 movui r4,799 + 100c770: 0100c7b4 movhi r4,798 + 100c774: 0100c7b4 movhi r4,798 + 100c778: 0100c7b4 movhi r4,798 + 100c77c: 0100c7d4 movui r4,799 + 100c780: 0100c7b4 movhi r4,798 + 100c784: 0100c7b4 movhi r4,798 + 100c788: 0100c7ac andhi r4,zero,798 + 100c78c: 0100c7ac andhi r4,zero,798 + 100c790: 0100c7ac andhi r4,zero,798 + 100c794: 0100c7ac andhi r4,zero,798 + 100c798: 0100c7ac andhi r4,zero,798 + 100c79c: 0100c7b4 movhi r4,798 + 100c7a0: 0100c7b4 movhi r4,798 + 100c7a4: 0100c7ac andhi r4,zero,798 + 100c7a8: 0100c7ac andhi r4,zero,798 + * The Posix standard defines the default behaviour for all these signals + * as being eqivalent to a call to _exit(). No mechanism is provided to + * change this behaviour. + */ + + _exit(0); + 100c7ac: 0009883a mov r4,zero + 100c7b0: 100c4380 call 100c438 <_exit> + break; + default: + + /* Tried to send an unsupported signal */ + + status = EINVAL; + 100c7b4: 00800584 movi r2,22 + 100c7b8: e0bffc15 stw r2,-16(fp) + 100c7bc: 00000506 br 100c7d4 + } + } + + else if (pid > 0) + 100c7c0: e0bffd17 ldw r2,-12(fp) + 100c7c4: 10800050 cmplti r2,r2,1 + 100c7c8: 1000021e bne r2,zero,100c7d4 + { + /* Attempted to signal a non-existant process */ + + status = ESRCH; + 100c7cc: 008000c4 movi r2,3 + 100c7d0: e0bffc15 stw r2,-16(fp) + } + + if (status) + 100c7d4: e0bffc17 ldw r2,-16(fp) + 100c7d8: 1005003a cmpeq r2,r2,zero + 100c7dc: 1000071e bne r2,zero,100c7fc + { + ALT_ERRNO = status; + 100c7e0: 100c8180 call 100c818 + 100c7e4: 1007883a mov r3,r2 + 100c7e8: e0bffc17 ldw r2,-16(fp) + 100c7ec: 18800015 stw r2,0(r3) + return -1; + 100c7f0: 00bfffc4 movi r2,-1 + 100c7f4: e0bfff15 stw r2,-4(fp) + 100c7f8: 00000106 br 100c800 + } + + return 0; + 100c7fc: e03fff15 stw zero,-4(fp) + 100c800: e0bfff17 ldw r2,-4(fp) +} + 100c804: e037883a mov sp,fp + 100c808: dfc00117 ldw ra,4(sp) + 100c80c: df000017 ldw fp,0(sp) + 100c810: dec00204 addi sp,sp,8 + 100c814: f800283a ret + +0100c818 : +#undef errno + +extern int errno; + +static ALT_INLINE int* alt_get_errno(void) +{ + 100c818: defffd04 addi sp,sp,-12 + 100c81c: dfc00215 stw ra,8(sp) + 100c820: df000115 stw fp,4(sp) + 100c824: df000104 addi fp,sp,4 + return ((alt_errno) ? alt_errno() : &errno); + 100c828: 008040b4 movhi r2,258 + 100c82c: 10aba104 addi r2,r2,-20860 + 100c830: 10800017 ldw r2,0(r2) + 100c834: 1005003a cmpeq r2,r2,zero + 100c838: 1000061e bne r2,zero,100c854 + 100c83c: 008040b4 movhi r2,258 + 100c840: 10aba104 addi r2,r2,-20860 + 100c844: 10800017 ldw r2,0(r2) + 100c848: 103ee83a callr r2 + 100c84c: e0bfff15 stw r2,-4(fp) + 100c850: 00000306 br 100c860 + 100c854: 008040b4 movhi r2,258 + 100c858: 10b30404 addi r2,r2,-13296 + 100c85c: e0bfff15 stw r2,-4(fp) + 100c860: e0bfff17 ldw r2,-4(fp) +} + 100c864: e037883a mov sp,fp + 100c868: dfc00117 ldw ra,4(sp) + 100c86c: df000017 ldw fp,0(sp) + 100c870: dec00204 addi sp,sp,8 + 100c874: f800283a ret + +0100c878 : + * there is no bootloader, so this application is responsible for loading to + * RAM any sections that are required. + */ + +void alt_load (void) +{ + 100c878: defffe04 addi sp,sp,-8 + 100c87c: dfc00115 stw ra,4(sp) + 100c880: df000015 stw fp,0(sp) + 100c884: d839883a mov fp,sp + /* + * Copy the .rwdata section. + */ + + alt_load_section (&__flash_rwdata_start, + 100c888: 010040b4 movhi r4,258 + 100c88c: 212bc504 addi r4,r4,-20716 + 100c890: 014040b4 movhi r5,258 + 100c894: 29649004 addi r5,r5,-28096 + 100c898: 018040b4 movhi r6,258 + 100c89c: 31abc504 addi r6,r6,-20716 + 100c8a0: 100c8f80 call 100c8f8 + + /* + * Copy the exception handler. + */ + + alt_load_section (&__flash_exceptions_start, + 100c8a4: 01004034 movhi r4,256 + 100c8a8: 21000804 addi r4,r4,32 + 100c8ac: 01404034 movhi r5,256 + 100c8b0: 29400804 addi r5,r5,32 + 100c8b4: 01804034 movhi r6,256 + 100c8b8: 31807004 addi r6,r6,448 + 100c8bc: 100c8f80 call 100c8f8 + + /* + * Copy the .rodata section. + */ + + alt_load_section (&__flash_rodata_start, + 100c8c0: 010040b4 movhi r4,258 + 100c8c4: 2122f504 addi r4,r4,-29740 + 100c8c8: 014040b4 movhi r5,258 + 100c8cc: 2962f504 addi r5,r5,-29740 + 100c8d0: 018040b4 movhi r6,258 + 100c8d4: 31a49004 addi r6,r6,-28096 + 100c8d8: 100c8f80 call 100c8f8 + + /* + * Now ensure that the caches are in synch. + */ + + alt_dcache_flush_all(); + 100c8dc: 10175c00 call 10175c0 + alt_icache_flush_all(); + 100c8e0: 10178740 call 1017874 +} + 100c8e4: e037883a mov sp,fp + 100c8e8: dfc00117 ldw ra,4(sp) + 100c8ec: df000017 ldw fp,0(sp) + 100c8f0: dec00204 addi sp,sp,8 + 100c8f4: f800283a ret + +0100c8f8 : + */ + +static void ALT_INLINE alt_load_section (alt_u32* from, + alt_u32* to, + alt_u32* end) +{ + 100c8f8: defffc04 addi sp,sp,-16 + 100c8fc: df000315 stw fp,12(sp) + 100c900: df000304 addi fp,sp,12 + 100c904: e13ffd15 stw r4,-12(fp) + 100c908: e17ffe15 stw r5,-8(fp) + 100c90c: e1bfff15 stw r6,-4(fp) + if (to != from) + 100c910: e0fffe17 ldw r3,-8(fp) + 100c914: e0bffd17 ldw r2,-12(fp) + 100c918: 18800e26 beq r3,r2,100c954 + { + while( to != end ) + 100c91c: 00000a06 br 100c948 + { + *to++ = *from++; + 100c920: e0bffd17 ldw r2,-12(fp) + 100c924: 10c00017 ldw r3,0(r2) + 100c928: e0bffe17 ldw r2,-8(fp) + 100c92c: 10c00015 stw r3,0(r2) + 100c930: e0bffe17 ldw r2,-8(fp) + 100c934: 10800104 addi r2,r2,4 + 100c938: e0bffe15 stw r2,-8(fp) + 100c93c: e0bffd17 ldw r2,-12(fp) + 100c940: 10800104 addi r2,r2,4 + 100c944: e0bffd15 stw r2,-12(fp) + alt_u32* to, + alt_u32* end) +{ + if (to != from) + { + while( to != end ) + 100c948: e0fffe17 ldw r3,-8(fp) + 100c94c: e0bfff17 ldw r2,-4(fp) + 100c950: 18bff31e bne r3,r2,100c920 + { + *to++ = *from++; + } + } +} + 100c954: e037883a mov sp,fp + 100c958: df000017 ldw fp,0(sp) + 100c95c: dec00104 addi sp,sp,4 + 100c960: f800283a ret + +0100c964 : + * ALT_LSEEK is mapped onto the lseek() system call in alt_syscall.h + * + */ + +off_t ALT_LSEEK (int file, off_t ptr, int dir) +{ + 100c964: defff804 addi sp,sp,-32 + 100c968: dfc00715 stw ra,28(sp) + 100c96c: df000615 stw fp,24(sp) + 100c970: df000604 addi fp,sp,24 + 100c974: e13ffc15 stw r4,-16(fp) + 100c978: e17ffd15 stw r5,-12(fp) + 100c97c: e1bffe15 stw r6,-8(fp) + alt_fd* fd; + off_t rc = 0; + 100c980: e03ffa15 stw zero,-24(fp) + * A common error case is that when the file descriptor was created, the call + * to open() failed resulting in a negative file descriptor. This is trapped + * below so that we don't try and process an invalid file descriptor. + */ + + fd = (file < 0) ? NULL : &alt_fd_list[file]; + 100c984: e0bffc17 ldw r2,-16(fp) + 100c988: 1004803a cmplt r2,r2,zero + 100c98c: 1000081e bne r2,zero,100c9b0 + 100c990: e0bffc17 ldw r2,-16(fp) + 100c994: 10800324 muli r2,r2,12 + 100c998: 1007883a mov r3,r2 + 100c99c: 008040b4 movhi r2,258 + 100c9a0: 10a69f04 addi r2,r2,-25988 + 100c9a4: 1887883a add r3,r3,r2 + 100c9a8: e0ffff15 stw r3,-4(fp) + 100c9ac: 00000106 br 100c9b4 + 100c9b0: e03fff15 stw zero,-4(fp) + 100c9b4: e0bfff17 ldw r2,-4(fp) + 100c9b8: e0bffb15 stw r2,-20(fp) + + if (fd) + 100c9bc: e0bffb17 ldw r2,-20(fp) + 100c9c0: 1005003a cmpeq r2,r2,zero + 100c9c4: 1000111e bne r2,zero,100ca0c + /* + * If the device driver provides an implementation of the lseek() function, + * then call that to process the request. + */ + + if (fd->dev->lseek) + 100c9c8: e0bffb17 ldw r2,-20(fp) + 100c9cc: 10800017 ldw r2,0(r2) + 100c9d0: 10800717 ldw r2,28(r2) + 100c9d4: 1005003a cmpeq r2,r2,zero + 100c9d8: 1000091e bne r2,zero,100ca00 + { + rc = fd->dev->lseek(fd, ptr, dir); + 100c9dc: e0bffb17 ldw r2,-20(fp) + 100c9e0: 10800017 ldw r2,0(r2) + 100c9e4: 10800717 ldw r2,28(r2) + 100c9e8: e13ffb17 ldw r4,-20(fp) + 100c9ec: e17ffd17 ldw r5,-12(fp) + 100c9f0: e1bffe17 ldw r6,-8(fp) + 100c9f4: 103ee83a callr r2 + 100c9f8: e0bffa15 stw r2,-24(fp) + 100c9fc: 00000506 br 100ca14 + * Otherwise return an error. + */ + + else + { + rc = -ENOTSUP; + 100ca00: 00bfde84 movi r2,-134 + 100ca04: e0bffa15 stw r2,-24(fp) + 100ca08: 00000206 br 100ca14 + } + } + else + { + rc = -EBADFD; + 100ca0c: 00bfebc4 movi r2,-81 + 100ca10: e0bffa15 stw r2,-24(fp) + } + + if (rc < 0) + 100ca14: e0bffa17 ldw r2,-24(fp) + 100ca18: 1004403a cmpge r2,r2,zero + 100ca1c: 1000071e bne r2,zero,100ca3c + { + ALT_ERRNO = -rc; + 100ca20: 100ca540 call 100ca54 + 100ca24: 1007883a mov r3,r2 + 100ca28: e0bffa17 ldw r2,-24(fp) + 100ca2c: 0085c83a sub r2,zero,r2 + 100ca30: 18800015 stw r2,0(r3) + rc = -1; + 100ca34: 00bfffc4 movi r2,-1 + 100ca38: e0bffa15 stw r2,-24(fp) + } + + return rc; + 100ca3c: e0bffa17 ldw r2,-24(fp) +} + 100ca40: e037883a mov sp,fp + 100ca44: dfc00117 ldw ra,4(sp) + 100ca48: df000017 ldw fp,0(sp) + 100ca4c: dec00204 addi sp,sp,8 + 100ca50: f800283a ret + +0100ca54 : +#undef errno + +extern int errno; + +static ALT_INLINE int* alt_get_errno(void) +{ + 100ca54: defffd04 addi sp,sp,-12 + 100ca58: dfc00215 stw ra,8(sp) + 100ca5c: df000115 stw fp,4(sp) + 100ca60: df000104 addi fp,sp,4 + return ((alt_errno) ? alt_errno() : &errno); + 100ca64: 008040b4 movhi r2,258 + 100ca68: 10aba104 addi r2,r2,-20860 + 100ca6c: 10800017 ldw r2,0(r2) + 100ca70: 1005003a cmpeq r2,r2,zero + 100ca74: 1000061e bne r2,zero,100ca90 + 100ca78: 008040b4 movhi r2,258 + 100ca7c: 10aba104 addi r2,r2,-20860 + 100ca80: 10800017 ldw r2,0(r2) + 100ca84: 103ee83a callr r2 + 100ca88: e0bfff15 stw r2,-4(fp) + 100ca8c: 00000306 br 100ca9c + 100ca90: 008040b4 movhi r2,258 + 100ca94: 10b30404 addi r2,r2,-13296 + 100ca98: e0bfff15 stw r2,-4(fp) + 100ca9c: e0bfff17 ldw r2,-4(fp) +} + 100caa0: e037883a mov sp,fp + 100caa4: dfc00117 ldw ra,4(sp) + 100caa8: df000017 ldw fp,0(sp) + 100caac: dec00204 addi sp,sp,8 + 100cab0: f800283a ret + +0100cab4 : + * devices/filesystems/components in the system; and call the entry point for + * the users application, i.e. main(). + */ + +void alt_main (void) +{ + 100cab4: defffb04 addi sp,sp,-20 + 100cab8: dfc00415 stw ra,16(sp) + 100cabc: df000315 stw fp,12(sp) + 100cac0: df000304 addi fp,sp,12 +#endif + + /* ALT LOG - please see HAL/sys/alt_log_printf.h for details */ + ALT_LOG_PRINT_BOOT("[alt_main.c] Entering alt_main, calling alt_irq_init.\r\n"); + /* Initialize the interrupt controller. */ + alt_irq_init (NULL); + 100cac4: 0009883a mov r4,zero + 100cac8: 10155440 call 1015544 + + /* Initialize the operating system */ + ALT_LOG_PRINT_BOOT("[alt_main.c] Done alt_irq_init, calling alt_os_init.\r\n"); + ALT_OS_INIT(); + 100cacc: 100dba00 call 100dba0 + 100cad0: 01000044 movi r4,1 + 100cad4: 1012a640 call 1012a64 + 100cad8: 1007883a mov r3,r2 + 100cadc: 008040b4 movhi r2,258 + 100cae0: 10b30d04 addi r2,r2,-13260 + 100cae4: 10c00015 stw r3,0(r2) + 100cae8: 01000044 movi r4,1 + 100caec: 1012a640 call 1012a64 + 100caf0: 1007883a mov r3,r2 + 100caf4: 008040b4 movhi r2,258 + 100caf8: 10b30f04 addi r2,r2,-13252 + 100cafc: 10c00015 stw r3,0(r2) + 100cb00: 008040b4 movhi r2,258 + 100cb04: 10b30804 addi r2,r2,-13280 + 100cb08: e0bffd15 stw r2,-12(fp) + 100cb0c: 00800044 movi r2,1 + 100cb10: e0bffe0d sth r2,-8(fp) + */ + +static ALT_INLINE int ALT_ALWAYS_INLINE alt_sem_create (OS_EVENT** sem, + INT16U value) +{ + *sem = OSSemCreate (value); + 100cb14: e13ffe0b ldhu r4,-8(fp) + 100cb18: 1012a640 call 1012a64 + 100cb1c: 1007883a mov r3,r2 + 100cb20: e0bffd17 ldw r2,-12(fp) + 100cb24: 10c00015 stw r3,0(r2) + ALT_LOG_PRINT_BOOT("[alt_main.c] Done OS Init, calling alt_sem_create.\r\n"); + ALT_SEM_CREATE (&alt_fd_list_lock, 1); + + /* Initialize the device drivers/software components. */ + ALT_LOG_PRINT_BOOT("[alt_main.c] Calling alt_sys_init.\r\n"); + alt_sys_init(); + 100cb28: 10155780 call 1015578 + * devices be present (not equal to /dev/null) and if direct drivers + * aren't being used. + */ + + ALT_LOG_PRINT_BOOT("[alt_main.c] Redirecting IO.\r\n"); + alt_io_redirect(ALT_STDOUT, ALT_STDIN, ALT_STDERR); + 100cb2c: 010040b4 movhi r4,258 + 100cb30: 21243104 addi r4,r4,-28476 + 100cb34: 014040b4 movhi r5,258 + 100cb38: 29643104 addi r5,r5,-28476 + 100cb3c: 018040b4 movhi r6,258 + 100cb40: 31a43104 addi r6,r6,-28476 + 100cb44: 10179680 call 1017968 + /* + * Call the C++ constructors + */ + + ALT_LOG_PRINT_BOOT("[alt_main.c] Calling C++ constructors.\r\n"); + _do_ctors (); + 100cb48: 10177180 call 1017718 <_do_ctors> + * redefined as _exit()). This is in the interest of reducing code footprint, + * in that the atexit() overhead is removed when it's not needed. + */ + + ALT_LOG_PRINT_BOOT("[alt_main.c] Calling atexit.\r\n"); + atexit (_do_dtors); + 100cb4c: 01004074 movhi r4,257 + 100cb50: 211ddf04 addi r4,r4,30588 + 100cb54: 10187b80 call 10187b8 + ALT_LOG_PRINT_BOOT("[alt_main.c] Calling main.\r\n"); + +#ifdef ALT_NO_EXIT + main (alt_argc, alt_argv, alt_envp); +#else + result = main (alt_argc, alt_argv, alt_envp); + 100cb58: d1277c17 ldw r4,-25104(gp) + 100cb5c: d1677d17 ldw r5,-25100(gp) + 100cb60: d1a77e17 ldw r6,-25096(gp) + 100cb64: 10007dc0 call 10007dc
+ 100cb68: e0bfff15 stw r2,-4(fp) + close(STDOUT_FILENO); + 100cb6c: 01000044 movi r4,1 + 100cb70: 100c2700 call 100c270 + exit (result); + 100cb74: e13fff17 ldw r4,-4(fp) + 100cb78: 10187cc0 call 10187cc + +0100cb7c : +} + +#else /* !ALT_USE_DIRECT_DRIVERS */ + +int ALT_READ (int file, void *ptr, size_t len) +{ + 100cb7c: defff704 addi sp,sp,-36 + 100cb80: dfc00815 stw ra,32(sp) + 100cb84: df000715 stw fp,28(sp) + 100cb88: df000704 addi fp,sp,28 + 100cb8c: e13ffb15 stw r4,-20(fp) + 100cb90: e17ffc15 stw r5,-16(fp) + 100cb94: e1bffd15 stw r6,-12(fp) + * A common error case is that when the file descriptor was created, the call + * to open() failed resulting in a negative file descriptor. This is trapped + * below so that we don't try and process an invalid file descriptor. + */ + + fd = (file < 0) ? NULL : &alt_fd_list[file]; + 100cb98: e0bffb17 ldw r2,-20(fp) + 100cb9c: 1004803a cmplt r2,r2,zero + 100cba0: 1000081e bne r2,zero,100cbc4 + 100cba4: e0bffb17 ldw r2,-20(fp) + 100cba8: 10800324 muli r2,r2,12 + 100cbac: 1007883a mov r3,r2 + 100cbb0: 008040b4 movhi r2,258 + 100cbb4: 10a69f04 addi r2,r2,-25988 + 100cbb8: 1887883a add r3,r3,r2 + 100cbbc: e0ffff15 stw r3,-4(fp) + 100cbc0: 00000106 br 100cbc8 + 100cbc4: e03fff15 stw zero,-4(fp) + 100cbc8: e0bfff17 ldw r2,-4(fp) + 100cbcc: e0bffa15 stw r2,-24(fp) + + if (fd) + 100cbd0: e0bffa17 ldw r2,-24(fp) + 100cbd4: 1005003a cmpeq r2,r2,zero + 100cbd8: 1000241e bne r2,zero,100cc6c + * If the file has not been opened with read access, or if the driver does + * not provide an implementation of read(), generate an error. Otherwise + * call the drivers read() function to process the request. + */ + + if (((fd->fd_flags & O_ACCMODE) != O_WRONLY) && + 100cbdc: e0bffa17 ldw r2,-24(fp) + 100cbe0: 10800217 ldw r2,8(r2) + 100cbe4: 108000cc andi r2,r2,3 + 100cbe8: 10800060 cmpeqi r2,r2,1 + 100cbec: 10001a1e bne r2,zero,100cc58 + 100cbf0: e0bffa17 ldw r2,-24(fp) + 100cbf4: 10800017 ldw r2,0(r2) + 100cbf8: 10800517 ldw r2,20(r2) + 100cbfc: 1005003a cmpeq r2,r2,zero + 100cc00: 1000151e bne r2,zero,100cc58 + (fd->dev->read)) + { + if ((rval = fd->dev->read(fd, ptr, len)) < 0) + 100cc04: e0bffa17 ldw r2,-24(fp) + 100cc08: 10800017 ldw r2,0(r2) + 100cc0c: 10800517 ldw r2,20(r2) + 100cc10: e17ffc17 ldw r5,-16(fp) + 100cc14: e1bffd17 ldw r6,-12(fp) + 100cc18: e13ffa17 ldw r4,-24(fp) + 100cc1c: 103ee83a callr r2 + 100cc20: e0bff915 stw r2,-28(fp) + 100cc24: e0bff917 ldw r2,-28(fp) + 100cc28: 1004403a cmpge r2,r2,zero + 100cc2c: 1000071e bne r2,zero,100cc4c + { + ALT_ERRNO = -rval; + 100cc30: 100cc9c0 call 100cc9c + 100cc34: e0fff917 ldw r3,-28(fp) + 100cc38: 00c7c83a sub r3,zero,r3 + 100cc3c: 10c00015 stw r3,0(r2) + return -1; + 100cc40: 00bfffc4 movi r2,-1 + 100cc44: e0bffe15 stw r2,-8(fp) + 100cc48: 00000e06 br 100cc84 + } + return rval; + 100cc4c: e0bff917 ldw r2,-28(fp) + 100cc50: e0bffe15 stw r2,-8(fp) + 100cc54: 00000b06 br 100cc84 + } + else + { + ALT_ERRNO = EACCES; + 100cc58: 100cc9c0 call 100cc9c + 100cc5c: 1007883a mov r3,r2 + 100cc60: 00800344 movi r2,13 + 100cc64: 18800015 stw r2,0(r3) + 100cc68: 00000406 br 100cc7c + } + } + else + { + ALT_ERRNO = EBADFD; + 100cc6c: 100cc9c0 call 100cc9c + 100cc70: 1007883a mov r3,r2 + 100cc74: 00801444 movi r2,81 + 100cc78: 18800015 stw r2,0(r3) + } + return -1; + 100cc7c: 00bfffc4 movi r2,-1 + 100cc80: e0bffe15 stw r2,-8(fp) + 100cc84: e0bffe17 ldw r2,-8(fp) +} + 100cc88: e037883a mov sp,fp + 100cc8c: dfc00117 ldw ra,4(sp) + 100cc90: df000017 ldw fp,0(sp) + 100cc94: dec00204 addi sp,sp,8 + 100cc98: f800283a ret + +0100cc9c : +#undef errno + +extern int errno; + +static ALT_INLINE int* alt_get_errno(void) +{ + 100cc9c: defffd04 addi sp,sp,-12 + 100cca0: dfc00215 stw ra,8(sp) + 100cca4: df000115 stw fp,4(sp) + 100cca8: df000104 addi fp,sp,4 + return ((alt_errno) ? alt_errno() : &errno); + 100ccac: 008040b4 movhi r2,258 + 100ccb0: 10aba104 addi r2,r2,-20860 + 100ccb4: 10800017 ldw r2,0(r2) + 100ccb8: 1005003a cmpeq r2,r2,zero + 100ccbc: 1000061e bne r2,zero,100ccd8 + 100ccc0: 008040b4 movhi r2,258 + 100ccc4: 10aba104 addi r2,r2,-20860 + 100ccc8: 10800017 ldw r2,0(r2) + 100cccc: 103ee83a callr r2 + 100ccd0: e0bfff15 stw r2,-4(fp) + 100ccd4: 00000306 br 100cce4 + 100ccd8: 008040b4 movhi r2,258 + 100ccdc: 10b30404 addi r2,r2,-13296 + 100cce0: e0bfff15 stw r2,-4(fp) + 100cce4: e0bfff17 ldw r2,-4(fp) +} + 100cce8: e037883a mov sp,fp + 100ccec: dfc00117 ldw ra,4(sp) + 100ccf0: df000017 ldw fp,0(sp) + 100ccf4: dec00204 addi sp,sp,8 + 100ccf8: f800283a ret + +0100ccfc : + * File descriptors correcponding to standard in, standard out and standard + * error cannont be released backed to the pool. They are always reserved. + */ + +void alt_release_fd (int fd) +{ + 100ccfc: defffe04 addi sp,sp,-8 + 100cd00: df000115 stw fp,4(sp) + 100cd04: df000104 addi fp,sp,4 + 100cd08: e13fff15 stw r4,-4(fp) + if (fd > 2) + 100cd0c: e0bfff17 ldw r2,-4(fp) + 100cd10: 108000d0 cmplti r2,r2,3 + 100cd14: 10000d1e bne r2,zero,100cd4c + { + alt_fd_list[fd].fd_flags = 0; + 100cd18: e0bfff17 ldw r2,-4(fp) + 100cd1c: 00c040b4 movhi r3,258 + 100cd20: 18e69f04 addi r3,r3,-25988 + 100cd24: 10800324 muli r2,r2,12 + 100cd28: 10c5883a add r2,r2,r3 + 100cd2c: 10800204 addi r2,r2,8 + 100cd30: 10000015 stw zero,0(r2) + alt_fd_list[fd].dev = 0; + 100cd34: e0bfff17 ldw r2,-4(fp) + 100cd38: 00c040b4 movhi r3,258 + 100cd3c: 18e69f04 addi r3,r3,-25988 + 100cd40: 10800324 muli r2,r2,12 + 100cd44: 10c5883a add r2,r2,r3 + 100cd48: 10000015 stw zero,0(r2) + } +} + 100cd4c: e037883a mov sp,fp + 100cd50: df000017 ldw fp,0(sp) + 100cd54: dec00104 addi sp,sp,4 + 100cd58: f800283a ret + +0100cd5c : +#endif + +caddr_t ALT_SBRK (int incr) __attribute__ ((no_instrument_function )); + +caddr_t ALT_SBRK (int incr) +{ + 100cd5c: defff804 addi sp,sp,-32 + 100cd60: df000715 stw fp,28(sp) + 100cd64: df000704 addi fp,sp,28 + 100cd68: e13ffe15 stw r4,-8(fp) +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 100cd6c: 0005303a rdctl r2,status + 100cd70: e0bffb15 stw r2,-20(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 100cd74: e0fffb17 ldw r3,-20(fp) + 100cd78: 00bfff84 movi r2,-2 + 100cd7c: 1884703a and r2,r3,r2 + 100cd80: 1001703a wrctl status,r2 + + return context; + 100cd84: e0bffb17 ldw r2,-20(fp) + alt_irq_context context; + char *prev_heap_end; + + context = alt_irq_disable_all(); + 100cd88: e0bffd15 stw r2,-12(fp) + + /* Always return data aligned on a word boundary */ + heap_end = (char *)(((unsigned int)heap_end + 3) & ~3); + 100cd8c: d0a01517 ldw r2,-32684(gp) + 100cd90: 10c000c4 addi r3,r2,3 + 100cd94: 00bfff04 movi r2,-4 + 100cd98: 1884703a and r2,r3,r2 + 100cd9c: d0a01515 stw r2,-32684(gp) + if (((heap_end + incr) - __alt_heap_start) > ALT_MAX_HEAP_BYTES) { + alt_irq_enable_all(context); + return (caddr_t)-1; + } +#else + if ((heap_end + incr) > __alt_heap_limit) { + 100cda0: d0e01517 ldw r3,-32684(gp) + 100cda4: e0bffe17 ldw r2,-8(fp) + 100cda8: 1887883a add r3,r3,r2 + 100cdac: 00808034 movhi r2,512 + 100cdb0: 10800004 addi r2,r2,0 + 100cdb4: 10c0072e bgeu r2,r3,100cdd4 + 100cdb8: e0bffd17 ldw r2,-12(fp) + 100cdbc: e0bffa15 stw r2,-24(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 100cdc0: e0bffa17 ldw r2,-24(fp) + 100cdc4: 1001703a wrctl status,r2 + alt_irq_enable_all(context); + return (caddr_t)-1; + 100cdc8: 00bfffc4 movi r2,-1 + 100cdcc: e0bfff15 stw r2,-4(fp) + 100cdd0: 00000c06 br 100ce04 + } +#endif + + prev_heap_end = heap_end; + 100cdd4: d0a01517 ldw r2,-32684(gp) + 100cdd8: e0bffc15 stw r2,-16(fp) + heap_end += incr; + 100cddc: d0e01517 ldw r3,-32684(gp) + 100cde0: e0bffe17 ldw r2,-8(fp) + 100cde4: 1885883a add r2,r3,r2 + 100cde8: d0a01515 stw r2,-32684(gp) + 100cdec: e0bffd17 ldw r2,-12(fp) + 100cdf0: e0bff915 stw r2,-28(fp) + 100cdf4: e0bff917 ldw r2,-28(fp) + 100cdf8: 1001703a wrctl status,r2 + +#endif + + alt_irq_enable_all(context); + + return (caddr_t) prev_heap_end; + 100cdfc: e0bffc17 ldw r2,-16(fp) + 100ce00: e0bfff15 stw r2,-4(fp) + 100ce04: e0bfff17 ldw r2,-4(fp) +} + 100ce08: e037883a mov sp,fp + 100ce0c: df000017 ldw fp,0(sp) + 100ce10: dec00104 addi sp,sp,4 + 100ce14: f800283a ret + +0100ce18 : +} + +#else /* !ALT_USE_DIRECT_DRIVERS */ + +int ALT_WRITE (int file, const void *ptr, size_t len) +{ + 100ce18: defff704 addi sp,sp,-36 + 100ce1c: dfc00815 stw ra,32(sp) + 100ce20: df000715 stw fp,28(sp) + 100ce24: df000704 addi fp,sp,28 + 100ce28: e13ffb15 stw r4,-20(fp) + 100ce2c: e17ffc15 stw r5,-16(fp) + 100ce30: e1bffd15 stw r6,-12(fp) + * A common error case is that when the file descriptor was created, the call + * to open() failed resulting in a negative file descriptor. This is trapped + * below so that we don't try and process an invalid file descriptor. + */ + + fd = (file < 0) ? NULL : &alt_fd_list[file]; + 100ce34: e0bffb17 ldw r2,-20(fp) + 100ce38: 1004803a cmplt r2,r2,zero + 100ce3c: 1000081e bne r2,zero,100ce60 + 100ce40: e0bffb17 ldw r2,-20(fp) + 100ce44: 10800324 muli r2,r2,12 + 100ce48: 1007883a mov r3,r2 + 100ce4c: 008040b4 movhi r2,258 + 100ce50: 10a69f04 addi r2,r2,-25988 + 100ce54: 1887883a add r3,r3,r2 + 100ce58: e0ffff15 stw r3,-4(fp) + 100ce5c: 00000106 br 100ce64 + 100ce60: e03fff15 stw zero,-4(fp) + 100ce64: e0bfff17 ldw r2,-4(fp) + 100ce68: e0bffa15 stw r2,-24(fp) + + if (fd) + 100ce6c: e0bffa17 ldw r2,-24(fp) + 100ce70: 1005003a cmpeq r2,r2,zero + 100ce74: 1000241e bne r2,zero,100cf08 + * If the file has not been opened with write access, or if the driver does + * not provide an implementation of write(), generate an error. Otherwise + * call the drivers write() function to process the request. + */ + + if (((fd->fd_flags & O_ACCMODE) != O_RDONLY) && fd->dev->write) + 100ce78: e0bffa17 ldw r2,-24(fp) + 100ce7c: 10800217 ldw r2,8(r2) + 100ce80: 108000cc andi r2,r2,3 + 100ce84: 1005003a cmpeq r2,r2,zero + 100ce88: 10001a1e bne r2,zero,100cef4 + 100ce8c: e0bffa17 ldw r2,-24(fp) + 100ce90: 10800017 ldw r2,0(r2) + 100ce94: 10800617 ldw r2,24(r2) + 100ce98: 1005003a cmpeq r2,r2,zero + 100ce9c: 1000151e bne r2,zero,100cef4 + { + + /* ALT_LOG - see altera_hal/HAL/inc/sys/alt_log_printf.h */ + ALT_LOG_WRITE_FUNCTION(ptr,len); + + if ((rval = fd->dev->write(fd, ptr, len)) < 0) + 100cea0: e0bffa17 ldw r2,-24(fp) + 100cea4: 10800017 ldw r2,0(r2) + 100cea8: 10800617 ldw r2,24(r2) + 100ceac: e17ffc17 ldw r5,-16(fp) + 100ceb0: e1bffd17 ldw r6,-12(fp) + 100ceb4: e13ffa17 ldw r4,-24(fp) + 100ceb8: 103ee83a callr r2 + 100cebc: e0bff915 stw r2,-28(fp) + 100cec0: e0bff917 ldw r2,-28(fp) + 100cec4: 1004403a cmpge r2,r2,zero + 100cec8: 1000071e bne r2,zero,100cee8 + { + ALT_ERRNO = -rval; + 100cecc: 100cf380 call 100cf38 + 100ced0: e0fff917 ldw r3,-28(fp) + 100ced4: 00c7c83a sub r3,zero,r3 + 100ced8: 10c00015 stw r3,0(r2) + return -1; + 100cedc: 00bfffc4 movi r2,-1 + 100cee0: e0bffe15 stw r2,-8(fp) + 100cee4: 00000e06 br 100cf20 + } + return rval; + 100cee8: e0bff917 ldw r2,-28(fp) + 100ceec: e0bffe15 stw r2,-8(fp) + 100cef0: 00000b06 br 100cf20 + } + else + { + ALT_ERRNO = EACCES; + 100cef4: 100cf380 call 100cf38 + 100cef8: 1007883a mov r3,r2 + 100cefc: 00800344 movi r2,13 + 100cf00: 18800015 stw r2,0(r3) + 100cf04: 00000406 br 100cf18 + } + } + else + { + ALT_ERRNO = EBADFD; + 100cf08: 100cf380 call 100cf38 + 100cf0c: 1007883a mov r3,r2 + 100cf10: 00801444 movi r2,81 + 100cf14: 18800015 stw r2,0(r3) + } + return -1; + 100cf18: 00bfffc4 movi r2,-1 + 100cf1c: e0bffe15 stw r2,-8(fp) + 100cf20: e0bffe17 ldw r2,-8(fp) +} + 100cf24: e037883a mov sp,fp + 100cf28: dfc00117 ldw ra,4(sp) + 100cf2c: df000017 ldw fp,0(sp) + 100cf30: dec00204 addi sp,sp,8 + 100cf34: f800283a ret + +0100cf38 : +#undef errno + +extern int errno; + +static ALT_INLINE int* alt_get_errno(void) +{ + 100cf38: defffd04 addi sp,sp,-12 + 100cf3c: dfc00215 stw ra,8(sp) + 100cf40: df000115 stw fp,4(sp) + 100cf44: df000104 addi fp,sp,4 + return ((alt_errno) ? alt_errno() : &errno); + 100cf48: 008040b4 movhi r2,258 + 100cf4c: 10aba104 addi r2,r2,-20860 + 100cf50: 10800017 ldw r2,0(r2) + 100cf54: 1005003a cmpeq r2,r2,zero + 100cf58: 1000061e bne r2,zero,100cf74 + 100cf5c: 008040b4 movhi r2,258 + 100cf60: 10aba104 addi r2,r2,-20860 + 100cf64: 10800017 ldw r2,0(r2) + 100cf68: 103ee83a callr r2 + 100cf6c: e0bfff15 stw r2,-4(fp) + 100cf70: 00000306 br 100cf80 + 100cf74: 008040b4 movhi r2,258 + 100cf78: 10b30404 addi r2,r2,-13296 + 100cf7c: e0bfff15 stw r2,-4(fp) + 100cf80: e0bfff17 ldw r2,-4(fp) +} + 100cf84: e037883a mov sp,fp + 100cf88: dfc00117 ldw ra,4(sp) + 100cf8c: df000017 ldw fp,0(sp) + 100cf90: dec00204 addi sp,sp,8 + 100cf94: f800283a ret + +0100cf98 <__env_lock>: +/* + * + */ + +void __env_lock ( struct _reent *_r ) +{ + 100cf98: deffdf04 addi sp,sp,-132 + 100cf9c: dfc02015 stw ra,128(sp) + 100cfa0: df001f15 stw fp,124(sp) + 100cfa4: df001f04 addi fp,sp,124 + 100cfa8: e13fff15 stw r4,-4(fp) + INT8U err; + int id; + + /* use our priority as a task id */ + + err = OSTaskQuery( OS_PRIO_SELF, &tcb ); + 100cfac: e17fe204 addi r5,fp,-120 + 100cfb0: 01003fc4 movi r4,255 + 100cfb4: 1014dec0 call 1014dec + 100cfb8: e0bffe85 stb r2,-6(fp) + if (err != OS_NO_ERR) + 100cfbc: e0bffe83 ldbu r2,-6(fp) + 100cfc0: 10803fcc andi r2,r2,255 + 100cfc4: 1004c03a cmpne r2,r2,zero + 100cfc8: 1000191e bne r2,zero,100d030 <__env_lock+0x98> + return; + + id = tcb.OSTCBPrio; + 100cfcc: e0bfee83 ldbu r2,-70(fp) + 100cfd0: 10803fcc andi r2,r2,255 + 100cfd4: e0bfe115 stw r2,-124(fp) + + /* see if we own the environment already */ + + OSSemQuery( alt_envsem, &semdata ); + 100cfd8: d1278017 ldw r4,-25088(gp) + 100cfdc: e17ffd04 addi r5,fp,-12 + 100cfe0: 10133380 call 1013338 + if( semdata.OSEventGrp && id == lockid ) + 100cfe4: e0bffe43 ldbu r2,-7(fp) + 100cfe8: 10803fcc andi r2,r2,255 + 100cfec: 1005003a cmpeq r2,r2,zero + 100cff0: 1000071e bne r2,zero,100d010 <__env_lock+0x78> + 100cff4: d0e01617 ldw r3,-32680(gp) + 100cff8: e0bfe117 ldw r2,-124(fp) + 100cffc: 10c0041e bne r2,r3,100d010 <__env_lock+0x78> + { + /* we do; just count the recursion */ + + locks++; + 100d000: d0a77f17 ldw r2,-25092(gp) + 100d004: 10800044 addi r2,r2,1 + 100d008: d0a77f15 stw r2,-25092(gp) + id = tcb.OSTCBPrio; + + /* see if we own the environment already */ + + OSSemQuery( alt_envsem, &semdata ); + if( semdata.OSEventGrp && id == lockid ) + 100d00c: 00000806 br 100d030 <__env_lock+0x98> + } + else + { + /* wait on the other task to yield, then claim ownership */ + + OSSemPend( alt_envsem, 0, &err ); + 100d010: d1278017 ldw r4,-25088(gp) + 100d014: e1bffe84 addi r6,fp,-6 + 100d018: 000b883a mov r5,zero + 100d01c: 1012e180 call 1012e18 + locks = 1; + 100d020: 00800044 movi r2,1 + 100d024: d0a77f15 stw r2,-25092(gp) + lockid = id; + 100d028: e0bfe117 ldw r2,-124(fp) + 100d02c: d0a01615 stw r2,-32680(gp) + } + +#endif /* OS_THREAD_SAFE_NEWLIB */ + return; +} + 100d030: e037883a mov sp,fp + 100d034: dfc00117 ldw ra,4(sp) + 100d038: df000017 ldw fp,0(sp) + 100d03c: dec00204 addi sp,sp,8 + 100d040: f800283a ret + +0100d044 <__env_unlock>: +/* + * + */ + +void __env_unlock ( struct _reent *_r ) +{ + 100d044: defffd04 addi sp,sp,-12 + 100d048: dfc00215 stw ra,8(sp) + 100d04c: df000115 stw fp,4(sp) + 100d050: df000104 addi fp,sp,4 + 100d054: e13fff15 stw r4,-4(fp) +#if OS_THREAD_SAFE_NEWLIB + if (locks == 0) + 100d058: d0a77f17 ldw r2,-25092(gp) + 100d05c: 1005003a cmpeq r2,r2,zero + 100d060: 10000a1e bne r2,zero,100d08c <__env_unlock+0x48> + /* + * release the environment once the number of locks == the number + * of unlocks + */ + + if( (--locks) == 0 ) + 100d064: d0a77f17 ldw r2,-25092(gp) + 100d068: 10bfffc4 addi r2,r2,-1 + 100d06c: d0a77f15 stw r2,-25092(gp) + 100d070: d0a77f17 ldw r2,-25092(gp) + 100d074: 1004c03a cmpne r2,r2,zero + 100d078: 1000041e bne r2,zero,100d08c <__env_unlock+0x48> + { + lockid = -1; + 100d07c: 00bfffc4 movi r2,-1 + 100d080: d0a01615 stw r2,-32680(gp) + OSSemPost( alt_envsem ); + 100d084: d1278017 ldw r4,-25088(gp) + 100d088: 10132100 call 1013210 + } +#endif /* OS_THREAD_SAFE_NEWLIB */ +} + 100d08c: e037883a mov sp,fp + 100d090: dfc00117 ldw ra,4(sp) + 100d094: df000017 ldw fp,0(sp) + 100d098: dec00204 addi sp,sp,8 + 100d09c: f800283a ret + +0100d0a0 <__malloc_lock>: +/* + * + */ + +void __malloc_lock ( struct _reent *_r ) +{ + 100d0a0: deffdb04 addi sp,sp,-148 + 100d0a4: dfc02415 stw ra,144(sp) + 100d0a8: df002315 stw fp,140(sp) + 100d0ac: df002304 addi fp,sp,140 + 100d0b0: e13fff15 stw r4,-4(fp) + OS_TCB tcb; + OS_SEM_DATA semdata; + INT8U err; + int id; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 100d0b4: e03fe015 stw zero,-128(fp) +#endif + + if (OSRunning != OS_TRUE) + 100d0b8: 008040b4 movhi r2,258 + 100d0bc: 10b31044 addi r2,r2,-13247 + 100d0c0: 10800003 ldbu r2,0(r2) + 100d0c4: 10803fcc andi r2,r2,255 + 100d0c8: 10800058 cmpnei r2,r2,1 + 100d0cc: 1000311e bne r2,zero,100d194 <__malloc_lock+0xf4> + return; + + /* use our priority as a task id */ + + err = OSTaskQuery( OS_PRIO_SELF, &tcb ); + 100d0d0: e17fe204 addi r5,fp,-120 + 100d0d4: 01003fc4 movi r4,255 + 100d0d8: 1014dec0 call 1014dec + 100d0dc: e0bffe85 stb r2,-6(fp) + if (err != OS_NO_ERR) + 100d0e0: e0bffe83 ldbu r2,-6(fp) + 100d0e4: 10803fcc andi r2,r2,255 + 100d0e8: 1004c03a cmpne r2,r2,zero + 100d0ec: 1000291e bne r2,zero,100d194 <__malloc_lock+0xf4> + return; + + id = tcb.OSTCBPrio; + 100d0f0: e0bfee83 ldbu r2,-70(fp) + 100d0f4: 10803fcc andi r2,r2,255 + 100d0f8: e0bfe115 stw r2,-124(fp) + + /* see if we own the heap already */ + + OSSemQuery( alt_heapsem, &semdata ); + 100d0fc: d1278217 ldw r4,-25080(gp) + 100d100: e17ffd04 addi r5,fp,-12 + 100d104: 10133380 call 1013338 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 100d108: 0005303a rdctl r2,status + 100d10c: e0bfdf15 stw r2,-132(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 100d110: e0ffdf17 ldw r3,-132(fp) + 100d114: 00bfff84 movi r2,-2 + 100d118: 1884703a and r2,r3,r2 + 100d11c: 1001703a wrctl status,r2 + + return context; + 100d120: e0bfdf17 ldw r2,-132(fp) + + OS_ENTER_CRITICAL(); + 100d124: e0bfe015 stw r2,-128(fp) + + if( !semdata.OSCnt && id == lockid ) + 100d128: e0bffd0b ldhu r2,-12(fp) + 100d12c: 10bfffcc andi r2,r2,65535 + 100d130: 1004c03a cmpne r2,r2,zero + 100d134: 10000b1e bne r2,zero,100d164 <__malloc_lock+0xc4> + 100d138: d0e01717 ldw r3,-32676(gp) + 100d13c: e0bfe117 ldw r2,-124(fp) + 100d140: 10c0081e bne r2,r3,100d164 <__malloc_lock+0xc4> + { + /* we do; just count the recursion */ + locks++; + 100d144: d0a78117 ldw r2,-25084(gp) + 100d148: 10800044 addi r2,r2,1 + 100d14c: d0a78115 stw r2,-25084(gp) + 100d150: e0bfe017 ldw r2,-128(fp) + 100d154: e0bfde15 stw r2,-136(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 100d158: e0bfde17 ldw r2,-136(fp) + 100d15c: 1001703a wrctl status,r2 + + OSSemQuery( alt_heapsem, &semdata ); + + OS_ENTER_CRITICAL(); + + if( !semdata.OSCnt && id == lockid ) + 100d160: 00000c06 br 100d194 <__malloc_lock+0xf4> + 100d164: e0bfe017 ldw r2,-128(fp) + 100d168: e0bfdd15 stw r2,-140(fp) + 100d16c: e0bfdd17 ldw r2,-140(fp) + 100d170: 1001703a wrctl status,r2 + else + { + /* wait on the other task to yield the heap, then claim ownership of it */ + OS_EXIT_CRITICAL(); + + OSSemPend( alt_heapsem, 0, &err ); + 100d174: d1278217 ldw r4,-25080(gp) + 100d178: e1bffe84 addi r6,fp,-6 + 100d17c: 000b883a mov r5,zero + 100d180: 1012e180 call 1012e18 + locks = 1; + 100d184: 00800044 movi r2,1 + 100d188: d0a78115 stw r2,-25084(gp) + lockid = id; + 100d18c: e0bfe117 ldw r2,-124(fp) + 100d190: d0a01715 stw r2,-32676(gp) + } + +#endif /* OS_THREAD_SAFE_NEWLIB */ + return; +} + 100d194: e037883a mov sp,fp + 100d198: dfc00117 ldw ra,4(sp) + 100d19c: df000017 ldw fp,0(sp) + 100d1a0: dec00204 addi sp,sp,8 + 100d1a4: f800283a ret + +0100d1a8 <__malloc_unlock>: +/* + * + */ + +void __malloc_unlock ( struct _reent *_r ) +{ + 100d1a8: defff804 addi sp,sp,-32 + 100d1ac: dfc00715 stw ra,28(sp) + 100d1b0: df000615 stw fp,24(sp) + 100d1b4: df000604 addi fp,sp,24 + 100d1b8: e13fff15 stw r4,-4(fp) +#if OS_THREAD_SAFE_NEWLIB + +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 100d1bc: e03ffe15 stw zero,-8(fp) +#endif + + if (OSRunning != OS_TRUE) + 100d1c0: 008040b4 movhi r2,258 + 100d1c4: 10b31044 addi r2,r2,-13247 + 100d1c8: 10800003 ldbu r2,0(r2) + 100d1cc: 10803fcc andi r2,r2,255 + 100d1d0: 10800058 cmpnei r2,r2,1 + 100d1d4: 1000231e bne r2,zero,100d264 <__malloc_unlock+0xbc> +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 100d1d8: 0005303a rdctl r2,status + 100d1dc: e0bffd15 stw r2,-12(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 100d1e0: e0fffd17 ldw r3,-12(fp) + 100d1e4: 00bfff84 movi r2,-2 + 100d1e8: 1884703a and r2,r3,r2 + 100d1ec: 1001703a wrctl status,r2 + + return context; + 100d1f0: e0bffd17 ldw r2,-12(fp) + return; + + OS_ENTER_CRITICAL(); + 100d1f4: e0bffe15 stw r2,-8(fp) + if (locks == 0) + 100d1f8: d0a78117 ldw r2,-25084(gp) + 100d1fc: 1004c03a cmpne r2,r2,zero + 100d200: 1000051e bne r2,zero,100d218 <__malloc_unlock+0x70> + 100d204: e0bffe17 ldw r2,-8(fp) + 100d208: e0bffc15 stw r2,-16(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 100d20c: e0bffc17 ldw r2,-16(fp) + 100d210: 1001703a wrctl status,r2 + { + OS_EXIT_CRITICAL(); + return; + 100d214: 00001306 br 100d264 <__malloc_unlock+0xbc> + } + + /* release the heap once the number of locks == the number of unlocks */ + if( (--locks) == 0 ) + 100d218: d0a78117 ldw r2,-25084(gp) + 100d21c: 10bfffc4 addi r2,r2,-1 + 100d220: d0a78115 stw r2,-25084(gp) + 100d224: d0a78117 ldw r2,-25084(gp) + 100d228: 1004c03a cmpne r2,r2,zero + 100d22c: 1000091e bne r2,zero,100d254 <__malloc_unlock+0xac> + { + lockid = -1; + 100d230: 00bfffc4 movi r2,-1 + 100d234: d0a01715 stw r2,-32676(gp) + 100d238: e0bffe17 ldw r2,-8(fp) + 100d23c: e0bffb15 stw r2,-20(fp) + 100d240: e0bffb17 ldw r2,-20(fp) + 100d244: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + OSSemPost( alt_heapsem ); + 100d248: d1278217 ldw r4,-25080(gp) + 100d24c: 10132100 call 1013210 + 100d250: 00000406 br 100d264 <__malloc_unlock+0xbc> + 100d254: e0bffe17 ldw r2,-8(fp) + 100d258: e0bffa15 stw r2,-24(fp) + 100d25c: e0bffa17 ldw r2,-24(fp) + 100d260: 1001703a wrctl status,r2 + { + OS_EXIT_CRITICAL(); + } + +#endif /* OS_THREAD_SAFE_NEWLIB */ +} + 100d264: e037883a mov sp,fp + 100d268: dfc00117 ldw ra,4(sp) + 100d26c: df000017 ldw fp,0(sp) + 100d270: dec00204 addi sp,sp,8 + 100d274: f800283a ret + +0100d278 : +********************************************************************************************************* +*/ + +#if (OS_EVENT_EN) && (OS_EVENT_NAME_SIZE > 1) +INT8U OSEventNameGet (OS_EVENT *pevent, INT8U *pname, INT8U *perr) +{ + 100d278: defff604 addi sp,sp,-40 + 100d27c: dfc00915 stw ra,36(sp) + 100d280: df000815 stw fp,32(sp) + 100d284: df000804 addi fp,sp,32 + 100d288: e13ffc15 stw r4,-16(fp) + 100d28c: e17ffd15 stw r5,-12(fp) + 100d290: e1bffe15 stw r6,-8(fp) + INT8U len; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 100d294: e03ffa15 stw zero,-24(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + 100d298: e0bffe17 ldw r2,-8(fp) + 100d29c: 1004c03a cmpne r2,r2,zero + 100d2a0: 1000021e bne r2,zero,100d2ac + return (0); + 100d2a4: e03fff15 stw zero,-4(fp) + 100d2a8: 00003906 br 100d390 + } + if (pevent == (OS_EVENT *)0) { /* Is 'pevent' a NULL pointer? */ + 100d2ac: e0bffc17 ldw r2,-16(fp) + 100d2b0: 1004c03a cmpne r2,r2,zero + 100d2b4: 1000051e bne r2,zero,100d2cc + *perr = OS_ERR_PEVENT_NULL; + 100d2b8: e0fffe17 ldw r3,-8(fp) + 100d2bc: 00800104 movi r2,4 + 100d2c0: 18800005 stb r2,0(r3) + return (0); + 100d2c4: e03fff15 stw zero,-4(fp) + 100d2c8: 00003106 br 100d390 + } + if (pname == (INT8U *)0) { /* Is 'pname' a NULL pointer? */ + 100d2cc: e0bffd17 ldw r2,-12(fp) + 100d2d0: 1004c03a cmpne r2,r2,zero + 100d2d4: 1000051e bne r2,zero,100d2ec + *perr = OS_ERR_PNAME_NULL; + 100d2d8: e0fffe17 ldw r3,-8(fp) + 100d2dc: 00800304 movi r2,12 + 100d2e0: 18800005 stb r2,0(r3) + return (0); + 100d2e4: e03fff15 stw zero,-4(fp) + 100d2e8: 00002906 br 100d390 + } +#endif + if (OSIntNesting > 0) { /* See if trying to call from an ISR */ + 100d2ec: d0a79103 ldbu r2,-25020(gp) + 100d2f0: 10803fcc andi r2,r2,255 + 100d2f4: 1005003a cmpeq r2,r2,zero + 100d2f8: 1000051e bne r2,zero,100d310 + *perr = OS_ERR_NAME_GET_ISR; + 100d2fc: e0fffe17 ldw r3,-8(fp) + 100d300: 00800444 movi r2,17 + 100d304: 18800005 stb r2,0(r3) + return (0); + 100d308: e03fff15 stw zero,-4(fp) + 100d30c: 00002006 br 100d390 + } + switch (pevent->OSEventType) { + 100d310: e0bffc17 ldw r2,-16(fp) + 100d314: 10800003 ldbu r2,0(r2) + 100d318: 10803fcc andi r2,r2,255 + 100d31c: 10bfffc4 addi r2,r2,-1 + 100d320: 10800128 cmpgeui r2,r2,4 + 100d324: 1000161e bne r2,zero,100d380 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 100d328: 0005303a rdctl r2,status + 100d32c: e0bff915 stw r2,-28(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 100d330: e0fff917 ldw r3,-28(fp) + 100d334: 00bfff84 movi r2,-2 + 100d338: 1884703a and r2,r3,r2 + 100d33c: 1001703a wrctl status,r2 + + return context; + 100d340: e0bff917 ldw r2,-28(fp) + + default: + *perr = OS_ERR_EVENT_TYPE; + return (0); + } + OS_ENTER_CRITICAL(); + 100d344: e0bffa15 stw r2,-24(fp) + len = OS_StrCopy(pname, pevent->OSEventName); /* Copy name from OS_EVENT */ + 100d348: e0bffc17 ldw r2,-16(fp) + 100d34c: 11400384 addi r5,r2,14 + 100d350: e13ffd17 ldw r4,-12(fp) + 100d354: 100edfc0 call 100edfc + 100d358: e0bffb05 stb r2,-20(fp) + 100d35c: e0bffa17 ldw r2,-24(fp) + 100d360: e0bff815 stw r2,-32(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 100d364: e0bff817 ldw r2,-32(fp) + 100d368: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + 100d36c: e0bffe17 ldw r2,-8(fp) + 100d370: 10000005 stb zero,0(r2) + return (len); + 100d374: e0bffb03 ldbu r2,-20(fp) + 100d378: e0bfff15 stw r2,-4(fp) + 100d37c: 00000406 br 100d390 + case OS_EVENT_TYPE_MBOX: + case OS_EVENT_TYPE_Q: + break; + + default: + *perr = OS_ERR_EVENT_TYPE; + 100d380: e0fffe17 ldw r3,-8(fp) + 100d384: 00800044 movi r2,1 + 100d388: 18800005 stb r2,0(r3) + return (0); + 100d38c: e03fff15 stw zero,-4(fp) + 100d390: e0bfff17 ldw r2,-4(fp) + OS_ENTER_CRITICAL(); + len = OS_StrCopy(pname, pevent->OSEventName); /* Copy name from OS_EVENT */ + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + return (len); +} + 100d394: e037883a mov sp,fp + 100d398: dfc00117 ldw ra,4(sp) + 100d39c: df000017 ldw fp,0(sp) + 100d3a0: dec00204 addi sp,sp,8 + 100d3a4: f800283a ret + +0100d3a8 : +********************************************************************************************************* +*/ + +#if (OS_EVENT_EN) && (OS_EVENT_NAME_SIZE > 1) +void OSEventNameSet (OS_EVENT *pevent, INT8U *pname, INT8U *perr) +{ + 100d3a8: defff604 addi sp,sp,-40 + 100d3ac: dfc00915 stw ra,36(sp) + 100d3b0: df000815 stw fp,32(sp) + 100d3b4: df000804 addi fp,sp,32 + 100d3b8: e13ffd15 stw r4,-12(fp) + 100d3bc: e17ffe15 stw r5,-8(fp) + 100d3c0: e1bfff15 stw r6,-4(fp) + INT8U len; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 100d3c4: e03ffb15 stw zero,-20(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + 100d3c8: e0bfff17 ldw r2,-4(fp) + 100d3cc: 1005003a cmpeq r2,r2,zero + 100d3d0: 1000411e bne r2,zero,100d4d8 + return; + } + if (pevent == (OS_EVENT *)0) { /* Is 'pevent' a NULL pointer? */ + 100d3d4: e0bffd17 ldw r2,-12(fp) + 100d3d8: 1004c03a cmpne r2,r2,zero + 100d3dc: 1000041e bne r2,zero,100d3f0 + *perr = OS_ERR_PEVENT_NULL; + 100d3e0: e0ffff17 ldw r3,-4(fp) + 100d3e4: 00800104 movi r2,4 + 100d3e8: 18800005 stb r2,0(r3) + return; + 100d3ec: 00003a06 br 100d4d8 + } + if (pname == (INT8U *)0) { /* Is 'pname' a NULL pointer? */ + 100d3f0: e0bffe17 ldw r2,-8(fp) + 100d3f4: 1004c03a cmpne r2,r2,zero + 100d3f8: 1000041e bne r2,zero,100d40c + *perr = OS_ERR_PNAME_NULL; + 100d3fc: e0ffff17 ldw r3,-4(fp) + 100d400: 00800304 movi r2,12 + 100d404: 18800005 stb r2,0(r3) + return; + 100d408: 00003306 br 100d4d8 + } +#endif + if (OSIntNesting > 0) { /* See if trying to call from an ISR */ + 100d40c: d0a79103 ldbu r2,-25020(gp) + 100d410: 10803fcc andi r2,r2,255 + 100d414: 1005003a cmpeq r2,r2,zero + 100d418: 1000041e bne r2,zero,100d42c + *perr = OS_ERR_NAME_SET_ISR; + 100d41c: e0ffff17 ldw r3,-4(fp) + 100d420: 00800484 movi r2,18 + 100d424: 18800005 stb r2,0(r3) + return; + 100d428: 00002b06 br 100d4d8 + } + switch (pevent->OSEventType) { + 100d42c: e0bffd17 ldw r2,-12(fp) + 100d430: 10800003 ldbu r2,0(r2) + 100d434: 10803fcc andi r2,r2,255 + 100d438: 10bfffc4 addi r2,r2,-1 + 100d43c: 10800128 cmpgeui r2,r2,4 + 100d440: 10000f1e bne r2,zero,100d480 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 100d444: 0005303a rdctl r2,status + 100d448: e0bffa15 stw r2,-24(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 100d44c: e0fffa17 ldw r3,-24(fp) + 100d450: 00bfff84 movi r2,-2 + 100d454: 1884703a and r2,r3,r2 + 100d458: 1001703a wrctl status,r2 + + return context; + 100d45c: e0bffa17 ldw r2,-24(fp) + + default: + *perr = OS_ERR_EVENT_TYPE; + return; + } + OS_ENTER_CRITICAL(); + 100d460: e0bffb15 stw r2,-20(fp) + len = OS_StrLen(pname); /* Can we fit the string in the storage area? */ + 100d464: e13ffe17 ldw r4,-8(fp) + 100d468: 100ee7c0 call 100ee7c + 100d46c: e0bffc05 stb r2,-16(fp) + if (len > (OS_EVENT_NAME_SIZE - 1)) { /* No */ + 100d470: e0bffc03 ldbu r2,-16(fp) + 100d474: 10800828 cmpgeui r2,r2,32 + 100d478: 1000051e bne r2,zero,100d490 + 100d47c: 00000c06 br 100d4b0 + case OS_EVENT_TYPE_MBOX: + case OS_EVENT_TYPE_Q: + break; + + default: + *perr = OS_ERR_EVENT_TYPE; + 100d480: e0ffff17 ldw r3,-4(fp) + 100d484: 00800044 movi r2,1 + 100d488: 18800005 stb r2,0(r3) + return; + 100d48c: 00001206 br 100d4d8 + 100d490: e0bffb17 ldw r2,-20(fp) + 100d494: e0bff915 stw r2,-28(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 100d498: e0bff917 ldw r2,-28(fp) + 100d49c: 1001703a wrctl status,r2 + } + OS_ENTER_CRITICAL(); + len = OS_StrLen(pname); /* Can we fit the string in the storage area? */ + if (len > (OS_EVENT_NAME_SIZE - 1)) { /* No */ + OS_EXIT_CRITICAL(); + *perr = OS_ERR_EVENT_NAME_TOO_LONG; + 100d4a0: e0ffff17 ldw r3,-4(fp) + 100d4a4: 008002c4 movi r2,11 + 100d4a8: 18800005 stb r2,0(r3) + return; + 100d4ac: 00000a06 br 100d4d8 + } + (void)OS_StrCopy(pevent->OSEventName, pname); /* Yes, copy name to the event control block */ + 100d4b0: e0bffd17 ldw r2,-12(fp) + 100d4b4: 11000384 addi r4,r2,14 + 100d4b8: e17ffe17 ldw r5,-8(fp) + 100d4bc: 100edfc0 call 100edfc + 100d4c0: e0bffb17 ldw r2,-20(fp) + 100d4c4: e0bff815 stw r2,-32(fp) + 100d4c8: e0bff817 ldw r2,-32(fp) + 100d4cc: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + 100d4d0: e0bfff17 ldw r2,-4(fp) + 100d4d4: 10000005 stb zero,0(r2) +} + 100d4d8: e037883a mov sp,fp + 100d4dc: dfc00117 ldw ra,4(sp) + 100d4e0: df000017 ldw fp,0(sp) + 100d4e4: dec00204 addi sp,sp,8 + 100d4e8: f800283a ret + +0100d4ec : +********************************************************************************************************* +*/ +/*$PAGE*/ +#if ((OS_EVENT_EN) && (OS_EVENT_MULTI_EN > 0)) +INT16U OSEventPendMulti (OS_EVENT **pevents_pend, OS_EVENT **pevents_rdy, void **pmsgs_rdy, INT16U timeout, INT8U *perr) +{ + 100d4ec: deffe704 addi sp,sp,-100 + 100d4f0: dfc01815 stw ra,96(sp) + 100d4f4: df001715 stw fp,92(sp) + 100d4f8: df001704 addi fp,sp,92 + 100d4fc: e13ff615 stw r4,-40(fp) + 100d500: e17ff715 stw r5,-36(fp) + 100d504: e1bff815 stw r6,-32(fp) + 100d508: e1fff90d sth r7,-28(fp) +#endif + BOOLEAN events_rdy; + INT16U events_rdy_nbr; + INT8U events_stat; +#if (OS_CRITICAL_METHOD == 3) /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 100d50c: e03ff015 stw zero,-64(fp) +#endif + + + +#if (OS_ARG_CHK_EN > 0) + if (perr == (INT8U *)0) { /* Validate 'perr' */ + 100d510: e0800217 ldw r2,8(fp) + 100d514: 1004c03a cmpne r2,r2,zero + 100d518: 1000021e bne r2,zero,100d524 + return (0); + 100d51c: e03fff15 stw zero,-4(fp) + 100d520: 00019906 br 100db88 + } + if (pevents_pend == (OS_EVENT **)0) { /* Validate 'pevents_pend' */ + 100d524: e0bff617 ldw r2,-40(fp) + 100d528: 1004c03a cmpne r2,r2,zero + 100d52c: 1000051e bne r2,zero,100d544 + *perr = OS_ERR_PEVENT_NULL; + 100d530: e0c00217 ldw r3,8(fp) + 100d534: 00800104 movi r2,4 + 100d538: 18800005 stb r2,0(r3) + return (0); + 100d53c: e03fff15 stw zero,-4(fp) + 100d540: 00019106 br 100db88 + } + if (pevents_rdy == (OS_EVENT **)0) { /* Validate 'pevents_rdy' */ + 100d544: e0bff717 ldw r2,-36(fp) + 100d548: 1004c03a cmpne r2,r2,zero + 100d54c: 1000051e bne r2,zero,100d564 + *perr = OS_ERR_PEVENT_NULL; + 100d550: e0c00217 ldw r3,8(fp) + 100d554: 00800104 movi r2,4 + 100d558: 18800005 stb r2,0(r3) + return (0); + 100d55c: e03fff15 stw zero,-4(fp) + 100d560: 00018906 br 100db88 + } + if (pmsgs_rdy == (void **)0) { /* Validate 'pmsgs_rdy' */ + 100d564: e0bff817 ldw r2,-32(fp) + 100d568: 1004c03a cmpne r2,r2,zero + 100d56c: 1000051e bne r2,zero,100d584 + *perr = OS_ERR_PEVENT_NULL; + 100d570: e0c00217 ldw r3,8(fp) + 100d574: 00800104 movi r2,4 + 100d578: 18800005 stb r2,0(r3) + return (0); + 100d57c: e03fff15 stw zero,-4(fp) + 100d580: 00018106 br 100db88 + } +#endif + + *pevents_rdy = (OS_EVENT *)0; /* Init array to NULL in case of errors */ + 100d584: e0bff717 ldw r2,-36(fp) + 100d588: 10000015 stw zero,0(r2) + + pevents = pevents_pend; + 100d58c: e0bff617 ldw r2,-40(fp) + 100d590: e0bff515 stw r2,-44(fp) + pevent = *pevents; + 100d594: e0bff517 ldw r2,-44(fp) + 100d598: 10800017 ldw r2,0(r2) + 100d59c: e0bff415 stw r2,-48(fp) + while (pevent != (OS_EVENT *)0) { + 100d5a0: 00001806 br 100d604 + switch (pevent->OSEventType) { /* Validate event block types */ + 100d5a4: e0bff417 ldw r2,-48(fp) + 100d5a8: 10800003 ldbu r2,0(r2) + 100d5ac: 10803fcc andi r2,r2,255 + 100d5b0: e0bffe15 stw r2,-8(fp) + 100d5b4: e0fffe17 ldw r3,-8(fp) + 100d5b8: 188000a0 cmpeqi r2,r3,2 + 100d5bc: 10000b1e bne r2,zero,100d5ec + 100d5c0: e0fffe17 ldw r3,-8(fp) + 100d5c4: 188000e0 cmpeqi r2,r3,3 + 100d5c8: 1000081e bne r2,zero,100d5ec + 100d5cc: e0fffe17 ldw r3,-8(fp) + 100d5d0: 18800060 cmpeqi r2,r3,1 + 100d5d4: 1000051e bne r2,zero,100d5ec +#endif + + case OS_EVENT_TYPE_MUTEX: + case OS_EVENT_TYPE_FLAG: + default: + *perr = OS_ERR_EVENT_TYPE; + 100d5d8: e0c00217 ldw r3,8(fp) + 100d5dc: 00800044 movi r2,1 + 100d5e0: 18800005 stb r2,0(r3) + return (0); + 100d5e4: e03fff15 stw zero,-4(fp) + 100d5e8: 00016706 br 100db88 + } + pevents++; + 100d5ec: e0bff517 ldw r2,-44(fp) + 100d5f0: 10800104 addi r2,r2,4 + 100d5f4: e0bff515 stw r2,-44(fp) + pevent = *pevents; + 100d5f8: e0bff517 ldw r2,-44(fp) + 100d5fc: 10800017 ldw r2,0(r2) + 100d600: e0bff415 stw r2,-48(fp) + + *pevents_rdy = (OS_EVENT *)0; /* Init array to NULL in case of errors */ + + pevents = pevents_pend; + pevent = *pevents; + while (pevent != (OS_EVENT *)0) { + 100d604: e0bff417 ldw r2,-48(fp) + 100d608: 1004c03a cmpne r2,r2,zero + 100d60c: 103fe51e bne r2,zero,100d5a4 + } + pevents++; + pevent = *pevents; + } + + if (OSIntNesting > 0) { /* See if called from ISR ... */ + 100d610: d0a79103 ldbu r2,-25020(gp) + 100d614: 10803fcc andi r2,r2,255 + 100d618: 1005003a cmpeq r2,r2,zero + 100d61c: 1000051e bne r2,zero,100d634 + *perr = OS_ERR_PEND_ISR; /* ... can't PEND from an ISR */ + 100d620: e0c00217 ldw r3,8(fp) + 100d624: 00800084 movi r2,2 + 100d628: 18800005 stb r2,0(r3) + return (0); + 100d62c: e03fff15 stw zero,-4(fp) + 100d630: 00015506 br 100db88 + } + if (OSLockNesting > 0) { /* See if called with scheduler locked ... */ + 100d634: d0a78303 ldbu r2,-25076(gp) + 100d638: 10803fcc andi r2,r2,255 + 100d63c: 1005003a cmpeq r2,r2,zero + 100d640: 1000051e bne r2,zero,100d658 + *perr = OS_ERR_PEND_LOCKED; /* ... can't PEND when locked */ + 100d644: e0c00217 ldw r3,8(fp) + 100d648: 00800344 movi r2,13 + 100d64c: 18800005 stb r2,0(r3) + return (0); + 100d650: e03fff15 stw zero,-4(fp) + 100d654: 00014c06 br 100db88 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 100d658: 0005303a rdctl r2,status + 100d65c: e0bfef15 stw r2,-68(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 100d660: e0ffef17 ldw r3,-68(fp) + 100d664: 00bfff84 movi r2,-2 + 100d668: 1884703a and r2,r3,r2 + 100d66c: 1001703a wrctl status,r2 + + return context; + 100d670: e0bfef17 ldw r2,-68(fp) + } + +/*$PAGE*/ + OS_ENTER_CRITICAL(); + 100d674: e0bff015 stw r2,-64(fp) + events_rdy = OS_FALSE; + 100d678: e03ff205 stb zero,-56(fp) + events_rdy_nbr = 0; + 100d67c: e03ff18d sth zero,-58(fp) + events_stat = OS_STAT_RDY; + 100d680: e03ff105 stb zero,-60(fp) + pevents = pevents_pend; + 100d684: e0bff617 ldw r2,-40(fp) + 100d688: e0bff515 stw r2,-44(fp) + pevent = *pevents; + 100d68c: e0bff517 ldw r2,-44(fp) + 100d690: 10800017 ldw r2,0(r2) + 100d694: e0bff415 stw r2,-48(fp) + while (pevent != (OS_EVENT *)0) { /* See if any events already available */ + 100d698: 00008f06 br 100d8d8 + switch (pevent->OSEventType) { + 100d69c: e0bff417 ldw r2,-48(fp) + 100d6a0: 10800003 ldbu r2,0(r2) + 100d6a4: 10803fcc andi r2,r2,255 + 100d6a8: e0bffd15 stw r2,-12(fp) + 100d6ac: e0fffd17 ldw r3,-12(fp) + 100d6b0: 188000a0 cmpeqi r2,r3,2 + 100d6b4: 1000441e bne r2,zero,100d7c8 + 100d6b8: e0fffd17 ldw r3,-12(fp) + 100d6bc: 188000e0 cmpeqi r2,r3,3 + 100d6c0: 1000041e bne r2,zero,100d6d4 + 100d6c4: e0fffd17 ldw r3,-12(fp) + 100d6c8: 18800060 cmpeqi r2,r3,1 + 100d6cc: 1000211e bne r2,zero,100d754 + 100d6d0: 00006f06 br 100d890 +#if (OS_SEM_EN > 0) + case OS_EVENT_TYPE_SEM: + if (pevent->OSEventCnt > 0) { /* If semaphore count > 0, resource available; */ + 100d6d4: e0bff417 ldw r2,-48(fp) + 100d6d8: 1080020b ldhu r2,8(r2) + 100d6dc: 10bfffcc andi r2,r2,65535 + 100d6e0: 1005003a cmpeq r2,r2,zero + 100d6e4: 1000171e bne r2,zero,100d744 + pevent->OSEventCnt--; /* ... decrement semaphore, ... */ + 100d6e8: e0bff417 ldw r2,-48(fp) + 100d6ec: 1080020b ldhu r2,8(r2) + 100d6f0: 10bfffc4 addi r2,r2,-1 + 100d6f4: 1007883a mov r3,r2 + 100d6f8: e0bff417 ldw r2,-48(fp) + 100d6fc: 10c0020d sth r3,8(r2) + *pevents_rdy++ = pevent; /* ... and return available semaphore event */ + 100d700: e0fff717 ldw r3,-36(fp) + 100d704: e0bff417 ldw r2,-48(fp) + 100d708: 18800015 stw r2,0(r3) + 100d70c: e0bff717 ldw r2,-36(fp) + 100d710: 10800104 addi r2,r2,4 + 100d714: e0bff715 stw r2,-36(fp) + events_rdy = OS_TRUE; + 100d718: 00800044 movi r2,1 + 100d71c: e0bff205 stb r2,-56(fp) + *pmsgs_rdy++ = (void *)0; /* NO message returned for semaphores */ + 100d720: e0bff817 ldw r2,-32(fp) + 100d724: 10000015 stw zero,0(r2) + 100d728: e0bff817 ldw r2,-32(fp) + 100d72c: 10800104 addi r2,r2,4 + 100d730: e0bff815 stw r2,-32(fp) + events_rdy_nbr++; + 100d734: e0bff18b ldhu r2,-58(fp) + 100d738: 10800044 addi r2,r2,1 + 100d73c: e0bff18d sth r2,-58(fp) + 100d740: 00005f06 br 100d8c0 + + } else { + events_stat |= OS_STAT_SEM; /* Configure multi-pend for semaphore events */ + 100d744: e0bff103 ldbu r2,-60(fp) + 100d748: 10800054 ori r2,r2,1 + 100d74c: e0bff105 stb r2,-60(fp) + } + break; + 100d750: 00005b06 br 100d8c0 +#endif + +#if (OS_MBOX_EN > 0) + case OS_EVENT_TYPE_MBOX: + if (pevent->OSEventPtr != (void *)0) { /* If mailbox NOT empty; ... */ + 100d754: e0bff417 ldw r2,-48(fp) + 100d758: 10800117 ldw r2,4(r2) + 100d75c: 1005003a cmpeq r2,r2,zero + 100d760: 1000151e bne r2,zero,100d7b8 + /* ... return available message, ... */ + *pmsgs_rdy++ = (void *)pevent->OSEventPtr; + 100d764: e0bff417 ldw r2,-48(fp) + 100d768: 10c00117 ldw r3,4(r2) + 100d76c: e0bff817 ldw r2,-32(fp) + 100d770: 10c00015 stw r3,0(r2) + 100d774: e0bff817 ldw r2,-32(fp) + 100d778: 10800104 addi r2,r2,4 + 100d77c: e0bff815 stw r2,-32(fp) + pevent->OSEventPtr = (void *)0; + 100d780: e0bff417 ldw r2,-48(fp) + 100d784: 10000115 stw zero,4(r2) + *pevents_rdy++ = pevent; /* ... and return available mailbox event */ + 100d788: e0fff717 ldw r3,-36(fp) + 100d78c: e0bff417 ldw r2,-48(fp) + 100d790: 18800015 stw r2,0(r3) + 100d794: e0bff717 ldw r2,-36(fp) + 100d798: 10800104 addi r2,r2,4 + 100d79c: e0bff715 stw r2,-36(fp) + events_rdy = OS_TRUE; + 100d7a0: 00800044 movi r2,1 + 100d7a4: e0bff205 stb r2,-56(fp) + events_rdy_nbr++; + 100d7a8: e0bff18b ldhu r2,-58(fp) + 100d7ac: 10800044 addi r2,r2,1 + 100d7b0: e0bff18d sth r2,-58(fp) + 100d7b4: 00004206 br 100d8c0 + + } else { + events_stat |= OS_STAT_MBOX; /* Configure multi-pend for mailbox events */ + 100d7b8: e0bff103 ldbu r2,-60(fp) + 100d7bc: 10800094 ori r2,r2,2 + 100d7c0: e0bff105 stb r2,-60(fp) + } + break; + 100d7c4: 00003e06 br 100d8c0 +#endif + +#if ((OS_Q_EN > 0) && (OS_MAX_QS > 0)) + case OS_EVENT_TYPE_Q: + pq = (OS_Q *)pevent->OSEventPtr; + 100d7c8: e0bff417 ldw r2,-48(fp) + 100d7cc: 10800117 ldw r2,4(r2) + 100d7d0: e0bff315 stw r2,-52(fp) + if (pq->OSQEntries > 0) { /* If queue NOT empty; ... */ + 100d7d4: e0bff317 ldw r2,-52(fp) + 100d7d8: 1080058b ldhu r2,22(r2) + 100d7dc: 10bfffcc andi r2,r2,65535 + 100d7e0: 1005003a cmpeq r2,r2,zero + 100d7e4: 1000261e bne r2,zero,100d880 + /* ... return available message, ... */ + *pmsgs_rdy++ = (void *)*pq->OSQOut++; + 100d7e8: e0bff317 ldw r2,-52(fp) + 100d7ec: 11000417 ldw r4,16(r2) + 100d7f0: 20c00017 ldw r3,0(r4) + 100d7f4: e0bff817 ldw r2,-32(fp) + 100d7f8: 10c00015 stw r3,0(r2) + 100d7fc: e0bff817 ldw r2,-32(fp) + 100d800: 10800104 addi r2,r2,4 + 100d804: e0bff815 stw r2,-32(fp) + 100d808: 20c00104 addi r3,r4,4 + 100d80c: e0bff317 ldw r2,-52(fp) + 100d810: 10c00415 stw r3,16(r2) + if (pq->OSQOut == pq->OSQEnd) { /* If OUT ptr at queue end, ... */ + 100d814: e0bff317 ldw r2,-52(fp) + 100d818: 10c00417 ldw r3,16(r2) + 100d81c: e0bff317 ldw r2,-52(fp) + 100d820: 10800217 ldw r2,8(r2) + 100d824: 1880041e bne r3,r2,100d838 + pq->OSQOut = pq->OSQStart; /* ... wrap to queue start */ + 100d828: e0bff317 ldw r2,-52(fp) + 100d82c: 10c00117 ldw r3,4(r2) + 100d830: e0bff317 ldw r2,-52(fp) + 100d834: 10c00415 stw r3,16(r2) + } + pq->OSQEntries--; /* Update number of queue entries */ + 100d838: e0bff317 ldw r2,-52(fp) + 100d83c: 1080058b ldhu r2,22(r2) + 100d840: 10bfffc4 addi r2,r2,-1 + 100d844: 1007883a mov r3,r2 + 100d848: e0bff317 ldw r2,-52(fp) + 100d84c: 10c0058d sth r3,22(r2) + *pevents_rdy++ = pevent; /* ... and return available queue event */ + 100d850: e0fff717 ldw r3,-36(fp) + 100d854: e0bff417 ldw r2,-48(fp) + 100d858: 18800015 stw r2,0(r3) + 100d85c: e0bff717 ldw r2,-36(fp) + 100d860: 10800104 addi r2,r2,4 + 100d864: e0bff715 stw r2,-36(fp) + events_rdy = OS_TRUE; + 100d868: 00800044 movi r2,1 + 100d86c: e0bff205 stb r2,-56(fp) + events_rdy_nbr++; + 100d870: e0bff18b ldhu r2,-58(fp) + 100d874: 10800044 addi r2,r2,1 + 100d878: e0bff18d sth r2,-58(fp) + 100d87c: 00001006 br 100d8c0 + + } else { + events_stat |= OS_STAT_Q; /* Configure multi-pend for queue events */ + 100d880: e0bff103 ldbu r2,-60(fp) + 100d884: 10800114 ori r2,r2,4 + 100d888: e0bff105 stb r2,-60(fp) + } + break; + 100d88c: 00000c06 br 100d8c0 + 100d890: e0bff017 ldw r2,-64(fp) + 100d894: e0bfee15 stw r2,-72(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 100d898: e0bfee17 ldw r2,-72(fp) + 100d89c: 1001703a wrctl status,r2 + + case OS_EVENT_TYPE_MUTEX: + case OS_EVENT_TYPE_FLAG: + default: + OS_EXIT_CRITICAL(); + *pevents_rdy = (OS_EVENT *)0; /* NULL terminate return event array */ + 100d8a0: e0bff717 ldw r2,-36(fp) + 100d8a4: 10000015 stw zero,0(r2) + *perr = OS_ERR_EVENT_TYPE; + 100d8a8: e0c00217 ldw r3,8(fp) + 100d8ac: 00800044 movi r2,1 + 100d8b0: 18800005 stb r2,0(r3) + return (events_rdy_nbr); + 100d8b4: e0bff18b ldhu r2,-58(fp) + 100d8b8: e0bfff15 stw r2,-4(fp) + 100d8bc: 0000b206 br 100db88 + } + pevents++; + 100d8c0: e0bff517 ldw r2,-44(fp) + 100d8c4: 10800104 addi r2,r2,4 + 100d8c8: e0bff515 stw r2,-44(fp) + pevent = *pevents; + 100d8cc: e0bff517 ldw r2,-44(fp) + 100d8d0: 10800017 ldw r2,0(r2) + 100d8d4: e0bff415 stw r2,-48(fp) + events_rdy = OS_FALSE; + events_rdy_nbr = 0; + events_stat = OS_STAT_RDY; + pevents = pevents_pend; + pevent = *pevents; + while (pevent != (OS_EVENT *)0) { /* See if any events already available */ + 100d8d8: e0bff417 ldw r2,-48(fp) + 100d8dc: 1004c03a cmpne r2,r2,zero + 100d8e0: 103f6e1e bne r2,zero,100d69c + } + pevents++; + pevent = *pevents; + } + + if ( events_rdy == OS_TRUE) { /* Return any events already available */ + 100d8e4: e0bff203 ldbu r2,-56(fp) + 100d8e8: 10800058 cmpnei r2,r2,1 + 100d8ec: 10000b1e bne r2,zero,100d91c + *pevents_rdy = (OS_EVENT *)0; /* NULL terminate return event array */ + 100d8f0: e0bff717 ldw r2,-36(fp) + 100d8f4: 10000015 stw zero,0(r2) + 100d8f8: e0bff017 ldw r2,-64(fp) + 100d8fc: e0bfed15 stw r2,-76(fp) + 100d900: e0bfed17 ldw r2,-76(fp) + 100d904: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + 100d908: e0800217 ldw r2,8(fp) + 100d90c: 10000005 stb zero,0(r2) + return (events_rdy_nbr); + 100d910: e0fff18b ldhu r3,-58(fp) + 100d914: e0ffff15 stw r3,-4(fp) + 100d918: 00009b06 br 100db88 + } +/*$PAGE*/ + /* Otherwise, must wait until any event occurs */ + OSTCBCur->OSTCBStat |= events_stat | /* Resource not available, ... */ + 100d91c: d1279217 ldw r4,-25016(gp) + 100d920: d0a79217 ldw r2,-25016(gp) + 100d924: 10c00c03 ldbu r3,48(r2) + 100d928: e0bff103 ldbu r2,-60(fp) + 100d92c: 1884b03a or r2,r3,r2 + 100d930: 1007883a mov r3,r2 + 100d934: 00bfe004 movi r2,-128 + 100d938: 1884b03a or r2,r3,r2 + 100d93c: 20800c05 stb r2,48(r4) + OS_STAT_MULTI; /* ... pend on multiple events */ + OSTCBCur->OSTCBStatPend = OS_STAT_PEND_OK; + 100d940: d0a79217 ldw r2,-25016(gp) + 100d944: 10000c45 stb zero,49(r2) + OSTCBCur->OSTCBDly = timeout; /* Store pend timeout in TCB */ + 100d948: d0e79217 ldw r3,-25016(gp) + 100d94c: e0bff90b ldhu r2,-28(fp) + 100d950: 18800b8d sth r2,46(r3) + OS_EventTaskWaitMulti(pevents_pend); /* Suspend task until events or timeout occurs */ + 100d954: e13ff617 ldw r4,-40(fp) + 100d958: 100e51c0 call 100e51c + 100d95c: e0bff017 ldw r2,-64(fp) + 100d960: e0bfec15 stw r2,-80(fp) + 100d964: e0bfec17 ldw r2,-80(fp) + 100d968: 1001703a wrctl status,r2 + + OS_EXIT_CRITICAL(); + OS_Sched(); /* Find next highest priority task ready */ + 100d96c: 100ecb80 call 100ecb8 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 100d970: 0005303a rdctl r2,status + 100d974: e0bfeb15 stw r2,-84(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 100d978: e0ffeb17 ldw r3,-84(fp) + 100d97c: 00bfff84 movi r2,-2 + 100d980: 1884703a and r2,r3,r2 + 100d984: 1001703a wrctl status,r2 + + return context; + 100d988: e0bfeb17 ldw r2,-84(fp) + OS_ENTER_CRITICAL(); + 100d98c: e0bff015 stw r2,-64(fp) + + switch (OSTCBCur->OSTCBStatPend) { /* Handle event posted, aborted, or timed-out */ + 100d990: d0a79217 ldw r2,-25016(gp) + 100d994: 10800c43 ldbu r2,49(r2) + 100d998: 10803fcc andi r2,r2,255 + 100d99c: e0bffc15 stw r2,-16(fp) + 100d9a0: e0fffc17 ldw r3,-16(fp) + 100d9a4: 1805003a cmpeq r2,r3,zero + 100d9a8: 1000041e bne r2,zero,100d9bc + 100d9ac: e0fffc17 ldw r3,-16(fp) + 100d9b0: 188000a0 cmpeqi r2,r3,2 + 100d9b4: 1000011e bne r2,zero,100d9bc + 100d9b8: 00001906 br 100da20 + case OS_STAT_PEND_OK: + case OS_STAT_PEND_ABORT: + pevent = OSTCBCur->OSTCBEventPtr; + 100d9bc: d0a79217 ldw r2,-25016(gp) + 100d9c0: 10800717 ldw r2,28(r2) + 100d9c4: e0bff415 stw r2,-48(fp) + if (pevent != (OS_EVENT *)0) { /* If task event ptr != NULL, ... */ + 100d9c8: e0bff417 ldw r2,-48(fp) + 100d9cc: 1005003a cmpeq r2,r2,zero + 100d9d0: 10000c1e bne r2,zero,100da04 + *pevents_rdy++ = pevent; /* ... return available event ... */ + 100d9d4: e0fff717 ldw r3,-36(fp) + 100d9d8: e0bff417 ldw r2,-48(fp) + 100d9dc: 18800015 stw r2,0(r3) + 100d9e0: e0bff717 ldw r2,-36(fp) + 100d9e4: 10800104 addi r2,r2,4 + 100d9e8: e0bff715 stw r2,-36(fp) + *pevents_rdy = (OS_EVENT *)0; /* ... & NULL terminate return event array */ + 100d9ec: e0bff717 ldw r2,-36(fp) + 100d9f0: 10000015 stw zero,0(r2) + events_rdy_nbr++; + 100d9f4: e0bff18b ldhu r2,-58(fp) + 100d9f8: 10800044 addi r2,r2,1 + 100d9fc: e0bff18d sth r2,-58(fp) + 100da00: 00000a06 br 100da2c + + } else { /* Else NO event available, handle as timeout */ + OSTCBCur->OSTCBStatPend = OS_STAT_PEND_TO; + 100da04: d0a79217 ldw r2,-25016(gp) + 100da08: 00c00044 movi r3,1 + 100da0c: 10c00c45 stb r3,49(r2) + OS_EventTaskRemoveMulti(OSTCBCur, pevents_pend); + 100da10: d1279217 ldw r4,-25016(gp) + 100da14: e17ff617 ldw r5,-40(fp) + 100da18: 100e7280 call 100e728 + } + break; + 100da1c: 00000306 br 100da2c + + case OS_STAT_PEND_TO: + default: /* ... remove task from events' wait lists */ + OS_EventTaskRemoveMulti(OSTCBCur, pevents_pend); + 100da20: d1279217 ldw r4,-25016(gp) + 100da24: e17ff617 ldw r5,-40(fp) + 100da28: 100e7280 call 100e728 + break; + } + + switch (OSTCBCur->OSTCBStatPend) { + 100da2c: d0a79217 ldw r2,-25016(gp) + 100da30: 10800c43 ldbu r2,49(r2) + 100da34: 10803fcc andi r2,r2,255 + 100da38: e0bffb15 stw r2,-20(fp) + 100da3c: e0fffb17 ldw r3,-20(fp) + 100da40: 1805003a cmpeq r2,r3,zero + 100da44: 1000041e bne r2,zero,100da58 + 100da48: e0fffb17 ldw r3,-20(fp) + 100da4c: 188000a0 cmpeqi r2,r3,2 + 100da50: 10002c1e bne r2,zero,100db04 + 100da54: 00003406 br 100db28 + case OS_STAT_PEND_OK: + switch (pevent->OSEventType) { /* Return event's message */ + 100da58: e0bff417 ldw r2,-48(fp) + 100da5c: 10800003 ldbu r2,0(r2) + 100da60: 10803fcc andi r2,r2,255 + 100da64: e0bffa15 stw r2,-24(fp) + 100da68: e0fffa17 ldw r3,-24(fp) + 100da6c: 18800050 cmplti r2,r3,1 + 100da70: 1000151e bne r2,zero,100dac8 + 100da74: e0fffa17 ldw r3,-24(fp) + 100da78: 188000d0 cmplti r2,r3,3 + 100da7c: 10000a1e bne r2,zero,100daa8 + 100da80: e0fffa17 ldw r3,-24(fp) + 100da84: 188000e0 cmpeqi r2,r3,3 + 100da88: 1000011e bne r2,zero,100da90 + 100da8c: 00000e06 br 100dac8 +#if (OS_SEM_EN > 0) + case OS_EVENT_TYPE_SEM: + *pmsgs_rdy++ = (void *)0; /* NO message returned for semaphores */ + 100da90: e0bff817 ldw r2,-32(fp) + 100da94: 10000015 stw zero,0(r2) + 100da98: e0bff817 ldw r2,-32(fp) + 100da9c: 10800104 addi r2,r2,4 + 100daa0: e0bff815 stw r2,-32(fp) + break; + 100daa4: 00001406 br 100daf8 + +#if ((OS_MBOX_EN > 0) || \ + ((OS_Q_EN > 0) && (OS_MAX_QS > 0))) + case OS_EVENT_TYPE_MBOX: + case OS_EVENT_TYPE_Q: + *pmsgs_rdy++ = (void *)OSTCBCur->OSTCBMsg; /* Return received message */ + 100daa8: d0a79217 ldw r2,-25016(gp) + 100daac: 10c00917 ldw r3,36(r2) + 100dab0: e0bff817 ldw r2,-32(fp) + 100dab4: 10c00015 stw r3,0(r2) + 100dab8: e0bff817 ldw r2,-32(fp) + 100dabc: 10800104 addi r2,r2,4 + 100dac0: e0bff815 stw r2,-32(fp) + break; + 100dac4: 00000c06 br 100daf8 + 100dac8: e0bff017 ldw r2,-64(fp) + 100dacc: e0bfea15 stw r2,-88(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 100dad0: e0bfea17 ldw r2,-88(fp) + 100dad4: 1001703a wrctl status,r2 + + case OS_EVENT_TYPE_MUTEX: + case OS_EVENT_TYPE_FLAG: + default: + OS_EXIT_CRITICAL(); + *pevents_rdy = (OS_EVENT *)0; /* NULL terminate return event array */ + 100dad8: e0bff717 ldw r2,-36(fp) + 100dadc: 10000015 stw zero,0(r2) + *perr = OS_ERR_EVENT_TYPE; + 100dae0: e0c00217 ldw r3,8(fp) + 100dae4: 00800044 movi r2,1 + 100dae8: 18800005 stb r2,0(r3) + return (events_rdy_nbr); + 100daec: e0bff18b ldhu r2,-58(fp) + 100daf0: e0bfff15 stw r2,-4(fp) + 100daf4: 00002406 br 100db88 + } + *perr = OS_ERR_NONE; + 100daf8: e0800217 ldw r2,8(fp) + 100dafc: 10000005 stb zero,0(r2) + break; + 100db00: 00001106 br 100db48 + + case OS_STAT_PEND_ABORT: + *pmsgs_rdy++ = (void *)0; /* NO message returned for abort */ + 100db04: e0bff817 ldw r2,-32(fp) + 100db08: 10000015 stw zero,0(r2) + 100db0c: e0bff817 ldw r2,-32(fp) + 100db10: 10800104 addi r2,r2,4 + 100db14: e0bff815 stw r2,-32(fp) + *perr = OS_ERR_PEND_ABORT; /* Indicate that event aborted */ + 100db18: e0c00217 ldw r3,8(fp) + 100db1c: 00800384 movi r2,14 + 100db20: 18800005 stb r2,0(r3) + break; + 100db24: 00000806 br 100db48 + + case OS_STAT_PEND_TO: + default: + *pmsgs_rdy++ = (void *)0; /* NO message returned for timeout */ + 100db28: e0bff817 ldw r2,-32(fp) + 100db2c: 10000015 stw zero,0(r2) + 100db30: e0bff817 ldw r2,-32(fp) + 100db34: 10800104 addi r2,r2,4 + 100db38: e0bff815 stw r2,-32(fp) + *perr = OS_ERR_TIMEOUT; /* Indicate that events timed out */ + 100db3c: e0c00217 ldw r3,8(fp) + 100db40: 00800284 movi r2,10 + 100db44: 18800005 stb r2,0(r3) + break; + } + + OSTCBCur->OSTCBStat = OS_STAT_RDY; /* Set task status to ready */ + 100db48: d0a79217 ldw r2,-25016(gp) + 100db4c: 10000c05 stb zero,48(r2) + OSTCBCur->OSTCBStatPend = OS_STAT_PEND_OK; /* Clear pend status */ + 100db50: d0a79217 ldw r2,-25016(gp) + 100db54: 10000c45 stb zero,49(r2) + OSTCBCur->OSTCBEventPtr = (OS_EVENT *)0; /* Clear event pointers */ + 100db58: d0a79217 ldw r2,-25016(gp) + 100db5c: 10000715 stw zero,28(r2) + OSTCBCur->OSTCBEventMultiPtr = (OS_EVENT **)0; + 100db60: d0a79217 ldw r2,-25016(gp) + 100db64: 10000815 stw zero,32(r2) + OSTCBCur->OSTCBMsg = (void *)0; /* Clear task message */ + 100db68: d0a79217 ldw r2,-25016(gp) + 100db6c: 10000915 stw zero,36(r2) + 100db70: e0bff017 ldw r2,-64(fp) + 100db74: e0bfe915 stw r2,-92(fp) + 100db78: e0bfe917 ldw r2,-92(fp) + 100db7c: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + + return (events_rdy_nbr); + 100db80: e0fff18b ldhu r3,-58(fp) + 100db84: e0ffff15 stw r3,-4(fp) + 100db88: e0bfff17 ldw r2,-4(fp) +} + 100db8c: e037883a mov sp,fp + 100db90: dfc00117 ldw ra,4(sp) + 100db94: df000017 ldw fp,0(sp) + 100db98: dec00204 addi sp,sp,8 + 100db9c: f800283a ret + +0100dba0 : +* Returns : none +********************************************************************************************************* +*/ + +void OSInit (void) +{ + 100dba0: defffe04 addi sp,sp,-8 + 100dba4: dfc00115 stw ra,4(sp) + 100dba8: df000015 stw fp,0(sp) + 100dbac: d839883a mov fp,sp + OSInitHookBegin(); /* Call port specific initialization code */ + 100dbb0: 10184a00 call 10184a0 + + OS_InitMisc(); /* Initialize miscellaneous variables */ + 100dbb4: 100e9700 call 100e970 + + OS_InitRdyList(); /* Initialize the Ready List */ + 100dbb8: 100e9b40 call 100e9b4 + + OS_InitTCBList(); /* Initialize the free list of OS_TCBs */ + 100dbbc: 100eb180 call 100eb18 + + OS_InitEventList(); /* Initialize the free list of OS_EVENTs */ + 100dbc0: 100e8940 call 100e894 + +#if (OS_FLAG_EN > 0) && (OS_MAX_FLAGS > 0) + OS_FlagInit(); /* Initialize the event flag structures */ + 100dbc4: 1010bc80 call 1010bc8 +#endif + +#if (OS_MEM_EN > 0) && (OS_MAX_MEM_PART > 0) + OS_MemInit(); /* Initialize the memory manager */ + 100dbc8: 10115a00 call 10115a0 +#endif + +#if (OS_Q_EN > 0) && (OS_MAX_QS > 0) + OS_QInit(); /* Initialize the message queue structures */ + 100dbcc: 10128f80 call 10128f8 +#endif + + OS_InitTaskIdle(); /* Create the Idle Task */ + 100dbd0: 100ea200 call 100ea20 +#if OS_TASK_STAT_EN > 0 + OS_InitTaskStat(); /* Create the Statistic Task */ + 100dbd4: 100ea9c0 call 100ea9c + +#if OS_TMR_EN > 0 + OSTmr_Init(); /* Initialize the Timer Manager */ +#endif + + OSInitHookEnd(); /* Call port specific init. code */ + 100dbd8: 10184bc0 call 10184bc + +#if OS_DEBUG_EN > 0 + OSDebugInit(); + 100dbdc: 100f3a00 call 100f3a0 +#endif +} + 100dbe0: e037883a mov sp,fp + 100dbe4: dfc00117 ldw ra,4(sp) + 100dbe8: df000017 ldw fp,0(sp) + 100dbec: dec00204 addi sp,sp,8 + 100dbf0: f800283a ret + +0100dbf4 : +* 5) You are allowed to nest interrupts up to 255 levels deep. +********************************************************************************************************* +*/ + +void OSIntEnter (void) +{ + 100dbf4: defffc04 addi sp,sp,-16 + 100dbf8: df000315 stw fp,12(sp) + 100dbfc: df000304 addi fp,sp,12 +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 100dc00: e03fff15 stw zero,-4(fp) +#endif + + if (OSRunning == OS_TRUE) { + 100dc04: d0a78343 ldbu r2,-25075(gp) + 100dc08: 10803fcc andi r2,r2,255 + 100dc0c: 10800058 cmpnei r2,r2,1 + 100dc10: 1000131e bne r2,zero,100dc60 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 100dc14: 0005303a rdctl r2,status + 100dc18: e0bffe15 stw r2,-8(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 100dc1c: e0fffe17 ldw r3,-8(fp) + 100dc20: 00bfff84 movi r2,-2 + 100dc24: 1884703a and r2,r3,r2 + 100dc28: 1001703a wrctl status,r2 + + return context; + 100dc2c: e0bffe17 ldw r2,-8(fp) + OS_ENTER_CRITICAL(); + 100dc30: e0bfff15 stw r2,-4(fp) + if (OSIntNesting < 255u) { + 100dc34: d0a79103 ldbu r2,-25020(gp) + 100dc38: 10803fcc andi r2,r2,255 + 100dc3c: 10803fe0 cmpeqi r2,r2,255 + 100dc40: 1000031e bne r2,zero,100dc50 + OSIntNesting++; /* Increment ISR nesting level */ + 100dc44: d0a79103 ldbu r2,-25020(gp) + 100dc48: 10800044 addi r2,r2,1 + 100dc4c: d0a79105 stb r2,-25020(gp) + 100dc50: e0bfff17 ldw r2,-4(fp) + 100dc54: e0bffd15 stw r2,-12(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 100dc58: e0bffd17 ldw r2,-12(fp) + 100dc5c: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); + } +} + 100dc60: e037883a mov sp,fp + 100dc64: df000017 ldw fp,0(sp) + 100dc68: dec00104 addi sp,sp,4 + 100dc6c: f800283a ret + +0100dc70 : +* 2) Rescheduling is prevented when the scheduler is locked (see OS_SchedLock()) +********************************************************************************************************* +*/ + +void OSIntExit (void) +{ + 100dc70: defffb04 addi sp,sp,-20 + 100dc74: dfc00415 stw ra,16(sp) + 100dc78: df000315 stw fp,12(sp) + 100dc7c: df000304 addi fp,sp,12 +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 100dc80: e03fff15 stw zero,-4(fp) +#endif + + + + if (OSRunning == OS_TRUE) { + 100dc84: d0a78343 ldbu r2,-25075(gp) + 100dc88: 10803fcc andi r2,r2,255 + 100dc8c: 10800058 cmpnei r2,r2,1 + 100dc90: 1000321e bne r2,zero,100dd5c +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 100dc94: 0005303a rdctl r2,status + 100dc98: e0bffe15 stw r2,-8(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 100dc9c: e0fffe17 ldw r3,-8(fp) + 100dca0: 00bfff84 movi r2,-2 + 100dca4: 1884703a and r2,r3,r2 + 100dca8: 1001703a wrctl status,r2 + + return context; + 100dcac: e0bffe17 ldw r2,-8(fp) + OS_ENTER_CRITICAL(); + 100dcb0: e0bfff15 stw r2,-4(fp) + if (OSIntNesting > 0) { /* Prevent OSIntNesting from wrapping */ + 100dcb4: d0a79103 ldbu r2,-25020(gp) + 100dcb8: 10803fcc andi r2,r2,255 + 100dcbc: 1005003a cmpeq r2,r2,zero + 100dcc0: 1000031e bne r2,zero,100dcd0 + OSIntNesting--; + 100dcc4: d0a79103 ldbu r2,-25020(gp) + 100dcc8: 10bfffc4 addi r2,r2,-1 + 100dccc: d0a79105 stb r2,-25020(gp) + } + if (OSIntNesting == 0) { /* Reschedule only if all ISRs complete ... */ + 100dcd0: d0a79103 ldbu r2,-25020(gp) + 100dcd4: 10803fcc andi r2,r2,255 + 100dcd8: 1004c03a cmpne r2,r2,zero + 100dcdc: 10001b1e bne r2,zero,100dd4c + if (OSLockNesting == 0) { /* ... and not locked. */ + 100dce0: d0a78303 ldbu r2,-25076(gp) + 100dce4: 10803fcc andi r2,r2,255 + 100dce8: 1004c03a cmpne r2,r2,zero + 100dcec: 1000171e bne r2,zero,100dd4c + OS_SchedNew(); + 100dcf0: 100ed8c0 call 100ed8c + if (OSPrioHighRdy != OSPrioCur) { /* No Ctx Sw if current task is highest rdy */ + 100dcf4: d0a78503 ldbu r2,-25068(gp) + 100dcf8: d0e78543 ldbu r3,-25067(gp) + 100dcfc: 11003fcc andi r4,r2,255 + 100dd00: 18803fcc andi r2,r3,255 + 100dd04: 20801126 beq r4,r2,100dd4c + OSTCBHighRdy = OSTCBPrioTbl[OSPrioHighRdy]; + 100dd08: d0a78503 ldbu r2,-25068(gp) + 100dd0c: 10803fcc andi r2,r2,255 + 100dd10: 00c040b4 movhi r3,258 + 100dd14: 18d9a904 addi r3,r3,26276 + 100dd18: 1085883a add r2,r2,r2 + 100dd1c: 1085883a add r2,r2,r2 + 100dd20: 10c5883a add r2,r2,r3 + 100dd24: 10800017 ldw r2,0(r2) + 100dd28: d0a78d15 stw r2,-25036(gp) +#if OS_TASK_PROFILE_EN > 0 + OSTCBHighRdy->OSTCBCtxSwCtr++; /* Inc. # of context switches to this task */ + 100dd2c: d0e78d17 ldw r3,-25036(gp) + 100dd30: 18800e17 ldw r2,56(r3) + 100dd34: 10800044 addi r2,r2,1 + 100dd38: 18800e15 stw r2,56(r3) +#endif + OSCtxSwCtr++; /* Keep track of the number of ctx switches */ + 100dd3c: d0a78817 ldw r2,-25056(gp) + 100dd40: 10800044 addi r2,r2,1 + 100dd44: d0a78815 stw r2,-25056(gp) + OSIntCtxSw(); /* Perform interrupt level ctx switch */ + 100dd48: 101802c0 call 101802c + 100dd4c: e0bfff17 ldw r2,-4(fp) + 100dd50: e0bffd15 stw r2,-12(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 100dd54: e0bffd17 ldw r2,-12(fp) + 100dd58: 1001703a wrctl status,r2 + } + } + } + OS_EXIT_CRITICAL(); + } +} + 100dd5c: e037883a mov sp,fp + 100dd60: dfc00117 ldw ra,4(sp) + 100dd64: df000017 ldw fp,0(sp) + 100dd68: dec00204 addi sp,sp,8 + 100dd6c: f800283a ret + +0100dd70 : +********************************************************************************************************* +*/ + +#if OS_SCHED_LOCK_EN > 0 +void OSSchedLock (void) +{ + 100dd70: defffc04 addi sp,sp,-16 + 100dd74: df000315 stw fp,12(sp) + 100dd78: df000304 addi fp,sp,12 +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 100dd7c: e03fff15 stw zero,-4(fp) +#endif + + + + if (OSRunning == OS_TRUE) { /* Make sure multitasking is running */ + 100dd80: d0a78343 ldbu r2,-25075(gp) + 100dd84: 10803fcc andi r2,r2,255 + 100dd88: 10800058 cmpnei r2,r2,1 + 100dd8c: 1000171e bne r2,zero,100ddec +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 100dd90: 0005303a rdctl r2,status + 100dd94: e0bffe15 stw r2,-8(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 100dd98: e0fffe17 ldw r3,-8(fp) + 100dd9c: 00bfff84 movi r2,-2 + 100dda0: 1884703a and r2,r3,r2 + 100dda4: 1001703a wrctl status,r2 + + return context; + 100dda8: e0bffe17 ldw r2,-8(fp) + OS_ENTER_CRITICAL(); + 100ddac: e0bfff15 stw r2,-4(fp) + if (OSIntNesting == 0) { /* Can't call from an ISR */ + 100ddb0: d0a79103 ldbu r2,-25020(gp) + 100ddb4: 10803fcc andi r2,r2,255 + 100ddb8: 1004c03a cmpne r2,r2,zero + 100ddbc: 1000071e bne r2,zero,100dddc + if (OSLockNesting < 255u) { /* Prevent OSLockNesting from wrapping back to 0 */ + 100ddc0: d0a78303 ldbu r2,-25076(gp) + 100ddc4: 10803fcc andi r2,r2,255 + 100ddc8: 10803fe0 cmpeqi r2,r2,255 + 100ddcc: 1000031e bne r2,zero,100dddc + OSLockNesting++; /* Increment lock nesting level */ + 100ddd0: d0a78303 ldbu r2,-25076(gp) + 100ddd4: 10800044 addi r2,r2,1 + 100ddd8: d0a78305 stb r2,-25076(gp) + 100dddc: e0bfff17 ldw r2,-4(fp) + 100dde0: e0bffd15 stw r2,-12(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 100dde4: e0bffd17 ldw r2,-12(fp) + 100dde8: 1001703a wrctl status,r2 + } + } + OS_EXIT_CRITICAL(); + } +} + 100ddec: e037883a mov sp,fp + 100ddf0: df000017 ldw fp,0(sp) + 100ddf4: dec00104 addi sp,sp,4 + 100ddf8: f800283a ret + +0100ddfc : +********************************************************************************************************* +*/ + +#if OS_SCHED_LOCK_EN > 0 +void OSSchedUnlock (void) +{ + 100ddfc: defff804 addi sp,sp,-32 + 100de00: dfc00715 stw ra,28(sp) + 100de04: df000615 stw fp,24(sp) + 100de08: df000604 addi fp,sp,24 +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 100de0c: e03fff15 stw zero,-4(fp) +#endif + + + + if (OSRunning == OS_TRUE) { /* Make sure multitasking is running */ + 100de10: d0a78343 ldbu r2,-25075(gp) + 100de14: 10803fcc andi r2,r2,255 + 100de18: 10800058 cmpnei r2,r2,1 + 100de1c: 10002b1e bne r2,zero,100decc +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 100de20: 0005303a rdctl r2,status + 100de24: e0bffe15 stw r2,-8(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 100de28: e0fffe17 ldw r3,-8(fp) + 100de2c: 00bfff84 movi r2,-2 + 100de30: 1884703a and r2,r3,r2 + 100de34: 1001703a wrctl status,r2 + + return context; + 100de38: e0bffe17 ldw r2,-8(fp) + OS_ENTER_CRITICAL(); + 100de3c: e0bfff15 stw r2,-4(fp) + if (OSLockNesting > 0) { /* Do not decrement if already 0 */ + 100de40: d0a78303 ldbu r2,-25076(gp) + 100de44: 10803fcc andi r2,r2,255 + 100de48: 1005003a cmpeq r2,r2,zero + 100de4c: 10001b1e bne r2,zero,100debc + OSLockNesting--; /* Decrement lock nesting level */ + 100de50: d0a78303 ldbu r2,-25076(gp) + 100de54: 10bfffc4 addi r2,r2,-1 + 100de58: d0a78305 stb r2,-25076(gp) + if (OSLockNesting == 0) { /* See if scheduler is enabled and ... */ + 100de5c: d0a78303 ldbu r2,-25076(gp) + 100de60: 10803fcc andi r2,r2,255 + 100de64: 1004c03a cmpne r2,r2,zero + 100de68: 10000f1e bne r2,zero,100dea8 + if (OSIntNesting == 0) { /* ... not in an ISR */ + 100de6c: d0a79103 ldbu r2,-25020(gp) + 100de70: 10803fcc andi r2,r2,255 + 100de74: 1004c03a cmpne r2,r2,zero + 100de78: 1000061e bne r2,zero,100de94 + 100de7c: e0bfff17 ldw r2,-4(fp) + 100de80: e0bffd15 stw r2,-12(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 100de84: e0bffd17 ldw r2,-12(fp) + 100de88: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + OS_Sched(); /* See if a HPT is ready */ + 100de8c: 100ecb80 call 100ecb8 + 100de90: 00000e06 br 100decc + 100de94: e0bfff17 ldw r2,-4(fp) + 100de98: e0bffc15 stw r2,-16(fp) + 100de9c: e0bffc17 ldw r2,-16(fp) + 100dea0: 1001703a wrctl status,r2 + 100dea4: 00000906 br 100decc + 100dea8: e0bfff17 ldw r2,-4(fp) + 100deac: e0bffb15 stw r2,-20(fp) + 100deb0: e0bffb17 ldw r2,-20(fp) + 100deb4: 1001703a wrctl status,r2 + 100deb8: 00000406 br 100decc + 100debc: e0bfff17 ldw r2,-4(fp) + 100dec0: e0bffa15 stw r2,-24(fp) + 100dec4: e0bffa17 ldw r2,-24(fp) + 100dec8: 1001703a wrctl status,r2 + } + } else { + OS_EXIT_CRITICAL(); + } + } +} + 100decc: e037883a mov sp,fp + 100ded0: dfc00117 ldw ra,4(sp) + 100ded4: df000017 ldw fp,0(sp) + 100ded8: dec00204 addi sp,sp,8 + 100dedc: f800283a ret + +0100dee0 : +* d_ Execute the task. +********************************************************************************************************* +*/ + +void OSStart (void) +{ + 100dee0: defffe04 addi sp,sp,-8 + 100dee4: dfc00115 stw ra,4(sp) + 100dee8: df000015 stw fp,0(sp) + 100deec: d839883a mov fp,sp + if (OSRunning == OS_FALSE) { + 100def0: d0a78343 ldbu r2,-25075(gp) + 100def4: 10803fcc andi r2,r2,255 + 100def8: 1004c03a cmpne r2,r2,zero + 100defc: 10000f1e bne r2,zero,100df3c + OS_SchedNew(); /* Find highest priority's task priority number */ + 100df00: 100ed8c0 call 100ed8c + OSPrioCur = OSPrioHighRdy; + 100df04: d0a78503 ldbu r2,-25068(gp) + 100df08: d0a78545 stb r2,-25067(gp) + OSTCBHighRdy = OSTCBPrioTbl[OSPrioHighRdy]; /* Point to highest priority task ready to run */ + 100df0c: d0a78503 ldbu r2,-25068(gp) + 100df10: 10803fcc andi r2,r2,255 + 100df14: 00c040b4 movhi r3,258 + 100df18: 18d9a904 addi r3,r3,26276 + 100df1c: 1085883a add r2,r2,r2 + 100df20: 1085883a add r2,r2,r2 + 100df24: 10c5883a add r2,r2,r3 + 100df28: 10800017 ldw r2,0(r2) + 100df2c: d0a78d15 stw r2,-25036(gp) + OSTCBCur = OSTCBHighRdy; + 100df30: d0a78d17 ldw r2,-25036(gp) + 100df34: d0a79215 stw r2,-25016(gp) + OSStartHighRdy(); /* Execute target specific code to start task */ + 100df38: 10180b80 call 10180b8 + } +} + 100df3c: e037883a mov sp,fp + 100df40: dfc00117 ldw ra,4(sp) + 100df44: df000017 ldw fp,0(sp) + 100df48: dec00204 addi sp,sp,8 + 100df4c: f800283a ret + +0100df50 : +********************************************************************************************************* +*/ + +#if OS_TASK_STAT_EN > 0 +void OSStatInit (void) +{ + 100df50: defff904 addi sp,sp,-28 + 100df54: dfc00615 stw ra,24(sp) + 100df58: df000515 stw fp,20(sp) + 100df5c: df000504 addi fp,sp,20 +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 100df60: e03fff15 stw zero,-4(fp) +#endif + + + + OSTimeDly(2); /* Synchronize with clock tick */ + 100df64: 01000084 movi r4,2 + 100df68: 1014fac0 call 1014fac +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 100df6c: 0005303a rdctl r2,status + 100df70: e0bffe15 stw r2,-8(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 100df74: e0fffe17 ldw r3,-8(fp) + 100df78: 00bfff84 movi r2,-2 + 100df7c: 1884703a and r2,r3,r2 + 100df80: 1001703a wrctl status,r2 + + return context; + 100df84: e0bffe17 ldw r2,-8(fp) + OS_ENTER_CRITICAL(); + 100df88: e0bfff15 stw r2,-4(fp) + OSIdleCtr = 0L; /* Clear idle counter */ + 100df8c: d0278415 stw zero,-25072(gp) + 100df90: e0bfff17 ldw r2,-4(fp) + 100df94: e0bffd15 stw r2,-12(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 100df98: e0bffd17 ldw r2,-12(fp) + 100df9c: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + OSTimeDly(OS_TICKS_PER_SEC / 10); /* Determine MAX. idle counter value for 1/10 second */ + 100dfa0: 01001904 movi r4,100 + 100dfa4: 1014fac0 call 1014fac +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 100dfa8: 0005303a rdctl r2,status + 100dfac: e0bffc15 stw r2,-16(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 100dfb0: e0fffc17 ldw r3,-16(fp) + 100dfb4: 00bfff84 movi r2,-2 + 100dfb8: 1884703a and r2,r3,r2 + 100dfbc: 1001703a wrctl status,r2 + + return context; + 100dfc0: e0bffc17 ldw r2,-16(fp) + OS_ENTER_CRITICAL(); + 100dfc4: e0bfff15 stw r2,-4(fp) + OSIdleCtrMax = OSIdleCtr; /* Store maximum idle counter count in 1/10 second */ + 100dfc8: d0a78417 ldw r2,-25072(gp) + 100dfcc: d0a78915 stw r2,-25052(gp) + OSStatRdy = OS_TRUE; + 100dfd0: 00800044 movi r2,1 + 100dfd4: d0a79505 stb r2,-25004(gp) + 100dfd8: e0bfff17 ldw r2,-4(fp) + 100dfdc: e0bffb15 stw r2,-20(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 100dfe0: e0bffb17 ldw r2,-20(fp) + 100dfe4: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); +} + 100dfe8: e037883a mov sp,fp + 100dfec: dfc00117 ldw ra,4(sp) + 100dff0: df000017 ldw fp,0(sp) + 100dff4: dec00204 addi sp,sp,8 + 100dff8: f800283a ret + +0100dffc : +* Returns : none +********************************************************************************************************* +*/ + +void OSTimeTick (void) +{ + 100dffc: defff604 addi sp,sp,-40 + 100e000: dfc00915 stw ra,36(sp) + 100e004: df000815 stw fp,32(sp) + 100e008: df000804 addi fp,sp,32 + OS_TCB *ptcb; +#if OS_TICK_STEP_EN > 0 + BOOLEAN step; +#endif +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 100e00c: e03ffc15 stw zero,-16(fp) +#endif + + + +#if OS_TIME_TICK_HOOK_EN > 0 + OSTimeTickHook(); /* Call user definable hook */ + 100e010: 10184840 call 1018484 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 100e014: 0005303a rdctl r2,status + 100e018: e0bffb15 stw r2,-20(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 100e01c: e0fffb17 ldw r3,-20(fp) + 100e020: 00bfff84 movi r2,-2 + 100e024: 1884703a and r2,r3,r2 + 100e028: 1001703a wrctl status,r2 + + return context; + 100e02c: e0bffb17 ldw r2,-20(fp) +#endif +#if OS_TIME_GET_SET_EN > 0 + OS_ENTER_CRITICAL(); /* Update the 32-bit tick counter */ + 100e030: e0bffc15 stw r2,-16(fp) + OSTime++; + 100e034: d0a79317 ldw r2,-25012(gp) + 100e038: 10800044 addi r2,r2,1 + 100e03c: d0a79315 stw r2,-25012(gp) + 100e040: e0bffc17 ldw r2,-16(fp) + 100e044: e0bffa15 stw r2,-24(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 100e048: e0bffa17 ldw r2,-24(fp) + 100e04c: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); +#endif + if (OSRunning == OS_TRUE) { + 100e050: d0a78343 ldbu r2,-25075(gp) + 100e054: 10803fcc andi r2,r2,255 + 100e058: 10800058 cmpnei r2,r2,1 + 100e05c: 1000721e bne r2,zero,100e228 +#if OS_TICK_STEP_EN > 0 + switch (OSTickStepState) { /* Determine whether we need to process a tick */ + 100e060: d0a78703 ldbu r2,-25060(gp) + 100e064: 10803fcc andi r2,r2,255 + 100e068: e0bfff15 stw r2,-4(fp) + 100e06c: e0ffff17 ldw r3,-4(fp) + 100e070: 18800060 cmpeqi r2,r3,1 + 100e074: 10000a1e bne r2,zero,100e0a0 + 100e078: e0ffff17 ldw r3,-4(fp) + 100e07c: 188000a0 cmpeqi r2,r3,2 + 100e080: 1000091e bne r2,zero,100e0a8 + 100e084: e0ffff17 ldw r3,-4(fp) + 100e088: 1805003a cmpeq r2,r3,zero + 100e08c: 1000011e bne r2,zero,100e094 + 100e090: 00000a06 br 100e0bc + case OS_TICK_STEP_DIS: /* Yes, stepping is disabled */ + step = OS_TRUE; + 100e094: 00800044 movi r2,1 + 100e098: e0bffd05 stb r2,-12(fp) + break; + 100e09c: 00000a06 br 100e0c8 + + case OS_TICK_STEP_WAIT: /* No, waiting for uC/OS-View to set ... */ + step = OS_FALSE; /* .. OSTickStepState to OS_TICK_STEP_ONCE */ + 100e0a0: e03ffd05 stb zero,-12(fp) + break; + 100e0a4: 00000806 br 100e0c8 + + case OS_TICK_STEP_ONCE: /* Yes, process tick once and wait for next ... */ + step = OS_TRUE; /* ... step command from uC/OS-View */ + 100e0a8: 00800044 movi r2,1 + 100e0ac: e0bffd05 stb r2,-12(fp) + OSTickStepState = OS_TICK_STEP_WAIT; + 100e0b0: 00800044 movi r2,1 + 100e0b4: d0a78705 stb r2,-25060(gp) + break; + 100e0b8: 00000306 br 100e0c8 + + default: /* Invalid case, correct situation */ + step = OS_TRUE; + 100e0bc: 00800044 movi r2,1 + 100e0c0: e0bffd05 stb r2,-12(fp) + OSTickStepState = OS_TICK_STEP_DIS; + 100e0c4: d0278705 stb zero,-25060(gp) + break; + } + if (step == OS_FALSE) { /* Return if waiting for step command */ + 100e0c8: e0bffd03 ldbu r2,-12(fp) + 100e0cc: 1005003a cmpeq r2,r2,zero + 100e0d0: 1000551e bne r2,zero,100e228 + return; + } +#endif + ptcb = OSTCBList; /* Point at first TCB in TCB list */ + 100e0d4: d0a78617 ldw r2,-25064(gp) + 100e0d8: e0bffe15 stw r2,-8(fp) + while (ptcb->OSTCBPrio != OS_TASK_IDLE_PRIO) { /* Go through all TCBs in TCB list */ + 100e0dc: 00004d06 br 100e214 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 100e0e0: 0005303a rdctl r2,status + 100e0e4: e0bff915 stw r2,-28(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 100e0e8: e0fff917 ldw r3,-28(fp) + 100e0ec: 00bfff84 movi r2,-2 + 100e0f0: 1884703a and r2,r3,r2 + 100e0f4: 1001703a wrctl status,r2 + + return context; + 100e0f8: e0bff917 ldw r2,-28(fp) + OS_ENTER_CRITICAL(); + 100e0fc: e0bffc15 stw r2,-16(fp) + if (ptcb->OSTCBDly != 0) { /* No, Delayed or waiting for event with TO */ + 100e100: e0bffe17 ldw r2,-8(fp) + 100e104: 10800b8b ldhu r2,46(r2) + 100e108: 10bfffcc andi r2,r2,65535 + 100e10c: 1005003a cmpeq r2,r2,zero + 100e110: 1000391e bne r2,zero,100e1f8 + if (--ptcb->OSTCBDly == 0) { /* Decrement nbr of ticks to end of delay */ + 100e114: e0bffe17 ldw r2,-8(fp) + 100e118: 10800b8b ldhu r2,46(r2) + 100e11c: 10bfffc4 addi r2,r2,-1 + 100e120: 1007883a mov r3,r2 + 100e124: e0bffe17 ldw r2,-8(fp) + 100e128: 10c00b8d sth r3,46(r2) + 100e12c: e0bffe17 ldw r2,-8(fp) + 100e130: 10800b8b ldhu r2,46(r2) + 100e134: 10bfffcc andi r2,r2,65535 + 100e138: 1004c03a cmpne r2,r2,zero + 100e13c: 10002e1e bne r2,zero,100e1f8 + /* Check for timeout */ + if ((ptcb->OSTCBStat & OS_STAT_PEND_ANY) != OS_STAT_RDY) { + 100e140: e0bffe17 ldw r2,-8(fp) + 100e144: 10800c03 ldbu r2,48(r2) + 100e148: 10803fcc andi r2,r2,255 + 100e14c: 10800dcc andi r2,r2,55 + 100e150: 1005003a cmpeq r2,r2,zero + 100e154: 10000b1e bne r2,zero,100e184 + ptcb->OSTCBStat &= ~(INT8U)OS_STAT_PEND_ANY; /* Yes, Clear status flag */ + 100e158: e0bffe17 ldw r2,-8(fp) + 100e15c: 10c00c03 ldbu r3,48(r2) + 100e160: 00bff204 movi r2,-56 + 100e164: 1884703a and r2,r3,r2 + 100e168: 1007883a mov r3,r2 + 100e16c: e0bffe17 ldw r2,-8(fp) + 100e170: 10c00c05 stb r3,48(r2) + ptcb->OSTCBStatPend = OS_STAT_PEND_TO; /* Indicate PEND timeout */ + 100e174: e0fffe17 ldw r3,-8(fp) + 100e178: 00800044 movi r2,1 + 100e17c: 18800c45 stb r2,49(r3) + 100e180: 00000206 br 100e18c + } else { + ptcb->OSTCBStatPend = OS_STAT_PEND_OK; + 100e184: e0bffe17 ldw r2,-8(fp) + 100e188: 10000c45 stb zero,49(r2) + } + + if ((ptcb->OSTCBStat & OS_STAT_SUSPEND) == OS_STAT_RDY) { /* Is task suspended? */ + 100e18c: e0bffe17 ldw r2,-8(fp) + 100e190: 10800c03 ldbu r2,48(r2) + 100e194: 10803fcc andi r2,r2,255 + 100e198: 1080020c andi r2,r2,8 + 100e19c: 1004c03a cmpne r2,r2,zero + 100e1a0: 1000151e bne r2,zero,100e1f8 + OSRdyGrp |= ptcb->OSTCBBitY; /* No, Make ready */ + 100e1a4: e0bffe17 ldw r2,-8(fp) + 100e1a8: 10c00d83 ldbu r3,54(r2) + 100e1ac: d0a78f03 ldbu r2,-25028(gp) + 100e1b0: 1884b03a or r2,r3,r2 + 100e1b4: d0a78f05 stb r2,-25028(gp) + OSRdyTbl[ptcb->OSTCBY] |= ptcb->OSTCBBitX; + 100e1b8: e0bffe17 ldw r2,-8(fp) + 100e1bc: 10800d03 ldbu r2,52(r2) + 100e1c0: 11003fcc andi r4,r2,255 + 100e1c4: e0bffe17 ldw r2,-8(fp) + 100e1c8: 10800d03 ldbu r2,52(r2) + 100e1cc: 10c03fcc andi r3,r2,255 + 100e1d0: d0a78f44 addi r2,gp,-25027 + 100e1d4: 1885883a add r2,r3,r2 + 100e1d8: 10c00003 ldbu r3,0(r2) + 100e1dc: e0bffe17 ldw r2,-8(fp) + 100e1e0: 10800d43 ldbu r2,53(r2) + 100e1e4: 1884b03a or r2,r3,r2 + 100e1e8: 1007883a mov r3,r2 + 100e1ec: d0a78f44 addi r2,gp,-25027 + 100e1f0: 2085883a add r2,r4,r2 + 100e1f4: 10c00005 stb r3,0(r2) + } + } + } + ptcb = ptcb->OSTCBNext; /* Point at next TCB in TCB list */ + 100e1f8: e0bffe17 ldw r2,-8(fp) + 100e1fc: 10800517 ldw r2,20(r2) + 100e200: e0bffe15 stw r2,-8(fp) + 100e204: e0bffc17 ldw r2,-16(fp) + 100e208: e0bff815 stw r2,-32(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 100e20c: e0bff817 ldw r2,-32(fp) + 100e210: 1001703a wrctl status,r2 + if (step == OS_FALSE) { /* Return if waiting for step command */ + return; + } +#endif + ptcb = OSTCBList; /* Point at first TCB in TCB list */ + while (ptcb->OSTCBPrio != OS_TASK_IDLE_PRIO) { /* Go through all TCBs in TCB list */ + 100e214: e0bffe17 ldw r2,-8(fp) + 100e218: 10800c83 ldbu r2,50(r2) + 100e21c: 10803fcc andi r2,r2,255 + 100e220: 10800518 cmpnei r2,r2,20 + 100e224: 103fae1e bne r2,zero,100e0e0 + } + ptcb = ptcb->OSTCBNext; /* Point at next TCB in TCB list */ + OS_EXIT_CRITICAL(); + } + } +} + 100e228: e037883a mov sp,fp + 100e22c: dfc00117 ldw ra,4(sp) + 100e230: df000017 ldw fp,0(sp) + 100e234: dec00204 addi sp,sp,8 + 100e238: f800283a ret + +0100e23c : +* Returns : the version number of uC/OS-II multiplied by 100. +********************************************************************************************************* +*/ + +INT16U OSVersion (void) +{ + 100e23c: deffff04 addi sp,sp,-4 + 100e240: df000015 stw fp,0(sp) + 100e244: d839883a mov fp,sp + return (OS_VERSION); + 100e248: 00804784 movi r2,286 +} + 100e24c: e037883a mov sp,fp + 100e250: df000017 ldw fp,0(sp) + 100e254: dec00104 addi sp,sp,4 + 100e258: f800283a ret + +0100e25c : +********************************************************************************************************* +*/ + +#if OS_TASK_DEL_EN > 0 +void OS_Dummy (void) +{ + 100e25c: deffff04 addi sp,sp,-4 + 100e260: df000015 stw fp,0(sp) + 100e264: d839883a mov fp,sp +} + 100e268: e037883a mov sp,fp + 100e26c: df000017 ldw fp,0(sp) + 100e270: dec00104 addi sp,sp,4 + 100e274: f800283a ret + +0100e278 : +* Note : This function is INTERNAL to uC/OS-II and your application should not call it. +********************************************************************************************************* +*/ +#if (OS_EVENT_EN) +INT8U OS_EventTaskRdy (OS_EVENT *pevent, void *pmsg, INT8U msk, INT8U pend_stat) +{ + 100e278: defff804 addi sp,sp,-32 + 100e27c: dfc00715 stw ra,28(sp) + 100e280: df000615 stw fp,24(sp) + 100e284: df000604 addi fp,sp,24 + 100e288: e13ffc15 stw r4,-16(fp) + 100e28c: e17ffd15 stw r5,-12(fp) + 100e290: e1bffe05 stb r6,-8(fp) + 100e294: e1ffff05 stb r7,-4(fp) + INT16U *ptbl; +#endif + + +#if OS_LOWEST_PRIO <= 63 + y = OSUnMapTbl[pevent->OSEventGrp]; /* Find HPT waiting for message */ + 100e298: e0bffc17 ldw r2,-16(fp) + 100e29c: 10800283 ldbu r2,10(r2) + 100e2a0: 10c03fcc andi r3,r2,255 + 100e2a4: 008040b4 movhi r2,258 + 100e2a8: 10a43604 addi r2,r2,-28456 + 100e2ac: 10c5883a add r2,r2,r3 + 100e2b0: 10800003 ldbu r2,0(r2) + 100e2b4: e0bffa85 stb r2,-22(fp) + x = OSUnMapTbl[pevent->OSEventTbl[y]]; + 100e2b8: e0fffa83 ldbu r3,-22(fp) + 100e2bc: e0bffc17 ldw r2,-16(fp) + 100e2c0: 1885883a add r2,r3,r2 + 100e2c4: 10800204 addi r2,r2,8 + 100e2c8: 108000c3 ldbu r2,3(r2) + 100e2cc: 10c03fcc andi r3,r2,255 + 100e2d0: 008040b4 movhi r2,258 + 100e2d4: 10a43604 addi r2,r2,-28456 + 100e2d8: 10c5883a add r2,r2,r3 + 100e2dc: 10800003 ldbu r2,0(r2) + 100e2e0: e0bffa45 stb r2,-23(fp) + prio = (INT8U)((y << 3) + x); /* Find priority of task getting the msg */ + 100e2e4: e0bffa83 ldbu r2,-22(fp) + 100e2e8: 100490fa slli r2,r2,3 + 100e2ec: 1007883a mov r3,r2 + 100e2f0: e0bffa43 ldbu r2,-23(fp) + 100e2f4: 1885883a add r2,r3,r2 + 100e2f8: e0bffa05 stb r2,-24(fp) + x = OSUnMapTbl[(*ptbl >> 8) & 0xFF] + 8; + } + prio = (INT8U)((y << 4) + x); /* Find priority of task getting the msg */ +#endif + + ptcb = OSTCBPrioTbl[prio]; /* Point to this task's OS_TCB */ + 100e2fc: e0bffa03 ldbu r2,-24(fp) + 100e300: 00c040b4 movhi r3,258 + 100e304: 18d9a904 addi r3,r3,26276 + 100e308: 1085883a add r2,r2,r2 + 100e30c: 1085883a add r2,r2,r2 + 100e310: 10c5883a add r2,r2,r3 + 100e314: 10800017 ldw r2,0(r2) + 100e318: e0bffb15 stw r2,-20(fp) + ptcb->OSTCBDly = 0; /* Prevent OSTimeTick() from readying task */ + 100e31c: e0bffb17 ldw r2,-20(fp) + 100e320: 10000b8d sth zero,46(r2) +#if ((OS_Q_EN > 0) && (OS_MAX_QS > 0)) || (OS_MBOX_EN > 0) + ptcb->OSTCBMsg = pmsg; /* Send message directly to waiting task */ + 100e324: e0fffb17 ldw r3,-20(fp) + 100e328: e0bffd17 ldw r2,-12(fp) + 100e32c: 18800915 stw r2,36(r3) +#else + pmsg = pmsg; /* Prevent compiler warning if not used */ +#endif + ptcb->OSTCBStat &= ~msk; /* Clear bit associated with event type */ + 100e330: e0bffb17 ldw r2,-20(fp) + 100e334: 10800c03 ldbu r2,48(r2) + 100e338: 1007883a mov r3,r2 + 100e33c: e0bffe03 ldbu r2,-8(fp) + 100e340: 0084303a nor r2,zero,r2 + 100e344: 1884703a and r2,r3,r2 + 100e348: 1007883a mov r3,r2 + 100e34c: e0bffb17 ldw r2,-20(fp) + 100e350: 10c00c05 stb r3,48(r2) + ptcb->OSTCBStatPend = pend_stat; /* Set pend status of post or abort */ + 100e354: e0fffb17 ldw r3,-20(fp) + 100e358: e0bfff03 ldbu r2,-4(fp) + 100e35c: 18800c45 stb r2,49(r3) + /* See if task is ready (could be susp'd) */ + if ((ptcb->OSTCBStat & OS_STAT_SUSPEND) == OS_STAT_RDY) { + 100e360: e0bffb17 ldw r2,-20(fp) + 100e364: 10800c03 ldbu r2,48(r2) + 100e368: 10803fcc andi r2,r2,255 + 100e36c: 1080020c andi r2,r2,8 + 100e370: 1004c03a cmpne r2,r2,zero + 100e374: 1000111e bne r2,zero,100e3bc + OSRdyGrp |= ptcb->OSTCBBitY; /* Put task in the ready to run list */ + 100e378: e0bffb17 ldw r2,-20(fp) + 100e37c: 10c00d83 ldbu r3,54(r2) + 100e380: d0a78f03 ldbu r2,-25028(gp) + 100e384: 1884b03a or r2,r3,r2 + 100e388: d0a78f05 stb r2,-25028(gp) + OSRdyTbl[y] |= ptcb->OSTCBBitX; + 100e38c: e13ffa83 ldbu r4,-22(fp) + 100e390: e0fffa83 ldbu r3,-22(fp) + 100e394: d0a78f44 addi r2,gp,-25027 + 100e398: 1885883a add r2,r3,r2 + 100e39c: 10c00003 ldbu r3,0(r2) + 100e3a0: e0bffb17 ldw r2,-20(fp) + 100e3a4: 10800d43 ldbu r2,53(r2) + 100e3a8: 1884b03a or r2,r3,r2 + 100e3ac: 1007883a mov r3,r2 + 100e3b0: d0a78f44 addi r2,gp,-25027 + 100e3b4: 2085883a add r2,r4,r2 + 100e3b8: 10c00005 stb r3,0(r2) + } + + OS_EventTaskRemove(ptcb, pevent); /* Remove this task from event wait list */ + 100e3bc: e13ffb17 ldw r4,-20(fp) + 100e3c0: e17ffc17 ldw r5,-16(fp) + 100e3c4: 100e6700 call 100e670 +#if (OS_EVENT_MULTI_EN > 0) + if (ptcb->OSTCBEventMultiPtr != (OS_EVENT **)0) { /* Remove this task from events' wait lists */ + 100e3c8: e0bffb17 ldw r2,-20(fp) + 100e3cc: 10800817 ldw r2,32(r2) + 100e3d0: 1005003a cmpeq r2,r2,zero + 100e3d4: 1000071e bne r2,zero,100e3f4 + OS_EventTaskRemoveMulti(ptcb, ptcb->OSTCBEventMultiPtr); + 100e3d8: e0bffb17 ldw r2,-20(fp) + 100e3dc: 11400817 ldw r5,32(r2) + 100e3e0: e13ffb17 ldw r4,-20(fp) + 100e3e4: 100e7280 call 100e728 + ptcb->OSTCBEventPtr = (OS_EVENT *)pevent;/* Return event as first multi-pend event ready*/ + 100e3e8: e0fffb17 ldw r3,-20(fp) + 100e3ec: e0bffc17 ldw r2,-16(fp) + 100e3f0: 18800715 stw r2,28(r3) + } +#endif + + return (prio); + 100e3f4: e0bffa03 ldbu r2,-24(fp) +} + 100e3f8: e037883a mov sp,fp + 100e3fc: dfc00117 ldw ra,4(sp) + 100e400: df000017 ldw fp,0(sp) + 100e404: dec00204 addi sp,sp,8 + 100e408: f800283a ret + +0100e40c : +* Note : This function is INTERNAL to uC/OS-II and your application should not call it. +********************************************************************************************************* +*/ +#if (OS_EVENT_EN) +void OS_EventTaskWait (OS_EVENT *pevent) +{ + 100e40c: defffd04 addi sp,sp,-12 + 100e410: df000215 stw fp,8(sp) + 100e414: df000204 addi fp,sp,8 + 100e418: e13fff15 stw r4,-4(fp) + INT8U y; + + + OSTCBCur->OSTCBEventPtr = pevent; /* Store ptr to ECB in TCB */ + 100e41c: d0e79217 ldw r3,-25016(gp) + 100e420: e0bfff17 ldw r2,-4(fp) + 100e424: 18800715 stw r2,28(r3) + + pevent->OSEventTbl[OSTCBCur->OSTCBY] |= OSTCBCur->OSTCBBitX; /* Put task in waiting list */ + 100e428: d0a79217 ldw r2,-25016(gp) + 100e42c: 10800d03 ldbu r2,52(r2) + 100e430: 11003fcc andi r4,r2,255 + 100e434: d0a79217 ldw r2,-25016(gp) + 100e438: 10800d03 ldbu r2,52(r2) + 100e43c: 10c03fcc andi r3,r2,255 + 100e440: e0bfff17 ldw r2,-4(fp) + 100e444: 1885883a add r2,r3,r2 + 100e448: 10800204 addi r2,r2,8 + 100e44c: 10c000c3 ldbu r3,3(r2) + 100e450: d0a79217 ldw r2,-25016(gp) + 100e454: 10800d43 ldbu r2,53(r2) + 100e458: 1884b03a or r2,r3,r2 + 100e45c: 1007883a mov r3,r2 + 100e460: e0bfff17 ldw r2,-4(fp) + 100e464: 2085883a add r2,r4,r2 + 100e468: 10800204 addi r2,r2,8 + 100e46c: 10c000c5 stb r3,3(r2) + pevent->OSEventGrp |= OSTCBCur->OSTCBBitY; + 100e470: e0bfff17 ldw r2,-4(fp) + 100e474: 10c00283 ldbu r3,10(r2) + 100e478: d0a79217 ldw r2,-25016(gp) + 100e47c: 10800d83 ldbu r2,54(r2) + 100e480: 1884b03a or r2,r3,r2 + 100e484: 1007883a mov r3,r2 + 100e488: e0bfff17 ldw r2,-4(fp) + 100e48c: 10c00285 stb r3,10(r2) + + y = OSTCBCur->OSTCBY; /* Task no longer ready */ + 100e490: d0a79217 ldw r2,-25016(gp) + 100e494: 10800d03 ldbu r2,52(r2) + 100e498: e0bffe05 stb r2,-8(fp) + OSRdyTbl[y] &= ~OSTCBCur->OSTCBBitX; + 100e49c: e13ffe03 ldbu r4,-8(fp) + 100e4a0: e0fffe03 ldbu r3,-8(fp) + 100e4a4: d0a78f44 addi r2,gp,-25027 + 100e4a8: 1885883a add r2,r3,r2 + 100e4ac: 10800003 ldbu r2,0(r2) + 100e4b0: 1007883a mov r3,r2 + 100e4b4: d0a79217 ldw r2,-25016(gp) + 100e4b8: 10800d43 ldbu r2,53(r2) + 100e4bc: 0084303a nor r2,zero,r2 + 100e4c0: 1884703a and r2,r3,r2 + 100e4c4: 1007883a mov r3,r2 + 100e4c8: d0a78f44 addi r2,gp,-25027 + 100e4cc: 2085883a add r2,r4,r2 + 100e4d0: 10c00005 stb r3,0(r2) + if (OSRdyTbl[y] == 0) { + 100e4d4: e0fffe03 ldbu r3,-8(fp) + 100e4d8: d0a78f44 addi r2,gp,-25027 + 100e4dc: 1885883a add r2,r3,r2 + 100e4e0: 10800003 ldbu r2,0(r2) + 100e4e4: 10803fcc andi r2,r2,255 + 100e4e8: 1004c03a cmpne r2,r2,zero + 100e4ec: 1000071e bne r2,zero,100e50c + OSRdyGrp &= ~OSTCBCur->OSTCBBitY; /* Clear event grp bit if this was only task pending */ + 100e4f0: d0a79217 ldw r2,-25016(gp) + 100e4f4: 10800d83 ldbu r2,54(r2) + 100e4f8: 0084303a nor r2,zero,r2 + 100e4fc: 1007883a mov r3,r2 + 100e500: d0a78f03 ldbu r2,-25028(gp) + 100e504: 1884703a and r2,r3,r2 + 100e508: d0a78f05 stb r2,-25028(gp) + } +} + 100e50c: e037883a mov sp,fp + 100e510: df000017 ldw fp,0(sp) + 100e514: dec00104 addi sp,sp,4 + 100e518: f800283a ret + +0100e51c : +* Note : This function is INTERNAL to uC/OS-II and your application should not call it. +********************************************************************************************************* +*/ +#if ((OS_EVENT_EN) && (OS_EVENT_MULTI_EN > 0)) +void OS_EventTaskWaitMulti (OS_EVENT **pevents_wait) +{ + 100e51c: defffb04 addi sp,sp,-20 + 100e520: df000415 stw fp,16(sp) + 100e524: df000404 addi fp,sp,16 + 100e528: e13fff15 stw r4,-4(fp) + OS_EVENT **pevents; + OS_EVENT *pevent; + INT8U y; + + + OSTCBCur->OSTCBEventPtr = (OS_EVENT *)0; + 100e52c: d0a79217 ldw r2,-25016(gp) + 100e530: 10000715 stw zero,28(r2) + OSTCBCur->OSTCBEventMultiPtr = (OS_EVENT **)pevents_wait; /* Store ptr to ECBs in TCB */ + 100e534: d0e79217 ldw r3,-25016(gp) + 100e538: e0bfff17 ldw r2,-4(fp) + 100e53c: 18800815 stw r2,32(r3) + + pevents = pevents_wait; + 100e540: e0bfff17 ldw r2,-4(fp) + 100e544: e0bffe15 stw r2,-8(fp) + pevent = *pevents; + 100e548: e0bffe17 ldw r2,-8(fp) + 100e54c: 10800017 ldw r2,0(r2) + 100e550: e0bffd15 stw r2,-12(fp) + while (pevent != (OS_EVENT *)0) { /* Put task in waiting lists */ + 100e554: 00002006 br 100e5d8 + pevent->OSEventTbl[OSTCBCur->OSTCBY] |= OSTCBCur->OSTCBBitX; + 100e558: d0a79217 ldw r2,-25016(gp) + 100e55c: 10800d03 ldbu r2,52(r2) + 100e560: 11003fcc andi r4,r2,255 + 100e564: d0a79217 ldw r2,-25016(gp) + 100e568: 10800d03 ldbu r2,52(r2) + 100e56c: 10c03fcc andi r3,r2,255 + 100e570: e0bffd17 ldw r2,-12(fp) + 100e574: 1885883a add r2,r3,r2 + 100e578: 10800204 addi r2,r2,8 + 100e57c: 10c000c3 ldbu r3,3(r2) + 100e580: d0a79217 ldw r2,-25016(gp) + 100e584: 10800d43 ldbu r2,53(r2) + 100e588: 1884b03a or r2,r3,r2 + 100e58c: 1007883a mov r3,r2 + 100e590: e0bffd17 ldw r2,-12(fp) + 100e594: 2085883a add r2,r4,r2 + 100e598: 10800204 addi r2,r2,8 + 100e59c: 10c000c5 stb r3,3(r2) + pevent->OSEventGrp |= OSTCBCur->OSTCBBitY; + 100e5a0: e0bffd17 ldw r2,-12(fp) + 100e5a4: 10c00283 ldbu r3,10(r2) + 100e5a8: d0a79217 ldw r2,-25016(gp) + 100e5ac: 10800d83 ldbu r2,54(r2) + 100e5b0: 1884b03a or r2,r3,r2 + 100e5b4: 1007883a mov r3,r2 + 100e5b8: e0bffd17 ldw r2,-12(fp) + 100e5bc: 10c00285 stb r3,10(r2) + pevents++; + 100e5c0: e0bffe17 ldw r2,-8(fp) + 100e5c4: 10800104 addi r2,r2,4 + 100e5c8: e0bffe15 stw r2,-8(fp) + pevent = *pevents; + 100e5cc: e0bffe17 ldw r2,-8(fp) + 100e5d0: 10800017 ldw r2,0(r2) + 100e5d4: e0bffd15 stw r2,-12(fp) + OSTCBCur->OSTCBEventPtr = (OS_EVENT *)0; + OSTCBCur->OSTCBEventMultiPtr = (OS_EVENT **)pevents_wait; /* Store ptr to ECBs in TCB */ + + pevents = pevents_wait; + pevent = *pevents; + while (pevent != (OS_EVENT *)0) { /* Put task in waiting lists */ + 100e5d8: e0bffd17 ldw r2,-12(fp) + 100e5dc: 1004c03a cmpne r2,r2,zero + 100e5e0: 103fdd1e bne r2,zero,100e558 + pevent->OSEventGrp |= OSTCBCur->OSTCBBitY; + pevents++; + pevent = *pevents; + } + + y = OSTCBCur->OSTCBY; /* Task no longer ready */ + 100e5e4: d0a79217 ldw r2,-25016(gp) + 100e5e8: 10800d03 ldbu r2,52(r2) + 100e5ec: e0bffc05 stb r2,-16(fp) + OSRdyTbl[y] &= ~OSTCBCur->OSTCBBitX; + 100e5f0: e13ffc03 ldbu r4,-16(fp) + 100e5f4: e0fffc03 ldbu r3,-16(fp) + 100e5f8: d0a78f44 addi r2,gp,-25027 + 100e5fc: 1885883a add r2,r3,r2 + 100e600: 10800003 ldbu r2,0(r2) + 100e604: 1007883a mov r3,r2 + 100e608: d0a79217 ldw r2,-25016(gp) + 100e60c: 10800d43 ldbu r2,53(r2) + 100e610: 0084303a nor r2,zero,r2 + 100e614: 1884703a and r2,r3,r2 + 100e618: 1007883a mov r3,r2 + 100e61c: d0a78f44 addi r2,gp,-25027 + 100e620: 2085883a add r2,r4,r2 + 100e624: 10c00005 stb r3,0(r2) + if (OSRdyTbl[y] == 0) { + 100e628: e0fffc03 ldbu r3,-16(fp) + 100e62c: d0a78f44 addi r2,gp,-25027 + 100e630: 1885883a add r2,r3,r2 + 100e634: 10800003 ldbu r2,0(r2) + 100e638: 10803fcc andi r2,r2,255 + 100e63c: 1004c03a cmpne r2,r2,zero + 100e640: 1000071e bne r2,zero,100e660 + OSRdyGrp &= ~OSTCBCur->OSTCBBitY; /* Clear event grp bit if this was only task pending */ + 100e644: d0a79217 ldw r2,-25016(gp) + 100e648: 10800d83 ldbu r2,54(r2) + 100e64c: 0084303a nor r2,zero,r2 + 100e650: 1007883a mov r3,r2 + 100e654: d0a78f03 ldbu r2,-25028(gp) + 100e658: 1884703a and r2,r3,r2 + 100e65c: d0a78f05 stb r2,-25028(gp) + } +} + 100e660: e037883a mov sp,fp + 100e664: df000017 ldw fp,0(sp) + 100e668: dec00104 addi sp,sp,4 + 100e66c: f800283a ret + +0100e670 : +********************************************************************************************************* +*/ +#if (OS_EVENT_EN) +void OS_EventTaskRemove (OS_TCB *ptcb, + OS_EVENT *pevent) +{ + 100e670: defffc04 addi sp,sp,-16 + 100e674: df000315 stw fp,12(sp) + 100e678: df000304 addi fp,sp,12 + 100e67c: e13ffe15 stw r4,-8(fp) + 100e680: e17fff15 stw r5,-4(fp) + INT8U y; + + + y = ptcb->OSTCBY; + 100e684: e0bffe17 ldw r2,-8(fp) + 100e688: 10800d03 ldbu r2,52(r2) + 100e68c: e0bffd05 stb r2,-12(fp) + pevent->OSEventTbl[y] &= ~ptcb->OSTCBBitX; /* Remove task from wait list */ + 100e690: e13ffd03 ldbu r4,-12(fp) + 100e694: e0fffd03 ldbu r3,-12(fp) + 100e698: e0bfff17 ldw r2,-4(fp) + 100e69c: 1885883a add r2,r3,r2 + 100e6a0: 10800204 addi r2,r2,8 + 100e6a4: 108000c3 ldbu r2,3(r2) + 100e6a8: 1007883a mov r3,r2 + 100e6ac: e0bffe17 ldw r2,-8(fp) + 100e6b0: 10800d43 ldbu r2,53(r2) + 100e6b4: 0084303a nor r2,zero,r2 + 100e6b8: 1884703a and r2,r3,r2 + 100e6bc: 1007883a mov r3,r2 + 100e6c0: e0bfff17 ldw r2,-4(fp) + 100e6c4: 2085883a add r2,r4,r2 + 100e6c8: 10800204 addi r2,r2,8 + 100e6cc: 10c000c5 stb r3,3(r2) + if (pevent->OSEventTbl[y] == 0) { + 100e6d0: e0fffd03 ldbu r3,-12(fp) + 100e6d4: e0bfff17 ldw r2,-4(fp) + 100e6d8: 1885883a add r2,r3,r2 + 100e6dc: 10800204 addi r2,r2,8 + 100e6e0: 108000c3 ldbu r2,3(r2) + 100e6e4: 10803fcc andi r2,r2,255 + 100e6e8: 1004c03a cmpne r2,r2,zero + 100e6ec: 10000a1e bne r2,zero,100e718 + pevent->OSEventGrp &= ~ptcb->OSTCBBitY; + 100e6f0: e0bfff17 ldw r2,-4(fp) + 100e6f4: 10800283 ldbu r2,10(r2) + 100e6f8: 1007883a mov r3,r2 + 100e6fc: e0bffe17 ldw r2,-8(fp) + 100e700: 10800d83 ldbu r2,54(r2) + 100e704: 0084303a nor r2,zero,r2 + 100e708: 1884703a and r2,r3,r2 + 100e70c: 1007883a mov r3,r2 + 100e710: e0bfff17 ldw r2,-4(fp) + 100e714: 10c00285 stb r3,10(r2) + } +} + 100e718: e037883a mov sp,fp + 100e71c: df000017 ldw fp,0(sp) + 100e720: dec00104 addi sp,sp,4 + 100e724: f800283a ret + +0100e728 : +********************************************************************************************************* +*/ +#if ((OS_EVENT_EN) && (OS_EVENT_MULTI_EN > 0)) +void OS_EventTaskRemoveMulti (OS_TCB *ptcb, + OS_EVENT **pevents_multi) +{ + 100e728: defffa04 addi sp,sp,-24 + 100e72c: df000515 stw fp,20(sp) + 100e730: df000504 addi fp,sp,20 + 100e734: e13ffe15 stw r4,-8(fp) + 100e738: e17fff15 stw r5,-4(fp) + INT16U bity; + INT16U bitx; +#endif + + + y = ptcb->OSTCBY; + 100e73c: e0bffe17 ldw r2,-8(fp) + 100e740: 10800d03 ldbu r2,52(r2) + 100e744: e0bffb85 stb r2,-18(fp) + bity = ptcb->OSTCBBitY; + 100e748: e0bffe17 ldw r2,-8(fp) + 100e74c: 10800d83 ldbu r2,54(r2) + 100e750: e0bffb45 stb r2,-19(fp) + bitx = ptcb->OSTCBBitX; + 100e754: e0bffe17 ldw r2,-8(fp) + 100e758: 10800d43 ldbu r2,53(r2) + 100e75c: e0bffb05 stb r2,-20(fp) + pevents = pevents_multi; + 100e760: e0bfff17 ldw r2,-4(fp) + 100e764: e0bffd15 stw r2,-12(fp) + pevent = *pevents; + 100e768: e0bffd17 ldw r2,-12(fp) + 100e76c: 10800017 ldw r2,0(r2) + 100e770: e0bffc15 stw r2,-16(fp) + while (pevent != (OS_EVENT *)0) { /* Remove task from all events' wait lists */ + 100e774: 00002606 br 100e810 + pevent->OSEventTbl[y] &= ~bitx; + 100e778: e13ffb83 ldbu r4,-18(fp) + 100e77c: e0fffb83 ldbu r3,-18(fp) + 100e780: e0bffc17 ldw r2,-16(fp) + 100e784: 1885883a add r2,r3,r2 + 100e788: 10800204 addi r2,r2,8 + 100e78c: 108000c3 ldbu r2,3(r2) + 100e790: 1007883a mov r3,r2 + 100e794: e0bffb03 ldbu r2,-20(fp) + 100e798: 0084303a nor r2,zero,r2 + 100e79c: 1884703a and r2,r3,r2 + 100e7a0: 1007883a mov r3,r2 + 100e7a4: e0bffc17 ldw r2,-16(fp) + 100e7a8: 2085883a add r2,r4,r2 + 100e7ac: 10800204 addi r2,r2,8 + 100e7b0: 10c000c5 stb r3,3(r2) + if (pevent->OSEventTbl[y] == 0) { + 100e7b4: e0fffb83 ldbu r3,-18(fp) + 100e7b8: e0bffc17 ldw r2,-16(fp) + 100e7bc: 1885883a add r2,r3,r2 + 100e7c0: 10800204 addi r2,r2,8 + 100e7c4: 108000c3 ldbu r2,3(r2) + 100e7c8: 10803fcc andi r2,r2,255 + 100e7cc: 1004c03a cmpne r2,r2,zero + 100e7d0: 1000091e bne r2,zero,100e7f8 + pevent->OSEventGrp &= ~bity; + 100e7d4: e0bffc17 ldw r2,-16(fp) + 100e7d8: 10800283 ldbu r2,10(r2) + 100e7dc: 1007883a mov r3,r2 + 100e7e0: e0bffb43 ldbu r2,-19(fp) + 100e7e4: 0084303a nor r2,zero,r2 + 100e7e8: 1884703a and r2,r3,r2 + 100e7ec: 1007883a mov r3,r2 + 100e7f0: e0bffc17 ldw r2,-16(fp) + 100e7f4: 10c00285 stb r3,10(r2) + } + pevents++; + 100e7f8: e0bffd17 ldw r2,-12(fp) + 100e7fc: 10800104 addi r2,r2,4 + 100e800: e0bffd15 stw r2,-12(fp) + pevent = *pevents; + 100e804: e0bffd17 ldw r2,-12(fp) + 100e808: 10800017 ldw r2,0(r2) + 100e80c: e0bffc15 stw r2,-16(fp) + y = ptcb->OSTCBY; + bity = ptcb->OSTCBBitY; + bitx = ptcb->OSTCBBitX; + pevents = pevents_multi; + pevent = *pevents; + while (pevent != (OS_EVENT *)0) { /* Remove task from all events' wait lists */ + 100e810: e0bffc17 ldw r2,-16(fp) + 100e814: 1004c03a cmpne r2,r2,zero + 100e818: 103fd71e bne r2,zero,100e778 + pevent->OSEventGrp &= ~bity; + } + pevents++; + pevent = *pevents; + } +} + 100e81c: e037883a mov sp,fp + 100e820: df000017 ldw fp,0(sp) + 100e824: dec00104 addi sp,sp,4 + 100e828: f800283a ret + +0100e82c : +* Note : This function is INTERNAL to uC/OS-II and your application should not call it. +********************************************************************************************************* +*/ +#if (OS_EVENT_EN) +void OS_EventWaitListInit (OS_EVENT *pevent) +{ + 100e82c: defffc04 addi sp,sp,-16 + 100e830: df000315 stw fp,12(sp) + 100e834: df000304 addi fp,sp,12 + 100e838: e13fff15 stw r4,-4(fp) + INT16U *ptbl; +#endif + INT8U i; + + + pevent->OSEventGrp = 0; /* No task waiting on event */ + 100e83c: e0bfff17 ldw r2,-4(fp) + 100e840: 10000285 stb zero,10(r2) + ptbl = &pevent->OSEventTbl[0]; + 100e844: e0bfff17 ldw r2,-4(fp) + 100e848: 108002c4 addi r2,r2,11 + 100e84c: e0bffe15 stw r2,-8(fp) + + for (i = 0; i < OS_EVENT_TBL_SIZE; i++) { + 100e850: e03ffd05 stb zero,-12(fp) + 100e854: 00000806 br 100e878 + *ptbl++ = 0; + 100e858: e0bffe17 ldw r2,-8(fp) + 100e85c: 10000005 stb zero,0(r2) + 100e860: e0bffe17 ldw r2,-8(fp) + 100e864: 10800044 addi r2,r2,1 + 100e868: e0bffe15 stw r2,-8(fp) + + + pevent->OSEventGrp = 0; /* No task waiting on event */ + ptbl = &pevent->OSEventTbl[0]; + + for (i = 0; i < OS_EVENT_TBL_SIZE; i++) { + 100e86c: e0bffd03 ldbu r2,-12(fp) + 100e870: 10800044 addi r2,r2,1 + 100e874: e0bffd05 stb r2,-12(fp) + 100e878: e0bffd03 ldbu r2,-12(fp) + 100e87c: 108000f0 cmpltui r2,r2,3 + 100e880: 103ff51e bne r2,zero,100e858 + *ptbl++ = 0; + } +} + 100e884: e037883a mov sp,fp + 100e888: df000017 ldw fp,0(sp) + 100e88c: dec00104 addi sp,sp,4 + 100e890: f800283a ret + +0100e894 : +* Returns : none +********************************************************************************************************* +*/ + +static void OS_InitEventList (void) +{ + 100e894: defffb04 addi sp,sp,-20 + 100e898: dfc00415 stw ra,16(sp) + 100e89c: df000315 stw fp,12(sp) + 100e8a0: df000304 addi fp,sp,12 + INT16U i; + OS_EVENT *pevent1; + OS_EVENT *pevent2; + + + OS_MemClr((INT8U *)&OSEventTbl[0], sizeof(OSEventTbl)); /* Clear the event table */ + 100e8a4: 010040b4 movhi r4,258 + 100e8a8: 21159504 addi r4,r4,22100 + 100e8ac: 0142d004 movi r5,2880 + 100e8b0: 100ebf80 call 100ebf8 + pevent1 = &OSEventTbl[0]; + 100e8b4: 008040b4 movhi r2,258 + 100e8b8: 10959504 addi r2,r2,22100 + 100e8bc: e0bffe15 stw r2,-8(fp) + pevent2 = &OSEventTbl[1]; + 100e8c0: 008040b4 movhi r2,258 + 100e8c4: 1095a104 addi r2,r2,22148 + 100e8c8: e0bffd15 stw r2,-12(fp) + for (i = 0; i < (OS_MAX_EVENTS - 1); i++) { /* Init. list of free EVENT control blocks */ + 100e8cc: e03fff0d sth zero,-4(fp) + 100e8d0: 00001306 br 100e920 + pevent1->OSEventType = OS_EVENT_TYPE_UNUSED; + 100e8d4: e0bffe17 ldw r2,-8(fp) + 100e8d8: 10000005 stb zero,0(r2) + pevent1->OSEventPtr = pevent2; + 100e8dc: e0fffe17 ldw r3,-8(fp) + 100e8e0: e0bffd17 ldw r2,-12(fp) + 100e8e4: 18800115 stw r2,4(r3) +#if OS_EVENT_NAME_SIZE > 1 + pevent1->OSEventName[0] = '?'; /* Unknown name */ + 100e8e8: e0fffe17 ldw r3,-8(fp) + 100e8ec: 00800fc4 movi r2,63 + 100e8f0: 18800385 stb r2,14(r3) + pevent1->OSEventName[1] = OS_ASCII_NUL; + 100e8f4: e0bffe17 ldw r2,-8(fp) + 100e8f8: 100003c5 stb zero,15(r2) +#endif + pevent1++; + 100e8fc: e0bffe17 ldw r2,-8(fp) + 100e900: 10800c04 addi r2,r2,48 + 100e904: e0bffe15 stw r2,-8(fp) + pevent2++; + 100e908: e0bffd17 ldw r2,-12(fp) + 100e90c: 10800c04 addi r2,r2,48 + 100e910: e0bffd15 stw r2,-12(fp) + + + OS_MemClr((INT8U *)&OSEventTbl[0], sizeof(OSEventTbl)); /* Clear the event table */ + pevent1 = &OSEventTbl[0]; + pevent2 = &OSEventTbl[1]; + for (i = 0; i < (OS_MAX_EVENTS - 1); i++) { /* Init. list of free EVENT control blocks */ + 100e914: e0bfff0b ldhu r2,-4(fp) + 100e918: 10800044 addi r2,r2,1 + 100e91c: e0bfff0d sth r2,-4(fp) + 100e920: e0bfff0b ldhu r2,-4(fp) + 100e924: 10800ef0 cmpltui r2,r2,59 + 100e928: 103fea1e bne r2,zero,100e8d4 + pevent1->OSEventName[1] = OS_ASCII_NUL; +#endif + pevent1++; + pevent2++; + } + pevent1->OSEventType = OS_EVENT_TYPE_UNUSED; + 100e92c: e0bffe17 ldw r2,-8(fp) + 100e930: 10000005 stb zero,0(r2) + pevent1->OSEventPtr = (OS_EVENT *)0; + 100e934: e0bffe17 ldw r2,-8(fp) + 100e938: 10000115 stw zero,4(r2) +#if OS_EVENT_NAME_SIZE > 1 + pevent1->OSEventName[0] = '?'; + 100e93c: e0fffe17 ldw r3,-8(fp) + 100e940: 00800fc4 movi r2,63 + 100e944: 18800385 stb r2,14(r3) + pevent1->OSEventName[1] = OS_ASCII_NUL; + 100e948: e0bffe17 ldw r2,-8(fp) + 100e94c: 100003c5 stb zero,15(r2) +#endif + OSEventFreeList = &OSEventTbl[0]; + 100e950: 008040b4 movhi r2,258 + 100e954: 10959504 addi r2,r2,22100 + 100e958: d0a79015 stw r2,-25024(gp) + OSEventFreeList->OSEventName[0] = '?'; /* Unknown name */ + OSEventFreeList->OSEventName[1] = OS_ASCII_NUL; +#endif +#endif +#endif +} + 100e95c: e037883a mov sp,fp + 100e960: dfc00117 ldw ra,4(sp) + 100e964: df000017 ldw fp,0(sp) + 100e968: dec00204 addi sp,sp,8 + 100e96c: f800283a ret + +0100e970 : +* Returns : none +********************************************************************************************************* +*/ + +static void OS_InitMisc (void) +{ + 100e970: deffff04 addi sp,sp,-4 + 100e974: df000015 stw fp,0(sp) + 100e978: d839883a mov fp,sp +#if OS_TIME_GET_SET_EN > 0 + OSTime = 0L; /* Clear the 32-bit system clock */ + 100e97c: d0279315 stw zero,-25012(gp) +#endif + + OSIntNesting = 0; /* Clear the interrupt nesting counter */ + 100e980: d0279105 stb zero,-25020(gp) + OSLockNesting = 0; /* Clear the scheduling lock counter */ + 100e984: d0278305 stb zero,-25076(gp) + + OSTaskCtr = 0; /* Clear the number of tasks */ + 100e988: d0278b45 stb zero,-25043(gp) + + OSRunning = OS_FALSE; /* Indicate that multitasking not started */ + 100e98c: d0278345 stb zero,-25075(gp) + + OSCtxSwCtr = 0; /* Clear the context switch counter */ + 100e990: d0278815 stw zero,-25056(gp) + OSIdleCtr = 0L; /* Clear the 32-bit idle counter */ + 100e994: d0278415 stw zero,-25072(gp) + +#if OS_TASK_STAT_EN > 0 + OSIdleCtrRun = 0L; + 100e998: d0279615 stw zero,-25000(gp) + OSIdleCtrMax = 0L; + 100e99c: d0278915 stw zero,-25052(gp) + OSStatRdy = OS_FALSE; /* Statistic task is not ready */ + 100e9a0: d0279505 stb zero,-25004(gp) +#endif +} + 100e9a4: e037883a mov sp,fp + 100e9a8: df000017 ldw fp,0(sp) + 100e9ac: dec00104 addi sp,sp,4 + 100e9b0: f800283a ret + +0100e9b4 : +* Returns : none +********************************************************************************************************* +*/ + +static void OS_InitRdyList (void) +{ + 100e9b4: defffd04 addi sp,sp,-12 + 100e9b8: df000215 stw fp,8(sp) + 100e9bc: df000204 addi fp,sp,8 +#else + INT16U *prdytbl; +#endif + + + OSRdyGrp = 0; /* Clear the ready list */ + 100e9c0: d0278f05 stb zero,-25028(gp) + prdytbl = &OSRdyTbl[0]; + 100e9c4: d0a78f44 addi r2,gp,-25027 + 100e9c8: e0bffe15 stw r2,-8(fp) + for (i = 0; i < OS_RDY_TBL_SIZE; i++) { + 100e9cc: e03fff05 stb zero,-4(fp) + 100e9d0: 00000806 br 100e9f4 + *prdytbl++ = 0; + 100e9d4: e0bffe17 ldw r2,-8(fp) + 100e9d8: 10000005 stb zero,0(r2) + 100e9dc: e0bffe17 ldw r2,-8(fp) + 100e9e0: 10800044 addi r2,r2,1 + 100e9e4: e0bffe15 stw r2,-8(fp) +#endif + + + OSRdyGrp = 0; /* Clear the ready list */ + prdytbl = &OSRdyTbl[0]; + for (i = 0; i < OS_RDY_TBL_SIZE; i++) { + 100e9e8: e0bfff03 ldbu r2,-4(fp) + 100e9ec: 10800044 addi r2,r2,1 + 100e9f0: e0bfff05 stb r2,-4(fp) + 100e9f4: e0bfff03 ldbu r2,-4(fp) + 100e9f8: 108000f0 cmpltui r2,r2,3 + 100e9fc: 103ff51e bne r2,zero,100e9d4 + *prdytbl++ = 0; + } + + OSPrioCur = 0; + 100ea00: d0278545 stb zero,-25067(gp) + OSPrioHighRdy = 0; + 100ea04: d0278505 stb zero,-25068(gp) + + OSTCBHighRdy = (OS_TCB *)0; + 100ea08: d0278d15 stw zero,-25036(gp) + OSTCBCur = (OS_TCB *)0; + 100ea0c: d0279215 stw zero,-25016(gp) +} + 100ea10: e037883a mov sp,fp + 100ea14: df000017 ldw fp,0(sp) + 100ea18: dec00104 addi sp,sp,4 + 100ea1c: f800283a ret + +0100ea20 : +* Returns : none +********************************************************************************************************* +*/ + +static void OS_InitTaskIdle (void) +{ + 100ea20: defff804 addi sp,sp,-32 + 100ea24: dfc00715 stw ra,28(sp) + 100ea28: df000615 stw fp,24(sp) + 100ea2c: df000604 addi fp,sp,24 +#endif + + +#if OS_TASK_CREATE_EXT_EN > 0 + #if OS_STK_GROWTH == 1 + (void)OSTaskCreateExt(OS_TaskIdle, + 100ea30: 018040b4 movhi r6,258 + 100ea34: 31959404 addi r6,r6,22096 + 100ea38: 00bfffd4 movui r2,65535 + 100ea3c: d8800015 stw r2,0(sp) + 100ea40: 008040b4 movhi r2,258 + 100ea44: 10939504 addi r2,r2,20052 + 100ea48: d8800115 stw r2,4(sp) + 100ea4c: 00808004 movi r2,512 + 100ea50: d8800215 stw r2,8(sp) + 100ea54: d8000315 stw zero,12(sp) + 100ea58: 008000c4 movi r2,3 + 100ea5c: d8800415 stw r2,16(sp) + 100ea60: 01004074 movhi r4,257 + 100ea64: 213bb504 addi r4,r4,-4396 + 100ea68: 000b883a mov r5,zero + 100ea6c: 01c00504 movi r7,20 + 100ea70: 1013cb40 call 1013cb4 + OS_TASK_IDLE_PRIO); + #endif +#endif + +#if OS_TASK_NAME_SIZE > 14 + OSTaskNameSet(OS_TASK_IDLE_PRIO, (INT8U *)"uC/OS-II Idle", &err); + 100ea74: 014040b4 movhi r5,258 + 100ea78: 29647604 addi r5,r5,-28200 + 100ea7c: 01000504 movi r4,20 + 100ea80: e1bfff04 addi r6,fp,-4 + 100ea84: 10145e80 call 10145e8 +#else +#if OS_TASK_NAME_SIZE > 7 + OSTaskNameSet(OS_TASK_IDLE_PRIO, (INT8U *)"OS-Idle", &err); +#endif +#endif +} + 100ea88: e037883a mov sp,fp + 100ea8c: dfc00117 ldw ra,4(sp) + 100ea90: df000017 ldw fp,0(sp) + 100ea94: dec00204 addi sp,sp,8 + 100ea98: f800283a ret + +0100ea9c : +********************************************************************************************************* +*/ + +#if OS_TASK_STAT_EN > 0 +static void OS_InitTaskStat (void) +{ + 100ea9c: defff804 addi sp,sp,-32 + 100eaa0: dfc00715 stw ra,28(sp) + 100eaa4: df000615 stw fp,24(sp) + 100eaa8: df000604 addi fp,sp,24 +#endif + + +#if OS_TASK_CREATE_EXT_EN > 0 + #if OS_STK_GROWTH == 1 + (void)OSTaskCreateExt(OS_TaskStat, + 100eaac: 018040b4 movhi r6,258 + 100eab0: 31931c04 addi r6,r6,19568 + 100eab4: 00bfff94 movui r2,65534 + 100eab8: d8800015 stw r2,0(sp) + 100eabc: 008040b4 movhi r2,258 + 100eac0: 10911d04 addi r2,r2,17524 + 100eac4: d8800115 stw r2,4(sp) + 100eac8: 00808004 movi r2,512 + 100eacc: d8800215 stw r2,8(sp) + 100ead0: d8000315 stw zero,12(sp) + 100ead4: 008000c4 movi r2,3 + 100ead8: d8800415 stw r2,16(sp) + 100eadc: 01004074 movhi r4,257 + 100eae0: 213bcc04 addi r4,r4,-4304 + 100eae4: 000b883a mov r5,zero + 100eae8: 01c004c4 movi r7,19 + 100eaec: 1013cb40 call 1013cb4 + OS_TASK_STAT_PRIO); /* One higher than the idle task */ + #endif +#endif + +#if OS_TASK_NAME_SIZE > 14 + OSTaskNameSet(OS_TASK_STAT_PRIO, (INT8U *)"uC/OS-II Stat", &err); + 100eaf0: 014040b4 movhi r5,258 + 100eaf4: 29647a04 addi r5,r5,-28184 + 100eaf8: 010004c4 movi r4,19 + 100eafc: e1bfff04 addi r6,fp,-4 + 100eb00: 10145e80 call 10145e8 +#else +#if OS_TASK_NAME_SIZE > 7 + OSTaskNameSet(OS_TASK_STAT_PRIO, (INT8U *)"OS-Stat", &err); +#endif +#endif +} + 100eb04: e037883a mov sp,fp + 100eb08: dfc00117 ldw ra,4(sp) + 100eb0c: df000017 ldw fp,0(sp) + 100eb10: dec00204 addi sp,sp,8 + 100eb14: f800283a ret + +0100eb18 : +* Returns : none +********************************************************************************************************* +*/ + +static void OS_InitTCBList (void) +{ + 100eb18: defffb04 addi sp,sp,-20 + 100eb1c: dfc00415 stw ra,16(sp) + 100eb20: df000315 stw fp,12(sp) + 100eb24: df000304 addi fp,sp,12 + INT8U i; + OS_TCB *ptcb1; + OS_TCB *ptcb2; + + + OS_MemClr((INT8U *)&OSTCBTbl[0], sizeof(OSTCBTbl)); /* Clear all the TCBs */ + 100eb28: 010040b4 movhi r4,258 + 100eb2c: 21186504 addi r4,r4,24980 + 100eb30: 01414404 movi r5,1296 + 100eb34: 100ebf80 call 100ebf8 + OS_MemClr((INT8U *)&OSTCBPrioTbl[0], sizeof(OSTCBPrioTbl)); /* Clear the priority table */ + 100eb38: 010040b4 movhi r4,258 + 100eb3c: 2119a904 addi r4,r4,26276 + 100eb40: 01401504 movi r5,84 + 100eb44: 100ebf80 call 100ebf8 + ptcb1 = &OSTCBTbl[0]; + 100eb48: 008040b4 movhi r2,258 + 100eb4c: 10986504 addi r2,r2,24980 + 100eb50: e0bffe15 stw r2,-8(fp) + ptcb2 = &OSTCBTbl[1]; + 100eb54: 008040b4 movhi r2,258 + 100eb58: 10988004 addi r2,r2,25088 + 100eb5c: e0bffd15 stw r2,-12(fp) + for (i = 0; i < (OS_MAX_TASKS + OS_N_SYS_TASKS - 1); i++) { /* Init. list of free TCBs */ + 100eb60: e03fff05 stb zero,-4(fp) + 100eb64: 00001106 br 100ebac + ptcb1->OSTCBNext = ptcb2; + 100eb68: e0fffe17 ldw r3,-8(fp) + 100eb6c: e0bffd17 ldw r2,-12(fp) + 100eb70: 18800515 stw r2,20(r3) +#if OS_TASK_NAME_SIZE > 1 + ptcb1->OSTCBTaskName[0] = '?'; /* Unknown name */ + 100eb74: e0fffe17 ldw r3,-8(fp) + 100eb78: 00800fc4 movi r2,63 + 100eb7c: 18801305 stb r2,76(r3) + ptcb1->OSTCBTaskName[1] = OS_ASCII_NUL; + 100eb80: e0bffe17 ldw r2,-8(fp) + 100eb84: 10001345 stb zero,77(r2) +#endif + ptcb1++; + 100eb88: e0bffe17 ldw r2,-8(fp) + 100eb8c: 10801b04 addi r2,r2,108 + 100eb90: e0bffe15 stw r2,-8(fp) + ptcb2++; + 100eb94: e0bffd17 ldw r2,-12(fp) + 100eb98: 10801b04 addi r2,r2,108 + 100eb9c: e0bffd15 stw r2,-12(fp) + + OS_MemClr((INT8U *)&OSTCBTbl[0], sizeof(OSTCBTbl)); /* Clear all the TCBs */ + OS_MemClr((INT8U *)&OSTCBPrioTbl[0], sizeof(OSTCBPrioTbl)); /* Clear the priority table */ + ptcb1 = &OSTCBTbl[0]; + ptcb2 = &OSTCBTbl[1]; + for (i = 0; i < (OS_MAX_TASKS + OS_N_SYS_TASKS - 1); i++) { /* Init. list of free TCBs */ + 100eba0: e0bfff03 ldbu r2,-4(fp) + 100eba4: 10800044 addi r2,r2,1 + 100eba8: e0bfff05 stb r2,-4(fp) + 100ebac: e0bfff03 ldbu r2,-4(fp) + 100ebb0: 108002f0 cmpltui r2,r2,11 + 100ebb4: 103fec1e bne r2,zero,100eb68 + ptcb1->OSTCBTaskName[1] = OS_ASCII_NUL; +#endif + ptcb1++; + ptcb2++; + } + ptcb1->OSTCBNext = (OS_TCB *)0; /* Last OS_TCB */ + 100ebb8: e0bffe17 ldw r2,-8(fp) + 100ebbc: 10000515 stw zero,20(r2) +#if OS_TASK_NAME_SIZE > 1 + ptcb1->OSTCBTaskName[0] = '?'; /* Unknown name */ + 100ebc0: e0fffe17 ldw r3,-8(fp) + 100ebc4: 00800fc4 movi r2,63 + 100ebc8: 18801305 stb r2,76(r3) + ptcb1->OSTCBTaskName[1] = OS_ASCII_NUL; + 100ebcc: e0bffe17 ldw r2,-8(fp) + 100ebd0: 10001345 stb zero,77(r2) +#endif + OSTCBList = (OS_TCB *)0; /* TCB lists initializations */ + 100ebd4: d0278615 stw zero,-25064(gp) + OSTCBFreeList = &OSTCBTbl[0]; + 100ebd8: 008040b4 movhi r2,258 + 100ebdc: 10986504 addi r2,r2,24980 + 100ebe0: d0a78a15 stw r2,-25048(gp) +} + 100ebe4: e037883a mov sp,fp + 100ebe8: dfc00117 ldw ra,4(sp) + 100ebec: df000017 ldw fp,0(sp) + 100ebf0: dec00204 addi sp,sp,8 + 100ebf4: f800283a ret + +0100ebf8 : +* of the alignment of the destination. +********************************************************************************************************* +*/ + +void OS_MemClr (INT8U *pdest, INT16U size) +{ + 100ebf8: defffd04 addi sp,sp,-12 + 100ebfc: df000215 stw fp,8(sp) + 100ec00: df000204 addi fp,sp,8 + 100ec04: e13ffe15 stw r4,-8(fp) + 100ec08: e17fff0d sth r5,-4(fp) + while (size > 0) { + 100ec0c: 00000806 br 100ec30 + *pdest++ = (INT8U)0; + 100ec10: e0bffe17 ldw r2,-8(fp) + 100ec14: 10000005 stb zero,0(r2) + 100ec18: e0bffe17 ldw r2,-8(fp) + 100ec1c: 10800044 addi r2,r2,1 + 100ec20: e0bffe15 stw r2,-8(fp) + size--; + 100ec24: e0bfff0b ldhu r2,-4(fp) + 100ec28: 10bfffc4 addi r2,r2,-1 + 100ec2c: e0bfff0d sth r2,-4(fp) +********************************************************************************************************* +*/ + +void OS_MemClr (INT8U *pdest, INT16U size) +{ + while (size > 0) { + 100ec30: e0bfff0b ldhu r2,-4(fp) + 100ec34: 1004c03a cmpne r2,r2,zero + 100ec38: 103ff51e bne r2,zero,100ec10 + *pdest++ = (INT8U)0; + size--; + } +} + 100ec3c: e037883a mov sp,fp + 100ec40: df000017 ldw fp,0(sp) + 100ec44: dec00104 addi sp,sp,4 + 100ec48: f800283a ret + +0100ec4c : +* of the alignment of the source and destination. +********************************************************************************************************* +*/ + +void OS_MemCopy (INT8U *pdest, INT8U *psrc, INT16U size) +{ + 100ec4c: defffc04 addi sp,sp,-16 + 100ec50: df000315 stw fp,12(sp) + 100ec54: df000304 addi fp,sp,12 + 100ec58: e13ffd15 stw r4,-12(fp) + 100ec5c: e17ffe15 stw r5,-8(fp) + 100ec60: e1bfff0d sth r6,-4(fp) + while (size > 0) { + 100ec64: 00000d06 br 100ec9c + *pdest++ = *psrc++; + 100ec68: e0bffe17 ldw r2,-8(fp) + 100ec6c: 10c00003 ldbu r3,0(r2) + 100ec70: e0bffd17 ldw r2,-12(fp) + 100ec74: 10c00005 stb r3,0(r2) + 100ec78: e0bffd17 ldw r2,-12(fp) + 100ec7c: 10800044 addi r2,r2,1 + 100ec80: e0bffd15 stw r2,-12(fp) + 100ec84: e0bffe17 ldw r2,-8(fp) + 100ec88: 10800044 addi r2,r2,1 + 100ec8c: e0bffe15 stw r2,-8(fp) + size--; + 100ec90: e0bfff0b ldhu r2,-4(fp) + 100ec94: 10bfffc4 addi r2,r2,-1 + 100ec98: e0bfff0d sth r2,-4(fp) +********************************************************************************************************* +*/ + +void OS_MemCopy (INT8U *pdest, INT8U *psrc, INT16U size) +{ + while (size > 0) { + 100ec9c: e0bfff0b ldhu r2,-4(fp) + 100eca0: 1004c03a cmpne r2,r2,zero + 100eca4: 103ff01e bne r2,zero,100ec68 + *pdest++ = *psrc++; + size--; + } +} + 100eca8: e037883a mov sp,fp + 100ecac: df000017 ldw fp,0(sp) + 100ecb0: dec00104 addi sp,sp,4 + 100ecb4: f800283a ret + +0100ecb8 : +* 2) Rescheduling is prevented when the scheduler is locked (see OS_SchedLock()) +********************************************************************************************************* +*/ + +void OS_Sched (void) +{ + 100ecb8: defffb04 addi sp,sp,-20 + 100ecbc: dfc00415 stw ra,16(sp) + 100ecc0: df000315 stw fp,12(sp) + 100ecc4: df000304 addi fp,sp,12 +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 100ecc8: e03fff15 stw zero,-4(fp) +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 100eccc: 0005303a rdctl r2,status + 100ecd0: e0bffe15 stw r2,-8(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 100ecd4: e0fffe17 ldw r3,-8(fp) + 100ecd8: 00bfff84 movi r2,-2 + 100ecdc: 1884703a and r2,r3,r2 + 100ece0: 1001703a wrctl status,r2 + + return context; + 100ece4: e0bffe17 ldw r2,-8(fp) +#endif + + + + OS_ENTER_CRITICAL(); + 100ece8: e0bfff15 stw r2,-4(fp) + if (OSIntNesting == 0) { /* Schedule only if all ISRs done and ... */ + 100ecec: d0a79103 ldbu r2,-25020(gp) + 100ecf0: 10803fcc andi r2,r2,255 + 100ecf4: 1004c03a cmpne r2,r2,zero + 100ecf8: 10001b1e bne r2,zero,100ed68 + if (OSLockNesting == 0) { /* ... scheduler is not locked */ + 100ecfc: d0a78303 ldbu r2,-25076(gp) + 100ed00: 10803fcc andi r2,r2,255 + 100ed04: 1004c03a cmpne r2,r2,zero + 100ed08: 1000171e bne r2,zero,100ed68 + OS_SchedNew(); + 100ed0c: 100ed8c0 call 100ed8c + if (OSPrioHighRdy != OSPrioCur) { /* No Ctx Sw if current task is highest rdy */ + 100ed10: d0a78503 ldbu r2,-25068(gp) + 100ed14: d0e78543 ldbu r3,-25067(gp) + 100ed18: 11003fcc andi r4,r2,255 + 100ed1c: 18803fcc andi r2,r3,255 + 100ed20: 20801126 beq r4,r2,100ed68 + OSTCBHighRdy = OSTCBPrioTbl[OSPrioHighRdy]; + 100ed24: d0a78503 ldbu r2,-25068(gp) + 100ed28: 10803fcc andi r2,r2,255 + 100ed2c: 00c040b4 movhi r3,258 + 100ed30: 18d9a904 addi r3,r3,26276 + 100ed34: 1085883a add r2,r2,r2 + 100ed38: 1085883a add r2,r2,r2 + 100ed3c: 10c5883a add r2,r2,r3 + 100ed40: 10800017 ldw r2,0(r2) + 100ed44: d0a78d15 stw r2,-25036(gp) +#if OS_TASK_PROFILE_EN > 0 + OSTCBHighRdy->OSTCBCtxSwCtr++; /* Inc. # of context switches to this task */ + 100ed48: d0e78d17 ldw r3,-25036(gp) + 100ed4c: 18800e17 ldw r2,56(r3) + 100ed50: 10800044 addi r2,r2,1 + 100ed54: 18800e15 stw r2,56(r3) +#endif + OSCtxSwCtr++; /* Increment context switch counter */ + 100ed58: d0a78817 ldw r2,-25056(gp) + 100ed5c: 10800044 addi r2,r2,1 + 100ed60: d0a78815 stw r2,-25056(gp) + OS_TASK_SW(); /* Perform a context switch */ + 100ed64: 101802c0 call 101802c + 100ed68: e0bfff17 ldw r2,-4(fp) + 100ed6c: e0bffd15 stw r2,-12(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 100ed70: e0bffd17 ldw r2,-12(fp) + 100ed74: 1001703a wrctl status,r2 + } + } + } + OS_EXIT_CRITICAL(); +} + 100ed78: e037883a mov sp,fp + 100ed7c: dfc00117 ldw ra,4(sp) + 100ed80: df000017 ldw fp,0(sp) + 100ed84: dec00204 addi sp,sp,8 + 100ed88: f800283a ret + +0100ed8c : +* 2) Interrupts are assumed to be disabled when this function is called. +********************************************************************************************************* +*/ + +static void OS_SchedNew (void) +{ + 100ed8c: defffe04 addi sp,sp,-8 + 100ed90: df000115 stw fp,4(sp) + 100ed94: df000104 addi fp,sp,4 +#if OS_LOWEST_PRIO <= 63 /* See if we support up to 64 tasks */ + INT8U y; + + + y = OSUnMapTbl[OSRdyGrp]; + 100ed98: d0a78f03 ldbu r2,-25028(gp) + 100ed9c: 10c03fcc andi r3,r2,255 + 100eda0: 008040b4 movhi r2,258 + 100eda4: 10a43604 addi r2,r2,-28456 + 100eda8: 10c5883a add r2,r2,r3 + 100edac: 10800003 ldbu r2,0(r2) + 100edb0: e0bfff05 stb r2,-4(fp) + OSPrioHighRdy = (INT8U)((y << 3) + OSUnMapTbl[OSRdyTbl[y]]); + 100edb4: e0bfff03 ldbu r2,-4(fp) + 100edb8: 100490fa slli r2,r2,3 + 100edbc: 1009883a mov r4,r2 + 100edc0: e0ffff03 ldbu r3,-4(fp) + 100edc4: d0a78f44 addi r2,gp,-25027 + 100edc8: 1885883a add r2,r3,r2 + 100edcc: 10800003 ldbu r2,0(r2) + 100edd0: 10c03fcc andi r3,r2,255 + 100edd4: 008040b4 movhi r2,258 + 100edd8: 10a43604 addi r2,r2,-28456 + 100eddc: 10c5883a add r2,r2,r3 + 100ede0: 10800003 ldbu r2,0(r2) + 100ede4: 2085883a add r2,r4,r2 + 100ede8: d0a78505 stb r2,-25068(gp) + OSPrioHighRdy = (INT8U)((y << 4) + OSUnMapTbl[(*ptbl & 0xFF)]); + } else { + OSPrioHighRdy = (INT8U)((y << 4) + OSUnMapTbl[(*ptbl >> 8) & 0xFF] + 8); + } +#endif +} + 100edec: e037883a mov sp,fp + 100edf0: df000017 ldw fp,0(sp) + 100edf4: dec00104 addi sp,sp,4 + 100edf8: f800283a ret + +0100edfc : +********************************************************************************************************* +*/ + +#if (OS_EVENT_NAME_SIZE > 1) || (OS_FLAG_NAME_SIZE > 1) || (OS_MEM_NAME_SIZE > 1) || (OS_TASK_NAME_SIZE > 1) || (OS_TMR_CFG_NAME_SIZE > 1) +INT8U OS_StrCopy (INT8U *pdest, INT8U *psrc) +{ + 100edfc: defffc04 addi sp,sp,-16 + 100ee00: df000315 stw fp,12(sp) + 100ee04: df000304 addi fp,sp,12 + 100ee08: e13ffe15 stw r4,-8(fp) + 100ee0c: e17fff15 stw r5,-4(fp) + INT8U len; + + + len = 0; + 100ee10: e03ffd05 stb zero,-12(fp) + while (*psrc != OS_ASCII_NUL) { + 100ee14: 00000d06 br 100ee4c + *pdest++ = *psrc++; + 100ee18: e0bfff17 ldw r2,-4(fp) + 100ee1c: 10c00003 ldbu r3,0(r2) + 100ee20: e0bffe17 ldw r2,-8(fp) + 100ee24: 10c00005 stb r3,0(r2) + 100ee28: e0bffe17 ldw r2,-8(fp) + 100ee2c: 10800044 addi r2,r2,1 + 100ee30: e0bffe15 stw r2,-8(fp) + 100ee34: e0bfff17 ldw r2,-4(fp) + 100ee38: 10800044 addi r2,r2,1 + 100ee3c: e0bfff15 stw r2,-4(fp) + len++; + 100ee40: e0bffd03 ldbu r2,-12(fp) + 100ee44: 10800044 addi r2,r2,1 + 100ee48: e0bffd05 stb r2,-12(fp) +{ + INT8U len; + + + len = 0; + while (*psrc != OS_ASCII_NUL) { + 100ee4c: e0bfff17 ldw r2,-4(fp) + 100ee50: 10800003 ldbu r2,0(r2) + 100ee54: 10803fcc andi r2,r2,255 + 100ee58: 1004c03a cmpne r2,r2,zero + 100ee5c: 103fee1e bne r2,zero,100ee18 + *pdest++ = *psrc++; + len++; + } + *pdest = OS_ASCII_NUL; + 100ee60: e0bffe17 ldw r2,-8(fp) + 100ee64: 10000005 stb zero,0(r2) + return (len); + 100ee68: e0bffd03 ldbu r2,-12(fp) +} + 100ee6c: e037883a mov sp,fp + 100ee70: df000017 ldw fp,0(sp) + 100ee74: dec00104 addi sp,sp,4 + 100ee78: f800283a ret + +0100ee7c : +********************************************************************************************************* +*/ + +#if (OS_EVENT_NAME_SIZE > 1) || (OS_FLAG_NAME_SIZE > 1) || (OS_MEM_NAME_SIZE > 1) || (OS_TASK_NAME_SIZE > 1) || (OS_TMR_CFG_NAME_SIZE > 1) +INT8U OS_StrLen (INT8U *psrc) +{ + 100ee7c: defffd04 addi sp,sp,-12 + 100ee80: df000215 stw fp,8(sp) + 100ee84: df000204 addi fp,sp,8 + 100ee88: e13fff15 stw r4,-4(fp) + INT8U len; + + + len = 0; + 100ee8c: e03ffe05 stb zero,-8(fp) + while (*psrc != OS_ASCII_NUL) { + 100ee90: 00000606 br 100eeac + psrc++; + 100ee94: e0bfff17 ldw r2,-4(fp) + 100ee98: 10800044 addi r2,r2,1 + 100ee9c: e0bfff15 stw r2,-4(fp) + len++; + 100eea0: e0bffe03 ldbu r2,-8(fp) + 100eea4: 10800044 addi r2,r2,1 + 100eea8: e0bffe05 stb r2,-8(fp) +{ + INT8U len; + + + len = 0; + while (*psrc != OS_ASCII_NUL) { + 100eeac: e0bfff17 ldw r2,-4(fp) + 100eeb0: 10800003 ldbu r2,0(r2) + 100eeb4: 10803fcc andi r2,r2,255 + 100eeb8: 1004c03a cmpne r2,r2,zero + 100eebc: 103ff51e bne r2,zero,100ee94 + psrc++; + len++; + } + return (len); + 100eec0: e0bffe03 ldbu r2,-8(fp) +} + 100eec4: e037883a mov sp,fp + 100eec8: df000017 ldw fp,0(sp) + 100eecc: dec00104 addi sp,sp,4 + 100eed0: f800283a ret + +0100eed4 : +* power. +********************************************************************************************************* +*/ + +void OS_TaskIdle (void *p_arg) +{ + 100eed4: defffa04 addi sp,sp,-24 + 100eed8: dfc00515 stw ra,20(sp) + 100eedc: df000415 stw fp,16(sp) + 100eee0: df000404 addi fp,sp,16 + 100eee4: e13fff15 stw r4,-4(fp) +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 100eee8: e03ffe15 stw zero,-8(fp) +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 100eeec: 0005303a rdctl r2,status + 100eef0: e0bffd15 stw r2,-12(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 100eef4: e0fffd17 ldw r3,-12(fp) + 100eef8: 00bfff84 movi r2,-2 + 100eefc: 1884703a and r2,r3,r2 + 100ef00: 1001703a wrctl status,r2 + + return context; + 100ef04: e0bffd17 ldw r2,-12(fp) + + + + (void)p_arg; /* Prevent compiler warning for not using 'p_arg' */ + for (;;) { + OS_ENTER_CRITICAL(); + 100ef08: e0bffe15 stw r2,-8(fp) + OSIdleCtr++; + 100ef0c: d0a78417 ldw r2,-25072(gp) + 100ef10: 10800044 addi r2,r2,1 + 100ef14: d0a78415 stw r2,-25072(gp) + 100ef18: e0bffe17 ldw r2,-8(fp) + 100ef1c: e0bffc15 stw r2,-16(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 100ef20: e0bffc17 ldw r2,-16(fp) + 100ef24: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + OSTaskIdleHook(); /* Call user definable HOOK */ + 100ef28: 10184d80 call 10184d8 + } + 100ef2c: 003fef06 br 100eeec + +0100ef30 : +********************************************************************************************************* +*/ + +#if OS_TASK_STAT_EN > 0 +void OS_TaskStat (void *p_arg) +{ + 100ef30: defffa04 addi sp,sp,-24 + 100ef34: dfc00515 stw ra,20(sp) + 100ef38: df000415 stw fp,16(sp) + 100ef3c: df000404 addi fp,sp,16 + 100ef40: e13fff15 stw r4,-4(fp) +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 100ef44: e03ffe15 stw zero,-8(fp) +#endif + + + + (void)p_arg; /* Prevent compiler warning for not using 'p_arg' */ + while (OSStatRdy == OS_FALSE) { + 100ef48: 00000206 br 100ef54 + OSTimeDly(2 * OS_TICKS_PER_SEC / 10); /* Wait until statistic task is ready */ + 100ef4c: 01003204 movi r4,200 + 100ef50: 1014fac0 call 1014fac +#endif + + + + (void)p_arg; /* Prevent compiler warning for not using 'p_arg' */ + while (OSStatRdy == OS_FALSE) { + 100ef54: d0a79503 ldbu r2,-25004(gp) + 100ef58: 10803fcc andi r2,r2,255 + 100ef5c: 1005003a cmpeq r2,r2,zero + 100ef60: 103ffa1e bne r2,zero,100ef4c + OSTimeDly(2 * OS_TICKS_PER_SEC / 10); /* Wait until statistic task is ready */ + } + OSIdleCtrMax /= 100L; + 100ef64: d1278917 ldw r4,-25052(gp) + 100ef68: 01401904 movi r5,100 + 100ef6c: 100bc340 call 100bc34 <__udivsi3> + 100ef70: d0a78915 stw r2,-25052(gp) + if (OSIdleCtrMax == 0L) { + 100ef74: d0a78917 ldw r2,-25052(gp) + 100ef78: 1004c03a cmpne r2,r2,zero + 100ef7c: 1000031e bne r2,zero,100ef8c + OSCPUUsage = 0; + 100ef80: d0278b05 stb zero,-25044(gp) + (void)OSTaskSuspend(OS_PRIO_SELF); + 100ef84: 01003fc4 movi r4,255 + 100ef88: 1014bc00 call 1014bc0 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 100ef8c: 0005303a rdctl r2,status + 100ef90: e0bffd15 stw r2,-12(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 100ef94: e0fffd17 ldw r3,-12(fp) + 100ef98: 00bfff84 movi r2,-2 + 100ef9c: 1884703a and r2,r3,r2 + 100efa0: 1001703a wrctl status,r2 + + return context; + 100efa4: e0bffd17 ldw r2,-12(fp) + } + for (;;) { + OS_ENTER_CRITICAL(); + 100efa8: e0bffe15 stw r2,-8(fp) + OSIdleCtrRun = OSIdleCtr; /* Obtain the of the idle counter for the past second */ + 100efac: d0a78417 ldw r2,-25072(gp) + 100efb0: d0a79615 stw r2,-25000(gp) + OSIdleCtr = 0L; /* Reset the idle counter for the next second */ + 100efb4: d0278415 stw zero,-25072(gp) + 100efb8: e0bffe17 ldw r2,-8(fp) + 100efbc: e0bffc15 stw r2,-16(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 100efc0: e0bffc17 ldw r2,-16(fp) + 100efc4: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + OSCPUUsage = (INT8U)(100L - OSIdleCtrRun / OSIdleCtrMax); + 100efc8: d1279617 ldw r4,-25000(gp) + 100efcc: d1678917 ldw r5,-25052(gp) + 100efd0: 100bc340 call 100bc34 <__udivsi3> + 100efd4: 1007883a mov r3,r2 + 100efd8: 00801904 movi r2,100 + 100efdc: 10c5c83a sub r2,r2,r3 + 100efe0: d0a78b05 stb r2,-25044(gp) + OSTaskStatHook(); /* Invoke user definable hook */ + 100efe4: 10184680 call 1018468 +#if (OS_TASK_STAT_STK_CHK_EN > 0) && (OS_TASK_CREATE_EXT_EN > 0) + OS_TaskStatStkChk(); /* Check the stacks for each task */ + 100efe8: 100eff80 call 100eff8 +#endif + OSTimeDly(OS_TICKS_PER_SEC / 10); /* Accumulate OSIdleCtr for the next 1/10 second */ + 100efec: 01001904 movi r4,100 + 100eff0: 1014fac0 call 1014fac + } + 100eff4: 003fe506 br 100ef8c + +0100eff8 : +********************************************************************************************************* +*/ + +#if (OS_TASK_STAT_STK_CHK_EN > 0) && (OS_TASK_CREATE_EXT_EN > 0) +void OS_TaskStatStkChk (void) +{ + 100eff8: defffa04 addi sp,sp,-24 + 100effc: dfc00515 stw ra,20(sp) + 100f000: df000415 stw fp,16(sp) + 100f004: df000404 addi fp,sp,16 + OS_STK_DATA stk_data; + INT8U err; + INT8U prio; + + + for (prio = 0; prio <= OS_TASK_IDLE_PRIO; prio++) { + 100f008: e03ffc05 stb zero,-16(fp) + 100f00c: 00002406 br 100f0a0 + err = OSTaskStkChk(prio, &stk_data); + 100f010: e13ffc03 ldbu r4,-16(fp) + 100f014: e17ffe04 addi r5,fp,-8 + 100f018: 10149c40 call 10149c4 + 100f01c: e0bffc45 stb r2,-15(fp) + if (err == OS_ERR_NONE) { + 100f020: e0bffc43 ldbu r2,-15(fp) + 100f024: 1004c03a cmpne r2,r2,zero + 100f028: 10001a1e bne r2,zero,100f094 + ptcb = OSTCBPrioTbl[prio]; + 100f02c: e0bffc03 ldbu r2,-16(fp) + 100f030: 00c040b4 movhi r3,258 + 100f034: 18d9a904 addi r3,r3,26276 + 100f038: 1085883a add r2,r2,r2 + 100f03c: 1085883a add r2,r2,r2 + 100f040: 10c5883a add r2,r2,r3 + 100f044: 10800017 ldw r2,0(r2) + 100f048: e0bffd15 stw r2,-12(fp) + if (ptcb != (OS_TCB *)0) { /* Make sure task 'ptcb' is ... */ + 100f04c: e0bffd17 ldw r2,-12(fp) + 100f050: 1005003a cmpeq r2,r2,zero + 100f054: 10000f1e bne r2,zero,100f094 + if (ptcb != OS_TCB_RESERVED) { /* ... still valid. */ + 100f058: e0bffd17 ldw r2,-12(fp) + 100f05c: 10800060 cmpeqi r2,r2,1 + 100f060: 10000c1e bne r2,zero,100f094 +#if OS_TASK_PROFILE_EN > 0 + #if OS_STK_GROWTH == 1 + ptcb->OSTCBStkBase = ptcb->OSTCBStkBottom + ptcb->OSTCBStkSize; + 100f064: e0bffd17 ldw r2,-12(fp) + 100f068: 10c00217 ldw r3,8(r2) + 100f06c: e0bffd17 ldw r2,-12(fp) + 100f070: 10800317 ldw r2,12(r2) + 100f074: 1085883a add r2,r2,r2 + 100f078: 1085883a add r2,r2,r2 + 100f07c: 1887883a add r3,r3,r2 + 100f080: e0bffd17 ldw r2,-12(fp) + 100f084: 10c01115 stw r3,68(r2) + #else + ptcb->OSTCBStkBase = ptcb->OSTCBStkBottom - ptcb->OSTCBStkSize; + #endif + ptcb->OSTCBStkUsed = stk_data.OSUsed; /* Store the number of bytes used */ + 100f088: e0ffff17 ldw r3,-4(fp) + 100f08c: e0bffd17 ldw r2,-12(fp) + 100f090: 10c01215 stw r3,72(r2) + OS_STK_DATA stk_data; + INT8U err; + INT8U prio; + + + for (prio = 0; prio <= OS_TASK_IDLE_PRIO; prio++) { + 100f094: e0bffc03 ldbu r2,-16(fp) + 100f098: 10800044 addi r2,r2,1 + 100f09c: e0bffc05 stb r2,-16(fp) + 100f0a0: e0bffc03 ldbu r2,-16(fp) + 100f0a4: 10800570 cmpltui r2,r2,21 + 100f0a8: 103fd91e bne r2,zero,100f010 +#endif + } + } + } + } +} + 100f0ac: e037883a mov sp,fp + 100f0b0: dfc00117 ldw ra,4(sp) + 100f0b4: df000017 ldw fp,0(sp) + 100f0b8: dec00204 addi sp,sp,8 + 100f0bc: f800283a ret + +0100f0c0 : +* Note : This function is INTERNAL to uC/OS-II and your application should not call it. +********************************************************************************************************* +*/ + +INT8U OS_TCBInit (INT8U prio, OS_STK *ptos, OS_STK *pbos, INT16U id, INT32U stk_size, void *pext, INT16U opt) +{ + 100f0c0: defff104 addi sp,sp,-60 + 100f0c4: dfc00e15 stw ra,56(sp) + 100f0c8: df000d15 stw fp,52(sp) + 100f0cc: df000d04 addi fp,sp,52 + 100f0d0: e17ffb15 stw r5,-20(fp) + 100f0d4: e1bffc15 stw r6,-16(fp) + 100f0d8: e0800417 ldw r2,16(fp) + 100f0dc: e13ffa05 stb r4,-24(fp) + 100f0e0: e1fffd0d sth r7,-12(fp) + 100f0e4: e0bffe0d sth r2,-8(fp) + OS_TCB *ptcb; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 100f0e8: e03ff815 stw zero,-32(fp) +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 100f0ec: 0005303a rdctl r2,status + 100f0f0: e0bff715 stw r2,-36(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 100f0f4: e0fff717 ldw r3,-36(fp) + 100f0f8: 00bfff84 movi r2,-2 + 100f0fc: 1884703a and r2,r3,r2 + 100f100: 1001703a wrctl status,r2 + + return context; + 100f104: e0bff717 ldw r2,-36(fp) +#endif + + + + OS_ENTER_CRITICAL(); + 100f108: e0bff815 stw r2,-32(fp) + ptcb = OSTCBFreeList; /* Get a free TCB from the free TCB list */ + 100f10c: d0a78a17 ldw r2,-25048(gp) + 100f110: e0bff915 stw r2,-28(fp) + if (ptcb != (OS_TCB *)0) { + 100f114: e0bff917 ldw r2,-28(fp) + 100f118: 1005003a cmpeq r2,r2,zero + 100f11c: 1000941e bne r2,zero,100f370 + OSTCBFreeList = ptcb->OSTCBNext; /* Update pointer to free TCB list */ + 100f120: e0bff917 ldw r2,-28(fp) + 100f124: 10800517 ldw r2,20(r2) + 100f128: d0a78a15 stw r2,-25048(gp) + 100f12c: e0bff817 ldw r2,-32(fp) + 100f130: e0bff615 stw r2,-40(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 100f134: e0bff617 ldw r2,-40(fp) + 100f138: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + ptcb->OSTCBStkPtr = ptos; /* Load Stack pointer in TCB */ + 100f13c: e0fff917 ldw r3,-28(fp) + 100f140: e0bffb17 ldw r2,-20(fp) + 100f144: 18800015 stw r2,0(r3) + ptcb->OSTCBPrio = prio; /* Load task priority into TCB */ + 100f148: e0fff917 ldw r3,-28(fp) + 100f14c: e0bffa03 ldbu r2,-24(fp) + 100f150: 18800c85 stb r2,50(r3) + ptcb->OSTCBStat = OS_STAT_RDY; /* Task is ready to run */ + 100f154: e0bff917 ldw r2,-28(fp) + 100f158: 10000c05 stb zero,48(r2) + ptcb->OSTCBStatPend = OS_STAT_PEND_OK; /* Clear pend status */ + 100f15c: e0bff917 ldw r2,-28(fp) + 100f160: 10000c45 stb zero,49(r2) + ptcb->OSTCBDly = 0; /* Task is not delayed */ + 100f164: e0bff917 ldw r2,-28(fp) + 100f168: 10000b8d sth zero,46(r2) + +#if OS_TASK_CREATE_EXT_EN > 0 + ptcb->OSTCBExtPtr = pext; /* Store pointer to TCB extension */ + 100f16c: e0fff917 ldw r3,-28(fp) + 100f170: e0800317 ldw r2,12(fp) + 100f174: 18800115 stw r2,4(r3) + ptcb->OSTCBStkSize = stk_size; /* Store stack size */ + 100f178: e0fff917 ldw r3,-28(fp) + 100f17c: e0800217 ldw r2,8(fp) + 100f180: 18800315 stw r2,12(r3) + ptcb->OSTCBStkBottom = pbos; /* Store pointer to bottom of stack */ + 100f184: e0fff917 ldw r3,-28(fp) + 100f188: e0bffc17 ldw r2,-16(fp) + 100f18c: 18800215 stw r2,8(r3) + ptcb->OSTCBOpt = opt; /* Store task options */ + 100f190: e0fff917 ldw r3,-28(fp) + 100f194: e0bffe0b ldhu r2,-8(fp) + 100f198: 1880040d sth r2,16(r3) + ptcb->OSTCBId = id; /* Store task ID */ + 100f19c: e0fff917 ldw r3,-28(fp) + 100f1a0: e0bffd0b ldhu r2,-12(fp) + 100f1a4: 1880048d sth r2,18(r3) + opt = opt; + id = id; +#endif + +#if OS_TASK_DEL_EN > 0 + ptcb->OSTCBDelReq = OS_ERR_NONE; + 100f1a8: e0bff917 ldw r2,-28(fp) + 100f1ac: 10000dc5 stb zero,55(r2) +#endif + +#if OS_LOWEST_PRIO <= 63 + ptcb->OSTCBY = (INT8U)(prio >> 3); /* Pre-compute X, Y, BitX and BitY */ + 100f1b0: e0bffa03 ldbu r2,-24(fp) + 100f1b4: 1004d0fa srli r2,r2,3 + 100f1b8: 1007883a mov r3,r2 + 100f1bc: e0bff917 ldw r2,-28(fp) + 100f1c0: 10c00d05 stb r3,52(r2) + ptcb->OSTCBX = (INT8U)(prio & 0x07); + 100f1c4: e0bffa03 ldbu r2,-24(fp) + 100f1c8: 108001cc andi r2,r2,7 + 100f1cc: 1007883a mov r3,r2 + 100f1d0: e0bff917 ldw r2,-28(fp) + 100f1d4: 10c00cc5 stb r3,51(r2) + ptcb->OSTCBBitY = (INT8U)(1 << ptcb->OSTCBY); + 100f1d8: e0bff917 ldw r2,-28(fp) + 100f1dc: 10800d03 ldbu r2,52(r2) + 100f1e0: 10c03fcc andi r3,r2,255 + 100f1e4: 00800044 movi r2,1 + 100f1e8: 10c4983a sll r2,r2,r3 + 100f1ec: 1007883a mov r3,r2 + 100f1f0: e0bff917 ldw r2,-28(fp) + 100f1f4: 10c00d85 stb r3,54(r2) + ptcb->OSTCBBitX = (INT8U)(1 << ptcb->OSTCBX); + 100f1f8: e0bff917 ldw r2,-28(fp) + 100f1fc: 10800cc3 ldbu r2,51(r2) + 100f200: 10c03fcc andi r3,r2,255 + 100f204: 00800044 movi r2,1 + 100f208: 10c4983a sll r2,r2,r3 + 100f20c: 1007883a mov r3,r2 + 100f210: e0bff917 ldw r2,-28(fp) + 100f214: 10c00d45 stb r3,53(r2) + ptcb->OSTCBBitY = (INT16U)(1 << ptcb->OSTCBY); + ptcb->OSTCBBitX = (INT16U)(1 << ptcb->OSTCBX); +#endif + +#if (OS_EVENT_EN) + ptcb->OSTCBEventPtr = (OS_EVENT *)0; /* Task is not pending on an event */ + 100f218: e0bff917 ldw r2,-28(fp) + 100f21c: 10000715 stw zero,28(r2) +#if (OS_EVENT_MULTI_EN > 0) + ptcb->OSTCBEventMultiPtr = (OS_EVENT **)0; /* Task is not pending on any events */ + 100f220: e0bff917 ldw r2,-28(fp) + 100f224: 10000815 stw zero,32(r2) +#endif +#endif + +#if (OS_FLAG_EN > 0) && (OS_MAX_FLAGS > 0) && (OS_TASK_DEL_EN > 0) + ptcb->OSTCBFlagNode = (OS_FLAG_NODE *)0; /* Task is not pending on an event flag */ + 100f228: e0bff917 ldw r2,-28(fp) + 100f22c: 10000a15 stw zero,40(r2) +#endif + +#if (OS_MBOX_EN > 0) || ((OS_Q_EN > 0) && (OS_MAX_QS > 0)) + ptcb->OSTCBMsg = (void *)0; /* No message received */ + 100f230: e0bff917 ldw r2,-28(fp) + 100f234: 10000915 stw zero,36(r2) +#endif + +#if OS_TASK_PROFILE_EN > 0 + ptcb->OSTCBCtxSwCtr = 0L; /* Initialize profiling variables */ + 100f238: e0bff917 ldw r2,-28(fp) + 100f23c: 10000e15 stw zero,56(r2) + ptcb->OSTCBCyclesStart = 0L; + 100f240: e0bff917 ldw r2,-28(fp) + 100f244: 10001015 stw zero,64(r2) + ptcb->OSTCBCyclesTot = 0L; + 100f248: e0bff917 ldw r2,-28(fp) + 100f24c: 10000f15 stw zero,60(r2) + ptcb->OSTCBStkBase = (OS_STK *)0; + 100f250: e0bff917 ldw r2,-28(fp) + 100f254: 10001115 stw zero,68(r2) + ptcb->OSTCBStkUsed = 0L; + 100f258: e0bff917 ldw r2,-28(fp) + 100f25c: 10001215 stw zero,72(r2) +#endif + +#if OS_TASK_NAME_SIZE > 1 + ptcb->OSTCBTaskName[0] = '?'; /* Unknown name at task creation */ + 100f260: e0fff917 ldw r3,-28(fp) + 100f264: 00800fc4 movi r2,63 + 100f268: 18801305 stb r2,76(r3) + ptcb->OSTCBTaskName[1] = OS_ASCII_NUL; + 100f26c: e0bff917 ldw r2,-28(fp) + 100f270: 10001345 stb zero,77(r2) +#endif + + OSTCBInitHook(ptcb); + 100f274: e13ff917 ldw r4,-28(fp) + 100f278: 10184f40 call 10184f4 + + OSTaskCreateHook(ptcb); /* Call user defined hook */ + 100f27c: e13ff917 ldw r4,-28(fp) + 100f280: 101840c0 call 101840c +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 100f284: 0005303a rdctl r2,status + 100f288: e0bff515 stw r2,-44(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 100f28c: e0fff517 ldw r3,-44(fp) + 100f290: 00bfff84 movi r2,-2 + 100f294: 1884703a and r2,r3,r2 + 100f298: 1001703a wrctl status,r2 + + return context; + 100f29c: e0bff517 ldw r2,-44(fp) + + OS_ENTER_CRITICAL(); + 100f2a0: e0bff815 stw r2,-32(fp) + OSTCBPrioTbl[prio] = ptcb; + 100f2a4: e0bffa03 ldbu r2,-24(fp) + 100f2a8: 00c040b4 movhi r3,258 + 100f2ac: 18d9a904 addi r3,r3,26276 + 100f2b0: 1085883a add r2,r2,r2 + 100f2b4: 1085883a add r2,r2,r2 + 100f2b8: 10c7883a add r3,r2,r3 + 100f2bc: e0bff917 ldw r2,-28(fp) + 100f2c0: 18800015 stw r2,0(r3) + ptcb->OSTCBNext = OSTCBList; /* Link into TCB chain */ + 100f2c4: d0e78617 ldw r3,-25064(gp) + 100f2c8: e0bff917 ldw r2,-28(fp) + 100f2cc: 10c00515 stw r3,20(r2) + ptcb->OSTCBPrev = (OS_TCB *)0; + 100f2d0: e0bff917 ldw r2,-28(fp) + 100f2d4: 10000615 stw zero,24(r2) + if (OSTCBList != (OS_TCB *)0) { + 100f2d8: d0a78617 ldw r2,-25064(gp) + 100f2dc: 1005003a cmpeq r2,r2,zero + 100f2e0: 1000031e bne r2,zero,100f2f0 + OSTCBList->OSTCBPrev = ptcb; + 100f2e4: d0e78617 ldw r3,-25064(gp) + 100f2e8: e0bff917 ldw r2,-28(fp) + 100f2ec: 18800615 stw r2,24(r3) + } + OSTCBList = ptcb; + 100f2f0: e0bff917 ldw r2,-28(fp) + 100f2f4: d0a78615 stw r2,-25064(gp) + OSRdyGrp |= ptcb->OSTCBBitY; /* Make task ready to run */ + 100f2f8: e0bff917 ldw r2,-28(fp) + 100f2fc: 10c00d83 ldbu r3,54(r2) + 100f300: d0a78f03 ldbu r2,-25028(gp) + 100f304: 1884b03a or r2,r3,r2 + 100f308: d0a78f05 stb r2,-25028(gp) + OSRdyTbl[ptcb->OSTCBY] |= ptcb->OSTCBBitX; + 100f30c: e0bff917 ldw r2,-28(fp) + 100f310: 10800d03 ldbu r2,52(r2) + 100f314: 11003fcc andi r4,r2,255 + 100f318: e0bff917 ldw r2,-28(fp) + 100f31c: 10800d03 ldbu r2,52(r2) + 100f320: 10c03fcc andi r3,r2,255 + 100f324: d0a78f44 addi r2,gp,-25027 + 100f328: 1885883a add r2,r3,r2 + 100f32c: 10c00003 ldbu r3,0(r2) + 100f330: e0bff917 ldw r2,-28(fp) + 100f334: 10800d43 ldbu r2,53(r2) + 100f338: 1884b03a or r2,r3,r2 + 100f33c: 1007883a mov r3,r2 + 100f340: d0a78f44 addi r2,gp,-25027 + 100f344: 2085883a add r2,r4,r2 + 100f348: 10c00005 stb r3,0(r2) + OSTaskCtr++; /* Increment the #tasks counter */ + 100f34c: d0a78b43 ldbu r2,-25043(gp) + 100f350: 10800044 addi r2,r2,1 + 100f354: d0a78b45 stb r2,-25043(gp) + 100f358: e0bff817 ldw r2,-32(fp) + 100f35c: e0bff415 stw r2,-48(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 100f360: e0bff417 ldw r2,-48(fp) + 100f364: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_NONE); + 100f368: e03fff15 stw zero,-4(fp) + 100f36c: 00000606 br 100f388 + 100f370: e0bff817 ldw r2,-32(fp) + 100f374: e0bff315 stw r2,-52(fp) + 100f378: e0bff317 ldw r2,-52(fp) + 100f37c: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_NO_MORE_TCB); + 100f380: 00801084 movi r2,66 + 100f384: e0bfff15 stw r2,-4(fp) + 100f388: e0bfff17 ldw r2,-4(fp) +} + 100f38c: e037883a mov sp,fp + 100f390: dfc00117 ldw ra,4(sp) + 100f394: df000017 ldw fp,0(sp) + 100f398: dec00204 addi sp,sp,8 + 100f39c: f800283a ret + +0100f3a0 : +********************************************************************************************************* +*/ + +#if OS_DEBUG_EN > 0 +void OSDebugInit (void) +{ + 100f3a0: defffe04 addi sp,sp,-8 + 100f3a4: df000115 stw fp,4(sp) + 100f3a8: df000104 addi fp,sp,4 + void *ptemp; + + + ptemp = (void *)&OSDebugEn; + 100f3ac: d0a01804 addi r2,gp,-32672 + 100f3b0: e0bfff15 stw r2,-4(fp) + + ptemp = (void *)&OSEndiannessTest; + 100f3b4: d0a01904 addi r2,gp,-32668 + 100f3b8: e0bfff15 stw r2,-4(fp) + + ptemp = (void *)&OSEventMax; + 100f3bc: d0a01a84 addi r2,gp,-32662 + 100f3c0: e0bfff15 stw r2,-4(fp) + ptemp = (void *)&OSEventNameSize; + 100f3c4: d0a01b04 addi r2,gp,-32660 + 100f3c8: e0bfff15 stw r2,-4(fp) + ptemp = (void *)&OSEventEn; + 100f3cc: d0a01a04 addi r2,gp,-32664 + 100f3d0: e0bfff15 stw r2,-4(fp) + ptemp = (void *)&OSEventSize; + 100f3d4: d0a01b84 addi r2,gp,-32658 + 100f3d8: e0bfff15 stw r2,-4(fp) + ptemp = (void *)&OSEventTblSize; + 100f3dc: d0a01c04 addi r2,gp,-32656 + 100f3e0: e0bfff15 stw r2,-4(fp) + ptemp = (void *)&OSEventMultiEn; + 100f3e4: d0a01c84 addi r2,gp,-32654 + 100f3e8: e0bfff15 stw r2,-4(fp) + + ptemp = (void *)&OSFlagEn; + 100f3ec: d0a01d04 addi r2,gp,-32652 + 100f3f0: e0bfff15 stw r2,-4(fp) + ptemp = (void *)&OSFlagGrpSize; + 100f3f4: d0a01d84 addi r2,gp,-32650 + 100f3f8: e0bfff15 stw r2,-4(fp) + ptemp = (void *)&OSFlagNodeSize; + 100f3fc: d0a01e04 addi r2,gp,-32648 + 100f400: e0bfff15 stw r2,-4(fp) + ptemp = (void *)&OSFlagWidth; + 100f404: d0a01e84 addi r2,gp,-32646 + 100f408: e0bfff15 stw r2,-4(fp) + ptemp = (void *)&OSFlagMax; + 100f40c: d0a01f04 addi r2,gp,-32644 + 100f410: e0bfff15 stw r2,-4(fp) + ptemp = (void *)&OSFlagNameSize; + 100f414: d0a01f84 addi r2,gp,-32642 + 100f418: e0bfff15 stw r2,-4(fp) + + ptemp = (void *)&OSLowestPrio; + 100f41c: d0a02004 addi r2,gp,-32640 + 100f420: e0bfff15 stw r2,-4(fp) + + ptemp = (void *)&OSMboxEn; + 100f424: d0a02084 addi r2,gp,-32638 + 100f428: e0bfff15 stw r2,-4(fp) + + ptemp = (void *)&OSMemEn; + 100f42c: d0a02104 addi r2,gp,-32636 + 100f430: e0bfff15 stw r2,-4(fp) + ptemp = (void *)&OSMemMax; + 100f434: d0a02184 addi r2,gp,-32634 + 100f438: e0bfff15 stw r2,-4(fp) + ptemp = (void *)&OSMemNameSize; + 100f43c: d0a02204 addi r2,gp,-32632 + 100f440: e0bfff15 stw r2,-4(fp) + ptemp = (void *)&OSMemSize; + 100f444: d0a02284 addi r2,gp,-32630 + 100f448: e0bfff15 stw r2,-4(fp) + ptemp = (void *)&OSMemTblSize; + 100f44c: d0a02304 addi r2,gp,-32628 + 100f450: e0bfff15 stw r2,-4(fp) + + ptemp = (void *)&OSMutexEn; + 100f454: d0a02384 addi r2,gp,-32626 + 100f458: e0bfff15 stw r2,-4(fp) + + ptemp = (void *)&OSPtrSize; + 100f45c: d0a02404 addi r2,gp,-32624 + 100f460: e0bfff15 stw r2,-4(fp) + + ptemp = (void *)&OSQEn; + 100f464: d0a02484 addi r2,gp,-32622 + 100f468: e0bfff15 stw r2,-4(fp) + ptemp = (void *)&OSQMax; + 100f46c: d0a02504 addi r2,gp,-32620 + 100f470: e0bfff15 stw r2,-4(fp) + ptemp = (void *)&OSQSize; + 100f474: d0a02584 addi r2,gp,-32618 + 100f478: e0bfff15 stw r2,-4(fp) + + ptemp = (void *)&OSRdyTblSize; + 100f47c: d0a02604 addi r2,gp,-32616 + 100f480: e0bfff15 stw r2,-4(fp) + + ptemp = (void *)&OSSemEn; + 100f484: d0a02684 addi r2,gp,-32614 + 100f488: e0bfff15 stw r2,-4(fp) + + ptemp = (void *)&OSStkWidth; + 100f48c: d0a02704 addi r2,gp,-32612 + 100f490: e0bfff15 stw r2,-4(fp) + + ptemp = (void *)&OSTaskCreateEn; + 100f494: d0a02784 addi r2,gp,-32610 + 100f498: e0bfff15 stw r2,-4(fp) + ptemp = (void *)&OSTaskCreateExtEn; + 100f49c: d0a02804 addi r2,gp,-32608 + 100f4a0: e0bfff15 stw r2,-4(fp) + ptemp = (void *)&OSTaskDelEn; + 100f4a4: d0a02884 addi r2,gp,-32606 + 100f4a8: e0bfff15 stw r2,-4(fp) + ptemp = (void *)&OSTaskIdleStkSize; + 100f4ac: d0a02904 addi r2,gp,-32604 + 100f4b0: e0bfff15 stw r2,-4(fp) + ptemp = (void *)&OSTaskProfileEn; + 100f4b4: d0a02984 addi r2,gp,-32602 + 100f4b8: e0bfff15 stw r2,-4(fp) + ptemp = (void *)&OSTaskMax; + 100f4bc: d0a02a04 addi r2,gp,-32600 + 100f4c0: e0bfff15 stw r2,-4(fp) + ptemp = (void *)&OSTaskNameSize; + 100f4c4: d0a02a84 addi r2,gp,-32598 + 100f4c8: e0bfff15 stw r2,-4(fp) + ptemp = (void *)&OSTaskStatEn; + 100f4cc: d0a02b04 addi r2,gp,-32596 + 100f4d0: e0bfff15 stw r2,-4(fp) + ptemp = (void *)&OSTaskStatStkSize; + 100f4d4: d0a02b84 addi r2,gp,-32594 + 100f4d8: e0bfff15 stw r2,-4(fp) + ptemp = (void *)&OSTaskStatStkChkEn; + 100f4dc: d0a02c04 addi r2,gp,-32592 + 100f4e0: e0bfff15 stw r2,-4(fp) + ptemp = (void *)&OSTaskSwHookEn; + 100f4e4: d0a02c84 addi r2,gp,-32590 + 100f4e8: e0bfff15 stw r2,-4(fp) + + ptemp = (void *)&OSTCBPrioTblMax; + 100f4ec: d0a02d04 addi r2,gp,-32588 + 100f4f0: e0bfff15 stw r2,-4(fp) + ptemp = (void *)&OSTCBSize; + 100f4f4: d0a02d84 addi r2,gp,-32586 + 100f4f8: e0bfff15 stw r2,-4(fp) + + ptemp = (void *)&OSTicksPerSec; + 100f4fc: d0a02e04 addi r2,gp,-32584 + 100f500: e0bfff15 stw r2,-4(fp) + ptemp = (void *)&OSTimeTickHookEn; + 100f504: d0a02e84 addi r2,gp,-32582 + 100f508: e0bfff15 stw r2,-4(fp) + + ptemp = (void *)&OSTmrWheelSize; + ptemp = (void *)&OSTmrWheelTblSize; +#endif + + ptemp = (void *)&OSVersionNbr; + 100f50c: d0a02f04 addi r2,gp,-32580 + 100f510: e0bfff15 stw r2,-4(fp) + + ptemp = (void *)&OSDataSize; + 100f514: d0a03404 addi r2,gp,-32560 + 100f518: e0bfff15 stw r2,-4(fp) + + ptemp = ptemp; /* Prevent compiler warning for 'ptemp' not being used! */ +} + 100f51c: e037883a mov sp,fp + 100f520: df000017 ldw fp,0(sp) + 100f524: dec00104 addi sp,sp,4 + 100f528: f800283a ret + +0100f52c : +********************************************************************************************************* +*/ + +#if OS_FLAG_ACCEPT_EN > 0 +OS_FLAGS OSFlagAccept (OS_FLAG_GRP *pgrp, OS_FLAGS flags, INT8U wait_type, INT8U *perr) +{ + 100f52c: defff104 addi sp,sp,-60 + 100f530: df000e15 stw fp,56(sp) + 100f534: df000e04 addi fp,sp,56 + 100f538: e13ffa15 stw r4,-24(fp) + 100f53c: e1fffd15 stw r7,-12(fp) + 100f540: e17ffb0d sth r5,-20(fp) + 100f544: e1bffc05 stb r6,-16(fp) + OS_FLAGS flags_rdy; + INT8U result; + BOOLEAN consume; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 100f548: e03ff815 stw zero,-32(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + 100f54c: e0bffd17 ldw r2,-12(fp) + 100f550: 1004c03a cmpne r2,r2,zero + 100f554: 1000021e bne r2,zero,100f560 + return ((OS_FLAGS)0); + 100f558: e03fff15 stw zero,-4(fp) + 100f55c: 0000bb06 br 100f84c + } + if (pgrp == (OS_FLAG_GRP *)0) { /* Validate 'pgrp' */ + 100f560: e0bffa17 ldw r2,-24(fp) + 100f564: 1004c03a cmpne r2,r2,zero + 100f568: 1000051e bne r2,zero,100f580 + *perr = OS_ERR_FLAG_INVALID_PGRP; + 100f56c: e0fffd17 ldw r3,-12(fp) + 100f570: 00801b84 movi r2,110 + 100f574: 18800005 stb r2,0(r3) + return ((OS_FLAGS)0); + 100f578: e03fff15 stw zero,-4(fp) + 100f57c: 0000b306 br 100f84c + } +#endif + if (pgrp->OSFlagType != OS_EVENT_TYPE_FLAG) { /* Validate event block type */ + 100f580: e0bffa17 ldw r2,-24(fp) + 100f584: 10800003 ldbu r2,0(r2) + 100f588: 10803fcc andi r2,r2,255 + 100f58c: 10800160 cmpeqi r2,r2,5 + 100f590: 1000051e bne r2,zero,100f5a8 + *perr = OS_ERR_EVENT_TYPE; + 100f594: e0fffd17 ldw r3,-12(fp) + 100f598: 00800044 movi r2,1 + 100f59c: 18800005 stb r2,0(r3) + return ((OS_FLAGS)0); + 100f5a0: e03fff15 stw zero,-4(fp) + 100f5a4: 0000a906 br 100f84c + } + result = (INT8U)(wait_type & OS_FLAG_CONSUME); + 100f5a8: e0fffc03 ldbu r3,-16(fp) + 100f5ac: 00bfe004 movi r2,-128 + 100f5b0: 1884703a and r2,r3,r2 + 100f5b4: e0bff945 stb r2,-27(fp) + if (result != (INT8U)0) { /* See if we need to consume the flags */ + 100f5b8: e0bff943 ldbu r2,-27(fp) + 100f5bc: 1005003a cmpeq r2,r2,zero + 100f5c0: 1000061e bne r2,zero,100f5dc + wait_type &= ~OS_FLAG_CONSUME; + 100f5c4: e0bffc03 ldbu r2,-16(fp) + 100f5c8: 10801fcc andi r2,r2,127 + 100f5cc: e0bffc05 stb r2,-16(fp) + consume = OS_TRUE; + 100f5d0: 00800044 movi r2,1 + 100f5d4: e0bff905 stb r2,-28(fp) + 100f5d8: 00000106 br 100f5e0 + } else { + consume = OS_FALSE; + 100f5dc: e03ff905 stb zero,-28(fp) + } +/*$PAGE*/ + *perr = OS_ERR_NONE; /* Assume NO error until proven otherwise. */ + 100f5e0: e0bffd17 ldw r2,-12(fp) + 100f5e4: 10000005 stb zero,0(r2) +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 100f5e8: 0005303a rdctl r2,status + 100f5ec: e0bff715 stw r2,-36(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 100f5f0: e0fff717 ldw r3,-36(fp) + 100f5f4: 00bfff84 movi r2,-2 + 100f5f8: 1884703a and r2,r3,r2 + 100f5fc: 1001703a wrctl status,r2 + + return context; + 100f600: e0bff717 ldw r2,-36(fp) + OS_ENTER_CRITICAL(); + 100f604: e0bff815 stw r2,-32(fp) + switch (wait_type) { + 100f608: e0bffc03 ldbu r2,-16(fp) + 100f60c: e0bffe15 stw r2,-8(fp) + 100f610: e0fffe17 ldw r3,-8(fp) + 100f614: 18800060 cmpeqi r2,r3,1 + 100f618: 1000651e bne r2,zero,100f7b0 + 100f61c: e0fffe17 ldw r3,-8(fp) + 100f620: 18800088 cmpgei r2,r3,2 + 100f624: 1000041e bne r2,zero,100f638 + 100f628: e0fffe17 ldw r3,-8(fp) + 100f62c: 1805003a cmpeq r2,r3,zero + 100f630: 1000421e bne r2,zero,100f73c + 100f634: 00007b06 br 100f824 + 100f638: e0fffe17 ldw r3,-8(fp) + 100f63c: 188000a0 cmpeqi r2,r3,2 + 100f640: 1000041e bne r2,zero,100f654 + 100f644: e0fffe17 ldw r3,-8(fp) + 100f648: 188000e0 cmpeqi r2,r3,3 + 100f64c: 10001e1e bne r2,zero,100f6c8 + 100f650: 00007406 br 100f824 + case OS_FLAG_WAIT_SET_ALL: /* See if all required flags are set */ + flags_rdy = (OS_FLAGS)(pgrp->OSFlagFlags & flags); /* Extract only the bits we want */ + 100f654: e0bffa17 ldw r2,-24(fp) + 100f658: 10c0020b ldhu r3,8(r2) + 100f65c: e0bffb0b ldhu r2,-20(fp) + 100f660: 1884703a and r2,r3,r2 + 100f664: e0bff98d sth r2,-26(fp) + if (flags_rdy == flags) { /* Must match ALL the bits that we want */ + 100f668: e0fff98b ldhu r3,-26(fp) + 100f66c: e0bffb0b ldhu r2,-20(fp) + 100f670: 18800d1e bne r3,r2,100f6a8 + if (consume == OS_TRUE) { /* See if we need to consume the flags */ + 100f674: e0bff903 ldbu r2,-28(fp) + 100f678: 10800058 cmpnei r2,r2,1 + 100f67c: 10000d1e bne r2,zero,100f6b4 + pgrp->OSFlagFlags &= ~flags_rdy; /* Clear ONLY the flags that we wanted */ + 100f680: e0bffa17 ldw r2,-24(fp) + 100f684: 1080020b ldhu r2,8(r2) + 100f688: 1007883a mov r3,r2 + 100f68c: e0bff98b ldhu r2,-26(fp) + 100f690: 0084303a nor r2,zero,r2 + 100f694: 1884703a and r2,r3,r2 + 100f698: 1007883a mov r3,r2 + 100f69c: e0bffa17 ldw r2,-24(fp) + 100f6a0: 10c0020d sth r3,8(r2) + 100f6a4: 00000306 br 100f6b4 + } + } else { + *perr = OS_ERR_FLAG_NOT_RDY; + 100f6a8: e0fffd17 ldw r3,-12(fp) + 100f6ac: 00801c04 movi r2,112 + 100f6b0: 18800005 stb r2,0(r3) + 100f6b4: e0bff817 ldw r2,-32(fp) + 100f6b8: e0bff615 stw r2,-40(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 100f6bc: e0bff617 ldw r2,-40(fp) + 100f6c0: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); + break; + 100f6c4: 00005f06 br 100f844 + + case OS_FLAG_WAIT_SET_ANY: + flags_rdy = (OS_FLAGS)(pgrp->OSFlagFlags & flags); /* Extract only the bits we want */ + 100f6c8: e0bffa17 ldw r2,-24(fp) + 100f6cc: 10c0020b ldhu r3,8(r2) + 100f6d0: e0bffb0b ldhu r2,-20(fp) + 100f6d4: 1884703a and r2,r3,r2 + 100f6d8: e0bff98d sth r2,-26(fp) + if (flags_rdy != (OS_FLAGS)0) { /* See if any flag set */ + 100f6dc: e0bff98b ldhu r2,-26(fp) + 100f6e0: 1005003a cmpeq r2,r2,zero + 100f6e4: 10000d1e bne r2,zero,100f71c + if (consume == OS_TRUE) { /* See if we need to consume the flags */ + 100f6e8: e0bff903 ldbu r2,-28(fp) + 100f6ec: 10800058 cmpnei r2,r2,1 + 100f6f0: 10000d1e bne r2,zero,100f728 + pgrp->OSFlagFlags &= ~flags_rdy; /* Clear ONLY the flags that we got */ + 100f6f4: e0bffa17 ldw r2,-24(fp) + 100f6f8: 1080020b ldhu r2,8(r2) + 100f6fc: 1007883a mov r3,r2 + 100f700: e0bff98b ldhu r2,-26(fp) + 100f704: 0084303a nor r2,zero,r2 + 100f708: 1884703a and r2,r3,r2 + 100f70c: 1007883a mov r3,r2 + 100f710: e0bffa17 ldw r2,-24(fp) + 100f714: 10c0020d sth r3,8(r2) + 100f718: 00000306 br 100f728 + } + } else { + *perr = OS_ERR_FLAG_NOT_RDY; + 100f71c: e0fffd17 ldw r3,-12(fp) + 100f720: 00801c04 movi r2,112 + 100f724: 18800005 stb r2,0(r3) + 100f728: e0bff817 ldw r2,-32(fp) + 100f72c: e0bff515 stw r2,-44(fp) + 100f730: e0bff517 ldw r2,-44(fp) + 100f734: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); + break; + 100f738: 00004206 br 100f844 + +#if OS_FLAG_WAIT_CLR_EN > 0 + case OS_FLAG_WAIT_CLR_ALL: /* See if all required flags are cleared */ + flags_rdy = (OS_FLAGS)(~pgrp->OSFlagFlags & flags); /* Extract only the bits we want */ + 100f73c: e0bffa17 ldw r2,-24(fp) + 100f740: 1080020b ldhu r2,8(r2) + 100f744: 0084303a nor r2,zero,r2 + 100f748: 1007883a mov r3,r2 + 100f74c: e0bffb0b ldhu r2,-20(fp) + 100f750: 1884703a and r2,r3,r2 + 100f754: e0bff98d sth r2,-26(fp) + if (flags_rdy == flags) { /* Must match ALL the bits that we want */ + 100f758: e0fff98b ldhu r3,-26(fp) + 100f75c: e0bffb0b ldhu r2,-20(fp) + 100f760: 18800b1e bne r3,r2,100f790 + if (consume == OS_TRUE) { /* See if we need to consume the flags */ + 100f764: e0bff903 ldbu r2,-28(fp) + 100f768: 10800058 cmpnei r2,r2,1 + 100f76c: 10000b1e bne r2,zero,100f79c + pgrp->OSFlagFlags |= flags_rdy; /* Set ONLY the flags that we wanted */ + 100f770: e0bffa17 ldw r2,-24(fp) + 100f774: 10c0020b ldhu r3,8(r2) + 100f778: e0bff98b ldhu r2,-26(fp) + 100f77c: 1884b03a or r2,r3,r2 + 100f780: 1007883a mov r3,r2 + 100f784: e0bffa17 ldw r2,-24(fp) + 100f788: 10c0020d sth r3,8(r2) + 100f78c: 00000306 br 100f79c + } + } else { + *perr = OS_ERR_FLAG_NOT_RDY; + 100f790: e0fffd17 ldw r3,-12(fp) + 100f794: 00801c04 movi r2,112 + 100f798: 18800005 stb r2,0(r3) + 100f79c: e0bff817 ldw r2,-32(fp) + 100f7a0: e0bff415 stw r2,-48(fp) + 100f7a4: e0bff417 ldw r2,-48(fp) + 100f7a8: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); + break; + 100f7ac: 00002506 br 100f844 + + case OS_FLAG_WAIT_CLR_ANY: + flags_rdy = (OS_FLAGS)(~pgrp->OSFlagFlags & flags); /* Extract only the bits we want */ + 100f7b0: e0bffa17 ldw r2,-24(fp) + 100f7b4: 1080020b ldhu r2,8(r2) + 100f7b8: 0084303a nor r2,zero,r2 + 100f7bc: 1007883a mov r3,r2 + 100f7c0: e0bffb0b ldhu r2,-20(fp) + 100f7c4: 1884703a and r2,r3,r2 + 100f7c8: e0bff98d sth r2,-26(fp) + if (flags_rdy != (OS_FLAGS)0) { /* See if any flag cleared */ + 100f7cc: e0bff98b ldhu r2,-26(fp) + 100f7d0: 1005003a cmpeq r2,r2,zero + 100f7d4: 10000b1e bne r2,zero,100f804 + if (consume == OS_TRUE) { /* See if we need to consume the flags */ + 100f7d8: e0bff903 ldbu r2,-28(fp) + 100f7dc: 10800058 cmpnei r2,r2,1 + 100f7e0: 10000b1e bne r2,zero,100f810 + pgrp->OSFlagFlags |= flags_rdy; /* Set ONLY the flags that we got */ + 100f7e4: e0bffa17 ldw r2,-24(fp) + 100f7e8: 10c0020b ldhu r3,8(r2) + 100f7ec: e0bff98b ldhu r2,-26(fp) + 100f7f0: 1884b03a or r2,r3,r2 + 100f7f4: 1007883a mov r3,r2 + 100f7f8: e0bffa17 ldw r2,-24(fp) + 100f7fc: 10c0020d sth r3,8(r2) + 100f800: 00000306 br 100f810 + } + } else { + *perr = OS_ERR_FLAG_NOT_RDY; + 100f804: e0fffd17 ldw r3,-12(fp) + 100f808: 00801c04 movi r2,112 + 100f80c: 18800005 stb r2,0(r3) + 100f810: e0bff817 ldw r2,-32(fp) + 100f814: e0bff315 stw r2,-52(fp) + 100f818: e0bff317 ldw r2,-52(fp) + 100f81c: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); + break; + 100f820: 00000806 br 100f844 + 100f824: e0bff817 ldw r2,-32(fp) + 100f828: e0bff215 stw r2,-56(fp) + 100f82c: e0bff217 ldw r2,-56(fp) + 100f830: 1001703a wrctl status,r2 +#endif + + default: + OS_EXIT_CRITICAL(); + flags_rdy = (OS_FLAGS)0; + 100f834: e03ff98d sth zero,-26(fp) + *perr = OS_ERR_FLAG_WAIT_TYPE; + 100f838: e0fffd17 ldw r3,-12(fp) + 100f83c: 00801bc4 movi r2,111 + 100f840: 18800005 stb r2,0(r3) + break; + } + return (flags_rdy); + 100f844: e0bff98b ldhu r2,-26(fp) + 100f848: e0bfff15 stw r2,-4(fp) + 100f84c: e0bfff17 ldw r2,-4(fp) +} + 100f850: e037883a mov sp,fp + 100f854: df000017 ldw fp,0(sp) + 100f858: dec00104 addi sp,sp,4 + 100f85c: f800283a ret + +0100f860 : +* Called from: Task ONLY +********************************************************************************************************* +*/ + +OS_FLAG_GRP *OSFlagCreate (OS_FLAGS flags, INT8U *perr) +{ + 100f860: defff704 addi sp,sp,-36 + 100f864: df000815 stw fp,32(sp) + 100f868: df000804 addi fp,sp,32 + 100f86c: e17ffe15 stw r5,-8(fp) + 100f870: e13ffd0d sth r4,-12(fp) + OS_FLAG_GRP *pgrp; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 100f874: e03ffb15 stw zero,-20(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + 100f878: e0bffe17 ldw r2,-8(fp) + 100f87c: 1004c03a cmpne r2,r2,zero + 100f880: 1000021e bne r2,zero,100f88c + return ((OS_FLAG_GRP *)0); + 100f884: e03fff15 stw zero,-4(fp) + 100f888: 00003f06 br 100f988 + } +#endif + if (OSIntNesting > 0) { /* See if called from ISR ... */ + 100f88c: 008040b4 movhi r2,258 + 100f890: 10b31e04 addi r2,r2,-13192 + 100f894: 10800003 ldbu r2,0(r2) + 100f898: 10803fcc andi r2,r2,255 + 100f89c: 1005003a cmpeq r2,r2,zero + 100f8a0: 1000051e bne r2,zero,100f8b8 + *perr = OS_ERR_CREATE_ISR; /* ... can't CREATE from an ISR */ + 100f8a4: e0fffe17 ldw r3,-8(fp) + 100f8a8: 00800404 movi r2,16 + 100f8ac: 18800005 stb r2,0(r3) + return ((OS_FLAG_GRP *)0); + 100f8b0: e03fff15 stw zero,-4(fp) + 100f8b4: 00003406 br 100f988 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 100f8b8: 0005303a rdctl r2,status + 100f8bc: e0bffa15 stw r2,-24(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 100f8c0: e0fffa17 ldw r3,-24(fp) + 100f8c4: 00bfff84 movi r2,-2 + 100f8c8: 1884703a and r2,r3,r2 + 100f8cc: 1001703a wrctl status,r2 + + return context; + 100f8d0: e0bffa17 ldw r2,-24(fp) + } + OS_ENTER_CRITICAL(); + 100f8d4: e0bffb15 stw r2,-20(fp) + pgrp = OSFlagFreeList; /* Get next free event flag */ + 100f8d8: 008040b4 movhi r2,258 + 100f8dc: 10b32104 addi r2,r2,-13180 + 100f8e0: 10800017 ldw r2,0(r2) + 100f8e4: e0bffc15 stw r2,-16(fp) + if (pgrp != (OS_FLAG_GRP *)0) { /* See if we have event flag groups available */ + 100f8e8: e0bffc17 ldw r2,-16(fp) + 100f8ec: 1005003a cmpeq r2,r2,zero + 100f8f0: 10001c1e bne r2,zero,100f964 + /* Adjust free list */ + OSFlagFreeList = (OS_FLAG_GRP *)OSFlagFreeList->OSFlagWaitList; + 100f8f4: 008040b4 movhi r2,258 + 100f8f8: 10b32104 addi r2,r2,-13180 + 100f8fc: 10800017 ldw r2,0(r2) + 100f900: 10800117 ldw r2,4(r2) + 100f904: 1007883a mov r3,r2 + 100f908: 008040b4 movhi r2,258 + 100f90c: 10b32104 addi r2,r2,-13180 + 100f910: 10c00015 stw r3,0(r2) + pgrp->OSFlagType = OS_EVENT_TYPE_FLAG; /* Set to event flag group type */ + 100f914: e0fffc17 ldw r3,-16(fp) + 100f918: 00800144 movi r2,5 + 100f91c: 18800005 stb r2,0(r3) + pgrp->OSFlagFlags = flags; /* Set to desired initial value */ + 100f920: e0fffc17 ldw r3,-16(fp) + 100f924: e0bffd0b ldhu r2,-12(fp) + 100f928: 1880020d sth r2,8(r3) + pgrp->OSFlagWaitList = (void *)0; /* Clear list of tasks waiting on flags */ + 100f92c: e0bffc17 ldw r2,-16(fp) + 100f930: 10000115 stw zero,4(r2) +#if OS_FLAG_NAME_SIZE > 1 + pgrp->OSFlagName[0] = '?'; + 100f934: e0fffc17 ldw r3,-16(fp) + 100f938: 00800fc4 movi r2,63 + 100f93c: 18800285 stb r2,10(r3) + pgrp->OSFlagName[1] = OS_ASCII_NUL; + 100f940: e0bffc17 ldw r2,-16(fp) + 100f944: 100002c5 stb zero,11(r2) + 100f948: e0bffb17 ldw r2,-20(fp) + 100f94c: e0bff915 stw r2,-28(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 100f950: e0bff917 ldw r2,-28(fp) + 100f954: 1001703a wrctl status,r2 +#endif + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + 100f958: e0bffe17 ldw r2,-8(fp) + 100f95c: 10000005 stb zero,0(r2) + 100f960: 00000706 br 100f980 + 100f964: e0bffb17 ldw r2,-20(fp) + 100f968: e0bff815 stw r2,-32(fp) + 100f96c: e0bff817 ldw r2,-32(fp) + 100f970: 1001703a wrctl status,r2 + } else { + OS_EXIT_CRITICAL(); + *perr = OS_ERR_FLAG_GRP_DEPLETED; + 100f974: e0fffe17 ldw r3,-8(fp) + 100f978: 00801c84 movi r2,114 + 100f97c: 18800005 stb r2,0(r3) + } + return (pgrp); /* Return pointer to event flag group */ + 100f980: e0bffc17 ldw r2,-16(fp) + 100f984: e0bfff15 stw r2,-4(fp) + 100f988: e0bfff17 ldw r2,-4(fp) +} + 100f98c: e037883a mov sp,fp + 100f990: df000017 ldw fp,0(sp) + 100f994: dec00104 addi sp,sp,4 + 100f998: f800283a ret + +0100f99c : +********************************************************************************************************* +*/ + +#if OS_FLAG_DEL_EN > 0 +OS_FLAG_GRP *OSFlagDel (OS_FLAG_GRP *pgrp, INT8U opt, INT8U *perr) +{ + 100f99c: defff004 addi sp,sp,-64 + 100f9a0: dfc00f15 stw ra,60(sp) + 100f9a4: df000e15 stw fp,56(sp) + 100f9a8: df000e04 addi fp,sp,56 + 100f9ac: e13ffb15 stw r4,-20(fp) + 100f9b0: e1bffd15 stw r6,-12(fp) + 100f9b4: e17ffc05 stb r5,-16(fp) + BOOLEAN tasks_waiting; + OS_FLAG_NODE *pnode; + OS_FLAG_GRP *pgrp_return; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 100f9b8: e03ff715 stw zero,-36(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + 100f9bc: e0bffd17 ldw r2,-12(fp) + 100f9c0: 1004c03a cmpne r2,r2,zero + 100f9c4: 1000031e bne r2,zero,100f9d4 + return (pgrp); + 100f9c8: e0bffb17 ldw r2,-20(fp) + 100f9cc: e0bfff15 stw r2,-4(fp) + 100f9d0: 00009606 br 100fc2c + } + if (pgrp == (OS_FLAG_GRP *)0) { /* Validate 'pgrp' */ + 100f9d4: e0bffb17 ldw r2,-20(fp) + 100f9d8: 1004c03a cmpne r2,r2,zero + 100f9dc: 1000061e bne r2,zero,100f9f8 + *perr = OS_ERR_FLAG_INVALID_PGRP; + 100f9e0: e0fffd17 ldw r3,-12(fp) + 100f9e4: 00801b84 movi r2,110 + 100f9e8: 18800005 stb r2,0(r3) + return (pgrp); + 100f9ec: e0fffb17 ldw r3,-20(fp) + 100f9f0: e0ffff15 stw r3,-4(fp) + 100f9f4: 00008d06 br 100fc2c + } +#endif + if (OSIntNesting > 0) { /* See if called from ISR ... */ + 100f9f8: 008040b4 movhi r2,258 + 100f9fc: 10b31e04 addi r2,r2,-13192 + 100fa00: 10800003 ldbu r2,0(r2) + 100fa04: 10803fcc andi r2,r2,255 + 100fa08: 1005003a cmpeq r2,r2,zero + 100fa0c: 1000061e bne r2,zero,100fa28 + *perr = OS_ERR_DEL_ISR; /* ... can't DELETE from an ISR */ + 100fa10: e0fffd17 ldw r3,-12(fp) + 100fa14: 008003c4 movi r2,15 + 100fa18: 18800005 stb r2,0(r3) + return (pgrp); + 100fa1c: e0bffb17 ldw r2,-20(fp) + 100fa20: e0bfff15 stw r2,-4(fp) + 100fa24: 00008106 br 100fc2c + } + if (pgrp->OSFlagType != OS_EVENT_TYPE_FLAG) { /* Validate event group type */ + 100fa28: e0bffb17 ldw r2,-20(fp) + 100fa2c: 10800003 ldbu r2,0(r2) + 100fa30: 10803fcc andi r2,r2,255 + 100fa34: 10800160 cmpeqi r2,r2,5 + 100fa38: 1000061e bne r2,zero,100fa54 + *perr = OS_ERR_EVENT_TYPE; + 100fa3c: e0fffd17 ldw r3,-12(fp) + 100fa40: 00800044 movi r2,1 + 100fa44: 18800005 stb r2,0(r3) + return (pgrp); + 100fa48: e0fffb17 ldw r3,-20(fp) + 100fa4c: e0ffff15 stw r3,-4(fp) + 100fa50: 00007606 br 100fc2c +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 100fa54: 0005303a rdctl r2,status + 100fa58: e0bff615 stw r2,-40(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 100fa5c: e0fff617 ldw r3,-40(fp) + 100fa60: 00bfff84 movi r2,-2 + 100fa64: 1884703a and r2,r3,r2 + 100fa68: 1001703a wrctl status,r2 + + return context; + 100fa6c: e0bff617 ldw r2,-40(fp) + } + OS_ENTER_CRITICAL(); + 100fa70: e0bff715 stw r2,-36(fp) + if (pgrp->OSFlagWaitList != (void *)0) { /* See if any tasks waiting on event flags */ + 100fa74: e0bffb17 ldw r2,-20(fp) + 100fa78: 10800117 ldw r2,4(r2) + 100fa7c: 1005003a cmpeq r2,r2,zero + 100fa80: 1000031e bne r2,zero,100fa90 + tasks_waiting = OS_TRUE; /* Yes */ + 100fa84: 00800044 movi r2,1 + 100fa88: e0bffa05 stb r2,-24(fp) + 100fa8c: 00000106 br 100fa94 + } else { + tasks_waiting = OS_FALSE; /* No */ + 100fa90: e03ffa05 stb zero,-24(fp) + } + switch (opt) { + 100fa94: e0bffc03 ldbu r2,-16(fp) + 100fa98: e0bffe15 stw r2,-8(fp) + 100fa9c: e0fffe17 ldw r3,-8(fp) + 100faa0: 1805003a cmpeq r2,r3,zero + 100faa4: 1000041e bne r2,zero,100fab8 + 100faa8: e0fffe17 ldw r3,-8(fp) + 100faac: 18800060 cmpeqi r2,r3,1 + 100fab0: 1000281e bne r2,zero,100fb54 + 100fab4: 00005206 br 100fc00 + case OS_DEL_NO_PEND: /* Delete group if no task waiting */ + if (tasks_waiting == OS_FALSE) { + 100fab8: e0bffa03 ldbu r2,-24(fp) + 100fabc: 1004c03a cmpne r2,r2,zero + 100fac0: 10001a1e bne r2,zero,100fb2c +#if OS_FLAG_NAME_SIZE > 1 + pgrp->OSFlagName[0] = '?'; /* Unknown name */ + 100fac4: e0fffb17 ldw r3,-20(fp) + 100fac8: 00800fc4 movi r2,63 + 100facc: 18800285 stb r2,10(r3) + pgrp->OSFlagName[1] = OS_ASCII_NUL; + 100fad0: e0bffb17 ldw r2,-20(fp) + 100fad4: 100002c5 stb zero,11(r2) +#endif + pgrp->OSFlagType = OS_EVENT_TYPE_UNUSED; + 100fad8: e0bffb17 ldw r2,-20(fp) + 100fadc: 10000005 stb zero,0(r2) + pgrp->OSFlagWaitList = (void *)OSFlagFreeList; /* Return group to free list */ + 100fae0: 008040b4 movhi r2,258 + 100fae4: 10b32104 addi r2,r2,-13180 + 100fae8: 10c00017 ldw r3,0(r2) + 100faec: e0bffb17 ldw r2,-20(fp) + 100faf0: 10c00115 stw r3,4(r2) + pgrp->OSFlagFlags = (OS_FLAGS)0; + 100faf4: e0bffb17 ldw r2,-20(fp) + 100faf8: 1000020d sth zero,8(r2) + OSFlagFreeList = pgrp; + 100fafc: 00c040b4 movhi r3,258 + 100fb00: 18f32104 addi r3,r3,-13180 + 100fb04: e0bffb17 ldw r2,-20(fp) + 100fb08: 18800015 stw r2,0(r3) + 100fb0c: e0bff717 ldw r2,-36(fp) + 100fb10: e0bff515 stw r2,-44(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 100fb14: e0bff517 ldw r2,-44(fp) + 100fb18: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + 100fb1c: e0bffd17 ldw r2,-12(fp) + 100fb20: 10000005 stb zero,0(r2) + pgrp_return = (OS_FLAG_GRP *)0; /* Event Flag Group has been deleted */ + 100fb24: e03ff815 stw zero,-32(fp) + 100fb28: 00003e06 br 100fc24 + 100fb2c: e0bff717 ldw r2,-36(fp) + 100fb30: e0bff415 stw r2,-48(fp) + 100fb34: e0bff417 ldw r2,-48(fp) + 100fb38: 1001703a wrctl status,r2 + } else { + OS_EXIT_CRITICAL(); + *perr = OS_ERR_TASK_WAITING; + 100fb3c: e0fffd17 ldw r3,-12(fp) + 100fb40: 00801244 movi r2,73 + 100fb44: 18800005 stb r2,0(r3) + pgrp_return = pgrp; + 100fb48: e0bffb17 ldw r2,-20(fp) + 100fb4c: e0bff815 stw r2,-32(fp) + } + break; + 100fb50: 00003406 br 100fc24 + + case OS_DEL_ALWAYS: /* Always delete the event flag group */ + pnode = (OS_FLAG_NODE *)pgrp->OSFlagWaitList; + 100fb54: e0bffb17 ldw r2,-20(fp) + 100fb58: 10800117 ldw r2,4(r2) + 100fb5c: e0bff915 stw r2,-28(fp) + while (pnode != (OS_FLAG_NODE *)0) { /* Ready ALL tasks waiting for flags */ + 100fb60: 00000606 br 100fb7c + (void)OS_FlagTaskRdy(pnode, (OS_FLAGS)0); + 100fb64: e13ff917 ldw r4,-28(fp) + 100fb68: 000b883a mov r5,zero + 100fb6c: 1010cac0 call 1010cac + pnode = (OS_FLAG_NODE *)pnode->OSFlagNodeNext; + 100fb70: e0bff917 ldw r2,-28(fp) + 100fb74: 10800017 ldw r2,0(r2) + 100fb78: e0bff915 stw r2,-28(fp) + } + break; + + case OS_DEL_ALWAYS: /* Always delete the event flag group */ + pnode = (OS_FLAG_NODE *)pgrp->OSFlagWaitList; + while (pnode != (OS_FLAG_NODE *)0) { /* Ready ALL tasks waiting for flags */ + 100fb7c: e0bff917 ldw r2,-28(fp) + 100fb80: 1004c03a cmpne r2,r2,zero + 100fb84: 103ff71e bne r2,zero,100fb64 + (void)OS_FlagTaskRdy(pnode, (OS_FLAGS)0); + pnode = (OS_FLAG_NODE *)pnode->OSFlagNodeNext; + } +#if OS_FLAG_NAME_SIZE > 1 + pgrp->OSFlagName[0] = '?'; /* Unknown name */ + 100fb88: e0fffb17 ldw r3,-20(fp) + 100fb8c: 00800fc4 movi r2,63 + 100fb90: 18800285 stb r2,10(r3) + pgrp->OSFlagName[1] = OS_ASCII_NUL; + 100fb94: e0bffb17 ldw r2,-20(fp) + 100fb98: 100002c5 stb zero,11(r2) +#endif + pgrp->OSFlagType = OS_EVENT_TYPE_UNUSED; + 100fb9c: e0bffb17 ldw r2,-20(fp) + 100fba0: 10000005 stb zero,0(r2) + pgrp->OSFlagWaitList = (void *)OSFlagFreeList;/* Return group to free list */ + 100fba4: 008040b4 movhi r2,258 + 100fba8: 10b32104 addi r2,r2,-13180 + 100fbac: 10c00017 ldw r3,0(r2) + 100fbb0: e0bffb17 ldw r2,-20(fp) + 100fbb4: 10c00115 stw r3,4(r2) + pgrp->OSFlagFlags = (OS_FLAGS)0; + 100fbb8: e0bffb17 ldw r2,-20(fp) + 100fbbc: 1000020d sth zero,8(r2) + OSFlagFreeList = pgrp; + 100fbc0: 00c040b4 movhi r3,258 + 100fbc4: 18f32104 addi r3,r3,-13180 + 100fbc8: e0bffb17 ldw r2,-20(fp) + 100fbcc: 18800015 stw r2,0(r3) + 100fbd0: e0bff717 ldw r2,-36(fp) + 100fbd4: e0bff315 stw r2,-52(fp) + 100fbd8: e0bff317 ldw r2,-52(fp) + 100fbdc: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + if (tasks_waiting == OS_TRUE) { /* Reschedule only if task(s) were waiting */ + 100fbe0: e0bffa03 ldbu r2,-24(fp) + 100fbe4: 10800058 cmpnei r2,r2,1 + 100fbe8: 1000011e bne r2,zero,100fbf0 + OS_Sched(); /* Find highest priority task ready to run */ + 100fbec: 100ecb80 call 100ecb8 + } + *perr = OS_ERR_NONE; + 100fbf0: e0bffd17 ldw r2,-12(fp) + 100fbf4: 10000005 stb zero,0(r2) + pgrp_return = (OS_FLAG_GRP *)0; /* Event Flag Group has been deleted */ + 100fbf8: e03ff815 stw zero,-32(fp) + break; + 100fbfc: 00000906 br 100fc24 + 100fc00: e0bff717 ldw r2,-36(fp) + 100fc04: e0bff215 stw r2,-56(fp) + 100fc08: e0bff217 ldw r2,-56(fp) + 100fc0c: 1001703a wrctl status,r2 + + default: + OS_EXIT_CRITICAL(); + *perr = OS_ERR_INVALID_OPT; + 100fc10: e0fffd17 ldw r3,-12(fp) + 100fc14: 008001c4 movi r2,7 + 100fc18: 18800005 stb r2,0(r3) + pgrp_return = pgrp; + 100fc1c: e0bffb17 ldw r2,-20(fp) + 100fc20: e0bff815 stw r2,-32(fp) + break; + } + return (pgrp_return); + 100fc24: e0bff817 ldw r2,-32(fp) + 100fc28: e0bfff15 stw r2,-4(fp) + 100fc2c: e0bfff17 ldw r2,-4(fp) +} + 100fc30: e037883a mov sp,fp + 100fc34: dfc00117 ldw ra,4(sp) + 100fc38: df000017 ldw fp,0(sp) + 100fc3c: dec00204 addi sp,sp,8 + 100fc40: f800283a ret + +0100fc44 : +********************************************************************************************************* +*/ + +#if OS_FLAG_NAME_SIZE > 1 +INT8U OSFlagNameGet (OS_FLAG_GRP *pgrp, INT8U *pname, INT8U *perr) +{ + 100fc44: defff504 addi sp,sp,-44 + 100fc48: dfc00a15 stw ra,40(sp) + 100fc4c: df000915 stw fp,36(sp) + 100fc50: df000904 addi fp,sp,36 + 100fc54: e13ffc15 stw r4,-16(fp) + 100fc58: e17ffd15 stw r5,-12(fp) + 100fc5c: e1bffe15 stw r6,-8(fp) + INT8U len; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 100fc60: e03ffa15 stw zero,-24(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + 100fc64: e0bffe17 ldw r2,-8(fp) + 100fc68: 1004c03a cmpne r2,r2,zero + 100fc6c: 1000021e bne r2,zero,100fc78 + return (0); + 100fc70: e03fff15 stw zero,-4(fp) + 100fc74: 00003e06 br 100fd70 + } + if (pgrp == (OS_FLAG_GRP *)0) { /* Is 'pgrp' a NULL pointer? */ + 100fc78: e0bffc17 ldw r2,-16(fp) + 100fc7c: 1004c03a cmpne r2,r2,zero + 100fc80: 1000051e bne r2,zero,100fc98 + *perr = OS_ERR_FLAG_INVALID_PGRP; + 100fc84: e0fffe17 ldw r3,-8(fp) + 100fc88: 00801b84 movi r2,110 + 100fc8c: 18800005 stb r2,0(r3) + return (0); + 100fc90: e03fff15 stw zero,-4(fp) + 100fc94: 00003606 br 100fd70 + } + if (pname == (INT8U *)0) { /* Is 'pname' a NULL pointer? */ + 100fc98: e0bffd17 ldw r2,-12(fp) + 100fc9c: 1004c03a cmpne r2,r2,zero + 100fca0: 1000051e bne r2,zero,100fcb8 + *perr = OS_ERR_PNAME_NULL; + 100fca4: e0fffe17 ldw r3,-8(fp) + 100fca8: 00800304 movi r2,12 + 100fcac: 18800005 stb r2,0(r3) + return (0); + 100fcb0: e03fff15 stw zero,-4(fp) + 100fcb4: 00002e06 br 100fd70 + } +#endif + if (OSIntNesting > 0) { /* See if trying to call from an ISR */ + 100fcb8: 008040b4 movhi r2,258 + 100fcbc: 10b31e04 addi r2,r2,-13192 + 100fcc0: 10800003 ldbu r2,0(r2) + 100fcc4: 10803fcc andi r2,r2,255 + 100fcc8: 1005003a cmpeq r2,r2,zero + 100fccc: 1000051e bne r2,zero,100fce4 + *perr = OS_ERR_NAME_GET_ISR; + 100fcd0: e0fffe17 ldw r3,-8(fp) + 100fcd4: 00800444 movi r2,17 + 100fcd8: 18800005 stb r2,0(r3) + return (0); + 100fcdc: e03fff15 stw zero,-4(fp) + 100fce0: 00002306 br 100fd70 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 100fce4: 0005303a rdctl r2,status + 100fce8: e0bff915 stw r2,-28(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 100fcec: e0fff917 ldw r3,-28(fp) + 100fcf0: 00bfff84 movi r2,-2 + 100fcf4: 1884703a and r2,r3,r2 + 100fcf8: 1001703a wrctl status,r2 + + return context; + 100fcfc: e0bff917 ldw r2,-28(fp) + } + OS_ENTER_CRITICAL(); + 100fd00: e0bffa15 stw r2,-24(fp) + if (pgrp->OSFlagType != OS_EVENT_TYPE_FLAG) { + 100fd04: e0bffc17 ldw r2,-16(fp) + 100fd08: 10800003 ldbu r2,0(r2) + 100fd0c: 10803fcc andi r2,r2,255 + 100fd10: 10800160 cmpeqi r2,r2,5 + 100fd14: 1000091e bne r2,zero,100fd3c + 100fd18: e0bffa17 ldw r2,-24(fp) + 100fd1c: e0bff815 stw r2,-32(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 100fd20: e0bff817 ldw r2,-32(fp) + 100fd24: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + *perr = OS_ERR_EVENT_TYPE; + 100fd28: e0fffe17 ldw r3,-8(fp) + 100fd2c: 00800044 movi r2,1 + 100fd30: 18800005 stb r2,0(r3) + return (0); + 100fd34: e03fff15 stw zero,-4(fp) + 100fd38: 00000d06 br 100fd70 + } + len = OS_StrCopy(pname, pgrp->OSFlagName); /* Copy name from OS_FLAG_GRP */ + 100fd3c: e0bffc17 ldw r2,-16(fp) + 100fd40: 11400284 addi r5,r2,10 + 100fd44: e13ffd17 ldw r4,-12(fp) + 100fd48: 100edfc0 call 100edfc + 100fd4c: e0bffb05 stb r2,-20(fp) + 100fd50: e0bffa17 ldw r2,-24(fp) + 100fd54: e0bff715 stw r2,-36(fp) + 100fd58: e0bff717 ldw r2,-36(fp) + 100fd5c: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + 100fd60: e0bffe17 ldw r2,-8(fp) + 100fd64: 10000005 stb zero,0(r2) + return (len); + 100fd68: e0bffb03 ldbu r2,-20(fp) + 100fd6c: e0bfff15 stw r2,-4(fp) + 100fd70: e0bfff17 ldw r2,-4(fp) +} + 100fd74: e037883a mov sp,fp + 100fd78: dfc00117 ldw ra,4(sp) + 100fd7c: df000017 ldw fp,0(sp) + 100fd80: dec00204 addi sp,sp,8 + 100fd84: f800283a ret + +0100fd88 : +********************************************************************************************************* +*/ + +#if OS_FLAG_NAME_SIZE > 1 +void OSFlagNameSet (OS_FLAG_GRP *pgrp, INT8U *pname, INT8U *perr) +{ + 100fd88: defff504 addi sp,sp,-44 + 100fd8c: dfc00a15 stw ra,40(sp) + 100fd90: df000915 stw fp,36(sp) + 100fd94: df000904 addi fp,sp,36 + 100fd98: e13ffd15 stw r4,-12(fp) + 100fd9c: e17ffe15 stw r5,-8(fp) + 100fda0: e1bfff15 stw r6,-4(fp) + INT8U len; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 100fda4: e03ffb15 stw zero,-20(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + 100fda8: e0bfff17 ldw r2,-4(fp) + 100fdac: 1005003a cmpeq r2,r2,zero + 100fdb0: 1000451e bne r2,zero,100fec8 + return; + } + if (pgrp == (OS_FLAG_GRP *)0) { /* Is 'pgrp' a NULL pointer? */ + 100fdb4: e0bffd17 ldw r2,-12(fp) + 100fdb8: 1004c03a cmpne r2,r2,zero + 100fdbc: 1000041e bne r2,zero,100fdd0 + *perr = OS_ERR_FLAG_INVALID_PGRP; + 100fdc0: e0ffff17 ldw r3,-4(fp) + 100fdc4: 00801b84 movi r2,110 + 100fdc8: 18800005 stb r2,0(r3) + return; + 100fdcc: 00003e06 br 100fec8 + } + if (pname == (INT8U *)0) { /* Is 'pname' a NULL pointer? */ + 100fdd0: e0bffe17 ldw r2,-8(fp) + 100fdd4: 1004c03a cmpne r2,r2,zero + 100fdd8: 1000041e bne r2,zero,100fdec + *perr = OS_ERR_PNAME_NULL; + 100fddc: e0ffff17 ldw r3,-4(fp) + 100fde0: 00800304 movi r2,12 + 100fde4: 18800005 stb r2,0(r3) + return; + 100fde8: 00003706 br 100fec8 + } +#endif + if (OSIntNesting > 0) { /* See if trying to call from an ISR */ + 100fdec: 008040b4 movhi r2,258 + 100fdf0: 10b31e04 addi r2,r2,-13192 + 100fdf4: 10800003 ldbu r2,0(r2) + 100fdf8: 10803fcc andi r2,r2,255 + 100fdfc: 1005003a cmpeq r2,r2,zero + 100fe00: 1000041e bne r2,zero,100fe14 + *perr = OS_ERR_NAME_SET_ISR; + 100fe04: e0ffff17 ldw r3,-4(fp) + 100fe08: 00800484 movi r2,18 + 100fe0c: 18800005 stb r2,0(r3) + return; + 100fe10: 00002d06 br 100fec8 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 100fe14: 0005303a rdctl r2,status + 100fe18: e0bffa15 stw r2,-24(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 100fe1c: e0fffa17 ldw r3,-24(fp) + 100fe20: 00bfff84 movi r2,-2 + 100fe24: 1884703a and r2,r3,r2 + 100fe28: 1001703a wrctl status,r2 + + return context; + 100fe2c: e0bffa17 ldw r2,-24(fp) + } + OS_ENTER_CRITICAL(); + 100fe30: e0bffb15 stw r2,-20(fp) + if (pgrp->OSFlagType != OS_EVENT_TYPE_FLAG) { + 100fe34: e0bffd17 ldw r2,-12(fp) + 100fe38: 10800003 ldbu r2,0(r2) + 100fe3c: 10803fcc andi r2,r2,255 + 100fe40: 10800160 cmpeqi r2,r2,5 + 100fe44: 1000081e bne r2,zero,100fe68 + 100fe48: e0bffb17 ldw r2,-20(fp) + 100fe4c: e0bff915 stw r2,-28(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 100fe50: e0bff917 ldw r2,-28(fp) + 100fe54: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + *perr = OS_ERR_EVENT_TYPE; + 100fe58: e0ffff17 ldw r3,-4(fp) + 100fe5c: 00800044 movi r2,1 + 100fe60: 18800005 stb r2,0(r3) + return; + 100fe64: 00001806 br 100fec8 + } + len = OS_StrLen(pname); /* Can we fit the string in the storage area? */ + 100fe68: e13ffe17 ldw r4,-8(fp) + 100fe6c: 100ee7c0 call 100ee7c + 100fe70: e0bffc05 stb r2,-16(fp) + if (len > (OS_FLAG_NAME_SIZE - 1)) { /* No */ + 100fe74: e0bffc03 ldbu r2,-16(fp) + 100fe78: 10800830 cmpltui r2,r2,32 + 100fe7c: 1000081e bne r2,zero,100fea0 + 100fe80: e0bffb17 ldw r2,-20(fp) + 100fe84: e0bff815 stw r2,-32(fp) + 100fe88: e0bff817 ldw r2,-32(fp) + 100fe8c: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + *perr = OS_ERR_FLAG_NAME_TOO_LONG; + 100fe90: e0ffff17 ldw r3,-4(fp) + 100fe94: 00801cc4 movi r2,115 + 100fe98: 18800005 stb r2,0(r3) + return; + 100fe9c: 00000a06 br 100fec8 + } + (void)OS_StrCopy(pgrp->OSFlagName, pname); /* Yes, copy name from OS_FLAG_GRP */ + 100fea0: e0bffd17 ldw r2,-12(fp) + 100fea4: 11000284 addi r4,r2,10 + 100fea8: e17ffe17 ldw r5,-8(fp) + 100feac: 100edfc0 call 100edfc + 100feb0: e0bffb17 ldw r2,-20(fp) + 100feb4: e0bff715 stw r2,-36(fp) + 100feb8: e0bff717 ldw r2,-36(fp) + 100febc: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + 100fec0: e0bfff17 ldw r2,-4(fp) + 100fec4: 10000005 stb zero,0(r2) + return; +} + 100fec8: e037883a mov sp,fp + 100fecc: dfc00117 ldw ra,4(sp) + 100fed0: df000017 ldw fp,0(sp) + 100fed4: dec00204 addi sp,sp,8 + 100fed8: f800283a ret + +0100fedc : +* event flags. +********************************************************************************************************* +*/ + +OS_FLAGS OSFlagPend (OS_FLAG_GRP *pgrp, OS_FLAGS flags, INT8U wait_type, INT16U timeout, INT8U *perr) +{ + 100fedc: deffe004 addi sp,sp,-128 + 100fee0: dfc01f15 stw ra,124(sp) + 100fee4: df001e15 stw fp,120(sp) + 100fee8: df001e04 addi fp,sp,120 + 100feec: e13ff915 stw r4,-28(fp) + 100fef0: e17ffa0d sth r5,-24(fp) + 100fef4: e1bffb05 stb r6,-20(fp) + 100fef8: e1fffc0d sth r7,-16(fp) + OS_FLAGS flags_rdy; + INT8U result; + INT8U pend_stat; + BOOLEAN consume; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 100fefc: e03ff115 stw zero,-60(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + 100ff00: e0800217 ldw r2,8(fp) + 100ff04: 1004c03a cmpne r2,r2,zero + 100ff08: 1000021e bne r2,zero,100ff14 + return ((OS_FLAGS)0); + 100ff0c: e03fff15 stw zero,-4(fp) + 100ff10: 00017d06 br 1010508 + } + if (pgrp == (OS_FLAG_GRP *)0) { /* Validate 'pgrp' */ + 100ff14: e0bff917 ldw r2,-28(fp) + 100ff18: 1004c03a cmpne r2,r2,zero + 100ff1c: 1000051e bne r2,zero,100ff34 + *perr = OS_ERR_FLAG_INVALID_PGRP; + 100ff20: e0c00217 ldw r3,8(fp) + 100ff24: 00801b84 movi r2,110 + 100ff28: 18800005 stb r2,0(r3) + return ((OS_FLAGS)0); + 100ff2c: e03fff15 stw zero,-4(fp) + 100ff30: 00017506 br 1010508 + } +#endif + if (OSIntNesting > 0) { /* See if called from ISR ... */ + 100ff34: 008040b4 movhi r2,258 + 100ff38: 10b31e04 addi r2,r2,-13192 + 100ff3c: 10800003 ldbu r2,0(r2) + 100ff40: 10803fcc andi r2,r2,255 + 100ff44: 1005003a cmpeq r2,r2,zero + 100ff48: 1000051e bne r2,zero,100ff60 + *perr = OS_ERR_PEND_ISR; /* ... can't PEND from an ISR */ + 100ff4c: e0c00217 ldw r3,8(fp) + 100ff50: 00800084 movi r2,2 + 100ff54: 18800005 stb r2,0(r3) + return ((OS_FLAGS)0); + 100ff58: e03fff15 stw zero,-4(fp) + 100ff5c: 00016a06 br 1010508 + } + if (OSLockNesting > 0) { /* See if called with scheduler locked ... */ + 100ff60: 008040b4 movhi r2,258 + 100ff64: 10b31004 addi r2,r2,-13248 + 100ff68: 10800003 ldbu r2,0(r2) + 100ff6c: 10803fcc andi r2,r2,255 + 100ff70: 1005003a cmpeq r2,r2,zero + 100ff74: 1000051e bne r2,zero,100ff8c + *perr = OS_ERR_PEND_LOCKED; /* ... can't PEND when locked */ + 100ff78: e0c00217 ldw r3,8(fp) + 100ff7c: 00800344 movi r2,13 + 100ff80: 18800005 stb r2,0(r3) + return ((OS_FLAGS)0); + 100ff84: e03fff15 stw zero,-4(fp) + 100ff88: 00015f06 br 1010508 + } + if (pgrp->OSFlagType != OS_EVENT_TYPE_FLAG) { /* Validate event block type */ + 100ff8c: e0bff917 ldw r2,-28(fp) + 100ff90: 10800003 ldbu r2,0(r2) + 100ff94: 10803fcc andi r2,r2,255 + 100ff98: 10800160 cmpeqi r2,r2,5 + 100ff9c: 1000051e bne r2,zero,100ffb4 + *perr = OS_ERR_EVENT_TYPE; + 100ffa0: e0c00217 ldw r3,8(fp) + 100ffa4: 00800044 movi r2,1 + 100ffa8: 18800005 stb r2,0(r3) + return ((OS_FLAGS)0); + 100ffac: e03fff15 stw zero,-4(fp) + 100ffb0: 00015506 br 1010508 + } + result = (INT8U)(wait_type & OS_FLAG_CONSUME); + 100ffb4: e0fffb03 ldbu r3,-20(fp) + 100ffb8: 00bfe004 movi r2,-128 + 100ffbc: 1884703a and r2,r3,r2 + 100ffc0: e0bff285 stb r2,-54(fp) + if (result != (INT8U)0) { /* See if we need to consume the flags */ + 100ffc4: e0bff283 ldbu r2,-54(fp) + 100ffc8: 1005003a cmpeq r2,r2,zero + 100ffcc: 1000071e bne r2,zero,100ffec + wait_type &= ~(INT8U)OS_FLAG_CONSUME; + 100ffd0: 00c01fc4 movi r3,127 + 100ffd4: e0bffb03 ldbu r2,-20(fp) + 100ffd8: 10c4703a and r2,r2,r3 + 100ffdc: e0bffb05 stb r2,-20(fp) + consume = OS_TRUE; + 100ffe0: 00800044 movi r2,1 + 100ffe4: e0bff205 stb r2,-56(fp) + 100ffe8: 00000106 br 100fff0 + } else { + consume = OS_FALSE; + 100ffec: e03ff205 stb zero,-56(fp) +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 100fff0: 0005303a rdctl r2,status + 100fff4: e0bff015 stw r2,-64(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 100fff8: e0fff017 ldw r3,-64(fp) + 100fffc: 00bfff84 movi r2,-2 + 1010000: 1884703a and r2,r3,r2 + 1010004: 1001703a wrctl status,r2 + + return context; + 1010008: e0bff017 ldw r2,-64(fp) + } +/*$PAGE*/ + OS_ENTER_CRITICAL(); + 101000c: e0bff115 stw r2,-60(fp) + switch (wait_type) { + 1010010: e0bffb03 ldbu r2,-20(fp) + 1010014: e0bffe15 stw r2,-8(fp) + 1010018: e0fffe17 ldw r3,-8(fp) + 101001c: 18800060 cmpeqi r2,r3,1 + 1010020: 1000981e bne r2,zero,1010284 + 1010024: e0fffe17 ldw r3,-8(fp) + 1010028: 18800088 cmpgei r2,r3,2 + 101002c: 1000041e bne r2,zero,1010040 + 1010030: e0fffe17 ldw r3,-8(fp) + 1010034: 1805003a cmpeq r2,r3,zero + 1010038: 1000641e bne r2,zero,10101cc + 101003c: 0000bf06 br 101033c + 1010040: e0fffe17 ldw r3,-8(fp) + 1010044: 188000a0 cmpeqi r2,r3,2 + 1010048: 1000041e bne r2,zero,101005c + 101004c: e0fffe17 ldw r3,-8(fp) + 1010050: 188000e0 cmpeqi r2,r3,3 + 1010054: 10002f1e bne r2,zero,1010114 + 1010058: 0000b806 br 101033c + case OS_FLAG_WAIT_SET_ALL: /* See if all required flags are set */ + flags_rdy = (OS_FLAGS)(pgrp->OSFlagFlags & flags); /* Extract only the bits we want */ + 101005c: e0bff917 ldw r2,-28(fp) + 1010060: 10c0020b ldhu r3,8(r2) + 1010064: e0bffa0b ldhu r2,-24(fp) + 1010068: 1884703a and r2,r3,r2 + 101006c: e0bff30d sth r2,-52(fp) + if (flags_rdy == flags) { /* Must match ALL the bits that we want */ + 1010070: e0fff30b ldhu r3,-52(fp) + 1010074: e0bffa0b ldhu r2,-24(fp) + 1010078: 18801a1e bne r3,r2,10100e4 + if (consume == OS_TRUE) { /* See if we need to consume the flags */ + 101007c: e0bff203 ldbu r2,-56(fp) + 1010080: 10800058 cmpnei r2,r2,1 + 1010084: 1000091e bne r2,zero,10100ac + pgrp->OSFlagFlags &= ~flags_rdy; /* Clear ONLY the flags that we wanted */ + 1010088: e0bff917 ldw r2,-28(fp) + 101008c: 1080020b ldhu r2,8(r2) + 1010090: 1007883a mov r3,r2 + 1010094: e0bff30b ldhu r2,-52(fp) + 1010098: 0084303a nor r2,zero,r2 + 101009c: 1884703a and r2,r3,r2 + 10100a0: 1007883a mov r3,r2 + 10100a4: e0bff917 ldw r2,-28(fp) + 10100a8: 10c0020d sth r3,8(r2) + } + OSTCBCur->OSTCBFlagsRdy = flags_rdy; /* Save flags that were ready */ + 10100ac: 008040b4 movhi r2,258 + 10100b0: 10b31f04 addi r2,r2,-13188 + 10100b4: 10c00017 ldw r3,0(r2) + 10100b8: e0bff30b ldhu r2,-52(fp) + 10100bc: 18800b0d sth r2,44(r3) + 10100c0: e0bff117 ldw r2,-60(fp) + 10100c4: e0bfef15 stw r2,-68(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 10100c8: e0bfef17 ldw r2,-68(fp) + 10100cc: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); /* Yes, condition met, return to caller */ + *perr = OS_ERR_NONE; + 10100d0: e0800217 ldw r2,8(fp) + 10100d4: 10000005 stb zero,0(r2) + return (flags_rdy); + 10100d8: e0bff30b ldhu r2,-52(fp) + 10100dc: e0bfff15 stw r2,-4(fp) + 10100e0: 00010906 br 1010508 + } else { /* Block task until events occur or timeout */ + OS_FlagBlock(pgrp, &node, flags, wait_type, timeout); + 10100e4: e1bffa0b ldhu r6,-24(fp) + 10100e8: e1fffb03 ldbu r7,-20(fp) + 10100ec: e0bffc0b ldhu r2,-16(fp) + 10100f0: e17ff404 addi r5,fp,-48 + 10100f4: d8800015 stw r2,0(sp) + 10100f8: e13ff917 ldw r4,-28(fp) + 10100fc: 1010a040 call 1010a04 + 1010100: e0bff117 ldw r2,-60(fp) + 1010104: e0bfee15 stw r2,-72(fp) + 1010108: e0bfee17 ldw r2,-72(fp) + 101010c: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + } + break; + 1010110: 00009506 br 1010368 + + case OS_FLAG_WAIT_SET_ANY: + flags_rdy = (OS_FLAGS)(pgrp->OSFlagFlags & flags); /* Extract only the bits we want */ + 1010114: e0bff917 ldw r2,-28(fp) + 1010118: 10c0020b ldhu r3,8(r2) + 101011c: e0bffa0b ldhu r2,-24(fp) + 1010120: 1884703a and r2,r3,r2 + 1010124: e0bff30d sth r2,-52(fp) + if (flags_rdy != (OS_FLAGS)0) { /* See if any flag set */ + 1010128: e0bff30b ldhu r2,-52(fp) + 101012c: 1005003a cmpeq r2,r2,zero + 1010130: 10001a1e bne r2,zero,101019c + if (consume == OS_TRUE) { /* See if we need to consume the flags */ + 1010134: e0bff203 ldbu r2,-56(fp) + 1010138: 10800058 cmpnei r2,r2,1 + 101013c: 1000091e bne r2,zero,1010164 + pgrp->OSFlagFlags &= ~flags_rdy; /* Clear ONLY the flags that we got */ + 1010140: e0bff917 ldw r2,-28(fp) + 1010144: 1080020b ldhu r2,8(r2) + 1010148: 1007883a mov r3,r2 + 101014c: e0bff30b ldhu r2,-52(fp) + 1010150: 0084303a nor r2,zero,r2 + 1010154: 1884703a and r2,r3,r2 + 1010158: 1007883a mov r3,r2 + 101015c: e0bff917 ldw r2,-28(fp) + 1010160: 10c0020d sth r3,8(r2) + } + OSTCBCur->OSTCBFlagsRdy = flags_rdy; /* Save flags that were ready */ + 1010164: 008040b4 movhi r2,258 + 1010168: 10b31f04 addi r2,r2,-13188 + 101016c: 10c00017 ldw r3,0(r2) + 1010170: e0bff30b ldhu r2,-52(fp) + 1010174: 18800b0d sth r2,44(r3) + 1010178: e0bff117 ldw r2,-60(fp) + 101017c: e0bfed15 stw r2,-76(fp) + 1010180: e0bfed17 ldw r2,-76(fp) + 1010184: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); /* Yes, condition met, return to caller */ + *perr = OS_ERR_NONE; + 1010188: e0800217 ldw r2,8(fp) + 101018c: 10000005 stb zero,0(r2) + return (flags_rdy); + 1010190: e0fff30b ldhu r3,-52(fp) + 1010194: e0ffff15 stw r3,-4(fp) + 1010198: 0000db06 br 1010508 + } else { /* Block task until events occur or timeout */ + OS_FlagBlock(pgrp, &node, flags, wait_type, timeout); + 101019c: e1bffa0b ldhu r6,-24(fp) + 10101a0: e1fffb03 ldbu r7,-20(fp) + 10101a4: e0bffc0b ldhu r2,-16(fp) + 10101a8: e17ff404 addi r5,fp,-48 + 10101ac: d8800015 stw r2,0(sp) + 10101b0: e13ff917 ldw r4,-28(fp) + 10101b4: 1010a040 call 1010a04 + 10101b8: e0bff117 ldw r2,-60(fp) + 10101bc: e0bfec15 stw r2,-80(fp) + 10101c0: e0bfec17 ldw r2,-80(fp) + 10101c4: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + } + break; + 10101c8: 00006706 br 1010368 + +#if OS_FLAG_WAIT_CLR_EN > 0 + case OS_FLAG_WAIT_CLR_ALL: /* See if all required flags are cleared */ + flags_rdy = (OS_FLAGS)(~pgrp->OSFlagFlags & flags); /* Extract only the bits we want */ + 10101cc: e0bff917 ldw r2,-28(fp) + 10101d0: 1080020b ldhu r2,8(r2) + 10101d4: 0084303a nor r2,zero,r2 + 10101d8: 1007883a mov r3,r2 + 10101dc: e0bffa0b ldhu r2,-24(fp) + 10101e0: 1884703a and r2,r3,r2 + 10101e4: e0bff30d sth r2,-52(fp) + if (flags_rdy == flags) { /* Must match ALL the bits that we want */ + 10101e8: e0fff30b ldhu r3,-52(fp) + 10101ec: e0bffa0b ldhu r2,-24(fp) + 10101f0: 1880181e bne r3,r2,1010254 + if (consume == OS_TRUE) { /* See if we need to consume the flags */ + 10101f4: e0bff203 ldbu r2,-56(fp) + 10101f8: 10800058 cmpnei r2,r2,1 + 10101fc: 1000071e bne r2,zero,101021c + pgrp->OSFlagFlags |= flags_rdy; /* Set ONLY the flags that we wanted */ + 1010200: e0bff917 ldw r2,-28(fp) + 1010204: 10c0020b ldhu r3,8(r2) + 1010208: e0bff30b ldhu r2,-52(fp) + 101020c: 1884b03a or r2,r3,r2 + 1010210: 1007883a mov r3,r2 + 1010214: e0bff917 ldw r2,-28(fp) + 1010218: 10c0020d sth r3,8(r2) + } + OSTCBCur->OSTCBFlagsRdy = flags_rdy; /* Save flags that were ready */ + 101021c: 008040b4 movhi r2,258 + 1010220: 10b31f04 addi r2,r2,-13188 + 1010224: 10c00017 ldw r3,0(r2) + 1010228: e0bff30b ldhu r2,-52(fp) + 101022c: 18800b0d sth r2,44(r3) + 1010230: e0bff117 ldw r2,-60(fp) + 1010234: e0bfeb15 stw r2,-84(fp) + 1010238: e0bfeb17 ldw r2,-84(fp) + 101023c: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); /* Yes, condition met, return to caller */ + *perr = OS_ERR_NONE; + 1010240: e0800217 ldw r2,8(fp) + 1010244: 10000005 stb zero,0(r2) + return (flags_rdy); + 1010248: e0bff30b ldhu r2,-52(fp) + 101024c: e0bfff15 stw r2,-4(fp) + 1010250: 0000ad06 br 1010508 + } else { /* Block task until events occur or timeout */ + OS_FlagBlock(pgrp, &node, flags, wait_type, timeout); + 1010254: e1bffa0b ldhu r6,-24(fp) + 1010258: e1fffb03 ldbu r7,-20(fp) + 101025c: e0bffc0b ldhu r2,-16(fp) + 1010260: e17ff404 addi r5,fp,-48 + 1010264: d8800015 stw r2,0(sp) + 1010268: e13ff917 ldw r4,-28(fp) + 101026c: 1010a040 call 1010a04 + 1010270: e0bff117 ldw r2,-60(fp) + 1010274: e0bfea15 stw r2,-88(fp) + 1010278: e0bfea17 ldw r2,-88(fp) + 101027c: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + } + break; + 1010280: 00003906 br 1010368 + + case OS_FLAG_WAIT_CLR_ANY: + flags_rdy = (OS_FLAGS)(~pgrp->OSFlagFlags & flags); /* Extract only the bits we want */ + 1010284: e0bff917 ldw r2,-28(fp) + 1010288: 1080020b ldhu r2,8(r2) + 101028c: 0084303a nor r2,zero,r2 + 1010290: 1007883a mov r3,r2 + 1010294: e0bffa0b ldhu r2,-24(fp) + 1010298: 1884703a and r2,r3,r2 + 101029c: e0bff30d sth r2,-52(fp) + if (flags_rdy != (OS_FLAGS)0) { /* See if any flag cleared */ + 10102a0: e0bff30b ldhu r2,-52(fp) + 10102a4: 1005003a cmpeq r2,r2,zero + 10102a8: 1000181e bne r2,zero,101030c + if (consume == OS_TRUE) { /* See if we need to consume the flags */ + 10102ac: e0bff203 ldbu r2,-56(fp) + 10102b0: 10800058 cmpnei r2,r2,1 + 10102b4: 1000071e bne r2,zero,10102d4 + pgrp->OSFlagFlags |= flags_rdy; /* Set ONLY the flags that we got */ + 10102b8: e0bff917 ldw r2,-28(fp) + 10102bc: 10c0020b ldhu r3,8(r2) + 10102c0: e0bff30b ldhu r2,-52(fp) + 10102c4: 1884b03a or r2,r3,r2 + 10102c8: 1007883a mov r3,r2 + 10102cc: e0bff917 ldw r2,-28(fp) + 10102d0: 10c0020d sth r3,8(r2) + } + OSTCBCur->OSTCBFlagsRdy = flags_rdy; /* Save flags that were ready */ + 10102d4: 008040b4 movhi r2,258 + 10102d8: 10b31f04 addi r2,r2,-13188 + 10102dc: 10c00017 ldw r3,0(r2) + 10102e0: e0bff30b ldhu r2,-52(fp) + 10102e4: 18800b0d sth r2,44(r3) + 10102e8: e0bff117 ldw r2,-60(fp) + 10102ec: e0bfe915 stw r2,-92(fp) + 10102f0: e0bfe917 ldw r2,-92(fp) + 10102f4: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); /* Yes, condition met, return to caller */ + *perr = OS_ERR_NONE; + 10102f8: e0800217 ldw r2,8(fp) + 10102fc: 10000005 stb zero,0(r2) + return (flags_rdy); + 1010300: e0fff30b ldhu r3,-52(fp) + 1010304: e0ffff15 stw r3,-4(fp) + 1010308: 00007f06 br 1010508 + } else { /* Block task until events occur or timeout */ + OS_FlagBlock(pgrp, &node, flags, wait_type, timeout); + 101030c: e1bffa0b ldhu r6,-24(fp) + 1010310: e1fffb03 ldbu r7,-20(fp) + 1010314: e0bffc0b ldhu r2,-16(fp) + 1010318: e17ff404 addi r5,fp,-48 + 101031c: d8800015 stw r2,0(sp) + 1010320: e13ff917 ldw r4,-28(fp) + 1010324: 1010a040 call 1010a04 + 1010328: e0bff117 ldw r2,-60(fp) + 101032c: e0bfe815 stw r2,-96(fp) + 1010330: e0bfe817 ldw r2,-96(fp) + 1010334: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + } + break; + 1010338: 00000b06 br 1010368 + 101033c: e0bff117 ldw r2,-60(fp) + 1010340: e0bfe715 stw r2,-100(fp) + 1010344: e0bfe717 ldw r2,-100(fp) + 1010348: 1001703a wrctl status,r2 +#endif + + default: + OS_EXIT_CRITICAL(); + flags_rdy = (OS_FLAGS)0; + 101034c: e03ff30d sth zero,-52(fp) + *perr = OS_ERR_FLAG_WAIT_TYPE; + 1010350: e0c00217 ldw r3,8(fp) + 1010354: 00801bc4 movi r2,111 + 1010358: 18800005 stb r2,0(r3) + return (flags_rdy); + 101035c: e0bff30b ldhu r2,-52(fp) + 1010360: e0bfff15 stw r2,-4(fp) + 1010364: 00006806 br 1010508 + } +/*$PAGE*/ + OS_Sched(); /* Find next HPT ready to run */ + 1010368: 100ecb80 call 100ecb8 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 101036c: 0005303a rdctl r2,status + 1010370: e0bfe615 stw r2,-104(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1010374: e0ffe617 ldw r3,-104(fp) + 1010378: 00bfff84 movi r2,-2 + 101037c: 1884703a and r2,r3,r2 + 1010380: 1001703a wrctl status,r2 + + return context; + 1010384: e0bfe617 ldw r2,-104(fp) + OS_ENTER_CRITICAL(); + 1010388: e0bff115 stw r2,-60(fp) + if (OSTCBCur->OSTCBStatPend != OS_STAT_PEND_OK) { /* Have we timed-out or aborted? */ + 101038c: 008040b4 movhi r2,258 + 1010390: 10b31f04 addi r2,r2,-13188 + 1010394: 10800017 ldw r2,0(r2) + 1010398: 10800c43 ldbu r2,49(r2) + 101039c: 10803fcc andi r2,r2,255 + 10103a0: 1005003a cmpeq r2,r2,zero + 10103a4: 1000221e bne r2,zero,1010430 + pend_stat = OSTCBCur->OSTCBStatPend; + 10103a8: 008040b4 movhi r2,258 + 10103ac: 10b31f04 addi r2,r2,-13188 + 10103b0: 10800017 ldw r2,0(r2) + 10103b4: 10800c43 ldbu r2,49(r2) + 10103b8: e0bff245 stb r2,-55(fp) + OSTCBCur->OSTCBStatPend = OS_STAT_PEND_OK; + 10103bc: 008040b4 movhi r2,258 + 10103c0: 10b31f04 addi r2,r2,-13188 + 10103c4: 10800017 ldw r2,0(r2) + 10103c8: 10000c45 stb zero,49(r2) + OS_FlagUnlink(&node); + 10103cc: e13ff404 addi r4,fp,-48 + 10103d0: 1010dbc0 call 1010dbc + OSTCBCur->OSTCBStat = OS_STAT_RDY; /* Yes, make task ready-to-run */ + 10103d4: 008040b4 movhi r2,258 + 10103d8: 10b31f04 addi r2,r2,-13188 + 10103dc: 10800017 ldw r2,0(r2) + 10103e0: 10000c05 stb zero,48(r2) + 10103e4: e0bff117 ldw r2,-60(fp) + 10103e8: e0bfe515 stw r2,-108(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 10103ec: e0bfe517 ldw r2,-108(fp) + 10103f0: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + flags_rdy = (OS_FLAGS)0; + 10103f4: e03ff30d sth zero,-52(fp) + switch (pend_stat) { + 10103f8: e0bff243 ldbu r2,-55(fp) + 10103fc: 108000a0 cmpeqi r2,r2,2 + 1010400: 1000011e bne r2,zero,1010408 + 1010404: 00000406 br 1010418 + case OS_STAT_PEND_ABORT: + *perr = OS_ERR_PEND_ABORT; /* Indicate that we aborted waiting */ + 1010408: e0c00217 ldw r3,8(fp) + 101040c: 00800384 movi r2,14 + 1010410: 18800005 stb r2,0(r3) + break; + 1010414: 00000306 br 1010424 + + case OS_STAT_PEND_TO: + default: + *perr = OS_ERR_TIMEOUT; /* Indicate that we timed-out waiting */ + 1010418: e0c00217 ldw r3,8(fp) + 101041c: 00800284 movi r2,10 + 1010420: 18800005 stb r2,0(r3) + break; + } + return (flags_rdy); + 1010424: e0fff30b ldhu r3,-52(fp) + 1010428: e0ffff15 stw r3,-4(fp) + 101042c: 00003606 br 1010508 + } + flags_rdy = OSTCBCur->OSTCBFlagsRdy; + 1010430: 008040b4 movhi r2,258 + 1010434: 10b31f04 addi r2,r2,-13188 + 1010438: 10800017 ldw r2,0(r2) + 101043c: 10800b0b ldhu r2,44(r2) + 1010440: e0bff30d sth r2,-52(fp) + if (consume == OS_TRUE) { /* See if we need to consume the flags */ + 1010444: e0bff203 ldbu r2,-56(fp) + 1010448: 10800058 cmpnei r2,r2,1 + 101044c: 1000261e bne r2,zero,10104e8 + switch (wait_type) { + 1010450: e0bffb03 ldbu r2,-20(fp) + 1010454: e0bffd15 stw r2,-12(fp) + 1010458: e0fffd17 ldw r3,-12(fp) + 101045c: 1804803a cmplt r2,r3,zero + 1010460: 1000181e bne r2,zero,10104c4 + 1010464: e0fffd17 ldw r3,-12(fp) + 1010468: 18800090 cmplti r2,r3,2 + 101046c: 10000d1e bne r2,zero,10104a4 + 1010470: e0fffd17 ldw r3,-12(fp) + 1010474: 18800108 cmpgei r2,r3,4 + 1010478: 1000121e bne r2,zero,10104c4 + case OS_FLAG_WAIT_SET_ALL: + case OS_FLAG_WAIT_SET_ANY: /* Clear ONLY the flags we got */ + pgrp->OSFlagFlags &= ~flags_rdy; + 101047c: e0bff917 ldw r2,-28(fp) + 1010480: 1080020b ldhu r2,8(r2) + 1010484: 1007883a mov r3,r2 + 1010488: e0bff30b ldhu r2,-52(fp) + 101048c: 0084303a nor r2,zero,r2 + 1010490: 1884703a and r2,r3,r2 + 1010494: 1007883a mov r3,r2 + 1010498: e0bff917 ldw r2,-28(fp) + 101049c: 10c0020d sth r3,8(r2) + break; + 10104a0: 00001106 br 10104e8 + +#if OS_FLAG_WAIT_CLR_EN > 0 + case OS_FLAG_WAIT_CLR_ALL: + case OS_FLAG_WAIT_CLR_ANY: /* Set ONLY the flags we got */ + pgrp->OSFlagFlags |= flags_rdy; + 10104a4: e0bff917 ldw r2,-28(fp) + 10104a8: 10c0020b ldhu r3,8(r2) + 10104ac: e0bff30b ldhu r2,-52(fp) + 10104b0: 1884b03a or r2,r3,r2 + 10104b4: 1007883a mov r3,r2 + 10104b8: e0bff917 ldw r2,-28(fp) + 10104bc: 10c0020d sth r3,8(r2) + break; + 10104c0: 00000906 br 10104e8 + 10104c4: e0bff117 ldw r2,-60(fp) + 10104c8: e0bfe415 stw r2,-112(fp) + 10104cc: e0bfe417 ldw r2,-112(fp) + 10104d0: 1001703a wrctl status,r2 +#endif + default: + OS_EXIT_CRITICAL(); + *perr = OS_ERR_FLAG_WAIT_TYPE; + 10104d4: e0c00217 ldw r3,8(fp) + 10104d8: 00801bc4 movi r2,111 + 10104dc: 18800005 stb r2,0(r3) + return ((OS_FLAGS)0); + 10104e0: e03fff15 stw zero,-4(fp) + 10104e4: 00000806 br 1010508 + 10104e8: e0bff117 ldw r2,-60(fp) + 10104ec: e0bfe315 stw r2,-116(fp) + 10104f0: e0bfe317 ldw r2,-116(fp) + 10104f4: 1001703a wrctl status,r2 + } + } + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; /* Event(s) must have occurred */ + 10104f8: e0800217 ldw r2,8(fp) + 10104fc: 10000005 stb zero,0(r2) + return (flags_rdy); + 1010500: e0bff30b ldhu r2,-52(fp) + 1010504: e0bfff15 stw r2,-4(fp) + 1010508: e0bfff17 ldw r2,-4(fp) +} + 101050c: e037883a mov sp,fp + 1010510: dfc00117 ldw ra,4(sp) + 1010514: df000017 ldw fp,0(sp) + 1010518: dec00204 addi sp,sp,8 + 101051c: f800283a ret + +01010520 : +* Called from: Task ONLY +********************************************************************************************************* +*/ + +OS_FLAGS OSFlagPendGetFlagsRdy (void) +{ + 1010520: defffb04 addi sp,sp,-20 + 1010524: df000415 stw fp,16(sp) + 1010528: df000404 addi fp,sp,16 + OS_FLAGS flags; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 101052c: e03ffe15 stw zero,-8(fp) +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1010530: 0005303a rdctl r2,status + 1010534: e0bffd15 stw r2,-12(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1010538: e0fffd17 ldw r3,-12(fp) + 101053c: 00bfff84 movi r2,-2 + 1010540: 1884703a and r2,r3,r2 + 1010544: 1001703a wrctl status,r2 + + return context; + 1010548: e0bffd17 ldw r2,-12(fp) +#endif + + + + OS_ENTER_CRITICAL(); + 101054c: e0bffe15 stw r2,-8(fp) + flags = OSTCBCur->OSTCBFlagsRdy; + 1010550: 008040b4 movhi r2,258 + 1010554: 10b31f04 addi r2,r2,-13188 + 1010558: 10800017 ldw r2,0(r2) + 101055c: 10800b0b ldhu r2,44(r2) + 1010560: e0bfff0d sth r2,-4(fp) + 1010564: e0bffe17 ldw r2,-8(fp) + 1010568: e0bffc15 stw r2,-16(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 101056c: e0bffc17 ldw r2,-16(fp) + 1010570: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (flags); + 1010574: e0bfff0b ldhu r2,-4(fp) +} + 1010578: e037883a mov sp,fp + 101057c: df000017 ldw fp,0(sp) + 1010580: dec00104 addi sp,sp,4 + 1010584: f800283a ret + +01010588 : +* 2) The amount of time interrupts are DISABLED depends on the number of tasks waiting on +* the event flag group. +********************************************************************************************************* +*/ +OS_FLAGS OSFlagPost (OS_FLAG_GRP *pgrp, OS_FLAGS flags, INT8U opt, INT8U *perr) +{ + 1010588: deffed04 addi sp,sp,-76 + 101058c: dfc01215 stw ra,72(sp) + 1010590: df001115 stw fp,68(sp) + 1010594: df001104 addi fp,sp,68 + 1010598: e13ff915 stw r4,-28(fp) + 101059c: e1fffc15 stw r7,-16(fp) + 10105a0: e17ffa0d sth r5,-24(fp) + 10105a4: e1bffb05 stb r6,-20(fp) + BOOLEAN sched; + OS_FLAGS flags_cur; + OS_FLAGS flags_rdy; + BOOLEAN rdy; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 10105a8: e03ff515 stw zero,-44(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + 10105ac: e0bffc17 ldw r2,-16(fp) + 10105b0: 1004c03a cmpne r2,r2,zero + 10105b4: 1000021e bne r2,zero,10105c0 + return ((OS_FLAGS)0); + 10105b8: e03fff15 stw zero,-4(fp) + 10105bc: 0000d606 br 1010918 + } + if (pgrp == (OS_FLAG_GRP *)0) { /* Validate 'pgrp' */ + 10105c0: e0bff917 ldw r2,-28(fp) + 10105c4: 1004c03a cmpne r2,r2,zero + 10105c8: 1000051e bne r2,zero,10105e0 + *perr = OS_ERR_FLAG_INVALID_PGRP; + 10105cc: e0fffc17 ldw r3,-16(fp) + 10105d0: 00801b84 movi r2,110 + 10105d4: 18800005 stb r2,0(r3) + return ((OS_FLAGS)0); + 10105d8: e03fff15 stw zero,-4(fp) + 10105dc: 0000ce06 br 1010918 + } +#endif + if (pgrp->OSFlagType != OS_EVENT_TYPE_FLAG) { /* Make sure we are pointing to an event flag grp */ + 10105e0: e0bff917 ldw r2,-28(fp) + 10105e4: 10800003 ldbu r2,0(r2) + 10105e8: 10803fcc andi r2,r2,255 + 10105ec: 10800160 cmpeqi r2,r2,5 + 10105f0: 1000051e bne r2,zero,1010608 + *perr = OS_ERR_EVENT_TYPE; + 10105f4: e0fffc17 ldw r3,-16(fp) + 10105f8: 00800044 movi r2,1 + 10105fc: 18800005 stb r2,0(r3) + return ((OS_FLAGS)0); + 1010600: e03fff15 stw zero,-4(fp) + 1010604: 0000c406 br 1010918 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1010608: 0005303a rdctl r2,status + 101060c: e0bff415 stw r2,-48(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1010610: e0fff417 ldw r3,-48(fp) + 1010614: 00bfff84 movi r2,-2 + 1010618: 1884703a and r2,r3,r2 + 101061c: 1001703a wrctl status,r2 + + return context; + 1010620: e0bff417 ldw r2,-48(fp) + } +/*$PAGE*/ + OS_ENTER_CRITICAL(); + 1010624: e0bff515 stw r2,-44(fp) + switch (opt) { + 1010628: e0bffb03 ldbu r2,-20(fp) + 101062c: e0bffe15 stw r2,-8(fp) + 1010630: e0fffe17 ldw r3,-8(fp) + 1010634: 1805003a cmpeq r2,r3,zero + 1010638: 1000041e bne r2,zero,101064c + 101063c: e0fffe17 ldw r3,-8(fp) + 1010640: 18800060 cmpeqi r2,r3,1 + 1010644: 10000b1e bne r2,zero,1010674 + 1010648: 00001206 br 1010694 + case OS_FLAG_CLR: + pgrp->OSFlagFlags &= ~flags; /* Clear the flags specified in the group */ + 101064c: e0bff917 ldw r2,-28(fp) + 1010650: 1080020b ldhu r2,8(r2) + 1010654: 1007883a mov r3,r2 + 1010658: e0bffa0b ldhu r2,-24(fp) + 101065c: 0084303a nor r2,zero,r2 + 1010660: 1884703a and r2,r3,r2 + 1010664: 1007883a mov r3,r2 + 1010668: e0bff917 ldw r2,-28(fp) + 101066c: 10c0020d sth r3,8(r2) + break; + 1010670: 00001106 br 10106b8 + + case OS_FLAG_SET: + pgrp->OSFlagFlags |= flags; /* Set the flags specified in the group */ + 1010674: e0bff917 ldw r2,-28(fp) + 1010678: 10c0020b ldhu r3,8(r2) + 101067c: e0bffa0b ldhu r2,-24(fp) + 1010680: 1884b03a or r2,r3,r2 + 1010684: 1007883a mov r3,r2 + 1010688: e0bff917 ldw r2,-28(fp) + 101068c: 10c0020d sth r3,8(r2) + break; + 1010690: 00000906 br 10106b8 + 1010694: e0bff517 ldw r2,-44(fp) + 1010698: e0bff315 stw r2,-52(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 101069c: e0bff317 ldw r2,-52(fp) + 10106a0: 1001703a wrctl status,r2 + + default: + OS_EXIT_CRITICAL(); /* INVALID option */ + *perr = OS_ERR_FLAG_INVALID_OPT; + 10106a4: e0fffc17 ldw r3,-16(fp) + 10106a8: 00801c44 movi r2,113 + 10106ac: 18800005 stb r2,0(r3) + return ((OS_FLAGS)0); + 10106b0: e03fff15 stw zero,-4(fp) + 10106b4: 00009806 br 1010918 + } + sched = OS_FALSE; /* Indicate that we don't need rescheduling */ + 10106b8: e03ff785 stb zero,-34(fp) + pnode = (OS_FLAG_NODE *)pgrp->OSFlagWaitList; + 10106bc: e0bff917 ldw r2,-28(fp) + 10106c0: 10800117 ldw r2,4(r2) + 10106c4: e0bff815 stw r2,-32(fp) + while (pnode != (OS_FLAG_NODE *)0) { /* Go through all tasks waiting on event flag(s) */ + 10106c8: 00007506 br 10108a0 + switch (pnode->OSFlagNodeWaitType) { + 10106cc: e0bff817 ldw r2,-32(fp) + 10106d0: 10800483 ldbu r2,18(r2) + 10106d4: 10803fcc andi r2,r2,255 + 10106d8: e0bffd15 stw r2,-12(fp) + 10106dc: e0fffd17 ldw r3,-12(fp) + 10106e0: 18800060 cmpeqi r2,r3,1 + 10106e4: 10004d1e bne r2,zero,101081c + 10106e8: e0fffd17 ldw r3,-12(fp) + 10106ec: 18800088 cmpgei r2,r3,2 + 10106f0: 1000041e bne r2,zero,1010704 + 10106f4: e0fffd17 ldw r3,-12(fp) + 10106f8: 1805003a cmpeq r2,r3,zero + 10106fc: 1000301e bne r2,zero,10107c0 + 1010700: 00005b06 br 1010870 + 1010704: e0fffd17 ldw r3,-12(fp) + 1010708: 188000a0 cmpeqi r2,r3,2 + 101070c: 1000041e bne r2,zero,1010720 + 1010710: e0fffd17 ldw r3,-12(fp) + 1010714: 188000e0 cmpeqi r2,r3,3 + 1010718: 1000161e bne r2,zero,1010774 + 101071c: 00005406 br 1010870 + case OS_FLAG_WAIT_SET_ALL: /* See if all req. flags are set for current node */ + flags_rdy = (OS_FLAGS)(pgrp->OSFlagFlags & pnode->OSFlagNodeFlags); + 1010720: e0bff917 ldw r2,-28(fp) + 1010724: 10c0020b ldhu r3,8(r2) + 1010728: e0bff817 ldw r2,-32(fp) + 101072c: 1080040b ldhu r2,16(r2) + 1010730: 1884703a and r2,r3,r2 + 1010734: e0bff68d sth r2,-38(fp) + if (flags_rdy == pnode->OSFlagNodeFlags) { + 1010738: e0bff817 ldw r2,-32(fp) + 101073c: 1080040b ldhu r2,16(r2) + 1010740: 10ffffcc andi r3,r2,65535 + 1010744: e0bff68b ldhu r2,-38(fp) + 1010748: 1880521e bne r3,r2,1010894 + rdy = OS_FlagTaskRdy(pnode, flags_rdy); /* Make task RTR, event(s) Rx'd */ + 101074c: e17ff68b ldhu r5,-38(fp) + 1010750: e13ff817 ldw r4,-32(fp) + 1010754: 1010cac0 call 1010cac + 1010758: e0bff605 stb r2,-40(fp) + if (rdy == OS_TRUE) { + 101075c: e0bff603 ldbu r2,-40(fp) + 1010760: 10800058 cmpnei r2,r2,1 + 1010764: 10004b1e bne r2,zero,1010894 + sched = OS_TRUE; /* When done we will reschedule */ + 1010768: 00800044 movi r2,1 + 101076c: e0bff785 stb r2,-34(fp) + } + } + break; + 1010770: 00004806 br 1010894 + + case OS_FLAG_WAIT_SET_ANY: /* See if any flag set */ + flags_rdy = (OS_FLAGS)(pgrp->OSFlagFlags & pnode->OSFlagNodeFlags); + 1010774: e0bff917 ldw r2,-28(fp) + 1010778: 10c0020b ldhu r3,8(r2) + 101077c: e0bff817 ldw r2,-32(fp) + 1010780: 1080040b ldhu r2,16(r2) + 1010784: 1884703a and r2,r3,r2 + 1010788: e0bff68d sth r2,-38(fp) + if (flags_rdy != (OS_FLAGS)0) { + 101078c: e0bff68b ldhu r2,-38(fp) + 1010790: 1005003a cmpeq r2,r2,zero + 1010794: 10003f1e bne r2,zero,1010894 + rdy = OS_FlagTaskRdy(pnode, flags_rdy); /* Make task RTR, event(s) Rx'd */ + 1010798: e17ff68b ldhu r5,-38(fp) + 101079c: e13ff817 ldw r4,-32(fp) + 10107a0: 1010cac0 call 1010cac + 10107a4: e0bff605 stb r2,-40(fp) + if (rdy == OS_TRUE) { + 10107a8: e0bff603 ldbu r2,-40(fp) + 10107ac: 10800058 cmpnei r2,r2,1 + 10107b0: 1000381e bne r2,zero,1010894 + sched = OS_TRUE; /* When done we will reschedule */ + 10107b4: 00800044 movi r2,1 + 10107b8: e0bff785 stb r2,-34(fp) + } + } + break; + 10107bc: 00003506 br 1010894 + +#if OS_FLAG_WAIT_CLR_EN > 0 + case OS_FLAG_WAIT_CLR_ALL: /* See if all req. flags are set for current node */ + flags_rdy = (OS_FLAGS)(~pgrp->OSFlagFlags & pnode->OSFlagNodeFlags); + 10107c0: e0bff917 ldw r2,-28(fp) + 10107c4: 1080020b ldhu r2,8(r2) + 10107c8: 0084303a nor r2,zero,r2 + 10107cc: 1007883a mov r3,r2 + 10107d0: e0bff817 ldw r2,-32(fp) + 10107d4: 1080040b ldhu r2,16(r2) + 10107d8: 1884703a and r2,r3,r2 + 10107dc: e0bff68d sth r2,-38(fp) + if (flags_rdy == pnode->OSFlagNodeFlags) { + 10107e0: e0bff817 ldw r2,-32(fp) + 10107e4: 1080040b ldhu r2,16(r2) + 10107e8: 10ffffcc andi r3,r2,65535 + 10107ec: e0bff68b ldhu r2,-38(fp) + 10107f0: 1880281e bne r3,r2,1010894 + rdy = OS_FlagTaskRdy(pnode, flags_rdy); /* Make task RTR, event(s) Rx'd */ + 10107f4: e17ff68b ldhu r5,-38(fp) + 10107f8: e13ff817 ldw r4,-32(fp) + 10107fc: 1010cac0 call 1010cac + 1010800: e0bff605 stb r2,-40(fp) + if (rdy == OS_TRUE) { + 1010804: e0bff603 ldbu r2,-40(fp) + 1010808: 10800058 cmpnei r2,r2,1 + 101080c: 1000211e bne r2,zero,1010894 + sched = OS_TRUE; /* When done we will reschedule */ + 1010810: 00800044 movi r2,1 + 1010814: e0bff785 stb r2,-34(fp) + } + } + break; + 1010818: 00001e06 br 1010894 + + case OS_FLAG_WAIT_CLR_ANY: /* See if any flag set */ + flags_rdy = (OS_FLAGS)(~pgrp->OSFlagFlags & pnode->OSFlagNodeFlags); + 101081c: e0bff917 ldw r2,-28(fp) + 1010820: 1080020b ldhu r2,8(r2) + 1010824: 0084303a nor r2,zero,r2 + 1010828: 1007883a mov r3,r2 + 101082c: e0bff817 ldw r2,-32(fp) + 1010830: 1080040b ldhu r2,16(r2) + 1010834: 1884703a and r2,r3,r2 + 1010838: e0bff68d sth r2,-38(fp) + if (flags_rdy != (OS_FLAGS)0) { + 101083c: e0bff68b ldhu r2,-38(fp) + 1010840: 1005003a cmpeq r2,r2,zero + 1010844: 1000131e bne r2,zero,1010894 + rdy = OS_FlagTaskRdy(pnode, flags_rdy); /* Make task RTR, event(s) Rx'd */ + 1010848: e17ff68b ldhu r5,-38(fp) + 101084c: e13ff817 ldw r4,-32(fp) + 1010850: 1010cac0 call 1010cac + 1010854: e0bff605 stb r2,-40(fp) + if (rdy == OS_TRUE) { + 1010858: e0bff603 ldbu r2,-40(fp) + 101085c: 10800058 cmpnei r2,r2,1 + 1010860: 10000c1e bne r2,zero,1010894 + sched = OS_TRUE; /* When done we will reschedule */ + 1010864: 00800044 movi r2,1 + 1010868: e0bff785 stb r2,-34(fp) + } + } + break; + 101086c: 00000906 br 1010894 + 1010870: e0bff517 ldw r2,-44(fp) + 1010874: e0bff215 stw r2,-56(fp) + 1010878: e0bff217 ldw r2,-56(fp) + 101087c: 1001703a wrctl status,r2 +#endif + default: + OS_EXIT_CRITICAL(); + *perr = OS_ERR_FLAG_WAIT_TYPE; + 1010880: e0fffc17 ldw r3,-16(fp) + 1010884: 00801bc4 movi r2,111 + 1010888: 18800005 stb r2,0(r3) + return ((OS_FLAGS)0); + 101088c: e03fff15 stw zero,-4(fp) + 1010890: 00002106 br 1010918 + } + pnode = (OS_FLAG_NODE *)pnode->OSFlagNodeNext; /* Point to next task waiting for event flag(s) */ + 1010894: e0bff817 ldw r2,-32(fp) + 1010898: 10800017 ldw r2,0(r2) + 101089c: e0bff815 stw r2,-32(fp) + *perr = OS_ERR_FLAG_INVALID_OPT; + return ((OS_FLAGS)0); + } + sched = OS_FALSE; /* Indicate that we don't need rescheduling */ + pnode = (OS_FLAG_NODE *)pgrp->OSFlagWaitList; + while (pnode != (OS_FLAG_NODE *)0) { /* Go through all tasks waiting on event flag(s) */ + 10108a0: e0bff817 ldw r2,-32(fp) + 10108a4: 1004c03a cmpne r2,r2,zero + 10108a8: 103f881e bne r2,zero,10106cc + 10108ac: e0bff517 ldw r2,-44(fp) + 10108b0: e0bff115 stw r2,-60(fp) + 10108b4: e0bff117 ldw r2,-60(fp) + 10108b8: 1001703a wrctl status,r2 + return ((OS_FLAGS)0); + } + pnode = (OS_FLAG_NODE *)pnode->OSFlagNodeNext; /* Point to next task waiting for event flag(s) */ + } + OS_EXIT_CRITICAL(); + if (sched == OS_TRUE) { + 10108bc: e0bff783 ldbu r2,-34(fp) + 10108c0: 10800058 cmpnei r2,r2,1 + 10108c4: 1000011e bne r2,zero,10108cc + OS_Sched(); + 10108c8: 100ecb80 call 100ecb8 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 10108cc: 0005303a rdctl r2,status + 10108d0: e0bff015 stw r2,-64(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 10108d4: e0fff017 ldw r3,-64(fp) + 10108d8: 00bfff84 movi r2,-2 + 10108dc: 1884703a and r2,r3,r2 + 10108e0: 1001703a wrctl status,r2 + + return context; + 10108e4: e0bff017 ldw r2,-64(fp) + } + OS_ENTER_CRITICAL(); + 10108e8: e0bff515 stw r2,-44(fp) + flags_cur = pgrp->OSFlagFlags; + 10108ec: e0bff917 ldw r2,-28(fp) + 10108f0: 1080020b ldhu r2,8(r2) + 10108f4: e0bff70d sth r2,-36(fp) + 10108f8: e0bff517 ldw r2,-44(fp) + 10108fc: e0bfef15 stw r2,-68(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1010900: e0bfef17 ldw r2,-68(fp) + 1010904: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + 1010908: e0bffc17 ldw r2,-16(fp) + 101090c: 10000005 stb zero,0(r2) + return (flags_cur); + 1010910: e0bff70b ldhu r2,-36(fp) + 1010914: e0bfff15 stw r2,-4(fp) + 1010918: e0bfff17 ldw r2,-4(fp) +} + 101091c: e037883a mov sp,fp + 1010920: dfc00117 ldw ra,4(sp) + 1010924: df000017 ldw fp,0(sp) + 1010928: dec00204 addi sp,sp,8 + 101092c: f800283a ret + +01010930 : +********************************************************************************************************* +*/ + +#if OS_FLAG_QUERY_EN > 0 +OS_FLAGS OSFlagQuery (OS_FLAG_GRP *pgrp, INT8U *perr) +{ + 1010930: defff804 addi sp,sp,-32 + 1010934: df000715 stw fp,28(sp) + 1010938: df000704 addi fp,sp,28 + 101093c: e13ffd15 stw r4,-12(fp) + 1010940: e17ffe15 stw r5,-8(fp) + OS_FLAGS flags; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 1010944: e03ffb15 stw zero,-20(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + 1010948: e0bffe17 ldw r2,-8(fp) + 101094c: 1004c03a cmpne r2,r2,zero + 1010950: 1000021e bne r2,zero,101095c + return ((OS_FLAGS)0); + 1010954: e03fff15 stw zero,-4(fp) + 1010958: 00002506 br 10109f0 + } + if (pgrp == (OS_FLAG_GRP *)0) { /* Validate 'pgrp' */ + 101095c: e0bffd17 ldw r2,-12(fp) + 1010960: 1004c03a cmpne r2,r2,zero + 1010964: 1000051e bne r2,zero,101097c + *perr = OS_ERR_FLAG_INVALID_PGRP; + 1010968: e0fffe17 ldw r3,-8(fp) + 101096c: 00801b84 movi r2,110 + 1010970: 18800005 stb r2,0(r3) + return ((OS_FLAGS)0); + 1010974: e03fff15 stw zero,-4(fp) + 1010978: 00001d06 br 10109f0 + } +#endif + if (pgrp->OSFlagType != OS_EVENT_TYPE_FLAG) { /* Validate event block type */ + 101097c: e0bffd17 ldw r2,-12(fp) + 1010980: 10800003 ldbu r2,0(r2) + 1010984: 10803fcc andi r2,r2,255 + 1010988: 10800160 cmpeqi r2,r2,5 + 101098c: 1000051e bne r2,zero,10109a4 + *perr = OS_ERR_EVENT_TYPE; + 1010990: e0fffe17 ldw r3,-8(fp) + 1010994: 00800044 movi r2,1 + 1010998: 18800005 stb r2,0(r3) + return ((OS_FLAGS)0); + 101099c: e03fff15 stw zero,-4(fp) + 10109a0: 00001306 br 10109f0 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 10109a4: 0005303a rdctl r2,status + 10109a8: e0bffa15 stw r2,-24(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 10109ac: e0fffa17 ldw r3,-24(fp) + 10109b0: 00bfff84 movi r2,-2 + 10109b4: 1884703a and r2,r3,r2 + 10109b8: 1001703a wrctl status,r2 + + return context; + 10109bc: e0bffa17 ldw r2,-24(fp) + } + OS_ENTER_CRITICAL(); + 10109c0: e0bffb15 stw r2,-20(fp) + flags = pgrp->OSFlagFlags; + 10109c4: e0bffd17 ldw r2,-12(fp) + 10109c8: 1080020b ldhu r2,8(r2) + 10109cc: e0bffc0d sth r2,-16(fp) + 10109d0: e0bffb17 ldw r2,-20(fp) + 10109d4: e0bff915 stw r2,-28(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 10109d8: e0bff917 ldw r2,-28(fp) + 10109dc: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + 10109e0: e0bffe17 ldw r2,-8(fp) + 10109e4: 10000005 stb zero,0(r2) + return (flags); /* Return the current value of the event flags */ + 10109e8: e0bffc0b ldhu r2,-16(fp) + 10109ec: e0bfff15 stw r2,-4(fp) + 10109f0: e0bfff17 ldw r2,-4(fp) +} + 10109f4: e037883a mov sp,fp + 10109f8: df000017 ldw fp,0(sp) + 10109fc: dec00104 addi sp,sp,4 + 1010a00: f800283a ret + +01010a04 : +* Note(s) : This function is INTERNAL to uC/OS-II and your application should not call it. +********************************************************************************************************* +*/ + +static void OS_FlagBlock (OS_FLAG_GRP *pgrp, OS_FLAG_NODE *pnode, OS_FLAGS flags, INT8U wait_type, INT16U timeout) +{ + 1010a04: defff804 addi sp,sp,-32 + 1010a08: df000715 stw fp,28(sp) + 1010a0c: df000704 addi fp,sp,28 + 1010a10: e13ffb15 stw r4,-20(fp) + 1010a14: e17ffc15 stw r5,-16(fp) + 1010a18: e0800117 ldw r2,4(fp) + 1010a1c: e1bffd0d sth r6,-12(fp) + 1010a20: e1fffe05 stb r7,-8(fp) + 1010a24: e0bfff0d sth r2,-4(fp) + OS_FLAG_NODE *pnode_next; + INT8U y; + + + OSTCBCur->OSTCBStat |= OS_STAT_FLAG; + 1010a28: 008040b4 movhi r2,258 + 1010a2c: 10b31f04 addi r2,r2,-13188 + 1010a30: 10c00017 ldw r3,0(r2) + 1010a34: 008040b4 movhi r2,258 + 1010a38: 10b31f04 addi r2,r2,-13188 + 1010a3c: 10800017 ldw r2,0(r2) + 1010a40: 10800c03 ldbu r2,48(r2) + 1010a44: 10800814 ori r2,r2,32 + 1010a48: 18800c05 stb r2,48(r3) + OSTCBCur->OSTCBStatPend = OS_STAT_PEND_OK; + 1010a4c: 008040b4 movhi r2,258 + 1010a50: 10b31f04 addi r2,r2,-13188 + 1010a54: 10800017 ldw r2,0(r2) + 1010a58: 10000c45 stb zero,49(r2) + OSTCBCur->OSTCBDly = timeout; /* Store timeout in task's TCB */ + 1010a5c: 008040b4 movhi r2,258 + 1010a60: 10b31f04 addi r2,r2,-13188 + 1010a64: 10c00017 ldw r3,0(r2) + 1010a68: e0bfff0b ldhu r2,-4(fp) + 1010a6c: 18800b8d sth r2,46(r3) +#if OS_TASK_DEL_EN > 0 + OSTCBCur->OSTCBFlagNode = pnode; /* TCB to link to node */ + 1010a70: 008040b4 movhi r2,258 + 1010a74: 10b31f04 addi r2,r2,-13188 + 1010a78: 10c00017 ldw r3,0(r2) + 1010a7c: e0bffc17 ldw r2,-16(fp) + 1010a80: 18800a15 stw r2,40(r3) +#endif + pnode->OSFlagNodeFlags = flags; /* Save the flags that we need to wait for */ + 1010a84: e0fffc17 ldw r3,-16(fp) + 1010a88: e0bffd0b ldhu r2,-12(fp) + 1010a8c: 1880040d sth r2,16(r3) + pnode->OSFlagNodeWaitType = wait_type; /* Save the type of wait we are doing */ + 1010a90: e0fffc17 ldw r3,-16(fp) + 1010a94: e0bffe03 ldbu r2,-8(fp) + 1010a98: 18800485 stb r2,18(r3) + pnode->OSFlagNodeTCB = (void *)OSTCBCur; /* Link to task's TCB */ + 1010a9c: 008040b4 movhi r2,258 + 1010aa0: 10b31f04 addi r2,r2,-13188 + 1010aa4: 10c00017 ldw r3,0(r2) + 1010aa8: e0bffc17 ldw r2,-16(fp) + 1010aac: 10c00215 stw r3,8(r2) + pnode->OSFlagNodeNext = pgrp->OSFlagWaitList; /* Add node at beginning of event flag wait list */ + 1010ab0: e0bffb17 ldw r2,-20(fp) + 1010ab4: 10c00117 ldw r3,4(r2) + 1010ab8: e0bffc17 ldw r2,-16(fp) + 1010abc: 10c00015 stw r3,0(r2) + pnode->OSFlagNodePrev = (void *)0; + 1010ac0: e0bffc17 ldw r2,-16(fp) + 1010ac4: 10000115 stw zero,4(r2) + pnode->OSFlagNodeFlagGrp = (void *)pgrp; /* Link to Event Flag Group */ + 1010ac8: e0fffc17 ldw r3,-16(fp) + 1010acc: e0bffb17 ldw r2,-20(fp) + 1010ad0: 18800315 stw r2,12(r3) + pnode_next = (OS_FLAG_NODE *)pgrp->OSFlagWaitList; + 1010ad4: e0bffb17 ldw r2,-20(fp) + 1010ad8: 10800117 ldw r2,4(r2) + 1010adc: e0bffa15 stw r2,-24(fp) + if (pnode_next != (void *)0) { /* Is this the first NODE to insert? */ + 1010ae0: e0bffa17 ldw r2,-24(fp) + 1010ae4: 1005003a cmpeq r2,r2,zero + 1010ae8: 1000031e bne r2,zero,1010af8 + pnode_next->OSFlagNodePrev = pnode; /* No, link in doubly linked list */ + 1010aec: e0fffa17 ldw r3,-24(fp) + 1010af0: e0bffc17 ldw r2,-16(fp) + 1010af4: 18800115 stw r2,4(r3) + } + pgrp->OSFlagWaitList = (void *)pnode; + 1010af8: e0fffb17 ldw r3,-20(fp) + 1010afc: e0bffc17 ldw r2,-16(fp) + 1010b00: 18800115 stw r2,4(r3) + + y = OSTCBCur->OSTCBY; /* Suspend current task until flag(s) received */ + 1010b04: 008040b4 movhi r2,258 + 1010b08: 10b31f04 addi r2,r2,-13188 + 1010b0c: 10800017 ldw r2,0(r2) + 1010b10: 10800d03 ldbu r2,52(r2) + 1010b14: e0bff905 stb r2,-28(fp) + OSRdyTbl[y] &= ~OSTCBCur->OSTCBBitX; + 1010b18: e13ff903 ldbu r4,-28(fp) + 1010b1c: e0fff903 ldbu r3,-28(fp) + 1010b20: 008040b4 movhi r2,258 + 1010b24: 10b31c44 addi r2,r2,-13199 + 1010b28: 10c5883a add r2,r2,r3 + 1010b2c: 10800003 ldbu r2,0(r2) + 1010b30: 1007883a mov r3,r2 + 1010b34: 008040b4 movhi r2,258 + 1010b38: 10b31f04 addi r2,r2,-13188 + 1010b3c: 10800017 ldw r2,0(r2) + 1010b40: 10800d43 ldbu r2,53(r2) + 1010b44: 0084303a nor r2,zero,r2 + 1010b48: 1884703a and r2,r3,r2 + 1010b4c: 1007883a mov r3,r2 + 1010b50: 008040b4 movhi r2,258 + 1010b54: 10b31c44 addi r2,r2,-13199 + 1010b58: 1105883a add r2,r2,r4 + 1010b5c: 10c00005 stb r3,0(r2) + if (OSRdyTbl[y] == 0x00) { + 1010b60: e0fff903 ldbu r3,-28(fp) + 1010b64: 008040b4 movhi r2,258 + 1010b68: 10b31c44 addi r2,r2,-13199 + 1010b6c: 10c5883a add r2,r2,r3 + 1010b70: 10800003 ldbu r2,0(r2) + 1010b74: 10803fcc andi r2,r2,255 + 1010b78: 1004c03a cmpne r2,r2,zero + 1010b7c: 10000e1e bne r2,zero,1010bb8 + OSRdyGrp &= ~OSTCBCur->OSTCBBitY; + 1010b80: 008040b4 movhi r2,258 + 1010b84: 10b31f04 addi r2,r2,-13188 + 1010b88: 10800017 ldw r2,0(r2) + 1010b8c: 10800d83 ldbu r2,54(r2) + 1010b90: 0084303a nor r2,zero,r2 + 1010b94: 1007883a mov r3,r2 + 1010b98: 008040b4 movhi r2,258 + 1010b9c: 10b31c04 addi r2,r2,-13200 + 1010ba0: 10800003 ldbu r2,0(r2) + 1010ba4: 1884703a and r2,r3,r2 + 1010ba8: 1007883a mov r3,r2 + 1010bac: 008040b4 movhi r2,258 + 1010bb0: 10b31c04 addi r2,r2,-13200 + 1010bb4: 10c00005 stb r3,0(r2) + } +} + 1010bb8: e037883a mov sp,fp + 1010bbc: df000017 ldw fp,0(sp) + 1010bc0: dec00104 addi sp,sp,4 + 1010bc4: f800283a ret + +01010bc8 : +* WARNING : You MUST NOT call this function from your code. This is an INTERNAL function to uC/OS-II. +********************************************************************************************************* +*/ + +void OS_FlagInit (void) +{ + 1010bc8: defffb04 addi sp,sp,-20 + 1010bcc: dfc00415 stw ra,16(sp) + 1010bd0: df000315 stw fp,12(sp) + 1010bd4: df000304 addi fp,sp,12 + INT16U i; + OS_FLAG_GRP *pgrp1; + OS_FLAG_GRP *pgrp2; + + + OS_MemClr((INT8U *)&OSFlagTbl[0], sizeof(OSFlagTbl)); /* Clear the flag group table */ + 1010bd8: 010040b4 movhi r4,258 + 1010bdc: 210d3504 addi r4,r4,13524 + 1010be0: 0140dc04 movi r5,880 + 1010be4: 100ebf80 call 100ebf8 + pgrp1 = &OSFlagTbl[0]; + 1010be8: 008040b4 movhi r2,258 + 1010bec: 108d3504 addi r2,r2,13524 + 1010bf0: e0bffe15 stw r2,-8(fp) + pgrp2 = &OSFlagTbl[1]; + 1010bf4: 008040b4 movhi r2,258 + 1010bf8: 108d4004 addi r2,r2,13568 + 1010bfc: e0bffd15 stw r2,-12(fp) + for (i = 0; i < (OS_MAX_FLAGS - 1); i++) { /* Init. list of free EVENT FLAGS */ + 1010c00: e03fff0d sth zero,-4(fp) + 1010c04: 00001306 br 1010c54 + pgrp1->OSFlagType = OS_EVENT_TYPE_UNUSED; + 1010c08: e0bffe17 ldw r2,-8(fp) + 1010c0c: 10000005 stb zero,0(r2) + pgrp1->OSFlagWaitList = (void *)pgrp2; + 1010c10: e0fffe17 ldw r3,-8(fp) + 1010c14: e0bffd17 ldw r2,-12(fp) + 1010c18: 18800115 stw r2,4(r3) +#if OS_FLAG_NAME_SIZE > 1 + pgrp1->OSFlagName[0] = '?'; /* Unknown name */ + 1010c1c: e0fffe17 ldw r3,-8(fp) + 1010c20: 00800fc4 movi r2,63 + 1010c24: 18800285 stb r2,10(r3) + pgrp1->OSFlagName[1] = OS_ASCII_NUL; + 1010c28: e0bffe17 ldw r2,-8(fp) + 1010c2c: 100002c5 stb zero,11(r2) +#endif + pgrp1++; + 1010c30: e0bffe17 ldw r2,-8(fp) + 1010c34: 10800b04 addi r2,r2,44 + 1010c38: e0bffe15 stw r2,-8(fp) + pgrp2++; + 1010c3c: e0bffd17 ldw r2,-12(fp) + 1010c40: 10800b04 addi r2,r2,44 + 1010c44: e0bffd15 stw r2,-12(fp) + + + OS_MemClr((INT8U *)&OSFlagTbl[0], sizeof(OSFlagTbl)); /* Clear the flag group table */ + pgrp1 = &OSFlagTbl[0]; + pgrp2 = &OSFlagTbl[1]; + for (i = 0; i < (OS_MAX_FLAGS - 1); i++) { /* Init. list of free EVENT FLAGS */ + 1010c48: e0bfff0b ldhu r2,-4(fp) + 1010c4c: 10800044 addi r2,r2,1 + 1010c50: e0bfff0d sth r2,-4(fp) + 1010c54: e0bfff0b ldhu r2,-4(fp) + 1010c58: 108004f0 cmpltui r2,r2,19 + 1010c5c: 103fea1e bne r2,zero,1010c08 + pgrp1->OSFlagName[1] = OS_ASCII_NUL; +#endif + pgrp1++; + pgrp2++; + } + pgrp1->OSFlagType = OS_EVENT_TYPE_UNUSED; + 1010c60: e0bffe17 ldw r2,-8(fp) + 1010c64: 10000005 stb zero,0(r2) + pgrp1->OSFlagWaitList = (void *)0; + 1010c68: e0bffe17 ldw r2,-8(fp) + 1010c6c: 10000115 stw zero,4(r2) +#if OS_FLAG_NAME_SIZE > 1 + pgrp1->OSFlagName[0] = '?'; /* Unknown name */ + 1010c70: e0fffe17 ldw r3,-8(fp) + 1010c74: 00800fc4 movi r2,63 + 1010c78: 18800285 stb r2,10(r3) + pgrp1->OSFlagName[1] = OS_ASCII_NUL; + 1010c7c: e0bffe17 ldw r2,-8(fp) + 1010c80: 100002c5 stb zero,11(r2) +#endif + OSFlagFreeList = &OSFlagTbl[0]; + 1010c84: 00c040b4 movhi r3,258 + 1010c88: 18f32104 addi r3,r3,-13180 + 1010c8c: 008040b4 movhi r2,258 + 1010c90: 108d3504 addi r2,r2,13524 + 1010c94: 18800015 stw r2,0(r3) +#endif +} + 1010c98: e037883a mov sp,fp + 1010c9c: dfc00117 ldw ra,4(sp) + 1010ca0: df000017 ldw fp,0(sp) + 1010ca4: dec00204 addi sp,sp,8 + 1010ca8: f800283a ret + +01010cac : +* 2) This function is INTERNAL to uC/OS-II and your application should not call it. +********************************************************************************************************* +*/ + +static BOOLEAN OS_FlagTaskRdy (OS_FLAG_NODE *pnode, OS_FLAGS flags_rdy) +{ + 1010cac: defffa04 addi sp,sp,-24 + 1010cb0: dfc00515 stw ra,20(sp) + 1010cb4: df000415 stw fp,16(sp) + 1010cb8: df000404 addi fp,sp,16 + 1010cbc: e13ffe15 stw r4,-8(fp) + 1010cc0: e17fff0d sth r5,-4(fp) + OS_TCB *ptcb; + BOOLEAN sched; + + + ptcb = (OS_TCB *)pnode->OSFlagNodeTCB; /* Point to TCB of waiting task */ + 1010cc4: e0bffe17 ldw r2,-8(fp) + 1010cc8: 10800217 ldw r2,8(r2) + 1010ccc: e0bffd15 stw r2,-12(fp) + ptcb->OSTCBDly = 0; + 1010cd0: e0bffd17 ldw r2,-12(fp) + 1010cd4: 10000b8d sth zero,46(r2) + ptcb->OSTCBFlagsRdy = flags_rdy; + 1010cd8: e0fffd17 ldw r3,-12(fp) + 1010cdc: e0bfff0b ldhu r2,-4(fp) + 1010ce0: 18800b0d sth r2,44(r3) + ptcb->OSTCBStat &= ~(INT8U)OS_STAT_FLAG; + 1010ce4: e0bffd17 ldw r2,-12(fp) + 1010ce8: 10c00c03 ldbu r3,48(r2) + 1010cec: 00bff7c4 movi r2,-33 + 1010cf0: 1884703a and r2,r3,r2 + 1010cf4: 1007883a mov r3,r2 + 1010cf8: e0bffd17 ldw r2,-12(fp) + 1010cfc: 10c00c05 stb r3,48(r2) + ptcb->OSTCBStatPend = OS_STAT_PEND_OK; + 1010d00: e0bffd17 ldw r2,-12(fp) + 1010d04: 10000c45 stb zero,49(r2) + if (ptcb->OSTCBStat == OS_STAT_RDY) { /* Task now ready? */ + 1010d08: e0bffd17 ldw r2,-12(fp) + 1010d0c: 10800c03 ldbu r2,48(r2) + 1010d10: 10803fcc andi r2,r2,255 + 1010d14: 1004c03a cmpne r2,r2,zero + 1010d18: 10001f1e bne r2,zero,1010d98 + OSRdyGrp |= ptcb->OSTCBBitY; /* Put task into ready list */ + 1010d1c: e0bffd17 ldw r2,-12(fp) + 1010d20: 10c00d83 ldbu r3,54(r2) + 1010d24: 008040b4 movhi r2,258 + 1010d28: 10b31c04 addi r2,r2,-13200 + 1010d2c: 10800003 ldbu r2,0(r2) + 1010d30: 1884b03a or r2,r3,r2 + 1010d34: 1007883a mov r3,r2 + 1010d38: 008040b4 movhi r2,258 + 1010d3c: 10b31c04 addi r2,r2,-13200 + 1010d40: 10c00005 stb r3,0(r2) + OSRdyTbl[ptcb->OSTCBY] |= ptcb->OSTCBBitX; + 1010d44: e0bffd17 ldw r2,-12(fp) + 1010d48: 10800d03 ldbu r2,52(r2) + 1010d4c: 11003fcc andi r4,r2,255 + 1010d50: e0bffd17 ldw r2,-12(fp) + 1010d54: 10800d03 ldbu r2,52(r2) + 1010d58: 10c03fcc andi r3,r2,255 + 1010d5c: 008040b4 movhi r2,258 + 1010d60: 10b31c44 addi r2,r2,-13199 + 1010d64: 10c5883a add r2,r2,r3 + 1010d68: 10c00003 ldbu r3,0(r2) + 1010d6c: e0bffd17 ldw r2,-12(fp) + 1010d70: 10800d43 ldbu r2,53(r2) + 1010d74: 1884b03a or r2,r3,r2 + 1010d78: 1007883a mov r3,r2 + 1010d7c: 008040b4 movhi r2,258 + 1010d80: 10b31c44 addi r2,r2,-13199 + 1010d84: 1105883a add r2,r2,r4 + 1010d88: 10c00005 stb r3,0(r2) + sched = OS_TRUE; + 1010d8c: 00800044 movi r2,1 + 1010d90: e0bffc05 stb r2,-16(fp) + 1010d94: 00000106 br 1010d9c + } else { + sched = OS_FALSE; + 1010d98: e03ffc05 stb zero,-16(fp) + } + OS_FlagUnlink(pnode); + 1010d9c: e13ffe17 ldw r4,-8(fp) + 1010da0: 1010dbc0 call 1010dbc + return (sched); + 1010da4: e0bffc03 ldbu r2,-16(fp) +} + 1010da8: e037883a mov sp,fp + 1010dac: dfc00117 ldw ra,4(sp) + 1010db0: df000017 ldw fp,0(sp) + 1010db4: dec00204 addi sp,sp,8 + 1010db8: f800283a ret + +01010dbc : +* 2) This function is INTERNAL to uC/OS-II and your application should not call it. +********************************************************************************************************* +*/ + +void OS_FlagUnlink (OS_FLAG_NODE *pnode) +{ + 1010dbc: defffa04 addi sp,sp,-24 + 1010dc0: df000515 stw fp,20(sp) + 1010dc4: df000504 addi fp,sp,20 + 1010dc8: e13fff15 stw r4,-4(fp) + OS_FLAG_GRP *pgrp; + OS_FLAG_NODE *pnode_prev; + OS_FLAG_NODE *pnode_next; + + + pnode_prev = (OS_FLAG_NODE *)pnode->OSFlagNodePrev; + 1010dcc: e0bfff17 ldw r2,-4(fp) + 1010dd0: 10800117 ldw r2,4(r2) + 1010dd4: e0bffc15 stw r2,-16(fp) + pnode_next = (OS_FLAG_NODE *)pnode->OSFlagNodeNext; + 1010dd8: e0bfff17 ldw r2,-4(fp) + 1010ddc: 10800017 ldw r2,0(r2) + 1010de0: e0bffb15 stw r2,-20(fp) + if (pnode_prev == (OS_FLAG_NODE *)0) { /* Is it first node in wait list? */ + 1010de4: e0bffc17 ldw r2,-16(fp) + 1010de8: 1004c03a cmpne r2,r2,zero + 1010dec: 10000c1e bne r2,zero,1010e20 + pgrp = (OS_FLAG_GRP *)pnode->OSFlagNodeFlagGrp; + 1010df0: e0bfff17 ldw r2,-4(fp) + 1010df4: 10800317 ldw r2,12(r2) + 1010df8: e0bffd15 stw r2,-12(fp) + pgrp->OSFlagWaitList = (void *)pnode_next; /* Update list for new 1st node */ + 1010dfc: e0fffd17 ldw r3,-12(fp) + 1010e00: e0bffb17 ldw r2,-20(fp) + 1010e04: 18800115 stw r2,4(r3) + if (pnode_next != (OS_FLAG_NODE *)0) { + 1010e08: e0bffb17 ldw r2,-20(fp) + 1010e0c: 1005003a cmpeq r2,r2,zero + 1010e10: 10000c1e bne r2,zero,1010e44 + pnode_next->OSFlagNodePrev = (OS_FLAG_NODE *)0; /* Link new 1st node PREV to NULL */ + 1010e14: e0bffb17 ldw r2,-20(fp) + 1010e18: 10000115 stw zero,4(r2) + 1010e1c: 00000906 br 1010e44 + } + } else { /* No, A node somewhere in the list */ + pnode_prev->OSFlagNodeNext = pnode_next; /* Link around the node to unlink */ + 1010e20: e0fffc17 ldw r3,-16(fp) + 1010e24: e0bffb17 ldw r2,-20(fp) + 1010e28: 18800015 stw r2,0(r3) + if (pnode_next != (OS_FLAG_NODE *)0) { /* Was this the LAST node? */ + 1010e2c: e0bffb17 ldw r2,-20(fp) + 1010e30: 1005003a cmpeq r2,r2,zero + 1010e34: 1000031e bne r2,zero,1010e44 + pnode_next->OSFlagNodePrev = pnode_prev; /* No, Link around current node */ + 1010e38: e0fffb17 ldw r3,-20(fp) + 1010e3c: e0bffc17 ldw r2,-16(fp) + 1010e40: 18800115 stw r2,4(r3) + } + } +#if OS_TASK_DEL_EN > 0 + ptcb = (OS_TCB *)pnode->OSFlagNodeTCB; + 1010e44: e0bfff17 ldw r2,-4(fp) + 1010e48: 10800217 ldw r2,8(r2) + 1010e4c: e0bffe15 stw r2,-8(fp) + ptcb->OSTCBFlagNode = (OS_FLAG_NODE *)0; + 1010e50: e0bffe17 ldw r2,-8(fp) + 1010e54: 10000a15 stw zero,40(r2) +#endif +} + 1010e58: e037883a mov sp,fp + 1010e5c: df000017 ldw fp,0(sp) + 1010e60: dec00104 addi sp,sp,4 + 1010e64: f800283a ret + +01010e68 : +* free partition is available. +********************************************************************************************************* +*/ + +OS_MEM *OSMemCreate (void *addr, INT32U nblks, INT32U blksize, INT8U *perr) +{ + 1010e68: defff304 addi sp,sp,-52 + 1010e6c: df000c15 stw fp,48(sp) + 1010e70: df000c04 addi fp,sp,48 + 1010e74: e13ffb15 stw r4,-20(fp) + 1010e78: e17ffc15 stw r5,-16(fp) + 1010e7c: e1bffd15 stw r6,-12(fp) + 1010e80: e1fffe15 stw r7,-8(fp) + OS_MEM *pmem; + INT8U *pblk; + void **plink; + INT32U i; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 1010e84: e03ff615 stw zero,-40(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + 1010e88: e0bffe17 ldw r2,-8(fp) + 1010e8c: 1004c03a cmpne r2,r2,zero + 1010e90: 1000021e bne r2,zero,1010e9c + return ((OS_MEM *)0); + 1010e94: e03fff15 stw zero,-4(fp) + 1010e98: 00007506 br 1011070 + } + if (addr == (void *)0) { /* Must pass a valid address for the memory part.*/ + 1010e9c: e0bffb17 ldw r2,-20(fp) + 1010ea0: 1004c03a cmpne r2,r2,zero + 1010ea4: 1000051e bne r2,zero,1010ebc + *perr = OS_ERR_MEM_INVALID_ADDR; + 1010ea8: e0fffe17 ldw r3,-8(fp) + 1010eac: 00801884 movi r2,98 + 1010eb0: 18800005 stb r2,0(r3) + return ((OS_MEM *)0); + 1010eb4: e03fff15 stw zero,-4(fp) + 1010eb8: 00006d06 br 1011070 + } + if (((INT32U)addr & (sizeof(void *) - 1)) != 0){ /* Must be pointer size aligned */ + 1010ebc: e0bffb17 ldw r2,-20(fp) + 1010ec0: 108000cc andi r2,r2,3 + 1010ec4: 1005003a cmpeq r2,r2,zero + 1010ec8: 1000051e bne r2,zero,1010ee0 + *perr = OS_ERR_MEM_INVALID_ADDR; + 1010ecc: e0fffe17 ldw r3,-8(fp) + 1010ed0: 00801884 movi r2,98 + 1010ed4: 18800005 stb r2,0(r3) + return ((OS_MEM *)0); + 1010ed8: e03fff15 stw zero,-4(fp) + 1010edc: 00006406 br 1011070 + } + if (nblks < 2) { /* Must have at least 2 blocks per partition */ + 1010ee0: e0bffc17 ldw r2,-16(fp) + 1010ee4: 108000a8 cmpgeui r2,r2,2 + 1010ee8: 1000051e bne r2,zero,1010f00 + *perr = OS_ERR_MEM_INVALID_BLKS; + 1010eec: e0fffe17 ldw r3,-8(fp) + 1010ef0: 008016c4 movi r2,91 + 1010ef4: 18800005 stb r2,0(r3) + return ((OS_MEM *)0); + 1010ef8: e03fff15 stw zero,-4(fp) + 1010efc: 00005c06 br 1011070 + } + if (blksize < sizeof(void *)) { /* Must contain space for at least a pointer */ + 1010f00: e0bffd17 ldw r2,-12(fp) + 1010f04: 10800128 cmpgeui r2,r2,4 + 1010f08: 1000051e bne r2,zero,1010f20 + *perr = OS_ERR_MEM_INVALID_SIZE; + 1010f0c: e0fffe17 ldw r3,-8(fp) + 1010f10: 00801704 movi r2,92 + 1010f14: 18800005 stb r2,0(r3) + return ((OS_MEM *)0); + 1010f18: e03fff15 stw zero,-4(fp) + 1010f1c: 00005406 br 1011070 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1010f20: 0005303a rdctl r2,status + 1010f24: e0bff515 stw r2,-44(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1010f28: e0fff517 ldw r3,-44(fp) + 1010f2c: 00bfff84 movi r2,-2 + 1010f30: 1884703a and r2,r3,r2 + 1010f34: 1001703a wrctl status,r2 + + return context; + 1010f38: e0bff517 ldw r2,-44(fp) + } +#endif + OS_ENTER_CRITICAL(); + 1010f3c: e0bff615 stw r2,-40(fp) + pmem = OSMemFreeList; /* Get next free memory partition */ + 1010f40: 008040b4 movhi r2,258 + 1010f44: 10b31904 addi r2,r2,-13212 + 1010f48: 10800017 ldw r2,0(r2) + 1010f4c: e0bffa15 stw r2,-24(fp) + if (OSMemFreeList != (OS_MEM *)0) { /* See if pool of free partitions was empty */ + 1010f50: 008040b4 movhi r2,258 + 1010f54: 10b31904 addi r2,r2,-13212 + 1010f58: 10800017 ldw r2,0(r2) + 1010f5c: 1005003a cmpeq r2,r2,zero + 1010f60: 1000081e bne r2,zero,1010f84 + OSMemFreeList = (OS_MEM *)OSMemFreeList->OSMemFreeList; + 1010f64: 008040b4 movhi r2,258 + 1010f68: 10b31904 addi r2,r2,-13212 + 1010f6c: 10800017 ldw r2,0(r2) + 1010f70: 10800117 ldw r2,4(r2) + 1010f74: 1007883a mov r3,r2 + 1010f78: 008040b4 movhi r2,258 + 1010f7c: 10b31904 addi r2,r2,-13212 + 1010f80: 10c00015 stw r3,0(r2) + 1010f84: e0bff617 ldw r2,-40(fp) + 1010f88: e0bff415 stw r2,-48(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1010f8c: e0bff417 ldw r2,-48(fp) + 1010f90: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); + if (pmem == (OS_MEM *)0) { /* See if we have a memory partition */ + 1010f94: e0bffa17 ldw r2,-24(fp) + 1010f98: 1004c03a cmpne r2,r2,zero + 1010f9c: 1000051e bne r2,zero,1010fb4 + *perr = OS_ERR_MEM_INVALID_PART; + 1010fa0: e0fffe17 ldw r3,-8(fp) + 1010fa4: 00801684 movi r2,90 + 1010fa8: 18800005 stb r2,0(r3) + return ((OS_MEM *)0); + 1010fac: e03fff15 stw zero,-4(fp) + 1010fb0: 00002f06 br 1011070 + } + plink = (void **)addr; /* Create linked list of free memory blocks */ + 1010fb4: e0bffb17 ldw r2,-20(fp) + 1010fb8: e0bff815 stw r2,-32(fp) + pblk = (INT8U *)((INT32U)addr + blksize); + 1010fbc: e0bffb17 ldw r2,-20(fp) + 1010fc0: 1007883a mov r3,r2 + 1010fc4: e0bffd17 ldw r2,-12(fp) + 1010fc8: 1885883a add r2,r3,r2 + 1010fcc: e0bff915 stw r2,-28(fp) + for (i = 0; i < (nblks - 1); i++) { + 1010fd0: e03ff715 stw zero,-36(fp) + 1010fd4: 00000d06 br 101100c + *plink = (void *)pblk; /* Save pointer to NEXT block in CURRENT block */ + 1010fd8: e0fff817 ldw r3,-32(fp) + 1010fdc: e0bff917 ldw r2,-28(fp) + 1010fe0: 18800015 stw r2,0(r3) + plink = (void **)pblk; /* Position to NEXT block */ + 1010fe4: e0bff917 ldw r2,-28(fp) + 1010fe8: e0bff815 stw r2,-32(fp) + pblk = (INT8U *)((INT32U)pblk + blksize); /* Point to the FOLLOWING block */ + 1010fec: e0bff917 ldw r2,-28(fp) + 1010ff0: 1007883a mov r3,r2 + 1010ff4: e0bffd17 ldw r2,-12(fp) + 1010ff8: 1885883a add r2,r3,r2 + 1010ffc: e0bff915 stw r2,-28(fp) + *perr = OS_ERR_MEM_INVALID_PART; + return ((OS_MEM *)0); + } + plink = (void **)addr; /* Create linked list of free memory blocks */ + pblk = (INT8U *)((INT32U)addr + blksize); + for (i = 0; i < (nblks - 1); i++) { + 1011000: e0bff717 ldw r2,-36(fp) + 1011004: 10800044 addi r2,r2,1 + 1011008: e0bff715 stw r2,-36(fp) + 101100c: e0bffc17 ldw r2,-16(fp) + 1011010: 10ffffc4 addi r3,r2,-1 + 1011014: e0bff717 ldw r2,-36(fp) + 1011018: 10ffef36 bltu r2,r3,1010fd8 + *plink = (void *)pblk; /* Save pointer to NEXT block in CURRENT block */ + plink = (void **)pblk; /* Position to NEXT block */ + pblk = (INT8U *)((INT32U)pblk + blksize); /* Point to the FOLLOWING block */ + } + *plink = (void *)0; /* Last memory block points to NULL */ + 101101c: e0bff817 ldw r2,-32(fp) + 1011020: 10000015 stw zero,0(r2) + pmem->OSMemAddr = addr; /* Store start address of memory partition */ + 1011024: e0fffa17 ldw r3,-24(fp) + 1011028: e0bffb17 ldw r2,-20(fp) + 101102c: 18800015 stw r2,0(r3) + pmem->OSMemFreeList = addr; /* Initialize pointer to pool of free blocks */ + 1011030: e0fffa17 ldw r3,-24(fp) + 1011034: e0bffb17 ldw r2,-20(fp) + 1011038: 18800115 stw r2,4(r3) + pmem->OSMemNFree = nblks; /* Store number of free blocks in MCB */ + 101103c: e0fffa17 ldw r3,-24(fp) + 1011040: e0bffc17 ldw r2,-16(fp) + 1011044: 18800415 stw r2,16(r3) + pmem->OSMemNBlks = nblks; + 1011048: e0fffa17 ldw r3,-24(fp) + 101104c: e0bffc17 ldw r2,-16(fp) + 1011050: 18800315 stw r2,12(r3) + pmem->OSMemBlkSize = blksize; /* Store block size of each memory blocks */ + 1011054: e0fffa17 ldw r3,-24(fp) + 1011058: e0bffd17 ldw r2,-12(fp) + 101105c: 18800215 stw r2,8(r3) + *perr = OS_ERR_NONE; + 1011060: e0bffe17 ldw r2,-8(fp) + 1011064: 10000005 stb zero,0(r2) + return (pmem); + 1011068: e0bffa17 ldw r2,-24(fp) + 101106c: e0bfff15 stw r2,-4(fp) + 1011070: e0bfff17 ldw r2,-4(fp) +} + 1011074: e037883a mov sp,fp + 1011078: df000017 ldw fp,0(sp) + 101107c: dec00104 addi sp,sp,4 + 1011080: f800283a ret + +01011084 : +* A pointer to NULL if an error is detected +********************************************************************************************************* +*/ + +void *OSMemGet (OS_MEM *pmem, INT8U *perr) +{ + 1011084: defff704 addi sp,sp,-36 + 1011088: df000815 stw fp,32(sp) + 101108c: df000804 addi fp,sp,32 + 1011090: e13ffd15 stw r4,-12(fp) + 1011094: e17ffe15 stw r5,-8(fp) + void *pblk; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 1011098: e03ffb15 stw zero,-20(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + 101109c: e0bffe17 ldw r2,-8(fp) + 10110a0: 1004c03a cmpne r2,r2,zero + 10110a4: 1000021e bne r2,zero,10110b0 + return ((void *)0); + 10110a8: e03fff15 stw zero,-4(fp) + 10110ac: 00003106 br 1011174 + } + if (pmem == (OS_MEM *)0) { /* Must point to a valid memory partition */ + 10110b0: e0bffd17 ldw r2,-12(fp) + 10110b4: 1004c03a cmpne r2,r2,zero + 10110b8: 1000051e bne r2,zero,10110d0 + *perr = OS_ERR_MEM_INVALID_PMEM; + 10110bc: e0fffe17 ldw r3,-8(fp) + 10110c0: 00801804 movi r2,96 + 10110c4: 18800005 stb r2,0(r3) + return ((void *)0); + 10110c8: e03fff15 stw zero,-4(fp) + 10110cc: 00002906 br 1011174 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 10110d0: 0005303a rdctl r2,status + 10110d4: e0bffa15 stw r2,-24(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 10110d8: e0fffa17 ldw r3,-24(fp) + 10110dc: 00bfff84 movi r2,-2 + 10110e0: 1884703a and r2,r3,r2 + 10110e4: 1001703a wrctl status,r2 + + return context; + 10110e8: e0bffa17 ldw r2,-24(fp) + } +#endif + OS_ENTER_CRITICAL(); + 10110ec: e0bffb15 stw r2,-20(fp) + if (pmem->OSMemNFree > 0) { /* See if there are any free memory blocks */ + 10110f0: e0bffd17 ldw r2,-12(fp) + 10110f4: 10800417 ldw r2,16(r2) + 10110f8: 1005003a cmpeq r2,r2,zero + 10110fc: 1000151e bne r2,zero,1011154 + pblk = pmem->OSMemFreeList; /* Yes, point to next free memory block */ + 1011100: e0bffd17 ldw r2,-12(fp) + 1011104: 10800117 ldw r2,4(r2) + 1011108: e0bffc15 stw r2,-16(fp) + pmem->OSMemFreeList = *(void **)pblk; /* Adjust pointer to new free list */ + 101110c: e0bffc17 ldw r2,-16(fp) + 1011110: 10c00017 ldw r3,0(r2) + 1011114: e0bffd17 ldw r2,-12(fp) + 1011118: 10c00115 stw r3,4(r2) + pmem->OSMemNFree--; /* One less memory block in this partition */ + 101111c: e0bffd17 ldw r2,-12(fp) + 1011120: 10800417 ldw r2,16(r2) + 1011124: 10ffffc4 addi r3,r2,-1 + 1011128: e0bffd17 ldw r2,-12(fp) + 101112c: 10c00415 stw r3,16(r2) + 1011130: e0bffb17 ldw r2,-20(fp) + 1011134: e0bff915 stw r2,-28(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1011138: e0bff917 ldw r2,-28(fp) + 101113c: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; /* No error */ + 1011140: e0bffe17 ldw r2,-8(fp) + 1011144: 10000005 stb zero,0(r2) + return (pblk); /* Return memory block to caller */ + 1011148: e0bffc17 ldw r2,-16(fp) + 101114c: e0bfff15 stw r2,-4(fp) + 1011150: 00000806 br 1011174 + 1011154: e0bffb17 ldw r2,-20(fp) + 1011158: e0bff815 stw r2,-32(fp) + 101115c: e0bff817 ldw r2,-32(fp) + 1011160: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); + *perr = OS_ERR_MEM_NO_FREE_BLKS; /* No, Notify caller of empty memory partition */ + 1011164: e0fffe17 ldw r3,-8(fp) + 1011168: 00801744 movi r2,93 + 101116c: 18800005 stb r2,0(r3) + return ((void *)0); /* Return NULL pointer to caller */ + 1011170: e03fff15 stw zero,-4(fp) + 1011174: e0bfff17 ldw r2,-4(fp) +} + 1011178: e037883a mov sp,fp + 101117c: df000017 ldw fp,0(sp) + 1011180: dec00104 addi sp,sp,4 + 1011184: f800283a ret + +01011188 : +********************************************************************************************************* +*/ + +#if OS_MEM_NAME_SIZE > 1 +INT8U OSMemNameGet (OS_MEM *pmem, INT8U *pname, INT8U *perr) +{ + 1011188: defff604 addi sp,sp,-40 + 101118c: dfc00915 stw ra,36(sp) + 1011190: df000815 stw fp,32(sp) + 1011194: df000804 addi fp,sp,32 + 1011198: e13ffc15 stw r4,-16(fp) + 101119c: e17ffd15 stw r5,-12(fp) + 10111a0: e1bffe15 stw r6,-8(fp) + INT8U len; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 10111a4: e03ffa15 stw zero,-24(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + 10111a8: e0bffe17 ldw r2,-8(fp) + 10111ac: 1004c03a cmpne r2,r2,zero + 10111b0: 1000021e bne r2,zero,10111bc + return (0); + 10111b4: e03fff15 stw zero,-4(fp) + 10111b8: 00003006 br 101127c + } + if (pmem == (OS_MEM *)0) { /* Is 'pmem' a NULL pointer? */ + 10111bc: e0bffc17 ldw r2,-16(fp) + 10111c0: 1004c03a cmpne r2,r2,zero + 10111c4: 1000051e bne r2,zero,10111dc + *perr = OS_ERR_MEM_INVALID_PMEM; + 10111c8: e0fffe17 ldw r3,-8(fp) + 10111cc: 00801804 movi r2,96 + 10111d0: 18800005 stb r2,0(r3) + return (0); + 10111d4: e03fff15 stw zero,-4(fp) + 10111d8: 00002806 br 101127c + } + if (pname == (INT8U *)0) { /* Is 'pname' a NULL pointer? */ + 10111dc: e0bffd17 ldw r2,-12(fp) + 10111e0: 1004c03a cmpne r2,r2,zero + 10111e4: 1000051e bne r2,zero,10111fc + *perr = OS_ERR_PNAME_NULL; + 10111e8: e0fffe17 ldw r3,-8(fp) + 10111ec: 00800304 movi r2,12 + 10111f0: 18800005 stb r2,0(r3) + return (0); + 10111f4: e03fff15 stw zero,-4(fp) + 10111f8: 00002006 br 101127c + } +#endif + if (OSIntNesting > 0) { /* See if trying to call from an ISR */ + 10111fc: 008040b4 movhi r2,258 + 1011200: 10b31e04 addi r2,r2,-13192 + 1011204: 10800003 ldbu r2,0(r2) + 1011208: 10803fcc andi r2,r2,255 + 101120c: 1005003a cmpeq r2,r2,zero + 1011210: 1000051e bne r2,zero,1011228 + *perr = OS_ERR_NAME_GET_ISR; + 1011214: e0fffe17 ldw r3,-8(fp) + 1011218: 00800444 movi r2,17 + 101121c: 18800005 stb r2,0(r3) + return (0); + 1011220: e03fff15 stw zero,-4(fp) + 1011224: 00001506 br 101127c +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1011228: 0005303a rdctl r2,status + 101122c: e0bff915 stw r2,-28(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1011230: e0fff917 ldw r3,-28(fp) + 1011234: 00bfff84 movi r2,-2 + 1011238: 1884703a and r2,r3,r2 + 101123c: 1001703a wrctl status,r2 + + return context; + 1011240: e0bff917 ldw r2,-28(fp) + } + OS_ENTER_CRITICAL(); + 1011244: e0bffa15 stw r2,-24(fp) + len = OS_StrCopy(pname, pmem->OSMemName); /* Copy name from OS_MEM */ + 1011248: e0bffc17 ldw r2,-16(fp) + 101124c: 11400504 addi r5,r2,20 + 1011250: e13ffd17 ldw r4,-12(fp) + 1011254: 100edfc0 call 100edfc + 1011258: e0bffb05 stb r2,-20(fp) + 101125c: e0bffa17 ldw r2,-24(fp) + 1011260: e0bff815 stw r2,-32(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1011264: e0bff817 ldw r2,-32(fp) + 1011268: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + 101126c: e0bffe17 ldw r2,-8(fp) + 1011270: 10000005 stb zero,0(r2) + return (len); + 1011274: e0bffb03 ldbu r2,-20(fp) + 1011278: e0bfff15 stw r2,-4(fp) + 101127c: e0bfff17 ldw r2,-4(fp) +} + 1011280: e037883a mov sp,fp + 1011284: dfc00117 ldw ra,4(sp) + 1011288: df000017 ldw fp,0(sp) + 101128c: dec00204 addi sp,sp,8 + 1011290: f800283a ret + +01011294 : +********************************************************************************************************* +*/ + +#if OS_MEM_NAME_SIZE > 1 +void OSMemNameSet (OS_MEM *pmem, INT8U *pname, INT8U *perr) +{ + 1011294: defff604 addi sp,sp,-40 + 1011298: dfc00915 stw ra,36(sp) + 101129c: df000815 stw fp,32(sp) + 10112a0: df000804 addi fp,sp,32 + 10112a4: e13ffd15 stw r4,-12(fp) + 10112a8: e17ffe15 stw r5,-8(fp) + 10112ac: e1bfff15 stw r6,-4(fp) + INT8U len; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 10112b0: e03ffb15 stw zero,-20(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + 10112b4: e0bfff17 ldw r2,-4(fp) + 10112b8: 1005003a cmpeq r2,r2,zero + 10112bc: 1000381e bne r2,zero,10113a0 + return; + } + if (pmem == (OS_MEM *)0) { /* Is 'pmem' a NULL pointer? */ + 10112c0: e0bffd17 ldw r2,-12(fp) + 10112c4: 1004c03a cmpne r2,r2,zero + 10112c8: 1000041e bne r2,zero,10112dc + *perr = OS_ERR_MEM_INVALID_PMEM; + 10112cc: e0ffff17 ldw r3,-4(fp) + 10112d0: 00801804 movi r2,96 + 10112d4: 18800005 stb r2,0(r3) + return; + 10112d8: 00003106 br 10113a0 + } + if (pname == (INT8U *)0) { /* Is 'pname' a NULL pointer? */ + 10112dc: e0bffe17 ldw r2,-8(fp) + 10112e0: 1004c03a cmpne r2,r2,zero + 10112e4: 1000041e bne r2,zero,10112f8 + *perr = OS_ERR_PNAME_NULL; + 10112e8: e0ffff17 ldw r3,-4(fp) + 10112ec: 00800304 movi r2,12 + 10112f0: 18800005 stb r2,0(r3) + return; + 10112f4: 00002a06 br 10113a0 + } +#endif + if (OSIntNesting > 0) { /* See if trying to call from an ISR */ + 10112f8: 008040b4 movhi r2,258 + 10112fc: 10b31e04 addi r2,r2,-13192 + 1011300: 10800003 ldbu r2,0(r2) + 1011304: 10803fcc andi r2,r2,255 + 1011308: 1005003a cmpeq r2,r2,zero + 101130c: 1000041e bne r2,zero,1011320 + *perr = OS_ERR_NAME_SET_ISR; + 1011310: e0ffff17 ldw r3,-4(fp) + 1011314: 00800484 movi r2,18 + 1011318: 18800005 stb r2,0(r3) + return; + 101131c: 00002006 br 10113a0 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1011320: 0005303a rdctl r2,status + 1011324: e0bffa15 stw r2,-24(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1011328: e0fffa17 ldw r3,-24(fp) + 101132c: 00bfff84 movi r2,-2 + 1011330: 1884703a and r2,r3,r2 + 1011334: 1001703a wrctl status,r2 + + return context; + 1011338: e0bffa17 ldw r2,-24(fp) + } + OS_ENTER_CRITICAL(); + 101133c: e0bffb15 stw r2,-20(fp) + len = OS_StrLen(pname); /* Can we fit the string in the storage area? */ + 1011340: e13ffe17 ldw r4,-8(fp) + 1011344: 100ee7c0 call 100ee7c + 1011348: e0bffc05 stb r2,-16(fp) + if (len > (OS_MEM_NAME_SIZE - 1)) { /* No */ + 101134c: e0bffc03 ldbu r2,-16(fp) + 1011350: 10800830 cmpltui r2,r2,32 + 1011354: 1000081e bne r2,zero,1011378 + 1011358: e0bffb17 ldw r2,-20(fp) + 101135c: e0bff915 stw r2,-28(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1011360: e0bff917 ldw r2,-28(fp) + 1011364: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + *perr = OS_ERR_MEM_NAME_TOO_LONG; + 1011368: e0ffff17 ldw r3,-4(fp) + 101136c: 008018c4 movi r2,99 + 1011370: 18800005 stb r2,0(r3) + return; + 1011374: 00000a06 br 10113a0 + } + (void)OS_StrCopy(pmem->OSMemName, pname); /* Yes, copy name to the memory partition header */ + 1011378: e0bffd17 ldw r2,-12(fp) + 101137c: 11000504 addi r4,r2,20 + 1011380: e17ffe17 ldw r5,-8(fp) + 1011384: 100edfc0 call 100edfc + 1011388: e0bffb17 ldw r2,-20(fp) + 101138c: e0bff815 stw r2,-32(fp) + 1011390: e0bff817 ldw r2,-32(fp) + 1011394: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + 1011398: e0bfff17 ldw r2,-4(fp) + 101139c: 10000005 stb zero,0(r2) +} + 10113a0: e037883a mov sp,fp + 10113a4: dfc00117 ldw ra,4(sp) + 10113a8: df000017 ldw fp,0(sp) + 10113ac: dec00204 addi sp,sp,8 + 10113b0: f800283a ret + +010113b4 : +* OS_ERR_MEM_INVALID_PBLK if you passed a NULL pointer for the block to release. +********************************************************************************************************* +*/ + +INT8U OSMemPut (OS_MEM *pmem, void *pblk) +{ + 10113b4: defff804 addi sp,sp,-32 + 10113b8: df000715 stw fp,28(sp) + 10113bc: df000704 addi fp,sp,28 + 10113c0: e13ffd15 stw r4,-12(fp) + 10113c4: e17ffe15 stw r5,-8(fp) +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 10113c8: e03ffc15 stw zero,-16(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (pmem == (OS_MEM *)0) { /* Must point to a valid memory partition */ + 10113cc: e0bffd17 ldw r2,-12(fp) + 10113d0: 1004c03a cmpne r2,r2,zero + 10113d4: 1000031e bne r2,zero,10113e4 + return (OS_ERR_MEM_INVALID_PMEM); + 10113d8: 00801804 movi r2,96 + 10113dc: e0bfff15 stw r2,-4(fp) + 10113e0: 00002b06 br 1011490 + } + if (pblk == (void *)0) { /* Must release a valid block */ + 10113e4: e0bffe17 ldw r2,-8(fp) + 10113e8: 1004c03a cmpne r2,r2,zero + 10113ec: 1000031e bne r2,zero,10113fc + return (OS_ERR_MEM_INVALID_PBLK); + 10113f0: 008017c4 movi r2,95 + 10113f4: e0bfff15 stw r2,-4(fp) + 10113f8: 00002506 br 1011490 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 10113fc: 0005303a rdctl r2,status + 1011400: e0bffb15 stw r2,-20(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1011404: e0fffb17 ldw r3,-20(fp) + 1011408: 00bfff84 movi r2,-2 + 101140c: 1884703a and r2,r3,r2 + 1011410: 1001703a wrctl status,r2 + + return context; + 1011414: e0bffb17 ldw r2,-20(fp) + } +#endif + OS_ENTER_CRITICAL(); + 1011418: e0bffc15 stw r2,-16(fp) + if (pmem->OSMemNFree >= pmem->OSMemNBlks) { /* Make sure all blocks not already returned */ + 101141c: e0bffd17 ldw r2,-12(fp) + 1011420: 10c00417 ldw r3,16(r2) + 1011424: e0bffd17 ldw r2,-12(fp) + 1011428: 10800317 ldw r2,12(r2) + 101142c: 18800736 bltu r3,r2,101144c + 1011430: e0bffc17 ldw r2,-16(fp) + 1011434: e0bffa15 stw r2,-24(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1011438: e0bffa17 ldw r2,-24(fp) + 101143c: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_MEM_FULL); + 1011440: 00801784 movi r2,94 + 1011444: e0bfff15 stw r2,-4(fp) + 1011448: 00001106 br 1011490 + } + *(void **)pblk = pmem->OSMemFreeList; /* Insert released block into free block list */ + 101144c: e0fffe17 ldw r3,-8(fp) + 1011450: e0bffd17 ldw r2,-12(fp) + 1011454: 10800117 ldw r2,4(r2) + 1011458: 18800015 stw r2,0(r3) + pmem->OSMemFreeList = pblk; + 101145c: e0fffd17 ldw r3,-12(fp) + 1011460: e0bffe17 ldw r2,-8(fp) + 1011464: 18800115 stw r2,4(r3) + pmem->OSMemNFree++; /* One more memory block in this partition */ + 1011468: e0bffd17 ldw r2,-12(fp) + 101146c: 10800417 ldw r2,16(r2) + 1011470: 10c00044 addi r3,r2,1 + 1011474: e0bffd17 ldw r2,-12(fp) + 1011478: 10c00415 stw r3,16(r2) + 101147c: e0bffc17 ldw r2,-16(fp) + 1011480: e0bff915 stw r2,-28(fp) + 1011484: e0bff917 ldw r2,-28(fp) + 1011488: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_NONE); /* Notify caller that memory block was released */ + 101148c: e03fff15 stw zero,-4(fp) + 1011490: e0bfff17 ldw r2,-4(fp) +} + 1011494: e037883a mov sp,fp + 1011498: df000017 ldw fp,0(sp) + 101149c: dec00104 addi sp,sp,4 + 10114a0: f800283a ret + +010114a4 : +********************************************************************************************************* +*/ + +#if OS_MEM_QUERY_EN > 0 +INT8U OSMemQuery (OS_MEM *pmem, OS_MEM_DATA *p_mem_data) +{ + 10114a4: defff904 addi sp,sp,-28 + 10114a8: df000615 stw fp,24(sp) + 10114ac: df000604 addi fp,sp,24 + 10114b0: e13ffd15 stw r4,-12(fp) + 10114b4: e17ffe15 stw r5,-8(fp) +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 10114b8: e03ffc15 stw zero,-16(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (pmem == (OS_MEM *)0) { /* Must point to a valid memory partition */ + 10114bc: e0bffd17 ldw r2,-12(fp) + 10114c0: 1004c03a cmpne r2,r2,zero + 10114c4: 1000031e bne r2,zero,10114d4 + return (OS_ERR_MEM_INVALID_PMEM); + 10114c8: 00801804 movi r2,96 + 10114cc: e0bfff15 stw r2,-4(fp) + 10114d0: 00002e06 br 101158c + } + if (p_mem_data == (OS_MEM_DATA *)0) { /* Must release a valid storage area for the data */ + 10114d4: e0bffe17 ldw r2,-8(fp) + 10114d8: 1004c03a cmpne r2,r2,zero + 10114dc: 1000031e bne r2,zero,10114ec + return (OS_ERR_MEM_INVALID_PDATA); + 10114e0: 00801844 movi r2,97 + 10114e4: e0bfff15 stw r2,-4(fp) + 10114e8: 00002806 br 101158c +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 10114ec: 0005303a rdctl r2,status + 10114f0: e0bffb15 stw r2,-20(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 10114f4: e0fffb17 ldw r3,-20(fp) + 10114f8: 00bfff84 movi r2,-2 + 10114fc: 1884703a and r2,r3,r2 + 1011500: 1001703a wrctl status,r2 + + return context; + 1011504: e0bffb17 ldw r2,-20(fp) + } +#endif + OS_ENTER_CRITICAL(); + 1011508: e0bffc15 stw r2,-16(fp) + p_mem_data->OSAddr = pmem->OSMemAddr; + 101150c: e0bffd17 ldw r2,-12(fp) + 1011510: 10c00017 ldw r3,0(r2) + 1011514: e0bffe17 ldw r2,-8(fp) + 1011518: 10c00015 stw r3,0(r2) + p_mem_data->OSFreeList = pmem->OSMemFreeList; + 101151c: e0bffd17 ldw r2,-12(fp) + 1011520: 10c00117 ldw r3,4(r2) + 1011524: e0bffe17 ldw r2,-8(fp) + 1011528: 10c00115 stw r3,4(r2) + p_mem_data->OSBlkSize = pmem->OSMemBlkSize; + 101152c: e0bffd17 ldw r2,-12(fp) + 1011530: 10c00217 ldw r3,8(r2) + 1011534: e0bffe17 ldw r2,-8(fp) + 1011538: 10c00215 stw r3,8(r2) + p_mem_data->OSNBlks = pmem->OSMemNBlks; + 101153c: e0bffd17 ldw r2,-12(fp) + 1011540: 10c00317 ldw r3,12(r2) + 1011544: e0bffe17 ldw r2,-8(fp) + 1011548: 10c00315 stw r3,12(r2) + p_mem_data->OSNFree = pmem->OSMemNFree; + 101154c: e0bffd17 ldw r2,-12(fp) + 1011550: 10c00417 ldw r3,16(r2) + 1011554: e0bffe17 ldw r2,-8(fp) + 1011558: 10c00415 stw r3,16(r2) + 101155c: e0bffc17 ldw r2,-16(fp) + 1011560: e0bffa15 stw r2,-24(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1011564: e0bffa17 ldw r2,-24(fp) + 1011568: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + p_mem_data->OSNUsed = p_mem_data->OSNBlks - p_mem_data->OSNFree; + 101156c: e0bffe17 ldw r2,-8(fp) + 1011570: 10c00317 ldw r3,12(r2) + 1011574: e0bffe17 ldw r2,-8(fp) + 1011578: 10800417 ldw r2,16(r2) + 101157c: 1887c83a sub r3,r3,r2 + 1011580: e0bffe17 ldw r2,-8(fp) + 1011584: 10c00515 stw r3,20(r2) + return (OS_ERR_NONE); + 1011588: e03fff15 stw zero,-4(fp) + 101158c: e0bfff17 ldw r2,-4(fp) +} + 1011590: e037883a mov sp,fp + 1011594: df000017 ldw fp,0(sp) + 1011598: dec00104 addi sp,sp,4 + 101159c: f800283a ret + +010115a0 : +* Note(s) : This function is INTERNAL to uC/OS-II and your application should not call it. +********************************************************************************************************* +*/ + +void OS_MemInit (void) +{ + 10115a0: defffc04 addi sp,sp,-16 + 10115a4: dfc00315 stw ra,12(sp) + 10115a8: df000215 stw fp,8(sp) + 10115ac: df000204 addi fp,sp,8 +#if OS_MAX_MEM_PART >= 2 + OS_MEM *pmem; + INT16U i; + + + OS_MemClr((INT8U *)&OSMemTbl[0], sizeof(OSMemTbl)); /* Clear the memory partition table */ + 10115b0: 010040b4 movhi r4,258 + 10115b4: 210e1104 addi r4,r4,14404 + 10115b8: 01430c04 movi r5,3120 + 10115bc: 100ebf80 call 100ebf8 + pmem = &OSMemTbl[0]; /* Point to memory control block (MCB) */ + 10115c0: 008040b4 movhi r2,258 + 10115c4: 108e1104 addi r2,r2,14404 + 10115c8: e0bfff15 stw r2,-4(fp) + for (i = 0; i < (OS_MAX_MEM_PART - 1); i++) { /* Init. list of free memory partitions */ + 10115cc: e03ffe0d sth zero,-8(fp) + 10115d0: 00001306 br 1011620 + pmem->OSMemFreeList = (void *)&OSMemTbl[i+1]; /* Chain list of free partitions */ + 10115d4: e0bffe0b ldhu r2,-8(fp) + 10115d8: 10800d24 muli r2,r2,52 + 10115dc: 1007883a mov r3,r2 + 10115e0: 008040b4 movhi r2,258 + 10115e4: 108e1e04 addi r2,r2,14456 + 10115e8: 1887883a add r3,r3,r2 + 10115ec: e0bfff17 ldw r2,-4(fp) + 10115f0: 10c00115 stw r3,4(r2) +#if OS_MEM_NAME_SIZE > 1 + pmem->OSMemName[0] = '?'; /* Unknown name */ + 10115f4: e0ffff17 ldw r3,-4(fp) + 10115f8: 00800fc4 movi r2,63 + 10115fc: 18800505 stb r2,20(r3) + pmem->OSMemName[1] = OS_ASCII_NUL; + 1011600: e0bfff17 ldw r2,-4(fp) + 1011604: 10000545 stb zero,21(r2) +#endif + pmem++; + 1011608: e0bfff17 ldw r2,-4(fp) + 101160c: 10800d04 addi r2,r2,52 + 1011610: e0bfff15 stw r2,-4(fp) + INT16U i; + + + OS_MemClr((INT8U *)&OSMemTbl[0], sizeof(OSMemTbl)); /* Clear the memory partition table */ + pmem = &OSMemTbl[0]; /* Point to memory control block (MCB) */ + for (i = 0; i < (OS_MAX_MEM_PART - 1); i++) { /* Init. list of free memory partitions */ + 1011614: e0bffe0b ldhu r2,-8(fp) + 1011618: 10800044 addi r2,r2,1 + 101161c: e0bffe0d sth r2,-8(fp) + 1011620: e0bffe0b ldhu r2,-8(fp) + 1011624: 10800ef0 cmpltui r2,r2,59 + 1011628: 103fea1e bne r2,zero,10115d4 + pmem->OSMemName[0] = '?'; /* Unknown name */ + pmem->OSMemName[1] = OS_ASCII_NUL; +#endif + pmem++; + } + pmem->OSMemFreeList = (void *)0; /* Initialize last node */ + 101162c: e0bfff17 ldw r2,-4(fp) + 1011630: 10000115 stw zero,4(r2) +#if OS_MEM_NAME_SIZE > 1 + pmem->OSMemName[0] = '?'; /* Unknown name */ + 1011634: e0ffff17 ldw r3,-4(fp) + 1011638: 00800fc4 movi r2,63 + 101163c: 18800505 stb r2,20(r3) + pmem->OSMemName[1] = OS_ASCII_NUL; + 1011640: e0bfff17 ldw r2,-4(fp) + 1011644: 10000545 stb zero,21(r2) +#endif + + OSMemFreeList = &OSMemTbl[0]; /* Point to beginning of free list */ + 1011648: 00c040b4 movhi r3,258 + 101164c: 18f31904 addi r3,r3,-13212 + 1011650: 008040b4 movhi r2,258 + 1011654: 108e1104 addi r2,r2,14404 + 1011658: 18800015 stw r2,0(r3) +#endif +} + 101165c: e037883a mov sp,fp + 1011660: dfc00117 ldw ra,4(sp) + 1011664: df000017 ldw fp,0(sp) + 1011668: dec00204 addi sp,sp,8 + 101166c: f800283a ret + +01011670 : +********************************************************************************************************* +*/ + +#if OS_Q_ACCEPT_EN > 0 +void *OSQAccept (OS_EVENT *pevent, INT8U *perr) +{ + 1011670: defff704 addi sp,sp,-36 + 1011674: df000815 stw fp,32(sp) + 1011678: df000804 addi fp,sp,32 + 101167c: e13ffd15 stw r4,-12(fp) + 1011680: e17ffe15 stw r5,-8(fp) + void *pmsg; + OS_Q *pq; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 1011684: e03ffa15 stw zero,-24(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + 1011688: e0bffe17 ldw r2,-8(fp) + 101168c: 1004c03a cmpne r2,r2,zero + 1011690: 1000021e bne r2,zero,101169c + return ((void *)0); + 1011694: e03fff15 stw zero,-4(fp) + 1011698: 00004506 br 10117b0 + } + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + 101169c: e0bffd17 ldw r2,-12(fp) + 10116a0: 1004c03a cmpne r2,r2,zero + 10116a4: 1000051e bne r2,zero,10116bc + *perr = OS_ERR_PEVENT_NULL; + 10116a8: e0fffe17 ldw r3,-8(fp) + 10116ac: 00800104 movi r2,4 + 10116b0: 18800005 stb r2,0(r3) + return ((void *)0); + 10116b4: e03fff15 stw zero,-4(fp) + 10116b8: 00003d06 br 10117b0 + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_Q) {/* Validate event block type */ + 10116bc: e0bffd17 ldw r2,-12(fp) + 10116c0: 10800003 ldbu r2,0(r2) + 10116c4: 10803fcc andi r2,r2,255 + 10116c8: 108000a0 cmpeqi r2,r2,2 + 10116cc: 1000051e bne r2,zero,10116e4 + *perr = OS_ERR_EVENT_TYPE; + 10116d0: e0fffe17 ldw r3,-8(fp) + 10116d4: 00800044 movi r2,1 + 10116d8: 18800005 stb r2,0(r3) + return ((void *)0); + 10116dc: e03fff15 stw zero,-4(fp) + 10116e0: 00003306 br 10117b0 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 10116e4: 0005303a rdctl r2,status + 10116e8: e0bff915 stw r2,-28(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 10116ec: e0fff917 ldw r3,-28(fp) + 10116f0: 00bfff84 movi r2,-2 + 10116f4: 1884703a and r2,r3,r2 + 10116f8: 1001703a wrctl status,r2 + + return context; + 10116fc: e0bff917 ldw r2,-28(fp) + } + OS_ENTER_CRITICAL(); + 1011700: e0bffa15 stw r2,-24(fp) + pq = (OS_Q *)pevent->OSEventPtr; /* Point at queue control block */ + 1011704: e0bffd17 ldw r2,-12(fp) + 1011708: 10800117 ldw r2,4(r2) + 101170c: e0bffb15 stw r2,-20(fp) + if (pq->OSQEntries > 0) { /* See if any messages in the queue */ + 1011710: e0bffb17 ldw r2,-20(fp) + 1011714: 1080058b ldhu r2,22(r2) + 1011718: 10bfffcc andi r2,r2,65535 + 101171c: 1005003a cmpeq r2,r2,zero + 1011720: 1000191e bne r2,zero,1011788 + pmsg = *pq->OSQOut++; /* Yes, extract oldest message from the queue */ + 1011724: e0bffb17 ldw r2,-20(fp) + 1011728: 10c00417 ldw r3,16(r2) + 101172c: 18800017 ldw r2,0(r3) + 1011730: e0bffc15 stw r2,-16(fp) + 1011734: 18c00104 addi r3,r3,4 + 1011738: e0bffb17 ldw r2,-20(fp) + 101173c: 10c00415 stw r3,16(r2) + pq->OSQEntries--; /* Update the number of entries in the queue */ + 1011740: e0bffb17 ldw r2,-20(fp) + 1011744: 1080058b ldhu r2,22(r2) + 1011748: 10bfffc4 addi r2,r2,-1 + 101174c: 1007883a mov r3,r2 + 1011750: e0bffb17 ldw r2,-20(fp) + 1011754: 10c0058d sth r3,22(r2) + if (pq->OSQOut == pq->OSQEnd) { /* Wrap OUT pointer if we are at the end of the queue */ + 1011758: e0bffb17 ldw r2,-20(fp) + 101175c: 10c00417 ldw r3,16(r2) + 1011760: e0bffb17 ldw r2,-20(fp) + 1011764: 10800217 ldw r2,8(r2) + 1011768: 1880041e bne r3,r2,101177c + pq->OSQOut = pq->OSQStart; + 101176c: e0bffb17 ldw r2,-20(fp) + 1011770: 10c00117 ldw r3,4(r2) + 1011774: e0bffb17 ldw r2,-20(fp) + 1011778: 10c00415 stw r3,16(r2) + } + *perr = OS_ERR_NONE; + 101177c: e0bffe17 ldw r2,-8(fp) + 1011780: 10000005 stb zero,0(r2) + 1011784: 00000406 br 1011798 + } else { + *perr = OS_ERR_Q_EMPTY; + 1011788: e0fffe17 ldw r3,-8(fp) + 101178c: 008007c4 movi r2,31 + 1011790: 18800005 stb r2,0(r3) + pmsg = (void *)0; /* Queue is empty */ + 1011794: e03ffc15 stw zero,-16(fp) + 1011798: e0bffa17 ldw r2,-24(fp) + 101179c: e0bff815 stw r2,-32(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 10117a0: e0bff817 ldw r2,-32(fp) + 10117a4: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); + return (pmsg); /* Return message received (or NULL) */ + 10117a8: e0bffc17 ldw r2,-16(fp) + 10117ac: e0bfff15 stw r2,-4(fp) + 10117b0: e0bfff17 ldw r2,-4(fp) +} + 10117b4: e037883a mov sp,fp + 10117b8: df000017 ldw fp,0(sp) + 10117bc: dec00104 addi sp,sp,4 + 10117c0: f800283a ret + +010117c4 : +* == (OS_EVENT *)0 if no event control blocks were available or an error was detected +********************************************************************************************************* +*/ + +OS_EVENT *OSQCreate (void **start, INT16U size) +{ + 10117c4: defff304 addi sp,sp,-52 + 10117c8: dfc00c15 stw ra,48(sp) + 10117cc: df000b15 stw fp,44(sp) + 10117d0: df000b04 addi fp,sp,44 + 10117d4: e13ffd15 stw r4,-12(fp) + 10117d8: e17ffe0d sth r5,-8(fp) + OS_EVENT *pevent; + OS_Q *pq; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 10117dc: e03ffa15 stw zero,-24(fp) +#endif + + + + if (OSIntNesting > 0) { /* See if called from ISR ... */ + 10117e0: 008040b4 movhi r2,258 + 10117e4: 10b31e04 addi r2,r2,-13192 + 10117e8: 10800003 ldbu r2,0(r2) + 10117ec: 10803fcc andi r2,r2,255 + 10117f0: 1005003a cmpeq r2,r2,zero + 10117f4: 1000021e bne r2,zero,1011800 + return ((OS_EVENT *)0); /* ... can't CREATE from an ISR */ + 10117f8: e03fff15 stw zero,-4(fp) + 10117fc: 00007006 br 10119c0 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1011800: 0005303a rdctl r2,status + 1011804: e0bff915 stw r2,-28(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1011808: e0fff917 ldw r3,-28(fp) + 101180c: 00bfff84 movi r2,-2 + 1011810: 1884703a and r2,r3,r2 + 1011814: 1001703a wrctl status,r2 + + return context; + 1011818: e0bff917 ldw r2,-28(fp) + } + OS_ENTER_CRITICAL(); + 101181c: e0bffa15 stw r2,-24(fp) + pevent = OSEventFreeList; /* Get next free event control block */ + 1011820: 008040b4 movhi r2,258 + 1011824: 10b31d04 addi r2,r2,-13196 + 1011828: 10800017 ldw r2,0(r2) + 101182c: e0bffc15 stw r2,-16(fp) + if (OSEventFreeList != (OS_EVENT *)0) { /* See if pool of free ECB pool was empty */ + 1011830: 008040b4 movhi r2,258 + 1011834: 10b31d04 addi r2,r2,-13196 + 1011838: 10800017 ldw r2,0(r2) + 101183c: 1005003a cmpeq r2,r2,zero + 1011840: 1000081e bne r2,zero,1011864 + OSEventFreeList = (OS_EVENT *)OSEventFreeList->OSEventPtr; + 1011844: 008040b4 movhi r2,258 + 1011848: 10b31d04 addi r2,r2,-13196 + 101184c: 10800017 ldw r2,0(r2) + 1011850: 10800117 ldw r2,4(r2) + 1011854: 1007883a mov r3,r2 + 1011858: 008040b4 movhi r2,258 + 101185c: 10b31d04 addi r2,r2,-13196 + 1011860: 10c00015 stw r3,0(r2) + 1011864: e0bffa17 ldw r2,-24(fp) + 1011868: e0bff815 stw r2,-32(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 101186c: e0bff817 ldw r2,-32(fp) + 1011870: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); + if (pevent != (OS_EVENT *)0) { /* See if we have an event control block */ + 1011874: e0bffc17 ldw r2,-16(fp) + 1011878: 1005003a cmpeq r2,r2,zero + 101187c: 10004e1e bne r2,zero,10119b8 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1011880: 0005303a rdctl r2,status + 1011884: e0bff715 stw r2,-36(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1011888: e0fff717 ldw r3,-36(fp) + 101188c: 00bfff84 movi r2,-2 + 1011890: 1884703a and r2,r3,r2 + 1011894: 1001703a wrctl status,r2 + + return context; + 1011898: e0bff717 ldw r2,-36(fp) + OS_ENTER_CRITICAL(); + 101189c: e0bffa15 stw r2,-24(fp) + pq = OSQFreeList; /* Get a free queue control block */ + 10118a0: 008040b4 movhi r2,258 + 10118a4: 10b31b04 addi r2,r2,-13204 + 10118a8: 10800017 ldw r2,0(r2) + 10118ac: e0bffb15 stw r2,-20(fp) + if (pq != (OS_Q *)0) { /* Were we able to get a queue control block ? */ + 10118b0: e0bffb17 ldw r2,-20(fp) + 10118b4: 1005003a cmpeq r2,r2,zero + 10118b8: 1000311e bne r2,zero,1011980 + OSQFreeList = OSQFreeList->OSQPtr; /* Yes, Adjust free list pointer to next free*/ + 10118bc: 008040b4 movhi r2,258 + 10118c0: 10b31b04 addi r2,r2,-13204 + 10118c4: 10800017 ldw r2,0(r2) + 10118c8: 10c00017 ldw r3,0(r2) + 10118cc: 008040b4 movhi r2,258 + 10118d0: 10b31b04 addi r2,r2,-13204 + 10118d4: 10c00015 stw r3,0(r2) + 10118d8: e0bffa17 ldw r2,-24(fp) + 10118dc: e0bff615 stw r2,-40(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 10118e0: e0bff617 ldw r2,-40(fp) + 10118e4: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + pq->OSQStart = start; /* Initialize the queue */ + 10118e8: e0fffb17 ldw r3,-20(fp) + 10118ec: e0bffd17 ldw r2,-12(fp) + 10118f0: 18800115 stw r2,4(r3) + pq->OSQEnd = &start[size]; + 10118f4: e0bffe0b ldhu r2,-8(fp) + 10118f8: 1085883a add r2,r2,r2 + 10118fc: 1085883a add r2,r2,r2 + 1011900: 1007883a mov r3,r2 + 1011904: e0bffd17 ldw r2,-12(fp) + 1011908: 1887883a add r3,r3,r2 + 101190c: e0bffb17 ldw r2,-20(fp) + 1011910: 10c00215 stw r3,8(r2) + pq->OSQIn = start; + 1011914: e0fffb17 ldw r3,-20(fp) + 1011918: e0bffd17 ldw r2,-12(fp) + 101191c: 18800315 stw r2,12(r3) + pq->OSQOut = start; + 1011920: e0fffb17 ldw r3,-20(fp) + 1011924: e0bffd17 ldw r2,-12(fp) + 1011928: 18800415 stw r2,16(r3) + pq->OSQSize = size; + 101192c: e0fffb17 ldw r3,-20(fp) + 1011930: e0bffe0b ldhu r2,-8(fp) + 1011934: 1880050d sth r2,20(r3) + pq->OSQEntries = 0; + 1011938: e0bffb17 ldw r2,-20(fp) + 101193c: 1000058d sth zero,22(r2) + pevent->OSEventType = OS_EVENT_TYPE_Q; + 1011940: e0fffc17 ldw r3,-16(fp) + 1011944: 00800084 movi r2,2 + 1011948: 18800005 stb r2,0(r3) + pevent->OSEventCnt = 0; + 101194c: e0bffc17 ldw r2,-16(fp) + 1011950: 1000020d sth zero,8(r2) + pevent->OSEventPtr = pq; + 1011954: e0fffc17 ldw r3,-16(fp) + 1011958: e0bffb17 ldw r2,-20(fp) + 101195c: 18800115 stw r2,4(r3) +#if OS_EVENT_NAME_SIZE > 1 + pevent->OSEventName[0] = '?'; /* Unknown name */ + 1011960: e0fffc17 ldw r3,-16(fp) + 1011964: 00800fc4 movi r2,63 + 1011968: 18800385 stb r2,14(r3) + pevent->OSEventName[1] = OS_ASCII_NUL; + 101196c: e0bffc17 ldw r2,-16(fp) + 1011970: 100003c5 stb zero,15(r2) +#endif + OS_EventWaitListInit(pevent); /* Initalize the wait list */ + 1011974: e13ffc17 ldw r4,-16(fp) + 1011978: 100e82c0 call 100e82c + 101197c: 00000e06 br 10119b8 + } else { + pevent->OSEventPtr = (void *)OSEventFreeList; /* No, Return event control block on error */ + 1011980: 008040b4 movhi r2,258 + 1011984: 10b31d04 addi r2,r2,-13196 + 1011988: 10c00017 ldw r3,0(r2) + 101198c: e0bffc17 ldw r2,-16(fp) + 1011990: 10c00115 stw r3,4(r2) + OSEventFreeList = pevent; + 1011994: 00c040b4 movhi r3,258 + 1011998: 18f31d04 addi r3,r3,-13196 + 101199c: e0bffc17 ldw r2,-16(fp) + 10119a0: 18800015 stw r2,0(r3) + 10119a4: e0bffa17 ldw r2,-24(fp) + 10119a8: e0bff515 stw r2,-44(fp) + 10119ac: e0bff517 ldw r2,-44(fp) + 10119b0: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + pevent = (OS_EVENT *)0; + 10119b4: e03ffc15 stw zero,-16(fp) + } + } + return (pevent); + 10119b8: e0bffc17 ldw r2,-16(fp) + 10119bc: e0bfff15 stw r2,-4(fp) + 10119c0: e0bfff17 ldw r2,-4(fp) +} + 10119c4: e037883a mov sp,fp + 10119c8: dfc00117 ldw ra,4(sp) + 10119cc: df000017 ldw fp,0(sp) + 10119d0: dec00204 addi sp,sp,8 + 10119d4: f800283a ret + +010119d8 : +********************************************************************************************************* +*/ + +#if OS_Q_DEL_EN > 0 +OS_EVENT *OSQDel (OS_EVENT *pevent, INT8U opt, INT8U *perr) +{ + 10119d8: defff004 addi sp,sp,-64 + 10119dc: dfc00f15 stw ra,60(sp) + 10119e0: df000e15 stw fp,56(sp) + 10119e4: df000e04 addi fp,sp,56 + 10119e8: e13ffb15 stw r4,-20(fp) + 10119ec: e1bffd15 stw r6,-12(fp) + 10119f0: e17ffc05 stb r5,-16(fp) + BOOLEAN tasks_waiting; + OS_EVENT *pevent_return; + OS_Q *pq; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 10119f4: e03ff715 stw zero,-36(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + 10119f8: e0bffd17 ldw r2,-12(fp) + 10119fc: 1004c03a cmpne r2,r2,zero + 1011a00: 1000031e bne r2,zero,1011a10 + return (pevent); + 1011a04: e0bffb17 ldw r2,-20(fp) + 1011a08: e0bfff15 stw r2,-4(fp) + 1011a0c: 0000ac06 br 1011cc0 + } + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + 1011a10: e0bffb17 ldw r2,-20(fp) + 1011a14: 1004c03a cmpne r2,r2,zero + 1011a18: 1000061e bne r2,zero,1011a34 + *perr = OS_ERR_PEVENT_NULL; + 1011a1c: e0fffd17 ldw r3,-12(fp) + 1011a20: 00800104 movi r2,4 + 1011a24: 18800005 stb r2,0(r3) + return (pevent); + 1011a28: e0fffb17 ldw r3,-20(fp) + 1011a2c: e0ffff15 stw r3,-4(fp) + 1011a30: 0000a306 br 1011cc0 + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_Q) { /* Validate event block type */ + 1011a34: e0bffb17 ldw r2,-20(fp) + 1011a38: 10800003 ldbu r2,0(r2) + 1011a3c: 10803fcc andi r2,r2,255 + 1011a40: 108000a0 cmpeqi r2,r2,2 + 1011a44: 1000061e bne r2,zero,1011a60 + *perr = OS_ERR_EVENT_TYPE; + 1011a48: e0fffd17 ldw r3,-12(fp) + 1011a4c: 00800044 movi r2,1 + 1011a50: 18800005 stb r2,0(r3) + return (pevent); + 1011a54: e0bffb17 ldw r2,-20(fp) + 1011a58: e0bfff15 stw r2,-4(fp) + 1011a5c: 00009806 br 1011cc0 + } + if (OSIntNesting > 0) { /* See if called from ISR ... */ + 1011a60: 008040b4 movhi r2,258 + 1011a64: 10b31e04 addi r2,r2,-13192 + 1011a68: 10800003 ldbu r2,0(r2) + 1011a6c: 10803fcc andi r2,r2,255 + 1011a70: 1005003a cmpeq r2,r2,zero + 1011a74: 1000061e bne r2,zero,1011a90 + *perr = OS_ERR_DEL_ISR; /* ... can't DELETE from an ISR */ + 1011a78: e0fffd17 ldw r3,-12(fp) + 1011a7c: 008003c4 movi r2,15 + 1011a80: 18800005 stb r2,0(r3) + return (pevent); + 1011a84: e0fffb17 ldw r3,-20(fp) + 1011a88: e0ffff15 stw r3,-4(fp) + 1011a8c: 00008c06 br 1011cc0 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1011a90: 0005303a rdctl r2,status + 1011a94: e0bff615 stw r2,-40(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1011a98: e0fff617 ldw r3,-40(fp) + 1011a9c: 00bfff84 movi r2,-2 + 1011aa0: 1884703a and r2,r3,r2 + 1011aa4: 1001703a wrctl status,r2 + + return context; + 1011aa8: e0bff617 ldw r2,-40(fp) + } + OS_ENTER_CRITICAL(); + 1011aac: e0bff715 stw r2,-36(fp) + if (pevent->OSEventGrp != 0) { /* See if any tasks waiting on queue */ + 1011ab0: e0bffb17 ldw r2,-20(fp) + 1011ab4: 10800283 ldbu r2,10(r2) + 1011ab8: 10803fcc andi r2,r2,255 + 1011abc: 1005003a cmpeq r2,r2,zero + 1011ac0: 1000031e bne r2,zero,1011ad0 + tasks_waiting = OS_TRUE; /* Yes */ + 1011ac4: 00800044 movi r2,1 + 1011ac8: e0bffa05 stb r2,-24(fp) + 1011acc: 00000106 br 1011ad4 + } else { + tasks_waiting = OS_FALSE; /* No */ + 1011ad0: e03ffa05 stb zero,-24(fp) + } + switch (opt) { + 1011ad4: e0bffc03 ldbu r2,-16(fp) + 1011ad8: e0bffe15 stw r2,-8(fp) + 1011adc: e0fffe17 ldw r3,-8(fp) + 1011ae0: 1805003a cmpeq r2,r3,zero + 1011ae4: 1000041e bne r2,zero,1011af8 + 1011ae8: e0fffe17 ldw r3,-8(fp) + 1011aec: 18800060 cmpeqi r2,r3,1 + 1011af0: 1000391e bne r2,zero,1011bd8 + 1011af4: 00006706 br 1011c94 + case OS_DEL_NO_PEND: /* Delete queue only if no task waiting */ + if (tasks_waiting == OS_FALSE) { + 1011af8: e0bffa03 ldbu r2,-24(fp) + 1011afc: 1004c03a cmpne r2,r2,zero + 1011b00: 1000261e bne r2,zero,1011b9c +#if OS_EVENT_NAME_SIZE > 1 + pevent->OSEventName[0] = '?'; /* Unknown name */ + 1011b04: e0fffb17 ldw r3,-20(fp) + 1011b08: 00800fc4 movi r2,63 + 1011b0c: 18800385 stb r2,14(r3) + pevent->OSEventName[1] = OS_ASCII_NUL; + 1011b10: e0bffb17 ldw r2,-20(fp) + 1011b14: 100003c5 stb zero,15(r2) +#endif + pq = (OS_Q *)pevent->OSEventPtr; /* Return OS_Q to free list */ + 1011b18: e0bffb17 ldw r2,-20(fp) + 1011b1c: 10800117 ldw r2,4(r2) + 1011b20: e0bff815 stw r2,-32(fp) + pq->OSQPtr = OSQFreeList; + 1011b24: 008040b4 movhi r2,258 + 1011b28: 10b31b04 addi r2,r2,-13204 + 1011b2c: 10c00017 ldw r3,0(r2) + 1011b30: e0bff817 ldw r2,-32(fp) + 1011b34: 10c00015 stw r3,0(r2) + OSQFreeList = pq; + 1011b38: 00c040b4 movhi r3,258 + 1011b3c: 18f31b04 addi r3,r3,-13204 + 1011b40: e0bff817 ldw r2,-32(fp) + 1011b44: 18800015 stw r2,0(r3) + pevent->OSEventType = OS_EVENT_TYPE_UNUSED; + 1011b48: e0bffb17 ldw r2,-20(fp) + 1011b4c: 10000005 stb zero,0(r2) + pevent->OSEventPtr = OSEventFreeList; /* Return Event Control Block to free list */ + 1011b50: 008040b4 movhi r2,258 + 1011b54: 10b31d04 addi r2,r2,-13196 + 1011b58: 10c00017 ldw r3,0(r2) + 1011b5c: e0bffb17 ldw r2,-20(fp) + 1011b60: 10c00115 stw r3,4(r2) + pevent->OSEventCnt = 0; + 1011b64: e0bffb17 ldw r2,-20(fp) + 1011b68: 1000020d sth zero,8(r2) + OSEventFreeList = pevent; /* Get next free event control block */ + 1011b6c: 00c040b4 movhi r3,258 + 1011b70: 18f31d04 addi r3,r3,-13196 + 1011b74: e0bffb17 ldw r2,-20(fp) + 1011b78: 18800015 stw r2,0(r3) + 1011b7c: e0bff717 ldw r2,-36(fp) + 1011b80: e0bff515 stw r2,-44(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1011b84: e0bff517 ldw r2,-44(fp) + 1011b88: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + 1011b8c: e0bffd17 ldw r2,-12(fp) + 1011b90: 10000005 stb zero,0(r2) + pevent_return = (OS_EVENT *)0; /* Queue has been deleted */ + 1011b94: e03ff915 stw zero,-28(fp) + 1011b98: 00004706 br 1011cb8 + 1011b9c: e0bff717 ldw r2,-36(fp) + 1011ba0: e0bff415 stw r2,-48(fp) + 1011ba4: e0bff417 ldw r2,-48(fp) + 1011ba8: 1001703a wrctl status,r2 + } else { + OS_EXIT_CRITICAL(); + *perr = OS_ERR_TASK_WAITING; + 1011bac: e0fffd17 ldw r3,-12(fp) + 1011bb0: 00801244 movi r2,73 + 1011bb4: 18800005 stb r2,0(r3) + pevent_return = pevent; + 1011bb8: e0bffb17 ldw r2,-20(fp) + 1011bbc: e0bff915 stw r2,-28(fp) + } + break; + 1011bc0: 00003d06 br 1011cb8 + + case OS_DEL_ALWAYS: /* Always delete the queue */ + while (pevent->OSEventGrp != 0) { /* Ready ALL tasks waiting for queue */ + (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_Q, OS_STAT_PEND_OK); + 1011bc4: e13ffb17 ldw r4,-20(fp) + 1011bc8: 000b883a mov r5,zero + 1011bcc: 01800104 movi r6,4 + 1011bd0: 000f883a mov r7,zero + 1011bd4: 100e2780 call 100e278 + pevent_return = pevent; + } + break; + + case OS_DEL_ALWAYS: /* Always delete the queue */ + while (pevent->OSEventGrp != 0) { /* Ready ALL tasks waiting for queue */ + 1011bd8: e0bffb17 ldw r2,-20(fp) + 1011bdc: 10800283 ldbu r2,10(r2) + 1011be0: 10803fcc andi r2,r2,255 + 1011be4: 1004c03a cmpne r2,r2,zero + 1011be8: 103ff61e bne r2,zero,1011bc4 + (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_Q, OS_STAT_PEND_OK); + } +#if OS_EVENT_NAME_SIZE > 1 + pevent->OSEventName[0] = '?'; /* Unknown name */ + 1011bec: e0fffb17 ldw r3,-20(fp) + 1011bf0: 00800fc4 movi r2,63 + 1011bf4: 18800385 stb r2,14(r3) + pevent->OSEventName[1] = OS_ASCII_NUL; + 1011bf8: e0bffb17 ldw r2,-20(fp) + 1011bfc: 100003c5 stb zero,15(r2) +#endif + pq = (OS_Q *)pevent->OSEventPtr; /* Return OS_Q to free list */ + 1011c00: e0bffb17 ldw r2,-20(fp) + 1011c04: 10800117 ldw r2,4(r2) + 1011c08: e0bff815 stw r2,-32(fp) + pq->OSQPtr = OSQFreeList; + 1011c0c: 008040b4 movhi r2,258 + 1011c10: 10b31b04 addi r2,r2,-13204 + 1011c14: 10c00017 ldw r3,0(r2) + 1011c18: e0bff817 ldw r2,-32(fp) + 1011c1c: 10c00015 stw r3,0(r2) + OSQFreeList = pq; + 1011c20: 00c040b4 movhi r3,258 + 1011c24: 18f31b04 addi r3,r3,-13204 + 1011c28: e0bff817 ldw r2,-32(fp) + 1011c2c: 18800015 stw r2,0(r3) + pevent->OSEventType = OS_EVENT_TYPE_UNUSED; + 1011c30: e0bffb17 ldw r2,-20(fp) + 1011c34: 10000005 stb zero,0(r2) + pevent->OSEventPtr = OSEventFreeList; /* Return Event Control Block to free list */ + 1011c38: 008040b4 movhi r2,258 + 1011c3c: 10b31d04 addi r2,r2,-13196 + 1011c40: 10c00017 ldw r3,0(r2) + 1011c44: e0bffb17 ldw r2,-20(fp) + 1011c48: 10c00115 stw r3,4(r2) + pevent->OSEventCnt = 0; + 1011c4c: e0bffb17 ldw r2,-20(fp) + 1011c50: 1000020d sth zero,8(r2) + OSEventFreeList = pevent; /* Get next free event control block */ + 1011c54: 00c040b4 movhi r3,258 + 1011c58: 18f31d04 addi r3,r3,-13196 + 1011c5c: e0bffb17 ldw r2,-20(fp) + 1011c60: 18800015 stw r2,0(r3) + 1011c64: e0bff717 ldw r2,-36(fp) + 1011c68: e0bff315 stw r2,-52(fp) + 1011c6c: e0bff317 ldw r2,-52(fp) + 1011c70: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + if (tasks_waiting == OS_TRUE) { /* Reschedule only if task(s) were waiting */ + 1011c74: e0bffa03 ldbu r2,-24(fp) + 1011c78: 10800058 cmpnei r2,r2,1 + 1011c7c: 1000011e bne r2,zero,1011c84 + OS_Sched(); /* Find highest priority task ready to run */ + 1011c80: 100ecb80 call 100ecb8 + } + *perr = OS_ERR_NONE; + 1011c84: e0bffd17 ldw r2,-12(fp) + 1011c88: 10000005 stb zero,0(r2) + pevent_return = (OS_EVENT *)0; /* Queue has been deleted */ + 1011c8c: e03ff915 stw zero,-28(fp) + break; + 1011c90: 00000906 br 1011cb8 + 1011c94: e0bff717 ldw r2,-36(fp) + 1011c98: e0bff215 stw r2,-56(fp) + 1011c9c: e0bff217 ldw r2,-56(fp) + 1011ca0: 1001703a wrctl status,r2 + + default: + OS_EXIT_CRITICAL(); + *perr = OS_ERR_INVALID_OPT; + 1011ca4: e0fffd17 ldw r3,-12(fp) + 1011ca8: 008001c4 movi r2,7 + 1011cac: 18800005 stb r2,0(r3) + pevent_return = pevent; + 1011cb0: e0bffb17 ldw r2,-20(fp) + 1011cb4: e0bff915 stw r2,-28(fp) + break; + } + return (pevent_return); + 1011cb8: e0bff917 ldw r2,-28(fp) + 1011cbc: e0bfff15 stw r2,-4(fp) + 1011cc0: e0bfff17 ldw r2,-4(fp) +} + 1011cc4: e037883a mov sp,fp + 1011cc8: dfc00117 ldw ra,4(sp) + 1011ccc: df000017 ldw fp,0(sp) + 1011cd0: dec00204 addi sp,sp,8 + 1011cd4: f800283a ret + +01011cd8 : +********************************************************************************************************* +*/ + +#if OS_Q_FLUSH_EN > 0 +INT8U OSQFlush (OS_EVENT *pevent) +{ + 1011cd8: defff904 addi sp,sp,-28 + 1011cdc: df000615 stw fp,24(sp) + 1011ce0: df000604 addi fp,sp,24 + 1011ce4: e13ffe15 stw r4,-8(fp) + OS_Q *pq; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 1011ce8: e03ffc15 stw zero,-16(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + 1011cec: e0bffe17 ldw r2,-8(fp) + 1011cf0: 1004c03a cmpne r2,r2,zero + 1011cf4: 1000031e bne r2,zero,1011d04 + return (OS_ERR_PEVENT_NULL); + 1011cf8: 00800104 movi r2,4 + 1011cfc: e0bfff15 stw r2,-4(fp) + 1011d00: 00002206 br 1011d8c + } + if (pevent->OSEventType != OS_EVENT_TYPE_Q) { /* Validate event block type */ + 1011d04: e0bffe17 ldw r2,-8(fp) + 1011d08: 10800003 ldbu r2,0(r2) + 1011d0c: 10803fcc andi r2,r2,255 + 1011d10: 108000a0 cmpeqi r2,r2,2 + 1011d14: 1000031e bne r2,zero,1011d24 + return (OS_ERR_EVENT_TYPE); + 1011d18: 00800044 movi r2,1 + 1011d1c: e0bfff15 stw r2,-4(fp) + 1011d20: 00001a06 br 1011d8c +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1011d24: 0005303a rdctl r2,status + 1011d28: e0bffb15 stw r2,-20(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1011d2c: e0fffb17 ldw r3,-20(fp) + 1011d30: 00bfff84 movi r2,-2 + 1011d34: 1884703a and r2,r3,r2 + 1011d38: 1001703a wrctl status,r2 + + return context; + 1011d3c: e0bffb17 ldw r2,-20(fp) + } +#endif + OS_ENTER_CRITICAL(); + 1011d40: e0bffc15 stw r2,-16(fp) + pq = (OS_Q *)pevent->OSEventPtr; /* Point to queue storage structure */ + 1011d44: e0bffe17 ldw r2,-8(fp) + 1011d48: 10800117 ldw r2,4(r2) + 1011d4c: e0bffd15 stw r2,-12(fp) + pq->OSQIn = pq->OSQStart; + 1011d50: e0bffd17 ldw r2,-12(fp) + 1011d54: 10c00117 ldw r3,4(r2) + 1011d58: e0bffd17 ldw r2,-12(fp) + 1011d5c: 10c00315 stw r3,12(r2) + pq->OSQOut = pq->OSQStart; + 1011d60: e0bffd17 ldw r2,-12(fp) + 1011d64: 10c00117 ldw r3,4(r2) + 1011d68: e0bffd17 ldw r2,-12(fp) + 1011d6c: 10c00415 stw r3,16(r2) + pq->OSQEntries = 0; + 1011d70: e0bffd17 ldw r2,-12(fp) + 1011d74: 1000058d sth zero,22(r2) + 1011d78: e0bffc17 ldw r2,-16(fp) + 1011d7c: e0bffa15 stw r2,-24(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1011d80: e0bffa17 ldw r2,-24(fp) + 1011d84: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_NONE); + 1011d88: e03fff15 stw zero,-4(fp) + 1011d8c: e0bfff17 ldw r2,-4(fp) +} + 1011d90: e037883a mov sp,fp + 1011d94: df000017 ldw fp,0(sp) + 1011d98: dec00104 addi sp,sp,4 + 1011d9c: f800283a ret + +01011da0 : +* Note(s) : As of V2.60, this function allows you to receive NULL pointer messages. +********************************************************************************************************* +*/ + +void *OSQPend (OS_EVENT *pevent, INT16U timeout, INT8U *perr) +{ + 1011da0: defff104 addi sp,sp,-60 + 1011da4: dfc00e15 stw ra,56(sp) + 1011da8: df000d15 stw fp,52(sp) + 1011dac: df000d04 addi fp,sp,52 + 1011db0: e13ffb15 stw r4,-20(fp) + 1011db4: e1bffd15 stw r6,-12(fp) + 1011db8: e17ffc0d sth r5,-16(fp) + void *pmsg; + OS_Q *pq; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 1011dbc: e03ff815 stw zero,-32(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + 1011dc0: e0bffd17 ldw r2,-12(fp) + 1011dc4: 1004c03a cmpne r2,r2,zero + 1011dc8: 1000021e bne r2,zero,1011dd4 + return ((void *)0); + 1011dcc: e03fff15 stw zero,-4(fp) + 1011dd0: 0000b506 br 10120a8 + } + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + 1011dd4: e0bffb17 ldw r2,-20(fp) + 1011dd8: 1004c03a cmpne r2,r2,zero + 1011ddc: 1000051e bne r2,zero,1011df4 + *perr = OS_ERR_PEVENT_NULL; + 1011de0: e0fffd17 ldw r3,-12(fp) + 1011de4: 00800104 movi r2,4 + 1011de8: 18800005 stb r2,0(r3) + return ((void *)0); + 1011dec: e03fff15 stw zero,-4(fp) + 1011df0: 0000ad06 br 10120a8 + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_Q) {/* Validate event block type */ + 1011df4: e0bffb17 ldw r2,-20(fp) + 1011df8: 10800003 ldbu r2,0(r2) + 1011dfc: 10803fcc andi r2,r2,255 + 1011e00: 108000a0 cmpeqi r2,r2,2 + 1011e04: 1000051e bne r2,zero,1011e1c + *perr = OS_ERR_EVENT_TYPE; + 1011e08: e0fffd17 ldw r3,-12(fp) + 1011e0c: 00800044 movi r2,1 + 1011e10: 18800005 stb r2,0(r3) + return ((void *)0); + 1011e14: e03fff15 stw zero,-4(fp) + 1011e18: 0000a306 br 10120a8 + } + if (OSIntNesting > 0) { /* See if called from ISR ... */ + 1011e1c: 008040b4 movhi r2,258 + 1011e20: 10b31e04 addi r2,r2,-13192 + 1011e24: 10800003 ldbu r2,0(r2) + 1011e28: 10803fcc andi r2,r2,255 + 1011e2c: 1005003a cmpeq r2,r2,zero + 1011e30: 1000051e bne r2,zero,1011e48 + *perr = OS_ERR_PEND_ISR; /* ... can't PEND from an ISR */ + 1011e34: e0fffd17 ldw r3,-12(fp) + 1011e38: 00800084 movi r2,2 + 1011e3c: 18800005 stb r2,0(r3) + return ((void *)0); + 1011e40: e03fff15 stw zero,-4(fp) + 1011e44: 00009806 br 10120a8 + } + if (OSLockNesting > 0) { /* See if called with scheduler locked ... */ + 1011e48: 008040b4 movhi r2,258 + 1011e4c: 10b31004 addi r2,r2,-13248 + 1011e50: 10800003 ldbu r2,0(r2) + 1011e54: 10803fcc andi r2,r2,255 + 1011e58: 1005003a cmpeq r2,r2,zero + 1011e5c: 1000051e bne r2,zero,1011e74 + *perr = OS_ERR_PEND_LOCKED; /* ... can't PEND when locked */ + 1011e60: e0fffd17 ldw r3,-12(fp) + 1011e64: 00800344 movi r2,13 + 1011e68: 18800005 stb r2,0(r3) + return ((void *)0); + 1011e6c: e03fff15 stw zero,-4(fp) + 1011e70: 00008d06 br 10120a8 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1011e74: 0005303a rdctl r2,status + 1011e78: e0bff715 stw r2,-36(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1011e7c: e0fff717 ldw r3,-36(fp) + 1011e80: 00bfff84 movi r2,-2 + 1011e84: 1884703a and r2,r3,r2 + 1011e88: 1001703a wrctl status,r2 + + return context; + 1011e8c: e0bff717 ldw r2,-36(fp) + } + OS_ENTER_CRITICAL(); + 1011e90: e0bff815 stw r2,-32(fp) + pq = (OS_Q *)pevent->OSEventPtr; /* Point at queue control block */ + 1011e94: e0bffb17 ldw r2,-20(fp) + 1011e98: 10800117 ldw r2,4(r2) + 1011e9c: e0bff915 stw r2,-28(fp) + if (pq->OSQEntries > 0) { /* See if any messages in the queue */ + 1011ea0: e0bff917 ldw r2,-28(fp) + 1011ea4: 1080058b ldhu r2,22(r2) + 1011ea8: 10bfffcc andi r2,r2,65535 + 1011eac: 1005003a cmpeq r2,r2,zero + 1011eb0: 10001f1e bne r2,zero,1011f30 + pmsg = *pq->OSQOut++; /* Yes, extract oldest message from the queue */ + 1011eb4: e0bff917 ldw r2,-28(fp) + 1011eb8: 10c00417 ldw r3,16(r2) + 1011ebc: 18800017 ldw r2,0(r3) + 1011ec0: e0bffa15 stw r2,-24(fp) + 1011ec4: 18c00104 addi r3,r3,4 + 1011ec8: e0bff917 ldw r2,-28(fp) + 1011ecc: 10c00415 stw r3,16(r2) + pq->OSQEntries--; /* Update the number of entries in the queue */ + 1011ed0: e0bff917 ldw r2,-28(fp) + 1011ed4: 1080058b ldhu r2,22(r2) + 1011ed8: 10bfffc4 addi r2,r2,-1 + 1011edc: 1007883a mov r3,r2 + 1011ee0: e0bff917 ldw r2,-28(fp) + 1011ee4: 10c0058d sth r3,22(r2) + if (pq->OSQOut == pq->OSQEnd) { /* Wrap OUT pointer if we are at the end of the queue */ + 1011ee8: e0bff917 ldw r2,-28(fp) + 1011eec: 10c00417 ldw r3,16(r2) + 1011ef0: e0bff917 ldw r2,-28(fp) + 1011ef4: 10800217 ldw r2,8(r2) + 1011ef8: 1880041e bne r3,r2,1011f0c + pq->OSQOut = pq->OSQStart; + 1011efc: e0bff917 ldw r2,-28(fp) + 1011f00: 10c00117 ldw r3,4(r2) + 1011f04: e0bff917 ldw r2,-28(fp) + 1011f08: 10c00415 stw r3,16(r2) + 1011f0c: e0bff817 ldw r2,-32(fp) + 1011f10: e0bff615 stw r2,-40(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1011f14: e0bff617 ldw r2,-40(fp) + 1011f18: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + 1011f1c: e0bffd17 ldw r2,-12(fp) + 1011f20: 10000005 stb zero,0(r2) + return (pmsg); /* Return message received */ + 1011f24: e0bffa17 ldw r2,-24(fp) + 1011f28: e0bfff15 stw r2,-4(fp) + 1011f2c: 00005e06 br 10120a8 + } + OSTCBCur->OSTCBStat |= OS_STAT_Q; /* Task will have to pend for a message to be posted */ + 1011f30: 008040b4 movhi r2,258 + 1011f34: 10b31f04 addi r2,r2,-13188 + 1011f38: 10c00017 ldw r3,0(r2) + 1011f3c: 008040b4 movhi r2,258 + 1011f40: 10b31f04 addi r2,r2,-13188 + 1011f44: 10800017 ldw r2,0(r2) + 1011f48: 10800c03 ldbu r2,48(r2) + 1011f4c: 10800114 ori r2,r2,4 + 1011f50: 18800c05 stb r2,48(r3) + OSTCBCur->OSTCBStatPend = OS_STAT_PEND_OK; + 1011f54: 008040b4 movhi r2,258 + 1011f58: 10b31f04 addi r2,r2,-13188 + 1011f5c: 10800017 ldw r2,0(r2) + 1011f60: 10000c45 stb zero,49(r2) + OSTCBCur->OSTCBDly = timeout; /* Load timeout into TCB */ + 1011f64: 008040b4 movhi r2,258 + 1011f68: 10b31f04 addi r2,r2,-13188 + 1011f6c: 10c00017 ldw r3,0(r2) + 1011f70: e0bffc0b ldhu r2,-16(fp) + 1011f74: 18800b8d sth r2,46(r3) + OS_EventTaskWait(pevent); /* Suspend task until event or timeout occurs */ + 1011f78: e13ffb17 ldw r4,-20(fp) + 1011f7c: 100e40c0 call 100e40c + 1011f80: e0bff817 ldw r2,-32(fp) + 1011f84: e0bff515 stw r2,-44(fp) + 1011f88: e0bff517 ldw r2,-44(fp) + 1011f8c: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + OS_Sched(); /* Find next highest priority task ready to run */ + 1011f90: 100ecb80 call 100ecb8 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1011f94: 0005303a rdctl r2,status + 1011f98: e0bff415 stw r2,-48(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1011f9c: e0fff417 ldw r3,-48(fp) + 1011fa0: 00bfff84 movi r2,-2 + 1011fa4: 1884703a and r2,r3,r2 + 1011fa8: 1001703a wrctl status,r2 + + return context; + 1011fac: e0bff417 ldw r2,-48(fp) + OS_ENTER_CRITICAL(); + 1011fb0: e0bff815 stw r2,-32(fp) + switch (OSTCBCur->OSTCBStatPend) { /* See if we timed-out or aborted */ + 1011fb4: 008040b4 movhi r2,258 + 1011fb8: 10b31f04 addi r2,r2,-13188 + 1011fbc: 10800017 ldw r2,0(r2) + 1011fc0: 10800c43 ldbu r2,49(r2) + 1011fc4: 10803fcc andi r2,r2,255 + 1011fc8: e0bffe15 stw r2,-8(fp) + 1011fcc: e0fffe17 ldw r3,-8(fp) + 1011fd0: 1805003a cmpeq r2,r3,zero + 1011fd4: 1000041e bne r2,zero,1011fe8 + 1011fd8: e0fffe17 ldw r3,-8(fp) + 1011fdc: 188000a0 cmpeqi r2,r3,2 + 1011fe0: 1000091e bne r2,zero,1012008 + 1011fe4: 00000d06 br 101201c + case OS_STAT_PEND_OK: /* Extract message from TCB (Put there by QPost) */ + pmsg = OSTCBCur->OSTCBMsg; + 1011fe8: 008040b4 movhi r2,258 + 1011fec: 10b31f04 addi r2,r2,-13188 + 1011ff0: 10800017 ldw r2,0(r2) + 1011ff4: 10800917 ldw r2,36(r2) + 1011ff8: e0bffa15 stw r2,-24(fp) + *perr = OS_ERR_NONE; + 1011ffc: e0bffd17 ldw r2,-12(fp) + 1012000: 10000005 stb zero,0(r2) + break; + 1012004: 00000e06 br 1012040 + + case OS_STAT_PEND_ABORT: + pmsg = (void *)0; + 1012008: e03ffa15 stw zero,-24(fp) + *perr = OS_ERR_PEND_ABORT; /* Indicate that we aborted */ + 101200c: e0fffd17 ldw r3,-12(fp) + 1012010: 00800384 movi r2,14 + 1012014: 18800005 stb r2,0(r3) + break; + 1012018: 00000906 br 1012040 + + case OS_STAT_PEND_TO: + default: + OS_EventTaskRemove(OSTCBCur, pevent); + 101201c: 008040b4 movhi r2,258 + 1012020: 10b31f04 addi r2,r2,-13188 + 1012024: 11000017 ldw r4,0(r2) + 1012028: e17ffb17 ldw r5,-20(fp) + 101202c: 100e6700 call 100e670 + pmsg = (void *)0; + 1012030: e03ffa15 stw zero,-24(fp) + *perr = OS_ERR_TIMEOUT; /* Indicate that we didn't get event within TO */ + 1012034: e0fffd17 ldw r3,-12(fp) + 1012038: 00800284 movi r2,10 + 101203c: 18800005 stb r2,0(r3) + break; + } + OSTCBCur->OSTCBStat = OS_STAT_RDY; /* Set task status to ready */ + 1012040: 008040b4 movhi r2,258 + 1012044: 10b31f04 addi r2,r2,-13188 + 1012048: 10800017 ldw r2,0(r2) + 101204c: 10000c05 stb zero,48(r2) + OSTCBCur->OSTCBStatPend = OS_STAT_PEND_OK; /* Clear pend status */ + 1012050: 008040b4 movhi r2,258 + 1012054: 10b31f04 addi r2,r2,-13188 + 1012058: 10800017 ldw r2,0(r2) + 101205c: 10000c45 stb zero,49(r2) + OSTCBCur->OSTCBEventPtr = (OS_EVENT *)0; /* Clear event pointers */ + 1012060: 008040b4 movhi r2,258 + 1012064: 10b31f04 addi r2,r2,-13188 + 1012068: 10800017 ldw r2,0(r2) + 101206c: 10000715 stw zero,28(r2) +#if (OS_EVENT_MULTI_EN > 0) + OSTCBCur->OSTCBEventMultiPtr = (OS_EVENT **)0; + 1012070: 008040b4 movhi r2,258 + 1012074: 10b31f04 addi r2,r2,-13188 + 1012078: 10800017 ldw r2,0(r2) + 101207c: 10000815 stw zero,32(r2) +#endif + OSTCBCur->OSTCBMsg = (void *)0; /* Clear received message */ + 1012080: 008040b4 movhi r2,258 + 1012084: 10b31f04 addi r2,r2,-13188 + 1012088: 10800017 ldw r2,0(r2) + 101208c: 10000915 stw zero,36(r2) + 1012090: e0bff817 ldw r2,-32(fp) + 1012094: e0bff315 stw r2,-52(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1012098: e0bff317 ldw r2,-52(fp) + 101209c: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (pmsg); /* Return received message */ + 10120a0: e0bffa17 ldw r2,-24(fp) + 10120a4: e0bfff15 stw r2,-4(fp) + 10120a8: e0bfff17 ldw r2,-4(fp) +} + 10120ac: e037883a mov sp,fp + 10120b0: dfc00117 ldw ra,4(sp) + 10120b4: df000017 ldw fp,0(sp) + 10120b8: dec00204 addi sp,sp,8 + 10120bc: f800283a ret + +010120c0 : +********************************************************************************************************* +*/ + +#if OS_Q_PEND_ABORT_EN > 0 +INT8U OSQPendAbort (OS_EVENT *pevent, INT8U opt, INT8U *perr) +{ + 10120c0: defff504 addi sp,sp,-44 + 10120c4: dfc00a15 stw ra,40(sp) + 10120c8: df000915 stw fp,36(sp) + 10120cc: df000904 addi fp,sp,36 + 10120d0: e13ffc15 stw r4,-16(fp) + 10120d4: e1bffe15 stw r6,-8(fp) + 10120d8: e17ffd05 stb r5,-12(fp) + INT8U nbr_tasks; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 10120dc: e03ffa15 stw zero,-24(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + 10120e0: e0bffe17 ldw r2,-8(fp) + 10120e4: 1004c03a cmpne r2,r2,zero + 10120e8: 1000021e bne r2,zero,10120f4 + return (0); + 10120ec: e03fff15 stw zero,-4(fp) + 10120f0: 00004c06 br 1012224 + } + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + 10120f4: e0bffc17 ldw r2,-16(fp) + 10120f8: 1004c03a cmpne r2,r2,zero + 10120fc: 1000051e bne r2,zero,1012114 + *perr = OS_ERR_PEVENT_NULL; + 1012100: e0fffe17 ldw r3,-8(fp) + 1012104: 00800104 movi r2,4 + 1012108: 18800005 stb r2,0(r3) + return (0); + 101210c: e03fff15 stw zero,-4(fp) + 1012110: 00004406 br 1012224 + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_Q) { /* Validate event block type */ + 1012114: e0bffc17 ldw r2,-16(fp) + 1012118: 10800003 ldbu r2,0(r2) + 101211c: 10803fcc andi r2,r2,255 + 1012120: 108000a0 cmpeqi r2,r2,2 + 1012124: 1000051e bne r2,zero,101213c + *perr = OS_ERR_EVENT_TYPE; + 1012128: e0fffe17 ldw r3,-8(fp) + 101212c: 00800044 movi r2,1 + 1012130: 18800005 stb r2,0(r3) + return (0); + 1012134: e03fff15 stw zero,-4(fp) + 1012138: 00003a06 br 1012224 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 101213c: 0005303a rdctl r2,status + 1012140: e0bff915 stw r2,-28(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1012144: e0fff917 ldw r3,-28(fp) + 1012148: 00bfff84 movi r2,-2 + 101214c: 1884703a and r2,r3,r2 + 1012150: 1001703a wrctl status,r2 + + return context; + 1012154: e0bff917 ldw r2,-28(fp) + } + OS_ENTER_CRITICAL(); + 1012158: e0bffa15 stw r2,-24(fp) + if (pevent->OSEventGrp != 0) { /* See if any task waiting on queue? */ + 101215c: e0bffc17 ldw r2,-16(fp) + 1012160: 10800283 ldbu r2,10(r2) + 1012164: 10803fcc andi r2,r2,255 + 1012168: 1005003a cmpeq r2,r2,zero + 101216c: 1000261e bne r2,zero,1012208 + nbr_tasks = 0; + 1012170: e03ffb05 stb zero,-20(fp) + switch (opt) { + 1012174: e0bffd03 ldbu r2,-12(fp) + 1012178: 10800060 cmpeqi r2,r2,1 + 101217c: 1000091e bne r2,zero,10121a4 + 1012180: 00000e06 br 10121bc + case OS_PEND_OPT_BROADCAST: /* Do we need to abort ALL waiting tasks? */ + while (pevent->OSEventGrp != 0) { /* Yes, ready ALL tasks waiting on queue */ + (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_Q, OS_STAT_PEND_ABORT); + 1012184: e13ffc17 ldw r4,-16(fp) + 1012188: 000b883a mov r5,zero + 101218c: 01800104 movi r6,4 + 1012190: 01c00084 movi r7,2 + 1012194: 100e2780 call 100e278 + nbr_tasks++; + 1012198: e0bffb03 ldbu r2,-20(fp) + 101219c: 10800044 addi r2,r2,1 + 10121a0: e0bffb05 stb r2,-20(fp) + OS_ENTER_CRITICAL(); + if (pevent->OSEventGrp != 0) { /* See if any task waiting on queue? */ + nbr_tasks = 0; + switch (opt) { + case OS_PEND_OPT_BROADCAST: /* Do we need to abort ALL waiting tasks? */ + while (pevent->OSEventGrp != 0) { /* Yes, ready ALL tasks waiting on queue */ + 10121a4: e0bffc17 ldw r2,-16(fp) + 10121a8: 10800283 ldbu r2,10(r2) + 10121ac: 10803fcc andi r2,r2,255 + 10121b0: 1004c03a cmpne r2,r2,zero + 10121b4: 103ff31e bne r2,zero,1012184 + (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_Q, OS_STAT_PEND_ABORT); + nbr_tasks++; + } + break; + 10121b8: 00000806 br 10121dc + + case OS_PEND_OPT_NONE: + default: /* No, ready HPT waiting on queue */ + (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_Q, OS_STAT_PEND_ABORT); + 10121bc: e13ffc17 ldw r4,-16(fp) + 10121c0: 000b883a mov r5,zero + 10121c4: 01800104 movi r6,4 + 10121c8: 01c00084 movi r7,2 + 10121cc: 100e2780 call 100e278 + nbr_tasks++; + 10121d0: e0bffb03 ldbu r2,-20(fp) + 10121d4: 10800044 addi r2,r2,1 + 10121d8: e0bffb05 stb r2,-20(fp) + 10121dc: e0bffa17 ldw r2,-24(fp) + 10121e0: e0bff815 stw r2,-32(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 10121e4: e0bff817 ldw r2,-32(fp) + 10121e8: 1001703a wrctl status,r2 + break; + } + OS_EXIT_CRITICAL(); + OS_Sched(); /* Find HPT ready to run */ + 10121ec: 100ecb80 call 100ecb8 + *perr = OS_ERR_PEND_ABORT; + 10121f0: e0fffe17 ldw r3,-8(fp) + 10121f4: 00800384 movi r2,14 + 10121f8: 18800005 stb r2,0(r3) + return (nbr_tasks); + 10121fc: e0bffb03 ldbu r2,-20(fp) + 1012200: e0bfff15 stw r2,-4(fp) + 1012204: 00000706 br 1012224 + 1012208: e0bffa17 ldw r2,-24(fp) + 101220c: e0bff715 stw r2,-36(fp) + 1012210: e0bff717 ldw r2,-36(fp) + 1012214: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + 1012218: e0bffe17 ldw r2,-8(fp) + 101221c: 10000005 stb zero,0(r2) + return (0); /* No tasks waiting on queue */ + 1012220: e03fff15 stw zero,-4(fp) + 1012224: e0bfff17 ldw r2,-4(fp) +} + 1012228: e037883a mov sp,fp + 101222c: dfc00117 ldw ra,4(sp) + 1012230: df000017 ldw fp,0(sp) + 1012234: dec00204 addi sp,sp,8 + 1012238: f800283a ret + +0101223c : +********************************************************************************************************* +*/ + +#if OS_Q_POST_EN > 0 +INT8U OSQPost (OS_EVENT *pevent, void *pmsg) +{ + 101223c: defff504 addi sp,sp,-44 + 1012240: dfc00a15 stw ra,40(sp) + 1012244: df000915 stw fp,36(sp) + 1012248: df000904 addi fp,sp,36 + 101224c: e13ffd15 stw r4,-12(fp) + 1012250: e17ffe15 stw r5,-8(fp) + OS_Q *pq; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 1012254: e03ffb15 stw zero,-20(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + 1012258: e0bffd17 ldw r2,-12(fp) + 101225c: 1004c03a cmpne r2,r2,zero + 1012260: 1000031e bne r2,zero,1012270 + return (OS_ERR_PEVENT_NULL); + 1012264: 00800104 movi r2,4 + 1012268: e0bfff15 stw r2,-4(fp) + 101226c: 00004d06 br 10123a4 + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_Q) { /* Validate event block type */ + 1012270: e0bffd17 ldw r2,-12(fp) + 1012274: 10800003 ldbu r2,0(r2) + 1012278: 10803fcc andi r2,r2,255 + 101227c: 108000a0 cmpeqi r2,r2,2 + 1012280: 1000031e bne r2,zero,1012290 + return (OS_ERR_EVENT_TYPE); + 1012284: 00800044 movi r2,1 + 1012288: e0bfff15 stw r2,-4(fp) + 101228c: 00004506 br 10123a4 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1012290: 0005303a rdctl r2,status + 1012294: e0bffa15 stw r2,-24(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1012298: e0fffa17 ldw r3,-24(fp) + 101229c: 00bfff84 movi r2,-2 + 10122a0: 1884703a and r2,r3,r2 + 10122a4: 1001703a wrctl status,r2 + + return context; + 10122a8: e0bffa17 ldw r2,-24(fp) + } + OS_ENTER_CRITICAL(); + 10122ac: e0bffb15 stw r2,-20(fp) + if (pevent->OSEventGrp != 0) { /* See if any task pending on queue */ + 10122b0: e0bffd17 ldw r2,-12(fp) + 10122b4: 10800283 ldbu r2,10(r2) + 10122b8: 10803fcc andi r2,r2,255 + 10122bc: 1005003a cmpeq r2,r2,zero + 10122c0: 10000c1e bne r2,zero,10122f4 + /* Ready highest priority task waiting on event */ + (void)OS_EventTaskRdy(pevent, pmsg, OS_STAT_Q, OS_STAT_PEND_OK); + 10122c4: e13ffd17 ldw r4,-12(fp) + 10122c8: e17ffe17 ldw r5,-8(fp) + 10122cc: 01800104 movi r6,4 + 10122d0: 000f883a mov r7,zero + 10122d4: 100e2780 call 100e278 + 10122d8: e0bffb17 ldw r2,-20(fp) + 10122dc: e0bff915 stw r2,-28(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 10122e0: e0bff917 ldw r2,-28(fp) + 10122e4: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + OS_Sched(); /* Find highest priority task ready to run */ + 10122e8: 100ecb80 call 100ecb8 + return (OS_ERR_NONE); + 10122ec: e03fff15 stw zero,-4(fp) + 10122f0: 00002c06 br 10123a4 + } + pq = (OS_Q *)pevent->OSEventPtr; /* Point to queue control block */ + 10122f4: e0bffd17 ldw r2,-12(fp) + 10122f8: 10800117 ldw r2,4(r2) + 10122fc: e0bffc15 stw r2,-16(fp) + if (pq->OSQEntries >= pq->OSQSize) { /* Make sure queue is not full */ + 1012300: e0bffc17 ldw r2,-16(fp) + 1012304: 10c0058b ldhu r3,22(r2) + 1012308: e0bffc17 ldw r2,-16(fp) + 101230c: 1080050b ldhu r2,20(r2) + 1012310: 18ffffcc andi r3,r3,65535 + 1012314: 10bfffcc andi r2,r2,65535 + 1012318: 18800736 bltu r3,r2,1012338 + 101231c: e0bffb17 ldw r2,-20(fp) + 1012320: e0bff815 stw r2,-32(fp) + 1012324: e0bff817 ldw r2,-32(fp) + 1012328: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_Q_FULL); + 101232c: 00800784 movi r2,30 + 1012330: e0bfff15 stw r2,-4(fp) + 1012334: 00001b06 br 10123a4 + } + *pq->OSQIn++ = pmsg; /* Insert message into queue */ + 1012338: e0bffc17 ldw r2,-16(fp) + 101233c: 10c00317 ldw r3,12(r2) + 1012340: e0bffe17 ldw r2,-8(fp) + 1012344: 18800015 stw r2,0(r3) + 1012348: 18c00104 addi r3,r3,4 + 101234c: e0bffc17 ldw r2,-16(fp) + 1012350: 10c00315 stw r3,12(r2) + pq->OSQEntries++; /* Update the nbr of entries in the queue */ + 1012354: e0bffc17 ldw r2,-16(fp) + 1012358: 1080058b ldhu r2,22(r2) + 101235c: 10800044 addi r2,r2,1 + 1012360: 1007883a mov r3,r2 + 1012364: e0bffc17 ldw r2,-16(fp) + 1012368: 10c0058d sth r3,22(r2) + if (pq->OSQIn == pq->OSQEnd) { /* Wrap IN ptr if we are at end of queue */ + 101236c: e0bffc17 ldw r2,-16(fp) + 1012370: 10c00317 ldw r3,12(r2) + 1012374: e0bffc17 ldw r2,-16(fp) + 1012378: 10800217 ldw r2,8(r2) + 101237c: 1880041e bne r3,r2,1012390 + pq->OSQIn = pq->OSQStart; + 1012380: e0bffc17 ldw r2,-16(fp) + 1012384: 10c00117 ldw r3,4(r2) + 1012388: e0bffc17 ldw r2,-16(fp) + 101238c: 10c00315 stw r3,12(r2) + 1012390: e0bffb17 ldw r2,-20(fp) + 1012394: e0bff715 stw r2,-36(fp) + 1012398: e0bff717 ldw r2,-36(fp) + 101239c: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); + return (OS_ERR_NONE); + 10123a0: e03fff15 stw zero,-4(fp) + 10123a4: e0bfff17 ldw r2,-4(fp) +} + 10123a8: e037883a mov sp,fp + 10123ac: dfc00117 ldw ra,4(sp) + 10123b0: df000017 ldw fp,0(sp) + 10123b4: dec00204 addi sp,sp,8 + 10123b8: f800283a ret + +010123bc : +********************************************************************************************************* +*/ + +#if OS_Q_POST_FRONT_EN > 0 +INT8U OSQPostFront (OS_EVENT *pevent, void *pmsg) +{ + 10123bc: defff504 addi sp,sp,-44 + 10123c0: dfc00a15 stw ra,40(sp) + 10123c4: df000915 stw fp,36(sp) + 10123c8: df000904 addi fp,sp,36 + 10123cc: e13ffd15 stw r4,-12(fp) + 10123d0: e17ffe15 stw r5,-8(fp) + OS_Q *pq; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 10123d4: e03ffb15 stw zero,-20(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + 10123d8: e0bffd17 ldw r2,-12(fp) + 10123dc: 1004c03a cmpne r2,r2,zero + 10123e0: 1000031e bne r2,zero,10123f0 + return (OS_ERR_PEVENT_NULL); + 10123e4: 00800104 movi r2,4 + 10123e8: e0bfff15 stw r2,-4(fp) + 10123ec: 00004f06 br 101252c + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_Q) { /* Validate event block type */ + 10123f0: e0bffd17 ldw r2,-12(fp) + 10123f4: 10800003 ldbu r2,0(r2) + 10123f8: 10803fcc andi r2,r2,255 + 10123fc: 108000a0 cmpeqi r2,r2,2 + 1012400: 1000031e bne r2,zero,1012410 + return (OS_ERR_EVENT_TYPE); + 1012404: 00800044 movi r2,1 + 1012408: e0bfff15 stw r2,-4(fp) + 101240c: 00004706 br 101252c +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1012410: 0005303a rdctl r2,status + 1012414: e0bffa15 stw r2,-24(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1012418: e0fffa17 ldw r3,-24(fp) + 101241c: 00bfff84 movi r2,-2 + 1012420: 1884703a and r2,r3,r2 + 1012424: 1001703a wrctl status,r2 + + return context; + 1012428: e0bffa17 ldw r2,-24(fp) + } + OS_ENTER_CRITICAL(); + 101242c: e0bffb15 stw r2,-20(fp) + if (pevent->OSEventGrp != 0) { /* See if any task pending on queue */ + 1012430: e0bffd17 ldw r2,-12(fp) + 1012434: 10800283 ldbu r2,10(r2) + 1012438: 10803fcc andi r2,r2,255 + 101243c: 1005003a cmpeq r2,r2,zero + 1012440: 10000c1e bne r2,zero,1012474 + /* Ready highest priority task waiting on event */ + (void)OS_EventTaskRdy(pevent, pmsg, OS_STAT_Q, OS_STAT_PEND_OK); + 1012444: e13ffd17 ldw r4,-12(fp) + 1012448: e17ffe17 ldw r5,-8(fp) + 101244c: 01800104 movi r6,4 + 1012450: 000f883a mov r7,zero + 1012454: 100e2780 call 100e278 + 1012458: e0bffb17 ldw r2,-20(fp) + 101245c: e0bff915 stw r2,-28(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1012460: e0bff917 ldw r2,-28(fp) + 1012464: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + OS_Sched(); /* Find highest priority task ready to run */ + 1012468: 100ecb80 call 100ecb8 + return (OS_ERR_NONE); + 101246c: e03fff15 stw zero,-4(fp) + 1012470: 00002e06 br 101252c + } + pq = (OS_Q *)pevent->OSEventPtr; /* Point to queue control block */ + 1012474: e0bffd17 ldw r2,-12(fp) + 1012478: 10800117 ldw r2,4(r2) + 101247c: e0bffc15 stw r2,-16(fp) + if (pq->OSQEntries >= pq->OSQSize) { /* Make sure queue is not full */ + 1012480: e0bffc17 ldw r2,-16(fp) + 1012484: 10c0058b ldhu r3,22(r2) + 1012488: e0bffc17 ldw r2,-16(fp) + 101248c: 1080050b ldhu r2,20(r2) + 1012490: 18ffffcc andi r3,r3,65535 + 1012494: 10bfffcc andi r2,r2,65535 + 1012498: 18800736 bltu r3,r2,10124b8 + 101249c: e0bffb17 ldw r2,-20(fp) + 10124a0: e0bff815 stw r2,-32(fp) + 10124a4: e0bff817 ldw r2,-32(fp) + 10124a8: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_Q_FULL); + 10124ac: 00800784 movi r2,30 + 10124b0: e0bfff15 stw r2,-4(fp) + 10124b4: 00001d06 br 101252c + } + if (pq->OSQOut == pq->OSQStart) { /* Wrap OUT ptr if we are at the 1st queue entry */ + 10124b8: e0bffc17 ldw r2,-16(fp) + 10124bc: 10c00417 ldw r3,16(r2) + 10124c0: e0bffc17 ldw r2,-16(fp) + 10124c4: 10800117 ldw r2,4(r2) + 10124c8: 1880041e bne r3,r2,10124dc + pq->OSQOut = pq->OSQEnd; + 10124cc: e0bffc17 ldw r2,-16(fp) + 10124d0: 10c00217 ldw r3,8(r2) + 10124d4: e0bffc17 ldw r2,-16(fp) + 10124d8: 10c00415 stw r3,16(r2) + } + pq->OSQOut--; + 10124dc: e0bffc17 ldw r2,-16(fp) + 10124e0: 10800417 ldw r2,16(r2) + 10124e4: 10ffff04 addi r3,r2,-4 + 10124e8: e0bffc17 ldw r2,-16(fp) + 10124ec: 10c00415 stw r3,16(r2) + *pq->OSQOut = pmsg; /* Insert message into queue */ + 10124f0: e0bffc17 ldw r2,-16(fp) + 10124f4: 10c00417 ldw r3,16(r2) + 10124f8: e0bffe17 ldw r2,-8(fp) + 10124fc: 18800015 stw r2,0(r3) + pq->OSQEntries++; /* Update the nbr of entries in the queue */ + 1012500: e0bffc17 ldw r2,-16(fp) + 1012504: 1080058b ldhu r2,22(r2) + 1012508: 10800044 addi r2,r2,1 + 101250c: 1007883a mov r3,r2 + 1012510: e0bffc17 ldw r2,-16(fp) + 1012514: 10c0058d sth r3,22(r2) + 1012518: e0bffb17 ldw r2,-20(fp) + 101251c: e0bff715 stw r2,-36(fp) + 1012520: e0bff717 ldw r2,-36(fp) + 1012524: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_NONE); + 1012528: e03fff15 stw zero,-4(fp) + 101252c: e0bfff17 ldw r2,-4(fp) +} + 1012530: e037883a mov sp,fp + 1012534: dfc00117 ldw ra,4(sp) + 1012538: df000017 ldw fp,0(sp) + 101253c: dec00204 addi sp,sp,8 + 1012540: f800283a ret + +01012544 : +********************************************************************************************************* +*/ + +#if OS_Q_POST_OPT_EN > 0 +INT8U OSQPostOpt (OS_EVENT *pevent, void *pmsg, INT8U opt) +{ + 1012544: defff404 addi sp,sp,-48 + 1012548: dfc00b15 stw ra,44(sp) + 101254c: df000a15 stw fp,40(sp) + 1012550: df000a04 addi fp,sp,40 + 1012554: e13ffc15 stw r4,-16(fp) + 1012558: e17ffd15 stw r5,-12(fp) + 101255c: e1bffe05 stb r6,-8(fp) + OS_Q *pq; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 1012560: e03ffa15 stw zero,-24(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + 1012564: e0bffc17 ldw r2,-16(fp) + 1012568: 1004c03a cmpne r2,r2,zero + 101256c: 1000031e bne r2,zero,101257c + return (OS_ERR_PEVENT_NULL); + 1012570: 00800104 movi r2,4 + 1012574: e0bfff15 stw r2,-4(fp) + 1012578: 00007906 br 1012760 + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_Q) { /* Validate event block type */ + 101257c: e0bffc17 ldw r2,-16(fp) + 1012580: 10800003 ldbu r2,0(r2) + 1012584: 10803fcc andi r2,r2,255 + 1012588: 108000a0 cmpeqi r2,r2,2 + 101258c: 1000031e bne r2,zero,101259c + return (OS_ERR_EVENT_TYPE); + 1012590: 00800044 movi r2,1 + 1012594: e0bfff15 stw r2,-4(fp) + 1012598: 00007106 br 1012760 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 101259c: 0005303a rdctl r2,status + 10125a0: e0bff915 stw r2,-28(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 10125a4: e0fff917 ldw r3,-28(fp) + 10125a8: 00bfff84 movi r2,-2 + 10125ac: 1884703a and r2,r3,r2 + 10125b0: 1001703a wrctl status,r2 + + return context; + 10125b4: e0bff917 ldw r2,-28(fp) + } + OS_ENTER_CRITICAL(); + 10125b8: e0bffa15 stw r2,-24(fp) + if (pevent->OSEventGrp != 0x00) { /* See if any task pending on queue */ + 10125bc: e0bffc17 ldw r2,-16(fp) + 10125c0: 10800283 ldbu r2,10(r2) + 10125c4: 10803fcc andi r2,r2,255 + 10125c8: 1005003a cmpeq r2,r2,zero + 10125cc: 1000211e bne r2,zero,1012654 + if ((opt & OS_POST_OPT_BROADCAST) != 0x00) { /* Do we need to post msg to ALL waiting tasks ? */ + 10125d0: e0bffe03 ldbu r2,-8(fp) + 10125d4: 1080004c andi r2,r2,1 + 10125d8: 10803fcc andi r2,r2,255 + 10125dc: 1005003a cmpeq r2,r2,zero + 10125e0: 10000c1e bne r2,zero,1012614 + while (pevent->OSEventGrp != 0) { /* Yes, Post to ALL tasks waiting on queue */ + 10125e4: 00000506 br 10125fc + (void)OS_EventTaskRdy(pevent, pmsg, OS_STAT_Q, OS_STAT_PEND_OK); + 10125e8: e13ffc17 ldw r4,-16(fp) + 10125ec: e17ffd17 ldw r5,-12(fp) + 10125f0: 01800104 movi r6,4 + 10125f4: 000f883a mov r7,zero + 10125f8: 100e2780 call 100e278 + return (OS_ERR_EVENT_TYPE); + } + OS_ENTER_CRITICAL(); + if (pevent->OSEventGrp != 0x00) { /* See if any task pending on queue */ + if ((opt & OS_POST_OPT_BROADCAST) != 0x00) { /* Do we need to post msg to ALL waiting tasks ? */ + while (pevent->OSEventGrp != 0) { /* Yes, Post to ALL tasks waiting on queue */ + 10125fc: e0bffc17 ldw r2,-16(fp) + 1012600: 10800283 ldbu r2,10(r2) + 1012604: 10803fcc andi r2,r2,255 + 1012608: 1004c03a cmpne r2,r2,zero + 101260c: 103ff61e bne r2,zero,10125e8 + 1012610: 00000506 br 1012628 + (void)OS_EventTaskRdy(pevent, pmsg, OS_STAT_Q, OS_STAT_PEND_OK); + } + } else { /* No, Post to HPT waiting on queue */ + (void)OS_EventTaskRdy(pevent, pmsg, OS_STAT_Q, OS_STAT_PEND_OK); + 1012614: e13ffc17 ldw r4,-16(fp) + 1012618: e17ffd17 ldw r5,-12(fp) + 101261c: 01800104 movi r6,4 + 1012620: 000f883a mov r7,zero + 1012624: 100e2780 call 100e278 + 1012628: e0bffa17 ldw r2,-24(fp) + 101262c: e0bff815 stw r2,-32(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1012630: e0bff817 ldw r2,-32(fp) + 1012634: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); + if ((opt & OS_POST_OPT_NO_SCHED) == 0) { /* See if scheduler needs to be invoked */ + 1012638: e0bffe03 ldbu r2,-8(fp) + 101263c: 1080010c andi r2,r2,4 + 1012640: 1004c03a cmpne r2,r2,zero + 1012644: 1000011e bne r2,zero,101264c + OS_Sched(); /* Find highest priority task ready to run */ + 1012648: 100ecb80 call 100ecb8 + } + return (OS_ERR_NONE); + 101264c: e03fff15 stw zero,-4(fp) + 1012650: 00004306 br 1012760 + } + pq = (OS_Q *)pevent->OSEventPtr; /* Point to queue control block */ + 1012654: e0bffc17 ldw r2,-16(fp) + 1012658: 10800117 ldw r2,4(r2) + 101265c: e0bffb15 stw r2,-20(fp) + if (pq->OSQEntries >= pq->OSQSize) { /* Make sure queue is not full */ + 1012660: e0bffb17 ldw r2,-20(fp) + 1012664: 10c0058b ldhu r3,22(r2) + 1012668: e0bffb17 ldw r2,-20(fp) + 101266c: 1080050b ldhu r2,20(r2) + 1012670: 18ffffcc andi r3,r3,65535 + 1012674: 10bfffcc andi r2,r2,65535 + 1012678: 18800736 bltu r3,r2,1012698 + 101267c: e0bffa17 ldw r2,-24(fp) + 1012680: e0bff715 stw r2,-36(fp) + 1012684: e0bff717 ldw r2,-36(fp) + 1012688: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_Q_FULL); + 101268c: 00800784 movi r2,30 + 1012690: e0bfff15 stw r2,-4(fp) + 1012694: 00003206 br 1012760 + } + if ((opt & OS_POST_OPT_FRONT) != 0x00) { /* Do we post to the FRONT of the queue? */ + 1012698: e0bffe03 ldbu r2,-8(fp) + 101269c: 1080008c andi r2,r2,2 + 10126a0: 1005003a cmpeq r2,r2,zero + 10126a4: 1000131e bne r2,zero,10126f4 + if (pq->OSQOut == pq->OSQStart) { /* Yes, Post as LIFO, Wrap OUT pointer if we ... */ + 10126a8: e0bffb17 ldw r2,-20(fp) + 10126ac: 10c00417 ldw r3,16(r2) + 10126b0: e0bffb17 ldw r2,-20(fp) + 10126b4: 10800117 ldw r2,4(r2) + 10126b8: 1880041e bne r3,r2,10126cc + pq->OSQOut = pq->OSQEnd; /* ... are at the 1st queue entry */ + 10126bc: e0bffb17 ldw r2,-20(fp) + 10126c0: 10c00217 ldw r3,8(r2) + 10126c4: e0bffb17 ldw r2,-20(fp) + 10126c8: 10c00415 stw r3,16(r2) + } + pq->OSQOut--; + 10126cc: e0bffb17 ldw r2,-20(fp) + 10126d0: 10800417 ldw r2,16(r2) + 10126d4: 10ffff04 addi r3,r2,-4 + 10126d8: e0bffb17 ldw r2,-20(fp) + 10126dc: 10c00415 stw r3,16(r2) + *pq->OSQOut = pmsg; /* Insert message into queue */ + 10126e0: e0bffb17 ldw r2,-20(fp) + 10126e4: 10c00417 ldw r3,16(r2) + 10126e8: e0bffd17 ldw r2,-12(fp) + 10126ec: 18800015 stw r2,0(r3) + 10126f0: 00001006 br 1012734 + } else { /* No, Post as FIFO */ + *pq->OSQIn++ = pmsg; /* Insert message into queue */ + 10126f4: e0bffb17 ldw r2,-20(fp) + 10126f8: 10c00317 ldw r3,12(r2) + 10126fc: e0bffd17 ldw r2,-12(fp) + 1012700: 18800015 stw r2,0(r3) + 1012704: 18c00104 addi r3,r3,4 + 1012708: e0bffb17 ldw r2,-20(fp) + 101270c: 10c00315 stw r3,12(r2) + if (pq->OSQIn == pq->OSQEnd) { /* Wrap IN ptr if we are at end of queue */ + 1012710: e0bffb17 ldw r2,-20(fp) + 1012714: 10c00317 ldw r3,12(r2) + 1012718: e0bffb17 ldw r2,-20(fp) + 101271c: 10800217 ldw r2,8(r2) + 1012720: 1880041e bne r3,r2,1012734 + pq->OSQIn = pq->OSQStart; + 1012724: e0bffb17 ldw r2,-20(fp) + 1012728: 10c00117 ldw r3,4(r2) + 101272c: e0bffb17 ldw r2,-20(fp) + 1012730: 10c00315 stw r3,12(r2) + } + } + pq->OSQEntries++; /* Update the nbr of entries in the queue */ + 1012734: e0bffb17 ldw r2,-20(fp) + 1012738: 1080058b ldhu r2,22(r2) + 101273c: 10800044 addi r2,r2,1 + 1012740: 1007883a mov r3,r2 + 1012744: e0bffb17 ldw r2,-20(fp) + 1012748: 10c0058d sth r3,22(r2) + 101274c: e0bffa17 ldw r2,-24(fp) + 1012750: e0bff615 stw r2,-40(fp) + 1012754: e0bff617 ldw r2,-40(fp) + 1012758: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_NONE); + 101275c: e03fff15 stw zero,-4(fp) + 1012760: e0bfff17 ldw r2,-4(fp) +} + 1012764: e037883a mov sp,fp + 1012768: dfc00117 ldw ra,4(sp) + 101276c: df000017 ldw fp,0(sp) + 1012770: dec00204 addi sp,sp,8 + 1012774: f800283a ret + +01012778 : +********************************************************************************************************* +*/ + +#if OS_Q_QUERY_EN > 0 +INT8U OSQQuery (OS_EVENT *pevent, OS_Q_DATA *p_q_data) +{ + 1012778: defff504 addi sp,sp,-44 + 101277c: df000a15 stw fp,40(sp) + 1012780: df000a04 addi fp,sp,40 + 1012784: e13ffd15 stw r4,-12(fp) + 1012788: e17ffe15 stw r5,-8(fp) +#else + INT16U *psrc; + INT16U *pdest; +#endif +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 101278c: e03ff815 stw zero,-32(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + 1012790: e0bffd17 ldw r2,-12(fp) + 1012794: 1004c03a cmpne r2,r2,zero + 1012798: 1000031e bne r2,zero,10127a8 + return (OS_ERR_PEVENT_NULL); + 101279c: 00800104 movi r2,4 + 10127a0: e0bfff15 stw r2,-4(fp) + 10127a4: 00004f06 br 10128e4 + } + if (p_q_data == (OS_Q_DATA *)0) { /* Validate 'p_q_data' */ + 10127a8: e0bffe17 ldw r2,-8(fp) + 10127ac: 1004c03a cmpne r2,r2,zero + 10127b0: 1000031e bne r2,zero,10127c0 + return (OS_ERR_PDATA_NULL); + 10127b4: 00800244 movi r2,9 + 10127b8: e0bfff15 stw r2,-4(fp) + 10127bc: 00004906 br 10128e4 + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_Q) { /* Validate event block type */ + 10127c0: e0bffd17 ldw r2,-12(fp) + 10127c4: 10800003 ldbu r2,0(r2) + 10127c8: 10803fcc andi r2,r2,255 + 10127cc: 108000a0 cmpeqi r2,r2,2 + 10127d0: 1000031e bne r2,zero,10127e0 + return (OS_ERR_EVENT_TYPE); + 10127d4: 00800044 movi r2,1 + 10127d8: e0bfff15 stw r2,-4(fp) + 10127dc: 00004106 br 10128e4 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 10127e0: 0005303a rdctl r2,status + 10127e4: e0bff715 stw r2,-36(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 10127e8: e0fff717 ldw r3,-36(fp) + 10127ec: 00bfff84 movi r2,-2 + 10127f0: 1884703a and r2,r3,r2 + 10127f4: 1001703a wrctl status,r2 + + return context; + 10127f8: e0bff717 ldw r2,-36(fp) + } + OS_ENTER_CRITICAL(); + 10127fc: e0bff815 stw r2,-32(fp) + p_q_data->OSEventGrp = pevent->OSEventGrp; /* Copy message queue wait list */ + 1012800: e0bffd17 ldw r2,-12(fp) + 1012804: 10c00283 ldbu r3,10(r2) + 1012808: e0bffe17 ldw r2,-8(fp) + 101280c: 10c002c5 stb r3,11(r2) + psrc = &pevent->OSEventTbl[0]; + 1012810: e0bffd17 ldw r2,-12(fp) + 1012814: 108002c4 addi r2,r2,11 + 1012818: e0bffa15 stw r2,-24(fp) + pdest = &p_q_data->OSEventTbl[0]; + 101281c: e0bffe17 ldw r2,-8(fp) + 1012820: 10800204 addi r2,r2,8 + 1012824: e0bff915 stw r2,-28(fp) + for (i = 0; i < OS_EVENT_TBL_SIZE; i++) { + 1012828: e03ffb05 stb zero,-20(fp) + 101282c: 00000d06 br 1012864 + *pdest++ = *psrc++; + 1012830: e0bffa17 ldw r2,-24(fp) + 1012834: 10c00003 ldbu r3,0(r2) + 1012838: e0bff917 ldw r2,-28(fp) + 101283c: 10c00005 stb r3,0(r2) + 1012840: e0bff917 ldw r2,-28(fp) + 1012844: 10800044 addi r2,r2,1 + 1012848: e0bff915 stw r2,-28(fp) + 101284c: e0bffa17 ldw r2,-24(fp) + 1012850: 10800044 addi r2,r2,1 + 1012854: e0bffa15 stw r2,-24(fp) + } + OS_ENTER_CRITICAL(); + p_q_data->OSEventGrp = pevent->OSEventGrp; /* Copy message queue wait list */ + psrc = &pevent->OSEventTbl[0]; + pdest = &p_q_data->OSEventTbl[0]; + for (i = 0; i < OS_EVENT_TBL_SIZE; i++) { + 1012858: e0bffb03 ldbu r2,-20(fp) + 101285c: 10800044 addi r2,r2,1 + 1012860: e0bffb05 stb r2,-20(fp) + 1012864: e0bffb03 ldbu r2,-20(fp) + 1012868: 108000f0 cmpltui r2,r2,3 + 101286c: 103ff01e bne r2,zero,1012830 + *pdest++ = *psrc++; + } + pq = (OS_Q *)pevent->OSEventPtr; + 1012870: e0bffd17 ldw r2,-12(fp) + 1012874: 10800117 ldw r2,4(r2) + 1012878: e0bffc15 stw r2,-16(fp) + if (pq->OSQEntries > 0) { + 101287c: e0bffc17 ldw r2,-16(fp) + 1012880: 1080058b ldhu r2,22(r2) + 1012884: 10bfffcc andi r2,r2,65535 + 1012888: 1005003a cmpeq r2,r2,zero + 101288c: 1000061e bne r2,zero,10128a8 + p_q_data->OSMsg = *pq->OSQOut; /* Get next message to return if available */ + 1012890: e0bffc17 ldw r2,-16(fp) + 1012894: 10800417 ldw r2,16(r2) + 1012898: 10c00017 ldw r3,0(r2) + 101289c: e0bffe17 ldw r2,-8(fp) + 10128a0: 10c00015 stw r3,0(r2) + 10128a4: 00000206 br 10128b0 + } else { + p_q_data->OSMsg = (void *)0; + 10128a8: e0bffe17 ldw r2,-8(fp) + 10128ac: 10000015 stw zero,0(r2) + } + p_q_data->OSNMsgs = pq->OSQEntries; + 10128b0: e0bffc17 ldw r2,-16(fp) + 10128b4: 10c0058b ldhu r3,22(r2) + 10128b8: e0bffe17 ldw r2,-8(fp) + 10128bc: 10c0010d sth r3,4(r2) + p_q_data->OSQSize = pq->OSQSize; + 10128c0: e0bffc17 ldw r2,-16(fp) + 10128c4: 10c0050b ldhu r3,20(r2) + 10128c8: e0bffe17 ldw r2,-8(fp) + 10128cc: 10c0018d sth r3,6(r2) + 10128d0: e0bff817 ldw r2,-32(fp) + 10128d4: e0bff615 stw r2,-40(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 10128d8: e0bff617 ldw r2,-40(fp) + 10128dc: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_NONE); + 10128e0: e03fff15 stw zero,-4(fp) + 10128e4: e0bfff17 ldw r2,-4(fp) +} + 10128e8: e037883a mov sp,fp + 10128ec: df000017 ldw fp,0(sp) + 10128f0: dec00104 addi sp,sp,4 + 10128f4: f800283a ret + +010128f8 : +* Note(s) : This function is INTERNAL to uC/OS-II and your application should not call it. +********************************************************************************************************* +*/ + +void OS_QInit (void) +{ + 10128f8: defffb04 addi sp,sp,-20 + 10128fc: dfc00415 stw ra,16(sp) + 1012900: df000315 stw fp,12(sp) + 1012904: df000304 addi fp,sp,12 + OS_Q *pq1; + OS_Q *pq2; + + + + OS_MemClr((INT8U *)&OSQTbl[0], sizeof(OSQTbl)); /* Clear the queue table */ + 1012908: 010040b4 movhi r4,258 + 101290c: 21131d04 addi r4,r4,19572 + 1012910: 01407804 movi r5,480 + 1012914: 100ebf80 call 100ebf8 + pq1 = &OSQTbl[0]; + 1012918: 008040b4 movhi r2,258 + 101291c: 10931d04 addi r2,r2,19572 + 1012920: e0bffe15 stw r2,-8(fp) + pq2 = &OSQTbl[1]; + 1012924: 008040b4 movhi r2,258 + 1012928: 10932304 addi r2,r2,19596 + 101292c: e0bffd15 stw r2,-12(fp) + for (i = 0; i < (OS_MAX_QS - 1); i++) { /* Init. list of free QUEUE control blocks */ + 1012930: e03fff0d sth zero,-4(fp) + 1012934: 00000c06 br 1012968 + pq1->OSQPtr = pq2; + 1012938: e0fffe17 ldw r3,-8(fp) + 101293c: e0bffd17 ldw r2,-12(fp) + 1012940: 18800015 stw r2,0(r3) + pq1++; + 1012944: e0bffe17 ldw r2,-8(fp) + 1012948: 10800604 addi r2,r2,24 + 101294c: e0bffe15 stw r2,-8(fp) + pq2++; + 1012950: e0bffd17 ldw r2,-12(fp) + 1012954: 10800604 addi r2,r2,24 + 1012958: e0bffd15 stw r2,-12(fp) + + + OS_MemClr((INT8U *)&OSQTbl[0], sizeof(OSQTbl)); /* Clear the queue table */ + pq1 = &OSQTbl[0]; + pq2 = &OSQTbl[1]; + for (i = 0; i < (OS_MAX_QS - 1); i++) { /* Init. list of free QUEUE control blocks */ + 101295c: e0bfff0b ldhu r2,-4(fp) + 1012960: 10800044 addi r2,r2,1 + 1012964: e0bfff0d sth r2,-4(fp) + 1012968: e0bfff0b ldhu r2,-4(fp) + 101296c: 108004f0 cmpltui r2,r2,19 + 1012970: 103ff11e bne r2,zero,1012938 + pq1->OSQPtr = pq2; + pq1++; + pq2++; + } + pq1->OSQPtr = (OS_Q *)0; + 1012974: e0bffe17 ldw r2,-8(fp) + 1012978: 10000015 stw zero,0(r2) + OSQFreeList = &OSQTbl[0]; + 101297c: 00c040b4 movhi r3,258 + 1012980: 18f31b04 addi r3,r3,-13204 + 1012984: 008040b4 movhi r2,258 + 1012988: 10931d04 addi r2,r2,19572 + 101298c: 18800015 stw r2,0(r3) +#endif +} + 1012990: e037883a mov sp,fp + 1012994: dfc00117 ldw ra,4(sp) + 1012998: df000017 ldw fp,0(sp) + 101299c: dec00204 addi sp,sp,8 + 10129a0: f800283a ret + +010129a4 : +********************************************************************************************************* +*/ + +#if OS_SEM_ACCEPT_EN > 0 +INT16U OSSemAccept (OS_EVENT *pevent) +{ + 10129a4: defff904 addi sp,sp,-28 + 10129a8: df000615 stw fp,24(sp) + 10129ac: df000604 addi fp,sp,24 + 10129b0: e13ffe15 stw r4,-8(fp) + INT16U cnt; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 10129b4: e03ffc15 stw zero,-16(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + 10129b8: e0bffe17 ldw r2,-8(fp) + 10129bc: 1004c03a cmpne r2,r2,zero + 10129c0: 1000021e bne r2,zero,10129cc + return (0); + 10129c4: e03fff15 stw zero,-4(fp) + 10129c8: 00002106 br 1012a50 + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_SEM) { /* Validate event block type */ + 10129cc: e0bffe17 ldw r2,-8(fp) + 10129d0: 10800003 ldbu r2,0(r2) + 10129d4: 10803fcc andi r2,r2,255 + 10129d8: 108000e0 cmpeqi r2,r2,3 + 10129dc: 1000021e bne r2,zero,10129e8 + return (0); + 10129e0: e03fff15 stw zero,-4(fp) + 10129e4: 00001a06 br 1012a50 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 10129e8: 0005303a rdctl r2,status + 10129ec: e0bffb15 stw r2,-20(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 10129f0: e0fffb17 ldw r3,-20(fp) + 10129f4: 00bfff84 movi r2,-2 + 10129f8: 1884703a and r2,r3,r2 + 10129fc: 1001703a wrctl status,r2 + + return context; + 1012a00: e0bffb17 ldw r2,-20(fp) + } + OS_ENTER_CRITICAL(); + 1012a04: e0bffc15 stw r2,-16(fp) + cnt = pevent->OSEventCnt; + 1012a08: e0bffe17 ldw r2,-8(fp) + 1012a0c: 1080020b ldhu r2,8(r2) + 1012a10: e0bffd0d sth r2,-12(fp) + if (cnt > 0) { /* See if resource is available */ + 1012a14: e0bffd0b ldhu r2,-12(fp) + 1012a18: 1005003a cmpeq r2,r2,zero + 1012a1c: 1000061e bne r2,zero,1012a38 + pevent->OSEventCnt--; /* Yes, decrement semaphore and notify caller */ + 1012a20: e0bffe17 ldw r2,-8(fp) + 1012a24: 1080020b ldhu r2,8(r2) + 1012a28: 10bfffc4 addi r2,r2,-1 + 1012a2c: 1007883a mov r3,r2 + 1012a30: e0bffe17 ldw r2,-8(fp) + 1012a34: 10c0020d sth r3,8(r2) + 1012a38: e0bffc17 ldw r2,-16(fp) + 1012a3c: e0bffa15 stw r2,-24(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1012a40: e0bffa17 ldw r2,-24(fp) + 1012a44: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); + return (cnt); /* Return semaphore count */ + 1012a48: e0bffd0b ldhu r2,-12(fp) + 1012a4c: e0bfff15 stw r2,-4(fp) + 1012a50: e0bfff17 ldw r2,-4(fp) +} + 1012a54: e037883a mov sp,fp + 1012a58: df000017 ldw fp,0(sp) + 1012a5c: dec00104 addi sp,sp,4 + 1012a60: f800283a ret + +01012a64 : +* == (void *)0 if no event control blocks were available +********************************************************************************************************* +*/ + +OS_EVENT *OSSemCreate (INT16U cnt) +{ + 1012a64: defff804 addi sp,sp,-32 + 1012a68: dfc00715 stw ra,28(sp) + 1012a6c: df000615 stw fp,24(sp) + 1012a70: df000604 addi fp,sp,24 + 1012a74: e13ffe0d sth r4,-8(fp) + OS_EVENT *pevent; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 1012a78: e03ffc15 stw zero,-16(fp) +#endif + + + + if (OSIntNesting > 0) { /* See if called from ISR ... */ + 1012a7c: 008040b4 movhi r2,258 + 1012a80: 10b31e04 addi r2,r2,-13192 + 1012a84: 10800003 ldbu r2,0(r2) + 1012a88: 10803fcc andi r2,r2,255 + 1012a8c: 1005003a cmpeq r2,r2,zero + 1012a90: 1000021e bne r2,zero,1012a9c + return ((OS_EVENT *)0); /* ... can't CREATE from an ISR */ + 1012a94: e03fff15 stw zero,-4(fp) + 1012a98: 00003106 br 1012b60 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1012a9c: 0005303a rdctl r2,status + 1012aa0: e0bffb15 stw r2,-20(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1012aa4: e0fffb17 ldw r3,-20(fp) + 1012aa8: 00bfff84 movi r2,-2 + 1012aac: 1884703a and r2,r3,r2 + 1012ab0: 1001703a wrctl status,r2 + + return context; + 1012ab4: e0bffb17 ldw r2,-20(fp) + } + OS_ENTER_CRITICAL(); + 1012ab8: e0bffc15 stw r2,-16(fp) + pevent = OSEventFreeList; /* Get next free event control block */ + 1012abc: 008040b4 movhi r2,258 + 1012ac0: 10b31d04 addi r2,r2,-13196 + 1012ac4: 10800017 ldw r2,0(r2) + 1012ac8: e0bffd15 stw r2,-12(fp) + if (OSEventFreeList != (OS_EVENT *)0) { /* See if pool of free ECB pool was empty */ + 1012acc: 008040b4 movhi r2,258 + 1012ad0: 10b31d04 addi r2,r2,-13196 + 1012ad4: 10800017 ldw r2,0(r2) + 1012ad8: 1005003a cmpeq r2,r2,zero + 1012adc: 1000081e bne r2,zero,1012b00 + OSEventFreeList = (OS_EVENT *)OSEventFreeList->OSEventPtr; + 1012ae0: 008040b4 movhi r2,258 + 1012ae4: 10b31d04 addi r2,r2,-13196 + 1012ae8: 10800017 ldw r2,0(r2) + 1012aec: 10800117 ldw r2,4(r2) + 1012af0: 1007883a mov r3,r2 + 1012af4: 008040b4 movhi r2,258 + 1012af8: 10b31d04 addi r2,r2,-13196 + 1012afc: 10c00015 stw r3,0(r2) + 1012b00: e0bffc17 ldw r2,-16(fp) + 1012b04: e0bffa15 stw r2,-24(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1012b08: e0bffa17 ldw r2,-24(fp) + 1012b0c: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); + if (pevent != (OS_EVENT *)0) { /* Get an event control block */ + 1012b10: e0bffd17 ldw r2,-12(fp) + 1012b14: 1005003a cmpeq r2,r2,zero + 1012b18: 10000f1e bne r2,zero,1012b58 + pevent->OSEventType = OS_EVENT_TYPE_SEM; + 1012b1c: e0fffd17 ldw r3,-12(fp) + 1012b20: 008000c4 movi r2,3 + 1012b24: 18800005 stb r2,0(r3) + pevent->OSEventCnt = cnt; /* Set semaphore value */ + 1012b28: e0fffd17 ldw r3,-12(fp) + 1012b2c: e0bffe0b ldhu r2,-8(fp) + 1012b30: 1880020d sth r2,8(r3) + pevent->OSEventPtr = (void *)0; /* Unlink from ECB free list */ + 1012b34: e0bffd17 ldw r2,-12(fp) + 1012b38: 10000115 stw zero,4(r2) +#if OS_EVENT_NAME_SIZE > 1 + pevent->OSEventName[0] = '?'; /* Unknown name */ + 1012b3c: e0fffd17 ldw r3,-12(fp) + 1012b40: 00800fc4 movi r2,63 + 1012b44: 18800385 stb r2,14(r3) + pevent->OSEventName[1] = OS_ASCII_NUL; + 1012b48: e0bffd17 ldw r2,-12(fp) + 1012b4c: 100003c5 stb zero,15(r2) +#endif + OS_EventWaitListInit(pevent); /* Initialize to 'nobody waiting' on sem. */ + 1012b50: e13ffd17 ldw r4,-12(fp) + 1012b54: 100e82c0 call 100e82c + } + return (pevent); + 1012b58: e0bffd17 ldw r2,-12(fp) + 1012b5c: e0bfff15 stw r2,-4(fp) + 1012b60: e0bfff17 ldw r2,-4(fp) +} + 1012b64: e037883a mov sp,fp + 1012b68: dfc00117 ldw ra,4(sp) + 1012b6c: df000017 ldw fp,0(sp) + 1012b70: dec00204 addi sp,sp,8 + 1012b74: f800283a ret + +01012b78 : +********************************************************************************************************* +*/ + +#if OS_SEM_DEL_EN > 0 +OS_EVENT *OSSemDel (OS_EVENT *pevent, INT8U opt, INT8U *perr) +{ + 1012b78: defff104 addi sp,sp,-60 + 1012b7c: dfc00e15 stw ra,56(sp) + 1012b80: df000d15 stw fp,52(sp) + 1012b84: df000d04 addi fp,sp,52 + 1012b88: e13ffb15 stw r4,-20(fp) + 1012b8c: e1bffd15 stw r6,-12(fp) + 1012b90: e17ffc05 stb r5,-16(fp) + BOOLEAN tasks_waiting; + OS_EVENT *pevent_return; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 1012b94: e03ff815 stw zero,-32(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + 1012b98: e0bffd17 ldw r2,-12(fp) + 1012b9c: 1004c03a cmpne r2,r2,zero + 1012ba0: 1000031e bne r2,zero,1012bb0 + return (pevent); + 1012ba4: e0bffb17 ldw r2,-20(fp) + 1012ba8: e0bfff15 stw r2,-4(fp) + 1012bac: 00009406 br 1012e00 + } + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + 1012bb0: e0bffb17 ldw r2,-20(fp) + 1012bb4: 1004c03a cmpne r2,r2,zero + 1012bb8: 1000061e bne r2,zero,1012bd4 + *perr = OS_ERR_PEVENT_NULL; + 1012bbc: e0fffd17 ldw r3,-12(fp) + 1012bc0: 00800104 movi r2,4 + 1012bc4: 18800005 stb r2,0(r3) + return (pevent); + 1012bc8: e0fffb17 ldw r3,-20(fp) + 1012bcc: e0ffff15 stw r3,-4(fp) + 1012bd0: 00008b06 br 1012e00 + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_SEM) { /* Validate event block type */ + 1012bd4: e0bffb17 ldw r2,-20(fp) + 1012bd8: 10800003 ldbu r2,0(r2) + 1012bdc: 10803fcc andi r2,r2,255 + 1012be0: 108000e0 cmpeqi r2,r2,3 + 1012be4: 1000061e bne r2,zero,1012c00 + *perr = OS_ERR_EVENT_TYPE; + 1012be8: e0fffd17 ldw r3,-12(fp) + 1012bec: 00800044 movi r2,1 + 1012bf0: 18800005 stb r2,0(r3) + return (pevent); + 1012bf4: e0bffb17 ldw r2,-20(fp) + 1012bf8: e0bfff15 stw r2,-4(fp) + 1012bfc: 00008006 br 1012e00 + } + if (OSIntNesting > 0) { /* See if called from ISR ... */ + 1012c00: 008040b4 movhi r2,258 + 1012c04: 10b31e04 addi r2,r2,-13192 + 1012c08: 10800003 ldbu r2,0(r2) + 1012c0c: 10803fcc andi r2,r2,255 + 1012c10: 1005003a cmpeq r2,r2,zero + 1012c14: 1000061e bne r2,zero,1012c30 + *perr = OS_ERR_DEL_ISR; /* ... can't DELETE from an ISR */ + 1012c18: e0fffd17 ldw r3,-12(fp) + 1012c1c: 008003c4 movi r2,15 + 1012c20: 18800005 stb r2,0(r3) + return (pevent); + 1012c24: e0fffb17 ldw r3,-20(fp) + 1012c28: e0ffff15 stw r3,-4(fp) + 1012c2c: 00007406 br 1012e00 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1012c30: 0005303a rdctl r2,status + 1012c34: e0bff715 stw r2,-36(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1012c38: e0fff717 ldw r3,-36(fp) + 1012c3c: 00bfff84 movi r2,-2 + 1012c40: 1884703a and r2,r3,r2 + 1012c44: 1001703a wrctl status,r2 + + return context; + 1012c48: e0bff717 ldw r2,-36(fp) + } + OS_ENTER_CRITICAL(); + 1012c4c: e0bff815 stw r2,-32(fp) + if (pevent->OSEventGrp != 0) { /* See if any tasks waiting on semaphore */ + 1012c50: e0bffb17 ldw r2,-20(fp) + 1012c54: 10800283 ldbu r2,10(r2) + 1012c58: 10803fcc andi r2,r2,255 + 1012c5c: 1005003a cmpeq r2,r2,zero + 1012c60: 1000031e bne r2,zero,1012c70 + tasks_waiting = OS_TRUE; /* Yes */ + 1012c64: 00800044 movi r2,1 + 1012c68: e0bffa05 stb r2,-24(fp) + 1012c6c: 00000106 br 1012c74 + } else { + tasks_waiting = OS_FALSE; /* No */ + 1012c70: e03ffa05 stb zero,-24(fp) + } + switch (opt) { + 1012c74: e0bffc03 ldbu r2,-16(fp) + 1012c78: e0bffe15 stw r2,-8(fp) + 1012c7c: e0fffe17 ldw r3,-8(fp) + 1012c80: 1805003a cmpeq r2,r3,zero + 1012c84: 1000041e bne r2,zero,1012c98 + 1012c88: e0fffe17 ldw r3,-8(fp) + 1012c8c: 18800060 cmpeqi r2,r3,1 + 1012c90: 10002d1e bne r2,zero,1012d48 + 1012c94: 00004f06 br 1012dd4 + case OS_DEL_NO_PEND: /* Delete semaphore only if no task waiting */ + if (tasks_waiting == OS_FALSE) { + 1012c98: e0bffa03 ldbu r2,-24(fp) + 1012c9c: 1004c03a cmpne r2,r2,zero + 1012ca0: 10001a1e bne r2,zero,1012d0c +#if OS_EVENT_NAME_SIZE > 1 + pevent->OSEventName[0] = '?'; /* Unknown name */ + 1012ca4: e0fffb17 ldw r3,-20(fp) + 1012ca8: 00800fc4 movi r2,63 + 1012cac: 18800385 stb r2,14(r3) + pevent->OSEventName[1] = OS_ASCII_NUL; + 1012cb0: e0bffb17 ldw r2,-20(fp) + 1012cb4: 100003c5 stb zero,15(r2) +#endif + pevent->OSEventType = OS_EVENT_TYPE_UNUSED; + 1012cb8: e0bffb17 ldw r2,-20(fp) + 1012cbc: 10000005 stb zero,0(r2) + pevent->OSEventPtr = OSEventFreeList; /* Return Event Control Block to free list */ + 1012cc0: 008040b4 movhi r2,258 + 1012cc4: 10b31d04 addi r2,r2,-13196 + 1012cc8: 10c00017 ldw r3,0(r2) + 1012ccc: e0bffb17 ldw r2,-20(fp) + 1012cd0: 10c00115 stw r3,4(r2) + pevent->OSEventCnt = 0; + 1012cd4: e0bffb17 ldw r2,-20(fp) + 1012cd8: 1000020d sth zero,8(r2) + OSEventFreeList = pevent; /* Get next free event control block */ + 1012cdc: 00c040b4 movhi r3,258 + 1012ce0: 18f31d04 addi r3,r3,-13196 + 1012ce4: e0bffb17 ldw r2,-20(fp) + 1012ce8: 18800015 stw r2,0(r3) + 1012cec: e0bff817 ldw r2,-32(fp) + 1012cf0: e0bff615 stw r2,-40(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1012cf4: e0bff617 ldw r2,-40(fp) + 1012cf8: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + 1012cfc: e0bffd17 ldw r2,-12(fp) + 1012d00: 10000005 stb zero,0(r2) + pevent_return = (OS_EVENT *)0; /* Semaphore has been deleted */ + 1012d04: e03ff915 stw zero,-28(fp) + 1012d08: 00003b06 br 1012df8 + 1012d0c: e0bff817 ldw r2,-32(fp) + 1012d10: e0bff515 stw r2,-44(fp) + 1012d14: e0bff517 ldw r2,-44(fp) + 1012d18: 1001703a wrctl status,r2 + } else { + OS_EXIT_CRITICAL(); + *perr = OS_ERR_TASK_WAITING; + 1012d1c: e0fffd17 ldw r3,-12(fp) + 1012d20: 00801244 movi r2,73 + 1012d24: 18800005 stb r2,0(r3) + pevent_return = pevent; + 1012d28: e0bffb17 ldw r2,-20(fp) + 1012d2c: e0bff915 stw r2,-28(fp) + } + break; + 1012d30: 00003106 br 1012df8 + + case OS_DEL_ALWAYS: /* Always delete the semaphore */ + while (pevent->OSEventGrp != 0) { /* Ready ALL tasks waiting for semaphore */ + (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_SEM, OS_STAT_PEND_OK); + 1012d34: e13ffb17 ldw r4,-20(fp) + 1012d38: 000b883a mov r5,zero + 1012d3c: 01800044 movi r6,1 + 1012d40: 000f883a mov r7,zero + 1012d44: 100e2780 call 100e278 + pevent_return = pevent; + } + break; + + case OS_DEL_ALWAYS: /* Always delete the semaphore */ + while (pevent->OSEventGrp != 0) { /* Ready ALL tasks waiting for semaphore */ + 1012d48: e0bffb17 ldw r2,-20(fp) + 1012d4c: 10800283 ldbu r2,10(r2) + 1012d50: 10803fcc andi r2,r2,255 + 1012d54: 1004c03a cmpne r2,r2,zero + 1012d58: 103ff61e bne r2,zero,1012d34 + (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_SEM, OS_STAT_PEND_OK); + } +#if OS_EVENT_NAME_SIZE > 1 + pevent->OSEventName[0] = '?'; /* Unknown name */ + 1012d5c: e0fffb17 ldw r3,-20(fp) + 1012d60: 00800fc4 movi r2,63 + 1012d64: 18800385 stb r2,14(r3) + pevent->OSEventName[1] = OS_ASCII_NUL; + 1012d68: e0bffb17 ldw r2,-20(fp) + 1012d6c: 100003c5 stb zero,15(r2) +#endif + pevent->OSEventType = OS_EVENT_TYPE_UNUSED; + 1012d70: e0bffb17 ldw r2,-20(fp) + 1012d74: 10000005 stb zero,0(r2) + pevent->OSEventPtr = OSEventFreeList; /* Return Event Control Block to free list */ + 1012d78: 008040b4 movhi r2,258 + 1012d7c: 10b31d04 addi r2,r2,-13196 + 1012d80: 10c00017 ldw r3,0(r2) + 1012d84: e0bffb17 ldw r2,-20(fp) + 1012d88: 10c00115 stw r3,4(r2) + pevent->OSEventCnt = 0; + 1012d8c: e0bffb17 ldw r2,-20(fp) + 1012d90: 1000020d sth zero,8(r2) + OSEventFreeList = pevent; /* Get next free event control block */ + 1012d94: 00c040b4 movhi r3,258 + 1012d98: 18f31d04 addi r3,r3,-13196 + 1012d9c: e0bffb17 ldw r2,-20(fp) + 1012da0: 18800015 stw r2,0(r3) + 1012da4: e0bff817 ldw r2,-32(fp) + 1012da8: e0bff415 stw r2,-48(fp) + 1012dac: e0bff417 ldw r2,-48(fp) + 1012db0: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + if (tasks_waiting == OS_TRUE) { /* Reschedule only if task(s) were waiting */ + 1012db4: e0bffa03 ldbu r2,-24(fp) + 1012db8: 10800058 cmpnei r2,r2,1 + 1012dbc: 1000011e bne r2,zero,1012dc4 + OS_Sched(); /* Find highest priority task ready to run */ + 1012dc0: 100ecb80 call 100ecb8 + } + *perr = OS_ERR_NONE; + 1012dc4: e0bffd17 ldw r2,-12(fp) + 1012dc8: 10000005 stb zero,0(r2) + pevent_return = (OS_EVENT *)0; /* Semaphore has been deleted */ + 1012dcc: e03ff915 stw zero,-28(fp) + break; + 1012dd0: 00000906 br 1012df8 + 1012dd4: e0bff817 ldw r2,-32(fp) + 1012dd8: e0bff315 stw r2,-52(fp) + 1012ddc: e0bff317 ldw r2,-52(fp) + 1012de0: 1001703a wrctl status,r2 + + default: + OS_EXIT_CRITICAL(); + *perr = OS_ERR_INVALID_OPT; + 1012de4: e0fffd17 ldw r3,-12(fp) + 1012de8: 008001c4 movi r2,7 + 1012dec: 18800005 stb r2,0(r3) + pevent_return = pevent; + 1012df0: e0bffb17 ldw r2,-20(fp) + 1012df4: e0bff915 stw r2,-28(fp) + break; + } + return (pevent_return); + 1012df8: e0bff917 ldw r2,-28(fp) + 1012dfc: e0bfff15 stw r2,-4(fp) + 1012e00: e0bfff17 ldw r2,-4(fp) +} + 1012e04: e037883a mov sp,fp + 1012e08: dfc00117 ldw ra,4(sp) + 1012e0c: df000017 ldw fp,0(sp) + 1012e10: dec00204 addi sp,sp,8 + 1012e14: f800283a ret + +01012e18 : +* Returns : none +********************************************************************************************************* +*/ +/*$PAGE*/ +void OSSemPend (OS_EVENT *pevent, INT16U timeout, INT8U *perr) +{ + 1012e18: defff404 addi sp,sp,-48 + 1012e1c: dfc00b15 stw ra,44(sp) + 1012e20: df000a15 stw fp,40(sp) + 1012e24: df000a04 addi fp,sp,40 + 1012e28: e13ffc15 stw r4,-16(fp) + 1012e2c: e1bffe15 stw r6,-8(fp) + 1012e30: e17ffd0d sth r5,-12(fp) +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 1012e34: e03ffb15 stw zero,-20(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + 1012e38: e0bffe17 ldw r2,-8(fp) + 1012e3c: 1005003a cmpeq r2,r2,zero + 1012e40: 10008f1e bne r2,zero,1013080 + return; + } + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + 1012e44: e0bffc17 ldw r2,-16(fp) + 1012e48: 1004c03a cmpne r2,r2,zero + 1012e4c: 1000041e bne r2,zero,1012e60 + *perr = OS_ERR_PEVENT_NULL; + 1012e50: e0fffe17 ldw r3,-8(fp) + 1012e54: 00800104 movi r2,4 + 1012e58: 18800005 stb r2,0(r3) + return; + 1012e5c: 00008806 br 1013080 + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_SEM) { /* Validate event block type */ + 1012e60: e0bffc17 ldw r2,-16(fp) + 1012e64: 10800003 ldbu r2,0(r2) + 1012e68: 10803fcc andi r2,r2,255 + 1012e6c: 108000e0 cmpeqi r2,r2,3 + 1012e70: 1000041e bne r2,zero,1012e84 + *perr = OS_ERR_EVENT_TYPE; + 1012e74: e0fffe17 ldw r3,-8(fp) + 1012e78: 00800044 movi r2,1 + 1012e7c: 18800005 stb r2,0(r3) + return; + 1012e80: 00007f06 br 1013080 + } + if (OSIntNesting > 0) { /* See if called from ISR ... */ + 1012e84: 008040b4 movhi r2,258 + 1012e88: 10b31e04 addi r2,r2,-13192 + 1012e8c: 10800003 ldbu r2,0(r2) + 1012e90: 10803fcc andi r2,r2,255 + 1012e94: 1005003a cmpeq r2,r2,zero + 1012e98: 1000041e bne r2,zero,1012eac + *perr = OS_ERR_PEND_ISR; /* ... can't PEND from an ISR */ + 1012e9c: e0fffe17 ldw r3,-8(fp) + 1012ea0: 00800084 movi r2,2 + 1012ea4: 18800005 stb r2,0(r3) + return; + 1012ea8: 00007506 br 1013080 + } + if (OSLockNesting > 0) { /* See if called with scheduler locked ... */ + 1012eac: 008040b4 movhi r2,258 + 1012eb0: 10b31004 addi r2,r2,-13248 + 1012eb4: 10800003 ldbu r2,0(r2) + 1012eb8: 10803fcc andi r2,r2,255 + 1012ebc: 1005003a cmpeq r2,r2,zero + 1012ec0: 1000041e bne r2,zero,1012ed4 + *perr = OS_ERR_PEND_LOCKED; /* ... can't PEND when locked */ + 1012ec4: e0fffe17 ldw r3,-8(fp) + 1012ec8: 00800344 movi r2,13 + 1012ecc: 18800005 stb r2,0(r3) + return; + 1012ed0: 00006b06 br 1013080 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1012ed4: 0005303a rdctl r2,status + 1012ed8: e0bffa15 stw r2,-24(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1012edc: e0fffa17 ldw r3,-24(fp) + 1012ee0: 00bfff84 movi r2,-2 + 1012ee4: 1884703a and r2,r3,r2 + 1012ee8: 1001703a wrctl status,r2 + + return context; + 1012eec: e0bffa17 ldw r2,-24(fp) + } + OS_ENTER_CRITICAL(); + 1012ef0: e0bffb15 stw r2,-20(fp) + if (pevent->OSEventCnt > 0) { /* If sem. is positive, resource available ... */ + 1012ef4: e0bffc17 ldw r2,-16(fp) + 1012ef8: 1080020b ldhu r2,8(r2) + 1012efc: 10bfffcc andi r2,r2,65535 + 1012f00: 1005003a cmpeq r2,r2,zero + 1012f04: 10000d1e bne r2,zero,1012f3c + pevent->OSEventCnt--; /* ... decrement semaphore only if positive. */ + 1012f08: e0bffc17 ldw r2,-16(fp) + 1012f0c: 1080020b ldhu r2,8(r2) + 1012f10: 10bfffc4 addi r2,r2,-1 + 1012f14: 1007883a mov r3,r2 + 1012f18: e0bffc17 ldw r2,-16(fp) + 1012f1c: 10c0020d sth r3,8(r2) + 1012f20: e0bffb17 ldw r2,-20(fp) + 1012f24: e0bff915 stw r2,-28(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1012f28: e0bff917 ldw r2,-28(fp) + 1012f2c: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + 1012f30: e0bffe17 ldw r2,-8(fp) + 1012f34: 10000005 stb zero,0(r2) + return; + 1012f38: 00005106 br 1013080 + } + /* Otherwise, must wait until event occurs */ + OSTCBCur->OSTCBStat |= OS_STAT_SEM; /* Resource not available, pend on semaphore */ + 1012f3c: 008040b4 movhi r2,258 + 1012f40: 10b31f04 addi r2,r2,-13188 + 1012f44: 10c00017 ldw r3,0(r2) + 1012f48: 008040b4 movhi r2,258 + 1012f4c: 10b31f04 addi r2,r2,-13188 + 1012f50: 10800017 ldw r2,0(r2) + 1012f54: 10800c03 ldbu r2,48(r2) + 1012f58: 10800054 ori r2,r2,1 + 1012f5c: 18800c05 stb r2,48(r3) + OSTCBCur->OSTCBStatPend = OS_STAT_PEND_OK; + 1012f60: 008040b4 movhi r2,258 + 1012f64: 10b31f04 addi r2,r2,-13188 + 1012f68: 10800017 ldw r2,0(r2) + 1012f6c: 10000c45 stb zero,49(r2) + OSTCBCur->OSTCBDly = timeout; /* Store pend timeout in TCB */ + 1012f70: 008040b4 movhi r2,258 + 1012f74: 10b31f04 addi r2,r2,-13188 + 1012f78: 10c00017 ldw r3,0(r2) + 1012f7c: e0bffd0b ldhu r2,-12(fp) + 1012f80: 18800b8d sth r2,46(r3) + OS_EventTaskWait(pevent); /* Suspend task until event or timeout occurs */ + 1012f84: e13ffc17 ldw r4,-16(fp) + 1012f88: 100e40c0 call 100e40c + 1012f8c: e0bffb17 ldw r2,-20(fp) + 1012f90: e0bff815 stw r2,-32(fp) + 1012f94: e0bff817 ldw r2,-32(fp) + 1012f98: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + OS_Sched(); /* Find next highest priority task ready */ + 1012f9c: 100ecb80 call 100ecb8 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1012fa0: 0005303a rdctl r2,status + 1012fa4: e0bff715 stw r2,-36(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1012fa8: e0fff717 ldw r3,-36(fp) + 1012fac: 00bfff84 movi r2,-2 + 1012fb0: 1884703a and r2,r3,r2 + 1012fb4: 1001703a wrctl status,r2 + + return context; + 1012fb8: e0bff717 ldw r2,-36(fp) + OS_ENTER_CRITICAL(); + 1012fbc: e0bffb15 stw r2,-20(fp) + switch (OSTCBCur->OSTCBStatPend) { /* See if we timed-out or aborted */ + 1012fc0: 008040b4 movhi r2,258 + 1012fc4: 10b31f04 addi r2,r2,-13188 + 1012fc8: 10800017 ldw r2,0(r2) + 1012fcc: 10800c43 ldbu r2,49(r2) + 1012fd0: 10803fcc andi r2,r2,255 + 1012fd4: e0bfff15 stw r2,-4(fp) + 1012fd8: e0ffff17 ldw r3,-4(fp) + 1012fdc: 1805003a cmpeq r2,r3,zero + 1012fe0: 1000041e bne r2,zero,1012ff4 + 1012fe4: e0ffff17 ldw r3,-4(fp) + 1012fe8: 188000a0 cmpeqi r2,r3,2 + 1012fec: 1000041e bne r2,zero,1013000 + 1012ff0: 00000706 br 1013010 + case OS_STAT_PEND_OK: + *perr = OS_ERR_NONE; + 1012ff4: e0bffe17 ldw r2,-8(fp) + 1012ff8: 10000005 stb zero,0(r2) + break; + 1012ffc: 00000c06 br 1013030 + + case OS_STAT_PEND_ABORT: + *perr = OS_ERR_PEND_ABORT; /* Indicate that we aborted */ + 1013000: e0fffe17 ldw r3,-8(fp) + 1013004: 00800384 movi r2,14 + 1013008: 18800005 stb r2,0(r3) + break; + 101300c: 00000806 br 1013030 + + case OS_STAT_PEND_TO: + default: + OS_EventTaskRemove(OSTCBCur, pevent); + 1013010: 008040b4 movhi r2,258 + 1013014: 10b31f04 addi r2,r2,-13188 + 1013018: 11000017 ldw r4,0(r2) + 101301c: e17ffc17 ldw r5,-16(fp) + 1013020: 100e6700 call 100e670 + *perr = OS_ERR_TIMEOUT; /* Indicate that we didn't get event within TO */ + 1013024: e0fffe17 ldw r3,-8(fp) + 1013028: 00800284 movi r2,10 + 101302c: 18800005 stb r2,0(r3) + break; + } + OSTCBCur->OSTCBStat = OS_STAT_RDY; /* Set task status to ready */ + 1013030: 008040b4 movhi r2,258 + 1013034: 10b31f04 addi r2,r2,-13188 + 1013038: 10800017 ldw r2,0(r2) + 101303c: 10000c05 stb zero,48(r2) + OSTCBCur->OSTCBStatPend = OS_STAT_PEND_OK; /* Clear pend status */ + 1013040: 008040b4 movhi r2,258 + 1013044: 10b31f04 addi r2,r2,-13188 + 1013048: 10800017 ldw r2,0(r2) + 101304c: 10000c45 stb zero,49(r2) + OSTCBCur->OSTCBEventPtr = (OS_EVENT *)0; /* Clear event pointers */ + 1013050: 008040b4 movhi r2,258 + 1013054: 10b31f04 addi r2,r2,-13188 + 1013058: 10800017 ldw r2,0(r2) + 101305c: 10000715 stw zero,28(r2) +#if (OS_EVENT_MULTI_EN > 0) + OSTCBCur->OSTCBEventMultiPtr = (OS_EVENT **)0; + 1013060: 008040b4 movhi r2,258 + 1013064: 10b31f04 addi r2,r2,-13188 + 1013068: 10800017 ldw r2,0(r2) + 101306c: 10000815 stw zero,32(r2) + 1013070: e0bffb17 ldw r2,-20(fp) + 1013074: e0bff615 stw r2,-40(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1013078: e0bff617 ldw r2,-40(fp) + 101307c: 1001703a wrctl status,r2 +#endif + OS_EXIT_CRITICAL(); +} + 1013080: e037883a mov sp,fp + 1013084: dfc00117 ldw ra,4(sp) + 1013088: df000017 ldw fp,0(sp) + 101308c: dec00204 addi sp,sp,8 + 1013090: f800283a ret + +01013094 : +********************************************************************************************************* +*/ + +#if OS_SEM_PEND_ABORT_EN > 0 +INT8U OSSemPendAbort (OS_EVENT *pevent, INT8U opt, INT8U *perr) +{ + 1013094: defff504 addi sp,sp,-44 + 1013098: dfc00a15 stw ra,40(sp) + 101309c: df000915 stw fp,36(sp) + 10130a0: df000904 addi fp,sp,36 + 10130a4: e13ffc15 stw r4,-16(fp) + 10130a8: e1bffe15 stw r6,-8(fp) + 10130ac: e17ffd05 stb r5,-12(fp) + INT8U nbr_tasks; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 10130b0: e03ffa15 stw zero,-24(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + 10130b4: e0bffe17 ldw r2,-8(fp) + 10130b8: 1004c03a cmpne r2,r2,zero + 10130bc: 1000021e bne r2,zero,10130c8 + return (0); + 10130c0: e03fff15 stw zero,-4(fp) + 10130c4: 00004c06 br 10131f8 + } + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + 10130c8: e0bffc17 ldw r2,-16(fp) + 10130cc: 1004c03a cmpne r2,r2,zero + 10130d0: 1000051e bne r2,zero,10130e8 + *perr = OS_ERR_PEVENT_NULL; + 10130d4: e0fffe17 ldw r3,-8(fp) + 10130d8: 00800104 movi r2,4 + 10130dc: 18800005 stb r2,0(r3) + return (0); + 10130e0: e03fff15 stw zero,-4(fp) + 10130e4: 00004406 br 10131f8 + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_SEM) { /* Validate event block type */ + 10130e8: e0bffc17 ldw r2,-16(fp) + 10130ec: 10800003 ldbu r2,0(r2) + 10130f0: 10803fcc andi r2,r2,255 + 10130f4: 108000e0 cmpeqi r2,r2,3 + 10130f8: 1000051e bne r2,zero,1013110 + *perr = OS_ERR_EVENT_TYPE; + 10130fc: e0fffe17 ldw r3,-8(fp) + 1013100: 00800044 movi r2,1 + 1013104: 18800005 stb r2,0(r3) + return (0); + 1013108: e03fff15 stw zero,-4(fp) + 101310c: 00003a06 br 10131f8 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1013110: 0005303a rdctl r2,status + 1013114: e0bff915 stw r2,-28(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1013118: e0fff917 ldw r3,-28(fp) + 101311c: 00bfff84 movi r2,-2 + 1013120: 1884703a and r2,r3,r2 + 1013124: 1001703a wrctl status,r2 + + return context; + 1013128: e0bff917 ldw r2,-28(fp) + } + OS_ENTER_CRITICAL(); + 101312c: e0bffa15 stw r2,-24(fp) + if (pevent->OSEventGrp != 0) { /* See if any task waiting on semaphore? */ + 1013130: e0bffc17 ldw r2,-16(fp) + 1013134: 10800283 ldbu r2,10(r2) + 1013138: 10803fcc andi r2,r2,255 + 101313c: 1005003a cmpeq r2,r2,zero + 1013140: 1000261e bne r2,zero,10131dc + nbr_tasks = 0; + 1013144: e03ffb05 stb zero,-20(fp) + switch (opt) { + 1013148: e0bffd03 ldbu r2,-12(fp) + 101314c: 10800060 cmpeqi r2,r2,1 + 1013150: 1000091e bne r2,zero,1013178 + 1013154: 00000e06 br 1013190 + case OS_PEND_OPT_BROADCAST: /* Do we need to abort ALL waiting tasks? */ + while (pevent->OSEventGrp != 0) { /* Yes, ready ALL tasks waiting on semaphore */ + (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_SEM, OS_STAT_PEND_ABORT); + 1013158: e13ffc17 ldw r4,-16(fp) + 101315c: 000b883a mov r5,zero + 1013160: 01800044 movi r6,1 + 1013164: 01c00084 movi r7,2 + 1013168: 100e2780 call 100e278 + nbr_tasks++; + 101316c: e0bffb03 ldbu r2,-20(fp) + 1013170: 10800044 addi r2,r2,1 + 1013174: e0bffb05 stb r2,-20(fp) + OS_ENTER_CRITICAL(); + if (pevent->OSEventGrp != 0) { /* See if any task waiting on semaphore? */ + nbr_tasks = 0; + switch (opt) { + case OS_PEND_OPT_BROADCAST: /* Do we need to abort ALL waiting tasks? */ + while (pevent->OSEventGrp != 0) { /* Yes, ready ALL tasks waiting on semaphore */ + 1013178: e0bffc17 ldw r2,-16(fp) + 101317c: 10800283 ldbu r2,10(r2) + 1013180: 10803fcc andi r2,r2,255 + 1013184: 1004c03a cmpne r2,r2,zero + 1013188: 103ff31e bne r2,zero,1013158 + (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_SEM, OS_STAT_PEND_ABORT); + nbr_tasks++; + } + break; + 101318c: 00000806 br 10131b0 + + case OS_PEND_OPT_NONE: + default: /* No, ready HPT waiting on semaphore */ + (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_SEM, OS_STAT_PEND_ABORT); + 1013190: e13ffc17 ldw r4,-16(fp) + 1013194: 000b883a mov r5,zero + 1013198: 01800044 movi r6,1 + 101319c: 01c00084 movi r7,2 + 10131a0: 100e2780 call 100e278 + nbr_tasks++; + 10131a4: e0bffb03 ldbu r2,-20(fp) + 10131a8: 10800044 addi r2,r2,1 + 10131ac: e0bffb05 stb r2,-20(fp) + 10131b0: e0bffa17 ldw r2,-24(fp) + 10131b4: e0bff815 stw r2,-32(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 10131b8: e0bff817 ldw r2,-32(fp) + 10131bc: 1001703a wrctl status,r2 + break; + } + OS_EXIT_CRITICAL(); + OS_Sched(); /* Find HPT ready to run */ + 10131c0: 100ecb80 call 100ecb8 + *perr = OS_ERR_PEND_ABORT; + 10131c4: e0fffe17 ldw r3,-8(fp) + 10131c8: 00800384 movi r2,14 + 10131cc: 18800005 stb r2,0(r3) + return (nbr_tasks); + 10131d0: e0bffb03 ldbu r2,-20(fp) + 10131d4: e0bfff15 stw r2,-4(fp) + 10131d8: 00000706 br 10131f8 + 10131dc: e0bffa17 ldw r2,-24(fp) + 10131e0: e0bff715 stw r2,-36(fp) + 10131e4: e0bff717 ldw r2,-36(fp) + 10131e8: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + 10131ec: e0bffe17 ldw r2,-8(fp) + 10131f0: 10000005 stb zero,0(r2) + return (0); /* No tasks waiting on semaphore */ + 10131f4: e03fff15 stw zero,-4(fp) + 10131f8: e0bfff17 ldw r2,-4(fp) +} + 10131fc: e037883a mov sp,fp + 1013200: dfc00117 ldw ra,4(sp) + 1013204: df000017 ldw fp,0(sp) + 1013208: dec00204 addi sp,sp,8 + 101320c: f800283a ret + +01013210 : +* OS_ERR_PEVENT_NULL If 'pevent' is a NULL pointer. +********************************************************************************************************* +*/ + +INT8U OSSemPost (OS_EVENT *pevent) +{ + 1013210: defff704 addi sp,sp,-36 + 1013214: dfc00815 stw ra,32(sp) + 1013218: df000715 stw fp,28(sp) + 101321c: df000704 addi fp,sp,28 + 1013220: e13ffe15 stw r4,-8(fp) +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 1013224: e03ffd15 stw zero,-12(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + 1013228: e0bffe17 ldw r2,-8(fp) + 101322c: 1004c03a cmpne r2,r2,zero + 1013230: 1000031e bne r2,zero,1013240 + return (OS_ERR_PEVENT_NULL); + 1013234: 00800104 movi r2,4 + 1013238: e0bfff15 stw r2,-4(fp) + 101323c: 00003806 br 1013320 + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_SEM) { /* Validate event block type */ + 1013240: e0bffe17 ldw r2,-8(fp) + 1013244: 10800003 ldbu r2,0(r2) + 1013248: 10803fcc andi r2,r2,255 + 101324c: 108000e0 cmpeqi r2,r2,3 + 1013250: 1000031e bne r2,zero,1013260 + return (OS_ERR_EVENT_TYPE); + 1013254: 00800044 movi r2,1 + 1013258: e0bfff15 stw r2,-4(fp) + 101325c: 00003006 br 1013320 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1013260: 0005303a rdctl r2,status + 1013264: e0bffc15 stw r2,-16(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1013268: e0fffc17 ldw r3,-16(fp) + 101326c: 00bfff84 movi r2,-2 + 1013270: 1884703a and r2,r3,r2 + 1013274: 1001703a wrctl status,r2 + + return context; + 1013278: e0bffc17 ldw r2,-16(fp) + } + OS_ENTER_CRITICAL(); + 101327c: e0bffd15 stw r2,-12(fp) + if (pevent->OSEventGrp != 0) { /* See if any task waiting for semaphore */ + 1013280: e0bffe17 ldw r2,-8(fp) + 1013284: 10800283 ldbu r2,10(r2) + 1013288: 10803fcc andi r2,r2,255 + 101328c: 1005003a cmpeq r2,r2,zero + 1013290: 10000c1e bne r2,zero,10132c4 + /* Ready HPT waiting on event */ + (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_SEM, OS_STAT_PEND_OK); + 1013294: e13ffe17 ldw r4,-8(fp) + 1013298: 000b883a mov r5,zero + 101329c: 01800044 movi r6,1 + 10132a0: 000f883a mov r7,zero + 10132a4: 100e2780 call 100e278 + 10132a8: e0bffd17 ldw r2,-12(fp) + 10132ac: e0bffb15 stw r2,-20(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 10132b0: e0bffb17 ldw r2,-20(fp) + 10132b4: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + OS_Sched(); /* Find HPT ready to run */ + 10132b8: 100ecb80 call 100ecb8 + return (OS_ERR_NONE); + 10132bc: e03fff15 stw zero,-4(fp) + 10132c0: 00001706 br 1013320 + } + if (pevent->OSEventCnt < 65535u) { /* Make sure semaphore will not overflow */ + 10132c4: e0bffe17 ldw r2,-8(fp) + 10132c8: 1080020b ldhu r2,8(r2) + 10132cc: 10ffffcc andi r3,r2,65535 + 10132d0: 00bfffd4 movui r2,65535 + 10132d4: 18800c26 beq r3,r2,1013308 + pevent->OSEventCnt++; /* Increment semaphore count to register event */ + 10132d8: e0bffe17 ldw r2,-8(fp) + 10132dc: 1080020b ldhu r2,8(r2) + 10132e0: 10800044 addi r2,r2,1 + 10132e4: 1007883a mov r3,r2 + 10132e8: e0bffe17 ldw r2,-8(fp) + 10132ec: 10c0020d sth r3,8(r2) + 10132f0: e0bffd17 ldw r2,-12(fp) + 10132f4: e0bffa15 stw r2,-24(fp) + 10132f8: e0bffa17 ldw r2,-24(fp) + 10132fc: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_NONE); + 1013300: e03fff15 stw zero,-4(fp) + 1013304: 00000606 br 1013320 + 1013308: e0bffd17 ldw r2,-12(fp) + 101330c: e0bff915 stw r2,-28(fp) + 1013310: e0bff917 ldw r2,-28(fp) + 1013314: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); /* Semaphore value has reached its maximum */ + return (OS_ERR_SEM_OVF); + 1013318: 00800c84 movi r2,50 + 101331c: e0bfff15 stw r2,-4(fp) + 1013320: e0bfff17 ldw r2,-4(fp) +} + 1013324: e037883a mov sp,fp + 1013328: dfc00117 ldw ra,4(sp) + 101332c: df000017 ldw fp,0(sp) + 1013330: dec00204 addi sp,sp,8 + 1013334: f800283a ret + +01013338 : +********************************************************************************************************* +*/ + +#if OS_SEM_QUERY_EN > 0 +INT8U OSSemQuery (OS_EVENT *pevent, OS_SEM_DATA *p_sem_data) +{ + 1013338: defff604 addi sp,sp,-40 + 101333c: df000915 stw fp,36(sp) + 1013340: df000904 addi fp,sp,36 + 1013344: e13ffd15 stw r4,-12(fp) + 1013348: e17ffe15 stw r5,-8(fp) + INT16U *psrc; + INT16U *pdest; +#endif + INT8U i; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 101334c: e03ff915 stw zero,-28(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + 1013350: e0bffd17 ldw r2,-12(fp) + 1013354: 1004c03a cmpne r2,r2,zero + 1013358: 1000031e bne r2,zero,1013368 + return (OS_ERR_PEVENT_NULL); + 101335c: 00800104 movi r2,4 + 1013360: e0bfff15 stw r2,-4(fp) + 1013364: 00003b06 br 1013454 + } + if (p_sem_data == (OS_SEM_DATA *)0) { /* Validate 'p_sem_data' */ + 1013368: e0bffe17 ldw r2,-8(fp) + 101336c: 1004c03a cmpne r2,r2,zero + 1013370: 1000031e bne r2,zero,1013380 + return (OS_ERR_PDATA_NULL); + 1013374: 00800244 movi r2,9 + 1013378: e0bfff15 stw r2,-4(fp) + 101337c: 00003506 br 1013454 + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_SEM) { /* Validate event block type */ + 1013380: e0bffd17 ldw r2,-12(fp) + 1013384: 10800003 ldbu r2,0(r2) + 1013388: 10803fcc andi r2,r2,255 + 101338c: 108000e0 cmpeqi r2,r2,3 + 1013390: 1000031e bne r2,zero,10133a0 + return (OS_ERR_EVENT_TYPE); + 1013394: 00800044 movi r2,1 + 1013398: e0bfff15 stw r2,-4(fp) + 101339c: 00002d06 br 1013454 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 10133a0: 0005303a rdctl r2,status + 10133a4: e0bff815 stw r2,-32(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 10133a8: e0fff817 ldw r3,-32(fp) + 10133ac: 00bfff84 movi r2,-2 + 10133b0: 1884703a and r2,r3,r2 + 10133b4: 1001703a wrctl status,r2 + + return context; + 10133b8: e0bff817 ldw r2,-32(fp) + } + OS_ENTER_CRITICAL(); + 10133bc: e0bff915 stw r2,-28(fp) + p_sem_data->OSEventGrp = pevent->OSEventGrp; /* Copy message mailbox wait list */ + 10133c0: e0bffd17 ldw r2,-12(fp) + 10133c4: 10c00283 ldbu r3,10(r2) + 10133c8: e0bffe17 ldw r2,-8(fp) + 10133cc: 10c00145 stb r3,5(r2) + psrc = &pevent->OSEventTbl[0]; + 10133d0: e0bffd17 ldw r2,-12(fp) + 10133d4: 108002c4 addi r2,r2,11 + 10133d8: e0bffc15 stw r2,-16(fp) + pdest = &p_sem_data->OSEventTbl[0]; + 10133dc: e0bffe17 ldw r2,-8(fp) + 10133e0: 10800084 addi r2,r2,2 + 10133e4: e0bffb15 stw r2,-20(fp) + for (i = 0; i < OS_EVENT_TBL_SIZE; i++) { + 10133e8: e03ffa05 stb zero,-24(fp) + 10133ec: 00000d06 br 1013424 + *pdest++ = *psrc++; + 10133f0: e0bffc17 ldw r2,-16(fp) + 10133f4: 10c00003 ldbu r3,0(r2) + 10133f8: e0bffb17 ldw r2,-20(fp) + 10133fc: 10c00005 stb r3,0(r2) + 1013400: e0bffb17 ldw r2,-20(fp) + 1013404: 10800044 addi r2,r2,1 + 1013408: e0bffb15 stw r2,-20(fp) + 101340c: e0bffc17 ldw r2,-16(fp) + 1013410: 10800044 addi r2,r2,1 + 1013414: e0bffc15 stw r2,-16(fp) + } + OS_ENTER_CRITICAL(); + p_sem_data->OSEventGrp = pevent->OSEventGrp; /* Copy message mailbox wait list */ + psrc = &pevent->OSEventTbl[0]; + pdest = &p_sem_data->OSEventTbl[0]; + for (i = 0; i < OS_EVENT_TBL_SIZE; i++) { + 1013418: e0bffa03 ldbu r2,-24(fp) + 101341c: 10800044 addi r2,r2,1 + 1013420: e0bffa05 stb r2,-24(fp) + 1013424: e0bffa03 ldbu r2,-24(fp) + 1013428: 108000f0 cmpltui r2,r2,3 + 101342c: 103ff01e bne r2,zero,10133f0 + *pdest++ = *psrc++; + } + p_sem_data->OSCnt = pevent->OSEventCnt; /* Get semaphore count */ + 1013430: e0bffd17 ldw r2,-12(fp) + 1013434: 10c0020b ldhu r3,8(r2) + 1013438: e0bffe17 ldw r2,-8(fp) + 101343c: 10c0000d sth r3,0(r2) + 1013440: e0bff917 ldw r2,-28(fp) + 1013444: e0bff715 stw r2,-36(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1013448: e0bff717 ldw r2,-36(fp) + 101344c: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_NONE); + 1013450: e03fff15 stw zero,-4(fp) + 1013454: e0bfff17 ldw r2,-4(fp) +} + 1013458: e037883a mov sp,fp + 101345c: df000017 ldw fp,0(sp) + 1013460: dec00104 addi sp,sp,4 + 1013464: f800283a ret + +01013468 : +********************************************************************************************************* +*/ + +#if OS_SEM_SET_EN > 0 +void OSSemSet (OS_EVENT *pevent, INT16U cnt, INT8U *perr) +{ + 1013468: defff904 addi sp,sp,-28 + 101346c: df000615 stw fp,24(sp) + 1013470: df000604 addi fp,sp,24 + 1013474: e13ffd15 stw r4,-12(fp) + 1013478: e1bfff15 stw r6,-4(fp) + 101347c: e17ffe0d sth r5,-8(fp) +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 1013480: e03ffc15 stw zero,-16(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + 1013484: e0bfff17 ldw r2,-4(fp) + 1013488: 1005003a cmpeq r2,r2,zero + 101348c: 1000331e bne r2,zero,101355c + return; + } + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + 1013490: e0bffd17 ldw r2,-12(fp) + 1013494: 1004c03a cmpne r2,r2,zero + 1013498: 1000041e bne r2,zero,10134ac + *perr = OS_ERR_PEVENT_NULL; + 101349c: e0ffff17 ldw r3,-4(fp) + 10134a0: 00800104 movi r2,4 + 10134a4: 18800005 stb r2,0(r3) + return; + 10134a8: 00002c06 br 101355c + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_SEM) { /* Validate event block type */ + 10134ac: e0bffd17 ldw r2,-12(fp) + 10134b0: 10800003 ldbu r2,0(r2) + 10134b4: 10803fcc andi r2,r2,255 + 10134b8: 108000e0 cmpeqi r2,r2,3 + 10134bc: 1000041e bne r2,zero,10134d0 + *perr = OS_ERR_EVENT_TYPE; + 10134c0: e0ffff17 ldw r3,-4(fp) + 10134c4: 00800044 movi r2,1 + 10134c8: 18800005 stb r2,0(r3) + return; + 10134cc: 00002306 br 101355c +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 10134d0: 0005303a rdctl r2,status + 10134d4: e0bffb15 stw r2,-20(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 10134d8: e0fffb17 ldw r3,-20(fp) + 10134dc: 00bfff84 movi r2,-2 + 10134e0: 1884703a and r2,r3,r2 + 10134e4: 1001703a wrctl status,r2 + + return context; + 10134e8: e0bffb17 ldw r2,-20(fp) + } + OS_ENTER_CRITICAL(); + 10134ec: e0bffc15 stw r2,-16(fp) + *perr = OS_ERR_NONE; + 10134f0: e0bfff17 ldw r2,-4(fp) + 10134f4: 10000005 stb zero,0(r2) + if (pevent->OSEventCnt > 0) { /* See if semaphore already has a count */ + 10134f8: e0bffd17 ldw r2,-12(fp) + 10134fc: 1080020b ldhu r2,8(r2) + 1013500: 10bfffcc andi r2,r2,65535 + 1013504: 1005003a cmpeq r2,r2,zero + 1013508: 1000041e bne r2,zero,101351c + pevent->OSEventCnt = cnt; /* Yes, set it to the new value specified. */ + 101350c: e0fffd17 ldw r3,-12(fp) + 1013510: e0bffe0b ldhu r2,-8(fp) + 1013514: 1880020d sth r2,8(r3) + 1013518: 00000c06 br 101354c + } else { /* No */ + if (pevent->OSEventGrp == 0) { /* See if task(s) waiting? */ + 101351c: e0bffd17 ldw r2,-12(fp) + 1013520: 10800283 ldbu r2,10(r2) + 1013524: 10803fcc andi r2,r2,255 + 1013528: 1004c03a cmpne r2,r2,zero + 101352c: 1000041e bne r2,zero,1013540 + pevent->OSEventCnt = cnt; /* No, OK to set the value */ + 1013530: e0fffd17 ldw r3,-12(fp) + 1013534: e0bffe0b ldhu r2,-8(fp) + 1013538: 1880020d sth r2,8(r3) + 101353c: 00000306 br 101354c + } else { + *perr = OS_ERR_TASK_WAITING; + 1013540: e0ffff17 ldw r3,-4(fp) + 1013544: 00801244 movi r2,73 + 1013548: 18800005 stb r2,0(r3) + 101354c: e0bffc17 ldw r2,-16(fp) + 1013550: e0bffa15 stw r2,-24(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1013554: e0bffa17 ldw r2,-24(fp) + 1013558: 1001703a wrctl status,r2 + } + } + OS_EXIT_CRITICAL(); +} + 101355c: e037883a mov sp,fp + 1013560: df000017 ldw fp,0(sp) + 1013564: dec00104 addi sp,sp,4 + 1013568: f800283a ret + +0101356c : +********************************************************************************************************* +*/ + +#if OS_TASK_CHANGE_PRIO_EN > 0 +INT8U OSTaskChangePrio (INT8U oldprio, INT8U newprio) +{ + 101356c: defff004 addi sp,sp,-64 + 1013570: dfc00f15 stw ra,60(sp) + 1013574: df000e15 stw fp,56(sp) + 1013578: df000e04 addi fp,sp,56 + 101357c: e13ffd05 stb r4,-12(fp) + 1013580: e17ffe05 stb r5,-8(fp) + INT16U bitx_new; + INT16U bity_old; + INT16U bitx_old; +#endif +#if OS_CRITICAL_METHOD == 3 + OS_CPU_SR cpu_sr = 0; /* Storage for CPU status register */ + 1013584: e03ff715 stw zero,-36(fp) +#endif + + +/*$PAGE*/ +#if OS_ARG_CHK_EN > 0 + if (oldprio >= OS_LOWEST_PRIO) { + 1013588: e0bffd03 ldbu r2,-12(fp) + 101358c: 10800530 cmpltui r2,r2,20 + 1013590: 1000061e bne r2,zero,10135ac + if (oldprio != OS_PRIO_SELF) { + 1013594: e0bffd03 ldbu r2,-12(fp) + 1013598: 10803fe0 cmpeqi r2,r2,255 + 101359c: 1000031e bne r2,zero,10135ac + return (OS_ERR_PRIO_INVALID); + 10135a0: 00800a84 movi r2,42 + 10135a4: e0bfff15 stw r2,-4(fp) + 10135a8: 00014706 br 1013ac8 + } + } + if (newprio >= OS_LOWEST_PRIO) { + 10135ac: e0bffe03 ldbu r2,-8(fp) + 10135b0: 10800530 cmpltui r2,r2,20 + 10135b4: 1000031e bne r2,zero,10135c4 + return (OS_ERR_PRIO_INVALID); + 10135b8: 00800a84 movi r2,42 + 10135bc: e0bfff15 stw r2,-4(fp) + 10135c0: 00014106 br 1013ac8 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 10135c4: 0005303a rdctl r2,status + 10135c8: e0bff615 stw r2,-40(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 10135cc: e0fff617 ldw r3,-40(fp) + 10135d0: 00bfff84 movi r2,-2 + 10135d4: 1884703a and r2,r3,r2 + 10135d8: 1001703a wrctl status,r2 + + return context; + 10135dc: e0bff617 ldw r2,-40(fp) + } +#endif + OS_ENTER_CRITICAL(); + 10135e0: e0bff715 stw r2,-36(fp) + if (OSTCBPrioTbl[newprio] != (OS_TCB *)0) { /* New priority must not already exist */ + 10135e4: e0bffe03 ldbu r2,-8(fp) + 10135e8: 00c040b4 movhi r3,258 + 10135ec: 18d9a904 addi r3,r3,26276 + 10135f0: 1085883a add r2,r2,r2 + 10135f4: 1085883a add r2,r2,r2 + 10135f8: 10c5883a add r2,r2,r3 + 10135fc: 10800017 ldw r2,0(r2) + 1013600: 1005003a cmpeq r2,r2,zero + 1013604: 1000071e bne r2,zero,1013624 + 1013608: e0bff717 ldw r2,-36(fp) + 101360c: e0bff515 stw r2,-44(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1013610: e0bff517 ldw r2,-44(fp) + 1013614: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_PRIO_EXIST); + 1013618: 00800a04 movi r2,40 + 101361c: e0bfff15 stw r2,-4(fp) + 1013620: 00012906 br 1013ac8 + } + if (oldprio == OS_PRIO_SELF) { /* See if changing self */ + 1013624: e0bffd03 ldbu r2,-12(fp) + 1013628: 10803fd8 cmpnei r2,r2,255 + 101362c: 1000051e bne r2,zero,1013644 + oldprio = OSTCBCur->OSTCBPrio; /* Yes, get priority */ + 1013630: 008040b4 movhi r2,258 + 1013634: 10b31f04 addi r2,r2,-13188 + 1013638: 10800017 ldw r2,0(r2) + 101363c: 10800c83 ldbu r2,50(r2) + 1013640: e0bffd05 stb r2,-12(fp) + } + ptcb = OSTCBPrioTbl[oldprio]; + 1013644: e0bffd03 ldbu r2,-12(fp) + 1013648: 00c040b4 movhi r3,258 + 101364c: 18d9a904 addi r3,r3,26276 + 1013650: 1085883a add r2,r2,r2 + 1013654: 1085883a add r2,r2,r2 + 1013658: 10c5883a add r2,r2,r3 + 101365c: 10800017 ldw r2,0(r2) + 1013660: e0bffa15 stw r2,-24(fp) + if (ptcb == (OS_TCB *)0) { /* Does task to change exist? */ + 1013664: e0bffa17 ldw r2,-24(fp) + 1013668: 1004c03a cmpne r2,r2,zero + 101366c: 1000071e bne r2,zero,101368c + 1013670: e0bff717 ldw r2,-36(fp) + 1013674: e0bff415 stw r2,-48(fp) + 1013678: e0bff417 ldw r2,-48(fp) + 101367c: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); /* No, can't change its priority! */ + return (OS_ERR_PRIO); + 1013680: 00800a44 movi r2,41 + 1013684: e0bfff15 stw r2,-4(fp) + 1013688: 00010f06 br 1013ac8 + } + if (ptcb == OS_TCB_RESERVED) { /* Is task assigned to Mutex */ + 101368c: e0bffa17 ldw r2,-24(fp) + 1013690: 10800058 cmpnei r2,r2,1 + 1013694: 1000071e bne r2,zero,10136b4 + 1013698: e0bff717 ldw r2,-36(fp) + 101369c: e0bff315 stw r2,-52(fp) + 10136a0: e0bff317 ldw r2,-52(fp) + 10136a4: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); /* No, can't change its priority! */ + return (OS_ERR_TASK_NOT_EXIST); + 10136a8: 008010c4 movi r2,67 + 10136ac: e0bfff15 stw r2,-4(fp) + 10136b0: 00010506 br 1013ac8 + } +#if OS_LOWEST_PRIO <= 63 + y_new = (INT8U)(newprio >> 3); /* Yes, compute new TCB fields */ + 10136b4: e0bffe03 ldbu r2,-8(fp) + 10136b8: 1004d0fa srli r2,r2,3 + 10136bc: e0bff985 stb r2,-26(fp) + x_new = (INT8U)(newprio & 0x07); + 10136c0: e0bffe03 ldbu r2,-8(fp) + 10136c4: 108001cc andi r2,r2,7 + 10136c8: e0bff945 stb r2,-27(fp) + bity_new = (INT8U)(1 << y_new); + 10136cc: e0fff983 ldbu r3,-26(fp) + 10136d0: 00800044 movi r2,1 + 10136d4: 10c4983a sll r2,r2,r3 + 10136d8: e0bff8c5 stb r2,-29(fp) + bitx_new = (INT8U)(1 << x_new); + 10136dc: e0fff943 ldbu r3,-27(fp) + 10136e0: 00800044 movi r2,1 + 10136e4: 10c4983a sll r2,r2,r3 + 10136e8: e0bff885 stb r2,-30(fp) + x_new = (INT8U)( newprio & 0x0F); + bity_new = (INT16U)(1 << y_new); + bitx_new = (INT16U)(1 << x_new); +#endif + + OSTCBPrioTbl[oldprio] = (OS_TCB *)0; /* Remove TCB from old priority */ + 10136ec: e0bffd03 ldbu r2,-12(fp) + 10136f0: 00c040b4 movhi r3,258 + 10136f4: 18d9a904 addi r3,r3,26276 + 10136f8: 1085883a add r2,r2,r2 + 10136fc: 1085883a add r2,r2,r2 + 1013700: 10c5883a add r2,r2,r3 + 1013704: 10000015 stw zero,0(r2) + OSTCBPrioTbl[newprio] = ptcb; /* Place pointer to TCB @ new priority */ + 1013708: e0bffe03 ldbu r2,-8(fp) + 101370c: 00c040b4 movhi r3,258 + 1013710: 18d9a904 addi r3,r3,26276 + 1013714: 1085883a add r2,r2,r2 + 1013718: 1085883a add r2,r2,r2 + 101371c: 10c7883a add r3,r2,r3 + 1013720: e0bffa17 ldw r2,-24(fp) + 1013724: 18800015 stw r2,0(r3) + y_old = ptcb->OSTCBY; + 1013728: e0bffa17 ldw r2,-24(fp) + 101372c: 10800d03 ldbu r2,52(r2) + 1013730: e0bff905 stb r2,-28(fp) + bity_old = ptcb->OSTCBBitY; + 1013734: e0bffa17 ldw r2,-24(fp) + 1013738: 10800d83 ldbu r2,54(r2) + 101373c: e0bff845 stb r2,-31(fp) + bitx_old = ptcb->OSTCBBitX; + 1013740: e0bffa17 ldw r2,-24(fp) + 1013744: 10800d43 ldbu r2,53(r2) + 1013748: e0bff805 stb r2,-32(fp) + if ((OSRdyTbl[y_old] & bitx_old) != 0) { /* If task is ready make it not */ + 101374c: e0fff903 ldbu r3,-28(fp) + 1013750: 008040b4 movhi r2,258 + 1013754: 10b31c44 addi r2,r2,-13199 + 1013758: 10c5883a add r2,r2,r3 + 101375c: 10c00003 ldbu r3,0(r2) + 1013760: e0bff803 ldbu r2,-32(fp) + 1013764: 1884703a and r2,r3,r2 + 1013768: 10803fcc andi r2,r2,255 + 101376c: 1005003a cmpeq r2,r2,zero + 1013770: 1000381e bne r2,zero,1013854 + OSRdyTbl[y_old] &= ~bitx_old; + 1013774: e13ff903 ldbu r4,-28(fp) + 1013778: e0fff903 ldbu r3,-28(fp) + 101377c: 008040b4 movhi r2,258 + 1013780: 10b31c44 addi r2,r2,-13199 + 1013784: 10c5883a add r2,r2,r3 + 1013788: 10800003 ldbu r2,0(r2) + 101378c: 1007883a mov r3,r2 + 1013790: e0bff803 ldbu r2,-32(fp) + 1013794: 0084303a nor r2,zero,r2 + 1013798: 1884703a and r2,r3,r2 + 101379c: 1007883a mov r3,r2 + 10137a0: 008040b4 movhi r2,258 + 10137a4: 10b31c44 addi r2,r2,-13199 + 10137a8: 1105883a add r2,r2,r4 + 10137ac: 10c00005 stb r3,0(r2) + if (OSRdyTbl[y_old] == 0) { + 10137b0: e0fff903 ldbu r3,-28(fp) + 10137b4: 008040b4 movhi r2,258 + 10137b8: 10b31c44 addi r2,r2,-13199 + 10137bc: 10c5883a add r2,r2,r3 + 10137c0: 10800003 ldbu r2,0(r2) + 10137c4: 10803fcc andi r2,r2,255 + 10137c8: 1004c03a cmpne r2,r2,zero + 10137cc: 10000b1e bne r2,zero,10137fc + OSRdyGrp &= ~bity_old; + 10137d0: e0bff843 ldbu r2,-31(fp) + 10137d4: 0084303a nor r2,zero,r2 + 10137d8: 1007883a mov r3,r2 + 10137dc: 008040b4 movhi r2,258 + 10137e0: 10b31c04 addi r2,r2,-13200 + 10137e4: 10800003 ldbu r2,0(r2) + 10137e8: 1884703a and r2,r3,r2 + 10137ec: 1007883a mov r3,r2 + 10137f0: 008040b4 movhi r2,258 + 10137f4: 10b31c04 addi r2,r2,-13200 + 10137f8: 10c00005 stb r3,0(r2) + } + OSRdyGrp |= bity_new; /* Make new priority ready to run */ + 10137fc: 008040b4 movhi r2,258 + 1013800: 10b31c04 addi r2,r2,-13200 + 1013804: 10c00003 ldbu r3,0(r2) + 1013808: e0bff8c3 ldbu r2,-29(fp) + 101380c: 1884b03a or r2,r3,r2 + 1013810: 1007883a mov r3,r2 + 1013814: 008040b4 movhi r2,258 + 1013818: 10b31c04 addi r2,r2,-13200 + 101381c: 10c00005 stb r3,0(r2) + OSRdyTbl[y_new] |= bitx_new; + 1013820: e13ff983 ldbu r4,-26(fp) + 1013824: e0fff983 ldbu r3,-26(fp) + 1013828: 008040b4 movhi r2,258 + 101382c: 10b31c44 addi r2,r2,-13199 + 1013830: 10c5883a add r2,r2,r3 + 1013834: 10c00003 ldbu r3,0(r2) + 1013838: e0bff883 ldbu r2,-30(fp) + 101383c: 1884b03a or r2,r3,r2 + 1013840: 1007883a mov r3,r2 + 1013844: 008040b4 movhi r2,258 + 1013848: 10b31c44 addi r2,r2,-13199 + 101384c: 1105883a add r2,r2,r4 + 1013850: 10c00005 stb r3,0(r2) + } + +#if (OS_EVENT_EN) + pevent = ptcb->OSTCBEventPtr; + 1013854: e0bffa17 ldw r2,-24(fp) + 1013858: 10800717 ldw r2,28(r2) + 101385c: e0bffc15 stw r2,-16(fp) + if (pevent != (OS_EVENT *)0) { + 1013860: e0bffc17 ldw r2,-16(fp) + 1013864: 1005003a cmpeq r2,r2,zero + 1013868: 1000341e bne r2,zero,101393c + pevent->OSEventTbl[y_old] &= ~bitx_old; /* Remove old task prio from wait list */ + 101386c: e13ff903 ldbu r4,-28(fp) + 1013870: e0fff903 ldbu r3,-28(fp) + 1013874: e0bffc17 ldw r2,-16(fp) + 1013878: 1885883a add r2,r3,r2 + 101387c: 10800204 addi r2,r2,8 + 1013880: 108000c3 ldbu r2,3(r2) + 1013884: 1007883a mov r3,r2 + 1013888: e0bff803 ldbu r2,-32(fp) + 101388c: 0084303a nor r2,zero,r2 + 1013890: 1884703a and r2,r3,r2 + 1013894: 1007883a mov r3,r2 + 1013898: e0bffc17 ldw r2,-16(fp) + 101389c: 2085883a add r2,r4,r2 + 10138a0: 10800204 addi r2,r2,8 + 10138a4: 10c000c5 stb r3,3(r2) + if (pevent->OSEventTbl[y_old] == 0) { + 10138a8: e0fff903 ldbu r3,-28(fp) + 10138ac: e0bffc17 ldw r2,-16(fp) + 10138b0: 1885883a add r2,r3,r2 + 10138b4: 10800204 addi r2,r2,8 + 10138b8: 108000c3 ldbu r2,3(r2) + 10138bc: 10803fcc andi r2,r2,255 + 10138c0: 1004c03a cmpne r2,r2,zero + 10138c4: 1000091e bne r2,zero,10138ec + pevent->OSEventGrp &= ~bity_old; + 10138c8: e0bffc17 ldw r2,-16(fp) + 10138cc: 10800283 ldbu r2,10(r2) + 10138d0: 1007883a mov r3,r2 + 10138d4: e0bff843 ldbu r2,-31(fp) + 10138d8: 0084303a nor r2,zero,r2 + 10138dc: 1884703a and r2,r3,r2 + 10138e0: 1007883a mov r3,r2 + 10138e4: e0bffc17 ldw r2,-16(fp) + 10138e8: 10c00285 stb r3,10(r2) + } + pevent->OSEventGrp |= bity_new; /* Add new task prio to wait list */ + 10138ec: e0bffc17 ldw r2,-16(fp) + 10138f0: 10c00283 ldbu r3,10(r2) + 10138f4: e0bff8c3 ldbu r2,-29(fp) + 10138f8: 1884b03a or r2,r3,r2 + 10138fc: 1007883a mov r3,r2 + 1013900: e0bffc17 ldw r2,-16(fp) + 1013904: 10c00285 stb r3,10(r2) + pevent->OSEventTbl[y_new] |= bitx_new; + 1013908: e13ff983 ldbu r4,-26(fp) + 101390c: e0fff983 ldbu r3,-26(fp) + 1013910: e0bffc17 ldw r2,-16(fp) + 1013914: 1885883a add r2,r3,r2 + 1013918: 10800204 addi r2,r2,8 + 101391c: 10c000c3 ldbu r3,3(r2) + 1013920: e0bff883 ldbu r2,-30(fp) + 1013924: 1884b03a or r2,r3,r2 + 1013928: 1007883a mov r3,r2 + 101392c: e0bffc17 ldw r2,-16(fp) + 1013930: 2085883a add r2,r4,r2 + 1013934: 10800204 addi r2,r2,8 + 1013938: 10c000c5 stb r3,3(r2) + } +#if (OS_EVENT_MULTI_EN > 0) + if (ptcb->OSTCBEventMultiPtr != (OS_EVENT **)0) { + 101393c: e0bffa17 ldw r2,-24(fp) + 1013940: 10800817 ldw r2,32(r2) + 1013944: 1005003a cmpeq r2,r2,zero + 1013948: 1000441e bne r2,zero,1013a5c + pevents = ptcb->OSTCBEventMultiPtr; + 101394c: e0bffa17 ldw r2,-24(fp) + 1013950: 10800817 ldw r2,32(r2) + 1013954: e0bffb15 stw r2,-20(fp) + pevent = *pevents; + 1013958: e0bffb17 ldw r2,-20(fp) + 101395c: 10800017 ldw r2,0(r2) + 1013960: e0bffc15 stw r2,-16(fp) + while (pevent != (OS_EVENT *)0) { + 1013964: 00003a06 br 1013a50 + pevent->OSEventTbl[y_old] &= ~bitx_old; /* Remove old task prio from wait lists */ + 1013968: e13ff903 ldbu r4,-28(fp) + 101396c: e0fff903 ldbu r3,-28(fp) + 1013970: e0bffc17 ldw r2,-16(fp) + 1013974: 1885883a add r2,r3,r2 + 1013978: 10800204 addi r2,r2,8 + 101397c: 108000c3 ldbu r2,3(r2) + 1013980: 1007883a mov r3,r2 + 1013984: e0bff803 ldbu r2,-32(fp) + 1013988: 0084303a nor r2,zero,r2 + 101398c: 1884703a and r2,r3,r2 + 1013990: 1007883a mov r3,r2 + 1013994: e0bffc17 ldw r2,-16(fp) + 1013998: 2085883a add r2,r4,r2 + 101399c: 10800204 addi r2,r2,8 + 10139a0: 10c000c5 stb r3,3(r2) + if (pevent->OSEventTbl[y_old] == 0) { + 10139a4: e0fff903 ldbu r3,-28(fp) + 10139a8: e0bffc17 ldw r2,-16(fp) + 10139ac: 1885883a add r2,r3,r2 + 10139b0: 10800204 addi r2,r2,8 + 10139b4: 108000c3 ldbu r2,3(r2) + 10139b8: 10803fcc andi r2,r2,255 + 10139bc: 1004c03a cmpne r2,r2,zero + 10139c0: 1000091e bne r2,zero,10139e8 + pevent->OSEventGrp &= ~bity_old; + 10139c4: e0bffc17 ldw r2,-16(fp) + 10139c8: 10800283 ldbu r2,10(r2) + 10139cc: 1007883a mov r3,r2 + 10139d0: e0bff843 ldbu r2,-31(fp) + 10139d4: 0084303a nor r2,zero,r2 + 10139d8: 1884703a and r2,r3,r2 + 10139dc: 1007883a mov r3,r2 + 10139e0: e0bffc17 ldw r2,-16(fp) + 10139e4: 10c00285 stb r3,10(r2) + } + pevent->OSEventGrp |= bity_new; /* Add new task prio to wait lists */ + 10139e8: e0bffc17 ldw r2,-16(fp) + 10139ec: 10c00283 ldbu r3,10(r2) + 10139f0: e0bff8c3 ldbu r2,-29(fp) + 10139f4: 1884b03a or r2,r3,r2 + 10139f8: 1007883a mov r3,r2 + 10139fc: e0bffc17 ldw r2,-16(fp) + 1013a00: 10c00285 stb r3,10(r2) + pevent->OSEventTbl[y_new] |= bitx_new; + 1013a04: e13ff983 ldbu r4,-26(fp) + 1013a08: e0fff983 ldbu r3,-26(fp) + 1013a0c: e0bffc17 ldw r2,-16(fp) + 1013a10: 1885883a add r2,r3,r2 + 1013a14: 10800204 addi r2,r2,8 + 1013a18: 10c000c3 ldbu r3,3(r2) + 1013a1c: e0bff883 ldbu r2,-30(fp) + 1013a20: 1884b03a or r2,r3,r2 + 1013a24: 1007883a mov r3,r2 + 1013a28: e0bffc17 ldw r2,-16(fp) + 1013a2c: 2085883a add r2,r4,r2 + 1013a30: 10800204 addi r2,r2,8 + 1013a34: 10c000c5 stb r3,3(r2) + pevents++; + 1013a38: e0bffb17 ldw r2,-20(fp) + 1013a3c: 10800104 addi r2,r2,4 + 1013a40: e0bffb15 stw r2,-20(fp) + pevent = *pevents; + 1013a44: e0bffb17 ldw r2,-20(fp) + 1013a48: 10800017 ldw r2,0(r2) + 1013a4c: e0bffc15 stw r2,-16(fp) + } +#if (OS_EVENT_MULTI_EN > 0) + if (ptcb->OSTCBEventMultiPtr != (OS_EVENT **)0) { + pevents = ptcb->OSTCBEventMultiPtr; + pevent = *pevents; + while (pevent != (OS_EVENT *)0) { + 1013a50: e0bffc17 ldw r2,-16(fp) + 1013a54: 1004c03a cmpne r2,r2,zero + 1013a58: 103fc31e bne r2,zero,1013968 + } + } +#endif +#endif + + ptcb->OSTCBPrio = newprio; /* Set new task priority */ + 1013a5c: e0fffa17 ldw r3,-24(fp) + 1013a60: e0bffe03 ldbu r2,-8(fp) + 1013a64: 18800c85 stb r2,50(r3) + ptcb->OSTCBY = y_new; + 1013a68: e0fffa17 ldw r3,-24(fp) + 1013a6c: e0bff983 ldbu r2,-26(fp) + 1013a70: 18800d05 stb r2,52(r3) + ptcb->OSTCBX = x_new; + 1013a74: e0fffa17 ldw r3,-24(fp) + 1013a78: e0bff943 ldbu r2,-27(fp) + 1013a7c: 18800cc5 stb r2,51(r3) + ptcb->OSTCBBitY = bity_new; + 1013a80: e0fffa17 ldw r3,-24(fp) + 1013a84: e0bff8c3 ldbu r2,-29(fp) + 1013a88: 18800d85 stb r2,54(r3) + ptcb->OSTCBBitX = bitx_new; + 1013a8c: e0fffa17 ldw r3,-24(fp) + 1013a90: e0bff883 ldbu r2,-30(fp) + 1013a94: 18800d45 stb r2,53(r3) + 1013a98: e0bff717 ldw r2,-36(fp) + 1013a9c: e0bff215 stw r2,-56(fp) + 1013aa0: e0bff217 ldw r2,-56(fp) + 1013aa4: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + if (OSRunning == OS_TRUE) { + 1013aa8: 008040b4 movhi r2,258 + 1013aac: 10b31044 addi r2,r2,-13247 + 1013ab0: 10800003 ldbu r2,0(r2) + 1013ab4: 10803fcc andi r2,r2,255 + 1013ab8: 10800058 cmpnei r2,r2,1 + 1013abc: 1000011e bne r2,zero,1013ac4 + OS_Sched(); /* Find new highest priority task */ + 1013ac0: 100ecb80 call 100ecb8 + } + return (OS_ERR_NONE); + 1013ac4: e03fff15 stw zero,-4(fp) + 1013ac8: e0bfff17 ldw r2,-4(fp) +} + 1013acc: e037883a mov sp,fp + 1013ad0: dfc00117 ldw ra,4(sp) + 1013ad4: df000017 ldw fp,0(sp) + 1013ad8: dec00204 addi sp,sp,8 + 1013adc: f800283a ret + +01013ae0 : +********************************************************************************************************* +*/ + +#if OS_TASK_CREATE_EN > 0 +INT8U OSTaskCreate (void (*task)(void *p_arg), void *p_arg, OS_STK *ptos, INT8U prio) +{ + 1013ae0: deffed04 addi sp,sp,-76 + 1013ae4: dfc01215 stw ra,72(sp) + 1013ae8: df001115 stw fp,68(sp) + 1013aec: df001104 addi fp,sp,68 + 1013af0: e13ffb15 stw r4,-20(fp) + 1013af4: e17ffc15 stw r5,-16(fp) + 1013af8: e1bffd15 stw r6,-12(fp) + 1013afc: e1fffe05 stb r7,-8(fp) + OS_STK *psp; + INT8U err; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 1013b00: e03ff815 stw zero,-32(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (prio > OS_LOWEST_PRIO) { /* Make sure priority is within allowable range */ + 1013b04: e0bffe03 ldbu r2,-8(fp) + 1013b08: 10800570 cmpltui r2,r2,21 + 1013b0c: 1000031e bne r2,zero,1013b1c + return (OS_ERR_PRIO_INVALID); + 1013b10: 00800a84 movi r2,42 + 1013b14: e0bfff15 stw r2,-4(fp) + 1013b18: 00006006 br 1013c9c +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1013b1c: 0005303a rdctl r2,status + 1013b20: e0bff715 stw r2,-36(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1013b24: e0fff717 ldw r3,-36(fp) + 1013b28: 00bfff84 movi r2,-2 + 1013b2c: 1884703a and r2,r3,r2 + 1013b30: 1001703a wrctl status,r2 + + return context; + 1013b34: e0bff717 ldw r2,-36(fp) + } +#endif + OS_ENTER_CRITICAL(); + 1013b38: e0bff815 stw r2,-32(fp) + if (OSIntNesting > 0) { /* Make sure we don't create the task from within an ISR */ + 1013b3c: 008040b4 movhi r2,258 + 1013b40: 10b31e04 addi r2,r2,-13192 + 1013b44: 10800003 ldbu r2,0(r2) + 1013b48: 10803fcc andi r2,r2,255 + 1013b4c: 1005003a cmpeq r2,r2,zero + 1013b50: 1000071e bne r2,zero,1013b70 + 1013b54: e0bff817 ldw r2,-32(fp) + 1013b58: e0bff615 stw r2,-40(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1013b5c: e0bff617 ldw r2,-40(fp) + 1013b60: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_CREATE_ISR); + 1013b64: 00800f04 movi r2,60 + 1013b68: e0bfff15 stw r2,-4(fp) + 1013b6c: 00004b06 br 1013c9c + } + if (OSTCBPrioTbl[prio] == (OS_TCB *)0) { /* Make sure task doesn't already exist at this priority */ + 1013b70: e0bffe03 ldbu r2,-8(fp) + 1013b74: 00c040b4 movhi r3,258 + 1013b78: 18d9a904 addi r3,r3,26276 + 1013b7c: 1085883a add r2,r2,r2 + 1013b80: 1085883a add r2,r2,r2 + 1013b84: 10c5883a add r2,r2,r3 + 1013b88: 10800017 ldw r2,0(r2) + 1013b8c: 1004c03a cmpne r2,r2,zero + 1013b90: 10003c1e bne r2,zero,1013c84 + OSTCBPrioTbl[prio] = OS_TCB_RESERVED;/* Reserve the priority to prevent others from doing ... */ + 1013b94: e0bffe03 ldbu r2,-8(fp) + 1013b98: 00c040b4 movhi r3,258 + 1013b9c: 18d9a904 addi r3,r3,26276 + 1013ba0: 1085883a add r2,r2,r2 + 1013ba4: 1085883a add r2,r2,r2 + 1013ba8: 10c7883a add r3,r2,r3 + 1013bac: 00800044 movi r2,1 + 1013bb0: 18800015 stw r2,0(r3) + 1013bb4: e0bff817 ldw r2,-32(fp) + 1013bb8: e0bff515 stw r2,-44(fp) + 1013bbc: e0bff517 ldw r2,-44(fp) + 1013bc0: 1001703a wrctl status,r2 + /* ... the same thing until task is created. */ + OS_EXIT_CRITICAL(); + psp = OSTaskStkInit(task, p_arg, ptos, 0); /* Initialize the task's stack */ + 1013bc4: e13ffb17 ldw r4,-20(fp) + 1013bc8: e17ffc17 ldw r5,-16(fp) + 1013bcc: e1bffd17 ldw r6,-12(fp) + 1013bd0: 000f883a mov r7,zero + 1013bd4: 10180fc0 call 10180fc + 1013bd8: e0bffa15 stw r2,-24(fp) + err = OS_TCBInit(prio, psp, (OS_STK *)0, 0, 0, (void *)0, 0); + 1013bdc: e13ffe03 ldbu r4,-8(fp) + 1013be0: d8000015 stw zero,0(sp) + 1013be4: d8000115 stw zero,4(sp) + 1013be8: d8000215 stw zero,8(sp) + 1013bec: e17ffa17 ldw r5,-24(fp) + 1013bf0: 000d883a mov r6,zero + 1013bf4: 000f883a mov r7,zero + 1013bf8: 100f0c00 call 100f0c0 + 1013bfc: e0bff905 stb r2,-28(fp) + if (err == OS_ERR_NONE) { + 1013c00: e0bff903 ldbu r2,-28(fp) + 1013c04: 1004c03a cmpne r2,r2,zero + 1013c08: 1000081e bne r2,zero,1013c2c + if (OSRunning == OS_TRUE) { /* Find highest priority task if multitasking has started */ + 1013c0c: 008040b4 movhi r2,258 + 1013c10: 10b31044 addi r2,r2,-13247 + 1013c14: 10800003 ldbu r2,0(r2) + 1013c18: 10803fcc andi r2,r2,255 + 1013c1c: 10800058 cmpnei r2,r2,1 + 1013c20: 1000151e bne r2,zero,1013c78 + OS_Sched(); + 1013c24: 100ecb80 call 100ecb8 + 1013c28: 00001306 br 1013c78 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1013c2c: 0005303a rdctl r2,status + 1013c30: e0bff415 stw r2,-48(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1013c34: e0fff417 ldw r3,-48(fp) + 1013c38: 00bfff84 movi r2,-2 + 1013c3c: 1884703a and r2,r3,r2 + 1013c40: 1001703a wrctl status,r2 + + return context; + 1013c44: e0bff417 ldw r2,-48(fp) + } + } else { + OS_ENTER_CRITICAL(); + 1013c48: e0bff815 stw r2,-32(fp) + OSTCBPrioTbl[prio] = (OS_TCB *)0;/* Make this priority available to others */ + 1013c4c: e0bffe03 ldbu r2,-8(fp) + 1013c50: 00c040b4 movhi r3,258 + 1013c54: 18d9a904 addi r3,r3,26276 + 1013c58: 1085883a add r2,r2,r2 + 1013c5c: 1085883a add r2,r2,r2 + 1013c60: 10c5883a add r2,r2,r3 + 1013c64: 10000015 stw zero,0(r2) + 1013c68: e0bff817 ldw r2,-32(fp) + 1013c6c: e0bff315 stw r2,-52(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1013c70: e0bff317 ldw r2,-52(fp) + 1013c74: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + } + return (err); + 1013c78: e0bff903 ldbu r2,-28(fp) + 1013c7c: e0bfff15 stw r2,-4(fp) + 1013c80: 00000606 br 1013c9c + 1013c84: e0bff817 ldw r2,-32(fp) + 1013c88: e0bff215 stw r2,-56(fp) + 1013c8c: e0bff217 ldw r2,-56(fp) + 1013c90: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); + return (OS_ERR_PRIO_EXIST); + 1013c94: 00800a04 movi r2,40 + 1013c98: e0bfff15 stw r2,-4(fp) + 1013c9c: e0bfff17 ldw r2,-4(fp) +} + 1013ca0: e037883a mov sp,fp + 1013ca4: dfc00117 ldw ra,4(sp) + 1013ca8: df000017 ldw fp,0(sp) + 1013cac: dec00204 addi sp,sp,8 + 1013cb0: f800283a ret + +01013cb4 : + INT16U id, + OS_STK *pbos, + INT32U stk_size, + void *pext, + INT16U opt) +{ + 1013cb4: deffeb04 addi sp,sp,-84 + 1013cb8: dfc01415 stw ra,80(sp) + 1013cbc: df001315 stw fp,76(sp) + 1013cc0: df001304 addi fp,sp,76 + 1013cc4: e13ff915 stw r4,-28(fp) + 1013cc8: e17ffa15 stw r5,-24(fp) + 1013ccc: e1bffb15 stw r6,-20(fp) + 1013cd0: e0800217 ldw r2,8(fp) + 1013cd4: e0c00617 ldw r3,24(fp) + 1013cd8: e1fffc05 stb r7,-16(fp) + 1013cdc: e0bffd0d sth r2,-12(fp) + 1013ce0: e0fffe0d sth r3,-8(fp) + OS_STK *psp; + INT8U err; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 1013ce4: e03ff615 stw zero,-40(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (prio > OS_LOWEST_PRIO) { /* Make sure priority is within allowable range */ + 1013ce8: e0bffc03 ldbu r2,-16(fp) + 1013cec: 10800570 cmpltui r2,r2,21 + 1013cf0: 1000031e bne r2,zero,1013d00 + return (OS_ERR_PRIO_INVALID); + 1013cf4: 00800a84 movi r2,42 + 1013cf8: e0bfff15 stw r2,-4(fp) + 1013cfc: 00006706 br 1013e9c +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1013d00: 0005303a rdctl r2,status + 1013d04: e0bff515 stw r2,-44(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1013d08: e0fff517 ldw r3,-44(fp) + 1013d0c: 00bfff84 movi r2,-2 + 1013d10: 1884703a and r2,r3,r2 + 1013d14: 1001703a wrctl status,r2 + + return context; + 1013d18: e0bff517 ldw r2,-44(fp) + } +#endif + OS_ENTER_CRITICAL(); + 1013d1c: e0bff615 stw r2,-40(fp) + if (OSIntNesting > 0) { /* Make sure we don't create the task from within an ISR */ + 1013d20: 008040b4 movhi r2,258 + 1013d24: 10b31e04 addi r2,r2,-13192 + 1013d28: 10800003 ldbu r2,0(r2) + 1013d2c: 10803fcc andi r2,r2,255 + 1013d30: 1005003a cmpeq r2,r2,zero + 1013d34: 1000071e bne r2,zero,1013d54 + 1013d38: e0bff617 ldw r2,-40(fp) + 1013d3c: e0bff415 stw r2,-48(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1013d40: e0bff417 ldw r2,-48(fp) + 1013d44: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_CREATE_ISR); + 1013d48: 00800f04 movi r2,60 + 1013d4c: e0bfff15 stw r2,-4(fp) + 1013d50: 00005206 br 1013e9c + } + if (OSTCBPrioTbl[prio] == (OS_TCB *)0) { /* Make sure task doesn't already exist at this priority */ + 1013d54: e0bffc03 ldbu r2,-16(fp) + 1013d58: 00c040b4 movhi r3,258 + 1013d5c: 18d9a904 addi r3,r3,26276 + 1013d60: 1085883a add r2,r2,r2 + 1013d64: 1085883a add r2,r2,r2 + 1013d68: 10c5883a add r2,r2,r3 + 1013d6c: 10800017 ldw r2,0(r2) + 1013d70: 1004c03a cmpne r2,r2,zero + 1013d74: 1000431e bne r2,zero,1013e84 + OSTCBPrioTbl[prio] = OS_TCB_RESERVED;/* Reserve the priority to prevent others from doing ... */ + 1013d78: e0bffc03 ldbu r2,-16(fp) + 1013d7c: 00c040b4 movhi r3,258 + 1013d80: 18d9a904 addi r3,r3,26276 + 1013d84: 1085883a add r2,r2,r2 + 1013d88: 1085883a add r2,r2,r2 + 1013d8c: 10c7883a add r3,r2,r3 + 1013d90: 00800044 movi r2,1 + 1013d94: 18800015 stw r2,0(r3) + 1013d98: e0bff617 ldw r2,-40(fp) + 1013d9c: e0bff315 stw r2,-52(fp) + 1013da0: e0bff317 ldw r2,-52(fp) + 1013da4: 1001703a wrctl status,r2 + /* ... the same thing until task is created. */ + OS_EXIT_CRITICAL(); + +#if (OS_TASK_STAT_STK_CHK_EN > 0) + OS_TaskStkClr(pbos, stk_size, opt); /* Clear the task stack (if needed) */ + 1013da8: e1bffe0b ldhu r6,-8(fp) + 1013dac: e1000317 ldw r4,12(fp) + 1013db0: e1400417 ldw r5,16(fp) + 1013db4: 1014f300 call 1014f30 +#endif + + psp = OSTaskStkInit(task, p_arg, ptos, opt); /* Initialize the task's stack */ + 1013db8: e1fffe0b ldhu r7,-8(fp) + 1013dbc: e13ff917 ldw r4,-28(fp) + 1013dc0: e17ffa17 ldw r5,-24(fp) + 1013dc4: e1bffb17 ldw r6,-20(fp) + 1013dc8: 10180fc0 call 10180fc + 1013dcc: e0bff815 stw r2,-32(fp) + err = OS_TCBInit(prio, psp, pbos, id, stk_size, pext, opt); + 1013dd0: e13ffc03 ldbu r4,-16(fp) + 1013dd4: e1fffd0b ldhu r7,-12(fp) + 1013dd8: e0fffe0b ldhu r3,-8(fp) + 1013ddc: e0800417 ldw r2,16(fp) + 1013de0: d8800015 stw r2,0(sp) + 1013de4: e0800517 ldw r2,20(fp) + 1013de8: d8800115 stw r2,4(sp) + 1013dec: d8c00215 stw r3,8(sp) + 1013df0: e17ff817 ldw r5,-32(fp) + 1013df4: e1800317 ldw r6,12(fp) + 1013df8: 100f0c00 call 100f0c0 + 1013dfc: e0bff705 stb r2,-36(fp) + if (err == OS_ERR_NONE) { + 1013e00: e0bff703 ldbu r2,-36(fp) + 1013e04: 1004c03a cmpne r2,r2,zero + 1013e08: 1000081e bne r2,zero,1013e2c + if (OSRunning == OS_TRUE) { /* Find HPT if multitasking has started */ + 1013e0c: 008040b4 movhi r2,258 + 1013e10: 10b31044 addi r2,r2,-13247 + 1013e14: 10800003 ldbu r2,0(r2) + 1013e18: 10803fcc andi r2,r2,255 + 1013e1c: 10800058 cmpnei r2,r2,1 + 1013e20: 1000151e bne r2,zero,1013e78 + OS_Sched(); + 1013e24: 100ecb80 call 100ecb8 + 1013e28: 00001306 br 1013e78 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1013e2c: 0005303a rdctl r2,status + 1013e30: e0bff215 stw r2,-56(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1013e34: e0fff217 ldw r3,-56(fp) + 1013e38: 00bfff84 movi r2,-2 + 1013e3c: 1884703a and r2,r3,r2 + 1013e40: 1001703a wrctl status,r2 + + return context; + 1013e44: e0bff217 ldw r2,-56(fp) + } + } else { + OS_ENTER_CRITICAL(); + 1013e48: e0bff615 stw r2,-40(fp) + OSTCBPrioTbl[prio] = (OS_TCB *)0; /* Make this priority avail. to others */ + 1013e4c: e0bffc03 ldbu r2,-16(fp) + 1013e50: 00c040b4 movhi r3,258 + 1013e54: 18d9a904 addi r3,r3,26276 + 1013e58: 1085883a add r2,r2,r2 + 1013e5c: 1085883a add r2,r2,r2 + 1013e60: 10c5883a add r2,r2,r3 + 1013e64: 10000015 stw zero,0(r2) + 1013e68: e0bff617 ldw r2,-40(fp) + 1013e6c: e0bff115 stw r2,-60(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1013e70: e0bff117 ldw r2,-60(fp) + 1013e74: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + } + return (err); + 1013e78: e0bff703 ldbu r2,-36(fp) + 1013e7c: e0bfff15 stw r2,-4(fp) + 1013e80: 00000606 br 1013e9c + 1013e84: e0bff617 ldw r2,-40(fp) + 1013e88: e0bff015 stw r2,-64(fp) + 1013e8c: e0bff017 ldw r2,-64(fp) + 1013e90: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); + return (OS_ERR_PRIO_EXIST); + 1013e94: 00800a04 movi r2,40 + 1013e98: e0bfff15 stw r2,-4(fp) + 1013e9c: e0bfff17 ldw r2,-4(fp) +} + 1013ea0: e037883a mov sp,fp + 1013ea4: dfc00117 ldw ra,4(sp) + 1013ea8: df000017 ldw fp,0(sp) + 1013eac: dec00204 addi sp,sp,8 + 1013eb0: f800283a ret + +01013eb4 : +********************************************************************************************************* +*/ + +#if OS_TASK_DEL_EN > 0 +INT8U OSTaskDel (INT8U prio) +{ + 1013eb4: defff304 addi sp,sp,-52 + 1013eb8: dfc00c15 stw ra,48(sp) + 1013ebc: df000b15 stw fp,44(sp) + 1013ec0: df000b04 addi fp,sp,44 + 1013ec4: e13ffe05 stb r4,-8(fp) +#if (OS_FLAG_EN > 0) && (OS_MAX_FLAGS > 0) + OS_FLAG_NODE *pnode; +#endif + OS_TCB *ptcb; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 1013ec8: e03ffb15 stw zero,-20(fp) +#endif + + + + if (OSIntNesting > 0) { /* See if trying to delete from ISR */ + 1013ecc: 008040b4 movhi r2,258 + 1013ed0: 10b31e04 addi r2,r2,-13192 + 1013ed4: 10800003 ldbu r2,0(r2) + 1013ed8: 10803fcc andi r2,r2,255 + 1013edc: 1005003a cmpeq r2,r2,zero + 1013ee0: 1000031e bne r2,zero,1013ef0 + return (OS_ERR_TASK_DEL_ISR); + 1013ee4: 00801004 movi r2,64 + 1013ee8: e0bfff15 stw r2,-4(fp) + 1013eec: 0000ee06 br 10142a8 + } + if (prio == OS_TASK_IDLE_PRIO) { /* Not allowed to delete idle task */ + 1013ef0: e0bffe03 ldbu r2,-8(fp) + 1013ef4: 10800518 cmpnei r2,r2,20 + 1013ef8: 1000031e bne r2,zero,1013f08 + return (OS_ERR_TASK_DEL_IDLE); + 1013efc: 00800f84 movi r2,62 + 1013f00: e0bfff15 stw r2,-4(fp) + 1013f04: 0000e806 br 10142a8 + } +#if OS_ARG_CHK_EN > 0 + if (prio >= OS_LOWEST_PRIO) { /* Task priority valid ? */ + 1013f08: e0bffe03 ldbu r2,-8(fp) + 1013f0c: 10800530 cmpltui r2,r2,20 + 1013f10: 1000061e bne r2,zero,1013f2c + if (prio != OS_PRIO_SELF) { + 1013f14: e0bffe03 ldbu r2,-8(fp) + 1013f18: 10803fe0 cmpeqi r2,r2,255 + 1013f1c: 1000031e bne r2,zero,1013f2c + return (OS_ERR_PRIO_INVALID); + 1013f20: 00800a84 movi r2,42 + 1013f24: e0bfff15 stw r2,-4(fp) + 1013f28: 0000df06 br 10142a8 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1013f2c: 0005303a rdctl r2,status + 1013f30: e0bffa15 stw r2,-24(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1013f34: e0fffa17 ldw r3,-24(fp) + 1013f38: 00bfff84 movi r2,-2 + 1013f3c: 1884703a and r2,r3,r2 + 1013f40: 1001703a wrctl status,r2 + + return context; + 1013f44: e0bffa17 ldw r2,-24(fp) + } + } +#endif + +/*$PAGE*/ + OS_ENTER_CRITICAL(); + 1013f48: e0bffb15 stw r2,-20(fp) + if (prio == OS_PRIO_SELF) { /* See if requesting to delete self */ + 1013f4c: e0bffe03 ldbu r2,-8(fp) + 1013f50: 10803fd8 cmpnei r2,r2,255 + 1013f54: 1000051e bne r2,zero,1013f6c + prio = OSTCBCur->OSTCBPrio; /* Set priority to delete to current */ + 1013f58: 008040b4 movhi r2,258 + 1013f5c: 10b31f04 addi r2,r2,-13188 + 1013f60: 10800017 ldw r2,0(r2) + 1013f64: 10800c83 ldbu r2,50(r2) + 1013f68: e0bffe05 stb r2,-8(fp) + } + ptcb = OSTCBPrioTbl[prio]; + 1013f6c: e0bffe03 ldbu r2,-8(fp) + 1013f70: 00c040b4 movhi r3,258 + 1013f74: 18d9a904 addi r3,r3,26276 + 1013f78: 1085883a add r2,r2,r2 + 1013f7c: 1085883a add r2,r2,r2 + 1013f80: 10c5883a add r2,r2,r3 + 1013f84: 10800017 ldw r2,0(r2) + 1013f88: e0bffc15 stw r2,-16(fp) + if (ptcb == (OS_TCB *)0) { /* Task to delete must exist */ + 1013f8c: e0bffc17 ldw r2,-16(fp) + 1013f90: 1004c03a cmpne r2,r2,zero + 1013f94: 1000071e bne r2,zero,1013fb4 + 1013f98: e0bffb17 ldw r2,-20(fp) + 1013f9c: e0bff915 stw r2,-28(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1013fa0: e0bff917 ldw r2,-28(fp) + 1013fa4: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_NOT_EXIST); + 1013fa8: 008010c4 movi r2,67 + 1013fac: e0bfff15 stw r2,-4(fp) + 1013fb0: 0000bd06 br 10142a8 + } + if (ptcb == OS_TCB_RESERVED) { /* Must not be assigned to Mutex */ + 1013fb4: e0bffc17 ldw r2,-16(fp) + 1013fb8: 10800058 cmpnei r2,r2,1 + 1013fbc: 1000071e bne r2,zero,1013fdc + 1013fc0: e0bffb17 ldw r2,-20(fp) + 1013fc4: e0bff815 stw r2,-32(fp) + 1013fc8: e0bff817 ldw r2,-32(fp) + 1013fcc: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_DEL); + 1013fd0: 00800f44 movi r2,61 + 1013fd4: e0bfff15 stw r2,-4(fp) + 1013fd8: 0000b306 br 10142a8 + } + + OSRdyTbl[ptcb->OSTCBY] &= ~ptcb->OSTCBBitX; + 1013fdc: e0bffc17 ldw r2,-16(fp) + 1013fe0: 10800d03 ldbu r2,52(r2) + 1013fe4: 11003fcc andi r4,r2,255 + 1013fe8: e0bffc17 ldw r2,-16(fp) + 1013fec: 10800d03 ldbu r2,52(r2) + 1013ff0: 10c03fcc andi r3,r2,255 + 1013ff4: 008040b4 movhi r2,258 + 1013ff8: 10b31c44 addi r2,r2,-13199 + 1013ffc: 10c5883a add r2,r2,r3 + 1014000: 10800003 ldbu r2,0(r2) + 1014004: 1007883a mov r3,r2 + 1014008: e0bffc17 ldw r2,-16(fp) + 101400c: 10800d43 ldbu r2,53(r2) + 1014010: 0084303a nor r2,zero,r2 + 1014014: 1884703a and r2,r3,r2 + 1014018: 1007883a mov r3,r2 + 101401c: 008040b4 movhi r2,258 + 1014020: 10b31c44 addi r2,r2,-13199 + 1014024: 1105883a add r2,r2,r4 + 1014028: 10c00005 stb r3,0(r2) + if (OSRdyTbl[ptcb->OSTCBY] == 0) { /* Make task not ready */ + 101402c: e0bffc17 ldw r2,-16(fp) + 1014030: 10800d03 ldbu r2,52(r2) + 1014034: 10c03fcc andi r3,r2,255 + 1014038: 008040b4 movhi r2,258 + 101403c: 10b31c44 addi r2,r2,-13199 + 1014040: 10c5883a add r2,r2,r3 + 1014044: 10800003 ldbu r2,0(r2) + 1014048: 10803fcc andi r2,r2,255 + 101404c: 1004c03a cmpne r2,r2,zero + 1014050: 10000c1e bne r2,zero,1014084 + OSRdyGrp &= ~ptcb->OSTCBBitY; + 1014054: e0bffc17 ldw r2,-16(fp) + 1014058: 10800d83 ldbu r2,54(r2) + 101405c: 0084303a nor r2,zero,r2 + 1014060: 1007883a mov r3,r2 + 1014064: 008040b4 movhi r2,258 + 1014068: 10b31c04 addi r2,r2,-13200 + 101406c: 10800003 ldbu r2,0(r2) + 1014070: 1884703a and r2,r3,r2 + 1014074: 1007883a mov r3,r2 + 1014078: 008040b4 movhi r2,258 + 101407c: 10b31c04 addi r2,r2,-13200 + 1014080: 10c00005 stb r3,0(r2) + } + +#if (OS_EVENT_EN) + if (ptcb->OSTCBEventPtr != (OS_EVENT *)0) { + 1014084: e0bffc17 ldw r2,-16(fp) + 1014088: 10800717 ldw r2,28(r2) + 101408c: 1005003a cmpeq r2,r2,zero + 1014090: 1000041e bne r2,zero,10140a4 + OS_EventTaskRemove(ptcb, ptcb->OSTCBEventPtr); /* Remove this task from any event wait list */ + 1014094: e0bffc17 ldw r2,-16(fp) + 1014098: 11400717 ldw r5,28(r2) + 101409c: e13ffc17 ldw r4,-16(fp) + 10140a0: 100e6700 call 100e670 + } +#if (OS_EVENT_MULTI_EN > 0) + if (ptcb->OSTCBEventMultiPtr != (OS_EVENT **)0) { /* Remove this task from any events' wait lists*/ + 10140a4: e0bffc17 ldw r2,-16(fp) + 10140a8: 10800817 ldw r2,32(r2) + 10140ac: 1005003a cmpeq r2,r2,zero + 10140b0: 1000041e bne r2,zero,10140c4 + OS_EventTaskRemoveMulti(ptcb, ptcb->OSTCBEventMultiPtr); + 10140b4: e0bffc17 ldw r2,-16(fp) + 10140b8: 11400817 ldw r5,32(r2) + 10140bc: e13ffc17 ldw r4,-16(fp) + 10140c0: 100e7280 call 100e728 + } +#endif +#endif + +#if (OS_FLAG_EN > 0) && (OS_MAX_FLAGS > 0) + pnode = ptcb->OSTCBFlagNode; + 10140c4: e0bffc17 ldw r2,-16(fp) + 10140c8: 10800a17 ldw r2,40(r2) + 10140cc: e0bffd15 stw r2,-12(fp) + if (pnode != (OS_FLAG_NODE *)0) { /* If task is waiting on event flag */ + 10140d0: e0bffd17 ldw r2,-12(fp) + 10140d4: 1005003a cmpeq r2,r2,zero + 10140d8: 1000021e bne r2,zero,10140e4 + OS_FlagUnlink(pnode); /* Remove from wait list */ + 10140dc: e13ffd17 ldw r4,-12(fp) + 10140e0: 1010dbc0 call 1010dbc + } +#endif + + ptcb->OSTCBDly = 0; /* Prevent OSTimeTick() from updating */ + 10140e4: e0bffc17 ldw r2,-16(fp) + 10140e8: 10000b8d sth zero,46(r2) + ptcb->OSTCBStat = OS_STAT_RDY; /* Prevent task from being resumed */ + 10140ec: e0bffc17 ldw r2,-16(fp) + 10140f0: 10000c05 stb zero,48(r2) + ptcb->OSTCBStatPend = OS_STAT_PEND_OK; + 10140f4: e0bffc17 ldw r2,-16(fp) + 10140f8: 10000c45 stb zero,49(r2) + if (OSLockNesting < 255u) { /* Make sure we don't context switch */ + 10140fc: 008040b4 movhi r2,258 + 1014100: 10b31004 addi r2,r2,-13248 + 1014104: 10800003 ldbu r2,0(r2) + 1014108: 10803fcc andi r2,r2,255 + 101410c: 10803fe0 cmpeqi r2,r2,255 + 1014110: 1000081e bne r2,zero,1014134 + OSLockNesting++; + 1014114: 008040b4 movhi r2,258 + 1014118: 10b31004 addi r2,r2,-13248 + 101411c: 10800003 ldbu r2,0(r2) + 1014120: 10800044 addi r2,r2,1 + 1014124: 1007883a mov r3,r2 + 1014128: 008040b4 movhi r2,258 + 101412c: 10b31004 addi r2,r2,-13248 + 1014130: 10c00005 stb r3,0(r2) + 1014134: e0bffb17 ldw r2,-20(fp) + 1014138: e0bff715 stw r2,-36(fp) + 101413c: e0bff717 ldw r2,-36(fp) + 1014140: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); /* Enabling INT. ignores next instruc. */ + OS_Dummy(); /* ... Dummy ensures that INTs will be */ + 1014144: 100e25c0 call 100e25c +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1014148: 0005303a rdctl r2,status + 101414c: e0bff615 stw r2,-40(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1014150: e0fff617 ldw r3,-40(fp) + 1014154: 00bfff84 movi r2,-2 + 1014158: 1884703a and r2,r3,r2 + 101415c: 1001703a wrctl status,r2 + + return context; + 1014160: e0bff617 ldw r2,-40(fp) + OS_ENTER_CRITICAL(); /* ... disabled HERE! */ + 1014164: e0bffb15 stw r2,-20(fp) + if (OSLockNesting > 0) { /* Remove context switch lock */ + 1014168: 008040b4 movhi r2,258 + 101416c: 10b31004 addi r2,r2,-13248 + 1014170: 10800003 ldbu r2,0(r2) + 1014174: 10803fcc andi r2,r2,255 + 1014178: 1005003a cmpeq r2,r2,zero + 101417c: 1000081e bne r2,zero,10141a0 + OSLockNesting--; + 1014180: 008040b4 movhi r2,258 + 1014184: 10b31004 addi r2,r2,-13248 + 1014188: 10800003 ldbu r2,0(r2) + 101418c: 10bfffc4 addi r2,r2,-1 + 1014190: 1007883a mov r3,r2 + 1014194: 008040b4 movhi r2,258 + 1014198: 10b31004 addi r2,r2,-13248 + 101419c: 10c00005 stb r3,0(r2) + } + OSTaskDelHook(ptcb); /* Call user defined hook */ + 10141a0: e13ffc17 ldw r4,-16(fp) + 10141a4: 101842c0 call 101842c + OSTaskCtr--; /* One less task being managed */ + 10141a8: 008040b4 movhi r2,258 + 10141ac: 10b31844 addi r2,r2,-13215 + 10141b0: 10800003 ldbu r2,0(r2) + 10141b4: 10bfffc4 addi r2,r2,-1 + 10141b8: 1007883a mov r3,r2 + 10141bc: 008040b4 movhi r2,258 + 10141c0: 10b31844 addi r2,r2,-13215 + 10141c4: 10c00005 stb r3,0(r2) + OSTCBPrioTbl[prio] = (OS_TCB *)0; /* Clear old priority entry */ + 10141c8: e0bffe03 ldbu r2,-8(fp) + 10141cc: 00c040b4 movhi r3,258 + 10141d0: 18d9a904 addi r3,r3,26276 + 10141d4: 1085883a add r2,r2,r2 + 10141d8: 1085883a add r2,r2,r2 + 10141dc: 10c5883a add r2,r2,r3 + 10141e0: 10000015 stw zero,0(r2) + if (ptcb->OSTCBPrev == (OS_TCB *)0) { /* Remove from TCB chain */ + 10141e4: e0bffc17 ldw r2,-16(fp) + 10141e8: 10800617 ldw r2,24(r2) + 10141ec: 1004c03a cmpne r2,r2,zero + 10141f0: 1000091e bne r2,zero,1014218 + ptcb->OSTCBNext->OSTCBPrev = (OS_TCB *)0; + 10141f4: e0bffc17 ldw r2,-16(fp) + 10141f8: 10800517 ldw r2,20(r2) + 10141fc: 10000615 stw zero,24(r2) + OSTCBList = ptcb->OSTCBNext; + 1014200: e0bffc17 ldw r2,-16(fp) + 1014204: 10c00517 ldw r3,20(r2) + 1014208: 008040b4 movhi r2,258 + 101420c: 10b31304 addi r2,r2,-13236 + 1014210: 10c00015 stw r3,0(r2) + 1014214: 00000a06 br 1014240 + } else { + ptcb->OSTCBPrev->OSTCBNext = ptcb->OSTCBNext; + 1014218: e0bffc17 ldw r2,-16(fp) + 101421c: 10c00617 ldw r3,24(r2) + 1014220: e0bffc17 ldw r2,-16(fp) + 1014224: 10800517 ldw r2,20(r2) + 1014228: 18800515 stw r2,20(r3) + ptcb->OSTCBNext->OSTCBPrev = ptcb->OSTCBPrev; + 101422c: e0bffc17 ldw r2,-16(fp) + 1014230: 10c00517 ldw r3,20(r2) + 1014234: e0bffc17 ldw r2,-16(fp) + 1014238: 10800617 ldw r2,24(r2) + 101423c: 18800615 stw r2,24(r3) + } + ptcb->OSTCBNext = OSTCBFreeList; /* Return TCB to free TCB list */ + 1014240: 008040b4 movhi r2,258 + 1014244: 10b31704 addi r2,r2,-13220 + 1014248: 10c00017 ldw r3,0(r2) + 101424c: e0bffc17 ldw r2,-16(fp) + 1014250: 10c00515 stw r3,20(r2) + OSTCBFreeList = ptcb; + 1014254: 00c040b4 movhi r3,258 + 1014258: 18f31704 addi r3,r3,-13220 + 101425c: e0bffc17 ldw r2,-16(fp) + 1014260: 18800015 stw r2,0(r3) +#if OS_TASK_NAME_SIZE > 1 + ptcb->OSTCBTaskName[0] = '?'; /* Unknown name */ + 1014264: e0fffc17 ldw r3,-16(fp) + 1014268: 00800fc4 movi r2,63 + 101426c: 18801305 stb r2,76(r3) + ptcb->OSTCBTaskName[1] = OS_ASCII_NUL; + 1014270: e0bffc17 ldw r2,-16(fp) + 1014274: 10001345 stb zero,77(r2) + 1014278: e0bffb17 ldw r2,-20(fp) + 101427c: e0bff515 stw r2,-44(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1014280: e0bff517 ldw r2,-44(fp) + 1014284: 1001703a wrctl status,r2 +#endif + OS_EXIT_CRITICAL(); + if (OSRunning == OS_TRUE) { + 1014288: 008040b4 movhi r2,258 + 101428c: 10b31044 addi r2,r2,-13247 + 1014290: 10800003 ldbu r2,0(r2) + 1014294: 10803fcc andi r2,r2,255 + 1014298: 10800058 cmpnei r2,r2,1 + 101429c: 1000011e bne r2,zero,10142a4 + OS_Sched(); /* Find new highest priority task */ + 10142a0: 100ecb80 call 100ecb8 + } + return (OS_ERR_NONE); + 10142a4: e03fff15 stw zero,-4(fp) + 10142a8: e0bfff17 ldw r2,-4(fp) +} + 10142ac: e037883a mov sp,fp + 10142b0: dfc00117 ldw ra,4(sp) + 10142b4: df000017 ldw fp,0(sp) + 10142b8: dec00204 addi sp,sp,8 + 10142bc: f800283a ret + +010142c0 : +********************************************************************************************************* +*/ +/*$PAGE*/ +#if OS_TASK_DEL_EN > 0 +INT8U OSTaskDelReq (INT8U prio) +{ + 10142c0: defff404 addi sp,sp,-48 + 10142c4: df000b15 stw fp,44(sp) + 10142c8: df000b04 addi fp,sp,44 + 10142cc: e13ffe05 stb r4,-8(fp) + INT8U stat; + OS_TCB *ptcb; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 10142d0: e03ffb15 stw zero,-20(fp) +#endif + + + + if (prio == OS_TASK_IDLE_PRIO) { /* Not allowed to delete idle task */ + 10142d4: e0bffe03 ldbu r2,-8(fp) + 10142d8: 10800518 cmpnei r2,r2,20 + 10142dc: 1000031e bne r2,zero,10142ec + return (OS_ERR_TASK_DEL_IDLE); + 10142e0: 00800f84 movi r2,62 + 10142e4: e0bfff15 stw r2,-4(fp) + 10142e8: 00004c06 br 101441c + } +#if OS_ARG_CHK_EN > 0 + if (prio >= OS_LOWEST_PRIO) { /* Task priority valid ? */ + 10142ec: e0bffe03 ldbu r2,-8(fp) + 10142f0: 10800530 cmpltui r2,r2,20 + 10142f4: 1000061e bne r2,zero,1014310 + if (prio != OS_PRIO_SELF) { + 10142f8: e0bffe03 ldbu r2,-8(fp) + 10142fc: 10803fe0 cmpeqi r2,r2,255 + 1014300: 1000031e bne r2,zero,1014310 + return (OS_ERR_PRIO_INVALID); + 1014304: 00800a84 movi r2,42 + 1014308: e0bfff15 stw r2,-4(fp) + 101430c: 00004306 br 101441c + } + } +#endif + if (prio == OS_PRIO_SELF) { /* See if a task is requesting to ... */ + 1014310: e0bffe03 ldbu r2,-8(fp) + 1014314: 10803fd8 cmpnei r2,r2,255 + 1014318: 1000141e bne r2,zero,101436c +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 101431c: 0005303a rdctl r2,status + 1014320: e0bffa15 stw r2,-24(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1014324: e0fffa17 ldw r3,-24(fp) + 1014328: 00bfff84 movi r2,-2 + 101432c: 1884703a and r2,r3,r2 + 1014330: 1001703a wrctl status,r2 + + return context; + 1014334: e0bffa17 ldw r2,-24(fp) + OS_ENTER_CRITICAL(); /* ... this task to delete itself */ + 1014338: e0bffb15 stw r2,-20(fp) + stat = OSTCBCur->OSTCBDelReq; /* Return request status to caller */ + 101433c: 008040b4 movhi r2,258 + 1014340: 10b31f04 addi r2,r2,-13188 + 1014344: 10800017 ldw r2,0(r2) + 1014348: 10800dc3 ldbu r2,55(r2) + 101434c: e0bffd05 stb r2,-12(fp) + 1014350: e0bffb17 ldw r2,-20(fp) + 1014354: e0bff915 stw r2,-28(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1014358: e0bff917 ldw r2,-28(fp) + 101435c: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (stat); + 1014360: e0bffd03 ldbu r2,-12(fp) + 1014364: e0bfff15 stw r2,-4(fp) + 1014368: 00002c06 br 101441c +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 101436c: 0005303a rdctl r2,status + 1014370: e0bff815 stw r2,-32(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1014374: e0fff817 ldw r3,-32(fp) + 1014378: 00bfff84 movi r2,-2 + 101437c: 1884703a and r2,r3,r2 + 1014380: 1001703a wrctl status,r2 + + return context; + 1014384: e0bff817 ldw r2,-32(fp) + } + OS_ENTER_CRITICAL(); + 1014388: e0bffb15 stw r2,-20(fp) + ptcb = OSTCBPrioTbl[prio]; + 101438c: e0bffe03 ldbu r2,-8(fp) + 1014390: 00c040b4 movhi r3,258 + 1014394: 18d9a904 addi r3,r3,26276 + 1014398: 1085883a add r2,r2,r2 + 101439c: 1085883a add r2,r2,r2 + 10143a0: 10c5883a add r2,r2,r3 + 10143a4: 10800017 ldw r2,0(r2) + 10143a8: e0bffc15 stw r2,-16(fp) + if (ptcb == (OS_TCB *)0) { /* Task to delete must exist */ + 10143ac: e0bffc17 ldw r2,-16(fp) + 10143b0: 1004c03a cmpne r2,r2,zero + 10143b4: 1000071e bne r2,zero,10143d4 + 10143b8: e0bffb17 ldw r2,-20(fp) + 10143bc: e0bff715 stw r2,-36(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 10143c0: e0bff717 ldw r2,-36(fp) + 10143c4: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_NOT_EXIST); /* Task must already be deleted */ + 10143c8: 008010c4 movi r2,67 + 10143cc: e0bfff15 stw r2,-4(fp) + 10143d0: 00001206 br 101441c + } + if (ptcb == OS_TCB_RESERVED) { /* Must NOT be assigned to a Mutex */ + 10143d4: e0bffc17 ldw r2,-16(fp) + 10143d8: 10800058 cmpnei r2,r2,1 + 10143dc: 1000071e bne r2,zero,10143fc + 10143e0: e0bffb17 ldw r2,-20(fp) + 10143e4: e0bff615 stw r2,-40(fp) + 10143e8: e0bff617 ldw r2,-40(fp) + 10143ec: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_DEL); + 10143f0: 00800f44 movi r2,61 + 10143f4: e0bfff15 stw r2,-4(fp) + 10143f8: 00000806 br 101441c + } + ptcb->OSTCBDelReq = OS_ERR_TASK_DEL_REQ; /* Set flag indicating task to be DEL. */ + 10143fc: e0fffc17 ldw r3,-16(fp) + 1014400: 00800fc4 movi r2,63 + 1014404: 18800dc5 stb r2,55(r3) + 1014408: e0bffb17 ldw r2,-20(fp) + 101440c: e0bff515 stw r2,-44(fp) + 1014410: e0bff517 ldw r2,-44(fp) + 1014414: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_NONE); + 1014418: e03fff15 stw zero,-4(fp) + 101441c: e0bfff17 ldw r2,-4(fp) +} + 1014420: e037883a mov sp,fp + 1014424: df000017 ldw fp,0(sp) + 1014428: dec00104 addi sp,sp,4 + 101442c: f800283a ret + +01014430 : +********************************************************************************************************* +*/ + +#if OS_TASK_NAME_SIZE > 1 +INT8U OSTaskNameGet (INT8U prio, INT8U *pname, INT8U *perr) +{ + 1014430: defff304 addi sp,sp,-52 + 1014434: dfc00c15 stw ra,48(sp) + 1014438: df000b15 stw fp,44(sp) + 101443c: df000b04 addi fp,sp,44 + 1014440: e17ffd15 stw r5,-12(fp) + 1014444: e1bffe15 stw r6,-8(fp) + 1014448: e13ffc05 stb r4,-16(fp) + OS_TCB *ptcb; + INT8U len; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 101444c: e03ff915 stw zero,-28(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + 1014450: e0bffe17 ldw r2,-8(fp) + 1014454: 1004c03a cmpne r2,r2,zero + 1014458: 1000021e bne r2,zero,1014464 + return (0); + 101445c: e03fff15 stw zero,-4(fp) + 1014460: 00005b06 br 10145d0 + } + if (prio > OS_LOWEST_PRIO) { /* Task priority valid ? */ + 1014464: e0bffc03 ldbu r2,-16(fp) + 1014468: 10800570 cmpltui r2,r2,21 + 101446c: 1000081e bne r2,zero,1014490 + if (prio != OS_PRIO_SELF) { + 1014470: e0bffc03 ldbu r2,-16(fp) + 1014474: 10803fe0 cmpeqi r2,r2,255 + 1014478: 1000051e bne r2,zero,1014490 + *perr = OS_ERR_PRIO_INVALID; /* No */ + 101447c: e0fffe17 ldw r3,-8(fp) + 1014480: 00800a84 movi r2,42 + 1014484: 18800005 stb r2,0(r3) + return (0); + 1014488: e03fff15 stw zero,-4(fp) + 101448c: 00005006 br 10145d0 + } + } + if (pname == (INT8U *)0) { /* Is 'pname' a NULL pointer? */ + 1014490: e0bffd17 ldw r2,-12(fp) + 1014494: 1004c03a cmpne r2,r2,zero + 1014498: 1000051e bne r2,zero,10144b0 + *perr = OS_ERR_PNAME_NULL; /* Yes */ + 101449c: e0fffe17 ldw r3,-8(fp) + 10144a0: 00800304 movi r2,12 + 10144a4: 18800005 stb r2,0(r3) + return (0); + 10144a8: e03fff15 stw zero,-4(fp) + 10144ac: 00004806 br 10145d0 + } +#endif + if (OSIntNesting > 0) { /* See if trying to call from an ISR */ + 10144b0: 008040b4 movhi r2,258 + 10144b4: 10b31e04 addi r2,r2,-13192 + 10144b8: 10800003 ldbu r2,0(r2) + 10144bc: 10803fcc andi r2,r2,255 + 10144c0: 1005003a cmpeq r2,r2,zero + 10144c4: 1000051e bne r2,zero,10144dc + *perr = OS_ERR_NAME_GET_ISR; + 10144c8: e0fffe17 ldw r3,-8(fp) + 10144cc: 00800444 movi r2,17 + 10144d0: 18800005 stb r2,0(r3) + return (0); + 10144d4: e03fff15 stw zero,-4(fp) + 10144d8: 00003d06 br 10145d0 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 10144dc: 0005303a rdctl r2,status + 10144e0: e0bff815 stw r2,-32(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 10144e4: e0fff817 ldw r3,-32(fp) + 10144e8: 00bfff84 movi r2,-2 + 10144ec: 1884703a and r2,r3,r2 + 10144f0: 1001703a wrctl status,r2 + + return context; + 10144f4: e0bff817 ldw r2,-32(fp) + } + OS_ENTER_CRITICAL(); + 10144f8: e0bff915 stw r2,-28(fp) + if (prio == OS_PRIO_SELF) { /* See if caller desires it's own name */ + 10144fc: e0bffc03 ldbu r2,-16(fp) + 1014500: 10803fd8 cmpnei r2,r2,255 + 1014504: 1000051e bne r2,zero,101451c + prio = OSTCBCur->OSTCBPrio; + 1014508: 008040b4 movhi r2,258 + 101450c: 10b31f04 addi r2,r2,-13188 + 1014510: 10800017 ldw r2,0(r2) + 1014514: 10800c83 ldbu r2,50(r2) + 1014518: e0bffc05 stb r2,-16(fp) + } + ptcb = OSTCBPrioTbl[prio]; + 101451c: e0bffc03 ldbu r2,-16(fp) + 1014520: 00c040b4 movhi r3,258 + 1014524: 18d9a904 addi r3,r3,26276 + 1014528: 1085883a add r2,r2,r2 + 101452c: 1085883a add r2,r2,r2 + 1014530: 10c5883a add r2,r2,r3 + 1014534: 10800017 ldw r2,0(r2) + 1014538: e0bffb15 stw r2,-20(fp) + if (ptcb == (OS_TCB *)0) { /* Does task exist? */ + 101453c: e0bffb17 ldw r2,-20(fp) + 1014540: 1004c03a cmpne r2,r2,zero + 1014544: 1000091e bne r2,zero,101456c + 1014548: e0bff917 ldw r2,-28(fp) + 101454c: e0bff715 stw r2,-36(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1014550: e0bff717 ldw r2,-36(fp) + 1014554: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); /* No */ + *perr = OS_ERR_TASK_NOT_EXIST; + 1014558: e0fffe17 ldw r3,-8(fp) + 101455c: 008010c4 movi r2,67 + 1014560: 18800005 stb r2,0(r3) + return (0); + 1014564: e03fff15 stw zero,-4(fp) + 1014568: 00001906 br 10145d0 + } + if (ptcb == OS_TCB_RESERVED) { /* Task assigned to a Mutex? */ + 101456c: e0bffb17 ldw r2,-20(fp) + 1014570: 10800058 cmpnei r2,r2,1 + 1014574: 1000091e bne r2,zero,101459c + 1014578: e0bff917 ldw r2,-28(fp) + 101457c: e0bff615 stw r2,-40(fp) + 1014580: e0bff617 ldw r2,-40(fp) + 1014584: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); /* Yes */ + *perr = OS_ERR_TASK_NOT_EXIST; + 1014588: e0fffe17 ldw r3,-8(fp) + 101458c: 008010c4 movi r2,67 + 1014590: 18800005 stb r2,0(r3) + return (0); + 1014594: e03fff15 stw zero,-4(fp) + 1014598: 00000d06 br 10145d0 + } + len = OS_StrCopy(pname, ptcb->OSTCBTaskName); /* Yes, copy name from TCB */ + 101459c: e0bffb17 ldw r2,-20(fp) + 10145a0: 11401304 addi r5,r2,76 + 10145a4: e13ffd17 ldw r4,-12(fp) + 10145a8: 100edfc0 call 100edfc + 10145ac: e0bffa05 stb r2,-24(fp) + 10145b0: e0bff917 ldw r2,-28(fp) + 10145b4: e0bff515 stw r2,-44(fp) + 10145b8: e0bff517 ldw r2,-44(fp) + 10145bc: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + 10145c0: e0bffe17 ldw r2,-8(fp) + 10145c4: 10000005 stb zero,0(r2) + return (len); + 10145c8: e0bffa03 ldbu r2,-24(fp) + 10145cc: e0bfff15 stw r2,-4(fp) + 10145d0: e0bfff17 ldw r2,-4(fp) +} + 10145d4: e037883a mov sp,fp + 10145d8: dfc00117 ldw ra,4(sp) + 10145dc: df000017 ldw fp,0(sp) + 10145e0: dec00204 addi sp,sp,8 + 10145e4: f800283a ret + +010145e8 : +* Returns : None +********************************************************************************************************* +*/ +#if OS_TASK_NAME_SIZE > 1 +void OSTaskNameSet (INT8U prio, INT8U *pname, INT8U *perr) +{ + 10145e8: defff304 addi sp,sp,-52 + 10145ec: dfc00c15 stw ra,48(sp) + 10145f0: df000b15 stw fp,44(sp) + 10145f4: df000b04 addi fp,sp,44 + 10145f8: e17ffe15 stw r5,-8(fp) + 10145fc: e1bfff15 stw r6,-4(fp) + 1014600: e13ffd05 stb r4,-12(fp) + INT8U len; + OS_TCB *ptcb; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 1014604: e03ffa15 stw zero,-24(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + 1014608: e0bfff17 ldw r2,-4(fp) + 101460c: 1005003a cmpeq r2,r2,zero + 1014610: 1000611e bne r2,zero,1014798 + return; + } + if (prio > OS_LOWEST_PRIO) { /* Task priority valid ? */ + 1014614: e0bffd03 ldbu r2,-12(fp) + 1014618: 10800570 cmpltui r2,r2,21 + 101461c: 1000071e bne r2,zero,101463c + if (prio != OS_PRIO_SELF) { + 1014620: e0bffd03 ldbu r2,-12(fp) + 1014624: 10803fe0 cmpeqi r2,r2,255 + 1014628: 1000041e bne r2,zero,101463c + *perr = OS_ERR_PRIO_INVALID; /* No */ + 101462c: e0ffff17 ldw r3,-4(fp) + 1014630: 00800a84 movi r2,42 + 1014634: 18800005 stb r2,0(r3) + return; + 1014638: 00005706 br 1014798 + } + } + if (pname == (INT8U *)0) { /* Is 'pname' a NULL pointer? */ + 101463c: e0bffe17 ldw r2,-8(fp) + 1014640: 1004c03a cmpne r2,r2,zero + 1014644: 1000041e bne r2,zero,1014658 + *perr = OS_ERR_PNAME_NULL; /* Yes */ + 1014648: e0ffff17 ldw r3,-4(fp) + 101464c: 00800304 movi r2,12 + 1014650: 18800005 stb r2,0(r3) + return; + 1014654: 00005006 br 1014798 + } +#endif + if (OSIntNesting > 0) { /* See if trying to call from an ISR */ + 1014658: 008040b4 movhi r2,258 + 101465c: 10b31e04 addi r2,r2,-13192 + 1014660: 10800003 ldbu r2,0(r2) + 1014664: 10803fcc andi r2,r2,255 + 1014668: 1005003a cmpeq r2,r2,zero + 101466c: 1000041e bne r2,zero,1014680 + *perr = OS_ERR_NAME_SET_ISR; + 1014670: e0ffff17 ldw r3,-4(fp) + 1014674: 00800484 movi r2,18 + 1014678: 18800005 stb r2,0(r3) + return; + 101467c: 00004606 br 1014798 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1014680: 0005303a rdctl r2,status + 1014684: e0bff915 stw r2,-28(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1014688: e0fff917 ldw r3,-28(fp) + 101468c: 00bfff84 movi r2,-2 + 1014690: 1884703a and r2,r3,r2 + 1014694: 1001703a wrctl status,r2 + + return context; + 1014698: e0bff917 ldw r2,-28(fp) + } + OS_ENTER_CRITICAL(); + 101469c: e0bffa15 stw r2,-24(fp) + if (prio == OS_PRIO_SELF) { /* See if caller desires to set it's own name */ + 10146a0: e0bffd03 ldbu r2,-12(fp) + 10146a4: 10803fd8 cmpnei r2,r2,255 + 10146a8: 1000051e bne r2,zero,10146c0 + prio = OSTCBCur->OSTCBPrio; + 10146ac: 008040b4 movhi r2,258 + 10146b0: 10b31f04 addi r2,r2,-13188 + 10146b4: 10800017 ldw r2,0(r2) + 10146b8: 10800c83 ldbu r2,50(r2) + 10146bc: e0bffd05 stb r2,-12(fp) + } + ptcb = OSTCBPrioTbl[prio]; + 10146c0: e0bffd03 ldbu r2,-12(fp) + 10146c4: 00c040b4 movhi r3,258 + 10146c8: 18d9a904 addi r3,r3,26276 + 10146cc: 1085883a add r2,r2,r2 + 10146d0: 1085883a add r2,r2,r2 + 10146d4: 10c5883a add r2,r2,r3 + 10146d8: 10800017 ldw r2,0(r2) + 10146dc: e0bffb15 stw r2,-20(fp) + if (ptcb == (OS_TCB *)0) { /* Does task exist? */ + 10146e0: e0bffb17 ldw r2,-20(fp) + 10146e4: 1004c03a cmpne r2,r2,zero + 10146e8: 1000081e bne r2,zero,101470c + 10146ec: e0bffa17 ldw r2,-24(fp) + 10146f0: e0bff815 stw r2,-32(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 10146f4: e0bff817 ldw r2,-32(fp) + 10146f8: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); /* No */ + *perr = OS_ERR_TASK_NOT_EXIST; + 10146fc: e0ffff17 ldw r3,-4(fp) + 1014700: 008010c4 movi r2,67 + 1014704: 18800005 stb r2,0(r3) + return; + 1014708: 00002306 br 1014798 + } + if (ptcb == OS_TCB_RESERVED) { /* Task assigned to a Mutex? */ + 101470c: e0bffb17 ldw r2,-20(fp) + 1014710: 10800058 cmpnei r2,r2,1 + 1014714: 1000081e bne r2,zero,1014738 + 1014718: e0bffa17 ldw r2,-24(fp) + 101471c: e0bff715 stw r2,-36(fp) + 1014720: e0bff717 ldw r2,-36(fp) + 1014724: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); /* Yes */ + *perr = OS_ERR_TASK_NOT_EXIST; + 1014728: e0ffff17 ldw r3,-4(fp) + 101472c: 008010c4 movi r2,67 + 1014730: 18800005 stb r2,0(r3) + return; + 1014734: 00001806 br 1014798 + } + len = OS_StrLen(pname); /* Yes, Can we fit the string in the TCB? */ + 1014738: e13ffe17 ldw r4,-8(fp) + 101473c: 100ee7c0 call 100ee7c + 1014740: e0bffc05 stb r2,-16(fp) + if (len > (OS_TASK_NAME_SIZE - 1)) { /* No */ + 1014744: e0bffc03 ldbu r2,-16(fp) + 1014748: 10800830 cmpltui r2,r2,32 + 101474c: 1000081e bne r2,zero,1014770 + 1014750: e0bffa17 ldw r2,-24(fp) + 1014754: e0bff615 stw r2,-40(fp) + 1014758: e0bff617 ldw r2,-40(fp) + 101475c: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + *perr = OS_ERR_TASK_NAME_TOO_LONG; + 1014760: e0ffff17 ldw r3,-4(fp) + 1014764: 00801044 movi r2,65 + 1014768: 18800005 stb r2,0(r3) + return; + 101476c: 00000a06 br 1014798 + } + (void)OS_StrCopy(ptcb->OSTCBTaskName, pname); /* Yes, copy to TCB */ + 1014770: e0bffb17 ldw r2,-20(fp) + 1014774: 11001304 addi r4,r2,76 + 1014778: e17ffe17 ldw r5,-8(fp) + 101477c: 100edfc0 call 100edfc + 1014780: e0bffa17 ldw r2,-24(fp) + 1014784: e0bff515 stw r2,-44(fp) + 1014788: e0bff517 ldw r2,-44(fp) + 101478c: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + 1014790: e0bfff17 ldw r2,-4(fp) + 1014794: 10000005 stb zero,0(r2) +} + 1014798: e037883a mov sp,fp + 101479c: dfc00117 ldw ra,4(sp) + 10147a0: df000017 ldw fp,0(sp) + 10147a4: dec00204 addi sp,sp,8 + 10147a8: f800283a ret + +010147ac : +********************************************************************************************************* +*/ + +#if OS_TASK_SUSPEND_EN > 0 +INT8U OSTaskResume (INT8U prio) +{ + 10147ac: defff304 addi sp,sp,-52 + 10147b0: dfc00c15 stw ra,48(sp) + 10147b4: df000b15 stw fp,44(sp) + 10147b8: df000b04 addi fp,sp,44 + 10147bc: e13ffe05 stb r4,-8(fp) + OS_TCB *ptcb; +#if OS_CRITICAL_METHOD == 3 /* Storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 10147c0: e03ffc15 stw zero,-16(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (prio >= OS_LOWEST_PRIO) { /* Make sure task priority is valid */ + 10147c4: e0bffe03 ldbu r2,-8(fp) + 10147c8: 10800530 cmpltui r2,r2,20 + 10147cc: 1000031e bne r2,zero,10147dc + return (OS_ERR_PRIO_INVALID); + 10147d0: 00800a84 movi r2,42 + 10147d4: e0bfff15 stw r2,-4(fp) + 10147d8: 00007406 br 10149ac +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 10147dc: 0005303a rdctl r2,status + 10147e0: e0bffb15 stw r2,-20(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 10147e4: e0fffb17 ldw r3,-20(fp) + 10147e8: 00bfff84 movi r2,-2 + 10147ec: 1884703a and r2,r3,r2 + 10147f0: 1001703a wrctl status,r2 + + return context; + 10147f4: e0bffb17 ldw r2,-20(fp) + } +#endif + OS_ENTER_CRITICAL(); + 10147f8: e0bffc15 stw r2,-16(fp) + ptcb = OSTCBPrioTbl[prio]; + 10147fc: e0bffe03 ldbu r2,-8(fp) + 1014800: 00c040b4 movhi r3,258 + 1014804: 18d9a904 addi r3,r3,26276 + 1014808: 1085883a add r2,r2,r2 + 101480c: 1085883a add r2,r2,r2 + 1014810: 10c5883a add r2,r2,r3 + 1014814: 10800017 ldw r2,0(r2) + 1014818: e0bffd15 stw r2,-12(fp) + if (ptcb == (OS_TCB *)0) { /* Task to suspend must exist */ + 101481c: e0bffd17 ldw r2,-12(fp) + 1014820: 1004c03a cmpne r2,r2,zero + 1014824: 1000071e bne r2,zero,1014844 + 1014828: e0bffc17 ldw r2,-16(fp) + 101482c: e0bffa15 stw r2,-24(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1014830: e0bffa17 ldw r2,-24(fp) + 1014834: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_RESUME_PRIO); + 1014838: 00801184 movi r2,70 + 101483c: e0bfff15 stw r2,-4(fp) + 1014840: 00005a06 br 10149ac + } + if (ptcb == OS_TCB_RESERVED) { /* See if assigned to Mutex */ + 1014844: e0bffd17 ldw r2,-12(fp) + 1014848: 10800058 cmpnei r2,r2,1 + 101484c: 1000071e bne r2,zero,101486c + 1014850: e0bffc17 ldw r2,-16(fp) + 1014854: e0bff915 stw r2,-28(fp) + 1014858: e0bff917 ldw r2,-28(fp) + 101485c: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_NOT_EXIST); + 1014860: 008010c4 movi r2,67 + 1014864: e0bfff15 stw r2,-4(fp) + 1014868: 00005006 br 10149ac + } + if ((ptcb->OSTCBStat & OS_STAT_SUSPEND) != OS_STAT_RDY) { /* Task must be suspended */ + 101486c: e0bffd17 ldw r2,-12(fp) + 1014870: 10800c03 ldbu r2,48(r2) + 1014874: 10803fcc andi r2,r2,255 + 1014878: 1080020c andi r2,r2,8 + 101487c: 1005003a cmpeq r2,r2,zero + 1014880: 1000441e bne r2,zero,1014994 + ptcb->OSTCBStat &= ~(INT8U)OS_STAT_SUSPEND; /* Remove suspension */ + 1014884: e0bffd17 ldw r2,-12(fp) + 1014888: 10c00c03 ldbu r3,48(r2) + 101488c: 00bffdc4 movi r2,-9 + 1014890: 1884703a and r2,r3,r2 + 1014894: 1007883a mov r3,r2 + 1014898: e0bffd17 ldw r2,-12(fp) + 101489c: 10c00c05 stb r3,48(r2) + if (ptcb->OSTCBStat == OS_STAT_RDY) { /* See if task is now ready */ + 10148a0: e0bffd17 ldw r2,-12(fp) + 10148a4: 10800c03 ldbu r2,48(r2) + 10148a8: 10803fcc andi r2,r2,255 + 10148ac: 1004c03a cmpne r2,r2,zero + 10148b0: 1000321e bne r2,zero,101497c + if (ptcb->OSTCBDly == 0) { + 10148b4: e0bffd17 ldw r2,-12(fp) + 10148b8: 10800b8b ldhu r2,46(r2) + 10148bc: 10bfffcc andi r2,r2,65535 + 10148c0: 1004c03a cmpne r2,r2,zero + 10148c4: 1000281e bne r2,zero,1014968 + OSRdyGrp |= ptcb->OSTCBBitY; /* Yes, Make task ready to run */ + 10148c8: e0bffd17 ldw r2,-12(fp) + 10148cc: 10c00d83 ldbu r3,54(r2) + 10148d0: 008040b4 movhi r2,258 + 10148d4: 10b31c04 addi r2,r2,-13200 + 10148d8: 10800003 ldbu r2,0(r2) + 10148dc: 1884b03a or r2,r3,r2 + 10148e0: 1007883a mov r3,r2 + 10148e4: 008040b4 movhi r2,258 + 10148e8: 10b31c04 addi r2,r2,-13200 + 10148ec: 10c00005 stb r3,0(r2) + OSRdyTbl[ptcb->OSTCBY] |= ptcb->OSTCBBitX; + 10148f0: e0bffd17 ldw r2,-12(fp) + 10148f4: 10800d03 ldbu r2,52(r2) + 10148f8: 11003fcc andi r4,r2,255 + 10148fc: e0bffd17 ldw r2,-12(fp) + 1014900: 10800d03 ldbu r2,52(r2) + 1014904: 10c03fcc andi r3,r2,255 + 1014908: 008040b4 movhi r2,258 + 101490c: 10b31c44 addi r2,r2,-13199 + 1014910: 10c5883a add r2,r2,r3 + 1014914: 10c00003 ldbu r3,0(r2) + 1014918: e0bffd17 ldw r2,-12(fp) + 101491c: 10800d43 ldbu r2,53(r2) + 1014920: 1884b03a or r2,r3,r2 + 1014924: 1007883a mov r3,r2 + 1014928: 008040b4 movhi r2,258 + 101492c: 10b31c44 addi r2,r2,-13199 + 1014930: 1105883a add r2,r2,r4 + 1014934: 10c00005 stb r3,0(r2) + 1014938: e0bffc17 ldw r2,-16(fp) + 101493c: e0bff815 stw r2,-32(fp) + 1014940: e0bff817 ldw r2,-32(fp) + 1014944: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + if (OSRunning == OS_TRUE) { + 1014948: 008040b4 movhi r2,258 + 101494c: 10b31044 addi r2,r2,-13247 + 1014950: 10800003 ldbu r2,0(r2) + 1014954: 10803fcc andi r2,r2,255 + 1014958: 10800058 cmpnei r2,r2,1 + 101495c: 10000b1e bne r2,zero,101498c + OS_Sched(); /* Find new highest priority task */ + 1014960: 100ecb80 call 100ecb8 + 1014964: 00000906 br 101498c + 1014968: e0bffc17 ldw r2,-16(fp) + 101496c: e0bff715 stw r2,-36(fp) + 1014970: e0bff717 ldw r2,-36(fp) + 1014974: 1001703a wrctl status,r2 + 1014978: 00000406 br 101498c + 101497c: e0bffc17 ldw r2,-16(fp) + 1014980: e0bff615 stw r2,-40(fp) + 1014984: e0bff617 ldw r2,-40(fp) + 1014988: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + } + } else { /* Must be pending on event */ + OS_EXIT_CRITICAL(); + } + return (OS_ERR_NONE); + 101498c: e03fff15 stw zero,-4(fp) + 1014990: 00000606 br 10149ac + 1014994: e0bffc17 ldw r2,-16(fp) + 1014998: e0bff515 stw r2,-44(fp) + 101499c: e0bff517 ldw r2,-44(fp) + 10149a0: 1001703a wrctl status,r2 + } + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_NOT_SUSPENDED); + 10149a4: 00801104 movi r2,68 + 10149a8: e0bfff15 stw r2,-4(fp) + 10149ac: e0bfff17 ldw r2,-4(fp) +} + 10149b0: e037883a mov sp,fp + 10149b4: dfc00117 ldw ra,4(sp) + 10149b8: df000017 ldw fp,0(sp) + 10149bc: dec00204 addi sp,sp,8 + 10149c0: f800283a ret + +010149c4 : +* OS_ERR_PDATA_NULL if 'p_stk_data' is a NULL pointer +********************************************************************************************************* +*/ +#if (OS_TASK_STAT_STK_CHK_EN > 0) && (OS_TASK_CREATE_EXT_EN > 0) +INT8U OSTaskStkChk (INT8U prio, OS_STK_DATA *p_stk_data) +{ + 10149c4: defff204 addi sp,sp,-56 + 10149c8: df000d15 stw fp,52(sp) + 10149cc: df000d04 addi fp,sp,52 + 10149d0: e17ffe15 stw r5,-8(fp) + 10149d4: e13ffd05 stb r4,-12(fp) + OS_TCB *ptcb; + OS_STK *pchk; + INT32U nfree; + INT32U size; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 10149d8: e03ff815 stw zero,-32(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (prio > OS_LOWEST_PRIO) { /* Make sure task priority is valid */ + 10149dc: e0bffd03 ldbu r2,-12(fp) + 10149e0: 10800570 cmpltui r2,r2,21 + 10149e4: 1000061e bne r2,zero,1014a00 + if (prio != OS_PRIO_SELF) { + 10149e8: e0bffd03 ldbu r2,-12(fp) + 10149ec: 10803fe0 cmpeqi r2,r2,255 + 10149f0: 1000031e bne r2,zero,1014a00 + return (OS_ERR_PRIO_INVALID); + 10149f4: 00800a84 movi r2,42 + 10149f8: e0bfff15 stw r2,-4(fp) + 10149fc: 00006b06 br 1014bac + } + } + if (p_stk_data == (OS_STK_DATA *)0) { /* Validate 'p_stk_data' */ + 1014a00: e0bffe17 ldw r2,-8(fp) + 1014a04: 1004c03a cmpne r2,r2,zero + 1014a08: 1000031e bne r2,zero,1014a18 + return (OS_ERR_PDATA_NULL); + 1014a0c: 00800244 movi r2,9 + 1014a10: e0bfff15 stw r2,-4(fp) + 1014a14: 00006506 br 1014bac + } +#endif + p_stk_data->OSFree = 0; /* Assume failure, set to 0 size */ + 1014a18: e0bffe17 ldw r2,-8(fp) + 1014a1c: 10000015 stw zero,0(r2) + p_stk_data->OSUsed = 0; + 1014a20: e0bffe17 ldw r2,-8(fp) + 1014a24: 10000115 stw zero,4(r2) +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1014a28: 0005303a rdctl r2,status + 1014a2c: e0bff715 stw r2,-36(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1014a30: e0fff717 ldw r3,-36(fp) + 1014a34: 00bfff84 movi r2,-2 + 1014a38: 1884703a and r2,r3,r2 + 1014a3c: 1001703a wrctl status,r2 + + return context; + 1014a40: e0bff717 ldw r2,-36(fp) + OS_ENTER_CRITICAL(); + 1014a44: e0bff815 stw r2,-32(fp) + if (prio == OS_PRIO_SELF) { /* See if check for SELF */ + 1014a48: e0bffd03 ldbu r2,-12(fp) + 1014a4c: 10803fd8 cmpnei r2,r2,255 + 1014a50: 1000051e bne r2,zero,1014a68 + prio = OSTCBCur->OSTCBPrio; + 1014a54: 008040b4 movhi r2,258 + 1014a58: 10b31f04 addi r2,r2,-13188 + 1014a5c: 10800017 ldw r2,0(r2) + 1014a60: 10800c83 ldbu r2,50(r2) + 1014a64: e0bffd05 stb r2,-12(fp) + } + ptcb = OSTCBPrioTbl[prio]; + 1014a68: e0bffd03 ldbu r2,-12(fp) + 1014a6c: 00c040b4 movhi r3,258 + 1014a70: 18d9a904 addi r3,r3,26276 + 1014a74: 1085883a add r2,r2,r2 + 1014a78: 1085883a add r2,r2,r2 + 1014a7c: 10c5883a add r2,r2,r3 + 1014a80: 10800017 ldw r2,0(r2) + 1014a84: e0bffc15 stw r2,-16(fp) + if (ptcb == (OS_TCB *)0) { /* Make sure task exist */ + 1014a88: e0bffc17 ldw r2,-16(fp) + 1014a8c: 1004c03a cmpne r2,r2,zero + 1014a90: 1000071e bne r2,zero,1014ab0 + 1014a94: e0bff817 ldw r2,-32(fp) + 1014a98: e0bff615 stw r2,-40(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1014a9c: e0bff617 ldw r2,-40(fp) + 1014aa0: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_NOT_EXIST); + 1014aa4: 008010c4 movi r2,67 + 1014aa8: e0bfff15 stw r2,-4(fp) + 1014aac: 00003f06 br 1014bac + } + if (ptcb == OS_TCB_RESERVED) { + 1014ab0: e0bffc17 ldw r2,-16(fp) + 1014ab4: 10800058 cmpnei r2,r2,1 + 1014ab8: 1000071e bne r2,zero,1014ad8 + 1014abc: e0bff817 ldw r2,-32(fp) + 1014ac0: e0bff515 stw r2,-44(fp) + 1014ac4: e0bff517 ldw r2,-44(fp) + 1014ac8: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_NOT_EXIST); + 1014acc: 008010c4 movi r2,67 + 1014ad0: e0bfff15 stw r2,-4(fp) + 1014ad4: 00003506 br 1014bac + } + if ((ptcb->OSTCBOpt & OS_TASK_OPT_STK_CHK) == 0) { /* Make sure stack checking option is set */ + 1014ad8: e0bffc17 ldw r2,-16(fp) + 1014adc: 1080040b ldhu r2,16(r2) + 1014ae0: 10bfffcc andi r2,r2,65535 + 1014ae4: 1080004c andi r2,r2,1 + 1014ae8: 1004c03a cmpne r2,r2,zero + 1014aec: 1000071e bne r2,zero,1014b0c + 1014af0: e0bff817 ldw r2,-32(fp) + 1014af4: e0bff415 stw r2,-48(fp) + 1014af8: e0bff417 ldw r2,-48(fp) + 1014afc: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_OPT); + 1014b00: 00801144 movi r2,69 + 1014b04: e0bfff15 stw r2,-4(fp) + 1014b08: 00002806 br 1014bac + } + nfree = 0; + 1014b0c: e03ffa15 stw zero,-24(fp) + size = ptcb->OSTCBStkSize; + 1014b10: e0bffc17 ldw r2,-16(fp) + 1014b14: 10800317 ldw r2,12(r2) + 1014b18: e0bff915 stw r2,-28(fp) + pchk = ptcb->OSTCBStkBottom; + 1014b1c: e0bffc17 ldw r2,-16(fp) + 1014b20: 10800217 ldw r2,8(r2) + 1014b24: e0bffb15 stw r2,-20(fp) + 1014b28: e0bff817 ldw r2,-32(fp) + 1014b2c: e0bff315 stw r2,-52(fp) + 1014b30: e0bff317 ldw r2,-52(fp) + 1014b34: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); +#if OS_STK_GROWTH == 1 + while (*pchk++ == (OS_STK)0) { /* Compute the number of zero entries on the stk */ + 1014b38: 00000306 br 1014b48 + nfree++; + 1014b3c: e0bffa17 ldw r2,-24(fp) + 1014b40: 10800044 addi r2,r2,1 + 1014b44: e0bffa15 stw r2,-24(fp) + nfree = 0; + size = ptcb->OSTCBStkSize; + pchk = ptcb->OSTCBStkBottom; + OS_EXIT_CRITICAL(); +#if OS_STK_GROWTH == 1 + while (*pchk++ == (OS_STK)0) { /* Compute the number of zero entries on the stk */ + 1014b48: e0bffb17 ldw r2,-20(fp) + 1014b4c: 10800017 ldw r2,0(r2) + 1014b50: 1005003a cmpeq r2,r2,zero + 1014b54: 1007883a mov r3,r2 + 1014b58: e0bffb17 ldw r2,-20(fp) + 1014b5c: 10800104 addi r2,r2,4 + 1014b60: e0bffb15 stw r2,-20(fp) + 1014b64: 18803fcc andi r2,r3,255 + 1014b68: 1004c03a cmpne r2,r2,zero + 1014b6c: 103ff31e bne r2,zero,1014b3c +#else + while (*pchk-- == (OS_STK)0) { + nfree++; + } +#endif + p_stk_data->OSFree = nfree * sizeof(OS_STK); /* Compute number of free bytes on the stack */ + 1014b70: e0bffa17 ldw r2,-24(fp) + 1014b74: 1085883a add r2,r2,r2 + 1014b78: 1085883a add r2,r2,r2 + 1014b7c: 1007883a mov r3,r2 + 1014b80: e0bffe17 ldw r2,-8(fp) + 1014b84: 10c00015 stw r3,0(r2) + p_stk_data->OSUsed = (size - nfree) * sizeof(OS_STK); /* Compute number of bytes used on the stack */ + 1014b88: e0fff917 ldw r3,-28(fp) + 1014b8c: e0bffa17 ldw r2,-24(fp) + 1014b90: 1885c83a sub r2,r3,r2 + 1014b94: 1085883a add r2,r2,r2 + 1014b98: 1085883a add r2,r2,r2 + 1014b9c: 1007883a mov r3,r2 + 1014ba0: e0bffe17 ldw r2,-8(fp) + 1014ba4: 10c00115 stw r3,4(r2) + return (OS_ERR_NONE); + 1014ba8: e03fff15 stw zero,-4(fp) + 1014bac: e0bfff17 ldw r2,-4(fp) +} + 1014bb0: e037883a mov sp,fp + 1014bb4: df000017 ldw fp,0(sp) + 1014bb8: dec00104 addi sp,sp,4 + 1014bbc: f800283a ret + +01014bc0 : +********************************************************************************************************* +*/ + +#if OS_TASK_SUSPEND_EN > 0 +INT8U OSTaskSuspend (INT8U prio) +{ + 1014bc0: defff404 addi sp,sp,-48 + 1014bc4: dfc00b15 stw ra,44(sp) + 1014bc8: df000a15 stw fp,40(sp) + 1014bcc: df000a04 addi fp,sp,40 + 1014bd0: e13ffe05 stb r4,-8(fp) + BOOLEAN self; + OS_TCB *ptcb; + INT8U y; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 1014bd4: e03ffa15 stw zero,-24(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (prio == OS_TASK_IDLE_PRIO) { /* Not allowed to suspend idle task */ + 1014bd8: e0bffe03 ldbu r2,-8(fp) + 1014bdc: 10800518 cmpnei r2,r2,20 + 1014be0: 1000031e bne r2,zero,1014bf0 + return (OS_ERR_TASK_SUSPEND_IDLE); + 1014be4: 008011c4 movi r2,71 + 1014be8: e0bfff15 stw r2,-4(fp) + 1014bec: 00007906 br 1014dd4 + } + if (prio >= OS_LOWEST_PRIO) { /* Task priority valid ? */ + 1014bf0: e0bffe03 ldbu r2,-8(fp) + 1014bf4: 10800530 cmpltui r2,r2,20 + 1014bf8: 1000061e bne r2,zero,1014c14 + if (prio != OS_PRIO_SELF) { + 1014bfc: e0bffe03 ldbu r2,-8(fp) + 1014c00: 10803fe0 cmpeqi r2,r2,255 + 1014c04: 1000031e bne r2,zero,1014c14 + return (OS_ERR_PRIO_INVALID); + 1014c08: 00800a84 movi r2,42 + 1014c0c: e0bfff15 stw r2,-4(fp) + 1014c10: 00007006 br 1014dd4 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1014c14: 0005303a rdctl r2,status + 1014c18: e0bff915 stw r2,-28(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1014c1c: e0fff917 ldw r3,-28(fp) + 1014c20: 00bfff84 movi r2,-2 + 1014c24: 1884703a and r2,r3,r2 + 1014c28: 1001703a wrctl status,r2 + + return context; + 1014c2c: e0bff917 ldw r2,-28(fp) + } + } +#endif + OS_ENTER_CRITICAL(); + 1014c30: e0bffa15 stw r2,-24(fp) + if (prio == OS_PRIO_SELF) { /* See if suspend SELF */ + 1014c34: e0bffe03 ldbu r2,-8(fp) + 1014c38: 10803fd8 cmpnei r2,r2,255 + 1014c3c: 1000081e bne r2,zero,1014c60 + prio = OSTCBCur->OSTCBPrio; + 1014c40: 008040b4 movhi r2,258 + 1014c44: 10b31f04 addi r2,r2,-13188 + 1014c48: 10800017 ldw r2,0(r2) + 1014c4c: 10800c83 ldbu r2,50(r2) + 1014c50: e0bffe05 stb r2,-8(fp) + self = OS_TRUE; + 1014c54: 00800044 movi r2,1 + 1014c58: e0bffd05 stb r2,-12(fp) + 1014c5c: 00000b06 br 1014c8c + } else if (prio == OSTCBCur->OSTCBPrio) { /* See if suspending self */ + 1014c60: 008040b4 movhi r2,258 + 1014c64: 10b31f04 addi r2,r2,-13188 + 1014c68: 10800017 ldw r2,0(r2) + 1014c6c: 10800c83 ldbu r2,50(r2) + 1014c70: 10c03fcc andi r3,r2,255 + 1014c74: e0bffe03 ldbu r2,-8(fp) + 1014c78: 1880031e bne r3,r2,1014c88 + self = OS_TRUE; + 1014c7c: 00800044 movi r2,1 + 1014c80: e0bffd05 stb r2,-12(fp) + 1014c84: 00000106 br 1014c8c + } else { + self = OS_FALSE; /* No suspending another task */ + 1014c88: e03ffd05 stb zero,-12(fp) + } + ptcb = OSTCBPrioTbl[prio]; + 1014c8c: e0bffe03 ldbu r2,-8(fp) + 1014c90: 00c040b4 movhi r3,258 + 1014c94: 18d9a904 addi r3,r3,26276 + 1014c98: 1085883a add r2,r2,r2 + 1014c9c: 1085883a add r2,r2,r2 + 1014ca0: 10c5883a add r2,r2,r3 + 1014ca4: 10800017 ldw r2,0(r2) + 1014ca8: e0bffc15 stw r2,-16(fp) + if (ptcb == (OS_TCB *)0) { /* Task to suspend must exist */ + 1014cac: e0bffc17 ldw r2,-16(fp) + 1014cb0: 1004c03a cmpne r2,r2,zero + 1014cb4: 1000071e bne r2,zero,1014cd4 + 1014cb8: e0bffa17 ldw r2,-24(fp) + 1014cbc: e0bff815 stw r2,-32(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1014cc0: e0bff817 ldw r2,-32(fp) + 1014cc4: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_SUSPEND_PRIO); + 1014cc8: 00801204 movi r2,72 + 1014ccc: e0bfff15 stw r2,-4(fp) + 1014cd0: 00004006 br 1014dd4 + } + if (ptcb == OS_TCB_RESERVED) { /* See if assigned to Mutex */ + 1014cd4: e0bffc17 ldw r2,-16(fp) + 1014cd8: 10800058 cmpnei r2,r2,1 + 1014cdc: 1000071e bne r2,zero,1014cfc + 1014ce0: e0bffa17 ldw r2,-24(fp) + 1014ce4: e0bff715 stw r2,-36(fp) + 1014ce8: e0bff717 ldw r2,-36(fp) + 1014cec: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_NOT_EXIST); + 1014cf0: 008010c4 movi r2,67 + 1014cf4: e0bfff15 stw r2,-4(fp) + 1014cf8: 00003606 br 1014dd4 + } + y = ptcb->OSTCBY; + 1014cfc: e0bffc17 ldw r2,-16(fp) + 1014d00: 10800d03 ldbu r2,52(r2) + 1014d04: e0bffb05 stb r2,-20(fp) + OSRdyTbl[y] &= ~ptcb->OSTCBBitX; /* Make task not ready */ + 1014d08: e13ffb03 ldbu r4,-20(fp) + 1014d0c: e0fffb03 ldbu r3,-20(fp) + 1014d10: 008040b4 movhi r2,258 + 1014d14: 10b31c44 addi r2,r2,-13199 + 1014d18: 10c5883a add r2,r2,r3 + 1014d1c: 10800003 ldbu r2,0(r2) + 1014d20: 1007883a mov r3,r2 + 1014d24: e0bffc17 ldw r2,-16(fp) + 1014d28: 10800d43 ldbu r2,53(r2) + 1014d2c: 0084303a nor r2,zero,r2 + 1014d30: 1884703a and r2,r3,r2 + 1014d34: 1007883a mov r3,r2 + 1014d38: 008040b4 movhi r2,258 + 1014d3c: 10b31c44 addi r2,r2,-13199 + 1014d40: 1105883a add r2,r2,r4 + 1014d44: 10c00005 stb r3,0(r2) + if (OSRdyTbl[y] == 0) { + 1014d48: e0fffb03 ldbu r3,-20(fp) + 1014d4c: 008040b4 movhi r2,258 + 1014d50: 10b31c44 addi r2,r2,-13199 + 1014d54: 10c5883a add r2,r2,r3 + 1014d58: 10800003 ldbu r2,0(r2) + 1014d5c: 10803fcc andi r2,r2,255 + 1014d60: 1004c03a cmpne r2,r2,zero + 1014d64: 10000c1e bne r2,zero,1014d98 + OSRdyGrp &= ~ptcb->OSTCBBitY; + 1014d68: e0bffc17 ldw r2,-16(fp) + 1014d6c: 10800d83 ldbu r2,54(r2) + 1014d70: 0084303a nor r2,zero,r2 + 1014d74: 1007883a mov r3,r2 + 1014d78: 008040b4 movhi r2,258 + 1014d7c: 10b31c04 addi r2,r2,-13200 + 1014d80: 10800003 ldbu r2,0(r2) + 1014d84: 1884703a and r2,r3,r2 + 1014d88: 1007883a mov r3,r2 + 1014d8c: 008040b4 movhi r2,258 + 1014d90: 10b31c04 addi r2,r2,-13200 + 1014d94: 10c00005 stb r3,0(r2) + } + ptcb->OSTCBStat |= OS_STAT_SUSPEND; /* Status of task is 'SUSPENDED' */ + 1014d98: e0bffc17 ldw r2,-16(fp) + 1014d9c: 10800c03 ldbu r2,48(r2) + 1014da0: 10800214 ori r2,r2,8 + 1014da4: 1007883a mov r3,r2 + 1014da8: e0bffc17 ldw r2,-16(fp) + 1014dac: 10c00c05 stb r3,48(r2) + 1014db0: e0bffa17 ldw r2,-24(fp) + 1014db4: e0bff615 stw r2,-40(fp) + 1014db8: e0bff617 ldw r2,-40(fp) + 1014dbc: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + if (self == OS_TRUE) { /* Context switch only if SELF */ + 1014dc0: e0bffd03 ldbu r2,-12(fp) + 1014dc4: 10800058 cmpnei r2,r2,1 + 1014dc8: 1000011e bne r2,zero,1014dd0 + OS_Sched(); /* Find new highest priority task */ + 1014dcc: 100ecb80 call 100ecb8 + } + return (OS_ERR_NONE); + 1014dd0: e03fff15 stw zero,-4(fp) + 1014dd4: e0bfff17 ldw r2,-4(fp) +} + 1014dd8: e037883a mov sp,fp + 1014ddc: dfc00117 ldw ra,4(sp) + 1014de0: df000017 ldw fp,0(sp) + 1014de4: dec00204 addi sp,sp,8 + 1014de8: f800283a ret + +01014dec : +********************************************************************************************************* +*/ + +#if OS_TASK_QUERY_EN > 0 +INT8U OSTaskQuery (INT8U prio, OS_TCB *p_task_data) +{ + 1014dec: defff504 addi sp,sp,-44 + 1014df0: dfc00a15 stw ra,40(sp) + 1014df4: df000915 stw fp,36(sp) + 1014df8: df000904 addi fp,sp,36 + 1014dfc: e17ffe15 stw r5,-8(fp) + 1014e00: e13ffd05 stb r4,-12(fp) + OS_TCB *ptcb; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 1014e04: e03ffb15 stw zero,-20(fp) +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (prio > OS_LOWEST_PRIO) { /* Task priority valid ? */ + 1014e08: e0bffd03 ldbu r2,-12(fp) + 1014e0c: 10800570 cmpltui r2,r2,21 + 1014e10: 1000061e bne r2,zero,1014e2c + if (prio != OS_PRIO_SELF) { + 1014e14: e0bffd03 ldbu r2,-12(fp) + 1014e18: 10803fe0 cmpeqi r2,r2,255 + 1014e1c: 1000031e bne r2,zero,1014e2c + return (OS_ERR_PRIO_INVALID); + 1014e20: 00800a84 movi r2,42 + 1014e24: e0bfff15 stw r2,-4(fp) + 1014e28: 00003b06 br 1014f18 + } + } + if (p_task_data == (OS_TCB *)0) { /* Validate 'p_task_data' */ + 1014e2c: e0bffe17 ldw r2,-8(fp) + 1014e30: 1004c03a cmpne r2,r2,zero + 1014e34: 1000031e bne r2,zero,1014e44 + return (OS_ERR_PDATA_NULL); + 1014e38: 00800244 movi r2,9 + 1014e3c: e0bfff15 stw r2,-4(fp) + 1014e40: 00003506 br 1014f18 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1014e44: 0005303a rdctl r2,status + 1014e48: e0bffa15 stw r2,-24(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1014e4c: e0fffa17 ldw r3,-24(fp) + 1014e50: 00bfff84 movi r2,-2 + 1014e54: 1884703a and r2,r3,r2 + 1014e58: 1001703a wrctl status,r2 + + return context; + 1014e5c: e0bffa17 ldw r2,-24(fp) + } +#endif + OS_ENTER_CRITICAL(); + 1014e60: e0bffb15 stw r2,-20(fp) + if (prio == OS_PRIO_SELF) { /* See if suspend SELF */ + 1014e64: e0bffd03 ldbu r2,-12(fp) + 1014e68: 10803fd8 cmpnei r2,r2,255 + 1014e6c: 1000051e bne r2,zero,1014e84 + prio = OSTCBCur->OSTCBPrio; + 1014e70: 008040b4 movhi r2,258 + 1014e74: 10b31f04 addi r2,r2,-13188 + 1014e78: 10800017 ldw r2,0(r2) + 1014e7c: 10800c83 ldbu r2,50(r2) + 1014e80: e0bffd05 stb r2,-12(fp) + } + ptcb = OSTCBPrioTbl[prio]; + 1014e84: e0bffd03 ldbu r2,-12(fp) + 1014e88: 00c040b4 movhi r3,258 + 1014e8c: 18d9a904 addi r3,r3,26276 + 1014e90: 1085883a add r2,r2,r2 + 1014e94: 1085883a add r2,r2,r2 + 1014e98: 10c5883a add r2,r2,r3 + 1014e9c: 10800017 ldw r2,0(r2) + 1014ea0: e0bffc15 stw r2,-16(fp) + if (ptcb == (OS_TCB *)0) { /* Task to query must exist */ + 1014ea4: e0bffc17 ldw r2,-16(fp) + 1014ea8: 1004c03a cmpne r2,r2,zero + 1014eac: 1000071e bne r2,zero,1014ecc + 1014eb0: e0bffb17 ldw r2,-20(fp) + 1014eb4: e0bff915 stw r2,-28(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1014eb8: e0bff917 ldw r2,-28(fp) + 1014ebc: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_PRIO); + 1014ec0: 00800a44 movi r2,41 + 1014ec4: e0bfff15 stw r2,-4(fp) + 1014ec8: 00001306 br 1014f18 + } + if (ptcb == OS_TCB_RESERVED) { /* Task to query must not be assigned to a Mutex */ + 1014ecc: e0bffc17 ldw r2,-16(fp) + 1014ed0: 10800058 cmpnei r2,r2,1 + 1014ed4: 1000071e bne r2,zero,1014ef4 + 1014ed8: e0bffb17 ldw r2,-20(fp) + 1014edc: e0bff815 stw r2,-32(fp) + 1014ee0: e0bff817 ldw r2,-32(fp) + 1014ee4: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_NOT_EXIST); + 1014ee8: 008010c4 movi r2,67 + 1014eec: e0bfff15 stw r2,-4(fp) + 1014ef0: 00000906 br 1014f18 + } + /* Copy TCB into user storage area */ + OS_MemCopy((INT8U *)p_task_data, (INT8U *)ptcb, sizeof(OS_TCB)); + 1014ef4: e13ffe17 ldw r4,-8(fp) + 1014ef8: e17ffc17 ldw r5,-16(fp) + 1014efc: 01801b04 movi r6,108 + 1014f00: 100ec4c0 call 100ec4c + 1014f04: e0bffb17 ldw r2,-20(fp) + 1014f08: e0bff715 stw r2,-36(fp) + 1014f0c: e0bff717 ldw r2,-36(fp) + 1014f10: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_NONE); + 1014f14: e03fff15 stw zero,-4(fp) + 1014f18: e0bfff17 ldw r2,-4(fp) +} + 1014f1c: e037883a mov sp,fp + 1014f20: dfc00117 ldw ra,4(sp) + 1014f24: df000017 ldw fp,0(sp) + 1014f28: dec00204 addi sp,sp,8 + 1014f2c: f800283a ret + +01014f30 : +* Returns : none +********************************************************************************************************* +*/ +#if (OS_TASK_STAT_STK_CHK_EN > 0) && (OS_TASK_CREATE_EXT_EN > 0) +void OS_TaskStkClr (OS_STK *pbos, INT32U size, INT16U opt) +{ + 1014f30: defffc04 addi sp,sp,-16 + 1014f34: df000315 stw fp,12(sp) + 1014f38: df000304 addi fp,sp,12 + 1014f3c: e13ffd15 stw r4,-12(fp) + 1014f40: e17ffe15 stw r5,-8(fp) + 1014f44: e1bfff0d sth r6,-4(fp) + if ((opt & OS_TASK_OPT_STK_CHK) != 0x0000) { /* See if stack checking has been enabled */ + 1014f48: e0bfff0b ldhu r2,-4(fp) + 1014f4c: 1080004c andi r2,r2,1 + 1014f50: 10803fcc andi r2,r2,255 + 1014f54: 1005003a cmpeq r2,r2,zero + 1014f58: 1000101e bne r2,zero,1014f9c + if ((opt & OS_TASK_OPT_STK_CLR) != 0x0000) { /* See if stack needs to be cleared */ + 1014f5c: e0bfff0b ldhu r2,-4(fp) + 1014f60: 1080008c andi r2,r2,2 + 1014f64: 1005003a cmpeq r2,r2,zero + 1014f68: 10000c1e bne r2,zero,1014f9c +#if OS_STK_GROWTH == 1 + while (size > 0) { /* Stack grows from HIGH to LOW memory */ + 1014f6c: 00000806 br 1014f90 + size--; + 1014f70: e0bffe17 ldw r2,-8(fp) + 1014f74: 10bfffc4 addi r2,r2,-1 + 1014f78: e0bffe15 stw r2,-8(fp) + *pbos++ = (OS_STK)0; /* Clear from bottom of stack and up! */ + 1014f7c: e0bffd17 ldw r2,-12(fp) + 1014f80: 10000015 stw zero,0(r2) + 1014f84: e0bffd17 ldw r2,-12(fp) + 1014f88: 10800104 addi r2,r2,4 + 1014f8c: e0bffd15 stw r2,-12(fp) +void OS_TaskStkClr (OS_STK *pbos, INT32U size, INT16U opt) +{ + if ((opt & OS_TASK_OPT_STK_CHK) != 0x0000) { /* See if stack checking has been enabled */ + if ((opt & OS_TASK_OPT_STK_CLR) != 0x0000) { /* See if stack needs to be cleared */ +#if OS_STK_GROWTH == 1 + while (size > 0) { /* Stack grows from HIGH to LOW memory */ + 1014f90: e0bffe17 ldw r2,-8(fp) + 1014f94: 1004c03a cmpne r2,r2,zero + 1014f98: 103ff51e bne r2,zero,1014f70 + *pbos-- = (OS_STK)0; /* Clear from bottom of stack and down */ + } +#endif + } + } +} + 1014f9c: e037883a mov sp,fp + 1014fa0: df000017 ldw fp,0(sp) + 1014fa4: dec00104 addi sp,sp,4 + 1014fa8: f800283a ret + +01014fac : +* Returns : none +********************************************************************************************************* +*/ + +void OSTimeDly (INT16U ticks) +{ + 1014fac: defff904 addi sp,sp,-28 + 1014fb0: dfc00615 stw ra,24(sp) + 1014fb4: df000515 stw fp,20(sp) + 1014fb8: df000504 addi fp,sp,20 + 1014fbc: e13fff0d sth r4,-4(fp) + INT8U y; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 1014fc0: e03ffd15 stw zero,-12(fp) +#endif + + + + if (OSIntNesting > 0) { /* See if trying to call from an ISR */ + 1014fc4: 008040b4 movhi r2,258 + 1014fc8: 10b31e04 addi r2,r2,-13192 + 1014fcc: 10800003 ldbu r2,0(r2) + 1014fd0: 10803fcc andi r2,r2,255 + 1014fd4: 1004c03a cmpne r2,r2,zero + 1014fd8: 1000421e bne r2,zero,10150e4 + return; + } + if (ticks > 0) { /* 0 means no delay! */ + 1014fdc: e0bfff0b ldhu r2,-4(fp) + 1014fe0: 1005003a cmpeq r2,r2,zero + 1014fe4: 10003f1e bne r2,zero,10150e4 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1014fe8: 0005303a rdctl r2,status + 1014fec: e0bffc15 stw r2,-16(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1014ff0: e0fffc17 ldw r3,-16(fp) + 1014ff4: 00bfff84 movi r2,-2 + 1014ff8: 1884703a and r2,r3,r2 + 1014ffc: 1001703a wrctl status,r2 + + return context; + 1015000: e0bffc17 ldw r2,-16(fp) + OS_ENTER_CRITICAL(); + 1015004: e0bffd15 stw r2,-12(fp) + y = OSTCBCur->OSTCBY; /* Delay current task */ + 1015008: 008040b4 movhi r2,258 + 101500c: 10b31f04 addi r2,r2,-13188 + 1015010: 10800017 ldw r2,0(r2) + 1015014: 10800d03 ldbu r2,52(r2) + 1015018: e0bffe05 stb r2,-8(fp) + OSRdyTbl[y] &= ~OSTCBCur->OSTCBBitX; + 101501c: e13ffe03 ldbu r4,-8(fp) + 1015020: e0fffe03 ldbu r3,-8(fp) + 1015024: 008040b4 movhi r2,258 + 1015028: 10b31c44 addi r2,r2,-13199 + 101502c: 10c5883a add r2,r2,r3 + 1015030: 10800003 ldbu r2,0(r2) + 1015034: 1007883a mov r3,r2 + 1015038: 008040b4 movhi r2,258 + 101503c: 10b31f04 addi r2,r2,-13188 + 1015040: 10800017 ldw r2,0(r2) + 1015044: 10800d43 ldbu r2,53(r2) + 1015048: 0084303a nor r2,zero,r2 + 101504c: 1884703a and r2,r3,r2 + 1015050: 1007883a mov r3,r2 + 1015054: 008040b4 movhi r2,258 + 1015058: 10b31c44 addi r2,r2,-13199 + 101505c: 1105883a add r2,r2,r4 + 1015060: 10c00005 stb r3,0(r2) + if (OSRdyTbl[y] == 0) { + 1015064: e0fffe03 ldbu r3,-8(fp) + 1015068: 008040b4 movhi r2,258 + 101506c: 10b31c44 addi r2,r2,-13199 + 1015070: 10c5883a add r2,r2,r3 + 1015074: 10800003 ldbu r2,0(r2) + 1015078: 10803fcc andi r2,r2,255 + 101507c: 1004c03a cmpne r2,r2,zero + 1015080: 10000e1e bne r2,zero,10150bc + OSRdyGrp &= ~OSTCBCur->OSTCBBitY; + 1015084: 008040b4 movhi r2,258 + 1015088: 10b31f04 addi r2,r2,-13188 + 101508c: 10800017 ldw r2,0(r2) + 1015090: 10800d83 ldbu r2,54(r2) + 1015094: 0084303a nor r2,zero,r2 + 1015098: 1007883a mov r3,r2 + 101509c: 008040b4 movhi r2,258 + 10150a0: 10b31c04 addi r2,r2,-13200 + 10150a4: 10800003 ldbu r2,0(r2) + 10150a8: 1884703a and r2,r3,r2 + 10150ac: 1007883a mov r3,r2 + 10150b0: 008040b4 movhi r2,258 + 10150b4: 10b31c04 addi r2,r2,-13200 + 10150b8: 10c00005 stb r3,0(r2) + } + OSTCBCur->OSTCBDly = ticks; /* Load ticks in TCB */ + 10150bc: 008040b4 movhi r2,258 + 10150c0: 10b31f04 addi r2,r2,-13188 + 10150c4: 10c00017 ldw r3,0(r2) + 10150c8: e0bfff0b ldhu r2,-4(fp) + 10150cc: 18800b8d sth r2,46(r3) + 10150d0: e0bffd17 ldw r2,-12(fp) + 10150d4: e0bffb15 stw r2,-20(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 10150d8: e0bffb17 ldw r2,-20(fp) + 10150dc: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + OS_Sched(); /* Find next task to run! */ + 10150e0: 100ecb80 call 100ecb8 + } +} + 10150e4: e037883a mov sp,fp + 10150e8: dfc00117 ldw ra,4(sp) + 10150ec: df000017 ldw fp,0(sp) + 10150f0: dec00204 addi sp,sp,8 + 10150f4: f800283a ret + +010150f8 : +********************************************************************************************************* +*/ + +#if OS_TIME_DLY_HMSM_EN > 0 +INT8U OSTimeDlyHMSM (INT8U hours, INT8U minutes, INT8U seconds, INT16U ms) +{ + 10150f8: defff604 addi sp,sp,-40 + 10150fc: dfc00915 stw ra,36(sp) + 1015100: df000815 stw fp,32(sp) + 1015104: dc000715 stw r16,28(sp) + 1015108: df000704 addi fp,sp,28 + 101510c: e13ffb05 stb r4,-20(fp) + 1015110: e17ffc05 stb r5,-16(fp) + 1015114: e1bffd05 stb r6,-12(fp) + 1015118: e1fffe0d sth r7,-8(fp) + INT32U ticks; + INT16U loops; + + + if (OSIntNesting > 0) { /* See if trying to call from an ISR */ + 101511c: 008040b4 movhi r2,258 + 1015120: 10b31e04 addi r2,r2,-13192 + 1015124: 10800003 ldbu r2,0(r2) + 1015128: 10803fcc andi r2,r2,255 + 101512c: 1005003a cmpeq r2,r2,zero + 1015130: 1000031e bne r2,zero,1015140 + return (OS_ERR_TIME_DLY_ISR); + 1015134: 00801544 movi r2,85 + 1015138: e0bfff15 stw r2,-4(fp) + 101513c: 00004406 br 1015250 + } +#if OS_ARG_CHK_EN > 0 + if (hours == 0) { + 1015140: e0bffb03 ldbu r2,-20(fp) + 1015144: 1004c03a cmpne r2,r2,zero + 1015148: 10000c1e bne r2,zero,101517c + if (minutes == 0) { + 101514c: e0bffc03 ldbu r2,-16(fp) + 1015150: 1004c03a cmpne r2,r2,zero + 1015154: 1000091e bne r2,zero,101517c + if (seconds == 0) { + 1015158: e0bffd03 ldbu r2,-12(fp) + 101515c: 1004c03a cmpne r2,r2,zero + 1015160: 1000061e bne r2,zero,101517c + if (ms == 0) { + 1015164: e0bffe0b ldhu r2,-8(fp) + 1015168: 1004c03a cmpne r2,r2,zero + 101516c: 1000031e bne r2,zero,101517c + return (OS_ERR_TIME_ZERO_DLY); + 1015170: 00801504 movi r2,84 + 1015174: e0bfff15 stw r2,-4(fp) + 1015178: 00003506 br 1015250 + } + } + } + } + if (minutes > 59) { + 101517c: e0bffc03 ldbu r2,-16(fp) + 1015180: 10800f30 cmpltui r2,r2,60 + 1015184: 1000031e bne r2,zero,1015194 + return (OS_ERR_TIME_INVALID_MINUTES); /* Validate arguments to be within range */ + 1015188: 00801444 movi r2,81 + 101518c: e0bfff15 stw r2,-4(fp) + 1015190: 00002f06 br 1015250 + } + if (seconds > 59) { + 1015194: e0bffd03 ldbu r2,-12(fp) + 1015198: 10800f30 cmpltui r2,r2,60 + 101519c: 1000031e bne r2,zero,10151ac + return (OS_ERR_TIME_INVALID_SECONDS); + 10151a0: 00801484 movi r2,82 + 10151a4: e0bfff15 stw r2,-4(fp) + 10151a8: 00002906 br 1015250 + } + if (ms > 999) { + 10151ac: e0bffe0b ldhu r2,-8(fp) + 10151b0: 1080fa30 cmpltui r2,r2,1000 + 10151b4: 1000031e bne r2,zero,10151c4 + return (OS_ERR_TIME_INVALID_MS); + 10151b8: 008014c4 movi r2,83 + 10151bc: e0bfff15 stw r2,-4(fp) + 10151c0: 00002306 br 1015250 + } +#endif + /* Compute the total number of clock ticks required.. */ + /* .. (rounded to the nearest tick) */ + ticks = ((INT32U)hours * 3600L + (INT32U)minutes * 60L + (INT32U)seconds) * OS_TICKS_PER_SEC + 10151c4: e0bffb03 ldbu r2,-20(fp) + 10151c8: 10c38424 muli r3,r2,3600 + 10151cc: e0bffc03 ldbu r2,-16(fp) + 10151d0: 10800f24 muli r2,r2,60 + 10151d4: 1887883a add r3,r3,r2 + 10151d8: e0bffd03 ldbu r2,-12(fp) + 10151dc: 1885883a add r2,r3,r2 + 10151e0: 1400fa24 muli r16,r2,1000 + 10151e4: e0bffe0b ldhu r2,-8(fp) + 10151e8: 1100fa24 muli r4,r2,1000 + 10151ec: 0140fa04 movi r5,1000 + 10151f0: 100bc340 call 100bc34 <__udivsi3> + 10151f4: 8085883a add r2,r16,r2 + 10151f8: e0bffa15 stw r2,-24(fp) + + OS_TICKS_PER_SEC * ((INT32U)ms + 500L / OS_TICKS_PER_SEC) / 1000L; + loops = (INT16U)(ticks >> 16); /* Compute the integral number of 65536 tick delays */ + 10151fc: e0bffa17 ldw r2,-24(fp) + 1015200: 1004d43a srli r2,r2,16 + 1015204: e0bff90d sth r2,-28(fp) + ticks = ticks & 0xFFFFL; /* Obtain the fractional number of ticks */ + 1015208: e0bffa17 ldw r2,-24(fp) + 101520c: 10bfffcc andi r2,r2,65535 + 1015210: e0bffa15 stw r2,-24(fp) + OSTimeDly((INT16U)ticks); + 1015214: e0bffa17 ldw r2,-24(fp) + 1015218: 113fffcc andi r4,r2,65535 + 101521c: 1014fac0 call 1014fac + while (loops > 0) { + 1015220: 00000706 br 1015240 + OSTimeDly((INT16U)32768u); + 1015224: 01200014 movui r4,32768 + 1015228: 1014fac0 call 1014fac + OSTimeDly((INT16U)32768u); + 101522c: 01200014 movui r4,32768 + 1015230: 1014fac0 call 1014fac + loops--; + 1015234: e0bff90b ldhu r2,-28(fp) + 1015238: 10bfffc4 addi r2,r2,-1 + 101523c: e0bff90d sth r2,-28(fp) + ticks = ((INT32U)hours * 3600L + (INT32U)minutes * 60L + (INT32U)seconds) * OS_TICKS_PER_SEC + + OS_TICKS_PER_SEC * ((INT32U)ms + 500L / OS_TICKS_PER_SEC) / 1000L; + loops = (INT16U)(ticks >> 16); /* Compute the integral number of 65536 tick delays */ + ticks = ticks & 0xFFFFL; /* Obtain the fractional number of ticks */ + OSTimeDly((INT16U)ticks); + while (loops > 0) { + 1015240: e0bff90b ldhu r2,-28(fp) + 1015244: 1004c03a cmpne r2,r2,zero + 1015248: 103ff61e bne r2,zero,1015224 + OSTimeDly((INT16U)32768u); + OSTimeDly((INT16U)32768u); + loops--; + } + return (OS_ERR_NONE); + 101524c: e03fff15 stw zero,-4(fp) + 1015250: e0bfff17 ldw r2,-4(fp) +} + 1015254: e037883a mov sp,fp + 1015258: dfc00217 ldw ra,8(sp) + 101525c: df000117 ldw fp,4(sp) + 1015260: dc000017 ldw r16,0(sp) + 1015264: dec00304 addi sp,sp,12 + 1015268: f800283a ret + +0101526c : +********************************************************************************************************* +*/ + +#if OS_TIME_DLY_RESUME_EN > 0 +INT8U OSTimeDlyResume (INT8U prio) +{ + 101526c: defff404 addi sp,sp,-48 + 1015270: dfc00b15 stw ra,44(sp) + 1015274: df000a15 stw fp,40(sp) + 1015278: df000a04 addi fp,sp,40 + 101527c: e13ffe05 stb r4,-8(fp) + OS_TCB *ptcb; +#if OS_CRITICAL_METHOD == 3 /* Storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 1015280: e03ffc15 stw zero,-16(fp) +#endif + + + + if (prio >= OS_LOWEST_PRIO) { + 1015284: e0bffe03 ldbu r2,-8(fp) + 1015288: 10800530 cmpltui r2,r2,20 + 101528c: 1000031e bne r2,zero,101529c + return (OS_ERR_PRIO_INVALID); + 1015290: 00800a84 movi r2,42 + 1015294: e0bfff15 stw r2,-4(fp) + 1015298: 00007206 br 1015464 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 101529c: 0005303a rdctl r2,status + 10152a0: e0bffb15 stw r2,-20(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 10152a4: e0fffb17 ldw r3,-20(fp) + 10152a8: 00bfff84 movi r2,-2 + 10152ac: 1884703a and r2,r3,r2 + 10152b0: 1001703a wrctl status,r2 + + return context; + 10152b4: e0bffb17 ldw r2,-20(fp) + } + OS_ENTER_CRITICAL(); + 10152b8: e0bffc15 stw r2,-16(fp) + ptcb = OSTCBPrioTbl[prio]; /* Make sure that task exist */ + 10152bc: e0bffe03 ldbu r2,-8(fp) + 10152c0: 00c040b4 movhi r3,258 + 10152c4: 18d9a904 addi r3,r3,26276 + 10152c8: 1085883a add r2,r2,r2 + 10152cc: 1085883a add r2,r2,r2 + 10152d0: 10c5883a add r2,r2,r3 + 10152d4: 10800017 ldw r2,0(r2) + 10152d8: e0bffd15 stw r2,-12(fp) + if (ptcb == (OS_TCB *)0) { + 10152dc: e0bffd17 ldw r2,-12(fp) + 10152e0: 1004c03a cmpne r2,r2,zero + 10152e4: 1000071e bne r2,zero,1015304 + 10152e8: e0bffc17 ldw r2,-16(fp) + 10152ec: e0bffa15 stw r2,-24(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 10152f0: e0bffa17 ldw r2,-24(fp) + 10152f4: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_NOT_EXIST); /* The task does not exist */ + 10152f8: 008010c4 movi r2,67 + 10152fc: e0bfff15 stw r2,-4(fp) + 1015300: 00005806 br 1015464 + } + if (ptcb == OS_TCB_RESERVED) { + 1015304: e0bffd17 ldw r2,-12(fp) + 1015308: 10800058 cmpnei r2,r2,1 + 101530c: 1000071e bne r2,zero,101532c + 1015310: e0bffc17 ldw r2,-16(fp) + 1015314: e0bff915 stw r2,-28(fp) + 1015318: e0bff917 ldw r2,-28(fp) + 101531c: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_NOT_EXIST); /* The task does not exist */ + 1015320: 008010c4 movi r2,67 + 1015324: e0bfff15 stw r2,-4(fp) + 1015328: 00004e06 br 1015464 + } + if (ptcb->OSTCBDly == 0) { /* See if task is delayed */ + 101532c: e0bffd17 ldw r2,-12(fp) + 1015330: 10800b8b ldhu r2,46(r2) + 1015334: 10bfffcc andi r2,r2,65535 + 1015338: 1004c03a cmpne r2,r2,zero + 101533c: 1000071e bne r2,zero,101535c + 1015340: e0bffc17 ldw r2,-16(fp) + 1015344: e0bff815 stw r2,-32(fp) + 1015348: e0bff817 ldw r2,-32(fp) + 101534c: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (OS_ERR_TIME_NOT_DLY); /* Indicate that task was not delayed */ + 1015350: 00801404 movi r2,80 + 1015354: e0bfff15 stw r2,-4(fp) + 1015358: 00004206 br 1015464 + } + + ptcb->OSTCBDly = 0; /* Clear the time delay */ + 101535c: e0bffd17 ldw r2,-12(fp) + 1015360: 10000b8d sth zero,46(r2) + if ((ptcb->OSTCBStat & OS_STAT_PEND_ANY) != OS_STAT_RDY) { + 1015364: e0bffd17 ldw r2,-12(fp) + 1015368: 10800c03 ldbu r2,48(r2) + 101536c: 10803fcc andi r2,r2,255 + 1015370: 10800dcc andi r2,r2,55 + 1015374: 1005003a cmpeq r2,r2,zero + 1015378: 10000b1e bne r2,zero,10153a8 + ptcb->OSTCBStat &= ~OS_STAT_PEND_ANY; /* Yes, Clear status flag */ + 101537c: e0bffd17 ldw r2,-12(fp) + 1015380: 10c00c03 ldbu r3,48(r2) + 1015384: 00bff204 movi r2,-56 + 1015388: 1884703a and r2,r3,r2 + 101538c: 1007883a mov r3,r2 + 1015390: e0bffd17 ldw r2,-12(fp) + 1015394: 10c00c05 stb r3,48(r2) + ptcb->OSTCBStatPend = OS_STAT_PEND_TO; /* Indicate PEND timeout */ + 1015398: e0fffd17 ldw r3,-12(fp) + 101539c: 00800044 movi r2,1 + 10153a0: 18800c45 stb r2,49(r3) + 10153a4: 00000206 br 10153b0 + } else { + ptcb->OSTCBStatPend = OS_STAT_PEND_OK; + 10153a8: e0bffd17 ldw r2,-12(fp) + 10153ac: 10000c45 stb zero,49(r2) + } + if ((ptcb->OSTCBStat & OS_STAT_SUSPEND) == OS_STAT_RDY) { /* Is task suspended? */ + 10153b0: e0bffd17 ldw r2,-12(fp) + 10153b4: 10800c03 ldbu r2,48(r2) + 10153b8: 10803fcc andi r2,r2,255 + 10153bc: 1080020c andi r2,r2,8 + 10153c0: 1004c03a cmpne r2,r2,zero + 10153c4: 1000221e bne r2,zero,1015450 + OSRdyGrp |= ptcb->OSTCBBitY; /* No, Make ready */ + 10153c8: e0bffd17 ldw r2,-12(fp) + 10153cc: 10c00d83 ldbu r3,54(r2) + 10153d0: 008040b4 movhi r2,258 + 10153d4: 10b31c04 addi r2,r2,-13200 + 10153d8: 10800003 ldbu r2,0(r2) + 10153dc: 1884b03a or r2,r3,r2 + 10153e0: 1007883a mov r3,r2 + 10153e4: 008040b4 movhi r2,258 + 10153e8: 10b31c04 addi r2,r2,-13200 + 10153ec: 10c00005 stb r3,0(r2) + OSRdyTbl[ptcb->OSTCBY] |= ptcb->OSTCBBitX; + 10153f0: e0bffd17 ldw r2,-12(fp) + 10153f4: 10800d03 ldbu r2,52(r2) + 10153f8: 11003fcc andi r4,r2,255 + 10153fc: e0bffd17 ldw r2,-12(fp) + 1015400: 10800d03 ldbu r2,52(r2) + 1015404: 10c03fcc andi r3,r2,255 + 1015408: 008040b4 movhi r2,258 + 101540c: 10b31c44 addi r2,r2,-13199 + 1015410: 10c5883a add r2,r2,r3 + 1015414: 10c00003 ldbu r3,0(r2) + 1015418: e0bffd17 ldw r2,-12(fp) + 101541c: 10800d43 ldbu r2,53(r2) + 1015420: 1884b03a or r2,r3,r2 + 1015424: 1007883a mov r3,r2 + 1015428: 008040b4 movhi r2,258 + 101542c: 10b31c44 addi r2,r2,-13199 + 1015430: 1105883a add r2,r2,r4 + 1015434: 10c00005 stb r3,0(r2) + 1015438: e0bffc17 ldw r2,-16(fp) + 101543c: e0bff715 stw r2,-36(fp) + 1015440: e0bff717 ldw r2,-36(fp) + 1015444: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + OS_Sched(); /* See if this is new highest priority */ + 1015448: 100ecb80 call 100ecb8 + 101544c: 00000406 br 1015460 + 1015450: e0bffc17 ldw r2,-16(fp) + 1015454: e0bff615 stw r2,-40(fp) + 1015458: e0bff617 ldw r2,-40(fp) + 101545c: 1001703a wrctl status,r2 + } else { + OS_EXIT_CRITICAL(); /* Task may be suspended */ + } + return (OS_ERR_NONE); + 1015460: e03fff15 stw zero,-4(fp) + 1015464: e0bfff17 ldw r2,-4(fp) +} + 1015468: e037883a mov sp,fp + 101546c: dfc00117 ldw ra,4(sp) + 1015470: df000017 ldw fp,0(sp) + 1015474: dec00204 addi sp,sp,8 + 1015478: f800283a ret + +0101547c : +********************************************************************************************************* +*/ + +#if OS_TIME_GET_SET_EN > 0 +INT32U OSTimeGet (void) +{ + 101547c: defffb04 addi sp,sp,-20 + 1015480: df000415 stw fp,16(sp) + 1015484: df000404 addi fp,sp,16 + INT32U ticks; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 1015488: e03ffe15 stw zero,-8(fp) +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 101548c: 0005303a rdctl r2,status + 1015490: e0bffd15 stw r2,-12(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1015494: e0fffd17 ldw r3,-12(fp) + 1015498: 00bfff84 movi r2,-2 + 101549c: 1884703a and r2,r3,r2 + 10154a0: 1001703a wrctl status,r2 + + return context; + 10154a4: e0bffd17 ldw r2,-12(fp) +#endif + + + + OS_ENTER_CRITICAL(); + 10154a8: e0bffe15 stw r2,-8(fp) + ticks = OSTime; + 10154ac: 008040b4 movhi r2,258 + 10154b0: 10b32004 addi r2,r2,-13184 + 10154b4: 10800017 ldw r2,0(r2) + 10154b8: e0bfff15 stw r2,-4(fp) + 10154bc: e0bffe17 ldw r2,-8(fp) + 10154c0: e0bffc15 stw r2,-16(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 10154c4: e0bffc17 ldw r2,-16(fp) + 10154c8: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); + return (ticks); + 10154cc: e0bfff17 ldw r2,-4(fp) +} + 10154d0: e037883a mov sp,fp + 10154d4: df000017 ldw fp,0(sp) + 10154d8: dec00104 addi sp,sp,4 + 10154dc: f800283a ret + +010154e0 : +********************************************************************************************************* +*/ + +#if OS_TIME_GET_SET_EN > 0 +void OSTimeSet (INT32U ticks) +{ + 10154e0: defffb04 addi sp,sp,-20 + 10154e4: df000415 stw fp,16(sp) + 10154e8: df000404 addi fp,sp,16 + 10154ec: e13fff15 stw r4,-4(fp) +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; + 10154f0: e03ffe15 stw zero,-8(fp) +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 10154f4: 0005303a rdctl r2,status + 10154f8: e0bffd15 stw r2,-12(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 10154fc: e0fffd17 ldw r3,-12(fp) + 1015500: 00bfff84 movi r2,-2 + 1015504: 1884703a and r2,r3,r2 + 1015508: 1001703a wrctl status,r2 + + return context; + 101550c: e0bffd17 ldw r2,-12(fp) +#endif + + + + OS_ENTER_CRITICAL(); + 1015510: e0bffe15 stw r2,-8(fp) + OSTime = ticks; + 1015514: 00c040b4 movhi r3,258 + 1015518: 18f32004 addi r3,r3,-13184 + 101551c: e0bfff17 ldw r2,-4(fp) + 1015520: 18800015 stw r2,0(r3) + 1015524: e0bffe17 ldw r2,-8(fp) + 1015528: e0bffc15 stw r2,-16(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 101552c: e0bffc17 ldw r2,-16(fp) + 1015530: 1001703a wrctl status,r2 + OS_EXIT_CRITICAL(); +} + 1015534: e037883a mov sp,fp + 1015538: df000017 ldw fp,0(sp) + 101553c: dec00104 addi sp,sp,4 + 1015540: f800283a ret + +01015544 : + * The "base" parameter is ignored and only + * present for backwards-compatibility. + */ + +void alt_irq_init ( const void* base ) +{ + 1015544: defffd04 addi sp,sp,-12 + 1015548: dfc00215 stw ra,8(sp) + 101554c: df000115 stw fp,4(sp) + 1015550: df000104 addi fp,sp,4 + 1015554: e13fff15 stw r4,-4(fp) + ALTERA_NIOS2_QSYS_IRQ_INIT ( CPU, cpu); + 1015558: 101800c0 call 101800c + * alt_irq_cpu_enable_interrupts() enables the CPU to start taking interrupts. + */ +static ALT_INLINE void ALT_ALWAYS_INLINE + alt_irq_cpu_enable_interrupts () +{ + NIOS2_WRITE_STATUS(NIOS2_STATUS_PIE_MSK + 101555c: 00800044 movi r2,1 + 1015560: 1001703a wrctl status,r2 + alt_irq_cpu_enable_interrupts(); +} + 1015564: e037883a mov sp,fp + 1015568: dfc00117 ldw ra,4(sp) + 101556c: df000017 ldw fp,0(sp) + 1015570: dec00204 addi sp,sp,8 + 1015574: f800283a ret + +01015578 : + * Initialize the non-interrupt controller devices. + * Called after alt_irq_init(). + */ + +void alt_sys_init( void ) +{ + 1015578: defffe04 addi sp,sp,-8 + 101557c: dfc00115 stw ra,4(sp) + 1015580: df000015 stw fp,0(sp) + 1015584: d839883a mov fp,sp + ALTERA_AVALON_TIMER_INIT ( SYS_CLK_TIMER, sys_clk_timer); + 1015588: 01008034 movhi r4,512 + 101558c: 21041804 addi r4,r4,4192 + 1015590: 000b883a mov r5,zero + 1015594: 000d883a mov r6,zero + 1015598: 01c0fa04 movi r7,1000 + 101559c: 10164240 call 1016424 + ALTERA_AVALON_JTAG_UART_INIT ( JTAG_UART_0, jtag_uart_0); + 10155a0: 010040b4 movhi r4,258 + 10155a4: 21270904 addi r4,r4,-25564 + 10155a8: 000b883a mov r5,zero + 10155ac: 01800384 movi r6,14 + 10155b0: 10157a00 call 10157a0 + 10155b4: 010040b4 movhi r4,258 + 10155b8: 2126ff04 addi r4,r4,-25604 + 10155bc: 10156200 call 1015620 + ALTERA_AVALON_SYSID_QSYS_INIT ( SYSID, sysid); + ALTERA_AVALON_UART_INIT ( UART_MC, uart_mc); + 10155c0: 010040b4 movhi r4,258 + 10155c4: 212b2404 addi r4,r4,-21360 + 10155c8: 000b883a mov r5,zero + 10155cc: 01800144 movi r6,5 + 10155d0: 10165a40 call 10165a4 + 10155d4: 010040b4 movhi r4,258 + 10155d8: 212b1a04 addi r4,r4,-21400 + 10155dc: 10156200 call 1015620 + ALTERA_AVALON_UART_INIT ( UART_WIFI, uart_wifi); + 10155e0: 010040b4 movhi r4,258 + 10155e4: 212b5804 addi r4,r4,-21152 + 10155e8: 000b883a mov r5,zero + 10155ec: 01800104 movi r6,4 + 10155f0: 10165a40 call 10165a4 + 10155f4: 010040b4 movhi r4,258 + 10155f8: 212b4e04 addi r4,r4,-21192 + 10155fc: 10156200 call 1015620 + ALTERA_UP_AVALON_RS232_INIT ( RS232_WIFI, rs232_wifi); + 1015600: 010040b4 movhi r4,258 + 1015604: 212b8204 addi r4,r4,-20984 + 1015608: 10156200 call 1015620 +} + 101560c: e037883a mov sp,fp + 1015610: dfc00117 ldw ra,4(sp) + 1015614: df000017 ldw fp,0(sp) + 1015618: dec00204 addi sp,sp,8 + 101561c: f800283a ret + +01015620 : + */ + +extern int alt_fs_reg (alt_dev* dev); + +static ALT_INLINE int alt_dev_reg (alt_dev* dev) +{ + 1015620: defffd04 addi sp,sp,-12 + 1015624: dfc00215 stw ra,8(sp) + 1015628: df000115 stw fp,4(sp) + 101562c: df000104 addi fp,sp,4 + 1015630: e13fff15 stw r4,-4(fp) + extern alt_llist alt_dev_list; + + return alt_dev_llist_insert ((alt_dev_llist*) dev, &alt_dev_list); + 1015634: e13fff17 ldw r4,-4(fp) + 1015638: 014040b4 movhi r5,258 + 101563c: 296b9e04 addi r5,r5,-20872 + 1015640: 10176040 call 1017604 +} + 1015644: e037883a mov sp,fp + 1015648: dfc00117 ldw ra,4(sp) + 101564c: df000017 ldw fp,0(sp) + 1015650: dec00204 addi sp,sp,8 + 1015654: f800283a ret + +01015658 : + * + */ + +int +altera_avalon_jtag_uart_read_fd(alt_fd* fd, char* buffer, int space) +{ + 1015658: defffa04 addi sp,sp,-24 + 101565c: dfc00515 stw ra,20(sp) + 1015660: df000415 stw fp,16(sp) + 1015664: df000404 addi fp,sp,16 + 1015668: e13ffd15 stw r4,-12(fp) + 101566c: e17ffe15 stw r5,-8(fp) + 1015670: e1bfff15 stw r6,-4(fp) + altera_avalon_jtag_uart_dev* dev = (altera_avalon_jtag_uart_dev*) fd->dev; + 1015674: e0bffd17 ldw r2,-12(fp) + 1015678: 10800017 ldw r2,0(r2) + 101567c: e0bffc15 stw r2,-16(fp) + + return altera_avalon_jtag_uart_read(&dev->state, buffer, space, + 1015680: e0bffc17 ldw r2,-16(fp) + 1015684: 11000a04 addi r4,r2,40 + 1015688: e0bffd17 ldw r2,-12(fp) + 101568c: 11c00217 ldw r7,8(r2) + 1015690: e17ffe17 ldw r5,-8(fp) + 1015694: e1bfff17 ldw r6,-4(fp) + 1015698: 1015e140 call 1015e14 + fd->fd_flags); +} + 101569c: e037883a mov sp,fp + 10156a0: dfc00117 ldw ra,4(sp) + 10156a4: df000017 ldw fp,0(sp) + 10156a8: dec00204 addi sp,sp,8 + 10156ac: f800283a ret + +010156b0 : + +int +altera_avalon_jtag_uart_write_fd(alt_fd* fd, const char* buffer, int space) +{ + 10156b0: defffa04 addi sp,sp,-24 + 10156b4: dfc00515 stw ra,20(sp) + 10156b8: df000415 stw fp,16(sp) + 10156bc: df000404 addi fp,sp,16 + 10156c0: e13ffd15 stw r4,-12(fp) + 10156c4: e17ffe15 stw r5,-8(fp) + 10156c8: e1bfff15 stw r6,-4(fp) + altera_avalon_jtag_uart_dev* dev = (altera_avalon_jtag_uart_dev*) fd->dev; + 10156cc: e0bffd17 ldw r2,-12(fp) + 10156d0: 10800017 ldw r2,0(r2) + 10156d4: e0bffc15 stw r2,-16(fp) + + return altera_avalon_jtag_uart_write(&dev->state, buffer, space, + 10156d8: e0bffc17 ldw r2,-16(fp) + 10156dc: 11000a04 addi r4,r2,40 + 10156e0: e0bffd17 ldw r2,-12(fp) + 10156e4: 11c00217 ldw r7,8(r2) + 10156e8: e17ffe17 ldw r5,-8(fp) + 10156ec: e1bfff17 ldw r6,-4(fp) + 10156f0: 10160d40 call 10160d4 + fd->fd_flags); +} + 10156f4: e037883a mov sp,fp + 10156f8: dfc00117 ldw ra,4(sp) + 10156fc: df000017 ldw fp,0(sp) + 1015700: dec00204 addi sp,sp,8 + 1015704: f800283a ret + +01015708 : + +#ifndef ALTERA_AVALON_JTAG_UART_SMALL + +int +altera_avalon_jtag_uart_close_fd(alt_fd* fd) +{ + 1015708: defffc04 addi sp,sp,-16 + 101570c: dfc00315 stw ra,12(sp) + 1015710: df000215 stw fp,8(sp) + 1015714: df000204 addi fp,sp,8 + 1015718: e13fff15 stw r4,-4(fp) + altera_avalon_jtag_uart_dev* dev = (altera_avalon_jtag_uart_dev*) fd->dev; + 101571c: e0bfff17 ldw r2,-4(fp) + 1015720: 10800017 ldw r2,0(r2) + 1015724: e0bffe15 stw r2,-8(fp) + + return altera_avalon_jtag_uart_close(&dev->state, fd->fd_flags); + 1015728: e0bffe17 ldw r2,-8(fp) + 101572c: 11000a04 addi r4,r2,40 + 1015730: e0bfff17 ldw r2,-4(fp) + 1015734: 11400217 ldw r5,8(r2) + 1015738: 1015cac0 call 1015cac +} + 101573c: e037883a mov sp,fp + 1015740: dfc00117 ldw ra,4(sp) + 1015744: df000017 ldw fp,0(sp) + 1015748: dec00204 addi sp,sp,8 + 101574c: f800283a ret + +01015750 : + +int +altera_avalon_jtag_uart_ioctl_fd(alt_fd* fd, int req, void* arg) +{ + 1015750: defffa04 addi sp,sp,-24 + 1015754: dfc00515 stw ra,20(sp) + 1015758: df000415 stw fp,16(sp) + 101575c: df000404 addi fp,sp,16 + 1015760: e13ffd15 stw r4,-12(fp) + 1015764: e17ffe15 stw r5,-8(fp) + 1015768: e1bfff15 stw r6,-4(fp) + altera_avalon_jtag_uart_dev* dev = (altera_avalon_jtag_uart_dev*) fd->dev; + 101576c: e0bffd17 ldw r2,-12(fp) + 1015770: 10800017 ldw r2,0(r2) + 1015774: e0bffc15 stw r2,-16(fp) + + return altera_avalon_jtag_uart_ioctl(&dev->state, req, arg); + 1015778: e0bffc17 ldw r2,-16(fp) + 101577c: 11000a04 addi r4,r2,40 + 1015780: e17ffe17 ldw r5,-8(fp) + 1015784: e1bfff17 ldw r6,-4(fp) + 1015788: 1015d200 call 1015d20 +} + 101578c: e037883a mov sp,fp + 1015790: dfc00117 ldw ra,4(sp) + 1015794: df000017 ldw fp,0(sp) + 1015798: dec00204 addi sp,sp,8 + 101579c: f800283a ret + +010157a0 : + * Return 1 on sucessful IRQ register and 0 on failure. + */ + +void altera_avalon_jtag_uart_init(altera_avalon_jtag_uart_state* sp, + int irq_controller_id, int irq) +{ + 10157a0: defff504 addi sp,sp,-44 + 10157a4: dfc00a15 stw ra,40(sp) + 10157a8: df000915 stw fp,36(sp) + 10157ac: df000904 addi fp,sp,36 + 10157b0: e13ffd15 stw r4,-12(fp) + 10157b4: e17ffe15 stw r5,-8(fp) + 10157b8: e1bfff15 stw r6,-4(fp) + ALT_FLAG_CREATE(&sp->events, 0); + 10157bc: e0bffd17 ldw r2,-12(fp) + 10157c0: 10800c04 addi r2,r2,48 + 10157c4: e0bffb15 stw r2,-20(fp) + 10157c8: e03ffc0d sth zero,-16(fp) + +static ALT_INLINE int ALT_ALWAYS_INLINE alt_flag_create (OS_FLAG_GRP** pgroup, + OS_FLAGS flags) +{ + INT8U err; + *pgroup = OSFlagCreate (flags, &err); + 10157cc: e13ffc0b ldhu r4,-16(fp) + 10157d0: e17ffc84 addi r5,fp,-14 + 10157d4: 100f8600 call 100f860 + 10157d8: 1007883a mov r3,r2 + 10157dc: e0bffb17 ldw r2,-20(fp) + 10157e0: 10c00015 stw r3,0(r2) + ALT_SEM_CREATE(&sp->read_lock, 1); + 10157e4: e0bffd17 ldw r2,-12(fp) + 10157e8: 10800a04 addi r2,r2,40 + 10157ec: e0bff915 stw r2,-28(fp) + 10157f0: 00800044 movi r2,1 + 10157f4: e0bffa0d sth r2,-24(fp) + 10157f8: e13ffa0b ldhu r4,-24(fp) + 10157fc: 1012a640 call 1012a64 + 1015800: 1007883a mov r3,r2 + 1015804: e0bff917 ldw r2,-28(fp) + 1015808: 10c00015 stw r3,0(r2) + ALT_SEM_CREATE(&sp->write_lock, 1); + 101580c: e0bffd17 ldw r2,-12(fp) + 1015810: 10800b04 addi r2,r2,44 + 1015814: e0bff715 stw r2,-36(fp) + 1015818: 00800044 movi r2,1 + 101581c: e0bff80d sth r2,-32(fp) + 1015820: e13ff80b ldhu r4,-32(fp) + 1015824: 1012a640 call 1012a64 + 1015828: 1007883a mov r3,r2 + 101582c: e0bff717 ldw r2,-36(fp) + 1015830: 10c00015 stw r3,0(r2) + + /* enable read interrupts at the device */ + sp->irq_enable = ALTERA_AVALON_JTAG_UART_CONTROL_RE_MSK; + 1015834: e0fffd17 ldw r3,-12(fp) + 1015838: 00800044 movi r2,1 + 101583c: 18800815 stw r2,32(r3) + + IOWR_ALTERA_AVALON_JTAG_UART_CONTROL(sp->base, sp->irq_enable); + 1015840: e0bffd17 ldw r2,-12(fp) + 1015844: 10800017 ldw r2,0(r2) + 1015848: 11000104 addi r4,r2,4 + 101584c: e0bffd17 ldw r2,-12(fp) + 1015850: 10800817 ldw r2,32(r2) + 1015854: 1007883a mov r3,r2 + 1015858: 2005883a mov r2,r4 + 101585c: 10c00035 stwio r3,0(r2) + /* register the interrupt handler */ +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT + alt_ic_isr_register(irq_controller_id, irq, altera_avalon_jtag_uart_irq, + sp, NULL); +#else + alt_irq_register(irq, sp, altera_avalon_jtag_uart_irq); + 1015860: e13fff17 ldw r4,-4(fp) + 1015864: e17ffd17 ldw r5,-12(fp) + 1015868: 01804074 movhi r6,257 + 101586c: 31963404 addi r6,r6,22736 + 1015870: 10179e00 call 10179e0 +#endif + + /* Register an alarm to go off every second to check for presence of host */ + sp->host_inactive = 0; + 1015874: e0bffd17 ldw r2,-12(fp) + 1015878: 10000915 stw zero,36(r2) + + if (alt_alarm_start(&sp->alarm, alt_ticks_per_second(), + 101587c: e0bffd17 ldw r2,-12(fp) + 1015880: 11000204 addi r4,r2,8 + * Obtain the system clock rate in ticks/s. + */ + +static ALT_INLINE alt_u32 ALT_ALWAYS_INLINE alt_ticks_per_second (void) +{ + return _alt_tick_rate; + 1015884: 008040b4 movhi r2,258 + 1015888: 10b32504 addi r2,r2,-13164 + 101588c: 10800017 ldw r2,0(r2) + 1015890: 100b883a mov r5,r2 + 1015894: 01804074 movhi r6,257 + 1015898: 3196e604 addi r6,r6,23448 + 101589c: e1fffd17 ldw r7,-12(fp) + 10158a0: 101746c0 call 101746c + 10158a4: 1004403a cmpge r2,r2,zero + 10158a8: 1000041e bne r2,zero,10158bc + &altera_avalon_jtag_uart_timeout, sp) < 0) + { + /* If we can't set the alarm then record "don't know if host present" + * and behave as though the host is present. + */ + sp->timeout = INT_MAX; + 10158ac: e0fffd17 ldw r3,-12(fp) + 10158b0: 00a00034 movhi r2,32768 + 10158b4: 10bfffc4 addi r2,r2,-1 + 10158b8: 18800115 stw r2,4(r3) + } + + /* ALT_LOG - see altera_hal/HAL/inc/sys/alt_log_printf.h */ + ALT_LOG_JTAG_UART_ALARM_REGISTER(sp, sp->base); +} + 10158bc: e037883a mov sp,fp + 10158c0: dfc00117 ldw ra,4(sp) + 10158c4: df000017 ldw fp,0(sp) + 10158c8: dec00204 addi sp,sp,8 + 10158cc: f800283a ret + +010158d0 : +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT +static void altera_avalon_jtag_uart_irq(void* context) +#else +static void altera_avalon_jtag_uart_irq(void* context, alt_u32 id) +#endif +{ + 10158d0: defff104 addi sp,sp,-60 + 10158d4: dfc00e15 stw ra,56(sp) + 10158d8: df000d15 stw fp,52(sp) + 10158dc: df000d04 addi fp,sp,52 + 10158e0: e13ffe15 stw r4,-8(fp) + 10158e4: e17fff15 stw r5,-4(fp) + altera_avalon_jtag_uart_state* sp = (altera_avalon_jtag_uart_state*) context; + 10158e8: e0bffe17 ldw r2,-8(fp) + 10158ec: e0bffc15 stw r2,-16(fp) + unsigned int base = sp->base; + 10158f0: e0bffc17 ldw r2,-16(fp) + 10158f4: 10800017 ldw r2,0(r2) + 10158f8: e0bffb15 stw r2,-20(fp) + 10158fc: 00000006 br 1015900 + /* ALT_LOG - see altera_hal/HAL/inc/sys/alt_log_printf.h */ + ALT_LOG_JTAG_UART_ISR_FUNCTION(base, sp); + + for ( ; ; ) + { + unsigned int control = IORD_ALTERA_AVALON_JTAG_UART_CONTROL(base); + 1015900: e0bffb17 ldw r2,-20(fp) + 1015904: 10800104 addi r2,r2,4 + 1015908: 10800037 ldwio r2,0(r2) + 101590c: e0bffa15 stw r2,-24(fp) + + /* Return once nothing more to do */ + if ((control & (ALTERA_AVALON_JTAG_UART_CONTROL_RI_MSK | ALTERA_AVALON_JTAG_UART_CONTROL_WI_MSK)) == 0) + 1015910: e0bffa17 ldw r2,-24(fp) + 1015914: 1080c00c andi r2,r2,768 + 1015918: 1005003a cmpeq r2,r2,zero + 101591c: 1000991e bne r2,zero,1015b84 + break; + + if (control & ALTERA_AVALON_JTAG_UART_CONTROL_RI_MSK) + 1015920: e0bffa17 ldw r2,-24(fp) + 1015924: 1080400c andi r2,r2,256 + 1015928: 1005003a cmpeq r2,r2,zero + 101592c: 1000481e bne r2,zero,1015a50 + { + /* process a read irq. Start by assuming that there is data in the + * receive FIFO (otherwise why would we have been interrupted?) + */ + unsigned int data = 1 << ALTERA_AVALON_JTAG_UART_DATA_RAVAIL_OFST; + 1015930: 00800074 movhi r2,1 + 1015934: e0bff915 stw r2,-28(fp) + 1015938: 00000006 br 101593c + for ( ; ; ) + { + /* Check whether there is space in the buffer. If not then we must not + * read any characters from the buffer as they will be lost. + */ + unsigned int next = (sp->rx_in + 1) % ALTERA_AVALON_JTAG_UART_BUF_LEN; + 101593c: e0bffc17 ldw r2,-16(fp) + 1015940: 10800d17 ldw r2,52(r2) + 1015944: 10800044 addi r2,r2,1 + 1015948: 1081ffcc andi r2,r2,2047 + 101594c: e0bff815 stw r2,-32(fp) + if (next == sp->rx_out) + 1015950: e0bffc17 ldw r2,-16(fp) + 1015954: 10c00e17 ldw r3,56(r2) + 1015958: e0bff817 ldw r2,-32(fp) + 101595c: 18802826 beq r3,r2,1015a00 + break; + + /* Try to remove a character from the FIFO and find out whether there + * are any more characters remaining. + */ + data = IORD_ALTERA_AVALON_JTAG_UART_DATA(base); + 1015960: e0bffb17 ldw r2,-20(fp) + 1015964: 10800037 ldwio r2,0(r2) + 1015968: e0bff915 stw r2,-28(fp) + + if ((data & ALTERA_AVALON_JTAG_UART_DATA_RVALID_MSK) == 0) + 101596c: e0bff917 ldw r2,-28(fp) + 1015970: 10a0000c andi r2,r2,32768 + 1015974: 1005003a cmpeq r2,r2,zero + 1015978: 1000211e bne r2,zero,1015a00 + break; + + sp->rx_buf[sp->rx_in] = (data & ALTERA_AVALON_JTAG_UART_DATA_DATA_MSK) >> ALTERA_AVALON_JTAG_UART_DATA_DATA_OFST; + 101597c: e0bffc17 ldw r2,-16(fp) + 1015980: 10c00d17 ldw r3,52(r2) + 1015984: e0bff917 ldw r2,-28(fp) + 1015988: 1009883a mov r4,r2 + 101598c: e0bffc17 ldw r2,-16(fp) + 1015990: 1885883a add r2,r3,r2 + 1015994: 10801104 addi r2,r2,68 + 1015998: 11000005 stb r4,0(r2) + sp->rx_in = (sp->rx_in + 1) % ALTERA_AVALON_JTAG_UART_BUF_LEN; + 101599c: e0bffc17 ldw r2,-16(fp) + 10159a0: 10800d17 ldw r2,52(r2) + 10159a4: 10800044 addi r2,r2,1 + 10159a8: 10c1ffcc andi r3,r2,2047 + 10159ac: e0bffc17 ldw r2,-16(fp) + 10159b0: 10c00d15 stw r3,52(r2) + + /* Post an event to notify jtag_uart_read that a character has been read */ + ALT_FLAG_POST (sp->events, ALT_JTAG_UART_READ_RDY, OS_FLAG_SET); + 10159b4: e0bffc17 ldw r2,-16(fp) + 10159b8: 10800c17 ldw r2,48(r2) + 10159bc: e0bff515 stw r2,-44(fp) + 10159c0: 00800044 movi r2,1 + 10159c4: e0bff60d sth r2,-40(fp) + 10159c8: 00800044 movi r2,1 + 10159cc: e0bff685 stb r2,-38(fp) + OS_FLAGS flags, + INT8U opt) +{ + INT8U err; + + if (OSRunning) + 10159d0: 008040b4 movhi r2,258 + 10159d4: 10b31044 addi r2,r2,-13247 + 10159d8: 10800003 ldbu r2,0(r2) + 10159dc: 10803fcc andi r2,r2,255 + 10159e0: 1005003a cmpeq r2,r2,zero + 10159e4: 103fd51e bne r2,zero,101593c + { + OSFlagPost (group, flags, opt, &err); + 10159e8: e17ff60b ldhu r5,-40(fp) + 10159ec: e1bff683 ldbu r6,-38(fp) + 10159f0: e1fffd04 addi r7,fp,-12 + 10159f4: e13ff517 ldw r4,-44(fp) + 10159f8: 10105880 call 1010588 + return err; + 10159fc: 003fcf06 br 101593c + } + + if (data & ALTERA_AVALON_JTAG_UART_DATA_RAVAIL_MSK) + 1015a00: e0bff917 ldw r2,-28(fp) + 1015a04: 10bfffec andhi r2,r2,65535 + 1015a08: 1005003a cmpeq r2,r2,zero + 1015a0c: 1000101e bne r2,zero,1015a50 + { + /* If there is still data available here then the buffer is full + * so turn off receive interrupts until some space becomes available. + */ + sp->irq_enable &= ~ALTERA_AVALON_JTAG_UART_CONTROL_RE_MSK; + 1015a10: e0bffc17 ldw r2,-16(fp) + 1015a14: 10c00817 ldw r3,32(r2) + 1015a18: 00bfff84 movi r2,-2 + 1015a1c: 1886703a and r3,r3,r2 + 1015a20: e0bffc17 ldw r2,-16(fp) + 1015a24: 10c00815 stw r3,32(r2) + IOWR_ALTERA_AVALON_JTAG_UART_CONTROL(base, sp->irq_enable); + 1015a28: e0bffb17 ldw r2,-20(fp) + 1015a2c: 11000104 addi r4,r2,4 + 1015a30: e0bffc17 ldw r2,-16(fp) + 1015a34: 10800817 ldw r2,32(r2) + 1015a38: 1007883a mov r3,r2 + 1015a3c: 2005883a mov r2,r4 + 1015a40: 10c00035 stwio r3,0(r2) + + /* Dummy read to ensure IRQ is cleared prior to ISR completion */ + IORD_ALTERA_AVALON_JTAG_UART_CONTROL(base); + 1015a44: e0bffb17 ldw r2,-20(fp) + 1015a48: 10800104 addi r2,r2,4 + 1015a4c: 10800037 ldwio r2,0(r2) + } + } + + if (control & ALTERA_AVALON_JTAG_UART_CONTROL_WI_MSK) + 1015a50: e0bffa17 ldw r2,-24(fp) + 1015a54: 1080800c andi r2,r2,512 + 1015a58: 1005003a cmpeq r2,r2,zero + 1015a5c: 103fa81e bne r2,zero,1015900 + { + /* process a write irq */ + unsigned int space = (control & ALTERA_AVALON_JTAG_UART_CONTROL_WSPACE_MSK) >> ALTERA_AVALON_JTAG_UART_CONTROL_WSPACE_OFST; + 1015a60: e0bffa17 ldw r2,-24(fp) + 1015a64: 10bfffec andhi r2,r2,65535 + 1015a68: 1004d43a srli r2,r2,16 + 1015a6c: e0bff715 stw r2,-36(fp) + + while (space > 0 && sp->tx_out != sp->tx_in) + 1015a70: 00002706 br 1015b10 + { + IOWR_ALTERA_AVALON_JTAG_UART_DATA(base, sp->tx_buf[sp->tx_out]); + 1015a74: e13ffb17 ldw r4,-20(fp) + 1015a78: e0bffc17 ldw r2,-16(fp) + 1015a7c: 10c01017 ldw r3,64(r2) + 1015a80: e0bffc17 ldw r2,-16(fp) + 1015a84: 1885883a add r2,r3,r2 + 1015a88: 10821104 addi r2,r2,2116 + 1015a8c: 10800003 ldbu r2,0(r2) + 1015a90: 10c03fcc andi r3,r2,255 + 1015a94: 18c0201c xori r3,r3,128 + 1015a98: 18ffe004 addi r3,r3,-128 + 1015a9c: 2005883a mov r2,r4 + 1015aa0: 10c00035 stwio r3,0(r2) + + sp->tx_out = (sp->tx_out + 1) % ALTERA_AVALON_JTAG_UART_BUF_LEN; + 1015aa4: e0bffc17 ldw r2,-16(fp) + 1015aa8: 10801017 ldw r2,64(r2) + 1015aac: 10800044 addi r2,r2,1 + 1015ab0: 10c1ffcc andi r3,r2,2047 + 1015ab4: e0bffc17 ldw r2,-16(fp) + 1015ab8: 10c01015 stw r3,64(r2) + + /* Post an event to notify jtag_uart_write that a character has been written */ + ALT_FLAG_POST (sp->events, ALT_JTAG_UART_WRITE_RDY, OS_FLAG_SET); + 1015abc: e0bffc17 ldw r2,-16(fp) + 1015ac0: 10800c17 ldw r2,48(r2) + 1015ac4: e0bff315 stw r2,-52(fp) + 1015ac8: 00800084 movi r2,2 + 1015acc: e0bff40d sth r2,-48(fp) + 1015ad0: 00800044 movi r2,1 + 1015ad4: e0bff485 stb r2,-46(fp) + OS_FLAGS flags, + INT8U opt) +{ + INT8U err; + + if (OSRunning) + 1015ad8: 008040b4 movhi r2,258 + 1015adc: 10b31044 addi r2,r2,-13247 + 1015ae0: 10800003 ldbu r2,0(r2) + 1015ae4: 10803fcc andi r2,r2,255 + 1015ae8: 1005003a cmpeq r2,r2,zero + 1015aec: 1000051e bne r2,zero,1015b04 + { + OSFlagPost (group, flags, opt, &err); + 1015af0: e17ff40b ldhu r5,-48(fp) + 1015af4: e1bff483 ldbu r6,-46(fp) + 1015af8: e1fffd44 addi r7,fp,-11 + 1015afc: e13ff317 ldw r4,-52(fp) + 1015b00: 10105880 call 1010588 + + space--; + 1015b04: e0bff717 ldw r2,-36(fp) + 1015b08: 10bfffc4 addi r2,r2,-1 + 1015b0c: e0bff715 stw r2,-36(fp) + if (control & ALTERA_AVALON_JTAG_UART_CONTROL_WI_MSK) + { + /* process a write irq */ + unsigned int space = (control & ALTERA_AVALON_JTAG_UART_CONTROL_WSPACE_MSK) >> ALTERA_AVALON_JTAG_UART_CONTROL_WSPACE_OFST; + + while (space > 0 && sp->tx_out != sp->tx_in) + 1015b10: e0bff717 ldw r2,-36(fp) + 1015b14: 1005003a cmpeq r2,r2,zero + 1015b18: 1000051e bne r2,zero,1015b30 + 1015b1c: e0bffc17 ldw r2,-16(fp) + 1015b20: 10c01017 ldw r3,64(r2) + 1015b24: e0bffc17 ldw r2,-16(fp) + 1015b28: 10800f17 ldw r2,60(r2) + 1015b2c: 18bfd11e bne r3,r2,1015a74 + ALT_FLAG_POST (sp->events, ALT_JTAG_UART_WRITE_RDY, OS_FLAG_SET); + + space--; + } + + if (space > 0) + 1015b30: e0bff717 ldw r2,-36(fp) + 1015b34: 1005003a cmpeq r2,r2,zero + 1015b38: 103f711e bne r2,zero,1015900 + { + /* If we don't have any more data available then turn off the TX interrupt */ + sp->irq_enable &= ~ALTERA_AVALON_JTAG_UART_CONTROL_WE_MSK; + 1015b3c: e0bffc17 ldw r2,-16(fp) + 1015b40: 10c00817 ldw r3,32(r2) + 1015b44: 00bfff44 movi r2,-3 + 1015b48: 1886703a and r3,r3,r2 + 1015b4c: e0bffc17 ldw r2,-16(fp) + 1015b50: 10c00815 stw r3,32(r2) + IOWR_ALTERA_AVALON_JTAG_UART_CONTROL(sp->base, sp->irq_enable); + 1015b54: e0bffc17 ldw r2,-16(fp) + 1015b58: 10800017 ldw r2,0(r2) + 1015b5c: 11000104 addi r4,r2,4 + 1015b60: e0bffc17 ldw r2,-16(fp) + 1015b64: 10800817 ldw r2,32(r2) + 1015b68: 1007883a mov r3,r2 + 1015b6c: 2005883a mov r2,r4 + 1015b70: 10c00035 stwio r3,0(r2) + + /* Dummy read to ensure IRQ is cleared prior to ISR completion */ + IORD_ALTERA_AVALON_JTAG_UART_CONTROL(base); + 1015b74: e0bffb17 ldw r2,-20(fp) + 1015b78: 10800104 addi r2,r2,4 + 1015b7c: 10800037 ldwio r2,0(r2) + } + } + } + 1015b80: 003f5f06 br 1015900 +} + 1015b84: e037883a mov sp,fp + 1015b88: dfc00117 ldw ra,4(sp) + 1015b8c: df000017 ldw fp,0(sp) + 1015b90: dec00204 addi sp,sp,8 + 1015b94: f800283a ret + +01015b98 : + * Timeout routine is called every second + */ + +static alt_u32 +altera_avalon_jtag_uart_timeout(void* context) +{ + 1015b98: defff804 addi sp,sp,-32 + 1015b9c: dfc00715 stw ra,28(sp) + 1015ba0: df000615 stw fp,24(sp) + 1015ba4: df000604 addi fp,sp,24 + 1015ba8: e13fff15 stw r4,-4(fp) + altera_avalon_jtag_uart_state* sp = (altera_avalon_jtag_uart_state *) context; + 1015bac: e0bfff17 ldw r2,-4(fp) + 1015bb0: e0bffd15 stw r2,-12(fp) + + unsigned int control = IORD_ALTERA_AVALON_JTAG_UART_CONTROL(sp->base); + 1015bb4: e0bffd17 ldw r2,-12(fp) + 1015bb8: 10800017 ldw r2,0(r2) + 1015bbc: 10800104 addi r2,r2,4 + 1015bc0: 10800037 ldwio r2,0(r2) + 1015bc4: e0bffc15 stw r2,-16(fp) + + if (control & ALTERA_AVALON_JTAG_UART_CONTROL_AC_MSK) + 1015bc8: e0bffc17 ldw r2,-16(fp) + 1015bcc: 1081000c andi r2,r2,1024 + 1015bd0: 1005003a cmpeq r2,r2,zero + 1015bd4: 10000c1e bne r2,zero,1015c08 + { + IOWR_ALTERA_AVALON_JTAG_UART_CONTROL(sp->base, sp->irq_enable | ALTERA_AVALON_JTAG_UART_CONTROL_AC_MSK); + 1015bd8: e0bffd17 ldw r2,-12(fp) + 1015bdc: 10800017 ldw r2,0(r2) + 1015be0: 11000104 addi r4,r2,4 + 1015be4: e0bffd17 ldw r2,-12(fp) + 1015be8: 10800817 ldw r2,32(r2) + 1015bec: 10810014 ori r2,r2,1024 + 1015bf0: 1007883a mov r3,r2 + 1015bf4: 2005883a mov r2,r4 + 1015bf8: 10c00035 stwio r3,0(r2) + sp->host_inactive = 0; + 1015bfc: e0bffd17 ldw r2,-12(fp) + 1015c00: 10000915 stw zero,36(r2) + 1015c04: 00002106 br 1015c8c + } + else if (sp->host_inactive < INT_MAX - 2) { + 1015c08: e0bffd17 ldw r2,-12(fp) + 1015c0c: 10c00917 ldw r3,36(r2) + 1015c10: 00a00034 movhi r2,32768 + 1015c14: 10bfff04 addi r2,r2,-4 + 1015c18: 10c01c36 bltu r2,r3,1015c8c + sp->host_inactive++; + 1015c1c: e0bffd17 ldw r2,-12(fp) + 1015c20: 10800917 ldw r2,36(r2) + 1015c24: 10c00044 addi r3,r2,1 + 1015c28: e0bffd17 ldw r2,-12(fp) + 1015c2c: 10c00915 stw r3,36(r2) + + if (sp->host_inactive >= sp->timeout) { + 1015c30: e0bffd17 ldw r2,-12(fp) + 1015c34: 10c00917 ldw r3,36(r2) + 1015c38: e0bffd17 ldw r2,-12(fp) + 1015c3c: 10800117 ldw r2,4(r2) + 1015c40: 18801236 bltu r3,r2,1015c8c + /* Post an event to indicate host is inactive (for jtag_uart_read */ + ALT_FLAG_POST (sp->events, ALT_JTAG_UART_TIMEOUT, OS_FLAG_SET); + 1015c44: e0bffd17 ldw r2,-12(fp) + 1015c48: 10800c17 ldw r2,48(r2) + 1015c4c: e0bffa15 stw r2,-24(fp) + 1015c50: 00800104 movi r2,4 + 1015c54: e0bffb0d sth r2,-20(fp) + 1015c58: 00800044 movi r2,1 + 1015c5c: e0bffb85 stb r2,-18(fp) + OS_FLAGS flags, + INT8U opt) +{ + INT8U err; + + if (OSRunning) + 1015c60: 008040b4 movhi r2,258 + 1015c64: 10b31044 addi r2,r2,-13247 + 1015c68: 10800003 ldbu r2,0(r2) + 1015c6c: 10803fcc andi r2,r2,255 + 1015c70: 1005003a cmpeq r2,r2,zero + 1015c74: 1000051e bne r2,zero,1015c8c + { + OSFlagPost (group, flags, opt, &err); + 1015c78: e17ffb0b ldhu r5,-20(fp) + 1015c7c: e1bffb83 ldbu r6,-18(fp) + 1015c80: e1fffe04 addi r7,fp,-8 + 1015c84: e13ffa17 ldw r4,-24(fp) + 1015c88: 10105880 call 1010588 + 1015c8c: 008040b4 movhi r2,258 + 1015c90: 10b32504 addi r2,r2,-13164 + 1015c94: 10800017 ldw r2,0(r2) + } + } + + return alt_ticks_per_second(); +} + 1015c98: e037883a mov sp,fp + 1015c9c: dfc00117 ldw ra,4(sp) + 1015ca0: df000017 ldw fp,0(sp) + 1015ca4: dec00204 addi sp,sp,8 + 1015ca8: f800283a ret + +01015cac : + * The close routine is not implemented for the small driver; instead it will + * map to null. This is because the small driver simply waits while characters + * are transmitted; there is no interrupt-serviced buffer to empty + */ +int altera_avalon_jtag_uart_close(altera_avalon_jtag_uart_state* sp, int flags) +{ + 1015cac: defffc04 addi sp,sp,-16 + 1015cb0: df000315 stw fp,12(sp) + 1015cb4: df000304 addi fp,sp,12 + 1015cb8: e13ffd15 stw r4,-12(fp) + 1015cbc: e17ffe15 stw r5,-8(fp) + /* + * Wait for all transmit data to be emptied by the JTAG UART ISR, or + * for a host-inactivity timeout, in which case transmit data will be lost + */ + while ( (sp->tx_out != sp->tx_in) && (sp->host_inactive < sp->timeout) ) { + 1015cc0: 00000706 br 1015ce0 + if (flags & O_NONBLOCK) { + 1015cc4: e0bffe17 ldw r2,-8(fp) + 1015cc8: 1090000c andi r2,r2,16384 + 1015ccc: 1005003a cmpeq r2,r2,zero + 1015cd0: 1000031e bne r2,zero,1015ce0 + return -EWOULDBLOCK; + 1015cd4: 00bffd44 movi r2,-11 + 1015cd8: e0bfff15 stw r2,-4(fp) + 1015cdc: 00000b06 br 1015d0c +{ + /* + * Wait for all transmit data to be emptied by the JTAG UART ISR, or + * for a host-inactivity timeout, in which case transmit data will be lost + */ + while ( (sp->tx_out != sp->tx_in) && (sp->host_inactive < sp->timeout) ) { + 1015ce0: e0bffd17 ldw r2,-12(fp) + 1015ce4: 10c01017 ldw r3,64(r2) + 1015ce8: e0bffd17 ldw r2,-12(fp) + 1015cec: 10800f17 ldw r2,60(r2) + 1015cf0: 18800526 beq r3,r2,1015d08 + 1015cf4: e0bffd17 ldw r2,-12(fp) + 1015cf8: 10c00917 ldw r3,36(r2) + 1015cfc: e0bffd17 ldw r2,-12(fp) + 1015d00: 10800117 ldw r2,4(r2) + 1015d04: 18bfef36 bltu r3,r2,1015cc4 + if (flags & O_NONBLOCK) { + return -EWOULDBLOCK; + } + } + + return 0; + 1015d08: e03fff15 stw zero,-4(fp) + 1015d0c: e0bfff17 ldw r2,-4(fp) +} + 1015d10: e037883a mov sp,fp + 1015d14: df000017 ldw fp,0(sp) + 1015d18: dec00104 addi sp,sp,4 + 1015d1c: f800283a ret + +01015d20 : +/* ----------------------------------------------------------- */ + +int +altera_avalon_jtag_uart_ioctl(altera_avalon_jtag_uart_state* sp, int req, + void* arg) +{ + 1015d20: defff804 addi sp,sp,-32 + 1015d24: df000715 stw fp,28(sp) + 1015d28: df000704 addi fp,sp,28 + 1015d2c: e13ffb15 stw r4,-20(fp) + 1015d30: e17ffc15 stw r5,-16(fp) + 1015d34: e1bffd15 stw r6,-12(fp) + int rc = -ENOTTY; + 1015d38: 00bff9c4 movi r2,-25 + 1015d3c: e0bffa15 stw r2,-24(fp) + + switch (req) + 1015d40: e0bffc17 ldw r2,-16(fp) + 1015d44: e0bfff15 stw r2,-4(fp) + 1015d48: e0ffff17 ldw r3,-4(fp) + 1015d4c: 189a8060 cmpeqi r2,r3,27137 + 1015d50: 1000041e bne r2,zero,1015d64 + 1015d54: e0ffff17 ldw r3,-4(fp) + 1015d58: 189a80a0 cmpeqi r2,r3,27138 + 1015d5c: 10001b1e bne r2,zero,1015dcc + 1015d60: 00002706 br 1015e00 + { + case TIOCSTIMEOUT: + /* Set the time to wait until assuming host is not connected */ + if (sp->timeout != INT_MAX) + 1015d64: e0bffb17 ldw r2,-20(fp) + 1015d68: 10c00117 ldw r3,4(r2) + 1015d6c: 00a00034 movhi r2,32768 + 1015d70: 10bfffc4 addi r2,r2,-1 + 1015d74: 18802226 beq r3,r2,1015e00 + { + int timeout = *((int *)arg); + 1015d78: e0bffd17 ldw r2,-12(fp) + 1015d7c: 10800017 ldw r2,0(r2) + 1015d80: e0bff915 stw r2,-28(fp) + sp->timeout = (timeout >= 2 && timeout < INT_MAX) ? timeout : INT_MAX - 1; + 1015d84: e0bff917 ldw r2,-28(fp) + 1015d88: 10800090 cmplti r2,r2,2 + 1015d8c: 1000071e bne r2,zero,1015dac + 1015d90: e0fff917 ldw r3,-28(fp) + 1015d94: 00a00034 movhi r2,32768 + 1015d98: 10bfffc4 addi r2,r2,-1 + 1015d9c: 18800326 beq r3,r2,1015dac + 1015da0: e0bff917 ldw r2,-28(fp) + 1015da4: e0bffe15 stw r2,-8(fp) + 1015da8: 00000306 br 1015db8 + 1015dac: 00e00034 movhi r3,32768 + 1015db0: 18ffff84 addi r3,r3,-2 + 1015db4: e0fffe15 stw r3,-8(fp) + 1015db8: e0bffb17 ldw r2,-20(fp) + 1015dbc: e0fffe17 ldw r3,-8(fp) + 1015dc0: 10c00115 stw r3,4(r2) + rc = 0; + 1015dc4: e03ffa15 stw zero,-24(fp) + } + break; + 1015dc8: 00000d06 br 1015e00 + + case TIOCGCONNECTED: + /* Find out whether host is connected */ + if (sp->timeout != INT_MAX) + 1015dcc: e0bffb17 ldw r2,-20(fp) + 1015dd0: 10c00117 ldw r3,4(r2) + 1015dd4: 00a00034 movhi r2,32768 + 1015dd8: 10bfffc4 addi r2,r2,-1 + 1015ddc: 18800826 beq r3,r2,1015e00 + { + *((int *)arg) = (sp->host_inactive < sp->timeout) ? 1 : 0; + 1015de0: e13ffd17 ldw r4,-12(fp) + 1015de4: e0bffb17 ldw r2,-20(fp) + 1015de8: 10c00917 ldw r3,36(r2) + 1015dec: e0bffb17 ldw r2,-20(fp) + 1015df0: 10800117 ldw r2,4(r2) + 1015df4: 1885803a cmpltu r2,r3,r2 + 1015df8: 20800015 stw r2,0(r4) + rc = 0; + 1015dfc: e03ffa15 stw zero,-24(fp) + + default: + break; + } + + return rc; + 1015e00: e0bffa17 ldw r2,-24(fp) +} + 1015e04: e037883a mov sp,fp + 1015e08: df000017 ldw fp,0(sp) + 1015e0c: dec00104 addi sp,sp,4 + 1015e10: f800283a ret + +01015e14 : +/* ----------------------------------------------------------- */ + +int +altera_avalon_jtag_uart_read(altera_avalon_jtag_uart_state* sp, + char * buffer, int space, int flags) +{ + 1015e14: deffeb04 addi sp,sp,-84 + 1015e18: dfc01415 stw ra,80(sp) + 1015e1c: df001315 stw fp,76(sp) + 1015e20: df001304 addi fp,sp,76 + 1015e24: e13ffb15 stw r4,-20(fp) + 1015e28: e17ffc15 stw r5,-16(fp) + 1015e2c: e1bffd15 stw r6,-12(fp) + 1015e30: e1fffe15 stw r7,-8(fp) + char * ptr = buffer; + 1015e34: e0bffc17 ldw r2,-16(fp) + 1015e38: e0bff915 stw r2,-28(fp) + + /* + * When running in a multi threaded environment, obtain the "read_lock" + * semaphore. This ensures that reading from the device is thread-safe. + */ + ALT_SEM_PEND (sp->read_lock, 0); + 1015e3c: e0bffb17 ldw r2,-20(fp) + 1015e40: 10800a17 ldw r2,40(r2) + 1015e44: e0bff315 stw r2,-52(fp) + 1015e48: e03ff40d sth zero,-48(fp) + +static ALT_INLINE int ALT_ALWAYS_INLINE alt_sem_pend (OS_EVENT* sem, + INT16U timeout) +{ + INT8U err; + OSSemPend (sem, timeout, &err); + 1015e4c: e17ff40b ldhu r5,-48(fp) + 1015e50: e1bffa44 addi r6,fp,-23 + 1015e54: e13ff317 ldw r4,-52(fp) + 1015e58: 1012e180 call 1012e18 + + while (space > 0) + 1015e5c: 00006406 br 1015ff0 + unsigned int in, out; + + /* Read as much data as possible */ + do + { + in = sp->rx_in; + 1015e60: e0bffb17 ldw r2,-20(fp) + 1015e64: 10800d17 ldw r2,52(r2) + 1015e68: e0bff615 stw r2,-40(fp) + out = sp->rx_out; + 1015e6c: e0bffb17 ldw r2,-20(fp) + 1015e70: 10800e17 ldw r2,56(r2) + 1015e74: e0bff515 stw r2,-44(fp) + + if (in >= out) + 1015e78: e0fff617 ldw r3,-40(fp) + 1015e7c: e0bff517 ldw r2,-44(fp) + 1015e80: 18800536 bltu r3,r2,1015e98 + n = in - out; + 1015e84: e0bff617 ldw r2,-40(fp) + 1015e88: e0fff517 ldw r3,-44(fp) + 1015e8c: 10c5c83a sub r2,r2,r3 + 1015e90: e0bff715 stw r2,-36(fp) + 1015e94: 00000406 br 1015ea8 + else + n = ALTERA_AVALON_JTAG_UART_BUF_LEN - out; + 1015e98: 00820004 movi r2,2048 + 1015e9c: e0fff517 ldw r3,-44(fp) + 1015ea0: 10c5c83a sub r2,r2,r3 + 1015ea4: e0bff715 stw r2,-36(fp) + + if (n == 0) + 1015ea8: e0bff717 ldw r2,-36(fp) + 1015eac: 1005003a cmpeq r2,r2,zero + 1015eb0: 10001f1e bne r2,zero,1015f30 + break; /* No more data available */ + + if (n > space) + 1015eb4: e0fffd17 ldw r3,-12(fp) + 1015eb8: e0bff717 ldw r2,-36(fp) + 1015ebc: 1880022e bgeu r3,r2,1015ec8 + n = space; + 1015ec0: e0bffd17 ldw r2,-12(fp) + 1015ec4: e0bff715 stw r2,-36(fp) + + memcpy(ptr, sp->rx_buf + out, n); + 1015ec8: e0bffb17 ldw r2,-20(fp) + 1015ecc: 10c01104 addi r3,r2,68 + 1015ed0: e0bff517 ldw r2,-44(fp) + 1015ed4: 1887883a add r3,r3,r2 + 1015ed8: e0bff917 ldw r2,-28(fp) + 1015edc: 1009883a mov r4,r2 + 1015ee0: 180b883a mov r5,r3 + 1015ee4: e1bff717 ldw r6,-36(fp) + 1015ee8: 1007fcc0 call 1007fcc + ptr += n; + 1015eec: e0fff717 ldw r3,-36(fp) + 1015ef0: e0bff917 ldw r2,-28(fp) + 1015ef4: 10c5883a add r2,r2,r3 + 1015ef8: e0bff915 stw r2,-28(fp) + space -= n; + 1015efc: e0fffd17 ldw r3,-12(fp) + 1015f00: e0bff717 ldw r2,-36(fp) + 1015f04: 1885c83a sub r2,r3,r2 + 1015f08: e0bffd15 stw r2,-12(fp) + + sp->rx_out = (out + n) % ALTERA_AVALON_JTAG_UART_BUF_LEN; + 1015f0c: e0fff517 ldw r3,-44(fp) + 1015f10: e0bff717 ldw r2,-36(fp) + 1015f14: 1885883a add r2,r3,r2 + 1015f18: 10c1ffcc andi r3,r2,2047 + 1015f1c: e0bffb17 ldw r2,-20(fp) + 1015f20: 10c00e15 stw r3,56(r2) + } + while (space > 0); + 1015f24: e0bffd17 ldw r2,-12(fp) + 1015f28: 10800048 cmpgei r2,r2,1 + 1015f2c: 103fcc1e bne r2,zero,1015e60 + + /* If we read any data then return it */ + if (ptr != buffer) + 1015f30: e0fff917 ldw r3,-28(fp) + 1015f34: e0bffc17 ldw r2,-16(fp) + 1015f38: 1880301e bne r3,r2,1015ffc + break; + + /* If in non-blocking mode then return error */ + if (flags & O_NONBLOCK) + 1015f3c: e0bffe17 ldw r2,-8(fp) + 1015f40: 1090000c andi r2,r2,16384 + 1015f44: 1004c03a cmpne r2,r2,zero + 1015f48: 10002c1e bne r2,zero,1015ffc + break; + +#ifdef __ucosii__ + /* OS Present: Pend on a flag if the OS is running, otherwise spin */ + if(OSRunning == OS_TRUE) { + 1015f4c: 008040b4 movhi r2,258 + 1015f50: 10b31044 addi r2,r2,-13247 + 1015f54: 10800003 ldbu r2,0(r2) + 1015f58: 10803fcc andi r2,r2,255 + 1015f5c: 10800058 cmpnei r2,r2,1 + 1015f60: 1000161e bne r2,zero,1015fbc + * When running in a multi-threaded mode, we pend on the read event + * flag set and timeout event flag set in the isr. This avoids wasting CPU + * cycles waiting in this thread, when we could be doing something more + * profitable elsewhere. + */ + ALT_FLAG_PEND (sp->events, + 1015f64: e0bffb17 ldw r2,-20(fp) + 1015f68: 10800c17 ldw r2,48(r2) + 1015f6c: e0bff015 stw r2,-64(fp) + 1015f70: 00800144 movi r2,5 + 1015f74: e0bff10d sth r2,-60(fp) + 1015f78: 00bfe0c4 movi r2,-125 + 1015f7c: e0bff185 stb r2,-58(fp) + 1015f80: e03ff20d sth zero,-56(fp) + OS_FLAGS flags, + INT8U wait_type, + INT16U timeout) +{ + INT8U err; + if (OSRunning) + 1015f84: 008040b4 movhi r2,258 + 1015f88: 10b31044 addi r2,r2,-13247 + 1015f8c: 10800003 ldbu r2,0(r2) + 1015f90: 10803fcc andi r2,r2,255 + 1015f94: 1005003a cmpeq r2,r2,zero + 1015f98: 1000111e bne r2,zero,1015fe0 + { + OSFlagPend (group, flags, wait_type, timeout, &err); + 1015f9c: e17ff10b ldhu r5,-60(fp) + 1015fa0: e1bff183 ldbu r6,-58(fp) + 1015fa4: e1fff20b ldhu r7,-56(fp) + 1015fa8: e0bffa04 addi r2,fp,-24 + 1015fac: d8800015 stw r2,0(sp) + 1015fb0: e13ff017 ldw r4,-64(fp) + 1015fb4: 100fedc0 call 100fedc + return err; + 1015fb8: 00000906 br 1015fe0 + OS_FLAG_WAIT_SET_ANY + OS_FLAG_CONSUME, + 0); + } + else { + /* Spin until more data arrives or until host disconnects */ + while (in == sp->rx_in && sp->host_inactive < sp->timeout) + 1015fbc: e0bffb17 ldw r2,-20(fp) + 1015fc0: 10c00d17 ldw r3,52(r2) + 1015fc4: e0bff617 ldw r2,-40(fp) + 1015fc8: 1880051e bne r3,r2,1015fe0 + 1015fcc: e0bffb17 ldw r2,-20(fp) + 1015fd0: 10c00917 ldw r3,36(r2) + 1015fd4: e0bffb17 ldw r2,-20(fp) + 1015fd8: 10800117 ldw r2,4(r2) + 1015fdc: 18bff736 bltu r3,r2,1015fbc + /* No OS: Always spin */ + while (in == sp->rx_in && sp->host_inactive < sp->timeout) + ; +#endif /* __ucosii__ */ + + if (in == sp->rx_in) + 1015fe0: e0bffb17 ldw r2,-20(fp) + 1015fe4: 10c00d17 ldw r3,52(r2) + 1015fe8: e0bff617 ldw r2,-40(fp) + 1015fec: 18800326 beq r3,r2,1015ffc + * When running in a multi threaded environment, obtain the "read_lock" + * semaphore. This ensures that reading from the device is thread-safe. + */ + ALT_SEM_PEND (sp->read_lock, 0); + + while (space > 0) + 1015ff0: e0bffd17 ldw r2,-12(fp) + 1015ff4: 10800048 cmpgei r2,r2,1 + 1015ff8: 103f991e bne r2,zero,1015e60 + /* + * Now that access to the circular buffer is complete, release the read + * semaphore so that other threads can access the buffer. + */ + + ALT_SEM_POST (sp->read_lock); + 1015ffc: e0bffb17 ldw r2,-20(fp) + 1016000: 11000a17 ldw r4,40(r2) + 1016004: 10132100 call 1013210 + + if (ptr != buffer) + 1016008: e0fff917 ldw r3,-28(fp) + 101600c: e0bffc17 ldw r2,-16(fp) + 1016010: 18801926 beq r3,r2,1016078 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1016014: 0005303a rdctl r2,status + 1016018: e0bfef15 stw r2,-68(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 101601c: e0ffef17 ldw r3,-68(fp) + 1016020: 00bfff84 movi r2,-2 + 1016024: 1884703a and r2,r3,r2 + 1016028: 1001703a wrctl status,r2 + + return context; + 101602c: e0bfef17 ldw r2,-68(fp) + { + /* If we read any data then there is space in the buffer so enable interrupts */ + context = alt_irq_disable_all(); + 1016030: e0bff815 stw r2,-32(fp) + sp->irq_enable |= ALTERA_AVALON_JTAG_UART_CONTROL_RE_MSK; + 1016034: e0bffb17 ldw r2,-20(fp) + 1016038: 10800817 ldw r2,32(r2) + 101603c: 10c00054 ori r3,r2,1 + 1016040: e0bffb17 ldw r2,-20(fp) + 1016044: 10c00815 stw r3,32(r2) + IOWR_ALTERA_AVALON_JTAG_UART_CONTROL(sp->base, sp->irq_enable); + 1016048: e0bffb17 ldw r2,-20(fp) + 101604c: 10800017 ldw r2,0(r2) + 1016050: 11000104 addi r4,r2,4 + 1016054: e0bffb17 ldw r2,-20(fp) + 1016058: 10800817 ldw r2,32(r2) + 101605c: 1007883a mov r3,r2 + 1016060: 2005883a mov r2,r4 + 1016064: 10c00035 stwio r3,0(r2) + 1016068: e0bff817 ldw r2,-32(fp) + 101606c: e0bfee15 stw r2,-72(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1016070: e0bfee17 ldw r2,-72(fp) + 1016074: 1001703a wrctl status,r2 + alt_irq_enable_all(context); + } + + if (ptr != buffer) + 1016078: e0fff917 ldw r3,-28(fp) + 101607c: e0bffc17 ldw r2,-16(fp) + 1016080: 18800526 beq r3,r2,1016098 + return ptr - buffer; + 1016084: e0fff917 ldw r3,-28(fp) + 1016088: e0bffc17 ldw r2,-16(fp) + 101608c: 1887c83a sub r3,r3,r2 + 1016090: e0ffff15 stw r3,-4(fp) + 1016094: 00000906 br 10160bc + else if (flags & O_NONBLOCK) + 1016098: e0bffe17 ldw r2,-8(fp) + 101609c: 1090000c andi r2,r2,16384 + 10160a0: 1005003a cmpeq r2,r2,zero + 10160a4: 1000031e bne r2,zero,10160b4 + return -EWOULDBLOCK; + 10160a8: 00bffd44 movi r2,-11 + 10160ac: e0bfff15 stw r2,-4(fp) + 10160b0: 00000206 br 10160bc + else + return -EIO; + 10160b4: 00bffec4 movi r2,-5 + 10160b8: e0bfff15 stw r2,-4(fp) + 10160bc: e0bfff17 ldw r2,-4(fp) +} + 10160c0: e037883a mov sp,fp + 10160c4: dfc00117 ldw ra,4(sp) + 10160c8: df000017 ldw fp,0(sp) + 10160cc: dec00204 addi sp,sp,8 + 10160d0: f800283a ret + +010160d4 : +/* ----------------------------------------------------------- */ + +int +altera_avalon_jtag_uart_write(altera_avalon_jtag_uart_state* sp, + const char * ptr, int count, int flags) +{ + 10160d4: deffeb04 addi sp,sp,-84 + 10160d8: dfc01415 stw ra,80(sp) + 10160dc: df001315 stw fp,76(sp) + 10160e0: df001304 addi fp,sp,76 + 10160e4: e13ffb15 stw r4,-20(fp) + 10160e8: e17ffc15 stw r5,-16(fp) + 10160ec: e1bffd15 stw r6,-12(fp) + 10160f0: e1fffe15 stw r7,-8(fp) + /* Remove warning at optimisation level 03 by seting out to 0 */ + unsigned int in, out=0; + 10160f4: e03ff815 stw zero,-32(fp) + unsigned int n; + alt_irq_context context; + + const char * start = ptr; + 10160f8: e0bffc17 ldw r2,-16(fp) + 10160fc: e0bff515 stw r2,-44(fp) + + /* + * When running in a multi threaded environment, obtain the "write_lock" + * semaphore. This ensures that writing to the device is thread-safe. + */ + ALT_SEM_PEND (sp->write_lock, 0); + 1016100: e0bffb17 ldw r2,-20(fp) + 1016104: 10800b17 ldw r2,44(r2) + 1016108: e0bff315 stw r2,-52(fp) + 101610c: e03ff40d sth zero,-48(fp) + 1016110: e17ff40b ldhu r5,-48(fp) + 1016114: e1bffa04 addi r6,fp,-24 + 1016118: e13ff317 ldw r4,-52(fp) + 101611c: 1012e180 call 1012e18 + + do + { + /* Copy as much as we can into the transmit buffer */ + while (count > 0) + 1016120: 00003a06 br 101620c + { + /* We need a stable value of the out pointer to calculate the space available */ + in = sp->tx_in; + 1016124: e0bffb17 ldw r2,-20(fp) + 1016128: 10800f17 ldw r2,60(r2) + 101612c: e0bff915 stw r2,-28(fp) + out = sp->tx_out; + 1016130: e0bffb17 ldw r2,-20(fp) + 1016134: 10801017 ldw r2,64(r2) + 1016138: e0bff815 stw r2,-32(fp) + + if (in < out) + 101613c: e0fff917 ldw r3,-28(fp) + 1016140: e0bff817 ldw r2,-32(fp) + 1016144: 1880062e bgeu r3,r2,1016160 + n = out - 1 - in; + 1016148: e0fff817 ldw r3,-32(fp) + 101614c: e0bff917 ldw r2,-28(fp) + 1016150: 1885c83a sub r2,r3,r2 + 1016154: 10bfffc4 addi r2,r2,-1 + 1016158: e0bff715 stw r2,-36(fp) + 101615c: 00000c06 br 1016190 + else if (out > 0) + 1016160: e0bff817 ldw r2,-32(fp) + 1016164: 1005003a cmpeq r2,r2,zero + 1016168: 1000051e bne r2,zero,1016180 + n = ALTERA_AVALON_JTAG_UART_BUF_LEN - in; + 101616c: 00820004 movi r2,2048 + 1016170: e0fff917 ldw r3,-28(fp) + 1016174: 10c5c83a sub r2,r2,r3 + 1016178: e0bff715 stw r2,-36(fp) + 101617c: 00000406 br 1016190 + else + n = ALTERA_AVALON_JTAG_UART_BUF_LEN - 1 - in; + 1016180: 0081ffc4 movi r2,2047 + 1016184: e0fff917 ldw r3,-28(fp) + 1016188: 10c5c83a sub r2,r2,r3 + 101618c: e0bff715 stw r2,-36(fp) + + if (n == 0) + 1016190: e0bff717 ldw r2,-36(fp) + 1016194: 1005003a cmpeq r2,r2,zero + 1016198: 10001f1e bne r2,zero,1016218 + break; + + if (n > count) + 101619c: e0fffd17 ldw r3,-12(fp) + 10161a0: e0bff717 ldw r2,-36(fp) + 10161a4: 1880022e bgeu r3,r2,10161b0 + n = count; + 10161a8: e0bffd17 ldw r2,-12(fp) + 10161ac: e0bff715 stw r2,-36(fp) + + memcpy(sp->tx_buf + in, ptr, n); + 10161b0: e0bffb17 ldw r2,-20(fp) + 10161b4: 10c21104 addi r3,r2,2116 + 10161b8: e0bff917 ldw r2,-28(fp) + 10161bc: 1885883a add r2,r3,r2 + 10161c0: e0fffc17 ldw r3,-16(fp) + 10161c4: 1009883a mov r4,r2 + 10161c8: 180b883a mov r5,r3 + 10161cc: e1bff717 ldw r6,-36(fp) + 10161d0: 1007fcc0 call 1007fcc + ptr += n; + 10161d4: e0fff717 ldw r3,-36(fp) + 10161d8: e0bffc17 ldw r2,-16(fp) + 10161dc: 10c5883a add r2,r2,r3 + 10161e0: e0bffc15 stw r2,-16(fp) + count -= n; + 10161e4: e0fffd17 ldw r3,-12(fp) + 10161e8: e0bff717 ldw r2,-36(fp) + 10161ec: 1885c83a sub r2,r3,r2 + 10161f0: e0bffd15 stw r2,-12(fp) + + sp->tx_in = (in + n) % ALTERA_AVALON_JTAG_UART_BUF_LEN; + 10161f4: e0fff917 ldw r3,-28(fp) + 10161f8: e0bff717 ldw r2,-36(fp) + 10161fc: 1885883a add r2,r3,r2 + 1016200: 10c1ffcc andi r3,r2,2047 + 1016204: e0bffb17 ldw r2,-20(fp) + 1016208: 10c00f15 stw r3,60(r2) + ALT_SEM_PEND (sp->write_lock, 0); + + do + { + /* Copy as much as we can into the transmit buffer */ + while (count > 0) + 101620c: e0bffd17 ldw r2,-12(fp) + 1016210: 10800048 cmpgei r2,r2,1 + 1016214: 103fc31e bne r2,zero,1016124 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1016218: 0005303a rdctl r2,status + 101621c: e0bff215 stw r2,-56(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1016220: e0fff217 ldw r3,-56(fp) + 1016224: 00bfff84 movi r2,-2 + 1016228: 1884703a and r2,r3,r2 + 101622c: 1001703a wrctl status,r2 + + return context; + 1016230: e0bff217 ldw r2,-56(fp) + * to enable interrupts if there is no space left in the FIFO + * + * For now kick the interrupt routine every time to make it transmit + * the data + */ + context = alt_irq_disable_all(); + 1016234: e0bff615 stw r2,-40(fp) + sp->irq_enable |= ALTERA_AVALON_JTAG_UART_CONTROL_WE_MSK; + 1016238: e0bffb17 ldw r2,-20(fp) + 101623c: 10800817 ldw r2,32(r2) + 1016240: 10c00094 ori r3,r2,2 + 1016244: e0bffb17 ldw r2,-20(fp) + 1016248: 10c00815 stw r3,32(r2) + IOWR_ALTERA_AVALON_JTAG_UART_CONTROL(sp->base, sp->irq_enable); + 101624c: e0bffb17 ldw r2,-20(fp) + 1016250: 10800017 ldw r2,0(r2) + 1016254: 11000104 addi r4,r2,4 + 1016258: e0bffb17 ldw r2,-20(fp) + 101625c: 10800817 ldw r2,32(r2) + 1016260: 1007883a mov r3,r2 + 1016264: 2005883a mov r2,r4 + 1016268: 10c00035 stwio r3,0(r2) + 101626c: e0bff617 ldw r2,-40(fp) + 1016270: e0bff115 stw r2,-60(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1016274: e0bff117 ldw r2,-60(fp) + 1016278: 1001703a wrctl status,r2 + /* + * If there is any data left then either return now or block until + * some has been sent + */ + /* consider: test whether there is anything there while doing this and delay for at most 2s. */ + if (count > 0) + 101627c: e0bffd17 ldw r2,-12(fp) + 1016280: 10800050 cmplti r2,r2,1 + 1016284: 10002d1e bne r2,zero,101633c + { + if (flags & O_NONBLOCK) + 1016288: e0bffe17 ldw r2,-8(fp) + 101628c: 1090000c andi r2,r2,16384 + 1016290: 1004c03a cmpne r2,r2,zero + 1016294: 10002c1e bne r2,zero,1016348 + break; + +#ifdef __ucosii__ + /* OS Present: Pend on a flag if the OS is running, otherwise spin */ + if(OSRunning == OS_TRUE) { + 1016298: 008040b4 movhi r2,258 + 101629c: 10b31044 addi r2,r2,-13247 + 10162a0: 10800003 ldbu r2,0(r2) + 10162a4: 10803fcc andi r2,r2,255 + 10162a8: 10800058 cmpnei r2,r2,1 + 10162ac: 1000161e bne r2,zero,1016308 + * When running in a multi-threaded mode, we pend on the write event + * flag set or the timeout flag in the isr. This avoids wasting CPU + * cycles waiting in this thread, when we could be doing something + * more profitable elsewhere. + */ + ALT_FLAG_PEND (sp->events, + 10162b0: e0bffb17 ldw r2,-20(fp) + 10162b4: 10800c17 ldw r2,48(r2) + 10162b8: e0bfee15 stw r2,-72(fp) + 10162bc: 00800184 movi r2,6 + 10162c0: e0bfef0d sth r2,-68(fp) + 10162c4: 00bfe0c4 movi r2,-125 + 10162c8: e0bfef85 stb r2,-66(fp) + 10162cc: e03ff00d sth zero,-64(fp) + OS_FLAGS flags, + INT8U wait_type, + INT16U timeout) +{ + INT8U err; + if (OSRunning) + 10162d0: 008040b4 movhi r2,258 + 10162d4: 10b31044 addi r2,r2,-13247 + 10162d8: 10800003 ldbu r2,0(r2) + 10162dc: 10803fcc andi r2,r2,255 + 10162e0: 1005003a cmpeq r2,r2,zero + 10162e4: 1000111e bne r2,zero,101632c + { + OSFlagPend (group, flags, wait_type, timeout, &err); + 10162e8: e17fef0b ldhu r5,-68(fp) + 10162ec: e1bfef83 ldbu r6,-66(fp) + 10162f0: e1fff00b ldhu r7,-64(fp) + 10162f4: e0bffa44 addi r2,fp,-23 + 10162f8: d8800015 stw r2,0(sp) + 10162fc: e13fee17 ldw r4,-72(fp) + 1016300: 100fedc0 call 100fedc + return err; + 1016304: 00000906 br 101632c + /* + * OS not running: Wait for data to be removed from buffer. + * Once the interrupt routine has removed some data then we + * will be able to insert some more. + */ + while (out == sp->tx_out && sp->host_inactive < sp->timeout) + 1016308: e0bffb17 ldw r2,-20(fp) + 101630c: 10c01017 ldw r3,64(r2) + 1016310: e0bff817 ldw r2,-32(fp) + 1016314: 1880051e bne r3,r2,101632c + 1016318: e0bffb17 ldw r2,-20(fp) + 101631c: 10c00917 ldw r3,36(r2) + 1016320: e0bffb17 ldw r2,-20(fp) + 1016324: 10800117 ldw r2,4(r2) + 1016328: 18bff736 bltu r3,r2,1016308 + */ + while (out == sp->tx_out && sp->host_inactive < sp->timeout) + ; +#endif /* __ucosii__ */ + + if (out == sp->tx_out) + 101632c: e0bffb17 ldw r2,-20(fp) + 1016330: 10c01017 ldw r3,64(r2) + 1016334: e0bff817 ldw r2,-32(fp) + 1016338: 18800326 beq r3,r2,1016348 + break; + } + } + while (count > 0); + 101633c: e0bffd17 ldw r2,-12(fp) + 1016340: 10800048 cmpgei r2,r2,1 + 1016344: 103fb11e bne r2,zero,101620c + + /* + * Now that access to the circular buffer is complete, release the write + * semaphore so that other threads can access the buffer. + */ + ALT_SEM_POST (sp->write_lock); + 1016348: e0bffb17 ldw r2,-20(fp) + 101634c: 11000b17 ldw r4,44(r2) + 1016350: 10132100 call 1013210 + + if (ptr != start) + 1016354: e0fffc17 ldw r3,-16(fp) + 1016358: e0bff517 ldw r2,-44(fp) + 101635c: 18800526 beq r3,r2,1016374 + return ptr - start; + 1016360: e0fffc17 ldw r3,-16(fp) + 1016364: e0bff517 ldw r2,-44(fp) + 1016368: 1887c83a sub r3,r3,r2 + 101636c: e0ffff15 stw r3,-4(fp) + 1016370: 00000906 br 1016398 + else if (flags & O_NONBLOCK) + 1016374: e0bffe17 ldw r2,-8(fp) + 1016378: 1090000c andi r2,r2,16384 + 101637c: 1005003a cmpeq r2,r2,zero + 1016380: 1000031e bne r2,zero,1016390 + return -EWOULDBLOCK; + 1016384: 00bffd44 movi r2,-11 + 1016388: e0bfff15 stw r2,-4(fp) + 101638c: 00000206 br 1016398 + else + return -EIO; /* Host not connected */ + 1016390: 00bffec4 movi r2,-5 + 1016394: e0bfff15 stw r2,-4(fp) + 1016398: e0bfff17 ldw r2,-4(fp) +} + 101639c: e037883a mov sp,fp + 10163a0: dfc00117 ldw ra,4(sp) + 10163a4: df000017 ldw fp,0(sp) + 10163a8: dec00204 addi sp,sp,8 + 10163ac: f800283a ret + +010163b0 : +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT +static void alt_avalon_timer_sc_irq (void* base) +#else +static void alt_avalon_timer_sc_irq (void* base, alt_u32 id) +#endif +{ + 10163b0: defff904 addi sp,sp,-28 + 10163b4: dfc00615 stw ra,24(sp) + 10163b8: df000515 stw fp,20(sp) + 10163bc: df000504 addi fp,sp,20 + 10163c0: e13ffe15 stw r4,-8(fp) + 10163c4: e17fff15 stw r5,-4(fp) + alt_irq_context cpu_sr; + + /* clear the interrupt */ + IOWR_ALTERA_AVALON_TIMER_STATUS (base, 0); + 10163c8: e0bffe17 ldw r2,-8(fp) + 10163cc: 10000035 stwio zero,0(r2) + /* + * Dummy read to ensure IRQ is negated before the ISR returns. + * The control register is read because reading the status + * register has side-effects per the register map documentation. + */ + IORD_ALTERA_AVALON_TIMER_CONTROL (base); + 10163d0: e0bffe17 ldw r2,-8(fp) + 10163d4: 10800104 addi r2,r2,4 + 10163d8: 10800037 ldwio r2,0(r2) +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 10163dc: 0005303a rdctl r2,status + 10163e0: e0bffc15 stw r2,-16(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 10163e4: e0fffc17 ldw r3,-16(fp) + 10163e8: 00bfff84 movi r2,-2 + 10163ec: 1884703a and r2,r3,r2 + 10163f0: 1001703a wrctl status,r2 + + return context; + 10163f4: e0bffc17 ldw r2,-16(fp) + + /* + * Notify the system of a clock tick. disable interrupts + * during this time to safely support ISR preemption + */ + cpu_sr = alt_irq_disable_all(); + 10163f8: e0bffd15 stw r2,-12(fp) + alt_tick (); + 10163fc: 1017efc0 call 1017efc + 1016400: e0bffd17 ldw r2,-12(fp) + 1016404: e0bffb15 stw r2,-20(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1016408: e0bffb17 ldw r2,-20(fp) + 101640c: 1001703a wrctl status,r2 + alt_irq_enable_all(cpu_sr); +} + 1016410: e037883a mov sp,fp + 1016414: dfc00117 ldw ra,4(sp) + 1016418: df000017 ldw fp,0(sp) + 101641c: dec00204 addi sp,sp,8 + 1016420: f800283a ret + +01016424 : + * auto-generated alt_sys_init() function. + */ + +void alt_avalon_timer_sc_init (void* base, alt_u32 irq_controller_id, + alt_u32 irq, alt_u32 freq) +{ + 1016424: defff904 addi sp,sp,-28 + 1016428: dfc00615 stw ra,24(sp) + 101642c: df000515 stw fp,20(sp) + 1016430: df000504 addi fp,sp,20 + 1016434: e13ffc15 stw r4,-16(fp) + 1016438: e17ffd15 stw r5,-12(fp) + 101643c: e1bffe15 stw r6,-8(fp) + 1016440: e1ffff15 stw r7,-4(fp) + 1016444: e0bfff17 ldw r2,-4(fp) + 1016448: e0bffb15 stw r2,-20(fp) + * in order to initialise the value of the clock frequency. + */ + +static ALT_INLINE int ALT_ALWAYS_INLINE alt_sysclk_init (alt_u32 nticks) +{ + if (! _alt_tick_rate) + 101644c: 008040b4 movhi r2,258 + 1016450: 10b32504 addi r2,r2,-13164 + 1016454: 10800017 ldw r2,0(r2) + 1016458: 1004c03a cmpne r2,r2,zero + 101645c: 1000041e bne r2,zero,1016470 + { + _alt_tick_rate = nticks; + 1016460: 00c040b4 movhi r3,258 + 1016464: 18f32504 addi r3,r3,-13164 + 1016468: e0bffb17 ldw r2,-20(fp) + 101646c: 18800015 stw r2,0(r3) + + alt_sysclk_init (freq); + + /* set to free running mode */ + + IOWR_ALTERA_AVALON_TIMER_CONTROL (base, + 1016470: e0bffc17 ldw r2,-16(fp) + 1016474: 10800104 addi r2,r2,4 + 1016478: 1007883a mov r3,r2 + 101647c: 008001c4 movi r2,7 + 1016480: 18800035 stwio r2,0(r3) + /* register the interrupt handler, and enable the interrupt */ +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT + alt_ic_isr_register(irq_controller_id, irq, alt_avalon_timer_sc_irq, + base, NULL); +#else + alt_irq_register (irq, base, alt_avalon_timer_sc_irq); + 1016484: e13ffe17 ldw r4,-8(fp) + 1016488: e17ffc17 ldw r5,-16(fp) + 101648c: 01804074 movhi r6,257 + 1016490: 3198ec04 addi r6,r6,25520 + 1016494: 10179e00 call 10179e0 +#endif +} + 1016498: e037883a mov sp,fp + 101649c: dfc00117 ldw ra,4(sp) + 10164a0: df000017 ldw fp,0(sp) + 10164a4: dec00204 addi sp,sp,8 + 10164a8: f800283a ret + +010164ac : + * + */ + +int +altera_avalon_uart_read_fd(alt_fd* fd, char* buffer, int space) +{ + 10164ac: defffa04 addi sp,sp,-24 + 10164b0: dfc00515 stw ra,20(sp) + 10164b4: df000415 stw fp,16(sp) + 10164b8: df000404 addi fp,sp,16 + 10164bc: e13ffd15 stw r4,-12(fp) + 10164c0: e17ffe15 stw r5,-8(fp) + 10164c4: e1bfff15 stw r6,-4(fp) + altera_avalon_uart_dev* dev = (altera_avalon_uart_dev*) fd->dev; + 10164c8: e0bffd17 ldw r2,-12(fp) + 10164cc: 10800017 ldw r2,0(r2) + 10164d0: e0bffc15 stw r2,-16(fp) + + return altera_avalon_uart_read(&dev->state, buffer, space, + 10164d4: e0bffc17 ldw r2,-16(fp) + 10164d8: 11000a04 addi r4,r2,40 + 10164dc: e0bffd17 ldw r2,-12(fp) + 10164e0: 11c00217 ldw r7,8(r2) + 10164e4: e17ffe17 ldw r5,-8(fp) + 10164e8: e1bfff17 ldw r6,-4(fp) + 10164ec: 1016b1c0 call 1016b1c + fd->fd_flags); +} + 10164f0: e037883a mov sp,fp + 10164f4: dfc00117 ldw ra,4(sp) + 10164f8: df000017 ldw fp,0(sp) + 10164fc: dec00204 addi sp,sp,8 + 1016500: f800283a ret + +01016504 : + +int +altera_avalon_uart_write_fd(alt_fd* fd, const char* buffer, int space) +{ + 1016504: defffa04 addi sp,sp,-24 + 1016508: dfc00515 stw ra,20(sp) + 101650c: df000415 stw fp,16(sp) + 1016510: df000404 addi fp,sp,16 + 1016514: e13ffd15 stw r4,-12(fp) + 1016518: e17ffe15 stw r5,-8(fp) + 101651c: e1bfff15 stw r6,-4(fp) + altera_avalon_uart_dev* dev = (altera_avalon_uart_dev*) fd->dev; + 1016520: e0bffd17 ldw r2,-12(fp) + 1016524: 10800017 ldw r2,0(r2) + 1016528: e0bffc15 stw r2,-16(fp) + + return altera_avalon_uart_write(&dev->state, buffer, space, + 101652c: e0bffc17 ldw r2,-16(fp) + 1016530: 11000a04 addi r4,r2,40 + 1016534: e0bffd17 ldw r2,-12(fp) + 1016538: 11c00217 ldw r7,8(r2) + 101653c: e17ffe17 ldw r5,-8(fp) + 1016540: e1bfff17 ldw r6,-4(fp) + 1016544: 1016e2c0 call 1016e2c + fd->fd_flags); +} + 1016548: e037883a mov sp,fp + 101654c: dfc00117 ldw ra,4(sp) + 1016550: df000017 ldw fp,0(sp) + 1016554: dec00204 addi sp,sp,8 + 1016558: f800283a ret + +0101655c : + +#endif /* ALTERA_AVALON_UART_USE_IOCTL */ + +int +altera_avalon_uart_close_fd(alt_fd* fd) +{ + 101655c: defffc04 addi sp,sp,-16 + 1016560: dfc00315 stw ra,12(sp) + 1016564: df000215 stw fp,8(sp) + 1016568: df000204 addi fp,sp,8 + 101656c: e13fff15 stw r4,-4(fp) + altera_avalon_uart_dev* dev = (altera_avalon_uart_dev*) fd->dev; + 1016570: e0bfff17 ldw r2,-4(fp) + 1016574: 10800017 ldw r2,0(r2) + 1016578: e0bffe15 stw r2,-8(fp) + + return altera_avalon_uart_close(&dev->state, fd->fd_flags); + 101657c: e0bffe17 ldw r2,-8(fp) + 1016580: 11000a04 addi r4,r2,40 + 1016584: e0bfff17 ldw r2,-4(fp) + 1016588: 11400217 ldw r5,8(r2) + 101658c: 1016abc0 call 1016abc +} + 1016590: e037883a mov sp,fp + 1016594: dfc00117 ldw ra,4(sp) + 1016598: df000017 ldw fp,0(sp) + 101659c: dec00204 addi sp,sp,8 + 10165a0: f800283a ret + +010165a4 : + alt_u32 status); + +void +altera_avalon_uart_init(altera_avalon_uart_state* sp, + alt_u32 irq_controller_id, alt_u32 irq) +{ + 10165a4: deffef04 addi sp,sp,-68 + 10165a8: dfc01015 stw ra,64(sp) + 10165ac: df000f15 stw fp,60(sp) + 10165b0: df000f04 addi fp,sp,60 + 10165b4: e13ffa15 stw r4,-24(fp) + 10165b8: e17ffb15 stw r5,-20(fp) + 10165bc: e1bffc15 stw r6,-16(fp) + void* base = sp->base; + 10165c0: e0bffa17 ldw r2,-24(fp) + 10165c4: 10800017 ldw r2,0(r2) + 10165c8: e0bff815 stw r2,-32(fp) + /* + * Initialise the read and write flags and the semaphores used to + * protect access to the circular buffers when running in a multi-threaded + * environment. + */ + error = ALT_FLAG_CREATE (&sp->events, 0) || + 10165cc: e0bffa17 ldw r2,-24(fp) + 10165d0: 10800704 addi r2,r2,28 + 10165d4: e0bff515 stw r2,-44(fp) + 10165d8: e03ff60d sth zero,-40(fp) + +static ALT_INLINE int ALT_ALWAYS_INLINE alt_flag_create (OS_FLAG_GRP** pgroup, + OS_FLAGS flags) +{ + INT8U err; + *pgroup = OSFlagCreate (flags, &err); + 10165dc: e13ff60b ldhu r4,-40(fp) + 10165e0: e17ff904 addi r5,fp,-28 + 10165e4: 100f8600 call 100f860 + 10165e8: 1007883a mov r3,r2 + 10165ec: e0bff517 ldw r2,-44(fp) + 10165f0: 10c00015 stw r3,0(r2) + return err; + 10165f4: e0bff903 ldbu r2,-28(fp) + 10165f8: 10803fcc andi r2,r2,255 + 10165fc: 1004c03a cmpne r2,r2,zero + 1016600: 10002a1e bne r2,zero,10166ac + 1016604: e0bffa17 ldw r2,-24(fp) + 1016608: 10800804 addi r2,r2,32 + 101660c: e0bff315 stw r2,-52(fp) + 1016610: 00800044 movi r2,1 + 1016614: e0bff40d sth r2,-48(fp) + */ + +static ALT_INLINE int ALT_ALWAYS_INLINE alt_sem_create (OS_EVENT** sem, + INT16U value) +{ + *sem = OSSemCreate (value); + 1016618: e13ff40b ldhu r4,-48(fp) + 101661c: 1012a640 call 1012a64 + 1016620: 1007883a mov r3,r2 + 1016624: e0bff317 ldw r2,-52(fp) + 1016628: 10c00015 stw r3,0(r2) + return *sem ? 0 : -1; + 101662c: e0bff317 ldw r2,-52(fp) + 1016630: 10800017 ldw r2,0(r2) + 1016634: 1005003a cmpeq r2,r2,zero + 1016638: 1000021e bne r2,zero,1016644 + 101663c: e03ffe15 stw zero,-8(fp) + 1016640: 00000206 br 101664c + 1016644: 00bfffc4 movi r2,-1 + 1016648: e0bffe15 stw r2,-8(fp) + 101664c: e0bffe17 ldw r2,-8(fp) + 1016650: 1004c03a cmpne r2,r2,zero + 1016654: 1000151e bne r2,zero,10166ac + 1016658: e0bffa17 ldw r2,-24(fp) + 101665c: 10800904 addi r2,r2,36 + 1016660: e0bff115 stw r2,-60(fp) + 1016664: 00800044 movi r2,1 + 1016668: e0bff20d sth r2,-56(fp) + */ + +static ALT_INLINE int ALT_ALWAYS_INLINE alt_sem_create (OS_EVENT** sem, + INT16U value) +{ + *sem = OSSemCreate (value); + 101666c: e13ff20b ldhu r4,-56(fp) + 1016670: 1012a640 call 1012a64 + 1016674: 1007883a mov r3,r2 + 1016678: e0bff117 ldw r2,-60(fp) + 101667c: 10c00015 stw r3,0(r2) + return *sem ? 0 : -1; + 1016680: e0bff117 ldw r2,-60(fp) + 1016684: 10800017 ldw r2,0(r2) + 1016688: 1005003a cmpeq r2,r2,zero + 101668c: 1000021e bne r2,zero,1016698 + 1016690: e03ffd15 stw zero,-12(fp) + 1016694: 00000206 br 10166a0 + 1016698: 00bfffc4 movi r2,-1 + 101669c: e0bffd15 stw r2,-12(fp) + 10166a0: e0bffd17 ldw r2,-12(fp) + 10166a4: 1005003a cmpeq r2,r2,zero + 10166a8: 1000031e bne r2,zero,10166b8 + 10166ac: 00800044 movi r2,1 + 10166b0: e0bfff15 stw r2,-4(fp) + 10166b4: 00000106 br 10166bc + 10166b8: e03fff15 stw zero,-4(fp) + 10166bc: e0bfff17 ldw r2,-4(fp) + 10166c0: e0bff715 stw r2,-36(fp) + ALT_SEM_CREATE (&sp->read_lock, 1) || + ALT_SEM_CREATE (&sp->write_lock, 1); + + if (!error) + 10166c4: e0bff717 ldw r2,-36(fp) + 10166c8: 1004c03a cmpne r2,r2,zero + 10166cc: 10000f1e bne r2,zero,101670c + { + /* enable interrupts at the device */ + sp->ctrl = ALTERA_AVALON_UART_CONTROL_RTS_MSK | + 10166d0: e0fffa17 ldw r3,-24(fp) + 10166d4: 00832004 movi r2,3200 + 10166d8: 18800115 stw r2,4(r3) + ALTERA_AVALON_UART_CONTROL_RRDY_MSK | + ALTERA_AVALON_UART_CONTROL_DCTS_MSK; + + IOWR_ALTERA_AVALON_UART_CONTROL(base, sp->ctrl); + 10166dc: e0bff817 ldw r2,-32(fp) + 10166e0: 11000304 addi r4,r2,12 + 10166e4: e0bffa17 ldw r2,-24(fp) + 10166e8: 10800117 ldw r2,4(r2) + 10166ec: 1007883a mov r3,r2 + 10166f0: 2005883a mov r2,r4 + 10166f4: 10c00035 stwio r3,0(r2) + /* register the interrupt handler */ +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT + alt_ic_isr_register(irq_controller_id, irq, altera_avalon_uart_irq, sp, + 0x0); +#else + alt_irq_register (irq, sp, altera_avalon_uart_irq); + 10166f8: e13ffc17 ldw r4,-16(fp) + 10166fc: e17ffa17 ldw r5,-24(fp) + 1016700: 01804074 movhi r6,257 + 1016704: 3199c804 addi r6,r6,26400 + 1016708: 10179e00 call 10179e0 +#endif + } +} + 101670c: e037883a mov sp,fp + 1016710: dfc00117 ldw ra,4(sp) + 1016714: df000017 ldw fp,0(sp) + 1016718: dec00204 addi sp,sp,8 + 101671c: f800283a ret + +01016720 : +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT +static void altera_avalon_uart_irq(void* context) +#else +static void altera_avalon_uart_irq(void* context, alt_u32 id) +#endif +{ + 1016720: defff904 addi sp,sp,-28 + 1016724: dfc00615 stw ra,24(sp) + 1016728: df000515 stw fp,20(sp) + 101672c: df000504 addi fp,sp,20 + 1016730: e13ffe15 stw r4,-8(fp) + 1016734: e17fff15 stw r5,-4(fp) + alt_u32 status; + + altera_avalon_uart_state* sp = (altera_avalon_uart_state*) context; + 1016738: e0bffe17 ldw r2,-8(fp) + 101673c: e0bffc15 stw r2,-16(fp) + void* base = sp->base; + 1016740: e0bffc17 ldw r2,-16(fp) + 1016744: 10800017 ldw r2,0(r2) + 1016748: e0bffb15 stw r2,-20(fp) + /* + * Read the status register in order to determine the cause of the + * interrupt. + */ + + status = IORD_ALTERA_AVALON_UART_STATUS(base); + 101674c: e0bffb17 ldw r2,-20(fp) + 1016750: 10800204 addi r2,r2,8 + 1016754: 10800037 ldwio r2,0(r2) + 1016758: e0bffd15 stw r2,-12(fp) + + /* Clear any error flags set at the device */ + IOWR_ALTERA_AVALON_UART_STATUS(base, 0); + 101675c: e0bffb17 ldw r2,-20(fp) + 1016760: 10800204 addi r2,r2,8 + 1016764: 10000035 stwio zero,0(r2) + + /* Dummy read to ensure IRQ is negated before ISR returns */ + IORD_ALTERA_AVALON_UART_STATUS(base); + 1016768: e0bffb17 ldw r2,-20(fp) + 101676c: 10800204 addi r2,r2,8 + 1016770: 10800037 ldwio r2,0(r2) + + /* process a read irq */ + if (status & ALTERA_AVALON_UART_STATUS_RRDY_MSK) + 1016774: e0bffd17 ldw r2,-12(fp) + 1016778: 1080200c andi r2,r2,128 + 101677c: 1005003a cmpeq r2,r2,zero + 1016780: 1000031e bne r2,zero,1016790 + { + altera_avalon_uart_rxirq(sp, status); + 1016784: e13ffc17 ldw r4,-16(fp) + 1016788: e17ffd17 ldw r5,-12(fp) + 101678c: 10167c00 call 10167c0 + } + + /* process a write irq */ + if (status & (ALTERA_AVALON_UART_STATUS_TRDY_MSK | + 1016790: e0bffd17 ldw r2,-12(fp) + 1016794: 1081100c andi r2,r2,1088 + 1016798: 1005003a cmpeq r2,r2,zero + 101679c: 1000031e bne r2,zero,10167ac + ALTERA_AVALON_UART_STATUS_DCTS_MSK)) + { + altera_avalon_uart_txirq(sp, status); + 10167a0: e13ffc17 ldw r4,-16(fp) + 10167a4: e17ffd17 ldw r5,-12(fp) + 10167a8: 10168fc0 call 10168fc + } + + +} + 10167ac: e037883a mov sp,fp + 10167b0: dfc00117 ldw ra,4(sp) + 10167b4: df000017 ldw fp,0(sp) + 10167b8: dec00204 addi sp,sp,8 + 10167bc: f800283a ret + +010167c0 : + * the receive circular buffer, and sets the apropriate flags to indicate + * that there is data ready to be processed. + */ +static void +altera_avalon_uart_rxirq(altera_avalon_uart_state* sp, alt_u32 status) +{ + 10167c0: defff804 addi sp,sp,-32 + 10167c4: dfc00715 stw ra,28(sp) + 10167c8: df000615 stw fp,24(sp) + 10167cc: df000604 addi fp,sp,24 + 10167d0: e13ffe15 stw r4,-8(fp) + 10167d4: e17fff15 stw r5,-4(fp) + alt_u32 next; + + /* If there was an error, discard the data */ + + if (status & (ALTERA_AVALON_UART_STATUS_PE_MSK | + 10167d8: e0bfff17 ldw r2,-4(fp) + 10167dc: 108000cc andi r2,r2,3 + 10167e0: 1004c03a cmpne r2,r2,zero + 10167e4: 1000401e bne r2,zero,10168e8 + * In a multi-threaded environment, set the read event flag to indicate + * that there is data ready. This is only done if the circular buffer was + * previously empty. + */ + + if (sp->rx_end == sp->rx_start) + 10167e8: e0bffe17 ldw r2,-8(fp) + 10167ec: 10c00317 ldw r3,12(r2) + 10167f0: e0bffe17 ldw r2,-8(fp) + 10167f4: 10800217 ldw r2,8(r2) + 10167f8: 1880121e bne r3,r2,1016844 + { + ALT_FLAG_POST (sp->events, ALT_UART_READ_RDY, OS_FLAG_SET); + 10167fc: e0bffe17 ldw r2,-8(fp) + 1016800: 10800717 ldw r2,28(r2) + 1016804: e0bffa15 stw r2,-24(fp) + 1016808: 00800044 movi r2,1 + 101680c: e0bffb0d sth r2,-20(fp) + 1016810: 00800044 movi r2,1 + 1016814: e0bffb85 stb r2,-18(fp) + OS_FLAGS flags, + INT8U opt) +{ + INT8U err; + + if (OSRunning) + 1016818: 008040b4 movhi r2,258 + 101681c: 10b31044 addi r2,r2,-13247 + 1016820: 10800003 ldbu r2,0(r2) + 1016824: 10803fcc andi r2,r2,255 + 1016828: 1005003a cmpeq r2,r2,zero + 101682c: 1000051e bne r2,zero,1016844 + { + OSFlagPost (group, flags, opt, &err); + 1016830: e17ffb0b ldhu r5,-20(fp) + 1016834: e1bffb83 ldbu r6,-18(fp) + 1016838: e1fffd04 addi r7,fp,-12 + 101683c: e13ffa17 ldw r4,-24(fp) + 1016840: 10105880 call 1010588 + } + + /* Determine which slot to use next in the circular buffer */ + + next = (sp->rx_end + 1) & ALT_AVALON_UART_BUF_MSK; + 1016844: e0bffe17 ldw r2,-8(fp) + 1016848: 10800317 ldw r2,12(r2) + 101684c: 10800044 addi r2,r2,1 + 1016850: 10800fcc andi r2,r2,63 + 1016854: e0bffc15 stw r2,-16(fp) + + /* Transfer data from the device to the circular buffer */ + + sp->rx_buf[sp->rx_end] = IORD_ALTERA_AVALON_UART_RXDATA(sp->base); + 1016858: e0bffe17 ldw r2,-8(fp) + 101685c: 11000317 ldw r4,12(r2) + 1016860: e0bffe17 ldw r2,-8(fp) + 1016864: 10800017 ldw r2,0(r2) + 1016868: 10800037 ldwio r2,0(r2) + 101686c: 1007883a mov r3,r2 + 1016870: e0bffe17 ldw r2,-8(fp) + 1016874: 2085883a add r2,r4,r2 + 1016878: 10800a04 addi r2,r2,40 + 101687c: 10c00005 stb r3,0(r2) + + sp->rx_end = next; + 1016880: e0fffe17 ldw r3,-8(fp) + 1016884: e0bffc17 ldw r2,-16(fp) + 1016888: 18800315 stw r2,12(r3) + + next = (sp->rx_end + 1) & ALT_AVALON_UART_BUF_MSK; + 101688c: e0bffe17 ldw r2,-8(fp) + 1016890: 10800317 ldw r2,12(r2) + 1016894: 10800044 addi r2,r2,1 + 1016898: 10800fcc andi r2,r2,63 + 101689c: e0bffc15 stw r2,-16(fp) + /* + * If the cicular buffer was full, disable interrupts. Interrupts will be + * re-enabled when data is removed from the buffer. + */ + + if (next == sp->rx_start) + 10168a0: e0bffe17 ldw r2,-8(fp) + 10168a4: 10c00217 ldw r3,8(r2) + 10168a8: e0bffc17 ldw r2,-16(fp) + 10168ac: 18800e1e bne r3,r2,10168e8 + { + sp->ctrl &= ~ALTERA_AVALON_UART_CONTROL_RRDY_MSK; + 10168b0: e0bffe17 ldw r2,-8(fp) + 10168b4: 10c00117 ldw r3,4(r2) + 10168b8: 00bfdfc4 movi r2,-129 + 10168bc: 1886703a and r3,r3,r2 + 10168c0: e0bffe17 ldw r2,-8(fp) + 10168c4: 10c00115 stw r3,4(r2) + IOWR_ALTERA_AVALON_UART_CONTROL(sp->base, sp->ctrl); + 10168c8: e0bffe17 ldw r2,-8(fp) + 10168cc: 10800017 ldw r2,0(r2) + 10168d0: 11000304 addi r4,r2,12 + 10168d4: e0bffe17 ldw r2,-8(fp) + 10168d8: 10800117 ldw r2,4(r2) + 10168dc: 1007883a mov r3,r2 + 10168e0: 2005883a mov r2,r4 + 10168e4: 10c00035 stwio r3,0(r2) + } +} + 10168e8: e037883a mov sp,fp + 10168ec: dfc00117 ldw ra,4(sp) + 10168f0: df000017 ldw fp,0(sp) + 10168f4: dec00204 addi sp,sp,8 + 10168f8: f800283a ret + +010168fc : + * buffer to the device, and sets the apropriate flags to indicate that + * there is data ready to be processed. + */ +static void +altera_avalon_uart_txirq(altera_avalon_uart_state* sp, alt_u32 status) +{ + 10168fc: defffa04 addi sp,sp,-24 + 1016900: dfc00515 stw ra,20(sp) + 1016904: df000415 stw fp,16(sp) + 1016908: df000404 addi fp,sp,16 + 101690c: e13ffe15 stw r4,-8(fp) + 1016910: e17fff15 stw r5,-4(fp) + /* Transfer data if there is some ready to be transfered */ + + if (sp->tx_start != sp->tx_end) + 1016914: e0bffe17 ldw r2,-8(fp) + 1016918: 10c00417 ldw r3,16(r2) + 101691c: e0bffe17 ldw r2,-8(fp) + 1016920: 10800517 ldw r2,20(r2) + 1016924: 18804d26 beq r3,r2,1016a5c + /* + * If the device is using flow control (i.e. RTS/CTS), then the + * transmitter is required to throttle if CTS is high. + */ + + if (!(sp->flags & ALT_AVALON_UART_FC) || + 1016928: e0bffe17 ldw r2,-8(fp) + 101692c: 10800617 ldw r2,24(r2) + 1016930: 1080008c andi r2,r2,2 + 1016934: 1005003a cmpeq r2,r2,zero + 1016938: 1000041e bne r2,zero,101694c + 101693c: e0bfff17 ldw r2,-4(fp) + 1016940: 1082000c andi r2,r2,2048 + 1016944: 1005003a cmpeq r2,r2,zero + 1016948: 1000351e bne r2,zero,1016a20 + * In a multi-threaded environment, set the write event flag to indicate + * that there is space in the circular buffer. This is only done if the + * buffer was previously empty. + */ + + if (sp->tx_start == ((sp->tx_end + 1) & ALT_AVALON_UART_BUF_MSK)) + 101694c: e0bffe17 ldw r2,-8(fp) + 1016950: 10c00417 ldw r3,16(r2) + 1016954: e0bffe17 ldw r2,-8(fp) + 1016958: 10800517 ldw r2,20(r2) + 101695c: 10800044 addi r2,r2,1 + 1016960: 10800fcc andi r2,r2,63 + 1016964: 1880121e bne r3,r2,10169b0 + { + ALT_FLAG_POST (sp->events, + 1016968: e0bffe17 ldw r2,-8(fp) + 101696c: 10800717 ldw r2,28(r2) + 1016970: e0bffc15 stw r2,-16(fp) + 1016974: 00800084 movi r2,2 + 1016978: e0bffd0d sth r2,-12(fp) + 101697c: 00800044 movi r2,1 + 1016980: e0bffd85 stb r2,-10(fp) + OS_FLAGS flags, + INT8U opt) +{ + INT8U err; + + if (OSRunning) + 1016984: 008040b4 movhi r2,258 + 1016988: 10b31044 addi r2,r2,-13247 + 101698c: 10800003 ldbu r2,0(r2) + 1016990: 10803fcc andi r2,r2,255 + 1016994: 1005003a cmpeq r2,r2,zero + 1016998: 1000051e bne r2,zero,10169b0 + { + OSFlagPost (group, flags, opt, &err); + 101699c: e17ffd0b ldhu r5,-12(fp) + 10169a0: e1bffd83 ldbu r6,-10(fp) + 10169a4: e1fffdc4 addi r7,fp,-9 + 10169a8: e13ffc17 ldw r4,-16(fp) + 10169ac: 10105880 call 1010588 + OS_FLAG_SET); + } + + /* Write the data to the device */ + + IOWR_ALTERA_AVALON_UART_TXDATA(sp->base, sp->tx_buf[sp->tx_start]); + 10169b0: e0bffe17 ldw r2,-8(fp) + 10169b4: 10800017 ldw r2,0(r2) + 10169b8: 11000104 addi r4,r2,4 + 10169bc: e0bffe17 ldw r2,-8(fp) + 10169c0: 10c00417 ldw r3,16(r2) + 10169c4: e0bffe17 ldw r2,-8(fp) + 10169c8: 1885883a add r2,r3,r2 + 10169cc: 10801a04 addi r2,r2,104 + 10169d0: 10800003 ldbu r2,0(r2) + 10169d4: 10c03fcc andi r3,r2,255 + 10169d8: 2005883a mov r2,r4 + 10169dc: 10c00035 stwio r3,0(r2) + + sp->tx_start = (++sp->tx_start) & ALT_AVALON_UART_BUF_MSK; + 10169e0: e0bffe17 ldw r2,-8(fp) + 10169e4: 10800417 ldw r2,16(r2) + 10169e8: 10c00044 addi r3,r2,1 + 10169ec: e0bffe17 ldw r2,-8(fp) + 10169f0: 10c00415 stw r3,16(r2) + 10169f4: e0bffe17 ldw r2,-8(fp) + 10169f8: 10800417 ldw r2,16(r2) + 10169fc: 10c00fcc andi r3,r2,63 + 1016a00: e0bffe17 ldw r2,-8(fp) + 1016a04: 10c00415 stw r3,16(r2) + /* + * In case the tranmit interrupt had previously been disabled by + * detecting a low value on CTS, it is reenabled here. + */ + + sp->ctrl |= ALTERA_AVALON_UART_CONTROL_TRDY_MSK; + 1016a08: e0bffe17 ldw r2,-8(fp) + 1016a0c: 10800117 ldw r2,4(r2) + 1016a10: 10c01014 ori r3,r2,64 + 1016a14: e0bffe17 ldw r2,-8(fp) + 1016a18: 10c00115 stw r3,4(r2) + /* + * If the device is using flow control (i.e. RTS/CTS), then the + * transmitter is required to throttle if CTS is high. + */ + + if (!(sp->flags & ALT_AVALON_UART_FC) || + 1016a1c: 00000f06 br 1016a5c + * the last write to the status register. To avoid this resulting in + * deadlock, it's necessary to re-check the status register here + * before throttling. + */ + + status = IORD_ALTERA_AVALON_UART_STATUS(sp->base); + 1016a20: e0bffe17 ldw r2,-8(fp) + 1016a24: 10800017 ldw r2,0(r2) + 1016a28: 10800204 addi r2,r2,8 + 1016a2c: 10800037 ldwio r2,0(r2) + 1016a30: e0bfff15 stw r2,-4(fp) + + if (!(status & ALTERA_AVALON_UART_STATUS_CTS_MSK)) + 1016a34: e0bfff17 ldw r2,-4(fp) + 1016a38: 1082000c andi r2,r2,2048 + 1016a3c: 1004c03a cmpne r2,r2,zero + 1016a40: 1000061e bne r2,zero,1016a5c + { + sp->ctrl &= ~ALTERA_AVALON_UART_CONTROL_TRDY_MSK; + 1016a44: e0bffe17 ldw r2,-8(fp) + 1016a48: 10c00117 ldw r3,4(r2) + 1016a4c: 00bfefc4 movi r2,-65 + 1016a50: 1886703a and r3,r3,r2 + 1016a54: e0bffe17 ldw r2,-8(fp) + 1016a58: 10c00115 stw r3,4(r2) + /* + * If the circular buffer is empty, disable the interrupt. This will be + * re-enabled when new data is placed in the buffer. + */ + + if (sp->tx_start == sp->tx_end) + 1016a5c: e0bffe17 ldw r2,-8(fp) + 1016a60: 10c00417 ldw r3,16(r2) + 1016a64: e0bffe17 ldw r2,-8(fp) + 1016a68: 10800517 ldw r2,20(r2) + 1016a6c: 1880061e bne r3,r2,1016a88 + { + sp->ctrl &= ~(ALTERA_AVALON_UART_CONTROL_TRDY_MSK | + 1016a70: e0bffe17 ldw r2,-8(fp) + 1016a74: 10c00117 ldw r3,4(r2) + 1016a78: 00beefc4 movi r2,-1089 + 1016a7c: 1886703a and r3,r3,r2 + 1016a80: e0bffe17 ldw r2,-8(fp) + 1016a84: 10c00115 stw r3,4(r2) + ALTERA_AVALON_UART_CONTROL_DCTS_MSK); + } + + IOWR_ALTERA_AVALON_UART_CONTROL(sp->base, sp->ctrl); + 1016a88: e0bffe17 ldw r2,-8(fp) + 1016a8c: 10800017 ldw r2,0(r2) + 1016a90: 11000304 addi r4,r2,12 + 1016a94: e0bffe17 ldw r2,-8(fp) + 1016a98: 10800117 ldw r2,4(r2) + 1016a9c: 1007883a mov r3,r2 + 1016aa0: 2005883a mov r2,r4 + 1016aa4: 10c00035 stwio r3,0(r2) +} + 1016aa8: e037883a mov sp,fp + 1016aac: dfc00117 ldw ra,4(sp) + 1016ab0: df000017 ldw fp,0(sp) + 1016ab4: dec00204 addi sp,sp,8 + 1016ab8: f800283a ret + +01016abc : + * The close routine is not implemented for the small driver; instead it will + * map to null. This is because the small driver simply waits while characters + * are transmitted; there is no interrupt-serviced buffer to empty + */ +int altera_avalon_uart_close(altera_avalon_uart_state* sp, int flags) +{ + 1016abc: defffc04 addi sp,sp,-16 + 1016ac0: df000315 stw fp,12(sp) + 1016ac4: df000304 addi fp,sp,12 + 1016ac8: e13ffd15 stw r4,-12(fp) + 1016acc: e17ffe15 stw r5,-8(fp) + /* + * Wait for all transmit data to be emptied by the UART ISR. + */ + while (sp->tx_start != sp->tx_end) { + 1016ad0: 00000706 br 1016af0 + if (flags & O_NONBLOCK) { + 1016ad4: e0bffe17 ldw r2,-8(fp) + 1016ad8: 1090000c andi r2,r2,16384 + 1016adc: 1005003a cmpeq r2,r2,zero + 1016ae0: 1000031e bne r2,zero,1016af0 + return -EWOULDBLOCK; + 1016ae4: 00bffd44 movi r2,-11 + 1016ae8: e0bfff15 stw r2,-4(fp) + 1016aec: 00000606 br 1016b08 +int altera_avalon_uart_close(altera_avalon_uart_state* sp, int flags) +{ + /* + * Wait for all transmit data to be emptied by the UART ISR. + */ + while (sp->tx_start != sp->tx_end) { + 1016af0: e0bffd17 ldw r2,-12(fp) + 1016af4: 10c00417 ldw r3,16(r2) + 1016af8: e0bffd17 ldw r2,-12(fp) + 1016afc: 10800517 ldw r2,20(r2) + 1016b00: 18bff41e bne r3,r2,1016ad4 + if (flags & O_NONBLOCK) { + return -EWOULDBLOCK; + } + } + + return 0; + 1016b04: e03fff15 stw zero,-4(fp) + 1016b08: e0bfff17 ldw r2,-4(fp) +} + 1016b0c: e037883a mov sp,fp + 1016b10: df000017 ldw fp,0(sp) + 1016b14: dec00104 addi sp,sp,4 + 1016b18: f800283a ret + +01016b1c : + */ + +int +altera_avalon_uart_read(altera_avalon_uart_state* sp, char* ptr, int len, + int flags) +{ + 1016b1c: deffe904 addi sp,sp,-92 + 1016b20: dfc01615 stw ra,88(sp) + 1016b24: df001515 stw fp,84(sp) + 1016b28: df001504 addi fp,sp,84 + 1016b2c: e13ffb15 stw r4,-20(fp) + 1016b30: e17ffc15 stw r5,-16(fp) + 1016b34: e1bffd15 stw r6,-12(fp) + 1016b38: e1fffe15 stw r7,-8(fp) + alt_irq_context context; + int block; + alt_u32 next; + alt_u8 read_would_block = 0; + 1016b3c: e03ff605 stb zero,-40(fp) + int count = 0; + 1016b40: e03ff515 stw zero,-44(fp) + /* + * Construct a flag to indicate whether the device is being accessed in + * blocking or non-blocking mode. + */ + + block = !(flags & O_NONBLOCK); + 1016b44: e0bffe17 ldw r2,-8(fp) + 1016b48: 1090000c andi r2,r2,16384 + 1016b4c: 1005003a cmpeq r2,r2,zero + 1016b50: e0bff815 stw r2,-32(fp) + /* + * When running in a multi threaded environment, obtain the "read_lock" + * semaphore. This ensures that reading from the device is thread-safe. + */ + + ALT_SEM_PEND (sp->read_lock, 0); + 1016b54: e0bffb17 ldw r2,-20(fp) + 1016b58: 10800817 ldw r2,32(r2) + 1016b5c: e0bff315 stw r2,-52(fp) + 1016b60: e03ff40d sth zero,-48(fp) + +static ALT_INLINE int ALT_ALWAYS_INLINE alt_sem_pend (OS_EVENT* sem, + INT16U timeout) +{ + INT8U err; + OSSemPend (sem, timeout, &err); + 1016b64: e17ff40b ldhu r5,-48(fp) + 1016b68: e1bffa04 addi r6,fp,-24 + 1016b6c: e13ff317 ldw r4,-52(fp) + 1016b70: 1012e180 call 1012e18 + /* + * Calculate which slot in the circular buffer is the next one to read + * data from. + */ + + next = (sp->rx_start + 1) & ALT_AVALON_UART_BUF_MSK; + 1016b74: e0bffb17 ldw r2,-20(fp) + 1016b78: 10800217 ldw r2,8(r2) + 1016b7c: 10800044 addi r2,r2,1 + 1016b80: 10800fcc andi r2,r2,63 + 1016b84: e0bff715 stw r2,-36(fp) + /* + * Read the required amount of data, until the circular buffer runs + * empty + */ + + while ((count < len) && (sp->rx_start != sp->rx_end)) + 1016b88: 00001906 br 1016bf0 + { + count++; + 1016b8c: e0bff517 ldw r2,-44(fp) + 1016b90: 10800044 addi r2,r2,1 + 1016b94: e0bff515 stw r2,-44(fp) + *ptr++ = sp->rx_buf[sp->rx_start]; + 1016b98: e0bffb17 ldw r2,-20(fp) + 1016b9c: 10c00217 ldw r3,8(r2) + 1016ba0: e0bffb17 ldw r2,-20(fp) + 1016ba4: 1885883a add r2,r3,r2 + 1016ba8: 10800a04 addi r2,r2,40 + 1016bac: 10800003 ldbu r2,0(r2) + 1016bb0: 1007883a mov r3,r2 + 1016bb4: e0bffc17 ldw r2,-16(fp) + 1016bb8: 10c00005 stb r3,0(r2) + 1016bbc: e0bffc17 ldw r2,-16(fp) + 1016bc0: 10800044 addi r2,r2,1 + 1016bc4: e0bffc15 stw r2,-16(fp) + + sp->rx_start = (++sp->rx_start) & ALT_AVALON_UART_BUF_MSK; + 1016bc8: e0bffb17 ldw r2,-20(fp) + 1016bcc: 10800217 ldw r2,8(r2) + 1016bd0: 10c00044 addi r3,r2,1 + 1016bd4: e0bffb17 ldw r2,-20(fp) + 1016bd8: 10c00215 stw r3,8(r2) + 1016bdc: e0bffb17 ldw r2,-20(fp) + 1016be0: 10800217 ldw r2,8(r2) + 1016be4: 10c00fcc andi r3,r2,63 + 1016be8: e0bffb17 ldw r2,-20(fp) + 1016bec: 10c00215 stw r3,8(r2) + /* + * Read the required amount of data, until the circular buffer runs + * empty + */ + + while ((count < len) && (sp->rx_start != sp->rx_end)) + 1016bf0: e0fff517 ldw r3,-44(fp) + 1016bf4: e0bffd17 ldw r2,-12(fp) + 1016bf8: 1880050e bge r3,r2,1016c10 + 1016bfc: e0bffb17 ldw r2,-20(fp) + 1016c00: 10c00217 ldw r3,8(r2) + 1016c04: e0bffb17 ldw r2,-20(fp) + 1016c08: 10800317 ldw r2,12(r2) + 1016c0c: 18bfdf1e bne r3,r2,1016b8c + /* + * If no data has been transferred, the circular buffer is empty, and + * this is not a non-blocking access, block waiting for data to arrive. + */ + + if (!count && (sp->rx_start == sp->rx_end)) + 1016c10: e0bff517 ldw r2,-44(fp) + 1016c14: 1004c03a cmpne r2,r2,zero + 1016c18: 10003c1e bne r2,zero,1016d0c + 1016c1c: e0bffb17 ldw r2,-20(fp) + 1016c20: 10c00217 ldw r3,8(r2) + 1016c24: e0bffb17 ldw r2,-20(fp) + 1016c28: 10800317 ldw r2,12(r2) + 1016c2c: 1880371e bne r3,r2,1016d0c + { + if (!block) + 1016c30: e0bff817 ldw r2,-32(fp) + 1016c34: 1004c03a cmpne r2,r2,zero + 1016c38: 1000061e bne r2,zero,1016c54 + { + /* Set errno to indicate the reason we're not returning any data */ + + ALT_ERRNO = EWOULDBLOCK; + 1016c3c: 1016dcc0 call 1016dcc + 1016c40: 00c002c4 movi r3,11 + 1016c44: 10c00015 stw r3,0(r2) + read_would_block = 1; + 1016c48: 00800044 movi r2,1 + 1016c4c: e0bff605 stb r2,-40(fp) + break; + 1016c50: 00003406 br 1016d24 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1016c54: 0005303a rdctl r2,status + 1016c58: e0bff215 stw r2,-56(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1016c5c: e0fff217 ldw r3,-56(fp) + 1016c60: 00bfff84 movi r2,-2 + 1016c64: 1884703a and r2,r3,r2 + 1016c68: 1001703a wrctl status,r2 + + return context; + 1016c6c: e0bff217 ldw r2,-56(fp) + { + /* Block waiting for some data to arrive */ + + /* First, ensure read interrupts are enabled to avoid deadlock */ + + context = alt_irq_disable_all (); + 1016c70: e0bff915 stw r2,-28(fp) + sp->ctrl |= ALTERA_AVALON_UART_CONTROL_RRDY_MSK; + 1016c74: e0bffb17 ldw r2,-20(fp) + 1016c78: 10800117 ldw r2,4(r2) + 1016c7c: 10c02014 ori r3,r2,128 + 1016c80: e0bffb17 ldw r2,-20(fp) + 1016c84: 10c00115 stw r3,4(r2) + IOWR_ALTERA_AVALON_UART_CONTROL(sp->base, sp->ctrl); + 1016c88: e0bffb17 ldw r2,-20(fp) + 1016c8c: 10800017 ldw r2,0(r2) + 1016c90: 11000304 addi r4,r2,12 + 1016c94: e0bffb17 ldw r2,-20(fp) + 1016c98: 10800117 ldw r2,4(r2) + 1016c9c: 1007883a mov r3,r2 + 1016ca0: 2005883a mov r2,r4 + 1016ca4: 10c00035 stwio r3,0(r2) + 1016ca8: e0bff917 ldw r2,-28(fp) + 1016cac: e0bff115 stw r2,-60(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1016cb0: e0bff117 ldw r2,-60(fp) + 1016cb4: 1001703a wrctl status,r2 + * flag set in the interrupt service routine. This avoids wasting CPU + * cycles waiting in this thread, when we could be doing something more + * profitable elsewhere. + */ + + ALT_FLAG_PEND (sp->events, + 1016cb8: e0bffb17 ldw r2,-20(fp) + 1016cbc: 10800717 ldw r2,28(r2) + 1016cc0: e0bfee15 stw r2,-72(fp) + 1016cc4: 00800044 movi r2,1 + 1016cc8: e0bfef0d sth r2,-68(fp) + 1016ccc: 00bfe0c4 movi r2,-125 + 1016cd0: e0bfef85 stb r2,-66(fp) + 1016cd4: e03ff00d sth zero,-64(fp) + OS_FLAGS flags, + INT8U wait_type, + INT16U timeout) +{ + INT8U err; + if (OSRunning) + 1016cd8: 008040b4 movhi r2,258 + 1016cdc: 10b31044 addi r2,r2,-13247 + 1016ce0: 10800003 ldbu r2,0(r2) + 1016ce4: 10803fcc andi r2,r2,255 + 1016ce8: 1005003a cmpeq r2,r2,zero + 1016cec: 1000071e bne r2,zero,1016d0c + { + OSFlagPend (group, flags, wait_type, timeout, &err); + 1016cf0: e17fef0b ldhu r5,-68(fp) + 1016cf4: e1bfef83 ldbu r6,-66(fp) + 1016cf8: e1fff00b ldhu r7,-64(fp) + 1016cfc: e0bffa44 addi r2,fp,-23 + 1016d00: d8800015 stw r2,0(sp) + 1016d04: e13fee17 ldw r4,-72(fp) + 1016d08: 100fedc0 call 100fedc + OS_FLAG_WAIT_SET_ANY + OS_FLAG_CONSUME, + 0); + } + } + } + while (!count && len); + 1016d0c: e0bff517 ldw r2,-44(fp) + 1016d10: 1004c03a cmpne r2,r2,zero + 1016d14: 1000031e bne r2,zero,1016d24 + 1016d18: e0bffd17 ldw r2,-12(fp) + 1016d1c: 1004c03a cmpne r2,r2,zero + 1016d20: 103fb31e bne r2,zero,1016bf0 + /* + * Now that access to the circular buffer is complete, release the read + * semaphore so that other threads can access the buffer. + */ + + ALT_SEM_POST (sp->read_lock); + 1016d24: e0bffb17 ldw r2,-20(fp) + 1016d28: 11000817 ldw r4,32(r2) + 1016d2c: 10132100 call 1013210 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1016d30: 0005303a rdctl r2,status + 1016d34: e0bfed15 stw r2,-76(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1016d38: e0ffed17 ldw r3,-76(fp) + 1016d3c: 00bfff84 movi r2,-2 + 1016d40: 1884703a and r2,r3,r2 + 1016d44: 1001703a wrctl status,r2 + + return context; + 1016d48: e0bfed17 ldw r2,-76(fp) + /* + * Ensure that interrupts are enabled, so that the circular buffer can + * re-fill. + */ + + context = alt_irq_disable_all (); + 1016d4c: e0bff915 stw r2,-28(fp) + sp->ctrl |= ALTERA_AVALON_UART_CONTROL_RRDY_MSK; + 1016d50: e0bffb17 ldw r2,-20(fp) + 1016d54: 10800117 ldw r2,4(r2) + 1016d58: 10c02014 ori r3,r2,128 + 1016d5c: e0bffb17 ldw r2,-20(fp) + 1016d60: 10c00115 stw r3,4(r2) + IOWR_ALTERA_AVALON_UART_CONTROL(sp->base, sp->ctrl); + 1016d64: e0bffb17 ldw r2,-20(fp) + 1016d68: 10800017 ldw r2,0(r2) + 1016d6c: 11000304 addi r4,r2,12 + 1016d70: e0bffb17 ldw r2,-20(fp) + 1016d74: 10800117 ldw r2,4(r2) + 1016d78: 1007883a mov r3,r2 + 1016d7c: 2005883a mov r2,r4 + 1016d80: 10c00035 stwio r3,0(r2) + 1016d84: e0bff917 ldw r2,-28(fp) + 1016d88: e0bfec15 stw r2,-80(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1016d8c: e0bfec17 ldw r2,-80(fp) + 1016d90: 1001703a wrctl status,r2 + alt_irq_enable_all (context); + + /* Return the number of bytes read */ + if(read_would_block) { + 1016d94: e0bff603 ldbu r2,-40(fp) + 1016d98: 1005003a cmpeq r2,r2,zero + 1016d9c: 1000031e bne r2,zero,1016dac + return ~EWOULDBLOCK; + 1016da0: 00bffd04 movi r2,-12 + 1016da4: e0bfff15 stw r2,-4(fp) + 1016da8: 00000206 br 1016db4 + } + else { + return count; + 1016dac: e0bff517 ldw r2,-44(fp) + 1016db0: e0bfff15 stw r2,-4(fp) + 1016db4: e0bfff17 ldw r2,-4(fp) + } +} + 1016db8: e037883a mov sp,fp + 1016dbc: dfc00117 ldw ra,4(sp) + 1016dc0: df000017 ldw fp,0(sp) + 1016dc4: dec00204 addi sp,sp,8 + 1016dc8: f800283a ret + +01016dcc : +#undef errno + +extern int errno; + +static ALT_INLINE int* alt_get_errno(void) +{ + 1016dcc: defffd04 addi sp,sp,-12 + 1016dd0: dfc00215 stw ra,8(sp) + 1016dd4: df000115 stw fp,4(sp) + 1016dd8: df000104 addi fp,sp,4 + return ((alt_errno) ? alt_errno() : &errno); + 1016ddc: 008040b4 movhi r2,258 + 1016de0: 10aba104 addi r2,r2,-20860 + 1016de4: 10800017 ldw r2,0(r2) + 1016de8: 1005003a cmpeq r2,r2,zero + 1016dec: 1000061e bne r2,zero,1016e08 + 1016df0: 008040b4 movhi r2,258 + 1016df4: 10aba104 addi r2,r2,-20860 + 1016df8: 10800017 ldw r2,0(r2) + 1016dfc: 103ee83a callr r2 + 1016e00: e0bfff15 stw r2,-4(fp) + 1016e04: 00000306 br 1016e14 + 1016e08: 008040b4 movhi r2,258 + 1016e0c: 10b30404 addi r2,r2,-13296 + 1016e10: e0bfff15 stw r2,-4(fp) + 1016e14: e0bfff17 ldw r2,-4(fp) +} + 1016e18: e037883a mov sp,fp + 1016e1c: dfc00117 ldw ra,4(sp) + 1016e20: df000017 ldw fp,0(sp) + 1016e24: dec00204 addi sp,sp,8 + 1016e28: f800283a ret + +01016e2c : + */ + +int +altera_avalon_uart_write(altera_avalon_uart_state* sp, const char* ptr, int len, + int flags) +{ + 1016e2c: deffeb04 addi sp,sp,-84 + 1016e30: dfc01415 stw ra,80(sp) + 1016e34: df001315 stw fp,76(sp) + 1016e38: df001304 addi fp,sp,76 + 1016e3c: e13ffc15 stw r4,-16(fp) + 1016e40: e17ffd15 stw r5,-12(fp) + 1016e44: e1bffe15 stw r6,-8(fp) + 1016e48: e1ffff15 stw r7,-4(fp) + alt_irq_context context; + int no_block; + alt_u32 next; + int count = len; + 1016e4c: e0bffe17 ldw r2,-8(fp) + 1016e50: e0bff715 stw r2,-36(fp) + /* + * Construct a flag to indicate whether the device is being accessed in + * blocking or non-blocking mode. + */ + + no_block = (flags & O_NONBLOCK); + 1016e54: e0bfff17 ldw r2,-4(fp) + 1016e58: 1090000c andi r2,r2,16384 + 1016e5c: e0bff915 stw r2,-28(fp) + /* + * When running in a multi threaded environment, obtain the "write_lock" + * semaphore. This ensures that writing to the device is thread-safe. + */ + + ALT_SEM_PEND (sp->write_lock, 0); + 1016e60: e0bffc17 ldw r2,-16(fp) + 1016e64: 10800917 ldw r2,36(r2) + 1016e68: e0bff515 stw r2,-44(fp) + 1016e6c: e03ff60d sth zero,-40(fp) + 1016e70: e17ff60b ldhu r5,-40(fp) + 1016e74: e1bffb04 addi r6,fp,-20 + 1016e78: e13ff517 ldw r4,-44(fp) + 1016e7c: 1012e180 call 1012e18 + * Loop transferring data from the input buffer to the transmit circular + * buffer. The loop is terminated once all the data has been transferred, + * or, (if in non-blocking mode) the buffer becomes full. + */ + + while (count) + 1016e80: 00005506 br 1016fd8 + { + /* Determine the next slot in the buffer to access */ + + next = (sp->tx_end + 1) & ALT_AVALON_UART_BUF_MSK; + 1016e84: e0bffc17 ldw r2,-16(fp) + 1016e88: 10800517 ldw r2,20(r2) + 1016e8c: 10800044 addi r2,r2,1 + 1016e90: 10800fcc andi r2,r2,63 + 1016e94: e0bff815 stw r2,-32(fp) + + /* block waiting for space if necessary */ + + if (next == sp->tx_start) + 1016e98: e0bffc17 ldw r2,-16(fp) + 1016e9c: 10c00417 ldw r3,16(r2) + 1016ea0: e0bff817 ldw r2,-32(fp) + 1016ea4: 18803a1e bne r3,r2,1016f90 + { + if (no_block) + 1016ea8: e0bff917 ldw r2,-28(fp) + 1016eac: 1005003a cmpeq r2,r2,zero + 1016eb0: 1000051e bne r2,zero,1016ec8 + { + /* Set errno to indicate why this function returned early */ + + ALT_ERRNO = EWOULDBLOCK; + 1016eb4: 10170740 call 1017074 + 1016eb8: 1007883a mov r3,r2 + 1016ebc: 008002c4 movi r2,11 + 1016ec0: 18800015 stw r2,0(r3) + break; + 1016ec4: 00004706 br 1016fe4 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1016ec8: 0005303a rdctl r2,status + 1016ecc: e0bff415 stw r2,-48(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1016ed0: e0fff417 ldw r3,-48(fp) + 1016ed4: 00bfff84 movi r2,-2 + 1016ed8: 1884703a and r2,r3,r2 + 1016edc: 1001703a wrctl status,r2 + + return context; + 1016ee0: e0bff417 ldw r2,-48(fp) + { + /* Block waiting for space in the circular buffer */ + + /* First, ensure transmit interrupts are enabled to avoid deadlock */ + + context = alt_irq_disable_all (); + 1016ee4: e0bffa15 stw r2,-24(fp) + sp->ctrl |= (ALTERA_AVALON_UART_CONTROL_TRDY_MSK | + 1016ee8: e0bffc17 ldw r2,-16(fp) + 1016eec: 10800117 ldw r2,4(r2) + 1016ef0: 10c11014 ori r3,r2,1088 + 1016ef4: e0bffc17 ldw r2,-16(fp) + 1016ef8: 10c00115 stw r3,4(r2) + ALTERA_AVALON_UART_CONTROL_DCTS_MSK); + IOWR_ALTERA_AVALON_UART_CONTROL(sp->base, sp->ctrl); + 1016efc: e0bffc17 ldw r2,-16(fp) + 1016f00: 10800017 ldw r2,0(r2) + 1016f04: 11000304 addi r4,r2,12 + 1016f08: e0bffc17 ldw r2,-16(fp) + 1016f0c: 10800117 ldw r2,4(r2) + 1016f10: 1007883a mov r3,r2 + 1016f14: 2005883a mov r2,r4 + 1016f18: 10c00035 stwio r3,0(r2) + 1016f1c: e0bffa17 ldw r2,-24(fp) + 1016f20: e0bff315 stw r2,-52(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1016f24: e0bff317 ldw r2,-52(fp) + 1016f28: 1001703a wrctl status,r2 + * flag set in the interrupt service routine. This avoids wasting CPU + * cycles waiting in this thread, when we could be doing something + * more profitable elsewhere. + */ + + ALT_FLAG_PEND (sp->events, + 1016f2c: e0bffc17 ldw r2,-16(fp) + 1016f30: 10800717 ldw r2,28(r2) + 1016f34: e0bff015 stw r2,-64(fp) + 1016f38: 00800084 movi r2,2 + 1016f3c: e0bff10d sth r2,-60(fp) + 1016f40: 00bfe0c4 movi r2,-125 + 1016f44: e0bff185 stb r2,-58(fp) + 1016f48: e03ff20d sth zero,-56(fp) + OS_FLAGS flags, + INT8U wait_type, + INT16U timeout) +{ + INT8U err; + if (OSRunning) + 1016f4c: 008040b4 movhi r2,258 + 1016f50: 10b31044 addi r2,r2,-13247 + 1016f54: 10800003 ldbu r2,0(r2) + 1016f58: 10803fcc andi r2,r2,255 + 1016f5c: 1005003a cmpeq r2,r2,zero + 1016f60: 1000071e bne r2,zero,1016f80 + { + OSFlagPend (group, flags, wait_type, timeout, &err); + 1016f64: e17ff10b ldhu r5,-60(fp) + 1016f68: e1bff183 ldbu r6,-58(fp) + 1016f6c: e1fff20b ldhu r7,-56(fp) + 1016f70: e0bffb44 addi r2,fp,-19 + 1016f74: d8800015 stw r2,0(sp) + 1016f78: e13ff017 ldw r4,-64(fp) + 1016f7c: 100fedc0 call 100fedc + ALT_UART_WRITE_RDY, + OS_FLAG_WAIT_SET_ANY + OS_FLAG_CONSUME, + 0); + } + while ((next == sp->tx_start)); + 1016f80: e0bffc17 ldw r2,-16(fp) + 1016f84: 10c00417 ldw r3,16(r2) + 1016f88: e0bff817 ldw r2,-32(fp) + 1016f8c: 18bfe726 beq r3,r2,1016f2c + } + } + + count--; + 1016f90: e0bff717 ldw r2,-36(fp) + 1016f94: 10bfffc4 addi r2,r2,-1 + 1016f98: e0bff715 stw r2,-36(fp) + + /* Add the next character to the transmit buffer */ + + sp->tx_buf[sp->tx_end] = *ptr++; + 1016f9c: e0bffc17 ldw r2,-16(fp) + 1016fa0: 10c00517 ldw r3,20(r2) + 1016fa4: e0bffd17 ldw r2,-12(fp) + 1016fa8: 10800003 ldbu r2,0(r2) + 1016fac: 1009883a mov r4,r2 + 1016fb0: e0bffc17 ldw r2,-16(fp) + 1016fb4: 1885883a add r2,r3,r2 + 1016fb8: 10801a04 addi r2,r2,104 + 1016fbc: 11000005 stb r4,0(r2) + 1016fc0: e0bffd17 ldw r2,-12(fp) + 1016fc4: 10800044 addi r2,r2,1 + 1016fc8: e0bffd15 stw r2,-12(fp) + sp->tx_end = next; + 1016fcc: e0fffc17 ldw r3,-16(fp) + 1016fd0: e0bff817 ldw r2,-32(fp) + 1016fd4: 18800515 stw r2,20(r3) + * Loop transferring data from the input buffer to the transmit circular + * buffer. The loop is terminated once all the data has been transferred, + * or, (if in non-blocking mode) the buffer becomes full. + */ + + while (count) + 1016fd8: e0bff717 ldw r2,-36(fp) + 1016fdc: 1004c03a cmpne r2,r2,zero + 1016fe0: 103fa81e bne r2,zero,1016e84 + /* + * Now that access to the circular buffer is complete, release the write + * semaphore so that other threads can access the buffer. + */ + + ALT_SEM_POST (sp->write_lock); + 1016fe4: e0bffc17 ldw r2,-16(fp) + 1016fe8: 11000917 ldw r4,36(r2) + 1016fec: 10132100 call 1013210 +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1016ff0: 0005303a rdctl r2,status + 1016ff4: e0bfef15 stw r2,-68(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1016ff8: e0ffef17 ldw r3,-68(fp) + 1016ffc: 00bfff84 movi r2,-2 + 1017000: 1884703a and r2,r3,r2 + 1017004: 1001703a wrctl status,r2 + + return context; + 1017008: e0bfef17 ldw r2,-68(fp) + /* + * Ensure that interrupts are enabled, so that the circular buffer can + * drain. + */ + + context = alt_irq_disable_all (); + 101700c: e0bffa15 stw r2,-24(fp) + sp->ctrl |= ALTERA_AVALON_UART_CONTROL_TRDY_MSK | + 1017010: e0bffc17 ldw r2,-16(fp) + 1017014: 10800117 ldw r2,4(r2) + 1017018: 10c11014 ori r3,r2,1088 + 101701c: e0bffc17 ldw r2,-16(fp) + 1017020: 10c00115 stw r3,4(r2) + ALTERA_AVALON_UART_CONTROL_DCTS_MSK; + IOWR_ALTERA_AVALON_UART_CONTROL(sp->base, sp->ctrl); + 1017024: e0bffc17 ldw r2,-16(fp) + 1017028: 10800017 ldw r2,0(r2) + 101702c: 11000304 addi r4,r2,12 + 1017030: e0bffc17 ldw r2,-16(fp) + 1017034: 10800117 ldw r2,4(r2) + 1017038: 1007883a mov r3,r2 + 101703c: 2005883a mov r2,r4 + 1017040: 10c00035 stwio r3,0(r2) + 1017044: e0bffa17 ldw r2,-24(fp) + 1017048: e0bfee15 stw r2,-72(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 101704c: e0bfee17 ldw r2,-72(fp) + 1017050: 1001703a wrctl status,r2 + alt_irq_enable_all (context); + + /* return the number of bytes written */ + + return (len - count); + 1017054: e0fffe17 ldw r3,-8(fp) + 1017058: e0bff717 ldw r2,-36(fp) + 101705c: 1885c83a sub r2,r3,r2 +} + 1017060: e037883a mov sp,fp + 1017064: dfc00117 ldw ra,4(sp) + 1017068: df000017 ldw fp,0(sp) + 101706c: dec00204 addi sp,sp,8 + 1017070: f800283a ret + +01017074 : +#undef errno + +extern int errno; + +static ALT_INLINE int* alt_get_errno(void) +{ + 1017074: defffd04 addi sp,sp,-12 + 1017078: dfc00215 stw ra,8(sp) + 101707c: df000115 stw fp,4(sp) + 1017080: df000104 addi fp,sp,4 + return ((alt_errno) ? alt_errno() : &errno); + 1017084: 008040b4 movhi r2,258 + 1017088: 10aba104 addi r2,r2,-20860 + 101708c: 10800017 ldw r2,0(r2) + 1017090: 1005003a cmpeq r2,r2,zero + 1017094: 1000061e bne r2,zero,10170b0 + 1017098: 008040b4 movhi r2,258 + 101709c: 10aba104 addi r2,r2,-20860 + 10170a0: 10800017 ldw r2,0(r2) + 10170a4: 103ee83a callr r2 + 10170a8: e0bfff15 stw r2,-4(fp) + 10170ac: 00000306 br 10170bc + 10170b0: 008040b4 movhi r2,258 + 10170b4: 10b30404 addi r2,r2,-13296 + 10170b8: e0bfff15 stw r2,-4(fp) + 10170bc: e0bfff17 ldw r2,-4(fp) +} + 10170c0: e037883a mov sp,fp + 10170c4: dfc00117 ldw ra,4(sp) + 10170c8: df000017 ldw fp,0(sp) + 10170cc: dec00204 addi sp,sp,8 + 10170d0: f800283a ret + +010170d4 : +#include "altera_up_avalon_rs232.h" +#include "altera_up_avalon_rs232_regs.h" + + +void alt_up_rs232_enable_read_interrupt(alt_up_rs232_dev *rs232) +{ + 10170d4: defffd04 addi sp,sp,-12 + 10170d8: df000215 stw fp,8(sp) + 10170dc: df000204 addi fp,sp,8 + 10170e0: e13fff15 stw r4,-4(fp) + alt_u32 ctrl_reg; + ctrl_reg = IORD_ALT_UP_RS232_CONTROL(rs232->base); + 10170e4: e0bfff17 ldw r2,-4(fp) + 10170e8: 10800a17 ldw r2,40(r2) + 10170ec: 10800104 addi r2,r2,4 + 10170f0: 10800037 ldwio r2,0(r2) + 10170f4: e0bffe15 stw r2,-8(fp) + // set RE to 1 while maintaining other bits the same + ctrl_reg |= ALT_UP_RS232_CONTROL_RE_MSK; + 10170f8: e0bffe17 ldw r2,-8(fp) + 10170fc: 10800054 ori r2,r2,1 + 1017100: e0bffe15 stw r2,-8(fp) + IOWR_ALT_UP_RS232_CONTROL(rs232->base, ctrl_reg); + 1017104: e0bfff17 ldw r2,-4(fp) + 1017108: 10800a17 ldw r2,40(r2) + 101710c: 10800104 addi r2,r2,4 + 1017110: e0fffe17 ldw r3,-8(fp) + 1017114: 10c00035 stwio r3,0(r2) +} + 1017118: e037883a mov sp,fp + 101711c: df000017 ldw fp,0(sp) + 1017120: dec00104 addi sp,sp,4 + 1017124: f800283a ret + +01017128 : + +void alt_up_rs232_disable_read_interrupt(alt_up_rs232_dev *rs232) +{ + 1017128: defffd04 addi sp,sp,-12 + 101712c: df000215 stw fp,8(sp) + 1017130: df000204 addi fp,sp,8 + 1017134: e13fff15 stw r4,-4(fp) + alt_u32 ctrl_reg; + ctrl_reg = IORD_ALT_UP_RS232_CONTROL(rs232->base); + 1017138: e0bfff17 ldw r2,-4(fp) + 101713c: 10800a17 ldw r2,40(r2) + 1017140: 10800104 addi r2,r2,4 + 1017144: 10800037 ldwio r2,0(r2) + 1017148: e0bffe15 stw r2,-8(fp) + // set RE to 0 while maintaining other bits the same + ctrl_reg &= ~ALT_UP_RS232_CONTROL_RE_MSK; + 101714c: e0fffe17 ldw r3,-8(fp) + 1017150: 00bfff84 movi r2,-2 + 1017154: 1884703a and r2,r3,r2 + 1017158: e0bffe15 stw r2,-8(fp) + IOWR_ALT_UP_RS232_CONTROL(rs232->base, ctrl_reg); + 101715c: e0bfff17 ldw r2,-4(fp) + 1017160: 10800a17 ldw r2,40(r2) + 1017164: 10800104 addi r2,r2,4 + 1017168: e0fffe17 ldw r3,-8(fp) + 101716c: 10c00035 stwio r3,0(r2) +} + 1017170: e037883a mov sp,fp + 1017174: df000017 ldw fp,0(sp) + 1017178: dec00104 addi sp,sp,4 + 101717c: f800283a ret + +01017180 : + +unsigned alt_up_rs232_get_used_space_in_read_FIFO(alt_up_rs232_dev *rs232) +{ + 1017180: defffd04 addi sp,sp,-12 + 1017184: df000215 stw fp,8(sp) + 1017188: df000204 addi fp,sp,8 + 101718c: e13fff15 stw r4,-4(fp) + alt_u16 ravail = 0; + 1017190: e03ffe0d sth zero,-8(fp) + // we can only read the 16 bits for RAVAIL --- a read of DATA will discard the data +// ravail = IORD_16DIRECT(IOADDR_ALT_UP_RS232_DATA(rs232->base), 2); + ravail = IORD_ALT_UP_RS232_RAVAIL(rs232->base); + 1017194: e0bfff17 ldw r2,-4(fp) + 1017198: 10800a17 ldw r2,40(r2) + 101719c: 10800084 addi r2,r2,2 + 10171a0: 1080002b ldhuio r2,0(r2) + 10171a4: e0bffe0d sth r2,-8(fp) +// return ravail; + return (ravail & ALT_UP_RS232_RAVAIL_MSK) >> ALT_UP_RS232_RAVAIL_OFST; + 10171a8: e0bffe0b ldhu r2,-8(fp) +} + 10171ac: e037883a mov sp,fp + 10171b0: df000017 ldw fp,0(sp) + 10171b4: dec00104 addi sp,sp,4 + 10171b8: f800283a ret + +010171bc : + +unsigned alt_up_rs232_get_available_space_in_write_FIFO(alt_up_rs232_dev *rs232) +{ + 10171bc: defffd04 addi sp,sp,-12 + 10171c0: df000215 stw fp,8(sp) + 10171c4: df000204 addi fp,sp,8 + 10171c8: e13fff15 stw r4,-4(fp) + alt_u32 ctrl_reg; + ctrl_reg = IORD_ALT_UP_RS232_CONTROL(rs232->base); + 10171cc: e0bfff17 ldw r2,-4(fp) + 10171d0: 10800a17 ldw r2,40(r2) + 10171d4: 10800104 addi r2,r2,4 + 10171d8: 10800037 ldwio r2,0(r2) + 10171dc: e0bffe15 stw r2,-8(fp) + return (ctrl_reg & ALT_UP_RS232_CONTROL_WSPACE_MSK) >> ALT_UP_RS232_CONTROL_WSPACE_OFST; + 10171e0: e0bffe17 ldw r2,-8(fp) + 10171e4: 10bfffec andhi r2,r2,65535 + 10171e8: 1004d43a srli r2,r2,16 +} + 10171ec: e037883a mov sp,fp + 10171f0: df000017 ldw fp,0(sp) + 10171f4: dec00104 addi sp,sp,4 + 10171f8: f800283a ret + +010171fc : + +int alt_up_rs232_check_parity(alt_u32 data_reg) +{ + 10171fc: defffc04 addi sp,sp,-16 + 1017200: df000315 stw fp,12(sp) + 1017204: df000304 addi fp,sp,12 + 1017208: e13ffe15 stw r4,-8(fp) + unsigned parity_error = (data_reg & ALT_UP_RS232_DATA_PE_MSK) >> ALT_UP_RS232_DATA_PE_OFST; + 101720c: e0bffe17 ldw r2,-8(fp) + 1017210: 1080800c andi r2,r2,512 + 1017214: 1004d27a srli r2,r2,9 + 1017218: e0bffd15 stw r2,-12(fp) + return (parity_error ? -1 : 0); + 101721c: e0bffd17 ldw r2,-12(fp) + 1017220: 1005003a cmpeq r2,r2,zero + 1017224: 1000031e bne r2,zero,1017234 + 1017228: 00bfffc4 movi r2,-1 + 101722c: e0bfff15 stw r2,-4(fp) + 1017230: 00000106 br 1017238 + 1017234: e03fff15 stw zero,-4(fp) + 1017238: e0bfff17 ldw r2,-4(fp) +} + 101723c: e037883a mov sp,fp + 1017240: df000017 ldw fp,0(sp) + 1017244: dec00104 addi sp,sp,4 + 1017248: f800283a ret + +0101724c : + +int alt_up_rs232_write_data(alt_up_rs232_dev *rs232, alt_u8 data) +{ + 101724c: defffc04 addi sp,sp,-16 + 1017250: df000315 stw fp,12(sp) + 1017254: df000304 addi fp,sp,12 + 1017258: e13ffe15 stw r4,-8(fp) + 101725c: e17fff05 stb r5,-4(fp) + alt_u32 data_reg; + data_reg = IORD_ALT_UP_RS232_DATA(rs232->base); + 1017260: e0bffe17 ldw r2,-8(fp) + 1017264: 10800a17 ldw r2,40(r2) + 1017268: 10800037 ldwio r2,0(r2) + 101726c: e0bffd15 stw r2,-12(fp) + + // we can write directly without thinking about other bit fields for this + // case ONLY, because only DATA field of the data register is writable + IOWR_ALT_UP_RS232_DATA(rs232->base, (data>>ALT_UP_RS232_DATA_DATA_OFST) & ALT_UP_RS232_DATA_DATA_MSK); + 1017270: e0bffe17 ldw r2,-8(fp) + 1017274: 10800a17 ldw r2,40(r2) + 1017278: e0ffff03 ldbu r3,-4(fp) + 101727c: 10c00035 stwio r3,0(r2) + return 0; + 1017280: 0005883a mov r2,zero +} + 1017284: e037883a mov sp,fp + 1017288: df000017 ldw fp,0(sp) + 101728c: dec00104 addi sp,sp,4 + 1017290: f800283a ret + +01017294 : + +int alt_up_rs232_read_data(alt_up_rs232_dev *rs232, alt_u8 *data, alt_u8 *parity_error) +{ + 1017294: defffa04 addi sp,sp,-24 + 1017298: dfc00515 stw ra,20(sp) + 101729c: df000415 stw fp,16(sp) + 10172a0: df000404 addi fp,sp,16 + 10172a4: e13ffd15 stw r4,-12(fp) + 10172a8: e17ffe15 stw r5,-8(fp) + 10172ac: e1bfff15 stw r6,-4(fp) + alt_u32 data_reg; + data_reg = IORD_ALT_UP_RS232_DATA(rs232->base); + 10172b0: e0bffd17 ldw r2,-12(fp) + 10172b4: 10800a17 ldw r2,40(r2) + 10172b8: 10800037 ldwio r2,0(r2) + 10172bc: e0bffc15 stw r2,-16(fp) + *data = (data_reg & ALT_UP_RS232_DATA_DATA_MSK) >> ALT_UP_RS232_DATA_DATA_OFST; + 10172c0: e0bffc17 ldw r2,-16(fp) + 10172c4: 1007883a mov r3,r2 + 10172c8: e0bffe17 ldw r2,-8(fp) + 10172cc: 10c00005 stb r3,0(r2) + *parity_error = alt_up_rs232_check_parity(data_reg); + 10172d0: e13ffc17 ldw r4,-16(fp) + 10172d4: 10171fc0 call 10171fc + 10172d8: 1007883a mov r3,r2 + 10172dc: e0bfff17 ldw r2,-4(fp) + 10172e0: 10c00005 stb r3,0(r2) + return (((data_reg & ALT_UP_RS232_DATA_RVALID_MSK) >> ALT_UP_RS232_DATA_RVALID_OFST) - 1); + 10172e4: e0bffc17 ldw r2,-16(fp) + 10172e8: 10a0000c andi r2,r2,32768 + 10172ec: 1004d3fa srli r2,r2,15 + 10172f0: 10bfffc4 addi r2,r2,-1 +} + 10172f4: e037883a mov sp,fp + 10172f8: dfc00117 ldw ra,4(sp) + 10172fc: df000017 ldw fp,0(sp) + 1017300: dec00204 addi sp,sp,8 + 1017304: f800283a ret + +01017308 : + +int alt_up_rs232_read_fd (alt_fd* fd, char* ptr, int len) +{ + 1017308: defff804 addi sp,sp,-32 + 101730c: dfc00715 stw ra,28(sp) + 1017310: df000615 stw fp,24(sp) + 1017314: df000604 addi fp,sp,24 + 1017318: e13ffd15 stw r4,-12(fp) + 101731c: e17ffe15 stw r5,-8(fp) + 1017320: e1bfff15 stw r6,-4(fp) + alt_up_rs232_dev *rs232 = (alt_up_rs232_dev*)fd->dev; + 1017324: e0bffd17 ldw r2,-12(fp) + 1017328: 10800017 ldw r2,0(r2) + 101732c: e0bffb15 stw r2,-20(fp) + int count = 0; + 1017330: e03ffa15 stw zero,-24(fp) + alt_u8 parity_error; + while(len--) + 1017334: 00000c06 br 1017368 + { + if (alt_up_rs232_read_data(rs232, ptr++, &parity_error)==0) + 1017338: e17ffe17 ldw r5,-8(fp) + 101733c: e0bffe17 ldw r2,-8(fp) + 1017340: 10800044 addi r2,r2,1 + 1017344: e0bffe15 stw r2,-8(fp) + 1017348: e1bffc04 addi r6,fp,-16 + 101734c: e13ffb17 ldw r4,-20(fp) + 1017350: 10172940 call 1017294 + 1017354: 1004c03a cmpne r2,r2,zero + 1017358: 1000091e bne r2,zero,1017380 + count++; + 101735c: e0bffa17 ldw r2,-24(fp) + 1017360: 10800044 addi r2,r2,1 + 1017364: e0bffa15 stw r2,-24(fp) +int alt_up_rs232_read_fd (alt_fd* fd, char* ptr, int len) +{ + alt_up_rs232_dev *rs232 = (alt_up_rs232_dev*)fd->dev; + int count = 0; + alt_u8 parity_error; + while(len--) + 1017368: e0bfff17 ldw r2,-4(fp) + 101736c: 10bfffc4 addi r2,r2,-1 + 1017370: e0bfff15 stw r2,-4(fp) + 1017374: e0bfff17 ldw r2,-4(fp) + 1017378: 10bfffd8 cmpnei r2,r2,-1 + 101737c: 103fee1e bne r2,zero,1017338 + if (alt_up_rs232_read_data(rs232, ptr++, &parity_error)==0) + count++; + else + break; + } + return count; + 1017380: e0bffa17 ldw r2,-24(fp) +} + 1017384: e037883a mov sp,fp + 1017388: dfc00117 ldw ra,4(sp) + 101738c: df000017 ldw fp,0(sp) + 1017390: dec00204 addi sp,sp,8 + 1017394: f800283a ret + +01017398 : + +int alt_up_rs232_write_fd (alt_fd* fd, const char* ptr, int len) +{ + 1017398: defff904 addi sp,sp,-28 + 101739c: dfc00615 stw ra,24(sp) + 10173a0: df000515 stw fp,20(sp) + 10173a4: df000504 addi fp,sp,20 + 10173a8: e13ffd15 stw r4,-12(fp) + 10173ac: e17ffe15 stw r5,-8(fp) + 10173b0: e1bfff15 stw r6,-4(fp) + alt_up_rs232_dev *rs232 = (alt_up_rs232_dev*)fd->dev; + 10173b4: e0bffd17 ldw r2,-12(fp) + 10173b8: 10800017 ldw r2,0(r2) + 10173bc: e0bffc15 stw r2,-16(fp) + int count = 0; + 10173c0: e03ffb15 stw zero,-20(fp) + while(len--) + 10173c4: 00000d06 br 10173fc + { + if (alt_up_rs232_write_data(rs232, *ptr)==0) + 10173c8: e0bffe17 ldw r2,-8(fp) + 10173cc: 10800003 ldbu r2,0(r2) + 10173d0: 11403fcc andi r5,r2,255 + 10173d4: e13ffc17 ldw r4,-16(fp) + 10173d8: 101724c0 call 101724c + 10173dc: 1004c03a cmpne r2,r2,zero + 10173e0: 10000c1e bne r2,zero,1017414 + { + count++; + 10173e4: e0bffb17 ldw r2,-20(fp) + 10173e8: 10800044 addi r2,r2,1 + 10173ec: e0bffb15 stw r2,-20(fp) + ptr++; + 10173f0: e0bffe17 ldw r2,-8(fp) + 10173f4: 10800044 addi r2,r2,1 + 10173f8: e0bffe15 stw r2,-8(fp) + +int alt_up_rs232_write_fd (alt_fd* fd, const char* ptr, int len) +{ + alt_up_rs232_dev *rs232 = (alt_up_rs232_dev*)fd->dev; + int count = 0; + while(len--) + 10173fc: e0bfff17 ldw r2,-4(fp) + 1017400: 10bfffc4 addi r2,r2,-1 + 1017404: e0bfff15 stw r2,-4(fp) + 1017408: e0bfff17 ldw r2,-4(fp) + 101740c: 10bfffd8 cmpnei r2,r2,-1 + 1017410: 103fed1e bne r2,zero,10173c8 + ptr++; + } + else + break; + } + return count; + 1017414: e0bffb17 ldw r2,-20(fp) +} + 1017418: e037883a mov sp,fp + 101741c: dfc00117 ldw ra,4(sp) + 1017420: df000017 ldw fp,0(sp) + 1017424: dec00204 addi sp,sp,8 + 1017428: f800283a ret + +0101742c : + +alt_up_rs232_dev* alt_up_rs232_open_dev(const char* name) +{ + 101742c: defffc04 addi sp,sp,-16 + 1017430: dfc00315 stw ra,12(sp) + 1017434: df000215 stw fp,8(sp) + 1017438: df000204 addi fp,sp,8 + 101743c: e13fff15 stw r4,-4(fp) + // find the device from the device list + // (see altera_hal/HAL/inc/priv/alt_file.h + // and altera_hal/HAL/src/alt_find_dev.c + // for details) + alt_up_rs232_dev *dev = (alt_up_rs232_dev*)alt_find_dev(name, &alt_dev_list); + 1017440: e13fff17 ldw r4,-4(fp) + 1017444: 014040b4 movhi r5,258 + 1017448: 296b9e04 addi r5,r5,-20872 + 101744c: 10177e00 call 10177e0 + 1017450: e0bffe15 stw r2,-8(fp) + + return dev; + 1017454: e0bffe17 ldw r2,-8(fp) +} + 1017458: e037883a mov sp,fp + 101745c: dfc00117 ldw ra,4(sp) + 1017460: df000017 ldw fp,0(sp) + 1017464: dec00204 addi sp,sp,8 + 1017468: f800283a ret + +0101746c : + */ + +int alt_alarm_start (alt_alarm* alarm, alt_u32 nticks, + alt_u32 (*callback) (void* context), + void* context) +{ + 101746c: defff404 addi sp,sp,-48 + 1017470: df000b15 stw fp,44(sp) + 1017474: df000b04 addi fp,sp,44 + 1017478: e13ffb15 stw r4,-20(fp) + 101747c: e17ffc15 stw r5,-16(fp) + 1017480: e1bffd15 stw r6,-12(fp) + 1017484: e1fffe15 stw r7,-8(fp) + alt_irq_context irq_context; + alt_u32 current_nticks = 0; + 1017488: e03ff915 stw zero,-28(fp) + * Obtain the system clock rate in ticks/s. + */ + +static ALT_INLINE alt_u32 ALT_ALWAYS_INLINE alt_ticks_per_second (void) +{ + return _alt_tick_rate; + 101748c: 008040b4 movhi r2,258 + 1017490: 10b32504 addi r2,r2,-13164 + 1017494: 10800017 ldw r2,0(r2) + + if (alt_ticks_per_second ()) + 1017498: 1005003a cmpeq r2,r2,zero + 101749c: 1000411e bne r2,zero,10175a4 + { + if (alarm) + 10174a0: e0bffb17 ldw r2,-20(fp) + 10174a4: 1005003a cmpeq r2,r2,zero + 10174a8: 10003b1e bne r2,zero,1017598 + { + alarm->callback = callback; + 10174ac: e0fffb17 ldw r3,-20(fp) + 10174b0: e0bffd17 ldw r2,-12(fp) + 10174b4: 18800315 stw r2,12(r3) + alarm->context = context; + 10174b8: e0fffb17 ldw r3,-20(fp) + 10174bc: e0bffe17 ldw r2,-8(fp) + 10174c0: 18800515 stw r2,20(r3) +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 10174c4: 0005303a rdctl r2,status + 10174c8: e0bff815 stw r2,-32(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 10174cc: e0fff817 ldw r3,-32(fp) + 10174d0: 00bfff84 movi r2,-2 + 10174d4: 1884703a and r2,r3,r2 + 10174d8: 1001703a wrctl status,r2 + + return context; + 10174dc: e0bff817 ldw r2,-32(fp) + + irq_context = alt_irq_disable_all (); + 10174e0: e0bffa15 stw r2,-24(fp) + * alt_nticks() returns the elapsed number of system clock ticks since reset. + */ + +static ALT_INLINE alt_u32 ALT_ALWAYS_INLINE alt_nticks (void) +{ + return _alt_nticks; + 10174e4: 008040b4 movhi r2,258 + 10174e8: 10b32604 addi r2,r2,-13160 + 10174ec: 10800017 ldw r2,0(r2) + + current_nticks = alt_nticks(); + 10174f0: e0bff915 stw r2,-28(fp) + + alarm->time = nticks + current_nticks + 1; + 10174f4: e0fffc17 ldw r3,-16(fp) + 10174f8: e0bff917 ldw r2,-28(fp) + 10174fc: 1885883a add r2,r3,r2 + 1017500: 10c00044 addi r3,r2,1 + 1017504: e0bffb17 ldw r2,-20(fp) + 1017508: 10c00215 stw r3,8(r2) + /* + * If the desired alarm time causes a roll-over, set the rollover + * flag. This will prevent the subsequent tick event from causing + * an alarm too early. + */ + if(alarm->time < current_nticks) + 101750c: e0bffb17 ldw r2,-20(fp) + 1017510: 10c00217 ldw r3,8(r2) + 1017514: e0bff917 ldw r2,-28(fp) + 1017518: 1880042e bgeu r3,r2,101752c + { + alarm->rollover = 1; + 101751c: e0fffb17 ldw r3,-20(fp) + 1017520: 00800044 movi r2,1 + 1017524: 18800405 stb r2,16(r3) + 1017528: 00000206 br 1017534 + } + else + { + alarm->rollover = 0; + 101752c: e0bffb17 ldw r2,-20(fp) + 1017530: 10000405 stb zero,16(r2) + } + + alt_llist_insert (&alt_alarm_list, &alarm->llist); + 1017534: e0fffb17 ldw r3,-20(fp) + 1017538: 008040b4 movhi r2,258 + 101753c: 10abc304 addi r2,r2,-20724 + 1017540: e0bff615 stw r2,-40(fp) + 1017544: e0fff715 stw r3,-36(fp) + */ + +static ALT_INLINE void ALT_ALWAYS_INLINE alt_llist_insert(alt_llist* list, + alt_llist* entry) +{ + entry->previous = list; + 1017548: e0fff717 ldw r3,-36(fp) + 101754c: e0bff617 ldw r2,-40(fp) + 1017550: 18800115 stw r2,4(r3) + entry->next = list->next; + 1017554: e0bff617 ldw r2,-40(fp) + 1017558: 10c00017 ldw r3,0(r2) + 101755c: e0bff717 ldw r2,-36(fp) + 1017560: 10c00015 stw r3,0(r2) + + list->next->previous = entry; + 1017564: e0bff617 ldw r2,-40(fp) + 1017568: 10c00017 ldw r3,0(r2) + 101756c: e0bff717 ldw r2,-36(fp) + 1017570: 18800115 stw r2,4(r3) + list->next = entry; + 1017574: e0fff617 ldw r3,-40(fp) + 1017578: e0bff717 ldw r2,-36(fp) + 101757c: 18800015 stw r2,0(r3) + 1017580: e0bffa17 ldw r2,-24(fp) + 1017584: e0bff515 stw r2,-44(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1017588: e0bff517 ldw r2,-44(fp) + 101758c: 1001703a wrctl status,r2 + alt_irq_enable_all (irq_context); + + return 0; + 1017590: e03fff15 stw zero,-4(fp) + 1017594: 00000506 br 10175ac + } + else + { + return -EINVAL; + 1017598: 00bffa84 movi r2,-22 + 101759c: e0bfff15 stw r2,-4(fp) + 10175a0: 00000206 br 10175ac + } + } + else + { + return -ENOTSUP; + 10175a4: 00bfde84 movi r2,-134 + 10175a8: e0bfff15 stw r2,-4(fp) + 10175ac: e0bfff17 ldw r2,-4(fp) + } +} + 10175b0: e037883a mov sp,fp + 10175b4: df000017 ldw fp,0(sp) + 10175b8: dec00104 addi sp,sp,4 + 10175bc: f800283a ret + +010175c0 : +/* + * alt_dcache_flush_all() is called to flush the entire data cache. + */ + +void alt_dcache_flush_all (void) +{ + 10175c0: defffe04 addi sp,sp,-8 + 10175c4: df000115 stw fp,4(sp) + 10175c8: df000104 addi fp,sp,4 +#if NIOS2_DCACHE_SIZE > 0 + char* i; + + for (i = (char*) 0; i < (char*) NIOS2_DCACHE_SIZE; i+= NIOS2_DCACHE_LINE_SIZE) + 10175cc: e03fff15 stw zero,-4(fp) + 10175d0: 00000506 br 10175e8 + { + __asm__ volatile ("flushd (%0)" :: "r" (i)); + 10175d4: e0bfff17 ldw r2,-4(fp) + 10175d8: 1000003b flushd 0(r2) +void alt_dcache_flush_all (void) +{ +#if NIOS2_DCACHE_SIZE > 0 + char* i; + + for (i = (char*) 0; i < (char*) NIOS2_DCACHE_SIZE; i+= NIOS2_DCACHE_LINE_SIZE) + 10175dc: e0bfff17 ldw r2,-4(fp) + 10175e0: 10800804 addi r2,r2,32 + 10175e4: e0bfff15 stw r2,-4(fp) + 10175e8: e0bfff17 ldw r2,-4(fp) + 10175ec: 10840030 cmpltui r2,r2,4096 + 10175f0: 103ff81e bne r2,zero,10175d4 + { + __asm__ volatile ("flushd (%0)" :: "r" (i)); + } +#endif /* NIOS2_DCACHE_SIZE > 0 */ +} + 10175f4: e037883a mov sp,fp + 10175f8: df000017 ldw fp,0(sp) + 10175fc: dec00104 addi sp,sp,4 + 1017600: f800283a ret + +01017604 : +/* + * + */ + +int alt_dev_llist_insert (alt_dev_llist* dev, alt_llist* list) +{ + 1017604: defff904 addi sp,sp,-28 + 1017608: dfc00615 stw ra,24(sp) + 101760c: df000515 stw fp,20(sp) + 1017610: df000504 addi fp,sp,20 + 1017614: e13ffd15 stw r4,-12(fp) + 1017618: e17ffe15 stw r5,-8(fp) + /* + * check that the device exists, and that it has a valid name. + */ + + if (!dev || !dev->name) + 101761c: e0bffd17 ldw r2,-12(fp) + 1017620: 1005003a cmpeq r2,r2,zero + 1017624: 1000041e bne r2,zero,1017638 + 1017628: e0bffd17 ldw r2,-12(fp) + 101762c: 10800217 ldw r2,8(r2) + 1017630: 1004c03a cmpne r2,r2,zero + 1017634: 1000071e bne r2,zero,1017654 + { + ALT_ERRNO = EINVAL; + 1017638: 10176b80 call 10176b8 + 101763c: 1007883a mov r3,r2 + 1017640: 00800584 movi r2,22 + 1017644: 18800015 stw r2,0(r3) + return -EINVAL; + 1017648: 00bffa84 movi r2,-22 + 101764c: e0bfff15 stw r2,-4(fp) + 1017650: 00001306 br 10176a0 + + /* + * register the device. + */ + + alt_llist_insert(list, &dev->llist); + 1017654: e0fffd17 ldw r3,-12(fp) + 1017658: e0bffe17 ldw r2,-8(fp) + 101765c: e0bffb15 stw r2,-20(fp) + 1017660: e0fffc15 stw r3,-16(fp) + */ + +static ALT_INLINE void ALT_ALWAYS_INLINE alt_llist_insert(alt_llist* list, + alt_llist* entry) +{ + entry->previous = list; + 1017664: e0fffc17 ldw r3,-16(fp) + 1017668: e0bffb17 ldw r2,-20(fp) + 101766c: 18800115 stw r2,4(r3) + entry->next = list->next; + 1017670: e0bffb17 ldw r2,-20(fp) + 1017674: 10c00017 ldw r3,0(r2) + 1017678: e0bffc17 ldw r2,-16(fp) + 101767c: 10c00015 stw r3,0(r2) + + list->next->previous = entry; + 1017680: e0bffb17 ldw r2,-20(fp) + 1017684: 10c00017 ldw r3,0(r2) + 1017688: e0bffc17 ldw r2,-16(fp) + 101768c: 18800115 stw r2,4(r3) + list->next = entry; + 1017690: e0fffb17 ldw r3,-20(fp) + 1017694: e0bffc17 ldw r2,-16(fp) + 1017698: 18800015 stw r2,0(r3) + + return 0; + 101769c: e03fff15 stw zero,-4(fp) + 10176a0: e0bfff17 ldw r2,-4(fp) +} + 10176a4: e037883a mov sp,fp + 10176a8: dfc00117 ldw ra,4(sp) + 10176ac: df000017 ldw fp,0(sp) + 10176b0: dec00204 addi sp,sp,8 + 10176b4: f800283a ret + +010176b8 : +#undef errno + +extern int errno; + +static ALT_INLINE int* alt_get_errno(void) +{ + 10176b8: defffd04 addi sp,sp,-12 + 10176bc: dfc00215 stw ra,8(sp) + 10176c0: df000115 stw fp,4(sp) + 10176c4: df000104 addi fp,sp,4 + return ((alt_errno) ? alt_errno() : &errno); + 10176c8: 008040b4 movhi r2,258 + 10176cc: 10aba104 addi r2,r2,-20860 + 10176d0: 10800017 ldw r2,0(r2) + 10176d4: 1005003a cmpeq r2,r2,zero + 10176d8: 1000061e bne r2,zero,10176f4 + 10176dc: 008040b4 movhi r2,258 + 10176e0: 10aba104 addi r2,r2,-20860 + 10176e4: 10800017 ldw r2,0(r2) + 10176e8: 103ee83a callr r2 + 10176ec: e0bfff15 stw r2,-4(fp) + 10176f0: 00000306 br 1017700 + 10176f4: 008040b4 movhi r2,258 + 10176f8: 10b30404 addi r2,r2,-13296 + 10176fc: e0bfff15 stw r2,-4(fp) + 1017700: e0bfff17 ldw r2,-4(fp) +} + 1017704: e037883a mov sp,fp + 1017708: dfc00117 ldw ra,4(sp) + 101770c: df000017 ldw fp,0(sp) + 1017710: dec00204 addi sp,sp,8 + 1017714: f800283a ret + +01017718 <_do_ctors>: +/* + * Run the C++ static constructors. + */ + +void _do_ctors(void) +{ + 1017718: defffd04 addi sp,sp,-12 + 101771c: dfc00215 stw ra,8(sp) + 1017720: df000115 stw fp,4(sp) + 1017724: df000104 addi fp,sp,4 + constructor* ctor; + + for (ctor = &__CTOR_END__[-1]; ctor >= __CTOR_LIST__; ctor--) + 1017728: 00bfff04 movi r2,-4 + 101772c: 00c040b4 movhi r3,258 + 1017730: 18e2f504 addi r3,r3,-29740 + 1017734: 1885883a add r2,r3,r2 + 1017738: e0bfff15 stw r2,-4(fp) + 101773c: 00000606 br 1017758 <_do_ctors+0x40> + (*ctor) (); + 1017740: e0bfff17 ldw r2,-4(fp) + 1017744: 10800017 ldw r2,0(r2) + 1017748: 103ee83a callr r2 + +void _do_ctors(void) +{ + constructor* ctor; + + for (ctor = &__CTOR_END__[-1]; ctor >= __CTOR_LIST__; ctor--) + 101774c: e0bfff17 ldw r2,-4(fp) + 1017750: 10bfff04 addi r2,r2,-4 + 1017754: e0bfff15 stw r2,-4(fp) + 1017758: e0ffff17 ldw r3,-4(fp) + 101775c: 008040b4 movhi r2,258 + 1017760: 10a2f304 addi r2,r2,-29748 + 1017764: 18bff62e bgeu r3,r2,1017740 <_do_ctors+0x28> + (*ctor) (); +} + 1017768: e037883a mov sp,fp + 101776c: dfc00117 ldw ra,4(sp) + 1017770: df000017 ldw fp,0(sp) + 1017774: dec00204 addi sp,sp,8 + 1017778: f800283a ret + +0101777c <_do_dtors>: +/* + * Run the C++ static destructors. + */ + +void _do_dtors(void) +{ + 101777c: defffd04 addi sp,sp,-12 + 1017780: dfc00215 stw ra,8(sp) + 1017784: df000115 stw fp,4(sp) + 1017788: df000104 addi fp,sp,4 + destructor* dtor; + + for (dtor = &__DTOR_END__[-1]; dtor >= __DTOR_LIST__; dtor--) + 101778c: 00bfff04 movi r2,-4 + 1017790: 00c040b4 movhi r3,258 + 1017794: 18e2f504 addi r3,r3,-29740 + 1017798: 1885883a add r2,r3,r2 + 101779c: e0bfff15 stw r2,-4(fp) + 10177a0: 00000606 br 10177bc <_do_dtors+0x40> + (*dtor) (); + 10177a4: e0bfff17 ldw r2,-4(fp) + 10177a8: 10800017 ldw r2,0(r2) + 10177ac: 103ee83a callr r2 + +void _do_dtors(void) +{ + destructor* dtor; + + for (dtor = &__DTOR_END__[-1]; dtor >= __DTOR_LIST__; dtor--) + 10177b0: e0bfff17 ldw r2,-4(fp) + 10177b4: 10bfff04 addi r2,r2,-4 + 10177b8: e0bfff15 stw r2,-4(fp) + 10177bc: e0ffff17 ldw r3,-4(fp) + 10177c0: 008040b4 movhi r2,258 + 10177c4: 10a2f504 addi r2,r2,-29740 + 10177c8: 18bff62e bgeu r3,r2,10177a4 <_do_dtors+0x28> + (*dtor) (); +} + 10177cc: e037883a mov sp,fp + 10177d0: dfc00117 ldw ra,4(sp) + 10177d4: df000017 ldw fp,0(sp) + 10177d8: dec00204 addi sp,sp,8 + 10177dc: f800283a ret + +010177e0 : + * "name" must be an exact match for the devices registered name for a match to + * be found. + */ + +alt_dev* alt_find_dev(const char* name, alt_llist* llist) +{ + 10177e0: defff904 addi sp,sp,-28 + 10177e4: dfc00615 stw ra,24(sp) + 10177e8: df000515 stw fp,20(sp) + 10177ec: df000504 addi fp,sp,20 + 10177f0: e13ffd15 stw r4,-12(fp) + 10177f4: e17ffe15 stw r5,-8(fp) + alt_dev* next = (alt_dev*) llist->next; + 10177f8: e0bffe17 ldw r2,-8(fp) + 10177fc: 10800017 ldw r2,0(r2) + 1017800: e0bffc15 stw r2,-16(fp) + alt_32 len; + + len = strlen(name) + 1; + 1017804: e13ffd17 ldw r4,-12(fp) + 1017808: 10034a00 call 10034a0 + 101780c: 10800044 addi r2,r2,1 + 1017810: e0bffb15 stw r2,-20(fp) + /* + * Check each list entry in turn, until a match is found, or we reach the + * end of the list (i.e. next winds up pointing back to the list head). + */ + + while (next != (alt_dev*) llist) + 1017814: 00000d06 br 101784c + /* + * memcmp() is used here rather than strcmp() in order to reduce the size + * of the executable. + */ + + if (!memcmp (next->name, name, len)) + 1017818: e0bffc17 ldw r2,-16(fp) + 101781c: 11000217 ldw r4,8(r2) + 1017820: e1bffb17 ldw r6,-20(fp) + 1017824: e17ffd17 ldw r5,-12(fp) + 1017828: 10188040 call 1018804 + 101782c: 1004c03a cmpne r2,r2,zero + 1017830: 1000031e bne r2,zero,1017840 + { + /* match found */ + + return next; + 1017834: e0bffc17 ldw r2,-16(fp) + 1017838: e0bfff15 stw r2,-4(fp) + 101783c: 00000706 br 101785c + } + next = (alt_dev*) next->llist.next; + 1017840: e0bffc17 ldw r2,-16(fp) + 1017844: 10800017 ldw r2,0(r2) + 1017848: e0bffc15 stw r2,-16(fp) + /* + * Check each list entry in turn, until a match is found, or we reach the + * end of the list (i.e. next winds up pointing back to the list head). + */ + + while (next != (alt_dev*) llist) + 101784c: e0fffe17 ldw r3,-8(fp) + 1017850: e0bffc17 ldw r2,-16(fp) + 1017854: 10fff01e bne r2,r3,1017818 + next = (alt_dev*) next->llist.next; + } + + /* No match found */ + + return NULL; + 1017858: e03fff15 stw zero,-4(fp) + 101785c: e0bfff17 ldw r2,-4(fp) +} + 1017860: e037883a mov sp,fp + 1017864: dfc00117 ldw ra,4(sp) + 1017868: df000017 ldw fp,0(sp) + 101786c: dec00204 addi sp,sp,8 + 1017870: f800283a ret + +01017874 : +/* + * alt_icache_flush_all() is called to flush the entire instruction cache. + */ + +void alt_icache_flush_all (void) +{ + 1017874: defffe04 addi sp,sp,-8 + 1017878: dfc00115 stw ra,4(sp) + 101787c: df000015 stw fp,0(sp) + 1017880: d839883a mov fp,sp +#if NIOS2_ICACHE_SIZE > 0 + alt_icache_flush (0, NIOS2_ICACHE_SIZE); + 1017884: 0009883a mov r4,zero + 1017888: 01480004 movi r5,8192 + 101788c: 10187280 call 1018728 +#endif +} + 1017890: e037883a mov sp,fp + 1017894: dfc00117 ldw ra,4(sp) + 1017898: df000017 ldw fp,0(sp) + 101789c: dec00204 addi sp,sp,8 + 10178a0: f800283a ret + +010178a4 : + * If the device can not be succesfully opened, then the input file descriptor + * remains unchanged. + */ + +static void alt_open_fd(alt_fd* fd, const char* name, int flags, int mode) +{ + 10178a4: defff904 addi sp,sp,-28 + 10178a8: dfc00615 stw ra,24(sp) + 10178ac: df000515 stw fp,20(sp) + 10178b0: df000504 addi fp,sp,20 + 10178b4: e13ffc15 stw r4,-16(fp) + 10178b8: e17ffd15 stw r5,-12(fp) + 10178bc: e1bffe15 stw r6,-8(fp) + 10178c0: e1ffff15 stw r7,-4(fp) + int old; + + old = open (name, flags, mode); + 10178c4: e13ffd17 ldw r4,-12(fp) + 10178c8: e17ffe17 ldw r5,-8(fp) + 10178cc: e1bfff17 ldw r6,-4(fp) + 10178d0: 1017c7c0 call 1017c7c + 10178d4: e0bffb15 stw r2,-20(fp) + + if (old >= 0) + 10178d8: e0bffb17 ldw r2,-20(fp) + 10178dc: 1004803a cmplt r2,r2,zero + 10178e0: 10001c1e bne r2,zero,1017954 + { + fd->dev = alt_fd_list[old].dev; + 10178e4: e0bffb17 ldw r2,-20(fp) + 10178e8: 00c040b4 movhi r3,258 + 10178ec: 18e69f04 addi r3,r3,-25988 + 10178f0: 10800324 muli r2,r2,12 + 10178f4: 10c5883a add r2,r2,r3 + 10178f8: 10c00017 ldw r3,0(r2) + 10178fc: e0bffc17 ldw r2,-16(fp) + 1017900: 10c00015 stw r3,0(r2) + fd->priv = alt_fd_list[old].priv; + 1017904: e0bffb17 ldw r2,-20(fp) + 1017908: 00c040b4 movhi r3,258 + 101790c: 18e69f04 addi r3,r3,-25988 + 1017910: 10800324 muli r2,r2,12 + 1017914: 10c5883a add r2,r2,r3 + 1017918: 10800104 addi r2,r2,4 + 101791c: 10c00017 ldw r3,0(r2) + 1017920: e0bffc17 ldw r2,-16(fp) + 1017924: 10c00115 stw r3,4(r2) + fd->fd_flags = alt_fd_list[old].fd_flags; + 1017928: e0bffb17 ldw r2,-20(fp) + 101792c: 00c040b4 movhi r3,258 + 1017930: 18e69f04 addi r3,r3,-25988 + 1017934: 10800324 muli r2,r2,12 + 1017938: 10c5883a add r2,r2,r3 + 101793c: 10800204 addi r2,r2,8 + 1017940: 10c00017 ldw r3,0(r2) + 1017944: e0bffc17 ldw r2,-16(fp) + 1017948: 10c00215 stw r3,8(r2) + + alt_release_fd (old); + 101794c: e13ffb17 ldw r4,-20(fp) + 1017950: 100ccfc0 call 100ccfc + } +} + 1017954: e037883a mov sp,fp + 1017958: dfc00117 ldw ra,4(sp) + 101795c: df000017 ldw fp,0(sp) + 1017960: dec00204 addi sp,sp,8 + 1017964: f800283a ret + +01017968 : + */ + +void alt_io_redirect(const char* stdout_dev, + const char* stdin_dev, + const char* stderr_dev) +{ + 1017968: defffb04 addi sp,sp,-20 + 101796c: dfc00415 stw ra,16(sp) + 1017970: df000315 stw fp,12(sp) + 1017974: df000304 addi fp,sp,12 + 1017978: e13ffd15 stw r4,-12(fp) + 101797c: e17ffe15 stw r5,-8(fp) + 1017980: e1bfff15 stw r6,-4(fp) + /* Redirect the channels */ + + alt_open_fd (&alt_fd_list[STDOUT_FILENO], stdout_dev, O_WRONLY, 0777); + 1017984: 010040b4 movhi r4,258 + 1017988: 2126a204 addi r4,r4,-25976 + 101798c: e17ffd17 ldw r5,-12(fp) + 1017990: 01800044 movi r6,1 + 1017994: 01c07fc4 movi r7,511 + 1017998: 10178a40 call 10178a4 + alt_open_fd (&alt_fd_list[STDIN_FILENO], stdin_dev, O_RDONLY, 0777); + 101799c: 010040b4 movhi r4,258 + 10179a0: 21269f04 addi r4,r4,-25988 + 10179a4: e17ffe17 ldw r5,-8(fp) + 10179a8: 000d883a mov r6,zero + 10179ac: 01c07fc4 movi r7,511 + 10179b0: 10178a40 call 10178a4 + alt_open_fd (&alt_fd_list[STDERR_FILENO], stderr_dev, O_WRONLY, 0777); + 10179b4: 010040b4 movhi r4,258 + 10179b8: 2126a504 addi r4,r4,-25964 + 10179bc: e17fff17 ldw r5,-4(fp) + 10179c0: 01800044 movi r6,1 + 10179c4: 01c07fc4 movi r7,511 + 10179c8: 10178a40 call 10178a4 +} + 10179cc: e037883a mov sp,fp + 10179d0: dfc00117 ldw ra,4(sp) + 10179d4: df000017 ldw fp,0(sp) + 10179d8: dec00204 addi sp,sp,8 + 10179dc: f800283a ret + +010179e0 : + */ + +int alt_irq_register (alt_u32 id, + void* context, + alt_isr_func handler) +{ + 10179e0: deffef04 addi sp,sp,-68 + 10179e4: df001015 stw fp,64(sp) + 10179e8: df001004 addi fp,sp,64 + 10179ec: e13ffc15 stw r4,-16(fp) + 10179f0: e17ffd15 stw r5,-12(fp) + 10179f4: e1bffe15 stw r6,-8(fp) + int rc = -EINVAL; + 10179f8: 00bffa84 movi r2,-22 + 10179fc: e0bffb15 stw r2,-20(fp) + alt_irq_context status; + + if (id < ALT_NIRQ) + 1017a00: e0bffc17 ldw r2,-16(fp) + 1017a04: 10800828 cmpgeui r2,r2,32 + 1017a08: 1000601e bne r2,zero,1017b8c +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1017a0c: 0005303a rdctl r2,status + 1017a10: e0bff915 stw r2,-28(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1017a14: e0fff917 ldw r3,-28(fp) + 1017a18: 00bfff84 movi r2,-2 + 1017a1c: 1884703a and r2,r3,r2 + 1017a20: 1001703a wrctl status,r2 + + return context; + 1017a24: e0bff917 ldw r2,-28(fp) + * interrupts are disabled while the handler tables are updated to ensure + * that an interrupt doesn't occur while the tables are in an inconsistant + * state. + */ + + status = alt_irq_disable_all (); + 1017a28: e0bffa15 stw r2,-24(fp) + + alt_irq[id].handler = handler; + 1017a2c: e0bffc17 ldw r2,-16(fp) + 1017a30: 00c040b4 movhi r3,258 + 1017a34: 18d9be04 addi r3,r3,26360 + 1017a38: 100490fa slli r2,r2,3 + 1017a3c: 10c7883a add r3,r2,r3 + 1017a40: e0bffe17 ldw r2,-8(fp) + 1017a44: 18800015 stw r2,0(r3) + alt_irq[id].context = context; + 1017a48: e0bffc17 ldw r2,-16(fp) + 1017a4c: 00c040b4 movhi r3,258 + 1017a50: 18d9be04 addi r3,r3,26360 + 1017a54: 100490fa slli r2,r2,3 + 1017a58: 10c5883a add r2,r2,r3 + 1017a5c: 10c00104 addi r3,r2,4 + 1017a60: e0bffd17 ldw r2,-12(fp) + 1017a64: 18800015 stw r2,0(r3) + + rc = (handler) ? alt_irq_enable (id): alt_irq_disable (id); + 1017a68: e0bffe17 ldw r2,-8(fp) + 1017a6c: 1005003a cmpeq r2,r2,zero + 1017a70: 1000201e bne r2,zero,1017af4 + 1017a74: e0bffc17 ldw r2,-16(fp) + 1017a78: e0bff715 stw r2,-36(fp) +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1017a7c: 0005303a rdctl r2,status + 1017a80: e0bff615 stw r2,-40(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1017a84: e0fff617 ldw r3,-40(fp) + 1017a88: 00bfff84 movi r2,-2 + 1017a8c: 1884703a and r2,r3,r2 + 1017a90: 1001703a wrctl status,r2 + + return context; + 1017a94: e0bff617 ldw r2,-40(fp) +static ALT_INLINE int ALT_ALWAYS_INLINE alt_irq_enable (alt_u32 id) +{ + alt_irq_context status; + extern volatile alt_u32 alt_irq_active; + + status = alt_irq_disable_all (); + 1017a98: e0bff815 stw r2,-32(fp) + + alt_irq_active |= (1 << id); + 1017a9c: e0fff717 ldw r3,-36(fp) + 1017aa0: 00800044 movi r2,1 + 1017aa4: 10c4983a sll r2,r2,r3 + 1017aa8: 1007883a mov r3,r2 + 1017aac: 008040b4 movhi r2,258 + 1017ab0: 10b32404 addi r2,r2,-13168 + 1017ab4: 10800017 ldw r2,0(r2) + 1017ab8: 1886b03a or r3,r3,r2 + 1017abc: 008040b4 movhi r2,258 + 1017ac0: 10b32404 addi r2,r2,-13168 + 1017ac4: 10c00015 stw r3,0(r2) + NIOS2_WRITE_IENABLE (alt_irq_active); + 1017ac8: 008040b4 movhi r2,258 + 1017acc: 10b32404 addi r2,r2,-13168 + 1017ad0: 10800017 ldw r2,0(r2) + 1017ad4: 100170fa wrctl ienable,r2 + 1017ad8: e0bff817 ldw r2,-32(fp) + 1017adc: e0bff515 stw r2,-44(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1017ae0: e0bff517 ldw r2,-44(fp) + 1017ae4: 1001703a wrctl status,r2 + + alt_irq_enable_all(status); + + return 0; + 1017ae8: 0005883a mov r2,zero + 1017aec: e0bfff15 stw r2,-4(fp) + 1017af0: 00002006 br 1017b74 + 1017af4: e0bffc17 ldw r2,-16(fp) + 1017af8: e0bff315 stw r2,-52(fp) +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1017afc: 0005303a rdctl r2,status + 1017b00: e0bff215 stw r2,-56(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1017b04: e0fff217 ldw r3,-56(fp) + 1017b08: 00bfff84 movi r2,-2 + 1017b0c: 1884703a and r2,r3,r2 + 1017b10: 1001703a wrctl status,r2 + + return context; + 1017b14: e0bff217 ldw r2,-56(fp) +static ALT_INLINE int ALT_ALWAYS_INLINE alt_irq_disable (alt_u32 id) +{ + alt_irq_context status; + extern volatile alt_u32 alt_irq_active; + + status = alt_irq_disable_all (); + 1017b18: e0bff415 stw r2,-48(fp) + + alt_irq_active &= ~(1 << id); + 1017b1c: e0fff317 ldw r3,-52(fp) + 1017b20: 00800044 movi r2,1 + 1017b24: 10c4983a sll r2,r2,r3 + 1017b28: 0084303a nor r2,zero,r2 + 1017b2c: 1007883a mov r3,r2 + 1017b30: 008040b4 movhi r2,258 + 1017b34: 10b32404 addi r2,r2,-13168 + 1017b38: 10800017 ldw r2,0(r2) + 1017b3c: 1886703a and r3,r3,r2 + 1017b40: 008040b4 movhi r2,258 + 1017b44: 10b32404 addi r2,r2,-13168 + 1017b48: 10c00015 stw r3,0(r2) + NIOS2_WRITE_IENABLE (alt_irq_active); + 1017b4c: 008040b4 movhi r2,258 + 1017b50: 10b32404 addi r2,r2,-13168 + 1017b54: 10800017 ldw r2,0(r2) + 1017b58: 100170fa wrctl ienable,r2 + 1017b5c: e0bff417 ldw r2,-48(fp) + 1017b60: e0bff115 stw r2,-60(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1017b64: e0bff117 ldw r2,-60(fp) + 1017b68: 1001703a wrctl status,r2 + + alt_irq_enable_all(status); + + return 0; + 1017b6c: 0005883a mov r2,zero + 1017b70: e0bfff15 stw r2,-4(fp) + 1017b74: e0bfff17 ldw r2,-4(fp) + 1017b78: e0bffb15 stw r2,-20(fp) + 1017b7c: e0bffa17 ldw r2,-24(fp) + 1017b80: e0bff015 stw r2,-64(fp) + 1017b84: e0bff017 ldw r2,-64(fp) + 1017b88: 1001703a wrctl status,r2 + + alt_irq_enable_all(status); + } + return rc; + 1017b8c: e0bffb17 ldw r2,-20(fp) +} + 1017b90: e037883a mov sp,fp + 1017b94: df000017 ldw fp,0(sp) + 1017b98: dec00104 addi sp,sp,4 + 1017b9c: f800283a ret + +01017ba0 : + * performed for devices. Filesystems are required to handle the ioctl() call + * themselves, and report the error from the filesystems open() function. + */ + +static int alt_file_locked (alt_fd* fd) +{ + 1017ba0: defffc04 addi sp,sp,-16 + 1017ba4: df000315 stw fp,12(sp) + 1017ba8: df000304 addi fp,sp,12 + 1017bac: e13ffe15 stw r4,-8(fp) + + /* + * Mark the file descriptor as belonging to a device. + */ + + fd->fd_flags |= ALT_FD_DEV; + 1017bb0: e0bffe17 ldw r2,-8(fp) + 1017bb4: 10800217 ldw r2,8(r2) + 1017bb8: 10d00034 orhi r3,r2,16384 + 1017bbc: e0bffe17 ldw r2,-8(fp) + 1017bc0: 10c00215 stw r3,8(r2) + /* + * Loop through all current file descriptors searching for one that's locked + * for exclusive access. If a match is found, generate an error. + */ + + for (i = 0; i <= alt_max_fd; i++) + 1017bc4: e03ffd15 stw zero,-12(fp) + 1017bc8: 00002006 br 1017c4c + { + if ((alt_fd_list[i].dev == fd->dev) && + 1017bcc: e0bffd17 ldw r2,-12(fp) + 1017bd0: 00c040b4 movhi r3,258 + 1017bd4: 18e69f04 addi r3,r3,-25988 + 1017bd8: 10800324 muli r2,r2,12 + 1017bdc: 10c5883a add r2,r2,r3 + 1017be0: 10c00017 ldw r3,0(r2) + 1017be4: e0bffe17 ldw r2,-8(fp) + 1017be8: 10800017 ldw r2,0(r2) + 1017bec: 1880141e bne r3,r2,1017c40 + 1017bf0: e0bffd17 ldw r2,-12(fp) + 1017bf4: 00c040b4 movhi r3,258 + 1017bf8: 18e69f04 addi r3,r3,-25988 + 1017bfc: 10800324 muli r2,r2,12 + 1017c00: 10c5883a add r2,r2,r3 + 1017c04: 10800204 addi r2,r2,8 + 1017c08: 10800017 ldw r2,0(r2) + 1017c0c: 1004403a cmpge r2,r2,zero + 1017c10: 10000b1e bne r2,zero,1017c40 + 1017c14: e0bffd17 ldw r2,-12(fp) + 1017c18: 10800324 muli r2,r2,12 + 1017c1c: 1007883a mov r3,r2 + 1017c20: 008040b4 movhi r2,258 + 1017c24: 10a69f04 addi r2,r2,-25988 + 1017c28: 1887883a add r3,r3,r2 + 1017c2c: e0bffe17 ldw r2,-8(fp) + 1017c30: 18800326 beq r3,r2,1017c40 + (alt_fd_list[i].fd_flags & ALT_FD_EXCL) && + (&alt_fd_list[i] != fd)) + { + return -EACCES; + 1017c34: 00bffcc4 movi r2,-13 + 1017c38: e0bfff15 stw r2,-4(fp) + 1017c3c: 00000a06 br 1017c68 + /* + * Loop through all current file descriptors searching for one that's locked + * for exclusive access. If a match is found, generate an error. + */ + + for (i = 0; i <= alt_max_fd; i++) + 1017c40: e0bffd17 ldw r2,-12(fp) + 1017c44: 10800044 addi r2,r2,1 + 1017c48: e0bffd15 stw r2,-12(fp) + 1017c4c: 008040b4 movhi r2,258 + 1017c50: 10aba004 addi r2,r2,-20864 + 1017c54: 10800017 ldw r2,0(r2) + 1017c58: 1007883a mov r3,r2 + 1017c5c: e0bffd17 ldw r2,-12(fp) + 1017c60: 18bfda2e bgeu r3,r2,1017bcc + } + } + + /* The device is not locked */ + + return 0; + 1017c64: e03fff15 stw zero,-4(fp) + 1017c68: e0bfff17 ldw r2,-4(fp) +} + 1017c6c: e037883a mov sp,fp + 1017c70: df000017 ldw fp,0(sp) + 1017c74: dec00104 addi sp,sp,4 + 1017c78: f800283a ret + +01017c7c : + * + * ALT_OPEN is mapped onto the open() system call in alt_syscall.h + */ + +int ALT_OPEN (const char* file, int flags, int mode) +{ + 1017c7c: defff404 addi sp,sp,-48 + 1017c80: dfc00b15 stw ra,44(sp) + 1017c84: df000a15 stw fp,40(sp) + 1017c88: df000a04 addi fp,sp,40 + 1017c8c: e13ffb15 stw r4,-20(fp) + 1017c90: e17ffc15 stw r5,-16(fp) + 1017c94: e1bffd15 stw r6,-12(fp) + alt_dev* dev; + alt_fd* fd; + int index = -1; + 1017c98: 00bfffc4 movi r2,-1 + 1017c9c: e0bff815 stw r2,-32(fp) + int status = -ENODEV; + 1017ca0: 00bffb44 movi r2,-19 + 1017ca4: e0bff715 stw r2,-36(fp) + int isafs = 0; + 1017ca8: e03ff615 stw zero,-40(fp) + /* + * Check the device list, to see if a device with a matching name is + * registered. + */ + + if (!(dev = alt_find_dev (file, &alt_dev_list))) + 1017cac: e13ffb17 ldw r4,-20(fp) + 1017cb0: 014040b4 movhi r5,258 + 1017cb4: 296b9e04 addi r5,r5,-20872 + 1017cb8: 10177e00 call 10177e0 + 1017cbc: e0bffa15 stw r2,-24(fp) + 1017cc0: e0bffa17 ldw r2,-24(fp) + 1017cc4: 1004c03a cmpne r2,r2,zero + 1017cc8: 1000051e bne r2,zero,1017ce0 + { + /* No matching device, so try the filesystem list */ + + dev = alt_find_file (file); + 1017ccc: e13ffb17 ldw r4,-20(fp) + 1017cd0: 10185140 call 1018514 + 1017cd4: e0bffa15 stw r2,-24(fp) + isafs = 1; + 1017cd8: 00800044 movi r2,1 + 1017cdc: e0bff615 stw r2,-40(fp) + + /* + * If a matching device or filesystem is found, allocate a file descriptor. + */ + + if (dev) + 1017ce0: e0bffa17 ldw r2,-24(fp) + 1017ce4: 1005003a cmpeq r2,r2,zero + 1017ce8: 1000301e bne r2,zero,1017dac + { + if ((index = alt_get_fd (dev)) < 0) + 1017cec: e13ffa17 ldw r4,-24(fp) + 1017cf0: 10186340 call 1018634 + 1017cf4: e0bff815 stw r2,-32(fp) + 1017cf8: e0bff817 ldw r2,-32(fp) + 1017cfc: 1004403a cmpge r2,r2,zero + 1017d00: 1000031e bne r2,zero,1017d10 + { + status = index; + 1017d04: e0bff817 ldw r2,-32(fp) + 1017d08: e0bff715 stw r2,-36(fp) + 1017d0c: 00002906 br 1017db4 + } + else + { + fd = &alt_fd_list[index]; + 1017d10: e0bff817 ldw r2,-32(fp) + 1017d14: 10800324 muli r2,r2,12 + 1017d18: 1007883a mov r3,r2 + 1017d1c: 008040b4 movhi r2,258 + 1017d20: 10a69f04 addi r2,r2,-25988 + 1017d24: 1885883a add r2,r3,r2 + 1017d28: e0bff915 stw r2,-28(fp) + fd->fd_flags = (flags & ~ALT_FD_FLAGS_MASK); + 1017d2c: e0fffc17 ldw r3,-16(fp) + 1017d30: 00900034 movhi r2,16384 + 1017d34: 10bfffc4 addi r2,r2,-1 + 1017d38: 1886703a and r3,r3,r2 + 1017d3c: e0bff917 ldw r2,-28(fp) + 1017d40: 10c00215 stw r3,8(r2) + + /* If this is a device, ensure it isn't already locked */ + + if (isafs || ((status = alt_file_locked (fd)) >= 0)) + 1017d44: e0bff617 ldw r2,-40(fp) + 1017d48: 1004c03a cmpne r2,r2,zero + 1017d4c: 1000061e bne r2,zero,1017d68 + 1017d50: e13ff917 ldw r4,-28(fp) + 1017d54: 1017ba00 call 1017ba0 + 1017d58: e0bff715 stw r2,-36(fp) + 1017d5c: e0bff717 ldw r2,-36(fp) + 1017d60: 1004803a cmplt r2,r2,zero + 1017d64: 1000131e bne r2,zero,1017db4 + /* + * If the device or filesystem provides an open() callback function, + * call it now to perform any device/filesystem specific operations. + */ + + status = (dev->open) ? dev->open(fd, file, flags, mode): 0; + 1017d68: e0bffa17 ldw r2,-24(fp) + 1017d6c: 10800317 ldw r2,12(r2) + 1017d70: 1005003a cmpeq r2,r2,zero + 1017d74: 1000091e bne r2,zero,1017d9c + 1017d78: e0bffa17 ldw r2,-24(fp) + 1017d7c: 10800317 ldw r2,12(r2) + 1017d80: e13ff917 ldw r4,-28(fp) + 1017d84: e17ffb17 ldw r5,-20(fp) + 1017d88: e1bffc17 ldw r6,-16(fp) + 1017d8c: e1fffd17 ldw r7,-12(fp) + 1017d90: 103ee83a callr r2 + 1017d94: e0bfff15 stw r2,-4(fp) + 1017d98: 00000106 br 1017da0 + 1017d9c: e03fff15 stw zero,-4(fp) + 1017da0: e0bfff17 ldw r2,-4(fp) + 1017da4: e0bff715 stw r2,-36(fp) + 1017da8: 00000206 br 1017db4 + } + } + } + else + { + status = -ENODEV; + 1017dac: 00bffb44 movi r2,-19 + 1017db0: e0bff715 stw r2,-36(fp) + } + + /* Allocation failed, so clean up and return an error */ + + if (status < 0) + 1017db4: e0bff717 ldw r2,-36(fp) + 1017db8: 1004403a cmpge r2,r2,zero + 1017dbc: 1000091e bne r2,zero,1017de4 + { + alt_release_fd (index); + 1017dc0: e13ff817 ldw r4,-32(fp) + 1017dc4: 100ccfc0 call 100ccfc + ALT_ERRNO = -status; + 1017dc8: 1017e040 call 1017e04 + 1017dcc: e0fff717 ldw r3,-36(fp) + 1017dd0: 00c7c83a sub r3,zero,r3 + 1017dd4: 10c00015 stw r3,0(r2) + return -1; + 1017dd8: 00bfffc4 movi r2,-1 + 1017ddc: e0bffe15 stw r2,-8(fp) + 1017de0: 00000206 br 1017dec + } + + /* return the reference upon success */ + + return index; + 1017de4: e0bff817 ldw r2,-32(fp) + 1017de8: e0bffe15 stw r2,-8(fp) + 1017dec: e0bffe17 ldw r2,-8(fp) +} + 1017df0: e037883a mov sp,fp + 1017df4: dfc00117 ldw ra,4(sp) + 1017df8: df000017 ldw fp,0(sp) + 1017dfc: dec00204 addi sp,sp,8 + 1017e00: f800283a ret + +01017e04 : +#undef errno + +extern int errno; + +static ALT_INLINE int* alt_get_errno(void) +{ + 1017e04: defffd04 addi sp,sp,-12 + 1017e08: dfc00215 stw ra,8(sp) + 1017e0c: df000115 stw fp,4(sp) + 1017e10: df000104 addi fp,sp,4 + return ((alt_errno) ? alt_errno() : &errno); + 1017e14: 008040b4 movhi r2,258 + 1017e18: 10aba104 addi r2,r2,-20860 + 1017e1c: 10800017 ldw r2,0(r2) + 1017e20: 1005003a cmpeq r2,r2,zero + 1017e24: 1000061e bne r2,zero,1017e40 + 1017e28: 008040b4 movhi r2,258 + 1017e2c: 10aba104 addi r2,r2,-20860 + 1017e30: 10800017 ldw r2,0(r2) + 1017e34: 103ee83a callr r2 + 1017e38: e0bfff15 stw r2,-4(fp) + 1017e3c: 00000306 br 1017e4c + 1017e40: 008040b4 movhi r2,258 + 1017e44: 10b30404 addi r2,r2,-13296 + 1017e48: e0bfff15 stw r2,-4(fp) + 1017e4c: e0bfff17 ldw r2,-4(fp) +} + 1017e50: e037883a mov sp,fp + 1017e54: dfc00117 ldw ra,4(sp) + 1017e58: df000017 ldw fp,0(sp) + 1017e5c: dec00204 addi sp,sp,8 + 1017e60: f800283a ret + +01017e64 : + * alarms. Alternatively an alarm can unregister itself by returning zero when + * the alarm executes. + */ + +void alt_alarm_stop (alt_alarm* alarm) +{ + 1017e64: defffa04 addi sp,sp,-24 + 1017e68: df000515 stw fp,20(sp) + 1017e6c: df000504 addi fp,sp,20 + 1017e70: e13fff15 stw r4,-4(fp) +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + 1017e74: 0005303a rdctl r2,status + 1017e78: e0bffd15 stw r2,-12(fp) + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + 1017e7c: e0fffd17 ldw r3,-12(fp) + 1017e80: 00bfff84 movi r2,-2 + 1017e84: 1884703a and r2,r3,r2 + 1017e88: 1001703a wrctl status,r2 + + return context; + 1017e8c: e0bffd17 ldw r2,-12(fp) + alt_irq_context irq_context; + + irq_context = alt_irq_disable_all(); + 1017e90: e0bffe15 stw r2,-8(fp) + alt_llist_remove (&alarm->llist); + 1017e94: e0bfff17 ldw r2,-4(fp) + 1017e98: e0bffc15 stw r2,-16(fp) + * input argument is the element to remove. + */ + +static ALT_INLINE void ALT_ALWAYS_INLINE alt_llist_remove(alt_llist* entry) +{ + entry->next->previous = entry->previous; + 1017e9c: e0bffc17 ldw r2,-16(fp) + 1017ea0: 10c00017 ldw r3,0(r2) + 1017ea4: e0bffc17 ldw r2,-16(fp) + 1017ea8: 10800117 ldw r2,4(r2) + 1017eac: 18800115 stw r2,4(r3) + entry->previous->next = entry->next; + 1017eb0: e0bffc17 ldw r2,-16(fp) + 1017eb4: 10c00117 ldw r3,4(r2) + 1017eb8: e0bffc17 ldw r2,-16(fp) + 1017ebc: 10800017 ldw r2,0(r2) + 1017ec0: 18800015 stw r2,0(r3) + /* + * Set the entry to point to itself, so that any further calls to + * alt_llist_remove() are harmless. + */ + + entry->previous = entry; + 1017ec4: e0fffc17 ldw r3,-16(fp) + 1017ec8: e0bffc17 ldw r2,-16(fp) + 1017ecc: 18800115 stw r2,4(r3) + entry->next = entry; + 1017ed0: e0fffc17 ldw r3,-16(fp) + 1017ed4: e0bffc17 ldw r2,-16(fp) + 1017ed8: 18800015 stw r2,0(r3) + 1017edc: e0bffe17 ldw r2,-8(fp) + 1017ee0: e0bffb15 stw r2,-20(fp) + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); + 1017ee4: e0bffb17 ldw r2,-20(fp) + 1017ee8: 1001703a wrctl status,r2 + alt_irq_enable_all (irq_context); +} + 1017eec: e037883a mov sp,fp + 1017ef0: df000017 ldw fp,0(sp) + 1017ef4: dec00104 addi sp,sp,4 + 1017ef8: f800283a ret + +01017efc : + * + * alt_tick() is expected to run at interrupt level. + */ + +void alt_tick (void) +{ + 1017efc: defffb04 addi sp,sp,-20 + 1017f00: dfc00415 stw ra,16(sp) + 1017f04: df000315 stw fp,12(sp) + 1017f08: df000304 addi fp,sp,12 + alt_alarm* next; + alt_alarm* alarm = (alt_alarm*) alt_alarm_list.next; + 1017f0c: d0a03617 ldw r2,-32552(gp) + 1017f10: e0bffe15 stw r2,-8(fp) + + alt_u32 next_callback; + + /* update the tick counter */ + + _alt_nticks++; + 1017f14: d0a79917 ldw r2,-24988(gp) + 1017f18: 10800044 addi r2,r2,1 + 1017f1c: d0a79915 stw r2,-24988(gp) + + /* process the registered callbacks */ + + while (alarm != (alt_alarm*) &alt_alarm_list) + 1017f20: 00003106 br 1017fe8 + { + next = (alt_alarm*) alarm->llist.next; + 1017f24: e0bffe17 ldw r2,-8(fp) + 1017f28: 10800017 ldw r2,0(r2) + 1017f2c: e0bfff15 stw r2,-4(fp) + /* + * Upon the tick-counter rolling over it is safe to clear the + * roll-over flag; once the flag is cleared this (or subsequnt) + * tick events are enabled to generate an alarm event. + */ + if ((alarm->rollover) && (_alt_nticks == 0)) + 1017f30: e0bffe17 ldw r2,-8(fp) + 1017f34: 10800403 ldbu r2,16(r2) + 1017f38: 10803fcc andi r2,r2,255 + 1017f3c: 1005003a cmpeq r2,r2,zero + 1017f40: 1000051e bne r2,zero,1017f58 + 1017f44: d0a79917 ldw r2,-24988(gp) + 1017f48: 1004c03a cmpne r2,r2,zero + 1017f4c: 1000021e bne r2,zero,1017f58 + { + alarm->rollover = 0; + 1017f50: e0bffe17 ldw r2,-8(fp) + 1017f54: 10000405 stb zero,16(r2) + } + + /* if the alarm period has expired, make the callback */ + if ((alarm->time <= _alt_nticks) && (alarm->rollover == 0)) + 1017f58: e0bffe17 ldw r2,-8(fp) + 1017f5c: 10c00217 ldw r3,8(r2) + 1017f60: d0a79917 ldw r2,-24988(gp) + 1017f64: 10c01e36 bltu r2,r3,1017fe0 + 1017f68: e0bffe17 ldw r2,-8(fp) + 1017f6c: 10800403 ldbu r2,16(r2) + 1017f70: 10803fcc andi r2,r2,255 + 1017f74: 1004c03a cmpne r2,r2,zero + 1017f78: 1000191e bne r2,zero,1017fe0 + { + next_callback = alarm->callback (alarm->context); + 1017f7c: e0bffe17 ldw r2,-8(fp) + 1017f80: 10c00317 ldw r3,12(r2) + 1017f84: e0bffe17 ldw r2,-8(fp) + 1017f88: 11000517 ldw r4,20(r2) + 1017f8c: 183ee83a callr r3 + 1017f90: e0bffd15 stw r2,-12(fp) + + /* deactivate the alarm if the return value is zero */ + + if (next_callback == 0) + 1017f94: e0bffd17 ldw r2,-12(fp) + 1017f98: 1004c03a cmpne r2,r2,zero + 1017f9c: 1000031e bne r2,zero,1017fac + { + alt_alarm_stop (alarm); + 1017fa0: e13ffe17 ldw r4,-8(fp) + 1017fa4: 1017e640 call 1017e64 + 1017fa8: 00000d06 br 1017fe0 + } + else + { + alarm->time += next_callback; + 1017fac: e0bffe17 ldw r2,-8(fp) + 1017fb0: 10c00217 ldw r3,8(r2) + 1017fb4: e0bffd17 ldw r2,-12(fp) + 1017fb8: 1887883a add r3,r3,r2 + 1017fbc: e0bffe17 ldw r2,-8(fp) + 1017fc0: 10c00215 stw r3,8(r2) + /* + * If the desired alarm time causes a roll-over, set the rollover + * flag. This will prevent the subsequent tick event from causing + * an alarm too early. + */ + if(alarm->time < _alt_nticks) + 1017fc4: e0bffe17 ldw r2,-8(fp) + 1017fc8: 10c00217 ldw r3,8(r2) + 1017fcc: d0a79917 ldw r2,-24988(gp) + 1017fd0: 1880032e bgeu r3,r2,1017fe0 + { + alarm->rollover = 1; + 1017fd4: e0fffe17 ldw r3,-8(fp) + 1017fd8: 00800044 movi r2,1 + 1017fdc: 18800405 stb r2,16(r3) + } + } + } + alarm = next; + 1017fe0: e0bfff17 ldw r2,-4(fp) + 1017fe4: e0bffe15 stw r2,-8(fp) + + _alt_nticks++; + + /* process the registered callbacks */ + + while (alarm != (alt_alarm*) &alt_alarm_list) + 1017fe8: d0e03604 addi r3,gp,-32552 + 1017fec: e0bffe17 ldw r2,-8(fp) + 1017ff0: 10ffcc1e bne r2,r3,1017f24 + + /* + * Update the operating system specific timer facilities. + */ + + ALT_OS_TIME_TICK(); + 1017ff4: 100dffc0 call 100dffc +} + 1017ff8: e037883a mov sp,fp + 1017ffc: dfc00117 ldw ra,4(sp) + 1018000: df000017 ldw fp,0(sp) + 1018004: dec00204 addi sp,sp,8 + 1018008: f800283a ret + +0101800c : +/* + * To initialize the internal interrupt controller, just clear the IENABLE + * register so that all possible IRQs are disabled. + */ +void altera_nios2_qsys_irq_init(void) +{ + 101800c: deffff04 addi sp,sp,-4 + 1018010: df000015 stw fp,0(sp) + 1018014: d839883a mov fp,sp + NIOS2_WRITE_IENABLE(0); + 1018018: 000170fa wrctl ienable,zero +} + 101801c: e037883a mov sp,fp + 1018020: df000017 ldw fp,0(sp) + 1018024: dec00104 addi sp,sp,4 + 1018028: f800283a ret + +0101802c : + + /* + * Save the remaining registers to the stack. + */ + + addi sp, sp, -44 + 101802c: defff504 addi sp,sp,-44 + bltu sp, et, .Lstack_overflow + +#endif + +#if OS_THREAD_SAFE_NEWLIB + ldw r3, %gprel(_impure_ptr)(gp) /* load the pointer */ + 1018030: d0e00b17 ldw r3,-32724(gp) +#endif /* OS_THREAD_SAFE_NEWLIB */ + + ldw r4, %gprel(OSTCBCur)(gp) + 1018034: d1279217 ldw r4,-25016(gp) + + stw ra, 0(sp) + 1018038: dfc00015 stw ra,0(sp) + stw fp, 4(sp) + 101803c: df000115 stw fp,4(sp) + stw r23, 8(sp) + 1018040: ddc00215 stw r23,8(sp) + stw r22, 12(sp) + 1018044: dd800315 stw r22,12(sp) + stw r21, 16(sp) + 1018048: dd400415 stw r21,16(sp) + stw r20, 20(sp) + 101804c: dd000515 stw r20,20(sp) + stw r19, 24(sp) + 1018050: dcc00615 stw r19,24(sp) + stw r18, 28(sp) + 1018054: dc800715 stw r18,28(sp) + stw r17, 32(sp) + 1018058: dc400815 stw r17,32(sp) + stw r16, 36(sp) + 101805c: dc000915 stw r16,36(sp) + * store the current value of _impure_ptr so it can be restored + * later; _impure_ptr is asigned on a per task basis. It is used + * by Newlib to achieve reentrancy. + */ + + stw r3, 40(sp) /* save the impure pointer */ + 1018060: d8c00a15 stw r3,40(sp) + /* + * Save the current tasks stack pointer into the current tasks OS_TCB. + * i.e. OSTCBCur->OSTCBStkPtr = sp; + */ + + stw sp, (r4) /* save the stack pointer (OSTCBStkPtr */ + 1018064: 26c00015 stw sp,0(r4) + + /* + * Call the user definable OSTaskSWHook() + */ + + call OSTaskSwHook + 1018068: 101844c0 call 101844c + /* + * OSTCBCur = OSTCBHighRdy; + * OSPrioCur = OSPrioHighRdy; + */ + + ldw r4, %gprel(OSTCBHighRdy)(gp) + 101806c: d1278d17 ldw r4,-25036(gp) + ldb r5, %gprel(OSPrioHighRdy)(gp) + 1018070: d1678507 ldb r5,-25068(gp) + + stw r4, %gprel(OSTCBCur)(gp) /* set the current task to be the new task */ + 1018074: d1279215 stw r4,-25016(gp) + stb r5, %gprel(OSPrioCur)(gp) /* store the new task's priority as the current */ + 1018078: d1678545 stb r5,-25067(gp) + + /* + * Set the stack pointer to point to the new task's stack + */ + + ldw sp, (r4) /* the stack pointer is the first entry in the OS_TCB structure */ + 101807c: 26c00017 ldw sp,0(r4) + /* + * restore the value of _impure_ptr ; _impure_ptr is asigned on a + * per task basis. It is used by Newlib to achieve reentrancy. + */ + + ldw r3, 40(sp) /* load the new impure pointer */ + 1018080: d8c00a17 ldw r3,40(sp) + + /* + * Restore the saved registers for the new task. + */ + + ldw ra, 0(sp) + 1018084: dfc00017 ldw ra,0(sp) + ldw fp, 4(sp) + 1018088: df000117 ldw fp,4(sp) + ldw r23, 8(sp) + 101808c: ddc00217 ldw r23,8(sp) + ldw r22, 12(sp) + 1018090: dd800317 ldw r22,12(sp) + ldw r21, 16(sp) + 1018094: dd400417 ldw r21,16(sp) + ldw r20, 20(sp) + 1018098: dd000517 ldw r20,20(sp) + ldw r19, 24(sp) + 101809c: dcc00617 ldw r19,24(sp) + ldw r18, 28(sp) + 10180a0: dc800717 ldw r18,28(sp) + ldw r17, 32(sp) + 10180a4: dc400817 ldw r17,32(sp) + ldw r16, 36(sp) + 10180a8: dc000917 ldw r16,36(sp) + +#if OS_THREAD_SAFE_NEWLIB + + stw r3, %gprel(_impure_ptr)(gp) /* update _impure_ptr */ + 10180ac: d0e00b15 stw r3,-32724(gp) + + stw et, %gprel(alt_stack_limit_value)(gp) + +#endif + + addi sp, sp, 44 + 10180b0: dec00b04 addi sp,sp,44 + + /* + * resume execution of the new task. + */ + + ret + 10180b4: f800283a ret + +010180b8 : + + /* + * disable interrupts so that the scheduler doesn't run while + * we're initialising this task. + */ + rdctl r18, status + 10180b8: 0025303a rdctl r18,status + subi r17, zero, 2 /* r17 = 0xfffffffe */ + 10180bc: 047fff84 movi r17,-2 + and r18, r18, r17 + 10180c0: 9464703a and r18,r18,r17 + wrctl status, r18 + 10180c4: 9001703a wrctl status,r18 + + /* + * Call the user definable OSTaskSWHook() + */ + + call OSTaskSwHook + 10180c8: 101844c0 call 101844c + + /* + * set OSRunning = TRUE. + */ + + movi r18, 1 /* set r18 to the value 'TRUE' */ + 10180cc: 04800044 movi r18,1 + stb r18, %gprel(OSRunning)(gp) /* save this to OSRunning */ + 10180d0: d4a78345 stb r18,-25075(gp) + + /* + * start execution of the new task. + */ + + br 9b + 10180d4: 003fe506 br 101806c + +010180d8 : + +OSStartTsk: + /* This instruction is never executed. Its here to make the + * backtrace work right + */ + movi sp, 0 + 10180d8: 06c00004 movi sp,0 + + /* Enable interrupts */ + rdctl r2, status + 10180dc: 0005303a rdctl r2,status + ori r2, r2, 0x1 + 10180e0: 10800054 ori r2,r2,1 + wrctl status, r2 + 10180e4: 1001703a wrctl status,r2 + + ldw r2, 4(sp) + 10180e8: d8800117 ldw r2,4(sp) + ldw r4, 0(sp) + 10180ec: d9000017 ldw r4,0(sp) + + addi sp, sp, 8 + 10180f0: dec00204 addi sp,sp,8 + + callr r2 + 10180f4: 103ee83a callr r2 + + nop + 10180f8: 0001883a nop + +010180fc : + * been placed on the stack in the proper order. + * + ***********************************************************************************************/ + +OS_STK *OSTaskStkInit(void (*task)(void *pd), void *pdata, OS_STK *pstk, INT16U opt) +{ + 10180fc: defff704 addi sp,sp,-36 + 1018100: dfc00815 stw ra,32(sp) + 1018104: df000715 stw fp,28(sp) + 1018108: df000704 addi fp,sp,28 + 101810c: e13ffc15 stw r4,-16(fp) + 1018110: e17ffd15 stw r5,-12(fp) + 1018114: e1bffe15 stw r6,-8(fp) + 1018118: e1ffff0d sth r7,-4(fp) + * create and initialise the impure pointer used for Newlib thread local storage. + * This is only done if the C library is being used in a thread safe mode. Otherwise + * a single reent structure is used for all threads, which saves memory. + */ + + local_impure_ptr = (struct _reent*)((((INT32U)(pstk)) & ~0x3) - sizeof(struct _reent)); + 101811c: e0bffe17 ldw r2,-8(fp) + 1018120: 1007883a mov r3,r2 + 1018124: 00bfff04 movi r2,-4 + 1018128: 1884703a and r2,r3,r2 + 101812c: 10bf0004 addi r2,r2,-1024 + 1018130: e0bff915 stw r2,-28(fp) + + _REENT_INIT_PTR (local_impure_ptr); + 1018134: e0bff917 ldw r2,-28(fp) + 1018138: 10000015 stw zero,0(r2) + 101813c: e0bff917 ldw r2,-28(fp) + 1018140: 10c0bb04 addi r3,r2,748 + 1018144: e0bff917 ldw r2,-28(fp) + 1018148: 10c00115 stw r3,4(r2) + 101814c: e0bff917 ldw r2,-28(fp) + 1018150: 1080bb04 addi r2,r2,748 + 1018154: 10c01704 addi r3,r2,92 + 1018158: e0bff917 ldw r2,-28(fp) + 101815c: 10c00215 stw r3,8(r2) + 1018160: e0bff917 ldw r2,-28(fp) + 1018164: 1080bb04 addi r2,r2,748 + 1018168: 10c02e04 addi r3,r2,184 + 101816c: e0bff917 ldw r2,-28(fp) + 1018170: 10c00315 stw r3,12(r2) + 1018174: e0bff917 ldw r2,-28(fp) + 1018178: 10000415 stw zero,16(r2) + 101817c: e0bff917 ldw r2,-28(fp) + 1018180: 10800504 addi r2,r2,20 + 1018184: 1009883a mov r4,r2 + 1018188: 01800644 movi r6,25 + 101818c: 000b883a mov r5,zero + 1018190: 1002f1c0 call 1002f1c + 1018194: e0bff917 ldw r2,-28(fp) + 1018198: 10000c15 stw zero,48(r2) + 101819c: e0fff917 ldw r3,-28(fp) + 10181a0: 008040b4 movhi r2,258 + 10181a4: 10a48f04 addi r2,r2,-28100 + 10181a8: 18800d15 stw r2,52(r3) + 10181ac: e0bff917 ldw r2,-28(fp) + 10181b0: 10000e15 stw zero,56(r2) + 10181b4: e0bff917 ldw r2,-28(fp) + 10181b8: 10000f15 stw zero,60(r2) + 10181bc: e0bff917 ldw r2,-28(fp) + 10181c0: 10001015 stw zero,64(r2) + 10181c4: e0bff917 ldw r2,-28(fp) + 10181c8: 10001115 stw zero,68(r2) + 10181cc: e0bff917 ldw r2,-28(fp) + 10181d0: 10001215 stw zero,72(r2) + 10181d4: e0bff917 ldw r2,-28(fp) + 10181d8: 10001315 stw zero,76(r2) + 10181dc: e0bff917 ldw r2,-28(fp) + 10181e0: 10001415 stw zero,80(r2) + 10181e4: e0bff917 ldw r2,-28(fp) + 10181e8: 10001515 stw zero,84(r2) + 10181ec: e0bff917 ldw r2,-28(fp) + 10181f0: 10001615 stw zero,88(r2) + 10181f4: e0bff917 ldw r2,-28(fp) + 10181f8: 10001715 stw zero,92(r2) + 10181fc: e0bff917 ldw r2,-28(fp) + 1018200: 10001805 stb zero,96(r2) + 1018204: e0bff917 ldw r2,-28(fp) + 1018208: 10801f04 addi r2,r2,124 + 101820c: 10000015 stw zero,0(r2) + 1018210: 10000115 stw zero,4(r2) + 1018214: 10000215 stw zero,8(r2) + 1018218: 10000315 stw zero,12(r2) + 101821c: 10000415 stw zero,16(r2) + 1018220: 10000515 stw zero,20(r2) + 1018224: 10000615 stw zero,24(r2) + 1018228: 10000715 stw zero,28(r2) + 101822c: 10000815 stw zero,32(r2) + 1018230: e0bff917 ldw r2,-28(fp) + 1018234: 10002815 stw zero,160(r2) + 1018238: e0fff917 ldw r3,-28(fp) + 101823c: 00800044 movi r2,1 + 1018240: 18802915 stw r2,164(r3) + 1018244: 18002a15 stw zero,168(r3) + 1018248: e0fff917 ldw r3,-28(fp) + 101824c: 008cc384 movi r2,13070 + 1018250: 18802b0d sth r2,172(r3) + 1018254: e0fff917 ldw r3,-28(fp) + 1018258: 00aaf344 movi r2,-21555 + 101825c: 18802b8d sth r2,174(r3) + 1018260: e0fff917 ldw r3,-28(fp) + 1018264: 00848d04 movi r2,4660 + 1018268: 18802c0d sth r2,176(r3) + 101826c: e0fff917 ldw r3,-28(fp) + 1018270: 00b99b44 movi r2,-6547 + 1018274: 18802c8d sth r2,178(r3) + 1018278: e0fff917 ldw r3,-28(fp) + 101827c: 00b7bb04 movi r2,-8468 + 1018280: 18802d0d sth r2,180(r3) + 1018284: e0fff917 ldw r3,-28(fp) + 1018288: 00800144 movi r2,5 + 101828c: 18802d8d sth r2,182(r3) + 1018290: e0fff917 ldw r3,-28(fp) + 1018294: 008002c4 movi r2,11 + 1018298: 18802e0d sth r2,184(r3) + 101829c: e0bff917 ldw r2,-28(fp) + 10182a0: 10002f15 stw zero,188(r2) + 10182a4: e0bff917 ldw r2,-28(fp) + 10182a8: 10003015 stw zero,192(r2) + 10182ac: e0bff917 ldw r2,-28(fp) + 10182b0: 10003115 stw zero,196(r2) + 10182b4: e0bff917 ldw r2,-28(fp) + 10182b8: 10003215 stw zero,200(r2) + 10182bc: e0bff917 ldw r2,-28(fp) + 10182c0: 10003315 stw zero,204(r2) + 10182c4: e0bff917 ldw r2,-28(fp) + 10182c8: 10003415 stw zero,208(r2) + 10182cc: e0bff917 ldw r2,-28(fp) + 10182d0: 10003e15 stw zero,248(r2) + 10182d4: e0bff917 ldw r2,-28(fp) + 10182d8: 10003f15 stw zero,252(r2) + 10182dc: e0bff917 ldw r2,-28(fp) + 10182e0: 10004015 stw zero,256(r2) + 10182e4: e0bff917 ldw r2,-28(fp) + 10182e8: 10004115 stw zero,260(r2) + 10182ec: e0bff917 ldw r2,-28(fp) + 10182f0: 10004215 stw zero,264(r2) + 10182f4: e0bff917 ldw r2,-28(fp) + 10182f8: 10004315 stw zero,268(r2) + 10182fc: e0bff917 ldw r2,-28(fp) + 1018300: 10004415 stw zero,272(r2) + 1018304: e0bff917 ldw r2,-28(fp) + 1018308: 10004515 stw zero,276(r2) + 101830c: e0bff917 ldw r2,-28(fp) + 1018310: 10004615 stw zero,280(r2) + 1018314: e0bff917 ldw r2,-28(fp) + 1018318: 10004715 stw zero,284(r2) + 101831c: e0bff917 ldw r2,-28(fp) + 1018320: 10003505 stb zero,212(r2) + 1018324: e0bff917 ldw r2,-28(fp) + 1018328: 10003705 stb zero,220(r2) + 101832c: e0bff917 ldw r2,-28(fp) + 1018330: 10003d15 stw zero,244(r2) + 1018334: e0bff917 ldw r2,-28(fp) + 1018338: 10005215 stw zero,328(r2) + 101833c: e0bff917 ldw r2,-28(fp) + 1018340: 10005315 stw zero,332(r2) + 1018344: e0bff917 ldw r2,-28(fp) + 1018348: 10005415 stw zero,336(r2) + 101834c: e0bff917 ldw r2,-28(fp) + 1018350: 10005515 stw zero,340(r2) + 1018354: e0bff917 ldw r2,-28(fp) + 1018358: 1000b515 stw zero,724(r2) + 101835c: e0bff917 ldw r2,-28(fp) + 1018360: 10007515 stw zero,468(r2) + 1018364: e0bff917 ldw r2,-28(fp) + 1018368: 1000b715 stw zero,732(r2) + 101836c: e0bff917 ldw r2,-28(fp) + 1018370: 1000b815 stw zero,736(r2) + 1018374: e0bff917 ldw r2,-28(fp) + 1018378: 1000b915 stw zero,740(r2) + 101837c: e0bff917 ldw r2,-28(fp) + 1018380: 1000ba15 stw zero,744(r2) + 1018384: e0bff917 ldw r2,-28(fp) + 1018388: 1080bb04 addi r2,r2,748 + 101838c: 1009883a mov r4,r2 + 1018390: 01804504 movi r6,276 + 1018394: 000b883a mov r5,zero + 1018398: 1002f1c0 call 1002f1c + /* + * create a stack frame at the top of the stack (leaving space for the + * reentrant data structure). + */ + + frame_pointer = (INT32U*) local_impure_ptr; + 101839c: e0bff917 ldw r2,-28(fp) + 10183a0: e0bffb15 stw r2,-20(fp) +#else + frame_pointer = (INT32U*) (((INT32U)(pstk)) & ~0x3); +#endif /* OS_THREAD_SAFE_NEWLIB */ + stk = frame_pointer - 13; + 10183a4: e0bffb17 ldw r2,-20(fp) + 10183a8: 10bff304 addi r2,r2,-52 + 10183ac: e0bffa15 stw r2,-24(fp) + + /* Now fill the stack frame. */ + + stk[12] = (INT32U)task; /* task address (ra) */ + 10183b0: e0bffa17 ldw r2,-24(fp) + 10183b4: 10c00c04 addi r3,r2,48 + 10183b8: e0bffc17 ldw r2,-16(fp) + 10183bc: 18800015 stw r2,0(r3) + stk[11] = (INT32U) pdata; /* first register argument (r4) */ + 10183c0: e0bffa17 ldw r2,-24(fp) + 10183c4: 10c00b04 addi r3,r2,44 + 10183c8: e0bffd17 ldw r2,-12(fp) + 10183cc: 18800015 stw r2,0(r3) + +#if OS_THREAD_SAFE_NEWLIB + stk[10] = (INT32U) local_impure_ptr; /* value of _impure_ptr for this thread */ + 10183d0: e0bffa17 ldw r2,-24(fp) + 10183d4: 10c00a04 addi r3,r2,40 + 10183d8: e0bff917 ldw r2,-28(fp) + 10183dc: 18800015 stw r2,0(r3) +#endif /* OS_THREAD_SAFE_NEWLIB */ + stk[0] = ((INT32U)&OSStartTsk) + 4;/* exception return address (ea) */ + 10183e0: 008040b4 movhi r2,258 + 10183e4: 10a03604 addi r2,r2,-32552 + 10183e8: 10c00104 addi r3,r2,4 + 10183ec: e0bffa17 ldw r2,-24(fp) + 10183f0: 10c00015 stw r3,0(r2) + */ + __asm__ (".set OSTCBNext_OFFSET,%0" :: "i" (offsetof(OS_TCB, OSTCBNext))); + __asm__ (".set OSTCBPrio_OFFSET,%0" :: "i" (offsetof(OS_TCB, OSTCBPrio))); + __asm__ (".set OSTCBStkPtr_OFFSET,%0" :: "i" (offsetof(OS_TCB, OSTCBStkPtr))); + + return((OS_STK *)stk); + 10183f4: e0bffa17 ldw r2,-24(fp) +} + 10183f8: e037883a mov sp,fp + 10183fc: dfc00117 ldw ra,4(sp) + 1018400: df000017 ldw fp,0(sp) + 1018404: dec00204 addi sp,sp,8 + 1018408: f800283a ret + +0101840c : +* +* Note(s) : 1) Interrupts are disabled during this call. +********************************************************************************************************* +*/ +void OSTaskCreateHook (OS_TCB *ptcb) +{ + 101840c: defffe04 addi sp,sp,-8 + 1018410: df000115 stw fp,4(sp) + 1018414: df000104 addi fp,sp,4 + 1018418: e13fff15 stw r4,-4(fp) + ptcb = ptcb; /* Prevent compiler warning */ +} + 101841c: e037883a mov sp,fp + 1018420: df000017 ldw fp,0(sp) + 1018424: dec00104 addi sp,sp,4 + 1018428: f800283a ret + +0101842c : +* +* Note(s) : 1) Interrupts are disabled during this call. +********************************************************************************************************* +*/ +void OSTaskDelHook (OS_TCB *ptcb) +{ + 101842c: defffe04 addi sp,sp,-8 + 1018430: df000115 stw fp,4(sp) + 1018434: df000104 addi fp,sp,4 + 1018438: e13fff15 stw r4,-4(fp) + ptcb = ptcb; /* Prevent compiler warning */ +} + 101843c: e037883a mov sp,fp + 1018440: df000017 ldw fp,0(sp) + 1018444: dec00104 addi sp,sp,4 + 1018448: f800283a ret + +0101844c : +* will be 'switched in' (i.e. the highest priority task) and, 'OSTCBCur' points to the +* task being switched out (i.e. the preempted task). +********************************************************************************************************* +*/ +void OSTaskSwHook (void) +{ + 101844c: deffff04 addi sp,sp,-4 + 1018450: df000015 stw fp,0(sp) + 1018454: d839883a mov fp,sp +} + 1018458: e037883a mov sp,fp + 101845c: df000017 ldw fp,0(sp) + 1018460: dec00104 addi sp,sp,4 + 1018464: f800283a ret + +01018468 : +* +* Arguments : none +********************************************************************************************************* +*/ +void OSTaskStatHook (void) +{ + 1018468: deffff04 addi sp,sp,-4 + 101846c: df000015 stw fp,0(sp) + 1018470: d839883a mov fp,sp +} + 1018474: e037883a mov sp,fp + 1018478: df000017 ldw fp,0(sp) + 101847c: dec00104 addi sp,sp,4 + 1018480: f800283a ret + +01018484 : +#ifdef ALT_INICHE +void cticks_hook(void); +#endif + +void OSTimeTickHook (void) +{ + 1018484: deffff04 addi sp,sp,-4 + 1018488: df000015 stw fp,0(sp) + 101848c: d839883a mov fp,sp + +#ifdef ALT_INICHE + /* Service the Interniche timer */ + cticks_hook(); +#endif +} + 1018490: e037883a mov sp,fp + 1018494: df000017 ldw fp,0(sp) + 1018498: dec00104 addi sp,sp,4 + 101849c: f800283a ret + +010184a0 : + +void OSInitHookBegin(void) +{ + 10184a0: deffff04 addi sp,sp,-4 + 10184a4: df000015 stw fp,0(sp) + 10184a8: d839883a mov fp,sp +#if OS_TMR_EN > 0 + OSTmrCtr = 0; +#endif +} + 10184ac: e037883a mov sp,fp + 10184b0: df000017 ldw fp,0(sp) + 10184b4: dec00104 addi sp,sp,4 + 10184b8: f800283a ret + +010184bc : + +void OSInitHookEnd(void) +{ + 10184bc: deffff04 addi sp,sp,-4 + 10184c0: df000015 stw fp,0(sp) + 10184c4: d839883a mov fp,sp +} + 10184c8: e037883a mov sp,fp + 10184cc: df000017 ldw fp,0(sp) + 10184d0: dec00104 addi sp,sp,4 + 10184d4: f800283a ret + +010184d8 : + +void OSTaskIdleHook(void) +{ + 10184d8: deffff04 addi sp,sp,-4 + 10184dc: df000015 stw fp,0(sp) + 10184e0: d839883a mov fp,sp +} + 10184e4: e037883a mov sp,fp + 10184e8: df000017 ldw fp,0(sp) + 10184ec: dec00104 addi sp,sp,4 + 10184f0: f800283a ret + +010184f4 : + +void OSTCBInitHook(OS_TCB *ptcb) +{ + 10184f4: defffe04 addi sp,sp,-8 + 10184f8: df000115 stw fp,4(sp) + 10184fc: df000104 addi fp,sp,4 + 1018500: e13fff15 stw r4,-4(fp) +} + 1018504: e037883a mov sp,fp + 1018508: df000017 ldw fp,0(sp) + 101850c: dec00104 addi sp,sp,4 + 1018510: f800283a ret + +01018514 : + * either '/' or '\0' is the prefix of the filename. For example the filename: + * "/myfilesystem/junk.txt" would match: "/myfilesystem", but not: "/myfile". + */ + +alt_dev* alt_find_file (const char* name) +{ + 1018514: defffa04 addi sp,sp,-24 + 1018518: dfc00515 stw ra,20(sp) + 101851c: df000415 stw fp,16(sp) + 1018520: df000404 addi fp,sp,16 + 1018524: e13ffe15 stw r4,-8(fp) + alt_dev* next = (alt_dev*) alt_fs_list.next; + 1018528: 008040b4 movhi r2,258 + 101852c: 10ab9c04 addi r2,r2,-20880 + 1018530: 10800017 ldw r2,0(r2) + 1018534: e0bffd15 stw r2,-12(fp) + /* + * Check each list entry in turn, until a match is found, or we reach the + * end of the list (i.e. next winds up pointing back to the list head). + */ + + while (next != (alt_dev*) &alt_fs_list) + 1018538: 00003306 br 1018608 + { + len = strlen(next->name); + 101853c: e0bffd17 ldw r2,-12(fp) + 1018540: 11000217 ldw r4,8(r2) + 1018544: 10034a00 call 10034a0 + 1018548: e0bffc15 stw r2,-16(fp) + + if (next->name[len-1] == '/') + 101854c: e0bffd17 ldw r2,-12(fp) + 1018550: 10c00217 ldw r3,8(r2) + 1018554: e0bffc17 ldw r2,-16(fp) + 1018558: 1885883a add r2,r3,r2 + 101855c: 10bfffc4 addi r2,r2,-1 + 1018560: 10800003 ldbu r2,0(r2) + 1018564: 10803fcc andi r2,r2,255 + 1018568: 1080201c xori r2,r2,128 + 101856c: 10bfe004 addi r2,r2,-128 + 1018570: 10800bd8 cmpnei r2,r2,47 + 1018574: 1000031e bne r2,zero,1018584 + { + len -= 1; + 1018578: e0bffc17 ldw r2,-16(fp) + 101857c: 10bfffc4 addi r2,r2,-1 + 1018580: e0bffc15 stw r2,-16(fp) + } + + if (((name[len] == '/') || (name[len] == '\0')) && + 1018584: e0bffc17 ldw r2,-16(fp) + 1018588: 1007883a mov r3,r2 + 101858c: e0bffe17 ldw r2,-8(fp) + 1018590: 1885883a add r2,r3,r2 + 1018594: 10800003 ldbu r2,0(r2) + 1018598: 10803fcc andi r2,r2,255 + 101859c: 1080201c xori r2,r2,128 + 10185a0: 10bfe004 addi r2,r2,-128 + 10185a4: 10800be0 cmpeqi r2,r2,47 + 10185a8: 10000a1e bne r2,zero,10185d4 + 10185ac: e0bffc17 ldw r2,-16(fp) + 10185b0: 1007883a mov r3,r2 + 10185b4: e0bffe17 ldw r2,-8(fp) + 10185b8: 1885883a add r2,r3,r2 + 10185bc: 10800003 ldbu r2,0(r2) + 10185c0: 10803fcc andi r2,r2,255 + 10185c4: 1080201c xori r2,r2,128 + 10185c8: 10bfe004 addi r2,r2,-128 + 10185cc: 1004c03a cmpne r2,r2,zero + 10185d0: 10000a1e bne r2,zero,10185fc + 10185d4: e0bffd17 ldw r2,-12(fp) + 10185d8: 11000217 ldw r4,8(r2) + 10185dc: e1bffc17 ldw r6,-16(fp) + 10185e0: e17ffe17 ldw r5,-8(fp) + 10185e4: 10188040 call 1018804 + 10185e8: 1004c03a cmpne r2,r2,zero + 10185ec: 1000031e bne r2,zero,10185fc + !memcmp (next->name, name, len)) + { + /* match found */ + + return next; + 10185f0: e0bffd17 ldw r2,-12(fp) + 10185f4: e0bfff15 stw r2,-4(fp) + 10185f8: 00000806 br 101861c + } + next = (alt_dev*) next->llist.next; + 10185fc: e0bffd17 ldw r2,-12(fp) + 1018600: 10800017 ldw r2,0(r2) + 1018604: e0bffd15 stw r2,-12(fp) + /* + * Check each list entry in turn, until a match is found, or we reach the + * end of the list (i.e. next winds up pointing back to the list head). + */ + + while (next != (alt_dev*) &alt_fs_list) + 1018608: 00c040b4 movhi r3,258 + 101860c: 18eb9c04 addi r3,r3,-20880 + 1018610: e0bffd17 ldw r2,-12(fp) + 1018614: 10ffc91e bne r2,r3,101853c + next = (alt_dev*) next->llist.next; + } + + /* No match found */ + + return NULL; + 1018618: e03fff15 stw zero,-4(fp) + 101861c: e0bfff17 ldw r2,-4(fp) +} + 1018620: e037883a mov sp,fp + 1018624: dfc00117 ldw ra,4(sp) + 1018628: df000017 ldw fp,0(sp) + 101862c: dec00204 addi sp,sp,8 + 1018630: f800283a ret + +01018634 : + * the offset of the file descriptor within the file descriptor array). A + * negative value indicates failure. + */ + +int alt_get_fd (alt_dev* dev) +{ + 1018634: defff804 addi sp,sp,-32 + 1018638: dfc00715 stw ra,28(sp) + 101863c: df000615 stw fp,24(sp) + 1018640: df000604 addi fp,sp,24 + 1018644: e13fff15 stw r4,-4(fp) + alt_32 i; + int rc = -EMFILE; + 1018648: 00bffa04 movi r2,-24 + 101864c: e0bffc15 stw r2,-16(fp) + /* + * Take the alt_fd_list_lock semaphore in order to avoid races when + * accessing the file descriptor pool. + */ + + ALT_SEM_PEND(alt_fd_list_lock, 0); + 1018650: 008040b4 movhi r2,258 + 1018654: 10b30804 addi r2,r2,-13280 + 1018658: 10800017 ldw r2,0(r2) + 101865c: e0bffa15 stw r2,-24(fp) + 1018660: e03ffb0d sth zero,-20(fp) + 1018664: e17ffb0b ldhu r5,-20(fp) + 1018668: e1bffe04 addi r6,fp,-8 + 101866c: e13ffa17 ldw r4,-24(fp) + 1018670: 1012e180 call 1012e18 + * indicates the highest file descriptor ever allocated. This is used to + * improve efficency when searching the file descriptor list, and + * therefore reduce contention on the alt_fd_list_lock semaphore. + */ + + for (i = 0; i < ALT_MAX_FD; i++) + 1018674: e03ffd15 stw zero,-12(fp) + 1018678: 00001e06 br 10186f4 + { + if (!alt_fd_list[i].dev) + 101867c: e0bffd17 ldw r2,-12(fp) + 1018680: 00c040b4 movhi r3,258 + 1018684: 18e69f04 addi r3,r3,-25988 + 1018688: 10800324 muli r2,r2,12 + 101868c: 10c5883a add r2,r2,r3 + 1018690: 10800017 ldw r2,0(r2) + 1018694: 1004c03a cmpne r2,r2,zero + 1018698: 1000131e bne r2,zero,10186e8 + { + alt_fd_list[i].dev = dev; + 101869c: e0bffd17 ldw r2,-12(fp) + 10186a0: 00c040b4 movhi r3,258 + 10186a4: 18e69f04 addi r3,r3,-25988 + 10186a8: 10800324 muli r2,r2,12 + 10186ac: 10c7883a add r3,r2,r3 + 10186b0: e0bfff17 ldw r2,-4(fp) + 10186b4: 18800015 stw r2,0(r3) + if (i > alt_max_fd) + 10186b8: 008040b4 movhi r2,258 + 10186bc: 10aba004 addi r2,r2,-20864 + 10186c0: 10c00017 ldw r3,0(r2) + 10186c4: e0bffd17 ldw r2,-12(fp) + 10186c8: 1880040e bge r3,r2,10186dc + { + alt_max_fd = i; + 10186cc: 00c040b4 movhi r3,258 + 10186d0: 18eba004 addi r3,r3,-20864 + 10186d4: e0bffd17 ldw r2,-12(fp) + 10186d8: 18800015 stw r2,0(r3) + } + rc = i; + 10186dc: e0bffd17 ldw r2,-12(fp) + 10186e0: e0bffc15 stw r2,-16(fp) + goto alt_get_fd_exit; + 10186e4: 00000606 br 1018700 + * indicates the highest file descriptor ever allocated. This is used to + * improve efficency when searching the file descriptor list, and + * therefore reduce contention on the alt_fd_list_lock semaphore. + */ + + for (i = 0; i < ALT_MAX_FD; i++) + 10186e8: e0bffd17 ldw r2,-12(fp) + 10186ec: 10800044 addi r2,r2,1 + 10186f0: e0bffd15 stw r2,-12(fp) + 10186f4: e0bffd17 ldw r2,-12(fp) + 10186f8: 10800810 cmplti r2,r2,32 + 10186fc: 103fdf1e bne r2,zero,101867c + /* + * Release the alt_fd_list_lock semaphore now that we are done with the + * file descriptor pool. + */ + + ALT_SEM_POST(alt_fd_list_lock); + 1018700: 008040b4 movhi r2,258 + 1018704: 10b30804 addi r2,r2,-13280 + 1018708: 11000017 ldw r4,0(r2) + 101870c: 10132100 call 1013210 + + return rc; + 1018710: e0bffc17 ldw r2,-16(fp) +} + 1018714: e037883a mov sp,fp + 1018718: dfc00117 ldw ra,4(sp) + 101871c: df000017 ldw fp,0(sp) + 1018720: dec00204 addi sp,sp,8 + 1018724: f800283a ret + +01018728 : + * alt_icache_flush() is called to flush the instruction cache for a memory + * region of length "len" bytes, starting at address "start". + */ + +void alt_icache_flush (void* start, alt_u32 len) +{ + 1018728: defffb04 addi sp,sp,-20 + 101872c: df000415 stw fp,16(sp) + 1018730: df000404 addi fp,sp,16 + 1018734: e13ffe15 stw r4,-8(fp) + 1018738: e17fff15 stw r5,-4(fp) + + /* + * This is the most we would ever need to flush. + */ + + if (len > NIOS2_ICACHE_SIZE) + 101873c: e0bfff17 ldw r2,-4(fp) + 1018740: 10880070 cmpltui r2,r2,8193 + 1018744: 1000021e bne r2,zero,1018750 + { + len = NIOS2_ICACHE_SIZE; + 1018748: 00880004 movi r2,8192 + 101874c: e0bfff15 stw r2,-4(fp) + } + + end = ((char*) start) + len; + 1018750: e0fffe17 ldw r3,-8(fp) + 1018754: e0bfff17 ldw r2,-4(fp) + 1018758: 1885883a add r2,r3,r2 + 101875c: e0bffc15 stw r2,-16(fp) + + for (i = start; i < end; i+= NIOS2_ICACHE_LINE_SIZE) + 1018760: e0bffe17 ldw r2,-8(fp) + 1018764: e0bffd15 stw r2,-12(fp) + 1018768: 00000506 br 1018780 + { + __asm__ volatile ("flushi %0" :: "r" (i)); + 101876c: e0bffd17 ldw r2,-12(fp) + 1018770: 1000603a flushi r2 + len = NIOS2_ICACHE_SIZE; + } + + end = ((char*) start) + len; + + for (i = start; i < end; i+= NIOS2_ICACHE_LINE_SIZE) + 1018774: e0bffd17 ldw r2,-12(fp) + 1018778: 10800804 addi r2,r2,32 + 101877c: e0bffd15 stw r2,-12(fp) + 1018780: e0fffd17 ldw r3,-12(fp) + 1018784: e0bffc17 ldw r2,-16(fp) + 1018788: 18bff836 bltu r3,r2,101876c + * For an unaligned flush request, we've got one more line left. + * Note that this is dependent on NIOS2_ICACHE_LINE_SIZE to be a + * multiple of 2 (which it always is). + */ + + if (((alt_u32) start) & (NIOS2_ICACHE_LINE_SIZE - 1)) + 101878c: e0bffe17 ldw r2,-8(fp) + 1018790: 108007cc andi r2,r2,31 + 1018794: 1005003a cmpeq r2,r2,zero + 1018798: 1000021e bne r2,zero,10187a4 + { + __asm__ volatile ("flushi %0" :: "r" (i)); + 101879c: e0bffd17 ldw r2,-12(fp) + 10187a0: 1000603a flushi r2 + /* + * Having flushed the cache, flush any stale instructions in the + * pipeline + */ + + __asm__ volatile ("flushp"); + 10187a4: 0000203a flushp + +#endif /* NIOS2_ICACHE_SIZE > 0 */ +} + 10187a8: e037883a mov sp,fp + 10187ac: df000017 ldw fp,0(sp) + 10187b0: dec00104 addi sp,sp,4 + 10187b4: f800283a ret + +010187b8 : + 10187b8: 200b883a mov r5,r4 + 10187bc: 000d883a mov r6,zero + 10187c0: 0009883a mov r4,zero + 10187c4: 000f883a mov r7,zero + 10187c8: 10188781 jmpi 1018878 <__register_exitproc> + +010187cc : + 10187cc: defffe04 addi sp,sp,-8 + 10187d0: 000b883a mov r5,zero + 10187d4: dc000015 stw r16,0(sp) + 10187d8: dfc00115 stw ra,4(sp) + 10187dc: 2021883a mov r16,r4 + 10187e0: 10189b00 call 10189b0 <__call_exitprocs> + 10187e4: 008040b4 movhi r2,258 + 10187e8: 10ab9904 addi r2,r2,-20892 + 10187ec: 11000017 ldw r4,0(r2) + 10187f0: 20800f17 ldw r2,60(r4) + 10187f4: 10000126 beq r2,zero,10187fc + 10187f8: 103ee83a callr r2 + 10187fc: 8009883a mov r4,r16 + 1018800: 100c4380 call 100c438 <_exit> + +01018804 : + 1018804: 00c000c4 movi r3,3 + 1018808: 1980032e bgeu r3,r6,1018818 + 101880c: 2144b03a or r2,r4,r5 + 1018810: 10c4703a and r2,r2,r3 + 1018814: 10000f26 beq r2,zero,1018854 + 1018818: 31ffffc4 addi r7,r6,-1 + 101881c: 3000061e bne r6,zero,1018838 + 1018820: 00000a06 br 101884c + 1018824: 39ffffc4 addi r7,r7,-1 + 1018828: 00bfffc4 movi r2,-1 + 101882c: 21000044 addi r4,r4,1 + 1018830: 29400044 addi r5,r5,1 + 1018834: 38800526 beq r7,r2,101884c + 1018838: 20c00003 ldbu r3,0(r4) + 101883c: 28800003 ldbu r2,0(r5) + 1018840: 18bff826 beq r3,r2,1018824 + 1018844: 1885c83a sub r2,r3,r2 + 1018848: f800283a ret + 101884c: 0005883a mov r2,zero + 1018850: f800283a ret + 1018854: 180f883a mov r7,r3 + 1018858: 20c00017 ldw r3,0(r4) + 101885c: 28800017 ldw r2,0(r5) + 1018860: 18bfed1e bne r3,r2,1018818 + 1018864: 31bfff04 addi r6,r6,-4 + 1018868: 21000104 addi r4,r4,4 + 101886c: 29400104 addi r5,r5,4 + 1018870: 39bff936 bltu r7,r6,1018858 + 1018874: 003fe806 br 1018818 + +01018878 <__register_exitproc>: + 1018878: defffa04 addi sp,sp,-24 + 101887c: 008040b4 movhi r2,258 + 1018880: 10ab9904 addi r2,r2,-20892 + 1018884: dc000015 stw r16,0(sp) + 1018888: 14000017 ldw r16,0(r2) + 101888c: dd000415 stw r20,16(sp) + 1018890: 2829883a mov r20,r5 + 1018894: 81405217 ldw r5,328(r16) + 1018898: dcc00315 stw r19,12(sp) + 101889c: dc800215 stw r18,8(sp) + 10188a0: dc400115 stw r17,4(sp) + 10188a4: dfc00515 stw ra,20(sp) + 10188a8: 2023883a mov r17,r4 + 10188ac: 3027883a mov r19,r6 + 10188b0: 3825883a mov r18,r7 + 10188b4: 28002526 beq r5,zero,101894c <__register_exitproc+0xd4> + 10188b8: 29000117 ldw r4,4(r5) + 10188bc: 008007c4 movi r2,31 + 10188c0: 11002716 blt r2,r4,1018960 <__register_exitproc+0xe8> + 10188c4: 8800101e bne r17,zero,1018908 <__register_exitproc+0x90> + 10188c8: 2105883a add r2,r4,r4 + 10188cc: 1085883a add r2,r2,r2 + 10188d0: 20c00044 addi r3,r4,1 + 10188d4: 1145883a add r2,r2,r5 + 10188d8: 0009883a mov r4,zero + 10188dc: 15000215 stw r20,8(r2) + 10188e0: 28c00115 stw r3,4(r5) + 10188e4: 2005883a mov r2,r4 + 10188e8: dfc00517 ldw ra,20(sp) + 10188ec: dd000417 ldw r20,16(sp) + 10188f0: dcc00317 ldw r19,12(sp) + 10188f4: dc800217 ldw r18,8(sp) + 10188f8: dc400117 ldw r17,4(sp) + 10188fc: dc000017 ldw r16,0(sp) + 1018900: dec00604 addi sp,sp,24 + 1018904: f800283a ret + 1018908: 29802204 addi r6,r5,136 + 101890c: 00800044 movi r2,1 + 1018910: 110e983a sll r7,r2,r4 + 1018914: 30c04017 ldw r3,256(r6) + 1018918: 2105883a add r2,r4,r4 + 101891c: 1085883a add r2,r2,r2 + 1018920: 1185883a add r2,r2,r6 + 1018924: 19c6b03a or r3,r3,r7 + 1018928: 14802015 stw r18,128(r2) + 101892c: 14c00015 stw r19,0(r2) + 1018930: 00800084 movi r2,2 + 1018934: 30c04015 stw r3,256(r6) + 1018938: 88bfe31e bne r17,r2,10188c8 <__register_exitproc+0x50> + 101893c: 30804117 ldw r2,260(r6) + 1018940: 11c4b03a or r2,r2,r7 + 1018944: 30804115 stw r2,260(r6) + 1018948: 003fdf06 br 10188c8 <__register_exitproc+0x50> + 101894c: 008040b4 movhi r2,258 + 1018950: 1099fe04 addi r2,r2,26616 + 1018954: 100b883a mov r5,r2 + 1018958: 80805215 stw r2,328(r16) + 101895c: 003fd606 br 10188b8 <__register_exitproc+0x40> + 1018960: 00804034 movhi r2,256 + 1018964: 1089f204 addi r2,r2,10184 + 1018968: 1000021e bne r2,zero,1018974 <__register_exitproc+0xfc> + 101896c: 013fffc4 movi r4,-1 + 1018970: 003fdc06 br 10188e4 <__register_exitproc+0x6c> + 1018974: 01006404 movi r4,400 + 1018978: 103ee83a callr r2 + 101897c: 1007883a mov r3,r2 + 1018980: 103ffa26 beq r2,zero,101896c <__register_exitproc+0xf4> + 1018984: 80805217 ldw r2,328(r16) + 1018988: 180b883a mov r5,r3 + 101898c: 18000115 stw zero,4(r3) + 1018990: 18800015 stw r2,0(r3) + 1018994: 80c05215 stw r3,328(r16) + 1018998: 18006215 stw zero,392(r3) + 101899c: 18006315 stw zero,396(r3) + 10189a0: 0009883a mov r4,zero + 10189a4: 883fc826 beq r17,zero,10188c8 <__register_exitproc+0x50> + 10189a8: 003fd706 br 1018908 <__register_exitproc+0x90> + +010189ac : + 10189ac: f800283a ret + +010189b0 <__call_exitprocs>: + 10189b0: 008040b4 movhi r2,258 + 10189b4: 10ab9904 addi r2,r2,-20892 + 10189b8: 10800017 ldw r2,0(r2) + 10189bc: defff304 addi sp,sp,-52 + 10189c0: df000b15 stw fp,44(sp) + 10189c4: d8800115 stw r2,4(sp) + 10189c8: 00804034 movhi r2,256 + 10189cc: 1089ed04 addi r2,r2,10164 + 10189d0: 1005003a cmpeq r2,r2,zero + 10189d4: d8800215 stw r2,8(sp) + 10189d8: d8800117 ldw r2,4(sp) + 10189dc: dd400815 stw r21,32(sp) + 10189e0: dd000715 stw r20,28(sp) + 10189e4: 10805204 addi r2,r2,328 + 10189e8: dfc00c15 stw ra,48(sp) + 10189ec: ddc00a15 stw r23,40(sp) + 10189f0: dd800915 stw r22,36(sp) + 10189f4: dcc00615 stw r19,24(sp) + 10189f8: dc800515 stw r18,20(sp) + 10189fc: dc400415 stw r17,16(sp) + 1018a00: dc000315 stw r16,12(sp) + 1018a04: 282b883a mov r21,r5 + 1018a08: 2039883a mov fp,r4 + 1018a0c: d8800015 stw r2,0(sp) + 1018a10: 2829003a cmpeq r20,r5,zero + 1018a14: d8800117 ldw r2,4(sp) + 1018a18: 14405217 ldw r17,328(r2) + 1018a1c: 88001026 beq r17,zero,1018a60 <__call_exitprocs+0xb0> + 1018a20: ddc00017 ldw r23,0(sp) + 1018a24: 88800117 ldw r2,4(r17) + 1018a28: 8c802204 addi r18,r17,136 + 1018a2c: 143fffc4 addi r16,r2,-1 + 1018a30: 80000916 blt r16,zero,1018a58 <__call_exitprocs+0xa8> + 1018a34: 05bfffc4 movi r22,-1 + 1018a38: a000151e bne r20,zero,1018a90 <__call_exitprocs+0xe0> + 1018a3c: 8409883a add r4,r16,r16 + 1018a40: 2105883a add r2,r4,r4 + 1018a44: 1485883a add r2,r2,r18 + 1018a48: 10c02017 ldw r3,128(r2) + 1018a4c: a8c01126 beq r21,r3,1018a94 <__call_exitprocs+0xe4> + 1018a50: 843fffc4 addi r16,r16,-1 + 1018a54: 85bff81e bne r16,r22,1018a38 <__call_exitprocs+0x88> + 1018a58: d8800217 ldw r2,8(sp) + 1018a5c: 10003126 beq r2,zero,1018b24 <__call_exitprocs+0x174> + 1018a60: dfc00c17 ldw ra,48(sp) + 1018a64: df000b17 ldw fp,44(sp) + 1018a68: ddc00a17 ldw r23,40(sp) + 1018a6c: dd800917 ldw r22,36(sp) + 1018a70: dd400817 ldw r21,32(sp) + 1018a74: dd000717 ldw r20,28(sp) + 1018a78: dcc00617 ldw r19,24(sp) + 1018a7c: dc800517 ldw r18,20(sp) + 1018a80: dc400417 ldw r17,16(sp) + 1018a84: dc000317 ldw r16,12(sp) + 1018a88: dec00d04 addi sp,sp,52 + 1018a8c: f800283a ret + 1018a90: 8409883a add r4,r16,r16 + 1018a94: 88c00117 ldw r3,4(r17) + 1018a98: 2105883a add r2,r4,r4 + 1018a9c: 1445883a add r2,r2,r17 + 1018aa0: 18ffffc4 addi r3,r3,-1 + 1018aa4: 11800217 ldw r6,8(r2) + 1018aa8: 1c001526 beq r3,r16,1018b00 <__call_exitprocs+0x150> + 1018aac: 10000215 stw zero,8(r2) + 1018ab0: 303fe726 beq r6,zero,1018a50 <__call_exitprocs+0xa0> + 1018ab4: 00c00044 movi r3,1 + 1018ab8: 1c06983a sll r3,r3,r16 + 1018abc: 90804017 ldw r2,256(r18) + 1018ac0: 8cc00117 ldw r19,4(r17) + 1018ac4: 1884703a and r2,r3,r2 + 1018ac8: 10001426 beq r2,zero,1018b1c <__call_exitprocs+0x16c> + 1018acc: 90804117 ldw r2,260(r18) + 1018ad0: 1884703a and r2,r3,r2 + 1018ad4: 10000c1e bne r2,zero,1018b08 <__call_exitprocs+0x158> + 1018ad8: 2105883a add r2,r4,r4 + 1018adc: 1485883a add r2,r2,r18 + 1018ae0: 11400017 ldw r5,0(r2) + 1018ae4: e009883a mov r4,fp + 1018ae8: 303ee83a callr r6 + 1018aec: 88800117 ldw r2,4(r17) + 1018af0: 98bfc81e bne r19,r2,1018a14 <__call_exitprocs+0x64> + 1018af4: b8800017 ldw r2,0(r23) + 1018af8: 147fd526 beq r2,r17,1018a50 <__call_exitprocs+0xa0> + 1018afc: 003fc506 br 1018a14 <__call_exitprocs+0x64> + 1018b00: 8c000115 stw r16,4(r17) + 1018b04: 003fea06 br 1018ab0 <__call_exitprocs+0x100> + 1018b08: 2105883a add r2,r4,r4 + 1018b0c: 1485883a add r2,r2,r18 + 1018b10: 11000017 ldw r4,0(r2) + 1018b14: 303ee83a callr r6 + 1018b18: 003ff406 br 1018aec <__call_exitprocs+0x13c> + 1018b1c: 303ee83a callr r6 + 1018b20: 003ff206 br 1018aec <__call_exitprocs+0x13c> + 1018b24: 88800117 ldw r2,4(r17) + 1018b28: 1000081e bne r2,zero,1018b4c <__call_exitprocs+0x19c> + 1018b2c: 89000017 ldw r4,0(r17) + 1018b30: 20000726 beq r4,zero,1018b50 <__call_exitprocs+0x1a0> + 1018b34: b9000015 stw r4,0(r23) + 1018b38: 8809883a mov r4,r17 + 1018b3c: 10027b40 call 10027b4 + 1018b40: bc400017 ldw r17,0(r23) + 1018b44: 883fb71e bne r17,zero,1018a24 <__call_exitprocs+0x74> + 1018b48: 003fc506 br 1018a60 <__call_exitprocs+0xb0> + 1018b4c: 89000017 ldw r4,0(r17) + 1018b50: 882f883a mov r23,r17 + 1018b54: 2023883a mov r17,r4 + 1018b58: 883fb21e bne r17,zero,1018a24 <__call_exitprocs+0x74> + 1018b5c: 003fc006 br 1018a60 <__call_exitprocs+0xb0> + 1018b60: 0201ffff 0x201ffff + 1018b64: 883a0000 call 883a000 <__alt_data_end+0x683a000> + 1018b68: 010d0bff 0x10d0bff + 1018b6c: 01000004 movi r4,0 + 1018b70: 00000101 jmpi 10 + 1018b74: 00000000 call 0 + 1018b78: 010d0bff 0x10d0bff + 1018b7c: 01000004 movi r4,0 + 1018b80: 00000101 jmpi 10 + 1018b84: 00000000 call 0 + 1018b88: 010d0bff 0x10d0bff + 1018b8c: 01000004 movi r4,0 + 1018b90: 00000101 jmpi 10 + 1018b94: 00000000 call 0 + 1018b98: 01090bff 0x1090bff + 1018b9c: 7f010002 0x7f010002 + ... + 1018ba8: 01090bff 0x1090bff + 1018bac: 7f010002 0x7f010002 + ... + 1018bb8: 010d0bff 0x10d0bff + 1018bbc: 7f010002 0x7f010002 + 1018bc0: 00000000 call 0 + 1018bc4: 01018d9c xori r4,zero,1590 + 1018bc8: 00000001 jmpi 0 + 1018bcc: 01000704 movi r4,28 + 1018bd0: 010189ac andhi r4,zero,1574 diff --git a/MCandWifiTestDE0/Software/MCTest/Makefile b/MCandWifiTestDE0/Software/MCTest/Makefile new file mode 100644 index 00000000..9e1d6dc7 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest/Makefile @@ -0,0 +1,1087 @@ +#------------------------------------------------------------------------------ +# VARIABLES APPENDED TO BY INCLUDED MAKEFILE FRAGMENTS +#------------------------------------------------------------------------------ + +# List of include directories for -I compiler option (-I added when used). +# Includes the BSP. +ALT_INCLUDE_DIRS := + +# List of library directories for -L linker option (-L added when used). +# Includes the BSP. +ALT_LIBRARY_DIRS := + +# List of library names for -l linker option (-l added when used). +# Includes the BSP. +ALT_LIBRARY_NAMES := + +# List of library names for -msys-lib linker option (-msys-lib added when used). +# These are libraries that might be located in the BSP and depend on the BSP +# library, or vice versa +ALT_BSP_DEP_LIBRARY_NAMES := + +# List of dependencies for the linker. This is usually the full pathname +# of each library (*.a) file. +# Includes the BSP. +ALT_LDDEPS := + +# List of root library directories that support running make to build them. +# Includes the BSP and any ALT libraries. +MAKEABLE_LIBRARY_ROOT_DIRS := + +# Generic flags passed to the compiler for different types of input files. +ALT_CFLAGS := +ALT_CXXFLAGS := +ALT_CPPFLAGS := +ALT_ASFLAGS := +ALT_LDFLAGS := + + +#------------------------------------------------------------------------------ +# The adjust-path macro +# +# If COMSPEC/ComSpec is defined, Make is launched from Windows through +# Cygwin. The adjust-path macro converts absolute windows paths into +# unix style paths (Example: c:/dir -> /c/dir). This will ensture +# paths are readable by GNU Make. +# +# If COMSPEC/ComSpec is not defined, Make is launched from linux, and no +# adjustment is necessary +# +#------------------------------------------------------------------------------ + +ifndef COMSPEC +ifdef ComSpec +COMSPEC = $(ComSpec) +endif # ComSpec +endif # COMSPEC + +ifdef COMSPEC # if Windows OS + +ifeq ($(MAKE_VERSION),3.81) +# +# adjust-path/adjust-path-mixed for Mingw Gnu Make on Windows +# +# Example Usage: +# $(call adjust-path,c:/aaa/bbb) => /c/aaa/bbb +# $(call adjust-path-mixed,/c/aaa/bbb) => c:/aaa/bbb +# $(call adjust-path-mixed,/cygdrive/c/aaa/bbb) => c:/aaa/bbb +# + +# +# adjust-path +# - converts back slash characters into forward slashes +# - if input arg ($1) is an empty string then return the empty string +# - if input arg ($1) does not contain the string ":/", then return input arg +# - using sed, convert mixed path [c:/...] into mingw path [/c/...] +define adjust-path +$(strip \ +$(if $1,\ +$(if $(findstring :/,$(subst \,/,$1)),\ +$(shell echo $(subst \,/,$1) | sed -e 's,^\([a-zA-Z]\):/,/\1/,'),\ +$(subst \,/,$1)))) +endef + +# +# adjust-path-mixed +# - converts back slash characters into forward slashes +# - if input arg ($1) is an empty string then return the empty string +# - if input arg ($1) does not begin with a forward slash '/' char, then +# return input arg +# - using sed, convert mingw path [/c/...] or cygwin path [/c/cygdrive/...] +# into a mixed path [c:/...] +define adjust-path-mixed +$(strip \ +$(if $1,\ +$(if $(findstring $(subst \,/,$1),$(patsubst /%,%,$(subst \,/,$1))),\ +$(subst \,/,$1),\ +$(shell echo $(subst \,/,$1) | sed -e 's,^/cygdrive/\([a-zA-Z]\)/,\1:/,' -e 's,^/\([a-zA-Z]\)/,\1:/,')))) +endef + +else # MAKE_VERSION != 3.81 (MAKE_VERSION == 3.80 or MAKE_VERSION == 3.79) +# +# adjust-path for Cygwin Gnu Make +# $(call adjust-path,c:/aaa/bbb) = /cygdrive/c/aaa/bbb +# $(call adjust-path-mixed,/cygdrive/c/aaa/bbb) = c:/aaa/bbb +# +adjust-path = $(if $1,$(shell cygpath -u "$1"),) +adjust-path-mixed = $(if $1,$(shell cygpath -m "$1"),) +endif + +else # !COMSPEC + +adjust-path = $1 +adjust-path-mixed = $1 + +endif # COMSPEC + + +#vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv +# GENERATED SETTINGS START v +#vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv + +#START GENERATED +ACTIVE_BUILD_CONFIG := default +BUILD_CONFIGS := default + +# The following TYPE comment allows tools to identify the 'type' of target this +# makefile is associated with. +# TYPE: APP_MAKEFILE + +# This following VERSION comment indicates the version of the tool used to +# generate this makefile. A makefile variable is provided for VERSION as well. +# ACDS_VERSION: 12.1sp1 +ACDS_VERSION := 12.1sp1 + +# This following BUILD_NUMBER comment indicates the build number of the tool +# used to generate this makefile. +# BUILD_NUMBER: 243 + +# Define path to the application ELF. +# It may be used by the makefile fragments so is defined before including them. +# +ELF := MCTest.elf + +# Paths to C, C++, and assembly source files. +C_SRCS := +CXX_SRCS += main.cpp +CXX_SRCS += MotorHandler.cpp +ASM_SRCS := + + +# Path to root of object file tree. +OBJ_ROOT_DIR := obj + +# Options to control objdump. +CREATE_OBJDUMP := 1 +OBJDUMP_INCLUDE_SOURCE := 1 +OBJDUMP_FULL_CONTENTS := 0 + +# Options to enable/disable optional files. +CREATE_ELF_DERIVED_FILES := 0 +CREATE_LINKER_MAP := 1 + +# Common arguments for ALT_CFLAGSs +APP_CFLAGS_DEFINED_SYMBOLS := +APP_CFLAGS_UNDEFINED_SYMBOLS := +APP_CFLAGS_OPTIMIZATION := -O0 +APP_CFLAGS_DEBUG_LEVEL := -g +APP_CFLAGS_WARNINGS := -Wall +APP_CFLAGS_USER_FLAGS := + +APP_ASFLAGS_USER := +APP_LDFLAGS_USER := + +# Linker options that have default values assigned later if not +# assigned here. +LINKER_SCRIPT := +CRT0 := +SYS_LIB := + +# Define path to the root of the BSP. +BSP_ROOT_DIR := ../MCTest_bsp/ + +# List of application specific include directories, library directories and library names +APP_INCLUDE_DIRS := +APP_LIBRARY_DIRS := +APP_LIBRARY_NAMES := + +# Pre- and post- processor settings. +BUILD_PRE_PROCESS := +BUILD_POST_PROCESS := + +QUARTUS_PROJECT_DIR := ../../ + + +#END GENERATED + +#^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +# GENERATED SETTINGS END ^ +#^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + + +#------------------------------------------------------------------------------ +# DEFAULT TARGET +#------------------------------------------------------------------------------ + +# Define the variable used to echo output if not already defined. +ifeq ($(ECHO),) +ECHO := echo +endif + +# Put "all" rule before included makefile fragments because they may +# define rules and we don't want one of those to become the default rule. +.PHONY : all + +all: + @$(ECHO) [$(APP_NAME) build complete] + +all : build_pre_process libs app build_post_process + + +#------------------------------------------------------------------------------ +# VARIABLES DEPENDENT ON GENERATED CONTENT +#------------------------------------------------------------------------------ + +# Define object file directory per build configuration +CONFIG_OBJ_DIR := $(OBJ_ROOT_DIR)/$(ACTIVE_BUILD_CONFIG) + +ifeq ($(BSP_ROOT_DIR),) +$(error Edit Makefile and provide a value for BSP_ROOT_DIR) +endif + +ifeq ($(wildcard $(BSP_ROOT_DIR)),) +$(error BSP directory does not exist: $(BSP_ROOT_DIR)) +endif + +# Define absolute path to the root of the BSP. +ABS_BSP_ROOT_DIR := $(call adjust-path-mixed,$(shell cd "$(BSP_ROOT_DIR)"; pwd)) + +# Include makefile fragments. Define variable ALT_LIBRARY_ROOT_DIR before +# including each makefile fragment so that it knows the path to itself. +BSP_INCLUDE_FILE := $(BSP_ROOT_DIR)/public.mk +ALT_LIBRARY_ROOT_DIR := $(BSP_ROOT_DIR) +include $(BSP_INCLUDE_FILE) +# C2H will need this to touch the BSP public.mk and avoid the sopc file +# out-of-date error during a BSP make +ABS_BSP_INCLUDE_FILE := $(ABS_BSP_ROOT_DIR)/public.mk + + +ifneq ($(WARNING.SMALL_STACK_SIZE),) +# This WARNING is here to protect you from unknowingly using a very small stack +# If the warning is set, increase your stack size or enable the BSP small stack +# setting to eliminate the warning +$(warning WARNING: $(WARNING.SMALL_STACK_SIZE)) +endif + + +# If the BSP public.mk indicates that ALT_SIM_OPTIMIZE is set, rename the ELF +# by prefixing it with RUN_ON_HDL_SIMULATOR_ONLY_. +ifneq ($(filter -DALT_SIM_OPTIMIZE,$(ALT_CPPFLAGS)),) +ELF := RUN_ON_HDL_SIMULATOR_ONLY_$(ELF) +endif + +# If the BSP public.mk indicates that ALT_PROVIDE_GMON is set, add option to +# download_elf target +ifneq ($(filter -DALT_PROVIDE_GMON,$(ALT_CPPFLAGS)),) +GMON_OUT_FILENAME := gmon.out +WRITE_GMON_OPTION := --write-gmon $(GMON_OUT_FILENAME) +endif + +# Name of ELF application. +APP_NAME := $(basename $(ELF)) + +# Set to defaults if variables not already defined in settings. +ifeq ($(LINKER_SCRIPT),) +LINKER_SCRIPT := $(BSP_LINKER_SCRIPT) +endif +ifeq ($(CRT0),) +CRT0 := $(BSP_CRT0) +endif +ifeq ($(SYS_LIB),) +SYS_LIB := $(BSP_SYS_LIB) +endif + +OBJDUMP_NAME := $(APP_NAME).objdump +OBJDUMP_FLAGS := --disassemble --syms --all-header +ifeq ($(OBJDUMP_INCLUDE_SOURCE),1) +OBJDUMP_FLAGS += --source +endif +ifeq ($(OBJDUMP_FULL_CONTENTS),1) +OBJDUMP_FLAGS += --full-contents +endif + +# Create list of linker dependencies (*.a files). +APP_LDDEPS := $(ALT_LDDEPS) $(LDDEPS) + +# Take lists and add required prefixes. +APP_INC_DIRS := $(addprefix -I, $(ALT_INCLUDE_DIRS) $(APP_INCLUDE_DIRS) $(INC_DIRS)) +ASM_INC_PREFIX := -Wa,-I +APP_ASM_INC_DIRS := $(addprefix $(ASM_INC_PREFIX), $(ALT_INCLUDE_DIRS) $(APP_INCLUDE_DIRS) $(INC_DIRS)) +APP_LIB_DIRS := $(addprefix -L, $(ALT_LIBRARY_DIRS) $(APP_LIBRARY_DIRS) $(LIB_DIRS)) +APP_LIBS := $(addprefix -l, $(ALT_LIBRARY_NAMES) $(APP_LIBRARY_NAMES) $(LIBS)) + +ifneq ($(AVOID_NIOS2_GCC3_OPTIONS),) + +# +# Avoid Nios II GCC 3.X options. +# + +# Detect if small newlib C library is requested. +# If yes, remove the -msmallc option because it is +# now handled by other means. +ifneq ($(filter -msmallc,$(ALT_LDFLAGS)),) + ALT_LDFLAGS := $(filter-out -msmallc,$(ALT_LDFLAGS)) + ALT_C_LIBRARY := smallc +else + ALT_C_LIBRARY := c +endif + +# Put each BSP dependent library in a group to avoid circular dependencies. +APP_BSP_DEP_LIBS := $(foreach l,$(ALT_BSP_DEP_LIBRARY_NAMES),-Wl,--start-group -l$(ALT_C_LIBRARY) -lgcc -l$(l) -Wl,--end-group) + +else # !AVOID_NIOS2_GCC3_OPTIONS + +# +# Use Nios II GCC 3.X options. +# +APP_BSP_DEP_LIBS := $(addprefix -msys-lib=, $(ALT_BSP_DEP_LIBRARY_NAMES)) + +endif # !AVOID_NIOS2_GCC3_OPTIONS + +# Arguments for the C preprocessor, C/C++ compiler, assembler, and linker. +APP_CFLAGS := $(APP_CFLAGS_DEFINED_SYMBOLS) \ + $(APP_CFLAGS_UNDEFINED_SYMBOLS) \ + $(APP_CFLAGS_OPTIMIZATION) \ + $(APP_CFLAGS_DEBUG_LEVEL) \ + $(APP_CFLAGS_WARNINGS) \ + $(APP_CFLAGS_USER_FLAGS) \ + $(ALT_CFLAGS) \ + $(CFLAGS) + +# Arguments only for the C++ compiler. +APP_CXXFLAGS := $(ALT_CXXFLAGS) $(CXXFLAGS) + +# Arguments only for the C preprocessor. +# Prefix each include directory with -I. +APP_CPPFLAGS := $(APP_INC_DIRS) \ + $(ALT_CPPFLAGS) \ + $(CPPFLAGS) + +# Arguments only for the assembler. +APP_ASFLAGS := $(APP_ASM_INC_DIRS) \ + $(ALT_ASFLAGS) \ + $(APP_ASFLAGS_USER) \ + $(ASFLAGS) + +# Arguments only for the linker. +APP_LDFLAGS := $(APP_LDFLAGS_USER) + +ifneq ($(LINKER_SCRIPT),) +APP_LDFLAGS += -T'$(LINKER_SCRIPT)' +endif + +ifneq ($(AVOID_NIOS2_GCC3_OPTIONS),) + +# Avoid Nios II GCC 3.x options. +ifneq ($(CRT0),) +APP_LDFLAGS += $(CRT0) +endif + +# The equivalent of the -msys-lib option is provided +# by the GROUP() command in the linker script. +# Note this means the SYS_LIB variable is now ignored. + +else # !AVOID_NIOS2_GCC3_OPTIONS + +# Use Nios II GCC 3.x options. +ifneq ($(CRT0),) +APP_LDFLAGS += -msys-crt0='$(CRT0)' +endif +ifneq ($(SYS_LIB),) +APP_LDFLAGS += -msys-lib=$(SYS_LIB) +endif + +endif # !AVOID_NIOS2_GCC3_OPTIONS + +APP_LDFLAGS += \ + $(APP_LIB_DIRS) \ + $(ALT_LDFLAGS) \ + $(LDFLAGS) + +LINKER_MAP_NAME := $(APP_NAME).map +ifeq ($(CREATE_LINKER_MAP), 1) +APP_LDFLAGS += -Wl,-Map=$(LINKER_MAP_NAME) +endif + +# QUARTUS_PROJECT_DIR and SOPC_NAME need to be defined if you want the +# mem_init_install target of the mem_init.mk (located in the associated BSP) +# to know how to copy memory initialization files (e.g. .dat, .hex) into +# directories required for Quartus compilation or RTL simulation. + +# Defining QUARTUS_PROJECT_DIR causes mem_init_install to copy memory +# initialization files into your Quartus project directory. This is required +# to provide the initial memory contents of FPGA memories that can be +# initialized by the programming file (.sof) or Hardcopy ROMs. It is also used +# for VHDL simulation of on-chip memories. + +# Defining SOPC_NAME causes the mem_init_install target to copy memory +# initialization files into your RTL simulation directory. This is required +# to provide the initial memory contents of all memories that can be +# initialized by RTL simulation. This variable should be set to the same name +# as your SOPC Builder system name. For example, if you have a system called +# "foo.sopc", this variable should be set to "foo". + +# If SOPC_NAME is not set and QUARTUS_PROJECT_DIR is set, then derive SOPC_NAME. +ifeq ($(SOPC_NAME),) +ifneq ($(QUARTUS_PROJECT_DIR),) +SOPC_NAME := $(basename $(notdir $(wildcard $(QUARTUS_PROJECT_DIR)/*.sopcinfo))) +endif +endif + +# Defining JDI_FILE is required to specify the JTAG Debug Information File +# path. This file is generated by Quartus, and is needed along with the +# .sopcinfo file to resolve processor instance ID's from names in a multi-CPU +# systems. For multi-CPU systems, the processor instance ID is used to select +# from multiple CPU's during ELF download. + +# Both JDI_FILE and SOPCINFO_FILE are provided by the BSP if they found during +# BSP creation. If JDI_FILE is not set and QUARTUS_PROJECT_DIR is set, then +# derive JDI_FILE. We do not attempt to derive SOPCINFO_FILE since there may be +# multiple .sopcinfo files in a Quartus project. +ifeq ($(JDI_FILE),) +ifneq ($(QUARTUS_PROJECT_DIR),) +JDI_FILE := $(wildcard $(QUARTUS_PROJECT_DIR)/*.jdi) +endif +endif + +# Path to root runtime directory used for hdl simulation +RUNTIME_ROOT_DIR := $(CONFIG_OBJ_DIR)/runtime + + + +#------------------------------------------------------------------------------ +# MAKEFILE INCLUDES DEPENDENT ON GENERATED CONTENT +#------------------------------------------------------------------------------ +# mem_init.mk is a generated makefile fragment. This file defines all targets +# used to generate HDL initialization simulation files and pre-initialized +# onchip memory files. +MEM_INIT_FILE := $(BSP_ROOT_DIR)/mem_init.mk +include $(MEM_INIT_FILE) + +# Create list of object files to be built using the list of source files. +# The source file hierarchy is preserved in the object tree. +# The supported file extensions are: +# +# .c - for C files +# .cxx .cc .cpp - for C++ files +# .S .s - for assembler files +# +# Handle source files specified by --src-dir & --src-rdir differently, to +# save some processing time in calling the adjust-path macro. + +OBJ_LIST_C := $(patsubst %.c,%.o,$(filter %.c,$(C_SRCS))) +OBJ_LIST_CPP := $(patsubst %.cpp,%.o,$(filter %.cpp,$(CXX_SRCS))) +OBJ_LIST_CXX := $(patsubst %.cxx,%.o,$(filter %.cxx,$(CXX_SRCS))) +OBJ_LIST_CC := $(patsubst %.cc,%.o,$(filter %.cc,$(CXX_SRCS))) +OBJ_LIST_S := $(patsubst %.S,%.o,$(filter %.S,$(ASM_SRCS))) +OBJ_LIST_SS := $(patsubst %.s,%.o,$(filter %.s,$(ASM_SRCS))) + +OBJ_LIST := $(sort $(OBJ_LIST_C) $(OBJ_LIST_CPP) $(OBJ_LIST_CXX) \ + $(OBJ_LIST_CC) $(OBJ_LIST_S) $(OBJ_LIST_SS)) + +SDIR_OBJ_LIST_C := $(patsubst %.c,%.o,$(filter %.c,$(SDIR_C_SRCS))) +SDIR_OBJ_LIST_CPP := $(patsubst %.cpp,%.o,$(filter %.cpp,$(SDIR_CXX_SRCS))) +SDIR_OBJ_LIST_CXX := $(patsubst %.cxx,%.o,$(filter %.cxx,$(SDIR_CXX_SRCS))) +SDIR_OBJ_LIST_CC := $(patsubst %.cc,%.o,$(filter %.cc,$(SDIR_CXX_SRCS))) +SDIR_OBJ_LIST_S := $(patsubst %.S,%.o,$(filter %.S,$(SDIR_ASM_SRCS))) +SDIR_OBJ_LIST_SS := $(patsubst %.s,%.o,$(filter %.s,$(SDIR_ASM_SRCS))) + +SDIR_OBJ_LIST := $(sort $(SDIR_OBJ_LIST_C) $(SDIR_OBJ_LIST_CPP) \ + $(SDIR_OBJ_LIST_CXX) $(SDIR_OBJ_LIST_CC) $(SDIR_OBJ_LIST_S) \ + $(SDIR_OBJ_LIST_SS)) + +# Relative-pathed objects that being with "../" are handled differently. +# +# Regular objects are created as +# $(CONFIG_OBJ_DIR)//.o +# where the path structure is maintained under the obj directory. This +# applies for both absolute and relative paths; in the absolute path +# case this means the entire source path will be recreated under the obj +# directory. This is done to allow two source files with the same name +# to be included as part of the project. +# +# Note: On Cygwin, the path recreated under the obj directory will be +# the cygpath -u output path. +# +# Relative-path objects that begin with "../" cause problems under this +# scheme, as $(CONFIG_OBJ_DIR)/..// can potentially put the object +# files anywhere in the system, creating clutter and polluting the source tree. +# As such, their paths are flattened - the object file created will be +# $(CONFIG_OBJ_DIR)/.o. Due to this, two files specified with +# "../" in the beginning cannot have the same name in the project. VPATH +# will be set for these sources to allow make to relocate the source file +# via %.o rules. +# +# The following lines separate the object list into the flatten and regular +# lists, and then handles them as appropriate. + +FLATTEN_OBJ_LIST := $(filter ../%,$(OBJ_LIST)) +FLATTEN_APP_OBJS := $(addprefix $(CONFIG_OBJ_DIR)/,$(notdir $(FLATTEN_OBJ_LIST))) + +REGULAR_OBJ_LIST := $(filter-out $(FLATTEN_OBJ_LIST),$(OBJ_LIST)) +REGULAR_OBJ_LIST_C := $(filter $(OBJ_LIST_C),$(REGULAR_OBJ_LIST)) +REGULAR_OBJ_LIST_CPP := $(filter $(OBJ_LIST_CPP),$(REGULAR_OBJ_LIST)) +REGULAR_OBJ_LIST_CXX := $(filter $(OBJ_LIST_CXX),$(REGULAR_OBJ_LIST)) +REGULAR_OBJ_LIST_CC := $(filter $(OBJ_LIST_CC),$(REGULAR_OBJ_LIST)) +REGULAR_OBJ_LIST_S := $(filter $(OBJ_LIST_S),$(REGULAR_OBJ_LIST)) +REGULAR_OBJ_LIST_SS := $(filter $(OBJ_LIST_SS),$(REGULAR_OBJ_LIST)) + +FLATTEN_SDIR_OBJ_LIST := $(filter ../%,$(SDIR_OBJ_LIST)) +FLATTEN_SDIR_APP_OBJS := $(addprefix $(CONFIG_OBJ_DIR)/,$(notdir $(FLATTEN_SDIR_OBJ_LIST))) + +REGULAR_SDIR_OBJ_LIST := $(filter-out $(FLATTEN_SDIR_OBJ_LIST),$(SDIR_OBJ_LIST)) +REGULAR_SDIR_OBJ_LIST_C := $(filter $(SDIR_OBJ_LIST_C),$(REGULAR_SDIR_OBJ_LIST)) +REGULAR_SDIR_OBJ_LIST_CPP := $(filter $(SDIR_OBJ_LIST_CPP),$(REGULAR_SDIR_OBJ_LIST)) +REGULAR_SDIR_OBJ_LIST_CXX := $(filter $(SDIR_OBJ_LIST_CXX),$(REGULAR_SDIR_OBJ_LIST)) +REGULAR_SDIR_OBJ_LIST_CC := $(filter $(SDIR_OBJ_LIST_CC),$(REGULAR_SDIR_OBJ_LIST)) +REGULAR_SDIR_OBJ_LIST_S := $(filter $(SDIR_OBJ_LIST_S),$(REGULAR_SDIR_OBJ_LIST)) +REGULAR_SDIR_OBJ_LIST_SS := $(filter $(SDIR_OBJ_LIST_SS),$(REGULAR_SDIR_OBJ_LIST)) + +VPATH := $(sort $(dir $(FLATTEN_OBJ_LIST)) $(dir $(FLATTEN_SDIR_OBJ_LIST))) + +APP_OBJS_C := $(addprefix $(CONFIG_OBJ_DIR)/,\ + $(REGULAR_SDIR_OBJ_LIST_C) \ + $(foreach s,$(REGULAR_OBJ_LIST_C),$(call adjust-path,$s))) + +APP_OBJS_CPP := $(addprefix $(CONFIG_OBJ_DIR)/,\ + $(REGULAR_SDIR_OBJ_LIST_CPP) \ + $(foreach s,$(REGULAR_OBJ_LIST_CPP),$(call adjust-path,$s))) + +APP_OBJS_CXX := $(addprefix $(CONFIG_OBJ_DIR)/,\ + $(REGULAR_SDIR_OBJ_LIST_CXX) \ + $(foreach s,$(REGULAR_OBJ_LIST_CXX),$(call adjust-path,$s))) + +APP_OBJS_CC := $(addprefix $(CONFIG_OBJ_DIR)/,\ + $(REGULAR_SDIR_OBJ_LIST_CC) \ + $(foreach s,$(REGULAR_OBJ_LIST_CC),$(call adjust-path,$s))) + +APP_OBJS_S := $(addprefix $(CONFIG_OBJ_DIR)/,\ + $(REGULAR_SDIR_OBJ_LIST_S) \ + $(foreach s,$(REGULAR_OBJ_LIST_S),$(call adjust-path,$s))) + +APP_OBJS_SS := $(addprefix $(CONFIG_OBJ_DIR)/,\ + $(REGULAR_SDIR_OBJ_LIST_SS) \ + $(foreach s,$(REGULAR_OBJ_LIST_SS),$(call adjust-path,$s))) + +APP_OBJS := $(APP_OBJS_C) $(APP_OBJS_CPP) $(APP_OBJS_CXX) $(APP_OBJS_CC) \ + $(APP_OBJS_S) $(APP_OBJS_SS) \ + $(FLATTEN_APP_OBJS) $(FLATTEN_SDIR_APP_OBJS) + +# Add any extra user-provided object files. +APP_OBJS += $(OBJS) + +# Create list of dependancy files for each object file. +APP_DEPS := $(APP_OBJS:.o=.d) + +# Patch the Elf file with system specific information + +# Patch the Elf with the name of the sopc system +ifneq ($(SOPC_NAME),) +ELF_PATCH_FLAG += --sopc_system_name $(SOPC_NAME) +endif + +# Patch the Elf with the absolute path to the Quartus Project Directory +ifneq ($(QUARTUS_PROJECT_DIR),) +ABS_QUARTUS_PROJECT_DIR := $(call adjust-path-mixed,$(shell cd "$(QUARTUS_PROJECT_DIR)"; pwd)) +ELF_PATCH_FLAG += --quartus_project_dir "$(ABS_QUARTUS_PROJECT_DIR)" +endif + +# Patch the Elf and download args with the JDI_FILE if specified +ifneq ($(wildcard $(JDI_FILE)),) +ELF_PATCH_FLAG += --jdi $(JDI_FILE) +DOWNLOAD_JDI_FLAG := --jdi $(JDI_FILE) +endif + +# Patch the Elf with the SOPCINFO_FILE if specified +ifneq ($(wildcard $(SOPCINFO_FILE)),) +ELF_PATCH_FLAG += --sopcinfo $(SOPCINFO_FILE) +endif + +# Use the DOWNLOAD_CABLE variable to specify which JTAG cable to use. +# This is not needed if you only have one cable. +ifneq ($(DOWNLOAD_CABLE),) +DOWNLOAD_CABLE_FLAG := --cable '$(DOWNLOAD_CABLE)' +endif + + +#------------------------------------------------------------------------------ +# BUILD PRE/POST PROCESS +#------------------------------------------------------------------------------ +build_pre_process : + $(BUILD_PRE_PROCESS) + +build_post_process : + $(BUILD_POST_PROCESS) + +.PHONY: build_pre_process build_post_process + + +#------------------------------------------------------------------------------ +# TOOLS +#------------------------------------------------------------------------------ + +# +# Set tool default variables if not already defined. +# If these are defined, they would typically be defined in an +# included makefile fragment. +# +ifeq ($(DEFAULT_CROSS_COMPILE),) +DEFAULT_CROSS_COMPILE := nios2-elf- +endif + +ifeq ($(DEFAULT_STACK_REPORT),) +DEFAULT_STACKREPORT := nios2-stackreport +endif + +ifeq ($(DEFAULT_DOWNLOAD),) +DEFAULT_DOWNLOAD := nios2-download +endif + +ifeq ($(DEFAULT_FLASHPROG),) +DEFAULT_FLASHPROG := nios2-flash-programmer +endif + +ifeq ($(DEFAULT_ELFPATCH),) +DEFAULT_ELFPATCH := nios2-elf-insert +endif + +ifeq ($(DEFAULT_RM),) +DEFAULT_RM := rm -f +endif + +ifeq ($(DEFAULT_CP),) +DEFAULT_CP := cp -f +endif + +ifeq ($(DEFAULT_MKDIR),) +DEFAULT_MKDIR := mkdir -p +endif + +# +# Set tool variables to defaults if not already defined. +# If these are defined, they would typically be defined by a +# setting in the generated portion of this makefile. +# +ifeq ($(CROSS_COMPILE),) +CROSS_COMPILE := $(DEFAULT_CROSS_COMPILE) +endif + +ifeq ($(origin CC),default) +CC := $(CROSS_COMPILE)gcc -xc +endif + +ifeq ($(origin CXX),default) +CXX := $(CROSS_COMPILE)gcc -xc++ +endif + +ifeq ($(origin AS),default) +AS := $(CROSS_COMPILE)gcc +endif + +ifeq ($(origin AR),default) +AR := $(CROSS_COMPILE)ar +endif + +ifeq ($(origin LD),default) +LD := $(CROSS_COMPILE)g++ +endif + +ifeq ($(origin NM),default) +NM := $(CROSS_COMPILE)nm +endif + +ifeq ($(origin RM),default) +RM := $(DEFAULT_RM) +endif + +ifeq ($(origin CP),default) +CP := $(DEFAULT_CP) +endif + +ifeq ($(OBJDUMP),) +OBJDUMP := $(CROSS_COMPILE)objdump +endif + +ifeq ($(OBJCOPY),) +OBJCOPY := $(CROSS_COMPILE)objcopy +endif + +ifeq ($(STACKREPORT),) +ifeq ($(CROSS_COMPILE),nios2-elf-) +STACKREPORT := $(DEFAULT_STACKREPORT) +else +DISABLE_STACKREPORT := 1 +endif +endif + +ifeq ($(DOWNLOAD),) +DOWNLOAD := $(DEFAULT_DOWNLOAD) +endif + +ifeq ($(FLASHPROG),) +FLASHPROG := $(DEFAULT_FLASHPROG) +endif + +ifeq ($(ELFPATCH),) +ELFPATCH := $(DEFAULT_ELFPATCH) +endif + +ifeq ($(MKDIR),) +MKDIR := $(DEFAULT_MKDIR) +endif + +#------------------------------------------------------------------------------ +# PATTERN RULES TO BUILD OBJECTS +#------------------------------------------------------------------------------ + +define compile.c +@$(ECHO) Info: Compiling $< to $@ +@$(MKDIR) $(@D) +$(CC) -MP -MMD -c $(APP_CPPFLAGS) $(APP_CFLAGS) -o $@ $< +$(CC_POST_PROCESS) +endef + +define compile.cpp +@$(ECHO) Info: Compiling $< to $@ +@$(MKDIR) $(@D) +$(CXX) -MP -MMD -c $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $< +$(CXX_POST_PROCESS) +endef + +# If assembling with the compiler, ensure "-Wa," is prepended to all APP_ASFLAGS +ifeq ($(AS),$(patsubst %as,%,$(AS))) +COMMA := , +APP_ASFLAGS := $(filter-out $(APP_CFLAGS),$(addprefix -Wa$(COMMA),$(patsubst -Wa$(COMMA)%,%,$(APP_ASFLAGS)))) +endif + +define compile.s +@$(ECHO) Info: Assembling $< to $@ +@$(MKDIR) $(@D) +$(AS) -MP -MMD -c $(APP_CPPFLAGS) $(APP_CFLAGS) $(APP_ASFLAGS) -o $@ $< +$(AS_POST_PROCESS) +endef + +ifeq ($(MAKE_VERSION),3.81) +.SECONDEXPANSION: + +$(APP_OBJS_C): $(CONFIG_OBJ_DIR)/%.o: $$(call adjust-path-mixed,%.c) + $(compile.c) + +$(APP_OBJS_CPP): $(CONFIG_OBJ_DIR)/%.o: $$(call adjust-path-mixed,%.cpp) + $(compile.cpp) + +$(APP_OBJS_CC): $(CONFIG_OBJ_DIR)/%.o: $$(call adjust-path-mixed,%.cc) + $(compile.cpp) + +$(APP_OBJS_CXX): $(CONFIG_OBJ_DIR)/%.o: $$(call adjust-path-mixed,%.cxx) + $(compile.cpp) + +$(APP_OBJS_S): $(CONFIG_OBJ_DIR)/%.o: $$(call adjust-path-mixed,%.S) + $(compile.s) + +$(APP_OBJS_SS): $(CONFIG_OBJ_DIR)/%.o: $$(call adjust-path-mixed,%.s) + $(compile.s) + +endif # MAKE_VERSION != 3.81 + +$(CONFIG_OBJ_DIR)/%.o: %.c + $(compile.c) + +$(CONFIG_OBJ_DIR)/%.o: %.cpp + $(compile.cpp) + +$(CONFIG_OBJ_DIR)/%.o: %.cc + $(compile.cpp) + +$(CONFIG_OBJ_DIR)/%.o: %.cxx + $(compile.cpp) + +$(CONFIG_OBJ_DIR)/%.o: %.S + $(compile.s) + +$(CONFIG_OBJ_DIR)/%.o: %.s + $(compile.s) + + +#------------------------------------------------------------------------------ +# PATTERN RULES TO INTERMEDIATE FILES +#------------------------------------------------------------------------------ + +$(CONFIG_OBJ_DIR)/%.s: %.c + @$(ECHO) Info: Compiling $< to $@ + @$(MKDIR) $(@D) + $(CC) -S $(APP_CPPFLAGS) $(APP_CFLAGS) -o $@ $< + +$(CONFIG_OBJ_DIR)/%.s: %.cpp + @$(ECHO) Info: Compiling $< to $@ + @$(MKDIR) $(@D) + $(CXX) -S $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $< + +$(CONFIG_OBJ_DIR)/%.s: %.cc + @$(ECHO) Info: Compiling $< to $@ + @$(MKDIR) $(@D) + $(CXX) -S $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $< + +$(CONFIG_OBJ_DIR)/%.s: %.cxx + @$(ECHO) Info: Compiling $< to $@ + @$(MKDIR) $(@D) + $(CXX) -S $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $< + +$(CONFIG_OBJ_DIR)/%.i: %.c + @$(ECHO) Info: Compiling $< to $@ + @$(MKDIR) $(@D) + $(CC) -E $(APP_CPPFLAGS) $(APP_CFLAGS) -o $@ $< + +$(CONFIG_OBJ_DIR)/%.i: %.cpp + @$(ECHO) Info: Compiling $< to $@ + @$(MKDIR) $(@D) + $(CXX) -E $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $< + +$(CONFIG_OBJ_DIR)/%.i: %.cc + @$(ECHO) Info: Compiling $< to $@ + @$(MKDIR) $(@D) + $(CXX) -E $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $< + +$(CONFIG_OBJ_DIR)/%.i: %.cxx + @$(ECHO) Info: Compiling $< to $@ + @$(MKDIR) $(@D) + $(CXX) -E $(APP_CPPFLAGS) $(APP_CXXFLAGS) $(APP_CFLAGS) -o $@ $< + + +#------------------------------------------------------------------------------ +# TARGET RULES +#------------------------------------------------------------------------------ + +.PHONY : help +help : + @$(ECHO) "Summary of Makefile targets" + @$(ECHO) " Build targets:" + @$(ECHO) " all (default) - Application and all libraries (including BSP)" + @$(ECHO) " bsp - Just the BSP" + @$(ECHO) " libs - All libraries (including BSP)" + @$(ECHO) " flash - All flash files" + @$(ECHO) " mem_init_generate - All memory initialization files" +ifeq ($(QSYS),1) + @$(ECHO) " mem_init_install - This target is deprecated for QSys Systems" + @$(ECHO) " --> Use the mem_init_generate target and then" + @$(ECHO) " add the generated meminit.qip file to your" + @$(ECHO) " Quartus II Project." +else # if QSYS != 1 + @$(ECHO) " mem_init_install - Copy memory initialization files to Quartus II project" +endif # QSYS == 1 + @$(ECHO) + @$(ECHO) " Clean targets:" + @$(ECHO) " clean_all - Application and all libraries (including BSP)" + @$(ECHO) " clean - Just the application" + @$(ECHO) " clean_bsp - Just the BSP" + @$(ECHO) " clean_libs - All libraries (including BSP)" + @$(ECHO) + @$(ECHO) " Run targets:" + @$(ECHO) " download-elf - Download and run your elf executable" + @$(ECHO) " program-flash - Program flash contents to the board" + +# Handy rule to skip making libraries and just make application. +.PHONY : app +app : $(ELF) + +ifeq ($(CREATE_OBJDUMP), 1) +app : $(OBJDUMP_NAME) +endif + +ifeq ($(CREATE_ELF_DERIVED_FILES),1) +app : elf_derived_files +endif + +.PHONY: elf_derived_files +elf_derived_files: default_mem_init + +# Handy rule for making just the BSP. +.PHONY : bsp +bsp : + @$(ECHO) Info: Building $(BSP_ROOT_DIR) + @$(MAKE) --no-print-directory -C $(BSP_ROOT_DIR) + + +# Make sure all makeable libraries (including the BSP) are up-to-date. +LIB_TARGETS := $(patsubst %,%-recurs-make-lib,$(MAKEABLE_LIBRARY_ROOT_DIRS)) + +.PHONY : libs +libs : $(LIB_TARGETS) + +ifneq ($(strip $(LIB_TARGETS)),) +$(LIB_TARGETS): %-recurs-make-lib: + @$(ECHO) Info: Building $* + $(MAKE) --no-print-directory -C $* +endif + +ifneq ($(strip $(APP_LDDEPS)),) +$(APP_LDDEPS): libs + @true +endif + +# Rules to force your project to rebuild or relink +# .force_relink file will cause any application that depends on this project to relink +# .force_rebuild file will cause this project to rebuild object files +# .force_rebuild_all file will cause this project and any project that depends on this project to rebuild object files + +FORCE_RELINK_DEP := .force_relink +FORCE_REBUILD_DEP := .force_rebuild +FORCE_REBUILD_ALL_DEP := .force_rebuild_all +FORCE_REBUILD_DEP_LIST := $(CONFIG_OBJ_DIR)/$(FORCE_RELINK_DEP) $(CONFIG_OBJ_DIR)/$(FORCE_REBUILD_DEP) $(FORCE_REBUILD_ALL_DEP) + +$(FORCE_REBUILD_DEP_LIST): + +$(APP_OBJS): $(wildcard $(CONFIG_OBJ_DIR)/$(FORCE_REBUILD_DEP)) $(wildcard $(addsuffix /$(FORCE_REBUILD_ALL_DEP), . $(ALT_LIBRARY_DIRS))) + +$(ELF): $(wildcard $(addsuffix /$(FORCE_RELINK_DEP), $(CONFIG_OBJ_DIR) $(ALT_LIBRARY_DIRS))) + + +# Clean just the application. +.PHONY : clean +ifeq ($(CREATE_ELF_DERIVED_FILES),1) +clean : clean_elf_derived_files +endif + +clean : + @$(RM) -r $(ELF) $(OBJDUMP_NAME) $(LINKER_MAP_NAME) $(OBJ_ROOT_DIR) $(RUNTIME_ROOT_DIR) $(FORCE_REBUILD_DEP_LIST) + @$(ECHO) [$(APP_NAME) clean complete] + +# Clean just the BSP. +.PHONY : clean_bsp +clean_bsp : + @$(ECHO) Info: Cleaning $(BSP_ROOT_DIR) + @$(MAKE) --no-print-directory -C $(BSP_ROOT_DIR) clean + +# Clean all makeable libraries including the BSP. +LIB_CLEAN_TARGETS := $(patsubst %,%-recurs-make-clean-lib,$(MAKEABLE_LIBRARY_ROOT_DIRS)) + +.PHONY : clean_libs +clean_libs : $(LIB_CLEAN_TARGETS) + +ifneq ($(strip $(LIB_CLEAN_TARGETS)),) +$(LIB_CLEAN_TARGETS): %-recurs-make-clean-lib: + @$(ECHO) Info: Cleaning $* + $(MAKE) --no-print-directory -C $* clean +endif + +.PHONY: clean_elf_derived_files +clean_elf_derived_files: mem_init_clean + +# Clean application and all makeable libraries including the BSP. +.PHONY : clean_all +clean_all : clean mem_init_clean clean_libs + +# Include the dependency files unless the make goal is performing a clean +# of the application. +ifneq ($(firstword $(MAKECMDGOALS)),clean) +ifneq ($(firstword $(MAKECMDGOALS)),clean_all) +-include $(APP_DEPS) +endif +endif + +.PHONY : download-elf +download-elf : $(ELF) + @if [ "$(DOWNLOAD)" = "none" ]; \ + then \ + $(ECHO) Downloading $(ELF) not supported; \ + else \ + $(ECHO) Info: Downloading $(ELF); \ + $(DOWNLOAD) --go --cpu_name=$(CPU_NAME) $(DOWNLOAD_CABLE_FLAG) $(SOPC_SYSID_FLAG) $(DOWNLOAD_JDI_FLAG) $(WRITE_GMON_OPTION) $(ELF); \ + fi + +# Delete the target of a rule if it has changed and its commands exit +# with a nonzero exit status. +.DELETE_ON_ERROR: + +# Rules for flash programming commands +PROGRAM_FLASH_SUFFIX := -program +PROGRAM_FLASH_TARGET := $(addsuffix $(PROGRAM_FLASH_SUFFIX), $(FLASH_FILES)) + +.PHONY : program-flash +program-flash : $(PROGRAM_FLASH_TARGET) + +.PHONY : $(PROGRAM_FLASH_TARGET) +$(PROGRAM_FLASH_TARGET) : flash + @if [ "$(FLASHPROG)" = "none" ]; \ + then \ + $(ECHO) Programming flash not supported; \ + else \ + $(ECHO) Info: Programming $(basename $@).flash; \ + if [ -z "$($(basename $@)_EPCS_FLAGS)" ]; \ + then \ + $(ECHO) $(FLASHPROG) $(SOPC_SYSID_FLAG) --base=$($(basename $@)_START) $(basename $@).flash; \ + $(FLASHPROG) $(DOWNLOAD_CABLE_FLAG) $(SOPC_SYSID_FLAG) --base=$($(basename $@)_START) $(basename $@).flash; \ + else \ + $(ECHO) $(FLASHPROG) $(SOPC_SYSID_FLAG) --epcs --base=$($(basename $@)_START) $(basename $@).flash; \ + $(FLASHPROG) $(DOWNLOAD_CABLE_FLAG) $(SOPC_SYSID_FLAG) --epcs --base=$($(basename $@)_START) $(basename $@).flash; \ + fi \ + fi + + +# Rules for simulating with an HDL Simulator [QSYS only] +ifeq ($(QSYS),1) +IP_MAKE_SIMSCRIPT := ip-make-simscript + +ifeq ($(VSIM),) +VSIM_EXE := $(if $(VSIM_DIR),$(VSIM_DIR)/,)vsim +ifeq ($(ENABLE_VSIM_GUI),1) +VSIM := $(VSIM_EXE) -gui +else +VSIM := $(VSIM_EXE) -c +endif # ENABLE_VSIM_GUI == 1 +endif # VSIM not set + +ifeq ($(SPD),) +ifneq ($(ABS_QUARTUS_PROJECT_DIR),) +ifneq ($(SOPC_NAME),) +SPD := $(ABS_QUARTUS_PROJECT_DIR)/$(SOPC_NAME)_tb.spd +endif # SOPC_NAME set +endif # ABS_QUARTUS_PROJECT_DIR set +endif # SPD == empty string + +ifeq ($(MSIM_SCRIPT),) +SIM_SCRIPT_DIR := $(RUNTIME_ROOT_DIR)/sim +MSIM_SCRIPT := $(SIM_SCRIPT_DIR)/mentor/msim_setup.tcl +endif # MSIM_SCRIPT == empty string + +ifeq ($(MAKE_VERSION),3.81) +ABS_MEM_INIT_DESCRIPTOR_FILE := $(abspath $(MEM_INIT_DESCRIPTOR_FILE)) +else +ABS_MEM_INIT_DESCRIPTOR_FILE := $(call adjust-path-mixed,$(shell pwd))/$(MEM_INIT_DESCRIPTOR_FILE) +endif + +$(MSIM_SCRIPT): $(SPD) $(MEM_INIT_DESCRIPTOR_FILE) +ifeq ($(SPD),) + $(error No SPD file specified. Ensure QUARTUS_PROJECT_DIR variable is set) +endif + @$(MKDIR) $(SIM_SCRIPT_DIR) + $(IP_MAKE_SIMSCRIPT) --spd=$(SPD) --spd=$(MEM_INIT_DESCRIPTOR_FILE) --output-directory=$(SIM_SCRIPT_DIR) + +VSIM_COMMAND = \ + cd $(dir $(MSIM_SCRIPT)) && \ + $(VSIM) -do "do $(notdir $(MSIM_SCRIPT)); ld; $(if $(VSIM_RUN_TIME),run ${VSIM_RUN_TIME};quit;)" + +.PHONY: sim +sim: $(MSIM_SCRIPT) mem_init_generate +ifeq ($(MSIM_SCRIPT),) + $(error MSIM_SCRIPT not set) +endif + $(VSIM_COMMAND) + +endif # QSYS == 1 + + +#------------------------------------------------------------------------------ +# ELF TARGET RULE +#------------------------------------------------------------------------------ +# Rule for constructing the executable elf file. +$(ELF) : $(APP_OBJS) $(LINKER_SCRIPT) $(APP_LDDEPS) + @$(ECHO) Info: Linking $@ + $(LD) $(APP_LDFLAGS) $(APP_CFLAGS) -o $@ $(filter-out $(CRT0),$(APP_OBJS)) $(APP_LIBS) $(APP_BSP_DEP_LIBS) +ifneq ($(DISABLE_ELFPATCH),1) + $(ELFPATCH) $@ $(ELF_PATCH_FLAG) +endif +ifneq ($(DISABLE_STACKREPORT),1) + @bash -c "$(STACKREPORT) $@" +endif + +$(OBJDUMP_NAME) : $(ELF) + @$(ECHO) Info: Creating $@ + $(OBJDUMP) $(OBJDUMP_FLAGS) $< >$@ + +# Rule for printing the name of the elf file +.PHONY: print-elf-name +print-elf-name: + @$(ECHO) $(ELF) + + diff --git a/MCandWifiTestDE0/Software/MCTest/MotorHandler.cpp b/MCandWifiTestDE0/Software/MCTest/MotorHandler.cpp new file mode 100644 index 00000000..01bb7944 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest/MotorHandler.cpp @@ -0,0 +1,86 @@ +/* + * MotorHandler.cpp + * + * Created on: 2014-03-03 + * Author: gongal + */ + +#include "MotorHandler.h" +#include "includes.h" +#include "altera_avalon_uart_regs.h" + +MotorHandler::MotorHandler() { + // TODO Auto-generated constructor stub + +} + +MotorHandler::~MotorHandler() { + // TODO Auto-generated destructor stub +} +void MotorHandler::sendByteMC(char msg){ + IOWR_ALTERA_AVALON_UART_TXDATA(UART_MC_BASE, msg); +} +/* + * Move rover forward by activating both motors + */ +void MotorHandler::mc_forward(){ + //motor 1 + sendByteMC(MOTOR_START_BYTE); + sendByteMC(MOTOR_DEVICE_TYPE); + sendByteMC(MOTOR_MOTOR2_FORWARD); + sendByteMC(MOTOR_CONST_SPEED); + //motor 2 + sendByteMC(MOTOR_START_BYTE); + sendByteMC(MOTOR_DEVICE_TYPE); + sendByteMC(MOTOR_MOTOR3_FORWARD); + sendByteMC(MOTOR_CONST_SPEED); +} +/* + * Move rover backward by activating both motor backwards + */ +void MotorHandler::mc_backward(){ + //motor 1 + sendByteMC(MOTOR_START_BYTE); + sendByteMC(MOTOR_DEVICE_TYPE); + sendByteMC(MOTOR_MOTOR2_BACKWARD); + sendByteMC(MOTOR_CONST_SPEED); + //motor 2 + sendByteMC(MOTOR_START_BYTE); + sendByteMC(MOTOR_DEVICE_TYPE); + sendByteMC(MOTOR_MOTOR3_BACKWARD); + sendByteMC(MOTOR_CONST_SPEED); +} +/* + * Turn rover left + */ +void MotorHandler::mc_left(){ + //Turn Left by driving the left motor only + + //motor 1 + sendByteMC(MOTOR_START_BYTE); + sendByteMC(MOTOR_DEVICE_TYPE); + sendByteMC(MOTOR_MOTOR2_FORWARD); + sendByteMC(MOTOR_CONST_SPEED); +} + +void MotorHandler::mc_right(){ + //Turn Right by driving right motor only + + //motor 1 + sendByteMC(MOTOR_START_BYTE); + sendByteMC(MOTOR_DEVICE_TYPE); + sendByteMC(MOTOR_MOTOR3_FORWARD); + sendByteMC(MOTOR_CONST_SPEED); +} +void MotorHandler::mc_stop(){ + //motor1 + sendByteMC(MOTOR_START_BYTE); + sendByteMC(MOTOR_DEVICE_TYPE); + sendByteMC(MOTOR_MOTOR2_FORWARD); + sendByteMC(MOTOR_STOP_SPEED); + //motor 2 + sendByteMC(MOTOR_START_BYTE); + sendByteMC(MOTOR_DEVICE_TYPE); + sendByteMC(MOTOR_MOTOR3_FORWARD); + sendByteMC(MOTOR_STOP_SPEED); +} diff --git a/MCandWifiTestDE0/Software/MCTest/MotorHandler.h b/MCandWifiTestDE0/Software/MCTest/MotorHandler.h new file mode 100644 index 00000000..873e3b97 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest/MotorHandler.h @@ -0,0 +1,32 @@ +/* + * MotorHandler.h + * + * Created on: 2014-03-03 + * Author: gongal + */ + +#ifndef MOTORHANDLER_H_ +#define MOTORHANDLER_H_ +#define MOTOR_START_BYTE 0x80 + +#define MOTOR_DEVICE_TYPE 0x00 +#define MOTOR_MOTOR2_BACKWARD 0x04 // motor 2 backward +#define MOTOR_MOTOR3_BACKWARD 0x06 //motor 3 backward +#define MOTOR_MOTOR2_FORWARD 0x05 // motor 2 forward +#define MOTOR_MOTOR3_FORWARD 0x07 // motor 3 forward +#define MOTOR_CONST_SPEED 0x5F +#define MOTOR_STOP_SPEED 0x00 + +class MotorHandler { +public: + MotorHandler(); + virtual ~MotorHandler(); + void sendByteMC(char msg); + void mc_forward(); + void mc_backward(); + void mc_right(); + void mc_left(); + void mc_stop(); +}; + +#endif /* MOTORHANDLER_H_ */ diff --git a/MCandWifiTestDE0/Software/MCTest/create-this-app b/MCandWifiTestDE0/Software/MCTest/create-this-app new file mode 100644 index 00000000..9dd2653f --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest/create-this-app @@ -0,0 +1,114 @@ +#!/bin/bash +# +# This script creates the hello_ucosii application in this directory. + + +BSP_DIR=../MCTest_bsp +QUARTUS_PROJECT_DIR=../../ +NIOS2_APP_GEN_ARGS="--elf-name MCTest.elf --set OBJDUMP_INCLUDE_SOURCE 1 --src-files hello_ucosii.c" + + +# First, check to see if $SOPC_KIT_NIOS2 environmental variable is set. +# This variable is required for the command line tools to execute correctly. +if [ -z "${SOPC_KIT_NIOS2}" ] +then + echo Required \$SOPC_KIT_NIOS2 Environmental Variable is not set! + exit 1 +fi + + +# Also make sure that the APP has not been created already. Check for +# existence of Makefile in the app directory +if [ -f ./Makefile ] +then + echo Application has already been created! Delete Makefile if you want to create a new application makefile + exit 1 +fi + + +# We are selecting ucosii_default bsp because it supports this application. +# Check to see if the ucosii_default has already been generated by checking for +# existence of the public.mk file. If not, we need to run +# create-this-bsp file to generate the bsp. +if [ ! -f ${BSP_DIR}/public.mk ]; then + # Since BSP doesn't exist, create the BSP + # Pass any command line arguments passed to this script to the BSP. + pushd ${BSP_DIR} >> /dev/null + ./create-this-bsp "$@" || { + echo "create-this-bsp failed" + exit 1 + } + popd >> /dev/null +fi + + +# Don't run make if create-this-app script is called with --no-make arg +SKIP_MAKE= +while [ $# -gt 0 ] +do + case "$1" in + --no-make) + SKIP_MAKE=1 + ;; + esac + shift +done + + +# Now we also need to go copy the sources for this application to the +# local directory. +find "${SOPC_KIT_NIOS2}/examples/software/hello_ucosii/" -name '*.c' -or -name '*.h' -or -name 'hostfs*' | xargs -i cp -L {} ./ || { + echo "failed during copying example source files" + exit 1 +} + +find "${SOPC_KIT_NIOS2}/examples/software/hello_ucosii/" -name 'readme.txt' -or -name 'Readme.txt' | xargs -i cp -L {} ./ || { + echo "failed copying readme file" +} + +if [ -d "${SOPC_KIT_NIOS2}/examples/software/hello_ucosii/system" ] +then + cp -RL "${SOPC_KIT_NIOS2}/examples/software/hello_ucosii/system" . || { + echo "failed during copying project support files" + exit 1 + } +fi + +chmod -R +w . || { + echo "failed during changing file permissions" + exit 1 +} + +cmd="nios2-app-generate-makefile --bsp-dir ${BSP_DIR} --set QUARTUS_PROJECT_DIR=${QUARTUS_PROJECT_DIR} ${NIOS2_APP_GEN_ARGS}" + +echo "create-this-app: Running \"${cmd}\"" +$cmd || { + echo "nios2-app-generate-makefile failed" + exit 1 +} + +if [ -z "$SKIP_MAKE" ]; then + cmd="make" + + echo "create-this-app: Running \"$cmd\"" + $cmd || { + echo "make failed" + exit 1 + } + + echo + echo "To download and run the application:" + echo " 1. Make sure the board is connected to the system." + echo " 2. Run 'nios2-configure-sof ' to configure the FPGA with the hardware design." + echo " 3. If you have a stdio device, run 'nios2-terminal' in a different shell." + echo " 4. Run 'make download-elf' from the application directory." + echo + echo "To debug the application:" + echo " Import the project into Nios II Software Build Tools for Eclipse." + echo " Refer to Nios II Software Build Tools for Eclipse Documentation for more information." + echo + echo -e "" +fi + + +exit 0 diff --git a/MCandWifiTestDE0/Software/MCTest/main.cpp b/MCandWifiTestDE0/Software/MCTest/main.cpp new file mode 100644 index 00000000..69caa508 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest/main.cpp @@ -0,0 +1,214 @@ +/************************************************************************* + * ARCap + * Amshu Gongal, Kenan Kigunda + * February 18, 2014 + ************************************************************************** + * Description: * + * Prototype testing for infrared and wifi. + **************************************************************************/ + +#include +#include "includes.h" +#include "altera_avalon_pio_regs.h" +#include "altera_avalon_uart_regs.h" +#include "sys/alt_irq.h" +#include "alt_types.h" +#include "MotorHandler.h" + +MotorHandler * motorHandler = new MotorHandler(); +/* Task stacks */ +#define TASK_STACKSIZE 2048 +OS_STK ir_task_stk[TASK_STACKSIZE]; +OS_STK wifi_task_stk[TASK_STACKSIZE]; +OS_STK mc_task_stk[TASK_STACKSIZE]; +/* Task priorities */ +#define IR_TASK_PRIORITY 1 +#define WIFI_TASK_PRIORITY 2 +#define MC_TASK_PRIORITY 2 + + +/* Error status */ +#define OK 0 + +/* Message queues */ +#define WAIT_FOREVER 0 + +// ==== INFRARED ==== + +/* Infrared message queue */ +#define IR_MAX_MESSAGES 4 +int ir_messages[IR_MAX_MESSAGES]; +OS_EVENT *ir_queue; + +/* Infrared messages */ +// Together these avoid passing 0 to the queue (which is not allowed since queue messages cannot be null) +// and invert pushbutton input (since the pushbutton returns 0 when it is pushed down). +#define IR_QUEUE_SEND_BASE 1 // Use: IR_QUEUE_SEND_BASE + IORD +#define IR_QUEUE_RECEIVE_BASE 2 // Use: IR_QUEUE_RECEIVE_BASE - OSQPend + + +/* Interrupt service routine triggered whenever the status of the IR emitter pushbutton changes. */ +static void isr_on_ir_pushbutton(void * context) { + // Read the state of the pushbutton and post it to the queue. + //printf("Pressed\n"); + int message = IR_QUEUE_SEND_BASE + IORD_ALTERA_AVALON_PIO_DATA(PIO_KEY_LEFT_BASE); + OSQPost(ir_queue, (void*)message); + // Mask to mark the end of the ISR. + IOWR_ALTERA_AVALON_PIO_EDGE_CAP(PIO_KEY_LEFT_BASE, PIO_KEY_LEFT_BIT_CLEARING_EDGE_REGISTER); +} + +/* Controllers the IR emitter based on the value of the pushbutton. */ +void ir_task(void* pdata) +{ + INT8U err; + while (1) + { + // Read the value from the queue. + int status = IR_QUEUE_RECEIVE_BASE - (int)OSQPend(ir_queue, WAIT_FOREVER, &err); + if (err == OS_NO_ERR) { + // Print the result and send it to the emitter. + printf("IR: %d\n", status); + IOWR_ALTERA_AVALON_PIO_DATA(PIO_IR_EMITTER_BASE, status); + } + } +} + +// ==== WIFI + +#define WIFI_GUARD_TIME 1 + +void wifi_wait() { + OSTimeDlyHMSM(0, 0, WIFI_GUARD_TIME, 0); +} + +void wifi_write(char *message, int length) { + int i; + for (i = 0; i < length; i++) { + IOWR_ALTERA_AVALON_UART_TXDATA(UART_WIFI_BASE, message[i]); + } +} + +void wifi_read() { + int status = IORD_ALTERA_AVALON_UART_STATUS(UART_WIFI_BASE); + printf("Wifi status: %d\n", status); + char c = IORD_ALTERA_AVALON_UART_RXDATA(UART_WIFI_BASE); + printf("Wifi: %c\n", c); +} + +void wifi_task(void *pdata) +{ + printf("Started wifi task\n"); + wifi_wait(); + wifi_write("+++", 3); + wifi_wait(); + wifi_read(); +} + + + +// ==== MC + + +//====MotorContoller +void mc_task(void *pdata) +{ + motorHandler->mc_forward(); + OSTimeDlyHMSM(0, 0, 4, 0); + motorHandler->mc_stop(); +} + +// ==== GENERAL + +void queue_init() { + ir_queue = OSQCreate((void**)&ir_messages, IR_MAX_MESSAGES); +} + +/* The main function creates the LCD task, registers the edge counter polling interrupt, + * and starts the OS. */ +int main(void) +{ + int status; + // Initialize components. + queue_init(); + + // Create the IR task. + OSTaskCreateExt(ir_task, + NULL, + &ir_task_stk[TASK_STACKSIZE - 1], + IR_TASK_PRIORITY, + IR_TASK_PRIORITY, + ir_task_stk, + TASK_STACKSIZE, + NULL, + 0); + + // Create the Wifi task. + OSTaskCreateExt(wifi_task, + NULL, + &wifi_task_stk[TASK_STACKSIZE - 1], + WIFI_TASK_PRIORITY, + WIFI_TASK_PRIORITY, + wifi_task_stk, + TASK_STACKSIZE, + NULL, + 0); + + // Create the MC task. + OSTaskCreateExt(mc_task, + NULL, + &mc_task_stk[TASK_STACKSIZE - 1], + MC_TASK_PRIORITY, + MC_TASK_PRIORITY, + mc_task_stk, + TASK_STACKSIZE, + NULL, + 0); + + // Register the IR pushbutton interrupt. + /*status = alt_ic_isr_register(PIO_KEY_LEFT_IRQ_INTERRUPT_CONTROLLER_ID, + PIO_KEY_LEFT_IRQ, + isr_on_ir_pushbutton, + NULL, + NULL);*/ + + // Enable key interrupts. + IOWR_ALTERA_AVALON_PIO_IRQ_MASK(PIO_KEY_LEFT_BASE, PIO_KEY_LEFT_CAPTURE); + + // Start. + if (status == OK) { + OSStart(); + } + + return 0; +} + +/****************************************************************************** + * * + * License Agreement * + * * + * Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * + * All rights reserved. * + * * + * Permission is hereby granted, free of charge, to any person obtaining a * + * copy of this software and associated documentation files (the "Software"), * + * to deal in the Software without restriction, including without limitation * + * the rights to use, copy, modify, merge, publish, distribute, sublicense, * + * and/or sell copies of the Software, and to permit persons to whom the * + * Software is furnished to do so, subject to the following conditions: * + * * + * The above copyright notice and this permission notice shall be included in * + * all copies or substantial portions of the Software. * + * * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * + * DEALINGS IN THE SOFTWARE. * + * * + * This agreement shall be governed in all respects by the laws of the State * + * of California and by the laws of the United States of America. * + * Altera does not recommend, suggest or require that this reference design * + * file be used in conjunction or combination with any other product. * + ******************************************************************************/ diff --git a/MCandWifiTestDE0/Software/MCTest/obj/default/MotorHandler.d b/MCandWifiTestDE0/Software/MCTest/obj/default/MotorHandler.d new file mode 100644 index 00000000..127e673c --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest/obj/default/MotorHandler.d @@ -0,0 +1,63 @@ +obj/default/MotorHandler.o: MotorHandler.cpp MotorHandler.h \ + ../MCTest_bsp//HAL/inc/includes.h ../MCTest_bsp//HAL/inc/os_cpu.h \ + ../MCTest_bsp//HAL/inc/sys/alt_irq.h ../MCTest_bsp//HAL/inc/nios2.h \ + ../MCTest_bsp//HAL/inc/alt_types.h ../MCTest_bsp/system.h \ + ../MCTest_bsp/linker.h ../MCTest_bsp//HAL/inc/priv/alt_legacy_irq.h \ + ../MCTest_bsp/system.h ../MCTest_bsp//HAL/inc/nios2.h \ + ../MCTest_bsp//HAL/inc/alt_types.h ../MCTest_bsp//HAL/inc/sys/alt_irq.h \ + ../MCTest_bsp//UCOSII/inc/os_cfg.h \ + ../MCTest_bsp//HAL/inc/sys/alt_alarm.h \ + ../MCTest_bsp//HAL/inc/sys/alt_llist.h \ + ../MCTest_bsp//HAL/inc/priv/alt_alarm.h ../MCTest_bsp/system.h \ + ../MCTest_bsp//UCOSII/inc/ucos_ii.h ../MCTest_bsp//UCOSII/inc/os_cfg.h \ + ../MCTest_bsp//HAL/inc/os_cpu.h \ + ../MCTest_bsp//drivers/inc/altera_avalon_uart_regs.h \ + ../MCTest_bsp//HAL/inc/io.h ../MCTest_bsp//HAL/inc/alt_types.h + +MotorHandler.h: + +../MCTest_bsp//HAL/inc/includes.h: + +../MCTest_bsp//HAL/inc/os_cpu.h: + +../MCTest_bsp//HAL/inc/sys/alt_irq.h: + +../MCTest_bsp//HAL/inc/nios2.h: + +../MCTest_bsp//HAL/inc/alt_types.h: + +../MCTest_bsp/system.h: + +../MCTest_bsp/linker.h: + +../MCTest_bsp//HAL/inc/priv/alt_legacy_irq.h: + +../MCTest_bsp/system.h: + +../MCTest_bsp//HAL/inc/nios2.h: + +../MCTest_bsp//HAL/inc/alt_types.h: + +../MCTest_bsp//HAL/inc/sys/alt_irq.h: + +../MCTest_bsp//UCOSII/inc/os_cfg.h: + +../MCTest_bsp//HAL/inc/sys/alt_alarm.h: + +../MCTest_bsp//HAL/inc/sys/alt_llist.h: + +../MCTest_bsp//HAL/inc/priv/alt_alarm.h: + +../MCTest_bsp/system.h: + +../MCTest_bsp//UCOSII/inc/ucos_ii.h: + +../MCTest_bsp//UCOSII/inc/os_cfg.h: + +../MCTest_bsp//HAL/inc/os_cpu.h: + +../MCTest_bsp//drivers/inc/altera_avalon_uart_regs.h: + +../MCTest_bsp//HAL/inc/io.h: + +../MCTest_bsp//HAL/inc/alt_types.h: diff --git a/MCandWifiTestDE0/Software/MCTest/obj/default/MotorHandler.o b/MCandWifiTestDE0/Software/MCTest/obj/default/MotorHandler.o new file mode 100644 index 00000000..13df8bf0 Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest/obj/default/MotorHandler.o differ diff --git a/MCandWifiTestDE0/Software/MCTest/obj/default/main.d b/MCandWifiTestDE0/Software/MCTest/obj/default/main.d new file mode 100644 index 00000000..c2d7a3a3 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest/obj/default/main.d @@ -0,0 +1,71 @@ +obj/default/main.o: main.cpp ../MCTest_bsp//HAL/inc/includes.h \ + ../MCTest_bsp//HAL/inc/os_cpu.h ../MCTest_bsp//HAL/inc/sys/alt_irq.h \ + ../MCTest_bsp//HAL/inc/nios2.h ../MCTest_bsp//HAL/inc/alt_types.h \ + ../MCTest_bsp/system.h ../MCTest_bsp/linker.h \ + ../MCTest_bsp//HAL/inc/priv/alt_legacy_irq.h ../MCTest_bsp/system.h \ + ../MCTest_bsp//HAL/inc/nios2.h ../MCTest_bsp//HAL/inc/alt_types.h \ + ../MCTest_bsp//HAL/inc/sys/alt_irq.h ../MCTest_bsp//UCOSII/inc/os_cfg.h \ + ../MCTest_bsp//HAL/inc/sys/alt_alarm.h \ + ../MCTest_bsp//HAL/inc/sys/alt_llist.h \ + ../MCTest_bsp//HAL/inc/priv/alt_alarm.h ../MCTest_bsp/system.h \ + ../MCTest_bsp//UCOSII/inc/ucos_ii.h ../MCTest_bsp//UCOSII/inc/os_cfg.h \ + ../MCTest_bsp//HAL/inc/os_cpu.h \ + ../MCTest_bsp//drivers/inc/altera_avalon_pio_regs.h \ + ../MCTest_bsp//HAL/inc/io.h ../MCTest_bsp//HAL/inc/alt_types.h \ + ../MCTest_bsp//drivers/inc/altera_avalon_uart_regs.h \ + ../MCTest_bsp//HAL/inc/sys/alt_irq.h ../MCTest_bsp//HAL/inc/alt_types.h \ + MotorHandler.h + +../MCTest_bsp//HAL/inc/includes.h: + +../MCTest_bsp//HAL/inc/os_cpu.h: + +../MCTest_bsp//HAL/inc/sys/alt_irq.h: + +../MCTest_bsp//HAL/inc/nios2.h: + +../MCTest_bsp//HAL/inc/alt_types.h: + +../MCTest_bsp/system.h: + +../MCTest_bsp/linker.h: + +../MCTest_bsp//HAL/inc/priv/alt_legacy_irq.h: + +../MCTest_bsp/system.h: + +../MCTest_bsp//HAL/inc/nios2.h: + +../MCTest_bsp//HAL/inc/alt_types.h: + +../MCTest_bsp//HAL/inc/sys/alt_irq.h: + +../MCTest_bsp//UCOSII/inc/os_cfg.h: + +../MCTest_bsp//HAL/inc/sys/alt_alarm.h: + +../MCTest_bsp//HAL/inc/sys/alt_llist.h: + +../MCTest_bsp//HAL/inc/priv/alt_alarm.h: + +../MCTest_bsp/system.h: + +../MCTest_bsp//UCOSII/inc/ucos_ii.h: + +../MCTest_bsp//UCOSII/inc/os_cfg.h: + +../MCTest_bsp//HAL/inc/os_cpu.h: + +../MCTest_bsp//drivers/inc/altera_avalon_pio_regs.h: + +../MCTest_bsp//HAL/inc/io.h: + +../MCTest_bsp//HAL/inc/alt_types.h: + +../MCTest_bsp//drivers/inc/altera_avalon_uart_regs.h: + +../MCTest_bsp//HAL/inc/sys/alt_irq.h: + +../MCTest_bsp//HAL/inc/alt_types.h: + +MotorHandler.h: diff --git a/MCandWifiTestDE0/Software/MCTest/obj/default/main.o b/MCandWifiTestDE0/Software/MCTest/obj/default/main.o new file mode 100644 index 00000000..f7dec039 Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest/obj/default/main.o differ diff --git a/MCandWifiTestDE0/Software/MCTest/readme.txt b/MCandWifiTestDE0/Software/MCTest/readme.txt new file mode 100644 index 00000000..49e8390f --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest/readme.txt @@ -0,0 +1,7 @@ +Readme - Hello MicroC/OS-II Hello Software Example + +Hello_uosii is a simple hello world program running MicroC/OS-II. The +purpose of the design is to be a very simple application that just +demonstrates MicroC/OS-II running on NIOS II. The design doesn't account +for issues such as checking system call return codes. etc. + diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/.cproject b/MCandWifiTestDE0/Software/MCTest_bsp/.cproject new file mode 100644 index 00000000..5141e477 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/.cproject @@ -0,0 +1,481 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/.project b/MCandWifiTestDE0/Software/MCTest_bsp/.project new file mode 100644 index 00000000..bebef029 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/.project @@ -0,0 +1,85 @@ + + + MCTest_bsp + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + + + + org.eclipse.cdt.make.core.buildCommand + make + + + org.eclipse.cdt.make.core.buildLocation + ${workspace_loc://MCTest_bsp} + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + org.eclipse.cdt.core.ccnature + com.altera.sbtgui.project.SBTGUINature + com.altera.sbtgui.project.SBTGUIBspNature + + diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/alt_types.h b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/alt_types.h new file mode 100644 index 00000000..d02f1716 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/alt_types.h @@ -0,0 +1,54 @@ +#ifndef __ALT_TYPES_H__ +#define __ALT_TYPES_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/* + * Don't declare these typedefs if this file is included by assembly source. + */ +#ifndef ALT_ASM_SRC +typedef signed char alt_8; +typedef unsigned char alt_u8; +typedef signed short alt_16; +typedef unsigned short alt_u16; +typedef signed long alt_32; +typedef unsigned long alt_u32; +typedef long long alt_64; +typedef unsigned long long alt_u64; +#endif + +#define ALT_INLINE __inline__ +#define ALT_ALWAYS_INLINE __attribute__ ((always_inline)) +#define ALT_WEAK __attribute__((weak)) + +#endif /* __ALT_TYPES_H__ */ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/altera_nios2_qsys_irq.h b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/altera_nios2_qsys_irq.h new file mode 100644 index 00000000..6629ec9f --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/altera_nios2_qsys_irq.h @@ -0,0 +1,80 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2009 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +/* + * Support for the Nios II internal interrupt controller. + */ + +#ifndef __ALT_NIOS2_QSYS_IRQ_H__ +#define __ALT_NIOS2_QSYS_IRQ_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * The macro ALTERA_NIOS2_IRQ_INSTANCE is used by the alt_irq_init() + * function in the auto-generated file alt_sys_init.c to create an + * instance of this interrupt controller device driver state if this + * module contains an interrupt controller. + * Only one instance of a Nios II is allowed so this macro is just empty. + */ + +#define ALTERA_NIOS2_QSYS_IRQ_INSTANCE(name, state) + +/* + * altera_nios2_irq_init() is called by the auto-generated function + * alt_irq_init() once for the Nios II if it contains an interrupt controller. + * The altera_nios2_irq_init() routine is called using the + * ALTERA_NIOS2_IRQ_INIT macro given below. + * + * This function initializes the internal interrupt controller + * so is not called if the Nios II contains an external interrupt + * controller port (because the internal interrupt controller + * is removed if this port is present). + */ + +extern void altera_nios2_qsys_irq_init( void ); + +/* + * The macro ALTERA_NIOS2_IRQ_INIT is used by the alt_irq_init() routine + * in the auto-generated file alt_sys_init.c to initialize an instance + * of the interrupt controller device driver state. + */ + +#define ALTERA_NIOS2_QSYS_IRQ_INIT(name, state) altera_nios2_qsys_irq_init() + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALT_NIOS2_QSYS_IRQ_H__ */ + diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/includes.h b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/includes.h new file mode 100644 index 00000000..0f515b04 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/includes.h @@ -0,0 +1,65 @@ +#ifndef __INCLUDES_H__ +#define __INCLUDES_H__ + +/* +********************************************************************************************************* +* uC/OS-II +* The Real-Time Kernel +* +* (c) Copyright 1992-1998, Jean J. Labrosse, Plantation, FL +* All Rights Reserved +* +* MASTER INCLUDE FILE +********************************************************************************************************* +*/ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +#include "os_cpu.h" +#include "os_cfg.h" +#include "ucos_ii.h" + +#ifdef ONT_GLOBALS +#define ONT_EXT +#else +#define ONT_EXT extern +#endif + +/* +********************************************************************************************************* +* DATA TYPES +********************************************************************************************************* +*/ + +typedef struct { + char TaskName[30]; + INT16U TaskCtr; + INT16U TaskExecTime; + INT32U TaskTotExecTime; +} TASK_USER_DATA; + +/* +********************************************************************************************************* +* VARIABLES +********************************************************************************************************* +*/ + +ONT_EXT TASK_USER_DATA TaskUserData[10]; + +/* +********************************************************************************************************* +* FUNCTION PROTOTYPES +********************************************************************************************************* +*/ + +void DispTaskStat(INT8U id); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __INCLUDES_H__ */ + diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/io.h b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/io.h new file mode 100644 index 00000000..362f1034 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/io.h @@ -0,0 +1,81 @@ +#ifndef __IO_H__ +#define __IO_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/* IO Header file for Nios II Toolchain */ + +#include "alt_types.h" +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +#ifndef SYSTEM_BUS_WIDTH +#error SYSTEM_BUS_WIDTH undefined +#endif + +/* Dynamic bus access functions */ + +#define __IO_CALC_ADDRESS_DYNAMIC(BASE, OFFSET) \ + ((void *)(((alt_u8*)BASE) + (OFFSET))) + +#define IORD_32DIRECT(BASE, OFFSET) \ + __builtin_ldwio (__IO_CALC_ADDRESS_DYNAMIC ((BASE), (OFFSET))) +#define IORD_16DIRECT(BASE, OFFSET) \ + __builtin_ldhuio (__IO_CALC_ADDRESS_DYNAMIC ((BASE), (OFFSET))) +#define IORD_8DIRECT(BASE, OFFSET) \ + __builtin_ldbuio (__IO_CALC_ADDRESS_DYNAMIC ((BASE), (OFFSET))) + +#define IOWR_32DIRECT(BASE, OFFSET, DATA) \ + __builtin_stwio (__IO_CALC_ADDRESS_DYNAMIC ((BASE), (OFFSET)), (DATA)) +#define IOWR_16DIRECT(BASE, OFFSET, DATA) \ + __builtin_sthio (__IO_CALC_ADDRESS_DYNAMIC ((BASE), (OFFSET)), (DATA)) +#define IOWR_8DIRECT(BASE, OFFSET, DATA) \ + __builtin_stbio (__IO_CALC_ADDRESS_DYNAMIC ((BASE), (OFFSET)), (DATA)) + +/* Native bus access functions */ + +#define __IO_CALC_ADDRESS_NATIVE(BASE, REGNUM) \ + ((void *)(((alt_u8*)BASE) + ((REGNUM) * (SYSTEM_BUS_WIDTH/8)))) + +#define IORD(BASE, REGNUM) \ + __builtin_ldwio (__IO_CALC_ADDRESS_NATIVE ((BASE), (REGNUM))) +#define IOWR(BASE, REGNUM, DATA) \ + __builtin_stwio (__IO_CALC_ADDRESS_NATIVE ((BASE), (REGNUM)), (DATA)) + +#ifdef __cplusplus +} +#endif + +#endif /* __IO_H__ */ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/nios2.h b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/nios2.h new file mode 100644 index 00000000..72cefba0 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/nios2.h @@ -0,0 +1,230 @@ +#ifndef __NIOS2_H__ +#define __NIOS2_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2008 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +/* + * This header provides processor specific macros for accessing the Nios2 + * control registers. + */ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Macros for accessing selected processor registers + */ + +#define NIOS2_READ_ET(et) \ + do { __asm ("mov %0, et" : "=r" (et) ); } while (0) + +#define NIOS2_WRITE_ET(et) \ + do { __asm volatile ("mov et, %z0" : : "rM" (et)); } while (0) + +#define NIOS2_READ_SP(sp) \ + do { __asm ("mov %0, sp" : "=r" (sp) ); } while (0) + +/* + * Macros for useful processor instructions + */ + +#define NIOS2_BREAK() \ + do { __asm volatile ("break"); } while (0) + +#define NIOS2_REPORT_STACK_OVERFLOW() \ + do { __asm volatile("break 3"); } while (0) + +/* + * Macros for accessing the control registers. + */ + +#define NIOS2_READ_STATUS(dest) \ + do { dest = __builtin_rdctl(0); } while (0) + +#define NIOS2_WRITE_STATUS(src) \ + do { __builtin_wrctl(0, src); } while (0) + +#define NIOS2_READ_ESTATUS(dest) \ + do { dest = __builtin_rdctl(1); } while (0) + +#define NIOS2_READ_BSTATUS(dest) \ + do { dest = __builtin_rdctl(2); } while (0) + +#define NIOS2_READ_IENABLE(dest) \ + do { dest = __builtin_rdctl(3); } while (0) + +#define NIOS2_WRITE_IENABLE(src) \ + do { __builtin_wrctl(3, src); } while (0) + +#define NIOS2_READ_IPENDING(dest) \ + do { dest = __builtin_rdctl(4); } while (0) + +#define NIOS2_READ_CPUID(dest) \ + do { dest = __builtin_rdctl(5); } while (0) + + +/* + * Macros for accessing extra exception registers. These + * are always enabled wit the MPU or MMU, and optionally + * with other advanced exception types/ + */ +#define NIOS2_READ_EXCEPTION(dest) \ + do { dest = __builtin_rdctl(7); } while (0) + +#define NIOS2_READ_BADADDR(dest) \ + do { dest = __builtin_rdctl(12); } while (0) + + +/* + * Macros for accessing control registers for MPU + * operation. These should not be used unless the + * MPU is enabled. + * + * The config register may be augmented for future + * enhancements. For now, only MPU support is provided. + */ +/* Config register */ +#define NIOS2_WRITE_CONFIG(src) \ + do { __builtin_wrctl(13, src); } while (0) + +#define NIOS2_READ_CONFIG(dest) \ + do { dest = __builtin_rdctl(13); } while (0) + +/* MPU Base Address Register */ +#define NIOS2_WRITE_MPUBASE(src) \ + do { __builtin_wrctl(14, src); } while (0) + +#define NIOS2_READ_MPUBASE(dest) \ + do { dest = __builtin_rdctl(14); } while (0) + +/* MPU Access Register */ +#define NIOS2_WRITE_MPUACC(src) \ + do { __builtin_wrctl(15, src); } while (0) + +#define NIOS2_READ_MPUACC(dest) \ + do { dest = __builtin_rdctl(15); } while (0) + + +/* + * Nios II control registers that are always present + */ +#define NIOS2_STATUS status +#define NIOS2_ESTATUS estatus +#define NIOS2_BSTATUS bstatus +#define NIOS2_IENABLE ienable +#define NIOS2_IPENDING ipending +#define NIOS2_CPUID cpuid + +/* + * STATUS, BSTATUS, ESTATUS, and SSTATUS fields. + * The presence of fields is a function of the Nios II configuration. + */ +#define NIOS2_STATUS_PIE_MSK (0x00000001) +#define NIOS2_STATUS_PIE_OFST (0) +#define NIOS2_STATUS_U_MSK (0x00000002) +#define NIOS2_STATUS_U_OFST (1) +#define NIOS2_STATUS_EH_MSK (0x00000004) +#define NIOS2_STATUS_EH_OFST (2) +#define NIOS2_STATUS_IH_MSK (0x00000008) +#define NIOS2_STATUS_IH_OFST (3) +#define NIOS2_STATUS_IL_MSK (0x000003f0) +#define NIOS2_STATUS_IL_OFST (4) +#define NIOS2_STATUS_CRS_MSK (0x0000fc00) +#define NIOS2_STATUS_CRS_OFST (10) +#define NIOS2_STATUS_PRS_MSK (0x003f0000) +#define NIOS2_STATUS_PRS_OFST (16) +#define NIOS2_STATUS_NMI_MSK (0x00400000) +#define NIOS2_STATUS_NMI_OFST (22) +#define NIOS2_STATUS_RSIE_MSK (0x00800000) +#define NIOS2_STATUS_RSIE_OFST (23) +#define NIOS2_STATUS_SRS_MSK (0x80000000) +#define NIOS2_STATUS_SRS_OFST (31) + +/* + * Bit masks & offsets available with extra exceptions support + */ + +/* Exception register */ +#define NIOS2_EXCEPTION_REG_CAUSE_MASK (0x0000007c) +#define NIOS2_EXCEPTION_REG_CAUSE_OFST (2) + +/* + * Bit masks & offsets for MPU support + * + * All bit-masks are expressed relative to the position + * of the data with a register. To read data that is LSB- + * aligned, the register read data should be masked, then + * right-shifted by the designated "OFST" macro value. The + * opposite should be used for register writes when starting + * with LSB-aligned data. + */ + +/* Config register */ +#define NIOS2_CONFIG_REG_PE_MASK (0x00000001) +#define NIOS2_CONFIG_REG_PE_OFST (0) +#define NIOS2_CONFIG_REG_ANI_MASK (0x00000002) +#define NIOS2_CONFIG_REG_ANI_OFST (1) + +/* MPU Base Address Register */ +#define NIOS2_MPUBASE_D_MASK (0x00000001) +#define NIOS2_MPUBASE_D_OFST (0) +#define NIOS2_MPUBASE_INDEX_MASK (0x0000003e) +#define NIOS2_MPUBASE_INDEX_OFST (1) +#define NIOS2_MPUBASE_BASE_ADDR_MASK (0xffffffc0) +#define NIOS2_MPUBASE_BASE_ADDR_OFST (6) + +/* MPU Access Register */ +#define NIOS2_MPUACC_LIMIT_MASK (0xffffffc0) +#define NIOS2_MPUACC_LIMIT_OFST (6) +#define NIOS2_MPUACC_MASK_MASK (0xffffffc0) +#define NIOS2_MPUACC_MASK_OFST (6) +#define NIOS2_MPUACC_C_MASK (0x00000020) +#define NIOS2_MPUACC_C_OFST (5) +#define NIOS2_MPUACC_PERM_MASK (0x0000001c) +#define NIOS2_MPUACC_PERM_OFST (2) +#define NIOS2_MPUACC_RD_MASK (0x00000002) +#define NIOS2_MPUACC_RD_OFST (1) +#define NIOS2_MPUACC_WR_MASK (0x00000001) +#define NIOS2_MPUACC_WR_OFST (0) + +/* + * Number of available IRQs in internal interrupt controller. + */ +#define NIOS2_NIRQ 32 + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __NIOS2_H__ */ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/os/alt_syscall.h b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/os/alt_syscall.h new file mode 100644 index 00000000..507c6aa2 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/os/alt_syscall.h @@ -0,0 +1,75 @@ +#ifndef __ALT_SYSCALL_H__ +#define __ALT_SYSCALL_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +/* + * The macros defined in this file are used to provide the function names used + * for the HAL 'UNIX style' interface, e.g. read(), write() etc. + * + * Operating systems which are ported to the HAL can provide their own + * version of this file, which will be used in preference. This allows + * the operating system to provide it's own implementation of the top level + * system calls, while retaining the HAL functions under a different name, + * for example, alt_read(), alt_write() etc. + */ + +#define ALT_CLOSE close +#define ALT_ENVIRON environ +#define ALT_EXECVE execve +#define ALT_EXIT _exit +#define ALT_FCNTL fcntl +#define ALT_FORK fork +#define ALT_FSTAT fstat +#define ALT_GETPID getpid +#define ALT_GETTIMEOFDAY gettimeofday +#define ALT_IOCTL ioctl +#define ALT_ISATTY isatty +#define ALT_KILL kill +#define ALT_LINK link +#define ALT_LSEEK lseek +#define ALT_OPEN open +#define ALT_READ read +#define ALT_RENAME _rename +#define ALT_SBRK sbrk +#define ALT_SETTIMEOFDAY settimeofday +#define ALT_STAT stat +#define ALT_UNLINK unlink +#define ALT_USLEEP usleep +#define ALT_WAIT wait +#define ALT_WRITE write +#define ALT_TIMES times + +/* + * + */ + +#endif /* __ALT_SYSCALL_H__ */ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/os_cpu.h b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/os_cpu.h new file mode 100644 index 00000000..cab12115 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/os_cpu.h @@ -0,0 +1,145 @@ +#ifndef __OS_CPU_H__ +#define __OS_CPU_H__ + +/* +********************************************************************************************************* +* uC/OS-II +* The Real-Time Kernel +* +* (c) Copyright 1992-1999, Jean J. Labrosse, Weston, FL +* All Rights Reserved +* +* 80x86/80x88 Specific code +* LARGE MEMORY MODEL +* +* Borland C/C++ V4.51 +* +* File : OS_CPU.H +* By : IS (modified from version by Jean J. Labrosse) +********************************************************************************************************* +*/ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003-5 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +#include "sys/alt_irq.h" + +#ifdef OS_CPU_GLOBALS +#define OS_CPU_EXT +#else +#define OS_CPU_EXT extern +#endif + +/***************************************************************************************** +/ REVISION HISTORY +/ +*****************************************************************************************/ + +/***************************************************************************************** +/ DATA TYPES +/ (Compiler Specific) +*****************************************************************************************/ + +/* This is the definition for Nios32. */ +typedef unsigned char BOOLEAN; +typedef unsigned char INT8U; /* Unsigned 8 bit quantity */ +typedef signed char INT8S; /* Signed 8 bit quantity */ +typedef unsigned short INT16U; /* Unsigned 16 bit quantity */ +typedef signed short INT16S; /* Signed 16 bit quantity */ +typedef unsigned long INT32U; /* Unsigned 32 bit quantity */ +typedef signed long INT32S; /* Signed 32 bit quantity */ +typedef float FP32; /* Single precision floating point */ +typedef double FP64; /* Double precision floating point */ +typedef unsigned int OS_STK; /* Each stack entry is 32-bits */ + +/**************************************************************************** +* Nios2 Miscellaneous defines +****************************************************************************/ + +#define OS_STK_GROWTH 1 /* Stack grows from HIGH to LOW memory */ +#define OS_TASK_SW OSCtxSw + +/****************************************************************************************** + * Disable and Enable Interrupts - 2 methods + * + * Method #1: Disable/Enable interrupts using simple instructions. After critical + * section, interrupts will be enabled even if they were disabled before + * entering the critical section. + * + * Method #2: Disable/Enable interrupts by preserving the state of interrupts. In + * other words, if interrupts were disabled before entering the critical + * section, they will be disabled when leaving the critical section. + * + * Method #3: Disable/Enable interrupts by preserving the state of interrupts. Generally speaking you + * would store the state of the interrupt disable flag in the local variable 'cpu_sr' and then + * disable interrupts. 'cpu_sr' is allocated in all of uC/OS-II's functions that need to + * disable interrupts. You would restore the interrupt disable state by copying back 'cpu_sr' + * into the CPU's status register. + * + *****************************************************************************************/ + +#define OS_CRITICAL_METHOD 3 + +#if OS_CRITICAL_METHOD == 1 +#error OS_CRITICAL_METHOD == 1 not supported, please use method 3 instead. +#endif + +#if OS_CRITICAL_METHOD == 2 +#error OS_CRITICAL_METHOD == 2 not supported, please use method 3 instead. +#endif + +#if OS_CRITICAL_METHOD == 3 +#define OS_CPU_SR alt_irq_context +#define OS_ENTER_CRITICAL() \ + cpu_sr = alt_irq_disable_all () +#define OS_EXIT_CRITICAL() \ + alt_irq_enable_all (cpu_sr); +#endif + +/* Prototypes */ +void OSStartHighRdy(void); +void OSCtxSw(void); +void OSIntCtxSw(void); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __OS_CPU_H__ */ + + + diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/priv/alt_alarm.h b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/priv/alt_alarm.h new file mode 100644 index 00000000..45d6a0e5 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/priv/alt_alarm.h @@ -0,0 +1,101 @@ +#ifndef __ALT_PRIV_ALARM_H__ +#define __ALT_PRIV_ALARM_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +#include "alt_types.h" + +/* + * This header provides the internal defenitions required by the public + * interface alt_alarm.h. These variables and structures are not guaranteed to + * exist in future implementations of the HAL. + */ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * "alt_alarm_s" is a structure type used to maintain lists of alarm callback + * functions. + */ + +struct alt_alarm_s +{ + alt_llist llist; /* linked list */ + alt_u32 time; /* time in system ticks of the callback */ + alt_u32 (*callback) (void* context); /* callback function. The return + * value is the period for the next callback; where + * zero indicates that the alarm should be removed + * from the list. + */ + alt_u8 rollover; /* set when desired alarm time + current time causes + overflow, to prevent premature alarm */ + void* context; /* Argument for the callback */ +}; + +/* + * "_alt_tick_rate" is a global variable used to store the system clock rate + * in ticks per second. This is initialised to zero, which coresponds to there + * being no system clock available. + * + * It is then set to it's final value by the system clock driver through a call + * to alt_sysclk_init(). + */ + +extern alt_u32 _alt_tick_rate; + +/* + * "_alt_nticks" is a global variable which records the elapsed number of + * system clock ticks since the last call to settimeofday() or since reset if + * settimeofday() has not been called. + */ + +extern volatile alt_u32 _alt_nticks; + +/* The list of registered alarms. */ + +extern alt_llist alt_alarm_list; + +#ifdef __cplusplus +} +#endif + +#endif /* __ALT_PRIV_ALARM_H__ */ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/priv/alt_busy_sleep.h b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/priv/alt_busy_sleep.h new file mode 100644 index 00000000..b1af8499 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/priv/alt_busy_sleep.h @@ -0,0 +1,35 @@ +#ifndef __ALT_BUSY_SLEEP_H +#define __ALT_BUSY_SLEEP_H + +/* + * Copyright (c) 2003 Altera Corporation, San Jose, California, USA. + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/* + * The function alt_busy_sleep provides a busy loop implementation of usleep. + * This is used to provide usleep for the standalone HAL, or when the timer is + * unavailable in uC/OS-II. + */ + +extern unsigned int alt_busy_sleep (unsigned int us); + +#endif /* __ALT_BUSY_SLEEP_H */ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/priv/alt_dev_llist.h b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/priv/alt_dev_llist.h new file mode 100644 index 00000000..451b063d --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/priv/alt_dev_llist.h @@ -0,0 +1,77 @@ +#ifndef __ALT_DEV_LLIST_H__ +#define __ALT_DEV_LLIST_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +#include "sys/alt_llist.h" +#include "alt_types.h" + +/* + * This header provides the internal defenitions required to control file + * access. These variables and functions are not guaranteed to exist in + * future implementations of the HAL. + */ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * The alt_dev_llist is an internal structure used to form a common base + * class for all device types. The use of this structure allows common code + * to be used to manipulate the various device lists. + */ + +typedef struct { + alt_llist llist; + const char* name; +} alt_dev_llist; + +/* + * + */ + +extern int alt_dev_llist_insert (alt_dev_llist* dev, alt_llist* list); + +#ifdef __cplusplus +} +#endif + +#endif /* __ALT_DEV_LLIST_H__ */ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/priv/alt_exception_handler_registry.h b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/priv/alt_exception_handler_registry.h new file mode 100644 index 00000000..c6905faf --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/priv/alt_exception_handler_registry.h @@ -0,0 +1,39 @@ +#ifndef __ALT_EXCEPTION_HANDLER_REGISTRY_H__ +#define __ALT_EXCEPTION_HANDLER_REGISTRY_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2008 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ +#include "sys/alt_exceptions.h" + +/* Function pointer to exception callback routine */ +extern alt_exception_result (*alt_instruction_exception_handler) + (alt_exception_cause, alt_u32, alt_u32); + +#endif /* __ALT_EXCEPTION_HANDLER_REGISTRY_H__ */ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/priv/alt_file.h b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/priv/alt_file.h new file mode 100644 index 00000000..2c3e843d --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/priv/alt_file.h @@ -0,0 +1,179 @@ +#ifndef __ALT_FILE_H__ +#define __ALT_FILE_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +#include "sys/alt_dev.h" +#include "sys/alt_llist.h" +#include "os/alt_sem.h" + +#include "alt_types.h" + +/* + * This header provides the internal defenitions required to control file + * access. These variables and functions are not guaranteed to exist in + * future implementations of the HAL. + */ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * The function alt_find_dev() is used to search the device list "list" to + * locate a device named "name". If a match is found, then a pointer to the + * device is returned, otherwise NULL is returned. + */ + +extern alt_dev* alt_find_dev (const char* name, alt_llist* list); + +/* + * alt_find_file() is used to search the list of registered file systems to + * find the filesystem that the file named "name" belongs to. If a match is + * found, then a pointer to the filesystems alt_dev structure is returned, + * otherwise NULL is returned. + * + * Note that a match does not indicate that the file exists, only that a + * filesystem exists that is registered for a partition that could contain + * the file. The filesystems open() function would need to be called in order + * to determine if the file exists. + */ + +extern alt_dev* alt_find_file (const char* name); + +/* + * alt_get_fd() is used to allocate a file descriptor for the device or + * filesystem "dev". A negative return value indicates an error, otherwise the + * return value is the index of the file descriptor within the file descriptor + * pool. + */ + +extern int alt_get_fd (alt_dev* dev); + +/* + * alt_release_fd() is called to free the file descriptor with index "fd". + */ + +extern void alt_release_fd (int fd); + +/* + * alt_fd_lock() is called by ioctl() to mark the file descriptor "fd" as + * being open for exclusive access. Subsequent calls to open() for the device + * associated with "fd" will fail. A device is unlocked by either calling + * close() for "fd", or by an alternate call to ioctl() (see ioctl.c for + * details). + */ + +extern int alt_fd_lock (alt_fd* fd); + +/* + * alt_fd_unlock() is called by ioctl() to unlock a descriptor previously + * locked by a call to alt_fd_lock(). + */ + +extern int alt_fd_unlock (alt_fd* fd); + +/* + * "alt_fd_list" is the pool of file descriptors. + */ + +extern alt_fd alt_fd_list[]; + +/* + * flags used by alt_fd. + * + * ALT_FD_EXCL is used to mark a file descriptor as locked for exclusive + * access, i.e. further calls to open() for the associated device should + * fail. + * + * ALT_FD_DEV marks a dile descriptor as belonging to a device as oposed to a + * filesystem. + */ + +#define ALT_FD_EXCL 0x80000000 +#define ALT_FD_DEV 0x40000000 + +#define ALT_FD_FLAGS_MASK (ALT_FD_EXCL | ALT_FD_DEV) + +/* + * "alt_dev_list" is the head of the linked list of registered devices. + */ + +extern alt_llist alt_dev_list; + +/* + * "alt_fs_list" is the head of the linked list of registered filesystems. + */ + +extern alt_llist alt_fs_list; + +/* + * "alt_fd_list_lock" is a semaphore used to ensure that access to the pool + * of file descriptors is thread safe. + */ + +ALT_EXTERN_SEM(alt_fd_list_lock) + +/* + * "alt_max_fd" is a 'high water mark'. It indicates the highest file + * descriptor allocated. Use of this can save searching the entire pool + * for active file descriptors, which helps avoid contention on access + * to the file descriptor pool. + */ + +extern alt_32 alt_max_fd; + +/* + * alt_io_redirect() is called at startup to redirect stdout, stdin, and + * stderr to the devices named in the input arguments. By default these streams + * are directed at /dev/null, and are then redirected using this function once + * all of the devices have been registered within the system. + */ + +extern void alt_io_redirect(const char* stdout_dev, + const char* stdin_dev, + const char* stderr_dev); + + +#ifdef __cplusplus +} +#endif + +#endif /* __ALT_FILE_H__ */ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/priv/alt_iic_isr_register.h b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/priv/alt_iic_isr_register.h new file mode 100644 index 00000000..a0cb01c0 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/priv/alt_iic_isr_register.h @@ -0,0 +1,39 @@ +#ifndef __ALT_IIC_ISR_REGISTER_H_ +#define __ALT_IIC_ISR_REGISTER_H_ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2009 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ +#include "alt_types.h" +#include "sys/alt_irq.h" + +extern int alt_iic_isr_register(alt_u32 ic_id, alt_u32 irq, alt_isr_func isr, + void *isr_context, void *flags); + +#endif /* __ALT_IIC_ISR_REGISTER_H_ */ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/priv/alt_irq_table.h b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/priv/alt_irq_table.h new file mode 100644 index 00000000..694ef066 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/priv/alt_irq_table.h @@ -0,0 +1,59 @@ +#ifndef __ALT_IRQ_TABLE_H__ +#define __ALT_IRQ_TABLE_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2009 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +/* + * Definition of a table describing each interrupt handler. The index into + * the array is the interrupt id associated with the handler. + * + * When an interrupt occurs, the associated handler is called with + * the argument stored in the context member. + * + * The table is physically created in alt_irq_handler.c + */ +extern struct ALT_IRQ_HANDLER +{ +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT + void (*handler)(void*); +#else + void (*handler)(void*, alt_u32); +#endif + void *context; +} alt_irq[ALT_NIRQ]; + +#endif diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/priv/alt_legacy_irq.h b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/priv/alt_legacy_irq.h new file mode 100644 index 00000000..c7aec027 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/priv/alt_legacy_irq.h @@ -0,0 +1,158 @@ +#ifndef __ALT_LEGACY_IRQ_H__ +#define __ALT_LEGACY_IRQ_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2009 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +/* + * This file provides prototypes and inline implementations of certain routines + * used by the legacy interrupt API. Do not include this in your driver or + * application source files, use "sys/alt_irq.h" instead to access the proper + * public API. + */ + +#include +#include "system.h" + +#ifndef NIOS2_EIC_PRESENT + +#include "nios2.h" +#include "alt_types.h" + +#include "sys/alt_irq.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * alt_irq_register() can be used to register an interrupt handler. If the + * function is succesful, then the requested interrupt will be enabled upon + * return. + */ +extern int alt_irq_register (alt_u32 id, + void* context, + alt_isr_func handler); + +/* + * alt_irq_disable() disables the individual interrupt indicated by "id". + */ +static ALT_INLINE int ALT_ALWAYS_INLINE alt_irq_disable (alt_u32 id) +{ + alt_irq_context status; + extern volatile alt_u32 alt_irq_active; + + status = alt_irq_disable_all (); + + alt_irq_active &= ~(1 << id); + NIOS2_WRITE_IENABLE (alt_irq_active); + + alt_irq_enable_all(status); + + return 0; +} + +/* + * alt_irq_enable() enables the individual interrupt indicated by "id". + */ +static ALT_INLINE int ALT_ALWAYS_INLINE alt_irq_enable (alt_u32 id) +{ + alt_irq_context status; + extern volatile alt_u32 alt_irq_active; + + status = alt_irq_disable_all (); + + alt_irq_active |= (1 << id); + NIOS2_WRITE_IENABLE (alt_irq_active); + + alt_irq_enable_all(status); + + return 0; +} + +#ifndef ALT_EXCEPTION_STACK +/* + * alt_irq_initerruptable() should only be called from within an ISR. It is used + * to allow higer priority interrupts to interrupt the current ISR. The input + * argument, "priority", is the priority, i.e. interrupt number of the current + * interrupt. + * + * If this function is called, then the ISR is required to make a call to + * alt_irq_non_interruptible() before returning. The input argument to + * alt_irq_non_interruptible() is the return value from alt_irq_interruptible(). + * + * Care should be taken when using this pair of functions, since they increasing + * the system overhead associated with interrupt handling. + * + * If you are using an exception stack then nested interrupts won't work, so + * these functions are not available in that case. + */ +static ALT_INLINE alt_u32 ALT_ALWAYS_INLINE alt_irq_interruptible (alt_u32 priority) +{ + extern volatile alt_u32 alt_priority_mask; + extern volatile alt_u32 alt_irq_active; + + alt_u32 old_priority; + + old_priority = alt_priority_mask; + alt_priority_mask = (1 << priority) - 1; + + NIOS2_WRITE_IENABLE (alt_irq_active & alt_priority_mask); + + NIOS2_WRITE_STATUS (1); + + return old_priority; +} + +/* + * See Comments above for alt_irq_interruptible() for an explanation of the use of this + * function. + */ +static ALT_INLINE void ALT_ALWAYS_INLINE alt_irq_non_interruptible (alt_u32 mask) +{ + extern volatile alt_u32 alt_priority_mask; + extern volatile alt_u32 alt_irq_active; + + NIOS2_WRITE_STATUS (0); + + alt_priority_mask = mask; + + NIOS2_WRITE_IENABLE (mask & alt_irq_active); +} +#endif /* ALT_EXCEPTION_STACK */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* NIOS2_EIC_PRESENT */ + +#endif /* __ALT_LEGACY_IRQ_H__ */ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/priv/alt_no_error.h b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/priv/alt_no_error.h new file mode 100644 index 00000000..6143fc90 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/priv/alt_no_error.h @@ -0,0 +1,77 @@ +#ifndef __ALT_NO_ERROR_H__ +#define __ALT_NO_ERROR_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +#include "alt_types.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * alt_no_error() is a dummy function used by alt_sem.h and alt_flag.h. It + * substitutes for functions that have a return code by creating a function + * that always returns zero. + * + * This may seem a little obscure, but what happens is that the compiler can + * then optomise away the call to this function, and any code written which + * handles the error path (i.e. non zero return values). + * + * This allows code to be written which correctly use the uC/OS-II semaphore + * and flag utilities, without the use of those utilities impacting on + * excutables built for a single threaded HAL environment. + * + * This function is considered to be part of the internal implementation of + * the HAL, and should not be called directly by application code or device + * drivers. It is not guaranteed to be preserved in future versions of the + * HAL. + */ + +static ALT_INLINE int ALT_ALWAYS_INLINE alt_no_error (void) +{ + return 0; +} + +#ifdef __cplusplus +} +#endif + +#endif /* __ALT_NO_ERROR_H__ */ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/priv/nios2_gmon_data.h b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/priv/nios2_gmon_data.h new file mode 100644 index 00000000..3f43f12d --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/priv/nios2_gmon_data.h @@ -0,0 +1,47 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ +#ifndef NIOS2_GMON_DATA_H +#define NIOS2_GMON_DATA_H + +#define GMON_DATA_SIG 0 +#define GMON_DATA_WORDS 1 +#define GMON_DATA_PROFILE_DATA 2 +#define GMON_DATA_PROFILE_LOWPC 3 +#define GMON_DATA_PROFILE_HIGHPC 4 +#define GMON_DATA_PROFILE_BUCKET 5 +#define GMON_DATA_PROFILE_RATE 6 +#define GMON_DATA_MCOUNT_START 7 +#define GMON_DATA_MCOUNT_LIMIT 8 + +#define GMON_DATA_SIZE 9 + +extern unsigned int alt_gmon_data[GMON_DATA_SIZE]; + +#endif diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/sys/alt_alarm.h b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/sys/alt_alarm.h new file mode 100644 index 00000000..68a2f5d8 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/sys/alt_alarm.h @@ -0,0 +1,126 @@ +#ifndef __ALT_ALARM_H__ +#define __ALT_ALARM_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +#include "alt_llist.h" +#include "alt_types.h" + +#include "priv/alt_alarm.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * "alt_alarm" is a structure type used by applications to register an alarm + * callback function. An instance of this type must be passed as an input + * argument to alt_alarm_start(). The user is not responsible for initialising + * the contents of the instance. This is done by alt_alarm_start(). + */ + +typedef struct alt_alarm_s alt_alarm; + +/* + * alt_alarm_start() can be called by an application/driver in order to register + * a function for periodic callback at the system clock frequency. Be aware that + * this callback is likely to occur in interrupt context. + */ + +extern int alt_alarm_start (alt_alarm* the_alarm, + alt_u32 nticks, + alt_u32 (*callback) (void* context), + void* context); + +/* + * alt_alarm_stop() is used to unregister a callback. Alternatively the callback + * can return zero to unregister. + */ + +extern void alt_alarm_stop (alt_alarm* the_alarm); + +/* + * Obtain the system clock rate in ticks/s. + */ + +static ALT_INLINE alt_u32 ALT_ALWAYS_INLINE alt_ticks_per_second (void) +{ + return _alt_tick_rate; +} + +/* + * alt_sysclk_init() is intended to be only used by the system clock driver + * in order to initialise the value of the clock frequency. + */ + +static ALT_INLINE int ALT_ALWAYS_INLINE alt_sysclk_init (alt_u32 nticks) +{ + if (! _alt_tick_rate) + { + _alt_tick_rate = nticks; + return 0; + } + else + { + return -1; + } +} + +/* + * alt_nticks() returns the elapsed number of system clock ticks since reset. + */ + +static ALT_INLINE alt_u32 ALT_ALWAYS_INLINE alt_nticks (void) +{ + return _alt_nticks; +} + +/* + * alt_tick() should only be called by the system clock driver. This is used + * to notify the system that the system timer period has expired. + */ + +extern void alt_tick (void); + +#ifdef __cplusplus +} +#endif + +#endif /* __ALT_ALARM_H__ */ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/sys/alt_cache.h b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/sys/alt_cache.h new file mode 100644 index 00000000..c4d8db97 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/sys/alt_cache.h @@ -0,0 +1,117 @@ +#ifndef __ALT_CACHE_H__ +#define __ALT_CACHE_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003, 2007 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include + +#include "alt_types.h" + +/* + * alt_cache.h defines the processor specific functions for manipulating the + * cache. + */ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * alt_icache_flush() is called to flush the instruction cache for a memory + * region of length "len" bytes, starting at address "start". + */ + +extern void alt_icache_flush (void* start, alt_u32 len); + +/* + * alt_dcache_flush() is called to flush the data cache for a memory + * region of length "len" bytes, starting at address "start". + * Any dirty lines in the data cache are written back to memory. + */ + +extern void alt_dcache_flush (void* start, alt_u32 len); + +/* + * alt_dcache_flush() is called to flush the data cache for a memory + * region of length "len" bytes, starting at address "start". + * Any dirty lines in the data cache are NOT written back to memory. + */ + +extern void alt_dcache_flush_no_writeback (void* start, alt_u32 len); + +/* + * Flush the entire instruction cache. + */ + +extern void alt_icache_flush_all (void); + +/* + * Flush the entire data cache. + */ + +extern void alt_dcache_flush_all (void); + +/* + * Allocate a block of uncached memory. + */ + +extern volatile void* alt_uncached_malloc (size_t size); + +/* + * Free a block of uncached memory. + */ + +extern void alt_uncached_free (volatile void* ptr); + +/* + * Convert a pointer to a block of cached memory, into a block of + * uncached memory. + */ + +extern volatile void* alt_remap_uncached (void* ptr, alt_u32 len); + +/* + * Convert a pointer to a block of uncached memory, into a block of + * cached memory. + */ + +extern void* alt_remap_cached (volatile void* ptr, alt_u32 len); + +/* + * + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __ALT_CACHE_H__ */ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/sys/alt_debug.h b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/sys/alt_debug.h new file mode 100644 index 00000000..d9f9599e --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/sys/alt_debug.h @@ -0,0 +1,45 @@ +#ifndef __ALT_DEBUG_H__ +#define __ALT_DEBUG_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +/* + * The ALT_DEVUG_ASSERT macro can be used to generate a debugger break + * from within software. The break is generated if "condition" evaluates to + * false. + */ + +#define ALT_DEBUG_ASSERT(condition) if (!condition) \ +{ \ + __asm__ volatile ("break"); \ +} + +#endif /* __ALT_DEBUG_H__ */ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/sys/alt_dev.h b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/sys/alt_dev.h new file mode 100644 index 00000000..66c5e413 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/sys/alt_dev.h @@ -0,0 +1,115 @@ +#ifndef __ALT_DEV_H__ +#define __ALT_DEV_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +#include "system.h" +#include "sys/alt_llist.h" +#include "priv/alt_dev_llist.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * The value ALT_IRQ_NOT_CONNECTED is used to represent an unconnected + * interrupt line. It cannot evaluate to a valid interrupt number. + */ + +#define ALT_IRQ_NOT_CONNECTED (-1) + +typedef struct alt_dev_s alt_dev; + +struct stat; + +/* + * The file descriptor structure definition. + */ + +typedef struct alt_fd_s +{ + alt_dev* dev; + alt_u8* priv; + int fd_flags; +} alt_fd; + +/* + * The device structure definition. + */ + +struct alt_dev_s { + alt_llist llist; /* for internal use */ + const char* name; + int (*open) (alt_fd* fd, const char* name, int flags, int mode); + int (*close) (alt_fd* fd); + int (*read) (alt_fd* fd, char* ptr, int len); + int (*write) (alt_fd* fd, const char* ptr, int len); + int (*lseek) (alt_fd* fd, int ptr, int dir); + int (*fstat) (alt_fd* fd, struct stat* buf); + int (*ioctl) (alt_fd* fd, int req, void* arg); +}; + +/* + * Functions used to register device for access through the C standard + * library. + * + * The only difference between alt_dev_reg() and alt_fs_reg() is the + * interpretation that open() places on the device name. In the case of + * alt_dev_reg the device is assumed to be a particular character device, + * and so there must be an exact match in the name for open to succeed. + * In the case of alt_fs_reg() the name of the device is treated as the + * mount point for a directory, and so any call to open() where the name + * is the root of the device filename will succeed. + */ + +extern int alt_fs_reg (alt_dev* dev); + +static ALT_INLINE int alt_dev_reg (alt_dev* dev) +{ + extern alt_llist alt_dev_list; + + return alt_dev_llist_insert ((alt_dev_llist*) dev, &alt_dev_list); +} + +#ifdef __cplusplus +} +#endif + +#endif /* __ALT_DEV_H__ */ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/sys/alt_dma.h b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/sys/alt_dma.h new file mode 100644 index 00000000..9f9b2ff1 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/sys/alt_dma.h @@ -0,0 +1,226 @@ +#ifndef __ALT_DMA_H__ +#define __ALT_DMA_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004-2005 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +#include "sys/alt_dma_dev.h" +#include "alt_types.h" + +#include + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * This header contains the application side interface for accessing DMA + * resources. See alt_dma_dev.h for the dma device driver interface. + * + * The interface model treats a DMA transaction as being composed of two + * halves (read and write). + * + * The application can supply data for transmit using an "alt_dma_txchan" + * descriptor. Alternatively an "alt_dma_rxchan" descriptor can be used to + * receive data. + */ + +/* + * alt_dma_txchan_open() is used to obtain an "alt_dma_txchan" descriptor for + * a DMA transmit device. The name is the name of the associated physical + * device (e.g. "/dev/dma_0"). + * + * The return value will be NULL on failure, and non-NULL otherwise. + */ + +extern alt_dma_txchan alt_dma_txchan_open (const char* name); + +/* + * alt_dma_txchan_close() is provided so that an application can notify the + * system that it has finished with a given DMA transmit channel. This is only + * provided for completness. + */ + +static ALT_INLINE int alt_dma_txchan_close (alt_dma_txchan dma) +{ + return 0; +} + +/* + * alt_dma_txchan_send() posts a transmit request to a DMA transmit channel. + * The input arguments are: + * + * dma: the channel to use. + * from: a pointer to the start of the data to send. + * length: the length of the data to send in bytes. + * done: callback function that will be called once the data has been sent. + * handle: opaque value passed to "done". + * + * The return value will be negative if the request cannot be posted, and + * zero otherwise. + */ + +static ALT_INLINE int alt_dma_txchan_send (alt_dma_txchan dma, + const void* from, + alt_u32 length, + alt_txchan_done* done, + void* handle) +{ + return dma ? dma->dma_send (dma, + from, + length, + done, + handle) : -ENODEV; +} + +/* + * alt_dma_txchan_space() returns the number of tranmit requests that can be + * posted to the specified DMA transmit channel. + * + * A negative value indicates that the value could not be determined. + */ + +static ALT_INLINE int alt_dma_txchan_space (alt_dma_txchan dma) +{ + return dma ? dma->space (dma) : -ENODEV; +} + +/* + * alt_dma_txchan_ioctl() can be used to perform device specific I/O + * operations on the indicated DMA transmit channel. For example some drivers + * support options to control the width of the transfer operations. See + * alt_dma_dev.h for the list of generic requests. + * + * A negative return value indicates failure, otherwise the interpretation + * of the return value is request specific. + */ + +static ALT_INLINE int alt_dma_txchan_ioctl (alt_dma_txchan dma, + int req, + void* arg) +{ + return dma ? dma->ioctl (dma, req, arg) : -ENODEV; +} + +/* + * alt_dma_rxchan_open() is used to obtain an "alt_dma_rxchan" descriptor for + * a DMA receive channel. The name is the name of the associated physical + * device (e.g. "/dev/dma_0"). + * + * The return value will be NULL on failure, and non-NULL otherwise. + */ + +extern alt_dma_rxchan alt_dma_rxchan_open (const char* dev); + +/* + * alt_dma_rxchan_close() is provided so that an application can notify the + * system that it has finished with a given DMA receive channel. This is only + * provided for completness. + */ + +static ALT_INLINE int alt_dma_rxchan_close (alt_dma_rxchan dma) +{ + return 0; +} + +/* + * + */ + +/* + * alt_dma_rxchan_prepare() posts a receive request to a DMA receive channel. + * + * The input arguments are: + * + * dma: the channel to use. + * data: a pointer to the location that data is to be received to. + * len: the maximum length of the data to receive. + * done: callback function that will be called once the data has been + * received. + * handle: opaque value passed to "done". + * + * The return value will be negative if the request cannot be posted, and + * zero otherwise. + */ + +static ALT_INLINE int alt_dma_rxchan_prepare (alt_dma_rxchan dma, + void* data, + alt_u32 len, + alt_rxchan_done* done, + void* handle) +{ + return dma ? dma->prepare (dma, data, len, done, handle) : -ENODEV; +} + +/* + * alt_dma_rxchan_ioctl() can be used to perform device specific I/O + * operations on the indicated DMA receive channel. For example some drivers + * support options to control the width of the transfer operations. See + * alt_dma_dev.h for the list of generic requests. + * + * A negative return value indicates failure, otherwise the interpretation + * of the return value is request specific. + */ + +static ALT_INLINE int alt_dma_rxchan_ioctl (alt_dma_rxchan dma, + int req, + void* arg) +{ + return dma ? dma->ioctl (dma, req, arg) : -ENODEV; +} + +/* + * alt_dma_rxchan_depth() returns the depth of the receive FIFO used to store + * receive requests. + */ + +static ALT_INLINE alt_u32 alt_dma_rxchan_depth(alt_dma_rxchan dma) +{ + return dma->depth; +} + +/* + * + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALT_DMA_H__ */ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/sys/alt_dma_dev.h b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/sys/alt_dma_dev.h new file mode 100644 index 00000000..832463d1 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/sys/alt_dma_dev.h @@ -0,0 +1,200 @@ +#ifndef __ALT_DMA_DEV_H__ +#define __ALT_DMA_DEV_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004-2005 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +#include "priv/alt_dev_llist.h" + +#include "alt_types.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * This header contains the device driver interface for accessing DMA + * resources. See alt_dma.h for the DMA application side interface. + * + * The interface model treats a DMA transaction as being composed of two + * halves (read and write). + * + * An "alt_dma_txchan_dev" is used to describe the device associated with a + * DMA transmit channel. An "alt_dma_rxchan_dev" is used to describe the + * device associated with a DMA receive channel. + */ + +/* + * List of generic ioctl requests that may be supported by a DMA device. + * + * ALT_DMA_RX_ONLY_ON: This causes a DMA channel to operate in a mode + * where only the receiver is under software control. + * The other side reads continously from a single + * location. The address to read is the argument to + * this request. + * ALT_DMA_RX_ONLY_OFF: Return to the default mode where both the receive + * and transmit sides of the DMA can be under software + * control. + * ALT_DMA_TX_ONLY_ON: This causes a DMA channel to operate in a mode + * where only the transmitter is under software control. + * The other side writes continously to a single + * location. The address to write to is the argument to + * this request. + * ALT_DMA_TX_ONLY_OFF: Return to the default mode where both the receive + * and transmit sides of the DMA can be under software + * control. + * ALT_DMA_SET_MODE_8: Transfer data in units of 8 bits. + * ALT_DMA_SET_MODE_16: Transfer data in units of 16 bits. + * ALT_DMA_SET_MODE_32: Transfer data in units of 32 bits. + * ALT_DMA_SET_MODE_64: Transfer data in units of 64 bits. + * ALT_DMA_SET_MODE_128: Transfer data in units of 128 bits. + * ALT_DMA_GET_MODE: Get the current transfer mode. + * + * The use of the macros: ALT_DMA_TX_STREAM_ON, ALT_DMA_TX_STREAM_OFF + * ALT_DMA_RX_STREAM_OFF and ALT_DMA_RX_STREAM_ON are depreciated. You should + * instead use the macros: ALT_DMA_RX_ONLY_ON, ALT_DMA_RX_ONLY_OFF, + * ALT_DMA_TX_ONLY_ON and ALT_DMA_TX_ONLY_OFF. + */ + +#define ALT_DMA_TX_STREAM_ON (0x1) +#define ALT_DMA_TX_STREAM_OFF (0x2) +#define ALT_DMA_RX_STREAM_ON (0x3) +#define ALT_DMA_RX_STREAM_OFF (0x4) +#define ALT_DMA_SET_MODE_8 (0x5) +#define ALT_DMA_SET_MODE_16 (0x6) +#define ALT_DMA_SET_MODE_32 (0x7) +#define ALT_DMA_SET_MODE_64 (0x8) +#define ALT_DMA_SET_MODE_128 (0x9) +#define ALT_DMA_GET_MODE (0xa) + +#define ALT_DMA_RX_ONLY_ON ALT_DMA_TX_STREAM_ON +#define ALT_DMA_RX_ONLY_OFF ALT_DMA_TX_STREAM_OFF +#define ALT_DMA_TX_ONLY_ON ALT_DMA_RX_STREAM_ON +#define ALT_DMA_TX_ONLY_OFF ALT_DMA_RX_STREAM_OFF + +/* + * + */ + +typedef struct alt_dma_txchan_dev_s alt_dma_txchan_dev; +typedef struct alt_dma_rxchan_dev_s alt_dma_rxchan_dev; + +typedef alt_dma_txchan_dev* alt_dma_txchan; +typedef alt_dma_rxchan_dev* alt_dma_rxchan; + +typedef void (alt_txchan_done)(void* handle); +typedef void (alt_rxchan_done)(void* handle, void* data); + +/* + * devices that provide a DMA transmit channel are required to provide an + * instance of the "alt_dma_txchan_dev" structure. + */ + +struct alt_dma_txchan_dev_s { + alt_llist llist; /* for internal use */ + const char* name; /* name of the device instance + * (e.g. "/dev/dma_0"). + */ + int (*space) (alt_dma_txchan dma); /* returns the maximum number of + * transmit requests that can be posted + */ + int (*dma_send) (alt_dma_txchan dma, + const void* from, + alt_u32 len, + alt_txchan_done* done, + void* handle); /* post a transmit request */ + int (*ioctl) (alt_dma_txchan dma, int req, void* arg); /* perform device + * specific I/O control. + */ +}; + +/* + * devices that provide a DMA receive channel are required to provide an + * instance of the "alt_dma_rxchan_dev" structure. + */ + +struct alt_dma_rxchan_dev_s { + alt_llist list; /* for internal use */ + const char* name; /* name of the device instance + * (e.g. "/dev/dma_0"). + */ + alt_u32 depth; /* maximum number of receive requests that + * can be posted. + */ + int (*prepare) (alt_dma_rxchan dma, + void* data, + alt_u32 len, + alt_rxchan_done* done, + void* handle); /* post a receive request */ + int (*ioctl) (alt_dma_rxchan dma, int req, void* arg); /* perform device + * specific I/O control. + */ +}; + +/* + * Register a DMA transmit channel with the system. + */ + +static ALT_INLINE int alt_dma_txchan_reg (alt_dma_txchan_dev* dev) +{ + extern alt_llist alt_dma_txchan_list; + + return alt_dev_llist_insert((alt_dev_llist*) dev, &alt_dma_txchan_list); +} + +/* + * Register a DMA receive channel with the system. + */ + +static ALT_INLINE int alt_dma_rxchan_reg (alt_dma_rxchan_dev* dev) +{ + extern alt_llist alt_dma_rxchan_list; + + return alt_dev_llist_insert((alt_dev_llist*) dev, &alt_dma_rxchan_list); +} + +/* + * + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALT_DMA_DEV_H__ */ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/sys/alt_driver.h b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/sys/alt_driver.h new file mode 100644 index 00000000..eb0f23be --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/sys/alt_driver.h @@ -0,0 +1,168 @@ +#ifndef __ALT_DRIVER_H__ +#define __ALT_DRIVER_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/* + * Macros used to access a driver without HAL file descriptors. + */ + +/* + * ALT_MODULE_CLASS + * + * This macro returns the module class name for the specified module instance. + * It uses information in the system.h file. + * Neither the instance name or class name are quoted (so that they can + * be used with other pre-processor macros). + * + * Example: + * Assume the design has an instance of an altera_avalon_uart called uart1. + * Calling ALT_MODULE_CLASS(uart1) returns altera_avalon_uart. + */ + +#define ALT_MODULE_CLASS(instance) ALT_MODULE_CLASS_ ## instance + + +/* + * ALT_DRIVER_FUNC_NAME + * + * --> instance Instance name. + * --> func Function name. + * + * This macro returns the device driver function name of the specified + * module instance for the specified function name. + * + * Example: + * Assume the design has an instance of an altera_avalon_uart called uart1. + * Calling ALT_DRIVER_FUNC_NAME(uart1, write) returns + * altera_avalon_uart_write. + */ + +#define ALT_DRIVER_FUNC_NAME(instance, func) \ + ALT_DRIVER_FUNC_NAME1(ALT_MODULE_CLASS(instance), func) +#define ALT_DRIVER_FUNC_NAME1(module_class, func) \ + ALT_DRIVER_FUNC_NAME2(module_class, func) +#define ALT_DRIVER_FUNC_NAME2(module_class, func) \ + module_class ## _ ## func + +/* + * ALT_DRIVER_STATE_STRUCT + * + * --> instance Instance name. + * + * This macro returns the device driver state type name of the specified + * module instance. + * + * Example: + * Assume the design has an instance of an altera_avalon_uart called uart1. + * Calling ALT_DRIVER_STATE_STRUCT(uart1) returns: + * struct altera_avalon_uart_state_s + * + * Note that the ALT_DRIVER_FUNC_NAME macro is used even though "state" isn't + * really a function but it does match the required naming convention. + */ +#define ALT_DRIVER_STATE_STRUCT(instance) \ + struct ALT_DRIVER_FUNC_NAME(instance, state_s) + +/* + * ALT_DRIVER_STATE + * + * --> instance Instance name. + * + * This macro returns the device driver state name of the specified + * module instance. + * + * Example: + * Assume the design has an instance of an altera_avalon_uart called uart1. + * Calling ALT_DRIVER_STATE(uart1) returns uart1. + */ +#define ALT_DRIVER_STATE(instance) instance + +/* + * ALT_DRIVER_WRITE + * + * --> instance Instance name. + * --> buffer Write buffer. + * --> len Length of write buffer data. + * --> flags Control flags (e.g. O_NONBLOCK) + * + * This macro calls the "write" function of the specified driver instance. + */ + +#define ALT_DRIVER_WRITE_EXTERNS(instance) \ + extern ALT_DRIVER_STATE_STRUCT(instance) ALT_DRIVER_STATE(instance); \ + extern int ALT_DRIVER_FUNC_NAME(instance, write) \ + (ALT_DRIVER_STATE_STRUCT(instance) *, const char *, int, int); + +#define ALT_DRIVER_WRITE(instance, buffer, len, flags) \ + ALT_DRIVER_FUNC_NAME(instance, write)(&ALT_DRIVER_STATE(instance), buffer, len, flags) + + +/* + * ALT_DRIVER_READ + * + * --> instance Instance name. + * <-- buffer Read buffer. + * --> len Length of read buffer. + * --> flags Control flags (e.g. O_NONBLOCK) + * + * This macro calls the "read" function of the specified driver instance. + */ + +#define ALT_DRIVER_READ_EXTERNS(instance) \ + extern ALT_DRIVER_STATE_STRUCT(instance) ALT_DRIVER_STATE(instance); \ + extern int ALT_DRIVER_FUNC_NAME(instance, read) \ + (ALT_DRIVER_STATE_STRUCT(instance) *, const char *, int, int); + +#define ALT_DRIVER_READ(instance, buffer, len, flags) \ + ALT_DRIVER_FUNC_NAME(instance, read)(&ALT_DRIVER_STATE(instance), buffer, len, flags) + +/* + * ALT_DRIVER_IOCTL + * + * --> instance Instance name. + * --> req ioctl request (e.g. TIOCSTIMEOUT) + * --> arg Optional argument (void*) + * + * This macro calls the "ioctl" function of the specified driver instance + */ + +#define ALT_DRIVER_IOCTL_EXTERNS(instance) \ + extern ALT_DRIVER_STATE_STRUCT(instance) ALT_DRIVER_STATE(instance); \ + extern int ALT_DRIVER_FUNC_NAME(instance, ioctl) \ + (ALT_DRIVER_STATE_STRUCT(instance) *, int, void*); + +#define ALT_DRIVER_IOCTL(instance, req, arg) \ + ALT_DRIVER_FUNC_NAME(instance, ioctl)(&ALT_DRIVER_STATE(instance), req, arg) + +#endif /* __ALT_DRIVER_H__ */ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/sys/alt_errno.h b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/sys/alt_errno.h new file mode 100644 index 00000000..97cc19c6 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/sys/alt_errno.h @@ -0,0 +1,84 @@ +#ifndef __ALT_ERRNO_H__ +#define __ALT_ERRNO_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +/* + * errno is defined in so that it uses the thread local version + * stored in the location pointed to by "_impure_ptr". This means that the + * accesses to errno within the HAL library can cause the entirety of + * of the structure pointed to by "_impure_ptr" to be added to the + * users application. This can be undesirable in very small footprint systems. + * + * To avoid this happening, the HAL uses the macro ALT_ERRNO, defined below, + * to access errno, rather than accessing it directly. This macro will only + * use the thread local version if some other code has already caused it to be + * included into the system, otherwise it will use the global errno value. + * + * This causes a slight increases in code size where errno is accessed, but + * can lead to significant overall benefits in very small systems. The + * increase is inconsequential when compared to the size of the structure + * pointed to by _impure_ptr. + * + * Note that this macro accesses __errno() using an externally declared + * function pointer (alt_errno). This is done so that the function call uses the + * subroutine call instruction via a register rather than an immediate address. + * This is important in the case that the code has been linked for a high + * address, but __errno() is not being used. In this case the weak linkage + * would have resulted in the instruction: "call 0" which would fail to link. + */ + +extern int* (*alt_errno) (void); + +#include + +#include "alt_types.h" + +#undef errno + +extern int errno; + +static ALT_INLINE int* alt_get_errno(void) +{ + return ((alt_errno) ? alt_errno() : &errno); +} + +#define ALT_ERRNO *alt_get_errno() + +#endif /* __ALT_ERRNO_H__ */ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/sys/alt_exceptions.h b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/sys/alt_exceptions.h new file mode 100644 index 00000000..3576a52e --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/sys/alt_exceptions.h @@ -0,0 +1,127 @@ +#ifndef __ALT_EXCEPTIONS_H__ +#define __ALT_EXCEPTIONS_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2008 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ +#include "alt_types.h" +#include "system.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * This file defines instruction-generated exception handling and registry + * API, exception type enumeration, and handler return value enumeration for + * Nios II. + */ + +/* + * The following enumeration describes the value in the CPU EXCEPTION + * register CAUSE bit field. Not all exception types will cause the + * processor to go to the exception vector; these are provided for + * reference. + */ +enum alt_exception_cause_e { + /* Exeption causes that will cause jump to exception vector */ + NIOS2_EXCEPTION_INTERRUPT = 2, + NIOS2_EXCEPTION_TRAP_INST = 3, + NIOS2_EXCEPTION_UNIMPLEMENTED_INST = 4, + NIOS2_EXCEPTION_ILLEGAL_INST = 5, + NIOS2_EXCEPTION_MISALIGNED_DATA_ADDR = 6, + NIOS2_EXCEPTION_MISALIGNED_TARGET_PC = 7, + NIOS2_EXCEPTION_DIVISION_ERROR = 8, + NIOS2_EXCEPTION_SUPERVISOR_ONLY_INST_ADDR = 9, + NIOS2_EXCEPTION_SUPERVISOR_ONLY_INST = 10, + NIOS2_EXCEPTION_SUPERVISOR_ONLY_DATA_ADDR = 11, + NIOS2_EXCEPTION_TLB_MISS = 12, + NIOS2_EXCEPTION_TLB_EXECUTE_PERM_VIOLATION = 13, + NIOS2_EXCEPTION_MPU_INST_REGION_VIOLATION = 16, + + /* Exception causes that will NOT cause a jump to exception vector */ + NIOS2_EXCEPTION_RESET = 0, + NIOS2_EXCEPTION_CPU_ONLY_RESET_REQUEST = 1, + NIOS2_EXCEPTION_TLB_READ_PERM_VIOLATION = 14, + NIOS2_EXCEPTION_TLB_WRITE_PERM_VIOLATION = 15, + NIOS2_EXCEPTION_MPU_DATA_REGION_VIOLATION = 17, + /* + * This value is passed to an exception handler's cause argument if + * "extra exceptions" information (EXECPTION) register is not + * present in the processor hardware configuration. + */ + NIOS2_EXCEPTION_CAUSE_NOT_PRESENT = -1 +}; +typedef enum alt_exception_cause_e alt_exception_cause; + +/* + * These define valid return values for a user-defined instruction-generated + * exception handler. The handler should return one of these to indicate + * whether to re-issue the instruction that triggered the exception, or to + * skip it. + */ +enum alt_exception_result_e { + NIOS2_EXCEPTION_RETURN_REISSUE_INST = 0, + NIOS2_EXCEPTION_RETURN_SKIP_INST = 1 +}; +typedef enum alt_exception_result_e alt_exception_result; + +/* + * alt_instruction_exception_register() can be used to register an exception + * handler for instruction-generated exceptions that are not handled by the + * built-in exception handler (i.e. for interrupts). + * + * The registry API is optionally enabled through the "Enable + * Instruction-related Exception API" HAL BSP setting, which will + * define the macro below. + */ +#ifdef ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API +void alt_instruction_exception_register ( + alt_exception_result (*exception_handler)( + alt_exception_cause cause, + alt_u32 exception_pc, + alt_u32 bad_addr) ); +#endif /*ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API */ + +/* + * alt_exception_cause_generated_bad_addr() indicates whether a particular + * exception cause value was from an exception-type that generated a valid + * address in the BADADDR register. The contents of BADADDR is passed to + * a user-registered exception handler in all cases, whether valid or not. + * This routine should be called to validate the bad_addr argument to + * your exception handler. + */ +int alt_exception_cause_generated_bad_addr(alt_exception_cause cause); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALT_EXCEPTIONS_H__ */ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/sys/alt_flash.h b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/sys/alt_flash.h new file mode 100644 index 00000000..527328df --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/sys/alt_flash.h @@ -0,0 +1,166 @@ +#ifndef __ALT_FLASH_H__ +#define __ALT_FLASH_H__ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +/****************************************************************************** +* * +* Alt_flash.h - User interface for flash code * +* * +* Use this interface to avoid being exposed to the internals of the device * +* driver architecture. If you chose to use the flash driver internal * +* structures we don't guarantee not to change them * +* * +* Author PRR * +* * +******************************************************************************/ + + + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +#include "alt_types.h" +#include "alt_flash_types.h" +#include "alt_flash_dev.h" +#include "sys/alt_cache.h" + +alt_flash_fd* alt_flash_open_dev(const char* name); +void alt_flash_close_dev(alt_flash_fd* fd ); + +/* + * alt_write_flash + * + * Program a buffer into flash. + * + * This routine erases all the affected erase blocks (if necessary) + * and then programs the data. However it does not read the data out first + * and preserve and none overwritten data, because this would require very + * large buffers on the target. If you need + * that functionality use the functions below. + */ +static __inline__ int __attribute__ ((always_inline)) alt_write_flash( + alt_flash_fd* fd, + int offset, + const void* src_addr, + int length ) +{ + return fd->write( fd, offset, src_addr, length ); +} + +/* + * alt_read_flash + * + * Read a block of flash for most flashes this is just memcpy + * it's here for completeness in case we need it for some serial flash device + * + */ +static __inline__ int __attribute__ ((always_inline)) alt_read_flash( + alt_flash_fd* fd, int offset, + void* dest_addr, int length ) +{ + return fd->read( fd, offset, dest_addr, length ); +} + +/* + * alt_get_flash_info + * + * Return the information on the flash sectors. + * + */ +static __inline__ int __attribute__ ((always_inline)) alt_get_flash_info( + alt_flash_fd* fd, flash_region** info, + int* number_of_regions) +{ + return fd->get_info( fd, info, number_of_regions); +} + +/* + * alt_erase_flash_block + * + * Erase a particular erase block, pass in the offset to the start of + * the block and it's size + */ +static __inline__ int __attribute__ ((always_inline)) alt_erase_flash_block( + alt_flash_fd* fd, int offset, int length) +{ + int ret_code; + ret_code = fd->erase_block( fd, offset ); + + if(!ret_code) + alt_dcache_flush((alt_u8*)fd->base_addr + offset, length); + + return ret_code; +} + +/* + * alt_write_flash_block + * + * Write a particular flash block, block_offset is the offset + * (from the base of flash) to start of the block + * data_offset is the offset (from the base of flash) + * where you wish to start programming + * + * NB this function DOES NOT check that you are only writing a single + * block of data as that would slow down this function. + * + * Use alt_write_flash if you want that level of error checking. + */ + +static __inline__ int __attribute__ ((always_inline)) alt_write_flash_block( + alt_flash_fd* fd, int block_offset, + int data_offset, + const void *data, int length) +{ + + int ret_code; + ret_code = fd->write_block( fd, block_offset, data_offset, data, length ); + + if(!ret_code) + alt_dcache_flush((alt_u8*)fd->base_addr + data_offset, length); + + return ret_code; +} + +#ifdef __cplusplus +} +#endif + +#endif /* __ALT_FLASH_H__ */ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/sys/alt_flash_dev.h b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/sys/alt_flash_dev.h new file mode 100644 index 00000000..8bab6018 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/sys/alt_flash_dev.h @@ -0,0 +1,98 @@ +#ifndef __ALT_FLASH_DEV_H__ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +/****************************************************************************** +* * +* Alt_flash_dev.h - Generic Flash device interfaces * +* * +* Author PRR * +* * +******************************************************************************/ +#define __ALT_FLASH_DEV_H__ + +#include "alt_flash_types.h" +#include "sys/alt_llist.h" +#include "priv/alt_dev_llist.h" + +#include "alt_types.h" + +typedef struct alt_flash_dev alt_flash_dev; +typedef alt_flash_dev alt_flash_fd; + +static ALT_INLINE int alt_flash_device_register( alt_flash_fd* fd) +{ + extern alt_llist alt_flash_dev_list; + + return alt_dev_llist_insert ((alt_dev_llist*) fd, &alt_flash_dev_list); +} + +typedef alt_flash_dev* (*alt_flash_open)(alt_flash_dev* flash, + const char* name ); +typedef int (*alt_flash_close)(alt_flash_dev* flash_info); + +typedef int (*alt_flash_write)( alt_flash_dev* flash, int offset, + const void* src_addr, int length ); + +typedef int (*alt_flash_get_flash_info)( alt_flash_dev* flash, flash_region** info, + int* number_of_regions); +typedef int (*alt_flash_write_block)( alt_flash_dev* flash, int block_offset, + int data_offset, const void* data, + int length); +typedef int (*alt_flash_erase_block)( alt_flash_dev* flash, int offset); +typedef int (*alt_flash_read)(alt_flash_dev* flash, int offset, + void* dest_addr, int length ); + +struct alt_flash_dev +{ + alt_llist llist; + const char* name; + alt_flash_open open; + alt_flash_close close; + alt_flash_write write; + alt_flash_read read; + alt_flash_get_flash_info get_info; + alt_flash_erase_block erase_block; + alt_flash_write_block write_block; + void* base_addr; + int length; + int number_of_regions; + flash_region region_info[ALT_MAX_NUMBER_OF_FLASH_REGIONS]; +}; + +#endif /* __ALT_FLASH_DEV_H__ */ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/sys/alt_flash_types.h b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/sys/alt_flash_types.h new file mode 100644 index 00000000..884cbf80 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/sys/alt_flash_types.h @@ -0,0 +1,64 @@ +#ifndef __ALT_FLASH_TYPES_H__ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +/****************************************************************************** +* * +* Alt_flash_types.h - Some generic types and defines used by the flash code * +* * +* Author PRR * +* * +******************************************************************************/ +#define __ALT_FLASH_TYPES_H__ + +#ifndef ALT_MAX_NUMBER_OF_FLASH_REGIONS +#define ALT_MAX_NUMBER_OF_FLASH_REGIONS 8 +#endif /* ALT_MAX_NUMBER_OF_FLASH_REGIONS */ + +/* + * Description of a single Erase region + */ +typedef struct flash_region +{ + int offset; + int region_size; + int number_of_blocks; + int block_size; +}flash_region; + +#endif /* __ALT_FLASH_TYPES_H__ */ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/sys/alt_irq.h b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/sys/alt_irq.h new file mode 100644 index 00000000..6666e52f --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/sys/alt_irq.h @@ -0,0 +1,245 @@ +#ifndef __ALT_IRQ_H__ +#define __ALT_IRQ_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2009 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +/* + * alt_irq.h is the Nios II specific implementation of the interrupt controller + * interface. + * + * Nios II includes optional support for an external interrupt controller. + * When an external controller is present, the "Enhanced" interrupt API + * must be used to manage individual interrupts. The enhanced API also + * supports the processor's internal interrupt controller. Certain API + * members are accessible from either the "legacy" or "enhanced" interrpt + * API. + * + * Regardless of which API is in use, this file should be included by + * application code and device drivers that register ISRs or manage interrpts. + */ +#include + +#include "nios2.h" +#include "alt_types.h" +#include "system.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Macros used by alt_irq_enabled + */ +#define ALT_IRQ_ENABLED 1 +#define ALT_IRQ_DISABLED 0 + +/* + * Number of available interrupts in internal interrupt controller. + */ +#define ALT_NIRQ NIOS2_NIRQ + +/* + * Used by alt_irq_disable_all() and alt_irq_enable_all(). + */ +typedef int alt_irq_context; + +/* ISR Prototype */ +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT +typedef void (*alt_isr_func)(void* isr_context); +#else +typedef void (*alt_isr_func)(void* isr_context, alt_u32 id); +#endif + +/* + * The following protypes and routines are supported by both + * the enhanced and legacy interrupt APIs + */ + +/* + * alt_irq_enabled can be called to determine if the processor's global + * interrupt enable is asserted. The return value is zero if interrupts + * are disabled, and non-zero otherwise. + * + * Whether the internal or external interrupt controller is present, + * individual interrupts may still be disabled. Use the other API to query + * a specific interrupt. + */ +static ALT_INLINE int ALT_ALWAYS_INLINE alt_irq_enabled (void) +{ + int status; + + NIOS2_READ_STATUS (status); + + return status & NIOS2_STATUS_PIE_MSK; +} + +/* + * alt_irq_disable_all() + * + * This routine inhibits all interrupts by negating the status register PIE + * bit. It returns the previous contents of the CPU status register (IRQ + * context) which can be used to restore the status register PIE bit to its + * state before this routine was called. + */ +static ALT_INLINE alt_irq_context ALT_ALWAYS_INLINE + alt_irq_disable_all (void) +{ + alt_irq_context context; + + NIOS2_READ_STATUS (context); + + NIOS2_WRITE_STATUS (context & ~NIOS2_STATUS_PIE_MSK); + + return context; +} + +/* + * alt_irq_enable_all() + * + * Enable all interrupts that were previously disabled by alt_irq_disable_all() + * + * This routine accepts a context to restore the CPU status register PIE bit + * to the state prior to a call to alt_irq_disable_all(). + + * In the case of nested calls to alt_irq_disable_all()/alt_irq_enable_all(), + * this means that alt_irq_enable_all() does not necessarily re-enable + * interrupts. + * + * This routine will perform a read-modify-write sequence to restore only + * status.PIE if the processor is configured with options that add additional + * writeable status register bits. These include the MMU, MPU, the enhanced + * interrupt controller port, and shadow registers. Otherwise, as a performance + * enhancement, status is overwritten with the prior context. + */ +static ALT_INLINE void ALT_ALWAYS_INLINE + alt_irq_enable_all (alt_irq_context context) +{ +#if (NIOS2_NUM_OF_SHADOW_REG_SETS > 0) || (defined NIOS2_EIC_PRESENT) || \ + (defined NIOS2_MMU_PRESENT) || (defined NIOS2_MPU_PRESENT) + alt_irq_context status; + + NIOS2_READ_STATUS (status); + + status &= ~NIOS2_STATUS_PIE_MSK; + status |= (context & NIOS2_STATUS_PIE_MSK); + + NIOS2_WRITE_STATUS (status); +#else + NIOS2_WRITE_STATUS (context); +#endif +} + +/* + * The function alt_irq_init() is defined within the auto-generated file + * alt_sys_init.c. This function calls the initilization macros for all + * interrupt controllers in the system at config time, before any other + * non-interrupt controller driver is initialized. + * + * The "base" parameter is ignored and only present for backwards-compatibility. + * It is recommended that NULL is passed in for the "base" parameter. + */ +extern void alt_irq_init (const void* base); + +/* + * alt_irq_cpu_enable_interrupts() enables the CPU to start taking interrupts. + */ +static ALT_INLINE void ALT_ALWAYS_INLINE + alt_irq_cpu_enable_interrupts () +{ + NIOS2_WRITE_STATUS(NIOS2_STATUS_PIE_MSK +#if defined(NIOS2_EIC_PRESENT) && (NIOS2_NUM_OF_SHADOW_REG_SETS > 0) + | NIOS2_STATUS_RSIE_MSK +#endif + ); +} + + +/* + * Prototypes for the enhanced interrupt API. + */ +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT +/* + * alt_ic_isr_register() can be used to register an interrupt handler. If the + * function is succesful, then the requested interrupt will be enabled upon + * return. + */ +extern int alt_ic_isr_register(alt_u32 ic_id, + alt_u32 irq, + alt_isr_func isr, + void *isr_context, + void *flags); + +/* + * alt_ic_irq_enable() and alt_ic_irq_disable() enable/disable a specific + * interrupt by using IRQ port and interrupt controller instance. + */ +int alt_ic_irq_enable (alt_u32 ic_id, alt_u32 irq); +int alt_ic_irq_disable(alt_u32 ic_id, alt_u32 irq); + + /* + * alt_ic_irq_enabled() indicates whether a specific interrupt, as + * specified by IRQ port and interrupt controller instance is enabled. + */ +alt_u32 alt_ic_irq_enabled(alt_u32 ic_id, alt_u32 irq); + +#else +/* + * Prototypes for the legacy interrupt API. + */ +#include "priv/alt_legacy_irq.h" +#endif + + +/* + * alt_irq_pending() returns a bit list of the current pending interrupts. + * This is used by alt_irq_handler() to determine which registered interrupt + * handlers should be called. + * + * This routine is only available for the Nios II internal interrupt + * controller. + */ +#ifndef NIOS2_EIC_PRESENT +static ALT_INLINE alt_u32 ALT_ALWAYS_INLINE alt_irq_pending (void) +{ + alt_u32 active; + + NIOS2_READ_IPENDING (active); + + return active; +} +#endif + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALT_IRQ_H__ */ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/sys/alt_irq_entry.h b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/sys/alt_irq_entry.h new file mode 100644 index 00000000..e2008d94 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/sys/alt_irq_entry.h @@ -0,0 +1,39 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +/* + * This file pulls in the IRQ entry assembler and C code, which is only + * required if there are any interruptes in the system. + */ + +__asm__( "\n\t.globl alt_irq_entry" ); + +__asm__( "\n\t.globl alt_irq_handler" ); + diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/sys/alt_license_reminder_ucosii.h b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/sys/alt_license_reminder_ucosii.h new file mode 100644 index 00000000..2fe649ce --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/sys/alt_license_reminder_ucosii.h @@ -0,0 +1,77 @@ +#ifndef __ALT_LICENSE_REMINDER_UCOSII_H__ +#define __ALT_LICENSE_REMINDER_UCOSII_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +#include + +#define ALT_LICENSE_REMINDER_UCOSII_STRING \ + "============== Software License Reminder ===============\n" \ + "\n" \ + "uC/OS-II is provided in source form for FREE evaluation,\n" \ + "for educational use, or for peaceful research. If you\n" \ + "plan on using uC/OS-II in a commercial product you need\n" \ + "to contact Micrium to properly license its use in your\n" \ + "product. Micrium provides ALL the source code on the\n" \ + "Altera distribution for your convenience and to help you\n" \ + "experience uC/OS-II. The fact that the source is provided\n" \ + "does NOT mean that you can use it without paying a\n" \ + "licensing fee. Please help us continue to provide the\n" \ + "Embedded community with the finest software available.\n" \ + "Your honesty is greatly appreciated.\n" \ + "\n" \ + "Please contact:\n" \ + "\n" \ + "M I C R I U M\n" \ + "949 Crestview Circle\n" \ + "Weston, FL 33327-1848\n" \ + "U.S.A.\n" \ + "\n" \ + "Phone : +1 954 217 2036\n" \ + "FAX : +1 954 217 2037\n" \ + "WEB : www.micrium.com\n" \ + "E-mail: Sales@Micrium.com\n" \ + "\n" \ + "========================================================\n" + +#define alt_license_reminder_ucosii() puts(ALT_LICENSE_REMINDER_UCOSII_STRING) + + +#endif /* __ALT_LICENSE_REMINDER_UCOSII_H__ */ + diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/sys/alt_llist.h b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/sys/alt_llist.h new file mode 100644 index 00000000..46f81ce4 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/sys/alt_llist.h @@ -0,0 +1,123 @@ +#ifndef __ALT_LIST_H__ +#define __ALT_LIST_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +#include "alt_types.h" + +/* + * alt_llist.h defines structures and functions for use in manipulating linked + * lists. A list is considered to be constructed from a chain of objects of + * type alt_llist, with one object being defined to be the head element. + * + * A list is considered to be empty if it only contains the head element. + */ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * alt_llist is the structure used to represent an element within a linked + * list. + */ + +typedef struct alt_llist_s alt_llist; + +struct alt_llist_s { + alt_llist* next; /* Pointer to the next element in the list. */ + alt_llist* previous; /* Pointer to the previous element in the list. */ +}; + +/* + * ALT_LLIST_HEAD is a macro that can be used to create the head of a new + * linked list. This is named "head". The head element is initialised to + * represent an empty list. + */ + +#define ALT_LLIST_HEAD(head) alt_llist head = {&head, &head} + +/* + * ALT_LLIST_ENTRY is a macro used to define an uninitialised linked list + * entry. This is used to reserve space in structure initialisation for + * structures that inherit form alt_llist. + */ + +#define ALT_LLIST_ENTRY {0, 0} + +/* + * alt_llist_insert() insert adds the linked list entry "entry" as the + * first entry in the linked list "list". "list" is the list head element. + */ + +static ALT_INLINE void ALT_ALWAYS_INLINE alt_llist_insert(alt_llist* list, + alt_llist* entry) +{ + entry->previous = list; + entry->next = list->next; + + list->next->previous = entry; + list->next = entry; +} + +/* + * alt_llist_remove() is called to remove an element from a linked list. The + * input argument is the element to remove. + */ + +static ALT_INLINE void ALT_ALWAYS_INLINE alt_llist_remove(alt_llist* entry) +{ + entry->next->previous = entry->previous; + entry->previous->next = entry->next; + + /* + * Set the entry to point to itself, so that any further calls to + * alt_llist_remove() are harmless. + */ + + entry->previous = entry; + entry->next = entry; +} + +#ifdef __cplusplus +} +#endif + +#endif /* __ALT_LLIST_H__ */ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/sys/alt_load.h b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/sys/alt_load.h new file mode 100644 index 00000000..432e9f21 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/sys/alt_load.h @@ -0,0 +1,78 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2005 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include "alt_types.h" + +/* + * This macro is used to load code/data from its load address to its + * execution address for a given section. The section name is the input + * argument. Note that a leading '.' is assumed in the name. For example + * to load the section .onchip_ram, use: + * + * ALT_LOAD_SECTION_BY_NAME(onchip_ram); + * + * This requires that the apropriate linker symbols have been generated + * for the section in question. This will be the case if you are using the + * default linker script. + */ + +#define ALT_LOAD_SECTION_BY_NAME(name) \ + { \ + extern void _alt_partition_##name##_start; \ + extern void _alt_partition_##name##_end; \ + extern void _alt_partition_##name##_load_addr; \ + \ + alt_load_section(&_alt_partition_##name##_load_addr, \ + &_alt_partition_##name##_start, \ + &_alt_partition_##name##_end); \ + } + +/* + * Function used to load an individual section from flash to RAM. + * + * There is an implicit assumption here that the linker script will ensure + * that all sections are word aligned. + * + */ + +static void ALT_INLINE alt_load_section (alt_u32* from, + alt_u32* to, + alt_u32* end) +{ + if (to != from) + { + while( to != end ) + { + *to++ = *from++; + } + } +} diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/sys/alt_log_printf.h b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/sys/alt_log_printf.h new file mode 100644 index 00000000..c15ca059 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/sys/alt_log_printf.h @@ -0,0 +1,349 @@ +/* alt_log_printf.h + * + * ALT_LOG is designed to provide extra logging/debugging messages from HAL + * through a different port than stdout. It is enabled by the ALT_LOG_ENABLE + * define, which needs to supplied at compile time. When logging is turned off, + * code size is unaffected. Thus, this should be transparent to the user + * when it is not actively turned on, and should not affect projects in any way. + * + * There are macros sprinkled within different components, such as the jtag uart + * and timer, in the HAL code. They are always named ALT_LOG_, and can be + * safely ignored if ALT_LOG is turned off. + * + * To turn on ALT_LOG, ALT_LOG_ENABLE must be defined, and ALT_LOG_PORT_TYPE and + * ALT_LOG_PORT_BASE must be set in system.h. This is done through editing + * .ptf, by editing the alt_log_port_type & alt_log_port_base settings. + * See the documentation html file for examples. + * + * When it is turned on, it will output extra HAL messages to a port specified + * in system.h. This can be a UART or JTAG UART port. By default it will + * output boot messages, detailing every step of the boot process. + * + * Extra logging is designed to be enabled by flags, which are defined in + * alt_log_printf.c. The default value is that all flags are off, so only the + * boot up logging messages show up. ALT_LOG_FLAGS can be set to enable certain + * groupings of flags, and that grouping is done in this file. Each flag can + * also be overridden with a -D at compile time. + * + * This header file includes the necessary prototypes for using the alt_log + * functions. It also contains all the macros that are used to remove the code + * from alt log is turned off. Also, the macros in other HAL files are defined + * here at the bottom. These macros all call some C function that is in + * alt_log_printf.c. + * + * The logging has functions for printing in C (ALT_LOG_PRINTF) and in assembly + * (ALT_LOG_PUTS). This was needed because the assembly printing occurs before + * the device is initialized. The assembly function corrupts register R4-R7, + * which are not used in the normal boot process. For this reason, do not call + * the assembly function in C. + * + * author: gkwan + */ + + +#ifndef __ALT_LOG_PRINTF_H__ +#define __ALT_LOG_PRINTF_H__ + +#include + +/* Global switch to turn on logging functions */ +#ifdef ALT_LOG_ENABLE + + /* ALT_LOG_PORT_TYPE values as defined in system.h. They are defined as + * numbers here first becasue the C preprocessor does not handle string + * comparisons. */ + #define ALTERA_AVALON_JTAG_UART 1 + #define ALTERA_AVALON_UART 0 + + /* If this .h file is included by an assembly file, skip over include files + * that won't compile in assembly. */ + #ifndef ALT_ASM_SRC + #include + #include "sys/alt_alarm.h" + #include "sys/alt_dev.h" + #ifdef __ALTERA_AVALON_JTAG_UART + #include "altera_avalon_jtag_uart.h" + #endif + #endif /* ALT_ASM_SRC */ + + /* These are included for the port register offsets and masks, needed + * to write to the port. Only include if the port type is set correctly, + * otherwise error. If alt_log is turned on and the port to output to is + * incorrect or does not exist, then should exit. */ + #if ALT_LOG_PORT_TYPE == ALTERA_AVALON_JTAG_UART + #ifdef __ALTERA_AVALON_JTAG_UART + #include + #else + #error ALT_LOG: JTAG_UART port chosen, but no JTAG_UART in system. + #endif + #elif ALT_LOG_PORT_TYPE == ALTERA_AVALON_UART + #ifdef __ALTERA_AVALON_UART + #include + #else + #error ALT_LOG: UART Port chosen, but no UART in system. + #endif + #else + #error ALT_LOG: alt_log_port_type declaration invalid! + #endif + + /* ALT_LOG_ENABLE turns on the basic printing function */ + #define ALT_LOG_PRINTF(...) do {alt_log_printf_proc(__VA_ARGS__);} while (0) + + /* Assembly macro for printing in assembly, calls tx_log_str + * which is in alt_log_macro.S. + * If alt_log_boot_on_flag is 0, skips the printing */ + #define ALT_LOG_PUTS(str) movhi r4, %hiadj(alt_log_boot_on_flag) ; \ + addi r4, r4, %lo(alt_log_boot_on_flag) ; \ + ldwio r5, 0(r4) ; \ + beq r0, r5, 0f ; \ + movhi r4, %hiadj(str) ; \ + addi r4, r4, %lo(str) ; \ + call tx_log_str ; \ + 0: + + /* These defines are here to faciliate the use of one output function + * (alt_log_txchar) to print to both the JTAG UART or the UART. Depending + * on the port type, the status register, read mask, and output register + * are set to the appropriate value for the port. */ + #if ALT_LOG_PORT_TYPE == ALTERA_AVALON_JTAG_UART + #define ALT_LOG_PRINT_REG_RD IORD_ALTERA_AVALON_JTAG_UART_CONTROL + #define ALT_LOG_PRINT_MSK ALTERA_AVALON_JTAG_UART_CONTROL_WSPACE_MSK + #define ALT_LOG_PRINT_TXDATA_WR IOWR_ALTERA_AVALON_JTAG_UART_DATA + #define ALT_LOG_PRINT_REG_OFFSET (ALTERA_AVALON_JTAG_UART_CONTROL_REG*0x4) + #define ALT_LOG_PRINT_TXDATA_REG_OFFSET (ALTERA_AVALON_JTAG_UART_DATA_REG*0x4) + #elif ALT_LOG_PORT_TYPE == ALTERA_AVALON_UART + #define ALT_LOG_PRINT_REG_RD IORD_ALTERA_AVALON_UART_STATUS + #define ALT_LOG_PRINT_MSK ALTERA_AVALON_UART_STATUS_TRDY_MSK + #define ALT_LOG_PRINT_TXDATA_WR IOWR_ALTERA_AVALON_UART_TXDATA + #define ALT_LOG_PRINT_REG_OFFSET (ALTERA_AVALON_UART_STATUS_REG*0x4) + #define ALT_LOG_PRINT_TXDATA_REG_OFFSET (ALTERA_AVALON_UART_TXDATA_REG*0x4) + #endif /* ALT_LOG_PORT */ + + /* Grouping of flags via ALT_LOG_FLAGS. Each specific flag can be set via + * -D at compile time, or else they'll be set to a default value according + * to ALT_LOG_FLAGS. ALT_LOG_FLAGS = 0 or not set is the default, where + * only the boot messages will be printed. As ALT_LOG_FLAGS increase, they + * increase in intrusiveness to the program, and will affect performance. + * + * Flag Level 1 - turns on system clock and JTAG UART startup status + * 2 - turns on write echo and JTAG_UART alarm (periodic report) + * 3 - turns on JTAG UART ISR logging - will slow performance + * significantly. + * -1 - All logging output is off, but if ALT_LOG_ENABLE is + * defined all logging function is built and code size + * remains constant + * + * Flag settings - 1 = on, 0 = off. */ + + /* This flag turns on "boot" messages for printing. This includes messages + * during crt0.S, then alt_main, and finally alt_exit. */ + #ifndef ALT_LOG_BOOT_ON_FLAG_SETTING + #if ALT_LOG_FLAGS == 1 + #define ALT_LOG_BOOT_ON_FLAG_SETTING 0x1 + #elif ALT_LOG_FLAGS == 2 + #define ALT_LOG_BOOT_ON_FLAG_SETTING 0x1 + #elif ALT_LOG_FLAGS == 3 + #define ALT_LOG_BOOT_ON_FLAG_SETTING 0x1 + #elif ALT_LOG_FLAGS == -1 /* silent mode */ + #define ALT_LOG_BOOT_ON_FLAG_SETTING 0x0 + #else /* default setting */ + #define ALT_LOG_BOOT_ON_FLAG_SETTING 0x1 + #endif + #endif /* ALT_LOG_BOOT_ON_FLAG_SETTING */ + + #ifndef ALT_LOG_SYS_CLK_ON_FLAG_SETTING + #if ALT_LOG_FLAGS == 1 + #define ALT_LOG_SYS_CLK_ON_FLAG_SETTING 0x1 + #elif ALT_LOG_FLAGS == 2 + #define ALT_LOG_SYS_CLK_ON_FLAG_SETTING 0x1 + #elif ALT_LOG_FLAGS == 3 + #define ALT_LOG_SYS_CLK_ON_FLAG_SETTING 0x1 + #elif ALT_LOG_FLAGS == -1 /* silent mode */ + #define ALT_LOG_SYS_CLK_ON_FLAG_SETTING 0x0 + #else /* default setting */ + #define ALT_LOG_SYS_CLK_ON_FLAG_SETTING 0x0 + #endif + #endif /* ALT_LOG_SYS_CLK_ON_FLAG_SETTING */ + + #ifndef ALT_LOG_WRITE_ON_FLAG_SETTING + #if ALT_LOG_FLAGS == 1 + #define ALT_LOG_WRITE_ON_FLAG_SETTING 0x0 + #elif ALT_LOG_FLAGS == 2 + #define ALT_LOG_WRITE_ON_FLAG_SETTING 0x1 + #elif ALT_LOG_FLAGS == 3 + #define ALT_LOG_WRITE_ON_FLAG_SETTING 0x1 + #elif ALT_LOG_FLAGS == -1 /* silent mode */ + #define ALT_LOG_WRITE_ON_FLAG_SETTING 0x0 + #else /* default setting */ + #define ALT_LOG_WRITE_ON_FLAG_SETTING 0x0 + #endif + #endif /* ALT_LOG_WRITE_ON_FLAG_SETTING */ + + #ifndef ALT_LOG_JTAG_UART_ALARM_ON_FLAG_SETTING + #ifndef __ALTERA_AVALON_JTAG_UART + #define ALT_LOG_JTAG_UART_ALARM_ON_FLAG_SETTING 0x0 + #elif ALT_LOG_FLAGS == 1 + #define ALT_LOG_JTAG_UART_ALARM_ON_FLAG_SETTING 0x0 + #elif ALT_LOG_FLAGS == 2 + #define ALT_LOG_JTAG_UART_ALARM_ON_FLAG_SETTING 0x1 + #elif ALT_LOG_FLAGS == 3 + #define ALT_LOG_JTAG_UART_ALARM_ON_FLAG_SETTING 0x1 + #elif ALT_LOG_FLAGS == -1 /* silent mode */ + #define ALT_LOG_JTAG_UART_ALARM_ON_FLAG_SETTING 0x0 + #else /* default setting */ + #define ALT_LOG_JTAG_UART_ALARM_ON_FLAG_SETTING 0x0 + #endif + #endif /* ALT_LOG_JTAG_UART_ALARM_ON_FLAG_SETTING */ + + #ifndef ALT_LOG_JTAG_UART_STARTUP_INFO_ON_FLAG_SETTING + #ifndef __ALTERA_AVALON_JTAG_UART + #define ALT_LOG_JTAG_UART_STARTUP_INFO_ON_FLAG_SETTING 0x0 + #elif ALT_LOG_FLAGS == 1 + #define ALT_LOG_JTAG_UART_STARTUP_INFO_ON_FLAG_SETTING 0x1 + #elif ALT_LOG_FLAGS == 2 + #define ALT_LOG_JTAG_UART_STARTUP_INFO_ON_FLAG_SETTING 0x1 + #elif ALT_LOG_FLAGS == 3 + #define ALT_LOG_JTAG_UART_STARTUP_INFO_ON_FLAG_SETTING 0x1 + #elif ALT_LOG_FLAGS == -1 /* silent mode */ + #define ALT_LOG_JTAG_UART_STARTUP_INFO_ON_FLAG_SETTING 0x0 + #else /* default setting */ + #define ALT_LOG_JTAG_UART_STARTUP_INFO_ON_FLAG_SETTING 0x0 + #endif + #endif /* ALT_LOG_JTAG_UART_STARTUP_INFO_FLAG_SETTING */ + + #ifndef ALT_LOG_JTAG_UART_ISR_ON_FLAG_SETTING + #ifndef __ALTERA_AVALON_JTAG_UART + #define ALT_LOG_JTAG_UART_ISR_ON_FLAG_SETTING 0x0 + #elif ALT_LOG_FLAGS == 1 + #define ALT_LOG_JTAG_UART_ISR_ON_FLAG_SETTING 0x0 + #elif ALT_LOG_FLAGS == 2 + #define ALT_LOG_JTAG_UART_ISR_ON_FLAG_SETTING 0x0 + #elif ALT_LOG_FLAGS == 3 + #define ALT_LOG_JTAG_UART_ISR_ON_FLAG_SETTING 0x1 + #elif ALT_LOG_FLAGS == -1 /* silent mode */ + #define ALT_LOG_JTAG_UART_ISR_ON_FLAG_SETTING 0x0 + #else /* default setting */ + #define ALT_LOG_JTAG_UART_ISR_ON_FLAG_SETTING 0x0 + #endif + #endif /* ALT_LOG_JTAG_UART_ISR_ON_FLAG_SETTING */ + +#ifndef ALT_ASM_SRC + /* Function Prototypes */ + void alt_log_txchar(int c,char *uartBase); + void alt_log_private_printf(const char *fmt,int base,va_list args); + void alt_log_repchar(char c,int r,int base); + int alt_log_printf_proc(const char *fmt, ... ); + void alt_log_system_clock(); + #ifdef __ALTERA_AVALON_JTAG_UART + alt_u32 altera_avalon_jtag_uart_report_log(void * context); + void alt_log_jtag_uart_startup_info(altera_avalon_jtag_uart_state* dev, int base); + void alt_log_jtag_uart_print_control_reg(altera_avalon_jtag_uart_state* dev, \ + int base, const char* header); + void alt_log_jtag_uart_isr_proc(int base, altera_avalon_jtag_uart_state* dev); + #endif + void alt_log_write(const void *ptr, size_t len); + + /* extern all global variables */ + extern volatile alt_u32 alt_log_boot_on_flag; + extern volatile alt_u8 alt_log_write_on_flag; + extern volatile alt_u8 alt_log_sys_clk_on_flag; + extern volatile alt_u8 alt_log_jtag_uart_alarm_on_flag; + extern volatile alt_u8 alt_log_jtag_uart_isr_on_flag; + extern volatile alt_u8 alt_log_jtag_uart_startup_info_on_flag; + extern volatile int alt_log_sys_clk_count; + extern volatile int alt_system_clock_in_sec; + extern alt_alarm alt_log_jtag_uart_alarm_1; +#endif /* ALT_ASM_SRC */ + + + /* Below are the MACRO defines used in various HAL files. They check + * if their specific flag is turned on; if it is, then it executes its + * code. + * + * To keep this file reasonable, most of these macros calls functions, + * which are defined in alt_log_printf.c. Look there for implementation + * details. */ + + /* Boot Messages Logging */ + #define ALT_LOG_PRINT_BOOT(...) \ + do { if (alt_log_boot_on_flag==1) {ALT_LOG_PRINTF(__VA_ARGS__);} \ + } while (0) + + /* JTAG UART Logging */ + /* number of ticks before alarm runs logging function */ + #ifndef ALT_LOG_JTAG_UART_TICKS_DIVISOR + #define ALT_LOG_JTAG_UART_TICKS_DIVISOR 10 + #endif + #ifndef ALT_LOG_JTAG_UART_TICKS + #define ALT_LOG_JTAG_UART_TICKS \ + (alt_ticks_per_second()/ALT_LOG_JTAG_UART_TICKS_DIVISOR) + #endif + + /* if there's a JTAG UART defined, then enable these macros */ + #ifdef __ALTERA_AVALON_JTAG_UART + + /* Macro in altera_avalon_jtag_uart.c, to register the alarm function. + * Also, the startup register info is also printed here, as this is + * called within the device driver initialization. */ + #define ALT_LOG_JTAG_UART_ALARM_REGISTER(dev, base) \ + do { if (alt_log_jtag_uart_alarm_on_flag==1) { \ + alt_alarm_start(&alt_log_jtag_uart_alarm_1, \ + ALT_LOG_JTAG_UART_TICKS, &altera_avalon_jtag_uart_report_log,\ + dev);} \ + if (alt_log_jtag_uart_startup_info_on_flag==1) {\ + alt_log_jtag_uart_startup_info(dev, base);} \ + } while (0) + + /* JTAG UART IRQ Logging (when buffer is empty) + * Inserted in the ISR in altera_avalon_jtag_uart.c */ + #define ALT_LOG_JTAG_UART_ISR_FUNCTION(base, dev) \ + do { alt_log_jtag_uart_isr_proc(base, dev); } while (0) + /* else, define macros to nothing. Or else the jtag_uart specific types + * will throw compiler errors */ + #else + #define ALT_LOG_JTAG_UART_ALARM_REGISTER(dev, base) + #define ALT_LOG_JTAG_UART_ISR_FUNCTION(base, dev) + #endif + + /* System clock logging + * How often (in seconds) the system clock logging prints. + * The default value is every 1 second */ + #ifndef ALT_LOG_SYS_CLK_INTERVAL_MULTIPLIER + #define ALT_LOG_SYS_CLK_INTERVAL_MULTIPLIER 1 + #endif + #ifndef ALT_LOG_SYS_CLK_INTERVAL + #define ALT_LOG_SYS_CLK_INTERVAL \ + (alt_ticks_per_second()*ALT_LOG_SYS_CLK_INTERVAL_MULTIPLIER) + #endif + + /* System clock logging - prints a message every interval (set above) + * to show that the system clock is alive. + * This macro is used in altera_avalon_timer_sc.c */ + #define ALT_LOG_SYS_CLK_HEARTBEAT() \ + do { alt_log_system_clock(); } while (0) + + /* alt_write_logging - echos a message every time write() is called, + * displays the first ALT_LOG_WRITE_ECHO_LEN characters. + * This macro is used in alt_write.c */ + #ifndef ALT_LOG_WRITE_ECHO_LEN + #define ALT_LOG_WRITE_ECHO_LEN 15 + #endif + + #define ALT_LOG_WRITE_FUNCTION(ptr,len) \ + do { alt_log_write(ptr,len); } while (0) + +#else /* ALT_LOG_ENABLE not defined */ + + /* logging is off, set all relevant macros to null */ + #define ALT_LOG_PRINT_BOOT(...) + #define ALT_LOG_PRINTF(...) + #define ALT_LOG_JTAG_UART_ISR_FUNCTION(base, dev) + #define ALT_LOG_JTAG_UART_ALARM_REGISTER(dev, base) + #define ALT_LOG_SYS_CLK_HEARTBEAT() + #define ALT_LOG_PUTS(str) + #define ALT_LOG_WRITE_FUNCTION(ptr,len) + +#endif /* ALT_LOG_ENABLE */ + +#endif /* __ALT_LOG_PRINTF_H__ */ + diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/sys/alt_set_args.h b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/sys/alt_set_args.h new file mode 100644 index 00000000..3750e67d --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/sys/alt_set_args.h @@ -0,0 +1,71 @@ +#ifndef __ALT_SET_ARGS_H__ +#define __ALT_SET_ARGS_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * The function alt_set_args() is provided in order to define the input + * arguments to main(). If this function is not called before main() then the + * argument list passed to main() will be empty. + * + * It is expected that this function will only be used by the ihost/iclient + * utility. + */ + +static inline void alt_set_args (int argc, char** argv, char** envp) +{ + extern int alt_argc; + extern char** alt_argv; + extern char** alt_envp; + + alt_argc = argc; + alt_argv = argv; + alt_envp = envp; +} + +#ifdef __cplusplus +} +#endif + +#endif /* __ALT_SET_ARGS_H__ */ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/sys/alt_sim.h b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/sys/alt_sim.h new file mode 100644 index 00000000..06bd27aa --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/sys/alt_sim.h @@ -0,0 +1,91 @@ +#ifndef __ALT_SIM_H__ +#define __ALT_SIM_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2007 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ +#include "system.h" +#include "alt_types.h" + +/* + * Instructions that might mean something special to a simulator. + * These have no special effect on real hardware (they are just nops). + */ +#define ALT_SIM_FAIL() \ + do { __asm volatile ("cmpltui r0, r0, 0xabc1"); } while (0) + +#define ALT_SIM_PASS() \ + do { __asm volatile ("cmpltui r0, r0, 0xabc2"); } while (0) + +#define ALT_SIM_IN_TOP_OF_HOT_LOOP() \ + do { __asm volatile ("cmpltui r0, r0, 0xabc3"); } while (0) + +/* + * Routine called on exit. + */ +static ALT_ALWAYS_INLINE void alt_sim_halt(int exit_code) +{ + int r2 = exit_code; + +#if defined(NIOS2_HAS_DEBUG_STUB) && (defined(ALT_BREAK_ON_EXIT) || defined(ALT_PROVIDE_GMON)) + + int r3 = (1 << 2); + +#ifdef ALT_PROVIDE_GMON + extern unsigned int alt_gmon_data[]; + int r4 = (int)alt_gmon_data; + r3 |= (1 << 4); +#define ALT_GMON_DATA ,"D04"(r4) +#else +#define ALT_GMON_DATA +#endif /* ALT_PROVIDE_GMON */ + + if (r2) { + ALT_SIM_FAIL(); + } else { + ALT_SIM_PASS(); + } + + __asm__ volatile ("\n0:\n\taddi %0,%0, -1\n\tbgt %0,zero,0b" : : "r" (ALT_CPU_FREQ/100) ); /* Delay for >30ms */ + + __asm__ volatile ("break 2" : : "D02"(r2), "D03"(r3) ALT_GMON_DATA ); + +#else /* !DEBUG_STUB */ + if (r2) { + ALT_SIM_FAIL(); + } else { + ALT_SIM_PASS(); + } +#endif /* DEBUG_STUB */ +} + +#define ALT_SIM_HALT(exit_code) \ + alt_sim_halt(exit_code) + +#endif /* __ALT_SIM_H__ */ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/sys/alt_stack.h b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/sys/alt_stack.h new file mode 100644 index 00000000..e30652ab --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/sys/alt_stack.h @@ -0,0 +1,126 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#ifndef __ALT_STACK_H__ +#define __ALT_STACK_H__ + +/* + * alt_stack.h is the nios2 specific implementation of functions used by the + * stack overflow code. + */ + +#include "nios2.h" + +#include "alt_types.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + + +extern char * alt_stack_limit_value; + +#ifdef ALT_EXCEPTION_STACK +extern char __alt_exception_stack_pointer[]; /* set by the linker */ +#endif /* ALT_EXCEPTION_STACK */ + + +/* + * alt_stack_limit can be called to determine the current value of the stack + * limit register. + */ + +static ALT_INLINE char * ALT_ALWAYS_INLINE alt_stack_limit (void) +{ + char * limit; + NIOS2_READ_ET(limit); + + return limit; +} + +/* + * alt_stack_pointer can be called to determine the current value of the stack + * pointer register. + */ + +static ALT_INLINE char * ALT_ALWAYS_INLINE alt_stack_pointer (void) +{ + char * pointer; + NIOS2_READ_SP(pointer); + + return pointer; +} + + +#ifdef ALT_EXCEPTION_STACK + +/* + * alt_exception_stack_pointer returns the normal stack pointer from + * where it is stored on the exception stack (uppermost 4 bytes). This + * is really only useful during exception processing, and is only + * available if a separate exception stack has been configured. + */ + +static ALT_INLINE char * ALT_ALWAYS_INLINE alt_exception_stack_pointer (void) +{ + return (char *) *(alt_u32 *)(__alt_exception_stack_pointer - sizeof(alt_u32)); +} + +#endif /* ALT_EXCEPTION_STACK */ + + +/* + * alt_set_stack_limit can be called to update the current value of the stack + * limit register. + */ + +static ALT_INLINE void ALT_ALWAYS_INLINE alt_set_stack_limit (char * limit) +{ + alt_stack_limit_value = limit; + NIOS2_WRITE_ET(limit); +} + +/* + * alt_report_stack_overflow reports that a stack overflow happened. + */ + +static ALT_INLINE void ALT_ALWAYS_INLINE alt_report_stack_overflow (void) +{ + NIOS2_REPORT_STACK_OVERFLOW(); +} + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALT_STACK_H__ */ + diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/sys/alt_stdio.h b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/sys/alt_stdio.h new file mode 100644 index 00000000..17303605 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/sys/alt_stdio.h @@ -0,0 +1,62 @@ +#ifndef __ALT_STDIO_H__ +#define __ALT_STDIO_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +/* + * Definitions for ALT stdio routines. + */ + +#include + + +#ifdef __cplusplus +extern "C" { +#endif + +int alt_getchar(); +int alt_putchar(int c); +int alt_putstr(const char* str); +void alt_printf(const char *fmt, ...); + +#ifdef __cplusplus +} +#endif + +#endif /* __ALT_STDIO_H__ */ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/sys/alt_sys_init.h b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/sys/alt_sys_init.h new file mode 100644 index 00000000..e4abc287 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/sys/alt_sys_init.h @@ -0,0 +1,62 @@ +#ifndef __ALT_SYS_INIT_H__ +#define __ALT_SYS_INIT_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * The function alt_sys_init() is defined within the auto-generated file: + * alt_sys_init.c. This function calls the initilisation macros for all + * devices, file systems, and software components within the system. + * + * The list of initilisation macros to use is constructed using the PTF and + * STF files associated with the system. + */ + +extern void alt_sys_init (void); + +#ifdef __cplusplus +} +#endif + +#endif /* __ALT_SYS_INIT_H__ */ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/sys/alt_sys_wrappers.h b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/sys/alt_sys_wrappers.h new file mode 100644 index 00000000..044833b4 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/sys/alt_sys_wrappers.h @@ -0,0 +1,100 @@ +#ifndef __ALT_SYS_WRAPPERS_H__ +#define __ALT_SYS_WRAPPERS_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +/* + * This file provides the prototypes for the HAL 'UNIX style functions. The + * names of these functions are defined in alt_syscall.h. THese are defined to + * be the standard names when running the standalone HAL, e.g. open(), close() + * etc., but the names may be redefined as a part of an operating system port + * in order to avoid name clashes. + */ + +#include "os/alt_syscall.h" + +#include +#include +#include +#include +#include +#include + +extern int ALT_CLOSE (int __fd); +extern int ALT_EXECVE (const char *__path, + char * const __argv[], + char * const __envp[]); +extern void ALT_EXIT (int __status); +extern int ALT_FSTAT (int file, struct stat *st); +extern int ALT_FCNTL (int file, int cmd, ...); +extern pid_t ALT_FORK (void); +extern pid_t ALT_GETPID (void); + +#if defined (__GNUC__) && __GNUC__ >= 4 +extern int ALT_GETTIMEOFDAY (struct timeval *ptimeval, + void *ptimezone); +#else +extern int ALT_GETTIMEOFDAY (struct timeval *ptimeval, + struct timezone *ptimezone); +#endif + +extern int ALT_IOCTL (int file, int req, void* arg); +extern int ALT_ISATTY (int file); +extern int ALT_KILL (int pid, int sig); +extern int ALT_LINK (const char *existing, const char *new); +extern off_t ALT_LSEEK (int file, off_t ptr, int dir); +extern int ALT_OPEN (const char* file, int flags, ...); +extern int ALT_READ (int file, void *ptr, size_t len); +extern int ALT_RENAME (char *existing, char *new); +extern void* ALT_SBRK (ptrdiff_t incr); +extern int ALT_SETTIMEOFDAY (const struct timeval *t, + const struct timezone *tz); +extern int ALT_STAT (const char *file, struct stat *st); +extern clock_t ALT_TIMES (struct tms *buf); +extern int ALT_UNLINK (const char *name); + +#if defined (__GNUC__) && __GNUC__ >= 4 +int ALT_USLEEP (useconds_t us); +#else +unsigned int ALT_USLEEP (unsigned int us); +#endif + +extern int ALT_WAIT (int *status); +extern int ALT_WRITE (int file, const void *ptr, size_t len); + + +extern char** ALT_ENVIRON; + +/* + * + */ + +#endif /* __ALT_SYS_WRAPPERS_H__ */ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/sys/alt_timestamp.h b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/sys/alt_timestamp.h new file mode 100644 index 00000000..8a18da22 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/sys/alt_timestamp.h @@ -0,0 +1,60 @@ +#ifndef __ALT_TIMESTAMP_H__ +#define __ALT_TIMESTAMP_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +#include "alt_types.h" +#include "altera_avalon_timer.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +extern int alt_timestamp_start (void); + +extern alt_timestamp_type alt_timestamp (void); + +extern alt_u32 alt_timestamp_freq (void); + +#ifdef __cplusplus +} +#endif + +#endif /* __ALT_TIMESTAMP_H__ */ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/sys/alt_warning.h b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/sys/alt_warning.h new file mode 100644 index 00000000..b66e71a2 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/sys/alt_warning.h @@ -0,0 +1,75 @@ +#ifndef __WARNING_H__ +#define __WARNING_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +/* + * alt_warning.h provides macro definitions that can be used to generate link + * time warnings. + */ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * The symbol "__alt_invalid" is used to force a link error. There should be + * no corresponding implementation of this function. + */ + +extern void __alt_invalid (void); + +#define ALT_LINK_WARNING(symbol, msg) \ + __asm__(".ifndef __evoke_link_warning_" #symbol \ + "\n\t .section .gnu.warning." #symbol \ + "\n__evoke_link_warning_" #symbol ":\n\t .string \x22" msg "\x22 \n\t .previous" \ + "\n .endif"); + +/* A canned warning for sysdeps/stub functions. */ + +#define ALT_STUB_WARNING(name) \ + ALT_LINK_WARNING (name, \ + "warning: " #name " is not implemented and will always fail") + +#define ALT_OBSOLETE_FUNCTION_WARNING(name) \ + ALT_LINK_WARNING (name, \ + "warning: " #name " is a deprecated function") + +#define ALT_LINK_ERROR(msg) \ + ALT_LINK_WARNING (__alt_invalid, msg); \ + __alt_invalid() + +#ifdef __cplusplus +} +#endif + +#endif /* __WARNING_H__ */ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/sys/ioctl.h b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/sys/ioctl.h new file mode 100644 index 00000000..4d565df3 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/sys/ioctl.h @@ -0,0 +1,90 @@ +#ifndef __IOCTL_H__ +#define __IOCTL_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * The ioctl() system call be used to initiate a variety of control operations + * on a file descriptor. For the most part this simply translates to a call to + * the ioctl() function of the associated device driver (TIOCEXCL and + * TIOCNXCL are notable exceptions - see ioctl.c for details). + * + * The interpretation of the ioctl requests are therefore device specific. + * + * This function is equivalent to the standard Posix ioctl() call. + */ + +extern int ioctl (int fd, int req, void* arg); + +/* + * list of ioctl calls handled by the system ioctl implementation. + */ + +#define TIOCEXCL 0x740d /* exclusive use of the device */ +#define TIOCNXCL 0x740e /* allow multiple use of the device */ + +/* + * ioctl calls which can be handled by device drivers. + */ + +#define TIOCOUTQ 0x7472 /* get output queue size */ +#define TIOCMGET 0x741d /* get termios flags */ +#define TIOCMSET 0x741a /* set termios flags */ + +/* + * ioctl calls specific to JTAG UART. + */ + +#define TIOCSTIMEOUT 0x6a01 /* Set Timeout before assuming no host present */ +#define TIOCGCONNECTED 0x6a02 /* Get indication of whether host is connected */ + +/* + * + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __IOCTL_H__ */ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/sys/termios.h b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/sys/termios.h new file mode 100644 index 00000000..cd09539f --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/inc/sys/termios.h @@ -0,0 +1,181 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT. * +* * +******************************************************************************/ + +/* + * This is the termios.h file provided with newlib. The only modification has + * been to the baud rate macro definitions, and an increase in the size of the + * termios structure to accomodate this. + */ + + +#ifndef _SYS_TERMIOS_H +# define _SYS_TERMIOS_H + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +# define _XCGETA (('x'<<8)|1) +# define _XCSETA (('x'<<8)|2) +# define _XCSETAW (('x'<<8)|3) +# define _XCSETAF (('x'<<8)|4) +# define _TCSBRK (('T'<<8)|5) +# define _TCFLSH (('T'<<8)|7) +# define _TCXONC (('T'<<8)|6) + +# define TCOOFF 0 +# define TCOON 1 +# define TCIOFF 2 +# define TCION 3 + +# define TCIFLUSH 0 +# define TCOFLUSH 1 +# define TCIOFLUSH 2 + +# define NCCS 13 + +# define TCSAFLUSH _XCSETAF +# define TCSANOW _XCSETA +# define TCSADRAIN _XCSETAW +# define TCSADFLUSH _XCSETAF + +# define IGNBRK 000001 +# define BRKINT 000002 +# define IGNPAR 000004 +# define INPCK 000020 +# define ISTRIP 000040 +# define INLCR 000100 +# define IGNCR 000200 +# define ICRNL 000400 +# define IXON 002000 +# define IXOFF 010000 + +# define OPOST 000001 +# define OCRNL 000004 +# define ONLCR 000010 +# define ONOCR 000020 +# define TAB3 014000 + +# define CLOCAL 004000 +# define CREAD 000200 +# define CSIZE 000060 +# define CS5 0 +# define CS6 020 +# define CS7 040 +# define CS8 060 +# define CSTOPB 000100 +# define HUPCL 002000 +# define PARENB 000400 +# define PAODD 001000 + +#define CCTS_OFLOW 010000 +#define CRTS_IFLOW 020000 +#define CRTSCTS (CCTS_OFLOW | CRTS_IFLOW) + +# define ECHO 0000010 +# define ECHOE 0000020 +# define ECHOK 0000040 +# define ECHONL 0000100 +# define ICANON 0000002 +# define IEXTEN 0000400 /* anybody know *what* this does?! */ +# define ISIG 0000001 +# define NOFLSH 0000200 +# define TOSTOP 0001000 + +# define VEOF 4 /* also VMIN -- thanks, AT&T */ +# define VEOL 5 /* also VTIME -- thanks again */ +# define VERASE 2 +# define VINTR 0 +# define VKILL 3 +# define VMIN 4 /* also VEOF */ +# define VQUIT 1 +# define VSUSP 10 +# define VTIME 5 /* also VEOL */ +# define VSTART 11 +# define VSTOP 12 + +# define B0 0 +# define B50 50 +# define B75 75 +# define B110 110 +# define B134 134 +# define B150 150 +# define B200 200 +# define B300 300 +# define B600 600 +# define B1200 1200 +# define B1800 1800 +# define B2400 2400 +# define B4800 4800 +# define B9600 9600 +# define B19200 19200 +# define B38400 38400 +# define B57600 57600 +# define B115200 115200 + +typedef unsigned char cc_t; +typedef unsigned short tcflag_t; +typedef unsigned long speed_t; + +struct termios { + tcflag_t c_iflag; + tcflag_t c_oflag; + tcflag_t c_cflag; + tcflag_t c_lflag; + char c_line; + cc_t c_cc[NCCS]; + speed_t c_ispeed; + speed_t c_ospeed; +}; + +# ifndef _NO_MACROS + +# define cfgetospeed(tp) ((tp)->c_ospeed) +# define cfgetispeed(tp) ((tp)->c_ispeed) +# define cfsetospeed(tp,s) (((tp)->c_ospeed = (s)), 0) +# define cfsetispeed(tp,s) (((tp)->c_ispeed = (s)), 0) +# define tcdrain(fd) _ioctl (fd, _TCSBRK, 1) +# endif /* _NO_MACROS */ + +#ifdef __cplusplus +} +#endif + +#endif /* _SYS_TERMIOS_H */ + diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_alarm_start.c b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_alarm_start.c new file mode 100644 index 00000000..7739959a --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_alarm_start.c @@ -0,0 +1,112 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include + +#include "sys/alt_alarm.h" +#include "sys/alt_irq.h" + +/* + * alt_alarm_start is called to register an alarm with the system. The + * "alarm" structure passed as an input argument does not need to be + * initialised by the user. This is done within this function. + * + * The remaining input arguments are: + * + * nticks - The time to elapse until the alarm executes. This is specified in + * system clock ticks. + * callback - The function to run when the indicated time has elapsed. + * context - An opaque value, passed to the callback function. +* + * Care should be taken when defining the callback function since it is + * likely to execute in interrupt context. In particular, this mean that + * library calls like printf() should not be made, since they can result in + * deadlock. + * + * The interval to be used for the next callback is the return + * value from the callback function. A return value of zero indicates that the + * alarm should be unregistered. + * + * alt_alarm_start() will fail if the timer facility has not been enabled + * (i.e. there is no system clock). Failure is indicated by a negative return + * value. + */ + +int alt_alarm_start (alt_alarm* alarm, alt_u32 nticks, + alt_u32 (*callback) (void* context), + void* context) +{ + alt_irq_context irq_context; + alt_u32 current_nticks = 0; + + if (alt_ticks_per_second ()) + { + if (alarm) + { + alarm->callback = callback; + alarm->context = context; + + irq_context = alt_irq_disable_all (); + + current_nticks = alt_nticks(); + + alarm->time = nticks + current_nticks + 1; + + /* + * If the desired alarm time causes a roll-over, set the rollover + * flag. This will prevent the subsequent tick event from causing + * an alarm too early. + */ + if(alarm->time < current_nticks) + { + alarm->rollover = 1; + } + else + { + alarm->rollover = 0; + } + + alt_llist_insert (&alt_alarm_list, &alarm->llist); + alt_irq_enable_all (irq_context); + + return 0; + } + else + { + return -EINVAL; + } + } + else + { + return -ENOTSUP; + } +} diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_busy_sleep.c b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_busy_sleep.c new file mode 100644 index 00000000..561c0bed --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_busy_sleep.c @@ -0,0 +1,133 @@ +/* + * Copyright (c) 2003-2004 Altera Corporation, San Jose, California, USA. + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * ------------ + * + * Altera does not recommend, suggest or require that this reference design + * file be used in conjunction or combination with any other product. + * + * alt_busy_sleep.c - Microsecond delay routine which uses a calibrated busy + * loop to perform the delay. This is used to implement + * usleep for both uC/OS-II and the standalone HAL. + * + * Author PRR + * + * Calibrated delay with no timer required + * + * The ASM instructions in the routine are equivalent to + * + * for (i=0;i +#include + +#include "system.h" +#include "alt_types.h" + +#include "priv/alt_busy_sleep.h" + +unsigned int alt_busy_sleep (unsigned int us) +{ +/* + * Only delay if ALT_SIM_OPTIMIZE is not defined; i.e., if software + * is built targetting ModelSim RTL simulation, the delay will be + * skipped to speed up simulation. + */ +#ifndef ALT_SIM_OPTIMIZE + int i; + int big_loops; + alt_u32 cycles_per_loop; + + if (!strcmp(NIOS2_CPU_IMPLEMENTATION,"tiny")) + { + cycles_per_loop = 9; + } + else + { + cycles_per_loop = 3; + } + + + big_loops = us / (INT_MAX/ + (ALT_CPU_FREQ/(cycles_per_loop * 1000000))); + + if (big_loops) + { + for(i=0;i + +#include "sys/alt_errno.h" +#include "sys/alt_warning.h" +#include "priv/alt_file.h" +#include "os/alt_syscall.h" + +#ifdef ALT_USE_DIRECT_DRIVERS + +int ALT_CLOSE (int fildes) +{ + /* Generate a link time warning, should this function ever be called. */ + + ALT_STUB_WARNING(close); + + /* Indicate an error */ + + ALT_ERRNO = ENOSYS; + return -1; +} + +#else /* !ALT_USE_DIRECT_DRIVERS */ + +/* + * close() is called by an application to release a file descriptor. If the + * associated file system/device has a close() callback function registered + * then this called. The file descriptor is then marked as free. + * + * ALT_CLOSE is mapped onto the close() system call in alt_syscall.h + */ + +int ALT_CLOSE (int fildes) +{ + alt_fd* fd; + int rval; + + /* + * A common error case is that when the file descriptor was created, the call + * to open() failed resulting in a negative file descriptor. This is trapped + * below so that we don't try and process an invalid file descriptor. + */ + + fd = (fildes < 0) ? NULL : &alt_fd_list[fildes]; + + if (fd) + { + /* + * If the associated file system/device has a close function, call it so + * that any necessary cleanup code can run. + */ + + rval = (fd->dev->close) ? fd->dev->close(fd) : 0; + + /* Free the file descriptor structure and return. */ + + alt_release_fd (fildes); + if (rval < 0) + { + ALT_ERRNO = -rval; + return -1; + } + return 0; + } + else + { + ALT_ERRNO = EBADFD; + return -1; + } +} + +#endif /* ALT_USE_DIRECT_DRIVERS */ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_dcache_flush.c b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_dcache_flush.c new file mode 100644 index 00000000..7ecc91ac --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_dcache_flush.c @@ -0,0 +1,97 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003-2005 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include "nios2.h" +#include "system.h" + +#include "alt_types.h" +#include "sys/alt_cache.h" + +/* + * Nios II version 1.2 and newer supports the "flush by address" instruction, in + * addition to the "flush by line" instruction provided by older versions of + * the core. This newer instruction is used by preference when it is + * available. + */ + +#ifdef NIOS2_FLUSHDA_SUPPORTED +#define ALT_FLUSH_DATA(i) __asm__ volatile ("flushda (%0)" :: "r" (i)); +#else +#define ALT_FLUSH_DATA(i) __asm__ volatile ("flushd (%0)" :: "r" (i)); +#endif /* NIOS2_FLUSHDA_SUPPORTED */ + +/* + * alt_dcache_flush() is called to flush the data cache for a memory + * region of length "len" bytes, starting at address "start". + * + * Any dirty lines in the data cache are written back to memory. + */ + +void alt_dcache_flush (void* start, alt_u32 len) +{ +#if NIOS2_DCACHE_SIZE > 0 + + char* i; + char* end; + + /* + * This is the most we would ever need to flush. + * + * SPR 196942, 2006.01.13: The cache flush loop below will use the + * 'flushda' instruction if its available; in that case each line + * must be flushed individually, and thus 'len' cannot be trimmed. + */ + #ifndef NIOS2_FLUSHDA_SUPPORTED + if (len > NIOS2_DCACHE_SIZE) + { + len = NIOS2_DCACHE_SIZE; + } + #endif + + end = ((char*) start) + len; + + for (i = start; i < end; i+= NIOS2_DCACHE_LINE_SIZE) + { + ALT_FLUSH_DATA(i); + } + + /* + * For an unaligned flush request, we've got one more line left. + * Note that this is dependent on NIOS2_DCACHE_LINE_SIZE to be a + * multiple of 2 (which it always is). + */ + + if (((alt_u32) start) & (NIOS2_DCACHE_LINE_SIZE - 1)) + { + ALT_FLUSH_DATA(i); + } + +#endif /* NIOS2_DCACHE_SIZE > 0 */ +} diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_dcache_flush_all.c b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_dcache_flush_all.c new file mode 100644 index 00000000..6529231a --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_dcache_flush_all.c @@ -0,0 +1,51 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003-2005 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include "nios2.h" +#include "system.h" + +#include "alt_types.h" +#include "sys/alt_cache.h" + +/* + * alt_dcache_flush_all() is called to flush the entire data cache. + */ + +void alt_dcache_flush_all (void) +{ +#if NIOS2_DCACHE_SIZE > 0 + char* i; + + for (i = (char*) 0; i < (char*) NIOS2_DCACHE_SIZE; i+= NIOS2_DCACHE_LINE_SIZE) + { + __asm__ volatile ("flushd (%0)" :: "r" (i)); + } +#endif /* NIOS2_DCACHE_SIZE > 0 */ +} diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_dcache_flush_no_writeback.c b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_dcache_flush_no_writeback.c new file mode 100644 index 00000000..c65ca7dc --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_dcache_flush_no_writeback.c @@ -0,0 +1,88 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2007 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include "nios2.h" +#include "system.h" + +#include "alt_types.h" +#include "sys/alt_cache.h" + +/* + * The INITDA instruction was added to Nios II in the 8.0 release. + * + * The INITDA instruction has one of the following possible behaviors + * depending on the processor configuration: + * 1) Flushes a line by address but does NOT write back dirty data. + * Occurs when a data cache is present that supports INITDA. + * The macro NIOS2_INITDA_SUPPORTED is defined in system.h. + * 2) Takes an unimplemented instruction exception. + * Occurs when a data cache is present that doesn't support INITDA. + * 3) Performs no operation + * Occurs when there is no data cache present. + * The macro NIOS2_DCACHE_SIZE is 0 in system.h. + */ + +#define ALT_FLUSH_DATA_NO_WRITEBACK(i) \ + __asm__ volatile ("initda (%0)" :: "r" (i)); + +/* + * alt_dcache_flush_no_writeback() is called to flush the data cache for a + * memory region of length "len" bytes, starting at address "start". + * + * Any dirty lines in the data cache are NOT written back to memory. + * Make sure you really want this behavior. If you aren't 100% sure, + * use the alt_dcache_flush() routine instead. + */ + +void alt_dcache_flush_no_writeback (void* start, alt_u32 len) +{ +#if defined(NIOS2_INITDA_SUPPORTED) + + char* i; + char* end = ((char*) start) + len; + + for (i = start; i < end; i+= NIOS2_DCACHE_LINE_SIZE) + { + ALT_FLUSH_DATA_NO_WRITEBACK(i); + } + + /* + * For an unaligned flush request, we've got one more line left. + * Note that this is dependent on NIOS2_DCACHE_LINE_SIZE to be a + * multiple of 2 (which it always is). + */ + + if (((alt_u32) start) & (NIOS2_DCACHE_LINE_SIZE - 1)) + { + ALT_FLUSH_DATA_NO_WRITEBACK(i); + } + +#endif /* NIOS2_INITDA_SUPPORTED */ +} diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_dev.c b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_dev.c new file mode 100644 index 00000000..ebc15e59 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_dev.c @@ -0,0 +1,149 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include +#include +#include +#include +#include + +#include "sys/alt_dev.h" +#include "priv/alt_file.h" + +#include "alt_types.h" + +#include "system.h" + +/* + * This file contains the data constructs used to control access to device and + * filesytems. + */ + +/* + * "alt_fs_list" is the head of a linked list of registered filesystems. It is + * initialised as an empty list. New entries can be added using the + * alt_fs_reg() function. + */ + +ALT_LLIST_HEAD(alt_fs_list); + + +/* + * "alt_dev_list" is the head of a linked list of registered devices. It is + * configured at startup to include a single device, "alt_dev_null". This + * device is discussed below. + */ + +extern alt_dev alt_dev_null; /* forward declaration */ + +alt_llist alt_dev_list = {&alt_dev_null.llist, &alt_dev_null.llist}; + +/* + * alt_dev_null_write() is the implementation of the write() function used + * by the alt_dev_null device. It simple discards all data passed to it, and + * indicates that the data has been successfully transmitted. + */ + +static int alt_dev_null_write (alt_fd* fd, const char* ptr, int len) +{ + return len; +} + +/* + * "alt_dev_null" is used to allow output to be redirected to nowhere. It is + * the only device registered before the call to alt_sys_init(). At startup + * stin, stdout & stderr are all directed towards this device so that library + * calls like printf() will be safe but inefectual. + */ + +alt_dev alt_dev_null = { + { + &alt_dev_list, + &alt_dev_list + }, + "/dev/null", + NULL, /* open */ + NULL, /* close */ + NULL, /* write */ + alt_dev_null_write, /* write */ + NULL, /* lseek */ + NULL, /* fstat */ + NULL /* ioctl */ + }; + +/* + * "alt_fd_list_lock" is a semaphore used to control access to the file + * descriptor list. This is used to ensure that access to the list is thread + * safe. + */ + +ALT_SEM(alt_fd_list_lock) + +/* + * "alt_max_fd" is used to make access to the file descriptor list more + * efficent. It is set to be the value of the highest allocated file + * descriptor. This saves having to search the entire pool of unallocated + * file descriptors when looking for a match. + */ + +alt_32 alt_max_fd = -1; + +/* + * "alt_fd_list" is the file descriptor pool. The first three entries in the + * array are configured as standard in, standard out, and standard error. These + * are all initialised so that accesses are directed to the alt_dev_null + * device. The remaining file descriptors are initialised as unallocated. + * + * The maximum number of file descriptors within the system is specified by the + * user defined macro "ALT_MAX_FD". This is defined in "system.h", which is + * auto-genereated using the projects PTF and STF files. + */ + +alt_fd alt_fd_list[ALT_MAX_FD] = + { + { + &alt_dev_null, /* standard in */ + 0, + 0 + }, + { + &alt_dev_null, /* standard out */ + 0, + 0 + }, + { + &alt_dev_null, /* standard error */ + 0, + 0 + } + /* all other elements are set to zero */ + }; diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_dev_llist_insert.c b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_dev_llist_insert.c new file mode 100644 index 00000000..fa7239dc --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_dev_llist_insert.c @@ -0,0 +1,59 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include "priv/alt_dev_llist.h" +#include "sys/alt_errno.h" + +/* + * + */ + +int alt_dev_llist_insert (alt_dev_llist* dev, alt_llist* list) +{ + /* + * check that the device exists, and that it has a valid name. + */ + + if (!dev || !dev->name) + { + ALT_ERRNO = EINVAL; + return -EINVAL; + } + + /* + * register the device. + */ + + alt_llist_insert(list, &dev->llist); + + return 0; +} diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_dma_rxchan_open.c b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_dma_rxchan_open.c new file mode 100644 index 00000000..6ea3b78e --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_dma_rxchan_open.c @@ -0,0 +1,63 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include "sys/alt_dma.h" +#include "sys/alt_errno.h" +#include "priv/alt_file.h" + +/* + * The list of registered DMA receive channels. + */ + +ALT_LLIST_HEAD(alt_dma_rxchan_list); + +/* + * alt_dma_txchan_open() is used to obtain an "alt_dma_txchan" descriptor for + * a DMA transmit device. The name is the name of the associated physical + * device (e.g. "/dev/dma_0"). + * + * The return value will be NULL on failure, and non-NULL otherwise. + */ + +alt_dma_rxchan alt_dma_rxchan_open (const char* name) +{ + alt_dma_rxchan dev; + + dev = (alt_dma_rxchan) alt_find_dev (name, &alt_dma_rxchan_list); + + if (!dev) + { + ALT_ERRNO = ENODEV; + } + + return dev; +} diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_dma_txchan_open.c b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_dma_txchan_open.c new file mode 100644 index 00000000..f41fa813 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_dma_txchan_open.c @@ -0,0 +1,63 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include "sys/alt_dma.h" +#include "sys/alt_errno.h" +#include "priv/alt_file.h" + +/* + * The list of registered receive channels. + */ + +ALT_LLIST_HEAD(alt_dma_txchan_list); + +/* + * alt_dma_txchan_open() is used to obtain an "alt_dma_txchan" descriptor for + * a DMA transmit device. The name is the name of the associated physical + * device (e.g. "/dev/dma_0"). + * + * The return value will be NULL on failure, and non-NULL otherwise. + */ + +alt_dma_txchan alt_dma_txchan_open (const char* name) +{ + alt_dma_txchan dev; + + dev = (alt_dma_txchan) alt_find_dev (name, &alt_dma_txchan_list); + + if (!dev) + { + ALT_ERRNO = ENODEV; + } + + return dev; +} diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_do_ctors.c b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_do_ctors.c new file mode 100644 index 00000000..ff5a1f7b --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_do_ctors.c @@ -0,0 +1,64 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT IT DIRECTLY. * +* * +* Overriding HAL Functions * +* * +* To provide your own implementation of a HAL function, include the file in * +* your Nios II IDE application project. When building the executable, the * +* Nios II IDE finds your function first, and uses it in place of the HAL * +* version. * +* * +******************************************************************************/ + +/* + * + */ + +typedef void (*constructor) (void); +extern constructor __CTOR_LIST__[]; +extern constructor __CTOR_END__[]; + +/* + * Run the C++ static constructors. + */ + +void _do_ctors(void) +{ + constructor* ctor; + + for (ctor = &__CTOR_END__[-1]; ctor >= __CTOR_LIST__; ctor--) + (*ctor) (); +} diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_do_dtors.c b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_do_dtors.c new file mode 100644 index 00000000..565c99fa --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_do_dtors.c @@ -0,0 +1,64 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* THIS IS A LIBRARY READ-ONLY SOURCE FILE. DO NOT EDIT IT DIRECTLY. * +* * +* Overriding HAL Functions * +* * +* To provide your own implementation of a HAL function, include the file in * +* your Nios II IDE application project. When building the executable, the * +* Nios II IDE finds your function first, and uses it in place of the HAL * +* version. * +* * +******************************************************************************/ + +/* + * + */ + +typedef void (*destructor) (void); +extern destructor __DTOR_LIST__[]; +extern destructor __DTOR_END__[]; + +/* + * Run the C++ static destructors. + */ + +void _do_dtors(void) +{ + destructor* dtor; + + for (dtor = &__DTOR_END__[-1]; dtor >= __DTOR_LIST__; dtor--) + (*dtor) (); +} diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_environ.c b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_environ.c new file mode 100644 index 00000000..404efc4a --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_environ.c @@ -0,0 +1,42 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include "os/alt_syscall.h" + +/* + * These are the environment variables passed to the C code. By default there + * are no variables registered. An application can manipulate this list using + * getenv() and setenv(). + */ + +char *__env[1] = { 0 }; +char **ALT_ENVIRON = __env; diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_errno.c b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_errno.c new file mode 100644 index 00000000..1d8368db --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_errno.c @@ -0,0 +1,44 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/* + * This file defines the alt_errno global variable. See comments in + * alt_errno.h for the use of this variable. + */ + + +#include "sys/alt_errno.h" +#include "alt_types.h" + +extern int ALT_WEAK *__errno (void); + +int* (*alt_errno) (void) = __errno; diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_exception_entry.S b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_exception_entry.S new file mode 100644 index 00000000..3afab937 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_exception_entry.S @@ -0,0 +1,360 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003-2008 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include "system.h" + +/* + * This is the exception entry point code, which saves all the caller saved + * registers and then handles the appropriate exception. It should be pulled + * in using a .globl from all the exception handler routines. This scheme is + * used so that if an interrupt is never registered, then this code will not + * appear in the generated executable, thereby improving code footprint. + * + * If an external interrpt controller (EIC) is present, it will supply an + * interrupt vector address to the processor when an interrupt occurs. For + * The Altera Vectored Interrupt Controller (VIC) driver will establish a + * vector table and the processor will jump directly to the appropriate + * table entry, funnel routine, and then user ISR. This will bypass this code + * in entirety. This code might still be linked into a system with an EIC, + * but would then be used only for non-interrupt exceptions. + */ + + /* + * Explicitly allow the use of r1 (the assembler temporary register) + * within this code. This register is normally reserved for the use of + * the assembler. + */ + .set noat + + /* + * The top and bottom of the exception stack + */ +#ifdef ALT_EXCEPTION_STACK + + .globl __alt_exception_stack_pointer + +#ifdef ALT_STACK_CHECK + + .globl __alt_exception_stack_limit + + /* + * We need to store the value of the stack limit after interrupt somewhere. + */ + .globl alt_exception_old_stack_limit + +#endif +#endif + + .section .exceptions.entry.label, "xa" + + .globl alt_exception + .type alt_exception, @function +alt_exception: + + .section .exceptions.entry, "xa" + +#ifdef ALT_EXCEPTION_STACK + +#ifdef ALT_STACK_CHECK + stw et, %gprel(alt_exception_old_stack_limit)(gp) +#endif + + movhi et, %hiadj(__alt_exception_stack_pointer - 80) + addi et, et, %lo(__alt_exception_stack_pointer - 80) + stw sp, 76(et) + mov sp, et + +#ifdef ALT_STACK_CHECK + movhi et, %hiadj(__alt_exception_stack_limit) + addi et, et, %lo(__alt_exception_stack_limit) + stw et, %gprel(alt_stack_limit_value)(gp) +#endif + +#else + /* + * Process an exception. For all exceptions we must preserve all + * caller saved registers on the stack (See the Nios2 ABI + * documentation for details). + */ + + addi sp, sp, -76 + +#ifdef ALT_STACK_CHECK + + bltu sp, et, .Lstack_overflow + +#endif + +#endif + + stw ra, 0(sp) + + /* + * Leave a gap in the stack frame at 4(sp) for the muldiv handler to + * store zero into. + */ + + stw r1, 8(sp) + stw r2, 12(sp) + stw r3, 16(sp) + stw r4, 20(sp) + stw r5, 24(sp) + stw r6, 28(sp) + stw r7, 32(sp) + + rdctl r5, estatus + + stw r8, 36(sp) + stw r9, 40(sp) + stw r10, 44(sp) + stw r11, 48(sp) + stw r12, 52(sp) + stw r13, 56(sp) + stw r14, 60(sp) + stw r15, 64(sp) + + /* + * ea-4 contains the address of the instruction being executed + * when the exception occured. For interrupt exceptions, we will + * will be re-issue the isntruction. Store it in 72(sp) + */ + stw r5, 68(sp) /* estatus */ + addi r15, ea, -4 /* instruction that caused exception */ + stw r15, 72(sp) + + /* + * The interrupt testing code (.exceptions.irqtest) will be + * linked here. If the Internal Interrupt Controller (IIC) is + * present (an EIC is not present), the presense of an interrupt + * is determined by examining CPU control registers or an interrupt + * custom instruction, if present. + * + * If the IIC is used and an interrupt is active, the code linked + * here will call the HAL IRQ handler (alt_irq_handler()) which + * successively calls registered interrupt handler(s) until no + * interrupts remain pending. It then jumps to .exceptions.exit. If + * there is no interrupt then it continues to .exception.notirq, below. + */ + + .section .exceptions.notirq, "xa" + + /* + * Prepare to service unimplemtned instructions or traps, + * each of which is optionally inked into section .exceptions.soft, + * which will preceed .exceptions.unknown below. + * + * Unlike interrupts, we want to skip the exception-causing instructon + * upon completion, so we write ea (address of instruction *after* + * the one where the exception occured) into 72(sp). The actual + * instruction that caused the exception is written in r2, which these + * handlers will utilize. + */ + stw ea, 72(sp) /* Don't re-issue */ + ldw r2, -4(ea) /* Instruction that caused exception */ + + /* + * Other exception handling code, if enabled, will be linked here. + * This includes unimplemted (multiply/divide) instruction support + * (a BSP generaton option), and a trap handler (that would typically + * be augmented with user-specific code). These are not linked in by + * default. + */ + + /* + * In the context of linker sections, "unknown" are all exceptions + * not handled by the built-in handlers above (interupt, and trap or + * unimplemented instruction decoding, if enabled). + * + * Advanced exception types can be serviced by registering a handler. + * To do so, enable the "Enable Instruction-related Exception API" HAL + * BSP setting. If this setting is disabled, this handler code will + * either break (if the debug core is present) or enter an infinite + * loop because we don't how how to handle the exception. + */ + .section .exceptions.unknown +#ifdef ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API + /* + * The C-based HAL routine alt_instruction_exception_entry() will + * attempt to service the exception by calling a user-registered + * exception handler using alt_instruction_exception_register(). + * If no handler was registered it will either break (if the + * debugger is present) or go into an infinite loop since the + * handling behavior is undefined; in that case we will not return here. + */ + + /* Load exception-causing address as first argument (r4) */ + addi r4, ea, -4 + + /* Call the instruction-exception entry */ + call alt_instruction_exception_entry + + /* + * If alt_instruction_exception_entry() returned, the exception was + * serviced by a user-registered routine. Its return code (now in r2) + * indicates whether to re-issue or skip the exception-causing + * instruction + * + * Return code was 0: Skip. The instruction after the exception is + * already stored in 72(sp). + */ + bne r2, r0, .Lexception_exit + + /* + * Otherwise, modify 72(sp) to re-issue the instruction that caused the + * exception. + */ + addi r15, ea, -4 /* instruction that caused exception */ + stw r15, 72(sp) + +#else /* ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API disabled */ + + /* + * We got here because an instruction-related exception occured, but the + * handler API was not compiled in. We do not presume to know how to + * handle it. If the debugger is present, break, otherwise hang. + * + * If you get here then one of the following could have happened: + * + * - An instruction-generated exception occured, and the processor + * does not have the extra exceptions feature enabled, or you + * have not registered a handler using + * alt_instruction_exception_register() + * + * Some examples of instruction-generated exceptions and why they + * might occur: + * + * - Your program could have been compiled for a full-featured + * Nios II core, but it is running on a smaller core, and + * instruction emulation has been disabled by defining + * ALT_NO_INSTRUCTION_EMULATION. + * + * You can work around the problem by re-enabling instruction + * emulation, or you can figure out why your program is being + * compiled for a system other than the one that it is running on. + * + * - Your program has executed a trap instruction, but has not + * implemented a handler for this instruction. + * + * - Your program has executed an illegal instruction (one which is + * not defined in the instruction set). + * + * - Your processor includes an MMU or MPU, and you have enabled it + * before registering an exception handler to service exceptions it + * generates. + * + * The problem could also be hardware related: + * - If your hardware is broken and is generating spurious interrupts + * (a peripheral which negates its interrupt output before its + * interrupt handler has been executed will cause spurious + * interrupts) + */ +#ifdef NIOS2_HAS_DEBUG_STUB + /* + * Either tell the user now (if there is a debugger attached) or go into + * the debug monitor which will loop until a debugger is attached. + */ + break +#else + /* + * If there is no debug stub then a BREAK will probably cause a reboot. + * An infinate loop will probably be more useful. + */ +0: + br 0b +#endif /* NIOS2_HAS_DEBUG_STUB */ + +#endif /* ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API */ + + .section .exceptions.exit.label +.Lexception_exit: + + .section .exceptions.exit, "xa" + + /* + * Restore the saved registers, so that all general purpose registers + * have been restored to their state at the time the interrupt occured. + */ + + ldw r5, 68(sp) + ldw ea, 72(sp) /* This becomes the PC once eret is executed */ + ldw ra, 0(sp) + + wrctl estatus, r5 + + ldw r1, 8(sp) + ldw r2, 12(sp) + ldw r3, 16(sp) + ldw r4, 20(sp) + ldw r5, 24(sp) + ldw r6, 28(sp) + ldw r7, 32(sp) + +#ifdef ALT_EXCEPTION_STACK +#ifdef ALT_STACK_CHECK + ldw et, %gprel(alt_exception_old_stack_limit)(gp) +#endif +#endif + + ldw r8, 36(sp) + ldw r9, 40(sp) + ldw r10, 44(sp) + ldw r11, 48(sp) + ldw r12, 52(sp) + ldw r13, 56(sp) + ldw r14, 60(sp) + ldw r15, 64(sp) + +#ifdef ALT_EXCEPTION_STACK + +#ifdef ALT_STACK_CHECK + stw et, %gprel(alt_stack_limit_value)(gp) + stw zero, %gprel(alt_exception_old_stack_limit)(gp) +#endif + + ldw sp, 76(sp) + +#else + addi sp, sp, 76 + +#endif + + /* + * Return to the interrupted instruction. + */ + + eret + +#ifdef ALT_STACK_CHECK + +.Lstack_overflow: + break 3 + +#endif + diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_exception_muldiv.S b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_exception_muldiv.S new file mode 100644 index 00000000..55617a6e --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_exception_muldiv.S @@ -0,0 +1,583 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003-2005 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + + /* + * This is the software multiply/divide handler for Nios2. + */ + + /* + * Provide a label which can be used to pull this file in. + */ + + .section .exceptions.start + .globl alt_exception_muldiv +alt_exception_muldiv: + + /* + * Pull in the entry/exit code. + */ + .globl alt_exception + + + .section .exceptions.soft, "xa" + + + /* INSTRUCTION EMULATION + * --------------------- + * + * Nios II processors generate exceptions for unimplemented instructions. + * The routines below emulate these instructions. Depending on the + * processor core, the only instructions that might need to be emulated + * are div, divu, mul, muli, mulxss, mulxsu, and mulxuu. + * + * The emulations match the instructions, except for the following + * limitations: + * + * 1) The emulation routines do not emulate the use of the exception + * temporary register (et) as a source operand because the exception + * handler already has modified it. + * + * 2) The routines do not emulate the use of the stack pointer (sp) or the + * exception return address register (ea) as a destination because + * modifying these registers crashes the exception handler or the + * interrupted routine. + * + * 3) To save code size, the routines do not emulate the use of the + * breakpoint registers (ba and bt) as operands. + * + * Detailed Design + * --------------- + * + * The emulation routines expect the contents of integer registers r0-r31 + * to be on the stack at addresses sp, 4(sp), 8(sp), ... 124(sp). The + * routines retrieve source operands from the stack and modify the + * destination register's value on the stack prior to the end of the + * exception handler. Then all registers except the destination register + * are restored to their previous values. + * + * The instruction that causes the exception is found at address -4(ea). + * The instruction's OP and OPX fields identify the operation to be + * performed. + * + * One instruction, muli, is an I-type instruction that is identified by + * an OP field of 0x24. + * + * muli AAAAA,BBBBB,IIIIIIIIIIIIIIII,-0x24- + * 27 22 6 0 <-- LSB of field + * + * The remaining emulated instructions are R-type and have an OP field + * of 0x3a. Their OPX fields identify them. + * + * R-type AAAAA,BBBBB,CCCCC,XXXXXX,NNNNN,-0x3a- + * 27 22 17 11 6 0 <-- LSB of field + * + * + */ + + + /* + * Split the instruction into its fields. We need 4*A, 4*B, and 4*C as + * offsets to the stack pointer for access to the stored register values. + */ + /* r2 = AAAAA,BBBBB,IIIIIIIIIIIIIIII,PPPPPP */ + roli r3, r2, 7 /* r3 = BBB,IIIIIIIIIIIIIIII,PPPPPP,AAAAA,BB */ + roli r4, r3, 3 /* r4 = IIIIIIIIIIIIIIII,PPPPPP,AAAAA,BBBBB */ + roli r6, r4, 2 /* r6 = IIIIIIIIIIIIII,PPPPPP,AAAAA,BBBBB,II */ + srai r4, r4, 16 /* r4 = (sign-extended) IMM16 */ + xori r6, r6, 0x42 /* r6 = CCC,XXXXXX,NNNNN,PPPPPP,AAAAA,bBBBB,cC */ + roli r7, r6, 5 /* r7 = XXXX,NNNNN,PPPPPP,AAAAA,bBBBB,cCCCC,XX */ + andi r5, r2, 0x3f /* r5 = 00000000000000000000000000,PPPPPP */ + xori r3, r3, 0x40 + andi r3, r3, 0x7c /* r3 = 0000000000000000000000000,aAAAA,00 */ + andi r6, r6, 0x7c /* r6 = 0000000000000000000000000,bBBBB,00 */ + andi r7, r7, 0x7c /* r7 = 0000000000000000000000000,cCCCC,00 */ + + /* Now either + * r5 = OP + * r3 = 4*(A^16) + * r4 = IMM16 (sign extended) + * r6 = 4*(B^16) + * r7 = 4*(C^16) + * or + * r5 = OP + */ + + + /* + * Save everything on the stack to make it easy for the emulation routines + * to retrieve the source register operands. The exception entry code has + * already saved some of this so we don't need to do it all again. + */ + + addi sp, sp, -60 + stw zero, 64(sp) /* Save zero on stack to avoid special case for r0. */ + /* Register at and r2-r15 have already been saved. */ + + stw r16, 0(sp) + stw r17, 4(sp) + stw r18, 8(sp) + stw r19, 12(sp) + stw r20, 16(sp) + stw r21, 20(sp) + stw r22, 24(sp) + stw r23, 28(sp) + /* et @ 32 - Has already been changed.*/ + /* bt @ 36 - Usually isn't an operand. */ + stw gp, 40(sp) + stw sp, 44(sp) + stw fp, 48(sp) + /* ea @ 52 - Don't bother to save - it's already been changed */ + /* ba @ 56 - Breakpoint register usually isn't an operand */ + /* ra @ 60 - Has already been saved */ + + + /* + * Prepare for either multiplication or division loop. + * They both loop 32 times. + */ + movi r14, 32 + + + /* + * Get the operands. + * + * It is necessary to check for muli because it uses an I-type instruction + * format, while the other instructions are have an R-type format. + */ + add r3, r3, sp /* r3 = address of A-operand. */ + ldw r3, 0(r3) /* r3 = A-operand. */ + movi r15, 0x24 /* muli opcode (I-type instruction format) */ + beq r5, r15, .Lmul_immed /* muli doesn't use the B register as a source */ + + add r6, r6, sp /* r6 = address of B-operand. */ + ldw r6, 0(r6) /* r6 = B-operand. */ + /* r4 = SSSSSSSSSSSSSSSS,-----IMM16------ */ + /* IMM16 not needed, align OPX portion */ + /* r4 = SSSSSSSSSSSSSSSS,CCCCC,-OPX--,00000 */ + srli r4, r4, 5 /* r4 = 00000,SSSSSSSSSSSSSSSS,CCCCC,-OPX-- */ + andi r4, r4, 0x3f /* r4 = 00000000000000000000000000,-OPX-- */ + + /* Now + * r5 = OP + * r3 = src1 + * r6 = src2 + * r4 = OPX (no longer can be muli) + * r7 = 4*(C^16) + * r14 = loop counter + */ + + /* ILLEGAL-INSTRUCTION EXCEPTION + * ----------------------------- + * + * This code is for Nios II cores that generate exceptions when attempting + * to execute illegal instructions. Nios II cores that support an + * illegal-instruction exception are identified by the presence of the + * macro definition NIOS2_HAS_ILLEGAL_INSTRUCTION_EXCEPTION in system.h . + * + * Remember that illegal instructions are different than unimplemented + * instructions. Illegal instructions are instruction encodings that + * have not been defined by the Nios II ISA. Unimplemented instructions + * are legal instructions that must be emulated by some Nios II cores. + * + * If we get here, all instructions except multiplies and divides + * are illegal. + * + * This code assumes that OP is not muli (because muli was tested above). + * All other multiplies and divides are legal. Anything else is illegal. + */ + + movi r8, 0x3a /* OP for R-type mul* and div* */ + bne r5, r8, .Lnot_muldiv + + /* r15 already is 0x24 */ /* OPX of divu */ + beq r4, r15, .Ldivide + + movi r15,0x27 /* OPX of mul */ + beq r4, r15, .Lmultiply + + movi r15,0x07 /* OPX of mulxuu */ + beq r4, r15, .Lmultiply + + movi r15,0x17 /* OPX of mulxsu */ + beq r4, r15, .Lmultiply + + movi r15,0x1f /* OPX of mulxss */ + beq r4, r15, .Lmultiply + + movi r15,0x25 /* OPX of div */ + bne r4, r15, .Lnot_muldiv + + + /* DIVISION + * + * Divide an unsigned dividend by an unsigned divisor using + * a shift-and-subtract algorithm. The example below shows + * 43 div 7 = 6 for 8-bit integers. This classic algorithm uses a + * single register to store both the dividend and the quotient, + * allowing both values to be shifted with a single instruction. + * + * remainder dividend:quotient + * --------- ----------------- + * initialize 00000000 00101011: + * shift 00000000 0101011:_ + * remainder >= divisor? no 00000000 0101011:0 + * shift 00000000 101011:0_ + * remainder >= divisor? no 00000000 101011:00 + * shift 00000001 01011:00_ + * remainder >= divisor? no 00000001 01011:000 + * shift 00000010 1011:000_ + * remainder >= divisor? no 00000010 1011:0000 + * shift 00000101 011:0000_ + * remainder >= divisor? no 00000101 011:00000 + * shift 00001010 11:00000_ + * remainder >= divisor? yes 00001010 11:000001 + * remainder -= divisor - 00000111 + * ---------- + * 00000011 11:000001 + * shift 00000111 1:000001_ + * remainder >= divisor? yes 00000111 1:0000011 + * remainder -= divisor - 00000111 + * ---------- + * 00000000 1:0000011 + * shift 00000001 :0000011_ + * remainder >= divisor? no 00000001 :00000110 + * + * The quotient is 00000110. + */ + +.Ldivide: + /* + * Prepare for division by assuming the result + * is unsigned, and storing its "sign" as 0. + */ + movi r17, 0 + + + /* Which division opcode? */ + xori r15, r4, 0x25 /* OPX of div */ + bne r15, zero, .Lunsigned_division + + + /* + * OPX is div. Determine and store the sign of the quotient. + * Then take the absolute value of both operands. + */ + xor r17, r3, r6 /* MSB contains sign of quotient */ + bge r3, zero, 0f + sub r3, zero, r3 /* -r3 */ +0: + bge r6, zero, 0f + sub r6, zero, r6 /* -r6 */ +0: + + +.Lunsigned_division: + /* Initialize the unsigned-division loop. */ + movi r13, 0 /* remainder = 0 */ + + /* Now + * r3 = dividend : quotient + * r4 = 0x25 for div, 0x24 for divu + * r6 = divisor + * r13 = remainder + * r14 = loop counter (already initialized to 32) + * r17 = MSB contains sign of quotient + */ + + + /* + * for (count = 32; count > 0; --count) + * { + */ +.Ldivide_loop: + + /* + * Division: + * + * (remainder:dividend:quotient) <<= 1; + */ + slli r13, r13, 1 + cmplt r15, r3, zero /* r15 = MSB of r3 */ + or r13, r13, r15 + slli r3, r3, 1 + + + /* + * if (remainder >= divisor) + * { + * set LSB of quotient + * remainder -= divisor; + * } + */ + bltu r13, r6, .Ldiv_skip + ori r3, r3, 1 + sub r13, r13, r6 +.Ldiv_skip: + + /* + * } + */ + subi r14, r14, 1 + bne r14, zero, .Ldivide_loop + + mov r9, r3 + + + /* Now + * r9 = quotient + * r4 = 0x25 for div, 0x24 for divu + * r7 = 4*(C^16) + * r17 = MSB contains sign of quotient + */ + + + /* + * Conditionally negate signed quotient. If quotient is unsigned, + * the sign already is initialized to 0. + */ + bge r17, zero, .Lstore_result + sub r9, zero, r9 /* -r9 */ + + br .Lstore_result + + + + + /* MULTIPLICATION + * + * A "product" is the number that one gets by summing a "multiplicand" + * several times. The "multiplier" specifies the number of copies of the + * multiplicand that are summed. + * + * Actual multiplication algorithms don't use repeated addition, however. + * Shift-and-add algorithms get the same answer as repeated addition, and + * they are faster. To compute the lower half of a product (pppp below) + * one shifts the product left before adding in each of the partial products + * (a * mmmm) through (d * mmmm). + * + * To compute the upper half of a product (PPPP below), one adds in the + * partial products (d * mmmm) through (a * mmmm), each time following the + * add by a right shift of the product. + * + * mmmm + * * abcd + * ------ + * #### = d * mmmm + * #### = c * mmmm + * #### = b * mmmm + * #### = a * mmmm + * -------- + * PPPPpppp + * + * The example above shows 4 partial products. Computing actual Nios II + * products requires 32 partials. + * + * It is possible to compute the result of mulxsu from the result of mulxuu + * because the only difference between the results of these two opcodes is + * the value of the partial product associated with the sign bit of rA. + * + * mulxsu = mulxuu - ((rA < 0) ? rB : 0); + * + * It is possible to compute the result of mulxss from the result of mulxsu + * because the only difference between the results of these two opcodes is + * the value of the partial product associated with the sign bit of rB. + * + * mulxss = mulxsu - ((rB < 0) ? rA : 0); + * + */ + +.Lmul_immed: + /* Opcode is muli. Change it into mul for remainder of algorithm. */ + mov r7, r6 /* Field B is dest register, not field C. */ + mov r6, r4 /* Field IMM16 is src2, not field B. */ + movi r4, 0x27 /* OPX of mul is 0x27 */ + +.Lmultiply: + /* Initialize the multiplication loop. */ + movi r9, 0 /* mul_product = 0 */ + movi r10, 0 /* mulxuu_product = 0 */ + mov r11, r6 /* save original multiplier for mulxsu and mulxss */ + mov r12, r6 /* mulxuu_multiplier (will be shifted) */ + movi r16, 1 /* used to create "rori B,A,1" from "ror B,A,r16" */ + + /* Now + * r3 = multiplicand + * r6 = mul_multiplier + * r7 = 4 * dest_register (used later as offset to sp) + * r9 = mul_product + * r10 = mulxuu_product + * r11 = original multiplier + * r12 = mulxuu_multiplier + * r14 = loop counter (already initialized) + * r15 = temp + * r16 = 1 + */ + + + /* + * for (count = 32; count > 0; --count) + * { + */ +.Lmultiply_loop: + + /* + * mul_product <<= 1; + * lsb = multiplier & 1; + */ + slli r9, r9, 1 + andi r15, r12, 1 + + /* + * if (lsb == 1) + * { + * mulxuu_product += multiplicand; + * } + */ + beq r15, zero, .Lmulx_skip + add r10, r10, r3 + cmpltu r15, r10, r3 /* Save the carry from the MSB of mulxuu_product. */ + ror r15, r15, r16 /* r15 = 0x80000000 on carry, or else 0x00000000 */ +.Lmulx_skip: + + /* + * if (MSB of mul_multiplier == 1) + * { + * mul_product += multiplicand; + * } + */ + bge r6, zero, .Lmul_skip + add r9, r9, r3 +.Lmul_skip: + + /* + * mulxuu_product >>= 1; logical shift + * mul_multiplier <<= 1; done with MSB + * mulx_multiplier >>= 1; done with LSB + */ + srli r10, r10, 1 + or r10, r10, r15 /* OR in the saved carry bit. */ + slli r6, r6, 1 + srli r12, r12, 1 + + + /* + * } + */ + subi r14, r14, 1 + bne r14, zero, .Lmultiply_loop + + + /* + * Multiply emulation loop done. + */ + + /* Now + * r3 = multiplicand + * r4 = OPX + * r7 = 4 * dest_register (used later as offset to sp) + * r9 = mul_product + * r10 = mulxuu_product + * r11 = original multiplier + * r15 = temp + */ + + + /* + * Select/compute the result based on OPX. + */ + + + /* OPX == mul? Then store. */ + xori r15, r4, 0x27 + beq r15, zero, .Lstore_result + + /* It's one of the mulx.. opcodes. Move over the result. */ + mov r9, r10 + + /* OPX == mulxuu? Then store. */ + xori r15, r4, 0x07 + beq r15, zero, .Lstore_result + + /* Compute mulxsu + * + * mulxsu = mulxuu - ((rA < 0) ? rB : 0); + */ + bge r3, zero, .Lmulxsu_skip + sub r9, r9, r11 +.Lmulxsu_skip: + + /* OPX == mulxsu? Then store. */ + xori r15, r4, 0x17 + beq r15, zero, .Lstore_result + + /* Compute mulxss + * + * mulxss = mulxsu - ((rB < 0) ? rA : 0); + */ + bge r11, zero, .Lmulxss_skip + sub r9, r9, r3 +.Lmulxss_skip: + /* At this point, assume that OPX is mulxss, so store */ + + +.Lstore_result: + add r7, r7, sp + stw r9, 0(r7) + + ldw r16, 0(sp) + ldw r17, 4(sp) + ldw r18, 8(sp) + ldw r19, 12(sp) + ldw r20, 16(sp) + ldw r21, 20(sp) + ldw r22, 24(sp) + ldw r23, 28(sp) + + /* bt @ 32 - Breakpoint register usually isn't an operand. */ + /* et @ 36 - Don't corrupt et. */ + /* gp @ 40 - Don't corrupt gp. */ + /* sp @ 44 - Don't corrupt sp. */ + ldw fp, 48(sp) + /* ea @ 52 - Don't corrupt ea. */ + /* ba @ 56 - Breakpoint register usually isn't an operand. */ + + addi sp, sp, 60 + + br .Lexception_exit + + +.Lnot_muldiv: + + addi sp, sp, 60 + + + .section .exceptions.exit.label +.Lexception_exit: + diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_exception_trap.S b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_exception_trap.S new file mode 100644 index 00000000..60a3d409 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_exception_trap.S @@ -0,0 +1,81 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003-2005 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + + /* + * This is the trap exception handler for Nios2. + */ + + /* + * Provide a label which can be used to pull this file in. + */ + + .section .exceptions.start + .globl alt_exception_trap +alt_exception_trap: + + /* + * Pull in the entry/exit code. + */ + .globl alt_exception + + .section .exceptions.soft, "xa" + +.Ltrap_handler: + + /* + * Did a trap instruction cause the exception? + * + * The instruction which the exception occurred on has been loaded + * into r2 by code in alt_exception_entry.S + * + */ + + movhi r3,0x003b /* upper half of trap opcode */ + ori r3,r3,0x683a /* lower half of trap opcode */ + bne r2,r3,.Lnot_trap + + /* + * There is no trap handler defined here, and so executing a trap + * instruction causes a software break. If you provide a trap handler, + * then you must replace the break instruction below with your handler. + * Your handler must preserve ea and the usual callee saved registers. + */ + + break + + br .Lexception_exit + +.Lnot_trap: + + + .section .exceptions.exit.label +.Lexception_exit: + + diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_execve.c b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_execve.c new file mode 100644 index 00000000..27b99cff --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_execve.c @@ -0,0 +1,55 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include "sys/alt_errno.h" +#include "sys/alt_warning.h" +#include "os/alt_syscall.h" + +/* + * execve() is used by newlib to launch new processes. This is unsupported in + * the HAL environment. However a "do-nothing" implementation is still + * provied for newlib compatability. + * + * ALT_EXECVE is mapped onto the execve() system call in alt_syscall.h + */ + +int ALT_EXECVE (char *name, char ** argv, char** env) +{ + /* Generate a link time warning, should this function ever be called. */ + + ALT_STUB_WARNING(execve); + + /* Indicate an error */ + + ALT_ERRNO = ENOSYS; + return -1; +} diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_exit.c b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_exit.c new file mode 100644 index 00000000..971b35ec --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_exit.c @@ -0,0 +1,71 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include "sys/alt_irq.h" +#include "sys/alt_sim.h" +#include "os/alt_hooks.h" +#include "os/alt_syscall.h" + +#include "alt_types.h" +#include "sys/alt_log_printf.h" +/* + * _exit() is called by exit() in order to terminate the current process. + * Typically this is called when main() completes. It should never return. + * Since there is nowhere to go once this process completes, this + * implementation simply blocks forever. + * + * Note that interrupts are not disabled so that execution outside of this + * thread is allowed to continue. + * + * ALT_EXIT is mapped onto the _exit() system call in alt_syscall.h + */ + +void ALT_EXIT (int exit_code) +{ + /* ALT_LOG - please see HAL/inc/alt_log_printf.h for details */ + ALT_LOG_PRINT_BOOT("[alt_exit.c] Entering _exit() function.\r\n"); + ALT_LOG_PRINT_BOOT("[alt_exit.c] Exit code from main was %d.\r\n",exit_code); + /* Stop all other threads */ + + ALT_LOG_PRINT_BOOT("[alt_exit.c] Calling ALT_OS_STOP().\r\n"); + ALT_OS_STOP(); + + /* Provide notification to the simulator that we've stopped */ + + ALT_LOG_PRINT_BOOT("[alt_exit.c] Calling ALT_SIM_HALT().\r\n"); + ALT_SIM_HALT(exit_code); + + /* spin forever, since there's no where to go back to */ + + ALT_LOG_PRINT_BOOT("[alt_exit.c] Spinning forever.\r\n"); + while (1); +} diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_fcntl.c b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_fcntl.c new file mode 100644 index 00000000..69c15445 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_fcntl.c @@ -0,0 +1,101 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include +#include + +#include +#include + +#include "sys/alt_errno.h" +#include "priv/alt_file.h" +#include "alt_types.h" +#include "os/alt_syscall.h" + +#define ALT_FCNTL_FLAGS_MASK ((alt_u32) (O_APPEND | O_NONBLOCK)) + +/* + * fcntl() is a limited implementation of the standard fcntl() system call. + * It can be used to change the state of the flags associated with an open + * file descriptor. Normally these flags are set during the call to + * open(). It is anticipated that the main use of this function will be to + * change the state of a device from blocking to non-blocking (where this is + * supported). + * + * The input argument "fd" is the file descriptor to be manipulated. "cmd" + * is the command to execute. This can be either F_GETFL (return the + * current value of the flags) or F_SETFL (set the value of the flags). + * + * If "cmd" is F_SETFL then the argument "arg" is the new value of flags, + * otherwise "arg" is ignored. Only the flags: O_APPEND and O_NONBLOCK + * can be updated by a call to fcntl(). All other flags remain + * unchanged. + * + * ALT_FCNTL is mapped onto the fcntl() system call in alt_syscall.h + */ + +int ALT_FCNTL (int file, int cmd, ...) +{ + alt_fd* fd; + long flags; + va_list argp; + + /* + * A common error case is that when the file descriptor was created, the call + * to open() failed resulting in a negative file descriptor. This is trapped + * below so that we don't try and process an invalid file descriptor. + */ + + fd = (file < 0) ? NULL : &alt_fd_list[file]; + + if (fd) + { + switch (cmd) + { + case F_GETFL: + return fd->fd_flags & ~((alt_u32) ALT_FD_FLAGS_MASK); + case F_SETFL: + va_start(argp, cmd); + flags = va_arg(argp, long); + fd->fd_flags &= ~ALT_FCNTL_FLAGS_MASK; + fd->fd_flags |= (flags & ALT_FCNTL_FLAGS_MASK); + va_end(argp); + return 0; + default: + ALT_ERRNO = EINVAL; + return -1; + } + } + + ALT_ERRNO = EBADFD; + return -1; +} diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_fd_lock.c b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_fd_lock.c new file mode 100644 index 00000000..0e2a85d6 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_fd_lock.c @@ -0,0 +1,75 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include + +#include "priv/alt_file.h" + +/* + * alt_fd_lock() is called as a consequence of an ioctl call to gain exclusive + * access to a device, i.e.: + * + * ioctl (fd, TIOCEXCL, NULL); + * + * If there are no other open file descriptors which reference the same + * device, then alt_fd_lock() will grant the lock. Further calls to open() + * for this device will fail until the lock is released. + * + * This is done by calling close() for this file descriptor, or by calling: + * + * ioctl (fd, TIOCNXCL, NULL); + * + * The return value is zero for success, or negative in the case of failure. + */ + +int alt_fd_lock (alt_fd* fd) +{ + int i; + int rc = 0; + + ALT_SEM_PEND(alt_fd_list_lock, 0); + + for (i = 0; i < alt_max_fd; i++) + { + if ((&alt_fd_list[i] != fd) && (alt_fd_list[i].dev == fd->dev)) + { + rc = -EACCES; + goto alt_fd_lock_exit; + } + } + fd->fd_flags |= ALT_FD_EXCL; + + alt_fd_lock_exit: + + ALT_SEM_POST(alt_fd_list_lock); + return rc; +} diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_fd_unlock.c b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_fd_unlock.c new file mode 100644 index 00000000..fb700dc5 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_fd_unlock.c @@ -0,0 +1,56 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include + +#include "priv/alt_file.h" + +/* + * alt_fd_unlock() is the inverse of alt_fd_lock(). It is called as a + * consequence of a TIOCNXCL ioctl request, e.g: + * + * ioctl (fd, TIOCNXCL, NULL); + * + * It enables multiple file descriptors to exist for the same device. This + * is normally the case, but it may have been disabled by a previous call to + * alt_fd_lock(). + * + * Return zero on sucess, and a negative value on failure. + * + * The current implementation always succeeds. + */ + +int alt_fd_unlock (alt_fd* fd) +{ + fd->fd_flags &= ~ALT_FD_EXCL; + return 0; +} diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_find_dev.c b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_find_dev.c new file mode 100644 index 00000000..37aefa4c --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_find_dev.c @@ -0,0 +1,88 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include +#include +#include + +#include "sys/alt_dev.h" +#include "priv/alt_file.h" + +#include "alt_types.h" + +/* + * alt_find_dev() is used by open() in order to locate a previously registered + * device with the name "name". The input argument "llist" is a pointer to the + * head of the device list to search. + * + * The return value is a pointer to the matching device, or NULL if there is + * no match. + * + * "name" must be an exact match for the devices registered name for a match to + * be found. + */ + +alt_dev* alt_find_dev(const char* name, alt_llist* llist) +{ + alt_dev* next = (alt_dev*) llist->next; + alt_32 len; + + len = strlen(name) + 1; + + /* + * Check each list entry in turn, until a match is found, or we reach the + * end of the list (i.e. next winds up pointing back to the list head). + */ + + while (next != (alt_dev*) llist) + { + + /* + * memcmp() is used here rather than strcmp() in order to reduce the size + * of the executable. + */ + + if (!memcmp (next->name, name, len)) + { + /* match found */ + + return next; + } + next = (alt_dev*) next->llist.next; + } + + /* No match found */ + + return NULL; +} + + diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_find_file.c b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_find_file.c new file mode 100644 index 00000000..2d97ec27 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_find_file.c @@ -0,0 +1,89 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include +#include +#include + +#include "sys/alt_dev.h" +#include "priv/alt_file.h" + +#include "alt_types.h" + +/* + * alt_find_file() is used by open() in order to locate a previously registered + * filesystem that owns that mount point that contains the file named "name". + * + * The return value is a pointer to the matching filesystem, or NULL if there is + * no match. + * + * A match is considered to have been found if the filesystem name followed by + * either '/' or '\0' is the prefix of the filename. For example the filename: + * "/myfilesystem/junk.txt" would match: "/myfilesystem", but not: "/myfile". + */ + +alt_dev* alt_find_file (const char* name) +{ + alt_dev* next = (alt_dev*) alt_fs_list.next; + + alt_32 len; + + /* + * Check each list entry in turn, until a match is found, or we reach the + * end of the list (i.e. next winds up pointing back to the list head). + */ + + while (next != (alt_dev*) &alt_fs_list) + { + len = strlen(next->name); + + if (next->name[len-1] == '/') + { + len -= 1; + } + + if (((name[len] == '/') || (name[len] == '\0')) && + !memcmp (next->name, name, len)) + { + /* match found */ + + return next; + } + next = (alt_dev*) next->llist.next; + } + + /* No match found */ + + return NULL; +} + + diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_flash_dev.c b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_flash_dev.c new file mode 100644 index 00000000..213f7214 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_flash_dev.c @@ -0,0 +1,69 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/****************************************************************************** +* * +* Alt_flash.c - Functions to register a flash device to the "generic" flash * +* interface * +* * +* Author PRR * +* * +******************************************************************************/ + +#include +#include "sys/alt_llist.h" +#include "sys/alt_flash_dev.h" +#include "priv/alt_file.h" + +ALT_LLIST_HEAD(alt_flash_dev_list); + +alt_flash_fd* alt_flash_open_dev(const char* name) +{ + alt_flash_dev* dev = (alt_flash_dev*)alt_find_dev(name, &alt_flash_dev_list); + + if ((dev) && dev->open) + { + return dev->open(dev, name); + } + + return dev; +} + +void alt_flash_close_dev(alt_flash_fd* fd) +{ + if (fd && fd->close) + { + fd->close(fd); + } + return; +} + diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_fork.c b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_fork.c new file mode 100644 index 00000000..ce74df00 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_fork.c @@ -0,0 +1,57 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include "sys/alt_warning.h" +#include "sys/alt_errno.h" +#include "os/alt_syscall.h" + +/* + * The fork() system call is used by newlib to create a duplicate copy of the + * curent process. This is unsupported in the HAL environment. However a + * "do-nothing" implementation is still provied for newlib compatability. + * + * ALT_FORK is mapped onto the fork() system call in alt_syscall.h + */ + +int ALT_FORK (void) +{ + /* Generate a link time warning, should this function ever be called. */ + + ALT_STUB_WARNING(fork); + + /* Indicate an error */ + + ALT_ERRNO = ENOSYS; + return -1; +} + + diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_fs_reg.c b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_fs_reg.c new file mode 100644 index 00000000..13437a11 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_fs_reg.c @@ -0,0 +1,75 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include + +#include "sys/alt_dev.h" +#include "priv/alt_file.h" + +/* + * The alt_fs_reg() function is used to register a file system. Once registered + * a device can be accessed using the standard posix calls: open(), read(), + * write() etc. + * + * System behaviour is undefined in the event that a file system is registered + * with a name that conflicts with an existing device or file system. + * + * alt_fs_reg() is not thread safe in the sense that there should be no other + * thread using the file system list at the time that alt_dev_reg() is called. In + * practice this means that alt_fs_reg() should only be called while operating + * in a single threaded mode. The expectation is that it will only be called + * by the file system initilisation functions invoked by alt_sys_init(), which in + * turn should only be called by the single threaded C startup code. + * + * A return value of zero indicates success. A negative return value indicates + * failure. + */ + +int alt_fs_reg (alt_dev* dev) +{ + /* + * check that the device has a name. + */ + + if (!dev->name) + { + return -ENODEV; + } + + /* + * register the file system. + */ + + alt_llist_insert(&alt_fs_list, &dev->llist); + + return 0; +} diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_fstat.c b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_fstat.c new file mode 100644 index 00000000..af5d527a --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_fstat.c @@ -0,0 +1,128 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include +#include + +#include "sys/alt_dev.h" +#include "sys/alt_warning.h" +#include "sys/alt_errno.h" +#include "priv/alt_file.h" +#include "os/alt_syscall.h" + +/* + * The fstat() system call is used to obtain information about the capabilities + * of an open file descriptor. By default file descriptors are marked as + * being character devices. If a device or file system wishes to advertise + * alternative capabilities then they can register an fstat() function within + * their associated alt_dev structure. This will be called to fill in the + * entries in the imput "st" structure. + * + * This function is provided for compatability with newlib. + * + * ALT_FSTAT is mapped onto the fstat() system call in alt_syscall.h + */ + +#ifdef ALT_USE_DIRECT_DRIVERS + +#include "system.h" + +/* + * Provide minimal version that just describes all file descriptors + * as character devices for provided stdio devices. + */ +int ALT_FSTAT (int file, struct stat *st) +{ + switch (file) { +#ifdef ALT_STDIN_PRESENT + case 0: /* stdin file descriptor */ +#endif /* ALT_STDIN_PRESENT */ +#ifdef ALT_STDOUT_PRESENT + case 1: /* stdout file descriptor */ +#endif /* ALT_STDOUT_PRESENT */ +#ifdef ALT_STDERR_PRESENT + case 2: /* stderr file descriptor */ +#endif /* ALT_STDERR_PRESENT */ + st->st_mode = _IFCHR; + return 0; + default: + return -1; + } + +#if !defined(ALT_STDIN_PRESENT) && !defined(ALT_STDOUT_PRESENT) && !defined(ALT_STDERR_PRESENT) + /* Generate a link time warning, should this function ever be called. */ + ALT_STUB_WARNING(fstat); +#endif +} + +#else /* !ALT_USE_DIRECT_DRIVERS */ + +int ALT_FSTAT (int file, struct stat *st) +{ + alt_fd* fd; + + /* + * A common error case is that when the file descriptor was created, the call + * to open() failed resulting in a negative file descriptor. This is trapped + * below so that we don't try and process an invalid file descriptor. + */ + + fd = (file < 0) ? NULL : &alt_fd_list[file]; + + if (fd) + { + /* Call the drivers fstat() function to fill out the "st" structure. */ + + if (fd->dev->fstat) + { + return fd->dev->fstat(fd, st); + } + + /* + * If no function is provided, mark the fd as belonging to a character + * device. + */ + + else + { + st->st_mode = _IFCHR; + return 0; + } + } + else + { + ALT_ERRNO = EBADFD; + return -1; + } +} + +#endif /* ALT_USE_DIRECT_DRIVERS */ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_get_fd.c b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_get_fd.c new file mode 100644 index 00000000..db17b2cb --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_get_fd.c @@ -0,0 +1,105 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include +#include +#include + +#include "sys/alt_dev.h" +#include "priv/alt_file.h" + +#include "alt_types.h" + +#include "system.h" + +/* + * alt_get_fd() is called to allocate a new file descriptor from the file + * descriptor pool. If a file descriptor is succesfully allocated, it is + * configured to refer to device "dev". + * + * The return value is the index of the file descriptor structure (i.e. + * the offset of the file descriptor within the file descriptor array). A + * negative value indicates failure. + */ + +int alt_get_fd (alt_dev* dev) +{ + alt_32 i; + int rc = -EMFILE; + + /* + * Take the alt_fd_list_lock semaphore in order to avoid races when + * accessing the file descriptor pool. + */ + + ALT_SEM_PEND(alt_fd_list_lock, 0); + + /* + * Search through the list of file descriptors, and allocate the first + * free descriptor that's found. + * + * If a free descriptor is found, then the value of "alt_max_fd" is + * updated accordingly. "alt_max_fd" is a 'highwater mark' which + * indicates the highest file descriptor ever allocated. This is used to + * improve efficency when searching the file descriptor list, and + * therefore reduce contention on the alt_fd_list_lock semaphore. + */ + + for (i = 0; i < ALT_MAX_FD; i++) + { + if (!alt_fd_list[i].dev) + { + alt_fd_list[i].dev = dev; + if (i > alt_max_fd) + { + alt_max_fd = i; + } + rc = i; + goto alt_get_fd_exit; + } + } + + alt_get_fd_exit: + + /* + * Release the alt_fd_list_lock semaphore now that we are done with the + * file descriptor pool. + */ + + ALT_SEM_POST(alt_fd_list_lock); + + return rc; +} + + + + diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_getchar.c b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_getchar.c new file mode 100644 index 00000000..a8f50d5f --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_getchar.c @@ -0,0 +1,61 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include + +#ifdef ALT_USE_DIRECT_DRIVERS +#include "system.h" +#include "sys/alt_driver.h" +#include "sys/alt_stdio.h" +#include "priv/alt_file.h" +#include "unistd.h" +#endif + +/* + * Uses the ALT_DRIVER_READ() macro to call directly to driver if available. + * Otherwise, uses newlib provided getchar() routine. + */ +int +alt_getchar(void) +{ +#ifdef ALT_USE_DIRECT_DRIVERS + ALT_DRIVER_READ_EXTERNS(ALT_STDIN_DEV); + char c; + + if (ALT_DRIVER_READ(ALT_STDIN_DEV, &c, 1, alt_fd_list[STDIN_FILENO].fd_flags) <= 0) { + return -1; + } + return c; +#else + return getchar(); +#endif +} diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_getpid.c b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_getpid.c new file mode 100644 index 00000000..2228c7e9 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_getpid.c @@ -0,0 +1,47 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include "os/alt_syscall.h" + +/* + * The getpid() system call is used by newlib to obtain the current process + * id. Since there is only ever a single process in the HAL environment, + * this just returns a constant. + * + * ALT_GETPID is mapped onto the getpid() system call in alt_syscall.h + */ + +int ALT_GETPID (void) +{ + return 0; +} + diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_gettod.c b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_gettod.c new file mode 100644 index 00000000..ed86cba6 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_gettod.c @@ -0,0 +1,125 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include +#include +#include + +#include "sys/alt_alarm.h" +#include "alt_types.h" +#include "os/alt_syscall.h" + +/* + * Macro defining the number of micoseconds in a second. + */ + +#define ALT_US (1000000) + +/* + * "alt_timezone" and "alt_resettime" are the values of the the reset time and + * time zone set through the last call to settimeofday(). By default they are + * zero initialised. + */ + +struct timezone alt_timezone = {0, 0}; +struct timeval alt_resettime = {0, 0}; + +/* + * gettimeofday() can be called to obtain a time structure which indicates the + * current "wall clock" time. This is calculated using the elapsed number of + * system clock ticks, and the value of "alt_resettime" and "alt_timezone" set + * through the last call to settimeofday(). + * + * Warning: if this function is called concurrently with a call to + * settimeofday(), the value returned by gettimeofday() will be unreliable. + * + * ALT_GETTIMEOFDAY is mapped onto the gettimeofday() system call in + * alt_syscall.h + */ + + +#if defined (__GNUC__) && (__GNUC__ >= 4) +int ALT_GETTIMEOFDAY (struct timeval *ptimeval, void *ptimezone_vptr) +{ + struct timezone *ptimezone = (struct timezone*)ptimezone_vptr; +#else +int ALT_GETTIMEOFDAY (struct timeval *ptimeval, struct timezone *ptimezone) +{ +#endif + + alt_u32 nticks = alt_nticks (); + alt_u32 tick_rate = alt_ticks_per_second (); + + /* + * Check to see if the system clock is running. This is indicated by a + * non-zero system clock rate. If the system clock is not running, an error + * is generated and the contents of "ptimeval" and "ptimezone" are not + * updated. + */ + + if (tick_rate) + { + ptimeval->tv_sec = alt_resettime.tv_sec + nticks/tick_rate; + ptimeval->tv_usec = alt_resettime.tv_usec + + (alt_u32)(((alt_u64)nticks*(ALT_US/tick_rate))%ALT_US); + + while(ptimeval->tv_usec < 0) { + if (ptimeval->tv_sec <= 0) + { + ptimeval->tv_sec = 0; + ptimeval->tv_usec = 0; + break; + } + else + { + ptimeval->tv_sec--; + ptimeval->tv_usec += ALT_US; + } + } + + while(ptimeval->tv_usec >= ALT_US) { + ptimeval->tv_sec++; + ptimeval->tv_usec -= ALT_US; + } + + if (ptimezone) + { + ptimezone->tz_minuteswest = alt_timezone.tz_minuteswest; + ptimezone->tz_dsttime = alt_timezone.tz_dsttime; + } + + return 0; + } + + return -ENOTSUP; +} + diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_gmon.c b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_gmon.c new file mode 100644 index 00000000..6add9f16 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_gmon.c @@ -0,0 +1,272 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003-2005 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include +#include +#include + +#include "priv/nios2_gmon_data.h" + +#include "sys/alt_irq.h" +#include "sys/alt_alarm.h" + + +/* Macros */ + +/* How large should the bins be which we use to generate the histogram */ +#define PCSAMPLE_BYTES_PER_BUCKET 32 + +#define NIOS2_READ_EA(dest) __asm__ ("mov %0, ea" : "=r" (dest)) + +/* The compiler inserts calls to mcount() at the start of + * every function call. The structure mcount_fn_arc records t + * he return address of the function called (in from_pc) + * and the return address of the mcount function + * (in self_pc). The number of times this arc is executed is + * recorded in the field count. + */ +struct mcount_fn_arc +{ + struct mcount_fn_arc * next; + void * from_pc; + unsigned int count; +}; + +/* We need to maintain a list of pointers to the heads of each adjacency + * list so that we can find them when writing out the gmon.out file. Since + * we don't know at the start of program execution how many functions will + * be called we use a list structure to do this. + */ +struct mcount_fn_entry +{ + struct mcount_fn_entry * next; + void * self_pc; + struct mcount_fn_arc * arc_head; +}; + +/* function prototypes */ + +void __mcount_record(void * self_pc, void * from_pc, struct mcount_fn_entry * fn_entry, struct mcount_fn_entry * * fn_head) __attribute__ ((no_instrument_function)); + +static __inline__ void * mcount_allocate(unsigned int size) __attribute__ ((no_instrument_function)); +static int nios2_pcsample_init(void) __attribute__ ((no_instrument_function)); +static alt_u32 nios2_pcsample(void* alarm) __attribute__ ((no_instrument_function)); + +/* global variables */ + +/* stext and etext are defined in the linker script */ +extern char stext[]; +extern char etext[]; + +/* Is the PC sampling stuff enabled yet? */ +static int pcsample_need_init = 1; + +#define HASH_BUCKETS 64 /* Must be a power of 2 */ + +/* This points to the list of adjacency list pointers. */ +struct mcount_fn_entry * __mcount_fn_head[HASH_BUCKETS]; + +/* pointer to the in-memory buffer containing the histogram */ +static unsigned short* s_pcsamples = 0; + +/* the address of the start and end of text section */ +static const unsigned int s_low_pc = (unsigned int)stext; +static const unsigned int s_high_pc = (unsigned int)etext; + +/* the alarm structure to register for pc sampling */ +static alt_alarm s_nios2_pcsample_alarm; + +unsigned int alt_gmon_data[GMON_DATA_SIZE] = +{ + 0x6e6f6d67, /* "gmon" */ + GMON_DATA_SIZE, + 0, + (unsigned int)stext, + (unsigned int)etext, + PCSAMPLE_BYTES_PER_BUCKET, + 0, + (unsigned int)__mcount_fn_head, + (unsigned int)(__mcount_fn_head + HASH_BUCKETS) +}; + +/* This holds the current slab of memory we're allocating out of */ +static char * mcount_slab_ptr = 0; +static int mcount_slab_size = 0; + +#define MCOUNT_SLAB_INCREMENT 1020 + + +/* + * We can't use malloc to allocate memory because that's too complicated, and + * can't be called at interrupt time. Use the lower level allocator instead + * because that's interrupt safe (and because we never free anything). + * + * For speed, we allocate a block of data at once. + */ +static __inline__ void * mcount_allocate(unsigned int size) +{ + void * data; + + if (size > mcount_slab_size) + { + mcount_slab_ptr = sbrk(MCOUNT_SLAB_INCREMENT); + mcount_slab_size = MCOUNT_SLAB_INCREMENT; + } + + data = mcount_slab_ptr; + mcount_slab_ptr += size; + mcount_slab_size -= size; + + return data; +} + + +/* + * Add the arc with the values of frompc and topc given to the graph. + * This function might be called at interrupt time so must be able to + * cope with reentrancy. + * + * The fast case, where we have already allocated a function arc, has been + * handled by the assmebler code. + */ +void __mcount_record(void * self_pc, void * from_pc, struct mcount_fn_entry * fn_entry, struct mcount_fn_entry * * fn_head) +{ + alt_irq_context context; + struct mcount_fn_arc * arc_entry; + + /* Keep trying to start up the PC sampler until it is running. + * (It can't start until the timer is going). + */ + if (pcsample_need_init) + { + pcsample_need_init = 0; + pcsample_need_init = nios2_pcsample_init(); + } + + /* + * We must disable interrupts around the allocation and the list update to + * prevent corruption if the instrumented function is re-entrant. + * + * It's safe for the code above to be stepping through the chain and be + * interrupted by this code modifying it - there is an edge case which will + * leave two copies of the same arc on the list (both with count=1), but + * this is dealt with on the host. + */ + context = alt_irq_disable_all(); + + if (fn_entry == NULL) + { + /* Add it to the list of functions we must output later. */ + fn_entry = (struct mcount_fn_entry *)mcount_allocate(sizeof(struct mcount_fn_entry)); + + fn_entry->self_pc = self_pc; + fn_entry->arc_head = NULL; + + fn_entry->next = *fn_head; + *fn_head = fn_entry; + } + + /* We will need a new list entry - if there was a list entry before + * then the assembler code would have handled it. */ + arc_entry = (struct mcount_fn_arc *)mcount_allocate(sizeof(struct mcount_fn_arc)); + + arc_entry->from_pc = from_pc; + arc_entry->count = 1; + + arc_entry->next = fn_entry->arc_head; + fn_entry->arc_head = arc_entry; + + alt_irq_enable_all(context); +} + + +/* + * nios2_pcsample_init starts profiling. + * It is called the first time mcount is called, and on subsequent calls to + * mcount until it returns zero. It initializes the pc histogram and turns on + * timer driven pc sampling. + */ +static int nios2_pcsample_init(void) +{ + unsigned int pcsamples_size; + + /* We sample the PC every tick */ + unsigned int prof_rate = alt_ticks_per_second(); + if (prof_rate == 0) + return 1; + + /* allocate the histogram buffer s_pcsamples */ + pcsamples_size = (s_high_pc - s_low_pc)/PCSAMPLE_BYTES_PER_BUCKET; + s_pcsamples = (unsigned short*)sbrk(pcsamples_size * sizeof(unsigned short)); + + if (s_pcsamples != 0) + { + /* initialize the buffer to zero */ + memset(s_pcsamples, 0, pcsamples_size * sizeof(unsigned short)); + + alt_gmon_data[GMON_DATA_PROFILE_DATA] = (int)s_pcsamples; + alt_gmon_data[GMON_DATA_PROFILE_RATE] = prof_rate; + + /* Sample every tick (it's cheap) */ + alt_alarm_start(&s_nios2_pcsample_alarm, 1, nios2_pcsample, 0); + } + + return 0; +} + + +/* + * Sample the PC value and store it in the histogram + */ +static alt_u32 nios2_pcsample(void* context) +{ + unsigned int pc; + unsigned int bucket; + + /* read the exception return address - this will be + * inaccurate if there are nested interrupts but we + * assume that this is rare and the inaccuracy will + * not be great */ + NIOS2_READ_EA(pc); + + /* + * If we're within the profilable range then increment the relevant + * bucket in the histogram + */ + if (pc >= s_low_pc && pc < s_high_pc && s_pcsamples != 0) + { + bucket = (pc - s_low_pc)/PCSAMPLE_BYTES_PER_BUCKET; + s_pcsamples[bucket]++; + } + + /* Sample every tick */ + return 1; +} + diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_icache_flush.c b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_icache_flush.c new file mode 100644 index 00000000..4b706ed6 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_icache_flush.c @@ -0,0 +1,84 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include "nios2.h" +#include "system.h" + +#include "alt_types.h" +#include "sys/alt_cache.h" + +/* + * alt_icache_flush() is called to flush the instruction cache for a memory + * region of length "len" bytes, starting at address "start". + */ + +void alt_icache_flush (void* start, alt_u32 len) +{ +#if NIOS2_ICACHE_SIZE > 0 + + char* i; + char* end; + + /* + * This is the most we would ever need to flush. + */ + + if (len > NIOS2_ICACHE_SIZE) + { + len = NIOS2_ICACHE_SIZE; + } + + end = ((char*) start) + len; + + for (i = start; i < end; i+= NIOS2_ICACHE_LINE_SIZE) + { + __asm__ volatile ("flushi %0" :: "r" (i)); + } + + /* + * For an unaligned flush request, we've got one more line left. + * Note that this is dependent on NIOS2_ICACHE_LINE_SIZE to be a + * multiple of 2 (which it always is). + */ + + if (((alt_u32) start) & (NIOS2_ICACHE_LINE_SIZE - 1)) + { + __asm__ volatile ("flushi %0" :: "r" (i)); + } + + /* + * Having flushed the cache, flush any stale instructions in the + * pipeline + */ + + __asm__ volatile ("flushp"); + +#endif /* NIOS2_ICACHE_SIZE > 0 */ +} diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_icache_flush_all.c b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_icache_flush_all.c new file mode 100644 index 00000000..50885522 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_icache_flush_all.c @@ -0,0 +1,46 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include "nios2.h" +#include "system.h" + +#include "alt_types.h" +#include "sys/alt_cache.h" + +/* + * alt_icache_flush_all() is called to flush the entire instruction cache. + */ + +void alt_icache_flush_all (void) +{ +#if NIOS2_ICACHE_SIZE > 0 + alt_icache_flush (0, NIOS2_ICACHE_SIZE); +#endif +} diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_iic.c b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_iic.c new file mode 100644 index 00000000..1db5afa6 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_iic.c @@ -0,0 +1,106 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2009 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ +#include "system.h" + +/* + * This file implements the HAL Enhanced interrupt API for Nios II processors + * with an internal interrupt controller (IIC). For most routines, this serves + * as a wrapper layer over the legacy interrupt API (which must be used with + * the IIC only). + * + * Use of the enhanced API is recommended so that application and device + * drivers are compatible with a Nios II system configured with an external + * interrupt controller (EIC), or IIC. This will afford maximum portability. + * + * If an EIC is present, the EIC device driver must provide these routines, + * because their operation will be specific to that EIC type. + */ +#ifndef NIOS2_EIC_PRESENT +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT + +#include "sys/alt_irq.h" +#include "priv/alt_iic_isr_register.h" +#include "priv/alt_legacy_irq.h" + +/** @Function Description: This function registers an interrupt handler. + * If the function is succesful, then the requested interrupt will be enabled upon + * return. Registering a NULL handler will disable the interrupt. + * @API Type: External + * @param ic_id Ignored. + * @param irq IRQ number + * @return 0 if successful, else error (-1) + */ +int alt_ic_isr_register(alt_u32 ic_id, alt_u32 irq, alt_isr_func isr, + void *isr_context, void *flags) +{ + return alt_iic_isr_register(ic_id, irq, isr, isr_context, flags); +} + +/** @Function Description: This function enables a single interrupt. + * @API Type: External + * @param ic_id Ignored. + * @param irq IRQ number + * @return 0 if successful, else error (-1) + */ +int alt_ic_irq_enable (alt_u32 ic_id, alt_u32 irq) +{ + return alt_irq_enable(irq); +} + +/** @Function Description: This function disables a single interrupt. + * @API Type: External + * @param ic_id Ignored. + * @param irq IRQ number + * @return 0 if successful, else error (-1) + */ +int alt_ic_irq_disable(alt_u32 ic_id, alt_u32 irq) +{ + return alt_irq_disable(irq); +} + +/** @Function Description: This function to determine if corresponding + * interrupt is enabled. + * @API Type: External + * @param ic_id Ignored. + * @param irq IRQ number + * @return Zero if corresponding interrupt is disabled and + * non-zero otherwise. + */ +alt_u32 alt_ic_irq_enabled(alt_u32 ic_id, alt_u32 irq) +{ + alt_u32 irq_enabled; + + NIOS2_READ_IENABLE(irq_enabled); + + return (irq_enabled & (1 << irq)) ? 1: 0; +} + +#endif /* ALT_ENHANCED_INTERRUPT_API_PRESENT */ +#endif /* NIOS2_EIC_PRESENT */ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_iic_isr_register.c b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_iic_isr_register.c new file mode 100644 index 00000000..b104395d --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_iic_isr_register.c @@ -0,0 +1,104 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2009 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ +#include +#include "system.h" + +/* + * Provides an interrupt registry mechanism for the any CPUs internal interrupt + * controller (IIC) when the enhanced interrupt API is active. + */ +#ifndef ALT_CPU_EIC_PRESENT +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT + +#include "alt_types.h" +#include "sys/alt_irq.h" +#include "priv/alt_iic_isr_register.h" + +/* + * The header, alt_irq_entry.h, contains the exception entry point, and is + * provided by the processor component. It is included here, so that the code + * will be added to the executable only if alt_irq_register() is present, i.e. + * if no interrupts are registered - there's no need to provide any + * interrupt handling. + */ + +#include "sys/alt_irq_entry.h" + +/* + * The header, alt_irq_table.h contains a table describing which function + * handles each interrupt. + */ + +#include "priv/alt_irq_table.h" + +/** @Function Description: This function registers an interrupt handler. + * If the function is succesful, then the requested interrupt will be enabled + * upon return. Registering a NULL handler will disable the interrupt. + * + * @API Type: External + * @param ic_id Interrupt controller ID + * @param irq IRQ ID number + * @param isr Pointer to interrupt service routine + * @param isr_context Opaque pointer passed to ISR + * @param flags + * @return 0 if successful, else error (-1) + */ +int alt_iic_isr_register(alt_u32 ic_id, alt_u32 irq, alt_isr_func isr, + void *isr_context, void *flags) +{ + int rc = -EINVAL; + int id = irq; /* IRQ interpreted as the interrupt ID. */ + alt_irq_context status; + + if (id < ALT_NIRQ) + { + /* + * interrupts are disabled while the handler tables are updated to ensure + * that an interrupt doesn't occur while the tables are in an inconsistant + * state. + */ + + status = alt_irq_disable_all(); + + alt_irq[id].handler = isr; + alt_irq[id].context = isr_context; + + rc = (isr) ? alt_ic_irq_enable(ic_id, id) : alt_ic_irq_disable(ic_id, id); + + alt_irq_enable_all(status); + } + + return rc; +} + +#endif /* ALT_ENHANCED_INTERRUPT_API_PRESENT */ +#endif /* ALT_CPU_EIC_PRESENT */ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_instruction_exception_entry.c b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_instruction_exception_entry.c new file mode 100644 index 00000000..f4f52fc3 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_instruction_exception_entry.c @@ -0,0 +1,203 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2008 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ +#include "sys/alt_exceptions.h" +#include "nios2.h" +#include "alt_types.h" +#include "system.h" + +/* + * This file implements support for calling user-registered handlers for + * instruction-generated exceptions. This handler could also be reached + * in the event of a spurious interrupt. + * + * The handler code is optionally enabled through the "Enable + * Instruction-related Exception API" HAL BSP setting, which will + * define the macro below. + */ +#ifdef ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API + +/* Function pointer to exception callback routine */ +alt_exception_result (*alt_instruction_exception_handler) + (alt_exception_cause, alt_u32, alt_u32) = 0x0; + +/* Link entry routine to .exceptions section */ +int alt_instruction_exception_entry (alt_u32 exception_pc) + __attribute__ ((section (".exceptions"))); + +/* + * This is the entry point for instruction-generated exceptions handling. + * This routine will be called by alt_exceptions_entry.S, after it determines + * that an exception could not be handled by handlers that preceed that + * of instruction-generated exceptions (such as interrupts). + * + * For this to function properly, you must register an exception handler + * using alt_instruction_exception_register(). This routine will call + * that handler if it has been registered. Absent a handler, it will + * break break or hang as discussed below. + */ +int alt_instruction_exception_entry (alt_u32 exception_pc) +{ + alt_u32 cause, badaddr; + +/* + * If the processor hardware has the optional EXCEPTIONS & BADADDR registers, + * read them and pass their content to the user handler. These are always + * present if the MMU or MPU is enabled, and optionally for other advanced + * exception types via the "Extra exceptions information" setting in the + * processor (hardware) configuration. + * + * If these registers are not present, the cause field will be set to + * NIOS2_EXCEPTION_CAUSE_NOT_PRESENT. Your handling routine should + * check the validity of the cause argument before proceeding. + */ +#ifdef NIOS2_HAS_EXTRA_EXCEPTION_INFO + /* Get exception cause & "badaddr" */ + NIOS2_READ_EXCEPTION(cause); + cause = ( (cause & NIOS2_EXCEPTION_REG_CAUSE_MASK) >> + NIOS2_EXCEPTION_REG_CAUSE_OFST ); + + NIOS2_READ_BADADDR(badaddr); +#else + cause = NIOS2_EXCEPTION_CAUSE_NOT_PRESENT; + badaddr = 0; +#endif /* NIOS2_HAS_EXTRA_EXCEPTION_INFO */ + + if(alt_instruction_exception_handler) { + /* + * Call handler. Its return value indicates whether the exception-causing + * instruction should be re-issued. The code that called us, + * alt_eceptions_entry.S, will look at this value and adjust the ea + * register as necessary + */ + return alt_instruction_exception_handler(cause, exception_pc, badaddr); + } + /* + * We got here because an instruction-generated exception occured, but no + * handler is present. We do not presume to know how to handle it. If the + * debugger is present, break, otherwise hang. + * + * If you've reached here in the debugger, consider examining the + * EXCEPTIONS register cause bit-field, which was read into the 'cause' + * variable above, and compare it against the exceptions-type enumeration + * in alt_exceptions.h. This register is availabe if the MMU or MPU is + * present, or if the "Extra exceptions information" hardware option is + * selected. + * + * If you get here then one of the following could have happened: + * + * - An instruction-generated exception occured, and the processor + * does not have the extra exceptions feature enabled, or you + * have not registered a handler using + * alt_instruction_exception_register() + * + * Some examples of instruction-generated exceptions and why they + * might occur: + * + * - Your program could have been compiled for a full-featured + * Nios II core, but it is running on a smaller core, and + * instruction emulation has been disabled by defining + * ALT_NO_INSTRUCTION_EMULATION. + * + * You can work around the problem by re-enabling instruction + * emulation, or you can figure out why your program is being + * compiled for a system other than the one that it is running on. + * + * - Your program has executed a trap instruction, but has not + * implemented a handler for this instruction. + * + * - Your program has executed an illegal instruction (one which is + * not defined in the instruction set). + * + * - Your processor includes an MMU or MPU, and you have enabled it + * before registering an exception handler to service exceptions it + * generates. + * + * The problem could also be hardware related: + * - If your hardware is broken and is generating spurious interrupts + * (a peripheral which negates its interrupt output before its + * interrupt handler has been executed will cause spurious interrupts) + */ + else { +#ifdef NIOS2_HAS_DEBUG_STUB + NIOS2_BREAK(); +#else + while(1) + ; +#endif /* NIOS2_HAS_DEBUG_STUB */ + } + + /* // We should not get here. Remove compiler warning. */ + return NIOS2_EXCEPTION_RETURN_REISSUE_INST; +} + +#endif /* ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API */ + +/* + * This routine indicates whether a particular exception cause will have + * set a valid address into the BADADDR register, which is included + * in the arguments to a user-registered instruction-generated exception + * handler. Many exception types do not set valid contents in BADADDR; + * this is a convenience routine to easily test the validity of that + * argument in your handler. + * + * Note that this routine will return false (0) for cause '12', + * TLB miss. This is because there are four exception types that + * share that cause, two of which do not have a valid BADADDR. You + * must determine BADADDR's validity for these. + * + * Arguments: + * cause: The 5-bit exception cause field of the EXCEPTIONS register, + * shifted to the LSB position. You may pass the 'cause' argument + * in a handler you registered directy to this routine. + * + * Return: 1: BADADDR (bad_addr argument to handler) is valid + * 0: BADADDR is not valid + */ +int alt_exception_cause_generated_bad_addr(alt_exception_cause cause) +{ + switch (cause) { + case NIOS2_EXCEPTION_SUPERVISOR_ONLY_DATA_ADDR: + return 1; + case NIOS2_EXCEPTION_MISALIGNED_DATA_ADDR: + return 1; + case NIOS2_EXCEPTION_MISALIGNED_TARGET_PC: + return 1; + case NIOS2_EXCEPTION_TLB_READ_PERM_VIOLATION: + return 1; + case NIOS2_EXCEPTION_TLB_WRITE_PERM_VIOLATION: + return 1; + case NIOS2_EXCEPTION_MPU_DATA_REGION_VIOLATION: + return 1; + default: + return 0; + } +} diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_instruction_exception_register.c b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_instruction_exception_register.c new file mode 100644 index 00000000..b059e1dd --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_instruction_exception_register.c @@ -0,0 +1,82 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2008 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ +#include "sys/alt_exceptions.h" +#include "alt_types.h" +#include "system.h" + +/* + * This file implements support for calling user-registered handlers for + * instruction-generated exceptions. + * + * The registry API is optionally enabled through the "Enable + * Instruction-related Exception API" HAL BSP setting, which will + * define the macro below. + */ +#ifdef ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API + +/* + * The header, alt_exception_handler_registry.h contains a struct describing + * the registered exception handler + */ +#include "priv/alt_exception_handler_registry.h" + +/* + * Pull in the exception entry assembly code. This will not be linked in + * unless this object is linked into the executable (i.e. only if + * alt_instruction_exception_register() is called). + */ +__asm__( "\n\t.globl alt_exception" ); + +/* + * alt_instruction_exception_register() is called to register a handler to + * service instruction-generated exceptions that are not handled by the + * default exception handler code (interrupts, and optionally unimplemented + * instructions and traps). + * + * Passing null (0x0) in the handler argument will disable a previously- + * registered handler. + * + * Note that if no handler is registered, exceptions that are not processed + * using the built-in handler (interrupts, and optionally unimplemented + * instructions and traps) are treated as unknown exceptions, resulting + * in either a break or an infinite loop. + */ +void alt_instruction_exception_register ( + alt_exception_result (*exception_handler)( + alt_exception_cause cause, + alt_u32 exception_pc, + alt_u32 bad_addr) ) +{ + alt_instruction_exception_handler = exception_handler; +} + +#endif /* ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API */ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_io_redirect.c b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_io_redirect.c new file mode 100644 index 00000000..8c862f7b --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_io_redirect.c @@ -0,0 +1,98 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include +#include +#include +#include + +#include "sys/alt_dev.h" +#include "priv/alt_file.h" + + +/* + * alt_open_fd() is similar to open() in that it is used to obtain a file + * descriptor for the file named "name". The "flags" and "mode" arguments are + * identical to the "flags" and "mode" arguments of open(). + * + * The distinction between the two functions is that the file descriptor + * structure to use is passed in as an argument, rather than allocated from the + * list of free file descriptors. + * + * This is used by alt_io_redirect() to redirect the stdin, stdout and stderr + * file descriptors to point to new devices. + * + * If the device can not be succesfully opened, then the input file descriptor + * remains unchanged. + */ + +static void alt_open_fd(alt_fd* fd, const char* name, int flags, int mode) +{ + int old; + + old = open (name, flags, mode); + + if (old >= 0) + { + fd->dev = alt_fd_list[old].dev; + fd->priv = alt_fd_list[old].priv; + fd->fd_flags = alt_fd_list[old].fd_flags; + + alt_release_fd (old); + } +} + +/* + * alt_io_redirect() is called once the device/filesystem lists have been + * initialised, but before main(). Its function is to redirect standard in, + * standard out and standard error so that they point to the devices selected by + * the user (as defined in system.h). + * + * Prior to the call to this function, io is directed towards /dev/null. If + * i/o can not be redirected to the requested device, for example if the device + * does not exist, then it remains directed at /dev/null. + */ + +void alt_io_redirect(const char* stdout_dev, + const char* stdin_dev, + const char* stderr_dev) +{ + /* Redirect the channels */ + + alt_open_fd (&alt_fd_list[STDOUT_FILENO], stdout_dev, O_WRONLY, 0777); + alt_open_fd (&alt_fd_list[STDIN_FILENO], stdin_dev, O_RDONLY, 0777); + alt_open_fd (&alt_fd_list[STDERR_FILENO], stderr_dev, O_WRONLY, 0777); +} + + + + diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_ioctl.c b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_ioctl.c new file mode 100644 index 00000000..f5d7ef1f --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_ioctl.c @@ -0,0 +1,170 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include + +#include "sys/ioctl.h" +#include "sys/alt_errno.h" +#include "sys/alt_warning.h" +#include "priv/alt_file.h" +#include "os/alt_syscall.h" + +/* + * The ioctl() system call is provided so that application code can manipulate + * the i/o capabilities of a device in device specific ways. This is identical + * to the standard posix ioctl() function. + * + * In general this implementation simply vectors ioctl requests to the + * apropriate drivers ioctl function (as registered in the drivers alt_dev + * structure). + * + * However in the case of devices (as oposed to filesystem), the TIOCEXCL and + * TIOCNXCL requests are handled without reference to the driver. These + * requests are used to lock/release a device for exclusive access. + * + * Handling these requests centrally eases the task of device driver + * development. + * + * ALT_IOCTL is mapped onto the ioctl() system call in alt_syscall.h + */ + +#ifdef ALT_USE_DIRECT_DRIVERS + +#include "system.h" +#include "sys/alt_driver.h" + +/* + * Provide minimal version that calls ioctl routine of provided stdio devices. + */ +int ALT_IOCTL (int file, int req, void* arg) +{ +#ifdef ALT_STDIN_PRESENT + ALT_DRIVER_IOCTL_EXTERNS(ALT_STDIN_DEV); +#endif +#ifdef ALT_STDOUT_PRESENT + ALT_DRIVER_IOCTL_EXTERNS(ALT_STDOUT_DEV); +#endif +#ifdef ALT_STDERR_PRESENT + ALT_DRIVER_IOCTL_EXTERNS(ALT_STDERR_DEV); +#endif + +#if !defined(ALT_STDIN_PRESENT) && !defined(ALT_STDOUT_PRESENT) && !defined(ALT_STDERR_PRESENT) + /* Generate a link time warning, should this function ever be called. */ + ALT_STUB_WARNING(ioctl); +#endif + + switch (file) { +#ifdef ALT_STDIN_PRESENT + case 0: /* stdin file descriptor */ + return ALT_DRIVER_IOCTL(ALT_STDIN_DEV, req, arg); +#endif /* ALT_STDIN_PRESENT */ +#ifdef ALT_STDOUT_PRESENT + case 1: /* stdout file descriptor */ + return ALT_DRIVER_IOCTL(ALT_STDOUT_DEV, req, arg); +#endif /* ALT_STDOUT_PRESENT */ +#ifdef ALT_STDERR_PRESENT + case 2: /* stderr file descriptor */ + return ALT_DRIVER_IOCTL(ALT_STDERR_DEV, req, arg); +#endif /* ALT_STDERR_PRESENT */ + default: + ALT_ERRNO = EBADFD; + return -1; + } +} + +#else /* !ALT_USE_DIRECT_DRIVERS */ + +int ALT_IOCTL (int file, int req, void* arg) +{ + alt_fd* fd; + int rc; + + /* + * A common error case is that when the file descriptor was created, the call + * to open() failed resulting in a negative file descriptor. This is trapped + * below so that we don't try and process an invalid file descriptor. + */ + + fd = (file < 0) ? NULL : &alt_fd_list[file]; + + if (fd) + { + + /* + * In the case of device drivers (not file systems) handle the TIOCEXCL + * and TIOCNXCL requests as special cases. + */ + + if (fd->fd_flags & ALT_FD_DEV) + { + if (req == TIOCEXCL) + { + rc = alt_fd_lock (fd); + goto ioctl_done; + } + else if (req == TIOCNXCL) + { + rc = alt_fd_unlock (fd); + goto ioctl_done; + } + } + + /* + * If the driver provides an ioctl() function, call that to handle the + * request, otherwise set the return code to indicate that the request + * could not be processed. + */ + + if (fd->dev->ioctl) + { + rc = fd->dev->ioctl(fd, req, arg); + } + else + { + rc = -ENOTTY; + } + } + else + { + rc = -EBADFD; + } + +ioctl_done: + + if (rc < 0) + { + ALT_ERRNO = -rc; + } + return rc; +} + +#endif /* ALT_USE_DIRECT_DRIVERS */ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_irq_entry.S b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_irq_entry.S new file mode 100644 index 00000000..d3efe7db --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_irq_entry.S @@ -0,0 +1,108 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003-2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include "system.h" + +/* + * This is the interrupt exception entry point code, which saves all the + * registers and calls the interrupt handler. It should be pulled in using + * a .globl from alt_irq_register.c. This scheme is used so that if an + * interrupt is never registered, then this code will not appear in the + * generated executable, thereby improving code footprint. + */ + + /* + * Explicitly allow the use of r1 (the assembler temporary register) + * within this code. This register is normally reserved for the use of + * the compiler. + */ + .set noat + + /* + * Pull in the exception handler register save code. + */ + .globl alt_exception + + .globl alt_irq_entry + .section .exceptions.entry.label, "xa" +alt_irq_entry: + + /* + * Section .exceptions.entry is in alt_exception_entry.S + * This saves all the caller saved registers and reads estatus into r5 + */ + + .section .exceptions.irqtest, "xa" + +#ifdef ALT_CI_INTERRUPT_VECTOR_N + /* + * Use the interrupt vector custom instruction if present to accelerate + * this code. + * If the interrupt vector custom instruction returns a negative + * value, there are no interrupts active (estatus.pie is 0 + * or ipending is 0) so assume it is a software exception. + */ + custom ALT_CI_INTERRUPT_VECTOR_N, r4, r0, r0 + blt r4, r0, .Lnot_irq +#else + /* + * Test to see if the exception was a software exception or caused + * by an external interrupt, and vector accordingly. + */ + rdctl r4, ipending + andi r2, r5, 1 + beq r2, zero, .Lnot_irq + beq r4, zero, .Lnot_irq +#endif /* ALT_CI_INTERRUPT_VECTOR_N */ + + .section .exceptions.irqhandler, "xa" + /* + * Now that all necessary registers have been preserved, call + * alt_irq_handler() to process the interrupts. + */ + + call alt_irq_handler + + .section .exceptions.irqreturn, "xa" + + br .Lexception_exit + + .section .exceptions.notirq.label, "xa" + +.Lnot_irq: + + /* + * Section .exceptions.exit is in alt_exception_entry.S + * This restores all the caller saved registers + */ + + .section .exceptions.exit.label +.Lexception_exit: + diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_irq_handler.c b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_irq_handler.c new file mode 100644 index 00000000..3253d02c --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_irq_handler.c @@ -0,0 +1,169 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2009 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include +#include "system.h" + +/* + * This interrupt handler only works with an internal interrupt controller + * (IIC). Processors with an external interrupt controller (EIC) use an + * implementation provided by an EIC driver. + */ +#ifndef ALT_CPU_EIC_PRESENT + +#include "sys/alt_irq.h" +#include "os/alt_hooks.h" + +#include "alt_types.h" + +/* + * A table describing each interrupt handler. The index into the array is the + * interrupt id associated with the handler. + * + * When an interrupt occurs, the associated handler is called with + * the argument stored in the context member. + */ +struct ALT_IRQ_HANDLER +{ +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT + void (*handler)(void*); +#else + void (*handler)(void*, alt_u32); +#endif + void *context; +} alt_irq[ALT_NIRQ]; + +/* + * alt_irq_handler() is called by the interrupt exception handler in order to + * process any outstanding interrupts. + * + * It is defined here since it is linked in using weak linkage. + * This means that if there is never a call to alt_irq_register() (above) then + * this function will not get linked in to the executable. This is acceptable + * since if no handler is ever registered, then an interrupt can never occur. + * + * If Nios II interrupt vector custom instruction exists, use it to accelerate + * the dispatch of interrupt handlers. The Nios II interrupt vector custom + * instruction is present if the macro ALT_CI_INTERRUPT_VECTOR defined. + */ + +void alt_irq_handler (void) __attribute__ ((section (".exceptions"))); +void alt_irq_handler (void) +{ +#ifdef ALT_CI_INTERRUPT_VECTOR + alt_32 offset; + char* alt_irq_base = (char*)alt_irq; +#else + alt_u32 active; + alt_u32 mask; + alt_u32 i; +#endif /* ALT_CI_INTERRUPT_VECTOR */ + + /* + * Notify the operating system that we are at interrupt level. + */ + + ALT_OS_INT_ENTER(); + +#ifdef ALT_CI_INTERRUPT_VECTOR + /* + * Call the interrupt vector custom instruction using the + * ALT_CI_INTERRUPT_VECTOR macro. + * It returns the offset into the vector table of the lowest-valued pending + * interrupt (corresponds to highest priority) or a negative value if none. + * The custom instruction assumes that each table entry is eight bytes. + */ + while ((offset = ALT_CI_INTERRUPT_VECTOR) >= 0) { + struct ALT_IRQ_HANDLER* handler_entry = + (struct ALT_IRQ_HANDLER*)(alt_irq_base + offset); +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT + handler_entry->handler(handler_entry->context); +#else + handler_entry->handler(handler_entry->context, offset >> 3); +#endif + } +#else /* ALT_CI_INTERRUPT_VECTOR */ + /* + * Obtain from the interrupt controller a bit list of pending interrupts, + * and then process the highest priority interrupt. This process loops, + * loading the active interrupt list on each pass until alt_irq_pending() + * return zero. + * + * The maximum interrupt latency for the highest priority interrupt is + * reduced by finding out which interrupts are pending as late as possible. + * Consider the case where the high priority interupt is asserted during + * the interrupt entry sequence for a lower priority interrupt to see why + * this is the case. + */ + + active = alt_irq_pending (); + + do + { + i = 0; + mask = 1; + + /* + * Test each bit in turn looking for an active interrupt. Once one is + * found, the interrupt handler asigned by a call to alt_irq_register() is + * called to clear the interrupt condition. + */ + + do + { + if (active & mask) + { +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT + alt_irq[i].handler(alt_irq[i].context); +#else + alt_irq[i].handler(alt_irq[i].context, i); +#endif + break; + } + mask <<= 1; + i++; + + } while (1); + + active = alt_irq_pending (); + + } while (active); +#endif /* ALT_CI_INTERRUPT_VECTOR */ + + /* + * Notify the operating system that interrupt processing is complete. + */ + + ALT_OS_INT_EXIT(); +} + +#endif /* ALT_CPU_EIC_PRESENT */ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_irq_register.c b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_irq_register.c new file mode 100644 index 00000000..b5ea474f --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_irq_register.c @@ -0,0 +1,102 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2009 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ +#include +#include "system.h" + +/* + * This interrupt registry mechanism works with the Nios II internal interrupt + * controller (IIC) only. Systems with an external interrupt controller (EIC), + * or those with the IIC who are using the enhanced interrupt API will + * utilize the alt_ic_isr_register() routine to register an interrupt. + */ +#ifndef NIOS2_EIC_PRESENT + +#include "sys/alt_irq.h" +#include "priv/alt_legacy_irq.h" +#include "os/alt_hooks.h" + +#include "alt_types.h" + +/* + * The header, alt_irq_entry.h, contains the exception entry point, and is + * provided by the processor component. It is included here, so that the code + * will be added to the executable only if alt_irq_register() is present, i.e. + * if no interrupts are registered - there's no need to provide any + * interrupt handling. + */ + +#include "sys/alt_irq_entry.h" + +/* + * The header, alt_irq_table.h contains a table describing which function + * handles each interrupt. + */ + +#include "priv/alt_irq_table.h" + +/* + * alt_irq_handler() is called to register an interrupt handler. If the + * function is succesful, then the requested interrupt will be enabled upon + * return. Registering a NULL handler will disable the interrupt. + * + * The return value is 0 if the interrupt handler was registered and the + * interrupt was enabled, otherwise it is negative. + */ + +int alt_irq_register (alt_u32 id, + void* context, + alt_isr_func handler) +{ + int rc = -EINVAL; + alt_irq_context status; + + if (id < ALT_NIRQ) + { + /* + * interrupts are disabled while the handler tables are updated to ensure + * that an interrupt doesn't occur while the tables are in an inconsistant + * state. + */ + + status = alt_irq_disable_all (); + + alt_irq[id].handler = handler; + alt_irq[id].context = context; + + rc = (handler) ? alt_irq_enable (id): alt_irq_disable (id); + + alt_irq_enable_all(status); + } + return rc; +} +#endif /* NIOS2_EIC_PRESENT */ + diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_irq_vars.c b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_irq_vars.c new file mode 100644 index 00000000..8c0a18d7 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_irq_vars.c @@ -0,0 +1,47 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include "alt_types.h" + +#include "system.h" + +/* + * These global variables are used to save the current list of enabled + * interrupts. See alt_irq.h for further details. + */ + +volatile alt_u32 alt_irq_active = 0; + +#ifndef ALT_EXCEPTION_STACK + +volatile alt_u32 alt_priority_mask = (alt_u32) -1; + +#endif + diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_isatty.c b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_isatty.c new file mode 100644 index 00000000..92764725 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_isatty.c @@ -0,0 +1,125 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include +#include + +#include "sys/alt_dev.h" +#include "sys/alt_errno.h" +#include "sys/alt_warning.h" +#include "priv/alt_file.h" +#include "os/alt_syscall.h" + +#ifdef ALT_USE_DIRECT_DRIVERS + +#include "system.h" + +/* + * Provide minimal version that just describes all file descriptors + * as tty devices for provided stdio devices. + */ +int ALT_ISATTY (int file) +{ + switch (file) { +#ifdef ALT_STDIN_PRESENT + case 0: /* stdin file descriptor */ +#endif /* ALT_STDIN_PRESENT */ +#ifdef ALT_STDOUT_PRESENT + case 1: /* stdout file descriptor */ +#endif /* ALT_STDOUT_PRESENT */ +#ifdef ALT_STDERR_PRESENT + case 2: /* stderr file descriptor */ +#endif /* ALT_STDERR_PRESENT */ + return 1; + default: + return 0; + } + +#if !defined(ALT_STDIN_PRESENT) && !defined(ALT_STDOUT_PRESENT) && !defined(ALT_STDERR_PRESENT) + /* Generate a link time warning, should this function ever be called. */ + ALT_STUB_WARNING(isatty); +#endif +} + +#else /* !ALT_USE_DIRECT_DRIVERS */ +/* + * isatty() can be used to determine whether the input file descriptor "file" + * refers to a terminal device or not. If it is a terminal device then the + * return value is one, otherwise it is zero. + * + * ALT_ISATTY is mapped onto the isatty() system call in alt_syscall.h + */ + +int ALT_ISATTY (int file) +{ + alt_fd* fd; + struct stat stat; + + /* + * A common error case is that when the file descriptor was created, the call + * to open() failed resulting in a negative file descriptor. This is trapped + * below so that we don't try and process an invalid file descriptor. + */ + + fd = (file < 0) ? NULL : &alt_fd_list[file]; + + if (fd) + { + /* + * If a device driver does not provide an fstat() function, then it is + * treated as a terminal device by default. + */ + + if (!fd->dev->fstat) + { + return 1; + } + + /* + * If a driver does provide an implementation of the fstat() function, then + * this is called so that the device can identify itself. + */ + + else + { + fstat (file, &stat); + return (stat.st_mode == _IFCHR) ? 1 : 0; + } + } + else + { + ALT_ERRNO = EBADFD; + return 0; + } +} + +#endif /* ALT_USE_DIRECT_DRIVERS */ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_kill.c b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_kill.c new file mode 100644 index 00000000..42c2e1d5 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_kill.c @@ -0,0 +1,121 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include +#include + +#include "sys/alt_errno.h" +#include "os/alt_syscall.h" + + +/* + * kill() is used by newlib in order to send signals to processes. Since there + * is only a single process in the HAL, the only valid values for pid are + * either the current process id, or the broadcast values, i.e. pid must be + * less than or equal to zero. + * + * ALT_KILL is mapped onto the kill() system call in alt_syscall.h + */ + +int ALT_KILL (int pid, int sig) +{ + int status = 0; + + if (pid <= 0) + { + switch (sig) + { + case 0: + + /* The null signal is used to check that a pid is valid. */ + + break; + + case SIGABRT: + case SIGALRM: + case SIGFPE: + case SIGILL: + case SIGKILL: + case SIGPIPE: + case SIGQUIT: + case SIGSEGV: + case SIGTERM: + case SIGUSR1: + case SIGUSR2: + case SIGBUS: + case SIGPOLL: + case SIGPROF: + case SIGSYS: + case SIGTRAP: + case SIGVTALRM: + case SIGXCPU: + case SIGXFSZ: + + /* + * The Posix standard defines the default behaviour for all these signals + * as being eqivalent to a call to _exit(). No mechanism is provided to + * change this behaviour. + */ + + _exit(0); + case SIGCHLD: + case SIGURG: + + /* + * The Posix standard defines these signals to be ignored by default. No + * mechanism is provided to change this behaviour. + */ + + break; + default: + + /* Tried to send an unsupported signal */ + + status = EINVAL; + } + } + + else if (pid > 0) + { + /* Attempted to signal a non-existant process */ + + status = ESRCH; + } + + if (status) + { + ALT_ERRNO = status; + return -1; + } + + return 0; +} diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_link.c b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_link.c new file mode 100644 index 00000000..d796c592 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_link.c @@ -0,0 +1,56 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include "sys/alt_warning.h" +#include "sys/alt_errno.h" +#include "os/alt_syscall.h" + +/* + * link() is used by newlib to create a new link to an existing file. This is + * unsupported in the HAL environment. However a "do-nothing" implementation + * is still provied for newlib compatability. + * + * ALT_LINK is mapped onto the link() system call in alt_syscall.h + */ + +int ALT_LINK ( char *existing, char *new) +{ + /* Generate a link time warning, should this function ever be called. */ + + ALT_STUB_WARNING(link); + + /* Indicate an error */ + + ALT_ERRNO = ENOSYS; + return -1; +} + diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_load.c b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_load.c new file mode 100644 index 00000000..ffab4b9c --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_load.c @@ -0,0 +1,88 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004-2005 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include "sys/alt_load.h" +#include "sys/alt_cache.h" + +/* + * Linker defined symbols. + */ + +extern void __flash_rwdata_start; +extern void __ram_rwdata_start; +extern void __ram_rwdata_end; +extern void __flash_rodata_start; +extern void __ram_rodata_start; +extern void __ram_rodata_end; +extern void __flash_exceptions_start; +extern void __ram_exceptions_start; +extern void __ram_exceptions_end; + +/* + * alt_load() is called when the code is executing from flash. In this case + * there is no bootloader, so this application is responsible for loading to + * RAM any sections that are required. + */ + +void alt_load (void) +{ + /* + * Copy the .rwdata section. + */ + + alt_load_section (&__flash_rwdata_start, + &__ram_rwdata_start, + &__ram_rwdata_end); + + /* + * Copy the exception handler. + */ + + alt_load_section (&__flash_exceptions_start, + &__ram_exceptions_start, + &__ram_exceptions_end); + + /* + * Copy the .rodata section. + */ + + alt_load_section (&__flash_rodata_start, + &__ram_rodata_start, + &__ram_rodata_end); + + /* + * Now ensure that the caches are in synch. + */ + + alt_dcache_flush_all(); + alt_icache_flush_all(); +} diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_log_macro.S b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_log_macro.S new file mode 100644 index 00000000..499c4ad2 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_log_macro.S @@ -0,0 +1,56 @@ +/* alt_log_macro.S + * + * Implements the function tx_log_str, called by the assembly macro + * ALT_LOG_PUTS(). The macro will be empty when logging is turned off, + * and this function will not be compiled. When logging is on, + * this function is used to print out the strings defined in the beginning + * of alt_log_printf.c, using port information taken from system.h and + * alt_log_printf.h. + * + * This routine only handles strings, and sends a character into the defined + * output device's output buffer when the device is ready. It's intended for + * debugging purposes, where messages can be set to print out at certain + * points in the boot code to indicate the progress of the program. + * + */ + +#ifndef __ALT_LOG_MACROS__ +#define __ALT_LOG_MACROS__ + +/* define this flag to skip assembly-incompatible parts + * of various include files. */ +#define ALT_ASM_SRC + +#ifdef ALT_LOG_ENABLE // only compile this function if this flag is defined. + + #include "system.h" + #include "sys/alt_log_printf.h" + + .global tx_log_str +tx_log_str: + /* load base uart / jtag uart address into r6 */ + movhi r6, %hiadj(ALT_LOG_PORT_BASE) + addi r6, r6, %lo(ALT_LOG_PORT_BASE) +tx_next_char: + /* if pointer points to null, return + * r4 is the pointer to the str to be printed, set by ALT_LOG_PUTS */ + ldb r7, (r4) + beq r0, r7, end_tx + + /* check device transmit ready */ +wait_tx_ready_loop: + ldwio r5, ALT_LOG_PRINT_REG_OFFSET(r6) + andi r5, r5, ALT_LOG_PRINT_MSK + beq r5, r0, wait_tx_ready_loop + /* write char */ + stwio r7, ALT_LOG_PRINT_TXDATA_REG_OFFSET (r6) + /* advance string pointer */ + addi r4, r4, 1 + br tx_next_char +end_tx: + ret + +#endif + +#endif /* __ALT_LOG_MACROS__ */ + diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_log_printf.c b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_log_printf.c new file mode 100644 index 00000000..1f7056db --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_log_printf.c @@ -0,0 +1,479 @@ + +/* alt_log_printf.c + * + * This file implements the various C functions used for the + * alt_log logging/debugging print functions. The functions + * sit as is here - the job of hiding them from the compiler + * if logging is disabled is accomplished in the .h file. + * + * All the global variables for alt_log are defined here. + * These include the various flags that turn on additional + * logging options; the strings for assembly printing; and + * other globals needed by different logging options. + * + * There are 4 functions that handle the actual printing: + * alt_log_txchar: Actual function that puts 1 char to UART/JTAG UART. + * alt_log_repchar: Calls alt_log_txchar 'n' times - used by + * alt_log_private_printf for formatting. + * alt_log_private_printf: + * Stripped down implementation of printf - no floats. + * alt_log_printf_proc: + * Wrapper function for private_printf. + * + * The rest of the functions are called by the macros which + * were called by code in the other components. Each function + * is preceded by a comment, about which file it gets called + * in, and what its purpose is. + * + * author: gkwan + */ + +/* skip all code if enable is off */ +#ifdef ALT_LOG_ENABLE + +#include +#include +#include +#ifdef __ALTERA_AVALON_JTAG_UART + #include "altera_avalon_jtag_uart.h" + #include +#endif +#include "sys/alt_log_printf.h" + +/* strings for assembly puts */ +char alt_log_msg_bss[] = "[crt0.S] Clearing BSS \r\n";; +char alt_log_msg_alt_main[] = "[crt0.S] Calling alt_main.\r\n"; +char alt_log_msg_stackpointer[] \ + = "[crt0.S] Setting up stack and global pointers.\r\n"; +char alt_log_msg_cache[] = "[crt0.S] Inst & Data Cache Initialized.\r\n"; +/* char array allocation for alt_write */ +char alt_log_write_buf[ALT_LOG_WRITE_ECHO_LEN+2]; + +/* global variables for all 'on' flags */ + +/* + * The boot message flag is linked into the data (rwdata) section + * because if it is zero, it would otherwise be placed in the bss section. + * alt_log examines this variable before the BSS is cleared in the boot-up + * process. + */ +volatile alt_u32 alt_log_boot_on_flag \ + __attribute__ ((section (".data"))) = ALT_LOG_BOOT_ON_FLAG_SETTING; + +volatile alt_u8 alt_log_write_on_flag = ALT_LOG_WRITE_ON_FLAG_SETTING; + +volatile alt_u8 alt_log_sys_clk_on_flag = ALT_LOG_SYS_CLK_ON_FLAG_SETTING; + +volatile alt_u8 alt_log_jtag_uart_alarm_on_flag = \ + ALT_LOG_JTAG_UART_ALARM_ON_FLAG_SETTING; + +volatile alt_u8 alt_log_jtag_uart_isr_on_flag = \ + ALT_LOG_JTAG_UART_ISR_ON_FLAG_SETTING; + +volatile alt_u8 alt_log_jtag_uart_startup_info_on_flag = \ + ALT_LOG_JTAG_UART_STARTUP_INFO_ON_FLAG_SETTING; + +/* Global alarm object for recurrent JTAG UART status printing */ +alt_alarm alt_log_jtag_uart_alarm_1; + +/* Global ints for system clock printing and count */ +volatile int alt_log_sys_clk_count; +volatile int alt_system_clock_in_sec; + +/* enum used by alt_log_private_printf */ +enum +{ + pfState_chars, + pfState_firstFmtChar, + pfState_otherFmtChar +}; + + + + +/* Function to put one char onto the UART/JTAG UART txdata register. */ +void alt_log_txchar(int c,char *base) +{ + /* Wait until the device is ready for a character */ + while((ALT_LOG_PRINT_REG_RD(base) & ALT_LOG_PRINT_MSK) == 0) + ; + /* And pop the character into the register */ + ALT_LOG_PRINT_TXDATA_WR(base,c); +} + + +/* Called by alt_log_private_printf to print out characters repeatedly */ +void alt_log_repchar(char c,int r,int base) +{ + while(r-- > 0) + alt_log_txchar(c,(char*) base); +} + + +/* Stripped down printf function */ +void alt_log_private_printf(const char *fmt,int base,va_list args) + { + const char *w; + char c; + int state; + int fmtLeadingZero = 0; /* init these all to 0 for -W warnings. */ + int fmtLong = 0; + int fmtBeforeDecimal = 0; + int fmtAfterDecimal = 0; + int fmtBase = 0; + int fmtSigned = 0; + int fmtCase = 0; /* For hex format, if 1, A-F, else a-f. */ + + w = fmt; + state = pfState_chars; + + while(0 != (c = *w++)) + { + switch(state) + { + case pfState_chars: + if(c == '%') + { + fmtLeadingZero = 0; + fmtLong = 0; + fmtBase = 10; + fmtSigned = 1; + fmtCase = 0; /* Only %X sets this. */ + fmtBeforeDecimal = -1; + fmtAfterDecimal = -1; + state = pfState_firstFmtChar; + } + else + { + alt_log_txchar(c,(char*)base); + } + break; + + case pfState_firstFmtChar: + if(c == '0') + { + fmtLeadingZero = 1; + state = pfState_otherFmtChar; + } + else if(c == '%') + { + alt_log_txchar(c,(char*)base); + state = pfState_chars; + } + else + { + state = pfState_otherFmtChar; + goto otherFmtChar; + } + break; + + case pfState_otherFmtChar: +otherFmtChar: + if(c == '.') + { + fmtAfterDecimal = 0; + } + else if('0' <= c && c <= '9') + { + c -= '0'; + if(fmtAfterDecimal < 0) /* still before decimal */ + { + if(fmtBeforeDecimal < 0) + { + fmtBeforeDecimal = 0; + } + else + { + fmtBeforeDecimal *= 10; + } + fmtBeforeDecimal += c; + } + else + { + fmtAfterDecimal = (fmtAfterDecimal * 10) + c; + } + } + else if(c == 'l') + { + fmtLong = 1; + } + else /* we're up to the letter which determines type */ + { + switch(c) + { + case 'd': + case 'i': +doIntegerPrint: + { + unsigned long v; + unsigned long p; /* biggest power of fmtBase */ + unsigned long vShrink; /* used to count digits */ + int sign; + int digitCount; + + /* Get the value */ + if(fmtLong) + { + if (fmtSigned) + { + v = va_arg(args,long); + } + else + { + v = va_arg(args,unsigned long); + } + } + else + { + if (fmtSigned) + { + v = va_arg(args,int); + } + else + { + v = va_arg(args,unsigned int); + } + } + + /* Strip sign */ + sign = 0; + /* (assumes sign bit is #31) */ + if( fmtSigned && (v & (0x80000000)) ) + { + v = ~v + 1; + sign = 1; + } + + /* Count digits, and get largest place value */ + vShrink = v; + p = 1; + digitCount = 1; + while( (vShrink = vShrink / fmtBase) > 0 ) + { + digitCount++; + p *= fmtBase; + } + + /* Print leading characters & sign */ + fmtBeforeDecimal -= digitCount; + if(fmtLeadingZero) + { + if(sign) + { + alt_log_txchar('-',(char*)base); + fmtBeforeDecimal--; + } + alt_log_repchar('0',fmtBeforeDecimal,base); + } + else + { + if(sign) + { + fmtBeforeDecimal--; + } + alt_log_repchar(' ',fmtBeforeDecimal,base); + if(sign) + { + alt_log_txchar('-',(char*)base); + } + } + + /* Print numbery parts */ + while(p) + { + unsigned char d; + + d = v / p; + d += '0'; + if(d > '9') + { + d += (fmtCase ? 'A' : 'a') - '0' - 10; + } + alt_log_txchar(d,(char*)base); + + v = v % p; + p = p / fmtBase; + } + } + + state = pfState_chars; + break; + + case 'u': + fmtSigned = 0; + goto doIntegerPrint; + case 'o': + fmtSigned = 0; + fmtBase = 8; + goto doIntegerPrint; + case 'x': + fmtSigned = 0; + fmtBase = 16; + goto doIntegerPrint; + case 'X': + fmtSigned = 0; + fmtBase = 16; + fmtCase = 1; + goto doIntegerPrint; + + case 'c': + alt_log_repchar(' ',fmtBeforeDecimal-1,base); + alt_log_txchar(va_arg(args,int),(char*)base); + break; + + case 's': + { + char *s; + + s = va_arg(args,char *); + alt_log_repchar(' ',fmtBeforeDecimal-strlen(s),base); + + while(*s) + alt_log_txchar(*s++,(char*)base); + } + break; + } /* switch last letter of fmt */ + state=pfState_chars; + } + break; + } /* switch */ + } /* while chars left */ + } /* printf */ + +/* Main logging printf function */ +int alt_log_printf_proc(const char *fmt, ... ) +{ + va_list args; + + va_start (args, fmt); + alt_log_private_printf(fmt,ALT_LOG_PORT_BASE,args); + return (0); +} + +/* Below are the functions called by different macros in various components. */ + +/* If the system has a JTAG_UART, include JTAG_UART debugging functions */ +#ifdef __ALTERA_AVALON_JTAG_UART + +/* The alarm function in altera_avalon_jtag_uart.c. + * This function, when turned on, prints out the status + * of the JTAG UART Control register, every ALT_LOG_JTAG_UART_TICKS. + * If the flag is off, the alarm should never be registered, and this + * function should never run */ +alt_u32 altera_avalon_jtag_uart_report_log(void * context) +{ + if (alt_log_jtag_uart_alarm_on_flag) { + altera_avalon_jtag_uart_state* dev = (altera_avalon_jtag_uart_state*) context; + const char* header="JTAG Alarm:"; + alt_log_jtag_uart_print_control_reg(dev, dev->base, header); + return ALT_LOG_JTAG_UART_TICKS; + } + else + { + /* If flag is not on, return 0 to disable future alarms. + * Should never be here, alarm should not be enabled at all. */ + return 0; + } +} + +void alt_log_jtag_uart_print_control_reg(altera_avalon_jtag_uart_state* dev, int base, const char* header) +{ + unsigned int control, space, ac, wi, ri, we, re; + control = IORD_ALTERA_AVALON_JTAG_UART_CONTROL(base); + space = (control & ALTERA_AVALON_JTAG_UART_CONTROL_WSPACE_MSK) >> + ALTERA_AVALON_JTAG_UART_CONTROL_WSPACE_OFST; + we= (control & ALTERA_AVALON_JTAG_UART_CONTROL_WE_MSK) >> + ALTERA_AVALON_JTAG_UART_CONTROL_WE_OFST; + re= (control & ALTERA_AVALON_JTAG_UART_CONTROL_RE_MSK) >> + ALTERA_AVALON_JTAG_UART_CONTROL_RE_OFST; + ri= (control & ALTERA_AVALON_JTAG_UART_CONTROL_RI_MSK) >> + ALTERA_AVALON_JTAG_UART_CONTROL_RI_OFST; + wi= (control & ALTERA_AVALON_JTAG_UART_CONTROL_WI_MSK) >> + ALTERA_AVALON_JTAG_UART_CONTROL_WI_OFST; + ac= (control & ALTERA_AVALON_JTAG_UART_CONTROL_AC_MSK) >> + ALTERA_AVALON_JTAG_UART_CONTROL_AC_OFST; + +#ifdef ALTERA_AVALON_JTAG_UART_SMALL + ALT_LOG_PRINTF( + "%s HW FIFO wspace=%d AC=%d WI=%d RI=%d WE=%d RE=%d\r\n", + header,space,ac,wi,ri,we,re); +#else + ALT_LOG_PRINTF( + "%s SW CirBuf = %d, HW FIFO wspace=%d AC=%d WI=%d RI=%d WE=%d RE=%d\r\n", + header,(dev->tx_out-dev->tx_in),space,ac,wi,ri,we,re); +#endif + + return; + +} + +/* In altera_avalon_jtag_uart.c + * Same output as the alarm function above, but this is called in the driver + * init function. Hence, it gives the status of the JTAG UART control register + * right at the initialization of the driver */ +void alt_log_jtag_uart_startup_info(altera_avalon_jtag_uart_state* dev, int base) +{ + const char* header="JTAG Startup Info:"; + alt_log_jtag_uart_print_control_reg(dev, base, header); + return; +} + +/* In altera_avalon_jtag_uart.c + * When turned on, this function will print out the status of the jtag uart + * control register every time there is a jtag uart "almost-empty" interrupt. */ +void alt_log_jtag_uart_isr_proc(int base, altera_avalon_jtag_uart_state* dev) +{ + if (alt_log_jtag_uart_isr_on_flag) { + const char* header="JTAG IRQ:"; + alt_log_jtag_uart_print_control_reg(dev, base, header); + } + return; +} + +#endif /* __ALTERA_AVALON_JTAG_UART */ + +/* In alt_write.c + * When the alt_log_write_on_flag is turned on, this function gets called + * every time alt_write gets called. The first + * ALT_LOG_WRITE_ECHO_LEN characters of every printf command (or any command + * that eventually calls write()) gets echoed to the alt_log output. */ +void alt_log_write(const void *ptr, size_t len) +{ + if (alt_log_write_on_flag) { + int temp_cnt; + int length=(ALT_LOG_WRITE_ECHO_LEN>len) ? len : ALT_LOG_WRITE_ECHO_LEN; + + if (length < 2) return; + + strncpy (alt_log_write_buf,ptr,length); + alt_log_write_buf[length-1]='\n'; + alt_log_write_buf[length]='\r'; + alt_log_write_buf[length+1]='\0'; + + /* Escape Ctrl-D's. If the Ctrl-D gets sent it might kill the terminal + * connection of alt_log. It will get replaced by 'D'. */ + for (temp_cnt=0;temp_cnt < length; temp_cnt++) { + if (alt_log_write_buf[temp_cnt]== 0x4) { + alt_log_write_buf[temp_cnt]='D'; + } + } + ALT_LOG_PRINTF("Write Echo: %s",alt_log_write_buf); + } +} + +/* In altera_avalon_timer_sc + * This function prints out a system clock is alive message + * every ALT_LOG_SYS_CLK_INTERVAL (in ticks). */ +void alt_log_system_clock() +{ + if (alt_log_sys_clk_on_flag) { + alt_log_sys_clk_count++; + if (alt_log_sys_clk_count > ALT_LOG_SYS_CLK_INTERVAL) { + alt_log_sys_clk_count = 0; + ALT_LOG_PRINTF("System Clock On %u\r\n",alt_system_clock_in_sec++); + } + } +} + + +#endif diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_lseek.c b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_lseek.c new file mode 100644 index 00000000..7857b0d6 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_lseek.c @@ -0,0 +1,117 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004-2005 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include + +#include "sys/alt_errno.h" +#include "sys/alt_warning.h" +#include "priv/alt_file.h" +#include "os/alt_syscall.h" + +#ifdef ALT_USE_DIRECT_DRIVERS + +off_t ALT_LSEEK (int file, off_t ptr, int dir) +{ + /* Generate a link time warning, should this function ever be called. */ + + ALT_STUB_WARNING(lseek); + + /* Indicate an error */ + + ALT_ERRNO = ENOSYS; + return -1; +} + +#else /* !ALT_USE_DIRECT_DRIVERS */ + +/* + * lseek() can be called to move the read/write pointer associated with the + * file descriptor "file". This function simply vectors the call to the lseek() + * function provided by the driver associated with the file descriptor. + * + * If the driver does not provide an implementation of lseek() an error is + * indicated. + * + * lseek() corresponds to the standard lseek() function. + * + * ALT_LSEEK is mapped onto the lseek() system call in alt_syscall.h + * + */ + +off_t ALT_LSEEK (int file, off_t ptr, int dir) +{ + alt_fd* fd; + off_t rc = 0; + + /* + * A common error case is that when the file descriptor was created, the call + * to open() failed resulting in a negative file descriptor. This is trapped + * below so that we don't try and process an invalid file descriptor. + */ + + fd = (file < 0) ? NULL : &alt_fd_list[file]; + + if (fd) + { + /* + * If the device driver provides an implementation of the lseek() function, + * then call that to process the request. + */ + + if (fd->dev->lseek) + { + rc = fd->dev->lseek(fd, ptr, dir); + } + /* + * Otherwise return an error. + */ + + else + { + rc = -ENOTSUP; + } + } + else + { + rc = -EBADFD; + } + + if (rc < 0) + { + ALT_ERRNO = -rc; + rc = -1; + } + + return rc; +} + +#endif /* ALT_USE_DIRECT_DRIVERS */ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_main.c b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_main.c new file mode 100644 index 00000000..a96229b3 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_main.c @@ -0,0 +1,161 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2007 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include +#include +#include +#include +#include +#include + +#include "sys/alt_dev.h" +#include "sys/alt_sys_init.h" +#include "sys/alt_irq.h" +#include "sys/alt_dev.h" + +#include "os/alt_hooks.h" + +#include "priv/alt_file.h" +#include "alt_types.h" + +#include "system.h" + +#include "sys/alt_log_printf.h" + +extern void _do_ctors(void); +extern void _do_dtors(void); + +/* + * Standard arguments for main. By default, no arguments are passed to main. + * However a device driver may choose to configure these arguments by calling + * alt_set_args(). The expectation is that this facility will only be used by + * the iclient/ihost utility. + */ + +int alt_argc = 0; +char** alt_argv = {NULL}; +char** alt_envp = {NULL}; + +/* + * Prototype for the entry point to the users application. + */ + +extern int main (int, char **, char **); + +/* + * alt_main is the C entry point for the HAL. It is called by the assembler + * startup code in the processor specific crt0.S. It is responsible for: + * completing the C runtime configuration; configuring all the + * devices/filesystems/components in the system; and call the entry point for + * the users application, i.e. main(). + */ + +void alt_main (void) +{ +#ifndef ALT_NO_EXIT + int result; +#endif + + /* ALT LOG - please see HAL/sys/alt_log_printf.h for details */ + ALT_LOG_PRINT_BOOT("[alt_main.c] Entering alt_main, calling alt_irq_init.\r\n"); + /* Initialize the interrupt controller. */ + alt_irq_init (NULL); + + /* Initialize the operating system */ + ALT_LOG_PRINT_BOOT("[alt_main.c] Done alt_irq_init, calling alt_os_init.\r\n"); + ALT_OS_INIT(); + + /* + * Initialize the semaphore used to control access to the file descriptor + * list. + */ + + ALT_LOG_PRINT_BOOT("[alt_main.c] Done OS Init, calling alt_sem_create.\r\n"); + ALT_SEM_CREATE (&alt_fd_list_lock, 1); + + /* Initialize the device drivers/software components. */ + ALT_LOG_PRINT_BOOT("[alt_main.c] Calling alt_sys_init.\r\n"); + alt_sys_init(); + ALT_LOG_PRINT_BOOT("[alt_main.c] Done alt_sys_init.\r\n"); + +#if !defined(ALT_USE_DIRECT_DRIVERS) && (defined(ALT_STDIN_PRESENT) || defined(ALT_STDOUT_PRESENT) || defined(ALT_STDERR_PRESENT)) + + /* + * Redirect stdio to the apropriate devices now that the devices have + * been initialized. This is only done if the user has requested these + * devices be present (not equal to /dev/null) and if direct drivers + * aren't being used. + */ + + ALT_LOG_PRINT_BOOT("[alt_main.c] Redirecting IO.\r\n"); + alt_io_redirect(ALT_STDOUT, ALT_STDIN, ALT_STDERR); +#endif + +#ifndef ALT_NO_C_PLUS_PLUS + /* + * Call the C++ constructors + */ + + ALT_LOG_PRINT_BOOT("[alt_main.c] Calling C++ constructors.\r\n"); + _do_ctors (); +#endif /* ALT_NO_C_PLUS_PLUS */ + +#if !defined(ALT_NO_C_PLUS_PLUS) && !defined(ALT_NO_CLEAN_EXIT) && !defined(ALT_NO_EXIT) + /* + * Set the C++ destructors to be called at system shutdown. This is only done + * if a clean exit has been requested (i.e. the exit() function has not been + * redefined as _exit()). This is in the interest of reducing code footprint, + * in that the atexit() overhead is removed when it's not needed. + */ + + ALT_LOG_PRINT_BOOT("[alt_main.c] Calling atexit.\r\n"); + atexit (_do_dtors); +#endif + + /* + * Finally, call main(). The return code is then passed to a subsequent + * call to exit() unless the application is never supposed to exit. + */ + + ALT_LOG_PRINT_BOOT("[alt_main.c] Calling main.\r\n"); + +#ifdef ALT_NO_EXIT + main (alt_argc, alt_argv, alt_envp); +#else + result = main (alt_argc, alt_argv, alt_envp); + close(STDOUT_FILENO); + exit (result); +#endif + + ALT_LOG_PRINT_BOOT("[alt_main.c] After main - we should not be here?.\r\n"); +} + diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_mcount.S b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_mcount.S new file mode 100644 index 00000000..38375230 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_mcount.S @@ -0,0 +1,198 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003-2010 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +/* mcount or _mcount is inserted by GCC before the function prologue of every + * function when a program is compiled for profiling. At the start of mcount, + * we guarantee that: + * ra = self_pc (an address in the function which called mcount) + * r8 = from_pc (an address in the function which called mcount's caller) + * + * Because this is always called at the start of a function we can corrupt + * r2,r3 and r11-r15. We must not corrupt r4-r7 (because they might contain + * function arguments for the instrumented function) or r8 (which holds ra + * for the instrumented function). + */ + + .global __mcount_fn_head + + .global mcount + + /* _mcount is used by gcc4 */ + .global _mcount + +_mcount: +mcount: + /* Use a hash to speed up locating fn_entry. We use bits 5 upwards to choose + * the bucket because bits 1:0 will always be 0, and because the distribution + * of values for bits 4:2 won't be even (aligning on cache line boundaries + * will skew it). Higher bits should be fairly random. + */ + /* fn_head = mcount_fn_head + (((unsigned int)self_pc >> 5) & (HASH_BUCKETS - 1)); */ + + srli r2, ra, 3 + movhi r3, %hiadj(__mcount_fn_head) + addi r3, r3, %lo(__mcount_fn_head) + andi r2, r2, 0xFC + add r11, r2, r3 + + /* The fast case is where we have already allocated a function arc, and so + * also a function pointer. + */ + + /* First find the function being called (using self_pc) */ + mov r10, r11 +0: + ldw r10, 0(r10) + beq r10, zero, .Lnew_arc + ldw r2, 4(r10) + bne r2, ra, 0b + + /* Found a function entry for this PC. Now look for an arc with a matching + * from_pc value. There will always be at least one arc. */ + ldw r3, 8(r10) +0: + ldw r2, 4(r3) + beq r2, r8, .Lfound_arc + ldw r3, 0(r3) + bne r3, zero, 0b + +.Lnew_arc: + addi sp, sp, -24 + +.LCFI0: + stw ra, 0(sp) + stw r4, 4(sp) + stw r5, 8(sp) + stw r6, 12(sp) + stw r7, 16(sp) + stw r8, 20(sp) + +.LCFI1: + /* __mcount_record(orig_ra, orig_r8, fn_entry, *fn_head); */ + mov r4, ra + mov r5, r8 + mov r6, r10 + mov r7, r11 + call __mcount_record + + /* restore registers from the stack */ + ldw ra, 0(sp) + ldw r4, 4(sp) + ldw r5, 8(sp) + ldw r6, 12(sp) + ldw r7, 16(sp) + ldw r8, 20(sp) + + addi sp, sp, 24 + +.LCFI2: + ret + +.Lfound_arc: + /* We've found the correct arc record. Increment the count and return */ + ldw r2, 8(r3) + addi r2, r2, 1 + stw r2, 8(r3) + ret + +.Lmcount_end: + + + +/* + * Dwarf2 debug information for the function. This provides GDB with the + * information it needs to backtrace out of this function. + */ + + .section .debug_frame,"",@progbits +.LCIE: + .4byte 2f - 1f /* Length */ +1: + .4byte 0xffffffff /* CIE id */ + .byte 0x1 /* Version */ + .string "" /* Augmentation */ + .uleb128 0x1 /* Code alignment factor */ + .sleb128 -4 /* Data alignment factor */ + .byte 0x1f /* Return address register */ + + .byte 0xc /* Define CFA */ + .uleb128 0x1b /* Register 27 (sp) */ + .uleb128 0x0 /* Offset 0 */ + + .align 2 /* Padding */ +2: + +.LFDE_mcount: + .4byte 2f - 1f /* Length */ +1: + .4byte .LCIE /* Pointer to CIE */ + .4byte mcount /* Start of table entry */ + .4byte .Lmcount_end - mcount /* Size of table entry */ + + .byte 0x4 /* Advance location */ + .4byte .LCFI0 - mcount /* to .LCFI0 */ + .byte 0xe /* Define CFA offset */ + .uleb128 24 /* to 24 */ + + .byte 0x4 /* Advance location */ + .4byte .LCFI1 - .LCFI0 /* to .LCFI1 */ + .byte 0x9f /* Store ra */ + .uleb128 0x6 /* at CFA-24 */ + .byte 0x84 /* Store r4 */ + .uleb128 0x5 /* at CFA-20 */ + .byte 0x85 /* Store r5 */ + .uleb128 0x4 /* at CFA-16 */ + .byte 0x86 /* Store r6 */ + .uleb128 0x3 /* at CFA-12 */ + .byte 0x87 /* Store r7 */ + .uleb128 0x2 /* at CFA-8 */ + .byte 0x88 /* Store r8 */ + .uleb128 0x1 /* at CFA-4 */ + + .byte 0x4 /* Advance location */ + .4byte .LCFI2 - .LCFI1 /* to .LCFI2 */ + .byte 0xe /* Define CFA offset */ + .uleb128 0 /* to 0 */ + .byte 0x8 /* Same value */ + .uleb128 31 /* for ra */ + .byte 0x8 /* Same value */ + .uleb128 4 /* for r4 */ + .byte 0x8 /* Same value */ + .uleb128 5 /* for r5 */ + .byte 0x8 /* Same value */ + .uleb128 6 /* for r6 */ + .byte 0x8 /* Same value */ + .uleb128 7 /* for r7 */ + .byte 0x8 /* Same value */ + .uleb128 8 /* for r8 */ + + .align 2 +2: + diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_open.c b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_open.c new file mode 100644 index 00000000..4790f538 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_open.c @@ -0,0 +1,173 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include "sys/alt_errno.h" +#include "sys/alt_warning.h" +#include "priv/alt_file.h" +#include "alt_types.h" +#include "os/alt_syscall.h" + +#ifdef ALT_USE_DIRECT_DRIVERS + +int ALT_OPEN (const char* file, int flags, int mode) +{ + /* Generate a link time warning, should this function ever be called. */ + + ALT_STUB_WARNING(open); + + /* Indicate an error */ + + ALT_ERRNO = ENOSYS; + return -1; +} + +#else /* !ALT_USE_DIRECT_DRIVERS */ + +extern alt_llist alt_dev_list; + +/* + * alt_file_locked() is used by open() to ensure that a device has not been + * previously locked for exclusive access using ioctl(). This test is only + * performed for devices. Filesystems are required to handle the ioctl() call + * themselves, and report the error from the filesystems open() function. + */ + +static int alt_file_locked (alt_fd* fd) +{ + alt_u32 i; + + /* + * Mark the file descriptor as belonging to a device. + */ + + fd->fd_flags |= ALT_FD_DEV; + + /* + * Loop through all current file descriptors searching for one that's locked + * for exclusive access. If a match is found, generate an error. + */ + + for (i = 0; i <= alt_max_fd; i++) + { + if ((alt_fd_list[i].dev == fd->dev) && + (alt_fd_list[i].fd_flags & ALT_FD_EXCL) && + (&alt_fd_list[i] != fd)) + { + return -EACCES; + } + } + + /* The device is not locked */ + + return 0; +} + +/* + * open() is called in order to get a file descriptor that reference the file + * or device named "name". This descriptor can then be used to manipulate the + * file/device using the standard system calls, e.g. write(), read(), ioctl() + * etc. + * + * This is equivalent to the standard open() system call. + * + * ALT_OPEN is mapped onto the open() system call in alt_syscall.h + */ + +int ALT_OPEN (const char* file, int flags, int mode) +{ + alt_dev* dev; + alt_fd* fd; + int index = -1; + int status = -ENODEV; + int isafs = 0; + + /* + * Check the device list, to see if a device with a matching name is + * registered. + */ + + if (!(dev = alt_find_dev (file, &alt_dev_list))) + { + /* No matching device, so try the filesystem list */ + + dev = alt_find_file (file); + isafs = 1; + } + + /* + * If a matching device or filesystem is found, allocate a file descriptor. + */ + + if (dev) + { + if ((index = alt_get_fd (dev)) < 0) + { + status = index; + } + else + { + fd = &alt_fd_list[index]; + fd->fd_flags = (flags & ~ALT_FD_FLAGS_MASK); + + /* If this is a device, ensure it isn't already locked */ + + if (isafs || ((status = alt_file_locked (fd)) >= 0)) + { + /* + * If the device or filesystem provides an open() callback function, + * call it now to perform any device/filesystem specific operations. + */ + + status = (dev->open) ? dev->open(fd, file, flags, mode): 0; + } + } + } + else + { + status = -ENODEV; + } + + /* Allocation failed, so clean up and return an error */ + + if (status < 0) + { + alt_release_fd (index); + ALT_ERRNO = -status; + return -1; + } + + /* return the reference upon success */ + + return index; +} + +#endif /* ALT_USE_DIRECT_DRIVERS */ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_printf.c b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_printf.c new file mode 100644 index 00000000..e742b57a --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_printf.c @@ -0,0 +1,127 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/* + * This file provides a very minimal printf implementation for use with very + * small applications. Only the following format strings are supported: + * %x + * %s + * %c + * %% + */ + +#include +#include "sys/alt_stdio.h" + +/* + * ALT printf function + */ +void +alt_printf(const char* fmt, ... ) +{ + va_list args; + va_start(args, fmt); + const char *w; + char c; + + /* Process format string. */ + w = fmt; + while ((c = *w++) != 0) + { + /* If not a format escape character, just print */ + /* character. Otherwise, process format string. */ + if (c != '%') + { + alt_putchar(c); + } + else + { + /* Get format character. If none */ + /* available, processing is complete. */ + if ((c = *w++) != 0) + { + if (c == '%') + { + /* Process "%" escape sequence. */ + alt_putchar(c); + } + else if (c == 'c') + { + int v = va_arg(args, int); + alt_putchar(v); + } + else if (c == 'x') + { + /* Process hexadecimal number format. */ + unsigned long v = va_arg(args, unsigned long); + unsigned long digit; + int digit_shift; + + /* If the number value is zero, just print and continue. */ + if (v == 0) + { + alt_putchar('0'); + continue; + } + + /* Find first non-zero digit. */ + digit_shift = 28; + while (!(v & (0xF << digit_shift))) + digit_shift -= 4; + + /* Print digits. */ + for (; digit_shift >= 0; digit_shift -= 4) + { + digit = (v & (0xF << digit_shift)) >> digit_shift; + if (digit <= 9) + c = '0' + digit; + else + c = 'a' + digit - 10; + alt_putchar(c); + } + } + else if (c == 's') + { + /* Process string format. */ + char *s = va_arg(args, char *); + + while(*s) + alt_putchar(*s++); + } + } + else + { + break; + } + } + } +} diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_putchar.c b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_putchar.c new file mode 100644 index 00000000..badaa02c --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_putchar.c @@ -0,0 +1,59 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include + +#ifdef ALT_USE_DIRECT_DRIVERS +#include "system.h" +#include "sys/alt_driver.h" +#include "sys/alt_stdio.h" +#endif + +/* + * Uses the ALT_DRIVER_WRITE() macro to call directly to driver if available. + * Otherwise, uses newlib provided putchar() routine. + */ +int +alt_putchar(int c) +{ +#ifdef ALT_USE_DIRECT_DRIVERS + ALT_DRIVER_WRITE_EXTERNS(ALT_STDOUT_DEV); + char c1 = (char)(c & 0xff); + + if (ALT_DRIVER_WRITE(ALT_STDOUT_DEV, &c1, 1, 0) == -1) { + return -1; + } + return c; +#else + return putchar(c); +#endif +} diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_putstr.c b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_putstr.c new file mode 100644 index 00000000..5345945c --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_putstr.c @@ -0,0 +1,55 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include + +#ifdef ALT_USE_DIRECT_DRIVERS +#include +#include "system.h" +#include "sys/alt_driver.h" +#include "sys/alt_stdio.h" +#endif + +/* + * Uses the ALT_DRIVER_WRITE() macro to call directly to driver if available. + * Otherwise, uses newlib provided fputs() routine. + */ +int +alt_putstr(const char* str) +{ +#ifdef ALT_USE_DIRECT_DRIVERS + ALT_DRIVER_WRITE_EXTERNS(ALT_STDOUT_DEV); + return ALT_DRIVER_WRITE(ALT_STDOUT_DEV, str, strlen(str), 0); +#else + return fputs(str, stdout); +#endif +} diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_read.c b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_read.c new file mode 100644 index 00000000..1c897771 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_read.c @@ -0,0 +1,125 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include +#include + +#include "sys/alt_errno.h" +#include "sys/alt_warning.h" +#include "priv/alt_file.h" +#include "os/alt_syscall.h" + +/* + * The read() system call is used to read a block of data from a file or device. + * This function simply vectors the request to the device driver associated + * with the input file descriptor "file". + * + * ALT_READ is mapped onto the read() system call in alt_syscall.h + */ + +#ifdef ALT_USE_DIRECT_DRIVERS + +#include "system.h" +#include "sys/alt_driver.h" + +/* + * Provide minimal version that just reads from the stdin device when provided. + */ + +int ALT_READ (int file, void *ptr, size_t len) +{ +#ifdef ALT_STDIN_PRESENT + ALT_DRIVER_READ_EXTERNS(ALT_STDIN_DEV); +#endif + +#if !defined(ALT_STDIN_PRESENT) + /* Generate a link time warning, should this function ever be called. */ + ALT_STUB_WARNING(read); +#endif + + switch (file) { +#ifdef ALT_STDIN_PRESENT + case 0: /* stdin file descriptor */ + return ALT_DRIVER_READ(ALT_STDIN_DEV, ptr, len, 0); +#endif /* ALT_STDIN_PRESENT */ + default: + ALT_ERRNO = EBADFD; + return -1; + } +} + +#else /* !ALT_USE_DIRECT_DRIVERS */ + +int ALT_READ (int file, void *ptr, size_t len) +{ + alt_fd* fd; + int rval; + + /* + * A common error case is that when the file descriptor was created, the call + * to open() failed resulting in a negative file descriptor. This is trapped + * below so that we don't try and process an invalid file descriptor. + */ + + fd = (file < 0) ? NULL : &alt_fd_list[file]; + + if (fd) + { + /* + * If the file has not been opened with read access, or if the driver does + * not provide an implementation of read(), generate an error. Otherwise + * call the drivers read() function to process the request. + */ + + if (((fd->fd_flags & O_ACCMODE) != O_WRONLY) && + (fd->dev->read)) + { + if ((rval = fd->dev->read(fd, ptr, len)) < 0) + { + ALT_ERRNO = -rval; + return -1; + } + return rval; + } + else + { + ALT_ERRNO = EACCES; + } + } + else + { + ALT_ERRNO = EBADFD; + } + return -1; +} + +#endif /* ALT_USE_DIRECT_DRIVERS */ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_release_fd.c b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_release_fd.c new file mode 100644 index 00000000..84733a78 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_release_fd.c @@ -0,0 +1,54 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include "sys/alt_dev.h" +#include "priv/alt_file.h" + +/* + * alt_release_fd() is called to free an allocated file descriptor. This is + * done by setting the device pointer in the file descriptor structure to zero. + * + * File descriptors correcponding to standard in, standard out and standard + * error cannont be released backed to the pool. They are always reserved. + */ + +void alt_release_fd (int fd) +{ + if (fd > 2) + { + alt_fd_list[fd].fd_flags = 0; + alt_fd_list[fd].dev = 0; + } +} + + + diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_remap_cached.c b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_remap_cached.c new file mode 100644 index 00000000..f61cb9c5 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_remap_cached.c @@ -0,0 +1,50 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003,2007 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include "sys/alt_cache.h" +#include "system.h" + +#ifdef NIOS2_MMU_PRESENT +/* Convert KERNEL region address to IO region address */ +#define BYPASS_DCACHE_MASK (0x1 << 29) +#else +/* Set bit 31 of address to bypass D-cache */ +#define BYPASS_DCACHE_MASK (0x1 << 31) +#endif + +/* + * Convert a pointer to a block of uncached memory, into a block of + * cached memory. + */ + +void* alt_remap_cached (volatile void* ptr, alt_u32 len) +{ + return (void*) (((alt_u32) ptr) & ~BYPASS_DCACHE_MASK); +} diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_remap_uncached.c b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_remap_uncached.c new file mode 100644 index 00000000..7ff6302f --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_remap_uncached.c @@ -0,0 +1,51 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003,2007 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include "sys/alt_cache.h" +#include "system.h" + +#ifdef NIOS2_MMU_PRESENT +/* Convert KERNEL region address to IO region address */ +#define BYPASS_DCACHE_MASK (0x1 << 29) +#else +/* Set bit 31 of address to bypass D-cache */ +#define BYPASS_DCACHE_MASK (0x1 << 31) +#endif + +/* + * Convert a pointer to a block of cached memory, into a block of + * uncached memory. + */ + +volatile void* alt_remap_uncached (void* ptr, alt_u32 len) +{ + alt_dcache_flush (ptr, len); + return (volatile void*) (((alt_u32) ptr) | BYPASS_DCACHE_MASK); +} diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_rename.c b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_rename.c new file mode 100644 index 00000000..48afac0f --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_rename.c @@ -0,0 +1,55 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include "sys/alt_errno.h" +#include "sys/alt_warning.h" +#include "os/alt_syscall.h" + +/* + * _rename() is used by newlib to rename an existing file. This is unsupported + * in the HAL environment. However a "do-nothing" implementation is still + * provied for newlib compatability. + * + * ALT_RENAME is mapped onto the _rename() system call in alt_syscall.h + */ + +int ALT_RENAME (char *existing, char *new) +{ + /* Generate a link time warning, should this function ever be called. */ + + ALT_STUB_WARNING(_rename); + + /* Indicate an error */ + + ALT_ERRNO = ENOSYS; + return -1; +} diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_sbrk.c b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_sbrk.c new file mode 100644 index 00000000..b8c3799e --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_sbrk.c @@ -0,0 +1,136 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include + +#include "os/alt_syscall.h" + +#include "sys/alt_irq.h" +#include "sys/alt_stack.h" + +#include "system.h" + +/* + * sbrk() is called to dynamically extend the data segment for the application. + * Thie input argument "incr" is the size of the block to allocate. + * + * This simple implementation does not perform any bounds checking. Memory will + * be allocated, even if the request region colides with the stack or overflows + * the available physical memory. + * + * ALT_SBRK is mapped onto the sbrk() system call in alt_syscall.h + * + * This function is called by the profiling code to allocate memory so must be + * safe if called from an interrupt context. It must also not be instrumented + * because that would lead to an infinate loop. + */ + +extern char __alt_heap_start[]; /* set by linker */ +extern char __alt_heap_limit[]; /* set by linker */ + +static char *heap_end = __alt_heap_start; + +#if defined(ALT_EXCEPTION_STACK) && defined(ALT_STACK_CHECK) +char * alt_exception_old_stack_limit = NULL; +#endif + +caddr_t ALT_SBRK (int incr) __attribute__ ((no_instrument_function )); + +caddr_t ALT_SBRK (int incr) +{ + alt_irq_context context; + char *prev_heap_end; + + context = alt_irq_disable_all(); + + /* Always return data aligned on a word boundary */ + heap_end = (char *)(((unsigned int)heap_end + 3) & ~3); + +#ifdef ALT_MAX_HEAP_BYTES + /* + * User specified a maximum heap size. Return -1 if it would + * be exceeded by this sbrk call. + */ + if (((heap_end + incr) - __alt_heap_start) > ALT_MAX_HEAP_BYTES) { + alt_irq_enable_all(context); + return (caddr_t)-1; + } +#else + if ((heap_end + incr) > __alt_heap_limit) { + alt_irq_enable_all(context); + return (caddr_t)-1; + } +#endif + + prev_heap_end = heap_end; + heap_end += incr; + +#ifdef ALT_STACK_CHECK + /* + * If the stack and heap are contiguous then extending the heap reduces the + * space available for the stack. If we are still using the default stack + * then adjust the stack limit to note this, while checking for stack + * pointer overflow. + * If the stack limit isn't pointing at the top of the heap then the code + * is using a different stack so none of this needs to be done. + */ + + if (alt_stack_limit() == prev_heap_end) + { + if (alt_stack_pointer() <= heap_end) + alt_report_stack_overflow(); + + alt_set_stack_limit(heap_end); + } + +#ifdef ALT_EXCEPTION_STACK + /* + * If we are executing from the exception stack then compare against the + * stack we switched away from as well. The exception stack is a fixed + * size so doesn't need to be checked. + */ + + if (alt_exception_old_stack_limit == prev_heap_end) + { + if (alt_exception_old_stack_limit <= heap_end) + alt_report_stack_overflow(); + + alt_exception_old_stack_limit = heap_end; + } +#endif + +#endif + + alt_irq_enable_all(context); + + return (caddr_t) prev_heap_end; +} diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_settod.c b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_settod.c new file mode 100644 index 00000000..59db0f8e --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_settod.c @@ -0,0 +1,96 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include +#include + +#include "sys/alt_errno.h" +#include "sys/alt_alarm.h" +#include "os/alt_syscall.h" + +/* + * "alt_timezone" and "alt_resettime" are the values of the the reset time and + * time zone set through the last call to settimeofday(). By default they are + * zero initialised. + */ + +extern struct timezone alt_timezone; +extern struct timeval alt_resettime; + +/* + * Macro defining the number of micoseconds in a second. + */ + +#define ALT_US (1000000) + + +/* + * settimeofday() can be called to calibrate the system clock, so that + * subsequent calls to gettimeofday() will return the elapsed "wall clock" + * time. + * + * This is done by updating the global structures "alt_resettime" and + * "alt_timezone" so that an immediate call to gettimeofday() would return + * the value specified by "t" and "tz". + * + * Warning: if this function is called concurrently with a call to + * gettimeofday(), the value returned by gettimeofday() will be unreliable. + * + * ALT_SETTIMEOFDAY is mapped onto the settimeofday() system call in + * alt_syscall.h + */ + +int ALT_SETTIMEOFDAY (const struct timeval *t, + const struct timezone *tz) +{ + alt_u32 nticks = alt_nticks (); + alt_u32 tick_rate = alt_ticks_per_second (); + + /* If there is a system clock available, update the current time */ + + if (tick_rate) + { + alt_resettime.tv_sec = t->tv_sec - nticks/tick_rate; + alt_resettime.tv_usec = t->tv_usec - + ((nticks*(ALT_US/tick_rate))%ALT_US); + + alt_timezone.tz_minuteswest = tz->tz_minuteswest; + alt_timezone.tz_dsttime = tz->tz_dsttime; + + return 0; + } + + /* There's no system clock available */ + + ALT_ERRNO = ENOSYS; + return -1; +} diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_software_exception.S b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_software_exception.S new file mode 100644 index 00000000..21425944 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_software_exception.S @@ -0,0 +1,53 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003-2005 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + + /* + * This file provides the global symbol: software_exception. It is provided to + * support legacy code, and should not be used by new software. + * + * It is used by legacy code to invoke the software exception handler as + * defined by version 1.0 of the Nios II kit. It should only be used when you + * are providing your own interrupt entry point, i.e. you are not using + * alt_irq_entry. + */ + +#include "system.h" + + /* + * Pull in the exception handler. + */ + + .globl alt_exception + + .section .exceptions.entry.label, "xa" + + .globl software_exception + .type software_exception, @function +software_exception: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_stat.c b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_stat.c new file mode 100644 index 00000000..44e207b8 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_stat.c @@ -0,0 +1,59 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include +#include +#include +#include + +#include "os/alt_syscall.h" + +/* + * The stat() function is similar to the fstat() function in that it is used to + * obtain status information about a file. Instead of using an open file + * descriptor (like fstat()), stat() takes the name of a file as an input + * argument. + * + * ALT_STAT is mapped onto the stat() system call in alt_syscall.h + */ + +int ALT_STAT (const char *file, struct stat *st) +{ + int fd; + int rc; + + fd = open (file, 0); + rc = fstat (fd, st); + close (fd); + + return rc; +} diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_tick.c b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_tick.c new file mode 100644 index 00000000..c73488df --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_tick.c @@ -0,0 +1,149 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include "sys/alt_irq.h" +#include "sys/alt_alarm.h" +#include "os/alt_hooks.h" +#include "alt_types.h" + +/* + * "_alt_tick_rate" is used to store the value of the system clock frequency + * in ticks per second. It is initialised to zero, which corresponds to there + * being no system clock facility available. + */ + +alt_u32 _alt_tick_rate = 0; + +/* + * "_alt_nticks" is the number of system clock ticks that have elapsed since + * reset. + */ + +volatile alt_u32 _alt_nticks = 0; + +/* + * "alt_alarm_list" is the head of a linked list of registered alarms. This is + * initialised to be an empty list. + */ + +ALT_LLIST_HEAD(alt_alarm_list); + +/* + * alt_alarm_stop() is called to remove an alarm from the list of registered + * alarms. Alternatively an alarm can unregister itself by returning zero when + * the alarm executes. + */ + +void alt_alarm_stop (alt_alarm* alarm) +{ + alt_irq_context irq_context; + + irq_context = alt_irq_disable_all(); + alt_llist_remove (&alarm->llist); + alt_irq_enable_all (irq_context); +} + +/* + * alt_tick() is periodically called by the system clock driver in order to + * process the registered list of alarms. Each alarm is registed with a + * callback interval, and a callback function, "callback". + * + * The return value of the callback function indicates how many ticks are to + * elapse until the next callback. A return value of zero indicates that the + * alarm should be deactivated. + * + * alt_tick() is expected to run at interrupt level. + */ + +void alt_tick (void) +{ + alt_alarm* next; + alt_alarm* alarm = (alt_alarm*) alt_alarm_list.next; + + alt_u32 next_callback; + + /* update the tick counter */ + + _alt_nticks++; + + /* process the registered callbacks */ + + while (alarm != (alt_alarm*) &alt_alarm_list) + { + next = (alt_alarm*) alarm->llist.next; + + /* + * Upon the tick-counter rolling over it is safe to clear the + * roll-over flag; once the flag is cleared this (or subsequnt) + * tick events are enabled to generate an alarm event. + */ + if ((alarm->rollover) && (_alt_nticks == 0)) + { + alarm->rollover = 0; + } + + /* if the alarm period has expired, make the callback */ + if ((alarm->time <= _alt_nticks) && (alarm->rollover == 0)) + { + next_callback = alarm->callback (alarm->context); + + /* deactivate the alarm if the return value is zero */ + + if (next_callback == 0) + { + alt_alarm_stop (alarm); + } + else + { + alarm->time += next_callback; + + /* + * If the desired alarm time causes a roll-over, set the rollover + * flag. This will prevent the subsequent tick event from causing + * an alarm too early. + */ + if(alarm->time < _alt_nticks) + { + alarm->rollover = 1; + } + } + } + alarm = next; + } + + /* + * Update the operating system specific timer facilities. + */ + + ALT_OS_TIME_TICK(); +} + diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_times.c b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_times.c new file mode 100644 index 00000000..4dd965d4 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_times.c @@ -0,0 +1,71 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include + +#include "sys/alt_errno.h" +#include "sys/alt_alarm.h" +#include "os/alt_syscall.h" + +/* + * The times() function is used by newlib to obtain elapsed time information. + * The return value is the elapsed time since reset in system clock ticks. Note + * that this is distinct from the strict Posix version of times(), which should + * return the time since: 0 hours, 0 minutes, 0 seconds, January 1, 1970, GMT. + * + * The input structure is filled in with time accounting information. This + * implementation attributes all cpu time to the system. + * + * ALT_TIMES is mapped onto the times() system call in alt_syscall.h + */ + +clock_t ALT_TIMES (struct tms *buf) +{ + clock_t ticks = alt_nticks(); + + /* If there is no system clock present, generate an error */ + + if (!alt_ticks_per_second()) + { + ALT_ERRNO = ENOSYS; + return 0; + } + + /* Otherwise return the elapsed time */ + + buf->tms_utime = 0; + buf->tms_stime = ticks; + buf->tms_cutime = 0; + buf->tms_cstime = 0; + + return ticks; +} diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_uncached_free.c b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_uncached_free.c new file mode 100644 index 00000000..6e362baf --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_uncached_free.c @@ -0,0 +1,49 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003,2007 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include "sys/alt_cache.h" +#include "system.h" + +#ifdef NIOS2_MMU_PRESENT +/* Convert KERNEL region address to IO region address */ +#define BYPASS_DCACHE_MASK (0x1 << 29) +#else +/* Set bit 31 of address to bypass D-cache */ +#define BYPASS_DCACHE_MASK (0x1 << 31) +#endif + +/* + * Free a block of uncached memory. + */ + +void alt_uncached_free (volatile void* ptr) +{ + free ((void*) (((alt_u32) ptr) & ~BYPASS_DCACHE_MASK)); +} diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_uncached_malloc.c b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_uncached_malloc.c new file mode 100644 index 00000000..ab3416d2 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_uncached_malloc.c @@ -0,0 +1,55 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003,2007 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include "sys/alt_cache.h" +#include "system.h" + +#ifdef NIOS2_MMU_PRESENT +/* Convert KERNEL region address to IO region address */ +#define BYPASS_DCACHE_MASK (0x1 << 29) +#else +/* Set bit 31 of address to bypass D-cache */ +#define BYPASS_DCACHE_MASK (0x1 << 31) +#endif + +/* + * Allocate a block of uncached memory. + */ + +volatile void* alt_uncached_malloc (size_t size) +{ + void* ptr; + + ptr = malloc (size); + + alt_dcache_flush (ptr, size); + + return ptr ? (volatile void*) (((alt_u32) ptr) | BYPASS_DCACHE_MASK) : NULL; +} diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_unlink.c b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_unlink.c new file mode 100644 index 00000000..29e35d6c --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_unlink.c @@ -0,0 +1,55 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include "sys/alt_errno.h" +#include "sys/alt_warning.h" +#include "os/alt_syscall.h" + +/* + * unlink() is used by newlib to delete an existing link to a file. This is + * unsupported in the HAL environment. However a "do-nothing" implementation + * is still provied for newlib compatability. + * + * ALT_UNLINK is mapped onto the unlink() system call in alt_syscall.h + */ + +int ALT_UNLINK (char *name) +{ + /* Generate a link time warning, should this function ever be called. */ + + ALT_STUB_WARNING(unlink); + + /* Indicate an error */ + + ALT_ERRNO = ENOSYS; + return -1; +} diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_usleep.c b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_usleep.c new file mode 100644 index 00000000..9e946210 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_usleep.c @@ -0,0 +1,104 @@ +/* + * Copyright (c) 2003 Altera Corporation, San Jose, California, USA. + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * ------------ + * + * Altera does not recommend, suggest or require that this reference design + * file be used in conjunction or combination with any other product. + */ + +#include +#include +#include + +#include "sys/alt_alarm.h" +#include "priv/alt_busy_sleep.h" +#include "os/alt_syscall.h" + +#include "includes.h" + +/* + * Macro defining the number of micoseconds in a second. + */ + +#define ALT_US (1000000) + +/* + * This implementation of usleep overrides the default provided in the HAL/src + * directory of the altera_nios2 component. When possible, this + * implementation uses the uC/OS-II OSTimeDly function to block the current + * thread, rather than using a busy loop. This allows other threads to execute + * while the current thread is sleeping. + * + * ALT_USLEEP is mapped onto the usleep() system call in alt_syscall.h + */ + +#if defined (__GNUC__) && __GNUC__ >= 4 +int ALT_USLEEP (useconds_t us) +#else +unsigned int ALT_USLEEP (unsigned int us) +#endif +{ + alt_u32 ticks; + alt_u32 tick_rate; + + /* + * If the O/S hasn't started yet, then we delay using a busy loop, rather than + * OSTimeDly (since this would fail). The use of a busy loop is acceptable, + * since the system is still running in a single-threaded mode. + */ + + if (OSRunning == OS_FALSE) + { + return alt_busy_sleep (us); + } + + /* + * Calculate the number of whole system clock ticks to delay. + */ + + tick_rate = alt_ticks_per_second (); + ticks = (us/ALT_US)* tick_rate + ((us%ALT_US)*tick_rate)/ALT_US; + + /* + * OSTimeDly can only delay for a maximum of 0xffff ticks, so if the requested + * delay is greater than that, we need to break it down into a number of + * seperate delays. + */ + + while (ticks > 0xffff) + { + OSTimeDly(0xffff); + ticks -= 0xffff; + } + + OSTimeDly ((INT16U) (ticks)); + + /* + * Now delay by the remainder using a busy loop. This is here in order to + * provide very short delays of less than one clock tick. + */ + + alt_busy_sleep (us%(ALT_US/tick_rate)); + + return 0; +} diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_wait.c b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_wait.c new file mode 100644 index 00000000..a42f80ff --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_wait.c @@ -0,0 +1,52 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include "sys/alt_errno.h" +#include "os/alt_syscall.h" + +/* + * wait() is used by newlib to wait for all child processes to exit. Since the + * HAL does not support spawning child processes, this returns immediately as + * there can't be anythign to wait for. + * + * ALT_WAIT is mapped onto the wait() system call in alt_syscall.h + */ + +int ALT_WAIT (int *status) +{ + *status = 0; + + ALT_ERRNO = ECHILD; + + return -1; +} + diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_write.c b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_write.c new file mode 100644 index 00000000..51debb57 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/alt_write.c @@ -0,0 +1,138 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include +#include + +#include "sys/alt_errno.h" +#include "sys/alt_warning.h" +#include "priv/alt_file.h" +#include "os/alt_syscall.h" + +#include "sys/alt_log_printf.h" + +/* + * The write() system call is used to write a block of data to a file or + * device. This function simply vectors the request to the device driver + * associated with the input file descriptor "file". + * + * ALT_WRITE is mapped onto the write() system call in alt_syscall.h + */ + +#ifdef ALT_USE_DIRECT_DRIVERS + +#include "system.h" +#include "sys/alt_driver.h" + +/* + * Provide minimal version that just writes to the stdout/stderr devices + * when provided. + */ + +int ALT_WRITE (int file, const void *ptr, size_t len) +{ +#ifdef ALT_STDOUT_PRESENT + ALT_DRIVER_WRITE_EXTERNS(ALT_STDOUT_DEV); +#endif +#ifdef ALT_STDERR_PRESENT + ALT_DRIVER_WRITE_EXTERNS(ALT_STDERR_DEV); +#endif + +#if !defined(ALT_STDOUT_PRESENT) && !defined(ALT_STDERR_PRESENT) + /* Generate a link time warning, should this function ever be called. */ + ALT_STUB_WARNING(write); +#endif + + switch (file) { +#ifdef ALT_STDOUT_PRESENT + case 1: /* stdout file descriptor */ + return ALT_DRIVER_WRITE(ALT_STDOUT_DEV, ptr, len, 0); +#endif /* ALT_STDOUT_PRESENT */ +#ifdef ALT_STDERR_PRESENT + case 2: /* stderr file descriptor */ + return ALT_DRIVER_WRITE(ALT_STDERR_DEV, ptr, len, 0); +#endif /* ALT_STDERR_PRESENT */ + default: + ALT_ERRNO = EBADFD; + return -1; + } +} + +#else /* !ALT_USE_DIRECT_DRIVERS */ + +int ALT_WRITE (int file, const void *ptr, size_t len) +{ + alt_fd* fd; + int rval; + + /* + * A common error case is that when the file descriptor was created, the call + * to open() failed resulting in a negative file descriptor. This is trapped + * below so that we don't try and process an invalid file descriptor. + */ + + fd = (file < 0) ? NULL : &alt_fd_list[file]; + + if (fd) + { + /* + * If the file has not been opened with write access, or if the driver does + * not provide an implementation of write(), generate an error. Otherwise + * call the drivers write() function to process the request. + */ + + if (((fd->fd_flags & O_ACCMODE) != O_RDONLY) && fd->dev->write) + { + + /* ALT_LOG - see altera_hal/HAL/inc/sys/alt_log_printf.h */ + ALT_LOG_WRITE_FUNCTION(ptr,len); + + if ((rval = fd->dev->write(fd, ptr, len)) < 0) + { + ALT_ERRNO = -rval; + return -1; + } + return rval; + } + else + { + ALT_ERRNO = EACCES; + } + } + else + { + ALT_ERRNO = EBADFD; + } + return -1; +} + +#endif /* ALT_USE_DIRECT_DRIVERS */ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/altera_nios2_qsys_irq.c b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/altera_nios2_qsys_irq.c new file mode 100644 index 00000000..c7a4f93e --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/altera_nios2_qsys_irq.c @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2009 Altera Corporation, San Jose, California, USA. + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * altera_nios2_irq.c - Support for Nios II internal interrupt controller. + * + */ + +#include "sys/alt_irq.h" +#include "altera_nios2_qsys_irq.h" + +/* + * To initialize the internal interrupt controller, just clear the IENABLE + * register so that all possible IRQs are disabled. + */ +void altera_nios2_qsys_irq_init(void) +{ + NIOS2_WRITE_IENABLE(0); +} diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/crt0.S b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/crt0.S new file mode 100644 index 00000000..582445d6 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/crt0.S @@ -0,0 +1,456 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include "system.h" +#include "nios2.h" + +/* Setup header files to work with assembler code. */ +#define ALT_ASM_SRC + +/* Debug logging facility */ +#include "sys/alt_log_printf.h" + +/*************************************************************************\ +| MACROS | +\*************************************************************************/ + +/* + * The new build tools explicitly define macros when alt_load() + * must be called. The define ALT_LOAD_EXPLICITLY_CONTROLLED tells us that + * those macros are controlling if alt_load() needs to be called. + */ +#ifdef ALT_LOAD_EXPLICITLY_CONTROLLED + +/* Need to call alt_load() if any of these sections are being copied. */ +#if defined(ALT_LOAD_COPY_RODATA) || defined(ALT_LOAD_COPY_RWDATA) || defined(ALT_LOAD_COPY_EXCEPTIONS) +#define CALL_ALT_LOAD +#endif + +#else /* !ALT_LOAD_EXPLICITLY_CONTROLLED */ + +/* + * The legacy build tools use the following macros to detect when alt_load() + * needs to be called. + */ + +#define __ALT_LOAD_SECTIONS(res, text, rodata, exc) \ + ((res##_BASE != rodata##_BASE) || \ + (res##_BASE != rwdata##_BASE) || \ + (res##_BASE != exc##_BASE)) + +#define _ALT_LOAD_SECTIONS(res, text, rodata, exc) \ + __ALT_LOAD_SECTIONS(res, text, rodata, exc) + +#define ALT_LOAD_SECTIONS _ALT_LOAD_SECTIONS(ALT_RESET_DEVICE, \ + ALT_RODATA_DEVICE, \ + ALT_RWDATA_DEVICE, \ + ALT_EXCEPTIONS_DEVICE) + +/* Call alt_load() if there is no bootloader and ALT_LOAD_SECTIONS isn't 0. */ +#if defined(ALT_NO_BOOTLOADER) && ALT_LOAD_SECTIONS +#define CALL_ALT_LOAD +#endif + +#endif /* !ALT_LOAD_EXPLICITLY_CONTROLLED */ + +/* + * When the legacy build tools define a macro called ALT_NO_BOOTLOADER, + * it indicates that initialization code is allowed at the reset address. + * The new build tools define a macro called ALT_ALLOW_CODE_AT_RESET for + * the same purpose. + */ +#ifdef ALT_NO_BOOTLOADER +#define ALT_ALLOW_CODE_AT_RESET +#endif + +/*************************************************************************\ +| EXTERNAL REFERENCES | +\*************************************************************************/ + +/* + * The entry point for user code is either "main" in hosted mode, or + * "alt_main" in standalone mode. These are explicitly referenced here, + * to ensure they are built into the executable. This allows the user + * to build them into libraries, rather than supplying them in object + * files at link time. + */ + .globl main + .globl alt_main + +/* + * Create a reference to the software multiply/divide and trap handers, + * so that if they are provided, they will appear in the executable. + */ +#ifndef ALT_NO_INSTRUCTION_EMULATION + .globl alt_exception_muldiv +#endif +#ifdef ALT_TRAP_HANDLER + .globl alt_exception_trap +#endif + +/* + * Linker defined symbols used to initialize bss. + */ +.globl __bss_start +.globl __bss_end + +/*************************************************************************\ +| RESET SECTION (.entry) | +\*************************************************************************/ + +/* + * This is the reset entry point for Nios II. + * + * At reset, only the cache line which contain the reset vector is + * initialized by the hardware. The code within the first cache line + * initializes the remainder of the instruction cache. + */ + + .section .entry, "xa" + .align 5 + +/* + * Explicitly allow the use of r1 (the assembler temporary register) + * within this code. This register is normally reserved for the use of + * the assembler. + */ + .set noat + +/* + * Some tools want to know where the reset vector is. + * Code isn't always provided at the reset vector but at least the + * __reset label always contains the reset vector address because + * it is defined at the start of the .entry section. + */ + + .globl __reset + .type __reset, @function +__reset: + +/* + * Initialize the instruction cache if present (i.e. size > 0) and + * reset code is allowed unless optimizing for RTL simulation. + * RTL simulations can ensure the instruction cache is already initialized + * so skipping this loop speeds up RTL simulation. + */ + +#if NIOS2_ICACHE_SIZE > 0 && defined(ALT_ALLOW_CODE_AT_RESET) && !defined(ALT_SIM_OPTIMIZE) + /* Assume the instruction cache size is always a power of two. */ +#if NIOS2_ICACHE_SIZE > 0x8000 + movhi r2, %hi(NIOS2_ICACHE_SIZE) +#else + movui r2, NIOS2_ICACHE_SIZE +#endif + +0: + initi r2 + addi r2, r2, -NIOS2_ICACHE_LINE_SIZE + bgt r2, zero, 0b +1: + + /* + * The following debug information tells the ISS not to run the loop above + * but to perform its actions using faster internal code. + */ + .pushsection .debug_alt_sim_info + .int 1, 1, 0b, 1b + .popsection +#endif /* Initialize Instruction Cache */ + +/* + * Jump to the _start entry point in the .text section if reset code + * is allowed or if optimizing for RTL simulation. + */ +#if defined(ALT_ALLOW_CODE_AT_RESET) || defined(ALT_SIM_OPTIMIZE) + /* Jump to the _start entry point in the .text section. */ + movhi r1, %hi(_start) + ori r1, r1, %lo(_start) + jmp r1 + + .size __reset, . - __reset +#endif /* Jump to _start */ + +/* + * When not using exit, provide an _exit symbol to prevent unresolved + * references to _exit from the linker script. + */ +#ifdef ALT_NO_EXIT + .globl _exit +_exit: +#endif + +/*************************************************************************\ +| TEXT SECTION (.text) | +\*************************************************************************/ + +/* + * Start of the .text section, and also the code entry point when + * the code is executed by a bootloader rather than directly from reset. + */ + .section .text + .align 2 + + .globl _start + .type _start, @function +_start: + +/* + * Initialize the data cache if present (i.e. size > 0) and not + * optimizing for RTL simulation. + * RTL simulations can ensure the data cache is already initialized + * so skipping this loop speeds up RTL simulation. + */ + +#if NIOS2_DCACHE_SIZE > 0 && !defined(ALT_SIM_OPTIMIZE) + + /* Assume the data cache size is always a power of two. */ +#if NIOS2_DCACHE_SIZE > 0x8000 + movhi r2, %hi(NIOS2_DCACHE_SIZE) +#else + movui r2, NIOS2_DCACHE_SIZE +#endif + +0: + initd 0(r2) + addi r2, r2, -NIOS2_DCACHE_LINE_SIZE + bgt r2, zero, 0b +1: + + /* + * The following debug information tells the ISS not to run the loop above + * but to perform its actions using faster internal code. + */ + .pushsection .debug_alt_sim_info + .int 2, 1, 0b, 1b + .popsection + +#endif /* Initialize Data Cache */ + + /* Log that caches have been initialized. */ + ALT_LOG_PUTS(alt_log_msg_cache) + + /* Log that the stack pointer is about to be setup. */ + ALT_LOG_PUTS(alt_log_msg_stackpointer) + +#if (NIOS2_NUM_OF_SHADOW_REG_SETS == 0) + /* + * Now that the caches are initialized, set up the stack pointer. + * The value provided by the linker is assumed to be correctly aligned. + */ + movhi sp, %hi(__alt_stack_pointer) + ori sp, sp, %lo(__alt_stack_pointer) + + /* Set up the global pointer. */ + movhi gp, %hi(_gp) + ori gp, gp, %lo(_gp) + +#else /* NIOS2_NUM_OF_SHADOW_REG_SETS > 0 */ + + /* + * Set up the GP and SP in all shadow register sets. + */ + + /* + * Check current register set number, if CPU resets into a shadow register + * set, switch register set to 0 by writing zero to SSTATUS register and + * execute an ERET instruction that just jumps to the next PC address + * (use the NEXTPC instruction to get this). + */ + + rdctl r2, status + + /* Get the current register set number (STATUS.CRS). */ + andi r3, r2, NIOS2_STATUS_CRS_MSK + + /* Skip switch register set if STATUS.CRS is 0. */ + beq r3, zero, .Lskip_switch_reg_set + + .set nobreak + + /* Current register set is non-zero, set SSTATUS to 0. */ + mov sstatus, zero + + /* Get next pc and store in ea. */ + nextpc ea + + /* Point to instruction after eret. */ + addi ea, ea, 8 + + /* + * Execute ERET instruction that just jumps to the next PC address + */ + eret + +.Lskip_switch_reg_set: + mov r2, zero + + /* Reset STATUS register */ + wrctl status, r2 + + movui r3, NIOS2_NUM_OF_SHADOW_REG_SETS + + /* Set up the stack pointer in register set 0. */ + movhi sp, %hi(__alt_stack_pointer) + ori sp, sp, %lo(__alt_stack_pointer) + + /* Set up the global pointer in register set 0. */ + movhi gp, %hi(_gp) + ori gp, gp, %lo(_gp) + +.Lsetup_sp_and_gp_loop: + /* + * Setup GP and SP for shadow register set + * from NIOS2_NUM_OF_SHADOW_REG_SETS to 0 + */ + + /* Skip if number of register sets is 0. */ + beq r3, zero, .Lno_shadow_register_set + + + /* Add previous register set STATUS.PRS by 1 */ + movhi r4, 1 + add r2, r2, r4 + + /* Write STATUS */ + wrctl status, r2 + + /* Clear r0 in the shadow register set (not done by hardware) */ + wrprs r0, r0 + + /* Write the GP in previous register set */ + wrprs gp, gp + + /* Only write the SP in previous register set + * if using the seperate exception stack. For normal case (single stack), + * funnel code would read the SP from previous register set. + */ +#ifdef ALT_INTERRUPT_STACK + + movhi et, %hiadj(__alt_interrupt_stack_pointer) + addi et, et, %lo(__alt_interrupt_stack_pointer) + wrprs sp, et + +#endif /* ALT_INTERRUPT_STACK */ + + /* Decrease number of register set counter by 1 */ + addi r3, r3, -1 + + br .Lsetup_sp_and_gp_loop +.Lno_shadow_register_set: + +#endif /* NIOS2_NUM_OF_SHADOW_REG_SETS */ +/* + * Clear the BSS if not optimizing for RTL simulation. + * + * This uses the symbols: __bss_start and __bss_end, which are defined + * by the linker script. They mark the begining and the end of the bss + * region. The linker script guarantees that these values are word aligned. + */ +#ifndef ALT_SIM_OPTIMIZE + /* Log that the BSS is about to be cleared. */ + ALT_LOG_PUTS(alt_log_msg_bss) + + movhi r2, %hi(__bss_start) + ori r2, r2, %lo(__bss_start) + + movhi r3, %hi(__bss_end) + ori r3, r3, %lo(__bss_end) + + beq r2, r3, 1f + +0: + stw zero, (r2) + addi r2, r2, 4 + bltu r2, r3, 0b + +1: + + /* + * The following debug information tells the ISS not to run the loop above + * but to perform its actions using faster internal code. + */ + .pushsection .debug_alt_sim_info + .int 3, 1, 0b, 1b + .popsection +#endif /* ALT_SIM_OPTIMIZE */ + +/* + * The alt_load() facility is normally used when there is no bootloader. + * It copies some sections into RAM so it acts like a mini-bootloader. + */ +#ifdef CALL_ALT_LOAD + +#ifdef ALT_STACK_CHECK + /* + * If the user has selected stack checking then we need to set up a safe + * value in the stack limit register so that the relocation functions + * don't think the stack has overflowed (the contents of the rwdata + * section aren't defined until alt_load() has been called). + */ + mov et, zero +#endif + + call alt_load + +#endif /* CALL_ALT_LOAD */ + +#ifdef ALT_STACK_CHECK + /* + * Set up the stack limit (if required). The linker has set up the + * copy of the variable which is in memory. + */ + + ldw et, %gprel(alt_stack_limit_value)(gp) +#endif + + /* Log that alt_main is about to be called. */ + ALT_LOG_PUTS(alt_log_msg_alt_main) + + /* Call the C entry point. It should never return. */ + call alt_main + + /* Wait in infinite loop in case alt_main does return. */ +alt_after_alt_main: + br alt_after_alt_main + + .size _start, . - _start + +/* + * Add information about the stack base if stack overflow checking is enabled. + */ +#ifdef ALT_STACK_CHECK + .globl alt_stack_limit_value + .section .sdata,"aws",@progbits + .align 2 + .type alt_stack_limit_value, @object + .size alt_stack_limit_value, 4 +alt_stack_limit_value: + .long __alt_stack_limit +#endif diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/os_cpu_a.S b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/os_cpu_a.S new file mode 100644 index 00000000..7219fb77 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/os_cpu_a.S @@ -0,0 +1,270 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2009 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +/********************************************************************************************************* + * uC/OS-II + * The Real-Time Kernel + * File : os_cpu_a.S + * For : uC/OS Real-time multitasking kernel for the Nios2 SoftCore Processor + * Written by : IS + * + *********************************************************************************************************/ + +#include "os_cfg.h" + + .text + +/********************************************************************************************************* + * PERFORM A CONTEXT SWITCH + * void OSCtxSw(void) - from task level + * void OSIntCtxSw(void) - from interrupt level + * + * Note(s): 1) Upon entry, + * OSTCBCur points to the OS_TCB of the task to suspend + * OSTCBHighRdy points to the OS_TCB of the task to resume + * + *********************************************************************************************************/ + .global OSIntCtxSw + .global OSCtxSw + +OSIntCtxSw: +OSCtxSw: + + /* + * Save the remaining registers to the stack. + */ + + addi sp, sp, -44 + +#ifdef ALT_STACK_CHECK + + bltu sp, et, .Lstack_overflow + +#endif + +#if OS_THREAD_SAFE_NEWLIB + ldw r3, %gprel(_impure_ptr)(gp) /* load the pointer */ +#endif /* OS_THREAD_SAFE_NEWLIB */ + + ldw r4, %gprel(OSTCBCur)(gp) + + stw ra, 0(sp) + stw fp, 4(sp) + stw r23, 8(sp) + stw r22, 12(sp) + stw r21, 16(sp) + stw r20, 20(sp) + stw r19, 24(sp) + stw r18, 28(sp) + stw r17, 32(sp) + stw r16, 36(sp) + +#if OS_THREAD_SAFE_NEWLIB + /* + * store the current value of _impure_ptr so it can be restored + * later; _impure_ptr is asigned on a per task basis. It is used + * by Newlib to achieve reentrancy. + */ + + stw r3, 40(sp) /* save the impure pointer */ +#endif /* OS_THREAD_SAFE_NEWLIB */ + + /* + * Save the current tasks stack pointer into the current tasks OS_TCB. + * i.e. OSTCBCur->OSTCBStkPtr = sp; + */ + + stw sp, (r4) /* save the stack pointer (OSTCBStkPtr */ + /* is the first element in the OS_TCB */ + /* structure. */ + + /* + * Call the user definable OSTaskSWHook() + */ + + call OSTaskSwHook + +0: + +9: + + /* + * OSTCBCur = OSTCBHighRdy; + * OSPrioCur = OSPrioHighRdy; + */ + + ldw r4, %gprel(OSTCBHighRdy)(gp) + ldb r5, %gprel(OSPrioHighRdy)(gp) + + stw r4, %gprel(OSTCBCur)(gp) /* set the current task to be the new task */ + stb r5, %gprel(OSPrioCur)(gp) /* store the new task's priority as the current */ + /* task's priority */ + + /* + * Set the stack pointer to point to the new task's stack + */ + + ldw sp, (r4) /* the stack pointer is the first entry in the OS_TCB structure */ + +#if defined(ALT_STACK_CHECK) && (OS_TASK_CREATE_EXT_EN > 0) + + ldw et, 8(r4) /* load the new stack limit */ + +#endif + +#if OS_THREAD_SAFE_NEWLIB + /* + * restore the value of _impure_ptr ; _impure_ptr is asigned on a + * per task basis. It is used by Newlib to achieve reentrancy. + */ + + ldw r3, 40(sp) /* load the new impure pointer */ +#endif /* OS_THREAD_SAFE_NEWLIB */ + + /* + * Restore the saved registers for the new task. + */ + + ldw ra, 0(sp) + ldw fp, 4(sp) + ldw r23, 8(sp) + ldw r22, 12(sp) + ldw r21, 16(sp) + ldw r20, 20(sp) + ldw r19, 24(sp) + ldw r18, 28(sp) + ldw r17, 32(sp) + ldw r16, 36(sp) + +#if OS_THREAD_SAFE_NEWLIB + + stw r3, %gprel(_impure_ptr)(gp) /* update _impure_ptr */ + +#endif /* OS_THREAD_SAFE_NEWLIB */ + +#if defined(ALT_STACK_CHECK) && (OS_TASK_CREATE_EXT_EN > 0) + + stw et, %gprel(alt_stack_limit_value)(gp) + +#endif + + addi sp, sp, 44 + + /* + * resume execution of the new task. + */ + + ret + +#ifdef ALT_STACK_CHECK + +.Lstack_overflow: + break 3 + +#endif + +.set OSCtxSw_SWITCH_PC,0b-OSCtxSw + +/********************************************************************************************************* + * START THE HIGHEST PRIORITY TASK + * void OSStartHighRdy(void) + * + * Note(s): 1) Upon entry, + * OSTCBCur points to the OS_TCB of the task to suspend + * OSTCBHighRdy points to the OS_TCB of the task to resume + * + *********************************************************************************************************/ + .global OSStartHighRdy + +OSStartHighRdy: + + /* + * disable interrupts so that the scheduler doesn't run while + * we're initialising this task. + */ + rdctl r18, status + subi r17, zero, 2 /* r17 = 0xfffffffe */ + and r18, r18, r17 + wrctl status, r18 + + /* + * Call the user definable OSTaskSWHook() + */ + + call OSTaskSwHook + + /* + * set OSRunning = TRUE. + */ + + movi r18, 1 /* set r18 to the value 'TRUE' */ + stb r18, %gprel(OSRunning)(gp) /* save this to OSRunning */ + +#if defined(ALT_STACK_CHECK) && (OS_TASK_CREATE_EXT_EN == 0) + + mov et, zero /* Don't check stack limits */ + stw et, %gprel(alt_stack_limit_value)(gp) + +#endif + + /* + * start execution of the new task. + */ + + br 9b + +/********************************************************************************************************* + * CALL THE TASK INITILISATION FUNCTION + * void OSStartTsk(void) + *********************************************************************************************************/ + + .global OSStartTsk + +OSStartTsk: + /* This instruction is never executed. Its here to make the + * backtrace work right + */ + movi sp, 0 + + /* Enable interrupts */ + rdctl r2, status + ori r2, r2, 0x1 + wrctl status, r2 + + ldw r2, 4(sp) + ldw r4, 0(sp) + + addi sp, sp, 8 + + callr r2 + + nop diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/os_cpu_c.c b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/os_cpu_c.c new file mode 100644 index 00000000..ffea7b21 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/HAL/src/os_cpu_c.c @@ -0,0 +1,229 @@ +/*********************************************************************************************** + * uC/OS-II + * The Real-Time Kernel + * File : os_cpu_c.c + * For : uC/OS Real-time multitasking kernel for the Nios2 SoftCore Processor + * Written by : IS + * Based on : Nios port done by JS + * + * Functions defined in this module: + * + ***********************************************************************************************/ + +#include +#include + +#include + +#define OS_CPU_GLOBALS +#include "includes.h" /* Standard includes for uC/OS-II */ + +#include "system.h" + +extern void OSStartTsk; /* The entry point for all tasks. */ + +#if OS_TMR_EN > 0 +static INT16U OSTmrCtr; +#endif + +/*********************************************************************************************** + * INITIALIZE A TASK'S STACK + * + * Description: This function is called by either OSTaskCreate() or OSTaskCreateExt() to + * initialize the stack frame of the task being created. This function is + * highly processor specific. + * + * What it does: It builds up initial stack for a task. + * + * Arguments : task is a pointer to the task code + * + * pdata is a pointer to a user supplied data area that will be passed to the task + * when the task first executes. + * + * ptos is a pointer to the top of stack. It is assumed that 'ptos' points to + * a 'free' entry on the task stack. If OS_STK_GROWTH is set to 1 then + * 'ptos' will contain the HIGHEST valid address of the stack. Similarly, if + * OS_STK_GROWTH is set to 0, the 'ptos' will contains the LOWEST valid address + * of the stack. + * + * opt specifies options that can be used to alter the behavior of OSTaskStkInit(). + * (see uCOS_II.H for OS_TASK_OPT_???). + * + * Returns : Always returns the location of the new top-of-stack' once the processor registers have + * been placed on the stack in the proper order. + * + ***********************************************************************************************/ + +OS_STK *OSTaskStkInit(void (*task)(void *pd), void *pdata, OS_STK *pstk, INT16U opt) +{ + INT32U *frame_pointer; + INT32U *stk; + +#if OS_THREAD_SAFE_NEWLIB + struct _reent* local_impure_ptr; + + /* + * create and initialise the impure pointer used for Newlib thread local storage. + * This is only done if the C library is being used in a thread safe mode. Otherwise + * a single reent structure is used for all threads, which saves memory. + */ + + local_impure_ptr = (struct _reent*)((((INT32U)(pstk)) & ~0x3) - sizeof(struct _reent)); + + _REENT_INIT_PTR (local_impure_ptr); + + /* + * create a stack frame at the top of the stack (leaving space for the + * reentrant data structure). + */ + + frame_pointer = (INT32U*) local_impure_ptr; +#else + frame_pointer = (INT32U*) (((INT32U)(pstk)) & ~0x3); +#endif /* OS_THREAD_SAFE_NEWLIB */ + stk = frame_pointer - 13; + + /* Now fill the stack frame. */ + + stk[12] = (INT32U)task; /* task address (ra) */ + stk[11] = (INT32U) pdata; /* first register argument (r4) */ + +#if OS_THREAD_SAFE_NEWLIB + stk[10] = (INT32U) local_impure_ptr; /* value of _impure_ptr for this thread */ +#endif /* OS_THREAD_SAFE_NEWLIB */ + stk[0] = ((INT32U)&OSStartTsk) + 4;/* exception return address (ea) */ + + /* The next three lines don't generate any code, they just put symbols into + * the debug information which will later be used to navigate the thread + * data structures + */ + __asm__ (".set OSTCBNext_OFFSET,%0" :: "i" (offsetof(OS_TCB, OSTCBNext))); + __asm__ (".set OSTCBPrio_OFFSET,%0" :: "i" (offsetof(OS_TCB, OSTCBPrio))); + __asm__ (".set OSTCBStkPtr_OFFSET,%0" :: "i" (offsetof(OS_TCB, OSTCBStkPtr))); + + return((OS_STK *)stk); +} + +#if OS_CPU_HOOKS_EN +/* +********************************************************************************************************* +* TASK CREATION HOOK +* +* Description: This function is called when a task is created. +* +* Arguments : ptcb is a pointer to the task control block of the task being created. +* +* Note(s) : 1) Interrupts are disabled during this call. +********************************************************************************************************* +*/ +void OSTaskCreateHook (OS_TCB *ptcb) +{ + ptcb = ptcb; /* Prevent compiler warning */ +} + + +/* +********************************************************************************************************* +* TASK DELETION HOOK +* +* Description: This function is called when a task is deleted. +* +* Arguments : ptcb is a pointer to the task control block of the task being deleted. +* +* Note(s) : 1) Interrupts are disabled during this call. +********************************************************************************************************* +*/ +void OSTaskDelHook (OS_TCB *ptcb) +{ + ptcb = ptcb; /* Prevent compiler warning */ +} + +/* +********************************************************************************************************* +* TASK SWITCH HOOK +* +* Description: This function is called when a task switch is performed. This allows you to perform other +* operations during a context switch. +* +* Arguments : none +* +* Note(s) : 1) Interrupts are disabled during this call. +* 2) It is assumed that the global pointer 'OSTCBHighRdy' points to the TCB of the task that +* will be 'switched in' (i.e. the highest priority task) and, 'OSTCBCur' points to the +* task being switched out (i.e. the preempted task). +********************************************************************************************************* +*/ +void OSTaskSwHook (void) +{ +} + +/* +********************************************************************************************************* +* STATISTIC TASK HOOK +* +* Description: This function is called every second by uC/OS-II's statistics task. This allows your +* application to add functionality to the statistics task. +* +* Arguments : none +********************************************************************************************************* +*/ +void OSTaskStatHook (void) +{ +} + +/* +********************************************************************************************************* +* TICK HOOK +* +* Description: This function is called every tick. +* +* Arguments : none +* +* Note(s) : 1) Interrupts may or may not be ENABLED during this call. +********************************************************************************************************* +*/ + +/* + * Iniche stack has no header declaration for its timer 'hook'. + * Do that here to avoid build warnings. + */ +#ifdef ALT_INICHE +void cticks_hook(void); +#endif + +void OSTimeTickHook (void) +{ +#if OS_TMR_EN > 0 + OSTmrCtr++; + if (OSTmrCtr >= (OS_TICKS_PER_SEC / OS_TMR_CFG_TICKS_PER_SEC)) { + OSTmrCtr = 0; + OSTmrSignal(); + } +#endif + +#ifdef ALT_INICHE + /* Service the Interniche timer */ + cticks_hook(); +#endif +} + +void OSInitHookBegin(void) +{ +#if OS_TMR_EN > 0 + OSTmrCtr = 0; +#endif +} + +void OSInitHookEnd(void) +{ +} + +void OSTaskIdleHook(void) +{ +} + +void OSTCBInitHook(OS_TCB *ptcb) +{ +} + +#endif diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/Makefile b/MCandWifiTestDE0/Software/MCTest_bsp/Makefile new file mode 100644 index 00000000..b20b3449 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/Makefile @@ -0,0 +1,813 @@ +#------------------------------------------------------------------------------ +# BSP MAKEFILE +# +# This makefile was automatically generated by the nios2-bsp-generate-files +# command. Its purpose is to build a custom Board Support Package (BSP) +# targeting a specific Nios II processor in an SOPC Builder-based design. +# +# To create an application or library Makefile which uses this BSP, try the +# nios2-app-generate-makefile or nios2-lib-generate-makefile commands. +#------------------------------------------------------------------------------ + +#------------------------------------------------------------------------------ +# TOOLS +#------------------------------------------------------------------------------ + +MKDIR := mkdir -p +ECHO := echo +SPACE := $(empty) $(empty) + +#------------------------------------------------------------------------------ +# The adjust-path macro +# +# If COMSPEC is defined, Make is launched from Windows through +# Cygwin. This adjust-path macro will call 'cygpath -u' on all +# paths to ensure they are readable by Make. +# +# If COMSPEC is not defined, Make is launched from *nix, and no adjustment +# is necessary +#------------------------------------------------------------------------------ + +ifndef COMSPEC +ifdef ComSpec +COMSPEC = $(ComSpec) +endif # ComSpec +endif # !COMSPEC + +ifdef COMSPEC + adjust-path = $(subst $(SPACE),\$(SPACE),$(shell cygpath -u "$1")) + adjust-path-mixed = $(subst $(SPACE),\$(SPACE),$(shell cygpath -m "$1")) +else + adjust-path = $(subst $(SPACE),\$(SPACE),$1) + adjust-path-mixed = $(subst $(SPACE),\$(SPACE),$1) +endif + +#------------------------------------------------------------------------------ +# DEFAULT TARGET +# +# The default target, "all", must appear before any other target in the +# Makefile. Note that extra prerequisites are added to the "all" rule later. +#------------------------------------------------------------------------------ +.PHONY: all +all: + @$(ECHO) [BSP build complete] + + +#------------------------------------------------------------------------------ +# PATHS & DIRECTORY NAMES +# +# Explicitly locate absolute path of the BSP root +#------------------------------------------------------------------------------ + +BSP_ROOT_DIR := . + +# Define absolute path to the root of the BSP. +ABS_BSP_ROOT := $(call adjust-path-mixed,$(shell pwd)) + +# Stash all BSP object files here +OBJ_DIR := ./obj + + +#------------------------------------------------------------------------------ +# MANAGED CONTENT +# +# All content between the lines "START MANAGED" and "END MANAGED" below is +# generated based on variables in the BSP settings file when the +# nios2-bsp-generate-files command is invoked. If you wish to persist any +# information pertaining to the build process, it is recomended that you +# utilize the BSP settings mechanism to do so. +# +# Note that most variable assignments in this section have a corresponding BSP +# setting that can be changed by using the nios2-bsp-create-settings or +# nios2-bsp-update-settings command before nios2-bsp-generate-files; if you +# want any variable set to a specific value when this Makefile is re-generated +# (to prevent hand-edits from being over-written), use the BSP settings +# facilities above. +#------------------------------------------------------------------------------ + +#START MANAGED + +# The following TYPE comment allows tools to identify the 'type' of target this +# makefile is associated with. +# TYPE: BSP_PRIVATE_MAKEFILE + +# This following VERSION comment indicates the version of the tool used to +# generate this makefile. A makefile variable is provided for VERSION as well. +# ACDS_VERSION: 12.1sp1 +ACDS_VERSION := 12.1sp1 + +# This following BUILD_NUMBER comment indicates the build number of the tool +# used to generate this makefile. +# BUILD_NUMBER: 243 + +SETTINGS_FILE := settings.bsp +SOPC_FILE := C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system.sopcinfo + +#------------------------------------------------------------------------------- +# TOOL & COMMAND DEFINITIONS +# +# The base command for each build operation are expressed here. Additional +# switches may be expressed here. They will run for all instances of the +# utility. +#------------------------------------------------------------------------------- + +# Archiver command. Creates library files. +AR = nios2-elf-ar + +# Assembler command. Note that CC is used for .S files. +AS = nios2-elf-gcc + +# Custom flags only passed to the archiver. This content of this variable is +# directly passed to the archiver rather than the more standard "ARFLAGS". The +# reason for this is that GNU Make assumes some default content in ARFLAGS. +# This setting defines the value of BSP_ARFLAGS in Makefile. +BSP_ARFLAGS = -src + +# Custom flags only passed to the assembler. This setting defines the value of +# BSP_ASFLAGS in Makefile. +BSP_ASFLAGS = -Wa,-gdwarf2 + +# C/C++ compiler debug level. '-g' provides the default set of debug symbols +# typically required to debug a typical application. Omitting '-g' removes +# debug symbols from the ELF. This setting defines the value of +# BSP_CFLAGS_DEBUG in Makefile. +BSP_CFLAGS_DEBUG = -g + +# C/C++ compiler optimization level. "-O0" = no optimization,"-O2" = "normal" +# optimization, etc. "-O0" is recommended for code that you want to debug since +# compiler optimization can remove variables and produce non-sequential +# execution of code while debugging. This setting defines the value of +# BSP_CFLAGS_OPTIMIZATION in Makefile. +BSP_CFLAGS_OPTIMIZATION = -O0 + +# C/C++ compiler warning level. "-Wall" is commonly used.This setting defines +# the value of BSP_CFLAGS_WARNINGS in Makefile. +BSP_CFLAGS_WARNINGS = -Wall + +# C compiler command. +CC = nios2-elf-gcc -xc + +# C++ compiler command. +CXX = nios2-elf-gcc -xc++ + +# Command used to remove files during 'clean' target. +RM = rm -f + + +#------------------------------------------------------------------------------- +# BUILD PRE & POST PROCESS COMMANDS +# +# The following variables are treated as shell commands in the rule +# definitions for each file-type associated with the BSP build, as well as +# commands run at the beginning and end of the entire BSP build operation. +# Pre-process commands are executed before the relevant command (for example, +# a command defined in the "CC_PRE_PROCESS" variable executes before the C +# compiler for building .c files), while post-process commands are executed +# immediately afterwards. +# +# You can view each pre/post-process command in the "Build Rules: All & +# Clean", "Pattern Rules to Build Objects", and "Library Rules" sections of +# this Makefile. +#------------------------------------------------------------------------------- + + +#------------------------------------------------------------------------------- +# BSP SOURCE BUILD SETTINGS (FLAG GENERATION) +# +# Software build settings such as compiler optimization, debug level, warning +# flags, etc., may be defined in the following variables. The variables below +# are concatenated together in the 'Flags' section of this Makefile to form +# final variables of flags passed to the build tools. +# +# These settings are considered private to the BSP and apply to all library & +# driver files in it; they do NOT automatically propagate to, for example, the +# build settings for an application. +# # For additional detail and syntax requirements, please refer to GCC help +# (example: "nios2-elf-gcc --help --verbose"). +# +# Unless indicated otherwise, multiple entries in each variable should be +# space-separated. +#------------------------------------------------------------------------------- + +# Altera HAL alt_sys_init.c generated source file +GENERATED_C_FILES := $(ABS_BSP_ROOT)/alt_sys_init.c +GENERATED_C_LIB_SRCS += alt_sys_init.c + + +#------------------------------------------------------------------------------- +# BSP SOURCE FILE LISTING +# +# All source files that comprise the BSP are listed here, along with path +# information to each file expressed relative to the BSP root. The precise +# list and location of each file is derived from the driver, operating system, +# or software package source file declarations. +# +# Following specification of the source files for each component, driver, etc., +# each source file type (C, assembly, etc.) is concatenated together and used +# to construct a list of objects. Pattern rules to build each object are then +# used to build each file. +#------------------------------------------------------------------------------- + +# altera_avalon_jtag_uart_driver sources root +altera_avalon_jtag_uart_driver_SRCS_ROOT := drivers + +# altera_avalon_jtag_uart_driver sources +altera_avalon_jtag_uart_driver_C_LIB_SRCS := \ + $(altera_avalon_jtag_uart_driver_SRCS_ROOT)/src/altera_avalon_jtag_uart_init.c \ + $(altera_avalon_jtag_uart_driver_SRCS_ROOT)/src/altera_avalon_jtag_uart_read.c \ + $(altera_avalon_jtag_uart_driver_SRCS_ROOT)/src/altera_avalon_jtag_uart_write.c \ + $(altera_avalon_jtag_uart_driver_SRCS_ROOT)/src/altera_avalon_jtag_uart_ioctl.c \ + $(altera_avalon_jtag_uart_driver_SRCS_ROOT)/src/altera_avalon_jtag_uart_fd.c + +# altera_avalon_pio_driver sources root +altera_avalon_pio_driver_SRCS_ROOT := drivers + +# altera_avalon_pio_driver sources +# altera_avalon_sysid_qsys_driver sources root +altera_avalon_sysid_qsys_driver_SRCS_ROOT := drivers + +# altera_avalon_sysid_qsys_driver sources +altera_avalon_sysid_qsys_driver_C_LIB_SRCS := \ + $(altera_avalon_sysid_qsys_driver_SRCS_ROOT)/src/altera_avalon_sysid_qsys.c + +# altera_avalon_timer_driver sources root +altera_avalon_timer_driver_SRCS_ROOT := drivers + +# altera_avalon_timer_driver sources +altera_avalon_timer_driver_C_LIB_SRCS := \ + $(altera_avalon_timer_driver_SRCS_ROOT)/src/altera_avalon_timer_sc.c \ + $(altera_avalon_timer_driver_SRCS_ROOT)/src/altera_avalon_timer_ts.c \ + $(altera_avalon_timer_driver_SRCS_ROOT)/src/altera_avalon_timer_vars.c + +# altera_avalon_uart_driver sources root +altera_avalon_uart_driver_SRCS_ROOT := drivers + +# altera_avalon_uart_driver sources +altera_avalon_uart_driver_C_LIB_SRCS := \ + $(altera_avalon_uart_driver_SRCS_ROOT)/src/altera_avalon_uart_fd.c \ + $(altera_avalon_uart_driver_SRCS_ROOT)/src/altera_avalon_uart_init.c \ + $(altera_avalon_uart_driver_SRCS_ROOT)/src/altera_avalon_uart_ioctl.c \ + $(altera_avalon_uart_driver_SRCS_ROOT)/src/altera_avalon_uart_read.c \ + $(altera_avalon_uart_driver_SRCS_ROOT)/src/altera_avalon_uart_write.c + +# altera_nios2_qsys_ucosii_driver sources root +altera_nios2_qsys_ucosii_driver_SRCS_ROOT := HAL + +# altera_nios2_qsys_ucosii_driver sources +altera_nios2_qsys_ucosii_driver_C_LIB_SRCS := \ + $(altera_nios2_qsys_ucosii_driver_SRCS_ROOT)/src/altera_nios2_qsys_irq.c \ + $(altera_nios2_qsys_ucosii_driver_SRCS_ROOT)/src/alt_busy_sleep.c \ + $(altera_nios2_qsys_ucosii_driver_SRCS_ROOT)/src/alt_irq_vars.c \ + $(altera_nios2_qsys_ucosii_driver_SRCS_ROOT)/src/alt_icache_flush.c \ + $(altera_nios2_qsys_ucosii_driver_SRCS_ROOT)/src/alt_icache_flush_all.c \ + $(altera_nios2_qsys_ucosii_driver_SRCS_ROOT)/src/alt_dcache_flush.c \ + $(altera_nios2_qsys_ucosii_driver_SRCS_ROOT)/src/alt_dcache_flush_all.c \ + $(altera_nios2_qsys_ucosii_driver_SRCS_ROOT)/src/alt_dcache_flush_no_writeback.c \ + $(altera_nios2_qsys_ucosii_driver_SRCS_ROOT)/src/alt_instruction_exception_entry.c \ + $(altera_nios2_qsys_ucosii_driver_SRCS_ROOT)/src/alt_irq_register.c \ + $(altera_nios2_qsys_ucosii_driver_SRCS_ROOT)/src/alt_iic.c \ + $(altera_nios2_qsys_ucosii_driver_SRCS_ROOT)/src/alt_remap_cached.c \ + $(altera_nios2_qsys_ucosii_driver_SRCS_ROOT)/src/alt_remap_uncached.c \ + $(altera_nios2_qsys_ucosii_driver_SRCS_ROOT)/src/alt_uncached_free.c \ + $(altera_nios2_qsys_ucosii_driver_SRCS_ROOT)/src/alt_uncached_malloc.c \ + $(altera_nios2_qsys_ucosii_driver_SRCS_ROOT)/src/alt_do_ctors.c \ + $(altera_nios2_qsys_ucosii_driver_SRCS_ROOT)/src/alt_do_dtors.c \ + $(altera_nios2_qsys_ucosii_driver_SRCS_ROOT)/src/alt_gmon.c \ + $(altera_nios2_qsys_ucosii_driver_SRCS_ROOT)/src/alt_usleep.c \ + $(altera_nios2_qsys_ucosii_driver_SRCS_ROOT)/src/os_cpu_c.c + +altera_nios2_qsys_ucosii_driver_ASM_LIB_SRCS := \ + $(altera_nios2_qsys_ucosii_driver_SRCS_ROOT)/src/alt_exception_entry.S \ + $(altera_nios2_qsys_ucosii_driver_SRCS_ROOT)/src/alt_exception_trap.S \ + $(altera_nios2_qsys_ucosii_driver_SRCS_ROOT)/src/alt_exception_muldiv.S \ + $(altera_nios2_qsys_ucosii_driver_SRCS_ROOT)/src/alt_irq_entry.S \ + $(altera_nios2_qsys_ucosii_driver_SRCS_ROOT)/src/alt_software_exception.S \ + $(altera_nios2_qsys_ucosii_driver_SRCS_ROOT)/src/alt_mcount.S \ + $(altera_nios2_qsys_ucosii_driver_SRCS_ROOT)/src/alt_log_macro.S \ + $(altera_nios2_qsys_ucosii_driver_SRCS_ROOT)/src/crt0.S \ + $(altera_nios2_qsys_ucosii_driver_SRCS_ROOT)/src/os_cpu_a.S + +# hal sources root +hal_SRCS_ROOT := HAL + +# hal sources +hal_C_LIB_SRCS := \ + $(hal_SRCS_ROOT)/src/alt_alarm_start.c \ + $(hal_SRCS_ROOT)/src/alt_close.c \ + $(hal_SRCS_ROOT)/src/alt_dev.c \ + $(hal_SRCS_ROOT)/src/alt_dev_llist_insert.c \ + $(hal_SRCS_ROOT)/src/alt_dma_rxchan_open.c \ + $(hal_SRCS_ROOT)/src/alt_dma_txchan_open.c \ + $(hal_SRCS_ROOT)/src/alt_environ.c \ + $(hal_SRCS_ROOT)/src/alt_errno.c \ + $(hal_SRCS_ROOT)/src/alt_execve.c \ + $(hal_SRCS_ROOT)/src/alt_exit.c \ + $(hal_SRCS_ROOT)/src/alt_fcntl.c \ + $(hal_SRCS_ROOT)/src/alt_fd_lock.c \ + $(hal_SRCS_ROOT)/src/alt_fd_unlock.c \ + $(hal_SRCS_ROOT)/src/alt_find_dev.c \ + $(hal_SRCS_ROOT)/src/alt_find_file.c \ + $(hal_SRCS_ROOT)/src/alt_flash_dev.c \ + $(hal_SRCS_ROOT)/src/alt_fork.c \ + $(hal_SRCS_ROOT)/src/alt_fs_reg.c \ + $(hal_SRCS_ROOT)/src/alt_fstat.c \ + $(hal_SRCS_ROOT)/src/alt_get_fd.c \ + $(hal_SRCS_ROOT)/src/alt_getchar.c \ + $(hal_SRCS_ROOT)/src/alt_getpid.c \ + $(hal_SRCS_ROOT)/src/alt_gettod.c \ + $(hal_SRCS_ROOT)/src/alt_iic_isr_register.c \ + $(hal_SRCS_ROOT)/src/alt_instruction_exception_register.c \ + $(hal_SRCS_ROOT)/src/alt_ioctl.c \ + $(hal_SRCS_ROOT)/src/alt_io_redirect.c \ + $(hal_SRCS_ROOT)/src/alt_irq_handler.c \ + $(hal_SRCS_ROOT)/src/alt_isatty.c \ + $(hal_SRCS_ROOT)/src/alt_kill.c \ + $(hal_SRCS_ROOT)/src/alt_link.c \ + $(hal_SRCS_ROOT)/src/alt_load.c \ + $(hal_SRCS_ROOT)/src/alt_log_printf.c \ + $(hal_SRCS_ROOT)/src/alt_lseek.c \ + $(hal_SRCS_ROOT)/src/alt_main.c \ + $(hal_SRCS_ROOT)/src/alt_open.c \ + $(hal_SRCS_ROOT)/src/alt_printf.c \ + $(hal_SRCS_ROOT)/src/alt_putchar.c \ + $(hal_SRCS_ROOT)/src/alt_putstr.c \ + $(hal_SRCS_ROOT)/src/alt_read.c \ + $(hal_SRCS_ROOT)/src/alt_release_fd.c \ + $(hal_SRCS_ROOT)/src/alt_rename.c \ + $(hal_SRCS_ROOT)/src/alt_sbrk.c \ + $(hal_SRCS_ROOT)/src/alt_settod.c \ + $(hal_SRCS_ROOT)/src/alt_stat.c \ + $(hal_SRCS_ROOT)/src/alt_tick.c \ + $(hal_SRCS_ROOT)/src/alt_times.c \ + $(hal_SRCS_ROOT)/src/alt_unlink.c \ + $(hal_SRCS_ROOT)/src/alt_wait.c \ + $(hal_SRCS_ROOT)/src/alt_write.c + +# ucosii sources root +ucosii_SRCS_ROOT := UCOSII + +# ucosii sources +ucosii_C_LIB_SRCS := \ + $(ucosii_SRCS_ROOT)/src/alt_env_lock.c \ + $(ucosii_SRCS_ROOT)/src/alt_malloc_lock.c \ + $(ucosii_SRCS_ROOT)/src/os_core.c \ + $(ucosii_SRCS_ROOT)/src/os_dbg.c \ + $(ucosii_SRCS_ROOT)/src/os_flag.c \ + $(ucosii_SRCS_ROOT)/src/os_mbox.c \ + $(ucosii_SRCS_ROOT)/src/os_mem.c \ + $(ucosii_SRCS_ROOT)/src/os_mutex.c \ + $(ucosii_SRCS_ROOT)/src/os_q.c \ + $(ucosii_SRCS_ROOT)/src/os_sem.c \ + $(ucosii_SRCS_ROOT)/src/os_task.c \ + $(ucosii_SRCS_ROOT)/src/os_time.c \ + $(ucosii_SRCS_ROOT)/src/os_tmr.c + +# up_avalon_rs232_driver sources root +up_avalon_rs232_driver_SRCS_ROOT := drivers + +# up_avalon_rs232_driver sources +up_avalon_rs232_driver_C_LIB_SRCS := \ + $(up_avalon_rs232_driver_SRCS_ROOT)/src/altera_up_avalon_rs232.c + + +# Assemble all component C source files +COMPONENT_C_LIB_SRCS += \ + $(altera_avalon_jtag_uart_driver_C_LIB_SRCS) \ + $(altera_avalon_sysid_qsys_driver_C_LIB_SRCS) \ + $(altera_avalon_timer_driver_C_LIB_SRCS) \ + $(altera_avalon_uart_driver_C_LIB_SRCS) \ + $(altera_nios2_qsys_ucosii_driver_C_LIB_SRCS) \ + $(hal_C_LIB_SRCS) \ + $(ucosii_C_LIB_SRCS) \ + $(up_avalon_rs232_driver_C_LIB_SRCS) + +# Assemble all component assembly source files +COMPONENT_ASM_LIB_SRCS += \ + $(altera_nios2_qsys_ucosii_driver_ASM_LIB_SRCS) + +# Assemble all component C++ source files +COMPONENT_CPP_LIB_SRCS += \ + +#END MANAGED + +#------------------------------------------------------------------------------ +# PUBLIC.MK +# +# The generated public.mk file contains BSP information that is shared with +# other external makefiles, such as a Nios II application makefile. System- +# dependent information such as hardware-specific compiler flags and +# simulation file generation are stored here. +# +# In addition, public.mk contains include paths that various software, +# such as a device driver, may need for the C compiler. These paths are +# written to public.mk with respect to the BSP root. In public.mk, each +# path is prefixed with a special variable, $(ALT_LIBRARY_ROOT_DIR). The +# purpose of this variable is to allow an external Makefile to append on +# path information to precisely locate paths expressed in public.mk +# Since this is the BSP Makefile, we set ALT_LIBRARY_ROOT_DIR to point right +# here ("."), at the BSP root. +# +# ALT_LIBRARY_ROOT_DIR must always be set before public.mk is included. +#------------------------------------------------------------------------------ +ALT_LIBRARY_ROOT_DIR := . +include public.mk + + +#------------------------------------------------------------------------------ +# FLAGS +# +# Include paths for BSP files are written into the public.mk file and must +# be added to the existing list of pre-processor flags. In addition, "hooks" +# for standard flags left intentionally empty (CFLAGS, CPPFLAGS, ASFLAGS, +# and CXXFLAGS) are provided for conveniently adding to the relevant flags +# on the command-line or via script that calls make. +#------------------------------------------------------------------------------ +# Assemble final list of compiler flags from generated content +BSP_CFLAGS += \ + $(BSP_CFLAGS_DEFINED_SYMBOLS) \ + $(BSP_CFLAGS_UNDEFINED_SYMBOLS) \ + $(BSP_CFLAGS_OPTIMIZATION) \ + $(BSP_CFLAGS_DEBUG) \ + $(BSP_CFLAGS_WARNINGS) \ + $(BSP_CFLAGS_USER_FLAGS) \ + $(ALT_CFLAGS) \ + $(CFLAGS) + +# Make ready the final list of include directories and other C pre-processor +# flags. Each include path is made ready by prefixing it with "-I". +BSP_CPPFLAGS += \ + $(addprefix -I, $(BSP_INC_DIRS)) \ + $(addprefix -I, $(ALT_INCLUDE_DIRS)) \ + $(ALT_CPPFLAGS) \ + $(CPPFLAGS) + +# Finish off assembler flags with any user-provided flags +BSP_ASFLAGS += $(ASFLAGS) + +# Finish off C++ flags with any user-provided flags +BSP_CXXFLAGS += $(CXXFLAGS) + +# And finally, the ordered list +C_SRCS += $(GENERATED_C_LIB_SRCS) \ + $(COMPONENT_C_LIB_SRCS) + +CXX_SRCS += $(GENERATED_CPP_LIB_SRCS) \ + $(COMPONENT_CPP_LIB_SRCS) + +ASM_SRCS += $(GENERATED_ASM_LIB_SRCS) \ + $(COMPONENT_ASM_LIB_SRCS) + + +#------------------------------------------------------------------------------ +# LIST OF GENERATED FILES +# +# A Nios II BSP relies on the generation of several source files used +# by both the BSP and any applications referencing the BSP. +#------------------------------------------------------------------------------ + + +GENERATED_H_FILES := $(ABS_BSP_ROOT)/system.h + +GENERATED_LINKER_SCRIPT := $(ABS_BSP_ROOT)/linker.x + +GENERATED_FILES += $(GENERATED_H_FILES) \ + $(GENERATED_LINKER_SCRIPT) + + +#------------------------------------------------------------------------------ +# SETUP TO BUILD OBJECTS +# +# List of object files which are to be built. This is constructed from the input +# list of C source files (C_SRCS), C++ source files (CXX_SRCS), and assembler +# source file (ASM_SRCS). The permitted file extensions are: +# +# .c .C - for C files +# .cxx .cc .cpp .CXX .CC .CPP - for C++ files +# .S .s - for assembly files +# +# Extended description: The list of objects is a sorted list (duplicates +# removed) of all possible objects, placed beneath the ./obj directory, +# including any path information stored in the "*_SRCS" variable. The +# "patsubst" commands are used to concatenate together multiple file suffix +# types for common files (i.e. c++ as .cxx, .cc, .cpp). +# +# File extensions are case-insensitive in build rules with the exception of +# assembly sources. Nios II assembly sources with the ".S" extension are first +# run through the C preprocessor. Sources with the ".s" extension are not. +#------------------------------------------------------------------------------ +OBJS = $(sort $(addprefix $(OBJ_DIR)/, \ + $(patsubst %.c, %.o, $(patsubst %.C, %.o, $(C_SRCS))) \ + $(patsubst %.cxx, %.o, $(patsubst %.CXX, %.o, \ + $(patsubst %.cc, %.o, $(patsubst %.CC, %.o, \ + $(patsubst %.cpp, %.o, $(patsubst %.CPP, %.o, \ + $(CXX_SRCS) )))))) \ + $(patsubst %.S, %.o, $(patsubst %.s, %.o, $(ASM_SRCS))) )) + +# List of dependancy files for each object file. +DEPS = $(OBJS:.o=.d) + + +# Rules to force your project to rebuild or relink +# .force_relink file will cause any application that depends on this project to relink +# .force_rebuild file will cause this project to rebuild object files +# .force_rebuild_all file will cause this project and any project that depends on this project to rebuild object files + +FORCE_RELINK_DEP := .force_relink +FORCE_REBUILD_DEP := .force_rebuild +FORCE_REBUILD_ALL_DEP := .force_rebuild_all +FORCE_REBUILD_DEP_LIST := $(FORCE_RELINK_DEP) $(FORCE_REBUILD_DEP) $(FORCE_REBUILD_ALL_DEP) + +$(FORCE_REBUILD_DEP_LIST): + +$(OBJS): $(wildcard $(FORCE_REBUILD_DEP)) $(wildcard $(FORCE_REBUILD_ALL_DEP)) + + +#------------------------------------------------------------------------------ +# BUILD RULES: ALL & CLEAN +#------------------------------------------------------------------------------ +.DELETE_ON_ERROR: + +.PHONY: all +all: build_pre_process +all: Makefile $(GENERATED_FILES) $(BSP_LIB) $(NEWLIB_DIR) +all: build_post_process + + +# clean: remove .o/.a/.d +.PHONY: clean +clean: + @$(RM) -r $(BSP_LIB) $(OBJ_DIR) $(FORCE_REBUILD_DEP_LIST) +ifneq ($(wildcard $(NEWLIB_DIR)),) + @$(RM) -r $(NEWLIB_DIR) +endif + @$(ECHO) [BSP clean complete] + + +#------------------------------------------------------------------------------ +# BUILD PRE/POST PROCESS +#------------------------------------------------------------------------------ +build_pre_process : + $(BUILD_PRE_PROCESS) + +build_post_process : + $(BUILD_POST_PROCESS) + +.PHONY: build_pre_process build_post_process + + + +#------------------------------------------------------------------------------ +# MAKEFILE UP TO DATE? +# +# Is this very Makefile up to date? Someone may have changed the BSP settings +# file or the associated target hardware. +#------------------------------------------------------------------------------ +# Skip this check when clean is the only target +ifneq ($(MAKECMDGOALS),clean) + +ifneq ($(wildcard $(SETTINGS_FILE)),$(SETTINGS_FILE)) +$(warning Warning: BSP Settings File $(SETTINGS_FILE) could not be found.) +endif + +Makefile: $(wildcard $(SETTINGS_FILE)) + @$(ECHO) Makefile not up to date. + @$(ECHO) $(SETTINGS_FILE) has been modified since the BSP Makefile was generated. + @$(ECHO) + @$(ECHO) Generate the BSP to update the Makefile, and then build again. + @$(ECHO) + @$(ECHO) To generate from Eclipse: + @$(ECHO) " 1. Right-click the BSP project." + @$(ECHO) " 2. In the Nios II Menu, click Generate BSP." + @$(ECHO) + @$(ECHO) To generate from the command line: + @$(ECHO) " nios2-bsp-generate-files --settings= --bsp-dir=" + @$(ECHO) + @exit 1 + +ifneq ($(wildcard $(SOPC_FILE)),$(SOPC_FILE)) +$(warning Warning: SOPC File $(SOPC_FILE) could not be found.) +endif + +public.mk: $(wildcard $(SOPC_FILE)) + @$(ECHO) Makefile not up to date. + @$(ECHO) $(SOPC_FILE) has been modified since the BSP was generated. + @$(ECHO) + @$(ECHO) Generate the BSP to update the Makefile, and then build again. + @$(ECHO) + @$(ECHO) To generate from Eclipse: + @$(ECHO) " 1. Right-click the BSP project." + @$(ECHO) " 2. In the Nios II Menu, click Generate BSP." + @$(ECHO) + @$(ECHO) To generate from the command line: + @$(ECHO) " nios2-bsp-generate-files --settings= --bsp-dir=" + @$(ECHO) + @exit 1 + +endif # $(MAKECMDGOALS) != clean + +#------------------------------------------------------------------------------ +# PATTERN RULES TO BUILD OBJECTS +#------------------------------------------------------------------------------ +$(OBJ_DIR)/%.o: %.c + @$(ECHO) Compiling $( +#include +#include + +/* +********************************************************************************************************* +* MISCELLANEOUS +********************************************************************************************************* +*/ + +#ifdef OS_GLOBALS +#define OS_EXT +#else +#define OS_EXT extern +#endif + +#ifndef OS_FALSE +#define OS_FALSE 0u +#endif + +#ifndef OS_TRUE +#define OS_TRUE 1u +#endif + +#define OS_ASCII_NUL (INT8U)0 + +#define OS_PRIO_SELF 0xFFu /* Indicate SELF priority */ + +#if OS_TASK_STAT_EN > 0 +#define OS_N_SYS_TASKS 2u /* Number of system tasks */ +#else +#define OS_N_SYS_TASKS 1u +#endif + +#define OS_TASK_STAT_PRIO (OS_LOWEST_PRIO - 1) /* Statistic task priority */ +#define OS_TASK_IDLE_PRIO (OS_LOWEST_PRIO) /* IDLE task priority */ + +#if OS_LOWEST_PRIO <= 63 +#define OS_EVENT_TBL_SIZE ((OS_LOWEST_PRIO) / 8 + 1) /* Size of event table */ +#define OS_RDY_TBL_SIZE ((OS_LOWEST_PRIO) / 8 + 1) /* Size of ready table */ +#else +#define OS_EVENT_TBL_SIZE ((OS_LOWEST_PRIO) / 16 + 1) /* Size of event table */ +#define OS_RDY_TBL_SIZE ((OS_LOWEST_PRIO) / 16 + 1) /* Size of ready table */ +#endif + +#define OS_TASK_IDLE_ID 65535u /* ID numbers for Idle, Stat and Timer tasks */ +#define OS_TASK_STAT_ID 65534u +#define OS_TASK_TMR_ID 65533u + +#define OS_EVENT_EN (((OS_Q_EN > 0) && (OS_MAX_QS > 0)) || (OS_MBOX_EN > 0) || (OS_SEM_EN > 0) || (OS_MUTEX_EN > 0)) + +#define OS_TCB_RESERVED ((OS_TCB *)1) + +/*$PAGE*/ +/* +********************************************************************************************************* +* TASK STATUS (Bit definition for OSTCBStat) +********************************************************************************************************* +*/ +#define OS_STAT_RDY 0x00u /* Ready to run */ +#define OS_STAT_SEM 0x01u /* Pending on semaphore */ +#define OS_STAT_MBOX 0x02u /* Pending on mailbox */ +#define OS_STAT_Q 0x04u /* Pending on queue */ +#define OS_STAT_SUSPEND 0x08u /* Task is suspended */ +#define OS_STAT_MUTEX 0x10u /* Pending on mutual exclusion semaphore */ +#define OS_STAT_FLAG 0x20u /* Pending on event flag group */ +#define OS_STAT_MULTI 0x80u /* Pending on multiple events */ + +#define OS_STAT_PEND_ANY (OS_STAT_SEM | OS_STAT_MBOX | OS_STAT_Q | OS_STAT_MUTEX | OS_STAT_FLAG) + +/* +********************************************************************************************************* +* TASK PEND STATUS (Status codes for OSTCBStatPend) +********************************************************************************************************* +*/ +#define OS_STAT_PEND_OK 0u /* Pending status OK, not pending, or pending complete */ +#define OS_STAT_PEND_TO 1u /* Pending timed out */ +#define OS_STAT_PEND_ABORT 2u /* Pending aborted */ + +/* +********************************************************************************************************* +* OS_EVENT types +********************************************************************************************************* +*/ +#define OS_EVENT_TYPE_UNUSED 0u +#define OS_EVENT_TYPE_MBOX 1u +#define OS_EVENT_TYPE_Q 2u +#define OS_EVENT_TYPE_SEM 3u +#define OS_EVENT_TYPE_MUTEX 4u +#define OS_EVENT_TYPE_FLAG 5u + +#define OS_TMR_TYPE 100u /* Used to identify Timers ... */ + /* ... (Must be different value than OS_EVENT_TYPE_xxx) */ + +/* +********************************************************************************************************* +* EVENT FLAGS +********************************************************************************************************* +*/ +#define OS_FLAG_WAIT_CLR_ALL 0u /* Wait for ALL the bits specified to be CLR (i.e. 0) */ +#define OS_FLAG_WAIT_CLR_AND 0u + +#define OS_FLAG_WAIT_CLR_ANY 1u /* Wait for ANY of the bits specified to be CLR (i.e. 0) */ +#define OS_FLAG_WAIT_CLR_OR 1u + +#define OS_FLAG_WAIT_SET_ALL 2u /* Wait for ALL the bits specified to be SET (i.e. 1) */ +#define OS_FLAG_WAIT_SET_AND 2u + +#define OS_FLAG_WAIT_SET_ANY 3u /* Wait for ANY of the bits specified to be SET (i.e. 1) */ +#define OS_FLAG_WAIT_SET_OR 3u + + +#define OS_FLAG_CONSUME 0x80u /* Consume the flags if condition(s) satisfied */ + + +#define OS_FLAG_CLR 0u +#define OS_FLAG_SET 1u + +/* +********************************************************************************************************* +* Values for OSTickStepState +* +* Note(s): This feature is used by uC/OS-View. +********************************************************************************************************* +*/ + +#if OS_TICK_STEP_EN > 0 +#define OS_TICK_STEP_DIS 0u /* Stepping is disabled, tick runs as mormal */ +#define OS_TICK_STEP_WAIT 1u /* Waiting for uC/OS-View to set OSTickStepState to _ONCE */ +#define OS_TICK_STEP_ONCE 2u /* Process tick once and wait for next cmd from uC/OS-View */ +#endif + +/* +********************************************************************************************************* +* Possible values for 'opt' argument of OSSemDel(), OSMboxDel(), OSQDel() and OSMutexDel() +********************************************************************************************************* +*/ +#define OS_DEL_NO_PEND 0u +#define OS_DEL_ALWAYS 1u + +/* +********************************************************************************************************* +* OS???Pend() OPTIONS +* +* These #defines are used to establish the options for OS???PendAbort(). +********************************************************************************************************* +*/ +#define OS_PEND_OPT_NONE 0u /* NO option selected */ +#define OS_PEND_OPT_BROADCAST 1u /* Broadcast action to ALL tasks waiting */ + +/* +********************************************************************************************************* +* OS???PostOpt() OPTIONS +* +* These #defines are used to establish the options for OSMboxPostOpt() and OSQPostOpt(). +********************************************************************************************************* +*/ +#define OS_POST_OPT_NONE 0x00u /* NO option selected */ +#define OS_POST_OPT_BROADCAST 0x01u /* Broadcast message to ALL tasks waiting */ +#define OS_POST_OPT_FRONT 0x02u /* Post to highest priority task waiting */ +#define OS_POST_OPT_NO_SCHED 0x04u /* Do not call the scheduler if this option is selected */ + +/* +********************************************************************************************************* +* TASK OPTIONS (see OSTaskCreateExt()) +********************************************************************************************************* +*/ +#define OS_TASK_OPT_NONE 0x0000u /* NO option selected */ +#define OS_TASK_OPT_STK_CHK 0x0001u /* Enable stack checking for the task */ +#define OS_TASK_OPT_STK_CLR 0x0002u /* Clear the stack when the task is create */ +#define OS_TASK_OPT_SAVE_FP 0x0004u /* Save the contents of any floating-point registers */ + +/* +********************************************************************************************************* +* TIMER OPTIONS (see OSTmrStart() and OSTmrStop()) +********************************************************************************************************* +*/ +#define OS_TMR_OPT_NONE 0u /* No option selected */ + +#define OS_TMR_OPT_ONE_SHOT 1u /* Timer will not automatically restart when it expires */ +#define OS_TMR_OPT_PERIODIC 2u /* Timer will automatically restart when it expires */ + +#define OS_TMR_OPT_CALLBACK 3u /* OSTmrStop() option to call 'callback' w/ timer arg. */ +#define OS_TMR_OPT_CALLBACK_ARG 4u /* OSTmrStop() option to call 'callback' w/ new arg. */ + +/* +********************************************************************************************************* +* TIMER STATES +********************************************************************************************************* +*/ +#define OS_TMR_STATE_UNUSED 0u +#define OS_TMR_STATE_STOPPED 1u +#define OS_TMR_STATE_COMPLETED 2u +#define OS_TMR_STATE_RUNNING 3u + +/* +********************************************************************************************************* +* ERROR CODES +********************************************************************************************************* +*/ +#define OS_ERR_NONE 0u + +#define OS_ERR_EVENT_TYPE 1u +#define OS_ERR_PEND_ISR 2u +#define OS_ERR_POST_NULL_PTR 3u +#define OS_ERR_PEVENT_NULL 4u +#define OS_ERR_POST_ISR 5u +#define OS_ERR_QUERY_ISR 6u +#define OS_ERR_INVALID_OPT 7u +#define OS_ERR_PDATA_NULL 9u + +#define OS_ERR_TIMEOUT 10u +#define OS_ERR_EVENT_NAME_TOO_LONG 11u +#define OS_ERR_PNAME_NULL 12u +#define OS_ERR_PEND_LOCKED 13u +#define OS_ERR_PEND_ABORT 14u +#define OS_ERR_DEL_ISR 15u +#define OS_ERR_CREATE_ISR 16u +#define OS_ERR_NAME_GET_ISR 17u +#define OS_ERR_NAME_SET_ISR 18u + +#define OS_ERR_MBOX_FULL 20u + +#define OS_ERR_Q_FULL 30u +#define OS_ERR_Q_EMPTY 31u + +#define OS_ERR_PRIO_EXIST 40u +#define OS_ERR_PRIO 41u +#define OS_ERR_PRIO_INVALID 42u + +#define OS_ERR_SEM_OVF 50u + +#define OS_ERR_TASK_CREATE_ISR 60u +#define OS_ERR_TASK_DEL 61u +#define OS_ERR_TASK_DEL_IDLE 62u +#define OS_ERR_TASK_DEL_REQ 63u +#define OS_ERR_TASK_DEL_ISR 64u +#define OS_ERR_TASK_NAME_TOO_LONG 65u +#define OS_ERR_TASK_NO_MORE_TCB 66u +#define OS_ERR_TASK_NOT_EXIST 67u +#define OS_ERR_TASK_NOT_SUSPENDED 68u +#define OS_ERR_TASK_OPT 69u +#define OS_ERR_TASK_RESUME_PRIO 70u +#define OS_ERR_TASK_SUSPEND_IDLE 71u +#define OS_ERR_TASK_SUSPEND_PRIO 72u +#define OS_ERR_TASK_WAITING 73u + +#define OS_ERR_TIME_NOT_DLY 80u +#define OS_ERR_TIME_INVALID_MINUTES 81u +#define OS_ERR_TIME_INVALID_SECONDS 82u +#define OS_ERR_TIME_INVALID_MS 83u +#define OS_ERR_TIME_ZERO_DLY 84u +#define OS_ERR_TIME_DLY_ISR 85u + +#define OS_ERR_MEM_INVALID_PART 90u +#define OS_ERR_MEM_INVALID_BLKS 91u +#define OS_ERR_MEM_INVALID_SIZE 92u +#define OS_ERR_MEM_NO_FREE_BLKS 93u +#define OS_ERR_MEM_FULL 94u +#define OS_ERR_MEM_INVALID_PBLK 95u +#define OS_ERR_MEM_INVALID_PMEM 96u +#define OS_ERR_MEM_INVALID_PDATA 97u +#define OS_ERR_MEM_INVALID_ADDR 98u +#define OS_ERR_MEM_NAME_TOO_LONG 99u + +#define OS_ERR_NOT_MUTEX_OWNER 100u + +#define OS_ERR_FLAG_INVALID_PGRP 110u +#define OS_ERR_FLAG_WAIT_TYPE 111u +#define OS_ERR_FLAG_NOT_RDY 112u +#define OS_ERR_FLAG_INVALID_OPT 113u +#define OS_ERR_FLAG_GRP_DEPLETED 114u +#define OS_ERR_FLAG_NAME_TOO_LONG 115u + +#define OS_ERR_PIP_LOWER 120u + +#define OS_ERR_TMR_INVALID_DLY 130u +#define OS_ERR_TMR_INVALID_PERIOD 131u +#define OS_ERR_TMR_INVALID_OPT 132u +#define OS_ERR_TMR_INVALID_NAME 133u +#define OS_ERR_TMR_NON_AVAIL 134u +#define OS_ERR_TMR_INACTIVE 135u +#define OS_ERR_TMR_INVALID_DEST 136u +#define OS_ERR_TMR_INVALID_TYPE 137u +#define OS_ERR_TMR_INVALID 138u +#define OS_ERR_TMR_ISR 139u +#define OS_ERR_TMR_NAME_TOO_LONG 140u +#define OS_ERR_TMR_INVALID_STATE 141u +#define OS_ERR_TMR_STOPPED 142u +#define OS_ERR_TMR_NO_CALLBACK 143u + +/* +********************************************************************************************************* +* OLD ERROR CODE NAMES (< V2.84) +********************************************************************************************************* +*/ +#define OS_NO_ERR OS_ERR_NONE +#define OS_TIMEOUT OS_ERR_TIMEOUT +#define OS_TASK_NOT_EXIST OS_ERR_TASK_NOT_EXIST +#define OS_MBOX_FULL OS_ERR_MBOX_FULL +#define OS_Q_FULL OS_ERR_Q_FULL +#define OS_Q_EMPTY OS_ERR_Q_EMPTY +#define OS_PRIO_EXIST OS_ERR_PRIO_EXIST +#define OS_PRIO_ERR OS_ERR_PRIO +#define OS_PRIO_INVALID OS_ERR_PRIO_INVALID +#define OS_SEM_OVF OS_ERR_SEM_OVF +#define OS_TASK_DEL_ERR OS_ERR_TASK_DEL +#define OS_TASK_DEL_IDLE OS_ERR_TASK_DEL_IDLE +#define OS_TASK_DEL_REQ OS_ERR_TASK_DEL_REQ +#define OS_TASK_DEL_ISR OS_ERR_TASK_DEL_ISR +#define OS_NO_MORE_TCB OS_ERR_TASK_NO_MORE_TCB +#define OS_TIME_NOT_DLY OS_ERR_TIME_NOT_DLY +#define OS_TIME_INVALID_MINUTES OS_ERR_TIME_INVALID_MINUTES +#define OS_TIME_INVALID_SECONDS OS_ERR_TIME_INVALID_SECONDS +#define OS_TIME_INVALID_MS OS_ERR_TIME_INVALID_MS +#define OS_TIME_ZERO_DLY OS_ERR_TIME_ZERO_DLY +#define OS_TASK_SUSPEND_PRIO OS_ERR_TASK_SUSPEND_PRIO +#define OS_TASK_SUSPEND_IDLE OS_ERR_TASK_SUSPEND_IDLE +#define OS_TASK_RESUME_PRIO OS_ERR_TASK_RESUME_PRIO +#define OS_TASK_NOT_SUSPENDED OS_ERR_TASK_NOT_SUSPENDED +#define OS_MEM_INVALID_PART OS_ERR_MEM_INVALID_PART +#define OS_MEM_INVALID_BLKS OS_ERR_MEM_INVALID_BLKS +#define OS_MEM_INVALID_SIZE OS_ERR_MEM_INVALID_SIZE +#define OS_MEM_NO_FREE_BLKS OS_ERR_MEM_NO_FREE_BLKS +#define OS_MEM_FULL OS_ERR_MEM_FULL +#define OS_MEM_INVALID_PBLK OS_ERR_MEM_INVALID_PBLK +#define OS_MEM_INVALID_PMEM OS_ERR_MEM_INVALID_PMEM +#define OS_MEM_INVALID_PDATA OS_ERR_MEM_INVALID_PDATA +#define OS_MEM_INVALID_ADDR OS_ERR_MEM_INVALID_ADDR +#define OS_MEM_NAME_TOO_LONG OS_ERR_MEM_NAME_TOO_LONG +#define OS_TASK_OPT_ERR OS_ERR_TASK_OPT +#define OS_FLAG_INVALID_PGRP OS_ERR_FLAG_INVALID_PGRP +#define OS_FLAG_ERR_WAIT_TYPE OS_ERR_FLAG_WAIT_TYPE +#define OS_FLAG_ERR_NOT_RDY OS_ERR_FLAG_NOT_RDY +#define OS_FLAG_INVALID_OPT OS_ERR_FLAG_INVALID_OPT +#define OS_FLAG_GRP_DEPLETED OS_ERR_FLAG_GRP_DEPLETED + +/*$PAGE*/ +/* +********************************************************************************************************* +* EVENT CONTROL BLOCK +********************************************************************************************************* +*/ + +#if (OS_EVENT_EN) && (OS_MAX_EVENTS > 0) +typedef struct os_event { + INT8U OSEventType; /* Type of event control block (see OS_EVENT_TYPE_xxxx) */ + void *OSEventPtr; /* Pointer to message or queue structure */ + INT16U OSEventCnt; /* Semaphore Count (not used if other EVENT type) */ +#if OS_LOWEST_PRIO <= 63 + INT8U OSEventGrp; /* Group corresponding to tasks waiting for event to occur */ + INT8U OSEventTbl[OS_EVENT_TBL_SIZE]; /* List of tasks waiting for event to occur */ +#else + INT16U OSEventGrp; /* Group corresponding to tasks waiting for event to occur */ + INT16U OSEventTbl[OS_EVENT_TBL_SIZE]; /* List of tasks waiting for event to occur */ +#endif + +#if OS_EVENT_NAME_SIZE > 1 + INT8U OSEventName[OS_EVENT_NAME_SIZE]; +#endif +} OS_EVENT; +#endif + + +/* +********************************************************************************************************* +* EVENT FLAGS CONTROL BLOCK +********************************************************************************************************* +*/ + +#if (OS_FLAG_EN > 0) && (OS_MAX_FLAGS > 0) + +#if OS_FLAGS_NBITS == 8 /* Determine the size of OS_FLAGS (8, 16 or 32 bits) */ +typedef INT8U OS_FLAGS; +#endif + +#if OS_FLAGS_NBITS == 16 +typedef INT16U OS_FLAGS; +#endif + +#if OS_FLAGS_NBITS == 32 +typedef INT32U OS_FLAGS; +#endif + + +typedef struct os_flag_grp { /* Event Flag Group */ + INT8U OSFlagType; /* Should be set to OS_EVENT_TYPE_FLAG */ + void *OSFlagWaitList; /* Pointer to first NODE of task waiting on event flag */ + OS_FLAGS OSFlagFlags; /* 8, 16 or 32 bit flags */ +#if OS_FLAG_NAME_SIZE > 1 + INT8U OSFlagName[OS_FLAG_NAME_SIZE]; +#endif +} OS_FLAG_GRP; + + + +typedef struct os_flag_node { /* Event Flag Wait List Node */ + void *OSFlagNodeNext; /* Pointer to next NODE in wait list */ + void *OSFlagNodePrev; /* Pointer to previous NODE in wait list */ + void *OSFlagNodeTCB; /* Pointer to TCB of waiting task */ + void *OSFlagNodeFlagGrp; /* Pointer to Event Flag Group */ + OS_FLAGS OSFlagNodeFlags; /* Event flag to wait on */ + INT8U OSFlagNodeWaitType; /* Type of wait: */ + /* OS_FLAG_WAIT_AND */ + /* OS_FLAG_WAIT_ALL */ + /* OS_FLAG_WAIT_OR */ + /* OS_FLAG_WAIT_ANY */ +} OS_FLAG_NODE; +#endif + +/*$PAGE*/ +/* +********************************************************************************************************* +* MESSAGE MAILBOX DATA +********************************************************************************************************* +*/ + +#if OS_MBOX_EN > 0 +typedef struct os_mbox_data { + void *OSMsg; /* Pointer to message in mailbox */ +#if OS_LOWEST_PRIO <= 63 + INT8U OSEventTbl[OS_EVENT_TBL_SIZE]; /* List of tasks waiting for event to occur */ + INT8U OSEventGrp; /* Group corresponding to tasks waiting for event to occur */ +#else + INT16U OSEventTbl[OS_EVENT_TBL_SIZE]; /* List of tasks waiting for event to occur */ + INT16U OSEventGrp; /* Group corresponding to tasks waiting for event to occur */ +#endif +} OS_MBOX_DATA; +#endif + +/* +********************************************************************************************************* +* MEMORY PARTITION DATA STRUCTURES +********************************************************************************************************* +*/ + +#if (OS_MEM_EN > 0) && (OS_MAX_MEM_PART > 0) +typedef struct os_mem { /* MEMORY CONTROL BLOCK */ + void *OSMemAddr; /* Pointer to beginning of memory partition */ + void *OSMemFreeList; /* Pointer to list of free memory blocks */ + INT32U OSMemBlkSize; /* Size (in bytes) of each block of memory */ + INT32U OSMemNBlks; /* Total number of blocks in this partition */ + INT32U OSMemNFree; /* Number of memory blocks remaining in this partition */ +#if OS_MEM_NAME_SIZE > 1 + INT8U OSMemName[OS_MEM_NAME_SIZE]; /* Memory partition name */ +#endif +} OS_MEM; + + +typedef struct os_mem_data { + void *OSAddr; /* Pointer to the beginning address of the memory partition */ + void *OSFreeList; /* Pointer to the beginning of the free list of memory blocks */ + INT32U OSBlkSize; /* Size (in bytes) of each memory block */ + INT32U OSNBlks; /* Total number of blocks in the partition */ + INT32U OSNFree; /* Number of memory blocks free */ + INT32U OSNUsed; /* Number of memory blocks used */ +} OS_MEM_DATA; +#endif + +/*$PAGE*/ +/* +********************************************************************************************************* +* MUTUAL EXCLUSION SEMAPHORE DATA +********************************************************************************************************* +*/ + +#if OS_MUTEX_EN > 0 +typedef struct os_mutex_data { +#if OS_LOWEST_PRIO <= 63 + INT8U OSEventTbl[OS_EVENT_TBL_SIZE]; /* List of tasks waiting for event to occur */ + INT8U OSEventGrp; /* Group corresponding to tasks waiting for event to occur */ +#else + INT16U OSEventTbl[OS_EVENT_TBL_SIZE]; /* List of tasks waiting for event to occur */ + INT16U OSEventGrp; /* Group corresponding to tasks waiting for event to occur */ +#endif + BOOLEAN OSValue; /* Mutex value (OS_FALSE = used, OS_TRUE = available) */ + INT8U OSOwnerPrio; /* Mutex owner's task priority or 0xFF if no owner */ + INT8U OSMutexPIP; /* Priority Inheritance Priority or 0xFF if no owner */ +} OS_MUTEX_DATA; +#endif + +/* +********************************************************************************************************* +* MESSAGE QUEUE DATA +********************************************************************************************************* +*/ + +#if OS_Q_EN > 0 +typedef struct os_q { /* QUEUE CONTROL BLOCK */ + struct os_q *OSQPtr; /* Link to next queue control block in list of free blocks */ + void **OSQStart; /* Pointer to start of queue data */ + void **OSQEnd; /* Pointer to end of queue data */ + void **OSQIn; /* Pointer to where next message will be inserted in the Q */ + void **OSQOut; /* Pointer to where next message will be extracted from the Q */ + INT16U OSQSize; /* Size of queue (maximum number of entries) */ + INT16U OSQEntries; /* Current number of entries in the queue */ +} OS_Q; + + +typedef struct os_q_data { + void *OSMsg; /* Pointer to next message to be extracted from queue */ + INT16U OSNMsgs; /* Number of messages in message queue */ + INT16U OSQSize; /* Size of message queue */ +#if OS_LOWEST_PRIO <= 63 + INT8U OSEventTbl[OS_EVENT_TBL_SIZE]; /* List of tasks waiting for event to occur */ + INT8U OSEventGrp; /* Group corresponding to tasks waiting for event to occur */ +#else + INT16U OSEventTbl[OS_EVENT_TBL_SIZE]; /* List of tasks waiting for event to occur */ + INT16U OSEventGrp; /* Group corresponding to tasks waiting for event to occur */ +#endif +} OS_Q_DATA; +#endif + +/* +********************************************************************************************************* +* SEMAPHORE DATA +********************************************************************************************************* +*/ + +#if OS_SEM_EN > 0 +typedef struct os_sem_data { + INT16U OSCnt; /* Semaphore count */ +#if OS_LOWEST_PRIO <= 63 + INT8U OSEventTbl[OS_EVENT_TBL_SIZE]; /* List of tasks waiting for event to occur */ + INT8U OSEventGrp; /* Group corresponding to tasks waiting for event to occur */ +#else + INT16U OSEventTbl[OS_EVENT_TBL_SIZE]; /* List of tasks waiting for event to occur */ + INT16U OSEventGrp; /* Group corresponding to tasks waiting for event to occur */ +#endif +} OS_SEM_DATA; +#endif + +/* +********************************************************************************************************* +* TASK STACK DATA +********************************************************************************************************* +*/ + +#if OS_TASK_CREATE_EXT_EN > 0 +typedef struct os_stk_data { + INT32U OSFree; /* Number of free bytes on the stack */ + INT32U OSUsed; /* Number of bytes used on the stack */ +} OS_STK_DATA; +#endif + +/*$PAGE*/ +/* +********************************************************************************************************* +* TASK CONTROL BLOCK +********************************************************************************************************* +*/ + +typedef struct os_tcb { + OS_STK *OSTCBStkPtr; /* Pointer to current top of stack */ + +#if OS_TASK_CREATE_EXT_EN > 0 + void *OSTCBExtPtr; /* Pointer to user definable data for TCB extension */ + OS_STK *OSTCBStkBottom; /* Pointer to bottom of stack */ + INT32U OSTCBStkSize; /* Size of task stack (in number of stack elements) */ + INT16U OSTCBOpt; /* Task options as passed by OSTaskCreateExt() */ + INT16U OSTCBId; /* Task ID (0..65535) */ +#endif + + struct os_tcb *OSTCBNext; /* Pointer to next TCB in the TCB list */ + struct os_tcb *OSTCBPrev; /* Pointer to previous TCB in the TCB list */ + +#if (OS_EVENT_EN) || (OS_FLAG_EN > 0) + OS_EVENT *OSTCBEventPtr; /* Pointer to event control block */ +#endif + +#if (OS_EVENT_EN) && (OS_EVENT_MULTI_EN > 0) + OS_EVENT **OSTCBEventMultiPtr; /* Pointer to multiple event control blocks */ +#endif + +#if ((OS_Q_EN > 0) && (OS_MAX_QS > 0)) || (OS_MBOX_EN > 0) + void *OSTCBMsg; /* Message received from OSMboxPost() or OSQPost() */ +#endif + +#if (OS_FLAG_EN > 0) && (OS_MAX_FLAGS > 0) +#if OS_TASK_DEL_EN > 0 + OS_FLAG_NODE *OSTCBFlagNode; /* Pointer to event flag node */ +#endif + OS_FLAGS OSTCBFlagsRdy; /* Event flags that made task ready to run */ +#endif + + INT16U OSTCBDly; /* Nbr ticks to delay task or, timeout waiting for event */ + INT8U OSTCBStat; /* Task status */ + INT8U OSTCBStatPend; /* Task PEND status */ + INT8U OSTCBPrio; /* Task priority (0 == highest) */ + + INT8U OSTCBX; /* Bit position in group corresponding to task priority */ + INT8U OSTCBY; /* Index into ready table corresponding to task priority */ +#if OS_LOWEST_PRIO <= 63 + INT8U OSTCBBitX; /* Bit mask to access bit position in ready table */ + INT8U OSTCBBitY; /* Bit mask to access bit position in ready group */ +#else + INT16U OSTCBBitX; /* Bit mask to access bit position in ready table */ + INT16U OSTCBBitY; /* Bit mask to access bit position in ready group */ +#endif + +#if OS_TASK_DEL_EN > 0 + INT8U OSTCBDelReq; /* Indicates whether a task needs to delete itself */ +#endif + +#if OS_TASK_PROFILE_EN > 0 + INT32U OSTCBCtxSwCtr; /* Number of time the task was switched in */ + INT32U OSTCBCyclesTot; /* Total number of clock cycles the task has been running */ + INT32U OSTCBCyclesStart; /* Snapshot of cycle counter at start of task resumption */ + OS_STK *OSTCBStkBase; /* Pointer to the beginning of the task stack */ + INT32U OSTCBStkUsed; /* Number of bytes used from the stack */ +#endif + +#if OS_TASK_NAME_SIZE > 1 + INT8U OSTCBTaskName[OS_TASK_NAME_SIZE]; +#endif +} OS_TCB; + +/*$PAGE*/ +/* +************************************************************************************************************************ +* TIMER DATA TYPES +************************************************************************************************************************ +*/ + +#if OS_TMR_EN > 0 +typedef void (*OS_TMR_CALLBACK)(void *ptmr, void *parg); + + + +typedef struct os_tmr { + INT8U OSTmrType; /* Should be set to OS_TMR_TYPE */ + OS_TMR_CALLBACK OSTmrCallback; /* Function to call when timer expires */ + void *OSTmrCallbackArg; /* Argument to pass to function when timer expires */ + void *OSTmrNext; /* Double link list pointers */ + void *OSTmrPrev; + INT32U OSTmrMatch; /* Timer expires when OSTmrTime == OSTmrMatch */ + INT32U OSTmrDly; /* Delay time before periodic update starts */ + INT32U OSTmrPeriod; /* Period to repeat timer */ +#if OS_TMR_CFG_NAME_SIZE > 0 + INT8U OSTmrName[OS_TMR_CFG_NAME_SIZE]; /* Name to give the timer */ +#endif + INT8U OSTmrOpt; /* Options (see OS_TMR_OPT_xxx) */ + INT8U OSTmrState; /* Indicates the state of the timer: */ + /* OS_TMR_STATE_UNUSED */ + /* OS_TMR_STATE_RUNNING */ + /* OS_TMR_STATE_STOPPED */ +} OS_TMR; + + + +typedef struct os_tmr_wheel { + OS_TMR *OSTmrFirst; /* Pointer to first timer in linked list */ + INT16U OSTmrEntries; +} OS_TMR_WHEEL; +#endif + +/*$PAGE*/ +/* +********************************************************************************************************* +* GLOBAL VARIABLES +********************************************************************************************************* +*/ + +OS_EXT INT32U OSCtxSwCtr; /* Counter of number of context switches */ + +#if (OS_EVENT_EN) && (OS_MAX_EVENTS > 0) +OS_EXT OS_EVENT *OSEventFreeList; /* Pointer to list of free EVENT control blocks */ +OS_EXT OS_EVENT OSEventTbl[OS_MAX_EVENTS];/* Table of EVENT control blocks */ +#endif + +#if (OS_FLAG_EN > 0) && (OS_MAX_FLAGS > 0) +OS_EXT OS_FLAG_GRP OSFlagTbl[OS_MAX_FLAGS]; /* Table containing event flag groups */ +OS_EXT OS_FLAG_GRP *OSFlagFreeList; /* Pointer to free list of event flag groups */ +#endif + +#if OS_TASK_STAT_EN > 0 +OS_EXT INT8U OSCPUUsage; /* Percentage of CPU used */ +OS_EXT INT32U OSIdleCtrMax; /* Max. value that idle ctr can take in 1 sec. */ +OS_EXT INT32U OSIdleCtrRun; /* Val. reached by idle ctr at run time in 1 sec. */ +OS_EXT BOOLEAN OSStatRdy; /* Flag indicating that the statistic task is rdy */ +OS_EXT OS_STK OSTaskStatStk[OS_TASK_STAT_STK_SIZE]; /* Statistics task stack */ +#endif + +OS_EXT INT8U OSIntNesting; /* Interrupt nesting level */ + +OS_EXT INT8U OSLockNesting; /* Multitasking lock nesting level */ + +OS_EXT INT8U OSPrioCur; /* Priority of current task */ +OS_EXT INT8U OSPrioHighRdy; /* Priority of highest priority task */ + +#if OS_LOWEST_PRIO <= 63 +OS_EXT INT8U OSRdyGrp; /* Ready list group */ +OS_EXT INT8U OSRdyTbl[OS_RDY_TBL_SIZE]; /* Table of tasks which are ready to run */ +#else +OS_EXT INT16U OSRdyGrp; /* Ready list group */ +OS_EXT INT16U OSRdyTbl[OS_RDY_TBL_SIZE]; /* Table of tasks which are ready to run */ +#endif + +OS_EXT BOOLEAN OSRunning; /* Flag indicating that kernel is running */ + +OS_EXT INT8U OSTaskCtr; /* Number of tasks created */ + +OS_EXT volatile INT32U OSIdleCtr; /* Idle counter */ + +OS_EXT OS_STK OSTaskIdleStk[OS_TASK_IDLE_STK_SIZE]; /* Idle task stack */ + + +OS_EXT OS_TCB *OSTCBCur; /* Pointer to currently running TCB */ +OS_EXT OS_TCB *OSTCBFreeList; /* Pointer to list of free TCBs */ +OS_EXT OS_TCB *OSTCBHighRdy; /* Pointer to highest priority TCB R-to-R */ +OS_EXT OS_TCB *OSTCBList; /* Pointer to doubly linked list of TCBs */ +OS_EXT OS_TCB *OSTCBPrioTbl[OS_LOWEST_PRIO + 1];/* Table of pointers to created TCBs */ +OS_EXT OS_TCB OSTCBTbl[OS_MAX_TASKS + OS_N_SYS_TASKS]; /* Table of TCBs */ + +#if OS_TICK_STEP_EN > 0 +OS_EXT INT8U OSTickStepState; /* Indicates the state of the tick step feature */ +#endif + +#if (OS_MEM_EN > 0) && (OS_MAX_MEM_PART > 0) +OS_EXT OS_MEM *OSMemFreeList; /* Pointer to free list of memory partitions */ +OS_EXT OS_MEM OSMemTbl[OS_MAX_MEM_PART];/* Storage for memory partition manager */ +#endif + +#if (OS_Q_EN > 0) && (OS_MAX_QS > 0) +OS_EXT OS_Q *OSQFreeList; /* Pointer to list of free QUEUE control blocks */ +OS_EXT OS_Q OSQTbl[OS_MAX_QS]; /* Table of QUEUE control blocks */ +#endif + +#if OS_TIME_GET_SET_EN > 0 +OS_EXT volatile INT32U OSTime; /* Current value of system time (in ticks) */ +#endif + +#if OS_TMR_EN > 0 +OS_EXT INT16U OSTmrFree; /* Number of free entries in the timer pool */ +OS_EXT INT16U OSTmrUsed; /* Number of timers used */ +OS_EXT INT32U OSTmrTime; /* Current timer time */ + +OS_EXT OS_EVENT *OSTmrSem; /* Sem. used to gain exclusive access to timers */ +OS_EXT OS_EVENT *OSTmrSemSignal; /* Sem. used to signal the update of timers */ + +OS_EXT OS_TMR OSTmrTbl[OS_TMR_CFG_MAX]; /* Table containing pool of timers */ +OS_EXT OS_TMR *OSTmrFreeList; /* Pointer to free list of timers */ +OS_EXT OS_STK OSTmrTaskStk[OS_TASK_TMR_STK_SIZE]; + +OS_EXT OS_TMR_WHEEL OSTmrWheelTbl[OS_TMR_CFG_WHEEL_SIZE]; +#endif + +extern INT8U const OSUnMapTbl[256]; /* Priority->Index lookup table */ + +/*$PAGE*/ +/* +********************************************************************************************************* +* FUNCTION PROTOTYPES +* (Target Independent Functions) +********************************************************************************************************* +*/ + +/* +********************************************************************************************************* +* MISCELLANEOUS +********************************************************************************************************* +*/ + +#if (OS_EVENT_EN) + +#if (OS_EVENT_NAME_SIZE > 1) +INT8U OSEventNameGet (OS_EVENT *pevent, + INT8U *pname, + INT8U *perr); + +void OSEventNameSet (OS_EVENT *pevent, + INT8U *pname, + INT8U *perr); +#endif + +#if (OS_EVENT_MULTI_EN > 0) +INT16U OSEventPendMulti (OS_EVENT **pevents_pend, + OS_EVENT **pevents_rdy, + void **pmsgs_rdy, + INT16U timeout, + INT8U *perr); +#endif + +#endif + +/* +********************************************************************************************************* +* EVENT FLAGS MANAGEMENT +********************************************************************************************************* +*/ + +#if (OS_FLAG_EN > 0) && (OS_MAX_FLAGS > 0) + +#if OS_FLAG_ACCEPT_EN > 0 +OS_FLAGS OSFlagAccept (OS_FLAG_GRP *pgrp, + OS_FLAGS flags, + INT8U wait_type, + INT8U *perr); +#endif + +OS_FLAG_GRP *OSFlagCreate (OS_FLAGS flags, + INT8U *perr); + +#if OS_FLAG_DEL_EN > 0 +OS_FLAG_GRP *OSFlagDel (OS_FLAG_GRP *pgrp, + INT8U opt, + INT8U *perr); +#endif + +#if (OS_FLAG_EN > 0) && (OS_FLAG_NAME_SIZE > 1) +INT8U OSFlagNameGet (OS_FLAG_GRP *pgrp, + INT8U *pname, + INT8U *perr); + +void OSFlagNameSet (OS_FLAG_GRP *pgrp, + INT8U *pname, + INT8U *perr); +#endif + +OS_FLAGS OSFlagPend (OS_FLAG_GRP *pgrp, + OS_FLAGS flags, + INT8U wait_type, + INT16U timeout, + INT8U *perr); + +OS_FLAGS OSFlagPendGetFlagsRdy (void); +OS_FLAGS OSFlagPost (OS_FLAG_GRP *pgrp, + OS_FLAGS flags, + INT8U opt, + INT8U *perr); + +#if OS_FLAG_QUERY_EN > 0 +OS_FLAGS OSFlagQuery (OS_FLAG_GRP *pgrp, + INT8U *perr); +#endif +#endif + +/* +********************************************************************************************************* +* MESSAGE MAILBOX MANAGEMENT +********************************************************************************************************* +*/ + +#if OS_MBOX_EN > 0 + +#if OS_MBOX_ACCEPT_EN > 0 +void *OSMboxAccept (OS_EVENT *pevent); +#endif + +OS_EVENT *OSMboxCreate (void *pmsg); + +#if OS_MBOX_DEL_EN > 0 +OS_EVENT *OSMboxDel (OS_EVENT *pevent, + INT8U opt, + INT8U *perr); +#endif + +void *OSMboxPend (OS_EVENT *pevent, + INT16U timeout, + INT8U *perr); + +#if OS_MBOX_PEND_ABORT_EN > 0 +INT8U OSMboxPendAbort (OS_EVENT *pevent, + INT8U opt, + INT8U *perr); +#endif + +#if OS_MBOX_POST_EN > 0 +INT8U OSMboxPost (OS_EVENT *pevent, + void *pmsg); +#endif + +#if OS_MBOX_POST_OPT_EN > 0 +INT8U OSMboxPostOpt (OS_EVENT *pevent, + void *pmsg, + INT8U opt); +#endif + +#if OS_MBOX_QUERY_EN > 0 +INT8U OSMboxQuery (OS_EVENT *pevent, + OS_MBOX_DATA *p_mbox_data); +#endif +#endif + +/* +********************************************************************************************************* +* MEMORY MANAGEMENT +********************************************************************************************************* +*/ + +#if (OS_MEM_EN > 0) && (OS_MAX_MEM_PART > 0) + +OS_MEM *OSMemCreate (void *addr, + INT32U nblks, + INT32U blksize, + INT8U *perr); + +void *OSMemGet (OS_MEM *pmem, + INT8U *perr); +#if OS_MEM_NAME_SIZE > 1 +INT8U OSMemNameGet (OS_MEM *pmem, + INT8U *pname, + INT8U *perr); + +void OSMemNameSet (OS_MEM *pmem, + INT8U *pname, + INT8U *perr); +#endif +INT8U OSMemPut (OS_MEM *pmem, + void *pblk); + +#if OS_MEM_QUERY_EN > 0 +INT8U OSMemQuery (OS_MEM *pmem, + OS_MEM_DATA *p_mem_data); +#endif + +#endif + +/* +********************************************************************************************************* +* MUTUAL EXCLUSION SEMAPHORE MANAGEMENT +********************************************************************************************************* +*/ + +#if OS_MUTEX_EN > 0 + +#if OS_MUTEX_ACCEPT_EN > 0 +BOOLEAN OSMutexAccept (OS_EVENT *pevent, + INT8U *perr); +#endif + +OS_EVENT *OSMutexCreate (INT8U prio, + INT8U *perr); + +#if OS_MUTEX_DEL_EN > 0 +OS_EVENT *OSMutexDel (OS_EVENT *pevent, + INT8U opt, + INT8U *perr); +#endif + +void OSMutexPend (OS_EVENT *pevent, + INT16U timeout, + INT8U *perr); + +INT8U OSMutexPost (OS_EVENT *pevent); + +#if OS_MUTEX_QUERY_EN > 0 +INT8U OSMutexQuery (OS_EVENT *pevent, + OS_MUTEX_DATA *p_mutex_data); +#endif + +#endif + +/*$PAGE*/ +/* +********************************************************************************************************* +* MESSAGE QUEUE MANAGEMENT +********************************************************************************************************* +*/ + +#if (OS_Q_EN > 0) && (OS_MAX_QS > 0) + +#if OS_Q_ACCEPT_EN > 0 +void *OSQAccept (OS_EVENT *pevent, + INT8U *perr); +#endif + +OS_EVENT *OSQCreate (void **start, + INT16U size); + +#if OS_Q_DEL_EN > 0 +OS_EVENT *OSQDel (OS_EVENT *pevent, + INT8U opt, + INT8U *perr); +#endif + +#if OS_Q_FLUSH_EN > 0 +INT8U OSQFlush (OS_EVENT *pevent); +#endif + +void *OSQPend (OS_EVENT *pevent, + INT16U timeout, + INT8U *perr); + +#if OS_Q_PEND_ABORT_EN > 0 +INT8U OSQPendAbort (OS_EVENT *pevent, + INT8U opt, + INT8U *perr); +#endif + +#if OS_Q_POST_EN > 0 +INT8U OSQPost (OS_EVENT *pevent, + void *pmsg); +#endif + +#if OS_Q_POST_FRONT_EN > 0 +INT8U OSQPostFront (OS_EVENT *pevent, + void *pmsg); +#endif + +#if OS_Q_POST_OPT_EN > 0 +INT8U OSQPostOpt (OS_EVENT *pevent, + void *pmsg, + INT8U opt); +#endif + +#if OS_Q_QUERY_EN > 0 +INT8U OSQQuery (OS_EVENT *pevent, + OS_Q_DATA *p_q_data); +#endif + +#endif + +/*$PAGE*/ +/* +********************************************************************************************************* +* SEMAPHORE MANAGEMENT +********************************************************************************************************* +*/ +#if OS_SEM_EN > 0 + +#if OS_SEM_ACCEPT_EN > 0 +INT16U OSSemAccept (OS_EVENT *pevent); +#endif + +OS_EVENT *OSSemCreate (INT16U cnt); + +#if OS_SEM_DEL_EN > 0 +OS_EVENT *OSSemDel (OS_EVENT *pevent, + INT8U opt, + INT8U *perr); +#endif + +void OSSemPend (OS_EVENT *pevent, + INT16U timeout, + INT8U *perr); + +#if OS_SEM_PEND_ABORT_EN > 0 +INT8U OSSemPendAbort (OS_EVENT *pevent, + INT8U opt, + INT8U *perr); +#endif + +INT8U OSSemPost (OS_EVENT *pevent); + +#if OS_SEM_QUERY_EN > 0 +INT8U OSSemQuery (OS_EVENT *pevent, + OS_SEM_DATA *p_sem_data); +#endif + +#if OS_SEM_SET_EN > 0 +void OSSemSet (OS_EVENT *pevent, + INT16U cnt, + INT8U *perr); +#endif + +#endif + +/*$PAGE*/ +/* +********************************************************************************************************* +* TASK MANAGEMENT +********************************************************************************************************* +*/ +#if OS_TASK_CHANGE_PRIO_EN > 0 +INT8U OSTaskChangePrio (INT8U oldprio, + INT8U newprio); +#endif + +#if OS_TASK_CREATE_EN > 0 +INT8U OSTaskCreate (void (*task)(void *p_arg), + void *p_arg, + OS_STK *ptos, + INT8U prio); +#endif + +#if OS_TASK_CREATE_EXT_EN > 0 +INT8U OSTaskCreateExt (void (*task)(void *p_arg), + void *p_arg, + OS_STK *ptos, + INT8U prio, + INT16U id, + OS_STK *pbos, + INT32U stk_size, + void *pext, + INT16U opt); +#endif + +#if OS_TASK_DEL_EN > 0 +INT8U OSTaskDel (INT8U prio); +INT8U OSTaskDelReq (INT8U prio); +#endif + +#if OS_TASK_NAME_SIZE > 1 +INT8U OSTaskNameGet (INT8U prio, + INT8U *pname, + INT8U *perr); + +void OSTaskNameSet (INT8U prio, + INT8U *pname, + INT8U *perr); +#endif + +#if OS_TASK_SUSPEND_EN > 0 +INT8U OSTaskResume (INT8U prio); +INT8U OSTaskSuspend (INT8U prio); +#endif + +#if (OS_TASK_STAT_STK_CHK_EN > 0) && (OS_TASK_CREATE_EXT_EN > 0) +INT8U OSTaskStkChk (INT8U prio, + OS_STK_DATA *p_stk_data); +#endif + +#if OS_TASK_QUERY_EN > 0 +INT8U OSTaskQuery (INT8U prio, + OS_TCB *p_task_data); +#endif + +/*$PAGE*/ +/* +********************************************************************************************************* +* TIME MANAGEMENT +********************************************************************************************************* +*/ + +void OSTimeDly (INT16U ticks); + +#if OS_TIME_DLY_HMSM_EN > 0 +INT8U OSTimeDlyHMSM (INT8U hours, + INT8U minutes, + INT8U seconds, + INT16U milli); +#endif + +#if OS_TIME_DLY_RESUME_EN > 0 +INT8U OSTimeDlyResume (INT8U prio); +#endif + +#if OS_TIME_GET_SET_EN > 0 +INT32U OSTimeGet (void); +void OSTimeSet (INT32U ticks); +#endif + +void OSTimeTick (void); + +/* +********************************************************************************************************* +* TIMER MANAGEMENT +********************************************************************************************************* +*/ + +#if OS_TMR_EN > 0 +OS_TMR *OSTmrCreate (INT32U dly, + INT32U period, + INT8U opt, + OS_TMR_CALLBACK callback, + void *callback_arg, + INT8U *pname, + INT8U *perr); + +BOOLEAN OSTmrDel (OS_TMR *ptmr, + INT8U *perr); + +#if OS_TMR_CFG_NAME_SIZE > 0 +INT8U OSTmrNameGet (OS_TMR *ptmr, + INT8U *pdest, + INT8U *perr); +#endif +INT32U OSTmrRemainGet (OS_TMR *ptmr, + INT8U *perr); + +INT8U OSTmrStateGet (OS_TMR *ptmr, + INT8U *perr); + +BOOLEAN OSTmrStart (OS_TMR *ptmr, + INT8U *perr); + +BOOLEAN OSTmrStop (OS_TMR *ptmr, + INT8U opt, + void *callback_arg, + INT8U *perr); + +INT8U OSTmrSignal (void); +#endif + +/* +********************************************************************************************************* +* MISCELLANEOUS +********************************************************************************************************* +*/ + +void OSInit (void); + +void OSIntEnter (void); +void OSIntExit (void); + +#if OS_SCHED_LOCK_EN > 0 +void OSSchedLock (void); +void OSSchedUnlock (void); +#endif + +void OSStart (void); + +void OSStatInit (void); + +INT16U OSVersion (void); + +/*$PAGE*/ +/* +********************************************************************************************************* +* INTERNAL FUNCTION PROTOTYPES +* (Your application MUST NOT call these functions) +********************************************************************************************************* +*/ + +#if OS_TASK_DEL_EN > 0 +void OS_Dummy (void); +#endif + +#if (OS_EVENT_EN) +INT8U OS_EventTaskRdy (OS_EVENT *pevent, + void *pmsg, + INT8U msk, + INT8U pend_stat); + +void OS_EventTaskWait (OS_EVENT *pevent); + +void OS_EventTaskRemove (OS_TCB *ptcb, + OS_EVENT *pevent); + +#if (OS_EVENT_MULTI_EN > 0) +void OS_EventTaskWaitMulti (OS_EVENT **pevents_wait); + +void OS_EventTaskRemoveMulti (OS_TCB *ptcb, + OS_EVENT **pevents_multi); +#endif + +void OS_EventWaitListInit (OS_EVENT *pevent); +#endif + +#if (OS_FLAG_EN > 0) && (OS_MAX_FLAGS > 0) +void OS_FlagInit (void); +void OS_FlagUnlink (OS_FLAG_NODE *pnode); +#endif + +void OS_MemClr (INT8U *pdest, + INT16U size); + +void OS_MemCopy (INT8U *pdest, + INT8U *psrc, + INT16U size); + +#if (OS_MEM_EN > 0) && (OS_MAX_MEM_PART > 0) +void OS_MemInit (void); +#endif + +#if OS_Q_EN > 0 +void OS_QInit (void); +#endif + +void OS_Sched (void); + +#if (OS_EVENT_NAME_SIZE > 1) || (OS_FLAG_NAME_SIZE > 1) || (OS_MEM_NAME_SIZE > 1) || (OS_TASK_NAME_SIZE > 1) +INT8U OS_StrCopy (INT8U *pdest, + INT8U *psrc); + +INT8U OS_StrLen (INT8U *psrc); +#endif + +void OS_TaskIdle (void *p_arg); + +#if OS_TASK_STAT_EN > 0 +void OS_TaskStat (void *p_arg); +#endif + +#if (OS_TASK_STAT_STK_CHK_EN > 0) && (OS_TASK_CREATE_EXT_EN > 0) +void OS_TaskStkClr (OS_STK *pbos, + INT32U size, + INT16U opt); +#endif + +#if (OS_TASK_STAT_STK_CHK_EN > 0) && (OS_TASK_CREATE_EXT_EN > 0) +void OS_TaskStatStkChk (void); +#endif + +INT8U OS_TCBInit (INT8U prio, + OS_STK *ptos, + OS_STK *pbos, + INT16U id, + INT32U stk_size, + void *pext, + INT16U opt); + +#if OS_TMR_EN > 0 +void OSTmr_Init (void); +#endif + +/*$PAGE*/ +/* +********************************************************************************************************* +* FUNCTION PROTOTYPES +* (Target Specific Functions) +********************************************************************************************************* +*/ + +#if OS_DEBUG_EN > 0 +void OSDebugInit (void); +#endif + +void OSInitHookBegin (void); +void OSInitHookEnd (void); + +void OSTaskCreateHook (OS_TCB *ptcb); +void OSTaskDelHook (OS_TCB *ptcb); + +void OSTaskIdleHook (void); + +void OSTaskStatHook (void); +OS_STK *OSTaskStkInit (void (*task)(void *p_arg), + void *p_arg, + OS_STK *ptos, + INT16U opt); + +#if OS_TASK_SW_HOOK_EN > 0 +void OSTaskSwHook (void); +#endif + +void OSTCBInitHook (OS_TCB *ptcb); + +#if OS_TIME_TICK_HOOK_EN > 0 +void OSTimeTickHook (void); +#endif + +/*$PAGE*/ +/* +********************************************************************************************************* +* FUNCTION PROTOTYPES +* (Application Specific Functions) +********************************************************************************************************* +*/ + +#if OS_APP_HOOKS_EN > 0 +void App_TaskCreateHook (OS_TCB *ptcb); +void App_TaskDelHook (OS_TCB *ptcb); +void App_TaskIdleHook (void); + +void App_TaskStatHook (void); + +#if OS_TASK_SW_HOOK_EN > 0 +void App_TaskSwHook (void); +#endif + +void App_TCBInitHook (OS_TCB *ptcb); + +#if OS_TIME_TICK_HOOK_EN > 0 +void App_TimeTickHook (void); +#endif +#endif + +/* +********************************************************************************************************* +* FUNCTION PROTOTYPES +* +* IMPORTANT: These prototypes MUST be placed in OS_CPU.H +********************************************************************************************************* +*/ + +#if 0 +void OSStartHighRdy (void); +void OSIntCtxSw (void); +void OSCtxSw (void); +#endif + +/*$PAGE*/ +/* +********************************************************************************************************* +* LOOK FOR MISSING #define CONSTANTS +* +* This section is used to generate ERROR messages at compile time if certain #define constants are +* MISSING in OS_CFG.H. This allows you to quickly determine the source of the error. +* +* You SHOULD NOT change this section UNLESS you would like to add more comments as to the source of the +* compile time error. +********************************************************************************************************* +*/ + +/* +********************************************************************************************************* +* EVENT FLAGS +********************************************************************************************************* +*/ + +#ifndef OS_FLAG_EN +#error "OS_CFG.H, Missing OS_FLAG_EN: Enable (1) or Disable (0) code generation for Event Flags" +#else + #ifndef OS_MAX_FLAGS + #error "OS_CFG.H, Missing OS_MAX_FLAGS: Max. number of Event Flag Groups in your application" + #else + #if OS_MAX_FLAGS > 65500u + #error "OS_CFG.H, OS_MAX_FLAGS must be <= 65500" + #endif + #endif + + #ifndef OS_FLAGS_NBITS + #error "OS_CFG.H, Missing OS_FLAGS_NBITS: Determine #bits used for event flags, MUST be either 8, 16 or 32" + #endif + + #ifndef OS_FLAG_WAIT_CLR_EN + #error "OS_CFG.H, Missing OS_FLAG_WAIT_CLR_EN: Include code for Wait on Clear EVENT FLAGS" + #endif + + #ifndef OS_FLAG_ACCEPT_EN + #error "OS_CFG.H, Missing OS_FLAG_ACCEPT_EN: Include code for OSFlagAccept()" + #endif + + #ifndef OS_FLAG_DEL_EN + #error "OS_CFG.H, Missing OS_FLAG_DEL_EN: Include code for OSFlagDel()" + #endif + + #ifndef OS_FLAG_NAME_SIZE + #error "OS_CFG.H, Missing OS_FLAG_NAME_SIZE: Determines the size of flag group names" + #endif + + #ifndef OS_FLAG_QUERY_EN + #error "OS_CFG.H, Missing OS_FLAG_QUERY_EN: Include code for OSFlagQuery()" + #endif +#endif + +/* +********************************************************************************************************* +* MESSAGE MAILBOXES +********************************************************************************************************* +*/ + +#ifndef OS_MBOX_EN +#error "OS_CFG.H, Missing OS_MBOX_EN: Enable (1) or Disable (0) code generation for MAILBOXES" +#else + #ifndef OS_MBOX_ACCEPT_EN + #error "OS_CFG.H, Missing OS_MBOX_ACCEPT_EN: Include code for OSMboxAccept()" + #endif + + #ifndef OS_MBOX_DEL_EN + #error "OS_CFG.H, Missing OS_MBOX_DEL_EN: Include code for OSMboxDel()" + #endif + + #ifndef OS_MBOX_PEND_ABORT_EN + #error "OS_CFG.H, Missing OS_MBOX_PEND_ABORT_EN: Include code for OSMboxPendAbort()" + #endif + + #ifndef OS_MBOX_POST_EN + #error "OS_CFG.H, Missing OS_MBOX_POST_EN: Include code for OSMboxPost()" + #endif + + #ifndef OS_MBOX_POST_OPT_EN + #error "OS_CFG.H, Missing OS_MBOX_POST_OPT_EN: Include code for OSMboxPostOpt()" + #endif + + #ifndef OS_MBOX_QUERY_EN + #error "OS_CFG.H, Missing OS_MBOX_QUERY_EN: Include code for OSMboxQuery()" + #endif +#endif + +/* +********************************************************************************************************* +* MEMORY MANAGEMENT +********************************************************************************************************* +*/ + +#ifndef OS_MEM_EN +#error "OS_CFG.H, Missing OS_MEM_EN: Enable (1) or Disable (0) code generation for MEMORY MANAGER" +#else + #ifndef OS_MAX_MEM_PART + #error "OS_CFG.H, Missing OS_MAX_MEM_PART: Max. number of memory partitions" + #else + #if OS_MAX_MEM_PART > 65500u + #error "OS_CFG.H, OS_MAX_MEM_PART must be <= 65500" + #endif + #endif + + #ifndef OS_MEM_NAME_SIZE + #error "OS_CFG.H, Missing OS_MEM_NAME_SIZE: Determines the size of memory partition names" + #endif + + #ifndef OS_MEM_QUERY_EN + #error "OS_CFG.H, Missing OS_MEM_QUERY_EN: Include code for OSMemQuery()" + #endif +#endif + +/* +********************************************************************************************************* +* MUTUAL EXCLUSION SEMAPHORES +********************************************************************************************************* +*/ + +#ifndef OS_MUTEX_EN +#error "OS_CFG.H, Missing OS_MUTEX_EN: Enable (1) or Disable (0) code generation for MUTEX" +#else + #ifndef OS_MUTEX_ACCEPT_EN + #error "OS_CFG.H, Missing OS_MUTEX_ACCEPT_EN: Include code for OSMutexAccept()" + #endif + + #ifndef OS_MUTEX_DEL_EN + #error "OS_CFG.H, Missing OS_MUTEX_DEL_EN: Include code for OSMutexDel()" + #endif + + #ifndef OS_MUTEX_QUERY_EN + #error "OS_CFG.H, Missing OS_MUTEX_QUERY_EN: Include code for OSMutexQuery()" + #endif +#endif + +/* +********************************************************************************************************* +* MESSAGE QUEUES +********************************************************************************************************* +*/ + +#ifndef OS_Q_EN +#error "OS_CFG.H, Missing OS_Q_EN: Enable (1) or Disable (0) code generation for QUEUES" +#else + #ifndef OS_MAX_QS + #error "OS_CFG.H, Missing OS_MAX_QS: Max. number of queue control blocks" + #else + #if OS_MAX_QS > 65500u + #error "OS_CFG.H, OS_MAX_QS must be <= 65500" + #endif + #endif + + #ifndef OS_Q_ACCEPT_EN + #error "OS_CFG.H, Missing OS_Q_ACCEPT_EN: Include code for OSQAccept()" + #endif + + #ifndef OS_Q_DEL_EN + #error "OS_CFG.H, Missing OS_Q_DEL_EN: Include code for OSQDel()" + #endif + + #ifndef OS_Q_FLUSH_EN + #error "OS_CFG.H, Missing OS_Q_FLUSH_EN: Include code for OSQFlush()" + #endif + + #ifndef OS_Q_PEND_ABORT_EN + #error "OS_CFG.H, Missing OS_Q_PEND_ABORT_EN: Include code for OSQPendAbort()" + #endif + + #ifndef OS_Q_POST_EN + #error "OS_CFG.H, Missing OS_Q_POST_EN: Include code for OSQPost()" + #endif + + #ifndef OS_Q_POST_FRONT_EN + #error "OS_CFG.H, Missing OS_Q_POST_FRONT_EN: Include code for OSQPostFront()" + #endif + + #ifndef OS_Q_POST_OPT_EN + #error "OS_CFG.H, Missing OS_Q_POST_OPT_EN: Include code for OSQPostOpt()" + #endif + + #ifndef OS_Q_QUERY_EN + #error "OS_CFG.H, Missing OS_Q_QUERY_EN: Include code for OSQQuery()" + #endif +#endif + +/* +********************************************************************************************************* +* SEMAPHORES +********************************************************************************************************* +*/ + +#ifndef OS_SEM_EN +#error "OS_CFG.H, Missing OS_SEM_EN: Enable (1) or Disable (0) code generation for SEMAPHORES" +#else + #ifndef OS_SEM_ACCEPT_EN + #error "OS_CFG.H, Missing OS_SEM_ACCEPT_EN: Include code for OSSemAccept()" + #endif + + #ifndef OS_SEM_DEL_EN + #error "OS_CFG.H, Missing OS_SEM_DEL_EN: Include code for OSSemDel()" + #endif + + #ifndef OS_SEM_PEND_ABORT_EN + #error "OS_CFG.H, Missing OS_SEM_PEND_ABORT_EN: Include code for OSSemPendAbort()" + #endif + + #ifndef OS_SEM_QUERY_EN + #error "OS_CFG.H, Missing OS_SEM_QUERY_EN: Include code for OSSemQuery()" + #endif + + #ifndef OS_SEM_SET_EN + #error "OS_CFG.H, Missing OS_SEM_SET_EN: Include code for OSSemSet()" + #endif +#endif + +/* +********************************************************************************************************* +* TASK MANAGEMENT +********************************************************************************************************* +*/ + +#ifndef OS_MAX_TASKS +#error "OS_CFG.H, Missing OS_MAX_TASKS: Max. number of tasks in your application" +#else + #if OS_MAX_TASKS < 2 + #error "OS_CFG.H, OS_MAX_TASKS must be >= 2" + #endif + + #if OS_MAX_TASKS > ((OS_LOWEST_PRIO - OS_N_SYS_TASKS) + 1) + #error "OS_CFG.H, OS_MAX_TASKS must be <= OS_LOWEST_PRIO - OS_N_SYS_TASKS + 1" + #endif + +#endif + +#if OS_LOWEST_PRIO > 254 +#error "OS_CFG.H, OS_LOWEST_PRIO must be <= 254 in V2.8x and higher" +#endif + +#ifndef OS_TASK_IDLE_STK_SIZE +#error "OS_CFG.H, Missing OS_TASK_IDLE_STK_SIZE: Idle task stack size" +#endif + +#ifndef OS_TASK_STAT_EN +#error "OS_CFG.H, Missing OS_TASK_STAT_EN: Enable (1) or Disable(0) the statistics task" +#endif + +#ifndef OS_TASK_STAT_STK_SIZE +#error "OS_CFG.H, Missing OS_TASK_STAT_STK_SIZE: Statistics task stack size" +#endif + +#ifndef OS_TASK_STAT_STK_CHK_EN +#error "OS_CFG.H, Missing OS_TASK_STAT_STK_CHK_EN: Check task stacks from statistics task" +#endif + +#ifndef OS_TASK_CHANGE_PRIO_EN +#error "OS_CFG.H, Missing OS_TASK_CHANGE_PRIO_EN: Include code for OSTaskChangePrio()" +#endif + +#ifndef OS_TASK_CREATE_EN +#error "OS_CFG.H, Missing OS_TASK_CREATE_EN: Include code for OSTaskCreate()" +#endif + +#ifndef OS_TASK_CREATE_EXT_EN +#error "OS_CFG.H, Missing OS_TASK_CREATE_EXT_EN: Include code for OSTaskCreateExt()" +#endif + +#ifndef OS_TASK_DEL_EN +#error "OS_CFG.H, Missing OS_TASK_DEL_EN: Include code for OSTaskDel()" +#endif + +#ifndef OS_TASK_NAME_SIZE +#error "OS_CFG.H, Missing OS_TASK_NAME_SIZE: Determine the size of task names" +#endif + +#ifndef OS_TASK_SUSPEND_EN +#error "OS_CFG.H, Missing OS_TASK_SUSPEND_EN: Include code for OSTaskSuspend() and OSTaskResume()" +#endif + +#ifndef OS_TASK_QUERY_EN +#error "OS_CFG.H, Missing OS_TASK_QUERY_EN: Include code for OSTaskQuery()" +#endif + +/* +********************************************************************************************************* +* TIME MANAGEMENT +********************************************************************************************************* +*/ + +#ifndef OS_TICKS_PER_SEC +#error "OS_CFG.H, Missing OS_TICKS_PER_SEC: Sets the number of ticks in one second" +#endif + +#ifndef OS_TIME_DLY_HMSM_EN +#error "OS_CFG.H, Missing OS_TIME_DLY_HMSM_EN: Include code for OSTimeDlyHMSM()" +#endif + +#ifndef OS_TIME_DLY_RESUME_EN +#error "OS_CFG.H, Missing OS_TIME_DLY_RESUME_EN: Include code for OSTimeDlyResume()" +#endif + +#ifndef OS_TIME_GET_SET_EN +#error "OS_CFG.H, Missing OS_TIME_GET_SET_EN: Include code for OSTimeGet() and OSTimeSet()" +#endif + +/* +********************************************************************************************************* +* TIMER MANAGEMENT +********************************************************************************************************* +*/ + +#ifndef OS_TMR_EN +#error "OS_CFG.H, Missing OS_TMR_EN: When (1) enables code generation for Timer Management" +#elif OS_TMR_EN > 0 + #if OS_SEM_EN == 0 + #error "OS_CFG.H, Semaphore management is required (set OS_SEM_EN to 1) when enabling Timer Management." + #error " Timer management require TWO semaphores." + #endif + + #ifndef OS_TMR_CFG_MAX + #error "OS_CFG.H, Missing OS_TMR_CFG_MAX: Determines the total number of timers in an application (2 .. 65500)" + #else + #if OS_TMR_CFG_MAX < 2 + #error "OS_CFG.H, OS_TMR_CFG_MAX should be between 2 and 65500" + #endif + + #if OS_TMR_CFG_MAX > 65500 + #error "OS_CFG.H, OS_TMR_CFG_MAX should be between 2 and 65500" + #endif + #endif + + #ifndef OS_TMR_CFG_WHEEL_SIZE + #error "OS_CFG.H, Missing OS_TMR_CFG_WHEEL_SIZE: Sets the size of the timer wheel (1 .. 1023)" + #else + #if OS_TMR_CFG_WHEEL_SIZE < 2 + #error "OS_CFG.H, OS_TMR_CFG_WHEEL_SIZE should be between 2 and 1024" + #endif + + #if OS_TMR_CFG_WHEEL_SIZE > 1024 + #error "OS_CFG.H, OS_TMR_CFG_WHEEL_SIZE should be between 2 and 1024" + #endif + #endif + + #ifndef OS_TMR_CFG_NAME_SIZE + #error "OS_CFG.H, Missing OS_TMR_CFG_NAME_SIZE: Determines the number of characters used for Timer names" + #endif + + #ifndef OS_TMR_CFG_TICKS_PER_SEC + #error "OS_CFG.H, Missing OS_TMR_CFG_TICKS_PER_SEC: Determines the rate at which tiem timer management task will run (Hz)" + #endif + + #ifndef OS_TASK_TMR_STK_SIZE + #error "OS_CFG.H, Missing OS_TASK_TMR_STK_SIZE: Determines the size of the Timer Task's stack" + #endif +#endif + + +/* +********************************************************************************************************* +* MISCELLANEOUS +********************************************************************************************************* +*/ + +#ifndef OS_ARG_CHK_EN +#error "OS_CFG.H, Missing OS_ARG_CHK_EN: Enable (1) or Disable (0) argument checking" +#endif + + +#ifndef OS_CPU_HOOKS_EN +#error "OS_CFG.H, Missing OS_CPU_HOOKS_EN: uC/OS-II hooks are found in the processor port files when 1" +#endif + + +#ifndef OS_APP_HOOKS_EN +#error "OS_CFG.H, Missing OS_APP_HOOKS_EN: Application-defined hooks are called from the uC/OS-II hooks" +#endif + + +#ifndef OS_DEBUG_EN +#error "OS_CFG.H, Missing OS_DEBUG_EN: Allows you to include variables for debugging or not" +#endif + + +#ifndef OS_LOWEST_PRIO +#error "OS_CFG.H, Missing OS_LOWEST_PRIO: Defines the lowest priority that can be assigned" +#endif + + +#ifndef OS_MAX_EVENTS +#error "OS_CFG.H, Missing OS_MAX_EVENTS: Max. number of event control blocks in your application" +#else + #if OS_MAX_EVENTS > 65500u + #error "OS_CFG.H, OS_MAX_EVENTS must be <= 65500" + #endif +#endif + + +#ifndef OS_SCHED_LOCK_EN +#error "OS_CFG.H, Missing OS_SCHED_LOCK_EN: Include code for OSSchedLock() and OSSchedUnlock()" +#endif + + +#ifndef OS_EVENT_MULTI_EN +#error "OS_CFG.H, Missing OS_EVENT_MULTI_EN: Include code for OSEventPendMulti()" +#endif + + +#ifndef OS_TASK_PROFILE_EN +#error "OS_CFG.H, Missing OS_TASK_PROFILE_EN: Include data structure for run-time task profiling" +#endif + + +#ifndef OS_TASK_SW_HOOK_EN +#error "OS_CFG.H, Missing OS_TASK_SW_HOOK_EN: Allows you to include the code for OSTaskSwHook() or not" +#endif + + +#ifndef OS_TICK_STEP_EN +#error "OS_CFG.H, Missing OS_TICK_STEP_EN: Allows to 'step' one tick at a time with uC/OS-View" +#endif + + +#ifndef OS_TIME_TICK_HOOK_EN +#error "OS_CFG.H, Missing OS_TIME_TICK_HOOK_EN: Allows you to include the code for OSTimeTickHook() or not" +#endif + +/* +********************************************************************************************************* +* SAFETY CRITICAL USE +********************************************************************************************************* +*/ + +#ifdef SAFETY_CRITICAL_RELEASE + +#if OS_ARG_CHK_EN < 1 +#error "OS_CFG.H, OS_ARG_CHK_EN must be enabled for safety-critical release code" +#endif + +#if OS_APP_HOOKS_EN > 0 +#error "OS_CFG.H, OS_APP_HOOKS_EN must be disabled for safety-critical release code" +#endif + +#if OS_DEBUG_EN > 0 +#error "OS_CFG.H, OS_DEBUG_EN must be disabled for safety-critical release code" +#endif + +#ifdef CANTATA +#error "OS_CFG.H, CANTATA must be disabled for safety-critical release code" +#endif + +#ifdef OS_SCHED_LOCK_EN +#error "OS_CFG.H, OS_SCHED_LOCK_EN must be disabled for safety-critical release code" +#endif + +#ifdef VSC_VALIDATION_MODE +#error "OS_CFG.H, VSC_VALIDATION_MODE must be disabled for safety-critical release code" +#endif + +#if OS_TASK_STAT_EN > 0 +#error "OS_CFG.H, OS_TASK_STAT_EN must be disabled for safety-critical release code" +#endif + +#if OS_TICK_STEP_EN > 0 +#error "OS_CFG.H, OS_TICK_STEP_EN must be disabled for safety-critical release code" +#endif + +#if OS_FLAG_EN > 0 + #if OS_FLAG_DEL_EN > 0 + #error "OS_CFG.H, OS_FLAG_DEL_EN must be disabled for safety-critical release code" + #endif +#endif + +#if OS_MBOX_EN > 0 + #if OS_MBOX_DEL_EN > 0 + #error "OS_CFG.H, OS_MBOX_DEL_EN must be disabled for safety-critical release code" + #endif +#endif + +#if OS_MUTEX_EN > 0 + #if OS_MUTEX_DEL_EN > 0 + #error "OS_CFG.H, OS_MUTEX_DEL_EN must be disabled for safety-critical release code" + #endif +#endif + +#if OS_Q_EN > 0 + #if OS_Q_DEL_EN > 0 + #error "OS_CFG.H, OS_Q_DEL_EN must be disabled for safety-critical release code" + #endif +#endif + +#if OS_SEM_EN > 0 + #if OS_SEM_DEL_EN > 0 + #error "OS_CFG.H, OS_SEM_DEL_EN must be disabled for safety-critical release code" + #endif +#endif + +#if OS_TASK_EN > 0 + #if OS_TASK_DEL_EN > 0 + #error "OS_CFG.H, OS_TASK_DEL_EN must be disabled for safety-critical release code" + #endif +#endif + +#if OS_CRITICAL_METHOD != 3 +#error "OS_CPU.H, OS_CRITICAL_METHOD must be type 3 for safety-critical release code" +#endif + +#endif /* ------------------------ SAFETY_CRITICAL_RELEASE ------------------------ */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/UCOSII/src/alt_env_lock.c b/MCandWifiTestDE0/Software/MCTest_bsp/UCOSII/src/alt_env_lock.c new file mode 100644 index 00000000..203271f2 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/UCOSII/src/alt_env_lock.c @@ -0,0 +1,122 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +/* + * These are the env lock/unlock stubs required by newlib. These are + * used to make accesses to environment variables thread safe. Note that + * this implementation requires that environment variables are never manipulated + * by an interrupt service routine. + */ + + +#include + +#include "includes.h" +#include "system.h" + +/* semaphore to protect the environment */ + +OS_EVENT *alt_envsem; + +#if OS_THREAD_SAFE_NEWLIB +/* id of the task that is currently manipulating the environment */ + +static int lockid = -1; + +/* number of times __env_lock has recursed */ + +static int locks; +#endif /* OS_THREAD_SAFE_NEWLIB */ + +/* + * + */ + +void __env_lock ( struct _reent *_r ) +{ +#if OS_THREAD_SAFE_NEWLIB + OS_TCB tcb; + OS_SEM_DATA semdata; + INT8U err; + int id; + + /* use our priority as a task id */ + + err = OSTaskQuery( OS_PRIO_SELF, &tcb ); + if (err != OS_NO_ERR) + return; + + id = tcb.OSTCBPrio; + + /* see if we own the environment already */ + + OSSemQuery( alt_envsem, &semdata ); + if( semdata.OSEventGrp && id == lockid ) + { + /* we do; just count the recursion */ + + locks++; + } + else + { + /* wait on the other task to yield, then claim ownership */ + + OSSemPend( alt_envsem, 0, &err ); + locks = 1; + lockid = id; + } + +#endif /* OS_THREAD_SAFE_NEWLIB */ + return; +} + +/* + * + */ + +void __env_unlock ( struct _reent *_r ) +{ +#if OS_THREAD_SAFE_NEWLIB + if (locks == 0) + return; + + /* + * release the environment once the number of locks == the number + * of unlocks + */ + + if( (--locks) == 0 ) + { + lockid = -1; + OSSemPost( alt_envsem ); + } +#endif /* OS_THREAD_SAFE_NEWLIB */ +} + diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/UCOSII/src/alt_malloc_lock.c b/MCandWifiTestDE0/Software/MCTest_bsp/UCOSII/src/alt_malloc_lock.c new file mode 100644 index 00000000..a74685de --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/UCOSII/src/alt_malloc_lock.c @@ -0,0 +1,147 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include "system.h" + +/* + * These are the malloc lock/unlock stubs required by newlib. These are + * used to make accesses to the heap thread safe. Note that + * this implementation requires that the heap is never manipulated + * by an interrupt service routine. + */ + +#include + +#include "includes.h" + +/* semaphore to protect the heap */ + +OS_EVENT *alt_heapsem; + + +#if OS_THREAD_SAFE_NEWLIB +/* id of the task that is currently manipulating the heap */ + +static int lockid = -1; + +/* number of times __malloc_lock has recursed */ + +static int locks; +#endif /* OS_THREAD_SAFE_NEWLIB */ + +/* + * + */ + +void __malloc_lock ( struct _reent *_r ) +{ +#if OS_THREAD_SAFE_NEWLIB + OS_TCB tcb; + OS_SEM_DATA semdata; + INT8U err; + int id; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + if (OSRunning != OS_TRUE) + return; + + /* use our priority as a task id */ + + err = OSTaskQuery( OS_PRIO_SELF, &tcb ); + if (err != OS_NO_ERR) + return; + + id = tcb.OSTCBPrio; + + /* see if we own the heap already */ + + OSSemQuery( alt_heapsem, &semdata ); + + OS_ENTER_CRITICAL(); + + if( !semdata.OSCnt && id == lockid ) + { + /* we do; just count the recursion */ + locks++; + OS_EXIT_CRITICAL(); + } + else + { + /* wait on the other task to yield the heap, then claim ownership of it */ + OS_EXIT_CRITICAL(); + + OSSemPend( alt_heapsem, 0, &err ); + locks = 1; + lockid = id; + } + +#endif /* OS_THREAD_SAFE_NEWLIB */ + return; +} + +/* + * + */ + +void __malloc_unlock ( struct _reent *_r ) +{ +#if OS_THREAD_SAFE_NEWLIB + +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + if (OSRunning != OS_TRUE) + return; + + OS_ENTER_CRITICAL(); + if (locks == 0) + { + OS_EXIT_CRITICAL(); + return; + } + + /* release the heap once the number of locks == the number of unlocks */ + if( (--locks) == 0 ) + { + lockid = -1; + OS_EXIT_CRITICAL(); + OSSemPost( alt_heapsem ); + } + else + { + OS_EXIT_CRITICAL(); + } + +#endif /* OS_THREAD_SAFE_NEWLIB */ +} + diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/UCOSII/src/os_core.c b/MCandWifiTestDE0/Software/MCTest_bsp/UCOSII/src/os_core.c new file mode 100644 index 00000000..3d062273 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/UCOSII/src/os_core.c @@ -0,0 +1,2024 @@ +/* +********************************************************************************************************* +* uC/OS-II +* The Real-Time Kernel +* CORE FUNCTIONS +* +* (c) Copyright 1992-2007, Micrium, Weston, FL +* All Rights Reserved +* +* File : OS_CORE.C +* By : Jean J. Labrosse +* Version : V2.86 +* +* LICENSING TERMS: +* --------------- +* uC/OS-II is provided in source form for FREE evaluation, for educational use or for peaceful research. +* If you plan on using uC/OS-II in a commercial product you need to contact Micri�m to properly license +* its use in your product. We provide ALL the source code for your convenience and to help you experience +* uC/OS-II. The fact that the source is provided does NOT mean that you can use it without paying a +* licensing fee. +********************************************************************************************************* +*/ + +#ifndef OS_MASTER_FILE +#define OS_GLOBALS +#include +#endif + +/* +********************************************************************************************************* +* PRIORITY RESOLUTION TABLE +* +* Note: Index into table is bit pattern to resolve highest priority +* Indexed value corresponds to highest priority bit position (i.e. 0..7) +********************************************************************************************************* +*/ + +INT8U const OSUnMapTbl[256] = { + 0, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, /* 0x00 to 0x0F */ + 4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, /* 0x10 to 0x1F */ + 5, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, /* 0x20 to 0x2F */ + 4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, /* 0x30 to 0x3F */ + 6, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, /* 0x40 to 0x4F */ + 4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, /* 0x50 to 0x5F */ + 5, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, /* 0x60 to 0x6F */ + 4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, /* 0x70 to 0x7F */ + 7, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, /* 0x80 to 0x8F */ + 4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, /* 0x90 to 0x9F */ + 5, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, /* 0xA0 to 0xAF */ + 4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, /* 0xB0 to 0xBF */ + 6, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, /* 0xC0 to 0xCF */ + 4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, /* 0xD0 to 0xDF */ + 5, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0, /* 0xE0 to 0xEF */ + 4, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0 /* 0xF0 to 0xFF */ +}; + +/*$PAGE*/ +/* +********************************************************************************************************* +* FUNCTION PROTOTYPES +********************************************************************************************************* +*/ + +static void OS_InitEventList(void); + +static void OS_InitMisc(void); + +static void OS_InitRdyList(void); + +static void OS_InitTaskIdle(void); + +#if OS_TASK_STAT_EN > 0 +static void OS_InitTaskStat(void); +#endif + +static void OS_InitTCBList(void); + +static void OS_SchedNew(void); + +/*$PAGE*/ +/* +********************************************************************************************************* +* GET THE NAME OF A SEMAPHORE, MUTEX, MAILBOX or QUEUE +* +* Description: This function is used to obtain the name assigned to a semaphore, mutex, mailbox or queue. +* +* Arguments : pevent is a pointer to the event group. 'pevent' can point either to a semaphore, +* a mutex, a mailbox or a queue. Where this function is concerned, the actual +* type is irrelevant. +* +* pname is a pointer to an ASCII string that will receive the name of the semaphore, +* mutex, mailbox or queue. The string must be able to hold at least +* OS_EVENT_NAME_SIZE characters. +* +* perr is a pointer to an error code that can contain one of the following values: +* +* OS_ERR_NONE if the name was copied to 'pname' +* OS_ERR_EVENT_TYPE if 'pevent' is not pointing to the proper event +* control block type. +* OS_ERR_PNAME_NULL You passed a NULL pointer for 'pname' +* OS_ERR_PEVENT_NULL if you passed a NULL pointer for 'pevent' +* OS_ERR_NAME_GET_ISR if you are trying to call this function from an ISR +* +* Returns : The length of the string or 0 if the 'pevent' is a NULL pointer. +********************************************************************************************************* +*/ + +#if (OS_EVENT_EN) && (OS_EVENT_NAME_SIZE > 1) +INT8U OSEventNameGet (OS_EVENT *pevent, INT8U *pname, INT8U *perr) +{ + INT8U len; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + return (0); + } + if (pevent == (OS_EVENT *)0) { /* Is 'pevent' a NULL pointer? */ + *perr = OS_ERR_PEVENT_NULL; + return (0); + } + if (pname == (INT8U *)0) { /* Is 'pname' a NULL pointer? */ + *perr = OS_ERR_PNAME_NULL; + return (0); + } +#endif + if (OSIntNesting > 0) { /* See if trying to call from an ISR */ + *perr = OS_ERR_NAME_GET_ISR; + return (0); + } + switch (pevent->OSEventType) { + case OS_EVENT_TYPE_SEM: + case OS_EVENT_TYPE_MUTEX: + case OS_EVENT_TYPE_MBOX: + case OS_EVENT_TYPE_Q: + break; + + default: + *perr = OS_ERR_EVENT_TYPE; + return (0); + } + OS_ENTER_CRITICAL(); + len = OS_StrCopy(pname, pevent->OSEventName); /* Copy name from OS_EVENT */ + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + return (len); +} +#endif + +/*$PAGE*/ +/* +********************************************************************************************************* +* ASSIGN A NAME TO A SEMAPHORE, MUTEX, MAILBOX or QUEUE +* +* Description: This function assigns a name to a semaphore, mutex, mailbox or queue. +* +* Arguments : pevent is a pointer to the event group. 'pevent' can point either to a semaphore, +* a mutex, a mailbox or a queue. Where this function is concerned, it doesn't +* matter the actual type. +* +* pname is a pointer to an ASCII string that will be used as the name of the semaphore, +* mutex, mailbox or queue. The string must be able to hold at least +* OS_EVENT_NAME_SIZE characters. +* +* perr is a pointer to an error code that can contain one of the following values: +* +* OS_ERR_NONE if the requested task is resumed +* OS_ERR_EVENT_TYPE if 'pevent' is not pointing to the proper event +* control block type. +* OS_ERR_PNAME_NULL You passed a NULL pointer for 'pname' +* OS_ERR_PEVENT_NULL if you passed a NULL pointer for 'pevent' +* OS_ERR_NAME_SET_ISR if you called this function from an ISR +* +* Returns : None +********************************************************************************************************* +*/ + +#if (OS_EVENT_EN) && (OS_EVENT_NAME_SIZE > 1) +void OSEventNameSet (OS_EVENT *pevent, INT8U *pname, INT8U *perr) +{ + INT8U len; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + return; + } + if (pevent == (OS_EVENT *)0) { /* Is 'pevent' a NULL pointer? */ + *perr = OS_ERR_PEVENT_NULL; + return; + } + if (pname == (INT8U *)0) { /* Is 'pname' a NULL pointer? */ + *perr = OS_ERR_PNAME_NULL; + return; + } +#endif + if (OSIntNesting > 0) { /* See if trying to call from an ISR */ + *perr = OS_ERR_NAME_SET_ISR; + return; + } + switch (pevent->OSEventType) { + case OS_EVENT_TYPE_SEM: + case OS_EVENT_TYPE_MUTEX: + case OS_EVENT_TYPE_MBOX: + case OS_EVENT_TYPE_Q: + break; + + default: + *perr = OS_ERR_EVENT_TYPE; + return; + } + OS_ENTER_CRITICAL(); + len = OS_StrLen(pname); /* Can we fit the string in the storage area? */ + if (len > (OS_EVENT_NAME_SIZE - 1)) { /* No */ + OS_EXIT_CRITICAL(); + *perr = OS_ERR_EVENT_NAME_TOO_LONG; + return; + } + (void)OS_StrCopy(pevent->OSEventName, pname); /* Yes, copy name to the event control block */ + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; +} +#endif + +/*$PAGE*/ +/* +********************************************************************************************************* +* PEND ON MULTIPLE EVENTS +* +* Description: This function waits for multiple events. If multiple events are ready at the start of the +* pend call, then all available events are returned as ready. If the task must pend on the +* multiple events, then only the first posted or aborted event is returned as ready. +* +* Arguments : pevents_pend is a pointer to a NULL-terminated array of event control blocks to wait for. +* +* pevents_rdy is a pointer to an array to return which event control blocks are available +* or ready. The size of the array MUST be greater than or equal to the size +* of the 'pevents_pend' array, including terminating NULL. +* +* pmsgs_rdy is a pointer to an array to return messages from any available message-type +* events. The size of the array MUST be greater than or equal to the size of +* the 'pevents_pend' array, excluding the terminating NULL. Since NULL +* messages are valid messages, this array cannot be NULL-terminated. Instead, +* every available message-type event returns its messages in the 'pmsgs_rdy' +* array at the same index as the event is returned in the 'pevents_rdy' array. +* All other 'pmsgs_rdy' array indices are filled with NULL messages. +* +* timeout is an optional timeout period (in clock ticks). If non-zero, your task will +* wait for the resources up to the amount of time specified by this argument. +* If you specify 0, however, your task will wait forever for the specified +* events or, until the resources becomes available (or the events occur). +* +* perr is a pointer to where an error message will be deposited. Possible error +* messages are: +* +* OS_ERR_NONE The call was successful and your task owns the resources +* or, the events you are waiting for occurred; check the +* 'pevents_rdy' array for which events are available. +* OS_ERR_PEND_ABORT The wait on the events was aborted; check the +* 'pevents_rdy' array for which events were aborted. +* OS_ERR_TIMEOUT The events were not received within the specified +* 'timeout'. +* OS_ERR_PEVENT_NULL If 'pevents_pend', 'pevents_rdy', or 'pmsgs_rdy' is a +* NULL pointer. +* OS_ERR_EVENT_TYPE If you didn't pass a pointer to an array of semaphores, +* mailboxes, and/or queues. +* OS_ERR_PEND_ISR If you called this function from an ISR and the result +* would lead to a suspension. +* OS_ERR_PEND_LOCKED If you called this function when the scheduler is locked. +* +* Returns : > 0 the number of events returned as ready or aborted. +* == 0 if no events are returned as ready because of timeout or upon error. +* +* Notes : 1) a. Validate 'pevents_pend' array as valid OS_EVENTs : +* +* semaphores, mailboxes, queues +* +* b. Return ALL available events and messages, if any +* +* c. Add current task priority as pending to each events's wait list +* Performed in OS_EventTaskWaitMulti() +* +* d. Wait on any of multiple events +* +* e. Remove current task priority as pending from each events's wait list +* Performed in OS_EventTaskRdy(), if events posted or aborted +* +* f. Return any event posted or aborted, if any +* else +* Return timeout +* +* 2) 'pevents_rdy' initialized to NULL PRIOR to all other validation or function handling in +* case of any error(s). +********************************************************************************************************* +*/ +/*$PAGE*/ +#if ((OS_EVENT_EN) && (OS_EVENT_MULTI_EN > 0)) +INT16U OSEventPendMulti (OS_EVENT **pevents_pend, OS_EVENT **pevents_rdy, void **pmsgs_rdy, INT16U timeout, INT8U *perr) +{ + OS_EVENT **pevents; + OS_EVENT *pevent; +#if ((OS_Q_EN > 0) && (OS_MAX_QS > 0)) + OS_Q *pq; +#endif + BOOLEAN events_rdy; + INT16U events_rdy_nbr; + INT8U events_stat; +#if (OS_CRITICAL_METHOD == 3) /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if (OS_ARG_CHK_EN > 0) + if (perr == (INT8U *)0) { /* Validate 'perr' */ + return (0); + } + if (pevents_pend == (OS_EVENT **)0) { /* Validate 'pevents_pend' */ + *perr = OS_ERR_PEVENT_NULL; + return (0); + } + if (pevents_rdy == (OS_EVENT **)0) { /* Validate 'pevents_rdy' */ + *perr = OS_ERR_PEVENT_NULL; + return (0); + } + if (pmsgs_rdy == (void **)0) { /* Validate 'pmsgs_rdy' */ + *perr = OS_ERR_PEVENT_NULL; + return (0); + } +#endif + + *pevents_rdy = (OS_EVENT *)0; /* Init array to NULL in case of errors */ + + pevents = pevents_pend; + pevent = *pevents; + while (pevent != (OS_EVENT *)0) { + switch (pevent->OSEventType) { /* Validate event block types */ +#if (OS_SEM_EN > 0) + case OS_EVENT_TYPE_SEM: + break; +#endif +#if (OS_MBOX_EN > 0) + case OS_EVENT_TYPE_MBOX: + break; +#endif +#if ((OS_Q_EN > 0) && (OS_MAX_QS > 0)) + case OS_EVENT_TYPE_Q: + break; +#endif + + case OS_EVENT_TYPE_MUTEX: + case OS_EVENT_TYPE_FLAG: + default: + *perr = OS_ERR_EVENT_TYPE; + return (0); + } + pevents++; + pevent = *pevents; + } + + if (OSIntNesting > 0) { /* See if called from ISR ... */ + *perr = OS_ERR_PEND_ISR; /* ... can't PEND from an ISR */ + return (0); + } + if (OSLockNesting > 0) { /* See if called with scheduler locked ... */ + *perr = OS_ERR_PEND_LOCKED; /* ... can't PEND when locked */ + return (0); + } + +/*$PAGE*/ + OS_ENTER_CRITICAL(); + events_rdy = OS_FALSE; + events_rdy_nbr = 0; + events_stat = OS_STAT_RDY; + pevents = pevents_pend; + pevent = *pevents; + while (pevent != (OS_EVENT *)0) { /* See if any events already available */ + switch (pevent->OSEventType) { +#if (OS_SEM_EN > 0) + case OS_EVENT_TYPE_SEM: + if (pevent->OSEventCnt > 0) { /* If semaphore count > 0, resource available; */ + pevent->OSEventCnt--; /* ... decrement semaphore, ... */ + *pevents_rdy++ = pevent; /* ... and return available semaphore event */ + events_rdy = OS_TRUE; + *pmsgs_rdy++ = (void *)0; /* NO message returned for semaphores */ + events_rdy_nbr++; + + } else { + events_stat |= OS_STAT_SEM; /* Configure multi-pend for semaphore events */ + } + break; +#endif + +#if (OS_MBOX_EN > 0) + case OS_EVENT_TYPE_MBOX: + if (pevent->OSEventPtr != (void *)0) { /* If mailbox NOT empty; ... */ + /* ... return available message, ... */ + *pmsgs_rdy++ = (void *)pevent->OSEventPtr; + pevent->OSEventPtr = (void *)0; + *pevents_rdy++ = pevent; /* ... and return available mailbox event */ + events_rdy = OS_TRUE; + events_rdy_nbr++; + + } else { + events_stat |= OS_STAT_MBOX; /* Configure multi-pend for mailbox events */ + } + break; +#endif + +#if ((OS_Q_EN > 0) && (OS_MAX_QS > 0)) + case OS_EVENT_TYPE_Q: + pq = (OS_Q *)pevent->OSEventPtr; + if (pq->OSQEntries > 0) { /* If queue NOT empty; ... */ + /* ... return available message, ... */ + *pmsgs_rdy++ = (void *)*pq->OSQOut++; + if (pq->OSQOut == pq->OSQEnd) { /* If OUT ptr at queue end, ... */ + pq->OSQOut = pq->OSQStart; /* ... wrap to queue start */ + } + pq->OSQEntries--; /* Update number of queue entries */ + *pevents_rdy++ = pevent; /* ... and return available queue event */ + events_rdy = OS_TRUE; + events_rdy_nbr++; + + } else { + events_stat |= OS_STAT_Q; /* Configure multi-pend for queue events */ + } + break; +#endif + + case OS_EVENT_TYPE_MUTEX: + case OS_EVENT_TYPE_FLAG: + default: + OS_EXIT_CRITICAL(); + *pevents_rdy = (OS_EVENT *)0; /* NULL terminate return event array */ + *perr = OS_ERR_EVENT_TYPE; + return (events_rdy_nbr); + } + pevents++; + pevent = *pevents; + } + + if ( events_rdy == OS_TRUE) { /* Return any events already available */ + *pevents_rdy = (OS_EVENT *)0; /* NULL terminate return event array */ + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + return (events_rdy_nbr); + } +/*$PAGE*/ + /* Otherwise, must wait until any event occurs */ + OSTCBCur->OSTCBStat |= events_stat | /* Resource not available, ... */ + OS_STAT_MULTI; /* ... pend on multiple events */ + OSTCBCur->OSTCBStatPend = OS_STAT_PEND_OK; + OSTCBCur->OSTCBDly = timeout; /* Store pend timeout in TCB */ + OS_EventTaskWaitMulti(pevents_pend); /* Suspend task until events or timeout occurs */ + + OS_EXIT_CRITICAL(); + OS_Sched(); /* Find next highest priority task ready */ + OS_ENTER_CRITICAL(); + + switch (OSTCBCur->OSTCBStatPend) { /* Handle event posted, aborted, or timed-out */ + case OS_STAT_PEND_OK: + case OS_STAT_PEND_ABORT: + pevent = OSTCBCur->OSTCBEventPtr; + if (pevent != (OS_EVENT *)0) { /* If task event ptr != NULL, ... */ + *pevents_rdy++ = pevent; /* ... return available event ... */ + *pevents_rdy = (OS_EVENT *)0; /* ... & NULL terminate return event array */ + events_rdy_nbr++; + + } else { /* Else NO event available, handle as timeout */ + OSTCBCur->OSTCBStatPend = OS_STAT_PEND_TO; + OS_EventTaskRemoveMulti(OSTCBCur, pevents_pend); + } + break; + + case OS_STAT_PEND_TO: + default: /* ... remove task from events' wait lists */ + OS_EventTaskRemoveMulti(OSTCBCur, pevents_pend); + break; + } + + switch (OSTCBCur->OSTCBStatPend) { + case OS_STAT_PEND_OK: + switch (pevent->OSEventType) { /* Return event's message */ +#if (OS_SEM_EN > 0) + case OS_EVENT_TYPE_SEM: + *pmsgs_rdy++ = (void *)0; /* NO message returned for semaphores */ + break; +#endif + +#if ((OS_MBOX_EN > 0) || \ + ((OS_Q_EN > 0) && (OS_MAX_QS > 0))) + case OS_EVENT_TYPE_MBOX: + case OS_EVENT_TYPE_Q: + *pmsgs_rdy++ = (void *)OSTCBCur->OSTCBMsg; /* Return received message */ + break; +#endif + + case OS_EVENT_TYPE_MUTEX: + case OS_EVENT_TYPE_FLAG: + default: + OS_EXIT_CRITICAL(); + *pevents_rdy = (OS_EVENT *)0; /* NULL terminate return event array */ + *perr = OS_ERR_EVENT_TYPE; + return (events_rdy_nbr); + } + *perr = OS_ERR_NONE; + break; + + case OS_STAT_PEND_ABORT: + *pmsgs_rdy++ = (void *)0; /* NO message returned for abort */ + *perr = OS_ERR_PEND_ABORT; /* Indicate that event aborted */ + break; + + case OS_STAT_PEND_TO: + default: + *pmsgs_rdy++ = (void *)0; /* NO message returned for timeout */ + *perr = OS_ERR_TIMEOUT; /* Indicate that events timed out */ + break; + } + + OSTCBCur->OSTCBStat = OS_STAT_RDY; /* Set task status to ready */ + OSTCBCur->OSTCBStatPend = OS_STAT_PEND_OK; /* Clear pend status */ + OSTCBCur->OSTCBEventPtr = (OS_EVENT *)0; /* Clear event pointers */ + OSTCBCur->OSTCBEventMultiPtr = (OS_EVENT **)0; + OSTCBCur->OSTCBMsg = (void *)0; /* Clear task message */ + OS_EXIT_CRITICAL(); + + return (events_rdy_nbr); +} +#endif + +/*$PAGE*/ +/* +********************************************************************************************************* +* INITIALIZATION +* +* Description: This function is used to initialize the internals of uC/OS-II and MUST be called prior to +* creating any uC/OS-II object and, prior to calling OSStart(). +* +* Arguments : none +* +* Returns : none +********************************************************************************************************* +*/ + +void OSInit (void) +{ + OSInitHookBegin(); /* Call port specific initialization code */ + + OS_InitMisc(); /* Initialize miscellaneous variables */ + + OS_InitRdyList(); /* Initialize the Ready List */ + + OS_InitTCBList(); /* Initialize the free list of OS_TCBs */ + + OS_InitEventList(); /* Initialize the free list of OS_EVENTs */ + +#if (OS_FLAG_EN > 0) && (OS_MAX_FLAGS > 0) + OS_FlagInit(); /* Initialize the event flag structures */ +#endif + +#if (OS_MEM_EN > 0) && (OS_MAX_MEM_PART > 0) + OS_MemInit(); /* Initialize the memory manager */ +#endif + +#if (OS_Q_EN > 0) && (OS_MAX_QS > 0) + OS_QInit(); /* Initialize the message queue structures */ +#endif + + OS_InitTaskIdle(); /* Create the Idle Task */ +#if OS_TASK_STAT_EN > 0 + OS_InitTaskStat(); /* Create the Statistic Task */ +#endif + +#if OS_TMR_EN > 0 + OSTmr_Init(); /* Initialize the Timer Manager */ +#endif + + OSInitHookEnd(); /* Call port specific init. code */ + +#if OS_DEBUG_EN > 0 + OSDebugInit(); +#endif +} +/*$PAGE*/ +/* +********************************************************************************************************* +* ENTER ISR +* +* Description: This function is used to notify uC/OS-II that you are about to service an interrupt +* service routine (ISR). This allows uC/OS-II to keep track of interrupt nesting and thus +* only perform rescheduling at the last nested ISR. +* +* Arguments : none +* +* Returns : none +* +* Notes : 1) This function should be called ith interrupts already disabled +* 2) Your ISR can directly increment OSIntNesting without calling this function because +* OSIntNesting has been declared 'global'. +* 3) You MUST still call OSIntExit() even though you increment OSIntNesting directly. +* 4) You MUST invoke OSIntEnter() and OSIntExit() in pair. In other words, for every call +* to OSIntEnter() at the beginning of the ISR you MUST have a call to OSIntExit() at the +* end of the ISR. +* 5) You are allowed to nest interrupts up to 255 levels deep. +********************************************************************************************************* +*/ + +void OSIntEnter (void) +{ +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + if (OSRunning == OS_TRUE) { + OS_ENTER_CRITICAL(); + if (OSIntNesting < 255u) { + OSIntNesting++; /* Increment ISR nesting level */ + } + OS_EXIT_CRITICAL(); + } +} +/*$PAGE*/ +/* +********************************************************************************************************* +* EXIT ISR +* +* Description: This function is used to notify uC/OS-II that you have completed serviving an ISR. When +* the last nested ISR has completed, uC/OS-II will call the scheduler to determine whether +* a new, high-priority task, is ready to run. +* +* Arguments : none +* +* Returns : none +* +* Notes : 1) You MUST invoke OSIntEnter() and OSIntExit() in pair. In other words, for every call +* to OSIntEnter() at the beginning of the ISR you MUST have a call to OSIntExit() at the +* end of the ISR. +* 2) Rescheduling is prevented when the scheduler is locked (see OS_SchedLock()) +********************************************************************************************************* +*/ + +void OSIntExit (void) +{ +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + + if (OSRunning == OS_TRUE) { + OS_ENTER_CRITICAL(); + if (OSIntNesting > 0) { /* Prevent OSIntNesting from wrapping */ + OSIntNesting--; + } + if (OSIntNesting == 0) { /* Reschedule only if all ISRs complete ... */ + if (OSLockNesting == 0) { /* ... and not locked. */ + OS_SchedNew(); + if (OSPrioHighRdy != OSPrioCur) { /* No Ctx Sw if current task is highest rdy */ + OSTCBHighRdy = OSTCBPrioTbl[OSPrioHighRdy]; +#if OS_TASK_PROFILE_EN > 0 + OSTCBHighRdy->OSTCBCtxSwCtr++; /* Inc. # of context switches to this task */ +#endif + OSCtxSwCtr++; /* Keep track of the number of ctx switches */ + OSIntCtxSw(); /* Perform interrupt level ctx switch */ + } + } + } + OS_EXIT_CRITICAL(); + } +} +/*$PAGE*/ +/* +********************************************************************************************************* +* PREVENT SCHEDULING +* +* Description: This function is used to prevent rescheduling to take place. This allows your application +* to prevent context switches until you are ready to permit context switching. +* +* Arguments : none +* +* Returns : none +* +* Notes : 1) You MUST invoke OSSchedLock() and OSSchedUnlock() in pair. In other words, for every +* call to OSSchedLock() you MUST have a call to OSSchedUnlock(). +********************************************************************************************************* +*/ + +#if OS_SCHED_LOCK_EN > 0 +void OSSchedLock (void) +{ +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + + if (OSRunning == OS_TRUE) { /* Make sure multitasking is running */ + OS_ENTER_CRITICAL(); + if (OSIntNesting == 0) { /* Can't call from an ISR */ + if (OSLockNesting < 255u) { /* Prevent OSLockNesting from wrapping back to 0 */ + OSLockNesting++; /* Increment lock nesting level */ + } + } + OS_EXIT_CRITICAL(); + } +} +#endif + +/*$PAGE*/ +/* +********************************************************************************************************* +* ENABLE SCHEDULING +* +* Description: This function is used to re-allow rescheduling. +* +* Arguments : none +* +* Returns : none +* +* Notes : 1) You MUST invoke OSSchedLock() and OSSchedUnlock() in pair. In other words, for every +* call to OSSchedLock() you MUST have a call to OSSchedUnlock(). +********************************************************************************************************* +*/ + +#if OS_SCHED_LOCK_EN > 0 +void OSSchedUnlock (void) +{ +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + + if (OSRunning == OS_TRUE) { /* Make sure multitasking is running */ + OS_ENTER_CRITICAL(); + if (OSLockNesting > 0) { /* Do not decrement if already 0 */ + OSLockNesting--; /* Decrement lock nesting level */ + if (OSLockNesting == 0) { /* See if scheduler is enabled and ... */ + if (OSIntNesting == 0) { /* ... not in an ISR */ + OS_EXIT_CRITICAL(); + OS_Sched(); /* See if a HPT is ready */ + } else { + OS_EXIT_CRITICAL(); + } + } else { + OS_EXIT_CRITICAL(); + } + } else { + OS_EXIT_CRITICAL(); + } + } +} +#endif + +/*$PAGE*/ +/* +********************************************************************************************************* +* START MULTITASKING +* +* Description: This function is used to start the multitasking process which lets uC/OS-II manages the +* task that you have created. Before you can call OSStart(), you MUST have called OSInit() +* and you MUST have created at least one task. +* +* Arguments : none +* +* Returns : none +* +* Note : OSStartHighRdy() MUST: +* a) Call OSTaskSwHook() then, +* b) Set OSRunning to OS_TRUE. +* c) Load the context of the task pointed to by OSTCBHighRdy. +* d_ Execute the task. +********************************************************************************************************* +*/ + +void OSStart (void) +{ + if (OSRunning == OS_FALSE) { + OS_SchedNew(); /* Find highest priority's task priority number */ + OSPrioCur = OSPrioHighRdy; + OSTCBHighRdy = OSTCBPrioTbl[OSPrioHighRdy]; /* Point to highest priority task ready to run */ + OSTCBCur = OSTCBHighRdy; + OSStartHighRdy(); /* Execute target specific code to start task */ + } +} +/*$PAGE*/ +/* +********************************************************************************************************* +* STATISTICS INITIALIZATION +* +* Description: This function is called by your application to establish CPU usage by first determining +* how high a 32-bit counter would count to in 1 second if no other tasks were to execute +* during that time. CPU usage is then determined by a low priority task which keeps track +* of this 32-bit counter every second but this time, with other tasks running. CPU usage is +* determined by: +* +* OSIdleCtr +* CPU Usage (%) = 100 * (1 - ------------) +* OSIdleCtrMax +* +* Arguments : none +* +* Returns : none +********************************************************************************************************* +*/ + +#if OS_TASK_STAT_EN > 0 +void OSStatInit (void) +{ +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + + OSTimeDly(2); /* Synchronize with clock tick */ + OS_ENTER_CRITICAL(); + OSIdleCtr = 0L; /* Clear idle counter */ + OS_EXIT_CRITICAL(); + OSTimeDly(OS_TICKS_PER_SEC / 10); /* Determine MAX. idle counter value for 1/10 second */ + OS_ENTER_CRITICAL(); + OSIdleCtrMax = OSIdleCtr; /* Store maximum idle counter count in 1/10 second */ + OSStatRdy = OS_TRUE; + OS_EXIT_CRITICAL(); +} +#endif +/*$PAGE*/ +/* +********************************************************************************************************* +* PROCESS SYSTEM TICK +* +* Description: This function is used to signal to uC/OS-II the occurrence of a 'system tick' (also known +* as a 'clock tick'). This function should be called by the ticker ISR but, can also be +* called by a high priority task. +* +* Arguments : none +* +* Returns : none +********************************************************************************************************* +*/ + +void OSTimeTick (void) +{ + OS_TCB *ptcb; +#if OS_TICK_STEP_EN > 0 + BOOLEAN step; +#endif +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_TIME_TICK_HOOK_EN > 0 + OSTimeTickHook(); /* Call user definable hook */ +#endif +#if OS_TIME_GET_SET_EN > 0 + OS_ENTER_CRITICAL(); /* Update the 32-bit tick counter */ + OSTime++; + OS_EXIT_CRITICAL(); +#endif + if (OSRunning == OS_TRUE) { +#if OS_TICK_STEP_EN > 0 + switch (OSTickStepState) { /* Determine whether we need to process a tick */ + case OS_TICK_STEP_DIS: /* Yes, stepping is disabled */ + step = OS_TRUE; + break; + + case OS_TICK_STEP_WAIT: /* No, waiting for uC/OS-View to set ... */ + step = OS_FALSE; /* .. OSTickStepState to OS_TICK_STEP_ONCE */ + break; + + case OS_TICK_STEP_ONCE: /* Yes, process tick once and wait for next ... */ + step = OS_TRUE; /* ... step command from uC/OS-View */ + OSTickStepState = OS_TICK_STEP_WAIT; + break; + + default: /* Invalid case, correct situation */ + step = OS_TRUE; + OSTickStepState = OS_TICK_STEP_DIS; + break; + } + if (step == OS_FALSE) { /* Return if waiting for step command */ + return; + } +#endif + ptcb = OSTCBList; /* Point at first TCB in TCB list */ + while (ptcb->OSTCBPrio != OS_TASK_IDLE_PRIO) { /* Go through all TCBs in TCB list */ + OS_ENTER_CRITICAL(); + if (ptcb->OSTCBDly != 0) { /* No, Delayed or waiting for event with TO */ + if (--ptcb->OSTCBDly == 0) { /* Decrement nbr of ticks to end of delay */ + /* Check for timeout */ + if ((ptcb->OSTCBStat & OS_STAT_PEND_ANY) != OS_STAT_RDY) { + ptcb->OSTCBStat &= ~(INT8U)OS_STAT_PEND_ANY; /* Yes, Clear status flag */ + ptcb->OSTCBStatPend = OS_STAT_PEND_TO; /* Indicate PEND timeout */ + } else { + ptcb->OSTCBStatPend = OS_STAT_PEND_OK; + } + + if ((ptcb->OSTCBStat & OS_STAT_SUSPEND) == OS_STAT_RDY) { /* Is task suspended? */ + OSRdyGrp |= ptcb->OSTCBBitY; /* No, Make ready */ + OSRdyTbl[ptcb->OSTCBY] |= ptcb->OSTCBBitX; + } + } + } + ptcb = ptcb->OSTCBNext; /* Point at next TCB in TCB list */ + OS_EXIT_CRITICAL(); + } + } +} + +/*$PAGE*/ +/* +********************************************************************************************************* +* GET VERSION +* +* Description: This function is used to return the version number of uC/OS-II. The returned value +* corresponds to uC/OS-II's version number multiplied by 100. In other words, version 2.00 +* would be returned as 200. +* +* Arguments : none +* +* Returns : the version number of uC/OS-II multiplied by 100. +********************************************************************************************************* +*/ + +INT16U OSVersion (void) +{ + return (OS_VERSION); +} + +/*$PAGE*/ +/* +********************************************************************************************************* +* DUMMY FUNCTION +* +* Description: This function doesn't do anything. It is called by OSTaskDel(). +* +* Arguments : none +* +* Returns : none +********************************************************************************************************* +*/ + +#if OS_TASK_DEL_EN > 0 +void OS_Dummy (void) +{ +} +#endif + +/*$PAGE*/ +/* +********************************************************************************************************* +* MAKE TASK READY TO RUN BASED ON EVENT OCCURING +* +* Description: This function is called by other uC/OS-II services and is used to ready a task that was +* waiting for an event to occur. +* +* Arguments : pevent is a pointer to the event control block corresponding to the event. +* +* pmsg is a pointer to a message. This pointer is used by message oriented services +* such as MAILBOXEs and QUEUEs. The pointer is not used when called by other +* service functions. +* +* msk is a mask that is used to clear the status byte of the TCB. For example, +* OSSemPost() will pass OS_STAT_SEM, OSMboxPost() will pass OS_STAT_MBOX etc. +* +* pend_stat is used to indicate the readied task's pending status: +* +* OS_STAT_PEND_OK Task ready due to a post (or delete), not a timeout or +* an abort. +* OS_STAT_PEND_ABORT Task ready due to an abort. +* +* Returns : none +* +* Note : This function is INTERNAL to uC/OS-II and your application should not call it. +********************************************************************************************************* +*/ +#if (OS_EVENT_EN) +INT8U OS_EventTaskRdy (OS_EVENT *pevent, void *pmsg, INT8U msk, INT8U pend_stat) +{ + OS_TCB *ptcb; + INT8U y; + INT8U x; + INT8U prio; +#if OS_LOWEST_PRIO > 63 + INT16U *ptbl; +#endif + + +#if OS_LOWEST_PRIO <= 63 + y = OSUnMapTbl[pevent->OSEventGrp]; /* Find HPT waiting for message */ + x = OSUnMapTbl[pevent->OSEventTbl[y]]; + prio = (INT8U)((y << 3) + x); /* Find priority of task getting the msg */ +#else + if ((pevent->OSEventGrp & 0xFF) != 0) { /* Find HPT waiting for message */ + y = OSUnMapTbl[ pevent->OSEventGrp & 0xFF]; + } else { + y = OSUnMapTbl[(pevent->OSEventGrp >> 8) & 0xFF] + 8; + } + ptbl = &pevent->OSEventTbl[y]; + if ((*ptbl & 0xFF) != 0) { + x = OSUnMapTbl[*ptbl & 0xFF]; + } else { + x = OSUnMapTbl[(*ptbl >> 8) & 0xFF] + 8; + } + prio = (INT8U)((y << 4) + x); /* Find priority of task getting the msg */ +#endif + + ptcb = OSTCBPrioTbl[prio]; /* Point to this task's OS_TCB */ + ptcb->OSTCBDly = 0; /* Prevent OSTimeTick() from readying task */ +#if ((OS_Q_EN > 0) && (OS_MAX_QS > 0)) || (OS_MBOX_EN > 0) + ptcb->OSTCBMsg = pmsg; /* Send message directly to waiting task */ +#else + pmsg = pmsg; /* Prevent compiler warning if not used */ +#endif + ptcb->OSTCBStat &= ~msk; /* Clear bit associated with event type */ + ptcb->OSTCBStatPend = pend_stat; /* Set pend status of post or abort */ + /* See if task is ready (could be susp'd) */ + if ((ptcb->OSTCBStat & OS_STAT_SUSPEND) == OS_STAT_RDY) { + OSRdyGrp |= ptcb->OSTCBBitY; /* Put task in the ready to run list */ + OSRdyTbl[y] |= ptcb->OSTCBBitX; + } + + OS_EventTaskRemove(ptcb, pevent); /* Remove this task from event wait list */ +#if (OS_EVENT_MULTI_EN > 0) + if (ptcb->OSTCBEventMultiPtr != (OS_EVENT **)0) { /* Remove this task from events' wait lists */ + OS_EventTaskRemoveMulti(ptcb, ptcb->OSTCBEventMultiPtr); + ptcb->OSTCBEventPtr = (OS_EVENT *)pevent;/* Return event as first multi-pend event ready*/ + } +#endif + + return (prio); +} +#endif +/*$PAGE*/ +/* +********************************************************************************************************* +* MAKE TASK WAIT FOR EVENT TO OCCUR +* +* Description: This function is called by other uC/OS-II services to suspend a task because an event has +* not occurred. +* +* Arguments : pevent is a pointer to the event control block for which the task will be waiting for. +* +* Returns : none +* +* Note : This function is INTERNAL to uC/OS-II and your application should not call it. +********************************************************************************************************* +*/ +#if (OS_EVENT_EN) +void OS_EventTaskWait (OS_EVENT *pevent) +{ + INT8U y; + + + OSTCBCur->OSTCBEventPtr = pevent; /* Store ptr to ECB in TCB */ + + pevent->OSEventTbl[OSTCBCur->OSTCBY] |= OSTCBCur->OSTCBBitX; /* Put task in waiting list */ + pevent->OSEventGrp |= OSTCBCur->OSTCBBitY; + + y = OSTCBCur->OSTCBY; /* Task no longer ready */ + OSRdyTbl[y] &= ~OSTCBCur->OSTCBBitX; + if (OSRdyTbl[y] == 0) { + OSRdyGrp &= ~OSTCBCur->OSTCBBitY; /* Clear event grp bit if this was only task pending */ + } +} +#endif +/*$PAGE*/ +/* +********************************************************************************************************* +* MAKE TASK WAIT FOR ANY OF MULTIPLE EVENTS TO OCCUR +* +* Description: This function is called by other uC/OS-II services to suspend a task because any one of +* multiple events has not occurred. +* +* Arguments : pevents_wait is a pointer to an array of event control blocks, NULL-terminated, for +* which the task will be waiting for. +* +* Returns : none. +* +* Note : This function is INTERNAL to uC/OS-II and your application should not call it. +********************************************************************************************************* +*/ +#if ((OS_EVENT_EN) && (OS_EVENT_MULTI_EN > 0)) +void OS_EventTaskWaitMulti (OS_EVENT **pevents_wait) +{ + OS_EVENT **pevents; + OS_EVENT *pevent; + INT8U y; + + + OSTCBCur->OSTCBEventPtr = (OS_EVENT *)0; + OSTCBCur->OSTCBEventMultiPtr = (OS_EVENT **)pevents_wait; /* Store ptr to ECBs in TCB */ + + pevents = pevents_wait; + pevent = *pevents; + while (pevent != (OS_EVENT *)0) { /* Put task in waiting lists */ + pevent->OSEventTbl[OSTCBCur->OSTCBY] |= OSTCBCur->OSTCBBitX; + pevent->OSEventGrp |= OSTCBCur->OSTCBBitY; + pevents++; + pevent = *pevents; + } + + y = OSTCBCur->OSTCBY; /* Task no longer ready */ + OSRdyTbl[y] &= ~OSTCBCur->OSTCBBitX; + if (OSRdyTbl[y] == 0) { + OSRdyGrp &= ~OSTCBCur->OSTCBBitY; /* Clear event grp bit if this was only task pending */ + } +} +#endif +/*$PAGE*/ +/* +********************************************************************************************************* +* REMOVE TASK FROM EVENT WAIT LIST +* +* Description: Remove a task from an event's wait list. +* +* Arguments : ptcb is a pointer to the task to remove. +* +* pevent is a pointer to the event control block. +* +* Returns : none +* +* Note : This function is INTERNAL to uC/OS-II and your application should not call it. +********************************************************************************************************* +*/ +#if (OS_EVENT_EN) +void OS_EventTaskRemove (OS_TCB *ptcb, + OS_EVENT *pevent) +{ + INT8U y; + + + y = ptcb->OSTCBY; + pevent->OSEventTbl[y] &= ~ptcb->OSTCBBitX; /* Remove task from wait list */ + if (pevent->OSEventTbl[y] == 0) { + pevent->OSEventGrp &= ~ptcb->OSTCBBitY; + } +} +#endif +/*$PAGE*/ +/* +********************************************************************************************************* +* REMOVE TASK FROM MULTIPLE EVENTS WAIT LISTS +* +* Description: Remove a task from multiple events' wait lists. +* +* Arguments : ptcb is a pointer to the task to remove. +* +* pevents_multi is a pointer to the array of event control blocks, NULL-terminated. +* +* Returns : none +* +* Note : This function is INTERNAL to uC/OS-II and your application should not call it. +********************************************************************************************************* +*/ +#if ((OS_EVENT_EN) && (OS_EVENT_MULTI_EN > 0)) +void OS_EventTaskRemoveMulti (OS_TCB *ptcb, + OS_EVENT **pevents_multi) +{ + OS_EVENT **pevents; + OS_EVENT *pevent; + INT8U y; +#if (OS_LOWEST_PRIO <= 63) + INT8U bity; + INT8U bitx; +#else + INT16U bity; + INT16U bitx; +#endif + + + y = ptcb->OSTCBY; + bity = ptcb->OSTCBBitY; + bitx = ptcb->OSTCBBitX; + pevents = pevents_multi; + pevent = *pevents; + while (pevent != (OS_EVENT *)0) { /* Remove task from all events' wait lists */ + pevent->OSEventTbl[y] &= ~bitx; + if (pevent->OSEventTbl[y] == 0) { + pevent->OSEventGrp &= ~bity; + } + pevents++; + pevent = *pevents; + } +} +#endif +/*$PAGE*/ +/* +********************************************************************************************************* +* INITIALIZE EVENT CONTROL BLOCK'S WAIT LIST +* +* Description: This function is called by other uC/OS-II services to initialize the event wait list. +* +* Arguments : pevent is a pointer to the event control block allocated to the event. +* +* Returns : none +* +* Note : This function is INTERNAL to uC/OS-II and your application should not call it. +********************************************************************************************************* +*/ +#if (OS_EVENT_EN) +void OS_EventWaitListInit (OS_EVENT *pevent) +{ +#if OS_LOWEST_PRIO <= 63 + INT8U *ptbl; +#else + INT16U *ptbl; +#endif + INT8U i; + + + pevent->OSEventGrp = 0; /* No task waiting on event */ + ptbl = &pevent->OSEventTbl[0]; + + for (i = 0; i < OS_EVENT_TBL_SIZE; i++) { + *ptbl++ = 0; + } +} +#endif +/*$PAGE*/ +/* +********************************************************************************************************* +* INITIALIZATION +* INITIALIZE THE FREE LIST OF EVENT CONTROL BLOCKS +* +* Description: This function is called by OSInit() to initialize the free list of event control blocks. +* +* Arguments : none +* +* Returns : none +********************************************************************************************************* +*/ + +static void OS_InitEventList (void) +{ +#if (OS_EVENT_EN) && (OS_MAX_EVENTS > 0) +#if (OS_MAX_EVENTS > 1) + INT16U i; + OS_EVENT *pevent1; + OS_EVENT *pevent2; + + + OS_MemClr((INT8U *)&OSEventTbl[0], sizeof(OSEventTbl)); /* Clear the event table */ + pevent1 = &OSEventTbl[0]; + pevent2 = &OSEventTbl[1]; + for (i = 0; i < (OS_MAX_EVENTS - 1); i++) { /* Init. list of free EVENT control blocks */ + pevent1->OSEventType = OS_EVENT_TYPE_UNUSED; + pevent1->OSEventPtr = pevent2; +#if OS_EVENT_NAME_SIZE > 1 + pevent1->OSEventName[0] = '?'; /* Unknown name */ + pevent1->OSEventName[1] = OS_ASCII_NUL; +#endif + pevent1++; + pevent2++; + } + pevent1->OSEventType = OS_EVENT_TYPE_UNUSED; + pevent1->OSEventPtr = (OS_EVENT *)0; +#if OS_EVENT_NAME_SIZE > 1 + pevent1->OSEventName[0] = '?'; + pevent1->OSEventName[1] = OS_ASCII_NUL; +#endif + OSEventFreeList = &OSEventTbl[0]; +#else + OSEventFreeList = &OSEventTbl[0]; /* Only have ONE event control block */ + OSEventFreeList->OSEventType = OS_EVENT_TYPE_UNUSED; + OSEventFreeList->OSEventPtr = (OS_EVENT *)0; +#if OS_EVENT_NAME_SIZE > 1 + OSEventFreeList->OSEventName[0] = '?'; /* Unknown name */ + OSEventFreeList->OSEventName[1] = OS_ASCII_NUL; +#endif +#endif +#endif +} +/*$PAGE*/ +/* +********************************************************************************************************* +* INITIALIZATION +* INITIALIZE MISCELLANEOUS VARIABLES +* +* Description: This function is called by OSInit() to initialize miscellaneous variables. +* +* Arguments : none +* +* Returns : none +********************************************************************************************************* +*/ + +static void OS_InitMisc (void) +{ +#if OS_TIME_GET_SET_EN > 0 + OSTime = 0L; /* Clear the 32-bit system clock */ +#endif + + OSIntNesting = 0; /* Clear the interrupt nesting counter */ + OSLockNesting = 0; /* Clear the scheduling lock counter */ + + OSTaskCtr = 0; /* Clear the number of tasks */ + + OSRunning = OS_FALSE; /* Indicate that multitasking not started */ + + OSCtxSwCtr = 0; /* Clear the context switch counter */ + OSIdleCtr = 0L; /* Clear the 32-bit idle counter */ + +#if OS_TASK_STAT_EN > 0 + OSIdleCtrRun = 0L; + OSIdleCtrMax = 0L; + OSStatRdy = OS_FALSE; /* Statistic task is not ready */ +#endif +} +/*$PAGE*/ +/* +********************************************************************************************************* +* INITIALIZATION +* INITIALIZE THE READY LIST +* +* Description: This function is called by OSInit() to initialize the Ready List. +* +* Arguments : none +* +* Returns : none +********************************************************************************************************* +*/ + +static void OS_InitRdyList (void) +{ + INT8U i; +#if OS_LOWEST_PRIO <= 63 + INT8U *prdytbl; +#else + INT16U *prdytbl; +#endif + + + OSRdyGrp = 0; /* Clear the ready list */ + prdytbl = &OSRdyTbl[0]; + for (i = 0; i < OS_RDY_TBL_SIZE; i++) { + *prdytbl++ = 0; + } + + OSPrioCur = 0; + OSPrioHighRdy = 0; + + OSTCBHighRdy = (OS_TCB *)0; + OSTCBCur = (OS_TCB *)0; +} + +/*$PAGE*/ +/* +********************************************************************************************************* +* INITIALIZATION +* CREATING THE IDLE TASK +* +* Description: This function creates the Idle Task. +* +* Arguments : none +* +* Returns : none +********************************************************************************************************* +*/ + +static void OS_InitTaskIdle (void) +{ +#if OS_TASK_NAME_SIZE > 7 + INT8U err; +#endif + + +#if OS_TASK_CREATE_EXT_EN > 0 + #if OS_STK_GROWTH == 1 + (void)OSTaskCreateExt(OS_TaskIdle, + (void *)0, /* No arguments passed to OS_TaskIdle() */ + &OSTaskIdleStk[OS_TASK_IDLE_STK_SIZE - 1], /* Set Top-Of-Stack */ + OS_TASK_IDLE_PRIO, /* Lowest priority level */ + OS_TASK_IDLE_ID, + &OSTaskIdleStk[0], /* Set Bottom-Of-Stack */ + OS_TASK_IDLE_STK_SIZE, + (void *)0, /* No TCB extension */ + OS_TASK_OPT_STK_CHK | OS_TASK_OPT_STK_CLR);/* Enable stack checking + clear stack */ + #else + (void)OSTaskCreateExt(OS_TaskIdle, + (void *)0, /* No arguments passed to OS_TaskIdle() */ + &OSTaskIdleStk[0], /* Set Top-Of-Stack */ + OS_TASK_IDLE_PRIO, /* Lowest priority level */ + OS_TASK_IDLE_ID, + &OSTaskIdleStk[OS_TASK_IDLE_STK_SIZE - 1], /* Set Bottom-Of-Stack */ + OS_TASK_IDLE_STK_SIZE, + (void *)0, /* No TCB extension */ + OS_TASK_OPT_STK_CHK | OS_TASK_OPT_STK_CLR);/* Enable stack checking + clear stack */ + #endif +#else + #if OS_STK_GROWTH == 1 + (void)OSTaskCreate(OS_TaskIdle, + (void *)0, + &OSTaskIdleStk[OS_TASK_IDLE_STK_SIZE - 1], + OS_TASK_IDLE_PRIO); + #else + (void)OSTaskCreate(OS_TaskIdle, + (void *)0, + &OSTaskIdleStk[0], + OS_TASK_IDLE_PRIO); + #endif +#endif + +#if OS_TASK_NAME_SIZE > 14 + OSTaskNameSet(OS_TASK_IDLE_PRIO, (INT8U *)"uC/OS-II Idle", &err); +#else +#if OS_TASK_NAME_SIZE > 7 + OSTaskNameSet(OS_TASK_IDLE_PRIO, (INT8U *)"OS-Idle", &err); +#endif +#endif +} +/*$PAGE*/ +/* +********************************************************************************************************* +* INITIALIZATION +* CREATING THE STATISTIC TASK +* +* Description: This function creates the Statistic Task. +* +* Arguments : none +* +* Returns : none +********************************************************************************************************* +*/ + +#if OS_TASK_STAT_EN > 0 +static void OS_InitTaskStat (void) +{ +#if OS_TASK_NAME_SIZE > 7 + INT8U err; +#endif + + +#if OS_TASK_CREATE_EXT_EN > 0 + #if OS_STK_GROWTH == 1 + (void)OSTaskCreateExt(OS_TaskStat, + (void *)0, /* No args passed to OS_TaskStat()*/ + &OSTaskStatStk[OS_TASK_STAT_STK_SIZE - 1], /* Set Top-Of-Stack */ + OS_TASK_STAT_PRIO, /* One higher than the idle task */ + OS_TASK_STAT_ID, + &OSTaskStatStk[0], /* Set Bottom-Of-Stack */ + OS_TASK_STAT_STK_SIZE, + (void *)0, /* No TCB extension */ + OS_TASK_OPT_STK_CHK | OS_TASK_OPT_STK_CLR); /* Enable stack checking + clear */ + #else + (void)OSTaskCreateExt(OS_TaskStat, + (void *)0, /* No args passed to OS_TaskStat()*/ + &OSTaskStatStk[0], /* Set Top-Of-Stack */ + OS_TASK_STAT_PRIO, /* One higher than the idle task */ + OS_TASK_STAT_ID, + &OSTaskStatStk[OS_TASK_STAT_STK_SIZE - 1], /* Set Bottom-Of-Stack */ + OS_TASK_STAT_STK_SIZE, + (void *)0, /* No TCB extension */ + OS_TASK_OPT_STK_CHK | OS_TASK_OPT_STK_CLR); /* Enable stack checking + clear */ + #endif +#else + #if OS_STK_GROWTH == 1 + (void)OSTaskCreate(OS_TaskStat, + (void *)0, /* No args passed to OS_TaskStat()*/ + &OSTaskStatStk[OS_TASK_STAT_STK_SIZE - 1], /* Set Top-Of-Stack */ + OS_TASK_STAT_PRIO); /* One higher than the idle task */ + #else + (void)OSTaskCreate(OS_TaskStat, + (void *)0, /* No args passed to OS_TaskStat()*/ + &OSTaskStatStk[0], /* Set Top-Of-Stack */ + OS_TASK_STAT_PRIO); /* One higher than the idle task */ + #endif +#endif + +#if OS_TASK_NAME_SIZE > 14 + OSTaskNameSet(OS_TASK_STAT_PRIO, (INT8U *)"uC/OS-II Stat", &err); +#else +#if OS_TASK_NAME_SIZE > 7 + OSTaskNameSet(OS_TASK_STAT_PRIO, (INT8U *)"OS-Stat", &err); +#endif +#endif +} +#endif +/*$PAGE*/ +/* +********************************************************************************************************* +* INITIALIZATION +* INITIALIZE THE FREE LIST OF TASK CONTROL BLOCKS +* +* Description: This function is called by OSInit() to initialize the free list of OS_TCBs. +* +* Arguments : none +* +* Returns : none +********************************************************************************************************* +*/ + +static void OS_InitTCBList (void) +{ + INT8U i; + OS_TCB *ptcb1; + OS_TCB *ptcb2; + + + OS_MemClr((INT8U *)&OSTCBTbl[0], sizeof(OSTCBTbl)); /* Clear all the TCBs */ + OS_MemClr((INT8U *)&OSTCBPrioTbl[0], sizeof(OSTCBPrioTbl)); /* Clear the priority table */ + ptcb1 = &OSTCBTbl[0]; + ptcb2 = &OSTCBTbl[1]; + for (i = 0; i < (OS_MAX_TASKS + OS_N_SYS_TASKS - 1); i++) { /* Init. list of free TCBs */ + ptcb1->OSTCBNext = ptcb2; +#if OS_TASK_NAME_SIZE > 1 + ptcb1->OSTCBTaskName[0] = '?'; /* Unknown name */ + ptcb1->OSTCBTaskName[1] = OS_ASCII_NUL; +#endif + ptcb1++; + ptcb2++; + } + ptcb1->OSTCBNext = (OS_TCB *)0; /* Last OS_TCB */ +#if OS_TASK_NAME_SIZE > 1 + ptcb1->OSTCBTaskName[0] = '?'; /* Unknown name */ + ptcb1->OSTCBTaskName[1] = OS_ASCII_NUL; +#endif + OSTCBList = (OS_TCB *)0; /* TCB lists initializations */ + OSTCBFreeList = &OSTCBTbl[0]; +} +/*$PAGE*/ +/* +********************************************************************************************************* +* CLEAR A SECTION OF MEMORY +* +* Description: This function is called by other uC/OS-II services to clear a contiguous block of RAM. +* +* Arguments : pdest is the start of the RAM to clear (i.e. write 0x00 to) +* +* size is the number of bytes to clear. +* +* Returns : none +* +* Notes : 1) This function is INTERNAL to uC/OS-II and your application should not call it. +* 2) Note that we can only clear up to 64K bytes of RAM. This is not an issue because none +* of the uses of this function gets close to this limit. +* 3) The clear is done one byte at a time since this will work on any processor irrespective +* of the alignment of the destination. +********************************************************************************************************* +*/ + +void OS_MemClr (INT8U *pdest, INT16U size) +{ + while (size > 0) { + *pdest++ = (INT8U)0; + size--; + } +} +/*$PAGE*/ +/* +********************************************************************************************************* +* COPY A BLOCK OF MEMORY +* +* Description: This function is called by other uC/OS-II services to copy a block of memory from one +* location to another. +* +* Arguments : pdest is a pointer to the 'destination' memory block +* +* psrc is a pointer to the 'source' memory block +* +* size is the number of bytes to copy. +* +* Returns : none +* +* Notes : 1) This function is INTERNAL to uC/OS-II and your application should not call it. There is +* no provision to handle overlapping memory copy. However, that's not a problem since this +* is not a situation that will happen. +* 2) Note that we can only copy up to 64K bytes of RAM +* 3) The copy is done one byte at a time since this will work on any processor irrespective +* of the alignment of the source and destination. +********************************************************************************************************* +*/ + +void OS_MemCopy (INT8U *pdest, INT8U *psrc, INT16U size) +{ + while (size > 0) { + *pdest++ = *psrc++; + size--; + } +} +/*$PAGE*/ +/* +********************************************************************************************************* +* SCHEDULER +* +* Description: This function is called by other uC/OS-II services to determine whether a new, high +* priority task has been made ready to run. This function is invoked by TASK level code +* and is not used to reschedule tasks from ISRs (see OSIntExit() for ISR rescheduling). +* +* Arguments : none +* +* Returns : none +* +* Notes : 1) This function is INTERNAL to uC/OS-II and your application should not call it. +* 2) Rescheduling is prevented when the scheduler is locked (see OS_SchedLock()) +********************************************************************************************************* +*/ + +void OS_Sched (void) +{ +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + + OS_ENTER_CRITICAL(); + if (OSIntNesting == 0) { /* Schedule only if all ISRs done and ... */ + if (OSLockNesting == 0) { /* ... scheduler is not locked */ + OS_SchedNew(); + if (OSPrioHighRdy != OSPrioCur) { /* No Ctx Sw if current task is highest rdy */ + OSTCBHighRdy = OSTCBPrioTbl[OSPrioHighRdy]; +#if OS_TASK_PROFILE_EN > 0 + OSTCBHighRdy->OSTCBCtxSwCtr++; /* Inc. # of context switches to this task */ +#endif + OSCtxSwCtr++; /* Increment context switch counter */ + OS_TASK_SW(); /* Perform a context switch */ + } + } + } + OS_EXIT_CRITICAL(); +} + + +/* +********************************************************************************************************* +* FIND HIGHEST PRIORITY TASK READY TO RUN +* +* Description: This function is called by other uC/OS-II services to determine the highest priority task +* that is ready to run. The global variable 'OSPrioHighRdy' is changed accordingly. +* +* Arguments : none +* +* Returns : none +* +* Notes : 1) This function is INTERNAL to uC/OS-II and your application should not call it. +* 2) Interrupts are assumed to be disabled when this function is called. +********************************************************************************************************* +*/ + +static void OS_SchedNew (void) +{ +#if OS_LOWEST_PRIO <= 63 /* See if we support up to 64 tasks */ + INT8U y; + + + y = OSUnMapTbl[OSRdyGrp]; + OSPrioHighRdy = (INT8U)((y << 3) + OSUnMapTbl[OSRdyTbl[y]]); +#else /* We support up to 256 tasks */ + INT8U y; + INT16U *ptbl; + + + if ((OSRdyGrp & 0xFF) != 0) { + y = OSUnMapTbl[OSRdyGrp & 0xFF]; + } else { + y = OSUnMapTbl[(OSRdyGrp >> 8) & 0xFF] + 8; + } + ptbl = &OSRdyTbl[y]; + if ((*ptbl & 0xFF) != 0) { + OSPrioHighRdy = (INT8U)((y << 4) + OSUnMapTbl[(*ptbl & 0xFF)]); + } else { + OSPrioHighRdy = (INT8U)((y << 4) + OSUnMapTbl[(*ptbl >> 8) & 0xFF] + 8); + } +#endif +} + +/*$PAGE*/ +/* +********************************************************************************************************* +* COPY AN ASCII STRING +* +* Description: This function is called by other uC/OS-II services to copy an ASCII string from a 'source' +* string to a 'destination' string. +* +* Arguments : pdest is a pointer to the string that will be receiving the copy. Note that there MUST +* be sufficient space in the destination storage area to receive this string. +* +* psrc is a pointer to the source string. The source string MUST NOT be greater than +* 254 characters. +* +* Returns : The size of the string (excluding the NUL terminating character) +* +* Notes : 1) This function is INTERNAL to uC/OS-II and your application should not call it. +********************************************************************************************************* +*/ + +#if (OS_EVENT_NAME_SIZE > 1) || (OS_FLAG_NAME_SIZE > 1) || (OS_MEM_NAME_SIZE > 1) || (OS_TASK_NAME_SIZE > 1) || (OS_TMR_CFG_NAME_SIZE > 1) +INT8U OS_StrCopy (INT8U *pdest, INT8U *psrc) +{ + INT8U len; + + + len = 0; + while (*psrc != OS_ASCII_NUL) { + *pdest++ = *psrc++; + len++; + } + *pdest = OS_ASCII_NUL; + return (len); +} +#endif +/*$PAGE*/ +/* +********************************************************************************************************* +* DETERMINE THE LENGTH OF AN ASCII STRING +* +* Description: This function is called by other uC/OS-II services to determine the size of an ASCII string +* (excluding the NUL character). +* +* Arguments : psrc is a pointer to the string for which we need to know the size. +* +* Returns : The size of the string (excluding the NUL terminating character) +* +* Notes : 1) This function is INTERNAL to uC/OS-II and your application should not call it. +* 2) The string to check must be less than 255 characters long. +********************************************************************************************************* +*/ + +#if (OS_EVENT_NAME_SIZE > 1) || (OS_FLAG_NAME_SIZE > 1) || (OS_MEM_NAME_SIZE > 1) || (OS_TASK_NAME_SIZE > 1) || (OS_TMR_CFG_NAME_SIZE > 1) +INT8U OS_StrLen (INT8U *psrc) +{ + INT8U len; + + + len = 0; + while (*psrc != OS_ASCII_NUL) { + psrc++; + len++; + } + return (len); +} +#endif +/*$PAGE*/ +/* +********************************************************************************************************* +* IDLE TASK +* +* Description: This task is internal to uC/OS-II and executes whenever no other higher priority tasks +* executes because they are ALL waiting for event(s) to occur. +* +* Arguments : none +* +* Returns : none +* +* Note(s) : 1) OSTaskIdleHook() is called after the critical section to ensure that interrupts will be +* enabled for at least a few instructions. On some processors (ex. Philips XA), enabling +* and then disabling interrupts didn't allow the processor enough time to have interrupts +* enabled before they were disabled again. uC/OS-II would thus never recognize +* interrupts. +* 2) This hook has been added to allow you to do such things as STOP the CPU to conserve +* power. +********************************************************************************************************* +*/ + +void OS_TaskIdle (void *p_arg) +{ +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + + (void)p_arg; /* Prevent compiler warning for not using 'p_arg' */ + for (;;) { + OS_ENTER_CRITICAL(); + OSIdleCtr++; + OS_EXIT_CRITICAL(); + OSTaskIdleHook(); /* Call user definable HOOK */ + } +} +/*$PAGE*/ +/* +********************************************************************************************************* +* STATISTICS TASK +* +* Description: This task is internal to uC/OS-II and is used to compute some statistics about the +* multitasking environment. Specifically, OS_TaskStat() computes the CPU usage. +* CPU usage is determined by: +* +* OSIdleCtr +* OSCPUUsage = 100 * (1 - ------------) (units are in %) +* OSIdleCtrMax +* +* Arguments : parg this pointer is not used at this time. +* +* Returns : none +* +* Notes : 1) This task runs at a priority level higher than the idle task. In fact, it runs at the +* next higher priority, OS_TASK_IDLE_PRIO-1. +* 2) You can disable this task by setting the configuration #define OS_TASK_STAT_EN to 0. +* 3) You MUST have at least a delay of 2/10 seconds to allow for the system to establish the +* maximum value for the idle counter. +********************************************************************************************************* +*/ + +#if OS_TASK_STAT_EN > 0 +void OS_TaskStat (void *p_arg) +{ +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + + (void)p_arg; /* Prevent compiler warning for not using 'p_arg' */ + while (OSStatRdy == OS_FALSE) { + OSTimeDly(2 * OS_TICKS_PER_SEC / 10); /* Wait until statistic task is ready */ + } + OSIdleCtrMax /= 100L; + if (OSIdleCtrMax == 0L) { + OSCPUUsage = 0; + (void)OSTaskSuspend(OS_PRIO_SELF); + } + for (;;) { + OS_ENTER_CRITICAL(); + OSIdleCtrRun = OSIdleCtr; /* Obtain the of the idle counter for the past second */ + OSIdleCtr = 0L; /* Reset the idle counter for the next second */ + OS_EXIT_CRITICAL(); + OSCPUUsage = (INT8U)(100L - OSIdleCtrRun / OSIdleCtrMax); + OSTaskStatHook(); /* Invoke user definable hook */ +#if (OS_TASK_STAT_STK_CHK_EN > 0) && (OS_TASK_CREATE_EXT_EN > 0) + OS_TaskStatStkChk(); /* Check the stacks for each task */ +#endif + OSTimeDly(OS_TICKS_PER_SEC / 10); /* Accumulate OSIdleCtr for the next 1/10 second */ + } +} +#endif +/*$PAGE*/ +/* +********************************************************************************************************* +* CHECK ALL TASK STACKS +* +* Description: This function is called by OS_TaskStat() to check the stacks of each active task. +* +* Arguments : none +* +* Returns : none +********************************************************************************************************* +*/ + +#if (OS_TASK_STAT_STK_CHK_EN > 0) && (OS_TASK_CREATE_EXT_EN > 0) +void OS_TaskStatStkChk (void) +{ + OS_TCB *ptcb; + OS_STK_DATA stk_data; + INT8U err; + INT8U prio; + + + for (prio = 0; prio <= OS_TASK_IDLE_PRIO; prio++) { + err = OSTaskStkChk(prio, &stk_data); + if (err == OS_ERR_NONE) { + ptcb = OSTCBPrioTbl[prio]; + if (ptcb != (OS_TCB *)0) { /* Make sure task 'ptcb' is ... */ + if (ptcb != OS_TCB_RESERVED) { /* ... still valid. */ +#if OS_TASK_PROFILE_EN > 0 + #if OS_STK_GROWTH == 1 + ptcb->OSTCBStkBase = ptcb->OSTCBStkBottom + ptcb->OSTCBStkSize; + #else + ptcb->OSTCBStkBase = ptcb->OSTCBStkBottom - ptcb->OSTCBStkSize; + #endif + ptcb->OSTCBStkUsed = stk_data.OSUsed; /* Store the number of bytes used */ +#endif + } + } + } + } +} +#endif +/*$PAGE*/ +/* +********************************************************************************************************* +* INITIALIZE TCB +* +* Description: This function is internal to uC/OS-II and is used to initialize a Task Control Block when +* a task is created (see OSTaskCreate() and OSTaskCreateExt()). +* +* Arguments : prio is the priority of the task being created +* +* ptos is a pointer to the task's top-of-stack assuming that the CPU registers +* have been placed on the stack. Note that the top-of-stack corresponds to a +* 'high' memory location is OS_STK_GROWTH is set to 1 and a 'low' memory +* location if OS_STK_GROWTH is set to 0. Note that stack growth is CPU +* specific. +* +* pbos is a pointer to the bottom of stack. A NULL pointer is passed if called by +* 'OSTaskCreate()'. +* +* id is the task's ID (0..65535) +* +* stk_size is the size of the stack (in 'stack units'). If the stack units are INT8Us +* then, 'stk_size' contains the number of bytes for the stack. If the stack +* units are INT32Us then, the stack contains '4 * stk_size' bytes. The stack +* units are established by the #define constant OS_STK which is CPU +* specific. 'stk_size' is 0 if called by 'OSTaskCreate()'. +* +* pext is a pointer to a user supplied memory area that is used to extend the task +* control block. This allows you to store the contents of floating-point +* registers, MMU registers or anything else you could find useful during a +* context switch. You can even assign a name to each task and store this name +* in this TCB extension. A NULL pointer is passed if called by OSTaskCreate(). +* +* opt options as passed to 'OSTaskCreateExt()' or, +* 0 if called from 'OSTaskCreate()'. +* +* Returns : OS_ERR_NONE if the call was successful +* OS_ERR_TASK_NO_MORE_TCB if there are no more free TCBs to be allocated and thus, the task cannot +* be created. +* +* Note : This function is INTERNAL to uC/OS-II and your application should not call it. +********************************************************************************************************* +*/ + +INT8U OS_TCBInit (INT8U prio, OS_STK *ptos, OS_STK *pbos, INT16U id, INT32U stk_size, void *pext, INT16U opt) +{ + OS_TCB *ptcb; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + + OS_ENTER_CRITICAL(); + ptcb = OSTCBFreeList; /* Get a free TCB from the free TCB list */ + if (ptcb != (OS_TCB *)0) { + OSTCBFreeList = ptcb->OSTCBNext; /* Update pointer to free TCB list */ + OS_EXIT_CRITICAL(); + ptcb->OSTCBStkPtr = ptos; /* Load Stack pointer in TCB */ + ptcb->OSTCBPrio = prio; /* Load task priority into TCB */ + ptcb->OSTCBStat = OS_STAT_RDY; /* Task is ready to run */ + ptcb->OSTCBStatPend = OS_STAT_PEND_OK; /* Clear pend status */ + ptcb->OSTCBDly = 0; /* Task is not delayed */ + +#if OS_TASK_CREATE_EXT_EN > 0 + ptcb->OSTCBExtPtr = pext; /* Store pointer to TCB extension */ + ptcb->OSTCBStkSize = stk_size; /* Store stack size */ + ptcb->OSTCBStkBottom = pbos; /* Store pointer to bottom of stack */ + ptcb->OSTCBOpt = opt; /* Store task options */ + ptcb->OSTCBId = id; /* Store task ID */ +#else + pext = pext; /* Prevent compiler warning if not used */ + stk_size = stk_size; + pbos = pbos; + opt = opt; + id = id; +#endif + +#if OS_TASK_DEL_EN > 0 + ptcb->OSTCBDelReq = OS_ERR_NONE; +#endif + +#if OS_LOWEST_PRIO <= 63 + ptcb->OSTCBY = (INT8U)(prio >> 3); /* Pre-compute X, Y, BitX and BitY */ + ptcb->OSTCBX = (INT8U)(prio & 0x07); + ptcb->OSTCBBitY = (INT8U)(1 << ptcb->OSTCBY); + ptcb->OSTCBBitX = (INT8U)(1 << ptcb->OSTCBX); +#else + ptcb->OSTCBY = (INT8U)((prio >> 4) & 0xFF); /* Pre-compute X, Y, BitX and BitY */ + ptcb->OSTCBX = (INT8U) (prio & 0x0F); + ptcb->OSTCBBitY = (INT16U)(1 << ptcb->OSTCBY); + ptcb->OSTCBBitX = (INT16U)(1 << ptcb->OSTCBX); +#endif + +#if (OS_EVENT_EN) + ptcb->OSTCBEventPtr = (OS_EVENT *)0; /* Task is not pending on an event */ +#if (OS_EVENT_MULTI_EN > 0) + ptcb->OSTCBEventMultiPtr = (OS_EVENT **)0; /* Task is not pending on any events */ +#endif +#endif + +#if (OS_FLAG_EN > 0) && (OS_MAX_FLAGS > 0) && (OS_TASK_DEL_EN > 0) + ptcb->OSTCBFlagNode = (OS_FLAG_NODE *)0; /* Task is not pending on an event flag */ +#endif + +#if (OS_MBOX_EN > 0) || ((OS_Q_EN > 0) && (OS_MAX_QS > 0)) + ptcb->OSTCBMsg = (void *)0; /* No message received */ +#endif + +#if OS_TASK_PROFILE_EN > 0 + ptcb->OSTCBCtxSwCtr = 0L; /* Initialize profiling variables */ + ptcb->OSTCBCyclesStart = 0L; + ptcb->OSTCBCyclesTot = 0L; + ptcb->OSTCBStkBase = (OS_STK *)0; + ptcb->OSTCBStkUsed = 0L; +#endif + +#if OS_TASK_NAME_SIZE > 1 + ptcb->OSTCBTaskName[0] = '?'; /* Unknown name at task creation */ + ptcb->OSTCBTaskName[1] = OS_ASCII_NUL; +#endif + + OSTCBInitHook(ptcb); + + OSTaskCreateHook(ptcb); /* Call user defined hook */ + + OS_ENTER_CRITICAL(); + OSTCBPrioTbl[prio] = ptcb; + ptcb->OSTCBNext = OSTCBList; /* Link into TCB chain */ + ptcb->OSTCBPrev = (OS_TCB *)0; + if (OSTCBList != (OS_TCB *)0) { + OSTCBList->OSTCBPrev = ptcb; + } + OSTCBList = ptcb; + OSRdyGrp |= ptcb->OSTCBBitY; /* Make task ready to run */ + OSRdyTbl[ptcb->OSTCBY] |= ptcb->OSTCBBitX; + OSTaskCtr++; /* Increment the #tasks counter */ + OS_EXIT_CRITICAL(); + return (OS_ERR_NONE); + } + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_NO_MORE_TCB); +} diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/UCOSII/src/os_dbg.c b/MCandWifiTestDE0/Software/MCTest_bsp/UCOSII/src/os_dbg.c new file mode 100644 index 00000000..428c0a7d --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/UCOSII/src/os_dbg.c @@ -0,0 +1,312 @@ +/* +********************************************************************************************************* +* uC/OS-II +* The Real-Time Kernel +* DEBUGGER CONSTANTS +* +* (c) Copyright 1992-2007, Micrium, Weston, FL +* All Rights Reserved +* +* File : OS_DBG.C +* By : Jean J. Labrosse +* Version : V2.86 +* +* LICENSING TERMS: +* --------------- +* uC/OS-II is provided in source form for FREE evaluation, for educational use or for peaceful research. +* If you plan on using uC/OS-II in a commercial product you need to contact Micriµm to properly license +* its use in your product. We provide ALL the source code for your convenience and to help you experience +* uC/OS-II. The fact that the source is provided does NOT mean that you can use it without paying a +* licensing fee. +********************************************************************************************************* +*/ + +#include + +/* +********************************************************************************************************* +* DEBUG DATA +********************************************************************************************************* +*/ + +INT16U const OSDebugEn = OS_DEBUG_EN; /* Debug constants are defined below */ + +#if OS_DEBUG_EN > 0 + +INT32U const OSEndiannessTest = 0x12345678L; /* Variable to test CPU endianness */ + +INT16U const OSEventEn = OS_EVENT_EN; +INT16U const OSEventMax = OS_MAX_EVENTS; /* Number of event control blocks */ +INT16U const OSEventNameSize = OS_EVENT_NAME_SIZE; /* Size (in bytes) of event names */ +#if (OS_EVENT_EN) && (OS_MAX_EVENTS > 0) +INT16U const OSEventSize = sizeof(OS_EVENT); /* Size in Bytes of OS_EVENT */ +INT16U const OSEventTblSize = sizeof(OSEventTbl); /* Size of OSEventTbl[] in bytes */ +#else +INT16U const OSEventSize = 0; +INT16U const OSEventTblSize = 0; +#endif +INT16U const OSEventMultiEn = OS_EVENT_MULTI_EN; + + +INT16U const OSFlagEn = OS_FLAG_EN; +#if (OS_FLAG_EN > 0) && (OS_MAX_FLAGS > 0) +INT16U const OSFlagGrpSize = sizeof(OS_FLAG_GRP); /* Size in Bytes of OS_FLAG_GRP */ +INT16U const OSFlagNodeSize = sizeof(OS_FLAG_NODE); /* Size in Bytes of OS_FLAG_NODE */ +INT16U const OSFlagWidth = sizeof(OS_FLAGS); /* Width (in bytes) of OS_FLAGS */ +#else +INT16U const OSFlagGrpSize = 0; +INT16U const OSFlagNodeSize = 0; +INT16U const OSFlagWidth = 0; +#endif +INT16U const OSFlagMax = OS_MAX_FLAGS; +INT16U const OSFlagNameSize = OS_FLAG_NAME_SIZE; /* Size (in bytes) of flag names */ + +INT16U const OSLowestPrio = OS_LOWEST_PRIO; + +INT16U const OSMboxEn = OS_MBOX_EN; + +INT16U const OSMemEn = OS_MEM_EN; +INT16U const OSMemMax = OS_MAX_MEM_PART; /* Number of memory partitions */ +INT16U const OSMemNameSize = OS_MEM_NAME_SIZE; /* Size (in bytes) of partition names */ +#if (OS_MEM_EN > 0) && (OS_MAX_MEM_PART > 0) +INT16U const OSMemSize = sizeof(OS_MEM); /* Mem. Partition header sine (bytes) */ +INT16U const OSMemTblSize = sizeof(OSMemTbl); +#else +INT16U const OSMemSize = 0; +INT16U const OSMemTblSize = 0; +#endif +INT16U const OSMutexEn = OS_MUTEX_EN; + +INT16U const OSPtrSize = sizeof(void *); /* Size in Bytes of a pointer */ + +INT16U const OSQEn = OS_Q_EN; +INT16U const OSQMax = OS_MAX_QS; /* Number of queues */ +#if (OS_Q_EN > 0) && (OS_MAX_QS > 0) +INT16U const OSQSize = sizeof(OS_Q); /* Size in bytes of OS_Q structure */ +#else +INT16U const OSQSize = 0; +#endif + +INT16U const OSRdyTblSize = OS_RDY_TBL_SIZE; /* Number of bytes in the ready table */ + +INT16U const OSSemEn = OS_SEM_EN; + +INT16U const OSStkWidth = sizeof(OS_STK); /* Size in Bytes of a stack entry */ + +INT16U const OSTaskCreateEn = OS_TASK_CREATE_EN; +INT16U const OSTaskCreateExtEn = OS_TASK_CREATE_EXT_EN; +INT16U const OSTaskDelEn = OS_TASK_DEL_EN; +INT16U const OSTaskIdleStkSize = OS_TASK_IDLE_STK_SIZE; +INT16U const OSTaskProfileEn = OS_TASK_PROFILE_EN; +INT16U const OSTaskMax = OS_MAX_TASKS + OS_N_SYS_TASKS; /* Total max. number of tasks */ +INT16U const OSTaskNameSize = OS_TASK_NAME_SIZE; /* Size (in bytes) of task names */ +INT16U const OSTaskStatEn = OS_TASK_STAT_EN; +INT16U const OSTaskStatStkSize = OS_TASK_STAT_STK_SIZE; +INT16U const OSTaskStatStkChkEn = OS_TASK_STAT_STK_CHK_EN; +INT16U const OSTaskSwHookEn = OS_TASK_SW_HOOK_EN; + +INT16U const OSTCBPrioTblMax = OS_LOWEST_PRIO + 1; /* Number of entries in OSTCBPrioTbl[] */ +INT16U const OSTCBSize = sizeof(OS_TCB); /* Size in Bytes of OS_TCB */ +INT16U const OSTicksPerSec = OS_TICKS_PER_SEC; +INT16U const OSTimeTickHookEn = OS_TIME_TICK_HOOK_EN; +INT16U const OSVersionNbr = OS_VERSION; + +INT16U const OSTmrEn = OS_TMR_EN; +INT16U const OSTmrCfgMax = OS_TMR_CFG_MAX; +INT16U const OSTmrCfgNameSize = OS_TMR_CFG_NAME_SIZE; +INT16U const OSTmrCfgWheelSize = OS_TMR_CFG_WHEEL_SIZE; +INT16U const OSTmrCfgTicksPerSec = OS_TMR_CFG_TICKS_PER_SEC; + +#if (OS_TMR_EN > 0) && (OS_TMR_CFG_MAX > 0) +INT16U const OSTmrSize = sizeof(OS_TMR); +INT16U const OSTmrTblSize = sizeof(OSTmrTbl); +INT16U const OSTmrWheelSize = sizeof(OS_TMR_WHEEL); +INT16U const OSTmrWheelTblSize = sizeof(OSTmrWheelTbl); +#else +INT16U const OSTmrSize = 0; +INT16U const OSTmrTblSize = 0; +INT16U const OSTmrWheelSize = 0; +INT16U const OSTmrWheelTblSize = 0; +#endif + +#endif + +/*$PAGE*/ +/* +********************************************************************************************************* +* DEBUG DATA +* TOTAL DATA SPACE (i.e. RAM) USED BY uC/OS-II +********************************************************************************************************* +*/ +#if OS_DEBUG_EN > 0 + +INT16U const OSDataSize = sizeof(OSCtxSwCtr) +#if (OS_EVENT_EN) && (OS_MAX_EVENTS > 0) + + sizeof(OSEventFreeList) + + sizeof(OSEventTbl) +#endif +#if (OS_FLAG_EN > 0) && (OS_MAX_FLAGS > 0) + + sizeof(OSFlagTbl) + + sizeof(OSFlagFreeList) +#endif +#if OS_TASK_STAT_EN > 0 + + sizeof(OSCPUUsage) + + sizeof(OSIdleCtrMax) + + sizeof(OSIdleCtrRun) + + sizeof(OSStatRdy) + + sizeof(OSTaskStatStk) +#endif +#if OS_TICK_STEP_EN > 0 + + sizeof(OSTickStepState) +#endif +#if (OS_MEM_EN > 0) && (OS_MAX_MEM_PART > 0) + + sizeof(OSMemFreeList) + + sizeof(OSMemTbl) +#endif +#if (OS_Q_EN > 0) && (OS_MAX_QS > 0) + + sizeof(OSQFreeList) + + sizeof(OSQTbl) +#endif +#if OS_TIME_GET_SET_EN > 0 + + sizeof(OSTime) +#endif +#if (OS_TMR_EN > 0) && (OS_TMR_CFG_MAX > 0) + + sizeof(OSTmrFree) + + sizeof(OSTmrUsed) + + sizeof(OSTmrTime) + + sizeof(OSTmrSem) + + sizeof(OSTmrSemSignal) + + sizeof(OSTmrTbl) + + sizeof(OSTmrFreeList) + + sizeof(OSTmrTaskStk) + + sizeof(OSTmrWheelTbl) +#endif + + sizeof(OSIntNesting) + + sizeof(OSLockNesting) + + sizeof(OSPrioCur) + + sizeof(OSPrioHighRdy) + + sizeof(OSRdyGrp) + + sizeof(OSRdyTbl) + + sizeof(OSRunning) + + sizeof(OSTaskCtr) + + sizeof(OSIdleCtr) + + sizeof(OSTaskIdleStk) + + sizeof(OSTCBCur) + + sizeof(OSTCBFreeList) + + sizeof(OSTCBHighRdy) + + sizeof(OSTCBList) + + sizeof(OSTCBPrioTbl) + + sizeof(OSTCBTbl); + +#endif + +/*$PAGE*/ +/* +********************************************************************************************************* +* OS DEBUG INITIALIZATION +* +* Description: This function is used to make sure that debug variables that are unused in the application +* are not optimized away. This function might not be necessary for all compilers. In this +* case, you should simply DELETE the code in this function while still leaving the declaration +* of the function itself. +* +* Arguments : none +* +* Returns : none +* +* Note(s) : (1) This code doesn't do anything, it simply prevents the compiler from optimizing out +* the 'const' variables which are declared in this file. +* (2) You may decide to 'compile out' the code (by using #if 0/#endif) INSIDE the function +* if your compiler DOES NOT optimize out the 'const' variables above. +********************************************************************************************************* +*/ + +#if OS_DEBUG_EN > 0 +void OSDebugInit (void) +{ + void *ptemp; + + + ptemp = (void *)&OSDebugEn; + + ptemp = (void *)&OSEndiannessTest; + + ptemp = (void *)&OSEventMax; + ptemp = (void *)&OSEventNameSize; + ptemp = (void *)&OSEventEn; + ptemp = (void *)&OSEventSize; + ptemp = (void *)&OSEventTblSize; + ptemp = (void *)&OSEventMultiEn; + + ptemp = (void *)&OSFlagEn; + ptemp = (void *)&OSFlagGrpSize; + ptemp = (void *)&OSFlagNodeSize; + ptemp = (void *)&OSFlagWidth; + ptemp = (void *)&OSFlagMax; + ptemp = (void *)&OSFlagNameSize; + + ptemp = (void *)&OSLowestPrio; + + ptemp = (void *)&OSMboxEn; + + ptemp = (void *)&OSMemEn; + ptemp = (void *)&OSMemMax; + ptemp = (void *)&OSMemNameSize; + ptemp = (void *)&OSMemSize; + ptemp = (void *)&OSMemTblSize; + + ptemp = (void *)&OSMutexEn; + + ptemp = (void *)&OSPtrSize; + + ptemp = (void *)&OSQEn; + ptemp = (void *)&OSQMax; + ptemp = (void *)&OSQSize; + + ptemp = (void *)&OSRdyTblSize; + + ptemp = (void *)&OSSemEn; + + ptemp = (void *)&OSStkWidth; + + ptemp = (void *)&OSTaskCreateEn; + ptemp = (void *)&OSTaskCreateExtEn; + ptemp = (void *)&OSTaskDelEn; + ptemp = (void *)&OSTaskIdleStkSize; + ptemp = (void *)&OSTaskProfileEn; + ptemp = (void *)&OSTaskMax; + ptemp = (void *)&OSTaskNameSize; + ptemp = (void *)&OSTaskStatEn; + ptemp = (void *)&OSTaskStatStkSize; + ptemp = (void *)&OSTaskStatStkChkEn; + ptemp = (void *)&OSTaskSwHookEn; + + ptemp = (void *)&OSTCBPrioTblMax; + ptemp = (void *)&OSTCBSize; + + ptemp = (void *)&OSTicksPerSec; + ptemp = (void *)&OSTimeTickHookEn; + +#if OS_TMR_EN > 0 + ptemp = (void *)&OSTmrTbl[0]; + ptemp = (void *)&OSTmrWheelTbl[0]; + + ptemp = (void *)&OSTmrEn; + ptemp = (void *)&OSTmrCfgMax; + ptemp = (void *)&OSTmrCfgNameSize; + ptemp = (void *)&OSTmrCfgWheelSize; + ptemp = (void *)&OSTmrCfgTicksPerSec; + ptemp = (void *)&OSTmrSize; + ptemp = (void *)&OSTmrTblSize; + + ptemp = (void *)&OSTmrWheelSize; + ptemp = (void *)&OSTmrWheelTblSize; +#endif + + ptemp = (void *)&OSVersionNbr; + + ptemp = (void *)&OSDataSize; + + ptemp = ptemp; /* Prevent compiler warning for 'ptemp' not being used! */ +} +#endif diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/UCOSII/src/os_flag.c b/MCandWifiTestDE0/Software/MCTest_bsp/UCOSII/src/os_flag.c new file mode 100644 index 00000000..b255d286 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/UCOSII/src/os_flag.c @@ -0,0 +1,1174 @@ +/* +********************************************************************************************************* +* uC/OS-II +* The Real-Time Kernel +* EVENT FLAG MANAGEMENT +* +* (c) Copyright 1992-2007, Micrium, Weston, FL +* All Rights Reserved +* +* File : OS_FLAG.C +* By : Jean J. Labrosse +* Version : V2.86 +* +* LICENSING TERMS: +* --------------- +* uC/OS-II is provided in source form for FREE evaluation, for educational use or for peaceful research. +* If you plan on using uC/OS-II in a commercial product you need to contact Micriµm to properly license +* its use in your product. We provide ALL the source code for your convenience and to help you experience +* uC/OS-II. The fact that the source is provided does NOT mean that you can use it without paying a +* licensing fee. +********************************************************************************************************* +*/ + +#ifndef OS_MASTER_FILE +#include +#endif + +#if (OS_FLAG_EN > 0) && (OS_MAX_FLAGS > 0) +/* +********************************************************************************************************* +* LOCAL PROTOTYPES +********************************************************************************************************* +*/ + +static void OS_FlagBlock(OS_FLAG_GRP *pgrp, OS_FLAG_NODE *pnode, OS_FLAGS flags, INT8U wait_type, INT16U timeout); +static BOOLEAN OS_FlagTaskRdy(OS_FLAG_NODE *pnode, OS_FLAGS flags_rdy); + +/*$PAGE*/ +/* +********************************************************************************************************* +* CHECK THE STATUS OF FLAGS IN AN EVENT FLAG GROUP +* +* Description: This function is called to check the status of a combination of bits to be set or cleared +* in an event flag group. Your application can check for ANY bit to be set/cleared or ALL +* bits to be set/cleared. +* +* This call does not block if the desired flags are not present. +* +* Arguments : pgrp is a pointer to the desired event flag group. +* +* flags Is a bit pattern indicating which bit(s) (i.e. flags) you wish to check. +* The bits you want are specified by setting the corresponding bits in +* 'flags'. e.g. if your application wants to wait for bits 0 and 1 then +* 'flags' would contain 0x03. +* +* wait_type specifies whether you want ALL bits to be set/cleared or ANY of the bits +* to be set/cleared. +* You can specify the following argument: +* +* OS_FLAG_WAIT_CLR_ALL You will check ALL bits in 'flags' to be clear (0) +* OS_FLAG_WAIT_CLR_ANY You will check ANY bit in 'flags' to be clear (0) +* OS_FLAG_WAIT_SET_ALL You will check ALL bits in 'flags' to be set (1) +* OS_FLAG_WAIT_SET_ANY You will check ANY bit in 'flags' to be set (1) +* +* NOTE: Add OS_FLAG_CONSUME if you want the event flag to be 'consumed' by +* the call. Example, to wait for any flag in a group AND then clear +* the flags that are present, set 'wait_type' to: +* +* OS_FLAG_WAIT_SET_ANY + OS_FLAG_CONSUME +* +* perr is a pointer to an error code and can be: +* OS_ERR_NONE No error +* OS_ERR_EVENT_TYPE You are not pointing to an event flag group +* OS_ERR_FLAG_WAIT_TYPE You didn't specify a proper 'wait_type' argument. +* OS_ERR_FLAG_INVALID_PGRP You passed a NULL pointer instead of the event flag +* group handle. +* OS_ERR_FLAG_NOT_RDY The desired flags you are waiting for are not +* available. +* +* Returns : The flags in the event flag group that made the task ready or, 0 if a timeout or an error +* occurred. +* +* Called from: Task or ISR +* +* Note(s) : 1) IMPORTANT, the behavior of this function has changed from PREVIOUS versions. The +* function NOW returns the flags that were ready INSTEAD of the current state of the +* event flags. +********************************************************************************************************* +*/ + +#if OS_FLAG_ACCEPT_EN > 0 +OS_FLAGS OSFlagAccept (OS_FLAG_GRP *pgrp, OS_FLAGS flags, INT8U wait_type, INT8U *perr) +{ + OS_FLAGS flags_rdy; + INT8U result; + BOOLEAN consume; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + return ((OS_FLAGS)0); + } + if (pgrp == (OS_FLAG_GRP *)0) { /* Validate 'pgrp' */ + *perr = OS_ERR_FLAG_INVALID_PGRP; + return ((OS_FLAGS)0); + } +#endif + if (pgrp->OSFlagType != OS_EVENT_TYPE_FLAG) { /* Validate event block type */ + *perr = OS_ERR_EVENT_TYPE; + return ((OS_FLAGS)0); + } + result = (INT8U)(wait_type & OS_FLAG_CONSUME); + if (result != (INT8U)0) { /* See if we need to consume the flags */ + wait_type &= ~OS_FLAG_CONSUME; + consume = OS_TRUE; + } else { + consume = OS_FALSE; + } +/*$PAGE*/ + *perr = OS_ERR_NONE; /* Assume NO error until proven otherwise. */ + OS_ENTER_CRITICAL(); + switch (wait_type) { + case OS_FLAG_WAIT_SET_ALL: /* See if all required flags are set */ + flags_rdy = (OS_FLAGS)(pgrp->OSFlagFlags & flags); /* Extract only the bits we want */ + if (flags_rdy == flags) { /* Must match ALL the bits that we want */ + if (consume == OS_TRUE) { /* See if we need to consume the flags */ + pgrp->OSFlagFlags &= ~flags_rdy; /* Clear ONLY the flags that we wanted */ + } + } else { + *perr = OS_ERR_FLAG_NOT_RDY; + } + OS_EXIT_CRITICAL(); + break; + + case OS_FLAG_WAIT_SET_ANY: + flags_rdy = (OS_FLAGS)(pgrp->OSFlagFlags & flags); /* Extract only the bits we want */ + if (flags_rdy != (OS_FLAGS)0) { /* See if any flag set */ + if (consume == OS_TRUE) { /* See if we need to consume the flags */ + pgrp->OSFlagFlags &= ~flags_rdy; /* Clear ONLY the flags that we got */ + } + } else { + *perr = OS_ERR_FLAG_NOT_RDY; + } + OS_EXIT_CRITICAL(); + break; + +#if OS_FLAG_WAIT_CLR_EN > 0 + case OS_FLAG_WAIT_CLR_ALL: /* See if all required flags are cleared */ + flags_rdy = (OS_FLAGS)(~pgrp->OSFlagFlags & flags); /* Extract only the bits we want */ + if (flags_rdy == flags) { /* Must match ALL the bits that we want */ + if (consume == OS_TRUE) { /* See if we need to consume the flags */ + pgrp->OSFlagFlags |= flags_rdy; /* Set ONLY the flags that we wanted */ + } + } else { + *perr = OS_ERR_FLAG_NOT_RDY; + } + OS_EXIT_CRITICAL(); + break; + + case OS_FLAG_WAIT_CLR_ANY: + flags_rdy = (OS_FLAGS)(~pgrp->OSFlagFlags & flags); /* Extract only the bits we want */ + if (flags_rdy != (OS_FLAGS)0) { /* See if any flag cleared */ + if (consume == OS_TRUE) { /* See if we need to consume the flags */ + pgrp->OSFlagFlags |= flags_rdy; /* Set ONLY the flags that we got */ + } + } else { + *perr = OS_ERR_FLAG_NOT_RDY; + } + OS_EXIT_CRITICAL(); + break; +#endif + + default: + OS_EXIT_CRITICAL(); + flags_rdy = (OS_FLAGS)0; + *perr = OS_ERR_FLAG_WAIT_TYPE; + break; + } + return (flags_rdy); +} +#endif + +/*$PAGE*/ +/* +********************************************************************************************************* +* CREATE AN EVENT FLAG +* +* Description: This function is called to create an event flag group. +* +* Arguments : flags Contains the initial value to store in the event flag group. +* +* perr is a pointer to an error code which will be returned to your application: +* OS_ERR_NONE if the call was successful. +* OS_ERR_CREATE_ISR if you attempted to create an Event Flag from an +* ISR. +* OS_ERR_FLAG_GRP_DEPLETED if there are no more event flag groups +* +* Returns : A pointer to an event flag group or a NULL pointer if no more groups are available. +* +* Called from: Task ONLY +********************************************************************************************************* +*/ + +OS_FLAG_GRP *OSFlagCreate (OS_FLAGS flags, INT8U *perr) +{ + OS_FLAG_GRP *pgrp; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + return ((OS_FLAG_GRP *)0); + } +#endif + if (OSIntNesting > 0) { /* See if called from ISR ... */ + *perr = OS_ERR_CREATE_ISR; /* ... can't CREATE from an ISR */ + return ((OS_FLAG_GRP *)0); + } + OS_ENTER_CRITICAL(); + pgrp = OSFlagFreeList; /* Get next free event flag */ + if (pgrp != (OS_FLAG_GRP *)0) { /* See if we have event flag groups available */ + /* Adjust free list */ + OSFlagFreeList = (OS_FLAG_GRP *)OSFlagFreeList->OSFlagWaitList; + pgrp->OSFlagType = OS_EVENT_TYPE_FLAG; /* Set to event flag group type */ + pgrp->OSFlagFlags = flags; /* Set to desired initial value */ + pgrp->OSFlagWaitList = (void *)0; /* Clear list of tasks waiting on flags */ +#if OS_FLAG_NAME_SIZE > 1 + pgrp->OSFlagName[0] = '?'; + pgrp->OSFlagName[1] = OS_ASCII_NUL; +#endif + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + } else { + OS_EXIT_CRITICAL(); + *perr = OS_ERR_FLAG_GRP_DEPLETED; + } + return (pgrp); /* Return pointer to event flag group */ +} + +/*$PAGE*/ +/* +********************************************************************************************************* +* DELETE AN EVENT FLAG GROUP +* +* Description: This function deletes an event flag group and readies all tasks pending on the event flag +* group. +* +* Arguments : pgrp is a pointer to the desired event flag group. +* +* opt determines delete options as follows: +* opt == OS_DEL_NO_PEND Deletes the event flag group ONLY if no task pending +* opt == OS_DEL_ALWAYS Deletes the event flag group even if tasks are +* waiting. In this case, all the tasks pending will be +* readied. +* +* perr is a pointer to an error code that can contain one of the following values: +* OS_ERR_NONE The call was successful and the event flag group was +* deleted +* OS_ERR_DEL_ISR If you attempted to delete the event flag group from +* an ISR +* OS_ERR_FLAG_INVALID_PGRP If 'pgrp' is a NULL pointer. +* OS_ERR_EVENT_TYPE If you didn't pass a pointer to an event flag group +* OS_ERR_INVALID_OPT An invalid option was specified +* OS_ERR_TASK_WAITING One or more tasks were waiting on the event flag +* group. +* +* Returns : pgrp upon error +* (OS_EVENT *)0 if the event flag group was successfully deleted. +* +* Note(s) : 1) This function must be used with care. Tasks that would normally expect the presence of +* the event flag group MUST check the return code of OSFlagAccept() and OSFlagPend(). +* 2) This call can potentially disable interrupts for a long time. The interrupt disable +* time is directly proportional to the number of tasks waiting on the event flag group. +********************************************************************************************************* +*/ + +#if OS_FLAG_DEL_EN > 0 +OS_FLAG_GRP *OSFlagDel (OS_FLAG_GRP *pgrp, INT8U opt, INT8U *perr) +{ + BOOLEAN tasks_waiting; + OS_FLAG_NODE *pnode; + OS_FLAG_GRP *pgrp_return; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + return (pgrp); + } + if (pgrp == (OS_FLAG_GRP *)0) { /* Validate 'pgrp' */ + *perr = OS_ERR_FLAG_INVALID_PGRP; + return (pgrp); + } +#endif + if (OSIntNesting > 0) { /* See if called from ISR ... */ + *perr = OS_ERR_DEL_ISR; /* ... can't DELETE from an ISR */ + return (pgrp); + } + if (pgrp->OSFlagType != OS_EVENT_TYPE_FLAG) { /* Validate event group type */ + *perr = OS_ERR_EVENT_TYPE; + return (pgrp); + } + OS_ENTER_CRITICAL(); + if (pgrp->OSFlagWaitList != (void *)0) { /* See if any tasks waiting on event flags */ + tasks_waiting = OS_TRUE; /* Yes */ + } else { + tasks_waiting = OS_FALSE; /* No */ + } + switch (opt) { + case OS_DEL_NO_PEND: /* Delete group if no task waiting */ + if (tasks_waiting == OS_FALSE) { +#if OS_FLAG_NAME_SIZE > 1 + pgrp->OSFlagName[0] = '?'; /* Unknown name */ + pgrp->OSFlagName[1] = OS_ASCII_NUL; +#endif + pgrp->OSFlagType = OS_EVENT_TYPE_UNUSED; + pgrp->OSFlagWaitList = (void *)OSFlagFreeList; /* Return group to free list */ + pgrp->OSFlagFlags = (OS_FLAGS)0; + OSFlagFreeList = pgrp; + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + pgrp_return = (OS_FLAG_GRP *)0; /* Event Flag Group has been deleted */ + } else { + OS_EXIT_CRITICAL(); + *perr = OS_ERR_TASK_WAITING; + pgrp_return = pgrp; + } + break; + + case OS_DEL_ALWAYS: /* Always delete the event flag group */ + pnode = (OS_FLAG_NODE *)pgrp->OSFlagWaitList; + while (pnode != (OS_FLAG_NODE *)0) { /* Ready ALL tasks waiting for flags */ + (void)OS_FlagTaskRdy(pnode, (OS_FLAGS)0); + pnode = (OS_FLAG_NODE *)pnode->OSFlagNodeNext; + } +#if OS_FLAG_NAME_SIZE > 1 + pgrp->OSFlagName[0] = '?'; /* Unknown name */ + pgrp->OSFlagName[1] = OS_ASCII_NUL; +#endif + pgrp->OSFlagType = OS_EVENT_TYPE_UNUSED; + pgrp->OSFlagWaitList = (void *)OSFlagFreeList;/* Return group to free list */ + pgrp->OSFlagFlags = (OS_FLAGS)0; + OSFlagFreeList = pgrp; + OS_EXIT_CRITICAL(); + if (tasks_waiting == OS_TRUE) { /* Reschedule only if task(s) were waiting */ + OS_Sched(); /* Find highest priority task ready to run */ + } + *perr = OS_ERR_NONE; + pgrp_return = (OS_FLAG_GRP *)0; /* Event Flag Group has been deleted */ + break; + + default: + OS_EXIT_CRITICAL(); + *perr = OS_ERR_INVALID_OPT; + pgrp_return = pgrp; + break; + } + return (pgrp_return); +} +#endif +/*$PAGE*/ +/* +********************************************************************************************************* +* GET THE NAME OF AN EVENT FLAG GROUP +* +* Description: This function is used to obtain the name assigned to an event flag group +* +* Arguments : pgrp is a pointer to the event flag group. +* +* pname is a pointer to an ASCII string that will receive the name of the event flag +* group. The string must be able to hold at least OS_FLAG_NAME_SIZE characters. +* +* perr is a pointer to an error code that can contain one of the following values: +* +* OS_ERR_NONE if the requested task is resumed +* OS_ERR_EVENT_TYPE if 'pevent' is not pointing to an event flag group +* OS_ERR_PNAME_NULL You passed a NULL pointer for 'pname' +* OS_ERR_FLAG_INVALID_PGRP if you passed a NULL pointer for 'pgrp' +* OS_ERR_NAME_GET_ISR if you called this function from an ISR +* +* Returns : The length of the string or 0 if the 'pgrp' is a NULL pointer. +********************************************************************************************************* +*/ + +#if OS_FLAG_NAME_SIZE > 1 +INT8U OSFlagNameGet (OS_FLAG_GRP *pgrp, INT8U *pname, INT8U *perr) +{ + INT8U len; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + return (0); + } + if (pgrp == (OS_FLAG_GRP *)0) { /* Is 'pgrp' a NULL pointer? */ + *perr = OS_ERR_FLAG_INVALID_PGRP; + return (0); + } + if (pname == (INT8U *)0) { /* Is 'pname' a NULL pointer? */ + *perr = OS_ERR_PNAME_NULL; + return (0); + } +#endif + if (OSIntNesting > 0) { /* See if trying to call from an ISR */ + *perr = OS_ERR_NAME_GET_ISR; + return (0); + } + OS_ENTER_CRITICAL(); + if (pgrp->OSFlagType != OS_EVENT_TYPE_FLAG) { + OS_EXIT_CRITICAL(); + *perr = OS_ERR_EVENT_TYPE; + return (0); + } + len = OS_StrCopy(pname, pgrp->OSFlagName); /* Copy name from OS_FLAG_GRP */ + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + return (len); +} +#endif + +/*$PAGE*/ +/* +********************************************************************************************************* +* ASSIGN A NAME TO AN EVENT FLAG GROUP +* +* Description: This function assigns a name to an event flag group. +* +* Arguments : pgrp is a pointer to the event flag group. +* +* pname is a pointer to an ASCII string that will be used as the name of the event flag +* group. The string must be able to hold at least OS_FLAG_NAME_SIZE characters. +* +* perr is a pointer to an error code that can contain one of the following values: +* +* OS_ERR_NONE if the requested task is resumed +* OS_ERR_EVENT_TYPE if 'pevent' is not pointing to an event flag group +* OS_ERR_PNAME_NULL You passed a NULL pointer for 'pname' +* OS_ERR_FLAG_INVALID_PGRP if you passed a NULL pointer for 'pgrp' +* OS_ERR_NAME_SET_ISR if you called this function from an ISR +* +* Returns : None +********************************************************************************************************* +*/ + +#if OS_FLAG_NAME_SIZE > 1 +void OSFlagNameSet (OS_FLAG_GRP *pgrp, INT8U *pname, INT8U *perr) +{ + INT8U len; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + return; + } + if (pgrp == (OS_FLAG_GRP *)0) { /* Is 'pgrp' a NULL pointer? */ + *perr = OS_ERR_FLAG_INVALID_PGRP; + return; + } + if (pname == (INT8U *)0) { /* Is 'pname' a NULL pointer? */ + *perr = OS_ERR_PNAME_NULL; + return; + } +#endif + if (OSIntNesting > 0) { /* See if trying to call from an ISR */ + *perr = OS_ERR_NAME_SET_ISR; + return; + } + OS_ENTER_CRITICAL(); + if (pgrp->OSFlagType != OS_EVENT_TYPE_FLAG) { + OS_EXIT_CRITICAL(); + *perr = OS_ERR_EVENT_TYPE; + return; + } + len = OS_StrLen(pname); /* Can we fit the string in the storage area? */ + if (len > (OS_FLAG_NAME_SIZE - 1)) { /* No */ + OS_EXIT_CRITICAL(); + *perr = OS_ERR_FLAG_NAME_TOO_LONG; + return; + } + (void)OS_StrCopy(pgrp->OSFlagName, pname); /* Yes, copy name from OS_FLAG_GRP */ + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + return; +} +#endif + +/*$PAGE*/ +/* +********************************************************************************************************* +* WAIT ON AN EVENT FLAG GROUP +* +* Description: This function is called to wait for a combination of bits to be set in an event flag +* group. Your application can wait for ANY bit to be set or ALL bits to be set. +* +* Arguments : pgrp is a pointer to the desired event flag group. +* +* flags Is a bit pattern indicating which bit(s) (i.e. flags) you wish to wait for. +* The bits you want are specified by setting the corresponding bits in +* 'flags'. e.g. if your application wants to wait for bits 0 and 1 then +* 'flags' would contain 0x03. +* +* wait_type specifies whether you want ALL bits to be set or ANY of the bits to be set. +* You can specify the following argument: +* +* OS_FLAG_WAIT_CLR_ALL You will wait for ALL bits in 'mask' to be clear (0) +* OS_FLAG_WAIT_SET_ALL You will wait for ALL bits in 'mask' to be set (1) +* OS_FLAG_WAIT_CLR_ANY You will wait for ANY bit in 'mask' to be clear (0) +* OS_FLAG_WAIT_SET_ANY You will wait for ANY bit in 'mask' to be set (1) +* +* NOTE: Add OS_FLAG_CONSUME if you want the event flag to be 'consumed' by +* the call. Example, to wait for any flag in a group AND then clear +* the flags that are present, set 'wait_type' to: +* +* OS_FLAG_WAIT_SET_ANY + OS_FLAG_CONSUME +* +* timeout is an optional timeout (in clock ticks) that your task will wait for the +* desired bit combination. If you specify 0, however, your task will wait +* forever at the specified event flag group or, until a message arrives. +* +* perr is a pointer to an error code and can be: +* OS_ERR_NONE The desired bits have been set within the specified +* 'timeout'. +* OS_ERR_PEND_ISR If you tried to PEND from an ISR +* OS_ERR_FLAG_INVALID_PGRP If 'pgrp' is a NULL pointer. +* OS_ERR_EVENT_TYPE You are not pointing to an event flag group +* OS_ERR_TIMEOUT The bit(s) have not been set in the specified +* 'timeout'. +* OS_ERR_PEND_ABORT The wait on the flag was aborted. +* OS_ERR_FLAG_WAIT_TYPE You didn't specify a proper 'wait_type' argument. +* +* Returns : The flags in the event flag group that made the task ready or, 0 if a timeout or an error +* occurred. +* +* Called from: Task ONLY +* +* Note(s) : 1) IMPORTANT, the behavior of this function has changed from PREVIOUS versions. The +* function NOW returns the flags that were ready INSTEAD of the current state of the +* event flags. +********************************************************************************************************* +*/ + +OS_FLAGS OSFlagPend (OS_FLAG_GRP *pgrp, OS_FLAGS flags, INT8U wait_type, INT16U timeout, INT8U *perr) +{ + OS_FLAG_NODE node; + OS_FLAGS flags_rdy; + INT8U result; + INT8U pend_stat; + BOOLEAN consume; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + return ((OS_FLAGS)0); + } + if (pgrp == (OS_FLAG_GRP *)0) { /* Validate 'pgrp' */ + *perr = OS_ERR_FLAG_INVALID_PGRP; + return ((OS_FLAGS)0); + } +#endif + if (OSIntNesting > 0) { /* See if called from ISR ... */ + *perr = OS_ERR_PEND_ISR; /* ... can't PEND from an ISR */ + return ((OS_FLAGS)0); + } + if (OSLockNesting > 0) { /* See if called with scheduler locked ... */ + *perr = OS_ERR_PEND_LOCKED; /* ... can't PEND when locked */ + return ((OS_FLAGS)0); + } + if (pgrp->OSFlagType != OS_EVENT_TYPE_FLAG) { /* Validate event block type */ + *perr = OS_ERR_EVENT_TYPE; + return ((OS_FLAGS)0); + } + result = (INT8U)(wait_type & OS_FLAG_CONSUME); + if (result != (INT8U)0) { /* See if we need to consume the flags */ + wait_type &= ~(INT8U)OS_FLAG_CONSUME; + consume = OS_TRUE; + } else { + consume = OS_FALSE; + } +/*$PAGE*/ + OS_ENTER_CRITICAL(); + switch (wait_type) { + case OS_FLAG_WAIT_SET_ALL: /* See if all required flags are set */ + flags_rdy = (OS_FLAGS)(pgrp->OSFlagFlags & flags); /* Extract only the bits we want */ + if (flags_rdy == flags) { /* Must match ALL the bits that we want */ + if (consume == OS_TRUE) { /* See if we need to consume the flags */ + pgrp->OSFlagFlags &= ~flags_rdy; /* Clear ONLY the flags that we wanted */ + } + OSTCBCur->OSTCBFlagsRdy = flags_rdy; /* Save flags that were ready */ + OS_EXIT_CRITICAL(); /* Yes, condition met, return to caller */ + *perr = OS_ERR_NONE; + return (flags_rdy); + } else { /* Block task until events occur or timeout */ + OS_FlagBlock(pgrp, &node, flags, wait_type, timeout); + OS_EXIT_CRITICAL(); + } + break; + + case OS_FLAG_WAIT_SET_ANY: + flags_rdy = (OS_FLAGS)(pgrp->OSFlagFlags & flags); /* Extract only the bits we want */ + if (flags_rdy != (OS_FLAGS)0) { /* See if any flag set */ + if (consume == OS_TRUE) { /* See if we need to consume the flags */ + pgrp->OSFlagFlags &= ~flags_rdy; /* Clear ONLY the flags that we got */ + } + OSTCBCur->OSTCBFlagsRdy = flags_rdy; /* Save flags that were ready */ + OS_EXIT_CRITICAL(); /* Yes, condition met, return to caller */ + *perr = OS_ERR_NONE; + return (flags_rdy); + } else { /* Block task until events occur or timeout */ + OS_FlagBlock(pgrp, &node, flags, wait_type, timeout); + OS_EXIT_CRITICAL(); + } + break; + +#if OS_FLAG_WAIT_CLR_EN > 0 + case OS_FLAG_WAIT_CLR_ALL: /* See if all required flags are cleared */ + flags_rdy = (OS_FLAGS)(~pgrp->OSFlagFlags & flags); /* Extract only the bits we want */ + if (flags_rdy == flags) { /* Must match ALL the bits that we want */ + if (consume == OS_TRUE) { /* See if we need to consume the flags */ + pgrp->OSFlagFlags |= flags_rdy; /* Set ONLY the flags that we wanted */ + } + OSTCBCur->OSTCBFlagsRdy = flags_rdy; /* Save flags that were ready */ + OS_EXIT_CRITICAL(); /* Yes, condition met, return to caller */ + *perr = OS_ERR_NONE; + return (flags_rdy); + } else { /* Block task until events occur or timeout */ + OS_FlagBlock(pgrp, &node, flags, wait_type, timeout); + OS_EXIT_CRITICAL(); + } + break; + + case OS_FLAG_WAIT_CLR_ANY: + flags_rdy = (OS_FLAGS)(~pgrp->OSFlagFlags & flags); /* Extract only the bits we want */ + if (flags_rdy != (OS_FLAGS)0) { /* See if any flag cleared */ + if (consume == OS_TRUE) { /* See if we need to consume the flags */ + pgrp->OSFlagFlags |= flags_rdy; /* Set ONLY the flags that we got */ + } + OSTCBCur->OSTCBFlagsRdy = flags_rdy; /* Save flags that were ready */ + OS_EXIT_CRITICAL(); /* Yes, condition met, return to caller */ + *perr = OS_ERR_NONE; + return (flags_rdy); + } else { /* Block task until events occur or timeout */ + OS_FlagBlock(pgrp, &node, flags, wait_type, timeout); + OS_EXIT_CRITICAL(); + } + break; +#endif + + default: + OS_EXIT_CRITICAL(); + flags_rdy = (OS_FLAGS)0; + *perr = OS_ERR_FLAG_WAIT_TYPE; + return (flags_rdy); + } +/*$PAGE*/ + OS_Sched(); /* Find next HPT ready to run */ + OS_ENTER_CRITICAL(); + if (OSTCBCur->OSTCBStatPend != OS_STAT_PEND_OK) { /* Have we timed-out or aborted? */ + pend_stat = OSTCBCur->OSTCBStatPend; + OSTCBCur->OSTCBStatPend = OS_STAT_PEND_OK; + OS_FlagUnlink(&node); + OSTCBCur->OSTCBStat = OS_STAT_RDY; /* Yes, make task ready-to-run */ + OS_EXIT_CRITICAL(); + flags_rdy = (OS_FLAGS)0; + switch (pend_stat) { + case OS_STAT_PEND_ABORT: + *perr = OS_ERR_PEND_ABORT; /* Indicate that we aborted waiting */ + break; + + case OS_STAT_PEND_TO: + default: + *perr = OS_ERR_TIMEOUT; /* Indicate that we timed-out waiting */ + break; + } + return (flags_rdy); + } + flags_rdy = OSTCBCur->OSTCBFlagsRdy; + if (consume == OS_TRUE) { /* See if we need to consume the flags */ + switch (wait_type) { + case OS_FLAG_WAIT_SET_ALL: + case OS_FLAG_WAIT_SET_ANY: /* Clear ONLY the flags we got */ + pgrp->OSFlagFlags &= ~flags_rdy; + break; + +#if OS_FLAG_WAIT_CLR_EN > 0 + case OS_FLAG_WAIT_CLR_ALL: + case OS_FLAG_WAIT_CLR_ANY: /* Set ONLY the flags we got */ + pgrp->OSFlagFlags |= flags_rdy; + break; +#endif + default: + OS_EXIT_CRITICAL(); + *perr = OS_ERR_FLAG_WAIT_TYPE; + return ((OS_FLAGS)0); + } + } + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; /* Event(s) must have occurred */ + return (flags_rdy); +} +/*$PAGE*/ +/* +********************************************************************************************************* +* GET FLAGS WHO CAUSED TASK TO BECOME READY +* +* Description: This function is called to obtain the flags that caused the task to become ready to run. +* In other words, this function allows you to tell "Who done it!". +* +* Arguments : None +* +* Returns : The flags that caused the task to be ready. +* +* Called from: Task ONLY +********************************************************************************************************* +*/ + +OS_FLAGS OSFlagPendGetFlagsRdy (void) +{ + OS_FLAGS flags; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + + OS_ENTER_CRITICAL(); + flags = OSTCBCur->OSTCBFlagsRdy; + OS_EXIT_CRITICAL(); + return (flags); +} + +/*$PAGE*/ +/* +********************************************************************************************************* +* POST EVENT FLAG BIT(S) +* +* Description: This function is called to set or clear some bits in an event flag group. The bits to +* set or clear are specified by a 'bit mask'. +* +* Arguments : pgrp is a pointer to the desired event flag group. +* +* flags If 'opt' (see below) is OS_FLAG_SET, each bit that is set in 'flags' will +* set the corresponding bit in the event flag group. e.g. to set bits 0, 4 +* and 5 you would set 'flags' to: +* +* 0x31 (note, bit 0 is least significant bit) +* +* If 'opt' (see below) is OS_FLAG_CLR, each bit that is set in 'flags' will +* CLEAR the corresponding bit in the event flag group. e.g. to clear bits 0, +* 4 and 5 you would specify 'flags' as: +* +* 0x31 (note, bit 0 is least significant bit) +* +* opt indicates whether the flags will be: +* set (OS_FLAG_SET) or +* cleared (OS_FLAG_CLR) +* +* perr is a pointer to an error code and can be: +* OS_ERR_NONE The call was successfull +* OS_ERR_FLAG_INVALID_PGRP You passed a NULL pointer +* OS_ERR_EVENT_TYPE You are not pointing to an event flag group +* OS_ERR_FLAG_INVALID_OPT You specified an invalid option +* +* Returns : the new value of the event flags bits that are still set. +* +* Called From: Task or ISR +* +* WARNING(s) : 1) The execution time of this function depends on the number of tasks waiting on the event +* flag group. +* 2) The amount of time interrupts are DISABLED depends on the number of tasks waiting on +* the event flag group. +********************************************************************************************************* +*/ +OS_FLAGS OSFlagPost (OS_FLAG_GRP *pgrp, OS_FLAGS flags, INT8U opt, INT8U *perr) +{ + OS_FLAG_NODE *pnode; + BOOLEAN sched; + OS_FLAGS flags_cur; + OS_FLAGS flags_rdy; + BOOLEAN rdy; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + return ((OS_FLAGS)0); + } + if (pgrp == (OS_FLAG_GRP *)0) { /* Validate 'pgrp' */ + *perr = OS_ERR_FLAG_INVALID_PGRP; + return ((OS_FLAGS)0); + } +#endif + if (pgrp->OSFlagType != OS_EVENT_TYPE_FLAG) { /* Make sure we are pointing to an event flag grp */ + *perr = OS_ERR_EVENT_TYPE; + return ((OS_FLAGS)0); + } +/*$PAGE*/ + OS_ENTER_CRITICAL(); + switch (opt) { + case OS_FLAG_CLR: + pgrp->OSFlagFlags &= ~flags; /* Clear the flags specified in the group */ + break; + + case OS_FLAG_SET: + pgrp->OSFlagFlags |= flags; /* Set the flags specified in the group */ + break; + + default: + OS_EXIT_CRITICAL(); /* INVALID option */ + *perr = OS_ERR_FLAG_INVALID_OPT; + return ((OS_FLAGS)0); + } + sched = OS_FALSE; /* Indicate that we don't need rescheduling */ + pnode = (OS_FLAG_NODE *)pgrp->OSFlagWaitList; + while (pnode != (OS_FLAG_NODE *)0) { /* Go through all tasks waiting on event flag(s) */ + switch (pnode->OSFlagNodeWaitType) { + case OS_FLAG_WAIT_SET_ALL: /* See if all req. flags are set for current node */ + flags_rdy = (OS_FLAGS)(pgrp->OSFlagFlags & pnode->OSFlagNodeFlags); + if (flags_rdy == pnode->OSFlagNodeFlags) { + rdy = OS_FlagTaskRdy(pnode, flags_rdy); /* Make task RTR, event(s) Rx'd */ + if (rdy == OS_TRUE) { + sched = OS_TRUE; /* When done we will reschedule */ + } + } + break; + + case OS_FLAG_WAIT_SET_ANY: /* See if any flag set */ + flags_rdy = (OS_FLAGS)(pgrp->OSFlagFlags & pnode->OSFlagNodeFlags); + if (flags_rdy != (OS_FLAGS)0) { + rdy = OS_FlagTaskRdy(pnode, flags_rdy); /* Make task RTR, event(s) Rx'd */ + if (rdy == OS_TRUE) { + sched = OS_TRUE; /* When done we will reschedule */ + } + } + break; + +#if OS_FLAG_WAIT_CLR_EN > 0 + case OS_FLAG_WAIT_CLR_ALL: /* See if all req. flags are set for current node */ + flags_rdy = (OS_FLAGS)(~pgrp->OSFlagFlags & pnode->OSFlagNodeFlags); + if (flags_rdy == pnode->OSFlagNodeFlags) { + rdy = OS_FlagTaskRdy(pnode, flags_rdy); /* Make task RTR, event(s) Rx'd */ + if (rdy == OS_TRUE) { + sched = OS_TRUE; /* When done we will reschedule */ + } + } + break; + + case OS_FLAG_WAIT_CLR_ANY: /* See if any flag set */ + flags_rdy = (OS_FLAGS)(~pgrp->OSFlagFlags & pnode->OSFlagNodeFlags); + if (flags_rdy != (OS_FLAGS)0) { + rdy = OS_FlagTaskRdy(pnode, flags_rdy); /* Make task RTR, event(s) Rx'd */ + if (rdy == OS_TRUE) { + sched = OS_TRUE; /* When done we will reschedule */ + } + } + break; +#endif + default: + OS_EXIT_CRITICAL(); + *perr = OS_ERR_FLAG_WAIT_TYPE; + return ((OS_FLAGS)0); + } + pnode = (OS_FLAG_NODE *)pnode->OSFlagNodeNext; /* Point to next task waiting for event flag(s) */ + } + OS_EXIT_CRITICAL(); + if (sched == OS_TRUE) { + OS_Sched(); + } + OS_ENTER_CRITICAL(); + flags_cur = pgrp->OSFlagFlags; + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + return (flags_cur); +} +/*$PAGE*/ +/* +********************************************************************************************************* +* QUERY EVENT FLAG +* +* Description: This function is used to check the value of the event flag group. +* +* Arguments : pgrp is a pointer to the desired event flag group. +* +* perr is a pointer to an error code returned to the called: +* OS_ERR_NONE The call was successfull +* OS_ERR_FLAG_INVALID_PGRP You passed a NULL pointer +* OS_ERR_EVENT_TYPE You are not pointing to an event flag group +* +* Returns : The current value of the event flag group. +* +* Called From: Task or ISR +********************************************************************************************************* +*/ + +#if OS_FLAG_QUERY_EN > 0 +OS_FLAGS OSFlagQuery (OS_FLAG_GRP *pgrp, INT8U *perr) +{ + OS_FLAGS flags; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + return ((OS_FLAGS)0); + } + if (pgrp == (OS_FLAG_GRP *)0) { /* Validate 'pgrp' */ + *perr = OS_ERR_FLAG_INVALID_PGRP; + return ((OS_FLAGS)0); + } +#endif + if (pgrp->OSFlagType != OS_EVENT_TYPE_FLAG) { /* Validate event block type */ + *perr = OS_ERR_EVENT_TYPE; + return ((OS_FLAGS)0); + } + OS_ENTER_CRITICAL(); + flags = pgrp->OSFlagFlags; + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + return (flags); /* Return the current value of the event flags */ +} +#endif + +/*$PAGE*/ +/* +********************************************************************************************************* +* SUSPEND TASK UNTIL EVENT FLAG(s) RECEIVED OR TIMEOUT OCCURS +* +* Description: This function is internal to uC/OS-II and is used to put a task to sleep until the desired +* event flag bit(s) are set. +* +* Arguments : pgrp is a pointer to the desired event flag group. +* +* pnode is a pointer to a structure which contains data about the task waiting for +* event flag bit(s) to be set. +* +* flags Is a bit pattern indicating which bit(s) (i.e. flags) you wish to check. +* The bits you want are specified by setting the corresponding bits in +* 'flags'. e.g. if your application wants to wait for bits 0 and 1 then +* 'flags' would contain 0x03. +* +* wait_type specifies whether you want ALL bits to be set/cleared or ANY of the bits +* to be set/cleared. +* You can specify the following argument: +* +* OS_FLAG_WAIT_CLR_ALL You will check ALL bits in 'mask' to be clear (0) +* OS_FLAG_WAIT_CLR_ANY You will check ANY bit in 'mask' to be clear (0) +* OS_FLAG_WAIT_SET_ALL You will check ALL bits in 'mask' to be set (1) +* OS_FLAG_WAIT_SET_ANY You will check ANY bit in 'mask' to be set (1) +* +* timeout is the desired amount of time that the task will wait for the event flag +* bit(s) to be set. +* +* Returns : none +* +* Called by : OSFlagPend() OS_FLAG.C +* +* Note(s) : This function is INTERNAL to uC/OS-II and your application should not call it. +********************************************************************************************************* +*/ + +static void OS_FlagBlock (OS_FLAG_GRP *pgrp, OS_FLAG_NODE *pnode, OS_FLAGS flags, INT8U wait_type, INT16U timeout) +{ + OS_FLAG_NODE *pnode_next; + INT8U y; + + + OSTCBCur->OSTCBStat |= OS_STAT_FLAG; + OSTCBCur->OSTCBStatPend = OS_STAT_PEND_OK; + OSTCBCur->OSTCBDly = timeout; /* Store timeout in task's TCB */ +#if OS_TASK_DEL_EN > 0 + OSTCBCur->OSTCBFlagNode = pnode; /* TCB to link to node */ +#endif + pnode->OSFlagNodeFlags = flags; /* Save the flags that we need to wait for */ + pnode->OSFlagNodeWaitType = wait_type; /* Save the type of wait we are doing */ + pnode->OSFlagNodeTCB = (void *)OSTCBCur; /* Link to task's TCB */ + pnode->OSFlagNodeNext = pgrp->OSFlagWaitList; /* Add node at beginning of event flag wait list */ + pnode->OSFlagNodePrev = (void *)0; + pnode->OSFlagNodeFlagGrp = (void *)pgrp; /* Link to Event Flag Group */ + pnode_next = (OS_FLAG_NODE *)pgrp->OSFlagWaitList; + if (pnode_next != (void *)0) { /* Is this the first NODE to insert? */ + pnode_next->OSFlagNodePrev = pnode; /* No, link in doubly linked list */ + } + pgrp->OSFlagWaitList = (void *)pnode; + + y = OSTCBCur->OSTCBY; /* Suspend current task until flag(s) received */ + OSRdyTbl[y] &= ~OSTCBCur->OSTCBBitX; + if (OSRdyTbl[y] == 0x00) { + OSRdyGrp &= ~OSTCBCur->OSTCBBitY; + } +} + +/*$PAGE*/ +/* +********************************************************************************************************* +* INITIALIZE THE EVENT FLAG MODULE +* +* Description: This function is called by uC/OS-II to initialize the event flag module. Your application +* MUST NOT call this function. In other words, this function is internal to uC/OS-II. +* +* Arguments : none +* +* Returns : none +* +* WARNING : You MUST NOT call this function from your code. This is an INTERNAL function to uC/OS-II. +********************************************************************************************************* +*/ + +void OS_FlagInit (void) +{ +#if OS_MAX_FLAGS == 1 + OSFlagFreeList = (OS_FLAG_GRP *)&OSFlagTbl[0]; /* Only ONE event flag group! */ + OSFlagFreeList->OSFlagType = OS_EVENT_TYPE_UNUSED; + OSFlagFreeList->OSFlagWaitList = (void *)0; + OSFlagFreeList->OSFlagFlags = (OS_FLAGS)0; +#if OS_FLAG_NAME_SIZE > 1 + OSFlagFreeList->OSFlagName[0] = '?'; + OSFlagFreeList->OSFlagName[1] = OS_ASCII_NUL; +#endif +#endif + +#if OS_MAX_FLAGS >= 2 + INT16U i; + OS_FLAG_GRP *pgrp1; + OS_FLAG_GRP *pgrp2; + + + OS_MemClr((INT8U *)&OSFlagTbl[0], sizeof(OSFlagTbl)); /* Clear the flag group table */ + pgrp1 = &OSFlagTbl[0]; + pgrp2 = &OSFlagTbl[1]; + for (i = 0; i < (OS_MAX_FLAGS - 1); i++) { /* Init. list of free EVENT FLAGS */ + pgrp1->OSFlagType = OS_EVENT_TYPE_UNUSED; + pgrp1->OSFlagWaitList = (void *)pgrp2; +#if OS_FLAG_NAME_SIZE > 1 + pgrp1->OSFlagName[0] = '?'; /* Unknown name */ + pgrp1->OSFlagName[1] = OS_ASCII_NUL; +#endif + pgrp1++; + pgrp2++; + } + pgrp1->OSFlagType = OS_EVENT_TYPE_UNUSED; + pgrp1->OSFlagWaitList = (void *)0; +#if OS_FLAG_NAME_SIZE > 1 + pgrp1->OSFlagName[0] = '?'; /* Unknown name */ + pgrp1->OSFlagName[1] = OS_ASCII_NUL; +#endif + OSFlagFreeList = &OSFlagTbl[0]; +#endif +} + +/*$PAGE*/ +/* +********************************************************************************************************* +* MAKE TASK READY-TO-RUN, EVENT(s) OCCURRED +* +* Description: This function is internal to uC/OS-II and is used to make a task ready-to-run because the +* desired event flag bits have been set. +* +* Arguments : pnode is a pointer to a structure which contains data about the task waiting for +* event flag bit(s) to be set. +* +* flags_rdy contains the bit pattern of the event flags that cause the task to become +* ready-to-run. +* +* Returns : OS_TRUE If the task has been placed in the ready list and thus needs scheduling +* OS_FALSE The task is still not ready to run and thus scheduling is not necessary +* +* Called by : OSFlagsPost() OS_FLAG.C +* +* Note(s) : 1) This function assumes that interrupts are disabled. +* 2) This function is INTERNAL to uC/OS-II and your application should not call it. +********************************************************************************************************* +*/ + +static BOOLEAN OS_FlagTaskRdy (OS_FLAG_NODE *pnode, OS_FLAGS flags_rdy) +{ + OS_TCB *ptcb; + BOOLEAN sched; + + + ptcb = (OS_TCB *)pnode->OSFlagNodeTCB; /* Point to TCB of waiting task */ + ptcb->OSTCBDly = 0; + ptcb->OSTCBFlagsRdy = flags_rdy; + ptcb->OSTCBStat &= ~(INT8U)OS_STAT_FLAG; + ptcb->OSTCBStatPend = OS_STAT_PEND_OK; + if (ptcb->OSTCBStat == OS_STAT_RDY) { /* Task now ready? */ + OSRdyGrp |= ptcb->OSTCBBitY; /* Put task into ready list */ + OSRdyTbl[ptcb->OSTCBY] |= ptcb->OSTCBBitX; + sched = OS_TRUE; + } else { + sched = OS_FALSE; + } + OS_FlagUnlink(pnode); + return (sched); +} + +/*$PAGE*/ +/* +********************************************************************************************************* +* UNLINK EVENT FLAG NODE FROM WAITING LIST +* +* Description: This function is internal to uC/OS-II and is used to unlink an event flag node from a +* list of tasks waiting for the event flag. +* +* Arguments : pnode is a pointer to a structure which contains data about the task waiting for +* event flag bit(s) to be set. +* +* Returns : none +* +* Called by : OS_FlagTaskRdy() OS_FLAG.C +* OSFlagPend() OS_FLAG.C +* OSTaskDel() OS_TASK.C +* +* Note(s) : 1) This function assumes that interrupts are disabled. +* 2) This function is INTERNAL to uC/OS-II and your application should not call it. +********************************************************************************************************* +*/ + +void OS_FlagUnlink (OS_FLAG_NODE *pnode) +{ +#if OS_TASK_DEL_EN > 0 + OS_TCB *ptcb; +#endif + OS_FLAG_GRP *pgrp; + OS_FLAG_NODE *pnode_prev; + OS_FLAG_NODE *pnode_next; + + + pnode_prev = (OS_FLAG_NODE *)pnode->OSFlagNodePrev; + pnode_next = (OS_FLAG_NODE *)pnode->OSFlagNodeNext; + if (pnode_prev == (OS_FLAG_NODE *)0) { /* Is it first node in wait list? */ + pgrp = (OS_FLAG_GRP *)pnode->OSFlagNodeFlagGrp; + pgrp->OSFlagWaitList = (void *)pnode_next; /* Update list for new 1st node */ + if (pnode_next != (OS_FLAG_NODE *)0) { + pnode_next->OSFlagNodePrev = (OS_FLAG_NODE *)0; /* Link new 1st node PREV to NULL */ + } + } else { /* No, A node somewhere in the list */ + pnode_prev->OSFlagNodeNext = pnode_next; /* Link around the node to unlink */ + if (pnode_next != (OS_FLAG_NODE *)0) { /* Was this the LAST node? */ + pnode_next->OSFlagNodePrev = pnode_prev; /* No, Link around current node */ + } + } +#if OS_TASK_DEL_EN > 0 + ptcb = (OS_TCB *)pnode->OSFlagNodeTCB; + ptcb->OSTCBFlagNode = (OS_FLAG_NODE *)0; +#endif +} +#endif diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/UCOSII/src/os_mbox.c b/MCandWifiTestDE0/Software/MCTest_bsp/UCOSII/src/os_mbox.c new file mode 100644 index 00000000..5ee01dcf --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/UCOSII/src/os_mbox.c @@ -0,0 +1,629 @@ +/* +********************************************************************************************************* +* uC/OS-II +* The Real-Time Kernel +* MESSAGE MAILBOX MANAGEMENT +* +* (c) Copyright 1992-2007, Micrium, Weston, FL +* All Rights Reserved +* +* File : OS_MBOX.C +* By : Jean J. Labrosse +* Version : V2.86 +* +* LICENSING TERMS: +* --------------- +* uC/OS-II is provided in source form for FREE evaluation, for educational use or for peaceful research. +* If you plan on using uC/OS-II in a commercial product you need to contact Micriµm to properly license +* its use in your product. We provide ALL the source code for your convenience and to help you experience +* uC/OS-II. The fact that the source is provided does NOT mean that you can use it without paying a +* licensing fee. +********************************************************************************************************* +*/ + +#ifndef OS_MASTER_FILE +#include +#endif + +#if OS_MBOX_EN > 0 +/* +********************************************************************************************************* +* ACCEPT MESSAGE FROM MAILBOX +* +* Description: This function checks the mailbox to see if a message is available. Unlike OSMboxPend(), +* OSMboxAccept() does not suspend the calling task if a message is not available. +* +* Arguments : pevent is a pointer to the event control block +* +* Returns : != (void *)0 is the message in the mailbox if one is available. The mailbox is cleared +* so the next time OSMboxAccept() is called, the mailbox will be empty. +* == (void *)0 if the mailbox is empty or, +* if 'pevent' is a NULL pointer or, +* if you didn't pass the proper event pointer. +********************************************************************************************************* +*/ + +#if OS_MBOX_ACCEPT_EN > 0 +void *OSMboxAccept (OS_EVENT *pevent) +{ + void *pmsg; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + return ((void *)0); + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_MBOX) { /* Validate event block type */ + return ((void *)0); + } + OS_ENTER_CRITICAL(); + pmsg = pevent->OSEventPtr; + pevent->OSEventPtr = (void *)0; /* Clear the mailbox */ + OS_EXIT_CRITICAL(); + return (pmsg); /* Return the message received (or NULL) */ +} +#endif +/*$PAGE*/ +/* +********************************************************************************************************* +* CREATE A MESSAGE MAILBOX +* +* Description: This function creates a message mailbox if free event control blocks are available. +* +* Arguments : pmsg is a pointer to a message that you wish to deposit in the mailbox. If +* you set this value to the NULL pointer (i.e. (void *)0) then the mailbox +* will be considered empty. +* +* Returns : != (OS_EVENT *)0 is a pointer to the event control clock (OS_EVENT) associated with the +* created mailbox +* == (OS_EVENT *)0 if no event control blocks were available +********************************************************************************************************* +*/ + +OS_EVENT *OSMboxCreate (void *pmsg) +{ + OS_EVENT *pevent; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + + if (OSIntNesting > 0) { /* See if called from ISR ... */ + return ((OS_EVENT *)0); /* ... can't CREATE from an ISR */ + } + OS_ENTER_CRITICAL(); + pevent = OSEventFreeList; /* Get next free event control block */ + if (OSEventFreeList != (OS_EVENT *)0) { /* See if pool of free ECB pool was empty */ + OSEventFreeList = (OS_EVENT *)OSEventFreeList->OSEventPtr; + } + OS_EXIT_CRITICAL(); + if (pevent != (OS_EVENT *)0) { + pevent->OSEventType = OS_EVENT_TYPE_MBOX; + pevent->OSEventCnt = 0; + pevent->OSEventPtr = pmsg; /* Deposit message in event control block */ +#if OS_EVENT_NAME_SIZE > 1 + pevent->OSEventName[0] = '?'; + pevent->OSEventName[1] = OS_ASCII_NUL; +#endif + OS_EventWaitListInit(pevent); + } + return (pevent); /* Return pointer to event control block */ +} +/*$PAGE*/ +/* +********************************************************************************************************* +* DELETE A MAIBOX +* +* Description: This function deletes a mailbox and readies all tasks pending on the mailbox. +* +* Arguments : pevent is a pointer to the event control block associated with the desired +* mailbox. +* +* opt determines delete options as follows: +* opt == OS_DEL_NO_PEND Delete the mailbox ONLY if no task pending +* opt == OS_DEL_ALWAYS Deletes the mailbox even if tasks are waiting. +* In this case, all the tasks pending will be readied. +* +* perr is a pointer to an error code that can contain one of the following values: +* OS_ERR_NONE The call was successful and the mailbox was deleted +* OS_ERR_DEL_ISR If you attempted to delete the mailbox from an ISR +* OS_ERR_INVALID_OPT An invalid option was specified +* OS_ERR_TASK_WAITING One or more tasks were waiting on the mailbox +* OS_ERR_EVENT_TYPE If you didn't pass a pointer to a mailbox +* OS_ERR_PEVENT_NULL If 'pevent' is a NULL pointer. +* +* Returns : pevent upon error +* (OS_EVENT *)0 if the mailbox was successfully deleted. +* +* Note(s) : 1) This function must be used with care. Tasks that would normally expect the presence of +* the mailbox MUST check the return code of OSMboxPend(). +* 2) OSMboxAccept() callers will not know that the intended mailbox has been deleted! +* 3) This call can potentially disable interrupts for a long time. The interrupt disable +* time is directly proportional to the number of tasks waiting on the mailbox. +* 4) Because ALL tasks pending on the mailbox will be readied, you MUST be careful in +* applications where the mailbox is used for mutual exclusion because the resource(s) +* will no longer be guarded by the mailbox. +********************************************************************************************************* +*/ + +#if OS_MBOX_DEL_EN > 0 +OS_EVENT *OSMboxDel (OS_EVENT *pevent, INT8U opt, INT8U *perr) +{ + BOOLEAN tasks_waiting; + OS_EVENT *pevent_return; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + return (pevent); + } + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + *perr = OS_ERR_PEVENT_NULL; + return (pevent); + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_MBOX) { /* Validate event block type */ + *perr = OS_ERR_EVENT_TYPE; + return (pevent); + } + if (OSIntNesting > 0) { /* See if called from ISR ... */ + *perr = OS_ERR_DEL_ISR; /* ... can't DELETE from an ISR */ + return (pevent); + } + OS_ENTER_CRITICAL(); + if (pevent->OSEventGrp != 0) { /* See if any tasks waiting on mailbox */ + tasks_waiting = OS_TRUE; /* Yes */ + } else { + tasks_waiting = OS_FALSE; /* No */ + } + switch (opt) { + case OS_DEL_NO_PEND: /* Delete mailbox only if no task waiting */ + if (tasks_waiting == OS_FALSE) { +#if OS_EVENT_NAME_SIZE > 1 + pevent->OSEventName[0] = '?'; /* Unknown name */ + pevent->OSEventName[1] = OS_ASCII_NUL; +#endif + pevent->OSEventType = OS_EVENT_TYPE_UNUSED; + pevent->OSEventPtr = OSEventFreeList; /* Return Event Control Block to free list */ + pevent->OSEventCnt = 0; + OSEventFreeList = pevent; /* Get next free event control block */ + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + pevent_return = (OS_EVENT *)0; /* Mailbox has been deleted */ + } else { + OS_EXIT_CRITICAL(); + *perr = OS_ERR_TASK_WAITING; + pevent_return = pevent; + } + break; + + case OS_DEL_ALWAYS: /* Always delete the mailbox */ + while (pevent->OSEventGrp != 0) { /* Ready ALL tasks waiting for mailbox */ + (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_MBOX, OS_STAT_PEND_OK); + } +#if OS_EVENT_NAME_SIZE > 1 + pevent->OSEventName[0] = '?'; /* Unknown name */ + pevent->OSEventName[1] = OS_ASCII_NUL; +#endif + pevent->OSEventType = OS_EVENT_TYPE_UNUSED; + pevent->OSEventPtr = OSEventFreeList; /* Return Event Control Block to free list */ + pevent->OSEventCnt = 0; + OSEventFreeList = pevent; /* Get next free event control block */ + OS_EXIT_CRITICAL(); + if (tasks_waiting == OS_TRUE) { /* Reschedule only if task(s) were waiting */ + OS_Sched(); /* Find highest priority task ready to run */ + } + *perr = OS_ERR_NONE; + pevent_return = (OS_EVENT *)0; /* Mailbox has been deleted */ + break; + + default: + OS_EXIT_CRITICAL(); + *perr = OS_ERR_INVALID_OPT; + pevent_return = pevent; + break; + } + return (pevent_return); +} +#endif + +/*$PAGE*/ +/* +********************************************************************************************************* +* PEND ON MAILBOX FOR A MESSAGE +* +* Description: This function waits for a message to be sent to a mailbox +* +* Arguments : pevent is a pointer to the event control block associated with the desired mailbox +* +* timeout is an optional timeout period (in clock ticks). If non-zero, your task will +* wait for a message to arrive at the mailbox up to the amount of time +* specified by this argument. If you specify 0, however, your task will wait +* forever at the specified mailbox or, until a message arrives. +* +* perr is a pointer to where an error message will be deposited. Possible error +* messages are: +* +* OS_ERR_NONE The call was successful and your task received a +* message. +* OS_ERR_TIMEOUT A message was not received within the specified 'timeout'. +* OS_ERR_PEND_ABORT The wait on the mailbox was aborted. +* OS_ERR_EVENT_TYPE Invalid event type +* OS_ERR_PEND_ISR If you called this function from an ISR and the result +* would lead to a suspension. +* OS_ERR_PEVENT_NULL If 'pevent' is a NULL pointer +* OS_ERR_PEND_LOCKED If you called this function when the scheduler is locked +* +* Returns : != (void *)0 is a pointer to the message received +* == (void *)0 if no message was received or, +* if 'pevent' is a NULL pointer or, +* if you didn't pass the proper pointer to the event control block. +********************************************************************************************************* +*/ +/*$PAGE*/ +void *OSMboxPend (OS_EVENT *pevent, INT16U timeout, INT8U *perr) +{ + void *pmsg; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + return ((void *)0); + } + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + *perr = OS_ERR_PEVENT_NULL; + return ((void *)0); + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_MBOX) { /* Validate event block type */ + *perr = OS_ERR_EVENT_TYPE; + return ((void *)0); + } + if (OSIntNesting > 0) { /* See if called from ISR ... */ + *perr = OS_ERR_PEND_ISR; /* ... can't PEND from an ISR */ + return ((void *)0); + } + if (OSLockNesting > 0) { /* See if called with scheduler locked ... */ + *perr = OS_ERR_PEND_LOCKED; /* ... can't PEND when locked */ + return ((void *)0); + } + OS_ENTER_CRITICAL(); + pmsg = pevent->OSEventPtr; + if (pmsg != (void *)0) { /* See if there is already a message */ + pevent->OSEventPtr = (void *)0; /* Clear the mailbox */ + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + return (pmsg); /* Return the message received (or NULL) */ + } + OSTCBCur->OSTCBStat |= OS_STAT_MBOX; /* Message not available, task will pend */ + OSTCBCur->OSTCBStatPend = OS_STAT_PEND_OK; + OSTCBCur->OSTCBDly = timeout; /* Load timeout in TCB */ + OS_EventTaskWait(pevent); /* Suspend task until event or timeout occurs */ + OS_EXIT_CRITICAL(); + OS_Sched(); /* Find next highest priority task ready to run */ + OS_ENTER_CRITICAL(); + switch (OSTCBCur->OSTCBStatPend) { /* See if we timed-out or aborted */ + case OS_STAT_PEND_OK: + pmsg = OSTCBCur->OSTCBMsg; + *perr = OS_ERR_NONE; + break; + + case OS_STAT_PEND_ABORT: + pmsg = (void *)0; + *perr = OS_ERR_PEND_ABORT; /* Indicate that we aborted */ + break; + + case OS_STAT_PEND_TO: + default: + OS_EventTaskRemove(OSTCBCur, pevent); + pmsg = (void *)0; + *perr = OS_ERR_TIMEOUT; /* Indicate that we didn't get event within TO */ + break; + } + OSTCBCur->OSTCBStat = OS_STAT_RDY; /* Set task status to ready */ + OSTCBCur->OSTCBStatPend = OS_STAT_PEND_OK; /* Clear pend status */ + OSTCBCur->OSTCBEventPtr = (OS_EVENT *)0; /* Clear event pointers */ +#if (OS_EVENT_MULTI_EN > 0) + OSTCBCur->OSTCBEventMultiPtr = (OS_EVENT **)0; +#endif + OSTCBCur->OSTCBMsg = (void *)0; /* Clear received message */ + OS_EXIT_CRITICAL(); + return (pmsg); /* Return received message */ +} +/*$PAGE*/ +/* +********************************************************************************************************* +* ABORT WAITING ON A MESSAGE MAILBOX +* +* Description: This function aborts & readies any tasks currently waiting on a mailbox. This function +* should be used to fault-abort the wait on the mailbox, rather than to normally signal +* the mailbox via OSMboxPost() or OSMboxPostOpt(). +* +* Arguments : pevent is a pointer to the event control block associated with the desired mailbox. +* +* opt determines the type of ABORT performed: +* OS_PEND_OPT_NONE ABORT wait for a single task (HPT) waiting on the +* mailbox +* OS_PEND_OPT_BROADCAST ABORT wait for ALL tasks that are waiting on the +* mailbox +* +* perr is a pointer to where an error message will be deposited. Possible error +* messages are: +* +* OS_ERR_NONE No tasks were waiting on the mailbox. +* OS_ERR_PEND_ABORT At least one task waiting on the mailbox was readied +* and informed of the aborted wait; check return value +* for the number of tasks whose wait on the mailbox +* was aborted. +* OS_ERR_EVENT_TYPE If you didn't pass a pointer to a mailbox. +* OS_ERR_PEVENT_NULL If 'pevent' is a NULL pointer. +* +* Returns : == 0 if no tasks were waiting on the mailbox, or upon error. +* > 0 if one or more tasks waiting on the mailbox are now readied and informed. +********************************************************************************************************* +*/ + +#if OS_MBOX_PEND_ABORT_EN > 0 +INT8U OSMboxPendAbort (OS_EVENT *pevent, INT8U opt, INT8U *perr) +{ + INT8U nbr_tasks; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + return (0); + } + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + *perr = OS_ERR_PEVENT_NULL; + return (0); + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_MBOX) { /* Validate event block type */ + *perr = OS_ERR_EVENT_TYPE; + return (0); + } + OS_ENTER_CRITICAL(); + if (pevent->OSEventGrp != 0) { /* See if any task waiting on mailbox? */ + nbr_tasks = 0; + switch (opt) { + case OS_PEND_OPT_BROADCAST: /* Do we need to abort ALL waiting tasks? */ + while (pevent->OSEventGrp != 0) { /* Yes, ready ALL tasks waiting on mailbox */ + (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_MBOX, OS_STAT_PEND_ABORT); + nbr_tasks++; + } + break; + + case OS_PEND_OPT_NONE: + default: /* No, ready HPT waiting on mailbox */ + (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_MBOX, OS_STAT_PEND_ABORT); + nbr_tasks++; + break; + } + OS_EXIT_CRITICAL(); + OS_Sched(); /* Find HPT ready to run */ + *perr = OS_ERR_PEND_ABORT; + return (nbr_tasks); + } + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + return (0); /* No tasks waiting on mailbox */ +} +#endif + +/*$PAGE*/ +/* +********************************************************************************************************* +* POST MESSAGE TO A MAILBOX +* +* Description: This function sends a message to a mailbox +* +* Arguments : pevent is a pointer to the event control block associated with the desired mailbox +* +* pmsg is a pointer to the message to send. You MUST NOT send a NULL pointer. +* +* Returns : OS_ERR_NONE The call was successful and the message was sent +* OS_ERR_MBOX_FULL If the mailbox already contains a message. You can can only send one +* message at a time and thus, the message MUST be consumed before you +* are allowed to send another one. +* OS_ERR_EVENT_TYPE If you are attempting to post to a non mailbox. +* OS_ERR_PEVENT_NULL If 'pevent' is a NULL pointer +* OS_ERR_POST_NULL_PTR If you are attempting to post a NULL pointer +* +* Note(s) : 1) HPT means Highest Priority Task +********************************************************************************************************* +*/ + +#if OS_MBOX_POST_EN > 0 +INT8U OSMboxPost (OS_EVENT *pevent, void *pmsg) +{ +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + return (OS_ERR_PEVENT_NULL); + } + if (pmsg == (void *)0) { /* Make sure we are not posting a NULL pointer */ + return (OS_ERR_POST_NULL_PTR); + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_MBOX) { /* Validate event block type */ + return (OS_ERR_EVENT_TYPE); + } + OS_ENTER_CRITICAL(); + if (pevent->OSEventGrp != 0) { /* See if any task pending on mailbox */ + /* Ready HPT waiting on event */ + (void)OS_EventTaskRdy(pevent, pmsg, OS_STAT_MBOX, OS_STAT_PEND_OK); + OS_EXIT_CRITICAL(); + OS_Sched(); /* Find highest priority task ready to run */ + return (OS_ERR_NONE); + } + if (pevent->OSEventPtr != (void *)0) { /* Make sure mailbox doesn't already have a msg */ + OS_EXIT_CRITICAL(); + return (OS_ERR_MBOX_FULL); + } + pevent->OSEventPtr = pmsg; /* Place message in mailbox */ + OS_EXIT_CRITICAL(); + return (OS_ERR_NONE); +} +#endif + +/*$PAGE*/ +/* +********************************************************************************************************* +* POST MESSAGE TO A MAILBOX +* +* Description: This function sends a message to a mailbox +* +* Arguments : pevent is a pointer to the event control block associated with the desired mailbox +* +* pmsg is a pointer to the message to send. You MUST NOT send a NULL pointer. +* +* opt determines the type of POST performed: +* OS_POST_OPT_NONE POST to a single waiting task +* (Identical to OSMboxPost()) +* OS_POST_OPT_BROADCAST POST to ALL tasks that are waiting on the mailbox +* +* OS_POST_OPT_NO_SCHED Indicates that the scheduler will NOT be invoked +* +* Returns : OS_ERR_NONE The call was successful and the message was sent +* OS_ERR_MBOX_FULL If the mailbox already contains a message. You can can only send one +* message at a time and thus, the message MUST be consumed before you +* are allowed to send another one. +* OS_ERR_EVENT_TYPE If you are attempting to post to a non mailbox. +* OS_ERR_PEVENT_NULL If 'pevent' is a NULL pointer +* OS_ERR_POST_NULL_PTR If you are attempting to post a NULL pointer +* +* Note(s) : 1) HPT means Highest Priority Task +* +* Warning : Interrupts can be disabled for a long time if you do a 'broadcast'. In fact, the +* interrupt disable time is proportional to the number of tasks waiting on the mailbox. +********************************************************************************************************* +*/ + +#if OS_MBOX_POST_OPT_EN > 0 +INT8U OSMboxPostOpt (OS_EVENT *pevent, void *pmsg, INT8U opt) +{ +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + return (OS_ERR_PEVENT_NULL); + } + if (pmsg == (void *)0) { /* Make sure we are not posting a NULL pointer */ + return (OS_ERR_POST_NULL_PTR); + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_MBOX) { /* Validate event block type */ + return (OS_ERR_EVENT_TYPE); + } + OS_ENTER_CRITICAL(); + if (pevent->OSEventGrp != 0) { /* See if any task pending on mailbox */ + if ((opt & OS_POST_OPT_BROADCAST) != 0x00) { /* Do we need to post msg to ALL waiting tasks ? */ + while (pevent->OSEventGrp != 0) { /* Yes, Post to ALL tasks waiting on mailbox */ + (void)OS_EventTaskRdy(pevent, pmsg, OS_STAT_MBOX, OS_STAT_PEND_OK); + } + } else { /* No, Post to HPT waiting on mbox */ + (void)OS_EventTaskRdy(pevent, pmsg, OS_STAT_MBOX, OS_STAT_PEND_OK); + } + OS_EXIT_CRITICAL(); + if ((opt & OS_POST_OPT_NO_SCHED) == 0) { /* See if scheduler needs to be invoked */ + OS_Sched(); /* Find HPT ready to run */ + } + return (OS_ERR_NONE); + } + if (pevent->OSEventPtr != (void *)0) { /* Make sure mailbox doesn't already have a msg */ + OS_EXIT_CRITICAL(); + return (OS_ERR_MBOX_FULL); + } + pevent->OSEventPtr = pmsg; /* Place message in mailbox */ + OS_EXIT_CRITICAL(); + return (OS_ERR_NONE); +} +#endif + +/*$PAGE*/ +/* +********************************************************************************************************* +* QUERY A MESSAGE MAILBOX +* +* Description: This function obtains information about a message mailbox. +* +* Arguments : pevent is a pointer to the event control block associated with the desired mailbox +* +* p_mbox_data is a pointer to a structure that will contain information about the message +* mailbox. +* +* Returns : OS_ERR_NONE The call was successful and the message was sent +* OS_ERR_EVENT_TYPE If you are attempting to obtain data from a non mailbox. +* OS_ERR_PEVENT_NULL If 'pevent' is a NULL pointer +* OS_ERR_PDATA_NULL If 'p_mbox_data' is a NULL pointer +********************************************************************************************************* +*/ + +#if OS_MBOX_QUERY_EN > 0 +INT8U OSMboxQuery (OS_EVENT *pevent, OS_MBOX_DATA *p_mbox_data) +{ + INT8U i; +#if OS_LOWEST_PRIO <= 63 + INT8U *psrc; + INT8U *pdest; +#else + INT16U *psrc; + INT16U *pdest; +#endif +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + return (OS_ERR_PEVENT_NULL); + } + if (p_mbox_data == (OS_MBOX_DATA *)0) { /* Validate 'p_mbox_data' */ + return (OS_ERR_PDATA_NULL); + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_MBOX) { /* Validate event block type */ + return (OS_ERR_EVENT_TYPE); + } + OS_ENTER_CRITICAL(); + p_mbox_data->OSEventGrp = pevent->OSEventGrp; /* Copy message mailbox wait list */ + psrc = &pevent->OSEventTbl[0]; + pdest = &p_mbox_data->OSEventTbl[0]; + for (i = 0; i < OS_EVENT_TBL_SIZE; i++) { + *pdest++ = *psrc++; + } + p_mbox_data->OSMsg = pevent->OSEventPtr; /* Get message from mailbox */ + OS_EXIT_CRITICAL(); + return (OS_ERR_NONE); +} +#endif /* OS_MBOX_QUERY_EN */ +#endif /* OS_MBOX_EN */ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/UCOSII/src/os_mem.c b/MCandWifiTestDE0/Software/MCTest_bsp/UCOSII/src/os_mem.c new file mode 100644 index 00000000..89ec75d1 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/UCOSII/src/os_mem.c @@ -0,0 +1,434 @@ +/* +********************************************************************************************************* +* uC/OS-II +* The Real-Time Kernel +* MEMORY MANAGEMENT +* +* (c) Copyright 1992-2007, Micrium, Weston, FL +* All Rights Reserved +* +* File : OS_MEM.C +* By : Jean J. Labrosse +* Version : V2.86 +* +* LICENSING TERMS: +* --------------- +* uC/OS-II is provided in source form for FREE evaluation, for educational use or for peaceful research. +* If you plan on using uC/OS-II in a commercial product you need to contact Micriµm to properly license +* its use in your product. We provide ALL the source code for your convenience and to help you experience +* uC/OS-II. The fact that the source is provided does NOT mean that you can use it without paying a +* licensing fee. +********************************************************************************************************* +*/ + +#ifndef OS_MASTER_FILE +#include +#endif + +#if (OS_MEM_EN > 0) && (OS_MAX_MEM_PART > 0) +/* +********************************************************************************************************* +* CREATE A MEMORY PARTITION +* +* Description : Create a fixed-sized memory partition that will be managed by uC/OS-II. +* +* Arguments : addr is the starting address of the memory partition +* +* nblks is the number of memory blocks to create from the partition. +* +* blksize is the size (in bytes) of each block in the memory partition. +* +* perr is a pointer to a variable containing an error message which will be set by +* this function to either: +* +* OS_ERR_NONE if the memory partition has been created correctly. +* OS_ERR_MEM_INVALID_ADDR if you are specifying an invalid address for the memory +* storage of the partition or, the block does not align +* on a pointer boundary +* OS_ERR_MEM_INVALID_PART no free partitions available +* OS_ERR_MEM_INVALID_BLKS user specified an invalid number of blocks (must be >= 2) +* OS_ERR_MEM_INVALID_SIZE user specified an invalid block size +* - must be greater than the size of a pointer +* - must be able to hold an integral number of pointers +* Returns : != (OS_MEM *)0 is the partition was created +* == (OS_MEM *)0 if the partition was not created because of invalid arguments or, no +* free partition is available. +********************************************************************************************************* +*/ + +OS_MEM *OSMemCreate (void *addr, INT32U nblks, INT32U blksize, INT8U *perr) +{ + OS_MEM *pmem; + INT8U *pblk; + void **plink; + INT32U i; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + return ((OS_MEM *)0); + } + if (addr == (void *)0) { /* Must pass a valid address for the memory part.*/ + *perr = OS_ERR_MEM_INVALID_ADDR; + return ((OS_MEM *)0); + } + if (((INT32U)addr & (sizeof(void *) - 1)) != 0){ /* Must be pointer size aligned */ + *perr = OS_ERR_MEM_INVALID_ADDR; + return ((OS_MEM *)0); + } + if (nblks < 2) { /* Must have at least 2 blocks per partition */ + *perr = OS_ERR_MEM_INVALID_BLKS; + return ((OS_MEM *)0); + } + if (blksize < sizeof(void *)) { /* Must contain space for at least a pointer */ + *perr = OS_ERR_MEM_INVALID_SIZE; + return ((OS_MEM *)0); + } +#endif + OS_ENTER_CRITICAL(); + pmem = OSMemFreeList; /* Get next free memory partition */ + if (OSMemFreeList != (OS_MEM *)0) { /* See if pool of free partitions was empty */ + OSMemFreeList = (OS_MEM *)OSMemFreeList->OSMemFreeList; + } + OS_EXIT_CRITICAL(); + if (pmem == (OS_MEM *)0) { /* See if we have a memory partition */ + *perr = OS_ERR_MEM_INVALID_PART; + return ((OS_MEM *)0); + } + plink = (void **)addr; /* Create linked list of free memory blocks */ + pblk = (INT8U *)((INT32U)addr + blksize); + for (i = 0; i < (nblks - 1); i++) { + *plink = (void *)pblk; /* Save pointer to NEXT block in CURRENT block */ + plink = (void **)pblk; /* Position to NEXT block */ + pblk = (INT8U *)((INT32U)pblk + blksize); /* Point to the FOLLOWING block */ + } + *plink = (void *)0; /* Last memory block points to NULL */ + pmem->OSMemAddr = addr; /* Store start address of memory partition */ + pmem->OSMemFreeList = addr; /* Initialize pointer to pool of free blocks */ + pmem->OSMemNFree = nblks; /* Store number of free blocks in MCB */ + pmem->OSMemNBlks = nblks; + pmem->OSMemBlkSize = blksize; /* Store block size of each memory blocks */ + *perr = OS_ERR_NONE; + return (pmem); +} +/*$PAGE*/ +/* +********************************************************************************************************* +* GET A MEMORY BLOCK +* +* Description : Get a memory block from a partition +* +* Arguments : pmem is a pointer to the memory partition control block +* +* perr is a pointer to a variable containing an error message which will be set by this +* function to either: +* +* OS_ERR_NONE if the memory partition has been created correctly. +* OS_ERR_MEM_NO_FREE_BLKS if there are no more free memory blocks to allocate to caller +* OS_ERR_MEM_INVALID_PMEM if you passed a NULL pointer for 'pmem' +* +* Returns : A pointer to a memory block if no error is detected +* A pointer to NULL if an error is detected +********************************************************************************************************* +*/ + +void *OSMemGet (OS_MEM *pmem, INT8U *perr) +{ + void *pblk; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + return ((void *)0); + } + if (pmem == (OS_MEM *)0) { /* Must point to a valid memory partition */ + *perr = OS_ERR_MEM_INVALID_PMEM; + return ((void *)0); + } +#endif + OS_ENTER_CRITICAL(); + if (pmem->OSMemNFree > 0) { /* See if there are any free memory blocks */ + pblk = pmem->OSMemFreeList; /* Yes, point to next free memory block */ + pmem->OSMemFreeList = *(void **)pblk; /* Adjust pointer to new free list */ + pmem->OSMemNFree--; /* One less memory block in this partition */ + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; /* No error */ + return (pblk); /* Return memory block to caller */ + } + OS_EXIT_CRITICAL(); + *perr = OS_ERR_MEM_NO_FREE_BLKS; /* No, Notify caller of empty memory partition */ + return ((void *)0); /* Return NULL pointer to caller */ +} +/*$PAGE*/ +/* +********************************************************************************************************* +* GET THE NAME OF A MEMORY PARTITION +* +* Description: This function is used to obtain the name assigned to a memory partition. +* +* Arguments : pmem is a pointer to the memory partition +* +* pname is a pointer to an ASCII string that will receive the name of the memory partition. +* +* perr is a pointer to an error code that can contain one of the following values: +* +* OS_ERR_NONE if the name was copied to 'pname' +* OS_ERR_MEM_INVALID_PMEM if you passed a NULL pointer for 'pmem' +* OS_ERR_PNAME_NULL You passed a NULL pointer for 'pname' +* OS_ERR_NAME_GET_ISR You called this function from an ISR +* +* Returns : The length of the string or 0 if 'pmem' is a NULL pointer. +********************************************************************************************************* +*/ + +#if OS_MEM_NAME_SIZE > 1 +INT8U OSMemNameGet (OS_MEM *pmem, INT8U *pname, INT8U *perr) +{ + INT8U len; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + return (0); + } + if (pmem == (OS_MEM *)0) { /* Is 'pmem' a NULL pointer? */ + *perr = OS_ERR_MEM_INVALID_PMEM; + return (0); + } + if (pname == (INT8U *)0) { /* Is 'pname' a NULL pointer? */ + *perr = OS_ERR_PNAME_NULL; + return (0); + } +#endif + if (OSIntNesting > 0) { /* See if trying to call from an ISR */ + *perr = OS_ERR_NAME_GET_ISR; + return (0); + } + OS_ENTER_CRITICAL(); + len = OS_StrCopy(pname, pmem->OSMemName); /* Copy name from OS_MEM */ + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + return (len); +} +#endif + +/*$PAGE*/ +/* +********************************************************************************************************* +* ASSIGN A NAME TO A MEMORY PARTITION +* +* Description: This function assigns a name to a memory partition. +* +* Arguments : pmem is a pointer to the memory partition +* +* pname is a pointer to an ASCII string that contains the name of the memory partition. +* +* perr is a pointer to an error code that can contain one of the following values: +* +* OS_ERR_NONE if the name was copied to 'pname' +* OS_ERR_MEM_INVALID_PMEM if you passed a NULL pointer for 'pmem' +* OS_ERR_PNAME_NULL You passed a NULL pointer for 'pname' +* OS_ERR_MEM_NAME_TOO_LONG if the name doesn't fit in the storage area +* OS_ERR_NAME_SET_ISR if you called this function from an ISR +* +* Returns : None +********************************************************************************************************* +*/ + +#if OS_MEM_NAME_SIZE > 1 +void OSMemNameSet (OS_MEM *pmem, INT8U *pname, INT8U *perr) +{ + INT8U len; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + return; + } + if (pmem == (OS_MEM *)0) { /* Is 'pmem' a NULL pointer? */ + *perr = OS_ERR_MEM_INVALID_PMEM; + return; + } + if (pname == (INT8U *)0) { /* Is 'pname' a NULL pointer? */ + *perr = OS_ERR_PNAME_NULL; + return; + } +#endif + if (OSIntNesting > 0) { /* See if trying to call from an ISR */ + *perr = OS_ERR_NAME_SET_ISR; + return; + } + OS_ENTER_CRITICAL(); + len = OS_StrLen(pname); /* Can we fit the string in the storage area? */ + if (len > (OS_MEM_NAME_SIZE - 1)) { /* No */ + OS_EXIT_CRITICAL(); + *perr = OS_ERR_MEM_NAME_TOO_LONG; + return; + } + (void)OS_StrCopy(pmem->OSMemName, pname); /* Yes, copy name to the memory partition header */ + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; +} +#endif + +/*$PAGE*/ +/* +********************************************************************************************************* +* RELEASE A MEMORY BLOCK +* +* Description : Returns a memory block to a partition +* +* Arguments : pmem is a pointer to the memory partition control block +* +* pblk is a pointer to the memory block being released. +* +* Returns : OS_ERR_NONE if the memory block was inserted into the partition +* OS_ERR_MEM_FULL if you are returning a memory block to an already FULL memory +* partition (You freed more blocks than you allocated!) +* OS_ERR_MEM_INVALID_PMEM if you passed a NULL pointer for 'pmem' +* OS_ERR_MEM_INVALID_PBLK if you passed a NULL pointer for the block to release. +********************************************************************************************************* +*/ + +INT8U OSMemPut (OS_MEM *pmem, void *pblk) +{ +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (pmem == (OS_MEM *)0) { /* Must point to a valid memory partition */ + return (OS_ERR_MEM_INVALID_PMEM); + } + if (pblk == (void *)0) { /* Must release a valid block */ + return (OS_ERR_MEM_INVALID_PBLK); + } +#endif + OS_ENTER_CRITICAL(); + if (pmem->OSMemNFree >= pmem->OSMemNBlks) { /* Make sure all blocks not already returned */ + OS_EXIT_CRITICAL(); + return (OS_ERR_MEM_FULL); + } + *(void **)pblk = pmem->OSMemFreeList; /* Insert released block into free block list */ + pmem->OSMemFreeList = pblk; + pmem->OSMemNFree++; /* One more memory block in this partition */ + OS_EXIT_CRITICAL(); + return (OS_ERR_NONE); /* Notify caller that memory block was released */ +} +/*$PAGE*/ +/* +********************************************************************************************************* +* QUERY MEMORY PARTITION +* +* Description : This function is used to determine the number of free memory blocks and the number of +* used memory blocks from a memory partition. +* +* Arguments : pmem is a pointer to the memory partition control block +* +* p_mem_data is a pointer to a structure that will contain information about the memory +* partition. +* +* Returns : OS_ERR_NONE if no errors were found. +* OS_ERR_MEM_INVALID_PMEM if you passed a NULL pointer for 'pmem' +* OS_ERR_MEM_INVALID_PDATA if you passed a NULL pointer to the data recipient. +********************************************************************************************************* +*/ + +#if OS_MEM_QUERY_EN > 0 +INT8U OSMemQuery (OS_MEM *pmem, OS_MEM_DATA *p_mem_data) +{ +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (pmem == (OS_MEM *)0) { /* Must point to a valid memory partition */ + return (OS_ERR_MEM_INVALID_PMEM); + } + if (p_mem_data == (OS_MEM_DATA *)0) { /* Must release a valid storage area for the data */ + return (OS_ERR_MEM_INVALID_PDATA); + } +#endif + OS_ENTER_CRITICAL(); + p_mem_data->OSAddr = pmem->OSMemAddr; + p_mem_data->OSFreeList = pmem->OSMemFreeList; + p_mem_data->OSBlkSize = pmem->OSMemBlkSize; + p_mem_data->OSNBlks = pmem->OSMemNBlks; + p_mem_data->OSNFree = pmem->OSMemNFree; + OS_EXIT_CRITICAL(); + p_mem_data->OSNUsed = p_mem_data->OSNBlks - p_mem_data->OSNFree; + return (OS_ERR_NONE); +} +#endif /* OS_MEM_QUERY_EN */ +/*$PAGE*/ +/* +********************************************************************************************************* +* INITIALIZE MEMORY PARTITION MANAGER +* +* Description : This function is called by uC/OS-II to initialize the memory partition manager. Your +* application MUST NOT call this function. +* +* Arguments : none +* +* Returns : none +* +* Note(s) : This function is INTERNAL to uC/OS-II and your application should not call it. +********************************************************************************************************* +*/ + +void OS_MemInit (void) +{ +#if OS_MAX_MEM_PART == 1 + OS_MemClr((INT8U *)&OSMemTbl[0], sizeof(OSMemTbl)); /* Clear the memory partition table */ + OSMemFreeList = (OS_MEM *)&OSMemTbl[0]; /* Point to beginning of free list */ +#if OS_MEM_NAME_SIZE > 1 + OSMemFreeList->OSMemName[0] = '?'; /* Unknown name */ + OSMemFreeList->OSMemName[1] = OS_ASCII_NUL; +#endif +#endif + +#if OS_MAX_MEM_PART >= 2 + OS_MEM *pmem; + INT16U i; + + + OS_MemClr((INT8U *)&OSMemTbl[0], sizeof(OSMemTbl)); /* Clear the memory partition table */ + pmem = &OSMemTbl[0]; /* Point to memory control block (MCB) */ + for (i = 0; i < (OS_MAX_MEM_PART - 1); i++) { /* Init. list of free memory partitions */ + pmem->OSMemFreeList = (void *)&OSMemTbl[i+1]; /* Chain list of free partitions */ +#if OS_MEM_NAME_SIZE > 1 + pmem->OSMemName[0] = '?'; /* Unknown name */ + pmem->OSMemName[1] = OS_ASCII_NUL; +#endif + pmem++; + } + pmem->OSMemFreeList = (void *)0; /* Initialize last node */ +#if OS_MEM_NAME_SIZE > 1 + pmem->OSMemName[0] = '?'; /* Unknown name */ + pmem->OSMemName[1] = OS_ASCII_NUL; +#endif + + OSMemFreeList = &OSMemTbl[0]; /* Point to beginning of free list */ +#endif +} +#endif /* OS_MEM_EN */ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/UCOSII/src/os_mutex.c b/MCandWifiTestDE0/Software/MCTest_bsp/UCOSII/src/os_mutex.c new file mode 100644 index 00000000..180cdfcf --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/UCOSII/src/os_mutex.c @@ -0,0 +1,715 @@ +/* +********************************************************************************************************* +* uC/OS-II +* The Real-Time Kernel +* MUTUAL EXCLUSION SEMAPHORE MANAGEMENT +* +* (c) Copyright 1992-2007, Micrium, Weston, FL +* All Rights Reserved +* +* File : OS_MUTEX.C +* By : Jean J. Labrosse +* Version : V2.86 +* +* LICENSING TERMS: +* --------------- +* uC/OS-II is provided in source form for FREE evaluation, for educational use or for peaceful research. +* If you plan on using uC/OS-II in a commercial product you need to contact Micriµm to properly license +* its use in your product. We provide ALL the source code for your convenience and to help you experience +* uC/OS-II. The fact that the source is provided does NOT mean that you can use it without paying a +* licensing fee. +********************************************************************************************************* +*/ + +#ifndef OS_MASTER_FILE +#include +#endif + + +#if OS_MUTEX_EN > 0 +/* +********************************************************************************************************* +* LOCAL CONSTANTS +********************************************************************************************************* +*/ + +#define OS_MUTEX_KEEP_LOWER_8 ((INT16U)0x00FFu) +#define OS_MUTEX_KEEP_UPPER_8 ((INT16U)0xFF00u) + +#define OS_MUTEX_AVAILABLE ((INT16U)0x00FFu) + +/* +********************************************************************************************************* +* LOCAL CONSTANTS +********************************************************************************************************* +*/ + +static void OSMutex_RdyAtPrio(OS_TCB *ptcb, INT8U prio); + +/*$PAGE*/ +/* +********************************************************************************************************* +* ACCEPT MUTUAL EXCLUSION SEMAPHORE +* +* Description: This function checks the mutual exclusion semaphore to see if a resource is available. +* Unlike OSMutexPend(), OSMutexAccept() does not suspend the calling task if the resource is +* not available or the event did not occur. +* +* Arguments : pevent is a pointer to the event control block +* +* perr is a pointer to an error code which will be returned to your application: +* OS_ERR_NONE if the call was successful. +* OS_ERR_EVENT_TYPE if 'pevent' is not a pointer to a mutex +* OS_ERR_PEVENT_NULL 'pevent' is a NULL pointer +* OS_ERR_PEND_ISR if you called this function from an ISR +* OS_ERR_PIP_LOWER If the priority of the task that owns the Mutex is +* HIGHER (i.e. a lower number) than the PIP. This error +* indicates that you did not set the PIP higher (lower +* number) than ALL the tasks that compete for the Mutex. +* Unfortunately, this is something that could not be +* detected when the Mutex is created because we don't know +* what tasks will be using the Mutex. +* +* Returns : == OS_TRUE if the resource is available, the mutual exclusion semaphore is acquired +* == OS_FALSE a) if the resource is not available +* b) you didn't pass a pointer to a mutual exclusion semaphore +* c) you called this function from an ISR +* +* Warning(s) : This function CANNOT be called from an ISR because mutual exclusion semaphores are +* intended to be used by tasks only. +********************************************************************************************************* +*/ + +#if OS_MUTEX_ACCEPT_EN > 0 +BOOLEAN OSMutexAccept (OS_EVENT *pevent, INT8U *perr) +{ + INT8U pip; /* Priority Inheritance Priority (PIP) */ +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + return (OS_FALSE); + } + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + *perr = OS_ERR_PEVENT_NULL; + return (OS_FALSE); + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_MUTEX) { /* Validate event block type */ + *perr = OS_ERR_EVENT_TYPE; + return (OS_FALSE); + } + if (OSIntNesting > 0) { /* Make sure it's not called from an ISR */ + *perr = OS_ERR_PEND_ISR; + return (OS_FALSE); + } + OS_ENTER_CRITICAL(); /* Get value (0 or 1) of Mutex */ + pip = (INT8U)(pevent->OSEventCnt >> 8); /* Get PIP from mutex */ + if ((pevent->OSEventCnt & OS_MUTEX_KEEP_LOWER_8) == OS_MUTEX_AVAILABLE) { + pevent->OSEventCnt &= OS_MUTEX_KEEP_UPPER_8; /* Mask off LSByte (Acquire Mutex) */ + pevent->OSEventCnt |= OSTCBCur->OSTCBPrio; /* Save current task priority in LSByte */ + pevent->OSEventPtr = (void *)OSTCBCur; /* Link TCB of task owning Mutex */ + if (OSTCBCur->OSTCBPrio <= pip) { /* PIP 'must' have a SMALLER prio ... */ + OS_EXIT_CRITICAL(); /* ... than current task! */ + *perr = OS_ERR_PIP_LOWER; + } else { + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + } + return (OS_TRUE); + } + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + return (OS_FALSE); +} +#endif + +/*$PAGE*/ +/* +********************************************************************************************************* +* CREATE A MUTUAL EXCLUSION SEMAPHORE +* +* Description: This function creates a mutual exclusion semaphore. +* +* Arguments : prio is the priority to use when accessing the mutual exclusion semaphore. In +* other words, when the semaphore is acquired and a higher priority task +* attempts to obtain the semaphore then the priority of the task owning the +* semaphore is raised to this priority. It is assumed that you will specify +* a priority that is LOWER in value than ANY of the tasks competing for the +* mutex. +* +* perr is a pointer to an error code which will be returned to your application: +* OS_ERR_NONE if the call was successful. +* OS_ERR_CREATE_ISR if you attempted to create a MUTEX from an ISR +* OS_ERR_PRIO_EXIST if a task at the priority inheritance priority +* already exist. +* OS_ERR_PEVENT_NULL No more event control blocks available. +* OS_ERR_PRIO_INVALID if the priority you specify is higher that the +* maximum allowed (i.e. > OS_LOWEST_PRIO) +* +* Returns : != (void *)0 is a pointer to the event control clock (OS_EVENT) associated with the +* created mutex. +* == (void *)0 if an error is detected. +* +* Note(s) : 1) The LEAST significant 8 bits of '.OSEventCnt' are used to hold the priority number +* of the task owning the mutex or 0xFF if no task owns the mutex. +* +* 2) The MOST significant 8 bits of '.OSEventCnt' are used to hold the priority number +* to use to reduce priority inversion. +********************************************************************************************************* +*/ + +OS_EVENT *OSMutexCreate (INT8U prio, INT8U *perr) +{ + OS_EVENT *pevent; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + return ((OS_EVENT *)0); + } + if (prio >= OS_LOWEST_PRIO) { /* Validate PIP */ + *perr = OS_ERR_PRIO_INVALID; + return ((OS_EVENT *)0); + } +#endif + if (OSIntNesting > 0) { /* See if called from ISR ... */ + *perr = OS_ERR_CREATE_ISR; /* ... can't CREATE mutex from an ISR */ + return ((OS_EVENT *)0); + } + OS_ENTER_CRITICAL(); + if (OSTCBPrioTbl[prio] != (OS_TCB *)0) { /* Mutex priority must not already exist */ + OS_EXIT_CRITICAL(); /* Task already exist at priority ... */ + *perr = OS_ERR_PRIO_EXIST; /* ... inheritance priority */ + return ((OS_EVENT *)0); + } + OSTCBPrioTbl[prio] = OS_TCB_RESERVED; /* Reserve the table entry */ + pevent = OSEventFreeList; /* Get next free event control block */ + if (pevent == (OS_EVENT *)0) { /* See if an ECB was available */ + OSTCBPrioTbl[prio] = (OS_TCB *)0; /* No, Release the table entry */ + OS_EXIT_CRITICAL(); + *perr = OS_ERR_PEVENT_NULL; /* No more event control blocks */ + return (pevent); + } + OSEventFreeList = (OS_EVENT *)OSEventFreeList->OSEventPtr; /* Adjust the free list */ + OS_EXIT_CRITICAL(); + pevent->OSEventType = OS_EVENT_TYPE_MUTEX; + pevent->OSEventCnt = (INT16U)((INT16U)prio << 8) | OS_MUTEX_AVAILABLE; /* Resource is avail. */ + pevent->OSEventPtr = (void *)0; /* No task owning the mutex */ +#if OS_EVENT_NAME_SIZE > 1 + pevent->OSEventName[0] = '?'; + pevent->OSEventName[1] = OS_ASCII_NUL; +#endif + OS_EventWaitListInit(pevent); + *perr = OS_ERR_NONE; + return (pevent); +} + +/*$PAGE*/ +/* +********************************************************************************************************* +* DELETE A MUTEX +* +* Description: This function deletes a mutual exclusion semaphore and readies all tasks pending on the it. +* +* Arguments : pevent is a pointer to the event control block associated with the desired mutex. +* +* opt determines delete options as follows: +* opt == OS_DEL_NO_PEND Delete mutex ONLY if no task pending +* opt == OS_DEL_ALWAYS Deletes the mutex even if tasks are waiting. +* In this case, all the tasks pending will be readied. +* +* perr is a pointer to an error code that can contain one of the following values: +* OS_ERR_NONE The call was successful and the mutex was deleted +* OS_ERR_DEL_ISR If you attempted to delete the MUTEX from an ISR +* OS_ERR_INVALID_OPT An invalid option was specified +* OS_ERR_TASK_WAITING One or more tasks were waiting on the mutex +* OS_ERR_EVENT_TYPE If you didn't pass a pointer to a mutex +* OS_ERR_PEVENT_NULL If 'pevent' is a NULL pointer. +* +* Returns : pevent upon error +* (OS_EVENT *)0 if the mutex was successfully deleted. +* +* Note(s) : 1) This function must be used with care. Tasks that would normally expect the presence of +* the mutex MUST check the return code of OSMutexPend(). +* +* 2) This call can potentially disable interrupts for a long time. The interrupt disable +* time is directly proportional to the number of tasks waiting on the mutex. +* +* 3) Because ALL tasks pending on the mutex will be readied, you MUST be careful because the +* resource(s) will no longer be guarded by the mutex. +* +* 4) IMPORTANT: In the 'OS_DEL_ALWAYS' case, we assume that the owner of the Mutex (if there +* is one) is ready-to-run and is thus NOT pending on another kernel object or +* has delayed itself. In other words, if a task owns the mutex being deleted, +* that task will be made ready-to-run at its original priority. +********************************************************************************************************* +*/ + +#if OS_MUTEX_DEL_EN +OS_EVENT *OSMutexDel (OS_EVENT *pevent, INT8U opt, INT8U *perr) +{ + BOOLEAN tasks_waiting; + OS_EVENT *pevent_return; + INT8U pip; /* Priority inheritance priority */ + INT8U prio; + OS_TCB *ptcb; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + return (pevent); + } + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + *perr = OS_ERR_PEVENT_NULL; + return (pevent); + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_MUTEX) { /* Validate event block type */ + *perr = OS_ERR_EVENT_TYPE; + return (pevent); + } + if (OSIntNesting > 0) { /* See if called from ISR ... */ + *perr = OS_ERR_DEL_ISR; /* ... can't DELETE from an ISR */ + return (pevent); + } + OS_ENTER_CRITICAL(); + if (pevent->OSEventGrp != 0) { /* See if any tasks waiting on mutex */ + tasks_waiting = OS_TRUE; /* Yes */ + } else { + tasks_waiting = OS_FALSE; /* No */ + } + switch (opt) { + case OS_DEL_NO_PEND: /* DELETE MUTEX ONLY IF NO TASK WAITING --- */ + if (tasks_waiting == OS_FALSE) { +#if OS_EVENT_NAME_SIZE > 1 + pevent->OSEventName[0] = '?'; /* Unknown name */ + pevent->OSEventName[1] = OS_ASCII_NUL; +#endif + pip = (INT8U)(pevent->OSEventCnt >> 8); + OSTCBPrioTbl[pip] = (OS_TCB *)0; /* Free up the PIP */ + pevent->OSEventType = OS_EVENT_TYPE_UNUSED; + pevent->OSEventPtr = OSEventFreeList; /* Return Event Control Block to free list */ + pevent->OSEventCnt = 0; + OSEventFreeList = pevent; + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + pevent_return = (OS_EVENT *)0; /* Mutex has been deleted */ + } else { + OS_EXIT_CRITICAL(); + *perr = OS_ERR_TASK_WAITING; + pevent_return = pevent; + } + break; + + case OS_DEL_ALWAYS: /* ALWAYS DELETE THE MUTEX ---------------- */ + pip = (INT8U)(pevent->OSEventCnt >> 8); /* Get PIP of mutex */ + prio = (INT8U)(pevent->OSEventCnt & OS_MUTEX_KEEP_LOWER_8); /* Get owner's original prio */ + ptcb = (OS_TCB *)pevent->OSEventPtr; + if (ptcb != (OS_TCB *)0) { /* See if any task owns the mutex */ + if (ptcb->OSTCBPrio == pip) { /* See if original prio was changed */ + OSMutex_RdyAtPrio(ptcb, prio); /* Yes, Restore the task's original prio */ + } + } + while (pevent->OSEventGrp != 0) { /* Ready ALL tasks waiting for mutex */ + (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_MUTEX, OS_STAT_PEND_OK); + } +#if OS_EVENT_NAME_SIZE > 1 + pevent->OSEventName[0] = '?'; /* Unknown name */ + pevent->OSEventName[1] = OS_ASCII_NUL; +#endif + pip = (INT8U)(pevent->OSEventCnt >> 8); + OSTCBPrioTbl[pip] = (OS_TCB *)0; /* Free up the PIP */ + pevent->OSEventType = OS_EVENT_TYPE_UNUSED; + pevent->OSEventPtr = OSEventFreeList; /* Return Event Control Block to free list */ + pevent->OSEventCnt = 0; + OSEventFreeList = pevent; /* Get next free event control block */ + OS_EXIT_CRITICAL(); + if (tasks_waiting == OS_TRUE) { /* Reschedule only if task(s) were waiting */ + OS_Sched(); /* Find highest priority task ready to run */ + } + *perr = OS_ERR_NONE; + pevent_return = (OS_EVENT *)0; /* Mutex has been deleted */ + break; + + default: + OS_EXIT_CRITICAL(); + *perr = OS_ERR_INVALID_OPT; + pevent_return = pevent; + break; + } + return (pevent_return); +} +#endif + +/*$PAGE*/ +/* +********************************************************************************************************* +* PEND ON MUTUAL EXCLUSION SEMAPHORE +* +* Description: This function waits for a mutual exclusion semaphore. +* +* Arguments : pevent is a pointer to the event control block associated with the desired +* mutex. +* +* timeout is an optional timeout period (in clock ticks). If non-zero, your task will +* wait for the resource up to the amount of time specified by this argument. +* If you specify 0, however, your task will wait forever at the specified +* mutex or, until the resource becomes available. +* +* perr is a pointer to where an error message will be deposited. Possible error +* messages are: +* OS_ERR_NONE The call was successful and your task owns the mutex +* OS_ERR_TIMEOUT The mutex was not available within the specified 'timeout'. +* OS_ERR_PEND_ABORT The wait on the mutex was aborted. +* OS_ERR_EVENT_TYPE If you didn't pass a pointer to a mutex +* OS_ERR_PEVENT_NULL 'pevent' is a NULL pointer +* OS_ERR_PEND_ISR If you called this function from an ISR and the result +* would lead to a suspension. +* OS_ERR_PIP_LOWER If the priority of the task that owns the Mutex is +* HIGHER (i.e. a lower number) than the PIP. This error +* indicates that you did not set the PIP higher (lower +* number) than ALL the tasks that compete for the Mutex. +* Unfortunately, this is something that could not be +* detected when the Mutex is created because we don't know +* what tasks will be using the Mutex. +* OS_ERR_PEND_LOCKED If you called this function when the scheduler is locked +* +* Returns : none +* +* Note(s) : 1) The task that owns the Mutex MUST NOT pend on any other event while it owns the mutex. +* +* 2) You MUST NOT change the priority of the task that owns the mutex +********************************************************************************************************* +*/ + +void OSMutexPend (OS_EVENT *pevent, INT16U timeout, INT8U *perr) +{ + INT8U pip; /* Priority Inheritance Priority (PIP) */ + INT8U mprio; /* Mutex owner priority */ + BOOLEAN rdy; /* Flag indicating task was ready */ + OS_TCB *ptcb; + OS_EVENT *pevent2; + INT8U y; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + return; + } + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + *perr = OS_ERR_PEVENT_NULL; + return; + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_MUTEX) { /* Validate event block type */ + *perr = OS_ERR_EVENT_TYPE; + return; + } + if (OSIntNesting > 0) { /* See if called from ISR ... */ + *perr = OS_ERR_PEND_ISR; /* ... can't PEND from an ISR */ + return; + } + if (OSLockNesting > 0) { /* See if called with scheduler locked ... */ + *perr = OS_ERR_PEND_LOCKED; /* ... can't PEND when locked */ + return; + } +/*$PAGE*/ + OS_ENTER_CRITICAL(); + pip = (INT8U)(pevent->OSEventCnt >> 8); /* Get PIP from mutex */ + /* Is Mutex available? */ + if ((INT8U)(pevent->OSEventCnt & OS_MUTEX_KEEP_LOWER_8) == OS_MUTEX_AVAILABLE) { + pevent->OSEventCnt &= OS_MUTEX_KEEP_UPPER_8; /* Yes, Acquire the resource */ + pevent->OSEventCnt |= OSTCBCur->OSTCBPrio; /* Save priority of owning task */ + pevent->OSEventPtr = (void *)OSTCBCur; /* Point to owning task's OS_TCB */ + if (OSTCBCur->OSTCBPrio <= pip) { /* PIP 'must' have a SMALLER prio ... */ + OS_EXIT_CRITICAL(); /* ... than current task! */ + *perr = OS_ERR_PIP_LOWER; + } else { + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + } + return; + } + mprio = (INT8U)(pevent->OSEventCnt & OS_MUTEX_KEEP_LOWER_8); /* No, Get priority of mutex owner */ + ptcb = (OS_TCB *)(pevent->OSEventPtr); /* Point to TCB of mutex owner */ + if (ptcb->OSTCBPrio > pip) { /* Need to promote prio of owner?*/ + if (mprio > OSTCBCur->OSTCBPrio) { + y = ptcb->OSTCBY; + if ((OSRdyTbl[y] & ptcb->OSTCBBitX) != 0) { /* See if mutex owner is ready */ + OSRdyTbl[y] &= ~ptcb->OSTCBBitX; /* Yes, Remove owner from Rdy ...*/ + if (OSRdyTbl[y] == 0) { /* ... list at current prio */ + OSRdyGrp &= ~ptcb->OSTCBBitY; + } + rdy = OS_TRUE; + } else { + pevent2 = ptcb->OSTCBEventPtr; + if (pevent2 != (OS_EVENT *)0) { /* Remove from event wait list */ + if ((pevent2->OSEventTbl[ptcb->OSTCBY] &= ~ptcb->OSTCBBitX) == 0) { + pevent2->OSEventGrp &= ~ptcb->OSTCBBitY; + } + } + rdy = OS_FALSE; /* No */ + } + ptcb->OSTCBPrio = pip; /* Change owner task prio to PIP */ +#if OS_LOWEST_PRIO <= 63 + ptcb->OSTCBY = (INT8U)( ptcb->OSTCBPrio >> 3); + ptcb->OSTCBX = (INT8U)( ptcb->OSTCBPrio & 0x07); + ptcb->OSTCBBitY = (INT8U)(1 << ptcb->OSTCBY); + ptcb->OSTCBBitX = (INT8U)(1 << ptcb->OSTCBX); +#else + ptcb->OSTCBY = (INT8U)((ptcb->OSTCBPrio >> 4) & 0xFF); + ptcb->OSTCBX = (INT8U)( ptcb->OSTCBPrio & 0x0F); + ptcb->OSTCBBitY = (INT16U)(1 << ptcb->OSTCBY); + ptcb->OSTCBBitX = (INT16U)(1 << ptcb->OSTCBX); +#endif + if (rdy == OS_TRUE) { /* If task was ready at owner's priority ...*/ + OSRdyGrp |= ptcb->OSTCBBitY; /* ... make it ready at new priority. */ + OSRdyTbl[ptcb->OSTCBY] |= ptcb->OSTCBBitX; + } else { + pevent2 = ptcb->OSTCBEventPtr; + if (pevent2 != (OS_EVENT *)0) { /* Add to event wait list */ + pevent2->OSEventGrp |= ptcb->OSTCBBitY; + pevent2->OSEventTbl[ptcb->OSTCBY] |= ptcb->OSTCBBitX; + } + } + OSTCBPrioTbl[pip] = ptcb; + } + } + OSTCBCur->OSTCBStat |= OS_STAT_MUTEX; /* Mutex not available, pend current task */ + OSTCBCur->OSTCBStatPend = OS_STAT_PEND_OK; + OSTCBCur->OSTCBDly = timeout; /* Store timeout in current task's TCB */ + OS_EventTaskWait(pevent); /* Suspend task until event or timeout occurs */ + OS_EXIT_CRITICAL(); + OS_Sched(); /* Find next highest priority task ready */ + OS_ENTER_CRITICAL(); + switch (OSTCBCur->OSTCBStatPend) { /* See if we timed-out or aborted */ + case OS_STAT_PEND_OK: + *perr = OS_ERR_NONE; + break; + + case OS_STAT_PEND_ABORT: + *perr = OS_ERR_PEND_ABORT; /* Indicate that we aborted getting mutex */ + break; + + case OS_STAT_PEND_TO: + default: + OS_EventTaskRemove(OSTCBCur, pevent); + *perr = OS_ERR_TIMEOUT; /* Indicate that we didn't get mutex within TO */ + break; + } + OSTCBCur->OSTCBStat = OS_STAT_RDY; /* Set task status to ready */ + OSTCBCur->OSTCBStatPend = OS_STAT_PEND_OK; /* Clear pend status */ + OSTCBCur->OSTCBEventPtr = (OS_EVENT *)0; /* Clear event pointers */ +#if (OS_EVENT_MULTI_EN > 0) + OSTCBCur->OSTCBEventMultiPtr = (OS_EVENT **)0; +#endif + OS_EXIT_CRITICAL(); +} +/*$PAGE*/ +/* +********************************************************************************************************* +* POST TO A MUTUAL EXCLUSION SEMAPHORE +* +* Description: This function signals a mutual exclusion semaphore +* +* Arguments : pevent is a pointer to the event control block associated with the desired +* mutex. +* +* Returns : OS_ERR_NONE The call was successful and the mutex was signaled. +* OS_ERR_EVENT_TYPE If you didn't pass a pointer to a mutex +* OS_ERR_PEVENT_NULL 'pevent' is a NULL pointer +* OS_ERR_POST_ISR Attempted to post from an ISR (not valid for MUTEXes) +* OS_ERR_NOT_MUTEX_OWNER The task that did the post is NOT the owner of the MUTEX. +* OS_ERR_PIP_LOWER If the priority of the new task that owns the Mutex is +* HIGHER (i.e. a lower number) than the PIP. This error +* indicates that you did not set the PIP higher (lower +* number) than ALL the tasks that compete for the Mutex. +* Unfortunately, this is something that could not be +* detected when the Mutex is created because we don't know +* what tasks will be using the Mutex. +********************************************************************************************************* +*/ + +INT8U OSMutexPost (OS_EVENT *pevent) +{ + INT8U pip; /* Priority inheritance priority */ + INT8U prio; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + + if (OSIntNesting > 0) { /* See if called from ISR ... */ + return (OS_ERR_POST_ISR); /* ... can't POST mutex from an ISR */ + } +#if OS_ARG_CHK_EN > 0 + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + return (OS_ERR_PEVENT_NULL); + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_MUTEX) { /* Validate event block type */ + return (OS_ERR_EVENT_TYPE); + } + OS_ENTER_CRITICAL(); + pip = (INT8U)(pevent->OSEventCnt >> 8); /* Get priority inheritance priority of mutex */ + prio = (INT8U)(pevent->OSEventCnt & OS_MUTEX_KEEP_LOWER_8); /* Get owner's original priority */ + if (OSTCBCur != (OS_TCB *)pevent->OSEventPtr) { /* See if posting task owns the MUTEX */ + OS_EXIT_CRITICAL(); + return (OS_ERR_NOT_MUTEX_OWNER); + } + if (OSTCBCur->OSTCBPrio == pip) { /* Did we have to raise current task's priority? */ + OSMutex_RdyAtPrio(OSTCBCur, prio); /* Restore the task's original priority */ + } + OSTCBPrioTbl[pip] = OS_TCB_RESERVED; /* Reserve table entry */ + if (pevent->OSEventGrp != 0) { /* Any task waiting for the mutex? */ + /* Yes, Make HPT waiting for mutex ready */ + prio = OS_EventTaskRdy(pevent, (void *)0, OS_STAT_MUTEX, OS_STAT_PEND_OK); + pevent->OSEventCnt &= OS_MUTEX_KEEP_UPPER_8; /* Save priority of mutex's new owner */ + pevent->OSEventCnt |= prio; + pevent->OSEventPtr = OSTCBPrioTbl[prio]; /* Link to new mutex owner's OS_TCB */ + if (prio <= pip) { /* PIP 'must' have a SMALLER prio ... */ + OS_EXIT_CRITICAL(); /* ... than current task! */ + OS_Sched(); /* Find highest priority task ready to run */ + return (OS_ERR_PIP_LOWER); + } else { + OS_EXIT_CRITICAL(); + OS_Sched(); /* Find highest priority task ready to run */ + return (OS_ERR_NONE); + } + } + pevent->OSEventCnt |= OS_MUTEX_AVAILABLE; /* No, Mutex is now available */ + pevent->OSEventPtr = (void *)0; + OS_EXIT_CRITICAL(); + return (OS_ERR_NONE); +} +/*$PAGE*/ +/* +********************************************************************************************************* +* QUERY A MUTUAL EXCLUSION SEMAPHORE +* +* Description: This function obtains information about a mutex +* +* Arguments : pevent is a pointer to the event control block associated with the desired mutex +* +* p_mutex_data is a pointer to a structure that will contain information about the mutex +* +* Returns : OS_ERR_NONE The call was successful and the message was sent +* OS_ERR_QUERY_ISR If you called this function from an ISR +* OS_ERR_PEVENT_NULL If 'pevent' is a NULL pointer +* OS_ERR_PDATA_NULL If 'p_mutex_data' is a NULL pointer +* OS_ERR_EVENT_TYPE If you are attempting to obtain data from a non mutex. +********************************************************************************************************* +*/ + +#if OS_MUTEX_QUERY_EN > 0 +INT8U OSMutexQuery (OS_EVENT *pevent, OS_MUTEX_DATA *p_mutex_data) +{ + INT8U i; +#if OS_LOWEST_PRIO <= 63 + INT8U *psrc; + INT8U *pdest; +#else + INT16U *psrc; + INT16U *pdest; +#endif +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + + if (OSIntNesting > 0) { /* See if called from ISR ... */ + return (OS_ERR_QUERY_ISR); /* ... can't QUERY mutex from an ISR */ + } +#if OS_ARG_CHK_EN > 0 + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + return (OS_ERR_PEVENT_NULL); + } + if (p_mutex_data == (OS_MUTEX_DATA *)0) { /* Validate 'p_mutex_data' */ + return (OS_ERR_PDATA_NULL); + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_MUTEX) { /* Validate event block type */ + return (OS_ERR_EVENT_TYPE); + } + OS_ENTER_CRITICAL(); + p_mutex_data->OSMutexPIP = (INT8U)(pevent->OSEventCnt >> 8); + p_mutex_data->OSOwnerPrio = (INT8U)(pevent->OSEventCnt & OS_MUTEX_KEEP_LOWER_8); + if (p_mutex_data->OSOwnerPrio == 0xFF) { + p_mutex_data->OSValue = OS_TRUE; + } else { + p_mutex_data->OSValue = OS_FALSE; + } + p_mutex_data->OSEventGrp = pevent->OSEventGrp; /* Copy wait list */ + psrc = &pevent->OSEventTbl[0]; + pdest = &p_mutex_data->OSEventTbl[0]; + for (i = 0; i < OS_EVENT_TBL_SIZE; i++) { + *pdest++ = *psrc++; + } + OS_EXIT_CRITICAL(); + return (OS_ERR_NONE); +} +#endif /* OS_MUTEX_QUERY_EN */ + +/*$PAGE*/ +/* +********************************************************************************************************* +* RESTORE A TASK BACK TO ITS ORIGINAL PRIORITY +* +* Description: This function makes a task ready at the specified priority +* +* Arguments : ptcb is a pointer to OS_TCB of the task to make ready +* +* prio is the desired priority +* +* Returns : none +********************************************************************************************************* +*/ + +static void OSMutex_RdyAtPrio (OS_TCB *ptcb, INT8U prio) +{ + INT8U y; + + + y = ptcb->OSTCBY; /* Remove owner from ready list at 'pip' */ + OSRdyTbl[y] &= ~ptcb->OSTCBBitX; + if (OSRdyTbl[y] == 0) { + OSRdyGrp &= ~ptcb->OSTCBBitY; + } + ptcb->OSTCBPrio = prio; +#if OS_LOWEST_PRIO <= 63 + ptcb->OSTCBY = (INT8U)((prio >> (INT8U)3) & (INT8U)0x07); + ptcb->OSTCBX = (INT8U) (prio & (INT8U)0x07); + ptcb->OSTCBBitY = (INT8U)(1 << ptcb->OSTCBY); + ptcb->OSTCBBitX = (INT8U)(1 << ptcb->OSTCBX); +#else + ptcb->OSTCBY = (INT8U)((prio >> (INT8U)4) & (INT8U)0x0F); + ptcb->OSTCBX = (INT8U) (prio & (INT8U)0x0F); + ptcb->OSTCBBitY = (INT16U)(1 << ptcb->OSTCBY); + ptcb->OSTCBBitX = (INT16U)(1 << ptcb->OSTCBX); +#endif + OSRdyGrp |= ptcb->OSTCBBitY; /* Make task ready at original priority */ + OSRdyTbl[ptcb->OSTCBY] |= ptcb->OSTCBBitX; + OSTCBPrioTbl[prio] = ptcb; +} + + +#endif /* OS_MUTEX_EN */ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/UCOSII/src/os_q.c b/MCandWifiTestDE0/Software/MCTest_bsp/UCOSII/src/os_q.c new file mode 100644 index 00000000..5b655d27 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/UCOSII/src/os_q.c @@ -0,0 +1,868 @@ +/* +********************************************************************************************************* +* uC/OS-II +* The Real-Time Kernel +* MESSAGE QUEUE MANAGEMENT +* +* (c) Copyright 1992-2007, Micrium, Weston, FL +* All Rights Reserved +* +* File : OS_Q.C +* By : Jean J. Labrosse +* Version : V2.86 +* +* LICENSING TERMS: +* --------------- +* uC/OS-II is provided in source form for FREE evaluation, for educational use or for peaceful research. +* If you plan on using uC/OS-II in a commercial product you need to contact Micriµm to properly license +* its use in your product. We provide ALL the source code for your convenience and to help you experience +* uC/OS-II. The fact that the source is provided does NOT mean that you can use it without paying a +* licensing fee. +********************************************************************************************************* +*/ + +#ifndef OS_MASTER_FILE +#include +#endif + +#if (OS_Q_EN > 0) && (OS_MAX_QS > 0) +/* +********************************************************************************************************* +* ACCEPT MESSAGE FROM QUEUE +* +* Description: This function checks the queue to see if a message is available. Unlike OSQPend(), +* OSQAccept() does not suspend the calling task if a message is not available. +* +* Arguments : pevent is a pointer to the event control block +* +* perr is a pointer to where an error message will be deposited. Possible error +* messages are: +* +* OS_ERR_NONE The call was successful and your task received a +* message. +* OS_ERR_EVENT_TYPE You didn't pass a pointer to a queue +* OS_ERR_PEVENT_NULL If 'pevent' is a NULL pointer +* OS_ERR_Q_EMPTY The queue did not contain any messages +* +* Returns : != (void *)0 is the message in the queue if one is available. The message is removed +* from the so the next time OSQAccept() is called, the queue will contain +* one less entry. +* == (void *)0 if you received a NULL pointer message +* if the queue is empty or, +* if 'pevent' is a NULL pointer or, +* if you passed an invalid event type +* +* Note(s) : As of V2.60, you can now pass NULL pointers through queues. Because of this, the argument +* 'perr' has been added to the API to tell you about the outcome of the call. +********************************************************************************************************* +*/ + +#if OS_Q_ACCEPT_EN > 0 +void *OSQAccept (OS_EVENT *pevent, INT8U *perr) +{ + void *pmsg; + OS_Q *pq; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + return ((void *)0); + } + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + *perr = OS_ERR_PEVENT_NULL; + return ((void *)0); + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_Q) {/* Validate event block type */ + *perr = OS_ERR_EVENT_TYPE; + return ((void *)0); + } + OS_ENTER_CRITICAL(); + pq = (OS_Q *)pevent->OSEventPtr; /* Point at queue control block */ + if (pq->OSQEntries > 0) { /* See if any messages in the queue */ + pmsg = *pq->OSQOut++; /* Yes, extract oldest message from the queue */ + pq->OSQEntries--; /* Update the number of entries in the queue */ + if (pq->OSQOut == pq->OSQEnd) { /* Wrap OUT pointer if we are at the end of the queue */ + pq->OSQOut = pq->OSQStart; + } + *perr = OS_ERR_NONE; + } else { + *perr = OS_ERR_Q_EMPTY; + pmsg = (void *)0; /* Queue is empty */ + } + OS_EXIT_CRITICAL(); + return (pmsg); /* Return message received (or NULL) */ +} +#endif +/*$PAGE*/ +/* +********************************************************************************************************* +* CREATE A MESSAGE QUEUE +* +* Description: This function creates a message queue if free event control blocks are available. +* +* Arguments : start is a pointer to the base address of the message queue storage area. The +* storage area MUST be declared as an array of pointers to 'void' as follows +* +* void *MessageStorage[size] +* +* size is the number of elements in the storage area +* +* Returns : != (OS_EVENT *)0 is a pointer to the event control clock (OS_EVENT) associated with the +* created queue +* == (OS_EVENT *)0 if no event control blocks were available or an error was detected +********************************************************************************************************* +*/ + +OS_EVENT *OSQCreate (void **start, INT16U size) +{ + OS_EVENT *pevent; + OS_Q *pq; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + + if (OSIntNesting > 0) { /* See if called from ISR ... */ + return ((OS_EVENT *)0); /* ... can't CREATE from an ISR */ + } + OS_ENTER_CRITICAL(); + pevent = OSEventFreeList; /* Get next free event control block */ + if (OSEventFreeList != (OS_EVENT *)0) { /* See if pool of free ECB pool was empty */ + OSEventFreeList = (OS_EVENT *)OSEventFreeList->OSEventPtr; + } + OS_EXIT_CRITICAL(); + if (pevent != (OS_EVENT *)0) { /* See if we have an event control block */ + OS_ENTER_CRITICAL(); + pq = OSQFreeList; /* Get a free queue control block */ + if (pq != (OS_Q *)0) { /* Were we able to get a queue control block ? */ + OSQFreeList = OSQFreeList->OSQPtr; /* Yes, Adjust free list pointer to next free*/ + OS_EXIT_CRITICAL(); + pq->OSQStart = start; /* Initialize the queue */ + pq->OSQEnd = &start[size]; + pq->OSQIn = start; + pq->OSQOut = start; + pq->OSQSize = size; + pq->OSQEntries = 0; + pevent->OSEventType = OS_EVENT_TYPE_Q; + pevent->OSEventCnt = 0; + pevent->OSEventPtr = pq; +#if OS_EVENT_NAME_SIZE > 1 + pevent->OSEventName[0] = '?'; /* Unknown name */ + pevent->OSEventName[1] = OS_ASCII_NUL; +#endif + OS_EventWaitListInit(pevent); /* Initalize the wait list */ + } else { + pevent->OSEventPtr = (void *)OSEventFreeList; /* No, Return event control block on error */ + OSEventFreeList = pevent; + OS_EXIT_CRITICAL(); + pevent = (OS_EVENT *)0; + } + } + return (pevent); +} +/*$PAGE*/ +/* +********************************************************************************************************* +* DELETE A MESSAGE QUEUE +* +* Description: This function deletes a message queue and readies all tasks pending on the queue. +* +* Arguments : pevent is a pointer to the event control block associated with the desired +* queue. +* +* opt determines delete options as follows: +* opt == OS_DEL_NO_PEND Delete the queue ONLY if no task pending +* opt == OS_DEL_ALWAYS Deletes the queue even if tasks are waiting. +* In this case, all the tasks pending will be readied. +* +* perr is a pointer to an error code that can contain one of the following values: +* OS_ERR_NONE The call was successful and the queue was deleted +* OS_ERR_DEL_ISR If you tried to delete the queue from an ISR +* OS_ERR_INVALID_OPT An invalid option was specified +* OS_ERR_TASK_WAITING One or more tasks were waiting on the queue +* OS_ERR_EVENT_TYPE If you didn't pass a pointer to a queue +* OS_ERR_PEVENT_NULL If 'pevent' is a NULL pointer. +* +* Returns : pevent upon error +* (OS_EVENT *)0 if the queue was successfully deleted. +* +* Note(s) : 1) This function must be used with care. Tasks that would normally expect the presence of +* the queue MUST check the return code of OSQPend(). +* 2) OSQAccept() callers will not know that the intended queue has been deleted unless +* they check 'pevent' to see that it's a NULL pointer. +* 3) This call can potentially disable interrupts for a long time. The interrupt disable +* time is directly proportional to the number of tasks waiting on the queue. +* 4) Because ALL tasks pending on the queue will be readied, you MUST be careful in +* applications where the queue is used for mutual exclusion because the resource(s) +* will no longer be guarded by the queue. +* 5) If the storage for the message queue was allocated dynamically (i.e. using a malloc() +* type call) then your application MUST release the memory storage by call the counterpart +* call of the dynamic allocation scheme used. If the queue storage was created statically +* then, the storage can be reused. +********************************************************************************************************* +*/ + +#if OS_Q_DEL_EN > 0 +OS_EVENT *OSQDel (OS_EVENT *pevent, INT8U opt, INT8U *perr) +{ + BOOLEAN tasks_waiting; + OS_EVENT *pevent_return; + OS_Q *pq; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + return (pevent); + } + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + *perr = OS_ERR_PEVENT_NULL; + return (pevent); + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_Q) { /* Validate event block type */ + *perr = OS_ERR_EVENT_TYPE; + return (pevent); + } + if (OSIntNesting > 0) { /* See if called from ISR ... */ + *perr = OS_ERR_DEL_ISR; /* ... can't DELETE from an ISR */ + return (pevent); + } + OS_ENTER_CRITICAL(); + if (pevent->OSEventGrp != 0) { /* See if any tasks waiting on queue */ + tasks_waiting = OS_TRUE; /* Yes */ + } else { + tasks_waiting = OS_FALSE; /* No */ + } + switch (opt) { + case OS_DEL_NO_PEND: /* Delete queue only if no task waiting */ + if (tasks_waiting == OS_FALSE) { +#if OS_EVENT_NAME_SIZE > 1 + pevent->OSEventName[0] = '?'; /* Unknown name */ + pevent->OSEventName[1] = OS_ASCII_NUL; +#endif + pq = (OS_Q *)pevent->OSEventPtr; /* Return OS_Q to free list */ + pq->OSQPtr = OSQFreeList; + OSQFreeList = pq; + pevent->OSEventType = OS_EVENT_TYPE_UNUSED; + pevent->OSEventPtr = OSEventFreeList; /* Return Event Control Block to free list */ + pevent->OSEventCnt = 0; + OSEventFreeList = pevent; /* Get next free event control block */ + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + pevent_return = (OS_EVENT *)0; /* Queue has been deleted */ + } else { + OS_EXIT_CRITICAL(); + *perr = OS_ERR_TASK_WAITING; + pevent_return = pevent; + } + break; + + case OS_DEL_ALWAYS: /* Always delete the queue */ + while (pevent->OSEventGrp != 0) { /* Ready ALL tasks waiting for queue */ + (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_Q, OS_STAT_PEND_OK); + } +#if OS_EVENT_NAME_SIZE > 1 + pevent->OSEventName[0] = '?'; /* Unknown name */ + pevent->OSEventName[1] = OS_ASCII_NUL; +#endif + pq = (OS_Q *)pevent->OSEventPtr; /* Return OS_Q to free list */ + pq->OSQPtr = OSQFreeList; + OSQFreeList = pq; + pevent->OSEventType = OS_EVENT_TYPE_UNUSED; + pevent->OSEventPtr = OSEventFreeList; /* Return Event Control Block to free list */ + pevent->OSEventCnt = 0; + OSEventFreeList = pevent; /* Get next free event control block */ + OS_EXIT_CRITICAL(); + if (tasks_waiting == OS_TRUE) { /* Reschedule only if task(s) were waiting */ + OS_Sched(); /* Find highest priority task ready to run */ + } + *perr = OS_ERR_NONE; + pevent_return = (OS_EVENT *)0; /* Queue has been deleted */ + break; + + default: + OS_EXIT_CRITICAL(); + *perr = OS_ERR_INVALID_OPT; + pevent_return = pevent; + break; + } + return (pevent_return); +} +#endif + +/*$PAGE*/ +/* +********************************************************************************************************* +* FLUSH QUEUE +* +* Description : This function is used to flush the contents of the message queue. +* +* Arguments : none +* +* Returns : OS_ERR_NONE upon success +* OS_ERR_EVENT_TYPE If you didn't pass a pointer to a queue +* OS_ERR_PEVENT_NULL If 'pevent' is a NULL pointer +* +* WARNING : You should use this function with great care because, when to flush the queue, you LOOSE +* the references to what the queue entries are pointing to and thus, you could cause +* 'memory leaks'. In other words, the data you are pointing to that's being referenced +* by the queue entries should, most likely, need to be de-allocated (i.e. freed). +********************************************************************************************************* +*/ + +#if OS_Q_FLUSH_EN > 0 +INT8U OSQFlush (OS_EVENT *pevent) +{ + OS_Q *pq; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + return (OS_ERR_PEVENT_NULL); + } + if (pevent->OSEventType != OS_EVENT_TYPE_Q) { /* Validate event block type */ + return (OS_ERR_EVENT_TYPE); + } +#endif + OS_ENTER_CRITICAL(); + pq = (OS_Q *)pevent->OSEventPtr; /* Point to queue storage structure */ + pq->OSQIn = pq->OSQStart; + pq->OSQOut = pq->OSQStart; + pq->OSQEntries = 0; + OS_EXIT_CRITICAL(); + return (OS_ERR_NONE); +} +#endif + +/*$PAGE*/ +/* +********************************************************************************************************* +* PEND ON A QUEUE FOR A MESSAGE +* +* Description: This function waits for a message to be sent to a queue +* +* Arguments : pevent is a pointer to the event control block associated with the desired queue +* +* timeout is an optional timeout period (in clock ticks). If non-zero, your task will +* wait for a message to arrive at the queue up to the amount of time +* specified by this argument. If you specify 0, however, your task will wait +* forever at the specified queue or, until a message arrives. +* +* perr is a pointer to where an error message will be deposited. Possible error +* messages are: +* +* OS_ERR_NONE The call was successful and your task received a +* message. +* OS_ERR_TIMEOUT A message was not received within the specified 'timeout'. +* OS_ERR_PEND_ABORT The wait on the queue was aborted. +* OS_ERR_EVENT_TYPE You didn't pass a pointer to a queue +* OS_ERR_PEVENT_NULL If 'pevent' is a NULL pointer +* OS_ERR_PEND_ISR If you called this function from an ISR and the result +* would lead to a suspension. +* OS_ERR_PEND_LOCKED If you called this function with the scheduler is locked +* +* Returns : != (void *)0 is a pointer to the message received +* == (void *)0 if you received a NULL pointer message or, +* if no message was received or, +* if 'pevent' is a NULL pointer or, +* if you didn't pass a pointer to a queue. +* +* Note(s) : As of V2.60, this function allows you to receive NULL pointer messages. +********************************************************************************************************* +*/ + +void *OSQPend (OS_EVENT *pevent, INT16U timeout, INT8U *perr) +{ + void *pmsg; + OS_Q *pq; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + return ((void *)0); + } + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + *perr = OS_ERR_PEVENT_NULL; + return ((void *)0); + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_Q) {/* Validate event block type */ + *perr = OS_ERR_EVENT_TYPE; + return ((void *)0); + } + if (OSIntNesting > 0) { /* See if called from ISR ... */ + *perr = OS_ERR_PEND_ISR; /* ... can't PEND from an ISR */ + return ((void *)0); + } + if (OSLockNesting > 0) { /* See if called with scheduler locked ... */ + *perr = OS_ERR_PEND_LOCKED; /* ... can't PEND when locked */ + return ((void *)0); + } + OS_ENTER_CRITICAL(); + pq = (OS_Q *)pevent->OSEventPtr; /* Point at queue control block */ + if (pq->OSQEntries > 0) { /* See if any messages in the queue */ + pmsg = *pq->OSQOut++; /* Yes, extract oldest message from the queue */ + pq->OSQEntries--; /* Update the number of entries in the queue */ + if (pq->OSQOut == pq->OSQEnd) { /* Wrap OUT pointer if we are at the end of the queue */ + pq->OSQOut = pq->OSQStart; + } + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + return (pmsg); /* Return message received */ + } + OSTCBCur->OSTCBStat |= OS_STAT_Q; /* Task will have to pend for a message to be posted */ + OSTCBCur->OSTCBStatPend = OS_STAT_PEND_OK; + OSTCBCur->OSTCBDly = timeout; /* Load timeout into TCB */ + OS_EventTaskWait(pevent); /* Suspend task until event or timeout occurs */ + OS_EXIT_CRITICAL(); + OS_Sched(); /* Find next highest priority task ready to run */ + OS_ENTER_CRITICAL(); + switch (OSTCBCur->OSTCBStatPend) { /* See if we timed-out or aborted */ + case OS_STAT_PEND_OK: /* Extract message from TCB (Put there by QPost) */ + pmsg = OSTCBCur->OSTCBMsg; + *perr = OS_ERR_NONE; + break; + + case OS_STAT_PEND_ABORT: + pmsg = (void *)0; + *perr = OS_ERR_PEND_ABORT; /* Indicate that we aborted */ + break; + + case OS_STAT_PEND_TO: + default: + OS_EventTaskRemove(OSTCBCur, pevent); + pmsg = (void *)0; + *perr = OS_ERR_TIMEOUT; /* Indicate that we didn't get event within TO */ + break; + } + OSTCBCur->OSTCBStat = OS_STAT_RDY; /* Set task status to ready */ + OSTCBCur->OSTCBStatPend = OS_STAT_PEND_OK; /* Clear pend status */ + OSTCBCur->OSTCBEventPtr = (OS_EVENT *)0; /* Clear event pointers */ +#if (OS_EVENT_MULTI_EN > 0) + OSTCBCur->OSTCBEventMultiPtr = (OS_EVENT **)0; +#endif + OSTCBCur->OSTCBMsg = (void *)0; /* Clear received message */ + OS_EXIT_CRITICAL(); + return (pmsg); /* Return received message */ +} +/*$PAGE*/ +/* +********************************************************************************************************* +* ABORT WAITING ON A MESSAGE QUEUE +* +* Description: This function aborts & readies any tasks currently waiting on a queue. This function +* should be used to fault-abort the wait on the queue, rather than to normally signal +* the queue via OSQPost(), OSQPostFront() or OSQPostOpt(). +* +* Arguments : pevent is a pointer to the event control block associated with the desired queue. +* +* opt determines the type of ABORT performed: +* OS_PEND_OPT_NONE ABORT wait for a single task (HPT) waiting on the +* queue +* OS_PEND_OPT_BROADCAST ABORT wait for ALL tasks that are waiting on the +* queue +* +* perr is a pointer to where an error message will be deposited. Possible error +* messages are: +* +* OS_ERR_NONE No tasks were waiting on the queue. +* OS_ERR_PEND_ABORT At least one task waiting on the queue was readied +* and informed of the aborted wait; check return value +* for the number of tasks whose wait on the queue +* was aborted. +* OS_ERR_EVENT_TYPE If you didn't pass a pointer to a queue. +* OS_ERR_PEVENT_NULL If 'pevent' is a NULL pointer. +* +* Returns : == 0 if no tasks were waiting on the queue, or upon error. +* > 0 if one or more tasks waiting on the queue are now readied and informed. +********************************************************************************************************* +*/ + +#if OS_Q_PEND_ABORT_EN > 0 +INT8U OSQPendAbort (OS_EVENT *pevent, INT8U opt, INT8U *perr) +{ + INT8U nbr_tasks; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + return (0); + } + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + *perr = OS_ERR_PEVENT_NULL; + return (0); + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_Q) { /* Validate event block type */ + *perr = OS_ERR_EVENT_TYPE; + return (0); + } + OS_ENTER_CRITICAL(); + if (pevent->OSEventGrp != 0) { /* See if any task waiting on queue? */ + nbr_tasks = 0; + switch (opt) { + case OS_PEND_OPT_BROADCAST: /* Do we need to abort ALL waiting tasks? */ + while (pevent->OSEventGrp != 0) { /* Yes, ready ALL tasks waiting on queue */ + (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_Q, OS_STAT_PEND_ABORT); + nbr_tasks++; + } + break; + + case OS_PEND_OPT_NONE: + default: /* No, ready HPT waiting on queue */ + (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_Q, OS_STAT_PEND_ABORT); + nbr_tasks++; + break; + } + OS_EXIT_CRITICAL(); + OS_Sched(); /* Find HPT ready to run */ + *perr = OS_ERR_PEND_ABORT; + return (nbr_tasks); + } + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + return (0); /* No tasks waiting on queue */ +} +#endif + +/*$PAGE*/ +/* +********************************************************************************************************* +* POST MESSAGE TO A QUEUE +* +* Description: This function sends a message to a queue +* +* Arguments : pevent is a pointer to the event control block associated with the desired queue +* +* pmsg is a pointer to the message to send. +* +* Returns : OS_ERR_NONE The call was successful and the message was sent +* OS_ERR_Q_FULL If the queue cannot accept any more messages because it is full. +* OS_ERR_EVENT_TYPE If you didn't pass a pointer to a queue. +* OS_ERR_PEVENT_NULL If 'pevent' is a NULL pointer +* +* Note(s) : As of V2.60, this function allows you to send NULL pointer messages. +********************************************************************************************************* +*/ + +#if OS_Q_POST_EN > 0 +INT8U OSQPost (OS_EVENT *pevent, void *pmsg) +{ + OS_Q *pq; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + return (OS_ERR_PEVENT_NULL); + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_Q) { /* Validate event block type */ + return (OS_ERR_EVENT_TYPE); + } + OS_ENTER_CRITICAL(); + if (pevent->OSEventGrp != 0) { /* See if any task pending on queue */ + /* Ready highest priority task waiting on event */ + (void)OS_EventTaskRdy(pevent, pmsg, OS_STAT_Q, OS_STAT_PEND_OK); + OS_EXIT_CRITICAL(); + OS_Sched(); /* Find highest priority task ready to run */ + return (OS_ERR_NONE); + } + pq = (OS_Q *)pevent->OSEventPtr; /* Point to queue control block */ + if (pq->OSQEntries >= pq->OSQSize) { /* Make sure queue is not full */ + OS_EXIT_CRITICAL(); + return (OS_ERR_Q_FULL); + } + *pq->OSQIn++ = pmsg; /* Insert message into queue */ + pq->OSQEntries++; /* Update the nbr of entries in the queue */ + if (pq->OSQIn == pq->OSQEnd) { /* Wrap IN ptr if we are at end of queue */ + pq->OSQIn = pq->OSQStart; + } + OS_EXIT_CRITICAL(); + return (OS_ERR_NONE); +} +#endif +/*$PAGE*/ +/* +********************************************************************************************************* +* POST MESSAGE TO THE FRONT OF A QUEUE +* +* Description: This function sends a message to a queue but unlike OSQPost(), the message is posted at +* the front instead of the end of the queue. Using OSQPostFront() allows you to send +* 'priority' messages. +* +* Arguments : pevent is a pointer to the event control block associated with the desired queue +* +* pmsg is a pointer to the message to send. +* +* Returns : OS_ERR_NONE The call was successful and the message was sent +* OS_ERR_Q_FULL If the queue cannot accept any more messages because it is full. +* OS_ERR_EVENT_TYPE If you didn't pass a pointer to a queue. +* OS_ERR_PEVENT_NULL If 'pevent' is a NULL pointer +* +* Note(s) : As of V2.60, this function allows you to send NULL pointer messages. +********************************************************************************************************* +*/ + +#if OS_Q_POST_FRONT_EN > 0 +INT8U OSQPostFront (OS_EVENT *pevent, void *pmsg) +{ + OS_Q *pq; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + return (OS_ERR_PEVENT_NULL); + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_Q) { /* Validate event block type */ + return (OS_ERR_EVENT_TYPE); + } + OS_ENTER_CRITICAL(); + if (pevent->OSEventGrp != 0) { /* See if any task pending on queue */ + /* Ready highest priority task waiting on event */ + (void)OS_EventTaskRdy(pevent, pmsg, OS_STAT_Q, OS_STAT_PEND_OK); + OS_EXIT_CRITICAL(); + OS_Sched(); /* Find highest priority task ready to run */ + return (OS_ERR_NONE); + } + pq = (OS_Q *)pevent->OSEventPtr; /* Point to queue control block */ + if (pq->OSQEntries >= pq->OSQSize) { /* Make sure queue is not full */ + OS_EXIT_CRITICAL(); + return (OS_ERR_Q_FULL); + } + if (pq->OSQOut == pq->OSQStart) { /* Wrap OUT ptr if we are at the 1st queue entry */ + pq->OSQOut = pq->OSQEnd; + } + pq->OSQOut--; + *pq->OSQOut = pmsg; /* Insert message into queue */ + pq->OSQEntries++; /* Update the nbr of entries in the queue */ + OS_EXIT_CRITICAL(); + return (OS_ERR_NONE); +} +#endif +/*$PAGE*/ +/* +********************************************************************************************************* +* POST MESSAGE TO A QUEUE +* +* Description: This function sends a message to a queue. This call has been added to reduce code size +* since it can replace both OSQPost() and OSQPostFront(). Also, this function adds the +* capability to broadcast a message to ALL tasks waiting on the message queue. +* +* Arguments : pevent is a pointer to the event control block associated with the desired queue +* +* pmsg is a pointer to the message to send. +* +* opt determines the type of POST performed: +* OS_POST_OPT_NONE POST to a single waiting task +* (Identical to OSQPost()) +* OS_POST_OPT_BROADCAST POST to ALL tasks that are waiting on the queue +* OS_POST_OPT_FRONT POST as LIFO (Simulates OSQPostFront()) +* OS_POST_OPT_NO_SCHED Indicates that the scheduler will NOT be invoked +* +* Returns : OS_ERR_NONE The call was successful and the message was sent +* OS_ERR_Q_FULL If the queue cannot accept any more messages because it is full. +* OS_ERR_EVENT_TYPE If you didn't pass a pointer to a queue. +* OS_ERR_PEVENT_NULL If 'pevent' is a NULL pointer +* +* Warning : Interrupts can be disabled for a long time if you do a 'broadcast'. In fact, the +* interrupt disable time is proportional to the number of tasks waiting on the queue. +********************************************************************************************************* +*/ + +#if OS_Q_POST_OPT_EN > 0 +INT8U OSQPostOpt (OS_EVENT *pevent, void *pmsg, INT8U opt) +{ + OS_Q *pq; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + return (OS_ERR_PEVENT_NULL); + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_Q) { /* Validate event block type */ + return (OS_ERR_EVENT_TYPE); + } + OS_ENTER_CRITICAL(); + if (pevent->OSEventGrp != 0x00) { /* See if any task pending on queue */ + if ((opt & OS_POST_OPT_BROADCAST) != 0x00) { /* Do we need to post msg to ALL waiting tasks ? */ + while (pevent->OSEventGrp != 0) { /* Yes, Post to ALL tasks waiting on queue */ + (void)OS_EventTaskRdy(pevent, pmsg, OS_STAT_Q, OS_STAT_PEND_OK); + } + } else { /* No, Post to HPT waiting on queue */ + (void)OS_EventTaskRdy(pevent, pmsg, OS_STAT_Q, OS_STAT_PEND_OK); + } + OS_EXIT_CRITICAL(); + if ((opt & OS_POST_OPT_NO_SCHED) == 0) { /* See if scheduler needs to be invoked */ + OS_Sched(); /* Find highest priority task ready to run */ + } + return (OS_ERR_NONE); + } + pq = (OS_Q *)pevent->OSEventPtr; /* Point to queue control block */ + if (pq->OSQEntries >= pq->OSQSize) { /* Make sure queue is not full */ + OS_EXIT_CRITICAL(); + return (OS_ERR_Q_FULL); + } + if ((opt & OS_POST_OPT_FRONT) != 0x00) { /* Do we post to the FRONT of the queue? */ + if (pq->OSQOut == pq->OSQStart) { /* Yes, Post as LIFO, Wrap OUT pointer if we ... */ + pq->OSQOut = pq->OSQEnd; /* ... are at the 1st queue entry */ + } + pq->OSQOut--; + *pq->OSQOut = pmsg; /* Insert message into queue */ + } else { /* No, Post as FIFO */ + *pq->OSQIn++ = pmsg; /* Insert message into queue */ + if (pq->OSQIn == pq->OSQEnd) { /* Wrap IN ptr if we are at end of queue */ + pq->OSQIn = pq->OSQStart; + } + } + pq->OSQEntries++; /* Update the nbr of entries in the queue */ + OS_EXIT_CRITICAL(); + return (OS_ERR_NONE); +} +#endif +/*$PAGE*/ +/* +********************************************************************************************************* +* QUERY A MESSAGE QUEUE +* +* Description: This function obtains information about a message queue. +* +* Arguments : pevent is a pointer to the event control block associated with the desired queue +* +* p_q_data is a pointer to a structure that will contain information about the message +* queue. +* +* Returns : OS_ERR_NONE The call was successful and the message was sent +* OS_ERR_EVENT_TYPE If you are attempting to obtain data from a non queue. +* OS_ERR_PEVENT_NULL If 'pevent' is a NULL pointer +* OS_ERR_PDATA_NULL If 'p_q_data' is a NULL pointer +********************************************************************************************************* +*/ + +#if OS_Q_QUERY_EN > 0 +INT8U OSQQuery (OS_EVENT *pevent, OS_Q_DATA *p_q_data) +{ + OS_Q *pq; + INT8U i; +#if OS_LOWEST_PRIO <= 63 + INT8U *psrc; + INT8U *pdest; +#else + INT16U *psrc; + INT16U *pdest; +#endif +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + return (OS_ERR_PEVENT_NULL); + } + if (p_q_data == (OS_Q_DATA *)0) { /* Validate 'p_q_data' */ + return (OS_ERR_PDATA_NULL); + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_Q) { /* Validate event block type */ + return (OS_ERR_EVENT_TYPE); + } + OS_ENTER_CRITICAL(); + p_q_data->OSEventGrp = pevent->OSEventGrp; /* Copy message queue wait list */ + psrc = &pevent->OSEventTbl[0]; + pdest = &p_q_data->OSEventTbl[0]; + for (i = 0; i < OS_EVENT_TBL_SIZE; i++) { + *pdest++ = *psrc++; + } + pq = (OS_Q *)pevent->OSEventPtr; + if (pq->OSQEntries > 0) { + p_q_data->OSMsg = *pq->OSQOut; /* Get next message to return if available */ + } else { + p_q_data->OSMsg = (void *)0; + } + p_q_data->OSNMsgs = pq->OSQEntries; + p_q_data->OSQSize = pq->OSQSize; + OS_EXIT_CRITICAL(); + return (OS_ERR_NONE); +} +#endif /* OS_Q_QUERY_EN */ + +/*$PAGE*/ +/* +********************************************************************************************************* +* QUEUE MODULE INITIALIZATION +* +* Description : This function is called by uC/OS-II to initialize the message queue module. Your +* application MUST NOT call this function. +* +* Arguments : none +* +* Returns : none +* +* Note(s) : This function is INTERNAL to uC/OS-II and your application should not call it. +********************************************************************************************************* +*/ + +void OS_QInit (void) +{ +#if OS_MAX_QS == 1 + OSQFreeList = &OSQTbl[0]; /* Only ONE queue! */ + OSQFreeList->OSQPtr = (OS_Q *)0; +#endif + +#if OS_MAX_QS >= 2 + INT16U i; + OS_Q *pq1; + OS_Q *pq2; + + + + OS_MemClr((INT8U *)&OSQTbl[0], sizeof(OSQTbl)); /* Clear the queue table */ + pq1 = &OSQTbl[0]; + pq2 = &OSQTbl[1]; + for (i = 0; i < (OS_MAX_QS - 1); i++) { /* Init. list of free QUEUE control blocks */ + pq1->OSQPtr = pq2; + pq1++; + pq2++; + } + pq1->OSQPtr = (OS_Q *)0; + OSQFreeList = &OSQTbl[0]; +#endif +} +#endif /* OS_Q_EN */ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/UCOSII/src/os_sem.c b/MCandWifiTestDE0/Software/MCTest_bsp/UCOSII/src/os_sem.c new file mode 100644 index 00000000..19770041 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/UCOSII/src/os_sem.c @@ -0,0 +1,609 @@ +/* +********************************************************************************************************* +* uC/OS-II +* The Real-Time Kernel +* SEMAPHORE MANAGEMENT +* +* (c) Copyright 1992-2007, Micrium, Weston, FL +* All Rights Reserved +* +* File : OS_SEM.C +* By : Jean J. Labrosse +* Version : V2.86 +* +* LICENSING TERMS: +* --------------- +* uC/OS-II is provided in source form for FREE evaluation, for educational use or for peaceful research. +* If you plan on using uC/OS-II in a commercial product you need to contact Micriµm to properly license +* its use in your product. We provide ALL the source code for your convenience and to help you experience +* uC/OS-II. The fact that the source is provided does NOT mean that you can use it without paying a +* licensing fee. +********************************************************************************************************* +*/ + +#ifndef OS_MASTER_FILE +#include +#endif + +#if OS_SEM_EN > 0 +/*$PAGE*/ +/* +********************************************************************************************************* +* ACCEPT SEMAPHORE +* +* Description: This function checks the semaphore to see if a resource is available or, if an event +* occurred. Unlike OSSemPend(), OSSemAccept() does not suspend the calling task if the +* resource is not available or the event did not occur. +* +* Arguments : pevent is a pointer to the event control block +* +* Returns : > 0 if the resource is available or the event did not occur the semaphore is +* decremented to obtain the resource. +* == 0 if the resource is not available or the event did not occur or, +* if 'pevent' is a NULL pointer or, +* if you didn't pass a pointer to a semaphore +********************************************************************************************************* +*/ + +#if OS_SEM_ACCEPT_EN > 0 +INT16U OSSemAccept (OS_EVENT *pevent) +{ + INT16U cnt; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + return (0); + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_SEM) { /* Validate event block type */ + return (0); + } + OS_ENTER_CRITICAL(); + cnt = pevent->OSEventCnt; + if (cnt > 0) { /* See if resource is available */ + pevent->OSEventCnt--; /* Yes, decrement semaphore and notify caller */ + } + OS_EXIT_CRITICAL(); + return (cnt); /* Return semaphore count */ +} +#endif + +/*$PAGE*/ +/* +********************************************************************************************************* +* CREATE A SEMAPHORE +* +* Description: This function creates a semaphore. +* +* Arguments : cnt is the initial value for the semaphore. If the value is 0, no resource is +* available (or no event has occurred). You initialize the semaphore to a +* non-zero value to specify how many resources are available (e.g. if you have +* 10 resources, you would initialize the semaphore to 10). +* +* Returns : != (void *)0 is a pointer to the event control block (OS_EVENT) associated with the +* created semaphore +* == (void *)0 if no event control blocks were available +********************************************************************************************************* +*/ + +OS_EVENT *OSSemCreate (INT16U cnt) +{ + OS_EVENT *pevent; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + + if (OSIntNesting > 0) { /* See if called from ISR ... */ + return ((OS_EVENT *)0); /* ... can't CREATE from an ISR */ + } + OS_ENTER_CRITICAL(); + pevent = OSEventFreeList; /* Get next free event control block */ + if (OSEventFreeList != (OS_EVENT *)0) { /* See if pool of free ECB pool was empty */ + OSEventFreeList = (OS_EVENT *)OSEventFreeList->OSEventPtr; + } + OS_EXIT_CRITICAL(); + if (pevent != (OS_EVENT *)0) { /* Get an event control block */ + pevent->OSEventType = OS_EVENT_TYPE_SEM; + pevent->OSEventCnt = cnt; /* Set semaphore value */ + pevent->OSEventPtr = (void *)0; /* Unlink from ECB free list */ +#if OS_EVENT_NAME_SIZE > 1 + pevent->OSEventName[0] = '?'; /* Unknown name */ + pevent->OSEventName[1] = OS_ASCII_NUL; +#endif + OS_EventWaitListInit(pevent); /* Initialize to 'nobody waiting' on sem. */ + } + return (pevent); +} + +/*$PAGE*/ +/* +********************************************************************************************************* +* DELETE A SEMAPHORE +* +* Description: This function deletes a semaphore and readies all tasks pending on the semaphore. +* +* Arguments : pevent is a pointer to the event control block associated with the desired +* semaphore. +* +* opt determines delete options as follows: +* opt == OS_DEL_NO_PEND Delete semaphore ONLY if no task pending +* opt == OS_DEL_ALWAYS Deletes the semaphore even if tasks are waiting. +* In this case, all the tasks pending will be readied. +* +* perr is a pointer to an error code that can contain one of the following values: +* OS_ERR_NONE The call was successful and the semaphore was deleted +* OS_ERR_DEL_ISR If you attempted to delete the semaphore from an ISR +* OS_ERR_INVALID_OPT An invalid option was specified +* OS_ERR_TASK_WAITING One or more tasks were waiting on the semaphore +* OS_ERR_EVENT_TYPE If you didn't pass a pointer to a semaphore +* OS_ERR_PEVENT_NULL If 'pevent' is a NULL pointer. +* +* Returns : pevent upon error +* (OS_EVENT *)0 if the semaphore was successfully deleted. +* +* Note(s) : 1) This function must be used with care. Tasks that would normally expect the presence of +* the semaphore MUST check the return code of OSSemPend(). +* 2) OSSemAccept() callers will not know that the intended semaphore has been deleted unless +* they check 'pevent' to see that it's a NULL pointer. +* 3) This call can potentially disable interrupts for a long time. The interrupt disable +* time is directly proportional to the number of tasks waiting on the semaphore. +* 4) Because ALL tasks pending on the semaphore will be readied, you MUST be careful in +* applications where the semaphore is used for mutual exclusion because the resource(s) +* will no longer be guarded by the semaphore. +********************************************************************************************************* +*/ + +#if OS_SEM_DEL_EN > 0 +OS_EVENT *OSSemDel (OS_EVENT *pevent, INT8U opt, INT8U *perr) +{ + BOOLEAN tasks_waiting; + OS_EVENT *pevent_return; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + return (pevent); + } + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + *perr = OS_ERR_PEVENT_NULL; + return (pevent); + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_SEM) { /* Validate event block type */ + *perr = OS_ERR_EVENT_TYPE; + return (pevent); + } + if (OSIntNesting > 0) { /* See if called from ISR ... */ + *perr = OS_ERR_DEL_ISR; /* ... can't DELETE from an ISR */ + return (pevent); + } + OS_ENTER_CRITICAL(); + if (pevent->OSEventGrp != 0) { /* See if any tasks waiting on semaphore */ + tasks_waiting = OS_TRUE; /* Yes */ + } else { + tasks_waiting = OS_FALSE; /* No */ + } + switch (opt) { + case OS_DEL_NO_PEND: /* Delete semaphore only if no task waiting */ + if (tasks_waiting == OS_FALSE) { +#if OS_EVENT_NAME_SIZE > 1 + pevent->OSEventName[0] = '?'; /* Unknown name */ + pevent->OSEventName[1] = OS_ASCII_NUL; +#endif + pevent->OSEventType = OS_EVENT_TYPE_UNUSED; + pevent->OSEventPtr = OSEventFreeList; /* Return Event Control Block to free list */ + pevent->OSEventCnt = 0; + OSEventFreeList = pevent; /* Get next free event control block */ + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + pevent_return = (OS_EVENT *)0; /* Semaphore has been deleted */ + } else { + OS_EXIT_CRITICAL(); + *perr = OS_ERR_TASK_WAITING; + pevent_return = pevent; + } + break; + + case OS_DEL_ALWAYS: /* Always delete the semaphore */ + while (pevent->OSEventGrp != 0) { /* Ready ALL tasks waiting for semaphore */ + (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_SEM, OS_STAT_PEND_OK); + } +#if OS_EVENT_NAME_SIZE > 1 + pevent->OSEventName[0] = '?'; /* Unknown name */ + pevent->OSEventName[1] = OS_ASCII_NUL; +#endif + pevent->OSEventType = OS_EVENT_TYPE_UNUSED; + pevent->OSEventPtr = OSEventFreeList; /* Return Event Control Block to free list */ + pevent->OSEventCnt = 0; + OSEventFreeList = pevent; /* Get next free event control block */ + OS_EXIT_CRITICAL(); + if (tasks_waiting == OS_TRUE) { /* Reschedule only if task(s) were waiting */ + OS_Sched(); /* Find highest priority task ready to run */ + } + *perr = OS_ERR_NONE; + pevent_return = (OS_EVENT *)0; /* Semaphore has been deleted */ + break; + + default: + OS_EXIT_CRITICAL(); + *perr = OS_ERR_INVALID_OPT; + pevent_return = pevent; + break; + } + return (pevent_return); +} +#endif + +/*$PAGE*/ +/* +********************************************************************************************************* +* PEND ON SEMAPHORE +* +* Description: This function waits for a semaphore. +* +* Arguments : pevent is a pointer to the event control block associated with the desired +* semaphore. +* +* timeout is an optional timeout period (in clock ticks). If non-zero, your task will +* wait for the resource up to the amount of time specified by this argument. +* If you specify 0, however, your task will wait forever at the specified +* semaphore or, until the resource becomes available (or the event occurs). +* +* perr is a pointer to where an error message will be deposited. Possible error +* messages are: +* +* OS_ERR_NONE The call was successful and your task owns the resource +* or, the event you are waiting for occurred. +* OS_ERR_TIMEOUT The semaphore was not received within the specified +* 'timeout'. +* OS_ERR_PEND_ABORT The wait on the semaphore was aborted. +* OS_ERR_EVENT_TYPE If you didn't pass a pointer to a semaphore. +* OS_ERR_PEND_ISR If you called this function from an ISR and the result +* would lead to a suspension. +* OS_ERR_PEVENT_NULL If 'pevent' is a NULL pointer. +* OS_ERR_PEND_LOCKED If you called this function when the scheduler is locked +* +* Returns : none +********************************************************************************************************* +*/ +/*$PAGE*/ +void OSSemPend (OS_EVENT *pevent, INT16U timeout, INT8U *perr) +{ +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + return; + } + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + *perr = OS_ERR_PEVENT_NULL; + return; + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_SEM) { /* Validate event block type */ + *perr = OS_ERR_EVENT_TYPE; + return; + } + if (OSIntNesting > 0) { /* See if called from ISR ... */ + *perr = OS_ERR_PEND_ISR; /* ... can't PEND from an ISR */ + return; + } + if (OSLockNesting > 0) { /* See if called with scheduler locked ... */ + *perr = OS_ERR_PEND_LOCKED; /* ... can't PEND when locked */ + return; + } + OS_ENTER_CRITICAL(); + if (pevent->OSEventCnt > 0) { /* If sem. is positive, resource available ... */ + pevent->OSEventCnt--; /* ... decrement semaphore only if positive. */ + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + return; + } + /* Otherwise, must wait until event occurs */ + OSTCBCur->OSTCBStat |= OS_STAT_SEM; /* Resource not available, pend on semaphore */ + OSTCBCur->OSTCBStatPend = OS_STAT_PEND_OK; + OSTCBCur->OSTCBDly = timeout; /* Store pend timeout in TCB */ + OS_EventTaskWait(pevent); /* Suspend task until event or timeout occurs */ + OS_EXIT_CRITICAL(); + OS_Sched(); /* Find next highest priority task ready */ + OS_ENTER_CRITICAL(); + switch (OSTCBCur->OSTCBStatPend) { /* See if we timed-out or aborted */ + case OS_STAT_PEND_OK: + *perr = OS_ERR_NONE; + break; + + case OS_STAT_PEND_ABORT: + *perr = OS_ERR_PEND_ABORT; /* Indicate that we aborted */ + break; + + case OS_STAT_PEND_TO: + default: + OS_EventTaskRemove(OSTCBCur, pevent); + *perr = OS_ERR_TIMEOUT; /* Indicate that we didn't get event within TO */ + break; + } + OSTCBCur->OSTCBStat = OS_STAT_RDY; /* Set task status to ready */ + OSTCBCur->OSTCBStatPend = OS_STAT_PEND_OK; /* Clear pend status */ + OSTCBCur->OSTCBEventPtr = (OS_EVENT *)0; /* Clear event pointers */ +#if (OS_EVENT_MULTI_EN > 0) + OSTCBCur->OSTCBEventMultiPtr = (OS_EVENT **)0; +#endif + OS_EXIT_CRITICAL(); +} + +/*$PAGE*/ +/* +********************************************************************************************************* +* ABORT WAITING ON A SEMAPHORE +* +* Description: This function aborts & readies any tasks currently waiting on a semaphore. This function +* should be used to fault-abort the wait on the semaphore, rather than to normally signal +* the semaphore via OSSemPost(). +* +* Arguments : pevent is a pointer to the event control block associated with the desired +* semaphore. +* +* opt determines the type of ABORT performed: +* OS_PEND_OPT_NONE ABORT wait for a single task (HPT) waiting on the +* semaphore +* OS_PEND_OPT_BROADCAST ABORT wait for ALL tasks that are waiting on the +* semaphore +* +* perr is a pointer to where an error message will be deposited. Possible error +* messages are: +* +* OS_ERR_NONE No tasks were waiting on the semaphore. +* OS_ERR_PEND_ABORT At least one task waiting on the semaphore was readied +* and informed of the aborted wait; check return value +* for the number of tasks whose wait on the semaphore +* was aborted. +* OS_ERR_EVENT_TYPE If you didn't pass a pointer to a semaphore. +* OS_ERR_PEVENT_NULL If 'pevent' is a NULL pointer. +* +* Returns : == 0 if no tasks were waiting on the semaphore, or upon error. +* > 0 if one or more tasks waiting on the semaphore are now readied and informed. +********************************************************************************************************* +*/ + +#if OS_SEM_PEND_ABORT_EN > 0 +INT8U OSSemPendAbort (OS_EVENT *pevent, INT8U opt, INT8U *perr) +{ + INT8U nbr_tasks; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + return (0); + } + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + *perr = OS_ERR_PEVENT_NULL; + return (0); + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_SEM) { /* Validate event block type */ + *perr = OS_ERR_EVENT_TYPE; + return (0); + } + OS_ENTER_CRITICAL(); + if (pevent->OSEventGrp != 0) { /* See if any task waiting on semaphore? */ + nbr_tasks = 0; + switch (opt) { + case OS_PEND_OPT_BROADCAST: /* Do we need to abort ALL waiting tasks? */ + while (pevent->OSEventGrp != 0) { /* Yes, ready ALL tasks waiting on semaphore */ + (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_SEM, OS_STAT_PEND_ABORT); + nbr_tasks++; + } + break; + + case OS_PEND_OPT_NONE: + default: /* No, ready HPT waiting on semaphore */ + (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_SEM, OS_STAT_PEND_ABORT); + nbr_tasks++; + break; + } + OS_EXIT_CRITICAL(); + OS_Sched(); /* Find HPT ready to run */ + *perr = OS_ERR_PEND_ABORT; + return (nbr_tasks); + } + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + return (0); /* No tasks waiting on semaphore */ +} +#endif + +/*$PAGE*/ +/* +********************************************************************************************************* +* POST TO A SEMAPHORE +* +* Description: This function signals a semaphore +* +* Arguments : pevent is a pointer to the event control block associated with the desired +* semaphore. +* +* Returns : OS_ERR_NONE The call was successful and the semaphore was signaled. +* OS_ERR_SEM_OVF If the semaphore count exceeded its limit. In other words, you have +* signalled the semaphore more often than you waited on it with either +* OSSemAccept() or OSSemPend(). +* OS_ERR_EVENT_TYPE If you didn't pass a pointer to a semaphore +* OS_ERR_PEVENT_NULL If 'pevent' is a NULL pointer. +********************************************************************************************************* +*/ + +INT8U OSSemPost (OS_EVENT *pevent) +{ +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + return (OS_ERR_PEVENT_NULL); + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_SEM) { /* Validate event block type */ + return (OS_ERR_EVENT_TYPE); + } + OS_ENTER_CRITICAL(); + if (pevent->OSEventGrp != 0) { /* See if any task waiting for semaphore */ + /* Ready HPT waiting on event */ + (void)OS_EventTaskRdy(pevent, (void *)0, OS_STAT_SEM, OS_STAT_PEND_OK); + OS_EXIT_CRITICAL(); + OS_Sched(); /* Find HPT ready to run */ + return (OS_ERR_NONE); + } + if (pevent->OSEventCnt < 65535u) { /* Make sure semaphore will not overflow */ + pevent->OSEventCnt++; /* Increment semaphore count to register event */ + OS_EXIT_CRITICAL(); + return (OS_ERR_NONE); + } + OS_EXIT_CRITICAL(); /* Semaphore value has reached its maximum */ + return (OS_ERR_SEM_OVF); +} + +/*$PAGE*/ +/* +********************************************************************************************************* +* QUERY A SEMAPHORE +* +* Description: This function obtains information about a semaphore +* +* Arguments : pevent is a pointer to the event control block associated with the desired +* semaphore +* +* p_sem_data is a pointer to a structure that will contain information about the +* semaphore. +* +* Returns : OS_ERR_NONE The call was successful and the message was sent +* OS_ERR_EVENT_TYPE If you are attempting to obtain data from a non semaphore. +* OS_ERR_PEVENT_NULL If 'pevent' is a NULL pointer. +* OS_ERR_PDATA_NULL If 'p_sem_data' is a NULL pointer +********************************************************************************************************* +*/ + +#if OS_SEM_QUERY_EN > 0 +INT8U OSSemQuery (OS_EVENT *pevent, OS_SEM_DATA *p_sem_data) +{ +#if OS_LOWEST_PRIO <= 63 + INT8U *psrc; + INT8U *pdest; +#else + INT16U *psrc; + INT16U *pdest; +#endif + INT8U i; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + return (OS_ERR_PEVENT_NULL); + } + if (p_sem_data == (OS_SEM_DATA *)0) { /* Validate 'p_sem_data' */ + return (OS_ERR_PDATA_NULL); + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_SEM) { /* Validate event block type */ + return (OS_ERR_EVENT_TYPE); + } + OS_ENTER_CRITICAL(); + p_sem_data->OSEventGrp = pevent->OSEventGrp; /* Copy message mailbox wait list */ + psrc = &pevent->OSEventTbl[0]; + pdest = &p_sem_data->OSEventTbl[0]; + for (i = 0; i < OS_EVENT_TBL_SIZE; i++) { + *pdest++ = *psrc++; + } + p_sem_data->OSCnt = pevent->OSEventCnt; /* Get semaphore count */ + OS_EXIT_CRITICAL(); + return (OS_ERR_NONE); +} +#endif /* OS_SEM_QUERY_EN */ + +/*$PAGE*/ +/* +********************************************************************************************************* +* SET SEMAPHORE +* +* Description: This function sets the semaphore count to the value specified as an argument. Typically, +* this value would be 0. +* +* You would typically use this function when a semaphore is used as a signaling mechanism +* and, you want to reset the count value. +* +* Arguments : pevent is a pointer to the event control block +* +* cnt is the new value for the semaphore count. You would pass 0 to reset the +* semaphore count. +* +* perr is a pointer to an error code returned by the function as follows: +* +* OS_ERR_NONE The call was successful and the semaphore value was set. +* OS_ERR_EVENT_TYPE If you didn't pass a pointer to a semaphore. +* OS_ERR_PEVENT_NULL If 'pevent' is a NULL pointer. +* OS_ERR_TASK_WAITING If tasks are waiting on the semaphore. +********************************************************************************************************* +*/ + +#if OS_SEM_SET_EN > 0 +void OSSemSet (OS_EVENT *pevent, INT16U cnt, INT8U *perr) +{ +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + return; + } + if (pevent == (OS_EVENT *)0) { /* Validate 'pevent' */ + *perr = OS_ERR_PEVENT_NULL; + return; + } +#endif + if (pevent->OSEventType != OS_EVENT_TYPE_SEM) { /* Validate event block type */ + *perr = OS_ERR_EVENT_TYPE; + return; + } + OS_ENTER_CRITICAL(); + *perr = OS_ERR_NONE; + if (pevent->OSEventCnt > 0) { /* See if semaphore already has a count */ + pevent->OSEventCnt = cnt; /* Yes, set it to the new value specified. */ + } else { /* No */ + if (pevent->OSEventGrp == 0) { /* See if task(s) waiting? */ + pevent->OSEventCnt = cnt; /* No, OK to set the value */ + } else { + *perr = OS_ERR_TASK_WAITING; + } + } + OS_EXIT_CRITICAL(); +} +#endif + +#endif /* OS_SEM_EN */ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/UCOSII/src/os_task.c b/MCandWifiTestDE0/Software/MCTest_bsp/UCOSII/src/os_task.c new file mode 100644 index 00000000..212a15ff --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/UCOSII/src/os_task.c @@ -0,0 +1,1095 @@ +/* +********************************************************************************************************* +* uC/OS-II +* The Real-Time Kernel +* TASK MANAGEMENT +* +* (c) Copyright 1992-2007, Micrium, Weston, FL +* All Rights Reserved +* +* File : OS_TASK.C +* By : Jean J. Labrosse +* Version : V2.86 +* +* LICENSING TERMS: +* --------------- +* uC/OS-II is provided in source form for FREE evaluation, for educational use or for peaceful research. +* If you plan on using uC/OS-II in a commercial product you need to contact Micriµm to properly license +* its use in your product. We provide ALL the source code for your convenience and to help you experience +* uC/OS-II. The fact that the source is provided does NOT mean that you can use it without paying a +* licensing fee. +********************************************************************************************************* +*/ + +#ifndef OS_MASTER_FILE +#include +#endif + +/*$PAGE*/ +/* +********************************************************************************************************* +* CHANGE PRIORITY OF A TASK +* +* Description: This function allows you to change the priority of a task dynamically. Note that the new +* priority MUST be available. +* +* Arguments : oldp is the old priority +* +* newp is the new priority +* +* Returns : OS_ERR_NONE is the call was successful +* OS_ERR_PRIO_INVALID if the priority you specify is higher that the maximum allowed +* (i.e. >= OS_LOWEST_PRIO) +* OS_ERR_PRIO_EXIST if the new priority already exist. +* OS_ERR_PRIO there is no task with the specified OLD priority (i.e. the OLD task does +* not exist. +* OS_ERR_TASK_NOT_EXIST if the task is assigned to a Mutex PIP. +********************************************************************************************************* +*/ + +#if OS_TASK_CHANGE_PRIO_EN > 0 +INT8U OSTaskChangePrio (INT8U oldprio, INT8U newprio) +{ +#if (OS_EVENT_EN) + OS_EVENT *pevent; +#if (OS_EVENT_MULTI_EN > 0) + OS_EVENT **pevents; +#endif +#endif + OS_TCB *ptcb; + INT8U y_new; + INT8U x_new; + INT8U y_old; +#if OS_LOWEST_PRIO <= 63 + INT8U bity_new; + INT8U bitx_new; + INT8U bity_old; + INT8U bitx_old; +#else + INT16U bity_new; + INT16U bitx_new; + INT16U bity_old; + INT16U bitx_old; +#endif +#if OS_CRITICAL_METHOD == 3 + OS_CPU_SR cpu_sr = 0; /* Storage for CPU status register */ +#endif + + +/*$PAGE*/ +#if OS_ARG_CHK_EN > 0 + if (oldprio >= OS_LOWEST_PRIO) { + if (oldprio != OS_PRIO_SELF) { + return (OS_ERR_PRIO_INVALID); + } + } + if (newprio >= OS_LOWEST_PRIO) { + return (OS_ERR_PRIO_INVALID); + } +#endif + OS_ENTER_CRITICAL(); + if (OSTCBPrioTbl[newprio] != (OS_TCB *)0) { /* New priority must not already exist */ + OS_EXIT_CRITICAL(); + return (OS_ERR_PRIO_EXIST); + } + if (oldprio == OS_PRIO_SELF) { /* See if changing self */ + oldprio = OSTCBCur->OSTCBPrio; /* Yes, get priority */ + } + ptcb = OSTCBPrioTbl[oldprio]; + if (ptcb == (OS_TCB *)0) { /* Does task to change exist? */ + OS_EXIT_CRITICAL(); /* No, can't change its priority! */ + return (OS_ERR_PRIO); + } + if (ptcb == OS_TCB_RESERVED) { /* Is task assigned to Mutex */ + OS_EXIT_CRITICAL(); /* No, can't change its priority! */ + return (OS_ERR_TASK_NOT_EXIST); + } +#if OS_LOWEST_PRIO <= 63 + y_new = (INT8U)(newprio >> 3); /* Yes, compute new TCB fields */ + x_new = (INT8U)(newprio & 0x07); + bity_new = (INT8U)(1 << y_new); + bitx_new = (INT8U)(1 << x_new); +#else + y_new = (INT8U)((newprio >> 4) & 0x0F); + x_new = (INT8U)( newprio & 0x0F); + bity_new = (INT16U)(1 << y_new); + bitx_new = (INT16U)(1 << x_new); +#endif + + OSTCBPrioTbl[oldprio] = (OS_TCB *)0; /* Remove TCB from old priority */ + OSTCBPrioTbl[newprio] = ptcb; /* Place pointer to TCB @ new priority */ + y_old = ptcb->OSTCBY; + bity_old = ptcb->OSTCBBitY; + bitx_old = ptcb->OSTCBBitX; + if ((OSRdyTbl[y_old] & bitx_old) != 0) { /* If task is ready make it not */ + OSRdyTbl[y_old] &= ~bitx_old; + if (OSRdyTbl[y_old] == 0) { + OSRdyGrp &= ~bity_old; + } + OSRdyGrp |= bity_new; /* Make new priority ready to run */ + OSRdyTbl[y_new] |= bitx_new; + } + +#if (OS_EVENT_EN) + pevent = ptcb->OSTCBEventPtr; + if (pevent != (OS_EVENT *)0) { + pevent->OSEventTbl[y_old] &= ~bitx_old; /* Remove old task prio from wait list */ + if (pevent->OSEventTbl[y_old] == 0) { + pevent->OSEventGrp &= ~bity_old; + } + pevent->OSEventGrp |= bity_new; /* Add new task prio to wait list */ + pevent->OSEventTbl[y_new] |= bitx_new; + } +#if (OS_EVENT_MULTI_EN > 0) + if (ptcb->OSTCBEventMultiPtr != (OS_EVENT **)0) { + pevents = ptcb->OSTCBEventMultiPtr; + pevent = *pevents; + while (pevent != (OS_EVENT *)0) { + pevent->OSEventTbl[y_old] &= ~bitx_old; /* Remove old task prio from wait lists */ + if (pevent->OSEventTbl[y_old] == 0) { + pevent->OSEventGrp &= ~bity_old; + } + pevent->OSEventGrp |= bity_new; /* Add new task prio to wait lists */ + pevent->OSEventTbl[y_new] |= bitx_new; + pevents++; + pevent = *pevents; + } + } +#endif +#endif + + ptcb->OSTCBPrio = newprio; /* Set new task priority */ + ptcb->OSTCBY = y_new; + ptcb->OSTCBX = x_new; + ptcb->OSTCBBitY = bity_new; + ptcb->OSTCBBitX = bitx_new; + OS_EXIT_CRITICAL(); + if (OSRunning == OS_TRUE) { + OS_Sched(); /* Find new highest priority task */ + } + return (OS_ERR_NONE); +} +#endif +/*$PAGE*/ +/* +********************************************************************************************************* +* CREATE A TASK +* +* Description: This function is used to have uC/OS-II manage the execution of a task. Tasks can either +* be created prior to the start of multitasking or by a running task. A task cannot be +* created by an ISR. +* +* Arguments : task is a pointer to the task's code +* +* p_arg is a pointer to an optional data area which can be used to pass parameters to +* the task when the task first executes. Where the task is concerned it thinks +* it was invoked and passed the argument 'p_arg' as follows: +* +* void Task (void *p_arg) +* { +* for (;;) { +* Task code; +* } +* } +* +* ptos is a pointer to the task's top of stack. If the configuration constant +* OS_STK_GROWTH is set to 1, the stack is assumed to grow downward (i.e. from high +* memory to low memory). 'pstk' will thus point to the highest (valid) memory +* location of the stack. If OS_STK_GROWTH is set to 0, 'pstk' will point to the +* lowest memory location of the stack and the stack will grow with increasing +* memory locations. +* +* prio is the task's priority. A unique priority MUST be assigned to each task and the +* lower the number, the higher the priority. +* +* Returns : OS_ERR_NONE if the function was successful. +* OS_PRIO_EXIT if the task priority already exist +* (each task MUST have a unique priority). +* OS_ERR_PRIO_INVALID if the priority you specify is higher that the maximum allowed +* (i.e. >= OS_LOWEST_PRIO) +* OS_ERR_TASK_CREATE_ISR if you tried to create a task from an ISR. +********************************************************************************************************* +*/ + +#if OS_TASK_CREATE_EN > 0 +INT8U OSTaskCreate (void (*task)(void *p_arg), void *p_arg, OS_STK *ptos, INT8U prio) +{ + OS_STK *psp; + INT8U err; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (prio > OS_LOWEST_PRIO) { /* Make sure priority is within allowable range */ + return (OS_ERR_PRIO_INVALID); + } +#endif + OS_ENTER_CRITICAL(); + if (OSIntNesting > 0) { /* Make sure we don't create the task from within an ISR */ + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_CREATE_ISR); + } + if (OSTCBPrioTbl[prio] == (OS_TCB *)0) { /* Make sure task doesn't already exist at this priority */ + OSTCBPrioTbl[prio] = OS_TCB_RESERVED;/* Reserve the priority to prevent others from doing ... */ + /* ... the same thing until task is created. */ + OS_EXIT_CRITICAL(); + psp = OSTaskStkInit(task, p_arg, ptos, 0); /* Initialize the task's stack */ + err = OS_TCBInit(prio, psp, (OS_STK *)0, 0, 0, (void *)0, 0); + if (err == OS_ERR_NONE) { + if (OSRunning == OS_TRUE) { /* Find highest priority task if multitasking has started */ + OS_Sched(); + } + } else { + OS_ENTER_CRITICAL(); + OSTCBPrioTbl[prio] = (OS_TCB *)0;/* Make this priority available to others */ + OS_EXIT_CRITICAL(); + } + return (err); + } + OS_EXIT_CRITICAL(); + return (OS_ERR_PRIO_EXIST); +} +#endif +/*$PAGE*/ +/* +********************************************************************************************************* +* CREATE A TASK (Extended Version) +* +* Description: This function is used to have uC/OS-II manage the execution of a task. Tasks can either +* be created prior to the start of multitasking or by a running task. A task cannot be +* created by an ISR. This function is similar to OSTaskCreate() except that it allows +* additional information about a task to be specified. +* +* Arguments : task is a pointer to the task's code +* +* p_arg is a pointer to an optional data area which can be used to pass parameters to +* the task when the task first executes. Where the task is concerned it thinks +* it was invoked and passed the argument 'p_arg' as follows: +* +* void Task (void *p_arg) +* { +* for (;;) { +* Task code; +* } +* } +* +* ptos is a pointer to the task's top of stack. If the configuration constant +* OS_STK_GROWTH is set to 1, the stack is assumed to grow downward (i.e. from high +* memory to low memory). 'ptos' will thus point to the highest (valid) memory +* location of the stack. If OS_STK_GROWTH is set to 0, 'ptos' will point to the +* lowest memory location of the stack and the stack will grow with increasing +* memory locations. 'ptos' MUST point to a valid 'free' data item. +* +* prio is the task's priority. A unique priority MUST be assigned to each task and the +* lower the number, the higher the priority. +* +* id is the task's ID (0..65535) +* +* pbos is a pointer to the task's bottom of stack. If the configuration constant +* OS_STK_GROWTH is set to 1, the stack is assumed to grow downward (i.e. from high +* memory to low memory). 'pbos' will thus point to the LOWEST (valid) memory +* location of the stack. If OS_STK_GROWTH is set to 0, 'pbos' will point to the +* HIGHEST memory location of the stack and the stack will grow with increasing +* memory locations. 'pbos' MUST point to a valid 'free' data item. +* +* stk_size is the size of the stack in number of elements. If OS_STK is set to INT8U, +* 'stk_size' corresponds to the number of bytes available. If OS_STK is set to +* INT16U, 'stk_size' contains the number of 16-bit entries available. Finally, if +* OS_STK is set to INT32U, 'stk_size' contains the number of 32-bit entries +* available on the stack. +* +* pext is a pointer to a user supplied memory location which is used as a TCB extension. +* For example, this user memory can hold the contents of floating-point registers +* during a context switch, the time each task takes to execute, the number of times +* the task has been switched-in, etc. +* +* opt contains additional information (or options) about the behavior of the task. The +* LOWER 8-bits are reserved by uC/OS-II while the upper 8 bits can be application +* specific. See OS_TASK_OPT_??? in uCOS-II.H. Current choices are: +* +* OS_TASK_OPT_STK_CHK Stack checking to be allowed for the task +* OS_TASK_OPT_STK_CLR Clear the stack when the task is created +* OS_TASK_OPT_SAVE_FP If the CPU has floating-point registers, save them +* during a context switch. +* +* Returns : OS_ERR_NONE if the function was successful. +* OS_PRIO_EXIT if the task priority already exist +* (each task MUST have a unique priority). +* OS_ERR_PRIO_INVALID if the priority you specify is higher that the maximum allowed +* (i.e. > OS_LOWEST_PRIO) +* OS_ERR_TASK_CREATE_ISR if you tried to create a task from an ISR. +********************************************************************************************************* +*/ +/*$PAGE*/ +#if OS_TASK_CREATE_EXT_EN > 0 +INT8U OSTaskCreateExt (void (*task)(void *p_arg), + void *p_arg, + OS_STK *ptos, + INT8U prio, + INT16U id, + OS_STK *pbos, + INT32U stk_size, + void *pext, + INT16U opt) +{ + OS_STK *psp; + INT8U err; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (prio > OS_LOWEST_PRIO) { /* Make sure priority is within allowable range */ + return (OS_ERR_PRIO_INVALID); + } +#endif + OS_ENTER_CRITICAL(); + if (OSIntNesting > 0) { /* Make sure we don't create the task from within an ISR */ + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_CREATE_ISR); + } + if (OSTCBPrioTbl[prio] == (OS_TCB *)0) { /* Make sure task doesn't already exist at this priority */ + OSTCBPrioTbl[prio] = OS_TCB_RESERVED;/* Reserve the priority to prevent others from doing ... */ + /* ... the same thing until task is created. */ + OS_EXIT_CRITICAL(); + +#if (OS_TASK_STAT_STK_CHK_EN > 0) + OS_TaskStkClr(pbos, stk_size, opt); /* Clear the task stack (if needed) */ +#endif + + psp = OSTaskStkInit(task, p_arg, ptos, opt); /* Initialize the task's stack */ + err = OS_TCBInit(prio, psp, pbos, id, stk_size, pext, opt); + if (err == OS_ERR_NONE) { + if (OSRunning == OS_TRUE) { /* Find HPT if multitasking has started */ + OS_Sched(); + } + } else { + OS_ENTER_CRITICAL(); + OSTCBPrioTbl[prio] = (OS_TCB *)0; /* Make this priority avail. to others */ + OS_EXIT_CRITICAL(); + } + return (err); + } + OS_EXIT_CRITICAL(); + return (OS_ERR_PRIO_EXIST); +} +#endif +/*$PAGE*/ +/* +********************************************************************************************************* +* DELETE A TASK +* +* Description: This function allows you to delete a task. The calling task can delete itself by +* its own priority number. The deleted task is returned to the dormant state and can be +* re-activated by creating the deleted task again. +* +* Arguments : prio is the priority of the task to delete. Note that you can explicitely delete +* the current task without knowing its priority level by setting 'prio' to +* OS_PRIO_SELF. +* +* Returns : OS_ERR_NONE if the call is successful +* OS_ERR_TASK_DEL_IDLE if you attempted to delete uC/OS-II's idle task +* OS_ERR_PRIO_INVALID if the priority you specify is higher that the maximum allowed +* (i.e. >= OS_LOWEST_PRIO) or, you have not specified OS_PRIO_SELF. +* OS_ERR_TASK_DEL if the task is assigned to a Mutex PIP. +* OS_ERR_TASK_NOT_EXIST if the task you want to delete does not exist. +* OS_ERR_TASK_DEL_ISR if you tried to delete a task from an ISR +* +* Notes : 1) To reduce interrupt latency, OSTaskDel() 'disables' the task: +* a) by making it not ready +* b) by removing it from any wait lists +* c) by preventing OSTimeTick() from making the task ready to run. +* The task can then be 'unlinked' from the miscellaneous structures in uC/OS-II. +* 2) The function OS_Dummy() is called after OS_EXIT_CRITICAL() because, on most processors, +* the next instruction following the enable interrupt instruction is ignored. +* 3) An ISR cannot delete a task. +* 4) The lock nesting counter is incremented because, for a brief instant, if the current +* task is being deleted, the current task would not be able to be rescheduled because it +* is removed from the ready list. Incrementing the nesting counter prevents another task +* from being schedule. This means that an ISR would return to the current task which is +* being deleted. The rest of the deletion would thus be able to be completed. +********************************************************************************************************* +*/ + +#if OS_TASK_DEL_EN > 0 +INT8U OSTaskDel (INT8U prio) +{ +#if (OS_FLAG_EN > 0) && (OS_MAX_FLAGS > 0) + OS_FLAG_NODE *pnode; +#endif + OS_TCB *ptcb; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + + if (OSIntNesting > 0) { /* See if trying to delete from ISR */ + return (OS_ERR_TASK_DEL_ISR); + } + if (prio == OS_TASK_IDLE_PRIO) { /* Not allowed to delete idle task */ + return (OS_ERR_TASK_DEL_IDLE); + } +#if OS_ARG_CHK_EN > 0 + if (prio >= OS_LOWEST_PRIO) { /* Task priority valid ? */ + if (prio != OS_PRIO_SELF) { + return (OS_ERR_PRIO_INVALID); + } + } +#endif + +/*$PAGE*/ + OS_ENTER_CRITICAL(); + if (prio == OS_PRIO_SELF) { /* See if requesting to delete self */ + prio = OSTCBCur->OSTCBPrio; /* Set priority to delete to current */ + } + ptcb = OSTCBPrioTbl[prio]; + if (ptcb == (OS_TCB *)0) { /* Task to delete must exist */ + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_NOT_EXIST); + } + if (ptcb == OS_TCB_RESERVED) { /* Must not be assigned to Mutex */ + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_DEL); + } + + OSRdyTbl[ptcb->OSTCBY] &= ~ptcb->OSTCBBitX; + if (OSRdyTbl[ptcb->OSTCBY] == 0) { /* Make task not ready */ + OSRdyGrp &= ~ptcb->OSTCBBitY; + } + +#if (OS_EVENT_EN) + if (ptcb->OSTCBEventPtr != (OS_EVENT *)0) { + OS_EventTaskRemove(ptcb, ptcb->OSTCBEventPtr); /* Remove this task from any event wait list */ + } +#if (OS_EVENT_MULTI_EN > 0) + if (ptcb->OSTCBEventMultiPtr != (OS_EVENT **)0) { /* Remove this task from any events' wait lists*/ + OS_EventTaskRemoveMulti(ptcb, ptcb->OSTCBEventMultiPtr); + } +#endif +#endif + +#if (OS_FLAG_EN > 0) && (OS_MAX_FLAGS > 0) + pnode = ptcb->OSTCBFlagNode; + if (pnode != (OS_FLAG_NODE *)0) { /* If task is waiting on event flag */ + OS_FlagUnlink(pnode); /* Remove from wait list */ + } +#endif + + ptcb->OSTCBDly = 0; /* Prevent OSTimeTick() from updating */ + ptcb->OSTCBStat = OS_STAT_RDY; /* Prevent task from being resumed */ + ptcb->OSTCBStatPend = OS_STAT_PEND_OK; + if (OSLockNesting < 255u) { /* Make sure we don't context switch */ + OSLockNesting++; + } + OS_EXIT_CRITICAL(); /* Enabling INT. ignores next instruc. */ + OS_Dummy(); /* ... Dummy ensures that INTs will be */ + OS_ENTER_CRITICAL(); /* ... disabled HERE! */ + if (OSLockNesting > 0) { /* Remove context switch lock */ + OSLockNesting--; + } + OSTaskDelHook(ptcb); /* Call user defined hook */ + OSTaskCtr--; /* One less task being managed */ + OSTCBPrioTbl[prio] = (OS_TCB *)0; /* Clear old priority entry */ + if (ptcb->OSTCBPrev == (OS_TCB *)0) { /* Remove from TCB chain */ + ptcb->OSTCBNext->OSTCBPrev = (OS_TCB *)0; + OSTCBList = ptcb->OSTCBNext; + } else { + ptcb->OSTCBPrev->OSTCBNext = ptcb->OSTCBNext; + ptcb->OSTCBNext->OSTCBPrev = ptcb->OSTCBPrev; + } + ptcb->OSTCBNext = OSTCBFreeList; /* Return TCB to free TCB list */ + OSTCBFreeList = ptcb; +#if OS_TASK_NAME_SIZE > 1 + ptcb->OSTCBTaskName[0] = '?'; /* Unknown name */ + ptcb->OSTCBTaskName[1] = OS_ASCII_NUL; +#endif + OS_EXIT_CRITICAL(); + if (OSRunning == OS_TRUE) { + OS_Sched(); /* Find new highest priority task */ + } + return (OS_ERR_NONE); +} +#endif +/*$PAGE*/ +/* +********************************************************************************************************* +* REQUEST THAT A TASK DELETE ITSELF +* +* Description: This function is used to: +* a) notify a task to delete itself. +* b) to see if a task requested that the current task delete itself. +* This function is a little tricky to understand. Basically, you have a task that needs +* to be deleted however, this task has resources that it has allocated (memory buffers, +* semaphores, mailboxes, queues etc.). The task cannot be deleted otherwise these +* resources would not be freed. The requesting task calls OSTaskDelReq() to indicate that +* the task needs to be deleted. Deleting of the task is however, deferred to the task to +* be deleted. For example, suppose that task #10 needs to be deleted. The requesting task +* example, task #5, would call OSTaskDelReq(10). When task #10 gets to execute, it calls +* this function by specifying OS_PRIO_SELF and monitors the returned value. If the return +* value is OS_ERR_TASK_DEL_REQ, another task requested a task delete. Task #10 would look like +* this: +* +* void Task(void *p_arg) +* { +* . +* . +* while (1) { +* OSTimeDly(1); +* if (OSTaskDelReq(OS_PRIO_SELF) == OS_ERR_TASK_DEL_REQ) { +* Release any owned resources; +* De-allocate any dynamic memory; +* OSTaskDel(OS_PRIO_SELF); +* } +* } +* } +* +* Arguments : prio is the priority of the task to request the delete from +* +* Returns : OS_ERR_NONE if the task exist and the request has been registered +* OS_ERR_TASK_NOT_EXIST if the task has been deleted. This allows the caller to know whether +* the request has been executed. +* OS_ERR_TASK_DEL if the task is assigned to a Mutex. +* OS_ERR_TASK_DEL_IDLE if you requested to delete uC/OS-II's idle task +* OS_ERR_PRIO_INVALID if the priority you specify is higher that the maximum allowed +* (i.e. >= OS_LOWEST_PRIO) or, you have not specified OS_PRIO_SELF. +* OS_ERR_TASK_DEL_REQ if a task (possibly another task) requested that the running task be +* deleted. +********************************************************************************************************* +*/ +/*$PAGE*/ +#if OS_TASK_DEL_EN > 0 +INT8U OSTaskDelReq (INT8U prio) +{ + INT8U stat; + OS_TCB *ptcb; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + + if (prio == OS_TASK_IDLE_PRIO) { /* Not allowed to delete idle task */ + return (OS_ERR_TASK_DEL_IDLE); + } +#if OS_ARG_CHK_EN > 0 + if (prio >= OS_LOWEST_PRIO) { /* Task priority valid ? */ + if (prio != OS_PRIO_SELF) { + return (OS_ERR_PRIO_INVALID); + } + } +#endif + if (prio == OS_PRIO_SELF) { /* See if a task is requesting to ... */ + OS_ENTER_CRITICAL(); /* ... this task to delete itself */ + stat = OSTCBCur->OSTCBDelReq; /* Return request status to caller */ + OS_EXIT_CRITICAL(); + return (stat); + } + OS_ENTER_CRITICAL(); + ptcb = OSTCBPrioTbl[prio]; + if (ptcb == (OS_TCB *)0) { /* Task to delete must exist */ + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_NOT_EXIST); /* Task must already be deleted */ + } + if (ptcb == OS_TCB_RESERVED) { /* Must NOT be assigned to a Mutex */ + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_DEL); + } + ptcb->OSTCBDelReq = OS_ERR_TASK_DEL_REQ; /* Set flag indicating task to be DEL. */ + OS_EXIT_CRITICAL(); + return (OS_ERR_NONE); +} +#endif +/*$PAGE*/ +/* +********************************************************************************************************* +* GET THE NAME OF A TASK +* +* Description: This function is called to obtain the name of a task. +* +* Arguments : prio is the priority of the task that you want to obtain the name from. +* +* pname is a pointer to an ASCII string that will receive the name of the task. The +* string must be able to hold at least OS_TASK_NAME_SIZE characters. +* +* perr is a pointer to an error code that can contain one of the following values: +* +* OS_ERR_NONE if the requested task is resumed +* OS_ERR_TASK_NOT_EXIST if the task has not been created or is assigned to a Mutex +* OS_ERR_PRIO_INVALID if you specified an invalid priority: +* A higher value than the idle task or not OS_PRIO_SELF. +* OS_ERR_PNAME_NULL You passed a NULL pointer for 'pname' +* OS_ERR_NAME_GET_ISR You called this function from an ISR +* +* +* Returns : The length of the string or 0 if the task does not exist. +********************************************************************************************************* +*/ + +#if OS_TASK_NAME_SIZE > 1 +INT8U OSTaskNameGet (INT8U prio, INT8U *pname, INT8U *perr) +{ + OS_TCB *ptcb; + INT8U len; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + return (0); + } + if (prio > OS_LOWEST_PRIO) { /* Task priority valid ? */ + if (prio != OS_PRIO_SELF) { + *perr = OS_ERR_PRIO_INVALID; /* No */ + return (0); + } + } + if (pname == (INT8U *)0) { /* Is 'pname' a NULL pointer? */ + *perr = OS_ERR_PNAME_NULL; /* Yes */ + return (0); + } +#endif + if (OSIntNesting > 0) { /* See if trying to call from an ISR */ + *perr = OS_ERR_NAME_GET_ISR; + return (0); + } + OS_ENTER_CRITICAL(); + if (prio == OS_PRIO_SELF) { /* See if caller desires it's own name */ + prio = OSTCBCur->OSTCBPrio; + } + ptcb = OSTCBPrioTbl[prio]; + if (ptcb == (OS_TCB *)0) { /* Does task exist? */ + OS_EXIT_CRITICAL(); /* No */ + *perr = OS_ERR_TASK_NOT_EXIST; + return (0); + } + if (ptcb == OS_TCB_RESERVED) { /* Task assigned to a Mutex? */ + OS_EXIT_CRITICAL(); /* Yes */ + *perr = OS_ERR_TASK_NOT_EXIST; + return (0); + } + len = OS_StrCopy(pname, ptcb->OSTCBTaskName); /* Yes, copy name from TCB */ + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; + return (len); +} +#endif + +/*$PAGE*/ +/* +********************************************************************************************************* +* ASSIGN A NAME TO A TASK +* +* Description: This function is used to set the name of a task. +* +* Arguments : prio is the priority of the task that you want the assign a name to. +* +* pname is a pointer to an ASCII string that contains the name of the task. The ASCII +* string must be NUL terminated. +* +* perr is a pointer to an error code that can contain one of the following values: +* +* OS_ERR_NONE if the requested task is resumed +* OS_ERR_TASK_NOT_EXIST if the task has not been created or is assigned to a Mutex +* OS_ERR_TASK_NAME_TOO_LONG if the name you are giving to the task exceeds the +* storage capacity of a task name as specified by +* OS_TASK_NAME_SIZE. +* OS_ERR_PNAME_NULL You passed a NULL pointer for 'pname' +* OS_ERR_PRIO_INVALID if you specified an invalid priority: +* A higher value than the idle task or not OS_PRIO_SELF. +* OS_ERR_NAME_SET_ISR if you called this function from an ISR +* +* Returns : None +********************************************************************************************************* +*/ +#if OS_TASK_NAME_SIZE > 1 +void OSTaskNameSet (INT8U prio, INT8U *pname, INT8U *perr) +{ + INT8U len; + OS_TCB *ptcb; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate 'perr' */ + return; + } + if (prio > OS_LOWEST_PRIO) { /* Task priority valid ? */ + if (prio != OS_PRIO_SELF) { + *perr = OS_ERR_PRIO_INVALID; /* No */ + return; + } + } + if (pname == (INT8U *)0) { /* Is 'pname' a NULL pointer? */ + *perr = OS_ERR_PNAME_NULL; /* Yes */ + return; + } +#endif + if (OSIntNesting > 0) { /* See if trying to call from an ISR */ + *perr = OS_ERR_NAME_SET_ISR; + return; + } + OS_ENTER_CRITICAL(); + if (prio == OS_PRIO_SELF) { /* See if caller desires to set it's own name */ + prio = OSTCBCur->OSTCBPrio; + } + ptcb = OSTCBPrioTbl[prio]; + if (ptcb == (OS_TCB *)0) { /* Does task exist? */ + OS_EXIT_CRITICAL(); /* No */ + *perr = OS_ERR_TASK_NOT_EXIST; + return; + } + if (ptcb == OS_TCB_RESERVED) { /* Task assigned to a Mutex? */ + OS_EXIT_CRITICAL(); /* Yes */ + *perr = OS_ERR_TASK_NOT_EXIST; + return; + } + len = OS_StrLen(pname); /* Yes, Can we fit the string in the TCB? */ + if (len > (OS_TASK_NAME_SIZE - 1)) { /* No */ + OS_EXIT_CRITICAL(); + *perr = OS_ERR_TASK_NAME_TOO_LONG; + return; + } + (void)OS_StrCopy(ptcb->OSTCBTaskName, pname); /* Yes, copy to TCB */ + OS_EXIT_CRITICAL(); + *perr = OS_ERR_NONE; +} +#endif + +/*$PAGE*/ +/* +********************************************************************************************************* +* RESUME A SUSPENDED TASK +* +* Description: This function is called to resume a previously suspended task. This is the only call that +* will remove an explicit task suspension. +* +* Arguments : prio is the priority of the task to resume. +* +* Returns : OS_ERR_NONE if the requested task is resumed +* OS_ERR_PRIO_INVALID if the priority you specify is higher that the maximum allowed +* (i.e. >= OS_LOWEST_PRIO) +* OS_ERR_TASK_RESUME_PRIO if the task to resume does not exist +* OS_ERR_TASK_NOT_EXIST if the task is assigned to a Mutex PIP +* OS_ERR_TASK_NOT_SUSPENDED if the task to resume has not been suspended +********************************************************************************************************* +*/ + +#if OS_TASK_SUSPEND_EN > 0 +INT8U OSTaskResume (INT8U prio) +{ + OS_TCB *ptcb; +#if OS_CRITICAL_METHOD == 3 /* Storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (prio >= OS_LOWEST_PRIO) { /* Make sure task priority is valid */ + return (OS_ERR_PRIO_INVALID); + } +#endif + OS_ENTER_CRITICAL(); + ptcb = OSTCBPrioTbl[prio]; + if (ptcb == (OS_TCB *)0) { /* Task to suspend must exist */ + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_RESUME_PRIO); + } + if (ptcb == OS_TCB_RESERVED) { /* See if assigned to Mutex */ + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_NOT_EXIST); + } + if ((ptcb->OSTCBStat & OS_STAT_SUSPEND) != OS_STAT_RDY) { /* Task must be suspended */ + ptcb->OSTCBStat &= ~(INT8U)OS_STAT_SUSPEND; /* Remove suspension */ + if (ptcb->OSTCBStat == OS_STAT_RDY) { /* See if task is now ready */ + if (ptcb->OSTCBDly == 0) { + OSRdyGrp |= ptcb->OSTCBBitY; /* Yes, Make task ready to run */ + OSRdyTbl[ptcb->OSTCBY] |= ptcb->OSTCBBitX; + OS_EXIT_CRITICAL(); + if (OSRunning == OS_TRUE) { + OS_Sched(); /* Find new highest priority task */ + } + } else { + OS_EXIT_CRITICAL(); + } + } else { /* Must be pending on event */ + OS_EXIT_CRITICAL(); + } + return (OS_ERR_NONE); + } + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_NOT_SUSPENDED); +} +#endif +/*$PAGE*/ +/* +********************************************************************************************************* +* STACK CHECKING +* +* Description: This function is called to check the amount of free memory left on the specified task's +* stack. +* +* Arguments : prio is the task priority +* +* p_stk_data is a pointer to a data structure of type OS_STK_DATA. +* +* Returns : OS_ERR_NONE upon success +* OS_ERR_PRIO_INVALID if the priority you specify is higher that the maximum allowed +* (i.e. > OS_LOWEST_PRIO) or, you have not specified OS_PRIO_SELF. +* OS_ERR_TASK_NOT_EXIST if the desired task has not been created or is assigned to a Mutex PIP +* OS_ERR_TASK_OPT if you did NOT specified OS_TASK_OPT_STK_CHK when the task was created +* OS_ERR_PDATA_NULL if 'p_stk_data' is a NULL pointer +********************************************************************************************************* +*/ +#if (OS_TASK_STAT_STK_CHK_EN > 0) && (OS_TASK_CREATE_EXT_EN > 0) +INT8U OSTaskStkChk (INT8U prio, OS_STK_DATA *p_stk_data) +{ + OS_TCB *ptcb; + OS_STK *pchk; + INT32U nfree; + INT32U size; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (prio > OS_LOWEST_PRIO) { /* Make sure task priority is valid */ + if (prio != OS_PRIO_SELF) { + return (OS_ERR_PRIO_INVALID); + } + } + if (p_stk_data == (OS_STK_DATA *)0) { /* Validate 'p_stk_data' */ + return (OS_ERR_PDATA_NULL); + } +#endif + p_stk_data->OSFree = 0; /* Assume failure, set to 0 size */ + p_stk_data->OSUsed = 0; + OS_ENTER_CRITICAL(); + if (prio == OS_PRIO_SELF) { /* See if check for SELF */ + prio = OSTCBCur->OSTCBPrio; + } + ptcb = OSTCBPrioTbl[prio]; + if (ptcb == (OS_TCB *)0) { /* Make sure task exist */ + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_NOT_EXIST); + } + if (ptcb == OS_TCB_RESERVED) { + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_NOT_EXIST); + } + if ((ptcb->OSTCBOpt & OS_TASK_OPT_STK_CHK) == 0) { /* Make sure stack checking option is set */ + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_OPT); + } + nfree = 0; + size = ptcb->OSTCBStkSize; + pchk = ptcb->OSTCBStkBottom; + OS_EXIT_CRITICAL(); +#if OS_STK_GROWTH == 1 + while (*pchk++ == (OS_STK)0) { /* Compute the number of zero entries on the stk */ + nfree++; + } +#else + while (*pchk-- == (OS_STK)0) { + nfree++; + } +#endif + p_stk_data->OSFree = nfree * sizeof(OS_STK); /* Compute number of free bytes on the stack */ + p_stk_data->OSUsed = (size - nfree) * sizeof(OS_STK); /* Compute number of bytes used on the stack */ + return (OS_ERR_NONE); +} +#endif +/*$PAGE*/ +/* +********************************************************************************************************* +* SUSPEND A TASK +* +* Description: This function is called to suspend a task. The task can be the calling task if the +* priority passed to OSTaskSuspend() is the priority of the calling task or OS_PRIO_SELF. +* +* Arguments : prio is the priority of the task to suspend. If you specify OS_PRIO_SELF, the +* calling task will suspend itself and rescheduling will occur. +* +* Returns : OS_ERR_NONE if the requested task is suspended +* OS_ERR_TASK_SUSPEND_IDLE if you attempted to suspend the idle task which is not allowed. +* OS_ERR_PRIO_INVALID if the priority you specify is higher that the maximum allowed +* (i.e. >= OS_LOWEST_PRIO) or, you have not specified OS_PRIO_SELF. +* OS_ERR_TASK_SUSPEND_PRIO if the task to suspend does not exist +* OS_ERR_TASK_NOT_EXITS if the task is assigned to a Mutex PIP +* +* Note : You should use this function with great care. If you suspend a task that is waiting for +* an event (i.e. a message, a semaphore, a queue ...) you will prevent this task from +* running when the event arrives. +********************************************************************************************************* +*/ + +#if OS_TASK_SUSPEND_EN > 0 +INT8U OSTaskSuspend (INT8U prio) +{ + BOOLEAN self; + OS_TCB *ptcb; + INT8U y; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (prio == OS_TASK_IDLE_PRIO) { /* Not allowed to suspend idle task */ + return (OS_ERR_TASK_SUSPEND_IDLE); + } + if (prio >= OS_LOWEST_PRIO) { /* Task priority valid ? */ + if (prio != OS_PRIO_SELF) { + return (OS_ERR_PRIO_INVALID); + } + } +#endif + OS_ENTER_CRITICAL(); + if (prio == OS_PRIO_SELF) { /* See if suspend SELF */ + prio = OSTCBCur->OSTCBPrio; + self = OS_TRUE; + } else if (prio == OSTCBCur->OSTCBPrio) { /* See if suspending self */ + self = OS_TRUE; + } else { + self = OS_FALSE; /* No suspending another task */ + } + ptcb = OSTCBPrioTbl[prio]; + if (ptcb == (OS_TCB *)0) { /* Task to suspend must exist */ + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_SUSPEND_PRIO); + } + if (ptcb == OS_TCB_RESERVED) { /* See if assigned to Mutex */ + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_NOT_EXIST); + } + y = ptcb->OSTCBY; + OSRdyTbl[y] &= ~ptcb->OSTCBBitX; /* Make task not ready */ + if (OSRdyTbl[y] == 0) { + OSRdyGrp &= ~ptcb->OSTCBBitY; + } + ptcb->OSTCBStat |= OS_STAT_SUSPEND; /* Status of task is 'SUSPENDED' */ + OS_EXIT_CRITICAL(); + if (self == OS_TRUE) { /* Context switch only if SELF */ + OS_Sched(); /* Find new highest priority task */ + } + return (OS_ERR_NONE); +} +#endif +/*$PAGE*/ +/* +********************************************************************************************************* +* QUERY A TASK +* +* Description: This function is called to obtain a copy of the desired task's TCB. +* +* Arguments : prio is the priority of the task to obtain information from. +* +* p_task_data is a pointer to where the desired task's OS_TCB will be stored. +* +* Returns : OS_ERR_NONE if the requested task is suspended +* OS_ERR_PRIO_INVALID if the priority you specify is higher that the maximum allowed +* (i.e. > OS_LOWEST_PRIO) or, you have not specified OS_PRIO_SELF. +* OS_ERR_PRIO if the desired task has not been created +* OS_ERR_TASK_NOT_EXIST if the task is assigned to a Mutex PIP +* OS_ERR_PDATA_NULL if 'p_task_data' is a NULL pointer +********************************************************************************************************* +*/ + +#if OS_TASK_QUERY_EN > 0 +INT8U OSTaskQuery (INT8U prio, OS_TCB *p_task_data) +{ + OS_TCB *ptcb; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + +#if OS_ARG_CHK_EN > 0 + if (prio > OS_LOWEST_PRIO) { /* Task priority valid ? */ + if (prio != OS_PRIO_SELF) { + return (OS_ERR_PRIO_INVALID); + } + } + if (p_task_data == (OS_TCB *)0) { /* Validate 'p_task_data' */ + return (OS_ERR_PDATA_NULL); + } +#endif + OS_ENTER_CRITICAL(); + if (prio == OS_PRIO_SELF) { /* See if suspend SELF */ + prio = OSTCBCur->OSTCBPrio; + } + ptcb = OSTCBPrioTbl[prio]; + if (ptcb == (OS_TCB *)0) { /* Task to query must exist */ + OS_EXIT_CRITICAL(); + return (OS_ERR_PRIO); + } + if (ptcb == OS_TCB_RESERVED) { /* Task to query must not be assigned to a Mutex */ + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_NOT_EXIST); + } + /* Copy TCB into user storage area */ + OS_MemCopy((INT8U *)p_task_data, (INT8U *)ptcb, sizeof(OS_TCB)); + OS_EXIT_CRITICAL(); + return (OS_ERR_NONE); +} +#endif +/*$PAGE*/ +/* +********************************************************************************************************* +* CLEAR TASK STACK +* +* Description: This function is used to clear the stack of a task (i.e. write all zeros) +* +* Arguments : pbos is a pointer to the task's bottom of stack. If the configuration constant +* OS_STK_GROWTH is set to 1, the stack is assumed to grow downward (i.e. from high +* memory to low memory). 'pbos' will thus point to the lowest (valid) memory +* location of the stack. If OS_STK_GROWTH is set to 0, 'pbos' will point to the +* highest memory location of the stack and the stack will grow with increasing +* memory locations. 'pbos' MUST point to a valid 'free' data item. +* +* size is the number of 'stack elements' to clear. +* +* opt contains additional information (or options) about the behavior of the task. The +* LOWER 8-bits are reserved by uC/OS-II while the upper 8 bits can be application +* specific. See OS_TASK_OPT_??? in uCOS-II.H. +* +* Returns : none +********************************************************************************************************* +*/ +#if (OS_TASK_STAT_STK_CHK_EN > 0) && (OS_TASK_CREATE_EXT_EN > 0) +void OS_TaskStkClr (OS_STK *pbos, INT32U size, INT16U opt) +{ + if ((opt & OS_TASK_OPT_STK_CHK) != 0x0000) { /* See if stack checking has been enabled */ + if ((opt & OS_TASK_OPT_STK_CLR) != 0x0000) { /* See if stack needs to be cleared */ +#if OS_STK_GROWTH == 1 + while (size > 0) { /* Stack grows from HIGH to LOW memory */ + size--; + *pbos++ = (OS_STK)0; /* Clear from bottom of stack and up! */ + } +#else + while (size > 0) { /* Stack grows from LOW to HIGH memory */ + size--; + *pbos-- = (OS_STK)0; /* Clear from bottom of stack and down */ + } +#endif + } + } +} + +#endif diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/UCOSII/src/os_time.c b/MCandWifiTestDE0/Software/MCTest_bsp/UCOSII/src/os_time.c new file mode 100644 index 00000000..f68d1e7e --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/UCOSII/src/os_time.c @@ -0,0 +1,268 @@ +/* +********************************************************************************************************* +* uC/OS-II +* The Real-Time Kernel +* TIME MANAGEMENT +* +* (c) Copyright 1992-2007, Micrium, Weston, FL +* All Rights Reserved +* +* File : OS_TIME.C +* By : Jean J. Labrosse +* Version : V2.86 +* +* LICENSING TERMS: +* --------------- +* uC/OS-II is provided in source form for FREE evaluation, for educational use or for peaceful research. +* If you plan on using uC/OS-II in a commercial product you need to contact Micriµm to properly license +* its use in your product. We provide ALL the source code for your convenience and to help you experience +* uC/OS-II. The fact that the source is provided does NOT mean that you can use it without paying a +* licensing fee. +********************************************************************************************************* +*/ + +#ifndef OS_MASTER_FILE +#include +#endif + +/* +********************************************************************************************************* +* DELAY TASK 'n' TICKS (n from 0 to 65535) +* +* Description: This function is called to delay execution of the currently running task until the +* specified number of system ticks expires. This, of course, directly equates to delaying +* the current task for some time to expire. No delay will result If the specified delay is +* 0. If the specified delay is greater than 0 then, a context switch will result. +* +* Arguments : ticks is the time delay that the task will be suspended in number of clock 'ticks'. +* Note that by specifying 0, the task will not be delayed. +* +* Returns : none +********************************************************************************************************* +*/ + +void OSTimeDly (INT16U ticks) +{ + INT8U y; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + + if (OSIntNesting > 0) { /* See if trying to call from an ISR */ + return; + } + if (ticks > 0) { /* 0 means no delay! */ + OS_ENTER_CRITICAL(); + y = OSTCBCur->OSTCBY; /* Delay current task */ + OSRdyTbl[y] &= ~OSTCBCur->OSTCBBitX; + if (OSRdyTbl[y] == 0) { + OSRdyGrp &= ~OSTCBCur->OSTCBBitY; + } + OSTCBCur->OSTCBDly = ticks; /* Load ticks in TCB */ + OS_EXIT_CRITICAL(); + OS_Sched(); /* Find next task to run! */ + } +} +/*$PAGE*/ +/* +********************************************************************************************************* +* DELAY TASK FOR SPECIFIED TIME +* +* Description: This function is called to delay execution of the currently running task until some time +* expires. This call allows you to specify the delay time in HOURS, MINUTES, SECONDS and +* MILLISECONDS instead of ticks. +* +* Arguments : hours specifies the number of hours that the task will be delayed (max. is 255) +* minutes specifies the number of minutes (max. 59) +* seconds specifies the number of seconds (max. 59) +* milli specifies the number of milliseconds (max. 999) +* +* Returns : OS_ERR_NONE +* OS_ERR_TIME_INVALID_MINUTES +* OS_ERR_TIME_INVALID_SECONDS +* OS_ERR_TIME_INVALID_MS +* OS_ERR_TIME_ZERO_DLY +* OS_ERR_TIME_DLY_ISR +* +* Note(s) : The resolution on the milliseconds depends on the tick rate. For example, you can't do +* a 10 mS delay if the ticker interrupts every 100 mS. In this case, the delay would be +* set to 0. The actual delay is rounded to the nearest tick. +********************************************************************************************************* +*/ + +#if OS_TIME_DLY_HMSM_EN > 0 +INT8U OSTimeDlyHMSM (INT8U hours, INT8U minutes, INT8U seconds, INT16U ms) +{ + INT32U ticks; + INT16U loops; + + + if (OSIntNesting > 0) { /* See if trying to call from an ISR */ + return (OS_ERR_TIME_DLY_ISR); + } +#if OS_ARG_CHK_EN > 0 + if (hours == 0) { + if (minutes == 0) { + if (seconds == 0) { + if (ms == 0) { + return (OS_ERR_TIME_ZERO_DLY); + } + } + } + } + if (minutes > 59) { + return (OS_ERR_TIME_INVALID_MINUTES); /* Validate arguments to be within range */ + } + if (seconds > 59) { + return (OS_ERR_TIME_INVALID_SECONDS); + } + if (ms > 999) { + return (OS_ERR_TIME_INVALID_MS); + } +#endif + /* Compute the total number of clock ticks required.. */ + /* .. (rounded to the nearest tick) */ + ticks = ((INT32U)hours * 3600L + (INT32U)minutes * 60L + (INT32U)seconds) * OS_TICKS_PER_SEC + + OS_TICKS_PER_SEC * ((INT32U)ms + 500L / OS_TICKS_PER_SEC) / 1000L; + loops = (INT16U)(ticks >> 16); /* Compute the integral number of 65536 tick delays */ + ticks = ticks & 0xFFFFL; /* Obtain the fractional number of ticks */ + OSTimeDly((INT16U)ticks); + while (loops > 0) { + OSTimeDly((INT16U)32768u); + OSTimeDly((INT16U)32768u); + loops--; + } + return (OS_ERR_NONE); +} +#endif +/*$PAGE*/ +/* +********************************************************************************************************* +* RESUME A DELAYED TASK +* +* Description: This function is used resume a task that has been delayed through a call to either +* OSTimeDly() or OSTimeDlyHMSM(). Note that you can call this function to resume a +* task that is waiting for an event with timeout. This would make the task look +* like a timeout occurred. +* +* Also, you cannot resume a task that has called OSTimeDlyHMSM() with a combined time that +* exceeds 65535 clock ticks. In other words, if the clock tick runs at 100 Hz then, you will +* not be able to resume a delayed task that called OSTimeDlyHMSM(0, 10, 55, 350) or higher: +* +* (10 Minutes * 60 + 55 Seconds + 0.35) * 100 ticks/second. +* +* Arguments : prio specifies the priority of the task to resume +* +* Returns : OS_ERR_NONE Task has been resumed +* OS_ERR_PRIO_INVALID if the priority you specify is higher that the maximum allowed +* (i.e. >= OS_LOWEST_PRIO) +* OS_ERR_TIME_NOT_DLY Task is not waiting for time to expire +* OS_ERR_TASK_NOT_EXIST The desired task has not been created or has been assigned to a Mutex. +********************************************************************************************************* +*/ + +#if OS_TIME_DLY_RESUME_EN > 0 +INT8U OSTimeDlyResume (INT8U prio) +{ + OS_TCB *ptcb; +#if OS_CRITICAL_METHOD == 3 /* Storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + + if (prio >= OS_LOWEST_PRIO) { + return (OS_ERR_PRIO_INVALID); + } + OS_ENTER_CRITICAL(); + ptcb = OSTCBPrioTbl[prio]; /* Make sure that task exist */ + if (ptcb == (OS_TCB *)0) { + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_NOT_EXIST); /* The task does not exist */ + } + if (ptcb == OS_TCB_RESERVED) { + OS_EXIT_CRITICAL(); + return (OS_ERR_TASK_NOT_EXIST); /* The task does not exist */ + } + if (ptcb->OSTCBDly == 0) { /* See if task is delayed */ + OS_EXIT_CRITICAL(); + return (OS_ERR_TIME_NOT_DLY); /* Indicate that task was not delayed */ + } + + ptcb->OSTCBDly = 0; /* Clear the time delay */ + if ((ptcb->OSTCBStat & OS_STAT_PEND_ANY) != OS_STAT_RDY) { + ptcb->OSTCBStat &= ~OS_STAT_PEND_ANY; /* Yes, Clear status flag */ + ptcb->OSTCBStatPend = OS_STAT_PEND_TO; /* Indicate PEND timeout */ + } else { + ptcb->OSTCBStatPend = OS_STAT_PEND_OK; + } + if ((ptcb->OSTCBStat & OS_STAT_SUSPEND) == OS_STAT_RDY) { /* Is task suspended? */ + OSRdyGrp |= ptcb->OSTCBBitY; /* No, Make ready */ + OSRdyTbl[ptcb->OSTCBY] |= ptcb->OSTCBBitX; + OS_EXIT_CRITICAL(); + OS_Sched(); /* See if this is new highest priority */ + } else { + OS_EXIT_CRITICAL(); /* Task may be suspended */ + } + return (OS_ERR_NONE); +} +#endif +/*$PAGE*/ +/* +********************************************************************************************************* +* GET CURRENT SYSTEM TIME +* +* Description: This function is used by your application to obtain the current value of the 32-bit +* counter which keeps track of the number of clock ticks. +* +* Arguments : none +* +* Returns : The current value of OSTime +********************************************************************************************************* +*/ + +#if OS_TIME_GET_SET_EN > 0 +INT32U OSTimeGet (void) +{ + INT32U ticks; +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + + OS_ENTER_CRITICAL(); + ticks = OSTime; + OS_EXIT_CRITICAL(); + return (ticks); +} +#endif + +/* +********************************************************************************************************* +* SET SYSTEM CLOCK +* +* Description: This function sets the 32-bit counter which keeps track of the number of clock ticks. +* +* Arguments : ticks specifies the new value that OSTime needs to take. +* +* Returns : none +********************************************************************************************************* +*/ + +#if OS_TIME_GET_SET_EN > 0 +void OSTimeSet (INT32U ticks) +{ +#if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */ + OS_CPU_SR cpu_sr = 0; +#endif + + + + OS_ENTER_CRITICAL(); + OSTime = ticks; + OS_EXIT_CRITICAL(); +} +#endif diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/UCOSII/src/os_tmr.c b/MCandWifiTestDE0/Software/MCTest_bsp/UCOSII/src/os_tmr.c new file mode 100644 index 00000000..6fb18f44 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/UCOSII/src/os_tmr.c @@ -0,0 +1,1116 @@ +/* +************************************************************************************************************************ +* uC/OS-II +* The Real-Time Kernel +* TIMER MANAGEMENT +* +* (c) Copyright 1992-2007, Micrium, Weston, FL +* All Rights Reserved +* +* +* File : OS_TMR.C +* By : Jean J. Labrosse +* Version : V2.86 +* +* LICENSING TERMS: +* --------------- +* uC/OS-II is provided in source form for FREE evaluation, for educational use or for peaceful research. +* If you plan on using uC/OS-II in a commercial product you need to contact Micriµm to properly license +* its use in your product. We provide ALL the source code for your convenience and to help you experience +* uC/OS-II. The fact that the source is provided does NOT mean that you can use it without paying a +* licensing fee. +************************************************************************************************************************ +*/ + +#include + +/* +************************************************************************************************************************ +* NOTES +* +* 1) Your application MUST define the following #define constants: +* +* OS_TASK_TMR_PRIO The priority of the Timer management task +* OS_TASK_TMR_STK_SIZE The size of the Timer management task's stack +* +* 2) You must call OSTmrSignal() to notify the Timer management task that it's time to update the timers. +************************************************************************************************************************ +*/ + +/* +************************************************************************************************************************ +* CONSTANTS +************************************************************************************************************************ +*/ + +#define OS_TMR_LINK_DLY 0 +#define OS_TMR_LINK_PERIODIC 1 + +/* +************************************************************************************************************************ +* LOCAL PROTOTYPES +************************************************************************************************************************ +*/ + +#if OS_TMR_EN > 0 +static OS_TMR *OSTmr_Alloc (void); +static void OSTmr_Free (OS_TMR *ptmr); +static void OSTmr_InitTask (void); +static void OSTmr_Link (OS_TMR *ptmr, INT8U type); +static void OSTmr_Unlink (OS_TMR *ptmr); +static void OSTmr_Lock (void); +static void OSTmr_Unlock (void); +static void OSTmr_Task (void *p_arg); +#endif + +/*$PAGE*/ +/* +************************************************************************************************************************ +* CREATE A TIMER +* +* Description: This function is called by your application code to create a timer. +* +* Arguments : dly Initial delay. +* If the timer is configured for ONE-SHOT mode, this is the timeout used +* If the timer is configured for PERIODIC mode, this is the first timeout to wait for +* before the timer starts entering periodic mode +* +* period The 'period' being repeated for the timer. +* If you specified 'OS_TMR_OPT_PERIODIC' as an option, when the timer expires, it will +* automatically restart with the same period. +* +* opt Specifies either: +* OS_TMR_OPT_ONE_SHOT The timer counts down only once +* OS_TMR_OPT_PERIODIC The timer counts down and then reloads itself +* +* callback Is a pointer to a callback function that will be called when the timer expires. The +* callback function must be declared as follows: +* +* void MyCallback (OS_TMR *ptmr, void *p_arg); +* +* callback_arg Is an argument (a pointer) that is passed to the callback function when it is called. +* +* pname Is a pointer to an ASCII string that is used to name the timer. Names are useful for +* debugging. The length of the ASCII string for the name can be as big as: +* +* OS_TMR_CFG_NAME_SIZE and should be found in OS_CFG.H +* +* perr Is a pointer to an error code. '*perr' will contain one of the following: +* OS_ERR_NONE +* OS_ERR_TMR_INVALID_DLY you specified an invalid delay +* OS_ERR_TMR_INVALID_PERIOD you specified an invalid period +* OS_ERR_TMR_INVALID_OPT you specified an invalid option +* OS_ERR_TMR_ISR if the call was made from an ISR +* OS_ERR_TMR_NON_AVAIL if there are no free timers from the timer pool +* OS_ERR_TMR_NAME_TOO_LONG if the timer name is too long to fit +* +* Returns : A pointer to an OS_TMR data structure. +* This is the 'handle' that your application will use to reference the timer created. +************************************************************************************************************************ +*/ + +#if OS_TMR_EN > 0 +OS_TMR *OSTmrCreate (INT32U dly, + INT32U period, + INT8U opt, + OS_TMR_CALLBACK callback, + void *callback_arg, + INT8U *pname, + INT8U *perr) +{ + OS_TMR *ptmr; +#if OS_TMR_CFG_NAME_SIZE > 0 + INT8U len; +#endif + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate arguments */ + return ((OS_TMR *)0); + } + switch (opt) { + case OS_TMR_OPT_PERIODIC: + if (period == 0) { + *perr = OS_ERR_TMR_INVALID_PERIOD; + return ((OS_TMR *)0); + } + break; + + case OS_TMR_OPT_ONE_SHOT: + if (dly == 0) { + *perr = OS_ERR_TMR_INVALID_DLY; + return ((OS_TMR *)0); + } + break; + + default: + *perr = OS_ERR_TMR_INVALID_OPT; + return ((OS_TMR *)0); + } +#endif + if (OSIntNesting > 0) { /* See if trying to call from an ISR */ + *perr = OS_ERR_TMR_ISR; + return ((OS_TMR *)0); + } + OSTmr_Lock(); + ptmr = OSTmr_Alloc(); /* Obtain a timer from the free pool */ + if (ptmr == (OS_TMR *)0) { + OSTmr_Unlock(); + *perr = OS_ERR_TMR_NON_AVAIL; + return ((OS_TMR *)0); + } + ptmr->OSTmrState = OS_TMR_STATE_STOPPED; /* Indicate that timer is not running yet */ + ptmr->OSTmrDly = dly; + ptmr->OSTmrPeriod = period; + ptmr->OSTmrOpt = opt; + ptmr->OSTmrCallback = callback; + ptmr->OSTmrCallbackArg = callback_arg; +#if OS_TMR_CFG_NAME_SIZE > 0 + if (pname !=(INT8U *)0) { + len = OS_StrLen(pname); /* Copy timer name */ + if (len < OS_TMR_CFG_NAME_SIZE) { + (void)OS_StrCopy(ptmr->OSTmrName, pname); + } else { +#if OS_TMR_CFG_NAME_SIZE > 1 + ptmr->OSTmrName[0] = '#'; /* Invalid size specified */ + ptmr->OSTmrName[1] = OS_ASCII_NUL; +#endif + *perr = OS_ERR_TMR_NAME_TOO_LONG; + OSTmr_Unlock(); + return (ptmr); + } + } +#endif + OSTmr_Unlock(); + *perr = OS_ERR_NONE; + return (ptmr); +} +#endif + +/*$PAGE*/ +/* +************************************************************************************************************************ +* DELETE A TIMER +* +* Description: This function is called by your application code to delete a timer. +* +* Arguments : ptmr Is a pointer to the timer to stop and delete. +* +* perr Is a pointer to an error code. '*perr' will contain one of the following: +* OS_ERR_NONE +* OS_ERR_TMR_INVALID 'ptmr' is a NULL pointer +* OS_ERR_TMR_INVALID_TYPE 'ptmr' is not pointing to an OS_TMR +* OS_ERR_TMR_ISR if the function was called from an ISR +* OS_ERR_TMR_INACTIVE if the timer was not created +* OS_ERR_TMR_INVALID_STATE the timer is in an invalid state +* +* Returns : OS_TRUE If the call was successful +* OS_FALSE If not +************************************************************************************************************************ +*/ + +#if OS_TMR_EN > 0 +BOOLEAN OSTmrDel (OS_TMR *ptmr, + INT8U *perr) +{ +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate arguments */ + return (OS_FALSE); + } + if (ptmr == (OS_TMR *)0) { + *perr = OS_ERR_TMR_INVALID; + return (OS_FALSE); + } +#endif + if (ptmr->OSTmrType != OS_TMR_TYPE) { /* Validate timer structure */ + *perr = OS_ERR_TMR_INVALID_TYPE; + return (OS_FALSE); + } + if (OSIntNesting > 0) { /* See if trying to call from an ISR */ + *perr = OS_ERR_TMR_ISR; + return (OS_FALSE); + } + OSTmr_Lock(); + switch (ptmr->OSTmrState) { + case OS_TMR_STATE_RUNNING: + OSTmr_Unlink(ptmr); /* Remove from current wheel spoke */ + OSTmr_Free(ptmr); /* Return timer to free list of timers */ + OSTmr_Unlock(); + *perr = OS_ERR_NONE; + return (OS_TRUE); + + case OS_TMR_STATE_STOPPED: /* Timer has not started or ... */ + case OS_TMR_STATE_COMPLETED: /* ... timer has completed the ONE-SHOT time */ + OSTmr_Free(ptmr); /* Return timer to free list of timers */ + OSTmr_Unlock(); + *perr = OS_ERR_NONE; + return (OS_TRUE); + + case OS_TMR_STATE_UNUSED: /* Already deleted */ + OSTmr_Unlock(); + *perr = OS_ERR_TMR_INACTIVE; + return (OS_FALSE); + + default: + OSTmr_Unlock(); + *perr = OS_ERR_TMR_INVALID_STATE; + return (OS_FALSE); + } +} +#endif + +/*$PAGE*/ +/* +************************************************************************************************************************ +* GET THE NAME OF A TIMER +* +* Description: This function is called to obtain the name of a timer. +* +* Arguments : ptmr Is a pointer to the timer to obtain the name for +* +* pdest Is a pointer to where the name of the timer will be placed. It is the caller's responsibility +* to ensure that he has sufficient storage in the destination, i.e. at least OS_TMR_CFG_NAME_SIZE +* +* perr Is a pointer to an error code. '*perr' will contain one of the following: +* OS_ERR_NONE The call was successful +* OS_ERR_TMR_INVALID_DEST 'pdest' is a NULL pointer +* OS_ERR_TMR_INVALID 'ptmr' is a NULL pointer +* OS_ERR_TMR_INVALID_TYPE 'ptmr' is not pointing to an OS_TMR +* OS_ERR_NAME_GET_ISR if the call was made from an ISR +* OS_ERR_TMR_INACTIVE 'ptmr' points to a timer that is not active +* OS_ERR_TMR_INVALID_STATE the timer is in an invalid state +* +* Returns : The length of the string or 0 if the timer does not exist. +************************************************************************************************************************ +*/ + +#if OS_TMR_EN > 0 && OS_TMR_CFG_NAME_SIZE > 0 +INT8U OSTmrNameGet (OS_TMR *ptmr, + INT8U *pdest, + INT8U *perr) +{ + INT8U len; + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { + return (0); + } + if (pdest == (INT8U *)0) { + *perr = OS_ERR_TMR_INVALID_DEST; + return (0); + } + if (ptmr == (OS_TMR *)0) { + *perr = OS_ERR_TMR_INVALID; + return (0); + } +#endif + if (ptmr->OSTmrType != OS_TMR_TYPE) { /* Validate timer structure */ + *perr = OS_ERR_TMR_INVALID_TYPE; + return (0); + } + if (OSIntNesting > 0) { /* See if trying to call from an ISR */ + *perr = OS_ERR_NAME_GET_ISR; + return (0); + } + OSTmr_Lock(); + switch (ptmr->OSTmrState) { + case OS_TMR_STATE_RUNNING: + case OS_TMR_STATE_STOPPED: + case OS_TMR_STATE_COMPLETED: + len = OS_StrCopy(pdest, ptmr->OSTmrName); + OSTmr_Unlock(); + *perr = OS_ERR_NONE; + return (len); + + case OS_TMR_STATE_UNUSED: /* Timer is not allocated */ + OSTmr_Unlock(); + *perr = OS_ERR_TMR_INACTIVE; + return (0); + + default: + OSTmr_Unlock(); + *perr = OS_ERR_TMR_INVALID_STATE; + return (0); + } +} +#endif + +/*$PAGE*/ +/* +************************************************************************************************************************ +* GET HOW MUCH TIME IS LEFT BEFORE A TIMER EXPIRES +* +* Description: This function is called to get the number of ticks before a timer times out. +* +* Arguments : ptmr Is a pointer to the timer to obtain the remaining time from. +* +* perr Is a pointer to an error code. '*perr' will contain one of the following: +* OS_ERR_NONE +* OS_ERR_TMR_INVALID 'ptmr' is a NULL pointer +* OS_ERR_TMR_INVALID_TYPE 'ptmr' is not pointing to an OS_TMR +* OS_ERR_TMR_ISR if the call was made from an ISR +* OS_ERR_TMR_INACTIVE 'ptmr' points to a timer that is not active +* OS_ERR_TMR_INVALID_STATE the timer is in an invalid state +* +* Returns : The time remaining for the timer to expire. The time represents 'timer' increments. In other words, if +* OSTmr_Task() is signaled every 1/10 of a second then the returned value represents the number of 1/10 of +* a second remaining before the timer expires. +************************************************************************************************************************ +*/ + +#if OS_TMR_EN > 0 +INT32U OSTmrRemainGet (OS_TMR *ptmr, + INT8U *perr) +{ + INT32U remain; + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { + return (0); + } + if (ptmr == (OS_TMR *)0) { + *perr = OS_ERR_TMR_INVALID; + return (0); + } +#endif + if (ptmr->OSTmrType != OS_TMR_TYPE) { /* Validate timer structure */ + *perr = OS_ERR_TMR_INVALID_TYPE; + return (0); + } + if (OSIntNesting > 0) { /* See if trying to call from an ISR */ + *perr = OS_ERR_TMR_ISR; + return (0); + } + OSTmr_Lock(); + switch (ptmr->OSTmrState) { + case OS_TMR_STATE_RUNNING: + remain = ptmr->OSTmrMatch - OSTmrTime; /* Determine how much time is left to timeout */ + OSTmr_Unlock(); + *perr = OS_ERR_NONE; + return (remain); + + case OS_TMR_STATE_STOPPED: /* It's assumed that the timer has not started yet */ + switch (ptmr->OSTmrOpt) { + case OS_TMR_OPT_PERIODIC: + if (ptmr->OSTmrDly == 0) { + remain = ptmr->OSTmrPeriod; + } else { + remain = ptmr->OSTmrDly; + } + OSTmr_Unlock(); + *perr = OS_ERR_NONE; + break; + + case OS_TMR_OPT_ONE_SHOT: + default: + remain = ptmr->OSTmrDly; + OSTmr_Unlock(); + *perr = OS_ERR_NONE; + break; + } + return (remain); + + case OS_TMR_STATE_COMPLETED: /* Only ONE-SHOT that timed out can be in this state */ + OSTmr_Unlock(); + *perr = OS_ERR_NONE; + return (0); + + case OS_TMR_STATE_UNUSED: + OSTmr_Unlock(); + *perr = OS_ERR_TMR_INACTIVE; + return (0); + + default: + OSTmr_Unlock(); + *perr = OS_ERR_TMR_INVALID_STATE; + return (0); + } +} +#endif + +/*$PAGE*/ +/* +************************************************************************************************************************ +* FIND OUT WHAT STATE A TIMER IS IN +* +* Description: This function is called to determine what state the timer is in: +* +* OS_TMR_STATE_UNUSED the timer has not been created +* OS_TMR_STATE_STOPPED the timer has been created but has not been started or has been stopped +* OS_TMR_COMPLETED the timer is in ONE-SHOT mode and has completed it's timeout +* OS_TMR_RUNNING the timer is currently running +* +* Arguments : ptmr Is a pointer to the desired timer +* +* perr Is a pointer to an error code. '*perr' will contain one of the following: +* OS_ERR_NONE +* OS_ERR_TMR_INVALID 'ptmr' is a NULL pointer +* OS_ERR_TMR_INVALID_TYPE 'ptmr' is not pointing to an OS_TMR +* OS_ERR_TMR_ISR if the call was made from an ISR +* OS_ERR_TMR_INACTIVE 'ptmr' points to a timer that is not active +* OS_ERR_TMR_INVALID_STATE if the timer is not in a valid state +* +* Returns : The current state of the timer (see description). +************************************************************************************************************************ +*/ + +#if OS_TMR_EN > 0 +INT8U OSTmrStateGet (OS_TMR *ptmr, + INT8U *perr) +{ + INT8U state; + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { + return (0); + } + if (ptmr == (OS_TMR *)0) { + *perr = OS_ERR_TMR_INVALID; + return (0); + } +#endif + if (ptmr->OSTmrType != OS_TMR_TYPE) { /* Validate timer structure */ + *perr = OS_ERR_TMR_INVALID_TYPE; + return (0); + } + if (OSIntNesting > 0) { /* See if trying to call from an ISR */ + *perr = OS_ERR_TMR_ISR; + return (0); + } + OSTmr_Lock(); + state = ptmr->OSTmrState; + switch (state) { + case OS_TMR_STATE_UNUSED: + case OS_TMR_STATE_STOPPED: + case OS_TMR_STATE_COMPLETED: + case OS_TMR_STATE_RUNNING: + *perr = OS_ERR_NONE; + break; + + default: + *perr = OS_ERR_TMR_INVALID_STATE; + break; + } + OSTmr_Unlock(); + return (state); +} +#endif + +/*$PAGE*/ +/* +************************************************************************************************************************ +* START A TIMER +* +* Description: This function is called by your application code to start a timer. +* +* Arguments : ptmr Is a pointer to an OS_TMR +* +* perr Is a pointer to an error code. '*perr' will contain one of the following: +* OS_ERR_NONE +* OS_ERR_TMR_INVALID +* OS_ERR_TMR_INVALID_TYPE 'ptmr' is not pointing to an OS_TMR +* OS_ERR_TMR_ISR if the call was made from an ISR +* OS_ERR_TMR_INACTIVE if the timer was not created +* OS_ERR_TMR_INVALID_STATE the timer is in an invalid state +* +* Returns : OS_TRUE if the timer was started +* OS_FALSE if an error was detected +************************************************************************************************************************ +*/ + +#if OS_TMR_EN > 0 +BOOLEAN OSTmrStart (OS_TMR *ptmr, + INT8U *perr) +{ +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate arguments */ + return (OS_FALSE); + } + if (ptmr == (OS_TMR *)0) { + *perr = OS_ERR_TMR_INVALID; + return (OS_FALSE); + } +#endif + if (ptmr->OSTmrType != OS_TMR_TYPE) { /* Validate timer structure */ + *perr = OS_ERR_TMR_INVALID_TYPE; + return (OS_FALSE); + } + if (OSIntNesting > 0) { /* See if trying to call from an ISR */ + *perr = OS_ERR_TMR_ISR; + return (OS_FALSE); + } + OSTmr_Lock(); + switch (ptmr->OSTmrState) { + case OS_TMR_STATE_RUNNING: /* Restart the timer */ + OSTmr_Unlink(ptmr); /* ... Stop the timer */ + OSTmr_Link(ptmr, OS_TMR_LINK_DLY); /* ... Link timer to timer wheel */ + OSTmr_Unlock(); + *perr = OS_ERR_NONE; + return (OS_TRUE); + + case OS_TMR_STATE_STOPPED: /* Start the timer */ + case OS_TMR_STATE_COMPLETED: + OSTmr_Link(ptmr, OS_TMR_LINK_DLY); /* ... Link timer to timer wheel */ + OSTmr_Unlock(); + *perr = OS_ERR_NONE; + return (OS_TRUE); + + case OS_TMR_STATE_UNUSED: /* Timer not created */ + OSTmr_Unlock(); + *perr = OS_ERR_TMR_INACTIVE; + return (OS_FALSE); + + default: + OSTmr_Unlock(); + *perr = OS_ERR_TMR_INVALID_STATE; + return (OS_FALSE); + } +} +#endif + +/*$PAGE*/ +/* +************************************************************************************************************************ +* STOP A TIMER +* +* Description: This function is called by your application code to stop a timer. +* +* Arguments : ptmr Is a pointer to the timer to stop. +* +* opt Allows you to specify an option to this functions which can be: +* +* OS_TMR_OPT_NONE Do nothing special but stop the timer +* OS_TMR_OPT_CALLBACK Execute the callback function, pass it the callback argument +* specified when the timer was created. +* OS_TMR_OPT_CALLBACK_ARG Execute the callback function, pass it the callback argument +* specified in THIS function call +* +* callback_arg Is a pointer to a 'new' callback argument that can be passed to the callback function +* instead of the timer's callback argument. In other words, use 'callback_arg' passed in +* THIS function INSTEAD of ptmr->OSTmrCallbackArg +* +* perr Is a pointer to an error code. '*perr' will contain one of the following: +* OS_ERR_NONE +* OS_ERR_TMR_INVALID 'ptmr' is a NULL pointer +* OS_ERR_TMR_INVALID_TYPE 'ptmr' is not pointing to an OS_TMR +* OS_ERR_TMR_ISR if the function was called from an ISR +* OS_ERR_TMR_INACTIVE if the timer was not created +* OS_ERR_TMR_INVALID_OPT if you specified an invalid option for 'opt' +* OS_ERR_TMR_STOPPED if the timer was already stopped +* OS_ERR_TMR_INVALID_STATE the timer is in an invalid state +* OS_ERR_TMR_NO_CALLBACK if the timer does not have a callback function defined +* +* Returns : OS_TRUE If we stopped the timer (if the timer is already stopped, we also return OS_TRUE) +* OS_FALSE If not +************************************************************************************************************************ +*/ + +#if OS_TMR_EN > 0 +BOOLEAN OSTmrStop (OS_TMR *ptmr, + INT8U opt, + void *callback_arg, + INT8U *perr) +{ + OS_TMR_CALLBACK pfnct; + + +#if OS_ARG_CHK_EN > 0 + if (perr == (INT8U *)0) { /* Validate arguments */ + return (OS_FALSE); + } + if (ptmr == (OS_TMR *)0) { + *perr = OS_ERR_TMR_INVALID; + return (OS_FALSE); + } +#endif + if (ptmr->OSTmrType != OS_TMR_TYPE) { /* Validate timer structure */ + *perr = OS_ERR_TMR_INVALID_TYPE; + return (OS_FALSE); + } + if (OSIntNesting > 0) { /* See if trying to call from an ISR */ + *perr = OS_ERR_TMR_ISR; + return (OS_FALSE); + } + OSTmr_Lock(); + switch (ptmr->OSTmrState) { + case OS_TMR_STATE_RUNNING: + OSTmr_Unlink(ptmr); /* Remove from current wheel spoke */ + *perr = OS_ERR_NONE; + switch (opt) { + case OS_TMR_OPT_CALLBACK: + pfnct = ptmr->OSTmrCallback; /* Execute callback function if available ... */ + if (pfnct != (OS_TMR_CALLBACK)0) { + (*pfnct)((void *)ptmr, ptmr->OSTmrCallbackArg); /* Use callback arg when timer was created */ + } else { + *perr = OS_ERR_TMR_NO_CALLBACK; + } + break; + + case OS_TMR_OPT_CALLBACK_ARG: + pfnct = ptmr->OSTmrCallback; /* Execute callback function if available ... */ + if (pfnct != (OS_TMR_CALLBACK)0) { + (*pfnct)((void *)ptmr, callback_arg); /* ... using the 'callback_arg' provided in call */ + } else { + *perr = OS_ERR_TMR_NO_CALLBACK; + } + break; + + case OS_TMR_OPT_NONE: + break; + + default: + *perr = OS_ERR_TMR_INVALID_OPT; + break; + } + OSTmr_Unlock(); + return (OS_TRUE); + + case OS_TMR_STATE_COMPLETED: /* Timer has already completed the ONE-SHOT or ... */ + case OS_TMR_STATE_STOPPED: /* ... timer has not started yet. */ + OSTmr_Unlock(); + *perr = OS_ERR_TMR_STOPPED; + return (OS_TRUE); + + case OS_TMR_STATE_UNUSED: /* Timer was not created */ + OSTmr_Unlock(); + *perr = OS_ERR_TMR_INACTIVE; + return (OS_FALSE); + + default: + OSTmr_Unlock(); + *perr = OS_ERR_TMR_INVALID_STATE; + return (OS_FALSE); + } +} +#endif + +/*$PAGE*/ +/* +************************************************************************************************************************ +* SIGNAL THAT IT'S TIME TO UPDATE THE TIMERS +* +* Description: This function is typically called by the ISR that occurs at the timer tick rate and is used to signal to +* OSTmr_Task() that it's time to update the timers. +* +* Arguments : none +* +* Returns : OS_ERR_NONE The call was successful and the timer task was signaled. +* OS_ERR_SEM_OVF If OSTmrSignal() was called more often than OSTmr_Task() can handle the timers. +* This would indicate that your system is heavily loaded. +* OS_ERR_EVENT_TYPE Unlikely you would get this error because the semaphore used for signaling is created +* by uC/OS-II. +* OS_ERR_PEVENT_NULL Again, unlikely you would ever get this error because the semaphore used for signaling +* is created by uC/OS-II. +************************************************************************************************************************ +*/ + +#if OS_TMR_EN > 0 +INT8U OSTmrSignal (void) +{ + INT8U err; + + + err = OSSemPost(OSTmrSemSignal); + return (err); +} +#endif + +/*$PAGE*/ +/* +************************************************************************************************************************ +* ALLOCATE AND FREE A TIMER +* +* Description: This function is called to allocate a timer. +* +* Arguments : none +* +* Returns : a pointer to a timer if one is available +************************************************************************************************************************ +*/ + +#if OS_TMR_EN > 0 +static OS_TMR *OSTmr_Alloc (void) +{ + OS_TMR *ptmr; + + + if (OSTmrFreeList == (OS_TMR *)0) { + return ((OS_TMR *)0); + } + ptmr = (OS_TMR *)OSTmrFreeList; + OSTmrFreeList = (OS_TMR *)ptmr->OSTmrNext; + ptmr->OSTmrNext = (OS_TCB *)0; + ptmr->OSTmrPrev = (OS_TCB *)0; + OSTmrUsed++; + OSTmrFree--; + return (ptmr); +} +#endif + + +/* +************************************************************************************************************************ +* RETURN A TIMER TO THE FREE LIST +* +* Description: This function is called to return a timer object to the free list of timers. +* +* Arguments : ptmr is a pointer to the timer to free +* +* Returns : none +************************************************************************************************************************ +*/ + +#if OS_TMR_EN > 0 +static void OSTmr_Free (OS_TMR *ptmr) +{ + ptmr->OSTmrState = OS_TMR_STATE_UNUSED; /* Clear timer object fields */ + ptmr->OSTmrOpt = OS_TMR_OPT_NONE; + ptmr->OSTmrPeriod = 0; + ptmr->OSTmrMatch = 0; + ptmr->OSTmrCallback = (OS_TMR_CALLBACK)0; + ptmr->OSTmrCallbackArg = (void *)0; +#if OS_TMR_CFG_NAME_SIZE > 1 + ptmr->OSTmrName[0] = '?'; /* Unknown name */ + ptmr->OSTmrName[1] = OS_ASCII_NUL; +#endif + + ptmr->OSTmrPrev = (OS_TCB *)0; /* Chain timer to free list */ + ptmr->OSTmrNext = OSTmrFreeList; + OSTmrFreeList = ptmr; + + OSTmrUsed--; /* Update timer object statistics */ + OSTmrFree++; +} +#endif + +/*$PAGE*/ +/* +************************************************************************************************************************ +* INITIALIZATION +* INITIALIZE THE FREE LIST OF TIMERS +* +* Description: This function is called by OSInit() to initialize the free list of OS_TMRs. +* +* Arguments : none +* +* Returns : none +************************************************************************************************************************ +*/ + +#if OS_TMR_EN > 0 +void OSTmr_Init (void) +{ +#if OS_EVENT_NAME_SIZE > 10 + INT8U err; +#endif + INT16U i; + OS_TMR *ptmr1; + OS_TMR *ptmr2; + + + OS_MemClr((INT8U *)&OSTmrTbl[0], sizeof(OSTmrTbl)); /* Clear all the TMRs */ + OS_MemClr((INT8U *)&OSTmrWheelTbl[0], sizeof(OSTmrWheelTbl)); /* Clear the timer wheel */ + + ptmr1 = &OSTmrTbl[0]; + ptmr2 = &OSTmrTbl[1]; + for (i = 0; i < (OS_TMR_CFG_MAX - 1); i++) { /* Init. list of free TMRs */ + ptmr1->OSTmrType = OS_TMR_TYPE; + ptmr1->OSTmrState = OS_TMR_STATE_UNUSED; /* Indicate that timer is inactive */ + ptmr1->OSTmrNext = (void *)ptmr2; /* Link to next timer */ +#if OS_TMR_CFG_NAME_SIZE > 1 + ptmr1->OSTmrName[0] = '?'; /* Unknown name */ + ptmr1->OSTmrName[1] = OS_ASCII_NUL; +#endif + ptmr1++; + ptmr2++; + } + ptmr1->OSTmrType = OS_TMR_TYPE; + ptmr1->OSTmrState = OS_TMR_STATE_UNUSED; /* Indicate that timer is inactive */ + ptmr1->OSTmrNext = (void *)0; /* Last OS_TMR */ +#if OS_TMR_CFG_NAME_SIZE > 1 + ptmr1->OSTmrName[0] = '?'; /* Unknown name */ + ptmr1->OSTmrName[1] = OS_ASCII_NUL; +#endif + OSTmrTime = 0; + OSTmrUsed = 0; + OSTmrFree = OS_TMR_CFG_MAX; + OSTmrFreeList = &OSTmrTbl[0]; + OSTmrSem = OSSemCreate(1); + OSTmrSemSignal = OSSemCreate(0); + +#if OS_EVENT_NAME_SIZE > 18 + OSEventNameSet(OSTmrSem, (INT8U *)"uC/OS-II TmrLock", &err);/* Assign names to semaphores */ +#else +#if OS_EVENT_NAME_SIZE > 10 + OSEventNameSet(OSTmrSem, (INT8U *)"OS-TmrLock", &err); +#endif +#endif + +#if OS_EVENT_NAME_SIZE > 18 + OSEventNameSet(OSTmrSemSignal, (INT8U *)"uC/OS-II TmrSignal", &err); +#else +#if OS_EVENT_NAME_SIZE > 10 + OSEventNameSet(OSTmrSemSignal, (INT8U *)"OS-TmrSig", &err); +#endif +#endif + + OSTmr_InitTask(); +} +#endif + +/*$PAGE*/ +/* +************************************************************************************************************************ +* INITIALIZE THE TIMER MANAGEMENT TASK +* +* Description: This function is called by OSTmrInit() to create the timer management task. +* +* Arguments : none +* +* Returns : none +************************************************************************************************************************ +*/ + +#if OS_TMR_EN > 0 +static void OSTmr_InitTask (void) +{ +#if OS_TASK_NAME_SIZE > 6 + INT8U err; +#endif + + +#if OS_TASK_CREATE_EXT_EN > 0 + #if OS_STK_GROWTH == 1 + (void)OSTaskCreateExt(OSTmr_Task, + (void *)0, /* No arguments passed to OSTmrTask() */ + &OSTmrTaskStk[OS_TASK_TMR_STK_SIZE - 1], /* Set Top-Of-Stack */ + OS_TASK_TMR_PRIO, + OS_TASK_TMR_ID, + &OSTmrTaskStk[0], /* Set Bottom-Of-Stack */ + OS_TASK_TMR_STK_SIZE, + (void *)0, /* No TCB extension */ + OS_TASK_OPT_STK_CHK | OS_TASK_OPT_STK_CLR); /* Enable stack checking + clear stack */ + #else + (void)OSTaskCreateExt(OSTmr_Task, + (void *)0, /* No arguments passed to OSTmrTask() */ + &OSTmrTaskStk[0], /* Set Top-Of-Stack */ + OS_TASK_TMR_PRIO, + OS_TASK_TMR_ID, + &OSTmrTaskStk[OS_TASK_TMR_STK_SIZE - 1], /* Set Bottom-Of-Stack */ + OS_TASK_TMR_STK_SIZE, + (void *)0, /* No TCB extension */ + OS_TASK_OPT_STK_CHK | OS_TASK_OPT_STK_CLR); /* Enable stack checking + clear stack */ + #endif +#else + #if OS_STK_GROWTH == 1 + (void)OSTaskCreate(OSTmr_Task, + (void *)0, + &OSTmrTaskStk[OS_TASK_TMR_STK_SIZE - 1], + OS_TASK_TMR_PRIO); + #else + (void)OSTaskCreate(OSTmr_Task, + (void *)0, + &OSTmrTaskStk[0], + OS_TASK_TMR_PRIO); + #endif +#endif + +#if OS_TASK_NAME_SIZE > 12 + OSTaskNameSet(OS_TASK_TMR_PRIO, (INT8U *)"uC/OS-II Tmr", &err); +#else +#if OS_TASK_NAME_SIZE > 6 + OSTaskNameSet(OS_TASK_TMR_PRIO, (INT8U *)"OS-Tmr", &err); +#endif +#endif +} +#endif + +/*$PAGE*/ +/* +************************************************************************************************************************ +* INSERT A TIMER INTO THE TIMER WHEEL +* +* Description: This function is called to insert the timer into the timer wheel. The timer is always inserted at the +* beginning of the list. +* +* Arguments : ptmr Is a pointer to the timer to insert. +* +* type Is either: +* OS_TMR_LINK_PERIODIC Means to re-insert the timer after a period expired +* OS_TMR_LINK_DLY Means to insert the timer the first time +* +* Returns : none +************************************************************************************************************************ +*/ + +#if OS_TMR_EN > 0 +static void OSTmr_Link (OS_TMR *ptmr, INT8U type) +{ + OS_TMR *ptmr1; + OS_TMR_WHEEL *pspoke; + INT16U spoke; + + + ptmr->OSTmrState = OS_TMR_STATE_RUNNING; + if (type == OS_TMR_LINK_PERIODIC) { /* Determine when timer will expire */ + ptmr->OSTmrMatch = ptmr->OSTmrPeriod + OSTmrTime; + } else { + if (ptmr->OSTmrDly == 0) { + ptmr->OSTmrMatch = ptmr->OSTmrPeriod + OSTmrTime; + } else { + ptmr->OSTmrMatch = ptmr->OSTmrDly + OSTmrTime; + } + } + spoke = (INT16U)(ptmr->OSTmrMatch % OS_TMR_CFG_WHEEL_SIZE); + pspoke = &OSTmrWheelTbl[spoke]; + + if (pspoke->OSTmrFirst == (OS_TMR *)0) { /* Link into timer wheel */ + pspoke->OSTmrFirst = ptmr; + ptmr->OSTmrNext = (OS_TMR *)0; + pspoke->OSTmrEntries = 1; + } else { + ptmr1 = pspoke->OSTmrFirst; /* Point to first timer in the spoke */ + pspoke->OSTmrFirst = ptmr; + ptmr->OSTmrNext = (void *)ptmr1; + ptmr1->OSTmrPrev = (void *)ptmr; + pspoke->OSTmrEntries++; + } + ptmr->OSTmrPrev = (void *)0; /* Timer always inserted as first node in list */ +} +#endif + +/*$PAGE*/ +/* +************************************************************************************************************************ +* REMOVE A TIMER FROM THE TIMER WHEEL +* +* Description: This function is called to remove the timer from the timer wheel. +* +* Arguments : ptmr Is a pointer to the timer to remove. +* +* Returns : none +************************************************************************************************************************ +*/ + +#if OS_TMR_EN > 0 +static void OSTmr_Unlink (OS_TMR *ptmr) +{ + OS_TMR *ptmr1; + OS_TMR *ptmr2; + OS_TMR_WHEEL *pspoke; + INT16U spoke; + + + spoke = (INT16U)(ptmr->OSTmrMatch % OS_TMR_CFG_WHEEL_SIZE); + pspoke = &OSTmrWheelTbl[spoke]; + + if (pspoke->OSTmrFirst == ptmr) { /* See if timer to remove is at the beginning of list */ + ptmr1 = (OS_TMR *)ptmr->OSTmrNext; + pspoke->OSTmrFirst = (OS_TMR *)ptmr1; + if (ptmr1 != (OS_TMR *)0) { + ptmr1->OSTmrPrev = (void *)0; + } + } else { + ptmr1 = (OS_TMR *)ptmr->OSTmrPrev; /* Remove timer from somewhere in the list */ + ptmr2 = (OS_TMR *)ptmr->OSTmrNext; + ptmr1->OSTmrNext = ptmr2; + if (ptmr2 != (OS_TMR *)0) { + ptmr2->OSTmrPrev = (void *)ptmr1; + } + } + ptmr->OSTmrState = OS_TMR_STATE_STOPPED; + ptmr->OSTmrNext = (void *)0; + ptmr->OSTmrPrev = (void *)0; + pspoke->OSTmrEntries--; +} +#endif + +/*$PAGE*/ +/* +************************************************************************************************************************ +* TIMER MANAGER DATA STRUCTURE LOCKING MECHANISM +* +* Description: These functions are used to gain exclusive access to timer management data structures. +* +* Arguments : none +* +* Returns : none +************************************************************************************************************************ +*/ + +#if OS_TMR_EN > 0 +static void OSTmr_Lock (void) +{ + INT8U err; + + + OSSemPend(OSTmrSem, 0, &err); + (void)err; +} +#endif + + + +#if OS_TMR_EN > 0 +static void OSTmr_Unlock (void) +{ + (void)OSSemPost(OSTmrSem); +} +#endif + +/*$PAGE*/ +/* +************************************************************************************************************************ +* TIMER MANAGEMENT TASK +* +* Description: This task is created by OSTmrInit(). +* +* Arguments : none +* +* Returns : none +************************************************************************************************************************ +*/ + +#if OS_TMR_EN > 0 +static void OSTmr_Task (void *p_arg) +{ + INT8U err; + OS_TMR *ptmr; + OS_TMR *ptmr_next; + OS_TMR_CALLBACK pfnct; + OS_TMR_WHEEL *pspoke; + INT16U spoke; + + + (void)p_arg; /* Not using 'p_arg', prevent compiler warning */ + for (;;) { + OSSemPend(OSTmrSemSignal, 0, &err); /* Wait for signal indicating time to update timers */ + OSTmr_Lock(); + OSTmrTime++; /* Increment the current time */ + spoke = (INT16U)(OSTmrTime % OS_TMR_CFG_WHEEL_SIZE); /* Position on current timer wheel entry */ + pspoke = &OSTmrWheelTbl[spoke]; + ptmr = pspoke->OSTmrFirst; + while (ptmr != (OS_TMR *)0) { + ptmr_next = (OS_TMR *)ptmr->OSTmrNext; /* Point to next timer to update because current ... */ + /* ... timer could get unlinked from the wheel. */ + if (OSTmrTime == ptmr->OSTmrMatch) { /* Process each timer that expires */ + pfnct = ptmr->OSTmrCallback; /* Execute callback function if available */ + if (pfnct != (OS_TMR_CALLBACK)0) { + (*pfnct)((void *)ptmr, ptmr->OSTmrCallbackArg); + } + OSTmr_Unlink(ptmr); /* Remove from current wheel spoke */ + if (ptmr->OSTmrOpt == OS_TMR_OPT_PERIODIC) { + OSTmr_Link(ptmr, OS_TMR_LINK_PERIODIC); /* Recalculate new position of timer in wheel */ + } else { + ptmr->OSTmrState = OS_TMR_STATE_COMPLETED; /* Indicate that the timer has completed */ + } + } + ptmr = ptmr_next; + } + OSTmr_Unlock(); + } +} +#endif diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/alt_sys_init.c b/MCandWifiTestDE0/Software/MCTest_bsp/alt_sys_init.c new file mode 100644 index 00000000..758161af --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/alt_sys_init.c @@ -0,0 +1,107 @@ +/* + * alt_sys_init.c - HAL initialization source + * + * Machine generated for CPU 'cpu' in SOPC Builder design 'system' + * SOPC Builder design path: C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system.sopcinfo + * + * Generated: Mon Mar 03 15:52:38 MST 2014 + */ + +/* + * DO NOT MODIFY THIS FILE + * + * Changing this file will have subtle consequences + * which will almost certainly lead to a nonfunctioning + * system. If you do modify this file, be aware that your + * changes will be overwritten and lost when this file + * is generated again. + * + * DO NOT MODIFY THIS FILE + */ + +/* + * License Agreement + * + * Copyright (c) 2008 + * Altera Corporation, San Jose, California, USA. + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * This agreement shall be governed in all respects by the laws of the State + * of California and by the laws of the United States of America. + */ + +#include "system.h" +#include "sys/alt_irq.h" +#include "sys/alt_sys_init.h" + +#include + +/* + * Device headers + */ + +#include "altera_nios2_qsys_irq.h" +#include "altera_avalon_jtag_uart.h" +#include "altera_avalon_sysid_qsys.h" +#include "altera_avalon_timer.h" +#include "altera_avalon_uart.h" +#include "altera_up_avalon_rs232.h" + +/* + * Allocate the device storage + */ + +ALTERA_NIOS2_QSYS_IRQ_INSTANCE ( CPU, cpu); +ALTERA_AVALON_JTAG_UART_INSTANCE ( JTAG_UART_0, jtag_uart_0); +ALTERA_AVALON_SYSID_QSYS_INSTANCE ( SYSID, sysid); +ALTERA_AVALON_TIMER_INSTANCE ( SYS_CLK_TIMER, sys_clk_timer); +ALTERA_AVALON_UART_INSTANCE ( UART_MC, uart_mc); +ALTERA_AVALON_UART_INSTANCE ( UART_WIFI, uart_wifi); +ALTERA_UP_AVALON_RS232_INSTANCE ( RS232_WIFI, rs232_wifi); + +/* + * Initialize the interrupt controller devices + * and then enable interrupts in the CPU. + * Called before alt_sys_init(). + * The "base" parameter is ignored and only + * present for backwards-compatibility. + */ + +void alt_irq_init ( const void* base ) +{ + ALTERA_NIOS2_QSYS_IRQ_INIT ( CPU, cpu); + alt_irq_cpu_enable_interrupts(); +} + +/* + * Initialize the non-interrupt controller devices. + * Called after alt_irq_init(). + */ + +void alt_sys_init( void ) +{ + ALTERA_AVALON_TIMER_INIT ( SYS_CLK_TIMER, sys_clk_timer); + ALTERA_AVALON_JTAG_UART_INIT ( JTAG_UART_0, jtag_uart_0); + ALTERA_AVALON_SYSID_QSYS_INIT ( SYSID, sysid); + ALTERA_AVALON_UART_INIT ( UART_MC, uart_mc); + ALTERA_AVALON_UART_INIT ( UART_WIFI, uart_wifi); + ALTERA_UP_AVALON_RS232_INIT ( RS232_WIFI, rs232_wifi); +} diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/create-this-bsp b/MCandWifiTestDE0/Software/MCTest_bsp/create-this-bsp new file mode 100644 index 00000000..b3c68e06 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/create-this-bsp @@ -0,0 +1,49 @@ +#!/bin/bash +# +# This script creates the ucosii_net_zipfs Board Support Package (BSP). + +BSP_TYPE=ucosii +BSP_DIR=. +SOPC_DIR=../../ +SOPC_FILE=C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system.sopcinfo +NIOS2_BSP_ARGS="" +CPU_NAME= + + +# Don't run make if create-this-app script is called with --no-make arg +SKIP_MAKE= +while [ $# -gt 0 ] +do + case "$1" in + --no-make) + SKIP_MAKE=1 + ;; + *) + NIOS2_BSP_ARGS="$NIOS2_BSP_ARGS $1" + ;; + esac + shift +done + + +# Run nios2-bsp utility to create a ucosii BSP in this directory +# for the system with a .sopc file in $SOPC_FILE. +# Deprecating $SOPC_DIR in 10.1. Multiple .sopcinfo files in a directory may exist. + +if [ -z "$SOPC_FILE" ]; then + echo "WARNING: Use of a directory for locating a .sopcinfo file is deprecated in 10.1. Multiple .sopcinfo files may exist. You must specify the full .sopcinfo path." + cmd="nios2-bsp $BSP_TYPE $BSP_DIR $SOPC_DIR $NIOS2_BSP_ARGS $CPU_NAME" +else + cmd="nios2-bsp $BSP_TYPE $BSP_DIR $SOPC_FILE $NIOS2_BSP_ARGS $CPU_NAME" +fi + + +echo "create-this-bsp: Running \"$cmd\"" +$cmd || { + echo "$cmd failed" + exit 1 +} +if [ -z "$SKIP_MAKE" ]; then + echo "create-this-bsp: Running make" + make +fi diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/drivers/inc/altera_avalon_jtag_uart.h b/MCandWifiTestDE0/Software/MCTest_bsp/drivers/inc/altera_avalon_jtag_uart.h new file mode 100644 index 00000000..b00529aa --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/drivers/inc/altera_avalon_jtag_uart.h @@ -0,0 +1,191 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#ifndef __ALT_AVALON_JTAG_UART_H__ +#define __ALT_AVALON_JTAG_UART_H__ + +#include + +#include "sys/alt_alarm.h" +#include "sys/alt_warning.h" + +#include "os/alt_sem.h" +#include "os/alt_flag.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * If the user wants all drivers to be small rather than fast then make sure + * this one is marked as needing to be small. + */ +#if defined ALT_USE_SMALL_DRIVERS && !defined ALTERA_AVALON_JTAG_UART_SMALL +#define ALTERA_AVALON_JTAG_UART_SMALL +#endif + +/* + * Constants that can be overriden. + */ +#ifndef ALTERA_AVALON_JTAG_UART_DEFAULT_TIMEOUT +#define ALTERA_AVALON_JTAG_UART_DEFAULT_TIMEOUT 10 +#endif + +#ifndef ALTERA_AVALON_JTAG_UART_BUF_LEN +#define ALTERA_AVALON_JTAG_UART_BUF_LEN 2048 +#endif + +/* + * ALT_JTAG_UART_READ_RDY and ALT_JTAG_UART_WRITE_RDY are the bitmasks + * that define uC/OS-II event flags that are releated to this device. + * + * ALT_JTAG_UART_READ_RDY indicates that there is read data in the buffer + * ready to be processed. ALT_JTAG_UART_WRITE_RDY indicates that the transmitter is + * ready for more data. + */ +#define ALT_JTAG_UART_READ_RDY 0x1 +#define ALT_JTAG_UART_WRITE_RDY 0x2 +#define ALT_JTAG_UART_TIMEOUT 0x4 + +/* + * State structure definition. Each instance of the driver uses one + * of these structures to hold its associated state. + */ + +typedef struct altera_avalon_jtag_uart_state_s +{ + unsigned int base; + +#ifndef ALTERA_AVALON_JTAG_UART_SMALL + + unsigned int timeout; /* Timeout until host is assumed inactive */ + alt_alarm alarm; + unsigned int irq_enable; + unsigned int host_inactive; + + ALT_SEM (read_lock) + ALT_SEM (write_lock) + ALT_FLAG_GRP (events) + + /* The variables below are volatile because they are modified by the + * interrupt routine. Making them volatile and reading them atomically + * means that we don't need any large critical sections. + */ + volatile unsigned int rx_in; + unsigned int rx_out; + unsigned int tx_in; + volatile unsigned int tx_out; + char rx_buf[ALTERA_AVALON_JTAG_UART_BUF_LEN]; + char tx_buf[ALTERA_AVALON_JTAG_UART_BUF_LEN]; + +#endif /* !ALTERA_AVALON_JTAG_UART_SMALL */ + +} altera_avalon_jtag_uart_state; + +/* + * Macros used by alt_sys_init when the ALT file descriptor facility isn't used. + */ + +#ifdef ALTERA_AVALON_JTAG_UART_SMALL + +#define ALTERA_AVALON_JTAG_UART_STATE_INSTANCE(name, state) \ + altera_avalon_jtag_uart_state state = \ + { \ + name##_BASE, \ + } + +#define ALTERA_AVALON_JTAG_UART_STATE_INIT(name, state) + +#else /* !ALTERA_AVALON_JTAG_UART_SMALL */ + +#define ALTERA_AVALON_JTAG_UART_STATE_INSTANCE(name, state) \ + altera_avalon_jtag_uart_state state = \ + { \ + name##_BASE, \ + ALTERA_AVALON_JTAG_UART_DEFAULT_TIMEOUT, \ + } + +/* + * Externally referenced routines + */ +extern void altera_avalon_jtag_uart_init(altera_avalon_jtag_uart_state* sp, + int irq_controller_id, int irq); + +#define ALTERA_AVALON_JTAG_UART_STATE_INIT(name, state) \ + { \ + if (name##_IRQ == ALT_IRQ_NOT_CONNECTED) \ + { \ + ALT_LINK_ERROR ("Error: Interrupt not connected for " #name ". " \ + "You have selected the interrupt driven version of " \ + "the ALTERA Avalon JTAG UART driver, but the " \ + "interrupt is not connected for this device. You can " \ + "select a polled mode driver by checking the 'small " \ + "driver' option in the HAL configuration window, or " \ + "by using the -DALTERA_AVALON_JTAG_UART_SMALL " \ + "preprocessor flag."); \ + } \ + else \ + altera_avalon_jtag_uart_init(&state, \ + name##_IRQ_INTERRUPT_CONTROLLER_ID, \ + name##_IRQ); \ + } + +#endif /* ALTERA_AVALON_JTAG_UART_SMALL */ + +/* + * Include in case non-direct version of driver required. + */ +#include "altera_avalon_jtag_uart_fd.h" + +/* + * Map alt_sys_init macros to direct or non-direct versions. + */ +#ifdef ALT_USE_DIRECT_DRIVERS + +#define ALTERA_AVALON_JTAG_UART_INSTANCE(name, state) \ + ALTERA_AVALON_JTAG_UART_STATE_INSTANCE(name, state) +#define ALTERA_AVALON_JTAG_UART_INIT(name, state) \ + ALTERA_AVALON_JTAG_UART_STATE_INIT(name, state) + +#else /* !ALT_USE_DIRECT_DRIVERS */ + +#define ALTERA_AVALON_JTAG_UART_INSTANCE(name, dev) \ + ALTERA_AVALON_JTAG_UART_DEV_INSTANCE(name, dev) +#define ALTERA_AVALON_JTAG_UART_INIT(name, dev) \ + ALTERA_AVALON_JTAG_UART_DEV_INIT(name, dev) + +#endif /* ALT_USE_DIRECT_DRIVERS */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALT_AVALON_JTAG_UART_H__ */ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/drivers/inc/altera_avalon_jtag_uart_fd.h b/MCandWifiTestDE0/Software/MCTest_bsp/drivers/inc/altera_avalon_jtag_uart_fd.h new file mode 100644 index 00000000..b3c32009 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/drivers/inc/altera_avalon_jtag_uart_fd.h @@ -0,0 +1,125 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2007 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#ifndef __ALT_AVALON_JTAG_UART_FD_H__ +#define __ALT_AVALON_JTAG_UART_FD_H__ + +#include "sys/alt_dev.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Externally referenced routines + */ +extern int altera_avalon_jtag_uart_read_fd (alt_fd* fd, char* ptr, int len); +extern int altera_avalon_jtag_uart_write_fd (alt_fd* fd, const char* ptr, + int len); + +/* + * Device structure definition. This is needed by alt_sys_init in order to + * reserve memory for the device instance. + */ + +typedef struct altera_avalon_jtag_uart_dev_s +{ + alt_dev dev; + altera_avalon_jtag_uart_state state; +} altera_avalon_jtag_uart_dev; + +/* + * Macros used by alt_sys_init when the ALT file descriptor facility is used. + */ + +#ifdef ALTERA_AVALON_JTAG_UART_SMALL + +#define ALTERA_AVALON_JTAG_UART_DEV_INSTANCE(name, d) \ + static altera_avalon_jtag_uart_dev d = \ + { \ + { \ + ALT_LLIST_ENTRY, \ + name##_NAME, \ + NULL, /* open */ \ + NULL, /* close */ \ + altera_avalon_jtag_uart_read_fd, \ + altera_avalon_jtag_uart_write_fd, \ + NULL, /* lseek */ \ + NULL, /* fstat */ \ + NULL, /* ioctl */ \ + }, \ + { \ + name##_BASE, \ + } \ + } + +#define ALTERA_AVALON_JTAG_UART_DEV_INIT(name, d) alt_dev_reg (&d.dev) + +#else /* !ALTERA_AVALON_JTAG_UART_SMALL */ + +extern int altera_avalon_jtag_uart_close_fd(alt_fd* fd); +extern int altera_avalon_jtag_uart_ioctl_fd (alt_fd* fd, int req, void* arg); + +#define ALTERA_AVALON_JTAG_UART_DEV_INSTANCE(name, d) \ + static altera_avalon_jtag_uart_dev d = \ + { \ + { \ + ALT_LLIST_ENTRY, \ + name##_NAME, \ + NULL, /* open */ \ + altera_avalon_jtag_uart_close_fd, \ + altera_avalon_jtag_uart_read_fd, \ + altera_avalon_jtag_uart_write_fd, \ + NULL, /* lseek */ \ + NULL, /* fstat */ \ + altera_avalon_jtag_uart_ioctl_fd, \ + }, \ + { \ + name##_BASE, \ + ALTERA_AVALON_JTAG_UART_DEFAULT_TIMEOUT, \ + } \ + } + +#define ALTERA_AVALON_JTAG_UART_DEV_INIT(name, d) \ + { \ + ALTERA_AVALON_JTAG_UART_STATE_INIT(name, d.state); \ + \ + /* make the device available to the system */ \ + alt_dev_reg(&d.dev); \ + } + +#endif /* ALTERA_AVALON_JTAG_UART_SMALL */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALT_AVALON_JTAG_UART_FD_H__ */ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/drivers/inc/altera_avalon_jtag_uart_regs.h b/MCandWifiTestDE0/Software/MCTest_bsp/drivers/inc/altera_avalon_jtag_uart_regs.h new file mode 100644 index 00000000..7f971602 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/drivers/inc/altera_avalon_jtag_uart_regs.h @@ -0,0 +1,73 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#ifndef __ALTERA_AVALON_JTAG_UART_REGS_H__ +#define __ALTERA_AVALON_JTAG_UART_REGS_H__ + +#include + +#define ALTERA_AVALON_JTAG_UART_DATA_REG 0 +#define IOADDR_ALTERA_AVALON_JTAG_UART_DATA(base) \ + __IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_JTAG_UART_DATA_REG) +#define IORD_ALTERA_AVALON_JTAG_UART_DATA(base) \ + IORD(base, ALTERA_AVALON_JTAG_UART_DATA_REG) +#define IOWR_ALTERA_AVALON_JTAG_UART_DATA(base, data) \ + IOWR(base, ALTERA_AVALON_JTAG_UART_DATA_REG, data) + +#define ALTERA_AVALON_JTAG_UART_DATA_DATA_MSK (0x000000FF) +#define ALTERA_AVALON_JTAG_UART_DATA_DATA_OFST (0) +#define ALTERA_AVALON_JTAG_UART_DATA_RVALID_MSK (0x00008000) +#define ALTERA_AVALON_JTAG_UART_DATA_RVALID_OFST (15) +#define ALTERA_AVALON_JTAG_UART_DATA_RAVAIL_MSK (0xFFFF0000) +#define ALTERA_AVALON_JTAG_UART_DATA_RAVAIL_OFST (16) + + +#define ALTERA_AVALON_JTAG_UART_CONTROL_REG 1 +#define IOADDR_ALTERA_AVALON_JTAG_UART_CONTROL(base) \ + __IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_JTAG_UART_CONTROL_REG) +#define IORD_ALTERA_AVALON_JTAG_UART_CONTROL(base) \ + IORD(base, ALTERA_AVALON_JTAG_UART_CONTROL_REG) +#define IOWR_ALTERA_AVALON_JTAG_UART_CONTROL(base, data) \ + IOWR(base, ALTERA_AVALON_JTAG_UART_CONTROL_REG, data) + +#define ALTERA_AVALON_JTAG_UART_CONTROL_RE_MSK (0x00000001) +#define ALTERA_AVALON_JTAG_UART_CONTROL_RE_OFST (0) +#define ALTERA_AVALON_JTAG_UART_CONTROL_WE_MSK (0x00000002) +#define ALTERA_AVALON_JTAG_UART_CONTROL_WE_OFST (1) +#define ALTERA_AVALON_JTAG_UART_CONTROL_RI_MSK (0x00000100) +#define ALTERA_AVALON_JTAG_UART_CONTROL_RI_OFST (8) +#define ALTERA_AVALON_JTAG_UART_CONTROL_WI_MSK (0x00000200) +#define ALTERA_AVALON_JTAG_UART_CONTROL_WI_OFST (9) +#define ALTERA_AVALON_JTAG_UART_CONTROL_AC_MSK (0x00000400) +#define ALTERA_AVALON_JTAG_UART_CONTROL_AC_OFST (10) +#define ALTERA_AVALON_JTAG_UART_CONTROL_WSPACE_MSK (0xFFFF0000) +#define ALTERA_AVALON_JTAG_UART_CONTROL_WSPACE_OFST (16) + +#endif /* __ALTERA_AVALON_JTAG_UART_REGS_H__ */ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/drivers/inc/altera_avalon_pio_regs.h b/MCandWifiTestDE0/Software/MCTest_bsp/drivers/inc/altera_avalon_pio_regs.h new file mode 100644 index 00000000..052439ff --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/drivers/inc/altera_avalon_pio_regs.h @@ -0,0 +1,67 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#ifndef __ALTERA_AVALON_PIO_REGS_H__ +#define __ALTERA_AVALON_PIO_REGS_H__ + +#include + +#define IOADDR_ALTERA_AVALON_PIO_DATA(base) __IO_CALC_ADDRESS_NATIVE(base, 0) +#define IORD_ALTERA_AVALON_PIO_DATA(base) IORD(base, 0) +#define IOWR_ALTERA_AVALON_PIO_DATA(base, data) IOWR(base, 0, data) + +#define IOADDR_ALTERA_AVALON_PIO_DIRECTION(base) __IO_CALC_ADDRESS_NATIVE(base, 1) +#define IORD_ALTERA_AVALON_PIO_DIRECTION(base) IORD(base, 1) +#define IOWR_ALTERA_AVALON_PIO_DIRECTION(base, data) IOWR(base, 1, data) + +#define IOADDR_ALTERA_AVALON_PIO_IRQ_MASK(base) __IO_CALC_ADDRESS_NATIVE(base, 2) +#define IORD_ALTERA_AVALON_PIO_IRQ_MASK(base) IORD(base, 2) +#define IOWR_ALTERA_AVALON_PIO_IRQ_MASK(base, data) IOWR(base, 2, data) + +#define IOADDR_ALTERA_AVALON_PIO_EDGE_CAP(base) __IO_CALC_ADDRESS_NATIVE(base, 3) +#define IORD_ALTERA_AVALON_PIO_EDGE_CAP(base) IORD(base, 3) +#define IOWR_ALTERA_AVALON_PIO_EDGE_CAP(base, data) IOWR(base, 3, data) + + +#define IOADDR_ALTERA_AVALON_PIO_SET_BIT(base) __IO_CALC_ADDRESS_NATIVE(base, 4) +#define IORD_ALTERA_AVALON_PIO_SET_BITS(base) IORD(base, 4) +#define IOWR_ALTERA_AVALON_PIO_SET_BITS(base, data) IOWR(base, 4, data) + +#define IOADDR_ALTERA_AVALON_PIO_CLEAR_BITS(base) __IO_CALC_ADDRESS_NATIVE(base, 5) +#define IORD_ALTERA_AVALON_PIO_CLEAR_BITS(base) IORD(base, 5) +#define IOWR_ALTERA_AVALON_PIO_CLEAR_BITS(base, data) IOWR(base, 5, data) + + + +/* Defintions for direction-register operation with bi-directional PIOs */ +#define ALTERA_AVALON_PIO_DIRECTION_INPUT 0 +#define ALTERA_AVALON_PIO_DIRECTION_OUTPUT 1 + +#endif /* __ALTERA_AVALON_PIO_REGS_H__ */ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/drivers/inc/altera_avalon_sysid_qsys.h b/MCandWifiTestDE0/Software/MCTest_bsp/drivers/inc/altera_avalon_sysid_qsys.h new file mode 100644 index 00000000..930e4a8c --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/drivers/inc/altera_avalon_sysid_qsys.h @@ -0,0 +1,60 @@ +#ifndef __ALT_AVALON_SYSID_QSYS_H__ +#define __ALT_AVALON_SYSID_QSYS_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include "alt_types.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * ALTERA_AVALON_SYSID_QSYS_INSTANCE is the macro used by alt_sys_init() to + * allocate any per device memory that may be required. In this case no + * allocation is necessary. + */ + +#define ALTERA_AVALON_SYSID_QSYS_INSTANCE(name, dev) extern int alt_no_storage +#define ALTERA_AVALON_SYSID_QSYS_INIT(name, dev) while (0) + +#ifdef SYSID_BASE +alt_32 alt_avalon_sysid_qsys_test(void); +#endif + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALT_AVALON_SYSID_QSYS_H__ */ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/drivers/inc/altera_avalon_sysid_qsys_regs.h b/MCandWifiTestDE0/Software/MCTest_bsp/drivers/inc/altera_avalon_sysid_qsys_regs.h new file mode 100644 index 00000000..c59cbfb8 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/drivers/inc/altera_avalon_sysid_qsys_regs.h @@ -0,0 +1,42 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#ifndef __ALTERA_AVALON_SYSID_QSYS_REGS_H__ +#define __ALTERA_AVALON_SYSID_QSYS_REGS_H__ + +#include + +#define IOADDR_ALTERA_AVALON_SYSID_QSYS_ID(base) __IO_CALC_ADDRESS_NATIVE(base, 0) +#define IORD_ALTERA_AVALON_SYSID_QSYS_ID(base) IORD(base, 0) + +#define IOADDR_ALTERA_AVALON_SYSID_QSYS_TIMESTAMP(base) __IO_CALC_ADDRESS_NATIVE(base, 1) +#define IORD_ALTERA_AVALON_SYSID_QSYS_TIMESTAMP(base) IORD(base, 1) + +#endif /* __ALTERA_AVALON_SYSID_QSYS_REGS_H__ */ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/drivers/inc/altera_avalon_timer.h b/MCandWifiTestDE0/Software/MCTest_bsp/drivers/inc/altera_avalon_timer.h new file mode 100644 index 00000000..dae4193d --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/drivers/inc/altera_avalon_timer.h @@ -0,0 +1,193 @@ +#ifndef __ALT_AVALON_TIMER_H__ +#define __ALT_AVALON_TIMER_H__ + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include + +#include "alt_types.h" +#include "sys/alt_dev.h" +#include "sys/alt_warning.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + + +#define __ALT_COUNTER_SIZE(name) name##_COUNTER_SIZE +#define _ALT_COUNTER_SIZE(name) __ALT_COUNTER_SIZE(name) + +#define ALT_SYS_CLK_COUNTER_SIZE _ALT_COUNTER_SIZE(ALT_SYS_CLK) +#define ALT_TIMESTAMP_COUNTER_SIZE _ALT_COUNTER_SIZE(ALT_TIMESTAMP_CLK) + +#if (ALT_SYS_CLK_COUNTER_SIZE == 64) +#define alt_sysclk_type alt_u64 +#else +#define alt_sysclk_type alt_u32 +#endif + +#if (ALT_TIMESTAMP_COUNTER_SIZE == 64) +#define alt_timestamp_type alt_u64 +#else +#define alt_timestamp_type alt_u32 +#endif + +/* + * The function alt_avalon_timer_sc_init() is the initialisation function for + * the system clock. It registers the timers interrupt handler, and then calls + * the system clock regestration function, alt_sysclk_init(). + */ + +extern void alt_avalon_timer_sc_init (void* base, alt_u32 irq_controller_id, + alt_u32 irq, alt_u32 freq); + +/* + * Variables used to store the timestamp parameters, when the device is to be + * accessed using the high resolution timestamp driver. + */ + +extern void* altera_avalon_timer_ts_base; +extern alt_u32 altera_avalon_timer_ts_freq; + +/* + * ALTERA_AVALON_TIMER_INSTANCE is the macro used by alt_sys_init() to + * allocate any per device memory that may be required. In this case no + * allocation is necessary. + */ + +#define ALTERA_AVALON_TIMER_INSTANCE(name, dev) extern int alt_no_storage + +/* + * Macro used to calculate the timer interrupt frequency. Although this is + * somewhat fearsome, when compiled with -O2 it will be resolved at compile + * time to a constant value. + */ + +#define ALTERA_AVALON_TIMER_FREQ(freq, period, units) \ + strcmp (units, "us") ? \ + (strcmp (units, "ms") ? \ + (strcmp (units, "s") ? \ + ((freq + (period - 1))/period) \ + : 1) \ + : (1000 + (period - 1))/period) \ + : ((1000000 + (period - 1))/period) + +/* + * Construct macros which contain the base address of the system clock and the + * timestamp device. These are used below to determine which driver to use for + * a given timer. + */ + +#define __ALT_CLK_BASE(name) name##_BASE +#define _ALT_CLK_BASE(name) __ALT_CLK_BASE(name) + +#define ALT_SYS_CLK_BASE _ALT_CLK_BASE(ALT_SYS_CLK) +#define ALT_TIMESTAMP_CLK_BASE _ALT_CLK_BASE(ALT_TIMESTAMP_CLK) + +/* + * If there is no system clock, then the above macro will result in + * ALT_SYS_CLK_BASE being set to none_BASE. We therefore need to provide an + * invalid value for this, so that no timer is wrongly identified as the system + * clock. + */ + +#define none_BASE 0xffffffff + +/* + * ALTERA_AVALON_TIMER_INIT is the macro used by alt_sys_init() to provide + * the run time initialisation of the device. In this case this translates to + * a call to alt_avalon_timer_sc_init() if the device is the system clock, i.e. + * if it has the name "sysclk". + * + * If the device is not the system clock, then it is used to provide the + * timestamp facility. + * + * To ensure as much as possible is evaluated at compile time, rather than + * compare the name of the device to "/dev/sysclk" using strcmp(), the base + * address of the device is compared to SYSCLK_BASE to determine whether it's + * the system clock. Since the base address of a device must be unique, these + * two aproaches are equivalent. + * + * This macro performs a sanity check to ensure that the interrupt has been + * connected for this device. If not, then an apropriate error message is + * generated at build time. + */ + + +#define ALTERA_AVALON_TIMER_INIT(name, dev) \ + if (name##_BASE == ALT_SYS_CLK_BASE) \ + { \ + if (name##_IRQ == ALT_IRQ_NOT_CONNECTED) \ + { \ + ALT_LINK_ERROR ("Error: Interrupt not connected for " #dev ". " \ + "The system clock driver requires an interrupt to be " \ + "connected. Please select an IRQ for this device in " \ + "SOPC builder."); \ + } \ + else \ + { \ + alt_avalon_timer_sc_init((void*) name##_BASE, \ + name##_IRQ_INTERRUPT_CONTROLLER_ID, \ + name##_IRQ, \ + ALTERA_AVALON_TIMER_FREQ(name##_FREQ, \ + name##_PERIOD, \ + name##_PERIOD_UNITS));\ + } \ + } \ + else if (name##_BASE == ALT_TIMESTAMP_CLK_BASE) \ + { \ + if (name##_SNAPSHOT) \ + { \ + altera_avalon_timer_ts_base = (void*) name##_BASE; \ + altera_avalon_timer_ts_freq = name##_FREQ; \ + } \ + else \ + { \ + ALT_LINK_ERROR ("Error: Snapshot register not available for " \ + #dev ". " \ + "The timestamp driver requires the snapshot register " \ + "to be readable. Please enable this register for this " \ + "device in SOPC builder."); \ + } \ + } + +/* + * + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALT_AVALON_TIMER_H__ */ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/drivers/inc/altera_avalon_timer_regs.h b/MCandWifiTestDE0/Software/MCTest_bsp/drivers/inc/altera_avalon_timer_regs.h new file mode 100644 index 00000000..37bb44d8 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/drivers/inc/altera_avalon_timer_regs.h @@ -0,0 +1,202 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#ifndef __ALTERA_AVALON_TIMER_REGS_H__ +#define __ALTERA_AVALON_TIMER_REGS_H__ + +#include + +/* STATUS register */ +#define ALTERA_AVALON_TIMER_STATUS_REG 0 +#define IOADDR_ALTERA_AVALON_TIMER_STATUS(base) \ + __IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_STATUS_REG) +#define IORD_ALTERA_AVALON_TIMER_STATUS(base) \ + IORD(base, ALTERA_AVALON_TIMER_STATUS_REG) +#define IOWR_ALTERA_AVALON_TIMER_STATUS(base, data) \ + IOWR(base, ALTERA_AVALON_TIMER_STATUS_REG, data) +#define ALTERA_AVALON_TIMER_STATUS_TO_MSK (0x1) +#define ALTERA_AVALON_TIMER_STATUS_TO_OFST (0) +#define ALTERA_AVALON_TIMER_STATUS_RUN_MSK (0x2) +#define ALTERA_AVALON_TIMER_STATUS_RUN_OFST (1) + +/* CONTROL register */ +#define ALTERA_AVALON_TIMER_CONTROL_REG 1 +#define IOADDR_ALTERA_AVALON_TIMER_CONTROL(base) \ + __IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_CONTROL_REG) +#define IORD_ALTERA_AVALON_TIMER_CONTROL(base) \ + IORD(base, ALTERA_AVALON_TIMER_CONTROL_REG) +#define IOWR_ALTERA_AVALON_TIMER_CONTROL(base, data) \ + IOWR(base, ALTERA_AVALON_TIMER_CONTROL_REG, data) +#define ALTERA_AVALON_TIMER_CONTROL_ITO_MSK (0x1) +#define ALTERA_AVALON_TIMER_CONTROL_ITO_OFST (0) +#define ALTERA_AVALON_TIMER_CONTROL_CONT_MSK (0x2) +#define ALTERA_AVALON_TIMER_CONTROL_CONT_OFST (1) +#define ALTERA_AVALON_TIMER_CONTROL_START_MSK (0x4) +#define ALTERA_AVALON_TIMER_CONTROL_START_OFST (2) +#define ALTERA_AVALON_TIMER_CONTROL_STOP_MSK (0x8) +#define ALTERA_AVALON_TIMER_CONTROL_STOP_OFST (3) + +/* Period and SnapShot Register for COUNTER_SIZE = 32 */ +/*----------------------------------------------------*/ +/* PERIODL register */ +#define ALTERA_AVALON_TIMER_PERIODL_REG 2 +#define IOADDR_ALTERA_AVALON_TIMER_PERIODL(base) \ + __IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_PERIODL_REG) +#define IORD_ALTERA_AVALON_TIMER_PERIODL(base) \ + IORD(base, ALTERA_AVALON_TIMER_PERIODL_REG) +#define IOWR_ALTERA_AVALON_TIMER_PERIODL(base, data) \ + IOWR(base, ALTERA_AVALON_TIMER_PERIODL_REG, data) +#define ALTERA_AVALON_TIMER_PERIODL_MSK (0xFFFF) +#define ALTERA_AVALON_TIMER_PERIODL_OFST (0) + +/* PERIODH register */ +#define ALTERA_AVALON_TIMER_PERIODH_REG 3 +#define IOADDR_ALTERA_AVALON_TIMER_PERIODH(base) \ + __IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_PERIODH_REG) +#define IORD_ALTERA_AVALON_TIMER_PERIODH(base) \ + IORD(base, ALTERA_AVALON_TIMER_PERIODH_REG) +#define IOWR_ALTERA_AVALON_TIMER_PERIODH(base, data) \ + IOWR(base, ALTERA_AVALON_TIMER_PERIODH_REG, data) +#define ALTERA_AVALON_TIMER_PERIODH_MSK (0xFFFF) +#define ALTERA_AVALON_TIMER_PERIODH_OFST (0) + +/* SNAPL register */ +#define ALTERA_AVALON_TIMER_SNAPL_REG 4 +#define IOADDR_ALTERA_AVALON_TIMER_SNAPL(base) \ + __IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_SNAPL_REG) +#define IORD_ALTERA_AVALON_TIMER_SNAPL(base) \ + IORD(base, ALTERA_AVALON_TIMER_SNAPL_REG) +#define IOWR_ALTERA_AVALON_TIMER_SNAPL(base, data) \ + IOWR(base, ALTERA_AVALON_TIMER_SNAPL_REG, data) +#define ALTERA_AVALON_TIMER_SNAPL_MSK (0xFFFF) +#define ALTERA_AVALON_TIMER_SNAPL_OFST (0) + +/* SNAPH register */ +#define ALTERA_AVALON_TIMER_SNAPH_REG 5 +#define IOADDR_ALTERA_AVALON_TIMER_SNAPH(base) \ + __IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_SNAPH_REG) +#define IORD_ALTERA_AVALON_TIMER_SNAPH(base) \ + IORD(base, ALTERA_AVALON_TIMER_SNAPH_REG) +#define IOWR_ALTERA_AVALON_TIMER_SNAPH(base, data) \ + IOWR(base, ALTERA_AVALON_TIMER_SNAPH_REG, data) +#define ALTERA_AVALON_TIMER_SNAPH_MSK (0xFFFF) +#define ALTERA_AVALON_TIMER_SNAPH_OFST (0) + +/* Period and SnapShot Register for COUNTER_SIZE = 64 */ +/*----------------------------------------------------*/ +/* PERIOD_0 register */ +#define ALTERA_AVALON_TIMER_PERIOD_0_REG 2 +#define IOADDR_ALTERA_AVALON_TIMER_PERIOD_0(base) \ + __IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_PERIOD_0_REG) +#define IORD_ALTERA_AVALON_TIMER_PERIOD_0(base) \ + IORD(base, ALTERA_AVALON_TIMER_PERIOD_0_REG) +#define IOWR_ALTERA_AVALON_TIMER_PERIOD_0(base, data) \ + IOWR(base, ALTERA_AVALON_TIMER_PERIOD_0_REG, data) +#define ALTERA_AVALON_TIMER_PERIOD_0_MSK (0xFFFF) +#define ALTERA_AVALON_TIMER_PERIOD_0_OFST (0) + +/* PERIOD_1 register */ +#define ALTERA_AVALON_TIMER_PERIOD_1_REG 3 +#define IOADDR_ALTERA_AVALON_TIMER_PERIOD_1(base) \ + __IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_PERIOD_1_REG) +#define IORD_ALTERA_AVALON_TIMER_PERIOD_1(base) \ + IORD(base, ALTERA_AVALON_TIMER_PERIOD_1_REG) +#define IOWR_ALTERA_AVALON_TIMER_PERIOD_1(base, data) \ + IOWR(base, ALTERA_AVALON_TIMER_PERIOD_1_REG, data) +#define ALTERA_AVALON_TIMER_PERIOD_1_MSK (0xFFFF) +#define ALTERA_AVALON_TIMER_PERIOD_1_OFST (0) + +/* PERIOD_2 register */ +#define ALTERA_AVALON_TIMER_PERIOD_2_REG 4 +#define IOADDR_ALTERA_AVALON_TIMER_PERIOD_2(base) \ + __IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_PERIOD_2_REG) +#define IORD_ALTERA_AVALON_TIMER_PERIOD_2(base) \ + IORD(base, ALTERA_AVALON_TIMER_PERIOD_2_REG) +#define IOWR_ALTERA_AVALON_TIMER_PERIOD_2(base, data) \ + IOWR(base, ALTERA_AVALON_TIMER_PERIOD_2_REG, data) +#define ALTERA_AVALON_TIMER_PERIOD_2_MSK (0xFFFF) +#define ALTERA_AVALON_TIMER_PERIOD_2_OFST (0) + +/* PERIOD_3 register */ +#define ALTERA_AVALON_TIMER_PERIOD_3_REG 5 +#define IOADDR_ALTERA_AVALON_TIMER_PERIOD_3(base) \ + __IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_PERIOD_3_REG) +#define IORD_ALTERA_AVALON_TIMER_PERIOD_3(base) \ + IORD(base, ALTERA_AVALON_TIMER_PERIOD_3_REG) +#define IOWR_ALTERA_AVALON_TIMER_PERIOD_3(base, data) \ + IOWR(base, ALTERA_AVALON_TIMER_PERIOD_3_REG, data) +#define ALTERA_AVALON_TIMER_PERIOD_3_MSK (0xFFFF) +#define ALTERA_AVALON_TIMER_PERIOD_3_OFST (0) + +/* SNAP_0 register */ +#define ALTERA_AVALON_TIMER_SNAP_0_REG 6 +#define IOADDR_ALTERA_AVALON_TIMER_SNAP_0(base) \ + __IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_SNAP_0_REG) +#define IORD_ALTERA_AVALON_TIMER_SNAP_0(base) \ + IORD(base, ALTERA_AVALON_TIMER_SNAP_0_REG) +#define IOWR_ALTERA_AVALON_TIMER_SNAP_0(base, data) \ + IOWR(base, ALTERA_AVALON_TIMER_SNAP_0_REG, data) +#define ALTERA_AVALON_TIMER_SNAP_0_MSK (0xFFFF) +#define ALTERA_AVALON_TIMER_SNAP_0_OFST (0) + +/* SNAP_1 register */ +#define ALTERA_AVALON_TIMER_SNAP_1_REG 7 +#define IOADDR_ALTERA_AVALON_TIMER_SNAP_1(base) \ + __IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_SNAP_1_REG) +#define IORD_ALTERA_AVALON_TIMER_SNAP_1(base) \ + IORD(base, ALTERA_AVALON_TIMER_SNAP_1_REG) +#define IOWR_ALTERA_AVALON_TIMER_SNAP_1(base, data) \ + IOWR(base, ALTERA_AVALON_TIMER_SNAP_1_REG, data) +#define ALTERA_AVALON_TIMER_SNAP_1_MSK (0xFFFF) +#define ALTERA_AVALON_TIMER_SNAP_1_OFST (0) + +/* SNAP_2 register */ +#define ALTERA_AVALON_TIMER_SNAP_2_REG 8 +#define IOADDR_ALTERA_AVALON_TIMER_SNAP_2(base) \ + __IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_SNAP_2_REG) +#define IORD_ALTERA_AVALON_TIMER_SNAP_2(base) \ + IORD(base, ALTERA_AVALON_TIMER_SNAP_2_REG) +#define IOWR_ALTERA_AVALON_TIMER_SNAP_2(base, data) \ + IOWR(base, ALTERA_AVALON_TIMER_SNAP_2_REG, data) +#define ALTERA_AVALON_TIMER_SNAP_2_MSK (0xFFFF) +#define ALTERA_AVALON_TIMER_SNAP_2_OFST (0) + +/* SNAP_3 register */ +#define ALTERA_AVALON_TIMER_SNAP_3_REG 9 +#define IOADDR_ALTERA_AVALON_TIMER_SNAP_3(base) \ + __IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_SNAP_3_REG) +#define IORD_ALTERA_AVALON_TIMER_SNAP_3(base) \ + IORD(base, ALTERA_AVALON_TIMER_SNAP_3_REG) +#define IOWR_ALTERA_AVALON_TIMER_SNAP_3(base, data) \ + IOWR(base, ALTERA_AVALON_TIMER_SNAP_3_REG, data) +#define ALTERA_AVALON_TIMER_SNAP_3_MSK (0xFFFF) +#define ALTERA_AVALON_TIMER_SNAP_3_OFST (0) + +#endif /* __ALTERA_AVALON_TIMER_REGS_H__ */ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/drivers/inc/altera_avalon_uart.h b/MCandWifiTestDE0/Software/MCTest_bsp/drivers/inc/altera_avalon_uart.h new file mode 100644 index 00000000..d1f7d32f --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/drivers/inc/altera_avalon_uart.h @@ -0,0 +1,319 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#ifndef __ALT_AVALON_UART_H__ +#define __ALT_AVALON_UART_H__ + +#include +#include + +#include "sys/alt_warning.h" + +#include "os/alt_sem.h" +#include "os/alt_flag.h" +#include "alt_types.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +#if defined(ALT_USE_SMALL_DRIVERS) || defined(ALTERA_AVALON_UART_SMALL) + +/* + *********************************************************************** + *********************** SMALL DRIVER ********************************** + *********************************************************************** + */ + +/* + * State structure definition. Each instance of the driver uses one + * of these structures to hold its associated state. + */ + +typedef struct altera_avalon_uart_state_s +{ + unsigned int base; +} altera_avalon_uart_state; + +/* + * The macro ALTERA_AVALON_UART_STATE_INSTANCE is used by the + * auto-generated file alt_sys_init.c to create an instance of this + * device driver state. + */ + +#define ALTERA_AVALON_UART_STATE_INSTANCE(name, state) \ + altera_avalon_uart_state state = \ + { \ + name##_BASE \ + } + +/* + * The macro ALTERA_AVALON_UART_STATE_INIT is used by the auto-generated file + * alt_sys_init.c to initialize an instance of the device driver state. + */ + +#define ALTERA_AVALON_UART_STATE_INIT(name, state) + +#else /* fast driver */ + +/* + ********************************************************************** + *********************** FAST DRIVER ********************************** + ********************************************************************** + */ + +/* + * ALT_AVALON_UART_READ_RDY and ALT_AVALON_UART_WRITE_RDY are the bitmasks + * that define uC/OS-II event flags that are releated to this device. + * + * ALT_AVALON_UART_READY_RDY indicates that there is read data in the buffer + * ready to be processed. ALT_UART_WRITE_RDY indicates that the transmitter is + * ready for more data. + */ + +#define ALT_UART_READ_RDY 0x1 +#define ALT_UART_WRITE_RDY 0x2 + +/* + * ALT_AVALON_UART_BUF_LEN is the length of the circular buffers used to hold + * pending transmit and receive data. This value must be a power of two. + */ + +#define ALT_AVALON_UART_BUF_LEN (64) + +/* + * ALT_AVALON_UART_BUF_MSK is used as an internal convenience for detecting + * the end of the arrays used to implement the transmit and receive buffers. + */ + +#define ALT_AVALON_UART_BUF_MSK (ALT_AVALON_UART_BUF_LEN - 1) + +/* + * This is somewhat of an ugly hack, but we need some mechanism for + * representing the non-standard 9 bit mode provided by this UART. In this + * case we abscond with the 5 bit mode setting. The value CS5 is defined in + * termios.h. + */ + +#define CS9 CS5 + +/* + * The value ALT_AVALON_UART_FB is a value set in the devices flag field to + * indicate that the device has a fixed baud rate; i.e. if this flag is set + * software can not control the baud rate of the device. + */ + +#define ALT_AVALON_UART_FB 0x1 + +/* + * The value ALT_AVALON_UART_FC is a value set in the device flag field to + * indicate the the device is using flow control, i.e. the driver must + * throttle on transmit if the nCTS pin is low. + */ + +#define ALT_AVALON_UART_FC 0x2 + +/* + * The altera_avalon_uart_state structure is used to hold device specific data. + * This includes the transmit and receive buffers. + * + * An instance of this structure is created in the auto-generated + * alt_sys_init.c file for each UART listed in the systems PTF file. This is + * done using the ALTERA_AVALON_UART_STATE_INSTANCE macro given below. + */ + +typedef struct altera_avalon_uart_state_s +{ + void* base; /* The base address of the device */ + alt_u32 ctrl; /* Shadow value of the control register */ + alt_u32 rx_start; /* Start of the pending receive data */ + volatile alt_u32 rx_end; /* End of the pending receive data */ + volatile alt_u32 tx_start; /* Start of the pending transmit data */ + alt_u32 tx_end; /* End of the pending transmit data */ +#ifdef ALTERA_AVALON_UART_USE_IOCTL + struct termios termios; /* Current device configuration */ + alt_u32 freq; /* Current baud rate */ +#endif + alt_u32 flags; /* Configuation flags */ + ALT_FLAG_GRP (events) /* Event flags used for + * foreground/background in mult-threaded + * mode */ + ALT_SEM (read_lock) /* Semaphore used to control access to the + * read buffer in multi-threaded mode */ + ALT_SEM (write_lock) /* Semaphore used to control access to the + * write buffer in multi-threaded mode */ + alt_u8 rx_buf[ALT_AVALON_UART_BUF_LEN]; /* The receive buffer */ + alt_u8 tx_buf[ALT_AVALON_UART_BUF_LEN]; /* The transmit buffer */ +} altera_avalon_uart_state; + +/* + * Conditionally define the data structures used to process ioctl requests. + * The following macros are defined for use in creating a device instance: + * + * ALTERA_AVALON_UART_TERMIOS - Initialise the termios structure used to + * describe the UART configuration. + * ALTERA_AVALON_UART_FREQ - Initialise the 'freq' field of the device + * structure, if the field exists. + * ALTERA_AVALON_UART_IOCTL - Initialise the 'ioctl' field of the device + * callback structure, if ioctls are enabled. + */ + +#ifdef ALTERA_AVALON_UART_USE_IOCTL + +#define ALTERA_AVALON_UART_TERMIOS(stop_bits, \ + parity, \ + odd_parity, \ + data_bits, \ + ctsrts, \ + baud) \ +{ \ + 0, \ + 0, \ + ((stop_bits == 2) ? CSTOPB: 0) | \ + ((parity) ? PARENB: 0) | \ + ((odd_parity) ? PAODD: 0) | \ + ((data_bits == 7) ? CS7: (data_bits == 9) ? CS9: CS8) | \ + ((ctsrts) ? CRTSCTS : 0), \ + 0, \ + 0, \ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, \ + baud, \ + baud \ +}, +#define ALTERA_AVALON_UART_FREQ(name) name##_FREQ, + +#else /* !ALTERA_AVALON_UART_USE_IOCTL */ + +#define ALTERA_AVALON_UART_TERMIOS(stop_bits, \ + parity, \ + odd_parity, \ + data_bits, \ + ctsrts, \ + baud) +#define ALTERA_AVALON_UART_FREQ(name) + +#endif /* ALTERA_AVALON_UART_USE_IOCTL */ + +/* + * The macro ALTERA_AVALON_UART_INSTANCE is used by the auto-generated file + * alt_sys_init.c to create an instance of this device driver state. + */ + +#define ALTERA_AVALON_UART_STATE_INSTANCE(name, state) \ + altera_avalon_uart_state state = \ + { \ + (void*) name##_BASE, \ + 0, \ + 0, \ + 0, \ + 0, \ + 0, \ + ALTERA_AVALON_UART_TERMIOS(name##_STOP_BITS, \ + (name##_PARITY == 'N'), \ + (name##_PARITY == 'O'), \ + name##_DATA_BITS, \ + name##_USE_CTS_RTS, \ + name##_BAUD) \ + ALTERA_AVALON_UART_FREQ(name) \ + (name##_FIXED_BAUD ? ALT_AVALON_UART_FB : 0) | \ + (name##_USE_CTS_RTS ? ALT_AVALON_UART_FC : 0) \ + } + +/* + * altera_avalon_uart_init() is called by the auto-generated function + * alt_sys_init() for each UART in the system. This is done using the + * ALTERA_AVALON_UART_INIT macro given below. + * + * This function is responsible for performing all the run time initilisation + * for a device instance, i.e. registering the interrupt handler, and + * regestering the device with the system. + */ +extern void altera_avalon_uart_init(altera_avalon_uart_state* sp, + alt_u32 irq_controller_id, alt_u32 irq); + +/* + * The macro ALTERA_AVALON_UART_STATE_INIT is used by the auto-generated file + * alt_sys_init.c to initialize an instance of the device driver state. + * + * This macro performs a sanity check to ensure that the interrupt has been + * connected for this device. If not, then an apropriate error message is + * generated at build time. + */ + +#define ALTERA_AVALON_UART_STATE_INIT(name, state) \ + if (name##_IRQ == ALT_IRQ_NOT_CONNECTED) \ + { \ + ALT_LINK_ERROR ("Error: Interrupt not connected for " #name ". " \ + "You have selected the interrupt driven version of " \ + "the ALTERA Avalon UART driver, but the interrupt is " \ + "not connected for this device. You can select a " \ + "polled mode driver by checking the 'small driver' " \ + "option in the HAL configuration window, or by " \ + "using the -DALTERA_AVALON_UART_SMALL preprocessor " \ + "flag."); \ + } \ + else \ + { \ + altera_avalon_uart_init(&state, name##_IRQ_INTERRUPT_CONTROLLER_ID, \ + name##_IRQ); \ + } + +#endif /* small driver */ + +/* + * Include in case non-direct version of driver required. + */ +#include "altera_avalon_uart_fd.h" + +/* + * Map alt_sys_init macros to direct or non-direct versions. + */ +#ifdef ALT_USE_DIRECT_DRIVERS + +#define ALTERA_AVALON_UART_INSTANCE(name, state) \ + ALTERA_AVALON_UART_STATE_INSTANCE(name, state) +#define ALTERA_AVALON_UART_INIT(name, state) \ + ALTERA_AVALON_UART_STATE_INIT(name, state) + +#else /* !ALT_USE_DIRECT_DRIVERS */ + +#define ALTERA_AVALON_UART_INSTANCE(name, dev) \ + ALTERA_AVALON_UART_DEV_INSTANCE(name, dev) +#define ALTERA_AVALON_UART_INIT(name, dev) \ + ALTERA_AVALON_UART_DEV_INIT(name, dev) + +#endif /* ALT_USE_DIRECT_DRIVERS */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALT_AVALON_UART_H__ */ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/drivers/inc/altera_avalon_uart_fd.h b/MCandWifiTestDE0/Software/MCTest_bsp/drivers/inc/altera_avalon_uart_fd.h new file mode 100644 index 00000000..92c8731d --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/drivers/inc/altera_avalon_uart_fd.h @@ -0,0 +1,143 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2007 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#ifndef __ALT_AVALON_UART_FD_H__ +#define __ALT_AVALON_UART_FD_H__ + +#include "sys/alt_dev.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Externally referenced routines + */ +extern int altera_avalon_uart_read_fd (alt_fd* fd, char* ptr, int len); +extern int altera_avalon_uart_write_fd (alt_fd* fd, const char* ptr, + int len); + +/* + * Device structure definition. This is needed by alt_sys_init in order to + * reserve memory for the device instance. + */ +typedef struct altera_avalon_uart_dev_s +{ + alt_dev dev; + altera_avalon_uart_state state; +} altera_avalon_uart_dev; + +#if defined(ALT_USE_SMALL_DRIVERS) || defined(ALTERA_AVALON_UART_SMALL) + +/* + * Macros used by alt_sys_init when the ALT file descriptor facility is used. + */ + +#define ALTERA_AVALON_UART_DEV_INSTANCE(name, d) \ + static altera_avalon_uart_dev d = \ + { \ + { \ + ALT_LLIST_ENTRY, \ + name##_NAME, \ + NULL, /* open */ \ + NULL, /* close */ \ + altera_avalon_uart_read_fd, \ + altera_avalon_uart_write_fd, \ + NULL, /* lseek */ \ + NULL, /* fstat */ \ + NULL, /* ioctl */ \ + }, \ + { \ + name##_BASE, \ + } \ + } + +#define ALTERA_AVALON_UART_DEV_INIT(name, d) alt_dev_reg (&d.dev) + +#else /* use fast version of the driver */ + +extern int altera_avalon_uart_ioctl_fd (alt_fd* fd, int req, void* arg); +extern int altera_avalon_uart_close_fd(alt_fd* fd); + +#ifdef ALTERA_AVALON_UART_USE_IOCTL +#define ALTERA_AVALON_UART_IOCTL_FD altera_avalon_uart_ioctl_fd +#else +#define ALTERA_AVALON_UART_IOCTL_FD NULL +#endif + +#define ALTERA_AVALON_UART_DEV_INSTANCE(name, d) \ + static altera_avalon_uart_dev d = \ + { \ + { \ + ALT_LLIST_ENTRY, \ + name##_NAME, \ + NULL, /* open */ \ + altera_avalon_uart_close_fd, \ + altera_avalon_uart_read_fd, \ + altera_avalon_uart_write_fd, \ + NULL, /* lseek */ \ + NULL, /* fstat */ \ + ALTERA_AVALON_UART_IOCTL_FD, \ + }, \ + { \ + (void*) name##_BASE, \ + 0, \ + 0, \ + 0, \ + 0, \ + 0, \ + ALTERA_AVALON_UART_TERMIOS(name##_STOP_BITS, \ + (name##_PARITY == 'N'), \ + (name##_PARITY == 'O'), \ + name##_DATA_BITS, \ + name##_USE_CTS_RTS, \ + name##_BAUD) \ + ALTERA_AVALON_UART_FREQ(name) \ + (name##_FIXED_BAUD ? ALT_AVALON_UART_FB : 0) | \ + (name##_USE_CTS_RTS ? ALT_AVALON_UART_FC : 0) \ + } \ + } + +#define ALTERA_AVALON_UART_DEV_INIT(name, d) \ + { \ + ALTERA_AVALON_UART_STATE_INIT(name, d.state); \ + \ + /* make the device available to the system */ \ + alt_dev_reg(&d.dev); \ + } + +#endif /* fast driver */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALT_AVALON_UART_FD_H__ */ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/drivers/inc/altera_avalon_uart_regs.h b/MCandWifiTestDE0/Software/MCTest_bsp/drivers/inc/altera_avalon_uart_regs.h new file mode 100644 index 00000000..9aa4a03a --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/drivers/inc/altera_avalon_uart_regs.h @@ -0,0 +1,137 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#ifndef __ALTERA_AVALON_UART_REGS_H__ +#define __ALTERA_AVALON_UART_REGS_H__ + +#include + +#define ALTERA_AVALON_UART_RXDATA_REG 0 +#define IOADDR_ALTERA_AVALON_UART_RXDATA(base) \ + __IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_UART_RXDATA_REG) +#define IORD_ALTERA_AVALON_UART_RXDATA(base) \ + IORD(base, ALTERA_AVALON_UART_RXDATA_REG) +#define IOWR_ALTERA_AVALON_UART_RXDATA(base, data) \ + IOWR(base, ALTERA_AVALON_UART_RXDATA_REG, data) + +#define ALTERA_AVALON_UART_TXDATA_REG 1 +#define IOADDR_ALTERA_AVALON_UART_TXDATA(base) \ + __IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_UART_TXDATA_REG) +#define IORD_ALTERA_AVALON_UART_TXDATA(base) \ + IORD(base, ALTERA_AVALON_UART_TXDATA_REG) +#define IOWR_ALTERA_AVALON_UART_TXDATA(base, data) \ + IOWR(base, ALTERA_AVALON_UART_TXDATA_REG, data) + +#define ALTERA_AVALON_UART_STATUS_REG 2 +#define IOADDR_ALTERA_AVALON_UART_STATUS(base) \ + __IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_UART_STATUS_REG) +#define IORD_ALTERA_AVALON_UART_STATUS(base) \ + IORD(base, ALTERA_AVALON_UART_STATUS_REG) +#define IOWR_ALTERA_AVALON_UART_STATUS(base, data) \ + IOWR(base, ALTERA_AVALON_UART_STATUS_REG, data) + +#define ALTERA_AVALON_UART_STATUS_PE_MSK (0x1) +#define ALTERA_AVALON_UART_STATUS_PE_OFST (0) +#define ALTERA_AVALON_UART_STATUS_FE_MSK (0x2) +#define ALTERA_AVALON_UART_STATUS_FE_OFST (1) +#define ALTERA_AVALON_UART_STATUS_BRK_MSK (0x4) +#define ALTERA_AVALON_UART_STATUS_BRK_OFST (2) +#define ALTERA_AVALON_UART_STATUS_ROE_MSK (0x8) +#define ALTERA_AVALON_UART_STATUS_ROE_OFST (3) +#define ALTERA_AVALON_UART_STATUS_TOE_MSK (0x10) +#define ALTERA_AVALON_UART_STATUS_TOE_OFST (4) +#define ALTERA_AVALON_UART_STATUS_TMT_MSK (0x20) +#define ALTERA_AVALON_UART_STATUS_TMT_OFST (5) +#define ALTERA_AVALON_UART_STATUS_TRDY_MSK (0x40) +#define ALTERA_AVALON_UART_STATUS_TRDY_OFST (6) +#define ALTERA_AVALON_UART_STATUS_RRDY_MSK (0x80) +#define ALTERA_AVALON_UART_STATUS_RRDY_OFST (7) +#define ALTERA_AVALON_UART_STATUS_E_MSK (0x100) +#define ALTERA_AVALON_UART_STATUS_E_OFST (8) +#define ALTERA_AVALON_UART_STATUS_DCTS_MSK (0x400) +#define ALTERA_AVALON_UART_STATUS_DCTS_OFST (10) +#define ALTERA_AVALON_UART_STATUS_CTS_MSK (0x800) +#define ALTERA_AVALON_UART_STATUS_CTS_OFST (11) +#define ALTERA_AVALON_UART_STATUS_EOP_MSK (0x1000) +#define ALTERA_AVALON_UART_STATUS_EOP_OFST (12) + +#define ALTERA_AVALON_UART_CONTROL_REG 3 +#define IOADDR_ALTERA_AVALON_UART_CONTROL(base) \ + __IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_UART_CONTROL_REG) +#define IORD_ALTERA_AVALON_UART_CONTROL(base) \ + IORD(base, ALTERA_AVALON_UART_CONTROL_REG) +#define IOWR_ALTERA_AVALON_UART_CONTROL(base, data) \ + IOWR(base, ALTERA_AVALON_UART_CONTROL_REG, data) + +#define ALTERA_AVALON_UART_CONTROL_PE_MSK (0x1) +#define ALTERA_AVALON_UART_CONTROL_PE_OFST (0) +#define ALTERA_AVALON_UART_CONTROL_FE_MSK (0x2) +#define ALTERA_AVALON_UART_CONTROL_FE_OFST (1) +#define ALTERA_AVALON_UART_CONTROL_BRK_MSK (0x4) +#define ALTERA_AVALON_UART_CONTROL_BRK_OFST (2) +#define ALTERA_AVALON_UART_CONTROL_ROE_MSK (0x8) +#define ALTERA_AVALON_UART_CONTROL_ROE_OFST (3) +#define ALTERA_AVALON_UART_CONTROL_TOE_MSK (0x10) +#define ALTERA_AVALON_UART_CONTROL_TOE_OFST (4) +#define ALTERA_AVALON_UART_CONTROL_TMT_MSK (0x20) +#define ALTERA_AVALON_UART_CONTROL_TMT_OFST (5) +#define ALTERA_AVALON_UART_CONTROL_TRDY_MSK (0x40) +#define ALTERA_AVALON_UART_CONTROL_TRDY_OFST (6) +#define ALTERA_AVALON_UART_CONTROL_RRDY_MSK (0x80) +#define ALTERA_AVALON_UART_CONTROL_RRDY_OFST (7) +#define ALTERA_AVALON_UART_CONTROL_E_MSK (0x100) +#define ALTERA_AVALON_UART_CONTROL_E_OFST (8) +#define ALTERA_AVALON_UART_CONTROL_DCTS_MSK (0x400) +#define ALTERA_AVALON_UART_CONTROL_DCTS_OFST (10) +#define ALTERA_AVALON_UART_CONTROL_RTS_MSK (0x800) +#define ALTERA_AVALON_UART_CONTROL_RTS_OFST (11) +#define ALTERA_AVALON_UART_CONTROL_EOP_MSK (0x1000) +#define ALTERA_AVALON_UART_CONTROL_EOP_OFST (12) + +#define ALTERA_AVALON_UART_DIVISOR_REG 4 +#define IOADDR_ALTERA_AVALON_UART_DIVISOR(base) \ + __IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_UART_DIVISOR_REG) +#define IORD_ALTERA_AVALON_UART_DIVISOR(base) \ + IORD(base, ALTERA_AVALON_UART_DIVISOR_REG) +#define IOWR_ALTERA_AVALON_UART_DIVISOR(base, data) \ + IOWR(base, ALTERA_AVALON_UART_DIVISOR_REG, data) + +#define ALTERA_AVALON_UART_EOP_REG 5 +#define IOADDR_ALTERA_AVALON_UART_EOP(base) \ + __IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_UART_EOP_REG) +#define IORD_ALTERA_AVALON_UART_EOP(base) \ + IORD(base, ALTERA_AVALON_UART_EOP_REG) +#define IOWR_ALTERA_AVALON_UART_EOP(base, data) \ + IOWR(base, ALTERA_AVALON_UART_EOP_REG, data) + +#define ALTERA_AVALON_UART_EOP_MSK (0xFF) +#define ALTERA_AVALON_UART_EOP_OFST (0) + +#endif /* __ALTERA_AVALON_UART_REGS_H__ */ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/drivers/inc/altera_up_avalon_rs232.h b/MCandWifiTestDE0/Software/MCTest_bsp/drivers/inc/altera_up_avalon_rs232.h new file mode 100644 index 00000000..53b1ec3e --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/drivers/inc/altera_up_avalon_rs232.h @@ -0,0 +1,182 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2007 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +* * +******************************************************************************/ + +#ifndef __ALTERA_UP_AVALON_RS232_H__ +#define __ALTERA_UP_AVALON_RS232_H__ + +#include +#include +#include + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/* + * Device structure definition. Each instance of the driver uses one + * of these structures to hold its associated state. + */ +typedef struct alt_up_rs232_dev { + /// @brief character mode device structure + /// @sa Developing Device Drivers for the HAL in Nios II Software Developer's Handbook + alt_dev dev; + /// @brief the base address of the device + unsigned int base; +} alt_up_rs232_dev; + + +////////////////////////////////////////////////////////////////////////// +// HAL system functions + +/** + * @brief Enable the read interrupts for the RS232 UART core. + * + * @param rs232 -- the RS232 device structure + **/ +void alt_up_rs232_enable_read_interrupt(alt_up_rs232_dev *rs232); + +/** + * @brief Disable the read interrupts for the RS232 UART core. + * + * @param rs232 -- the RS232 device structure + * + **/ +void alt_up_rs232_disable_read_interrupt(alt_up_rs232_dev *rs232); + +/** + * @brief Check whether the DATA field has a parity error. + * + * @param data_reg -- the date register + * + * @return 0 for no errors, \f$-1\f$ for parity error. + **/ +int alt_up_rs232_check_parity(alt_u32 data_reg); + +/** + * @brief Gets the number of data words remaining in the read FIFO. + * + * @param rs232 -- the RS232 device structure + * + * @return The number of data words remaining. + **/ +unsigned alt_up_rs232_get_used_space_in_read_FIFO(alt_up_rs232_dev *rs232); + +/** + * @brief Gets the amount of available space remaining in the write FIFO. + * + * @param rs232 -- the RS232 device structure + * + * @return The amount of available space remaining. + **/ +unsigned alt_up_rs232_get_available_space_in_write_FIFO(alt_up_rs232_dev *rs232); + +/** + * @brief Write data to the RS232 UART core. + * + * @param rs232 -- the RS232 device structure + * @param data -- the character to be transferred to the RS232 UART Core. + * + * @note User should ensure the write FIFO is not full before writing, otherwise the character is lost. + * + * @return 0 for success or \f$-1\f$ on error. + **/ +int alt_up_rs232_write_data(alt_up_rs232_dev *rs232, alt_u8 data); + +/** + * @brief Read data from the RS232 UART core. + * + * @param rs232 -- the RS232 device structure + * @param data -- pointer to the memory where the character read from the RS232 UART core should be stored. + * @param parity_error -- pointer to the memory where the parity error should be stored. + * + * @return 0 for success or \f$-1\f$ on error. + * + * @note This function will clear the DATA field of the data register after reading and it + * uses the \c alt_up_rs232_check_parity function to check the parity for the + * DATA field. + **/ +int alt_up_rs232_read_data(alt_up_rs232_dev *rs232, alt_u8 *data, alt_u8 *parity_error); + +////////////////////////////////////////////////////////////////////////// +// file-like operation functions +int alt_up_rs232_read_fd (alt_fd* fd, char* ptr, int len); +int alt_up_rs232_write_fd (alt_fd* fd, const char* ptr, int len); + +////////////////////////////////////////////////////////////////////////// +// direct operation functions + +/** + * @brief Open the RS232 device according to device name + * + * @param name -- the device name in SOPC Builder + * + * @return the \c alt_up_rs232_dev device structure + **/ +alt_up_rs232_dev* alt_up_rs232_open_dev(const char* name); + +/* + * Macros used by alt_sys_init + */ +#define ALTERA_UP_AVALON_RS232_INSTANCE(name, device) \ + static alt_up_rs232_dev device = \ + { \ + { \ + ALT_LLIST_ENTRY, \ + name##_NAME, \ + NULL , /* open */ \ + NULL , /* close */ \ + alt_up_rs232_read_fd , /* read */ \ + alt_up_rs232_write_fd , /* write */ \ + NULL , /* lseek */ \ + NULL , /* fstat */ \ + NULL , /* ioctl */ \ + }, \ + name##_BASE, \ + } + +#define ALTERA_UP_AVALON_RS232_INIT(name, device) \ + { \ + /* make the device available to the system */ \ + alt_dev_reg(&device.dev); \ + } + + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __ALTERA_UP_AVALON_RS232_H__ */ + + diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/drivers/inc/altera_up_avalon_rs232_regs.h b/MCandWifiTestDE0/Software/MCTest_bsp/drivers/inc/altera_up_avalon_rs232_regs.h new file mode 100644 index 00000000..00a1f236 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/drivers/inc/altera_up_avalon_rs232_regs.h @@ -0,0 +1,96 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#ifndef __ALT_UP_RS232_REGS_H__ +#define __ALT_UP_RS232_REGS_H__ +#include +#include + +#define IOWR_ALT_UP_RS232_ADDR(base, addr, data) \ + IOWR(base, addr, data) +/* + * Data Register + */ +#define ALT_UP_RS232_DATA_REG 0 + +#define IOADDR_ALT_UP_RS232_DATA(base) \ + __IO_CALC_ADDRESS_NATIVE(base, ALT_UP_RS232_DATA_REG) +#define IORD_ALT_UP_RS232_DATA(base) \ + IORD(base, ALT_UP_RS232_DATA_REG) +#define IOWR_ALT_UP_RS232_DATA(base, data) \ + IOWR(base, ALT_UP_RS232_DATA_REG, data) + +#define ALT_UP_RS232_DATA_DATA_MSK (0x000001FF) +#define ALT_UP_RS232_DATA_DATA_OFST (0) +#define ALT_UP_RS232_DATA_PE_MSK (0x00000200) +#define ALT_UP_RS232_DATA_PE_OFST (9) +#define ALT_UP_RS232_DATA_RVALID_MSK (0x00008000) +#define ALT_UP_RS232_DATA_RVALID_OFST (15) +#define ALT_UP_RS232_DATA_RAVAIL_MSK (0xFFFF0000) +#define ALT_UP_RS232_DATA_RAVAIL_OFST (16) + +#define ALT_UP_RS232_DATA_REG_RAVAIL 2 +#define IORD_ALT_UP_RS232_RAVAIL(base) \ + IORD_16DIRECT(base, ALT_UP_RS232_DATA_REG_RAVAIL) +#define ALT_UP_RS232_RAVAIL_MSK (0x0000FFFF) +#define ALT_UP_RS232_RAVAIL_OFST (0) + +#define ALT_UP_RS232_DATA_VALID_MSK (ALT_UP_RS232_DATA_DATA_MSK \ + | ALT_UP_RS232_DATA_PE_MSK \ + | ALT_UP_RS232_DATA_RAVAIL_MSK) +/* + * Control Register + */ +#define ALT_UP_RS232_CONTROL_REG 1 + +#define IOADDR_ALT_UP_RS232_CONTROL(base) \ + __IO_CALC_ADDRESS_NATIVE(base, ALT_UP_RS232_CONTROL_REG) +#define IORD_ALT_UP_RS232_CONTROL(base) \ + IORD(base, ALT_UP_RS232_CONTROL_REG) +#define IOWR_ALT_UP_RS232_CONTROL(base, data) \ + IOWR(base, ALT_UP_RS232_CONTROL_REG, data) + +#define ALT_UP_RS232_CONTROL_RE_MSK (0x00000001) +#define ALT_UP_RS232_CONTROL_RE_OFST (0) +#define ALT_UP_RS232_CONTROL_WE_MSK (0x00000002) +#define ALT_UP_RS232_CONTROL_WE_OFST (1) +#define ALT_UP_RS232_CONTROL_RI_MSK (0x00000100) +#define ALT_UP_RS232_CONTROL_RI_OFST (8) +#define ALT_UP_RS232_CONTROL_WI_MSK (0x00000200) +#define ALT_UP_RS232_CONTROL_WI_OFST (9) +#define ALT_UP_RS232_CONTROL_WSPACE_MSK (0xFFFF0000) +#define ALT_UP_RS232_CONTROL_WSPACE_OFST (16) + +#define ALT_UP_RS232_CONTROL_VALID_MSK (ALT_UP_RS232_CONTROL_RE_MSK \ + | ALT_UP_RS232_CONTROL_WE_MSK \ + | ALT_UP_RS232_CONTROL_RI_MSK \ + | ALT_UP_RS232_CONTROL_WI_MSK \ + | ALT_UP_RS232_CONTROL_WSPACE_MSK) +#endif /*__ALT_UP_RS232_REGS_H__*/ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/drivers/src/altera_avalon_jtag_uart_fd.c b/MCandWifiTestDE0/Software/MCTest_bsp/drivers/src/altera_avalon_jtag_uart_fd.c new file mode 100644 index 00000000..53dfc3b9 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/drivers/src/altera_avalon_jtag_uart_fd.c @@ -0,0 +1,86 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2007 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include "alt_types.h" +#include "sys/alt_dev.h" +#include "altera_avalon_jtag_uart.h" + +extern int altera_avalon_jtag_uart_read(altera_avalon_jtag_uart_state* sp, + char* buffer, int space, int flags); +extern int altera_avalon_jtag_uart_write(altera_avalon_jtag_uart_state* sp, + const char* ptr, int count, int flags); +extern int altera_avalon_jtag_uart_ioctl(altera_avalon_jtag_uart_state* sp, + int req, void* arg); +extern int altera_avalon_jtag_uart_close(altera_avalon_jtag_uart_state* sp, + int flags); + +/* ----------------------------------------------------------------------- */ +/* --------------------- WRAPPERS FOR ALT FD SUPPORT --------------------- */ +/* + * + */ + +int +altera_avalon_jtag_uart_read_fd(alt_fd* fd, char* buffer, int space) +{ + altera_avalon_jtag_uart_dev* dev = (altera_avalon_jtag_uart_dev*) fd->dev; + + return altera_avalon_jtag_uart_read(&dev->state, buffer, space, + fd->fd_flags); +} + +int +altera_avalon_jtag_uart_write_fd(alt_fd* fd, const char* buffer, int space) +{ + altera_avalon_jtag_uart_dev* dev = (altera_avalon_jtag_uart_dev*) fd->dev; + + return altera_avalon_jtag_uart_write(&dev->state, buffer, space, + fd->fd_flags); +} + +#ifndef ALTERA_AVALON_JTAG_UART_SMALL + +int +altera_avalon_jtag_uart_close_fd(alt_fd* fd) +{ + altera_avalon_jtag_uart_dev* dev = (altera_avalon_jtag_uart_dev*) fd->dev; + + return altera_avalon_jtag_uart_close(&dev->state, fd->fd_flags); +} + +int +altera_avalon_jtag_uart_ioctl_fd(alt_fd* fd, int req, void* arg) +{ + altera_avalon_jtag_uart_dev* dev = (altera_avalon_jtag_uart_dev*) fd->dev; + + return altera_avalon_jtag_uart_ioctl(&dev->state, req, arg); +} + +#endif /* ALTERA_AVALON_JTAG_UART_SMALL */ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/drivers/src/altera_avalon_jtag_uart_init.c b/MCandWifiTestDE0/Software/MCTest_bsp/drivers/src/altera_avalon_jtag_uart_init.c new file mode 100644 index 00000000..7317becb --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/drivers/src/altera_avalon_jtag_uart_init.c @@ -0,0 +1,256 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2007 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include +#include +#include +#include + +#include + +#include "sys/alt_irq.h" +#include "sys/alt_alarm.h" +#include "sys/ioctl.h" +#include "alt_types.h" + +#include "altera_avalon_jtag_uart_regs.h" +#include "altera_avalon_jtag_uart.h" + +#include "sys/alt_log_printf.h" + +#ifndef ALTERA_AVALON_JTAG_UART_SMALL + +/* ----------------------------------------------------------- */ +/* ------------------------- FAST DRIVER --------------------- */ +/* ----------------------------------------------------------- */ +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT +static void altera_avalon_jtag_uart_irq(void* context); +#else +static void altera_avalon_jtag_uart_irq(void* context, alt_u32 id); +#endif +static alt_u32 altera_avalon_jtag_uart_timeout(void* context); + +/* + * Driver initialization code. Register interrupts and start a timer + * which we can use to check whether the host is there. + * Return 1 on sucessful IRQ register and 0 on failure. + */ + +void altera_avalon_jtag_uart_init(altera_avalon_jtag_uart_state* sp, + int irq_controller_id, int irq) +{ + ALT_FLAG_CREATE(&sp->events, 0); + ALT_SEM_CREATE(&sp->read_lock, 1); + ALT_SEM_CREATE(&sp->write_lock, 1); + + /* enable read interrupts at the device */ + sp->irq_enable = ALTERA_AVALON_JTAG_UART_CONTROL_RE_MSK; + + IOWR_ALTERA_AVALON_JTAG_UART_CONTROL(sp->base, sp->irq_enable); + + /* register the interrupt handler */ +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT + alt_ic_isr_register(irq_controller_id, irq, altera_avalon_jtag_uart_irq, + sp, NULL); +#else + alt_irq_register(irq, sp, altera_avalon_jtag_uart_irq); +#endif + + /* Register an alarm to go off every second to check for presence of host */ + sp->host_inactive = 0; + + if (alt_alarm_start(&sp->alarm, alt_ticks_per_second(), + &altera_avalon_jtag_uart_timeout, sp) < 0) + { + /* If we can't set the alarm then record "don't know if host present" + * and behave as though the host is present. + */ + sp->timeout = INT_MAX; + } + + /* ALT_LOG - see altera_hal/HAL/inc/sys/alt_log_printf.h */ + ALT_LOG_JTAG_UART_ALARM_REGISTER(sp, sp->base); +} + +/* + * Interrupt routine + */ +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT +static void altera_avalon_jtag_uart_irq(void* context) +#else +static void altera_avalon_jtag_uart_irq(void* context, alt_u32 id) +#endif +{ + altera_avalon_jtag_uart_state* sp = (altera_avalon_jtag_uart_state*) context; + unsigned int base = sp->base; + + /* ALT_LOG - see altera_hal/HAL/inc/sys/alt_log_printf.h */ + ALT_LOG_JTAG_UART_ISR_FUNCTION(base, sp); + + for ( ; ; ) + { + unsigned int control = IORD_ALTERA_AVALON_JTAG_UART_CONTROL(base); + + /* Return once nothing more to do */ + if ((control & (ALTERA_AVALON_JTAG_UART_CONTROL_RI_MSK | ALTERA_AVALON_JTAG_UART_CONTROL_WI_MSK)) == 0) + break; + + if (control & ALTERA_AVALON_JTAG_UART_CONTROL_RI_MSK) + { + /* process a read irq. Start by assuming that there is data in the + * receive FIFO (otherwise why would we have been interrupted?) + */ + unsigned int data = 1 << ALTERA_AVALON_JTAG_UART_DATA_RAVAIL_OFST; + + for ( ; ; ) + { + /* Check whether there is space in the buffer. If not then we must not + * read any characters from the buffer as they will be lost. + */ + unsigned int next = (sp->rx_in + 1) % ALTERA_AVALON_JTAG_UART_BUF_LEN; + if (next == sp->rx_out) + break; + + /* Try to remove a character from the FIFO and find out whether there + * are any more characters remaining. + */ + data = IORD_ALTERA_AVALON_JTAG_UART_DATA(base); + + if ((data & ALTERA_AVALON_JTAG_UART_DATA_RVALID_MSK) == 0) + break; + + sp->rx_buf[sp->rx_in] = (data & ALTERA_AVALON_JTAG_UART_DATA_DATA_MSK) >> ALTERA_AVALON_JTAG_UART_DATA_DATA_OFST; + sp->rx_in = (sp->rx_in + 1) % ALTERA_AVALON_JTAG_UART_BUF_LEN; + + /* Post an event to notify jtag_uart_read that a character has been read */ + ALT_FLAG_POST (sp->events, ALT_JTAG_UART_READ_RDY, OS_FLAG_SET); + } + + if (data & ALTERA_AVALON_JTAG_UART_DATA_RAVAIL_MSK) + { + /* If there is still data available here then the buffer is full + * so turn off receive interrupts until some space becomes available. + */ + sp->irq_enable &= ~ALTERA_AVALON_JTAG_UART_CONTROL_RE_MSK; + IOWR_ALTERA_AVALON_JTAG_UART_CONTROL(base, sp->irq_enable); + + /* Dummy read to ensure IRQ is cleared prior to ISR completion */ + IORD_ALTERA_AVALON_JTAG_UART_CONTROL(base); + } + } + + if (control & ALTERA_AVALON_JTAG_UART_CONTROL_WI_MSK) + { + /* process a write irq */ + unsigned int space = (control & ALTERA_AVALON_JTAG_UART_CONTROL_WSPACE_MSK) >> ALTERA_AVALON_JTAG_UART_CONTROL_WSPACE_OFST; + + while (space > 0 && sp->tx_out != sp->tx_in) + { + IOWR_ALTERA_AVALON_JTAG_UART_DATA(base, sp->tx_buf[sp->tx_out]); + + sp->tx_out = (sp->tx_out + 1) % ALTERA_AVALON_JTAG_UART_BUF_LEN; + + /* Post an event to notify jtag_uart_write that a character has been written */ + ALT_FLAG_POST (sp->events, ALT_JTAG_UART_WRITE_RDY, OS_FLAG_SET); + + space--; + } + + if (space > 0) + { + /* If we don't have any more data available then turn off the TX interrupt */ + sp->irq_enable &= ~ALTERA_AVALON_JTAG_UART_CONTROL_WE_MSK; + IOWR_ALTERA_AVALON_JTAG_UART_CONTROL(sp->base, sp->irq_enable); + + /* Dummy read to ensure IRQ is cleared prior to ISR completion */ + IORD_ALTERA_AVALON_JTAG_UART_CONTROL(base); + } + } + } +} + +/* + * Timeout routine is called every second + */ + +static alt_u32 +altera_avalon_jtag_uart_timeout(void* context) +{ + altera_avalon_jtag_uart_state* sp = (altera_avalon_jtag_uart_state *) context; + + unsigned int control = IORD_ALTERA_AVALON_JTAG_UART_CONTROL(sp->base); + + if (control & ALTERA_AVALON_JTAG_UART_CONTROL_AC_MSK) + { + IOWR_ALTERA_AVALON_JTAG_UART_CONTROL(sp->base, sp->irq_enable | ALTERA_AVALON_JTAG_UART_CONTROL_AC_MSK); + sp->host_inactive = 0; + } + else if (sp->host_inactive < INT_MAX - 2) { + sp->host_inactive++; + + if (sp->host_inactive >= sp->timeout) { + /* Post an event to indicate host is inactive (for jtag_uart_read */ + ALT_FLAG_POST (sp->events, ALT_JTAG_UART_TIMEOUT, OS_FLAG_SET); + } + } + + return alt_ticks_per_second(); +} + +/* + * The close() routine is implemented to drain the JTAG UART transmit buffer + * when not in "small" mode. This routine will wait for transimt data to be + * emptied unless a timeout from host-activity occurs. If the driver flags + * have been set to non-blocking mode, this routine will exit immediately if + * any data remains. This routine should be called indirectly (i.e. though + * the C library close() routine) so that the file descriptor associated + * with the relevant stream (i.e. stdout) can be closed as well. This routine + * does not manage file descriptors. + * + * The close routine is not implemented for the small driver; instead it will + * map to null. This is because the small driver simply waits while characters + * are transmitted; there is no interrupt-serviced buffer to empty + */ +int altera_avalon_jtag_uart_close(altera_avalon_jtag_uart_state* sp, int flags) +{ + /* + * Wait for all transmit data to be emptied by the JTAG UART ISR, or + * for a host-inactivity timeout, in which case transmit data will be lost + */ + while ( (sp->tx_out != sp->tx_in) && (sp->host_inactive < sp->timeout) ) { + if (flags & O_NONBLOCK) { + return -EWOULDBLOCK; + } + } + + return 0; +} + +#endif /* !ALTERA_AVALON_JTAG_UART_SMALL */ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/drivers/src/altera_avalon_jtag_uart_ioctl.c b/MCandWifiTestDE0/Software/MCTest_bsp/drivers/src/altera_avalon_jtag_uart_ioctl.c new file mode 100644 index 00000000..cf71e6f6 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/drivers/src/altera_avalon_jtag_uart_ioctl.c @@ -0,0 +1,86 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include +#include +#include +#include + +#include + +#include "sys/ioctl.h" +#include "alt_types.h" + +#include "altera_avalon_jtag_uart_regs.h" +#include "altera_avalon_jtag_uart.h" + +#include "sys/alt_log_printf.h" + +#ifndef ALTERA_AVALON_JTAG_UART_SMALL + +/* ----------------------------------------------------------- */ +/* ------------------------- FAST DRIVER --------------------- */ +/* ----------------------------------------------------------- */ + +int +altera_avalon_jtag_uart_ioctl(altera_avalon_jtag_uart_state* sp, int req, + void* arg) +{ + int rc = -ENOTTY; + + switch (req) + { + case TIOCSTIMEOUT: + /* Set the time to wait until assuming host is not connected */ + if (sp->timeout != INT_MAX) + { + int timeout = *((int *)arg); + sp->timeout = (timeout >= 2 && timeout < INT_MAX) ? timeout : INT_MAX - 1; + rc = 0; + } + break; + + case TIOCGCONNECTED: + /* Find out whether host is connected */ + if (sp->timeout != INT_MAX) + { + *((int *)arg) = (sp->host_inactive < sp->timeout) ? 1 : 0; + rc = 0; + } + break; + + default: + break; + } + + return rc; +} + +#endif /* !ALTERA_AVALON_JTAG_UART_SMALL */ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/drivers/src/altera_avalon_jtag_uart_read.c b/MCandWifiTestDE0/Software/MCTest_bsp/drivers/src/altera_avalon_jtag_uart_read.c new file mode 100644 index 00000000..5657adba --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/drivers/src/altera_avalon_jtag_uart_read.c @@ -0,0 +1,205 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include +#include +#include +#include + +#include + +#include "sys/alt_irq.h" +#include "sys/alt_alarm.h" +#include "sys/ioctl.h" +#include "alt_types.h" + +#include "altera_avalon_jtag_uart_regs.h" +#include "altera_avalon_jtag_uart.h" + +#include "sys/alt_log_printf.h" + +#ifdef __ucosii__ +#include "includes.h" +#endif /* __ucosii__ */ + +#ifdef ALTERA_AVALON_JTAG_UART_SMALL + +/* ----------------------------------------------------------- */ +/* ----------------------- SMALL DRIVER ---------------------- */ +/* ----------------------------------------------------------- */ + +/* Read routine. The small version blocks until it has at least one byte + * available, it then returns as much as is immediately available without + * waiting any more. It's performance will be very poor without + * interrupts. + */ + +int +altera_avalon_jtag_uart_read(altera_avalon_jtag_uart_state* sp, + char* buffer, int space, int flags) +{ + unsigned int base = sp->base; + + char * ptr = buffer; + char * end = buffer + space; + + while (ptr < end) + { + unsigned int data = IORD_ALTERA_AVALON_JTAG_UART_DATA(base); + + if (data & ALTERA_AVALON_JTAG_UART_DATA_RVALID_MSK) + *ptr++ = (data & ALTERA_AVALON_JTAG_UART_DATA_DATA_MSK) >> ALTERA_AVALON_JTAG_UART_DATA_DATA_OFST; + else if (ptr != buffer) + break; + else if(flags & O_NONBLOCK) + break; + + } + + if (ptr != buffer) + return ptr - buffer; + else if (flags & O_NONBLOCK) + return -EWOULDBLOCK; + else + return -EIO; +} + +#else /* !ALTERA_AVALON_JTAG_UART_SMALL */ + +/* ----------------------------------------------------------- */ +/* ----------------------- FAST DRIVER ----------------------- */ +/* ----------------------------------------------------------- */ + +int +altera_avalon_jtag_uart_read(altera_avalon_jtag_uart_state* sp, + char * buffer, int space, int flags) +{ + char * ptr = buffer; + + alt_irq_context context; + unsigned int n; + + /* + * When running in a multi threaded environment, obtain the "read_lock" + * semaphore. This ensures that reading from the device is thread-safe. + */ + ALT_SEM_PEND (sp->read_lock, 0); + + while (space > 0) + { + unsigned int in, out; + + /* Read as much data as possible */ + do + { + in = sp->rx_in; + out = sp->rx_out; + + if (in >= out) + n = in - out; + else + n = ALTERA_AVALON_JTAG_UART_BUF_LEN - out; + + if (n == 0) + break; /* No more data available */ + + if (n > space) + n = space; + + memcpy(ptr, sp->rx_buf + out, n); + ptr += n; + space -= n; + + sp->rx_out = (out + n) % ALTERA_AVALON_JTAG_UART_BUF_LEN; + } + while (space > 0); + + /* If we read any data then return it */ + if (ptr != buffer) + break; + + /* If in non-blocking mode then return error */ + if (flags & O_NONBLOCK) + break; + +#ifdef __ucosii__ + /* OS Present: Pend on a flag if the OS is running, otherwise spin */ + if(OSRunning == OS_TRUE) { + /* + * When running in a multi-threaded mode, we pend on the read event + * flag set and timeout event flag set in the isr. This avoids wasting CPU + * cycles waiting in this thread, when we could be doing something more + * profitable elsewhere. + */ + ALT_FLAG_PEND (sp->events, + ALT_JTAG_UART_READ_RDY | ALT_JTAG_UART_TIMEOUT, + OS_FLAG_WAIT_SET_ANY + OS_FLAG_CONSUME, + 0); + } + else { + /* Spin until more data arrives or until host disconnects */ + while (in == sp->rx_in && sp->host_inactive < sp->timeout) + ; + } +#else + /* No OS: Always spin */ + while (in == sp->rx_in && sp->host_inactive < sp->timeout) + ; +#endif /* __ucosii__ */ + + if (in == sp->rx_in) + break; + } + + /* + * Now that access to the circular buffer is complete, release the read + * semaphore so that other threads can access the buffer. + */ + + ALT_SEM_POST (sp->read_lock); + + if (ptr != buffer) + { + /* If we read any data then there is space in the buffer so enable interrupts */ + context = alt_irq_disable_all(); + sp->irq_enable |= ALTERA_AVALON_JTAG_UART_CONTROL_RE_MSK; + IOWR_ALTERA_AVALON_JTAG_UART_CONTROL(sp->base, sp->irq_enable); + alt_irq_enable_all(context); + } + + if (ptr != buffer) + return ptr - buffer; + else if (flags & O_NONBLOCK) + return -EWOULDBLOCK; + else + return -EIO; +} + +#endif /* ALTERA_AVALON_JTAG_UART_SMALL */ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/drivers/src/altera_avalon_jtag_uart_write.c b/MCandWifiTestDE0/Software/MCTest_bsp/drivers/src/altera_avalon_jtag_uart_write.c new file mode 100644 index 00000000..1e7ac919 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/drivers/src/altera_avalon_jtag_uart_write.c @@ -0,0 +1,204 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include +#include +#include +#include + +#include + +#include "sys/alt_irq.h" +#include "sys/alt_alarm.h" +#include "sys/ioctl.h" +#include "alt_types.h" + +#include "altera_avalon_jtag_uart_regs.h" +#include "altera_avalon_jtag_uart.h" + +#include "sys/alt_log_printf.h" + +#ifdef __ucosii__ +#include "includes.h" +#endif /* __ucosii__ */ + +#ifdef ALTERA_AVALON_JTAG_UART_SMALL + +/* ----------------------------------------------------------- */ +/* ------------------------ SMALL DRIVER --------------------- */ +/* ----------------------------------------------------------- */ + +/* Write routine. The small version blocks when there is no space to write + * into, so it's performance will be very bad if you are writing more than + * one FIFOs worth of data. But you said you didn't want to use interrupts :-) + */ + +int altera_avalon_jtag_uart_write(altera_avalon_jtag_uart_state* sp, + const char * ptr, int count, int flags) +{ + unsigned int base = sp->base; + + const char * end = ptr + count; + + while (ptr < end) + if ((IORD_ALTERA_AVALON_JTAG_UART_CONTROL(base) & ALTERA_AVALON_JTAG_UART_CONTROL_WSPACE_MSK) != 0) + IOWR_ALTERA_AVALON_JTAG_UART_DATA(base, *ptr++); + + return count; +} + +#else /* !ALTERA_AVALON_JTAG_UART_SMALL */ + +/* ----------------------------------------------------------- */ +/* ------------------------- FAST DRIVER --------------------- */ +/* ----------------------------------------------------------- */ + +int +altera_avalon_jtag_uart_write(altera_avalon_jtag_uart_state* sp, + const char * ptr, int count, int flags) +{ + /* Remove warning at optimisation level 03 by seting out to 0 */ + unsigned int in, out=0; + unsigned int n; + alt_irq_context context; + + const char * start = ptr; + + /* + * When running in a multi threaded environment, obtain the "write_lock" + * semaphore. This ensures that writing to the device is thread-safe. + */ + ALT_SEM_PEND (sp->write_lock, 0); + + do + { + /* Copy as much as we can into the transmit buffer */ + while (count > 0) + { + /* We need a stable value of the out pointer to calculate the space available */ + in = sp->tx_in; + out = sp->tx_out; + + if (in < out) + n = out - 1 - in; + else if (out > 0) + n = ALTERA_AVALON_JTAG_UART_BUF_LEN - in; + else + n = ALTERA_AVALON_JTAG_UART_BUF_LEN - 1 - in; + + if (n == 0) + break; + + if (n > count) + n = count; + + memcpy(sp->tx_buf + in, ptr, n); + ptr += n; + count -= n; + + sp->tx_in = (in + n) % ALTERA_AVALON_JTAG_UART_BUF_LEN; + } + + /* + * If interrupts are disabled then we could transmit here, we only need + * to enable interrupts if there is no space left in the FIFO + * + * For now kick the interrupt routine every time to make it transmit + * the data + */ + context = alt_irq_disable_all(); + sp->irq_enable |= ALTERA_AVALON_JTAG_UART_CONTROL_WE_MSK; + IOWR_ALTERA_AVALON_JTAG_UART_CONTROL(sp->base, sp->irq_enable); + alt_irq_enable_all(context); + + /* + * If there is any data left then either return now or block until + * some has been sent + */ + /* consider: test whether there is anything there while doing this and delay for at most 2s. */ + if (count > 0) + { + if (flags & O_NONBLOCK) + break; + +#ifdef __ucosii__ + /* OS Present: Pend on a flag if the OS is running, otherwise spin */ + if(OSRunning == OS_TRUE) { + /* + * When running in a multi-threaded mode, we pend on the write event + * flag set or the timeout flag in the isr. This avoids wasting CPU + * cycles waiting in this thread, when we could be doing something + * more profitable elsewhere. + */ + ALT_FLAG_PEND (sp->events, + ALT_JTAG_UART_WRITE_RDY | ALT_JTAG_UART_TIMEOUT, + OS_FLAG_WAIT_SET_ANY + OS_FLAG_CONSUME, + 0); + } + else { + /* + * OS not running: Wait for data to be removed from buffer. + * Once the interrupt routine has removed some data then we + * will be able to insert some more. + */ + while (out == sp->tx_out && sp->host_inactive < sp->timeout) + ; + } +#else + /* + * No OS present: Always wait for data to be removed from buffer. Once + * the interrupt routine has removed some data then we will be able to + * insert some more. + */ + while (out == sp->tx_out && sp->host_inactive < sp->timeout) + ; +#endif /* __ucosii__ */ + + if (out == sp->tx_out) + break; + } + } + while (count > 0); + + /* + * Now that access to the circular buffer is complete, release the write + * semaphore so that other threads can access the buffer. + */ + ALT_SEM_POST (sp->write_lock); + + if (ptr != start) + return ptr - start; + else if (flags & O_NONBLOCK) + return -EWOULDBLOCK; + else + return -EIO; /* Host not connected */ +} + +#endif /* ALTERA_AVALON_JTAG_UART_SMALL */ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/drivers/src/altera_avalon_sysid_qsys.c b/MCandWifiTestDE0/Software/MCTest_bsp/drivers/src/altera_avalon_sysid_qsys.c new file mode 100644 index 00000000..323adf9d --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/drivers/src/altera_avalon_sysid_qsys.c @@ -0,0 +1,82 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include "altera_avalon_sysid_qsys.h" +#include "altera_avalon_sysid_qsys_regs.h" +#include "alt_types.h" +#include + +/* +* This component is special: there's only one of it. +* Therefore we can dispense with a bunch of complexity +* normally associated with components, such as specialized +* structs containing parameter info, and instead use that +* info by name directly out of system.h. A downside of this +* approach is that each time the system is regenerated, and +* system.h changes, this file must be recompiled. Fortunately +* this file is, and is likely to remain, quite small. +*/ +#include "system.h" + +#ifdef SYSID_BASE +/* +* return values: +* 0 if the hardware and software appear to be in sync +* 1 if software appears to be older than hardware +* -1 if hardware appears to be older than software +*/ + +alt_32 alt_avalon_sysid_qsys_test(void) +{ + /* Read the hardware-tag, aka value0, from the hardware. */ + alt_u32 hardware_id = IORD_ALTERA_AVALON_SYSID_QSYS_ID(SYSID_BASE); + + /* Read the time-of-generation, aka value1, from the hardware register. */ + alt_u32 hardware_timestamp = IORD_ALTERA_AVALON_SYSID_QSYS_TIMESTAMP(SYSID_BASE); + + /* Return 0 if the hardware and software appear to be in sync. */ + if ((SYSID_TIMESTAMP == hardware_timestamp) && (SYSID_ID == hardware_id)) + { + return 0; + } + + /* + * Return 1 if software appears to be older than hardware (that is, + * the value returned by the hardware is larger than that recorded by + * the generator function). + * If the hardware time happens to match the generator program's value + * (but the hardware tag, value0, doesn't match or 0 would have been + * returned above), return an arbitrary value, let's say -1. + */ + return ((alt_32)(hardware_timestamp - SYSID_TIMESTAMP)) > 0 ? 1 : -1; +} +#endif diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/drivers/src/altera_avalon_timer_sc.c b/MCandWifiTestDE0/Software/MCTest_bsp/drivers/src/altera_avalon_timer_sc.c new file mode 100644 index 00000000..d9a7b850 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/drivers/src/altera_avalon_timer_sc.c @@ -0,0 +1,110 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include + +#include "sys/alt_alarm.h" +#include "sys/alt_irq.h" + +#include "altera_avalon_timer.h" +#include "altera_avalon_timer_regs.h" + +#include "alt_types.h" +#include "sys/alt_log_printf.h" + +/* + * alt_avalon_timer_sc_irq() is the interrupt handler used for the system + * clock. This is called periodically when a timer interrupt occurs. The + * function first clears the interrupt condition, and then calls the + * alt_tick() function to notify the system that a timer tick has occurred. + * + * alt_tick() increments the system tick count, and updates any registered + * alarms, see alt_tick.c for further details. + */ +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT +static void alt_avalon_timer_sc_irq (void* base) +#else +static void alt_avalon_timer_sc_irq (void* base, alt_u32 id) +#endif +{ + alt_irq_context cpu_sr; + + /* clear the interrupt */ + IOWR_ALTERA_AVALON_TIMER_STATUS (base, 0); + + /* + * Dummy read to ensure IRQ is negated before the ISR returns. + * The control register is read because reading the status + * register has side-effects per the register map documentation. + */ + IORD_ALTERA_AVALON_TIMER_CONTROL (base); + + /* ALT_LOG - see altera_hal/HAL/inc/sys/alt_log_printf.h */ + ALT_LOG_SYS_CLK_HEARTBEAT(); + + /* + * Notify the system of a clock tick. disable interrupts + * during this time to safely support ISR preemption + */ + cpu_sr = alt_irq_disable_all(); + alt_tick (); + alt_irq_enable_all(cpu_sr); +} + +/* + * alt_avalon_timer_sc_init() is called to initialise the timer that will be + * used to provide the periodic system clock. This is called from the + * auto-generated alt_sys_init() function. + */ + +void alt_avalon_timer_sc_init (void* base, alt_u32 irq_controller_id, + alt_u32 irq, alt_u32 freq) +{ + /* set the system clock frequency */ + + alt_sysclk_init (freq); + + /* set to free running mode */ + + IOWR_ALTERA_AVALON_TIMER_CONTROL (base, + ALTERA_AVALON_TIMER_CONTROL_ITO_MSK | + ALTERA_AVALON_TIMER_CONTROL_CONT_MSK | + ALTERA_AVALON_TIMER_CONTROL_START_MSK); + + /* register the interrupt handler, and enable the interrupt */ +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT + alt_ic_isr_register(irq_controller_id, irq, alt_avalon_timer_sc_irq, + base, NULL); +#else + alt_irq_register (irq, base, alt_avalon_timer_sc_irq); +#endif +} diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/drivers/src/altera_avalon_timer_ts.c b/MCandWifiTestDE0/Software/MCTest_bsp/drivers/src/altera_avalon_timer_ts.c new file mode 100644 index 00000000..6514f338 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/drivers/src/altera_avalon_timer_ts.c @@ -0,0 +1,143 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include + +#include "system.h" +#include "sys/alt_timestamp.h" + +#include "altera_avalon_timer.h" +#include "altera_avalon_timer_regs.h" + +#include "alt_types.h" + +/* + * These functions are only available if a timestamp device has been selected + * for this system. + */ + +#if (ALT_TIMESTAMP_CLK_BASE != none_BASE) + +/* + * The function alt_timestamp_start() can be called at application level to + * initialise the timestamp facility. In this case the period register is + * set to full scale, i.e. 0xffffffff, and then started running. Note that + * the period register may not be writable, depending on the hardware + * configuration, in which case this function does not reset the period. + * + * The timer is not run in continuous mode, so that the user can detect timer + * roll-over, i.e. alt_timestamp() returns 0. + * + * The return value of this function is 0 upon sucess and -1 if in timestamp + * device has not been registered. + */ + +int alt_timestamp_start(void) +{ + void* base = altera_avalon_timer_ts_base; + + if (!altera_avalon_timer_ts_freq) + { + return -1; + } + else + { + if(ALT_TIMESTAMP_COUNTER_SIZE == 64) { + IOWR_ALTERA_AVALON_TIMER_CONTROL (base,ALTERA_AVALON_TIMER_CONTROL_STOP_MSK); + IOWR_ALTERA_AVALON_TIMER_PERIOD_0 (base, 0xFFFF); + IOWR_ALTERA_AVALON_TIMER_PERIOD_1 (base, 0xFFFF);; + IOWR_ALTERA_AVALON_TIMER_PERIOD_2 (base, 0xFFFF); + IOWR_ALTERA_AVALON_TIMER_PERIOD_3 (base, 0xFFFF); + IOWR_ALTERA_AVALON_TIMER_CONTROL (base, ALTERA_AVALON_TIMER_CONTROL_START_MSK); + } else { + IOWR_ALTERA_AVALON_TIMER_CONTROL (base,ALTERA_AVALON_TIMER_CONTROL_STOP_MSK); + IOWR_ALTERA_AVALON_TIMER_PERIODL (base, 0xFFFF); + IOWR_ALTERA_AVALON_TIMER_PERIODH (base, 0xFFFF); + IOWR_ALTERA_AVALON_TIMER_CONTROL (base, ALTERA_AVALON_TIMER_CONTROL_START_MSK); + } + } + return 0; +} + +/* + * alt_timestamp() returns the current timestamp count. In the event that + * the timer has run full period, or there is no timestamp available, this + * function return -1. + * + * The returned timestamp counts up from the last time the period register + * was reset. + */ + +alt_timestamp_type alt_timestamp(void) +{ + + void* base = altera_avalon_timer_ts_base; + + if (!altera_avalon_timer_ts_freq) + { + if(ALT_TIMESTAMP_COUNTER_SIZE == 64) { + return 0xFFFFFFFFFFFFFFFFULL; + } else { + return 0xFFFFFFFF; + } + } + else + { + if(ALT_TIMESTAMP_COUNTER_SIZE == 64) { + IOWR_ALTERA_AVALON_TIMER_SNAP_0 (base, 0); + alt_timestamp_type snap_0 = IORD_ALTERA_AVALON_TIMER_SNAP_0(base) & ALTERA_AVALON_TIMER_SNAP_0_MSK; + alt_timestamp_type snap_1 = IORD_ALTERA_AVALON_TIMER_SNAP_1(base) & ALTERA_AVALON_TIMER_SNAP_1_MSK; + alt_timestamp_type snap_2 = IORD_ALTERA_AVALON_TIMER_SNAP_2(base) & ALTERA_AVALON_TIMER_SNAP_2_MSK; + alt_timestamp_type snap_3 = IORD_ALTERA_AVALON_TIMER_SNAP_3(base) & ALTERA_AVALON_TIMER_SNAP_3_MSK; + + return (0xFFFFFFFFFFFFFFFFULL - ( (snap_3 << 48) | (snap_2 << 32) | (snap_1 << 16) | (snap_0) )); + } else { + IOWR_ALTERA_AVALON_TIMER_SNAPL (base, 0); + alt_timestamp_type lower = IORD_ALTERA_AVALON_TIMER_SNAPL(base) & ALTERA_AVALON_TIMER_SNAPL_MSK; + alt_timestamp_type upper = IORD_ALTERA_AVALON_TIMER_SNAPH(base) & ALTERA_AVALON_TIMER_SNAPH_MSK; + + return (0xFFFFFFFF - ((upper << 16) | lower)); + } + } +} + +/* + * Return the number of timestamp ticks per second. This will be 0 if no + * timestamp device has been registered. + */ + +alt_u32 alt_timestamp_freq(void) +{ + return altera_avalon_timer_ts_freq; +} + +#endif /* timestamp available */ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/drivers/src/altera_avalon_timer_vars.c b/MCandWifiTestDE0/Software/MCTest_bsp/drivers/src/altera_avalon_timer_vars.c new file mode 100644 index 00000000..cb8b1972 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/drivers/src/altera_avalon_timer_vars.c @@ -0,0 +1,45 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +#include + +#include "altera_avalon_timer.h" +#include "alt_types.h" + +/* + * Variables used to store the timestamp parameters. These are initialised + * from alt_sys_init() using the ALTERA_AVALON_TIMER_INIT macro + * defined in altera_avalon_timer.h. + */ + +void* altera_avalon_timer_ts_base = (void*) 0; +alt_u32 altera_avalon_timer_ts_freq = 0; diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/drivers/src/altera_avalon_uart_fd.c b/MCandWifiTestDE0/Software/MCTest_bsp/drivers/src/altera_avalon_uart_fd.c new file mode 100644 index 00000000..69a391b7 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/drivers/src/altera_avalon_uart_fd.c @@ -0,0 +1,100 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2007 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include "alt_types.h" +#include "sys/alt_dev.h" +#include "altera_avalon_uart.h" + +extern int altera_avalon_uart_read(altera_avalon_uart_state* sp, + char* buffer, int space, int flags); +extern int altera_avalon_uart_write(altera_avalon_uart_state* sp, + const char* ptr, int count, int flags); +extern int altera_avalon_uart_ioctl(altera_avalon_uart_state* sp, + int req, void* arg); +extern int altera_avalon_uart_close(altera_avalon_uart_state* sp, int flags); + +/* ----------------------------------------------------------------------- */ +/* --------------------- WRAPPERS FOR ALT FD SUPPORT --------------------- */ +/* + * + */ + +int +altera_avalon_uart_read_fd(alt_fd* fd, char* buffer, int space) +{ + altera_avalon_uart_dev* dev = (altera_avalon_uart_dev*) fd->dev; + + return altera_avalon_uart_read(&dev->state, buffer, space, + fd->fd_flags); +} + +int +altera_avalon_uart_write_fd(alt_fd* fd, const char* buffer, int space) +{ + altera_avalon_uart_dev* dev = (altera_avalon_uart_dev*) fd->dev; + + return altera_avalon_uart_write(&dev->state, buffer, space, + fd->fd_flags); +} + +#if !defined(ALT_USE_SMALL_DRIVERS) && !defined(ALTERA_AVALON_UART_SMALL) + +/* + * Fast driver + */ + +/* + * To reduce the code footprint of this driver, the ioctl() function is not + * included by default. If you wish to use the ioctl features provided + * below, you can do so by adding the option : -DALTERA_AVALON_UART_USE_IOCTL + * to CPPFLAGS in the Makefile (or through the Eclipse IDE). + */ + +#ifdef ALTERA_AVALON_UART_USE_IOCTL + +int +altera_avalon_uart_ioctl_fd(alt_fd* fd, int req, void* arg) +{ + altera_avalon_uart_dev* dev = (altera_avalon_uart_dev*) fd->dev; + + return altera_avalon_uart_ioctl(&dev->state, req, arg); +} + +#endif /* ALTERA_AVALON_UART_USE_IOCTL */ + +int +altera_avalon_uart_close_fd(alt_fd* fd) +{ + altera_avalon_uart_dev* dev = (altera_avalon_uart_dev*) fd->dev; + + return altera_avalon_uart_close(&dev->state, fd->fd_flags); +} + +#endif /* fast driver */ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/drivers/src/altera_avalon_uart_init.c b/MCandWifiTestDE0/Software/MCTest_bsp/drivers/src/altera_avalon_uart_init.c new file mode 100644 index 00000000..cec4e032 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/drivers/src/altera_avalon_uart_init.c @@ -0,0 +1,312 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2009 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include + +#include "sys/alt_dev.h" +#include "sys/alt_irq.h" +#include "sys/ioctl.h" +#include "sys/alt_errno.h" + +#include "altera_avalon_uart.h" +#include "altera_avalon_uart_regs.h" + +#if !defined(ALT_USE_SMALL_DRIVERS) && !defined(ALTERA_AVALON_UART_SMALL) + +/* ----------------------------------------------------------- */ +/* ------------------------- FAST DRIVER --------------------- */ +/* ----------------------------------------------------------- */ + +/* + * altera_avalon_uart_init() is called by the auto-generated function + * alt_sys_init() in order to initialize a particular instance of this device. + * It is responsible for configuring the device and associated software + * constructs. + */ + +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT +static void altera_avalon_uart_irq(void* context); +#else +static void altera_avalon_uart_irq(void* context, alt_u32 id); +#endif + +static void altera_avalon_uart_rxirq(altera_avalon_uart_state* sp, + alt_u32 status); +static void altera_avalon_uart_txirq(altera_avalon_uart_state* sp, + alt_u32 status); + +void +altera_avalon_uart_init(altera_avalon_uart_state* sp, + alt_u32 irq_controller_id, alt_u32 irq) +{ + void* base = sp->base; + int error; + + /* + * Initialise the read and write flags and the semaphores used to + * protect access to the circular buffers when running in a multi-threaded + * environment. + */ + error = ALT_FLAG_CREATE (&sp->events, 0) || + ALT_SEM_CREATE (&sp->read_lock, 1) || + ALT_SEM_CREATE (&sp->write_lock, 1); + + if (!error) + { + /* enable interrupts at the device */ + sp->ctrl = ALTERA_AVALON_UART_CONTROL_RTS_MSK | + ALTERA_AVALON_UART_CONTROL_RRDY_MSK | + ALTERA_AVALON_UART_CONTROL_DCTS_MSK; + + IOWR_ALTERA_AVALON_UART_CONTROL(base, sp->ctrl); + + /* register the interrupt handler */ +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT + alt_ic_isr_register(irq_controller_id, irq, altera_avalon_uart_irq, sp, + 0x0); +#else + alt_irq_register (irq, sp, altera_avalon_uart_irq); +#endif + } +} + +/* + * altera_avalon_uart_irq() is the interrupt handler registered at + * configuration time for processing UART interrupts. It vectors + * interrupt requests to either altera_avalon_uart_rxirq() (for incoming + * data), or altera_avalon_uart_txirq() (for outgoing data). + */ +#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT +static void altera_avalon_uart_irq(void* context) +#else +static void altera_avalon_uart_irq(void* context, alt_u32 id) +#endif +{ + alt_u32 status; + + altera_avalon_uart_state* sp = (altera_avalon_uart_state*) context; + void* base = sp->base; + + /* + * Read the status register in order to determine the cause of the + * interrupt. + */ + + status = IORD_ALTERA_AVALON_UART_STATUS(base); + + /* Clear any error flags set at the device */ + IOWR_ALTERA_AVALON_UART_STATUS(base, 0); + + /* Dummy read to ensure IRQ is negated before ISR returns */ + IORD_ALTERA_AVALON_UART_STATUS(base); + + /* process a read irq */ + if (status & ALTERA_AVALON_UART_STATUS_RRDY_MSK) + { + altera_avalon_uart_rxirq(sp, status); + } + + /* process a write irq */ + if (status & (ALTERA_AVALON_UART_STATUS_TRDY_MSK | + ALTERA_AVALON_UART_STATUS_DCTS_MSK)) + { + altera_avalon_uart_txirq(sp, status); + } + + +} + +/* + * altera_avalon_uart_rxirq() is called by altera_avalon_uart_irq() to + * process a receive interrupt. It transfers the incoming character into + * the receive circular buffer, and sets the apropriate flags to indicate + * that there is data ready to be processed. + */ +static void +altera_avalon_uart_rxirq(altera_avalon_uart_state* sp, alt_u32 status) +{ + alt_u32 next; + + /* If there was an error, discard the data */ + + if (status & (ALTERA_AVALON_UART_STATUS_PE_MSK | + ALTERA_AVALON_UART_STATUS_FE_MSK)) + { + return; + } + + /* + * In a multi-threaded environment, set the read event flag to indicate + * that there is data ready. This is only done if the circular buffer was + * previously empty. + */ + + if (sp->rx_end == sp->rx_start) + { + ALT_FLAG_POST (sp->events, ALT_UART_READ_RDY, OS_FLAG_SET); + } + + /* Determine which slot to use next in the circular buffer */ + + next = (sp->rx_end + 1) & ALT_AVALON_UART_BUF_MSK; + + /* Transfer data from the device to the circular buffer */ + + sp->rx_buf[sp->rx_end] = IORD_ALTERA_AVALON_UART_RXDATA(sp->base); + + sp->rx_end = next; + + next = (sp->rx_end + 1) & ALT_AVALON_UART_BUF_MSK; + + /* + * If the cicular buffer was full, disable interrupts. Interrupts will be + * re-enabled when data is removed from the buffer. + */ + + if (next == sp->rx_start) + { + sp->ctrl &= ~ALTERA_AVALON_UART_CONTROL_RRDY_MSK; + IOWR_ALTERA_AVALON_UART_CONTROL(sp->base, sp->ctrl); + } +} + +/* + * altera_avalon_uart_txirq() is called by altera_avalon_uart_irq() to + * process a transmit interrupt. It transfers data from the transmit + * buffer to the device, and sets the apropriate flags to indicate that + * there is data ready to be processed. + */ +static void +altera_avalon_uart_txirq(altera_avalon_uart_state* sp, alt_u32 status) +{ + /* Transfer data if there is some ready to be transfered */ + + if (sp->tx_start != sp->tx_end) + { + /* + * If the device is using flow control (i.e. RTS/CTS), then the + * transmitter is required to throttle if CTS is high. + */ + + if (!(sp->flags & ALT_AVALON_UART_FC) || + (status & ALTERA_AVALON_UART_STATUS_CTS_MSK)) + { + + /* + * In a multi-threaded environment, set the write event flag to indicate + * that there is space in the circular buffer. This is only done if the + * buffer was previously empty. + */ + + if (sp->tx_start == ((sp->tx_end + 1) & ALT_AVALON_UART_BUF_MSK)) + { + ALT_FLAG_POST (sp->events, + ALT_UART_WRITE_RDY, + OS_FLAG_SET); + } + + /* Write the data to the device */ + + IOWR_ALTERA_AVALON_UART_TXDATA(sp->base, sp->tx_buf[sp->tx_start]); + + sp->tx_start = (++sp->tx_start) & ALT_AVALON_UART_BUF_MSK; + + /* + * In case the tranmit interrupt had previously been disabled by + * detecting a low value on CTS, it is reenabled here. + */ + + sp->ctrl |= ALTERA_AVALON_UART_CONTROL_TRDY_MSK; + } + else + { + /* + * CTS is low and we are using flow control, so disable the transmit + * interrupt while we wait for CTS to go high again. This will be + * detected using the DCTS interrupt. + * + * There is a race condition here. "status" may indicate that + * CTS is low, but it actually went high before DCTS was cleared on + * the last write to the status register. To avoid this resulting in + * deadlock, it's necessary to re-check the status register here + * before throttling. + */ + + status = IORD_ALTERA_AVALON_UART_STATUS(sp->base); + + if (!(status & ALTERA_AVALON_UART_STATUS_CTS_MSK)) + { + sp->ctrl &= ~ALTERA_AVALON_UART_CONTROL_TRDY_MSK; + } + } + } + + /* + * If the circular buffer is empty, disable the interrupt. This will be + * re-enabled when new data is placed in the buffer. + */ + + if (sp->tx_start == sp->tx_end) + { + sp->ctrl &= ~(ALTERA_AVALON_UART_CONTROL_TRDY_MSK | + ALTERA_AVALON_UART_CONTROL_DCTS_MSK); + } + + IOWR_ALTERA_AVALON_UART_CONTROL(sp->base, sp->ctrl); +} + +/* + * The close() routine is implemented to drain the UART transmit buffer + * when not in "small" mode. This routine will wait for transimt data to be + * emptied unless the driver flags have been set to non-blocking mode. + * This routine should be called indirectly (i.e. though the C library + * close() routine) so that the file descriptor associated with the relevant + * stream (i.e. stdout) can be closed as well. This routine does not manage + * file descriptors. + * + * The close routine is not implemented for the small driver; instead it will + * map to null. This is because the small driver simply waits while characters + * are transmitted; there is no interrupt-serviced buffer to empty + */ +int altera_avalon_uart_close(altera_avalon_uart_state* sp, int flags) +{ + /* + * Wait for all transmit data to be emptied by the UART ISR. + */ + while (sp->tx_start != sp->tx_end) { + if (flags & O_NONBLOCK) { + return -EWOULDBLOCK; + } + } + + return 0; +} + +#endif /* fast driver */ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/drivers/src/altera_avalon_uart_ioctl.c b/MCandWifiTestDE0/Software/MCTest_bsp/drivers/src/altera_avalon_uart_ioctl.c new file mode 100644 index 00000000..eb4b2e30 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/drivers/src/altera_avalon_uart_ioctl.c @@ -0,0 +1,153 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include +#include + +#include "sys/alt_irq.h" +#include "sys/ioctl.h" +#include "sys/alt_errno.h" + +#include "altera_avalon_uart_regs.h" +#include "altera_avalon_uart.h" + + +#if !defined(ALT_USE_SMALL_DRIVERS) && !defined(ALTERA_AVALON_UART_SMALL) + +/* ----------------------------------------------------------- */ +/* ------------------------- FAST DRIVER --------------------- */ +/* ----------------------------------------------------------- */ + +/* + * To reduce the code footprint of this driver, the ioctl() function is not + * included by default. If you wish to use the ioctl features provided + * below, you can do so by adding the option : -DALTERA_AVALON_UART_USE_IOCTL + * to CPPFLAGS in the Makefile (or through the Eclipse IDE). + */ + +#ifdef ALTERA_AVALON_UART_USE_IOCTL + +/* + * altera_avalon_uart_ioctl() is called by the system ioctl() function to handle + * ioctl requests for the UART. The only ioctl requests supported are TIOCMGET + * and TIOCMSET. + * + * TIOCMGET returns a termios structure that describes the current device + * configuration. + * + * TIOCMSET sets the device (if possible) to match the requested configuration. + * The requested configuration is described using a termios structure passed + * through the input argument "arg". + */ + +static int altera_avalon_uart_tiocmget(altera_avalon_uart_state* sp, + struct termios* term); +static int altera_avalon_uart_tiocmset(altera_avalon_uart_state* sp, + struct termios* term); + +int +altera_avalon_uart_ioctl(altera_avalon_uart_state* sp, int req, void* arg) +{ + int rc = -ENOTTY; + + switch (req) + { + case TIOCMGET: + rc = altera_avalon_uart_tiocmget(sp, (struct termios*) arg); + break; + case TIOCMSET: + rc = altera_avalon_uart_tiocmset(sp, (struct termios*) arg); + break; + default: + break; + } + return rc; +} + +/* + * altera_avalon_uart_tiocmget() is used by altera_avalon_uart_ioctl() to fill + * in the input termios structure with the current device configuration. + * + * See termios.h for further details on the contents of the termios structure. + */ + +static int +altera_avalon_uart_tiocmget(altera_avalon_uart_state* sp, + struct termios* term) +{ + memcpy (term, &sp->termios, sizeof (struct termios)); + return 0; +} + +/* + * altera_avalon_uart_tiocmset() is used by altera_avalon_uart_ioctl() to + * configure the device according to the settings in the input termios + * structure. In practice the only configuration that can be changed is the + * baud rate, and then only if the hardware is configured to have a writable + * baud register. + */ + +static int +altera_avalon_uart_tiocmset(altera_avalon_uart_state* sp, + struct termios* term) +{ + speed_t speed; + + speed = sp->termios.c_ispeed; + + /* Update the settings if the hardware supports it */ + + if (!(sp->flags & ALT_AVALON_UART_FB)) + { + sp->termios.c_ispeed = sp->termios.c_ospeed = term->c_ispeed; + } + /* + * If the request was for an unsupported setting, return an error. + */ + + if (memcmp(term, &sp->termios, sizeof (struct termios))) + { + sp->termios.c_ispeed = sp->termios.c_ospeed = speed; + return -EIO; + } + + /* + * Otherwise, update the hardware. + */ + + IOWR_ALTERA_AVALON_UART_DIVISOR(sp->base, + ((sp->freq/sp->termios.c_ispeed) - 1)); + + return 0; +} + +#endif /* ALTERA_AVALON_UART_USE_IOCTL */ + +#endif /* fast driver */ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/drivers/src/altera_avalon_uart_read.c b/MCandWifiTestDE0/Software/MCTest_bsp/drivers/src/altera_avalon_uart_read.c new file mode 100644 index 00000000..8d14bdad --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/drivers/src/altera_avalon_uart_read.c @@ -0,0 +1,248 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include + +#include "sys/alt_irq.h" +#include "sys/ioctl.h" +#include "sys/alt_errno.h" + +#include "altera_avalon_uart.h" +#include "altera_avalon_uart_regs.h" + +#if defined(ALT_USE_SMALL_DRIVERS) || defined(ALTERA_AVALON_UART_SMALL) + +/* ----------------------------------------------------------- */ +/* ----------------------- SMALL DRIVER ---------------------- */ +/* ----------------------------------------------------------- */ + +/* + * altera_avalon_uart_read() is called by the system read() function in order to + * read a block of data from the UART. "len" is the maximum length of the data + * to read, and "ptr" indicates the destination address. "fd" is the file + * descriptor for the device to be read from. + * + * Permission checks are made before the call to altera_avalon_uart_read(), so + * we know that the file descriptor has been opened with the correct permissions + * for this operation. + * + * The return value is the number of bytes actually read. + * + * This implementation polls the device waiting for characters. At most it can + * only return one character, regardless of how many are requested. If the + * device is being accessed in non-blocking mode then it is possible for this + * function to return without reading any characters. In this case errno is + * set to EWOULDBLOCK. + */ + +int +altera_avalon_uart_read(altera_avalon_uart_state* sp, char* ptr, int len, + int flags) +{ + int block; + unsigned int status; + + block = !(flags & O_NONBLOCK); + + do + { + status = IORD_ALTERA_AVALON_UART_STATUS(sp->base); + + /* clear any error flags */ + + IOWR_ALTERA_AVALON_UART_STATUS(sp->base, 0); + + if (status & ALTERA_AVALON_UART_CONTROL_RRDY_MSK) + { + ptr[0] = IORD_ALTERA_AVALON_UART_RXDATA(sp->base); + + if (!(status & (ALTERA_AVALON_UART_STATUS_PE_MSK | + ALTERA_AVALON_UART_STATUS_FE_MSK))) + { + return 1; + } + } + } + while (block); + + ALT_ERRNO = EWOULDBLOCK; + + return 0; +} + +#else + +/* ----------------------------------------------------------- */ +/* ----------------------- FAST DRIVER ----------------------- */ +/* ----------------------------------------------------------- */ + +/* + * altera_avalon_uart_read() is called by the system read() function in order to + * read a block of data from the UART. "len" is the maximum length of the data + * to read, and "ptr" indicates the destination address. "sp" is the state + * pointer for the device to be read from. + * + * Permission checks are made before the call to altera_avalon_uart_read(), so + * we know that the file descriptor has been opened with the correct permissions + * for this operation. + * + * The return value is the number of bytes actually read. + * + * This function does not communicate with the device directly. Instead data is + * transfered from a circular buffer. The interrupt handler is then responsible + * for copying data from the device into this buffer. + */ + +int +altera_avalon_uart_read(altera_avalon_uart_state* sp, char* ptr, int len, + int flags) +{ + alt_irq_context context; + int block; + alt_u32 next; + alt_u8 read_would_block = 0; + int count = 0; + + /* + * Construct a flag to indicate whether the device is being accessed in + * blocking or non-blocking mode. + */ + + block = !(flags & O_NONBLOCK); + + /* + * When running in a multi threaded environment, obtain the "read_lock" + * semaphore. This ensures that reading from the device is thread-safe. + */ + + ALT_SEM_PEND (sp->read_lock, 0); + + /* + * Calculate which slot in the circular buffer is the next one to read + * data from. + */ + + next = (sp->rx_start + 1) & ALT_AVALON_UART_BUF_MSK; + + /* + * Loop, copying data from the circular buffer to the destination address + * supplied in "ptr". This loop is terminated when the required number of + * bytes have been read. If the circular buffer is empty, and no data has + * been read, then the loop will block (when in blocking mode). + * + * If the circular buffer is empty, and some data has already been + * transferred, or the device is being accessed in non-blocking mode, then + * the loop terminates without necessarily reading all the requested data. + */ + + do + { + /* + * Read the required amount of data, until the circular buffer runs + * empty + */ + + while ((count < len) && (sp->rx_start != sp->rx_end)) + { + count++; + *ptr++ = sp->rx_buf[sp->rx_start]; + + sp->rx_start = (++sp->rx_start) & ALT_AVALON_UART_BUF_MSK; + } + + /* + * If no data has been transferred, the circular buffer is empty, and + * this is not a non-blocking access, block waiting for data to arrive. + */ + + if (!count && (sp->rx_start == sp->rx_end)) + { + if (!block) + { + /* Set errno to indicate the reason we're not returning any data */ + + ALT_ERRNO = EWOULDBLOCK; + read_would_block = 1; + break; + } + else + { + /* Block waiting for some data to arrive */ + + /* First, ensure read interrupts are enabled to avoid deadlock */ + + context = alt_irq_disable_all (); + sp->ctrl |= ALTERA_AVALON_UART_CONTROL_RRDY_MSK; + IOWR_ALTERA_AVALON_UART_CONTROL(sp->base, sp->ctrl); + alt_irq_enable_all (context); + + /* + * When running in a multi-threaded mode, we pend on the read event + * flag set in the interrupt service routine. This avoids wasting CPU + * cycles waiting in this thread, when we could be doing something more + * profitable elsewhere. + */ + + ALT_FLAG_PEND (sp->events, + ALT_UART_READ_RDY, + OS_FLAG_WAIT_SET_ANY + OS_FLAG_CONSUME, + 0); + } + } + } + while (!count && len); + + /* + * Now that access to the circular buffer is complete, release the read + * semaphore so that other threads can access the buffer. + */ + + ALT_SEM_POST (sp->read_lock); + + /* + * Ensure that interrupts are enabled, so that the circular buffer can + * re-fill. + */ + + context = alt_irq_disable_all (); + sp->ctrl |= ALTERA_AVALON_UART_CONTROL_RRDY_MSK; + IOWR_ALTERA_AVALON_UART_CONTROL(sp->base, sp->ctrl); + alt_irq_enable_all (context); + + /* Return the number of bytes read */ + if(read_would_block) { + return ~EWOULDBLOCK; + } + else { + return count; + } +} + +#endif /* fast driver */ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/drivers/src/altera_avalon_uart_write.c b/MCandWifiTestDE0/Software/MCTest_bsp/drivers/src/altera_avalon_uart_write.c new file mode 100644 index 00000000..cb23d1f8 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/drivers/src/altera_avalon_uart_write.c @@ -0,0 +1,232 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +******************************************************************************/ + +#include + +#include "sys/alt_dev.h" +#include "sys/alt_irq.h" +#include "sys/ioctl.h" +#include "sys/alt_errno.h" + +#include "altera_avalon_uart_regs.h" +#include "altera_avalon_uart.h" + +#if defined(ALT_USE_SMALL_DRIVERS) || defined(ALTERA_AVALON_UART_SMALL) + +/* ----------------------------------------------------------- */ +/* ------------------------ SMALL DRIVER --------------------- */ +/* ----------------------------------------------------------- */ + +/* + * altera_avalon_uart_write() is called by the system write() function in + * order to write a block of data to the UART. + * "len" is the length of the data to write, + * and "ptr" indicates the source address. "fd" is the file descriptor for the + * device to be read from. + * + * Permission checks are made before the call to altera_avalon_uart_write(), so + * we know that the file descriptor has been opened with the correct permissions + * for this operation. + * + * The return value is the number of bytes actually written. + * + * This function will block on the devices transmit register, until all + * characters have been transmitted. This is unless the device is being + * accessed in non-blocking mode. In this case this function will return as + * soon as the device reports that it is not ready to transmit. + * + * Since this is the small footprint version of the UART driver, the value of + * CTS is ignored. + */ + +int +altera_avalon_uart_write(altera_avalon_uart_state* sp, const char* ptr, int len, + int flags) +{ + int block; + unsigned int status; + int count; + + block = !(flags & O_NONBLOCK); + count = len; + + do + { + status = IORD_ALTERA_AVALON_UART_STATUS(sp->base); + + if (status & ALTERA_AVALON_UART_STATUS_TRDY_MSK) + { + IOWR_ALTERA_AVALON_UART_TXDATA(sp->base, *ptr++); + count--; + } + } + while (block && count); + + if (count) + { + ALT_ERRNO = EWOULDBLOCK; + } + + return (len - count); +} + +#else /* Using the "fast" version of the driver */ + +/* ----------------------------------------------------------- */ +/* ------------------------- FAST DRIVER --------------------- */ +/* ----------------------------------------------------------- */ + +/* + * altera_avalon_uart_write() is called by the system write() function in order + * to write a block of data to the UART. "len" is the length of the data to + * write, and "ptr" indicates the source address. "sp" is the state pointer + * for the device to be written to. + * + * Permission checks are made before the call to altera_avalon_uart_write(), so + * we know that the file descriptor has been opened with the correct permissions + * for this operation. + * + * The return value is the number of bytes actually written. + * + * This function does not communicate with the device directly. Instead data is + * transfered to a circular buffer. The interrupt handler is then responsible + * for copying data from this buffer into the device. + */ + +int +altera_avalon_uart_write(altera_avalon_uart_state* sp, const char* ptr, int len, + int flags) +{ + alt_irq_context context; + int no_block; + alt_u32 next; + int count = len; + + /* + * Construct a flag to indicate whether the device is being accessed in + * blocking or non-blocking mode. + */ + + no_block = (flags & O_NONBLOCK); + + /* + * When running in a multi threaded environment, obtain the "write_lock" + * semaphore. This ensures that writing to the device is thread-safe. + */ + + ALT_SEM_PEND (sp->write_lock, 0); + + /* + * Loop transferring data from the input buffer to the transmit circular + * buffer. The loop is terminated once all the data has been transferred, + * or, (if in non-blocking mode) the buffer becomes full. + */ + + while (count) + { + /* Determine the next slot in the buffer to access */ + + next = (sp->tx_end + 1) & ALT_AVALON_UART_BUF_MSK; + + /* block waiting for space if necessary */ + + if (next == sp->tx_start) + { + if (no_block) + { + /* Set errno to indicate why this function returned early */ + + ALT_ERRNO = EWOULDBLOCK; + break; + } + else + { + /* Block waiting for space in the circular buffer */ + + /* First, ensure transmit interrupts are enabled to avoid deadlock */ + + context = alt_irq_disable_all (); + sp->ctrl |= (ALTERA_AVALON_UART_CONTROL_TRDY_MSK | + ALTERA_AVALON_UART_CONTROL_DCTS_MSK); + IOWR_ALTERA_AVALON_UART_CONTROL(sp->base, sp->ctrl); + alt_irq_enable_all (context); + + /* wait for space to come free */ + + do + { + /* + * When running in a multi-threaded mode, we pend on the write event + * flag set in the interrupt service routine. This avoids wasting CPU + * cycles waiting in this thread, when we could be doing something + * more profitable elsewhere. + */ + + ALT_FLAG_PEND (sp->events, + ALT_UART_WRITE_RDY, + OS_FLAG_WAIT_SET_ANY + OS_FLAG_CONSUME, + 0); + } + while ((next == sp->tx_start)); + } + } + + count--; + + /* Add the next character to the transmit buffer */ + + sp->tx_buf[sp->tx_end] = *ptr++; + sp->tx_end = next; + } + + /* + * Now that access to the circular buffer is complete, release the write + * semaphore so that other threads can access the buffer. + */ + + ALT_SEM_POST (sp->write_lock); + + /* + * Ensure that interrupts are enabled, so that the circular buffer can + * drain. + */ + + context = alt_irq_disable_all (); + sp->ctrl |= ALTERA_AVALON_UART_CONTROL_TRDY_MSK | + ALTERA_AVALON_UART_CONTROL_DCTS_MSK; + IOWR_ALTERA_AVALON_UART_CONTROL(sp->base, sp->ctrl); + alt_irq_enable_all (context); + + /* return the number of bytes written */ + + return (len - count); +} + +#endif /* fast driver */ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/drivers/src/altera_up_avalon_rs232.c b/MCandWifiTestDE0/Software/MCTest_bsp/drivers/src/altera_up_avalon_rs232.c new file mode 100644 index 00000000..3a22b7a9 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/drivers/src/altera_up_avalon_rs232.c @@ -0,0 +1,145 @@ +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2007 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +* * +******************************************************************************/ + +#include + +#include + +#include "altera_up_avalon_rs232.h" +#include "altera_up_avalon_rs232_regs.h" + + +void alt_up_rs232_enable_read_interrupt(alt_up_rs232_dev *rs232) +{ + alt_u32 ctrl_reg; + ctrl_reg = IORD_ALT_UP_RS232_CONTROL(rs232->base); + // set RE to 1 while maintaining other bits the same + ctrl_reg |= ALT_UP_RS232_CONTROL_RE_MSK; + IOWR_ALT_UP_RS232_CONTROL(rs232->base, ctrl_reg); +} + +void alt_up_rs232_disable_read_interrupt(alt_up_rs232_dev *rs232) +{ + alt_u32 ctrl_reg; + ctrl_reg = IORD_ALT_UP_RS232_CONTROL(rs232->base); + // set RE to 0 while maintaining other bits the same + ctrl_reg &= ~ALT_UP_RS232_CONTROL_RE_MSK; + IOWR_ALT_UP_RS232_CONTROL(rs232->base, ctrl_reg); +} + +unsigned alt_up_rs232_get_used_space_in_read_FIFO(alt_up_rs232_dev *rs232) +{ + alt_u16 ravail = 0; + // we can only read the 16 bits for RAVAIL --- a read of DATA will discard the data +// ravail = IORD_16DIRECT(IOADDR_ALT_UP_RS232_DATA(rs232->base), 2); + ravail = IORD_ALT_UP_RS232_RAVAIL(rs232->base); +// return ravail; + return (ravail & ALT_UP_RS232_RAVAIL_MSK) >> ALT_UP_RS232_RAVAIL_OFST; +} + +unsigned alt_up_rs232_get_available_space_in_write_FIFO(alt_up_rs232_dev *rs232) +{ + alt_u32 ctrl_reg; + ctrl_reg = IORD_ALT_UP_RS232_CONTROL(rs232->base); + return (ctrl_reg & ALT_UP_RS232_CONTROL_WSPACE_MSK) >> ALT_UP_RS232_CONTROL_WSPACE_OFST; +} + +int alt_up_rs232_check_parity(alt_u32 data_reg) +{ + unsigned parity_error = (data_reg & ALT_UP_RS232_DATA_PE_MSK) >> ALT_UP_RS232_DATA_PE_OFST; + return (parity_error ? -1 : 0); +} + +int alt_up_rs232_write_data(alt_up_rs232_dev *rs232, alt_u8 data) +{ + alt_u32 data_reg; + data_reg = IORD_ALT_UP_RS232_DATA(rs232->base); + + // we can write directly without thinking about other bit fields for this + // case ONLY, because only DATA field of the data register is writable + IOWR_ALT_UP_RS232_DATA(rs232->base, (data>>ALT_UP_RS232_DATA_DATA_OFST) & ALT_UP_RS232_DATA_DATA_MSK); + return 0; +} + +int alt_up_rs232_read_data(alt_up_rs232_dev *rs232, alt_u8 *data, alt_u8 *parity_error) +{ + alt_u32 data_reg; + data_reg = IORD_ALT_UP_RS232_DATA(rs232->base); + *data = (data_reg & ALT_UP_RS232_DATA_DATA_MSK) >> ALT_UP_RS232_DATA_DATA_OFST; + *parity_error = alt_up_rs232_check_parity(data_reg); + return (((data_reg & ALT_UP_RS232_DATA_RVALID_MSK) >> ALT_UP_RS232_DATA_RVALID_OFST) - 1); +} + +int alt_up_rs232_read_fd (alt_fd* fd, char* ptr, int len) +{ + alt_up_rs232_dev *rs232 = (alt_up_rs232_dev*)fd->dev; + int count = 0; + alt_u8 parity_error; + while(len--) + { + if (alt_up_rs232_read_data(rs232, ptr++, &parity_error)==0) + count++; + else + break; + } + return count; +} + +int alt_up_rs232_write_fd (alt_fd* fd, const char* ptr, int len) +{ + alt_up_rs232_dev *rs232 = (alt_up_rs232_dev*)fd->dev; + int count = 0; + while(len--) + { + if (alt_up_rs232_write_data(rs232, *ptr)==0) + { + count++; + ptr++; + } + else + break; + } + return count; +} + +alt_up_rs232_dev* alt_up_rs232_open_dev(const char* name) +{ + // find the device from the device list + // (see altera_hal/HAL/inc/priv/alt_file.h + // and altera_hal/HAL/src/alt_find_dev.c + // for details) + alt_up_rs232_dev *dev = (alt_up_rs232_dev*)alt_find_dev(name, &alt_dev_list); + + return dev; +} + diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/libucosii_bsp.a b/MCandWifiTestDE0/Software/MCTest_bsp/libucosii_bsp.a new file mode 100644 index 00000000..f2115049 Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/libucosii_bsp.a differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/linker.h b/MCandWifiTestDE0/Software/MCTest_bsp/linker.h new file mode 100644 index 00000000..1a4c67db --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/linker.h @@ -0,0 +1,101 @@ +/* + * linker.h - Linker script mapping information + * + * Machine generated for CPU 'cpu' in SOPC Builder design 'system' + * SOPC Builder design path: C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system.sopcinfo + * + * Generated: Mon Mar 03 15:52:38 MST 2014 + */ + +/* + * DO NOT MODIFY THIS FILE + * + * Changing this file will have subtle consequences + * which will almost certainly lead to a nonfunctioning + * system. If you do modify this file, be aware that your + * changes will be overwritten and lost when this file + * is generated again. + * + * DO NOT MODIFY THIS FILE + */ + +/* + * License Agreement + * + * Copyright (c) 2008 + * Altera Corporation, San Jose, California, USA. + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * This agreement shall be governed in all respects by the laws of the State + * of California and by the laws of the United States of America. + */ + +#ifndef __LINKER_H_ +#define __LINKER_H_ + + +/* + * BSP controls alt_load() behavior in crt0. + * + */ + +#define ALT_LOAD_EXPLICITLY_CONTROLLED + + +/* + * Base address and span (size in bytes) of each linker region + * + */ + +#define RESET_REGION_BASE 0x1000000 +#define RESET_REGION_SPAN 32 +#define SDRAM_REGION_BASE 0x1000020 +#define SDRAM_REGION_SPAN 16777184 + + +/* + * Devices associated with code sections + * + */ + +#define ALT_EXCEPTIONS_DEVICE SDRAM +#define ALT_RESET_DEVICE SDRAM +#define ALT_RODATA_DEVICE SDRAM +#define ALT_RWDATA_DEVICE SDRAM +#define ALT_TEXT_DEVICE SDRAM + + +/* + * Initialization code at the reset address is allowed (e.g. no external bootloader). + * + */ + +#define ALT_ALLOW_CODE_AT_RESET + + +/* + * The alt_load() facility is called from crt0 to copy sections into RAM. + * + */ + +#define ALT_LOAD_COPY_RWDATA + +#endif /* __LINKER_H_ */ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/linker.x b/MCandWifiTestDE0/Software/MCTest_bsp/linker.x new file mode 100644 index 00000000..ac831e61 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/linker.x @@ -0,0 +1,385 @@ +/* + * linker.x - Linker script + * + * Machine generated for CPU 'cpu' in SOPC Builder design 'system' + * SOPC Builder design path: C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system.sopcinfo + * + * Generated: Mon Mar 03 15:52:38 MST 2014 + */ + +/* + * DO NOT MODIFY THIS FILE + * + * Changing this file will have subtle consequences + * which will almost certainly lead to a nonfunctioning + * system. If you do modify this file, be aware that your + * changes will be overwritten and lost when this file + * is generated again. + * + * DO NOT MODIFY THIS FILE + */ + +/* + * License Agreement + * + * Copyright (c) 2008 + * Altera Corporation, San Jose, California, USA. + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * This agreement shall be governed in all respects by the laws of the State + * of California and by the laws of the United States of America. + */ + +MEMORY +{ + reset : ORIGIN = 0x1000000, LENGTH = 32 + sdram : ORIGIN = 0x1000020, LENGTH = 16777184 +} + +/* Define symbols for each memory base-address */ +__alt_mem_sdram = 0x1000000; + +OUTPUT_FORMAT( "elf32-littlenios2", + "elf32-littlenios2", + "elf32-littlenios2" ) +OUTPUT_ARCH( nios2 ) +ENTRY( _start ) + +/* + * The alt_load() facility is enabled. This typically happens when there isn't + * an external bootloader (e.g. flash bootloader). + * The LMA (aka physical address) of each loaded section is + * set to the .text memory device. + * The HAL alt_load() routine called from crt0 copies sections from + * the .text memory to RAM as needed. + */ + +SECTIONS +{ + + /* + * Output sections associated with reset and exceptions (they have to be first) + */ + + .entry : + { + KEEP (*(.entry)) + } > reset + + .exceptions : + { + PROVIDE (__ram_exceptions_start = ABSOLUTE(.)); + . = ALIGN(0x20); + KEEP (*(.irq)); + KEEP (*(.exceptions.entry.label)); + KEEP (*(.exceptions.entry.user)); + KEEP (*(.exceptions.entry)); + KEEP (*(.exceptions.irqtest.user)); + KEEP (*(.exceptions.irqtest)); + KEEP (*(.exceptions.irqhandler.user)); + KEEP (*(.exceptions.irqhandler)); + KEEP (*(.exceptions.irqreturn.user)); + KEEP (*(.exceptions.irqreturn)); + KEEP (*(.exceptions.notirq.label)); + KEEP (*(.exceptions.notirq.user)); + KEEP (*(.exceptions.notirq)); + KEEP (*(.exceptions.soft.user)); + KEEP (*(.exceptions.soft)); + KEEP (*(.exceptions.unknown.user)); + KEEP (*(.exceptions.unknown)); + KEEP (*(.exceptions.exit.label)); + KEEP (*(.exceptions.exit.user)); + KEEP (*(.exceptions.exit)); + KEEP (*(.exceptions)); + PROVIDE (__ram_exceptions_end = ABSOLUTE(.)); + } > sdram + + PROVIDE (__flash_exceptions_start = LOADADDR(.exceptions)); + + .text : + { + /* + * All code sections are merged into the text output section, along with + * the read only data sections. + * + */ + + PROVIDE (stext = ABSOLUTE(.)); + + *(.interp) + *(.hash) + *(.dynsym) + *(.dynstr) + *(.gnu.version) + *(.gnu.version_d) + *(.gnu.version_r) + *(.rel.init) + *(.rela.init) + *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) + *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) + *(.rel.fini) + *(.rela.fini) + *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) + *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) + *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) + *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) + *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) + *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) + *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) + *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) + *(.rel.ctors) + *(.rela.ctors) + *(.rel.dtors) + *(.rela.dtors) + *(.rel.got) + *(.rela.got) + *(.rel.sdata .rel.sdata.* .rel.gnu.linkonce.s.*) + *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*) + *(.rel.sbss .rel.sbss.* .rel.gnu.linkonce.sb.*) + *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*) + *(.rel.sdata2 .rel.sdata2.* .rel.gnu.linkonce.s2.*) + *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*) + *(.rel.sbss2 .rel.sbss2.* .rel.gnu.linkonce.sb2.*) + *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*) + *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) + *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) + *(.rel.plt) + *(.rela.plt) + *(.rel.dyn) + + KEEP (*(.init)) + *(.plt) + *(.text .stub .text.* .gnu.linkonce.t.*) + + /* .gnu.warning sections are handled specially by elf32.em. */ + + *(.gnu.warning.*) + KEEP (*(.fini)) + PROVIDE (__etext = ABSOLUTE(.)); + PROVIDE (_etext = ABSOLUTE(.)); + PROVIDE (etext = ABSOLUTE(.)); + + *(.eh_frame_hdr) + /* Ensure the __preinit_array_start label is properly aligned. We + could instead move the label definition inside the section, but + the linker would then create the section even if it turns out to + be empty, which isn't pretty. */ + . = ALIGN(4); + PROVIDE (__preinit_array_start = ABSOLUTE(.)); + *(.preinit_array) + PROVIDE (__preinit_array_end = ABSOLUTE(.)); + PROVIDE (__init_array_start = ABSOLUTE(.)); + *(.init_array) + PROVIDE (__init_array_end = ABSOLUTE(.)); + PROVIDE (__fini_array_start = ABSOLUTE(.)); + *(.fini_array) + PROVIDE (__fini_array_end = ABSOLUTE(.)); + SORT(CONSTRUCTORS) + KEEP (*(.eh_frame)) + *(.gcc_except_table) + *(.dynamic) + PROVIDE (__CTOR_LIST__ = ABSOLUTE(.)); + KEEP (*(.ctors)) + KEEP (*(SORT(.ctors.*))) + PROVIDE (__CTOR_END__ = ABSOLUTE(.)); + PROVIDE (__DTOR_LIST__ = ABSOLUTE(.)); + KEEP (*(.dtors)) + KEEP (*(SORT(.dtors.*))) + PROVIDE (__DTOR_END__ = ABSOLUTE(.)); + KEEP (*(.jcr)) + . = ALIGN(4); + } > sdram = 0x3a880100 /* Nios II NOP instruction */ + + .rodata : + { + PROVIDE (__ram_rodata_start = ABSOLUTE(.)); + . = ALIGN(4); + *(.rodata .rodata.* .gnu.linkonce.r.*) + *(.rodata1) + . = ALIGN(4); + PROVIDE (__ram_rodata_end = ABSOLUTE(.)); + } > sdram + + PROVIDE (__flash_rodata_start = LOADADDR(.rodata)); + + /* + * + * This section's LMA is set to the .text region. + * crt0 will copy to this section's specified mapped region virtual memory address (VMA) + * + * .rwdata region equals the .text region, and is set to be loaded into .text region. + * This requires two copies of .rwdata in the .text region. One read writable at VMA. + * and one read-only at LMA. crt0 will copy from LMA to VMA on reset + * + */ + + .rwdata LOADADDR (.rodata) + SIZEOF (.rodata) : AT ( LOADADDR (.rodata) + SIZEOF (.rodata)+ SIZEOF (.rwdata) ) + { + PROVIDE (__ram_rwdata_start = ABSOLUTE(.)); + . = ALIGN(4); + *(.got.plt) *(.got) + *(.data1) + *(.data .data.* .gnu.linkonce.d.*) + + _gp = ABSOLUTE(. + 0x8000); + PROVIDE(gp = _gp); + + *(.rwdata .rwdata.*) + *(.sdata .sdata.* .gnu.linkonce.s.*) + *(.sdata2 .sdata2.* .gnu.linkonce.s2.*) + + . = ALIGN(4); + _edata = ABSOLUTE(.); + PROVIDE (edata = ABSOLUTE(.)); + PROVIDE (__ram_rwdata_end = ABSOLUTE(.)); + } > sdram + + PROVIDE (__flash_rwdata_start = LOADADDR(.rwdata)); + + /* + * + * This section's LMA is set to the .text region. + * crt0 will copy to this section's specified mapped region virtual memory address (VMA) + * + */ + + .bss LOADADDR (.rwdata) + SIZEOF (.rwdata) : AT ( LOADADDR (.rwdata) + SIZEOF (.rwdata) ) + { + __bss_start = ABSOLUTE(.); + PROVIDE (__sbss_start = ABSOLUTE(.)); + PROVIDE (___sbss_start = ABSOLUTE(.)); + + *(.dynsbss) + *(.sbss .sbss.* .gnu.linkonce.sb.*) + *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*) + *(.scommon) + + PROVIDE (__sbss_end = ABSOLUTE(.)); + PROVIDE (___sbss_end = ABSOLUTE(.)); + + *(.dynbss) + *(.bss .bss.* .gnu.linkonce.b.*) + *(COMMON) + + . = ALIGN(4); + __bss_end = ABSOLUTE(.); + } > sdram + + /* + * + * One output section mapped to the associated memory device for each of + * the available memory devices. These are not used by default, but can + * be used by user applications by using the .section directive. + * + * The output section used for the heap is treated in a special way, + * i.e. the symbols "end" and "_end" are added to point to the heap start. + * + * Because alt_load() is enabled, these sections have + * their LMA set to be loaded into the .text memory region. + * However, the alt_load() code will NOT automatically copy + * these sections into their mapped memory region. + * + */ + + /* + * + * This section's LMA is set to the .text region. + * crt0 will copy to this section's specified mapped region virtual memory address (VMA) + * + */ + + .sdram LOADADDR (.bss) + SIZEOF (.bss) : AT ( LOADADDR (.bss) + SIZEOF (.bss) ) + { + PROVIDE (_alt_partition_sdram_start = ABSOLUTE(.)); + *(.sdram. sdram.*) + . = ALIGN(4); + PROVIDE (_alt_partition_sdram_end = ABSOLUTE(.)); + _end = ABSOLUTE(.); + end = ABSOLUTE(.); + __alt_stack_base = ABSOLUTE(.); + } > sdram + + PROVIDE (_alt_partition_sdram_load_addr = LOADADDR(.sdram)); + + /* + * Stabs debugging sections. + * + */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + + /* Altera debug extensions */ + .debug_alt_sim_info 0 : { *(.debug_alt_sim_info) } +} + +/* provide a pointer for the stack */ + +/* + * Don't override this, override the __alt_stack_* symbols instead. + */ +__alt_data_end = 0x2000000; + +/* + * The next two symbols define the location of the default stack. You can + * override them to move the stack to a different memory. + */ +PROVIDE( __alt_stack_pointer = __alt_data_end ); +PROVIDE( __alt_stack_limit = __alt_stack_base ); + +/* + * This symbol controls where the start of the heap is. If the stack is + * contiguous with the heap then the stack will contract as memory is + * allocated to the heap. + * Override this symbol to put the heap in a different memory. + */ +PROVIDE( __alt_heap_start = end ); +PROVIDE( __alt_heap_limit = 0x2000000 ); diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/mem_init.mk b/MCandWifiTestDE0/Software/MCTest_bsp/mem_init.mk new file mode 100644 index 00000000..90c8af0c --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/mem_init.mk @@ -0,0 +1,319 @@ + +######################################################################### +####### M E M I N I T M A K E F I L E C O N T E N T ###### +######################################################################### + +######################################################################### +# This file is intended to be included by public.mk +# +# +# The following variables must be defined before including this file: +# - ELF +# +# The following variables may be defined to override the default behavior: +# - HDL_SIM_DIR +# - HDL_SIM_INSTALL_DIR +# - MEM_INIT_DIR +# - MEM_INIT_INSTALL_DIR +# - QUARTUS_PROJECT_DIR +# - SOPC_NAME +# - SIM_OPTIMIZE +# - RESET_ADDRESS +# +######################################################################### + +ifeq ($(MEM_INIT_FILE),) +# MEM_INIT_FILE should be set equal to the working relative path to this +# mem_init.mk makefile fragment +MEM_INIT_FILE := $(wildcard $(word $(words $(MAKEFILE_LIST)),$(MAKEFILE_LIST))) +endif + +ifeq ($(ELF2DAT),) +ELF2DAT := elf2dat +endif + +ifeq ($(ELF2HEX),) +ELF2HEX := elf2hex +endif + +ifeq ($(ELF2FLASH),) +ELF2FLASH := elf2flash +endif + +ifeq ($(FLASH2DAT),) +FLASH2DAT := flash2dat +endif + +ifeq ($(NM),) +NM := nios2-elf-nm +endif + +ifeq ($(MKDIR),) +MKDIR := mkdir -p +endif + +ifeq ($(RM),) +RM := rm -f +endif + +ifeq ($(CP),) +CP := cp +endif + +ifeq ($(ECHO),) +ECHO := echo +endif + +MEM_INIT_DIR ?= mem_init +HDL_SIM_DIR ?= $(MEM_INIT_DIR)/hdl_sim + +ifdef QUARTUS_PROJECT_DIR +MEM_INIT_INSTALL_DIR ?= $(patsubst %/,%,$(QUARTUS_PROJECT_DIR)) +ifdef SOPC_NAME +HDL_SIM_INSTALL_DIR ?= $(patsubst %/,%,$(QUARTUS_PROJECT_DIR))/$(SOPC_NAME)_sim +endif +endif + +MEM_INIT_DESCRIPTOR_FILE ?= $(MEM_INIT_DIR)/meminit.spd + +MEM_INIT_QIP_FILE ?= $(MEM_INIT_DIR)/meminit.qip + +#------------------------------------- +# Default Flash Boot Loaders +#------------------------------------- + +BOOT_LOADER_PATH ?= $(SOPC_KIT_NIOS2)/components/altera_nios2 +BOOT_LOADER_CFI ?= $(BOOT_LOADER_PATH)/boot_loader_cfi.srec +BOOT_LOADER_CFI_BE ?= $(BOOT_LOADER_PATH)/boot_loader_cfi_be.srec + + +#------------------------------------- +# Default Target +#------------------------------------- + +.PHONY: default_mem_init +ifeq ($(QSYS),1) +default_mem_init: mem_init_generate +else +default_mem_init: mem_init_install +endif +#------------------------------------- +# Runtime Macros +#------------------------------------- + +define post-process-info + @echo Post-processing to create $@... +endef + +target_stem = $(notdir $(basename $@)) + +mem_start_address = $($(target_stem)_START) +mem_end_address = $($(target_stem)_END) +mem_width = $($(target_stem)_WIDTH) +mem_endianness = $($(target_stem)_ENDIANNESS) +mem_create_lanes = $($(target_stem)_CREATE_LANES) + +mem_pad_flag = $($(target_stem)_PAD_FLAG) +mem_reloc_input_flag = $($(target_stem)_RELOC_INPUT_FLAG) +mem_no_zero_fill_flag = $($(target_stem)_NO_ZERO_FILL_FLAG) + +flash_mem_epcs_flag = $($(target_stem)_EPCS_FLAGS) +flash_mem_cfi_flag = $($(target_stem)_CFI_FLAGS) +flash_mem_boot_loader_flag = $($(target_stem)_BOOT_LOADER_FLAG) + +elf2dat_extra_args = $(mem_pad_flag) +elf2hex_extra_args = $(mem_no_zero_fill_flag) +elf2flash_extra_args = $(flash_mem_cfi_flag) $(flash_mem_epcs_flag) $(flash_mem_boot_loader_flag) +flash2dat_extra_args = $(mem_pad_flag) $(mem_reloc_input_flag) + +#------------------------------------------------------------------------------ +# BSP SPECIFIC CONTENT +# +# The content below is controlled by the BSP and SOPC System +#------------------------------------------------------------------------------ +#START OF BSP SPECIFIC + +#------------------------------------- +# Global Settings +#------------------------------------- + + +# The following TYPE comment allows tools to identify the 'type' of target this +# makefile is associated with. +# TYPE: BSP_MEMINIT_MAKEFILE + +# This following VERSION comment indicates the version of the tool used to +# generate this makefile. A makefile variable is provided for VERSION as well. +# ACDS_VERSION: 12.1sp1 +ACDS_VERSION := 12.1sp1 + +# This following BUILD_NUMBER comment indicates the build number of the tool +# used to generate this makefile. +# BUILD_NUMBER: 243 + +# Optimize for simulation +SIM_OPTIMIZE ?= 0 + +# The CPU reset address as needed by elf2flash +RESET_ADDRESS ?= 0x01000000 + +#------------------------------------- +# Pre-Initialized Memory Descriptions +#------------------------------------- + +# Memory: sdram +MEM_0 := sdram +$(MEM_0)_NAME := sdram +DAT_FILES += $(HDL_SIM_DIR)/$(MEM_0).dat +HDL_SIM_INSTALL_FILES += $(HDL_SIM_INSTALL_DIR)/$(MEM_0).dat +SYM_FILES += $(HDL_SIM_DIR)/$(MEM_0).sym +HDL_SIM_INSTALL_FILES += $(HDL_SIM_INSTALL_DIR)/$(MEM_0).sym +$(MEM_0)_START := 0x01000000 +$(MEM_0)_END := 0x01ffffff +$(MEM_0)_HIERARCHICAL_PATH := sdram +$(MEM_0)_WIDTH := 16 +$(MEM_0)_ENDIANNESS := --little-endian-mem +$(MEM_0)_CREATE_LANES := 0 + +.PHONY: sdram +sdram: check_elf_exists $(HDL_SIM_DIR)/$(MEM_0).dat $(HDL_SIM_DIR)/$(MEM_0).sym + + +#END OF BSP SPECIFIC + +#------------------------------------- +# Pre-Initialized Memory Targets +#------------------------------------- + +.PHONY: mem_init_install mem_init_generate mem_init_clean + +ifeq ($(QSYS),1) +# Target mem_init_install is deprecated for QSys based systems +# To initialize onchip memories for Quartus II Synthesis with Qsys based systems: +# 1) Use "make mem_init_genearate" +# 2) Add the generated mem_init/meminit.qip file to your Quartus II Project +# +mem_init_install: + $(error Deprecated Makefile Target: '$@'. Use target 'mem_init_generate' and then add $(MEM_INIT_QIP_FILE) to your Quartus II Project) + +else # QSYS != 1, if SopcBuilder based system + +ifneq ($(MEM_INIT_INSTALL_DIR),) +mem_init_install: $(MEM_INIT_INSTALL_FILES) +endif + +ifneq ($(HDL_SIM_INSTALL_DIR),) +mem_init_install: $(HDL_SIM_INSTALL_FILES) +endif + +mem_init_install: mem_init_generate +ifeq ($(MEM_INIT_INSTALL_DIR),) + @echo "WARNING: MEM_INIT_INSTALL_DIR not set. Set your QUARTUS_PROJECT_DIR environment variable." +endif +ifeq ($(HDL_SIM_INSTALL_DIR),) + @echo "WARNING: HDL_SIM_INSTALL_DIR not set. Set your QUARTUS_PROJECT_DIR and SOPC_NAME environment variable." +endif + +$(MEM_INIT_INSTALL_FILES): $(MEM_INIT_INSTALL_DIR)/%: $(MEM_INIT_DIR)/% + @$(MKDIR) $(@D) + @$(CP) -v $< $@ + +$(HDL_SIM_INSTALL_FILES): $(HDL_SIM_INSTALL_DIR)/%: $(HDL_SIM_DIR)/% + @$(MKDIR) $(@D) + @$(CP) -v $< $@ + +endif # QSYS == 1 + + +mem_init_generate: hex dat sym flash $(MEM_INIT_DESCRIPTOR_FILE) $(MEM_INIT_QIP_FILE) + +mem_init_clean: + @$(RM) -r $(MEM_INIT_DIR) $(HDL_SIM_DIR) $(FLASH_FILES) + +.PHONY: hex dat sym flash + +hex: check_elf_exists $(HEX_FILES) + +dat: check_elf_exists $(DAT_FILES) + +sym: check_elf_exists $(SYM_FILES) + +flash: check_elf_exists $(FLASH_FILES) + +#------------------------------------- +# Pre-Initialized Memory Rules +#------------------------------------- + +.PHONY: check_elf_exists +check_elf_exists: $(ELF) +ifeq ($(ELF),) + $(error ELF var not set in mem_init.mk) +endif + +$(filter-out $(FLASH_DAT_FILES),$(DAT_FILES)): %.dat: $(ELF) + $(post-process-info) + @$(MKDIR) $(@D) + bash -c '$(ELF2DAT) --infile=$< --outfile=$@ \ + --base=$(mem_start_address) --end=$(mem_end_address) --width=$(mem_width) \ + $(mem_endianness) --create-lanes=$(mem_create_lanes) $(elf2dat_extra_args)' + +$(foreach i,0 1 2 3 4 5 6 7,%_lane$(i).dat): %.dat + @true + +$(HEX_FILES): %.hex: $(ELF) + $(post-process-info) + @$(MKDIR) $(@D) + bash -c '$(ELF2HEX) $< $(mem_start_address) $(mem_end_address) --width=$(mem_width) \ + $(mem_endianness) --create-lanes=$(mem_create_lanes) $(elf2hex_extra_args) $@' + +$(SYM_FILES): %.sym: $(ELF) + $(post-process-info) + @$(MKDIR) $(@D) + $(NM) -n $< > $@ + +$(FLASH_FILES): %.flash: $(ELF) + $(post-process-info) + @$(MKDIR) $(@D) + bash -c '$(ELF2FLASH) --input=$< --outfile=$@ --sim_optimize=$(SIM_OPTIMIZE) $(mem_endianness) \ + $(elf2flash_extra_args)' + +# +# Function generate_spd_entry +# Arg1: path to the memory initialization file +# Arg2: Type HEX or DAT +# Arg3: Output spd file to append +gen_spd_entry.BASE_FILE = $(basename $(notdir $1)) +gen_spd_entry.PARAM_NAME = $($(gen_spd_entry.BASE_FILE)_MEM_INIT_FILE_PARAM_NAME) +gen_spd_entry.MEM_PATH = $($(gen_spd_entry.BASE_FILE)_HIERARCHICAL_PATH) +gen_spd_entry.SETTINGS = $(strip \ + path=\"$1\" \ + type=\"$2\" \ + $(if $(gen_spd_entry.PARAM_NAME),initParamName=\"$(gen_spd_entry.PARAM_NAME)\") \ + $(if $(gen_spd_entry.MEM_PATH),memoryPath=\"$(gen_spd_entry.MEM_PATH)\") \ +) +define gen_spd_entry +$(ECHO) "" >> $3 +endef + +$(MEM_INIT_DESCRIPTOR_FILE).DAT_FILESET := $(patsubst $(dir $(MEM_INIT_DESCRIPTOR_FILE))%,%,$(DAT_FILES)) +$(MEM_INIT_DESCRIPTOR_FILE).HEX_FILESET := $(patsubst $(dir $(MEM_INIT_DESCRIPTOR_FILE))%,%,$(HEX_FILES)) + +$(MEM_INIT_DESCRIPTOR_FILE): %.spd: $(MEM_INIT_FILE) + $(post-process-info) + @$(MKDIR) $(@D) + @$(RM) $@ + @$(ECHO) "" > $@ + @$(ECHO) "" >> $@ + @$(foreach dat_file,$($@.DAT_FILESET),$(call gen_spd_entry,$(dat_file),DAT,$@) &&)true + @$(foreach hex_file,$($@.HEX_FILESET),$(call gen_spd_entry,$(hex_file),HEX,$@) &&)true + @$(ECHO) "" >> $@ + +.DELETE_ON_ERROR: $(MEM_INIT_DESCRIPTOR_FILE) + +$(MEM_INIT_QIP_FILE): %.qip: $(MEM_INIT_FILE) + $(post-process-info) + @$(MKDIR) $(@D) + @$(RM) $@ + @$(ECHO) "set_global_assignment -name SEARCH_PATH $$::quartus(qip_path)" > $@ + +.DELETE_ON_ERROR: $(MEM_INIT_QIP_FILE) diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/memory.gdb b/MCandWifiTestDE0/Software/MCTest_bsp/memory.gdb new file mode 100644 index 00000000..b685f21f --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/memory.gdb @@ -0,0 +1,50 @@ +# memory.gdb - GDB memory region definitions +# +# Machine generated for CPU 'cpu' in SOPC Builder design 'system' +# SOPC Builder design path: C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system.sopcinfo +# +# Generated: Mon Mar 03 15:52:38 MST 2014 + +# DO NOT MODIFY THIS FILE +# +# Changing this file will have subtle consequences +# which will almost certainly lead to a nonfunctioning +# system. If you do modify this file, be aware that your +# changes will be overwritten and lost when this file +# is generated again. +# +# DO NOT MODIFY THIS FILE + +# License Agreement +# +# Copyright (c) 2008 +# Altera Corporation, San Jose, California, USA. +# All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +# DEALINGS IN THE SOFTWARE. +# +# This agreement shall be governed in all respects by the laws of the State +# of California and by the laws of the United States of America. + +# Define memory regions for each memory connected to the CPU. +# The cache attribute is specified which improves GDB performance +# by allowing GDB to cache memory contents on the host. + +# sdram +memory 0x1000000 0x2000000 cache diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_alarm_start.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_alarm_start.d new file mode 100644 index 00000000..4db38228 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_alarm_start.d @@ -0,0 +1,31 @@ +obj/HAL/src/alt_alarm_start.o: HAL/src/alt_alarm_start.c \ + HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \ + HAL/inc/priv/alt_alarm.h HAL/inc/alt_types.h HAL/inc/sys/alt_irq.h \ + HAL/inc/nios2.h system.h linker.h HAL/inc/priv/alt_legacy_irq.h \ + system.h HAL/inc/nios2.h HAL/inc/sys/alt_irq.h + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_alarm.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +system.h: + +linker.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/sys/alt_irq.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_alarm_start.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_alarm_start.o new file mode 100644 index 00000000..52430843 Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_alarm_start.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_busy_sleep.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_busy_sleep.d new file mode 100644 index 00000000..e93e80c4 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_busy_sleep.d @@ -0,0 +1,10 @@ +obj/HAL/src/alt_busy_sleep.o: HAL/src/alt_busy_sleep.c system.h linker.h \ + HAL/inc/alt_types.h HAL/inc/priv/alt_busy_sleep.h + +system.h: + +linker.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_busy_sleep.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_busy_sleep.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_busy_sleep.o new file mode 100644 index 00000000..3e6c0f66 Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_busy_sleep.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_close.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_close.d new file mode 100644 index 00000000..517b93c3 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_close.d @@ -0,0 +1,74 @@ +obj/HAL/src/alt_close.o: HAL/src/alt_close.c HAL/inc/sys/alt_errno.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_warning.h HAL/inc/priv/alt_file.h \ + HAL/inc/sys/alt_dev.h system.h linker.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h UCOSII/inc/os/alt_sem.h \ + UCOSII/inc/priv/alt_sem_ucosii.h HAL/inc/includes.h HAL/inc/os_cpu.h \ + HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/priv/alt_legacy_irq.h \ + system.h HAL/inc/nios2.h HAL/inc/sys/alt_irq.h UCOSII/inc/os_cfg.h \ + HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_alarm.h system.h UCOSII/inc/ucos_ii.h \ + UCOSII/inc/os_cfg.h HAL/inc/os_cpu.h HAL/inc/alt_types.h \ + HAL/inc/os/alt_syscall.h + +HAL/inc/sys/alt_errno.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_warning.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +UCOSII/inc/os/alt_sem.h: + +UCOSII/inc/priv/alt_sem_ucosii.h: + +HAL/inc/includes.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/sys/alt_irq.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +system.h: + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/os_cpu.h: + +HAL/inc/alt_types.h: + +HAL/inc/os/alt_syscall.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_close.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_close.o new file mode 100644 index 00000000..f0f62382 Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_close.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_dcache_flush.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_dcache_flush.d new file mode 100644 index 00000000..a0eaf8a1 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_dcache_flush.d @@ -0,0 +1,15 @@ +obj/HAL/src/alt_dcache_flush.o: HAL/src/alt_dcache_flush.c \ + HAL/inc/nios2.h system.h linker.h HAL/inc/alt_types.h \ + HAL/inc/sys/alt_cache.h HAL/inc/alt_types.h + +HAL/inc/nios2.h: + +system.h: + +linker.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_cache.h: + +HAL/inc/alt_types.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_dcache_flush.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_dcache_flush.o new file mode 100644 index 00000000..4ad16b4e Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_dcache_flush.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_dcache_flush_all.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_dcache_flush_all.d new file mode 100644 index 00000000..792c3e4a --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_dcache_flush_all.d @@ -0,0 +1,15 @@ +obj/HAL/src/alt_dcache_flush_all.o: HAL/src/alt_dcache_flush_all.c \ + HAL/inc/nios2.h system.h linker.h HAL/inc/alt_types.h \ + HAL/inc/sys/alt_cache.h HAL/inc/alt_types.h + +HAL/inc/nios2.h: + +system.h: + +linker.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_cache.h: + +HAL/inc/alt_types.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_dcache_flush_all.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_dcache_flush_all.o new file mode 100644 index 00000000..67d647eb Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_dcache_flush_all.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_dcache_flush_no_writeback.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_dcache_flush_no_writeback.d new file mode 100644 index 00000000..867c42ba --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_dcache_flush_no_writeback.d @@ -0,0 +1,16 @@ +obj/HAL/src/alt_dcache_flush_no_writeback.o: \ + HAL/src/alt_dcache_flush_no_writeback.c HAL/inc/nios2.h system.h \ + linker.h HAL/inc/alt_types.h HAL/inc/sys/alt_cache.h \ + HAL/inc/alt_types.h + +HAL/inc/nios2.h: + +system.h: + +linker.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_cache.h: + +HAL/inc/alt_types.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_dcache_flush_no_writeback.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_dcache_flush_no_writeback.o new file mode 100644 index 00000000..aebfd4c1 Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_dcache_flush_no_writeback.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_dev.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_dev.d new file mode 100644 index 00000000..5a738e17 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_dev.d @@ -0,0 +1,73 @@ +obj/HAL/src/alt_dev.o: HAL/src/alt_dev.c HAL/inc/sys/alt_dev.h system.h \ + linker.h HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/priv/alt_file.h HAL/inc/sys/alt_dev.h \ + UCOSII/inc/os/alt_sem.h UCOSII/inc/priv/alt_sem_ucosii.h \ + HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \ + HAL/inc/nios2.h HAL/inc/priv/alt_legacy_irq.h system.h HAL/inc/nios2.h \ + HAL/inc/sys/alt_irq.h UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h \ + HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h system.h \ + UCOSII/inc/ucos_ii.h UCOSII/inc/os_cfg.h HAL/inc/os_cpu.h \ + HAL/inc/alt_types.h HAL/inc/alt_types.h system.h + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +UCOSII/inc/os/alt_sem.h: + +UCOSII/inc/priv/alt_sem_ucosii.h: + +HAL/inc/includes.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/sys/alt_irq.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +system.h: + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/os_cpu.h: + +HAL/inc/alt_types.h: + +HAL/inc/alt_types.h: + +system.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_dev.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_dev.o new file mode 100644 index 00000000..9e467fe7 Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_dev.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_dev_llist_insert.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_dev_llist_insert.d new file mode 100644 index 00000000..344d0651 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_dev_llist_insert.d @@ -0,0 +1,13 @@ +obj/HAL/src/alt_dev_llist_insert.o: HAL/src/alt_dev_llist_insert.c \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/alt_types.h HAL/inc/sys/alt_errno.h + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_errno.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_dev_llist_insert.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_dev_llist_insert.o new file mode 100644 index 00000000..500ae1c3 Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_dev_llist_insert.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_dma_rxchan_open.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_dma_rxchan_open.d new file mode 100644 index 00000000..1942c7da --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_dma_rxchan_open.d @@ -0,0 +1,74 @@ +obj/HAL/src/alt_dma_rxchan_open.o: HAL/src/alt_dma_rxchan_open.c \ + HAL/inc/sys/alt_dma.h HAL/inc/sys/alt_dma_dev.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/alt_types.h HAL/inc/sys/alt_errno.h \ + HAL/inc/priv/alt_file.h HAL/inc/sys/alt_dev.h system.h linker.h \ + HAL/inc/sys/alt_llist.h UCOSII/inc/os/alt_sem.h \ + UCOSII/inc/priv/alt_sem_ucosii.h HAL/inc/includes.h HAL/inc/os_cpu.h \ + HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/priv/alt_legacy_irq.h \ + system.h HAL/inc/nios2.h HAL/inc/sys/alt_irq.h UCOSII/inc/os_cfg.h \ + HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_alarm.h system.h UCOSII/inc/ucos_ii.h \ + UCOSII/inc/os_cfg.h HAL/inc/os_cpu.h HAL/inc/alt_types.h + +HAL/inc/sys/alt_dma.h: + +HAL/inc/sys/alt_dma_dev.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_errno.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +UCOSII/inc/os/alt_sem.h: + +UCOSII/inc/priv/alt_sem_ucosii.h: + +HAL/inc/includes.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/sys/alt_irq.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +system.h: + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/os_cpu.h: + +HAL/inc/alt_types.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_dma_rxchan_open.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_dma_rxchan_open.o new file mode 100644 index 00000000..765b1f35 Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_dma_rxchan_open.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_dma_txchan_open.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_dma_txchan_open.d new file mode 100644 index 00000000..91e5e694 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_dma_txchan_open.d @@ -0,0 +1,74 @@ +obj/HAL/src/alt_dma_txchan_open.o: HAL/src/alt_dma_txchan_open.c \ + HAL/inc/sys/alt_dma.h HAL/inc/sys/alt_dma_dev.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/alt_types.h HAL/inc/sys/alt_errno.h \ + HAL/inc/priv/alt_file.h HAL/inc/sys/alt_dev.h system.h linker.h \ + HAL/inc/sys/alt_llist.h UCOSII/inc/os/alt_sem.h \ + UCOSII/inc/priv/alt_sem_ucosii.h HAL/inc/includes.h HAL/inc/os_cpu.h \ + HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/priv/alt_legacy_irq.h \ + system.h HAL/inc/nios2.h HAL/inc/sys/alt_irq.h UCOSII/inc/os_cfg.h \ + HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_alarm.h system.h UCOSII/inc/ucos_ii.h \ + UCOSII/inc/os_cfg.h HAL/inc/os_cpu.h HAL/inc/alt_types.h + +HAL/inc/sys/alt_dma.h: + +HAL/inc/sys/alt_dma_dev.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_errno.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +UCOSII/inc/os/alt_sem.h: + +UCOSII/inc/priv/alt_sem_ucosii.h: + +HAL/inc/includes.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/sys/alt_irq.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +system.h: + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/os_cpu.h: + +HAL/inc/alt_types.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_dma_txchan_open.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_dma_txchan_open.o new file mode 100644 index 00000000..f860a758 Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_dma_txchan_open.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_do_ctors.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_do_ctors.d new file mode 100644 index 00000000..daf8bafc --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_do_ctors.d @@ -0,0 +1 @@ +obj/HAL/src/alt_do_ctors.o: HAL/src/alt_do_ctors.c diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_do_ctors.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_do_ctors.o new file mode 100644 index 00000000..8c8382ad Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_do_ctors.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_do_dtors.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_do_dtors.d new file mode 100644 index 00000000..c3471ebe --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_do_dtors.d @@ -0,0 +1 @@ +obj/HAL/src/alt_do_dtors.o: HAL/src/alt_do_dtors.c diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_do_dtors.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_do_dtors.o new file mode 100644 index 00000000..408bae1c Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_do_dtors.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_environ.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_environ.d new file mode 100644 index 00000000..e9ca295b --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_environ.d @@ -0,0 +1,3 @@ +obj/HAL/src/alt_environ.o: HAL/src/alt_environ.c HAL/inc/os/alt_syscall.h + +HAL/inc/os/alt_syscall.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_environ.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_environ.o new file mode 100644 index 00000000..f4c0a55f Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_environ.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_errno.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_errno.d new file mode 100644 index 00000000..29ca5443 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_errno.d @@ -0,0 +1,8 @@ +obj/HAL/src/alt_errno.o: HAL/src/alt_errno.c HAL/inc/sys/alt_errno.h \ + HAL/inc/alt_types.h HAL/inc/alt_types.h + +HAL/inc/sys/alt_errno.h: + +HAL/inc/alt_types.h: + +HAL/inc/alt_types.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_errno.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_errno.o new file mode 100644 index 00000000..a4bb6add Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_errno.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_exception_entry.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_exception_entry.d new file mode 100644 index 00000000..540567e6 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_exception_entry.d @@ -0,0 +1,6 @@ +obj/HAL/src/alt_exception_entry.o: HAL/src/alt_exception_entry.S system.h \ + linker.h + +system.h: + +linker.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_exception_entry.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_exception_entry.o new file mode 100644 index 00000000..f3febed4 Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_exception_entry.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_exception_muldiv.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_exception_muldiv.d new file mode 100644 index 00000000..63d66a74 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_exception_muldiv.d @@ -0,0 +1 @@ +obj/HAL/src/alt_exception_muldiv.o: HAL/src/alt_exception_muldiv.S diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_exception_muldiv.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_exception_muldiv.o new file mode 100644 index 00000000..1054a514 Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_exception_muldiv.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_exception_trap.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_exception_trap.d new file mode 100644 index 00000000..6e184888 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_exception_trap.d @@ -0,0 +1 @@ +obj/HAL/src/alt_exception_trap.o: HAL/src/alt_exception_trap.S diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_exception_trap.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_exception_trap.o new file mode 100644 index 00000000..29817c56 Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_exception_trap.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_execve.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_execve.d new file mode 100644 index 00000000..9cef7d20 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_execve.d @@ -0,0 +1,10 @@ +obj/HAL/src/alt_execve.o: HAL/src/alt_execve.c HAL/inc/sys/alt_errno.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_warning.h HAL/inc/os/alt_syscall.h + +HAL/inc/sys/alt_errno.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_warning.h: + +HAL/inc/os/alt_syscall.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_execve.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_execve.o new file mode 100644 index 00000000..4e4c5a5b Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_execve.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_exit.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_exit.d new file mode 100644 index 00000000..bab1db93 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_exit.d @@ -0,0 +1,64 @@ +obj/HAL/src/alt_exit.o: HAL/src/alt_exit.c HAL/inc/sys/alt_irq.h \ + HAL/inc/nios2.h HAL/inc/alt_types.h system.h linker.h \ + HAL/inc/priv/alt_legacy_irq.h system.h HAL/inc/nios2.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_irq.h HAL/inc/sys/alt_sim.h \ + UCOSII/inc/os/alt_hooks.h HAL/inc/includes.h HAL/inc/os_cpu.h \ + HAL/inc/sys/alt_irq.h UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h \ + HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h system.h \ + UCOSII/inc/ucos_ii.h UCOSII/inc/os_cfg.h HAL/inc/os_cpu.h \ + HAL/inc/os/alt_syscall.h HAL/inc/alt_types.h \ + HAL/inc/sys/alt_log_printf.h system.h + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/sys/alt_sim.h: + +UCOSII/inc/os/alt_hooks.h: + +HAL/inc/includes.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +system.h: + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/os_cpu.h: + +HAL/inc/os/alt_syscall.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_log_printf.h: + +system.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_exit.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_exit.o new file mode 100644 index 00000000..32313e95 Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_exit.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_fcntl.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_fcntl.d new file mode 100644 index 00000000..aa2a44d8 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_fcntl.d @@ -0,0 +1,73 @@ +obj/HAL/src/alt_fcntl.o: HAL/src/alt_fcntl.c HAL/inc/sys/alt_errno.h \ + HAL/inc/alt_types.h HAL/inc/priv/alt_file.h HAL/inc/sys/alt_dev.h \ + system.h linker.h HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_dev_llist.h \ + HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h UCOSII/inc/os/alt_sem.h \ + UCOSII/inc/priv/alt_sem_ucosii.h HAL/inc/includes.h HAL/inc/os_cpu.h \ + HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/priv/alt_legacy_irq.h \ + system.h HAL/inc/nios2.h HAL/inc/sys/alt_irq.h UCOSII/inc/os_cfg.h \ + HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_alarm.h system.h UCOSII/inc/ucos_ii.h \ + UCOSII/inc/os_cfg.h HAL/inc/os_cpu.h HAL/inc/alt_types.h \ + HAL/inc/alt_types.h HAL/inc/os/alt_syscall.h + +HAL/inc/sys/alt_errno.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +UCOSII/inc/os/alt_sem.h: + +UCOSII/inc/priv/alt_sem_ucosii.h: + +HAL/inc/includes.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/sys/alt_irq.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +system.h: + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/os_cpu.h: + +HAL/inc/alt_types.h: + +HAL/inc/alt_types.h: + +HAL/inc/os/alt_syscall.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_fcntl.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_fcntl.o new file mode 100644 index 00000000..6b2f54a2 Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_fcntl.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_fd_lock.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_fd_lock.d new file mode 100644 index 00000000..249754ea --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_fd_lock.d @@ -0,0 +1,66 @@ +obj/HAL/src/alt_fd_lock.o: HAL/src/alt_fd_lock.c HAL/inc/priv/alt_file.h \ + HAL/inc/sys/alt_dev.h system.h linker.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/priv/alt_dev_llist.h \ + HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h UCOSII/inc/os/alt_sem.h \ + UCOSII/inc/priv/alt_sem_ucosii.h HAL/inc/includes.h HAL/inc/os_cpu.h \ + HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/priv/alt_legacy_irq.h \ + system.h HAL/inc/nios2.h HAL/inc/sys/alt_irq.h UCOSII/inc/os_cfg.h \ + HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_alarm.h system.h UCOSII/inc/ucos_ii.h \ + UCOSII/inc/os_cfg.h HAL/inc/os_cpu.h HAL/inc/alt_types.h + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +UCOSII/inc/os/alt_sem.h: + +UCOSII/inc/priv/alt_sem_ucosii.h: + +HAL/inc/includes.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/sys/alt_irq.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +system.h: + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/os_cpu.h: + +HAL/inc/alt_types.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_fd_lock.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_fd_lock.o new file mode 100644 index 00000000..290532d8 Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_fd_lock.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_fd_unlock.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_fd_unlock.d new file mode 100644 index 00000000..fc9666c7 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_fd_unlock.d @@ -0,0 +1,67 @@ +obj/HAL/src/alt_fd_unlock.o: HAL/src/alt_fd_unlock.c \ + HAL/inc/priv/alt_file.h HAL/inc/sys/alt_dev.h system.h linker.h \ + HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h UCOSII/inc/os/alt_sem.h \ + UCOSII/inc/priv/alt_sem_ucosii.h HAL/inc/includes.h HAL/inc/os_cpu.h \ + HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/priv/alt_legacy_irq.h \ + system.h HAL/inc/nios2.h HAL/inc/sys/alt_irq.h UCOSII/inc/os_cfg.h \ + HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_alarm.h system.h UCOSII/inc/ucos_ii.h \ + UCOSII/inc/os_cfg.h HAL/inc/os_cpu.h HAL/inc/alt_types.h + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +UCOSII/inc/os/alt_sem.h: + +UCOSII/inc/priv/alt_sem_ucosii.h: + +HAL/inc/includes.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/sys/alt_irq.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +system.h: + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/os_cpu.h: + +HAL/inc/alt_types.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_fd_unlock.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_fd_unlock.o new file mode 100644 index 00000000..04d1e3a5 Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_fd_unlock.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_find_dev.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_find_dev.d new file mode 100644 index 00000000..5971c9fe --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_find_dev.d @@ -0,0 +1,71 @@ +obj/HAL/src/alt_find_dev.o: HAL/src/alt_find_dev.c HAL/inc/sys/alt_dev.h \ + system.h linker.h HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/priv/alt_file.h HAL/inc/sys/alt_dev.h \ + UCOSII/inc/os/alt_sem.h UCOSII/inc/priv/alt_sem_ucosii.h \ + HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \ + HAL/inc/nios2.h HAL/inc/priv/alt_legacy_irq.h system.h HAL/inc/nios2.h \ + HAL/inc/sys/alt_irq.h UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h \ + HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h system.h \ + UCOSII/inc/ucos_ii.h UCOSII/inc/os_cfg.h HAL/inc/os_cpu.h \ + HAL/inc/alt_types.h HAL/inc/alt_types.h + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +UCOSII/inc/os/alt_sem.h: + +UCOSII/inc/priv/alt_sem_ucosii.h: + +HAL/inc/includes.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/sys/alt_irq.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +system.h: + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/os_cpu.h: + +HAL/inc/alt_types.h: + +HAL/inc/alt_types.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_find_dev.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_find_dev.o new file mode 100644 index 00000000..7886a26b Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_find_dev.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_find_file.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_find_file.d new file mode 100644 index 00000000..1b93849b --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_find_file.d @@ -0,0 +1,72 @@ +obj/HAL/src/alt_find_file.o: HAL/src/alt_find_file.c \ + HAL/inc/sys/alt_dev.h system.h linker.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/priv/alt_dev_llist.h \ + HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h HAL/inc/priv/alt_file.h \ + HAL/inc/sys/alt_dev.h UCOSII/inc/os/alt_sem.h \ + UCOSII/inc/priv/alt_sem_ucosii.h HAL/inc/includes.h HAL/inc/os_cpu.h \ + HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/priv/alt_legacy_irq.h \ + system.h HAL/inc/nios2.h HAL/inc/sys/alt_irq.h UCOSII/inc/os_cfg.h \ + HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_alarm.h system.h UCOSII/inc/ucos_ii.h \ + UCOSII/inc/os_cfg.h HAL/inc/os_cpu.h HAL/inc/alt_types.h \ + HAL/inc/alt_types.h + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +UCOSII/inc/os/alt_sem.h: + +UCOSII/inc/priv/alt_sem_ucosii.h: + +HAL/inc/includes.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/sys/alt_irq.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +system.h: + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/os_cpu.h: + +HAL/inc/alt_types.h: + +HAL/inc/alt_types.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_find_file.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_find_file.o new file mode 100644 index 00000000..344faa8a Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_find_file.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_flash_dev.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_flash_dev.d new file mode 100644 index 00000000..4592b116 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_flash_dev.d @@ -0,0 +1,74 @@ +obj/HAL/src/alt_flash_dev.o: HAL/src/alt_flash_dev.c \ + HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h HAL/inc/sys/alt_flash_dev.h \ + HAL/inc/sys/alt_flash_types.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/priv/alt_file.h HAL/inc/sys/alt_dev.h \ + system.h linker.h UCOSII/inc/os/alt_sem.h \ + UCOSII/inc/priv/alt_sem_ucosii.h HAL/inc/includes.h HAL/inc/os_cpu.h \ + HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/priv/alt_legacy_irq.h \ + system.h HAL/inc/nios2.h HAL/inc/sys/alt_irq.h UCOSII/inc/os_cfg.h \ + HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_alarm.h system.h UCOSII/inc/ucos_ii.h \ + UCOSII/inc/os_cfg.h HAL/inc/os_cpu.h HAL/inc/alt_types.h + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_flash_dev.h: + +HAL/inc/sys/alt_flash_types.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +UCOSII/inc/os/alt_sem.h: + +UCOSII/inc/priv/alt_sem_ucosii.h: + +HAL/inc/includes.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/sys/alt_irq.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +system.h: + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/os_cpu.h: + +HAL/inc/alt_types.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_flash_dev.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_flash_dev.o new file mode 100644 index 00000000..df3a78c9 Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_flash_dev.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_fork.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_fork.d new file mode 100644 index 00000000..492be651 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_fork.d @@ -0,0 +1,10 @@ +obj/HAL/src/alt_fork.o: HAL/src/alt_fork.c HAL/inc/sys/alt_warning.h \ + HAL/inc/sys/alt_errno.h HAL/inc/alt_types.h HAL/inc/os/alt_syscall.h + +HAL/inc/sys/alt_warning.h: + +HAL/inc/sys/alt_errno.h: + +HAL/inc/alt_types.h: + +HAL/inc/os/alt_syscall.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_fork.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_fork.o new file mode 100644 index 00000000..12538b05 Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_fork.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_fs_reg.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_fs_reg.d new file mode 100644 index 00000000..d5ccf1ad --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_fs_reg.d @@ -0,0 +1,69 @@ +obj/HAL/src/alt_fs_reg.o: HAL/src/alt_fs_reg.c HAL/inc/sys/alt_dev.h \ + system.h linker.h HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/priv/alt_file.h HAL/inc/sys/alt_dev.h \ + UCOSII/inc/os/alt_sem.h UCOSII/inc/priv/alt_sem_ucosii.h \ + HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \ + HAL/inc/nios2.h HAL/inc/priv/alt_legacy_irq.h system.h HAL/inc/nios2.h \ + HAL/inc/sys/alt_irq.h UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h \ + HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h system.h \ + UCOSII/inc/ucos_ii.h UCOSII/inc/os_cfg.h HAL/inc/os_cpu.h \ + HAL/inc/alt_types.h + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +UCOSII/inc/os/alt_sem.h: + +UCOSII/inc/priv/alt_sem_ucosii.h: + +HAL/inc/includes.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/sys/alt_irq.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +system.h: + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/os_cpu.h: + +HAL/inc/alt_types.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_fs_reg.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_fs_reg.o new file mode 100644 index 00000000..684315a3 Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_fs_reg.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_fstat.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_fstat.d new file mode 100644 index 00000000..5385b6e1 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_fstat.d @@ -0,0 +1,76 @@ +obj/HAL/src/alt_fstat.o: HAL/src/alt_fstat.c HAL/inc/sys/alt_dev.h \ + system.h linker.h HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_warning.h HAL/inc/sys/alt_errno.h \ + HAL/inc/priv/alt_file.h HAL/inc/sys/alt_dev.h UCOSII/inc/os/alt_sem.h \ + UCOSII/inc/priv/alt_sem_ucosii.h HAL/inc/includes.h HAL/inc/os_cpu.h \ + HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/priv/alt_legacy_irq.h \ + system.h HAL/inc/nios2.h HAL/inc/sys/alt_irq.h UCOSII/inc/os_cfg.h \ + HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_alarm.h system.h UCOSII/inc/ucos_ii.h \ + UCOSII/inc/os_cfg.h HAL/inc/os_cpu.h HAL/inc/alt_types.h \ + HAL/inc/os/alt_syscall.h + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_warning.h: + +HAL/inc/sys/alt_errno.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +UCOSII/inc/os/alt_sem.h: + +UCOSII/inc/priv/alt_sem_ucosii.h: + +HAL/inc/includes.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/sys/alt_irq.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +system.h: + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/os_cpu.h: + +HAL/inc/alt_types.h: + +HAL/inc/os/alt_syscall.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_fstat.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_fstat.o new file mode 100644 index 00000000..4be1a6b7 Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_fstat.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_get_fd.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_get_fd.d new file mode 100644 index 00000000..d579fd48 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_get_fd.d @@ -0,0 +1,73 @@ +obj/HAL/src/alt_get_fd.o: HAL/src/alt_get_fd.c HAL/inc/sys/alt_dev.h \ + system.h linker.h HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/priv/alt_file.h HAL/inc/sys/alt_dev.h \ + UCOSII/inc/os/alt_sem.h UCOSII/inc/priv/alt_sem_ucosii.h \ + HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \ + HAL/inc/nios2.h HAL/inc/priv/alt_legacy_irq.h system.h HAL/inc/nios2.h \ + HAL/inc/sys/alt_irq.h UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h \ + HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h system.h \ + UCOSII/inc/ucos_ii.h UCOSII/inc/os_cfg.h HAL/inc/os_cpu.h \ + HAL/inc/alt_types.h HAL/inc/alt_types.h system.h + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +UCOSII/inc/os/alt_sem.h: + +UCOSII/inc/priv/alt_sem_ucosii.h: + +HAL/inc/includes.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/sys/alt_irq.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +system.h: + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/os_cpu.h: + +HAL/inc/alt_types.h: + +HAL/inc/alt_types.h: + +system.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_get_fd.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_get_fd.o new file mode 100644 index 00000000..6814e93d Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_get_fd.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_getchar.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_getchar.d new file mode 100644 index 00000000..2a468def --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_getchar.d @@ -0,0 +1 @@ +obj/HAL/src/alt_getchar.o: HAL/src/alt_getchar.c diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_getchar.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_getchar.o new file mode 100644 index 00000000..f4a93d6d Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_getchar.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_getpid.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_getpid.d new file mode 100644 index 00000000..d9499b94 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_getpid.d @@ -0,0 +1,3 @@ +obj/HAL/src/alt_getpid.o: HAL/src/alt_getpid.c HAL/inc/os/alt_syscall.h + +HAL/inc/os/alt_syscall.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_getpid.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_getpid.o new file mode 100644 index 00000000..520ee989 Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_getpid.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_gettod.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_gettod.d new file mode 100644 index 00000000..cf3cf343 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_gettod.d @@ -0,0 +1,17 @@ +obj/HAL/src/alt_gettod.o: HAL/src/alt_gettod.c HAL/inc/sys/alt_alarm.h \ + HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h HAL/inc/priv/alt_alarm.h \ + HAL/inc/alt_types.h HAL/inc/alt_types.h HAL/inc/os/alt_syscall.h + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_alarm.h: + +HAL/inc/alt_types.h: + +HAL/inc/alt_types.h: + +HAL/inc/os/alt_syscall.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_gettod.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_gettod.o new file mode 100644 index 00000000..9f3b0d84 Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_gettod.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_gmon.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_gmon.d new file mode 100644 index 00000000..2ec2b57d --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_gmon.d @@ -0,0 +1,33 @@ +obj/HAL/src/alt_gmon.o: HAL/src/alt_gmon.c HAL/inc/priv/nios2_gmon_data.h \ + HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/alt_types.h system.h \ + linker.h HAL/inc/priv/alt_legacy_irq.h system.h HAL/inc/nios2.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_irq.h HAL/inc/sys/alt_alarm.h \ + HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h + +HAL/inc/priv/nios2_gmon_data.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_gmon.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_gmon.o new file mode 100644 index 00000000..5e31c2c3 Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_gmon.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_icache_flush.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_icache_flush.d new file mode 100644 index 00000000..2e4ddd18 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_icache_flush.d @@ -0,0 +1,15 @@ +obj/HAL/src/alt_icache_flush.o: HAL/src/alt_icache_flush.c \ + HAL/inc/nios2.h system.h linker.h HAL/inc/alt_types.h \ + HAL/inc/sys/alt_cache.h HAL/inc/alt_types.h + +HAL/inc/nios2.h: + +system.h: + +linker.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_cache.h: + +HAL/inc/alt_types.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_icache_flush.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_icache_flush.o new file mode 100644 index 00000000..e81adc0a Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_icache_flush.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_icache_flush_all.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_icache_flush_all.d new file mode 100644 index 00000000..47cfbf38 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_icache_flush_all.d @@ -0,0 +1,15 @@ +obj/HAL/src/alt_icache_flush_all.o: HAL/src/alt_icache_flush_all.c \ + HAL/inc/nios2.h system.h linker.h HAL/inc/alt_types.h \ + HAL/inc/sys/alt_cache.h HAL/inc/alt_types.h + +HAL/inc/nios2.h: + +system.h: + +linker.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_cache.h: + +HAL/inc/alt_types.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_icache_flush_all.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_icache_flush_all.o new file mode 100644 index 00000000..6cb7f5c9 Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_icache_flush_all.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_iic.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_iic.d new file mode 100644 index 00000000..572d1fc3 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_iic.d @@ -0,0 +1,5 @@ +obj/HAL/src/alt_iic.o: HAL/src/alt_iic.c system.h linker.h + +system.h: + +linker.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_iic.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_iic.o new file mode 100644 index 00000000..f85a36c8 Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_iic.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_iic_isr_register.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_iic_isr_register.d new file mode 100644 index 00000000..f54a6859 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_iic_isr_register.d @@ -0,0 +1,6 @@ +obj/HAL/src/alt_iic_isr_register.o: HAL/src/alt_iic_isr_register.c \ + system.h linker.h + +system.h: + +linker.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_iic_isr_register.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_iic_isr_register.o new file mode 100644 index 00000000..d22d465f Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_iic_isr_register.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_instruction_exception_entry.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_instruction_exception_entry.d new file mode 100644 index 00000000..6d0705f5 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_instruction_exception_entry.d @@ -0,0 +1,18 @@ +obj/HAL/src/alt_instruction_exception_entry.o: \ + HAL/src/alt_instruction_exception_entry.c HAL/inc/sys/alt_exceptions.h \ + HAL/inc/alt_types.h system.h linker.h HAL/inc/nios2.h \ + HAL/inc/alt_types.h system.h + +HAL/inc/sys/alt_exceptions.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +system.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_instruction_exception_entry.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_instruction_exception_entry.o new file mode 100644 index 00000000..93653490 Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_instruction_exception_entry.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_instruction_exception_register.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_instruction_exception_register.d new file mode 100644 index 00000000..d4fac042 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_instruction_exception_register.d @@ -0,0 +1,16 @@ +obj/HAL/src/alt_instruction_exception_register.o: \ + HAL/src/alt_instruction_exception_register.c \ + HAL/inc/sys/alt_exceptions.h HAL/inc/alt_types.h system.h linker.h \ + HAL/inc/alt_types.h system.h + +HAL/inc/sys/alt_exceptions.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: + +HAL/inc/alt_types.h: + +system.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_instruction_exception_register.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_instruction_exception_register.o new file mode 100644 index 00000000..0ad955be Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_instruction_exception_register.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_io_redirect.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_io_redirect.d new file mode 100644 index 00000000..d851a0e5 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_io_redirect.d @@ -0,0 +1,69 @@ +obj/HAL/src/alt_io_redirect.o: HAL/src/alt_io_redirect.c \ + HAL/inc/sys/alt_dev.h system.h linker.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/priv/alt_dev_llist.h \ + HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h HAL/inc/priv/alt_file.h \ + HAL/inc/sys/alt_dev.h UCOSII/inc/os/alt_sem.h \ + UCOSII/inc/priv/alt_sem_ucosii.h HAL/inc/includes.h HAL/inc/os_cpu.h \ + HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/priv/alt_legacy_irq.h \ + system.h HAL/inc/nios2.h HAL/inc/sys/alt_irq.h UCOSII/inc/os_cfg.h \ + HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_alarm.h system.h UCOSII/inc/ucos_ii.h \ + UCOSII/inc/os_cfg.h HAL/inc/os_cpu.h HAL/inc/alt_types.h + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +UCOSII/inc/os/alt_sem.h: + +UCOSII/inc/priv/alt_sem_ucosii.h: + +HAL/inc/includes.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/sys/alt_irq.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +system.h: + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/os_cpu.h: + +HAL/inc/alt_types.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_io_redirect.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_io_redirect.o new file mode 100644 index 00000000..1c80d984 Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_io_redirect.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_ioctl.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_ioctl.d new file mode 100644 index 00000000..39ac3db6 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_ioctl.d @@ -0,0 +1,76 @@ +obj/HAL/src/alt_ioctl.o: HAL/src/alt_ioctl.c HAL/inc/sys/ioctl.h \ + HAL/inc/sys/alt_errno.h HAL/inc/alt_types.h HAL/inc/sys/alt_warning.h \ + HAL/inc/priv/alt_file.h HAL/inc/sys/alt_dev.h system.h linker.h \ + HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_dev_llist.h \ + HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h UCOSII/inc/os/alt_sem.h \ + UCOSII/inc/priv/alt_sem_ucosii.h HAL/inc/includes.h HAL/inc/os_cpu.h \ + HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/priv/alt_legacy_irq.h \ + system.h HAL/inc/nios2.h HAL/inc/sys/alt_irq.h UCOSII/inc/os_cfg.h \ + HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_alarm.h system.h UCOSII/inc/ucos_ii.h \ + UCOSII/inc/os_cfg.h HAL/inc/os_cpu.h HAL/inc/alt_types.h \ + HAL/inc/os/alt_syscall.h + +HAL/inc/sys/ioctl.h: + +HAL/inc/sys/alt_errno.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_warning.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +UCOSII/inc/os/alt_sem.h: + +UCOSII/inc/priv/alt_sem_ucosii.h: + +HAL/inc/includes.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/sys/alt_irq.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +system.h: + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/os_cpu.h: + +HAL/inc/alt_types.h: + +HAL/inc/os/alt_syscall.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_ioctl.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_ioctl.o new file mode 100644 index 00000000..4e006ead Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_ioctl.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_irq_entry.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_irq_entry.d new file mode 100644 index 00000000..9ec37513 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_irq_entry.d @@ -0,0 +1,5 @@ +obj/HAL/src/alt_irq_entry.o: HAL/src/alt_irq_entry.S system.h linker.h + +system.h: + +linker.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_irq_entry.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_irq_entry.o new file mode 100644 index 00000000..a29788a2 Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_irq_entry.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_irq_handler.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_irq_handler.d new file mode 100644 index 00000000..8ebea6c3 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_irq_handler.d @@ -0,0 +1,56 @@ +obj/HAL/src/alt_irq_handler.o: HAL/src/alt_irq_handler.c system.h \ + linker.h HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/alt_types.h \ + system.h HAL/inc/priv/alt_legacy_irq.h system.h HAL/inc/nios2.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_irq.h UCOSII/inc/os/alt_hooks.h \ + HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \ + UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_alarm.h system.h UCOSII/inc/ucos_ii.h \ + UCOSII/inc/os_cfg.h HAL/inc/os_cpu.h HAL/inc/alt_types.h + +system.h: + +linker.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +system.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_irq.h: + +UCOSII/inc/os/alt_hooks.h: + +HAL/inc/includes.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +system.h: + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/os_cpu.h: + +HAL/inc/alt_types.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_irq_handler.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_irq_handler.o new file mode 100644 index 00000000..a260c025 Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_irq_handler.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_irq_register.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_irq_register.d new file mode 100644 index 00000000..607377ae --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_irq_register.d @@ -0,0 +1,64 @@ +obj/HAL/src/alt_irq_register.o: HAL/src/alt_irq_register.c system.h \ + linker.h HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/alt_types.h \ + system.h HAL/inc/priv/alt_legacy_irq.h system.h HAL/inc/nios2.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_irq.h HAL/inc/priv/alt_legacy_irq.h \ + UCOSII/inc/os/alt_hooks.h HAL/inc/includes.h HAL/inc/os_cpu.h \ + HAL/inc/sys/alt_irq.h UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h \ + HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h system.h \ + UCOSII/inc/ucos_ii.h UCOSII/inc/os_cfg.h HAL/inc/os_cpu.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_irq_entry.h \ + HAL/inc/priv/alt_irq_table.h + +system.h: + +linker.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +system.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/priv/alt_legacy_irq.h: + +UCOSII/inc/os/alt_hooks.h: + +HAL/inc/includes.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +system.h: + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/os_cpu.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_irq_entry.h: + +HAL/inc/priv/alt_irq_table.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_irq_register.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_irq_register.o new file mode 100644 index 00000000..addd4a6b Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_irq_register.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_irq_vars.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_irq_vars.d new file mode 100644 index 00000000..f316558a --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_irq_vars.d @@ -0,0 +1,8 @@ +obj/HAL/src/alt_irq_vars.o: HAL/src/alt_irq_vars.c HAL/inc/alt_types.h \ + system.h linker.h + +HAL/inc/alt_types.h: + +system.h: + +linker.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_irq_vars.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_irq_vars.o new file mode 100644 index 00000000..b04281c9 Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_irq_vars.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_isatty.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_isatty.d new file mode 100644 index 00000000..ead56fcc --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_isatty.d @@ -0,0 +1,76 @@ +obj/HAL/src/alt_isatty.o: HAL/src/alt_isatty.c HAL/inc/sys/alt_dev.h \ + system.h linker.h HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_errno.h HAL/inc/sys/alt_warning.h \ + HAL/inc/priv/alt_file.h HAL/inc/sys/alt_dev.h UCOSII/inc/os/alt_sem.h \ + UCOSII/inc/priv/alt_sem_ucosii.h HAL/inc/includes.h HAL/inc/os_cpu.h \ + HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/priv/alt_legacy_irq.h \ + system.h HAL/inc/nios2.h HAL/inc/sys/alt_irq.h UCOSII/inc/os_cfg.h \ + HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_alarm.h system.h UCOSII/inc/ucos_ii.h \ + UCOSII/inc/os_cfg.h HAL/inc/os_cpu.h HAL/inc/alt_types.h \ + HAL/inc/os/alt_syscall.h + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_errno.h: + +HAL/inc/sys/alt_warning.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +UCOSII/inc/os/alt_sem.h: + +UCOSII/inc/priv/alt_sem_ucosii.h: + +HAL/inc/includes.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/sys/alt_irq.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +system.h: + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/os_cpu.h: + +HAL/inc/alt_types.h: + +HAL/inc/os/alt_syscall.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_isatty.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_isatty.o new file mode 100644 index 00000000..e0051107 Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_isatty.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_kill.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_kill.d new file mode 100644 index 00000000..0c14ae80 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_kill.d @@ -0,0 +1,8 @@ +obj/HAL/src/alt_kill.o: HAL/src/alt_kill.c HAL/inc/sys/alt_errno.h \ + HAL/inc/alt_types.h HAL/inc/os/alt_syscall.h + +HAL/inc/sys/alt_errno.h: + +HAL/inc/alt_types.h: + +HAL/inc/os/alt_syscall.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_kill.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_kill.o new file mode 100644 index 00000000..3644ce69 Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_kill.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_link.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_link.d new file mode 100644 index 00000000..dc844c6a --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_link.d @@ -0,0 +1,10 @@ +obj/HAL/src/alt_link.o: HAL/src/alt_link.c HAL/inc/sys/alt_warning.h \ + HAL/inc/sys/alt_errno.h HAL/inc/alt_types.h HAL/inc/os/alt_syscall.h + +HAL/inc/sys/alt_warning.h: + +HAL/inc/sys/alt_errno.h: + +HAL/inc/alt_types.h: + +HAL/inc/os/alt_syscall.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_link.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_link.o new file mode 100644 index 00000000..3f068d00 Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_link.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_load.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_load.d new file mode 100644 index 00000000..d496ab8d --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_load.d @@ -0,0 +1,8 @@ +obj/HAL/src/alt_load.o: HAL/src/alt_load.c HAL/inc/sys/alt_load.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_cache.h + +HAL/inc/sys/alt_load.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_cache.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_load.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_load.o new file mode 100644 index 00000000..6446076c Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_load.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_log_macro.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_log_macro.d new file mode 100644 index 00000000..9768c1fa --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_log_macro.d @@ -0,0 +1 @@ +obj/HAL/src/alt_log_macro.o: HAL/src/alt_log_macro.S diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_log_macro.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_log_macro.o new file mode 100644 index 00000000..489e2cc3 Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_log_macro.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_log_printf.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_log_printf.d new file mode 100644 index 00000000..251ff6db --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_log_printf.d @@ -0,0 +1 @@ +obj/HAL/src/alt_log_printf.o: HAL/src/alt_log_printf.c diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_log_printf.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_log_printf.o new file mode 100644 index 00000000..7a0f38c2 Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_log_printf.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_lseek.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_lseek.d new file mode 100644 index 00000000..7edaff1d --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_lseek.d @@ -0,0 +1,74 @@ +obj/HAL/src/alt_lseek.o: HAL/src/alt_lseek.c HAL/inc/sys/alt_errno.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_warning.h HAL/inc/priv/alt_file.h \ + HAL/inc/sys/alt_dev.h system.h linker.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h UCOSII/inc/os/alt_sem.h \ + UCOSII/inc/priv/alt_sem_ucosii.h HAL/inc/includes.h HAL/inc/os_cpu.h \ + HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/priv/alt_legacy_irq.h \ + system.h HAL/inc/nios2.h HAL/inc/sys/alt_irq.h UCOSII/inc/os_cfg.h \ + HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_alarm.h system.h UCOSII/inc/ucos_ii.h \ + UCOSII/inc/os_cfg.h HAL/inc/os_cpu.h HAL/inc/alt_types.h \ + HAL/inc/os/alt_syscall.h + +HAL/inc/sys/alt_errno.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_warning.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +UCOSII/inc/os/alt_sem.h: + +UCOSII/inc/priv/alt_sem_ucosii.h: + +HAL/inc/includes.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/sys/alt_irq.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +system.h: + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/os_cpu.h: + +HAL/inc/alt_types.h: + +HAL/inc/os/alt_syscall.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_lseek.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_lseek.o new file mode 100644 index 00000000..38d9e421 Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_lseek.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_main.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_main.d new file mode 100644 index 00000000..f8c2cda4 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_main.d @@ -0,0 +1,87 @@ +obj/HAL/src/alt_main.o: HAL/src/alt_main.c HAL/inc/sys/alt_dev.h system.h \ + linker.h HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_sys_init.h HAL/inc/sys/alt_irq.h \ + HAL/inc/nios2.h HAL/inc/priv/alt_legacy_irq.h system.h HAL/inc/nios2.h \ + HAL/inc/sys/alt_irq.h UCOSII/inc/os/alt_hooks.h HAL/inc/includes.h \ + HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h UCOSII/inc/os_cfg.h \ + HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_alarm.h system.h UCOSII/inc/ucos_ii.h \ + UCOSII/inc/os_cfg.h HAL/inc/os_cpu.h HAL/inc/priv/alt_file.h \ + HAL/inc/sys/alt_dev.h UCOSII/inc/os/alt_sem.h \ + UCOSII/inc/priv/alt_sem_ucosii.h HAL/inc/includes.h HAL/inc/alt_types.h \ + HAL/inc/alt_types.h system.h HAL/inc/sys/alt_log_printf.h system.h + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_sys_init.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/sys/alt_irq.h: + +UCOSII/inc/os/alt_hooks.h: + +HAL/inc/includes.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +system.h: + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/os_cpu.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +UCOSII/inc/os/alt_sem.h: + +UCOSII/inc/priv/alt_sem_ucosii.h: + +HAL/inc/includes.h: + +HAL/inc/alt_types.h: + +HAL/inc/alt_types.h: + +system.h: + +HAL/inc/sys/alt_log_printf.h: + +system.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_main.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_main.o new file mode 100644 index 00000000..71bf5896 Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_main.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_mcount.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_mcount.d new file mode 100644 index 00000000..1203efcc --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_mcount.d @@ -0,0 +1 @@ +obj/HAL/src/alt_mcount.o: HAL/src/alt_mcount.S diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_mcount.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_mcount.o new file mode 100644 index 00000000..8a824390 Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_mcount.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_open.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_open.d new file mode 100644 index 00000000..2ff521af --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_open.d @@ -0,0 +1,76 @@ +obj/HAL/src/alt_open.o: HAL/src/alt_open.c HAL/inc/sys/alt_errno.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_warning.h HAL/inc/priv/alt_file.h \ + HAL/inc/sys/alt_dev.h system.h linker.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h UCOSII/inc/os/alt_sem.h \ + UCOSII/inc/priv/alt_sem_ucosii.h HAL/inc/includes.h HAL/inc/os_cpu.h \ + HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/priv/alt_legacy_irq.h \ + system.h HAL/inc/nios2.h HAL/inc/sys/alt_irq.h UCOSII/inc/os_cfg.h \ + HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_alarm.h system.h UCOSII/inc/ucos_ii.h \ + UCOSII/inc/os_cfg.h HAL/inc/os_cpu.h HAL/inc/alt_types.h \ + HAL/inc/alt_types.h HAL/inc/os/alt_syscall.h + +HAL/inc/sys/alt_errno.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_warning.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +UCOSII/inc/os/alt_sem.h: + +UCOSII/inc/priv/alt_sem_ucosii.h: + +HAL/inc/includes.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/sys/alt_irq.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +system.h: + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/os_cpu.h: + +HAL/inc/alt_types.h: + +HAL/inc/alt_types.h: + +HAL/inc/os/alt_syscall.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_open.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_open.o new file mode 100644 index 00000000..b8c86d91 Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_open.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_printf.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_printf.d new file mode 100644 index 00000000..3ce68a43 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_printf.d @@ -0,0 +1,3 @@ +obj/HAL/src/alt_printf.o: HAL/src/alt_printf.c HAL/inc/sys/alt_stdio.h + +HAL/inc/sys/alt_stdio.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_printf.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_printf.o new file mode 100644 index 00000000..54fa8bc8 Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_printf.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_putchar.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_putchar.d new file mode 100644 index 00000000..0f19fb81 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_putchar.d @@ -0,0 +1 @@ +obj/HAL/src/alt_putchar.o: HAL/src/alt_putchar.c diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_putchar.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_putchar.o new file mode 100644 index 00000000..b8d65e39 Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_putchar.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_putstr.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_putstr.d new file mode 100644 index 00000000..ed03fdc0 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_putstr.d @@ -0,0 +1 @@ +obj/HAL/src/alt_putstr.o: HAL/src/alt_putstr.c diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_putstr.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_putstr.o new file mode 100644 index 00000000..03903265 Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_putstr.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_read.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_read.d new file mode 100644 index 00000000..a06cf466 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_read.d @@ -0,0 +1,74 @@ +obj/HAL/src/alt_read.o: HAL/src/alt_read.c HAL/inc/sys/alt_errno.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_warning.h HAL/inc/priv/alt_file.h \ + HAL/inc/sys/alt_dev.h system.h linker.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h UCOSII/inc/os/alt_sem.h \ + UCOSII/inc/priv/alt_sem_ucosii.h HAL/inc/includes.h HAL/inc/os_cpu.h \ + HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/priv/alt_legacy_irq.h \ + system.h HAL/inc/nios2.h HAL/inc/sys/alt_irq.h UCOSII/inc/os_cfg.h \ + HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_alarm.h system.h UCOSII/inc/ucos_ii.h \ + UCOSII/inc/os_cfg.h HAL/inc/os_cpu.h HAL/inc/alt_types.h \ + HAL/inc/os/alt_syscall.h + +HAL/inc/sys/alt_errno.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_warning.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +UCOSII/inc/os/alt_sem.h: + +UCOSII/inc/priv/alt_sem_ucosii.h: + +HAL/inc/includes.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/sys/alt_irq.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +system.h: + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/os_cpu.h: + +HAL/inc/alt_types.h: + +HAL/inc/os/alt_syscall.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_read.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_read.o new file mode 100644 index 00000000..f51939fe Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_read.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_release_fd.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_release_fd.d new file mode 100644 index 00000000..adb3c578 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_release_fd.d @@ -0,0 +1,69 @@ +obj/HAL/src/alt_release_fd.o: HAL/src/alt_release_fd.c \ + HAL/inc/sys/alt_dev.h system.h linker.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/priv/alt_dev_llist.h \ + HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h HAL/inc/priv/alt_file.h \ + HAL/inc/sys/alt_dev.h UCOSII/inc/os/alt_sem.h \ + UCOSII/inc/priv/alt_sem_ucosii.h HAL/inc/includes.h HAL/inc/os_cpu.h \ + HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/priv/alt_legacy_irq.h \ + system.h HAL/inc/nios2.h HAL/inc/sys/alt_irq.h UCOSII/inc/os_cfg.h \ + HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_alarm.h system.h UCOSII/inc/ucos_ii.h \ + UCOSII/inc/os_cfg.h HAL/inc/os_cpu.h HAL/inc/alt_types.h + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +UCOSII/inc/os/alt_sem.h: + +UCOSII/inc/priv/alt_sem_ucosii.h: + +HAL/inc/includes.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/sys/alt_irq.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +system.h: + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/os_cpu.h: + +HAL/inc/alt_types.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_release_fd.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_release_fd.o new file mode 100644 index 00000000..402edc0f Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_release_fd.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_remap_cached.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_remap_cached.d new file mode 100644 index 00000000..b5fb1513 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_remap_cached.d @@ -0,0 +1,10 @@ +obj/HAL/src/alt_remap_cached.o: HAL/src/alt_remap_cached.c \ + HAL/inc/sys/alt_cache.h HAL/inc/alt_types.h system.h linker.h + +HAL/inc/sys/alt_cache.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_remap_cached.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_remap_cached.o new file mode 100644 index 00000000..b3494abb Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_remap_cached.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_remap_uncached.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_remap_uncached.d new file mode 100644 index 00000000..04234057 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_remap_uncached.d @@ -0,0 +1,10 @@ +obj/HAL/src/alt_remap_uncached.o: HAL/src/alt_remap_uncached.c \ + HAL/inc/sys/alt_cache.h HAL/inc/alt_types.h system.h linker.h + +HAL/inc/sys/alt_cache.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_remap_uncached.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_remap_uncached.o new file mode 100644 index 00000000..33a3c610 Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_remap_uncached.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_rename.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_rename.d new file mode 100644 index 00000000..b7af4b26 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_rename.d @@ -0,0 +1,10 @@ +obj/HAL/src/alt_rename.o: HAL/src/alt_rename.c HAL/inc/sys/alt_errno.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_warning.h HAL/inc/os/alt_syscall.h + +HAL/inc/sys/alt_errno.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_warning.h: + +HAL/inc/os/alt_syscall.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_rename.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_rename.o new file mode 100644 index 00000000..fa679923 Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_rename.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_sbrk.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_sbrk.d new file mode 100644 index 00000000..23a1342d --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_sbrk.d @@ -0,0 +1,31 @@ +obj/HAL/src/alt_sbrk.o: HAL/src/alt_sbrk.c HAL/inc/os/alt_syscall.h \ + HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/alt_types.h system.h \ + linker.h HAL/inc/priv/alt_legacy_irq.h system.h HAL/inc/nios2.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_irq.h HAL/inc/sys/alt_stack.h \ + system.h + +HAL/inc/os/alt_syscall.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/sys/alt_stack.h: + +system.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_sbrk.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_sbrk.o new file mode 100644 index 00000000..e0683acb Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_sbrk.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_settod.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_settod.d new file mode 100644 index 00000000..56718d55 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_settod.d @@ -0,0 +1,17 @@ +obj/HAL/src/alt_settod.o: HAL/src/alt_settod.c HAL/inc/sys/alt_errno.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_alarm.h HAL/inc/alt_types.h HAL/inc/os/alt_syscall.h + +HAL/inc/sys/alt_errno.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +HAL/inc/alt_types.h: + +HAL/inc/os/alt_syscall.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_settod.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_settod.o new file mode 100644 index 00000000..ea6cc06c Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_settod.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_software_exception.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_software_exception.d new file mode 100644 index 00000000..fab40238 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_software_exception.d @@ -0,0 +1,6 @@ +obj/HAL/src/alt_software_exception.o: HAL/src/alt_software_exception.S \ + system.h linker.h + +system.h: + +linker.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_software_exception.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_software_exception.o new file mode 100644 index 00000000..f9e01c24 Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_software_exception.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_stat.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_stat.d new file mode 100644 index 00000000..8a63c276 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_stat.d @@ -0,0 +1,3 @@ +obj/HAL/src/alt_stat.o: HAL/src/alt_stat.c HAL/inc/os/alt_syscall.h + +HAL/inc/os/alt_syscall.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_stat.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_stat.o new file mode 100644 index 00000000..0033b84d Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_stat.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_tick.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_tick.d new file mode 100644 index 00000000..8bdf3df0 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_tick.d @@ -0,0 +1,57 @@ +obj/HAL/src/alt_tick.o: HAL/src/alt_tick.c HAL/inc/sys/alt_irq.h \ + HAL/inc/nios2.h HAL/inc/alt_types.h system.h linker.h \ + HAL/inc/priv/alt_legacy_irq.h system.h HAL/inc/nios2.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_irq.h HAL/inc/sys/alt_alarm.h \ + HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \ + UCOSII/inc/os/alt_hooks.h HAL/inc/includes.h HAL/inc/os_cpu.h \ + HAL/inc/sys/alt_irq.h UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h \ + system.h UCOSII/inc/ucos_ii.h UCOSII/inc/os_cfg.h HAL/inc/os_cpu.h \ + HAL/inc/alt_types.h + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +UCOSII/inc/os/alt_hooks.h: + +HAL/inc/includes.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +system.h: + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/os_cpu.h: + +HAL/inc/alt_types.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_tick.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_tick.o new file mode 100644 index 00000000..32629c4a Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_tick.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_times.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_times.d new file mode 100644 index 00000000..4bad83d4 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_times.d @@ -0,0 +1,17 @@ +obj/HAL/src/alt_times.o: HAL/src/alt_times.c HAL/inc/sys/alt_errno.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_alarm.h HAL/inc/alt_types.h HAL/inc/os/alt_syscall.h + +HAL/inc/sys/alt_errno.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +HAL/inc/alt_types.h: + +HAL/inc/os/alt_syscall.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_times.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_times.o new file mode 100644 index 00000000..0771677b Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_times.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_uncached_free.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_uncached_free.d new file mode 100644 index 00000000..d74ef4b9 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_uncached_free.d @@ -0,0 +1,10 @@ +obj/HAL/src/alt_uncached_free.o: HAL/src/alt_uncached_free.c \ + HAL/inc/sys/alt_cache.h HAL/inc/alt_types.h system.h linker.h + +HAL/inc/sys/alt_cache.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_uncached_free.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_uncached_free.o new file mode 100644 index 00000000..353f720c Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_uncached_free.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_uncached_malloc.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_uncached_malloc.d new file mode 100644 index 00000000..16799fba --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_uncached_malloc.d @@ -0,0 +1,10 @@ +obj/HAL/src/alt_uncached_malloc.o: HAL/src/alt_uncached_malloc.c \ + HAL/inc/sys/alt_cache.h HAL/inc/alt_types.h system.h linker.h + +HAL/inc/sys/alt_cache.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_uncached_malloc.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_uncached_malloc.o new file mode 100644 index 00000000..5d7e8776 Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_uncached_malloc.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_unlink.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_unlink.d new file mode 100644 index 00000000..0205f86c --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_unlink.d @@ -0,0 +1,10 @@ +obj/HAL/src/alt_unlink.o: HAL/src/alt_unlink.c HAL/inc/sys/alt_errno.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_warning.h HAL/inc/os/alt_syscall.h + +HAL/inc/sys/alt_errno.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_warning.h: + +HAL/inc/os/alt_syscall.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_unlink.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_unlink.o new file mode 100644 index 00000000..411fc9ac Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_unlink.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_usleep.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_usleep.d new file mode 100644 index 00000000..e7846b46 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_usleep.d @@ -0,0 +1,50 @@ +obj/HAL/src/alt_usleep.o: HAL/src/alt_usleep.c system.h linker.h \ + HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \ + HAL/inc/priv/alt_alarm.h HAL/inc/alt_types.h \ + HAL/inc/priv/alt_busy_sleep.h HAL/inc/os/alt_syscall.h \ + HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \ + HAL/inc/nios2.h HAL/inc/priv/alt_legacy_irq.h HAL/inc/nios2.h \ + HAL/inc/sys/alt_irq.h UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h \ + UCOSII/inc/ucos_ii.h UCOSII/inc/os_cfg.h HAL/inc/os_cpu.h + +system.h: + +linker.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_alarm.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_busy_sleep.h: + +HAL/inc/os/alt_syscall.h: + +HAL/inc/includes.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/priv/alt_legacy_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/sys/alt_irq.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/os_cpu.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_usleep.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_usleep.o new file mode 100644 index 00000000..6eb63edb Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_usleep.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_wait.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_wait.d new file mode 100644 index 00000000..f47f5df1 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_wait.d @@ -0,0 +1,8 @@ +obj/HAL/src/alt_wait.o: HAL/src/alt_wait.c HAL/inc/sys/alt_errno.h \ + HAL/inc/alt_types.h HAL/inc/os/alt_syscall.h + +HAL/inc/sys/alt_errno.h: + +HAL/inc/alt_types.h: + +HAL/inc/os/alt_syscall.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_wait.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_wait.o new file mode 100644 index 00000000..8cd11654 Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_wait.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_write.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_write.d new file mode 100644 index 00000000..30d74a77 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_write.d @@ -0,0 +1,78 @@ +obj/HAL/src/alt_write.o: HAL/src/alt_write.c HAL/inc/sys/alt_errno.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_warning.h HAL/inc/priv/alt_file.h \ + HAL/inc/sys/alt_dev.h system.h linker.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h UCOSII/inc/os/alt_sem.h \ + UCOSII/inc/priv/alt_sem_ucosii.h HAL/inc/includes.h HAL/inc/os_cpu.h \ + HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/priv/alt_legacy_irq.h \ + system.h HAL/inc/nios2.h HAL/inc/sys/alt_irq.h UCOSII/inc/os_cfg.h \ + HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_alarm.h system.h UCOSII/inc/ucos_ii.h \ + UCOSII/inc/os_cfg.h HAL/inc/os_cpu.h HAL/inc/alt_types.h \ + HAL/inc/os/alt_syscall.h HAL/inc/sys/alt_log_printf.h system.h + +HAL/inc/sys/alt_errno.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_warning.h: + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +UCOSII/inc/os/alt_sem.h: + +UCOSII/inc/priv/alt_sem_ucosii.h: + +HAL/inc/includes.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/sys/alt_irq.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +system.h: + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/os_cpu.h: + +HAL/inc/alt_types.h: + +HAL/inc/os/alt_syscall.h: + +HAL/inc/sys/alt_log_printf.h: + +system.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_write.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_write.o new file mode 100644 index 00000000..6a7f93c2 Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/alt_write.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/altera_nios2_qsys_irq.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/altera_nios2_qsys_irq.d new file mode 100644 index 00000000..4c73383c --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/altera_nios2_qsys_irq.d @@ -0,0 +1,27 @@ +obj/HAL/src/altera_nios2_qsys_irq.o: HAL/src/altera_nios2_qsys_irq.c \ + HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/alt_types.h system.h \ + linker.h HAL/inc/priv/alt_legacy_irq.h system.h HAL/inc/nios2.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_irq.h \ + HAL/inc/altera_nios2_qsys_irq.h + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/altera_nios2_qsys_irq.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/altera_nios2_qsys_irq.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/altera_nios2_qsys_irq.o new file mode 100644 index 00000000..4d8b8cee Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/altera_nios2_qsys_irq.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/crt0.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/crt0.d new file mode 100644 index 00000000..3af0bb0c --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/crt0.d @@ -0,0 +1,12 @@ +obj/HAL/src/crt0.o: HAL/src/crt0.S system.h linker.h HAL/inc/nios2.h \ + HAL/inc/sys/alt_log_printf.h system.h + +system.h: + +linker.h: + +HAL/inc/nios2.h: + +HAL/inc/sys/alt_log_printf.h: + +system.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/crt0.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/crt0.o new file mode 100644 index 00000000..e7c01426 Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/crt0.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/os_cpu_a.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/os_cpu_a.d new file mode 100644 index 00000000..1c0caef5 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/os_cpu_a.d @@ -0,0 +1,8 @@ +obj/HAL/src/os_cpu_a.o: HAL/src/os_cpu_a.S UCOSII/inc/os_cfg.h system.h \ + linker.h + +UCOSII/inc/os_cfg.h: + +system.h: + +linker.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/os_cpu_a.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/os_cpu_a.o new file mode 100644 index 00000000..aeb05fcc Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/os_cpu_a.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/os_cpu_c.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/os_cpu_c.d new file mode 100644 index 00000000..a7c2e588 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/os_cpu_c.d @@ -0,0 +1,49 @@ +obj/HAL/src/os_cpu_c.o: HAL/src/os_cpu_c.c HAL/inc/includes.h \ + HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h HAL/inc/nios2.h \ + HAL/inc/alt_types.h system.h linker.h HAL/inc/priv/alt_legacy_irq.h \ + system.h HAL/inc/nios2.h HAL/inc/alt_types.h HAL/inc/sys/alt_irq.h \ + UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_alarm.h system.h UCOSII/inc/ucos_ii.h \ + UCOSII/inc/os_cfg.h HAL/inc/os_cpu.h system.h + +HAL/inc/includes.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_irq.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +system.h: + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/os_cpu.h: + +system.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/os_cpu_c.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/os_cpu_c.o new file mode 100644 index 00000000..156fae45 Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/HAL/src/os_cpu_c.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/UCOSII/src/alt_env_lock.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/UCOSII/src/alt_env_lock.d new file mode 100644 index 00000000..b7aff0d6 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/UCOSII/src/alt_env_lock.d @@ -0,0 +1,50 @@ +obj/UCOSII/src/alt_env_lock.o: UCOSII/src/alt_env_lock.c \ + HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \ + HAL/inc/nios2.h HAL/inc/alt_types.h system.h linker.h \ + HAL/inc/priv/alt_legacy_irq.h system.h HAL/inc/nios2.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_irq.h UCOSII/inc/os_cfg.h \ + HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_alarm.h system.h UCOSII/inc/ucos_ii.h \ + UCOSII/inc/os_cfg.h HAL/inc/os_cpu.h system.h + +HAL/inc/includes.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_irq.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +system.h: + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/os_cpu.h: + +system.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/UCOSII/src/alt_env_lock.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/UCOSII/src/alt_env_lock.o new file mode 100644 index 00000000..db31f2dc Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/UCOSII/src/alt_env_lock.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/UCOSII/src/alt_malloc_lock.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/UCOSII/src/alt_malloc_lock.d new file mode 100644 index 00000000..bcc90128 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/UCOSII/src/alt_malloc_lock.d @@ -0,0 +1,50 @@ +obj/UCOSII/src/alt_malloc_lock.o: UCOSII/src/alt_malloc_lock.c system.h \ + linker.h HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \ + HAL/inc/nios2.h HAL/inc/alt_types.h system.h \ + HAL/inc/priv/alt_legacy_irq.h system.h HAL/inc/nios2.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_irq.h UCOSII/inc/os_cfg.h \ + HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_alarm.h system.h UCOSII/inc/ucos_ii.h \ + UCOSII/inc/os_cfg.h HAL/inc/os_cpu.h + +system.h: + +linker.h: + +HAL/inc/includes.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +system.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_irq.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +system.h: + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/os_cpu.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/UCOSII/src/alt_malloc_lock.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/UCOSII/src/alt_malloc_lock.o new file mode 100644 index 00000000..2ce1cc0f Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/UCOSII/src/alt_malloc_lock.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/UCOSII/src/os_core.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/UCOSII/src/os_core.d new file mode 100644 index 00000000..189739ee --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/UCOSII/src/os_core.d @@ -0,0 +1,40 @@ +obj/UCOSII/src/os_core.o: UCOSII/src/os_core.c UCOSII/inc/ucos_ii.h \ + UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/priv/alt_alarm.h HAL/inc/alt_types.h \ + system.h linker.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \ + HAL/inc/nios2.h system.h HAL/inc/priv/alt_legacy_irq.h system.h \ + HAL/inc/nios2.h HAL/inc/sys/alt_irq.h + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_alarm.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +system.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/sys/alt_irq.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/UCOSII/src/os_core.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/UCOSII/src/os_core.o new file mode 100644 index 00000000..ec317ffc Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/UCOSII/src/os_core.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/UCOSII/src/os_dbg.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/UCOSII/src/os_dbg.d new file mode 100644 index 00000000..3735d257 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/UCOSII/src/os_dbg.d @@ -0,0 +1,40 @@ +obj/UCOSII/src/os_dbg.o: UCOSII/src/os_dbg.c UCOSII/inc/ucos_ii.h \ + UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/priv/alt_alarm.h HAL/inc/alt_types.h \ + system.h linker.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \ + HAL/inc/nios2.h system.h HAL/inc/priv/alt_legacy_irq.h system.h \ + HAL/inc/nios2.h HAL/inc/sys/alt_irq.h + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_alarm.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +system.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/sys/alt_irq.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/UCOSII/src/os_dbg.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/UCOSII/src/os_dbg.o new file mode 100644 index 00000000..19276a05 Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/UCOSII/src/os_dbg.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/UCOSII/src/os_flag.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/UCOSII/src/os_flag.d new file mode 100644 index 00000000..f3072713 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/UCOSII/src/os_flag.d @@ -0,0 +1,40 @@ +obj/UCOSII/src/os_flag.o: UCOSII/src/os_flag.c UCOSII/inc/ucos_ii.h \ + UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/priv/alt_alarm.h HAL/inc/alt_types.h \ + system.h linker.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \ + HAL/inc/nios2.h system.h HAL/inc/priv/alt_legacy_irq.h system.h \ + HAL/inc/nios2.h HAL/inc/sys/alt_irq.h + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_alarm.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +system.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/sys/alt_irq.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/UCOSII/src/os_flag.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/UCOSII/src/os_flag.o new file mode 100644 index 00000000..88721e21 Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/UCOSII/src/os_flag.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/UCOSII/src/os_mbox.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/UCOSII/src/os_mbox.d new file mode 100644 index 00000000..2cbf19c5 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/UCOSII/src/os_mbox.d @@ -0,0 +1,40 @@ +obj/UCOSII/src/os_mbox.o: UCOSII/src/os_mbox.c UCOSII/inc/ucos_ii.h \ + UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/priv/alt_alarm.h HAL/inc/alt_types.h \ + system.h linker.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \ + HAL/inc/nios2.h system.h HAL/inc/priv/alt_legacy_irq.h system.h \ + HAL/inc/nios2.h HAL/inc/sys/alt_irq.h + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_alarm.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +system.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/sys/alt_irq.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/UCOSII/src/os_mbox.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/UCOSII/src/os_mbox.o new file mode 100644 index 00000000..60f0f88d Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/UCOSII/src/os_mbox.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/UCOSII/src/os_mem.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/UCOSII/src/os_mem.d new file mode 100644 index 00000000..33c65518 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/UCOSII/src/os_mem.d @@ -0,0 +1,40 @@ +obj/UCOSII/src/os_mem.o: UCOSII/src/os_mem.c UCOSII/inc/ucos_ii.h \ + UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/priv/alt_alarm.h HAL/inc/alt_types.h \ + system.h linker.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \ + HAL/inc/nios2.h system.h HAL/inc/priv/alt_legacy_irq.h system.h \ + HAL/inc/nios2.h HAL/inc/sys/alt_irq.h + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_alarm.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +system.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/sys/alt_irq.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/UCOSII/src/os_mem.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/UCOSII/src/os_mem.o new file mode 100644 index 00000000..0af26e27 Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/UCOSII/src/os_mem.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/UCOSII/src/os_mutex.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/UCOSII/src/os_mutex.d new file mode 100644 index 00000000..866feaa2 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/UCOSII/src/os_mutex.d @@ -0,0 +1,40 @@ +obj/UCOSII/src/os_mutex.o: UCOSII/src/os_mutex.c UCOSII/inc/ucos_ii.h \ + UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/priv/alt_alarm.h HAL/inc/alt_types.h \ + system.h linker.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \ + HAL/inc/nios2.h system.h HAL/inc/priv/alt_legacy_irq.h system.h \ + HAL/inc/nios2.h HAL/inc/sys/alt_irq.h + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_alarm.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +system.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/sys/alt_irq.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/UCOSII/src/os_mutex.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/UCOSII/src/os_mutex.o new file mode 100644 index 00000000..0e57cdca Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/UCOSII/src/os_mutex.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/UCOSII/src/os_q.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/UCOSII/src/os_q.d new file mode 100644 index 00000000..757ceb45 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/UCOSII/src/os_q.d @@ -0,0 +1,40 @@ +obj/UCOSII/src/os_q.o: UCOSII/src/os_q.c UCOSII/inc/ucos_ii.h \ + UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/priv/alt_alarm.h HAL/inc/alt_types.h \ + system.h linker.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \ + HAL/inc/nios2.h system.h HAL/inc/priv/alt_legacy_irq.h system.h \ + HAL/inc/nios2.h HAL/inc/sys/alt_irq.h + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_alarm.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +system.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/sys/alt_irq.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/UCOSII/src/os_q.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/UCOSII/src/os_q.o new file mode 100644 index 00000000..aa855752 Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/UCOSII/src/os_q.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/UCOSII/src/os_sem.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/UCOSII/src/os_sem.d new file mode 100644 index 00000000..90aeefff --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/UCOSII/src/os_sem.d @@ -0,0 +1,40 @@ +obj/UCOSII/src/os_sem.o: UCOSII/src/os_sem.c UCOSII/inc/ucos_ii.h \ + UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/priv/alt_alarm.h HAL/inc/alt_types.h \ + system.h linker.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \ + HAL/inc/nios2.h system.h HAL/inc/priv/alt_legacy_irq.h system.h \ + HAL/inc/nios2.h HAL/inc/sys/alt_irq.h + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_alarm.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +system.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/sys/alt_irq.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/UCOSII/src/os_sem.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/UCOSII/src/os_sem.o new file mode 100644 index 00000000..23c87649 Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/UCOSII/src/os_sem.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/UCOSII/src/os_task.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/UCOSII/src/os_task.d new file mode 100644 index 00000000..046981a2 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/UCOSII/src/os_task.d @@ -0,0 +1,40 @@ +obj/UCOSII/src/os_task.o: UCOSII/src/os_task.c UCOSII/inc/ucos_ii.h \ + UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/priv/alt_alarm.h HAL/inc/alt_types.h \ + system.h linker.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \ + HAL/inc/nios2.h system.h HAL/inc/priv/alt_legacy_irq.h system.h \ + HAL/inc/nios2.h HAL/inc/sys/alt_irq.h + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_alarm.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +system.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/sys/alt_irq.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/UCOSII/src/os_task.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/UCOSII/src/os_task.o new file mode 100644 index 00000000..3af950f2 Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/UCOSII/src/os_task.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/UCOSII/src/os_time.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/UCOSII/src/os_time.d new file mode 100644 index 00000000..fba03554 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/UCOSII/src/os_time.d @@ -0,0 +1,40 @@ +obj/UCOSII/src/os_time.o: UCOSII/src/os_time.c UCOSII/inc/ucos_ii.h \ + UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/priv/alt_alarm.h HAL/inc/alt_types.h \ + system.h linker.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \ + HAL/inc/nios2.h system.h HAL/inc/priv/alt_legacy_irq.h system.h \ + HAL/inc/nios2.h HAL/inc/sys/alt_irq.h + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_alarm.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +system.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/sys/alt_irq.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/UCOSII/src/os_time.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/UCOSII/src/os_time.o new file mode 100644 index 00000000..786ea4a6 Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/UCOSII/src/os_time.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/UCOSII/src/os_tmr.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/UCOSII/src/os_tmr.d new file mode 100644 index 00000000..222d4c34 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/UCOSII/src/os_tmr.d @@ -0,0 +1,40 @@ +obj/UCOSII/src/os_tmr.o: UCOSII/src/os_tmr.c UCOSII/inc/ucos_ii.h \ + UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/priv/alt_alarm.h HAL/inc/alt_types.h \ + system.h linker.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \ + HAL/inc/nios2.h system.h HAL/inc/priv/alt_legacy_irq.h system.h \ + HAL/inc/nios2.h HAL/inc/sys/alt_irq.h + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_alarm.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +system.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/sys/alt_irq.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/UCOSII/src/os_tmr.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/UCOSII/src/os_tmr.o new file mode 100644 index 00000000..5f4f338c Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/UCOSII/src/os_tmr.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/alt_sys_init.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/alt_sys_init.d new file mode 100644 index 00000000..744324d5 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/alt_sys_init.d @@ -0,0 +1,113 @@ +obj/alt_sys_init.o: alt_sys_init.c system.h linker.h \ + HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/alt_types.h system.h \ + HAL/inc/priv/alt_legacy_irq.h system.h HAL/inc/nios2.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_irq.h HAL/inc/sys/alt_sys_init.h \ + HAL/inc/altera_nios2_qsys_irq.h drivers/inc/altera_avalon_jtag_uart.h \ + HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_alarm.h HAL/inc/sys/alt_warning.h \ + UCOSII/inc/os/alt_sem.h UCOSII/inc/priv/alt_sem_ucosii.h \ + HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \ + UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h system.h \ + UCOSII/inc/ucos_ii.h UCOSII/inc/os_cfg.h HAL/inc/os_cpu.h \ + HAL/inc/alt_types.h UCOSII/inc/os/alt_flag.h \ + UCOSII/inc/priv/alt_flag_ucosii.h \ + drivers/inc/altera_avalon_jtag_uart_fd.h HAL/inc/sys/alt_dev.h \ + HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_dev_llist.h \ + HAL/inc/sys/alt_llist.h drivers/inc/altera_avalon_sysid_qsys.h \ + HAL/inc/alt_types.h drivers/inc/altera_avalon_timer.h \ + drivers/inc/altera_avalon_uart.h HAL/inc/sys/termios.h \ + drivers/inc/altera_avalon_uart_fd.h \ + drivers/inc/altera_up_avalon_rs232.h HAL/inc/alt_types.h \ + HAL/inc/sys/alt_dev.h + +system.h: + +linker.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +system.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/sys/alt_sys_init.h: + +HAL/inc/altera_nios2_qsys_irq.h: + +drivers/inc/altera_avalon_jtag_uart.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +HAL/inc/sys/alt_warning.h: + +UCOSII/inc/os/alt_sem.h: + +UCOSII/inc/priv/alt_sem_ucosii.h: + +HAL/inc/includes.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +system.h: + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/os_cpu.h: + +HAL/inc/alt_types.h: + +UCOSII/inc/os/alt_flag.h: + +UCOSII/inc/priv/alt_flag_ucosii.h: + +drivers/inc/altera_avalon_jtag_uart_fd.h: + +HAL/inc/sys/alt_dev.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +drivers/inc/altera_avalon_sysid_qsys.h: + +HAL/inc/alt_types.h: + +drivers/inc/altera_avalon_timer.h: + +drivers/inc/altera_avalon_uart.h: + +HAL/inc/sys/termios.h: + +drivers/inc/altera_avalon_uart_fd.h: + +drivers/inc/altera_up_avalon_rs232.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_dev.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/alt_sys_init.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/alt_sys_init.o new file mode 100644 index 00000000..7e2eb612 Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/alt_sys_init.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/drivers/src/altera_avalon_jtag_uart_fd.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/drivers/src/altera_avalon_jtag_uart_fd.d new file mode 100644 index 00000000..d4994f53 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/drivers/src/altera_avalon_jtag_uart_fd.d @@ -0,0 +1,85 @@ +obj/drivers/src/altera_avalon_jtag_uart_fd.o: \ + drivers/src/altera_avalon_jtag_uart_fd.c HAL/inc/alt_types.h \ + HAL/inc/sys/alt_dev.h system.h linker.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/priv/alt_dev_llist.h \ + HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \ + drivers/inc/altera_avalon_jtag_uart.h HAL/inc/sys/alt_alarm.h \ + HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h \ + HAL/inc/sys/alt_warning.h UCOSII/inc/os/alt_sem.h \ + UCOSII/inc/priv/alt_sem_ucosii.h HAL/inc/includes.h HAL/inc/os_cpu.h \ + HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/priv/alt_legacy_irq.h \ + system.h HAL/inc/nios2.h HAL/inc/sys/alt_irq.h UCOSII/inc/os_cfg.h \ + HAL/inc/sys/alt_alarm.h system.h UCOSII/inc/ucos_ii.h \ + UCOSII/inc/os_cfg.h HAL/inc/os_cpu.h HAL/inc/alt_types.h \ + UCOSII/inc/os/alt_flag.h UCOSII/inc/priv/alt_flag_ucosii.h \ + drivers/inc/altera_avalon_jtag_uart_fd.h HAL/inc/sys/alt_dev.h + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +drivers/inc/altera_avalon_jtag_uart.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +HAL/inc/sys/alt_warning.h: + +UCOSII/inc/os/alt_sem.h: + +UCOSII/inc/priv/alt_sem_ucosii.h: + +HAL/inc/includes.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/sys/alt_irq.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +system.h: + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/os_cpu.h: + +HAL/inc/alt_types.h: + +UCOSII/inc/os/alt_flag.h: + +UCOSII/inc/priv/alt_flag_ucosii.h: + +drivers/inc/altera_avalon_jtag_uart_fd.h: + +HAL/inc/sys/alt_dev.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/drivers/src/altera_avalon_jtag_uart_fd.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/drivers/src/altera_avalon_jtag_uart_fd.o new file mode 100644 index 00000000..4f44a215 Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/drivers/src/altera_avalon_jtag_uart_fd.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/drivers/src/altera_avalon_jtag_uart_init.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/drivers/src/altera_avalon_jtag_uart_init.d new file mode 100644 index 00000000..553359a1 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/drivers/src/altera_avalon_jtag_uart_init.d @@ -0,0 +1,102 @@ +obj/drivers/src/altera_avalon_jtag_uart_init.o: \ + drivers/src/altera_avalon_jtag_uart_init.c HAL/inc/sys/alt_irq.h \ + HAL/inc/nios2.h HAL/inc/alt_types.h system.h linker.h \ + HAL/inc/priv/alt_legacy_irq.h system.h HAL/inc/nios2.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_irq.h HAL/inc/sys/alt_alarm.h \ + HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h HAL/inc/sys/ioctl.h \ + HAL/inc/alt_types.h drivers/inc/altera_avalon_jtag_uart_regs.h \ + HAL/inc/io.h HAL/inc/alt_types.h drivers/inc/altera_avalon_jtag_uart.h \ + HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_warning.h \ + UCOSII/inc/os/alt_sem.h UCOSII/inc/priv/alt_sem_ucosii.h \ + HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \ + UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h system.h \ + UCOSII/inc/ucos_ii.h UCOSII/inc/os_cfg.h HAL/inc/os_cpu.h \ + HAL/inc/alt_types.h UCOSII/inc/os/alt_flag.h \ + UCOSII/inc/priv/alt_flag_ucosii.h \ + drivers/inc/altera_avalon_jtag_uart_fd.h HAL/inc/sys/alt_dev.h \ + HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_dev_llist.h \ + HAL/inc/sys/alt_llist.h HAL/inc/sys/alt_log_printf.h system.h + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +HAL/inc/sys/ioctl.h: + +HAL/inc/alt_types.h: + +drivers/inc/altera_avalon_jtag_uart_regs.h: + +HAL/inc/io.h: + +HAL/inc/alt_types.h: + +drivers/inc/altera_avalon_jtag_uart.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_warning.h: + +UCOSII/inc/os/alt_sem.h: + +UCOSII/inc/priv/alt_sem_ucosii.h: + +HAL/inc/includes.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +system.h: + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/os_cpu.h: + +HAL/inc/alt_types.h: + +UCOSII/inc/os/alt_flag.h: + +UCOSII/inc/priv/alt_flag_ucosii.h: + +drivers/inc/altera_avalon_jtag_uart_fd.h: + +HAL/inc/sys/alt_dev.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/sys/alt_log_printf.h: + +system.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/drivers/src/altera_avalon_jtag_uart_init.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/drivers/src/altera_avalon_jtag_uart_init.o new file mode 100644 index 00000000..eb9167b1 Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/drivers/src/altera_avalon_jtag_uart_init.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/drivers/src/altera_avalon_jtag_uart_ioctl.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/drivers/src/altera_avalon_jtag_uart_ioctl.d new file mode 100644 index 00000000..b29ef0f6 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/drivers/src/altera_avalon_jtag_uart_ioctl.d @@ -0,0 +1,96 @@ +obj/drivers/src/altera_avalon_jtag_uart_ioctl.o: \ + drivers/src/altera_avalon_jtag_uart_ioctl.c HAL/inc/sys/ioctl.h \ + HAL/inc/alt_types.h drivers/inc/altera_avalon_jtag_uart_regs.h \ + HAL/inc/io.h HAL/inc/alt_types.h drivers/inc/altera_avalon_jtag_uart.h \ + HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \ + HAL/inc/priv/alt_alarm.h HAL/inc/alt_types.h HAL/inc/sys/alt_warning.h \ + UCOSII/inc/os/alt_sem.h UCOSII/inc/priv/alt_sem_ucosii.h \ + HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \ + HAL/inc/nios2.h system.h linker.h HAL/inc/priv/alt_legacy_irq.h \ + system.h HAL/inc/nios2.h HAL/inc/sys/alt_irq.h UCOSII/inc/os_cfg.h \ + HAL/inc/sys/alt_alarm.h system.h UCOSII/inc/ucos_ii.h \ + UCOSII/inc/os_cfg.h HAL/inc/os_cpu.h HAL/inc/alt_types.h \ + UCOSII/inc/os/alt_flag.h UCOSII/inc/priv/alt_flag_ucosii.h \ + drivers/inc/altera_avalon_jtag_uart_fd.h HAL/inc/sys/alt_dev.h \ + HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_dev_llist.h \ + HAL/inc/sys/alt_llist.h HAL/inc/sys/alt_log_printf.h system.h + +HAL/inc/sys/ioctl.h: + +HAL/inc/alt_types.h: + +drivers/inc/altera_avalon_jtag_uart_regs.h: + +HAL/inc/io.h: + +HAL/inc/alt_types.h: + +drivers/inc/altera_avalon_jtag_uart.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_alarm.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_warning.h: + +UCOSII/inc/os/alt_sem.h: + +UCOSII/inc/priv/alt_sem_ucosii.h: + +HAL/inc/includes.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +system.h: + +linker.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/sys/alt_irq.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +system.h: + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/os_cpu.h: + +HAL/inc/alt_types.h: + +UCOSII/inc/os/alt_flag.h: + +UCOSII/inc/priv/alt_flag_ucosii.h: + +drivers/inc/altera_avalon_jtag_uart_fd.h: + +HAL/inc/sys/alt_dev.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/sys/alt_log_printf.h: + +system.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/drivers/src/altera_avalon_jtag_uart_ioctl.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/drivers/src/altera_avalon_jtag_uart_ioctl.o new file mode 100644 index 00000000..4d649c21 Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/drivers/src/altera_avalon_jtag_uart_ioctl.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/drivers/src/altera_avalon_jtag_uart_read.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/drivers/src/altera_avalon_jtag_uart_read.d new file mode 100644 index 00000000..821f92ac --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/drivers/src/altera_avalon_jtag_uart_read.d @@ -0,0 +1,105 @@ +obj/drivers/src/altera_avalon_jtag_uart_read.o: \ + drivers/src/altera_avalon_jtag_uart_read.c HAL/inc/sys/alt_irq.h \ + HAL/inc/nios2.h HAL/inc/alt_types.h system.h linker.h \ + HAL/inc/priv/alt_legacy_irq.h system.h HAL/inc/nios2.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_irq.h HAL/inc/sys/alt_alarm.h \ + HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h HAL/inc/sys/ioctl.h \ + HAL/inc/alt_types.h drivers/inc/altera_avalon_jtag_uart_regs.h \ + HAL/inc/io.h HAL/inc/alt_types.h drivers/inc/altera_avalon_jtag_uart.h \ + HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_warning.h \ + UCOSII/inc/os/alt_sem.h UCOSII/inc/priv/alt_sem_ucosii.h \ + HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \ + UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h system.h \ + UCOSII/inc/ucos_ii.h UCOSII/inc/os_cfg.h HAL/inc/os_cpu.h \ + HAL/inc/alt_types.h UCOSII/inc/os/alt_flag.h \ + UCOSII/inc/priv/alt_flag_ucosii.h \ + drivers/inc/altera_avalon_jtag_uart_fd.h HAL/inc/sys/alt_dev.h \ + HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_dev_llist.h \ + HAL/inc/sys/alt_llist.h HAL/inc/sys/alt_log_printf.h system.h \ + HAL/inc/includes.h + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +HAL/inc/sys/ioctl.h: + +HAL/inc/alt_types.h: + +drivers/inc/altera_avalon_jtag_uart_regs.h: + +HAL/inc/io.h: + +HAL/inc/alt_types.h: + +drivers/inc/altera_avalon_jtag_uart.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_warning.h: + +UCOSII/inc/os/alt_sem.h: + +UCOSII/inc/priv/alt_sem_ucosii.h: + +HAL/inc/includes.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +system.h: + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/os_cpu.h: + +HAL/inc/alt_types.h: + +UCOSII/inc/os/alt_flag.h: + +UCOSII/inc/priv/alt_flag_ucosii.h: + +drivers/inc/altera_avalon_jtag_uart_fd.h: + +HAL/inc/sys/alt_dev.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/sys/alt_log_printf.h: + +system.h: + +HAL/inc/includes.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/drivers/src/altera_avalon_jtag_uart_read.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/drivers/src/altera_avalon_jtag_uart_read.o new file mode 100644 index 00000000..e3881b8d Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/drivers/src/altera_avalon_jtag_uart_read.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/drivers/src/altera_avalon_jtag_uart_write.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/drivers/src/altera_avalon_jtag_uart_write.d new file mode 100644 index 00000000..626796a4 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/drivers/src/altera_avalon_jtag_uart_write.d @@ -0,0 +1,105 @@ +obj/drivers/src/altera_avalon_jtag_uart_write.o: \ + drivers/src/altera_avalon_jtag_uart_write.c HAL/inc/sys/alt_irq.h \ + HAL/inc/nios2.h HAL/inc/alt_types.h system.h linker.h \ + HAL/inc/priv/alt_legacy_irq.h system.h HAL/inc/nios2.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_irq.h HAL/inc/sys/alt_alarm.h \ + HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h HAL/inc/sys/ioctl.h \ + HAL/inc/alt_types.h drivers/inc/altera_avalon_jtag_uart_regs.h \ + HAL/inc/io.h HAL/inc/alt_types.h drivers/inc/altera_avalon_jtag_uart.h \ + HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_warning.h \ + UCOSII/inc/os/alt_sem.h UCOSII/inc/priv/alt_sem_ucosii.h \ + HAL/inc/includes.h HAL/inc/os_cpu.h HAL/inc/sys/alt_irq.h \ + UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h system.h \ + UCOSII/inc/ucos_ii.h UCOSII/inc/os_cfg.h HAL/inc/os_cpu.h \ + HAL/inc/alt_types.h UCOSII/inc/os/alt_flag.h \ + UCOSII/inc/priv/alt_flag_ucosii.h \ + drivers/inc/altera_avalon_jtag_uart_fd.h HAL/inc/sys/alt_dev.h \ + HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_dev_llist.h \ + HAL/inc/sys/alt_llist.h HAL/inc/sys/alt_log_printf.h system.h \ + HAL/inc/includes.h + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +HAL/inc/sys/ioctl.h: + +HAL/inc/alt_types.h: + +drivers/inc/altera_avalon_jtag_uart_regs.h: + +HAL/inc/io.h: + +HAL/inc/alt_types.h: + +drivers/inc/altera_avalon_jtag_uart.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_warning.h: + +UCOSII/inc/os/alt_sem.h: + +UCOSII/inc/priv/alt_sem_ucosii.h: + +HAL/inc/includes.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +system.h: + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/os_cpu.h: + +HAL/inc/alt_types.h: + +UCOSII/inc/os/alt_flag.h: + +UCOSII/inc/priv/alt_flag_ucosii.h: + +drivers/inc/altera_avalon_jtag_uart_fd.h: + +HAL/inc/sys/alt_dev.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/sys/alt_log_printf.h: + +system.h: + +HAL/inc/includes.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/drivers/src/altera_avalon_jtag_uart_write.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/drivers/src/altera_avalon_jtag_uart_write.o new file mode 100644 index 00000000..bfa458ee Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/drivers/src/altera_avalon_jtag_uart_write.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/drivers/src/altera_avalon_sysid_qsys.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/drivers/src/altera_avalon_sysid_qsys.d new file mode 100644 index 00000000..b90af16d --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/drivers/src/altera_avalon_sysid_qsys.d @@ -0,0 +1,21 @@ +obj/drivers/src/altera_avalon_sysid_qsys.o: \ + drivers/src/altera_avalon_sysid_qsys.c \ + drivers/inc/altera_avalon_sysid_qsys.h HAL/inc/alt_types.h \ + drivers/inc/altera_avalon_sysid_qsys_regs.h HAL/inc/io.h \ + HAL/inc/alt_types.h HAL/inc/alt_types.h system.h linker.h + +drivers/inc/altera_avalon_sysid_qsys.h: + +HAL/inc/alt_types.h: + +drivers/inc/altera_avalon_sysid_qsys_regs.h: + +HAL/inc/io.h: + +HAL/inc/alt_types.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/drivers/src/altera_avalon_sysid_qsys.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/drivers/src/altera_avalon_sysid_qsys.o new file mode 100644 index 00000000..a7d0e376 Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/drivers/src/altera_avalon_sysid_qsys.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/drivers/src/altera_avalon_timer_sc.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/drivers/src/altera_avalon_timer_sc.d new file mode 100644 index 00000000..12d1d652 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/drivers/src/altera_avalon_timer_sc.d @@ -0,0 +1,63 @@ +obj/drivers/src/altera_avalon_timer_sc.o: \ + drivers/src/altera_avalon_timer_sc.c HAL/inc/sys/alt_alarm.h \ + HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h HAL/inc/priv/alt_alarm.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_irq.h HAL/inc/nios2.h system.h \ + linker.h HAL/inc/priv/alt_legacy_irq.h system.h HAL/inc/nios2.h \ + HAL/inc/sys/alt_irq.h drivers/inc/altera_avalon_timer.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_dev.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/sys/alt_warning.h drivers/inc/altera_avalon_timer_regs.h \ + HAL/inc/io.h HAL/inc/alt_types.h HAL/inc/alt_types.h \ + HAL/inc/sys/alt_log_printf.h system.h + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_alarm.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +system.h: + +linker.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/sys/alt_irq.h: + +drivers/inc/altera_avalon_timer.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_dev.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/sys/alt_warning.h: + +drivers/inc/altera_avalon_timer_regs.h: + +HAL/inc/io.h: + +HAL/inc/alt_types.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_log_printf.h: + +system.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/drivers/src/altera_avalon_timer_sc.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/drivers/src/altera_avalon_timer_sc.o new file mode 100644 index 00000000..1701280d Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/drivers/src/altera_avalon_timer_sc.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/drivers/src/altera_avalon_timer_ts.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/drivers/src/altera_avalon_timer_ts.d new file mode 100644 index 00000000..444f9465 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/drivers/src/altera_avalon_timer_ts.d @@ -0,0 +1,46 @@ +obj/drivers/src/altera_avalon_timer_ts.o: \ + drivers/src/altera_avalon_timer_ts.c system.h linker.h \ + HAL/inc/sys/alt_timestamp.h HAL/inc/alt_types.h \ + drivers/inc/altera_avalon_timer.h HAL/inc/alt_types.h \ + HAL/inc/sys/alt_dev.h system.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_warning.h \ + drivers/inc/altera_avalon_timer.h \ + drivers/inc/altera_avalon_timer_regs.h HAL/inc/io.h HAL/inc/alt_types.h \ + HAL/inc/alt_types.h + +system.h: + +linker.h: + +HAL/inc/sys/alt_timestamp.h: + +HAL/inc/alt_types.h: + +drivers/inc/altera_avalon_timer.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_dev.h: + +system.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_warning.h: + +drivers/inc/altera_avalon_timer.h: + +drivers/inc/altera_avalon_timer_regs.h: + +HAL/inc/io.h: + +HAL/inc/alt_types.h: + +HAL/inc/alt_types.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/drivers/src/altera_avalon_timer_ts.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/drivers/src/altera_avalon_timer_ts.o new file mode 100644 index 00000000..02f9f18b Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/drivers/src/altera_avalon_timer_ts.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/drivers/src/altera_avalon_timer_vars.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/drivers/src/altera_avalon_timer_vars.d new file mode 100644 index 00000000..f478e393 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/drivers/src/altera_avalon_timer_vars.d @@ -0,0 +1,30 @@ +obj/drivers/src/altera_avalon_timer_vars.o: \ + drivers/src/altera_avalon_timer_vars.c drivers/inc/altera_avalon_timer.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_dev.h system.h linker.h \ + HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_warning.h HAL/inc/alt_types.h + +drivers/inc/altera_avalon_timer.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_warning.h: + +HAL/inc/alt_types.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/drivers/src/altera_avalon_timer_vars.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/drivers/src/altera_avalon_timer_vars.o new file mode 100644 index 00000000..75aebf57 Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/drivers/src/altera_avalon_timer_vars.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/drivers/src/altera_avalon_uart_fd.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/drivers/src/altera_avalon_uart_fd.d new file mode 100644 index 00000000..7fb73e8d --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/drivers/src/altera_avalon_uart_fd.d @@ -0,0 +1,88 @@ +obj/drivers/src/altera_avalon_uart_fd.o: \ + drivers/src/altera_avalon_uart_fd.c HAL/inc/alt_types.h \ + HAL/inc/sys/alt_dev.h system.h linker.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/priv/alt_dev_llist.h \ + HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \ + drivers/inc/altera_avalon_uart.h HAL/inc/sys/termios.h \ + HAL/inc/sys/alt_warning.h UCOSII/inc/os/alt_sem.h \ + UCOSII/inc/priv/alt_sem_ucosii.h HAL/inc/includes.h HAL/inc/os_cpu.h \ + HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/priv/alt_legacy_irq.h \ + system.h HAL/inc/nios2.h HAL/inc/sys/alt_irq.h UCOSII/inc/os_cfg.h \ + HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_alarm.h system.h UCOSII/inc/ucos_ii.h \ + UCOSII/inc/os_cfg.h HAL/inc/os_cpu.h HAL/inc/alt_types.h \ + UCOSII/inc/os/alt_flag.h UCOSII/inc/priv/alt_flag_ucosii.h \ + HAL/inc/alt_types.h drivers/inc/altera_avalon_uart_fd.h \ + HAL/inc/sys/alt_dev.h + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +drivers/inc/altera_avalon_uart.h: + +HAL/inc/sys/termios.h: + +HAL/inc/sys/alt_warning.h: + +UCOSII/inc/os/alt_sem.h: + +UCOSII/inc/priv/alt_sem_ucosii.h: + +HAL/inc/includes.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/sys/alt_irq.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +system.h: + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/os_cpu.h: + +HAL/inc/alt_types.h: + +UCOSII/inc/os/alt_flag.h: + +UCOSII/inc/priv/alt_flag_ucosii.h: + +HAL/inc/alt_types.h: + +drivers/inc/altera_avalon_uart_fd.h: + +HAL/inc/sys/alt_dev.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/drivers/src/altera_avalon_uart_fd.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/drivers/src/altera_avalon_uart_fd.o new file mode 100644 index 00000000..c5962b44 Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/drivers/src/altera_avalon_uart_fd.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/drivers/src/altera_avalon_uart_init.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/drivers/src/altera_avalon_uart_init.d new file mode 100644 index 00000000..8e9ad772 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/drivers/src/altera_avalon_uart_init.d @@ -0,0 +1,99 @@ +obj/drivers/src/altera_avalon_uart_init.o: \ + drivers/src/altera_avalon_uart_init.c HAL/inc/sys/alt_dev.h system.h \ + linker.h HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_irq.h HAL/inc/nios2.h \ + HAL/inc/priv/alt_legacy_irq.h system.h HAL/inc/nios2.h \ + HAL/inc/sys/alt_irq.h HAL/inc/sys/ioctl.h HAL/inc/sys/alt_errno.h \ + drivers/inc/altera_avalon_uart.h HAL/inc/sys/termios.h \ + HAL/inc/sys/alt_warning.h UCOSII/inc/os/alt_sem.h \ + UCOSII/inc/priv/alt_sem_ucosii.h HAL/inc/includes.h HAL/inc/os_cpu.h \ + HAL/inc/sys/alt_irq.h UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h \ + HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h system.h \ + UCOSII/inc/ucos_ii.h UCOSII/inc/os_cfg.h HAL/inc/os_cpu.h \ + HAL/inc/alt_types.h UCOSII/inc/os/alt_flag.h \ + UCOSII/inc/priv/alt_flag_ucosii.h HAL/inc/alt_types.h \ + drivers/inc/altera_avalon_uart_fd.h HAL/inc/sys/alt_dev.h \ + drivers/inc/altera_avalon_uart_regs.h HAL/inc/io.h HAL/inc/alt_types.h + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/sys/ioctl.h: + +HAL/inc/sys/alt_errno.h: + +drivers/inc/altera_avalon_uart.h: + +HAL/inc/sys/termios.h: + +HAL/inc/sys/alt_warning.h: + +UCOSII/inc/os/alt_sem.h: + +UCOSII/inc/priv/alt_sem_ucosii.h: + +HAL/inc/includes.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +system.h: + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/os_cpu.h: + +HAL/inc/alt_types.h: + +UCOSII/inc/os/alt_flag.h: + +UCOSII/inc/priv/alt_flag_ucosii.h: + +HAL/inc/alt_types.h: + +drivers/inc/altera_avalon_uart_fd.h: + +HAL/inc/sys/alt_dev.h: + +drivers/inc/altera_avalon_uart_regs.h: + +HAL/inc/io.h: + +HAL/inc/alt_types.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/drivers/src/altera_avalon_uart_init.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/drivers/src/altera_avalon_uart_init.o new file mode 100644 index 00000000..69b4655a Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/drivers/src/altera_avalon_uart_init.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/drivers/src/altera_avalon_uart_ioctl.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/drivers/src/altera_avalon_uart_ioctl.d new file mode 100644 index 00000000..28a0afbf --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/drivers/src/altera_avalon_uart_ioctl.d @@ -0,0 +1,97 @@ +obj/drivers/src/altera_avalon_uart_ioctl.o: \ + drivers/src/altera_avalon_uart_ioctl.c HAL/inc/sys/alt_irq.h \ + HAL/inc/nios2.h HAL/inc/alt_types.h system.h linker.h \ + HAL/inc/priv/alt_legacy_irq.h system.h HAL/inc/nios2.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_irq.h HAL/inc/sys/ioctl.h \ + HAL/inc/sys/alt_errno.h drivers/inc/altera_avalon_uart_regs.h \ + HAL/inc/io.h HAL/inc/alt_types.h drivers/inc/altera_avalon_uart.h \ + HAL/inc/sys/termios.h HAL/inc/sys/alt_warning.h UCOSII/inc/os/alt_sem.h \ + UCOSII/inc/priv/alt_sem_ucosii.h HAL/inc/includes.h HAL/inc/os_cpu.h \ + HAL/inc/sys/alt_irq.h UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h \ + HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h system.h \ + UCOSII/inc/ucos_ii.h UCOSII/inc/os_cfg.h HAL/inc/os_cpu.h \ + HAL/inc/alt_types.h UCOSII/inc/os/alt_flag.h \ + UCOSII/inc/priv/alt_flag_ucosii.h HAL/inc/alt_types.h \ + drivers/inc/altera_avalon_uart_fd.h HAL/inc/sys/alt_dev.h \ + HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_dev_llist.h \ + HAL/inc/sys/alt_llist.h + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/sys/ioctl.h: + +HAL/inc/sys/alt_errno.h: + +drivers/inc/altera_avalon_uart_regs.h: + +HAL/inc/io.h: + +HAL/inc/alt_types.h: + +drivers/inc/altera_avalon_uart.h: + +HAL/inc/sys/termios.h: + +HAL/inc/sys/alt_warning.h: + +UCOSII/inc/os/alt_sem.h: + +UCOSII/inc/priv/alt_sem_ucosii.h: + +HAL/inc/includes.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +system.h: + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/os_cpu.h: + +HAL/inc/alt_types.h: + +UCOSII/inc/os/alt_flag.h: + +UCOSII/inc/priv/alt_flag_ucosii.h: + +HAL/inc/alt_types.h: + +drivers/inc/altera_avalon_uart_fd.h: + +HAL/inc/sys/alt_dev.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/drivers/src/altera_avalon_uart_ioctl.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/drivers/src/altera_avalon_uart_ioctl.o new file mode 100644 index 00000000..89e05f1c Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/drivers/src/altera_avalon_uart_ioctl.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/drivers/src/altera_avalon_uart_read.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/drivers/src/altera_avalon_uart_read.d new file mode 100644 index 00000000..b7c7f8fc --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/drivers/src/altera_avalon_uart_read.d @@ -0,0 +1,97 @@ +obj/drivers/src/altera_avalon_uart_read.o: \ + drivers/src/altera_avalon_uart_read.c HAL/inc/sys/alt_irq.h \ + HAL/inc/nios2.h HAL/inc/alt_types.h system.h linker.h \ + HAL/inc/priv/alt_legacy_irq.h system.h HAL/inc/nios2.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_irq.h HAL/inc/sys/ioctl.h \ + HAL/inc/sys/alt_errno.h drivers/inc/altera_avalon_uart.h \ + HAL/inc/sys/termios.h HAL/inc/sys/alt_warning.h UCOSII/inc/os/alt_sem.h \ + UCOSII/inc/priv/alt_sem_ucosii.h HAL/inc/includes.h HAL/inc/os_cpu.h \ + HAL/inc/sys/alt_irq.h UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h \ + HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h system.h \ + UCOSII/inc/ucos_ii.h UCOSII/inc/os_cfg.h HAL/inc/os_cpu.h \ + HAL/inc/alt_types.h UCOSII/inc/os/alt_flag.h \ + UCOSII/inc/priv/alt_flag_ucosii.h HAL/inc/alt_types.h \ + drivers/inc/altera_avalon_uart_fd.h HAL/inc/sys/alt_dev.h \ + HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_dev_llist.h \ + HAL/inc/sys/alt_llist.h drivers/inc/altera_avalon_uart_regs.h \ + HAL/inc/io.h HAL/inc/alt_types.h + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +system.h: + +linker.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/sys/ioctl.h: + +HAL/inc/sys/alt_errno.h: + +drivers/inc/altera_avalon_uart.h: + +HAL/inc/sys/termios.h: + +HAL/inc/sys/alt_warning.h: + +UCOSII/inc/os/alt_sem.h: + +UCOSII/inc/priv/alt_sem_ucosii.h: + +HAL/inc/includes.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +system.h: + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/os_cpu.h: + +HAL/inc/alt_types.h: + +UCOSII/inc/os/alt_flag.h: + +UCOSII/inc/priv/alt_flag_ucosii.h: + +HAL/inc/alt_types.h: + +drivers/inc/altera_avalon_uart_fd.h: + +HAL/inc/sys/alt_dev.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +drivers/inc/altera_avalon_uart_regs.h: + +HAL/inc/io.h: + +HAL/inc/alt_types.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/drivers/src/altera_avalon_uart_read.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/drivers/src/altera_avalon_uart_read.o new file mode 100644 index 00000000..a763f341 Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/drivers/src/altera_avalon_uart_read.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/drivers/src/altera_avalon_uart_write.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/drivers/src/altera_avalon_uart_write.d new file mode 100644 index 00000000..46efd14c --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/drivers/src/altera_avalon_uart_write.d @@ -0,0 +1,99 @@ +obj/drivers/src/altera_avalon_uart_write.o: \ + drivers/src/altera_avalon_uart_write.c HAL/inc/sys/alt_dev.h system.h \ + linker.h HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h \ + HAL/inc/priv/alt_dev_llist.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/sys/alt_irq.h HAL/inc/nios2.h \ + HAL/inc/priv/alt_legacy_irq.h system.h HAL/inc/nios2.h \ + HAL/inc/sys/alt_irq.h HAL/inc/sys/ioctl.h HAL/inc/sys/alt_errno.h \ + drivers/inc/altera_avalon_uart_regs.h HAL/inc/io.h HAL/inc/alt_types.h \ + drivers/inc/altera_avalon_uart.h HAL/inc/sys/termios.h \ + HAL/inc/sys/alt_warning.h UCOSII/inc/os/alt_sem.h \ + UCOSII/inc/priv/alt_sem_ucosii.h HAL/inc/includes.h HAL/inc/os_cpu.h \ + HAL/inc/sys/alt_irq.h UCOSII/inc/os_cfg.h HAL/inc/sys/alt_alarm.h \ + HAL/inc/sys/alt_llist.h HAL/inc/priv/alt_alarm.h system.h \ + UCOSII/inc/ucos_ii.h UCOSII/inc/os_cfg.h HAL/inc/os_cpu.h \ + HAL/inc/alt_types.h UCOSII/inc/os/alt_flag.h \ + UCOSII/inc/priv/alt_flag_ucosii.h HAL/inc/alt_types.h \ + drivers/inc/altera_avalon_uart_fd.h HAL/inc/sys/alt_dev.h + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/sys/ioctl.h: + +HAL/inc/sys/alt_errno.h: + +drivers/inc/altera_avalon_uart_regs.h: + +HAL/inc/io.h: + +HAL/inc/alt_types.h: + +drivers/inc/altera_avalon_uart.h: + +HAL/inc/sys/termios.h: + +HAL/inc/sys/alt_warning.h: + +UCOSII/inc/os/alt_sem.h: + +UCOSII/inc/priv/alt_sem_ucosii.h: + +HAL/inc/includes.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +system.h: + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/os_cpu.h: + +HAL/inc/alt_types.h: + +UCOSII/inc/os/alt_flag.h: + +UCOSII/inc/priv/alt_flag_ucosii.h: + +HAL/inc/alt_types.h: + +drivers/inc/altera_avalon_uart_fd.h: + +HAL/inc/sys/alt_dev.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/drivers/src/altera_avalon_uart_write.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/drivers/src/altera_avalon_uart_write.o new file mode 100644 index 00000000..917861ae Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/drivers/src/altera_avalon_uart_write.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/drivers/src/altera_up_avalon_rs232.d b/MCandWifiTestDE0/Software/MCTest_bsp/obj/drivers/src/altera_up_avalon_rs232.d new file mode 100644 index 00000000..3f3972bf --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/obj/drivers/src/altera_up_avalon_rs232.d @@ -0,0 +1,82 @@ +obj/drivers/src/altera_up_avalon_rs232.o: \ + drivers/src/altera_up_avalon_rs232.c HAL/inc/priv/alt_file.h \ + HAL/inc/sys/alt_dev.h system.h linker.h HAL/inc/sys/alt_llist.h \ + HAL/inc/alt_types.h HAL/inc/priv/alt_dev_llist.h \ + HAL/inc/sys/alt_llist.h HAL/inc/alt_types.h UCOSII/inc/os/alt_sem.h \ + UCOSII/inc/priv/alt_sem_ucosii.h HAL/inc/includes.h HAL/inc/os_cpu.h \ + HAL/inc/sys/alt_irq.h HAL/inc/nios2.h HAL/inc/priv/alt_legacy_irq.h \ + system.h HAL/inc/nios2.h HAL/inc/sys/alt_irq.h UCOSII/inc/os_cfg.h \ + HAL/inc/sys/alt_alarm.h HAL/inc/sys/alt_llist.h \ + HAL/inc/priv/alt_alarm.h system.h UCOSII/inc/ucos_ii.h \ + UCOSII/inc/os_cfg.h HAL/inc/os_cpu.h HAL/inc/alt_types.h \ + drivers/inc/altera_up_avalon_rs232.h HAL/inc/alt_types.h \ + HAL/inc/sys/alt_dev.h drivers/inc/altera_up_avalon_rs232_regs.h \ + HAL/inc/io.h HAL/inc/alt_types.h + +HAL/inc/priv/alt_file.h: + +HAL/inc/sys/alt_dev.h: + +system.h: + +linker.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +HAL/inc/priv/alt_dev_llist.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/alt_types.h: + +UCOSII/inc/os/alt_sem.h: + +UCOSII/inc/priv/alt_sem_ucosii.h: + +HAL/inc/includes.h: + +HAL/inc/os_cpu.h: + +HAL/inc/sys/alt_irq.h: + +HAL/inc/nios2.h: + +HAL/inc/priv/alt_legacy_irq.h: + +system.h: + +HAL/inc/nios2.h: + +HAL/inc/sys/alt_irq.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/sys/alt_alarm.h: + +HAL/inc/sys/alt_llist.h: + +HAL/inc/priv/alt_alarm.h: + +system.h: + +UCOSII/inc/ucos_ii.h: + +UCOSII/inc/os_cfg.h: + +HAL/inc/os_cpu.h: + +HAL/inc/alt_types.h: + +drivers/inc/altera_up_avalon_rs232.h: + +HAL/inc/alt_types.h: + +HAL/inc/sys/alt_dev.h: + +drivers/inc/altera_up_avalon_rs232_regs.h: + +HAL/inc/io.h: + +HAL/inc/alt_types.h: diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/obj/drivers/src/altera_up_avalon_rs232.o b/MCandWifiTestDE0/Software/MCTest_bsp/obj/drivers/src/altera_up_avalon_rs232.o new file mode 100644 index 00000000..f98d689b Binary files /dev/null and b/MCandWifiTestDE0/Software/MCTest_bsp/obj/drivers/src/altera_up_avalon_rs232.o differ diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/public.mk b/MCandWifiTestDE0/Software/MCTest_bsp/public.mk new file mode 100644 index 00000000..b68b630a --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/public.mk @@ -0,0 +1,402 @@ +#------------------------------------------------------------------------------ +# BSP "PUBLIC" MAKEFILE CONTENT +# +# This file is intended to be included in an application or library +# Makefile that is using this BSP. You can create such a Makefile with +# the nios2-app-generate-makefile or nios2-lib-generate-makefile +# commands. +# +# The following variables must be defined before including this file: +# +# ALT_LIBRARY_ROOT_DIR +# Contains the path to the BSP top-level (aka root) directory +#------------------------------------------------------------------------------ + +#------------------------------------------------------------------------------ +# PATHS +#------------------------------------------------------------------------------ + + + +# Path to the provided linker script. +BSP_LINKER_SCRIPT := $(ALT_LIBRARY_ROOT_DIR)/linker.x + +# Include paths: +# The path to root of all header files that a library wishes to make +# available for an application's use is specified here. Note that this +# may not be *all* folders within a hierarchy. For example, if it is +# desired that the application developer type: +# #include +# #include +# With files laid out like this: +# /inc/sockets.h +# /inc/ip/tcpip.h +# +# Then, only /inc need be added to the list of include +# directories. Alternatively, if you wish to be able to directly include +# all files in a hierarchy, separate paths to each folder in that +# hierarchy must be defined. + +# The following are the "base" set of include paths for a BSP. +# These paths are appended to the list that individual software +# components, drivers, etc., add in the generated portion of this +# file (below). +ALT_INCLUDE_DIRS_TO_APPEND += \ + $(ALT_LIBRARY_ROOT_DIR) \ + $(ALT_LIBRARY_ROOT_DIR)/drivers/inc + +# Additions to linker library search-path: +# Here we provide a path to "our self" for the application to construct a +# "-L " out of. This should contain a list of directories, +# relative to the library root, of all directories with .a files to link +# against. +ALT_LIBRARY_DIRS += $(ALT_LIBRARY_ROOT_DIR) + + +#------------------------------------------------------------------------------ +# COMPILATION FLAGS +#------------------------------------------------------------------------------ +# Default C pre-processor flags for a BSP: +ALT_CPPFLAGS += -DSYSTEM_BUS_WIDTH=32 \ + -pipe + + +#------------------------------------------------------------------------------ +# MANAGED CONTENT +# +# All content between the lines "START MANAGED" and "END MANAGED" below is +# generated based on variables in the BSP settings file when the +# nios2-bsp-generate-files command is invoked. If you wish to persist any +# information pertaining to the build process, it is recomended that you +# utilize the BSP settings mechanism to do so. +#------------------------------------------------------------------------------ +#START MANAGED + +# The following TYPE comment allows tools to identify the 'type' of target this +# makefile is associated with. +# TYPE: BSP_PUBLIC_MAKEFILE + +# This following VERSION comment indicates the version of the tool used to +# generate this makefile. A makefile variable is provided for VERSION as well. +# ACDS_VERSION: 12.1sp1 +ACDS_VERSION := 12.1sp1 + +# This following BUILD_NUMBER comment indicates the build number of the tool +# used to generate this makefile. +# BUILD_NUMBER: 243 + +# Quartus Generated JDI File. Required for resolving node instance ID's with +# design component names. +JDI_FILE := C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.jdi + +# Qsys--generated SOPCINFO file. Required for resolving node instance ID's with +# design component names. +SOPCINFO_FILE := C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system.sopcinfo + +# Big-Endian operation. +# setting BIG_ENDIAN is false +ALT_CFLAGS += -EL + +# Path to the provided C language runtime initialization code. +BSP_CRT0 := $(ALT_LIBRARY_ROOT_DIR)/obj/HAL/src/crt0.o + +# Name of BSP library as provided to linker using the "-msys-lib" flag or +# linker script GROUP command. +# setting BSP_SYS_LIB is ucosii_bsp +BSP_SYS_LIB := ucosii_bsp +ELF_PATCH_FLAG += --thread_model ucosii + +# Type identifier of the BSP library +# setting BSP_TYPE is ucosii +ALT_CPPFLAGS += -D__hal__ +BSP_TYPE := ucosii + +# CPU Name +# setting CPU_NAME is cpu +CPU_NAME = cpu +ELF_PATCH_FLAG += --cpu_name $(CPU_NAME) + +# Hardware Divider present. +# setting HARDWARE_DIVIDE is false +ALT_CFLAGS += -mno-hw-div + +# Hardware Multiplier present. +# setting HARDWARE_MULTIPLY is true +ALT_CFLAGS += -mhw-mul + +# Hardware Mulx present. +# setting HARDWARE_MULX is false +ALT_CFLAGS += -mno-hw-mulx + +# Debug Core present. +# setting HAS_DEBUG_CORE is true +CPU_HAS_DEBUG_CORE = 1 + +# Qsys generated design +# setting QSYS is 1 +QSYS := 1 +ELF_PATCH_FLAG += --qsys true + +# Design Name +# setting SOPC_NAME is system +SOPC_NAME := system + +# SopcBuilder Simulation Enabled +# setting SOPC_SIMULATION_ENABLED is false +ELF_PATCH_FLAG += --simulation_enabled false + +# The SOPC System ID +# setting SOPC_SYSID is 0 +SOPC_SYSID_FLAG += --id=0 +ELF_PATCH_FLAG += --id 0 + +# The SOPC System ID Base Address +# setting SOPC_SYSID_BASE_ADDRESS is 0x20010c0 +SOPC_SYSID_FLAG += --sidp=0x20010c0 +ELF_PATCH_FLAG += --sidp 0x20010c0 + +# The SOPC Timestamp +# setting SOPC_TIMESTAMP is 1393886764 +SOPC_SYSID_FLAG += --timestamp=1393886764 +ELF_PATCH_FLAG += --timestamp 1393886764 + +# Small-footprint (polled mode) driver none +# setting altera_avalon_jtag_uart_driver.enable_small_driver is false + +# Enable driver ioctl() support. This feature is not compatible with the +# 'small' driver; ioctl() support will not be compiled if either the UART +# 'enable_small_driver' or HAL 'enable_reduced_device_drivers' settings are +# enabled. none +# setting altera_avalon_uart_driver.enable_ioctl is false + +# Small-footprint (polled mode) driver none +# setting altera_avalon_uart_driver.enable_small_driver is false + +# Build a custom version of newlib with the specified space-separated compiler +# flags. The custom newlib build will be placed in the <bsp root>/newlib +# directory, and will be used only for applications that utilize this BSP. +# setting hal.custom_newlib_flags is none + +# Enable support for a subset of the C++ language. This option increases code +# footprint by adding support for C++ constructors. Certain features, such as +# multiple inheritance and exceptions are not supported. If false, adds +# -DALT_NO_C_PLUS_PLUS to ALT_CPPFLAGS in public.mk, and reduces code +# footprint. none +# setting hal.enable_c_plus_plus is 1 + +# When your application exits, close file descriptors, call C++ destructors, +# etc. Code footprint can be reduced by disabling clean exit. If disabled, adds +# -DALT_NO_CLEAN_EXIT to ALT_CPPFLAGS and -Wl,--defsym, exit=_exit to +# ALT_LDFLAGS in public.mk. none +# setting hal.enable_clean_exit is 1 + +# Add exit() support. This option increases code footprint if your "main()" +# routine does "return" or call "exit()". If false, adds -DALT_NO_EXIT to +# ALT_CPPFLAGS in public.mk, and reduces footprint none +# setting hal.enable_exit is 1 + +# Causes code to be compiled with gprof profiling enabled and the application +# ELF to be linked with the GPROF library. If true, adds -DALT_PROVIDE_GMON to +# ALT_CPPFLAGS and -pg to ALT_CFLAGS in public.mk. none +# setting hal.enable_gprof is 0 + +# Enables lightweight device driver API. This reduces code and data footprint +# by removing the HAL layer that maps device names (e.g. /dev/uart0) to file +# descriptors. Instead, driver routines are called directly. The open(), +# close(), and lseek() routines will always fail if called. The read(), +# write(), fstat(), ioctl(), and isatty() routines only work for the stdio +# devices. If true, adds -DALT_USE_DIRECT_DRIVERS to ALT_CPPFLAGS in public.mk. +# The Altera Host and read-only ZIP file systems can't be used if +# hal.enable_lightweight_device_driver_api is true. +# setting hal.enable_lightweight_device_driver_api is 0 + +# Adds code to emulate multiply and divide instructions in case they are +# executed but aren't present in the CPU. Normally this isn't required because +# the compiler won't use multiply and divide instructions that aren't present +# in the CPU. If false, adds -DALT_NO_INSTRUCTION_EMULATION to ALT_CPPFLAGS in +# public.mk. none +# setting hal.enable_mul_div_emulation is 0 +ALT_CPPFLAGS += -DALT_NO_INSTRUCTION_EMULATION + +# Certain drivers are compiled with reduced functionality to reduce code +# footprint. Not all drivers observe this setting. The altera_avalon_uart and +# altera_avalon_jtag_uart drivers switch from interrupt-driven to polled +# operation. CAUTION: Several device drivers are disabled entirely. These +# include the altera_avalon_cfi_flash, altera_avalon_epcs_flash_controller, and +# altera_avalon_lcd_16207 drivers. This can result in certain API (HAL flash +# access routines) to fail. You can define a symbol provided by each driver to +# prevent it from being removed. If true, adds -DALT_USE_SMALL_DRIVERS to +# ALT_CPPFLAGS in public.mk. none +# setting hal.enable_reduced_device_drivers is 0 + +# Turns on HAL runtime stack checking feature. Enabling this setting causes +# additional code to be placed into each subroutine call to generate an +# exception if a stack collision occurs with the heap or statically allocated +# data. If true, adds -DALT_STACK_CHECK and -mstack-check to ALT_CPPFLAGS in +# public.mk. none +# setting hal.enable_runtime_stack_checking is 0 + +# The BSP is compiled with optimizations to speedup HDL simulation such as +# initializing the cache, clearing the .bss section, and skipping long delay +# loops. If true, adds -DALT_SIM_OPTIMIZE to ALT_CPPFLAGS in public.mk. When +# this setting is true, the BSP shouldn't be used to build applications that +# are expected to run real hardware. +# setting hal.enable_sim_optimize is 0 + +# Causes the small newlib (C library) to be used. This reduces code and data +# footprint at the expense of reduced functionality. Several newlib features +# are removed such as floating-point support in printf(), stdin input routines, +# and buffered I/O. The small C library is not compatible with Micrium +# MicroC/OS-II. If true, adds -msmallc to ALT_LDFLAGS in public.mk. none +# setting hal.enable_small_c_library is 0 + +# Enable SOPC Builder System ID. If a System ID SOPC Builder component is +# connected to the CPU associated with this BSP, it will be enabled in the +# creation of command-line arguments to download an ELF to the target. +# Otherwise, system ID and timestamp values are left out of public.mk for +# application Makefile "download-elf" target definition. With the system ID +# check disabled, the Nios II EDS tools will not automatically ensure that the +# application .elf file (and BSP it is linked against) corresponds to the +# hardware design on the target. If false, adds --accept-bad-sysid to +# SOPC_SYSID_FLAG in public.mk. none +# setting hal.enable_sopc_sysid_check is 1 + +# Enable BSP generation to query if SOPC system is big endian. If true ignores +# export of 'ALT_CFLAGS += -EB' to public.mk if big endian system. If true +# ignores export of 'ALT_CFLAGS += -EL' if little endian system. none +# setting hal.make.ignore_system_derived.big_endian is 0 + +# Enable BSP generation to query if SOPC system has a debug core present. If +# true ignores export of 'CPU_HAS_DEBUG_CORE = 1' to public.mk if a debug core +# is found in the system. If true ignores export of 'CPU_HAS_DEBUG_CORE = 0' if +# no debug core is found in the system. none +# setting hal.make.ignore_system_derived.debug_core_present is 0 + +# Enable BSP generation to query if SOPC system has FPU present. If true +# ignores export of 'ALT_CFLAGS += -mhard-float' to public.mk if FPU is found +# in the system. If true ignores export of 'ALT_CFLAGS += -mhard-soft' if FPU +# is not found in the system. none +# setting hal.make.ignore_system_derived.fpu_present is 0 + +# Enable BSP generation to query if SOPC system has hardware divide present. If +# true ignores export of 'ALT_CFLAGS += -mno-hw-div' to public.mk if no +# division is found in system. If true ignores export of 'ALT_CFLAGS += +# -mhw-div' if division is found in the system. none +# setting hal.make.ignore_system_derived.hardware_divide_present is 0 + +# Enable BSP generation to query if SOPC system floating point custom +# instruction with a divider is present. If true ignores export of 'ALT_CFLAGS +# += -mcustom-fpu-cfg=60-2' and 'ALT_LDFLAGS += -mcustom-fpu-cfg=60-2' to +# public.mk if the custom instruction is found in the system. none +# setting hal.make.ignore_system_derived.hardware_fp_cust_inst_divider_present is 0 + +# Enable BSP generation to query if SOPC system floating point custom +# instruction without a divider is present. If true ignores export of +# 'ALT_CFLAGS += -mcustom-fpu-cfg=60-1' and 'ALT_LDFLAGS += +# -mcustom-fpu-cfg=60-1' to public.mk if the custom instruction is found in the +# system. none +# setting hal.make.ignore_system_derived.hardware_fp_cust_inst_no_divider_present is 0 + +# Enable BSP generation to query if SOPC system has multiplier present. If true +# ignores export of 'ALT_CFLAGS += -mno-hw-mul' to public.mk if no multiplier +# is found in the system. If true ignores export of 'ALT_CFLAGS += -mhw-mul' if +# multiplier is found in the system. none +# setting hal.make.ignore_system_derived.hardware_multiplier_present is 0 + +# Enable BSP generation to query if SOPC system has hardware mulx present. If +# true ignores export of 'ALT_CFLAGS += -mno-hw-mulx' to public.mk if no mulx +# is found in the system. If true ignores export of 'ALT_CFLAGS += -mhw-mulx' +# if mulx is found in the system. none +# setting hal.make.ignore_system_derived.hardware_mulx_present is 0 + +# Enable BSP generation to query if SOPC system has simulation enabled. If true +# ignores export of 'ELF_PATCH_FLAG += --simulation_enabled' to public.mk. none +# setting hal.make.ignore_system_derived.sopc_simulation_enabled is 0 + +# Enable BSP generation to query SOPC system for system ID base address. If +# true ignores export of 'SOPC_SYSID_FLAG += --sidp=
' and +# 'ELF_PATCH_FLAG += --sidp=
' to public.mk. none +# setting hal.make.ignore_system_derived.sopc_system_base_address is 0 + +# Enable BSP generation to query SOPC system for system ID. If true ignores +# export of 'SOPC_SYSID_FLAG += --id=' and 'ELF_PATCH_FLAG += +# --id=' to public.mk. none +# setting hal.make.ignore_system_derived.sopc_system_id is 0 + +# Enable BSP generation to query SOPC system for system timestamp. If true +# ignores export of 'SOPC_SYSID_FLAG += --timestamp=' and +# 'ELF_PATCH_FLAG += --timestamp=' to public.mk. none +# setting hal.make.ignore_system_derived.sopc_system_timestamp is 0 + +# Slave descriptor of STDERR character-mode device. This setting is used by the +# ALT_STDERR family of defines in system.h. none +# setting hal.stderr is jtag_uart_0 +ELF_PATCH_FLAG += --stderr_dev jtag_uart_0 + +# Slave descriptor of STDIN character-mode device. This setting is used by the +# ALT_STDIN family of defines in system.h. none +# setting hal.stdin is jtag_uart_0 +ELF_PATCH_FLAG += --stdin_dev jtag_uart_0 + +# Slave descriptor of STDOUT character-mode device. This setting is used by the +# ALT_STDOUT family of defines in system.h. none +# setting hal.stdout is jtag_uart_0 +ELF_PATCH_FLAG += --stdout_dev jtag_uart_0 + + +#------------------------------------------------------------------------------ +# SOFTWARE COMPONENT & DRIVER INCLUDE PATHS +#------------------------------------------------------------------------------ + +ALT_INCLUDE_DIRS += $(ALT_LIBRARY_ROOT_DIR)/UCOSII/inc +ALT_INCLUDE_DIRS += $(ALT_LIBRARY_ROOT_DIR)/HAL/inc + +#------------------------------------------------------------------------------ +# SOFTWARE COMPONENT & DRIVER PRODUCED ALT_CPPFLAGS ADDITIONS +#------------------------------------------------------------------------------ + +ALT_CPPFLAGS += -D__ucosii__ + +#END MANAGED + + +#------------------------------------------------------------------------------ +# LIBRARY INFORMATION +#------------------------------------------------------------------------------ +# Assemble the name of the BSP *.a file using the BSP library name +# (BSP_SYS_LIB) in generated content above. +BSP_LIB := lib$(BSP_SYS_LIB).a + +# Additional libraries to link against: +# An application including this file will prefix each library with "-l". +# For example, to include the Newlib math library "m" is included, which +# becomes "-lm" when linking the application. +ALT_LIBRARY_NAMES += m + +# Additions to linker dependencies: +# An application Makefile will typically add these directly to the list +# of dependencies required to build the executable target(s). The BSP +# library (*.a) file is specified here. +ALT_LDDEPS += $(ALT_LIBRARY_ROOT_DIR)/$(BSP_LIB) + +# Is this library "Makeable"? +# Add to list of root library directories that support running 'make' +# to build them. Because libraries may or may not have a Makefile in their +# root, appending to this variable tells an application to run 'make' in +# the library root to build/update this library. +MAKEABLE_LIBRARY_ROOT_DIRS += $(ALT_LIBRARY_ROOT_DIR) + +# Additional Assembler Flags +# -gdwarf2 flag is required for stepping through assembly code +ALT_ASFLAGS += -gdwarf2 + +#------------------------------------------------------------------------------ +# FINAL INCLUDE PATH LIST +#------------------------------------------------------------------------------ +# Append static include paths to paths specified by OS/driver/sw package +# additions to the BSP thus giving them precedence in case a BSP addition +# is attempting to override BSP sources. +ALT_INCLUDE_DIRS += $(ALT_INCLUDE_DIRS_TO_APPEND) + + + diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/settings.bsp b/MCandWifiTestDE0/Software/MCTest_bsp/settings.bsp new file mode 100644 index 00000000..cceb92ae --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/settings.bsp @@ -0,0 +1,1807 @@ + + + ucosii + default + 3-Mar-2014 4:25:26 PM + 1393889126953 + C:\Users\gongal\NewRepARCap\MCandWifiTestDE0\Software\MCTest_bsp + settings.bsp + C:\Users\gongal\NewRepARCap\MCandWifiTestDE0\system.sopcinfo + default + cpu + 1.9 + + hal.sys_clk_timer + ALT_SYS_CLK + UnquotedString + sys_clk_timer + none + system_h_define + Slave descriptor of the system clock timer device. This device provides a periodic interrupt ("tick") and is typically required for RTOS use. This setting defines the value of ALT_SYS_CLK in system.h. + none + false + common + + + hal.timestamp_timer + ALT_TIMESTAMP_CLK + UnquotedString + none + none + system_h_define + Slave descriptor of timestamp timer device. This device is used by Altera HAL timestamp drivers for high-resolution time measurement. This setting defines the value of ALT_TIMESTAMP_CLK in system.h. + none + false + common + + + hal.max_file_descriptors + ALT_MAX_FD + DecimalNumber + 32 + 32 + system_h_define + Determines the number of file descriptors statically allocated. This setting defines the value of ALT_MAX_FD in system.h. + If hal.enable_lightweight_device_driver_api is true, there are no file descriptors so this setting is ignored. If hal.enable_lightweight_device_driver_api is false, this setting must be at least 4 because HAL needs a file descriptor for /dev/null, /dev/stdin, /dev/stdout, and /dev/stderr. + false + + + + hal.enable_instruction_related_exceptions_api + ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API + BooleanDefineOnly + false + false + system_h_define + Enables API for registering handlers to service instruction-related exceptions. Enabling this setting increases the size of the exception entry code. + These exception types can be generated if various processor options are enabled, such as the MMU, MPU, or other advanced exception types. + false + + + + hal.linker.allow_code_at_reset + ALT_ALLOW_CODE_AT_RESET + Boolean + 1 + 0 + none + Indicates if initialization code is allowed at the reset address. If true, defines the macro ALT_ALLOW_CODE_AT_RESET in linker.h. + If true, defines the macro ALT_ALLOW_CODE_AT_RESET in linker.h. This setting is typically false if an external bootloader (e.g. flash bootloader) is present. + false + + + + hal.linker.enable_alt_load + NONE + Boolean + 1 + 0 + none + Enables the alt_load() facility. The alt_load() facility copies sections from the .text memory into RAM. If true, this setting sets up the VMA/LMA of sections in linker.x to allow them to be loaded into the .text memory. + This setting is typically false if an external bootloader (e.g. flash bootloader) is present. + false + + + + hal.linker.enable_alt_load_copy_rodata + NONE + Boolean + 0 + 0 + none + Causes the alt_load() facility to copy the .rodata section. If true, this setting defines the macro ALT_LOAD_COPY_RODATA in linker.h. + none + false + + + + hal.linker.enable_alt_load_copy_rwdata + NONE + Boolean + 1 + 0 + none + Causes the alt_load() facility to copy the .rwdata section. If true, this setting defines the macro ALT_LOAD_COPY_RWDATA in linker.h. + none + false + + + + hal.linker.enable_alt_load_copy_exceptions + NONE + Boolean + 0 + 0 + none + Causes the alt_load() facility to copy the .exceptions section. If true, this setting defines the macro ALT_LOAD_COPY_EXCEPTIONS in linker.h. + none + false + + + + hal.linker.enable_exception_stack + NONE + Boolean + 0 + 0 + none + Enables use of a separate exception stack. If true, defines the macro ALT_EXCEPTION_STACK in linker.h, adds a memory region called exception_stack to linker.x, and provides the symbols __alt_exception_stack_pointer and __alt_exception_stack_limit in linker.x. + The hal.linker.exception_stack_size and hal.linker.exception_stack_memory_region_name settings must also be valid. This setting must be false for MicroC/OS-II BSPs. The exception stack can be used to improve interrupt and other exception performance if the EIC is *not* used. + false + common + + + hal.linker.exception_stack_size + NONE + DecimalNumber + 1024 + 1024 + none + Size of the exception stack in bytes. + Only used if hal.linker.enable_exception_stack is true. + false + common + + + hal.linker.exception_stack_memory_region_name + NONE + UnquotedString + sdram + none + none + Name of the existing memory region that will be divided up to create the 'exception_stack' memory region. The selected region name will be adjusted automatically when the BSP is generated to create the 'exception_stack' memory region. + Only used if hal.linker.enable_exception_stack is true. + false + common + + + hal.linker.enable_interrupt_stack + NONE + Boolean + 0 + 0 + none + Enables use of a separate interrupt stack. If true, defines the macro ALT_INTERRUPT_STACK in linker.h, adds a memory region called interrupt_stack to linker.x, and provides the symbols __alt_interrupt_stack_pointer and __alt_interrupt_stack_limit in linker.x. + The hal.linker.interrupt_stack_size and hal.linker.interrupt_stack_memory_region_name settings must also be valid. This setting must be false for MicroC/OS-II BSPs. Only enable if the EIC is used exclusively. The exception stack can be used to improve interrupt and other exception performance if the EIC is *not* used. + false + common + + + hal.linker.interrupt_stack_size + NONE + DecimalNumber + 1024 + 1024 + none + Size of the interrupt stack in bytes. + Only used if hal.linker.enable_interrupt_stack is true. + false + common + + + hal.linker.interrupt_stack_memory_region_name + NONE + UnquotedString + sdram + none + none + Name of the existing memory region that will be divided up to create the 'interrupt_stack' memory region. The selected region name will be adjusted automatically when the BSP is generated to create the 'interrupt_stack' memory region. + Only used if hal.linker.enable_interrupt_stack is true. + false + common + + + hal.stdin + NONE + UnquotedString + jtag_uart_0 + none + system_h_define + Slave descriptor of STDIN character-mode device. This setting is used by the ALT_STDIN family of defines in system.h. + none + false + common + + + hal.stdout + NONE + UnquotedString + jtag_uart_0 + none + system_h_define + Slave descriptor of STDOUT character-mode device. This setting is used by the ALT_STDOUT family of defines in system.h. + none + false + common + + + hal.stderr + NONE + UnquotedString + jtag_uart_0 + none + system_h_define + Slave descriptor of STDERR character-mode device. This setting is used by the ALT_STDERR family of defines in system.h. + none + false + common + + + hal.log_port + NONE + UnquotedString + none + none + public_mk_define + Slave descriptor of debug logging character-mode device. If defined, it enables extra debug messages in the HAL source. This setting is used by the ALT_LOG_PORT family of defines in system.h. + none + false + none + + + hal.make.build_pre_process + BUILD_PRE_PROCESS + UnquotedString + none + none + makefile_variable + Command executed before BSP built. + none + false + none + + + hal.make.ar_pre_process + AR_PRE_PROCESS + UnquotedString + none + none + makefile_variable + Command executed before archiver execution. + none + false + none + + + hal.make.bsp_cflags_defined_symbols + BSP_CFLAGS_DEFINED_SYMBOLS + UnquotedString + none + none + makefile_variable + Preprocessor macros to define. A macro definition in this setting has the same effect as a "#define" in source code. Adding "-DALT_DEBUG" to this setting has the same effect as "#define ALT_DEBUG" in a souce file. Adding "-DFOO=1" to this setting is equivalent to the macro "#define FOO 1" in a source file. Macros defined with this setting are applied to all .S, .c, and C++ files in the BSP. This setting defines the value of BSP_CFLAGS_DEFINED_SYMBOLS in the BSP Makefile. + none + false + none + + + hal.make.ar_post_process + AR_POST_PROCESS + UnquotedString + none + none + makefile_variable + Command executed after archiver execution. + none + false + none + + + hal.make.as + AS + UnquotedString + nios2-elf-gcc + nios2-elf-gcc + makefile_variable + Assembler command. Note that CC is used for .S files. + none + false + none + + + hal.make.build_post_process + BUILD_POST_PROCESS + UnquotedString + none + none + makefile_variable + Command executed after BSP built. + none + false + none + + + hal.make.bsp_cflags_debug + BSP_CFLAGS_DEBUG + UnquotedString + -g + -g + makefile_variable + C/C++ compiler debug level. '-g' provides the default set of debug symbols typically required to debug a typical application. Omitting '-g' removes debug symbols from the ELF. This setting defines the value of BSP_CFLAGS_DEBUG in Makefile. + none + false + common + + + hal.make.ar + AR + UnquotedString + nios2-elf-ar + nios2-elf-ar + makefile_variable + Archiver command. Creates library files. + none + false + none + + + hal.make.rm + RM + UnquotedString + rm -f + rm -f + makefile_variable + Command used to remove files during 'clean' target. + none + false + none + + + hal.make.cxx_pre_process + CXX_PRE_PROCESS + UnquotedString + none + none + makefile_variable + Command executed before each C++ file is compiled. + none + false + none + + + hal.make.bsp_cflags_warnings + BSP_CFLAGS_WARNINGS + UnquotedString + -Wall + -Wall + makefile_variable + C/C++ compiler warning level. "-Wall" is commonly used.This setting defines the value of BSP_CFLAGS_WARNINGS in Makefile. + none + false + none + + + hal.make.bsp_arflags + BSP_ARFLAGS + UnquotedString + -src + -src + makefile_variable + Custom flags only passed to the archiver. This content of this variable is directly passed to the archiver rather than the more standard "ARFLAGS". The reason for this is that GNU Make assumes some default content in ARFLAGS. This setting defines the value of BSP_ARFLAGS in Makefile. + none + false + none + + + hal.make.bsp_cflags_optimization + BSP_CFLAGS_OPTIMIZATION + UnquotedString + -O0 + -O0 + makefile_variable + C/C++ compiler optimization level. "-O0" = no optimization,"-O2" = "normal" optimization, etc. "-O0" is recommended for code that you want to debug since compiler optimization can remove variables and produce non-sequential execution of code while debugging. This setting defines the value of BSP_CFLAGS_OPTIMIZATION in Makefile. + none + false + common + + + hal.make.as_post_process + AS_POST_PROCESS + UnquotedString + none + none + makefile_variable + Command executed after each assembly file is compiled. + none + false + none + + + hal.make.cc_pre_process + CC_PRE_PROCESS + UnquotedString + none + none + makefile_variable + Command executed before each .c/.S file is compiled. + none + false + none + + + hal.make.bsp_asflags + BSP_ASFLAGS + UnquotedString + -Wa,-gdwarf2 + -Wa,-gdwarf2 + makefile_variable + Custom flags only passed to the assembler. This setting defines the value of BSP_ASFLAGS in Makefile. + none + false + none + + + hal.make.as_pre_process + AS_PRE_PROCESS + UnquotedString + none + none + makefile_variable + Command executed before each assembly file is compiled. + none + false + none + + + hal.make.bsp_cflags_undefined_symbols + BSP_CFLAGS_UNDEFINED_SYMBOLS + UnquotedString + none + none + makefile_variable + Preprocessor macros to undefine. Undefined macros are similar to defined macros, but replicate the "#undef" directive in source code. To undefine the macro FOO use the syntax "-u FOO" in this setting. This is equivalent to "#undef FOO" in a source file. Note: the syntax differs from macro definition (there is a space, i.e. "-u FOO" versus "-DFOO"). Macros defined with this setting are applied to all .S, .c, and C++ files in the BSP. This setting defines the value of BSP_CFLAGS_UNDEFINED_SYMBOLS in the BSP Makefile. + none + false + none + + + hal.make.cc_post_process + CC_POST_PROCESS + UnquotedString + none + none + makefile_variable + Command executed after each .c/.S file is compiled. + none + false + none + + + hal.make.cxx_post_process + CXX_POST_PROCESS + UnquotedString + none + none + makefile_variable + Command executed before each C++ file is compiled. + none + false + none + + + hal.make.cc + CC + UnquotedString + nios2-elf-gcc -xc + nios2-elf-gcc -xc + makefile_variable + C compiler command. + none + false + none + + + hal.make.bsp_cxx_flags + BSP_CXXFLAGS + UnquotedString + none + none + makefile_variable + Custom flags only passed to the C++ compiler. This setting defines the value of BSP_CXXFLAGS in Makefile. + none + false + none + + + hal.make.bsp_inc_dirs + BSP_INC_DIRS + UnquotedString + none + none + makefile_variable + Space separated list of extra include directories to scan for header files. Directories are relative to the top-level BSP directory. The -I prefix's added by the makefile so don't add it here. This setting defines the value of BSP_INC_DIRS in Makefile. + none + false + none + + + hal.make.cxx + CXX + UnquotedString + nios2-elf-gcc -xc++ + nios2-elf-gcc -xc++ + makefile_variable + C++ compiler command. + none + false + none + + + hal.make.bsp_cflags_user_flags + BSP_CFLAGS_USER_FLAGS + UnquotedString + none + none + makefile_variable + Custom flags passed to the compiler when compiling C, C++, and .S files. This setting defines the value of BSP_CFLAGS_USER_FLAGS in Makefile. + none + false + none + + + hal.make.ignore_system_derived.sopc_system_id + NONE + Boolean + 0 + 0 + public_mk_define + Enable BSP generation to query SOPC system for system ID. If true ignores export of 'SOPC_SYSID_FLAG += --id=<sysid>' and 'ELF_PATCH_FLAG += --id=<sysid>' to public.mk. + none + false + none + + + hal.make.ignore_system_derived.sopc_system_timestamp + NONE + Boolean + 0 + 0 + public_mk_define + Enable BSP generation to query SOPC system for system timestamp. If true ignores export of 'SOPC_SYSID_FLAG += --timestamp=<timestamp>' and 'ELF_PATCH_FLAG += --timestamp=<timestamp>' to public.mk. + none + false + none + + + hal.make.ignore_system_derived.sopc_system_base_address + NONE + Boolean + 0 + 0 + public_mk_define + Enable BSP generation to query SOPC system for system ID base address. If true ignores export of 'SOPC_SYSID_FLAG += --sidp=<address>' and 'ELF_PATCH_FLAG += --sidp=<address>' to public.mk. + none + false + none + + + hal.make.ignore_system_derived.sopc_simulation_enabled + NONE + Boolean + 0 + 0 + public_mk_define + Enable BSP generation to query if SOPC system has simulation enabled. If true ignores export of 'ELF_PATCH_FLAG += --simulation_enabled' to public.mk. + none + false + none + + + hal.make.ignore_system_derived.fpu_present + NONE + Boolean + 0 + 0 + public_mk_define + Enable BSP generation to query if SOPC system has FPU present. If true ignores export of 'ALT_CFLAGS += -mhard-float' to public.mk if FPU is found in the system. If true ignores export of 'ALT_CFLAGS += -mhard-soft' if FPU is not found in the system. + none + false + none + + + hal.make.ignore_system_derived.hardware_multiplier_present + NONE + Boolean + 0 + 0 + public_mk_define + Enable BSP generation to query if SOPC system has multiplier present. If true ignores export of 'ALT_CFLAGS += -mno-hw-mul' to public.mk if no multiplier is found in the system. If true ignores export of 'ALT_CFLAGS += -mhw-mul' if multiplier is found in the system. + none + false + none + + + hal.make.ignore_system_derived.hardware_mulx_present + NONE + Boolean + 0 + 0 + public_mk_define + Enable BSP generation to query if SOPC system has hardware mulx present. If true ignores export of 'ALT_CFLAGS += -mno-hw-mulx' to public.mk if no mulx is found in the system. If true ignores export of 'ALT_CFLAGS += -mhw-mulx' if mulx is found in the system. + none + false + none + + + hal.make.ignore_system_derived.hardware_divide_present + NONE + Boolean + 0 + 0 + public_mk_define + Enable BSP generation to query if SOPC system has hardware divide present. If true ignores export of 'ALT_CFLAGS += -mno-hw-div' to public.mk if no division is found in system. If true ignores export of 'ALT_CFLAGS += -mhw-div' if division is found in the system. + none + false + none + + + hal.make.ignore_system_derived.debug_core_present + NONE + Boolean + 0 + 0 + public_mk_define + Enable BSP generation to query if SOPC system has a debug core present. If true ignores export of 'CPU_HAS_DEBUG_CORE = 1' to public.mk if a debug core is found in the system. If true ignores export of 'CPU_HAS_DEBUG_CORE = 0' if no debug core is found in the system. + none + false + none + + + hal.make.ignore_system_derived.big_endian + NONE + Boolean + 0 + 0 + public_mk_define + Enable BSP generation to query if SOPC system is big endian. If true ignores export of 'ALT_CFLAGS += -EB' to public.mk if big endian system. If true ignores export of 'ALT_CFLAGS += -EL' if little endian system. + none + false + none + + + hal.make.ignore_system_derived.hardware_fp_cust_inst_divider_present + NONE + Boolean + 0 + 0 + public_mk_define + Enable BSP generation to query if SOPC system floating point custom instruction with a divider is present. If true ignores export of 'ALT_CFLAGS += -mcustom-fpu-cfg=60-2' and 'ALT_LDFLAGS += -mcustom-fpu-cfg=60-2' to public.mk if the custom instruction is found in the system. + none + false + none + + + hal.make.ignore_system_derived.hardware_fp_cust_inst_no_divider_present + NONE + Boolean + 0 + 0 + public_mk_define + Enable BSP generation to query if SOPC system floating point custom instruction without a divider is present. If true ignores export of 'ALT_CFLAGS += -mcustom-fpu-cfg=60-1' and 'ALT_LDFLAGS += -mcustom-fpu-cfg=60-1' to public.mk if the custom instruction is found in the system. + none + false + none + + + hal.enable_exit + ALT_NO_EXIT + Boolean + 1 + 1 + public_mk_define + Add exit() support. This option increases code footprint if your "main()" routine does "return" or call "exit()". If false, adds -DALT_NO_EXIT to ALT_CPPFLAGS in public.mk, and reduces footprint + none + false + none + + + hal.enable_small_c_library + NONE + Boolean + 0 + 0 + public_mk_define + Causes the small newlib (C library) to be used. This reduces code and data footprint at the expense of reduced functionality. Several newlib features are removed such as floating-point support in printf(), stdin input routines, and buffered I/O. The small C library is not compatible with Micrium MicroC/OS-II. If true, adds -msmallc to ALT_LDFLAGS in public.mk. + none + false + common + + + hal.enable_clean_exit + ALT_NO_CLEAN_EXIT + Boolean + 1 + 1 + public_mk_define + When your application exits, close file descriptors, call C++ destructors, etc. Code footprint can be reduced by disabling clean exit. If disabled, adds -DALT_NO_CLEAN_EXIT to ALT_CPPFLAGS and -Wl,--defsym, exit=_exit to ALT_LDFLAGS in public.mk. + none + false + none + + + hal.enable_runtime_stack_checking + ALT_STACK_CHECK + Boolean + 0 + 0 + public_mk_define + Turns on HAL runtime stack checking feature. Enabling this setting causes additional code to be placed into each subroutine call to generate an exception if a stack collision occurs with the heap or statically allocated data. If true, adds -DALT_STACK_CHECK and -mstack-check to ALT_CPPFLAGS in public.mk. + none + false + none + + + hal.enable_gprof + ALT_PROVIDE_GMON + Boolean + 0 + 0 + public_mk_define + Causes code to be compiled with gprof profiling enabled and the application ELF to be linked with the GPROF library. If true, adds -DALT_PROVIDE_GMON to ALT_CPPFLAGS and -pg to ALT_CFLAGS in public.mk. + none + false + common + + + hal.enable_c_plus_plus + ALT_NO_C_PLUS_PLUS + Boolean + 1 + 1 + public_mk_define + Enable support for a subset of the C++ language. This option increases code footprint by adding support for C++ constructors. Certain features, such as multiple inheritance and exceptions are not supported. If false, adds -DALT_NO_C_PLUS_PLUS to ALT_CPPFLAGS in public.mk, and reduces code footprint. + none + false + none + + + hal.enable_reduced_device_drivers + ALT_USE_SMALL_DRIVERS + Boolean + 0 + 0 + public_mk_define + Certain drivers are compiled with reduced functionality to reduce code footprint. Not all drivers observe this setting. The altera_avalon_uart and altera_avalon_jtag_uart drivers switch from interrupt-driven to polled operation. CAUTION: Several device drivers are disabled entirely. These include the altera_avalon_cfi_flash, altera_avalon_epcs_flash_controller, and altera_avalon_lcd_16207 drivers. This can result in certain API (HAL flash access routines) to fail. You can define a symbol provided by each driver to prevent it from being removed. If true, adds -DALT_USE_SMALL_DRIVERS to ALT_CPPFLAGS in public.mk. + none + false + common + + + hal.enable_lightweight_device_driver_api + ALT_USE_DIRECT_DRIVERS + Boolean + 0 + 0 + public_mk_define + Enables lightweight device driver API. This reduces code and data footprint by removing the HAL layer that maps device names (e.g. /dev/uart0) to file descriptors. Instead, driver routines are called directly. The open(), close(), and lseek() routines will always fail if called. The read(), write(), fstat(), ioctl(), and isatty() routines only work for the stdio devices. If true, adds -DALT_USE_DIRECT_DRIVERS to ALT_CPPFLAGS in public.mk. + The Altera Host and read-only ZIP file systems can't be used if hal.enable_lightweight_device_driver_api is true. + false + none + + + hal.enable_mul_div_emulation + ALT_NO_INSTRUCTION_EMULATION + Boolean + 0 + 0 + public_mk_define + Adds code to emulate multiply and divide instructions in case they are executed but aren't present in the CPU. Normally this isn't required because the compiler won't use multiply and divide instructions that aren't present in the CPU. If false, adds -DALT_NO_INSTRUCTION_EMULATION to ALT_CPPFLAGS in public.mk. + none + false + none + + + hal.enable_sim_optimize + ALT_SIM_OPTIMIZE + Boolean + 0 + 0 + public_mk_define + The BSP is compiled with optimizations to speedup HDL simulation such as initializing the cache, clearing the .bss section, and skipping long delay loops. If true, adds -DALT_SIM_OPTIMIZE to ALT_CPPFLAGS in public.mk. + When this setting is true, the BSP shouldn't be used to build applications that are expected to run real hardware. + false + common + + + hal.enable_sopc_sysid_check + NONE + Boolean + 1 + 1 + public_mk_define + Enable SOPC Builder System ID. If a System ID SOPC Builder component is connected to the CPU associated with this BSP, it will be enabled in the creation of command-line arguments to download an ELF to the target. Otherwise, system ID and timestamp values are left out of public.mk for application Makefile "download-elf" target definition. With the system ID check disabled, the Nios II EDS tools will not automatically ensure that the application .elf file (and BSP it is linked against) corresponds to the hardware design on the target. If false, adds --accept-bad-sysid to SOPC_SYSID_FLAG in public.mk. + none + false + none + + + hal.custom_newlib_flags + CUSTOM_NEWLIB_FLAGS + UnquotedString + none + none + public_mk_define + Build a custom version of newlib with the specified space-separated compiler flags. + The custom newlib build will be placed in the &lt;bsp root>/newlib directory, and will be used only for applications that utilize this BSP. + false + none + + + hal.log_flags + ALT_LOG_FLAGS + DecimalNumber + 0 + 0 + public_mk_define + The value is assigned to ALT_LOG_FLAGS in the generated public.mk. See hal.log_port setting description. Values can be -1 through 3. + hal.log_port must be set for this to be used. + false + none + + + ucosii.os_max_tasks + OS_MAX_TASKS + DecimalNumber + 10 + 10 + system_h_define + Maximum number of tasks + none + false + + + + ucosii.os_lowest_prio + OS_LOWEST_PRIO + DecimalNumber + 20 + 20 + system_h_define + Lowest assignable priority + none + false + + + + ucosii.os_thread_safe_newlib + OS_THREAD_SAFE_NEWLIB + Boolean + 1 + 1 + system_h_define + Thread safe C library + none + false + + + + ucosii.miscellaneous.os_arg_chk_en + OS_ARG_CHK_EN + Boolean + 1 + 1 + system_h_define + Enable argument checking + none + false + + + + ucosii.miscellaneous.os_cpu_hooks_en + OS_CPU_HOOKS_EN + Boolean + 1 + 1 + system_h_define + Enable uCOS-II hooks + none + false + + + + ucosii.miscellaneous.os_debug_en + OS_DEBUG_EN + Boolean + 1 + 1 + system_h_define + Enable debug variables + none + false + + + + ucosii.miscellaneous.os_sched_lock_en + OS_SCHED_LOCK_EN + Boolean + 1 + 1 + system_h_define + Include code for OSSchedLock() and OSSchedUnlock() + none + false + + + + ucosii.miscellaneous.os_task_stat_en + OS_TASK_STAT_EN + Boolean + 1 + 1 + system_h_define + Enable statistics task + none + false + + + + ucosii.miscellaneous.os_task_stat_stk_chk_en + OS_TASK_STAT_STK_CHK_EN + Boolean + 1 + 1 + system_h_define + Check task stacks from statistics task + none + false + + + + ucosii.miscellaneous.os_tick_step_en + OS_TICK_STEP_EN + Boolean + 1 + 1 + system_h_define + Enable tick stepping feature for uCOS-View + none + false + + + + ucosii.miscellaneous.os_event_name_size + OS_EVENT_NAME_SIZE + DecimalNumber + 32 + 32 + system_h_define + Size of name of Event Control Block groups + none + false + + + + ucosii.miscellaneous.os_max_events + OS_MAX_EVENTS + DecimalNumber + 60 + 60 + system_h_define + Maximum number of event control blocks + none + false + + + + ucosii.miscellaneous.os_task_idle_stk_size + OS_TASK_IDLE_STK_SIZE + DecimalNumber + 512 + 512 + system_h_define + Idle task stack size + none + false + + + + ucosii.miscellaneous.os_task_stat_stk_size + OS_TASK_STAT_STK_SIZE + DecimalNumber + 512 + 512 + system_h_define + Statistics task stack size + none + false + + + + ucosii.task.os_task_change_prio_en + OS_TASK_CHANGE_PRIO_EN + Boolean + 1 + 1 + system_h_define + Include code for OSTaskChangePrio() + none + false + + + + ucosii.task.os_task_create_en + OS_TASK_CREATE_EN + Boolean + 1 + 1 + system_h_define + Include code for OSTaskCreate() + none + false + + + + ucosii.task.os_task_create_ext_en + OS_TASK_CREATE_EXT_EN + Boolean + 1 + 1 + system_h_define + Include code for OSTaskCreateExt() + none + false + + + + ucosii.task.os_task_del_en + OS_TASK_DEL_EN + Boolean + 1 + 1 + system_h_define + Include code for OSTaskDel() + none + false + + + + ucosii.task.os_task_name_size + OS_TASK_NAME_SIZE + DecimalNumber + 32 + 32 + system_h_define + Size of task name + none + false + + + + ucosii.task.os_task_profile_en + OS_TASK_PROFILE_EN + Boolean + 1 + 1 + system_h_define + Include data structure for run-time task profiling + none + false + + + + ucosii.task.os_task_query_en + OS_TASK_QUERY_EN + Boolean + 1 + 1 + system_h_define + Include code for OSTaskQuery + none + false + + + + ucosii.task.os_task_suspend_en + OS_TASK_SUSPEND_EN + Boolean + 1 + 1 + system_h_define + Include code for OSTaskSuspend() and OSTaskResume() + none + false + + + + ucosii.task.os_task_sw_hook_en + OS_TASK_SW_HOOK_EN + Boolean + 1 + 1 + system_h_define + Include code for OSTaskSwHook() + none + false + + + + ucosii.time.os_time_tick_hook_en + OS_TIME_TICK_HOOK_EN + Boolean + 1 + 1 + system_h_define + Include code for OSTimeTickHook() + none + false + + + + ucosii.time.os_time_dly_resume_en + OS_TIME_DLY_RESUME_EN + Boolean + 1 + 1 + system_h_define + Include code for OSTimeDlyResume() + none + false + + + + ucosii.time.os_time_dly_hmsm_en + OS_TIME_DLY_HMSM_EN + Boolean + 1 + 1 + system_h_define + Include code for OSTimeDlyHMSM() + none + false + + + + ucosii.time.os_time_get_set_en + OS_TIME_GET_SET_EN + Boolean + 1 + 1 + system_h_define + Include code for OSTimeGet and OSTimeSet() + none + false + + + + ucosii.os_flag_en + OS_FLAG_EN + Boolean + 1 + 1 + system_h_define + Enable code for Event Flags. CAUTION: This is required by the HAL and many Altera device drivers. + none + false + + + + ucosii.event_flag.os_flag_wait_clr_en + OS_FLAG_WAIT_CLR_EN + Boolean + 1 + 1 + system_h_define + Include code for Wait on Clear Event Flags. CAUTION: This is required by the HAL and many Altera device drivers. + none + false + + + + ucosii.event_flag.os_flag_accept_en + OS_FLAG_ACCEPT_EN + Boolean + 1 + 1 + system_h_define + Include code for OSFlagAccept(). CAUTION: This is required by the HAL and many Altera device drivers. + none + false + + + + ucosii.event_flag.os_flag_del_en + OS_FLAG_DEL_EN + Boolean + 1 + 1 + system_h_define + Include code for OSFlagDel(). CAUTION: This is required by the HAL and many Altera device drivers. + none + false + + + + ucosii.event_flag.os_flag_query_en + OS_FLAG_QUERY_EN + Boolean + 1 + 1 + system_h_define + Include code for OSFlagQuery(). CAUTION: This is required by the HAL and many Altera device drivers. + none + false + + + + ucosii.event_flag.os_flag_name_size + OS_FLAG_NAME_SIZE + DecimalNumber + 32 + 32 + system_h_define + Size of name of Event Flags group. CAUTION: This is required by the HAL and many Altera device drivers; use caution in reducing this value. + none + false + + + + ucosii.event_flag.os_flags_nbits + OS_FLAGS_NBITS + DecimalNumber + 16 + 16 + system_h_define + Event Flag bits (8,16,32). CAUTION: This is required by the HAL and many Altera device drivers; use caution in changing this value. + none + false + + + + ucosii.event_flag.os_max_flags + OS_MAX_FLAGS + DecimalNumber + 20 + 20 + system_h_define + Maximum number of Event Flags groups. CAUTION: This is required by the HAL and many Altera device drivers; use caution in reducing this value. + none + false + + + + ucosii.os_mutex_en + OS_MUTEX_EN + Boolean + 1 + 1 + system_h_define + Enable code for Mutex Semaphores + none + false + + + + ucosii.mutex.os_mutex_accept_en + OS_MUTEX_ACCEPT_EN + Boolean + 1 + 1 + system_h_define + Include code for OSMutexAccept() + none + false + + + + ucosii.mutex.os_mutex_del_en + OS_MUTEX_DEL_EN + Boolean + 1 + 1 + system_h_define + Include code for OSMutexDel() + none + false + + + + ucosii.mutex.os_mutex_query_en + OS_MUTEX_QUERY_EN + Boolean + 1 + 1 + system_h_define + Include code for OSMutexQuery + none + false + + + + ucosii.os_sem_en + OS_SEM_EN + Boolean + 1 + 1 + system_h_define + Enable code for semaphores. CAUTION: This is required by the HAL and many Altera device drivers. + none + false + + + + ucosii.semaphore.os_sem_accept_en + OS_SEM_ACCEPT_EN + Boolean + 1 + 1 + system_h_define + Include code for OSSemAccept(). CAUTION: This is required by the HAL and many Altera device drivers. + none + false + + + + ucosii.semaphore.os_sem_set_en + OS_SEM_SET_EN + Boolean + 1 + 1 + system_h_define + Include code for OSSemSet(). CAUTION: This is required by the HAL and many Altera device drivers. + none + false + + + + ucosii.semaphore.os_sem_del_en + OS_SEM_DEL_EN + Boolean + 1 + 1 + system_h_define + Include code for OSSemDel(). CAUTION: This is required by the HAL and many Altera device drivers. + none + false + + + + ucosii.semaphore.os_sem_query_en + OS_SEM_QUERY_EN + Boolean + 1 + 1 + system_h_define + Include code for OSSemQuery(). CAUTION: This is required by the HAL and many Altera device drivers. + none + false + + + + ucosii.os_mbox_en + OS_MBOX_EN + Boolean + 1 + 1 + system_h_define + Enable code for mailboxes + none + false + + + + ucosii.mailbox.os_mbox_accept_en + OS_MBOX_ACCEPT_EN + Boolean + 1 + 1 + system_h_define + Include code for OSMboxAccept() + none + false + + + + ucosii.mailbox.os_mbox_del_en + OS_MBOX_DEL_EN + Boolean + 1 + 1 + system_h_define + Include code for OSMboxDel() + none + false + + + + ucosii.mailbox.os_mbox_post_en + OS_MBOX_POST_EN + Boolean + 1 + 1 + system_h_define + Include code for OSMboxPost() + none + false + + + + ucosii.mailbox.os_mbox_post_opt_en + OS_MBOX_POST_OPT_EN + Boolean + 1 + 1 + system_h_define + Include code for OSMboxPostOpt() + none + false + + + + ucosii.mailbox.os_mbox_query_en + OS_MBOX_QUERY_EN + Boolean + 1 + 1 + system_h_define + Include code for OSMboxQuery() + none + false + + + + ucosii.os_q_en + OS_Q_EN + Boolean + 1 + 1 + system_h_define + Enable code for Queues + none + false + + + + ucosii.queue.os_q_accept_en + OS_Q_ACCEPT_EN + Boolean + 1 + 1 + system_h_define + Include code for OSQAccept() + none + false + + + + ucosii.queue.os_q_del_en + OS_Q_DEL_EN + Boolean + 1 + 1 + system_h_define + Include code for OSQDel() + none + false + + + + ucosii.queue.os_q_flush_en + OS_Q_FLUSH_EN + Boolean + 1 + 1 + system_h_define + Include code for OSQFlush() + none + false + + + + ucosii.queue.os_q_post_en + OS_Q_POST_EN + Boolean + 1 + 1 + system_h_define + Include code of OSQFlush() + none + false + + + + ucosii.queue.os_q_post_front_en + OS_Q_POST_FRONT_EN + Boolean + 1 + 1 + system_h_define + Include code for OSQPostFront() + none + false + + + + ucosii.queue.os_q_post_opt_en + OS_Q_POST_OPT_EN + Boolean + 1 + 1 + system_h_define + Include code for OSQPostOpt() + none + false + + + + ucosii.queue.os_q_query_en + OS_Q_QUERY_EN + Boolean + 1 + 1 + system_h_define + Include code for OSQQuery() + none + false + + + + ucosii.queue.os_max_qs + OS_MAX_QS + DecimalNumber + 20 + 20 + system_h_define + Maximum number of Queue Control Blocks + none + false + + + + ucosii.os_mem_en + OS_MEM_EN + Boolean + 1 + 1 + system_h_define + Enable code for memory management + none + false + + + + ucosii.memory.os_mem_query_en + OS_MEM_QUERY_EN + Boolean + 1 + 1 + system_h_define + Include code for OSMemQuery() + none + false + + + + ucosii.memory.os_mem_name_size + OS_MEM_NAME_SIZE + DecimalNumber + 32 + 32 + system_h_define + Size of memory partition name + none + false + + + + ucosii.memory.os_max_mem_part + OS_MAX_MEM_PART + DecimalNumber + 60 + 60 + system_h_define + Maximum number of memory partitions + none + false + + + + ucosii.os_tmr_en + OS_TMR_EN + Boolean + 0 + 0 + system_h_define + Enable code for timers + none + false + + + + ucosii.timer.os_task_tmr_stk_size + OS_TASK_TMR_STK_SIZE + DecimalNumber + 512 + 512 + system_h_define + Stack size for timer task + none + false + + + + ucosii.timer.os_task_tmr_prio + OS_TASK_TMR_PRIO + DecimalNumber + 0 + 0 + system_h_define + Priority of timer task (0=highest) + none + false + + + + ucosii.timer.os_tmr_cfg_max + OS_TMR_CFG_MAX + DecimalNumber + 16 + 16 + system_h_define + Maximum number of timers + none + false + + + + ucosii.timer.os_tmr_cfg_name_size + OS_TMR_CFG_NAME_SIZE + DecimalNumber + 16 + 16 + system_h_define + Size of timer name + none + false + + + + ucosii.timer.os_tmr_cfg_ticks_per_sec + OS_TMR_CFG_TICKS_PER_SEC + DecimalNumber + 10 + 10 + system_h_define + Rate at which timer management task runs (Hz) + none + false + + + + ucosii.timer.os_tmr_cfg_wheel_size + OS_TMR_CFG_WHEEL_SIZE + DecimalNumber + 2 + 2 + system_h_define + Size of timer wheel (number of spokes) + none + false + + + + altera_avalon_uart_driver.enable_small_driver + ALTERA_AVALON_UART_SMALL + BooleanDefineOnly + false + false + public_mk_define + Small-footprint (polled mode) driver + none + false + + + + altera_avalon_uart_driver.enable_ioctl + ALTERA_AVALON_UART_USE_IOCTL + BooleanDefineOnly + false + false + public_mk_define + Enable driver ioctl() support. This feature is not compatible with the 'small' driver; ioctl() support will not be compiled if either the UART 'enable_small_driver' or HAL 'enable_reduced_device_drivers' settings are enabled. + none + false + + + + altera_avalon_jtag_uart_driver.enable_small_driver + ALTERA_AVALON_JTAG_UART_SMALL + BooleanDefineOnly + false + false + public_mk_define + Small-footprint (polled mode) driver + none + false + + + + sdram + 0x01000000 - 0x01FFFFFF + 16777216 + memory + + + uart_mc + 0x02001000 - 0x0200101F + 32 + printable + + + pio_led + 0x02001020 - 0x0200103F + 32 + + + + uart_wifi + 0x02001040 - 0x0200105F + 32 + printable + + + sys_clk_timer + 0x02001060 - 0x0200107F + 32 + timer + + + pio_ir_emitter + 0x02001080 - 0x0200108F + 16 + + + + pio_sw + 0x02001090 - 0x0200109F + 16 + + + + pio_key_left + 0x020010A0 - 0x020010AF + 16 + + + + rs232_wifi + 0x020010B0 - 0x020010B7 + 8 + + + + jtag_uart_0 + 0x020010B8 - 0x020010BF + 8 + printable + + + sysid + 0x020010C0 - 0x020010C7 + 8 + + + + .text + sdram + + + .rodata + sdram + + + .rwdata + sdram + + + .bss + sdram + + + .heap + sdram + + + .stack + sdram + + \ No newline at end of file diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/summary.html b/MCandWifiTestDE0/Software/MCTest_bsp/summary.html new file mode 100644 index 00000000..c81f4201 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/summary.html @@ -0,0 +1,3946 @@ + +Altera Nios II BSP Summary + +

BSP Description

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BSP Type:ucosii
SOPC Design File:C:\Users\gongal\NewRepARCap\MCandWifiTestDE0\system.sopcinfo
Quartus JDI File:default
CPU:cpu
BSP Settings File:settings.bsp
BSP Version:default
BSP Generated On:3-Mar-2014 4:25:26 PM
BSP Generated Timestamp:1393889126953
BSP Generated Location:C:\Users\gongal\NewRepARCap\MCandWifiTestDE0\Software\MCTest_bsp
+
+

Nios II Memory Map

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Slave DescriptorAddress RangeSizeAttributes
sysid0x020010C0 - 0x020010C78 
jtag_uart_00x020010B8 - 0x020010BF8printable
rs232_wifi0x020010B0 - 0x020010B78 
pio_key_left0x020010A0 - 0x020010AF16 
pio_sw0x02001090 - 0x0200109F16 
pio_ir_emitter0x02001080 - 0x0200108F16 
sys_clk_timer0x02001060 - 0x0200107F32timer
uart_wifi0x02001040 - 0x0200105F32printable
pio_led0x02001020 - 0x0200103F32 
uart_mc0x02001000 - 0x0200101F32printable
sdram0x01000000 - 0x01FFFFFF16777216memory
+
+
+

Linker Regions

+ + + + +
RegionAddress RangeSizeMemoryOffset
+
+
+

Linker Section Mappings

+ + + + + + + + + + + + + + + + + + + + + + +
SectionRegion
.textsdram
.rodatasdram
.rwdatasdram
.bsssdram
.heapsdram
.stacksdram
+

Settings

+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:altera_avalon_jtag_uart_driver.enable_small_driver
Identifier:ALTERA_AVALON_JTAG_UART_SMALL
Default Value:false
Value:false
Type:BooleanDefineOnly
Destination:public_mk_define
Description:Small-footprint (polled mode) driver
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:altera_avalon_uart_driver.enable_ioctl
Identifier:ALTERA_AVALON_UART_USE_IOCTL
Default Value:false
Value:false
Type:BooleanDefineOnly
Destination:public_mk_define
Description:Enable driver ioctl() support. This feature is not compatible with the 'small' driver; ioctl() support will not be compiled if either the UART 'enable_small_driver' or HAL 'enable_reduced_device_drivers' settings are enabled.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:altera_avalon_uart_driver.enable_small_driver
Identifier:ALTERA_AVALON_UART_SMALL
Default Value:false
Value:false
Type:BooleanDefineOnly
Destination:public_mk_define
Description:Small-footprint (polled mode) driver
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.custom_newlib_flags
Identifier:CUSTOM_NEWLIB_FLAGS
Default Value:none
Value:none
Type:UnquotedString
Destination:public_mk_define
Description:Build a custom version of newlib with the specified space-separated compiler flags.
Restrictions:The custom newlib build will be placed in the &lt;bsp root>/newlib directory, and will be used only for applications that utilize this BSP.
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.enable_c_plus_plus
Identifier:ALT_NO_C_PLUS_PLUS
Default Value:1
Value:1
Type:Boolean
Destination:public_mk_define
Description:Enable support for a subset of the C++ language. This option increases code footprint by adding support for C++ constructors. Certain features, such as multiple inheritance and exceptions are not supported. If false, adds -DALT_NO_C_PLUS_PLUS to ALT_CPPFLAGS in public.mk, and reduces code footprint.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.enable_clean_exit
Identifier:ALT_NO_CLEAN_EXIT
Default Value:1
Value:1
Type:Boolean
Destination:public_mk_define
Description:When your application exits, close file descriptors, call C++ destructors, etc. Code footprint can be reduced by disabling clean exit. If disabled, adds -DALT_NO_CLEAN_EXIT to ALT_CPPFLAGS and -Wl,--defsym, exit=_exit to ALT_LDFLAGS in public.mk.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.enable_exit
Identifier:ALT_NO_EXIT
Default Value:1
Value:1
Type:Boolean
Destination:public_mk_define
Description:Add exit() support. This option increases code footprint if your "main()" routine does "return" or call "exit()". If false, adds -DALT_NO_EXIT to ALT_CPPFLAGS in public.mk, and reduces footprint
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.enable_gprof
Identifier:ALT_PROVIDE_GMON
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Causes code to be compiled with gprof profiling enabled and the application ELF to be linked with the GPROF library. If true, adds -DALT_PROVIDE_GMON to ALT_CPPFLAGS and -pg to ALT_CFLAGS in public.mk.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.enable_instruction_related_exceptions_api
Identifier:ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API
Default Value:false
Value:false
Type:BooleanDefineOnly
Destination:system_h_define
Description:Enables API for registering handlers to service instruction-related exceptions. Enabling this setting increases the size of the exception entry code.
Restrictions:These exception types can be generated if various processor options are enabled, such as the MMU, MPU, or other advanced exception types.
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.enable_lightweight_device_driver_api
Identifier:ALT_USE_DIRECT_DRIVERS
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Enables lightweight device driver API. This reduces code and data footprint by removing the HAL layer that maps device names (e.g. /dev/uart0) to file descriptors. Instead, driver routines are called directly. The open(), close(), and lseek() routines will always fail if called. The read(), write(), fstat(), ioctl(), and isatty() routines only work for the stdio devices. If true, adds -DALT_USE_DIRECT_DRIVERS to ALT_CPPFLAGS in public.mk.
Restrictions:The Altera Host and read-only ZIP file systems can't be used if hal.enable_lightweight_device_driver_api is true.
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.enable_mul_div_emulation
Identifier:ALT_NO_INSTRUCTION_EMULATION
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Adds code to emulate multiply and divide instructions in case they are executed but aren't present in the CPU. Normally this isn't required because the compiler won't use multiply and divide instructions that aren't present in the CPU. If false, adds -DALT_NO_INSTRUCTION_EMULATION to ALT_CPPFLAGS in public.mk.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.enable_reduced_device_drivers
Identifier:ALT_USE_SMALL_DRIVERS
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Certain drivers are compiled with reduced functionality to reduce code footprint. Not all drivers observe this setting. The altera_avalon_uart and altera_avalon_jtag_uart drivers switch from interrupt-driven to polled operation. CAUTION: Several device drivers are disabled entirely. These include the altera_avalon_cfi_flash, altera_avalon_epcs_flash_controller, and altera_avalon_lcd_16207 drivers. This can result in certain API (HAL flash access routines) to fail. You can define a symbol provided by each driver to prevent it from being removed. If true, adds -DALT_USE_SMALL_DRIVERS to ALT_CPPFLAGS in public.mk.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.enable_runtime_stack_checking
Identifier:ALT_STACK_CHECK
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Turns on HAL runtime stack checking feature. Enabling this setting causes additional code to be placed into each subroutine call to generate an exception if a stack collision occurs with the heap or statically allocated data. If true, adds -DALT_STACK_CHECK and -mstack-check to ALT_CPPFLAGS in public.mk.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.enable_sim_optimize
Identifier:ALT_SIM_OPTIMIZE
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:The BSP is compiled with optimizations to speedup HDL simulation such as initializing the cache, clearing the .bss section, and skipping long delay loops. If true, adds -DALT_SIM_OPTIMIZE to ALT_CPPFLAGS in public.mk.
Restrictions:When this setting is true, the BSP shouldn't be used to build applications that are expected to run real hardware.
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.enable_small_c_library
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Causes the small newlib (C library) to be used. This reduces code and data footprint at the expense of reduced functionality. Several newlib features are removed such as floating-point support in printf(), stdin input routines, and buffered I/O. The small C library is not compatible with Micrium MicroC/OS-II. If true, adds -msmallc to ALT_LDFLAGS in public.mk.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.enable_sopc_sysid_check
Identifier:NONE
Default Value:1
Value:1
Type:Boolean
Destination:public_mk_define
Description:Enable SOPC Builder System ID. If a System ID SOPC Builder component is connected to the CPU associated with this BSP, it will be enabled in the creation of command-line arguments to download an ELF to the target. Otherwise, system ID and timestamp values are left out of public.mk for application Makefile "download-elf" target definition. With the system ID check disabled, the Nios II EDS tools will not automatically ensure that the application .elf file (and BSP it is linked against) corresponds to the hardware design on the target. If false, adds --accept-bad-sysid to SOPC_SYSID_FLAG in public.mk.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.linker.allow_code_at_reset
Identifier:ALT_ALLOW_CODE_AT_RESET
Default Value:0
Value:1
Type:Boolean
Destination:none
Description:Indicates if initialization code is allowed at the reset address. If true, defines the macro ALT_ALLOW_CODE_AT_RESET in linker.h.
Restrictions:If true, defines the macro ALT_ALLOW_CODE_AT_RESET in linker.h. This setting is typically false if an external bootloader (e.g. flash bootloader) is present.
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.linker.enable_alt_load
Identifier:NONE
Default Value:0
Value:1
Type:Boolean
Destination:none
Description:Enables the alt_load() facility. The alt_load() facility copies sections from the .text memory into RAM. If true, this setting sets up the VMA/LMA of sections in linker.x to allow them to be loaded into the .text memory.
Restrictions:This setting is typically false if an external bootloader (e.g. flash bootloader) is present.
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.linker.enable_alt_load_copy_exceptions
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:none
Description:Causes the alt_load() facility to copy the .exceptions section. If true, this setting defines the macro ALT_LOAD_COPY_EXCEPTIONS in linker.h.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.linker.enable_alt_load_copy_rodata
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:none
Description:Causes the alt_load() facility to copy the .rodata section. If true, this setting defines the macro ALT_LOAD_COPY_RODATA in linker.h.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.linker.enable_alt_load_copy_rwdata
Identifier:NONE
Default Value:0
Value:1
Type:Boolean
Destination:none
Description:Causes the alt_load() facility to copy the .rwdata section. If true, this setting defines the macro ALT_LOAD_COPY_RWDATA in linker.h.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.linker.enable_exception_stack
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:none
Description:Enables use of a separate exception stack. If true, defines the macro ALT_EXCEPTION_STACK in linker.h, adds a memory region called exception_stack to linker.x, and provides the symbols __alt_exception_stack_pointer and __alt_exception_stack_limit in linker.x.
Restrictions:The hal.linker.exception_stack_size and hal.linker.exception_stack_memory_region_name settings must also be valid. This setting must be false for MicroC/OS-II BSPs. The exception stack can be used to improve interrupt and other exception performance if the EIC is *not* used.
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.linker.enable_interrupt_stack
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:none
Description:Enables use of a separate interrupt stack. If true, defines the macro ALT_INTERRUPT_STACK in linker.h, adds a memory region called interrupt_stack to linker.x, and provides the symbols __alt_interrupt_stack_pointer and __alt_interrupt_stack_limit in linker.x.
Restrictions:The hal.linker.interrupt_stack_size and hal.linker.interrupt_stack_memory_region_name settings must also be valid. This setting must be false for MicroC/OS-II BSPs. Only enable if the EIC is used exclusively. The exception stack can be used to improve interrupt and other exception performance if the EIC is *not* used.
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.linker.exception_stack_memory_region_name
Identifier:NONE
Default Value:none
Value:sdram
Type:UnquotedString
Destination:none
Description:Name of the existing memory region that will be divided up to create the 'exception_stack' memory region. The selected region name will be adjusted automatically when the BSP is generated to create the 'exception_stack' memory region.
Restrictions:Only used if hal.linker.enable_exception_stack is true.
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.linker.exception_stack_size
Identifier:NONE
Default Value:1024
Value:1024
Type:DecimalNumber
Destination:none
Description:Size of the exception stack in bytes.
Restrictions:Only used if hal.linker.enable_exception_stack is true.
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.linker.interrupt_stack_memory_region_name
Identifier:NONE
Default Value:none
Value:sdram
Type:UnquotedString
Destination:none
Description:Name of the existing memory region that will be divided up to create the 'interrupt_stack' memory region. The selected region name will be adjusted automatically when the BSP is generated to create the 'interrupt_stack' memory region.
Restrictions:Only used if hal.linker.enable_interrupt_stack is true.
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.linker.interrupt_stack_size
Identifier:NONE
Default Value:1024
Value:1024
Type:DecimalNumber
Destination:none
Description:Size of the interrupt stack in bytes.
Restrictions:Only used if hal.linker.enable_interrupt_stack is true.
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.log_flags
Identifier:ALT_LOG_FLAGS
Default Value:0
Value:0
Type:DecimalNumber
Destination:public_mk_define
Description:The value is assigned to ALT_LOG_FLAGS in the generated public.mk. See hal.log_port setting description. Values can be -1 through 3.
Restrictions:hal.log_port must be set for this to be used.
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.log_port
Identifier:NONE
Default Value:none
Value:none
Type:UnquotedString
Destination:public_mk_define
Description:Slave descriptor of debug logging character-mode device. If defined, it enables extra debug messages in the HAL source. This setting is used by the ALT_LOG_PORT family of defines in system.h.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.ar
Identifier:AR
Default Value:nios2-elf-ar
Value:nios2-elf-ar
Type:UnquotedString
Destination:makefile_variable
Description:Archiver command. Creates library files.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.ar_post_process
Identifier:AR_POST_PROCESS
Default Value:none
Value:none
Type:UnquotedString
Destination:makefile_variable
Description:Command executed after archiver execution.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.ar_pre_process
Identifier:AR_PRE_PROCESS
Default Value:none
Value:none
Type:UnquotedString
Destination:makefile_variable
Description:Command executed before archiver execution.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.as
Identifier:AS
Default Value:nios2-elf-gcc
Value:nios2-elf-gcc
Type:UnquotedString
Destination:makefile_variable
Description:Assembler command. Note that CC is used for .S files.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.as_post_process
Identifier:AS_POST_PROCESS
Default Value:none
Value:none
Type:UnquotedString
Destination:makefile_variable
Description:Command executed after each assembly file is compiled.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.as_pre_process
Identifier:AS_PRE_PROCESS
Default Value:none
Value:none
Type:UnquotedString
Destination:makefile_variable
Description:Command executed before each assembly file is compiled.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.bsp_arflags
Identifier:BSP_ARFLAGS
Default Value:-src
Value:-src
Type:UnquotedString
Destination:makefile_variable
Description:Custom flags only passed to the archiver. This content of this variable is directly passed to the archiver rather than the more standard "ARFLAGS". The reason for this is that GNU Make assumes some default content in ARFLAGS. This setting defines the value of BSP_ARFLAGS in Makefile.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.bsp_asflags
Identifier:BSP_ASFLAGS
Default Value:-Wa,-gdwarf2
Value:-Wa,-gdwarf2
Type:UnquotedString
Destination:makefile_variable
Description:Custom flags only passed to the assembler. This setting defines the value of BSP_ASFLAGS in Makefile.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.bsp_cflags_debug
Identifier:BSP_CFLAGS_DEBUG
Default Value:-g
Value:-g
Type:UnquotedString
Destination:makefile_variable
Description:C/C++ compiler debug level. '-g' provides the default set of debug symbols typically required to debug a typical application. Omitting '-g' removes debug symbols from the ELF. This setting defines the value of BSP_CFLAGS_DEBUG in Makefile.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.bsp_cflags_defined_symbols
Identifier:BSP_CFLAGS_DEFINED_SYMBOLS
Default Value:none
Value:none
Type:UnquotedString
Destination:makefile_variable
Description:Preprocessor macros to define. A macro definition in this setting has the same effect as a "#define" in source code. Adding "-DALT_DEBUG" to this setting has the same effect as "#define ALT_DEBUG" in a souce file. Adding "-DFOO=1" to this setting is equivalent to the macro "#define FOO 1" in a source file. Macros defined with this setting are applied to all .S, .c, and C++ files in the BSP. This setting defines the value of BSP_CFLAGS_DEFINED_SYMBOLS in the BSP Makefile.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.bsp_cflags_optimization
Identifier:BSP_CFLAGS_OPTIMIZATION
Default Value:-O0
Value:-O0
Type:UnquotedString
Destination:makefile_variable
Description:C/C++ compiler optimization level. "-O0" = no optimization,"-O2" = "normal" optimization, etc. "-O0" is recommended for code that you want to debug since compiler optimization can remove variables and produce non-sequential execution of code while debugging. This setting defines the value of BSP_CFLAGS_OPTIMIZATION in Makefile.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.bsp_cflags_undefined_symbols
Identifier:BSP_CFLAGS_UNDEFINED_SYMBOLS
Default Value:none
Value:none
Type:UnquotedString
Destination:makefile_variable
Description:Preprocessor macros to undefine. Undefined macros are similar to defined macros, but replicate the "#undef" directive in source code. To undefine the macro FOO use the syntax "-u FOO" in this setting. This is equivalent to "#undef FOO" in a source file. Note: the syntax differs from macro definition (there is a space, i.e. "-u FOO" versus "-DFOO"). Macros defined with this setting are applied to all .S, .c, and C++ files in the BSP. This setting defines the value of BSP_CFLAGS_UNDEFINED_SYMBOLS in the BSP Makefile.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.bsp_cflags_user_flags
Identifier:BSP_CFLAGS_USER_FLAGS
Default Value:none
Value:none
Type:UnquotedString
Destination:makefile_variable
Description:Custom flags passed to the compiler when compiling C, C++, and .S files. This setting defines the value of BSP_CFLAGS_USER_FLAGS in Makefile.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.bsp_cflags_warnings
Identifier:BSP_CFLAGS_WARNINGS
Default Value:-Wall
Value:-Wall
Type:UnquotedString
Destination:makefile_variable
Description:C/C++ compiler warning level. "-Wall" is commonly used.This setting defines the value of BSP_CFLAGS_WARNINGS in Makefile.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.bsp_cxx_flags
Identifier:BSP_CXXFLAGS
Default Value:none
Value:none
Type:UnquotedString
Destination:makefile_variable
Description:Custom flags only passed to the C++ compiler. This setting defines the value of BSP_CXXFLAGS in Makefile.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.bsp_inc_dirs
Identifier:BSP_INC_DIRS
Default Value:none
Value:none
Type:UnquotedString
Destination:makefile_variable
Description:Space separated list of extra include directories to scan for header files. Directories are relative to the top-level BSP directory. The -I prefix's added by the makefile so don't add it here. This setting defines the value of BSP_INC_DIRS in Makefile.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.build_post_process
Identifier:BUILD_POST_PROCESS
Default Value:none
Value:none
Type:UnquotedString
Destination:makefile_variable
Description:Command executed after BSP built.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.build_pre_process
Identifier:BUILD_PRE_PROCESS
Default Value:none
Value:none
Type:UnquotedString
Destination:makefile_variable
Description:Command executed before BSP built.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.cc
Identifier:CC
Default Value:nios2-elf-gcc -xc
Value:nios2-elf-gcc -xc
Type:UnquotedString
Destination:makefile_variable
Description:C compiler command.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.cc_post_process
Identifier:CC_POST_PROCESS
Default Value:none
Value:none
Type:UnquotedString
Destination:makefile_variable
Description:Command executed after each .c/.S file is compiled.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.cc_pre_process
Identifier:CC_PRE_PROCESS
Default Value:none
Value:none
Type:UnquotedString
Destination:makefile_variable
Description:Command executed before each .c/.S file is compiled.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.cxx
Identifier:CXX
Default Value:nios2-elf-gcc -xc++
Value:nios2-elf-gcc -xc++
Type:UnquotedString
Destination:makefile_variable
Description:C++ compiler command.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.cxx_post_process
Identifier:CXX_POST_PROCESS
Default Value:none
Value:none
Type:UnquotedString
Destination:makefile_variable
Description:Command executed before each C++ file is compiled.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.cxx_pre_process
Identifier:CXX_PRE_PROCESS
Default Value:none
Value:none
Type:UnquotedString
Destination:makefile_variable
Description:Command executed before each C++ file is compiled.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.ignore_system_derived.big_endian
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Enable BSP generation to query if SOPC system is big endian. If true ignores export of 'ALT_CFLAGS += -EB' to public.mk if big endian system. If true ignores export of 'ALT_CFLAGS += -EL' if little endian system.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.ignore_system_derived.debug_core_present
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Enable BSP generation to query if SOPC system has a debug core present. If true ignores export of 'CPU_HAS_DEBUG_CORE = 1' to public.mk if a debug core is found in the system. If true ignores export of 'CPU_HAS_DEBUG_CORE = 0' if no debug core is found in the system.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.ignore_system_derived.fpu_present
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Enable BSP generation to query if SOPC system has FPU present. If true ignores export of 'ALT_CFLAGS += -mhard-float' to public.mk if FPU is found in the system. If true ignores export of 'ALT_CFLAGS += -mhard-soft' if FPU is not found in the system.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.ignore_system_derived.hardware_divide_present
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Enable BSP generation to query if SOPC system has hardware divide present. If true ignores export of 'ALT_CFLAGS += -mno-hw-div' to public.mk if no division is found in system. If true ignores export of 'ALT_CFLAGS += -mhw-div' if division is found in the system.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.ignore_system_derived.hardware_fp_cust_inst_divider_present
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Enable BSP generation to query if SOPC system floating point custom instruction with a divider is present. If true ignores export of 'ALT_CFLAGS += -mcustom-fpu-cfg=60-2' and 'ALT_LDFLAGS += -mcustom-fpu-cfg=60-2' to public.mk if the custom instruction is found in the system.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.ignore_system_derived.hardware_fp_cust_inst_no_divider_present
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Enable BSP generation to query if SOPC system floating point custom instruction without a divider is present. If true ignores export of 'ALT_CFLAGS += -mcustom-fpu-cfg=60-1' and 'ALT_LDFLAGS += -mcustom-fpu-cfg=60-1' to public.mk if the custom instruction is found in the system.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.ignore_system_derived.hardware_multiplier_present
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Enable BSP generation to query if SOPC system has multiplier present. If true ignores export of 'ALT_CFLAGS += -mno-hw-mul' to public.mk if no multiplier is found in the system. If true ignores export of 'ALT_CFLAGS += -mhw-mul' if multiplier is found in the system.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.ignore_system_derived.hardware_mulx_present
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Enable BSP generation to query if SOPC system has hardware mulx present. If true ignores export of 'ALT_CFLAGS += -mno-hw-mulx' to public.mk if no mulx is found in the system. If true ignores export of 'ALT_CFLAGS += -mhw-mulx' if mulx is found in the system.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.ignore_system_derived.sopc_simulation_enabled
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Enable BSP generation to query if SOPC system has simulation enabled. If true ignores export of 'ELF_PATCH_FLAG += --simulation_enabled' to public.mk.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.ignore_system_derived.sopc_system_base_address
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Enable BSP generation to query SOPC system for system ID base address. If true ignores export of 'SOPC_SYSID_FLAG += --sidp=<address>' and 'ELF_PATCH_FLAG += --sidp=<address>' to public.mk.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.ignore_system_derived.sopc_system_id
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Enable BSP generation to query SOPC system for system ID. If true ignores export of 'SOPC_SYSID_FLAG += --id=<sysid>' and 'ELF_PATCH_FLAG += --id=<sysid>' to public.mk.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.ignore_system_derived.sopc_system_timestamp
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Enable BSP generation to query SOPC system for system timestamp. If true ignores export of 'SOPC_SYSID_FLAG += --timestamp=<timestamp>' and 'ELF_PATCH_FLAG += --timestamp=<timestamp>' to public.mk.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.make.rm
Identifier:RM
Default Value:rm -f
Value:rm -f
Type:UnquotedString
Destination:makefile_variable
Description:Command used to remove files during 'clean' target.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.max_file_descriptors
Identifier:ALT_MAX_FD
Default Value:32
Value:32
Type:DecimalNumber
Destination:system_h_define
Description:Determines the number of file descriptors statically allocated. This setting defines the value of ALT_MAX_FD in system.h.
Restrictions:If hal.enable_lightweight_device_driver_api is true, there are no file descriptors so this setting is ignored. If hal.enable_lightweight_device_driver_api is false, this setting must be at least 4 because HAL needs a file descriptor for /dev/null, /dev/stdin, /dev/stdout, and /dev/stderr.
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.stderr
Identifier:NONE
Default Value:none
Value:jtag_uart_0
Type:UnquotedString
Destination:system_h_define
Description:Slave descriptor of STDERR character-mode device. This setting is used by the ALT_STDERR family of defines in system.h.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.stdin
Identifier:NONE
Default Value:none
Value:jtag_uart_0
Type:UnquotedString
Destination:system_h_define
Description:Slave descriptor of STDIN character-mode device. This setting is used by the ALT_STDIN family of defines in system.h.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.stdout
Identifier:NONE
Default Value:none
Value:jtag_uart_0
Type:UnquotedString
Destination:system_h_define
Description:Slave descriptor of STDOUT character-mode device. This setting is used by the ALT_STDOUT family of defines in system.h.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.sys_clk_timer
Identifier:ALT_SYS_CLK
Default Value:none
Value:sys_clk_timer
Type:UnquotedString
Destination:system_h_define
Description:Slave descriptor of the system clock timer device. This device provides a periodic interrupt ("tick") and is typically required for RTOS use. This setting defines the value of ALT_SYS_CLK in system.h.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:hal.timestamp_timer
Identifier:ALT_TIMESTAMP_CLK
Default Value:none
Value:none
Type:UnquotedString
Destination:system_h_define
Description:Slave descriptor of timestamp timer device. This device is used by Altera HAL timestamp drivers for high-resolution time measurement. This setting defines the value of ALT_TIMESTAMP_CLK in system.h.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.event_flag.os_flag_accept_en
Identifier:OS_FLAG_ACCEPT_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSFlagAccept(). CAUTION: This is required by the HAL and many Altera device drivers.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.event_flag.os_flag_del_en
Identifier:OS_FLAG_DEL_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSFlagDel(). CAUTION: This is required by the HAL and many Altera device drivers.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.event_flag.os_flag_name_size
Identifier:OS_FLAG_NAME_SIZE
Default Value:32
Value:32
Type:DecimalNumber
Destination:system_h_define
Description:Size of name of Event Flags group. CAUTION: This is required by the HAL and many Altera device drivers; use caution in reducing this value.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.event_flag.os_flag_query_en
Identifier:OS_FLAG_QUERY_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSFlagQuery(). CAUTION: This is required by the HAL and many Altera device drivers.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.event_flag.os_flag_wait_clr_en
Identifier:OS_FLAG_WAIT_CLR_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for Wait on Clear Event Flags. CAUTION: This is required by the HAL and many Altera device drivers.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.event_flag.os_flags_nbits
Identifier:OS_FLAGS_NBITS
Default Value:16
Value:16
Type:DecimalNumber
Destination:system_h_define
Description:Event Flag bits (8,16,32). CAUTION: This is required by the HAL and many Altera device drivers; use caution in changing this value.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.event_flag.os_max_flags
Identifier:OS_MAX_FLAGS
Default Value:20
Value:20
Type:DecimalNumber
Destination:system_h_define
Description:Maximum number of Event Flags groups. CAUTION: This is required by the HAL and many Altera device drivers; use caution in reducing this value.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.mailbox.os_mbox_accept_en
Identifier:OS_MBOX_ACCEPT_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSMboxAccept()
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.mailbox.os_mbox_del_en
Identifier:OS_MBOX_DEL_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSMboxDel()
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.mailbox.os_mbox_post_en
Identifier:OS_MBOX_POST_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSMboxPost()
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.mailbox.os_mbox_post_opt_en
Identifier:OS_MBOX_POST_OPT_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSMboxPostOpt()
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.mailbox.os_mbox_query_en
Identifier:OS_MBOX_QUERY_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSMboxQuery()
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.memory.os_max_mem_part
Identifier:OS_MAX_MEM_PART
Default Value:60
Value:60
Type:DecimalNumber
Destination:system_h_define
Description:Maximum number of memory partitions
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.memory.os_mem_name_size
Identifier:OS_MEM_NAME_SIZE
Default Value:32
Value:32
Type:DecimalNumber
Destination:system_h_define
Description:Size of memory partition name
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.memory.os_mem_query_en
Identifier:OS_MEM_QUERY_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSMemQuery()
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.miscellaneous.os_arg_chk_en
Identifier:OS_ARG_CHK_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Enable argument checking
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.miscellaneous.os_cpu_hooks_en
Identifier:OS_CPU_HOOKS_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Enable uCOS-II hooks
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.miscellaneous.os_debug_en
Identifier:OS_DEBUG_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Enable debug variables
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.miscellaneous.os_event_name_size
Identifier:OS_EVENT_NAME_SIZE
Default Value:32
Value:32
Type:DecimalNumber
Destination:system_h_define
Description:Size of name of Event Control Block groups
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.miscellaneous.os_max_events
Identifier:OS_MAX_EVENTS
Default Value:60
Value:60
Type:DecimalNumber
Destination:system_h_define
Description:Maximum number of event control blocks
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.miscellaneous.os_sched_lock_en
Identifier:OS_SCHED_LOCK_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSSchedLock() and OSSchedUnlock()
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.miscellaneous.os_task_idle_stk_size
Identifier:OS_TASK_IDLE_STK_SIZE
Default Value:512
Value:512
Type:DecimalNumber
Destination:system_h_define
Description:Idle task stack size
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.miscellaneous.os_task_stat_en
Identifier:OS_TASK_STAT_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Enable statistics task
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.miscellaneous.os_task_stat_stk_chk_en
Identifier:OS_TASK_STAT_STK_CHK_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Check task stacks from statistics task
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.miscellaneous.os_task_stat_stk_size
Identifier:OS_TASK_STAT_STK_SIZE
Default Value:512
Value:512
Type:DecimalNumber
Destination:system_h_define
Description:Statistics task stack size
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.miscellaneous.os_tick_step_en
Identifier:OS_TICK_STEP_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Enable tick stepping feature for uCOS-View
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.mutex.os_mutex_accept_en
Identifier:OS_MUTEX_ACCEPT_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSMutexAccept()
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.mutex.os_mutex_del_en
Identifier:OS_MUTEX_DEL_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSMutexDel()
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.mutex.os_mutex_query_en
Identifier:OS_MUTEX_QUERY_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSMutexQuery
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.os_flag_en
Identifier:OS_FLAG_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Enable code for Event Flags. CAUTION: This is required by the HAL and many Altera device drivers.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.os_lowest_prio
Identifier:OS_LOWEST_PRIO
Default Value:20
Value:20
Type:DecimalNumber
Destination:system_h_define
Description:Lowest assignable priority
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.os_max_tasks
Identifier:OS_MAX_TASKS
Default Value:10
Value:10
Type:DecimalNumber
Destination:system_h_define
Description:Maximum number of tasks
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.os_mbox_en
Identifier:OS_MBOX_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Enable code for mailboxes
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.os_mem_en
Identifier:OS_MEM_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Enable code for memory management
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.os_mutex_en
Identifier:OS_MUTEX_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Enable code for Mutex Semaphores
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.os_q_en
Identifier:OS_Q_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Enable code for Queues
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.os_sem_en
Identifier:OS_SEM_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Enable code for semaphores. CAUTION: This is required by the HAL and many Altera device drivers.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.os_thread_safe_newlib
Identifier:OS_THREAD_SAFE_NEWLIB
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Thread safe C library
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.os_tmr_en
Identifier:OS_TMR_EN
Default Value:0
Value:0
Type:Boolean
Destination:system_h_define
Description:Enable code for timers
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.queue.os_max_qs
Identifier:OS_MAX_QS
Default Value:20
Value:20
Type:DecimalNumber
Destination:system_h_define
Description:Maximum number of Queue Control Blocks
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.queue.os_q_accept_en
Identifier:OS_Q_ACCEPT_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSQAccept()
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.queue.os_q_del_en
Identifier:OS_Q_DEL_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSQDel()
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.queue.os_q_flush_en
Identifier:OS_Q_FLUSH_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSQFlush()
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.queue.os_q_post_en
Identifier:OS_Q_POST_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code of OSQFlush()
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.queue.os_q_post_front_en
Identifier:OS_Q_POST_FRONT_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSQPostFront()
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.queue.os_q_post_opt_en
Identifier:OS_Q_POST_OPT_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSQPostOpt()
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.queue.os_q_query_en
Identifier:OS_Q_QUERY_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSQQuery()
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.semaphore.os_sem_accept_en
Identifier:OS_SEM_ACCEPT_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSSemAccept(). CAUTION: This is required by the HAL and many Altera device drivers.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.semaphore.os_sem_del_en
Identifier:OS_SEM_DEL_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSSemDel(). CAUTION: This is required by the HAL and many Altera device drivers.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.semaphore.os_sem_query_en
Identifier:OS_SEM_QUERY_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSSemQuery(). CAUTION: This is required by the HAL and many Altera device drivers.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.semaphore.os_sem_set_en
Identifier:OS_SEM_SET_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSSemSet(). CAUTION: This is required by the HAL and many Altera device drivers.
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.task.os_task_change_prio_en
Identifier:OS_TASK_CHANGE_PRIO_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSTaskChangePrio()
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.task.os_task_create_en
Identifier:OS_TASK_CREATE_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSTaskCreate()
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.task.os_task_create_ext_en
Identifier:OS_TASK_CREATE_EXT_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSTaskCreateExt()
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.task.os_task_del_en
Identifier:OS_TASK_DEL_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSTaskDel()
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.task.os_task_name_size
Identifier:OS_TASK_NAME_SIZE
Default Value:32
Value:32
Type:DecimalNumber
Destination:system_h_define
Description:Size of task name
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.task.os_task_profile_en
Identifier:OS_TASK_PROFILE_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include data structure for run-time task profiling
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.task.os_task_query_en
Identifier:OS_TASK_QUERY_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSTaskQuery
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.task.os_task_suspend_en
Identifier:OS_TASK_SUSPEND_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSTaskSuspend() and OSTaskResume()
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.task.os_task_sw_hook_en
Identifier:OS_TASK_SW_HOOK_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSTaskSwHook()
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.time.os_time_dly_hmsm_en
Identifier:OS_TIME_DLY_HMSM_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSTimeDlyHMSM()
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.time.os_time_dly_resume_en
Identifier:OS_TIME_DLY_RESUME_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSTimeDlyResume()
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.time.os_time_get_set_en
Identifier:OS_TIME_GET_SET_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSTimeGet and OSTimeSet()
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.time.os_time_tick_hook_en
Identifier:OS_TIME_TICK_HOOK_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSTimeTickHook()
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.timer.os_task_tmr_prio
Identifier:OS_TASK_TMR_PRIO
Default Value:0
Value:0
Type:DecimalNumber
Destination:system_h_define
Description:Priority of timer task (0=highest)
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.timer.os_task_tmr_stk_size
Identifier:OS_TASK_TMR_STK_SIZE
Default Value:512
Value:512
Type:DecimalNumber
Destination:system_h_define
Description:Stack size for timer task
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.timer.os_tmr_cfg_max
Identifier:OS_TMR_CFG_MAX
Default Value:16
Value:16
Type:DecimalNumber
Destination:system_h_define
Description:Maximum number of timers
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.timer.os_tmr_cfg_name_size
Identifier:OS_TMR_CFG_NAME_SIZE
Default Value:16
Value:16
Type:DecimalNumber
Destination:system_h_define
Description:Size of timer name
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.timer.os_tmr_cfg_ticks_per_sec
Identifier:OS_TMR_CFG_TICKS_PER_SEC
Default Value:10
Value:10
Type:DecimalNumber
Destination:system_h_define
Description:Rate at which timer management task runs (Hz)
Restrictions:none
+
+ + + + + + + + + + + + + + + + + + + + + + + + + +
Setting Name:ucosii.timer.os_tmr_cfg_wheel_size
Identifier:OS_TMR_CFG_WHEEL_SIZE
Default Value:2
Value:2
Type:DecimalNumber
Destination:system_h_define
Description:Size of timer wheel (number of spokes)
Restrictions:none
+
+
+
+ + diff --git a/MCandWifiTestDE0/Software/MCTest_bsp/system.h b/MCandWifiTestDE0/Software/MCTest_bsp/system.h new file mode 100644 index 00000000..0f9ed689 --- /dev/null +++ b/MCandWifiTestDE0/Software/MCTest_bsp/system.h @@ -0,0 +1,534 @@ +/* + * system.h - SOPC Builder system and BSP software package information + * + * Machine generated for CPU 'cpu' in SOPC Builder design 'system' + * SOPC Builder design path: C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system.sopcinfo + * + * Generated: Mon Mar 03 15:52:38 MST 2014 + */ + +/* + * DO NOT MODIFY THIS FILE + * + * Changing this file will have subtle consequences + * which will almost certainly lead to a nonfunctioning + * system. If you do modify this file, be aware that your + * changes will be overwritten and lost when this file + * is generated again. + * + * DO NOT MODIFY THIS FILE + */ + +/* + * License Agreement + * + * Copyright (c) 2008 + * Altera Corporation, San Jose, California, USA. + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * This agreement shall be governed in all respects by the laws of the State + * of California and by the laws of the United States of America. + */ + +#ifndef __SYSTEM_H_ +#define __SYSTEM_H_ + +/* Include definitions from linker script generator */ +#include "linker.h" + + +/* + * CPU configuration + * + */ + +#define ALT_CPU_ARCHITECTURE "altera_nios2_qsys" +#define ALT_CPU_BIG_ENDIAN 0 +#define ALT_CPU_BREAK_ADDR 0x2000820 +#define ALT_CPU_CPU_FREQ 100000000u +#define ALT_CPU_CPU_ID_SIZE 1 +#define ALT_CPU_CPU_ID_VALUE 0x00000000 +#define ALT_CPU_CPU_IMPLEMENTATION "fast" +#define ALT_CPU_DATA_ADDR_WIDTH 0x1a +#define ALT_CPU_DCACHE_LINE_SIZE 32 +#define ALT_CPU_DCACHE_LINE_SIZE_LOG2 5 +#define ALT_CPU_DCACHE_SIZE 4096 +#define ALT_CPU_EXCEPTION_ADDR 0x1000020 +#define ALT_CPU_FLUSHDA_SUPPORTED +#define ALT_CPU_FREQ 100000000 +#define ALT_CPU_HARDWARE_DIVIDE_PRESENT 0 +#define ALT_CPU_HARDWARE_MULTIPLY_PRESENT 1 +#define ALT_CPU_HARDWARE_MULX_PRESENT 0 +#define ALT_CPU_HAS_DEBUG_CORE 1 +#define ALT_CPU_HAS_DEBUG_STUB +#define ALT_CPU_HAS_JMPI_INSTRUCTION +#define ALT_CPU_ICACHE_LINE_SIZE 32 +#define ALT_CPU_ICACHE_LINE_SIZE_LOG2 5 +#define ALT_CPU_ICACHE_SIZE 8192 +#define ALT_CPU_INITDA_SUPPORTED +#define ALT_CPU_INST_ADDR_WIDTH 0x1a +#define ALT_CPU_NAME "cpu" +#define ALT_CPU_NUM_OF_SHADOW_REG_SETS 0 +#define ALT_CPU_RESET_ADDR 0x1000000 + + +/* + * CPU configuration (with legacy prefix - don't use these anymore) + * + */ + +#define NIOS2_BIG_ENDIAN 0 +#define NIOS2_BREAK_ADDR 0x2000820 +#define NIOS2_CPU_FREQ 100000000u +#define NIOS2_CPU_ID_SIZE 1 +#define NIOS2_CPU_ID_VALUE 0x00000000 +#define NIOS2_CPU_IMPLEMENTATION "fast" +#define NIOS2_DATA_ADDR_WIDTH 0x1a +#define NIOS2_DCACHE_LINE_SIZE 32 +#define NIOS2_DCACHE_LINE_SIZE_LOG2 5 +#define NIOS2_DCACHE_SIZE 4096 +#define NIOS2_EXCEPTION_ADDR 0x1000020 +#define NIOS2_FLUSHDA_SUPPORTED +#define NIOS2_HARDWARE_DIVIDE_PRESENT 0 +#define NIOS2_HARDWARE_MULTIPLY_PRESENT 1 +#define NIOS2_HARDWARE_MULX_PRESENT 0 +#define NIOS2_HAS_DEBUG_CORE 1 +#define NIOS2_HAS_DEBUG_STUB +#define NIOS2_HAS_JMPI_INSTRUCTION +#define NIOS2_ICACHE_LINE_SIZE 32 +#define NIOS2_ICACHE_LINE_SIZE_LOG2 5 +#define NIOS2_ICACHE_SIZE 8192 +#define NIOS2_INITDA_SUPPORTED +#define NIOS2_INST_ADDR_WIDTH 0x1a +#define NIOS2_NUM_OF_SHADOW_REG_SETS 0 +#define NIOS2_RESET_ADDR 0x1000000 + + +/* + * Define for each module class mastered by the CPU + * + */ + +#define __ALTERA_AVALON_JTAG_UART +#define __ALTERA_AVALON_NEW_SDRAM_CONTROLLER +#define __ALTERA_AVALON_PIO +#define __ALTERA_AVALON_SYSID_QSYS +#define __ALTERA_AVALON_TIMER +#define __ALTERA_AVALON_UART +#define __ALTERA_NIOS2_QSYS +#define __ALTERA_UP_AVALON_RS232 + + +/* + * System configuration + * + */ + +#define ALT_DEVICE_FAMILY "Cyclone IV E" +#define ALT_IRQ_BASE NULL +#define ALT_LEGACY_INTERRUPT_API_PRESENT +#define ALT_LOG_PORT "/dev/null" +#define ALT_LOG_PORT_BASE 0x0 +#define ALT_LOG_PORT_DEV null +#define ALT_LOG_PORT_TYPE "" +#define ALT_NUM_EXTERNAL_INTERRUPT_CONTROLLERS 0 +#define ALT_NUM_INTERNAL_INTERRUPT_CONTROLLERS 1 +#define ALT_NUM_INTERRUPT_CONTROLLERS 1 +#define ALT_STDERR "/dev/jtag_uart_0" +#define ALT_STDERR_BASE 0x20010b8 +#define ALT_STDERR_DEV jtag_uart_0 +#define ALT_STDERR_IS_JTAG_UART +#define ALT_STDERR_PRESENT +#define ALT_STDERR_TYPE "altera_avalon_jtag_uart" +#define ALT_STDIN "/dev/jtag_uart_0" +#define ALT_STDIN_BASE 0x20010b8 +#define ALT_STDIN_DEV jtag_uart_0 +#define ALT_STDIN_IS_JTAG_UART +#define ALT_STDIN_PRESENT +#define ALT_STDIN_TYPE "altera_avalon_jtag_uart" +#define ALT_STDOUT "/dev/jtag_uart_0" +#define ALT_STDOUT_BASE 0x20010b8 +#define ALT_STDOUT_DEV jtag_uart_0 +#define ALT_STDOUT_IS_JTAG_UART +#define ALT_STDOUT_PRESENT +#define ALT_STDOUT_TYPE "altera_avalon_jtag_uart" +#define ALT_SYSTEM_NAME "system" + + +/* + * hal configuration + * + */ + +#define ALT_MAX_FD 32 +#define ALT_SYS_CLK SYS_CLK_TIMER +#define ALT_TIMESTAMP_CLK none + + +/* + * jtag_uart_0 configuration + * + */ + +#define ALT_MODULE_CLASS_jtag_uart_0 altera_avalon_jtag_uart +#define JTAG_UART_0_BASE 0x20010b8 +#define JTAG_UART_0_IRQ 14 +#define JTAG_UART_0_IRQ_INTERRUPT_CONTROLLER_ID 0 +#define JTAG_UART_0_NAME "/dev/jtag_uart_0" +#define JTAG_UART_0_READ_DEPTH 64 +#define JTAG_UART_0_READ_THRESHOLD 8 +#define JTAG_UART_0_SPAN 8 +#define JTAG_UART_0_TYPE "altera_avalon_jtag_uart" +#define JTAG_UART_0_WRITE_DEPTH 64 +#define JTAG_UART_0_WRITE_THRESHOLD 8 + + +/* + * pio_ir_emitter configuration + * + */ + +#define ALT_MODULE_CLASS_pio_ir_emitter altera_avalon_pio +#define PIO_IR_EMITTER_BASE 0x2001080 +#define PIO_IR_EMITTER_BIT_CLEARING_EDGE_REGISTER 0 +#define PIO_IR_EMITTER_BIT_MODIFYING_OUTPUT_REGISTER 0 +#define PIO_IR_EMITTER_CAPTURE 0 +#define PIO_IR_EMITTER_DATA_WIDTH 1 +#define PIO_IR_EMITTER_DO_TEST_BENCH_WIRING 0 +#define PIO_IR_EMITTER_DRIVEN_SIM_VALUE 0x0 +#define PIO_IR_EMITTER_EDGE_TYPE "NONE" +#define PIO_IR_EMITTER_FREQ 100000000u +#define PIO_IR_EMITTER_HAS_IN 0 +#define PIO_IR_EMITTER_HAS_OUT 1 +#define PIO_IR_EMITTER_HAS_TRI 0 +#define PIO_IR_EMITTER_IRQ -1 +#define PIO_IR_EMITTER_IRQ_INTERRUPT_CONTROLLER_ID -1 +#define PIO_IR_EMITTER_IRQ_TYPE "NONE" +#define PIO_IR_EMITTER_NAME "/dev/pio_ir_emitter" +#define PIO_IR_EMITTER_RESET_VALUE 0x0 +#define PIO_IR_EMITTER_SPAN 16 +#define PIO_IR_EMITTER_TYPE "altera_avalon_pio" + + +/* + * pio_key_left configuration + * + */ + +#define ALT_MODULE_CLASS_pio_key_left altera_avalon_pio +#define PIO_KEY_LEFT_BASE 0x20010a0 +#define PIO_KEY_LEFT_BIT_CLEARING_EDGE_REGISTER 1 +#define PIO_KEY_LEFT_BIT_MODIFYING_OUTPUT_REGISTER 0 +#define PIO_KEY_LEFT_CAPTURE 1 +#define PIO_KEY_LEFT_DATA_WIDTH 1 +#define PIO_KEY_LEFT_DO_TEST_BENCH_WIRING 0 +#define PIO_KEY_LEFT_DRIVEN_SIM_VALUE 0x0 +#define PIO_KEY_LEFT_EDGE_TYPE "ANY" +#define PIO_KEY_LEFT_FREQ 100000000u +#define PIO_KEY_LEFT_HAS_IN 1 +#define PIO_KEY_LEFT_HAS_OUT 0 +#define PIO_KEY_LEFT_HAS_TRI 0 +#define PIO_KEY_LEFT_IRQ 1 +#define PIO_KEY_LEFT_IRQ_INTERRUPT_CONTROLLER_ID 0 +#define PIO_KEY_LEFT_IRQ_TYPE "EDGE" +#define PIO_KEY_LEFT_NAME "/dev/pio_key_left" +#define PIO_KEY_LEFT_RESET_VALUE 0x0 +#define PIO_KEY_LEFT_SPAN 16 +#define PIO_KEY_LEFT_TYPE "altera_avalon_pio" + + +/* + * pio_led configuration + * + */ + +#define ALT_MODULE_CLASS_pio_led altera_avalon_pio +#define PIO_LED_BASE 0x2001020 +#define PIO_LED_BIT_CLEARING_EDGE_REGISTER 0 +#define PIO_LED_BIT_MODIFYING_OUTPUT_REGISTER 1 +#define PIO_LED_CAPTURE 0 +#define PIO_LED_DATA_WIDTH 7 +#define PIO_LED_DO_TEST_BENCH_WIRING 0 +#define PIO_LED_DRIVEN_SIM_VALUE 0x0 +#define PIO_LED_EDGE_TYPE "NONE" +#define PIO_LED_FREQ 100000000u +#define PIO_LED_HAS_IN 0 +#define PIO_LED_HAS_OUT 1 +#define PIO_LED_HAS_TRI 0 +#define PIO_LED_IRQ -1 +#define PIO_LED_IRQ_INTERRUPT_CONTROLLER_ID -1 +#define PIO_LED_IRQ_TYPE "NONE" +#define PIO_LED_NAME "/dev/pio_led" +#define PIO_LED_RESET_VALUE 0x0 +#define PIO_LED_SPAN 32 +#define PIO_LED_TYPE "altera_avalon_pio" + + +/* + * pio_sw configuration + * + */ + +#define ALT_MODULE_CLASS_pio_sw altera_avalon_pio +#define PIO_SW_BASE 0x2001090 +#define PIO_SW_BIT_CLEARING_EDGE_REGISTER 0 +#define PIO_SW_BIT_MODIFYING_OUTPUT_REGISTER 0 +#define PIO_SW_CAPTURE 0 +#define PIO_SW_DATA_WIDTH 4 +#define PIO_SW_DO_TEST_BENCH_WIRING 0 +#define PIO_SW_DRIVEN_SIM_VALUE 0x0 +#define PIO_SW_EDGE_TYPE "NONE" +#define PIO_SW_FREQ 100000000u +#define PIO_SW_HAS_IN 1 +#define PIO_SW_HAS_OUT 0 +#define PIO_SW_HAS_TRI 0 +#define PIO_SW_IRQ -1 +#define PIO_SW_IRQ_INTERRUPT_CONTROLLER_ID -1 +#define PIO_SW_IRQ_TYPE "NONE" +#define PIO_SW_NAME "/dev/pio_sw" +#define PIO_SW_RESET_VALUE 0x0 +#define PIO_SW_SPAN 16 +#define PIO_SW_TYPE "altera_avalon_pio" + + +/* + * rs232_wifi configuration + * + */ + +#define ALT_MODULE_CLASS_rs232_wifi altera_up_avalon_rs232 +#define RS232_WIFI_BASE 0x20010b0 +#define RS232_WIFI_IRQ 6 +#define RS232_WIFI_IRQ_INTERRUPT_CONTROLLER_ID 0 +#define RS232_WIFI_NAME "/dev/rs232_wifi" +#define RS232_WIFI_SPAN 8 +#define RS232_WIFI_TYPE "altera_up_avalon_rs232" + + +/* + * sdram configuration + * + */ + +#define ALT_MODULE_CLASS_sdram altera_avalon_new_sdram_controller +#define SDRAM_BASE 0x1000000 +#define SDRAM_CAS_LATENCY 3 +#define SDRAM_CONTENTS_INFO "" +#define SDRAM_INIT_NOP_DELAY 0.0 +#define SDRAM_INIT_REFRESH_COMMANDS 8 +#define SDRAM_IRQ -1 +#define SDRAM_IRQ_INTERRUPT_CONTROLLER_ID -1 +#define SDRAM_IS_INITIALIZED 1 +#define SDRAM_NAME "/dev/sdram" +#define SDRAM_POWERUP_DELAY 200.0 +#define SDRAM_REFRESH_PERIOD 7.8125 +#define SDRAM_REGISTER_DATA_IN 1 +#define SDRAM_SDRAM_ADDR_WIDTH 0x17 +#define SDRAM_SDRAM_BANK_WIDTH 2 +#define SDRAM_SDRAM_COL_WIDTH 8 +#define SDRAM_SDRAM_DATA_WIDTH 16 +#define SDRAM_SDRAM_NUM_BANKS 4 +#define SDRAM_SDRAM_NUM_CHIPSELECTS 1 +#define SDRAM_SDRAM_ROW_WIDTH 13 +#define SDRAM_SHARED_DATA 0 +#define SDRAM_SIM_MODEL_BASE 0 +#define SDRAM_SPAN 16777216 +#define SDRAM_STARVATION_INDICATOR 0 +#define SDRAM_TRISTATE_BRIDGE_SLAVE "" +#define SDRAM_TYPE "altera_avalon_new_sdram_controller" +#define SDRAM_T_AC 5.5 +#define SDRAM_T_MRD 3 +#define SDRAM_T_RCD 20.0 +#define SDRAM_T_RFC 70.0 +#define SDRAM_T_RP 20.0 +#define SDRAM_T_WR 14.0 + + +/* + * sys_clk_timer configuration + * + */ + +#define ALT_MODULE_CLASS_sys_clk_timer altera_avalon_timer +#define SYS_CLK_TIMER_ALWAYS_RUN 0 +#define SYS_CLK_TIMER_BASE 0x2001060 +#define SYS_CLK_TIMER_COUNTER_SIZE 32 +#define SYS_CLK_TIMER_FIXED_PERIOD 0 +#define SYS_CLK_TIMER_FREQ 100000000u +#define SYS_CLK_TIMER_IRQ 0 +#define SYS_CLK_TIMER_IRQ_INTERRUPT_CONTROLLER_ID 0 +#define SYS_CLK_TIMER_LOAD_VALUE 99999ull +#define SYS_CLK_TIMER_MULT 0.0010 +#define SYS_CLK_TIMER_NAME "/dev/sys_clk_timer" +#define SYS_CLK_TIMER_PERIOD 1 +#define SYS_CLK_TIMER_PERIOD_UNITS "ms" +#define SYS_CLK_TIMER_RESET_OUTPUT 0 +#define SYS_CLK_TIMER_SNAPSHOT 1 +#define SYS_CLK_TIMER_SPAN 32 +#define SYS_CLK_TIMER_TICKS_PER_SEC 1000u +#define SYS_CLK_TIMER_TIMEOUT_PULSE_OUTPUT 0 +#define SYS_CLK_TIMER_TYPE "altera_avalon_timer" + + +/* + * sysid configuration + * + */ + +#define ALT_MODULE_CLASS_sysid altera_avalon_sysid_qsys +#define SYSID_BASE 0x20010c0 +#define SYSID_ID 0 +#define SYSID_IRQ -1 +#define SYSID_IRQ_INTERRUPT_CONTROLLER_ID -1 +#define SYSID_NAME "/dev/sysid" +#define SYSID_SPAN 8 +#define SYSID_TIMESTAMP 1393886764 +#define SYSID_TYPE "altera_avalon_sysid_qsys" + + +/* + * uart_mc configuration + * + */ + +#define ALT_MODULE_CLASS_uart_mc altera_avalon_uart +#define UART_MC_BASE 0x2001000 +#define UART_MC_BAUD 9600 +#define UART_MC_DATA_BITS 8 +#define UART_MC_FIXED_BAUD 1 +#define UART_MC_FREQ 100000000u +#define UART_MC_IRQ 5 +#define UART_MC_IRQ_INTERRUPT_CONTROLLER_ID 0 +#define UART_MC_NAME "/dev/uart_mc" +#define UART_MC_PARITY 'N' +#define UART_MC_SIM_CHAR_STREAM "" +#define UART_MC_SIM_TRUE_BAUD 0 +#define UART_MC_SPAN 32 +#define UART_MC_STOP_BITS 1 +#define UART_MC_SYNC_REG_DEPTH 2 +#define UART_MC_TYPE "altera_avalon_uart" +#define UART_MC_USE_CTS_RTS 0 +#define UART_MC_USE_EOP_REGISTER 0 + + +/* + * uart_wifi configuration + * + */ + +#define ALT_MODULE_CLASS_uart_wifi altera_avalon_uart +#define UART_WIFI_BASE 0x2001040 +#define UART_WIFI_BAUD 9600 +#define UART_WIFI_DATA_BITS 8 +#define UART_WIFI_FIXED_BAUD 0 +#define UART_WIFI_FREQ 100000000u +#define UART_WIFI_IRQ 4 +#define UART_WIFI_IRQ_INTERRUPT_CONTROLLER_ID 0 +#define UART_WIFI_NAME "/dev/uart_wifi" +#define UART_WIFI_PARITY 'N' +#define UART_WIFI_SIM_CHAR_STREAM "" +#define UART_WIFI_SIM_TRUE_BAUD 0 +#define UART_WIFI_SPAN 32 +#define UART_WIFI_STOP_BITS 1 +#define UART_WIFI_SYNC_REG_DEPTH 2 +#define UART_WIFI_TYPE "altera_avalon_uart" +#define UART_WIFI_USE_CTS_RTS 0 +#define UART_WIFI_USE_EOP_REGISTER 0 + + +/* + * ucosii configuration + * + */ + +#define OS_ARG_CHK_EN 1 +#define OS_CPU_HOOKS_EN 1 +#define OS_DEBUG_EN 1 +#define OS_EVENT_NAME_SIZE 32 +#define OS_FLAGS_NBITS 16 +#define OS_FLAG_ACCEPT_EN 1 +#define OS_FLAG_DEL_EN 1 +#define OS_FLAG_EN 1 +#define OS_FLAG_NAME_SIZE 32 +#define OS_FLAG_QUERY_EN 1 +#define OS_FLAG_WAIT_CLR_EN 1 +#define OS_LOWEST_PRIO 20 +#define OS_MAX_EVENTS 60 +#define OS_MAX_FLAGS 20 +#define OS_MAX_MEM_PART 60 +#define OS_MAX_QS 20 +#define OS_MAX_TASKS 10 +#define OS_MBOX_ACCEPT_EN 1 +#define OS_MBOX_DEL_EN 1 +#define OS_MBOX_EN 1 +#define OS_MBOX_POST_EN 1 +#define OS_MBOX_POST_OPT_EN 1 +#define OS_MBOX_QUERY_EN 1 +#define OS_MEM_EN 1 +#define OS_MEM_NAME_SIZE 32 +#define OS_MEM_QUERY_EN 1 +#define OS_MUTEX_ACCEPT_EN 1 +#define OS_MUTEX_DEL_EN 1 +#define OS_MUTEX_EN 1 +#define OS_MUTEX_QUERY_EN 1 +#define OS_Q_ACCEPT_EN 1 +#define OS_Q_DEL_EN 1 +#define OS_Q_EN 1 +#define OS_Q_FLUSH_EN 1 +#define OS_Q_POST_EN 1 +#define OS_Q_POST_FRONT_EN 1 +#define OS_Q_POST_OPT_EN 1 +#define OS_Q_QUERY_EN 1 +#define OS_SCHED_LOCK_EN 1 +#define OS_SEM_ACCEPT_EN 1 +#define OS_SEM_DEL_EN 1 +#define OS_SEM_EN 1 +#define OS_SEM_QUERY_EN 1 +#define OS_SEM_SET_EN 1 +#define OS_TASK_CHANGE_PRIO_EN 1 +#define OS_TASK_CREATE_EN 1 +#define OS_TASK_CREATE_EXT_EN 1 +#define OS_TASK_DEL_EN 1 +#define OS_TASK_IDLE_STK_SIZE 512 +#define OS_TASK_NAME_SIZE 32 +#define OS_TASK_PROFILE_EN 1 +#define OS_TASK_QUERY_EN 1 +#define OS_TASK_STAT_EN 1 +#define OS_TASK_STAT_STK_CHK_EN 1 +#define OS_TASK_STAT_STK_SIZE 512 +#define OS_TASK_SUSPEND_EN 1 +#define OS_TASK_SW_HOOK_EN 1 +#define OS_TASK_TMR_PRIO 0 +#define OS_TASK_TMR_STK_SIZE 512 +#define OS_THREAD_SAFE_NEWLIB 1 +#define OS_TICKS_PER_SEC SYS_CLK_TIMER_TICKS_PER_SEC +#define OS_TICK_STEP_EN 1 +#define OS_TIME_DLY_HMSM_EN 1 +#define OS_TIME_DLY_RESUME_EN 1 +#define OS_TIME_GET_SET_EN 1 +#define OS_TIME_TICK_HOOK_EN 1 +#define OS_TMR_CFG_MAX 16 +#define OS_TMR_CFG_NAME_SIZE 16 +#define OS_TMR_CFG_TICKS_PER_SEC 10 +#define OS_TMR_CFG_WHEEL_SIZE 2 +#define OS_TMR_EN 0 + +#endif /* __SYSTEM_H_ */ diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/.cproject b/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/.cproject deleted file mode 100644 index 7c500caa..00000000 --- a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/.cproject +++ /dev/null @@ -1,481 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/.project b/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/.project deleted file mode 100644 index d0418be3..00000000 --- a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/.project +++ /dev/null @@ -1,85 +0,0 @@ - - - MCandWifiTestDE0_bsp - - - - - - org.eclipse.cdt.managedbuilder.core.genmakebuilder - clean,full,incremental, - - - ?name? - - - - org.eclipse.cdt.make.core.append_environment - true - - - org.eclipse.cdt.make.core.autoBuildTarget - all - - - org.eclipse.cdt.make.core.buildArguments - - - - org.eclipse.cdt.make.core.buildCommand - make - - - org.eclipse.cdt.make.core.buildLocation - ${workspace_loc://MCandWifiTestDE0_bsp} - - - org.eclipse.cdt.make.core.cleanBuildTarget - clean - - - org.eclipse.cdt.make.core.contents - org.eclipse.cdt.make.core.activeConfigSettings - - - org.eclipse.cdt.make.core.enableAutoBuild - false - - - org.eclipse.cdt.make.core.enableCleanBuild - true - - - org.eclipse.cdt.make.core.enableFullBuild - true - - - org.eclipse.cdt.make.core.fullBuildTarget - all - - - org.eclipse.cdt.make.core.stopOnError - true - - - org.eclipse.cdt.make.core.useDefaultBuildCmd - true - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder - full,incremental, - - - - - - org.eclipse.cdt.core.cnature - org.eclipse.cdt.managedbuilder.core.managedBuildNature - org.eclipse.cdt.managedbuilder.core.ScannerConfigNature - org.eclipse.cdt.core.ccnature - com.altera.sbtgui.project.SBTGUINature - com.altera.sbtgui.project.SBTGUIBspNature - - diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/alt_sys_init.c b/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/alt_sys_init.c deleted file mode 100644 index 6432a444..00000000 --- a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/alt_sys_init.c +++ /dev/null @@ -1,107 +0,0 @@ -/* - * alt_sys_init.c - HAL initialization source - * - * Machine generated for CPU 'cpu' in SOPC Builder design 'system' - * SOPC Builder design path: C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system.sopcinfo - * - * Generated: Sun Mar 02 19:03:49 MST 2014 - */ - -/* - * DO NOT MODIFY THIS FILE - * - * Changing this file will have subtle consequences - * which will almost certainly lead to a nonfunctioning - * system. If you do modify this file, be aware that your - * changes will be overwritten and lost when this file - * is generated again. - * - * DO NOT MODIFY THIS FILE - */ - -/* - * License Agreement - * - * Copyright (c) 2008 - * Altera Corporation, San Jose, California, USA. - * All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - * This agreement shall be governed in all respects by the laws of the State - * of California and by the laws of the United States of America. - */ - -#include "system.h" -#include "sys/alt_irq.h" -#include "sys/alt_sys_init.h" - -#include - -/* - * Device headers - */ - -#include "altera_nios2_qsys_irq.h" -#include "altera_avalon_jtag_uart.h" -#include "altera_avalon_sysid_qsys.h" -#include "altera_avalon_timer.h" -#include "altera_avalon_uart.h" -#include "altera_up_avalon_rs232.h" - -/* - * Allocate the device storage - */ - -ALTERA_NIOS2_QSYS_IRQ_INSTANCE ( CPU, cpu); -ALTERA_AVALON_JTAG_UART_INSTANCE ( JTAG_UART_0, jtag_uart_0); -ALTERA_AVALON_SYSID_QSYS_INSTANCE ( SYSID, sysid); -ALTERA_AVALON_TIMER_INSTANCE ( SYS_CLK_TIMER, sys_clk_timer); -ALTERA_AVALON_UART_INSTANCE ( UART_MC, uart_mc); -ALTERA_AVALON_UART_INSTANCE ( UART_WIFI, uart_wifi); -ALTERA_UP_AVALON_RS232_INSTANCE ( RS232_WIFI, rs232_wifi); - -/* - * Initialize the interrupt controller devices - * and then enable interrupts in the CPU. - * Called before alt_sys_init(). - * The "base" parameter is ignored and only - * present for backwards-compatibility. - */ - -void alt_irq_init ( const void* base ) -{ - ALTERA_NIOS2_QSYS_IRQ_INIT ( CPU, cpu); - alt_irq_cpu_enable_interrupts(); -} - -/* - * Initialize the non-interrupt controller devices. - * Called after alt_irq_init(). - */ - -void alt_sys_init( void ) -{ - ALTERA_AVALON_TIMER_INIT ( SYS_CLK_TIMER, sys_clk_timer); - ALTERA_AVALON_JTAG_UART_INIT ( JTAG_UART_0, jtag_uart_0); - ALTERA_AVALON_SYSID_QSYS_INIT ( SYSID, sysid); - ALTERA_AVALON_UART_INIT ( UART_MC, uart_mc); - ALTERA_AVALON_UART_INIT ( UART_WIFI, uart_wifi); - ALTERA_UP_AVALON_RS232_INIT ( RS232_WIFI, rs232_wifi); -} diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/libucosii_bsp.a b/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/libucosii_bsp.a deleted file mode 100644 index d317eb9e..00000000 Binary files a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/libucosii_bsp.a and /dev/null differ diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/linker.h b/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/linker.h deleted file mode 100644 index 1c77d824..00000000 --- a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/linker.h +++ /dev/null @@ -1,101 +0,0 @@ -/* - * linker.h - Linker script mapping information - * - * Machine generated for CPU 'cpu' in SOPC Builder design 'system' - * SOPC Builder design path: C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system.sopcinfo - * - * Generated: Sun Mar 02 19:03:50 MST 2014 - */ - -/* - * DO NOT MODIFY THIS FILE - * - * Changing this file will have subtle consequences - * which will almost certainly lead to a nonfunctioning - * system. If you do modify this file, be aware that your - * changes will be overwritten and lost when this file - * is generated again. - * - * DO NOT MODIFY THIS FILE - */ - -/* - * License Agreement - * - * Copyright (c) 2008 - * Altera Corporation, San Jose, California, USA. - * All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - * This agreement shall be governed in all respects by the laws of the State - * of California and by the laws of the United States of America. - */ - -#ifndef __LINKER_H_ -#define __LINKER_H_ - - -/* - * BSP controls alt_load() behavior in crt0. - * - */ - -#define ALT_LOAD_EXPLICITLY_CONTROLLED - - -/* - * Base address and span (size in bytes) of each linker region - * - */ - -#define RESET_REGION_BASE 0x1000000 -#define RESET_REGION_SPAN 32 -#define SDRAM_REGION_BASE 0x1000020 -#define SDRAM_REGION_SPAN 16777184 - - -/* - * Devices associated with code sections - * - */ - -#define ALT_EXCEPTIONS_DEVICE SDRAM -#define ALT_RESET_DEVICE SDRAM -#define ALT_RODATA_DEVICE SDRAM -#define ALT_RWDATA_DEVICE SDRAM -#define ALT_TEXT_DEVICE SDRAM - - -/* - * Initialization code at the reset address is allowed (e.g. no external bootloader). - * - */ - -#define ALT_ALLOW_CODE_AT_RESET - - -/* - * The alt_load() facility is called from crt0 to copy sections into RAM. - * - */ - -#define ALT_LOAD_COPY_RWDATA - -#endif /* __LINKER_H_ */ diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/linker.x b/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/linker.x deleted file mode 100644 index edd3ddf3..00000000 --- a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/linker.x +++ /dev/null @@ -1,385 +0,0 @@ -/* - * linker.x - Linker script - * - * Machine generated for CPU 'cpu' in SOPC Builder design 'system' - * SOPC Builder design path: C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system.sopcinfo - * - * Generated: Sun Mar 02 19:03:50 MST 2014 - */ - -/* - * DO NOT MODIFY THIS FILE - * - * Changing this file will have subtle consequences - * which will almost certainly lead to a nonfunctioning - * system. If you do modify this file, be aware that your - * changes will be overwritten and lost when this file - * is generated again. - * - * DO NOT MODIFY THIS FILE - */ - -/* - * License Agreement - * - * Copyright (c) 2008 - * Altera Corporation, San Jose, California, USA. - * All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - * This agreement shall be governed in all respects by the laws of the State - * of California and by the laws of the United States of America. - */ - -MEMORY -{ - reset : ORIGIN = 0x1000000, LENGTH = 32 - sdram : ORIGIN = 0x1000020, LENGTH = 16777184 -} - -/* Define symbols for each memory base-address */ -__alt_mem_sdram = 0x1000000; - -OUTPUT_FORMAT( "elf32-littlenios2", - "elf32-littlenios2", - "elf32-littlenios2" ) -OUTPUT_ARCH( nios2 ) -ENTRY( _start ) - -/* - * The alt_load() facility is enabled. This typically happens when there isn't - * an external bootloader (e.g. flash bootloader). - * The LMA (aka physical address) of each loaded section is - * set to the .text memory device. - * The HAL alt_load() routine called from crt0 copies sections from - * the .text memory to RAM as needed. - */ - -SECTIONS -{ - - /* - * Output sections associated with reset and exceptions (they have to be first) - */ - - .entry : - { - KEEP (*(.entry)) - } > reset - - .exceptions : - { - PROVIDE (__ram_exceptions_start = ABSOLUTE(.)); - . = ALIGN(0x20); - KEEP (*(.irq)); - KEEP (*(.exceptions.entry.label)); - KEEP (*(.exceptions.entry.user)); - KEEP (*(.exceptions.entry)); - KEEP (*(.exceptions.irqtest.user)); - KEEP (*(.exceptions.irqtest)); - KEEP (*(.exceptions.irqhandler.user)); - KEEP (*(.exceptions.irqhandler)); - KEEP (*(.exceptions.irqreturn.user)); - KEEP (*(.exceptions.irqreturn)); - KEEP (*(.exceptions.notirq.label)); - KEEP (*(.exceptions.notirq.user)); - KEEP (*(.exceptions.notirq)); - KEEP (*(.exceptions.soft.user)); - KEEP (*(.exceptions.soft)); - KEEP (*(.exceptions.unknown.user)); - KEEP (*(.exceptions.unknown)); - KEEP (*(.exceptions.exit.label)); - KEEP (*(.exceptions.exit.user)); - KEEP (*(.exceptions.exit)); - KEEP (*(.exceptions)); - PROVIDE (__ram_exceptions_end = ABSOLUTE(.)); - } > sdram - - PROVIDE (__flash_exceptions_start = LOADADDR(.exceptions)); - - .text : - { - /* - * All code sections are merged into the text output section, along with - * the read only data sections. - * - */ - - PROVIDE (stext = ABSOLUTE(.)); - - *(.interp) - *(.hash) - *(.dynsym) - *(.dynstr) - *(.gnu.version) - *(.gnu.version_d) - *(.gnu.version_r) - *(.rel.init) - *(.rela.init) - *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) - *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) - *(.rel.fini) - *(.rela.fini) - *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) - *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) - *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) - *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) - *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) - *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) - *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) - *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) - *(.rel.ctors) - *(.rela.ctors) - *(.rel.dtors) - *(.rela.dtors) - *(.rel.got) - *(.rela.got) - *(.rel.sdata .rel.sdata.* .rel.gnu.linkonce.s.*) - *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*) - *(.rel.sbss .rel.sbss.* .rel.gnu.linkonce.sb.*) - *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*) - *(.rel.sdata2 .rel.sdata2.* .rel.gnu.linkonce.s2.*) - *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*) - *(.rel.sbss2 .rel.sbss2.* .rel.gnu.linkonce.sb2.*) - *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*) - *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) - *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) - *(.rel.plt) - *(.rela.plt) - *(.rel.dyn) - - KEEP (*(.init)) - *(.plt) - *(.text .stub .text.* .gnu.linkonce.t.*) - - /* .gnu.warning sections are handled specially by elf32.em. */ - - *(.gnu.warning.*) - KEEP (*(.fini)) - PROVIDE (__etext = ABSOLUTE(.)); - PROVIDE (_etext = ABSOLUTE(.)); - PROVIDE (etext = ABSOLUTE(.)); - - *(.eh_frame_hdr) - /* Ensure the __preinit_array_start label is properly aligned. We - could instead move the label definition inside the section, but - the linker would then create the section even if it turns out to - be empty, which isn't pretty. */ - . = ALIGN(4); - PROVIDE (__preinit_array_start = ABSOLUTE(.)); - *(.preinit_array) - PROVIDE (__preinit_array_end = ABSOLUTE(.)); - PROVIDE (__init_array_start = ABSOLUTE(.)); - *(.init_array) - PROVIDE (__init_array_end = ABSOLUTE(.)); - PROVIDE (__fini_array_start = ABSOLUTE(.)); - *(.fini_array) - PROVIDE (__fini_array_end = ABSOLUTE(.)); - SORT(CONSTRUCTORS) - KEEP (*(.eh_frame)) - *(.gcc_except_table) - *(.dynamic) - PROVIDE (__CTOR_LIST__ = ABSOLUTE(.)); - KEEP (*(.ctors)) - KEEP (*(SORT(.ctors.*))) - PROVIDE (__CTOR_END__ = ABSOLUTE(.)); - PROVIDE (__DTOR_LIST__ = ABSOLUTE(.)); - KEEP (*(.dtors)) - KEEP (*(SORT(.dtors.*))) - PROVIDE (__DTOR_END__ = ABSOLUTE(.)); - KEEP (*(.jcr)) - . = ALIGN(4); - } > sdram = 0x3a880100 /* Nios II NOP instruction */ - - .rodata : - { - PROVIDE (__ram_rodata_start = ABSOLUTE(.)); - . = ALIGN(4); - *(.rodata .rodata.* .gnu.linkonce.r.*) - *(.rodata1) - . = ALIGN(4); - PROVIDE (__ram_rodata_end = ABSOLUTE(.)); - } > sdram - - PROVIDE (__flash_rodata_start = LOADADDR(.rodata)); - - /* - * - * This section's LMA is set to the .text region. - * crt0 will copy to this section's specified mapped region virtual memory address (VMA) - * - * .rwdata region equals the .text region, and is set to be loaded into .text region. - * This requires two copies of .rwdata in the .text region. One read writable at VMA. - * and one read-only at LMA. crt0 will copy from LMA to VMA on reset - * - */ - - .rwdata LOADADDR (.rodata) + SIZEOF (.rodata) : AT ( LOADADDR (.rodata) + SIZEOF (.rodata)+ SIZEOF (.rwdata) ) - { - PROVIDE (__ram_rwdata_start = ABSOLUTE(.)); - . = ALIGN(4); - *(.got.plt) *(.got) - *(.data1) - *(.data .data.* .gnu.linkonce.d.*) - - _gp = ABSOLUTE(. + 0x8000); - PROVIDE(gp = _gp); - - *(.rwdata .rwdata.*) - *(.sdata .sdata.* .gnu.linkonce.s.*) - *(.sdata2 .sdata2.* .gnu.linkonce.s2.*) - - . = ALIGN(4); - _edata = ABSOLUTE(.); - PROVIDE (edata = ABSOLUTE(.)); - PROVIDE (__ram_rwdata_end = ABSOLUTE(.)); - } > sdram - - PROVIDE (__flash_rwdata_start = LOADADDR(.rwdata)); - - /* - * - * This section's LMA is set to the .text region. - * crt0 will copy to this section's specified mapped region virtual memory address (VMA) - * - */ - - .bss LOADADDR (.rwdata) + SIZEOF (.rwdata) : AT ( LOADADDR (.rwdata) + SIZEOF (.rwdata) ) - { - __bss_start = ABSOLUTE(.); - PROVIDE (__sbss_start = ABSOLUTE(.)); - PROVIDE (___sbss_start = ABSOLUTE(.)); - - *(.dynsbss) - *(.sbss .sbss.* .gnu.linkonce.sb.*) - *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*) - *(.scommon) - - PROVIDE (__sbss_end = ABSOLUTE(.)); - PROVIDE (___sbss_end = ABSOLUTE(.)); - - *(.dynbss) - *(.bss .bss.* .gnu.linkonce.b.*) - *(COMMON) - - . = ALIGN(4); - __bss_end = ABSOLUTE(.); - } > sdram - - /* - * - * One output section mapped to the associated memory device for each of - * the available memory devices. These are not used by default, but can - * be used by user applications by using the .section directive. - * - * The output section used for the heap is treated in a special way, - * i.e. the symbols "end" and "_end" are added to point to the heap start. - * - * Because alt_load() is enabled, these sections have - * their LMA set to be loaded into the .text memory region. - * However, the alt_load() code will NOT automatically copy - * these sections into their mapped memory region. - * - */ - - /* - * - * This section's LMA is set to the .text region. - * crt0 will copy to this section's specified mapped region virtual memory address (VMA) - * - */ - - .sdram LOADADDR (.bss) + SIZEOF (.bss) : AT ( LOADADDR (.bss) + SIZEOF (.bss) ) - { - PROVIDE (_alt_partition_sdram_start = ABSOLUTE(.)); - *(.sdram. sdram.*) - . = ALIGN(4); - PROVIDE (_alt_partition_sdram_end = ABSOLUTE(.)); - _end = ABSOLUTE(.); - end = ABSOLUTE(.); - __alt_stack_base = ABSOLUTE(.); - } > sdram - - PROVIDE (_alt_partition_sdram_load_addr = LOADADDR(.sdram)); - - /* - * Stabs debugging sections. - * - */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - /* DWARF debug sections. - Symbols in the DWARF debugging sections are relative to the beginning - of the section so we begin them at 0. */ - /* DWARF 1 */ - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - /* GNU DWARF 1 extensions */ - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - /* DWARF 1.1 and DWARF 2 */ - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - /* DWARF 2 */ - .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - /* SGI/MIPS DWARF 2 extensions */ - .debug_weaknames 0 : { *(.debug_weaknames) } - .debug_funcnames 0 : { *(.debug_funcnames) } - .debug_typenames 0 : { *(.debug_typenames) } - .debug_varnames 0 : { *(.debug_varnames) } - - /* Altera debug extensions */ - .debug_alt_sim_info 0 : { *(.debug_alt_sim_info) } -} - -/* provide a pointer for the stack */ - -/* - * Don't override this, override the __alt_stack_* symbols instead. - */ -__alt_data_end = 0x2000000; - -/* - * The next two symbols define the location of the default stack. You can - * override them to move the stack to a different memory. - */ -PROVIDE( __alt_stack_pointer = __alt_data_end ); -PROVIDE( __alt_stack_limit = __alt_stack_base ); - -/* - * This symbol controls where the start of the heap is. If the stack is - * contiguous with the heap then the stack will contract as memory is - * allocated to the heap. - * Override this symbol to put the heap in a different memory. - */ -PROVIDE( __alt_heap_start = end ); -PROVIDE( __alt_heap_limit = 0x2000000 ); diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/memory.gdb b/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/memory.gdb deleted file mode 100644 index ce491d95..00000000 --- a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/memory.gdb +++ /dev/null @@ -1,50 +0,0 @@ -# memory.gdb - GDB memory region definitions -# -# Machine generated for CPU 'cpu' in SOPC Builder design 'system' -# SOPC Builder design path: C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system.sopcinfo -# -# Generated: Sun Mar 02 19:03:50 MST 2014 - -# DO NOT MODIFY THIS FILE -# -# Changing this file will have subtle consequences -# which will almost certainly lead to a nonfunctioning -# system. If you do modify this file, be aware that your -# changes will be overwritten and lost when this file -# is generated again. -# -# DO NOT MODIFY THIS FILE - -# License Agreement -# -# Copyright (c) 2008 -# Altera Corporation, San Jose, California, USA. -# All rights reserved. -# -# Permission is hereby granted, free of charge, to any person obtaining a -# copy of this software and associated documentation files (the "Software"), -# to deal in the Software without restriction, including without limitation -# the rights to use, copy, modify, merge, publish, distribute, sublicense, -# and/or sell copies of the Software, and to permit persons to whom the -# Software is furnished to do so, subject to the following conditions: -# -# The above copyright notice and this permission notice shall be included in -# all copies or substantial portions of the Software. -# -# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER -# DEALINGS IN THE SOFTWARE. -# -# This agreement shall be governed in all respects by the laws of the State -# of California and by the laws of the United States of America. - -# Define memory regions for each memory connected to the CPU. -# The cache attribute is specified which improves GDB performance -# by allowing GDB to cache memory contents on the host. - -# sdram -memory 0x1000000 0x2000000 cache diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/obj/HAL/src/alt_alarm_start.o b/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/obj/HAL/src/alt_alarm_start.o deleted file mode 100644 index 4363d3bb..00000000 Binary files a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/obj/HAL/src/alt_alarm_start.o and /dev/null differ diff --git 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You can create such a Makefile with -# the nios2-app-generate-makefile or nios2-lib-generate-makefile -# commands. -# -# The following variables must be defined before including this file: -# -# ALT_LIBRARY_ROOT_DIR -# Contains the path to the BSP top-level (aka root) directory -#------------------------------------------------------------------------------ - -#------------------------------------------------------------------------------ -# PATHS -#------------------------------------------------------------------------------ - - - -# Path to the provided linker script. -BSP_LINKER_SCRIPT := $(ALT_LIBRARY_ROOT_DIR)/linker.x - -# Include paths: -# The path to root of all header files that a library wishes to make -# available for an application's use is specified here. Note that this -# may not be *all* folders within a hierarchy. For example, if it is -# desired that the application developer type: -# #include -# #include -# With files laid out like this: -# /inc/sockets.h -# /inc/ip/tcpip.h -# -# Then, only /inc need be added to the list of include -# directories. Alternatively, if you wish to be able to directly include -# all files in a hierarchy, separate paths to each folder in that -# hierarchy must be defined. - -# The following are the "base" set of include paths for a BSP. -# These paths are appended to the list that individual software -# components, drivers, etc., add in the generated portion of this -# file (below). -ALT_INCLUDE_DIRS_TO_APPEND += \ - $(ALT_LIBRARY_ROOT_DIR) \ - $(ALT_LIBRARY_ROOT_DIR)/drivers/inc - -# Additions to linker library search-path: -# Here we provide a path to "our self" for the application to construct a -# "-L " out of. This should contain a list of directories, -# relative to the library root, of all directories with .a files to link -# against. -ALT_LIBRARY_DIRS += $(ALT_LIBRARY_ROOT_DIR) - - -#------------------------------------------------------------------------------ -# COMPILATION FLAGS -#------------------------------------------------------------------------------ -# Default C pre-processor flags for a BSP: -ALT_CPPFLAGS += -DSYSTEM_BUS_WIDTH=32 \ - -pipe - - -#------------------------------------------------------------------------------ -# MANAGED CONTENT -# -# All content between the lines "START MANAGED" and "END MANAGED" below is -# generated based on variables in the BSP settings file when the -# nios2-bsp-generate-files command is invoked. If you wish to persist any -# information pertaining to the build process, it is recomended that you -# utilize the BSP settings mechanism to do so. -#------------------------------------------------------------------------------ -#START MANAGED - -# The following TYPE comment allows tools to identify the 'type' of target this -# makefile is associated with. -# TYPE: BSP_PUBLIC_MAKEFILE - -# This following VERSION comment indicates the version of the tool used to -# generate this makefile. A makefile variable is provided for VERSION as well. -# ACDS_VERSION: 12.1sp1 -ACDS_VERSION := 12.1sp1 - -# This following BUILD_NUMBER comment indicates the build number of the tool -# used to generate this makefile. -# BUILD_NUMBER: 243 - -# Quartus Generated JDI File. Required for resolving node instance ID's with -# design component names. -JDI_FILE := C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.jdi - -# Qsys--generated SOPCINFO file. Required for resolving node instance ID's with -# design component names. -SOPCINFO_FILE := C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system.sopcinfo - -# Big-Endian operation. -# setting BIG_ENDIAN is false -ALT_CFLAGS += -EL - -# Path to the provided C language runtime initialization code. -BSP_CRT0 := $(ALT_LIBRARY_ROOT_DIR)/obj/HAL/src/crt0.o - -# Name of BSP library as provided to linker using the "-msys-lib" flag or -# linker script GROUP command. -# setting BSP_SYS_LIB is ucosii_bsp -BSP_SYS_LIB := ucosii_bsp -ELF_PATCH_FLAG += --thread_model ucosii - -# Type identifier of the BSP library -# setting BSP_TYPE is ucosii -ALT_CPPFLAGS += -D__hal__ -BSP_TYPE := ucosii - -# CPU Name -# setting CPU_NAME is cpu -CPU_NAME = cpu -ELF_PATCH_FLAG += --cpu_name $(CPU_NAME) - -# Hardware Divider present. -# setting HARDWARE_DIVIDE is false -ALT_CFLAGS += -mno-hw-div - -# Hardware Multiplier present. -# setting HARDWARE_MULTIPLY is true -ALT_CFLAGS += -mhw-mul - -# Hardware Mulx present. -# setting HARDWARE_MULX is false -ALT_CFLAGS += -mno-hw-mulx - -# Debug Core present. -# setting HAS_DEBUG_CORE is true -CPU_HAS_DEBUG_CORE = 1 - -# Qsys generated design -# setting QSYS is 1 -QSYS := 1 -ELF_PATCH_FLAG += --qsys true - -# Design Name -# setting SOPC_NAME is system -SOPC_NAME := system - -# SopcBuilder Simulation Enabled -# setting SOPC_SIMULATION_ENABLED is false -ELF_PATCH_FLAG += --simulation_enabled false - -# The SOPC System ID -# setting SOPC_SYSID is 0 -SOPC_SYSID_FLAG += --id=0 -ELF_PATCH_FLAG += --id 0 - -# The SOPC System ID Base Address -# setting SOPC_SYSID_BASE_ADDRESS is 0x20010c0 -SOPC_SYSID_FLAG += --sidp=0x20010c0 -ELF_PATCH_FLAG += --sidp 0x20010c0 - -# The SOPC Timestamp -# setting SOPC_TIMESTAMP is 1393806947 -SOPC_SYSID_FLAG += --timestamp=1393806947 -ELF_PATCH_FLAG += --timestamp 1393806947 - -# Small-footprint (polled mode) driver none -# setting altera_avalon_jtag_uart_driver.enable_small_driver is false - -# Enable driver ioctl() support. This feature is not compatible with the -# 'small' driver; ioctl() support will not be compiled if either the UART -# 'enable_small_driver' or HAL 'enable_reduced_device_drivers' settings are -# enabled. none -# setting altera_avalon_uart_driver.enable_ioctl is false - -# Small-footprint (polled mode) driver none -# setting altera_avalon_uart_driver.enable_small_driver is false - -# Build a custom version of newlib with the specified space-separated compiler -# flags. The custom newlib build will be placed in the <bsp root>/newlib -# directory, and will be used only for applications that utilize this BSP. -# setting hal.custom_newlib_flags is none - -# Enable support for a subset of the C++ language. This option increases code -# footprint by adding support for C++ constructors. Certain features, such as -# multiple inheritance and exceptions are not supported. If false, adds -# -DALT_NO_C_PLUS_PLUS to ALT_CPPFLAGS in public.mk, and reduces code -# footprint. none -# setting hal.enable_c_plus_plus is true - -# When your application exits, close file descriptors, call C++ destructors, -# etc. Code footprint can be reduced by disabling clean exit. If disabled, adds -# -DALT_NO_CLEAN_EXIT to ALT_CPPFLAGS and -Wl,--defsym, exit=_exit to -# ALT_LDFLAGS in public.mk. none -# setting hal.enable_clean_exit is true - -# Add exit() support. This option increases code footprint if your "main()" -# routine does "return" or call "exit()". If false, adds -DALT_NO_EXIT to -# ALT_CPPFLAGS in public.mk, and reduces footprint none -# setting hal.enable_exit is true - -# Causes code to be compiled with gprof profiling enabled and the application -# ELF to be linked with the GPROF library. If true, adds -DALT_PROVIDE_GMON to -# ALT_CPPFLAGS and -pg to ALT_CFLAGS in public.mk. none -# setting hal.enable_gprof is false - -# Enables lightweight device driver API. This reduces code and data footprint -# by removing the HAL layer that maps device names (e.g. /dev/uart0) to file -# descriptors. Instead, driver routines are called directly. The open(), -# close(), and lseek() routines will always fail if called. The read(), -# write(), fstat(), ioctl(), and isatty() routines only work for the stdio -# devices. If true, adds -DALT_USE_DIRECT_DRIVERS to ALT_CPPFLAGS in public.mk. -# The Altera Host and read-only ZIP file systems can't be used if -# hal.enable_lightweight_device_driver_api is true. -# setting hal.enable_lightweight_device_driver_api is false - -# Adds code to emulate multiply and divide instructions in case they are -# executed but aren't present in the CPU. Normally this isn't required because -# the compiler won't use multiply and divide instructions that aren't present -# in the CPU. If false, adds -DALT_NO_INSTRUCTION_EMULATION to ALT_CPPFLAGS in -# public.mk. none -# setting hal.enable_mul_div_emulation is false -ALT_CPPFLAGS += -DALT_NO_INSTRUCTION_EMULATION - -# Certain drivers are compiled with reduced functionality to reduce code -# footprint. Not all drivers observe this setting. The altera_avalon_uart and -# altera_avalon_jtag_uart drivers switch from interrupt-driven to polled -# operation. CAUTION: Several device drivers are disabled entirely. These -# include the altera_avalon_cfi_flash, altera_avalon_epcs_flash_controller, and -# altera_avalon_lcd_16207 drivers. This can result in certain API (HAL flash -# access routines) to fail. You can define a symbol provided by each driver to -# prevent it from being removed. If true, adds -DALT_USE_SMALL_DRIVERS to -# ALT_CPPFLAGS in public.mk. none -# setting hal.enable_reduced_device_drivers is false - -# Turns on HAL runtime stack checking feature. Enabling this setting causes -# additional code to be placed into each subroutine call to generate an -# exception if a stack collision occurs with the heap or statically allocated -# data. If true, adds -DALT_STACK_CHECK and -mstack-check to ALT_CPPFLAGS in -# public.mk. none -# setting hal.enable_runtime_stack_checking is false - -# The BSP is compiled with optimizations to speedup HDL simulation such as -# initializing the cache, clearing the .bss section, and skipping long delay -# loops. If true, adds -DALT_SIM_OPTIMIZE to ALT_CPPFLAGS in public.mk. When -# this setting is true, the BSP shouldn't be used to build applications that -# are expected to run real hardware. -# setting hal.enable_sim_optimize is false - -# Causes the small newlib (C library) to be used. This reduces code and data -# footprint at the expense of reduced functionality. Several newlib features -# are removed such as floating-point support in printf(), stdin input routines, -# and buffered I/O. The small C library is not compatible with Micrium -# MicroC/OS-II. If true, adds -msmallc to ALT_LDFLAGS in public.mk. none -# setting hal.enable_small_c_library is false - -# Enable SOPC Builder System ID. If a System ID SOPC Builder component is -# connected to the CPU associated with this BSP, it will be enabled in the -# creation of command-line arguments to download an ELF to the target. -# Otherwise, system ID and timestamp values are left out of public.mk for -# application Makefile "download-elf" target definition. With the system ID -# check disabled, the Nios II EDS tools will not automatically ensure that the -# application .elf file (and BSP it is linked against) corresponds to the -# hardware design on the target. If false, adds --accept-bad-sysid to -# SOPC_SYSID_FLAG in public.mk. none -# setting hal.enable_sopc_sysid_check is true - -# Enable BSP generation to query if SOPC system is big endian. If true ignores -# export of 'ALT_CFLAGS += -EB' to public.mk if big endian system. If true -# ignores export of 'ALT_CFLAGS += -EL' if little endian system. none -# setting hal.make.ignore_system_derived.big_endian is false - -# Enable BSP generation to query if SOPC system has a debug core present. If -# true ignores export of 'CPU_HAS_DEBUG_CORE = 1' to public.mk if a debug core -# is found in the system. If true ignores export of 'CPU_HAS_DEBUG_CORE = 0' if -# no debug core is found in the system. none -# setting hal.make.ignore_system_derived.debug_core_present is false - -# Enable BSP generation to query if SOPC system has FPU present. If true -# ignores export of 'ALT_CFLAGS += -mhard-float' to public.mk if FPU is found -# in the system. If true ignores export of 'ALT_CFLAGS += -mhard-soft' if FPU -# is not found in the system. none -# setting hal.make.ignore_system_derived.fpu_present is false - -# Enable BSP generation to query if SOPC system has hardware divide present. If -# true ignores export of 'ALT_CFLAGS += -mno-hw-div' to public.mk if no -# division is found in system. If true ignores export of 'ALT_CFLAGS += -# -mhw-div' if division is found in the system. none -# setting hal.make.ignore_system_derived.hardware_divide_present is false - -# Enable BSP generation to query if SOPC system floating point custom -# instruction with a divider is present. If true ignores export of 'ALT_CFLAGS -# += -mcustom-fpu-cfg=60-2' and 'ALT_LDFLAGS += -mcustom-fpu-cfg=60-2' to -# public.mk if the custom instruction is found in the system. none -# setting hal.make.ignore_system_derived.hardware_fp_cust_inst_divider_present is false - -# Enable BSP generation to query if SOPC system floating point custom -# instruction without a divider is present. If true ignores export of -# 'ALT_CFLAGS += -mcustom-fpu-cfg=60-1' and 'ALT_LDFLAGS += -# -mcustom-fpu-cfg=60-1' to public.mk if the custom instruction is found in the -# system. none -# setting hal.make.ignore_system_derived.hardware_fp_cust_inst_no_divider_present is false - -# Enable BSP generation to query if SOPC system has multiplier present. If true -# ignores export of 'ALT_CFLAGS += -mno-hw-mul' to public.mk if no multiplier -# is found in the system. If true ignores export of 'ALT_CFLAGS += -mhw-mul' if -# multiplier is found in the system. none -# setting hal.make.ignore_system_derived.hardware_multiplier_present is false - -# Enable BSP generation to query if SOPC system has hardware mulx present. If -# true ignores export of 'ALT_CFLAGS += -mno-hw-mulx' to public.mk if no mulx -# is found in the system. If true ignores export of 'ALT_CFLAGS += -mhw-mulx' -# if mulx is found in the system. none -# setting hal.make.ignore_system_derived.hardware_mulx_present is false - -# Enable BSP generation to query if SOPC system has simulation enabled. If true -# ignores export of 'ELF_PATCH_FLAG += --simulation_enabled' to public.mk. none -# setting hal.make.ignore_system_derived.sopc_simulation_enabled is false - -# Enable BSP generation to query SOPC system for system ID base address. If -# true ignores export of 'SOPC_SYSID_FLAG += --sidp=
' and -# 'ELF_PATCH_FLAG += --sidp=
' to public.mk. none -# setting hal.make.ignore_system_derived.sopc_system_base_address is false - -# Enable BSP generation to query SOPC system for system ID. If true ignores -# export of 'SOPC_SYSID_FLAG += --id=' and 'ELF_PATCH_FLAG += -# --id=' to public.mk. none -# setting hal.make.ignore_system_derived.sopc_system_id is false - -# Enable BSP generation to query SOPC system for system timestamp. If true -# ignores export of 'SOPC_SYSID_FLAG += --timestamp=' and -# 'ELF_PATCH_FLAG += --timestamp=' to public.mk. none -# setting hal.make.ignore_system_derived.sopc_system_timestamp is false - -# Slave descriptor of STDERR character-mode device. This setting is used by the -# ALT_STDERR family of defines in system.h. none -# setting hal.stderr is jtag_uart_0 -ELF_PATCH_FLAG += --stderr_dev jtag_uart_0 - -# Slave descriptor of STDIN character-mode device. This setting is used by the -# ALT_STDIN family of defines in system.h. none -# setting hal.stdin is jtag_uart_0 -ELF_PATCH_FLAG += --stdin_dev jtag_uart_0 - -# Slave descriptor of STDOUT character-mode device. This setting is used by the -# ALT_STDOUT family of defines in system.h. none -# setting hal.stdout is jtag_uart_0 -ELF_PATCH_FLAG += --stdout_dev jtag_uart_0 - - -#------------------------------------------------------------------------------ -# SOFTWARE COMPONENT & DRIVER INCLUDE PATHS -#------------------------------------------------------------------------------ - -ALT_INCLUDE_DIRS += $(ALT_LIBRARY_ROOT_DIR)/UCOSII/inc -ALT_INCLUDE_DIRS += $(ALT_LIBRARY_ROOT_DIR)/HAL/inc - -#------------------------------------------------------------------------------ -# SOFTWARE COMPONENT & DRIVER PRODUCED ALT_CPPFLAGS ADDITIONS -#------------------------------------------------------------------------------ - -ALT_CPPFLAGS += -D__ucosii__ - -#END MANAGED - - -#------------------------------------------------------------------------------ -# LIBRARY INFORMATION -#------------------------------------------------------------------------------ -# Assemble the name of the BSP *.a file using the BSP library name -# (BSP_SYS_LIB) in generated content above. -BSP_LIB := lib$(BSP_SYS_LIB).a - -# Additional libraries to link against: -# An application including this file will prefix each library with "-l". -# For example, to include the Newlib math library "m" is included, which -# becomes "-lm" when linking the application. -ALT_LIBRARY_NAMES += m - -# Additions to linker dependencies: -# An application Makefile will typically add these directly to the list -# of dependencies required to build the executable target(s). The BSP -# library (*.a) file is specified here. -ALT_LDDEPS += $(ALT_LIBRARY_ROOT_DIR)/$(BSP_LIB) - -# Is this library "Makeable"? -# Add to list of root library directories that support running 'make' -# to build them. Because libraries may or may not have a Makefile in their -# root, appending to this variable tells an application to run 'make' in -# the library root to build/update this library. -MAKEABLE_LIBRARY_ROOT_DIRS += $(ALT_LIBRARY_ROOT_DIR) - -# Additional Assembler Flags -# -gdwarf2 flag is required for stepping through assembly code -ALT_ASFLAGS += -gdwarf2 - -#------------------------------------------------------------------------------ -# FINAL INCLUDE PATH LIST -#------------------------------------------------------------------------------ -# Append static include paths to paths specified by OS/driver/sw package -# additions to the BSP thus giving them precedence in case a BSP addition -# is attempting to override BSP sources. -ALT_INCLUDE_DIRS += $(ALT_INCLUDE_DIRS_TO_APPEND) - - - diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/settings.bsp b/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/settings.bsp deleted file mode 100644 index f49df209..00000000 --- a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/settings.bsp +++ /dev/null @@ -1,1807 +0,0 @@ - - - ucosii - default - 2-Mar-2014 7:03:49 PM - 1393812229544 - C:\Users\gongal\NewRepARCap\MCandWifiTestDE0\software\MCandWifiTestDE0_bsp - .\settings.bsp - C:\Users\gongal\NewRepARCap\MCandWifiTestDE0\system.sopcinfo - default - cpu - 1.9 - - hal.sys_clk_timer - ALT_SYS_CLK - UnquotedString - sys_clk_timer - none - system_h_define - Slave descriptor of the system clock timer device. This device provides a periodic interrupt ("tick") and is typically required for RTOS use. This setting defines the value of ALT_SYS_CLK in system.h. - none - false - common - - - hal.timestamp_timer - ALT_TIMESTAMP_CLK - UnquotedString - none - none - system_h_define - Slave descriptor of timestamp timer device. This device is used by Altera HAL timestamp drivers for high-resolution time measurement. This setting defines the value of ALT_TIMESTAMP_CLK in system.h. - none - false - common - - - hal.max_file_descriptors - ALT_MAX_FD - DecimalNumber - 32 - 32 - system_h_define - Determines the number of file descriptors statically allocated. This setting defines the value of ALT_MAX_FD in system.h. - If hal.enable_lightweight_device_driver_api is true, there are no file descriptors so this setting is ignored. If hal.enable_lightweight_device_driver_api is false, this setting must be at least 4 because HAL needs a file descriptor for /dev/null, /dev/stdin, /dev/stdout, and /dev/stderr. - false - - - - hal.enable_instruction_related_exceptions_api - ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API - BooleanDefineOnly - false - false - system_h_define - Enables API for registering handlers to service instruction-related exceptions. Enabling this setting increases the size of the exception entry code. - These exception types can be generated if various processor options are enabled, such as the MMU, MPU, or other advanced exception types. - false - - - - hal.linker.allow_code_at_reset - ALT_ALLOW_CODE_AT_RESET - Boolean - 1 - 0 - none - Indicates if initialization code is allowed at the reset address. If true, defines the macro ALT_ALLOW_CODE_AT_RESET in linker.h. - If true, defines the macro ALT_ALLOW_CODE_AT_RESET in linker.h. This setting is typically false if an external bootloader (e.g. flash bootloader) is present. - false - - - - hal.linker.enable_alt_load - NONE - Boolean - 1 - 0 - none - Enables the alt_load() facility. The alt_load() facility copies sections from the .text memory into RAM. If true, this setting sets up the VMA/LMA of sections in linker.x to allow them to be loaded into the .text memory. - This setting is typically false if an external bootloader (e.g. flash bootloader) is present. - false - - - - hal.linker.enable_alt_load_copy_rodata - NONE - Boolean - 0 - 0 - none - Causes the alt_load() facility to copy the .rodata section. If true, this setting defines the macro ALT_LOAD_COPY_RODATA in linker.h. - none - false - - - - hal.linker.enable_alt_load_copy_rwdata - NONE - Boolean - 1 - 0 - none - Causes the alt_load() facility to copy the .rwdata section. If true, this setting defines the macro ALT_LOAD_COPY_RWDATA in linker.h. - none - false - - - - hal.linker.enable_alt_load_copy_exceptions - NONE - Boolean - 0 - 0 - none - Causes the alt_load() facility to copy the .exceptions section. If true, this setting defines the macro ALT_LOAD_COPY_EXCEPTIONS in linker.h. - none - false - - - - hal.linker.enable_exception_stack - NONE - Boolean - 0 - 0 - none - Enables use of a separate exception stack. If true, defines the macro ALT_EXCEPTION_STACK in linker.h, adds a memory region called exception_stack to linker.x, and provides the symbols __alt_exception_stack_pointer and __alt_exception_stack_limit in linker.x. - The hal.linker.exception_stack_size and hal.linker.exception_stack_memory_region_name settings must also be valid. This setting must be false for MicroC/OS-II BSPs. The exception stack can be used to improve interrupt and other exception performance if the EIC is *not* used. - false - common - - - hal.linker.exception_stack_size - NONE - DecimalNumber - 1024 - 1024 - none - Size of the exception stack in bytes. - Only used if hal.linker.enable_exception_stack is true. - false - common - - - hal.linker.exception_stack_memory_region_name - NONE - UnquotedString - sdram - none - none - Name of the existing memory region that will be divided up to create the 'exception_stack' memory region. The selected region name will be adjusted automatically when the BSP is generated to create the 'exception_stack' memory region. - Only used if hal.linker.enable_exception_stack is true. - false - common - - - hal.linker.enable_interrupt_stack - NONE - Boolean - 0 - 0 - none - Enables use of a separate interrupt stack. If true, defines the macro ALT_INTERRUPT_STACK in linker.h, adds a memory region called interrupt_stack to linker.x, and provides the symbols __alt_interrupt_stack_pointer and __alt_interrupt_stack_limit in linker.x. - The hal.linker.interrupt_stack_size and hal.linker.interrupt_stack_memory_region_name settings must also be valid. This setting must be false for MicroC/OS-II BSPs. Only enable if the EIC is used exclusively. The exception stack can be used to improve interrupt and other exception performance if the EIC is *not* used. - false - common - - - hal.linker.interrupt_stack_size - NONE - DecimalNumber - 1024 - 1024 - none - Size of the interrupt stack in bytes. - Only used if hal.linker.enable_interrupt_stack is true. - false - common - - - hal.linker.interrupt_stack_memory_region_name - NONE - UnquotedString - sdram - none - none - Name of the existing memory region that will be divided up to create the 'interrupt_stack' memory region. The selected region name will be adjusted automatically when the BSP is generated to create the 'interrupt_stack' memory region. - Only used if hal.linker.enable_interrupt_stack is true. - false - common - - - hal.stdin - NONE - UnquotedString - jtag_uart_0 - none - system_h_define - Slave descriptor of STDIN character-mode device. This setting is used by the ALT_STDIN family of defines in system.h. - none - false - common - - - hal.stdout - NONE - UnquotedString - jtag_uart_0 - none - system_h_define - Slave descriptor of STDOUT character-mode device. This setting is used by the ALT_STDOUT family of defines in system.h. - none - false - common - - - hal.stderr - NONE - UnquotedString - jtag_uart_0 - none - system_h_define - Slave descriptor of STDERR character-mode device. This setting is used by the ALT_STDERR family of defines in system.h. - none - false - common - - - hal.log_port - NONE - UnquotedString - none - none - public_mk_define - Slave descriptor of debug logging character-mode device. If defined, it enables extra debug messages in the HAL source. This setting is used by the ALT_LOG_PORT family of defines in system.h. - none - false - none - - - hal.make.build_pre_process - BUILD_PRE_PROCESS - UnquotedString - none - none - makefile_variable - Command executed before BSP built. - none - false - none - - - hal.make.ar_pre_process - AR_PRE_PROCESS - UnquotedString - none - none - makefile_variable - Command executed before archiver execution. - none - false - none - - - hal.make.bsp_cflags_defined_symbols - BSP_CFLAGS_DEFINED_SYMBOLS - UnquotedString - none - none - makefile_variable - Preprocessor macros to define. A macro definition in this setting has the same effect as a "#define" in source code. Adding "-DALT_DEBUG" to this setting has the same effect as "#define ALT_DEBUG" in a souce file. Adding "-DFOO=1" to this setting is equivalent to the macro "#define FOO 1" in a source file. Macros defined with this setting are applied to all .S, .c, and C++ files in the BSP. This setting defines the value of BSP_CFLAGS_DEFINED_SYMBOLS in the BSP Makefile. - none - false - none - - - hal.make.ar_post_process - AR_POST_PROCESS - UnquotedString - none - none - makefile_variable - Command executed after archiver execution. - none - false - none - - - hal.make.as - AS - UnquotedString - nios2-elf-gcc - nios2-elf-gcc - makefile_variable - Assembler command. Note that CC is used for .S files. - none - false - none - - - hal.make.build_post_process - BUILD_POST_PROCESS - UnquotedString - none - none - makefile_variable - Command executed after BSP built. - none - false - none - - - hal.make.bsp_cflags_debug - BSP_CFLAGS_DEBUG - UnquotedString - -g - -g - makefile_variable - C/C++ compiler debug level. '-g' provides the default set of debug symbols typically required to debug a typical application. Omitting '-g' removes debug symbols from the ELF. This setting defines the value of BSP_CFLAGS_DEBUG in Makefile. - none - false - common - - - hal.make.ar - AR - UnquotedString - nios2-elf-ar - nios2-elf-ar - makefile_variable - Archiver command. Creates library files. - none - false - none - - - hal.make.rm - RM - UnquotedString - rm -f - rm -f - makefile_variable - Command used to remove files during 'clean' target. - none - false - none - - - hal.make.cxx_pre_process - CXX_PRE_PROCESS - UnquotedString - none - none - makefile_variable - Command executed before each C++ file is compiled. - none - false - none - - - hal.make.bsp_cflags_warnings - BSP_CFLAGS_WARNINGS - UnquotedString - -Wall - -Wall - makefile_variable - C/C++ compiler warning level. "-Wall" is commonly used.This setting defines the value of BSP_CFLAGS_WARNINGS in Makefile. - none - false - none - - - hal.make.bsp_arflags - BSP_ARFLAGS - UnquotedString - -src - -src - makefile_variable - Custom flags only passed to the archiver. This content of this variable is directly passed to the archiver rather than the more standard "ARFLAGS". The reason for this is that GNU Make assumes some default content in ARFLAGS. This setting defines the value of BSP_ARFLAGS in Makefile. - none - false - none - - - hal.make.bsp_cflags_optimization - BSP_CFLAGS_OPTIMIZATION - UnquotedString - -O0 - -O0 - makefile_variable - C/C++ compiler optimization level. "-O0" = no optimization,"-O2" = "normal" optimization, etc. "-O0" is recommended for code that you want to debug since compiler optimization can remove variables and produce non-sequential execution of code while debugging. This setting defines the value of BSP_CFLAGS_OPTIMIZATION in Makefile. - none - false - common - - - hal.make.as_post_process - AS_POST_PROCESS - UnquotedString - none - none - makefile_variable - Command executed after each assembly file is compiled. - none - false - none - - - hal.make.cc_pre_process - CC_PRE_PROCESS - UnquotedString - none - none - makefile_variable - Command executed before each .c/.S file is compiled. - none - false - none - - - hal.make.bsp_asflags - BSP_ASFLAGS - UnquotedString - -Wa,-gdwarf2 - -Wa,-gdwarf2 - makefile_variable - Custom flags only passed to the assembler. This setting defines the value of BSP_ASFLAGS in Makefile. - none - false - none - - - hal.make.as_pre_process - AS_PRE_PROCESS - UnquotedString - none - none - makefile_variable - Command executed before each assembly file is compiled. - none - false - none - - - hal.make.bsp_cflags_undefined_symbols - BSP_CFLAGS_UNDEFINED_SYMBOLS - UnquotedString - none - none - makefile_variable - Preprocessor macros to undefine. Undefined macros are similar to defined macros, but replicate the "#undef" directive in source code. To undefine the macro FOO use the syntax "-u FOO" in this setting. This is equivalent to "#undef FOO" in a source file. Note: the syntax differs from macro definition (there is a space, i.e. "-u FOO" versus "-DFOO"). Macros defined with this setting are applied to all .S, .c, and C++ files in the BSP. This setting defines the value of BSP_CFLAGS_UNDEFINED_SYMBOLS in the BSP Makefile. - none - false - none - - - hal.make.cc_post_process - CC_POST_PROCESS - UnquotedString - none - none - makefile_variable - Command executed after each .c/.S file is compiled. - none - false - none - - - hal.make.cxx_post_process - CXX_POST_PROCESS - UnquotedString - none - none - makefile_variable - Command executed before each C++ file is compiled. - none - false - none - - - hal.make.cc - CC - UnquotedString - nios2-elf-gcc -xc - nios2-elf-gcc -xc - makefile_variable - C compiler command. - none - false - none - - - hal.make.bsp_cxx_flags - BSP_CXXFLAGS - UnquotedString - none - none - makefile_variable - Custom flags only passed to the C++ compiler. This setting defines the value of BSP_CXXFLAGS in Makefile. - none - false - none - - - hal.make.bsp_inc_dirs - BSP_INC_DIRS - UnquotedString - none - none - makefile_variable - Space separated list of extra include directories to scan for header files. Directories are relative to the top-level BSP directory. The -I prefix's added by the makefile so don't add it here. This setting defines the value of BSP_INC_DIRS in Makefile. - none - false - none - - - hal.make.cxx - CXX - UnquotedString - nios2-elf-gcc -xc++ - nios2-elf-gcc -xc++ - makefile_variable - C++ compiler command. - none - false - none - - - hal.make.bsp_cflags_user_flags - BSP_CFLAGS_USER_FLAGS - UnquotedString - none - none - makefile_variable - Custom flags passed to the compiler when compiling C, C++, and .S files. This setting defines the value of BSP_CFLAGS_USER_FLAGS in Makefile. - none - false - none - - - hal.make.ignore_system_derived.sopc_system_id - NONE - Boolean - 0 - 0 - public_mk_define - Enable BSP generation to query SOPC system for system ID. If true ignores export of 'SOPC_SYSID_FLAG += --id=<sysid>' and 'ELF_PATCH_FLAG += --id=<sysid>' to public.mk. - none - false - none - - - hal.make.ignore_system_derived.sopc_system_timestamp - NONE - Boolean - 0 - 0 - public_mk_define - Enable BSP generation to query SOPC system for system timestamp. If true ignores export of 'SOPC_SYSID_FLAG += --timestamp=<timestamp>' and 'ELF_PATCH_FLAG += --timestamp=<timestamp>' to public.mk. - none - false - none - - - hal.make.ignore_system_derived.sopc_system_base_address - NONE - Boolean - 0 - 0 - public_mk_define - Enable BSP generation to query SOPC system for system ID base address. If true ignores export of 'SOPC_SYSID_FLAG += --sidp=<address>' and 'ELF_PATCH_FLAG += --sidp=<address>' to public.mk. - none - false - none - - - hal.make.ignore_system_derived.sopc_simulation_enabled - NONE - Boolean - 0 - 0 - public_mk_define - Enable BSP generation to query if SOPC system has simulation enabled. If true ignores export of 'ELF_PATCH_FLAG += --simulation_enabled' to public.mk. - none - false - none - - - hal.make.ignore_system_derived.fpu_present - NONE - Boolean - 0 - 0 - public_mk_define - Enable BSP generation to query if SOPC system has FPU present. If true ignores export of 'ALT_CFLAGS += -mhard-float' to public.mk if FPU is found in the system. If true ignores export of 'ALT_CFLAGS += -mhard-soft' if FPU is not found in the system. - none - false - none - - - hal.make.ignore_system_derived.hardware_multiplier_present - NONE - Boolean - 0 - 0 - public_mk_define - Enable BSP generation to query if SOPC system has multiplier present. If true ignores export of 'ALT_CFLAGS += -mno-hw-mul' to public.mk if no multiplier is found in the system. If true ignores export of 'ALT_CFLAGS += -mhw-mul' if multiplier is found in the system. - none - false - none - - - hal.make.ignore_system_derived.hardware_mulx_present - NONE - Boolean - 0 - 0 - public_mk_define - Enable BSP generation to query if SOPC system has hardware mulx present. If true ignores export of 'ALT_CFLAGS += -mno-hw-mulx' to public.mk if no mulx is found in the system. If true ignores export of 'ALT_CFLAGS += -mhw-mulx' if mulx is found in the system. - none - false - none - - - hal.make.ignore_system_derived.hardware_divide_present - NONE - Boolean - 0 - 0 - public_mk_define - Enable BSP generation to query if SOPC system has hardware divide present. If true ignores export of 'ALT_CFLAGS += -mno-hw-div' to public.mk if no division is found in system. If true ignores export of 'ALT_CFLAGS += -mhw-div' if division is found in the system. - none - false - none - - - hal.make.ignore_system_derived.debug_core_present - NONE - Boolean - 0 - 0 - public_mk_define - Enable BSP generation to query if SOPC system has a debug core present. If true ignores export of 'CPU_HAS_DEBUG_CORE = 1' to public.mk if a debug core is found in the system. If true ignores export of 'CPU_HAS_DEBUG_CORE = 0' if no debug core is found in the system. - none - false - none - - - hal.make.ignore_system_derived.big_endian - NONE - Boolean - 0 - 0 - public_mk_define - Enable BSP generation to query if SOPC system is big endian. If true ignores export of 'ALT_CFLAGS += -EB' to public.mk if big endian system. If true ignores export of 'ALT_CFLAGS += -EL' if little endian system. - none - false - none - - - hal.make.ignore_system_derived.hardware_fp_cust_inst_divider_present - NONE - Boolean - 0 - 0 - public_mk_define - Enable BSP generation to query if SOPC system floating point custom instruction with a divider is present. If true ignores export of 'ALT_CFLAGS += -mcustom-fpu-cfg=60-2' and 'ALT_LDFLAGS += -mcustom-fpu-cfg=60-2' to public.mk if the custom instruction is found in the system. - none - false - none - - - hal.make.ignore_system_derived.hardware_fp_cust_inst_no_divider_present - NONE - Boolean - 0 - 0 - public_mk_define - Enable BSP generation to query if SOPC system floating point custom instruction without a divider is present. If true ignores export of 'ALT_CFLAGS += -mcustom-fpu-cfg=60-1' and 'ALT_LDFLAGS += -mcustom-fpu-cfg=60-1' to public.mk if the custom instruction is found in the system. - none - false - none - - - hal.enable_exit - ALT_NO_EXIT - Boolean - 1 - 1 - public_mk_define - Add exit() support. This option increases code footprint if your "main()" routine does "return" or call "exit()". If false, adds -DALT_NO_EXIT to ALT_CPPFLAGS in public.mk, and reduces footprint - none - false - none - - - hal.enable_small_c_library - NONE - Boolean - 0 - 0 - public_mk_define - Causes the small newlib (C library) to be used. This reduces code and data footprint at the expense of reduced functionality. Several newlib features are removed such as floating-point support in printf(), stdin input routines, and buffered I/O. The small C library is not compatible with Micrium MicroC/OS-II. If true, adds -msmallc to ALT_LDFLAGS in public.mk. - none - false - common - - - hal.enable_clean_exit - ALT_NO_CLEAN_EXIT - Boolean - 1 - 1 - public_mk_define - When your application exits, close file descriptors, call C++ destructors, etc. Code footprint can be reduced by disabling clean exit. If disabled, adds -DALT_NO_CLEAN_EXIT to ALT_CPPFLAGS and -Wl,--defsym, exit=_exit to ALT_LDFLAGS in public.mk. - none - false - none - - - hal.enable_runtime_stack_checking - ALT_STACK_CHECK - Boolean - 0 - 0 - public_mk_define - Turns on HAL runtime stack checking feature. Enabling this setting causes additional code to be placed into each subroutine call to generate an exception if a stack collision occurs with the heap or statically allocated data. If true, adds -DALT_STACK_CHECK and -mstack-check to ALT_CPPFLAGS in public.mk. - none - false - none - - - hal.enable_gprof - ALT_PROVIDE_GMON - Boolean - 0 - 0 - public_mk_define - Causes code to be compiled with gprof profiling enabled and the application ELF to be linked with the GPROF library. If true, adds -DALT_PROVIDE_GMON to ALT_CPPFLAGS and -pg to ALT_CFLAGS in public.mk. - none - false - common - - - hal.enable_c_plus_plus - ALT_NO_C_PLUS_PLUS - Boolean - 1 - 1 - public_mk_define - Enable support for a subset of the C++ language. This option increases code footprint by adding support for C++ constructors. Certain features, such as multiple inheritance and exceptions are not supported. If false, adds -DALT_NO_C_PLUS_PLUS to ALT_CPPFLAGS in public.mk, and reduces code footprint. - none - false - none - - - hal.enable_reduced_device_drivers - ALT_USE_SMALL_DRIVERS - Boolean - 0 - 0 - public_mk_define - Certain drivers are compiled with reduced functionality to reduce code footprint. Not all drivers observe this setting. The altera_avalon_uart and altera_avalon_jtag_uart drivers switch from interrupt-driven to polled operation. CAUTION: Several device drivers are disabled entirely. These include the altera_avalon_cfi_flash, altera_avalon_epcs_flash_controller, and altera_avalon_lcd_16207 drivers. This can result in certain API (HAL flash access routines) to fail. You can define a symbol provided by each driver to prevent it from being removed. If true, adds -DALT_USE_SMALL_DRIVERS to ALT_CPPFLAGS in public.mk. - none - false - common - - - hal.enable_lightweight_device_driver_api - ALT_USE_DIRECT_DRIVERS - Boolean - 0 - 0 - public_mk_define - Enables lightweight device driver API. This reduces code and data footprint by removing the HAL layer that maps device names (e.g. /dev/uart0) to file descriptors. Instead, driver routines are called directly. The open(), close(), and lseek() routines will always fail if called. The read(), write(), fstat(), ioctl(), and isatty() routines only work for the stdio devices. If true, adds -DALT_USE_DIRECT_DRIVERS to ALT_CPPFLAGS in public.mk. - The Altera Host and read-only ZIP file systems can't be used if hal.enable_lightweight_device_driver_api is true. - false - none - - - hal.enable_mul_div_emulation - ALT_NO_INSTRUCTION_EMULATION - Boolean - 0 - 0 - public_mk_define - Adds code to emulate multiply and divide instructions in case they are executed but aren't present in the CPU. Normally this isn't required because the compiler won't use multiply and divide instructions that aren't present in the CPU. If false, adds -DALT_NO_INSTRUCTION_EMULATION to ALT_CPPFLAGS in public.mk. - none - false - none - - - hal.enable_sim_optimize - ALT_SIM_OPTIMIZE - Boolean - 0 - 0 - public_mk_define - The BSP is compiled with optimizations to speedup HDL simulation such as initializing the cache, clearing the .bss section, and skipping long delay loops. If true, adds -DALT_SIM_OPTIMIZE to ALT_CPPFLAGS in public.mk. - When this setting is true, the BSP shouldn't be used to build applications that are expected to run real hardware. - false - common - - - hal.enable_sopc_sysid_check - NONE - Boolean - 1 - 1 - public_mk_define - Enable SOPC Builder System ID. If a System ID SOPC Builder component is connected to the CPU associated with this BSP, it will be enabled in the creation of command-line arguments to download an ELF to the target. Otherwise, system ID and timestamp values are left out of public.mk for application Makefile "download-elf" target definition. With the system ID check disabled, the Nios II EDS tools will not automatically ensure that the application .elf file (and BSP it is linked against) corresponds to the hardware design on the target. If false, adds --accept-bad-sysid to SOPC_SYSID_FLAG in public.mk. - none - false - none - - - hal.custom_newlib_flags - CUSTOM_NEWLIB_FLAGS - UnquotedString - none - none - public_mk_define - Build a custom version of newlib with the specified space-separated compiler flags. - The custom newlib build will be placed in the &lt;bsp root>/newlib directory, and will be used only for applications that utilize this BSP. - false - none - - - hal.log_flags - ALT_LOG_FLAGS - DecimalNumber - 0 - 0 - public_mk_define - The value is assigned to ALT_LOG_FLAGS in the generated public.mk. See hal.log_port setting description. Values can be -1 through 3. - hal.log_port must be set for this to be used. - false - none - - - ucosii.os_max_tasks - OS_MAX_TASKS - DecimalNumber - 10 - 10 - system_h_define - Maximum number of tasks - none - false - - - - ucosii.os_lowest_prio - OS_LOWEST_PRIO - DecimalNumber - 20 - 20 - system_h_define - Lowest assignable priority - none - false - - - - ucosii.os_thread_safe_newlib - OS_THREAD_SAFE_NEWLIB - Boolean - 1 - 1 - system_h_define - Thread safe C library - none - false - - - - ucosii.miscellaneous.os_arg_chk_en - OS_ARG_CHK_EN - Boolean - 1 - 1 - system_h_define - Enable argument checking - none - false - - - - ucosii.miscellaneous.os_cpu_hooks_en - OS_CPU_HOOKS_EN - Boolean - 1 - 1 - system_h_define - Enable uCOS-II hooks - none - false - - - - ucosii.miscellaneous.os_debug_en - OS_DEBUG_EN - Boolean - 1 - 1 - system_h_define - Enable debug variables - none - false - - - - ucosii.miscellaneous.os_sched_lock_en - OS_SCHED_LOCK_EN - Boolean - 1 - 1 - system_h_define - Include code for OSSchedLock() and OSSchedUnlock() - none - false - - - - ucosii.miscellaneous.os_task_stat_en - OS_TASK_STAT_EN - Boolean - 1 - 1 - system_h_define - Enable statistics task - none - false - - - - ucosii.miscellaneous.os_task_stat_stk_chk_en - OS_TASK_STAT_STK_CHK_EN - Boolean - 1 - 1 - system_h_define - Check task stacks from statistics task - none - false - - - - ucosii.miscellaneous.os_tick_step_en - OS_TICK_STEP_EN - Boolean - 1 - 1 - system_h_define - Enable tick stepping feature for uCOS-View - none - false - - - - ucosii.miscellaneous.os_event_name_size - OS_EVENT_NAME_SIZE - DecimalNumber - 32 - 32 - system_h_define - Size of name of Event Control Block groups - none - false - - - - ucosii.miscellaneous.os_max_events - OS_MAX_EVENTS - DecimalNumber - 60 - 60 - system_h_define - Maximum number of event control blocks - none - false - - - - ucosii.miscellaneous.os_task_idle_stk_size - OS_TASK_IDLE_STK_SIZE - DecimalNumber - 512 - 512 - system_h_define - Idle task stack size - none - false - - - - ucosii.miscellaneous.os_task_stat_stk_size - OS_TASK_STAT_STK_SIZE - DecimalNumber - 512 - 512 - system_h_define - Statistics task stack size - none - false - - - - ucosii.task.os_task_change_prio_en - OS_TASK_CHANGE_PRIO_EN - Boolean - 1 - 1 - system_h_define - Include code for OSTaskChangePrio() - none - false - - - - ucosii.task.os_task_create_en - OS_TASK_CREATE_EN - Boolean - 1 - 1 - system_h_define - Include code for OSTaskCreate() - none - false - - - - ucosii.task.os_task_create_ext_en - OS_TASK_CREATE_EXT_EN - Boolean - 1 - 1 - system_h_define - Include code for OSTaskCreateExt() - none - false - - - - ucosii.task.os_task_del_en - OS_TASK_DEL_EN - Boolean - 1 - 1 - system_h_define - Include code for OSTaskDel() - none - false - - - - ucosii.task.os_task_name_size - OS_TASK_NAME_SIZE - DecimalNumber - 32 - 32 - system_h_define - Size of task name - none - false - - - - ucosii.task.os_task_profile_en - OS_TASK_PROFILE_EN - Boolean - 1 - 1 - system_h_define - Include data structure for run-time task profiling - none - false - - - - ucosii.task.os_task_query_en - OS_TASK_QUERY_EN - Boolean - 1 - 1 - system_h_define - Include code for OSTaskQuery - none - false - - - - ucosii.task.os_task_suspend_en - OS_TASK_SUSPEND_EN - Boolean - 1 - 1 - system_h_define - Include code for OSTaskSuspend() and OSTaskResume() - none - false - - - - ucosii.task.os_task_sw_hook_en - OS_TASK_SW_HOOK_EN - Boolean - 1 - 1 - system_h_define - Include code for OSTaskSwHook() - none - false - - - - ucosii.time.os_time_tick_hook_en - OS_TIME_TICK_HOOK_EN - Boolean - 1 - 1 - system_h_define - Include code for OSTimeTickHook() - none - false - - - - ucosii.time.os_time_dly_resume_en - OS_TIME_DLY_RESUME_EN - Boolean - 1 - 1 - system_h_define - Include code for OSTimeDlyResume() - none - false - - - - ucosii.time.os_time_dly_hmsm_en - OS_TIME_DLY_HMSM_EN - Boolean - 1 - 1 - system_h_define - Include code for OSTimeDlyHMSM() - none - false - - - - ucosii.time.os_time_get_set_en - OS_TIME_GET_SET_EN - Boolean - 1 - 1 - system_h_define - Include code for OSTimeGet and OSTimeSet() - none - false - - - - ucosii.os_flag_en - OS_FLAG_EN - Boolean - 1 - 1 - system_h_define - Enable code for Event Flags. CAUTION: This is required by the HAL and many Altera device drivers. - none - false - - - - ucosii.event_flag.os_flag_wait_clr_en - OS_FLAG_WAIT_CLR_EN - Boolean - 1 - 1 - system_h_define - Include code for Wait on Clear Event Flags. CAUTION: This is required by the HAL and many Altera device drivers. - none - false - - - - ucosii.event_flag.os_flag_accept_en - OS_FLAG_ACCEPT_EN - Boolean - 1 - 1 - system_h_define - Include code for OSFlagAccept(). CAUTION: This is required by the HAL and many Altera device drivers. - none - false - - - - ucosii.event_flag.os_flag_del_en - OS_FLAG_DEL_EN - Boolean - 1 - 1 - system_h_define - Include code for OSFlagDel(). CAUTION: This is required by the HAL and many Altera device drivers. - none - false - - - - ucosii.event_flag.os_flag_query_en - OS_FLAG_QUERY_EN - Boolean - 1 - 1 - system_h_define - Include code for OSFlagQuery(). CAUTION: This is required by the HAL and many Altera device drivers. - none - false - - - - ucosii.event_flag.os_flag_name_size - OS_FLAG_NAME_SIZE - DecimalNumber - 32 - 32 - system_h_define - Size of name of Event Flags group. CAUTION: This is required by the HAL and many Altera device drivers; use caution in reducing this value. - none - false - - - - ucosii.event_flag.os_flags_nbits - OS_FLAGS_NBITS - DecimalNumber - 16 - 16 - system_h_define - Event Flag bits (8,16,32). CAUTION: This is required by the HAL and many Altera device drivers; use caution in changing this value. - none - false - - - - ucosii.event_flag.os_max_flags - OS_MAX_FLAGS - DecimalNumber - 20 - 20 - system_h_define - Maximum number of Event Flags groups. CAUTION: This is required by the HAL and many Altera device drivers; use caution in reducing this value. - none - false - - - - ucosii.os_mutex_en - OS_MUTEX_EN - Boolean - 1 - 1 - system_h_define - Enable code for Mutex Semaphores - none - false - - - - ucosii.mutex.os_mutex_accept_en - OS_MUTEX_ACCEPT_EN - Boolean - 1 - 1 - system_h_define - Include code for OSMutexAccept() - none - false - - - - ucosii.mutex.os_mutex_del_en - OS_MUTEX_DEL_EN - Boolean - 1 - 1 - system_h_define - Include code for OSMutexDel() - none - false - - - - ucosii.mutex.os_mutex_query_en - OS_MUTEX_QUERY_EN - Boolean - 1 - 1 - system_h_define - Include code for OSMutexQuery - none - false - - - - ucosii.os_sem_en - OS_SEM_EN - Boolean - 1 - 1 - system_h_define - Enable code for semaphores. CAUTION: This is required by the HAL and many Altera device drivers. - none - false - - - - ucosii.semaphore.os_sem_accept_en - OS_SEM_ACCEPT_EN - Boolean - 1 - 1 - system_h_define - Include code for OSSemAccept(). CAUTION: This is required by the HAL and many Altera device drivers. - none - false - - - - ucosii.semaphore.os_sem_set_en - OS_SEM_SET_EN - Boolean - 1 - 1 - system_h_define - Include code for OSSemSet(). CAUTION: This is required by the HAL and many Altera device drivers. - none - false - - - - ucosii.semaphore.os_sem_del_en - OS_SEM_DEL_EN - Boolean - 1 - 1 - system_h_define - Include code for OSSemDel(). CAUTION: This is required by the HAL and many Altera device drivers. - none - false - - - - ucosii.semaphore.os_sem_query_en - OS_SEM_QUERY_EN - Boolean - 1 - 1 - system_h_define - Include code for OSSemQuery(). CAUTION: This is required by the HAL and many Altera device drivers. - none - false - - - - ucosii.os_mbox_en - OS_MBOX_EN - Boolean - 1 - 1 - system_h_define - Enable code for mailboxes - none - false - - - - ucosii.mailbox.os_mbox_accept_en - OS_MBOX_ACCEPT_EN - Boolean - 1 - 1 - system_h_define - Include code for OSMboxAccept() - none - false - - - - ucosii.mailbox.os_mbox_del_en - OS_MBOX_DEL_EN - Boolean - 1 - 1 - system_h_define - Include code for OSMboxDel() - none - false - - - - ucosii.mailbox.os_mbox_post_en - OS_MBOX_POST_EN - Boolean - 1 - 1 - system_h_define - Include code for OSMboxPost() - none - false - - - - ucosii.mailbox.os_mbox_post_opt_en - OS_MBOX_POST_OPT_EN - Boolean - 1 - 1 - system_h_define - Include code for OSMboxPostOpt() - none - false - - - - ucosii.mailbox.os_mbox_query_en - OS_MBOX_QUERY_EN - Boolean - 1 - 1 - system_h_define - Include code for OSMboxQuery() - none - false - - - - ucosii.os_q_en - OS_Q_EN - Boolean - 1 - 1 - system_h_define - Enable code for Queues - none - false - - - - ucosii.queue.os_q_accept_en - OS_Q_ACCEPT_EN - Boolean - 1 - 1 - system_h_define - Include code for OSQAccept() - none - false - - - - ucosii.queue.os_q_del_en - OS_Q_DEL_EN - Boolean - 1 - 1 - system_h_define - Include code for OSQDel() - none - false - - - - ucosii.queue.os_q_flush_en - OS_Q_FLUSH_EN - Boolean - 1 - 1 - system_h_define - Include code for OSQFlush() - none - false - - - - ucosii.queue.os_q_post_en - OS_Q_POST_EN - Boolean - 1 - 1 - system_h_define - Include code of OSQFlush() - none - false - - - - ucosii.queue.os_q_post_front_en - OS_Q_POST_FRONT_EN - Boolean - 1 - 1 - system_h_define - Include code for OSQPostFront() - none - false - - - - ucosii.queue.os_q_post_opt_en - OS_Q_POST_OPT_EN - Boolean - 1 - 1 - system_h_define - Include code for OSQPostOpt() - none - false - - - - ucosii.queue.os_q_query_en - OS_Q_QUERY_EN - Boolean - 1 - 1 - system_h_define - Include code for OSQQuery() - none - false - - - - ucosii.queue.os_max_qs - OS_MAX_QS - DecimalNumber - 20 - 20 - system_h_define - Maximum number of Queue Control Blocks - none - false - - - - ucosii.os_mem_en - OS_MEM_EN - Boolean - 1 - 1 - system_h_define - Enable code for memory management - none - false - - - - ucosii.memory.os_mem_query_en - OS_MEM_QUERY_EN - Boolean - 1 - 1 - system_h_define - Include code for OSMemQuery() - none - false - - - - ucosii.memory.os_mem_name_size - OS_MEM_NAME_SIZE - DecimalNumber - 32 - 32 - system_h_define - Size of memory partition name - none - false - - - - ucosii.memory.os_max_mem_part - OS_MAX_MEM_PART - DecimalNumber - 60 - 60 - system_h_define - Maximum number of memory partitions - none - false - - - - ucosii.os_tmr_en - OS_TMR_EN - Boolean - 0 - 0 - system_h_define - Enable code for timers - none - false - - - - ucosii.timer.os_task_tmr_stk_size - OS_TASK_TMR_STK_SIZE - DecimalNumber - 512 - 512 - system_h_define - Stack size for timer task - none - false - - - - ucosii.timer.os_task_tmr_prio - OS_TASK_TMR_PRIO - DecimalNumber - 0 - 0 - system_h_define - Priority of timer task (0=highest) - none - false - - - - ucosii.timer.os_tmr_cfg_max - OS_TMR_CFG_MAX - DecimalNumber - 16 - 16 - system_h_define - Maximum number of timers - none - false - - - - ucosii.timer.os_tmr_cfg_name_size - OS_TMR_CFG_NAME_SIZE - DecimalNumber - 16 - 16 - system_h_define - Size of timer name - none - false - - - - ucosii.timer.os_tmr_cfg_ticks_per_sec - OS_TMR_CFG_TICKS_PER_SEC - DecimalNumber - 10 - 10 - system_h_define - Rate at which timer management task runs (Hz) - none - false - - - - ucosii.timer.os_tmr_cfg_wheel_size - OS_TMR_CFG_WHEEL_SIZE - DecimalNumber - 2 - 2 - system_h_define - Size of timer wheel (number of spokes) - none - false - - - - altera_avalon_uart_driver.enable_small_driver - ALTERA_AVALON_UART_SMALL - BooleanDefineOnly - false - false - public_mk_define - Small-footprint (polled mode) driver - none - false - - - - altera_avalon_uart_driver.enable_ioctl - ALTERA_AVALON_UART_USE_IOCTL - BooleanDefineOnly - false - false - public_mk_define - Enable driver ioctl() support. This feature is not compatible with the 'small' driver; ioctl() support will not be compiled if either the UART 'enable_small_driver' or HAL 'enable_reduced_device_drivers' settings are enabled. - none - false - - - - altera_avalon_jtag_uart_driver.enable_small_driver - ALTERA_AVALON_JTAG_UART_SMALL - BooleanDefineOnly - false - false - public_mk_define - Small-footprint (polled mode) driver - none - false - - - - sdram - 0x01000000 - 0x01FFFFFF - 16777216 - memory - - - uart_mc - 0x02001000 - 0x0200101F - 32 - printable - - - pio_led - 0x02001020 - 0x0200103F - 32 - - - - uart_wifi - 0x02001040 - 0x0200105F - 32 - printable - - - sys_clk_timer - 0x02001060 - 0x0200107F - 32 - timer - - - pio_ir_emitter - 0x02001080 - 0x0200108F - 16 - - - - pio_sw - 0x02001090 - 0x0200109F - 16 - - - - pio_key_left - 0x020010A0 - 0x020010AF - 16 - - - - rs232_wifi - 0x020010B0 - 0x020010B7 - 8 - - - - jtag_uart_0 - 0x020010B8 - 0x020010BF - 8 - printable - - - sysid - 0x020010C0 - 0x020010C7 - 8 - - - - .text - sdram - - - .rodata - sdram - - - .rwdata - sdram - - - .bss - sdram - - - .heap - sdram - - - .stack - sdram - - \ No newline at end of file diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/summary.html b/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/summary.html deleted file mode 100644 index b0f5879a..00000000 --- a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/summary.html +++ /dev/null @@ -1,3946 +0,0 @@ - -Altera Nios II BSP Summary - -

BSP Description

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BSP Type:ucosii
SOPC Design File:C:\Users\gongal\NewRepARCap\MCandWifiTestDE0\system.sopcinfo
Quartus JDI File:default
CPU:cpu
BSP Settings File:.\settings.bsp
BSP Version:default
BSP Generated On:2-Mar-2014 7:03:49 PM
BSP Generated Timestamp:1393812229544
BSP Generated Location:C:\Users\gongal\NewRepARCap\MCandWifiTestDE0\software\MCandWifiTestDE0_bsp
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Nios II Memory Map

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Slave DescriptorAddress RangeSizeAttributes
sysid0x020010C0 - 0x020010C78 
jtag_uart_00x020010B8 - 0x020010BF8printable
rs232_wifi0x020010B0 - 0x020010B78 
pio_key_left0x020010A0 - 0x020010AF16 
pio_sw0x02001090 - 0x0200109F16 
pio_ir_emitter0x02001080 - 0x0200108F16 
sys_clk_timer0x02001060 - 0x0200107F32timer
uart_wifi0x02001040 - 0x0200105F32printable
pio_led0x02001020 - 0x0200103F32 
uart_mc0x02001000 - 0x0200101F32printable
sdram0x01000000 - 0x01FFFFFF16777216memory
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Linker Regions

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RegionAddress RangeSizeMemoryOffset
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Linker Section Mappings

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SectionRegion
.textsdram
.rodatasdram
.rwdatasdram
.bsssdram
.heapsdram
.stacksdram
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Settings

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Setting Name:altera_avalon_jtag_uart_driver.enable_small_driver
Identifier:ALTERA_AVALON_JTAG_UART_SMALL
Default Value:false
Value:false
Type:BooleanDefineOnly
Destination:public_mk_define
Description:Small-footprint (polled mode) driver
Restrictions:none
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Setting Name:altera_avalon_uart_driver.enable_ioctl
Identifier:ALTERA_AVALON_UART_USE_IOCTL
Default Value:false
Value:false
Type:BooleanDefineOnly
Destination:public_mk_define
Description:Enable driver ioctl() support. This feature is not compatible with the 'small' driver; ioctl() support will not be compiled if either the UART 'enable_small_driver' or HAL 'enable_reduced_device_drivers' settings are enabled.
Restrictions:none
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Setting Name:altera_avalon_uart_driver.enable_small_driver
Identifier:ALTERA_AVALON_UART_SMALL
Default Value:false
Value:false
Type:BooleanDefineOnly
Destination:public_mk_define
Description:Small-footprint (polled mode) driver
Restrictions:none
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Setting Name:hal.custom_newlib_flags
Identifier:CUSTOM_NEWLIB_FLAGS
Default Value:none
Value:none
Type:UnquotedString
Destination:public_mk_define
Description:Build a custom version of newlib with the specified space-separated compiler flags.
Restrictions:The custom newlib build will be placed in the &lt;bsp root>/newlib directory, and will be used only for applications that utilize this BSP.
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Setting Name:hal.enable_c_plus_plus
Identifier:ALT_NO_C_PLUS_PLUS
Default Value:1
Value:1
Type:Boolean
Destination:public_mk_define
Description:Enable support for a subset of the C++ language. This option increases code footprint by adding support for C++ constructors. Certain features, such as multiple inheritance and exceptions are not supported. If false, adds -DALT_NO_C_PLUS_PLUS to ALT_CPPFLAGS in public.mk, and reduces code footprint.
Restrictions:none
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Setting Name:hal.enable_clean_exit
Identifier:ALT_NO_CLEAN_EXIT
Default Value:1
Value:1
Type:Boolean
Destination:public_mk_define
Description:When your application exits, close file descriptors, call C++ destructors, etc. Code footprint can be reduced by disabling clean exit. If disabled, adds -DALT_NO_CLEAN_EXIT to ALT_CPPFLAGS and -Wl,--defsym, exit=_exit to ALT_LDFLAGS in public.mk.
Restrictions:none
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Setting Name:hal.enable_exit
Identifier:ALT_NO_EXIT
Default Value:1
Value:1
Type:Boolean
Destination:public_mk_define
Description:Add exit() support. This option increases code footprint if your "main()" routine does "return" or call "exit()". If false, adds -DALT_NO_EXIT to ALT_CPPFLAGS in public.mk, and reduces footprint
Restrictions:none
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Setting Name:hal.enable_gprof
Identifier:ALT_PROVIDE_GMON
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Causes code to be compiled with gprof profiling enabled and the application ELF to be linked with the GPROF library. If true, adds -DALT_PROVIDE_GMON to ALT_CPPFLAGS and -pg to ALT_CFLAGS in public.mk.
Restrictions:none
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Setting Name:hal.enable_instruction_related_exceptions_api
Identifier:ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API
Default Value:false
Value:false
Type:BooleanDefineOnly
Destination:system_h_define
Description:Enables API for registering handlers to service instruction-related exceptions. Enabling this setting increases the size of the exception entry code.
Restrictions:These exception types can be generated if various processor options are enabled, such as the MMU, MPU, or other advanced exception types.
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Setting Name:hal.enable_lightweight_device_driver_api
Identifier:ALT_USE_DIRECT_DRIVERS
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Enables lightweight device driver API. This reduces code and data footprint by removing the HAL layer that maps device names (e.g. /dev/uart0) to file descriptors. Instead, driver routines are called directly. The open(), close(), and lseek() routines will always fail if called. The read(), write(), fstat(), ioctl(), and isatty() routines only work for the stdio devices. If true, adds -DALT_USE_DIRECT_DRIVERS to ALT_CPPFLAGS in public.mk.
Restrictions:The Altera Host and read-only ZIP file systems can't be used if hal.enable_lightweight_device_driver_api is true.
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Setting Name:hal.enable_mul_div_emulation
Identifier:ALT_NO_INSTRUCTION_EMULATION
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Adds code to emulate multiply and divide instructions in case they are executed but aren't present in the CPU. Normally this isn't required because the compiler won't use multiply and divide instructions that aren't present in the CPU. If false, adds -DALT_NO_INSTRUCTION_EMULATION to ALT_CPPFLAGS in public.mk.
Restrictions:none
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Setting Name:hal.enable_reduced_device_drivers
Identifier:ALT_USE_SMALL_DRIVERS
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Certain drivers are compiled with reduced functionality to reduce code footprint. Not all drivers observe this setting. The altera_avalon_uart and altera_avalon_jtag_uart drivers switch from interrupt-driven to polled operation. CAUTION: Several device drivers are disabled entirely. These include the altera_avalon_cfi_flash, altera_avalon_epcs_flash_controller, and altera_avalon_lcd_16207 drivers. This can result in certain API (HAL flash access routines) to fail. You can define a symbol provided by each driver to prevent it from being removed. If true, adds -DALT_USE_SMALL_DRIVERS to ALT_CPPFLAGS in public.mk.
Restrictions:none
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Setting Name:hal.enable_runtime_stack_checking
Identifier:ALT_STACK_CHECK
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Turns on HAL runtime stack checking feature. Enabling this setting causes additional code to be placed into each subroutine call to generate an exception if a stack collision occurs with the heap or statically allocated data. If true, adds -DALT_STACK_CHECK and -mstack-check to ALT_CPPFLAGS in public.mk.
Restrictions:none
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Setting Name:hal.enable_sim_optimize
Identifier:ALT_SIM_OPTIMIZE
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:The BSP is compiled with optimizations to speedup HDL simulation such as initializing the cache, clearing the .bss section, and skipping long delay loops. If true, adds -DALT_SIM_OPTIMIZE to ALT_CPPFLAGS in public.mk.
Restrictions:When this setting is true, the BSP shouldn't be used to build applications that are expected to run real hardware.
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Setting Name:hal.enable_small_c_library
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Causes the small newlib (C library) to be used. This reduces code and data footprint at the expense of reduced functionality. Several newlib features are removed such as floating-point support in printf(), stdin input routines, and buffered I/O. The small C library is not compatible with Micrium MicroC/OS-II. If true, adds -msmallc to ALT_LDFLAGS in public.mk.
Restrictions:none
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Setting Name:hal.enable_sopc_sysid_check
Identifier:NONE
Default Value:1
Value:1
Type:Boolean
Destination:public_mk_define
Description:Enable SOPC Builder System ID. If a System ID SOPC Builder component is connected to the CPU associated with this BSP, it will be enabled in the creation of command-line arguments to download an ELF to the target. Otherwise, system ID and timestamp values are left out of public.mk for application Makefile "download-elf" target definition. With the system ID check disabled, the Nios II EDS tools will not automatically ensure that the application .elf file (and BSP it is linked against) corresponds to the hardware design on the target. If false, adds --accept-bad-sysid to SOPC_SYSID_FLAG in public.mk.
Restrictions:none
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Setting Name:hal.linker.allow_code_at_reset
Identifier:ALT_ALLOW_CODE_AT_RESET
Default Value:0
Value:1
Type:Boolean
Destination:none
Description:Indicates if initialization code is allowed at the reset address. If true, defines the macro ALT_ALLOW_CODE_AT_RESET in linker.h.
Restrictions:If true, defines the macro ALT_ALLOW_CODE_AT_RESET in linker.h. This setting is typically false if an external bootloader (e.g. flash bootloader) is present.
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Setting Name:hal.linker.enable_alt_load
Identifier:NONE
Default Value:0
Value:1
Type:Boolean
Destination:none
Description:Enables the alt_load() facility. The alt_load() facility copies sections from the .text memory into RAM. If true, this setting sets up the VMA/LMA of sections in linker.x to allow them to be loaded into the .text memory.
Restrictions:This setting is typically false if an external bootloader (e.g. flash bootloader) is present.
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Setting Name:hal.linker.enable_alt_load_copy_exceptions
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:none
Description:Causes the alt_load() facility to copy the .exceptions section. If true, this setting defines the macro ALT_LOAD_COPY_EXCEPTIONS in linker.h.
Restrictions:none
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Setting Name:hal.linker.enable_alt_load_copy_rodata
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:none
Description:Causes the alt_load() facility to copy the .rodata section. If true, this setting defines the macro ALT_LOAD_COPY_RODATA in linker.h.
Restrictions:none
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Setting Name:hal.linker.enable_alt_load_copy_rwdata
Identifier:NONE
Default Value:0
Value:1
Type:Boolean
Destination:none
Description:Causes the alt_load() facility to copy the .rwdata section. If true, this setting defines the macro ALT_LOAD_COPY_RWDATA in linker.h.
Restrictions:none
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Setting Name:hal.linker.enable_exception_stack
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:none
Description:Enables use of a separate exception stack. If true, defines the macro ALT_EXCEPTION_STACK in linker.h, adds a memory region called exception_stack to linker.x, and provides the symbols __alt_exception_stack_pointer and __alt_exception_stack_limit in linker.x.
Restrictions:The hal.linker.exception_stack_size and hal.linker.exception_stack_memory_region_name settings must also be valid. This setting must be false for MicroC/OS-II BSPs. The exception stack can be used to improve interrupt and other exception performance if the EIC is *not* used.
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Setting Name:hal.linker.enable_interrupt_stack
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:none
Description:Enables use of a separate interrupt stack. If true, defines the macro ALT_INTERRUPT_STACK in linker.h, adds a memory region called interrupt_stack to linker.x, and provides the symbols __alt_interrupt_stack_pointer and __alt_interrupt_stack_limit in linker.x.
Restrictions:The hal.linker.interrupt_stack_size and hal.linker.interrupt_stack_memory_region_name settings must also be valid. This setting must be false for MicroC/OS-II BSPs. Only enable if the EIC is used exclusively. The exception stack can be used to improve interrupt and other exception performance if the EIC is *not* used.
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Setting Name:hal.linker.exception_stack_memory_region_name
Identifier:NONE
Default Value:none
Value:sdram
Type:UnquotedString
Destination:none
Description:Name of the existing memory region that will be divided up to create the 'exception_stack' memory region. The selected region name will be adjusted automatically when the BSP is generated to create the 'exception_stack' memory region.
Restrictions:Only used if hal.linker.enable_exception_stack is true.
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Setting Name:hal.linker.exception_stack_size
Identifier:NONE
Default Value:1024
Value:1024
Type:DecimalNumber
Destination:none
Description:Size of the exception stack in bytes.
Restrictions:Only used if hal.linker.enable_exception_stack is true.
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Setting Name:hal.linker.interrupt_stack_memory_region_name
Identifier:NONE
Default Value:none
Value:sdram
Type:UnquotedString
Destination:none
Description:Name of the existing memory region that will be divided up to create the 'interrupt_stack' memory region. The selected region name will be adjusted automatically when the BSP is generated to create the 'interrupt_stack' memory region.
Restrictions:Only used if hal.linker.enable_interrupt_stack is true.
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Setting Name:hal.linker.interrupt_stack_size
Identifier:NONE
Default Value:1024
Value:1024
Type:DecimalNumber
Destination:none
Description:Size of the interrupt stack in bytes.
Restrictions:Only used if hal.linker.enable_interrupt_stack is true.
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Setting Name:hal.log_flags
Identifier:ALT_LOG_FLAGS
Default Value:0
Value:0
Type:DecimalNumber
Destination:public_mk_define
Description:The value is assigned to ALT_LOG_FLAGS in the generated public.mk. See hal.log_port setting description. Values can be -1 through 3.
Restrictions:hal.log_port must be set for this to be used.
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Setting Name:hal.log_port
Identifier:NONE
Default Value:none
Value:none
Type:UnquotedString
Destination:public_mk_define
Description:Slave descriptor of debug logging character-mode device. If defined, it enables extra debug messages in the HAL source. This setting is used by the ALT_LOG_PORT family of defines in system.h.
Restrictions:none
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Setting Name:hal.make.ar
Identifier:AR
Default Value:nios2-elf-ar
Value:nios2-elf-ar
Type:UnquotedString
Destination:makefile_variable
Description:Archiver command. Creates library files.
Restrictions:none
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Setting Name:hal.make.ar_post_process
Identifier:AR_POST_PROCESS
Default Value:none
Value:none
Type:UnquotedString
Destination:makefile_variable
Description:Command executed after archiver execution.
Restrictions:none
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Setting Name:hal.make.ar_pre_process
Identifier:AR_PRE_PROCESS
Default Value:none
Value:none
Type:UnquotedString
Destination:makefile_variable
Description:Command executed before archiver execution.
Restrictions:none
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Setting Name:hal.make.as
Identifier:AS
Default Value:nios2-elf-gcc
Value:nios2-elf-gcc
Type:UnquotedString
Destination:makefile_variable
Description:Assembler command. Note that CC is used for .S files.
Restrictions:none
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Setting Name:hal.make.as_post_process
Identifier:AS_POST_PROCESS
Default Value:none
Value:none
Type:UnquotedString
Destination:makefile_variable
Description:Command executed after each assembly file is compiled.
Restrictions:none
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Setting Name:hal.make.as_pre_process
Identifier:AS_PRE_PROCESS
Default Value:none
Value:none
Type:UnquotedString
Destination:makefile_variable
Description:Command executed before each assembly file is compiled.
Restrictions:none
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Setting Name:hal.make.bsp_arflags
Identifier:BSP_ARFLAGS
Default Value:-src
Value:-src
Type:UnquotedString
Destination:makefile_variable
Description:Custom flags only passed to the archiver. This content of this variable is directly passed to the archiver rather than the more standard "ARFLAGS". The reason for this is that GNU Make assumes some default content in ARFLAGS. This setting defines the value of BSP_ARFLAGS in Makefile.
Restrictions:none
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Setting Name:hal.make.bsp_asflags
Identifier:BSP_ASFLAGS
Default Value:-Wa,-gdwarf2
Value:-Wa,-gdwarf2
Type:UnquotedString
Destination:makefile_variable
Description:Custom flags only passed to the assembler. This setting defines the value of BSP_ASFLAGS in Makefile.
Restrictions:none
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Setting Name:hal.make.bsp_cflags_debug
Identifier:BSP_CFLAGS_DEBUG
Default Value:-g
Value:-g
Type:UnquotedString
Destination:makefile_variable
Description:C/C++ compiler debug level. '-g' provides the default set of debug symbols typically required to debug a typical application. Omitting '-g' removes debug symbols from the ELF. This setting defines the value of BSP_CFLAGS_DEBUG in Makefile.
Restrictions:none
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Setting Name:hal.make.bsp_cflags_defined_symbols
Identifier:BSP_CFLAGS_DEFINED_SYMBOLS
Default Value:none
Value:none
Type:UnquotedString
Destination:makefile_variable
Description:Preprocessor macros to define. A macro definition in this setting has the same effect as a "#define" in source code. Adding "-DALT_DEBUG" to this setting has the same effect as "#define ALT_DEBUG" in a souce file. Adding "-DFOO=1" to this setting is equivalent to the macro "#define FOO 1" in a source file. Macros defined with this setting are applied to all .S, .c, and C++ files in the BSP. This setting defines the value of BSP_CFLAGS_DEFINED_SYMBOLS in the BSP Makefile.
Restrictions:none
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Setting Name:hal.make.bsp_cflags_optimization
Identifier:BSP_CFLAGS_OPTIMIZATION
Default Value:-O0
Value:-O0
Type:UnquotedString
Destination:makefile_variable
Description:C/C++ compiler optimization level. "-O0" = no optimization,"-O2" = "normal" optimization, etc. "-O0" is recommended for code that you want to debug since compiler optimization can remove variables and produce non-sequential execution of code while debugging. This setting defines the value of BSP_CFLAGS_OPTIMIZATION in Makefile.
Restrictions:none
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Setting Name:hal.make.bsp_cflags_undefined_symbols
Identifier:BSP_CFLAGS_UNDEFINED_SYMBOLS
Default Value:none
Value:none
Type:UnquotedString
Destination:makefile_variable
Description:Preprocessor macros to undefine. Undefined macros are similar to defined macros, but replicate the "#undef" directive in source code. To undefine the macro FOO use the syntax "-u FOO" in this setting. This is equivalent to "#undef FOO" in a source file. Note: the syntax differs from macro definition (there is a space, i.e. "-u FOO" versus "-DFOO"). Macros defined with this setting are applied to all .S, .c, and C++ files in the BSP. This setting defines the value of BSP_CFLAGS_UNDEFINED_SYMBOLS in the BSP Makefile.
Restrictions:none
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Setting Name:hal.make.bsp_cflags_user_flags
Identifier:BSP_CFLAGS_USER_FLAGS
Default Value:none
Value:none
Type:UnquotedString
Destination:makefile_variable
Description:Custom flags passed to the compiler when compiling C, C++, and .S files. This setting defines the value of BSP_CFLAGS_USER_FLAGS in Makefile.
Restrictions:none
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Setting Name:hal.make.bsp_cflags_warnings
Identifier:BSP_CFLAGS_WARNINGS
Default Value:-Wall
Value:-Wall
Type:UnquotedString
Destination:makefile_variable
Description:C/C++ compiler warning level. "-Wall" is commonly used.This setting defines the value of BSP_CFLAGS_WARNINGS in Makefile.
Restrictions:none
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Setting Name:hal.make.bsp_cxx_flags
Identifier:BSP_CXXFLAGS
Default Value:none
Value:none
Type:UnquotedString
Destination:makefile_variable
Description:Custom flags only passed to the C++ compiler. This setting defines the value of BSP_CXXFLAGS in Makefile.
Restrictions:none
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Setting Name:hal.make.bsp_inc_dirs
Identifier:BSP_INC_DIRS
Default Value:none
Value:none
Type:UnquotedString
Destination:makefile_variable
Description:Space separated list of extra include directories to scan for header files. Directories are relative to the top-level BSP directory. The -I prefix's added by the makefile so don't add it here. This setting defines the value of BSP_INC_DIRS in Makefile.
Restrictions:none
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Setting Name:hal.make.build_post_process
Identifier:BUILD_POST_PROCESS
Default Value:none
Value:none
Type:UnquotedString
Destination:makefile_variable
Description:Command executed after BSP built.
Restrictions:none
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Setting Name:hal.make.build_pre_process
Identifier:BUILD_PRE_PROCESS
Default Value:none
Value:none
Type:UnquotedString
Destination:makefile_variable
Description:Command executed before BSP built.
Restrictions:none
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Setting Name:hal.make.cc
Identifier:CC
Default Value:nios2-elf-gcc -xc
Value:nios2-elf-gcc -xc
Type:UnquotedString
Destination:makefile_variable
Description:C compiler command.
Restrictions:none
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Setting Name:hal.make.cc_post_process
Identifier:CC_POST_PROCESS
Default Value:none
Value:none
Type:UnquotedString
Destination:makefile_variable
Description:Command executed after each .c/.S file is compiled.
Restrictions:none
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Setting Name:hal.make.cc_pre_process
Identifier:CC_PRE_PROCESS
Default Value:none
Value:none
Type:UnquotedString
Destination:makefile_variable
Description:Command executed before each .c/.S file is compiled.
Restrictions:none
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Setting Name:hal.make.cxx
Identifier:CXX
Default Value:nios2-elf-gcc -xc++
Value:nios2-elf-gcc -xc++
Type:UnquotedString
Destination:makefile_variable
Description:C++ compiler command.
Restrictions:none
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Setting Name:hal.make.cxx_post_process
Identifier:CXX_POST_PROCESS
Default Value:none
Value:none
Type:UnquotedString
Destination:makefile_variable
Description:Command executed before each C++ file is compiled.
Restrictions:none
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Setting Name:hal.make.cxx_pre_process
Identifier:CXX_PRE_PROCESS
Default Value:none
Value:none
Type:UnquotedString
Destination:makefile_variable
Description:Command executed before each C++ file is compiled.
Restrictions:none
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Setting Name:hal.make.ignore_system_derived.big_endian
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Enable BSP generation to query if SOPC system is big endian. If true ignores export of 'ALT_CFLAGS += -EB' to public.mk if big endian system. If true ignores export of 'ALT_CFLAGS += -EL' if little endian system.
Restrictions:none
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Setting Name:hal.make.ignore_system_derived.debug_core_present
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Enable BSP generation to query if SOPC system has a debug core present. If true ignores export of 'CPU_HAS_DEBUG_CORE = 1' to public.mk if a debug core is found in the system. If true ignores export of 'CPU_HAS_DEBUG_CORE = 0' if no debug core is found in the system.
Restrictions:none
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Setting Name:hal.make.ignore_system_derived.fpu_present
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Enable BSP generation to query if SOPC system has FPU present. If true ignores export of 'ALT_CFLAGS += -mhard-float' to public.mk if FPU is found in the system. If true ignores export of 'ALT_CFLAGS += -mhard-soft' if FPU is not found in the system.
Restrictions:none
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Setting Name:hal.make.ignore_system_derived.hardware_divide_present
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Enable BSP generation to query if SOPC system has hardware divide present. If true ignores export of 'ALT_CFLAGS += -mno-hw-div' to public.mk if no division is found in system. If true ignores export of 'ALT_CFLAGS += -mhw-div' if division is found in the system.
Restrictions:none
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Setting Name:hal.make.ignore_system_derived.hardware_fp_cust_inst_divider_present
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Enable BSP generation to query if SOPC system floating point custom instruction with a divider is present. If true ignores export of 'ALT_CFLAGS += -mcustom-fpu-cfg=60-2' and 'ALT_LDFLAGS += -mcustom-fpu-cfg=60-2' to public.mk if the custom instruction is found in the system.
Restrictions:none
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Setting Name:hal.make.ignore_system_derived.hardware_fp_cust_inst_no_divider_present
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Enable BSP generation to query if SOPC system floating point custom instruction without a divider is present. If true ignores export of 'ALT_CFLAGS += -mcustom-fpu-cfg=60-1' and 'ALT_LDFLAGS += -mcustom-fpu-cfg=60-1' to public.mk if the custom instruction is found in the system.
Restrictions:none
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Setting Name:hal.make.ignore_system_derived.hardware_multiplier_present
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Enable BSP generation to query if SOPC system has multiplier present. If true ignores export of 'ALT_CFLAGS += -mno-hw-mul' to public.mk if no multiplier is found in the system. If true ignores export of 'ALT_CFLAGS += -mhw-mul' if multiplier is found in the system.
Restrictions:none
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Setting Name:hal.make.ignore_system_derived.hardware_mulx_present
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Enable BSP generation to query if SOPC system has hardware mulx present. If true ignores export of 'ALT_CFLAGS += -mno-hw-mulx' to public.mk if no mulx is found in the system. If true ignores export of 'ALT_CFLAGS += -mhw-mulx' if mulx is found in the system.
Restrictions:none
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Setting Name:hal.make.ignore_system_derived.sopc_simulation_enabled
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Enable BSP generation to query if SOPC system has simulation enabled. If true ignores export of 'ELF_PATCH_FLAG += --simulation_enabled' to public.mk.
Restrictions:none
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Setting Name:hal.make.ignore_system_derived.sopc_system_base_address
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Enable BSP generation to query SOPC system for system ID base address. If true ignores export of 'SOPC_SYSID_FLAG += --sidp=<address>' and 'ELF_PATCH_FLAG += --sidp=<address>' to public.mk.
Restrictions:none
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Setting Name:hal.make.ignore_system_derived.sopc_system_id
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Enable BSP generation to query SOPC system for system ID. If true ignores export of 'SOPC_SYSID_FLAG += --id=<sysid>' and 'ELF_PATCH_FLAG += --id=<sysid>' to public.mk.
Restrictions:none
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Setting Name:hal.make.ignore_system_derived.sopc_system_timestamp
Identifier:NONE
Default Value:0
Value:0
Type:Boolean
Destination:public_mk_define
Description:Enable BSP generation to query SOPC system for system timestamp. If true ignores export of 'SOPC_SYSID_FLAG += --timestamp=<timestamp>' and 'ELF_PATCH_FLAG += --timestamp=<timestamp>' to public.mk.
Restrictions:none
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Setting Name:hal.make.rm
Identifier:RM
Default Value:rm -f
Value:rm -f
Type:UnquotedString
Destination:makefile_variable
Description:Command used to remove files during 'clean' target.
Restrictions:none
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Setting Name:hal.max_file_descriptors
Identifier:ALT_MAX_FD
Default Value:32
Value:32
Type:DecimalNumber
Destination:system_h_define
Description:Determines the number of file descriptors statically allocated. This setting defines the value of ALT_MAX_FD in system.h.
Restrictions:If hal.enable_lightweight_device_driver_api is true, there are no file descriptors so this setting is ignored. If hal.enable_lightweight_device_driver_api is false, this setting must be at least 4 because HAL needs a file descriptor for /dev/null, /dev/stdin, /dev/stdout, and /dev/stderr.
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Setting Name:hal.stderr
Identifier:NONE
Default Value:none
Value:jtag_uart_0
Type:UnquotedString
Destination:system_h_define
Description:Slave descriptor of STDERR character-mode device. This setting is used by the ALT_STDERR family of defines in system.h.
Restrictions:none
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Setting Name:hal.stdin
Identifier:NONE
Default Value:none
Value:jtag_uart_0
Type:UnquotedString
Destination:system_h_define
Description:Slave descriptor of STDIN character-mode device. This setting is used by the ALT_STDIN family of defines in system.h.
Restrictions:none
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Setting Name:hal.stdout
Identifier:NONE
Default Value:none
Value:jtag_uart_0
Type:UnquotedString
Destination:system_h_define
Description:Slave descriptor of STDOUT character-mode device. This setting is used by the ALT_STDOUT family of defines in system.h.
Restrictions:none
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Setting Name:hal.sys_clk_timer
Identifier:ALT_SYS_CLK
Default Value:none
Value:sys_clk_timer
Type:UnquotedString
Destination:system_h_define
Description:Slave descriptor of the system clock timer device. This device provides a periodic interrupt ("tick") and is typically required for RTOS use. This setting defines the value of ALT_SYS_CLK in system.h.
Restrictions:none
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Setting Name:hal.timestamp_timer
Identifier:ALT_TIMESTAMP_CLK
Default Value:none
Value:none
Type:UnquotedString
Destination:system_h_define
Description:Slave descriptor of timestamp timer device. This device is used by Altera HAL timestamp drivers for high-resolution time measurement. This setting defines the value of ALT_TIMESTAMP_CLK in system.h.
Restrictions:none
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Setting Name:ucosii.event_flag.os_flag_accept_en
Identifier:OS_FLAG_ACCEPT_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSFlagAccept(). CAUTION: This is required by the HAL and many Altera device drivers.
Restrictions:none
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Setting Name:ucosii.event_flag.os_flag_del_en
Identifier:OS_FLAG_DEL_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSFlagDel(). CAUTION: This is required by the HAL and many Altera device drivers.
Restrictions:none
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Setting Name:ucosii.event_flag.os_flag_name_size
Identifier:OS_FLAG_NAME_SIZE
Default Value:32
Value:32
Type:DecimalNumber
Destination:system_h_define
Description:Size of name of Event Flags group. CAUTION: This is required by the HAL and many Altera device drivers; use caution in reducing this value.
Restrictions:none
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Setting Name:ucosii.event_flag.os_flag_query_en
Identifier:OS_FLAG_QUERY_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSFlagQuery(). CAUTION: This is required by the HAL and many Altera device drivers.
Restrictions:none
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Setting Name:ucosii.event_flag.os_flag_wait_clr_en
Identifier:OS_FLAG_WAIT_CLR_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for Wait on Clear Event Flags. CAUTION: This is required by the HAL and many Altera device drivers.
Restrictions:none
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Setting Name:ucosii.event_flag.os_flags_nbits
Identifier:OS_FLAGS_NBITS
Default Value:16
Value:16
Type:DecimalNumber
Destination:system_h_define
Description:Event Flag bits (8,16,32). CAUTION: This is required by the HAL and many Altera device drivers; use caution in changing this value.
Restrictions:none
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Setting Name:ucosii.event_flag.os_max_flags
Identifier:OS_MAX_FLAGS
Default Value:20
Value:20
Type:DecimalNumber
Destination:system_h_define
Description:Maximum number of Event Flags groups. CAUTION: This is required by the HAL and many Altera device drivers; use caution in reducing this value.
Restrictions:none
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Setting Name:ucosii.mailbox.os_mbox_accept_en
Identifier:OS_MBOX_ACCEPT_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSMboxAccept()
Restrictions:none
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Setting Name:ucosii.mailbox.os_mbox_del_en
Identifier:OS_MBOX_DEL_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSMboxDel()
Restrictions:none
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Setting Name:ucosii.mailbox.os_mbox_post_en
Identifier:OS_MBOX_POST_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSMboxPost()
Restrictions:none
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Setting Name:ucosii.mailbox.os_mbox_post_opt_en
Identifier:OS_MBOX_POST_OPT_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSMboxPostOpt()
Restrictions:none
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Setting Name:ucosii.mailbox.os_mbox_query_en
Identifier:OS_MBOX_QUERY_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSMboxQuery()
Restrictions:none
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Setting Name:ucosii.memory.os_max_mem_part
Identifier:OS_MAX_MEM_PART
Default Value:60
Value:60
Type:DecimalNumber
Destination:system_h_define
Description:Maximum number of memory partitions
Restrictions:none
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Setting Name:ucosii.memory.os_mem_name_size
Identifier:OS_MEM_NAME_SIZE
Default Value:32
Value:32
Type:DecimalNumber
Destination:system_h_define
Description:Size of memory partition name
Restrictions:none
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Setting Name:ucosii.memory.os_mem_query_en
Identifier:OS_MEM_QUERY_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSMemQuery()
Restrictions:none
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Setting Name:ucosii.miscellaneous.os_arg_chk_en
Identifier:OS_ARG_CHK_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Enable argument checking
Restrictions:none
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Setting Name:ucosii.miscellaneous.os_cpu_hooks_en
Identifier:OS_CPU_HOOKS_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Enable uCOS-II hooks
Restrictions:none
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Setting Name:ucosii.miscellaneous.os_debug_en
Identifier:OS_DEBUG_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Enable debug variables
Restrictions:none
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Setting Name:ucosii.miscellaneous.os_event_name_size
Identifier:OS_EVENT_NAME_SIZE
Default Value:32
Value:32
Type:DecimalNumber
Destination:system_h_define
Description:Size of name of Event Control Block groups
Restrictions:none
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Setting Name:ucosii.miscellaneous.os_max_events
Identifier:OS_MAX_EVENTS
Default Value:60
Value:60
Type:DecimalNumber
Destination:system_h_define
Description:Maximum number of event control blocks
Restrictions:none
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Setting Name:ucosii.miscellaneous.os_sched_lock_en
Identifier:OS_SCHED_LOCK_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSSchedLock() and OSSchedUnlock()
Restrictions:none
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Setting Name:ucosii.miscellaneous.os_task_idle_stk_size
Identifier:OS_TASK_IDLE_STK_SIZE
Default Value:512
Value:512
Type:DecimalNumber
Destination:system_h_define
Description:Idle task stack size
Restrictions:none
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Setting Name:ucosii.miscellaneous.os_task_stat_en
Identifier:OS_TASK_STAT_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Enable statistics task
Restrictions:none
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Setting Name:ucosii.miscellaneous.os_task_stat_stk_chk_en
Identifier:OS_TASK_STAT_STK_CHK_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Check task stacks from statistics task
Restrictions:none
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Setting Name:ucosii.miscellaneous.os_task_stat_stk_size
Identifier:OS_TASK_STAT_STK_SIZE
Default Value:512
Value:512
Type:DecimalNumber
Destination:system_h_define
Description:Statistics task stack size
Restrictions:none
-
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Setting Name:ucosii.miscellaneous.os_tick_step_en
Identifier:OS_TICK_STEP_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Enable tick stepping feature for uCOS-View
Restrictions:none
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Setting Name:ucosii.mutex.os_mutex_accept_en
Identifier:OS_MUTEX_ACCEPT_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSMutexAccept()
Restrictions:none
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Setting Name:ucosii.mutex.os_mutex_del_en
Identifier:OS_MUTEX_DEL_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSMutexDel()
Restrictions:none
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Setting Name:ucosii.mutex.os_mutex_query_en
Identifier:OS_MUTEX_QUERY_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSMutexQuery
Restrictions:none
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Setting Name:ucosii.os_flag_en
Identifier:OS_FLAG_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Enable code for Event Flags. CAUTION: This is required by the HAL and many Altera device drivers.
Restrictions:none
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Setting Name:ucosii.os_lowest_prio
Identifier:OS_LOWEST_PRIO
Default Value:20
Value:20
Type:DecimalNumber
Destination:system_h_define
Description:Lowest assignable priority
Restrictions:none
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Setting Name:ucosii.os_max_tasks
Identifier:OS_MAX_TASKS
Default Value:10
Value:10
Type:DecimalNumber
Destination:system_h_define
Description:Maximum number of tasks
Restrictions:none
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Setting Name:ucosii.os_mbox_en
Identifier:OS_MBOX_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Enable code for mailboxes
Restrictions:none
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Setting Name:ucosii.os_mem_en
Identifier:OS_MEM_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Enable code for memory management
Restrictions:none
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Setting Name:ucosii.os_mutex_en
Identifier:OS_MUTEX_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Enable code for Mutex Semaphores
Restrictions:none
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Setting Name:ucosii.os_q_en
Identifier:OS_Q_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Enable code for Queues
Restrictions:none
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Setting Name:ucosii.os_sem_en
Identifier:OS_SEM_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Enable code for semaphores. CAUTION: This is required by the HAL and many Altera device drivers.
Restrictions:none
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Setting Name:ucosii.os_thread_safe_newlib
Identifier:OS_THREAD_SAFE_NEWLIB
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Thread safe C library
Restrictions:none
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Setting Name:ucosii.os_tmr_en
Identifier:OS_TMR_EN
Default Value:0
Value:0
Type:Boolean
Destination:system_h_define
Description:Enable code for timers
Restrictions:none
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Setting Name:ucosii.queue.os_max_qs
Identifier:OS_MAX_QS
Default Value:20
Value:20
Type:DecimalNumber
Destination:system_h_define
Description:Maximum number of Queue Control Blocks
Restrictions:none
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Setting Name:ucosii.queue.os_q_accept_en
Identifier:OS_Q_ACCEPT_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSQAccept()
Restrictions:none
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Setting Name:ucosii.queue.os_q_del_en
Identifier:OS_Q_DEL_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSQDel()
Restrictions:none
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Setting Name:ucosii.queue.os_q_flush_en
Identifier:OS_Q_FLUSH_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSQFlush()
Restrictions:none
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Setting Name:ucosii.queue.os_q_post_en
Identifier:OS_Q_POST_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code of OSQFlush()
Restrictions:none
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Setting Name:ucosii.queue.os_q_post_front_en
Identifier:OS_Q_POST_FRONT_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSQPostFront()
Restrictions:none
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Setting Name:ucosii.queue.os_q_post_opt_en
Identifier:OS_Q_POST_OPT_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSQPostOpt()
Restrictions:none
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Setting Name:ucosii.queue.os_q_query_en
Identifier:OS_Q_QUERY_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSQQuery()
Restrictions:none
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Setting Name:ucosii.semaphore.os_sem_accept_en
Identifier:OS_SEM_ACCEPT_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSSemAccept(). CAUTION: This is required by the HAL and many Altera device drivers.
Restrictions:none
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Setting Name:ucosii.semaphore.os_sem_del_en
Identifier:OS_SEM_DEL_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSSemDel(). CAUTION: This is required by the HAL and many Altera device drivers.
Restrictions:none
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Setting Name:ucosii.semaphore.os_sem_query_en
Identifier:OS_SEM_QUERY_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSSemQuery(). CAUTION: This is required by the HAL and many Altera device drivers.
Restrictions:none
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Setting Name:ucosii.semaphore.os_sem_set_en
Identifier:OS_SEM_SET_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSSemSet(). CAUTION: This is required by the HAL and many Altera device drivers.
Restrictions:none
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Setting Name:ucosii.task.os_task_change_prio_en
Identifier:OS_TASK_CHANGE_PRIO_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSTaskChangePrio()
Restrictions:none
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Setting Name:ucosii.task.os_task_create_en
Identifier:OS_TASK_CREATE_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSTaskCreate()
Restrictions:none
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Setting Name:ucosii.task.os_task_create_ext_en
Identifier:OS_TASK_CREATE_EXT_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSTaskCreateExt()
Restrictions:none
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Setting Name:ucosii.task.os_task_del_en
Identifier:OS_TASK_DEL_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSTaskDel()
Restrictions:none
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Setting Name:ucosii.task.os_task_name_size
Identifier:OS_TASK_NAME_SIZE
Default Value:32
Value:32
Type:DecimalNumber
Destination:system_h_define
Description:Size of task name
Restrictions:none
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Setting Name:ucosii.task.os_task_profile_en
Identifier:OS_TASK_PROFILE_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include data structure for run-time task profiling
Restrictions:none
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Setting Name:ucosii.task.os_task_query_en
Identifier:OS_TASK_QUERY_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSTaskQuery
Restrictions:none
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Setting Name:ucosii.task.os_task_suspend_en
Identifier:OS_TASK_SUSPEND_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSTaskSuspend() and OSTaskResume()
Restrictions:none
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Setting Name:ucosii.task.os_task_sw_hook_en
Identifier:OS_TASK_SW_HOOK_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSTaskSwHook()
Restrictions:none
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Setting Name:ucosii.time.os_time_dly_hmsm_en
Identifier:OS_TIME_DLY_HMSM_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSTimeDlyHMSM()
Restrictions:none
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Setting Name:ucosii.time.os_time_dly_resume_en
Identifier:OS_TIME_DLY_RESUME_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSTimeDlyResume()
Restrictions:none
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Setting Name:ucosii.time.os_time_get_set_en
Identifier:OS_TIME_GET_SET_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSTimeGet and OSTimeSet()
Restrictions:none
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Setting Name:ucosii.time.os_time_tick_hook_en
Identifier:OS_TIME_TICK_HOOK_EN
Default Value:1
Value:1
Type:Boolean
Destination:system_h_define
Description:Include code for OSTimeTickHook()
Restrictions:none
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Setting Name:ucosii.timer.os_task_tmr_prio
Identifier:OS_TASK_TMR_PRIO
Default Value:0
Value:0
Type:DecimalNumber
Destination:system_h_define
Description:Priority of timer task (0=highest)
Restrictions:none
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Setting Name:ucosii.timer.os_task_tmr_stk_size
Identifier:OS_TASK_TMR_STK_SIZE
Default Value:512
Value:512
Type:DecimalNumber
Destination:system_h_define
Description:Stack size for timer task
Restrictions:none
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Setting Name:ucosii.timer.os_tmr_cfg_max
Identifier:OS_TMR_CFG_MAX
Default Value:16
Value:16
Type:DecimalNumber
Destination:system_h_define
Description:Maximum number of timers
Restrictions:none
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Setting Name:ucosii.timer.os_tmr_cfg_name_size
Identifier:OS_TMR_CFG_NAME_SIZE
Default Value:16
Value:16
Type:DecimalNumber
Destination:system_h_define
Description:Size of timer name
Restrictions:none
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Setting Name:ucosii.timer.os_tmr_cfg_ticks_per_sec
Identifier:OS_TMR_CFG_TICKS_PER_SEC
Default Value:10
Value:10
Type:DecimalNumber
Destination:system_h_define
Description:Rate at which timer management task runs (Hz)
Restrictions:none
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Setting Name:ucosii.timer.os_tmr_cfg_wheel_size
Identifier:OS_TMR_CFG_WHEEL_SIZE
Default Value:2
Value:2
Type:DecimalNumber
Destination:system_h_define
Description:Size of timer wheel (number of spokes)
Restrictions:none
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-
-
- - diff --git a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/system.h b/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/system.h deleted file mode 100644 index 4805bcc5..00000000 --- a/MCandWifiTestDE0/Software/MCandWifiTestDE0_bsp/system.h +++ /dev/null @@ -1,534 +0,0 @@ -/* - * system.h - SOPC Builder system and BSP software package information - * - * Machine generated for CPU 'cpu' in SOPC Builder design 'system' - * SOPC Builder design path: C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system.sopcinfo - * - * Generated: Sun Mar 02 19:03:50 MST 2014 - */ - -/* - * DO NOT MODIFY THIS FILE - * - * Changing this file will have subtle consequences - * which will almost certainly lead to a nonfunctioning - * system. If you do modify this file, be aware that your - * changes will be overwritten and lost when this file - * is generated again. - * - * DO NOT MODIFY THIS FILE - */ - -/* - * License Agreement - * - * Copyright (c) 2008 - * Altera Corporation, San Jose, California, USA. - * All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - * This agreement shall be governed in all respects by the laws of the State - * of California and by the laws of the United States of America. - */ - -#ifndef __SYSTEM_H_ -#define __SYSTEM_H_ - -/* Include definitions from linker script generator */ -#include "linker.h" - - -/* - * CPU configuration - * - */ - -#define ALT_CPU_ARCHITECTURE "altera_nios2_qsys" -#define ALT_CPU_BIG_ENDIAN 0 -#define ALT_CPU_BREAK_ADDR 0x2000820 -#define ALT_CPU_CPU_FREQ 100000000u -#define ALT_CPU_CPU_ID_SIZE 1 -#define ALT_CPU_CPU_ID_VALUE 0x00000000 -#define ALT_CPU_CPU_IMPLEMENTATION "fast" -#define ALT_CPU_DATA_ADDR_WIDTH 0x1a -#define ALT_CPU_DCACHE_LINE_SIZE 32 -#define ALT_CPU_DCACHE_LINE_SIZE_LOG2 5 -#define ALT_CPU_DCACHE_SIZE 4096 -#define ALT_CPU_EXCEPTION_ADDR 0x1000020 -#define ALT_CPU_FLUSHDA_SUPPORTED -#define ALT_CPU_FREQ 100000000 -#define ALT_CPU_HARDWARE_DIVIDE_PRESENT 0 -#define ALT_CPU_HARDWARE_MULTIPLY_PRESENT 1 -#define ALT_CPU_HARDWARE_MULX_PRESENT 0 -#define ALT_CPU_HAS_DEBUG_CORE 1 -#define ALT_CPU_HAS_DEBUG_STUB -#define ALT_CPU_HAS_JMPI_INSTRUCTION -#define ALT_CPU_ICACHE_LINE_SIZE 32 -#define ALT_CPU_ICACHE_LINE_SIZE_LOG2 5 -#define ALT_CPU_ICACHE_SIZE 8192 -#define ALT_CPU_INITDA_SUPPORTED -#define ALT_CPU_INST_ADDR_WIDTH 0x1a -#define ALT_CPU_NAME "cpu" -#define ALT_CPU_NUM_OF_SHADOW_REG_SETS 0 -#define ALT_CPU_RESET_ADDR 0x1000000 - - -/* - * CPU configuration (with legacy prefix - don't use these anymore) - * - */ - -#define NIOS2_BIG_ENDIAN 0 -#define NIOS2_BREAK_ADDR 0x2000820 -#define NIOS2_CPU_FREQ 100000000u -#define NIOS2_CPU_ID_SIZE 1 -#define NIOS2_CPU_ID_VALUE 0x00000000 -#define NIOS2_CPU_IMPLEMENTATION "fast" -#define NIOS2_DATA_ADDR_WIDTH 0x1a -#define NIOS2_DCACHE_LINE_SIZE 32 -#define NIOS2_DCACHE_LINE_SIZE_LOG2 5 -#define NIOS2_DCACHE_SIZE 4096 -#define NIOS2_EXCEPTION_ADDR 0x1000020 -#define NIOS2_FLUSHDA_SUPPORTED -#define NIOS2_HARDWARE_DIVIDE_PRESENT 0 -#define NIOS2_HARDWARE_MULTIPLY_PRESENT 1 -#define NIOS2_HARDWARE_MULX_PRESENT 0 -#define NIOS2_HAS_DEBUG_CORE 1 -#define NIOS2_HAS_DEBUG_STUB -#define NIOS2_HAS_JMPI_INSTRUCTION -#define NIOS2_ICACHE_LINE_SIZE 32 -#define NIOS2_ICACHE_LINE_SIZE_LOG2 5 -#define NIOS2_ICACHE_SIZE 8192 -#define NIOS2_INITDA_SUPPORTED -#define NIOS2_INST_ADDR_WIDTH 0x1a -#define NIOS2_NUM_OF_SHADOW_REG_SETS 0 -#define NIOS2_RESET_ADDR 0x1000000 - - -/* - * Define for each module class mastered by the CPU - * - */ - -#define __ALTERA_AVALON_JTAG_UART -#define __ALTERA_AVALON_NEW_SDRAM_CONTROLLER -#define __ALTERA_AVALON_PIO -#define __ALTERA_AVALON_SYSID_QSYS -#define __ALTERA_AVALON_TIMER -#define __ALTERA_AVALON_UART -#define __ALTERA_NIOS2_QSYS -#define __ALTERA_UP_AVALON_RS232 - - -/* - * System configuration - * - */ - -#define ALT_DEVICE_FAMILY "Cyclone IV E" -#define ALT_IRQ_BASE NULL -#define ALT_LEGACY_INTERRUPT_API_PRESENT -#define ALT_LOG_PORT "/dev/null" -#define ALT_LOG_PORT_BASE 0x0 -#define ALT_LOG_PORT_DEV null -#define ALT_LOG_PORT_TYPE "" -#define ALT_NUM_EXTERNAL_INTERRUPT_CONTROLLERS 0 -#define ALT_NUM_INTERNAL_INTERRUPT_CONTROLLERS 1 -#define ALT_NUM_INTERRUPT_CONTROLLERS 1 -#define ALT_STDERR "/dev/jtag_uart_0" -#define ALT_STDERR_BASE 0x20010b8 -#define ALT_STDERR_DEV jtag_uart_0 -#define ALT_STDERR_IS_JTAG_UART -#define ALT_STDERR_PRESENT -#define ALT_STDERR_TYPE "altera_avalon_jtag_uart" -#define ALT_STDIN "/dev/jtag_uart_0" -#define ALT_STDIN_BASE 0x20010b8 -#define ALT_STDIN_DEV jtag_uart_0 -#define ALT_STDIN_IS_JTAG_UART -#define ALT_STDIN_PRESENT -#define ALT_STDIN_TYPE "altera_avalon_jtag_uart" -#define ALT_STDOUT "/dev/jtag_uart_0" -#define ALT_STDOUT_BASE 0x20010b8 -#define ALT_STDOUT_DEV jtag_uart_0 -#define ALT_STDOUT_IS_JTAG_UART -#define ALT_STDOUT_PRESENT -#define ALT_STDOUT_TYPE "altera_avalon_jtag_uart" -#define ALT_SYSTEM_NAME "system" - - -/* - * hal configuration - * - */ - -#define ALT_MAX_FD 32 -#define ALT_SYS_CLK SYS_CLK_TIMER -#define ALT_TIMESTAMP_CLK none - - -/* - * jtag_uart_0 configuration - * - */ - -#define ALT_MODULE_CLASS_jtag_uart_0 altera_avalon_jtag_uart -#define JTAG_UART_0_BASE 0x20010b8 -#define JTAG_UART_0_IRQ 14 -#define JTAG_UART_0_IRQ_INTERRUPT_CONTROLLER_ID 0 -#define JTAG_UART_0_NAME "/dev/jtag_uart_0" -#define JTAG_UART_0_READ_DEPTH 64 -#define JTAG_UART_0_READ_THRESHOLD 8 -#define JTAG_UART_0_SPAN 8 -#define JTAG_UART_0_TYPE "altera_avalon_jtag_uart" -#define JTAG_UART_0_WRITE_DEPTH 64 -#define JTAG_UART_0_WRITE_THRESHOLD 8 - - -/* - * pio_ir_emitter configuration - * - */ - -#define ALT_MODULE_CLASS_pio_ir_emitter altera_avalon_pio -#define PIO_IR_EMITTER_BASE 0x2001080 -#define PIO_IR_EMITTER_BIT_CLEARING_EDGE_REGISTER 0 -#define PIO_IR_EMITTER_BIT_MODIFYING_OUTPUT_REGISTER 0 -#define PIO_IR_EMITTER_CAPTURE 0 -#define PIO_IR_EMITTER_DATA_WIDTH 1 -#define PIO_IR_EMITTER_DO_TEST_BENCH_WIRING 0 -#define PIO_IR_EMITTER_DRIVEN_SIM_VALUE 0x0 -#define PIO_IR_EMITTER_EDGE_TYPE "NONE" -#define PIO_IR_EMITTER_FREQ 100000000u -#define PIO_IR_EMITTER_HAS_IN 0 -#define PIO_IR_EMITTER_HAS_OUT 1 -#define PIO_IR_EMITTER_HAS_TRI 0 -#define PIO_IR_EMITTER_IRQ -1 -#define PIO_IR_EMITTER_IRQ_INTERRUPT_CONTROLLER_ID -1 -#define PIO_IR_EMITTER_IRQ_TYPE "NONE" -#define PIO_IR_EMITTER_NAME "/dev/pio_ir_emitter" -#define PIO_IR_EMITTER_RESET_VALUE 0x0 -#define PIO_IR_EMITTER_SPAN 16 -#define PIO_IR_EMITTER_TYPE "altera_avalon_pio" - - -/* - * pio_key_left configuration - * - */ - -#define ALT_MODULE_CLASS_pio_key_left altera_avalon_pio -#define PIO_KEY_LEFT_BASE 0x20010a0 -#define PIO_KEY_LEFT_BIT_CLEARING_EDGE_REGISTER 1 -#define PIO_KEY_LEFT_BIT_MODIFYING_OUTPUT_REGISTER 0 -#define PIO_KEY_LEFT_CAPTURE 1 -#define PIO_KEY_LEFT_DATA_WIDTH 1 -#define PIO_KEY_LEFT_DO_TEST_BENCH_WIRING 0 -#define PIO_KEY_LEFT_DRIVEN_SIM_VALUE 0x0 -#define PIO_KEY_LEFT_EDGE_TYPE "ANY" -#define PIO_KEY_LEFT_FREQ 100000000u -#define PIO_KEY_LEFT_HAS_IN 1 -#define PIO_KEY_LEFT_HAS_OUT 0 -#define PIO_KEY_LEFT_HAS_TRI 0 -#define PIO_KEY_LEFT_IRQ 1 -#define PIO_KEY_LEFT_IRQ_INTERRUPT_CONTROLLER_ID 0 -#define PIO_KEY_LEFT_IRQ_TYPE "EDGE" -#define PIO_KEY_LEFT_NAME "/dev/pio_key_left" -#define PIO_KEY_LEFT_RESET_VALUE 0x0 -#define PIO_KEY_LEFT_SPAN 16 -#define PIO_KEY_LEFT_TYPE "altera_avalon_pio" - - -/* - * pio_led configuration - * - */ - -#define ALT_MODULE_CLASS_pio_led altera_avalon_pio -#define PIO_LED_BASE 0x2001020 -#define PIO_LED_BIT_CLEARING_EDGE_REGISTER 0 -#define PIO_LED_BIT_MODIFYING_OUTPUT_REGISTER 1 -#define PIO_LED_CAPTURE 0 -#define PIO_LED_DATA_WIDTH 7 -#define PIO_LED_DO_TEST_BENCH_WIRING 0 -#define PIO_LED_DRIVEN_SIM_VALUE 0x0 -#define PIO_LED_EDGE_TYPE "NONE" -#define PIO_LED_FREQ 100000000u -#define PIO_LED_HAS_IN 0 -#define PIO_LED_HAS_OUT 1 -#define PIO_LED_HAS_TRI 0 -#define PIO_LED_IRQ -1 -#define PIO_LED_IRQ_INTERRUPT_CONTROLLER_ID -1 -#define PIO_LED_IRQ_TYPE "NONE" -#define PIO_LED_NAME "/dev/pio_led" -#define PIO_LED_RESET_VALUE 0x0 -#define PIO_LED_SPAN 32 -#define PIO_LED_TYPE "altera_avalon_pio" - - -/* - * pio_sw configuration - * - */ - -#define ALT_MODULE_CLASS_pio_sw altera_avalon_pio -#define PIO_SW_BASE 0x2001090 -#define PIO_SW_BIT_CLEARING_EDGE_REGISTER 0 -#define PIO_SW_BIT_MODIFYING_OUTPUT_REGISTER 0 -#define PIO_SW_CAPTURE 0 -#define PIO_SW_DATA_WIDTH 4 -#define PIO_SW_DO_TEST_BENCH_WIRING 0 -#define PIO_SW_DRIVEN_SIM_VALUE 0x0 -#define PIO_SW_EDGE_TYPE "NONE" -#define PIO_SW_FREQ 100000000u -#define PIO_SW_HAS_IN 1 -#define PIO_SW_HAS_OUT 0 -#define PIO_SW_HAS_TRI 0 -#define PIO_SW_IRQ -1 -#define PIO_SW_IRQ_INTERRUPT_CONTROLLER_ID -1 -#define PIO_SW_IRQ_TYPE "NONE" -#define PIO_SW_NAME "/dev/pio_sw" -#define PIO_SW_RESET_VALUE 0x0 -#define PIO_SW_SPAN 16 -#define PIO_SW_TYPE "altera_avalon_pio" - - -/* - * rs232_wifi configuration - * - */ - -#define ALT_MODULE_CLASS_rs232_wifi altera_up_avalon_rs232 -#define RS232_WIFI_BASE 0x20010b0 -#define RS232_WIFI_IRQ 6 -#define RS232_WIFI_IRQ_INTERRUPT_CONTROLLER_ID 0 -#define RS232_WIFI_NAME "/dev/rs232_wifi" -#define RS232_WIFI_SPAN 8 -#define RS232_WIFI_TYPE "altera_up_avalon_rs232" - - -/* - * sdram configuration - * - */ - -#define ALT_MODULE_CLASS_sdram altera_avalon_new_sdram_controller -#define SDRAM_BASE 0x1000000 -#define SDRAM_CAS_LATENCY 3 -#define SDRAM_CONTENTS_INFO "" -#define SDRAM_INIT_NOP_DELAY 0.0 -#define SDRAM_INIT_REFRESH_COMMANDS 8 -#define SDRAM_IRQ -1 -#define SDRAM_IRQ_INTERRUPT_CONTROLLER_ID -1 -#define SDRAM_IS_INITIALIZED 1 -#define SDRAM_NAME "/dev/sdram" -#define SDRAM_POWERUP_DELAY 200.0 -#define SDRAM_REFRESH_PERIOD 7.8125 -#define SDRAM_REGISTER_DATA_IN 1 -#define SDRAM_SDRAM_ADDR_WIDTH 0x17 -#define SDRAM_SDRAM_BANK_WIDTH 2 -#define SDRAM_SDRAM_COL_WIDTH 8 -#define SDRAM_SDRAM_DATA_WIDTH 16 -#define SDRAM_SDRAM_NUM_BANKS 4 -#define SDRAM_SDRAM_NUM_CHIPSELECTS 1 -#define SDRAM_SDRAM_ROW_WIDTH 13 -#define SDRAM_SHARED_DATA 0 -#define SDRAM_SIM_MODEL_BASE 0 -#define SDRAM_SPAN 16777216 -#define SDRAM_STARVATION_INDICATOR 0 -#define SDRAM_TRISTATE_BRIDGE_SLAVE "" -#define SDRAM_TYPE "altera_avalon_new_sdram_controller" -#define SDRAM_T_AC 5.5 -#define SDRAM_T_MRD 3 -#define SDRAM_T_RCD 20.0 -#define SDRAM_T_RFC 70.0 -#define SDRAM_T_RP 20.0 -#define SDRAM_T_WR 14.0 - - -/* - * sys_clk_timer configuration - * - */ - -#define ALT_MODULE_CLASS_sys_clk_timer altera_avalon_timer -#define SYS_CLK_TIMER_ALWAYS_RUN 0 -#define SYS_CLK_TIMER_BASE 0x2001060 -#define SYS_CLK_TIMER_COUNTER_SIZE 32 -#define SYS_CLK_TIMER_FIXED_PERIOD 0 -#define SYS_CLK_TIMER_FREQ 100000000u -#define SYS_CLK_TIMER_IRQ 0 -#define SYS_CLK_TIMER_IRQ_INTERRUPT_CONTROLLER_ID 0 -#define SYS_CLK_TIMER_LOAD_VALUE 99999ull -#define SYS_CLK_TIMER_MULT 0.0010 -#define SYS_CLK_TIMER_NAME "/dev/sys_clk_timer" -#define SYS_CLK_TIMER_PERIOD 1 -#define SYS_CLK_TIMER_PERIOD_UNITS "ms" -#define SYS_CLK_TIMER_RESET_OUTPUT 0 -#define SYS_CLK_TIMER_SNAPSHOT 1 -#define SYS_CLK_TIMER_SPAN 32 -#define SYS_CLK_TIMER_TICKS_PER_SEC 1000u -#define SYS_CLK_TIMER_TIMEOUT_PULSE_OUTPUT 0 -#define SYS_CLK_TIMER_TYPE "altera_avalon_timer" - - -/* - * sysid configuration - * - */ - -#define ALT_MODULE_CLASS_sysid altera_avalon_sysid_qsys -#define SYSID_BASE 0x20010c0 -#define SYSID_ID 0 -#define SYSID_IRQ -1 -#define SYSID_IRQ_INTERRUPT_CONTROLLER_ID -1 -#define SYSID_NAME "/dev/sysid" -#define SYSID_SPAN 8 -#define SYSID_TIMESTAMP 1393806947 -#define SYSID_TYPE "altera_avalon_sysid_qsys" - - -/* - * uart_mc configuration - * - */ - -#define ALT_MODULE_CLASS_uart_mc altera_avalon_uart -#define UART_MC_BASE 0x2001000 -#define UART_MC_BAUD 9600 -#define UART_MC_DATA_BITS 8 -#define UART_MC_FIXED_BAUD 1 -#define UART_MC_FREQ 100000000u -#define UART_MC_IRQ 5 -#define UART_MC_IRQ_INTERRUPT_CONTROLLER_ID 0 -#define UART_MC_NAME "/dev/uart_mc" -#define UART_MC_PARITY 'N' -#define UART_MC_SIM_CHAR_STREAM "" -#define UART_MC_SIM_TRUE_BAUD 0 -#define UART_MC_SPAN 32 -#define UART_MC_STOP_BITS 1 -#define UART_MC_SYNC_REG_DEPTH 2 -#define UART_MC_TYPE "altera_avalon_uart" -#define UART_MC_USE_CTS_RTS 0 -#define UART_MC_USE_EOP_REGISTER 0 - - -/* - * uart_wifi configuration - * - */ - -#define ALT_MODULE_CLASS_uart_wifi altera_avalon_uart -#define UART_WIFI_BASE 0x2001040 -#define UART_WIFI_BAUD 9600 -#define UART_WIFI_DATA_BITS 8 -#define UART_WIFI_FIXED_BAUD 0 -#define UART_WIFI_FREQ 100000000u -#define UART_WIFI_IRQ 4 -#define UART_WIFI_IRQ_INTERRUPT_CONTROLLER_ID 0 -#define UART_WIFI_NAME "/dev/uart_wifi" -#define UART_WIFI_PARITY 'N' -#define UART_WIFI_SIM_CHAR_STREAM "" -#define UART_WIFI_SIM_TRUE_BAUD 0 -#define UART_WIFI_SPAN 32 -#define UART_WIFI_STOP_BITS 1 -#define UART_WIFI_SYNC_REG_DEPTH 2 -#define UART_WIFI_TYPE "altera_avalon_uart" -#define UART_WIFI_USE_CTS_RTS 0 -#define UART_WIFI_USE_EOP_REGISTER 0 - - -/* - * ucosii configuration - * - */ - -#define OS_ARG_CHK_EN 1 -#define OS_CPU_HOOKS_EN 1 -#define OS_DEBUG_EN 1 -#define OS_EVENT_NAME_SIZE 32 -#define OS_FLAGS_NBITS 16 -#define OS_FLAG_ACCEPT_EN 1 -#define OS_FLAG_DEL_EN 1 -#define OS_FLAG_EN 1 -#define OS_FLAG_NAME_SIZE 32 -#define OS_FLAG_QUERY_EN 1 -#define OS_FLAG_WAIT_CLR_EN 1 -#define OS_LOWEST_PRIO 20 -#define OS_MAX_EVENTS 60 -#define OS_MAX_FLAGS 20 -#define OS_MAX_MEM_PART 60 -#define OS_MAX_QS 20 -#define OS_MAX_TASKS 10 -#define OS_MBOX_ACCEPT_EN 1 -#define OS_MBOX_DEL_EN 1 -#define OS_MBOX_EN 1 -#define OS_MBOX_POST_EN 1 -#define OS_MBOX_POST_OPT_EN 1 -#define OS_MBOX_QUERY_EN 1 -#define OS_MEM_EN 1 -#define OS_MEM_NAME_SIZE 32 -#define OS_MEM_QUERY_EN 1 -#define OS_MUTEX_ACCEPT_EN 1 -#define OS_MUTEX_DEL_EN 1 -#define OS_MUTEX_EN 1 -#define OS_MUTEX_QUERY_EN 1 -#define OS_Q_ACCEPT_EN 1 -#define OS_Q_DEL_EN 1 -#define OS_Q_EN 1 -#define OS_Q_FLUSH_EN 1 -#define OS_Q_POST_EN 1 -#define OS_Q_POST_FRONT_EN 1 -#define OS_Q_POST_OPT_EN 1 -#define OS_Q_QUERY_EN 1 -#define OS_SCHED_LOCK_EN 1 -#define OS_SEM_ACCEPT_EN 1 -#define OS_SEM_DEL_EN 1 -#define OS_SEM_EN 1 -#define OS_SEM_QUERY_EN 1 -#define OS_SEM_SET_EN 1 -#define OS_TASK_CHANGE_PRIO_EN 1 -#define OS_TASK_CREATE_EN 1 -#define OS_TASK_CREATE_EXT_EN 1 -#define OS_TASK_DEL_EN 1 -#define OS_TASK_IDLE_STK_SIZE 512 -#define OS_TASK_NAME_SIZE 32 -#define OS_TASK_PROFILE_EN 1 -#define OS_TASK_QUERY_EN 1 -#define OS_TASK_STAT_EN 1 -#define OS_TASK_STAT_STK_CHK_EN 1 -#define OS_TASK_STAT_STK_SIZE 512 -#define OS_TASK_SUSPEND_EN 1 -#define OS_TASK_SW_HOOK_EN 1 -#define OS_TASK_TMR_PRIO 0 -#define OS_TASK_TMR_STK_SIZE 512 -#define OS_THREAD_SAFE_NEWLIB 1 -#define OS_TICKS_PER_SEC SYS_CLK_TIMER_TICKS_PER_SEC -#define OS_TICK_STEP_EN 1 -#define OS_TIME_DLY_HMSM_EN 1 -#define OS_TIME_DLY_RESUME_EN 1 -#define OS_TIME_GET_SET_EN 1 -#define OS_TIME_TICK_HOOK_EN 1 -#define OS_TMR_CFG_MAX 16 -#define OS_TMR_CFG_NAME_SIZE 16 -#define OS_TMR_CFG_TICKS_PER_SEC 10 -#define OS_TMR_CFG_WHEEL_SIZE 2 -#define OS_TMR_EN 0 - -#endif /* __SYSTEM_H_ */ diff --git a/MCandWifiTestDE0/db/de0_nano_system.(169).cnf.cdb b/MCandWifiTestDE0/db/de0_nano_system.(169).cnf.cdb new file mode 100644 index 00000000..d094be68 Binary files /dev/null and b/MCandWifiTestDE0/db/de0_nano_system.(169).cnf.cdb differ diff --git a/MCandWifiTestDE0/db/de0_nano_system.(169).cnf.hdb b/MCandWifiTestDE0/db/de0_nano_system.(169).cnf.hdb new file mode 100644 index 00000000..13fc36f0 Binary files /dev/null and b/MCandWifiTestDE0/db/de0_nano_system.(169).cnf.hdb differ diff --git a/MCandWifiTestDE0/db/de0_nano_system.(170).cnf.cdb b/MCandWifiTestDE0/db/de0_nano_system.(170).cnf.cdb new file mode 100644 index 00000000..34294eb0 Binary files /dev/null and b/MCandWifiTestDE0/db/de0_nano_system.(170).cnf.cdb differ diff --git a/MCandWifiTestDE0/db/de0_nano_system.(170).cnf.hdb b/MCandWifiTestDE0/db/de0_nano_system.(170).cnf.hdb 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mode 100644 index 00000000..b29dcf36 Binary files /dev/null and b/MCandWifiTestDE0/db/de0_nano_system.(172).cnf.hdb differ diff --git a/MCandWifiTestDE0/db/de0_nano_system.(5).cnf.hdb b/MCandWifiTestDE0/db/de0_nano_system.(5).cnf.hdb index b46d5eda..a000d6c0 100644 Binary files a/MCandWifiTestDE0/db/de0_nano_system.(5).cnf.hdb and b/MCandWifiTestDE0/db/de0_nano_system.(5).cnf.hdb differ diff --git a/MCandWifiTestDE0/db/de0_nano_system.(68).cnf.cdb b/MCandWifiTestDE0/db/de0_nano_system.(68).cnf.cdb index 35b5a287..71376045 100644 Binary files a/MCandWifiTestDE0/db/de0_nano_system.(68).cnf.cdb and b/MCandWifiTestDE0/db/de0_nano_system.(68).cnf.cdb differ diff --git a/MCandWifiTestDE0/db/de0_nano_system.(68).cnf.hdb b/MCandWifiTestDE0/db/de0_nano_system.(68).cnf.hdb index 263fe1a3..68ea7db8 100644 Binary files a/MCandWifiTestDE0/db/de0_nano_system.(68).cnf.hdb and b/MCandWifiTestDE0/db/de0_nano_system.(68).cnf.hdb differ diff --git a/MCandWifiTestDE0/db/de0_nano_system.asm.qmsg b/MCandWifiTestDE0/db/de0_nano_system.asm.qmsg index 597fc9cf..285f45ad 100644 --- a/MCandWifiTestDE0/db/de0_nano_system.asm.qmsg +++ b/MCandWifiTestDE0/db/de0_nano_system.asm.qmsg @@ -1,6 +1,6 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1 1393811688097 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Full Version " "Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1 1393811688097 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Mar 02 18:54:47 2014 " "Processing started: Sun Mar 02 18:54:47 2014" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1 1393811688097 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1 1393811688097 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off de0_nano_system -c de0_nano_system " "Command: quartus_asm --read_settings_files=off --write_settings_files=off de0_nano_system -c de0_nano_system" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1 1393811688097 ""} -{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "" 0 -1 1393811690057 ""} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "" 0 -1 1393811690097 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "460 " "Peak virtual memory: 460 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1 1393811690507 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Mar 02 18:54:50 2014 " "Processing ended: Sun Mar 02 18:54:50 2014" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1 1393811690507 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1 1393811690507 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1 1393811690507 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1 1393811690507 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1 1393888384609 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Full Version " "Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1 1393888384610 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 03 16:13:04 2014 " "Processing started: Mon Mar 03 16:13:04 2014" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1 1393888384610 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1 1393888384610 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off de0_nano_system -c de0_nano_system " "Command: quartus_asm --read_settings_files=off --write_settings_files=off de0_nano_system -c de0_nano_system" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1 1393888384610 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "" 0 -1 1393888386605 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "" 0 -1 1393888386637 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "456 " "Peak virtual memory: 456 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1 1393888387073 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 03 16:13:07 2014 " "Processing ended: Mon Mar 03 16:13:07 2014" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1 1393888387073 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1 1393888387073 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1 1393888387073 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1 1393888387073 ""} diff --git a/MCandWifiTestDE0/db/de0_nano_system.asm.rdb b/MCandWifiTestDE0/db/de0_nano_system.asm.rdb index 4b6cd88a..30708cbc 100644 Binary files a/MCandWifiTestDE0/db/de0_nano_system.asm.rdb and b/MCandWifiTestDE0/db/de0_nano_system.asm.rdb differ diff --git a/MCandWifiTestDE0/db/de0_nano_system.asm_labs.ddb b/MCandWifiTestDE0/db/de0_nano_system.asm_labs.ddb index 4bfbbe97..a0f841cd 100644 Binary files a/MCandWifiTestDE0/db/de0_nano_system.asm_labs.ddb and b/MCandWifiTestDE0/db/de0_nano_system.asm_labs.ddb differ diff --git a/MCandWifiTestDE0/db/de0_nano_system.cmp.bpm b/MCandWifiTestDE0/db/de0_nano_system.cmp.bpm index b81574c1..8e926ad4 100644 Binary files a/MCandWifiTestDE0/db/de0_nano_system.cmp.bpm and b/MCandWifiTestDE0/db/de0_nano_system.cmp.bpm differ diff --git a/MCandWifiTestDE0/db/de0_nano_system.cmp.cdb b/MCandWifiTestDE0/db/de0_nano_system.cmp.cdb index 19740143..062cf47f 100644 Binary files a/MCandWifiTestDE0/db/de0_nano_system.cmp.cdb and b/MCandWifiTestDE0/db/de0_nano_system.cmp.cdb differ diff --git a/MCandWifiTestDE0/db/de0_nano_system.cmp.hdb b/MCandWifiTestDE0/db/de0_nano_system.cmp.hdb index d96fd8a9..7c22e41f 100644 Binary files a/MCandWifiTestDE0/db/de0_nano_system.cmp.hdb and b/MCandWifiTestDE0/db/de0_nano_system.cmp.hdb differ diff --git a/MCandWifiTestDE0/db/de0_nano_system.cmp.idb b/MCandWifiTestDE0/db/de0_nano_system.cmp.idb index a9818fd1..67c80ffc 100644 Binary files a/MCandWifiTestDE0/db/de0_nano_system.cmp.idb and b/MCandWifiTestDE0/db/de0_nano_system.cmp.idb differ diff --git a/MCandWifiTestDE0/db/de0_nano_system.cmp.kpt b/MCandWifiTestDE0/db/de0_nano_system.cmp.kpt index 993e49bb..b9676e6f 100644 Binary files a/MCandWifiTestDE0/db/de0_nano_system.cmp.kpt and b/MCandWifiTestDE0/db/de0_nano_system.cmp.kpt differ diff --git a/MCandWifiTestDE0/db/de0_nano_system.cmp.rdb b/MCandWifiTestDE0/db/de0_nano_system.cmp.rdb index 0cf6013e..ef81f9d9 100644 Binary files a/MCandWifiTestDE0/db/de0_nano_system.cmp.rdb and b/MCandWifiTestDE0/db/de0_nano_system.cmp.rdb differ diff --git a/MCandWifiTestDE0/db/de0_nano_system.db_info b/MCandWifiTestDE0/db/de0_nano_system.db_info index cbccb470..083227ea 100644 --- a/MCandWifiTestDE0/db/de0_nano_system.db_info +++ b/MCandWifiTestDE0/db/de0_nano_system.db_info @@ -1,3 +1,3 @@ Quartus_Version = Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Full Version Version_Index = 285274881 -Creation_Time = Sun Mar 02 17:21:09 2014 +Creation_Time = Fri Mar 14 08:39:27 2014 diff --git a/MCandWifiTestDE0/db/de0_nano_system.fit.qmsg b/MCandWifiTestDE0/db/de0_nano_system.fit.qmsg index 9f481bd0..24adefa8 100644 --- a/MCandWifiTestDE0/db/de0_nano_system.fit.qmsg +++ b/MCandWifiTestDE0/db/de0_nano_system.fit.qmsg @@ -1,63 +1,63 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1 1393811648986 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 64-Bit " "Running Quartus II 64-Bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Full Version " "Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1 1393811648986 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Mar 02 18:54:08 2014 " "Processing started: Sun Mar 02 18:54:08 2014" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1 1393811648986 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1 1393811648986 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off de0_nano_system -c de0_nano_system " "Command: quartus_fit --read_settings_files=off --write_settings_files=off de0_nano_system -c de0_nano_system" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1 1393811648986 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." { } { } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "" 0 -1 1393811649146 ""} -{ "Info" "IMPP_MPP_USER_DEVICE" "de0_nano_system EP4CE22F17C6 " "Selected device EP4CE22F17C6 for design \"de0_nano_system\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 -1 1393811649436 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "" 0 -1 1393811649496 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "" 0 -1 1393811649496 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "" 0 -1 1393811649496 ""} -{ "Info" "ICUT_CUT_PLL_COMPUTATION_SUCCESS" "pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|pll1 Cyclone IV E PLL " "Implemented PLL \"pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|pll1\" as Cyclone IV E PLL type" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|wire_pll1_clk\[0\] 2 1 0 0 " "Implementing clock multiplication of 2, clock division of 1, and phase shift of 0 degrees (0 ps) for pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|wire_pll1_clk\[0\] port" { } { { "db/pll_sys_altpll.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/pll_sys_altpll.v" 45 -1 0 } } { "" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 6290 8336 9085 0} } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "" 0 -1 1393811649546 ""} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|wire_pll1_clk\[1\] 2 1 -54 -1500 " "Implementing clock multiplication of 2, clock division of 1, and phase shift of -54 degrees (-1500 ps) for pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|wire_pll1_clk\[1\] port" { } { { "db/pll_sys_altpll.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/pll_sys_altpll.v" 45 -1 0 } } { "" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 6291 8336 9085 0} } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "" 0 -1 1393811649546 ""} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|wire_pll1_clk\[2\] 1 5 0 0 " "Implementing clock multiplication of 1, clock division of 5, and phase shift of 0 degrees (0 ps) for pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|wire_pll1_clk\[2\] port" { } { { "db/pll_sys_altpll.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/pll_sys_altpll.v" 45 -1 0 } } { "" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 6292 8336 9085 0} } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "" 0 -1 1393811649546 ""} } { { "db/pll_sys_altpll.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/pll_sys_altpll.v" 45 -1 0 } } { "" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 6290 8336 9085 0} } } } } 0 15535 "Implemented %3!s! \"%1!s!\" as %2!s! PLL type" 0 0 "" 0 -1 1393811649546 ""} -{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0 -1 1393811649766 ""} -{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE10F17C6 " "Device EP4CE10F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "" 0 -1 1393811650076 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE6F17C6 " "Device EP4CE6F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "" 0 -1 1393811650076 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE15F17C6 " "Device EP4CE15F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "" 0 -1 1393811650076 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 -1 1393811650076 ""} -{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ C1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location C1" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 16681 8336 9085 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1 1393811650086 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ D2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location D2" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 16683 8336 9085 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1 1393811650086 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ H1 " "Pin ~ALTERA_DCLK~ is reserved at location H1" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 16685 8336 9085 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1 1393811650086 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ H2 " "Pin ~ALTERA_DATA0~ is reserved at location H2" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 16687 8336 9085 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1 1393811650086 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ F16 " "Pin ~ALTERA_nCEO~ is reserved at location F16" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 16689 8336 9085 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1 1393811650086 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 -1 1393811650086 ""} -{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "" 0 -1 1393811650086 ""} -{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." { } { } 0 176045 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "" 0 -1 1393811650146 ""} -{ "Info" "ISTA_SDC_STATEMENT_PARENT" "" "Evaluating HDL-embedded SDC commands" { { "Info" "ISTA_SDC_STATEMENT_ENTITY" "alt_jtag_atlantic " "Entity alt_jtag_atlantic" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate1*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate1*\}\] " { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393811651919 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393811651919 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393811651919 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393811651919 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393811651919 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393811651919 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393811651919 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393811651919 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393811651919 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|read1*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|read1*\}\] " { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393811651919 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read_req\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read_req\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393811651919 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393811651919 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|tck_t_dav\}\] " "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|tck_t_dav\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393811651919 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|user_saw_rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid0*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|user_saw_rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid0*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393811651919 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393811651919 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393811651919 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393811651919 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393811651919 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393811651919 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393811651919 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393811651919 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393811651919 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write1*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write1*\}\] " { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393811651919 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_ena*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_ena*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393811651919 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_pause*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_pause*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393811651919 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_valid\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_valid\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393811651919 ""} } { } 0 332165 "Entity %1!s!" 0 0 "" 0 -1 1393811651919 ""} { "Info" "ISTA_SDC_STATEMENT_ENTITY" "altera_std_synchronizer " "Entity altera_std_synchronizer" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -to \[get_keepers \{*altera_std_synchronizer:*\|din_s1\}\] " "set_false_path -to \[get_keepers \{*altera_std_synchronizer:*\|din_s1\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393811651919 ""} } { } 0 332165 "Entity %1!s!" 0 0 "" 0 -1 1393811651919 ""} { "Info" "ISTA_SDC_STATEMENT_ENTITY" "sld_jtag_hub " "Entity sld_jtag_hub" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "create_clock -period 10MHz -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] " "create_clock -period 10MHz -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393811651919 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_clock_groups -asynchronous -group \{altera_reserved_tck\} " "set_clock_groups -asynchronous -group \{altera_reserved_tck\}" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393811651919 ""} } { } 0 332165 "Entity %1!s!" 0 0 "" 0 -1 1393811651919 ""} } { } 0 332164 "Evaluating HDL-embedded SDC commands" 0 0 "" 0 -1 1393811651919 ""} -{ "Info" "ISTA_SDC_FOUND" "de0_nano_system.sdc " "Reading SDC File: 'de0_nano_system.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "" 0 -1 1393811652209 ""} -{ "Warning" "WSTA_OVERWRITING_EXISTING_CLOCK" "altera_reserved_tck " "Overwriting existing clock: altera_reserved_tck" { } { } 0 332043 "Overwriting existing clock: %1!s!" 0 0 "" 0 -1 1393811652219 ""} -{ "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "Deriving PLL clocks " "Deriving PLL clocks" { { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -duty_cycle 50.00 -name \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} " "create_generated_clock -source \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -duty_cycle 50.00 -name \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}" { } { } 0 332110 "%1!s!" 0 0 "" 0 -1 1393811652219 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -phase -54.00 -duty_cycle 50.00 -name \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} " "create_generated_clock -source \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -phase -54.00 -duty_cycle 50.00 -name \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}" { } { } 0 332110 "%1!s!" 0 0 "" 0 -1 1393811652219 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 5 -duty_cycle 50.00 -name \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} " "create_generated_clock -source \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 5 -duty_cycle 50.00 -name \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\]\}" { } { } 0 332110 "%1!s!" 0 0 "" 0 -1 1393811652219 ""} } { } 0 332110 "%1!s!" 0 0 "" 0 -1 1393811652219 ""} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_CALL_IS_DELAYED" "" "Clock uncertainty is not calculated until you update the timing netlist." { } { } 0 332151 "Clock uncertainty is not calculated until you update the timing netlist." 0 0 "" 0 -1 1393811652219 ""} -{ "Info" "ISTA_SDC_FOUND" "system/synthesis/submodules/altera_reset_controller.sdc " "Reading SDC File: 'system/synthesis/submodules/altera_reset_controller.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "" 0 -1 1393811652229 ""} -{ "Info" "ISTA_SDC_FOUND" "system/synthesis/submodules/system_cpu.sdc " "Reading SDC File: 'system/synthesis/submodules/system_cpu.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "" 0 -1 1393811652259 ""} -{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "" 0 -1 1393811652449 ""} -{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "" 0 -1 1393811652449 ""} -{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 5 clocks " "Found 5 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "" 0 -1 1393811652449 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "" 0 -1 1393811652449 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 100.000 altera_reserved_tck " " 100.000 altera_reserved_tck" { } { } 0 332111 "%1!s!" 0 0 "" 0 -1 1393811652449 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 20.000 CLOCK_50 " " 20.000 CLOCK_50" { } { } 0 332111 "%1!s!" 0 0 "" 0 -1 1393811652449 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 10.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 10.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\]" { } { } 0 332111 "%1!s!" 0 0 "" 0 -1 1393811652449 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 10.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 10.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[1\]" { } { } 0 332111 "%1!s!" 0 0 "" 0 -1 1393811652449 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 100.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 100.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\]" { } { } 0 332111 "%1!s!" 0 0 "" 0 -1 1393811652449 ""} } { } 0 332111 "%1!s!" 0 0 "" 0 -1 1393811652449 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C0 of PLL_4) " "Automatically promoted node pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C0 of PLL_4)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G18 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G18" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1 1393811652883 ""} } { { "db/pll_sys_altpll.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/pll_sys_altpll.v" 80 -1 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { pll_sys:inst_pll_sys|altpll:altpll_component|pll_sys_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 6290 8336 9085 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1 1393811652883 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|wire_pll1_clk\[1\] (placed in counter C2 of PLL_4) " "Automatically promoted node pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|wire_pll1_clk\[1\] (placed in counter C2 of PLL_4)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G17 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G17" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1 1393811652883 ""} } { { "db/pll_sys_altpll.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/pll_sys_altpll.v" 80 -1 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { pll_sys:inst_pll_sys|altpll:altpll_component|pll_sys_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 6290 8336 9085 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1 1393811652883 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|wire_pll1_clk\[2\] (placed in counter C1 of PLL_4) " "Automatically promoted node pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|wire_pll1_clk\[2\] (placed in counter C1 of PLL_4)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G19 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G19" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1 1393811652883 ""} } { { "db/pll_sys_altpll.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/pll_sys_altpll.v" 80 -1 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { pll_sys:inst_pll_sys|altpll:altpll_component|pll_sys_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 6290 8336 9085 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1 1393811652883 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "altera_internal_jtag~TCKUTAP " "Automatically promoted node altera_internal_jtag~TCKUTAP " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1 1393811652883 ""} } { { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 16160 8336 9085 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1 1393811652883 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "system:inst_cpu\|altera_reset_controller:rst_controller\|altera_reset_synchronizer:alt_rst_sync_uq1\|altera_reset_synchronizer_int_chain_out " "Automatically promoted node system:inst_cpu\|altera_reset_controller:rst_controller\|altera_reset_synchronizer:alt_rst_sync_uq1\|altera_reset_synchronizer_int_chain_out " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1 1393811652883 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr\|counter_reg_bit\[6\] " "Destination node system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr\|counter_reg_bit\[6\]" { } { { "db/cntr_0ab.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/cntr_0ab.tdf" 68 17 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 6531 8336 9085 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "" 0 -1 1393811652883 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr\|counter_reg_bit\[5\] " "Destination node system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr\|counter_reg_bit\[5\]" { } { { "db/cntr_0ab.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/cntr_0ab.tdf" 68 17 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 6532 8336 9085 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "" 0 -1 1393811652883 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr\|counter_reg_bit\[4\] " "Destination node system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr\|counter_reg_bit\[4\]" { } { { "db/cntr_0ab.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/cntr_0ab.tdf" 68 17 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 6533 8336 9085 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "" 0 -1 1393811652883 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr\|counter_reg_bit\[3\] " "Destination node system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr\|counter_reg_bit\[3\]" { } { { "db/cntr_0ab.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/cntr_0ab.tdf" 68 17 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 6534 8336 9085 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "" 0 -1 1393811652883 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr\|counter_reg_bit\[2\] " "Destination node system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr\|counter_reg_bit\[2\]" { } { { "db/cntr_0ab.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/cntr_0ab.tdf" 68 17 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 6535 8336 9085 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "" 0 -1 1393811652883 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr\|counter_reg_bit\[1\] " "Destination node system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr\|counter_reg_bit\[1\]" { } { { "db/cntr_0ab.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/cntr_0ab.tdf" 68 17 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 6536 8336 9085 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "" 0 -1 1393811652883 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr\|counter_reg_bit\[0\] " "Destination node system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr\|counter_reg_bit\[0\]" { } { { "db/cntr_0ab.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/cntr_0ab.tdf" 68 17 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 6537 8336 9085 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "" 0 -1 1393811652883 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_ca7:usedw_counter\|counter_reg_bit\[6\] " "Destination node system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_ca7:usedw_counter\|counter_reg_bit\[6\]" { } { { "db/cntr_ca7.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/cntr_ca7.tdf" 69 17 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_ca7:usedw_counter|counter_reg_bit[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 6554 8336 9085 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "" 0 -1 1393811652883 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_ca7:usedw_counter\|counter_reg_bit\[5\] " "Destination node system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_ca7:usedw_counter\|counter_reg_bit\[5\]" { } { { "db/cntr_ca7.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/cntr_ca7.tdf" 69 17 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_ca7:usedw_counter|counter_reg_bit[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 6555 8336 9085 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "" 0 -1 1393811652883 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_ca7:usedw_counter\|counter_reg_bit\[4\] " "Destination node system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_ca7:usedw_counter\|counter_reg_bit\[4\]" { } { { "db/cntr_ca7.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/cntr_ca7.tdf" 69 17 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_ca7:usedw_counter|counter_reg_bit[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 6556 8336 9085 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "" 0 -1 1393811652883 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_LIMITED_TO_SUB" "10 " "Non-global destination nodes limited to 10 nodes" { } { } 0 176358 "Non-global destination nodes limited to %1!d! nodes" 0 0 "" 0 -1 1393811652883 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0 -1 1393811652883 ""} } { { "system/synthesis/submodules/altera_reset_synchronizer.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_reset_synchronizer.v" 62 -1 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 695 8336 9085 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1 1393811652883 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "sld_hub:auto_hub\|sld_jtag_hub:\\jtag_hub_gen:sld_jtag_hub_inst\|clr_reg " "Automatically promoted node sld_hub:auto_hub\|sld_jtag_hub:\\jtag_hub_gen:sld_jtag_hub_inst\|clr_reg " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1 1393811652883 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "sld_hub:auto_hub\|sld_jtag_hub:\\jtag_hub_gen:sld_jtag_hub_inst\|clr_reg~_wirecell " "Destination node sld_hub:auto_hub\|sld_jtag_hub:\\jtag_hub_gen:sld_jtag_hub_inst\|clr_reg~_wirecell" { } { { "sld_jtag_hub.vhd" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/sld_jtag_hub.vhd" 335 -1 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg~_wirecell } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 16541 8336 9085 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "" 0 -1 1393811652883 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0 -1 1393811652883 ""} } { { "sld_jtag_hub.vhd" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/sld_jtag_hub.vhd" 335 -1 0 } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "sld_hub:auto_hub\|sld_jtag_hub:\\jtag_hub_gen:sld_jtag_hub_inst\|clr_reg" } } } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 16291 8336 9085 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1 1393811652883 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "sld_hub:auto_hub\|sld_jtag_hub:\\jtag_hub_gen:sld_jtag_hub_inst\|sld_shadow_jsm:shadow_jsm\|state\[0\] " "Automatically promoted node sld_hub:auto_hub\|sld_jtag_hub:\\jtag_hub_gen:sld_jtag_hub_inst\|sld_shadow_jsm:shadow_jsm\|state\[0\] " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1 1393811652883 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "sld_hub:auto_hub\|sld_jtag_hub:\\jtag_hub_gen:sld_jtag_hub_inst\|sld_shadow_jsm:shadow_jsm\|state~0 " "Destination node sld_hub:auto_hub\|sld_jtag_hub:\\jtag_hub_gen:sld_jtag_hub_inst\|sld_shadow_jsm:shadow_jsm\|state~0" { } { { "sld_jtag_hub.vhd" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/sld_jtag_hub.vhd" 1076 -1 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 16425 8336 9085 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "" 0 -1 1393811652883 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "sld_hub:auto_hub\|sld_jtag_hub:\\jtag_hub_gen:sld_jtag_hub_inst\|sld_shadow_jsm:shadow_jsm\|state~1 " "Destination node sld_hub:auto_hub\|sld_jtag_hub:\\jtag_hub_gen:sld_jtag_hub_inst\|sld_shadow_jsm:shadow_jsm\|state~1" { } { { "sld_jtag_hub.vhd" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/sld_jtag_hub.vhd" 1076 -1 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state~1 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 16426 8336 9085 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "" 0 -1 1393811652883 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "sld_hub:auto_hub\|sld_jtag_hub:\\jtag_hub_gen:sld_jtag_hub_inst\|sld_shadow_jsm:shadow_jsm\|state\[0\]~_wirecell " "Destination node sld_hub:auto_hub\|sld_jtag_hub:\\jtag_hub_gen:sld_jtag_hub_inst\|sld_shadow_jsm:shadow_jsm\|state\[0\]~_wirecell" { } { { "sld_jtag_hub.vhd" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/sld_jtag_hub.vhd" 1090 -1 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0]~_wirecell } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 16542 8336 9085 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "" 0 -1 1393811652883 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0 -1 1393811652883 ""} } { { "sld_jtag_hub.vhd" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/sld_jtag_hub.vhd" 1090 -1 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 16184 8336 9085 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1 1393811652883 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "system:inst_cpu\|altera_reset_controller:rst_controller\|merged_reset~0 " "Automatically promoted node system:inst_cpu\|altera_reset_controller:rst_controller\|merged_reset~0 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1 1393811652883 ""} } { { "system/synthesis/submodules/altera_reset_controller.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_reset_controller.v" 61 -1 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { system:inst_cpu|altera_reset_controller:rst_controller|merged_reset~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 7557 8336 9085 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1 1393811652883 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "" 0 -1 1393811654427 ""} -{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1 1393811654437 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1 1393811654437 ""} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "" 0 -1 1393811654457 ""} -{ "Warning" "WFSAC_FSAC_IGNORED_FAST_REGISTER_IO_ASSIGNMENTS" "" "Ignoring invalid fast I/O register assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 176250 "Ignoring invalid fast I/O register assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "" 0 -1 1393811657067 ""} -{ "Warning" "WFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS" "" "Ignoring some wildcard destinations of fast I/O register assignments" { { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Enable Register ON oe " "Wildcard assignment \"Fast Output Enable Register=ON\" to \"oe\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1393811657067 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[9\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[9\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1393811657067 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[8\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[8\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1393811657067 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[7\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[7\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1393811657067 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[6\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[6\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1393811657067 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[5\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[5\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1393811657067 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[4\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[4\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1393811657067 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[3\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[3\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1393811657067 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[2\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[2\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1393811657067 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[1\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[1\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1393811657067 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[15\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[15\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1393811657067 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[14\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[14\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1393811657067 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[13\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[13\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1393811657067 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[12\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[12\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1393811657067 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[11\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[11\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1393811657067 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[10\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[10\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1393811657067 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[0\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[0\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1393811657067 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_cmd\[2\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_cmd\[2\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1393811657067 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_cmd\[1\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_cmd\[1\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1393811657067 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_cmd\[0\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_cmd\[0\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1393811657067 ""} } { } 0 176251 "Ignoring some wildcard destinations of fast I/O register assignments" 0 0 "" 0 -1 1393811657067 ""} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "" 0 -1 1393811657067 ""} -{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "" 0 -1 1393811657087 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "" 0 -1 1393811658707 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NUM_REGISTERS_PACKED_INTO_ATOM_TYPE" "10 EC " "Packed 10 registers into blocks of type EC" { } { } 1 176218 "Packed %1!d! registers into blocks of type %2!s!" 0 0 "" 0 -1 1393811660237 ""} { "Extra Info" "IFSAC_NUM_REGISTERS_PACKED_INTO_ATOM_TYPE" "64 Embedded multiplier block " "Packed 64 registers into blocks of type Embedded multiplier block" { } { } 1 176218 "Packed %1!d! registers into blocks of type %2!s!" 0 0 "" 0 -1 1393811660237 ""} { "Extra Info" "IFSAC_NUM_REGISTERS_PACKED_INTO_ATOM_TYPE" "16 I/O Input Buffer " "Packed 16 registers into blocks of type I/O Input Buffer" { } { } 1 176218 "Packed %1!d! registers into blocks of type %2!s!" 0 0 "" 0 -1 1393811660237 ""} { "Extra Info" "IFSAC_NUM_REGISTERS_PACKED_INTO_ATOM_TYPE" "53 I/O Output Buffer " "Packed 53 registers into blocks of type I/O Output Buffer" { } { } 1 176218 "Packed %1!d! registers into blocks of type %2!s!" 0 0 "" 0 -1 1393811660237 ""} { "Extra Info" "IFSAC_NUM_REGISTERS_DUPLICATED" "66 " "Created 66 register duplicates" { } { } 1 176220 "Created %1!d! register duplicates" 0 0 "" 0 -1 1393811660237 ""} } { } 0 176235 "Finished register packing" 0 0 "" 0 -1 1393811660237 ""} -{ "Warning" "WCUT_PLL_CLK_FEEDS_NON_DEDICATED_IO" "pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|pll1 clk\[1\] DRAM_CLK~output " "PLL \"pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|pll1\" output port clk\[1\] feeds output pin \"DRAM_CLK~output\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" { } { { "db/pll_sys_altpll.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/pll_sys_altpll.v" 45 -1 0 } } { "altpll.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altpll.tdf" 897 0 0 } } { "pll_sys.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/pll_sys.vhd" 154 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 152 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 61 0 0 } } } 0 15064 "PLL \"%1!s!\" output port %2!s! feeds output pin \"%3!s!\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" 0 0 "" 0 -1 1393811660377 ""} -{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_CS_N " "Node \"ADC_CS_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393811660507 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SADDR " "Node \"ADC_SADDR\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SADDR" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393811660507 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SCLK " "Node \"ADC_SCLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393811660507 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDAT " "Node \"ADC_SDAT\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393811660507 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0_IN\[0\] " "Node \"GPIO_0_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393811660507 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0_IN\[1\] " "Node \"GPIO_0_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393811660507 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1_IN\[0\] " "Node \"GPIO_1_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393811660507 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1_IN\[1\] " "Node \"GPIO_1_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393811660507 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[0\] " "Node \"GPIO_2\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393811660507 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[10\] " "Node \"GPIO_2\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393811660507 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[11\] " "Node \"GPIO_2\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393811660507 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[12\] " "Node \"GPIO_2\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393811660507 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[1\] " "Node \"GPIO_2\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393811660507 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[2\] " "Node \"GPIO_2\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393811660507 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[3\] " "Node \"GPIO_2\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393811660507 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[4\] " "Node \"GPIO_2\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393811660507 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[5\] " "Node \"GPIO_2\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393811660507 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[6\] " "Node \"GPIO_2\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393811660507 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[7\] " "Node \"GPIO_2\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393811660507 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[8\] " "Node \"GPIO_2\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393811660507 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[9\] " "Node \"GPIO_2\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393811660507 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[0\] " "Node \"GPIO_2_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393811660507 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[1\] " "Node \"GPIO_2_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393811660507 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[2\] " "Node \"GPIO_2_IN\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393811660507 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "G_SENSOR_CS_N " "Node \"G_SENSOR_CS_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "G_SENSOR_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393811660507 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "G_SENSOR_INT " "Node \"G_SENSOR_INT\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "G_SENSOR_INT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393811660507 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SCLK " "Node \"I2C_SCLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "I2C_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393811660507 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SDAT " "Node \"I2C_SDAT\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393811660507 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "" 0 -1 1393811660507 ""} -{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:11 " "Fitter preparation operations ending: elapsed time is 00:00:11" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1 1393811660507 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "" 0 -1 1393811662377 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:02 " "Fitter placement preparation operations ending: elapsed time is 00:00:02" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1 1393811663957 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "" 0 -1 1393811663997 ""} -{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "" 0 -1 1393811671157 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:07 " "Fitter placement operations ending: elapsed time is 00:00:07" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 -1 1393811671157 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "" 0 -1 1393811673017 ""} -{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "6 " "Router estimated average interconnect usage is 6% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "37 X21_Y11 X31_Y22 " "Router estimated peak interconnect usage is 37% of the available device resources in the region that extends from location X21_Y11 to location X31_Y22" { } { { "loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 1 { 0 "Router estimated peak interconnect usage is 37% of the available device resources in the region that extends from location X21_Y11 to location X31_Y22"} { { 11 { 0 "Router estimated peak interconnect usage is 37% of the available device resources in the region that extends from location X21_Y11 to location X31_Y22"} 21 11 11 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1 1393811677587 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1 1393811677587 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:06 " "Fitter routing operations ending: elapsed time is 00:00:06" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 -1 1393811680087 ""} -{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 -1 1393811680087 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 -1 1393811680087 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "" 0 -1 1393811680087 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "" 0 -1 1393811680327 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "" 0 -1 1393811681007 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "" 0 -1 1393811681067 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "" 0 -1 1393811681817 ""} -{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:04 " "Fitter post-fit operations ending: elapsed time is 00:00:04" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "" 0 -1 1393811684047 ""} -{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "" 0 -1 1393811684687 ""} -{ "Warning" "WFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE" "68 " "Following 68 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[0\] a permanently disabled " "Pin GPIO_0\[0\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[0] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[0\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 320 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393811684747 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[1\] a permanently disabled " "Pin GPIO_0\[1\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[1] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[1\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 321 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393811684747 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[2\] a permanently disabled " "Pin GPIO_0\[2\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[2] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[2\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 322 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393811684747 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[3\] a permanently disabled " "Pin GPIO_0\[3\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[3] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[3\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 323 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393811684747 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[4\] a permanently disabled " "Pin GPIO_0\[4\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[4] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[4\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 324 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393811684747 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[5\] a permanently disabled " "Pin GPIO_0\[5\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[5] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[5\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 325 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393811684747 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[6\] a permanently disabled " "Pin GPIO_0\[6\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[6] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[6\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 326 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393811684747 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[7\] a permanently disabled " "Pin GPIO_0\[7\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[7] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[7\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 327 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393811684747 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[8\] a permanently disabled " "Pin GPIO_0\[8\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[8] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[8\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 328 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393811684747 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[9\] a permanently disabled " "Pin GPIO_0\[9\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[9] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[9\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 329 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393811684747 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[10\] a permanently disabled " "Pin GPIO_0\[10\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[10] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[10\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 330 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393811684747 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[11\] a permanently disabled " "Pin GPIO_0\[11\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[11] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[11\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 331 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393811684747 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[12\] a permanently disabled " "Pin GPIO_0\[12\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[12] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[12\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 332 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393811684747 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[13\] a permanently disabled " "Pin GPIO_0\[13\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[13] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[13\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 333 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393811684747 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[14\] a permanently disabled " "Pin GPIO_0\[14\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[14] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[14\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 334 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393811684747 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[15\] a permanently disabled " "Pin GPIO_0\[15\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[15] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[15\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 335 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393811684747 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[16\] a permanently disabled " "Pin GPIO_0\[16\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[16] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[16\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[16] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 336 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393811684747 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[17\] a permanently disabled " "Pin GPIO_0\[17\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[17] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[17\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[17] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 337 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393811684747 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[18\] a permanently disabled " "Pin GPIO_0\[18\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[18] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[18\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[18] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 338 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393811684747 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[19\] a permanently disabled " "Pin GPIO_0\[19\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[19] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[19\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[19] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 339 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393811684747 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[20\] a permanently disabled " "Pin GPIO_0\[20\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[20] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[20\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[20] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 340 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393811684747 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[21\] a permanently disabled " "Pin GPIO_0\[21\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[21] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[21\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[21] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 341 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393811684747 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[22\] a permanently disabled " "Pin GPIO_0\[22\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[22] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[22\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[22] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 342 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393811684747 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[23\] a permanently disabled " "Pin GPIO_0\[23\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[23] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[23\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[23] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 343 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393811684747 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[24\] a permanently disabled " "Pin GPIO_0\[24\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[24] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[24\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[24] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 344 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393811684747 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[25\] a permanently disabled " "Pin GPIO_0\[25\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[25] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[25\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[25] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 345 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393811684747 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[26\] a permanently disabled " "Pin GPIO_0\[26\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[26] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[26\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[26] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 346 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393811684747 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[27\] a permanently disabled " "Pin GPIO_0\[27\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[27] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[27\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[27] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 347 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393811684747 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[28\] a permanently disabled " "Pin GPIO_0\[28\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[28] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[28\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[28] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 348 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393811684747 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[29\] a permanently disabled " "Pin GPIO_0\[29\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[29] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[29\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[29] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 349 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393811684747 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[30\] a permanently disabled " "Pin GPIO_0\[30\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[30] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[30\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[30] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 350 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393811684747 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[32\] a permanently disabled " "Pin GPIO_0\[32\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[32] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[32\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[32] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 351 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393811684747 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[1\] a permanently disabled " "Pin GPIO_1\[1\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[1] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[1\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 352 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393811684747 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[2\] a permanently disabled " "Pin GPIO_1\[2\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[2] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[2\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 353 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393811684747 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[3\] a permanently disabled " "Pin GPIO_1\[3\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[3] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[3\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 354 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393811684747 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[4\] a permanently disabled " "Pin GPIO_1\[4\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[4] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[4\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 355 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393811684747 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[5\] a permanently disabled " "Pin GPIO_1\[5\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[5] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[5\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 356 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393811684747 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[6\] a permanently disabled " "Pin GPIO_1\[6\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[6] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[6\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 357 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393811684747 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[7\] a permanently disabled " "Pin GPIO_1\[7\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[7] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[7\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 358 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393811684747 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[8\] a permanently disabled " "Pin GPIO_1\[8\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[8] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[8\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 359 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393811684747 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[9\] a permanently disabled " "Pin GPIO_1\[9\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[9] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[9\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 360 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393811684747 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[10\] a permanently disabled " "Pin GPIO_1\[10\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[10] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[10\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 361 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393811684747 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[11\] a permanently disabled " "Pin GPIO_1\[11\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[11] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[11\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 362 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393811684747 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[12\] a permanently disabled " "Pin GPIO_1\[12\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[12] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[12\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 363 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393811684747 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[13\] a permanently disabled " "Pin GPIO_1\[13\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[13] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[13\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 364 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393811684747 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[14\] a permanently disabled " "Pin GPIO_1\[14\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[14] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[14\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 365 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393811684747 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[15\] a permanently disabled " "Pin GPIO_1\[15\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[15] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[15\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 366 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393811684747 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[16\] a permanently disabled " "Pin GPIO_1\[16\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[16] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[16\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[16] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 367 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393811684747 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[17\] a permanently disabled " "Pin GPIO_1\[17\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[17] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[17\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[17] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 368 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393811684747 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[18\] a permanently disabled " "Pin GPIO_1\[18\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[18] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[18\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[18] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 369 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393811684747 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[19\] a permanently disabled " "Pin GPIO_1\[19\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[19] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[19\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[19] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 370 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393811684747 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[20\] a permanently disabled " "Pin GPIO_1\[20\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[20] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[20\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[20] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 371 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393811684747 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[21\] a permanently disabled " "Pin GPIO_1\[21\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[21] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[21\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[21] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 372 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393811684747 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[22\] a permanently disabled " "Pin GPIO_1\[22\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[22] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[22\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[22] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 373 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393811684747 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[23\] a permanently disabled " "Pin GPIO_1\[23\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[23] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[23\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[23] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 374 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393811684747 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[24\] a permanently disabled " "Pin GPIO_1\[24\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[24] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[24\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[24] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 375 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393811684747 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[25\] a permanently disabled " "Pin GPIO_1\[25\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[25] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[25\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[25] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 376 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393811684747 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[26\] a permanently disabled " "Pin GPIO_1\[26\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[26] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[26\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[26] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 377 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393811684747 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[27\] a permanently disabled " "Pin GPIO_1\[27\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[27] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[27\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[27] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 378 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393811684747 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[28\] a permanently disabled " "Pin GPIO_1\[28\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[28] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[28\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[28] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 379 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393811684747 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[29\] a permanently disabled " "Pin GPIO_1\[29\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[29] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[29\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[29] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 380 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393811684747 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[30\] a permanently disabled " "Pin GPIO_1\[30\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[30] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[30\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[30] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 381 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393811684747 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[32\] a permanently disabled " "Pin GPIO_1\[32\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[32] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[32\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[32] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 382 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393811684747 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[31\] a permanently disabled " "Pin GPIO_0\[31\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[31] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[31\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[31] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 271 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393811684747 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[33\] a permanently enabled " "Pin GPIO_0\[33\] has a permanently enabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[33] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[33\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[33] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 268 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393811684747 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[0\] a permanently enabled " "Pin GPIO_1\[0\] has a permanently enabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[0] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[0\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 272 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393811684747 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[31\] a permanently disabled " "Pin GPIO_1\[31\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[31] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[31\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[31] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 270 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393811684747 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[33\] a permanently enabled " "Pin GPIO_1\[33\] has a permanently enabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[33] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[33\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[33] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 269 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393811684747 ""} } { } 0 169064 "Following %1!d! pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results" 0 0 "" 0 -1 1393811684747 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/output_files/de0_nano_system.fit.smsg " "Generated suppressed messages file C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/output_files/de0_nano_system.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "" 0 -1 1393811685307 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 36 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 36 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1138 " "Peak virtual memory: 1138 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1 1393811686897 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Mar 02 18:54:46 2014 " "Processing ended: Sun Mar 02 18:54:46 2014" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1 1393811686897 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:38 " "Elapsed time: 00:00:38" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1 1393811686897 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:47 " "Total CPU time (on all processors): 00:00:47" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1 1393811686897 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1 1393811686897 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1 1393888342009 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 64-Bit " "Running Quartus II 64-Bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Full Version " "Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1 1393888342009 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 03 16:12:21 2014 " "Processing started: Mon Mar 03 16:12:21 2014" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1 1393888342009 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1 1393888342009 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off de0_nano_system -c de0_nano_system " "Command: quartus_fit --read_settings_files=off --write_settings_files=off de0_nano_system -c de0_nano_system" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1 1393888342009 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." { } { } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "" 0 -1 1393888342172 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "de0_nano_system EP4CE22F17C6 " "Selected device EP4CE22F17C6 for design \"de0_nano_system\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 -1 1393888342469 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "" 0 -1 1393888342516 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "" 0 -1 1393888342516 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "" 0 -1 1393888342517 ""} +{ "Info" "ICUT_CUT_PLL_COMPUTATION_SUCCESS" "pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|pll1 Cyclone IV E PLL " "Implemented PLL \"pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|pll1\" as Cyclone IV E PLL type" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|wire_pll1_clk\[0\] 2 1 0 0 " "Implementing clock multiplication of 2, clock division of 1, and phase shift of 0 degrees (0 ps) for pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|wire_pll1_clk\[0\] port" { } { { "db/pll_sys_altpll.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/pll_sys_altpll.v" 45 -1 0 } } { "" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 6291 8336 9085 0} } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "" 0 -1 1393888342563 ""} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|wire_pll1_clk\[1\] 2 1 -54 -1500 " "Implementing clock multiplication of 2, clock division of 1, and phase shift of -54 degrees (-1500 ps) for pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|wire_pll1_clk\[1\] port" { } { { "db/pll_sys_altpll.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/pll_sys_altpll.v" 45 -1 0 } } { "" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 6292 8336 9085 0} } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "" 0 -1 1393888342563 ""} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|wire_pll1_clk\[2\] 1 5 0 0 " "Implementing clock multiplication of 1, clock division of 5, and phase shift of 0 degrees (0 ps) for pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|wire_pll1_clk\[2\] port" { } { { "db/pll_sys_altpll.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/pll_sys_altpll.v" 45 -1 0 } } { "" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 6293 8336 9085 0} } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "" 0 -1 1393888342563 ""} } { { "db/pll_sys_altpll.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/pll_sys_altpll.v" 45 -1 0 } } { "" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 6291 8336 9085 0} } } } } 0 15535 "Implemented %3!s! \"%1!s!\" as %2!s! PLL type" 0 0 "" 0 -1 1393888342563 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0 -1 1393888342768 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE10F17C6 " "Device EP4CE10F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "" 0 -1 1393888343062 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE6F17C6 " "Device EP4CE6F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "" 0 -1 1393888343062 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE15F17C6 " "Device EP4CE15F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "" 0 -1 1393888343062 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 -1 1393888343062 ""} +{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ C1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location C1" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 16681 8336 9085 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1 1393888343077 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ D2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location D2" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 16683 8336 9085 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1 1393888343077 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ H1 " "Pin ~ALTERA_DCLK~ is reserved at location H1" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 16685 8336 9085 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1 1393888343077 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ H2 " "Pin ~ALTERA_DATA0~ is reserved at location H2" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 16687 8336 9085 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1 1393888343077 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ F16 " "Pin ~ALTERA_nCEO~ is reserved at location F16" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 16689 8336 9085 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1 1393888343077 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 -1 1393888343077 ""} +{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "" 0 -1 1393888343079 ""} +{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." { } { } 0 176045 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "" 0 -1 1393888343136 ""} +{ "Info" "ISTA_SDC_STATEMENT_PARENT" "" "Evaluating HDL-embedded SDC commands" { { "Info" "ISTA_SDC_STATEMENT_ENTITY" "alt_jtag_atlantic " "Entity alt_jtag_atlantic" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate1*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate1*\}\] " { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393888344865 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393888344865 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393888344865 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393888344865 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393888344865 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393888344865 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393888344865 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393888344865 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393888344865 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|read1*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|read1*\}\] " { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393888344865 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read_req\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read_req\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393888344865 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393888344865 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|tck_t_dav\}\] " "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|tck_t_dav\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393888344865 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|user_saw_rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid0*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|user_saw_rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid0*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393888344865 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393888344865 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393888344865 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393888344865 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393888344865 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393888344865 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393888344865 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393888344865 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393888344865 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write1*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write1*\}\] " { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393888344865 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_ena*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_ena*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393888344865 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_pause*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_pause*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393888344865 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_valid\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_valid\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393888344865 ""} } { } 0 332165 "Entity %1!s!" 0 0 "" 0 -1 1393888344865 ""} { "Info" "ISTA_SDC_STATEMENT_ENTITY" "altera_std_synchronizer " "Entity altera_std_synchronizer" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -to \[get_keepers \{*altera_std_synchronizer:*\|din_s1\}\] " "set_false_path -to \[get_keepers \{*altera_std_synchronizer:*\|din_s1\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393888344865 ""} } { } 0 332165 "Entity %1!s!" 0 0 "" 0 -1 1393888344865 ""} { "Info" "ISTA_SDC_STATEMENT_ENTITY" "sld_jtag_hub " "Entity sld_jtag_hub" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "create_clock -period 10MHz -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] " "create_clock -period 10MHz -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393888344865 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_clock_groups -asynchronous -group \{altera_reserved_tck\} " "set_clock_groups -asynchronous -group \{altera_reserved_tck\}" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393888344865 ""} } { } 0 332165 "Entity %1!s!" 0 0 "" 0 -1 1393888344865 ""} } { } 0 332164 "Evaluating HDL-embedded SDC commands" 0 0 "" 0 -1 1393888344865 ""} +{ "Info" "ISTA_SDC_FOUND" "de0_nano_system.sdc " "Reading SDC File: 'de0_nano_system.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "" 0 -1 1393888345151 ""} +{ "Warning" "WSTA_OVERWRITING_EXISTING_CLOCK" "altera_reserved_tck " "Overwriting existing clock: altera_reserved_tck" { } { } 0 332043 "Overwriting existing clock: %1!s!" 0 0 "" 0 -1 1393888345167 ""} +{ "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "Deriving PLL clocks " "Deriving PLL clocks" { { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -duty_cycle 50.00 -name \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} " "create_generated_clock -source \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -duty_cycle 50.00 -name \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}" { } { } 0 332110 "%1!s!" 0 0 "" 0 -1 1393888345168 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -phase -54.00 -duty_cycle 50.00 -name \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} " "create_generated_clock -source \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -phase -54.00 -duty_cycle 50.00 -name \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}" { } { } 0 332110 "%1!s!" 0 0 "" 0 -1 1393888345168 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 5 -duty_cycle 50.00 -name \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} " "create_generated_clock -source \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 5 -duty_cycle 50.00 -name \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\]\}" { } { } 0 332110 "%1!s!" 0 0 "" 0 -1 1393888345168 ""} } { } 0 332110 "%1!s!" 0 0 "" 0 -1 1393888345168 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_CALL_IS_DELAYED" "" "Clock uncertainty is not calculated until you update the timing netlist." { } { } 0 332151 "Clock uncertainty is not calculated until you update the timing netlist." 0 0 "" 0 -1 1393888345168 ""} +{ "Info" "ISTA_SDC_FOUND" "system/synthesis/submodules/altera_reset_controller.sdc " "Reading SDC File: 'system/synthesis/submodules/altera_reset_controller.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "" 0 -1 1393888345176 ""} +{ "Info" "ISTA_SDC_FOUND" "system/synthesis/submodules/system_cpu.sdc " "Reading SDC File: 'system/synthesis/submodules/system_cpu.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "" 0 -1 1393888345203 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "" 0 -1 1393888345393 ""} +{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "" 0 -1 1393888345395 ""} +{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 5 clocks " "Found 5 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "" 0 -1 1393888345396 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "" 0 -1 1393888345396 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 100.000 altera_reserved_tck " " 100.000 altera_reserved_tck" { } { } 0 332111 "%1!s!" 0 0 "" 0 -1 1393888345396 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 20.000 CLOCK_50 " " 20.000 CLOCK_50" { } { } 0 332111 "%1!s!" 0 0 "" 0 -1 1393888345396 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 10.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 10.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\]" { } { } 0 332111 "%1!s!" 0 0 "" 0 -1 1393888345396 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 10.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 10.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[1\]" { } { } 0 332111 "%1!s!" 0 0 "" 0 -1 1393888345396 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 100.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 100.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\]" { } { } 0 332111 "%1!s!" 0 0 "" 0 -1 1393888345396 ""} } { } 0 332111 "%1!s!" 0 0 "" 0 -1 1393888345396 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C0 of PLL_4) " "Automatically promoted node pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C0 of PLL_4)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G18 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G18" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1 1393888345841 ""} } { { "db/pll_sys_altpll.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/pll_sys_altpll.v" 80 -1 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { pll_sys:inst_pll_sys|altpll:altpll_component|pll_sys_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 6291 8336 9085 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1 1393888345841 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|wire_pll1_clk\[1\] (placed in counter C2 of PLL_4) " "Automatically promoted node pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|wire_pll1_clk\[1\] (placed in counter C2 of PLL_4)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G17 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G17" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1 1393888345841 ""} } { { "db/pll_sys_altpll.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/pll_sys_altpll.v" 80 -1 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { pll_sys:inst_pll_sys|altpll:altpll_component|pll_sys_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 6291 8336 9085 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1 1393888345841 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|wire_pll1_clk\[2\] (placed in counter C1 of PLL_4) " "Automatically promoted node pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|wire_pll1_clk\[2\] (placed in counter C1 of PLL_4)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G19 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G19" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1 1393888345841 ""} } { { "db/pll_sys_altpll.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/pll_sys_altpll.v" 80 -1 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { pll_sys:inst_pll_sys|altpll:altpll_component|pll_sys_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 6291 8336 9085 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1 1393888345841 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "altera_internal_jtag~TCKUTAP " "Automatically promoted node altera_internal_jtag~TCKUTAP " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1 1393888345841 ""} } { { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 16157 8336 9085 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1 1393888345841 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "system:inst_cpu\|altera_reset_controller:rst_controller\|altera_reset_synchronizer:alt_rst_sync_uq1\|altera_reset_synchronizer_int_chain_out " "Automatically promoted node system:inst_cpu\|altera_reset_controller:rst_controller\|altera_reset_synchronizer:alt_rst_sync_uq1\|altera_reset_synchronizer_int_chain_out " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1 1393888345841 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr\|counter_reg_bit\[6\] " "Destination node system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr\|counter_reg_bit\[6\]" { } { { "db/cntr_0ab.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/cntr_0ab.tdf" 68 17 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 6532 8336 9085 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "" 0 -1 1393888345841 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr\|counter_reg_bit\[5\] " "Destination node system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr\|counter_reg_bit\[5\]" { } { { "db/cntr_0ab.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/cntr_0ab.tdf" 68 17 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 6533 8336 9085 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "" 0 -1 1393888345841 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr\|counter_reg_bit\[4\] " "Destination node system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr\|counter_reg_bit\[4\]" { } { { "db/cntr_0ab.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/cntr_0ab.tdf" 68 17 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 6534 8336 9085 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "" 0 -1 1393888345841 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr\|counter_reg_bit\[3\] " "Destination node system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr\|counter_reg_bit\[3\]" { } { { "db/cntr_0ab.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/cntr_0ab.tdf" 68 17 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 6535 8336 9085 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "" 0 -1 1393888345841 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr\|counter_reg_bit\[2\] " "Destination node system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr\|counter_reg_bit\[2\]" { } { { "db/cntr_0ab.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/cntr_0ab.tdf" 68 17 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 6536 8336 9085 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "" 0 -1 1393888345841 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr\|counter_reg_bit\[1\] " "Destination node system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr\|counter_reg_bit\[1\]" { } { { "db/cntr_0ab.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/cntr_0ab.tdf" 68 17 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 6537 8336 9085 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "" 0 -1 1393888345841 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr\|counter_reg_bit\[0\] " "Destination node system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr\|counter_reg_bit\[0\]" { } { { "db/cntr_0ab.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/cntr_0ab.tdf" 68 17 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 6538 8336 9085 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "" 0 -1 1393888345841 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_ca7:usedw_counter\|counter_reg_bit\[6\] " "Destination node system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_ca7:usedw_counter\|counter_reg_bit\[6\]" { } { { "db/cntr_ca7.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/cntr_ca7.tdf" 69 17 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_ca7:usedw_counter|counter_reg_bit[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 6555 8336 9085 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "" 0 -1 1393888345841 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_ca7:usedw_counter\|counter_reg_bit\[5\] " "Destination node system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_ca7:usedw_counter\|counter_reg_bit\[5\]" { } { { "db/cntr_ca7.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/cntr_ca7.tdf" 69 17 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_ca7:usedw_counter|counter_reg_bit[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 6556 8336 9085 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "" 0 -1 1393888345841 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_ca7:usedw_counter\|counter_reg_bit\[4\] " "Destination node system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_ca7:usedw_counter\|counter_reg_bit\[4\]" { } { { "db/cntr_ca7.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/cntr_ca7.tdf" 69 17 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_ca7:usedw_counter|counter_reg_bit[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 6557 8336 9085 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "" 0 -1 1393888345841 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_LIMITED_TO_SUB" "10 " "Non-global destination nodes limited to 10 nodes" { } { } 0 176358 "Non-global destination nodes limited to %1!d! nodes" 0 0 "" 0 -1 1393888345841 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0 -1 1393888345841 ""} } { { "system/synthesis/submodules/altera_reset_synchronizer.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_reset_synchronizer.v" 62 -1 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 695 8336 9085 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1 1393888345841 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "sld_hub:auto_hub\|sld_jtag_hub:\\jtag_hub_gen:sld_jtag_hub_inst\|clr_reg " "Automatically promoted node sld_hub:auto_hub\|sld_jtag_hub:\\jtag_hub_gen:sld_jtag_hub_inst\|clr_reg " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1 1393888345843 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "sld_hub:auto_hub\|sld_jtag_hub:\\jtag_hub_gen:sld_jtag_hub_inst\|clr_reg~_wirecell " "Destination node sld_hub:auto_hub\|sld_jtag_hub:\\jtag_hub_gen:sld_jtag_hub_inst\|clr_reg~_wirecell" { } { { "sld_jtag_hub.vhd" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/sld_jtag_hub.vhd" 335 -1 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg~_wirecell } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 16541 8336 9085 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "" 0 -1 1393888345843 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0 -1 1393888345843 ""} } { { "sld_jtag_hub.vhd" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/sld_jtag_hub.vhd" 335 -1 0 } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "sld_hub:auto_hub\|sld_jtag_hub:\\jtag_hub_gen:sld_jtag_hub_inst\|clr_reg" } } } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 16288 8336 9085 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1 1393888345843 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "sld_hub:auto_hub\|sld_jtag_hub:\\jtag_hub_gen:sld_jtag_hub_inst\|sld_shadow_jsm:shadow_jsm\|state\[0\] " "Automatically promoted node sld_hub:auto_hub\|sld_jtag_hub:\\jtag_hub_gen:sld_jtag_hub_inst\|sld_shadow_jsm:shadow_jsm\|state\[0\] " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1 1393888345844 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "sld_hub:auto_hub\|sld_jtag_hub:\\jtag_hub_gen:sld_jtag_hub_inst\|sld_shadow_jsm:shadow_jsm\|state~0 " "Destination node sld_hub:auto_hub\|sld_jtag_hub:\\jtag_hub_gen:sld_jtag_hub_inst\|sld_shadow_jsm:shadow_jsm\|state~0" { } { { "sld_jtag_hub.vhd" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/sld_jtag_hub.vhd" 1076 -1 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 16422 8336 9085 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "" 0 -1 1393888345844 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "sld_hub:auto_hub\|sld_jtag_hub:\\jtag_hub_gen:sld_jtag_hub_inst\|sld_shadow_jsm:shadow_jsm\|state~1 " "Destination node sld_hub:auto_hub\|sld_jtag_hub:\\jtag_hub_gen:sld_jtag_hub_inst\|sld_shadow_jsm:shadow_jsm\|state~1" { } { { "sld_jtag_hub.vhd" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/sld_jtag_hub.vhd" 1076 -1 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state~1 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 16423 8336 9085 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "" 0 -1 1393888345844 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "sld_hub:auto_hub\|sld_jtag_hub:\\jtag_hub_gen:sld_jtag_hub_inst\|sld_shadow_jsm:shadow_jsm\|state\[0\]~_wirecell " "Destination node sld_hub:auto_hub\|sld_jtag_hub:\\jtag_hub_gen:sld_jtag_hub_inst\|sld_shadow_jsm:shadow_jsm\|state\[0\]~_wirecell" { } { { "sld_jtag_hub.vhd" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/sld_jtag_hub.vhd" 1090 -1 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0]~_wirecell } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 16542 8336 9085 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "" 0 -1 1393888345844 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0 -1 1393888345844 ""} } { { "sld_jtag_hub.vhd" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/sld_jtag_hub.vhd" 1090 -1 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 16181 8336 9085 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1 1393888345844 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "system:inst_cpu\|altera_reset_controller:rst_controller\|merged_reset~0 " "Automatically promoted node system:inst_cpu\|altera_reset_controller:rst_controller\|merged_reset~0 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1 1393888345845 ""} } { { "system/synthesis/submodules/altera_reset_controller.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_reset_controller.v" 61 -1 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { system:inst_cpu|altera_reset_controller:rst_controller|merged_reset~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 7558 8336 9085 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1 1393888345845 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "" 0 -1 1393888347381 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1 1393888347394 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1 1393888347394 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "" 0 -1 1393888347409 ""} +{ "Warning" "WFSAC_FSAC_IGNORED_FAST_REGISTER_IO_ASSIGNMENTS" "" "Ignoring invalid fast I/O register assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 176250 "Ignoring invalid fast I/O register assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "" 0 -1 1393888350041 ""} +{ "Warning" "WFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS" "" "Ignoring some wildcard destinations of fast I/O register assignments" { { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Enable Register ON oe " "Wildcard assignment \"Fast Output Enable Register=ON\" to \"oe\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1393888350042 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[9\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[9\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1393888350042 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[8\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[8\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1393888350042 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[7\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[7\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1393888350042 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[6\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[6\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1393888350042 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[5\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[5\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1393888350042 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[4\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[4\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1393888350042 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[3\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[3\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1393888350042 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[2\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[2\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1393888350042 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[1\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[1\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1393888350042 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[15\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[15\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1393888350042 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[14\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[14\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1393888350042 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[13\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[13\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1393888350042 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[12\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[12\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1393888350042 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[11\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[11\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1393888350042 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[10\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[10\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1393888350042 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[0\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[0\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1393888350042 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_cmd\[2\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_cmd\[2\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1393888350042 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_cmd\[1\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_cmd\[1\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1393888350042 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_cmd\[0\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_cmd\[0\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1393888350042 ""} } { } 0 176251 "Ignoring some wildcard destinations of fast I/O register assignments" 0 0 "" 0 -1 1393888350042 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "" 0 -1 1393888350044 ""} +{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "" 0 -1 1393888350056 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "" 0 -1 1393888351689 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NUM_REGISTERS_PACKED_INTO_ATOM_TYPE" "10 EC " "Packed 10 registers into blocks of type EC" { } { } 1 176218 "Packed %1!d! registers into blocks of type %2!s!" 0 0 "" 0 -1 1393888353212 ""} { "Extra Info" "IFSAC_NUM_REGISTERS_PACKED_INTO_ATOM_TYPE" "64 Embedded multiplier block " "Packed 64 registers into blocks of type Embedded multiplier block" { } { } 1 176218 "Packed %1!d! registers into blocks of type %2!s!" 0 0 "" 0 -1 1393888353212 ""} { "Extra Info" "IFSAC_NUM_REGISTERS_PACKED_INTO_ATOM_TYPE" "16 I/O Input Buffer " "Packed 16 registers into blocks of type I/O Input Buffer" { } { } 1 176218 "Packed %1!d! registers into blocks of type %2!s!" 0 0 "" 0 -1 1393888353212 ""} { "Extra Info" "IFSAC_NUM_REGISTERS_PACKED_INTO_ATOM_TYPE" "53 I/O Output Buffer " "Packed 53 registers into blocks of type I/O Output Buffer" { } { } 1 176218 "Packed %1!d! registers into blocks of type %2!s!" 0 0 "" 0 -1 1393888353212 ""} { "Extra Info" "IFSAC_NUM_REGISTERS_DUPLICATED" "66 " "Created 66 register duplicates" { } { } 1 176220 "Created %1!d! register duplicates" 0 0 "" 0 -1 1393888353212 ""} } { } 0 176235 "Finished register packing" 0 0 "" 0 -1 1393888353212 ""} +{ "Warning" "WCUT_PLL_CLK_FEEDS_NON_DEDICATED_IO" "pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|pll1 clk\[1\] DRAM_CLK~output " "PLL \"pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|pll1\" output port clk\[1\] feeds output pin \"DRAM_CLK~output\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" { } { { "db/pll_sys_altpll.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/pll_sys_altpll.v" 45 -1 0 } } { "altpll.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altpll.tdf" 897 0 0 } } { "pll_sys.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/pll_sys.vhd" 154 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 152 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 61 0 0 } } } 0 15064 "PLL \"%1!s!\" output port %2!s! feeds output pin \"%3!s!\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" 0 0 "" 0 -1 1393888353361 ""} +{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_CS_N " "Node \"ADC_CS_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393888353493 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SADDR " "Node \"ADC_SADDR\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SADDR" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393888353493 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SCLK " "Node \"ADC_SCLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393888353493 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDAT " "Node \"ADC_SDAT\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393888353493 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0_IN\[0\] " "Node \"GPIO_0_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393888353493 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0_IN\[1\] " "Node \"GPIO_0_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393888353493 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1_IN\[0\] " "Node \"GPIO_1_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393888353493 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1_IN\[1\] " "Node \"GPIO_1_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393888353493 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[0\] " "Node \"GPIO_2\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393888353493 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[10\] " "Node \"GPIO_2\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393888353493 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[11\] " "Node \"GPIO_2\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393888353493 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[12\] " "Node \"GPIO_2\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393888353493 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[1\] " "Node \"GPIO_2\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393888353493 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[2\] " "Node \"GPIO_2\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393888353493 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[3\] " "Node \"GPIO_2\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393888353493 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[4\] " "Node \"GPIO_2\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393888353493 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[5\] " "Node \"GPIO_2\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393888353493 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[6\] " "Node \"GPIO_2\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393888353493 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[7\] " "Node \"GPIO_2\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393888353493 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[8\] " "Node \"GPIO_2\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393888353493 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[9\] " "Node \"GPIO_2\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393888353493 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[0\] " "Node \"GPIO_2_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393888353493 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[1\] " "Node \"GPIO_2_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393888353493 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[2\] " "Node \"GPIO_2_IN\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393888353493 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "G_SENSOR_CS_N " "Node \"G_SENSOR_CS_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "G_SENSOR_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393888353493 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "G_SENSOR_INT " "Node \"G_SENSOR_INT\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "G_SENSOR_INT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393888353493 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SCLK " "Node \"I2C_SCLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "I2C_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393888353493 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SDAT " "Node \"I2C_SDAT\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393888353493 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "" 0 -1 1393888353493 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:11 " "Fitter preparation operations ending: elapsed time is 00:00:11" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1 1393888353495 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "" 0 -1 1393888355356 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:02 " "Fitter placement preparation operations ending: elapsed time is 00:00:02" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1 1393888356990 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "" 0 -1 1393888357037 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "" 0 -1 1393888364467 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:07 " "Fitter placement operations ending: elapsed time is 00:00:07" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 -1 1393888364468 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "" 0 -1 1393888366329 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "7 " "Router estimated average interconnect usage is 7% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "36 X21_Y11 X31_Y22 " "Router estimated peak interconnect usage is 36% of the available device resources in the region that extends from location X21_Y11 to location X31_Y22" { } { { "loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 1 { 0 "Router estimated peak interconnect usage is 36% of the available device resources in the region that extends from location X21_Y11 to location X31_Y22"} { { 11 { 0 "Router estimated peak interconnect usage is 36% of the available device resources in the region that extends from location X21_Y11 to location X31_Y22"} 21 11 11 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1 1393888371091 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1 1393888371091 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:09 " "Fitter routing operations ending: elapsed time is 00:00:09" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 -1 1393888376195 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 -1 1393888376198 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 -1 1393888376198 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "" 0 -1 1393888376198 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "" 0 -1 1393888376439 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "" 0 -1 1393888377127 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "" 0 -1 1393888377190 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "" 0 -1 1393888377931 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:04 " "Fitter post-fit operations ending: elapsed time is 00:00:04" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "" 0 -1 1393888380204 ""} +{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "" 0 -1 1393888380840 ""} +{ "Warning" "WFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE" "68 " "Following 68 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[0\] a permanently disabled " "Pin GPIO_0\[0\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[0] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[0\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 320 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393888380895 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[1\] a permanently disabled " "Pin GPIO_0\[1\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[1] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[1\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 321 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393888380895 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[2\] a permanently disabled " "Pin GPIO_0\[2\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[2] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[2\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 322 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393888380895 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[3\] a permanently disabled " "Pin GPIO_0\[3\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[3] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[3\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 323 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393888380895 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[4\] a permanently disabled " "Pin GPIO_0\[4\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[4] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[4\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 324 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393888380895 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[5\] a permanently disabled " "Pin GPIO_0\[5\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[5] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[5\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 325 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393888380895 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[6\] a permanently disabled " "Pin GPIO_0\[6\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[6] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[6\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 326 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393888380895 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[7\] a permanently disabled " "Pin GPIO_0\[7\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[7] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[7\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 327 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393888380895 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[8\] a permanently disabled " "Pin GPIO_0\[8\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[8] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[8\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 328 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393888380895 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[9\] a permanently disabled " "Pin GPIO_0\[9\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[9] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[9\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 329 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393888380895 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[10\] a permanently disabled " "Pin GPIO_0\[10\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[10] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[10\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 330 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393888380895 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[11\] a permanently disabled " "Pin GPIO_0\[11\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[11] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[11\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 331 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393888380895 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[12\] a permanently disabled " "Pin GPIO_0\[12\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[12] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[12\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 332 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393888380895 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[13\] a permanently disabled " "Pin GPIO_0\[13\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[13] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[13\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 333 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393888380895 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[14\] a permanently disabled " "Pin GPIO_0\[14\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[14] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[14\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 334 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393888380895 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[15\] a permanently disabled " "Pin GPIO_0\[15\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[15] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[15\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 335 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393888380895 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[16\] a permanently disabled " "Pin GPIO_0\[16\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[16] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[16\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[16] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 336 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393888380895 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[17\] a permanently disabled " "Pin GPIO_0\[17\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[17] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[17\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[17] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 337 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393888380895 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[18\] a permanently disabled " "Pin GPIO_0\[18\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[18] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[18\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[18] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 338 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393888380895 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[19\] a permanently disabled " "Pin GPIO_0\[19\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[19] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[19\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[19] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 339 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393888380895 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[20\] a permanently disabled " "Pin GPIO_0\[20\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[20] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[20\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[20] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 340 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393888380895 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[21\] a permanently disabled " "Pin GPIO_0\[21\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[21] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[21\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[21] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 341 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393888380895 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[22\] a permanently disabled " "Pin GPIO_0\[22\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[22] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[22\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[22] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 342 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393888380895 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[23\] a permanently disabled " "Pin GPIO_0\[23\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[23] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[23\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[23] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 343 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393888380895 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[24\] a permanently disabled " "Pin GPIO_0\[24\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[24] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[24\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[24] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 344 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393888380895 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[25\] a permanently disabled " "Pin GPIO_0\[25\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[25] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[25\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[25] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 345 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393888380895 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[26\] a permanently disabled " "Pin GPIO_0\[26\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[26] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[26\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[26] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 346 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393888380895 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[27\] a permanently disabled " "Pin GPIO_0\[27\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[27] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[27\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[27] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 347 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393888380895 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[28\] a permanently disabled " "Pin GPIO_0\[28\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[28] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[28\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[28] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 348 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393888380895 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[29\] a permanently disabled " "Pin GPIO_0\[29\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[29] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[29\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[29] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 349 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393888380895 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[30\] a permanently disabled " "Pin GPIO_0\[30\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[30] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[30\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[30] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 350 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393888380895 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[32\] a permanently disabled " "Pin GPIO_0\[32\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[32] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[32\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[32] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 351 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393888380895 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[1\] a permanently disabled " "Pin GPIO_1\[1\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[1] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[1\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 352 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393888380895 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[2\] a permanently disabled " "Pin GPIO_1\[2\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[2] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[2\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 353 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393888380895 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[3\] a permanently disabled " "Pin GPIO_1\[3\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[3] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[3\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 354 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393888380895 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[4\] a permanently disabled " "Pin GPIO_1\[4\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[4] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[4\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 355 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393888380895 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[5\] a permanently disabled " "Pin GPIO_1\[5\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[5] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[5\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 356 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393888380895 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[6\] a permanently disabled " "Pin GPIO_1\[6\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[6] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[6\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 357 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393888380895 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[7\] a permanently disabled " "Pin GPIO_1\[7\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[7] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[7\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 358 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393888380895 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[8\] a permanently disabled " "Pin GPIO_1\[8\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[8] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[8\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 359 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393888380895 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[9\] a permanently disabled " "Pin GPIO_1\[9\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[9] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[9\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 360 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393888380895 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[10\] a permanently disabled " "Pin GPIO_1\[10\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[10] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[10\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 361 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393888380895 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[11\] a permanently disabled " "Pin GPIO_1\[11\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[11] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[11\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 362 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393888380895 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[12\] a permanently disabled " "Pin GPIO_1\[12\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[12] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[12\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 363 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393888380895 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[13\] a permanently disabled " "Pin GPIO_1\[13\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[13] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[13\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 364 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393888380895 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[14\] a permanently disabled " "Pin GPIO_1\[14\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[14] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[14\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 365 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393888380895 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[15\] a permanently disabled " "Pin GPIO_1\[15\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[15] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[15\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 366 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393888380895 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[16\] a permanently disabled " "Pin GPIO_1\[16\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[16] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[16\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[16] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 367 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393888380895 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[17\] a permanently disabled " "Pin GPIO_1\[17\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[17] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[17\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[17] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 368 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393888380895 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[18\] a permanently disabled " "Pin GPIO_1\[18\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[18] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[18\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[18] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 369 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393888380895 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[19\] a permanently disabled " "Pin GPIO_1\[19\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[19] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[19\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[19] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 370 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393888380895 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[20\] a permanently disabled " "Pin GPIO_1\[20\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[20] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[20\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[20] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 371 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393888380895 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[21\] a permanently disabled " "Pin GPIO_1\[21\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[21] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[21\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[21] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 372 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393888380895 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[22\] a permanently disabled " "Pin GPIO_1\[22\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[22] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[22\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[22] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 373 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393888380895 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[23\] a permanently disabled " "Pin GPIO_1\[23\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[23] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[23\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[23] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 374 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393888380895 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[24\] a permanently disabled " "Pin GPIO_1\[24\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[24] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[24\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[24] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 375 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393888380895 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[25\] a permanently disabled " "Pin GPIO_1\[25\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[25] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[25\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[25] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 376 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393888380895 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[26\] a permanently disabled " "Pin GPIO_1\[26\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[26] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[26\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[26] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 377 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393888380895 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[27\] a permanently disabled " "Pin GPIO_1\[27\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[27] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[27\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[27] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 378 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393888380895 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[28\] a permanently disabled " "Pin GPIO_1\[28\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[28] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[28\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[28] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 379 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393888380895 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[29\] a permanently disabled " "Pin GPIO_1\[29\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[29] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[29\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[29] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 380 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393888380895 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[30\] a permanently disabled " "Pin GPIO_1\[30\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[30] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[30\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[30] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 381 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393888380895 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[32\] a permanently disabled " "Pin GPIO_1\[32\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[32] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[32\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[32] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 382 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393888380895 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[31\] a permanently disabled " "Pin GPIO_0\[31\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[31] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[31\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[31] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 271 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393888380895 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[33\] a permanently enabled " "Pin GPIO_0\[33\] has a permanently enabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[33] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[33\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[33] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 268 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393888380895 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[0\] a permanently enabled " "Pin GPIO_1\[0\] has a permanently enabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[0] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[0\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 272 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393888380895 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[31\] a permanently disabled " "Pin GPIO_1\[31\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[31] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[31\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[31] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 270 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393888380895 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[33\] a permanently enabled " "Pin GPIO_1\[33\] has a permanently enabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[33] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[33\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[33] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 269 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393888380895 ""} } { } 0 169064 "Following %1!d! pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results" 0 0 "" 0 -1 1393888380895 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/output_files/de0_nano_system.fit.smsg " "Generated suppressed messages file C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/output_files/de0_nano_system.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "" 0 -1 1393888381466 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 36 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 36 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1135 " "Peak virtual memory: 1135 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1 1393888383399 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 03 16:13:03 2014 " "Processing ended: Mon Mar 03 16:13:03 2014" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1 1393888383399 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:42 " "Elapsed time: 00:00:42" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1 1393888383399 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:52 " "Total CPU time (on all processors): 00:00:52" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1 1393888383399 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1 1393888383399 ""} diff --git a/MCandWifiTestDE0/db/de0_nano_system.hier_info b/MCandWifiTestDE0/db/de0_nano_system.hier_info index 88c8b1d8..aedbaa5b 100644 --- a/MCandWifiTestDE0/db/de0_nano_system.hier_info +++ b/MCandWifiTestDE0/db/de0_nano_system.hier_info @@ -13587,38 +13587,34 @@ address => readdata[28].DATAIN address => readdata[25].DATAIN address => readdata[24].DATAIN address => readdata[20].DATAIN -address => readdata[17].DATAIN +address => readdata[18].DATAIN address => readdata[16].DATAIN -address => readdata[15].DATAIN -address => readdata[14].DATAIN -address => readdata[11].DATAIN address => readdata[10].DATAIN address => readdata[9].DATAIN -address => readdata[6].DATAIN address => readdata[5].DATAIN -address => readdata[1].DATAIN -address => readdata[0].DATAIN +address => readdata[3].DATAIN +address => readdata[2].DATAIN clock => ~NO_FANOUT~ reset_n => ~NO_FANOUT~ -readdata[0] <= address.DB_MAX_OUTPUT_PORT_TYPE -readdata[1] <= address.DB_MAX_OUTPUT_PORT_TYPE -readdata[2] <= -readdata[3] <= +readdata[0] <= +readdata[1] <= +readdata[2] <= address.DB_MAX_OUTPUT_PORT_TYPE +readdata[3] <= address.DB_MAX_OUTPUT_PORT_TYPE readdata[4] <= readdata[5] <= address.DB_MAX_OUTPUT_PORT_TYPE -readdata[6] <= address.DB_MAX_OUTPUT_PORT_TYPE +readdata[6] <= readdata[7] <= readdata[8] <= readdata[9] <= address.DB_MAX_OUTPUT_PORT_TYPE readdata[10] <= address.DB_MAX_OUTPUT_PORT_TYPE -readdata[11] <= address.DB_MAX_OUTPUT_PORT_TYPE +readdata[11] <= readdata[12] <= readdata[13] <= -readdata[14] <= address.DB_MAX_OUTPUT_PORT_TYPE -readdata[15] <= address.DB_MAX_OUTPUT_PORT_TYPE +readdata[14] <= +readdata[15] <= readdata[16] <= address.DB_MAX_OUTPUT_PORT_TYPE -readdata[17] <= address.DB_MAX_OUTPUT_PORT_TYPE -readdata[18] <= +readdata[17] <= +readdata[18] <= address.DB_MAX_OUTPUT_PORT_TYPE readdata[19] <= readdata[20] <= address.DB_MAX_OUTPUT_PORT_TYPE readdata[21] <= diff --git a/MCandWifiTestDE0/db/de0_nano_system.hif b/MCandWifiTestDE0/db/de0_nano_system.hif index 470df43f..20c7cc59 100644 Binary files a/MCandWifiTestDE0/db/de0_nano_system.hif and b/MCandWifiTestDE0/db/de0_nano_system.hif differ diff --git a/MCandWifiTestDE0/db/de0_nano_system.lpc.html b/MCandWifiTestDE0/db/de0_nano_system.lpc.html index 97bec1f8..e7e3f0c3 100644 --- a/MCandWifiTestDE0/db/de0_nano_system.lpc.html +++ b/MCandWifiTestDE0/db/de0_nano_system.lpc.html @@ -2818,13 +2818,13 @@ inst_cpu|sysid 3 -16 +20 2 -16 +20 32 -16 -16 -16 +20 +20 +20 0 0 0 diff --git a/MCandWifiTestDE0/db/de0_nano_system.lpc.rdb b/MCandWifiTestDE0/db/de0_nano_system.lpc.rdb index 8ec0114e..8ae353ab 100644 Binary files a/MCandWifiTestDE0/db/de0_nano_system.lpc.rdb and b/MCandWifiTestDE0/db/de0_nano_system.lpc.rdb differ diff --git a/MCandWifiTestDE0/db/de0_nano_system.lpc.txt b/MCandWifiTestDE0/db/de0_nano_system.lpc.txt index 29bd7a9e..55c64bea 100644 --- a/MCandWifiTestDE0/db/de0_nano_system.lpc.txt +++ b/MCandWifiTestDE0/db/de0_nano_system.lpc.txt @@ -178,7 +178,7 @@ ; inst_cpu|sys_clk_timer ; 23 ; 0 ; 0 ; 0 ; 17 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; ; inst_cpu|sdram|the_system_sdram_input_efifo_module ; 46 ; 0 ; 0 ; 0 ; 46 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; ; inst_cpu|sdram ; 46 ; 1 ; 1 ; 1 ; 40 ; 1 ; 1 ; 1 ; 16 ; 0 ; 0 ; 0 ; 0 ; -; inst_cpu|sysid ; 3 ; 16 ; 2 ; 16 ; 32 ; 16 ; 16 ; 16 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst_cpu|sysid ; 3 ; 20 ; 2 ; 20 ; 32 ; 20 ; 20 ; 20 ; 0 ; 0 ; 0 ; 0 ; 0 ; ; inst_cpu|cpu ; 151 ; 0 ; 26 ; 0 ; 125 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; ; inst_cpu ; 10 ; 1 ; 0 ; 1 ; 33 ; 1 ; 1 ; 1 ; 16 ; 0 ; 0 ; 0 ; 0 ; ; inst_heartbeat ; 1 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; diff --git a/MCandWifiTestDE0/db/de0_nano_system.map.bpm b/MCandWifiTestDE0/db/de0_nano_system.map.bpm index d8769d0b..26101cfc 100644 Binary files a/MCandWifiTestDE0/db/de0_nano_system.map.bpm and b/MCandWifiTestDE0/db/de0_nano_system.map.bpm differ diff --git a/MCandWifiTestDE0/db/de0_nano_system.map.cdb b/MCandWifiTestDE0/db/de0_nano_system.map.cdb index 2675703e..627562d9 100644 Binary files a/MCandWifiTestDE0/db/de0_nano_system.map.cdb and b/MCandWifiTestDE0/db/de0_nano_system.map.cdb differ diff --git a/MCandWifiTestDE0/db/de0_nano_system.map.hdb b/MCandWifiTestDE0/db/de0_nano_system.map.hdb index 2bdc14f7..9a7d96d3 100644 Binary files a/MCandWifiTestDE0/db/de0_nano_system.map.hdb and b/MCandWifiTestDE0/db/de0_nano_system.map.hdb differ diff --git a/MCandWifiTestDE0/db/de0_nano_system.map.kpt b/MCandWifiTestDE0/db/de0_nano_system.map.kpt index e1192707..fa6355a6 100644 Binary files a/MCandWifiTestDE0/db/de0_nano_system.map.kpt and b/MCandWifiTestDE0/db/de0_nano_system.map.kpt differ diff --git a/MCandWifiTestDE0/db/de0_nano_system.map.qmsg b/MCandWifiTestDE0/db/de0_nano_system.map.qmsg index 98ab02c9..857f85be 100644 --- a/MCandWifiTestDE0/db/de0_nano_system.map.qmsg +++ b/MCandWifiTestDE0/db/de0_nano_system.map.qmsg @@ -1,315 +1,315 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1 1393811624916 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Full Version " "Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1 1393811624916 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Mar 02 18:53:44 2014 " "Processing started: Sun Mar 02 18:53:44 2014" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1 1393811624916 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1 1393811624916 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off de0_nano_system -c de0_nano_system " "Command: quartus_map --read_settings_files=on --write_settings_files=off de0_nano_system -c de0_nano_system" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1 1393811624916 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." { } { } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "" 0 -1 1393811625316 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "de0_nano_system.vhd 2 1 " "Found 2 design units, including 1 entities, in source file de0_nano_system.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 de0_nano_system-syn " "Found design unit 1: de0_nano_system-syn" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 86 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1 1393811625766 ""} { "Info" "ISGN_ENTITY_NAME" "1 de0_nano_system " "Found entity 1: de0_nano_system" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 55 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811625766 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393811625766 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "heartbeat.vhd 2 1 " "Found 2 design units, including 1 entities, in source file heartbeat.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 heartbeat-syn " "Found design unit 1: heartbeat-syn" { } { { "heartbeat.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/heartbeat.vhd" 61 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1 1393811625776 ""} { "Info" "ISGN_ENTITY_NAME" "1 heartbeat " "Found entity 1: heartbeat" { } { { "heartbeat.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/heartbeat.vhd" 49 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811625776 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393811625776 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/system.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/system.v" { { "Info" "ISGN_ENTITY_NAME" "1 system " "Found entity 1: system" { } { { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 6 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811625786 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393811625786 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_irq_mapper.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_irq_mapper.sv" { { "Info" "ISGN_ENTITY_NAME" "1 system_irq_mapper " "Found entity 1: system_irq_mapper" { } { { "system/synthesis/submodules/system_irq_mapper.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_irq_mapper.sv" 31 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811625786 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393811625786 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_merlin_width_adapter.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_width_adapter.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_width_adapter " "Found entity 1: altera_merlin_width_adapter" { } { { "system/synthesis/submodules/altera_merlin_width_adapter.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_width_adapter.sv" 25 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811625796 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393811625796 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_merlin_burst_uncompressor.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_burst_uncompressor.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_burst_uncompressor " "Found entity 1: altera_merlin_burst_uncompressor" { } { { "system/synthesis/submodules/altera_merlin_burst_uncompressor.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_burst_uncompressor.sv" 40 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811625796 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393811625796 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_merlin_address_alignment.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_address_alignment.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_address_alignment " "Found entity 1: altera_merlin_address_alignment" { } { { "system/synthesis/submodules/altera_merlin_address_alignment.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_address_alignment.sv" 26 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811625796 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393811625796 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_merlin_arbitrator.sv 2 2 " "Found 2 design units, including 2 entities, in source file system/synthesis/submodules/altera_merlin_arbitrator.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_arbitrator " "Found entity 1: altera_merlin_arbitrator" { } { { "system/synthesis/submodules/altera_merlin_arbitrator.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_arbitrator.sv" 103 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811625806 ""} { "Info" "ISGN_ENTITY_NAME" "2 altera_merlin_arb_adder " "Found entity 2: altera_merlin_arb_adder" { } { { "system/synthesis/submodules/altera_merlin_arbitrator.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_arbitrator.sv" 228 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811625806 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393811625806 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_rsp_xbar_mux_001.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_rsp_xbar_mux_001.sv" { { "Info" "ISGN_ENTITY_NAME" "1 system_rsp_xbar_mux_001 " "Found entity 1: system_rsp_xbar_mux_001" { } { { "system/synthesis/submodules/system_rsp_xbar_mux_001.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_rsp_xbar_mux_001.sv" 38 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811625806 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393811625806 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_rsp_xbar_mux.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_rsp_xbar_mux.sv" { { "Info" "ISGN_ENTITY_NAME" "1 system_rsp_xbar_mux " "Found entity 1: system_rsp_xbar_mux" { } { { "system/synthesis/submodules/system_rsp_xbar_mux.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_rsp_xbar_mux.sv" 38 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811625806 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393811625806 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_rsp_xbar_demux_002.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_rsp_xbar_demux_002.sv" { { "Info" "ISGN_ENTITY_NAME" "1 system_rsp_xbar_demux_002 " "Found entity 1: system_rsp_xbar_demux_002" { } { { "system/synthesis/submodules/system_rsp_xbar_demux_002.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_rsp_xbar_demux_002.sv" 43 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811625806 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393811625806 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_rsp_xbar_demux.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_rsp_xbar_demux.sv" { { "Info" "ISGN_ENTITY_NAME" "1 system_rsp_xbar_demux " "Found entity 1: system_rsp_xbar_demux" { } { { "system/synthesis/submodules/system_rsp_xbar_demux.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_rsp_xbar_demux.sv" 43 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811625816 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393811625816 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_cmd_xbar_mux.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_cmd_xbar_mux.sv" { { "Info" "ISGN_ENTITY_NAME" "1 system_cmd_xbar_mux " "Found entity 1: system_cmd_xbar_mux" { } { { "system/synthesis/submodules/system_cmd_xbar_mux.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cmd_xbar_mux.sv" 38 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811625816 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393811625816 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_cmd_xbar_demux_001.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_cmd_xbar_demux_001.sv" { { "Info" "ISGN_ENTITY_NAME" "1 system_cmd_xbar_demux_001 " "Found entity 1: system_cmd_xbar_demux_001" { } { { "system/synthesis/submodules/system_cmd_xbar_demux_001.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cmd_xbar_demux_001.sv" 43 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811625816 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393811625816 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_cmd_xbar_demux.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_cmd_xbar_demux.sv" { { "Info" "ISGN_ENTITY_NAME" "1 system_cmd_xbar_demux " "Found entity 1: system_cmd_xbar_demux" { } { { "system/synthesis/submodules/system_cmd_xbar_demux.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cmd_xbar_demux.sv" 43 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811625816 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393811625816 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_reset_controller.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_reset_controller.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_reset_controller " "Found entity 1: altera_reset_controller" { } { { "system/synthesis/submodules/altera_reset_controller.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_reset_controller.v" 28 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811625826 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393811625826 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_reset_synchronizer.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_reset_synchronizer.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_reset_synchronizer " "Found entity 1: altera_reset_synchronizer" { } { { "system/synthesis/submodules/altera_reset_synchronizer.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_reset_synchronizer.v" 24 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811625826 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393811625826 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_merlin_burst_adapter.sv 7 7 " "Found 7 design units, including 7 entities, in source file system/synthesis/submodules/altera_merlin_burst_adapter.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_burst_adapter_burstwrap_increment " "Found entity 1: altera_merlin_burst_adapter_burstwrap_increment" { } { { "system/synthesis/submodules/altera_merlin_burst_adapter.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_burst_adapter.sv" 40 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811625826 ""} { "Info" "ISGN_ENTITY_NAME" "2 altera_merlin_burst_adapter_adder " "Found entity 2: altera_merlin_burst_adapter_adder" { } { { "system/synthesis/submodules/altera_merlin_burst_adapter.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_burst_adapter.sv" 55 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811625826 ""} { "Info" "ISGN_ENTITY_NAME" "3 altera_merlin_burst_adapter_subtractor " "Found entity 3: altera_merlin_burst_adapter_subtractor" { } { { "system/synthesis/submodules/altera_merlin_burst_adapter.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_burst_adapter.sv" 77 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811625826 ""} { "Info" "ISGN_ENTITY_NAME" "4 altera_merlin_burst_adapter_min " "Found entity 4: altera_merlin_burst_adapter_min" { } { { "system/synthesis/submodules/altera_merlin_burst_adapter.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_burst_adapter.sv" 98 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811625826 ""} { "Info" "ISGN_ENTITY_NAME" "5 altera_merlin_burst_adapter " "Found entity 5: altera_merlin_burst_adapter" { } { { "system/synthesis/submodules/altera_merlin_burst_adapter.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_burst_adapter.sv" 264 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811625826 ""} { "Info" "ISGN_ENTITY_NAME" "6 altera_merlin_burst_adapter_uncompressed_only " "Found entity 6: altera_merlin_burst_adapter_uncompressed_only" { } { { "system/synthesis/submodules/altera_merlin_burst_adapter.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_burst_adapter.sv" 414 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811625826 ""} { "Info" "ISGN_ENTITY_NAME" "7 altera_merlin_burst_adapter_full " "Found entity 7: altera_merlin_burst_adapter_full" { } { { "system/synthesis/submodules/altera_merlin_burst_adapter.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_burst_adapter.sv" 468 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811625826 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393811625826 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_merlin_traffic_limiter.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_traffic_limiter.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_traffic_limiter " "Found entity 1: altera_merlin_traffic_limiter" { } { { "system/synthesis/submodules/altera_merlin_traffic_limiter.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_traffic_limiter.sv" 44 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811625836 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393811625836 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_avalon_st_pipeline_base.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_avalon_st_pipeline_base.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_avalon_st_pipeline_base " "Found entity 1: altera_avalon_st_pipeline_base" { } { { "system/synthesis/submodules/altera_avalon_st_pipeline_base.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_avalon_st_pipeline_base.v" 22 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811625836 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393811625836 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_id_router_002.sv 2 2 " "Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_id_router_002.sv" { { "Info" "ISGN_ENTITY_NAME" "1 system_id_router_002_default_decode " "Found entity 1: system_id_router_002_default_decode" { } { { "system/synthesis/submodules/system_id_router_002.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_id_router_002.sv" 32 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811625836 ""} { "Info" "ISGN_ENTITY_NAME" "2 system_id_router_002 " "Found entity 2: system_id_router_002" { } { { "system/synthesis/submodules/system_id_router_002.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_id_router_002.sv" 54 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811625836 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393811625836 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_id_router_001.sv 2 2 " "Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_id_router_001.sv" { { "Info" "ISGN_ENTITY_NAME" "1 system_id_router_001_default_decode " "Found entity 1: system_id_router_001_default_decode" { } { { "system/synthesis/submodules/system_id_router_001.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_id_router_001.sv" 32 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811625836 ""} { "Info" "ISGN_ENTITY_NAME" "2 system_id_router_001 " "Found entity 2: system_id_router_001" { } { { "system/synthesis/submodules/system_id_router_001.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_id_router_001.sv" 54 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811625836 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393811625836 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_id_router.sv 2 2 " "Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_id_router.sv" { { "Info" "ISGN_ENTITY_NAME" "1 system_id_router_default_decode " "Found entity 1: system_id_router_default_decode" { } { { "system/synthesis/submodules/system_id_router.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_id_router.sv" 32 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811625846 ""} { "Info" "ISGN_ENTITY_NAME" "2 system_id_router " "Found entity 2: system_id_router" { } { { "system/synthesis/submodules/system_id_router.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_id_router.sv" 54 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811625846 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393811625846 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_addr_router_001.sv 2 2 " "Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_addr_router_001.sv" { { "Info" "ISGN_ENTITY_NAME" "1 system_addr_router_001_default_decode " "Found entity 1: system_addr_router_001_default_decode" { } { { "system/synthesis/submodules/system_addr_router_001.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_addr_router_001.sv" 32 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811625846 ""} { "Info" "ISGN_ENTITY_NAME" "2 system_addr_router_001 " "Found entity 2: system_addr_router_001" { } { { "system/synthesis/submodules/system_addr_router_001.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_addr_router_001.sv" 54 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811625846 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393811625846 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_addr_router.sv 2 2 " "Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_addr_router.sv" { { "Info" "ISGN_ENTITY_NAME" "1 system_addr_router_default_decode " "Found entity 1: system_addr_router_default_decode" { } { { "system/synthesis/submodules/system_addr_router.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_addr_router.sv" 32 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811625846 ""} { "Info" "ISGN_ENTITY_NAME" "2 system_addr_router " "Found entity 2: system_addr_router" { } { { "system/synthesis/submodules/system_addr_router.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_addr_router.sv" 54 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811625846 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393811625846 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_avalon_sc_fifo.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_avalon_sc_fifo.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_avalon_sc_fifo " "Found entity 1: altera_avalon_sc_fifo" { } { { "system/synthesis/submodules/altera_avalon_sc_fifo.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_avalon_sc_fifo.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811625856 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393811625856 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_merlin_slave_agent.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_slave_agent.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_slave_agent " "Found entity 1: altera_merlin_slave_agent" { } { { "system/synthesis/submodules/altera_merlin_slave_agent.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_slave_agent.sv" 34 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811625856 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393811625856 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_merlin_master_agent.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_master_agent.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_master_agent " "Found entity 1: altera_merlin_master_agent" { } { { "system/synthesis/submodules/altera_merlin_master_agent.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_master_agent.sv" 28 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811625856 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393811625856 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_merlin_slave_translator.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_slave_translator.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_slave_translator " "Found entity 1: altera_merlin_slave_translator" { } { { "system/synthesis/submodules/altera_merlin_slave_translator.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_slave_translator.sv" 35 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811625866 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393811625866 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_merlin_master_translator.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_master_translator.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_master_translator " "Found entity 1: altera_merlin_master_translator" { } { { "system/synthesis/submodules/altera_merlin_master_translator.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_master_translator.sv" 30 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811625866 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393811625866 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_up_rs232_counters.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_up_rs232_counters.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_up_rs232_counters " "Found entity 1: altera_up_rs232_counters" { } { { "system/synthesis/submodules/altera_up_rs232_counters.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_up_rs232_counters.v" 48 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811625866 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393811625866 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_up_rs232_in_deserializer.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_up_rs232_in_deserializer.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_up_rs232_in_deserializer " "Found entity 1: altera_up_rs232_in_deserializer" { } { { "system/synthesis/submodules/altera_up_rs232_in_deserializer.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_up_rs232_in_deserializer.v" 47 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811625866 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393811625866 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_up_rs232_out_serializer.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_up_rs232_out_serializer.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_up_rs232_out_serializer " "Found entity 1: altera_up_rs232_out_serializer" { } { { "system/synthesis/submodules/altera_up_rs232_out_serializer.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_up_rs232_out_serializer.v" 47 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811625876 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393811625876 ""} -{ "Warning" "WVRFX_L2_VERI_INGORE_DANGLING_COMMA" "altera_up_sync_fifo.v(157) " "Verilog HDL Module Instantiation warning at altera_up_sync_fifo.v(157): ignored dangling comma in List of Port Connections" { } { { "system/synthesis/submodules/altera_up_sync_fifo.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_up_sync_fifo.v" 157 0 0 } } } 0 10275 "Verilog HDL Module Instantiation warning at %1!s!: ignored dangling comma in List of Port Connections" 0 0 "" 0 -1 1393811625876 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_up_sync_fifo.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_up_sync_fifo.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_up_sync_fifo " "Found entity 1: altera_up_sync_fifo" { } { { "system/synthesis/submodules/altera_up_sync_fifo.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_up_sync_fifo.v" 47 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811625876 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393811625876 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_rs232_wifi.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_rs232_wifi.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_rs232_wifi " "Found entity 1: system_rs232_wifi" { } { { "system/synthesis/submodules/system_rs232_wifi.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_rs232_wifi.v" 48 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811625876 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393811625876 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_uart_mc.v 7 7 " "Found 7 design units, including 7 entities, in source file system/synthesis/submodules/system_uart_mc.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_uart_mc_log_module " "Found entity 1: system_uart_mc_log_module" { } { { "system/synthesis/submodules/system_uart_mc.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_mc.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811625886 ""} { "Info" "ISGN_ENTITY_NAME" "2 system_uart_mc_tx " "Found entity 2: system_uart_mc_tx" { } { { "system/synthesis/submodules/system_uart_mc.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_mc.v" 66 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811625886 ""} { "Info" "ISGN_ENTITY_NAME" "3 system_uart_mc_rx_stimulus_source_character_source_rom_module " "Found entity 3: system_uart_mc_rx_stimulus_source_character_source_rom_module" { } { { "system/synthesis/submodules/system_uart_mc.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_mc.v" 238 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811625886 ""} { "Info" "ISGN_ENTITY_NAME" "4 system_uart_mc_rx_stimulus_source " "Found entity 4: system_uart_mc_rx_stimulus_source" { } { { "system/synthesis/submodules/system_uart_mc.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_mc.v" 387 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811625886 ""} { "Info" "ISGN_ENTITY_NAME" "5 system_uart_mc_rx " "Found entity 5: system_uart_mc_rx" { } { { "system/synthesis/submodules/system_uart_mc.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_mc.v" 492 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811625886 ""} { "Info" "ISGN_ENTITY_NAME" "6 system_uart_mc_regs " "Found entity 6: system_uart_mc_regs" { } { { "system/synthesis/submodules/system_uart_mc.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_mc.v" 750 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811625886 ""} { "Info" "ISGN_ENTITY_NAME" "7 system_uart_mc " "Found entity 7: system_uart_mc" { } { { "system/synthesis/submodules/system_uart_mc.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_mc.v" 995 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811625886 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393811625886 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_pio_ir_emitter.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_pio_ir_emitter.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_pio_ir_emitter " "Found entity 1: system_pio_ir_emitter" { } { { "system/synthesis/submodules/system_pio_ir_emitter.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_pio_ir_emitter.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811625886 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393811625886 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_jtag_uart_0.v 7 7 " "Found 7 design units, including 7 entities, in source file system/synthesis/submodules/system_jtag_uart_0.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_jtag_uart_0_log_module " "Found entity 1: system_jtag_uart_0_log_module" { } { { "system/synthesis/submodules/system_jtag_uart_0.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_jtag_uart_0.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811625886 ""} { "Info" "ISGN_ENTITY_NAME" "2 system_jtag_uart_0_sim_scfifo_w " "Found entity 2: system_jtag_uart_0_sim_scfifo_w" { } { { "system/synthesis/submodules/system_jtag_uart_0.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_jtag_uart_0.v" 65 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811625886 ""} { "Info" "ISGN_ENTITY_NAME" "3 system_jtag_uart_0_scfifo_w " "Found entity 3: system_jtag_uart_0_scfifo_w" { } { { "system/synthesis/submodules/system_jtag_uart_0.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_jtag_uart_0.v" 123 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811625886 ""} { "Info" "ISGN_ENTITY_NAME" "4 system_jtag_uart_0_drom_module " "Found entity 4: system_jtag_uart_0_drom_module" { } { { "system/synthesis/submodules/system_jtag_uart_0.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_jtag_uart_0.v" 208 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811625886 ""} { "Info" "ISGN_ENTITY_NAME" "5 system_jtag_uart_0_sim_scfifo_r " "Found entity 5: system_jtag_uart_0_sim_scfifo_r" { } { { "system/synthesis/submodules/system_jtag_uart_0.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_jtag_uart_0.v" 362 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811625886 ""} { "Info" "ISGN_ENTITY_NAME" "6 system_jtag_uart_0_scfifo_r " "Found entity 6: system_jtag_uart_0_scfifo_r" { } { { "system/synthesis/submodules/system_jtag_uart_0.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_jtag_uart_0.v" 450 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811625886 ""} { "Info" "ISGN_ENTITY_NAME" "7 system_jtag_uart_0 " "Found entity 7: system_jtag_uart_0" { } { { "system/synthesis/submodules/system_jtag_uart_0.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_jtag_uart_0.v" 537 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811625886 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393811625886 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_pio_sw.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_pio_sw.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_pio_sw " "Found entity 1: system_pio_sw" { } { { "system/synthesis/submodules/system_pio_sw.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_pio_sw.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811625896 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393811625896 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_pio_key_left.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_pio_key_left.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_pio_key_left " "Found entity 1: system_pio_key_left" { } { { "system/synthesis/submodules/system_pio_key_left.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_pio_key_left.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811625896 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393811625896 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_pio_led.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_pio_led.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_pio_led " "Found entity 1: system_pio_led" { } { { "system/synthesis/submodules/system_pio_led.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_pio_led.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811625896 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393811625896 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_uart_wifi.v 7 7 " "Found 7 design units, including 7 entities, in source file system/synthesis/submodules/system_uart_wifi.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_uart_wifi_log_module " "Found entity 1: system_uart_wifi_log_module" { } { { "system/synthesis/submodules/system_uart_wifi.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_wifi.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811625906 ""} { "Info" "ISGN_ENTITY_NAME" "2 system_uart_wifi_tx " "Found entity 2: system_uart_wifi_tx" { } { { "system/synthesis/submodules/system_uart_wifi.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_wifi.v" 66 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811625906 ""} { "Info" "ISGN_ENTITY_NAME" "3 system_uart_wifi_rx_stimulus_source_character_source_rom_module " "Found entity 3: system_uart_wifi_rx_stimulus_source_character_source_rom_module" { } { { "system/synthesis/submodules/system_uart_wifi.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_wifi.v" 238 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811625906 ""} { "Info" "ISGN_ENTITY_NAME" "4 system_uart_wifi_rx_stimulus_source " "Found entity 4: system_uart_wifi_rx_stimulus_source" { } { { "system/synthesis/submodules/system_uart_wifi.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_wifi.v" 387 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811625906 ""} { "Info" "ISGN_ENTITY_NAME" "5 system_uart_wifi_rx " "Found entity 5: system_uart_wifi_rx" { } { { "system/synthesis/submodules/system_uart_wifi.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_wifi.v" 492 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811625906 ""} { "Info" "ISGN_ENTITY_NAME" "6 system_uart_wifi_regs " "Found entity 6: system_uart_wifi_regs" { } { { "system/synthesis/submodules/system_uart_wifi.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_wifi.v" 750 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811625906 ""} { "Info" "ISGN_ENTITY_NAME" "7 system_uart_wifi " "Found entity 7: system_uart_wifi" { } { { "system/synthesis/submodules/system_uart_wifi.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_wifi.v" 1006 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811625906 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393811625906 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_sys_clk_timer.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_sys_clk_timer.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_sys_clk_timer " "Found entity 1: system_sys_clk_timer" { } { { "system/synthesis/submodules/system_sys_clk_timer.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_sys_clk_timer.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811625906 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393811625906 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_sdram.v 2 2 " "Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_sdram.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_sdram_input_efifo_module " "Found entity 1: system_sdram_input_efifo_module" { } { { "system/synthesis/submodules/system_sdram.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_sdram.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811625906 ""} { "Info" "ISGN_ENTITY_NAME" "2 system_sdram " "Found entity 2: system_sdram" { } { { "system/synthesis/submodules/system_sdram.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_sdram.v" 158 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811625906 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393811625906 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_sysid.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_sysid.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_sysid " "Found entity 1: system_sysid" { } { { "system/synthesis/submodules/system_sysid.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_sysid.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811625906 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393811625906 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_cpu.v 28 28 " "Found 28 design units, including 28 entities, in source file system/synthesis/submodules/system_cpu.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_cpu_ic_data_module " "Found entity 1: system_cpu_ic_data_module" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811627336 ""} { "Info" "ISGN_ENTITY_NAME" "2 system_cpu_ic_tag_module " "Found entity 2: system_cpu_ic_tag_module" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 86 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811627336 ""} { "Info" "ISGN_ENTITY_NAME" "3 system_cpu_bht_module " "Found entity 3: system_cpu_bht_module" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 152 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811627336 ""} { "Info" "ISGN_ENTITY_NAME" "4 system_cpu_register_bank_a_module " "Found entity 4: system_cpu_register_bank_a_module" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 218 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811627336 ""} { "Info" "ISGN_ENTITY_NAME" "5 system_cpu_register_bank_b_module " "Found entity 5: system_cpu_register_bank_b_module" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 281 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811627336 ""} { "Info" "ISGN_ENTITY_NAME" "6 system_cpu_dc_tag_module " "Found entity 6: system_cpu_dc_tag_module" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 344 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811627336 ""} { "Info" "ISGN_ENTITY_NAME" "7 system_cpu_dc_data_module " "Found entity 7: system_cpu_dc_data_module" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 407 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811627336 ""} { "Info" "ISGN_ENTITY_NAME" "8 system_cpu_dc_victim_module " "Found entity 8: system_cpu_dc_victim_module" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 473 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811627336 ""} { "Info" "ISGN_ENTITY_NAME" "9 system_cpu_nios2_oci_debug " "Found entity 9: system_cpu_nios2_oci_debug" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 538 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811627336 ""} { "Info" "ISGN_ENTITY_NAME" "10 system_cpu_ociram_lpm_dram_bdp_component_module " "Found entity 10: system_cpu_ociram_lpm_dram_bdp_component_module" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 666 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811627336 ""} { "Info" "ISGN_ENTITY_NAME" "11 system_cpu_nios2_ocimem " "Found entity 11: system_cpu_nios2_ocimem" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 759 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811627336 ""} { "Info" "ISGN_ENTITY_NAME" "12 system_cpu_nios2_avalon_reg " "Found entity 12: system_cpu_nios2_avalon_reg" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 905 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811627336 ""} { "Info" "ISGN_ENTITY_NAME" "13 system_cpu_nios2_oci_break " "Found entity 13: system_cpu_nios2_oci_break" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 999 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811627336 ""} { "Info" "ISGN_ENTITY_NAME" "14 system_cpu_nios2_oci_xbrk " "Found entity 14: system_cpu_nios2_oci_xbrk" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 1293 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811627336 ""} { "Info" "ISGN_ENTITY_NAME" "15 system_cpu_nios2_oci_dbrk " "Found entity 15: system_cpu_nios2_oci_dbrk" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 1553 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811627336 ""} { "Info" "ISGN_ENTITY_NAME" "16 system_cpu_nios2_oci_itrace " "Found entity 16: system_cpu_nios2_oci_itrace" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 1741 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811627336 ""} { "Info" "ISGN_ENTITY_NAME" "17 system_cpu_nios2_oci_td_mode " "Found entity 17: system_cpu_nios2_oci_td_mode" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 2098 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811627336 ""} { "Info" "ISGN_ENTITY_NAME" "18 system_cpu_nios2_oci_dtrace " "Found entity 18: system_cpu_nios2_oci_dtrace" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 2165 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811627336 ""} { "Info" "ISGN_ENTITY_NAME" "19 system_cpu_nios2_oci_compute_tm_count " "Found entity 19: system_cpu_nios2_oci_compute_tm_count" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 2259 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811627336 ""} { "Info" "ISGN_ENTITY_NAME" "20 system_cpu_nios2_oci_fifowp_inc " "Found entity 20: system_cpu_nios2_oci_fifowp_inc" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 2330 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811627336 ""} { "Info" "ISGN_ENTITY_NAME" "21 system_cpu_nios2_oci_fifocount_inc " "Found entity 21: system_cpu_nios2_oci_fifocount_inc" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 2372 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811627336 ""} { "Info" "ISGN_ENTITY_NAME" "22 system_cpu_nios2_oci_fifo " "Found entity 22: system_cpu_nios2_oci_fifo" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 2418 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811627336 ""} { "Info" "ISGN_ENTITY_NAME" "23 system_cpu_nios2_oci_pib " "Found entity 23: system_cpu_nios2_oci_pib" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 2923 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811627336 ""} { "Info" "ISGN_ENTITY_NAME" "24 system_cpu_traceram_lpm_dram_bdp_component_module " "Found entity 24: system_cpu_traceram_lpm_dram_bdp_component_module" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 2991 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811627336 ""} { "Info" "ISGN_ENTITY_NAME" "25 system_cpu_nios2_oci_im " "Found entity 25: system_cpu_nios2_oci_im" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3080 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811627336 ""} { "Info" "ISGN_ENTITY_NAME" "26 system_cpu_nios2_performance_monitors " "Found entity 26: system_cpu_nios2_performance_monitors" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3217 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811627336 ""} { "Info" "ISGN_ENTITY_NAME" "27 system_cpu_nios2_oci " "Found entity 27: system_cpu_nios2_oci" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3233 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811627336 ""} { "Info" "ISGN_ENTITY_NAME" "28 system_cpu " "Found entity 28: system_cpu" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3736 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811627336 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393811627336 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_cpu_jtag_debug_module_sysclk.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_cpu_jtag_debug_module_sysclk.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_cpu_jtag_debug_module_sysclk " "Found entity 1: system_cpu_jtag_debug_module_sysclk" { } { { "system/synthesis/submodules/system_cpu_jtag_debug_module_sysclk.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu_jtag_debug_module_sysclk.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811627336 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393811627336 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_cpu_jtag_debug_module_tck.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_cpu_jtag_debug_module_tck.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_cpu_jtag_debug_module_tck " "Found entity 1: system_cpu_jtag_debug_module_tck" { } { { "system/synthesis/submodules/system_cpu_jtag_debug_module_tck.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu_jtag_debug_module_tck.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811627336 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393811627336 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_cpu_jtag_debug_module_wrapper " "Found entity 1: system_cpu_jtag_debug_module_wrapper" { } { { "system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811627346 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393811627346 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_cpu_mult_cell.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_cpu_mult_cell.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_cpu_mult_cell " "Found entity 1: system_cpu_mult_cell" { } { { "system/synthesis/submodules/system_cpu_mult_cell.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu_mult_cell.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811627346 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393811627346 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_cpu_oci_test_bench.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_cpu_oci_test_bench.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_cpu_oci_test_bench " "Found entity 1: system_cpu_oci_test_bench" { } { { "system/synthesis/submodules/system_cpu_oci_test_bench.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu_oci_test_bench.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811627346 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393811627346 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_cpu_test_bench.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_cpu_test_bench.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_cpu_test_bench " "Found entity 1: system_cpu_test_bench" { } { { "system/synthesis/submodules/system_cpu_test_bench.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu_test_bench.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811627356 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393811627356 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pll_sys.vhd 2 1 " "Found 2 design units, including 1 entities, in source file pll_sys.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 pll_sys-SYN " "Found design unit 1: pll_sys-SYN" { } { { "pll_sys.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/pll_sys.vhd" 54 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1 1393811627356 ""} { "Info" "ISGN_ENTITY_NAME" "1 pll_sys " "Found entity 1: pll_sys" { } { { "pll_sys.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/pll_sys.vhd" 42 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811627356 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393811627356 ""} -{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "system_cpu.v(2066) " "Verilog HDL or VHDL warning at system_cpu.v(2066): conditional expression evaluates to a constant" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 2066 0 0 } } } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1 1393811627376 ""} -{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "system_cpu.v(2068) " "Verilog HDL or VHDL warning at system_cpu.v(2068): conditional expression evaluates to a constant" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 2068 0 0 } } } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1 1393811627376 ""} -{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "system_cpu.v(2224) " "Verilog HDL or VHDL warning at system_cpu.v(2224): conditional expression evaluates to a constant" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 2224 0 0 } } } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1 1393811627376 ""} -{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "system_cpu.v(3143) " "Verilog HDL or VHDL warning at system_cpu.v(3143): conditional expression evaluates to a constant" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3143 0 0 } } } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1 1393811627386 ""} -{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "system_sdram.v(316) " "Verilog HDL or VHDL warning at system_sdram.v(316): conditional expression evaluates to a constant" { } { { "system/synthesis/submodules/system_sdram.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_sdram.v" 316 0 0 } } } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1 1393811627386 ""} -{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "system_sdram.v(326) " "Verilog HDL or VHDL warning at system_sdram.v(326): conditional expression evaluates to a constant" { } { { "system/synthesis/submodules/system_sdram.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_sdram.v" 326 0 0 } } } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1 1393811627386 ""} -{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "system_sdram.v(336) " "Verilog HDL or VHDL warning at system_sdram.v(336): conditional expression evaluates to a constant" { } { { "system/synthesis/submodules/system_sdram.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_sdram.v" 336 0 0 } } } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1 1393811627386 ""} -{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "system_sdram.v(680) " "Verilog HDL or VHDL warning at system_sdram.v(680): conditional expression evaluates to a constant" { } { { "system/synthesis/submodules/system_sdram.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_sdram.v" 680 0 0 } } } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1 1393811627396 ""} -{ "Info" "ISGN_START_ELABORATION_TOP" "de0_nano_system " "Elaborating entity \"de0_nano_system\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1 1393811627546 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pll_sys pll_sys:inst_pll_sys " "Elaborating entity \"pll_sys\" for hierarchy \"pll_sys:inst_pll_sys\"" { } { { "de0_nano_system.vhd" "inst_pll_sys" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 152 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811627546 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll pll_sys:inst_pll_sys\|altpll:altpll_component " "Elaborating entity \"altpll\" for hierarchy \"pll_sys:inst_pll_sys\|altpll:altpll_component\"" { } { { "pll_sys.vhd" "altpll_component" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/pll_sys.vhd" 154 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811627606 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "pll_sys:inst_pll_sys\|altpll:altpll_component " "Elaborated megafunction instantiation \"pll_sys:inst_pll_sys\|altpll:altpll_component\"" { } { { "pll_sys.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/pll_sys.vhd" 154 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1393811627606 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "pll_sys:inst_pll_sys\|altpll:altpll_component " "Instantiated megafunction \"pll_sys:inst_pll_sys\|altpll:altpll_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "bandwidth_type AUTO " "Parameter \"bandwidth_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811627606 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_divide_by 1 " "Parameter \"clk0_divide_by\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811627606 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_duty_cycle 50 " "Parameter \"clk0_duty_cycle\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811627606 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_multiply_by 2 " "Parameter \"clk0_multiply_by\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811627606 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_phase_shift 0 " "Parameter \"clk0_phase_shift\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811627606 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_divide_by 1 " "Parameter \"clk1_divide_by\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811627606 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_duty_cycle 50 " "Parameter \"clk1_duty_cycle\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811627606 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_multiply_by 2 " "Parameter \"clk1_multiply_by\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811627606 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_phase_shift -1500 " "Parameter \"clk1_phase_shift\" = \"-1500\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811627606 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_divide_by 5 " "Parameter \"clk2_divide_by\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811627606 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_duty_cycle 50 " "Parameter \"clk2_duty_cycle\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811627606 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_multiply_by 1 " "Parameter \"clk2_multiply_by\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811627606 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_phase_shift 0 " "Parameter \"clk2_phase_shift\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811627606 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "compensate_clock CLK0 " "Parameter \"compensate_clock\" = \"CLK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811627606 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "inclk0_input_frequency 20000 " "Parameter \"inclk0_input_frequency\" = \"20000\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811627606 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811627606 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint CBX_MODULE_PREFIX=pll_sys " "Parameter \"lpm_hint\" = \"CBX_MODULE_PREFIX=pll_sys\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811627606 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altpll " "Parameter \"lpm_type\" = \"altpll\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811627606 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode NORMAL " "Parameter \"operation_mode\" = \"NORMAL\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811627606 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_type AUTO " "Parameter \"pll_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811627606 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_activeclock PORT_UNUSED " "Parameter \"port_activeclock\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811627606 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_areset PORT_UNUSED " "Parameter \"port_areset\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811627606 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad0 PORT_UNUSED " "Parameter \"port_clkbad0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811627606 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad1 PORT_UNUSED " "Parameter \"port_clkbad1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811627606 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkloss PORT_UNUSED " "Parameter \"port_clkloss\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811627606 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkswitch PORT_UNUSED " "Parameter \"port_clkswitch\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811627606 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_configupdate PORT_UNUSED " "Parameter \"port_configupdate\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811627606 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_fbin PORT_UNUSED " "Parameter \"port_fbin\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811627606 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk0 PORT_USED " "Parameter \"port_inclk0\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811627606 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk1 PORT_UNUSED " "Parameter \"port_inclk1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811627606 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_locked PORT_USED " "Parameter \"port_locked\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811627606 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pfdena PORT_UNUSED " "Parameter \"port_pfdena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811627606 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasecounterselect PORT_UNUSED " "Parameter \"port_phasecounterselect\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811627606 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasedone PORT_UNUSED " "Parameter \"port_phasedone\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811627606 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasestep PORT_UNUSED " "Parameter \"port_phasestep\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811627606 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phaseupdown PORT_UNUSED " "Parameter \"port_phaseupdown\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811627606 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pllena PORT_UNUSED " "Parameter \"port_pllena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811627606 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanaclr PORT_UNUSED " "Parameter \"port_scanaclr\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811627606 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclk PORT_UNUSED " "Parameter \"port_scanclk\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811627606 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclkena PORT_UNUSED " "Parameter \"port_scanclkena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811627606 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandata PORT_UNUSED " "Parameter \"port_scandata\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811627606 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandataout PORT_UNUSED " "Parameter \"port_scandataout\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811627606 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandone PORT_UNUSED " "Parameter \"port_scandone\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811627606 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanread PORT_UNUSED " "Parameter \"port_scanread\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811627606 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanwrite PORT_UNUSED " "Parameter \"port_scanwrite\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811627606 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk0 PORT_USED " "Parameter \"port_clk0\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811627606 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk1 PORT_USED " "Parameter \"port_clk1\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811627606 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk2 PORT_USED " "Parameter \"port_clk2\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811627606 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk3 PORT_UNUSED " "Parameter \"port_clk3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811627606 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk4 PORT_UNUSED " "Parameter \"port_clk4\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811627606 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk5 PORT_UNUSED " "Parameter \"port_clk5\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811627606 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena0 PORT_UNUSED " "Parameter \"port_clkena0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811627606 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena1 PORT_UNUSED " "Parameter \"port_clkena1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811627606 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena2 PORT_UNUSED " "Parameter \"port_clkena2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811627606 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena3 PORT_UNUSED " "Parameter \"port_clkena3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811627606 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena4 PORT_UNUSED " "Parameter \"port_clkena4\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811627606 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena5 PORT_UNUSED " "Parameter \"port_clkena5\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811627606 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk0 PORT_UNUSED " "Parameter \"port_extclk0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811627606 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk1 PORT_UNUSED " "Parameter \"port_extclk1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811627606 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk2 PORT_UNUSED " "Parameter \"port_extclk2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811627606 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk3 PORT_UNUSED " "Parameter \"port_extclk3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811627606 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "self_reset_on_loss_lock ON " "Parameter \"self_reset_on_loss_lock\" = \"ON\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811627606 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_clock 5 " "Parameter \"width_clock\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811627606 ""} } { { "pll_sys.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/pll_sys.vhd" 154 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1393811627606 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/pll_sys_altpll.v 1 1 " "Found 1 design units, including 1 entities, in source file db/pll_sys_altpll.v" { { "Info" "ISGN_ENTITY_NAME" "1 pll_sys_altpll " "Found entity 1: pll_sys_altpll" { } { { "db/pll_sys_altpll.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/pll_sys_altpll.v" 29 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811627676 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393811627676 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pll_sys_altpll pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated " "Elaborating entity \"pll_sys_altpll\" for hierarchy \"pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\"" { } { { "altpll.tdf" "auto_generated" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altpll.tdf" 897 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811627676 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "heartbeat heartbeat:inst_heartbeat " "Elaborating entity \"heartbeat\" for hierarchy \"heartbeat:inst_heartbeat\"" { } { { "de0_nano_system.vhd" "inst_heartbeat" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 161 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811627676 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system system:inst_cpu " "Elaborating entity \"system\" for hierarchy \"system:inst_cpu\"" { } { { "de0_nano_system.vhd" "inst_cpu" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811627686 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu system:inst_cpu\|system_cpu:cpu " "Elaborating entity \"system_cpu\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\"" { } { { "system/synthesis/system.v" "cpu" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811627736 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_test_bench system:inst_cpu\|system_cpu:cpu\|system_cpu_test_bench:the_system_cpu_test_bench " "Elaborating entity \"system_cpu_test_bench\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_test_bench:the_system_cpu_test_bench\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_test_bench" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 6073 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811627766 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_ic_data_module system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_data_module:system_cpu_ic_data " "Elaborating entity \"system_cpu_ic_data_module\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_data_module:system_cpu_ic_data\"" { } { { "system/synthesis/submodules/system_cpu.v" "system_cpu_ic_data" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 7098 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811627776 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_data_module:system_cpu_ic_data\|altsyncram:the_altsyncram " "Elaborating entity \"altsyncram\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_data_module:system_cpu_ic_data\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_altsyncram" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 58 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811627806 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_data_module:system_cpu_ic_data\|altsyncram:the_altsyncram " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_data_module:system_cpu_ic_data\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 58 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1393811627806 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_data_module:system_cpu_ic_data\|altsyncram:the_altsyncram " "Instantiated megafunction \"system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_data_module:system_cpu_ic_data\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811627806 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 0 " "Parameter \"maximum_depth\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811627806 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 2048 " "Parameter \"numwords_a\" = \"2048\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811627806 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 2048 " "Parameter \"numwords_b\" = \"2048\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811627806 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Parameter \"operation_mode\" = \"DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811627806 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811627806 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811627806 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rdcontrol_reg_b CLOCK0 " "Parameter \"rdcontrol_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811627806 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811627806 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 32 " "Parameter \"width_a\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811627806 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 32 " "Parameter \"width_b\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811627806 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 11 " "Parameter \"widthad_a\" = \"11\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811627806 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 11 " "Parameter \"widthad_b\" = \"11\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811627806 ""} } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 58 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1393811627806 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_sjd1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_sjd1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_sjd1 " "Found entity 1: altsyncram_sjd1" { } { { "db/altsyncram_sjd1.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_sjd1.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811627886 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393811627886 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_sjd1 system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_data_module:system_cpu_ic_data\|altsyncram:the_altsyncram\|altsyncram_sjd1:auto_generated " "Elaborating entity \"altsyncram_sjd1\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_data_module:system_cpu_ic_data\|altsyncram:the_altsyncram\|altsyncram_sjd1:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811627886 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_ic_tag_module system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_tag_module:system_cpu_ic_tag " "Elaborating entity \"system_cpu_ic_tag_module\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_tag_module:system_cpu_ic_tag\"" { } { { "system/synthesis/submodules/system_cpu.v" "system_cpu_ic_tag" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 7164 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811627886 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_tag_module:system_cpu_ic_tag\|altsyncram:the_altsyncram " "Elaborating entity \"altsyncram\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_tag_module:system_cpu_ic_tag\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_altsyncram" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 123 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811627906 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_tag_module:system_cpu_ic_tag\|altsyncram:the_altsyncram " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_tag_module:system_cpu_ic_tag\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 123 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1393811627906 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_tag_module:system_cpu_ic_tag\|altsyncram:the_altsyncram " "Instantiated megafunction \"system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_tag_module:system_cpu_ic_tag\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811627906 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file system_cpu_ic_tag_ram.mif " "Parameter \"init_file\" = \"system_cpu_ic_tag_ram.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811627906 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 0 " "Parameter \"maximum_depth\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811627906 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 256 " "Parameter \"numwords_a\" = \"256\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811627906 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 256 " "Parameter \"numwords_b\" = \"256\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811627906 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Parameter \"operation_mode\" = \"DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811627906 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811627906 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811627906 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rdcontrol_reg_b CLOCK0 " "Parameter \"rdcontrol_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811627906 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports OLD_DATA " "Parameter \"read_during_write_mode_mixed_ports\" = \"OLD_DATA\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811627906 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 21 " "Parameter \"width_a\" = \"21\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811627906 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 21 " "Parameter \"width_b\" = \"21\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811627906 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 8 " "Parameter \"widthad_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811627906 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 8 " "Parameter \"widthad_b\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811627906 ""} } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 123 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1393811627906 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_qtg1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_qtg1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_qtg1 " "Found entity 1: altsyncram_qtg1" { } { { "db/altsyncram_qtg1.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_qtg1.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811627976 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393811627976 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_qtg1 system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_tag_module:system_cpu_ic_tag\|altsyncram:the_altsyncram\|altsyncram_qtg1:auto_generated " "Elaborating entity \"altsyncram_qtg1\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_tag_module:system_cpu_ic_tag\|altsyncram:the_altsyncram\|altsyncram_qtg1:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811627976 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_bht_module system:inst_cpu\|system_cpu:cpu\|system_cpu_bht_module:system_cpu_bht " "Elaborating entity \"system_cpu_bht_module\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_bht_module:system_cpu_bht\"" { } { { "system/synthesis/submodules/system_cpu.v" "system_cpu_bht" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 7368 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811628006 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram system:inst_cpu\|system_cpu:cpu\|system_cpu_bht_module:system_cpu_bht\|altsyncram:the_altsyncram " "Elaborating entity \"altsyncram\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_bht_module:system_cpu_bht\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_altsyncram" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 189 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811628006 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_cpu:cpu\|system_cpu_bht_module:system_cpu_bht\|altsyncram:the_altsyncram " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_bht_module:system_cpu_bht\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 189 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1393811628016 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_cpu:cpu\|system_cpu_bht_module:system_cpu_bht\|altsyncram:the_altsyncram " "Instantiated megafunction \"system:inst_cpu\|system_cpu:cpu\|system_cpu_bht_module:system_cpu_bht\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628016 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file system_cpu_bht_ram.mif " "Parameter \"init_file\" = \"system_cpu_bht_ram.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628016 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 0 " "Parameter \"maximum_depth\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628016 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 256 " "Parameter \"numwords_a\" = \"256\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628016 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 256 " "Parameter \"numwords_b\" = \"256\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628016 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Parameter \"operation_mode\" = \"DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628016 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628016 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628016 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rdcontrol_reg_b CLOCK0 " "Parameter \"rdcontrol_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628016 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports OLD_DATA " "Parameter \"read_during_write_mode_mixed_ports\" = \"OLD_DATA\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628016 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 2 " "Parameter \"width_a\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628016 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 2 " "Parameter \"width_b\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628016 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 8 " "Parameter \"widthad_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628016 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 8 " "Parameter \"widthad_b\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628016 ""} } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 189 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1393811628016 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_fhg1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_fhg1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_fhg1 " "Found entity 1: altsyncram_fhg1" { } { { "db/altsyncram_fhg1.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_fhg1.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811628066 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393811628066 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_fhg1 system:inst_cpu\|system_cpu:cpu\|system_cpu_bht_module:system_cpu_bht\|altsyncram:the_altsyncram\|altsyncram_fhg1:auto_generated " "Elaborating entity \"altsyncram_fhg1\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_bht_module:system_cpu_bht\|altsyncram:the_altsyncram\|altsyncram_fhg1:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811628066 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_register_bank_a_module system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_a_module:system_cpu_register_bank_a " "Elaborating entity \"system_cpu_register_bank_a_module\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_a_module:system_cpu_register_bank_a\"" { } { { "system/synthesis/submodules/system_cpu.v" "system_cpu_register_bank_a" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 7514 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811628076 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_a_module:system_cpu_register_bank_a\|altsyncram:the_altsyncram " "Elaborating entity \"altsyncram\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_a_module:system_cpu_register_bank_a\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_altsyncram" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 252 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811628086 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_a_module:system_cpu_register_bank_a\|altsyncram:the_altsyncram " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_a_module:system_cpu_register_bank_a\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 252 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1393811628086 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_a_module:system_cpu_register_bank_a\|altsyncram:the_altsyncram " "Instantiated megafunction \"system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_a_module:system_cpu_register_bank_a\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628086 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file system_cpu_rf_ram_a.mif " "Parameter \"init_file\" = \"system_cpu_rf_ram_a.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628086 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 0 " "Parameter \"maximum_depth\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628086 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 32 " "Parameter \"numwords_a\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628086 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 32 " "Parameter \"numwords_b\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628086 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Parameter \"operation_mode\" = \"DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628086 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628086 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628086 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rdcontrol_reg_b CLOCK0 " "Parameter \"rdcontrol_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628086 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports OLD_DATA " "Parameter \"read_during_write_mode_mixed_ports\" = \"OLD_DATA\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628086 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 32 " "Parameter \"width_a\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628086 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 32 " "Parameter \"width_b\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628086 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 5 " "Parameter \"widthad_a\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628086 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 5 " "Parameter \"widthad_b\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628086 ""} } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 252 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1393811628086 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_fvf1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_fvf1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_fvf1 " "Found entity 1: altsyncram_fvf1" { } { { "db/altsyncram_fvf1.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_fvf1.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811628166 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393811628166 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_fvf1 system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_a_module:system_cpu_register_bank_a\|altsyncram:the_altsyncram\|altsyncram_fvf1:auto_generated " "Elaborating entity \"altsyncram_fvf1\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_a_module:system_cpu_register_bank_a\|altsyncram:the_altsyncram\|altsyncram_fvf1:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811628166 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_register_bank_b_module system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_b_module:system_cpu_register_bank_b " "Elaborating entity \"system_cpu_register_bank_b_module\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_b_module:system_cpu_register_bank_b\"" { } { { "system/synthesis/submodules/system_cpu.v" "system_cpu_register_bank_b" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 7535 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811628196 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_b_module:system_cpu_register_bank_b\|altsyncram:the_altsyncram " "Elaborating entity \"altsyncram\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_b_module:system_cpu_register_bank_b\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_altsyncram" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 315 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811628206 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_b_module:system_cpu_register_bank_b\|altsyncram:the_altsyncram " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_b_module:system_cpu_register_bank_b\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 315 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1393811628206 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_b_module:system_cpu_register_bank_b\|altsyncram:the_altsyncram " "Instantiated megafunction \"system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_b_module:system_cpu_register_bank_b\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628206 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file system_cpu_rf_ram_b.mif " "Parameter \"init_file\" = \"system_cpu_rf_ram_b.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628206 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 0 " "Parameter \"maximum_depth\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628206 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 32 " "Parameter \"numwords_a\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628206 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 32 " "Parameter \"numwords_b\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628206 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Parameter \"operation_mode\" = \"DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628206 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628206 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628206 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rdcontrol_reg_b CLOCK0 " "Parameter \"rdcontrol_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628206 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports OLD_DATA " "Parameter \"read_during_write_mode_mixed_ports\" = \"OLD_DATA\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628206 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 32 " "Parameter \"width_a\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628206 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 32 " "Parameter \"width_b\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628206 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 5 " "Parameter \"widthad_a\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628206 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 5 " "Parameter \"widthad_b\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628206 ""} } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 315 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1393811628206 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_gvf1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_gvf1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_gvf1 " "Found entity 1: altsyncram_gvf1" { } { { "db/altsyncram_gvf1.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_gvf1.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811628286 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393811628286 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_gvf1 system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_b_module:system_cpu_register_bank_b\|altsyncram:the_altsyncram\|altsyncram_gvf1:auto_generated " "Elaborating entity \"altsyncram_gvf1\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_b_module:system_cpu_register_bank_b\|altsyncram:the_altsyncram\|altsyncram_gvf1:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811628296 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_dc_tag_module system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_tag_module:system_cpu_dc_tag " "Elaborating entity \"system_cpu_dc_tag_module\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_tag_module:system_cpu_dc_tag\"" { } { { "system/synthesis/submodules/system_cpu.v" "system_cpu_dc_tag" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 7968 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811628326 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_tag_module:system_cpu_dc_tag\|altsyncram:the_altsyncram " "Elaborating entity \"altsyncram\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_tag_module:system_cpu_dc_tag\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_altsyncram" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 378 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811628326 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_tag_module:system_cpu_dc_tag\|altsyncram:the_altsyncram " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_tag_module:system_cpu_dc_tag\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 378 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1393811628326 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_tag_module:system_cpu_dc_tag\|altsyncram:the_altsyncram " "Instantiated megafunction \"system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_tag_module:system_cpu_dc_tag\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628336 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file system_cpu_dc_tag_ram.mif " "Parameter \"init_file\" = \"system_cpu_dc_tag_ram.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628336 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 0 " "Parameter \"maximum_depth\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628336 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 128 " "Parameter \"numwords_a\" = \"128\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628336 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 128 " "Parameter \"numwords_b\" = \"128\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628336 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Parameter \"operation_mode\" = \"DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628336 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628336 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628336 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rdcontrol_reg_b CLOCK0 " "Parameter \"rdcontrol_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628336 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports OLD_DATA " "Parameter \"read_during_write_mode_mixed_ports\" = \"OLD_DATA\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628336 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 16 " "Parameter \"width_a\" = \"16\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628336 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 16 " "Parameter \"width_b\" = \"16\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628336 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 7 " "Parameter \"widthad_a\" = \"7\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628336 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 7 " "Parameter \"widthad_b\" = \"7\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628336 ""} } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 378 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1393811628336 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_d9g1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_d9g1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_d9g1 " "Found entity 1: altsyncram_d9g1" { } { { "db/altsyncram_d9g1.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_d9g1.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811628396 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393811628396 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_d9g1 system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_tag_module:system_cpu_dc_tag\|altsyncram:the_altsyncram\|altsyncram_d9g1:auto_generated " "Elaborating entity \"altsyncram_d9g1\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_tag_module:system_cpu_dc_tag\|altsyncram:the_altsyncram\|altsyncram_d9g1:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811628396 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_dc_data_module system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_data_module:system_cpu_dc_data " "Elaborating entity \"system_cpu_dc_data_module\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_data_module:system_cpu_dc_data\"" { } { { "system/synthesis/submodules/system_cpu.v" "system_cpu_dc_data" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 8022 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811628416 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_data_module:system_cpu_dc_data\|altsyncram:the_altsyncram " "Elaborating entity \"altsyncram\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_data_module:system_cpu_dc_data\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_altsyncram" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 444 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811628426 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_data_module:system_cpu_dc_data\|altsyncram:the_altsyncram " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_data_module:system_cpu_dc_data\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 444 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1393811628426 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_data_module:system_cpu_dc_data\|altsyncram:the_altsyncram " "Instantiated megafunction \"system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_data_module:system_cpu_dc_data\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628426 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 0 " "Parameter \"maximum_depth\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628426 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 1024 " "Parameter \"numwords_a\" = \"1024\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628426 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 1024 " "Parameter \"numwords_b\" = \"1024\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628426 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Parameter \"operation_mode\" = \"DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628426 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628426 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628426 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rdcontrol_reg_b CLOCK0 " "Parameter \"rdcontrol_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628426 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628426 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 32 " "Parameter \"width_a\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628426 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 32 " "Parameter \"width_b\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628426 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 4 " "Parameter \"width_byteena_a\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628426 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 10 " "Parameter \"widthad_a\" = \"10\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628426 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 10 " "Parameter \"widthad_b\" = \"10\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628426 ""} } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 444 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1393811628426 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_2jf1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_2jf1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_2jf1 " "Found entity 1: altsyncram_2jf1" { } { { "db/altsyncram_2jf1.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_2jf1.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811628506 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393811628506 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_2jf1 system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_data_module:system_cpu_dc_data\|altsyncram:the_altsyncram\|altsyncram_2jf1:auto_generated " "Elaborating entity \"altsyncram_2jf1\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_data_module:system_cpu_dc_data\|altsyncram:the_altsyncram\|altsyncram_2jf1:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811628506 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_dc_victim_module system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_victim_module:system_cpu_dc_victim " "Elaborating entity \"system_cpu_dc_victim_module\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_victim_module:system_cpu_dc_victim\"" { } { { "system/synthesis/submodules/system_cpu.v" "system_cpu_dc_victim" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 8038 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811628516 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_victim_module:system_cpu_dc_victim\|altsyncram:the_altsyncram " "Elaborating entity \"altsyncram\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_victim_module:system_cpu_dc_victim\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_altsyncram" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 510 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811628516 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_victim_module:system_cpu_dc_victim\|altsyncram:the_altsyncram " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_victim_module:system_cpu_dc_victim\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 510 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1393811628526 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_victim_module:system_cpu_dc_victim\|altsyncram:the_altsyncram " "Instantiated megafunction \"system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_victim_module:system_cpu_dc_victim\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628526 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 0 " "Parameter \"maximum_depth\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628526 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 8 " "Parameter \"numwords_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628526 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 8 " "Parameter \"numwords_b\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628526 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Parameter \"operation_mode\" = \"DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628526 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628526 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628526 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rdcontrol_reg_b CLOCK0 " "Parameter \"rdcontrol_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628526 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports OLD_DATA " "Parameter \"read_during_write_mode_mixed_ports\" = \"OLD_DATA\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628526 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 32 " "Parameter \"width_a\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628526 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 32 " "Parameter \"width_b\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628526 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 3 " "Parameter \"widthad_a\" = \"3\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628526 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 3 " "Parameter \"widthad_b\" = \"3\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628526 ""} } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 510 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1393811628526 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_r3d1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_r3d1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_r3d1 " "Found entity 1: altsyncram_r3d1" { } { { "db/altsyncram_r3d1.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_r3d1.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811628596 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393811628596 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_r3d1 system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_victim_module:system_cpu_dc_victim\|altsyncram:the_altsyncram\|altsyncram_r3d1:auto_generated " "Elaborating entity \"altsyncram_r3d1\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_victim_module:system_cpu_dc_victim\|altsyncram:the_altsyncram\|altsyncram_r3d1:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811628596 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_mult_cell system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell " "Elaborating entity \"system_cpu_mult_cell\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_mult_cell" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 9915 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811628606 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altmult_add system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_1 " "Elaborating entity \"altmult_add\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_1\"" { } { { "system/synthesis/submodules/system_cpu_mult_cell.v" "the_altmult_add_part_1" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu_mult_cell.v" 52 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811628656 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_1 " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_1\"" { } { { "system/synthesis/submodules/system_cpu_mult_cell.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu_mult_cell.v" 52 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1393811628656 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_1 " "Instantiated megafunction \"system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_1\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "addnsub_multiplier_pipeline_aclr1 ACLR0 " "Parameter \"addnsub_multiplier_pipeline_aclr1\" = \"ACLR0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628656 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "addnsub_multiplier_pipeline_register1 CLOCK0 " "Parameter \"addnsub_multiplier_pipeline_register1\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628656 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "addnsub_multiplier_register1 UNREGISTERED " "Parameter \"addnsub_multiplier_register1\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628656 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "dedicated_multiplier_circuitry YES " "Parameter \"dedicated_multiplier_circuitry\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628656 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "input_register_a0 UNREGISTERED " "Parameter \"input_register_a0\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628656 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "input_register_b0 UNREGISTERED " "Parameter \"input_register_b0\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628656 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "input_source_a0 DATAA " "Parameter \"input_source_a0\" = \"DATAA\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628656 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "input_source_b0 DATAB " "Parameter \"input_source_b0\" = \"DATAB\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628656 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family CYCLONEIVE " "Parameter \"intended_device_family\" = \"CYCLONEIVE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628656 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altmult_add " "Parameter \"lpm_type\" = \"altmult_add\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628656 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "multiplier1_direction ADD " "Parameter \"multiplier1_direction\" = \"ADD\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628656 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "multiplier_aclr0 ACLR0 " "Parameter \"multiplier_aclr0\" = \"ACLR0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628656 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "multiplier_register0 CLOCK0 " "Parameter \"multiplier_register0\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628656 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "number_of_multipliers 1 " "Parameter \"number_of_multipliers\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628656 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_register UNREGISTERED " "Parameter \"output_register\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628656 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_addnsub1 PORT_UNUSED " "Parameter \"port_addnsub1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628656 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_addnsub3 PORT_UNUSED " "Parameter \"port_addnsub3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628656 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_signa PORT_UNUSED " "Parameter \"port_signa\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628656 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_signb PORT_UNUSED " "Parameter \"port_signb\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628656 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "representation_a UNSIGNED " "Parameter \"representation_a\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628656 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "representation_b UNSIGNED " "Parameter \"representation_b\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628656 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_pipeline_aclr_a ACLR0 " "Parameter \"signed_pipeline_aclr_a\" = \"ACLR0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628656 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_pipeline_aclr_b ACLR0 " "Parameter \"signed_pipeline_aclr_b\" = \"ACLR0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628656 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_pipeline_register_a CLOCK0 " "Parameter \"signed_pipeline_register_a\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628656 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_pipeline_register_b CLOCK0 " "Parameter \"signed_pipeline_register_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628656 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_register_a UNREGISTERED " "Parameter \"signed_register_a\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628656 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_register_b UNREGISTERED " "Parameter \"signed_register_b\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628656 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 16 " "Parameter \"width_a\" = \"16\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628656 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 16 " "Parameter \"width_b\" = \"16\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628656 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_result 32 " "Parameter \"width_result\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628656 ""} } { { "system/synthesis/submodules/system_cpu_mult_cell.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu_mult_cell.v" 52 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1393811628656 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mult_add_75u2.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mult_add_75u2.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mult_add_75u2 " "Found entity 1: mult_add_75u2" { } { { "db/mult_add_75u2.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/mult_add_75u2.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811628716 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393811628716 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mult_add_75u2 system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_1\|mult_add_75u2:auto_generated " "Elaborating entity \"mult_add_75u2\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_1\|mult_add_75u2:auto_generated\"" { } { { "altmult_add.tdf" "auto_generated" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altmult_add.tdf" 594 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811628716 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ded_mult_ks81.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/ded_mult_ks81.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 ded_mult_ks81 " "Found entity 1: ded_mult_ks81" { } { { "db/ded_mult_ks81.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/ded_mult_ks81.tdf" 30 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811628726 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393811628726 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ded_mult_ks81 system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_1\|mult_add_75u2:auto_generated\|ded_mult_ks81:ded_mult1 " "Elaborating entity \"ded_mult_ks81\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_1\|mult_add_75u2:auto_generated\|ded_mult_ks81:ded_mult1\"" { } { { "db/mult_add_75u2.tdf" "ded_mult1" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/mult_add_75u2.tdf" 33 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811628736 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/dffpipe_93c.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/dffpipe_93c.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 dffpipe_93c " "Found entity 1: dffpipe_93c" { } { { "db/dffpipe_93c.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/dffpipe_93c.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811628736 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393811628736 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dffpipe_93c system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_1\|mult_add_75u2:auto_generated\|ded_mult_ks81:ded_mult1\|dffpipe_93c:pre_result " "Elaborating entity \"dffpipe_93c\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_1\|mult_add_75u2:auto_generated\|ded_mult_ks81:ded_mult1\|dffpipe_93c:pre_result\"" { } { { "db/ded_mult_ks81.tdf" "pre_result" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/ded_mult_ks81.tdf" 50 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811628746 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altmult_add system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_2 " "Elaborating entity \"altmult_add\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_2\"" { } { { "system/synthesis/submodules/system_cpu_mult_cell.v" "the_altmult_add_part_2" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu_mult_cell.v" 93 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811628776 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_2 " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_2\"" { } { { "system/synthesis/submodules/system_cpu_mult_cell.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu_mult_cell.v" 93 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1393811628776 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_2 " "Instantiated megafunction \"system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_2\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "addnsub_multiplier_pipeline_aclr1 ACLR0 " "Parameter \"addnsub_multiplier_pipeline_aclr1\" = \"ACLR0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628786 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "addnsub_multiplier_pipeline_register1 CLOCK0 " "Parameter \"addnsub_multiplier_pipeline_register1\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628786 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "addnsub_multiplier_register1 UNREGISTERED " "Parameter \"addnsub_multiplier_register1\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628786 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "dedicated_multiplier_circuitry YES " "Parameter \"dedicated_multiplier_circuitry\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628786 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "input_register_a0 UNREGISTERED " "Parameter \"input_register_a0\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628786 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "input_register_b0 UNREGISTERED " "Parameter \"input_register_b0\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628786 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "input_source_a0 DATAA " "Parameter \"input_source_a0\" = \"DATAA\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628786 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "input_source_b0 DATAB " "Parameter \"input_source_b0\" = \"DATAB\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628786 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family CYCLONEIVE " "Parameter \"intended_device_family\" = \"CYCLONEIVE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628786 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altmult_add " "Parameter \"lpm_type\" = \"altmult_add\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628786 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "multiplier1_direction ADD " "Parameter \"multiplier1_direction\" = \"ADD\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628786 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "multiplier_aclr0 ACLR0 " "Parameter \"multiplier_aclr0\" = \"ACLR0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628786 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "multiplier_register0 CLOCK0 " "Parameter \"multiplier_register0\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628786 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "number_of_multipliers 1 " "Parameter \"number_of_multipliers\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628786 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_register UNREGISTERED " "Parameter \"output_register\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628786 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_addnsub1 PORT_UNUSED " "Parameter \"port_addnsub1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628786 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_addnsub3 PORT_UNUSED " "Parameter \"port_addnsub3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628786 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_signa PORT_UNUSED " "Parameter \"port_signa\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628786 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_signb PORT_UNUSED " "Parameter \"port_signb\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628786 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "representation_a UNSIGNED " "Parameter \"representation_a\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628786 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "representation_b UNSIGNED " "Parameter \"representation_b\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628786 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_pipeline_aclr_a ACLR0 " "Parameter \"signed_pipeline_aclr_a\" = \"ACLR0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628786 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_pipeline_aclr_b ACLR0 " "Parameter \"signed_pipeline_aclr_b\" = \"ACLR0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628786 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_pipeline_register_a CLOCK0 " "Parameter \"signed_pipeline_register_a\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628786 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_pipeline_register_b CLOCK0 " "Parameter \"signed_pipeline_register_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628786 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_register_a UNREGISTERED " "Parameter \"signed_register_a\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628786 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_register_b UNREGISTERED " "Parameter \"signed_register_b\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628786 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 16 " "Parameter \"width_a\" = \"16\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628786 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 16 " "Parameter \"width_b\" = \"16\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628786 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_result 16 " "Parameter \"width_result\" = \"16\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628786 ""} } { { "system/synthesis/submodules/system_cpu_mult_cell.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu_mult_cell.v" 93 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1393811628786 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mult_add_95u2.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mult_add_95u2.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mult_add_95u2 " "Found entity 1: mult_add_95u2" { } { { "db/mult_add_95u2.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/mult_add_95u2.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811628836 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393811628836 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mult_add_95u2 system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_2\|mult_add_95u2:auto_generated " "Elaborating entity \"mult_add_95u2\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_2\|mult_add_95u2:auto_generated\"" { } { { "altmult_add.tdf" "auto_generated" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altmult_add.tdf" 594 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811628846 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_oci system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci " "Elaborating entity \"system_cpu_nios2_oci\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_nios2_oci" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811628846 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_oci_debug system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_debug:the_system_cpu_nios2_oci_debug " "Elaborating entity \"system_cpu_nios2_oci_debug\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_debug:the_system_cpu_nios2_oci_debug\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_nios2_oci_debug" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3444 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811628856 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_ocimem system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem " "Elaborating entity \"system_cpu_nios2_ocimem\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_nios2_ocimem" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3464 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811628856 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_ociram_lpm_dram_bdp_component_module system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem\|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component " "Elaborating entity \"system_cpu_ociram_lpm_dram_bdp_component_module\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem\|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component\"" { } { { "system/synthesis/submodules/system_cpu.v" "system_cpu_ociram_lpm_dram_bdp_component" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 872 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811628856 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem\|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component\|altsyncram:the_altsyncram " "Elaborating entity \"altsyncram\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem\|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_altsyncram" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 720 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811628866 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem\|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component\|altsyncram:the_altsyncram " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem\|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 720 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1393811628866 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem\|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component\|altsyncram:the_altsyncram " "Instantiated megafunction \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem\|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_a NONE " "Parameter \"address_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628866 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_b NONE " "Parameter \"address_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628866 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK1 " "Parameter \"address_reg_b\" = \"CLOCK1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628866 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_aclr_a NONE " "Parameter \"indata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628866 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_aclr_b NONE " "Parameter \"indata_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628866 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file system_cpu_ociram_default_contents.mif " "Parameter \"init_file\" = \"system_cpu_ociram_default_contents.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628866 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family CYCLONEIVE " "Parameter \"intended_device_family\" = \"CYCLONEIVE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628866 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628866 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 256 " "Parameter \"numwords_a\" = \"256\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628866 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 256 " "Parameter \"numwords_b\" = \"256\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628866 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode BIDIR_DUAL_PORT " "Parameter \"operation_mode\" = \"BIDIR_DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628866 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628866 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_b NONE " "Parameter \"outdata_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628866 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a UNREGISTERED " "Parameter \"outdata_reg_a\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628866 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628866 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628866 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports OLD_DATA " "Parameter \"read_during_write_mode_mixed_ports\" = \"OLD_DATA\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628866 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 32 " "Parameter \"width_a\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628866 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 32 " "Parameter \"width_b\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628866 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 4 " "Parameter \"width_byteena_a\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628866 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 8 " "Parameter \"widthad_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628866 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 8 " "Parameter \"widthad_b\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628866 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_aclr_a NONE " "Parameter \"wrcontrol_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628866 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_aclr_b NONE " "Parameter \"wrcontrol_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811628866 ""} } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 720 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1393811628866 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_jt72.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_jt72.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_jt72 " "Found entity 1: altsyncram_jt72" { } { { "db/altsyncram_jt72.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_jt72.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811628966 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393811628966 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_jt72 system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem\|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_jt72:auto_generated " "Elaborating entity \"altsyncram_jt72\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem\|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_jt72:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811628966 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_avalon_reg system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg " "Elaborating entity \"system_cpu_nios2_avalon_reg\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_nios2_avalon_reg" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3484 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811628996 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_oci_break system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_break:the_system_cpu_nios2_oci_break " "Elaborating entity \"system_cpu_nios2_oci_break\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_break:the_system_cpu_nios2_oci_break\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_nios2_oci_break" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3515 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811628996 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_oci_xbrk system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_xbrk:the_system_cpu_nios2_oci_xbrk " "Elaborating entity \"system_cpu_nios2_oci_xbrk\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_xbrk:the_system_cpu_nios2_oci_xbrk\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_nios2_oci_xbrk" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3538 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811628996 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_oci_dbrk system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_dbrk:the_system_cpu_nios2_oci_dbrk " "Elaborating entity \"system_cpu_nios2_oci_dbrk\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_dbrk:the_system_cpu_nios2_oci_dbrk\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_nios2_oci_dbrk" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3565 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811629006 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_oci_itrace system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_itrace:the_system_cpu_nios2_oci_itrace " "Elaborating entity \"system_cpu_nios2_oci_itrace\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_itrace:the_system_cpu_nios2_oci_itrace\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_nios2_oci_itrace" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3606 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811629006 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_oci_dtrace system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_dtrace:the_system_cpu_nios2_oci_dtrace " "Elaborating entity \"system_cpu_nios2_oci_dtrace\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_dtrace:the_system_cpu_nios2_oci_dtrace\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_nios2_oci_dtrace" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3621 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811629006 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_oci_td_mode system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_dtrace:the_system_cpu_nios2_oci_dtrace\|system_cpu_nios2_oci_td_mode:system_cpu_nios2_oci_trc_ctrl_td_mode " "Elaborating entity \"system_cpu_nios2_oci_td_mode\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_dtrace:the_system_cpu_nios2_oci_dtrace\|system_cpu_nios2_oci_td_mode:system_cpu_nios2_oci_trc_ctrl_td_mode\"" { } { { "system/synthesis/submodules/system_cpu.v" "system_cpu_nios2_oci_trc_ctrl_td_mode" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 2213 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811629006 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_oci_fifo system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_fifo:the_system_cpu_nios2_oci_fifo " "Elaborating entity \"system_cpu_nios2_oci_fifo\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_fifo:the_system_cpu_nios2_oci_fifo\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_nios2_oci_fifo" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3640 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811629006 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_oci_compute_tm_count system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_fifo:the_system_cpu_nios2_oci_fifo\|system_cpu_nios2_oci_compute_tm_count:system_cpu_nios2_oci_compute_tm_count_tm_count " "Elaborating entity \"system_cpu_nios2_oci_compute_tm_count\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_fifo:the_system_cpu_nios2_oci_fifo\|system_cpu_nios2_oci_compute_tm_count:system_cpu_nios2_oci_compute_tm_count_tm_count\"" { } { { "system/synthesis/submodules/system_cpu.v" "system_cpu_nios2_oci_compute_tm_count_tm_count" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 2545 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811629016 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_oci_fifowp_inc system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_fifo:the_system_cpu_nios2_oci_fifo\|system_cpu_nios2_oci_fifowp_inc:system_cpu_nios2_oci_fifowp_inc_fifowp " "Elaborating entity \"system_cpu_nios2_oci_fifowp_inc\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_fifo:the_system_cpu_nios2_oci_fifo\|system_cpu_nios2_oci_fifowp_inc:system_cpu_nios2_oci_fifowp_inc_fifowp\"" { } { { "system/synthesis/submodules/system_cpu.v" "system_cpu_nios2_oci_fifowp_inc_fifowp" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 2555 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811629016 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_oci_fifocount_inc system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_fifo:the_system_cpu_nios2_oci_fifo\|system_cpu_nios2_oci_fifocount_inc:system_cpu_nios2_oci_fifocount_inc_fifocount " "Elaborating entity \"system_cpu_nios2_oci_fifocount_inc\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_fifo:the_system_cpu_nios2_oci_fifo\|system_cpu_nios2_oci_fifocount_inc:system_cpu_nios2_oci_fifocount_inc_fifocount\"" { } { { "system/synthesis/submodules/system_cpu.v" "system_cpu_nios2_oci_fifocount_inc_fifocount" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 2565 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811629016 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_oci_test_bench system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_fifo:the_system_cpu_nios2_oci_fifo\|system_cpu_oci_test_bench:the_system_cpu_oci_test_bench " "Elaborating entity \"system_cpu_oci_test_bench\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_fifo:the_system_cpu_nios2_oci_fifo\|system_cpu_oci_test_bench:the_system_cpu_oci_test_bench\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_oci_test_bench" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 2574 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811629016 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_oci_pib system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_pib:the_system_cpu_nios2_oci_pib " "Elaborating entity \"system_cpu_nios2_oci_pib\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_pib:the_system_cpu_nios2_oci_pib\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_nios2_oci_pib" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3650 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811629016 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_oci_im system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im " "Elaborating entity \"system_cpu_nios2_oci_im\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_nios2_oci_im" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811629026 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_traceram_lpm_dram_bdp_component_module system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component " "Elaborating entity \"system_cpu_traceram_lpm_dram_bdp_component_module\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\"" { } { { "system/synthesis/submodules/system_cpu.v" "system_cpu_traceram_lpm_dram_bdp_component" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811629026 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram " "Elaborating entity \"altsyncram\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_altsyncram" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811629036 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1393811629036 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram " "Instantiated megafunction \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_a NONE " "Parameter \"address_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811629036 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_b NONE " "Parameter \"address_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811629036 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK1 " "Parameter \"address_reg_b\" = \"CLOCK1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811629036 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_aclr_a NONE " "Parameter \"indata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811629036 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_aclr_b NONE " "Parameter \"indata_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811629036 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file UNUSED " "Parameter \"init_file\" = \"UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811629036 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family CYCLONEIVE " "Parameter \"intended_device_family\" = \"CYCLONEIVE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811629036 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811629036 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 128 " "Parameter \"numwords_a\" = \"128\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811629036 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 128 " "Parameter \"numwords_b\" = \"128\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811629036 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode BIDIR_DUAL_PORT " "Parameter \"operation_mode\" = \"BIDIR_DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811629036 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811629036 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_b NONE " "Parameter \"outdata_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811629036 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a UNREGISTERED " "Parameter \"outdata_reg_a\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811629036 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811629036 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811629036 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports OLD_DATA " "Parameter \"read_during_write_mode_mixed_ports\" = \"OLD_DATA\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811629036 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 36 " "Parameter \"width_a\" = \"36\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811629036 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 36 " "Parameter \"width_b\" = \"36\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811629036 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 7 " "Parameter \"widthad_a\" = \"7\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811629036 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 7 " "Parameter \"widthad_b\" = \"7\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811629036 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_aclr_a NONE " "Parameter \"wrcontrol_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811629036 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_aclr_b NONE " "Parameter \"wrcontrol_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811629036 ""} } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1393811629036 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_0a02.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_0a02.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_0a02 " "Found entity 1: altsyncram_0a02" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811629126 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393811629126 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_0a02 system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated " "Elaborating entity \"altsyncram_0a02\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811629126 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_jtag_debug_module_wrapper system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper " "Elaborating entity \"system_cpu_jtag_debug_module_wrapper\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_jtag_debug_module_wrapper" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3714 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811629136 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_jtag_debug_module_tck system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck " "Elaborating entity \"system_cpu_jtag_debug_module_tck\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck\"" { } { { "system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v" "the_system_cpu_jtag_debug_module_tck" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v" 165 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811629136 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_std_synchronizer system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck\|altera_std_synchronizer:the_altera_std_synchronizer " "Elaborating entity \"altera_std_synchronizer\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck\|altera_std_synchronizer:the_altera_std_synchronizer\"" { } { { "system/synthesis/submodules/system_cpu_jtag_debug_module_tck.v" "the_altera_std_synchronizer" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu_jtag_debug_module_tck.v" 202 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811629156 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck\|altera_std_synchronizer:the_altera_std_synchronizer " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck\|altera_std_synchronizer:the_altera_std_synchronizer\"" { } { { "system/synthesis/submodules/system_cpu_jtag_debug_module_tck.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu_jtag_debug_module_tck.v" 202 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1393811629156 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck\|altera_std_synchronizer:the_altera_std_synchronizer " "Instantiated megafunction \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck\|altera_std_synchronizer:the_altera_std_synchronizer\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "depth 2 " "Parameter \"depth\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811629156 ""} } { { "system/synthesis/submodules/system_cpu_jtag_debug_module_tck.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu_jtag_debug_module_tck.v" 202 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1393811629156 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_jtag_debug_module_sysclk system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk " "Elaborating entity \"system_cpu_jtag_debug_module_sysclk\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk\"" { } { { "system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v" "the_system_cpu_jtag_debug_module_sysclk" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v" 188 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811629156 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sld_virtual_jtag_basic system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy " "Elaborating entity \"sld_virtual_jtag_basic\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy\"" { } { { "system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v" "system_cpu_jtag_debug_module_phy" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v" 218 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811629176 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy\"" { } { { "system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v" 218 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1393811629176 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy " "Instantiated megafunction \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_auto_instance_index YES " "Parameter \"sld_auto_instance_index\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811629176 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_instance_index 0 " "Parameter \"sld_instance_index\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811629176 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_ir_width 2 " "Parameter \"sld_ir_width\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811629176 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_mfg_id 70 " "Parameter \"sld_mfg_id\" = \"70\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811629176 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_sim_action " "Parameter \"sld_sim_action\" = \"\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811629176 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_sim_n_scan 0 " "Parameter \"sld_sim_n_scan\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811629176 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_sim_total_length 0 " "Parameter \"sld_sim_total_length\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811629176 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_type_id 34 " "Parameter \"sld_type_id\" = \"34\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811629176 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_version 3 " "Parameter \"sld_version\" = \"3\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811629176 ""} } { { "system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v" 218 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1393811629176 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sld_virtual_jtag_impl system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy\|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst " "Elaborating entity \"sld_virtual_jtag_impl\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy\|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst\"" { } { { "sld_virtual_jtag_basic.v" "sld_virtual_jtag_impl_inst" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/sld_virtual_jtag_basic.v" 151 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811629176 ""} -{ "Info" "ISGN_MEGAFN_DESCENDANT" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy\|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy\|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst\", which is child of megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy\"" { } { { "sld_virtual_jtag_basic.v" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/sld_virtual_jtag_basic.v" 151 0 0 } } { "system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v" 218 0 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0 -1 1393811629186 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_sysid system:inst_cpu\|system_sysid:sysid " "Elaborating entity \"system_sysid\" for hierarchy \"system:inst_cpu\|system_sysid:sysid\"" { } { { "system/synthesis/system.v" "sysid" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 856 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811629186 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_sdram system:inst_cpu\|system_sdram:sdram " "Elaborating entity \"system_sdram\" for hierarchy \"system:inst_cpu\|system_sdram:sdram\"" { } { { "system/synthesis/system.v" "sdram" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 879 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811629186 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_sdram_input_efifo_module system:inst_cpu\|system_sdram:sdram\|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module " "Elaborating entity \"system_sdram_input_efifo_module\" for hierarchy \"system:inst_cpu\|system_sdram:sdram\|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module\"" { } { { "system/synthesis/submodules/system_sdram.v" "the_system_sdram_input_efifo_module" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_sdram.v" 296 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811629196 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_sys_clk_timer system:inst_cpu\|system_sys_clk_timer:sys_clk_timer " "Elaborating entity \"system_sys_clk_timer\" for hierarchy \"system:inst_cpu\|system_sys_clk_timer:sys_clk_timer\"" { } { { "system/synthesis/system.v" "sys_clk_timer" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 890 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811629196 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_uart_wifi system:inst_cpu\|system_uart_wifi:uart_wifi " "Elaborating entity \"system_uart_wifi\" for hierarchy \"system:inst_cpu\|system_uart_wifi:uart_wifi\"" { } { { "system/synthesis/system.v" "uart_wifi" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 907 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811629196 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_uart_wifi_tx system:inst_cpu\|system_uart_wifi:uart_wifi\|system_uart_wifi_tx:the_system_uart_wifi_tx " "Elaborating entity \"system_uart_wifi_tx\" for hierarchy \"system:inst_cpu\|system_uart_wifi:uart_wifi\|system_uart_wifi_tx:the_system_uart_wifi_tx\"" { } { { "system/synthesis/submodules/system_uart_wifi.v" "the_system_uart_wifi_tx" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_wifi.v" 1079 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811629196 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_uart_wifi_rx system:inst_cpu\|system_uart_wifi:uart_wifi\|system_uart_wifi_rx:the_system_uart_wifi_rx " "Elaborating entity \"system_uart_wifi_rx\" for hierarchy \"system:inst_cpu\|system_uart_wifi:uart_wifi\|system_uart_wifi_rx:the_system_uart_wifi_rx\"" { } { { "system/synthesis/submodules/system_uart_wifi.v" "the_system_uart_wifi_rx" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_wifi.v" 1097 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811629206 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_uart_wifi_rx_stimulus_source system:inst_cpu\|system_uart_wifi:uart_wifi\|system_uart_wifi_rx:the_system_uart_wifi_rx\|system_uart_wifi_rx_stimulus_source:the_system_uart_wifi_rx_stimulus_source " "Elaborating entity \"system_uart_wifi_rx_stimulus_source\" for hierarchy \"system:inst_cpu\|system_uart_wifi:uart_wifi\|system_uart_wifi_rx:the_system_uart_wifi_rx\|system_uart_wifi_rx_stimulus_source:the_system_uart_wifi_rx_stimulus_source\"" { } { { "system/synthesis/submodules/system_uart_wifi.v" "the_system_uart_wifi_rx_stimulus_source" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_wifi.v" 569 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811629206 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_uart_wifi_regs system:inst_cpu\|system_uart_wifi:uart_wifi\|system_uart_wifi_regs:the_system_uart_wifi_regs " "Elaborating entity \"system_uart_wifi_regs\" for hierarchy \"system:inst_cpu\|system_uart_wifi:uart_wifi\|system_uart_wifi_regs:the_system_uart_wifi_regs\"" { } { { "system/synthesis/submodules/system_uart_wifi.v" "the_system_uart_wifi_regs" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_wifi.v" 1128 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811629206 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_pio_led system:inst_cpu\|system_pio_led:pio_led " "Elaborating entity \"system_pio_led\" for hierarchy \"system:inst_cpu\|system_pio_led:pio_led\"" { } { { "system/synthesis/system.v" "pio_led" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 918 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811629216 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_pio_key_left system:inst_cpu\|system_pio_key_left:pio_key_left " "Elaborating entity \"system_pio_key_left\" for hierarchy \"system:inst_cpu\|system_pio_key_left:pio_key_left\"" { } { { "system/synthesis/system.v" "pio_key_left" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 930 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811629216 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_pio_sw system:inst_cpu\|system_pio_sw:pio_sw " "Elaborating entity \"system_pio_sw\" for hierarchy \"system:inst_cpu\|system_pio_sw:pio_sw\"" { } { { "system/synthesis/system.v" "pio_sw" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 938 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811629216 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_jtag_uart_0 system:inst_cpu\|system_jtag_uart_0:jtag_uart_0 " "Elaborating entity \"system_jtag_uart_0\" for hierarchy \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\"" { } { { "system/synthesis/system.v" "jtag_uart_0" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 951 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811629216 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_jtag_uart_0_scfifo_w system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w " "Elaborating entity \"system_jtag_uart_0_scfifo_w\" for hierarchy \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\"" { } { { "system/synthesis/submodules/system_jtag_uart_0.v" "the_system_jtag_uart_0_scfifo_w" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_jtag_uart_0.v" 625 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811629216 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scfifo system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo " "Elaborating entity \"scfifo\" for hierarchy \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\"" { } { { "system/synthesis/submodules/system_jtag_uart_0.v" "wfifo" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_jtag_uart_0.v" 183 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811629266 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo " "Elaborated megafunction instantiation \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\"" { } { { "system/synthesis/submodules/system_jtag_uart_0.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_jtag_uart_0.v" 183 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1393811629276 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo " "Instantiated megafunction \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint RAM_BLOCK_TYPE=AUTO " "Parameter \"lpm_hint\" = \"RAM_BLOCK_TYPE=AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811629276 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_numwords 64 " "Parameter \"lpm_numwords\" = \"64\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811629276 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_showahead OFF " "Parameter \"lpm_showahead\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811629276 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type scfifo " "Parameter \"lpm_type\" = \"scfifo\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811629276 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 8 " "Parameter \"lpm_width\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811629276 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widthu 6 " "Parameter \"lpm_widthu\" = \"6\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811629276 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "overflow_checking OFF " "Parameter \"overflow_checking\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811629276 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "underflow_checking OFF " "Parameter \"underflow_checking\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811629276 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "use_eab ON " "Parameter \"use_eab\" = \"ON\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811629276 ""} } { { "system/synthesis/submodules/system_jtag_uart_0.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_jtag_uart_0.v" 183 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1393811629276 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/scfifo_jr21.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/scfifo_jr21.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 scfifo_jr21 " "Found entity 1: scfifo_jr21" { } { { "db/scfifo_jr21.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/scfifo_jr21.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811629326 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393811629326 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scfifo_jr21 system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated " "Elaborating entity \"scfifo_jr21\" for hierarchy \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\"" { } { { "scfifo.tdf" "auto_generated" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/scfifo.tdf" 296 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811629326 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_dpfifo_q131.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/a_dpfifo_q131.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_dpfifo_q131 " "Found entity 1: a_dpfifo_q131" { } { { "db/a_dpfifo_q131.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/a_dpfifo_q131.tdf" 28 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811629336 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393811629336 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_dpfifo_q131 system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo " "Elaborating entity \"a_dpfifo_q131\" for hierarchy \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\"" { } { { "db/scfifo_jr21.tdf" "dpfifo" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/scfifo_jr21.tdf" 37 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811629346 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_fefifo_7cf.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/a_fefifo_7cf.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_fefifo_7cf " "Found entity 1: a_fefifo_7cf" { } { { "db/a_fefifo_7cf.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/a_fefifo_7cf.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811629346 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393811629346 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_fefifo_7cf system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|a_fefifo_7cf:fifo_state " "Elaborating entity \"a_fefifo_7cf\" for hierarchy \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|a_fefifo_7cf:fifo_state\"" { } { { "db/a_dpfifo_q131.tdf" "fifo_state" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/a_dpfifo_q131.tdf" 42 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811629356 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_do7.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_do7.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_do7 " "Found entity 1: cntr_do7" { } { { "db/cntr_do7.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/cntr_do7.tdf" 25 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811629406 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393811629406 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_do7 system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|a_fefifo_7cf:fifo_state\|cntr_do7:count_usedw " "Elaborating entity \"cntr_do7\" for hierarchy \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|a_fefifo_7cf:fifo_state\|cntr_do7:count_usedw\"" { } { { "db/a_fefifo_7cf.tdf" "count_usedw" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/a_fefifo_7cf.tdf" 38 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811629406 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/dpram_nl21.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/dpram_nl21.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 dpram_nl21 " "Found entity 1: dpram_nl21" { } { { "db/dpram_nl21.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/dpram_nl21.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811629466 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393811629466 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dpram_nl21 system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|dpram_nl21:FIFOram " "Elaborating entity \"dpram_nl21\" for hierarchy \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|dpram_nl21:FIFOram\"" { } { { "db/a_dpfifo_q131.tdf" "FIFOram" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/a_dpfifo_q131.tdf" 43 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811629466 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_r1m1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_r1m1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_r1m1 " "Found entity 1: altsyncram_r1m1" { } { { "db/altsyncram_r1m1.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_r1m1.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811629526 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393811629526 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_r1m1 system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|dpram_nl21:FIFOram\|altsyncram_r1m1:altsyncram1 " "Elaborating entity \"altsyncram_r1m1\" for hierarchy \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|dpram_nl21:FIFOram\|altsyncram_r1m1:altsyncram1\"" { } { { "db/dpram_nl21.tdf" "altsyncram1" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/dpram_nl21.tdf" 36 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811629526 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_1ob.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_1ob.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_1ob " "Found entity 1: cntr_1ob" { } { { "db/cntr_1ob.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/cntr_1ob.tdf" 25 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811629586 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393811629586 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_1ob system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|cntr_1ob:rd_ptr_count " "Elaborating entity \"cntr_1ob\" for hierarchy \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|cntr_1ob:rd_ptr_count\"" { } { { "db/a_dpfifo_q131.tdf" "rd_ptr_count" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/a_dpfifo_q131.tdf" 44 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811629586 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_jtag_uart_0_scfifo_r system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r " "Elaborating entity \"system_jtag_uart_0_scfifo_r\" for hierarchy \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r\"" { } { { "system/synthesis/submodules/system_jtag_uart_0.v" "the_system_jtag_uart_0_scfifo_r" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_jtag_uart_0.v" 639 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811629596 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_jtag_atlantic system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic " "Elaborating entity \"alt_jtag_atlantic\" for hierarchy \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic\"" { } { { "system/synthesis/submodules/system_jtag_uart_0.v" "system_jtag_uart_0_alt_jtag_atlantic" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_jtag_uart_0.v" 774 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811629706 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic " "Elaborated megafunction instantiation \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic\"" { } { { "system/synthesis/submodules/system_jtag_uart_0.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_jtag_uart_0.v" 774 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1393811629706 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic " "Instantiated megafunction \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "INSTANCE_ID 0 " "Parameter \"INSTANCE_ID\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811629706 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LOG2_RXFIFO_DEPTH 6 " "Parameter \"LOG2_RXFIFO_DEPTH\" = \"6\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811629706 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LOG2_TXFIFO_DEPTH 6 " "Parameter \"LOG2_TXFIFO_DEPTH\" = \"6\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811629706 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "SLD_AUTO_INSTANCE_INDEX YES " "Parameter \"SLD_AUTO_INSTANCE_INDEX\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811629706 ""} } { { "system/synthesis/submodules/system_jtag_uart_0.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_jtag_uart_0.v" 774 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1393811629706 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_pio_ir_emitter system:inst_cpu\|system_pio_ir_emitter:pio_ir_emitter " "Elaborating entity \"system_pio_ir_emitter\" for hierarchy \"system:inst_cpu\|system_pio_ir_emitter:pio_ir_emitter\"" { } { { "system/synthesis/system.v" "pio_ir_emitter" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 962 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811629716 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_uart_mc system:inst_cpu\|system_uart_mc:uart_mc " "Elaborating entity \"system_uart_mc\" for hierarchy \"system:inst_cpu\|system_uart_mc:uart_mc\"" { } { { "system/synthesis/system.v" "uart_mc" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 979 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811629716 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_uart_mc_tx system:inst_cpu\|system_uart_mc:uart_mc\|system_uart_mc_tx:the_system_uart_mc_tx " "Elaborating entity \"system_uart_mc_tx\" for hierarchy \"system:inst_cpu\|system_uart_mc:uart_mc\|system_uart_mc_tx:the_system_uart_mc_tx\"" { } { { "system/synthesis/submodules/system_uart_mc.v" "the_system_uart_mc_tx" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_mc.v" 1068 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811629716 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_uart_mc_rx system:inst_cpu\|system_uart_mc:uart_mc\|system_uart_mc_rx:the_system_uart_mc_rx " "Elaborating entity \"system_uart_mc_rx\" for hierarchy \"system:inst_cpu\|system_uart_mc:uart_mc\|system_uart_mc_rx:the_system_uart_mc_rx\"" { } { { "system/synthesis/submodules/system_uart_mc.v" "the_system_uart_mc_rx" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_mc.v" 1086 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811629716 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_uart_mc_rx_stimulus_source system:inst_cpu\|system_uart_mc:uart_mc\|system_uart_mc_rx:the_system_uart_mc_rx\|system_uart_mc_rx_stimulus_source:the_system_uart_mc_rx_stimulus_source " "Elaborating entity \"system_uart_mc_rx_stimulus_source\" for hierarchy \"system:inst_cpu\|system_uart_mc:uart_mc\|system_uart_mc_rx:the_system_uart_mc_rx\|system_uart_mc_rx_stimulus_source:the_system_uart_mc_rx_stimulus_source\"" { } { { "system/synthesis/submodules/system_uart_mc.v" "the_system_uart_mc_rx_stimulus_source" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_mc.v" 569 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811629726 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_uart_mc_regs system:inst_cpu\|system_uart_mc:uart_mc\|system_uart_mc_regs:the_system_uart_mc_regs " "Elaborating entity \"system_uart_mc_regs\" for hierarchy \"system:inst_cpu\|system_uart_mc:uart_mc\|system_uart_mc_regs:the_system_uart_mc_regs\"" { } { { "system/synthesis/submodules/system_uart_mc.v" "the_system_uart_mc_regs" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_mc.v" 1117 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811629726 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_rs232_wifi system:inst_cpu\|system_rs232_wifi:rs232_wifi " "Elaborating entity \"system_rs232_wifi\" for hierarchy \"system:inst_cpu\|system_rs232_wifi:rs232_wifi\"" { } { { "system/synthesis/system.v" "rs232_wifi" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 994 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811629726 ""} -{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "write_data_parity system_rs232_wifi.v(123) " "Verilog HDL or VHDL warning at system_rs232_wifi.v(123): object \"write_data_parity\" assigned a value but never read" { } { { "system/synthesis/submodules/system_rs232_wifi.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_rs232_wifi.v" 123 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 -1 1393811629736 "|de0_nano_system|system:inst_cpu|system_rs232_wifi:rs232_wifi"} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_up_rs232_in_deserializer system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer " "Elaborating entity \"altera_up_rs232_in_deserializer\" for hierarchy \"system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\"" { } { { "system/synthesis/submodules/system_rs232_wifi.v" "RS232_In_Deserializer" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_rs232_wifi.v" 268 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811629736 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_up_rs232_counters system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_rs232_counters:RS232_In_Counters " "Elaborating entity \"altera_up_rs232_counters\" for hierarchy \"system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_rs232_counters:RS232_In_Counters\"" { } { { "system/synthesis/submodules/altera_up_rs232_in_deserializer.v" "RS232_In_Counters" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_up_rs232_in_deserializer.v" 181 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811629736 ""} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 altera_up_rs232_counters.v(124) " "Verilog HDL assignment warning at altera_up_rs232_counters.v(124): truncated value with size 32 to match size of target (14)" { } { { "system/synthesis/submodules/altera_up_rs232_counters.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_up_rs232_counters.v" 124 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 -1 1393811629736 "|de0_nano_system|system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_rs232_counters:RS232_In_Counters"} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_up_sync_fifo system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO " "Elaborating entity \"altera_up_sync_fifo\" for hierarchy \"system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\"" { } { { "system/synthesis/submodules/altera_up_rs232_in_deserializer.v" "RS232_In_FIFO" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_up_rs232_in_deserializer.v" 206 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811629736 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scfifo system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO " "Elaborating entity \"scfifo\" for hierarchy \"system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\"" { } { { "system/synthesis/submodules/altera_up_sync_fifo.v" "Sync_FIFO" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_up_sync_fifo.v" 157 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811629766 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO " "Elaborated megafunction instantiation \"system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\"" { } { { "system/synthesis/submodules/altera_up_sync_fifo.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_up_sync_fifo.v" 157 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1393811629766 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO " "Instantiated megafunction \"system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "add_ram_output_register OFF " "Parameter \"add_ram_output_register\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811629766 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone II " "Parameter \"intended_device_family\" = \"Cyclone II\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811629766 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_numwords 128 " "Parameter \"lpm_numwords\" = \"128\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811629766 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_showahead ON " "Parameter \"lpm_showahead\" = \"ON\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811629766 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type scfifo " "Parameter \"lpm_type\" = \"scfifo\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811629766 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 8 " "Parameter \"lpm_width\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811629766 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widthu 7 " "Parameter \"lpm_widthu\" = \"7\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811629766 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "overflow_checking OFF " "Parameter \"overflow_checking\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811629766 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "underflow_checking OFF " "Parameter \"underflow_checking\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811629766 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "use_eab ON " "Parameter \"use_eab\" = \"ON\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811629766 ""} } { { "system/synthesis/submodules/altera_up_sync_fifo.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_up_sync_fifo.v" 157 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1393811629766 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/scfifo_a341.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/scfifo_a341.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 scfifo_a341 " "Found entity 1: scfifo_a341" { } { { "db/scfifo_a341.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/scfifo_a341.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811629826 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393811629826 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scfifo_a341 system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated " "Elaborating entity \"scfifo_a341\" for hierarchy \"system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\"" { } { { "scfifo.tdf" "auto_generated" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/scfifo.tdf" 296 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811629826 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_dpfifo_tq31.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/a_dpfifo_tq31.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_dpfifo_tq31 " "Found entity 1: a_dpfifo_tq31" { } { { "db/a_dpfifo_tq31.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/a_dpfifo_tq31.tdf" 32 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811629836 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393811629836 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_dpfifo_tq31 system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo " "Elaborating entity \"a_dpfifo_tq31\" for hierarchy \"system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\"" { } { { "db/scfifo_a341.tdf" "dpfifo" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/scfifo_a341.tdf" 37 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811629836 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_je81.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_je81.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_je81 " "Found entity 1: altsyncram_je81" { } { { "db/altsyncram_je81.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_je81.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811629896 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393811629896 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_je81 system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|altsyncram_je81:FIFOram " "Elaborating entity \"altsyncram_je81\" for hierarchy \"system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|altsyncram_je81:FIFOram\"" { } { { "db/a_dpfifo_tq31.tdf" "FIFOram" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/a_dpfifo_tq31.tdf" 45 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811629906 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cmpr_ks8.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cmpr_ks8.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cmpr_ks8 " "Found entity 1: cmpr_ks8" { } { { "db/cmpr_ks8.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/cmpr_ks8.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811629956 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393811629956 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cmpr_ks8 system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cmpr_ks8:almost_full_comparer " "Elaborating entity \"cmpr_ks8\" for hierarchy \"system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cmpr_ks8:almost_full_comparer\"" { } { { "db/a_dpfifo_tq31.tdf" "almost_full_comparer" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/a_dpfifo_tq31.tdf" 54 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811629956 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cmpr_ks8 system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cmpr_ks8:three_comparison " "Elaborating entity \"cmpr_ks8\" for hierarchy \"system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cmpr_ks8:three_comparison\"" { } { { "db/a_dpfifo_tq31.tdf" "three_comparison" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/a_dpfifo_tq31.tdf" 55 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811629956 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_v9b.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_v9b.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_v9b " "Found entity 1: cntr_v9b" { } { { "db/cntr_v9b.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/cntr_v9b.tdf" 25 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811630016 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393811630016 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_v9b system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_v9b:rd_ptr_msb " "Elaborating entity \"cntr_v9b\" for hierarchy \"system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_v9b:rd_ptr_msb\"" { } { { "db/a_dpfifo_tq31.tdf" "rd_ptr_msb" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/a_dpfifo_tq31.tdf" 56 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811630016 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_ca7.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_ca7.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_ca7 " "Found entity 1: cntr_ca7" { } { { "db/cntr_ca7.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/cntr_ca7.tdf" 25 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811630066 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393811630066 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_ca7 system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_ca7:usedw_counter " "Elaborating entity \"cntr_ca7\" for hierarchy \"system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_ca7:usedw_counter\"" { } { { "db/a_dpfifo_tq31.tdf" "usedw_counter" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/a_dpfifo_tq31.tdf" 57 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811630076 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_0ab.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_0ab.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_0ab " "Found entity 1: cntr_0ab" { } { { "db/cntr_0ab.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/cntr_0ab.tdf" 25 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811630126 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393811630126 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_0ab system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr " "Elaborating entity \"cntr_0ab\" for hierarchy \"system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr\"" { } { { "db/a_dpfifo_tq31.tdf" "wr_ptr" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/a_dpfifo_tq31.tdf" 58 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811630126 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_up_rs232_out_serializer system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_out_serializer:RS232_Out_Serializer " "Elaborating entity \"altera_up_rs232_out_serializer\" for hierarchy \"system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_out_serializer:RS232_Out_Serializer\"" { } { { "system/synthesis/submodules/system_rs232_wifi.v" "RS232_Out_Serializer" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_rs232_wifi.v" 290 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811630136 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_master_translator system:inst_cpu\|altera_merlin_master_translator:cpu_instruction_master_translator " "Elaborating entity \"altera_merlin_master_translator\" for hierarchy \"system:inst_cpu\|altera_merlin_master_translator:cpu_instruction_master_translator\"" { } { { "system/synthesis/system.v" "cpu_instruction_master_translator" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 1048 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811630186 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_master_translator system:inst_cpu\|altera_merlin_master_translator:cpu_data_master_translator " "Elaborating entity \"altera_merlin_master_translator\" for hierarchy \"system:inst_cpu\|altera_merlin_master_translator:cpu_data_master_translator\"" { } { { "system/synthesis/system.v" "cpu_data_master_translator" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 1102 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811630196 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_translator system:inst_cpu\|altera_merlin_slave_translator:cpu_jtag_debug_module_translator " "Elaborating entity \"altera_merlin_slave_translator\" for hierarchy \"system:inst_cpu\|altera_merlin_slave_translator:cpu_jtag_debug_module_translator\"" { } { { "system/synthesis/system.v" "cpu_jtag_debug_module_translator" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 1160 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811630196 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_translator system:inst_cpu\|altera_merlin_slave_translator:sdram_s1_translator " "Elaborating entity \"altera_merlin_slave_translator\" for hierarchy \"system:inst_cpu\|altera_merlin_slave_translator:sdram_s1_translator\"" { } { { "system/synthesis/system.v" "sdram_s1_translator" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 1218 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811630196 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_translator system:inst_cpu\|altera_merlin_slave_translator:sysid_control_slave_translator " "Elaborating entity \"altera_merlin_slave_translator\" for hierarchy \"system:inst_cpu\|altera_merlin_slave_translator:sysid_control_slave_translator\"" { } { { "system/synthesis/system.v" "sysid_control_slave_translator" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 1276 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811630196 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_translator system:inst_cpu\|altera_merlin_slave_translator:sys_clk_timer_s1_translator " "Elaborating entity \"altera_merlin_slave_translator\" for hierarchy \"system:inst_cpu\|altera_merlin_slave_translator:sys_clk_timer_s1_translator\"" { } { { "system/synthesis/system.v" "sys_clk_timer_s1_translator" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 1334 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811630206 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_translator system:inst_cpu\|altera_merlin_slave_translator:uart_wifi_s1_translator " "Elaborating entity \"altera_merlin_slave_translator\" for hierarchy \"system:inst_cpu\|altera_merlin_slave_translator:uart_wifi_s1_translator\"" { } { { "system/synthesis/system.v" "uart_wifi_s1_translator" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 1392 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811630206 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_translator system:inst_cpu\|altera_merlin_slave_translator:pio_led_s1_translator " "Elaborating entity \"altera_merlin_slave_translator\" for hierarchy \"system:inst_cpu\|altera_merlin_slave_translator:pio_led_s1_translator\"" { } { { "system/synthesis/system.v" "pio_led_s1_translator" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 1450 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811630206 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_translator system:inst_cpu\|altera_merlin_slave_translator:pio_key_left_s1_translator " "Elaborating entity \"altera_merlin_slave_translator\" for hierarchy \"system:inst_cpu\|altera_merlin_slave_translator:pio_key_left_s1_translator\"" { } { { "system/synthesis/system.v" "pio_key_left_s1_translator" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 1508 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811630216 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_translator system:inst_cpu\|altera_merlin_slave_translator:jtag_uart_0_avalon_jtag_slave_translator " "Elaborating entity \"altera_merlin_slave_translator\" for hierarchy \"system:inst_cpu\|altera_merlin_slave_translator:jtag_uart_0_avalon_jtag_slave_translator\"" { } { { "system/synthesis/system.v" "jtag_uart_0_avalon_jtag_slave_translator" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 1624 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811630216 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_translator system:inst_cpu\|altera_merlin_slave_translator:rs232_wifi_avalon_rs232_slave_translator " "Elaborating entity \"altera_merlin_slave_translator\" for hierarchy \"system:inst_cpu\|altera_merlin_slave_translator:rs232_wifi_avalon_rs232_slave_translator\"" { } { { "system/synthesis/system.v" "rs232_wifi_avalon_rs232_slave_translator" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 1798 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811630226 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_master_agent system:inst_cpu\|altera_merlin_master_agent:cpu_instruction_master_translator_avalon_universal_master_0_agent " "Elaborating entity \"altera_merlin_master_agent\" for hierarchy \"system:inst_cpu\|altera_merlin_master_agent:cpu_instruction_master_translator_avalon_universal_master_0_agent\"" { } { { "system/synthesis/system.v" "cpu_instruction_master_translator_avalon_universal_master_0_agent" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 1870 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811630226 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_master_agent system:inst_cpu\|altera_merlin_master_agent:cpu_data_master_translator_avalon_universal_master_0_agent " "Elaborating entity \"altera_merlin_master_agent\" for hierarchy \"system:inst_cpu\|altera_merlin_master_agent:cpu_data_master_translator_avalon_universal_master_0_agent\"" { } { { "system/synthesis/system.v" "cpu_data_master_translator_avalon_universal_master_0_agent" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 1942 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811630226 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_agent system:inst_cpu\|altera_merlin_slave_agent:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent " "Elaborating entity \"altera_merlin_slave_agent\" for hierarchy \"system:inst_cpu\|altera_merlin_slave_agent:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent\"" { } { { "system/synthesis/system.v" "cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 2018 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811630236 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_burst_uncompressor system:inst_cpu\|altera_merlin_slave_agent:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent\|altera_merlin_burst_uncompressor:uncompressor " "Elaborating entity \"altera_merlin_burst_uncompressor\" for hierarchy \"system:inst_cpu\|altera_merlin_slave_agent:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent\|altera_merlin_burst_uncompressor:uncompressor\"" { } { { "system/synthesis/submodules/altera_merlin_slave_agent.sv" "uncompressor" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_slave_agent.sv" 476 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811630236 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_avalon_sc_fifo system:inst_cpu\|altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo " "Elaborating entity \"altera_avalon_sc_fifo\" for hierarchy \"system:inst_cpu\|altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo\"" { } { { "system/synthesis/system.v" "cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 2059 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811630236 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_agent system:inst_cpu\|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent " "Elaborating entity \"altera_merlin_slave_agent\" for hierarchy \"system:inst_cpu\|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent\"" { } { { "system/synthesis/system.v" "sdram_s1_translator_avalon_universal_slave_0_agent" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 2135 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811630246 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_burst_uncompressor system:inst_cpu\|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent\|altera_merlin_burst_uncompressor:uncompressor " "Elaborating entity \"altera_merlin_burst_uncompressor\" for hierarchy \"system:inst_cpu\|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent\|altera_merlin_burst_uncompressor:uncompressor\"" { } { { "system/synthesis/submodules/altera_merlin_slave_agent.sv" "uncompressor" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_slave_agent.sv" 476 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811630246 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_avalon_sc_fifo system:inst_cpu\|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo " "Elaborating entity \"altera_avalon_sc_fifo\" for hierarchy \"system:inst_cpu\|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo\"" { } { { "system/synthesis/system.v" "sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 2176 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811630256 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_addr_router system:inst_cpu\|system_addr_router:addr_router " "Elaborating entity \"system_addr_router\" for hierarchy \"system:inst_cpu\|system_addr_router:addr_router\"" { } { { "system/synthesis/system.v" "addr_router" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 3362 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811630306 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_addr_router_default_decode system:inst_cpu\|system_addr_router:addr_router\|system_addr_router_default_decode:the_default_decode " "Elaborating entity \"system_addr_router_default_decode\" for hierarchy \"system:inst_cpu\|system_addr_router:addr_router\|system_addr_router_default_decode:the_default_decode\"" { } { { "system/synthesis/submodules/system_addr_router.sv" "the_default_decode" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_addr_router.sv" 140 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811630306 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_addr_router_001 system:inst_cpu\|system_addr_router_001:addr_router_001 " "Elaborating entity \"system_addr_router_001\" for hierarchy \"system:inst_cpu\|system_addr_router_001:addr_router_001\"" { } { { "system/synthesis/system.v" "addr_router_001" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 3378 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811630306 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_addr_router_001_default_decode system:inst_cpu\|system_addr_router_001:addr_router_001\|system_addr_router_001_default_decode:the_default_decode " "Elaborating entity \"system_addr_router_001_default_decode\" for hierarchy \"system:inst_cpu\|system_addr_router_001:addr_router_001\|system_addr_router_001_default_decode:the_default_decode\"" { } { { "system/synthesis/submodules/system_addr_router_001.sv" "the_default_decode" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_addr_router_001.sv" 150 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811630316 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_id_router system:inst_cpu\|system_id_router:id_router " "Elaborating entity \"system_id_router\" for hierarchy \"system:inst_cpu\|system_id_router:id_router\"" { } { { "system/synthesis/system.v" "id_router" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 3394 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811630316 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_id_router_default_decode system:inst_cpu\|system_id_router:id_router\|system_id_router_default_decode:the_default_decode " "Elaborating entity \"system_id_router_default_decode\" for hierarchy \"system:inst_cpu\|system_id_router:id_router\|system_id_router_default_decode:the_default_decode\"" { } { { "system/synthesis/submodules/system_id_router.sv" "the_default_decode" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_id_router.sv" 138 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811630316 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_id_router_001 system:inst_cpu\|system_id_router_001:id_router_001 " "Elaborating entity \"system_id_router_001\" for hierarchy \"system:inst_cpu\|system_id_router_001:id_router_001\"" { } { { "system/synthesis/system.v" "id_router_001" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 3410 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811630316 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_id_router_001_default_decode system:inst_cpu\|system_id_router_001:id_router_001\|system_id_router_001_default_decode:the_default_decode " "Elaborating entity \"system_id_router_001_default_decode\" for hierarchy \"system:inst_cpu\|system_id_router_001:id_router_001\|system_id_router_001_default_decode:the_default_decode\"" { } { { "system/synthesis/submodules/system_id_router_001.sv" "the_default_decode" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_id_router_001.sv" 138 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811630326 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_id_router_002 system:inst_cpu\|system_id_router_002:id_router_002 " "Elaborating entity \"system_id_router_002\" for hierarchy \"system:inst_cpu\|system_id_router_002:id_router_002\"" { } { { "system/synthesis/system.v" "id_router_002" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 3426 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811630326 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_id_router_002_default_decode system:inst_cpu\|system_id_router_002:id_router_002\|system_id_router_002_default_decode:the_default_decode " "Elaborating entity \"system_id_router_002_default_decode\" for hierarchy \"system:inst_cpu\|system_id_router_002:id_router_002\|system_id_router_002_default_decode:the_default_decode\"" { } { { "system/synthesis/submodules/system_id_router_002.sv" "the_default_decode" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_id_router_002.sv" 138 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811630326 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_traffic_limiter system:inst_cpu\|altera_merlin_traffic_limiter:limiter " "Elaborating entity \"altera_merlin_traffic_limiter\" for hierarchy \"system:inst_cpu\|altera_merlin_traffic_limiter:limiter\"" { } { { "system/synthesis/system.v" "limiter" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 3615 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811630346 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_burst_adapter system:inst_cpu\|altera_merlin_burst_adapter:burst_adapter " "Elaborating entity \"altera_merlin_burst_adapter\" for hierarchy \"system:inst_cpu\|altera_merlin_burst_adapter:burst_adapter\"" { } { { "system/synthesis/system.v" "burst_adapter" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 3708 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811630356 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_burst_adapter_uncompressed_only system:inst_cpu\|altera_merlin_burst_adapter:burst_adapter\|altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba " "Elaborating entity \"altera_merlin_burst_adapter_uncompressed_only\" for hierarchy \"system:inst_cpu\|altera_merlin_burst_adapter:burst_adapter\|altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba\"" { } { { "system/synthesis/submodules/altera_merlin_burst_adapter.sv" "altera_merlin_burst_adapter_uncompressed_only.the_ba" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_burst_adapter.sv" 397 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811630356 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_reset_controller system:inst_cpu\|altera_reset_controller:rst_controller " "Elaborating entity \"altera_reset_controller\" for hierarchy \"system:inst_cpu\|altera_reset_controller:rst_controller\"" { } { { "system/synthesis/system.v" "rst_controller" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 3733 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811630356 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_reset_synchronizer system:inst_cpu\|altera_reset_controller:rst_controller\|altera_reset_synchronizer:alt_rst_sync_uq1 " "Elaborating entity \"altera_reset_synchronizer\" for hierarchy \"system:inst_cpu\|altera_reset_controller:rst_controller\|altera_reset_synchronizer:alt_rst_sync_uq1\"" { } { { "system/synthesis/submodules/altera_reset_controller.v" "alt_rst_sync_uq1" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_reset_controller.v" 105 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811630356 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cmd_xbar_demux system:inst_cpu\|system_cmd_xbar_demux:cmd_xbar_demux " "Elaborating entity \"system_cmd_xbar_demux\" for hierarchy \"system:inst_cpu\|system_cmd_xbar_demux:cmd_xbar_demux\"" { } { { "system/synthesis/system.v" "cmd_xbar_demux" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 3756 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811630356 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cmd_xbar_demux_001 system:inst_cpu\|system_cmd_xbar_demux_001:cmd_xbar_demux_001 " "Elaborating entity \"system_cmd_xbar_demux_001\" for hierarchy \"system:inst_cpu\|system_cmd_xbar_demux_001:cmd_xbar_demux_001\"" { } { { "system/synthesis/system.v" "cmd_xbar_demux_001" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 3839 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811630366 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cmd_xbar_mux system:inst_cpu\|system_cmd_xbar_mux:cmd_xbar_mux " "Elaborating entity \"system_cmd_xbar_mux\" for hierarchy \"system:inst_cpu\|system_cmd_xbar_mux:cmd_xbar_mux\"" { } { { "system/synthesis/system.v" "cmd_xbar_mux" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 3862 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811630366 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arbitrator system:inst_cpu\|system_cmd_xbar_mux:cmd_xbar_mux\|altera_merlin_arbitrator:arb " "Elaborating entity \"altera_merlin_arbitrator\" for hierarchy \"system:inst_cpu\|system_cmd_xbar_mux:cmd_xbar_mux\|altera_merlin_arbitrator:arb\"" { } { { "system/synthesis/submodules/system_cmd_xbar_mux.sv" "arb" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cmd_xbar_mux.sv" 273 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811630366 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arb_adder system:inst_cpu\|system_cmd_xbar_mux:cmd_xbar_mux\|altera_merlin_arbitrator:arb\|altera_merlin_arb_adder:adder " "Elaborating entity \"altera_merlin_arb_adder\" for hierarchy \"system:inst_cpu\|system_cmd_xbar_mux:cmd_xbar_mux\|altera_merlin_arbitrator:arb\|altera_merlin_arb_adder:adder\"" { } { { "system/synthesis/submodules/altera_merlin_arbitrator.sv" "adder" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_arbitrator.sv" 169 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811630376 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_rsp_xbar_demux system:inst_cpu\|system_rsp_xbar_demux:rsp_xbar_demux " "Elaborating entity \"system_rsp_xbar_demux\" for hierarchy \"system:inst_cpu\|system_rsp_xbar_demux:rsp_xbar_demux\"" { } { { "system/synthesis/system.v" "rsp_xbar_demux" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 3908 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811630376 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_rsp_xbar_demux_002 system:inst_cpu\|system_rsp_xbar_demux_002:rsp_xbar_demux_002 " "Elaborating entity \"system_rsp_xbar_demux_002\" for hierarchy \"system:inst_cpu\|system_rsp_xbar_demux_002:rsp_xbar_demux_002\"" { } { { "system/synthesis/system.v" "rsp_xbar_demux_002" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 3948 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811630386 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_rsp_xbar_mux system:inst_cpu\|system_rsp_xbar_mux:rsp_xbar_mux " "Elaborating entity \"system_rsp_xbar_mux\" for hierarchy \"system:inst_cpu\|system_rsp_xbar_mux:rsp_xbar_mux\"" { } { { "system/synthesis/system.v" "rsp_xbar_mux" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 4124 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811630386 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arbitrator system:inst_cpu\|system_rsp_xbar_mux:rsp_xbar_mux\|altera_merlin_arbitrator:arb " "Elaborating entity \"altera_merlin_arbitrator\" for hierarchy \"system:inst_cpu\|system_rsp_xbar_mux:rsp_xbar_mux\|altera_merlin_arbitrator:arb\"" { } { { "system/synthesis/submodules/system_rsp_xbar_mux.sv" "arb" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_rsp_xbar_mux.sv" 296 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811630396 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_rsp_xbar_mux_001 system:inst_cpu\|system_rsp_xbar_mux_001:rsp_xbar_mux_001 " "Elaborating entity \"system_rsp_xbar_mux_001\" for hierarchy \"system:inst_cpu\|system_rsp_xbar_mux_001:rsp_xbar_mux_001\"" { } { { "system/synthesis/system.v" "rsp_xbar_mux_001" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 4207 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811630396 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arbitrator system:inst_cpu\|system_rsp_xbar_mux_001:rsp_xbar_mux_001\|altera_merlin_arbitrator:arb " "Elaborating entity \"altera_merlin_arbitrator\" for hierarchy \"system:inst_cpu\|system_rsp_xbar_mux_001:rsp_xbar_mux_001\|altera_merlin_arbitrator:arb\"" { } { { "system/synthesis/submodules/system_rsp_xbar_mux_001.sv" "arb" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_rsp_xbar_mux_001.sv" 456 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811630406 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arb_adder system:inst_cpu\|system_rsp_xbar_mux_001:rsp_xbar_mux_001\|altera_merlin_arbitrator:arb\|altera_merlin_arb_adder:adder " "Elaborating entity \"altera_merlin_arb_adder\" for hierarchy \"system:inst_cpu\|system_rsp_xbar_mux_001:rsp_xbar_mux_001\|altera_merlin_arbitrator:arb\|altera_merlin_arb_adder:adder\"" { } { { "system/synthesis/submodules/altera_merlin_arbitrator.sv" "adder" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_arbitrator.sv" 169 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811630406 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_width_adapter system:inst_cpu\|altera_merlin_width_adapter:width_adapter " "Elaborating entity \"altera_merlin_width_adapter\" for hierarchy \"system:inst_cpu\|altera_merlin_width_adapter:width_adapter\"" { } { { "system/synthesis/system.v" "width_adapter" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 4264 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811630406 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_width_adapter system:inst_cpu\|altera_merlin_width_adapter:width_adapter_001 " "Elaborating entity \"altera_merlin_width_adapter\" for hierarchy \"system:inst_cpu\|altera_merlin_width_adapter:width_adapter_001\"" { } { { "system/synthesis/system.v" "width_adapter_001" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 4321 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811630416 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_irq_mapper system:inst_cpu\|system_irq_mapper:irq_mapper " "Elaborating entity \"system_irq_mapper\" for hierarchy \"system:inst_cpu\|system_irq_mapper:irq_mapper\"" { } { { "system/synthesis/system.v" "irq_mapper" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 4333 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393811630416 ""} -{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "address_b system_cpu_traceram_lpm_dram_bdp_component 17 7 " "Port \"address_b\" on the entity instantiation of \"system_cpu_traceram_lpm_dram_bdp_component\" is connected to a signal of width 17. The formal width of the signal in the module is 7. The extra bits will be ignored." { } { { "system/synthesis/submodules/system_cpu.v" "system_cpu_traceram_lpm_dram_bdp_component" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } } 0 12020 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. The extra bits will be ignored." 0 0 "" 0 -1 1393811632126 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component"} -{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "jdo the_system_cpu_nios2_oci_itrace 38 16 " "Port \"jdo\" on the entity instantiation of \"the_system_cpu_nios2_oci_itrace\" is connected to a signal of width 38. The formal width of the signal in the module is 16. The extra bits will be ignored." { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_nios2_oci_itrace" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3606 0 0 } } } 0 12020 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. The extra bits will be ignored." 0 0 "" 0 -1 1393811632126 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_itrace:the_system_cpu_nios2_oci_itrace"} -{ "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_HDR" "" "Synthesized away the following node(s):" { { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_SUB_HDR" "RAM " "Synthesized away the following RAM node(s):" { { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[0\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[0\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 43 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393811633316 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a0"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[1\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[1\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 77 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393811633316 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a1"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[2\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[2\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 111 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393811633316 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a2"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[3\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[3\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 145 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393811633316 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a3"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[4\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[4\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 179 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393811633316 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a4"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[5\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[5\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 213 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393811633316 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a5"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[6\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[6\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 247 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393811633316 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a6"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[7\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[7\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 281 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393811633316 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a7"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[8\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[8\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 315 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393811633316 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a8"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[9\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[9\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 349 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393811633316 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a9"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[10\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[10\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 383 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393811633316 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a10"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[11\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[11\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 417 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393811633316 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a11"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[12\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[12\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 451 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393811633316 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a12"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[13\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[13\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 485 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393811633316 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a13"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[14\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[14\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 519 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393811633316 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a14"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[15\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[15\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 553 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393811633316 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a15"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[16\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[16\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 587 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393811633316 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a16"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[17\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[17\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 621 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393811633316 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a17"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[18\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[18\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 655 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393811633316 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a18"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[19\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[19\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 689 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393811633316 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a19"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[20\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[20\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 723 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393811633316 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a20"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[21\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[21\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 757 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393811633316 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a21"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[22\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[22\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 791 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393811633316 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a22"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[23\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[23\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 825 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393811633316 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a23"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[24\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[24\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 859 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393811633316 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a24"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[25\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[25\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 893 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393811633316 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a25"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[26\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[26\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 927 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393811633316 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a26"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[27\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[27\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 961 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393811633316 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a27"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[28\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[28\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 995 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393811633316 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a28"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[29\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[29\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 1029 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393811633316 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a29"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[30\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[30\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 1063 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393811633316 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a30"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[31\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[31\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 1097 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393811633316 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a31"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[32\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[32\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 1131 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393811633316 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a32"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[33\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[33\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 1165 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393811633316 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a33"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[34\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[34\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 1199 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393811633316 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a34"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[35\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[35\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 1233 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393811633316 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a35"} } { } 0 14285 "Synthesized away the following %1!s! node(s):" 0 0 "" 0 -1 1393811633316 ""} } { } 0 14284 "Synthesized away the following node(s):" 0 0 "" 0 -1 1393811633316 ""} -{ "Info" "ILPMS_INFERENCING_SUMMARY" "1 " "Inferred 1 megafunctions from design logic" { { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "system:inst_cpu\|system_cpu:cpu\|Add17 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"system:inst_cpu\|system_cpu:cpu\|Add17\"" { } { { "system/synthesis/submodules/system_cpu.v" "Add17" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 8743 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1 1393811638756 ""} } { } 0 278001 "Inferred %1!llu! megafunctions from design logic" 0 0 "" 0 -1 1393811638756 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_cpu:cpu\|lpm_add_sub:Add17 " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|lpm_add_sub:Add17\"" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 8743 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1393811638796 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_cpu:cpu\|lpm_add_sub:Add17 " "Instantiated megafunction \"system:inst_cpu\|system_cpu:cpu\|lpm_add_sub:Add17\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 33 " "Parameter \"LPM_WIDTH\" = \"33\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811638796 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION DEFAULT " "Parameter \"LPM_DIRECTION\" = \"DEFAULT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811638796 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811638796 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT NO " "Parameter \"ONE_INPUT_IS_CONSTANT\" = \"NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393811638796 ""} } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 8743 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1393811638796 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_qvi.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/add_sub_qvi.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_qvi " "Found entity 1: add_sub_qvi" { } { { "db/add_sub_qvi.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/add_sub_qvi.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393811638846 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393811638846 ""} -{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "2 " "2 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "" 0 -1 1393811639816 ""} -{ "Warning" "WMLS_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC_HDR" "" "The following nodes have both tri-state and non-tri-state drivers" { { "Warning" "WMLS_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC" "GPIO_0\[33\] " "Inserted always-enabled tri-state buffer between \"GPIO_0\[33\]\" and its non-tri-state driver." { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13035 "Inserted always-enabled tri-state buffer between \"%1!s!\" and its non-tri-state driver." 0 0 "" 0 -1 1393811640016 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC" "GPIO_1\[0\] " "Inserted always-enabled tri-state buffer between \"GPIO_1\[0\]\" and its non-tri-state driver." { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13035 "Inserted always-enabled tri-state buffer between \"%1!s!\" and its non-tri-state driver." 0 0 "" 0 -1 1393811640016 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC" "GPIO_1\[33\] " "Inserted always-enabled tri-state buffer between \"GPIO_1\[33\]\" and its non-tri-state driver." { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13035 "Inserted always-enabled tri-state buffer between \"%1!s!\" and its non-tri-state driver." 0 0 "" 0 -1 1393811640016 ""} } { } 0 13034 "The following nodes have both tri-state and non-tri-state drivers" 0 0 "" 0 -1 1393811640016 ""} -{ "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI_HDR" "" "The following bidir pins have no drivers" { { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[0\] " "Bidir \"GPIO_0\[0\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393811640016 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[1\] " "Bidir \"GPIO_0\[1\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393811640016 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[2\] " "Bidir \"GPIO_0\[2\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393811640016 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[3\] " "Bidir \"GPIO_0\[3\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393811640016 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[4\] " "Bidir \"GPIO_0\[4\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393811640016 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[5\] " "Bidir \"GPIO_0\[5\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393811640016 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[6\] " "Bidir \"GPIO_0\[6\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393811640016 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[7\] " "Bidir \"GPIO_0\[7\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393811640016 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[8\] " "Bidir \"GPIO_0\[8\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393811640016 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[9\] " "Bidir \"GPIO_0\[9\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393811640016 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[10\] " "Bidir \"GPIO_0\[10\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393811640016 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[11\] " "Bidir \"GPIO_0\[11\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393811640016 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[12\] " "Bidir \"GPIO_0\[12\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393811640016 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[13\] " "Bidir \"GPIO_0\[13\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393811640016 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[14\] " "Bidir \"GPIO_0\[14\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393811640016 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[15\] " "Bidir \"GPIO_0\[15\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393811640016 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[16\] " "Bidir \"GPIO_0\[16\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393811640016 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[17\] " "Bidir \"GPIO_0\[17\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393811640016 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[18\] " "Bidir \"GPIO_0\[18\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393811640016 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[19\] " "Bidir \"GPIO_0\[19\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393811640016 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[20\] " "Bidir \"GPIO_0\[20\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393811640016 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[21\] " "Bidir \"GPIO_0\[21\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393811640016 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[22\] " "Bidir \"GPIO_0\[22\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393811640016 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[23\] " "Bidir \"GPIO_0\[23\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393811640016 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[24\] " "Bidir \"GPIO_0\[24\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393811640016 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[25\] " "Bidir \"GPIO_0\[25\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393811640016 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[26\] " "Bidir \"GPIO_0\[26\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393811640016 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[27\] " "Bidir \"GPIO_0\[27\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393811640016 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[28\] " "Bidir \"GPIO_0\[28\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393811640016 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[29\] " "Bidir \"GPIO_0\[29\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393811640016 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[30\] " "Bidir \"GPIO_0\[30\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393811640016 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[32\] " "Bidir \"GPIO_0\[32\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393811640016 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[1\] " "Bidir \"GPIO_1\[1\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393811640016 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[2\] " "Bidir \"GPIO_1\[2\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393811640016 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[3\] " "Bidir \"GPIO_1\[3\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393811640016 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[4\] " "Bidir \"GPIO_1\[4\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393811640016 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[5\] " "Bidir \"GPIO_1\[5\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393811640016 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[6\] " "Bidir \"GPIO_1\[6\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393811640016 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[7\] " "Bidir \"GPIO_1\[7\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393811640016 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[8\] " "Bidir \"GPIO_1\[8\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393811640016 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[9\] " "Bidir \"GPIO_1\[9\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393811640016 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[10\] " "Bidir \"GPIO_1\[10\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393811640016 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[11\] " "Bidir \"GPIO_1\[11\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393811640016 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[12\] " "Bidir \"GPIO_1\[12\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393811640016 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[13\] " "Bidir \"GPIO_1\[13\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393811640016 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[14\] " "Bidir \"GPIO_1\[14\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393811640016 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[15\] " "Bidir \"GPIO_1\[15\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393811640016 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[16\] " "Bidir \"GPIO_1\[16\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393811640016 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[17\] " "Bidir \"GPIO_1\[17\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393811640016 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[18\] " "Bidir \"GPIO_1\[18\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393811640016 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[19\] " "Bidir \"GPIO_1\[19\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393811640016 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[20\] " "Bidir \"GPIO_1\[20\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393811640016 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[21\] " "Bidir \"GPIO_1\[21\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393811640016 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[22\] " "Bidir \"GPIO_1\[22\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393811640016 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[23\] " "Bidir \"GPIO_1\[23\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393811640016 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[24\] " "Bidir \"GPIO_1\[24\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393811640016 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[25\] " "Bidir \"GPIO_1\[25\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393811640016 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[26\] " "Bidir \"GPIO_1\[26\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393811640016 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[27\] " "Bidir \"GPIO_1\[27\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393811640016 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[28\] " "Bidir \"GPIO_1\[28\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393811640016 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[29\] " "Bidir \"GPIO_1\[29\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393811640016 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[30\] " "Bidir \"GPIO_1\[30\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393811640016 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[32\] " "Bidir \"GPIO_1\[32\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393811640016 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[31\] " "Bidir \"GPIO_0\[31\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393811640016 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[31\] " "Bidir \"GPIO_1\[31\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393811640016 ""} } { } 0 13039 "The following bidir pins have no drivers" 0 0 "" 0 -1 1393811640016 ""} -{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" { } { { "system/synthesis/submodules/system_sdram.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_sdram.v" 440 -1 0 } } { "system/synthesis/submodules/system_sdram.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_sdram.v" 354 -1 0 } } { "system/synthesis/submodules/altera_reset_synchronizer.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_reset_synchronizer.v" 62 -1 0 } } { "system/synthesis/submodules/system_sdram.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_sdram.v" 304 -1 0 } } { "system/synthesis/submodules/altera_merlin_slave_translator.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_slave_translator.sv" 277 -1 0 } } { "system/synthesis/submodules/system_jtag_uart_0.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_jtag_uart_0.v" 558 -1 0 } } { "alt_jtag_atlantic.v" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/alt_jtag_atlantic.v" 291 -1 0 } } { "system/synthesis/submodules/system_uart_mc.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_mc.v" 89 -1 0 } } { "system/synthesis/submodules/altera_merlin_arbitrator.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_arbitrator.sv" 203 -1 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 5563 -1 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 5963 -1 0 } } { "system/synthesis/submodules/system_jtag_uart_0.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_jtag_uart_0.v" 603 -1 0 } } { "system/synthesis/submodules/system_uart_mc.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_mc.v" 105 -1 0 } } { "alt_jtag_atlantic.v" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/alt_jtag_atlantic.v" 224 -1 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 5995 -1 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 9343 -1 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 9492 -1 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 982 -1 0 } } { "system/synthesis/submodules/system_uart_mc.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_mc.v" 87 -1 0 } } { "system/synthesis/submodules/system_uart_wifi.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_wifi.v" 88 -1 0 } } { "system/synthesis/submodules/system_uart_wifi.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_wifi.v" 87 -1 0 } } { "system/synthesis/submodules/system_uart_mc.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_mc.v" 88 -1 0 } } { "system/synthesis/submodules/system_sys_clk_timer.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_sys_clk_timer.v" 166 -1 0 } } { "system/synthesis/submodules/system_sys_clk_timer.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_sys_clk_timer.v" 175 -1 0 } } { "system/synthesis/submodules/system_uart_wifi.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_wifi.v" 891 -1 0 } } } 0 13000 "Registers with preset signals will power-up high" 0 0 "" 0 -1 1393811640186 ""} -{ "Info" "IMLS_MLS_DEV_CLRN_SETS_REGISTERS" "" "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" { } { } 0 13003 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "" 0 -1 1393811640186 ""} -{ "Warning" "WMLS_MLS_ENABLED_OE" "" "TRI or OPNDRN buffers permanently enabled" { { "Warning" "WMLS_MLS_NODE_NAME" "GPIO_0\[33\]~synth " "Node \"GPIO_0\[33\]~synth\"" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13010 "Node \"%1!s!\"" 0 0 "" 0 -1 1393811642276 ""} { "Warning" "WMLS_MLS_NODE_NAME" "GPIO_1\[0\]~synth " "Node \"GPIO_1\[0\]~synth\"" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13010 "Node \"%1!s!\"" 0 0 "" 0 -1 1393811642276 ""} { "Warning" "WMLS_MLS_NODE_NAME" "GPIO_1\[33\]~synth " "Node \"GPIO_1\[33\]~synth\"" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13010 "Node \"%1!s!\"" 0 0 "" 0 -1 1393811642276 ""} } { } 0 13009 "TRI or OPNDRN buffers permanently enabled" 0 0 "" 0 -1 1393811642276 ""} -{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "DRAM_CKE VCC " "Pin \"DRAM_CKE\" is stuck at VCC" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 62 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1 1393811642276 "|de0_nano_system|DRAM_CKE"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "" 0 -1 1393811642276 ""} -{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING_ON_PARTITION" "Top " "Timing-Driven Synthesis is running on partition \"Top\"" { } { } 0 286031 "Timing-Driven Synthesis is running on partition \"%1!s!\"" 0 0 "" 0 -1 1393811642836 ""} -{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "378 " "378 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "" 0 -1 1393811645576 ""} -{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "1 0 1 0 0 " "Adding 1 node(s), including 0 DDIO, 1 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "" 0 -1 1393811646966 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "" 0 -1 1393811646966 ""} -{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "1 " "Design contains 1 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[0\] " "No output dependent on input pin \"KEY\[0\]\"" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 74 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1 1393811647616 "|de0_nano_system|KEY[0]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0 -1 1393811647616 ""} -{ "Info" "ICUT_CUT_TM_SUMMARY" "5737 " "Implemented 5737 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "10 " "Implemented 10 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "" 0 -1 1393811647616 ""} { "Info" "ICUT_CUT_TM_OPINS" "32 " "Implemented 32 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "" 0 -1 1393811647616 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "84 " "Implemented 84 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "" 0 -1 1393811647616 ""} { "Info" "ICUT_CUT_TM_LCELLS" "5342 " "Implemented 5342 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "" 0 -1 1393811647616 ""} { "Info" "ICUT_CUT_TM_RAMS" "263 " "Implemented 263 RAM segments" { } { } 0 21064 "Implemented %1!d! RAM segments" 0 0 "" 0 -1 1393811647616 ""} { "Info" "ICUT_CUT_TM_PLLS" "1 " "Implemented 1 PLLs" { } { } 0 21065 "Implemented %1!d! PLLs" 0 0 "" 0 -1 1393811647616 ""} { "Info" "ICUT_CUT_TM_DSP_ELEM" "4 " "Implemented 4 DSP elements" { } { } 0 21062 "Implemented %1!d! DSP elements" 0 0 "" 0 -1 1393811647616 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1 1393811647616 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 130 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 130 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "644 " "Peak virtual memory: 644 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1 1393811647746 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Mar 02 18:54:07 2014 " "Processing ended: Sun Mar 02 18:54:07 2014" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1 1393811647746 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:23 " "Elapsed time: 00:00:23" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1 1393811647746 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:22 " "Total CPU time (on all processors): 00:00:22" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1 1393811647746 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1 1393811647746 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1 1393888317445 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Full Version " "Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1 1393888317445 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 03 16:11:57 2014 " "Processing started: Mon Mar 03 16:11:57 2014" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1 1393888317445 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1 1393888317445 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off de0_nano_system -c de0_nano_system " "Command: quartus_map --read_settings_files=on --write_settings_files=off de0_nano_system -c de0_nano_system" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1 1393888317445 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." { } { } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "" 0 -1 1393888317820 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "de0_nano_system.vhd 2 1 " "Found 2 design units, including 1 entities, in source file de0_nano_system.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 de0_nano_system-syn " "Found design unit 1: de0_nano_system-syn" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 86 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1 1393888318281 ""} { "Info" "ISGN_ENTITY_NAME" "1 de0_nano_system " "Found entity 1: de0_nano_system" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 55 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888318281 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393888318281 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "heartbeat.vhd 2 1 " "Found 2 design units, including 1 entities, in source file heartbeat.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 heartbeat-syn " "Found design unit 1: heartbeat-syn" { } { { "heartbeat.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/heartbeat.vhd" 61 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1 1393888318283 ""} { "Info" "ISGN_ENTITY_NAME" "1 heartbeat " "Found entity 1: heartbeat" { } { { "heartbeat.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/heartbeat.vhd" 49 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888318283 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393888318283 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/system.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/system.v" { { "Info" "ISGN_ENTITY_NAME" "1 system " "Found entity 1: system" { } { { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 6 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888318297 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393888318297 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_irq_mapper.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_irq_mapper.sv" { { "Info" "ISGN_ENTITY_NAME" "1 system_irq_mapper " "Found entity 1: system_irq_mapper" { } { { "system/synthesis/submodules/system_irq_mapper.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_irq_mapper.sv" 31 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888318299 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393888318299 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_merlin_width_adapter.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_width_adapter.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_width_adapter " "Found entity 1: altera_merlin_width_adapter" { } { { "system/synthesis/submodules/altera_merlin_width_adapter.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_width_adapter.sv" 25 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888318304 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393888318304 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_merlin_burst_uncompressor.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_burst_uncompressor.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_burst_uncompressor " "Found entity 1: altera_merlin_burst_uncompressor" { } { { "system/synthesis/submodules/altera_merlin_burst_uncompressor.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_burst_uncompressor.sv" 40 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888318306 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393888318306 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_merlin_address_alignment.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_address_alignment.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_address_alignment " "Found entity 1: altera_merlin_address_alignment" { } { { "system/synthesis/submodules/altera_merlin_address_alignment.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_address_alignment.sv" 26 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888318308 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393888318308 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_merlin_arbitrator.sv 2 2 " "Found 2 design units, including 2 entities, in source file system/synthesis/submodules/altera_merlin_arbitrator.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_arbitrator " "Found entity 1: altera_merlin_arbitrator" { } { { "system/synthesis/submodules/altera_merlin_arbitrator.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_arbitrator.sv" 103 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888318311 ""} { "Info" "ISGN_ENTITY_NAME" "2 altera_merlin_arb_adder " "Found entity 2: altera_merlin_arb_adder" { } { { "system/synthesis/submodules/altera_merlin_arbitrator.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_arbitrator.sv" 228 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888318311 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393888318311 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_rsp_xbar_mux_001.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_rsp_xbar_mux_001.sv" { { "Info" "ISGN_ENTITY_NAME" "1 system_rsp_xbar_mux_001 " "Found entity 1: system_rsp_xbar_mux_001" { } { { "system/synthesis/submodules/system_rsp_xbar_mux_001.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_rsp_xbar_mux_001.sv" 38 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888318314 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393888318314 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_rsp_xbar_mux.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_rsp_xbar_mux.sv" { { "Info" "ISGN_ENTITY_NAME" "1 system_rsp_xbar_mux " "Found entity 1: system_rsp_xbar_mux" { } { { "system/synthesis/submodules/system_rsp_xbar_mux.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_rsp_xbar_mux.sv" 38 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888318316 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393888318316 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_rsp_xbar_demux_002.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_rsp_xbar_demux_002.sv" { { "Info" "ISGN_ENTITY_NAME" "1 system_rsp_xbar_demux_002 " "Found entity 1: system_rsp_xbar_demux_002" { } { { "system/synthesis/submodules/system_rsp_xbar_demux_002.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_rsp_xbar_demux_002.sv" 43 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888318318 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393888318318 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_rsp_xbar_demux.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_rsp_xbar_demux.sv" { { "Info" "ISGN_ENTITY_NAME" "1 system_rsp_xbar_demux " "Found entity 1: system_rsp_xbar_demux" { } { { "system/synthesis/submodules/system_rsp_xbar_demux.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_rsp_xbar_demux.sv" 43 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888318320 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393888318320 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_cmd_xbar_mux.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_cmd_xbar_mux.sv" { { "Info" "ISGN_ENTITY_NAME" "1 system_cmd_xbar_mux " "Found entity 1: system_cmd_xbar_mux" { } { { "system/synthesis/submodules/system_cmd_xbar_mux.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cmd_xbar_mux.sv" 38 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888318322 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393888318322 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_cmd_xbar_demux_001.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_cmd_xbar_demux_001.sv" { { "Info" "ISGN_ENTITY_NAME" "1 system_cmd_xbar_demux_001 " "Found entity 1: system_cmd_xbar_demux_001" { } { { "system/synthesis/submodules/system_cmd_xbar_demux_001.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cmd_xbar_demux_001.sv" 43 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888318325 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393888318325 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_cmd_xbar_demux.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_cmd_xbar_demux.sv" { { "Info" "ISGN_ENTITY_NAME" "1 system_cmd_xbar_demux " "Found entity 1: system_cmd_xbar_demux" { } { { "system/synthesis/submodules/system_cmd_xbar_demux.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cmd_xbar_demux.sv" 43 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888318327 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393888318327 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_reset_controller.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_reset_controller.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_reset_controller " "Found entity 1: altera_reset_controller" { } { { "system/synthesis/submodules/altera_reset_controller.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_reset_controller.v" 28 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888318329 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393888318329 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_reset_synchronizer.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_reset_synchronizer.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_reset_synchronizer " "Found entity 1: altera_reset_synchronizer" { } { { "system/synthesis/submodules/altera_reset_synchronizer.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_reset_synchronizer.v" 24 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888318331 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393888318331 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_merlin_burst_adapter.sv 7 7 " "Found 7 design units, including 7 entities, in source file system/synthesis/submodules/altera_merlin_burst_adapter.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_burst_adapter_burstwrap_increment " "Found entity 1: altera_merlin_burst_adapter_burstwrap_increment" { } { { "system/synthesis/submodules/altera_merlin_burst_adapter.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_burst_adapter.sv" 40 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888318336 ""} { "Info" "ISGN_ENTITY_NAME" "2 altera_merlin_burst_adapter_adder " "Found entity 2: altera_merlin_burst_adapter_adder" { } { { "system/synthesis/submodules/altera_merlin_burst_adapter.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_burst_adapter.sv" 55 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888318336 ""} { "Info" "ISGN_ENTITY_NAME" "3 altera_merlin_burst_adapter_subtractor " "Found entity 3: altera_merlin_burst_adapter_subtractor" { } { { "system/synthesis/submodules/altera_merlin_burst_adapter.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_burst_adapter.sv" 77 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888318336 ""} { "Info" "ISGN_ENTITY_NAME" "4 altera_merlin_burst_adapter_min " "Found entity 4: altera_merlin_burst_adapter_min" { } { { "system/synthesis/submodules/altera_merlin_burst_adapter.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_burst_adapter.sv" 98 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888318336 ""} { "Info" "ISGN_ENTITY_NAME" "5 altera_merlin_burst_adapter " "Found entity 5: altera_merlin_burst_adapter" { } { { "system/synthesis/submodules/altera_merlin_burst_adapter.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_burst_adapter.sv" 264 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888318336 ""} { "Info" "ISGN_ENTITY_NAME" "6 altera_merlin_burst_adapter_uncompressed_only " "Found entity 6: altera_merlin_burst_adapter_uncompressed_only" { } { { "system/synthesis/submodules/altera_merlin_burst_adapter.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_burst_adapter.sv" 414 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888318336 ""} { "Info" "ISGN_ENTITY_NAME" "7 altera_merlin_burst_adapter_full " "Found entity 7: altera_merlin_burst_adapter_full" { } { { "system/synthesis/submodules/altera_merlin_burst_adapter.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_burst_adapter.sv" 468 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888318336 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393888318336 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_merlin_traffic_limiter.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_traffic_limiter.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_traffic_limiter " "Found entity 1: altera_merlin_traffic_limiter" { } { { "system/synthesis/submodules/altera_merlin_traffic_limiter.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_traffic_limiter.sv" 44 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888318340 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393888318340 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_avalon_st_pipeline_base.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_avalon_st_pipeline_base.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_avalon_st_pipeline_base " "Found entity 1: altera_avalon_st_pipeline_base" { } { { "system/synthesis/submodules/altera_avalon_st_pipeline_base.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_avalon_st_pipeline_base.v" 22 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888318342 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393888318342 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_id_router_002.sv 2 2 " "Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_id_router_002.sv" { { "Info" "ISGN_ENTITY_NAME" "1 system_id_router_002_default_decode " "Found entity 1: system_id_router_002_default_decode" { } { { "system/synthesis/submodules/system_id_router_002.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_id_router_002.sv" 32 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888318345 ""} { "Info" "ISGN_ENTITY_NAME" "2 system_id_router_002 " "Found entity 2: system_id_router_002" { } { { "system/synthesis/submodules/system_id_router_002.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_id_router_002.sv" 54 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888318345 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393888318345 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_id_router_001.sv 2 2 " "Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_id_router_001.sv" { { "Info" "ISGN_ENTITY_NAME" "1 system_id_router_001_default_decode " "Found entity 1: system_id_router_001_default_decode" { } { { "system/synthesis/submodules/system_id_router_001.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_id_router_001.sv" 32 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888318347 ""} { "Info" "ISGN_ENTITY_NAME" "2 system_id_router_001 " "Found entity 2: system_id_router_001" { } { { "system/synthesis/submodules/system_id_router_001.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_id_router_001.sv" 54 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888318347 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393888318347 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_id_router.sv 2 2 " "Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_id_router.sv" { { "Info" "ISGN_ENTITY_NAME" "1 system_id_router_default_decode " "Found entity 1: system_id_router_default_decode" { } { { "system/synthesis/submodules/system_id_router.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_id_router.sv" 32 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888318350 ""} { "Info" "ISGN_ENTITY_NAME" "2 system_id_router " "Found entity 2: system_id_router" { } { { "system/synthesis/submodules/system_id_router.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_id_router.sv" 54 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888318350 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393888318350 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_addr_router_001.sv 2 2 " "Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_addr_router_001.sv" { { "Info" "ISGN_ENTITY_NAME" "1 system_addr_router_001_default_decode " "Found entity 1: system_addr_router_001_default_decode" { } { { "system/synthesis/submodules/system_addr_router_001.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_addr_router_001.sv" 32 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888318352 ""} { "Info" "ISGN_ENTITY_NAME" "2 system_addr_router_001 " "Found entity 2: system_addr_router_001" { } { { "system/synthesis/submodules/system_addr_router_001.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_addr_router_001.sv" 54 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888318352 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393888318352 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_addr_router.sv 2 2 " "Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_addr_router.sv" { { "Info" "ISGN_ENTITY_NAME" "1 system_addr_router_default_decode " "Found entity 1: system_addr_router_default_decode" { } { { "system/synthesis/submodules/system_addr_router.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_addr_router.sv" 32 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888318355 ""} { "Info" "ISGN_ENTITY_NAME" "2 system_addr_router " "Found entity 2: system_addr_router" { } { { "system/synthesis/submodules/system_addr_router.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_addr_router.sv" 54 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888318355 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393888318355 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_avalon_sc_fifo.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_avalon_sc_fifo.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_avalon_sc_fifo " "Found entity 1: altera_avalon_sc_fifo" { } { { "system/synthesis/submodules/altera_avalon_sc_fifo.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_avalon_sc_fifo.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888318359 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393888318359 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_merlin_slave_agent.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_slave_agent.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_slave_agent " "Found entity 1: altera_merlin_slave_agent" { } { { "system/synthesis/submodules/altera_merlin_slave_agent.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_slave_agent.sv" 34 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888318362 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393888318362 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_merlin_master_agent.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_master_agent.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_master_agent " "Found entity 1: altera_merlin_master_agent" { } { { "system/synthesis/submodules/altera_merlin_master_agent.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_master_agent.sv" 28 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888318364 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393888318364 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_merlin_slave_translator.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_slave_translator.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_slave_translator " "Found entity 1: altera_merlin_slave_translator" { } { { "system/synthesis/submodules/altera_merlin_slave_translator.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_slave_translator.sv" 35 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888318367 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393888318367 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_merlin_master_translator.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_master_translator.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_master_translator " "Found entity 1: altera_merlin_master_translator" { } { { "system/synthesis/submodules/altera_merlin_master_translator.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_master_translator.sv" 30 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888318370 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393888318370 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_up_rs232_counters.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_up_rs232_counters.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_up_rs232_counters " "Found entity 1: altera_up_rs232_counters" { } { { "system/synthesis/submodules/altera_up_rs232_counters.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_up_rs232_counters.v" 48 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888318372 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393888318372 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_up_rs232_in_deserializer.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_up_rs232_in_deserializer.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_up_rs232_in_deserializer " "Found entity 1: altera_up_rs232_in_deserializer" { } { { "system/synthesis/submodules/altera_up_rs232_in_deserializer.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_up_rs232_in_deserializer.v" 47 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888318375 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393888318375 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_up_rs232_out_serializer.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_up_rs232_out_serializer.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_up_rs232_out_serializer " "Found entity 1: altera_up_rs232_out_serializer" { } { { "system/synthesis/submodules/altera_up_rs232_out_serializer.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_up_rs232_out_serializer.v" 47 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888318377 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393888318377 ""} +{ "Warning" "WVRFX_L2_VERI_INGORE_DANGLING_COMMA" "altera_up_sync_fifo.v(157) " "Verilog HDL Module Instantiation warning at altera_up_sync_fifo.v(157): ignored dangling comma in List of Port Connections" { } { { "system/synthesis/submodules/altera_up_sync_fifo.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_up_sync_fifo.v" 157 0 0 } } } 0 10275 "Verilog HDL Module Instantiation warning at %1!s!: ignored dangling comma in List of Port Connections" 0 0 "" 0 -1 1393888318379 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_up_sync_fifo.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_up_sync_fifo.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_up_sync_fifo " "Found entity 1: altera_up_sync_fifo" { } { { "system/synthesis/submodules/altera_up_sync_fifo.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_up_sync_fifo.v" 47 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888318380 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393888318380 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_rs232_wifi.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_rs232_wifi.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_rs232_wifi " "Found entity 1: system_rs232_wifi" { } { { "system/synthesis/submodules/system_rs232_wifi.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_rs232_wifi.v" 48 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888318382 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393888318382 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_uart_mc.v 7 7 " "Found 7 design units, including 7 entities, in source file system/synthesis/submodules/system_uart_mc.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_uart_mc_log_module " "Found entity 1: system_uart_mc_log_module" { } { { "system/synthesis/submodules/system_uart_mc.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_mc.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888318387 ""} { "Info" "ISGN_ENTITY_NAME" "2 system_uart_mc_tx " "Found entity 2: system_uart_mc_tx" { } { { "system/synthesis/submodules/system_uart_mc.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_mc.v" 66 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888318387 ""} { "Info" "ISGN_ENTITY_NAME" "3 system_uart_mc_rx_stimulus_source_character_source_rom_module " "Found entity 3: system_uart_mc_rx_stimulus_source_character_source_rom_module" { } { { "system/synthesis/submodules/system_uart_mc.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_mc.v" 238 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888318387 ""} { "Info" "ISGN_ENTITY_NAME" "4 system_uart_mc_rx_stimulus_source " "Found entity 4: system_uart_mc_rx_stimulus_source" { } { { "system/synthesis/submodules/system_uart_mc.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_mc.v" 387 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888318387 ""} { "Info" "ISGN_ENTITY_NAME" "5 system_uart_mc_rx " "Found entity 5: system_uart_mc_rx" { } { { "system/synthesis/submodules/system_uart_mc.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_mc.v" 492 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888318387 ""} { "Info" "ISGN_ENTITY_NAME" "6 system_uart_mc_regs " "Found entity 6: system_uart_mc_regs" { } { { "system/synthesis/submodules/system_uart_mc.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_mc.v" 750 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888318387 ""} { "Info" "ISGN_ENTITY_NAME" "7 system_uart_mc " "Found entity 7: system_uart_mc" { } { { "system/synthesis/submodules/system_uart_mc.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_mc.v" 995 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888318387 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393888318387 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_pio_ir_emitter.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_pio_ir_emitter.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_pio_ir_emitter " "Found entity 1: system_pio_ir_emitter" { } { { "system/synthesis/submodules/system_pio_ir_emitter.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_pio_ir_emitter.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888318389 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393888318389 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_jtag_uart_0.v 7 7 " "Found 7 design units, including 7 entities, in source file system/synthesis/submodules/system_jtag_uart_0.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_jtag_uart_0_log_module " "Found entity 1: system_jtag_uart_0_log_module" { } { { "system/synthesis/submodules/system_jtag_uart_0.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_jtag_uart_0.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888318394 ""} { "Info" "ISGN_ENTITY_NAME" "2 system_jtag_uart_0_sim_scfifo_w " "Found entity 2: system_jtag_uart_0_sim_scfifo_w" { } { { "system/synthesis/submodules/system_jtag_uart_0.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_jtag_uart_0.v" 65 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888318394 ""} { "Info" "ISGN_ENTITY_NAME" "3 system_jtag_uart_0_scfifo_w " "Found entity 3: system_jtag_uart_0_scfifo_w" { } { { "system/synthesis/submodules/system_jtag_uart_0.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_jtag_uart_0.v" 123 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888318394 ""} { "Info" "ISGN_ENTITY_NAME" "4 system_jtag_uart_0_drom_module " "Found entity 4: system_jtag_uart_0_drom_module" { } { { "system/synthesis/submodules/system_jtag_uart_0.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_jtag_uart_0.v" 208 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888318394 ""} { "Info" "ISGN_ENTITY_NAME" "5 system_jtag_uart_0_sim_scfifo_r " "Found entity 5: system_jtag_uart_0_sim_scfifo_r" { } { { "system/synthesis/submodules/system_jtag_uart_0.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_jtag_uart_0.v" 362 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888318394 ""} { "Info" "ISGN_ENTITY_NAME" "6 system_jtag_uart_0_scfifo_r " "Found entity 6: system_jtag_uart_0_scfifo_r" { } { { "system/synthesis/submodules/system_jtag_uart_0.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_jtag_uart_0.v" 450 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888318394 ""} { "Info" "ISGN_ENTITY_NAME" "7 system_jtag_uart_0 " "Found entity 7: system_jtag_uart_0" { } { { "system/synthesis/submodules/system_jtag_uart_0.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_jtag_uart_0.v" 537 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888318394 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393888318394 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_pio_sw.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_pio_sw.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_pio_sw " "Found entity 1: system_pio_sw" { } { { "system/synthesis/submodules/system_pio_sw.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_pio_sw.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888318397 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393888318397 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_pio_key_left.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_pio_key_left.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_pio_key_left " "Found entity 1: system_pio_key_left" { } { { "system/synthesis/submodules/system_pio_key_left.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_pio_key_left.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888318399 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393888318399 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_pio_led.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_pio_led.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_pio_led " "Found entity 1: system_pio_led" { } { { "system/synthesis/submodules/system_pio_led.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_pio_led.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888318401 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393888318401 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_uart_wifi.v 7 7 " "Found 7 design units, including 7 entities, in source file system/synthesis/submodules/system_uart_wifi.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_uart_wifi_log_module " "Found entity 1: system_uart_wifi_log_module" { } { { "system/synthesis/submodules/system_uart_wifi.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_wifi.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888318407 ""} { "Info" "ISGN_ENTITY_NAME" "2 system_uart_wifi_tx " "Found entity 2: system_uart_wifi_tx" { } { { "system/synthesis/submodules/system_uart_wifi.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_wifi.v" 66 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888318407 ""} { "Info" "ISGN_ENTITY_NAME" "3 system_uart_wifi_rx_stimulus_source_character_source_rom_module " "Found entity 3: system_uart_wifi_rx_stimulus_source_character_source_rom_module" { } { { "system/synthesis/submodules/system_uart_wifi.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_wifi.v" 238 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888318407 ""} { "Info" "ISGN_ENTITY_NAME" "4 system_uart_wifi_rx_stimulus_source " "Found entity 4: system_uart_wifi_rx_stimulus_source" { } { { "system/synthesis/submodules/system_uart_wifi.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_wifi.v" 387 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888318407 ""} { "Info" "ISGN_ENTITY_NAME" "5 system_uart_wifi_rx " "Found entity 5: system_uart_wifi_rx" { } { { "system/synthesis/submodules/system_uart_wifi.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_wifi.v" 492 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888318407 ""} { "Info" "ISGN_ENTITY_NAME" "6 system_uart_wifi_regs " "Found entity 6: system_uart_wifi_regs" { } { { "system/synthesis/submodules/system_uart_wifi.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_wifi.v" 750 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888318407 ""} { "Info" "ISGN_ENTITY_NAME" "7 system_uart_wifi " "Found entity 7: system_uart_wifi" { } { { "system/synthesis/submodules/system_uart_wifi.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_wifi.v" 1006 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888318407 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393888318407 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_sys_clk_timer.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_sys_clk_timer.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_sys_clk_timer " "Found entity 1: system_sys_clk_timer" { } { { "system/synthesis/submodules/system_sys_clk_timer.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_sys_clk_timer.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888318410 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393888318410 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_sdram.v 2 2 " "Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_sdram.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_sdram_input_efifo_module " "Found entity 1: system_sdram_input_efifo_module" { } { { "system/synthesis/submodules/system_sdram.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_sdram.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888318414 ""} { "Info" "ISGN_ENTITY_NAME" "2 system_sdram " "Found entity 2: system_sdram" { } { { "system/synthesis/submodules/system_sdram.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_sdram.v" 158 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888318414 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393888318414 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_sysid.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_sysid.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_sysid " "Found entity 1: system_sysid" { } { { "system/synthesis/submodules/system_sysid.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_sysid.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888318416 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393888318416 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_cpu.v 28 28 " "Found 28 design units, including 28 entities, in source file system/synthesis/submodules/system_cpu.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_cpu_ic_data_module " "Found entity 1: system_cpu_ic_data_module" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888319833 ""} { "Info" "ISGN_ENTITY_NAME" "2 system_cpu_ic_tag_module " "Found entity 2: system_cpu_ic_tag_module" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 86 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888319833 ""} { "Info" "ISGN_ENTITY_NAME" "3 system_cpu_bht_module " "Found entity 3: system_cpu_bht_module" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 152 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888319833 ""} { "Info" "ISGN_ENTITY_NAME" "4 system_cpu_register_bank_a_module " "Found entity 4: system_cpu_register_bank_a_module" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 218 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888319833 ""} { "Info" "ISGN_ENTITY_NAME" "5 system_cpu_register_bank_b_module " "Found entity 5: system_cpu_register_bank_b_module" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 281 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888319833 ""} { "Info" "ISGN_ENTITY_NAME" "6 system_cpu_dc_tag_module " "Found entity 6: system_cpu_dc_tag_module" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 344 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888319833 ""} { "Info" "ISGN_ENTITY_NAME" "7 system_cpu_dc_data_module " "Found entity 7: system_cpu_dc_data_module" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 407 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888319833 ""} { "Info" "ISGN_ENTITY_NAME" "8 system_cpu_dc_victim_module " "Found entity 8: system_cpu_dc_victim_module" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 473 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888319833 ""} { "Info" "ISGN_ENTITY_NAME" "9 system_cpu_nios2_oci_debug " "Found entity 9: system_cpu_nios2_oci_debug" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 538 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888319833 ""} { "Info" "ISGN_ENTITY_NAME" "10 system_cpu_ociram_lpm_dram_bdp_component_module " "Found entity 10: system_cpu_ociram_lpm_dram_bdp_component_module" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 666 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888319833 ""} { "Info" "ISGN_ENTITY_NAME" "11 system_cpu_nios2_ocimem " "Found entity 11: system_cpu_nios2_ocimem" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 759 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888319833 ""} { "Info" "ISGN_ENTITY_NAME" "12 system_cpu_nios2_avalon_reg " "Found entity 12: system_cpu_nios2_avalon_reg" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 905 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888319833 ""} { "Info" "ISGN_ENTITY_NAME" "13 system_cpu_nios2_oci_break " "Found entity 13: system_cpu_nios2_oci_break" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 999 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888319833 ""} { "Info" "ISGN_ENTITY_NAME" "14 system_cpu_nios2_oci_xbrk " "Found entity 14: system_cpu_nios2_oci_xbrk" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 1293 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888319833 ""} { "Info" "ISGN_ENTITY_NAME" "15 system_cpu_nios2_oci_dbrk " "Found entity 15: system_cpu_nios2_oci_dbrk" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 1553 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888319833 ""} { "Info" "ISGN_ENTITY_NAME" "16 system_cpu_nios2_oci_itrace " "Found entity 16: system_cpu_nios2_oci_itrace" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 1741 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888319833 ""} { "Info" "ISGN_ENTITY_NAME" "17 system_cpu_nios2_oci_td_mode " "Found entity 17: system_cpu_nios2_oci_td_mode" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 2098 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888319833 ""} { "Info" "ISGN_ENTITY_NAME" "18 system_cpu_nios2_oci_dtrace " "Found entity 18: system_cpu_nios2_oci_dtrace" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 2165 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888319833 ""} { "Info" "ISGN_ENTITY_NAME" "19 system_cpu_nios2_oci_compute_tm_count " "Found entity 19: system_cpu_nios2_oci_compute_tm_count" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 2259 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888319833 ""} { "Info" "ISGN_ENTITY_NAME" "20 system_cpu_nios2_oci_fifowp_inc " "Found entity 20: system_cpu_nios2_oci_fifowp_inc" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 2330 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888319833 ""} { "Info" "ISGN_ENTITY_NAME" "21 system_cpu_nios2_oci_fifocount_inc " "Found entity 21: system_cpu_nios2_oci_fifocount_inc" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 2372 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888319833 ""} { "Info" "ISGN_ENTITY_NAME" "22 system_cpu_nios2_oci_fifo " "Found entity 22: system_cpu_nios2_oci_fifo" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 2418 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888319833 ""} { "Info" "ISGN_ENTITY_NAME" "23 system_cpu_nios2_oci_pib " "Found entity 23: system_cpu_nios2_oci_pib" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 2923 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888319833 ""} { "Info" "ISGN_ENTITY_NAME" "24 system_cpu_traceram_lpm_dram_bdp_component_module " "Found entity 24: system_cpu_traceram_lpm_dram_bdp_component_module" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 2991 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888319833 ""} { "Info" "ISGN_ENTITY_NAME" "25 system_cpu_nios2_oci_im " "Found entity 25: system_cpu_nios2_oci_im" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3080 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888319833 ""} { "Info" "ISGN_ENTITY_NAME" "26 system_cpu_nios2_performance_monitors " "Found entity 26: system_cpu_nios2_performance_monitors" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3217 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888319833 ""} { "Info" "ISGN_ENTITY_NAME" "27 system_cpu_nios2_oci " "Found entity 27: system_cpu_nios2_oci" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3233 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888319833 ""} { "Info" "ISGN_ENTITY_NAME" "28 system_cpu " "Found entity 28: system_cpu" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3736 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888319833 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393888319833 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_cpu_jtag_debug_module_sysclk.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_cpu_jtag_debug_module_sysclk.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_cpu_jtag_debug_module_sysclk " "Found entity 1: system_cpu_jtag_debug_module_sysclk" { } { { "system/synthesis/submodules/system_cpu_jtag_debug_module_sysclk.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu_jtag_debug_module_sysclk.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888319837 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393888319837 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_cpu_jtag_debug_module_tck.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_cpu_jtag_debug_module_tck.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_cpu_jtag_debug_module_tck " "Found entity 1: system_cpu_jtag_debug_module_tck" { } { { "system/synthesis/submodules/system_cpu_jtag_debug_module_tck.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu_jtag_debug_module_tck.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888319840 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393888319840 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_cpu_jtag_debug_module_wrapper " "Found entity 1: system_cpu_jtag_debug_module_wrapper" { } { { "system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888319843 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393888319843 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_cpu_mult_cell.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_cpu_mult_cell.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_cpu_mult_cell " "Found entity 1: system_cpu_mult_cell" { } { { "system/synthesis/submodules/system_cpu_mult_cell.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu_mult_cell.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888319846 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393888319846 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_cpu_oci_test_bench.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_cpu_oci_test_bench.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_cpu_oci_test_bench " "Found entity 1: system_cpu_oci_test_bench" { } { { "system/synthesis/submodules/system_cpu_oci_test_bench.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu_oci_test_bench.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888319848 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393888319848 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_cpu_test_bench.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_cpu_test_bench.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_cpu_test_bench " "Found entity 1: system_cpu_test_bench" { } { { "system/synthesis/submodules/system_cpu_test_bench.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu_test_bench.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888319852 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393888319852 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pll_sys.vhd 2 1 " "Found 2 design units, including 1 entities, in source file pll_sys.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 pll_sys-SYN " "Found design unit 1: pll_sys-SYN" { } { { "pll_sys.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/pll_sys.vhd" 54 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1 1393888319854 ""} { "Info" "ISGN_ENTITY_NAME" "1 pll_sys " "Found entity 1: pll_sys" { } { { "pll_sys.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/pll_sys.vhd" 42 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888319854 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393888319854 ""} +{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "system_cpu.v(2066) " "Verilog HDL or VHDL warning at system_cpu.v(2066): conditional expression evaluates to a constant" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 2066 0 0 } } } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1 1393888319878 ""} +{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "system_cpu.v(2068) " "Verilog HDL or VHDL warning at system_cpu.v(2068): conditional expression evaluates to a constant" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 2068 0 0 } } } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1 1393888319878 ""} +{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "system_cpu.v(2224) " "Verilog HDL or VHDL warning at system_cpu.v(2224): conditional expression evaluates to a constant" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 2224 0 0 } } } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1 1393888319879 ""} +{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "system_cpu.v(3143) " "Verilog HDL or VHDL warning at system_cpu.v(3143): conditional expression evaluates to a constant" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3143 0 0 } } } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1 1393888319882 ""} +{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "system_sdram.v(316) " "Verilog HDL or VHDL warning at system_sdram.v(316): conditional expression evaluates to a constant" { } { { "system/synthesis/submodules/system_sdram.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_sdram.v" 316 0 0 } } } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1 1393888319890 ""} +{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "system_sdram.v(326) " "Verilog HDL or VHDL warning at system_sdram.v(326): conditional expression evaluates to a constant" { } { { "system/synthesis/submodules/system_sdram.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_sdram.v" 326 0 0 } } } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1 1393888319890 ""} +{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "system_sdram.v(336) " "Verilog HDL or VHDL warning at system_sdram.v(336): conditional expression evaluates to a constant" { } { { "system/synthesis/submodules/system_sdram.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_sdram.v" 336 0 0 } } } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1 1393888319890 ""} +{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "system_sdram.v(680) " "Verilog HDL or VHDL warning at system_sdram.v(680): conditional expression evaluates to a constant" { } { { "system/synthesis/submodules/system_sdram.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_sdram.v" 680 0 0 } } } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1 1393888319892 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "de0_nano_system " "Elaborating entity \"de0_nano_system\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1 1393888320047 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pll_sys pll_sys:inst_pll_sys " "Elaborating entity \"pll_sys\" for hierarchy \"pll_sys:inst_pll_sys\"" { } { { "de0_nano_system.vhd" "inst_pll_sys" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 152 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888320051 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll pll_sys:inst_pll_sys\|altpll:altpll_component " "Elaborating entity \"altpll\" for hierarchy \"pll_sys:inst_pll_sys\|altpll:altpll_component\"" { } { { "pll_sys.vhd" "altpll_component" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/pll_sys.vhd" 154 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888320101 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "pll_sys:inst_pll_sys\|altpll:altpll_component " "Elaborated megafunction instantiation \"pll_sys:inst_pll_sys\|altpll:altpll_component\"" { } { { "pll_sys.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/pll_sys.vhd" 154 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1393888320105 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "pll_sys:inst_pll_sys\|altpll:altpll_component " "Instantiated megafunction \"pll_sys:inst_pll_sys\|altpll:altpll_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "bandwidth_type AUTO " "Parameter \"bandwidth_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320109 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_divide_by 1 " "Parameter \"clk0_divide_by\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320109 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_duty_cycle 50 " "Parameter \"clk0_duty_cycle\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320109 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_multiply_by 2 " "Parameter \"clk0_multiply_by\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320109 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_phase_shift 0 " "Parameter \"clk0_phase_shift\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320109 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_divide_by 1 " "Parameter \"clk1_divide_by\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320109 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_duty_cycle 50 " "Parameter \"clk1_duty_cycle\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320109 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_multiply_by 2 " "Parameter \"clk1_multiply_by\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320109 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_phase_shift -1500 " "Parameter \"clk1_phase_shift\" = \"-1500\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320109 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_divide_by 5 " "Parameter \"clk2_divide_by\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320109 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_duty_cycle 50 " "Parameter \"clk2_duty_cycle\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320109 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_multiply_by 1 " "Parameter \"clk2_multiply_by\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320109 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_phase_shift 0 " "Parameter \"clk2_phase_shift\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320109 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "compensate_clock CLK0 " "Parameter \"compensate_clock\" = \"CLK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320109 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "inclk0_input_frequency 20000 " "Parameter \"inclk0_input_frequency\" = \"20000\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320109 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320109 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint CBX_MODULE_PREFIX=pll_sys " "Parameter \"lpm_hint\" = \"CBX_MODULE_PREFIX=pll_sys\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320109 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altpll " "Parameter \"lpm_type\" = \"altpll\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320109 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode NORMAL " "Parameter \"operation_mode\" = \"NORMAL\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320109 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_type AUTO " "Parameter \"pll_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320109 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_activeclock PORT_UNUSED " "Parameter \"port_activeclock\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320109 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_areset PORT_UNUSED " "Parameter \"port_areset\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320109 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad0 PORT_UNUSED " "Parameter \"port_clkbad0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320109 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad1 PORT_UNUSED " "Parameter \"port_clkbad1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320109 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkloss PORT_UNUSED " "Parameter \"port_clkloss\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320109 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkswitch PORT_UNUSED " "Parameter \"port_clkswitch\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320109 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_configupdate PORT_UNUSED " "Parameter \"port_configupdate\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320109 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_fbin PORT_UNUSED " "Parameter \"port_fbin\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320109 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk0 PORT_USED " "Parameter \"port_inclk0\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320109 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk1 PORT_UNUSED " "Parameter \"port_inclk1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320109 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_locked PORT_USED " "Parameter \"port_locked\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320109 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pfdena PORT_UNUSED " "Parameter \"port_pfdena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320109 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasecounterselect PORT_UNUSED " "Parameter \"port_phasecounterselect\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320109 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasedone PORT_UNUSED " "Parameter \"port_phasedone\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320109 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasestep PORT_UNUSED " "Parameter \"port_phasestep\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320109 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phaseupdown PORT_UNUSED " "Parameter \"port_phaseupdown\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320109 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pllena PORT_UNUSED " "Parameter \"port_pllena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320109 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanaclr PORT_UNUSED " "Parameter \"port_scanaclr\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320109 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclk PORT_UNUSED " "Parameter \"port_scanclk\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320109 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclkena PORT_UNUSED " "Parameter \"port_scanclkena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320109 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandata PORT_UNUSED " "Parameter \"port_scandata\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320109 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandataout PORT_UNUSED " "Parameter \"port_scandataout\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320109 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandone PORT_UNUSED " "Parameter \"port_scandone\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320109 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanread PORT_UNUSED " "Parameter \"port_scanread\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320109 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanwrite PORT_UNUSED " "Parameter \"port_scanwrite\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320109 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk0 PORT_USED " "Parameter \"port_clk0\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320109 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk1 PORT_USED " "Parameter \"port_clk1\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320109 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk2 PORT_USED " "Parameter \"port_clk2\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320109 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk3 PORT_UNUSED " "Parameter \"port_clk3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320109 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk4 PORT_UNUSED " "Parameter \"port_clk4\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320109 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk5 PORT_UNUSED " "Parameter \"port_clk5\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320109 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena0 PORT_UNUSED " "Parameter \"port_clkena0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320109 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena1 PORT_UNUSED " "Parameter \"port_clkena1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320109 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena2 PORT_UNUSED " "Parameter \"port_clkena2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320109 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena3 PORT_UNUSED " "Parameter \"port_clkena3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320109 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena4 PORT_UNUSED " "Parameter \"port_clkena4\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320109 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena5 PORT_UNUSED " "Parameter \"port_clkena5\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320109 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk0 PORT_UNUSED " "Parameter \"port_extclk0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320109 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk1 PORT_UNUSED " "Parameter \"port_extclk1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320109 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk2 PORT_UNUSED " "Parameter \"port_extclk2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320109 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk3 PORT_UNUSED " "Parameter \"port_extclk3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320109 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "self_reset_on_loss_lock ON " "Parameter \"self_reset_on_loss_lock\" = \"ON\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320109 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_clock 5 " "Parameter \"width_clock\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320109 ""} } { { "pll_sys.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/pll_sys.vhd" 154 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1393888320109 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/pll_sys_altpll.v 1 1 " "Found 1 design units, including 1 entities, in source file db/pll_sys_altpll.v" { { "Info" "ISGN_ENTITY_NAME" "1 pll_sys_altpll " "Found entity 1: pll_sys_altpll" { } { { "db/pll_sys_altpll.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/pll_sys_altpll.v" 29 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888320170 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393888320170 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pll_sys_altpll pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated " "Elaborating entity \"pll_sys_altpll\" for hierarchy \"pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\"" { } { { "altpll.tdf" "auto_generated" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altpll.tdf" 897 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888320173 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "heartbeat heartbeat:inst_heartbeat " "Elaborating entity \"heartbeat\" for hierarchy \"heartbeat:inst_heartbeat\"" { } { { "de0_nano_system.vhd" "inst_heartbeat" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 161 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888320177 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system system:inst_cpu " "Elaborating entity \"system\" for hierarchy \"system:inst_cpu\"" { } { { "de0_nano_system.vhd" "inst_cpu" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888320180 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu system:inst_cpu\|system_cpu:cpu " "Elaborating entity \"system_cpu\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\"" { } { { "system/synthesis/system.v" "cpu" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888320230 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_test_bench system:inst_cpu\|system_cpu:cpu\|system_cpu_test_bench:the_system_cpu_test_bench " "Elaborating entity \"system_cpu_test_bench\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_test_bench:the_system_cpu_test_bench\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_test_bench" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 6073 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888320266 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_ic_data_module system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_data_module:system_cpu_ic_data " "Elaborating entity \"system_cpu_ic_data_module\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_data_module:system_cpu_ic_data\"" { } { { "system/synthesis/submodules/system_cpu.v" "system_cpu_ic_data" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 7098 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888320268 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_data_module:system_cpu_ic_data\|altsyncram:the_altsyncram " "Elaborating entity \"altsyncram\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_data_module:system_cpu_ic_data\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_altsyncram" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 58 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888320299 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_data_module:system_cpu_ic_data\|altsyncram:the_altsyncram " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_data_module:system_cpu_ic_data\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 58 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1393888320301 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_data_module:system_cpu_ic_data\|altsyncram:the_altsyncram " "Instantiated megafunction \"system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_data_module:system_cpu_ic_data\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320302 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 0 " "Parameter \"maximum_depth\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320302 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 2048 " "Parameter \"numwords_a\" = \"2048\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320302 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 2048 " "Parameter \"numwords_b\" = \"2048\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320302 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Parameter \"operation_mode\" = \"DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320302 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320302 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320302 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rdcontrol_reg_b CLOCK0 " "Parameter \"rdcontrol_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320302 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320302 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 32 " "Parameter \"width_a\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320302 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 32 " "Parameter \"width_b\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320302 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 11 " "Parameter \"widthad_a\" = \"11\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320302 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 11 " "Parameter \"widthad_b\" = \"11\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320302 ""} } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 58 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1393888320302 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_sjd1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_sjd1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_sjd1 " "Found entity 1: altsyncram_sjd1" { } { { "db/altsyncram_sjd1.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_sjd1.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888320383 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393888320383 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_sjd1 system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_data_module:system_cpu_ic_data\|altsyncram:the_altsyncram\|altsyncram_sjd1:auto_generated " "Elaborating entity \"altsyncram_sjd1\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_data_module:system_cpu_ic_data\|altsyncram:the_altsyncram\|altsyncram_sjd1:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888320385 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_ic_tag_module system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_tag_module:system_cpu_ic_tag " "Elaborating entity \"system_cpu_ic_tag_module\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_tag_module:system_cpu_ic_tag\"" { } { { "system/synthesis/submodules/system_cpu.v" "system_cpu_ic_tag" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 7164 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888320389 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_tag_module:system_cpu_ic_tag\|altsyncram:the_altsyncram " "Elaborating entity \"altsyncram\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_tag_module:system_cpu_ic_tag\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_altsyncram" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 123 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888320402 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_tag_module:system_cpu_ic_tag\|altsyncram:the_altsyncram " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_tag_module:system_cpu_ic_tag\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 123 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1393888320404 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_tag_module:system_cpu_ic_tag\|altsyncram:the_altsyncram " "Instantiated megafunction \"system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_tag_module:system_cpu_ic_tag\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320405 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file system_cpu_ic_tag_ram.mif " "Parameter \"init_file\" = \"system_cpu_ic_tag_ram.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320405 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 0 " "Parameter \"maximum_depth\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320405 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 256 " "Parameter \"numwords_a\" = \"256\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320405 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 256 " "Parameter \"numwords_b\" = \"256\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320405 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Parameter \"operation_mode\" = \"DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320405 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320405 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320405 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rdcontrol_reg_b CLOCK0 " "Parameter \"rdcontrol_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320405 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports OLD_DATA " "Parameter \"read_during_write_mode_mixed_ports\" = \"OLD_DATA\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320405 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 21 " "Parameter \"width_a\" = \"21\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320405 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 21 " "Parameter \"width_b\" = \"21\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320405 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 8 " "Parameter \"widthad_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320405 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 8 " "Parameter \"widthad_b\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320405 ""} } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 123 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1393888320405 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_qtg1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_qtg1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_qtg1 " "Found entity 1: altsyncram_qtg1" { } { { "db/altsyncram_qtg1.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_qtg1.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888320477 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393888320477 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_qtg1 system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_tag_module:system_cpu_ic_tag\|altsyncram:the_altsyncram\|altsyncram_qtg1:auto_generated " "Elaborating entity \"altsyncram_qtg1\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_tag_module:system_cpu_ic_tag\|altsyncram:the_altsyncram\|altsyncram_qtg1:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888320479 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_bht_module system:inst_cpu\|system_cpu:cpu\|system_cpu_bht_module:system_cpu_bht " "Elaborating entity \"system_cpu_bht_module\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_bht_module:system_cpu_bht\"" { } { { "system/synthesis/submodules/system_cpu.v" "system_cpu_bht" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 7368 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888320502 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram system:inst_cpu\|system_cpu:cpu\|system_cpu_bht_module:system_cpu_bht\|altsyncram:the_altsyncram " "Elaborating entity \"altsyncram\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_bht_module:system_cpu_bht\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_altsyncram" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 189 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888320509 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_cpu:cpu\|system_cpu_bht_module:system_cpu_bht\|altsyncram:the_altsyncram " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_bht_module:system_cpu_bht\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 189 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1393888320511 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_cpu:cpu\|system_cpu_bht_module:system_cpu_bht\|altsyncram:the_altsyncram " "Instantiated megafunction \"system:inst_cpu\|system_cpu:cpu\|system_cpu_bht_module:system_cpu_bht\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320511 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file system_cpu_bht_ram.mif " "Parameter \"init_file\" = \"system_cpu_bht_ram.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320511 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 0 " "Parameter \"maximum_depth\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320511 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 256 " "Parameter \"numwords_a\" = \"256\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320511 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 256 " "Parameter \"numwords_b\" = \"256\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320511 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Parameter \"operation_mode\" = \"DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320511 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320511 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320511 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rdcontrol_reg_b CLOCK0 " "Parameter \"rdcontrol_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320511 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports OLD_DATA " "Parameter \"read_during_write_mode_mixed_ports\" = \"OLD_DATA\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320511 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 2 " "Parameter \"width_a\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320511 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 2 " "Parameter \"width_b\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320511 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 8 " "Parameter \"widthad_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320511 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 8 " "Parameter \"widthad_b\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320511 ""} } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 189 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1393888320511 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_fhg1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_fhg1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_fhg1 " "Found entity 1: altsyncram_fhg1" { } { { "db/altsyncram_fhg1.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_fhg1.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888320568 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393888320568 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_fhg1 system:inst_cpu\|system_cpu:cpu\|system_cpu_bht_module:system_cpu_bht\|altsyncram:the_altsyncram\|altsyncram_fhg1:auto_generated " "Elaborating entity \"altsyncram_fhg1\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_bht_module:system_cpu_bht\|altsyncram:the_altsyncram\|altsyncram_fhg1:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888320570 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_register_bank_a_module system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_a_module:system_cpu_register_bank_a " "Elaborating entity \"system_cpu_register_bank_a_module\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_a_module:system_cpu_register_bank_a\"" { } { { "system/synthesis/submodules/system_cpu.v" "system_cpu_register_bank_a" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 7514 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888320577 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_a_module:system_cpu_register_bank_a\|altsyncram:the_altsyncram " "Elaborating entity \"altsyncram\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_a_module:system_cpu_register_bank_a\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_altsyncram" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 252 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888320584 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_a_module:system_cpu_register_bank_a\|altsyncram:the_altsyncram " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_a_module:system_cpu_register_bank_a\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 252 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1393888320586 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_a_module:system_cpu_register_bank_a\|altsyncram:the_altsyncram " "Instantiated megafunction \"system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_a_module:system_cpu_register_bank_a\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320587 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file system_cpu_rf_ram_a.mif " "Parameter \"init_file\" = \"system_cpu_rf_ram_a.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320587 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 0 " "Parameter \"maximum_depth\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320587 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 32 " "Parameter \"numwords_a\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320587 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 32 " "Parameter \"numwords_b\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320587 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Parameter \"operation_mode\" = \"DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320587 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320587 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320587 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rdcontrol_reg_b CLOCK0 " "Parameter \"rdcontrol_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320587 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports OLD_DATA " "Parameter \"read_during_write_mode_mixed_ports\" = \"OLD_DATA\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320587 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 32 " "Parameter \"width_a\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320587 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 32 " "Parameter \"width_b\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320587 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 5 " "Parameter \"widthad_a\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320587 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 5 " "Parameter \"widthad_b\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320587 ""} } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 252 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1393888320587 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_fvf1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_fvf1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_fvf1 " "Found entity 1: altsyncram_fvf1" { } { { "db/altsyncram_fvf1.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_fvf1.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888320667 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393888320667 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_fvf1 system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_a_module:system_cpu_register_bank_a\|altsyncram:the_altsyncram\|altsyncram_fvf1:auto_generated " "Elaborating entity \"altsyncram_fvf1\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_a_module:system_cpu_register_bank_a\|altsyncram:the_altsyncram\|altsyncram_fvf1:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888320670 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_register_bank_b_module system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_b_module:system_cpu_register_bank_b " "Elaborating entity \"system_cpu_register_bank_b_module\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_b_module:system_cpu_register_bank_b\"" { } { { "system/synthesis/submodules/system_cpu.v" "system_cpu_register_bank_b" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 7535 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888320701 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_b_module:system_cpu_register_bank_b\|altsyncram:the_altsyncram " "Elaborating entity \"altsyncram\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_b_module:system_cpu_register_bank_b\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_altsyncram" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 315 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888320709 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_b_module:system_cpu_register_bank_b\|altsyncram:the_altsyncram " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_b_module:system_cpu_register_bank_b\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 315 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1393888320711 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_b_module:system_cpu_register_bank_b\|altsyncram:the_altsyncram " "Instantiated megafunction \"system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_b_module:system_cpu_register_bank_b\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320712 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file system_cpu_rf_ram_b.mif " "Parameter \"init_file\" = \"system_cpu_rf_ram_b.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320712 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 0 " "Parameter \"maximum_depth\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320712 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 32 " "Parameter \"numwords_a\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320712 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 32 " "Parameter \"numwords_b\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320712 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Parameter \"operation_mode\" = \"DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320712 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320712 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320712 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rdcontrol_reg_b CLOCK0 " "Parameter \"rdcontrol_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320712 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports OLD_DATA " "Parameter \"read_during_write_mode_mixed_ports\" = \"OLD_DATA\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320712 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 32 " "Parameter \"width_a\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320712 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 32 " "Parameter \"width_b\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320712 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 5 " "Parameter \"widthad_a\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320712 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 5 " "Parameter \"widthad_b\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320712 ""} } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 315 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1393888320712 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_gvf1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_gvf1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_gvf1 " "Found entity 1: altsyncram_gvf1" { } { { "db/altsyncram_gvf1.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_gvf1.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888320792 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393888320792 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_gvf1 system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_b_module:system_cpu_register_bank_b\|altsyncram:the_altsyncram\|altsyncram_gvf1:auto_generated " "Elaborating entity \"altsyncram_gvf1\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_b_module:system_cpu_register_bank_b\|altsyncram:the_altsyncram\|altsyncram_gvf1:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888320794 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_dc_tag_module system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_tag_module:system_cpu_dc_tag " "Elaborating entity \"system_cpu_dc_tag_module\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_tag_module:system_cpu_dc_tag\"" { } { { "system/synthesis/submodules/system_cpu.v" "system_cpu_dc_tag" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 7968 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888320825 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_tag_module:system_cpu_dc_tag\|altsyncram:the_altsyncram " "Elaborating entity \"altsyncram\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_tag_module:system_cpu_dc_tag\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_altsyncram" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 378 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888320833 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_tag_module:system_cpu_dc_tag\|altsyncram:the_altsyncram " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_tag_module:system_cpu_dc_tag\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 378 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1393888320835 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_tag_module:system_cpu_dc_tag\|altsyncram:the_altsyncram " "Instantiated megafunction \"system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_tag_module:system_cpu_dc_tag\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320836 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file system_cpu_dc_tag_ram.mif " "Parameter \"init_file\" = \"system_cpu_dc_tag_ram.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320836 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 0 " "Parameter \"maximum_depth\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320836 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 128 " "Parameter \"numwords_a\" = \"128\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320836 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 128 " "Parameter \"numwords_b\" = \"128\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320836 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Parameter \"operation_mode\" = \"DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320836 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320836 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320836 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rdcontrol_reg_b CLOCK0 " "Parameter \"rdcontrol_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320836 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports OLD_DATA " "Parameter \"read_during_write_mode_mixed_ports\" = \"OLD_DATA\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320836 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 16 " "Parameter \"width_a\" = \"16\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320836 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 16 " "Parameter \"width_b\" = \"16\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320836 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 7 " "Parameter \"widthad_a\" = \"7\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320836 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 7 " "Parameter \"widthad_b\" = \"7\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320836 ""} } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 378 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1393888320836 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_d9g1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_d9g1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_d9g1 " "Found entity 1: altsyncram_d9g1" { } { { "db/altsyncram_d9g1.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_d9g1.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888320904 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393888320904 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_d9g1 system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_tag_module:system_cpu_dc_tag\|altsyncram:the_altsyncram\|altsyncram_d9g1:auto_generated " "Elaborating entity \"altsyncram_d9g1\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_tag_module:system_cpu_dc_tag\|altsyncram:the_altsyncram\|altsyncram_d9g1:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888320906 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_dc_data_module system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_data_module:system_cpu_dc_data " "Elaborating entity \"system_cpu_dc_data_module\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_data_module:system_cpu_dc_data\"" { } { { "system/synthesis/submodules/system_cpu.v" "system_cpu_dc_data" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 8022 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888320923 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_data_module:system_cpu_dc_data\|altsyncram:the_altsyncram " "Elaborating entity \"altsyncram\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_data_module:system_cpu_dc_data\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_altsyncram" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 444 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888320931 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_data_module:system_cpu_dc_data\|altsyncram:the_altsyncram " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_data_module:system_cpu_dc_data\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 444 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1393888320933 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_data_module:system_cpu_dc_data\|altsyncram:the_altsyncram " "Instantiated megafunction \"system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_data_module:system_cpu_dc_data\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320934 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 0 " "Parameter \"maximum_depth\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320934 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 1024 " "Parameter \"numwords_a\" = \"1024\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320934 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 1024 " "Parameter \"numwords_b\" = \"1024\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320934 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Parameter \"operation_mode\" = \"DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320934 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320934 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320934 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rdcontrol_reg_b CLOCK0 " "Parameter \"rdcontrol_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320934 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320934 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 32 " "Parameter \"width_a\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320934 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 32 " "Parameter \"width_b\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320934 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 4 " "Parameter \"width_byteena_a\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320934 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 10 " "Parameter \"widthad_a\" = \"10\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320934 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 10 " "Parameter \"widthad_b\" = \"10\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888320934 ""} } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 444 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1393888320934 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_2jf1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_2jf1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_2jf1 " "Found entity 1: altsyncram_2jf1" { } { { "db/altsyncram_2jf1.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_2jf1.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888321014 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393888321014 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_2jf1 system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_data_module:system_cpu_dc_data\|altsyncram:the_altsyncram\|altsyncram_2jf1:auto_generated " "Elaborating entity \"altsyncram_2jf1\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_data_module:system_cpu_dc_data\|altsyncram:the_altsyncram\|altsyncram_2jf1:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888321016 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_dc_victim_module system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_victim_module:system_cpu_dc_victim " "Elaborating entity \"system_cpu_dc_victim_module\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_victim_module:system_cpu_dc_victim\"" { } { { "system/synthesis/submodules/system_cpu.v" "system_cpu_dc_victim" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 8038 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888321020 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_victim_module:system_cpu_dc_victim\|altsyncram:the_altsyncram " "Elaborating entity \"altsyncram\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_victim_module:system_cpu_dc_victim\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_altsyncram" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 510 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888321028 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_victim_module:system_cpu_dc_victim\|altsyncram:the_altsyncram " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_victim_module:system_cpu_dc_victim\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 510 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1393888321030 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_victim_module:system_cpu_dc_victim\|altsyncram:the_altsyncram " "Instantiated megafunction \"system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_victim_module:system_cpu_dc_victim\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321031 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 0 " "Parameter \"maximum_depth\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321031 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 8 " "Parameter \"numwords_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321031 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 8 " "Parameter \"numwords_b\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321031 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Parameter \"operation_mode\" = \"DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321031 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321031 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321031 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rdcontrol_reg_b CLOCK0 " "Parameter \"rdcontrol_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321031 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports OLD_DATA " "Parameter \"read_during_write_mode_mixed_ports\" = \"OLD_DATA\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321031 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 32 " "Parameter \"width_a\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321031 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 32 " "Parameter \"width_b\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321031 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 3 " "Parameter \"widthad_a\" = \"3\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321031 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 3 " "Parameter \"widthad_b\" = \"3\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321031 ""} } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 510 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1393888321031 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_r3d1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_r3d1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_r3d1 " "Found entity 1: altsyncram_r3d1" { } { { "db/altsyncram_r3d1.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_r3d1.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888321108 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393888321108 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_r3d1 system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_victim_module:system_cpu_dc_victim\|altsyncram:the_altsyncram\|altsyncram_r3d1:auto_generated " "Elaborating entity \"altsyncram_r3d1\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_victim_module:system_cpu_dc_victim\|altsyncram:the_altsyncram\|altsyncram_r3d1:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888321110 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_mult_cell system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell " "Elaborating entity \"system_cpu_mult_cell\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_mult_cell" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 9915 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888321115 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altmult_add system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_1 " "Elaborating entity \"altmult_add\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_1\"" { } { { "system/synthesis/submodules/system_cpu_mult_cell.v" "the_altmult_add_part_1" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu_mult_cell.v" 52 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888321160 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_1 " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_1\"" { } { { "system/synthesis/submodules/system_cpu_mult_cell.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu_mult_cell.v" 52 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1393888321164 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_1 " "Instantiated megafunction \"system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_1\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "addnsub_multiplier_pipeline_aclr1 ACLR0 " "Parameter \"addnsub_multiplier_pipeline_aclr1\" = \"ACLR0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321166 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "addnsub_multiplier_pipeline_register1 CLOCK0 " "Parameter \"addnsub_multiplier_pipeline_register1\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321166 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "addnsub_multiplier_register1 UNREGISTERED " "Parameter \"addnsub_multiplier_register1\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321166 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "dedicated_multiplier_circuitry YES " "Parameter \"dedicated_multiplier_circuitry\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321166 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "input_register_a0 UNREGISTERED " "Parameter \"input_register_a0\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321166 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "input_register_b0 UNREGISTERED " "Parameter \"input_register_b0\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321166 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "input_source_a0 DATAA " "Parameter \"input_source_a0\" = \"DATAA\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321166 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "input_source_b0 DATAB " "Parameter \"input_source_b0\" = \"DATAB\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321166 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family CYCLONEIVE " "Parameter \"intended_device_family\" = \"CYCLONEIVE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321166 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altmult_add " "Parameter \"lpm_type\" = \"altmult_add\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321166 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "multiplier1_direction ADD " "Parameter \"multiplier1_direction\" = \"ADD\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321166 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "multiplier_aclr0 ACLR0 " "Parameter \"multiplier_aclr0\" = \"ACLR0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321166 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "multiplier_register0 CLOCK0 " "Parameter \"multiplier_register0\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321166 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "number_of_multipliers 1 " "Parameter \"number_of_multipliers\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321166 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_register UNREGISTERED " "Parameter \"output_register\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321166 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_addnsub1 PORT_UNUSED " "Parameter \"port_addnsub1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321166 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_addnsub3 PORT_UNUSED " "Parameter \"port_addnsub3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321166 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_signa PORT_UNUSED " "Parameter \"port_signa\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321166 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_signb PORT_UNUSED " "Parameter \"port_signb\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321166 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "representation_a UNSIGNED " "Parameter \"representation_a\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321166 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "representation_b UNSIGNED " "Parameter \"representation_b\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321166 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_pipeline_aclr_a ACLR0 " "Parameter \"signed_pipeline_aclr_a\" = \"ACLR0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321166 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_pipeline_aclr_b ACLR0 " "Parameter \"signed_pipeline_aclr_b\" = \"ACLR0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321166 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_pipeline_register_a CLOCK0 " "Parameter \"signed_pipeline_register_a\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321166 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_pipeline_register_b CLOCK0 " "Parameter \"signed_pipeline_register_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321166 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_register_a UNREGISTERED " "Parameter \"signed_register_a\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321166 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_register_b UNREGISTERED " "Parameter \"signed_register_b\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321166 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 16 " "Parameter \"width_a\" = \"16\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321166 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 16 " "Parameter \"width_b\" = \"16\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321166 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_result 32 " "Parameter \"width_result\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321166 ""} } { { "system/synthesis/submodules/system_cpu_mult_cell.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu_mult_cell.v" 52 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1393888321166 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mult_add_75u2.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mult_add_75u2.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mult_add_75u2 " "Found entity 1: mult_add_75u2" { } { { "db/mult_add_75u2.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/mult_add_75u2.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888321224 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393888321224 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mult_add_75u2 system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_1\|mult_add_75u2:auto_generated " "Elaborating entity \"mult_add_75u2\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_1\|mult_add_75u2:auto_generated\"" { } { { "altmult_add.tdf" "auto_generated" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altmult_add.tdf" 594 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888321227 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ded_mult_ks81.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/ded_mult_ks81.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 ded_mult_ks81 " "Found entity 1: ded_mult_ks81" { } { { "db/ded_mult_ks81.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/ded_mult_ks81.tdf" 30 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888321236 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393888321236 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ded_mult_ks81 system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_1\|mult_add_75u2:auto_generated\|ded_mult_ks81:ded_mult1 " "Elaborating entity \"ded_mult_ks81\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_1\|mult_add_75u2:auto_generated\|ded_mult_ks81:ded_mult1\"" { } { { "db/mult_add_75u2.tdf" "ded_mult1" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/mult_add_75u2.tdf" 33 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888321238 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/dffpipe_93c.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/dffpipe_93c.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 dffpipe_93c " "Found entity 1: dffpipe_93c" { } { { "db/dffpipe_93c.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/dffpipe_93c.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888321247 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393888321247 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dffpipe_93c system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_1\|mult_add_75u2:auto_generated\|ded_mult_ks81:ded_mult1\|dffpipe_93c:pre_result " "Elaborating entity \"dffpipe_93c\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_1\|mult_add_75u2:auto_generated\|ded_mult_ks81:ded_mult1\|dffpipe_93c:pre_result\"" { } { { "db/ded_mult_ks81.tdf" "pre_result" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/ded_mult_ks81.tdf" 50 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888321249 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altmult_add system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_2 " "Elaborating entity \"altmult_add\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_2\"" { } { { "system/synthesis/submodules/system_cpu_mult_cell.v" "the_altmult_add_part_2" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu_mult_cell.v" 93 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888321281 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_2 " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_2\"" { } { { "system/synthesis/submodules/system_cpu_mult_cell.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu_mult_cell.v" 93 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1393888321287 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_2 " "Instantiated megafunction \"system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_2\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "addnsub_multiplier_pipeline_aclr1 ACLR0 " "Parameter \"addnsub_multiplier_pipeline_aclr1\" = \"ACLR0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321289 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "addnsub_multiplier_pipeline_register1 CLOCK0 " "Parameter \"addnsub_multiplier_pipeline_register1\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321289 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "addnsub_multiplier_register1 UNREGISTERED " "Parameter \"addnsub_multiplier_register1\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321289 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "dedicated_multiplier_circuitry YES " "Parameter \"dedicated_multiplier_circuitry\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321289 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "input_register_a0 UNREGISTERED " "Parameter \"input_register_a0\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321289 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "input_register_b0 UNREGISTERED " "Parameter \"input_register_b0\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321289 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "input_source_a0 DATAA " "Parameter \"input_source_a0\" = \"DATAA\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321289 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "input_source_b0 DATAB " "Parameter \"input_source_b0\" = \"DATAB\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321289 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family CYCLONEIVE " "Parameter \"intended_device_family\" = \"CYCLONEIVE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321289 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altmult_add " "Parameter \"lpm_type\" = \"altmult_add\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321289 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "multiplier1_direction ADD " "Parameter \"multiplier1_direction\" = \"ADD\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321289 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "multiplier_aclr0 ACLR0 " "Parameter \"multiplier_aclr0\" = \"ACLR0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321289 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "multiplier_register0 CLOCK0 " "Parameter \"multiplier_register0\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321289 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "number_of_multipliers 1 " "Parameter \"number_of_multipliers\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321289 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_register UNREGISTERED " "Parameter \"output_register\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321289 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_addnsub1 PORT_UNUSED " "Parameter \"port_addnsub1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321289 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_addnsub3 PORT_UNUSED " "Parameter \"port_addnsub3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321289 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_signa PORT_UNUSED " "Parameter \"port_signa\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321289 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_signb PORT_UNUSED " "Parameter \"port_signb\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321289 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "representation_a UNSIGNED " "Parameter \"representation_a\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321289 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "representation_b UNSIGNED " "Parameter \"representation_b\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321289 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_pipeline_aclr_a ACLR0 " "Parameter \"signed_pipeline_aclr_a\" = \"ACLR0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321289 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_pipeline_aclr_b ACLR0 " "Parameter \"signed_pipeline_aclr_b\" = \"ACLR0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321289 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_pipeline_register_a CLOCK0 " "Parameter \"signed_pipeline_register_a\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321289 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_pipeline_register_b CLOCK0 " "Parameter \"signed_pipeline_register_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321289 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_register_a UNREGISTERED " "Parameter \"signed_register_a\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321289 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_register_b UNREGISTERED " "Parameter \"signed_register_b\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321289 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 16 " "Parameter \"width_a\" = \"16\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321289 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 16 " "Parameter \"width_b\" = \"16\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321289 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_result 16 " "Parameter \"width_result\" = \"16\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321289 ""} } { { "system/synthesis/submodules/system_cpu_mult_cell.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu_mult_cell.v" 93 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1393888321289 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mult_add_95u2.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mult_add_95u2.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mult_add_95u2 " "Found entity 1: mult_add_95u2" { } { { "db/mult_add_95u2.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/mult_add_95u2.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888321348 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393888321348 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mult_add_95u2 system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_2\|mult_add_95u2:auto_generated " "Elaborating entity \"mult_add_95u2\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_2\|mult_add_95u2:auto_generated\"" { } { { "altmult_add.tdf" "auto_generated" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altmult_add.tdf" 594 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888321350 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_oci system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci " "Elaborating entity \"system_cpu_nios2_oci\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_nios2_oci" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888321358 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_oci_debug system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_debug:the_system_cpu_nios2_oci_debug " "Elaborating entity \"system_cpu_nios2_oci_debug\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_debug:the_system_cpu_nios2_oci_debug\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_nios2_oci_debug" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3444 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888321362 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_ocimem system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem " "Elaborating entity \"system_cpu_nios2_ocimem\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_nios2_ocimem" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3464 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888321364 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_ociram_lpm_dram_bdp_component_module system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem\|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component " "Elaborating entity \"system_cpu_ociram_lpm_dram_bdp_component_module\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem\|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component\"" { } { { "system/synthesis/submodules/system_cpu.v" "system_cpu_ociram_lpm_dram_bdp_component" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 872 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888321366 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem\|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component\|altsyncram:the_altsyncram " "Elaborating entity \"altsyncram\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem\|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_altsyncram" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 720 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888321375 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem\|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component\|altsyncram:the_altsyncram " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem\|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 720 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1393888321377 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem\|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component\|altsyncram:the_altsyncram " "Instantiated megafunction \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem\|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_a NONE " "Parameter \"address_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321379 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_b NONE " "Parameter \"address_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321379 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK1 " "Parameter \"address_reg_b\" = \"CLOCK1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321379 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_aclr_a NONE " "Parameter \"indata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321379 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_aclr_b NONE " "Parameter \"indata_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321379 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file system_cpu_ociram_default_contents.mif " "Parameter \"init_file\" = \"system_cpu_ociram_default_contents.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321379 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family CYCLONEIVE " "Parameter \"intended_device_family\" = \"CYCLONEIVE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321379 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321379 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 256 " "Parameter \"numwords_a\" = \"256\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321379 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 256 " "Parameter \"numwords_b\" = \"256\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321379 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode BIDIR_DUAL_PORT " "Parameter \"operation_mode\" = \"BIDIR_DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321379 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321379 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_b NONE " "Parameter \"outdata_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321379 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a UNREGISTERED " "Parameter \"outdata_reg_a\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321379 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321379 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321379 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports OLD_DATA " "Parameter \"read_during_write_mode_mixed_ports\" = \"OLD_DATA\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321379 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 32 " "Parameter \"width_a\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321379 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 32 " "Parameter \"width_b\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321379 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 4 " "Parameter \"width_byteena_a\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321379 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 8 " "Parameter \"widthad_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321379 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 8 " "Parameter \"widthad_b\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321379 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_aclr_a NONE " "Parameter \"wrcontrol_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321379 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_aclr_b NONE " "Parameter \"wrcontrol_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321379 ""} } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 720 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1393888321379 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_jt72.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_jt72.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_jt72 " "Found entity 1: altsyncram_jt72" { } { { "db/altsyncram_jt72.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_jt72.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888321471 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393888321471 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_jt72 system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem\|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_jt72:auto_generated " "Elaborating entity \"altsyncram_jt72\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem\|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_jt72:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888321473 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_avalon_reg system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg " "Elaborating entity \"system_cpu_nios2_avalon_reg\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_nios2_avalon_reg" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3484 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888321507 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_oci_break system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_break:the_system_cpu_nios2_oci_break " "Elaborating entity \"system_cpu_nios2_oci_break\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_break:the_system_cpu_nios2_oci_break\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_nios2_oci_break" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3515 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888321509 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_oci_xbrk system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_xbrk:the_system_cpu_nios2_oci_xbrk " "Elaborating entity \"system_cpu_nios2_oci_xbrk\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_xbrk:the_system_cpu_nios2_oci_xbrk\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_nios2_oci_xbrk" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3538 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888321512 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_oci_dbrk system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_dbrk:the_system_cpu_nios2_oci_dbrk " "Elaborating entity \"system_cpu_nios2_oci_dbrk\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_dbrk:the_system_cpu_nios2_oci_dbrk\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_nios2_oci_dbrk" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3565 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888321513 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_oci_itrace system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_itrace:the_system_cpu_nios2_oci_itrace " "Elaborating entity \"system_cpu_nios2_oci_itrace\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_itrace:the_system_cpu_nios2_oci_itrace\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_nios2_oci_itrace" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3606 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888321515 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_oci_dtrace system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_dtrace:the_system_cpu_nios2_oci_dtrace " "Elaborating entity \"system_cpu_nios2_oci_dtrace\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_dtrace:the_system_cpu_nios2_oci_dtrace\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_nios2_oci_dtrace" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3621 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888321518 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_oci_td_mode system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_dtrace:the_system_cpu_nios2_oci_dtrace\|system_cpu_nios2_oci_td_mode:system_cpu_nios2_oci_trc_ctrl_td_mode " "Elaborating entity \"system_cpu_nios2_oci_td_mode\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_dtrace:the_system_cpu_nios2_oci_dtrace\|system_cpu_nios2_oci_td_mode:system_cpu_nios2_oci_trc_ctrl_td_mode\"" { } { { "system/synthesis/submodules/system_cpu.v" "system_cpu_nios2_oci_trc_ctrl_td_mode" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 2213 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888321521 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_oci_fifo system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_fifo:the_system_cpu_nios2_oci_fifo " "Elaborating entity \"system_cpu_nios2_oci_fifo\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_fifo:the_system_cpu_nios2_oci_fifo\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_nios2_oci_fifo" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3640 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888321522 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_oci_compute_tm_count system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_fifo:the_system_cpu_nios2_oci_fifo\|system_cpu_nios2_oci_compute_tm_count:system_cpu_nios2_oci_compute_tm_count_tm_count " "Elaborating entity \"system_cpu_nios2_oci_compute_tm_count\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_fifo:the_system_cpu_nios2_oci_fifo\|system_cpu_nios2_oci_compute_tm_count:system_cpu_nios2_oci_compute_tm_count_tm_count\"" { } { { "system/synthesis/submodules/system_cpu.v" "system_cpu_nios2_oci_compute_tm_count_tm_count" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 2545 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888321525 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_oci_fifowp_inc system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_fifo:the_system_cpu_nios2_oci_fifo\|system_cpu_nios2_oci_fifowp_inc:system_cpu_nios2_oci_fifowp_inc_fifowp " "Elaborating entity \"system_cpu_nios2_oci_fifowp_inc\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_fifo:the_system_cpu_nios2_oci_fifo\|system_cpu_nios2_oci_fifowp_inc:system_cpu_nios2_oci_fifowp_inc_fifowp\"" { } { { "system/synthesis/submodules/system_cpu.v" "system_cpu_nios2_oci_fifowp_inc_fifowp" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 2555 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888321526 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_oci_fifocount_inc system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_fifo:the_system_cpu_nios2_oci_fifo\|system_cpu_nios2_oci_fifocount_inc:system_cpu_nios2_oci_fifocount_inc_fifocount " "Elaborating entity \"system_cpu_nios2_oci_fifocount_inc\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_fifo:the_system_cpu_nios2_oci_fifo\|system_cpu_nios2_oci_fifocount_inc:system_cpu_nios2_oci_fifocount_inc_fifocount\"" { } { { "system/synthesis/submodules/system_cpu.v" "system_cpu_nios2_oci_fifocount_inc_fifocount" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 2565 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888321528 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_oci_test_bench system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_fifo:the_system_cpu_nios2_oci_fifo\|system_cpu_oci_test_bench:the_system_cpu_oci_test_bench " "Elaborating entity \"system_cpu_oci_test_bench\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_fifo:the_system_cpu_nios2_oci_fifo\|system_cpu_oci_test_bench:the_system_cpu_oci_test_bench\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_oci_test_bench" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 2574 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888321530 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_oci_pib system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_pib:the_system_cpu_nios2_oci_pib " "Elaborating entity \"system_cpu_nios2_oci_pib\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_pib:the_system_cpu_nios2_oci_pib\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_nios2_oci_pib" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3650 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888321532 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_oci_im system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im " "Elaborating entity \"system_cpu_nios2_oci_im\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_nios2_oci_im" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888321533 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_traceram_lpm_dram_bdp_component_module system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component " "Elaborating entity \"system_cpu_traceram_lpm_dram_bdp_component_module\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\"" { } { { "system/synthesis/submodules/system_cpu.v" "system_cpu_traceram_lpm_dram_bdp_component" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888321536 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram " "Elaborating entity \"altsyncram\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_altsyncram" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888321544 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1393888321547 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram " "Instantiated megafunction \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_a NONE " "Parameter \"address_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321548 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_b NONE " "Parameter \"address_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321548 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK1 " "Parameter \"address_reg_b\" = \"CLOCK1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321548 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_aclr_a NONE " "Parameter \"indata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321548 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_aclr_b NONE " "Parameter \"indata_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321548 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file UNUSED " "Parameter \"init_file\" = \"UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321548 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family CYCLONEIVE " "Parameter \"intended_device_family\" = \"CYCLONEIVE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321548 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321548 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 128 " "Parameter \"numwords_a\" = \"128\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321548 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 128 " "Parameter \"numwords_b\" = \"128\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321548 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode BIDIR_DUAL_PORT " "Parameter \"operation_mode\" = \"BIDIR_DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321548 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321548 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_b NONE " "Parameter \"outdata_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321548 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a UNREGISTERED " "Parameter \"outdata_reg_a\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321548 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321548 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321548 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports OLD_DATA " "Parameter \"read_during_write_mode_mixed_ports\" = \"OLD_DATA\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321548 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 36 " "Parameter \"width_a\" = \"36\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321548 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 36 " "Parameter \"width_b\" = \"36\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321548 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 7 " "Parameter \"widthad_a\" = \"7\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321548 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 7 " "Parameter \"widthad_b\" = \"7\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321548 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_aclr_a NONE " "Parameter \"wrcontrol_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321548 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_aclr_b NONE " "Parameter \"wrcontrol_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321548 ""} } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1393888321548 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_0a02.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_0a02.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_0a02 " "Found entity 1: altsyncram_0a02" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888321639 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393888321639 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_0a02 system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated " "Elaborating entity \"altsyncram_0a02\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888321641 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_jtag_debug_module_wrapper system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper " "Elaborating entity \"system_cpu_jtag_debug_module_wrapper\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_jtag_debug_module_wrapper" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3714 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888321647 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_jtag_debug_module_tck system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck " "Elaborating entity \"system_cpu_jtag_debug_module_tck\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck\"" { } { { "system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v" "the_system_cpu_jtag_debug_module_tck" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v" 165 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888321650 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_std_synchronizer system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck\|altera_std_synchronizer:the_altera_std_synchronizer " "Elaborating entity \"altera_std_synchronizer\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck\|altera_std_synchronizer:the_altera_std_synchronizer\"" { } { { "system/synthesis/submodules/system_cpu_jtag_debug_module_tck.v" "the_altera_std_synchronizer" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu_jtag_debug_module_tck.v" 202 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888321663 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck\|altera_std_synchronizer:the_altera_std_synchronizer " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck\|altera_std_synchronizer:the_altera_std_synchronizer\"" { } { { "system/synthesis/submodules/system_cpu_jtag_debug_module_tck.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu_jtag_debug_module_tck.v" 202 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1393888321664 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck\|altera_std_synchronizer:the_altera_std_synchronizer " "Instantiated megafunction \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck\|altera_std_synchronizer:the_altera_std_synchronizer\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "depth 2 " "Parameter \"depth\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321664 ""} } { { "system/synthesis/submodules/system_cpu_jtag_debug_module_tck.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu_jtag_debug_module_tck.v" 202 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1393888321664 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_jtag_debug_module_sysclk system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk " "Elaborating entity \"system_cpu_jtag_debug_module_sysclk\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk\"" { } { { "system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v" "the_system_cpu_jtag_debug_module_sysclk" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v" 188 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888321669 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sld_virtual_jtag_basic system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy " "Elaborating entity \"sld_virtual_jtag_basic\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy\"" { } { { "system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v" "system_cpu_jtag_debug_module_phy" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v" 218 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888321687 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy\"" { } { { "system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v" 218 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1393888321688 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy " "Instantiated megafunction \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_auto_instance_index YES " "Parameter \"sld_auto_instance_index\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321688 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_instance_index 0 " "Parameter \"sld_instance_index\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321688 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_ir_width 2 " "Parameter \"sld_ir_width\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321688 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_mfg_id 70 " "Parameter \"sld_mfg_id\" = \"70\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321688 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_sim_action " "Parameter \"sld_sim_action\" = \"\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321688 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_sim_n_scan 0 " "Parameter \"sld_sim_n_scan\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321688 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_sim_total_length 0 " "Parameter \"sld_sim_total_length\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321688 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_type_id 34 " "Parameter \"sld_type_id\" = \"34\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321688 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_version 3 " "Parameter \"sld_version\" = \"3\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321688 ""} } { { "system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v" 218 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1393888321688 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sld_virtual_jtag_impl system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy\|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst " "Elaborating entity \"sld_virtual_jtag_impl\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy\|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst\"" { } { { "sld_virtual_jtag_basic.v" "sld_virtual_jtag_impl_inst" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/sld_virtual_jtag_basic.v" 151 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888321690 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy\|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy\|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst\", which is child of megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy\"" { } { { "sld_virtual_jtag_basic.v" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/sld_virtual_jtag_basic.v" 151 0 0 } } { "system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v" 218 0 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0 -1 1393888321692 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_sysid system:inst_cpu\|system_sysid:sysid " "Elaborating entity \"system_sysid\" for hierarchy \"system:inst_cpu\|system_sysid:sysid\"" { } { { "system/synthesis/system.v" "sysid" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 856 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888321695 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_sdram system:inst_cpu\|system_sdram:sdram " "Elaborating entity \"system_sdram\" for hierarchy \"system:inst_cpu\|system_sdram:sdram\"" { } { { "system/synthesis/system.v" "sdram" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 879 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888321697 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_sdram_input_efifo_module system:inst_cpu\|system_sdram:sdram\|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module " "Elaborating entity \"system_sdram_input_efifo_module\" for hierarchy \"system:inst_cpu\|system_sdram:sdram\|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module\"" { } { { "system/synthesis/submodules/system_sdram.v" "the_system_sdram_input_efifo_module" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_sdram.v" 296 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888321703 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_sys_clk_timer system:inst_cpu\|system_sys_clk_timer:sys_clk_timer " "Elaborating entity \"system_sys_clk_timer\" for hierarchy \"system:inst_cpu\|system_sys_clk_timer:sys_clk_timer\"" { } { { "system/synthesis/system.v" "sys_clk_timer" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 890 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888321706 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_uart_wifi system:inst_cpu\|system_uart_wifi:uart_wifi " "Elaborating entity \"system_uart_wifi\" for hierarchy \"system:inst_cpu\|system_uart_wifi:uart_wifi\"" { } { { "system/synthesis/system.v" "uart_wifi" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 907 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888321709 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_uart_wifi_tx system:inst_cpu\|system_uart_wifi:uart_wifi\|system_uart_wifi_tx:the_system_uart_wifi_tx " "Elaborating entity \"system_uart_wifi_tx\" for hierarchy \"system:inst_cpu\|system_uart_wifi:uart_wifi\|system_uart_wifi_tx:the_system_uart_wifi_tx\"" { } { { "system/synthesis/submodules/system_uart_wifi.v" "the_system_uart_wifi_tx" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_wifi.v" 1079 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888321711 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_uart_wifi_rx system:inst_cpu\|system_uart_wifi:uart_wifi\|system_uart_wifi_rx:the_system_uart_wifi_rx " "Elaborating entity \"system_uart_wifi_rx\" for hierarchy \"system:inst_cpu\|system_uart_wifi:uart_wifi\|system_uart_wifi_rx:the_system_uart_wifi_rx\"" { } { { "system/synthesis/submodules/system_uart_wifi.v" "the_system_uart_wifi_rx" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_wifi.v" 1097 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888321714 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_uart_wifi_rx_stimulus_source system:inst_cpu\|system_uart_wifi:uart_wifi\|system_uart_wifi_rx:the_system_uart_wifi_rx\|system_uart_wifi_rx_stimulus_source:the_system_uart_wifi_rx_stimulus_source " "Elaborating entity \"system_uart_wifi_rx_stimulus_source\" for hierarchy \"system:inst_cpu\|system_uart_wifi:uart_wifi\|system_uart_wifi_rx:the_system_uart_wifi_rx\|system_uart_wifi_rx_stimulus_source:the_system_uart_wifi_rx_stimulus_source\"" { } { { "system/synthesis/submodules/system_uart_wifi.v" "the_system_uart_wifi_rx_stimulus_source" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_wifi.v" 569 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888321717 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_uart_wifi_regs system:inst_cpu\|system_uart_wifi:uart_wifi\|system_uart_wifi_regs:the_system_uart_wifi_regs " "Elaborating entity \"system_uart_wifi_regs\" for hierarchy \"system:inst_cpu\|system_uart_wifi:uart_wifi\|system_uart_wifi_regs:the_system_uart_wifi_regs\"" { } { { "system/synthesis/submodules/system_uart_wifi.v" "the_system_uart_wifi_regs" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_wifi.v" 1128 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888321721 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_pio_led system:inst_cpu\|system_pio_led:pio_led " "Elaborating entity \"system_pio_led\" for hierarchy \"system:inst_cpu\|system_pio_led:pio_led\"" { } { { "system/synthesis/system.v" "pio_led" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 918 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888321724 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_pio_key_left system:inst_cpu\|system_pio_key_left:pio_key_left " "Elaborating entity \"system_pio_key_left\" for hierarchy \"system:inst_cpu\|system_pio_key_left:pio_key_left\"" { } { { "system/synthesis/system.v" "pio_key_left" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 930 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888321725 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_pio_sw system:inst_cpu\|system_pio_sw:pio_sw " "Elaborating entity \"system_pio_sw\" for hierarchy \"system:inst_cpu\|system_pio_sw:pio_sw\"" { } { { "system/synthesis/system.v" "pio_sw" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 938 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888321727 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_jtag_uart_0 system:inst_cpu\|system_jtag_uart_0:jtag_uart_0 " "Elaborating entity \"system_jtag_uart_0\" for hierarchy \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\"" { } { { "system/synthesis/system.v" "jtag_uart_0" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 951 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888321729 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_jtag_uart_0_scfifo_w system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w " "Elaborating entity \"system_jtag_uart_0_scfifo_w\" for hierarchy \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\"" { } { { "system/synthesis/submodules/system_jtag_uart_0.v" "the_system_jtag_uart_0_scfifo_w" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_jtag_uart_0.v" 625 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888321733 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scfifo system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo " "Elaborating entity \"scfifo\" for hierarchy \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\"" { } { { "system/synthesis/submodules/system_jtag_uart_0.v" "wfifo" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_jtag_uart_0.v" 183 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888321783 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo " "Elaborated megafunction instantiation \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\"" { } { { "system/synthesis/submodules/system_jtag_uart_0.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_jtag_uart_0.v" 183 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1393888321783 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo " "Instantiated megafunction \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint RAM_BLOCK_TYPE=AUTO " "Parameter \"lpm_hint\" = \"RAM_BLOCK_TYPE=AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321784 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_numwords 64 " "Parameter \"lpm_numwords\" = \"64\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321784 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_showahead OFF " "Parameter \"lpm_showahead\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321784 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type scfifo " "Parameter \"lpm_type\" = \"scfifo\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321784 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 8 " "Parameter \"lpm_width\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321784 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widthu 6 " "Parameter \"lpm_widthu\" = \"6\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321784 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "overflow_checking OFF " "Parameter \"overflow_checking\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321784 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "underflow_checking OFF " "Parameter \"underflow_checking\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321784 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "use_eab ON " "Parameter \"use_eab\" = \"ON\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888321784 ""} } { { "system/synthesis/submodules/system_jtag_uart_0.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_jtag_uart_0.v" 183 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1393888321784 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/scfifo_jr21.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/scfifo_jr21.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 scfifo_jr21 " "Found entity 1: scfifo_jr21" { } { { "db/scfifo_jr21.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/scfifo_jr21.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888321841 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393888321841 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scfifo_jr21 system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated " "Elaborating entity \"scfifo_jr21\" for hierarchy \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\"" { } { { "scfifo.tdf" "auto_generated" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/scfifo.tdf" 296 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888321843 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_dpfifo_q131.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/a_dpfifo_q131.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_dpfifo_q131 " "Found entity 1: a_dpfifo_q131" { } { { "db/a_dpfifo_q131.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/a_dpfifo_q131.tdf" 28 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888321853 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393888321853 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_dpfifo_q131 system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo " "Elaborating entity \"a_dpfifo_q131\" for hierarchy \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\"" { } { { "db/scfifo_jr21.tdf" "dpfifo" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/scfifo_jr21.tdf" 37 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888321855 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_fefifo_7cf.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/a_fefifo_7cf.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_fefifo_7cf " "Found entity 1: a_fefifo_7cf" { } { { "db/a_fefifo_7cf.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/a_fefifo_7cf.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888321863 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393888321863 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_fefifo_7cf system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|a_fefifo_7cf:fifo_state " "Elaborating entity \"a_fefifo_7cf\" for hierarchy \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|a_fefifo_7cf:fifo_state\"" { } { { "db/a_dpfifo_q131.tdf" "fifo_state" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/a_dpfifo_q131.tdf" 42 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888321865 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_do7.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_do7.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_do7 " "Found entity 1: cntr_do7" { } { { "db/cntr_do7.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/cntr_do7.tdf" 25 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888321919 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393888321919 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_do7 system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|a_fefifo_7cf:fifo_state\|cntr_do7:count_usedw " "Elaborating entity \"cntr_do7\" for hierarchy \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|a_fefifo_7cf:fifo_state\|cntr_do7:count_usedw\"" { } { { "db/a_fefifo_7cf.tdf" "count_usedw" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/a_fefifo_7cf.tdf" 38 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888321921 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/dpram_nl21.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/dpram_nl21.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 dpram_nl21 " "Found entity 1: dpram_nl21" { } { { "db/dpram_nl21.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/dpram_nl21.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888321975 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393888321975 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dpram_nl21 system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|dpram_nl21:FIFOram " "Elaborating entity \"dpram_nl21\" for hierarchy \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|dpram_nl21:FIFOram\"" { } { { "db/a_dpfifo_q131.tdf" "FIFOram" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/a_dpfifo_q131.tdf" 43 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888321977 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_r1m1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_r1m1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_r1m1 " "Found entity 1: altsyncram_r1m1" { } { { "db/altsyncram_r1m1.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_r1m1.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888322038 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393888322038 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_r1m1 system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|dpram_nl21:FIFOram\|altsyncram_r1m1:altsyncram1 " "Elaborating entity \"altsyncram_r1m1\" for hierarchy \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|dpram_nl21:FIFOram\|altsyncram_r1m1:altsyncram1\"" { } { { "db/dpram_nl21.tdf" "altsyncram1" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/dpram_nl21.tdf" 36 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888322041 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_1ob.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_1ob.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_1ob " "Found entity 1: cntr_1ob" { } { { "db/cntr_1ob.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/cntr_1ob.tdf" 25 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888322097 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393888322097 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_1ob system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|cntr_1ob:rd_ptr_count " "Elaborating entity \"cntr_1ob\" for hierarchy \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|cntr_1ob:rd_ptr_count\"" { } { { "db/a_dpfifo_q131.tdf" "rd_ptr_count" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/a_dpfifo_q131.tdf" 44 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888322099 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_jtag_uart_0_scfifo_r system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r " "Elaborating entity \"system_jtag_uart_0_scfifo_r\" for hierarchy \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r\"" { } { { "system/synthesis/submodules/system_jtag_uart_0.v" "the_system_jtag_uart_0_scfifo_r" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_jtag_uart_0.v" 639 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888322107 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_jtag_atlantic system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic " "Elaborating entity \"alt_jtag_atlantic\" for hierarchy \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic\"" { } { { "system/synthesis/submodules/system_jtag_uart_0.v" "system_jtag_uart_0_alt_jtag_atlantic" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_jtag_uart_0.v" 774 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888322225 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic " "Elaborated megafunction instantiation \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic\"" { } { { "system/synthesis/submodules/system_jtag_uart_0.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_jtag_uart_0.v" 774 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1393888322226 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic " "Instantiated megafunction \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "INSTANCE_ID 0 " "Parameter \"INSTANCE_ID\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888322226 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LOG2_RXFIFO_DEPTH 6 " "Parameter \"LOG2_RXFIFO_DEPTH\" = \"6\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888322226 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LOG2_TXFIFO_DEPTH 6 " "Parameter \"LOG2_TXFIFO_DEPTH\" = \"6\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888322226 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "SLD_AUTO_INSTANCE_INDEX YES " "Parameter \"SLD_AUTO_INSTANCE_INDEX\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888322226 ""} } { { "system/synthesis/submodules/system_jtag_uart_0.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_jtag_uart_0.v" 774 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1393888322226 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_pio_ir_emitter system:inst_cpu\|system_pio_ir_emitter:pio_ir_emitter " "Elaborating entity \"system_pio_ir_emitter\" for hierarchy \"system:inst_cpu\|system_pio_ir_emitter:pio_ir_emitter\"" { } { { "system/synthesis/system.v" "pio_ir_emitter" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 962 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888322232 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_uart_mc system:inst_cpu\|system_uart_mc:uart_mc " "Elaborating entity \"system_uart_mc\" for hierarchy \"system:inst_cpu\|system_uart_mc:uart_mc\"" { } { { "system/synthesis/system.v" "uart_mc" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 979 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888322234 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_uart_mc_tx system:inst_cpu\|system_uart_mc:uart_mc\|system_uart_mc_tx:the_system_uart_mc_tx " "Elaborating entity \"system_uart_mc_tx\" for hierarchy \"system:inst_cpu\|system_uart_mc:uart_mc\|system_uart_mc_tx:the_system_uart_mc_tx\"" { } { { "system/synthesis/submodules/system_uart_mc.v" "the_system_uart_mc_tx" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_mc.v" 1068 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888322236 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_uart_mc_rx system:inst_cpu\|system_uart_mc:uart_mc\|system_uart_mc_rx:the_system_uart_mc_rx " "Elaborating entity \"system_uart_mc_rx\" for hierarchy \"system:inst_cpu\|system_uart_mc:uart_mc\|system_uart_mc_rx:the_system_uart_mc_rx\"" { } { { "system/synthesis/submodules/system_uart_mc.v" "the_system_uart_mc_rx" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_mc.v" 1086 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888322239 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_uart_mc_rx_stimulus_source system:inst_cpu\|system_uart_mc:uart_mc\|system_uart_mc_rx:the_system_uart_mc_rx\|system_uart_mc_rx_stimulus_source:the_system_uart_mc_rx_stimulus_source " "Elaborating entity \"system_uart_mc_rx_stimulus_source\" for hierarchy \"system:inst_cpu\|system_uart_mc:uart_mc\|system_uart_mc_rx:the_system_uart_mc_rx\|system_uart_mc_rx_stimulus_source:the_system_uart_mc_rx_stimulus_source\"" { } { { "system/synthesis/submodules/system_uart_mc.v" "the_system_uart_mc_rx_stimulus_source" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_mc.v" 569 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888322242 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_uart_mc_regs system:inst_cpu\|system_uart_mc:uart_mc\|system_uart_mc_regs:the_system_uart_mc_regs " "Elaborating entity \"system_uart_mc_regs\" for hierarchy \"system:inst_cpu\|system_uart_mc:uart_mc\|system_uart_mc_regs:the_system_uart_mc_regs\"" { } { { "system/synthesis/submodules/system_uart_mc.v" "the_system_uart_mc_regs" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_mc.v" 1117 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888322246 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_rs232_wifi system:inst_cpu\|system_rs232_wifi:rs232_wifi " "Elaborating entity \"system_rs232_wifi\" for hierarchy \"system:inst_cpu\|system_rs232_wifi:rs232_wifi\"" { } { { "system/synthesis/system.v" "rs232_wifi" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 994 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888322249 ""} +{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "write_data_parity system_rs232_wifi.v(123) " "Verilog HDL or VHDL warning at system_rs232_wifi.v(123): object \"write_data_parity\" assigned a value but never read" { } { { "system/synthesis/submodules/system_rs232_wifi.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_rs232_wifi.v" 123 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 -1 1393888322251 "|de0_nano_system|system:inst_cpu|system_rs232_wifi:rs232_wifi"} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_up_rs232_in_deserializer system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer " "Elaborating entity \"altera_up_rs232_in_deserializer\" for hierarchy \"system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\"" { } { { "system/synthesis/submodules/system_rs232_wifi.v" "RS232_In_Deserializer" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_rs232_wifi.v" 268 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888322252 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_up_rs232_counters system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_rs232_counters:RS232_In_Counters " "Elaborating entity \"altera_up_rs232_counters\" for hierarchy \"system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_rs232_counters:RS232_In_Counters\"" { } { { "system/synthesis/submodules/altera_up_rs232_in_deserializer.v" "RS232_In_Counters" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_up_rs232_in_deserializer.v" 181 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888322255 ""} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 altera_up_rs232_counters.v(124) " "Verilog HDL assignment warning at altera_up_rs232_counters.v(124): truncated value with size 32 to match size of target (14)" { } { { "system/synthesis/submodules/altera_up_rs232_counters.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_up_rs232_counters.v" 124 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 -1 1393888322256 "|de0_nano_system|system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_rs232_counters:RS232_In_Counters"} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_up_sync_fifo system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO " "Elaborating entity \"altera_up_sync_fifo\" for hierarchy \"system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\"" { } { { "system/synthesis/submodules/altera_up_rs232_in_deserializer.v" "RS232_In_FIFO" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_up_rs232_in_deserializer.v" 206 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888322258 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scfifo system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO " "Elaborating entity \"scfifo\" for hierarchy \"system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\"" { } { { "system/synthesis/submodules/altera_up_sync_fifo.v" "Sync_FIFO" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_up_sync_fifo.v" 157 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888322289 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO " "Elaborated megafunction instantiation \"system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\"" { } { { "system/synthesis/submodules/altera_up_sync_fifo.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_up_sync_fifo.v" 157 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1393888322290 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO " "Instantiated megafunction \"system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "add_ram_output_register OFF " "Parameter \"add_ram_output_register\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888322290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone II " "Parameter \"intended_device_family\" = \"Cyclone II\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888322290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_numwords 128 " "Parameter \"lpm_numwords\" = \"128\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888322290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_showahead ON " "Parameter \"lpm_showahead\" = \"ON\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888322290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type scfifo " "Parameter \"lpm_type\" = \"scfifo\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888322290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 8 " "Parameter \"lpm_width\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888322290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widthu 7 " "Parameter \"lpm_widthu\" = \"7\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888322290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "overflow_checking OFF " "Parameter \"overflow_checking\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888322290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "underflow_checking OFF " "Parameter \"underflow_checking\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888322290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "use_eab ON " "Parameter \"use_eab\" = \"ON\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888322290 ""} } { { "system/synthesis/submodules/altera_up_sync_fifo.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_up_sync_fifo.v" 157 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1393888322290 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/scfifo_a341.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/scfifo_a341.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 scfifo_a341 " "Found entity 1: scfifo_a341" { } { { "db/scfifo_a341.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/scfifo_a341.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888322345 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393888322345 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scfifo_a341 system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated " "Elaborating entity \"scfifo_a341\" for hierarchy \"system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\"" { } { { "scfifo.tdf" "auto_generated" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/scfifo.tdf" 296 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888322347 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_dpfifo_tq31.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/a_dpfifo_tq31.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_dpfifo_tq31 " "Found entity 1: a_dpfifo_tq31" { } { { "db/a_dpfifo_tq31.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/a_dpfifo_tq31.tdf" 32 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888322356 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393888322356 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_dpfifo_tq31 system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo " "Elaborating entity \"a_dpfifo_tq31\" for hierarchy \"system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\"" { } { { "db/scfifo_a341.tdf" "dpfifo" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/scfifo_a341.tdf" 37 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888322359 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_je81.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_je81.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_je81 " "Found entity 1: altsyncram_je81" { } { { "db/altsyncram_je81.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_je81.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888322420 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393888322420 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_je81 system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|altsyncram_je81:FIFOram " "Elaborating entity \"altsyncram_je81\" for hierarchy \"system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|altsyncram_je81:FIFOram\"" { } { { "db/a_dpfifo_tq31.tdf" "FIFOram" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/a_dpfifo_tq31.tdf" 45 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888322422 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cmpr_ks8.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cmpr_ks8.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cmpr_ks8 " "Found entity 1: cmpr_ks8" { } { { "db/cmpr_ks8.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/cmpr_ks8.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888322475 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393888322475 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cmpr_ks8 system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cmpr_ks8:almost_full_comparer " "Elaborating entity \"cmpr_ks8\" for hierarchy \"system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cmpr_ks8:almost_full_comparer\"" { } { { "db/a_dpfifo_tq31.tdf" "almost_full_comparer" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/a_dpfifo_tq31.tdf" 54 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888322477 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cmpr_ks8 system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cmpr_ks8:three_comparison " "Elaborating entity \"cmpr_ks8\" for hierarchy \"system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cmpr_ks8:three_comparison\"" { } { { "db/a_dpfifo_tq31.tdf" "three_comparison" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/a_dpfifo_tq31.tdf" 55 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888322481 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_v9b.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_v9b.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_v9b " "Found entity 1: cntr_v9b" { } { { "db/cntr_v9b.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/cntr_v9b.tdf" 25 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888322535 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393888322535 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_v9b system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_v9b:rd_ptr_msb " "Elaborating entity \"cntr_v9b\" for hierarchy \"system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_v9b:rd_ptr_msb\"" { } { { "db/a_dpfifo_tq31.tdf" "rd_ptr_msb" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/a_dpfifo_tq31.tdf" 56 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888322538 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_ca7.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_ca7.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_ca7 " "Found entity 1: cntr_ca7" { } { { "db/cntr_ca7.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/cntr_ca7.tdf" 25 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888322591 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393888322591 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_ca7 system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_ca7:usedw_counter " "Elaborating entity \"cntr_ca7\" for hierarchy \"system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_ca7:usedw_counter\"" { } { { "db/a_dpfifo_tq31.tdf" "usedw_counter" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/a_dpfifo_tq31.tdf" 57 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888322593 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_0ab.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_0ab.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_0ab " "Found entity 1: cntr_0ab" { } { { "db/cntr_0ab.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/cntr_0ab.tdf" 25 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888322648 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393888322648 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_0ab system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr " "Elaborating entity \"cntr_0ab\" for hierarchy \"system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr\"" { } { { "db/a_dpfifo_tq31.tdf" "wr_ptr" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/a_dpfifo_tq31.tdf" 58 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888322650 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_up_rs232_out_serializer system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_out_serializer:RS232_Out_Serializer " "Elaborating entity \"altera_up_rs232_out_serializer\" for hierarchy \"system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_out_serializer:RS232_Out_Serializer\"" { } { { "system/synthesis/submodules/system_rs232_wifi.v" "RS232_Out_Serializer" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_rs232_wifi.v" 290 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888322655 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_master_translator system:inst_cpu\|altera_merlin_master_translator:cpu_instruction_master_translator " "Elaborating entity \"altera_merlin_master_translator\" for hierarchy \"system:inst_cpu\|altera_merlin_master_translator:cpu_instruction_master_translator\"" { } { { "system/synthesis/system.v" "cpu_instruction_master_translator" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 1048 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888322713 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_master_translator system:inst_cpu\|altera_merlin_master_translator:cpu_data_master_translator " "Elaborating entity \"altera_merlin_master_translator\" for hierarchy \"system:inst_cpu\|altera_merlin_master_translator:cpu_data_master_translator\"" { } { { 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system:inst_cpu\|altera_merlin_burst_adapter:burst_adapter\|altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba " "Elaborating entity \"altera_merlin_burst_adapter_uncompressed_only\" for hierarchy \"system:inst_cpu\|altera_merlin_burst_adapter:burst_adapter\|altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba\"" { } { { "system/synthesis/submodules/altera_merlin_burst_adapter.sv" "altera_merlin_burst_adapter_uncompressed_only.the_ba" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_burst_adapter.sv" 397 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888322879 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_reset_controller system:inst_cpu\|altera_reset_controller:rst_controller " "Elaborating entity \"altera_reset_controller\" for hierarchy \"system:inst_cpu\|altera_reset_controller:rst_controller\"" { } { { "system/synthesis/system.v" "rst_controller" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 3733 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888322881 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_reset_synchronizer system:inst_cpu\|altera_reset_controller:rst_controller\|altera_reset_synchronizer:alt_rst_sync_uq1 " "Elaborating entity \"altera_reset_synchronizer\" for hierarchy \"system:inst_cpu\|altera_reset_controller:rst_controller\|altera_reset_synchronizer:alt_rst_sync_uq1\"" { } { { "system/synthesis/submodules/altera_reset_controller.v" "alt_rst_sync_uq1" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_reset_controller.v" 105 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888322883 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cmd_xbar_demux system:inst_cpu\|system_cmd_xbar_demux:cmd_xbar_demux " "Elaborating entity \"system_cmd_xbar_demux\" for hierarchy \"system:inst_cpu\|system_cmd_xbar_demux:cmd_xbar_demux\"" { } { { "system/synthesis/system.v" "cmd_xbar_demux" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 3756 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888322885 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cmd_xbar_demux_001 system:inst_cpu\|system_cmd_xbar_demux_001:cmd_xbar_demux_001 " "Elaborating entity \"system_cmd_xbar_demux_001\" for hierarchy \"system:inst_cpu\|system_cmd_xbar_demux_001:cmd_xbar_demux_001\"" { } { { "system/synthesis/system.v" "cmd_xbar_demux_001" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 3839 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888322887 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cmd_xbar_mux system:inst_cpu\|system_cmd_xbar_mux:cmd_xbar_mux " "Elaborating entity \"system_cmd_xbar_mux\" for hierarchy \"system:inst_cpu\|system_cmd_xbar_mux:cmd_xbar_mux\"" { } { { "system/synthesis/system.v" "cmd_xbar_mux" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 3862 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888322891 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arbitrator system:inst_cpu\|system_cmd_xbar_mux:cmd_xbar_mux\|altera_merlin_arbitrator:arb " "Elaborating entity \"altera_merlin_arbitrator\" for hierarchy \"system:inst_cpu\|system_cmd_xbar_mux:cmd_xbar_mux\|altera_merlin_arbitrator:arb\"" { } { { "system/synthesis/submodules/system_cmd_xbar_mux.sv" "arb" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cmd_xbar_mux.sv" 273 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888322895 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arb_adder system:inst_cpu\|system_cmd_xbar_mux:cmd_xbar_mux\|altera_merlin_arbitrator:arb\|altera_merlin_arb_adder:adder " "Elaborating entity \"altera_merlin_arb_adder\" for hierarchy \"system:inst_cpu\|system_cmd_xbar_mux:cmd_xbar_mux\|altera_merlin_arbitrator:arb\|altera_merlin_arb_adder:adder\"" { } { { "system/synthesis/submodules/altera_merlin_arbitrator.sv" "adder" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_arbitrator.sv" 169 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888322897 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_rsp_xbar_demux system:inst_cpu\|system_rsp_xbar_demux:rsp_xbar_demux " "Elaborating entity \"system_rsp_xbar_demux\" for hierarchy \"system:inst_cpu\|system_rsp_xbar_demux:rsp_xbar_demux\"" { } { { "system/synthesis/system.v" "rsp_xbar_demux" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 3908 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888322902 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_rsp_xbar_demux_002 system:inst_cpu\|system_rsp_xbar_demux_002:rsp_xbar_demux_002 " "Elaborating entity \"system_rsp_xbar_demux_002\" for hierarchy \"system:inst_cpu\|system_rsp_xbar_demux_002:rsp_xbar_demux_002\"" { } { { "system/synthesis/system.v" "rsp_xbar_demux_002" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 3948 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888322905 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_rsp_xbar_mux system:inst_cpu\|system_rsp_xbar_mux:rsp_xbar_mux " "Elaborating entity \"system_rsp_xbar_mux\" for hierarchy \"system:inst_cpu\|system_rsp_xbar_mux:rsp_xbar_mux\"" { } { { "system/synthesis/system.v" "rsp_xbar_mux" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 4124 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888322912 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arbitrator system:inst_cpu\|system_rsp_xbar_mux:rsp_xbar_mux\|altera_merlin_arbitrator:arb " "Elaborating entity \"altera_merlin_arbitrator\" for hierarchy \"system:inst_cpu\|system_rsp_xbar_mux:rsp_xbar_mux\|altera_merlin_arbitrator:arb\"" { } { { "system/synthesis/submodules/system_rsp_xbar_mux.sv" "arb" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_rsp_xbar_mux.sv" 296 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888322915 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_rsp_xbar_mux_001 system:inst_cpu\|system_rsp_xbar_mux_001:rsp_xbar_mux_001 " "Elaborating entity \"system_rsp_xbar_mux_001\" for hierarchy \"system:inst_cpu\|system_rsp_xbar_mux_001:rsp_xbar_mux_001\"" { } { { "system/synthesis/system.v" "rsp_xbar_mux_001" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 4207 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888322919 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arbitrator system:inst_cpu\|system_rsp_xbar_mux_001:rsp_xbar_mux_001\|altera_merlin_arbitrator:arb " "Elaborating entity \"altera_merlin_arbitrator\" for hierarchy \"system:inst_cpu\|system_rsp_xbar_mux_001:rsp_xbar_mux_001\|altera_merlin_arbitrator:arb\"" { } { { "system/synthesis/submodules/system_rsp_xbar_mux_001.sv" "arb" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_rsp_xbar_mux_001.sv" 456 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888322927 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arb_adder system:inst_cpu\|system_rsp_xbar_mux_001:rsp_xbar_mux_001\|altera_merlin_arbitrator:arb\|altera_merlin_arb_adder:adder " "Elaborating entity \"altera_merlin_arb_adder\" for hierarchy \"system:inst_cpu\|system_rsp_xbar_mux_001:rsp_xbar_mux_001\|altera_merlin_arbitrator:arb\|altera_merlin_arb_adder:adder\"" { } { { "system/synthesis/submodules/altera_merlin_arbitrator.sv" "adder" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_arbitrator.sv" 169 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888322930 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_width_adapter system:inst_cpu\|altera_merlin_width_adapter:width_adapter " "Elaborating entity \"altera_merlin_width_adapter\" for hierarchy \"system:inst_cpu\|altera_merlin_width_adapter:width_adapter\"" { } { { "system/synthesis/system.v" "width_adapter" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 4264 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888322932 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_width_adapter system:inst_cpu\|altera_merlin_width_adapter:width_adapter_001 " "Elaborating entity \"altera_merlin_width_adapter\" for hierarchy \"system:inst_cpu\|altera_merlin_width_adapter:width_adapter_001\"" { } { { "system/synthesis/system.v" "width_adapter_001" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 4321 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888322936 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_irq_mapper system:inst_cpu\|system_irq_mapper:irq_mapper " "Elaborating entity \"system_irq_mapper\" for hierarchy \"system:inst_cpu\|system_irq_mapper:irq_mapper\"" { } { { "system/synthesis/system.v" "irq_mapper" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 4333 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393888322942 ""} +{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "address_b system_cpu_traceram_lpm_dram_bdp_component 17 7 " "Port \"address_b\" on the entity instantiation of \"system_cpu_traceram_lpm_dram_bdp_component\" is connected to a signal of width 17. The formal width of the signal in the module is 7. The extra bits will be ignored." { } { { "system/synthesis/submodules/system_cpu.v" "system_cpu_traceram_lpm_dram_bdp_component" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } } 0 12020 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. The extra bits will be ignored." 0 0 "" 0 -1 1393888324690 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component"} +{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "jdo the_system_cpu_nios2_oci_itrace 38 16 " "Port \"jdo\" on the entity instantiation of \"the_system_cpu_nios2_oci_itrace\" is connected to a signal of width 38. The formal width of the signal in the module is 16. The extra bits will be ignored." { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_nios2_oci_itrace" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3606 0 0 } } } 0 12020 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. The extra bits will be ignored." 0 0 "" 0 -1 1393888324695 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_itrace:the_system_cpu_nios2_oci_itrace"} +{ "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_HDR" "" "Synthesized away the following node(s):" { { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_SUB_HDR" "RAM " "Synthesized away the following RAM node(s):" { { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[0\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[0\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 43 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393888325898 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a0"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[1\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[1\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 77 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393888325898 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a1"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[2\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[2\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 111 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393888325898 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a2"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[3\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[3\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 145 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393888325898 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a3"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[4\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[4\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 179 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393888325898 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a4"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[5\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[5\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 213 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393888325898 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a5"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[6\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[6\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 247 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393888325898 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a6"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[7\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[7\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 281 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393888325898 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a7"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[8\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[8\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 315 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393888325898 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a8"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[9\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[9\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 349 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393888325898 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a9"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[10\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[10\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 383 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393888325898 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a10"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[11\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[11\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 417 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393888325898 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a11"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[12\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[12\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 451 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393888325898 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a12"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[13\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[13\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 485 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393888325898 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a13"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[14\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[14\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 519 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393888325898 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a14"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[15\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[15\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 553 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393888325898 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a15"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[16\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[16\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 587 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393888325898 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a16"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[17\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[17\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 621 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393888325898 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a17"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[18\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[18\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 655 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393888325898 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a18"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[19\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[19\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 689 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393888325898 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a19"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[20\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[20\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 723 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393888325898 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a20"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[21\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[21\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 757 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393888325898 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a21"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[22\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[22\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 791 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393888325898 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a22"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[23\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[23\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 825 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393888325898 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a23"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[24\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[24\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 859 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393888325898 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a24"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[25\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[25\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 893 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393888325898 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a25"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[26\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[26\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 927 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393888325898 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a26"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[27\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[27\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 961 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393888325898 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a27"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[28\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[28\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 995 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393888325898 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a28"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[29\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[29\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 1029 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393888325898 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a29"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[30\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[30\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 1063 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393888325898 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a30"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[31\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[31\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 1097 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393888325898 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a31"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[32\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[32\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 1131 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393888325898 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a32"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[33\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[33\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 1165 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393888325898 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a33"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[34\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[34\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 1199 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393888325898 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a34"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[35\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[35\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 1233 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393888325898 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a35"} } { } 0 14285 "Synthesized away the following %1!s! node(s):" 0 0 "" 0 -1 1393888325898 ""} } { } 0 14284 "Synthesized away the following node(s):" 0 0 "" 0 -1 1393888325898 ""} +{ "Info" "ILPMS_INFERENCING_SUMMARY" "1 " "Inferred 1 megafunctions from design logic" { { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "system:inst_cpu\|system_cpu:cpu\|Add17 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"system:inst_cpu\|system_cpu:cpu\|Add17\"" { } { { "system/synthesis/submodules/system_cpu.v" "Add17" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 8743 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1 1393888331457 ""} } { } 0 278001 "Inferred %1!llu! megafunctions from design logic" 0 0 "" 0 -1 1393888331457 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_cpu:cpu\|lpm_add_sub:Add17 " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|lpm_add_sub:Add17\"" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 8743 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1393888331495 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_cpu:cpu\|lpm_add_sub:Add17 " "Instantiated megafunction \"system:inst_cpu\|system_cpu:cpu\|lpm_add_sub:Add17\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 33 " "Parameter \"LPM_WIDTH\" = \"33\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888331496 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION DEFAULT " "Parameter \"LPM_DIRECTION\" = \"DEFAULT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888331496 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888331496 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT NO " "Parameter \"ONE_INPUT_IS_CONSTANT\" = \"NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393888331496 ""} } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 8743 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1393888331496 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_qvi.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/add_sub_qvi.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_qvi " "Found entity 1: add_sub_qvi" { } { { "db/add_sub_qvi.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/add_sub_qvi.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393888331550 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393888331550 ""} +{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "2 " "2 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "" 0 -1 1393888332682 ""} +{ "Warning" "WMLS_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC_HDR" "" "The following nodes have both tri-state and non-tri-state drivers" { { "Warning" "WMLS_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC" "GPIO_0\[33\] " "Inserted always-enabled tri-state buffer between \"GPIO_0\[33\]\" and its non-tri-state driver." { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13035 "Inserted always-enabled tri-state buffer between \"%1!s!\" and its non-tri-state driver." 0 0 "" 0 -1 1393888332888 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC" "GPIO_1\[0\] " "Inserted always-enabled tri-state buffer between \"GPIO_1\[0\]\" and its non-tri-state driver." { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13035 "Inserted always-enabled tri-state buffer between \"%1!s!\" and its non-tri-state driver." 0 0 "" 0 -1 1393888332888 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC" "GPIO_1\[33\] " "Inserted always-enabled tri-state buffer between \"GPIO_1\[33\]\" and its non-tri-state driver." { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13035 "Inserted always-enabled tri-state buffer between \"%1!s!\" and its non-tri-state driver." 0 0 "" 0 -1 1393888332888 ""} } { } 0 13034 "The following nodes have both tri-state and non-tri-state drivers" 0 0 "" 0 -1 1393888332888 ""} +{ "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI_HDR" "" "The following bidir pins have no drivers" { { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[0\] " "Bidir \"GPIO_0\[0\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393888332888 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[1\] " "Bidir \"GPIO_0\[1\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393888332888 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[2\] " "Bidir \"GPIO_0\[2\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393888332888 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[3\] " "Bidir \"GPIO_0\[3\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393888332888 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[4\] " "Bidir \"GPIO_0\[4\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393888332888 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[5\] " "Bidir \"GPIO_0\[5\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393888332888 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[6\] " "Bidir \"GPIO_0\[6\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393888332888 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[7\] " "Bidir \"GPIO_0\[7\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393888332888 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[8\] " "Bidir \"GPIO_0\[8\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393888332888 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[9\] " "Bidir \"GPIO_0\[9\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393888332888 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[10\] " "Bidir \"GPIO_0\[10\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393888332888 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[11\] " "Bidir \"GPIO_0\[11\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393888332888 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[12\] " "Bidir \"GPIO_0\[12\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393888332888 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[13\] " "Bidir \"GPIO_0\[13\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393888332888 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[14\] " "Bidir \"GPIO_0\[14\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393888332888 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[15\] " "Bidir \"GPIO_0\[15\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393888332888 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[16\] " "Bidir \"GPIO_0\[16\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393888332888 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[17\] " "Bidir \"GPIO_0\[17\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393888332888 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[18\] " "Bidir \"GPIO_0\[18\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393888332888 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[19\] " "Bidir \"GPIO_0\[19\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393888332888 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[20\] " "Bidir \"GPIO_0\[20\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393888332888 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[21\] " "Bidir \"GPIO_0\[21\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393888332888 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[22\] " "Bidir \"GPIO_0\[22\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393888332888 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[23\] " "Bidir \"GPIO_0\[23\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393888332888 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[24\] " "Bidir \"GPIO_0\[24\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393888332888 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[25\] " "Bidir \"GPIO_0\[25\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393888332888 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[26\] " "Bidir \"GPIO_0\[26\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393888332888 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[27\] " "Bidir \"GPIO_0\[27\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393888332888 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[28\] " "Bidir \"GPIO_0\[28\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393888332888 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[29\] " "Bidir \"GPIO_0\[29\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393888332888 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[30\] " "Bidir \"GPIO_0\[30\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393888332888 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[32\] " "Bidir \"GPIO_0\[32\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393888332888 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[1\] " "Bidir \"GPIO_1\[1\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393888332888 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[2\] " "Bidir \"GPIO_1\[2\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393888332888 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[3\] " "Bidir \"GPIO_1\[3\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393888332888 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[4\] " "Bidir \"GPIO_1\[4\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393888332888 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[5\] " "Bidir \"GPIO_1\[5\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393888332888 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[6\] " "Bidir \"GPIO_1\[6\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393888332888 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[7\] " "Bidir \"GPIO_1\[7\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393888332888 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[8\] " "Bidir \"GPIO_1\[8\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393888332888 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[9\] " "Bidir \"GPIO_1\[9\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393888332888 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[10\] " "Bidir \"GPIO_1\[10\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393888332888 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[11\] " "Bidir \"GPIO_1\[11\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393888332888 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[12\] " "Bidir \"GPIO_1\[12\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393888332888 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[13\] " "Bidir \"GPIO_1\[13\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393888332888 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[14\] " "Bidir \"GPIO_1\[14\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393888332888 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[15\] " "Bidir \"GPIO_1\[15\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393888332888 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[16\] " "Bidir \"GPIO_1\[16\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393888332888 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[17\] " "Bidir \"GPIO_1\[17\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393888332888 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[18\] " "Bidir \"GPIO_1\[18\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393888332888 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[19\] " "Bidir \"GPIO_1\[19\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393888332888 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[20\] " "Bidir \"GPIO_1\[20\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393888332888 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[21\] " "Bidir \"GPIO_1\[21\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393888332888 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[22\] " "Bidir \"GPIO_1\[22\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393888332888 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[23\] " "Bidir \"GPIO_1\[23\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393888332888 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[24\] " "Bidir \"GPIO_1\[24\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393888332888 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[25\] " "Bidir \"GPIO_1\[25\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393888332888 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[26\] " "Bidir \"GPIO_1\[26\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393888332888 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[27\] " "Bidir \"GPIO_1\[27\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393888332888 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[28\] " "Bidir \"GPIO_1\[28\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393888332888 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[29\] " "Bidir \"GPIO_1\[29\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393888332888 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[30\] " "Bidir \"GPIO_1\[30\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393888332888 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[32\] " "Bidir \"GPIO_1\[32\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393888332888 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[31\] " "Bidir \"GPIO_0\[31\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393888332888 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[31\] " "Bidir \"GPIO_1\[31\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393888332888 ""} } { } 0 13039 "The following bidir pins have no drivers" 0 0 "" 0 -1 1393888332888 ""} +{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" { } { { "system/synthesis/submodules/system_sdram.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_sdram.v" 440 -1 0 } } { "system/synthesis/submodules/system_sdram.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_sdram.v" 354 -1 0 } } { "system/synthesis/submodules/altera_reset_synchronizer.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_reset_synchronizer.v" 62 -1 0 } } { "system/synthesis/submodules/system_sdram.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_sdram.v" 304 -1 0 } } { "system/synthesis/submodules/altera_merlin_slave_translator.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_slave_translator.sv" 277 -1 0 } } { "system/synthesis/submodules/system_jtag_uart_0.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_jtag_uart_0.v" 558 -1 0 } } { "alt_jtag_atlantic.v" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/alt_jtag_atlantic.v" 291 -1 0 } } { "system/synthesis/submodules/system_uart_mc.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_mc.v" 89 -1 0 } } { "system/synthesis/submodules/altera_merlin_arbitrator.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_arbitrator.sv" 203 -1 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 5563 -1 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 5963 -1 0 } } { "system/synthesis/submodules/system_jtag_uart_0.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_jtag_uart_0.v" 603 -1 0 } } { "system/synthesis/submodules/system_uart_mc.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_mc.v" 105 -1 0 } } { "alt_jtag_atlantic.v" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/alt_jtag_atlantic.v" 224 -1 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 5995 -1 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 9343 -1 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 9492 -1 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 982 -1 0 } } { "system/synthesis/submodules/system_uart_mc.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_mc.v" 87 -1 0 } } { "system/synthesis/submodules/system_uart_wifi.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_wifi.v" 88 -1 0 } } { "system/synthesis/submodules/system_uart_wifi.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_wifi.v" 87 -1 0 } } { "system/synthesis/submodules/system_uart_mc.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_mc.v" 88 -1 0 } } { "system/synthesis/submodules/system_sys_clk_timer.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_sys_clk_timer.v" 166 -1 0 } } { "system/synthesis/submodules/system_sys_clk_timer.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_sys_clk_timer.v" 175 -1 0 } } { "system/synthesis/submodules/system_uart_wifi.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_wifi.v" 891 -1 0 } } } 0 13000 "Registers with preset signals will power-up high" 0 0 "" 0 -1 1393888333045 ""} +{ "Info" "IMLS_MLS_DEV_CLRN_SETS_REGISTERS" "" "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" { } { } 0 13003 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "" 0 -1 1393888333046 ""} +{ "Warning" "WMLS_MLS_ENABLED_OE" "" "TRI or OPNDRN buffers permanently enabled" { { "Warning" "WMLS_MLS_NODE_NAME" "GPIO_0\[33\]~synth " "Node \"GPIO_0\[33\]~synth\"" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13010 "Node \"%1!s!\"" 0 0 "" 0 -1 1393888335237 ""} { "Warning" "WMLS_MLS_NODE_NAME" "GPIO_1\[0\]~synth " "Node \"GPIO_1\[0\]~synth\"" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13010 "Node \"%1!s!\"" 0 0 "" 0 -1 1393888335237 ""} { "Warning" "WMLS_MLS_NODE_NAME" "GPIO_1\[33\]~synth " "Node \"GPIO_1\[33\]~synth\"" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13010 "Node \"%1!s!\"" 0 0 "" 0 -1 1393888335237 ""} } { } 0 13009 "TRI or OPNDRN buffers permanently enabled" 0 0 "" 0 -1 1393888335237 ""} +{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "DRAM_CKE VCC " "Pin \"DRAM_CKE\" is stuck at VCC" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 62 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1 1393888335238 "|de0_nano_system|DRAM_CKE"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "" 0 -1 1393888335238 ""} +{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING_ON_PARTITION" "Top " "Timing-Driven Synthesis is running on partition \"Top\"" { } { } 0 286031 "Timing-Driven Synthesis is running on partition \"%1!s!\"" 0 0 "" 0 -1 1393888335810 ""} +{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "378 " "378 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "" 0 -1 1393888338580 ""} +{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "1 0 1 0 0 " "Adding 1 node(s), including 0 DDIO, 1 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "" 0 -1 1393888340000 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "" 0 -1 1393888340000 ""} +{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "1 " "Design contains 1 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[0\] " "No output dependent on input pin \"KEY\[0\]\"" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 74 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1 1393888340642 "|de0_nano_system|KEY[0]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0 -1 1393888340642 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "5738 " "Implemented 5738 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "10 " "Implemented 10 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "" 0 -1 1393888340643 ""} { "Info" "ICUT_CUT_TM_OPINS" "32 " "Implemented 32 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "" 0 -1 1393888340643 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "84 " "Implemented 84 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "" 0 -1 1393888340643 ""} { "Info" "ICUT_CUT_TM_LCELLS" "5343 " "Implemented 5343 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "" 0 -1 1393888340643 ""} { "Info" "ICUT_CUT_TM_RAMS" "263 " "Implemented 263 RAM segments" { } { } 0 21064 "Implemented %1!d! RAM segments" 0 0 "" 0 -1 1393888340643 ""} { "Info" "ICUT_CUT_TM_PLLS" "1 " "Implemented 1 PLLs" { } { } 0 21065 "Implemented %1!d! PLLs" 0 0 "" 0 -1 1393888340643 ""} { "Info" "ICUT_CUT_TM_DSP_ELEM" "4 " "Implemented 4 DSP elements" { } { } 0 21062 "Implemented %1!d! DSP elements" 0 0 "" 0 -1 1393888340643 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1 1393888340643 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 130 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 130 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "644 " "Peak virtual memory: 644 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1 1393888340780 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 03 16:12:20 2014 " "Processing ended: Mon Mar 03 16:12:20 2014" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1 1393888340780 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:23 " "Elapsed time: 00:00:23" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1 1393888340780 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:22 " "Total CPU time (on all processors): 00:00:22" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1 1393888340780 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1 1393888340780 ""} diff --git a/MCandWifiTestDE0/db/de0_nano_system.map.rdb b/MCandWifiTestDE0/db/de0_nano_system.map.rdb index 9f9de110..f431d0b0 100644 Binary files a/MCandWifiTestDE0/db/de0_nano_system.map.rdb and b/MCandWifiTestDE0/db/de0_nano_system.map.rdb differ diff --git a/MCandWifiTestDE0/db/de0_nano_system.map_bb.cdb b/MCandWifiTestDE0/db/de0_nano_system.map_bb.cdb index 686f582f..5e169fdd 100644 Binary files a/MCandWifiTestDE0/db/de0_nano_system.map_bb.cdb and b/MCandWifiTestDE0/db/de0_nano_system.map_bb.cdb differ diff --git a/MCandWifiTestDE0/db/de0_nano_system.map_bb.hdb b/MCandWifiTestDE0/db/de0_nano_system.map_bb.hdb index 54874bdf..5babf595 100644 Binary files a/MCandWifiTestDE0/db/de0_nano_system.map_bb.hdb and b/MCandWifiTestDE0/db/de0_nano_system.map_bb.hdb differ diff --git a/MCandWifiTestDE0/db/de0_nano_system.pre_map.cdb b/MCandWifiTestDE0/db/de0_nano_system.pre_map.cdb index cefaa14c..11c9cf2a 100644 Binary files a/MCandWifiTestDE0/db/de0_nano_system.pre_map.cdb and b/MCandWifiTestDE0/db/de0_nano_system.pre_map.cdb differ diff --git a/MCandWifiTestDE0/db/de0_nano_system.pre_map.hdb b/MCandWifiTestDE0/db/de0_nano_system.pre_map.hdb index 827b5580..fcae7cd5 100644 Binary files a/MCandWifiTestDE0/db/de0_nano_system.pre_map.hdb and b/MCandWifiTestDE0/db/de0_nano_system.pre_map.hdb differ diff --git a/MCandWifiTestDE0/db/de0_nano_system.root_partition.map.reg_db.cdb b/MCandWifiTestDE0/db/de0_nano_system.root_partition.map.reg_db.cdb index 7050a186..70367f3d 100644 Binary files a/MCandWifiTestDE0/db/de0_nano_system.root_partition.map.reg_db.cdb and b/MCandWifiTestDE0/db/de0_nano_system.root_partition.map.reg_db.cdb differ diff --git a/MCandWifiTestDE0/db/de0_nano_system.routing.rdb b/MCandWifiTestDE0/db/de0_nano_system.routing.rdb index 83518ea3..9353c12a 100644 Binary files a/MCandWifiTestDE0/db/de0_nano_system.routing.rdb and b/MCandWifiTestDE0/db/de0_nano_system.routing.rdb differ diff --git a/MCandWifiTestDE0/db/de0_nano_system.rtlv.hdb b/MCandWifiTestDE0/db/de0_nano_system.rtlv.hdb index 9dad7a15..bad122f3 100644 Binary files a/MCandWifiTestDE0/db/de0_nano_system.rtlv.hdb and b/MCandWifiTestDE0/db/de0_nano_system.rtlv.hdb differ diff --git a/MCandWifiTestDE0/db/de0_nano_system.rtlv_sg.cdb b/MCandWifiTestDE0/db/de0_nano_system.rtlv_sg.cdb index 7d1a924c..09fd5f17 100644 Binary files a/MCandWifiTestDE0/db/de0_nano_system.rtlv_sg.cdb and b/MCandWifiTestDE0/db/de0_nano_system.rtlv_sg.cdb differ diff --git a/MCandWifiTestDE0/db/de0_nano_system.sgdiff.cdb b/MCandWifiTestDE0/db/de0_nano_system.sgdiff.cdb index 7aad86a2..bfbe86c7 100644 Binary files a/MCandWifiTestDE0/db/de0_nano_system.sgdiff.cdb and b/MCandWifiTestDE0/db/de0_nano_system.sgdiff.cdb differ diff --git a/MCandWifiTestDE0/db/de0_nano_system.sgdiff.hdb b/MCandWifiTestDE0/db/de0_nano_system.sgdiff.hdb index 571aee86..7419f477 100644 Binary files a/MCandWifiTestDE0/db/de0_nano_system.sgdiff.hdb and b/MCandWifiTestDE0/db/de0_nano_system.sgdiff.hdb differ diff --git a/MCandWifiTestDE0/db/de0_nano_system.sld_design_entry_dsc.sci b/MCandWifiTestDE0/db/de0_nano_system.sld_design_entry_dsc.sci index 4d40eada..e5a7cb99 100644 Binary files a/MCandWifiTestDE0/db/de0_nano_system.sld_design_entry_dsc.sci and b/MCandWifiTestDE0/db/de0_nano_system.sld_design_entry_dsc.sci differ diff --git a/MCandWifiTestDE0/db/de0_nano_system.sta.qmsg b/MCandWifiTestDE0/db/de0_nano_system.sta.qmsg index 074038f5..b5960944 100644 --- a/MCandWifiTestDE0/db/de0_nano_system.sta.qmsg +++ b/MCandWifiTestDE0/db/de0_nano_system.sta.qmsg @@ -1,45 +1,45 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1 1393811691767 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Full Version " "Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1 1393811691767 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Mar 02 18:54:51 2014 " "Processing started: Sun Mar 02 18:54:51 2014" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1 1393811691767 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1 1393811691767 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta de0_nano_system -c de0_nano_system " "Command: quartus_sta de0_nano_system -c de0_nano_system" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1 1393811691767 ""} -{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "" 0 0 1393811691827 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." { } { } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "" 0 -1 1393811692157 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "" 0 -1 1393811692157 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "" 0 -1 1393811692207 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "" 0 -1 1393811692207 ""} -{ "Info" "ISTA_SDC_STATEMENT_PARENT" "" "Evaluating HDL-embedded SDC commands" { { "Info" "ISTA_SDC_STATEMENT_ENTITY" "alt_jtag_atlantic " "Entity alt_jtag_atlantic" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate1*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate1*\}\] " { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393811692907 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393811692907 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393811692907 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393811692907 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393811692907 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393811692907 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393811692907 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393811692907 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393811692907 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|read1*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|read1*\}\] " { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393811692907 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read_req\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read_req\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393811692907 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393811692907 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|tck_t_dav\}\] " "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|tck_t_dav\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393811692907 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|user_saw_rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid0*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|user_saw_rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid0*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393811692907 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393811692907 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393811692907 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393811692907 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393811692907 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393811692907 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393811692907 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393811692907 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393811692907 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write1*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write1*\}\] " { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393811692907 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_ena*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_ena*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393811692907 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_pause*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_pause*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393811692907 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_valid\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_valid\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393811692907 ""} } { } 0 332165 "Entity %1!s!" 0 0 "" 0 -1 1393811692907 ""} { "Info" "ISTA_SDC_STATEMENT_ENTITY" "altera_std_synchronizer " "Entity altera_std_synchronizer" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -to \[get_keepers \{*altera_std_synchronizer:*\|din_s1\}\] " "set_false_path -to \[get_keepers \{*altera_std_synchronizer:*\|din_s1\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393811692907 ""} } { } 0 332165 "Entity %1!s!" 0 0 "" 0 -1 1393811692907 ""} { "Info" "ISTA_SDC_STATEMENT_ENTITY" "sld_jtag_hub " "Entity sld_jtag_hub" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "create_clock -period 10MHz -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] " "create_clock -period 10MHz -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393811692907 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_clock_groups -asynchronous -group \{altera_reserved_tck\} " "set_clock_groups -asynchronous -group \{altera_reserved_tck\}" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393811692907 ""} } { } 0 332165 "Entity %1!s!" 0 0 "" 0 -1 1393811692907 ""} } { } 0 332164 "Evaluating HDL-embedded SDC commands" 0 0 "" 0 -1 1393811692907 ""} -{ "Info" "ISTA_SDC_FOUND" "de0_nano_system.sdc " "Reading SDC File: 'de0_nano_system.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "" 0 -1 1393811692947 ""} -{ "Warning" "WSTA_OVERWRITING_EXISTING_CLOCK" "altera_reserved_tck " "Overwriting existing clock: altera_reserved_tck" { } { } 0 332043 "Overwriting existing clock: %1!s!" 0 0 "" 0 -1 1393811692947 ""} -{ "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "Deriving PLL clocks " "Deriving PLL clocks" { { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -duty_cycle 50.00 -name \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} " "create_generated_clock -source \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -duty_cycle 50.00 -name \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}" { } { } 0 332110 "%1!s!" 0 0 "" 0 -1 1393811692947 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -phase -54.00 -duty_cycle 50.00 -name \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} " "create_generated_clock -source \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -phase -54.00 -duty_cycle 50.00 -name \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}" { } { } 0 332110 "%1!s!" 0 0 "" 0 -1 1393811692947 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 5 -duty_cycle 50.00 -name \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} " "create_generated_clock -source \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 5 -duty_cycle 50.00 -name \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\]\}" { } { } 0 332110 "%1!s!" 0 0 "" 0 -1 1393811692947 ""} } { } 0 332110 "%1!s!" 0 0 "" 0 -1 1393811692947 ""} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_CALL_IS_DELAYED" "" "Clock uncertainty is not calculated until you update the timing netlist." { } { } 0 332151 "Clock uncertainty is not calculated until you update the timing netlist." 0 0 "" 0 -1 1393811692947 ""} -{ "Info" "ISTA_SDC_FOUND" "system/synthesis/submodules/altera_reset_controller.sdc " "Reading SDC File: 'system/synthesis/submodules/altera_reset_controller.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "" 0 -1 1393811692957 ""} -{ "Info" "ISTA_SDC_FOUND" "system/synthesis/submodules/system_cpu.sdc " "Reading SDC File: 'system/synthesis/submodules/system_cpu.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "" 0 -1 1393811692977 ""} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "" 0 -1 1393811693197 ""} -{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "" 0 0 1393811693197 ""} -{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "" 0 0 1393811693217 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup 1.944 " "Worst-case setup slack is 1.944" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393811693287 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393811693287 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.944 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 1.944 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393811693287 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 97.388 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 97.388 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393811693287 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1393811693287 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.246 " "Worst-case hold slack is 0.246" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393811693307 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393811693307 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.246 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.246 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393811693307 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.361 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 0.361 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393811693307 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1393811693307 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 2.156 " "Worst-case recovery slack is 2.156" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393811693317 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393811693317 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 2.156 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 2.156 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393811693317 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1393811693317 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "removal 2.023 " "Worst-case removal slack is 2.023" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393811693327 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393811693327 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 2.023 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 2.023 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393811693327 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1393811693327 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 4.693 " "Worst-case minimum pulse width slack is 4.693" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393811693357 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393811693357 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.693 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 4.693 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393811693357 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 9.835 0.000 CLOCK_50 " " 9.835 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393811693357 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 49.624 0.000 altera_reserved_tck " " 49.624 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393811693357 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 49.747 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 49.747 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393811693357 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1393811693357 ""} -{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 6 synchronizer chains. " "Report Metastability: Found 6 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n " "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393811693647 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 6 " "Number of Synchronizer Chains Found: 6" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393811693647 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393811693647 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 0.333 " "Fraction of Chains for which MTBFs Could Not be Calculated: 0.333" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393811693647 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 16.778 ns " "Worst Case Available Settling Time: 16.778 ns" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393811693647 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393811693647 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. " "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions." { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393811693647 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8 " " - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393811693647 ""} } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393811693647 ""} -{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "" 0 0 1393811693657 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "" 0 -1 1393811693697 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "" 0 -1 1393811694497 ""} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "" 0 -1 1393811694858 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup 2.250 " "Worst-case setup slack is 2.250" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393811694928 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393811694928 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 2.250 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 2.250 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393811694928 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 97.707 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 97.707 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393811694928 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1393811694928 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.242 " "Worst-case hold slack is 0.242" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393811694958 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393811694958 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.242 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.242 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393811694958 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.320 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 0.320 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393811694958 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1393811694958 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 2.469 " "Worst-case recovery slack is 2.469" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393811695118 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393811695118 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 2.469 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 2.469 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393811695118 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1393811695118 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "removal 1.807 " "Worst-case removal slack is 1.807" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393811695268 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393811695268 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.807 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 1.807 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393811695268 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1393811695268 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 4.719 " "Worst-case minimum pulse width slack is 4.719" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393811695278 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393811695278 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.719 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 4.719 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393811695278 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 9.818 0.000 CLOCK_50 " " 9.818 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393811695278 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 49.604 0.000 altera_reserved_tck " " 49.604 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393811695278 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 49.744 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 49.744 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393811695278 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1393811695278 ""} -{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 6 synchronizer chains. " "Report Metastability: Found 6 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n " "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393811695928 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 6 " "Number of Synchronizer Chains Found: 6" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393811695928 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393811695928 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 0.333 " "Fraction of Chains for which MTBFs Could Not be Calculated: 0.333" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393811695928 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 17.094 ns " "Worst Case Available Settling Time: 17.094 ns" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393811695928 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393811695928 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. " "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions." { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393811695928 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8 " " - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393811695928 ""} } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393811695928 ""} -{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "" 0 0 1393811695938 ""} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "" 0 -1 1393811696338 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup 3.218 " "Worst-case setup slack is 3.218" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393811696368 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393811696368 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 3.218 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 3.218 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393811696368 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 98.512 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 98.512 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393811696368 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1393811696368 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.110 " "Worst-case hold slack is 0.110" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393811696428 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393811696428 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.110 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.110 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393811696428 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.193 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 0.193 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393811696428 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1393811696428 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 3.339 " "Worst-case recovery slack is 3.339" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393811696448 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393811696448 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 3.339 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 3.339 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393811696448 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1393811696448 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "removal 1.171 " "Worst-case removal slack is 1.171" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393811696468 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393811696468 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.171 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 1.171 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393811696468 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1393811696468 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 4.749 " "Worst-case minimum pulse width slack is 4.749" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393811696478 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393811696478 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.749 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 4.749 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393811696478 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 9.587 0.000 CLOCK_50 " " 9.587 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393811696478 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 49.482 0.000 altera_reserved_tck " " 49.482 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393811696478 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 49.782 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 49.782 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393811696478 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1393811696478 ""} -{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 6 synchronizer chains. " "Report Metastability: Found 6 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n " "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393811696828 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 6 " "Number of Synchronizer Chains Found: 6" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393811696828 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393811696828 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 0.333 " "Fraction of Chains for which MTBFs Could Not be Calculated: 0.333" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393811696828 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 18.234 ns " "Worst Case Available Settling Time: 18.234 ns" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393811696828 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393811696828 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. " "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions." { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393811696828 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8 " " - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393811696828 ""} } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393811696828 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "" 0 -1 1393811697648 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "" 0 -1 1393811697648 ""} -{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 1 Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "563 " "Peak virtual memory: 563 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1 1393811697978 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Mar 02 18:54:57 2014 " "Processing ended: Sun Mar 02 18:54:57 2014" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1 1393811697978 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1 1393811697978 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:07 " "Total CPU time (on all processors): 00:00:07" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1 1393811697978 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1 1393811697978 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1 1393888388333 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Full Version " "Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1 1393888388334 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 03 16:13:07 2014 " "Processing started: Mon Mar 03 16:13:07 2014" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1 1393888388334 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1 1393888388334 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta de0_nano_system -c de0_nano_system " "Command: quartus_sta de0_nano_system -c de0_nano_system" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1 1393888388334 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "" 0 0 1393888388395 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." { } { } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "" 0 -1 1393888388725 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "" 0 -1 1393888388725 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "" 0 -1 1393888388779 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "" 0 -1 1393888388779 ""} +{ "Info" "ISTA_SDC_STATEMENT_PARENT" "" "Evaluating HDL-embedded SDC commands" { { "Info" "ISTA_SDC_STATEMENT_ENTITY" "alt_jtag_atlantic " "Entity alt_jtag_atlantic" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate1*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate1*\}\] " { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393888389479 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393888389479 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393888389479 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393888389479 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393888389479 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393888389479 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393888389479 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393888389479 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393888389479 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|read1*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|read1*\}\] " { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393888389479 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read_req\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read_req\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393888389479 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393888389479 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|tck_t_dav\}\] " "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|tck_t_dav\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393888389479 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|user_saw_rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid0*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|user_saw_rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid0*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393888389479 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393888389479 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393888389479 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393888389479 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393888389479 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393888389479 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393888389479 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393888389479 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393888389479 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write1*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write1*\}\] " { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393888389479 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_ena*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_ena*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393888389479 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_pause*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_pause*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393888389479 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_valid\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_valid\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393888389479 ""} } { } 0 332165 "Entity %1!s!" 0 0 "" 0 -1 1393888389479 ""} { "Info" "ISTA_SDC_STATEMENT_ENTITY" "altera_std_synchronizer " "Entity altera_std_synchronizer" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -to \[get_keepers \{*altera_std_synchronizer:*\|din_s1\}\] " "set_false_path -to \[get_keepers \{*altera_std_synchronizer:*\|din_s1\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393888389479 ""} } { } 0 332165 "Entity %1!s!" 0 0 "" 0 -1 1393888389479 ""} { "Info" "ISTA_SDC_STATEMENT_ENTITY" "sld_jtag_hub " "Entity sld_jtag_hub" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "create_clock -period 10MHz -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] " "create_clock -period 10MHz -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393888389479 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_clock_groups -asynchronous -group \{altera_reserved_tck\} " "set_clock_groups -asynchronous -group \{altera_reserved_tck\}" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393888389479 ""} } { } 0 332165 "Entity %1!s!" 0 0 "" 0 -1 1393888389479 ""} } { } 0 332164 "Evaluating HDL-embedded SDC commands" 0 0 "" 0 -1 1393888389479 ""} +{ "Info" "ISTA_SDC_FOUND" "de0_nano_system.sdc " "Reading SDC File: 'de0_nano_system.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "" 0 -1 1393888389527 ""} +{ "Warning" "WSTA_OVERWRITING_EXISTING_CLOCK" "altera_reserved_tck " "Overwriting existing clock: altera_reserved_tck" { } { } 0 332043 "Overwriting existing clock: %1!s!" 0 0 "" 0 -1 1393888389527 ""} +{ "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "Deriving PLL clocks " "Deriving PLL clocks" { { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -duty_cycle 50.00 -name \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} " "create_generated_clock -source \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -duty_cycle 50.00 -name \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}" { } { } 0 332110 "%1!s!" 0 0 "" 0 -1 1393888389529 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -phase -54.00 -duty_cycle 50.00 -name \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} " "create_generated_clock -source \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -phase -54.00 -duty_cycle 50.00 -name \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}" { } { } 0 332110 "%1!s!" 0 0 "" 0 -1 1393888389529 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 5 -duty_cycle 50.00 -name \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} " "create_generated_clock -source \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 5 -duty_cycle 50.00 -name \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\]\}" { } { } 0 332110 "%1!s!" 0 0 "" 0 -1 1393888389529 ""} } { } 0 332110 "%1!s!" 0 0 "" 0 -1 1393888389529 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_CALL_IS_DELAYED" "" "Clock uncertainty is not calculated until you update the timing netlist." { } { } 0 332151 "Clock uncertainty is not calculated until you update the timing netlist." 0 0 "" 0 -1 1393888389529 ""} +{ "Info" "ISTA_SDC_FOUND" "system/synthesis/submodules/altera_reset_controller.sdc " "Reading SDC File: 'system/synthesis/submodules/altera_reset_controller.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "" 0 -1 1393888389533 ""} +{ "Info" "ISTA_SDC_FOUND" "system/synthesis/submodules/system_cpu.sdc " "Reading SDC File: 'system/synthesis/submodules/system_cpu.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "" 0 -1 1393888389555 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "" 0 -1 1393888389776 ""} +{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "" 0 0 1393888389779 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "" 0 0 1393888389795 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup 2.068 " "Worst-case setup slack is 2.068" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393888389861 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393888389861 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 2.068 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 2.068 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393888389861 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 97.388 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 97.388 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393888389861 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1393888389861 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.230 " "Worst-case hold slack is 0.230" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393888389885 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393888389885 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.230 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.230 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393888389885 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.361 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 0.361 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393888389885 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1393888389885 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 1.948 " "Worst-case recovery slack is 1.948" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393888389896 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393888389896 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.948 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 1.948 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393888389896 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1393888389896 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "removal 2.524 " "Worst-case removal slack is 2.524" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393888389907 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393888389907 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 2.524 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 2.524 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393888389907 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1393888389907 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 4.694 " "Worst-case minimum pulse width slack is 4.694" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393888389914 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393888389914 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.694 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 4.694 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393888389914 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 9.835 0.000 CLOCK_50 " " 9.835 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393888389914 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 49.640 0.000 altera_reserved_tck " " 49.640 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393888389914 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 49.747 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 49.747 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393888389914 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1393888389914 ""} +{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 6 synchronizer chains. " "Report Metastability: Found 6 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n " "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393888390203 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 6 " "Number of Synchronizer Chains Found: 6" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393888390203 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393888390203 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 0.333 " "Fraction of Chains for which MTBFs Could Not be Calculated: 0.333" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393888390203 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 17.228 ns " "Worst Case Available Settling Time: 17.228 ns" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393888390203 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393888390203 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. " "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions." { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393888390203 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8 " " - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393888390203 ""} } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393888390203 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "" 0 0 1393888390212 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "" 0 -1 1393888390248 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "" 0 -1 1393888391065 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "" 0 -1 1393888391419 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup 2.461 " "Worst-case setup slack is 2.461" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393888391488 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393888391488 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 2.461 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 2.461 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393888391488 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 97.707 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 97.707 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393888391488 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1393888391488 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.227 " "Worst-case hold slack is 0.227" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393888391516 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393888391516 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.227 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.227 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393888391516 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.320 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 0.320 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393888391516 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1393888391516 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 2.272 " "Worst-case recovery slack is 2.272" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393888391531 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393888391531 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 2.272 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 2.272 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393888391531 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1393888391531 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "removal 2.259 " "Worst-case removal slack is 2.259" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393888391547 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393888391547 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 2.259 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 2.259 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393888391547 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1393888391547 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 4.716 " "Worst-case minimum pulse width slack is 4.716" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393888391556 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393888391556 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.716 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 4.716 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393888391556 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 9.818 0.000 CLOCK_50 " " 9.818 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393888391556 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 49.608 0.000 altera_reserved_tck " " 49.608 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393888391556 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 49.744 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 49.744 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393888391556 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1393888391556 ""} +{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 6 synchronizer chains. " "Report Metastability: Found 6 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n " "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393888391854 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 6 " "Number of Synchronizer Chains Found: 6" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393888391854 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393888391854 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 0.333 " "Fraction of Chains for which MTBFs Could Not be Calculated: 0.333" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393888391854 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 17.489 ns " "Worst Case Available Settling Time: 17.489 ns" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393888391854 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393888391854 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. " "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions." { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393888391854 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8 " " - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393888391854 ""} } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393888391854 ""} +{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "" 0 0 1393888391865 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "" 0 -1 1393888392270 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup 3.368 " "Worst-case setup slack is 3.368" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393888392299 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393888392299 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 3.368 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 3.368 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393888392299 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 98.512 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 98.512 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393888392299 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1393888392299 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.102 " "Worst-case hold slack is 0.102" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393888392327 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393888392327 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.102 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.102 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393888392327 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.193 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 0.193 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393888392327 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1393888392327 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 3.214 " "Worst-case recovery slack is 3.214" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393888392343 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393888392343 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 3.214 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 3.214 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393888392343 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1393888392343 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "removal 1.443 " "Worst-case removal slack is 1.443" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393888392361 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393888392361 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.443 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 1.443 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393888392361 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1393888392361 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 4.749 " "Worst-case minimum pulse width slack is 4.749" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393888392373 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393888392373 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.749 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 4.749 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393888392373 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 9.587 0.000 CLOCK_50 " " 9.587 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393888392373 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 49.484 0.000 altera_reserved_tck " " 49.484 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393888392373 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 49.782 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 49.782 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393888392373 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1393888392373 ""} +{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 6 synchronizer chains. " "Report Metastability: Found 6 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n " "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393888392720 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 6 " "Number of Synchronizer Chains Found: 6" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393888392720 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393888392720 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 0.333 " "Fraction of Chains for which MTBFs Could Not be Calculated: 0.333" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393888392720 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 18.472 ns " "Worst Case Available Settling Time: 18.472 ns" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393888392720 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393888392720 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. " "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions." { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393888392720 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8 " " - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393888392720 ""} } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393888392720 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "" 0 -1 1393888393319 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "" 0 -1 1393888393319 ""} +{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 1 Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "569 " "Peak virtual memory: 569 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1 1393888393715 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 03 16:13:13 2014 " "Processing ended: Mon Mar 03 16:13:13 2014" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1 1393888393715 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1 1393888393715 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:07 " "Total CPU time (on all processors): 00:00:07" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1 1393888393715 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1 1393888393715 ""} diff --git a/MCandWifiTestDE0/db/de0_nano_system.sta.rdb b/MCandWifiTestDE0/db/de0_nano_system.sta.rdb index 8d280ff5..71808f6c 100644 Binary files a/MCandWifiTestDE0/db/de0_nano_system.sta.rdb and b/MCandWifiTestDE0/db/de0_nano_system.sta.rdb differ diff --git a/MCandWifiTestDE0/db/de0_nano_system.sta_cmp.6_slow_1200mv_85c.tdb b/MCandWifiTestDE0/db/de0_nano_system.sta_cmp.6_slow_1200mv_85c.tdb index 69b8294f..ad24d89e 100644 Binary files a/MCandWifiTestDE0/db/de0_nano_system.sta_cmp.6_slow_1200mv_85c.tdb and b/MCandWifiTestDE0/db/de0_nano_system.sta_cmp.6_slow_1200mv_85c.tdb differ diff --git a/MCandWifiTestDE0/db/de0_nano_system.tiscmp.fast_1200mv_0c.ddb b/MCandWifiTestDE0/db/de0_nano_system.tiscmp.fast_1200mv_0c.ddb index b98f165f..2db3ee15 100644 Binary files a/MCandWifiTestDE0/db/de0_nano_system.tiscmp.fast_1200mv_0c.ddb and b/MCandWifiTestDE0/db/de0_nano_system.tiscmp.fast_1200mv_0c.ddb differ diff --git a/MCandWifiTestDE0/db/de0_nano_system.tiscmp.slow_1200mv_0c.ddb b/MCandWifiTestDE0/db/de0_nano_system.tiscmp.slow_1200mv_0c.ddb index 8f1136c8..798188c0 100644 Binary files a/MCandWifiTestDE0/db/de0_nano_system.tiscmp.slow_1200mv_0c.ddb and b/MCandWifiTestDE0/db/de0_nano_system.tiscmp.slow_1200mv_0c.ddb differ diff --git a/MCandWifiTestDE0/db/de0_nano_system.tiscmp.slow_1200mv_85c.ddb b/MCandWifiTestDE0/db/de0_nano_system.tiscmp.slow_1200mv_85c.ddb index 21a9e5af..5853d833 100644 Binary files a/MCandWifiTestDE0/db/de0_nano_system.tiscmp.slow_1200mv_85c.ddb and b/MCandWifiTestDE0/db/de0_nano_system.tiscmp.slow_1200mv_85c.ddb differ diff --git a/MCandWifiTestDE0/db/de0_nano_system.tmw_info b/MCandWifiTestDE0/db/de0_nano_system.tmw_info deleted file mode 100644 index a649a0eb..00000000 --- a/MCandWifiTestDE0/db/de0_nano_system.tmw_info +++ /dev/null @@ -1,6 +0,0 @@ -start_full_compilation:s:00:01:14 -start_analysis_synthesis:s:00:00:24-start_full_compilation -start_analysis_elaboration:s-start_full_compilation -start_fitter:s:00:00:39-start_full_compilation -start_assembler:s:00:00:04-start_full_compilation -start_timing_analyzer:s:00:00:07-start_full_compilation diff --git a/MCandWifiTestDE0/db/de0_nano_system.vpr.ammdb b/MCandWifiTestDE0/db/de0_nano_system.vpr.ammdb index 94e198c7..d77b80be 100644 Binary files a/MCandWifiTestDE0/db/de0_nano_system.vpr.ammdb and b/MCandWifiTestDE0/db/de0_nano_system.vpr.ammdb differ diff --git a/MCandWifiTestDE0/db/logic_util_heursitic.dat b/MCandWifiTestDE0/db/logic_util_heursitic.dat index cbb6b503..823ec5a8 100644 Binary files a/MCandWifiTestDE0/db/logic_util_heursitic.dat and b/MCandWifiTestDE0/db/logic_util_heursitic.dat differ diff --git a/MCandWifiTestDE0/db/prev_cmp_de0_nano_system.qmsg b/MCandWifiTestDE0/db/prev_cmp_de0_nano_system.qmsg index 1c85e2bb..db83484d 100644 --- a/MCandWifiTestDE0/db/prev_cmp_de0_nano_system.qmsg +++ b/MCandWifiTestDE0/db/prev_cmp_de0_nano_system.qmsg @@ -1,431 +1,431 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1 1393808668178 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Full Version " "Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1 1393808668178 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Mar 02 18:04:27 2014 " "Processing started: Sun Mar 02 18:04:27 2014" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1 1393808668178 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1 1393808668178 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off de0_nano_system -c de0_nano_system " "Command: quartus_map --read_settings_files=on --write_settings_files=off de0_nano_system -c de0_nano_system" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1 1393808668178 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." { } { } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "" 0 -1 1393808668538 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "de0_nano_system.vhd 2 1 " "Found 2 design units, including 1 entities, in source file de0_nano_system.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 de0_nano_system-syn " "Found design unit 1: de0_nano_system-syn" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 86 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1 1393808668988 ""} { "Info" "ISGN_ENTITY_NAME" "1 de0_nano_system " "Found entity 1: de0_nano_system" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 55 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808668988 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393808668988 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "heartbeat.vhd 2 1 " "Found 2 design units, including 1 entities, in source file heartbeat.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 heartbeat-syn " "Found design unit 1: heartbeat-syn" { } { { "heartbeat.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/heartbeat.vhd" 61 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1 1393808668988 ""} { "Info" "ISGN_ENTITY_NAME" "1 heartbeat " "Found entity 1: heartbeat" { } { { "heartbeat.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/heartbeat.vhd" 49 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808668988 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393808668988 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/system.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/system.v" { { "Info" "ISGN_ENTITY_NAME" "1 system " "Found entity 1: system" { } { { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 6 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808669008 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393808669008 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_irq_mapper.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_irq_mapper.sv" { { "Info" "ISGN_ENTITY_NAME" "1 system_irq_mapper " "Found entity 1: system_irq_mapper" { } { { "system/synthesis/submodules/system_irq_mapper.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_irq_mapper.sv" 31 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808669008 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393808669008 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_merlin_width_adapter.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_width_adapter.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_width_adapter " "Found entity 1: altera_merlin_width_adapter" { } { { "system/synthesis/submodules/altera_merlin_width_adapter.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_width_adapter.sv" 25 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808669018 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393808669018 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_merlin_burst_uncompressor.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_burst_uncompressor.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_burst_uncompressor " "Found entity 1: altera_merlin_burst_uncompressor" { } { { "system/synthesis/submodules/altera_merlin_burst_uncompressor.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_burst_uncompressor.sv" 40 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808669018 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393808669018 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_merlin_address_alignment.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_address_alignment.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_address_alignment " "Found entity 1: altera_merlin_address_alignment" { } { { "system/synthesis/submodules/altera_merlin_address_alignment.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_address_alignment.sv" 26 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808669018 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393808669018 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_merlin_arbitrator.sv 2 2 " "Found 2 design units, including 2 entities, in source file system/synthesis/submodules/altera_merlin_arbitrator.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_arbitrator " "Found entity 1: altera_merlin_arbitrator" { } { { "system/synthesis/submodules/altera_merlin_arbitrator.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_arbitrator.sv" 103 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808669018 ""} { "Info" "ISGN_ENTITY_NAME" "2 altera_merlin_arb_adder " "Found entity 2: altera_merlin_arb_adder" { } { { "system/synthesis/submodules/altera_merlin_arbitrator.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_arbitrator.sv" 228 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808669018 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393808669018 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_rsp_xbar_mux_001.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_rsp_xbar_mux_001.sv" { { "Info" "ISGN_ENTITY_NAME" "1 system_rsp_xbar_mux_001 " "Found entity 1: system_rsp_xbar_mux_001" { } { { "system/synthesis/submodules/system_rsp_xbar_mux_001.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_rsp_xbar_mux_001.sv" 38 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808669028 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393808669028 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_rsp_xbar_mux.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_rsp_xbar_mux.sv" { { "Info" "ISGN_ENTITY_NAME" "1 system_rsp_xbar_mux " "Found entity 1: system_rsp_xbar_mux" { } { { "system/synthesis/submodules/system_rsp_xbar_mux.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_rsp_xbar_mux.sv" 38 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808669028 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393808669028 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_rsp_xbar_demux_002.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_rsp_xbar_demux_002.sv" { { "Info" "ISGN_ENTITY_NAME" "1 system_rsp_xbar_demux_002 " "Found entity 1: system_rsp_xbar_demux_002" { } { { "system/synthesis/submodules/system_rsp_xbar_demux_002.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_rsp_xbar_demux_002.sv" 43 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808669028 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393808669028 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_rsp_xbar_demux.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_rsp_xbar_demux.sv" { { "Info" "ISGN_ENTITY_NAME" "1 system_rsp_xbar_demux " "Found entity 1: system_rsp_xbar_demux" { } { { "system/synthesis/submodules/system_rsp_xbar_demux.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_rsp_xbar_demux.sv" 43 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808669028 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393808669028 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_cmd_xbar_mux.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_cmd_xbar_mux.sv" { { "Info" "ISGN_ENTITY_NAME" "1 system_cmd_xbar_mux " "Found entity 1: system_cmd_xbar_mux" { } { { "system/synthesis/submodules/system_cmd_xbar_mux.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cmd_xbar_mux.sv" 38 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808669028 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393808669028 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_cmd_xbar_demux_001.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_cmd_xbar_demux_001.sv" { { "Info" "ISGN_ENTITY_NAME" "1 system_cmd_xbar_demux_001 " "Found entity 1: system_cmd_xbar_demux_001" { } { { "system/synthesis/submodules/system_cmd_xbar_demux_001.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cmd_xbar_demux_001.sv" 43 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808669038 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393808669038 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_cmd_xbar_demux.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_cmd_xbar_demux.sv" { { "Info" "ISGN_ENTITY_NAME" "1 system_cmd_xbar_demux " "Found entity 1: system_cmd_xbar_demux" { } { { "system/synthesis/submodules/system_cmd_xbar_demux.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cmd_xbar_demux.sv" 43 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808669038 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393808669038 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_reset_controller.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_reset_controller.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_reset_controller " "Found entity 1: altera_reset_controller" { } { { "system/synthesis/submodules/altera_reset_controller.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_reset_controller.v" 28 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808669038 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393808669038 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_reset_synchronizer.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_reset_synchronizer.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_reset_synchronizer " "Found entity 1: altera_reset_synchronizer" { } { { "system/synthesis/submodules/altera_reset_synchronizer.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_reset_synchronizer.v" 24 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808669038 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393808669038 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_merlin_burst_adapter.sv 7 7 " "Found 7 design units, including 7 entities, in source file system/synthesis/submodules/altera_merlin_burst_adapter.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_burst_adapter_burstwrap_increment " "Found entity 1: altera_merlin_burst_adapter_burstwrap_increment" { } { { "system/synthesis/submodules/altera_merlin_burst_adapter.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_burst_adapter.sv" 40 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808669048 ""} { "Info" "ISGN_ENTITY_NAME" "2 altera_merlin_burst_adapter_adder " "Found entity 2: altera_merlin_burst_adapter_adder" { } { { "system/synthesis/submodules/altera_merlin_burst_adapter.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_burst_adapter.sv" 55 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808669048 ""} { "Info" "ISGN_ENTITY_NAME" "3 altera_merlin_burst_adapter_subtractor " "Found entity 3: altera_merlin_burst_adapter_subtractor" { } { { "system/synthesis/submodules/altera_merlin_burst_adapter.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_burst_adapter.sv" 77 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808669048 ""} { "Info" "ISGN_ENTITY_NAME" "4 altera_merlin_burst_adapter_min " "Found entity 4: altera_merlin_burst_adapter_min" { } { { "system/synthesis/submodules/altera_merlin_burst_adapter.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_burst_adapter.sv" 98 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808669048 ""} { "Info" "ISGN_ENTITY_NAME" "5 altera_merlin_burst_adapter " "Found entity 5: altera_merlin_burst_adapter" { } { { "system/synthesis/submodules/altera_merlin_burst_adapter.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_burst_adapter.sv" 264 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808669048 ""} { "Info" "ISGN_ENTITY_NAME" "6 altera_merlin_burst_adapter_uncompressed_only " "Found entity 6: altera_merlin_burst_adapter_uncompressed_only" { } { { "system/synthesis/submodules/altera_merlin_burst_adapter.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_burst_adapter.sv" 414 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808669048 ""} { "Info" "ISGN_ENTITY_NAME" "7 altera_merlin_burst_adapter_full " "Found entity 7: altera_merlin_burst_adapter_full" { } { { "system/synthesis/submodules/altera_merlin_burst_adapter.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_burst_adapter.sv" 468 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808669048 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393808669048 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_merlin_traffic_limiter.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_traffic_limiter.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_traffic_limiter " "Found entity 1: altera_merlin_traffic_limiter" { } { { "system/synthesis/submodules/altera_merlin_traffic_limiter.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_traffic_limiter.sv" 44 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808669048 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393808669048 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_avalon_st_pipeline_base.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_avalon_st_pipeline_base.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_avalon_st_pipeline_base " "Found entity 1: altera_avalon_st_pipeline_base" { } { { "system/synthesis/submodules/altera_avalon_st_pipeline_base.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_avalon_st_pipeline_base.v" 22 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808669048 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393808669048 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_id_router_002.sv 2 2 " "Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_id_router_002.sv" { { "Info" "ISGN_ENTITY_NAME" "1 system_id_router_002_default_decode " "Found entity 1: system_id_router_002_default_decode" { } { { "system/synthesis/submodules/system_id_router_002.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_id_router_002.sv" 32 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808669058 ""} { "Info" "ISGN_ENTITY_NAME" "2 system_id_router_002 " "Found entity 2: system_id_router_002" { } { { "system/synthesis/submodules/system_id_router_002.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_id_router_002.sv" 54 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808669058 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393808669058 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_id_router_001.sv 2 2 " "Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_id_router_001.sv" { { "Info" "ISGN_ENTITY_NAME" "1 system_id_router_001_default_decode " "Found entity 1: system_id_router_001_default_decode" { } { { "system/synthesis/submodules/system_id_router_001.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_id_router_001.sv" 32 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808669058 ""} { "Info" "ISGN_ENTITY_NAME" "2 system_id_router_001 " "Found entity 2: system_id_router_001" { } { { "system/synthesis/submodules/system_id_router_001.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_id_router_001.sv" 54 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808669058 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393808669058 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_id_router.sv 2 2 " "Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_id_router.sv" { { "Info" "ISGN_ENTITY_NAME" "1 system_id_router_default_decode " "Found entity 1: system_id_router_default_decode" { } { { "system/synthesis/submodules/system_id_router.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_id_router.sv" 32 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808669058 ""} { "Info" "ISGN_ENTITY_NAME" "2 system_id_router " "Found entity 2: system_id_router" { } { { "system/synthesis/submodules/system_id_router.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_id_router.sv" 54 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808669058 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393808669058 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_addr_router_001.sv 2 2 " "Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_addr_router_001.sv" { { "Info" "ISGN_ENTITY_NAME" "1 system_addr_router_001_default_decode " "Found entity 1: system_addr_router_001_default_decode" { } { { "system/synthesis/submodules/system_addr_router_001.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_addr_router_001.sv" 32 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808669058 ""} { "Info" "ISGN_ENTITY_NAME" "2 system_addr_router_001 " "Found entity 2: system_addr_router_001" { } { { "system/synthesis/submodules/system_addr_router_001.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_addr_router_001.sv" 54 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808669058 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393808669058 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_addr_router.sv 2 2 " "Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_addr_router.sv" { { "Info" "ISGN_ENTITY_NAME" "1 system_addr_router_default_decode " "Found entity 1: system_addr_router_default_decode" { } { { "system/synthesis/submodules/system_addr_router.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_addr_router.sv" 32 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808669068 ""} { "Info" "ISGN_ENTITY_NAME" "2 system_addr_router " "Found entity 2: system_addr_router" { } { { "system/synthesis/submodules/system_addr_router.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_addr_router.sv" 54 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808669068 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393808669068 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_avalon_sc_fifo.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_avalon_sc_fifo.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_avalon_sc_fifo " "Found entity 1: altera_avalon_sc_fifo" { } { { "system/synthesis/submodules/altera_avalon_sc_fifo.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_avalon_sc_fifo.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808669068 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393808669068 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_merlin_slave_agent.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_slave_agent.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_slave_agent " "Found entity 1: altera_merlin_slave_agent" { } { { "system/synthesis/submodules/altera_merlin_slave_agent.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_slave_agent.sv" 34 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808669068 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393808669068 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_merlin_master_agent.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_master_agent.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_master_agent " "Found entity 1: altera_merlin_master_agent" { } { { "system/synthesis/submodules/altera_merlin_master_agent.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_master_agent.sv" 28 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808669068 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393808669068 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_merlin_slave_translator.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_slave_translator.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_slave_translator " "Found entity 1: altera_merlin_slave_translator" { } { { "system/synthesis/submodules/altera_merlin_slave_translator.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_slave_translator.sv" 35 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808669078 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393808669078 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_merlin_master_translator.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_master_translator.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_master_translator " "Found entity 1: altera_merlin_master_translator" { } { { "system/synthesis/submodules/altera_merlin_master_translator.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_master_translator.sv" 30 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808669078 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393808669078 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_up_rs232_counters.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_up_rs232_counters.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_up_rs232_counters " "Found entity 1: altera_up_rs232_counters" { } { { "system/synthesis/submodules/altera_up_rs232_counters.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_up_rs232_counters.v" 48 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808669078 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393808669078 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_up_rs232_in_deserializer.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_up_rs232_in_deserializer.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_up_rs232_in_deserializer " "Found entity 1: altera_up_rs232_in_deserializer" { } { { "system/synthesis/submodules/altera_up_rs232_in_deserializer.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_up_rs232_in_deserializer.v" 47 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808669078 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393808669078 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_up_rs232_out_serializer.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_up_rs232_out_serializer.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_up_rs232_out_serializer " "Found entity 1: altera_up_rs232_out_serializer" { } { { "system/synthesis/submodules/altera_up_rs232_out_serializer.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_up_rs232_out_serializer.v" 47 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808669088 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393808669088 ""} -{ "Warning" "WVRFX_L2_VERI_INGORE_DANGLING_COMMA" "altera_up_sync_fifo.v(157) " "Verilog HDL Module Instantiation warning at altera_up_sync_fifo.v(157): ignored dangling comma in List of Port Connections" { } { { "system/synthesis/submodules/altera_up_sync_fifo.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_up_sync_fifo.v" 157 0 0 } } } 0 10275 "Verilog HDL Module Instantiation warning at %1!s!: ignored dangling comma in List of Port Connections" 0 0 "" 0 -1 1393808669088 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_up_sync_fifo.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_up_sync_fifo.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_up_sync_fifo " "Found entity 1: altera_up_sync_fifo" { } { { "system/synthesis/submodules/altera_up_sync_fifo.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_up_sync_fifo.v" 47 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808669088 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393808669088 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_rs232_wifi.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_rs232_wifi.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_rs232_wifi " "Found entity 1: system_rs232_wifi" { } { { "system/synthesis/submodules/system_rs232_wifi.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_rs232_wifi.v" 48 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808669088 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393808669088 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_uart_mc.v 7 7 " "Found 7 design units, including 7 entities, in source file system/synthesis/submodules/system_uart_mc.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_uart_mc_log_module " "Found entity 1: system_uart_mc_log_module" { } { { "system/synthesis/submodules/system_uart_mc.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_mc.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808669098 ""} { "Info" "ISGN_ENTITY_NAME" "2 system_uart_mc_tx " "Found entity 2: system_uart_mc_tx" { } { { "system/synthesis/submodules/system_uart_mc.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_mc.v" 66 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808669098 ""} { "Info" "ISGN_ENTITY_NAME" "3 system_uart_mc_rx_stimulus_source_character_source_rom_module " "Found entity 3: system_uart_mc_rx_stimulus_source_character_source_rom_module" { } { { "system/synthesis/submodules/system_uart_mc.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_mc.v" 238 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808669098 ""} { "Info" "ISGN_ENTITY_NAME" "4 system_uart_mc_rx_stimulus_source " "Found entity 4: system_uart_mc_rx_stimulus_source" { } { { "system/synthesis/submodules/system_uart_mc.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_mc.v" 387 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808669098 ""} { "Info" "ISGN_ENTITY_NAME" "5 system_uart_mc_rx " "Found entity 5: system_uart_mc_rx" { } { { "system/synthesis/submodules/system_uart_mc.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_mc.v" 492 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808669098 ""} { "Info" "ISGN_ENTITY_NAME" "6 system_uart_mc_regs " "Found entity 6: system_uart_mc_regs" { } { { "system/synthesis/submodules/system_uart_mc.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_mc.v" 750 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808669098 ""} { "Info" "ISGN_ENTITY_NAME" "7 system_uart_mc " "Found entity 7: system_uart_mc" { } { { "system/synthesis/submodules/system_uart_mc.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_mc.v" 995 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808669098 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393808669098 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_pio_ir_emitter.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_pio_ir_emitter.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_pio_ir_emitter " "Found entity 1: system_pio_ir_emitter" { } { { "system/synthesis/submodules/system_pio_ir_emitter.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_pio_ir_emitter.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808669098 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393808669098 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_jtag_uart_0.v 7 7 " "Found 7 design units, including 7 entities, in source file system/synthesis/submodules/system_jtag_uart_0.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_jtag_uart_0_log_module " "Found entity 1: system_jtag_uart_0_log_module" { } { { "system/synthesis/submodules/system_jtag_uart_0.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_jtag_uart_0.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808669108 ""} { "Info" "ISGN_ENTITY_NAME" "2 system_jtag_uart_0_sim_scfifo_w " "Found entity 2: system_jtag_uart_0_sim_scfifo_w" { } { { "system/synthesis/submodules/system_jtag_uart_0.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_jtag_uart_0.v" 65 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808669108 ""} { "Info" "ISGN_ENTITY_NAME" "3 system_jtag_uart_0_scfifo_w " "Found entity 3: system_jtag_uart_0_scfifo_w" { } { { "system/synthesis/submodules/system_jtag_uart_0.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_jtag_uart_0.v" 123 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808669108 ""} { "Info" "ISGN_ENTITY_NAME" "4 system_jtag_uart_0_drom_module " "Found entity 4: system_jtag_uart_0_drom_module" { } { { "system/synthesis/submodules/system_jtag_uart_0.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_jtag_uart_0.v" 208 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808669108 ""} { "Info" "ISGN_ENTITY_NAME" "5 system_jtag_uart_0_sim_scfifo_r " "Found entity 5: system_jtag_uart_0_sim_scfifo_r" { } { { "system/synthesis/submodules/system_jtag_uart_0.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_jtag_uart_0.v" 362 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808669108 ""} { "Info" "ISGN_ENTITY_NAME" "6 system_jtag_uart_0_scfifo_r " "Found entity 6: system_jtag_uart_0_scfifo_r" { } { { "system/synthesis/submodules/system_jtag_uart_0.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_jtag_uart_0.v" 450 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808669108 ""} { "Info" "ISGN_ENTITY_NAME" "7 system_jtag_uart_0 " "Found entity 7: system_jtag_uart_0" { } { { "system/synthesis/submodules/system_jtag_uart_0.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_jtag_uart_0.v" 537 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808669108 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393808669108 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_pio_sw.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_pio_sw.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_pio_sw " "Found entity 1: system_pio_sw" { } { { "system/synthesis/submodules/system_pio_sw.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_pio_sw.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808669108 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393808669108 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_pio_key_left.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_pio_key_left.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_pio_key_left " "Found entity 1: system_pio_key_left" { } { { "system/synthesis/submodules/system_pio_key_left.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_pio_key_left.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808669108 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393808669108 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_pio_led.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_pio_led.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_pio_led " "Found entity 1: system_pio_led" { } { { "system/synthesis/submodules/system_pio_led.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_pio_led.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808669108 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393808669108 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_uart_wifi.v 7 7 " "Found 7 design units, including 7 entities, in source file system/synthesis/submodules/system_uart_wifi.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_uart_wifi_log_module " "Found entity 1: system_uart_wifi_log_module" { } { { "system/synthesis/submodules/system_uart_wifi.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_wifi.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808669118 ""} { "Info" "ISGN_ENTITY_NAME" "2 system_uart_wifi_tx " "Found entity 2: system_uart_wifi_tx" { } { { "system/synthesis/submodules/system_uart_wifi.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_wifi.v" 66 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808669118 ""} { "Info" "ISGN_ENTITY_NAME" "3 system_uart_wifi_rx_stimulus_source_character_source_rom_module " "Found entity 3: system_uart_wifi_rx_stimulus_source_character_source_rom_module" { } { { "system/synthesis/submodules/system_uart_wifi.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_wifi.v" 238 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808669118 ""} { "Info" "ISGN_ENTITY_NAME" "4 system_uart_wifi_rx_stimulus_source " "Found entity 4: system_uart_wifi_rx_stimulus_source" { } { { "system/synthesis/submodules/system_uart_wifi.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_wifi.v" 387 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808669118 ""} { "Info" "ISGN_ENTITY_NAME" "5 system_uart_wifi_rx " "Found entity 5: system_uart_wifi_rx" { } { { "system/synthesis/submodules/system_uart_wifi.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_wifi.v" 492 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808669118 ""} { "Info" "ISGN_ENTITY_NAME" "6 system_uart_wifi_regs " "Found entity 6: system_uart_wifi_regs" { } { { "system/synthesis/submodules/system_uart_wifi.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_wifi.v" 750 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808669118 ""} { "Info" "ISGN_ENTITY_NAME" "7 system_uart_wifi " "Found entity 7: system_uart_wifi" { } { { "system/synthesis/submodules/system_uart_wifi.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_wifi.v" 1006 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808669118 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393808669118 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_sys_clk_timer.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_sys_clk_timer.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_sys_clk_timer " "Found entity 1: system_sys_clk_timer" { } { { "system/synthesis/submodules/system_sys_clk_timer.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_sys_clk_timer.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808669118 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393808669118 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_sdram.v 2 2 " "Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_sdram.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_sdram_input_efifo_module " "Found entity 1: system_sdram_input_efifo_module" { } { { "system/synthesis/submodules/system_sdram.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_sdram.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808669118 ""} { "Info" "ISGN_ENTITY_NAME" "2 system_sdram " "Found entity 2: system_sdram" { } { { "system/synthesis/submodules/system_sdram.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_sdram.v" 158 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808669118 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393808669118 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_sysid.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_sysid.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_sysid " "Found entity 1: system_sysid" { } { { "system/synthesis/submodules/system_sysid.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_sysid.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808669128 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393808669128 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_cpu.v 28 28 " "Found 28 design units, including 28 entities, in source file system/synthesis/submodules/system_cpu.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_cpu_ic_data_module " "Found entity 1: system_cpu_ic_data_module" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808670528 ""} { "Info" "ISGN_ENTITY_NAME" "2 system_cpu_ic_tag_module " "Found entity 2: system_cpu_ic_tag_module" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 86 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808670528 ""} { "Info" "ISGN_ENTITY_NAME" "3 system_cpu_bht_module " "Found entity 3: system_cpu_bht_module" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 152 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808670528 ""} { "Info" "ISGN_ENTITY_NAME" "4 system_cpu_register_bank_a_module " "Found entity 4: system_cpu_register_bank_a_module" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 218 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808670528 ""} { "Info" "ISGN_ENTITY_NAME" "5 system_cpu_register_bank_b_module " "Found entity 5: system_cpu_register_bank_b_module" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 281 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808670528 ""} { "Info" "ISGN_ENTITY_NAME" "6 system_cpu_dc_tag_module " "Found entity 6: system_cpu_dc_tag_module" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 344 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808670528 ""} { "Info" "ISGN_ENTITY_NAME" "7 system_cpu_dc_data_module " "Found entity 7: system_cpu_dc_data_module" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 407 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808670528 ""} { "Info" "ISGN_ENTITY_NAME" "8 system_cpu_dc_victim_module " "Found entity 8: system_cpu_dc_victim_module" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 473 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808670528 ""} { "Info" "ISGN_ENTITY_NAME" "9 system_cpu_nios2_oci_debug " "Found entity 9: system_cpu_nios2_oci_debug" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 538 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808670528 ""} { "Info" "ISGN_ENTITY_NAME" "10 system_cpu_ociram_lpm_dram_bdp_component_module " "Found entity 10: system_cpu_ociram_lpm_dram_bdp_component_module" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 666 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808670528 ""} { "Info" "ISGN_ENTITY_NAME" "11 system_cpu_nios2_ocimem " "Found entity 11: system_cpu_nios2_ocimem" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 759 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808670528 ""} { "Info" "ISGN_ENTITY_NAME" "12 system_cpu_nios2_avalon_reg " "Found entity 12: system_cpu_nios2_avalon_reg" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 905 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808670528 ""} { "Info" "ISGN_ENTITY_NAME" "13 system_cpu_nios2_oci_break " "Found entity 13: system_cpu_nios2_oci_break" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 999 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808670528 ""} { "Info" "ISGN_ENTITY_NAME" "14 system_cpu_nios2_oci_xbrk " "Found entity 14: system_cpu_nios2_oci_xbrk" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 1293 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808670528 ""} { "Info" "ISGN_ENTITY_NAME" "15 system_cpu_nios2_oci_dbrk " "Found entity 15: system_cpu_nios2_oci_dbrk" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 1553 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808670528 ""} { "Info" "ISGN_ENTITY_NAME" "16 system_cpu_nios2_oci_itrace " "Found entity 16: system_cpu_nios2_oci_itrace" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 1741 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808670528 ""} { "Info" "ISGN_ENTITY_NAME" "17 system_cpu_nios2_oci_td_mode " "Found entity 17: system_cpu_nios2_oci_td_mode" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 2098 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808670528 ""} { "Info" "ISGN_ENTITY_NAME" "18 system_cpu_nios2_oci_dtrace " "Found entity 18: system_cpu_nios2_oci_dtrace" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 2165 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808670528 ""} { "Info" "ISGN_ENTITY_NAME" "19 system_cpu_nios2_oci_compute_tm_count " "Found entity 19: system_cpu_nios2_oci_compute_tm_count" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 2259 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808670528 ""} { "Info" "ISGN_ENTITY_NAME" "20 system_cpu_nios2_oci_fifowp_inc " "Found entity 20: system_cpu_nios2_oci_fifowp_inc" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 2330 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808670528 ""} { "Info" "ISGN_ENTITY_NAME" "21 system_cpu_nios2_oci_fifocount_inc " "Found entity 21: system_cpu_nios2_oci_fifocount_inc" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 2372 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808670528 ""} { "Info" "ISGN_ENTITY_NAME" "22 system_cpu_nios2_oci_fifo " "Found entity 22: system_cpu_nios2_oci_fifo" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 2418 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808670528 ""} { "Info" "ISGN_ENTITY_NAME" "23 system_cpu_nios2_oci_pib " "Found entity 23: system_cpu_nios2_oci_pib" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 2923 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808670528 ""} { "Info" "ISGN_ENTITY_NAME" "24 system_cpu_traceram_lpm_dram_bdp_component_module " "Found entity 24: system_cpu_traceram_lpm_dram_bdp_component_module" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 2991 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808670528 ""} { "Info" "ISGN_ENTITY_NAME" "25 system_cpu_nios2_oci_im " "Found entity 25: system_cpu_nios2_oci_im" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3080 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808670528 ""} { "Info" "ISGN_ENTITY_NAME" "26 system_cpu_nios2_performance_monitors " "Found entity 26: system_cpu_nios2_performance_monitors" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3217 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808670528 ""} { "Info" "ISGN_ENTITY_NAME" "27 system_cpu_nios2_oci " "Found entity 27: system_cpu_nios2_oci" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3233 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808670528 ""} { "Info" "ISGN_ENTITY_NAME" "28 system_cpu " "Found entity 28: system_cpu" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3736 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808670528 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393808670528 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_cpu_jtag_debug_module_sysclk.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_cpu_jtag_debug_module_sysclk.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_cpu_jtag_debug_module_sysclk " "Found entity 1: system_cpu_jtag_debug_module_sysclk" { } { { "system/synthesis/submodules/system_cpu_jtag_debug_module_sysclk.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu_jtag_debug_module_sysclk.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808670538 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393808670538 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_cpu_jtag_debug_module_tck.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_cpu_jtag_debug_module_tck.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_cpu_jtag_debug_module_tck " "Found entity 1: system_cpu_jtag_debug_module_tck" { } { { "system/synthesis/submodules/system_cpu_jtag_debug_module_tck.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu_jtag_debug_module_tck.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808670538 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393808670538 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_cpu_jtag_debug_module_wrapper " "Found entity 1: system_cpu_jtag_debug_module_wrapper" { } { { "system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808670538 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393808670538 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_cpu_mult_cell.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_cpu_mult_cell.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_cpu_mult_cell " "Found entity 1: system_cpu_mult_cell" { } { { "system/synthesis/submodules/system_cpu_mult_cell.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu_mult_cell.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808670548 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393808670548 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_cpu_oci_test_bench.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_cpu_oci_test_bench.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_cpu_oci_test_bench " "Found entity 1: system_cpu_oci_test_bench" { } { { "system/synthesis/submodules/system_cpu_oci_test_bench.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu_oci_test_bench.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808670548 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393808670548 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_cpu_test_bench.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_cpu_test_bench.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_cpu_test_bench " "Found entity 1: system_cpu_test_bench" { } { { "system/synthesis/submodules/system_cpu_test_bench.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu_test_bench.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808670548 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393808670548 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pll_sys.vhd 2 1 " "Found 2 design units, including 1 entities, in source file pll_sys.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 pll_sys-SYN " "Found design unit 1: pll_sys-SYN" { } { { "pll_sys.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/pll_sys.vhd" 54 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1 1393808670558 ""} { "Info" "ISGN_ENTITY_NAME" "1 pll_sys " "Found entity 1: pll_sys" { } { { "pll_sys.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/pll_sys.vhd" 42 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808670558 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393808670558 ""} -{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "system_cpu.v(2066) " "Verilog HDL or VHDL warning at system_cpu.v(2066): conditional expression evaluates to a constant" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 2066 0 0 } } } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1 1393808670578 ""} -{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "system_cpu.v(2068) " "Verilog HDL or VHDL warning at system_cpu.v(2068): conditional expression evaluates to a constant" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 2068 0 0 } } } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1 1393808670578 ""} -{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "system_cpu.v(2224) " "Verilog HDL or VHDL warning at system_cpu.v(2224): conditional expression evaluates to a constant" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 2224 0 0 } } } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1 1393808670578 ""} -{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "system_cpu.v(3143) " "Verilog HDL or VHDL warning at system_cpu.v(3143): conditional expression evaluates to a constant" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3143 0 0 } } } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1 1393808670578 ""} -{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "system_sdram.v(316) " "Verilog HDL or VHDL warning at system_sdram.v(316): conditional expression evaluates to a constant" { } { { "system/synthesis/submodules/system_sdram.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_sdram.v" 316 0 0 } } } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1 1393808670588 ""} -{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "system_sdram.v(326) " "Verilog HDL or VHDL warning at system_sdram.v(326): conditional expression evaluates to a constant" { } { { "system/synthesis/submodules/system_sdram.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_sdram.v" 326 0 0 } } } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1 1393808670588 ""} -{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "system_sdram.v(336) " "Verilog HDL or VHDL warning at system_sdram.v(336): conditional expression evaluates to a constant" { } { { "system/synthesis/submodules/system_sdram.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_sdram.v" 336 0 0 } } } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1 1393808670588 ""} -{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "system_sdram.v(680) " "Verilog HDL or VHDL warning at system_sdram.v(680): conditional expression evaluates to a constant" { } { { "system/synthesis/submodules/system_sdram.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_sdram.v" 680 0 0 } } } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1 1393808670588 ""} -{ "Info" "ISGN_START_ELABORATION_TOP" "de0_nano_system " "Elaborating entity \"de0_nano_system\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1 1393808670748 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pll_sys pll_sys:inst_pll_sys " "Elaborating entity \"pll_sys\" for hierarchy \"pll_sys:inst_pll_sys\"" { } { { "de0_nano_system.vhd" "inst_pll_sys" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 152 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808670748 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll pll_sys:inst_pll_sys\|altpll:altpll_component " "Elaborating entity \"altpll\" for hierarchy \"pll_sys:inst_pll_sys\|altpll:altpll_component\"" { } { { "pll_sys.vhd" "altpll_component" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/pll_sys.vhd" 154 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808670798 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "pll_sys:inst_pll_sys\|altpll:altpll_component " "Elaborated megafunction instantiation \"pll_sys:inst_pll_sys\|altpll:altpll_component\"" { } { { "pll_sys.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/pll_sys.vhd" 154 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1393808670798 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "pll_sys:inst_pll_sys\|altpll:altpll_component " "Instantiated megafunction \"pll_sys:inst_pll_sys\|altpll:altpll_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "bandwidth_type AUTO " "Parameter \"bandwidth_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808670808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_divide_by 1 " "Parameter \"clk0_divide_by\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808670808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_duty_cycle 50 " "Parameter \"clk0_duty_cycle\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808670808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_multiply_by 2 " "Parameter \"clk0_multiply_by\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808670808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_phase_shift 0 " "Parameter \"clk0_phase_shift\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808670808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_divide_by 1 " "Parameter \"clk1_divide_by\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808670808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_duty_cycle 50 " "Parameter \"clk1_duty_cycle\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808670808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_multiply_by 2 " "Parameter \"clk1_multiply_by\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808670808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_phase_shift -1500 " "Parameter \"clk1_phase_shift\" = \"-1500\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808670808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_divide_by 5 " "Parameter \"clk2_divide_by\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808670808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_duty_cycle 50 " "Parameter \"clk2_duty_cycle\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808670808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_multiply_by 1 " "Parameter \"clk2_multiply_by\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808670808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_phase_shift 0 " "Parameter \"clk2_phase_shift\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808670808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "compensate_clock CLK0 " "Parameter \"compensate_clock\" = \"CLK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808670808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "inclk0_input_frequency 20000 " "Parameter \"inclk0_input_frequency\" = \"20000\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808670808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808670808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint CBX_MODULE_PREFIX=pll_sys " "Parameter \"lpm_hint\" = \"CBX_MODULE_PREFIX=pll_sys\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808670808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altpll " "Parameter \"lpm_type\" = \"altpll\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808670808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode NORMAL " "Parameter \"operation_mode\" = \"NORMAL\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808670808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_type AUTO " "Parameter \"pll_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808670808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_activeclock PORT_UNUSED " "Parameter \"port_activeclock\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808670808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_areset PORT_UNUSED " "Parameter \"port_areset\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808670808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad0 PORT_UNUSED " "Parameter \"port_clkbad0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808670808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad1 PORT_UNUSED " "Parameter \"port_clkbad1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808670808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkloss PORT_UNUSED " "Parameter \"port_clkloss\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808670808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkswitch PORT_UNUSED " "Parameter \"port_clkswitch\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808670808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_configupdate PORT_UNUSED " "Parameter \"port_configupdate\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808670808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_fbin PORT_UNUSED " "Parameter \"port_fbin\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808670808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk0 PORT_USED " "Parameter \"port_inclk0\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808670808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk1 PORT_UNUSED " "Parameter \"port_inclk1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808670808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_locked PORT_USED " "Parameter \"port_locked\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808670808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pfdena PORT_UNUSED " "Parameter \"port_pfdena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808670808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasecounterselect PORT_UNUSED " "Parameter \"port_phasecounterselect\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808670808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasedone PORT_UNUSED " "Parameter \"port_phasedone\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808670808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasestep PORT_UNUSED " "Parameter \"port_phasestep\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808670808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phaseupdown PORT_UNUSED " "Parameter \"port_phaseupdown\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808670808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pllena PORT_UNUSED " "Parameter \"port_pllena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808670808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanaclr PORT_UNUSED " "Parameter \"port_scanaclr\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808670808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclk PORT_UNUSED " "Parameter \"port_scanclk\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808670808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclkena PORT_UNUSED " "Parameter \"port_scanclkena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808670808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandata PORT_UNUSED " "Parameter \"port_scandata\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808670808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandataout PORT_UNUSED " "Parameter \"port_scandataout\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808670808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandone PORT_UNUSED " "Parameter \"port_scandone\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808670808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanread PORT_UNUSED " "Parameter \"port_scanread\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808670808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanwrite PORT_UNUSED " "Parameter \"port_scanwrite\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808670808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk0 PORT_USED " "Parameter \"port_clk0\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808670808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk1 PORT_USED " "Parameter \"port_clk1\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808670808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk2 PORT_USED " "Parameter \"port_clk2\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808670808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk3 PORT_UNUSED " "Parameter \"port_clk3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808670808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk4 PORT_UNUSED " "Parameter \"port_clk4\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808670808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk5 PORT_UNUSED " "Parameter \"port_clk5\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808670808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena0 PORT_UNUSED " "Parameter \"port_clkena0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808670808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena1 PORT_UNUSED " "Parameter \"port_clkena1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808670808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena2 PORT_UNUSED " "Parameter \"port_clkena2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808670808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena3 PORT_UNUSED " "Parameter \"port_clkena3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808670808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena4 PORT_UNUSED " "Parameter \"port_clkena4\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808670808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena5 PORT_UNUSED " "Parameter \"port_clkena5\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808670808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk0 PORT_UNUSED " "Parameter \"port_extclk0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808670808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk1 PORT_UNUSED " "Parameter \"port_extclk1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808670808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk2 PORT_UNUSED " "Parameter \"port_extclk2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808670808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk3 PORT_UNUSED " "Parameter \"port_extclk3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808670808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "self_reset_on_loss_lock ON " "Parameter \"self_reset_on_loss_lock\" = \"ON\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808670808 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_clock 5 " "Parameter \"width_clock\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808670808 ""} } { { "pll_sys.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/pll_sys.vhd" 154 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1393808670808 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/pll_sys_altpll.v 1 1 " "Found 1 design units, including 1 entities, in source file db/pll_sys_altpll.v" { { "Info" "ISGN_ENTITY_NAME" "1 pll_sys_altpll " "Found entity 1: pll_sys_altpll" { } { { "db/pll_sys_altpll.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/pll_sys_altpll.v" 29 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808670868 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393808670868 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pll_sys_altpll pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated " "Elaborating entity \"pll_sys_altpll\" for hierarchy \"pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\"" { } { { "altpll.tdf" "auto_generated" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altpll.tdf" 897 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808670868 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "heartbeat heartbeat:inst_heartbeat " "Elaborating entity \"heartbeat\" for hierarchy \"heartbeat:inst_heartbeat\"" { } { { "de0_nano_system.vhd" "inst_heartbeat" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 161 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808670878 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system system:inst_cpu " "Elaborating entity \"system\" for hierarchy \"system:inst_cpu\"" { } { { "de0_nano_system.vhd" "inst_cpu" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808670878 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu system:inst_cpu\|system_cpu:cpu " "Elaborating entity \"system_cpu\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\"" { } { { "system/synthesis/system.v" "cpu" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808670928 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_test_bench system:inst_cpu\|system_cpu:cpu\|system_cpu_test_bench:the_system_cpu_test_bench " "Elaborating entity \"system_cpu_test_bench\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_test_bench:the_system_cpu_test_bench\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_test_bench" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 6073 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808670958 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_ic_data_module system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_data_module:system_cpu_ic_data " "Elaborating entity \"system_cpu_ic_data_module\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_data_module:system_cpu_ic_data\"" { } { { "system/synthesis/submodules/system_cpu.v" "system_cpu_ic_data" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 7098 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808670968 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_data_module:system_cpu_ic_data\|altsyncram:the_altsyncram " "Elaborating entity \"altsyncram\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_data_module:system_cpu_ic_data\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_altsyncram" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 58 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808670998 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_data_module:system_cpu_ic_data\|altsyncram:the_altsyncram " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_data_module:system_cpu_ic_data\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 58 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1393808670998 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_data_module:system_cpu_ic_data\|altsyncram:the_altsyncram " "Instantiated megafunction \"system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_data_module:system_cpu_ic_data\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808670998 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 0 " "Parameter \"maximum_depth\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808670998 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 2048 " "Parameter \"numwords_a\" = \"2048\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808670998 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 2048 " "Parameter \"numwords_b\" = \"2048\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808670998 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Parameter \"operation_mode\" = \"DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808670998 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808670998 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808670998 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rdcontrol_reg_b CLOCK0 " "Parameter \"rdcontrol_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808670998 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808670998 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 32 " "Parameter \"width_a\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808670998 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 32 " "Parameter \"width_b\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808670998 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 11 " "Parameter \"widthad_a\" = \"11\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808670998 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 11 " "Parameter \"widthad_b\" = \"11\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808670998 ""} } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 58 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1393808670998 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_sjd1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_sjd1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_sjd1 " "Found entity 1: altsyncram_sjd1" { } { { "db/altsyncram_sjd1.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_sjd1.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808671078 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393808671078 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_sjd1 system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_data_module:system_cpu_ic_data\|altsyncram:the_altsyncram\|altsyncram_sjd1:auto_generated " "Elaborating entity \"altsyncram_sjd1\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_data_module:system_cpu_ic_data\|altsyncram:the_altsyncram\|altsyncram_sjd1:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808671078 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_ic_tag_module system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_tag_module:system_cpu_ic_tag " "Elaborating entity \"system_cpu_ic_tag_module\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_tag_module:system_cpu_ic_tag\"" { } { { "system/synthesis/submodules/system_cpu.v" "system_cpu_ic_tag" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 7164 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808671078 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_tag_module:system_cpu_ic_tag\|altsyncram:the_altsyncram " "Elaborating entity \"altsyncram\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_tag_module:system_cpu_ic_tag\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_altsyncram" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 123 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808671098 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_tag_module:system_cpu_ic_tag\|altsyncram:the_altsyncram " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_tag_module:system_cpu_ic_tag\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 123 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1393808671098 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_tag_module:system_cpu_ic_tag\|altsyncram:the_altsyncram " "Instantiated megafunction \"system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_tag_module:system_cpu_ic_tag\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671098 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file system_cpu_ic_tag_ram.mif " "Parameter \"init_file\" = \"system_cpu_ic_tag_ram.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671098 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 0 " "Parameter \"maximum_depth\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671098 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 256 " "Parameter \"numwords_a\" = \"256\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671098 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 256 " "Parameter \"numwords_b\" = \"256\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671098 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Parameter \"operation_mode\" = \"DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671098 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671098 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671098 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rdcontrol_reg_b CLOCK0 " "Parameter \"rdcontrol_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671098 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports OLD_DATA " "Parameter \"read_during_write_mode_mixed_ports\" = \"OLD_DATA\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671098 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 21 " "Parameter \"width_a\" = \"21\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671098 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 21 " "Parameter \"width_b\" = \"21\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671098 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 8 " "Parameter \"widthad_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671098 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 8 " "Parameter \"widthad_b\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671098 ""} } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 123 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1393808671098 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_qtg1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_qtg1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_qtg1 " "Found entity 1: altsyncram_qtg1" { } { { "db/altsyncram_qtg1.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_qtg1.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808671168 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393808671168 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_qtg1 system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_tag_module:system_cpu_ic_tag\|altsyncram:the_altsyncram\|altsyncram_qtg1:auto_generated " "Elaborating entity \"altsyncram_qtg1\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_tag_module:system_cpu_ic_tag\|altsyncram:the_altsyncram\|altsyncram_qtg1:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808671168 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_bht_module system:inst_cpu\|system_cpu:cpu\|system_cpu_bht_module:system_cpu_bht " "Elaborating entity \"system_cpu_bht_module\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_bht_module:system_cpu_bht\"" { } { { "system/synthesis/submodules/system_cpu.v" "system_cpu_bht" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 7368 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808671188 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram system:inst_cpu\|system_cpu:cpu\|system_cpu_bht_module:system_cpu_bht\|altsyncram:the_altsyncram " "Elaborating entity \"altsyncram\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_bht_module:system_cpu_bht\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_altsyncram" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 189 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808671198 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_cpu:cpu\|system_cpu_bht_module:system_cpu_bht\|altsyncram:the_altsyncram " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_bht_module:system_cpu_bht\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 189 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1393808671198 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_cpu:cpu\|system_cpu_bht_module:system_cpu_bht\|altsyncram:the_altsyncram " "Instantiated megafunction \"system:inst_cpu\|system_cpu:cpu\|system_cpu_bht_module:system_cpu_bht\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671198 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file system_cpu_bht_ram.mif " "Parameter \"init_file\" = \"system_cpu_bht_ram.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671198 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 0 " "Parameter \"maximum_depth\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671198 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 256 " "Parameter \"numwords_a\" = \"256\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671198 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 256 " "Parameter \"numwords_b\" = \"256\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671198 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Parameter \"operation_mode\" = \"DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671198 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671198 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671198 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rdcontrol_reg_b CLOCK0 " "Parameter \"rdcontrol_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671198 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports OLD_DATA " "Parameter \"read_during_write_mode_mixed_ports\" = \"OLD_DATA\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671198 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 2 " "Parameter \"width_a\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671198 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 2 " "Parameter \"width_b\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671198 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 8 " "Parameter \"widthad_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671198 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 8 " "Parameter \"widthad_b\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671198 ""} } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 189 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1393808671198 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_fhg1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_fhg1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_fhg1 " "Found entity 1: altsyncram_fhg1" { } { { "db/altsyncram_fhg1.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_fhg1.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808671258 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393808671258 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_fhg1 system:inst_cpu\|system_cpu:cpu\|system_cpu_bht_module:system_cpu_bht\|altsyncram:the_altsyncram\|altsyncram_fhg1:auto_generated " "Elaborating entity \"altsyncram_fhg1\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_bht_module:system_cpu_bht\|altsyncram:the_altsyncram\|altsyncram_fhg1:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808671258 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_register_bank_a_module system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_a_module:system_cpu_register_bank_a " "Elaborating entity \"system_cpu_register_bank_a_module\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_a_module:system_cpu_register_bank_a\"" { } { { "system/synthesis/submodules/system_cpu.v" "system_cpu_register_bank_a" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 7514 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808671268 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_a_module:system_cpu_register_bank_a\|altsyncram:the_altsyncram " "Elaborating entity \"altsyncram\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_a_module:system_cpu_register_bank_a\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_altsyncram" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 252 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808671278 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_a_module:system_cpu_register_bank_a\|altsyncram:the_altsyncram " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_a_module:system_cpu_register_bank_a\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 252 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1393808671278 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_a_module:system_cpu_register_bank_a\|altsyncram:the_altsyncram " "Instantiated megafunction \"system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_a_module:system_cpu_register_bank_a\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671278 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file system_cpu_rf_ram_a.mif " "Parameter \"init_file\" = \"system_cpu_rf_ram_a.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671278 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 0 " "Parameter \"maximum_depth\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671278 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 32 " "Parameter \"numwords_a\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671278 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 32 " "Parameter \"numwords_b\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671278 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Parameter \"operation_mode\" = \"DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671278 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671278 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671278 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rdcontrol_reg_b CLOCK0 " "Parameter \"rdcontrol_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671278 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports OLD_DATA " "Parameter \"read_during_write_mode_mixed_ports\" = \"OLD_DATA\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671278 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 32 " "Parameter \"width_a\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671278 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 32 " "Parameter \"width_b\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671278 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 5 " "Parameter \"widthad_a\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671278 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 5 " "Parameter \"widthad_b\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671278 ""} } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 252 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1393808671278 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_fvf1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_fvf1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_fvf1 " "Found entity 1: altsyncram_fvf1" { } { { "db/altsyncram_fvf1.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_fvf1.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808671358 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393808671358 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_fvf1 system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_a_module:system_cpu_register_bank_a\|altsyncram:the_altsyncram\|altsyncram_fvf1:auto_generated " "Elaborating entity \"altsyncram_fvf1\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_a_module:system_cpu_register_bank_a\|altsyncram:the_altsyncram\|altsyncram_fvf1:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808671358 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_register_bank_b_module system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_b_module:system_cpu_register_bank_b " "Elaborating entity \"system_cpu_register_bank_b_module\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_b_module:system_cpu_register_bank_b\"" { } { { "system/synthesis/submodules/system_cpu.v" "system_cpu_register_bank_b" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 7535 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808671388 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_b_module:system_cpu_register_bank_b\|altsyncram:the_altsyncram " "Elaborating entity \"altsyncram\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_b_module:system_cpu_register_bank_b\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_altsyncram" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 315 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808671398 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_b_module:system_cpu_register_bank_b\|altsyncram:the_altsyncram " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_b_module:system_cpu_register_bank_b\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 315 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1393808671398 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_b_module:system_cpu_register_bank_b\|altsyncram:the_altsyncram " "Instantiated megafunction \"system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_b_module:system_cpu_register_bank_b\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671398 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file system_cpu_rf_ram_b.mif " "Parameter \"init_file\" = \"system_cpu_rf_ram_b.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671398 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 0 " "Parameter \"maximum_depth\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671398 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 32 " "Parameter \"numwords_a\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671398 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 32 " "Parameter \"numwords_b\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671398 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Parameter \"operation_mode\" = \"DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671398 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671398 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671398 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rdcontrol_reg_b CLOCK0 " "Parameter \"rdcontrol_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671398 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports OLD_DATA " "Parameter \"read_during_write_mode_mixed_ports\" = \"OLD_DATA\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671398 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 32 " "Parameter \"width_a\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671398 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 32 " "Parameter \"width_b\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671398 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 5 " "Parameter \"widthad_a\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671398 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 5 " "Parameter \"widthad_b\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671398 ""} } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 315 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1393808671398 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_gvf1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_gvf1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_gvf1 " "Found entity 1: altsyncram_gvf1" { } { { "db/altsyncram_gvf1.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_gvf1.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808671478 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393808671478 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_gvf1 system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_b_module:system_cpu_register_bank_b\|altsyncram:the_altsyncram\|altsyncram_gvf1:auto_generated " "Elaborating entity \"altsyncram_gvf1\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_b_module:system_cpu_register_bank_b\|altsyncram:the_altsyncram\|altsyncram_gvf1:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808671478 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_dc_tag_module system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_tag_module:system_cpu_dc_tag " "Elaborating entity \"system_cpu_dc_tag_module\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_tag_module:system_cpu_dc_tag\"" { } { { "system/synthesis/submodules/system_cpu.v" "system_cpu_dc_tag" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 7968 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808671508 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_tag_module:system_cpu_dc_tag\|altsyncram:the_altsyncram " "Elaborating entity \"altsyncram\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_tag_module:system_cpu_dc_tag\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_altsyncram" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 378 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808671518 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_tag_module:system_cpu_dc_tag\|altsyncram:the_altsyncram " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_tag_module:system_cpu_dc_tag\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 378 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1393808671518 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_tag_module:system_cpu_dc_tag\|altsyncram:the_altsyncram " "Instantiated megafunction \"system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_tag_module:system_cpu_dc_tag\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671518 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file system_cpu_dc_tag_ram.mif " "Parameter \"init_file\" = \"system_cpu_dc_tag_ram.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671518 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 0 " "Parameter \"maximum_depth\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671518 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 128 " "Parameter \"numwords_a\" = \"128\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671518 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 128 " "Parameter \"numwords_b\" = \"128\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671518 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Parameter \"operation_mode\" = \"DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671518 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671518 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671518 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rdcontrol_reg_b CLOCK0 " "Parameter \"rdcontrol_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671518 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports OLD_DATA " "Parameter \"read_during_write_mode_mixed_ports\" = \"OLD_DATA\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671518 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 16 " "Parameter \"width_a\" = \"16\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671518 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 16 " "Parameter \"width_b\" = \"16\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671518 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 7 " "Parameter \"widthad_a\" = \"7\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671518 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 7 " "Parameter \"widthad_b\" = \"7\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671518 ""} } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 378 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1393808671518 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_d9g1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_d9g1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_d9g1 " "Found entity 1: altsyncram_d9g1" { } { { "db/altsyncram_d9g1.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_d9g1.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808671588 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393808671588 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_d9g1 system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_tag_module:system_cpu_dc_tag\|altsyncram:the_altsyncram\|altsyncram_d9g1:auto_generated " "Elaborating entity \"altsyncram_d9g1\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_tag_module:system_cpu_dc_tag\|altsyncram:the_altsyncram\|altsyncram_d9g1:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808671588 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_dc_data_module system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_data_module:system_cpu_dc_data " "Elaborating entity \"system_cpu_dc_data_module\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_data_module:system_cpu_dc_data\"" { } { { "system/synthesis/submodules/system_cpu.v" "system_cpu_dc_data" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 8022 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808671608 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_data_module:system_cpu_dc_data\|altsyncram:the_altsyncram " "Elaborating entity \"altsyncram\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_data_module:system_cpu_dc_data\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_altsyncram" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 444 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808671618 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_data_module:system_cpu_dc_data\|altsyncram:the_altsyncram " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_data_module:system_cpu_dc_data\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 444 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1393808671618 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_data_module:system_cpu_dc_data\|altsyncram:the_altsyncram " "Instantiated megafunction \"system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_data_module:system_cpu_dc_data\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671618 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 0 " "Parameter \"maximum_depth\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671618 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 1024 " "Parameter \"numwords_a\" = \"1024\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671618 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 1024 " "Parameter \"numwords_b\" = \"1024\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671618 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Parameter \"operation_mode\" = \"DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671618 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671618 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671618 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rdcontrol_reg_b CLOCK0 " "Parameter \"rdcontrol_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671618 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671618 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 32 " "Parameter \"width_a\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671618 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 32 " "Parameter \"width_b\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671618 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 4 " "Parameter \"width_byteena_a\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671618 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 10 " "Parameter \"widthad_a\" = \"10\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671618 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 10 " "Parameter \"widthad_b\" = \"10\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671618 ""} } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 444 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1393808671618 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_2jf1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_2jf1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_2jf1 " "Found entity 1: altsyncram_2jf1" { } { { "db/altsyncram_2jf1.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_2jf1.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808671698 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393808671698 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_2jf1 system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_data_module:system_cpu_dc_data\|altsyncram:the_altsyncram\|altsyncram_2jf1:auto_generated " "Elaborating entity \"altsyncram_2jf1\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_data_module:system_cpu_dc_data\|altsyncram:the_altsyncram\|altsyncram_2jf1:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808671698 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_dc_victim_module system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_victim_module:system_cpu_dc_victim " "Elaborating entity \"system_cpu_dc_victim_module\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_victim_module:system_cpu_dc_victim\"" { } { { "system/synthesis/submodules/system_cpu.v" "system_cpu_dc_victim" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 8038 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808671708 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_victim_module:system_cpu_dc_victim\|altsyncram:the_altsyncram " "Elaborating entity \"altsyncram\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_victim_module:system_cpu_dc_victim\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_altsyncram" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 510 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808671708 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_victim_module:system_cpu_dc_victim\|altsyncram:the_altsyncram " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_victim_module:system_cpu_dc_victim\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 510 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1393808671718 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_victim_module:system_cpu_dc_victim\|altsyncram:the_altsyncram " "Instantiated megafunction \"system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_victim_module:system_cpu_dc_victim\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671718 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 0 " "Parameter \"maximum_depth\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671718 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 8 " "Parameter \"numwords_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671718 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 8 " "Parameter \"numwords_b\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671718 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Parameter \"operation_mode\" = \"DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671718 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671718 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671718 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rdcontrol_reg_b CLOCK0 " "Parameter \"rdcontrol_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671718 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports OLD_DATA " "Parameter \"read_during_write_mode_mixed_ports\" = \"OLD_DATA\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671718 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 32 " "Parameter \"width_a\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671718 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 32 " "Parameter \"width_b\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671718 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 3 " "Parameter \"widthad_a\" = \"3\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671718 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 3 " "Parameter \"widthad_b\" = \"3\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671718 ""} } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 510 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1393808671718 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_r3d1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_r3d1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_r3d1 " "Found entity 1: altsyncram_r3d1" { } { { "db/altsyncram_r3d1.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_r3d1.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808671788 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393808671788 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_r3d1 system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_victim_module:system_cpu_dc_victim\|altsyncram:the_altsyncram\|altsyncram_r3d1:auto_generated " "Elaborating entity \"altsyncram_r3d1\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_victim_module:system_cpu_dc_victim\|altsyncram:the_altsyncram\|altsyncram_r3d1:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808671798 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_mult_cell system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell " "Elaborating entity \"system_cpu_mult_cell\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_mult_cell" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 9915 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808671798 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altmult_add system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_1 " "Elaborating entity \"altmult_add\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_1\"" { } { { "system/synthesis/submodules/system_cpu_mult_cell.v" "the_altmult_add_part_1" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu_mult_cell.v" 52 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808671848 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_1 " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_1\"" { } { { "system/synthesis/submodules/system_cpu_mult_cell.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu_mult_cell.v" 52 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1393808671848 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_1 " "Instantiated megafunction \"system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_1\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "addnsub_multiplier_pipeline_aclr1 ACLR0 " "Parameter \"addnsub_multiplier_pipeline_aclr1\" = \"ACLR0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671848 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "addnsub_multiplier_pipeline_register1 CLOCK0 " "Parameter \"addnsub_multiplier_pipeline_register1\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671848 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "addnsub_multiplier_register1 UNREGISTERED " "Parameter \"addnsub_multiplier_register1\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671848 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "dedicated_multiplier_circuitry YES " "Parameter \"dedicated_multiplier_circuitry\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671848 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "input_register_a0 UNREGISTERED " "Parameter \"input_register_a0\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671848 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "input_register_b0 UNREGISTERED " "Parameter \"input_register_b0\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671848 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "input_source_a0 DATAA " "Parameter \"input_source_a0\" = \"DATAA\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671848 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "input_source_b0 DATAB " "Parameter \"input_source_b0\" = \"DATAB\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671848 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family CYCLONEIVE " "Parameter \"intended_device_family\" = \"CYCLONEIVE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671848 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altmult_add " "Parameter \"lpm_type\" = \"altmult_add\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671848 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "multiplier1_direction ADD " "Parameter \"multiplier1_direction\" = \"ADD\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671848 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "multiplier_aclr0 ACLR0 " "Parameter \"multiplier_aclr0\" = \"ACLR0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671848 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "multiplier_register0 CLOCK0 " "Parameter \"multiplier_register0\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671848 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "number_of_multipliers 1 " "Parameter \"number_of_multipliers\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671848 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_register UNREGISTERED " "Parameter \"output_register\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671848 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_addnsub1 PORT_UNUSED " "Parameter \"port_addnsub1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671848 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_addnsub3 PORT_UNUSED " "Parameter \"port_addnsub3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671848 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_signa PORT_UNUSED " "Parameter \"port_signa\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671848 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_signb PORT_UNUSED " "Parameter \"port_signb\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671848 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "representation_a UNSIGNED " "Parameter \"representation_a\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671848 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "representation_b UNSIGNED " "Parameter \"representation_b\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671848 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_pipeline_aclr_a ACLR0 " "Parameter \"signed_pipeline_aclr_a\" = \"ACLR0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671848 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_pipeline_aclr_b ACLR0 " "Parameter \"signed_pipeline_aclr_b\" = \"ACLR0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671848 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_pipeline_register_a CLOCK0 " "Parameter \"signed_pipeline_register_a\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671848 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_pipeline_register_b CLOCK0 " "Parameter \"signed_pipeline_register_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671848 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_register_a UNREGISTERED " "Parameter \"signed_register_a\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671848 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_register_b UNREGISTERED " "Parameter \"signed_register_b\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671848 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 16 " "Parameter \"width_a\" = \"16\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671848 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 16 " "Parameter \"width_b\" = \"16\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671848 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_result 32 " "Parameter \"width_result\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671848 ""} } { { "system/synthesis/submodules/system_cpu_mult_cell.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu_mult_cell.v" 52 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1393808671848 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mult_add_75u2.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mult_add_75u2.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mult_add_75u2 " "Found entity 1: mult_add_75u2" { } { { "db/mult_add_75u2.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/mult_add_75u2.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808671908 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393808671908 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mult_add_75u2 system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_1\|mult_add_75u2:auto_generated " "Elaborating entity \"mult_add_75u2\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_1\|mult_add_75u2:auto_generated\"" { } { { "altmult_add.tdf" "auto_generated" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altmult_add.tdf" 594 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808671908 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ded_mult_ks81.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/ded_mult_ks81.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 ded_mult_ks81 " "Found entity 1: ded_mult_ks81" { } { { "db/ded_mult_ks81.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/ded_mult_ks81.tdf" 30 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808671918 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393808671918 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ded_mult_ks81 system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_1\|mult_add_75u2:auto_generated\|ded_mult_ks81:ded_mult1 " "Elaborating entity \"ded_mult_ks81\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_1\|mult_add_75u2:auto_generated\|ded_mult_ks81:ded_mult1\"" { } { { "db/mult_add_75u2.tdf" "ded_mult1" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/mult_add_75u2.tdf" 33 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808671928 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/dffpipe_93c.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/dffpipe_93c.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 dffpipe_93c " "Found entity 1: dffpipe_93c" { } { { "db/dffpipe_93c.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/dffpipe_93c.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808671938 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393808671938 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dffpipe_93c system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_1\|mult_add_75u2:auto_generated\|ded_mult_ks81:ded_mult1\|dffpipe_93c:pre_result " "Elaborating entity \"dffpipe_93c\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_1\|mult_add_75u2:auto_generated\|ded_mult_ks81:ded_mult1\|dffpipe_93c:pre_result\"" { } { { "db/ded_mult_ks81.tdf" "pre_result" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/ded_mult_ks81.tdf" 50 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808671938 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altmult_add system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_2 " "Elaborating entity \"altmult_add\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_2\"" { } { { "system/synthesis/submodules/system_cpu_mult_cell.v" "the_altmult_add_part_2" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu_mult_cell.v" 93 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808671968 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_2 " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_2\"" { } { { "system/synthesis/submodules/system_cpu_mult_cell.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu_mult_cell.v" 93 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1393808671978 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_2 " "Instantiated megafunction \"system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_2\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "addnsub_multiplier_pipeline_aclr1 ACLR0 " "Parameter \"addnsub_multiplier_pipeline_aclr1\" = \"ACLR0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671978 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "addnsub_multiplier_pipeline_register1 CLOCK0 " "Parameter \"addnsub_multiplier_pipeline_register1\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671978 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "addnsub_multiplier_register1 UNREGISTERED " "Parameter \"addnsub_multiplier_register1\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671978 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "dedicated_multiplier_circuitry YES " "Parameter \"dedicated_multiplier_circuitry\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671978 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "input_register_a0 UNREGISTERED " "Parameter \"input_register_a0\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671978 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "input_register_b0 UNREGISTERED " "Parameter \"input_register_b0\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671978 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "input_source_a0 DATAA " "Parameter \"input_source_a0\" = \"DATAA\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671978 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "input_source_b0 DATAB " "Parameter \"input_source_b0\" = \"DATAB\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671978 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family CYCLONEIVE " "Parameter \"intended_device_family\" = \"CYCLONEIVE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671978 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altmult_add " "Parameter \"lpm_type\" = \"altmult_add\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671978 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "multiplier1_direction ADD " "Parameter \"multiplier1_direction\" = \"ADD\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671978 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "multiplier_aclr0 ACLR0 " "Parameter \"multiplier_aclr0\" = \"ACLR0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671978 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "multiplier_register0 CLOCK0 " "Parameter \"multiplier_register0\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671978 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "number_of_multipliers 1 " "Parameter \"number_of_multipliers\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671978 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_register UNREGISTERED " "Parameter \"output_register\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671978 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_addnsub1 PORT_UNUSED " "Parameter \"port_addnsub1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671978 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_addnsub3 PORT_UNUSED " "Parameter \"port_addnsub3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671978 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_signa PORT_UNUSED " "Parameter \"port_signa\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671978 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_signb PORT_UNUSED " "Parameter \"port_signb\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671978 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "representation_a UNSIGNED " "Parameter \"representation_a\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671978 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "representation_b UNSIGNED " "Parameter \"representation_b\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671978 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_pipeline_aclr_a ACLR0 " "Parameter \"signed_pipeline_aclr_a\" = \"ACLR0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671978 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_pipeline_aclr_b ACLR0 " "Parameter \"signed_pipeline_aclr_b\" = \"ACLR0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671978 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_pipeline_register_a CLOCK0 " "Parameter \"signed_pipeline_register_a\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671978 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_pipeline_register_b CLOCK0 " "Parameter \"signed_pipeline_register_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671978 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_register_a UNREGISTERED " "Parameter \"signed_register_a\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671978 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_register_b UNREGISTERED " "Parameter \"signed_register_b\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671978 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 16 " "Parameter \"width_a\" = \"16\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671978 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 16 " "Parameter \"width_b\" = \"16\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671978 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_result 16 " "Parameter \"width_result\" = \"16\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808671978 ""} } { { "system/synthesis/submodules/system_cpu_mult_cell.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu_mult_cell.v" 93 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1393808671978 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mult_add_95u2.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mult_add_95u2.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mult_add_95u2 " "Found entity 1: mult_add_95u2" { } { { "db/mult_add_95u2.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/mult_add_95u2.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808672038 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393808672038 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mult_add_95u2 system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_2\|mult_add_95u2:auto_generated " "Elaborating entity \"mult_add_95u2\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_2\|mult_add_95u2:auto_generated\"" { } { { "altmult_add.tdf" "auto_generated" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altmult_add.tdf" 594 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808672038 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_oci system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci " "Elaborating entity \"system_cpu_nios2_oci\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_nios2_oci" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808672048 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_oci_debug system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_debug:the_system_cpu_nios2_oci_debug " "Elaborating entity \"system_cpu_nios2_oci_debug\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_debug:the_system_cpu_nios2_oci_debug\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_nios2_oci_debug" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3444 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808672048 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_ocimem system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem " "Elaborating entity \"system_cpu_nios2_ocimem\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_nios2_ocimem" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3464 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808672048 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_ociram_lpm_dram_bdp_component_module system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem\|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component " "Elaborating entity \"system_cpu_ociram_lpm_dram_bdp_component_module\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem\|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component\"" { } { { "system/synthesis/submodules/system_cpu.v" "system_cpu_ociram_lpm_dram_bdp_component" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 872 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808672048 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem\|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component\|altsyncram:the_altsyncram " "Elaborating entity \"altsyncram\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem\|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_altsyncram" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 720 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808672058 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem\|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component\|altsyncram:the_altsyncram " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem\|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 720 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1393808672058 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem\|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component\|altsyncram:the_altsyncram " "Instantiated megafunction \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem\|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_a NONE " "Parameter \"address_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808672068 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_b NONE " "Parameter \"address_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808672068 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK1 " "Parameter \"address_reg_b\" = \"CLOCK1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808672068 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_aclr_a NONE " "Parameter \"indata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808672068 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_aclr_b NONE " "Parameter \"indata_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808672068 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file system_cpu_ociram_default_contents.mif " "Parameter \"init_file\" = \"system_cpu_ociram_default_contents.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808672068 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family CYCLONEIVE " "Parameter \"intended_device_family\" = \"CYCLONEIVE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808672068 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808672068 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 256 " "Parameter \"numwords_a\" = \"256\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808672068 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 256 " "Parameter \"numwords_b\" = \"256\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808672068 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode BIDIR_DUAL_PORT " "Parameter \"operation_mode\" = \"BIDIR_DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808672068 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808672068 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_b NONE " "Parameter \"outdata_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808672068 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a UNREGISTERED " "Parameter \"outdata_reg_a\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808672068 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808672068 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808672068 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports OLD_DATA " "Parameter \"read_during_write_mode_mixed_ports\" = \"OLD_DATA\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808672068 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 32 " "Parameter \"width_a\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808672068 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 32 " "Parameter \"width_b\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808672068 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 4 " "Parameter \"width_byteena_a\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808672068 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 8 " "Parameter \"widthad_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808672068 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 8 " "Parameter \"widthad_b\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808672068 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_aclr_a NONE " "Parameter \"wrcontrol_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808672068 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_aclr_b NONE " "Parameter \"wrcontrol_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808672068 ""} } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 720 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1393808672068 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_jt72.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_jt72.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_jt72 " "Found entity 1: altsyncram_jt72" { } { { "db/altsyncram_jt72.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_jt72.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808672158 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393808672158 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_jt72 system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem\|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_jt72:auto_generated " "Elaborating entity \"altsyncram_jt72\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem\|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_jt72:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808672158 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_avalon_reg system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg " "Elaborating entity \"system_cpu_nios2_avalon_reg\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_nios2_avalon_reg" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3484 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808672188 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_oci_break system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_break:the_system_cpu_nios2_oci_break " "Elaborating entity \"system_cpu_nios2_oci_break\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_break:the_system_cpu_nios2_oci_break\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_nios2_oci_break" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3515 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808672188 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_oci_xbrk system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_xbrk:the_system_cpu_nios2_oci_xbrk " "Elaborating entity \"system_cpu_nios2_oci_xbrk\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_xbrk:the_system_cpu_nios2_oci_xbrk\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_nios2_oci_xbrk" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3538 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808672198 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_oci_dbrk system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_dbrk:the_system_cpu_nios2_oci_dbrk " "Elaborating entity \"system_cpu_nios2_oci_dbrk\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_dbrk:the_system_cpu_nios2_oci_dbrk\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_nios2_oci_dbrk" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3565 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808672198 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_oci_itrace system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_itrace:the_system_cpu_nios2_oci_itrace " "Elaborating entity \"system_cpu_nios2_oci_itrace\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_itrace:the_system_cpu_nios2_oci_itrace\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_nios2_oci_itrace" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3606 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808672198 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_oci_dtrace system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_dtrace:the_system_cpu_nios2_oci_dtrace " "Elaborating entity \"system_cpu_nios2_oci_dtrace\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_dtrace:the_system_cpu_nios2_oci_dtrace\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_nios2_oci_dtrace" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3621 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808672198 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_oci_td_mode system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_dtrace:the_system_cpu_nios2_oci_dtrace\|system_cpu_nios2_oci_td_mode:system_cpu_nios2_oci_trc_ctrl_td_mode " "Elaborating entity \"system_cpu_nios2_oci_td_mode\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_dtrace:the_system_cpu_nios2_oci_dtrace\|system_cpu_nios2_oci_td_mode:system_cpu_nios2_oci_trc_ctrl_td_mode\"" { } { { "system/synthesis/submodules/system_cpu.v" "system_cpu_nios2_oci_trc_ctrl_td_mode" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 2213 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808672208 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_oci_fifo system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_fifo:the_system_cpu_nios2_oci_fifo " "Elaborating entity \"system_cpu_nios2_oci_fifo\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_fifo:the_system_cpu_nios2_oci_fifo\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_nios2_oci_fifo" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3640 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808672208 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_oci_compute_tm_count system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_fifo:the_system_cpu_nios2_oci_fifo\|system_cpu_nios2_oci_compute_tm_count:system_cpu_nios2_oci_compute_tm_count_tm_count " "Elaborating entity \"system_cpu_nios2_oci_compute_tm_count\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_fifo:the_system_cpu_nios2_oci_fifo\|system_cpu_nios2_oci_compute_tm_count:system_cpu_nios2_oci_compute_tm_count_tm_count\"" { } { { "system/synthesis/submodules/system_cpu.v" "system_cpu_nios2_oci_compute_tm_count_tm_count" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 2545 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808672208 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_oci_fifowp_inc system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_fifo:the_system_cpu_nios2_oci_fifo\|system_cpu_nios2_oci_fifowp_inc:system_cpu_nios2_oci_fifowp_inc_fifowp " "Elaborating entity \"system_cpu_nios2_oci_fifowp_inc\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_fifo:the_system_cpu_nios2_oci_fifo\|system_cpu_nios2_oci_fifowp_inc:system_cpu_nios2_oci_fifowp_inc_fifowp\"" { } { { "system/synthesis/submodules/system_cpu.v" "system_cpu_nios2_oci_fifowp_inc_fifowp" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 2555 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808672208 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_oci_fifocount_inc system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_fifo:the_system_cpu_nios2_oci_fifo\|system_cpu_nios2_oci_fifocount_inc:system_cpu_nios2_oci_fifocount_inc_fifocount " "Elaborating entity \"system_cpu_nios2_oci_fifocount_inc\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_fifo:the_system_cpu_nios2_oci_fifo\|system_cpu_nios2_oci_fifocount_inc:system_cpu_nios2_oci_fifocount_inc_fifocount\"" { } { { "system/synthesis/submodules/system_cpu.v" "system_cpu_nios2_oci_fifocount_inc_fifocount" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 2565 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808672208 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_oci_test_bench system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_fifo:the_system_cpu_nios2_oci_fifo\|system_cpu_oci_test_bench:the_system_cpu_oci_test_bench " "Elaborating entity \"system_cpu_oci_test_bench\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_fifo:the_system_cpu_nios2_oci_fifo\|system_cpu_oci_test_bench:the_system_cpu_oci_test_bench\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_oci_test_bench" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 2574 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808672208 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_oci_pib system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_pib:the_system_cpu_nios2_oci_pib " "Elaborating entity \"system_cpu_nios2_oci_pib\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_pib:the_system_cpu_nios2_oci_pib\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_nios2_oci_pib" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3650 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808672218 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_oci_im system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im " "Elaborating entity \"system_cpu_nios2_oci_im\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_nios2_oci_im" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808672218 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_traceram_lpm_dram_bdp_component_module system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component " "Elaborating entity \"system_cpu_traceram_lpm_dram_bdp_component_module\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\"" { } { { "system/synthesis/submodules/system_cpu.v" "system_cpu_traceram_lpm_dram_bdp_component" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808672218 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram " "Elaborating entity \"altsyncram\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_altsyncram" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808672228 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1393808672228 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram " "Instantiated megafunction \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_a NONE " "Parameter \"address_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808672228 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_b NONE " "Parameter \"address_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808672228 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK1 " "Parameter \"address_reg_b\" = \"CLOCK1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808672228 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_aclr_a NONE " "Parameter \"indata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808672228 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_aclr_b NONE " "Parameter \"indata_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808672228 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file UNUSED " "Parameter \"init_file\" = \"UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808672228 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family CYCLONEIVE " "Parameter \"intended_device_family\" = \"CYCLONEIVE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808672228 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808672228 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 128 " "Parameter \"numwords_a\" = \"128\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808672228 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 128 " "Parameter \"numwords_b\" = \"128\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808672228 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode BIDIR_DUAL_PORT " "Parameter \"operation_mode\" = \"BIDIR_DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808672228 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808672228 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_b NONE " "Parameter \"outdata_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808672228 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a UNREGISTERED " "Parameter \"outdata_reg_a\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808672228 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808672228 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808672228 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports OLD_DATA " "Parameter \"read_during_write_mode_mixed_ports\" = \"OLD_DATA\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808672228 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 36 " "Parameter \"width_a\" = \"36\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808672228 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 36 " "Parameter \"width_b\" = \"36\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808672228 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 7 " "Parameter \"widthad_a\" = \"7\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808672228 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 7 " "Parameter \"widthad_b\" = \"7\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808672228 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_aclr_a NONE " "Parameter \"wrcontrol_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808672228 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_aclr_b NONE " "Parameter \"wrcontrol_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808672228 ""} } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1393808672228 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_0a02.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_0a02.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_0a02 " "Found entity 1: altsyncram_0a02" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808672318 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393808672318 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_0a02 system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated " "Elaborating entity \"altsyncram_0a02\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808672318 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_jtag_debug_module_wrapper system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper " "Elaborating entity \"system_cpu_jtag_debug_module_wrapper\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_jtag_debug_module_wrapper" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3714 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808672328 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_jtag_debug_module_tck system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck " "Elaborating entity \"system_cpu_jtag_debug_module_tck\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck\"" { } { { "system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v" "the_system_cpu_jtag_debug_module_tck" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v" 165 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808672328 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_std_synchronizer system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck\|altera_std_synchronizer:the_altera_std_synchronizer " "Elaborating entity \"altera_std_synchronizer\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck\|altera_std_synchronizer:the_altera_std_synchronizer\"" { } { { "system/synthesis/submodules/system_cpu_jtag_debug_module_tck.v" "the_altera_std_synchronizer" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu_jtag_debug_module_tck.v" 202 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808672348 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck\|altera_std_synchronizer:the_altera_std_synchronizer " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck\|altera_std_synchronizer:the_altera_std_synchronizer\"" { } { { "system/synthesis/submodules/system_cpu_jtag_debug_module_tck.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu_jtag_debug_module_tck.v" 202 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1393808672348 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck\|altera_std_synchronizer:the_altera_std_synchronizer " "Instantiated megafunction \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck\|altera_std_synchronizer:the_altera_std_synchronizer\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "depth 2 " "Parameter \"depth\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808672348 ""} } { { "system/synthesis/submodules/system_cpu_jtag_debug_module_tck.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu_jtag_debug_module_tck.v" 202 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1393808672348 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_jtag_debug_module_sysclk system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk " "Elaborating entity \"system_cpu_jtag_debug_module_sysclk\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk\"" { } { { "system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v" "the_system_cpu_jtag_debug_module_sysclk" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v" 188 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808672348 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sld_virtual_jtag_basic system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy " "Elaborating entity \"sld_virtual_jtag_basic\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy\"" { } { { "system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v" "system_cpu_jtag_debug_module_phy" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v" 218 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808672368 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy\"" { } { { "system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v" 218 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1393808672368 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy " "Instantiated megafunction \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_auto_instance_index YES " "Parameter \"sld_auto_instance_index\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808672368 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_instance_index 0 " "Parameter \"sld_instance_index\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808672368 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_ir_width 2 " "Parameter \"sld_ir_width\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808672368 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_mfg_id 70 " "Parameter \"sld_mfg_id\" = \"70\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808672368 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_sim_action " "Parameter \"sld_sim_action\" = \"\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808672368 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_sim_n_scan 0 " "Parameter \"sld_sim_n_scan\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808672368 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_sim_total_length 0 " "Parameter \"sld_sim_total_length\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808672368 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_type_id 34 " "Parameter \"sld_type_id\" = \"34\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808672368 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_version 3 " "Parameter \"sld_version\" = \"3\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808672368 ""} } { { "system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v" 218 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1393808672368 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sld_virtual_jtag_impl system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy\|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst " "Elaborating entity \"sld_virtual_jtag_impl\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy\|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst\"" { } { { "sld_virtual_jtag_basic.v" "sld_virtual_jtag_impl_inst" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/sld_virtual_jtag_basic.v" 151 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808672378 ""} -{ "Info" "ISGN_MEGAFN_DESCENDANT" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy\|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy\|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst\", which is child of megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy\"" { } { { "sld_virtual_jtag_basic.v" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/sld_virtual_jtag_basic.v" 151 0 0 } } { "system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v" 218 0 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0 -1 1393808672378 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_sysid system:inst_cpu\|system_sysid:sysid " "Elaborating entity \"system_sysid\" for hierarchy \"system:inst_cpu\|system_sysid:sysid\"" { } { { "system/synthesis/system.v" "sysid" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 856 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808672378 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_sdram system:inst_cpu\|system_sdram:sdram " "Elaborating entity \"system_sdram\" for hierarchy \"system:inst_cpu\|system_sdram:sdram\"" { } { { "system/synthesis/system.v" "sdram" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 879 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808672378 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_sdram_input_efifo_module system:inst_cpu\|system_sdram:sdram\|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module " "Elaborating entity \"system_sdram_input_efifo_module\" for hierarchy \"system:inst_cpu\|system_sdram:sdram\|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module\"" { } { { "system/synthesis/submodules/system_sdram.v" "the_system_sdram_input_efifo_module" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_sdram.v" 296 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808672388 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_sys_clk_timer system:inst_cpu\|system_sys_clk_timer:sys_clk_timer " "Elaborating entity \"system_sys_clk_timer\" for hierarchy \"system:inst_cpu\|system_sys_clk_timer:sys_clk_timer\"" { } { { "system/synthesis/system.v" "sys_clk_timer" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 890 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808672388 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_uart_wifi system:inst_cpu\|system_uart_wifi:uart_wifi " "Elaborating entity \"system_uart_wifi\" for hierarchy \"system:inst_cpu\|system_uart_wifi:uart_wifi\"" { } { { "system/synthesis/system.v" "uart_wifi" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 907 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808672388 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_uart_wifi_tx system:inst_cpu\|system_uart_wifi:uart_wifi\|system_uart_wifi_tx:the_system_uart_wifi_tx " "Elaborating entity \"system_uart_wifi_tx\" for hierarchy \"system:inst_cpu\|system_uart_wifi:uart_wifi\|system_uart_wifi_tx:the_system_uart_wifi_tx\"" { } { { "system/synthesis/submodules/system_uart_wifi.v" "the_system_uart_wifi_tx" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_wifi.v" 1079 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808672398 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_uart_wifi_rx system:inst_cpu\|system_uart_wifi:uart_wifi\|system_uart_wifi_rx:the_system_uart_wifi_rx " "Elaborating entity \"system_uart_wifi_rx\" for hierarchy \"system:inst_cpu\|system_uart_wifi:uart_wifi\|system_uart_wifi_rx:the_system_uart_wifi_rx\"" { } { { "system/synthesis/submodules/system_uart_wifi.v" "the_system_uart_wifi_rx" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_wifi.v" 1097 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808672398 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_uart_wifi_rx_stimulus_source system:inst_cpu\|system_uart_wifi:uart_wifi\|system_uart_wifi_rx:the_system_uart_wifi_rx\|system_uart_wifi_rx_stimulus_source:the_system_uart_wifi_rx_stimulus_source " "Elaborating entity \"system_uart_wifi_rx_stimulus_source\" for hierarchy \"system:inst_cpu\|system_uart_wifi:uart_wifi\|system_uart_wifi_rx:the_system_uart_wifi_rx\|system_uart_wifi_rx_stimulus_source:the_system_uart_wifi_rx_stimulus_source\"" { } { { "system/synthesis/submodules/system_uart_wifi.v" "the_system_uart_wifi_rx_stimulus_source" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_wifi.v" 569 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808672398 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_uart_wifi_regs system:inst_cpu\|system_uart_wifi:uart_wifi\|system_uart_wifi_regs:the_system_uart_wifi_regs " "Elaborating entity \"system_uart_wifi_regs\" for hierarchy \"system:inst_cpu\|system_uart_wifi:uart_wifi\|system_uart_wifi_regs:the_system_uart_wifi_regs\"" { } { { "system/synthesis/submodules/system_uart_wifi.v" "the_system_uart_wifi_regs" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_wifi.v" 1128 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808672408 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_pio_led system:inst_cpu\|system_pio_led:pio_led " "Elaborating entity \"system_pio_led\" for hierarchy \"system:inst_cpu\|system_pio_led:pio_led\"" { } { { "system/synthesis/system.v" "pio_led" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 918 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808672408 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_pio_key_left system:inst_cpu\|system_pio_key_left:pio_key_left " "Elaborating entity \"system_pio_key_left\" for hierarchy \"system:inst_cpu\|system_pio_key_left:pio_key_left\"" { } { { "system/synthesis/system.v" "pio_key_left" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 930 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808672408 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_pio_sw system:inst_cpu\|system_pio_sw:pio_sw " "Elaborating entity \"system_pio_sw\" for hierarchy \"system:inst_cpu\|system_pio_sw:pio_sw\"" { } { { "system/synthesis/system.v" "pio_sw" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 938 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808672408 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_jtag_uart_0 system:inst_cpu\|system_jtag_uart_0:jtag_uart_0 " "Elaborating entity \"system_jtag_uart_0\" for hierarchy \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\"" { } { { "system/synthesis/system.v" "jtag_uart_0" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 951 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808672418 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_jtag_uart_0_scfifo_w system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w " "Elaborating entity \"system_jtag_uart_0_scfifo_w\" for hierarchy \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\"" { } { { "system/synthesis/submodules/system_jtag_uart_0.v" "the_system_jtag_uart_0_scfifo_w" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_jtag_uart_0.v" 625 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808672418 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scfifo system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo " "Elaborating entity \"scfifo\" for hierarchy \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\"" { } { { "system/synthesis/submodules/system_jtag_uart_0.v" "wfifo" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_jtag_uart_0.v" 183 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808672468 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo " "Elaborated megafunction instantiation \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\"" { } { { "system/synthesis/submodules/system_jtag_uart_0.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_jtag_uart_0.v" 183 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1393808672468 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo " "Instantiated megafunction \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint RAM_BLOCK_TYPE=AUTO " "Parameter \"lpm_hint\" = \"RAM_BLOCK_TYPE=AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808672468 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_numwords 64 " "Parameter \"lpm_numwords\" = \"64\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808672468 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_showahead OFF " "Parameter \"lpm_showahead\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808672468 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type scfifo " "Parameter \"lpm_type\" = \"scfifo\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808672468 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 8 " "Parameter \"lpm_width\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808672468 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widthu 6 " "Parameter \"lpm_widthu\" = \"6\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808672468 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "overflow_checking OFF " "Parameter \"overflow_checking\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808672468 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "underflow_checking OFF " "Parameter \"underflow_checking\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808672468 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "use_eab ON " "Parameter \"use_eab\" = \"ON\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808672468 ""} } { { "system/synthesis/submodules/system_jtag_uart_0.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_jtag_uart_0.v" 183 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1393808672468 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/scfifo_jr21.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/scfifo_jr21.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 scfifo_jr21 " "Found entity 1: scfifo_jr21" { } { { "db/scfifo_jr21.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/scfifo_jr21.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808672518 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393808672518 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scfifo_jr21 system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated " "Elaborating entity \"scfifo_jr21\" for hierarchy \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\"" { } { { "scfifo.tdf" "auto_generated" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/scfifo.tdf" 296 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808672518 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_dpfifo_q131.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/a_dpfifo_q131.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_dpfifo_q131 " "Found entity 1: a_dpfifo_q131" { } { { "db/a_dpfifo_q131.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/a_dpfifo_q131.tdf" 28 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808672528 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393808672528 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_dpfifo_q131 system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo " "Elaborating entity \"a_dpfifo_q131\" for hierarchy \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\"" { } { { "db/scfifo_jr21.tdf" "dpfifo" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/scfifo_jr21.tdf" 37 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808672538 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_fefifo_7cf.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/a_fefifo_7cf.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_fefifo_7cf " "Found entity 1: a_fefifo_7cf" { } { { "db/a_fefifo_7cf.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/a_fefifo_7cf.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808672538 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393808672538 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_fefifo_7cf system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|a_fefifo_7cf:fifo_state " "Elaborating entity \"a_fefifo_7cf\" for hierarchy \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|a_fefifo_7cf:fifo_state\"" { } { { "db/a_dpfifo_q131.tdf" "fifo_state" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/a_dpfifo_q131.tdf" 42 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808672548 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_do7.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_do7.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_do7 " "Found entity 1: cntr_do7" { } { { "db/cntr_do7.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/cntr_do7.tdf" 25 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808672598 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393808672598 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_do7 system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|a_fefifo_7cf:fifo_state\|cntr_do7:count_usedw " "Elaborating entity \"cntr_do7\" for hierarchy \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|a_fefifo_7cf:fifo_state\|cntr_do7:count_usedw\"" { } { { "db/a_fefifo_7cf.tdf" "count_usedw" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/a_fefifo_7cf.tdf" 38 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808672598 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/dpram_nl21.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/dpram_nl21.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 dpram_nl21 " "Found entity 1: dpram_nl21" { } { { "db/dpram_nl21.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/dpram_nl21.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808672658 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393808672658 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dpram_nl21 system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|dpram_nl21:FIFOram " "Elaborating entity \"dpram_nl21\" for hierarchy \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|dpram_nl21:FIFOram\"" { } { { "db/a_dpfifo_q131.tdf" "FIFOram" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/a_dpfifo_q131.tdf" 43 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808672658 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_r1m1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_r1m1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_r1m1 " "Found entity 1: altsyncram_r1m1" { } { { "db/altsyncram_r1m1.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_r1m1.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808672718 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393808672718 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_r1m1 system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|dpram_nl21:FIFOram\|altsyncram_r1m1:altsyncram1 " "Elaborating entity \"altsyncram_r1m1\" for hierarchy \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|dpram_nl21:FIFOram\|altsyncram_r1m1:altsyncram1\"" { } { { "db/dpram_nl21.tdf" "altsyncram1" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/dpram_nl21.tdf" 36 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808672718 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_1ob.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_1ob.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_1ob " "Found entity 1: cntr_1ob" { } { { "db/cntr_1ob.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/cntr_1ob.tdf" 25 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808672768 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393808672768 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_1ob system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|cntr_1ob:rd_ptr_count " "Elaborating entity \"cntr_1ob\" for hierarchy \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|cntr_1ob:rd_ptr_count\"" { } { { "db/a_dpfifo_q131.tdf" "rd_ptr_count" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/a_dpfifo_q131.tdf" 44 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808672778 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_jtag_uart_0_scfifo_r system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r " "Elaborating entity \"system_jtag_uart_0_scfifo_r\" for hierarchy \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r\"" { } { { "system/synthesis/submodules/system_jtag_uart_0.v" "the_system_jtag_uart_0_scfifo_r" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_jtag_uart_0.v" 639 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808672778 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_jtag_atlantic system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic " "Elaborating entity \"alt_jtag_atlantic\" for hierarchy \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic\"" { } { { "system/synthesis/submodules/system_jtag_uart_0.v" "system_jtag_uart_0_alt_jtag_atlantic" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_jtag_uart_0.v" 774 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808672898 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic " "Elaborated megafunction instantiation \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic\"" { } { { "system/synthesis/submodules/system_jtag_uart_0.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_jtag_uart_0.v" 774 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1393808672898 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic " "Instantiated megafunction \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "INSTANCE_ID 0 " "Parameter \"INSTANCE_ID\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808672898 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LOG2_RXFIFO_DEPTH 6 " "Parameter \"LOG2_RXFIFO_DEPTH\" = \"6\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808672898 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LOG2_TXFIFO_DEPTH 6 " "Parameter \"LOG2_TXFIFO_DEPTH\" = \"6\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808672898 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "SLD_AUTO_INSTANCE_INDEX YES " "Parameter \"SLD_AUTO_INSTANCE_INDEX\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808672898 ""} } { { "system/synthesis/submodules/system_jtag_uart_0.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_jtag_uart_0.v" 774 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1393808672898 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_pio_ir_emitter system:inst_cpu\|system_pio_ir_emitter:pio_ir_emitter " "Elaborating entity \"system_pio_ir_emitter\" for hierarchy \"system:inst_cpu\|system_pio_ir_emitter:pio_ir_emitter\"" { } { { "system/synthesis/system.v" "pio_ir_emitter" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 962 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808672908 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_uart_mc system:inst_cpu\|system_uart_mc:uart_mc " "Elaborating entity \"system_uart_mc\" for hierarchy \"system:inst_cpu\|system_uart_mc:uart_mc\"" { } { { "system/synthesis/system.v" "uart_mc" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 979 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808672908 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_uart_mc_tx system:inst_cpu\|system_uart_mc:uart_mc\|system_uart_mc_tx:the_system_uart_mc_tx " "Elaborating entity \"system_uart_mc_tx\" for hierarchy \"system:inst_cpu\|system_uart_mc:uart_mc\|system_uart_mc_tx:the_system_uart_mc_tx\"" { } { { "system/synthesis/submodules/system_uart_mc.v" "the_system_uart_mc_tx" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_mc.v" 1068 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808672908 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_uart_mc_rx system:inst_cpu\|system_uart_mc:uart_mc\|system_uart_mc_rx:the_system_uart_mc_rx " "Elaborating entity \"system_uart_mc_rx\" for hierarchy \"system:inst_cpu\|system_uart_mc:uart_mc\|system_uart_mc_rx:the_system_uart_mc_rx\"" { } { { "system/synthesis/submodules/system_uart_mc.v" "the_system_uart_mc_rx" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_mc.v" 1086 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808672908 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_uart_mc_rx_stimulus_source system:inst_cpu\|system_uart_mc:uart_mc\|system_uart_mc_rx:the_system_uart_mc_rx\|system_uart_mc_rx_stimulus_source:the_system_uart_mc_rx_stimulus_source " "Elaborating entity \"system_uart_mc_rx_stimulus_source\" for hierarchy \"system:inst_cpu\|system_uart_mc:uart_mc\|system_uart_mc_rx:the_system_uart_mc_rx\|system_uart_mc_rx_stimulus_source:the_system_uart_mc_rx_stimulus_source\"" { } { { "system/synthesis/submodules/system_uart_mc.v" "the_system_uart_mc_rx_stimulus_source" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_mc.v" 569 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808672918 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_uart_mc_regs system:inst_cpu\|system_uart_mc:uart_mc\|system_uart_mc_regs:the_system_uart_mc_regs " "Elaborating entity \"system_uart_mc_regs\" for hierarchy \"system:inst_cpu\|system_uart_mc:uart_mc\|system_uart_mc_regs:the_system_uart_mc_regs\"" { } { { "system/synthesis/submodules/system_uart_mc.v" "the_system_uart_mc_regs" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_mc.v" 1117 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808672918 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_rs232_wifi system:inst_cpu\|system_rs232_wifi:rs232_wifi " "Elaborating entity \"system_rs232_wifi\" for hierarchy \"system:inst_cpu\|system_rs232_wifi:rs232_wifi\"" { } { { "system/synthesis/system.v" "rs232_wifi" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 994 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808672918 ""} -{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "write_data_parity system_rs232_wifi.v(123) " "Verilog HDL or VHDL warning at system_rs232_wifi.v(123): object \"write_data_parity\" assigned a value but never read" { } { { "system/synthesis/submodules/system_rs232_wifi.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_rs232_wifi.v" 123 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 -1 1393808672928 "|de0_nano_system|system:inst_cpu|system_rs232_wifi:rs232_wifi"} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_up_rs232_in_deserializer system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer " "Elaborating entity \"altera_up_rs232_in_deserializer\" for hierarchy \"system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\"" { } { { "system/synthesis/submodules/system_rs232_wifi.v" "RS232_In_Deserializer" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_rs232_wifi.v" 268 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808672928 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_up_rs232_counters system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_rs232_counters:RS232_In_Counters " "Elaborating entity \"altera_up_rs232_counters\" for hierarchy \"system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_rs232_counters:RS232_In_Counters\"" { } { { "system/synthesis/submodules/altera_up_rs232_in_deserializer.v" "RS232_In_Counters" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_up_rs232_in_deserializer.v" 181 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808672928 ""} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 altera_up_rs232_counters.v(124) " "Verilog HDL assignment warning at altera_up_rs232_counters.v(124): truncated value with size 32 to match size of target (14)" { } { { "system/synthesis/submodules/altera_up_rs232_counters.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_up_rs232_counters.v" 124 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 -1 1393808672928 "|de0_nano_system|system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_rs232_counters:RS232_In_Counters"} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_up_sync_fifo system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO " "Elaborating entity \"altera_up_sync_fifo\" for hierarchy \"system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\"" { } { { "system/synthesis/submodules/altera_up_rs232_in_deserializer.v" "RS232_In_FIFO" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_up_rs232_in_deserializer.v" 206 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808672928 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scfifo system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO " "Elaborating entity \"scfifo\" for hierarchy \"system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\"" { } { { "system/synthesis/submodules/altera_up_sync_fifo.v" "Sync_FIFO" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_up_sync_fifo.v" 157 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808672958 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO " "Elaborated megafunction instantiation \"system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\"" { } { { "system/synthesis/submodules/altera_up_sync_fifo.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_up_sync_fifo.v" 157 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1393808672958 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO " "Instantiated megafunction \"system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "add_ram_output_register OFF " "Parameter \"add_ram_output_register\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808672958 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone II " "Parameter \"intended_device_family\" = \"Cyclone II\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808672958 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_numwords 128 " "Parameter \"lpm_numwords\" = \"128\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808672958 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_showahead ON " "Parameter \"lpm_showahead\" = \"ON\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808672958 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type scfifo " "Parameter \"lpm_type\" = \"scfifo\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808672958 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 8 " "Parameter \"lpm_width\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808672958 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widthu 7 " "Parameter \"lpm_widthu\" = \"7\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808672958 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "overflow_checking OFF " "Parameter \"overflow_checking\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808672958 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "underflow_checking OFF " "Parameter \"underflow_checking\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808672958 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "use_eab ON " "Parameter \"use_eab\" = \"ON\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808672958 ""} } { { "system/synthesis/submodules/altera_up_sync_fifo.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_up_sync_fifo.v" 157 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1393808672958 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/scfifo_a341.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/scfifo_a341.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 scfifo_a341 " "Found entity 1: scfifo_a341" { } { { "db/scfifo_a341.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/scfifo_a341.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808673018 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393808673018 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scfifo_a341 system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated " "Elaborating entity \"scfifo_a341\" for hierarchy \"system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\"" { } { { "scfifo.tdf" "auto_generated" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/scfifo.tdf" 296 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808673018 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_dpfifo_tq31.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/a_dpfifo_tq31.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_dpfifo_tq31 " "Found entity 1: a_dpfifo_tq31" { } { { "db/a_dpfifo_tq31.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/a_dpfifo_tq31.tdf" 32 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808673028 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393808673028 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_dpfifo_tq31 system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo " "Elaborating entity \"a_dpfifo_tq31\" for hierarchy \"system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\"" { } { { "db/scfifo_a341.tdf" "dpfifo" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/scfifo_a341.tdf" 37 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808673028 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_je81.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_je81.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_je81 " "Found entity 1: altsyncram_je81" { } { { "db/altsyncram_je81.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_je81.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808673088 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393808673088 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_je81 system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|altsyncram_je81:FIFOram " "Elaborating entity \"altsyncram_je81\" for hierarchy \"system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|altsyncram_je81:FIFOram\"" { } { { "db/a_dpfifo_tq31.tdf" "FIFOram" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/a_dpfifo_tq31.tdf" 45 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808673088 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cmpr_ks8.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cmpr_ks8.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cmpr_ks8 " "Found entity 1: cmpr_ks8" { } { { "db/cmpr_ks8.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/cmpr_ks8.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808673138 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393808673138 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cmpr_ks8 system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cmpr_ks8:almost_full_comparer " "Elaborating entity \"cmpr_ks8\" for hierarchy \"system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cmpr_ks8:almost_full_comparer\"" { } { { "db/a_dpfifo_tq31.tdf" "almost_full_comparer" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/a_dpfifo_tq31.tdf" 54 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808673148 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cmpr_ks8 system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cmpr_ks8:three_comparison " "Elaborating entity \"cmpr_ks8\" for hierarchy \"system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cmpr_ks8:three_comparison\"" { } { { "db/a_dpfifo_tq31.tdf" "three_comparison" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/a_dpfifo_tq31.tdf" 55 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808673148 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_v9b.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_v9b.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_v9b " "Found entity 1: cntr_v9b" { } { { "db/cntr_v9b.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/cntr_v9b.tdf" 25 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808673198 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393808673198 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_v9b system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_v9b:rd_ptr_msb " "Elaborating entity \"cntr_v9b\" for hierarchy \"system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_v9b:rd_ptr_msb\"" { } { { "db/a_dpfifo_tq31.tdf" "rd_ptr_msb" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/a_dpfifo_tq31.tdf" 56 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808673208 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_ca7.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_ca7.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_ca7 " "Found entity 1: cntr_ca7" { } { { "db/cntr_ca7.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/cntr_ca7.tdf" 25 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808673258 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393808673258 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_ca7 system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_ca7:usedw_counter " "Elaborating entity \"cntr_ca7\" for hierarchy \"system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_ca7:usedw_counter\"" { } { { "db/a_dpfifo_tq31.tdf" "usedw_counter" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/a_dpfifo_tq31.tdf" 57 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808673258 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_0ab.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_0ab.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_0ab " "Found entity 1: cntr_0ab" { } { { "db/cntr_0ab.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/cntr_0ab.tdf" 25 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808673318 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393808673318 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_0ab system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr " "Elaborating entity \"cntr_0ab\" for hierarchy \"system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr\"" { } { { "db/a_dpfifo_tq31.tdf" "wr_ptr" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/a_dpfifo_tq31.tdf" 58 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808673318 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_up_rs232_out_serializer system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_out_serializer:RS232_Out_Serializer " "Elaborating entity \"altera_up_rs232_out_serializer\" for hierarchy \"system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_out_serializer:RS232_Out_Serializer\"" { } { { "system/synthesis/submodules/system_rs232_wifi.v" "RS232_Out_Serializer" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_rs232_wifi.v" 290 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808673318 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_master_translator system:inst_cpu\|altera_merlin_master_translator:cpu_instruction_master_translator " "Elaborating entity \"altera_merlin_master_translator\" for hierarchy \"system:inst_cpu\|altera_merlin_master_translator:cpu_instruction_master_translator\"" { } { { "system/synthesis/system.v" "cpu_instruction_master_translator" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 1048 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808673378 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_master_translator system:inst_cpu\|altera_merlin_master_translator:cpu_data_master_translator " "Elaborating entity \"altera_merlin_master_translator\" for hierarchy \"system:inst_cpu\|altera_merlin_master_translator:cpu_data_master_translator\"" { } { { "system/synthesis/system.v" "cpu_data_master_translator" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 1102 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808673388 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_translator system:inst_cpu\|altera_merlin_slave_translator:cpu_jtag_debug_module_translator " "Elaborating entity \"altera_merlin_slave_translator\" for hierarchy \"system:inst_cpu\|altera_merlin_slave_translator:cpu_jtag_debug_module_translator\"" { } { { "system/synthesis/system.v" "cpu_jtag_debug_module_translator" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 1160 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808673388 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_translator system:inst_cpu\|altera_merlin_slave_translator:sdram_s1_translator " "Elaborating entity \"altera_merlin_slave_translator\" for hierarchy \"system:inst_cpu\|altera_merlin_slave_translator:sdram_s1_translator\"" { } { { "system/synthesis/system.v" "sdram_s1_translator" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 1218 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808673388 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_translator system:inst_cpu\|altera_merlin_slave_translator:sysid_control_slave_translator " "Elaborating entity \"altera_merlin_slave_translator\" for hierarchy \"system:inst_cpu\|altera_merlin_slave_translator:sysid_control_slave_translator\"" { } { { "system/synthesis/system.v" "sysid_control_slave_translator" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 1276 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808673388 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_translator system:inst_cpu\|altera_merlin_slave_translator:sys_clk_timer_s1_translator " "Elaborating entity \"altera_merlin_slave_translator\" for hierarchy \"system:inst_cpu\|altera_merlin_slave_translator:sys_clk_timer_s1_translator\"" { } { { "system/synthesis/system.v" "sys_clk_timer_s1_translator" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 1334 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808673398 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_translator system:inst_cpu\|altera_merlin_slave_translator:uart_wifi_s1_translator " "Elaborating entity \"altera_merlin_slave_translator\" for hierarchy \"system:inst_cpu\|altera_merlin_slave_translator:uart_wifi_s1_translator\"" { } { { "system/synthesis/system.v" "uart_wifi_s1_translator" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 1392 0 0 } } } 0 12128 "Elaborating entity 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"C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 1508 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808673398 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_translator system:inst_cpu\|altera_merlin_slave_translator:jtag_uart_0_avalon_jtag_slave_translator " "Elaborating entity \"altera_merlin_slave_translator\" for hierarchy \"system:inst_cpu\|altera_merlin_slave_translator:jtag_uart_0_avalon_jtag_slave_translator\"" { } { { "system/synthesis/system.v" "jtag_uart_0_avalon_jtag_slave_translator" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 1624 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808673408 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_translator system:inst_cpu\|altera_merlin_slave_translator:rs232_wifi_avalon_rs232_slave_translator " "Elaborating entity \"altera_merlin_slave_translator\" for hierarchy \"system:inst_cpu\|altera_merlin_slave_translator:rs232_wifi_avalon_rs232_slave_translator\"" { } { { "system/synthesis/system.v" "rs232_wifi_avalon_rs232_slave_translator" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 1798 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808673408 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_master_agent system:inst_cpu\|altera_merlin_master_agent:cpu_instruction_master_translator_avalon_universal_master_0_agent " "Elaborating entity \"altera_merlin_master_agent\" for hierarchy \"system:inst_cpu\|altera_merlin_master_agent:cpu_instruction_master_translator_avalon_universal_master_0_agent\"" { } { { "system/synthesis/system.v" "cpu_instruction_master_translator_avalon_universal_master_0_agent" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 1870 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808673418 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_master_agent system:inst_cpu\|altera_merlin_master_agent:cpu_data_master_translator_avalon_universal_master_0_agent " "Elaborating entity \"altera_merlin_master_agent\" for hierarchy \"system:inst_cpu\|altera_merlin_master_agent:cpu_data_master_translator_avalon_universal_master_0_agent\"" { } { { "system/synthesis/system.v" "cpu_data_master_translator_avalon_universal_master_0_agent" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 1942 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808673418 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_agent system:inst_cpu\|altera_merlin_slave_agent:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent " "Elaborating entity \"altera_merlin_slave_agent\" for hierarchy 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"C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_slave_agent.sv" 476 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808673428 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_avalon_sc_fifo system:inst_cpu\|altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo " "Elaborating entity \"altera_avalon_sc_fifo\" for hierarchy \"system:inst_cpu\|altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo\"" { } { { "system/synthesis/system.v" "cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 2059 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808673428 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_agent system:inst_cpu\|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent " "Elaborating entity \"altera_merlin_slave_agent\" for hierarchy \"system:inst_cpu\|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent\"" { } { { "system/synthesis/system.v" "sdram_s1_translator_avalon_universal_slave_0_agent" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 2135 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808673438 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_burst_uncompressor system:inst_cpu\|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent\|altera_merlin_burst_uncompressor:uncompressor " "Elaborating entity \"altera_merlin_burst_uncompressor\" for hierarchy \"system:inst_cpu\|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent\|altera_merlin_burst_uncompressor:uncompressor\"" { } { { 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system:inst_cpu\|system_addr_router:addr_router " "Elaborating entity \"system_addr_router\" for hierarchy \"system:inst_cpu\|system_addr_router:addr_router\"" { } { { "system/synthesis/system.v" "addr_router" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 3362 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808673498 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_addr_router_default_decode system:inst_cpu\|system_addr_router:addr_router\|system_addr_router_default_decode:the_default_decode " "Elaborating entity \"system_addr_router_default_decode\" for hierarchy \"system:inst_cpu\|system_addr_router:addr_router\|system_addr_router_default_decode:the_default_decode\"" { } { { "system/synthesis/submodules/system_addr_router.sv" "the_default_decode" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_addr_router.sv" 140 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" 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system:inst_cpu\|system_id_router_001:id_router_001\|system_id_router_001_default_decode:the_default_decode " "Elaborating entity \"system_id_router_001_default_decode\" for hierarchy \"system:inst_cpu\|system_id_router_001:id_router_001\|system_id_router_001_default_decode:the_default_decode\"" { } { { "system/synthesis/submodules/system_id_router_001.sv" "the_default_decode" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_id_router_001.sv" 138 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808673508 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_id_router_002 system:inst_cpu\|system_id_router_002:id_router_002 " "Elaborating entity \"system_id_router_002\" for hierarchy \"system:inst_cpu\|system_id_router_002:id_router_002\"" { } { { "system/synthesis/system.v" "id_router_002" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 3426 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808673508 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_id_router_002_default_decode system:inst_cpu\|system_id_router_002:id_router_002\|system_id_router_002_default_decode:the_default_decode " "Elaborating entity \"system_id_router_002_default_decode\" for hierarchy \"system:inst_cpu\|system_id_router_002:id_router_002\|system_id_router_002_default_decode:the_default_decode\"" { } { { "system/synthesis/submodules/system_id_router_002.sv" "the_default_decode" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_id_router_002.sv" 138 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808673518 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_traffic_limiter system:inst_cpu\|altera_merlin_traffic_limiter:limiter " "Elaborating entity \"altera_merlin_traffic_limiter\" for hierarchy \"system:inst_cpu\|altera_merlin_traffic_limiter:limiter\"" { } { { "system/synthesis/system.v" "limiter" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 3615 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808673538 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_burst_adapter system:inst_cpu\|altera_merlin_burst_adapter:burst_adapter " "Elaborating entity \"altera_merlin_burst_adapter\" for hierarchy \"system:inst_cpu\|altera_merlin_burst_adapter:burst_adapter\"" { } { { "system/synthesis/system.v" "burst_adapter" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 3708 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808673538 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_burst_adapter_uncompressed_only system:inst_cpu\|altera_merlin_burst_adapter:burst_adapter\|altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba " "Elaborating entity \"altera_merlin_burst_adapter_uncompressed_only\" for hierarchy \"system:inst_cpu\|altera_merlin_burst_adapter:burst_adapter\|altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba\"" { } { { "system/synthesis/submodules/altera_merlin_burst_adapter.sv" "altera_merlin_burst_adapter_uncompressed_only.the_ba" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_burst_adapter.sv" 397 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808673538 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_reset_controller system:inst_cpu\|altera_reset_controller:rst_controller " "Elaborating entity \"altera_reset_controller\" for hierarchy \"system:inst_cpu\|altera_reset_controller:rst_controller\"" { } { { "system/synthesis/system.v" "rst_controller" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 3733 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808673548 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_reset_synchronizer system:inst_cpu\|altera_reset_controller:rst_controller\|altera_reset_synchronizer:alt_rst_sync_uq1 " "Elaborating entity \"altera_reset_synchronizer\" for hierarchy \"system:inst_cpu\|altera_reset_controller:rst_controller\|altera_reset_synchronizer:alt_rst_sync_uq1\"" { } { { "system/synthesis/submodules/altera_reset_controller.v" "alt_rst_sync_uq1" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_reset_controller.v" 105 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808673548 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cmd_xbar_demux system:inst_cpu\|system_cmd_xbar_demux:cmd_xbar_demux " "Elaborating entity \"system_cmd_xbar_demux\" for hierarchy \"system:inst_cpu\|system_cmd_xbar_demux:cmd_xbar_demux\"" { } { { "system/synthesis/system.v" "cmd_xbar_demux" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 3756 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808673548 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cmd_xbar_demux_001 system:inst_cpu\|system_cmd_xbar_demux_001:cmd_xbar_demux_001 " "Elaborating entity \"system_cmd_xbar_demux_001\" for hierarchy \"system:inst_cpu\|system_cmd_xbar_demux_001:cmd_xbar_demux_001\"" { } { { "system/synthesis/system.v" "cmd_xbar_demux_001" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 3839 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808673548 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cmd_xbar_mux system:inst_cpu\|system_cmd_xbar_mux:cmd_xbar_mux " "Elaborating entity \"system_cmd_xbar_mux\" for hierarchy \"system:inst_cpu\|system_cmd_xbar_mux:cmd_xbar_mux\"" { } { { "system/synthesis/system.v" "cmd_xbar_mux" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 3862 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808673558 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arbitrator system:inst_cpu\|system_cmd_xbar_mux:cmd_xbar_mux\|altera_merlin_arbitrator:arb " "Elaborating entity \"altera_merlin_arbitrator\" for hierarchy \"system:inst_cpu\|system_cmd_xbar_mux:cmd_xbar_mux\|altera_merlin_arbitrator:arb\"" { } { { "system/synthesis/submodules/system_cmd_xbar_mux.sv" "arb" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cmd_xbar_mux.sv" 273 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808673558 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arb_adder system:inst_cpu\|system_cmd_xbar_mux:cmd_xbar_mux\|altera_merlin_arbitrator:arb\|altera_merlin_arb_adder:adder " "Elaborating entity \"altera_merlin_arb_adder\" for hierarchy \"system:inst_cpu\|system_cmd_xbar_mux:cmd_xbar_mux\|altera_merlin_arbitrator:arb\|altera_merlin_arb_adder:adder\"" { } { { "system/synthesis/submodules/altera_merlin_arbitrator.sv" "adder" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_arbitrator.sv" 169 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808673558 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_rsp_xbar_demux system:inst_cpu\|system_rsp_xbar_demux:rsp_xbar_demux " "Elaborating entity \"system_rsp_xbar_demux\" for hierarchy \"system:inst_cpu\|system_rsp_xbar_demux:rsp_xbar_demux\"" { } { { "system/synthesis/system.v" "rsp_xbar_demux" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 3908 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808673568 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_rsp_xbar_demux_002 system:inst_cpu\|system_rsp_xbar_demux_002:rsp_xbar_demux_002 " "Elaborating entity \"system_rsp_xbar_demux_002\" for hierarchy \"system:inst_cpu\|system_rsp_xbar_demux_002:rsp_xbar_demux_002\"" { } { { "system/synthesis/system.v" "rsp_xbar_demux_002" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 3948 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808673568 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_rsp_xbar_mux system:inst_cpu\|system_rsp_xbar_mux:rsp_xbar_mux " "Elaborating entity \"system_rsp_xbar_mux\" for hierarchy \"system:inst_cpu\|system_rsp_xbar_mux:rsp_xbar_mux\"" { } { { "system/synthesis/system.v" "rsp_xbar_mux" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 4124 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808673578 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arbitrator system:inst_cpu\|system_rsp_xbar_mux:rsp_xbar_mux\|altera_merlin_arbitrator:arb " "Elaborating entity \"altera_merlin_arbitrator\" for hierarchy \"system:inst_cpu\|system_rsp_xbar_mux:rsp_xbar_mux\|altera_merlin_arbitrator:arb\"" { } { { "system/synthesis/submodules/system_rsp_xbar_mux.sv" "arb" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_rsp_xbar_mux.sv" 296 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808673578 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_rsp_xbar_mux_001 system:inst_cpu\|system_rsp_xbar_mux_001:rsp_xbar_mux_001 " "Elaborating entity \"system_rsp_xbar_mux_001\" for hierarchy \"system:inst_cpu\|system_rsp_xbar_mux_001:rsp_xbar_mux_001\"" { } { { "system/synthesis/system.v" "rsp_xbar_mux_001" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 4207 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808673588 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arbitrator system:inst_cpu\|system_rsp_xbar_mux_001:rsp_xbar_mux_001\|altera_merlin_arbitrator:arb " "Elaborating entity \"altera_merlin_arbitrator\" for hierarchy \"system:inst_cpu\|system_rsp_xbar_mux_001:rsp_xbar_mux_001\|altera_merlin_arbitrator:arb\"" { } { { "system/synthesis/submodules/system_rsp_xbar_mux_001.sv" "arb" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_rsp_xbar_mux_001.sv" 456 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808673588 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arb_adder system:inst_cpu\|system_rsp_xbar_mux_001:rsp_xbar_mux_001\|altera_merlin_arbitrator:arb\|altera_merlin_arb_adder:adder " "Elaborating entity \"altera_merlin_arb_adder\" for hierarchy \"system:inst_cpu\|system_rsp_xbar_mux_001:rsp_xbar_mux_001\|altera_merlin_arbitrator:arb\|altera_merlin_arb_adder:adder\"" { } { { "system/synthesis/submodules/altera_merlin_arbitrator.sv" "adder" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_arbitrator.sv" 169 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808673598 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_width_adapter system:inst_cpu\|altera_merlin_width_adapter:width_adapter " "Elaborating entity \"altera_merlin_width_adapter\" for hierarchy \"system:inst_cpu\|altera_merlin_width_adapter:width_adapter\"" { } { { "system/synthesis/system.v" "width_adapter" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 4264 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808673598 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_width_adapter system:inst_cpu\|altera_merlin_width_adapter:width_adapter_001 " "Elaborating entity \"altera_merlin_width_adapter\" for hierarchy \"system:inst_cpu\|altera_merlin_width_adapter:width_adapter_001\"" { } { { "system/synthesis/system.v" "width_adapter_001" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 4321 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808673598 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_irq_mapper system:inst_cpu\|system_irq_mapper:irq_mapper " "Elaborating entity \"system_irq_mapper\" for hierarchy \"system:inst_cpu\|system_irq_mapper:irq_mapper\"" { } { { "system/synthesis/system.v" "irq_mapper" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 4333 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393808673608 ""} -{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "address_b system_cpu_traceram_lpm_dram_bdp_component 17 7 " "Port \"address_b\" on the entity instantiation of \"system_cpu_traceram_lpm_dram_bdp_component\" is connected to a signal of width 17. The formal width of the signal in the module is 7. The extra bits will be ignored." { } { { "system/synthesis/submodules/system_cpu.v" "system_cpu_traceram_lpm_dram_bdp_component" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } } 0 12020 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. The extra bits will be ignored." 0 0 "" 0 -1 1393808675358 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component"} -{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "jdo the_system_cpu_nios2_oci_itrace 38 16 " "Port \"jdo\" on the entity instantiation of \"the_system_cpu_nios2_oci_itrace\" is connected to a signal of width 38. The formal width of the signal in the module is 16. The extra bits will be ignored." { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_nios2_oci_itrace" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3606 0 0 } } } 0 12020 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. The extra bits will be ignored." 0 0 "" 0 -1 1393808675358 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_itrace:the_system_cpu_nios2_oci_itrace"} -{ "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_HDR" "" "Synthesized away the following node(s):" { { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_SUB_HDR" "RAM " "Synthesized away the following RAM node(s):" { { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[0\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[0\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 43 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393808676572 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a0"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[1\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[1\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 77 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393808676572 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a1"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[2\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[2\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 111 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393808676572 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a2"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[3\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[3\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 145 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393808676572 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a3"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[4\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[4\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 179 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393808676572 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a4"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[5\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[5\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 213 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393808676572 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a5"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[6\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[6\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 247 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393808676572 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a6"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[7\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[7\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 281 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393808676572 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a7"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[8\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[8\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 315 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393808676572 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a8"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[9\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[9\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 349 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393808676572 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a9"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[10\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[10\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 383 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393808676572 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a10"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[11\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[11\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 417 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393808676572 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a11"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[12\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[12\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 451 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393808676572 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a12"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[13\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[13\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 485 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393808676572 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a13"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[14\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[14\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 519 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393808676572 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a14"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[15\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[15\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 553 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393808676572 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a15"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[16\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[16\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 587 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393808676572 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a16"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[17\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[17\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 621 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393808676572 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a17"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[18\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[18\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 655 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393808676572 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a18"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[19\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[19\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 689 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393808676572 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a19"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[20\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[20\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 723 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393808676572 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a20"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[21\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[21\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 757 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393808676572 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a21"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[22\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[22\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 791 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393808676572 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a22"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[23\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[23\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 825 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393808676572 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a23"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[24\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[24\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 859 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393808676572 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a24"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[25\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[25\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 893 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393808676572 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a25"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[26\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[26\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 927 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393808676572 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a26"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[27\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[27\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 961 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393808676572 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a27"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[28\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[28\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 995 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393808676572 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a28"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[29\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[29\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 1029 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393808676572 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a29"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[30\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[30\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 1063 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393808676572 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a30"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[31\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[31\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 1097 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393808676572 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a31"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[32\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[32\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 1131 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393808676572 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a32"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[33\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[33\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 1165 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393808676572 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a33"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[34\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[34\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 1199 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393808676572 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a34"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[35\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[35\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 1233 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393808676572 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a35"} } { } 0 14285 "Synthesized away the following %1!s! node(s):" 0 0 "" 0 -1 1393808676572 ""} } { } 0 14284 "Synthesized away the following node(s):" 0 0 "" 0 -1 1393808676572 ""} -{ "Info" "ILPMS_INFERENCING_SUMMARY" "1 " "Inferred 1 megafunctions from design logic" { { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "system:inst_cpu\|system_cpu:cpu\|Add17 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"system:inst_cpu\|system_cpu:cpu\|Add17\"" { } { { "system/synthesis/submodules/system_cpu.v" "Add17" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 8743 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1 1393808682194 ""} } { } 0 278001 "Inferred %1!llu! megafunctions from design logic" 0 0 "" 0 -1 1393808682194 ""} -{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_cpu:cpu\|lpm_add_sub:Add17 " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|lpm_add_sub:Add17\"" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 8743 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1393808682234 ""} -{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_cpu:cpu\|lpm_add_sub:Add17 " "Instantiated megafunction \"system:inst_cpu\|system_cpu:cpu\|lpm_add_sub:Add17\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 33 " "Parameter \"LPM_WIDTH\" = \"33\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808682234 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION DEFAULT " "Parameter \"LPM_DIRECTION\" = \"DEFAULT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808682234 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808682234 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT NO " "Parameter \"ONE_INPUT_IS_CONSTANT\" = \"NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393808682234 ""} } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 8743 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1393808682234 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_qvi.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/add_sub_qvi.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_qvi " "Found entity 1: add_sub_qvi" { } { { "db/add_sub_qvi.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/add_sub_qvi.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393808682314 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393808682314 ""} -{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "2 " "2 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "" 0 -1 1393808683304 ""} -{ "Warning" "WMLS_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC_HDR" "" "The following nodes have both tri-state and non-tri-state drivers" { { "Warning" "WMLS_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC" "GPIO_0\[33\] " "Inserted always-enabled tri-state buffer between \"GPIO_0\[33\]\" and its non-tri-state driver." { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13035 "Inserted always-enabled tri-state buffer between \"%1!s!\" and its non-tri-state driver." 0 0 "" 0 -1 1393808683494 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC" "GPIO_1\[0\] " "Inserted always-enabled tri-state buffer between \"GPIO_1\[0\]\" and its non-tri-state driver." { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13035 "Inserted always-enabled tri-state buffer between \"%1!s!\" and its non-tri-state driver." 0 0 "" 0 -1 1393808683494 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC" "GPIO_1\[33\] " "Inserted always-enabled tri-state buffer between \"GPIO_1\[33\]\" and its non-tri-state driver." { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13035 "Inserted always-enabled tri-state buffer between \"%1!s!\" and its non-tri-state driver." 0 0 "" 0 -1 1393808683494 ""} } { } 0 13034 "The following nodes have both tri-state and non-tri-state drivers" 0 0 "" 0 -1 1393808683494 ""} -{ "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI_HDR" "" "The following bidir pins have no drivers" { { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[0\] " "Bidir \"GPIO_0\[0\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393808683494 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[1\] " "Bidir \"GPIO_0\[1\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393808683494 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[2\] " "Bidir \"GPIO_0\[2\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393808683494 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[3\] " "Bidir \"GPIO_0\[3\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393808683494 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[4\] " "Bidir \"GPIO_0\[4\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393808683494 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[5\] " "Bidir \"GPIO_0\[5\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393808683494 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[6\] " "Bidir \"GPIO_0\[6\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393808683494 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[7\] " "Bidir \"GPIO_0\[7\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393808683494 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[8\] " "Bidir \"GPIO_0\[8\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393808683494 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[9\] " "Bidir \"GPIO_0\[9\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393808683494 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[10\] " "Bidir \"GPIO_0\[10\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393808683494 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[11\] " "Bidir \"GPIO_0\[11\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393808683494 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[12\] " "Bidir \"GPIO_0\[12\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393808683494 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[13\] " "Bidir \"GPIO_0\[13\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393808683494 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[14\] " "Bidir \"GPIO_0\[14\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393808683494 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[15\] " "Bidir \"GPIO_0\[15\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393808683494 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[16\] " "Bidir \"GPIO_0\[16\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393808683494 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[17\] " "Bidir \"GPIO_0\[17\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393808683494 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[18\] " "Bidir \"GPIO_0\[18\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393808683494 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[19\] " "Bidir \"GPIO_0\[19\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393808683494 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[20\] " "Bidir \"GPIO_0\[20\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393808683494 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[21\] " "Bidir \"GPIO_0\[21\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393808683494 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[22\] " "Bidir \"GPIO_0\[22\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393808683494 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[23\] " "Bidir \"GPIO_0\[23\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393808683494 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[24\] " "Bidir \"GPIO_0\[24\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393808683494 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[25\] " "Bidir \"GPIO_0\[25\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393808683494 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[26\] " "Bidir \"GPIO_0\[26\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393808683494 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[27\] " "Bidir \"GPIO_0\[27\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393808683494 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[28\] " "Bidir \"GPIO_0\[28\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393808683494 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[29\] " "Bidir \"GPIO_0\[29\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393808683494 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[30\] " "Bidir \"GPIO_0\[30\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393808683494 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[32\] " "Bidir \"GPIO_0\[32\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393808683494 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[1\] " "Bidir \"GPIO_1\[1\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393808683494 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[2\] " "Bidir \"GPIO_1\[2\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393808683494 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[3\] " "Bidir \"GPIO_1\[3\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393808683494 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[4\] " "Bidir \"GPIO_1\[4\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393808683494 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[5\] " "Bidir \"GPIO_1\[5\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393808683494 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[6\] " "Bidir \"GPIO_1\[6\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393808683494 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[7\] " "Bidir \"GPIO_1\[7\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393808683494 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[8\] " "Bidir \"GPIO_1\[8\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393808683494 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[9\] " "Bidir \"GPIO_1\[9\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393808683494 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[10\] " "Bidir \"GPIO_1\[10\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393808683494 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[11\] " "Bidir \"GPIO_1\[11\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393808683494 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[12\] " "Bidir \"GPIO_1\[12\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393808683494 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[13\] " "Bidir \"GPIO_1\[13\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393808683494 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[14\] " "Bidir \"GPIO_1\[14\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393808683494 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[15\] " "Bidir \"GPIO_1\[15\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393808683494 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[16\] " "Bidir \"GPIO_1\[16\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393808683494 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[17\] " "Bidir \"GPIO_1\[17\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393808683494 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[18\] " "Bidir \"GPIO_1\[18\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393808683494 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[19\] " "Bidir \"GPIO_1\[19\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393808683494 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[20\] " "Bidir \"GPIO_1\[20\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393808683494 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[21\] " "Bidir \"GPIO_1\[21\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393808683494 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[22\] " "Bidir \"GPIO_1\[22\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393808683494 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[23\] " "Bidir \"GPIO_1\[23\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393808683494 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[24\] " "Bidir \"GPIO_1\[24\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393808683494 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[25\] " "Bidir \"GPIO_1\[25\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393808683494 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[26\] " "Bidir \"GPIO_1\[26\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393808683494 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[27\] " "Bidir \"GPIO_1\[27\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393808683494 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[28\] " "Bidir \"GPIO_1\[28\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393808683494 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[29\] " "Bidir \"GPIO_1\[29\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393808683494 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[30\] " "Bidir \"GPIO_1\[30\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393808683494 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[32\] " "Bidir \"GPIO_1\[32\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393808683494 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[31\] " "Bidir \"GPIO_0\[31\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393808683494 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[31\] " "Bidir \"GPIO_1\[31\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393808683494 ""} } { } 0 13039 "The following bidir pins have no drivers" 0 0 "" 0 -1 1393808683494 ""} -{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" { } { { "system/synthesis/submodules/system_sdram.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_sdram.v" 440 -1 0 } } { "system/synthesis/submodules/system_sdram.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_sdram.v" 354 -1 0 } } { "system/synthesis/submodules/altera_reset_synchronizer.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_reset_synchronizer.v" 62 -1 0 } } { "system/synthesis/submodules/system_sdram.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_sdram.v" 304 -1 0 } } { "system/synthesis/submodules/altera_merlin_slave_translator.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_slave_translator.sv" 277 -1 0 } } { "system/synthesis/submodules/system_jtag_uart_0.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_jtag_uart_0.v" 558 -1 0 } } { "alt_jtag_atlantic.v" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/alt_jtag_atlantic.v" 291 -1 0 } } { "system/synthesis/submodules/system_uart_mc.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_mc.v" 89 -1 0 } } { "system/synthesis/submodules/altera_merlin_arbitrator.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_arbitrator.sv" 203 -1 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 5563 -1 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 5963 -1 0 } } { "system/synthesis/submodules/system_jtag_uart_0.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_jtag_uart_0.v" 603 -1 0 } } { "system/synthesis/submodules/system_uart_mc.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_mc.v" 105 -1 0 } } { "alt_jtag_atlantic.v" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/alt_jtag_atlantic.v" 224 -1 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 5995 -1 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 9343 -1 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 9492 -1 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 982 -1 0 } } { "system/synthesis/submodules/system_uart_mc.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_mc.v" 87 -1 0 } } { "system/synthesis/submodules/system_uart_wifi.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_wifi.v" 88 -1 0 } } { "system/synthesis/submodules/system_uart_wifi.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_wifi.v" 87 -1 0 } } { "system/synthesis/submodules/system_uart_mc.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_mc.v" 88 -1 0 } } { "system/synthesis/submodules/system_sys_clk_timer.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_sys_clk_timer.v" 166 -1 0 } } { "system/synthesis/submodules/system_sys_clk_timer.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_sys_clk_timer.v" 175 -1 0 } } { "system/synthesis/submodules/system_uart_wifi.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_wifi.v" 891 -1 0 } } } 0 13000 "Registers with preset signals will power-up high" 0 0 "" 0 -1 1393808683674 ""} -{ "Info" "IMLS_MLS_DEV_CLRN_SETS_REGISTERS" "" "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" { } { } 0 13003 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "" 0 -1 1393808683674 ""} -{ "Warning" "WMLS_MLS_ENABLED_OE" "" "TRI or OPNDRN buffers permanently enabled" { { "Warning" "WMLS_MLS_NODE_NAME" "GPIO_0\[33\]~synth " "Node \"GPIO_0\[33\]~synth\"" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13010 "Node \"%1!s!\"" 0 0 "" 0 -1 1393808685914 ""} { "Warning" "WMLS_MLS_NODE_NAME" "GPIO_1\[0\]~synth " "Node \"GPIO_1\[0\]~synth\"" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13010 "Node \"%1!s!\"" 0 0 "" 0 -1 1393808685914 ""} { "Warning" "WMLS_MLS_NODE_NAME" "GPIO_1\[33\]~synth " "Node \"GPIO_1\[33\]~synth\"" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13010 "Node \"%1!s!\"" 0 0 "" 0 -1 1393808685914 ""} } { } 0 13009 "TRI or OPNDRN buffers permanently enabled" 0 0 "" 0 -1 1393808685914 ""} -{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "DRAM_CKE VCC " "Pin \"DRAM_CKE\" is stuck at VCC" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 62 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1 1393808685914 "|de0_nano_system|DRAM_CKE"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "" 0 -1 1393808685914 ""} -{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING_ON_PARTITION" "Top " "Timing-Driven Synthesis is running on partition \"Top\"" { } { } 0 286031 "Timing-Driven Synthesis is running on partition \"%1!s!\"" 0 0 "" 0 -1 1393808686564 ""} -{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "378 " "378 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "" 0 -1 1393808689534 ""} -{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "1 0 1 0 0 " "Adding 1 node(s), including 0 DDIO, 1 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "" 0 -1 1393808690964 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "" 0 -1 1393808690964 ""} -{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "1 " "Design contains 1 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[0\] " "No output dependent on input pin \"KEY\[0\]\"" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 74 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1 1393808691624 "|de0_nano_system|KEY[0]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0 -1 1393808691624 ""} -{ "Info" "ICUT_CUT_TM_SUMMARY" "5737 " "Implemented 5737 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "10 " "Implemented 10 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "" 0 -1 1393808691634 ""} { "Info" "ICUT_CUT_TM_OPINS" "32 " "Implemented 32 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "" 0 -1 1393808691634 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "84 " "Implemented 84 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "" 0 -1 1393808691634 ""} { "Info" "ICUT_CUT_TM_LCELLS" "5342 " "Implemented 5342 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "" 0 -1 1393808691634 ""} { "Info" "ICUT_CUT_TM_RAMS" "263 " "Implemented 263 RAM segments" { } { } 0 21064 "Implemented %1!d! RAM segments" 0 0 "" 0 -1 1393808691634 ""} { "Info" "ICUT_CUT_TM_PLLS" "1 " "Implemented 1 PLLs" { } { } 0 21065 "Implemented %1!d! PLLs" 0 0 "" 0 -1 1393808691634 ""} { "Info" "ICUT_CUT_TM_DSP_ELEM" "4 " "Implemented 4 DSP elements" { } { } 0 21062 "Implemented %1!d! DSP elements" 0 0 "" 0 -1 1393808691634 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1 1393808691634 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 130 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 130 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "644 " "Peak virtual memory: 644 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1 1393808691764 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Mar 02 18:04:51 2014 " "Processing ended: Sun Mar 02 18:04:51 2014" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1 1393808691764 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:24 " "Elapsed time: 00:00:24" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1 1393808691764 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:23 " "Total CPU time (on all processors): 00:00:23" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1 1393808691764 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1 1393808691764 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1 1393808693104 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 64-Bit " "Running Quartus II 64-Bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Full Version " "Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1 1393808693104 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Mar 02 18:04:52 2014 " "Processing started: Sun Mar 02 18:04:52 2014" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1 1393808693104 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1 1393808693104 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off de0_nano_system -c de0_nano_system " "Command: quartus_fit --read_settings_files=off --write_settings_files=off de0_nano_system -c de0_nano_system" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1 1393808693104 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." { } { } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "" 0 -1 1393808693264 ""} -{ "Info" "IMPP_MPP_USER_DEVICE" "de0_nano_system EP4CE22F17C6 " "Selected device EP4CE22F17C6 for design \"de0_nano_system\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 -1 1393808693554 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "" 0 -1 1393808693604 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "" 0 -1 1393808693604 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "" 0 -1 1393808693604 ""} -{ "Info" "ICUT_CUT_PLL_COMPUTATION_SUCCESS" "pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|pll1 Cyclone IV E PLL " "Implemented PLL \"pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|pll1\" as Cyclone IV E PLL type" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|wire_pll1_clk\[0\] 2 1 0 0 " "Implementing clock multiplication of 2, clock division of 1, and phase shift of 0 degrees (0 ps) for pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|wire_pll1_clk\[0\] port" { } { { "db/pll_sys_altpll.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/pll_sys_altpll.v" 45 -1 0 } } { "" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 6290 8336 9085 0} } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "" 0 -1 1393808693654 ""} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|wire_pll1_clk\[1\] 2 1 -54 -1500 " "Implementing clock multiplication of 2, clock division of 1, and phase shift of -54 degrees (-1500 ps) for pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|wire_pll1_clk\[1\] port" { } { { "db/pll_sys_altpll.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/pll_sys_altpll.v" 45 -1 0 } } { "" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 6291 8336 9085 0} } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "" 0 -1 1393808693654 ""} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|wire_pll1_clk\[2\] 1 5 0 0 " "Implementing clock multiplication of 1, clock division of 5, and phase shift of 0 degrees (0 ps) for pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|wire_pll1_clk\[2\] port" { } { { "db/pll_sys_altpll.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/pll_sys_altpll.v" 45 -1 0 } } { "" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 6292 8336 9085 0} } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "" 0 -1 1393808693654 ""} } { { "db/pll_sys_altpll.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/pll_sys_altpll.v" 45 -1 0 } } { "" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 6290 8336 9085 0} } } } } 0 15535 "Implemented %3!s! \"%1!s!\" as %2!s! PLL type" 0 0 "" 0 -1 1393808693654 ""} -{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0 -1 1393808693864 ""} -{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE10F17C6 " "Device EP4CE10F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "" 0 -1 1393808694154 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE6F17C6 " "Device EP4CE6F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "" 0 -1 1393808694154 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE15F17C6 " "Device EP4CE15F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "" 0 -1 1393808694154 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 -1 1393808694154 ""} -{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ C1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location C1" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 16681 8336 9085 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1 1393808694164 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ D2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location D2" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 16683 8336 9085 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1 1393808694164 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ H1 " "Pin ~ALTERA_DCLK~ is reserved at location H1" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 16685 8336 9085 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1 1393808694164 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ H2 " "Pin ~ALTERA_DATA0~ is reserved at location H2" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 16687 8336 9085 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1 1393808694164 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ F16 " "Pin ~ALTERA_nCEO~ is reserved at location F16" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 16689 8336 9085 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1 1393808694164 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 -1 1393808694164 ""} -{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "" 0 -1 1393808694174 ""} -{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." { } { } 0 176045 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "" 0 -1 1393808694224 ""} -{ "Info" "ISTA_SDC_STATEMENT_PARENT" "" "Evaluating HDL-embedded SDC commands" { { "Info" "ISTA_SDC_STATEMENT_ENTITY" "alt_jtag_atlantic " "Entity alt_jtag_atlantic" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate1*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate1*\}\] " { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393808695914 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393808695914 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393808695914 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393808695914 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393808695914 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393808695914 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393808695914 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393808695914 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393808695914 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|read1*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|read1*\}\] " { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393808695914 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read_req\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read_req\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393808695914 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393808695914 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|tck_t_dav\}\] " "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|tck_t_dav\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393808695914 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|user_saw_rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid0*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|user_saw_rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid0*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393808695914 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393808695914 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393808695914 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393808695914 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393808695914 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393808695914 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393808695914 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393808695914 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393808695914 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write1*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write1*\}\] " { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393808695914 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_ena*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_ena*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393808695914 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_pause*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_pause*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393808695914 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_valid\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_valid\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393808695914 ""} } { } 0 332165 "Entity %1!s!" 0 0 "" 0 -1 1393808695914 ""} { "Info" "ISTA_SDC_STATEMENT_ENTITY" "altera_std_synchronizer " "Entity altera_std_synchronizer" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -to \[get_keepers \{*altera_std_synchronizer:*\|din_s1\}\] " "set_false_path -to \[get_keepers \{*altera_std_synchronizer:*\|din_s1\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393808695914 ""} } { } 0 332165 "Entity %1!s!" 0 0 "" 0 -1 1393808695914 ""} { "Info" "ISTA_SDC_STATEMENT_ENTITY" "sld_jtag_hub " "Entity sld_jtag_hub" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "create_clock -period 10MHz -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] " "create_clock -period 10MHz -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393808695914 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_clock_groups -asynchronous -group \{altera_reserved_tck\} " "set_clock_groups -asynchronous -group \{altera_reserved_tck\}" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393808695914 ""} } { } 0 332165 "Entity %1!s!" 0 0 "" 0 -1 1393808695914 ""} } { } 0 332164 "Evaluating HDL-embedded SDC commands" 0 0 "" 0 -1 1393808695914 ""} -{ "Info" "ISTA_SDC_FOUND" "de0_nano_system.sdc " "Reading SDC File: 'de0_nano_system.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "" 0 -1 1393808696204 ""} -{ "Warning" "WSTA_OVERWRITING_EXISTING_CLOCK" "altera_reserved_tck " "Overwriting existing clock: altera_reserved_tck" { } { } 0 332043 "Overwriting existing clock: %1!s!" 0 0 "" 0 -1 1393808696224 ""} -{ "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "Deriving PLL clocks " "Deriving PLL clocks" { { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -duty_cycle 50.00 -name \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} " "create_generated_clock -source \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -duty_cycle 50.00 -name \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}" { } { } 0 332110 "%1!s!" 0 0 "" 0 -1 1393808696224 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -phase -54.00 -duty_cycle 50.00 -name \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} " "create_generated_clock -source \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -phase -54.00 -duty_cycle 50.00 -name \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}" { } { } 0 332110 "%1!s!" 0 0 "" 0 -1 1393808696224 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 5 -duty_cycle 50.00 -name \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} " "create_generated_clock -source \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 5 -duty_cycle 50.00 -name \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\]\}" { } { } 0 332110 "%1!s!" 0 0 "" 0 -1 1393808696224 ""} } { } 0 332110 "%1!s!" 0 0 "" 0 -1 1393808696224 ""} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_CALL_IS_DELAYED" "" "Clock uncertainty is not calculated until you update the timing netlist." { } { } 0 332151 "Clock uncertainty is not calculated until you update the timing netlist." 0 0 "" 0 -1 1393808696224 ""} -{ "Info" "ISTA_SDC_FOUND" "system/synthesis/submodules/altera_reset_controller.sdc " "Reading SDC File: 'system/synthesis/submodules/altera_reset_controller.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "" 0 -1 1393808696234 ""} -{ "Info" "ISTA_SDC_FOUND" "system/synthesis/submodules/system_cpu.sdc " "Reading SDC File: 'system/synthesis/submodules/system_cpu.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "" 0 -1 1393808696264 ""} -{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "" 0 -1 1393808696454 ""} -{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "" 0 -1 1393808696454 ""} -{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 5 clocks " "Found 5 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "" 0 -1 1393808696454 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "" 0 -1 1393808696454 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 100.000 altera_reserved_tck " " 100.000 altera_reserved_tck" { } { } 0 332111 "%1!s!" 0 0 "" 0 -1 1393808696454 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 20.000 CLOCK_50 " " 20.000 CLOCK_50" { } { } 0 332111 "%1!s!" 0 0 "" 0 -1 1393808696454 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 10.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 10.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\]" { } { } 0 332111 "%1!s!" 0 0 "" 0 -1 1393808696454 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 10.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 10.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[1\]" { } { } 0 332111 "%1!s!" 0 0 "" 0 -1 1393808696454 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 100.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 100.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\]" { } { } 0 332111 "%1!s!" 0 0 "" 0 -1 1393808696454 ""} } { } 0 332111 "%1!s!" 0 0 "" 0 -1 1393808696454 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C0 of PLL_4) " "Automatically promoted node pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C0 of PLL_4)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G18 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G18" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1 1393808696954 ""} } { { "db/pll_sys_altpll.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/pll_sys_altpll.v" 80 -1 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { pll_sys:inst_pll_sys|altpll:altpll_component|pll_sys_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 6290 8336 9085 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1 1393808696954 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|wire_pll1_clk\[1\] (placed in counter C2 of PLL_4) " "Automatically promoted node pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|wire_pll1_clk\[1\] (placed in counter C2 of PLL_4)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G17 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G17" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1 1393808696954 ""} } { { "db/pll_sys_altpll.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/pll_sys_altpll.v" 80 -1 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { pll_sys:inst_pll_sys|altpll:altpll_component|pll_sys_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 6290 8336 9085 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1 1393808696954 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|wire_pll1_clk\[2\] (placed in counter C1 of PLL_4) " "Automatically promoted node pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|wire_pll1_clk\[2\] (placed in counter C1 of PLL_4)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G19 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G19" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1 1393808696954 ""} } { { "db/pll_sys_altpll.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/pll_sys_altpll.v" 80 -1 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { pll_sys:inst_pll_sys|altpll:altpll_component|pll_sys_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 6290 8336 9085 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1 1393808696954 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "altera_internal_jtag~TCKUTAP " "Automatically promoted node altera_internal_jtag~TCKUTAP " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1 1393808696954 ""} } { { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 16160 8336 9085 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1 1393808696954 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "system:inst_cpu\|altera_reset_controller:rst_controller\|altera_reset_synchronizer:alt_rst_sync_uq1\|altera_reset_synchronizer_int_chain_out " "Automatically promoted node system:inst_cpu\|altera_reset_controller:rst_controller\|altera_reset_synchronizer:alt_rst_sync_uq1\|altera_reset_synchronizer_int_chain_out " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1 1393808696954 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr\|counter_reg_bit\[6\] " "Destination node system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr\|counter_reg_bit\[6\]" { } { { "db/cntr_0ab.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/cntr_0ab.tdf" 68 17 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 6531 8336 9085 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "" 0 -1 1393808696954 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr\|counter_reg_bit\[5\] " "Destination node system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr\|counter_reg_bit\[5\]" { } { { "db/cntr_0ab.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/cntr_0ab.tdf" 68 17 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 6532 8336 9085 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "" 0 -1 1393808696954 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr\|counter_reg_bit\[4\] " "Destination node system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr\|counter_reg_bit\[4\]" { } { { "db/cntr_0ab.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/cntr_0ab.tdf" 68 17 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 6533 8336 9085 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "" 0 -1 1393808696954 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr\|counter_reg_bit\[3\] " "Destination node system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr\|counter_reg_bit\[3\]" { } { { "db/cntr_0ab.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/cntr_0ab.tdf" 68 17 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 6534 8336 9085 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "" 0 -1 1393808696954 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr\|counter_reg_bit\[2\] " "Destination node system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr\|counter_reg_bit\[2\]" { } { { "db/cntr_0ab.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/cntr_0ab.tdf" 68 17 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 6535 8336 9085 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "" 0 -1 1393808696954 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr\|counter_reg_bit\[1\] " "Destination node system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr\|counter_reg_bit\[1\]" { } { { "db/cntr_0ab.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/cntr_0ab.tdf" 68 17 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 6536 8336 9085 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "" 0 -1 1393808696954 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr\|counter_reg_bit\[0\] " "Destination node system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr\|counter_reg_bit\[0\]" { } { { "db/cntr_0ab.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/cntr_0ab.tdf" 68 17 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 6537 8336 9085 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "" 0 -1 1393808696954 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_ca7:usedw_counter\|counter_reg_bit\[6\] " "Destination node system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_ca7:usedw_counter\|counter_reg_bit\[6\]" { } { { "db/cntr_ca7.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/cntr_ca7.tdf" 69 17 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_ca7:usedw_counter|counter_reg_bit[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 6554 8336 9085 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "" 0 -1 1393808696954 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_ca7:usedw_counter\|counter_reg_bit\[5\] " "Destination node system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_ca7:usedw_counter\|counter_reg_bit\[5\]" { } { { "db/cntr_ca7.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/cntr_ca7.tdf" 69 17 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_ca7:usedw_counter|counter_reg_bit[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 6555 8336 9085 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "" 0 -1 1393808696954 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_ca7:usedw_counter\|counter_reg_bit\[4\] " "Destination node system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_ca7:usedw_counter\|counter_reg_bit\[4\]" { } { { "db/cntr_ca7.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/cntr_ca7.tdf" 69 17 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_ca7:usedw_counter|counter_reg_bit[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 6556 8336 9085 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "" 0 -1 1393808696954 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_LIMITED_TO_SUB" "10 " "Non-global destination nodes limited to 10 nodes" { } { } 0 176358 "Non-global destination nodes limited to %1!d! nodes" 0 0 "" 0 -1 1393808696954 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0 -1 1393808696954 ""} } { { "system/synthesis/submodules/altera_reset_synchronizer.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_reset_synchronizer.v" 62 -1 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 695 8336 9085 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1 1393808696954 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "sld_hub:auto_hub\|sld_jtag_hub:\\jtag_hub_gen:sld_jtag_hub_inst\|clr_reg " "Automatically promoted node sld_hub:auto_hub\|sld_jtag_hub:\\jtag_hub_gen:sld_jtag_hub_inst\|clr_reg " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1 1393808696954 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "sld_hub:auto_hub\|sld_jtag_hub:\\jtag_hub_gen:sld_jtag_hub_inst\|clr_reg~_wirecell " "Destination node sld_hub:auto_hub\|sld_jtag_hub:\\jtag_hub_gen:sld_jtag_hub_inst\|clr_reg~_wirecell" { } { { "sld_jtag_hub.vhd" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/sld_jtag_hub.vhd" 335 -1 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg~_wirecell } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 16541 8336 9085 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "" 0 -1 1393808696954 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0 -1 1393808696954 ""} } { { "sld_jtag_hub.vhd" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/sld_jtag_hub.vhd" 335 -1 0 } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "sld_hub:auto_hub\|sld_jtag_hub:\\jtag_hub_gen:sld_jtag_hub_inst\|clr_reg" } } } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 16291 8336 9085 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1 1393808696954 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "sld_hub:auto_hub\|sld_jtag_hub:\\jtag_hub_gen:sld_jtag_hub_inst\|sld_shadow_jsm:shadow_jsm\|state\[0\] " "Automatically promoted node sld_hub:auto_hub\|sld_jtag_hub:\\jtag_hub_gen:sld_jtag_hub_inst\|sld_shadow_jsm:shadow_jsm\|state\[0\] " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1 1393808696954 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "sld_hub:auto_hub\|sld_jtag_hub:\\jtag_hub_gen:sld_jtag_hub_inst\|sld_shadow_jsm:shadow_jsm\|state~0 " "Destination node sld_hub:auto_hub\|sld_jtag_hub:\\jtag_hub_gen:sld_jtag_hub_inst\|sld_shadow_jsm:shadow_jsm\|state~0" { } { { "sld_jtag_hub.vhd" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/sld_jtag_hub.vhd" 1076 -1 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 16425 8336 9085 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "" 0 -1 1393808696954 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "sld_hub:auto_hub\|sld_jtag_hub:\\jtag_hub_gen:sld_jtag_hub_inst\|sld_shadow_jsm:shadow_jsm\|state~1 " "Destination node sld_hub:auto_hub\|sld_jtag_hub:\\jtag_hub_gen:sld_jtag_hub_inst\|sld_shadow_jsm:shadow_jsm\|state~1" { } { { "sld_jtag_hub.vhd" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/sld_jtag_hub.vhd" 1076 -1 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state~1 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 16426 8336 9085 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "" 0 -1 1393808696954 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "sld_hub:auto_hub\|sld_jtag_hub:\\jtag_hub_gen:sld_jtag_hub_inst\|sld_shadow_jsm:shadow_jsm\|state\[0\]~_wirecell " "Destination node sld_hub:auto_hub\|sld_jtag_hub:\\jtag_hub_gen:sld_jtag_hub_inst\|sld_shadow_jsm:shadow_jsm\|state\[0\]~_wirecell" { } { { "sld_jtag_hub.vhd" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/sld_jtag_hub.vhd" 1090 -1 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0]~_wirecell } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 16542 8336 9085 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "" 0 -1 1393808696954 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0 -1 1393808696954 ""} } { { "sld_jtag_hub.vhd" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/sld_jtag_hub.vhd" 1090 -1 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 16184 8336 9085 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1 1393808696954 ""} -{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "system:inst_cpu\|altera_reset_controller:rst_controller\|merged_reset~0 " "Automatically promoted node system:inst_cpu\|altera_reset_controller:rst_controller\|merged_reset~0 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1 1393808696954 ""} } { { "system/synthesis/submodules/altera_reset_controller.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_reset_controller.v" 61 -1 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { system:inst_cpu|altera_reset_controller:rst_controller|merged_reset~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 7557 8336 9085 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1 1393808696954 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "" 0 -1 1393808698484 ""} -{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1 1393808698494 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1 1393808698494 ""} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "" 0 -1 1393808698514 ""} -{ "Warning" "WFSAC_FSAC_IGNORED_FAST_REGISTER_IO_ASSIGNMENTS" "" "Ignoring invalid fast I/O register assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 176250 "Ignoring invalid fast I/O register assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "" 0 -1 1393808701254 ""} -{ "Warning" "WFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS" "" "Ignoring some wildcard destinations of fast I/O register assignments" { { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Enable Register ON oe " "Wildcard assignment \"Fast Output Enable Register=ON\" to \"oe\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1393808701254 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[9\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[9\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1393808701254 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[8\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[8\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1393808701254 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[7\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[7\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1393808701254 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[6\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[6\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1393808701254 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[5\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[5\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1393808701254 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[4\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[4\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1393808701254 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[3\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[3\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1393808701254 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[2\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[2\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1393808701254 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[1\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[1\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1393808701254 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[15\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[15\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1393808701254 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[14\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[14\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1393808701254 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[13\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[13\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1393808701254 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[12\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[12\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1393808701254 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[11\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[11\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1393808701254 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[10\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[10\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1393808701254 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[0\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[0\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1393808701254 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_cmd\[2\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_cmd\[2\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1393808701254 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_cmd\[1\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_cmd\[1\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1393808701254 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_cmd\[0\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_cmd\[0\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1393808701254 ""} } { } 0 176251 "Ignoring some wildcard destinations of fast I/O register assignments" 0 0 "" 0 -1 1393808701254 ""} -{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "" 0 -1 1393808701254 ""} -{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "" 0 -1 1393808701274 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "" 0 -1 1393808702974 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NUM_REGISTERS_PACKED_INTO_ATOM_TYPE" "10 EC " "Packed 10 registers into blocks of type EC" { } { } 1 176218 "Packed %1!d! registers into blocks of type %2!s!" 0 0 "" 0 -1 1393808704534 ""} { "Extra Info" "IFSAC_NUM_REGISTERS_PACKED_INTO_ATOM_TYPE" "64 Embedded multiplier block " "Packed 64 registers into blocks of type Embedded multiplier block" { } { } 1 176218 "Packed %1!d! registers into blocks of type %2!s!" 0 0 "" 0 -1 1393808704534 ""} { "Extra Info" "IFSAC_NUM_REGISTERS_PACKED_INTO_ATOM_TYPE" "16 I/O Input Buffer " "Packed 16 registers into blocks of type I/O Input Buffer" { } { } 1 176218 "Packed %1!d! registers into blocks of type %2!s!" 0 0 "" 0 -1 1393808704534 ""} { "Extra Info" "IFSAC_NUM_REGISTERS_PACKED_INTO_ATOM_TYPE" "53 I/O Output Buffer " "Packed 53 registers into blocks of type I/O Output Buffer" { } { } 1 176218 "Packed %1!d! registers into blocks of type %2!s!" 0 0 "" 0 -1 1393808704534 ""} { "Extra Info" "IFSAC_NUM_REGISTERS_DUPLICATED" "66 " "Created 66 register duplicates" { } { } 1 176220 "Created %1!d! register duplicates" 0 0 "" 0 -1 1393808704534 ""} } { } 0 176235 "Finished register packing" 0 0 "" 0 -1 1393808704534 ""} -{ "Warning" "WCUT_PLL_CLK_FEEDS_NON_DEDICATED_IO" "pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|pll1 clk\[1\] DRAM_CLK~output " "PLL \"pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|pll1\" output port clk\[1\] feeds output pin \"DRAM_CLK~output\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" { } { { "db/pll_sys_altpll.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/pll_sys_altpll.v" 45 -1 0 } } { "altpll.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altpll.tdf" 897 0 0 } } { "pll_sys.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/pll_sys.vhd" 154 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 152 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 61 0 0 } } } 0 15064 "PLL \"%1!s!\" output port %2!s! feeds output pin \"%3!s!\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" 0 0 "" 0 -1 1393808704694 ""} -{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_CS_N " "Node \"ADC_CS_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393808704834 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SADDR " "Node \"ADC_SADDR\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SADDR" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393808704834 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SCLK " "Node \"ADC_SCLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393808704834 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDAT " "Node \"ADC_SDAT\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393808704834 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0_IN\[0\] " "Node \"GPIO_0_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393808704834 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0_IN\[1\] " "Node \"GPIO_0_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393808704834 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1_IN\[0\] " "Node \"GPIO_1_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393808704834 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1_IN\[1\] " "Node \"GPIO_1_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393808704834 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[0\] " "Node \"GPIO_2\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393808704834 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[10\] " "Node \"GPIO_2\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393808704834 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[11\] " "Node \"GPIO_2\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393808704834 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[12\] " "Node \"GPIO_2\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393808704834 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[1\] " "Node \"GPIO_2\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393808704834 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[2\] " "Node \"GPIO_2\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393808704834 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[3\] " "Node \"GPIO_2\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393808704834 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[4\] " "Node \"GPIO_2\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393808704834 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[5\] " "Node \"GPIO_2\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393808704834 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[6\] " "Node \"GPIO_2\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393808704834 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[7\] " "Node \"GPIO_2\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393808704834 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[8\] " "Node \"GPIO_2\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393808704834 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[9\] " "Node \"GPIO_2\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393808704834 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[0\] " "Node \"GPIO_2_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393808704834 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[1\] " "Node \"GPIO_2_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393808704834 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[2\] " "Node \"GPIO_2_IN\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393808704834 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "G_SENSOR_CS_N " "Node \"G_SENSOR_CS_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "G_SENSOR_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393808704834 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "G_SENSOR_INT " "Node \"G_SENSOR_INT\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "G_SENSOR_INT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393808704834 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SCLK " "Node \"I2C_SCLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "I2C_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393808704834 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SDAT " "Node \"I2C_SDAT\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393808704834 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "" 0 -1 1393808704834 ""} -{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:10 " "Fitter preparation operations ending: elapsed time is 00:00:10" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1 1393808704834 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "" 0 -1 1393808706764 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:02 " "Fitter placement preparation operations ending: elapsed time is 00:00:02" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1 1393808708374 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "" 0 -1 1393808708424 ""} -{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "" 0 -1 1393808715634 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:07 " "Fitter placement operations ending: elapsed time is 00:00:07" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 -1 1393808715634 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "" 0 -1 1393808717474 ""} -{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "6 " "Router estimated average interconnect usage is 6% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "37 X21_Y11 X31_Y22 " "Router estimated peak interconnect usage is 37% of the available device resources in the region that extends from location X21_Y11 to location X31_Y22" { } { { "loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 1 { 0 "Router estimated peak interconnect usage is 37% of the available device resources in the region that extends from location X21_Y11 to location X31_Y22"} { { 11 { 0 "Router estimated peak interconnect usage is 37% of the available device resources in the region that extends from location X21_Y11 to location X31_Y22"} 21 11 11 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1 1393808722064 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1 1393808722064 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:06 " "Fitter routing operations ending: elapsed time is 00:00:06" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 -1 1393808724594 ""} -{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 -1 1393808724604 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 -1 1393808724604 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "" 0 -1 1393808724604 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "" 0 -1 1393808724844 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "" 0 -1 1393808725514 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "" 0 -1 1393808725574 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "" 0 -1 1393808726304 ""} -{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:04 " "Fitter post-fit operations ending: elapsed time is 00:00:04" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "" 0 -1 1393808728554 ""} -{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "" 0 -1 1393808729194 ""} -{ "Warning" "WFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE" "68 " "Following 68 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[0\] a permanently disabled " "Pin GPIO_0\[0\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[0] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[0\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 320 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393808729244 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[1\] a permanently disabled " "Pin GPIO_0\[1\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[1] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[1\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 321 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393808729244 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[2\] a permanently disabled " "Pin GPIO_0\[2\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[2] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[2\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 322 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393808729244 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[3\] a permanently disabled " "Pin GPIO_0\[3\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[3] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[3\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 323 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393808729244 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[4\] a permanently disabled " "Pin GPIO_0\[4\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[4] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[4\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 324 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393808729244 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[5\] a permanently disabled " "Pin GPIO_0\[5\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[5] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[5\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 325 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393808729244 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[6\] a permanently disabled " "Pin GPIO_0\[6\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[6] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[6\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 326 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393808729244 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[7\] a permanently disabled " "Pin GPIO_0\[7\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[7] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[7\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 327 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393808729244 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[8\] a permanently disabled " "Pin GPIO_0\[8\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[8] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[8\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 328 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393808729244 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[9\] a permanently disabled " "Pin GPIO_0\[9\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[9] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[9\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 329 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393808729244 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[10\] a permanently disabled " "Pin GPIO_0\[10\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[10] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[10\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 330 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393808729244 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[11\] a permanently disabled " "Pin GPIO_0\[11\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[11] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[11\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 331 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393808729244 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[12\] a permanently disabled " "Pin GPIO_0\[12\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[12] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[12\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 332 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393808729244 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[13\] a permanently disabled " "Pin GPIO_0\[13\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[13] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[13\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 333 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393808729244 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[14\] a permanently disabled " "Pin GPIO_0\[14\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[14] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[14\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 334 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393808729244 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[15\] a permanently disabled " "Pin GPIO_0\[15\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[15] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[15\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 335 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393808729244 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[16\] a permanently disabled " "Pin GPIO_0\[16\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[16] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[16\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[16] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 336 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393808729244 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[17\] a permanently disabled " "Pin GPIO_0\[17\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[17] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[17\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[17] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 337 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393808729244 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[18\] a permanently disabled " "Pin GPIO_0\[18\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[18] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[18\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[18] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 338 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393808729244 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[19\] a permanently disabled " "Pin GPIO_0\[19\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[19] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[19\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[19] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 339 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393808729244 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[20\] a permanently disabled " "Pin GPIO_0\[20\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[20] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[20\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[20] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 340 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393808729244 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[21\] a permanently disabled " "Pin GPIO_0\[21\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[21] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[21\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[21] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 341 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393808729244 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[22\] a permanently disabled " "Pin GPIO_0\[22\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[22] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[22\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[22] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 342 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393808729244 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[23\] a permanently disabled " "Pin GPIO_0\[23\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[23] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[23\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[23] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 343 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393808729244 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[24\] a permanently disabled " "Pin GPIO_0\[24\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[24] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[24\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[24] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 344 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393808729244 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[25\] a permanently disabled " "Pin GPIO_0\[25\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[25] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[25\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[25] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 345 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393808729244 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[26\] a permanently disabled " "Pin GPIO_0\[26\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[26] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[26\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[26] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 346 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393808729244 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[27\] a permanently disabled " "Pin GPIO_0\[27\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[27] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[27\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[27] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 347 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393808729244 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[28\] a permanently disabled " "Pin GPIO_0\[28\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[28] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[28\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[28] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 348 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393808729244 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[29\] a permanently disabled " "Pin GPIO_0\[29\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[29] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[29\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[29] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 349 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393808729244 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[30\] a permanently disabled " "Pin GPIO_0\[30\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[30] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[30\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[30] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 350 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393808729244 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[32\] a permanently disabled " "Pin GPIO_0\[32\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[32] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[32\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[32] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 351 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393808729244 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[1\] a permanently disabled " "Pin GPIO_1\[1\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[1] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[1\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 352 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393808729244 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[2\] a permanently disabled " "Pin GPIO_1\[2\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[2] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[2\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 353 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393808729244 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[3\] a permanently disabled " "Pin GPIO_1\[3\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[3] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[3\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 354 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393808729244 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[4\] a permanently disabled " "Pin GPIO_1\[4\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[4] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[4\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 355 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393808729244 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[5\] a permanently disabled " "Pin GPIO_1\[5\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[5] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[5\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 356 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393808729244 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[6\] a permanently disabled " "Pin GPIO_1\[6\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[6] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[6\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 357 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393808729244 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[7\] a permanently disabled " "Pin GPIO_1\[7\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[7] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[7\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 358 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393808729244 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[8\] a permanently disabled " "Pin GPIO_1\[8\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[8] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[8\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 359 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393808729244 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[9\] a permanently disabled " "Pin GPIO_1\[9\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[9] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[9\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 360 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393808729244 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[10\] a permanently disabled " "Pin GPIO_1\[10\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[10] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[10\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 361 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393808729244 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[11\] a permanently disabled " "Pin GPIO_1\[11\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[11] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[11\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 362 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393808729244 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[12\] a permanently disabled " "Pin GPIO_1\[12\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[12] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[12\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 363 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393808729244 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[13\] a permanently disabled " "Pin GPIO_1\[13\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[13] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[13\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 364 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393808729244 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[14\] a permanently disabled " "Pin GPIO_1\[14\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[14] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[14\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 365 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393808729244 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[15\] a permanently disabled " "Pin GPIO_1\[15\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[15] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[15\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 366 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393808729244 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[16\] a permanently disabled " "Pin GPIO_1\[16\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[16] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[16\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[16] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 367 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393808729244 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[17\] a permanently disabled " "Pin GPIO_1\[17\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[17] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[17\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[17] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 368 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393808729244 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[18\] a permanently disabled " "Pin GPIO_1\[18\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[18] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[18\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[18] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 369 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393808729244 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[19\] a permanently disabled " "Pin GPIO_1\[19\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[19] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[19\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[19] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 370 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393808729244 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[20\] a permanently disabled " "Pin GPIO_1\[20\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[20] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[20\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[20] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 371 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393808729244 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[21\] a permanently disabled " "Pin GPIO_1\[21\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[21] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[21\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[21] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 372 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393808729244 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[22\] a permanently disabled " "Pin GPIO_1\[22\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[22] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[22\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[22] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 373 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393808729244 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[23\] a permanently disabled " "Pin GPIO_1\[23\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[23] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[23\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[23] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 374 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393808729244 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[24\] a permanently disabled " "Pin GPIO_1\[24\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[24] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[24\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[24] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 375 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393808729244 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[25\] a permanently disabled " "Pin GPIO_1\[25\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[25] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[25\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[25] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 376 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393808729244 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[26\] a permanently disabled " "Pin GPIO_1\[26\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[26] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[26\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[26] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 377 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393808729244 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[27\] a permanently disabled " "Pin GPIO_1\[27\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[27] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[27\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[27] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 378 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393808729244 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[28\] a permanently disabled " "Pin GPIO_1\[28\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[28] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[28\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[28] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 379 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393808729244 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[29\] a permanently disabled " "Pin GPIO_1\[29\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[29] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[29\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[29] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 380 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393808729244 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[30\] a permanently disabled " "Pin GPIO_1\[30\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[30] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[30\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[30] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 381 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393808729244 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[32\] a permanently disabled " "Pin GPIO_1\[32\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[32] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[32\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[32] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 382 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393808729244 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[31\] a permanently disabled " "Pin GPIO_0\[31\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[31] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[31\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[31] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 271 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393808729244 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[33\] a permanently enabled " "Pin GPIO_0\[33\] has a permanently enabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[33] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[33\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[33] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 268 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393808729244 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[0\] a permanently enabled " "Pin GPIO_1\[0\] has a permanently enabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[0] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[0\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 272 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393808729244 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[31\] a permanently disabled " "Pin GPIO_1\[31\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[31] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[31\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[31] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 270 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393808729244 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[33\] a permanently enabled " "Pin GPIO_1\[33\] has a permanently enabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[33] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[33\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[33] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 269 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393808729244 ""} } { } 0 169064 "Following %1!d! pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results" 0 0 "" 0 -1 1393808729244 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/output_files/de0_nano_system.fit.smsg " "Generated suppressed messages file C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/output_files/de0_nano_system.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "" 0 -1 1393808729824 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 36 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 36 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1141 " "Peak virtual memory: 1141 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1 1393808731494 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Mar 02 18:05:31 2014 " "Processing ended: Sun Mar 02 18:05:31 2014" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1 1393808731494 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:39 " "Elapsed time: 00:00:39" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1 1393808731494 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:48 " "Total CPU time (on all processors): 00:00:48" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1 1393808731494 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1 1393808731494 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1 1393808732734 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Full Version " "Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1 1393808732734 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Mar 02 18:05:32 2014 " "Processing started: Sun Mar 02 18:05:32 2014" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1 1393808732734 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1 1393808732734 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off de0_nano_system -c de0_nano_system " "Command: quartus_asm --read_settings_files=off --write_settings_files=off de0_nano_system -c de0_nano_system" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1 1393808732734 ""} -{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "" 0 -1 1393808734904 ""} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "" 0 -1 1393808734954 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "460 " "Peak virtual memory: 460 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1 1393808735474 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Mar 02 18:05:35 2014 " "Processing ended: Sun Mar 02 18:05:35 2014" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1 1393808735474 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1 1393808735474 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1 1393808735474 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1 1393808735474 ""} -{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "" 0 -1 1393808736094 ""} -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1 1393808736824 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Full Version " "Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1 1393808736824 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Mar 02 18:05:36 2014 " "Processing started: Sun Mar 02 18:05:36 2014" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1 1393808736824 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1 1393808736824 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta de0_nano_system -c de0_nano_system " "Command: quartus_sta de0_nano_system -c de0_nano_system" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1 1393808736824 ""} -{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "" 0 0 1393808736894 ""} -{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." { } { } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "" 0 -1 1393808737274 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "" 0 -1 1393808737274 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "" 0 -1 1393808737334 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "" 0 -1 1393808737334 ""} -{ "Info" "ISTA_SDC_STATEMENT_PARENT" "" "Evaluating HDL-embedded SDC commands" { { "Info" "ISTA_SDC_STATEMENT_ENTITY" "alt_jtag_atlantic " "Entity alt_jtag_atlantic" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate1*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate1*\}\] " { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393808738104 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393808738104 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393808738104 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393808738104 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393808738104 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393808738104 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393808738104 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393808738104 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393808738104 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|read1*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|read1*\}\] " { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393808738104 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read_req\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read_req\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393808738104 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393808738104 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|tck_t_dav\}\] " "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|tck_t_dav\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393808738104 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|user_saw_rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid0*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|user_saw_rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid0*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393808738104 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393808738104 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393808738104 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393808738104 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393808738104 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393808738104 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393808738104 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393808738104 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393808738104 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write1*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write1*\}\] " { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393808738104 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_ena*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_ena*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393808738104 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_pause*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_pause*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393808738104 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_valid\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_valid\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393808738104 ""} } { } 0 332165 "Entity %1!s!" 0 0 "" 0 -1 1393808738104 ""} { "Info" "ISTA_SDC_STATEMENT_ENTITY" "altera_std_synchronizer " "Entity altera_std_synchronizer" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -to \[get_keepers \{*altera_std_synchronizer:*\|din_s1\}\] " "set_false_path -to \[get_keepers \{*altera_std_synchronizer:*\|din_s1\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393808738104 ""} } { } 0 332165 "Entity %1!s!" 0 0 "" 0 -1 1393808738104 ""} { "Info" "ISTA_SDC_STATEMENT_ENTITY" "sld_jtag_hub " "Entity sld_jtag_hub" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "create_clock -period 10MHz -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] " "create_clock -period 10MHz -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393808738104 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_clock_groups -asynchronous -group \{altera_reserved_tck\} " "set_clock_groups -asynchronous -group \{altera_reserved_tck\}" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393808738104 ""} } { } 0 332165 "Entity %1!s!" 0 0 "" 0 -1 1393808738104 ""} } { } 0 332164 "Evaluating HDL-embedded SDC commands" 0 0 "" 0 -1 1393808738104 ""} -{ "Info" "ISTA_SDC_FOUND" "de0_nano_system.sdc " "Reading SDC File: 'de0_nano_system.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "" 0 -1 1393808738154 ""} -{ "Warning" "WSTA_OVERWRITING_EXISTING_CLOCK" "altera_reserved_tck " "Overwriting existing clock: altera_reserved_tck" { } { } 0 332043 "Overwriting existing clock: %1!s!" 0 0 "" 0 -1 1393808738154 ""} -{ "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "Deriving PLL clocks " "Deriving PLL clocks" { { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -duty_cycle 50.00 -name \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} " "create_generated_clock -source \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -duty_cycle 50.00 -name \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}" { } { } 0 332110 "%1!s!" 0 0 "" 0 -1 1393808738154 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -phase -54.00 -duty_cycle 50.00 -name \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} " "create_generated_clock -source \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -phase -54.00 -duty_cycle 50.00 -name \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}" { } { } 0 332110 "%1!s!" 0 0 "" 0 -1 1393808738154 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 5 -duty_cycle 50.00 -name \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} " "create_generated_clock -source \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 5 -duty_cycle 50.00 -name \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\]\}" { } { } 0 332110 "%1!s!" 0 0 "" 0 -1 1393808738154 ""} } { } 0 332110 "%1!s!" 0 0 "" 0 -1 1393808738154 ""} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_CALL_IS_DELAYED" "" "Clock uncertainty is not calculated until you update the timing netlist." { } { } 0 332151 "Clock uncertainty is not calculated until you update the timing netlist." 0 0 "" 0 -1 1393808738154 ""} -{ "Info" "ISTA_SDC_FOUND" "system/synthesis/submodules/altera_reset_controller.sdc " "Reading SDC File: 'system/synthesis/submodules/altera_reset_controller.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "" 0 -1 1393808738164 ""} -{ "Info" "ISTA_SDC_FOUND" "system/synthesis/submodules/system_cpu.sdc " "Reading SDC File: 'system/synthesis/submodules/system_cpu.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "" 0 -1 1393808738184 ""} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "" 0 -1 1393808738394 ""} -{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "" 0 0 1393808738394 ""} -{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "" 0 0 1393808738414 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup 1.944 " "Worst-case setup slack is 1.944" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393808738494 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393808738494 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.944 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 1.944 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393808738494 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 97.388 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 97.388 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393808738494 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1393808738494 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.246 " "Worst-case hold slack is 0.246" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393808738514 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393808738514 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.246 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.246 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393808738514 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.361 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 0.361 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393808738514 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1393808738514 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 2.156 " "Worst-case recovery slack is 2.156" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393808738524 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393808738524 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 2.156 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 2.156 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393808738524 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1393808738524 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "removal 2.023 " "Worst-case removal slack is 2.023" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393808738534 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393808738534 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 2.023 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 2.023 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393808738534 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1393808738534 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 4.693 " "Worst-case minimum pulse width slack is 4.693" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393808738544 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393808738544 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.693 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 4.693 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393808738544 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 9.835 0.000 CLOCK_50 " " 9.835 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393808738544 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 49.624 0.000 altera_reserved_tck " " 49.624 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393808738544 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 49.747 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 49.747 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393808738544 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1393808738544 ""} -{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 6 synchronizer chains. " "Report Metastability: Found 6 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n " "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393808738824 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 6 " "Number of Synchronizer Chains Found: 6" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393808738824 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393808738824 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 0.333 " "Fraction of Chains for which MTBFs Could Not be Calculated: 0.333" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393808738824 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 16.778 ns " "Worst Case Available Settling Time: 16.778 ns" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393808738824 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393808738824 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. " "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions." { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393808738824 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8 " " - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393808738824 ""} } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393808738824 ""} -{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "" 0 0 1393808738834 ""} -{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "" 0 -1 1393808738874 ""} -{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "" 0 -1 1393808739704 ""} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "" 0 -1 1393808740064 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup 2.250 " "Worst-case setup slack is 2.250" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393808740144 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393808740144 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 2.250 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 2.250 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393808740144 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 97.707 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 97.707 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393808740144 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1393808740144 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.242 " "Worst-case hold slack is 0.242" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393808740184 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393808740184 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.242 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.242 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393808740184 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.320 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 0.320 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393808740184 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1393808740184 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 2.469 " "Worst-case recovery slack is 2.469" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393808740204 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393808740204 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 2.469 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 2.469 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393808740204 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1393808740204 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "removal 1.807 " "Worst-case removal slack is 1.807" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393808740214 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393808740214 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.807 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 1.807 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393808740214 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1393808740214 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 4.719 " "Worst-case minimum pulse width slack is 4.719" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393808740224 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393808740224 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.719 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 4.719 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393808740224 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 9.818 0.000 CLOCK_50 " " 9.818 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393808740224 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 49.604 0.000 altera_reserved_tck " " 49.604 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393808740224 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 49.744 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 49.744 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393808740224 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1393808740224 ""} -{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 6 synchronizer chains. " "Report Metastability: Found 6 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n " "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393808740514 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 6 " "Number of Synchronizer Chains Found: 6" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393808740514 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393808740514 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 0.333 " "Fraction of Chains for which MTBFs Could Not be Calculated: 0.333" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393808740514 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 17.094 ns " "Worst Case Available Settling Time: 17.094 ns" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393808740514 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393808740514 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. " "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions." { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393808740514 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8 " " - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393808740514 ""} } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393808740514 ""} -{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "" 0 0 1393808740524 ""} -{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "" 0 -1 1393808740924 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup 3.218 " "Worst-case setup slack is 3.218" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393808740964 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393808740964 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 3.218 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 3.218 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393808740964 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 98.512 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 98.512 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393808740964 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1393808740964 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.110 " "Worst-case hold slack is 0.110" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393808740994 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393808740994 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.110 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.110 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393808740994 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.193 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 0.193 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393808740994 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1393808740994 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 3.339 " "Worst-case recovery slack is 3.339" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393808741004 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393808741004 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 3.339 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 3.339 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393808741004 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1393808741004 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "removal 1.171 " "Worst-case removal slack is 1.171" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393808741024 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393808741024 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.171 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 1.171 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393808741024 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1393808741024 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 4.749 " "Worst-case minimum pulse width slack is 4.749" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393808741034 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393808741034 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.749 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 4.749 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393808741034 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 9.587 0.000 CLOCK_50 " " 9.587 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393808741034 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 49.482 0.000 altera_reserved_tck " " 49.482 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393808741034 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 49.782 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 49.782 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393808741034 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1393808741034 ""} -{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 6 synchronizer chains. " "Report Metastability: Found 6 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n " "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393808741334 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 6 " "Number of Synchronizer Chains Found: 6" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393808741334 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393808741334 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 0.333 " "Fraction of Chains for which MTBFs Could Not be Calculated: 0.333" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393808741334 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 18.234 ns " "Worst Case Available Settling Time: 18.234 ns" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393808741334 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393808741334 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. " "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions." { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393808741334 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8 " " - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393808741334 ""} } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393808741334 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "" 0 -1 1393808741864 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "" 0 -1 1393808741864 ""} -{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 1 Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "563 " "Peak virtual memory: 563 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1 1393808742204 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Mar 02 18:05:42 2014 " "Processing ended: Sun Mar 02 18:05:42 2014" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1 1393808742204 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1 1393808742204 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:07 " "Total CPU time (on all processors): 00:00:07" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1 1393808742204 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1 1393808742204 ""} -{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 167 s " "Quartus II Full Compilation was successful. 0 errors, 167 warnings" { } { } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1 1393808743194 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1 1393887288436 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Full Version " "Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1 1393887288437 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 03 15:54:48 2014 " "Processing started: Mon Mar 03 15:54:48 2014" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1 1393887288437 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1 1393887288437 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off de0_nano_system -c de0_nano_system " "Command: quartus_map --read_settings_files=on --write_settings_files=off de0_nano_system -c de0_nano_system" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1 1393887288437 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." { } { } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "" 0 -1 1393887288807 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "de0_nano_system.vhd 2 1 " "Found 2 design units, including 1 entities, in source file de0_nano_system.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 de0_nano_system-syn " "Found design unit 1: de0_nano_system-syn" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 86 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1 1393887289267 ""} { "Info" "ISGN_ENTITY_NAME" "1 de0_nano_system " "Found entity 1: de0_nano_system" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 55 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887289267 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393887289267 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "heartbeat.vhd 2 1 " "Found 2 design units, including 1 entities, in source file heartbeat.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 heartbeat-syn " "Found design unit 1: heartbeat-syn" { } { { "heartbeat.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/heartbeat.vhd" 61 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1 1393887289270 ""} { "Info" "ISGN_ENTITY_NAME" "1 heartbeat " "Found entity 1: heartbeat" { } { { "heartbeat.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/heartbeat.vhd" 49 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887289270 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393887289270 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/system.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/system.v" { { "Info" "ISGN_ENTITY_NAME" "1 system " "Found entity 1: system" { } { { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 6 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887289284 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393887289284 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_irq_mapper.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_irq_mapper.sv" { { "Info" "ISGN_ENTITY_NAME" "1 system_irq_mapper " "Found entity 1: system_irq_mapper" { } { { "system/synthesis/submodules/system_irq_mapper.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_irq_mapper.sv" 31 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887289286 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393887289286 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_merlin_width_adapter.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_width_adapter.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_width_adapter " "Found entity 1: altera_merlin_width_adapter" { } { { "system/synthesis/submodules/altera_merlin_width_adapter.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_width_adapter.sv" 25 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887289291 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393887289291 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_merlin_burst_uncompressor.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_burst_uncompressor.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_burst_uncompressor " "Found entity 1: altera_merlin_burst_uncompressor" { } { { "system/synthesis/submodules/altera_merlin_burst_uncompressor.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_burst_uncompressor.sv" 40 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887289293 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393887289293 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_merlin_address_alignment.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_address_alignment.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_address_alignment " "Found entity 1: altera_merlin_address_alignment" { } { { "system/synthesis/submodules/altera_merlin_address_alignment.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_address_alignment.sv" 26 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887289296 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393887289296 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_merlin_arbitrator.sv 2 2 " "Found 2 design units, including 2 entities, in source file system/synthesis/submodules/altera_merlin_arbitrator.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_arbitrator " "Found entity 1: altera_merlin_arbitrator" { } { { "system/synthesis/submodules/altera_merlin_arbitrator.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_arbitrator.sv" 103 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887289299 ""} { "Info" "ISGN_ENTITY_NAME" "2 altera_merlin_arb_adder " "Found entity 2: altera_merlin_arb_adder" { } { { "system/synthesis/submodules/altera_merlin_arbitrator.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_arbitrator.sv" 228 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887289299 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393887289299 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_rsp_xbar_mux_001.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_rsp_xbar_mux_001.sv" { { "Info" "ISGN_ENTITY_NAME" "1 system_rsp_xbar_mux_001 " "Found entity 1: system_rsp_xbar_mux_001" { } { { "system/synthesis/submodules/system_rsp_xbar_mux_001.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_rsp_xbar_mux_001.sv" 38 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887289302 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393887289302 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_rsp_xbar_mux.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_rsp_xbar_mux.sv" { { "Info" "ISGN_ENTITY_NAME" "1 system_rsp_xbar_mux " "Found entity 1: system_rsp_xbar_mux" { } { { "system/synthesis/submodules/system_rsp_xbar_mux.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_rsp_xbar_mux.sv" 38 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887289305 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393887289305 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_rsp_xbar_demux_002.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_rsp_xbar_demux_002.sv" { { "Info" "ISGN_ENTITY_NAME" "1 system_rsp_xbar_demux_002 " "Found entity 1: system_rsp_xbar_demux_002" { } { { "system/synthesis/submodules/system_rsp_xbar_demux_002.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_rsp_xbar_demux_002.sv" 43 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887289307 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393887289307 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_rsp_xbar_demux.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_rsp_xbar_demux.sv" { { "Info" "ISGN_ENTITY_NAME" "1 system_rsp_xbar_demux " "Found entity 1: system_rsp_xbar_demux" { } { { "system/synthesis/submodules/system_rsp_xbar_demux.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_rsp_xbar_demux.sv" 43 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887289309 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393887289309 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_cmd_xbar_mux.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_cmd_xbar_mux.sv" { { "Info" "ISGN_ENTITY_NAME" "1 system_cmd_xbar_mux " "Found entity 1: system_cmd_xbar_mux" { } { { "system/synthesis/submodules/system_cmd_xbar_mux.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cmd_xbar_mux.sv" 38 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887289311 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393887289311 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_cmd_xbar_demux_001.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_cmd_xbar_demux_001.sv" { { "Info" "ISGN_ENTITY_NAME" "1 system_cmd_xbar_demux_001 " "Found entity 1: system_cmd_xbar_demux_001" { } { { "system/synthesis/submodules/system_cmd_xbar_demux_001.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cmd_xbar_demux_001.sv" 43 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887289314 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393887289314 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_cmd_xbar_demux.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_cmd_xbar_demux.sv" { { "Info" "ISGN_ENTITY_NAME" "1 system_cmd_xbar_demux " "Found entity 1: system_cmd_xbar_demux" { } { { "system/synthesis/submodules/system_cmd_xbar_demux.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cmd_xbar_demux.sv" 43 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887289316 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393887289316 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_reset_controller.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_reset_controller.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_reset_controller " "Found entity 1: altera_reset_controller" { } { { "system/synthesis/submodules/altera_reset_controller.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_reset_controller.v" 28 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887289318 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393887289318 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_reset_synchronizer.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_reset_synchronizer.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_reset_synchronizer " "Found entity 1: altera_reset_synchronizer" { } { { "system/synthesis/submodules/altera_reset_synchronizer.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_reset_synchronizer.v" 24 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887289320 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393887289320 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_merlin_burst_adapter.sv 7 7 " "Found 7 design units, including 7 entities, in source file system/synthesis/submodules/altera_merlin_burst_adapter.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_burst_adapter_burstwrap_increment " "Found entity 1: altera_merlin_burst_adapter_burstwrap_increment" { } { { "system/synthesis/submodules/altera_merlin_burst_adapter.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_burst_adapter.sv" 40 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887289326 ""} { "Info" "ISGN_ENTITY_NAME" "2 altera_merlin_burst_adapter_adder " "Found entity 2: altera_merlin_burst_adapter_adder" { } { { "system/synthesis/submodules/altera_merlin_burst_adapter.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_burst_adapter.sv" 55 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887289326 ""} { "Info" "ISGN_ENTITY_NAME" "3 altera_merlin_burst_adapter_subtractor " "Found entity 3: altera_merlin_burst_adapter_subtractor" { } { { "system/synthesis/submodules/altera_merlin_burst_adapter.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_burst_adapter.sv" 77 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887289326 ""} { "Info" "ISGN_ENTITY_NAME" "4 altera_merlin_burst_adapter_min " "Found entity 4: altera_merlin_burst_adapter_min" { } { { "system/synthesis/submodules/altera_merlin_burst_adapter.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_burst_adapter.sv" 98 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887289326 ""} { "Info" "ISGN_ENTITY_NAME" "5 altera_merlin_burst_adapter " "Found entity 5: altera_merlin_burst_adapter" { } { { "system/synthesis/submodules/altera_merlin_burst_adapter.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_burst_adapter.sv" 264 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887289326 ""} { "Info" "ISGN_ENTITY_NAME" "6 altera_merlin_burst_adapter_uncompressed_only " "Found entity 6: altera_merlin_burst_adapter_uncompressed_only" { } { { "system/synthesis/submodules/altera_merlin_burst_adapter.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_burst_adapter.sv" 414 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887289326 ""} { "Info" "ISGN_ENTITY_NAME" "7 altera_merlin_burst_adapter_full " "Found entity 7: altera_merlin_burst_adapter_full" { } { { "system/synthesis/submodules/altera_merlin_burst_adapter.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_burst_adapter.sv" 468 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887289326 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393887289326 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_merlin_traffic_limiter.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_traffic_limiter.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_traffic_limiter " "Found entity 1: altera_merlin_traffic_limiter" { } { { "system/synthesis/submodules/altera_merlin_traffic_limiter.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_traffic_limiter.sv" 44 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887289329 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393887289329 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_avalon_st_pipeline_base.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_avalon_st_pipeline_base.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_avalon_st_pipeline_base " "Found entity 1: altera_avalon_st_pipeline_base" { } { { "system/synthesis/submodules/altera_avalon_st_pipeline_base.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_avalon_st_pipeline_base.v" 22 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887289331 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393887289331 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_id_router_002.sv 2 2 " "Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_id_router_002.sv" { { "Info" "ISGN_ENTITY_NAME" "1 system_id_router_002_default_decode " "Found entity 1: system_id_router_002_default_decode" { } { { "system/synthesis/submodules/system_id_router_002.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_id_router_002.sv" 32 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887289333 ""} { "Info" "ISGN_ENTITY_NAME" "2 system_id_router_002 " "Found entity 2: system_id_router_002" { } { { "system/synthesis/submodules/system_id_router_002.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_id_router_002.sv" 54 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887289333 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393887289333 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_id_router_001.sv 2 2 " "Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_id_router_001.sv" { { "Info" "ISGN_ENTITY_NAME" "1 system_id_router_001_default_decode " "Found entity 1: system_id_router_001_default_decode" { } { { "system/synthesis/submodules/system_id_router_001.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_id_router_001.sv" 32 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887289336 ""} { "Info" "ISGN_ENTITY_NAME" "2 system_id_router_001 " "Found entity 2: system_id_router_001" { } { { "system/synthesis/submodules/system_id_router_001.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_id_router_001.sv" 54 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887289336 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393887289336 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_id_router.sv 2 2 " "Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_id_router.sv" { { "Info" "ISGN_ENTITY_NAME" "1 system_id_router_default_decode " "Found entity 1: system_id_router_default_decode" { } { { "system/synthesis/submodules/system_id_router.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_id_router.sv" 32 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887289338 ""} { "Info" "ISGN_ENTITY_NAME" "2 system_id_router " "Found entity 2: system_id_router" { } { { "system/synthesis/submodules/system_id_router.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_id_router.sv" 54 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887289338 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393887289338 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_addr_router_001.sv 2 2 " "Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_addr_router_001.sv" { { "Info" "ISGN_ENTITY_NAME" "1 system_addr_router_001_default_decode " "Found entity 1: system_addr_router_001_default_decode" { } { { "system/synthesis/submodules/system_addr_router_001.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_addr_router_001.sv" 32 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887289341 ""} { "Info" "ISGN_ENTITY_NAME" "2 system_addr_router_001 " "Found entity 2: system_addr_router_001" { } { { "system/synthesis/submodules/system_addr_router_001.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_addr_router_001.sv" 54 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887289341 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393887289341 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_addr_router.sv 2 2 " "Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_addr_router.sv" { { "Info" "ISGN_ENTITY_NAME" "1 system_addr_router_default_decode " "Found entity 1: system_addr_router_default_decode" { } { { "system/synthesis/submodules/system_addr_router.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_addr_router.sv" 32 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887289343 ""} { "Info" "ISGN_ENTITY_NAME" "2 system_addr_router " "Found entity 2: system_addr_router" { } { { "system/synthesis/submodules/system_addr_router.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_addr_router.sv" 54 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887289343 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393887289343 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_avalon_sc_fifo.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_avalon_sc_fifo.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_avalon_sc_fifo " "Found entity 1: altera_avalon_sc_fifo" { } { { "system/synthesis/submodules/altera_avalon_sc_fifo.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_avalon_sc_fifo.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887289347 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393887289347 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_merlin_slave_agent.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_slave_agent.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_slave_agent " "Found entity 1: altera_merlin_slave_agent" { } { { "system/synthesis/submodules/altera_merlin_slave_agent.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_slave_agent.sv" 34 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887289350 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393887289350 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_merlin_master_agent.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_master_agent.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_master_agent " "Found entity 1: altera_merlin_master_agent" { } { { "system/synthesis/submodules/altera_merlin_master_agent.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_master_agent.sv" 28 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887289352 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393887289352 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_merlin_slave_translator.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_slave_translator.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_slave_translator " "Found entity 1: altera_merlin_slave_translator" { } { { "system/synthesis/submodules/altera_merlin_slave_translator.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_slave_translator.sv" 35 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887289355 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393887289355 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_merlin_master_translator.sv 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_merlin_master_translator.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_master_translator " "Found entity 1: altera_merlin_master_translator" { } { { "system/synthesis/submodules/altera_merlin_master_translator.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_master_translator.sv" 30 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887289358 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393887289358 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_up_rs232_counters.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_up_rs232_counters.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_up_rs232_counters " "Found entity 1: altera_up_rs232_counters" { } { { "system/synthesis/submodules/altera_up_rs232_counters.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_up_rs232_counters.v" 48 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887289360 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393887289360 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_up_rs232_in_deserializer.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_up_rs232_in_deserializer.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_up_rs232_in_deserializer " "Found entity 1: altera_up_rs232_in_deserializer" { } { { "system/synthesis/submodules/altera_up_rs232_in_deserializer.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_up_rs232_in_deserializer.v" 47 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887289363 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393887289363 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_up_rs232_out_serializer.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_up_rs232_out_serializer.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_up_rs232_out_serializer " "Found entity 1: altera_up_rs232_out_serializer" { } { { "system/synthesis/submodules/altera_up_rs232_out_serializer.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_up_rs232_out_serializer.v" 47 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887289365 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393887289365 ""} +{ "Warning" "WVRFX_L2_VERI_INGORE_DANGLING_COMMA" "altera_up_sync_fifo.v(157) " "Verilog HDL Module Instantiation warning at altera_up_sync_fifo.v(157): ignored dangling comma in List of Port Connections" { } { { "system/synthesis/submodules/altera_up_sync_fifo.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_up_sync_fifo.v" 157 0 0 } } } 0 10275 "Verilog HDL Module Instantiation warning at %1!s!: ignored dangling comma in List of Port Connections" 0 0 "" 0 -1 1393887289367 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/altera_up_sync_fifo.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/altera_up_sync_fifo.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_up_sync_fifo " "Found entity 1: altera_up_sync_fifo" { } { { "system/synthesis/submodules/altera_up_sync_fifo.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_up_sync_fifo.v" 47 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887289368 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393887289368 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_rs232_wifi.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_rs232_wifi.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_rs232_wifi " "Found entity 1: system_rs232_wifi" { } { { "system/synthesis/submodules/system_rs232_wifi.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_rs232_wifi.v" 48 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887289370 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393887289370 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_uart_mc.v 7 7 " "Found 7 design units, including 7 entities, in source file system/synthesis/submodules/system_uart_mc.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_uart_mc_log_module " "Found entity 1: system_uart_mc_log_module" { } { { "system/synthesis/submodules/system_uart_mc.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_mc.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887289375 ""} { "Info" "ISGN_ENTITY_NAME" "2 system_uart_mc_tx " "Found entity 2: system_uart_mc_tx" { } { { "system/synthesis/submodules/system_uart_mc.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_mc.v" 66 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887289375 ""} { "Info" "ISGN_ENTITY_NAME" "3 system_uart_mc_rx_stimulus_source_character_source_rom_module " "Found entity 3: system_uart_mc_rx_stimulus_source_character_source_rom_module" { } { { "system/synthesis/submodules/system_uart_mc.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_mc.v" 238 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887289375 ""} { "Info" "ISGN_ENTITY_NAME" "4 system_uart_mc_rx_stimulus_source " "Found entity 4: system_uart_mc_rx_stimulus_source" { } { { "system/synthesis/submodules/system_uart_mc.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_mc.v" 387 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887289375 ""} { "Info" "ISGN_ENTITY_NAME" "5 system_uart_mc_rx " "Found entity 5: system_uart_mc_rx" { } { { "system/synthesis/submodules/system_uart_mc.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_mc.v" 492 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887289375 ""} { "Info" "ISGN_ENTITY_NAME" "6 system_uart_mc_regs " "Found entity 6: system_uart_mc_regs" { } { { "system/synthesis/submodules/system_uart_mc.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_mc.v" 750 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887289375 ""} { "Info" "ISGN_ENTITY_NAME" "7 system_uart_mc " "Found entity 7: system_uart_mc" { } { { "system/synthesis/submodules/system_uart_mc.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_mc.v" 995 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887289375 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393887289375 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_pio_ir_emitter.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_pio_ir_emitter.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_pio_ir_emitter " "Found entity 1: system_pio_ir_emitter" { } { { "system/synthesis/submodules/system_pio_ir_emitter.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_pio_ir_emitter.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887289378 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393887289378 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_jtag_uart_0.v 7 7 " "Found 7 design units, including 7 entities, in source file system/synthesis/submodules/system_jtag_uart_0.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_jtag_uart_0_log_module " "Found entity 1: system_jtag_uart_0_log_module" { } { { "system/synthesis/submodules/system_jtag_uart_0.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_jtag_uart_0.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887289382 ""} { "Info" "ISGN_ENTITY_NAME" "2 system_jtag_uart_0_sim_scfifo_w " "Found entity 2: system_jtag_uart_0_sim_scfifo_w" { } { { "system/synthesis/submodules/system_jtag_uart_0.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_jtag_uart_0.v" 65 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887289382 ""} { "Info" "ISGN_ENTITY_NAME" "3 system_jtag_uart_0_scfifo_w " "Found entity 3: system_jtag_uart_0_scfifo_w" { } { { "system/synthesis/submodules/system_jtag_uart_0.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_jtag_uart_0.v" 123 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887289382 ""} { "Info" "ISGN_ENTITY_NAME" "4 system_jtag_uart_0_drom_module " "Found entity 4: system_jtag_uart_0_drom_module" { } { { "system/synthesis/submodules/system_jtag_uart_0.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_jtag_uart_0.v" 208 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887289382 ""} { "Info" "ISGN_ENTITY_NAME" "5 system_jtag_uart_0_sim_scfifo_r " "Found entity 5: system_jtag_uart_0_sim_scfifo_r" { } { { "system/synthesis/submodules/system_jtag_uart_0.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_jtag_uart_0.v" 362 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887289382 ""} { "Info" "ISGN_ENTITY_NAME" "6 system_jtag_uart_0_scfifo_r " "Found entity 6: system_jtag_uart_0_scfifo_r" { } { { "system/synthesis/submodules/system_jtag_uart_0.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_jtag_uart_0.v" 450 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887289382 ""} { "Info" "ISGN_ENTITY_NAME" "7 system_jtag_uart_0 " "Found entity 7: system_jtag_uart_0" { } { { "system/synthesis/submodules/system_jtag_uart_0.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_jtag_uart_0.v" 537 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887289382 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393887289382 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_pio_sw.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_pio_sw.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_pio_sw " "Found entity 1: system_pio_sw" { } { { "system/synthesis/submodules/system_pio_sw.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_pio_sw.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887289385 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393887289385 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_pio_key_left.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_pio_key_left.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_pio_key_left " "Found entity 1: system_pio_key_left" { } { { "system/synthesis/submodules/system_pio_key_left.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_pio_key_left.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887289387 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393887289387 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_pio_led.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_pio_led.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_pio_led " "Found entity 1: system_pio_led" { } { { "system/synthesis/submodules/system_pio_led.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_pio_led.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887289389 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393887289389 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_uart_wifi.v 7 7 " "Found 7 design units, including 7 entities, in source file system/synthesis/submodules/system_uart_wifi.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_uart_wifi_log_module " "Found entity 1: system_uart_wifi_log_module" { } { { "system/synthesis/submodules/system_uart_wifi.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_wifi.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887289394 ""} { "Info" "ISGN_ENTITY_NAME" "2 system_uart_wifi_tx " "Found entity 2: system_uart_wifi_tx" { } { { "system/synthesis/submodules/system_uart_wifi.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_wifi.v" 66 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887289394 ""} { "Info" "ISGN_ENTITY_NAME" "3 system_uart_wifi_rx_stimulus_source_character_source_rom_module " "Found entity 3: system_uart_wifi_rx_stimulus_source_character_source_rom_module" { } { { "system/synthesis/submodules/system_uart_wifi.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_wifi.v" 238 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887289394 ""} { "Info" "ISGN_ENTITY_NAME" "4 system_uart_wifi_rx_stimulus_source " "Found entity 4: system_uart_wifi_rx_stimulus_source" { } { { "system/synthesis/submodules/system_uart_wifi.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_wifi.v" 387 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887289394 ""} { "Info" "ISGN_ENTITY_NAME" "5 system_uart_wifi_rx " "Found entity 5: system_uart_wifi_rx" { } { { "system/synthesis/submodules/system_uart_wifi.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_wifi.v" 492 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887289394 ""} { "Info" "ISGN_ENTITY_NAME" "6 system_uart_wifi_regs " "Found entity 6: system_uart_wifi_regs" { } { { "system/synthesis/submodules/system_uart_wifi.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_wifi.v" 750 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887289394 ""} { "Info" "ISGN_ENTITY_NAME" "7 system_uart_wifi " "Found entity 7: system_uart_wifi" { } { { "system/synthesis/submodules/system_uart_wifi.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_wifi.v" 1006 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887289394 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393887289394 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_sys_clk_timer.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_sys_clk_timer.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_sys_clk_timer " "Found entity 1: system_sys_clk_timer" { } { { "system/synthesis/submodules/system_sys_clk_timer.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_sys_clk_timer.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887289397 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393887289397 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_sdram.v 2 2 " "Found 2 design units, including 2 entities, in source file system/synthesis/submodules/system_sdram.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_sdram_input_efifo_module " "Found entity 1: system_sdram_input_efifo_module" { } { { "system/synthesis/submodules/system_sdram.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_sdram.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887289401 ""} { "Info" "ISGN_ENTITY_NAME" "2 system_sdram " "Found entity 2: system_sdram" { } { { "system/synthesis/submodules/system_sdram.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_sdram.v" 158 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887289401 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393887289401 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_sysid.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_sysid.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_sysid " "Found entity 1: system_sysid" { } { { "system/synthesis/submodules/system_sysid.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_sysid.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887289403 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393887289403 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_cpu.v 28 28 " "Found 28 design units, including 28 entities, in source file system/synthesis/submodules/system_cpu.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_cpu_ic_data_module " "Found entity 1: system_cpu_ic_data_module" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887290834 ""} { "Info" "ISGN_ENTITY_NAME" "2 system_cpu_ic_tag_module " "Found entity 2: system_cpu_ic_tag_module" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 86 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887290834 ""} { "Info" "ISGN_ENTITY_NAME" "3 system_cpu_bht_module " "Found entity 3: system_cpu_bht_module" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 152 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887290834 ""} { "Info" "ISGN_ENTITY_NAME" "4 system_cpu_register_bank_a_module " "Found entity 4: system_cpu_register_bank_a_module" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 218 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887290834 ""} { "Info" "ISGN_ENTITY_NAME" "5 system_cpu_register_bank_b_module " "Found entity 5: system_cpu_register_bank_b_module" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 281 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887290834 ""} { "Info" "ISGN_ENTITY_NAME" "6 system_cpu_dc_tag_module " "Found entity 6: system_cpu_dc_tag_module" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 344 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887290834 ""} { "Info" "ISGN_ENTITY_NAME" "7 system_cpu_dc_data_module " "Found entity 7: system_cpu_dc_data_module" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 407 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887290834 ""} { "Info" "ISGN_ENTITY_NAME" "8 system_cpu_dc_victim_module " "Found entity 8: system_cpu_dc_victim_module" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 473 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887290834 ""} { "Info" "ISGN_ENTITY_NAME" "9 system_cpu_nios2_oci_debug " "Found entity 9: system_cpu_nios2_oci_debug" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 538 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887290834 ""} { "Info" "ISGN_ENTITY_NAME" "10 system_cpu_ociram_lpm_dram_bdp_component_module " "Found entity 10: system_cpu_ociram_lpm_dram_bdp_component_module" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 666 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887290834 ""} { "Info" "ISGN_ENTITY_NAME" "11 system_cpu_nios2_ocimem " "Found entity 11: system_cpu_nios2_ocimem" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 759 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887290834 ""} { "Info" "ISGN_ENTITY_NAME" "12 system_cpu_nios2_avalon_reg " "Found entity 12: system_cpu_nios2_avalon_reg" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 905 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887290834 ""} { "Info" "ISGN_ENTITY_NAME" "13 system_cpu_nios2_oci_break " "Found entity 13: system_cpu_nios2_oci_break" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 999 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887290834 ""} { "Info" "ISGN_ENTITY_NAME" "14 system_cpu_nios2_oci_xbrk " "Found entity 14: system_cpu_nios2_oci_xbrk" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 1293 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887290834 ""} { "Info" "ISGN_ENTITY_NAME" "15 system_cpu_nios2_oci_dbrk " "Found entity 15: system_cpu_nios2_oci_dbrk" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 1553 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887290834 ""} { "Info" "ISGN_ENTITY_NAME" "16 system_cpu_nios2_oci_itrace " "Found entity 16: system_cpu_nios2_oci_itrace" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 1741 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887290834 ""} { "Info" "ISGN_ENTITY_NAME" "17 system_cpu_nios2_oci_td_mode " "Found entity 17: system_cpu_nios2_oci_td_mode" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 2098 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887290834 ""} { "Info" "ISGN_ENTITY_NAME" "18 system_cpu_nios2_oci_dtrace " "Found entity 18: system_cpu_nios2_oci_dtrace" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 2165 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887290834 ""} { "Info" "ISGN_ENTITY_NAME" "19 system_cpu_nios2_oci_compute_tm_count " "Found entity 19: system_cpu_nios2_oci_compute_tm_count" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 2259 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887290834 ""} { "Info" "ISGN_ENTITY_NAME" "20 system_cpu_nios2_oci_fifowp_inc " "Found entity 20: system_cpu_nios2_oci_fifowp_inc" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 2330 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887290834 ""} { "Info" "ISGN_ENTITY_NAME" "21 system_cpu_nios2_oci_fifocount_inc " "Found entity 21: system_cpu_nios2_oci_fifocount_inc" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 2372 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887290834 ""} { "Info" "ISGN_ENTITY_NAME" "22 system_cpu_nios2_oci_fifo " "Found entity 22: system_cpu_nios2_oci_fifo" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 2418 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887290834 ""} { "Info" "ISGN_ENTITY_NAME" "23 system_cpu_nios2_oci_pib " "Found entity 23: system_cpu_nios2_oci_pib" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 2923 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887290834 ""} { "Info" "ISGN_ENTITY_NAME" "24 system_cpu_traceram_lpm_dram_bdp_component_module " "Found entity 24: system_cpu_traceram_lpm_dram_bdp_component_module" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 2991 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887290834 ""} { "Info" "ISGN_ENTITY_NAME" "25 system_cpu_nios2_oci_im " "Found entity 25: system_cpu_nios2_oci_im" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3080 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887290834 ""} { "Info" "ISGN_ENTITY_NAME" "26 system_cpu_nios2_performance_monitors " "Found entity 26: system_cpu_nios2_performance_monitors" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3217 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887290834 ""} { "Info" "ISGN_ENTITY_NAME" "27 system_cpu_nios2_oci " "Found entity 27: system_cpu_nios2_oci" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3233 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887290834 ""} { "Info" "ISGN_ENTITY_NAME" "28 system_cpu " "Found entity 28: system_cpu" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3736 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887290834 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393887290834 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_cpu_jtag_debug_module_sysclk.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_cpu_jtag_debug_module_sysclk.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_cpu_jtag_debug_module_sysclk " "Found entity 1: system_cpu_jtag_debug_module_sysclk" { } { { "system/synthesis/submodules/system_cpu_jtag_debug_module_sysclk.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu_jtag_debug_module_sysclk.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887290839 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393887290839 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_cpu_jtag_debug_module_tck.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_cpu_jtag_debug_module_tck.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_cpu_jtag_debug_module_tck " "Found entity 1: system_cpu_jtag_debug_module_tck" { } { { "system/synthesis/submodules/system_cpu_jtag_debug_module_tck.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu_jtag_debug_module_tck.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887290842 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393887290842 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_cpu_jtag_debug_module_wrapper " "Found entity 1: system_cpu_jtag_debug_module_wrapper" { } { { "system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887290845 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393887290845 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_cpu_mult_cell.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_cpu_mult_cell.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_cpu_mult_cell " "Found entity 1: system_cpu_mult_cell" { } { { "system/synthesis/submodules/system_cpu_mult_cell.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu_mult_cell.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887290848 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393887290848 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_cpu_oci_test_bench.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_cpu_oci_test_bench.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_cpu_oci_test_bench " "Found entity 1: system_cpu_oci_test_bench" { } { { "system/synthesis/submodules/system_cpu_oci_test_bench.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu_oci_test_bench.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887290850 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393887290850 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "system/synthesis/submodules/system_cpu_test_bench.v 1 1 " "Found 1 design units, including 1 entities, in source file system/synthesis/submodules/system_cpu_test_bench.v" { { "Info" "ISGN_ENTITY_NAME" "1 system_cpu_test_bench " "Found entity 1: system_cpu_test_bench" { } { { "system/synthesis/submodules/system_cpu_test_bench.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu_test_bench.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887290854 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393887290854 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pll_sys.vhd 2 1 " "Found 2 design units, including 1 entities, in source file pll_sys.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 pll_sys-SYN " "Found design unit 1: pll_sys-SYN" { } { { "pll_sys.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/pll_sys.vhd" 54 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1 1393887290857 ""} { "Info" "ISGN_ENTITY_NAME" "1 pll_sys " "Found entity 1: pll_sys" { } { { "pll_sys.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/pll_sys.vhd" 42 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887290857 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393887290857 ""} +{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "system_cpu.v(2066) " "Verilog HDL or VHDL warning at system_cpu.v(2066): conditional expression evaluates to a constant" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 2066 0 0 } } } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1 1393887290881 ""} +{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "system_cpu.v(2068) " "Verilog HDL or VHDL warning at system_cpu.v(2068): conditional expression evaluates to a constant" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 2068 0 0 } } } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1 1393887290881 ""} +{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "system_cpu.v(2224) " "Verilog HDL or VHDL warning at system_cpu.v(2224): conditional expression evaluates to a constant" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 2224 0 0 } } } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1 1393887290882 ""} +{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "system_cpu.v(3143) " "Verilog HDL or VHDL warning at system_cpu.v(3143): conditional expression evaluates to a constant" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3143 0 0 } } } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1 1393887290885 ""} +{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "system_sdram.v(316) " "Verilog HDL or VHDL warning at system_sdram.v(316): conditional expression evaluates to a constant" { } { { "system/synthesis/submodules/system_sdram.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_sdram.v" 316 0 0 } } } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1 1393887290892 ""} +{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "system_sdram.v(326) " "Verilog HDL or VHDL warning at system_sdram.v(326): conditional expression evaluates to a constant" { } { { "system/synthesis/submodules/system_sdram.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_sdram.v" 326 0 0 } } } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1 1393887290893 ""} +{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "system_sdram.v(336) " "Verilog HDL or VHDL warning at system_sdram.v(336): conditional expression evaluates to a constant" { } { { "system/synthesis/submodules/system_sdram.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_sdram.v" 336 0 0 } } } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1 1393887290893 ""} +{ "Warning" "WVRFX_L2_HDL_CONDITION_EXP_IS_CONST" "system_sdram.v(680) " "Verilog HDL or VHDL warning at system_sdram.v(680): conditional expression evaluates to a constant" { } { { "system/synthesis/submodules/system_sdram.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_sdram.v" 680 0 0 } } } 0 10037 "Verilog HDL or VHDL warning at %1!s!: conditional expression evaluates to a constant" 0 0 "" 0 -1 1393887290895 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "de0_nano_system " "Elaborating entity \"de0_nano_system\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1 1393887291050 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pll_sys pll_sys:inst_pll_sys " "Elaborating entity \"pll_sys\" for hierarchy \"pll_sys:inst_pll_sys\"" { } { { "de0_nano_system.vhd" "inst_pll_sys" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 152 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887291054 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll pll_sys:inst_pll_sys\|altpll:altpll_component " "Elaborating entity \"altpll\" for hierarchy \"pll_sys:inst_pll_sys\|altpll:altpll_component\"" { } { { "pll_sys.vhd" "altpll_component" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/pll_sys.vhd" 154 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887291103 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "pll_sys:inst_pll_sys\|altpll:altpll_component " "Elaborated megafunction instantiation \"pll_sys:inst_pll_sys\|altpll:altpll_component\"" { } { { "pll_sys.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/pll_sys.vhd" 154 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1393887291107 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "pll_sys:inst_pll_sys\|altpll:altpll_component " "Instantiated megafunction \"pll_sys:inst_pll_sys\|altpll:altpll_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "bandwidth_type AUTO " "Parameter \"bandwidth_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291111 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_divide_by 1 " "Parameter \"clk0_divide_by\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291111 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_duty_cycle 50 " "Parameter \"clk0_duty_cycle\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291111 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_multiply_by 2 " "Parameter \"clk0_multiply_by\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291111 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_phase_shift 0 " "Parameter \"clk0_phase_shift\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291111 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_divide_by 1 " "Parameter \"clk1_divide_by\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291111 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_duty_cycle 50 " "Parameter \"clk1_duty_cycle\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291111 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_multiply_by 2 " "Parameter \"clk1_multiply_by\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291111 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_phase_shift -1500 " "Parameter \"clk1_phase_shift\" = \"-1500\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291111 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_divide_by 5 " "Parameter \"clk2_divide_by\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291111 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_duty_cycle 50 " "Parameter \"clk2_duty_cycle\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291111 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_multiply_by 1 " "Parameter \"clk2_multiply_by\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291111 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_phase_shift 0 " "Parameter \"clk2_phase_shift\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291111 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "compensate_clock CLK0 " "Parameter \"compensate_clock\" = \"CLK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291111 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "inclk0_input_frequency 20000 " "Parameter \"inclk0_input_frequency\" = \"20000\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291111 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291111 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint CBX_MODULE_PREFIX=pll_sys " "Parameter \"lpm_hint\" = \"CBX_MODULE_PREFIX=pll_sys\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291111 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altpll " "Parameter \"lpm_type\" = \"altpll\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291111 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode NORMAL " "Parameter \"operation_mode\" = \"NORMAL\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291111 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_type AUTO " "Parameter \"pll_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291111 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_activeclock PORT_UNUSED " "Parameter \"port_activeclock\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291111 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_areset PORT_UNUSED " "Parameter \"port_areset\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291111 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad0 PORT_UNUSED " "Parameter \"port_clkbad0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291111 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad1 PORT_UNUSED " "Parameter \"port_clkbad1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291111 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkloss PORT_UNUSED " "Parameter \"port_clkloss\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291111 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkswitch PORT_UNUSED " "Parameter \"port_clkswitch\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291111 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_configupdate PORT_UNUSED " "Parameter \"port_configupdate\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291111 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_fbin PORT_UNUSED " "Parameter \"port_fbin\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291111 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk0 PORT_USED " "Parameter \"port_inclk0\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291111 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk1 PORT_UNUSED " "Parameter \"port_inclk1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291111 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_locked PORT_USED " "Parameter \"port_locked\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291111 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pfdena PORT_UNUSED " "Parameter \"port_pfdena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291111 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasecounterselect PORT_UNUSED " "Parameter \"port_phasecounterselect\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291111 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasedone PORT_UNUSED " "Parameter \"port_phasedone\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291111 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasestep PORT_UNUSED " "Parameter \"port_phasestep\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291111 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phaseupdown PORT_UNUSED " "Parameter \"port_phaseupdown\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291111 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pllena PORT_UNUSED " "Parameter \"port_pllena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291111 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanaclr PORT_UNUSED " "Parameter \"port_scanaclr\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291111 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclk PORT_UNUSED " "Parameter \"port_scanclk\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291111 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclkena PORT_UNUSED " "Parameter \"port_scanclkena\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291111 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandata PORT_UNUSED " "Parameter \"port_scandata\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291111 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandataout PORT_UNUSED " "Parameter \"port_scandataout\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291111 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandone PORT_UNUSED " "Parameter \"port_scandone\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291111 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanread PORT_UNUSED " "Parameter \"port_scanread\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291111 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanwrite PORT_UNUSED " "Parameter \"port_scanwrite\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291111 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk0 PORT_USED " "Parameter \"port_clk0\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291111 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk1 PORT_USED " "Parameter \"port_clk1\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291111 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk2 PORT_USED " "Parameter \"port_clk2\" = \"PORT_USED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291111 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk3 PORT_UNUSED " "Parameter \"port_clk3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291111 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk4 PORT_UNUSED " "Parameter \"port_clk4\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291111 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk5 PORT_UNUSED " "Parameter \"port_clk5\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291111 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena0 PORT_UNUSED " "Parameter \"port_clkena0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291111 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena1 PORT_UNUSED " "Parameter \"port_clkena1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291111 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena2 PORT_UNUSED " "Parameter \"port_clkena2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291111 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena3 PORT_UNUSED " "Parameter \"port_clkena3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291111 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena4 PORT_UNUSED " "Parameter \"port_clkena4\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291111 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena5 PORT_UNUSED " "Parameter \"port_clkena5\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291111 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk0 PORT_UNUSED " "Parameter \"port_extclk0\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291111 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk1 PORT_UNUSED " "Parameter \"port_extclk1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291111 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk2 PORT_UNUSED " "Parameter \"port_extclk2\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291111 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk3 PORT_UNUSED " "Parameter \"port_extclk3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291111 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "self_reset_on_loss_lock ON " "Parameter \"self_reset_on_loss_lock\" = \"ON\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291111 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_clock 5 " "Parameter \"width_clock\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291111 ""} } { { "pll_sys.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/pll_sys.vhd" 154 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1393887291111 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/pll_sys_altpll.v 1 1 " "Found 1 design units, including 1 entities, in source file db/pll_sys_altpll.v" { { "Info" "ISGN_ENTITY_NAME" "1 pll_sys_altpll " "Found entity 1: pll_sys_altpll" { } { { "db/pll_sys_altpll.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/pll_sys_altpll.v" 29 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887291174 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393887291174 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pll_sys_altpll pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated " "Elaborating entity \"pll_sys_altpll\" for hierarchy \"pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\"" { } { { "altpll.tdf" "auto_generated" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altpll.tdf" 897 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887291177 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "heartbeat heartbeat:inst_heartbeat " "Elaborating entity \"heartbeat\" for hierarchy \"heartbeat:inst_heartbeat\"" { } { { "de0_nano_system.vhd" "inst_heartbeat" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 161 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887291181 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system system:inst_cpu " "Elaborating entity \"system\" for hierarchy \"system:inst_cpu\"" { } { { "de0_nano_system.vhd" "inst_cpu" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887291184 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu system:inst_cpu\|system_cpu:cpu " "Elaborating entity \"system_cpu\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\"" { } { { "system/synthesis/system.v" "cpu" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887291235 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_test_bench system:inst_cpu\|system_cpu:cpu\|system_cpu_test_bench:the_system_cpu_test_bench " "Elaborating entity \"system_cpu_test_bench\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_test_bench:the_system_cpu_test_bench\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_test_bench" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 6073 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887291270 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_ic_data_module system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_data_module:system_cpu_ic_data " "Elaborating entity \"system_cpu_ic_data_module\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_data_module:system_cpu_ic_data\"" { } { { "system/synthesis/submodules/system_cpu.v" "system_cpu_ic_data" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 7098 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887291273 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_data_module:system_cpu_ic_data\|altsyncram:the_altsyncram " "Elaborating entity \"altsyncram\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_data_module:system_cpu_ic_data\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_altsyncram" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 58 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887291304 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_data_module:system_cpu_ic_data\|altsyncram:the_altsyncram " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_data_module:system_cpu_ic_data\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 58 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1393887291305 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_data_module:system_cpu_ic_data\|altsyncram:the_altsyncram " "Instantiated megafunction \"system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_data_module:system_cpu_ic_data\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291306 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 0 " "Parameter \"maximum_depth\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291306 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 2048 " "Parameter \"numwords_a\" = \"2048\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291306 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 2048 " "Parameter \"numwords_b\" = \"2048\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291306 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Parameter \"operation_mode\" = \"DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291306 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291306 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291306 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rdcontrol_reg_b CLOCK0 " "Parameter \"rdcontrol_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291306 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291306 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 32 " "Parameter \"width_a\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291306 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 32 " "Parameter \"width_b\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291306 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 11 " "Parameter \"widthad_a\" = \"11\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291306 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 11 " "Parameter \"widthad_b\" = \"11\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291306 ""} } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 58 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1393887291306 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_sjd1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_sjd1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_sjd1 " "Found entity 1: altsyncram_sjd1" { } { { "db/altsyncram_sjd1.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_sjd1.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887291386 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393887291386 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_sjd1 system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_data_module:system_cpu_ic_data\|altsyncram:the_altsyncram\|altsyncram_sjd1:auto_generated " "Elaborating entity \"altsyncram_sjd1\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_data_module:system_cpu_ic_data\|altsyncram:the_altsyncram\|altsyncram_sjd1:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887291388 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_ic_tag_module system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_tag_module:system_cpu_ic_tag " "Elaborating entity \"system_cpu_ic_tag_module\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_tag_module:system_cpu_ic_tag\"" { } { { "system/synthesis/submodules/system_cpu.v" "system_cpu_ic_tag" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 7164 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887291393 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_tag_module:system_cpu_ic_tag\|altsyncram:the_altsyncram " "Elaborating entity \"altsyncram\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_tag_module:system_cpu_ic_tag\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_altsyncram" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 123 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887291406 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_tag_module:system_cpu_ic_tag\|altsyncram:the_altsyncram " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_tag_module:system_cpu_ic_tag\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 123 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1393887291408 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_tag_module:system_cpu_ic_tag\|altsyncram:the_altsyncram " "Instantiated megafunction \"system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_tag_module:system_cpu_ic_tag\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291408 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file system_cpu_ic_tag_ram.mif " "Parameter \"init_file\" = \"system_cpu_ic_tag_ram.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291408 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 0 " "Parameter \"maximum_depth\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291408 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 256 " "Parameter \"numwords_a\" = \"256\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291408 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 256 " "Parameter \"numwords_b\" = \"256\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291408 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Parameter \"operation_mode\" = \"DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291408 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291408 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291408 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rdcontrol_reg_b CLOCK0 " "Parameter \"rdcontrol_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291408 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports OLD_DATA " "Parameter \"read_during_write_mode_mixed_ports\" = \"OLD_DATA\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291408 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 21 " "Parameter \"width_a\" = \"21\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291408 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 21 " "Parameter \"width_b\" = \"21\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291408 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 8 " "Parameter \"widthad_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291408 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 8 " "Parameter \"widthad_b\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291408 ""} } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 123 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1393887291408 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_qtg1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_qtg1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_qtg1 " "Found entity 1: altsyncram_qtg1" { } { { "db/altsyncram_qtg1.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_qtg1.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887291479 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393887291479 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_qtg1 system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_tag_module:system_cpu_ic_tag\|altsyncram:the_altsyncram\|altsyncram_qtg1:auto_generated " "Elaborating entity \"altsyncram_qtg1\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_ic_tag_module:system_cpu_ic_tag\|altsyncram:the_altsyncram\|altsyncram_qtg1:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887291481 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_bht_module system:inst_cpu\|system_cpu:cpu\|system_cpu_bht_module:system_cpu_bht " "Elaborating entity \"system_cpu_bht_module\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_bht_module:system_cpu_bht\"" { } { { "system/synthesis/submodules/system_cpu.v" "system_cpu_bht" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 7368 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887291503 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram system:inst_cpu\|system_cpu:cpu\|system_cpu_bht_module:system_cpu_bht\|altsyncram:the_altsyncram " "Elaborating entity \"altsyncram\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_bht_module:system_cpu_bht\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_altsyncram" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 189 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887291511 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_cpu:cpu\|system_cpu_bht_module:system_cpu_bht\|altsyncram:the_altsyncram " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_bht_module:system_cpu_bht\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 189 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1393887291512 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_cpu:cpu\|system_cpu_bht_module:system_cpu_bht\|altsyncram:the_altsyncram " "Instantiated megafunction \"system:inst_cpu\|system_cpu:cpu\|system_cpu_bht_module:system_cpu_bht\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291513 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file system_cpu_bht_ram.mif " "Parameter \"init_file\" = \"system_cpu_bht_ram.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291513 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 0 " "Parameter \"maximum_depth\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291513 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 256 " "Parameter \"numwords_a\" = \"256\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291513 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 256 " "Parameter \"numwords_b\" = \"256\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291513 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Parameter \"operation_mode\" = \"DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291513 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291513 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291513 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rdcontrol_reg_b CLOCK0 " "Parameter \"rdcontrol_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291513 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports OLD_DATA " "Parameter \"read_during_write_mode_mixed_ports\" = \"OLD_DATA\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291513 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 2 " "Parameter \"width_a\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291513 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 2 " "Parameter \"width_b\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291513 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 8 " "Parameter \"widthad_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291513 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 8 " "Parameter \"widthad_b\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291513 ""} } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 189 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1393887291513 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_fhg1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_fhg1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_fhg1 " "Found entity 1: altsyncram_fhg1" { } { { "db/altsyncram_fhg1.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_fhg1.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887291570 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393887291570 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_fhg1 system:inst_cpu\|system_cpu:cpu\|system_cpu_bht_module:system_cpu_bht\|altsyncram:the_altsyncram\|altsyncram_fhg1:auto_generated " "Elaborating entity \"altsyncram_fhg1\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_bht_module:system_cpu_bht\|altsyncram:the_altsyncram\|altsyncram_fhg1:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887291572 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_register_bank_a_module system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_a_module:system_cpu_register_bank_a " "Elaborating entity \"system_cpu_register_bank_a_module\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_a_module:system_cpu_register_bank_a\"" { } { { "system/synthesis/submodules/system_cpu.v" "system_cpu_register_bank_a" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 7514 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887291579 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_a_module:system_cpu_register_bank_a\|altsyncram:the_altsyncram " "Elaborating entity \"altsyncram\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_a_module:system_cpu_register_bank_a\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_altsyncram" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 252 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887291586 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_a_module:system_cpu_register_bank_a\|altsyncram:the_altsyncram " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_a_module:system_cpu_register_bank_a\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 252 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1393887291588 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_a_module:system_cpu_register_bank_a\|altsyncram:the_altsyncram " "Instantiated megafunction \"system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_a_module:system_cpu_register_bank_a\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291589 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file system_cpu_rf_ram_a.mif " "Parameter \"init_file\" = \"system_cpu_rf_ram_a.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291589 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 0 " "Parameter \"maximum_depth\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291589 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 32 " "Parameter \"numwords_a\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291589 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 32 " "Parameter \"numwords_b\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291589 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Parameter \"operation_mode\" = \"DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291589 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291589 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291589 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rdcontrol_reg_b CLOCK0 " "Parameter \"rdcontrol_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291589 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports OLD_DATA " "Parameter \"read_during_write_mode_mixed_ports\" = \"OLD_DATA\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291589 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 32 " "Parameter \"width_a\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291589 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 32 " "Parameter \"width_b\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291589 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 5 " "Parameter \"widthad_a\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291589 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 5 " "Parameter \"widthad_b\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291589 ""} } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 252 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1393887291589 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_fvf1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_fvf1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_fvf1 " "Found entity 1: altsyncram_fvf1" { } { { "db/altsyncram_fvf1.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_fvf1.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887291669 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393887291669 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_fvf1 system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_a_module:system_cpu_register_bank_a\|altsyncram:the_altsyncram\|altsyncram_fvf1:auto_generated " "Elaborating entity \"altsyncram_fvf1\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_a_module:system_cpu_register_bank_a\|altsyncram:the_altsyncram\|altsyncram_fvf1:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887291670 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_register_bank_b_module system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_b_module:system_cpu_register_bank_b " "Elaborating entity \"system_cpu_register_bank_b_module\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_b_module:system_cpu_register_bank_b\"" { } { { "system/synthesis/submodules/system_cpu.v" "system_cpu_register_bank_b" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 7535 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887291701 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_b_module:system_cpu_register_bank_b\|altsyncram:the_altsyncram " "Elaborating entity \"altsyncram\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_b_module:system_cpu_register_bank_b\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_altsyncram" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 315 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887291710 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_b_module:system_cpu_register_bank_b\|altsyncram:the_altsyncram " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_b_module:system_cpu_register_bank_b\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 315 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1393887291713 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_b_module:system_cpu_register_bank_b\|altsyncram:the_altsyncram " "Instantiated megafunction \"system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_b_module:system_cpu_register_bank_b\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291713 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file system_cpu_rf_ram_b.mif " "Parameter \"init_file\" = \"system_cpu_rf_ram_b.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291713 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 0 " "Parameter \"maximum_depth\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291713 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 32 " "Parameter \"numwords_a\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291713 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 32 " "Parameter \"numwords_b\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291713 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Parameter \"operation_mode\" = \"DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291713 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291713 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291713 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rdcontrol_reg_b CLOCK0 " "Parameter \"rdcontrol_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291713 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports OLD_DATA " "Parameter \"read_during_write_mode_mixed_ports\" = \"OLD_DATA\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291713 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 32 " "Parameter \"width_a\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291713 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 32 " "Parameter \"width_b\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291713 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 5 " "Parameter \"widthad_a\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291713 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 5 " "Parameter \"widthad_b\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291713 ""} } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 315 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1393887291713 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_gvf1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_gvf1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_gvf1 " "Found entity 1: altsyncram_gvf1" { } { { "db/altsyncram_gvf1.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_gvf1.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887291794 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393887291794 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_gvf1 system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_b_module:system_cpu_register_bank_b\|altsyncram:the_altsyncram\|altsyncram_gvf1:auto_generated " "Elaborating entity \"altsyncram_gvf1\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_register_bank_b_module:system_cpu_register_bank_b\|altsyncram:the_altsyncram\|altsyncram_gvf1:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887291796 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_dc_tag_module system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_tag_module:system_cpu_dc_tag " "Elaborating entity \"system_cpu_dc_tag_module\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_tag_module:system_cpu_dc_tag\"" { } { { "system/synthesis/submodules/system_cpu.v" "system_cpu_dc_tag" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 7968 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887291827 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_tag_module:system_cpu_dc_tag\|altsyncram:the_altsyncram " "Elaborating entity \"altsyncram\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_tag_module:system_cpu_dc_tag\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_altsyncram" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 378 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887291834 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_tag_module:system_cpu_dc_tag\|altsyncram:the_altsyncram " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_tag_module:system_cpu_dc_tag\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 378 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1393887291836 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_tag_module:system_cpu_dc_tag\|altsyncram:the_altsyncram " "Instantiated megafunction \"system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_tag_module:system_cpu_dc_tag\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291837 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file system_cpu_dc_tag_ram.mif " "Parameter \"init_file\" = \"system_cpu_dc_tag_ram.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291837 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 0 " "Parameter \"maximum_depth\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291837 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 128 " "Parameter \"numwords_a\" = \"128\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291837 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 128 " "Parameter \"numwords_b\" = \"128\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291837 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Parameter \"operation_mode\" = \"DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291837 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291837 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291837 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rdcontrol_reg_b CLOCK0 " "Parameter \"rdcontrol_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291837 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports OLD_DATA " "Parameter \"read_during_write_mode_mixed_ports\" = \"OLD_DATA\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291837 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 16 " "Parameter \"width_a\" = \"16\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291837 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 16 " "Parameter \"width_b\" = \"16\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291837 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 7 " "Parameter \"widthad_a\" = \"7\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291837 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 7 " "Parameter \"widthad_b\" = \"7\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291837 ""} } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 378 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1393887291837 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_d9g1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_d9g1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_d9g1 " "Found entity 1: altsyncram_d9g1" { } { { "db/altsyncram_d9g1.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_d9g1.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887291904 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393887291904 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_d9g1 system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_tag_module:system_cpu_dc_tag\|altsyncram:the_altsyncram\|altsyncram_d9g1:auto_generated " "Elaborating entity \"altsyncram_d9g1\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_tag_module:system_cpu_dc_tag\|altsyncram:the_altsyncram\|altsyncram_d9g1:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887291906 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_dc_data_module system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_data_module:system_cpu_dc_data " "Elaborating entity \"system_cpu_dc_data_module\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_data_module:system_cpu_dc_data\"" { } { { "system/synthesis/submodules/system_cpu.v" "system_cpu_dc_data" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 8022 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887291924 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_data_module:system_cpu_dc_data\|altsyncram:the_altsyncram " "Elaborating entity \"altsyncram\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_data_module:system_cpu_dc_data\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_altsyncram" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 444 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887291932 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_data_module:system_cpu_dc_data\|altsyncram:the_altsyncram " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_data_module:system_cpu_dc_data\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 444 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1393887291935 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_data_module:system_cpu_dc_data\|altsyncram:the_altsyncram " "Instantiated megafunction \"system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_data_module:system_cpu_dc_data\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291935 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 0 " "Parameter \"maximum_depth\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291935 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 1024 " "Parameter \"numwords_a\" = \"1024\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291935 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 1024 " "Parameter \"numwords_b\" = \"1024\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291935 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Parameter \"operation_mode\" = \"DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291935 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291935 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291935 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rdcontrol_reg_b CLOCK0 " "Parameter \"rdcontrol_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291935 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291935 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 32 " "Parameter \"width_a\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291935 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 32 " "Parameter \"width_b\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291935 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 4 " "Parameter \"width_byteena_a\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291935 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 10 " "Parameter \"widthad_a\" = \"10\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291935 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 10 " "Parameter \"widthad_b\" = \"10\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887291935 ""} } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 444 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1393887291935 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_2jf1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_2jf1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_2jf1 " "Found entity 1: altsyncram_2jf1" { } { { "db/altsyncram_2jf1.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_2jf1.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887292014 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393887292014 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_2jf1 system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_data_module:system_cpu_dc_data\|altsyncram:the_altsyncram\|altsyncram_2jf1:auto_generated " "Elaborating entity \"altsyncram_2jf1\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_data_module:system_cpu_dc_data\|altsyncram:the_altsyncram\|altsyncram_2jf1:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887292017 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_dc_victim_module system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_victim_module:system_cpu_dc_victim " "Elaborating entity \"system_cpu_dc_victim_module\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_victim_module:system_cpu_dc_victim\"" { } { { "system/synthesis/submodules/system_cpu.v" "system_cpu_dc_victim" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 8038 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887292020 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_victim_module:system_cpu_dc_victim\|altsyncram:the_altsyncram " "Elaborating entity \"altsyncram\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_victim_module:system_cpu_dc_victim\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_altsyncram" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 510 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887292028 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_victim_module:system_cpu_dc_victim\|altsyncram:the_altsyncram " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_victim_module:system_cpu_dc_victim\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 510 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1393887292031 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_victim_module:system_cpu_dc_victim\|altsyncram:the_altsyncram " "Instantiated megafunction \"system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_victim_module:system_cpu_dc_victim\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292032 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 0 " "Parameter \"maximum_depth\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292032 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 8 " "Parameter \"numwords_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292032 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 8 " "Parameter \"numwords_b\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292032 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Parameter \"operation_mode\" = \"DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292032 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292032 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292032 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rdcontrol_reg_b CLOCK0 " "Parameter \"rdcontrol_reg_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292032 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports OLD_DATA " "Parameter \"read_during_write_mode_mixed_ports\" = \"OLD_DATA\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292032 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 32 " "Parameter \"width_a\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292032 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 32 " "Parameter \"width_b\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292032 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 3 " "Parameter \"widthad_a\" = \"3\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292032 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 3 " "Parameter \"widthad_b\" = \"3\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292032 ""} } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 510 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1393887292032 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_r3d1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_r3d1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_r3d1 " "Found entity 1: altsyncram_r3d1" { } { { "db/altsyncram_r3d1.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_r3d1.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887292107 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393887292107 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_r3d1 system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_victim_module:system_cpu_dc_victim\|altsyncram:the_altsyncram\|altsyncram_r3d1:auto_generated " "Elaborating entity \"altsyncram_r3d1\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_dc_victim_module:system_cpu_dc_victim\|altsyncram:the_altsyncram\|altsyncram_r3d1:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887292110 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_mult_cell system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell " "Elaborating entity \"system_cpu_mult_cell\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_mult_cell" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 9915 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887292114 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altmult_add system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_1 " "Elaborating entity \"altmult_add\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_1\"" { } { { "system/synthesis/submodules/system_cpu_mult_cell.v" "the_altmult_add_part_1" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu_mult_cell.v" 52 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887292161 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_1 " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_1\"" { } { { "system/synthesis/submodules/system_cpu_mult_cell.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu_mult_cell.v" 52 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1393887292165 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_1 " "Instantiated megafunction \"system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_1\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "addnsub_multiplier_pipeline_aclr1 ACLR0 " "Parameter \"addnsub_multiplier_pipeline_aclr1\" = \"ACLR0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292167 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "addnsub_multiplier_pipeline_register1 CLOCK0 " "Parameter \"addnsub_multiplier_pipeline_register1\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292167 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "addnsub_multiplier_register1 UNREGISTERED " "Parameter \"addnsub_multiplier_register1\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292167 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "dedicated_multiplier_circuitry YES " "Parameter \"dedicated_multiplier_circuitry\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292167 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "input_register_a0 UNREGISTERED " "Parameter \"input_register_a0\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292167 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "input_register_b0 UNREGISTERED " "Parameter \"input_register_b0\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292167 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "input_source_a0 DATAA " "Parameter \"input_source_a0\" = \"DATAA\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292167 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "input_source_b0 DATAB " "Parameter \"input_source_b0\" = \"DATAB\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292167 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family CYCLONEIVE " "Parameter \"intended_device_family\" = \"CYCLONEIVE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292167 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altmult_add " "Parameter \"lpm_type\" = \"altmult_add\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292167 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "multiplier1_direction ADD " "Parameter \"multiplier1_direction\" = \"ADD\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292167 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "multiplier_aclr0 ACLR0 " "Parameter \"multiplier_aclr0\" = \"ACLR0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292167 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "multiplier_register0 CLOCK0 " "Parameter \"multiplier_register0\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292167 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "number_of_multipliers 1 " "Parameter \"number_of_multipliers\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292167 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_register UNREGISTERED " "Parameter \"output_register\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292167 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_addnsub1 PORT_UNUSED " "Parameter \"port_addnsub1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292167 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_addnsub3 PORT_UNUSED " "Parameter \"port_addnsub3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292167 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_signa PORT_UNUSED " "Parameter \"port_signa\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292167 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_signb PORT_UNUSED " "Parameter \"port_signb\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292167 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "representation_a UNSIGNED " "Parameter \"representation_a\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292167 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "representation_b UNSIGNED " "Parameter \"representation_b\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292167 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_pipeline_aclr_a ACLR0 " "Parameter \"signed_pipeline_aclr_a\" = \"ACLR0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292167 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_pipeline_aclr_b ACLR0 " "Parameter \"signed_pipeline_aclr_b\" = \"ACLR0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292167 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_pipeline_register_a CLOCK0 " "Parameter \"signed_pipeline_register_a\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292167 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_pipeline_register_b CLOCK0 " "Parameter \"signed_pipeline_register_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292167 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_register_a UNREGISTERED " "Parameter \"signed_register_a\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292167 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_register_b UNREGISTERED " "Parameter \"signed_register_b\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292167 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 16 " "Parameter \"width_a\" = \"16\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292167 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 16 " "Parameter \"width_b\" = \"16\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292167 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_result 32 " "Parameter \"width_result\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292167 ""} } { { "system/synthesis/submodules/system_cpu_mult_cell.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu_mult_cell.v" 52 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1393887292167 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mult_add_75u2.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mult_add_75u2.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mult_add_75u2 " "Found entity 1: mult_add_75u2" { } { { "db/mult_add_75u2.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/mult_add_75u2.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887292227 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393887292227 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mult_add_75u2 system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_1\|mult_add_75u2:auto_generated " "Elaborating entity \"mult_add_75u2\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_1\|mult_add_75u2:auto_generated\"" { } { { "altmult_add.tdf" "auto_generated" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altmult_add.tdf" 594 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887292229 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ded_mult_ks81.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/ded_mult_ks81.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 ded_mult_ks81 " "Found entity 1: ded_mult_ks81" { } { { "db/ded_mult_ks81.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/ded_mult_ks81.tdf" 30 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887292238 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393887292238 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ded_mult_ks81 system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_1\|mult_add_75u2:auto_generated\|ded_mult_ks81:ded_mult1 " "Elaborating entity \"ded_mult_ks81\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_1\|mult_add_75u2:auto_generated\|ded_mult_ks81:ded_mult1\"" { } { { "db/mult_add_75u2.tdf" "ded_mult1" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/mult_add_75u2.tdf" 33 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887292240 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/dffpipe_93c.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/dffpipe_93c.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 dffpipe_93c " "Found entity 1: dffpipe_93c" { } { { "db/dffpipe_93c.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/dffpipe_93c.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887292248 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393887292248 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dffpipe_93c system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_1\|mult_add_75u2:auto_generated\|ded_mult_ks81:ded_mult1\|dffpipe_93c:pre_result " "Elaborating entity \"dffpipe_93c\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_1\|mult_add_75u2:auto_generated\|ded_mult_ks81:ded_mult1\|dffpipe_93c:pre_result\"" { } { { "db/ded_mult_ks81.tdf" "pre_result" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/ded_mult_ks81.tdf" 50 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887292251 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altmult_add system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_2 " "Elaborating entity \"altmult_add\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_2\"" { } { { "system/synthesis/submodules/system_cpu_mult_cell.v" "the_altmult_add_part_2" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu_mult_cell.v" 93 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887292283 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_2 " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_2\"" { } { { "system/synthesis/submodules/system_cpu_mult_cell.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu_mult_cell.v" 93 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1393887292290 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_2 " "Instantiated megafunction \"system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_2\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "addnsub_multiplier_pipeline_aclr1 ACLR0 " "Parameter \"addnsub_multiplier_pipeline_aclr1\" = \"ACLR0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292291 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "addnsub_multiplier_pipeline_register1 CLOCK0 " "Parameter \"addnsub_multiplier_pipeline_register1\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292291 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "addnsub_multiplier_register1 UNREGISTERED " "Parameter \"addnsub_multiplier_register1\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292291 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "dedicated_multiplier_circuitry YES " "Parameter \"dedicated_multiplier_circuitry\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292291 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "input_register_a0 UNREGISTERED " "Parameter \"input_register_a0\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292291 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "input_register_b0 UNREGISTERED " "Parameter \"input_register_b0\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292291 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "input_source_a0 DATAA " "Parameter \"input_source_a0\" = \"DATAA\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292291 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "input_source_b0 DATAB " "Parameter \"input_source_b0\" = \"DATAB\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292291 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family CYCLONEIVE " "Parameter \"intended_device_family\" = \"CYCLONEIVE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292291 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altmult_add " "Parameter \"lpm_type\" = \"altmult_add\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292291 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "multiplier1_direction ADD " "Parameter \"multiplier1_direction\" = \"ADD\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292291 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "multiplier_aclr0 ACLR0 " "Parameter \"multiplier_aclr0\" = \"ACLR0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292291 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "multiplier_register0 CLOCK0 " "Parameter \"multiplier_register0\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292291 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "number_of_multipliers 1 " "Parameter \"number_of_multipliers\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292291 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_register UNREGISTERED " "Parameter \"output_register\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292291 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_addnsub1 PORT_UNUSED " "Parameter \"port_addnsub1\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292291 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_addnsub3 PORT_UNUSED " "Parameter \"port_addnsub3\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292291 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_signa PORT_UNUSED " "Parameter \"port_signa\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292291 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_signb PORT_UNUSED " "Parameter \"port_signb\" = \"PORT_UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292291 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "representation_a UNSIGNED " "Parameter \"representation_a\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292291 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "representation_b UNSIGNED " "Parameter \"representation_b\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292291 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_pipeline_aclr_a ACLR0 " "Parameter \"signed_pipeline_aclr_a\" = \"ACLR0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292291 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_pipeline_aclr_b ACLR0 " "Parameter \"signed_pipeline_aclr_b\" = \"ACLR0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292291 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_pipeline_register_a CLOCK0 " "Parameter \"signed_pipeline_register_a\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292291 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_pipeline_register_b CLOCK0 " "Parameter \"signed_pipeline_register_b\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292291 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_register_a UNREGISTERED " "Parameter \"signed_register_a\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292291 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signed_register_b UNREGISTERED " "Parameter \"signed_register_b\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292291 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 16 " "Parameter \"width_a\" = \"16\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292291 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 16 " "Parameter \"width_b\" = \"16\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292291 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_result 16 " "Parameter \"width_result\" = \"16\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292291 ""} } { { "system/synthesis/submodules/system_cpu_mult_cell.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu_mult_cell.v" 93 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1393887292291 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mult_add_95u2.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mult_add_95u2.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mult_add_95u2 " "Found entity 1: mult_add_95u2" { } { { "db/mult_add_95u2.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/mult_add_95u2.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887292351 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393887292351 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mult_add_95u2 system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_2\|mult_add_95u2:auto_generated " "Elaborating entity \"mult_add_95u2\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_mult_cell:the_system_cpu_mult_cell\|altmult_add:the_altmult_add_part_2\|mult_add_95u2:auto_generated\"" { } { { "altmult_add.tdf" "auto_generated" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altmult_add.tdf" 594 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887292353 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_oci system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci " "Elaborating entity \"system_cpu_nios2_oci\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_nios2_oci" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887292361 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_oci_debug system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_debug:the_system_cpu_nios2_oci_debug " "Elaborating entity \"system_cpu_nios2_oci_debug\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_debug:the_system_cpu_nios2_oci_debug\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_nios2_oci_debug" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3444 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887292366 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_ocimem system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem " "Elaborating entity \"system_cpu_nios2_ocimem\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_nios2_ocimem" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3464 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887292367 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_ociram_lpm_dram_bdp_component_module system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem\|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component " "Elaborating entity \"system_cpu_ociram_lpm_dram_bdp_component_module\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem\|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component\"" { } { { "system/synthesis/submodules/system_cpu.v" "system_cpu_ociram_lpm_dram_bdp_component" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 872 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887292370 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem\|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component\|altsyncram:the_altsyncram " "Elaborating entity \"altsyncram\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem\|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_altsyncram" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 720 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887292378 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem\|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component\|altsyncram:the_altsyncram " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem\|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 720 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1393887292381 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem\|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component\|altsyncram:the_altsyncram " "Instantiated megafunction \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem\|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_a NONE " "Parameter \"address_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292382 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_b NONE " "Parameter \"address_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292382 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK1 " "Parameter \"address_reg_b\" = \"CLOCK1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292382 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_aclr_a NONE " "Parameter \"indata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292382 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_aclr_b NONE " "Parameter \"indata_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292382 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file system_cpu_ociram_default_contents.mif " "Parameter \"init_file\" = \"system_cpu_ociram_default_contents.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292382 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family CYCLONEIVE " "Parameter \"intended_device_family\" = \"CYCLONEIVE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292382 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292382 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 256 " "Parameter \"numwords_a\" = \"256\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292382 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 256 " "Parameter \"numwords_b\" = \"256\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292382 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode BIDIR_DUAL_PORT " "Parameter \"operation_mode\" = \"BIDIR_DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292382 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292382 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_b NONE " "Parameter \"outdata_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292382 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a UNREGISTERED " "Parameter \"outdata_reg_a\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292382 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292382 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292382 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports OLD_DATA " "Parameter \"read_during_write_mode_mixed_ports\" = \"OLD_DATA\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292382 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 32 " "Parameter \"width_a\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292382 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 32 " "Parameter \"width_b\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292382 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 4 " "Parameter \"width_byteena_a\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292382 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 8 " "Parameter \"widthad_a\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292382 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 8 " "Parameter \"widthad_b\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292382 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_aclr_a NONE " "Parameter \"wrcontrol_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292382 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_aclr_b NONE " "Parameter \"wrcontrol_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292382 ""} } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 720 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1393887292382 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_jt72.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_jt72.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_jt72 " "Found entity 1: altsyncram_jt72" { } { { "db/altsyncram_jt72.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_jt72.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887292474 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393887292474 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_jt72 system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem\|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_jt72:auto_generated " "Elaborating entity \"altsyncram_jt72\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem\|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_jt72:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887292476 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_avalon_reg system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg " "Elaborating entity \"system_cpu_nios2_avalon_reg\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_nios2_avalon_reg" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3484 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887292508 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_oci_break system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_break:the_system_cpu_nios2_oci_break " "Elaborating entity \"system_cpu_nios2_oci_break\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_break:the_system_cpu_nios2_oci_break\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_nios2_oci_break" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3515 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887292510 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_oci_xbrk system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_xbrk:the_system_cpu_nios2_oci_xbrk " "Elaborating entity \"system_cpu_nios2_oci_xbrk\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_xbrk:the_system_cpu_nios2_oci_xbrk\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_nios2_oci_xbrk" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3538 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887292513 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_oci_dbrk system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_dbrk:the_system_cpu_nios2_oci_dbrk " "Elaborating entity \"system_cpu_nios2_oci_dbrk\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_dbrk:the_system_cpu_nios2_oci_dbrk\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_nios2_oci_dbrk" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3565 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887292514 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_oci_itrace system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_itrace:the_system_cpu_nios2_oci_itrace " "Elaborating entity \"system_cpu_nios2_oci_itrace\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_itrace:the_system_cpu_nios2_oci_itrace\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_nios2_oci_itrace" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3606 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887292516 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_oci_dtrace system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_dtrace:the_system_cpu_nios2_oci_dtrace " "Elaborating entity \"system_cpu_nios2_oci_dtrace\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_dtrace:the_system_cpu_nios2_oci_dtrace\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_nios2_oci_dtrace" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3621 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887292519 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_oci_td_mode system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_dtrace:the_system_cpu_nios2_oci_dtrace\|system_cpu_nios2_oci_td_mode:system_cpu_nios2_oci_trc_ctrl_td_mode " "Elaborating entity \"system_cpu_nios2_oci_td_mode\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_dtrace:the_system_cpu_nios2_oci_dtrace\|system_cpu_nios2_oci_td_mode:system_cpu_nios2_oci_trc_ctrl_td_mode\"" { } { { "system/synthesis/submodules/system_cpu.v" "system_cpu_nios2_oci_trc_ctrl_td_mode" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 2213 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887292522 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_oci_fifo system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_fifo:the_system_cpu_nios2_oci_fifo " "Elaborating entity \"system_cpu_nios2_oci_fifo\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_fifo:the_system_cpu_nios2_oci_fifo\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_nios2_oci_fifo" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3640 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887292523 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_oci_compute_tm_count system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_fifo:the_system_cpu_nios2_oci_fifo\|system_cpu_nios2_oci_compute_tm_count:system_cpu_nios2_oci_compute_tm_count_tm_count " "Elaborating entity \"system_cpu_nios2_oci_compute_tm_count\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_fifo:the_system_cpu_nios2_oci_fifo\|system_cpu_nios2_oci_compute_tm_count:system_cpu_nios2_oci_compute_tm_count_tm_count\"" { } { { "system/synthesis/submodules/system_cpu.v" "system_cpu_nios2_oci_compute_tm_count_tm_count" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 2545 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887292525 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_oci_fifowp_inc system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_fifo:the_system_cpu_nios2_oci_fifo\|system_cpu_nios2_oci_fifowp_inc:system_cpu_nios2_oci_fifowp_inc_fifowp " "Elaborating entity \"system_cpu_nios2_oci_fifowp_inc\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_fifo:the_system_cpu_nios2_oci_fifo\|system_cpu_nios2_oci_fifowp_inc:system_cpu_nios2_oci_fifowp_inc_fifowp\"" { } { { "system/synthesis/submodules/system_cpu.v" "system_cpu_nios2_oci_fifowp_inc_fifowp" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 2555 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887292527 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_oci_fifocount_inc system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_fifo:the_system_cpu_nios2_oci_fifo\|system_cpu_nios2_oci_fifocount_inc:system_cpu_nios2_oci_fifocount_inc_fifocount " "Elaborating entity \"system_cpu_nios2_oci_fifocount_inc\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_fifo:the_system_cpu_nios2_oci_fifo\|system_cpu_nios2_oci_fifocount_inc:system_cpu_nios2_oci_fifocount_inc_fifocount\"" { } { { "system/synthesis/submodules/system_cpu.v" "system_cpu_nios2_oci_fifocount_inc_fifocount" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 2565 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887292528 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_oci_test_bench system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_fifo:the_system_cpu_nios2_oci_fifo\|system_cpu_oci_test_bench:the_system_cpu_oci_test_bench " "Elaborating entity \"system_cpu_oci_test_bench\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_fifo:the_system_cpu_nios2_oci_fifo\|system_cpu_oci_test_bench:the_system_cpu_oci_test_bench\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_oci_test_bench" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 2574 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887292531 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_oci_pib system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_pib:the_system_cpu_nios2_oci_pib " "Elaborating entity \"system_cpu_nios2_oci_pib\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_pib:the_system_cpu_nios2_oci_pib\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_nios2_oci_pib" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3650 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887292533 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_nios2_oci_im system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im " "Elaborating entity \"system_cpu_nios2_oci_im\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_nios2_oci_im" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887292534 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_traceram_lpm_dram_bdp_component_module system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component " "Elaborating entity \"system_cpu_traceram_lpm_dram_bdp_component_module\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\"" { } { { "system/synthesis/submodules/system_cpu.v" "system_cpu_traceram_lpm_dram_bdp_component" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887292536 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram " "Elaborating entity \"altsyncram\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_altsyncram" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887292545 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\"" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1393887292547 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram " "Instantiated megafunction \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_a NONE " "Parameter \"address_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292549 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_b NONE " "Parameter \"address_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292549 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK1 " "Parameter \"address_reg_b\" = \"CLOCK1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292549 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_aclr_a NONE " "Parameter \"indata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292549 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_aclr_b NONE " "Parameter \"indata_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292549 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file UNUSED " "Parameter \"init_file\" = \"UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292549 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family CYCLONEIVE " "Parameter \"intended_device_family\" = \"CYCLONEIVE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292549 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292549 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 128 " "Parameter \"numwords_a\" = \"128\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292549 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 128 " "Parameter \"numwords_b\" = \"128\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292549 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode BIDIR_DUAL_PORT " "Parameter \"operation_mode\" = \"BIDIR_DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292549 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292549 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_b NONE " "Parameter \"outdata_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292549 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a UNREGISTERED " "Parameter \"outdata_reg_a\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292549 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292549 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292549 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports OLD_DATA " "Parameter \"read_during_write_mode_mixed_ports\" = \"OLD_DATA\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292549 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 36 " "Parameter \"width_a\" = \"36\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292549 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 36 " "Parameter \"width_b\" = \"36\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292549 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 7 " "Parameter \"widthad_a\" = \"7\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292549 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 7 " "Parameter \"widthad_b\" = \"7\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292549 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_aclr_a NONE " "Parameter \"wrcontrol_aclr_a\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292549 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_aclr_b NONE " "Parameter \"wrcontrol_aclr_b\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292549 ""} } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1393887292549 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_0a02.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_0a02.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_0a02 " "Found entity 1: altsyncram_0a02" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887292642 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393887292642 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_0a02 system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated " "Elaborating entity \"altsyncram_0a02\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\"" { } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887292644 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_jtag_debug_module_wrapper system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper " "Elaborating entity \"system_cpu_jtag_debug_module_wrapper\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\"" { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_jtag_debug_module_wrapper" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3714 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887292649 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_jtag_debug_module_tck system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck " "Elaborating entity \"system_cpu_jtag_debug_module_tck\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck\"" { } { { "system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v" "the_system_cpu_jtag_debug_module_tck" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v" 165 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887292652 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_std_synchronizer system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck\|altera_std_synchronizer:the_altera_std_synchronizer " "Elaborating entity \"altera_std_synchronizer\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck\|altera_std_synchronizer:the_altera_std_synchronizer\"" { } { { "system/synthesis/submodules/system_cpu_jtag_debug_module_tck.v" "the_altera_std_synchronizer" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu_jtag_debug_module_tck.v" 202 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887292665 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck\|altera_std_synchronizer:the_altera_std_synchronizer " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck\|altera_std_synchronizer:the_altera_std_synchronizer\"" { } { { "system/synthesis/submodules/system_cpu_jtag_debug_module_tck.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu_jtag_debug_module_tck.v" 202 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1393887292666 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck\|altera_std_synchronizer:the_altera_std_synchronizer " "Instantiated megafunction \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck\|altera_std_synchronizer:the_altera_std_synchronizer\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "depth 2 " "Parameter \"depth\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292666 ""} } { { "system/synthesis/submodules/system_cpu_jtag_debug_module_tck.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu_jtag_debug_module_tck.v" 202 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1393887292666 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cpu_jtag_debug_module_sysclk system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk " "Elaborating entity \"system_cpu_jtag_debug_module_sysclk\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk\"" { } { { "system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v" "the_system_cpu_jtag_debug_module_sysclk" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v" 188 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887292671 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sld_virtual_jtag_basic system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy " "Elaborating entity \"sld_virtual_jtag_basic\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy\"" { } { { "system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v" "system_cpu_jtag_debug_module_phy" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v" 218 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887292689 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy\"" { } { { "system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v" 218 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1393887292690 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy " "Instantiated megafunction \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_auto_instance_index YES " "Parameter \"sld_auto_instance_index\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292691 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_instance_index 0 " "Parameter \"sld_instance_index\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292691 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_ir_width 2 " "Parameter \"sld_ir_width\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292691 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_mfg_id 70 " "Parameter \"sld_mfg_id\" = \"70\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292691 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_sim_action " "Parameter \"sld_sim_action\" = \"\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292691 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_sim_n_scan 0 " "Parameter \"sld_sim_n_scan\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292691 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_sim_total_length 0 " "Parameter \"sld_sim_total_length\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292691 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_type_id 34 " "Parameter \"sld_type_id\" = \"34\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292691 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_version 3 " "Parameter \"sld_version\" = \"3\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292691 ""} } { { "system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v" 218 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1393887292691 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sld_virtual_jtag_impl system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy\|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst " "Elaborating entity \"sld_virtual_jtag_impl\" for hierarchy \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy\|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst\"" { } { { "sld_virtual_jtag_basic.v" "sld_virtual_jtag_impl_inst" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/sld_virtual_jtag_basic.v" 151 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887292693 ""} +{ "Info" "ISGN_MEGAFN_DESCENDANT" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy\|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy\|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst\", which is child of megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper\|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy\"" { } { { "sld_virtual_jtag_basic.v" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/sld_virtual_jtag_basic.v" 151 0 0 } } { "system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu_jtag_debug_module_wrapper.v" 218 0 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0 -1 1393887292695 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_sysid system:inst_cpu\|system_sysid:sysid " "Elaborating entity \"system_sysid\" for hierarchy \"system:inst_cpu\|system_sysid:sysid\"" { } { { "system/synthesis/system.v" "sysid" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 856 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887292698 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_sdram system:inst_cpu\|system_sdram:sdram " "Elaborating entity \"system_sdram\" for hierarchy \"system:inst_cpu\|system_sdram:sdram\"" { } { { "system/synthesis/system.v" "sdram" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 879 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887292700 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_sdram_input_efifo_module system:inst_cpu\|system_sdram:sdram\|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module " "Elaborating entity \"system_sdram_input_efifo_module\" for hierarchy \"system:inst_cpu\|system_sdram:sdram\|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module\"" { } { { "system/synthesis/submodules/system_sdram.v" "the_system_sdram_input_efifo_module" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_sdram.v" 296 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887292706 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_sys_clk_timer system:inst_cpu\|system_sys_clk_timer:sys_clk_timer " "Elaborating entity \"system_sys_clk_timer\" for hierarchy \"system:inst_cpu\|system_sys_clk_timer:sys_clk_timer\"" { } { { "system/synthesis/system.v" "sys_clk_timer" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 890 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887292709 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_uart_wifi system:inst_cpu\|system_uart_wifi:uart_wifi " "Elaborating entity \"system_uart_wifi\" for hierarchy \"system:inst_cpu\|system_uart_wifi:uart_wifi\"" { } { { "system/synthesis/system.v" "uart_wifi" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 907 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887292712 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_uart_wifi_tx system:inst_cpu\|system_uart_wifi:uart_wifi\|system_uart_wifi_tx:the_system_uart_wifi_tx " "Elaborating entity \"system_uart_wifi_tx\" for hierarchy \"system:inst_cpu\|system_uart_wifi:uart_wifi\|system_uart_wifi_tx:the_system_uart_wifi_tx\"" { } { { "system/synthesis/submodules/system_uart_wifi.v" "the_system_uart_wifi_tx" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_wifi.v" 1079 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887292715 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_uart_wifi_rx system:inst_cpu\|system_uart_wifi:uart_wifi\|system_uart_wifi_rx:the_system_uart_wifi_rx " "Elaborating entity \"system_uart_wifi_rx\" for hierarchy \"system:inst_cpu\|system_uart_wifi:uart_wifi\|system_uart_wifi_rx:the_system_uart_wifi_rx\"" { } { { "system/synthesis/submodules/system_uart_wifi.v" "the_system_uart_wifi_rx" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_wifi.v" 1097 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887292717 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_uart_wifi_rx_stimulus_source system:inst_cpu\|system_uart_wifi:uart_wifi\|system_uart_wifi_rx:the_system_uart_wifi_rx\|system_uart_wifi_rx_stimulus_source:the_system_uart_wifi_rx_stimulus_source " "Elaborating entity \"system_uart_wifi_rx_stimulus_source\" for hierarchy \"system:inst_cpu\|system_uart_wifi:uart_wifi\|system_uart_wifi_rx:the_system_uart_wifi_rx\|system_uart_wifi_rx_stimulus_source:the_system_uart_wifi_rx_stimulus_source\"" { } { { "system/synthesis/submodules/system_uart_wifi.v" "the_system_uart_wifi_rx_stimulus_source" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_wifi.v" 569 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887292720 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_uart_wifi_regs system:inst_cpu\|system_uart_wifi:uart_wifi\|system_uart_wifi_regs:the_system_uart_wifi_regs " "Elaborating entity \"system_uart_wifi_regs\" for hierarchy \"system:inst_cpu\|system_uart_wifi:uart_wifi\|system_uart_wifi_regs:the_system_uart_wifi_regs\"" { } { { "system/synthesis/submodules/system_uart_wifi.v" "the_system_uart_wifi_regs" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_wifi.v" 1128 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887292724 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_pio_led system:inst_cpu\|system_pio_led:pio_led " "Elaborating entity \"system_pio_led\" for hierarchy \"system:inst_cpu\|system_pio_led:pio_led\"" { } { { "system/synthesis/system.v" "pio_led" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 918 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887292727 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_pio_key_left system:inst_cpu\|system_pio_key_left:pio_key_left " "Elaborating entity \"system_pio_key_left\" for hierarchy \"system:inst_cpu\|system_pio_key_left:pio_key_left\"" { } { { "system/synthesis/system.v" "pio_key_left" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 930 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887292729 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_pio_sw system:inst_cpu\|system_pio_sw:pio_sw " "Elaborating entity \"system_pio_sw\" for hierarchy \"system:inst_cpu\|system_pio_sw:pio_sw\"" { } { { "system/synthesis/system.v" "pio_sw" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 938 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887292731 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_jtag_uart_0 system:inst_cpu\|system_jtag_uart_0:jtag_uart_0 " "Elaborating entity \"system_jtag_uart_0\" for hierarchy \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\"" { } { { "system/synthesis/system.v" "jtag_uart_0" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 951 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887292733 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_jtag_uart_0_scfifo_w system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w " "Elaborating entity \"system_jtag_uart_0_scfifo_w\" for hierarchy \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\"" { } { { "system/synthesis/submodules/system_jtag_uart_0.v" "the_system_jtag_uart_0_scfifo_w" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_jtag_uart_0.v" 625 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887292735 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scfifo system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo " "Elaborating entity \"scfifo\" for hierarchy \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\"" { } { { "system/synthesis/submodules/system_jtag_uart_0.v" "wfifo" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_jtag_uart_0.v" 183 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887292785 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo " "Elaborated megafunction instantiation \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\"" { } { { "system/synthesis/submodules/system_jtag_uart_0.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_jtag_uart_0.v" 183 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1393887292786 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo " "Instantiated megafunction \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint RAM_BLOCK_TYPE=AUTO " "Parameter \"lpm_hint\" = \"RAM_BLOCK_TYPE=AUTO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292787 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_numwords 64 " "Parameter \"lpm_numwords\" = \"64\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292787 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_showahead OFF " "Parameter \"lpm_showahead\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292787 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type scfifo " "Parameter \"lpm_type\" = \"scfifo\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292787 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 8 " "Parameter \"lpm_width\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292787 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widthu 6 " "Parameter \"lpm_widthu\" = \"6\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292787 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "overflow_checking OFF " "Parameter \"overflow_checking\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292787 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "underflow_checking OFF " "Parameter \"underflow_checking\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292787 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "use_eab ON " "Parameter \"use_eab\" = \"ON\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887292787 ""} } { { "system/synthesis/submodules/system_jtag_uart_0.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_jtag_uart_0.v" 183 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1393887292787 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/scfifo_jr21.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/scfifo_jr21.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 scfifo_jr21 " "Found entity 1: scfifo_jr21" { } { { "db/scfifo_jr21.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/scfifo_jr21.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887292842 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393887292842 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scfifo_jr21 system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated " "Elaborating entity \"scfifo_jr21\" for hierarchy \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\"" { } { { "scfifo.tdf" "auto_generated" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/scfifo.tdf" 296 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887292844 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_dpfifo_q131.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/a_dpfifo_q131.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_dpfifo_q131 " "Found entity 1: a_dpfifo_q131" { } { { "db/a_dpfifo_q131.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/a_dpfifo_q131.tdf" 28 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887292853 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393887292853 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_dpfifo_q131 system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo " "Elaborating entity \"a_dpfifo_q131\" for hierarchy \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\"" { } { { "db/scfifo_jr21.tdf" "dpfifo" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/scfifo_jr21.tdf" 37 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887292855 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_fefifo_7cf.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/a_fefifo_7cf.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_fefifo_7cf " "Found entity 1: a_fefifo_7cf" { } { { "db/a_fefifo_7cf.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/a_fefifo_7cf.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887292864 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393887292864 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_fefifo_7cf system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|a_fefifo_7cf:fifo_state " "Elaborating entity \"a_fefifo_7cf\" for hierarchy \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|a_fefifo_7cf:fifo_state\"" { } { { "db/a_dpfifo_q131.tdf" "fifo_state" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/a_dpfifo_q131.tdf" 42 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887292866 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_do7.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_do7.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_do7 " "Found entity 1: cntr_do7" { } { { "db/cntr_do7.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/cntr_do7.tdf" 25 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887292920 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393887292920 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_do7 system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|a_fefifo_7cf:fifo_state\|cntr_do7:count_usedw " "Elaborating entity \"cntr_do7\" for hierarchy \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|a_fefifo_7cf:fifo_state\|cntr_do7:count_usedw\"" { } { { "db/a_fefifo_7cf.tdf" "count_usedw" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/a_fefifo_7cf.tdf" 38 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887292922 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/dpram_nl21.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/dpram_nl21.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 dpram_nl21 " "Found entity 1: dpram_nl21" { } { { "db/dpram_nl21.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/dpram_nl21.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887292977 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393887292977 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dpram_nl21 system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|dpram_nl21:FIFOram " "Elaborating entity \"dpram_nl21\" for hierarchy \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|dpram_nl21:FIFOram\"" { } { { "db/a_dpfifo_q131.tdf" "FIFOram" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/a_dpfifo_q131.tdf" 43 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887292979 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_r1m1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_r1m1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_r1m1 " "Found entity 1: altsyncram_r1m1" { } { { "db/altsyncram_r1m1.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_r1m1.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887293041 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393887293041 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_r1m1 system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|dpram_nl21:FIFOram\|altsyncram_r1m1:altsyncram1 " "Elaborating entity \"altsyncram_r1m1\" for hierarchy \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|dpram_nl21:FIFOram\|altsyncram_r1m1:altsyncram1\"" { } { { "db/dpram_nl21.tdf" "altsyncram1" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/dpram_nl21.tdf" 36 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887293043 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_1ob.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_1ob.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_1ob " "Found entity 1: cntr_1ob" { } { { "db/cntr_1ob.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/cntr_1ob.tdf" 25 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887293097 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393887293097 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_1ob system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|cntr_1ob:rd_ptr_count " "Elaborating entity \"cntr_1ob\" for hierarchy \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_jr21:auto_generated\|a_dpfifo_q131:dpfifo\|cntr_1ob:rd_ptr_count\"" { } { { "db/a_dpfifo_q131.tdf" "rd_ptr_count" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/a_dpfifo_q131.tdf" 44 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887293099 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_jtag_uart_0_scfifo_r system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r " "Elaborating entity \"system_jtag_uart_0_scfifo_r\" for hierarchy \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r\"" { } { { "system/synthesis/submodules/system_jtag_uart_0.v" "the_system_jtag_uart_0_scfifo_r" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_jtag_uart_0.v" 639 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887293107 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_jtag_atlantic system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic " "Elaborating entity \"alt_jtag_atlantic\" for hierarchy \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic\"" { } { { "system/synthesis/submodules/system_jtag_uart_0.v" "system_jtag_uart_0_alt_jtag_atlantic" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_jtag_uart_0.v" 774 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887293226 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic " "Elaborated megafunction instantiation \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic\"" { } { { "system/synthesis/submodules/system_jtag_uart_0.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_jtag_uart_0.v" 774 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1393887293228 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic " "Instantiated megafunction \"system:inst_cpu\|system_jtag_uart_0:jtag_uart_0\|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "INSTANCE_ID 0 " "Parameter \"INSTANCE_ID\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887293228 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LOG2_RXFIFO_DEPTH 6 " "Parameter \"LOG2_RXFIFO_DEPTH\" = \"6\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887293228 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LOG2_TXFIFO_DEPTH 6 " "Parameter \"LOG2_TXFIFO_DEPTH\" = \"6\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887293228 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "SLD_AUTO_INSTANCE_INDEX YES " "Parameter \"SLD_AUTO_INSTANCE_INDEX\" = \"YES\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887293228 ""} } { { "system/synthesis/submodules/system_jtag_uart_0.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_jtag_uart_0.v" 774 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1393887293228 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_pio_ir_emitter system:inst_cpu\|system_pio_ir_emitter:pio_ir_emitter " "Elaborating entity \"system_pio_ir_emitter\" for hierarchy \"system:inst_cpu\|system_pio_ir_emitter:pio_ir_emitter\"" { } { { "system/synthesis/system.v" "pio_ir_emitter" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 962 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887293233 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_uart_mc system:inst_cpu\|system_uart_mc:uart_mc " "Elaborating entity \"system_uart_mc\" for hierarchy \"system:inst_cpu\|system_uart_mc:uart_mc\"" { } { { "system/synthesis/system.v" "uart_mc" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 979 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887293235 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_uart_mc_tx system:inst_cpu\|system_uart_mc:uart_mc\|system_uart_mc_tx:the_system_uart_mc_tx " "Elaborating entity \"system_uart_mc_tx\" for hierarchy \"system:inst_cpu\|system_uart_mc:uart_mc\|system_uart_mc_tx:the_system_uart_mc_tx\"" { } { { "system/synthesis/submodules/system_uart_mc.v" "the_system_uart_mc_tx" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_mc.v" 1068 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887293238 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_uart_mc_rx system:inst_cpu\|system_uart_mc:uart_mc\|system_uart_mc_rx:the_system_uart_mc_rx " "Elaborating entity \"system_uart_mc_rx\" for hierarchy \"system:inst_cpu\|system_uart_mc:uart_mc\|system_uart_mc_rx:the_system_uart_mc_rx\"" { } { { "system/synthesis/submodules/system_uart_mc.v" "the_system_uart_mc_rx" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_mc.v" 1086 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887293241 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_uart_mc_rx_stimulus_source system:inst_cpu\|system_uart_mc:uart_mc\|system_uart_mc_rx:the_system_uart_mc_rx\|system_uart_mc_rx_stimulus_source:the_system_uart_mc_rx_stimulus_source " "Elaborating entity \"system_uart_mc_rx_stimulus_source\" for hierarchy \"system:inst_cpu\|system_uart_mc:uart_mc\|system_uart_mc_rx:the_system_uart_mc_rx\|system_uart_mc_rx_stimulus_source:the_system_uart_mc_rx_stimulus_source\"" { } { { "system/synthesis/submodules/system_uart_mc.v" "the_system_uart_mc_rx_stimulus_source" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_mc.v" 569 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887293244 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_uart_mc_regs system:inst_cpu\|system_uart_mc:uart_mc\|system_uart_mc_regs:the_system_uart_mc_regs " "Elaborating entity \"system_uart_mc_regs\" for hierarchy \"system:inst_cpu\|system_uart_mc:uart_mc\|system_uart_mc_regs:the_system_uart_mc_regs\"" { } { { "system/synthesis/submodules/system_uart_mc.v" "the_system_uart_mc_regs" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_mc.v" 1117 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887293248 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_rs232_wifi system:inst_cpu\|system_rs232_wifi:rs232_wifi " "Elaborating entity \"system_rs232_wifi\" for hierarchy \"system:inst_cpu\|system_rs232_wifi:rs232_wifi\"" { } { { "system/synthesis/system.v" "rs232_wifi" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 994 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887293251 ""} +{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "write_data_parity system_rs232_wifi.v(123) " "Verilog HDL or VHDL warning at system_rs232_wifi.v(123): object \"write_data_parity\" assigned a value but never read" { } { { "system/synthesis/submodules/system_rs232_wifi.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_rs232_wifi.v" 123 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 -1 1393887293252 "|de0_nano_system|system:inst_cpu|system_rs232_wifi:rs232_wifi"} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_up_rs232_in_deserializer system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer " "Elaborating entity \"altera_up_rs232_in_deserializer\" for hierarchy \"system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\"" { } { { "system/synthesis/submodules/system_rs232_wifi.v" "RS232_In_Deserializer" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_rs232_wifi.v" 268 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887293254 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_up_rs232_counters system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_rs232_counters:RS232_In_Counters " "Elaborating entity \"altera_up_rs232_counters\" for hierarchy \"system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_rs232_counters:RS232_In_Counters\"" { } { { "system/synthesis/submodules/altera_up_rs232_in_deserializer.v" "RS232_In_Counters" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_up_rs232_in_deserializer.v" 181 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887293257 ""} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 altera_up_rs232_counters.v(124) " "Verilog HDL assignment warning at altera_up_rs232_counters.v(124): truncated value with size 32 to match size of target (14)" { } { { "system/synthesis/submodules/altera_up_rs232_counters.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_up_rs232_counters.v" 124 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 -1 1393887293258 "|de0_nano_system|system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_rs232_counters:RS232_In_Counters"} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_up_sync_fifo system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO " "Elaborating entity \"altera_up_sync_fifo\" for hierarchy \"system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\"" { } { { "system/synthesis/submodules/altera_up_rs232_in_deserializer.v" "RS232_In_FIFO" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_up_rs232_in_deserializer.v" 206 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887293259 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scfifo system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO " "Elaborating entity \"scfifo\" for hierarchy \"system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\"" { } { { "system/synthesis/submodules/altera_up_sync_fifo.v" "Sync_FIFO" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_up_sync_fifo.v" 157 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887293290 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO " "Elaborated megafunction instantiation \"system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\"" { } { { "system/synthesis/submodules/altera_up_sync_fifo.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_up_sync_fifo.v" 157 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1393887293291 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO " "Instantiated megafunction \"system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "add_ram_output_register OFF " "Parameter \"add_ram_output_register\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887293291 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone II " "Parameter \"intended_device_family\" = \"Cyclone II\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887293291 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_numwords 128 " "Parameter \"lpm_numwords\" = \"128\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887293291 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_showahead ON " "Parameter \"lpm_showahead\" = \"ON\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887293291 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type scfifo " "Parameter \"lpm_type\" = \"scfifo\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887293291 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 8 " "Parameter \"lpm_width\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887293291 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widthu 7 " "Parameter \"lpm_widthu\" = \"7\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887293291 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "overflow_checking OFF " "Parameter \"overflow_checking\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887293291 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "underflow_checking OFF " "Parameter \"underflow_checking\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887293291 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "use_eab ON " "Parameter \"use_eab\" = \"ON\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887293291 ""} } { { "system/synthesis/submodules/altera_up_sync_fifo.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_up_sync_fifo.v" 157 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1393887293291 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/scfifo_a341.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/scfifo_a341.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 scfifo_a341 " "Found entity 1: scfifo_a341" { } { { "db/scfifo_a341.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/scfifo_a341.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887293345 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393887293345 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scfifo_a341 system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated " "Elaborating entity \"scfifo_a341\" for hierarchy \"system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\"" { } { { "scfifo.tdf" "auto_generated" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/scfifo.tdf" 296 3 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887293347 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_dpfifo_tq31.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/a_dpfifo_tq31.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_dpfifo_tq31 " "Found entity 1: a_dpfifo_tq31" { } { { "db/a_dpfifo_tq31.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/a_dpfifo_tq31.tdf" 32 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887293356 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393887293356 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_dpfifo_tq31 system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo " "Elaborating entity \"a_dpfifo_tq31\" for hierarchy \"system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\"" { } { { "db/scfifo_a341.tdf" "dpfifo" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/scfifo_a341.tdf" 37 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887293359 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_je81.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_je81.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_je81 " "Found entity 1: altsyncram_je81" { } { { "db/altsyncram_je81.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_je81.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887293419 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393887293419 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_je81 system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|altsyncram_je81:FIFOram " "Elaborating entity \"altsyncram_je81\" for hierarchy \"system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|altsyncram_je81:FIFOram\"" { } { { "db/a_dpfifo_tq31.tdf" "FIFOram" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/a_dpfifo_tq31.tdf" 45 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887293422 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cmpr_ks8.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cmpr_ks8.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cmpr_ks8 " "Found entity 1: cmpr_ks8" { } { { "db/cmpr_ks8.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/cmpr_ks8.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887293475 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393887293475 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cmpr_ks8 system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cmpr_ks8:almost_full_comparer " "Elaborating entity \"cmpr_ks8\" for hierarchy \"system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cmpr_ks8:almost_full_comparer\"" { } { { "db/a_dpfifo_tq31.tdf" "almost_full_comparer" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/a_dpfifo_tq31.tdf" 54 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887293477 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cmpr_ks8 system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cmpr_ks8:three_comparison " "Elaborating entity \"cmpr_ks8\" for hierarchy \"system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cmpr_ks8:three_comparison\"" { } { { "db/a_dpfifo_tq31.tdf" "three_comparison" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/a_dpfifo_tq31.tdf" 55 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887293481 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_v9b.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_v9b.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_v9b " "Found entity 1: cntr_v9b" { } { { "db/cntr_v9b.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/cntr_v9b.tdf" 25 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887293534 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393887293534 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_v9b system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_v9b:rd_ptr_msb " "Elaborating entity \"cntr_v9b\" for hierarchy \"system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_v9b:rd_ptr_msb\"" { } { { "db/a_dpfifo_tq31.tdf" "rd_ptr_msb" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/a_dpfifo_tq31.tdf" 56 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887293537 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_ca7.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_ca7.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_ca7 " "Found entity 1: cntr_ca7" { } { { "db/cntr_ca7.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/cntr_ca7.tdf" 25 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887293591 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393887293591 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_ca7 system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_ca7:usedw_counter " "Elaborating entity \"cntr_ca7\" for hierarchy \"system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_ca7:usedw_counter\"" { } { { "db/a_dpfifo_tq31.tdf" "usedw_counter" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/a_dpfifo_tq31.tdf" 57 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887293593 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_0ab.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_0ab.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_0ab " "Found entity 1: cntr_0ab" { } { { "db/cntr_0ab.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/cntr_0ab.tdf" 25 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887293648 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393887293648 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_0ab system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr " "Elaborating entity \"cntr_0ab\" for hierarchy \"system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_in_deserializer:RS232_In_Deserializer\|altera_up_sync_fifo:RS232_In_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr\"" { } { { "db/a_dpfifo_tq31.tdf" "wr_ptr" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/a_dpfifo_tq31.tdf" 58 2 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887293650 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_up_rs232_out_serializer system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_out_serializer:RS232_Out_Serializer " "Elaborating entity \"altera_up_rs232_out_serializer\" for hierarchy \"system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_out_serializer:RS232_Out_Serializer\"" { } { { "system/synthesis/submodules/system_rs232_wifi.v" "RS232_Out_Serializer" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_rs232_wifi.v" 290 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887293656 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_master_translator system:inst_cpu\|altera_merlin_master_translator:cpu_instruction_master_translator " "Elaborating entity \"altera_merlin_master_translator\" for hierarchy \"system:inst_cpu\|altera_merlin_master_translator:cpu_instruction_master_translator\"" { } { { "system/synthesis/system.v" "cpu_instruction_master_translator" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 1048 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887293715 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_master_translator system:inst_cpu\|altera_merlin_master_translator:cpu_data_master_translator " "Elaborating entity \"altera_merlin_master_translator\" for hierarchy \"system:inst_cpu\|altera_merlin_master_translator:cpu_data_master_translator\"" { } { { "system/synthesis/system.v" "cpu_data_master_translator" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 1102 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887293718 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_translator system:inst_cpu\|altera_merlin_slave_translator:cpu_jtag_debug_module_translator " "Elaborating entity \"altera_merlin_slave_translator\" for hierarchy \"system:inst_cpu\|altera_merlin_slave_translator:cpu_jtag_debug_module_translator\"" { } { { "system/synthesis/system.v" "cpu_jtag_debug_module_translator" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 1160 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887293720 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_translator system:inst_cpu\|altera_merlin_slave_translator:sdram_s1_translator " "Elaborating entity \"altera_merlin_slave_translator\" for hierarchy \"system:inst_cpu\|altera_merlin_slave_translator:sdram_s1_translator\"" { } { { "system/synthesis/system.v" "sdram_s1_translator" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 1218 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887293723 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_translator system:inst_cpu\|altera_merlin_slave_translator:sysid_control_slave_translator " "Elaborating entity \"altera_merlin_slave_translator\" for hierarchy \"system:inst_cpu\|altera_merlin_slave_translator:sysid_control_slave_translator\"" { } { { "system/synthesis/system.v" "sysid_control_slave_translator" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 1276 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887293725 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_translator system:inst_cpu\|altera_merlin_slave_translator:sys_clk_timer_s1_translator " "Elaborating entity \"altera_merlin_slave_translator\" for hierarchy \"system:inst_cpu\|altera_merlin_slave_translator:sys_clk_timer_s1_translator\"" { } { { "system/synthesis/system.v" "sys_clk_timer_s1_translator" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 1334 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887293728 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_translator system:inst_cpu\|altera_merlin_slave_translator:uart_wifi_s1_translator " "Elaborating entity \"altera_merlin_slave_translator\" for hierarchy \"system:inst_cpu\|altera_merlin_slave_translator:uart_wifi_s1_translator\"" { } { { "system/synthesis/system.v" "uart_wifi_s1_translator" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 1392 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887293731 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_translator system:inst_cpu\|altera_merlin_slave_translator:pio_led_s1_translator " "Elaborating entity \"altera_merlin_slave_translator\" for hierarchy \"system:inst_cpu\|altera_merlin_slave_translator:pio_led_s1_translator\"" { } { { "system/synthesis/system.v" "pio_led_s1_translator" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 1450 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887293733 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_translator system:inst_cpu\|altera_merlin_slave_translator:pio_key_left_s1_translator " "Elaborating entity \"altera_merlin_slave_translator\" for hierarchy \"system:inst_cpu\|altera_merlin_slave_translator:pio_key_left_s1_translator\"" { } { { "system/synthesis/system.v" "pio_key_left_s1_translator" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 1508 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887293736 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_translator system:inst_cpu\|altera_merlin_slave_translator:jtag_uart_0_avalon_jtag_slave_translator " "Elaborating entity \"altera_merlin_slave_translator\" for hierarchy \"system:inst_cpu\|altera_merlin_slave_translator:jtag_uart_0_avalon_jtag_slave_translator\"" { } { { "system/synthesis/system.v" "jtag_uart_0_avalon_jtag_slave_translator" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 1624 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887293741 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_translator system:inst_cpu\|altera_merlin_slave_translator:rs232_wifi_avalon_rs232_slave_translator " "Elaborating entity \"altera_merlin_slave_translator\" for hierarchy \"system:inst_cpu\|altera_merlin_slave_translator:rs232_wifi_avalon_rs232_slave_translator\"" { } { { "system/synthesis/system.v" "rs232_wifi_avalon_rs232_slave_translator" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 1798 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887293746 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_master_agent system:inst_cpu\|altera_merlin_master_agent:cpu_instruction_master_translator_avalon_universal_master_0_agent " "Elaborating entity \"altera_merlin_master_agent\" for hierarchy \"system:inst_cpu\|altera_merlin_master_agent:cpu_instruction_master_translator_avalon_universal_master_0_agent\"" { } { { "system/synthesis/system.v" "cpu_instruction_master_translator_avalon_universal_master_0_agent" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 1870 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887293749 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_master_agent system:inst_cpu\|altera_merlin_master_agent:cpu_data_master_translator_avalon_universal_master_0_agent " "Elaborating entity \"altera_merlin_master_agent\" for hierarchy \"system:inst_cpu\|altera_merlin_master_agent:cpu_data_master_translator_avalon_universal_master_0_agent\"" { } { { "system/synthesis/system.v" "cpu_data_master_translator_avalon_universal_master_0_agent" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 1942 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887293754 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_agent system:inst_cpu\|altera_merlin_slave_agent:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent " "Elaborating entity \"altera_merlin_slave_agent\" for hierarchy \"system:inst_cpu\|altera_merlin_slave_agent:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent\"" { } { { "system/synthesis/system.v" "cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 2018 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887293757 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_burst_uncompressor system:inst_cpu\|altera_merlin_slave_agent:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent\|altera_merlin_burst_uncompressor:uncompressor " "Elaborating entity \"altera_merlin_burst_uncompressor\" for hierarchy \"system:inst_cpu\|altera_merlin_slave_agent:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent\|altera_merlin_burst_uncompressor:uncompressor\"" { } { { "system/synthesis/submodules/altera_merlin_slave_agent.sv" "uncompressor" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_slave_agent.sv" 476 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887293761 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_avalon_sc_fifo system:inst_cpu\|altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo " "Elaborating entity \"altera_avalon_sc_fifo\" for hierarchy \"system:inst_cpu\|altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo\"" { } { { "system/synthesis/system.v" "cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 2059 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887293764 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_agent system:inst_cpu\|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent " "Elaborating entity \"altera_merlin_slave_agent\" for hierarchy \"system:inst_cpu\|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent\"" { } { { "system/synthesis/system.v" "sdram_s1_translator_avalon_universal_slave_0_agent" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 2135 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887293770 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_burst_uncompressor system:inst_cpu\|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent\|altera_merlin_burst_uncompressor:uncompressor " "Elaborating entity \"altera_merlin_burst_uncompressor\" for hierarchy \"system:inst_cpu\|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent\|altera_merlin_burst_uncompressor:uncompressor\"" { } { { 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system:inst_cpu\|system_addr_router:addr_router " "Elaborating entity \"system_addr_router\" for hierarchy \"system:inst_cpu\|system_addr_router:addr_router\"" { } { { "system/synthesis/system.v" "addr_router" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 3362 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887293832 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_addr_router_default_decode system:inst_cpu\|system_addr_router:addr_router\|system_addr_router_default_decode:the_default_decode " "Elaborating entity \"system_addr_router_default_decode\" for hierarchy \"system:inst_cpu\|system_addr_router:addr_router\|system_addr_router_default_decode:the_default_decode\"" { } { { "system/synthesis/submodules/system_addr_router.sv" "the_default_decode" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_addr_router.sv" 140 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887293835 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_addr_router_001 system:inst_cpu\|system_addr_router_001:addr_router_001 " "Elaborating entity \"system_addr_router_001\" for hierarchy \"system:inst_cpu\|system_addr_router_001:addr_router_001\"" { } { { "system/synthesis/system.v" "addr_router_001" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 3378 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887293836 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_addr_router_001_default_decode system:inst_cpu\|system_addr_router_001:addr_router_001\|system_addr_router_001_default_decode:the_default_decode " "Elaborating entity \"system_addr_router_001_default_decode\" for hierarchy \"system:inst_cpu\|system_addr_router_001:addr_router_001\|system_addr_router_001_default_decode:the_default_decode\"" { } { { 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\"system:inst_cpu\|system_id_router:id_router\|system_id_router_default_decode:the_default_decode\"" { } { { "system/synthesis/submodules/system_id_router.sv" "the_default_decode" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_id_router.sv" 138 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887293843 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_id_router_001 system:inst_cpu\|system_id_router_001:id_router_001 " "Elaborating entity \"system_id_router_001\" for hierarchy \"system:inst_cpu\|system_id_router_001:id_router_001\"" { } { { "system/synthesis/system.v" "id_router_001" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 3410 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887293845 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_id_router_001_default_decode system:inst_cpu\|system_id_router_001:id_router_001\|system_id_router_001_default_decode:the_default_decode " "Elaborating entity \"system_id_router_001_default_decode\" for hierarchy \"system:inst_cpu\|system_id_router_001:id_router_001\|system_id_router_001_default_decode:the_default_decode\"" { } { { "system/synthesis/submodules/system_id_router_001.sv" "the_default_decode" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_id_router_001.sv" 138 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887293847 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_id_router_002 system:inst_cpu\|system_id_router_002:id_router_002 " "Elaborating entity \"system_id_router_002\" for hierarchy \"system:inst_cpu\|system_id_router_002:id_router_002\"" { } { { "system/synthesis/system.v" "id_router_002" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 3426 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887293849 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_id_router_002_default_decode system:inst_cpu\|system_id_router_002:id_router_002\|system_id_router_002_default_decode:the_default_decode " "Elaborating entity \"system_id_router_002_default_decode\" for hierarchy \"system:inst_cpu\|system_id_router_002:id_router_002\|system_id_router_002_default_decode:the_default_decode\"" { } { { "system/synthesis/submodules/system_id_router_002.sv" "the_default_decode" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_id_router_002.sv" 138 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887293852 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_traffic_limiter system:inst_cpu\|altera_merlin_traffic_limiter:limiter " "Elaborating entity \"altera_merlin_traffic_limiter\" for hierarchy \"system:inst_cpu\|altera_merlin_traffic_limiter:limiter\"" { } { { "system/synthesis/system.v" "limiter" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 3615 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887293872 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_burst_adapter system:inst_cpu\|altera_merlin_burst_adapter:burst_adapter " "Elaborating entity \"altera_merlin_burst_adapter\" for hierarchy \"system:inst_cpu\|altera_merlin_burst_adapter:burst_adapter\"" { } { { "system/synthesis/system.v" "burst_adapter" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 3708 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887293876 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_burst_adapter_uncompressed_only system:inst_cpu\|altera_merlin_burst_adapter:burst_adapter\|altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba " "Elaborating entity \"altera_merlin_burst_adapter_uncompressed_only\" for hierarchy \"system:inst_cpu\|altera_merlin_burst_adapter:burst_adapter\|altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.the_ba\"" { } { { "system/synthesis/submodules/altera_merlin_burst_adapter.sv" "altera_merlin_burst_adapter_uncompressed_only.the_ba" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_burst_adapter.sv" 397 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887293880 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_reset_controller system:inst_cpu\|altera_reset_controller:rst_controller " "Elaborating entity \"altera_reset_controller\" for hierarchy \"system:inst_cpu\|altera_reset_controller:rst_controller\"" { } { { "system/synthesis/system.v" "rst_controller" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 3733 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887293882 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_reset_synchronizer system:inst_cpu\|altera_reset_controller:rst_controller\|altera_reset_synchronizer:alt_rst_sync_uq1 " "Elaborating entity \"altera_reset_synchronizer\" for hierarchy \"system:inst_cpu\|altera_reset_controller:rst_controller\|altera_reset_synchronizer:alt_rst_sync_uq1\"" { } { { "system/synthesis/submodules/altera_reset_controller.v" "alt_rst_sync_uq1" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_reset_controller.v" 105 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887293884 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cmd_xbar_demux system:inst_cpu\|system_cmd_xbar_demux:cmd_xbar_demux " "Elaborating entity \"system_cmd_xbar_demux\" for hierarchy \"system:inst_cpu\|system_cmd_xbar_demux:cmd_xbar_demux\"" { } { { "system/synthesis/system.v" "cmd_xbar_demux" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 3756 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887293886 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cmd_xbar_demux_001 system:inst_cpu\|system_cmd_xbar_demux_001:cmd_xbar_demux_001 " "Elaborating entity \"system_cmd_xbar_demux_001\" for hierarchy \"system:inst_cpu\|system_cmd_xbar_demux_001:cmd_xbar_demux_001\"" { } { { "system/synthesis/system.v" "cmd_xbar_demux_001" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 3839 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887293888 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_cmd_xbar_mux system:inst_cpu\|system_cmd_xbar_mux:cmd_xbar_mux " "Elaborating entity \"system_cmd_xbar_mux\" for hierarchy \"system:inst_cpu\|system_cmd_xbar_mux:cmd_xbar_mux\"" { } { { "system/synthesis/system.v" "cmd_xbar_mux" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 3862 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887293892 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arbitrator system:inst_cpu\|system_cmd_xbar_mux:cmd_xbar_mux\|altera_merlin_arbitrator:arb " "Elaborating entity \"altera_merlin_arbitrator\" for hierarchy \"system:inst_cpu\|system_cmd_xbar_mux:cmd_xbar_mux\|altera_merlin_arbitrator:arb\"" { } { { "system/synthesis/submodules/system_cmd_xbar_mux.sv" "arb" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cmd_xbar_mux.sv" 273 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887293896 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arb_adder system:inst_cpu\|system_cmd_xbar_mux:cmd_xbar_mux\|altera_merlin_arbitrator:arb\|altera_merlin_arb_adder:adder " "Elaborating entity \"altera_merlin_arb_adder\" for hierarchy \"system:inst_cpu\|system_cmd_xbar_mux:cmd_xbar_mux\|altera_merlin_arbitrator:arb\|altera_merlin_arb_adder:adder\"" { } { { "system/synthesis/submodules/altera_merlin_arbitrator.sv" "adder" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_arbitrator.sv" 169 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887293899 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_rsp_xbar_demux system:inst_cpu\|system_rsp_xbar_demux:rsp_xbar_demux " "Elaborating entity \"system_rsp_xbar_demux\" for hierarchy \"system:inst_cpu\|system_rsp_xbar_demux:rsp_xbar_demux\"" { } { { "system/synthesis/system.v" "rsp_xbar_demux" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 3908 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887293904 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_rsp_xbar_demux_002 system:inst_cpu\|system_rsp_xbar_demux_002:rsp_xbar_demux_002 " "Elaborating entity \"system_rsp_xbar_demux_002\" for hierarchy \"system:inst_cpu\|system_rsp_xbar_demux_002:rsp_xbar_demux_002\"" { } { { "system/synthesis/system.v" "rsp_xbar_demux_002" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 3948 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887293907 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_rsp_xbar_mux system:inst_cpu\|system_rsp_xbar_mux:rsp_xbar_mux " "Elaborating entity \"system_rsp_xbar_mux\" for hierarchy \"system:inst_cpu\|system_rsp_xbar_mux:rsp_xbar_mux\"" { } { { "system/synthesis/system.v" "rsp_xbar_mux" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 4124 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887293915 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arbitrator system:inst_cpu\|system_rsp_xbar_mux:rsp_xbar_mux\|altera_merlin_arbitrator:arb " "Elaborating entity \"altera_merlin_arbitrator\" for hierarchy \"system:inst_cpu\|system_rsp_xbar_mux:rsp_xbar_mux\|altera_merlin_arbitrator:arb\"" { } { { "system/synthesis/submodules/system_rsp_xbar_mux.sv" "arb" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_rsp_xbar_mux.sv" 296 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887293918 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_rsp_xbar_mux_001 system:inst_cpu\|system_rsp_xbar_mux_001:rsp_xbar_mux_001 " "Elaborating entity \"system_rsp_xbar_mux_001\" for hierarchy \"system:inst_cpu\|system_rsp_xbar_mux_001:rsp_xbar_mux_001\"" { } { { "system/synthesis/system.v" "rsp_xbar_mux_001" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 4207 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887293921 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arbitrator system:inst_cpu\|system_rsp_xbar_mux_001:rsp_xbar_mux_001\|altera_merlin_arbitrator:arb " "Elaborating entity \"altera_merlin_arbitrator\" for hierarchy \"system:inst_cpu\|system_rsp_xbar_mux_001:rsp_xbar_mux_001\|altera_merlin_arbitrator:arb\"" { } { { "system/synthesis/submodules/system_rsp_xbar_mux_001.sv" "arb" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_rsp_xbar_mux_001.sv" 456 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887293930 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arb_adder system:inst_cpu\|system_rsp_xbar_mux_001:rsp_xbar_mux_001\|altera_merlin_arbitrator:arb\|altera_merlin_arb_adder:adder " "Elaborating entity \"altera_merlin_arb_adder\" for hierarchy \"system:inst_cpu\|system_rsp_xbar_mux_001:rsp_xbar_mux_001\|altera_merlin_arbitrator:arb\|altera_merlin_arb_adder:adder\"" { } { { "system/synthesis/submodules/altera_merlin_arbitrator.sv" "adder" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_arbitrator.sv" 169 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887293932 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_width_adapter system:inst_cpu\|altera_merlin_width_adapter:width_adapter " "Elaborating entity \"altera_merlin_width_adapter\" for hierarchy \"system:inst_cpu\|altera_merlin_width_adapter:width_adapter\"" { } { { "system/synthesis/system.v" "width_adapter" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 4264 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887293934 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_width_adapter system:inst_cpu\|altera_merlin_width_adapter:width_adapter_001 " "Elaborating entity \"altera_merlin_width_adapter\" for hierarchy \"system:inst_cpu\|altera_merlin_width_adapter:width_adapter_001\"" { } { { "system/synthesis/system.v" "width_adapter_001" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 4321 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887293938 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "system_irq_mapper system:inst_cpu\|system_irq_mapper:irq_mapper " "Elaborating entity \"system_irq_mapper\" for hierarchy \"system:inst_cpu\|system_irq_mapper:irq_mapper\"" { } { { "system/synthesis/system.v" "irq_mapper" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 4333 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1 1393887293944 ""} +{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "address_b system_cpu_traceram_lpm_dram_bdp_component 17 7 " "Port \"address_b\" on the entity instantiation of \"system_cpu_traceram_lpm_dram_bdp_component\" is connected to a signal of width 17. The formal width of the signal in the module is 7. The extra bits will be ignored." { } { { "system/synthesis/submodules/system_cpu.v" "system_cpu_traceram_lpm_dram_bdp_component" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } } 0 12020 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. The extra bits will be ignored." 0 0 "" 0 -1 1393887295694 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component"} +{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "jdo the_system_cpu_nios2_oci_itrace 38 16 " "Port \"jdo\" on the entity instantiation of \"the_system_cpu_nios2_oci_itrace\" is connected to a signal of width 38. The formal width of the signal in the module is 16. The extra bits will be ignored." { } { { "system/synthesis/submodules/system_cpu.v" "the_system_cpu_nios2_oci_itrace" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3606 0 0 } } } 0 12020 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. The extra bits will be ignored." 0 0 "" 0 -1 1393887295699 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_itrace:the_system_cpu_nios2_oci_itrace"} +{ "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_HDR" "" "Synthesized away the following node(s):" { { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_SUB_HDR" "RAM " "Synthesized away the following RAM node(s):" { { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[0\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[0\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 43 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393887296902 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a0"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[1\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[1\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 77 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393887296902 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a1"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[2\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[2\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 111 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393887296902 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a2"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[3\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[3\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 145 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393887296902 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a3"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[4\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[4\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 179 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393887296902 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a4"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[5\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[5\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 213 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393887296902 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a5"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[6\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[6\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 247 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393887296902 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a6"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[7\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[7\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 281 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393887296902 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a7"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[8\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[8\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 315 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393887296902 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a8"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[9\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[9\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 349 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393887296902 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a9"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[10\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[10\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 383 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393887296902 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a10"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[11\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[11\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 417 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393887296902 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a11"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[12\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[12\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 451 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393887296902 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a12"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[13\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[13\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 485 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393887296902 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a13"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[14\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[14\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 519 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393887296902 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a14"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[15\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[15\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 553 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393887296902 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a15"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[16\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[16\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 587 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393887296902 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a16"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[17\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[17\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 621 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393887296902 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a17"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[18\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[18\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 655 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393887296902 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a18"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[19\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[19\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 689 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393887296902 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a19"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[20\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[20\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 723 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393887296902 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a20"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[21\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[21\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 757 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393887296902 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a21"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[22\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[22\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 791 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393887296902 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a22"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[23\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[23\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 825 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393887296902 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a23"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[24\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[24\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 859 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393887296902 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a24"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[25\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[25\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 893 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393887296902 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a25"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[26\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[26\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 927 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393887296902 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a26"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[27\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[27\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 961 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393887296902 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a27"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[28\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[28\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 995 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393887296902 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a28"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[29\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[29\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 1029 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393887296902 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a29"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[30\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[30\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 1063 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393887296902 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a30"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[31\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[31\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 1097 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393887296902 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a31"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[32\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[32\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 1131 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393887296902 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a32"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[33\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[33\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 1165 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393887296902 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a33"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[34\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[34\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 1199 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393887296902 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a34"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[35\] " "Synthesized away node \"system:inst_cpu\|system_cpu:cpu\|system_cpu_nios2_oci:the_system_cpu_nios2_oci\|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im\|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component\|altsyncram:the_altsyncram\|altsyncram_0a02:auto_generated\|q_a\[35\]\"" { } { { "db/altsyncram_0a02.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/altsyncram_0a02.tdf" 1233 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3042 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3203 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 3671 0 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 10155 0 0 } } { "system/synthesis/system.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.v" 849 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 167 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "" 0 -1 1393887296902 "|de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_im:the_system_cpu_nios2_oci_im|system_cpu_traceram_lpm_dram_bdp_component_module:system_cpu_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_0a02:auto_generated|ram_block1a35"} } { } 0 14285 "Synthesized away the following %1!s! node(s):" 0 0 "" 0 -1 1393887296902 ""} } { } 0 14284 "Synthesized away the following node(s):" 0 0 "" 0 -1 1393887296902 ""} +{ "Info" "ILPMS_INFERENCING_SUMMARY" "1 " "Inferred 1 megafunctions from design logic" { { "Info" "ILPMS_LPM_ADD_SUB_INFERRED" "system:inst_cpu\|system_cpu:cpu\|Add17 lpm_add_sub " "Inferred adder/subtractor megafunction (\"lpm_add_sub\") from the following logic: \"system:inst_cpu\|system_cpu:cpu\|Add17\"" { } { { "system/synthesis/submodules/system_cpu.v" "Add17" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 8743 -1 0 } } } 0 278002 "Inferred adder/subtractor megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1 1393887302431 ""} } { } 0 278001 "Inferred %1!llu! megafunctions from design logic" 0 0 "" 0 -1 1393887302431 ""} +{ "Info" "ISGN_ELABORATION_HEADER" "system:inst_cpu\|system_cpu:cpu\|lpm_add_sub:Add17 " "Elaborated megafunction instantiation \"system:inst_cpu\|system_cpu:cpu\|lpm_add_sub:Add17\"" { } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 8743 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1 1393887302471 ""} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "system:inst_cpu\|system_cpu:cpu\|lpm_add_sub:Add17 " "Instantiated megafunction \"system:inst_cpu\|system_cpu:cpu\|lpm_add_sub:Add17\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 33 " "Parameter \"LPM_WIDTH\" = \"33\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887302471 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION DEFAULT " "Parameter \"LPM_DIRECTION\" = \"DEFAULT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887302471 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887302471 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT NO " "Parameter \"ONE_INPUT_IS_CONSTANT\" = \"NO\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1 1393887302471 ""} } { { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 8743 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1 1393887302471 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_qvi.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/add_sub_qvi.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_qvi " "Found entity 1: add_sub_qvi" { } { { "db/add_sub_qvi.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/add_sub_qvi.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1 1393887302526 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1 1393887302526 ""} +{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "2 " "2 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "" 0 -1 1393887303638 ""} +{ "Warning" "WMLS_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC_HDR" "" "The following nodes have both tri-state and non-tri-state drivers" { { "Warning" "WMLS_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC" "GPIO_0\[33\] " "Inserted always-enabled tri-state buffer between \"GPIO_0\[33\]\" and its non-tri-state driver." { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13035 "Inserted always-enabled tri-state buffer between \"%1!s!\" and its non-tri-state driver." 0 0 "" 0 -1 1393887303858 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC" "GPIO_1\[0\] " "Inserted always-enabled tri-state buffer between \"GPIO_1\[0\]\" and its non-tri-state driver." { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13035 "Inserted always-enabled tri-state buffer between \"%1!s!\" and its non-tri-state driver." 0 0 "" 0 -1 1393887303858 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_ENABLED_TRI_AFTER_LOGIC" "GPIO_1\[33\] " "Inserted always-enabled tri-state buffer between \"GPIO_1\[33\]\" and its non-tri-state driver." { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13035 "Inserted always-enabled tri-state buffer between \"%1!s!\" and its non-tri-state driver." 0 0 "" 0 -1 1393887303858 ""} } { } 0 13034 "The following nodes have both tri-state and non-tri-state drivers" 0 0 "" 0 -1 1393887303858 ""} +{ "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI_HDR" "" "The following bidir pins have no drivers" { { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[0\] " "Bidir \"GPIO_0\[0\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393887303858 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[1\] " "Bidir \"GPIO_0\[1\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393887303858 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[2\] " "Bidir \"GPIO_0\[2\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393887303858 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[3\] " "Bidir \"GPIO_0\[3\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393887303858 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[4\] " "Bidir \"GPIO_0\[4\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393887303858 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[5\] " "Bidir \"GPIO_0\[5\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393887303858 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[6\] " "Bidir \"GPIO_0\[6\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393887303858 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[7\] " "Bidir \"GPIO_0\[7\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393887303858 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[8\] " "Bidir \"GPIO_0\[8\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393887303858 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[9\] " "Bidir \"GPIO_0\[9\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393887303858 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[10\] " "Bidir \"GPIO_0\[10\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393887303858 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[11\] " "Bidir \"GPIO_0\[11\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393887303858 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[12\] " "Bidir \"GPIO_0\[12\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393887303858 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[13\] " "Bidir \"GPIO_0\[13\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393887303858 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[14\] " "Bidir \"GPIO_0\[14\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393887303858 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[15\] " "Bidir \"GPIO_0\[15\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393887303858 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[16\] " "Bidir \"GPIO_0\[16\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393887303858 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[17\] " "Bidir \"GPIO_0\[17\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393887303858 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[18\] " "Bidir \"GPIO_0\[18\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393887303858 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[19\] " "Bidir \"GPIO_0\[19\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393887303858 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[20\] " "Bidir \"GPIO_0\[20\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393887303858 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[21\] " "Bidir \"GPIO_0\[21\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393887303858 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[22\] " "Bidir \"GPIO_0\[22\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393887303858 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[23\] " "Bidir \"GPIO_0\[23\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393887303858 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[24\] " "Bidir \"GPIO_0\[24\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393887303858 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[25\] " "Bidir \"GPIO_0\[25\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393887303858 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[26\] " "Bidir \"GPIO_0\[26\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393887303858 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[27\] " "Bidir \"GPIO_0\[27\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393887303858 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[28\] " "Bidir \"GPIO_0\[28\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393887303858 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[29\] " "Bidir \"GPIO_0\[29\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393887303858 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[30\] " "Bidir \"GPIO_0\[30\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393887303858 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[32\] " "Bidir \"GPIO_0\[32\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393887303858 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[1\] " "Bidir \"GPIO_1\[1\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393887303858 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[2\] " "Bidir \"GPIO_1\[2\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393887303858 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[3\] " "Bidir \"GPIO_1\[3\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393887303858 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[4\] " "Bidir \"GPIO_1\[4\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393887303858 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[5\] " "Bidir \"GPIO_1\[5\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393887303858 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[6\] " "Bidir \"GPIO_1\[6\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393887303858 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[7\] " "Bidir \"GPIO_1\[7\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393887303858 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[8\] " "Bidir \"GPIO_1\[8\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393887303858 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[9\] " "Bidir \"GPIO_1\[9\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393887303858 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[10\] " "Bidir \"GPIO_1\[10\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393887303858 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[11\] " "Bidir \"GPIO_1\[11\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393887303858 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[12\] " "Bidir \"GPIO_1\[12\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393887303858 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[13\] " "Bidir \"GPIO_1\[13\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393887303858 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[14\] " "Bidir \"GPIO_1\[14\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393887303858 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[15\] " "Bidir \"GPIO_1\[15\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393887303858 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[16\] " "Bidir \"GPIO_1\[16\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393887303858 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[17\] " "Bidir \"GPIO_1\[17\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393887303858 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[18\] " "Bidir \"GPIO_1\[18\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393887303858 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[19\] " "Bidir \"GPIO_1\[19\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393887303858 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[20\] " "Bidir \"GPIO_1\[20\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393887303858 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[21\] " "Bidir \"GPIO_1\[21\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393887303858 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[22\] " "Bidir \"GPIO_1\[22\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393887303858 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[23\] " "Bidir \"GPIO_1\[23\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393887303858 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[24\] " "Bidir \"GPIO_1\[24\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393887303858 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[25\] " "Bidir \"GPIO_1\[25\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393887303858 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[26\] " "Bidir \"GPIO_1\[26\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393887303858 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[27\] " "Bidir \"GPIO_1\[27\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393887303858 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[28\] " "Bidir \"GPIO_1\[28\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393887303858 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[29\] " "Bidir \"GPIO_1\[29\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393887303858 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[30\] " "Bidir \"GPIO_1\[30\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393887303858 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[32\] " "Bidir \"GPIO_1\[32\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393887303858 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_0\[31\] " "Bidir \"GPIO_0\[31\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393887303858 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "GPIO_1\[31\] " "Bidir \"GPIO_1\[31\]\" has no driver" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "" 0 -1 1393887303858 ""} } { } 0 13039 "The following bidir pins have no drivers" 0 0 "" 0 -1 1393887303858 ""} +{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" { } { { "system/synthesis/submodules/system_sdram.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_sdram.v" 440 -1 0 } } { "system/synthesis/submodules/system_sdram.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_sdram.v" 354 -1 0 } } { "system/synthesis/submodules/altera_reset_synchronizer.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_reset_synchronizer.v" 62 -1 0 } } { "system/synthesis/submodules/system_sdram.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_sdram.v" 304 -1 0 } } { "system/synthesis/submodules/altera_merlin_slave_translator.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_slave_translator.sv" 277 -1 0 } } { "system/synthesis/submodules/system_jtag_uart_0.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_jtag_uart_0.v" 558 -1 0 } } { "alt_jtag_atlantic.v" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/alt_jtag_atlantic.v" 291 -1 0 } } { "system/synthesis/submodules/system_uart_mc.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_mc.v" 89 -1 0 } } { "system/synthesis/submodules/altera_merlin_arbitrator.sv" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_arbitrator.sv" 203 -1 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 5563 -1 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 5963 -1 0 } } { "system/synthesis/submodules/system_jtag_uart_0.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_jtag_uart_0.v" 603 -1 0 } } { "system/synthesis/submodules/system_uart_mc.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_mc.v" 105 -1 0 } } { "alt_jtag_atlantic.v" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/alt_jtag_atlantic.v" 224 -1 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 5995 -1 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 9343 -1 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 9492 -1 0 } } { "system/synthesis/submodules/system_cpu.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_cpu.v" 982 -1 0 } } { "system/synthesis/submodules/system_uart_mc.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_mc.v" 87 -1 0 } } { "system/synthesis/submodules/system_uart_wifi.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_wifi.v" 88 -1 0 } } { "system/synthesis/submodules/system_uart_wifi.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_wifi.v" 87 -1 0 } } { "system/synthesis/submodules/system_uart_mc.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_mc.v" 88 -1 0 } } { "system/synthesis/submodules/system_sys_clk_timer.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_sys_clk_timer.v" 166 -1 0 } } { "system/synthesis/submodules/system_sys_clk_timer.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_sys_clk_timer.v" 175 -1 0 } } { "system/synthesis/submodules/system_uart_wifi.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/system_uart_wifi.v" 891 -1 0 } } } 0 13000 "Registers with preset signals will power-up high" 0 0 "" 0 -1 1393887304016 ""} +{ "Info" "IMLS_MLS_DEV_CLRN_SETS_REGISTERS" "" "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" { } { } 0 13003 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "" 0 -1 1393887304017 ""} +{ "Warning" "WMLS_MLS_ENABLED_OE" "" "TRI or OPNDRN buffers permanently enabled" { { "Warning" "WMLS_MLS_NODE_NAME" "GPIO_0\[33\]~synth " "Node \"GPIO_0\[33\]~synth\"" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 -1 0 } } } 0 13010 "Node \"%1!s!\"" 0 0 "" 0 -1 1393887306180 ""} { "Warning" "WMLS_MLS_NODE_NAME" "GPIO_1\[0\]~synth " "Node \"GPIO_1\[0\]~synth\"" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13010 "Node \"%1!s!\"" 0 0 "" 0 -1 1393887306180 ""} { "Warning" "WMLS_MLS_NODE_NAME" "GPIO_1\[33\]~synth " "Node \"GPIO_1\[33\]~synth\"" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 -1 0 } } } 0 13010 "Node \"%1!s!\"" 0 0 "" 0 -1 1393887306180 ""} } { } 0 13009 "TRI or OPNDRN buffers permanently enabled" 0 0 "" 0 -1 1393887306180 ""} +{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "DRAM_CKE VCC " "Pin \"DRAM_CKE\" is stuck at VCC" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 62 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1 1393887306180 "|de0_nano_system|DRAM_CKE"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "" 0 -1 1393887306180 ""} +{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING_ON_PARTITION" "Top " "Timing-Driven Synthesis is running on partition \"Top\"" { } { } 0 286031 "Timing-Driven Synthesis is running on partition \"%1!s!\"" 0 0 "" 0 -1 1393887306753 ""} +{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "378 " "378 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "" 0 -1 1393887309491 ""} +{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "1 0 1 0 0 " "Adding 1 node(s), including 0 DDIO, 1 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "" 0 -1 1393887310901 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "" 0 -1 1393887310901 ""} +{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "1 " "Design contains 1 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[0\] " "No output dependent on input pin \"KEY\[0\]\"" { } { { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 74 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 -1 1393887311547 "|de0_nano_system|KEY[0]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0 -1 1393887311547 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "5738 " "Implemented 5738 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "10 " "Implemented 10 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "" 0 -1 1393887311549 ""} { "Info" "ICUT_CUT_TM_OPINS" "32 " "Implemented 32 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "" 0 -1 1393887311549 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "84 " "Implemented 84 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "" 0 -1 1393887311549 ""} { "Info" "ICUT_CUT_TM_LCELLS" "5343 " "Implemented 5343 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "" 0 -1 1393887311549 ""} { "Info" "ICUT_CUT_TM_RAMS" "263 " "Implemented 263 RAM segments" { } { } 0 21064 "Implemented %1!d! RAM segments" 0 0 "" 0 -1 1393887311549 ""} { "Info" "ICUT_CUT_TM_PLLS" "1 " "Implemented 1 PLLs" { } { } 0 21065 "Implemented %1!d! PLLs" 0 0 "" 0 -1 1393887311549 ""} { "Info" "ICUT_CUT_TM_DSP_ELEM" "4 " "Implemented 4 DSP elements" { } { } 0 21062 "Implemented %1!d! DSP elements" 0 0 "" 0 -1 1393887311549 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1 1393887311549 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 130 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 130 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "644 " "Peak virtual memory: 644 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1 1393887311686 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 03 15:55:11 2014 " "Processing ended: Mon Mar 03 15:55:11 2014" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1 1393887311686 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:23 " "Elapsed time: 00:00:23" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1 1393887311686 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:22 " "Total CPU time (on all processors): 00:00:22" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1 1393887311686 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1 1393887311686 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1 1393887312927 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 64-Bit " "Running Quartus II 64-Bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Full Version " "Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1 1393887312928 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 03 15:55:12 2014 " "Processing started: Mon Mar 03 15:55:12 2014" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1 1393887312928 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1 1393887312928 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off de0_nano_system -c de0_nano_system " "Command: quartus_fit --read_settings_files=off --write_settings_files=off de0_nano_system -c de0_nano_system" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1 1393887312928 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." { } { } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "" 0 -1 1393887313086 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "de0_nano_system EP4CE22F17C6 " "Selected device EP4CE22F17C6 for design \"de0_nano_system\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 -1 1393887313375 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "" 0 -1 1393887313430 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "" 0 -1 1393887313431 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "" 0 -1 1393887313431 ""} +{ "Info" "ICUT_CUT_PLL_COMPUTATION_SUCCESS" "pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|pll1 Cyclone IV E PLL " "Implemented PLL \"pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|pll1\" as Cyclone IV E PLL type" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|wire_pll1_clk\[0\] 2 1 0 0 " "Implementing clock multiplication of 2, clock division of 1, and phase shift of 0 degrees (0 ps) for pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|wire_pll1_clk\[0\] port" { } { { "db/pll_sys_altpll.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/pll_sys_altpll.v" 45 -1 0 } } { "" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 6291 8336 9085 0} } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "" 0 -1 1393887313479 ""} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|wire_pll1_clk\[1\] 2 1 -54 -1500 " "Implementing clock multiplication of 2, clock division of 1, and phase shift of -54 degrees (-1500 ps) for pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|wire_pll1_clk\[1\] port" { } { { "db/pll_sys_altpll.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/pll_sys_altpll.v" 45 -1 0 } } { "" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 6292 8336 9085 0} } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "" 0 -1 1393887313479 ""} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|wire_pll1_clk\[2\] 1 5 0 0 " "Implementing clock multiplication of 1, clock division of 5, and phase shift of 0 degrees (0 ps) for pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|wire_pll1_clk\[2\] port" { } { { "db/pll_sys_altpll.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/pll_sys_altpll.v" 45 -1 0 } } { "" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 6293 8336 9085 0} } } } } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "" 0 -1 1393887313479 ""} } { { "db/pll_sys_altpll.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/pll_sys_altpll.v" 45 -1 0 } } { "" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 6291 8336 9085 0} } } } } 0 15535 "Implemented %3!s! \"%1!s!\" as %2!s! PLL type" 0 0 "" 0 -1 1393887313479 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0 -1 1393887313687 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE10F17C6 " "Device EP4CE10F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "" 0 -1 1393887313977 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE6F17C6 " "Device EP4CE6F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "" 0 -1 1393887313977 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE15F17C6 " "Device EP4CE15F17C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "" 0 -1 1393887313977 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 -1 1393887313977 ""} +{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ C1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location C1" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 16681 8336 9085 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1 1393887313992 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ D2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location D2" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 16683 8336 9085 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1 1393887313992 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ H1 " "Pin ~ALTERA_DCLK~ is reserved at location H1" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 16685 8336 9085 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1 1393887313992 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ H2 " "Pin ~ALTERA_DATA0~ is reserved at location H2" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 16687 8336 9085 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1 1393887313992 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ F16 " "Pin ~ALTERA_nCEO~ is reserved at location F16" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 16689 8336 9085 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1 1393887313992 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 -1 1393887313992 ""} +{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "" 0 -1 1393887313994 ""} +{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." { } { } 0 176045 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "" 0 -1 1393887314050 ""} +{ "Info" "ISTA_SDC_STATEMENT_PARENT" "" "Evaluating HDL-embedded SDC commands" { { "Info" "ISTA_SDC_STATEMENT_ENTITY" "alt_jtag_atlantic " "Entity alt_jtag_atlantic" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate1*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate1*\}\] " { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393887315766 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393887315766 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393887315766 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393887315766 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393887315766 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393887315766 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393887315766 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393887315766 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393887315766 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|read1*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|read1*\}\] " { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393887315766 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read_req\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read_req\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393887315766 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393887315766 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|tck_t_dav\}\] " "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|tck_t_dav\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393887315766 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|user_saw_rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid0*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|user_saw_rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid0*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393887315766 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393887315766 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393887315766 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393887315766 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393887315766 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393887315766 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393887315766 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393887315766 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393887315766 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write1*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write1*\}\] " { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393887315766 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_ena*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_ena*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393887315766 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_pause*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_pause*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393887315766 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_valid\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_valid\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393887315766 ""} } { } 0 332165 "Entity %1!s!" 0 0 "" 0 -1 1393887315766 ""} { "Info" "ISTA_SDC_STATEMENT_ENTITY" "altera_std_synchronizer " "Entity altera_std_synchronizer" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -to \[get_keepers \{*altera_std_synchronizer:*\|din_s1\}\] " "set_false_path -to \[get_keepers \{*altera_std_synchronizer:*\|din_s1\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393887315766 ""} } { } 0 332165 "Entity %1!s!" 0 0 "" 0 -1 1393887315766 ""} { "Info" "ISTA_SDC_STATEMENT_ENTITY" "sld_jtag_hub " "Entity sld_jtag_hub" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "create_clock -period 10MHz -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] " "create_clock -period 10MHz -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393887315766 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_clock_groups -asynchronous -group \{altera_reserved_tck\} " "set_clock_groups -asynchronous -group \{altera_reserved_tck\}" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393887315766 ""} } { } 0 332165 "Entity %1!s!" 0 0 "" 0 -1 1393887315766 ""} } { } 0 332164 "Evaluating HDL-embedded SDC commands" 0 0 "" 0 -1 1393887315766 ""} +{ "Info" "ISTA_SDC_FOUND" "de0_nano_system.sdc " "Reading SDC File: 'de0_nano_system.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "" 0 -1 1393887316054 ""} +{ "Warning" "WSTA_OVERWRITING_EXISTING_CLOCK" "altera_reserved_tck " "Overwriting existing clock: altera_reserved_tck" { } { } 0 332043 "Overwriting existing clock: %1!s!" 0 0 "" 0 -1 1393887316069 ""} +{ "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "Deriving PLL clocks " "Deriving PLL clocks" { { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -duty_cycle 50.00 -name \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} " "create_generated_clock -source \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -duty_cycle 50.00 -name \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}" { } { } 0 332110 "%1!s!" 0 0 "" 0 -1 1393887316070 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -phase -54.00 -duty_cycle 50.00 -name \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} " "create_generated_clock -source \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -phase -54.00 -duty_cycle 50.00 -name \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}" { } { } 0 332110 "%1!s!" 0 0 "" 0 -1 1393887316070 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 5 -duty_cycle 50.00 -name \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} " "create_generated_clock -source \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 5 -duty_cycle 50.00 -name \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\]\}" { } { } 0 332110 "%1!s!" 0 0 "" 0 -1 1393887316070 ""} } { } 0 332110 "%1!s!" 0 0 "" 0 -1 1393887316070 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_CALL_IS_DELAYED" "" "Clock uncertainty is not calculated until you update the timing netlist." { } { } 0 332151 "Clock uncertainty is not calculated until you update the timing netlist." 0 0 "" 0 -1 1393887316070 ""} +{ "Info" "ISTA_SDC_FOUND" "system/synthesis/submodules/altera_reset_controller.sdc " "Reading SDC File: 'system/synthesis/submodules/altera_reset_controller.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "" 0 -1 1393887316078 ""} +{ "Info" "ISTA_SDC_FOUND" "system/synthesis/submodules/system_cpu.sdc " "Reading SDC File: 'system/synthesis/submodules/system_cpu.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "" 0 -1 1393887316105 ""} +{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "" 0 -1 1393887316295 ""} +{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "" 0 -1 1393887316296 ""} +{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 5 clocks " "Found 5 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "" 0 -1 1393887316297 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "" 0 -1 1393887316297 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 100.000 altera_reserved_tck " " 100.000 altera_reserved_tck" { } { } 0 332111 "%1!s!" 0 0 "" 0 -1 1393887316297 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 20.000 CLOCK_50 " " 20.000 CLOCK_50" { } { } 0 332111 "%1!s!" 0 0 "" 0 -1 1393887316297 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 10.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 10.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\]" { } { } 0 332111 "%1!s!" 0 0 "" 0 -1 1393887316297 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 10.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[1\] " " 10.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[1\]" { } { } 0 332111 "%1!s!" 0 0 "" 0 -1 1393887316297 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 100.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 100.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\]" { } { } 0 332111 "%1!s!" 0 0 "" 0 -1 1393887316297 ""} } { } 0 332111 "%1!s!" 0 0 "" 0 -1 1393887316297 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C0 of PLL_4) " "Automatically promoted node pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|wire_pll1_clk\[0\] (placed in counter C0 of PLL_4)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G18 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G18" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1 1393887316756 ""} } { { "db/pll_sys_altpll.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/pll_sys_altpll.v" 80 -1 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { pll_sys:inst_pll_sys|altpll:altpll_component|pll_sys_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 6291 8336 9085 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1 1393887316756 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|wire_pll1_clk\[1\] (placed in counter C2 of PLL_4) " "Automatically promoted node pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|wire_pll1_clk\[1\] (placed in counter C2 of PLL_4)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G17 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G17" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1 1393887316756 ""} } { { "db/pll_sys_altpll.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/pll_sys_altpll.v" 80 -1 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { pll_sys:inst_pll_sys|altpll:altpll_component|pll_sys_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 6291 8336 9085 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1 1393887316756 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|wire_pll1_clk\[2\] (placed in counter C1 of PLL_4) " "Automatically promoted node pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|wire_pll1_clk\[2\] (placed in counter C1 of PLL_4)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G19 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G19" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1 1393887316756 ""} } { { "db/pll_sys_altpll.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/pll_sys_altpll.v" 80 -1 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { pll_sys:inst_pll_sys|altpll:altpll_component|pll_sys_altpll:auto_generated|wire_pll1_clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 6291 8336 9085 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1 1393887316756 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "altera_internal_jtag~TCKUTAP " "Automatically promoted node altera_internal_jtag~TCKUTAP " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1 1393887316756 ""} } { { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 16157 8336 9085 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1 1393887316756 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "system:inst_cpu\|altera_reset_controller:rst_controller\|altera_reset_synchronizer:alt_rst_sync_uq1\|altera_reset_synchronizer_int_chain_out " "Automatically promoted node system:inst_cpu\|altera_reset_controller:rst_controller\|altera_reset_synchronizer:alt_rst_sync_uq1\|altera_reset_synchronizer_int_chain_out " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1 1393887316756 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr\|counter_reg_bit\[6\] " "Destination node system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr\|counter_reg_bit\[6\]" { } { { "db/cntr_0ab.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/cntr_0ab.tdf" 68 17 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 6532 8336 9085 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "" 0 -1 1393887316756 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr\|counter_reg_bit\[5\] " "Destination node system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr\|counter_reg_bit\[5\]" { } { { "db/cntr_0ab.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/cntr_0ab.tdf" 68 17 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 6533 8336 9085 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "" 0 -1 1393887316756 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr\|counter_reg_bit\[4\] " "Destination node system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr\|counter_reg_bit\[4\]" { } { { "db/cntr_0ab.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/cntr_0ab.tdf" 68 17 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 6534 8336 9085 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "" 0 -1 1393887316756 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr\|counter_reg_bit\[3\] " "Destination node system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr\|counter_reg_bit\[3\]" { } { { "db/cntr_0ab.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/cntr_0ab.tdf" 68 17 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 6535 8336 9085 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "" 0 -1 1393887316756 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr\|counter_reg_bit\[2\] " "Destination node system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr\|counter_reg_bit\[2\]" { } { { "db/cntr_0ab.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/cntr_0ab.tdf" 68 17 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 6536 8336 9085 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "" 0 -1 1393887316756 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr\|counter_reg_bit\[1\] " "Destination node system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr\|counter_reg_bit\[1\]" { } { { "db/cntr_0ab.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/cntr_0ab.tdf" 68 17 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 6537 8336 9085 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "" 0 -1 1393887316756 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr\|counter_reg_bit\[0\] " "Destination node system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_0ab:wr_ptr\|counter_reg_bit\[0\]" { } { { "db/cntr_0ab.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/cntr_0ab.tdf" 68 17 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 6538 8336 9085 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "" 0 -1 1393887316756 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_ca7:usedw_counter\|counter_reg_bit\[6\] " "Destination node system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_ca7:usedw_counter\|counter_reg_bit\[6\]" { } { { "db/cntr_ca7.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/cntr_ca7.tdf" 69 17 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_ca7:usedw_counter|counter_reg_bit[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 6555 8336 9085 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "" 0 -1 1393887316756 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_ca7:usedw_counter\|counter_reg_bit\[5\] " "Destination node system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_ca7:usedw_counter\|counter_reg_bit\[5\]" { } { { "db/cntr_ca7.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/cntr_ca7.tdf" 69 17 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_ca7:usedw_counter|counter_reg_bit[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 6556 8336 9085 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "" 0 -1 1393887316756 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_ca7:usedw_counter\|counter_reg_bit\[4\] " "Destination node system:inst_cpu\|system_rs232_wifi:rs232_wifi\|altera_up_rs232_out_serializer:RS232_Out_Serializer\|altera_up_sync_fifo:RS232_Out_FIFO\|scfifo:Sync_FIFO\|scfifo_a341:auto_generated\|a_dpfifo_tq31:dpfifo\|cntr_ca7:usedw_counter\|counter_reg_bit\[4\]" { } { { "db/cntr_ca7.tdf" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/cntr_ca7.tdf" 69 17 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_ca7:usedw_counter|counter_reg_bit[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 6557 8336 9085 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "" 0 -1 1393887316756 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_LIMITED_TO_SUB" "10 " "Non-global destination nodes limited to 10 nodes" { } { } 0 176358 "Non-global destination nodes limited to %1!d! nodes" 0 0 "" 0 -1 1393887316756 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0 -1 1393887316756 ""} } { { "system/synthesis/submodules/altera_reset_synchronizer.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_reset_synchronizer.v" 62 -1 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 695 8336 9085 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1 1393887316756 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "sld_hub:auto_hub\|sld_jtag_hub:\\jtag_hub_gen:sld_jtag_hub_inst\|clr_reg " "Automatically promoted node sld_hub:auto_hub\|sld_jtag_hub:\\jtag_hub_gen:sld_jtag_hub_inst\|clr_reg " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1 1393887316758 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "sld_hub:auto_hub\|sld_jtag_hub:\\jtag_hub_gen:sld_jtag_hub_inst\|clr_reg~_wirecell " "Destination node sld_hub:auto_hub\|sld_jtag_hub:\\jtag_hub_gen:sld_jtag_hub_inst\|clr_reg~_wirecell" { } { { "sld_jtag_hub.vhd" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/sld_jtag_hub.vhd" 335 -1 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg~_wirecell } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 16541 8336 9085 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "" 0 -1 1393887316758 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0 -1 1393887316758 ""} } { { "sld_jtag_hub.vhd" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/sld_jtag_hub.vhd" 335 -1 0 } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "sld_hub:auto_hub\|sld_jtag_hub:\\jtag_hub_gen:sld_jtag_hub_inst\|clr_reg" } } } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 16288 8336 9085 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1 1393887316758 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "sld_hub:auto_hub\|sld_jtag_hub:\\jtag_hub_gen:sld_jtag_hub_inst\|sld_shadow_jsm:shadow_jsm\|state\[0\] " "Automatically promoted node sld_hub:auto_hub\|sld_jtag_hub:\\jtag_hub_gen:sld_jtag_hub_inst\|sld_shadow_jsm:shadow_jsm\|state\[0\] " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1 1393887316759 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "sld_hub:auto_hub\|sld_jtag_hub:\\jtag_hub_gen:sld_jtag_hub_inst\|sld_shadow_jsm:shadow_jsm\|state~0 " "Destination node sld_hub:auto_hub\|sld_jtag_hub:\\jtag_hub_gen:sld_jtag_hub_inst\|sld_shadow_jsm:shadow_jsm\|state~0" { } { { "sld_jtag_hub.vhd" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/sld_jtag_hub.vhd" 1076 -1 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 16422 8336 9085 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "" 0 -1 1393887316759 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "sld_hub:auto_hub\|sld_jtag_hub:\\jtag_hub_gen:sld_jtag_hub_inst\|sld_shadow_jsm:shadow_jsm\|state~1 " "Destination node sld_hub:auto_hub\|sld_jtag_hub:\\jtag_hub_gen:sld_jtag_hub_inst\|sld_shadow_jsm:shadow_jsm\|state~1" { } { { "sld_jtag_hub.vhd" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/sld_jtag_hub.vhd" 1076 -1 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state~1 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 16423 8336 9085 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "" 0 -1 1393887316759 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "sld_hub:auto_hub\|sld_jtag_hub:\\jtag_hub_gen:sld_jtag_hub_inst\|sld_shadow_jsm:shadow_jsm\|state\[0\]~_wirecell " "Destination node sld_hub:auto_hub\|sld_jtag_hub:\\jtag_hub_gen:sld_jtag_hub_inst\|sld_shadow_jsm:shadow_jsm\|state\[0\]~_wirecell" { } { { "sld_jtag_hub.vhd" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/sld_jtag_hub.vhd" 1090 -1 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0]~_wirecell } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 16542 8336 9085 0} } } } } 0 176357 "Destination node %1!s!" 0 0 "" 0 -1 1393887316759 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0 -1 1393887316759 ""} } { { "sld_jtag_hub.vhd" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/sld_jtag_hub.vhd" 1090 -1 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 16181 8336 9085 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1 1393887316759 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "system:inst_cpu\|altera_reset_controller:rst_controller\|merged_reset~0 " "Automatically promoted node system:inst_cpu\|altera_reset_controller:rst_controller\|merged_reset~0 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1 1393887316759 ""} } { { "system/synthesis/submodules/altera_reset_controller.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_reset_controller.v" 61 -1 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { system:inst_cpu|altera_reset_controller:rst_controller|merged_reset~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 7558 8336 9085 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1 1393887316759 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "" 0 -1 1393887318320 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1 1393887318334 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1 1393887318334 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "" 0 -1 1393887318350 ""} +{ "Warning" "WFSAC_FSAC_IGNORED_FAST_REGISTER_IO_ASSIGNMENTS" "" "Ignoring invalid fast I/O register assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 176250 "Ignoring invalid fast I/O register assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "" 0 -1 1393887321013 ""} +{ "Warning" "WFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS" "" "Ignoring some wildcard destinations of fast I/O register assignments" { { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Enable Register ON oe " "Wildcard assignment \"Fast Output Enable Register=ON\" to \"oe\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1393887321014 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[9\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[9\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1393887321014 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[8\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[8\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1393887321014 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[7\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[7\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1393887321014 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[6\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[6\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1393887321014 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[5\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[5\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1393887321014 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[4\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[4\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1393887321014 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[3\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[3\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1393887321014 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[2\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[2\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1393887321014 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[1\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[1\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1393887321014 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[15\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[15\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1393887321014 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[14\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[14\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1393887321014 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[13\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[13\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1393887321014 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[12\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[12\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1393887321014 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[11\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[11\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1393887321014 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[10\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[10\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1393887321014 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_data\[0\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_data\[0\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1393887321014 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_cmd\[2\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_cmd\[2\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1393887321014 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_cmd\[1\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_cmd\[1\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1393887321014 ""} { "Info" "IFSAC_FSAC_INVALID_WILD_CARD_FAST_REGISTER_IO_ASSIGNMENTS_SUBMSG" "Fast Output Register ON m_cmd\[0\] " "Wildcard assignment \"Fast Output Register=ON\" to \"m_cmd\[0\]\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" { } { } 0 176252 "Wildcard assignment \"%1!s!=%2!s!\" to \"%3!s!\" matches multiple destination nodes -- some destinations are not valid targets for this assignment" 0 0 "" 0 -1 1393887321014 ""} } { } 0 176251 "Ignoring some wildcard destinations of fast I/O register assignments" 0 0 "" 0 -1 1393887321014 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "" 0 -1 1393887321015 ""} +{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "" 0 -1 1393887321029 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "" 0 -1 1393887322673 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NUM_REGISTERS_PACKED_INTO_ATOM_TYPE" "10 EC " "Packed 10 registers into blocks of type EC" { } { } 1 176218 "Packed %1!d! registers into blocks of type %2!s!" 0 0 "" 0 -1 1393887324220 ""} { "Extra Info" "IFSAC_NUM_REGISTERS_PACKED_INTO_ATOM_TYPE" "64 Embedded multiplier block " "Packed 64 registers into blocks of type Embedded multiplier block" { } { } 1 176218 "Packed %1!d! registers into blocks of type %2!s!" 0 0 "" 0 -1 1393887324220 ""} { "Extra Info" "IFSAC_NUM_REGISTERS_PACKED_INTO_ATOM_TYPE" "16 I/O Input Buffer " "Packed 16 registers into blocks of type I/O Input Buffer" { } { } 1 176218 "Packed %1!d! registers into blocks of type %2!s!" 0 0 "" 0 -1 1393887324220 ""} { "Extra Info" "IFSAC_NUM_REGISTERS_PACKED_INTO_ATOM_TYPE" "53 I/O Output Buffer " "Packed 53 registers into blocks of type I/O Output Buffer" { } { } 1 176218 "Packed %1!d! registers into blocks of type %2!s!" 0 0 "" 0 -1 1393887324220 ""} { "Extra Info" "IFSAC_NUM_REGISTERS_DUPLICATED" "66 " "Created 66 register duplicates" { } { } 1 176220 "Created %1!d! register duplicates" 0 0 "" 0 -1 1393887324220 ""} } { } 0 176235 "Finished register packing" 0 0 "" 0 -1 1393887324220 ""} +{ "Warning" "WCUT_PLL_CLK_FEEDS_NON_DEDICATED_IO" "pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|pll1 clk\[1\] DRAM_CLK~output " "PLL \"pll_sys:inst_pll_sys\|altpll:altpll_component\|pll_sys_altpll:auto_generated\|pll1\" output port clk\[1\] feeds output pin \"DRAM_CLK~output\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" { } { { "db/pll_sys_altpll.v" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/db/pll_sys_altpll.v" 45 -1 0 } } { "altpll.tdf" "" { Text "c:/altera/12.1sp1/quartus/libraries/megafunctions/altpll.tdf" 897 0 0 } } { "pll_sys.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/pll_sys.vhd" 154 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 152 0 0 } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 61 0 0 } } } 0 15064 "PLL \"%1!s!\" output port %2!s! feeds output pin \"%3!s!\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" 0 0 "" 0 -1 1393887324371 ""} +{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_CS_N " "Node \"ADC_CS_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393887324505 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SADDR " "Node \"ADC_SADDR\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SADDR" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393887324505 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SCLK " "Node \"ADC_SCLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393887324505 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ADC_SDAT " "Node \"ADC_SDAT\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ADC_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393887324505 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0_IN\[0\] " "Node \"GPIO_0_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393887324505 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_0_IN\[1\] " "Node \"GPIO_0_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393887324505 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1_IN\[0\] " "Node \"GPIO_1_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393887324505 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_1_IN\[1\] " "Node \"GPIO_1_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393887324505 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[0\] " "Node \"GPIO_2\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393887324505 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[10\] " "Node \"GPIO_2\[10\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2\[10\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393887324505 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[11\] " "Node \"GPIO_2\[11\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2\[11\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393887324505 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[12\] " "Node \"GPIO_2\[12\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2\[12\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393887324505 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[1\] " "Node \"GPIO_2\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393887324505 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[2\] " "Node \"GPIO_2\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393887324505 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[3\] " "Node \"GPIO_2\[3\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2\[3\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393887324505 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[4\] " "Node \"GPIO_2\[4\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2\[4\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393887324505 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[5\] " "Node \"GPIO_2\[5\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2\[5\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393887324505 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[6\] " "Node \"GPIO_2\[6\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2\[6\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393887324505 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[7\] " "Node \"GPIO_2\[7\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2\[7\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393887324505 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[8\] " "Node \"GPIO_2\[8\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2\[8\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393887324505 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2\[9\] " "Node \"GPIO_2\[9\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2\[9\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393887324505 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[0\] " "Node \"GPIO_2_IN\[0\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[0\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393887324505 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[1\] " "Node \"GPIO_2_IN\[1\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[1\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393887324505 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "GPIO_2_IN\[2\] " "Node \"GPIO_2_IN\[2\]\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_2_IN\[2\]" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393887324505 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "G_SENSOR_CS_N " "Node \"G_SENSOR_CS_N\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "G_SENSOR_CS_N" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393887324505 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "G_SENSOR_INT " "Node \"G_SENSOR_INT\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "G_SENSOR_INT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393887324505 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SCLK " "Node \"I2C_SCLK\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "I2C_SCLK" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393887324505 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "I2C_SDAT " "Node \"I2C_SDAT\" is assigned to location or region, but does not exist in design" { } { { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } } } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "" 0 -1 1393887324505 ""} } { } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "" 0 -1 1393887324505 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:11 " "Fitter preparation operations ending: elapsed time is 00:00:11" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1 1393887324506 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "" 0 -1 1393887326387 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:02 " "Fitter placement preparation operations ending: elapsed time is 00:00:02" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1 1393887328013 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "" 0 -1 1393887328057 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "" 0 -1 1393887335602 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:08 " "Fitter placement operations ending: elapsed time is 00:00:08" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 -1 1393887335602 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "" 0 -1 1393887337556 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "7 " "Router estimated average interconnect usage is 7% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "36 X21_Y11 X31_Y22 " "Router estimated peak interconnect usage is 36% of the available device resources in the region that extends from location X21_Y11 to location X31_Y22" { } { { "loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 1 { 0 "Router estimated peak interconnect usage is 36% of the available device resources in the region that extends from location X21_Y11 to location X31_Y22"} { { 11 { 0 "Router estimated peak interconnect usage is 36% of the available device resources in the region that extends from location X21_Y11 to location X31_Y22"} 21 11 11 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1 1393887342396 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1 1393887342396 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:09 " "Fitter routing operations ending: elapsed time is 00:00:09" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 -1 1393887347485 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 -1 1393887347488 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 -1 1393887347488 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "" 0 -1 1393887347488 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "" 0 -1 1393887347732 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "" 0 -1 1393887348427 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "" 0 -1 1393887348496 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "" 0 -1 1393887349248 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:04 " "Fitter post-fit operations ending: elapsed time is 00:00:04" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "" 0 -1 1393887351558 ""} +{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "" 0 -1 1393887352211 ""} +{ "Warning" "WFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE" "68 " "Following 68 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[0\] a permanently disabled " "Pin GPIO_0\[0\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[0] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[0\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 320 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393887352267 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[1\] a permanently disabled " "Pin GPIO_0\[1\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[1] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[1\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 321 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393887352267 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[2\] a permanently disabled " "Pin GPIO_0\[2\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[2] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[2\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 322 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393887352267 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[3\] a permanently disabled " "Pin GPIO_0\[3\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[3] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[3\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 323 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393887352267 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[4\] a permanently disabled " "Pin GPIO_0\[4\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[4] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[4\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 324 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393887352267 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[5\] a permanently disabled " "Pin GPIO_0\[5\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[5] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[5\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 325 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393887352267 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[6\] a permanently disabled " "Pin GPIO_0\[6\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[6] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[6\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 326 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393887352267 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[7\] a permanently disabled " "Pin GPIO_0\[7\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[7] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[7\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 327 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393887352267 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[8\] a permanently disabled " "Pin GPIO_0\[8\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[8] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[8\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 328 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393887352267 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[9\] a permanently disabled " "Pin GPIO_0\[9\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[9] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[9\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 329 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393887352267 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[10\] a permanently disabled " "Pin GPIO_0\[10\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[10] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[10\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 330 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393887352267 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[11\] a permanently disabled " "Pin GPIO_0\[11\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[11] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[11\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 331 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393887352267 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[12\] a permanently disabled " "Pin GPIO_0\[12\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[12] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[12\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 332 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393887352267 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[13\] a permanently disabled " "Pin GPIO_0\[13\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[13] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[13\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 333 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393887352267 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[14\] a permanently disabled " "Pin GPIO_0\[14\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[14] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[14\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 334 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393887352267 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[15\] a permanently disabled " "Pin GPIO_0\[15\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[15] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[15\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 335 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393887352267 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[16\] a permanently disabled " "Pin GPIO_0\[16\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[16] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[16\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[16] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 336 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393887352267 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[17\] a permanently disabled " "Pin GPIO_0\[17\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[17] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[17\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[17] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 337 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393887352267 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[18\] a permanently disabled " "Pin GPIO_0\[18\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[18] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[18\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[18] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 338 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393887352267 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[19\] a permanently disabled " "Pin GPIO_0\[19\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[19] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[19\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[19] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 339 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393887352267 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[20\] a permanently disabled " "Pin GPIO_0\[20\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[20] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[20\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[20] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 340 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393887352267 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[21\] a permanently disabled " "Pin GPIO_0\[21\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[21] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[21\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[21] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 341 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393887352267 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[22\] a permanently disabled " "Pin GPIO_0\[22\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[22] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[22\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[22] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 342 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393887352267 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[23\] a permanently disabled " "Pin GPIO_0\[23\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[23] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[23\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[23] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 343 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393887352267 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[24\] a permanently disabled " "Pin GPIO_0\[24\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[24] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[24\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[24] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 344 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393887352267 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[25\] a permanently disabled " "Pin GPIO_0\[25\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[25] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[25\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[25] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 345 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393887352267 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[26\] a permanently disabled " "Pin GPIO_0\[26\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[26] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[26\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[26] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 346 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393887352267 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[27\] a permanently disabled " "Pin GPIO_0\[27\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[27] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[27\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[27] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 347 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393887352267 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[28\] a permanently disabled " "Pin GPIO_0\[28\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[28] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[28\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[28] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 348 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393887352267 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[29\] a permanently disabled " "Pin GPIO_0\[29\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[29] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[29\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[29] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 349 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393887352267 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[30\] a permanently disabled " "Pin GPIO_0\[30\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[30] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[30\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[30] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 350 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393887352267 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[32\] a permanently disabled " "Pin GPIO_0\[32\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[32] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[32\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[32] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 351 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393887352267 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[1\] a permanently disabled " "Pin GPIO_1\[1\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[1] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[1\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 352 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393887352267 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[2\] a permanently disabled " "Pin GPIO_1\[2\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[2] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[2\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 353 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393887352267 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[3\] a permanently disabled " "Pin GPIO_1\[3\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[3] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[3\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 354 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393887352267 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[4\] a permanently disabled " "Pin GPIO_1\[4\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[4] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[4\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 355 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393887352267 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[5\] a permanently disabled " "Pin GPIO_1\[5\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[5] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[5\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 356 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393887352267 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[6\] a permanently disabled " "Pin GPIO_1\[6\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[6] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[6\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 357 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393887352267 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[7\] a permanently disabled " "Pin GPIO_1\[7\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[7] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[7\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 358 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393887352267 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[8\] a permanently disabled " "Pin GPIO_1\[8\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[8] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[8\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 359 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393887352267 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[9\] a permanently disabled " "Pin GPIO_1\[9\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[9] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[9\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 360 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393887352267 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[10\] a permanently disabled " "Pin GPIO_1\[10\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[10] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[10\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 361 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393887352267 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[11\] a permanently disabled " "Pin GPIO_1\[11\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[11] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[11\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 362 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393887352267 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[12\] a permanently disabled " "Pin GPIO_1\[12\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[12] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[12\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 363 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393887352267 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[13\] a permanently disabled " "Pin GPIO_1\[13\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[13] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[13\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 364 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393887352267 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[14\] a permanently disabled " "Pin GPIO_1\[14\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[14] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[14\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 365 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393887352267 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[15\] a permanently disabled " "Pin GPIO_1\[15\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[15] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[15\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 366 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393887352267 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[16\] a permanently disabled " "Pin GPIO_1\[16\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[16] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[16\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[16] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 367 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393887352267 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[17\] a permanently disabled " "Pin GPIO_1\[17\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[17] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[17\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[17] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 368 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393887352267 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[18\] a permanently disabled " "Pin GPIO_1\[18\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[18] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[18\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[18] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 369 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393887352267 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[19\] a permanently disabled " "Pin GPIO_1\[19\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[19] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[19\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[19] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 370 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393887352267 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[20\] a permanently disabled " "Pin GPIO_1\[20\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[20] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[20\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[20] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 371 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393887352267 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[21\] a permanently disabled " "Pin GPIO_1\[21\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[21] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[21\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[21] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 372 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393887352267 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[22\] a permanently disabled " "Pin GPIO_1\[22\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[22] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[22\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[22] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 373 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393887352267 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[23\] a permanently disabled " "Pin GPIO_1\[23\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[23] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[23\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[23] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 374 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393887352267 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[24\] a permanently disabled " "Pin GPIO_1\[24\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[24] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[24\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[24] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 375 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393887352267 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[25\] a permanently disabled " "Pin GPIO_1\[25\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[25] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[25\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[25] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 376 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393887352267 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[26\] a permanently disabled " "Pin GPIO_1\[26\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[26] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[26\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[26] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 377 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393887352267 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[27\] a permanently disabled " "Pin GPIO_1\[27\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[27] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[27\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[27] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 378 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393887352267 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[28\] a permanently disabled " "Pin GPIO_1\[28\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[28] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[28\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[28] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 379 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393887352267 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[29\] a permanently disabled " "Pin GPIO_1\[29\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[29] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[29\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[29] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 380 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393887352267 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[30\] a permanently disabled " "Pin GPIO_1\[30\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[30] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[30\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[30] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 381 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393887352267 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[32\] a permanently disabled " "Pin GPIO_1\[32\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[32] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[32\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[32] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 382 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393887352267 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[31\] a permanently disabled " "Pin GPIO_0\[31\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[31] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[31\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[31] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 271 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393887352267 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[33\] a permanently enabled " "Pin GPIO_0\[33\] has a permanently enabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[33] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[33\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 76 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[33] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 268 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393887352267 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[0\] a permanently enabled " "Pin GPIO_1\[0\] has a permanently enabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[0] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[0\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 272 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393887352267 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[31\] a permanently disabled " "Pin GPIO_1\[31\] has a permanently disabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[31] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[31\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[31] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 270 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393887352267 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[33\] a permanently enabled " "Pin GPIO_1\[33\] has a permanently enabled output enable" { } { { "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/12.1sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[33] } } } { "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/12.1sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[33\]" } } } } { "de0_nano_system.vhd" "" { Text "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/de0_nano_system.vhd" 77 0 0 } } { "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/12.1sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[33] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/" { { 0 { 0 ""} 0 269 8336 9085 0} } } } } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "" 0 -1 1393887352267 ""} } { } 0 169064 "Following %1!d! pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results" 0 0 "" 0 -1 1393887352267 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/output_files/de0_nano_system.fit.smsg " "Generated suppressed messages file C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/output_files/de0_nano_system.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "" 0 -1 1393887352845 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 36 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 36 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1149 " "Peak virtual memory: 1149 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1 1393887354444 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 03 15:55:54 2014 " "Processing ended: Mon Mar 03 15:55:54 2014" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1 1393887354444 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:42 " "Elapsed time: 00:00:42" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1 1393887354444 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:52 " "Total CPU time (on all processors): 00:00:52" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1 1393887354444 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1 1393887354444 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1 1393887355639 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Full Version " "Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1 1393887355640 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 03 15:55:55 2014 " "Processing started: Mon Mar 03 15:55:55 2014" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1 1393887355640 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1 1393887355640 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off de0_nano_system -c de0_nano_system " "Command: quartus_asm --read_settings_files=off --write_settings_files=off de0_nano_system -c de0_nano_system" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1 1393887355640 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "" 0 -1 1393887357638 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "" 0 -1 1393887357669 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "455 " "Peak virtual memory: 455 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1 1393887358109 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 03 15:55:58 2014 " "Processing ended: Mon Mar 03 15:55:58 2014" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1 1393887358109 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1 1393887358109 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1 1393887358109 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1 1393887358109 ""} +{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "" 0 -1 1393887358765 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1 1393887359401 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Full Version " "Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1 1393887359402 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 03 15:55:58 2014 " "Processing started: Mon Mar 03 15:55:58 2014" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1 1393887359402 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1 1393887359402 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta de0_nano_system -c de0_nano_system " "Command: quartus_sta de0_nano_system -c de0_nano_system" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1 1393887359402 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "" 0 0 1393887359464 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." { } { } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "" 0 -1 1393887359801 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Core supply voltage 1.2V " "Core supply voltage is 1.2V" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "" 0 -1 1393887359801 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "" 0 -1 1393887359854 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "" 0 -1 1393887359854 ""} +{ "Info" "ISTA_SDC_STATEMENT_PARENT" "" "Evaluating HDL-embedded SDC commands" { { "Info" "ISTA_SDC_STATEMENT_ENTITY" "alt_jtag_atlantic " "Entity alt_jtag_atlantic" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate1*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|jupdate1*\}\] " { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393887360595 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393887360595 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393887360595 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393887360595 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393887360595 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393887360595 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393887360595 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393887360595 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rdata\[*\]\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393887360595 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|read1*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|read1*\}\] " { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393887360595 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read_req\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|read_req\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393887360595 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic*\|td_shift\[*\]\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393887360595 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|tck_t_dav\}\] " "set_false_path -from \[get_registers \{*\|t_dav\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|tck_t_dav\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393887360595 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|user_saw_rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid0*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|user_saw_rvalid\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|rvalid0*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393887360595 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393887360595 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393887360595 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393887360595 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393887360595 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393887360595 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393887360595 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393887360595 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|wdata\[*\]\}\] -to \[get_registers \{*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393887360595 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write1*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|write1*\}\] " { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393887360595 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_ena*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_ena*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393887360595 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_pause*\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_stalled\}\] -to \[get_registers \{*\|alt_jtag_atlantic:*\|t_pause*\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393887360595 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_valid\}\] " "set_false_path -from \[get_registers \{*\|alt_jtag_atlantic:*\|write_valid\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393887360595 ""} } { } 0 332165 "Entity %1!s!" 0 0 "" 0 -1 1393887360595 ""} { "Info" "ISTA_SDC_STATEMENT_ENTITY" "altera_std_synchronizer " "Entity altera_std_synchronizer" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -to \[get_keepers \{*altera_std_synchronizer:*\|din_s1\}\] " "set_false_path -to \[get_keepers \{*altera_std_synchronizer:*\|din_s1\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393887360595 ""} } { } 0 332165 "Entity %1!s!" 0 0 "" 0 -1 1393887360595 ""} { "Info" "ISTA_SDC_STATEMENT_ENTITY" "sld_jtag_hub " "Entity sld_jtag_hub" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "create_clock -period 10MHz -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] " "create_clock -period 10MHz -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\]" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393887360595 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_clock_groups -asynchronous -group \{altera_reserved_tck\} " "set_clock_groups -asynchronous -group \{altera_reserved_tck\}" { } { } 0 332166 "%1!s!" 0 0 "" 0 -1 1393887360595 ""} } { } 0 332165 "Entity %1!s!" 0 0 "" 0 -1 1393887360595 ""} } { } 0 332164 "Evaluating HDL-embedded SDC commands" 0 0 "" 0 -1 1393887360595 ""} +{ "Info" "ISTA_SDC_FOUND" "de0_nano_system.sdc " "Reading SDC File: 'de0_nano_system.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "" 0 -1 1393887360644 ""} +{ "Warning" "WSTA_OVERWRITING_EXISTING_CLOCK" "altera_reserved_tck " "Overwriting existing clock: altera_reserved_tck" { } { } 0 332043 "Overwriting existing clock: %1!s!" 0 0 "" 0 -1 1393887360644 ""} +{ "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "Deriving PLL clocks " "Deriving PLL clocks" { { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -duty_cycle 50.00 -name \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} " "create_generated_clock -source \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -duty_cycle 50.00 -name \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\]\} \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\]\}" { } { } 0 332110 "%1!s!" 0 0 "" 0 -1 1393887360645 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -phase -54.00 -duty_cycle 50.00 -name \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} " "create_generated_clock -source \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 2 -phase -54.00 -duty_cycle 50.00 -name \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[1\]\} \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[1\]\}" { } { } 0 332110 "%1!s!" 0 0 "" 0 -1 1393887360645 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 5 -duty_cycle 50.00 -name \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} " "create_generated_clock -source \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|inclk\[0\]\} -divide_by 5 -duty_cycle 50.00 -name \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\]\} \{inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\]\}" { } { } 0 332110 "%1!s!" 0 0 "" 0 -1 1393887360645 ""} } { } 0 332110 "%1!s!" 0 0 "" 0 -1 1393887360645 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_CALL_IS_DELAYED" "" "Clock uncertainty is not calculated until you update the timing netlist." { } { } 0 332151 "Clock uncertainty is not calculated until you update the timing netlist." 0 0 "" 0 -1 1393887360646 ""} +{ "Info" "ISTA_SDC_FOUND" "system/synthesis/submodules/altera_reset_controller.sdc " "Reading SDC File: 'system/synthesis/submodules/altera_reset_controller.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "" 0 -1 1393887360651 ""} +{ "Info" "ISTA_SDC_FOUND" "system/synthesis/submodules/system_cpu.sdc " "Reading SDC File: 'system/synthesis/submodules/system_cpu.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "" 0 -1 1393887360673 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "" 0 -1 1393887360894 ""} +{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "" 0 0 1393887360896 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "" 0 0 1393887360913 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup 2.068 " "Worst-case setup slack is 2.068" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393887360997 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393887360997 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 2.068 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 2.068 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393887360997 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 97.388 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 97.388 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393887360997 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1393887360997 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.230 " "Worst-case hold slack is 0.230" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393887361024 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393887361024 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.230 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.230 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393887361024 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.361 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 0.361 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393887361024 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1393887361024 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 1.948 " "Worst-case recovery slack is 1.948" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393887361036 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393887361036 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.948 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 1.948 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393887361036 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1393887361036 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "removal 2.524 " "Worst-case removal slack is 2.524" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393887361048 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393887361048 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 2.524 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 2.524 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393887361048 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1393887361048 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 4.694 " "Worst-case minimum pulse width slack is 4.694" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393887361054 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393887361054 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.694 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 4.694 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393887361054 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 9.835 0.000 CLOCK_50 " " 9.835 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393887361054 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 49.640 0.000 altera_reserved_tck " " 49.640 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393887361054 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 49.747 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 49.747 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393887361054 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1393887361054 ""} +{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 6 synchronizer chains. " "Report Metastability: Found 6 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n " "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393887361334 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 6 " "Number of Synchronizer Chains Found: 6" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393887361334 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393887361334 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 0.333 " "Fraction of Chains for which MTBFs Could Not be Calculated: 0.333" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393887361334 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 17.228 ns " "Worst Case Available Settling Time: 17.228 ns" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393887361334 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393887361334 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. " "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions." { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393887361334 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8 " " - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393887361334 ""} } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393887361334 ""} +{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "" 0 0 1393887361342 ""} +{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "" 0 -1 1393887361379 ""} +{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "" 0 -1 1393887362217 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "" 0 -1 1393887362576 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup 2.461 " "Worst-case setup slack is 2.461" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393887362679 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393887362679 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 2.461 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 2.461 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393887362679 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 97.707 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 97.707 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393887362679 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1393887362679 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.227 " "Worst-case hold slack is 0.227" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393887362706 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393887362706 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.227 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.227 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393887362706 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.320 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 0.320 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393887362706 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1393887362706 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 2.272 " "Worst-case recovery slack is 2.272" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393887362727 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393887362727 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 2.272 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 2.272 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393887362727 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1393887362727 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "removal 2.259 " "Worst-case removal slack is 2.259" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393887362743 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393887362743 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 2.259 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 2.259 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393887362743 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1393887362743 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 4.716 " "Worst-case minimum pulse width slack is 4.716" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393887362753 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393887362753 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.716 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 4.716 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393887362753 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 9.818 0.000 CLOCK_50 " " 9.818 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393887362753 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 49.608 0.000 altera_reserved_tck " " 49.608 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393887362753 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 49.744 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 49.744 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393887362753 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1393887362753 ""} +{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 6 synchronizer chains. " "Report Metastability: Found 6 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n " "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393887363047 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 6 " "Number of Synchronizer Chains Found: 6" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393887363047 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393887363047 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 0.333 " "Fraction of Chains for which MTBFs Could Not be Calculated: 0.333" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393887363047 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 17.489 ns " "Worst Case Available Settling Time: 17.489 ns" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393887363047 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393887363047 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. " "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions." { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393887363047 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8 " " - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393887363047 ""} } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393887363047 ""} +{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "" 0 0 1393887363059 ""} +{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "" 0 -1 1393887363463 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup 3.368 " "Worst-case setup slack is 3.368" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393887363492 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393887363492 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 3.368 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 3.368 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393887363492 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 98.512 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 98.512 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393887363492 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1393887363492 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.102 " "Worst-case hold slack is 0.102" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393887363518 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393887363518 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.102 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 0.102 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393887363518 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.193 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 0.193 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393887363518 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1393887363518 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 3.214 " "Worst-case recovery slack is 3.214" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393887363534 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393887363534 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 3.214 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 3.214 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393887363534 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1393887363534 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "removal 1.443 " "Worst-case removal slack is 1.443" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393887363551 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393887363551 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.443 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 1.443 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393887363551 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1393887363551 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 4.749 " "Worst-case minimum pulse width slack is 4.749" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393887363562 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393887363562 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.749 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " " 4.749 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[0\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393887363562 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 9.587 0.000 CLOCK_50 " " 9.587 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393887363562 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 49.484 0.000 altera_reserved_tck " " 49.484 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393887363562 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 49.782 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " " 49.782 0.000 inst_pll_sys\|altpll_component\|auto_generated\|pll1\|clk\[2\] " { } { } 0 332119 "%1!s!" 0 0 "" 0 -1 1393887363562 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "" 0 -1 1393887363562 ""} +{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 6 synchronizer chains. " "Report Metastability: Found 6 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n " "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393887364135 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 6 " "Number of Synchronizer Chains Found: 6" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393887364135 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393887364135 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 0.333 " "Fraction of Chains for which MTBFs Could Not be Calculated: 0.333" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393887364135 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 18.472 ns " "Worst Case Available Settling Time: 18.472 ns" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393887364135 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393887364135 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. " "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions." { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393887364135 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8 " " - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8" { } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393887364135 ""} } { } 0 332114 "%1!s!" 0 0 "" 0 -1 1393887364135 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "" 0 -1 1393887364746 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "" 0 -1 1393887364747 ""} +{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 1 Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "569 " "Peak virtual memory: 569 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1 1393887365160 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 03 15:56:05 2014 " "Processing ended: Mon Mar 03 15:56:05 2014" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1 1393887365160 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1 1393887365160 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:07 " "Total CPU time (on all processors): 00:00:07" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1 1393887365160 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1 1393887365160 ""} +{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 167 s " "Quartus II Full Compilation was successful. 0 errors, 167 warnings" { } { } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1 1393887366147 ""} diff --git a/MCandWifiTestDE0/de0_nano_system.jdi b/MCandWifiTestDE0/de0_nano_system.jdi index e49f6be0..675911cc 100644 --- a/MCandWifiTestDE0/de0_nano_system.jdi +++ b/MCandWifiTestDE0/de0_nano_system.jdi @@ -1,6 +1,6 @@ - + @@ -142,7 +142,7 @@ - + diff --git a/MCandWifiTestDE0/de0_nano_system.qsf b/MCandWifiTestDE0/de0_nano_system.qsf index dc8988a6..ff07e51b 100644 --- a/MCandWifiTestDE0/de0_nano_system.qsf +++ b/MCandWifiTestDE0/de0_nano_system.qsf @@ -207,6 +207,6 @@ set_location_assignment PIN_J13 -to GPIO_1[32] set_location_assignment PIN_J14 -to GPIO_1[33] set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top set_global_assignment -name QIP_FILE system/synthesis/system.qip -set_global_assignment -name QIP_FILE pll_sys.qip -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file +set_global_assignment -name QIP_FILE pll_sys.qip \ No newline at end of file diff --git a/MCandWifiTestDE0/de0_nano_system.qws b/MCandWifiTestDE0/de0_nano_system.qws index 6c145286..7bb074bf 100644 Binary files a/MCandWifiTestDE0/de0_nano_system.qws and b/MCandWifiTestDE0/de0_nano_system.qws differ diff --git a/MCandWifiTestDE0/incremental_db/compiled_partitions/de0_nano_system.autoh_e40e1.map.cdb b/MCandWifiTestDE0/incremental_db/compiled_partitions/de0_nano_system.autoh_e40e1.map.cdb index e34bb27c..266efbf7 100644 Binary files a/MCandWifiTestDE0/incremental_db/compiled_partitions/de0_nano_system.autoh_e40e1.map.cdb and b/MCandWifiTestDE0/incremental_db/compiled_partitions/de0_nano_system.autoh_e40e1.map.cdb differ diff --git a/MCandWifiTestDE0/incremental_db/compiled_partitions/de0_nano_system.autoh_e40e1.map.dpi b/MCandWifiTestDE0/incremental_db/compiled_partitions/de0_nano_system.autoh_e40e1.map.dpi index 6849f780..f2ac2193 100644 Binary files a/MCandWifiTestDE0/incremental_db/compiled_partitions/de0_nano_system.autoh_e40e1.map.dpi and b/MCandWifiTestDE0/incremental_db/compiled_partitions/de0_nano_system.autoh_e40e1.map.dpi differ diff --git a/MCandWifiTestDE0/incremental_db/compiled_partitions/de0_nano_system.autoh_e40e1.map.hdb b/MCandWifiTestDE0/incremental_db/compiled_partitions/de0_nano_system.autoh_e40e1.map.hdb index 93dd64b0..4758e114 100644 Binary files a/MCandWifiTestDE0/incremental_db/compiled_partitions/de0_nano_system.autoh_e40e1.map.hdb and b/MCandWifiTestDE0/incremental_db/compiled_partitions/de0_nano_system.autoh_e40e1.map.hdb differ diff --git a/MCandWifiTestDE0/incremental_db/compiled_partitions/de0_nano_system.autoh_e40e1.map.kpt b/MCandWifiTestDE0/incremental_db/compiled_partitions/de0_nano_system.autoh_e40e1.map.kpt index c584a5e7..e4d5580a 100644 Binary files a/MCandWifiTestDE0/incremental_db/compiled_partitions/de0_nano_system.autoh_e40e1.map.kpt and b/MCandWifiTestDE0/incremental_db/compiled_partitions/de0_nano_system.autoh_e40e1.map.kpt differ diff --git a/MCandWifiTestDE0/incremental_db/compiled_partitions/de0_nano_system.root_partition.cmp.ammdb b/MCandWifiTestDE0/incremental_db/compiled_partitions/de0_nano_system.root_partition.cmp.ammdb index 6bf4b5c2..3b61a949 100644 Binary files a/MCandWifiTestDE0/incremental_db/compiled_partitions/de0_nano_system.root_partition.cmp.ammdb and b/MCandWifiTestDE0/incremental_db/compiled_partitions/de0_nano_system.root_partition.cmp.ammdb differ diff --git a/MCandWifiTestDE0/incremental_db/compiled_partitions/de0_nano_system.root_partition.cmp.cdb b/MCandWifiTestDE0/incremental_db/compiled_partitions/de0_nano_system.root_partition.cmp.cdb index d7755442..b1797d11 100644 Binary files a/MCandWifiTestDE0/incremental_db/compiled_partitions/de0_nano_system.root_partition.cmp.cdb and b/MCandWifiTestDE0/incremental_db/compiled_partitions/de0_nano_system.root_partition.cmp.cdb differ diff --git a/MCandWifiTestDE0/incremental_db/compiled_partitions/de0_nano_system.root_partition.cmp.hdb b/MCandWifiTestDE0/incremental_db/compiled_partitions/de0_nano_system.root_partition.cmp.hdb index 7ea2c76e..5213c10a 100644 Binary files a/MCandWifiTestDE0/incremental_db/compiled_partitions/de0_nano_system.root_partition.cmp.hdb and b/MCandWifiTestDE0/incremental_db/compiled_partitions/de0_nano_system.root_partition.cmp.hdb differ diff --git a/MCandWifiTestDE0/incremental_db/compiled_partitions/de0_nano_system.root_partition.cmp.rcfdb b/MCandWifiTestDE0/incremental_db/compiled_partitions/de0_nano_system.root_partition.cmp.rcfdb index d28c4458..01ed90e6 100644 Binary files a/MCandWifiTestDE0/incremental_db/compiled_partitions/de0_nano_system.root_partition.cmp.rcfdb and b/MCandWifiTestDE0/incremental_db/compiled_partitions/de0_nano_system.root_partition.cmp.rcfdb differ diff --git a/MCandWifiTestDE0/incremental_db/compiled_partitions/de0_nano_system.root_partition.map.cdb b/MCandWifiTestDE0/incremental_db/compiled_partitions/de0_nano_system.root_partition.map.cdb index d8927fb2..f61837e7 100644 Binary files a/MCandWifiTestDE0/incremental_db/compiled_partitions/de0_nano_system.root_partition.map.cdb and b/MCandWifiTestDE0/incremental_db/compiled_partitions/de0_nano_system.root_partition.map.cdb differ diff --git a/MCandWifiTestDE0/incremental_db/compiled_partitions/de0_nano_system.root_partition.map.dpi b/MCandWifiTestDE0/incremental_db/compiled_partitions/de0_nano_system.root_partition.map.dpi index 7d5f1686..1c62f17c 100644 Binary files a/MCandWifiTestDE0/incremental_db/compiled_partitions/de0_nano_system.root_partition.map.dpi and b/MCandWifiTestDE0/incremental_db/compiled_partitions/de0_nano_system.root_partition.map.dpi differ diff --git a/MCandWifiTestDE0/incremental_db/compiled_partitions/de0_nano_system.root_partition.map.hbdb.cdb b/MCandWifiTestDE0/incremental_db/compiled_partitions/de0_nano_system.root_partition.map.hbdb.cdb index 2fc409d1..2a216b5e 100644 Binary files a/MCandWifiTestDE0/incremental_db/compiled_partitions/de0_nano_system.root_partition.map.hbdb.cdb and b/MCandWifiTestDE0/incremental_db/compiled_partitions/de0_nano_system.root_partition.map.hbdb.cdb differ diff --git a/MCandWifiTestDE0/incremental_db/compiled_partitions/de0_nano_system.root_partition.map.hbdb.hdb b/MCandWifiTestDE0/incremental_db/compiled_partitions/de0_nano_system.root_partition.map.hbdb.hdb index d04b9eba..9fe52782 100644 Binary files a/MCandWifiTestDE0/incremental_db/compiled_partitions/de0_nano_system.root_partition.map.hbdb.hdb and b/MCandWifiTestDE0/incremental_db/compiled_partitions/de0_nano_system.root_partition.map.hbdb.hdb differ diff --git a/MCandWifiTestDE0/incremental_db/compiled_partitions/de0_nano_system.root_partition.map.hdb b/MCandWifiTestDE0/incremental_db/compiled_partitions/de0_nano_system.root_partition.map.hdb index 91ea6134..94ca27ec 100644 Binary files a/MCandWifiTestDE0/incremental_db/compiled_partitions/de0_nano_system.root_partition.map.hdb and b/MCandWifiTestDE0/incremental_db/compiled_partitions/de0_nano_system.root_partition.map.hdb differ diff --git a/MCandWifiTestDE0/incremental_db/compiled_partitions/de0_nano_system.root_partition.map.kpt b/MCandWifiTestDE0/incremental_db/compiled_partitions/de0_nano_system.root_partition.map.kpt index f8c154d4..45d96401 100644 Binary files a/MCandWifiTestDE0/incremental_db/compiled_partitions/de0_nano_system.root_partition.map.kpt and b/MCandWifiTestDE0/incremental_db/compiled_partitions/de0_nano_system.root_partition.map.kpt differ diff --git a/MCandWifiTestDE0/output_files/de0_nano_system.asm.rpt b/MCandWifiTestDE0/output_files/de0_nano_system.asm.rpt index aafc6455..a1fc0916 100644 --- a/MCandWifiTestDE0/output_files/de0_nano_system.asm.rpt +++ b/MCandWifiTestDE0/output_files/de0_nano_system.asm.rpt @@ -1,5 +1,5 @@ Assembler report for de0_nano_system -Sun Mar 02 18:54:50 2014 +Mon Mar 03 16:13:06 2014 Quartus II 64-Bit Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Full Version @@ -38,7 +38,7 @@ applicable agreement for further details. +---------------------------------------------------------------+ ; Assembler Summary ; +-----------------------+---------------------------------------+ -; Assembler Status ; Successful - Sun Mar 02 18:54:50 2014 ; +; Assembler Status ; Successful - Mon Mar 03 16:13:06 2014 ; ; Revision Name ; de0_nano_system ; ; Top-level Entity Name ; de0_nano_system ; ; Family ; Cyclone IV E ; @@ -105,7 +105,7 @@ applicable agreement for further details. +----------------+----------------------------------------------------------------------------------------+ ; Device ; EP4CE22F17C6 ; ; JTAG usercode ; 0xFFFFFFFF ; -; Checksum ; 0x004865F7 ; +; Checksum ; 0x004813C4 ; +----------------+----------------------------------------------------------------------------------------+ @@ -115,13 +115,13 @@ applicable agreement for further details. Info: ******************************************************************* Info: Running Quartus II 64-Bit Assembler Info: Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Full Version - Info: Processing started: Sun Mar 02 18:54:47 2014 + Info: Processing started: Mon Mar 03 16:13:04 2014 Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off de0_nano_system -c de0_nano_system Info (115031): Writing out detailed assembly data for power analysis Info (115030): Assembler is generating device programming files Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings - Info: Peak virtual memory: 460 megabytes - Info: Processing ended: Sun Mar 02 18:54:50 2014 + Info: Peak virtual memory: 456 megabytes + Info: Processing ended: Mon Mar 03 16:13:07 2014 Info: Elapsed time: 00:00:03 Info: Total CPU time (on all processors): 00:00:02 diff --git a/MCandWifiTestDE0/output_files/de0_nano_system.cdf b/MCandWifiTestDE0/output_files/de0_nano_system.cdf index ea02957f..cc08ea59 100644 --- a/MCandWifiTestDE0/output_files/de0_nano_system.cdf +++ b/MCandWifiTestDE0/output_files/de0_nano_system.cdf @@ -1,4 +1,4 @@ -/* Quartus II 32-bit Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Full Version */ +/* Quartus II 64-Bit Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Full Version */ JedecChain; FileRevision(JESD32A); DefaultMfr(6E); diff --git a/MCandWifiTestDE0/output_files/de0_nano_system.done b/MCandWifiTestDE0/output_files/de0_nano_system.done index 95683ea0..af11e0dc 100644 --- a/MCandWifiTestDE0/output_files/de0_nano_system.done +++ b/MCandWifiTestDE0/output_files/de0_nano_system.done @@ -1 +1 @@ -Sun Mar 02 18:54:58 2014 +Mon Mar 03 16:13:14 2014 diff --git a/MCandWifiTestDE0/output_files/de0_nano_system.fit.rpt b/MCandWifiTestDE0/output_files/de0_nano_system.fit.rpt index 6fdd8fbe..00b7adec 100644 --- a/MCandWifiTestDE0/output_files/de0_nano_system.fit.rpt +++ b/MCandWifiTestDE0/output_files/de0_nano_system.fit.rpt @@ -1,5 +1,5 @@ Fitter report for de0_nano_system -Sun Mar 02 18:54:45 2014 +Mon Mar 03 16:13:01 2014 Quartus II 64-Bit Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Full Version @@ -76,14 +76,14 @@ applicable agreement for further details. +----------------------------------------------------------------------------------------+ ; Fitter Summary ; +------------------------------------+---------------------------------------------------+ -; Fitter Status ; Successful - Sun Mar 02 18:54:45 2014 ; +; Fitter Status ; Successful - Mon Mar 03 16:13:01 2014 ; ; Quartus II 64-Bit Version ; 12.1 Build 243 01/31/2013 SP 1.33 SJ Full Version ; ; Revision Name ; de0_nano_system ; ; Top-level Entity Name ; de0_nano_system ; ; Family ; Cyclone IV E ; ; Device ; EP4CE22F17C6 ; ; Timing Models ; Final ; -; Total logic elements ; 4,752 / 22,320 ( 21 % ) ; +; Total logic elements ; 4,711 / 22,320 ( 21 % ) ; ; Total combinational functions ; 4,105 / 22,320 ( 18 % ) ; ; Dedicated logic registers ; 2,919 / 22,320 ( 13 % ) ; ; Total registers ; 2988 ; @@ -162,12 +162,12 @@ applicable agreement for further details. ; Number detected on machine ; 8 ; ; Maximum allowed ; 4 ; ; ; ; -; Average used ; 1.57 ; +; Average used ; 2.26 ; ; Maximum used ; 4 ; ; ; ; ; Usage by Processor ; % Time Used ; ; 1 processor ; 100.0% ; -; 2-4 processors ; 5.6% ; +; 2-4 processors ; 15.4% ; ; 5-8 processors ; 0.0% ; +----------------------------+-------------+ @@ -638,8 +638,8 @@ applicable agreement for further details. +--------------------------------+---------+-------------------+-------------------------+-------------------+ ; Partition Name ; # Nodes ; # Preserved Nodes ; Preservation Level Used ; Netlist Type Used ; +--------------------------------+---------+-------------------+-------------------------+-------------------+ -; Top ; 7451 ; 0 ; N/A ; Source File ; -; sld_hub:auto_hub ; 255 ; 0 ; N/A ; Post-Synthesis ; +; Top ; 7448 ; 0 ; N/A ; Source File ; +; sld_hub:auto_hub ; 258 ; 0 ; N/A ; Post-Synthesis ; ; hard_block:auto_generated_inst ; 14 ; 0 ; N/A ; Source File ; +--------------------------------+---------+-------------------+-------------------------+-------------------+ @@ -655,16 +655,16 @@ The pin-out file can be found in C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/ou +---------------------------------------------+----------------------------+ ; Resource ; Usage ; +---------------------------------------------+----------------------------+ -; Total logic elements ; 4,752 / 22,320 ( 21 % ) ; -; -- Combinational with no register ; 1833 ; -; -- Register only ; 647 ; -; -- Combinational with a register ; 2272 ; +; Total logic elements ; 4,711 / 22,320 ( 21 % ) ; +; -- Combinational with no register ; 1792 ; +; -- Register only ; 606 ; +; -- Combinational with a register ; 2313 ; ; ; ; ; Logic element usage by number of LUT inputs ; ; -; -- 4 input functions ; 1981 ; -; -- 3 input functions ; 1346 ; -; -- <=2 input functions ; 778 ; -; -- Register only ; 647 ; +; -- 4 input functions ; 1980 ; +; -- 3 input functions ; 1345 ; +; -- <=2 input functions ; 780 ; +; -- Register only ; 606 ; ; ; ; ; Logic elements by mode ; ; ; -- normal mode ; 3722 ; @@ -674,7 +674,7 @@ The pin-out file can be found in C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/ou ; -- Dedicated logic registers ; 2,919 / 22,320 ( 13 % ) ; ; -- I/O registers ; 69 / 698 ( 10 % ) ; ; ; ; -; Total LABs: partially or completely used ; 348 / 1,395 ( 25 % ) ; +; Total LABs: partially or completely used ; 342 / 1,395 ( 25 % ) ; ; Virtual pins ; 0 ; ; I/O pins ; 122 / 154 ( 79 % ) ; ; -- Clock pins ; 5 / 7 ( 71 % ) ; @@ -691,12 +691,12 @@ The pin-out file can be found in C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/ou ; CRC blocks ; 0 / 1 ( 0 % ) ; ; ASMI blocks ; 0 / 1 ( 0 % ) ; ; Impedance control blocks ; 0 / 4 ( 0 % ) ; -; Average interconnect usage (total/H/V) ; 7% / 7% / 7% ; -; Peak interconnect usage (total/H/V) ; 41% / 39% / 44% ; +; Average interconnect usage (total/H/V) ; 8% / 8% / 8% ; +; Peak interconnect usage (total/H/V) ; 40% / 42% / 38% ; ; Maximum fan-out ; 2827 ; ; Highest non-global fan-out ; 742 ; -; Total fan-out ; 26329 ; -; Average fan-out ; 3.29 ; +; Total fan-out ; 26298 ; +; Average fan-out ; 3.30 ; +---------------------------------------------+----------------------------+ * Register count does not include registers inside RAM blocks or DSP blocks. @@ -709,26 +709,26 @@ The pin-out file can be found in C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/ou +----------------------------------------------+-----------------------+-----------------------+--------------------------------+ ; Difficulty Clustering Region ; Low ; Low ; Low ; ; ; ; ; ; -; Total logic elements ; 4577 / 22320 ( 21 % ) ; 175 / 22320 ( < 1 % ) ; 0 / 22320 ( 0 % ) ; -; -- Combinational with no register ; 1755 ; 78 ; 0 ; -; -- Register only ; 628 ; 19 ; 0 ; -; -- Combinational with a register ; 2194 ; 78 ; 0 ; +; Total logic elements ; 4533 / 22320 ( 20 % ) ; 178 / 22320 ( < 1 % ) ; 0 / 22320 ( 0 % ) ; +; -- Combinational with no register ; 1711 ; 81 ; 0 ; +; -- Register only ; 587 ; 19 ; 0 ; +; -- Combinational with a register ; 2235 ; 78 ; 0 ; ; ; ; ; ; ; Logic element usage by number of LUT inputs ; ; ; ; -; -- 4 input functions ; 1911 ; 70 ; 0 ; -; -- 3 input functions ; 1302 ; 44 ; 0 ; -; -- <=2 input functions ; 736 ; 42 ; 0 ; -; -- Register only ; 628 ; 19 ; 0 ; +; -- 4 input functions ; 1909 ; 71 ; 0 ; +; -- 3 input functions ; 1300 ; 45 ; 0 ; +; -- <=2 input functions ; 737 ; 43 ; 0 ; +; -- Register only ; 587 ; 19 ; 0 ; ; ; ; ; ; ; Logic elements by mode ; ; ; ; -; -- normal mode ; 3574 ; 148 ; 0 ; +; -- normal mode ; 3571 ; 151 ; 0 ; ; -- arithmetic mode ; 375 ; 8 ; 0 ; ; ; ; ; ; ; Total registers ; 2891 ; 97 ; 0 ; ; -- Dedicated logic registers ; 2822 / 22320 ( 13 % ) ; 97 / 22320 ( < 1 % ) ; 0 / 22320 ( 0 % ) ; ; -- I/O registers ; 138 ; 0 ; 0 ; ; ; ; ; ; -; Total LABs: partially or completely used ; 331 / 1395 ( 24 % ) ; 17 / 1395 ( 1 % ) ; 0 / 1395 ( 0 % ) ; +; Total LABs: partially or completely used ; 327 / 1395 ( 23 % ) ; 15 / 1395 ( 1 % ) ; 0 / 1395 ( 0 % ) ; ; ; ; ; ; ; Virtual pins ; 0 ; 0 ; 0 ; ; I/O pins ; 122 ; 0 ; 0 ; @@ -749,8 +749,8 @@ The pin-out file can be found in C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/ou ; -- Registered Output Connections ; 4 ; 129 ; 0 ; ; ; ; ; ; ; Internal Connections ; ; ; ; -; -- Total Connections ; 25763 ; 1012 ; 2861 ; -; -- Registered Connections ; 12337 ; 621 ; 0 ; +; -- Total Connections ; 25723 ; 1021 ; 2861 ; +; -- Registered Connections ; 12326 ; 629 ; 0 ; ; ; ; ; ; ; External Connections ; ; ; ; ; -- Top ; 360 ; 307 ; 2852 ; @@ -850,8 +850,8 @@ The pin-out file can be found in C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/ou ; DRAM_DQ[4] ; K2 ; 2 ; 0 ; 12 ; 0 ; 0 ; 4 ; no ; yes ; yes ; yes ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_4 ; - ; ; DRAM_DQ[5] ; J2 ; 2 ; 0 ; 15 ; 0 ; 0 ; 4 ; no ; yes ; yes ; yes ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_5 ; - ; ; DRAM_DQ[6] ; J1 ; 2 ; 0 ; 15 ; 7 ; 0 ; 4 ; no ; yes ; yes ; yes ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_6 ; - ; -; DRAM_DQ[7] ; R7 ; 3 ; 16 ; 0 ; 14 ; 0 ; 4 ; no ; yes ; yes ; yes ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_7 ; - ; -; DRAM_DQ[8] ; T4 ; 3 ; 5 ; 0 ; 14 ; 0 ; 5 ; no ; yes ; yes ; yes ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_8 ; - ; +; DRAM_DQ[7] ; R7 ; 3 ; 16 ; 0 ; 14 ; 0 ; 5 ; no ; yes ; yes ; yes ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_7 ; - ; +; DRAM_DQ[8] ; T4 ; 3 ; 5 ; 0 ; 14 ; 0 ; 4 ; no ; yes ; yes ; yes ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_8 ; - ; ; DRAM_DQ[9] ; T2 ; 3 ; 3 ; 0 ; 0 ; 0 ; 4 ; no ; yes ; yes ; yes ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_9 ; - ; ; GPIO_0[0] ; D3 ; 8 ; 1 ; 34 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; - ; - ; ; GPIO_0[10] ; B6 ; 8 ; 16 ; 34 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; User ; 0 pF ; - ; - ; @@ -1311,63 +1311,63 @@ Note: Pin directions (input, output or bidir) are based on device operating in u +----------------------------------------------------------------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+ ; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Library Name ; +----------------------------------------------------------------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+ -; |de0_nano_system ; 4752 (1) ; 2919 (0) ; 69 (69) ; 119808 ; 24 ; 4 ; 0 ; 2 ; 122 ; 0 ; 1833 (1) ; 647 (0) ; 2272 (0) ; |de0_nano_system ; ; +; |de0_nano_system ; 4711 (1) ; 2919 (0) ; 69 (69) ; 119808 ; 24 ; 4 ; 0 ; 2 ; 122 ; 0 ; 1792 (1) ; 606 (0) ; 2313 (0) ; |de0_nano_system ; ; ; |heartbeat:inst_heartbeat| ; 22 (22) ; 22 (22) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 22 (22) ; |de0_nano_system|heartbeat:inst_heartbeat ; ; ; |pll_sys:inst_pll_sys| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |de0_nano_system|pll_sys:inst_pll_sys ; ; ; |altpll:altpll_component| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |de0_nano_system|pll_sys:inst_pll_sys|altpll:altpll_component ; ; ; |pll_sys_altpll:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |de0_nano_system|pll_sys:inst_pll_sys|altpll:altpll_component|pll_sys_altpll:auto_generated ; ; -; |sld_hub:auto_hub| ; 175 (1) ; 97 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 78 (1) ; 19 (0) ; 78 (0) ; |de0_nano_system|sld_hub:auto_hub ; ; -; |sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst| ; 174 (131) ; 97 (69) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 77 (62) ; 19 (18) ; 78 (53) ; |de0_nano_system|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst ; ; +; |sld_hub:auto_hub| ; 178 (1) ; 97 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 81 (1) ; 19 (0) ; 78 (0) ; |de0_nano_system|sld_hub:auto_hub ; ; +; |sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst| ; 177 (134) ; 97 (69) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 80 (65) ; 19 (18) ; 78 (53) ; |de0_nano_system|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst ; ; ; |sld_rom_sr:hub_info_reg| ; 23 (23) ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 14 (14) ; 0 (0) ; 9 (9) ; |de0_nano_system|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg ; ; ; |sld_shadow_jsm:shadow_jsm| ; 20 (20) ; 19 (19) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 1 (1) ; 18 (18) ; |de0_nano_system|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm ; ; -; |system:inst_cpu| ; 4554 (0) ; 2800 (0) ; 0 (0) ; 119808 ; 24 ; 4 ; 0 ; 2 ; 0 ; 0 ; 1754 (0) ; 628 (0) ; 2172 (0) ; |de0_nano_system|system:inst_cpu ; ; -; |altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 9 (9) ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 6 (6) ; |de0_nano_system|system:inst_cpu|altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo ; ; +; |system:inst_cpu| ; 4510 (0) ; 2800 (0) ; 0 (0) ; 119808 ; 24 ; 4 ; 0 ; 2 ; 0 ; 0 ; 1710 (0) ; 587 (0) ; 2213 (0) ; |de0_nano_system|system:inst_cpu ; ; +; |altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 9 (9) ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 2 (2) ; 4 (4) ; |de0_nano_system|system:inst_cpu|altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo ; ; ; |altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 7 (7) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 4 (4) ; |de0_nano_system|system:inst_cpu|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo ; ; ; |altera_avalon_sc_fifo:pio_ir_emitter_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 6 (6) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 4 (4) ; |de0_nano_system|system:inst_cpu|altera_avalon_sc_fifo:pio_ir_emitter_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; ; ; |altera_avalon_sc_fifo:pio_key_left_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 4 (4) ; |de0_nano_system|system:inst_cpu|altera_avalon_sc_fifo:pio_key_left_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; ; ; |altera_avalon_sc_fifo:pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 6 (6) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 4 (4) ; |de0_nano_system|system:inst_cpu|altera_avalon_sc_fifo:pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; ; ; |altera_avalon_sc_fifo:pio_sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 4 (4) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 4 (4) ; |de0_nano_system|system:inst_cpu|altera_avalon_sc_fifo:pio_sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; ; ; |altera_avalon_sc_fifo:rs232_wifi_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 4 (4) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 4 (4) ; |de0_nano_system|system:inst_cpu|altera_avalon_sc_fifo:rs232_wifi_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo ; ; -; |altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 66 (66) ; 56 (56) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 9 (9) ; 6 (6) ; 51 (51) ; |de0_nano_system|system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; ; +; |altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 67 (67) ; 56 (56) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 11 (11) ; 6 (6) ; 50 (50) ; |de0_nano_system|system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; ; ; |altera_avalon_sc_fifo:sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 6 (6) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 4 (4) ; |de0_nano_system|system:inst_cpu|altera_avalon_sc_fifo:sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; ; ; |altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 4 (4) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 4 (4) ; |de0_nano_system|system:inst_cpu|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo ; ; ; |altera_avalon_sc_fifo:uart_mc_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 4 (4) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 4 (4) ; |de0_nano_system|system:inst_cpu|altera_avalon_sc_fifo:uart_mc_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; ; ; |altera_avalon_sc_fifo:uart_wifi_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 4 (4) ; |de0_nano_system|system:inst_cpu|altera_avalon_sc_fifo:uart_wifi_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; ; -; |altera_merlin_slave_agent:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent| ; 5 (5) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 5 (5) ; 0 (0) ; 0 (0) ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_agent:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent ; ; +; |altera_merlin_slave_agent:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent| ; 5 (5) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 4 (4) ; 0 (0) ; 1 (1) ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_agent:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent ; ; ; |altera_merlin_slave_agent:pio_key_left_s1_translator_avalon_universal_slave_0_agent| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_agent:pio_key_left_s1_translator_avalon_universal_slave_0_agent ; ; ; |altera_merlin_slave_agent:pio_sw_s1_translator_avalon_universal_slave_0_agent| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_agent:pio_sw_s1_translator_avalon_universal_slave_0_agent ; ; -; |altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent| ; 19 (11) ; 3 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 16 (11) ; 0 (0) ; 3 (0) ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent ; ; +; |altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent| ; 18 (10) ; 3 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 15 (10) ; 0 (0) ; 3 (0) ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent ; ; ; |altera_merlin_burst_uncompressor:uncompressor| ; 8 (8) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 5 (5) ; 0 (0) ; 3 (3) ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor ; ; ; |altera_merlin_slave_agent:sys_clk_timer_s1_translator_avalon_universal_slave_0_agent| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_agent:sys_clk_timer_s1_translator_avalon_universal_slave_0_agent ; ; ; |altera_merlin_slave_agent:sysid_control_slave_translator_avalon_universal_slave_0_agent| ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_agent:sysid_control_slave_translator_avalon_universal_slave_0_agent ; ; -; |altera_merlin_slave_translator:cpu_jtag_debug_module_translator| ; 41 (41) ; 37 (37) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 4 (4) ; 0 (0) ; 37 (37) ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_translator:cpu_jtag_debug_module_translator ; ; +; |altera_merlin_slave_translator:cpu_jtag_debug_module_translator| ; 41 (41) ; 37 (37) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 38 (38) ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_translator:cpu_jtag_debug_module_translator ; ; ; |altera_merlin_slave_translator:jtag_uart_0_avalon_jtag_slave_translator| ; 23 (23) ; 23 (23) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 2 (2) ; 21 (21) ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_translator:jtag_uart_0_avalon_jtag_slave_translator ; ; ; |altera_merlin_slave_translator:pio_ir_emitter_s1_translator| ; 7 (7) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 1 (1) ; 3 (3) ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_translator:pio_ir_emitter_s1_translator ; ; -; |altera_merlin_slave_translator:pio_key_left_s1_translator| ; 10 (10) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 6 (6) ; 2 (2) ; 2 (2) ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_translator:pio_key_left_s1_translator ; ; +; |altera_merlin_slave_translator:pio_key_left_s1_translator| ; 10 (10) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 6 (6) ; 1 (1) ; 3 (3) ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_translator:pio_key_left_s1_translator ; ; ; |altera_merlin_slave_translator:pio_led_s1_translator| ; 14 (14) ; 10 (10) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 4 (4) ; 1 (1) ; 9 (9) ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_translator:pio_led_s1_translator ; ; ; |altera_merlin_slave_translator:pio_sw_s1_translator| ; 9 (9) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 7 (7) ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_translator:pio_sw_s1_translator ; ; ; |altera_merlin_slave_translator:rs232_wifi_avalon_rs232_slave_translator| ; 3 (3) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 1 (1) ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_translator:rs232_wifi_avalon_rs232_slave_translator ; ; -; |altera_merlin_slave_translator:sys_clk_timer_s1_translator| ; 25 (25) ; 19 (19) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 6 (6) ; 8 (8) ; 11 (11) ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_translator:sys_clk_timer_s1_translator ; ; -; |altera_merlin_slave_translator:sysid_control_slave_translator| ; 8 (8) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 4 (4) ; 0 (0) ; 4 (4) ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_translator:sysid_control_slave_translator ; ; +; |altera_merlin_slave_translator:sys_clk_timer_s1_translator| ; 24 (24) ; 19 (19) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 5 (5) ; 8 (8) ; 11 (11) ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_translator:sys_clk_timer_s1_translator ; ; +; |altera_merlin_slave_translator:sysid_control_slave_translator| ; 9 (9) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 5 (5) ; 1 (1) ; 3 (3) ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_translator:sysid_control_slave_translator ; ; ; |altera_merlin_slave_translator:uart_mc_s1_translator| ; 17 (17) ; 14 (14) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 14 (14) ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_translator:uart_mc_s1_translator ; ; ; |altera_merlin_slave_translator:uart_wifi_s1_translator| ; 23 (23) ; 20 (20) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 4 (4) ; 16 (16) ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_translator:uart_wifi_s1_translator ; ; -; |altera_merlin_traffic_limiter:limiter_001| ; 40 (40) ; 21 (21) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 19 (19) ; 0 (0) ; 21 (21) ; |de0_nano_system|system:inst_cpu|altera_merlin_traffic_limiter:limiter_001 ; ; -; |altera_merlin_traffic_limiter:limiter| ; 14 (14) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 7 (7) ; 0 (0) ; 7 (7) ; |de0_nano_system|system:inst_cpu|altera_merlin_traffic_limiter:limiter ; ; +; |altera_merlin_traffic_limiter:limiter_001| ; 40 (40) ; 21 (21) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 19 (19) ; 1 (1) ; 20 (20) ; |de0_nano_system|system:inst_cpu|altera_merlin_traffic_limiter:limiter_001 ; ; +; |altera_merlin_traffic_limiter:limiter| ; 14 (14) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 6 (6) ; 0 (0) ; 8 (8) ; |de0_nano_system|system:inst_cpu|altera_merlin_traffic_limiter:limiter ; ; ; |altera_merlin_width_adapter:width_adapter_001| ; 32 (32) ; 16 (16) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 16 (16) ; 0 (0) ; 16 (16) ; |de0_nano_system|system:inst_cpu|altera_merlin_width_adapter:width_adapter_001 ; ; -; |altera_merlin_width_adapter:width_adapter| ; 72 (72) ; 44 (44) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 27 (27) ; 10 (10) ; 35 (35) ; |de0_nano_system|system:inst_cpu|altera_merlin_width_adapter:width_adapter ; ; +; |altera_merlin_width_adapter:width_adapter| ; 75 (75) ; 44 (44) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 18 (18) ; 8 (8) ; 49 (49) ; |de0_nano_system|system:inst_cpu|altera_merlin_width_adapter:width_adapter ; ; ; |altera_reset_controller:rst_controller| ; 4 (1) ; 3 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 2 (0) ; 1 (0) ; |de0_nano_system|system:inst_cpu|altera_reset_controller:rst_controller ; ; ; |altera_reset_synchronizer:alt_rst_sync_uq1| ; 3 (3) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 2 (2) ; 1 (1) ; |de0_nano_system|system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1 ; ; -; |system_addr_router:addr_router| ; 5 (5) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 3 (3) ; |de0_nano_system|system:inst_cpu|system_addr_router:addr_router ; ; -; |system_addr_router_001:addr_router_001| ; 45 (45) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 31 (31) ; 0 (0) ; 14 (14) ; |de0_nano_system|system:inst_cpu|system_addr_router_001:addr_router_001 ; ; +; |system_addr_router:addr_router| ; 5 (5) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 4 (4) ; |de0_nano_system|system:inst_cpu|system_addr_router:addr_router ; ; +; |system_addr_router_001:addr_router_001| ; 45 (45) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 32 (32) ; 0 (0) ; 13 (13) ; |de0_nano_system|system:inst_cpu|system_addr_router_001:addr_router_001 ; ; ; |system_cmd_xbar_demux:cmd_xbar_demux| ; 5 (5) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 5 (5) ; 0 (0) ; 0 (0) ; |de0_nano_system|system:inst_cpu|system_cmd_xbar_demux:cmd_xbar_demux ; ; -; |system_cmd_xbar_demux_001:cmd_xbar_demux_001| ; 21 (21) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 19 (19) ; 0 (0) ; 2 (2) ; |de0_nano_system|system:inst_cpu|system_cmd_xbar_demux_001:cmd_xbar_demux_001 ; ; -; |system_cmd_xbar_mux:cmd_xbar_mux_001| ; 51 (48) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 28 (27) ; 1 (1) ; 22 (19) ; |de0_nano_system|system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux_001 ; ; -; |altera_merlin_arbitrator:arb| ; 4 (4) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 3 (3) ; |de0_nano_system|system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux_001|altera_merlin_arbitrator:arb ; ; -; |system_cmd_xbar_mux:cmd_xbar_mux| ; 57 (53) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 50 (48) ; 1 (1) ; 6 (4) ; |de0_nano_system|system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux ; ; +; |system_cmd_xbar_demux_001:cmd_xbar_demux_001| ; 21 (21) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 20 (20) ; 0 (0) ; 1 (1) ; |de0_nano_system|system:inst_cpu|system_cmd_xbar_demux_001:cmd_xbar_demux_001 ; ; +; |system_cmd_xbar_mux:cmd_xbar_mux_001| ; 52 (48) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 23 (21) ; 2 (2) ; 27 (25) ; |de0_nano_system|system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux_001 ; ; +; |altera_merlin_arbitrator:arb| ; 4 (4) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 2 (2) ; |de0_nano_system|system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux_001|altera_merlin_arbitrator:arb ; ; +; |system_cmd_xbar_mux:cmd_xbar_mux| ; 57 (53) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 49 (47) ; 0 (0) ; 8 (6) ; |de0_nano_system|system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux ; ; ; |altera_merlin_arbitrator:arb| ; 4 (4) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 2 (2) ; |de0_nano_system|system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux|altera_merlin_arbitrator:arb ; ; -; |system_cpu:cpu| ; 2634 (2271) ; 1596 (1408) ; 0 (0) ; 116736 ; 20 ; 4 ; 0 ; 2 ; 0 ; 0 ; 1010 (865) ; 447 (391) ; 1177 (1014) ; |de0_nano_system|system:inst_cpu|system_cpu:cpu ; ; -; |lpm_add_sub:Add17| ; 66 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 63 (0) ; 0 (0) ; 3 (0) ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|lpm_add_sub:Add17 ; ; -; |add_sub_qvi:auto_generated| ; 66 (66) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 63 (63) ; 0 (0) ; 3 (3) ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|lpm_add_sub:Add17|add_sub_qvi:auto_generated ; ; +; |system_cpu:cpu| ; 2591 (2228) ; 1596 (1408) ; 0 (0) ; 116736 ; 20 ; 4 ; 0 ; 2 ; 0 ; 0 ; 967 (823) ; 401 (346) ; 1223 (1059) ; |de0_nano_system|system:inst_cpu|system_cpu:cpu ; ; +; |lpm_add_sub:Add17| ; 66 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 62 (0) ; 0 (0) ; 4 (0) ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|lpm_add_sub:Add17 ; ; +; |add_sub_qvi:auto_generated| ; 66 (66) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 62 (62) ; 0 (0) ; 4 (4) ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|lpm_add_sub:Add17|add_sub_qvi:auto_generated ; ; ; |system_cpu_bht_module:system_cpu_bht| ; 0 (0) ; 0 (0) ; 0 (0) ; 512 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_bht_module:system_cpu_bht ; ; ; |altsyncram:the_altsyncram| ; 0 (0) ; 0 (0) ; 0 (0) ; 512 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_bht_module:system_cpu_bht|altsyncram:the_altsyncram ; ; ; |altsyncram_fhg1:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 512 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_bht_module:system_cpu_bht|altsyncram:the_altsyncram|altsyncram_fhg1:auto_generated ; ; @@ -1380,9 +1380,9 @@ Note: Pin directions (input, output or bidir) are based on device operating in u ; |system_cpu_dc_victim_module:system_cpu_dc_victim| ; 0 (0) ; 0 (0) ; 0 (0) ; 256 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_dc_victim_module:system_cpu_dc_victim ; ; ; |altsyncram:the_altsyncram| ; 0 (0) ; 0 (0) ; 0 (0) ; 256 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_dc_victim_module:system_cpu_dc_victim|altsyncram:the_altsyncram ; ; ; |altsyncram_r3d1:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 256 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_dc_victim_module:system_cpu_dc_victim|altsyncram:the_altsyncram|altsyncram_r3d1:auto_generated ; ; -; |system_cpu_ic_data_module:system_cpu_ic_data| ; 2 (0) ; 1 (0) ; 0 (0) ; 65536 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 1 (0) ; 0 (0) ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data ; ; -; |altsyncram:the_altsyncram| ; 2 (0) ; 1 (0) ; 0 (0) ; 65536 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 1 (0) ; 0 (0) ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram ; ; -; |altsyncram_sjd1:auto_generated| ; 2 (2) ; 1 (1) ; 0 (0) ; 65536 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 1 (1) ; 0 (0) ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated ; ; +; |system_cpu_ic_data_module:system_cpu_ic_data| ; 2 (0) ; 1 (0) ; 0 (0) ; 65536 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 1 (0) ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data ; ; +; |altsyncram:the_altsyncram| ; 2 (0) ; 1 (0) ; 0 (0) ; 65536 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 1 (0) ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram ; ; +; |altsyncram_sjd1:auto_generated| ; 2 (2) ; 1 (1) ; 0 (0) ; 65536 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 1 (1) ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated ; ; ; |system_cpu_ic_tag_module:system_cpu_ic_tag| ; 0 (0) ; 0 (0) ; 0 (0) ; 5376 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag ; ; ; |altsyncram:the_altsyncram| ; 0 (0) ; 0 (0) ; 0 (0) ; 5376 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram ; ; ; |altsyncram_qtg1:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 5376 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated ; ; @@ -1416,8 +1416,8 @@ Note: Pin directions (input, output or bidir) are based on device operating in u ; |altsyncram:the_altsyncram| ; 0 (0) ; 0 (0) ; 0 (0) ; 1024 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_register_bank_b_module:system_cpu_register_bank_b|altsyncram:the_altsyncram ; ; ; |altsyncram_gvf1:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 1024 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_register_bank_b_module:system_cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_gvf1:auto_generated ; ; ; |system_cpu_test_bench:the_system_cpu_test_bench| ; 10 (10) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 10 (10) ; 0 (0) ; 0 (0) ; |de0_nano_system|system:inst_cpu|system_cpu:cpu|system_cpu_test_bench:the_system_cpu_test_bench ; ; -; |system_jtag_uart_0:jtag_uart_0| ; 160 (41) ; 104 (13) ; 0 (0) ; 1024 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 48 (20) ; 19 (3) ; 93 (17) ; |de0_nano_system|system:inst_cpu|system_jtag_uart_0:jtag_uart_0 ; ; -; |alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic| ; 69 (69) ; 51 (51) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 17 (17) ; 16 (16) ; 36 (36) ; |de0_nano_system|system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic ; ; +; |system_jtag_uart_0:jtag_uart_0| ; 163 (42) ; 104 (13) ; 0 (0) ; 1024 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 51 (21) ; 22 (5) ; 90 (16) ; |de0_nano_system|system:inst_cpu|system_jtag_uart_0:jtag_uart_0 ; ; +; |alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic| ; 70 (70) ; 51 (51) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 19 (19) ; 17 (17) ; 34 (34) ; |de0_nano_system|system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic ; ; ; |system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r| ; 26 (0) ; 20 (0) ; 0 (0) ; 512 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 6 (0) ; 0 (0) ; 20 (0) ; |de0_nano_system|system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r ; ; ; |scfifo:rfifo| ; 26 (0) ; 20 (0) ; 0 (0) ; 512 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 6 (0) ; 0 (0) ; 20 (0) ; |de0_nano_system|system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo ; ; ; |scfifo_jr21:auto_generated| ; 26 (0) ; 20 (0) ; 0 (0) ; 512 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 6 (0) ; 0 (0) ; 20 (0) ; |de0_nano_system|system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated ; ; @@ -1464,20 +1464,20 @@ Note: Pin directions (input, output or bidir) are based on device operating in u ; |cntr_ca7:usedw_counter| ; 8 (8) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 7 (7) ; |de0_nano_system|system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_ca7:usedw_counter ; ; ; |cntr_v9b:rd_ptr_msb| ; 7 (7) ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 6 (6) ; |de0_nano_system|system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_v9b:rd_ptr_msb ; ; ; |system_rsp_xbar_demux:rsp_xbar_demux_001| ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; |de0_nano_system|system:inst_cpu|system_rsp_xbar_demux:rsp_xbar_demux_001 ; ; -; |system_rsp_xbar_demux:rsp_xbar_demux| ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 1 (1) ; |de0_nano_system|system:inst_cpu|system_rsp_xbar_demux:rsp_xbar_demux ; ; +; |system_rsp_xbar_demux:rsp_xbar_demux| ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; |de0_nano_system|system:inst_cpu|system_rsp_xbar_demux:rsp_xbar_demux ; ; ; |system_rsp_xbar_mux:rsp_xbar_mux| ; 34 (34) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 33 (33) ; |de0_nano_system|system:inst_cpu|system_rsp_xbar_mux:rsp_xbar_mux ; ; -; |system_rsp_xbar_mux_001:rsp_xbar_mux_001| ; 129 (129) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 55 (55) ; 0 (0) ; 74 (74) ; |de0_nano_system|system:inst_cpu|system_rsp_xbar_mux_001:rsp_xbar_mux_001 ; ; -; |system_sdram:sdram| ; 334 (234) ; 210 (122) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 124 (112) ; 58 (15) ; 152 (109) ; |de0_nano_system|system:inst_cpu|system_sdram:sdram ; ; -; |system_sdram_input_efifo_module:the_system_sdram_input_efifo_module| ; 100 (100) ; 88 (88) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 12 (12) ; 43 (43) ; 45 (45) ; |de0_nano_system|system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module ; ; -; |system_sys_clk_timer:sys_clk_timer| ; 154 (154) ; 120 (120) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 34 (34) ; 22 (22) ; 98 (98) ; |de0_nano_system|system:inst_cpu|system_sys_clk_timer:sys_clk_timer ; ; +; |system_rsp_xbar_mux_001:rsp_xbar_mux_001| ; 125 (125) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 52 (52) ; 0 (0) ; 73 (73) ; |de0_nano_system|system:inst_cpu|system_rsp_xbar_mux_001:rsp_xbar_mux_001 ; ; +; |system_sdram:sdram| ; 342 (230) ; 210 (122) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 132 (108) ; 53 (10) ; 157 (112) ; |de0_nano_system|system:inst_cpu|system_sdram:sdram ; ; +; |system_sdram_input_efifo_module:the_system_sdram_input_efifo_module| ; 114 (114) ; 88 (88) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 24 (24) ; 43 (43) ; 47 (47) ; |de0_nano_system|system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module ; ; +; |system_sys_clk_timer:sys_clk_timer| ; 158 (158) ; 120 (120) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 38 (38) ; 26 (26) ; 94 (94) ; |de0_nano_system|system:inst_cpu|system_sys_clk_timer:sys_clk_timer ; ; ; |system_uart_mc:uart_mc| ; 150 (0) ; 102 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 48 (0) ; 16 (0) ; 86 (0) ; |de0_nano_system|system:inst_cpu|system_uart_mc:uart_mc ; ; -; |system_uart_mc_regs:the_system_uart_mc_regs| ; 44 (44) ; 29 (29) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 8 (8) ; 11 (11) ; 25 (25) ; |de0_nano_system|system:inst_cpu|system_uart_mc:uart_mc|system_uart_mc_regs:the_system_uart_mc_regs ; ; -; |system_uart_mc_rx:the_system_uart_mc_rx| ; 68 (66) ; 42 (40) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 26 (26) ; 4 (2) ; 38 (38) ; |de0_nano_system|system:inst_cpu|system_uart_mc:uart_mc|system_uart_mc_rx:the_system_uart_mc_rx ; ; +; |system_uart_mc_regs:the_system_uart_mc_regs| ; 43 (43) ; 29 (29) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 7 (7) ; 10 (10) ; 26 (26) ; |de0_nano_system|system:inst_cpu|system_uart_mc:uart_mc|system_uart_mc_regs:the_system_uart_mc_regs ; ; +; |system_uart_mc_rx:the_system_uart_mc_rx| ; 69 (67) ; 42 (40) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 27 (27) ; 5 (3) ; 37 (37) ; |de0_nano_system|system:inst_cpu|system_uart_mc:uart_mc|system_uart_mc_rx:the_system_uart_mc_rx ; ; ; |altera_std_synchronizer:the_altera_std_synchronizer| ; 2 (2) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 2 (2) ; 0 (0) ; |de0_nano_system|system:inst_cpu|system_uart_mc:uart_mc|system_uart_mc_rx:the_system_uart_mc_rx|altera_std_synchronizer:the_altera_std_synchronizer ; ; ; |system_uart_mc_tx:the_system_uart_mc_tx| ; 45 (45) ; 31 (31) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 14 (14) ; 1 (1) ; 30 (30) ; |de0_nano_system|system:inst_cpu|system_uart_mc:uart_mc|system_uart_mc_tx:the_system_uart_mc_tx ; ; -; |system_uart_wifi:uart_wifi| ; 183 (0) ; 126 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 57 (0) ; 22 (0) ; 104 (0) ; |de0_nano_system|system:inst_cpu|system_uart_wifi:uart_wifi ; ; +; |system_uart_wifi:uart_wifi| ; 185 (0) ; 126 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 59 (0) ; 24 (0) ; 102 (0) ; |de0_nano_system|system:inst_cpu|system_uart_wifi:uart_wifi ; ; ; |system_uart_wifi_regs:the_system_uart_wifi_regs| ; 75 (75) ; 51 (51) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 16 (16) ; 20 (20) ; 39 (39) ; |de0_nano_system|system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_regs:the_system_uart_wifi_regs ; ; -; |system_uart_wifi_rx:the_system_uart_wifi_rx| ; 72 (70) ; 44 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 28 (28) ; 1 (0) ; 43 (42) ; |de0_nano_system|system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_rx:the_system_uart_wifi_rx ; ; +; |system_uart_wifi_rx:the_system_uart_wifi_rx| ; 74 (72) ; 44 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 30 (30) ; 3 (2) ; 41 (40) ; |de0_nano_system|system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_rx:the_system_uart_wifi_rx ; ; ; |altera_std_synchronizer:the_altera_std_synchronizer| ; 2 (2) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 1 (1) ; |de0_nano_system|system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_rx:the_system_uart_wifi_rx|altera_std_synchronizer:the_altera_std_synchronizer ; ; ; |system_uart_wifi_tx:the_system_uart_wifi_tx| ; 44 (44) ; 31 (31) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 13 (13) ; 1 (1) ; 30 (30) ; |de0_nano_system|system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_tx:the_system_uart_wifi_tx ; ; +----------------------------------------------------------------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+ @@ -1603,7 +1603,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; GPIO_0[31] ; Bidir ; (6) 1314 ps ; -- ; -- ; -- ; -- ; ; GPIO_0[33] ; Bidir ; -- ; -- ; -- ; -- ; -- ; ; GPIO_1[0] ; Bidir ; -- ; -- ; -- ; -- ; -- ; -; GPIO_1[31] ; Bidir ; (6) 1314 ps ; -- ; -- ; -- ; -- ; +; GPIO_1[31] ; Bidir ; -- ; (6) 1314 ps ; -- ; -- ; -- ; ; GPIO_1[33] ; Bidir ; -- ; -- ; -- ; -- ; -- ; ; CLOCK_50 ; Input ; -- ; -- ; -- ; -- ; -- ; ; KEY[1] ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; @@ -1614,106 +1614,106 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +---------------+----------+---------------+---------------+-----------------------+----------+----------+ -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Pad To Core Delay Chain Fanout ; -+---------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+---------+ -; Source Pin / Fanout ; Pad To Core Index ; Setting ; -+---------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+---------+ -; KEY[0] ; ; ; -; GPIO_0[0] ; ; ; -; GPIO_0[1] ; ; ; -; GPIO_0[2] ; ; ; -; GPIO_0[3] ; ; ; -; GPIO_0[4] ; ; ; -; GPIO_0[5] ; ; ; -; GPIO_0[6] ; ; ; -; GPIO_0[7] ; ; ; -; GPIO_0[8] ; ; ; -; GPIO_0[9] ; ; ; -; GPIO_0[10] ; ; ; -; GPIO_0[11] ; ; ; -; GPIO_0[12] ; ; ; -; GPIO_0[13] ; ; ; -; GPIO_0[14] ; ; ; -; GPIO_0[15] ; ; ; -; GPIO_0[16] ; ; ; -; GPIO_0[17] ; ; ; -; GPIO_0[18] ; ; ; -; GPIO_0[19] ; ; ; -; GPIO_0[20] ; ; ; -; GPIO_0[21] ; ; ; -; GPIO_0[22] ; ; ; -; GPIO_0[23] ; ; ; -; GPIO_0[24] ; ; ; -; GPIO_0[25] ; ; ; -; GPIO_0[26] ; ; ; -; GPIO_0[27] ; ; ; -; GPIO_0[28] ; ; ; -; GPIO_0[29] ; ; ; -; GPIO_0[30] ; ; ; -; GPIO_0[32] ; ; ; -; GPIO_1[1] ; ; ; -; GPIO_1[2] ; ; ; -; GPIO_1[3] ; ; ; -; GPIO_1[4] ; ; ; -; GPIO_1[5] ; ; ; -; GPIO_1[6] ; ; ; -; GPIO_1[7] ; ; ; -; GPIO_1[8] ; ; ; -; GPIO_1[9] ; ; ; -; GPIO_1[10] ; ; ; -; GPIO_1[11] ; ; ; -; GPIO_1[12] ; ; ; -; GPIO_1[13] ; ; ; -; GPIO_1[14] ; ; ; -; GPIO_1[15] ; ; ; -; GPIO_1[16] ; ; ; -; GPIO_1[17] ; ; ; -; GPIO_1[18] ; ; ; -; GPIO_1[19] ; ; ; -; GPIO_1[20] ; ; ; -; GPIO_1[21] ; ; ; -; GPIO_1[22] ; ; ; -; GPIO_1[23] ; ; ; -; GPIO_1[24] ; ; ; -; GPIO_1[25] ; ; ; -; GPIO_1[26] ; ; ; -; GPIO_1[27] ; ; ; -; GPIO_1[28] ; ; ; -; GPIO_1[29] ; ; ; -; GPIO_1[30] ; ; ; -; GPIO_1[32] ; ; ; -; DRAM_DQ[0] ; ; ; -; DRAM_DQ[1] ; ; ; -; DRAM_DQ[2] ; ; ; -; DRAM_DQ[3] ; ; ; -; DRAM_DQ[4] ; ; ; -; DRAM_DQ[5] ; ; ; -; DRAM_DQ[6] ; ; ; -; DRAM_DQ[7] ; ; ; -; DRAM_DQ[8] ; ; ; -; DRAM_DQ[9] ; ; ; -; DRAM_DQ[10] ; ; ; -; DRAM_DQ[11] ; ; ; -; DRAM_DQ[12] ; ; ; -; DRAM_DQ[13] ; ; ; -; DRAM_DQ[14] ; ; ; -; DRAM_DQ[15] ; ; ; -; GPIO_0[31] ; ; ; -; - system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|data_in_shift_reg~9 ; 0 ; 6 ; -; - system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|receiving_data~0 ; 0 ; 6 ; -; GPIO_0[33] ; ; ; -; GPIO_1[0] ; ; ; -; GPIO_1[31] ; ; ; -; - system:inst_cpu|system_uart_mc:uart_mc|system_uart_mc_rx:the_system_uart_mc_rx|altera_std_synchronizer:the_altera_std_synchronizer|din_s1~feeder ; 0 ; 6 ; -; GPIO_1[33] ; ; ; -; CLOCK_50 ; ; ; -; KEY[1] ; ; ; -; SW[3] ; ; ; -; SW[2] ; ; ; -; SW[1] ; ; ; -; SW[0] ; ; ; -+---------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+---------+ ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Pad To Core Delay Chain Fanout ; ++--------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+---------+ +; Source Pin / Fanout ; Pad To Core Index ; Setting ; ++--------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+---------+ +; KEY[0] ; ; ; +; GPIO_0[0] ; ; ; +; GPIO_0[1] ; ; ; +; GPIO_0[2] ; ; ; +; GPIO_0[3] ; ; ; +; GPIO_0[4] ; ; ; +; GPIO_0[5] ; ; ; +; GPIO_0[6] ; ; ; +; GPIO_0[7] ; ; ; +; GPIO_0[8] ; ; ; +; GPIO_0[9] ; ; ; +; GPIO_0[10] ; ; ; +; GPIO_0[11] ; ; ; +; GPIO_0[12] ; ; ; +; GPIO_0[13] ; ; ; +; GPIO_0[14] ; ; ; +; GPIO_0[15] ; ; ; +; GPIO_0[16] ; ; ; +; GPIO_0[17] ; ; ; +; GPIO_0[18] ; ; ; +; GPIO_0[19] ; ; ; +; GPIO_0[20] ; ; ; +; GPIO_0[21] ; ; ; +; GPIO_0[22] ; ; ; +; GPIO_0[23] ; ; ; +; GPIO_0[24] ; ; ; +; GPIO_0[25] ; ; ; +; GPIO_0[26] ; ; ; +; GPIO_0[27] ; ; ; +; GPIO_0[28] ; ; ; +; GPIO_0[29] ; ; ; +; GPIO_0[30] ; ; ; +; GPIO_0[32] ; ; ; +; GPIO_1[1] ; ; ; +; GPIO_1[2] ; ; ; +; GPIO_1[3] ; ; ; +; GPIO_1[4] ; ; ; +; GPIO_1[5] ; ; ; +; GPIO_1[6] ; ; ; +; GPIO_1[7] ; ; ; +; GPIO_1[8] ; ; ; +; GPIO_1[9] ; ; ; +; GPIO_1[10] ; ; ; +; GPIO_1[11] ; ; ; +; GPIO_1[12] ; ; ; +; GPIO_1[13] ; ; ; +; GPIO_1[14] ; ; ; +; GPIO_1[15] ; ; ; +; GPIO_1[16] ; ; ; +; GPIO_1[17] ; ; ; +; GPIO_1[18] ; ; ; +; GPIO_1[19] ; ; ; +; GPIO_1[20] ; ; ; +; GPIO_1[21] ; ; ; +; GPIO_1[22] ; ; ; +; GPIO_1[23] ; ; ; +; GPIO_1[24] ; ; ; +; GPIO_1[25] ; ; ; +; GPIO_1[26] ; ; ; +; GPIO_1[27] ; ; ; +; GPIO_1[28] ; ; ; +; GPIO_1[29] ; ; ; +; GPIO_1[30] ; ; ; +; GPIO_1[32] ; ; ; +; DRAM_DQ[0] ; ; ; +; DRAM_DQ[1] ; ; ; +; DRAM_DQ[2] ; ; ; +; DRAM_DQ[3] ; ; ; +; DRAM_DQ[4] ; ; ; +; DRAM_DQ[5] ; ; ; +; DRAM_DQ[6] ; ; ; +; DRAM_DQ[7] ; ; ; +; DRAM_DQ[8] ; ; ; +; DRAM_DQ[9] ; ; ; +; DRAM_DQ[10] ; ; ; +; DRAM_DQ[11] ; ; ; +; DRAM_DQ[12] ; ; ; +; DRAM_DQ[13] ; ; ; +; DRAM_DQ[14] ; ; ; +; DRAM_DQ[15] ; ; ; +; GPIO_0[31] ; ; ; +; - system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|data_in_shift_reg~9 ; 0 ; 6 ; +; - system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|receiving_data~0 ; 0 ; 6 ; +; GPIO_0[33] ; ; ; +; GPIO_1[0] ; ; ; +; GPIO_1[31] ; ; ; +; - system:inst_cpu|system_uart_mc:uart_mc|system_uart_mc_rx:the_system_uart_mc_rx|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 ; 1 ; 6 ; +; GPIO_1[33] ; ; ; +; CLOCK_50 ; ; ; +; KEY[1] ; ; ; +; SW[3] ; ; ; +; SW[2] ; ; ; +; SW[1] ; ; ; +; SW[0] ; ; ; ++--------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+---------+ +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ @@ -1722,154 +1722,154 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------+---------+----------------------------------------------------+--------+----------------------+------------------+---------------------------+ ; CLOCK_50 ; PIN_R8 ; 1 ; Clock ; no ; -- ; -- ; -- ; -; altera_internal_jtag~TCKUTAP ; JTAG_X1_Y17_N0 ; 183 ; Clock ; yes ; Global Clock ; GCLK0 ; -- ; +; altera_internal_jtag~TCKUTAP ; JTAG_X1_Y17_N0 ; 183 ; Clock ; yes ; Global Clock ; GCLK1 ; -- ; ; altera_internal_jtag~TMSUTAP ; JTAG_X1_Y17_N0 ; 21 ; Sync. clear ; no ; -- ; -- ; -- ; ; pll_sys:inst_pll_sys|altpll:altpll_component|pll_sys_altpll:auto_generated|wire_pll1_clk[0] ; PLL_4 ; 2811 ; Clock ; yes ; Global Clock ; GCLK18 ; -- ; ; pll_sys:inst_pll_sys|altpll:altpll_component|pll_sys_altpll:auto_generated|wire_pll1_clk[2] ; PLL_4 ; 22 ; Clock ; yes ; Global Clock ; GCLK19 ; -- ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; FF_X10_Y13_N1 ; 70 ; Async. clear ; yes ; Global Clock ; GCLK3 ; -- ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_proc~0 ; LCCOMB_X10_Y12_N24 ; 4 ; Sync. load ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_info_reg_ena ; LCCOMB_X10_Y12_N4 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_info_reg_ena~0 ; LCCOMB_X11_Y14_N4 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[0]~2 ; LCCOMB_X10_Y14_N2 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[0]~0 ; LCCOMB_X10_Y14_N0 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]~5 ; LCCOMB_X12_Y13_N14 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]~12 ; LCCOMB_X12_Y13_N30 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2]~3 ; LCCOMB_X14_Y13_N6 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[0]~14 ; LCCOMB_X11_Y12_N2 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[0]~19 ; LCCOMB_X11_Y12_N0 ; 5 ; Sync. load ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena~3 ; LCCOMB_X12_Y14_N16 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][0]~2 ; LCCOMB_X12_Y13_N22 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][0]~9 ; LCCOMB_X12_Y13_N18 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[0]~19 ; LCCOMB_X11_Y14_N16 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[4]~22 ; LCCOMB_X14_Y14_N16 ; 5 ; Sync. clear ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[4]~23 ; LCCOMB_X14_Y14_N14 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; FF_X12_Y15_N11 ; 12 ; Async. clear ; yes ; Global Clock ; GCLK4 ; -- ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[11] ; FF_X12_Y15_N15 ; 12 ; Clock enable ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; FF_X12_Y15_N19 ; 39 ; Sync. load ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; FF_X12_Y15_N7 ; 46 ; Sync. clear ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; FF_X12_Y14_N5 ; 13 ; Async. clear ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_dr_scan_proc~0 ; LCCOMB_X12_Y15_N0 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; FF_X14_Y15_N5 ; 30 ; Async. clear ; no ; -- ; -- ; -- ; -; system:inst_cpu|altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]~1 ; LCCOMB_X28_Y15_N18 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|always0~0 ; LCCOMB_X21_Y9_N24 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|always1~0 ; LCCOMB_X20_Y9_N10 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|always2~0 ; LCCOMB_X20_Y9_N0 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|always3~0 ; LCCOMB_X20_Y9_N16 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|always4~0 ; LCCOMB_X19_Y9_N26 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|always5~0 ; LCCOMB_X20_Y9_N12 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|always6~0 ; LCCOMB_X19_Y9_N6 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[6]~2 ; LCCOMB_X20_Y9_N4 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent|comb~0 ; LCCOMB_X20_Y9_N6 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent|rp_valid ; LCCOMB_X21_Y9_N20 ; 20 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|altera_merlin_slave_translator:cpu_jtag_debug_module_translator|waitrequest_reset_override ; FF_X21_Y16_N11 ; 22 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|altera_merlin_traffic_limiter:limiter_001|pending_response_count[3]~14 ; LCCOMB_X28_Y14_N30 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|altera_merlin_traffic_limiter:limiter_001|save_dest_id~0 ; LCCOMB_X27_Y16_N14 ; 16 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|altera_merlin_traffic_limiter:limiter|pending_response_count[3]~8 ; LCCOMB_X24_Y16_N2 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|altera_merlin_traffic_limiter:limiter|save_dest_id~0 ; LCCOMB_X19_Y19_N12 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|altera_merlin_width_adapter:width_adapter|byteen_reg[1]~0 ; LCCOMB_X19_Y8_N24 ; 40 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|altera_merlin_width_adapter:width_adapter|use_reg ; FF_X19_Y8_N3 ; 76 ; Clock enable, Sync. clear, Sync. load ; no ; -- ; -- ; -- ; -; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; FF_X28_Y1_N5 ; 2347 ; Async. clear, Async. load ; yes ; Global Clock ; GCLK16 ; -- ; -; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; FF_X28_Y1_N5 ; 162 ; Clock enable, Sync. clear, Sync. load ; no ; -- ; -- ; -- ; -; system:inst_cpu|altera_reset_controller:rst_controller|merged_reset~0 ; LCCOMB_X52_Y17_N16 ; 3 ; Async. clear ; yes ; Global Clock ; GCLK7 ; -- ; -; system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux_001|altera_merlin_arbitrator:arb|top_priority_reg[0]~0 ; LCCOMB_X20_Y8_N14 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux_001|update_grant~0 ; LCCOMB_X20_Y8_N18 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux|altera_merlin_arbitrator:arb|top_priority_reg[0]~0 ; LCCOMB_X20_Y16_N8 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux|src_data[46] ; LCCOMB_X21_Y15_N10 ; 35 ; Sync. load ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux|update_grant~2 ; LCCOMB_X21_Y16_N6 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_cpu:cpu|A_dc_rd_addr_cnt[0]~1 ; LCCOMB_X30_Y17_N4 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_cpu:cpu|A_dc_rd_data_cnt[0]~0 ; LCCOMB_X32_Y19_N24 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_cpu:cpu|A_dc_rd_data_cnt[0]~1 ; LCCOMB_X32_Y19_N14 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_cpu:cpu|A_dc_wb_en ; LCCOMB_X21_Y17_N0 ; 4 ; Clock enable, Read enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_cpu:cpu|A_dc_wb_update_av_writedata ; LCCOMB_X27_Y16_N24 ; 32 ; Sync. load ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_cpu:cpu|A_dc_wb_wr_want_dmaster ; LCCOMB_X31_Y17_N0 ; 21 ; Sync. load ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_cpu:cpu|A_dc_wr_data_cnt[3]~0 ; LCCOMB_X31_Y17_N8 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_cpu:cpu|A_dc_xfer_rd_data_starting ; FF_X34_Y20_N5 ; 22 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_cpu:cpu|A_dc_xfer_wr_active ; FF_X34_Y17_N3 ; 1 ; Write enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_cpu:cpu|A_ienable_reg_irq0~0 ; LCCOMB_X24_Y18_N30 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_cpu:cpu|A_ld_align_byte1_fill ; FF_X30_Y20_N11 ; 9 ; Sync. load ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_cpu:cpu|A_ld_align_sh8 ; FF_X28_Y19_N17 ; 10 ; Sync. load ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_cpu:cpu|A_mul_stall_d3 ; FF_X16_Y22_N1 ; 32 ; Sync. load ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_cpu:cpu|A_slow_inst_result_en~0 ; LCCOMB_X30_Y18_N2 ; 32 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_cpu:cpu|A_stall~0 ; LCCOMB_X31_Y20_N0 ; 742 ; Clock enable, Sync. clear ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_cpu:cpu|A_wr_dst_reg_from_M ; FF_X21_Y26_N13 ; 4 ; Write enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_cpu:cpu|Add8~5 ; LCCOMB_X30_Y26_N24 ; 32 ; Sync. load ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_cpu:cpu|D_ctrl_src2_choose_imm ; FF_X21_Y25_N27 ; 33 ; Sync. load ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_cpu:cpu|D_ic_fill_starting~1 ; LCCOMB_X19_Y24_N28 ; 25 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_cpu:cpu|E_hbreak_req ; LCCOMB_X23_Y20_N8 ; 30 ; Sync. load ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_cpu:cpu|E_iw[0] ; FF_X24_Y21_N13 ; 18 ; Sync. clear ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_cpu:cpu|E_iw[4] ; FF_X24_Y22_N31 ; 34 ; Sync. load ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_cpu:cpu|F_stall ; LCCOMB_X20_Y24_N30 ; 175 ; Clock enable, Read enable, Sync. clear, Sync. load ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_cpu:cpu|M_bht_wr_en_unfiltered ; LCCOMB_X28_Y24_N6 ; 1 ; Write enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_cpu:cpu|M_br_cond_taken_history[0]~0 ; LCCOMB_X25_Y24_N8 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_cpu:cpu|M_ctrl_rdctl_inst ; FF_X23_Y20_N15 ; 32 ; Sync. clear, Sync. load ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_cpu:cpu|M_pipe_flush ; FF_X25_Y24_N19 ; 52 ; Sync. load ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_cpu:cpu|M_rot_rn[3] ; FF_X30_Y26_N29 ; 32 ; Sync. load ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_cpu:cpu|always142~0 ; LCCOMB_X31_Y20_N30 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_cpu:cpu|d_address_offset_field[0]~2 ; LCCOMB_X30_Y17_N8 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_cpu:cpu|d_writedata[25]~33 ; LCCOMB_X27_Y16_N20 ; 32 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_cpu:cpu|dc_data_wr_port_en ; LCCOMB_X32_Y19_N20 ; 4 ; Clock enable, Write enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_cpu:cpu|dc_tag_wr_port_en ; LCCOMB_X35_Y21_N26 ; 1 ; Write enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_cpu:cpu|i_readdatavalid_d1 ; FF_X23_Y16_N5 ; 11 ; Clock enable, Write enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_cpu:cpu|ic_fill_ap_offset[1]~0 ; LCCOMB_X19_Y16_N16 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_cpu:cpu|ic_fill_dp_offset_en~0 ; LCCOMB_X20_Y23_N16 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_cpu:cpu|ic_fill_valid_bits_en ; LCCOMB_X20_Y23_N30 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_cpu:cpu|ic_tag_clr_valid_bits_nxt~2 ; LCCOMB_X23_Y20_N0 ; 9 ; Sync. load ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_cpu:cpu|ic_tag_wraddress[7]~6 ; LCCOMB_X25_Y19_N20 ; 8 ; Sync. clear ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_cpu:cpu|ic_tag_wren ; LCCOMB_X23_Y20_N4 ; 1 ; Write enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a0~0 ; LCCOMB_X21_Y24_N14 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy|virtual_state_sdr~0 ; LCCOMB_X15_Y15_N30 ; 39 ; Sync. load ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy|virtual_state_uir~0 ; LCCOMB_X15_Y16_N24 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|jxuir ; FF_X15_Y16_N23 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|take_action_ocimem_a ; LCCOMB_X17_Y16_N4 ; 15 ; Clock enable, Sync. load ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|take_action_ocimem_a~0 ; LCCOMB_X16_Y16_N10 ; 15 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|take_action_ocimem_b ; LCCOMB_X16_Y16_N6 ; 34 ; Sync. load ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|take_no_action_break_a~0 ; LCCOMB_X16_Y16_N4 ; 64 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|update_jdo_strobe ; FF_X15_Y16_N13 ; 39 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[27]~21 ; LCCOMB_X17_Y17_N24 ; 18 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[37]~28 ; LCCOMB_X15_Y15_N26 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[6]~13 ; LCCOMB_X15_Y15_N14 ; 13 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg|take_action_oci_intr_mask_reg~0 ; LCCOMB_X23_Y14_N6 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[0]~13 ; LCCOMB_X17_Y16_N10 ; 30 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[24]~22 ; LCCOMB_X17_Y16_N30 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonWr ; FF_X17_Y16_N27 ; 3 ; Write enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|comb~1 ; LCCOMB_X21_Y16_N8 ; 2 ; Write enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|r_ena~0 ; LCCOMB_X19_Y12_N30 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|td_shift[0]~4 ; LCCOMB_X18_Y12_N30 ; 21 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|write_stalled~1 ; LCCOMB_X18_Y12_N26 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|write~0 ; LCCOMB_X20_Y12_N30 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|fifo_rd~1 ; LCCOMB_X28_Y12_N30 ; 11 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|fifo_wr ; FF_X24_Y12_N27 ; 15 ; Clock enable, Write enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|ien_AE~0 ; LCCOMB_X24_Y12_N2 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|r_val~0 ; LCCOMB_X19_Y12_N2 ; 11 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|read_0 ; FF_X28_Y12_N29 ; 16 ; Sync. load ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|_~4 ; LCCOMB_X26_Y11_N22 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|_~0 ; LCCOMB_X19_Y13_N28 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|wr_rfifo ; LCCOMB_X21_Y12_N18 ; 13 ; Clock enable, Write enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_pio_led:pio_led|data_out[0]~4 ; LCCOMB_X29_Y15_N6 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_rs232_counters:RS232_In_Counters|baud_counter[6]~22 ; LCCOMB_X31_Y7_N6 ; 14 ; Sync. clear ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|_~0 ; LCCOMB_X30_Y10_N6 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_ca7:usedw_counter|_~2 ; LCCOMB_X30_Y10_N30 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_v9b:rd_ptr_msb|_~0 ; LCCOMB_X35_Y10_N24 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|rd_ptr_lsb~1 ; LCCOMB_X30_Y10_N24 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|comb~0 ; LCCOMB_X30_Y10_N14 ; 13 ; Clock enable, Write enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|data_in_shift_reg[3]~1 ; LCCOMB_X32_Y10_N28 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_rs232_counters:RS232_Out_Counters|baud_counter[4]~16 ; LCCOMB_X30_Y8_N6 ; 14 ; Sync. clear ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|_~0 ; LCCOMB_X32_Y10_N14 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_ca7:usedw_counter|_~2 ; LCCOMB_X29_Y9_N2 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_v9b:rd_ptr_msb|_~0 ; LCCOMB_X31_Y8_N20 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|comb~0 ; LCCOMB_X29_Y9_N26 ; 12 ; Clock enable, Write enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|data_out_shift_reg[1]~2 ; LCCOMB_X32_Y9_N14 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|data_out_shift_reg[1]~4 ; LCCOMB_X31_Y8_N14 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_rs232_wifi:rs232_wifi|read_interrupt_en~0 ; LCCOMB_X31_Y10_N22 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_rs232_wifi:rs232_wifi|readdata[0]~1 ; LCCOMB_X31_Y16_N12 ; 19 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_sdram:sdram|Selector27~6 ; LCCOMB_X11_Y9_N24 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_sdram:sdram|Selector34~2 ; LCCOMB_X10_Y8_N4 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_sdram:sdram|WideOr16~0 ; LCCOMB_X11_Y8_N12 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_sdram:sdram|active_rnw~3 ; LCCOMB_X11_Y8_N26 ; 42 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_sdram:sdram|m_addr[0]~1 ; LCCOMB_X10_Y9_N30 ; 13 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_sdram:sdram|m_state.000000010 ; FF_X10_Y8_N19 ; 33 ; Sync. clear ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_sdram:sdram|m_state.000010000 ; FF_X12_Y9_N1 ; 42 ; Sync. load ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_sdram:sdram|m_state.001000000 ; FF_X10_Y9_N23 ; 20 ; Sync. load ; no ; -- ; -- ; -- ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; FF_X12_Y16_N23 ; 70 ; Async. clear ; yes ; Global Clock ; GCLK3 ; -- ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_proc~0 ; LCCOMB_X9_Y16_N4 ; 4 ; Sync. load ; no ; -- ; -- ; -- ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_info_reg_ena ; LCCOMB_X9_Y16_N0 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_info_reg_ena~0 ; LCCOMB_X9_Y16_N6 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[0]~2 ; LCCOMB_X10_Y15_N22 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[0]~0 ; LCCOMB_X10_Y15_N28 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]~5 ; LCCOMB_X10_Y16_N4 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]~12 ; LCCOMB_X11_Y16_N12 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2]~3 ; LCCOMB_X11_Y15_N20 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[0]~16 ; LCCOMB_X11_Y18_N20 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[0]~19 ; LCCOMB_X9_Y16_N18 ; 5 ; Sync. load ; no ; -- ; -- ; -- ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena~3 ; LCCOMB_X12_Y16_N2 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][0]~2 ; LCCOMB_X10_Y16_N16 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][0]~9 ; LCCOMB_X10_Y16_N20 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[0]~15 ; LCCOMB_X11_Y18_N28 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[4]~22 ; LCCOMB_X10_Y18_N28 ; 5 ; Sync. clear ; no ; -- ; -- ; -- ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[4]~23 ; LCCOMB_X11_Y18_N10 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; FF_X12_Y16_N17 ; 12 ; Async. clear ; yes ; Global Clock ; GCLK4 ; -- ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[11] ; FF_X12_Y16_N19 ; 12 ; Clock enable ; no ; -- ; -- ; -- ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; FF_X12_Y16_N29 ; 39 ; Sync. load ; no ; -- ; -- ; -- ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; FF_X11_Y18_N9 ; 46 ; Sync. clear ; no ; -- ; -- ; -- ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; FF_X11_Y18_N25 ; 14 ; Async. clear ; no ; -- ; -- ; -- ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_dr_scan_proc~0 ; LCCOMB_X12_Y16_N10 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; FF_X12_Y18_N17 ; 31 ; Async. clear ; no ; -- ; -- ; -- ; +; system:inst_cpu|altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1]~1 ; LCCOMB_X25_Y11_N0 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|always0~0 ; LCCOMB_X11_Y13_N0 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|always1~0 ; LCCOMB_X12_Y13_N10 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|always2~0 ; LCCOMB_X12_Y13_N14 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|always3~0 ; LCCOMB_X12_Y13_N0 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|always4~0 ; LCCOMB_X11_Y13_N2 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|always5~0 ; LCCOMB_X12_Y12_N26 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|always6~0 ; LCCOMB_X11_Y11_N10 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[6]~11 ; LCCOMB_X12_Y12_N16 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent|comb~0 ; LCCOMB_X10_Y13_N30 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent|rp_valid ; LCCOMB_X12_Y12_N20 ; 20 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|altera_merlin_slave_translator:cpu_jtag_debug_module_translator|waitrequest_reset_override ; FF_X20_Y11_N29 ; 22 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|altera_merlin_traffic_limiter:limiter_001|pending_response_count[3]~9 ; LCCOMB_X21_Y15_N6 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|altera_merlin_traffic_limiter:limiter_001|save_dest_id~0 ; LCCOMB_X20_Y15_N30 ; 16 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|altera_merlin_traffic_limiter:limiter|pending_response_count[3]~8 ; LCCOMB_X24_Y12_N30 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|altera_merlin_traffic_limiter:limiter|save_dest_id~0 ; LCCOMB_X28_Y11_N24 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|altera_merlin_width_adapter:width_adapter|byteen_reg[1]~0 ; LCCOMB_X14_Y11_N20 ; 40 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|altera_merlin_width_adapter:width_adapter|use_reg ; FF_X14_Y9_N17 ; 76 ; Clock enable, Sync. clear, Sync. load ; no ; -- ; -- ; -- ; +; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; FF_X24_Y32_N5 ; 162 ; Clock enable, Sync. clear, Sync. load ; no ; -- ; -- ; -- ; +; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; FF_X24_Y32_N5 ; 2347 ; Async. clear, Async. load ; yes ; Global Clock ; GCLK13 ; -- ; +; system:inst_cpu|altera_reset_controller:rst_controller|merged_reset~0 ; LCCOMB_X27_Y1_N28 ; 3 ; Async. clear ; yes ; Global Clock ; GCLK16 ; -- ; +; system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux_001|altera_merlin_arbitrator:arb|top_priority_reg[0]~0 ; LCCOMB_X15_Y9_N8 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux_001|update_grant~0 ; LCCOMB_X14_Y9_N14 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux|altera_merlin_arbitrator:arb|top_priority_reg[0]~0 ; LCCOMB_X24_Y11_N20 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux|src_data[46] ; LCCOMB_X15_Y10_N22 ; 35 ; Sync. load ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux|update_grant~2 ; LCCOMB_X24_Y11_N24 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|A_dc_rd_addr_cnt[0]~1 ; LCCOMB_X23_Y17_N20 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|A_dc_rd_data_cnt[0]~0 ; LCCOMB_X27_Y15_N16 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|A_dc_rd_data_cnt[0]~1 ; LCCOMB_X27_Y15_N26 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|A_dc_wb_en ; LCCOMB_X21_Y18_N16 ; 4 ; Clock enable, Read enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|A_dc_wb_update_av_writedata ; LCCOMB_X20_Y15_N0 ; 32 ; Sync. load ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|A_dc_wb_wr_want_dmaster ; LCCOMB_X23_Y18_N22 ; 21 ; Sync. load ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|A_dc_wr_data_cnt[3]~0 ; LCCOMB_X23_Y18_N0 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|A_dc_xfer_rd_data_starting ; FF_X27_Y14_N11 ; 22 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|A_dc_xfer_wr_active ; FF_X26_Y14_N17 ; 1 ; Write enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|A_ienable_reg_irq0~0 ; LCCOMB_X26_Y13_N8 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|A_ld_align_byte1_fill ; FF_X28_Y19_N27 ; 9 ; Sync. load ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|A_ld_align_sh8 ; FF_X28_Y16_N9 ; 10 ; Sync. load ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|A_mul_stall_d3 ; FF_X35_Y16_N29 ; 32 ; Sync. load ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|A_slow_inst_result_en~0 ; LCCOMB_X28_Y15_N12 ; 32 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|A_stall~0 ; LCCOMB_X27_Y17_N8 ; 742 ; Clock enable, Sync. clear ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|A_wr_dst_reg_from_M ; FF_X30_Y14_N7 ; 4 ; Write enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|Add8~5 ; LCCOMB_X39_Y18_N20 ; 32 ; Sync. load ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|D_ctrl_src2_choose_imm ; FF_X32_Y14_N1 ; 33 ; Sync. load ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|D_ic_fill_starting~1 ; LCCOMB_X30_Y10_N22 ; 25 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|E_hbreak_req ; LCCOMB_X30_Y13_N18 ; 30 ; Sync. load ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|E_iw[0] ; FF_X32_Y17_N29 ; 18 ; Sync. clear ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|E_iw[4] ; FF_X32_Y17_N13 ; 34 ; Sync. load ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|F_stall ; LCCOMB_X31_Y13_N10 ; 175 ; Clock enable, Read enable, Sync. clear, Sync. load ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|M_bht_wr_en_unfiltered ; LCCOMB_X31_Y16_N14 ; 1 ; Write enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|M_br_cond_taken_history[0]~0 ; LCCOMB_X31_Y16_N8 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|M_ctrl_rdctl_inst ; FF_X30_Y13_N1 ; 32 ; Sync. clear, Sync. load ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|M_pipe_flush ; FF_X31_Y16_N1 ; 53 ; Sync. load ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|M_rot_rn[3] ; FF_X39_Y18_N25 ; 32 ; Sync. load ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|always142~0 ; LCCOMB_X27_Y17_N14 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|d_address_offset_field[0]~2 ; LCCOMB_X23_Y17_N0 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|d_writedata[25]~33 ; LCCOMB_X20_Y15_N8 ; 32 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|dc_data_wr_port_en ; LCCOMB_X26_Y15_N14 ; 4 ; Clock enable, Write enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|dc_tag_wr_port_en ; LCCOMB_X29_Y14_N26 ; 1 ; Write enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|i_readdatavalid_d1 ; FF_X25_Y14_N13 ; 11 ; Clock enable, Write enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|ic_fill_ap_offset[1]~0 ; LCCOMB_X27_Y11_N20 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|ic_fill_dp_offset_en~0 ; LCCOMB_X30_Y10_N6 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|ic_fill_valid_bits_en ; LCCOMB_X29_Y10_N22 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|ic_tag_clr_valid_bits_nxt~2 ; LCCOMB_X29_Y13_N12 ; 9 ; Sync. load ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|ic_tag_wraddress[7]~6 ; LCCOMB_X29_Y13_N4 ; 8 ; Sync. clear ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|ic_tag_wren ; LCCOMB_X30_Y10_N8 ; 1 ; Write enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a0~0 ; LCCOMB_X31_Y13_N20 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy|virtual_state_sdr~0 ; LCCOMB_X17_Y11_N30 ; 39 ; Sync. load ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy|virtual_state_uir~0 ; LCCOMB_X17_Y11_N10 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|jxuir ; FF_X17_Y11_N7 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|take_action_ocimem_a ; LCCOMB_X20_Y8_N16 ; 15 ; Clock enable, Sync. load ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|take_action_ocimem_a~0 ; LCCOMB_X23_Y11_N10 ; 15 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|take_action_ocimem_b ; LCCOMB_X23_Y11_N18 ; 34 ; Sync. load ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|take_no_action_break_a~0 ; LCCOMB_X23_Y11_N24 ; 64 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|update_jdo_strobe ; FF_X17_Y11_N25 ; 39 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[27]~21 ; LCCOMB_X19_Y10_N24 ; 18 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[37]~28 ; LCCOMB_X18_Y11_N6 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[6]~13 ; LCCOMB_X17_Y11_N20 ; 13 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg|take_action_oci_intr_mask_reg~0 ; LCCOMB_X19_Y11_N0 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[0]~13 ; LCCOMB_X20_Y8_N10 ; 30 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[24]~22 ; LCCOMB_X20_Y8_N14 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonWr ; FF_X23_Y11_N5 ; 3 ; Write enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|comb~1 ; LCCOMB_X19_Y11_N28 ; 2 ; Write enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|r_ena~0 ; LCCOMB_X23_Y20_N0 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|td_shift[0]~4 ; LCCOMB_X14_Y20_N0 ; 21 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|write_stalled~1 ; LCCOMB_X14_Y20_N20 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|write~0 ; LCCOMB_X17_Y20_N18 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|fifo_rd~1 ; LCCOMB_X18_Y14_N22 ; 11 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|fifo_wr ; FF_X18_Y18_N17 ; 15 ; Clock enable, Write enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|ien_AE~0 ; LCCOMB_X18_Y18_N14 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|r_val~0 ; LCCOMB_X19_Y20_N18 ; 11 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|read_0 ; FF_X18_Y14_N17 ; 16 ; Sync. load ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|_~4 ; LCCOMB_X19_Y19_N4 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|_~0 ; LCCOMB_X20_Y19_N28 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|wr_rfifo ; LCCOMB_X19_Y19_N18 ; 13 ; Clock enable, Write enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_pio_led:pio_led|data_out[0]~4 ; LCCOMB_X18_Y16_N4 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_rs232_counters:RS232_In_Counters|baud_counter[6]~22 ; LCCOMB_X19_Y23_N0 ; 14 ; Sync. clear ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|_~0 ; LCCOMB_X19_Y22_N24 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_ca7:usedw_counter|_~2 ; LCCOMB_X19_Y22_N22 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_v9b:rd_ptr_msb|_~0 ; LCCOMB_X26_Y21_N14 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|rd_ptr_lsb~1 ; LCCOMB_X26_Y22_N0 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|comb~0 ; LCCOMB_X19_Y22_N6 ; 13 ; Clock enable, Write enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|data_in_shift_reg[3]~1 ; LCCOMB_X20_Y23_N0 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_rs232_counters:RS232_Out_Counters|baud_counter[4]~16 ; LCCOMB_X24_Y22_N18 ; 14 ; Sync. clear ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|_~0 ; LCCOMB_X24_Y21_N10 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_ca7:usedw_counter|_~2 ; LCCOMB_X24_Y21_N14 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_v9b:rd_ptr_msb|_~0 ; LCCOMB_X23_Y23_N16 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|comb~0 ; LCCOMB_X25_Y21_N4 ; 12 ; Clock enable, Write enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|data_out_shift_reg[1]~2 ; LCCOMB_X23_Y23_N18 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|data_out_shift_reg[1]~4 ; LCCOMB_X24_Y22_N14 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_rs232_wifi:rs232_wifi|read_interrupt_en~0 ; LCCOMB_X21_Y19_N14 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_rs232_wifi:rs232_wifi|readdata[0]~1 ; LCCOMB_X21_Y17_N10 ; 19 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_sdram:sdram|Selector27~6 ; LCCOMB_X9_Y9_N28 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_sdram:sdram|Selector34~2 ; LCCOMB_X8_Y9_N28 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_sdram:sdram|WideOr16~0 ; LCCOMB_X9_Y10_N28 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_sdram:sdram|active_rnw~3 ; LCCOMB_X9_Y10_N26 ; 42 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_sdram:sdram|m_addr[0]~1 ; LCCOMB_X8_Y8_N2 ; 13 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_sdram:sdram|m_state.000000010 ; FF_X9_Y10_N31 ; 33 ; Sync. clear ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_sdram:sdram|m_state.000010000 ; FF_X9_Y9_N9 ; 42 ; Sync. load ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_sdram:sdram|m_state.001000000 ; FF_X9_Y8_N1 ; 20 ; Sync. load ; no ; -- ; -- ; -- ; ; system:inst_cpu|system_sdram:sdram|oe ; DDIOOECELL_X0_Y23_N19 ; 1 ; Output enable ; no ; -- ; -- ; -- ; ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_1 ; DDIOOECELL_X0_Y23_N26 ; 1 ; Output enable ; no ; -- ; -- ; -- ; ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_10 ; DDIOOECELL_X1_Y0_N5 ; 1 ; Output enable ; no ; -- ; -- ; -- ; @@ -1886,45 +1886,45 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_7 ; DDIOOECELL_X16_Y0_N19 ; 1 ; Output enable ; no ; -- ; -- ; -- ; ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_8 ; DDIOOECELL_X5_Y0_N19 ; 1 ; Output enable ; no ; -- ; -- ; -- ; ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_9 ; DDIOOECELL_X3_Y0_N5 ; 1 ; Output enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[41]~2 ; LCCOMB_X17_Y9_N16 ; 42 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_1[41]~2 ; LCCOMB_X17_Y9_N22 ; 42 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_sys_clk_timer:sys_clk_timer|always0~0 ; LCCOMB_X27_Y12_N14 ; 32 ; Sync. load ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_sys_clk_timer:sys_clk_timer|always0~1 ; LCCOMB_X27_Y12_N2 ; 32 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_sys_clk_timer:sys_clk_timer|control_wr_strobe ; LCCOMB_X27_Y12_N16 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_sys_clk_timer:sys_clk_timer|period_h_wr_strobe ; LCCOMB_X29_Y13_N18 ; 16 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_sys_clk_timer:sys_clk_timer|period_l_wr_strobe ; LCCOMB_X27_Y13_N24 ; 16 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_sys_clk_timer:sys_clk_timer|snap_strobe~0 ; LCCOMB_X28_Y11_N2 ; 32 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_uart_mc:uart_mc|system_uart_mc_regs:the_system_uart_mc_regs|control_wr_strobe~0 ; LCCOMB_X27_Y14_N26 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_uart_mc:uart_mc|system_uart_mc_rx:the_system_uart_mc_rx|got_new_char ; LCCOMB_X26_Y14_N26 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_uart_mc:uart_mc|system_uart_mc_rx:the_system_uart_mc_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[6]~0 ; LCCOMB_X34_Y15_N14 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_uart_mc:uart_mc|system_uart_mc_tx:the_system_uart_mc_tx|always4~0 ; LCCOMB_X25_Y9_N8 ; 14 ; Sync. load ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_uart_mc:uart_mc|system_uart_mc_tx:the_system_uart_mc_tx|tx_wr_strobe_onset~0 ; LCCOMB_X27_Y14_N14 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_uart_mc:uart_mc|system_uart_mc_tx:the_system_uart_mc_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_in[1]~1 ; LCCOMB_X26_Y9_N18 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_regs:the_system_uart_wifi_regs|control_wr_strobe ; LCCOMB_X30_Y14_N18 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_regs:the_system_uart_wifi_regs|divisor_wr_strobe ; LCCOMB_X30_Y14_N2 ; 16 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_rx:the_system_uart_wifi_rx|baud_clk_en~2 ; LCCOMB_X35_Y13_N20 ; 16 ; Sync. load ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_rx:the_system_uart_wifi_rx|got_new_char ; LCCOMB_X32_Y13_N24 ; 12 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_rx:the_system_uart_wifi_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[4]~0 ; LCCOMB_X35_Y13_N4 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_tx:the_system_uart_wifi_tx|always4~0 ; LCCOMB_X31_Y14_N6 ; 16 ; Sync. load ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_tx:the_system_uart_wifi_tx|tx_wr_strobe_onset~2 ; LCCOMB_X30_Y14_N16 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; -; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_tx:the_system_uart_wifi_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_in[0]~1 ; LCCOMB_X32_Y12_N2 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[41]~2 ; LCCOMB_X12_Y11_N10 ; 42 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_1[41]~2 ; LCCOMB_X12_Y11_N0 ; 42 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_sys_clk_timer:sys_clk_timer|always0~0 ; LCCOMB_X15_Y13_N26 ; 32 ; Sync. load ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_sys_clk_timer:sys_clk_timer|always0~1 ; LCCOMB_X15_Y13_N18 ; 32 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_sys_clk_timer:sys_clk_timer|control_wr_strobe ; LCCOMB_X16_Y16_N0 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_sys_clk_timer:sys_clk_timer|period_h_wr_strobe ; LCCOMB_X16_Y15_N28 ; 16 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_sys_clk_timer:sys_clk_timer|period_l_wr_strobe ; LCCOMB_X16_Y15_N14 ; 16 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_sys_clk_timer:sys_clk_timer|snap_strobe~0 ; LCCOMB_X16_Y15_N8 ; 32 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_uart_mc:uart_mc|system_uart_mc_regs:the_system_uart_mc_regs|control_wr_strobe~0 ; LCCOMB_X16_Y13_N18 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_uart_mc:uart_mc|system_uart_mc_rx:the_system_uart_mc_rx|got_new_char ; LCCOMB_X17_Y22_N30 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_uart_mc:uart_mc|system_uart_mc_rx:the_system_uart_mc_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[6]~0 ; LCCOMB_X18_Y21_N10 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_uart_mc:uart_mc|system_uart_mc_tx:the_system_uart_mc_tx|always4~0 ; LCCOMB_X14_Y18_N8 ; 14 ; Sync. load ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_uart_mc:uart_mc|system_uart_mc_tx:the_system_uart_mc_tx|tx_wr_strobe_onset~0 ; LCCOMB_X16_Y13_N6 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_uart_mc:uart_mc|system_uart_mc_tx:the_system_uart_mc_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_in[1]~1 ; LCCOMB_X14_Y18_N12 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_regs:the_system_uart_wifi_regs|control_wr_strobe ; LCCOMB_X17_Y18_N28 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_regs:the_system_uart_wifi_regs|divisor_wr_strobe ; LCCOMB_X17_Y18_N16 ; 16 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_rx:the_system_uart_wifi_rx|baud_clk_en~2 ; LCCOMB_X15_Y21_N6 ; 16 ; Sync. load ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_rx:the_system_uart_wifi_rx|got_new_char ; LCCOMB_X14_Y21_N26 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_rx:the_system_uart_wifi_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[4]~0 ; LCCOMB_X14_Y21_N30 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_tx:the_system_uart_wifi_tx|always4~0 ; LCCOMB_X15_Y20_N22 ; 16 ; Sync. load ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_tx:the_system_uart_wifi_tx|tx_wr_strobe_onset~2 ; LCCOMB_X17_Y18_N4 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; +; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_tx:the_system_uart_wifi_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_in[0]~1 ; LCCOMB_X15_Y19_N8 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------+---------+----------------------------------------------------+--------+----------------------+------------------+---------------------------+ -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Global & Other Fast Signals ; -+-------------------------------------------------------------------------------------------------------------------------------------------+--------------------+---------+--------------------------------------+----------------------+------------------+---------------------------+ -; Name ; Location ; Fan-Out ; Fan-Out Using Intentional Clock Skew ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; -+-------------------------------------------------------------------------------------------------------------------------------------------+--------------------+---------+--------------------------------------+----------------------+------------------+---------------------------+ -; altera_internal_jtag~TCKUTAP ; JTAG_X1_Y17_N0 ; 183 ; 0 ; Global Clock ; GCLK0 ; -- ; -; pll_sys:inst_pll_sys|altpll:altpll_component|pll_sys_altpll:auto_generated|wire_pll1_clk[0] ; PLL_4 ; 2811 ; 11 ; Global Clock ; GCLK18 ; -- ; -; pll_sys:inst_pll_sys|altpll:altpll_component|pll_sys_altpll:auto_generated|wire_pll1_clk[1] ; PLL_4 ; 1 ; 0 ; Global Clock ; GCLK17 ; -- ; -; pll_sys:inst_pll_sys|altpll:altpll_component|pll_sys_altpll:auto_generated|wire_pll1_clk[2] ; PLL_4 ; 22 ; 0 ; Global Clock ; GCLK19 ; -- ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; FF_X10_Y13_N1 ; 70 ; 0 ; Global Clock ; GCLK3 ; -- ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; FF_X12_Y15_N11 ; 12 ; 0 ; Global Clock ; GCLK4 ; -- ; -; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; FF_X28_Y1_N5 ; 2347 ; 0 ; Global Clock ; GCLK16 ; -- ; -; system:inst_cpu|altera_reset_controller:rst_controller|merged_reset~0 ; LCCOMB_X52_Y17_N16 ; 3 ; 0 ; Global Clock ; GCLK7 ; -- ; -+-------------------------------------------------------------------------------------------------------------------------------------------+--------------------+---------+--------------------------------------+----------------------+------------------+---------------------------+ ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Global & Other Fast Signals ; ++-------------------------------------------------------------------------------------------------------------------------------------------+-------------------+---------+--------------------------------------+----------------------+------------------+---------------------------+ +; Name ; Location ; Fan-Out ; Fan-Out Using Intentional Clock Skew ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; ++-------------------------------------------------------------------------------------------------------------------------------------------+-------------------+---------+--------------------------------------+----------------------+------------------+---------------------------+ +; altera_internal_jtag~TCKUTAP ; JTAG_X1_Y17_N0 ; 183 ; 0 ; Global Clock ; GCLK1 ; -- ; +; pll_sys:inst_pll_sys|altpll:altpll_component|pll_sys_altpll:auto_generated|wire_pll1_clk[0] ; PLL_4 ; 2811 ; 13 ; Global Clock ; GCLK18 ; -- ; +; pll_sys:inst_pll_sys|altpll:altpll_component|pll_sys_altpll:auto_generated|wire_pll1_clk[1] ; PLL_4 ; 1 ; 0 ; Global Clock ; GCLK17 ; -- ; +; pll_sys:inst_pll_sys|altpll:altpll_component|pll_sys_altpll:auto_generated|wire_pll1_clk[2] ; PLL_4 ; 22 ; 0 ; Global Clock ; GCLK19 ; -- ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; FF_X12_Y16_N23 ; 70 ; 0 ; Global Clock ; GCLK3 ; -- ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; FF_X12_Y16_N17 ; 12 ; 0 ; Global Clock ; GCLK4 ; -- ; +; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; FF_X24_Y32_N5 ; 2347 ; 0 ; Global Clock ; GCLK13 ; -- ; +; system:inst_cpu|altera_reset_controller:rst_controller|merged_reset~0 ; LCCOMB_X27_Y1_N28 ; 3 ; 0 ; Global Clock ; GCLK16 ; -- ; ++-------------------------------------------------------------------------------------------------------------------------------------------+-------------------+---------+--------------------------------------+----------------------+------------------+---------------------------+ +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ @@ -1935,17 +1935,17 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; system:inst_cpu|system_cpu:cpu|A_stall~0 ; 742 ; ; system:inst_cpu|system_cpu:cpu|F_stall ; 176 ; ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; 161 ; -; system:inst_cpu|system_cpu:cpu|d_address_offset_field[0] ; 91 ; -; system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux_001|saved_grant[1] ; 81 ; +; system:inst_cpu|system_cpu:cpu|d_address_offset_field[0] ; 89 ; +; system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux_001|saved_grant[1] ; 82 ; ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|use_reg ; 76 ; ; system:inst_cpu|system_cpu:cpu|A_mul_stall ; 73 ; -; system:inst_cpu|system_cpu:cpu|d_address_offset_field[1] ; 69 ; -; system:inst_cpu|system_cpu:cpu|d_address_offset_field[2] ; 66 ; +; system:inst_cpu|system_cpu:cpu|d_address_offset_field[1] ; 67 ; ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|take_no_action_break_a~0 ; 64 ; +; system:inst_cpu|system_cpu:cpu|d_address_offset_field[2] ; 64 ; ; system:inst_cpu|system_cpu:cpu|A_dc_fill_active ; 55 ; ; system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux|saved_grant[1] ; 55 ; +; system:inst_cpu|system_cpu:cpu|M_pipe_flush ; 53 ; ; system:inst_cpu|system_cpu:cpu|d_write ; 53 ; -; system:inst_cpu|system_cpu:cpu|M_pipe_flush ; 52 ; ; ~GND ; 49 ; ; system:inst_cpu|system_cpu:cpu|E_src1[6]~1 ; 48 ; ; system:inst_cpu|system_cpu:cpu|E_src1[6]~0 ; 48 ; @@ -1976,7 +1976,6 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; system:inst_cpu|system_sys_clk_timer:sys_clk_timer|Equal6~2 ; 36 ; ; system:inst_cpu|system_cpu:cpu|D_src2_hazard_E ; 36 ; ; system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux|src_data[46] ; 35 ; -; system:inst_cpu|system_cpu:cpu|d_read ; 35 ; ; system:inst_cpu|system_sys_clk_timer:sys_clk_timer|Equal6~5 ; 34 ; ; system:inst_cpu|system_cpu:cpu|F_pc[14]~1 ; 34 ; ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|take_action_ocimem_b ; 34 ; @@ -1985,6 +1984,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; system:inst_cpu|system_cpu:cpu|E_regnum_a_cmp_D ; 34 ; ; system:inst_cpu|system_cpu:cpu|D_ctrl_src2_choose_imm ; 33 ; ; system:inst_cpu|system_rsp_xbar_demux:rsp_xbar_demux|src0_valid ; 33 ; +; system:inst_cpu|system_cpu:cpu|d_read ; 33 ; ; system:inst_cpu|system_sdram:sdram|m_state.000000010 ; 33 ; ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonAReg[10] ; 33 ; ; system:inst_cpu|system_sys_clk_timer:sys_clk_timer|snap_strobe~0 ; 32 ; @@ -2010,11 +2010,11 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; system:inst_cpu|system_cpu:cpu|A_dc_wb_update_av_writedata ; 32 ; ; system:inst_cpu|system_cpu:cpu|Add8~5 ; 32 ; ; system:inst_cpu|system_cpu:cpu|Add8~3 ; 32 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; 30 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; 31 ; ; system:inst_cpu|system_cpu:cpu|D_ctrl_b_is_dst ; 30 ; ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[0]~13 ; 30 ; ; system:inst_cpu|system_cpu:cpu|E_hbreak_req ; 30 ; -; system:inst_cpu|altera_merlin_slave_translator:jtag_uart_0_avalon_jtag_slave_translator|read_latency_shift_reg[0] ; 28 ; +; system:inst_cpu|altera_merlin_slave_translator:jtag_uart_0_avalon_jtag_slave_translator|read_latency_shift_reg[0] ; 27 ; ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0] ; 26 ; ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg|oci_reg_readdata~0 ; 26 ; ; system:inst_cpu|system_cpu:cpu|D_bht_data[1] ; 26 ; @@ -2025,19 +2025,20 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; system:inst_cpu|system_cpu:cpu|E_ctrl_br_cond_nxt~1 ; 25 ; ; system:inst_cpu|system_cpu:cpu|E_valid_jmp_indirect ; 25 ; ; system:inst_cpu|system_cpu:cpu|E_ctrl_retaddr ; 25 ; -; system:inst_cpu|altera_merlin_slave_translator:rs232_wifi_avalon_rs232_slave_translator|read_latency_shift_reg[0] ; 25 ; ; system:inst_cpu|system_cpu:cpu|D_ic_fill_starting~1 ; 25 ; ; system:inst_cpu|system_cpu:cpu|E_ctrl_jmp_indirect ; 24 ; ; system:inst_cpu|system_cpu:cpu|A_wr_data_unfiltered[27]~23 ; 24 ; ; system:inst_cpu|system_cpu:cpu|A_data_ram_ld_align_fill_bit ; 24 ; +; system:inst_cpu|altera_merlin_slave_translator:rs232_wifi_avalon_rs232_slave_translator|read_latency_shift_reg[0] ; 24 ; ; system:inst_cpu|system_sdram:sdram|refresh_request ; 24 ; ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1] ; 23 ; ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|comb~2 ; 23 ; +; system:inst_cpu|system_sys_clk_timer:sys_clk_timer|Equal6~3 ; 23 ; ; system:inst_cpu|system_cpu:cpu|D_iw[12] ; 23 ; ; system:inst_cpu|system_sys_clk_timer:sys_clk_timer|Equal6~1 ; 23 ; ; system:inst_cpu|system_cpu:cpu|E_regnum_b_cmp_D ; 23 ; -; system:inst_cpu|system_sys_clk_timer:sys_clk_timer|Equal6~3 ; 22 ; ; system:inst_cpu|system_cpu:cpu|A_dc_xfer_rd_data_starting ; 22 ; +; system:inst_cpu|system_rsp_xbar_demux:rsp_xbar_demux|src1_valid ; 22 ; ; system:inst_cpu|altera_merlin_slave_translator:uart_wifi_s1_translator|read_latency_shift_reg[0] ; 22 ; ; system:inst_cpu|altera_merlin_slave_translator:cpu_jtag_debug_module_translator|waitrequest_reset_override ; 22 ; ; system:inst_cpu|system_sdram:sdram|m_state.000000001 ; 22 ; @@ -2045,8 +2046,8 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; altera_internal_jtag~TMSUTAP ; 21 ; ; system:inst_cpu|system_cpu:cpu|D_iw[16] ; 21 ; ; system:inst_cpu|system_cpu:cpu|D_iw[14] ; 21 ; -; system:inst_cpu|system_rsp_xbar_demux:rsp_xbar_demux|src1_valid ; 21 ; ; system:inst_cpu|altera_merlin_slave_translator:sys_clk_timer_s1_translator|read_latency_shift_reg[0] ; 21 ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][84] ; 21 ; ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|td_shift[0]~4 ; 21 ; ; system:inst_cpu|system_cpu:cpu|A_dc_wb_wr_want_dmaster ; 21 ; ; system:inst_cpu|system_cpu:cpu|d_address_tag_field_nxt~0 ; 21 ; @@ -2054,12 +2055,11 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; system:inst_cpu|system_cpu:cpu|E_ctrl_shift_rot_right ; 20 ; ; system:inst_cpu|system_cpu:cpu|D_iw[13] ; 20 ; ; system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent|rp_valid ; 20 ; -; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][84] ; 20 ; ; system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux|saved_grant[0] ; 20 ; ; system:inst_cpu|system_sdram:sdram|m_state.001000000 ; 20 ; ; system:inst_cpu|system_rs232_wifi:rs232_wifi|readdata[0]~1 ; 19 ; ; system:inst_cpu|system_cpu:cpu|i_readdatavalid_d1 ; 19 ; -; system:inst_cpu|altera_merlin_slave_translator:cpu_jtag_debug_module_translator|read_latency_shift_reg[0] ; 19 ; +; system:inst_cpu|system_rsp_xbar_demux:rsp_xbar_demux_001|src1_valid~0 ; 19 ; ; altera_internal_jtag~TDIUTAP ; 18 ; ; system:inst_cpu|system_uart_mc:uart_mc|system_uart_mc_rx:the_system_uart_mc_rx|altera_std_synchronizer:the_altera_std_synchronizer|dreg[0] ; 18 ; ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[27]~21 ; 18 ; @@ -2068,9 +2068,10 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; system:inst_cpu|system_cpu:cpu|A_dc_fill_starting_d1 ; 18 ; ; system:inst_cpu|system_cpu:cpu|D_iw[11] ; 18 ; ; system:inst_cpu|system_cpu:cpu|E_iw[0] ; 18 ; -; system:inst_cpu|system_rsp_xbar_demux:rsp_xbar_demux_001|src1_valid~0 ; 18 ; ; system:inst_cpu|system_rsp_xbar_demux:rsp_xbar_demux_001|src0_valid~0 ; 18 ; +; system:inst_cpu|altera_merlin_slave_translator:cpu_jtag_debug_module_translator|read_latency_shift_reg[0] ; 18 ; ; system:inst_cpu|system_cpu:cpu|M_valid_from_E ; 18 ; +; system:inst_cpu|altera_merlin_traffic_limiter:limiter_001|has_pending_responses ; 18 ; ; system:inst_cpu|system_sdram:sdram|WideOr9~0 ; 18 ; ; system:inst_cpu|system_sdram:sdram|always5~0 ; 18 ; ; system:inst_cpu|system_sdram:sdram|init_done ; 18 ; @@ -2078,8 +2079,6 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; system:inst_cpu|system_cpu:cpu|A_slow_ld_data_sign_bit~2 ; 17 ; ; system:inst_cpu|system_cpu:cpu|A_ld_align_byte2_byte3_fill ; 17 ; ; system:inst_cpu|system_cpu:cpu|D_iw[15] ; 17 ; -; system:inst_cpu|altera_merlin_traffic_limiter:limiter_001|has_pending_responses ; 17 ; -; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[7] ; 17 ; ; system:inst_cpu|system_cpu:cpu|d_address_line_field[1] ; 17 ; ; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_rx:the_system_uart_wifi_rx|baud_clk_en~2 ; 16 ; ; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_regs:the_system_uart_wifi_regs|divisor_wr_strobe ; 16 ; @@ -2095,17 +2094,21 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr~19 ; 16 ; ; system:inst_cpu|system_cpu:cpu|A_wr_data_unfiltered[14]~22 ; 16 ; ; system:inst_cpu|system_sdram:sdram|m_data[10]~0 ; 16 ; -; system:inst_cpu|altera_merlin_slave_translator:uart_mc_s1_translator|read_latency_shift_reg[0] ; 16 ; ; system:inst_cpu|altera_merlin_traffic_limiter:limiter_001|save_dest_id~0 ; 16 ; -; system:inst_cpu|altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][83] ; 16 ; ; system:inst_cpu|system_uart_mc:uart_mc|system_uart_mc_rx:the_system_uart_mc_rx|Equal0~4 ; 15 ; ; system:inst_cpu|system_cpu:cpu|D_src2[30]~20 ; 15 ; ; system:inst_cpu|system_cpu:cpu|D_iw[2] ; 15 ; ; system:inst_cpu|system_cpu:cpu|E_iw[2] ; 15 ; +; system:inst_cpu|altera_merlin_slave_translator:uart_mc_s1_translator|read_latency_shift_reg[0] ; 15 ; +; system:inst_cpu|altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][83] ; 15 ; ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|take_action_ocimem_a ; 15 ; ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|take_action_ocimem_a~0 ; 15 ; +; system:inst_cpu|system_cmd_xbar_demux_001:cmd_xbar_demux_001|WideOr0~10 ; 15 ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[7] ; 15 ; +; system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent|WideOr0~2 ; 15 ; ; system:inst_cpu|system_cpu:cpu|d_writedata[1] ; 15 ; ; system:inst_cpu|system_cpu:cpu|d_address_line_field[2] ; 15 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; 14 ; ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1] ; 14 ; ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0] ; 14 ; ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_rs232_counters:RS232_In_Counters|baud_counter[6]~22 ; 14 ; @@ -2114,16 +2117,15 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_rs232_counters:RS232_Out_Counters|baud_counter[4]~16 ; 14 ; ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|wr_rfifo ; 14 ; ; system:inst_cpu|system_cpu:cpu|D_iw[4] ; 14 ; -; system:inst_cpu|system_cmd_xbar_demux_001:cmd_xbar_demux_001|WideOr0~10 ; 14 ; ; system:inst_cpu|system_cpu:cpu|A_dc_wb_active ; 14 ; ; system:inst_cpu|system_addr_router_001:addr_router_001|Equal1~3 ; 14 ; -; system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent|WideOr0~2 ; 14 ; ; system:inst_cpu|system_sdram:sdram|m_state.100000000 ; 14 ; ; system:inst_cpu|system_cpu:cpu|d_writedata[3] ; 14 ; ; system:inst_cpu|system_cpu:cpu|d_writedata[2] ; 14 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; 13 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6] ; 13 ; ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2] ; 13 ; ; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_tx:the_system_uart_wifi_tx|do_load_shifter ; 13 ; +; system:inst_cpu|system_sys_clk_timer:sys_clk_timer|Equal6~4 ; 13 ; ; system:inst_cpu|system_uart_mc:uart_mc|system_uart_mc_tx:the_system_uart_mc_tx|do_load_shifter ; 13 ; ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|comb~0 ; 13 ; ; system:inst_cpu|system_cpu:cpu|A_dc_xfer_rd_addr_active ; 13 ; @@ -2132,30 +2134,29 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; system:inst_cpu|system_cpu:cpu|D_iw[1] ; 13 ; ; system:inst_cpu|system_cpu:cpu|D_ic_fill_starting_d1 ; 13 ; ; system:inst_cpu|system_cpu:cpu|E_iw[1] ; 13 ; -; system:inst_cpu|altera_merlin_slave_translator:sysid_control_slave_translator|read_latency_shift_reg[0] ; 13 ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0] ; 13 ; ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[6]~13 ; 13 ; ; system:inst_cpu|system_cpu:cpu|M_alu_result[6] ; 13 ; ; system:inst_cpu|system_cpu:cpu|M_alu_result[5] ; 13 ; -; system:inst_cpu|system_cpu:cpu|A_dc_wb_update_av_writedata~0 ; 13 ; ; system:inst_cpu|system_cpu:cpu|i_read ; 13 ; ; system:inst_cpu|system_sdram:sdram|Equal0~4 ; 13 ; ; system:inst_cpu|system_sdram:sdram|m_addr[0]~1 ; 13 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6] ; 12 ; ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[11] ; 12 ; -; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_rx:the_system_uart_wifi_rx|got_new_char ; 12 ; -; system:inst_cpu|system_sys_clk_timer:sys_clk_timer|Equal6~4 ; 12 ; ; system:inst_cpu|system_cpu:cpu|A_wr_data_unfiltered[4]~1 ; 12 ; ; system:inst_cpu|system_cpu:cpu|A_wr_data_unfiltered[4]~0 ; 12 ; ; system:inst_cpu|system_cpu:cpu|D_iw[5] ; 12 ; ; system:inst_cpu|system_cpu:cpu|E_iw[3] ; 12 ; ; system:inst_cpu|system_cpu:cpu|E_iw[5] ; 12 ; -; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0] ; 12 ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][83] ; 12 ; +; system:inst_cpu|system_sdram:sdram|za_valid ; 12 ; ; system:inst_cpu|system_cpu:cpu|M_alu_result[8] ; 12 ; ; system:inst_cpu|system_cpu:cpu|M_alu_result[7] ; 12 ; ; system:inst_cpu|system_cpu:cpu|M_alu_result[9] ; 12 ; ; system:inst_cpu|system_cpu:cpu|M_alu_result[10] ; 12 ; ; system:inst_cpu|system_cpu:cpu|M_alu_result[11] ; 12 ; ; system:inst_cpu|altera_merlin_slave_translator:pio_led_s1_translator|read_latency_shift_reg[0] ; 12 ; +; system:inst_cpu|system_cpu:cpu|A_dc_wb_update_av_writedata~0 ; 12 ; +; system:inst_cpu|altera_merlin_traffic_limiter:limiter_001|suppress~3 ; 12 ; ; system:inst_cpu|system_cpu:cpu|A_dc_fill_starting~0 ; 12 ; ; system:inst_cpu|system_cpu:cpu|ic_fill_line[3] ; 12 ; ; system:inst_cpu|system_cpu:cpu|ic_fill_line[2] ; 12 ; @@ -2167,7 +2168,6 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; system:inst_cpu|system_cpu:cpu|ic_fill_line[6] ; 12 ; ; system:inst_cpu|system_sdram:sdram|i_state.011 ; 12 ; ; system:inst_cpu|system_sdram:sdram|i_state.000 ; 12 ; -; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entries[0] ; 12 ; ; system:inst_cpu|system_cpu:cpu|E_src2[0] ; 12 ; ; system:inst_cpu|system_cpu:cpu|E_src2[1] ; 12 ; ; system:inst_cpu|system_cpu:cpu|E_src2[2] ; 12 ; @@ -2185,23 +2185,23 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; system:inst_cpu|system_cpu:cpu|Equal171~1 ; 11 ; ; system:inst_cpu|system_cpu:cpu|D_iw[3] ; 11 ; ; system:inst_cpu|system_cpu:cpu|ic_fill_dp_offset[0] ; 11 ; -; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][83] ; 11 ; -; system:inst_cpu|system_sdram:sdram|za_valid ; 11 ; ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|count[9] ; 11 ; -; system:inst_cpu|altera_merlin_traffic_limiter:limiter_001|suppress~3 ; 11 ; ; system:inst_cpu|altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; 11 ; ; system:inst_cpu|system_sdram:sdram|i_state.101 ; 11 ; ; system:inst_cpu|system_sdram:sdram|i_addr[12] ; 11 ; ; system:inst_cpu|system_sdram:sdram|m_addr[0]~0 ; 11 ; ; system:inst_cpu|system_sdram:sdram|pending ; 11 ; -; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entries[1] ; 11 ; +; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entries[0] ; 11 ; ; system:inst_cpu|system_sdram:sdram|m_state.010000000 ; 11 ; ; system:inst_cpu|system_cpu:cpu|d_writedata[7] ; 11 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; 10 ; ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0] ; 10 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[2] ; 10 ; ; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_regs:the_system_uart_wifi_regs|control_wr_strobe ; 10 ; ; system:inst_cpu|system_uart_mc:uart_mc|system_uart_mc_rx:the_system_uart_mc_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[6]~0 ; 10 ; ; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_rx:the_system_uart_wifi_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[4]~0 ; 10 ; ; system:inst_cpu|system_uart_mc:uart_mc|system_uart_mc_rx:the_system_uart_mc_rx|got_new_char ; 10 ; +; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_rx:the_system_uart_wifi_rx|got_new_char ; 10 ; ; system:inst_cpu|system_uart_mc:uart_mc|system_uart_mc_tx:the_system_uart_mc_tx|tx_wr_strobe_onset~0 ; 10 ; ; system:inst_cpu|system_cpu:cpu|F_ic_tag_rd_addr_nxt[7]~31 ; 10 ; ; system:inst_cpu|system_cpu:cpu|F_ic_tag_rd_addr_nxt[6]~27 ; 10 ; @@ -2217,21 +2217,20 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; system:inst_cpu|system_cpu:cpu|ic_fill_dp_offset_nxt[2]~2 ; 10 ; ; system:inst_cpu|system_cpu:cpu|ic_fill_dp_offset_nxt[1]~0 ; 10 ; ; system:inst_cpu|system_cpu:cpu|ic_fill_dp_offset[1] ; 10 ; -; system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent|local_read~1 ; 10 ; ; system:inst_cpu|system_cpu:cpu|hbreak_enabled ; 10 ; +; system:inst_cpu|altera_merlin_slave_translator:sysid_control_slave_translator|read_latency_shift_reg[0] ; 10 ; ; system:inst_cpu|system_cpu:cpu|M_alu_result[4] ; 10 ; ; system:inst_cpu|system_sdram:sdram|i_state.010 ; 10 ; +; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entries[1] ; 10 ; ; system:inst_cpu|system_sdram:sdram|m_state.000000100 ; 10 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; 9 ; ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[0] ; 9 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[4] ; 9 ; ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[3] ; 9 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[2] ; 9 ; ; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_rx:the_system_uart_wifi_rx|altera_std_synchronizer:the_altera_std_synchronizer|din_s1~0 ; 9 ; ; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_tx:the_system_uart_wifi_tx|tx_wr_strobe_onset~2 ; 9 ; ; system:inst_cpu|system_cpu:cpu|ic_tag_clr_valid_bits_nxt ; 9 ; ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|data_in_shift_reg[3]~1 ; 9 ; ; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_tx:the_system_uart_wifi_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_in[0]~1 ; 9 ; -; system:inst_cpu|system_rsp_xbar_mux_001:rsp_xbar_mux_001|src_payload~11 ; 9 ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[3] ; 9 ; ; system:inst_cpu|system_uart_mc:uart_mc|system_uart_mc_tx:the_system_uart_mc_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_in[1]~1 ; 9 ; ; system:inst_cpu|system_cpu:cpu|F_ic_data_rd_addr_nxt[2]~11 ; 9 ; @@ -2249,6 +2248,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[5] ; 9 ; ; system:inst_cpu|system_cpu:cpu|d_readdatavalid_d1 ; 9 ; ; system:inst_cpu|altera_merlin_slave_translator:pio_sw_s1_translator|read_latency_shift_reg[0] ; 9 ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|write~1 ; 9 ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[6] ; 9 ; ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|state ; 9 ; ; system:inst_cpu|system_cpu:cpu|M_alu_result[3] ; 9 ; @@ -2263,10 +2263,10 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|address_reg[1] ; 9 ; ; system:inst_cpu|system_cpu:cpu|d_address_line_field[3] ; 9 ; ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4] ; 8 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[4] ; 8 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[1] ; 8 ; ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|write~0 ; 8 ; ; system:inst_cpu|system_cpu:cpu|M_br_cond_taken_history[0]~0 ; 8 ; -; system:inst_cpu|altera_merlin_slave_translator:sysid_control_slave_translator|av_readdata_pre[30] ; 8 ; +; system:inst_cpu|system_rsp_xbar_mux_001:rsp_xbar_mux_001|src_payload~11 ; 8 ; ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a0~0 ; 8 ; ; system:inst_cpu|system_cpu:cpu|ic_fill_valid_bits_en ; 8 ; ; system:inst_cpu|system_cpu:cpu|ic_tag_wraddress[7]~6 ; 8 ; @@ -2292,6 +2292,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; system:inst_cpu|altera_avalon_sc_fifo:rs232_wifi_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; 8 ; ; system:inst_cpu|altera_avalon_sc_fifo:uart_wifi_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; 8 ; ; system:inst_cpu|system_cpu:cpu|A_dc_wb_wr_starting ; 8 ; +; system:inst_cpu|system_cmd_xbar_demux_001:cmd_xbar_demux_001|src1_valid~1 ; 8 ; ; system:inst_cpu|system_addr_router_001:addr_router_001|Equal10~1 ; 8 ; ; system:inst_cpu|system_addr_router_001:addr_router_001|Equal9~1 ; 8 ; ; system:inst_cpu|system_addr_router:addr_router|Equal1~4 ; 8 ; @@ -2304,11 +2305,11 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; 7 ; ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[0] ; 7 ; ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[2] ; 7 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[1] ; 7 ; ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_ca7:usedw_counter|_~2 ; 7 ; ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_ca7:usedw_counter|_~2 ; 7 ; ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|_~0 ; 7 ; ; system:inst_cpu|system_uart_mc:uart_mc|system_uart_mc_rx:the_system_uart_mc_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[0] ; 7 ; +; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_rx:the_system_uart_wifi_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[0] ; 7 ; ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|_~0 ; 7 ; ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_avalon_reg:the_system_cpu_nios2_avalon_reg|take_action_oci_intr_mask_reg~0 ; 7 ; ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|b_full ; 7 ; @@ -2321,6 +2322,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; system:inst_cpu|system_cpu:cpu|M_alu_result[1] ; 7 ; ; system:inst_cpu|system_cpu:cpu|dc_tag_wr_port_addr~0 ; 7 ; ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|out_endofpacket~0 ; 7 ; +; system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent|local_read~1 ; 7 ; ; system:inst_cpu|system_cpu:cpu|E_src1[13] ; 7 ; ; system:inst_cpu|system_cpu:cpu|E_src1[14] ; 7 ; ; system:inst_cpu|system_cpu:cpu|E_src1[15] ; 7 ; @@ -2346,9 +2348,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; system:inst_cpu|system_cpu:cpu|E_src1[3] ; 7 ; ; system:inst_cpu|system_cpu:cpu|E_src1[4] ; 7 ; ; system:inst_cpu|system_cpu:cpu|ic_fill_ap_offset[1]~0 ; 7 ; -; system:inst_cpu|altera_merlin_slave_translator:pio_ir_emitter_s1_translator|read_latency_shift_reg[0] ; 7 ; ; system:inst_cpu|system_cmd_xbar_demux:cmd_xbar_demux|WideOr0~1 ; 7 ; -; system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent|comb~0 ; 7 ; ; system:inst_cpu|system_sdram:sdram|i_count[2] ; 7 ; ; system:inst_cpu|system_cpu:cpu|M_alu_result[13] ; 7 ; ; system:inst_cpu|system_cpu:cpu|M_alu_result[15] ; 7 ; @@ -2365,8 +2365,8 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; system:inst_cpu|system_cpu:cpu|A_dc_wr_data_cnt[3] ; 7 ; ; system:inst_cpu|system_cpu:cpu|A_dc_wb_wr_active ; 7 ; ; system:inst_cpu|system_cpu:cpu|A_valid ; 7 ; +; system:inst_cpu|altera_merlin_slave_translator:sys_clk_timer_s1_translator|av_begintransfer~0 ; 7 ; ; system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent|m0_write ; 7 ; -; system:inst_cpu|system_cmd_xbar_demux_001:cmd_xbar_demux_001|src1_valid~1 ; 7 ; ; system:inst_cpu|system_addr_router_001:addr_router_001|Equal2~6 ; 7 ; ; system:inst_cpu|system_addr_router_001:addr_router_001|Equal4~1 ; 7 ; ; system:inst_cpu|system_addr_router_001:addr_router_001|Equal6~1 ; 7 ; @@ -2378,13 +2378,13 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; system:inst_cpu|system_sdram:sdram|f_pop ; 7 ; ; system:inst_cpu|system_cpu:cpu|d_writedata[9] ; 7 ; ; system:inst_cpu|system_cpu:cpu|d_writedata[8] ; 7 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|clear_signal ; 6 ; ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena_proc~1 ; 6 ; ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_info_reg_ena~0 ; 6 ; ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[3] ; 6 ; ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[3] ; 6 ; ; system:inst_cpu|system_cpu:cpu|D_ic_fill_starting~1_wirecell ; 6 ; ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|_~4 ; 6 ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[6]~11 ; 6 ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|always6~0 ; 6 ; ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_v9b:rd_ptr_msb|_~0 ; 6 ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|always5~0 ; 6 ; @@ -2394,7 +2394,6 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|_~0 ; 6 ; ; system:inst_cpu|system_cpu:cpu|E_ctrl_shift_rot_left ; 6 ; ; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_tx:the_system_uart_wifi_tx|tx_ready ; 6 ; -; system:inst_cpu|system_sys_clk_timer:sys_clk_timer|period_l_wr_strobe~3 ; 6 ; ; system:inst_cpu|system_cpu:cpu|A_ienable_reg_irq0~0 ; 6 ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|always3~0 ; 6 ; ; system:inst_cpu|system_uart_mc:uart_mc|system_uart_mc_tx:the_system_uart_mc_tx|tx_ready ; 6 ; @@ -2408,15 +2407,14 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; system:inst_cpu|system_cpu:cpu|D_iw[6] ; 6 ; ; system:inst_cpu|system_cpu:cpu|D_issue ; 6 ; ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|always0~0 ; 6 ; -; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[6]~2 ; 6 ; ; system:inst_cpu|system_cpu:cpu|E_src1[31] ; 6 ; ; system:inst_cpu|system_cpu:cpu|latched_oci_tb_hbreak_req ; 6 ; ; system:inst_cpu|system_cpu:cpu|E_valid~0 ; 6 ; -; system:inst_cpu|altera_merlin_traffic_limiter:limiter_001|response_accepted ; 6 ; +; system:inst_cpu|altera_merlin_slave_translator:pio_ir_emitter_s1_translator|read_latency_shift_reg[0] ; 6 ; ; system:inst_cpu|altera_merlin_slave_translator:pio_key_left_s1_translator|read_latency_shift_reg[0] ; 6 ; ; system:inst_cpu|altera_merlin_traffic_limiter:limiter|has_pending_responses~0 ; 6 ; ; system:inst_cpu|altera_merlin_traffic_limiter:limiter|response_accepted~0 ; 6 ; -; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|write~0 ; 6 ; +; system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent|comb~0 ; 6 ; ; system:inst_cpu|system_cpu:cpu|A_mem_baddr[6] ; 6 ; ; system:inst_cpu|system_cpu:cpu|A_mem_baddr[8] ; 6 ; ; system:inst_cpu|system_cpu:cpu|A_mem_baddr[7] ; 6 ; @@ -2424,7 +2422,8 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; system:inst_cpu|system_cpu:cpu|A_mem_baddr[10] ; 6 ; ; system:inst_cpu|system_cpu:cpu|A_mem_baddr[11] ; 6 ; ; system:inst_cpu|system_cpu:cpu|A_mem_baddr[5] ; 6 ; -; system:inst_cpu|altera_merlin_slave_translator:sys_clk_timer_s1_translator|av_begintransfer~0 ; 6 ; +; system:inst_cpu|altera_merlin_traffic_limiter:limiter_001|suppress~2 ; 6 ; +; system:inst_cpu|altera_merlin_traffic_limiter:limiter_001|suppress~0 ; 6 ; ; system:inst_cpu|altera_avalon_sc_fifo:sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; 6 ; ; system:inst_cpu|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; 6 ; ; system:inst_cpu|altera_avalon_sc_fifo:pio_ir_emitter_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; 6 ; @@ -2437,6 +2436,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; system:inst_cpu|altera_merlin_slave_translator:cpu_jtag_debug_module_translator|wait_latency_counter[0] ; 6 ; ; system:inst_cpu|altera_avalon_sc_fifo:uart_mc_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; 6 ; ; system:inst_cpu|system_cpu:cpu|A_dc_wb_rd_data_first ; 6 ; +; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|Equal0~0 ; 6 ; ; system:inst_cpu|system_addr_router_001:addr_router_001|src_data[89]~0 ; 6 ; ; system:inst_cpu|system_cmd_xbar_demux:cmd_xbar_demux|src1_valid~0 ; 6 ; ; system:inst_cpu|system_sdram:sdram|pending~10 ; 6 ; @@ -2464,7 +2464,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[4]~23 ; 5 ; ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[4]~22 ; 5 ; ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[0]~19 ; 5 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[0]~14 ; 5 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[0]~16 ; 5 ; ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][0]~9 ; 5 ; ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][0]~2 ; 5 ; ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2]~3 ; 5 ; @@ -2472,21 +2472,22 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0]~12 ; 5 ; ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0]~5 ; 5 ; ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_proc~0 ; 5 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|Equal11~0 ; 5 ; -; system:inst_cpu|system_sys_clk_timer:sys_clk_timer|control_wr_strobe ; 5 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[1] ; 5 ; ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_rs232_counters:RS232_In_Counters|Equal0~2 ; 5 ; ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_rs232_counters:RS232_In_Counters|bit_counter[0] ; 5 ; ; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_rx:the_system_uart_wifi_rx|altera_std_synchronizer:the_altera_std_synchronizer|dreg[0] ; 5 ; ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_rs232_counters:RS232_In_Counters|all_bits_transmitted ; 5 ; -; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_rx:the_system_uart_wifi_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[0] ; 5 ; ; system:inst_cpu|system_cpu:cpu|D_control_reg_rddata_muxed[1]~0 ; 5 ; +; system:inst_cpu|system_sys_clk_timer:sys_clk_timer|control_wr_strobe ; 5 ; +; system:inst_cpu|system_sys_clk_timer:sys_clk_timer|period_l_wr_strobe~3 ; 5 ; ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw|counter_reg_bit[0] ; 5 ; ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw|counter_reg_bit[3] ; 5 ; ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw|counter_reg_bit[4] ; 5 ; ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw|counter_reg_bit[5] ; 5 ; ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw|counter_reg_bit[1] ; 5 ; ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw|counter_reg_bit[2] ; 5 ; -; system:inst_cpu|system_sdram:sdram|za_data[8] ; 5 ; +; system:inst_cpu|system_sdram:sdram|za_data[7] ; 5 ; +; system:inst_cpu|altera_merlin_slave_translator:sysid_control_slave_translator|av_readdata_pre[30] ; 5 ; ; system:inst_cpu|system_cpu:cpu|M_iw[6] ; 5 ; ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_rs232_counters:RS232_Out_Counters|bit_counter[0] ; 5 ; ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw|counter_reg_bit[1] ; 5 ; @@ -2537,6 +2538,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; system:inst_cpu|system_cpu:cpu|A_wr_data_unfiltered[2]~13 ; 5 ; ; system:inst_cpu|system_cpu:cpu|A_wr_data_unfiltered[3]~9 ; 5 ; ; system:inst_cpu|system_cpu:cpu|A_wr_data_unfiltered[4]~5 ; 5 ; +; system:inst_cpu|altera_merlin_traffic_limiter:limiter_001|response_accepted ; 5 ; ; system:inst_cpu|system_cpu:cpu|F_pc[1] ; 5 ; ; system:inst_cpu|system_cpu:cpu|F_pc[0] ; 5 ; ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|jupdate~0 ; 5 ; @@ -2560,9 +2562,8 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; system:inst_cpu|system_sdram:sdram|Selector33~0 ; 5 ; ; system:inst_cpu|system_sdram:sdram|m_count[0] ; 5 ; ; system:inst_cpu|system_cpu:cpu|A_shift_rot_stall ; 5 ; -; system:inst_cpu|altera_merlin_traffic_limiter:limiter_001|suppress~2 ; 5 ; -; system:inst_cpu|altera_merlin_traffic_limiter:limiter_001|suppress~0 ; 5 ; ; system:inst_cpu|altera_merlin_slave_translator:sys_clk_timer_s1_translator|wait_latency_counter[1] ; 5 ; +; system:inst_cpu|altera_merlin_slave_translator:sys_clk_timer_s1_translator|wait_latency_counter[0] ; 5 ; ; system:inst_cpu|altera_merlin_slave_translator:pio_ir_emitter_s1_translator|av_waitrequest_generated~0 ; 5 ; ; system:inst_cpu|altera_merlin_slave_translator:pio_led_s1_translator|av_waitrequest_generated~1 ; 5 ; ; system:inst_cpu|altera_merlin_slave_agent:pio_key_left_s1_translator_avalon_universal_slave_0_agent|m0_write~0 ; 5 ; @@ -2571,7 +2572,6 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; system:inst_cpu|altera_merlin_slave_translator:cpu_jtag_debug_module_translator|wait_latency_counter[1] ; 5 ; ; system:inst_cpu|altera_merlin_slave_translator:uart_mc_s1_translator|wait_latency_counter[1] ; 5 ; ; system:inst_cpu|system_cpu:cpu|ic_fill_ap_offset[0] ; 5 ; -; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|Equal0~0 ; 5 ; ; system:inst_cpu|system_addr_router_001:addr_router_001|src_channel[1]~0 ; 5 ; ; system:inst_cpu|system_addr_router_001:addr_router_001|Equal8~1 ; 5 ; ; system:inst_cpu|system_addr_router_001:addr_router_001|Equal5~1 ; 5 ; @@ -2588,18 +2588,18 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; system:inst_cpu|system_cpu:cpu|lpm_add_sub:Add17|add_sub_qvi:auto_generated|result_int[2]~4 ; 5 ; ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|td_shift[9] ; 5 ; ; system:inst_cpu|system_cpu:cpu|A_dc_fill_has_started ; 5 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[0]~19 ; 4 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[0]~15 ; 4 ; ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[0]~2 ; 4 ; ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[0]~0 ; 4 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|clear_signal ; 4 ; ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_info_reg_ena ; 4 ; ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_proc~0 ; 4 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[1]~6 ; 4 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[1]~8 ; 4 ; ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena_proc~0 ; 4 ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|Equal11~0 ; 4 ; ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[15] ; 4 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[1] ; 4 ; ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[4] ; 4 ; ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[1] ; 4 ; -; system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent|cp_ready~2 ; 4 ; ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_rs232_counters:RS232_In_Counters|bit_counter[2]~0 ; 4 ; ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_rs232_counters:RS232_In_Counters|bit_counter[1] ; 4 ; ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_rs232_counters:RS232_In_Counters|bit_counter[2] ; 4 ; @@ -2636,8 +2636,8 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; system:inst_cpu|system_sdram:sdram|za_data[5] ; 4 ; ; system:inst_cpu|system_sdram:sdram|za_data[14] ; 4 ; ; system:inst_cpu|system_sdram:sdram|za_data[6] ; 4 ; -; system:inst_cpu|system_sdram:sdram|za_data[7] ; 4 ; ; system:inst_cpu|system_sdram:sdram|za_data[15] ; 4 ; +; system:inst_cpu|system_sdram:sdram|za_data[8] ; 4 ; ; system:inst_cpu|system_sdram:sdram|za_data[0] ; 4 ; ; system:inst_cpu|system_sdram:sdram|za_data[9] ; 4 ; ; system:inst_cpu|system_sdram:sdram|za_data[1] ; 4 ; @@ -2743,7 +2743,6 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; system:inst_cpu|altera_merlin_traffic_limiter:limiter|save_dest_id~0 ; 4 ; ; system:inst_cpu|system_cpu:cpu|d_byteenable_nxt[1]~0 ; 4 ; ; system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux_001|update_grant~0 ; 4 ; -; system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux_001|WideOr1 ; 4 ; ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|count[1] ; 4 ; ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|user_saw_rvalid ; 4 ; ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|sld_virtual_jtag_basic:system_cpu_jtag_debug_module_phy|virtual_state_uir~0 ; 4 ; @@ -2753,7 +2752,6 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; system:inst_cpu|system_cpu:cpu|A_mem_stall ; 4 ; ; system:inst_cpu|system_cpu:cpu|A_mem_baddr[4] ; 4 ; ; system:inst_cpu|altera_merlin_slave_translator:sys_clk_timer_s1_translator|av_waitrequest_generated~0 ; 4 ; -; system:inst_cpu|altera_merlin_slave_translator:sys_clk_timer_s1_translator|wait_latency_counter[0] ; 4 ; ; system:inst_cpu|altera_merlin_slave_translator:pio_ir_emitter_s1_translator|wait_latency_counter[1] ; 4 ; ; system:inst_cpu|altera_merlin_slave_translator:pio_ir_emitter_s1_translator|wait_latency_counter[0] ; 4 ; ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|count[0] ; 4 ; @@ -2791,13 +2789,13 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_ca7:usedw_counter|counter_reg_bit[2] ; 4 ; ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_ca7:usedw_counter|counter_reg_bit[3] ; 4 ; ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_ca7:usedw_counter|counter_reg_bit[4] ; 4 ; -; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_ca7:usedw_counter|counter_reg_bit[5] ; 4 ; -; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_ca7:usedw_counter|counter_reg_bit[6] ; 4 ; ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_ca7:usedw_counter|counter_reg_bit[2] ; 4 ; -; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_ca7:usedw_counter|counter_reg_bit[3] ; 4 ; -; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_ca7:usedw_counter|counter_reg_bit[4] ; 4 ; ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_ca7:usedw_counter|counter_reg_bit[0] ; 4 ; ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_ca7:usedw_counter|counter_reg_bit[1] ; 4 ; +; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_ca7:usedw_counter|counter_reg_bit[3] ; 4 ; +; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_ca7:usedw_counter|counter_reg_bit[4] ; 4 ; +; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_ca7:usedw_counter|counter_reg_bit[5] ; 4 ; +; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_ca7:usedw_counter|counter_reg_bit[6] ; 4 ; ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[31] ; 4 ; ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_data_module:system_cpu_dc_data|altsyncram:the_altsyncram|altsyncram_2jf1:auto_generated|q_b[23] ; 4 ; ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_data_module:system_cpu_dc_data|altsyncram:the_altsyncram|altsyncram_2jf1:auto_generated|q_b[15] ; 4 ; @@ -2828,7 +2826,6 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[1] ; 4 ; ; system:inst_cpu|system_cpu:cpu|d_address_line_field[4] ; 4 ; ; system:inst_cpu|system_cpu:cpu|d_address_line_field[5] ; 4 ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR~9 ; 3 ; ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[0] ; 3 ; ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0] ; 3 ; ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_dr_scan_proc~0 ; 3 ; @@ -2841,7 +2838,6 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0 ; 3 ; ; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_regs:the_system_uart_wifi_regs|status_wr_strobe ; 3 ; ; system:inst_cpu|system_cpu:cpu|F_iw[14]~35 ; 3 ; -; system:inst_cpu|altera_merlin_traffic_limiter:limiter_001|pending_response_count[3]~14 ; 3 ; ; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_rx:the_system_uart_wifi_rx|delayed_unxsync_rxdxx1 ; 3 ; ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_rs232_counters:RS232_In_Counters|bit_counter[3] ; 3 ; ; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_tx:the_system_uart_wifi_tx|baud_clk_en ; 3 ; @@ -2870,6 +2866,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_rx:the_system_uart_wifi_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[7] ; 3 ; ; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_rx:the_system_uart_wifi_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[8] ; 3 ; ; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_rx:the_system_uart_wifi_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[9] ; 3 ; +; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_rx:the_system_uart_wifi_rx|delayed_unxrx_in_processxx3 ; 3 ; ; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_tx:the_system_uart_wifi_tx|WideOr0~2 ; 3 ; ; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_tx:the_system_uart_wifi_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[9] ; 3 ; ; system:inst_cpu|system_sys_clk_timer:sys_clk_timer|counter_is_running ; 3 ; @@ -2880,8 +2877,8 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|write1 ; 3 ; ; system:inst_cpu|system_cpu:cpu|M_st_data[21] ; 3 ; ; system:inst_cpu|system_cpu:cpu|M_st_data[22] ; 3 ; +; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[7] ; 3 ; ; system:inst_cpu|system_cpu:cpu|M_st_data[23] ; 3 ; -; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[8] ; 3 ; ; system:inst_cpu|system_cpu:cpu|M_st_data[16] ; 3 ; ; system:inst_cpu|system_cpu:cpu|M_st_data[17] ; 3 ; ; system:inst_cpu|system_cpu:cpu|M_st_data[18] ; 3 ; @@ -2932,6 +2929,9 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; system:inst_cpu|system_cpu:cpu|d_readdata_d1[26] ; 3 ; ; system:inst_cpu|system_cpu:cpu|d_readdata_d1[18] ; 3 ; ; system:inst_cpu|system_cpu:cpu|d_readdata_d1[27] ; 3 ; +; system:inst_cpu|system_cpu:cpu|d_readdata_d1[19] ; 3 ; +; system:inst_cpu|system_cpu:cpu|A_dc_fill_dp_offset[2] ; 3 ; +; system:inst_cpu|system_cpu:cpu|d_readdata_d1[28] ; 3 ; +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+ @@ -2940,19 +2940,19 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+----------------------------------------+--------------------------------------------------------------------------------------------------------------------------------+ ; Name ; Type ; Mode ; Clock Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Port A Input Registers ; Port A Output Registers ; Port B Input Registers ; Port B Output Registers ; Size ; Implementation Port A Depth ; Implementation Port A Width ; Implementation Port B Depth ; Implementation Port B Width ; Implementation Bits ; M9Ks ; MIF ; Location ; +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+----------------------------------------+--------------------------------------------------------------------------------------------------------------------------------+ -; system:inst_cpu|system_cpu:cpu|system_cpu_bht_module:system_cpu_bht|altsyncram:the_altsyncram|altsyncram_fhg1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 256 ; 2 ; 256 ; 2 ; yes ; no ; yes ; yes ; 512 ; 256 ; 2 ; 256 ; 2 ; 512 ; 1 ; system_cpu_bht_ram.mif ; M9K_X22_Y26_N0 ; -; system:inst_cpu|system_cpu:cpu|system_cpu_dc_data_module:system_cpu_dc_data|altsyncram:the_altsyncram|altsyncram_2jf1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Dual Clocks ; 1024 ; 32 ; 1024 ; 32 ; yes ; no ; yes ; no ; 32768 ; 1024 ; 32 ; 1024 ; 32 ; 32768 ; 4 ; None ; M9K_X33_Y17_N0, M9K_X33_Y18_N0, M9K_X33_Y20_N0, M9K_X33_Y19_N0 ; -; system:inst_cpu|system_cpu:cpu|system_cpu_dc_tag_module:system_cpu_dc_tag|altsyncram:the_altsyncram|altsyncram_d9g1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 128 ; 16 ; 128 ; 16 ; yes ; no ; yes ; no ; 2048 ; 128 ; 16 ; 128 ; 16 ; 2048 ; 1 ; system_cpu_dc_tag_ram.mif ; M9K_X33_Y21_N0 ; -; system:inst_cpu|system_cpu:cpu|system_cpu_dc_victim_module:system_cpu_dc_victim|altsyncram:the_altsyncram|altsyncram_r3d1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 8 ; 32 ; 8 ; 32 ; yes ; no ; yes ; no ; 256 ; 8 ; 32 ; 8 ; 32 ; 256 ; 1 ; None ; M9K_X22_Y17_N0 ; -; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Dual Clocks ; 2048 ; 32 ; 2048 ; 32 ; yes ; no ; yes ; no ; 65536 ; 2048 ; 32 ; 2048 ; 32 ; 65536 ; 8 ; None ; M9K_X22_Y23_N0, M9K_X22_Y22_N0, M9K_X22_Y25_N0, M9K_X22_Y24_N0, M9K_X22_Y21_N0, M9K_X22_Y16_N0, M9K_X22_Y20_N0, M9K_X22_Y18_N0 ; -; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 256 ; 21 ; 256 ; 21 ; yes ; no ; yes ; no ; 5376 ; 256 ; 21 ; 256 ; 21 ; 5376 ; 1 ; system_cpu_ic_tag_ram.mif ; M9K_X22_Y19_N0 ; -; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port ; Single Clock ; 256 ; 32 ; 256 ; 32 ; yes ; no ; yes ; no ; 8192 ; 256 ; 32 ; 256 ; 32 ; 8192 ; 2 ; system_cpu_ociram_default_contents.mif ; M9K_X22_Y14_N0, M9K_X22_Y15_N0 ; -; system:inst_cpu|system_cpu:cpu|system_cpu_register_bank_a_module:system_cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_fvf1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 32 ; 32 ; 32 ; 32 ; yes ; no ; yes ; no ; 1024 ; 32 ; 32 ; 32 ; 32 ; 1024 ; 1 ; system_cpu_rf_ram_a.mif ; M9K_X33_Y24_N0 ; -; system:inst_cpu|system_cpu:cpu|system_cpu_register_bank_b_module:system_cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_gvf1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 32 ; 32 ; 32 ; 32 ; yes ; no ; yes ; no ; 1024 ; 32 ; 32 ; 32 ; 32 ; 1024 ; 1 ; system_cpu_rf_ram_b.mif ; M9K_X33_Y25_N0 ; -; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Dual Clocks ; 64 ; 8 ; 64 ; 8 ; yes ; no ; yes ; no ; 512 ; 64 ; 8 ; 64 ; 8 ; 512 ; 1 ; None ; M9K_X22_Y12_N0 ; -; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Dual Clocks ; 64 ; 8 ; 64 ; 8 ; yes ; no ; yes ; yes ; 512 ; 64 ; 8 ; 64 ; 8 ; 512 ; 1 ; None ; M9K_X22_Y11_N0 ; -; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Dual Clocks ; 128 ; 8 ; 128 ; 8 ; yes ; no ; yes ; no ; 1024 ; 128 ; 8 ; 128 ; 8 ; 1024 ; 1 ; None ; M9K_X33_Y10_N0 ; -; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Dual Clocks ; 128 ; 8 ; 128 ; 8 ; yes ; no ; yes ; no ; 1024 ; 128 ; 8 ; 128 ; 8 ; 1024 ; 1 ; None ; M9K_X33_Y9_N0 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_bht_module:system_cpu_bht|altsyncram:the_altsyncram|altsyncram_fhg1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 256 ; 2 ; 256 ; 2 ; yes ; no ; yes ; yes ; 512 ; 256 ; 2 ; 256 ; 2 ; 512 ; 1 ; system_cpu_bht_ram.mif ; M9K_X33_Y16_N0 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_dc_data_module:system_cpu_dc_data|altsyncram:the_altsyncram|altsyncram_2jf1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Dual Clocks ; 1024 ; 32 ; 1024 ; 32 ; yes ; no ; yes ; no ; 32768 ; 1024 ; 32 ; 1024 ; 32 ; 32768 ; 4 ; None ; M9K_X22_Y16_N0, M9K_X22_Y18_N0, M9K_X22_Y17_N0, M9K_X22_Y19_N0 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_dc_tag_module:system_cpu_dc_tag|altsyncram:the_altsyncram|altsyncram_d9g1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 128 ; 16 ; 128 ; 16 ; yes ; no ; yes ; no ; 2048 ; 128 ; 16 ; 128 ; 16 ; 2048 ; 1 ; system_cpu_dc_tag_ram.mif ; M9K_X33_Y17_N0 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_dc_victim_module:system_cpu_dc_victim|altsyncram:the_altsyncram|altsyncram_r3d1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 8 ; 32 ; 8 ; 32 ; yes ; no ; yes ; no ; 256 ; 8 ; 32 ; 8 ; 32 ; 256 ; 1 ; None ; M9K_X22_Y15_N0 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Dual Clocks ; 2048 ; 32 ; 2048 ; 32 ; yes ; no ; yes ; no ; 65536 ; 2048 ; 32 ; 2048 ; 32 ; 65536 ; 8 ; None ; M9K_X33_Y12_N0, M9K_X22_Y12_N0, M9K_X33_Y15_N0, M9K_X22_Y14_N0, M9K_X33_Y14_N0, M9K_X33_Y13_N0, M9K_X33_Y11_N0, M9K_X22_Y13_N0 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 256 ; 21 ; 256 ; 21 ; yes ; no ; yes ; no ; 5376 ; 256 ; 21 ; 256 ; 21 ; 5376 ; 1 ; system_cpu_ic_tag_ram.mif ; M9K_X33_Y10_N0 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port ; Single Clock ; 256 ; 32 ; 256 ; 32 ; yes ; no ; yes ; no ; 8192 ; 256 ; 32 ; 256 ; 32 ; 8192 ; 2 ; system_cpu_ociram_default_contents.mif ; M9K_X22_Y9_N0, M9K_X22_Y10_N0 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_register_bank_a_module:system_cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_fvf1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 32 ; 32 ; 32 ; 32 ; yes ; no ; yes ; no ; 1024 ; 32 ; 32 ; 32 ; 32 ; 1024 ; 1 ; system_cpu_rf_ram_a.mif ; M9K_X33_Y19_N0 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_register_bank_b_module:system_cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_gvf1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 32 ; 32 ; 32 ; 32 ; yes ; no ; yes ; no ; 1024 ; 32 ; 32 ; 32 ; 32 ; 1024 ; 1 ; system_cpu_rf_ram_b.mif ; M9K_X33_Y18_N0 ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Dual Clocks ; 64 ; 8 ; 64 ; 8 ; yes ; no ; yes ; no ; 512 ; 64 ; 8 ; 64 ; 8 ; 512 ; 1 ; None ; M9K_X22_Y20_N0 ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Dual Clocks ; 64 ; 8 ; 64 ; 8 ; yes ; no ; yes ; yes ; 512 ; 64 ; 8 ; 64 ; 8 ; 512 ; 1 ; None ; M9K_X22_Y21_N0 ; +; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Dual Clocks ; 128 ; 8 ; 128 ; 8 ; yes ; no ; yes ; no ; 1024 ; 128 ; 8 ; 128 ; 8 ; 1024 ; 1 ; None ; M9K_X22_Y22_N0 ; +; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Dual Clocks ; 128 ; 8 ; 128 ; 8 ; yes ; no ; yes ; no ; 1024 ; 128 ; 8 ; 128 ; 8 ; 1024 ; 1 ; None ; M9K_X22_Y23_N0 ; +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+----------------------------------------+--------------------------------------------------------------------------------------------------------------------------------+ Note: Fitter may spread logical memories into multiple blocks to improve timing. The actual required RAM blocks can be found in the Fitter Resource Usage section. @@ -2979,10 +2979,10 @@ Note: Fitter may spread logical memories into multiple blocks to improve timing. +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------+--------------------+---------------------+--------------------------------+-----------------------+-----------------------+-------------------+-----------------+ ; Name ; Mode ; Location ; Sign Representation ; Has Input Shift Register Chain ; Data A Input Register ; Data B Input Register ; Pipeline Register ; Output Register ; +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------+--------------------+---------------------+--------------------------------+-----------------------+-----------------------+-------------------+-----------------+ -; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3 ; Simple Multiplier (18-bit) ; DSPOUT_X13_Y23_N2 ; ; No ; ; ; ; yes ; -; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_mult2 ; ; DSPMULT_X13_Y23_N0 ; Unsigned ; ; yes ; yes ; no ; ; -; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3 ; Simple Multiplier (18-bit) ; DSPOUT_X13_Y22_N2 ; ; No ; ; ; ; yes ; -; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated|ded_mult_ks81:ded_mult1|mac_mult2 ; ; DSPMULT_X13_Y22_N0 ; Unsigned ; ; yes ; yes ; no ; ; +; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3 ; Simple Multiplier (18-bit) ; DSPOUT_X13_Y20_N2 ; ; No ; ; ; ; yes ; +; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_mult2 ; ; DSPMULT_X13_Y20_N0 ; Unsigned ; ; yes ; yes ; no ; ; +; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3 ; Simple Multiplier (18-bit) ; DSPOUT_X13_Y19_N2 ; ; No ; ; ; ; yes ; +; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated|ded_mult_ks81:ded_mult1|mac_mult2 ; ; DSPMULT_X13_Y19_N0 ; Unsigned ; ; yes ; yes ; no ; ; +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------+--------------------+---------------------+--------------------------------+-----------------------+-----------------------+-------------------+-----------------+ @@ -2991,173 +2991,174 @@ Note: Fitter may spread logical memories into multiple blocks to improve timing. +-----------------------------+-------------------------+ ; Other Routing Resource Type ; Usage ; +-----------------------------+-------------------------+ -; Block interconnects ; 7,239 / 71,559 ( 10 % ) ; -; C16 interconnects ; 66 / 2,597 ( 3 % ) ; -; C4 interconnects ; 3,789 / 46,848 ( 8 % ) ; -; Direct links ; 970 / 71,559 ( 1 % ) ; +; Block interconnects ; 7,344 / 71,559 ( 10 % ) ; +; C16 interconnects ; 64 / 2,597 ( 2 % ) ; +; C4 interconnects ; 3,873 / 46,848 ( 8 % ) ; +; Direct links ; 948 / 71,559 ( 1 % ) ; ; Global clocks ; 8 / 20 ( 40 % ) ; -; Local interconnects ; 2,588 / 24,624 ( 11 % ) ; -; R24 interconnects ; 126 / 2,496 ( 5 % ) ; -; R4 interconnects ; 4,661 / 62,424 ( 7 % ) ; +; Local interconnects ; 2,532 / 24,624 ( 10 % ) ; +; R24 interconnects ; 142 / 2,496 ( 6 % ) ; +; R4 interconnects ; 4,950 / 62,424 ( 8 % ) ; +-----------------------------+-------------------------+ +-----------------------------------------------------------------------------+ ; LAB Logic Elements ; +---------------------------------------------+-------------------------------+ -; Number of Logic Elements (Average = 13.66) ; Number of LABs (Total = 348) ; +; Number of Logic Elements (Average = 13.77) ; Number of LABs (Total = 342) ; +---------------------------------------------+-------------------------------+ -; 1 ; 14 ; -; 2 ; 4 ; -; 3 ; 4 ; -; 4 ; 3 ; -; 5 ; 6 ; +; 1 ; 9 ; +; 2 ; 8 ; +; 3 ; 7 ; +; 4 ; 4 ; +; 5 ; 0 ; ; 6 ; 5 ; -; 7 ; 6 ; -; 8 ; 5 ; -; 9 ; 10 ; -; 10 ; 6 ; -; 11 ; 7 ; -; 12 ; 6 ; -; 13 ; 6 ; -; 14 ; 18 ; -; 15 ; 33 ; -; 16 ; 215 ; +; 7 ; 0 ; +; 8 ; 6 ; +; 9 ; 9 ; +; 10 ; 8 ; +; 11 ; 4 ; +; 12 ; 8 ; +; 13 ; 14 ; +; 14 ; 19 ; +; 15 ; 34 ; +; 16 ; 207 ; +---------------------------------------------+-------------------------------+ +--------------------------------------------------------------------+ ; LAB-wide Signals ; +------------------------------------+-------------------------------+ -; LAB-wide Signals (Average = 2.66) ; Number of LABs (Total = 348) ; +; LAB-wide Signals (Average = 2.69) ; Number of LABs (Total = 342) ; +------------------------------------+-------------------------------+ -; 1 Async. clear ; 277 ; -; 1 Clock ; 329 ; -; 1 Clock enable ; 171 ; -; 1 Sync. clear ; 19 ; -; 1 Sync. load ; 63 ; -; 2 Async. clears ; 3 ; -; 2 Clock enables ; 57 ; -; 2 Clocks ; 7 ; +; 1 Async. clear ; 271 ; +; 1 Clock ; 321 ; +; 1 Clock enable ; 173 ; +; 1 Sync. clear ; 18 ; +; 1 Sync. load ; 67 ; +; 2 Async. clears ; 5 ; +; 2 Clock enables ; 55 ; +; 2 Clocks ; 10 ; +------------------------------------+-------------------------------+ +------------------------------------------------------------------------------+ ; LAB Signals Sourced ; +----------------------------------------------+-------------------------------+ -; Number of Signals Sourced (Average = 21.67) ; Number of LABs (Total = 348) ; +; Number of Signals Sourced (Average = 21.97) ; Number of LABs (Total = 342) ; +----------------------------------------------+-------------------------------+ -; 0 ; 2 ; -; 1 ; 5 ; -; 2 ; 7 ; -; 3 ; 1 ; -; 4 ; 3 ; -; 5 ; 2 ; +; 0 ; 1 ; +; 1 ; 4 ; +; 2 ; 5 ; +; 3 ; 5 ; +; 4 ; 5 ; +; 5 ; 1 ; ; 6 ; 3 ; ; 7 ; 3 ; ; 8 ; 1 ; ; 9 ; 3 ; -; 10 ; 4 ; +; 10 ; 2 ; ; 11 ; 3 ; -; 12 ; 2 ; -; 13 ; 6 ; -; 14 ; 8 ; -; 15 ; 4 ; +; 12 ; 5 ; +; 13 ; 1 ; +; 14 ; 3 ; +; 15 ; 5 ; ; 16 ; 11 ; -; 17 ; 5 ; +; 17 ; 3 ; ; 18 ; 5 ; -; 19 ; 14 ; -; 20 ; 16 ; -; 21 ; 20 ; -; 22 ; 28 ; -; 23 ; 26 ; -; 24 ; 30 ; -; 25 ; 22 ; -; 26 ; 28 ; -; 27 ; 21 ; -; 28 ; 14 ; -; 29 ; 17 ; -; 30 ; 15 ; -; 31 ; 3 ; -; 32 ; 16 ; +; 19 ; 11 ; +; 20 ; 18 ; +; 21 ; 23 ; +; 22 ; 31 ; +; 23 ; 25 ; +; 24 ; 26 ; +; 25 ; 23 ; +; 26 ; 23 ; +; 27 ; 26 ; +; 28 ; 15 ; +; 29 ; 11 ; +; 30 ; 13 ; +; 31 ; 8 ; +; 32 ; 20 ; +----------------------------------------------+-------------------------------+ +---------------------------------------------------------------------------------+ ; LAB Signals Sourced Out ; +-------------------------------------------------+-------------------------------+ -; Number of Signals Sourced Out (Average = 9.54) ; Number of LABs (Total = 348) ; +; Number of Signals Sourced Out (Average = 9.78) ; Number of LABs (Total = 342) ; +-------------------------------------------------+-------------------------------+ -; 0 ; 3 ; -; 1 ; 17 ; -; 2 ; 8 ; -; 3 ; 7 ; -; 4 ; 12 ; -; 5 ; 17 ; -; 6 ; 23 ; -; 7 ; 29 ; -; 8 ; 32 ; -; 9 ; 23 ; -; 10 ; 35 ; -; 11 ; 29 ; -; 12 ; 20 ; -; 13 ; 18 ; -; 14 ; 24 ; -; 15 ; 18 ; +; 0 ; 2 ; +; 1 ; 18 ; +; 2 ; 9 ; +; 3 ; 6 ; +; 4 ; 7 ; +; 5 ; 13 ; +; 6 ; 19 ; +; 7 ; 18 ; +; 8 ; 44 ; +; 9 ; 33 ; +; 10 ; 30 ; +; 11 ; 23 ; +; 12 ; 34 ; +; 13 ; 21 ; +; 14 ; 20 ; +; 15 ; 6 ; ; 16 ; 21 ; -; 17 ; 1 ; -; 18 ; 4 ; -; 19 ; 2 ; +; 17 ; 5 ; +; 18 ; 3 ; +; 19 ; 0 ; ; 20 ; 1 ; -; 21 ; 0 ; -; 22 ; 1 ; -; 23 ; 0 ; -; 24 ; 1 ; -; 25 ; 0 ; -; 26 ; 2 ; +; 21 ; 2 ; +; 22 ; 3 ; +; 23 ; 1 ; +; 24 ; 0 ; +; 25 ; 1 ; +; 26 ; 1 ; +; 27 ; 1 ; +-------------------------------------------------+-------------------------------+ +------------------------------------------------------------------------------+ ; LAB Distinct Inputs ; +----------------------------------------------+-------------------------------+ -; Number of Distinct Inputs (Average = 18.31) ; Number of LABs (Total = 348) ; +; Number of Distinct Inputs (Average = 18.92) ; Number of LABs (Total = 342) ; +----------------------------------------------+-------------------------------+ ; 0 ; 0 ; -; 1 ; 2 ; +; 1 ; 1 ; ; 2 ; 7 ; -; 3 ; 3 ; -; 4 ; 12 ; -; 5 ; 9 ; -; 6 ; 5 ; -; 7 ; 8 ; -; 8 ; 8 ; -; 9 ; 13 ; -; 10 ; 4 ; -; 11 ; 10 ; -; 12 ; 13 ; -; 13 ; 9 ; -; 14 ; 17 ; -; 15 ; 12 ; -; 16 ; 17 ; -; 17 ; 7 ; -; 18 ; 16 ; -; 19 ; 20 ; -; 20 ; 13 ; -; 21 ; 15 ; -; 22 ; 15 ; +; 3 ; 10 ; +; 4 ; 6 ; +; 5 ; 7 ; +; 6 ; 7 ; +; 7 ; 3 ; +; 8 ; 12 ; +; 9 ; 10 ; +; 10 ; 5 ; +; 11 ; 7 ; +; 12 ; 15 ; +; 13 ; 7 ; +; 14 ; 14 ; +; 15 ; 7 ; +; 16 ; 13 ; +; 17 ; 10 ; +; 18 ; 15 ; +; 19 ; 17 ; +; 20 ; 12 ; +; 21 ; 12 ; +; 22 ; 17 ; ; 23 ; 9 ; ; 24 ; 13 ; -; 25 ; 9 ; -; 26 ; 6 ; +; 25 ; 10 ; +; 26 ; 9 ; ; 27 ; 9 ; -; 28 ; 11 ; -; 29 ; 12 ; -; 30 ; 5 ; -; 31 ; 11 ; -; 32 ; 7 ; -; 33 ; 11 ; -; 34 ; 9 ; +; 28 ; 18 ; +; 29 ; 14 ; +; 30 ; 15 ; +; 31 ; 6 ; +; 32 ; 8 ; +; 33 ; 10 ; +; 34 ; 6 ; +----------------------------------------------+-------------------------------+ @@ -3393,62 +3394,79 @@ Note: Fitter may spread logical memories into multiple blocks to improve timing. +----------------------------------------------------------+----------------------------------------------------------+-------------------+ ; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ; +----------------------------------------------------------+----------------------------------------------------------+-------------------+ -; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 4.5 ; +; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 7.1 ; +----------------------------------------------------------+----------------------------------------------------------+-------------------+ Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off. This will disable optimization of problematic paths and expose them for further analysis using either the TimeQuest Timing Analyzer or the Classic Timing Analyzer. -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Estimated Delay Added for Hold Timing Details ; -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+ -; Source Register ; Destination Register ; Delay Added in ns ; -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+ -; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|data_in_shift_reg[4] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a3~porta_datain_reg0 ; 0.228 ; -; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|data_in_shift_reg[2] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a1~porta_datain_reg0 ; 0.228 ; -; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|data_in_shift_reg[3] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a2~porta_datain_reg0 ; 0.217 ; -; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|data_in_shift_reg[5] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a4~porta_datain_reg0 ; 0.217 ; -; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|data_in_shift_reg[6] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a5~porta_datain_reg0 ; 0.217 ; -; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|data_in_shift_reg[7] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a6~porta_datain_reg0 ; 0.217 ; -; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|data_in_shift_reg[1] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_datain_reg0 ; 0.217 ; -; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|data_in_shift_reg[8] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a7~porta_datain_reg0 ; 0.217 ; -; system:inst_cpu|system_rs232_wifi:rs232_wifi|data_to_uart[5] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a5~porta_datain_reg0 ; 0.217 ; -; system:inst_cpu|system_rs232_wifi:rs232_wifi|data_to_uart[1] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a1~porta_datain_reg0 ; 0.217 ; -; system:inst_cpu|system_rs232_wifi:rs232_wifi|data_to_uart[0] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_datain_reg0 ; 0.217 ; -; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[6] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a7~porta_address_reg0 ; 0.201 ; -; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[0] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a7~porta_address_reg0 ; 0.200 ; -; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[1] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a7~porta_address_reg0 ; 0.200 ; -; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[2] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a7~porta_address_reg0 ; 0.200 ; -; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[3] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a7~porta_address_reg0 ; 0.200 ; -; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[4] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a7~porta_address_reg0 ; 0.200 ; -; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[5] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a7~porta_address_reg0 ; 0.200 ; -; system:inst_cpu|system_cpu:cpu|M_bht_ptr_unfiltered[4] ; system:inst_cpu|system_cpu:cpu|system_cpu_bht_module:system_cpu_bht|altsyncram:the_altsyncram|altsyncram_fhg1:auto_generated|ram_block1a1~porta_address_reg0 ; 0.129 ; -; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[5] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a5~portb_datain_reg0 ; 0.026 ; -; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][84] ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[3][84] ; 0.023 ; -; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][56] ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[3][56] ; 0.023 ; -; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][53] ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[3][53] ; 0.023 ; -; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][19] ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[3][19] ; 0.023 ; -; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|jdo[19] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_debug:the_system_cpu_nios2_oci_debug|probepresent ; 0.023 ; -; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][55] ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[3][55] ; 0.023 ; -; system:inst_cpu|system_cpu:cpu|A_dc_rd_data[29] ; system:inst_cpu|system_cpu:cpu|A_dc_xfer_wr_data[29] ; 0.022 ; -; system:inst_cpu|system_cpu:cpu|A_dc_rd_data[3] ; system:inst_cpu|system_cpu:cpu|A_dc_xfer_wr_data[3] ; 0.022 ; -; system:inst_cpu|system_cpu:cpu|A_dc_rd_data[24] ; system:inst_cpu|system_cpu:cpu|A_dc_xfer_wr_data[24] ; 0.022 ; -; system:inst_cpu|system_cpu:cpu|A_dc_rd_data[12] ; system:inst_cpu|system_cpu:cpu|A_dc_xfer_wr_data[12] ; 0.022 ; -; system:inst_cpu|system_cpu:cpu|A_dc_rd_data[11] ; system:inst_cpu|system_cpu:cpu|A_dc_xfer_wr_data[11] ; 0.022 ; -; system:inst_cpu|system_cpu:cpu|A_dc_rd_data[8] ; system:inst_cpu|system_cpu:cpu|A_dc_xfer_wr_data[8] ; 0.022 ; -; system:inst_cpu|system_uart_mc:uart_mc|system_uart_mc_tx:the_system_uart_mc_tx|do_load_shifter ; system:inst_cpu|system_uart_mc:uart_mc|system_uart_mc_tx:the_system_uart_mc_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[9] ; 0.022 ; -; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][83] ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[3][83] ; 0.022 ; -; system:inst_cpu|system_cpu:cpu|A_dc_rd_data[19] ; system:inst_cpu|system_cpu:cpu|A_dc_xfer_wr_data[19] ; 0.022 ; -; system:inst_cpu|system_cpu:cpu|A_dc_rd_data[26] ; system:inst_cpu|system_cpu:cpu|A_dc_xfer_wr_data[26] ; 0.022 ; -; system:inst_cpu|system_cpu:cpu|A_dc_rd_data[30] ; system:inst_cpu|system_cpu:cpu|A_dc_xfer_wr_data[30] ; 0.022 ; -; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[6] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a6~portb_datain_reg0 ; 0.017 ; -; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[10] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a10~portb_datain_reg0 ; 0.017 ; -; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[11] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a11~portb_datain_reg0 ; 0.017 ; -; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[29] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a29~portb_datain_reg0 ; 0.016 ; -; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[2] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a2~portb_datain_reg0 ; 0.016 ; -; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[15] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a15~portb_datain_reg0 ; 0.012 ; -; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_rx:the_system_uart_wifi_rx|altera_std_synchronizer:the_altera_std_synchronizer|dreg[0] ; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_rx:the_system_uart_wifi_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[9] ; 0.012 ; -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+ ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Estimated Delay Added for Hold Timing Details ; ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+ +; Source Register ; Destination Register ; Delay Added in ns ; ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+ +; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|data_in_shift_reg[4] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a3~porta_datain_reg0 ; 0.228 ; +; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|data_in_shift_reg[2] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a1~porta_datain_reg0 ; 0.228 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[9] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a9~portb_datain_reg0 ; 0.222 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[17] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a17~portb_datain_reg0 ; 0.222 ; +; system:inst_cpu|system_rs232_wifi:rs232_wifi|data_to_uart[2] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a2~porta_datain_reg0 ; 0.217 ; +; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|data_in_shift_reg[3] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a2~porta_datain_reg0 ; 0.217 ; +; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|data_in_shift_reg[1] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_datain_reg0 ; 0.217 ; +; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|data_in_shift_reg[8] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a7~porta_datain_reg0 ; 0.217 ; +; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|data_in_shift_reg[5] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a4~porta_datain_reg0 ; 0.217 ; +; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|data_in_shift_reg[6] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a5~porta_datain_reg0 ; 0.217 ; +; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|data_in_shift_reg[7] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a6~porta_datain_reg0 ; 0.217 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[3] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a3~portb_datain_reg0 ; 0.212 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[4] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a4~portb_datain_reg0 ; 0.212 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[15] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a15~portb_datain_reg0 ; 0.212 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[20] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a20~portb_datain_reg0 ; 0.212 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[12] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a12~portb_datain_reg0 ; 0.212 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonAReg[8] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a31~portb_address_reg0 ; 0.202 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonAReg[7] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a31~portb_address_reg0 ; 0.202 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonAReg[9] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_address_reg0 ; 0.201 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonAReg[6] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a30~portb_address_reg0 ; 0.201 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonAReg[3] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a27~portb_address_reg0 ; 0.201 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonAReg[5] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a26~portb_address_reg0 ; 0.201 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonAReg[4] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a28~portb_address_reg0 ; 0.201 ; +; system:inst_cpu|system_cpu:cpu|M_bht_ptr_unfiltered[2] ; system:inst_cpu|system_cpu:cpu|system_cpu_bht_module:system_cpu_bht|altsyncram:the_altsyncram|altsyncram_fhg1:auto_generated|ram_block1a1~porta_address_reg0 ; 0.201 ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[5] ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a7~porta_address_reg0 ; 0.128 ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[0] ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a7~porta_address_reg0 ; 0.128 ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[1] ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a7~porta_address_reg0 ; 0.128 ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[2] ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a7~porta_address_reg0 ; 0.128 ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[3] ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a7~porta_address_reg0 ; 0.128 ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[4] ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a7~porta_address_reg0 ; 0.128 ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:rd_ptr_count|counter_reg_bit[5] ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a7~portb_address_reg0 ; 0.120 ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:rd_ptr_count|counter_reg_bit[0] ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a7~portb_address_reg0 ; 0.119 ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:rd_ptr_count|counter_reg_bit[1] ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a7~portb_address_reg0 ; 0.119 ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:rd_ptr_count|counter_reg_bit[2] ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a7~portb_address_reg0 ; 0.119 ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:rd_ptr_count|counter_reg_bit[3] ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a7~portb_address_reg0 ; 0.119 ; +; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:rd_ptr_count|counter_reg_bit[4] ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a7~portb_address_reg0 ; 0.119 ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[6] ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[7] ; 0.023 ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[2][56] ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][56] ; 0.023 ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][56] ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][56] ; 0.023 ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[2][53] ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][53] ; 0.023 ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][53] ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][53] ; 0.023 ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[2][19] ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][19] ; 0.023 ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][19] ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][19] ; 0.023 ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[2][84] ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][84] ; 0.023 ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][84] ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][84] ; 0.023 ; +; system:inst_cpu|system_cpu:cpu|A_dc_rd_data[9] ; system:inst_cpu|system_cpu:cpu|A_dc_xfer_wr_data[9] ; 0.023 ; +; system:inst_cpu|system_cpu:cpu|A_dc_rd_data[10] ; system:inst_cpu|system_cpu:cpu|A_dc_xfer_wr_data[10] ; 0.023 ; +; system:inst_cpu|system_cpu:cpu|A_dc_rd_data[20] ; system:inst_cpu|system_cpu:cpu|A_dc_xfer_wr_data[20] ; 0.023 ; +; system:inst_cpu|system_cpu:cpu|A_dc_rd_data[19] ; system:inst_cpu|system_cpu:cpu|A_dc_xfer_wr_data[19] ; 0.023 ; +; system:inst_cpu|system_cpu:cpu|A_dc_rd_data[25] ; system:inst_cpu|system_cpu:cpu|A_dc_xfer_wr_data[25] ; 0.023 ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[2][55] ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][55] ; 0.023 ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][55] ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][55] ; 0.023 ; +; system:inst_cpu|system_cpu:cpu|A_dc_rd_data[29] ; system:inst_cpu|system_cpu:cpu|A_dc_xfer_wr_data[29] ; 0.022 ; +; system:inst_cpu|system_cpu:cpu|A_dc_rd_data[2] ; system:inst_cpu|system_cpu:cpu|A_dc_xfer_wr_data[2] ; 0.022 ; +; system:inst_cpu|system_cpu:cpu|A_dc_rd_data[26] ; system:inst_cpu|system_cpu:cpu|A_dc_xfer_wr_data[26] ; 0.022 ; +; system:inst_cpu|system_cpu:cpu|A_dc_rd_data[30] ; system:inst_cpu|system_cpu:cpu|A_dc_xfer_wr_data[30] ; 0.022 ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[2][83] ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][83] ; 0.022 ; +; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][83] ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][83] ; 0.022 ; +; system:inst_cpu|system_cpu:cpu|A_dc_rd_data[12] ; system:inst_cpu|system_cpu:cpu|A_dc_xfer_wr_data[12] ; 0.022 ; +; system:inst_cpu|system_cpu:cpu|i_readdata_d1[3] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a3~porta_datain_reg0 ; 0.022 ; +; system:inst_cpu|system_cpu:cpu|M_ctrl_shift_rot ; system:inst_cpu|system_cpu:cpu|A_shift_rot_stall ; 0.021 ; ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+ Note: This table only shows the top 100 paths that have the largest delay added for hold. @@ -3458,7 +3476,7 @@ Note: This table only shows the top 100 paths that have the largest delay added Info: ******************************************************************* Info: Running Quartus II 64-Bit Fitter Info: Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Full Version - Info: Processing started: Sun Mar 02 18:54:08 2014 + Info: Processing started: Mon Mar 03 16:12:21 2014 Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off de0_nano_system -c de0_nano_system Info (11104): Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead. Info (119006): Selected device EP4CE22F17C6 for design "de0_nano_system" @@ -3634,9 +3652,9 @@ Info (170191): Fitter placement operations beginning Info (170137): Fitter placement was successful Info (170192): Fitter placement operations ending: elapsed time is 00:00:07 Info (170193): Fitter routing operations beginning -Info (170195): Router estimated average interconnect usage is 6% of the available device resources - Info (170196): Router estimated peak interconnect usage is 37% of the available device resources in the region that extends from location X21_Y11 to location X31_Y22 -Info (170194): Fitter routing operations ending: elapsed time is 00:00:06 +Info (170195): Router estimated average interconnect usage is 7% of the available device resources + Info (170196): Router estimated peak interconnect usage is 36% of the available device resources in the region that extends from location X21_Y11 to location X31_Y22 +Info (170194): Fitter routing operations ending: elapsed time is 00:00:09 Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. Info (170201): Optimizations that may affect the design's routability were skipped Info (170200): Optimizations that may affect the design's timing were skipped @@ -3717,10 +3735,10 @@ Warning (169064): Following 68 pins have no output enable or a GND or VCC output Info (169065): Pin GPIO_1[33] has a permanently enabled output enable Info (144001): Generated suppressed messages file C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/output_files/de0_nano_system.fit.smsg Info: Quartus II 64-Bit Fitter was successful. 0 errors, 36 warnings - Info: Peak virtual memory: 1138 megabytes - Info: Processing ended: Sun Mar 02 18:54:46 2014 - Info: Elapsed time: 00:00:38 - Info: Total CPU time (on all processors): 00:00:47 + Info: Peak virtual memory: 1135 megabytes + Info: Processing ended: Mon Mar 03 16:13:03 2014 + Info: Elapsed time: 00:00:42 + Info: Total CPU time (on all processors): 00:00:52 +----------------------------+ diff --git a/MCandWifiTestDE0/output_files/de0_nano_system.fit.summary b/MCandWifiTestDE0/output_files/de0_nano_system.fit.summary index 1ce5a1d0..71397b22 100644 --- a/MCandWifiTestDE0/output_files/de0_nano_system.fit.summary +++ b/MCandWifiTestDE0/output_files/de0_nano_system.fit.summary @@ -1,11 +1,11 @@ -Fitter Status : Successful - Sun Mar 02 18:54:45 2014 +Fitter Status : Successful - Mon Mar 03 16:13:01 2014 Quartus II 64-Bit Version : 12.1 Build 243 01/31/2013 SP 1.33 SJ Full Version Revision Name : de0_nano_system Top-level Entity Name : de0_nano_system Family : Cyclone IV E Device : EP4CE22F17C6 Timing Models : Final -Total logic elements : 4,752 / 22,320 ( 21 % ) +Total logic elements : 4,711 / 22,320 ( 21 % ) Total combinational functions : 4,105 / 22,320 ( 18 % ) Dedicated logic registers : 2,919 / 22,320 ( 13 % ) Total registers : 2988 diff --git a/MCandWifiTestDE0/output_files/de0_nano_system.flow.rpt b/MCandWifiTestDE0/output_files/de0_nano_system.flow.rpt index 0d3a9676..190ba3b5 100644 --- a/MCandWifiTestDE0/output_files/de0_nano_system.flow.rpt +++ b/MCandWifiTestDE0/output_files/de0_nano_system.flow.rpt @@ -1,5 +1,5 @@ Flow report for de0_nano_system -Sun Mar 02 18:54:57 2014 +Mon Mar 03 16:13:13 2014 Quartus II 64-Bit Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Full Version @@ -38,14 +38,14 @@ applicable agreement for further details. +----------------------------------------------------------------------------------------+ ; Flow Summary ; +------------------------------------+---------------------------------------------------+ -; Flow Status ; Successful - Sun Mar 02 18:54:50 2014 ; +; Flow Status ; Successful - Mon Mar 03 16:13:06 2014 ; ; Quartus II 64-Bit Version ; 12.1 Build 243 01/31/2013 SP 1.33 SJ Full Version ; ; Revision Name ; de0_nano_system ; ; Top-level Entity Name ; de0_nano_system ; ; Family ; Cyclone IV E ; ; Device ; EP4CE22F17C6 ; ; Timing Models ; Final ; -; Total logic elements ; 4,752 / 22,320 ( 21 % ) ; +; Total logic elements ; 4,711 / 22,320 ( 21 % ) ; ; Total combinational functions ; 4,105 / 22,320 ( 18 % ) ; ; Dedicated logic registers ; 2,919 / 22,320 ( 13 % ) ; ; Total registers ; 2988 ; @@ -62,7 +62,7 @@ applicable agreement for further details. +-------------------+---------------------+ ; Option ; Setting ; +-------------------+---------------------+ -; Start date & time ; 03/02/2014 18:53:45 ; +; Start date & time ; 03/03/2014 16:11:57 ; ; Main task ; Compilation ; ; Revision Name ; de0_nano_system ; +-------------------+---------------------+ @@ -73,7 +73,7 @@ applicable agreement for further details. +-------------------------------------+----------------------------------------------------------+---------------+---------------------------------+------------+ ; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; +-------------------------------------+----------------------------------------------------------+---------------+---------------------------------+------------+ -; COMPILER_SIGNATURE_ID ; 116530612622.139381162503784 ; -- ; -- ; -- ; +; COMPILER_SIGNATURE_ID ; 116530612622.139388831704860 ; -- ; -- ; -- ; ; IP_TOOL_ENV ; qsys ; -- ; altera_avalon_sc_fifo ; -- ; ; IP_TOOL_ENV ; qsys ; -- ; altera_merlin_burst_adapter ; -- ; ; IP_TOOL_ENV ; qsys ; -- ; altera_merlin_master_agent ; -- ; @@ -191,7 +191,7 @@ applicable agreement for further details. ; POWER_BOARD_THERMAL_MODEL ; None (CONSERVATIVE) ; -- ; -- ; -- ; ; POWER_PRESET_COOLING_SOLUTION ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; -- ; -- ; -- ; ; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; -; SLD_INFO ; QSYS_NAME system HAS_SOPCINFO 1 GENERATION_ID 1393806947 ; -- ; system ; -- ; +; SLD_INFO ; QSYS_NAME system HAS_SOPCINFO 1 GENERATION_ID 1393886764 ; -- ; system ; -- ; ; SOPCINFO_FILE ; system/synthesis/../../system.sopcinfo ; -- ; -- ; -- ; ; SYNTHESIS_ONLY_QIP ; On ; -- ; -- ; -- ; +-------------------------------------+----------------------------------------------------------+---------------+---------------------------------+------------+ @@ -202,11 +202,11 @@ applicable agreement for further details. +---------------------------+--------------+-------------------------+---------------------+------------------------------------+ ; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; +---------------------------+--------------+-------------------------+---------------------+------------------------------------+ -; Analysis & Synthesis ; 00:00:21 ; 1.0 ; 644 MB ; 00:00:20 ; -; Fitter ; 00:00:37 ; 1.6 ; 1138 MB ; 00:00:46 ; -; Assembler ; 00:00:03 ; 1.0 ; 460 MB ; 00:00:02 ; -; TimeQuest Timing Analyzer ; 00:00:06 ; 2.3 ; 563 MB ; 00:00:07 ; -; Total ; 00:01:07 ; -- ; -- ; 00:01:15 ; +; Analysis & Synthesis ; 00:00:21 ; 1.0 ; 644 MB ; 00:00:21 ; +; Fitter ; 00:00:40 ; 2.3 ; 1135 MB ; 00:00:50 ; +; Assembler ; 00:00:02 ; 1.0 ; 456 MB ; 00:00:02 ; +; TimeQuest Timing Analyzer ; 00:00:06 ; 1.0 ; 569 MB ; 00:00:06 ; +; Total ; 00:01:09 ; -- ; -- ; 00:01:19 ; +---------------------------+--------------+-------------------------+---------------------+------------------------------------+ diff --git a/MCandWifiTestDE0/output_files/de0_nano_system.jdi b/MCandWifiTestDE0/output_files/de0_nano_system.jdi index ed7bcc5d..466d245f 100644 --- a/MCandWifiTestDE0/output_files/de0_nano_system.jdi +++ b/MCandWifiTestDE0/output_files/de0_nano_system.jdi @@ -1,9 +1,9 @@ - + - + @@ -144,7 +144,7 @@ - + diff --git a/MCandWifiTestDE0/output_files/de0_nano_system.map.rpt b/MCandWifiTestDE0/output_files/de0_nano_system.map.rpt index 4a02c2f3..ec9b8a66 100644 --- a/MCandWifiTestDE0/output_files/de0_nano_system.map.rpt +++ b/MCandWifiTestDE0/output_files/de0_nano_system.map.rpt @@ -1,5 +1,5 @@ Analysis & Synthesis report for de0_nano_system -Sun Mar 02 18:54:07 2014 +Mon Mar 03 16:12:20 2014 Quartus II 64-Bit Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Full Version @@ -222,7 +222,7 @@ applicable agreement for further details. +----------------------------------------------------------------------------------------+ ; Analysis & Synthesis Summary ; +------------------------------------+---------------------------------------------------+ -; Analysis & Synthesis Status ; Successful - Sun Mar 02 18:54:07 2014 ; +; Analysis & Synthesis Status ; Successful - Mon Mar 03 16:12:20 2014 ; ; Quartus II 64-Bit Version ; 12.1 Build 243 01/31/2013 SP 1.33 SJ Full Version ; ; Revision Name ; de0_nano_system ; ; Top-level Entity Name ; de0_nano_system ; @@ -476,9 +476,9 @@ applicable agreement for further details. ; ; ; ; Total combinational functions ; 4100 ; ; Logic element usage by number of LUT inputs ; ; -; -- 4 input functions ; 1981 ; -; -- 3 input functions ; 1346 ; -; -- <=2 input functions ; 773 ; +; -- 4 input functions ; 1980 ; +; -- 3 input functions ; 1345 ; +; -- <=2 input functions ; 775 ; ; ; ; ; Logic elements by mode ; ; ; -- normal mode ; 3717 ; @@ -495,7 +495,7 @@ applicable agreement for further details. ; -- PLLs ; 1 ; ; ; ; ; Maximum fan-out ; 3081 ; -; Total fan-out ; 29791 ; +; Total fan-out ; 29788 ; ; Average fan-out ; 3.87 ; +---------------------------------------------+--------+ @@ -510,11 +510,11 @@ applicable agreement for further details. ; |pll_sys:inst_pll_sys| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|pll_sys:inst_pll_sys ; ; ; |altpll:altpll_component| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|pll_sys:inst_pll_sys|altpll:altpll_component ; ; ; |pll_sys_altpll:auto_generated| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|pll_sys:inst_pll_sys|altpll:altpll_component|pll_sys_altpll:auto_generated ; ; -; |sld_hub:auto_hub| ; 156 (1) ; 97 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|sld_hub:auto_hub ; ; -; |sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst| ; 155 (115) ; 97 (69) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst ; ; +; |sld_hub:auto_hub| ; 159 (1) ; 97 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|sld_hub:auto_hub ; ; +; |sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst| ; 158 (118) ; 97 (69) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst ; ; ; |sld_rom_sr:hub_info_reg| ; 23 (23) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg ; ; ; |sld_shadow_jsm:shadow_jsm| ; 17 (17) ; 19 (19) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm ; ; -; |system:inst_cpu| ; 3921 (0) ; 2877 (0) ; 119808 ; 4 ; 0 ; 2 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu ; ; +; |system:inst_cpu| ; 3918 (0) ; 2877 (0) ; 119808 ; 4 ; 0 ; 2 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu ; ; ; |altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 7 (7) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo ; ; ; |altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 7 (7) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|altera_avalon_sc_fifo:jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo ; ; ; |altera_avalon_sc_fifo:pio_ir_emitter_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 6 (6) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|altera_avalon_sc_fifo:pio_ir_emitter_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; ; @@ -522,7 +522,7 @@ applicable agreement for further details. ; |altera_avalon_sc_fifo:pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 6 (6) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|altera_avalon_sc_fifo:pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; ; ; |altera_avalon_sc_fifo:pio_sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 4 (4) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|altera_avalon_sc_fifo:pio_sw_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; ; ; |altera_avalon_sc_fifo:rs232_wifi_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 4 (4) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|altera_avalon_sc_fifo:rs232_wifi_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo ; ; -; |altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 60 (60) ; 56 (56) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; ; +; |altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 61 (61) ; 56 (56) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; ; ; |altera_avalon_sc_fifo:sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 6 (6) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|altera_avalon_sc_fifo:sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; ; ; |altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 4 (4) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo ; ; ; |altera_avalon_sc_fifo:uart_mc_s1_translator_avalon_universal_slave_0_agent_rsp_fifo| ; 4 (4) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|altera_avalon_sc_fifo:uart_mc_s1_translator_avalon_universal_slave_0_agent_rsp_fifo ; ; @@ -530,7 +530,7 @@ applicable agreement for further details. ; |altera_merlin_slave_agent:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent| ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_agent:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent ; ; ; |altera_merlin_slave_agent:pio_key_left_s1_translator_avalon_universal_slave_0_agent| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_agent:pio_key_left_s1_translator_avalon_universal_slave_0_agent ; ; ; |altera_merlin_slave_agent:pio_sw_s1_translator_avalon_universal_slave_0_agent| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_agent:pio_sw_s1_translator_avalon_universal_slave_0_agent ; ; -; |altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent| ; 19 (11) ; 3 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent ; ; +; |altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent| ; 18 (10) ; 3 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent ; ; ; |altera_merlin_burst_uncompressor:uncompressor| ; 8 (8) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor ; ; ; |altera_merlin_slave_agent:sys_clk_timer_s1_translator_avalon_universal_slave_0_agent| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_agent:sys_clk_timer_s1_translator_avalon_universal_slave_0_agent ; ; ; |altera_merlin_slave_agent:sysid_control_slave_translator_avalon_universal_slave_0_agent| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_agent:sysid_control_slave_translator_avalon_universal_slave_0_agent ; ; @@ -545,7 +545,7 @@ applicable agreement for further details. ; |altera_merlin_slave_translator:sysid_control_slave_translator| ; 8 (8) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_translator:sysid_control_slave_translator ; ; ; |altera_merlin_slave_translator:uart_mc_s1_translator| ; 7 (7) ; 14 (14) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_translator:uart_mc_s1_translator ; ; ; |altera_merlin_slave_translator:uart_wifi_s1_translator| ; 6 (6) ; 20 (20) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|altera_merlin_slave_translator:uart_wifi_s1_translator ; ; -; |altera_merlin_traffic_limiter:limiter_001| ; 24 (24) ; 21 (21) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|altera_merlin_traffic_limiter:limiter_001 ; ; +; |altera_merlin_traffic_limiter:limiter_001| ; 25 (25) ; 21 (21) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|altera_merlin_traffic_limiter:limiter_001 ; ; ; |altera_merlin_traffic_limiter:limiter| ; 14 (14) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|altera_merlin_traffic_limiter:limiter ; ; ; |altera_merlin_width_adapter:width_adapter_001| ; 32 (32) ; 16 (16) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|altera_merlin_width_adapter:width_adapter_001 ; ; ; |altera_merlin_width_adapter:width_adapter| ; 44 (44) ; 44 (44) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|altera_merlin_width_adapter:width_adapter ; ; @@ -660,7 +660,7 @@ applicable agreement for further details. ; |system_rsp_xbar_demux:rsp_xbar_demux_001| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_rsp_xbar_demux:rsp_xbar_demux_001 ; ; ; |system_rsp_xbar_demux:rsp_xbar_demux| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_rsp_xbar_demux:rsp_xbar_demux ; ; ; |system_rsp_xbar_mux:rsp_xbar_mux| ; 34 (34) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_rsp_xbar_mux:rsp_xbar_mux ; ; -; |system_rsp_xbar_mux_001:rsp_xbar_mux_001| ; 129 (129) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_rsp_xbar_mux_001:rsp_xbar_mux_001 ; ; +; |system_rsp_xbar_mux_001:rsp_xbar_mux_001| ; 125 (125) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_rsp_xbar_mux_001:rsp_xbar_mux_001 ; ; ; |system_sdram:sdram| ; 275 (220) ; 245 (157) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_sdram:sdram ; ; ; |system_sdram_input_efifo_module:the_system_sdram_input_efifo_module| ; 55 (55) ; 88 (88) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module ; ; ; |system_sys_clk_timer:sys_clk_timer| ; 132 (132) ; 120 (120) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |de0_nano_system|system:inst_cpu|system_sys_clk_timer:sys_clk_timer ; ; @@ -957,7 +957,7 @@ Encoding Type: One-Hot ; system:inst_cpu|altera_merlin_slave_translator:pio_led_s1_translator|av_chipselect_pre ; Stuck at GND due to stuck port data_in ; ; system:inst_cpu|altera_merlin_slave_translator:uart_wifi_s1_translator|av_chipselect_pre ; Stuck at GND due to stuck port data_in ; ; system:inst_cpu|altera_merlin_slave_translator:sys_clk_timer_s1_translator|av_chipselect_pre ; Stuck at GND due to stuck port data_in ; -; system:inst_cpu|altera_merlin_slave_translator:sysid_control_slave_translator|av_readdata_pre[2..4,7,8,12,13,18,19,21..23,26,27,29,31] ; Stuck at GND due to stuck port data_in ; +; system:inst_cpu|altera_merlin_slave_translator:sysid_control_slave_translator|av_readdata_pre[0,1,4,6..8,11..15,17,19,21..23,26,27,29,31] ; Stuck at GND due to stuck port data_in ; ; system:inst_cpu|altera_merlin_slave_translator:cpu_jtag_debug_module_translator|av_chipselect_pre ; Stuck at GND due to stuck port data_in ; ; system:inst_cpu|system_uart_mc:uart_mc|system_uart_mc_regs:the_system_uart_mc_regs|readdata[10..15] ; Stuck at GND due to stuck port data_in ; ; system:inst_cpu|system_pio_sw:pio_sw|readdata[4..31] ; Stuck at GND due to stuck port data_in ; @@ -1127,7 +1127,7 @@ Encoding Type: One-Hot ; system:inst_cpu|altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][69] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][86] ; ; system:inst_cpu|altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][84] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][86] ; ; system:inst_cpu|altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][68] ; Merged with system:inst_cpu|altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][86] ; -; system:inst_cpu|altera_merlin_slave_translator:sysid_control_slave_translator|av_readdata_pre[0,1,5,6,9..11,14..17,20,24,25,28] ; Merged with system:inst_cpu|altera_merlin_slave_translator:sysid_control_slave_translator|av_readdata_pre[30] ; +; system:inst_cpu|altera_merlin_slave_translator:sysid_control_slave_translator|av_readdata_pre[2,3,5,9,10,16,18,20,24,25,28] ; Merged with system:inst_cpu|altera_merlin_slave_translator:sysid_control_slave_translator|av_readdata_pre[30] ; ; system:inst_cpu|system_rs232_wifi:rs232_wifi|readdata[11..14,24..31] ; Merged with system:inst_cpu|system_rs232_wifi:rs232_wifi|readdata[10] ; ; system:inst_cpu|system_uart_mc:uart_mc|system_uart_mc_rx:the_system_uart_mc_rx|delayed_unxsync_rxdxx2 ; Merged with system:inst_cpu|system_uart_mc:uart_mc|system_uart_mc_rx:the_system_uart_mc_rx|delayed_unxsync_rxdxx1 ; ; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_rx:the_system_uart_wifi_rx|delayed_unxsync_rxdxx2 ; Merged with system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_rx:the_system_uart_wifi_rx|delayed_unxsync_rxdxx1 ; @@ -2212,7 +2212,7 @@ Encoding Type: One-Hot ; system:inst_cpu|system_uart_mc:uart_mc|system_uart_mc_tx:the_system_uart_mc_tx|txd ; 1 ; ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1] ; 1 ; ; system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux_001|altera_merlin_arbitrator:arb|top_priority_reg[0] ; 2 ; -; system:inst_cpu|system_cpu:cpu|M_pipe_flush ; 52 ; +; system:inst_cpu|system_cpu:cpu|M_pipe_flush ; 53 ; ; system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux|altera_merlin_arbitrator:arb|top_priority_reg[0] ; 2 ; ; system:inst_cpu|system_cpu:cpu|hbreak_enabled ; 10 ; ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|t_dav ; 3 ; @@ -6142,7 +6142,7 @@ Note: In order to hide this table in the UI and the text report file, please set +----------------+--------------+ ; Partition Name ; Elapsed Time ; +----------------+--------------+ -; Top ; 00:00:11 ; +; Top ; 00:00:12 ; +----------------+--------------+ @@ -6152,7 +6152,7 @@ Note: In order to hide this table in the UI and the text report file, please set Info: ******************************************************************* Info: Running Quartus II 64-Bit Analysis & Synthesis Info: Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Full Version - Info: Processing started: Sun Mar 02 18:53:44 2014 + Info: Processing started: Mon Mar 03 16:11:57 2014 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off de0_nano_system -c de0_nano_system Info (11104): Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead. Info (12021): Found 2 design units, including 1 entities, in source file de0_nano_system.vhd @@ -7037,17 +7037,17 @@ Info (16010): Generating hard_block partition "hard_block:auto_generated_inst" Info (16011): Adding 1 node(s), including 0 DDIO, 1 PLL, 0 transceiver and 0 LCELL Warning (21074): Design contains 1 input pin(s) that do not drive logic Warning (15610): No output dependent on input pin "KEY[0]" -Info (21057): Implemented 5737 device resources after synthesis - the final resource count might be different +Info (21057): Implemented 5738 device resources after synthesis - the final resource count might be different Info (21058): Implemented 10 input pins Info (21059): Implemented 32 output pins Info (21060): Implemented 84 bidirectional pins - Info (21061): Implemented 5342 logic cells + Info (21061): Implemented 5343 logic cells Info (21064): Implemented 263 RAM segments Info (21065): Implemented 1 PLLs Info (21062): Implemented 4 DSP elements Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 130 warnings Info: Peak virtual memory: 644 megabytes - Info: Processing ended: Sun Mar 02 18:54:07 2014 + Info: Processing ended: Mon Mar 03 16:12:20 2014 Info: Elapsed time: 00:00:23 Info: Total CPU time (on all processors): 00:00:22 diff --git a/MCandWifiTestDE0/output_files/de0_nano_system.map.summary b/MCandWifiTestDE0/output_files/de0_nano_system.map.summary index 63404476..ca21ea7d 100644 --- a/MCandWifiTestDE0/output_files/de0_nano_system.map.summary +++ b/MCandWifiTestDE0/output_files/de0_nano_system.map.summary @@ -1,4 +1,4 @@ -Analysis & Synthesis Status : Successful - Sun Mar 02 18:54:07 2014 +Analysis & Synthesis Status : Successful - Mon Mar 03 16:12:20 2014 Quartus II 64-Bit Version : 12.1 Build 243 01/31/2013 SP 1.33 SJ Full Version Revision Name : de0_nano_system Top-level Entity Name : de0_nano_system diff --git a/MCandWifiTestDE0/output_files/de0_nano_system.sof b/MCandWifiTestDE0/output_files/de0_nano_system.sof index 45e5cf6b..a8a4d306 100644 Binary files a/MCandWifiTestDE0/output_files/de0_nano_system.sof and b/MCandWifiTestDE0/output_files/de0_nano_system.sof differ diff --git a/MCandWifiTestDE0/output_files/de0_nano_system.sta.rpt b/MCandWifiTestDE0/output_files/de0_nano_system.sta.rpt index 18f0a1c2..50194d4a 100644 --- a/MCandWifiTestDE0/output_files/de0_nano_system.sta.rpt +++ b/MCandWifiTestDE0/output_files/de0_nano_system.sta.rpt @@ -1,5 +1,5 @@ TimeQuest Timing Analyzer report for de0_nano_system -Sun Mar 02 18:54:57 2014 +Mon Mar 03 16:13:13 2014 Quartus II 64-Bit Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Full Version @@ -167,12 +167,12 @@ applicable agreement for further details. ; Number detected on machine ; 8 ; ; Maximum allowed ; 4 ; ; ; ; -; Average used ; 2.33 ; +; Average used ; 1.00 ; ; Maximum used ; 4 ; ; ; ; ; Usage by Processor ; % Time Used ; ; 1 processor ; 100.0% ; -; 2-4 processors ; 16.7% ; +; 2-4 processors ; < 0.1% ; ; 5-8 processors ; 0.0% ; +----------------------------+-------------+ @@ -182,9 +182,9 @@ applicable agreement for further details. +---------------------------------------------------------+--------+--------------------------+ ; SDC File Path ; Status ; Read at ; +---------------------------------------------------------+--------+--------------------------+ -; de0_nano_system.sdc ; OK ; Sun Mar 02 18:54:52 2014 ; -; system/synthesis/submodules/altera_reset_controller.sdc ; OK ; Sun Mar 02 18:54:52 2014 ; -; system/synthesis/submodules/system_cpu.sdc ; OK ; Sun Mar 02 18:54:52 2014 ; +; de0_nano_system.sdc ; OK ; Mon Mar 03 16:13:09 2014 ; +; system/synthesis/submodules/altera_reset_controller.sdc ; OK ; Mon Mar 03 16:13:09 2014 ; +; system/synthesis/submodules/system_cpu.sdc ; OK ; Mon Mar 03 16:13:09 2014 ; +---------------------------------------------------------+--------+--------------------------+ @@ -206,7 +206,7 @@ applicable agreement for further details. +------------+-----------------+----------------------------------------------------------+------+ ; Fmax ; Restricted Fmax ; Clock Name ; Note ; +------------+-----------------+----------------------------------------------------------+------+ -; 124.86 MHz ; 124.86 MHz ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; +; 126.07 MHz ; 126.07 MHz ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; ; 382.85 MHz ; 382.85 MHz ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; ; +------------+-----------------+----------------------------------------------------------+------+ This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. @@ -217,7 +217,7 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +----------------------------------------------------------+--------+---------------+ ; Clock ; Slack ; End Point TNS ; +----------------------------------------------------------+--------+---------------+ -; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 1.944 ; 0.000 ; +; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 2.068 ; 0.000 ; ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 97.388 ; 0.000 ; +----------------------------------------------------------+--------+---------------+ @@ -227,7 +227,7 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +----------------------------------------------------------+-------+---------------+ ; Clock ; Slack ; End Point TNS ; +----------------------------------------------------------+-------+---------------+ -; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.246 ; 0.000 ; +; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.230 ; 0.000 ; ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.361 ; 0.000 ; +----------------------------------------------------------+-------+---------------+ @@ -237,7 +237,7 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +----------------------------------------------------------+-------+---------------+ ; Clock ; Slack ; End Point TNS ; +----------------------------------------------------------+-------+---------------+ -; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 2.156 ; 0.000 ; +; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 1.948 ; 0.000 ; +----------------------------------------------------------+-------+---------------+ @@ -246,7 +246,7 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +----------------------------------------------------------+-------+---------------+ ; Clock ; Slack ; End Point TNS ; +----------------------------------------------------------+-------+---------------+ -; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 2.023 ; 0.000 ; +; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 2.524 ; 0.000 ; +----------------------------------------------------------+-------+---------------+ @@ -255,9 +255,9 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +----------------------------------------------------------+--------+---------------+ ; Clock ; Slack ; End Point TNS ; +----------------------------------------------------------+--------+---------------+ -; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 4.693 ; 0.000 ; +; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 4.694 ; 0.000 ; ; CLOCK_50 ; 9.835 ; 0.000 ; -; altera_reserved_tck ; 49.624 ; 0.000 ; +; altera_reserved_tck ; 49.640 ; 0.000 ; ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 49.747 ; 0.000 ; +----------------------------------------------------------+--------+---------------+ @@ -267,106 +267,106 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +-------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ -; 1.944 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[20] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.070 ; 2.981 ; -; 1.945 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.070 ; 2.980 ; -; 1.948 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[24] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.070 ; 2.977 ; -; 1.991 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.100 ; 7.904 ; -; 1.991 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.100 ; 7.904 ; -; 1.994 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[5] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.100 ; 7.901 ; -; 1.994 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[5] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.100 ; 7.901 ; -; 2.000 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[3] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.100 ; 7.895 ; -; 2.000 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[3] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.100 ; 7.895 ; -; 2.022 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.095 ; 7.878 ; -; 2.022 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.095 ; 7.878 ; -; 2.022 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.095 ; 7.878 ; -; 2.025 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_cpu:cpu|d_writedata[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.088 ; 7.882 ; -; 2.025 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_cpu:cpu|d_writedata[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.088 ; 7.882 ; -; 2.025 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_cpu:cpu|d_writedata[31] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.088 ; 7.882 ; -; 2.025 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_cpu:cpu|d_writedata[28] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.088 ; 7.882 ; -; 2.025 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_cpu:cpu|d_writedata[27] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.088 ; 7.882 ; -; 2.025 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_cpu:cpu|d_writedata[25] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.088 ; 7.882 ; -; 2.025 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_cpu:cpu|d_writedata[22] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.088 ; 7.882 ; -; 2.025 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_cpu:cpu|d_writedata[20] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.088 ; 7.882 ; -; 2.025 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_cpu:cpu|d_writedata[16] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.088 ; 7.882 ; -; 2.025 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[5] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.095 ; 7.875 ; -; 2.025 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[5] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.095 ; 7.875 ; -; 2.025 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[5] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.095 ; 7.875 ; -; 2.031 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[3] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.095 ; 7.869 ; -; 2.031 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[3] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.095 ; 7.869 ; -; 2.031 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[3] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.095 ; 7.869 ; -; 2.032 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.087 ; 7.876 ; -; 2.032 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[22] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.087 ; 7.876 ; -; 2.032 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[23] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.087 ; 7.876 ; -; 2.032 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[24] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.087 ; 7.876 ; -; 2.032 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[25] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.087 ; 7.876 ; -; 2.035 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[5] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.087 ; 7.873 ; -; 2.035 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[5] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[22] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.087 ; 7.873 ; -; 2.035 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[5] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[23] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.087 ; 7.873 ; -; 2.035 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[5] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[24] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.087 ; 7.873 ; -; 2.035 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[5] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[25] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.087 ; 7.873 ; -; 2.038 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.087 ; 7.870 ; -; 2.038 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.087 ; 7.870 ; -; 2.038 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.087 ; 7.870 ; -; 2.038 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.087 ; 7.870 ; -; 2.041 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[3] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.087 ; 7.867 ; -; 2.041 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[3] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[22] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.087 ; 7.867 ; -; 2.041 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[3] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[23] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.087 ; 7.867 ; -; 2.041 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[3] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[24] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.087 ; 7.867 ; -; 2.041 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[3] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[25] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.087 ; 7.867 ; -; 2.041 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[5] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.087 ; 7.867 ; -; 2.041 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[5] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.087 ; 7.867 ; -; 2.041 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[5] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.087 ; 7.867 ; -; 2.041 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[5] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.087 ; 7.867 ; -; 2.047 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[3] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.087 ; 7.861 ; -; 2.047 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[3] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.087 ; 7.861 ; -; 2.047 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[3] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.087 ; 7.861 ; -; 2.047 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[3] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.087 ; 7.861 ; -; 2.049 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[26] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.095 ; 7.851 ; -; 2.049 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[40] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.095 ; 7.851 ; -; 2.049 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[27] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.095 ; 7.851 ; -; 2.049 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[28] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.095 ; 7.851 ; -; 2.049 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[29] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.095 ; 7.851 ; -; 2.049 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[35] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.095 ; 7.851 ; -; 2.049 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[32] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.095 ; 7.851 ; -; 2.049 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[33] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.095 ; 7.851 ; -; 2.052 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[5] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[26] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.095 ; 7.848 ; -; 2.052 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[5] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[40] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.095 ; 7.848 ; -; 2.052 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[5] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[27] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.095 ; 7.848 ; -; 2.052 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[5] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[28] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.095 ; 7.848 ; -; 2.052 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[5] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[29] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.095 ; 7.848 ; -; 2.052 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[5] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[35] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.095 ; 7.848 ; -; 2.052 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[5] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[32] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.095 ; 7.848 ; -; 2.052 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[5] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[33] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.095 ; 7.848 ; -; 2.058 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[3] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[26] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.095 ; 7.842 ; -; 2.058 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[3] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[40] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.095 ; 7.842 ; -; 2.058 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[3] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[27] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.095 ; 7.842 ; -; 2.058 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[3] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[28] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.095 ; 7.842 ; -; 2.058 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[3] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[29] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.095 ; 7.842 ; -; 2.058 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[3] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[35] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.095 ; 7.842 ; -; 2.058 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[3] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[32] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.095 ; 7.842 ; -; 2.058 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[3] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[33] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.095 ; 7.842 ; -; 2.068 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[36] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.079 ; 7.848 ; -; 2.068 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[37] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.079 ; 7.848 ; -; 2.068 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[34] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.079 ; 7.848 ; -; 2.068 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[39] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.079 ; 7.848 ; -; 2.068 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[38] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.079 ; 7.848 ; -; 2.068 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.079 ; 7.848 ; -; 2.068 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[20] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.079 ; 7.848 ; -; 2.071 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.070 ; 2.854 ; -; 2.071 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[5] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[36] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.079 ; 7.845 ; -; 2.071 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[5] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[37] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.079 ; 7.845 ; -; 2.071 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[5] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[34] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.079 ; 7.845 ; -; 2.071 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[5] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[39] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.079 ; 7.845 ; -; 2.071 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[5] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[38] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.079 ; 7.845 ; -; 2.071 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[5] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.079 ; 7.845 ; -; 2.071 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[5] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[20] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.079 ; 7.845 ; -; 2.072 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[12] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.100 ; 7.823 ; -; 2.072 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[12] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.100 ; 7.823 ; -; 2.076 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.070 ; 2.849 ; -; 2.077 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[3] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[36] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.079 ; 7.839 ; -; 2.077 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[3] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[37] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.079 ; 7.839 ; -; 2.077 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[3] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[34] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.079 ; 7.839 ; -; 2.077 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[3] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[39] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.079 ; 7.839 ; +; 2.068 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_cpu:cpu|d_address_offset_field[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.071 ; 7.856 ; +; 2.068 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_cpu:cpu|d_address_offset_field[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.071 ; 7.856 ; +; 2.068 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_cpu:cpu|d_address_offset_field[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.071 ; 7.856 ; +; 2.088 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_cpu:cpu|d_writedata[25] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.059 ; 7.848 ; +; 2.088 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_cpu:cpu|d_writedata[22] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.059 ; 7.848 ; +; 2.088 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_cpu:cpu|d_writedata[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.059 ; 7.848 ; +; 2.088 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_cpu:cpu|d_writedata[20] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.059 ; 7.848 ; +; 2.088 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_cpu:cpu|d_writedata[18] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.059 ; 7.848 ; +; 2.099 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_cpu:cpu|d_writedata[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.058 ; 7.838 ; +; 2.099 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_cpu:cpu|d_writedata[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.058 ; 7.838 ; +; 2.099 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_cpu:cpu|d_writedata[30] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.058 ; 7.838 ; +; 2.099 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_cpu:cpu|d_writedata[29] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.058 ; 7.838 ; +; 2.099 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_cpu:cpu|d_writedata[27] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.058 ; 7.838 ; +; 2.099 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_cpu:cpu|d_writedata[26] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.058 ; 7.838 ; +; 2.099 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_cpu:cpu|d_writedata[24] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.058 ; 7.838 ; +; 2.099 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_cpu:cpu|d_writedata[23] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.058 ; 7.838 ; +; 2.099 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_cpu:cpu|d_writedata[17] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.058 ; 7.838 ; +; 2.109 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[8] ; system:inst_cpu|system_cpu:cpu|d_address_offset_field[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.071 ; 7.815 ; +; 2.109 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[8] ; system:inst_cpu|system_cpu:cpu|d_address_offset_field[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.071 ; 7.815 ; +; 2.109 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[8] ; system:inst_cpu|system_cpu:cpu|d_address_offset_field[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.071 ; 7.815 ; +; 2.115 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[7] ; system:inst_cpu|system_cpu:cpu|d_address_offset_field[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.071 ; 7.809 ; +; 2.115 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[7] ; system:inst_cpu|system_cpu:cpu|d_address_offset_field[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.071 ; 7.809 ; +; 2.115 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[7] ; system:inst_cpu|system_cpu:cpu|d_address_offset_field[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.071 ; 7.809 ; +; 2.129 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[8] ; system:inst_cpu|system_cpu:cpu|d_writedata[25] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.059 ; 7.807 ; +; 2.129 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[8] ; system:inst_cpu|system_cpu:cpu|d_writedata[22] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.059 ; 7.807 ; +; 2.129 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[8] ; system:inst_cpu|system_cpu:cpu|d_writedata[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.059 ; 7.807 ; +; 2.129 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[8] ; system:inst_cpu|system_cpu:cpu|d_writedata[20] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.059 ; 7.807 ; +; 2.129 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[8] ; system:inst_cpu|system_cpu:cpu|d_writedata[18] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.059 ; 7.807 ; +; 2.135 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[7] ; system:inst_cpu|system_cpu:cpu|d_writedata[25] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.059 ; 7.801 ; +; 2.135 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[7] ; system:inst_cpu|system_cpu:cpu|d_writedata[22] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.059 ; 7.801 ; +; 2.135 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[7] ; system:inst_cpu|system_cpu:cpu|d_writedata[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.059 ; 7.801 ; +; 2.135 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[7] ; system:inst_cpu|system_cpu:cpu|d_writedata[20] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.059 ; 7.801 ; +; 2.135 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[7] ; system:inst_cpu|system_cpu:cpu|d_writedata[18] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.059 ; 7.801 ; +; 2.140 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[8] ; system:inst_cpu|system_cpu:cpu|d_writedata[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.058 ; 7.797 ; +; 2.140 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[8] ; system:inst_cpu|system_cpu:cpu|d_writedata[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.058 ; 7.797 ; +; 2.140 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[8] ; system:inst_cpu|system_cpu:cpu|d_writedata[30] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.058 ; 7.797 ; +; 2.140 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[8] ; system:inst_cpu|system_cpu:cpu|d_writedata[29] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.058 ; 7.797 ; +; 2.140 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[8] ; system:inst_cpu|system_cpu:cpu|d_writedata[27] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.058 ; 7.797 ; +; 2.140 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[8] ; system:inst_cpu|system_cpu:cpu|d_writedata[26] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.058 ; 7.797 ; +; 2.140 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[8] ; system:inst_cpu|system_cpu:cpu|d_writedata[24] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.058 ; 7.797 ; +; 2.140 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[8] ; system:inst_cpu|system_cpu:cpu|d_writedata[23] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.058 ; 7.797 ; +; 2.140 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[8] ; system:inst_cpu|system_cpu:cpu|d_writedata[17] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.058 ; 7.797 ; +; 2.146 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[7] ; system:inst_cpu|system_cpu:cpu|d_writedata[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.058 ; 7.791 ; +; 2.146 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[7] ; system:inst_cpu|system_cpu:cpu|d_writedata[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.058 ; 7.791 ; +; 2.146 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[7] ; system:inst_cpu|system_cpu:cpu|d_writedata[30] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.058 ; 7.791 ; +; 2.146 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[7] ; system:inst_cpu|system_cpu:cpu|d_writedata[29] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.058 ; 7.791 ; +; 2.146 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[7] ; system:inst_cpu|system_cpu:cpu|d_writedata[27] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.058 ; 7.791 ; +; 2.146 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[7] ; system:inst_cpu|system_cpu:cpu|d_writedata[26] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.058 ; 7.791 ; +; 2.146 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[7] ; system:inst_cpu|system_cpu:cpu|d_writedata[24] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.058 ; 7.791 ; +; 2.146 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[7] ; system:inst_cpu|system_cpu:cpu|d_writedata[23] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.058 ; 7.791 ; +; 2.146 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[7] ; system:inst_cpu|system_cpu:cpu|d_writedata[17] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.058 ; 7.791 ; +; 2.156 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[30] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[6] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.096 ; 2.743 ; +; 2.209 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[30] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.096 ; 2.690 ; +; 2.213 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[8] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[35] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.047 ; 7.735 ; +; 2.213 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[8] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[34] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.047 ; 7.735 ; +; 2.213 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[8] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[33] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.047 ; 7.735 ; +; 2.213 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[8] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[32] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.047 ; 7.735 ; +; 2.213 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[8] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[37] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.047 ; 7.735 ; +; 2.213 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[8] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[36] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.047 ; 7.735 ; +; 2.213 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[8] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[31] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.047 ; 7.735 ; +; 2.213 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[8] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[30] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.047 ; 7.735 ; +; 2.217 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[35] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.047 ; 7.731 ; +; 2.217 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[34] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.047 ; 7.731 ; +; 2.217 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[33] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.047 ; 7.731 ; +; 2.217 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[32] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.047 ; 7.731 ; +; 2.217 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[37] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.047 ; 7.731 ; +; 2.217 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[36] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.047 ; 7.731 ; +; 2.217 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[31] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.047 ; 7.731 ; +; 2.217 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[30] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.047 ; 7.731 ; +; 2.219 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[7] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[35] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.047 ; 7.729 ; +; 2.219 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[7] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[34] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.047 ; 7.729 ; +; 2.219 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[7] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[33] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.047 ; 7.729 ; +; 2.219 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[7] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[32] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.047 ; 7.729 ; +; 2.219 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[7] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[37] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.047 ; 7.729 ; +; 2.219 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[7] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[36] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.047 ; 7.729 ; +; 2.219 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[7] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[31] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.047 ; 7.729 ; +; 2.219 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[7] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[30] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.047 ; 7.729 ; +; 2.230 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_cpu:cpu|d_writedata[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.057 ; 7.708 ; +; 2.230 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_cpu:cpu|d_writedata[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.057 ; 7.708 ; +; 2.230 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_cpu:cpu|d_writedata[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.057 ; 7.708 ; +; 2.230 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_cpu:cpu|d_writedata[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.057 ; 7.708 ; +; 2.230 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_cpu:cpu|d_writedata[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.057 ; 7.708 ; +; 2.230 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_cpu:cpu|d_writedata[14] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.057 ; 7.708 ; +; 2.230 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_cpu:cpu|d_writedata[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.057 ; 7.708 ; +; 2.230 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_cpu:cpu|d_writedata[16] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.057 ; 7.708 ; +; 2.243 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.065 ; 2.687 ; +; 2.255 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[31] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.065 ; 2.675 ; +; 2.267 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[27] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.065 ; 2.663 ; +; 2.271 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[8] ; system:inst_cpu|system_cpu:cpu|d_writedata[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.057 ; 7.667 ; +; 2.271 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[8] ; system:inst_cpu|system_cpu:cpu|d_writedata[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.057 ; 7.667 ; +; 2.271 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[8] ; system:inst_cpu|system_cpu:cpu|d_writedata[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.057 ; 7.667 ; +; 2.271 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[8] ; system:inst_cpu|system_cpu:cpu|d_writedata[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.057 ; 7.667 ; +; 2.271 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[8] ; system:inst_cpu|system_cpu:cpu|d_writedata[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.057 ; 7.667 ; +; 2.271 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[8] ; system:inst_cpu|system_cpu:cpu|d_writedata[14] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.057 ; 7.667 ; +; 2.271 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[8] ; system:inst_cpu|system_cpu:cpu|d_writedata[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.057 ; 7.667 ; +; 2.271 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[8] ; system:inst_cpu|system_cpu:cpu|d_writedata[16] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.057 ; 7.667 ; +; 2.277 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[9] ; system:inst_cpu|system_cpu:cpu|d_address_offset_field[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.071 ; 7.647 ; +; 2.277 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[9] ; system:inst_cpu|system_cpu:cpu|d_address_offset_field[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.071 ; 7.647 ; +; 2.277 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[9] ; system:inst_cpu|system_cpu:cpu|d_address_offset_field[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.071 ; 7.647 ; +; 2.277 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[7] ; system:inst_cpu|system_cpu:cpu|d_writedata[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.057 ; 7.661 ; +-------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ @@ -483,106 +483,106 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ -; 0.246 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[10] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.388 ; 0.821 ; -; 0.254 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[5] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a0~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.389 ; 0.830 ; -; 0.294 ; system:inst_cpu|system_cpu:cpu|M_bht_ptr_unfiltered[0] ; system:inst_cpu|system_cpu:cpu|system_cpu_bht_module:system_cpu_bht|altsyncram:the_altsyncram|altsyncram_fhg1:auto_generated|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.382 ; 0.863 ; -; 0.297 ; system:inst_cpu|system_cpu:cpu|M_bht_ptr_unfiltered[3] ; system:inst_cpu|system_cpu:cpu|system_cpu_bht_module:system_cpu_bht|altsyncram:the_altsyncram|altsyncram_fhg1:auto_generated|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.382 ; 0.866 ; -; 0.299 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|data_to_uart[0] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.382 ; 0.868 ; -; 0.299 ; system:inst_cpu|system_cpu:cpu|M_bht_ptr_unfiltered[4] ; system:inst_cpu|system_cpu:cpu|system_cpu_bht_module:system_cpu_bht|altsyncram:the_altsyncram|altsyncram_fhg1:auto_generated|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.378 ; 0.864 ; -; 0.300 ; system:inst_cpu|system_cpu:cpu|ic_tag_wraddress[7] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.380 ; 0.867 ; -; 0.302 ; system:inst_cpu|system_cpu:cpu|ic_fill_valid_bits[2] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.381 ; 0.870 ; -; 0.303 ; system:inst_cpu|system_cpu:cpu|ic_tag_wraddress[5] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.380 ; 0.870 ; -; 0.303 ; system:inst_cpu|system_cpu:cpu|ic_fill_valid_bits[7] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.381 ; 0.871 ; -; 0.305 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[8] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.387 ; 0.879 ; -; 0.305 ; system:inst_cpu|system_cpu:cpu|A_dc_xfer_wr_data[3] ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_victim_module:system_cpu_dc_victim|altsyncram:the_altsyncram|altsyncram_r3d1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.384 ; 0.876 ; -; 0.306 ; system:inst_cpu|system_cpu:cpu|A_dc_wb_rd_addr_offset[2] ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_victim_module:system_cpu_dc_victim|altsyncram:the_altsyncram|altsyncram_r3d1:auto_generated|ram_block1a0~portb_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.380 ; 0.873 ; -; 0.306 ; system:inst_cpu|system_cpu:cpu|M_bht_ptr_unfiltered[5] ; system:inst_cpu|system_cpu:cpu|system_cpu_bht_module:system_cpu_bht|altsyncram:the_altsyncram|altsyncram_fhg1:auto_generated|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.382 ; 0.875 ; -; 0.307 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|data_in_shift_reg[2] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.382 ; 0.876 ; -; 0.309 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[3] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.381 ; 0.877 ; -; 0.309 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|data_in_shift_reg[1] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.382 ; 0.878 ; -; 0.310 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[6] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a0~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.388 ; 0.885 ; -; 0.312 ; system:inst_cpu|system_cpu:cpu|i_readdata_d1[16] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a9~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.381 ; 0.880 ; -; 0.312 ; system:inst_cpu|system_cpu:cpu|A_dc_wb_rd_addr_offset[1] ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_victim_module:system_cpu_dc_victim|altsyncram:the_altsyncram|altsyncram_r3d1:auto_generated|ram_block1a0~portb_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.380 ; 0.879 ; -; 0.313 ; system:inst_cpu|system_cpu:cpu|ic_fill_valid_bits[1] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.381 ; 0.881 ; -; 0.315 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|data_in_shift_reg[5] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.382 ; 0.884 ; -; 0.316 ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[2] ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.381 ; 0.884 ; -; 0.316 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[14] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.387 ; 0.890 ; -; 0.317 ; system:inst_cpu|system_cpu:cpu|ic_fill_valid_bits[4] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.381 ; 0.885 ; -; 0.318 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[20] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a0~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.388 ; 0.893 ; -; 0.318 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[0] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.379 ; 0.884 ; -; 0.318 ; system:inst_cpu|system_cpu:cpu|ic_fill_valid_bits[6] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.381 ; 0.886 ; -; 0.318 ; system:inst_cpu|system_cpu:cpu|ic_fill_tag[4] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.385 ; 0.890 ; -; 0.319 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|data_in_shift_reg[7] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.382 ; 0.888 ; -; 0.319 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|data_to_uart[5] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.382 ; 0.888 ; -; 0.320 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[16] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a0~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.388 ; 0.895 ; -; 0.320 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[17] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a0~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.388 ; 0.895 ; -; 0.320 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[2] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.379 ; 0.886 ; -; 0.320 ; system:inst_cpu|system_cpu:cpu|ic_fill_valid_bits[0] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.381 ; 0.888 ; -; 0.321 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[30] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.387 ; 0.895 ; -; 0.321 ; system:inst_cpu|system_cpu:cpu|ic_fill_dp_offset[1] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a27~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.381 ; 0.889 ; -; 0.321 ; system:inst_cpu|system_cpu:cpu|ic_fill_tag[7] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.385 ; 0.893 ; -; 0.322 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[26] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.387 ; 0.896 ; -; 0.322 ; system:inst_cpu|system_cpu:cpu|ic_fill_valid_bits[5] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.381 ; 0.890 ; -; 0.322 ; system:inst_cpu|system_cpu:cpu|ic_fill_tag[11] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.385 ; 0.894 ; -; 0.323 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[29] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.388 ; 0.898 ; -; 0.323 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[0] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.381 ; 0.891 ; -; 0.324 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[1] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.379 ; 0.890 ; -; 0.324 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[3] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.379 ; 0.890 ; -; 0.324 ; system:inst_cpu|system_cpu:cpu|A_dc_xfer_wr_data[16] ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_victim_module:system_cpu_dc_victim|altsyncram:the_altsyncram|altsyncram_r3d1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.384 ; 0.895 ; -; 0.324 ; system:inst_cpu|system_cpu:cpu|A_dc_xfer_wr_data[29] ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_victim_module:system_cpu_dc_victim|altsyncram:the_altsyncram|altsyncram_r3d1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.384 ; 0.895 ; -; 0.324 ; system:inst_cpu|system_cpu:cpu|ic_tag_wraddress[6] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.380 ; 0.891 ; -; 0.325 ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[0] ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.381 ; 0.893 ; -; 0.326 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[4] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.379 ; 0.892 ; -; 0.326 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|data_to_uart[3] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.378 ; 0.891 ; -; 0.327 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|data_in_shift_reg[6] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.382 ; 0.896 ; -; 0.327 ; system:inst_cpu|system_cpu:cpu|ic_tag_wraddress[3] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.380 ; 0.894 ; -; 0.328 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|data_in_shift_reg[4] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.382 ; 0.897 ; -; 0.329 ; system:inst_cpu|system_cpu:cpu|ic_fill_tag[2] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.385 ; 0.901 ; -; 0.332 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|data_to_uart[6] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.378 ; 0.897 ; -; 0.332 ; system:inst_cpu|system_cpu:cpu|A_dc_xfer_wr_data[30] ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_victim_module:system_cpu_dc_victim|altsyncram:the_altsyncram|altsyncram_r3d1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.384 ; 0.903 ; -; 0.332 ; system:inst_cpu|system_cpu:cpu|ic_tag_wraddress[1] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.380 ; 0.899 ; +; 0.230 ; system:inst_cpu|system_cpu:cpu|ic_fill_valid_bits[0] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.381 ; 0.798 ; +; 0.231 ; system:inst_cpu|system_cpu:cpu|ic_fill_valid_bits[5] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.381 ; 0.799 ; +; 0.233 ; system:inst_cpu|system_cpu:cpu|ic_fill_valid_bits[2] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.381 ; 0.801 ; +; 0.286 ; system:inst_cpu|system_cpu:cpu|M_bht_ptr_unfiltered[0] ; system:inst_cpu|system_cpu:cpu|system_cpu_bht_module:system_cpu_bht|altsyncram:the_altsyncram|altsyncram_fhg1:auto_generated|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.378 ; 0.851 ; +; 0.288 ; system:inst_cpu|system_cpu:cpu|M_bht_ptr_unfiltered[1] ; system:inst_cpu|system_cpu:cpu|system_cpu_bht_module:system_cpu_bht|altsyncram:the_altsyncram|altsyncram_fhg1:auto_generated|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.378 ; 0.853 ; +; 0.301 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[4] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a0~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.386 ; 0.874 ; +; 0.303 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[2] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.381 ; 0.871 ; +; 0.304 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[3] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.380 ; 0.871 ; +; 0.304 ; system:inst_cpu|system_cpu:cpu|i_readdata_d1[0] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.381 ; 0.872 ; +; 0.305 ; system:inst_cpu|system_cpu:cpu|M_bht_ptr_unfiltered[3] ; system:inst_cpu|system_cpu:cpu|system_cpu_bht_module:system_cpu_bht|altsyncram:the_altsyncram|altsyncram_fhg1:auto_generated|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.378 ; 0.870 ; +; 0.306 ; system:inst_cpu|system_cpu:cpu|i_readdata_d1[31] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a22~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.382 ; 0.875 ; +; 0.307 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[4] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.381 ; 0.875 ; +; 0.307 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[28] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.384 ; 0.878 ; +; 0.308 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|data_to_uart[6] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.382 ; 0.877 ; +; 0.308 ; system:inst_cpu|system_cpu:cpu|i_readdata_d1[18] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a18~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.381 ; 0.876 ; +; 0.308 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[26] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.384 ; 0.879 ; +; 0.308 ; system:inst_cpu|system_cpu:cpu|i_readdata_d1[1] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.381 ; 0.876 ; +; 0.308 ; system:inst_cpu|system_cpu:cpu|M_bht_ptr_unfiltered[4] ; system:inst_cpu|system_cpu:cpu|system_cpu_bht_module:system_cpu_bht|altsyncram:the_altsyncram|altsyncram_fhg1:auto_generated|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.378 ; 0.873 ; +; 0.309 ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[1] ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.392 ; 0.888 ; +; 0.309 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[1] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.381 ; 0.877 ; +; 0.309 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[8] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.390 ; 0.886 ; +; 0.309 ; system:inst_cpu|system_cpu:cpu|i_readdata_d1[2] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.385 ; 0.881 ; +; 0.310 ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[2] ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.378 ; 0.875 ; +; 0.310 ; system:inst_cpu|system_cpu:cpu|i_readdata_d1[20] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a18~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.381 ; 0.878 ; +; 0.311 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[1] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.380 ; 0.878 ; +; 0.311 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[25] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.384 ; 0.882 ; +; 0.311 ; system:inst_cpu|system_cpu:cpu|ic_fill_valid_bits[1] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.381 ; 0.879 ; +; 0.311 ; system:inst_cpu|system_cpu:cpu|ic_fill_valid_bits[7] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.381 ; 0.879 ; +; 0.313 ; system:inst_cpu|system_cpu:cpu|i_readdata_d1[21] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a18~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.381 ; 0.881 ; +; 0.313 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[6] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a0~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.388 ; 0.888 ; +; 0.315 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[0] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.380 ; 0.882 ; +; 0.315 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|data_in_shift_reg[4] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.384 ; 0.886 ; +; 0.315 ; system:inst_cpu|system_cpu:cpu|i_readdata_d1[3] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.386 ; 0.888 ; +; 0.316 ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[3] ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.378 ; 0.881 ; +; 0.316 ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[0] ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.392 ; 0.895 ; +; 0.316 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|data_in_shift_reg[7] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.384 ; 0.887 ; +; 0.317 ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[4] ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.392 ; 0.896 ; +; 0.318 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|data_in_shift_reg[1] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.384 ; 0.889 ; +; 0.318 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[12] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.387 ; 0.892 ; +; 0.320 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|data_in_shift_reg[8] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.384 ; 0.891 ; +; 0.320 ; system:inst_cpu|system_cpu:cpu|i_readdata_d1[19] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a18~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.381 ; 0.888 ; +; 0.321 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[0] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a0~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.388 ; 0.896 ; +; 0.322 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[6] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.380 ; 0.889 ; +; 0.322 ; system:inst_cpu|system_cpu:cpu|ic_fill_valid_bits[4] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.381 ; 0.890 ; +; 0.323 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[9] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.387 ; 0.897 ; +; 0.324 ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[5] ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.378 ; 0.889 ; +; 0.324 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[2] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.380 ; 0.891 ; +; 0.324 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[6] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.381 ; 0.892 ; +; 0.324 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|data_to_uart[0] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.380 ; 0.891 ; +; 0.324 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|data_to_uart[1] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.380 ; 0.891 ; +; 0.324 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[7] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a0~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.383 ; 0.894 ; +; 0.326 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|data_in_shift_reg[5] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.384 ; 0.897 ; +; 0.326 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[22] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a0~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.383 ; 0.896 ; +; 0.326 ; system:inst_cpu|system_cpu:cpu|M_bht_ptr_unfiltered[7] ; system:inst_cpu|system_cpu:cpu|system_cpu_bht_module:system_cpu_bht|altsyncram:the_altsyncram|altsyncram_fhg1:auto_generated|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.378 ; 0.891 ; +; 0.327 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[14] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.390 ; 0.904 ; +; 0.327 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[3] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a0~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.386 ; 0.900 ; +; 0.328 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[31] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.384 ; 0.899 ; +; 0.329 ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[4] ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.378 ; 0.894 ; +; 0.330 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|data_in_shift_reg[2] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.384 ; 0.901 ; +; 0.330 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonAReg[2] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.378 ; 0.895 ; ; 0.332 ; system:inst_cpu|system_cpu:cpu|ic_fill_valid_bits[3] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.381 ; 0.900 ; -; 0.333 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[2] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a0~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.388 ; 0.908 ; -; 0.334 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonAReg[5] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.381 ; 0.902 ; -; 0.335 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[19] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a0~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.388 ; 0.910 ; -; 0.335 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[22] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a0~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.388 ; 0.910 ; -; 0.336 ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[1] ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.381 ; 0.904 ; -; 0.336 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonAReg[7] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.381 ; 0.904 ; -; 0.336 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|data_to_uart[1] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.382 ; 0.905 ; -; 0.336 ; system:inst_cpu|system_cpu:cpu|M_bht_ptr_unfiltered[1] ; system:inst_cpu|system_cpu:cpu|system_cpu_bht_module:system_cpu_bht|altsyncram:the_altsyncram|altsyncram_fhg1:auto_generated|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.382 ; 0.905 ; -; 0.337 ; system:inst_cpu|system_cpu:cpu|ic_tag_wraddress[2] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.380 ; 0.904 ; -; 0.337 ; system:inst_cpu|system_cpu:cpu|ic_fill_tag[0] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.385 ; 0.909 ; -; 0.337 ; system:inst_cpu|system_cpu:cpu|ic_fill_tag[9] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.384 ; 0.908 ; -; 0.338 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|data_in_shift_reg[8] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.382 ; 0.907 ; -; 0.340 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|data_to_uart[4] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.378 ; 0.905 ; -; 0.340 ; system:inst_cpu|system_cpu:cpu|ic_fill_dp_offset[0] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a27~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.381 ; 0.908 ; -; 0.341 ; system:inst_cpu|system_cpu:cpu|ic_tag_wraddress[0] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.380 ; 0.908 ; -; 0.342 ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[4] ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.381 ; 0.910 ; -; 0.342 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|data_in_shift_reg[3] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.382 ; 0.911 ; -; 0.342 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|data_to_uart[7] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.378 ; 0.907 ; -; 0.342 ; system:inst_cpu|system_cpu:cpu|ic_tag_wraddress[4] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.380 ; 0.909 ; -; 0.343 ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[3] ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.381 ; 0.911 ; -; 0.346 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[27] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.387 ; 0.920 ; -; 0.346 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[2] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.381 ; 0.914 ; -; 0.347 ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[5] ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.381 ; 0.915 ; -; 0.350 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[25] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.387 ; 0.924 ; -; 0.352 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[11] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.388 ; 0.927 ; -; 0.353 ; system:inst_cpu|system_cpu:cpu|ic_fill_tag[12] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.384 ; 0.924 ; -; 0.354 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|data_to_uart[2] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.378 ; 0.919 ; -; 0.356 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[6] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.379 ; 0.922 ; -; 0.357 ; system:inst_cpu|altera_merlin_slave_translator:sysid_control_slave_translator|wait_latency_counter[1] ; system:inst_cpu|altera_merlin_slave_translator:sysid_control_slave_translator|wait_latency_counter[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.063 ; 0.577 ; -; 0.357 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_debug:the_system_cpu_nios2_oci_debug|resetlatch ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_debug:the_system_cpu_nios2_oci_debug|resetlatch ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.063 ; 0.577 ; -; 0.357 ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[15] ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.063 ; 0.577 ; -; 0.357 ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[6] ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[6] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.063 ; 0.577 ; -; 0.357 ; system:inst_cpu|system_cpu:cpu|ic_fill_ap_cnt[1] ; system:inst_cpu|system_cpu:cpu|ic_fill_ap_cnt[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.063 ; 0.577 ; -; 0.357 ; system:inst_cpu|system_cpu:cpu|ic_fill_ap_cnt[2] ; system:inst_cpu|system_cpu:cpu|ic_fill_ap_cnt[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.063 ; 0.577 ; -; 0.357 ; system:inst_cpu|system_cpu:cpu|i_read ; system:inst_cpu|system_cpu:cpu|i_read ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.063 ; 0.577 ; -; 0.357 ; system:inst_cpu|altera_merlin_traffic_limiter:limiter|has_pending_responses ; system:inst_cpu|altera_merlin_traffic_limiter:limiter|has_pending_responses ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.063 ; 0.577 ; -; 0.357 ; system:inst_cpu|system_sdram:sdram|m_count[0] ; system:inst_cpu|system_sdram:sdram|m_count[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.063 ; 0.577 ; -; 0.357 ; system:inst_cpu|system_sdram:sdram|m_state.000000100 ; system:inst_cpu|system_sdram:sdram|m_state.000000100 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.063 ; 0.577 ; -; 0.357 ; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_rx:the_system_uart_wifi_rx|rx_char_ready ; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_rx:the_system_uart_wifi_rx|rx_char_ready ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.063 ; 0.577 ; +; 0.334 ; system:inst_cpu|system_cpu:cpu|ic_fill_valid_bits[6] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.381 ; 0.902 ; +; 0.335 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[29] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.392 ; 0.914 ; +; 0.336 ; system:inst_cpu|system_cpu:cpu|A_dc_xfer_wr_offset[2] ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_victim_module:system_cpu_dc_victim|altsyncram:the_altsyncram|altsyncram_r3d1:auto_generated|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.377 ; 0.900 ; +; 0.337 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[3] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.381 ; 0.905 ; +; 0.337 ; system:inst_cpu|system_cpu:cpu|M_bht_ptr_unfiltered[5] ; system:inst_cpu|system_cpu:cpu|system_cpu_bht_module:system_cpu_bht|altsyncram:the_altsyncram|altsyncram_fhg1:auto_generated|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.378 ; 0.902 ; +; 0.338 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[5] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a0~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.383 ; 0.908 ; +; 0.338 ; system:inst_cpu|system_cpu:cpu|M_bht_ptr_unfiltered[2] ; system:inst_cpu|system_cpu:cpu|system_cpu_bht_module:system_cpu_bht|altsyncram:the_altsyncram|altsyncram_fhg1:auto_generated|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.381 ; 0.906 ; +; 0.339 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|data_in_shift_reg[3] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.384 ; 0.910 ; +; 0.341 ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[3] ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.392 ; 0.920 ; +; 0.342 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|data_to_uart[2] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.385 ; 0.914 ; +; 0.343 ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[1] ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.378 ; 0.908 ; +; 0.343 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[13] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.387 ; 0.917 ; +; 0.344 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[20] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a0~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.386 ; 0.917 ; +; 0.346 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[30] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.384 ; 0.917 ; +; 0.347 ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[5] ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.392 ; 0.926 ; +; 0.349 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[5] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.381 ; 0.917 ; +; 0.349 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[11] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.390 ; 0.926 ; +; 0.349 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[1] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a0~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.383 ; 0.919 ; +; 0.350 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[21] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a0~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.383 ; 0.920 ; +; 0.351 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[2] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a0~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.388 ; 0.926 ; +; 0.352 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[5] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.380 ; 0.919 ; +; 0.352 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|data_in_shift_reg[6] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.384 ; 0.923 ; +; 0.352 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[16] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a0~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.383 ; 0.922 ; +; 0.354 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[18] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a0~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.383 ; 0.924 ; +; 0.356 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonAReg[5] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a0~portb_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.374 ; 0.917 ; +; 0.357 ; system:inst_cpu|system_cpu:cpu|A_dc_wr_data_cnt[1] ; system:inst_cpu|system_cpu:cpu|A_dc_wr_data_cnt[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.063 ; 0.577 ; +; 0.357 ; system:inst_cpu|system_cpu:cpu|A_dc_wr_data_cnt[2] ; system:inst_cpu|system_cpu:cpu|A_dc_wr_data_cnt[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.063 ; 0.577 ; +; 0.357 ; system:inst_cpu|system_cpu:cpu|A_dc_wb_wr_active ; system:inst_cpu|system_cpu:cpu|A_dc_wb_wr_active ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.063 ; 0.577 ; +; 0.357 ; system:inst_cpu|system_cpu:cpu|A_dc_wb_active ; system:inst_cpu|system_cpu:cpu|A_dc_wb_active ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.063 ; 0.577 ; +; 0.357 ; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_tx:the_system_uart_wifi_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[9] ; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_tx:the_system_uart_wifi_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.063 ; 0.577 ; +; 0.357 ; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_tx:the_system_uart_wifi_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[0] ; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_tx:the_system_uart_wifi_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.063 ; 0.577 ; ; 0.357 ; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_tx:the_system_uart_wifi_tx|tx_overrun ; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_tx:the_system_uart_wifi_tx|tx_overrun ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.063 ; 0.577 ; -; 0.357 ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|rvalid ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|rvalid ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.063 ; 0.577 ; +; 0.357 ; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_rx:the_system_uart_wifi_rx|rx_overrun ; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_rx:the_system_uart_wifi_rx|rx_overrun ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.063 ; 0.577 ; +; 0.357 ; system:inst_cpu|system_uart_mc:uart_mc|system_uart_mc_tx:the_system_uart_mc_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[9] ; system:inst_cpu|system_uart_mc:uart_mc|system_uart_mc_tx:the_system_uart_mc_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.063 ; 0.577 ; +; 0.357 ; system:inst_cpu|system_uart_mc:uart_mc|system_uart_mc_tx:the_system_uart_mc_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[0] ; system:inst_cpu|system_uart_mc:uart_mc|system_uart_mc_tx:the_system_uart_mc_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.063 ; 0.577 ; +; 0.357 ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|woverflow ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|woverflow ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.063 ; 0.577 ; +; 0.357 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|full_dff ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|full_dff ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.063 ; 0.577 ; +; 0.357 ; system:inst_cpu|system_cpu:cpu|A_dc_rd_addr_cnt[1] ; system:inst_cpu|system_cpu:cpu|A_dc_rd_addr_cnt[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.063 ; 0.577 ; +; 0.357 ; system:inst_cpu|system_cpu:cpu|d_write ; system:inst_cpu|system_cpu:cpu|d_write ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.063 ; 0.577 ; +-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ @@ -699,323 +699,323 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-------+-------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +-------+-------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ -; 2.156 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.089 ; 2.750 ; -; 2.156 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[6] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.090 ; 2.749 ; -; 2.156 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.089 ; 2.750 ; -; 2.156 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[22] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.090 ; 2.749 ; -; 2.156 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.090 ; 2.749 ; -; 2.156 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[26] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.090 ; 2.749 ; -; 2.156 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[18] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.090 ; 2.749 ; -; 2.156 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[28] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.089 ; 2.750 ; -; 2.156 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[20] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.089 ; 2.750 ; -; 2.156 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.089 ; 2.750 ; -; 2.156 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.086 ; 2.753 ; -; 2.156 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[17] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.086 ; 2.753 ; -; 2.156 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[29] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.086 ; 2.753 ; -; 2.156 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.086 ; 2.753 ; -; 2.156 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.089 ; 2.750 ; -; 2.156 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[16] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.089 ; 2.750 ; -; 2.156 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.086 ; 2.753 ; -; 2.156 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[25] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.086 ; 2.753 ; -; 2.156 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.086 ; 2.753 ; -; 2.156 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[24] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.089 ; 2.750 ; -; 2.156 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.086 ; 2.753 ; -; 2.156 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.090 ; 2.749 ; -; 2.156 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[30] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.090 ; 2.749 ; -; 2.156 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[14] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.090 ; 2.749 ; -; 2.156 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.082 ; 2.757 ; -; 2.156 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.082 ; 2.757 ; -; 2.156 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.082 ; 2.757 ; -; 2.156 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[27] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.082 ; 2.757 ; -; 2.156 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.082 ; 2.757 ; -; 2.156 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[23] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.082 ; 2.757 ; -; 2.156 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.082 ; 2.757 ; -; 2.156 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[31] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.082 ; 2.757 ; -; 6.653 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.173 ; 3.066 ; -; 6.653 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.171 ; 3.068 ; -; 6.654 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.171 ; 3.067 ; -; 6.654 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.173 ; 3.065 ; -; 6.654 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[14] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.170 ; 3.068 ; -; 6.654 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.170 ; 3.068 ; -; 6.654 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.174 ; 3.064 ; -; 6.654 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.170 ; 3.068 ; -; 6.654 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.170 ; 3.068 ; -; 6.717 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.195 ; 2.980 ; -; 6.717 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.195 ; 2.980 ; -; 6.720 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.193 ; 2.979 ; -; 6.720 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[6] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.193 ; 2.979 ; -; 6.721 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.196 ; 2.975 ; -; 6.721 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.196 ; 2.975 ; -; 6.723 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.210 ; 2.959 ; -; 6.723 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.100 ; 3.077 ; -; 6.723 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.100 ; 3.077 ; -; 6.726 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.098 ; 3.076 ; -; 6.726 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[6] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.098 ; 3.076 ; -; 6.726 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.108 ; 3.066 ; -; 6.727 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.101 ; 3.072 ; -; 6.727 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.101 ; 3.072 ; -; 6.729 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.115 ; 3.056 ; -; 6.729 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.111 ; 3.060 ; -; 6.729 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.115 ; 3.056 ; -; 6.730 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.109 ; 3.061 ; -; 6.730 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.109 ; 3.061 ; -; 6.736 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.091 ; 3.071 ; -; 6.736 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.094 ; 3.068 ; -; 6.736 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.094 ; 3.068 ; -; 6.736 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.092 ; 3.070 ; -; 6.737 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.092 ; 3.069 ; -; 6.737 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.092 ; 3.069 ; -; 6.737 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.093 ; 3.068 ; -; 6.737 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[6] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.093 ; 3.068 ; -; 6.737 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.095 ; 3.066 ; -; 6.737 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.094 ; 3.067 ; -; 6.737 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.092 ; 3.069 ; -; 6.737 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.091 ; 3.070 ; -; 6.737 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.091 ; 3.070 ; -; 6.737 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.095 ; 3.066 ; -; 6.737 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.091 ; 3.070 ; -; 6.737 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[14] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.091 ; 3.070 ; -; 6.737 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_dqm[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.095 ; 3.066 ; -; 6.737 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_dqm[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.095 ; 3.066 ; -; 6.737 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_bank[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.093 ; 3.068 ; -; 6.737 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_bank[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.092 ; 3.069 ; -; 6.743 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.113 ; 3.044 ; -; 6.911 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_2 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.091 ; 2.877 ; -; 6.911 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_9 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.089 ; 2.879 ; -; 6.912 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_7 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.091 ; 2.876 ; -; 6.912 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_8 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.089 ; 2.878 ; -; 6.912 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_10 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.088 ; 2.879 ; -; 6.912 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_11 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.088 ; 2.879 ; -; 6.912 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_12 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.092 ; 2.875 ; -; 6.912 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_13 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.088 ; 2.879 ; -; 6.912 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_14 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.088 ; 2.879 ; -; 6.915 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_15 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.113 ; 2.852 ; -; 6.915 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_4 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.113 ; 2.852 ; -; 6.918 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_5 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.111 ; 2.851 ; -; 6.918 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_6 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.111 ; 2.851 ; -; 6.919 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.114 ; 2.847 ; -; 6.919 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_1 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.114 ; 2.847 ; -; 6.921 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_3 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.128 ; 2.831 ; -; 6.945 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_cmd[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.093 ; 2.860 ; -; 6.948 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_cmd[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.100 ; 2.852 ; -; 6.948 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_cmd[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.100 ; 2.852 ; +; 1.948 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.097 ; 2.950 ; +; 1.948 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[29] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.097 ; 2.950 ; +; 1.948 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.097 ; 2.950 ; +; 1.948 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[17] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.097 ; 2.950 ; +; 1.948 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[25] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.097 ; 2.950 ; +; 1.948 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.097 ; 2.950 ; +; 1.948 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.097 ; 2.950 ; +; 1.948 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.097 ; 2.950 ; +; 1.949 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[6] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.095 ; 2.951 ; +; 1.949 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[26] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.095 ; 2.951 ; +; 1.949 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.095 ; 2.951 ; +; 1.949 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[22] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.095 ; 2.951 ; +; 1.949 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[14] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.095 ; 2.951 ; +; 1.949 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[30] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.095 ; 2.951 ; +; 1.949 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[18] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.095 ; 2.951 ; +; 1.949 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.095 ; 2.951 ; +; 1.951 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[16] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.079 ; 2.965 ; +; 1.951 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[20] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.079 ; 2.965 ; +; 1.951 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[28] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.079 ; 2.965 ; +; 1.951 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.079 ; 2.965 ; +; 1.951 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.079 ; 2.965 ; +; 1.951 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.079 ; 2.965 ; +; 1.951 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[24] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.079 ; 2.965 ; +; 1.951 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.079 ; 2.965 ; +; 1.952 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.081 ; 2.962 ; +; 1.952 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[27] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.081 ; 2.962 ; +; 1.952 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.081 ; 2.962 ; +; 1.952 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.081 ; 2.962 ; +; 1.952 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[23] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.081 ; 2.962 ; +; 1.952 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[31] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.081 ; 2.962 ; +; 1.952 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.081 ; 2.962 ; +; 1.952 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.081 ; 2.962 ; +; 6.446 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.172 ; 3.274 ; +; 6.448 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.169 ; 3.275 ; +; 6.448 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.170 ; 3.274 ; +; 6.448 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[14] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.169 ; 3.275 ; +; 6.448 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.169 ; 3.275 ; +; 6.448 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.173 ; 3.271 ; +; 6.448 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.169 ; 3.275 ; +; 6.448 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.170 ; 3.274 ; +; 6.448 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.172 ; 3.272 ; +; 6.516 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.192 ; 3.184 ; +; 6.516 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[6] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.192 ; 3.184 ; +; 6.516 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.209 ; 3.167 ; +; 6.518 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.194 ; 3.180 ; +; 6.518 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.194 ; 3.180 ; +; 6.521 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.110 ; 3.269 ; +; 6.522 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.108 ; 3.270 ; +; 6.522 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.114 ; 3.264 ; +; 6.522 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.097 ; 3.281 ; +; 6.522 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[6] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.097 ; 3.281 ; +; 6.522 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.108 ; 3.270 ; +; 6.522 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.114 ; 3.264 ; +; 6.524 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.099 ; 3.277 ; +; 6.524 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.099 ; 3.277 ; +; 6.529 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.092 ; 3.277 ; +; 6.529 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[6] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.092 ; 3.277 ; +; 6.529 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.093 ; 3.276 ; +; 6.531 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.091 ; 3.276 ; +; 6.531 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.091 ; 3.276 ; +; 6.531 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.090 ; 3.277 ; +; 6.531 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.093 ; 3.274 ; +; 6.531 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.094 ; 3.273 ; +; 6.531 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.093 ; 3.274 ; +; 6.531 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.091 ; 3.276 ; +; 6.531 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.091 ; 3.276 ; +; 6.531 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.090 ; 3.277 ; +; 6.531 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.090 ; 3.277 ; +; 6.531 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.094 ; 3.273 ; +; 6.531 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.090 ; 3.277 ; +; 6.531 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[14] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.090 ; 3.277 ; +; 6.531 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_dqm[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.094 ; 3.273 ; +; 6.531 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_dqm[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.094 ; 3.273 ; +; 6.531 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.107 ; 3.262 ; +; 6.531 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_bank[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.091 ; 3.276 ; +; 6.532 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_bank[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.092 ; 3.274 ; +; 6.536 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.112 ; 3.252 ; +; 6.543 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.179 ; 3.170 ; +; 6.543 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.179 ; 3.170 ; +; 6.549 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.084 ; 3.267 ; +; 6.549 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.084 ; 3.267 ; +; 6.704 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_7 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.090 ; 3.085 ; +; 6.706 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_2 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.090 ; 3.083 ; +; 6.706 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_8 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.088 ; 3.085 ; +; 6.706 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_9 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.088 ; 3.085 ; +; 6.706 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_10 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.087 ; 3.086 ; +; 6.706 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_11 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.087 ; 3.086 ; +; 6.706 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_12 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.091 ; 3.082 ; +; 6.706 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_13 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.087 ; 3.086 ; +; 6.706 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_14 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.087 ; 3.086 ; +; 6.714 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_3 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.127 ; 3.039 ; +; 6.714 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_5 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.110 ; 3.056 ; +; 6.714 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_6 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.110 ; 3.056 ; +; 6.716 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_15 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.112 ; 3.052 ; +; 6.716 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_4 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.112 ; 3.052 ; +; 6.740 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_cmd[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.092 ; 3.066 ; +; 6.741 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.097 ; 3.042 ; +; 6.741 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_1 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.097 ; 3.042 ; +; 6.745 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_cmd[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.099 ; 3.056 ; +; 6.745 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_cmd[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.099 ; 3.056 ; +-------+-------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Slow 1200mV 85C Model Removal: 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[0]' ; -+-------+-------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+-------+-------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ -; 2.023 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_rx:the_system_uart_wifi_rx|altera_std_synchronizer:the_altera_std_synchronizer|dreg[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.391 ; 2.571 ; -; 2.023 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_rx:the_system_uart_wifi_rx|delayed_unxsync_rxdxx1 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.391 ; 2.571 ; -; 2.023 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_rx:the_system_uart_wifi_rx|baud_rate_counter[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.391 ; 2.571 ; -; 2.023 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_rx:the_system_uart_wifi_rx|baud_clk_en ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.391 ; 2.571 ; -; 2.023 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_rx:the_system_uart_wifi_rx|do_start_rx ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.391 ; 2.571 ; -; 2.334 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_slave_translator:cpu_jtag_debug_module_translator|av_readdata_pre[17] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.076 ; 2.567 ; -; 2.334 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|i_readdata_d1[17] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.076 ; 2.567 ; -; 2.334 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_slave_translator:cpu_jtag_debug_module_translator|av_readdata_pre[23] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.076 ; 2.567 ; -; 2.334 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|d_readdata_d1[23] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.076 ; 2.567 ; -; 2.334 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_slave_translator:cpu_jtag_debug_module_translator|av_readdata_pre[28] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.076 ; 2.567 ; -; 2.334 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_slave_translator:sys_clk_timer_s1_translator|read_latency_shift_reg[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.077 ; 2.568 ; -; 2.334 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|i_readdata_d1[28] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.076 ; 2.567 ; -; 2.334 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|i_readdatavalid_d1 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.076 ; 2.567 ; -; 2.334 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|d_readdata_d1[17] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.076 ; 2.567 ; -; 2.334 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|d_readdata_d1[16] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.076 ; 2.567 ; -; 2.334 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_slave_translator:sysid_control_slave_translator|wait_latency_counter[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.077 ; 2.568 ; -; 2.334 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_slave_translator:sysid_control_slave_translator|wait_latency_counter[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.077 ; 2.568 ; -; 2.334 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_slave_translator:cpu_jtag_debug_module_translator|av_readdata_pre[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.076 ; 2.567 ; -; 2.334 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_slave_translator:sys_clk_timer_s1_translator|av_readdata_pre[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.076 ; 2.567 ; -; 2.334 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_slave_translator:uart_wifi_s1_translator|av_readdata_pre[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.076 ; 2.567 ; -; 2.334 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|d_readdata_d1[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.076 ; 2.567 ; -; 2.334 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|ic_fill_ap_offset[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.072 ; 2.563 ; -; 2.334 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|i_readdata_d1[23] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.076 ; 2.567 ; -; 2.334 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|i_readdata_d1[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.076 ; 2.567 ; -; 2.334 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux|altera_merlin_arbitrator:arb|top_priority_reg[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 2.564 ; -; 2.334 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux|altera_merlin_arbitrator:arb|top_priority_reg[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 2.564 ; -; 2.334 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux|saved_grant[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 2.564 ; -; 2.334 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|ic_fill_ap_cnt[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.072 ; 2.563 ; -; 2.334 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|ic_fill_ap_cnt[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.072 ; 2.563 ; -; 2.334 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|ic_fill_ap_cnt[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.072 ; 2.563 ; -; 2.334 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|ic_fill_ap_cnt[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.072 ; 2.563 ; -; 2.334 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|i_read ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.072 ; 2.563 ; -; 2.334 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_traffic_limiter:limiter|pending_response_count[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.076 ; 2.567 ; -; 2.334 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_traffic_limiter:limiter|pending_response_count[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.076 ; 2.567 ; -; 2.334 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_traffic_limiter:limiter|pending_response_count[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.076 ; 2.567 ; -; 2.334 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_traffic_limiter:limiter|pending_response_count[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.076 ; 2.567 ; -; 2.334 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_traffic_limiter:limiter|has_pending_responses ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.072 ; 2.563 ; -; 2.334 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux|saved_grant[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 2.564 ; -; 2.334 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_slave_translator:cpu_jtag_debug_module_translator|av_readdata_pre[16] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.076 ; 2.567 ; -; 2.334 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|i_readdata_d1[16] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.076 ; 2.567 ; -; 2.335 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_slave_translator:cpu_jtag_debug_module_translator|waitrequest_reset_override ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 2.565 ; -; 2.335 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.076 ; 2.568 ; -; 2.335 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.076 ; 2.568 ; -; 2.335 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_slave_translator:cpu_jtag_debug_module_translator|wait_latency_counter[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 2.565 ; -; 2.335 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_slave_translator:cpu_jtag_debug_module_translator|wait_latency_counter[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 2.565 ; -; 2.335 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_slave_translator:cpu_jtag_debug_module_translator|end_begintransfer ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 2.565 ; -; 2.335 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|A_ienable_reg_irq14 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.076 ; 2.568 ; -; 2.335 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|A_ienable_reg_irq6 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.076 ; 2.568 ; -; 2.335 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|A_ienable_reg_irq4 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.076 ; 2.568 ; -; 2.335 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][102] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.076 ; 2.568 ; -; 2.335 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][102] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.076 ; 2.568 ; -; 2.335 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux|packet_in_progress ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 2.565 ; -; 2.342 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|refresh_counter[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.091 ; 2.590 ; -; 2.342 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|refresh_counter[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.090 ; 2.589 ; -; 2.342 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|refresh_counter[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.091 ; 2.590 ; -; 2.342 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|refresh_counter[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.091 ; 2.590 ; -; 2.342 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|refresh_counter[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.090 ; 2.589 ; -; 2.342 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|refresh_counter[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.090 ; 2.589 ; -; 2.342 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|refresh_counter[6] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.090 ; 2.589 ; -; 2.342 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|refresh_counter[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.090 ; 2.589 ; -; 2.342 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|refresh_counter[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.091 ; 2.590 ; -; 2.342 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|refresh_counter[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.090 ; 2.589 ; -; 2.342 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|refresh_counter[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.090 ; 2.589 ; -; 2.342 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|refresh_counter[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.090 ; 2.589 ; -; 2.342 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|refresh_counter[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.090 ; 2.589 ; -; 2.342 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|refresh_counter[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.090 ; 2.589 ; -; 2.342 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|refresh_counter[14] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.090 ; 2.589 ; -; 2.342 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[5]~_Duplicate_1 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.082 ; 2.581 ; -; 2.342 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[6]~_Duplicate_1 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.082 ; 2.581 ; -; 2.342 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[7]~_Duplicate_1 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.082 ; 2.581 ; -; 2.342 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[8]~_Duplicate_1 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.082 ; 2.581 ; -; 2.342 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[10]~_Duplicate_1 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.082 ; 2.581 ; -; 2.342 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|A_mul_result[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.081 ; 2.580 ; -; 2.342 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|A_mul_result[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.081 ; 2.580 ; -; 2.342 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|A_mul_result[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.081 ; 2.580 ; -; 2.342 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|A_mul_result[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.081 ; 2.580 ; -; 2.342 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|A_mul_result[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.081 ; 2.580 ; -; 2.342 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|A_mul_result[6] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.081 ; 2.580 ; -; 2.342 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|A_mul_result[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.081 ; 2.580 ; -; 2.342 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|A_mul_result[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.081 ; 2.580 ; -; 2.342 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|A_mul_result[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.081 ; 2.580 ; -; 2.342 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|A_mul_result[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.081 ; 2.580 ; -; 2.342 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|A_mul_result[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.081 ; 2.580 ; -; 2.342 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|A_mul_result[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.081 ; 2.580 ; -; 2.342 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|A_mul_result[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.081 ; 2.580 ; -; 2.342 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|A_mul_result[14] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.081 ; 2.580 ; -; 2.342 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|A_mul_result[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.081 ; 2.580 ; -; 2.342 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|A_mul_result[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.081 ; 2.580 ; -; 2.343 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entries[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.074 ; 2.574 ; -; 2.343 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][65] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.064 ; 2.564 ; -; 2.343 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[6][55] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.064 ; 2.564 ; -; 2.343 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][55] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.066 ; 2.566 ; -; 2.343 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.066 ; 2.566 ; -; 2.343 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:sysid_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.066 ; 2.566 ; -; 2.343 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|rst2 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.070 ; 2.570 ; -; 2.343 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|t_dav ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.070 ; 2.570 ; -; 2.343 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|write1 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.070 ; 2.570 ; -; 2.343 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|write2 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.070 ; 2.570 ; -; 2.343 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|t_ena~reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.070 ; 2.570 ; -; 2.343 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|cntr_do7:count_usedw|counter_reg_bit[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.074 ; 2.574 ; -+-------+-------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Slow 1200mV 85C Model Minimum Pulse Width: 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[0]' ; -+-------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; -+-------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; 4.693 ; 4.987 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[16] ; -; 4.693 ; 4.987 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[17] ; -; 4.693 ; 4.987 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[18] ; -; 4.693 ; 4.987 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[19] ; -; 4.693 ; 4.987 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[20] ; -; 4.693 ; 4.987 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[21] ; -; 4.693 ; 4.987 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[22] ; -; 4.693 ; 4.987 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[23] ; -; 4.693 ; 4.987 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[24] ; -; 4.693 ; 4.987 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[25] ; -; 4.693 ; 4.987 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[26] ; -; 4.693 ; 4.987 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[27] ; -; 4.693 ; 4.987 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[28] ; -; 4.693 ; 4.987 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[29] ; -; 4.693 ; 4.987 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[30] ; -; 4.693 ; 4.987 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[31] ; -; 4.693 ; 4.987 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[0]~_Duplicate_1 ; -; 4.693 ; 4.987 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[10]~_Duplicate_1 ; -; 4.693 ; 4.987 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[11]~_Duplicate_1 ; -; 4.693 ; 4.987 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[12]~_Duplicate_1 ; -; 4.693 ; 4.987 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[13]~_Duplicate_1 ; -; 4.693 ; 4.987 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[14]~_Duplicate_1 ; -; 4.693 ; 4.987 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[15]~_Duplicate_1 ; -; 4.693 ; 4.987 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[1]~_Duplicate_1 ; -; 4.693 ; 4.987 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[2]~_Duplicate_1 ; -; 4.693 ; 4.987 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[3]~_Duplicate_1 ; -; 4.693 ; 4.987 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[4]~_Duplicate_1 ; -; 4.693 ; 4.987 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[5]~_Duplicate_1 ; -; 4.693 ; 4.987 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[6]~_Duplicate_1 ; -; 4.693 ; 4.987 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[7]~_Duplicate_1 ; -; 4.693 ; 4.987 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[8]~_Duplicate_1 ; -; 4.693 ; 4.987 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[9]~_Duplicate_1 ; -; 4.693 ; 4.987 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3 ; -; 4.693 ; 4.987 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT1 ; -; 4.693 ; 4.987 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT10 ; -; 4.693 ; 4.987 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT11 ; -; 4.693 ; 4.987 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT12 ; -; 4.693 ; 4.987 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT13 ; -; 4.693 ; 4.987 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT14 ; -; 4.693 ; 4.987 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT15 ; -; 4.693 ; 4.987 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT2 ; -; 4.693 ; 4.987 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT3 ; -; 4.693 ; 4.987 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT4 ; -; 4.693 ; 4.987 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT5 ; -; 4.693 ; 4.987 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT6 ; -; 4.693 ; 4.987 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT7 ; -; 4.693 ; 4.987 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT8 ; -; 4.693 ; 4.987 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT9 ; -; 4.694 ; 4.988 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[0] ; -; 4.694 ; 4.988 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[10] ; -; 4.694 ; 4.988 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[11] ; -; 4.694 ; 4.988 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[12] ; -; 4.694 ; 4.988 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[13] ; -; 4.694 ; 4.988 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[14] ; -; 4.694 ; 4.988 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[15] ; -; 4.694 ; 4.988 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[1] ; -; 4.694 ; 4.988 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[2] ; -; 4.694 ; 4.988 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[3] ; -; 4.694 ; 4.988 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[4] ; -; 4.694 ; 4.988 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[5] ; -; 4.694 ; 4.988 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[6] ; -; 4.694 ; 4.988 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[7] ; -; 4.694 ; 4.988 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[8] ; -; 4.694 ; 4.988 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[9] ; -; 4.694 ; 4.988 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[0] ; -; 4.694 ; 4.988 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[10] ; -; 4.694 ; 4.988 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[11] ; -; 4.694 ; 4.988 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[12] ; -; 4.694 ; 4.988 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[13] ; -; 4.694 ; 4.988 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[14] ; -; 4.694 ; 4.988 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[15] ; -; 4.694 ; 4.988 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[1] ; -; 4.694 ; 4.988 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[2] ; -; 4.694 ; 4.988 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[3] ; -; 4.694 ; 4.988 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[4] ; -; 4.694 ; 4.988 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[5] ; -; 4.694 ; 4.988 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[6] ; -; 4.694 ; 4.988 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[7] ; -; 4.694 ; 4.988 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[8] ; -; 4.694 ; 4.988 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[9] ; -; 4.694 ; 4.988 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3 ; -; 4.694 ; 4.988 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT1 ; -; 4.694 ; 4.988 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT10 ; -; 4.694 ; 4.988 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT11 ; -; 4.694 ; 4.988 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT12 ; -; 4.694 ; 4.988 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT13 ; -; 4.694 ; 4.988 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT14 ; -; 4.694 ; 4.988 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT15 ; -; 4.694 ; 4.988 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT16 ; -; 4.694 ; 4.988 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT17 ; -; 4.694 ; 4.988 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT18 ; -; 4.694 ; 4.988 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT19 ; -; 4.694 ; 4.988 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT2 ; -; 4.694 ; 4.988 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT20 ; -; 4.694 ; 4.988 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT21 ; -; 4.694 ; 4.988 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT22 ; -; 4.694 ; 4.988 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT23 ; -; 4.694 ; 4.988 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT24 ; -; 4.694 ; 4.988 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT25 ; -; 4.694 ; 4.988 ; 0.294 ; High Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT26 ; -+-------+--------------+----------------+------------------+----------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Removal: 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[0]' ; ++-------+-------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+-------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ +; 2.524 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|i_addr[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.086 ; 2.767 ; +; 2.525 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|rd_address ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.084 ; 2.766 ; +; 2.525 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_state.000000010 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.085 ; 2.767 ; +; 2.525 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_state.000100000 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.085 ; 2.767 ; +; 2.525 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|f_pop ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.085 ; 2.767 ; +; 2.525 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|byteen_reg[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 2.762 ; +; 2.525 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|byteen_reg[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 2.762 ; +; 2.525 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|address_reg[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 2.762 ; +; 2.525 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|address_reg[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 2.762 ; +; 2.525 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|address_reg[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 2.762 ; +; 2.525 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|address_reg[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 2.762 ; +; 2.525 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|address_reg[23] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 2.762 ; +; 2.525 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_state.000000100 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.085 ; 2.767 ; +; 2.525 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|data_reg[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 2.762 ; +; 2.527 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_next.000001000 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.082 ; 2.766 ; +; 2.527 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_state.000001000 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.082 ; 2.766 ; +; 2.527 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_next.000000001 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.082 ; 2.766 ; +; 2.527 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_next.000010000 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.082 ; 2.766 ; +; 2.527 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_state.000010000 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.082 ; 2.766 ; +; 2.527 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|count[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.077 ; 2.761 ; +; 2.527 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|use_reg ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.077 ; 2.761 ; +; 2.527 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|i_next.010 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.083 ; 2.767 ; +; 2.527 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|i_count[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.083 ; 2.767 ; +; 2.527 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|i_count[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.083 ; 2.767 ; +; 2.527 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|i_state.111 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.083 ; 2.767 ; +; 2.527 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|i_count[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.083 ; 2.767 ; +; 2.527 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|i_state.010 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.083 ; 2.767 ; +; 2.527 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_cmd[0]~_Duplicate_1 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.082 ; 2.766 ; +; 2.527 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_cmd[2]~_Duplicate_1 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.082 ; 2.766 ; +; 2.527 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|i_cmd[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.083 ; 2.767 ; +; 2.527 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_cmd[1]~_Duplicate_1 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.082 ; 2.766 ; +; 2.527 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|rd_valid[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.082 ; 2.766 ; +; 2.527 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|endofpacket_reg ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.077 ; 2.761 ; +; 2.527 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][84] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.081 ; 2.765 ; +; 2.527 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][84] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.081 ; 2.765 ; +; 2.527 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux_001|packet_in_progress ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.077 ; 2.761 ; +; 2.527 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][83] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.081 ; 2.765 ; +; 2.527 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][83] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.081 ; 2.765 ; +; 2.527 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][54] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.077 ; 2.761 ; +; 2.527 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][53] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.081 ; 2.765 ; +; 2.527 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][53] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.081 ; 2.765 ; +; 2.527 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][56] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.081 ; 2.765 ; +; 2.527 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][56] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.081 ; 2.765 ; +; 2.527 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.081 ; 2.765 ; +; 2.527 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.081 ; 2.765 ; +; 2.527 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][55] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.081 ; 2.765 ; +; 2.527 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][55] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.081 ; 2.765 ; +; 2.527 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|i_state.011 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.083 ; 2.767 ; +; 2.527 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|i_next.101 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.083 ; 2.767 ; +; 2.527 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|i_state.101 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.083 ; 2.767 ; +; 2.527 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|init_done ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.082 ; 2.766 ; +; 2.527 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|ack_refresh_request ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.082 ; 2.766 ; +; 2.527 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|refresh_request ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.082 ; 2.766 ; +; 2.527 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_state.100000000 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.082 ; 2.766 ; +; 2.528 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux_001|altera_merlin_arbitrator:arb|top_priority_reg[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.076 ; 2.761 ; +; 2.528 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux_001|altera_merlin_arbitrator:arb|top_priority_reg[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.076 ; 2.761 ; +; 2.528 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux_001|saved_grant[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.076 ; 2.761 ; +; 2.528 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|i_next.000 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.082 ; 2.767 ; +; 2.528 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|i_state.000 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.082 ; 2.767 ; +; 2.528 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|i_next.111 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.082 ; 2.767 ; +; 2.528 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|i_cmd[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.082 ; 2.767 ; +; 2.528 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|i_cmd[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.082 ; 2.767 ; +; 2.528 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux_001|saved_grant[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.076 ; 2.761 ; +; 2.528 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|i_state.001 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.082 ; 2.767 ; +; 2.528 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[1]~_Duplicate_1 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.081 ; 2.766 ; +; 2.528 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[4]~_Duplicate_1 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.081 ; 2.766 ; +; 2.528 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[5]~_Duplicate_1 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.081 ; 2.766 ; +; 2.528 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[6]~_Duplicate_1 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.081 ; 2.766 ; +; 2.528 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[11]~_Duplicate_1 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.081 ; 2.766 ; +; 2.528 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|i_cmd[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.082 ; 2.767 ; +; 2.532 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_state.000000001 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 2.769 ; +; 2.532 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_next.010000000 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.080 ; 2.769 ; +; 2.532 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[2]~_Duplicate_1 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.078 ; 2.767 ; +; 2.533 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|wr_address ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.086 ; 2.776 ; +; 2.533 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_count[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.079 ; 2.769 ; +; 2.533 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_count[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.079 ; 2.769 ; +; 2.533 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entries[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.086 ; 2.776 ; +; 2.533 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entries[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.086 ; 2.776 ; +; 2.533 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_count[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.079 ; 2.769 ; +; 2.533 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_state.001000000 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.079 ; 2.769 ; +; 2.533 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_state.010000000 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.079 ; 2.769 ; +; 2.533 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[0]~_Duplicate_1 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.088 ; 2.778 ; +; 2.533 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[3]~_Duplicate_1 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.078 ; 2.768 ; +; 2.533 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[7]~_Duplicate_1 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.078 ; 2.768 ; +; 2.533 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[8]~_Duplicate_1 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.078 ; 2.768 ; +; 2.533 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[9]~_Duplicate_1 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.078 ; 2.768 ; +; 2.533 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[10]~_Duplicate_1 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.078 ; 2.768 ; +; 2.533 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[12]~_Duplicate_1 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.088 ; 2.778 ; +; 2.533 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[13]~_Duplicate_1 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.088 ; 2.778 ; +; 2.533 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[14]~_Duplicate_1 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.088 ; 2.778 ; +; 2.533 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[15]~_Duplicate_1 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.088 ; 2.778 ; +; 2.534 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux|altera_merlin_arbitrator:arb|top_priority_reg[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.074 ; 2.765 ; +; 2.534 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux|altera_merlin_arbitrator:arb|top_priority_reg[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.074 ; 2.765 ; +; 2.534 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux|saved_grant[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.074 ; 2.765 ; +; 2.534 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_slave_translator:cpu_jtag_debug_module_translator|waitrequest_reset_override ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.071 ; 2.762 ; +; 2.534 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_slave_translator:cpu_jtag_debug_module_translator|av_readdata_pre[22] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.074 ; 2.765 ; +; 2.534 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_slave_translator:cpu_jtag_debug_module_translator|wait_latency_counter[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.071 ; 2.762 ; +; 2.534 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_slave_translator:cpu_jtag_debug_module_translator|wait_latency_counter[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.071 ; 2.762 ; +; 2.534 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_slave_translator:cpu_jtag_debug_module_translator|end_begintransfer ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.071 ; 2.762 ; +; 2.534 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_slave_translator:cpu_jtag_debug_module_translator|av_readdata_pre[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.070 ; 2.761 ; ++-------+-------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 85C Model Minimum Pulse Width: 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[0]' ; ++-------+--------------+----------------+-----------------+----------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; ++-------+--------------+----------------+-----------------+----------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[0] ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[10] ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[11] ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[12] ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[13] ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[14] ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[15] ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[16] ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[17] ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[18] ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[19] ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[1] ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[20] ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[21] ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[22] ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[23] ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[24] ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[25] ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[26] ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[27] ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[28] ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[29] ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[2] ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[30] ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[31] ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[3] ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[4] ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[5] ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[6] ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[7] ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[8] ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[9] ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[0] ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[0]~_Duplicate_1 ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[10] ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[10]~_Duplicate_1 ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[11] ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[11]~_Duplicate_1 ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[12] ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[12]~_Duplicate_1 ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[13] ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[13]~_Duplicate_1 ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[14] ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[14]~_Duplicate_1 ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[15] ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[15]~_Duplicate_1 ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[1] ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[1]~_Duplicate_1 ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[2] ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[2]~_Duplicate_1 ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[3] ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[3]~_Duplicate_1 ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[4] ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[4]~_Duplicate_1 ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[5] ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[5]~_Duplicate_1 ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[6] ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[6]~_Duplicate_1 ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[7] ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[7]~_Duplicate_1 ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[8] ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[8]~_Duplicate_1 ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[9] ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[9]~_Duplicate_1 ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3 ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT1 ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT10 ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT11 ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT12 ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT13 ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT14 ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT15 ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT16 ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT17 ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT18 ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT19 ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT2 ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT20 ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT21 ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT22 ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT23 ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT24 ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT25 ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT26 ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT27 ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT28 ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT29 ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT3 ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT30 ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT31 ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT4 ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT5 ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT6 ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT7 ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT8 ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT9 ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3 ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT1 ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT10 ; +; 4.694 ; 4.988 ; 0.294 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT11 ; ++-------+--------------+----------------+-----------------+----------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------------------------------------------------------------------------------+ @@ -1046,106 +1046,106 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +--------+--------------+----------------+------------------+---------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; +--------+--------------+----------------+------------------+---------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; 49.624 ; 49.840 ; 0.216 ; High Pulse Width ; altera_reserved_tck ; Fall ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; -; 49.624 ; 49.840 ; 0.216 ; High Pulse Width ; altera_reserved_tck ; Fall ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|tdo~reg0 ; -; 49.627 ; 49.843 ; 0.216 ; High Pulse Width ; altera_reserved_tck ; Fall ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|jupdate ; -; 49.670 ; 49.854 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[10] ; -; 49.670 ; 49.854 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[11] ; -; 49.670 ; 49.854 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[12] ; -; 49.670 ; 49.854 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[13] ; -; 49.670 ; 49.854 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[14] ; -; 49.670 ; 49.854 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[1] ; -; 49.670 ; 49.854 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[2] ; -; 49.670 ; 49.854 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[3] ; -; 49.670 ; 49.854 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[4] ; -; 49.670 ; 49.854 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[5] ; -; 49.670 ; 49.854 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[6] ; -; 49.670 ; 49.854 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[8] ; -; 49.670 ; 49.854 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[9] ; -; 49.671 ; 49.855 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[0] ; -; 49.671 ; 49.855 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[1] ; -; 49.671 ; 49.855 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[2] ; -; 49.671 ; 49.855 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[3] ; -; 49.671 ; 49.855 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[0] ; -; 49.671 ; 49.855 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[1] ; -; 49.671 ; 49.855 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[2] ; -; 49.671 ; 49.855 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[3] ; -; 49.671 ; 49.855 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[0] ; -; 49.671 ; 49.855 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1] ; -; 49.671 ; 49.855 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2] ; -; 49.671 ; 49.855 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[3] ; -; 49.671 ; 49.855 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[4] ; -; 49.671 ; 49.855 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[5] ; -; 49.671 ; 49.855 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[6] ; -; 49.671 ; 49.855 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[7] ; -; 49.671 ; 49.855 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[8] ; -; 49.671 ; 49.855 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[9] ; -; 49.671 ; 49.855 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; -; 49.671 ; 49.855 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[10] ; -; 49.671 ; 49.855 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[11] ; -; 49.671 ; 49.855 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[12] ; -; 49.671 ; 49.855 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[13] ; -; 49.671 ; 49.855 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[14] ; -; 49.671 ; 49.855 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[15] ; -; 49.671 ; 49.855 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[1] ; -; 49.671 ; 49.855 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[2] ; -; 49.671 ; 49.855 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; -; 49.671 ; 49.855 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; -; 49.671 ; 49.855 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[5] ; -; 49.671 ; 49.855 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[6] ; -; 49.671 ; 49.855 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[7] ; -; 49.671 ; 49.855 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[9] ; -; 49.671 ; 49.855 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[0] ; -; 49.671 ; 49.855 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[1] ; -; 49.671 ; 49.855 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[2] ; -; 49.671 ; 49.855 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_dr_scan_reg ; -; 49.671 ; 49.855 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; -; 49.671 ; 49.855 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 ; -; 49.671 ; 49.855 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer|dreg[0] ; -; 49.671 ; 49.855 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|ir_out[1] ; -; 49.671 ; 49.855 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[0] ; -; 49.671 ; 49.855 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[15] ; -; 49.671 ; 49.855 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[35] ; -; 49.671 ; 49.855 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[36] ; -; 49.671 ; 49.855 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[37] ; -; 49.672 ; 49.856 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|din_s1 ; -; 49.672 ; 49.856 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|dreg[0] ; -; 49.672 ; 49.856 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[27] ; -; 49.672 ; 49.856 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[28] ; -; 49.672 ; 49.856 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[29] ; -; 49.672 ; 49.856 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[30] ; -; 49.672 ; 49.856 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[32] ; -; 49.672 ; 49.856 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[33] ; -; 49.672 ; 49.856 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[34] ; -; 49.673 ; 49.857 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[0] ; -; 49.673 ; 49.857 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[1] ; -; 49.673 ; 49.857 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[2] ; -; 49.673 ; 49.857 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[3] ; -; 49.673 ; 49.857 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[0] ; -; 49.673 ; 49.857 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[1] ; -; 49.673 ; 49.857 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[2] ; -; 49.673 ; 49.857 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[3] ; -; 49.673 ; 49.857 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1] ; -; 49.673 ; 49.857 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; -; 49.673 ; 49.857 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6] ; -; 49.673 ; 49.857 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; -; 49.673 ; 49.857 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0 ; -; 49.673 ; 49.857 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[0] ; -; 49.673 ; 49.857 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[1] ; -; 49.673 ; 49.857 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[2] ; -; 49.673 ; 49.857 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[3] ; -; 49.673 ; 49.857 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[0] ; -; 49.673 ; 49.857 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[1] ; -; 49.673 ; 49.857 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[2] ; -; 49.673 ; 49.857 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[3] ; -; 49.673 ; 49.857 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[4] ; -; 49.673 ; 49.857 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; -; 49.673 ; 49.857 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo_bypass_reg ; -; 49.673 ; 49.857 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|ir_out[0] ; -; 49.673 ; 49.857 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|count[0] ; -; 49.673 ; 49.857 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|count[1] ; -; 49.673 ; 49.857 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|count[2] ; -; 49.673 ; 49.857 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|count[3] ; +; 49.640 ; 49.856 ; 0.216 ; High Pulse Width ; altera_reserved_tck ; Fall ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|jupdate ; +; 49.641 ; 49.857 ; 0.216 ; High Pulse Width ; altera_reserved_tck ; Fall ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; +; 49.641 ; 49.857 ; 0.216 ; High Pulse Width ; altera_reserved_tck ; Fall ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|tdo~reg0 ; +; 49.685 ; 49.869 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|count[6] ; +; 49.685 ; 49.869 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|count[7] ; +; 49.685 ; 49.869 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|count[8] ; +; 49.685 ; 49.869 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|count[9] ; +; 49.685 ; 49.869 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|read ; +; 49.685 ; 49.869 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|read_req ; +; 49.685 ; 49.869 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|td_shift[8] ; +; 49.685 ; 49.869 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|td_shift[9] ; +; 49.685 ; 49.869 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|user_saw_rvalid ; +; 49.685 ; 49.869 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|wdata[0] ; +; 49.685 ; 49.869 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|wdata[1] ; +; 49.685 ; 49.869 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|wdata[2] ; +; 49.685 ; 49.869 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|wdata[3] ; +; 49.685 ; 49.869 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|wdata[4] ; +; 49.685 ; 49.869 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|wdata[5] ; +; 49.685 ; 49.869 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|wdata[6] ; +; 49.685 ; 49.869 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|wdata[7] ; +; 49.685 ; 49.869 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|write ; +; 49.685 ; 49.869 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|write_stalled ; +; 49.685 ; 49.869 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|write_valid ; +; 49.686 ; 49.870 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|count[1] ; +; 49.686 ; 49.870 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|count[2] ; +; 49.686 ; 49.870 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|count[3] ; +; 49.686 ; 49.870 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|count[4] ; +; 49.686 ; 49.870 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|count[5] ; +; 49.686 ; 49.870 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|state ; +; 49.686 ; 49.870 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|tck_t_dav ; +; 49.686 ; 49.870 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|td_shift[0] ; +; 49.686 ; 49.870 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|td_shift[10] ; +; 49.687 ; 49.871 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[10] ; +; 49.687 ; 49.871 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[11] ; +; 49.687 ; 49.871 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[12] ; +; 49.687 ; 49.871 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[13] ; +; 49.687 ; 49.871 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[14] ; +; 49.687 ; 49.871 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[15] ; +; 49.687 ; 49.871 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[35] ; +; 49.687 ; 49.871 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[8] ; +; 49.687 ; 49.871 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[9] ; +; 49.688 ; 49.872 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|DRsize.000 ; +; 49.688 ; 49.872 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|DRsize.010 ; +; 49.688 ; 49.872 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|DRsize.100 ; +; 49.688 ; 49.872 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|din_s1 ; +; 49.688 ; 49.872 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|dreg[0] ; +; 49.688 ; 49.872 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 ; +; 49.688 ; 49.872 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer|dreg[0] ; +; 49.688 ; 49.872 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|ir_out[0] ; +; 49.688 ; 49.872 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|ir_out[1] ; +; 49.688 ; 49.872 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[0] ; +; 49.688 ; 49.872 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[16] ; +; 49.688 ; 49.872 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[17] ; +; 49.688 ; 49.872 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[18] ; +; 49.688 ; 49.872 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[19] ; +; 49.688 ; 49.872 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[1] ; +; 49.688 ; 49.872 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[20] ; +; 49.688 ; 49.872 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[21] ; +; 49.688 ; 49.872 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[22] ; +; 49.688 ; 49.872 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[23] ; +; 49.688 ; 49.872 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[24] ; +; 49.688 ; 49.872 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[25] ; +; 49.688 ; 49.872 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[26] ; +; 49.688 ; 49.872 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[27] ; +; 49.688 ; 49.872 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[28] ; +; 49.688 ; 49.872 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[29] ; +; 49.688 ; 49.872 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[2] ; +; 49.688 ; 49.872 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[30] ; +; 49.688 ; 49.872 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[31] ; +; 49.688 ; 49.872 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[32] ; +; 49.688 ; 49.872 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[33] ; +; 49.688 ; 49.872 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[34] ; +; 49.688 ; 49.872 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[3] ; +; 49.688 ; 49.872 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[4] ; +; 49.688 ; 49.872 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[5] ; +; 49.688 ; 49.872 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[6] ; +; 49.688 ; 49.872 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[7] ; +; 49.688 ; 49.872 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|count[0] ; +; 49.688 ; 49.872 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|td_shift[1] ; +; 49.688 ; 49.872 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|td_shift[2] ; +; 49.688 ; 49.872 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|td_shift[3] ; +; 49.688 ; 49.872 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|td_shift[4] ; +; 49.688 ; 49.872 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|td_shift[5] ; +; 49.688 ; 49.872 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|td_shift[6] ; +; 49.688 ; 49.872 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|td_shift[7] ; +; 49.689 ; 49.873 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[0] ; +; 49.689 ; 49.873 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[1] ; +; 49.689 ; 49.873 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[2] ; +; 49.689 ; 49.873 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[3] ; +; 49.689 ; 49.873 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[0] ; +; 49.689 ; 49.873 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[1] ; +; 49.689 ; 49.873 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[2] ; +; 49.689 ; 49.873 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[3] ; +; 49.689 ; 49.873 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0] ; +; 49.689 ; 49.873 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1] ; +; 49.689 ; 49.873 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2] ; +; 49.689 ; 49.873 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[0] ; +; 49.689 ; 49.873 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[1] ; +; 49.689 ; 49.873 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[2] ; +; 49.689 ; 49.873 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[3] ; +--------+--------------+----------------+------------------+---------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ @@ -1262,8 +1262,8 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +---------------------+---------------------+-------+-------+------------+----------------------------------------------------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +---------------------+---------------------+-------+-------+------------+----------------------------------------------------------+ -; altera_reserved_tdi ; altera_reserved_tck ; 2.127 ; 2.283 ; Rise ; altera_reserved_tck ; -; altera_reserved_tms ; altera_reserved_tck ; 6.453 ; 6.601 ; Rise ; altera_reserved_tck ; +; altera_reserved_tdi ; altera_reserved_tck ; 2.287 ; 2.429 ; Rise ; altera_reserved_tck ; +; altera_reserved_tms ; altera_reserved_tck ; 6.520 ; 6.737 ; Rise ; altera_reserved_tck ; ; DRAM_DQ[*] ; CLOCK_50 ; 1.016 ; 1.180 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; DRAM_DQ[0] ; CLOCK_50 ; 1.002 ; 1.166 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; DRAM_DQ[1] ; CLOCK_50 ; 1.002 ; 1.166 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; @@ -1281,15 +1281,15 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp ; DRAM_DQ[13] ; CLOCK_50 ; 0.975 ; 1.137 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; DRAM_DQ[14] ; CLOCK_50 ; 0.975 ; 1.137 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; DRAM_DQ[15] ; CLOCK_50 ; 1.001 ; 1.165 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; GPIO_0[*] ; CLOCK_50 ; 4.886 ; 5.468 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; GPIO_0[31] ; CLOCK_50 ; 4.886 ; 5.468 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; KEY[*] ; CLOCK_50 ; 2.462 ; 2.621 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; KEY[1] ; CLOCK_50 ; 2.462 ; 2.621 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; SW[*] ; CLOCK_50 ; 2.412 ; 2.539 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; SW[0] ; CLOCK_50 ; 2.344 ; 2.476 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; SW[1] ; CLOCK_50 ; 1.905 ; 2.019 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; SW[2] ; CLOCK_50 ; 1.971 ; 2.081 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; SW[3] ; CLOCK_50 ; 2.412 ; 2.539 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_0[*] ; CLOCK_50 ; 4.763 ; 5.286 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_0[31] ; CLOCK_50 ; 4.763 ; 5.286 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; KEY[*] ; CLOCK_50 ; 2.250 ; 2.395 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; KEY[1] ; CLOCK_50 ; 2.250 ; 2.395 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; SW[*] ; CLOCK_50 ; 2.528 ; 2.577 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; SW[0] ; CLOCK_50 ; 1.904 ; 2.082 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; SW[1] ; CLOCK_50 ; 2.528 ; 2.577 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; SW[2] ; CLOCK_50 ; 2.263 ; 2.391 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; SW[3] ; CLOCK_50 ; 2.034 ; 2.152 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +---------------------+---------------------+-------+-------+------------+----------------------------------------------------------+ @@ -1298,8 +1298,8 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +---------------------+---------------------+--------+--------+------------+----------------------------------------------------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +---------------------+---------------------+--------+--------+------------+----------------------------------------------------------+ -; altera_reserved_tdi ; altera_reserved_tck ; 1.158 ; 1.079 ; Rise ; altera_reserved_tck ; -; altera_reserved_tms ; altera_reserved_tck ; -1.002 ; -1.093 ; Rise ; altera_reserved_tck ; +; altera_reserved_tdi ; altera_reserved_tck ; 1.171 ; 1.085 ; Rise ; altera_reserved_tck ; +; altera_reserved_tms ; altera_reserved_tck ; -0.738 ; -0.876 ; Rise ; altera_reserved_tck ; ; DRAM_DQ[*] ; CLOCK_50 ; -0.451 ; -0.614 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; DRAM_DQ[0] ; CLOCK_50 ; -0.475 ; -0.639 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; DRAM_DQ[1] ; CLOCK_50 ; -0.475 ; -0.639 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; @@ -1317,15 +1317,15 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp ; DRAM_DQ[13] ; CLOCK_50 ; -0.451 ; -0.614 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; DRAM_DQ[14] ; CLOCK_50 ; -0.451 ; -0.614 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; DRAM_DQ[15] ; CLOCK_50 ; -0.474 ; -0.638 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; GPIO_0[*] ; CLOCK_50 ; -3.764 ; -4.303 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; GPIO_0[31] ; CLOCK_50 ; -3.764 ; -4.303 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; KEY[*] ; CLOCK_50 ; -1.574 ; -1.708 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; KEY[1] ; CLOCK_50 ; -1.574 ; -1.708 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; SW[*] ; CLOCK_50 ; -1.296 ; -1.401 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; SW[0] ; CLOCK_50 ; -1.717 ; -1.841 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; SW[1] ; CLOCK_50 ; -1.296 ; -1.401 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; SW[2] ; CLOCK_50 ; -1.360 ; -1.462 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; SW[3] ; CLOCK_50 ; -1.781 ; -1.900 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_0[*] ; CLOCK_50 ; -3.868 ; -4.427 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_0[31] ; CLOCK_50 ; -3.868 ; -4.427 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; KEY[*] ; CLOCK_50 ; -1.335 ; -1.465 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; KEY[1] ; CLOCK_50 ; -1.335 ; -1.465 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; SW[*] ; CLOCK_50 ; -1.295 ; -1.462 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; SW[0] ; CLOCK_50 ; -1.295 ; -1.462 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; SW[1] ; CLOCK_50 ; -1.881 ; -1.909 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; SW[2] ; CLOCK_50 ; -1.590 ; -1.699 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; SW[3] ; CLOCK_50 ; -1.419 ; -1.530 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +---------------------+---------------------+--------+--------+------------+----------------------------------------------------------+ @@ -1334,7 +1334,7 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +---------------------+---------------------+--------+--------+------------+----------------------------------------------------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +---------------------+---------------------+--------+--------+------------+----------------------------------------------------------+ -; altera_reserved_tdo ; altera_reserved_tck ; 10.825 ; 11.491 ; Fall ; altera_reserved_tck ; +; altera_reserved_tdo ; altera_reserved_tck ; 10.941 ; 11.609 ; Fall ; altera_reserved_tck ; ; DRAM_ADDR[*] ; CLOCK_50 ; 3.071 ; 3.042 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; DRAM_ADDR[0] ; CLOCK_50 ; 3.070 ; 3.041 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; DRAM_ADDR[1] ; CLOCK_50 ; 2.995 ; 2.967 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; @@ -1375,20 +1375,20 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp ; DRAM_DQM[0] ; CLOCK_50 ; 2.992 ; 2.964 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; DRAM_DQM[1] ; CLOCK_50 ; 2.992 ; 2.964 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; DRAM_RAS_N ; CLOCK_50 ; 3.079 ; 3.050 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; DRAM_WE_N ; CLOCK_50 ; 3.085 ; 3.056 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; GPIO_0[*] ; CLOCK_50 ; 6.024 ; 6.145 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; GPIO_0[33] ; CLOCK_50 ; 6.024 ; 6.145 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; GPIO_1[*] ; CLOCK_50 ; 4.729 ; 4.710 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; GPIO_1[0] ; CLOCK_50 ; 4.585 ; 4.674 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; GPIO_1[33] ; CLOCK_50 ; 4.729 ; 4.710 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; LED[*] ; CLOCK_50 ; 6.156 ; 6.335 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; LED[0] ; CLOCK_50 ; 4.856 ; 4.934 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; LED[1] ; CLOCK_50 ; 5.079 ; 5.159 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; LED[2] ; CLOCK_50 ; 4.657 ; 4.730 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; LED[3] ; CLOCK_50 ; 4.783 ; 4.843 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; LED[4] ; CLOCK_50 ; 6.068 ; 6.293 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; LED[5] ; CLOCK_50 ; 6.114 ; 6.335 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; LED[6] ; CLOCK_50 ; 6.156 ; 6.186 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_WE_N ; CLOCK_50 ; 3.075 ; 3.046 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_0[*] ; CLOCK_50 ; 5.296 ; 5.355 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_0[33] ; CLOCK_50 ; 5.296 ; 5.355 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_1[*] ; CLOCK_50 ; 5.510 ; 5.696 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_1[0] ; CLOCK_50 ; 5.510 ; 5.696 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_1[33] ; CLOCK_50 ; 5.155 ; 5.166 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[*] ; CLOCK_50 ; 6.097 ; 6.222 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[0] ; CLOCK_50 ; 5.276 ; 5.428 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[1] ; CLOCK_50 ; 5.942 ; 6.107 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[2] ; CLOCK_50 ; 5.578 ; 5.664 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[3] ; CLOCK_50 ; 5.000 ; 5.053 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[4] ; CLOCK_50 ; 4.739 ; 4.787 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[5] ; CLOCK_50 ; 6.097 ; 6.222 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[6] ; CLOCK_50 ; 4.461 ; 4.532 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; DRAM_CLK ; CLOCK_50 ; 1.207 ; ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[1] ; ; DRAM_CLK ; CLOCK_50 ; ; 1.166 ; Fall ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[1] ; ; LED[*] ; CLOCK_50 ; 4.715 ; 4.828 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; @@ -1401,7 +1401,7 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +---------------------+---------------------+-------+-------+------------+----------------------------------------------------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +---------------------+---------------------+-------+-------+------------+----------------------------------------------------------+ -; altera_reserved_tdo ; altera_reserved_tck ; 8.608 ; 9.275 ; Fall ; altera_reserved_tck ; +; altera_reserved_tdo ; altera_reserved_tck ; 8.718 ; 9.387 ; Fall ; altera_reserved_tck ; ; DRAM_ADDR[*] ; CLOCK_50 ; 2.572 ; 2.550 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; DRAM_ADDR[0] ; CLOCK_50 ; 2.670 ; 2.641 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; DRAM_ADDR[1] ; CLOCK_50 ; 2.596 ; 2.568 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; @@ -1442,20 +1442,20 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp ; DRAM_DQM[0] ; CLOCK_50 ; 2.593 ; 2.565 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; DRAM_DQM[1] ; CLOCK_50 ; 2.593 ; 2.565 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; DRAM_RAS_N ; CLOCK_50 ; 2.679 ; 2.650 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; DRAM_WE_N ; CLOCK_50 ; 2.684 ; 2.655 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; GPIO_0[*] ; CLOCK_50 ; 5.433 ; 5.547 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; GPIO_0[33] ; CLOCK_50 ; 5.433 ; 5.547 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; GPIO_1[*] ; CLOCK_50 ; 4.050 ; 4.134 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; GPIO_1[0] ; CLOCK_50 ; 4.050 ; 4.134 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; GPIO_1[33] ; CLOCK_50 ; 4.191 ; 4.173 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; LED[*] ; CLOCK_50 ; 4.120 ; 4.189 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; LED[0] ; CLOCK_50 ; 4.311 ; 4.385 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; LED[1] ; CLOCK_50 ; 4.526 ; 4.601 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; LED[2] ; CLOCK_50 ; 4.120 ; 4.189 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; LED[3] ; CLOCK_50 ; 4.241 ; 4.298 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; LED[4] ; CLOCK_50 ; 5.477 ; 5.691 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; LED[5] ; CLOCK_50 ; 5.568 ; 5.783 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; LED[6] ; CLOCK_50 ; 5.558 ; 5.585 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_WE_N ; CLOCK_50 ; 2.675 ; 2.646 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_0[*] ; CLOCK_50 ; 4.734 ; 4.790 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_0[33] ; CLOCK_50 ; 4.734 ; 4.790 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_1[*] ; CLOCK_50 ; 4.599 ; 4.610 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_1[0] ; CLOCK_50 ; 4.938 ; 5.115 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_1[33] ; CLOCK_50 ; 4.599 ; 4.610 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[*] ; CLOCK_50 ; 3.930 ; 3.997 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[0] ; CLOCK_50 ; 4.715 ; 4.859 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[1] ; CLOCK_50 ; 5.354 ; 5.511 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[2] ; CLOCK_50 ; 5.005 ; 5.086 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[3] ; CLOCK_50 ; 4.450 ; 4.499 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[4] ; CLOCK_50 ; 4.200 ; 4.246 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[5] ; CLOCK_50 ; 5.552 ; 5.675 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[6] ; CLOCK_50 ; 3.930 ; 3.997 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; DRAM_CLK ; CLOCK_50 ; 0.757 ; ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[1] ; ; DRAM_CLK ; CLOCK_50 ; ; 0.718 ; Fall ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[1] ; ; LED[*] ; CLOCK_50 ; 4.224 ; 4.336 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; @@ -1571,7 +1571,7 @@ Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. Number of Synchronizer Chains Found: 6 Shortest Synchronizer Chain: 2 Registers Fraction of Chains for which MTBFs Could Not be Calculated: 0.333 -Worst Case Available Settling Time: 16.778 ns +Worst Case Available Settling Time: 17.228 ns Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8 @@ -1585,8 +1585,8 @@ Typical MTBF values are calculated based on the nominal silicon characteristics, +------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+-------------------------+ ; ; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_rx:the_system_uart_wifi_rx|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 ; Greater than 1 Billion ; Yes ; ; GPIO_1[31] ; system:inst_cpu|system_uart_mc:uart_mc|system_uart_mc_rx:the_system_uart_mc_rx|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 ; Greater than 1 Billion ; Yes ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3|din_s1 ; Greater than 1 Billion ; Yes ; ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer2|din_s1 ; Greater than 1 Billion ; Yes ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3|din_s1 ; Greater than 1 Billion ; Yes ; ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_debug:the_system_cpu_nios2_oci_debug|monitor_ready ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|din_s1 ; n/a ; Yes ; ; system:inst_cpu|system_cpu:cpu|hbreak_enabled ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 ; n/a ; Yes ; +------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+-------------------------+ @@ -1613,7 +1613,7 @@ Synchronizer Chain #1: Typical MTBF is Greater than 1 Billion Years ; Method of Synchronizer Identification ; User Specified ; ; ; ; ; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; ; Number of Synchronization Registers in Chain ; 2 ; ; ; ; -; Available Settling Time (ns) ; 16.778 ; ; ; ; +; Available Settling Time (ns) ; 17.228 ; ; ; ; ; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 12.5 ; ; ; ; ; Source Clock ; ; ; ; ; ; Unknown ; ; ; ; ; @@ -1621,8 +1621,8 @@ Synchronizer Chain #1: Typical MTBF is Greater than 1 Billion Years ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; 10.000 ; 100.0 MHz ; ; ; Asynchronous Source ; ; ; ; ; ; Synchronization Registers ; ; ; ; ; -; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_rx:the_system_uart_wifi_rx|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 ; ; ; ; 9.086 ; -; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_rx:the_system_uart_wifi_rx|altera_std_synchronizer:the_altera_std_synchronizer|dreg[0] ; ; ; ; 7.692 ; +; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_rx:the_system_uart_wifi_rx|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 ; ; ; ; 9.099 ; +; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_rx:the_system_uart_wifi_rx|altera_std_synchronizer:the_altera_std_synchronizer|dreg[0] ; ; ; ; 8.129 ; +-----------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ @@ -1648,7 +1648,7 @@ Synchronizer Chain #2: Typical MTBF is Greater than 1 Billion Years ; Method of Synchronizer Identification ; User Specified ; ; ; ; ; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; ; Number of Synchronization Registers in Chain ; 2 ; ; ; ; -; Available Settling Time (ns) ; 17.889 ; ; ; ; +; Available Settling Time (ns) ; 17.915 ; ; ; ; ; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 12.5 ; ; ; ; ; Source Clock ; ; ; ; ; ; Unknown ; ; ; ; ; @@ -1657,8 +1657,8 @@ Synchronizer Chain #2: Typical MTBF is Greater than 1 Billion Years ; Asynchronous Source ; ; ; ; ; ; GPIO_1[31] ; ; ; ; ; ; Synchronization Registers ; ; ; ; ; -; system:inst_cpu|system_uart_mc:uart_mc|system_uart_mc_rx:the_system_uart_mc_rx|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 ; ; ; ; 8.851 ; -; system:inst_cpu|system_uart_mc:uart_mc|system_uart_mc_rx:the_system_uart_mc_rx|altera_std_synchronizer:the_altera_std_synchronizer|dreg[0] ; ; ; ; 9.038 ; +; system:inst_cpu|system_uart_mc:uart_mc|system_uart_mc_rx:the_system_uart_mc_rx|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 ; ; ; ; 8.878 ; +; system:inst_cpu|system_uart_mc:uart_mc|system_uart_mc_rx:the_system_uart_mc_rx|altera_std_synchronizer:the_altera_std_synchronizer|dreg[0] ; ; ; ; 9.037 ; +---------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ @@ -1671,7 +1671,7 @@ Synchronizer Chain #3: Typical MTBF is Greater than 1 Billion Years ; Property ; Value ; +-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Source Node ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; -; Synchronization Node ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3|din_s1 ; +; Synchronization Node ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer2|din_s1 ; ; Typical MTBF (years) ; Greater than 1 Billion ; ; Included in Design MTBF ; Yes ; +-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ @@ -1684,7 +1684,7 @@ Synchronizer Chain #3: Typical MTBF is Greater than 1 Billion Years ; Method of Synchronizer Identification ; User Specified ; ; ; ; ; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; ; Number of Synchronization Registers in Chain ; 2 ; ; ; ; -; Available Settling Time (ns) ; 18.473 ; ; ; ; +; Available Settling Time (ns) ; 18.450 ; ; ; ; ; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 1.25 ; ; ; ; ; Source Clock ; ; ; ; ; ; altera_reserved_tck ; ; 100.000 ; 10.0 MHz ; ; @@ -1695,8 +1695,8 @@ Synchronizer Chain #3: Typical MTBF is Greater than 1 Billion Years ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; ; ; ; ; ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; ; ; ; ; ; Synchronization Registers ; ; ; ; ; -; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3|din_s1 ; ; ; ; 9.243 ; -; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3|dreg[0] ; ; ; ; 9.230 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer2|din_s1 ; ; ; ; 9.229 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer2|dreg[0] ; ; ; ; 9.221 ; +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ @@ -1709,7 +1709,7 @@ Synchronizer Chain #4: Typical MTBF is Greater than 1 Billion Years ; Property ; Value ; +-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Source Node ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; -; Synchronization Node ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer2|din_s1 ; +; Synchronization Node ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3|din_s1 ; ; Typical MTBF (years) ; Greater than 1 Billion ; ; Included in Design MTBF ; Yes ; +-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ @@ -1722,7 +1722,7 @@ Synchronizer Chain #4: Typical MTBF is Greater than 1 Billion Years ; Method of Synchronizer Identification ; User Specified ; ; ; ; ; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; ; Number of Synchronization Registers in Chain ; 2 ; ; ; ; -; Available Settling Time (ns) ; 18.476 ; ; ; ; +; Available Settling Time (ns) ; 18.450 ; ; ; ; ; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 1.25 ; ; ; ; ; Source Clock ; ; ; ; ; ; altera_reserved_tck ; ; 100.000 ; 10.0 MHz ; ; @@ -1733,8 +1733,8 @@ Synchronizer Chain #4: Typical MTBF is Greater than 1 Billion Years ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; ; ; ; ; ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; ; ; ; ; ; Synchronization Registers ; ; ; ; ; -; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer2|din_s1 ; ; ; ; 9.244 ; -; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer2|dreg[0] ; ; ; ; 9.232 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3|din_s1 ; ; ; ; 9.231 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3|dreg[0] ; ; ; ; 9.219 ; +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ @@ -1816,7 +1816,7 @@ Synchronizer Chain #6: Typical MTBF is n/a Years +------------+-----------------+----------------------------------------------------------+------+ ; Fmax ; Restricted Fmax ; Clock Name ; Note ; +------------+-----------------+----------------------------------------------------------+------+ -; 138.14 MHz ; 138.14 MHz ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; +; 140.25 MHz ; 140.25 MHz ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; ; 436.11 MHz ; 436.11 MHz ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; ; +------------+-----------------+----------------------------------------------------------+------+ This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. @@ -1827,7 +1827,7 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +----------------------------------------------------------+--------+---------------+ ; Clock ; Slack ; End Point TNS ; +----------------------------------------------------------+--------+---------------+ -; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 2.250 ; 0.000 ; +; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 2.461 ; 0.000 ; ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 97.707 ; 0.000 ; +----------------------------------------------------------+--------+---------------+ @@ -1837,7 +1837,7 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +----------------------------------------------------------+-------+---------------+ ; Clock ; Slack ; End Point TNS ; +----------------------------------------------------------+-------+---------------+ -; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.242 ; 0.000 ; +; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.227 ; 0.000 ; ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.320 ; 0.000 ; +----------------------------------------------------------+-------+---------------+ @@ -1847,7 +1847,7 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +----------------------------------------------------------+-------+---------------+ ; Clock ; Slack ; End Point TNS ; +----------------------------------------------------------+-------+---------------+ -; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 2.469 ; 0.000 ; +; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 2.272 ; 0.000 ; +----------------------------------------------------------+-------+---------------+ @@ -1856,7 +1856,7 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +----------------------------------------------------------+-------+---------------+ ; Clock ; Slack ; End Point TNS ; +----------------------------------------------------------+-------+---------------+ -; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 1.807 ; 0.000 ; +; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 2.259 ; 0.000 ; +----------------------------------------------------------+-------+---------------+ @@ -1865,9 +1865,9 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +----------------------------------------------------------+--------+---------------+ ; Clock ; Slack ; End Point TNS ; +----------------------------------------------------------+--------+---------------+ -; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 4.719 ; 0.000 ; +; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 4.716 ; 0.000 ; ; CLOCK_50 ; 9.818 ; 0.000 ; -; altera_reserved_tck ; 49.604 ; 0.000 ; +; altera_reserved_tck ; 49.608 ; 0.000 ; ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 49.744 ; 0.000 ; +----------------------------------------------------------+--------+---------------+ @@ -1877,106 +1877,106 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +-------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ -; 2.250 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.072 ; 2.673 ; -; 2.252 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[20] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.072 ; 2.671 ; -; 2.264 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[24] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.072 ; 2.659 ; -; 2.374 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.072 ; 2.549 ; -; 2.376 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[16] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.072 ; 2.547 ; -; 2.377 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[28] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.072 ; 2.546 ; -; 2.378 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.072 ; 2.545 ; -; 2.419 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[29] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.065 ; 2.511 ; -; 2.464 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[25] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.065 ; 2.466 ; -; 2.480 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[13] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[25] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.074 ; 2.441 ; -; 2.502 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.072 ; 2.421 ; -; 2.569 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[25] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.065 ; 2.361 ; -; 2.579 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[13] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.074 ; 2.342 ; -; 2.631 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[29] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.065 ; 2.299 ; -; 2.641 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[26] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.070 ; 2.284 ; -; 2.671 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[27] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.074 ; 2.250 ; -; 2.684 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.068 ; 2.243 ; -; 2.692 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.068 ; 2.235 ; -; 2.693 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[25] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.068 ; 2.234 ; -; 2.716 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[27] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.077 ; 2.202 ; -; 2.739 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[27] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.074 ; 2.182 ; -; 2.741 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[26] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[6] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.070 ; 2.184 ; -; 2.761 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.089 ; 7.145 ; -; 2.761 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.089 ; 7.145 ; -; 2.802 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.084 ; 7.109 ; -; 2.802 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.084 ; 7.109 ; -; 2.802 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.084 ; 7.109 ; -; 2.803 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[26] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.085 ; 7.107 ; -; 2.803 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[40] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.085 ; 7.107 ; -; 2.803 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[27] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.085 ; 7.107 ; -; 2.803 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[28] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.085 ; 7.107 ; -; 2.803 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[29] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.085 ; 7.107 ; -; 2.803 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[35] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.085 ; 7.107 ; -; 2.803 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[32] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.085 ; 7.107 ; -; 2.803 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[33] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.085 ; 7.107 ; -; 2.810 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[5] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.090 ; 7.095 ; -; 2.810 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[5] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.090 ; 7.095 ; -; 2.813 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.077 ; 7.105 ; -; 2.813 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.077 ; 7.105 ; -; 2.813 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.077 ; 7.105 ; -; 2.813 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.077 ; 7.105 ; -; 2.814 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.077 ; 7.104 ; -; 2.814 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[22] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.077 ; 7.104 ; -; 2.814 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[23] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.077 ; 7.104 ; -; 2.814 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[24] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.077 ; 7.104 ; -; 2.814 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[25] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.077 ; 7.104 ; -; 2.814 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[3] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.090 ; 7.091 ; -; 2.814 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[3] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.090 ; 7.091 ; -; 2.815 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[36] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.070 ; 7.110 ; -; 2.815 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[37] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.070 ; 7.110 ; -; 2.815 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[34] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.070 ; 7.110 ; -; 2.815 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[39] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.070 ; 7.110 ; -; 2.815 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[38] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.070 ; 7.110 ; -; 2.815 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.070 ; 7.110 ; -; 2.815 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[20] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.070 ; 7.110 ; -; 2.834 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.077 ; 2.084 ; -; 2.835 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[6] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.076 ; 7.084 ; -; 2.835 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.076 ; 7.084 ; -; 2.835 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.076 ; 7.084 ; -; 2.841 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_cpu:cpu|d_writedata[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.078 ; 7.076 ; -; 2.841 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_cpu:cpu|d_writedata[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.078 ; 7.076 ; -; 2.841 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_cpu:cpu|d_writedata[31] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.078 ; 7.076 ; -; 2.841 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_cpu:cpu|d_writedata[28] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.078 ; 7.076 ; -; 2.841 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_cpu:cpu|d_writedata[27] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.078 ; 7.076 ; -; 2.841 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_cpu:cpu|d_writedata[25] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.078 ; 7.076 ; -; 2.841 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_cpu:cpu|d_writedata[22] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.078 ; 7.076 ; -; 2.841 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_cpu:cpu|d_writedata[20] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.078 ; 7.076 ; -; 2.841 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_cpu:cpu|d_writedata[16] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.078 ; 7.076 ; -; 2.842 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[30] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.084 ; 7.069 ; -; 2.842 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[31] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.084 ; 7.069 ; -; 2.842 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.084 ; 7.069 ; -; 2.843 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[5] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.085 ; 7.067 ; -; 2.843 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[5] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.085 ; 7.067 ; -; 2.843 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[5] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.085 ; 7.067 ; -; 2.847 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[3] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.085 ; 7.063 ; -; 2.847 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[3] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.085 ; 7.063 ; -; 2.847 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[3] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.085 ; 7.063 ; -; 2.853 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[5] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.078 ; 7.064 ; -; 2.853 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[5] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[22] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.078 ; 7.064 ; -; 2.853 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[5] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[23] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.078 ; 7.064 ; -; 2.853 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[5] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[24] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.078 ; 7.064 ; -; 2.853 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[5] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[25] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.078 ; 7.064 ; -; 2.856 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[5] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.078 ; 7.061 ; -; 2.856 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[5] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.078 ; 7.061 ; -; 2.856 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[5] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.078 ; 7.061 ; -; 2.856 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[5] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.078 ; 7.061 ; -; 2.857 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[3] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.078 ; 7.060 ; -; 2.857 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[3] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[22] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.078 ; 7.060 ; -; 2.857 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[3] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[23] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.078 ; 7.060 ; -; 2.857 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[3] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[24] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.078 ; 7.060 ; -; 2.857 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[3] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[25] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.078 ; 7.060 ; -; 2.858 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[17] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.068 ; 2.069 ; -; 2.858 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[29] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.068 ; 2.069 ; -; 2.859 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.068 ; 2.068 ; -; 2.860 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[3] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.078 ; 7.057 ; -; 2.860 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[3] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.078 ; 7.057 ; -; 2.860 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[3] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.078 ; 7.057 ; -; 2.860 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[3] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.078 ; 7.057 ; -; 2.860 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.068 ; 2.067 ; -; 2.861 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.068 ; 2.066 ; +; 2.461 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[30] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[6] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.097 ; 2.437 ; +; 2.507 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[30] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.097 ; 2.391 ; +; 2.535 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[31] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.067 ; 2.393 ; +; 2.542 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.067 ; 2.386 ; +; 2.551 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[27] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.067 ; 2.377 ; +; 2.594 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.067 ; 2.334 ; +; 2.675 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.067 ; 2.253 ; +; 2.758 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.067 ; 2.170 ; +; 2.787 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[19] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[27] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.059 ; 2.149 ; +; 2.793 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[24] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.064 ; 2.138 ; +; 2.796 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.067 ; 2.132 ; +; 2.797 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[23] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.067 ; 2.131 ; +; 2.802 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[20] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.064 ; 2.129 ; +; 2.811 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.064 ; 2.120 ; +; 2.816 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.064 ; 2.115 ; +; 2.828 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[26] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.097 ; 2.070 ; +; 2.851 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[25] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.099 ; 2.045 ; +; 2.870 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[8] ; system:inst_cpu|system_cpu:cpu|d_address_offset_field[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.063 ; 7.062 ; +; 2.870 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[8] ; system:inst_cpu|system_cpu:cpu|d_address_offset_field[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.063 ; 7.062 ; +; 2.870 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[8] ; system:inst_cpu|system_cpu:cpu|d_address_offset_field[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.063 ; 7.062 ; +; 2.876 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[7] ; system:inst_cpu|system_cpu:cpu|d_address_offset_field[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.063 ; 7.056 ; +; 2.876 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[7] ; system:inst_cpu|system_cpu:cpu|d_address_offset_field[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.063 ; 7.056 ; +; 2.876 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[7] ; system:inst_cpu|system_cpu:cpu|d_address_offset_field[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.063 ; 7.056 ; +; 2.877 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[24] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.083 ; 2.035 ; +; 2.888 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[8] ; system:inst_cpu|system_cpu:cpu|d_writedata[25] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.052 ; 7.055 ; +; 2.888 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[8] ; system:inst_cpu|system_cpu:cpu|d_writedata[22] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.052 ; 7.055 ; +; 2.888 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[8] ; system:inst_cpu|system_cpu:cpu|d_writedata[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.052 ; 7.055 ; +; 2.888 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[8] ; system:inst_cpu|system_cpu:cpu|d_writedata[20] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.052 ; 7.055 ; +; 2.888 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[8] ; system:inst_cpu|system_cpu:cpu|d_writedata[18] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.052 ; 7.055 ; +; 2.892 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_cpu:cpu|d_address_offset_field[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.063 ; 7.040 ; +; 2.892 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_cpu:cpu|d_address_offset_field[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.063 ; 7.040 ; +; 2.892 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_cpu:cpu|d_address_offset_field[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.063 ; 7.040 ; +; 2.894 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[7] ; system:inst_cpu|system_cpu:cpu|d_writedata[25] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.052 ; 7.049 ; +; 2.894 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[7] ; system:inst_cpu|system_cpu:cpu|d_writedata[22] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.052 ; 7.049 ; +; 2.894 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[7] ; system:inst_cpu|system_cpu:cpu|d_writedata[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.052 ; 7.049 ; +; 2.894 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[7] ; system:inst_cpu|system_cpu:cpu|d_writedata[20] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.052 ; 7.049 ; +; 2.894 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[7] ; system:inst_cpu|system_cpu:cpu|d_writedata[18] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.052 ; 7.049 ; +; 2.894 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[29] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.099 ; 2.002 ; +; 2.903 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[26] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[6] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.097 ; 1.995 ; +; 2.910 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_cpu:cpu|d_writedata[25] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.052 ; 7.033 ; +; 2.910 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_cpu:cpu|d_writedata[22] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.052 ; 7.033 ; +; 2.910 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_cpu:cpu|d_writedata[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.052 ; 7.033 ; +; 2.910 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_cpu:cpu|d_writedata[20] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.052 ; 7.033 ; +; 2.910 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_cpu:cpu|d_writedata[18] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.052 ; 7.033 ; +; 2.912 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[8] ; system:inst_cpu|system_cpu:cpu|d_writedata[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.050 ; 7.033 ; +; 2.912 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[8] ; system:inst_cpu|system_cpu:cpu|d_writedata[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.050 ; 7.033 ; +; 2.912 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[8] ; system:inst_cpu|system_cpu:cpu|d_writedata[30] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.050 ; 7.033 ; +; 2.912 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[8] ; system:inst_cpu|system_cpu:cpu|d_writedata[29] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.050 ; 7.033 ; +; 2.912 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[8] ; system:inst_cpu|system_cpu:cpu|d_writedata[27] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.050 ; 7.033 ; +; 2.912 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[8] ; system:inst_cpu|system_cpu:cpu|d_writedata[26] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.050 ; 7.033 ; +; 2.912 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[8] ; system:inst_cpu|system_cpu:cpu|d_writedata[24] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.050 ; 7.033 ; +; 2.912 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[8] ; system:inst_cpu|system_cpu:cpu|d_writedata[23] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.050 ; 7.033 ; +; 2.912 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[8] ; system:inst_cpu|system_cpu:cpu|d_writedata[17] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.050 ; 7.033 ; +; 2.918 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[7] ; system:inst_cpu|system_cpu:cpu|d_writedata[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.050 ; 7.027 ; +; 2.918 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[7] ; system:inst_cpu|system_cpu:cpu|d_writedata[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.050 ; 7.027 ; +; 2.918 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[7] ; system:inst_cpu|system_cpu:cpu|d_writedata[30] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.050 ; 7.027 ; +; 2.918 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[7] ; system:inst_cpu|system_cpu:cpu|d_writedata[29] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.050 ; 7.027 ; +; 2.918 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[7] ; system:inst_cpu|system_cpu:cpu|d_writedata[27] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.050 ; 7.027 ; +; 2.918 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[7] ; system:inst_cpu|system_cpu:cpu|d_writedata[26] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.050 ; 7.027 ; +; 2.918 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[7] ; system:inst_cpu|system_cpu:cpu|d_writedata[24] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.050 ; 7.027 ; +; 2.918 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[7] ; system:inst_cpu|system_cpu:cpu|d_writedata[23] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.050 ; 7.027 ; +; 2.918 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[7] ; system:inst_cpu|system_cpu:cpu|d_writedata[17] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.050 ; 7.027 ; +; 2.923 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[16] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.064 ; 2.008 ; +; 2.928 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[27] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.086 ; 1.981 ; +; 2.928 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[28] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.064 ; 2.003 ; +; 2.928 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[6] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[14] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.080 ; 1.987 ; +; 2.930 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[35] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.042 ; 7.023 ; +; 2.930 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[34] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.042 ; 7.023 ; +; 2.930 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[33] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.042 ; 7.023 ; +; 2.930 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[32] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.042 ; 7.023 ; +; 2.930 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[37] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.042 ; 7.023 ; +; 2.930 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[36] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.042 ; 7.023 ; +; 2.930 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[31] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.042 ; 7.023 ; +; 2.930 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[30] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.042 ; 7.023 ; +; 2.932 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_cpu:cpu|d_writedata[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.050 ; 7.013 ; +; 2.932 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_cpu:cpu|d_writedata[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.050 ; 7.013 ; +; 2.932 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_cpu:cpu|d_writedata[30] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.050 ; 7.013 ; +; 2.932 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_cpu:cpu|d_writedata[29] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.050 ; 7.013 ; +; 2.932 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_cpu:cpu|d_writedata[27] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.050 ; 7.013 ; +; 2.932 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_cpu:cpu|d_writedata[26] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.050 ; 7.013 ; +; 2.932 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_cpu:cpu|d_writedata[24] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.050 ; 7.013 ; +; 2.932 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_cpu:cpu|d_writedata[23] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.050 ; 7.013 ; +; 2.932 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[13] ; system:inst_cpu|system_cpu:cpu|d_writedata[17] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.050 ; 7.013 ; +; 2.939 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.064 ; 1.992 ; +; 2.941 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.064 ; 1.990 ; +; 2.943 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[23] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.059 ; 1.993 ; +; 2.947 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[5] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.082 ; 1.966 ; +; 2.960 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[23] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[31] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.059 ; 1.976 ; +; 2.965 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[29] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.099 ; 1.931 ; +; 2.979 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[6] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[18] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.080 ; 1.936 ; +; 2.983 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[8] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[35] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.042 ; 6.970 ; +; 2.983 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[8] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[34] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.042 ; 6.970 ; +; 2.983 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[8] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[33] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.042 ; 6.970 ; +; 2.983 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[8] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[32] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.042 ; 6.970 ; +; 2.983 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[8] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[37] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.042 ; 6.970 ; +; 2.983 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[8] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[36] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.042 ; 6.970 ; +; 2.983 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[8] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[31] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.042 ; 6.970 ; +; 2.983 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[8] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[30] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.042 ; 6.970 ; +; 2.983 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[7] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[35] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.042 ; 6.970 ; +; 2.983 ; system:inst_cpu|system_cpu:cpu|d_address_tag_field[7] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entry_0[34] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.042 ; 6.970 ; +-------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ @@ -2093,106 +2093,106 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ -; 0.242 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[10] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.347 ; 0.758 ; -; 0.253 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[5] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a0~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.348 ; 0.770 ; -; 0.288 ; system:inst_cpu|system_cpu:cpu|M_bht_ptr_unfiltered[0] ; system:inst_cpu|system_cpu:cpu|system_cpu_bht_module:system_cpu_bht|altsyncram:the_altsyncram|altsyncram_fhg1:auto_generated|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.342 ; 0.799 ; -; 0.290 ; system:inst_cpu|system_cpu:cpu|ic_tag_wraddress[7] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.340 ; 0.799 ; -; 0.290 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|data_to_uart[0] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.341 ; 0.800 ; -; 0.291 ; system:inst_cpu|system_cpu:cpu|M_bht_ptr_unfiltered[3] ; system:inst_cpu|system_cpu:cpu|system_cpu_bht_module:system_cpu_bht|altsyncram:the_altsyncram|altsyncram_fhg1:auto_generated|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.342 ; 0.802 ; -; 0.293 ; system:inst_cpu|system_cpu:cpu|ic_tag_wraddress[5] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.340 ; 0.802 ; -; 0.296 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[8] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.345 ; 0.810 ; -; 0.296 ; system:inst_cpu|system_cpu:cpu|A_dc_wb_rd_addr_offset[2] ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_victim_module:system_cpu_dc_victim|altsyncram:the_altsyncram|altsyncram_r3d1:auto_generated|ram_block1a0~portb_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.340 ; 0.805 ; -; 0.296 ; system:inst_cpu|system_cpu:cpu|A_dc_xfer_wr_data[3] ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_victim_module:system_cpu_dc_victim|altsyncram:the_altsyncram|altsyncram_r3d1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.344 ; 0.809 ; -; 0.296 ; system:inst_cpu|system_cpu:cpu|M_bht_ptr_unfiltered[4] ; system:inst_cpu|system_cpu:cpu|system_cpu_bht_module:system_cpu_bht|altsyncram:the_altsyncram|altsyncram_fhg1:auto_generated|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.337 ; 0.802 ; -; 0.298 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|data_in_shift_reg[1] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.342 ; 0.809 ; -; 0.299 ; system:inst_cpu|system_cpu:cpu|M_bht_ptr_unfiltered[5] ; system:inst_cpu|system_cpu:cpu|system_cpu_bht_module:system_cpu_bht|altsyncram:the_altsyncram|altsyncram_fhg1:auto_generated|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.342 ; 0.810 ; -; 0.299 ; system:inst_cpu|system_cpu:cpu|ic_fill_valid_bits[2] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.342 ; 0.810 ; -; 0.301 ; system:inst_cpu|system_cpu:cpu|A_dc_wb_rd_addr_offset[1] ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_victim_module:system_cpu_dc_victim|altsyncram:the_altsyncram|altsyncram_r3d1:auto_generated|ram_block1a0~portb_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.340 ; 0.810 ; -; 0.301 ; system:inst_cpu|system_cpu:cpu|ic_fill_valid_bits[7] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.342 ; 0.812 ; -; 0.303 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[6] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a0~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.347 ; 0.819 ; -; 0.304 ; system:inst_cpu|system_cpu:cpu|ic_fill_valid_bits[1] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.342 ; 0.815 ; -; 0.306 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[14] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.345 ; 0.820 ; -; 0.306 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|data_in_shift_reg[2] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.342 ; 0.817 ; -; 0.307 ; system:inst_cpu|system_cpu:cpu|ic_fill_tag[7] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.346 ; 0.822 ; -; 0.307 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|data_in_shift_reg[5] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.342 ; 0.818 ; -; 0.307 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[0] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.338 ; 0.814 ; -; 0.308 ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[2] ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.340 ; 0.817 ; -; 0.308 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[20] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a0~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.346 ; 0.823 ; -; 0.308 ; system:inst_cpu|system_cpu:cpu|i_readdata_d1[16] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a9~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.342 ; 0.819 ; -; 0.309 ; system:inst_cpu|system_cpu:cpu|ic_fill_tag[4] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.346 ; 0.824 ; -; 0.309 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[3] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.340 ; 0.818 ; -; 0.309 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|data_in_shift_reg[7] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.342 ; 0.820 ; -; 0.309 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[2] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.338 ; 0.816 ; -; 0.310 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[30] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.345 ; 0.824 ; -; 0.310 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[16] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a0~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.346 ; 0.825 ; -; 0.311 ; system:inst_cpu|altera_merlin_slave_translator:sysid_control_slave_translator|wait_latency_counter[1] ; system:inst_cpu|altera_merlin_slave_translator:sysid_control_slave_translator|wait_latency_counter[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.511 ; -; 0.311 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_debug:the_system_cpu_nios2_oci_debug|resetlatch ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_debug:the_system_cpu_nios2_oci_debug|resetlatch ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.511 ; -; 0.311 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[26] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.345 ; 0.825 ; -; 0.311 ; system:inst_cpu|system_cpu:cpu|ic_fill_ap_cnt[1] ; system:inst_cpu|system_cpu:cpu|ic_fill_ap_cnt[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.511 ; -; 0.311 ; system:inst_cpu|system_cpu:cpu|ic_fill_ap_cnt[2] ; system:inst_cpu|system_cpu:cpu|ic_fill_ap_cnt[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.511 ; -; 0.311 ; system:inst_cpu|system_cpu:cpu|i_read ; system:inst_cpu|system_cpu:cpu|i_read ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.511 ; -; 0.311 ; system:inst_cpu|altera_merlin_traffic_limiter:limiter|has_pending_responses ; system:inst_cpu|altera_merlin_traffic_limiter:limiter|has_pending_responses ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.511 ; -; 0.311 ; system:inst_cpu|system_sdram:sdram|m_count[0] ; system:inst_cpu|system_sdram:sdram|m_count[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.511 ; -; 0.311 ; system:inst_cpu|system_sdram:sdram|m_state.000100000 ; system:inst_cpu|system_sdram:sdram|m_state.000100000 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.511 ; -; 0.311 ; system:inst_cpu|system_sdram:sdram|i_next.000 ; system:inst_cpu|system_sdram:sdram|i_next.000 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.511 ; -; 0.311 ; system:inst_cpu|system_sdram:sdram|i_refs[0] ; system:inst_cpu|system_sdram:sdram|i_refs[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.511 ; -; 0.311 ; system:inst_cpu|system_sdram:sdram|i_refs[1] ; system:inst_cpu|system_sdram:sdram|i_refs[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.511 ; -; 0.311 ; system:inst_cpu|system_sdram:sdram|i_refs[2] ; system:inst_cpu|system_sdram:sdram|i_refs[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.511 ; -; 0.311 ; system:inst_cpu|system_sdram:sdram|i_state.000 ; system:inst_cpu|system_sdram:sdram|i_state.000 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.511 ; -; 0.311 ; system:inst_cpu|system_sdram:sdram|i_cmd[2] ; system:inst_cpu|system_sdram:sdram|i_cmd[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.511 ; -; 0.311 ; system:inst_cpu|system_sdram:sdram|i_next.101 ; system:inst_cpu|system_sdram:sdram|i_next.101 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.511 ; +; 0.227 ; system:inst_cpu|system_cpu:cpu|ic_fill_valid_bits[0] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.341 ; 0.737 ; +; 0.228 ; system:inst_cpu|system_cpu:cpu|ic_fill_valid_bits[5] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.341 ; 0.738 ; +; 0.230 ; system:inst_cpu|system_cpu:cpu|ic_fill_valid_bits[2] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.341 ; 0.740 ; +; 0.286 ; system:inst_cpu|system_cpu:cpu|M_bht_ptr_unfiltered[0] ; system:inst_cpu|system_cpu:cpu|system_cpu_bht_module:system_cpu_bht|altsyncram:the_altsyncram|altsyncram_fhg1:auto_generated|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.339 ; 0.794 ; +; 0.287 ; system:inst_cpu|system_cpu:cpu|M_bht_ptr_unfiltered[1] ; system:inst_cpu|system_cpu:cpu|system_cpu_bht_module:system_cpu_bht|altsyncram:the_altsyncram|altsyncram_fhg1:auto_generated|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.339 ; 0.795 ; +; 0.292 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[4] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a0~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.345 ; 0.806 ; +; 0.294 ; system:inst_cpu|system_cpu:cpu|M_bht_ptr_unfiltered[3] ; system:inst_cpu|system_cpu:cpu|system_cpu_bht_module:system_cpu_bht|altsyncram:the_altsyncram|altsyncram_fhg1:auto_generated|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.339 ; 0.802 ; +; 0.297 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[2] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.340 ; 0.806 ; +; 0.298 ; system:inst_cpu|system_cpu:cpu|i_readdata_d1[2] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.345 ; 0.812 ; +; 0.299 ; system:inst_cpu|system_cpu:cpu|M_bht_ptr_unfiltered[4] ; system:inst_cpu|system_cpu:cpu|system_cpu_bht_module:system_cpu_bht|altsyncram:the_altsyncram|altsyncram_fhg1:auto_generated|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.339 ; 0.807 ; +; 0.301 ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[1] ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.348 ; 0.818 ; +; 0.301 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[8] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.348 ; 0.818 ; +; 0.302 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[4] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.340 ; 0.811 ; +; 0.302 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[6] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a0~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.347 ; 0.818 ; +; 0.302 ; system:inst_cpu|system_cpu:cpu|i_readdata_d1[0] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.341 ; 0.812 ; +; 0.303 ; system:inst_cpu|system_cpu:cpu|i_readdata_d1[20] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a18~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.342 ; 0.814 ; +; 0.304 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[26] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.342 ; 0.815 ; +; 0.304 ; system:inst_cpu|system_cpu:cpu|ic_fill_valid_bits[7] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.341 ; 0.814 ; +; 0.305 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[3] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.340 ; 0.814 ; +; 0.305 ; system:inst_cpu|system_cpu:cpu|i_readdata_d1[31] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a22~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.341 ; 0.815 ; +; 0.305 ; system:inst_cpu|system_cpu:cpu|i_readdata_d1[21] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a18~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.342 ; 0.816 ; +; 0.305 ; system:inst_cpu|system_cpu:cpu|ic_fill_valid_bits[1] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.341 ; 0.815 ; +; 0.306 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[0] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.340 ; 0.815 ; +; 0.306 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|data_in_shift_reg[4] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.344 ; 0.819 ; +; 0.306 ; system:inst_cpu|system_cpu:cpu|i_readdata_d1[18] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a18~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.342 ; 0.817 ; +; 0.306 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[25] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.342 ; 0.817 ; +; 0.307 ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[0] ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.348 ; 0.824 ; +; 0.307 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|data_in_shift_reg[7] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.344 ; 0.820 ; +; 0.307 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[1] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.340 ; 0.816 ; +; 0.307 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|data_to_uart[6] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.341 ; 0.817 ; +; 0.307 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[28] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.342 ; 0.818 ; +; 0.307 ; system:inst_cpu|system_cpu:cpu|i_readdata_d1[1] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.341 ; 0.817 ; +; 0.308 ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[4] ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.348 ; 0.825 ; +; 0.308 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[1] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.340 ; 0.817 ; +; 0.308 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|data_in_shift_reg[1] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.344 ; 0.821 ; +; 0.309 ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[2] ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.337 ; 0.815 ; +; 0.309 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[12] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.345 ; 0.823 ; +; 0.309 ; system:inst_cpu|system_cpu:cpu|i_readdata_d1[3] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.346 ; 0.824 ; +; 0.311 ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.511 ; +; 0.311 ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|b_full ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|b_full ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.511 ; +; 0.311 ; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_tx:the_system_uart_wifi_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[9] ; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_tx:the_system_uart_wifi_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.511 ; +; 0.311 ; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_tx:the_system_uart_wifi_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[0] ; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_tx:the_system_uart_wifi_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.511 ; +; 0.311 ; system:inst_cpu|system_uart_mc:uart_mc|system_uart_mc_tx:the_system_uart_mc_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[9] ; system:inst_cpu|system_uart_mc:uart_mc|system_uart_mc_tx:the_system_uart_mc_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.511 ; +; 0.311 ; system:inst_cpu|system_uart_mc:uart_mc|system_uart_mc_tx:the_system_uart_mc_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[0] ; system:inst_cpu|system_uart_mc:uart_mc|system_uart_mc_tx:the_system_uart_mc_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.511 ; +; 0.311 ; system:inst_cpu|system_pio_led:pio_led|data_out[6] ; system:inst_cpu|system_pio_led:pio_led|data_out[6] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.511 ; +; 0.311 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[6] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.340 ; 0.820 ; +; 0.311 ; system:inst_cpu|system_pio_led:pio_led|data_out[5] ; system:inst_cpu|system_pio_led:pio_led|data_out[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.511 ; +; 0.311 ; system:inst_cpu|system_pio_led:pio_led|data_out[4] ; system:inst_cpu|system_pio_led:pio_led|data_out[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.511 ; +; 0.311 ; system:inst_cpu|system_pio_led:pio_led|data_out[3] ; system:inst_cpu|system_pio_led:pio_led|data_out[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.511 ; +; 0.311 ; system:inst_cpu|system_pio_led:pio_led|data_out[2] ; system:inst_cpu|system_pio_led:pio_led|data_out[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.511 ; +; 0.311 ; system:inst_cpu|system_pio_led:pio_led|data_out[1] ; system:inst_cpu|system_pio_led:pio_led|data_out[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.511 ; +; 0.311 ; system:inst_cpu|system_pio_led:pio_led|data_out[0] ; system:inst_cpu|system_pio_led:pio_led|data_out[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.511 ; +; 0.311 ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[7] ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.511 ; +; 0.311 ; system:inst_cpu|system_cpu:cpu|A_dc_fill_has_started ; system:inst_cpu|system_cpu:cpu|A_dc_fill_has_started ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.511 ; +; 0.311 ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[13] ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.511 ; +; 0.311 ; system:inst_cpu|system_uart_mc:uart_mc|system_uart_mc_rx:the_system_uart_mc_rx|framing_error ; system:inst_cpu|system_uart_mc:uart_mc|system_uart_mc_rx:the_system_uart_mc_rx|framing_error ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.511 ; +; 0.311 ; system:inst_cpu|system_uart_mc:uart_mc|system_uart_mc_rx:the_system_uart_mc_rx|rx_overrun ; system:inst_cpu|system_uart_mc:uart_mc|system_uart_mc_rx:the_system_uart_mc_rx|rx_overrun ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.511 ; +; 0.311 ; system:inst_cpu|system_uart_mc:uart_mc|system_uart_mc_rx:the_system_uart_mc_rx|break_detect ; system:inst_cpu|system_uart_mc:uart_mc|system_uart_mc_rx:the_system_uart_mc_rx|break_detect ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.511 ; +; 0.311 ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[11] ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.511 ; +; 0.311 ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[10] ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.511 ; +; 0.311 ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[5] ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.511 ; +; 0.311 ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[1] ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.511 ; +; 0.311 ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|wr_address ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|wr_address ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.511 ; +; 0.311 ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entries[0] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entries[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.511 ; +; 0.311 ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entries[1] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entries[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.511 ; +; 0.311 ; system:inst_cpu|system_cpu:cpu|A_dc_fill_active ; system:inst_cpu|system_cpu:cpu|A_dc_fill_active ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.511 ; +; 0.311 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[0] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a0~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.347 ; 0.827 ; +; 0.311 ; system:inst_cpu|system_cpu:cpu|A_ld_bypass_delayed_started ; system:inst_cpu|system_cpu:cpu|A_ld_bypass_delayed_started ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.511 ; +; 0.311 ; system:inst_cpu|system_cpu:cpu|A_st_bypass_delayed_started ; system:inst_cpu|system_cpu:cpu|A_st_bypass_delayed_started ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.511 ; ; 0.311 ; system:inst_cpu|system_sdram:sdram|init_done ; system:inst_cpu|system_sdram:sdram|init_done ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.511 ; -; 0.311 ; system:inst_cpu|system_sdram:sdram|m_state.000000100 ; system:inst_cpu|system_sdram:sdram|m_state.000000100 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.511 ; -; 0.311 ; system:inst_cpu|altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][83] ; system:inst_cpu|altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][83] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.511 ; -; 0.311 ; system:inst_cpu|altera_avalon_sc_fifo:pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0] ; system:inst_cpu|altera_avalon_sc_fifo:pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.511 ; -; 0.311 ; system:inst_cpu|altera_avalon_sc_fifo:pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; system:inst_cpu|altera_avalon_sc_fifo:pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.511 ; -; 0.311 ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|rvalid ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|rvalid ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.511 ; -; 0.311 ; system:inst_cpu|altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][102] ; system:inst_cpu|altera_avalon_sc_fifo:cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][102] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.511 ; -; 0.311 ; system:inst_cpu|altera_avalon_sc_fifo:pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][102] ; system:inst_cpu|altera_avalon_sc_fifo:pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][102] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.511 ; -; 0.311 ; system:inst_cpu|altera_avalon_sc_fifo:pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][102] ; system:inst_cpu|altera_avalon_sc_fifo:pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][102] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.511 ; -; 0.311 ; system:inst_cpu|altera_merlin_traffic_limiter:limiter_001|pending_response_count[0] ; system:inst_cpu|altera_merlin_traffic_limiter:limiter_001|pending_response_count[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.511 ; -; 0.311 ; system:inst_cpu|altera_merlin_traffic_limiter:limiter_001|has_pending_responses ; system:inst_cpu|altera_merlin_traffic_limiter:limiter_001|has_pending_responses ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.511 ; -; 0.311 ; system:inst_cpu|altera_merlin_slave_translator:pio_sw_s1_translator|wait_latency_counter[1] ; system:inst_cpu|altera_merlin_slave_translator:pio_sw_s1_translator|wait_latency_counter[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.511 ; -; 0.312 ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entries[1] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entries[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.311 ; system:inst_cpu|system_sdram:sdram|ack_refresh_request ; system:inst_cpu|system_sdram:sdram|ack_refresh_request ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.511 ; +; 0.311 ; system:inst_cpu|system_sdram:sdram|refresh_request ; system:inst_cpu|system_sdram:sdram|refresh_request ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.511 ; +; 0.311 ; system:inst_cpu|system_cpu:cpu|A_dc_xfer_rd_addr_has_started ; system:inst_cpu|system_cpu:cpu|A_dc_xfer_rd_addr_has_started ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.511 ; +; 0.311 ; system:inst_cpu|system_cpu:cpu|A_dc_xfer_rd_addr_offset[1] ; system:inst_cpu|system_cpu:cpu|A_dc_xfer_rd_addr_offset[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.511 ; +; 0.311 ; system:inst_cpu|system_cpu:cpu|A_dc_xfer_rd_addr_offset[2] ; system:inst_cpu|system_cpu:cpu|A_dc_xfer_rd_addr_offset[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.511 ; +; 0.311 ; system:inst_cpu|system_cpu:cpu|A_dc_xfer_rd_addr_active ; system:inst_cpu|system_cpu:cpu|A_dc_xfer_rd_addr_active ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.511 ; +; 0.311 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|low_addressa[3] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|low_addressa[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 0.511 ; +; 0.312 ; system:inst_cpu|system_cpu:cpu|A_dc_wr_data_cnt[1] ; system:inst_cpu|system_cpu:cpu|A_dc_wr_data_cnt[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; system:inst_cpu|system_cpu:cpu|A_dc_wr_data_cnt[2] ; system:inst_cpu|system_cpu:cpu|A_dc_wr_data_cnt[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; system:inst_cpu|system_cpu:cpu|A_dc_wb_wr_active ; system:inst_cpu|system_cpu:cpu|A_dc_wb_wr_active ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; system:inst_cpu|system_cpu:cpu|A_dc_wb_active ; system:inst_cpu|system_cpu:cpu|A_dc_wb_active ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; system:inst_cpu|altera_merlin_slave_translator:uart_wifi_s1_translator|wait_latency_counter[1] ; system:inst_cpu|altera_merlin_slave_translator:uart_wifi_s1_translator|wait_latency_counter[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; system:inst_cpu|altera_avalon_sc_fifo:uart_wifi_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0] ; system:inst_cpu|altera_avalon_sc_fifo:uart_wifi_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; system:inst_cpu|altera_avalon_sc_fifo:uart_wifi_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; system:inst_cpu|altera_avalon_sc_fifo:uart_wifi_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; system:inst_cpu|system_cpu:cpu|A_dc_wb_rd_addr_offset[1] ; system:inst_cpu|system_cpu:cpu|A_dc_wb_rd_addr_offset[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; system:inst_cpu|system_cpu:cpu|A_dc_wb_rd_addr_offset[2] ; system:inst_cpu|system_cpu:cpu|A_dc_wb_rd_addr_offset[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; ; 0.312 ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; ; 0.312 ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|b_full ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|b_full ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; -; 0.312 ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|b_full ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|b_full ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; -; 0.312 ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; -; 0.312 ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[13] ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; -; 0.312 ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[11] ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; -; 0.312 ; system:inst_cpu|altera_avalon_sc_fifo:sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0] ; system:inst_cpu|altera_avalon_sc_fifo:sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; -; 0.312 ; system:inst_cpu|altera_avalon_sc_fifo:sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; system:inst_cpu|altera_avalon_sc_fifo:sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; -; 0.312 ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[12] ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; -; 0.312 ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[10] ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; -; 0.312 ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|ac ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|ac ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; -; 0.312 ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[9] ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; -; 0.312 ; system:inst_cpu|system_uart_mc:uart_mc|system_uart_mc_rx:the_system_uart_mc_rx|break_detect ; system:inst_cpu|system_uart_mc:uart_mc|system_uart_mc_rx:the_system_uart_mc_rx|break_detect ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_rs232_counters:RS232_In_Counters|bit_counter[0] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_rs232_counters:RS232_In_Counters|bit_counter[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_rs232_counters:RS232_In_Counters|bit_counter[1] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_rs232_counters:RS232_In_Counters|bit_counter[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_rs232_counters:RS232_In_Counters|bit_counter[2] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_rs232_counters:RS232_In_Counters|bit_counter[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_rs232_counters:RS232_In_Counters|bit_counter[3] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_rs232_counters:RS232_In_Counters|bit_counter[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; system:inst_cpu|altera_merlin_slave_translator:uart_wifi_s1_translator|end_begintransfer ; system:inst_cpu|altera_merlin_slave_translator:uart_wifi_s1_translator|end_begintransfer ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_tx:the_system_uart_wifi_tx|tx_ready ; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_tx:the_system_uart_wifi_tx|tx_ready ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_tx:the_system_uart_wifi_tx|tx_overrun ; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_tx:the_system_uart_wifi_tx|tx_overrun ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_rx:the_system_uart_wifi_rx|break_detect ; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_rx:the_system_uart_wifi_rx|break_detect ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_rx:the_system_uart_wifi_rx|framing_error ; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_rx:the_system_uart_wifi_rx|framing_error ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_rx:the_system_uart_wifi_rx|rx_char_ready ; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_rx:the_system_uart_wifi_rx|rx_char_ready ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +; 0.312 ; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_rx:the_system_uart_wifi_rx|rx_overrun ; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_rx:the_system_uart_wifi_rx|rx_overrun ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; ; 0.312 ; system:inst_cpu|system_uart_mc:uart_mc|system_uart_mc_rx:the_system_uart_mc_rx|rx_char_ready ; system:inst_cpu|system_uart_mc:uart_mc|system_uart_mc_rx:the_system_uart_mc_rx|rx_char_ready ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; -; 0.312 ; system:inst_cpu|system_uart_mc:uart_mc|system_uart_mc_rx:the_system_uart_mc_rx|rx_overrun ; system:inst_cpu|system_uart_mc:uart_mc|system_uart_mc_rx:the_system_uart_mc_rx|rx_overrun ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; -; 0.312 ; system:inst_cpu|system_uart_mc:uart_mc|system_uart_mc_rx:the_system_uart_mc_rx|framing_error ; system:inst_cpu|system_uart_mc:uart_mc|system_uart_mc_rx:the_system_uart_mc_rx|framing_error ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; -; 0.312 ; system:inst_cpu|system_uart_mc:uart_mc|system_uart_mc_tx:the_system_uart_mc_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[9] ; system:inst_cpu|system_uart_mc:uart_mc|system_uart_mc_tx:the_system_uart_mc_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; -; 0.312 ; system:inst_cpu|system_uart_mc:uart_mc|system_uart_mc_tx:the_system_uart_mc_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[0] ; system:inst_cpu|system_uart_mc:uart_mc|system_uart_mc_tx:the_system_uart_mc_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; -; 0.312 ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[5] ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; -; 0.312 ; system:inst_cpu|altera_merlin_slave_translator:cpu_jtag_debug_module_translator|end_begintransfer ; system:inst_cpu|altera_merlin_slave_translator:cpu_jtag_debug_module_translator|end_begintransfer ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; -; 0.312 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonRd ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonRd ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; -; 0.312 ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[2] ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; -; 0.312 ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[0] ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; -; 0.312 ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[15] ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; -; 0.312 ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[14] ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[14] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; -; 0.312 ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|woverflow ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|woverflow ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; -; 0.312 ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[1] ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; -; 0.312 ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[6] ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[6] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; -; 0.312 ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[7] ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; -; 0.312 ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[4] ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; -; 0.312 ; system:inst_cpu|system_cpu:cpu|ic_fill_ap_offset[1] ; system:inst_cpu|system_cpu:cpu|ic_fill_ap_offset[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; -; 0.312 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonWr ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonWr ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; -; 0.312 ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[8] ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; -; 0.312 ; system:inst_cpu|altera_avalon_sc_fifo:sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][102] ; system:inst_cpu|altera_avalon_sc_fifo:sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][102] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; -; 0.312 ; system:inst_cpu|altera_avalon_sc_fifo:sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][102] ; system:inst_cpu|altera_avalon_sc_fifo:sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][102] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; -; 0.312 ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[7] ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; -; 0.312 ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|use_reg ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|use_reg ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; -; 0.312 ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|count[0] ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|count[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; -; 0.312 ; system:inst_cpu|altera_merlin_traffic_limiter:limiter|pending_response_count[0] ; system:inst_cpu|altera_merlin_traffic_limiter:limiter|pending_response_count[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.055 ; 0.511 ; +-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ @@ -2309,215 +2309,215 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-------+-------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +-------+-------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ -; 2.469 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.089 ; 2.437 ; -; 2.469 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[6] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.090 ; 2.436 ; -; 2.469 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.089 ; 2.437 ; -; 2.469 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[22] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.090 ; 2.436 ; -; 2.469 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.090 ; 2.436 ; -; 2.469 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[26] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.090 ; 2.436 ; -; 2.469 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[18] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.090 ; 2.436 ; -; 2.469 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[28] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.089 ; 2.437 ; -; 2.469 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[20] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.089 ; 2.437 ; -; 2.469 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.089 ; 2.437 ; -; 2.469 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.089 ; 2.437 ; -; 2.469 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[16] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.089 ; 2.437 ; -; 2.469 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[24] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.089 ; 2.437 ; -; 2.469 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.090 ; 2.436 ; -; 2.469 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[30] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.090 ; 2.436 ; -; 2.469 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[14] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.090 ; 2.436 ; -; 2.470 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.085 ; 2.440 ; -; 2.470 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[17] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.085 ; 2.440 ; -; 2.470 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[29] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.085 ; 2.440 ; -; 2.470 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.085 ; 2.440 ; -; 2.470 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.085 ; 2.440 ; -; 2.470 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[25] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.085 ; 2.440 ; -; 2.470 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.085 ; 2.440 ; -; 2.470 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.085 ; 2.440 ; -; 2.474 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.080 ; 2.441 ; -; 2.474 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.080 ; 2.441 ; -; 2.474 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.080 ; 2.441 ; -; 2.474 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[27] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.080 ; 2.441 ; -; 2.474 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.080 ; 2.441 ; -; 2.474 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[23] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.080 ; 2.441 ; -; 2.474 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.080 ; 2.441 ; -; 2.474 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[31] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.080 ; 2.441 ; -; 7.011 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.162 ; 2.724 ; -; 7.011 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[14] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.159 ; 2.727 ; -; 7.011 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.159 ; 2.727 ; -; 7.011 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.161 ; 2.725 ; -; 7.011 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.159 ; 2.727 ; -; 7.011 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.159 ; 2.727 ; -; 7.011 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.159 ; 2.727 ; -; 7.012 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.159 ; 2.726 ; -; 7.012 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.162 ; 2.723 ; -; 7.071 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.178 ; 2.648 ; -; 7.071 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[6] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.178 ; 2.648 ; -; 7.072 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.184 ; 2.641 ; -; 7.072 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.184 ; 2.641 ; -; 7.073 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.181 ; 2.643 ; -; 7.073 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.181 ; 2.643 ; -; 7.076 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.195 ; 2.626 ; -; 7.087 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.083 ; 2.733 ; -; 7.087 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.086 ; 2.730 ; -; 7.087 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.086 ; 2.730 ; -; 7.087 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.085 ; 2.733 ; -; 7.087 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[6] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.085 ; 2.733 ; -; 7.087 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.087 ; 2.729 ; -; 7.087 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.084 ; 2.732 ; -; 7.087 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.084 ; 2.732 ; -; 7.087 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.084 ; 2.732 ; -; 7.087 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.084 ; 2.732 ; -; 7.087 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[14] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.084 ; 2.732 ; -; 7.087 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_bank[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.086 ; 2.730 ; -; 7.087 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_bank[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.085 ; 2.731 ; -; 7.088 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.084 ; 2.731 ; -; 7.088 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.084 ; 2.731 ; -; 7.088 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.085 ; 2.730 ; -; 7.088 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[6] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.085 ; 2.730 ; -; 7.088 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.087 ; 2.728 ; -; 7.088 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.084 ; 2.731 ; -; 7.088 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.087 ; 2.728 ; -; 7.088 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_dqm[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.087 ; 2.728 ; -; 7.088 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_dqm[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.087 ; 2.728 ; -; 7.088 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.096 ; 2.721 ; -; 7.088 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.091 ; 2.726 ; -; 7.088 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.091 ; 2.726 ; -; 7.089 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.088 ; 2.728 ; -; 7.089 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.088 ; 2.728 ; -; 7.092 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.102 ; 2.711 ; -; 7.092 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.098 ; 2.715 ; -; 7.092 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.102 ; 2.711 ; -; 7.094 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.096 ; 2.715 ; -; 7.094 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.096 ; 2.715 ; -; 7.105 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.100 ; 2.700 ; -; 7.238 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_2 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.082 ; 2.562 ; -; 7.238 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_7 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.083 ; 2.561 ; -; 7.238 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_9 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.080 ; 2.564 ; -; 7.238 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_10 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.080 ; 2.564 ; -; 7.238 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_11 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.080 ; 2.564 ; -; 7.238 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_13 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.080 ; 2.564 ; -; 7.238 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_14 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.080 ; 2.564 ; -; 7.239 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_8 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.080 ; 2.563 ; -; 7.239 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_12 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.083 ; 2.560 ; -; 7.260 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_5 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.097 ; 2.524 ; -; 7.260 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_6 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.097 ; 2.524 ; -; 7.261 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.103 ; 2.517 ; -; 7.261 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_1 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.103 ; 2.517 ; -; 7.262 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_15 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.100 ; 2.519 ; -; 7.262 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_4 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.100 ; 2.519 ; -; 7.265 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_3 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.114 ; 2.502 ; -; 7.270 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_cmd[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.086 ; 2.547 ; -; 7.295 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_cmd[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.088 ; 2.522 ; -; 7.295 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_cmd[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.088 ; 2.522 ; +; 2.272 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.098 ; 2.625 ; +; 2.272 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[29] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.098 ; 2.625 ; +; 2.272 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.098 ; 2.625 ; +; 2.272 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[17] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.098 ; 2.625 ; +; 2.272 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[25] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.098 ; 2.625 ; +; 2.272 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.098 ; 2.625 ; +; 2.272 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.098 ; 2.625 ; +; 2.272 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.098 ; 2.625 ; +; 2.273 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[6] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.096 ; 2.626 ; +; 2.273 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[26] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.096 ; 2.626 ; +; 2.273 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.096 ; 2.626 ; +; 2.273 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[22] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.096 ; 2.626 ; +; 2.273 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[14] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.096 ; 2.626 ; +; 2.273 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[30] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.096 ; 2.626 ; +; 2.273 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[18] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.096 ; 2.626 ; +; 2.273 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.096 ; 2.626 ; +; 2.276 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[16] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.082 ; 2.637 ; +; 2.276 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.085 ; 2.634 ; +; 2.276 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[20] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.082 ; 2.637 ; +; 2.276 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[27] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.085 ; 2.634 ; +; 2.276 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[28] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.082 ; 2.637 ; +; 2.276 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.082 ; 2.637 ; +; 2.276 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.085 ; 2.634 ; +; 2.276 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.082 ; 2.637 ; +; 2.276 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.085 ; 2.634 ; +; 2.276 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.082 ; 2.637 ; +; 2.276 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[24] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.082 ; 2.637 ; +; 2.276 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[23] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.085 ; 2.634 ; +; 2.276 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[31] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.085 ; 2.634 ; +; 2.276 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.085 ; 2.634 ; +; 2.276 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.082 ; 2.637 ; +; 2.276 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.085 ; 2.634 ; +; 6.822 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.162 ; 2.913 ; +; 6.824 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.159 ; 2.914 ; +; 6.824 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[14] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.159 ; 2.914 ; +; 6.824 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.159 ; 2.914 ; +; 6.824 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.159 ; 2.914 ; +; 6.824 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.159 ; 2.914 ; +; 6.825 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.159 ; 2.913 ; +; 6.825 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.162 ; 2.910 ; +; 6.825 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.161 ; 2.911 ; +; 6.889 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.195 ; 2.813 ; +; 6.892 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.181 ; 2.824 ; +; 6.892 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.181 ; 2.824 ; +; 6.893 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.178 ; 2.826 ; +; 6.893 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[6] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.178 ; 2.826 ; +; 6.898 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.085 ; 2.920 ; +; 6.898 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[6] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.085 ; 2.920 ; +; 6.898 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.087 ; 2.918 ; +; 6.900 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.083 ; 2.920 ; +; 6.900 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.084 ; 2.919 ; +; 6.900 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.084 ; 2.919 ; +; 6.900 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.084 ; 2.919 ; +; 6.900 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.084 ; 2.919 ; +; 6.900 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[14] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.084 ; 2.919 ; +; 6.900 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_bank[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.086 ; 2.917 ; +; 6.900 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_bank[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.085 ; 2.918 ; +; 6.901 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.084 ; 2.918 ; +; 6.901 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.084 ; 2.918 ; +; 6.901 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.086 ; 2.916 ; +; 6.901 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.087 ; 2.915 ; +; 6.901 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.086 ; 2.916 ; +; 6.901 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.084 ; 2.918 ; +; 6.901 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.087 ; 2.915 ; +; 6.901 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_dqm[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.087 ; 2.915 ; +; 6.901 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_dqm[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.087 ; 2.915 ; +; 6.905 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.096 ; 2.904 ; +; 6.905 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.102 ; 2.898 ; +; 6.905 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.098 ; 2.902 ; +; 6.905 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.096 ; 2.904 ; +; 6.905 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.102 ; 2.898 ; +; 6.908 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.088 ; 2.909 ; +; 6.908 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.088 ; 2.909 ; +; 6.909 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.085 ; 2.911 ; +; 6.909 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[6] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.085 ; 2.911 ; +; 6.912 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.170 ; 2.815 ; +; 6.912 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.170 ; 2.815 ; +; 6.914 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.096 ; 2.895 ; +; 6.918 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.100 ; 2.887 ; +; 6.928 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.077 ; 2.900 ; +; 6.928 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.077 ; 2.900 ; +; 7.040 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_7 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.083 ; 2.759 ; +; 7.042 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_10 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.080 ; 2.760 ; +; 7.042 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_11 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.080 ; 2.760 ; +; 7.042 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_13 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.080 ; 2.760 ; +; 7.042 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_14 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.080 ; 2.760 ; +; 7.043 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_2 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.082 ; 2.757 ; +; 7.043 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_8 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.080 ; 2.759 ; +; 7.043 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_9 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.080 ; 2.759 ; +; 7.043 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_12 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.083 ; 2.756 ; +; 7.075 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_cmd[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.086 ; 2.742 ; +; 7.078 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_3 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.114 ; 2.689 ; +; 7.081 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_15 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.100 ; 2.700 ; +; 7.081 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_4 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.100 ; 2.700 ; +; 7.082 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_5 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.097 ; 2.702 ; +; 7.082 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_6 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.097 ; 2.702 ; +; 7.101 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.089 ; 2.691 ; +; 7.101 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_1 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.089 ; 2.691 ; +; 7.115 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_cmd[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.088 ; 2.702 ; +; 7.115 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_cmd[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.088 ; 2.702 ; +-------+-------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Slow 1200mV 0C Model Removal: 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[0]' ; -+-------+-------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+-------+-------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ -; 1.807 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_rx:the_system_uart_wifi_rx|altera_std_synchronizer:the_altera_std_synchronizer|dreg[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.348 ; 2.299 ; -; 1.807 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_rx:the_system_uart_wifi_rx|delayed_unxsync_rxdxx1 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.348 ; 2.299 ; -; 1.807 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_rx:the_system_uart_wifi_rx|baud_rate_counter[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.348 ; 2.299 ; -; 1.807 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_rx:the_system_uart_wifi_rx|baud_clk_en ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.348 ; 2.299 ; -; 1.807 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_rx:the_system_uart_wifi_rx|do_start_rx ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.348 ; 2.299 ; -; 2.083 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_slave_translator:sys_clk_timer_s1_translator|read_latency_shift_reg[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.069 ; 2.296 ; -; 2.083 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_slave_translator:sysid_control_slave_translator|wait_latency_counter[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.069 ; 2.296 ; -; 2.083 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_slave_translator:sysid_control_slave_translator|wait_latency_counter[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.069 ; 2.296 ; -; 2.084 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_slave_translator:cpu_jtag_debug_module_translator|av_readdata_pre[17] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.068 ; 2.296 ; -; 2.084 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|i_readdata_d1[17] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.068 ; 2.296 ; -; 2.084 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_slave_translator:cpu_jtag_debug_module_translator|waitrequest_reset_override ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.065 ; 2.293 ; -; 2.084 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_slave_translator:cpu_jtag_debug_module_translator|av_readdata_pre[23] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.068 ; 2.296 ; -; 2.084 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|d_readdata_d1[23] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.068 ; 2.296 ; -; 2.084 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_slave_translator:cpu_jtag_debug_module_translator|av_readdata_pre[28] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.068 ; 2.296 ; -; 2.084 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.068 ; 2.296 ; -; 2.084 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.068 ; 2.296 ; -; 2.084 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|i_readdata_d1[28] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.068 ; 2.296 ; -; 2.084 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|i_readdatavalid_d1 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.068 ; 2.296 ; -; 2.084 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|d_readdata_d1[17] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.068 ; 2.296 ; -; 2.084 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|d_readdata_d1[16] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.068 ; 2.296 ; -; 2.084 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_slave_translator:cpu_jtag_debug_module_translator|av_readdata_pre[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.068 ; 2.296 ; -; 2.084 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_slave_translator:sys_clk_timer_s1_translator|av_readdata_pre[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.068 ; 2.296 ; -; 2.084 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_slave_translator:uart_wifi_s1_translator|av_readdata_pre[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.068 ; 2.296 ; -; 2.084 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|d_readdata_d1[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.068 ; 2.296 ; -; 2.084 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|ic_fill_ap_offset[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.064 ; 2.292 ; -; 2.084 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_slave_translator:cpu_jtag_debug_module_translator|wait_latency_counter[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.065 ; 2.293 ; -; 2.084 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_slave_translator:cpu_jtag_debug_module_translator|wait_latency_counter[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.065 ; 2.293 ; -; 2.084 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_slave_translator:cpu_jtag_debug_module_translator|end_begintransfer ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.065 ; 2.293 ; -; 2.084 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|A_ienable_reg_irq14 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.068 ; 2.296 ; -; 2.084 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|A_ienable_reg_irq6 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.068 ; 2.296 ; -; 2.084 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|A_ienable_reg_irq4 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.068 ; 2.296 ; -; 2.084 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|i_readdata_d1[23] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.068 ; 2.296 ; -; 2.084 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|i_readdata_d1[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.068 ; 2.296 ; -; 2.084 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][102] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.068 ; 2.296 ; -; 2.084 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][102] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.068 ; 2.296 ; -; 2.084 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux|altera_merlin_arbitrator:arb|top_priority_reg[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.065 ; 2.293 ; -; 2.084 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux|altera_merlin_arbitrator:arb|top_priority_reg[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.065 ; 2.293 ; -; 2.084 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux|saved_grant[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.065 ; 2.293 ; -; 2.084 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|ic_fill_ap_cnt[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.064 ; 2.292 ; -; 2.084 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|ic_fill_ap_cnt[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.064 ; 2.292 ; -; 2.084 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|ic_fill_ap_cnt[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.064 ; 2.292 ; -; 2.084 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|ic_fill_ap_cnt[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.064 ; 2.292 ; -; 2.084 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|i_read ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.064 ; 2.292 ; -; 2.084 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_traffic_limiter:limiter|pending_response_count[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.068 ; 2.296 ; -; 2.084 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_traffic_limiter:limiter|pending_response_count[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.068 ; 2.296 ; -; 2.084 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_traffic_limiter:limiter|pending_response_count[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.068 ; 2.296 ; -; 2.084 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_traffic_limiter:limiter|pending_response_count[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.068 ; 2.296 ; -; 2.084 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_traffic_limiter:limiter|has_pending_responses ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.064 ; 2.292 ; -; 2.084 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux|packet_in_progress ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.065 ; 2.293 ; -; 2.084 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux|saved_grant[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.065 ; 2.293 ; -; 2.084 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_slave_translator:cpu_jtag_debug_module_translator|av_readdata_pre[16] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.068 ; 2.296 ; -; 2.084 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|i_readdata_d1[16] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.068 ; 2.296 ; -; 2.092 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|d_readdata_d1[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.069 ; 2.305 ; -; 2.092 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_uart_mc:uart_mc|system_uart_mc_regs:the_system_uart_mc_regs|tx_data[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.069 ; 2.305 ; -; 2.092 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_uart_mc:uart_mc|system_uart_mc_regs:the_system_uart_mc_regs|tx_data[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.069 ; 2.305 ; -; 2.092 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|d_readdata_d1[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.069 ; 2.305 ; -; 2.092 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_uart_mc:uart_mc|system_uart_mc_regs:the_system_uart_mc_regs|readdata[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.069 ; 2.305 ; -; 2.092 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_slave_translator:uart_mc_s1_translator|av_readdata_pre[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.069 ; 2.305 ; -; 2.092 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_slave_translator:jtag_uart_0_avalon_jtag_slave_translator|av_readdata_pre[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.069 ; 2.305 ; -; 2.092 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|d_readdata_d1[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.069 ; 2.305 ; -; 2.092 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_slave_translator:jtag_uart_0_avalon_jtag_slave_translator|av_readdata_pre[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.069 ; 2.305 ; -; 2.092 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_uart_mc:uart_mc|system_uart_mc_regs:the_system_uart_mc_regs|readdata[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.069 ; 2.305 ; -; 2.092 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_slave_translator:uart_mc_s1_translator|av_readdata_pre[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.069 ; 2.305 ; -; 2.092 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_slave_translator:uart_wifi_s1_translator|av_readdata_pre[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.069 ; 2.305 ; -; 2.092 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_slave_translator:jtag_uart_0_avalon_jtag_slave_translator|av_readdata_pre[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.069 ; 2.305 ; -; 2.092 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_uart_mc:uart_mc|system_uart_mc_regs:the_system_uart_mc_regs|readdata[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.069 ; 2.305 ; -; 2.092 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_slave_translator:uart_mc_s1_translator|av_readdata_pre[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.069 ; 2.305 ; -; 2.092 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_count[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.071 ; 2.307 ; -; 2.092 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|i_next.000 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.063 ; 2.299 ; -; 2.092 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|i_next.111 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.063 ; 2.299 ; -; 2.092 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|i_state.000 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.063 ; 2.299 ; -; 2.092 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|i_cmd[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.063 ; 2.299 ; -; 2.092 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|i_cmd[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.063 ; 2.299 ; -; 2.092 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|refresh_counter[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.082 ; 2.318 ; -; 2.092 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|refresh_counter[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.081 ; 2.317 ; -; 2.092 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|refresh_counter[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.082 ; 2.318 ; -; 2.092 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|refresh_counter[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.082 ; 2.318 ; -; 2.092 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|refresh_counter[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.081 ; 2.317 ; -; 2.092 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|refresh_counter[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.081 ; 2.317 ; -; 2.092 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|refresh_counter[6] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.081 ; 2.317 ; -; 2.092 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|refresh_counter[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.081 ; 2.317 ; -; 2.092 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|refresh_counter[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.082 ; 2.318 ; -; 2.092 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|refresh_counter[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.081 ; 2.317 ; -; 2.092 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|refresh_counter[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.081 ; 2.317 ; -; 2.092 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|refresh_counter[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.081 ; 2.317 ; -; 2.092 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|refresh_counter[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.081 ; 2.317 ; -; 2.092 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|refresh_counter[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.081 ; 2.317 ; -; 2.092 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|refresh_counter[14] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.081 ; 2.317 ; -; 2.092 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|i_state.001 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.063 ; 2.299 ; -; 2.092 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|i_next.101 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.063 ; 2.299 ; -; 2.092 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|init_done ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.063 ; 2.299 ; -; 2.092 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_state.000000100 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.071 ; 2.307 ; -; 2.092 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[5]~_Duplicate_1 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.072 ; 2.308 ; -; 2.092 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[6]~_Duplicate_1 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.072 ; 2.308 ; -; 2.092 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[7]~_Duplicate_1 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.072 ; 2.308 ; -; 2.092 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[8]~_Duplicate_1 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.072 ; 2.308 ; -; 2.092 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[10]~_Duplicate_1 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.072 ; 2.308 ; -; 2.092 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|A_rot_mask[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.071 ; 2.307 ; -; 2.092 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|A_rot_mask[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.071 ; 2.307 ; -; 2.092 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|A_rot_sel_fill2 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.071 ; 2.307 ; -+-------+-------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Removal: 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[0]' ; ++-------+-------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+-------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ +; 2.259 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|rd_address ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.073 ; 2.476 ; +; 2.259 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_state.000000010 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.075 ; 2.478 ; +; 2.259 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_state.000100000 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.075 ; 2.478 ; +; 2.259 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|f_pop ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.075 ; 2.478 ; +; 2.259 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|byteen_reg[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.069 ; 2.472 ; +; 2.259 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|byteen_reg[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.069 ; 2.472 ; +; 2.259 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|address_reg[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.069 ; 2.472 ; +; 2.259 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|address_reg[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.069 ; 2.472 ; +; 2.259 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|address_reg[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.069 ; 2.472 ; +; 2.259 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|address_reg[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.069 ; 2.472 ; +; 2.259 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|address_reg[23] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.069 ; 2.472 ; +; 2.259 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_state.000000100 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.075 ; 2.478 ; +; 2.259 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|i_addr[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.075 ; 2.478 ; +; 2.259 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|data_reg[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.069 ; 2.472 ; +; 2.261 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux_001|altera_merlin_arbitrator:arb|top_priority_reg[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.066 ; 2.471 ; +; 2.261 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux_001|altera_merlin_arbitrator:arb|top_priority_reg[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.066 ; 2.471 ; +; 2.261 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux_001|saved_grant[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.066 ; 2.471 ; +; 2.261 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_next.000001000 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.072 ; 2.477 ; +; 2.261 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_state.000001000 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.072 ; 2.477 ; +; 2.261 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_next.000000001 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.072 ; 2.477 ; +; 2.261 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_next.000010000 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.072 ; 2.477 ; +; 2.261 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_state.000010000 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.072 ; 2.477 ; +; 2.261 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_cmd[0]~_Duplicate_1 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.072 ; 2.477 ; +; 2.261 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_cmd[2]~_Duplicate_1 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.072 ; 2.477 ; +; 2.261 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_cmd[1]~_Duplicate_1 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.072 ; 2.477 ; +; 2.261 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|rd_valid[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.072 ; 2.477 ; +; 2.261 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][84] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.071 ; 2.476 ; +; 2.261 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][84] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.071 ; 2.476 ; +; 2.261 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux_001|saved_grant[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.066 ; 2.471 ; +; 2.261 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][83] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.071 ; 2.476 ; +; 2.261 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][83] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.071 ; 2.476 ; +; 2.261 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][53] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.071 ; 2.476 ; +; 2.261 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][53] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.071 ; 2.476 ; +; 2.261 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][56] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.071 ; 2.476 ; +; 2.261 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][56] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.071 ; 2.476 ; +; 2.261 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.071 ; 2.476 ; +; 2.261 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.071 ; 2.476 ; +; 2.261 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][55] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.071 ; 2.476 ; +; 2.261 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][55] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.071 ; 2.476 ; +; 2.261 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|init_done ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.072 ; 2.477 ; +; 2.261 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|ack_refresh_request ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.072 ; 2.477 ; +; 2.261 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|refresh_request ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.072 ; 2.477 ; +; 2.261 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_state.100000000 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.072 ; 2.477 ; +; 2.262 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|count[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.066 ; 2.472 ; +; 2.262 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|use_reg ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.066 ; 2.472 ; +; 2.262 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|i_next.000 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.072 ; 2.478 ; +; 2.262 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|i_state.000 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.072 ; 2.478 ; +; 2.262 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|i_next.010 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.072 ; 2.478 ; +; 2.262 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|i_count[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.072 ; 2.478 ; +; 2.262 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|i_count[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.072 ; 2.478 ; +; 2.262 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|i_next.111 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.072 ; 2.478 ; +; 2.262 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|i_state.111 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.072 ; 2.478 ; +; 2.262 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|i_count[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.072 ; 2.478 ; +; 2.262 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|i_state.010 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.072 ; 2.478 ; +; 2.262 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|i_cmd[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.072 ; 2.478 ; +; 2.262 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|i_cmd[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.072 ; 2.478 ; +; 2.262 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|i_cmd[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.072 ; 2.478 ; +; 2.262 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|endofpacket_reg ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.066 ; 2.472 ; +; 2.262 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux_001|packet_in_progress ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.066 ; 2.472 ; +; 2.262 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][54] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.066 ; 2.472 ; +; 2.262 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|i_state.001 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.072 ; 2.478 ; +; 2.262 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|i_state.011 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.072 ; 2.478 ; +; 2.262 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|i_next.101 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.072 ; 2.478 ; +; 2.262 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|i_state.101 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.072 ; 2.478 ; +; 2.262 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[1]~_Duplicate_1 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.071 ; 2.477 ; +; 2.262 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[4]~_Duplicate_1 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.071 ; 2.477 ; +; 2.262 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[5]~_Duplicate_1 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.071 ; 2.477 ; +; 2.262 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[6]~_Duplicate_1 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.071 ; 2.477 ; +; 2.262 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[11]~_Duplicate_1 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.071 ; 2.477 ; +; 2.262 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|i_cmd[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.072 ; 2.478 ; +; 2.267 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_count[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.069 ; 2.480 ; +; 2.267 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_count[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.069 ; 2.480 ; +; 2.267 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_state.000000001 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.069 ; 2.480 ; +; 2.267 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_count[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.069 ; 2.480 ; +; 2.267 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_state.001000000 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.069 ; 2.480 ; +; 2.267 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_next.010000000 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.069 ; 2.480 ; +; 2.267 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_state.010000000 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.069 ; 2.480 ; +; 2.267 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[2]~_Duplicate_1 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.067 ; 2.478 ; +; 2.267 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[3]~_Duplicate_1 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.068 ; 2.479 ; +; 2.267 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[7]~_Duplicate_1 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.068 ; 2.479 ; +; 2.267 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[8]~_Duplicate_1 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.068 ; 2.479 ; +; 2.267 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[9]~_Duplicate_1 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.068 ; 2.479 ; +; 2.267 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[10]~_Duplicate_1 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.068 ; 2.479 ; +; 2.269 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|E_iw[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.066 ; 2.479 ; +; 2.269 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|E_iw[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.066 ; 2.479 ; +; 2.269 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|E_iw[14] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.066 ; 2.479 ; +; 2.269 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|E_iw[16] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.066 ; 2.479 ; +; 2.269 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|E_pc[23] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.065 ; 2.478 ; +; 2.269 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|E_iw[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.066 ; 2.479 ; +; 2.269 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|M_ctrl_rdctl_inst ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.066 ; 2.479 ; +; 2.269 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|D_iw[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.063 ; 2.476 ; +; 2.269 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|D_iw[6] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.064 ; 2.477 ; +; 2.269 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|D_ctrl_ignore_dst ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.063 ; 2.476 ; +; 2.269 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|latched_oci_tb_hbreak_req ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.065 ; 2.478 ; +; 2.269 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|D_iw[18] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.065 ; 2.478 ; +; 2.269 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|E_ctrl_shift_rot ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.064 ; 2.477 ; +; 2.269 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|D_pc[6] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.061 ; 2.474 ; +; 2.269 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|D_iw[24] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.066 ; 2.479 ; +; 2.269 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|D_iw[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 2.475 ; +; 2.269 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|E_dst_regnum[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.066 ; 2.479 ; ++-------+-------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ @@ -2525,18 +2525,74 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-------+--------------+----------------+-----------------+----------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; +-------+--------------+----------------+-----------------+----------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[0] ; -; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[10] ; -; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[11] ; -; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[12] ; -; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[13] ; -; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[14] ; -; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[15] ; +; 4.716 ; 4.987 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[0] ; +; 4.716 ; 4.987 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[10] ; +; 4.716 ; 4.987 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[11] ; +; 4.716 ; 4.987 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[12] ; +; 4.716 ; 4.987 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[13] ; +; 4.716 ; 4.987 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[14] ; +; 4.716 ; 4.987 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[15] ; +; 4.716 ; 4.987 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[1] ; +; 4.716 ; 4.987 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[2] ; +; 4.716 ; 4.987 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[3] ; +; 4.716 ; 4.987 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[4] ; +; 4.716 ; 4.987 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[5] ; +; 4.716 ; 4.987 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[6] ; +; 4.716 ; 4.987 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[7] ; +; 4.716 ; 4.987 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[8] ; +; 4.716 ; 4.987 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[9] ; +; 4.716 ; 4.987 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[0] ; +; 4.716 ; 4.987 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[10] ; +; 4.716 ; 4.987 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[11] ; +; 4.716 ; 4.987 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[12] ; +; 4.716 ; 4.987 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[13] ; +; 4.716 ; 4.987 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[14] ; +; 4.716 ; 4.987 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[15] ; +; 4.716 ; 4.987 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[1] ; +; 4.716 ; 4.987 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[2] ; +; 4.716 ; 4.987 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[3] ; +; 4.716 ; 4.987 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[4] ; +; 4.716 ; 4.987 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[5] ; +; 4.716 ; 4.987 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[6] ; +; 4.716 ; 4.987 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[7] ; +; 4.716 ; 4.987 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[8] ; +; 4.716 ; 4.987 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[9] ; +; 4.716 ; 4.987 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3 ; +; 4.716 ; 4.987 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT1 ; +; 4.716 ; 4.987 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT10 ; +; 4.716 ; 4.987 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT11 ; +; 4.716 ; 4.987 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT12 ; +; 4.716 ; 4.987 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT13 ; +; 4.716 ; 4.987 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT14 ; +; 4.716 ; 4.987 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT15 ; +; 4.716 ; 4.987 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT16 ; +; 4.716 ; 4.987 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT17 ; +; 4.716 ; 4.987 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT18 ; +; 4.716 ; 4.987 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT19 ; +; 4.716 ; 4.987 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT2 ; +; 4.716 ; 4.987 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT20 ; +; 4.716 ; 4.987 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT21 ; +; 4.716 ; 4.987 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT22 ; +; 4.716 ; 4.987 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT23 ; +; 4.716 ; 4.987 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT24 ; +; 4.716 ; 4.987 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT25 ; +; 4.716 ; 4.987 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT26 ; +; 4.716 ; 4.987 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT27 ; +; 4.716 ; 4.987 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT28 ; +; 4.716 ; 4.987 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT29 ; +; 4.716 ; 4.987 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT3 ; +; 4.716 ; 4.987 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT30 ; +; 4.716 ; 4.987 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT31 ; +; 4.716 ; 4.987 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT4 ; +; 4.716 ; 4.987 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT5 ; +; 4.716 ; 4.987 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT6 ; +; 4.716 ; 4.987 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT7 ; +; 4.716 ; 4.987 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT8 ; +; 4.716 ; 4.987 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT9 ; ; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[16] ; ; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[17] ; ; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[18] ; ; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[19] ; -; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[1] ; ; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[20] ; ; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[21] ; ; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[22] ; @@ -2547,80 +2603,24 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp ; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[27] ; ; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[28] ; ; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[29] ; -; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[2] ; ; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[30] ; ; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[31] ; -; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[3] ; -; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[4] ; -; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[5] ; -; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[6] ; -; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[7] ; -; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[8] ; -; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src1[9] ; -; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[0] ; ; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[0]~_Duplicate_1 ; -; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[10] ; ; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[10]~_Duplicate_1 ; -; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[11] ; ; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[11]~_Duplicate_1 ; -; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[12] ; ; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[12]~_Duplicate_1 ; -; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[13] ; ; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[13]~_Duplicate_1 ; -; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[14] ; ; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[14]~_Duplicate_1 ; -; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[15] ; ; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[15]~_Duplicate_1 ; -; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[1] ; ; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[1]~_Duplicate_1 ; -; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[2] ; ; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[2]~_Duplicate_1 ; -; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[3] ; ; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[3]~_Duplicate_1 ; -; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[4] ; ; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[4]~_Duplicate_1 ; -; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[5] ; ; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[5]~_Duplicate_1 ; -; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[6] ; ; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[6]~_Duplicate_1 ; -; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[7] ; ; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[7]~_Duplicate_1 ; -; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[8] ; ; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[8]~_Duplicate_1 ; -; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[9] ; ; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|A_mul_src2[9]~_Duplicate_1 ; -; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3 ; -; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT1 ; -; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT10 ; -; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT11 ; -; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT12 ; -; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT13 ; -; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT14 ; -; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT15 ; -; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT16 ; -; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT17 ; -; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT18 ; -; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT19 ; -; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT2 ; -; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT20 ; -; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT21 ; -; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT22 ; -; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT23 ; -; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT24 ; -; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT25 ; -; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT26 ; -; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT27 ; -; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT28 ; -; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT29 ; -; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT3 ; -; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT30 ; -; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT31 ; -; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT4 ; -; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT5 ; -; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT6 ; -; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT7 ; -; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT8 ; -; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_75u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT9 ; ; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3 ; ; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT1 ; ; 4.719 ; 4.990 ; 0.271 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_mult_cell:the_system_cpu_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_95u2:auto_generated|ded_mult_ks81:ded_mult1|mac_out3~DATAOUT10 ; @@ -2651,112 +2651,112 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +--------+--------------+----------------+------------------+----------+------------+--------------------------------------------------------------------+ -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Slow 1200mV 0C Model Minimum Pulse Width: 'altera_reserved_tck' ; -+--------+--------------+----------------+------------------+---------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; -+--------+--------------+----------------+------------------+---------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; 49.604 ; 49.820 ; 0.216 ; High Pulse Width ; altera_reserved_tck ; Fall ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; -; 49.604 ; 49.820 ; 0.216 ; High Pulse Width ; altera_reserved_tck ; Fall ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|tdo~reg0 ; -; 49.605 ; 49.821 ; 0.216 ; High Pulse Width ; altera_reserved_tck ; Fall ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|jupdate ; -; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[10] ; -; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[11] ; -; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[12] ; -; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[13] ; -; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[14] ; -; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[1] ; -; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[2] ; -; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[3] ; -; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[4] ; -; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[5] ; -; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[6] ; -; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[8] ; -; 49.642 ; 49.826 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[9] ; -; 49.643 ; 49.827 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[0] ; -; 49.643 ; 49.827 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[1] ; -; 49.643 ; 49.827 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[2] ; -; 49.643 ; 49.827 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[3] ; -; 49.643 ; 49.827 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[0] ; -; 49.643 ; 49.827 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[1] ; -; 49.643 ; 49.827 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[2] ; -; 49.643 ; 49.827 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[3] ; -; 49.643 ; 49.827 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[0] ; -; 49.643 ; 49.827 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1] ; -; 49.643 ; 49.827 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2] ; -; 49.643 ; 49.827 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[3] ; -; 49.643 ; 49.827 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[4] ; -; 49.643 ; 49.827 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[5] ; -; 49.643 ; 49.827 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[6] ; -; 49.643 ; 49.827 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[7] ; -; 49.643 ; 49.827 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[8] ; -; 49.643 ; 49.827 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[9] ; -; 49.643 ; 49.827 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[0] ; -; 49.643 ; 49.827 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[1] ; -; 49.643 ; 49.827 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[2] ; -; 49.643 ; 49.827 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_dr_scan_reg ; -; 49.643 ; 49.827 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; -; 49.643 ; 49.827 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[0] ; -; 49.643 ; 49.827 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[15] ; -; 49.643 ; 49.827 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|count[1] ; -; 49.643 ; 49.827 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|count[2] ; -; 49.643 ; 49.827 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|count[3] ; -; 49.643 ; 49.827 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|state ; -; 49.643 ; 49.827 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|tck_t_dav ; -; 49.643 ; 49.827 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|td_shift[0] ; -; 49.643 ; 49.827 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|user_saw_rvalid ; -; 49.644 ; 49.828 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[0] ; -; 49.644 ; 49.828 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[1] ; -; 49.644 ; 49.828 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[2] ; -; 49.644 ; 49.828 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[3] ; -; 49.644 ; 49.828 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[0] ; -; 49.644 ; 49.828 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[1] ; -; 49.644 ; 49.828 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[2] ; -; 49.644 ; 49.828 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[3] ; -; 49.644 ; 49.828 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[0] ; -; 49.644 ; 49.828 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[1] ; -; 49.644 ; 49.828 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[2] ; -; 49.644 ; 49.828 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[3] ; -; 49.644 ; 49.828 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[4] ; -; 49.644 ; 49.828 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[0] ; -; 49.644 ; 49.828 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[1] ; -; 49.644 ; 49.828 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[2] ; -; 49.644 ; 49.828 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[3] ; -; 49.644 ; 49.828 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[0] ; -; 49.644 ; 49.828 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[1] ; -; 49.644 ; 49.828 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[2] ; -; 49.644 ; 49.828 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[3] ; -; 49.644 ; 49.828 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[4] ; -; 49.644 ; 49.828 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; -; 49.644 ; 49.828 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[10] ; -; 49.644 ; 49.828 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[11] ; -; 49.644 ; 49.828 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[12] ; -; 49.644 ; 49.828 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[13] ; -; 49.644 ; 49.828 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[14] ; -; 49.644 ; 49.828 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[15] ; -; 49.644 ; 49.828 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[1] ; -; 49.644 ; 49.828 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[2] ; -; 49.644 ; 49.828 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; -; 49.644 ; 49.828 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; -; 49.644 ; 49.828 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[5] ; -; 49.644 ; 49.828 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[6] ; -; 49.644 ; 49.828 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[7] ; -; 49.644 ; 49.828 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[9] ; -; 49.644 ; 49.828 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|din_s1 ; -; 49.644 ; 49.828 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|dreg[0] ; -; 49.644 ; 49.828 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 ; -; 49.644 ; 49.828 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer|dreg[0] ; -; 49.644 ; 49.828 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|ir_out[1] ; -; 49.644 ; 49.828 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[27] ; -; 49.644 ; 49.828 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[28] ; -; 49.644 ; 49.828 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[29] ; -; 49.644 ; 49.828 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[30] ; -; 49.644 ; 49.828 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[32] ; -; 49.644 ; 49.828 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[33] ; -; 49.644 ; 49.828 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[34] ; -; 49.644 ; 49.828 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[35] ; -; 49.644 ; 49.828 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[36] ; -; 49.644 ; 49.828 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[37] ; -+--------+--------------+----------------+------------------+---------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow 1200mV 0C Model Minimum Pulse Width: 'altera_reserved_tck' ; ++--------+--------------+----------------+------------------+---------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; ++--------+--------------+----------------+------------------+---------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; 49.608 ; 49.824 ; 0.216 ; High Pulse Width ; altera_reserved_tck ; Fall ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; +; 49.609 ; 49.825 ; 0.216 ; High Pulse Width ; altera_reserved_tck ; Fall ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|jupdate ; +; 49.609 ; 49.825 ; 0.216 ; High Pulse Width ; altera_reserved_tck ; Fall ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|tdo~reg0 ; +; 49.644 ; 49.828 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|count[6] ; +; 49.644 ; 49.828 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|count[7] ; +; 49.644 ; 49.828 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|count[8] ; +; 49.644 ; 49.828 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|count[9] ; +; 49.644 ; 49.828 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|td_shift[8] ; +; 49.644 ; 49.828 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|td_shift[9] ; +; 49.644 ; 49.828 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|wdata[1] ; +; 49.644 ; 49.828 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|wdata[2] ; +; 49.644 ; 49.828 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|wdata[3] ; +; 49.644 ; 49.828 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|wdata[4] ; +; 49.644 ; 49.828 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|wdata[5] ; +; 49.644 ; 49.828 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|wdata[6] ; +; 49.644 ; 49.828 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|wdata[7] ; +; 49.644 ; 49.828 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|write ; +; 49.645 ; 49.829 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|read ; +; 49.645 ; 49.829 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|read_req ; +; 49.645 ; 49.829 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|tck_t_dav ; +; 49.645 ; 49.829 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|user_saw_rvalid ; +; 49.645 ; 49.829 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|wdata[0] ; +; 49.645 ; 49.829 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|write_stalled ; +; 49.645 ; 49.829 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|write_valid ; +; 49.646 ; 49.830 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|count[1] ; +; 49.646 ; 49.830 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|count[2] ; +; 49.646 ; 49.830 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|count[3] ; +; 49.646 ; 49.830 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|count[4] ; +; 49.646 ; 49.830 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|count[5] ; +; 49.646 ; 49.830 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|state ; +; 49.646 ; 49.830 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|td_shift[0] ; +; 49.646 ; 49.830 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|td_shift[10] ; +; 49.648 ; 49.832 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[10] ; +; 49.648 ; 49.832 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[11] ; +; 49.648 ; 49.832 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[12] ; +; 49.648 ; 49.832 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[13] ; +; 49.648 ; 49.832 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[14] ; +; 49.648 ; 49.832 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[15] ; +; 49.648 ; 49.832 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[16] ; +; 49.648 ; 49.832 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[17] ; +; 49.648 ; 49.832 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[18] ; +; 49.648 ; 49.832 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[19] ; +; 49.648 ; 49.832 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[1] ; +; 49.648 ; 49.832 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[20] ; +; 49.648 ; 49.832 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[21] ; +; 49.648 ; 49.832 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[22] ; +; 49.648 ; 49.832 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[23] ; +; 49.648 ; 49.832 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[24] ; +; 49.648 ; 49.832 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[25] ; +; 49.648 ; 49.832 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[26] ; +; 49.648 ; 49.832 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[27] ; +; 49.648 ; 49.832 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[28] ; +; 49.648 ; 49.832 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[29] ; +; 49.648 ; 49.832 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[2] ; +; 49.648 ; 49.832 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[30] ; +; 49.648 ; 49.832 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[31] ; +; 49.648 ; 49.832 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[32] ; +; 49.648 ; 49.832 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[33] ; +; 49.648 ; 49.832 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[34] ; +; 49.648 ; 49.832 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[35] ; +; 49.648 ; 49.832 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[3] ; +; 49.648 ; 49.832 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[4] ; +; 49.648 ; 49.832 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[5] ; +; 49.648 ; 49.832 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[6] ; +; 49.648 ; 49.832 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[7] ; +; 49.648 ; 49.832 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[8] ; +; 49.648 ; 49.832 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[9] ; +; 49.649 ; 49.833 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[0] ; +; 49.649 ; 49.833 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[1] ; +; 49.649 ; 49.833 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[2] ; +; 49.649 ; 49.833 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[3] ; +; 49.649 ; 49.833 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[0] ; +; 49.649 ; 49.833 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[1] ; +; 49.649 ; 49.833 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[2] ; +; 49.649 ; 49.833 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[3] ; +; 49.649 ; 49.833 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[0] ; +; 49.649 ; 49.833 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1] ; +; 49.649 ; 49.833 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[2] ; +; 49.649 ; 49.833 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[0] ; +; 49.649 ; 49.833 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[1] ; +; 49.649 ; 49.833 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[2] ; +; 49.649 ; 49.833 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[3] ; +; 49.649 ; 49.833 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[0] ; +; 49.649 ; 49.833 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[1] ; +; 49.649 ; 49.833 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[2] ; +; 49.649 ; 49.833 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[3] ; +; 49.649 ; 49.833 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0] ; +; 49.649 ; 49.833 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2] ; +; 49.649 ; 49.833 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4] ; +; 49.649 ; 49.833 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[0] ; +; 49.649 ; 49.833 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[1] ; +; 49.649 ; 49.833 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[2] ; +; 49.649 ; 49.833 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[3] ; +; 49.649 ; 49.833 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[4] ; +; 49.649 ; 49.833 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; +; 49.649 ; 49.833 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6] ; +; 49.649 ; 49.833 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; +; 49.649 ; 49.833 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0 ; +; 49.649 ; 49.833 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][0] ; +; 49.649 ; 49.833 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][2] ; ++--------+--------------+----------------+------------------+---------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ @@ -2872,8 +2872,8 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +---------------------+---------------------+-------+-------+------------+----------------------------------------------------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +---------------------+---------------------+-------+-------+------------+----------------------------------------------------------+ -; altera_reserved_tdi ; altera_reserved_tck ; 2.187 ; 2.325 ; Rise ; altera_reserved_tck ; -; altera_reserved_tms ; altera_reserved_tck ; 6.417 ; 6.523 ; Rise ; altera_reserved_tck ; +; altera_reserved_tdi ; altera_reserved_tck ; 2.358 ; 2.500 ; Rise ; altera_reserved_tck ; +; altera_reserved_tms ; altera_reserved_tck ; 6.502 ; 6.650 ; Rise ; altera_reserved_tck ; ; DRAM_DQ[*] ; CLOCK_50 ; 0.890 ; 1.030 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; DRAM_DQ[0] ; CLOCK_50 ; 0.879 ; 1.019 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; DRAM_DQ[1] ; CLOCK_50 ; 0.879 ; 1.019 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; @@ -2891,15 +2891,15 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp ; DRAM_DQ[13] ; CLOCK_50 ; 0.853 ; 0.995 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; DRAM_DQ[14] ; CLOCK_50 ; 0.853 ; 0.995 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; DRAM_DQ[15] ; CLOCK_50 ; 0.876 ; 1.016 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; GPIO_0[*] ; CLOCK_50 ; 4.288 ; 4.706 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; GPIO_0[31] ; CLOCK_50 ; 4.288 ; 4.706 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; KEY[*] ; CLOCK_50 ; 2.173 ; 2.334 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; KEY[1] ; CLOCK_50 ; 2.173 ; 2.334 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; SW[*] ; CLOCK_50 ; 2.122 ; 2.278 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; SW[0] ; CLOCK_50 ; 2.063 ; 2.226 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; SW[1] ; CLOCK_50 ; 1.670 ; 1.796 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; SW[2] ; CLOCK_50 ; 1.735 ; 1.852 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; SW[3] ; CLOCK_50 ; 2.122 ; 2.278 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_0[*] ; CLOCK_50 ; 4.171 ; 4.577 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_0[31] ; CLOCK_50 ; 4.171 ; 4.577 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; KEY[*] ; CLOCK_50 ; 1.983 ; 2.129 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; KEY[1] ; CLOCK_50 ; 1.983 ; 2.129 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; SW[*] ; CLOCK_50 ; 2.259 ; 2.305 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; SW[0] ; CLOCK_50 ; 1.676 ; 1.849 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; SW[1] ; CLOCK_50 ; 2.259 ; 2.305 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; SW[2] ; CLOCK_50 ; 1.992 ; 2.143 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; SW[3] ; CLOCK_50 ; 1.791 ; 1.929 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +---------------------+---------------------+-------+-------+------------+----------------------------------------------------------+ @@ -2908,8 +2908,8 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +---------------------+---------------------+--------+--------+------------+----------------------------------------------------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +---------------------+---------------------+--------+--------+------------+----------------------------------------------------------+ -; altera_reserved_tdi ; altera_reserved_tck ; 0.917 ; 0.829 ; Rise ; altera_reserved_tck ; -; altera_reserved_tms ; altera_reserved_tck ; -1.215 ; -1.319 ; Rise ; altera_reserved_tck ; +; altera_reserved_tdi ; altera_reserved_tck ; 0.920 ; 0.827 ; Rise ; altera_reserved_tck ; +; altera_reserved_tms ; altera_reserved_tck ; -0.997 ; -1.134 ; Rise ; altera_reserved_tck ; ; DRAM_DQ[*] ; CLOCK_50 ; -0.383 ; -0.525 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; DRAM_DQ[0] ; CLOCK_50 ; -0.407 ; -0.547 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; DRAM_DQ[1] ; CLOCK_50 ; -0.407 ; -0.547 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; @@ -2927,15 +2927,15 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp ; DRAM_DQ[13] ; CLOCK_50 ; -0.383 ; -0.525 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; DRAM_DQ[14] ; CLOCK_50 ; -0.383 ; -0.525 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; DRAM_DQ[15] ; CLOCK_50 ; -0.404 ; -0.544 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; GPIO_0[*] ; CLOCK_50 ; -3.270 ; -3.687 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; GPIO_0[31] ; CLOCK_50 ; -3.270 ; -3.687 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; KEY[*] ; CLOCK_50 ; -1.373 ; -1.523 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; KEY[1] ; CLOCK_50 ; -1.373 ; -1.523 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; SW[*] ; CLOCK_50 ; -1.126 ; -1.247 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; SW[0] ; CLOCK_50 ; -1.503 ; -1.659 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; SW[1] ; CLOCK_50 ; -1.126 ; -1.247 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; SW[2] ; CLOCK_50 ; -1.188 ; -1.301 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; SW[3] ; CLOCK_50 ; -1.559 ; -1.708 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_0[*] ; CLOCK_50 ; -3.381 ; -3.792 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_0[31] ; CLOCK_50 ; -3.381 ; -3.792 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; KEY[*] ; CLOCK_50 ; -1.158 ; -1.302 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; KEY[1] ; CLOCK_50 ; -1.158 ; -1.302 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; SW[*] ; CLOCK_50 ; -1.132 ; -1.298 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; SW[0] ; CLOCK_50 ; -1.132 ; -1.298 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; SW[1] ; CLOCK_50 ; -1.680 ; -1.709 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; SW[2] ; CLOCK_50 ; -1.391 ; -1.525 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; SW[3] ; CLOCK_50 ; -1.242 ; -1.375 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +---------------------+---------------------+--------+--------+------------+----------------------------------------------------------+ @@ -2944,7 +2944,7 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +---------------------+---------------------+--------+--------+------------+----------------------------------------------------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +---------------------+---------------------+--------+--------+------------+----------------------------------------------------------+ -; altera_reserved_tdo ; altera_reserved_tck ; 10.047 ; 10.540 ; Fall ; altera_reserved_tck ; +; altera_reserved_tdo ; altera_reserved_tck ; 10.146 ; 10.659 ; Fall ; altera_reserved_tck ; ; DRAM_ADDR[*] ; CLOCK_50 ; 2.776 ; 2.752 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; DRAM_ADDR[0] ; CLOCK_50 ; 2.776 ; 2.752 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; DRAM_ADDR[1] ; CLOCK_50 ; 2.685 ; 2.682 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; @@ -2985,20 +2985,20 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp ; DRAM_DQM[0] ; CLOCK_50 ; 2.682 ; 2.679 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; DRAM_DQM[1] ; CLOCK_50 ; 2.682 ; 2.679 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; DRAM_RAS_N ; CLOCK_50 ; 2.784 ; 2.760 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; DRAM_WE_N ; CLOCK_50 ; 2.790 ; 2.766 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; GPIO_0[*] ; CLOCK_50 ; 5.494 ; 5.555 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; GPIO_0[33] ; CLOCK_50 ; 5.494 ; 5.555 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; GPIO_1[*] ; CLOCK_50 ; 4.273 ; 4.309 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; GPIO_1[0] ; CLOCK_50 ; 4.169 ; 4.196 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; GPIO_1[33] ; CLOCK_50 ; 4.273 ; 4.309 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; LED[*] ; CLOCK_50 ; 5.653 ; 5.664 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; LED[0] ; CLOCK_50 ; 4.410 ; 4.440 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; LED[1] ; CLOCK_50 ; 4.629 ; 4.642 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; LED[2] ; CLOCK_50 ; 4.236 ; 4.274 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; LED[3] ; CLOCK_50 ; 4.354 ; 4.369 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; LED[4] ; CLOCK_50 ; 5.582 ; 5.664 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; LED[5] ; CLOCK_50 ; 5.551 ; 5.628 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; LED[6] ; CLOCK_50 ; 5.653 ; 5.599 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_WE_N ; CLOCK_50 ; 2.781 ; 2.757 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_0[*] ; CLOCK_50 ; 4.821 ; 4.799 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_0[33] ; CLOCK_50 ; 4.821 ; 4.799 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_1[*] ; CLOCK_50 ; 5.030 ; 5.138 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_1[0] ; CLOCK_50 ; 5.030 ; 5.138 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_1[33] ; CLOCK_50 ; 4.639 ; 4.727 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[*] ; CLOCK_50 ; 5.539 ; 5.519 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[0] ; CLOCK_50 ; 4.808 ; 4.875 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[1] ; CLOCK_50 ; 5.429 ; 5.473 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[2] ; CLOCK_50 ; 5.086 ; 5.115 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[3] ; CLOCK_50 ; 4.560 ; 4.554 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[4] ; CLOCK_50 ; 4.337 ; 4.320 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[5] ; CLOCK_50 ; 5.539 ; 5.519 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[6] ; CLOCK_50 ; 4.051 ; 4.069 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; DRAM_CLK ; CLOCK_50 ; 0.948 ; ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[1] ; ; DRAM_CLK ; CLOCK_50 ; ; 0.910 ; Fall ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[1] ; ; LED[*] ; CLOCK_50 ; 4.247 ; 4.292 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; @@ -3011,7 +3011,7 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +---------------------+---------------------+-------+-------+------------+----------------------------------------------------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +---------------------+---------------------+-------+-------+------------+----------------------------------------------------------+ -; altera_reserved_tdo ; altera_reserved_tck ; 7.841 ; 8.336 ; Fall ; altera_reserved_tck ; +; altera_reserved_tdo ; altera_reserved_tck ; 7.936 ; 8.450 ; Fall ; altera_reserved_tck ; ; DRAM_ADDR[*] ; CLOCK_50 ; 2.312 ; 2.310 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; DRAM_ADDR[0] ; CLOCK_50 ; 2.421 ; 2.397 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; DRAM_ADDR[1] ; CLOCK_50 ; 2.332 ; 2.328 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; @@ -3052,20 +3052,20 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp ; DRAM_DQM[0] ; CLOCK_50 ; 2.329 ; 2.325 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; DRAM_DQM[1] ; CLOCK_50 ; 2.329 ; 2.325 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; DRAM_RAS_N ; CLOCK_50 ; 2.429 ; 2.405 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; DRAM_WE_N ; CLOCK_50 ; 2.434 ; 2.410 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; GPIO_0[*] ; CLOCK_50 ; 4.954 ; 5.013 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; GPIO_0[33] ; CLOCK_50 ; 4.954 ; 5.013 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; GPIO_1[*] ; CLOCK_50 ; 3.680 ; 3.706 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; GPIO_1[0] ; CLOCK_50 ; 3.680 ; 3.706 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; GPIO_1[33] ; CLOCK_50 ; 3.783 ; 3.819 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; LED[*] ; CLOCK_50 ; 3.746 ; 3.783 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; LED[0] ; CLOCK_50 ; 3.914 ; 3.942 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; LED[1] ; CLOCK_50 ; 4.124 ; 4.136 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; LED[2] ; CLOCK_50 ; 3.746 ; 3.783 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; LED[3] ; CLOCK_50 ; 3.859 ; 3.874 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; LED[4] ; CLOCK_50 ; 5.041 ; 5.118 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; LED[5] ; CLOCK_50 ; 5.053 ; 5.127 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; LED[6] ; CLOCK_50 ; 5.105 ; 5.053 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_WE_N ; CLOCK_50 ; 2.426 ; 2.402 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_0[*] ; CLOCK_50 ; 4.308 ; 4.286 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_0[33] ; CLOCK_50 ; 4.308 ; 4.286 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_1[*] ; CLOCK_50 ; 4.134 ; 4.220 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_1[0] ; CLOCK_50 ; 4.506 ; 4.610 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_1[33] ; CLOCK_50 ; 4.134 ; 4.220 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[*] ; CLOCK_50 ; 3.566 ; 3.582 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[0] ; CLOCK_50 ; 4.294 ; 4.357 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[1] ; CLOCK_50 ; 4.890 ; 4.932 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[2] ; CLOCK_50 ; 4.561 ; 4.588 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[3] ; CLOCK_50 ; 4.056 ; 4.050 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[4] ; CLOCK_50 ; 3.845 ; 3.827 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[5] ; CLOCK_50 ; 5.040 ; 5.022 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[6] ; CLOCK_50 ; 3.566 ; 3.582 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; DRAM_CLK ; CLOCK_50 ; 0.537 ; ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[1] ; ; DRAM_CLK ; CLOCK_50 ; ; 0.500 ; Fall ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[1] ; ; LED[*] ; CLOCK_50 ; 3.801 ; 3.845 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; @@ -3181,7 +3181,7 @@ Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. Number of Synchronizer Chains Found: 6 Shortest Synchronizer Chain: 2 Registers Fraction of Chains for which MTBFs Could Not be Calculated: 0.333 -Worst Case Available Settling Time: 17.094 ns +Worst Case Available Settling Time: 17.489 ns Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8 @@ -3195,8 +3195,8 @@ Typical MTBF values are calculated based on the nominal silicon characteristics, +------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+-------------------------+ ; ; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_rx:the_system_uart_wifi_rx|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 ; Greater than 1 Billion ; Yes ; ; GPIO_1[31] ; system:inst_cpu|system_uart_mc:uart_mc|system_uart_mc_rx:the_system_uart_mc_rx|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 ; Greater than 1 Billion ; Yes ; -; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3|din_s1 ; Greater than 1 Billion ; Yes ; ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer2|din_s1 ; Greater than 1 Billion ; Yes ; +; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3|din_s1 ; Greater than 1 Billion ; Yes ; ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_oci_debug:the_system_cpu_nios2_oci_debug|monitor_ready ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|din_s1 ; n/a ; Yes ; ; system:inst_cpu|system_cpu:cpu|hbreak_enabled ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 ; n/a ; Yes ; +------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+-------------------------+ @@ -3223,7 +3223,7 @@ Synchronizer Chain #1: Typical MTBF is Greater than 1 Billion Years ; Method of Synchronizer Identification ; User Specified ; ; ; ; ; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; ; Number of Synchronization Registers in Chain ; 2 ; ; ; ; -; Available Settling Time (ns) ; 17.094 ; ; ; ; +; Available Settling Time (ns) ; 17.489 ; ; ; ; ; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 12.5 ; ; ; ; ; Source Clock ; ; ; ; ; ; Unknown ; ; ; ; ; @@ -3231,8 +3231,8 @@ Synchronizer Chain #1: Typical MTBF is Greater than 1 Billion Years ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; 10.000 ; 100.0 MHz ; ; ; Asynchronous Source ; ; ; ; ; ; Synchronization Registers ; ; ; ; ; -; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_rx:the_system_uart_wifi_rx|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 ; ; ; ; 9.179 ; -; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_rx:the_system_uart_wifi_rx|altera_std_synchronizer:the_altera_std_synchronizer|dreg[0] ; ; ; ; 7.915 ; +; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_rx:the_system_uart_wifi_rx|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 ; ; ; ; 9.191 ; +; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_rx:the_system_uart_wifi_rx|altera_std_synchronizer:the_altera_std_synchronizer|dreg[0] ; ; ; ; 8.298 ; +-----------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ @@ -3258,7 +3258,7 @@ Synchronizer Chain #2: Typical MTBF is Greater than 1 Billion Years ; Method of Synchronizer Identification ; User Specified ; ; ; ; ; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; ; Number of Synchronization Registers in Chain ; 2 ; ; ; ; -; Available Settling Time (ns) ; 18.107 ; ; ; ; +; Available Settling Time (ns) ; 18.134 ; ; ; ; ; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 12.5 ; ; ; ; ; Source Clock ; ; ; ; ; ; Unknown ; ; ; ; ; @@ -3267,8 +3267,8 @@ Synchronizer Chain #2: Typical MTBF is Greater than 1 Billion Years ; Asynchronous Source ; ; ; ; ; ; GPIO_1[31] ; ; ; ; ; ; Synchronization Registers ; ; ; ; ; -; system:inst_cpu|system_uart_mc:uart_mc|system_uart_mc_rx:the_system_uart_mc_rx|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 ; ; ; ; 8.975 ; -; system:inst_cpu|system_uart_mc:uart_mc|system_uart_mc_rx:the_system_uart_mc_rx|altera_std_synchronizer:the_altera_std_synchronizer|dreg[0] ; ; ; ; 9.132 ; +; system:inst_cpu|system_uart_mc:uart_mc|system_uart_mc_rx:the_system_uart_mc_rx|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 ; ; ; ; 9.001 ; +; system:inst_cpu|system_uart_mc:uart_mc|system_uart_mc_rx:the_system_uart_mc_rx|altera_std_synchronizer:the_altera_std_synchronizer|dreg[0] ; ; ; ; 9.133 ; +---------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ @@ -3281,7 +3281,7 @@ Synchronizer Chain #3: Typical MTBF is Greater than 1 Billion Years ; Property ; Value ; +-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Source Node ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; -; Synchronization Node ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3|din_s1 ; +; Synchronization Node ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer2|din_s1 ; ; Typical MTBF (years) ; Greater than 1 Billion ; ; Included in Design MTBF ; Yes ; +-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ @@ -3294,7 +3294,7 @@ Synchronizer Chain #3: Typical MTBF is Greater than 1 Billion Years ; Method of Synchronizer Identification ; User Specified ; ; ; ; ; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; ; Number of Synchronization Registers in Chain ; 2 ; ; ; ; -; Available Settling Time (ns) ; 18.645 ; ; ; ; +; Available Settling Time (ns) ; 18.626 ; ; ; ; ; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 1.25 ; ; ; ; ; Source Clock ; ; ; ; ; ; altera_reserved_tck ; ; 100.000 ; 10.0 MHz ; ; @@ -3305,8 +3305,8 @@ Synchronizer Chain #3: Typical MTBF is Greater than 1 Billion Years ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; ; ; ; ; ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; ; ; ; ; ; Synchronization Registers ; ; ; ; ; -; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3|din_s1 ; ; ; ; 9.328 ; -; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3|dreg[0] ; ; ; ; 9.317 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer2|din_s1 ; ; ; ; 9.317 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer2|dreg[0] ; ; ; ; 9.309 ; +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ @@ -3319,7 +3319,7 @@ Synchronizer Chain #4: Typical MTBF is Greater than 1 Billion Years ; Property ; Value ; +-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Source Node ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; -; Synchronization Node ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer2|din_s1 ; +; Synchronization Node ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3|din_s1 ; ; Typical MTBF (years) ; Greater than 1 Billion ; ; Included in Design MTBF ; Yes ; +-------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ @@ -3332,7 +3332,7 @@ Synchronizer Chain #4: Typical MTBF is Greater than 1 Billion Years ; Method of Synchronizer Identification ; User Specified ; ; ; ; ; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; ; Number of Synchronization Registers in Chain ; 2 ; ; ; ; -; Available Settling Time (ns) ; 18.648 ; ; ; ; +; Available Settling Time (ns) ; 18.626 ; ; ; ; ; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 1.25 ; ; ; ; ; Source Clock ; ; ; ; ; ; altera_reserved_tck ; ; 100.000 ; 10.0 MHz ; ; @@ -3343,8 +3343,8 @@ Synchronizer Chain #4: Typical MTBF is Greater than 1 Billion Years ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; ; ; ; ; ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; ; ; ; ; ; Synchronization Registers ; ; ; ; ; -; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer2|din_s1 ; ; ; ; 9.329 ; -; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer2|dreg[0] ; ; ; ; 9.319 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3|din_s1 ; ; ; ; 9.318 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3|dreg[0] ; ; ; ; 9.308 ; +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ @@ -3426,7 +3426,7 @@ Synchronizer Chain #6: Typical MTBF is n/a Years +----------------------------------------------------------+--------+---------------+ ; Clock ; Slack ; End Point TNS ; +----------------------------------------------------------+--------+---------------+ -; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 3.218 ; 0.000 ; +; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 3.368 ; 0.000 ; ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 98.512 ; 0.000 ; +----------------------------------------------------------+--------+---------------+ @@ -3436,7 +3436,7 @@ Synchronizer Chain #6: Typical MTBF is n/a Years +----------------------------------------------------------+-------+---------------+ ; Clock ; Slack ; End Point TNS ; +----------------------------------------------------------+-------+---------------+ -; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.110 ; 0.000 ; +; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.102 ; 0.000 ; ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 0.193 ; 0.000 ; +----------------------------------------------------------+-------+---------------+ @@ -3446,7 +3446,7 @@ Synchronizer Chain #6: Typical MTBF is n/a Years +----------------------------------------------------------+-------+---------------+ ; Clock ; Slack ; End Point TNS ; +----------------------------------------------------------+-------+---------------+ -; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 3.339 ; 0.000 ; +; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 3.214 ; 0.000 ; +----------------------------------------------------------+-------+---------------+ @@ -3455,7 +3455,7 @@ Synchronizer Chain #6: Typical MTBF is n/a Years +----------------------------------------------------------+-------+---------------+ ; Clock ; Slack ; End Point TNS ; +----------------------------------------------------------+-------+---------------+ -; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 1.171 ; 0.000 ; +; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 1.443 ; 0.000 ; +----------------------------------------------------------+-------+---------------+ @@ -3466,7 +3466,7 @@ Synchronizer Chain #6: Typical MTBF is n/a Years +----------------------------------------------------------+--------+---------------+ ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 4.749 ; 0.000 ; ; CLOCK_50 ; 9.587 ; 0.000 ; -; altera_reserved_tck ; 49.482 ; 0.000 ; +; altera_reserved_tck ; 49.484 ; 0.000 ; ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 49.782 ; 0.000 ; +----------------------------------------------------------+--------+---------------+ @@ -3476,106 +3476,106 @@ Synchronizer Chain #6: Typical MTBF is n/a Years +-------+------------------------------------------------+-------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +-------+------------------------------------------------+-------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ -; 3.218 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[24] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.021 ; 1.748 ; -; 3.220 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[20] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.021 ; 1.746 ; -; 3.230 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.021 ; 1.736 ; -; 3.290 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.021 ; 1.676 ; -; 3.299 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.021 ; 1.667 ; -; 3.299 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[29] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.014 ; 1.674 ; -; 3.306 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[16] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.021 ; 1.660 ; -; 3.311 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[28] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.021 ; 1.655 ; -; 3.318 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[25] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.014 ; 1.655 ; -; 3.331 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[13] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[25] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.023 ; 1.633 ; -; 3.380 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.021 ; 1.586 ; -; 3.396 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[25] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.014 ; 1.577 ; -; 3.407 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[13] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.023 ; 1.557 ; -; 3.441 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[29] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.014 ; 1.532 ; -; 3.498 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[26] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.018 ; 1.471 ; -; 3.502 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[27] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.022 ; 1.463 ; -; 3.514 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.018 ; 1.455 ; -; 3.516 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.018 ; 1.453 ; -; 3.522 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[25] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.018 ; 1.447 ; -; 3.540 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[27] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.026 ; 1.421 ; -; 3.553 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[27] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.022 ; 1.412 ; -; 3.561 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[26] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[6] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.018 ; 1.408 ; -; 3.626 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[29] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.018 ; 1.343 ; -; 3.626 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.018 ; 1.343 ; -; 3.627 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.026 ; 1.334 ; -; 3.628 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.018 ; 1.341 ; -; 3.629 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[17] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.018 ; 1.340 ; -; 3.630 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.018 ; 1.339 ; -; 3.635 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[25] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[25] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.014 ; 1.338 ; -; 3.646 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[11] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.009 ; 1.332 ; -; 3.646 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[5] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.018 ; 1.323 ; -; 3.647 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[13] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.023 ; 1.317 ; -; 3.650 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[29] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[29] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.014 ; 1.323 ; -; 3.659 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[1] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.018 ; 1.310 ; -; 3.660 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.026 ; 1.301 ; -; 3.666 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[17] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[25] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.023 ; 1.298 ; -; 3.669 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[25] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[29] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.014 ; 1.304 ; -; 3.676 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[13] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[17] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.023 ; 1.288 ; -; 3.679 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[29] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.014 ; 1.294 ; -; 3.680 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[19] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[31] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.009 ; 1.298 ; -; 3.682 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[31] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.026 ; 1.279 ; -; 3.691 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[31] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.026 ; 1.270 ; -; 3.714 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.026 ; 1.247 ; -; 3.721 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.026 ; 1.240 ; -; 3.723 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[7] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.026 ; 1.238 ; -; 3.740 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[9] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[17] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.023 ; 1.224 ; -; 3.742 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[1] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.018 ; 1.227 ; -; 3.756 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[11] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[23] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.009 ; 1.222 ; -; 3.764 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[7] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.026 ; 1.197 ; -; 3.765 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[21] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[29] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.023 ; 1.199 ; -; 3.765 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[9] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.023 ; 1.199 ; -; 3.790 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[5] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[17] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.018 ; 1.179 ; -; 3.792 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[27] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[27] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.022 ; 1.173 ; -; 3.792 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[23] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.026 ; 1.169 ; -; 3.796 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[21] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.023 ; 1.168 ; -; 3.797 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.026 ; 1.164 ; -; 3.800 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[26] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[30] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.018 ; 1.169 ; -; 3.801 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[17] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[29] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.023 ; 1.163 ; -; 3.815 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[27] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[31] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.022 ; 1.150 ; -; 3.816 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[26] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[26] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.018 ; 1.153 ; -; 3.827 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[10] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[22] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.027 ; 1.133 ; -; 3.828 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[28] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.017 ; 1.142 ; -; 3.829 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[8] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[20] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.021 ; 1.137 ; -; 3.834 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[18] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[30] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.027 ; 1.126 ; -; 3.837 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[19] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[27] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.009 ; 1.141 ; -; 3.840 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[12] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[24] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.026 ; 1.121 ; -; 3.845 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[10] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[18] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.027 ; 1.115 ; -; 3.852 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[23] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[31] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.009 ; 1.126 ; -; 3.852 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[15] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[27] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.009 ; 1.126 ; -; 3.852 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[18] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[26] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.027 ; 1.108 ; -; 3.893 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[28] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.017 ; 1.077 ; -; 3.915 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[20] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[20] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.026 ; 1.046 ; -; 3.922 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[8] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[16] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.021 ; 1.044 ; -; 3.925 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[31] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.026 ; 1.036 ; -; 3.931 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[15] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[23] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.009 ; 1.047 ; -; 3.931 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[20] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.026 ; 1.030 ; -; 3.951 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[30] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.022 ; 1.014 ; -; 3.958 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[30] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[6] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.018 ; 1.011 ; -; 3.960 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[30] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.018 ; 1.009 ; -; 3.961 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[11] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.009 ; 1.017 ; -; 3.967 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.022 ; 0.998 ; -; 3.969 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[26] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.022 ; 0.996 ; -; 3.973 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[22] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.027 ; 0.987 ; -; 3.973 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[22] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[30] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.027 ; 0.987 ; -; 3.977 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[9] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.023 ; 0.987 ; -; 3.980 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[1] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.018 ; 0.989 ; -; 3.987 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[3] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.026 ; 0.974 ; -; 3.987 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[3] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.026 ; 0.974 ; -; 3.987 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[3] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.026 ; 0.974 ; -; 3.987 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[3] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[27] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.026 ; 0.974 ; -; 3.987 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[3] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.026 ; 0.974 ; -; 3.987 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[3] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[23] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.026 ; 0.974 ; -; 3.987 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[3] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.026 ; 0.974 ; -; 3.987 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[3] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[31] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.026 ; 0.974 ; -; 3.990 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[14] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.022 ; 0.975 ; -; 3.991 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[0] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.021 ; 0.975 ; -; 3.992 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[14] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[26] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.027 ; 0.968 ; -; 3.995 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[31] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[31] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.026 ; 0.966 ; -; 3.996 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[11] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.009 ; 0.982 ; -; 3.996 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[3] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.018 ; 0.973 ; +; 3.368 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[30] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[6] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.040 ; 1.579 ; +; 3.397 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[30] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.040 ; 1.550 ; +; 3.409 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.016 ; 1.562 ; +; 3.428 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[31] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.016 ; 1.543 ; +; 3.437 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[27] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.016 ; 1.534 ; +; 3.457 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.016 ; 1.514 ; +; 3.547 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.016 ; 1.424 ; +; 3.552 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.016 ; 1.419 ; +; 3.587 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.016 ; 1.384 ; +; 3.592 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[19] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[27] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.011 ; 1.384 ; +; 3.599 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[24] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.015 ; 1.373 ; +; 3.606 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[26] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.040 ; 1.341 ; +; 3.607 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.015 ; 1.365 ; +; 3.613 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[23] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.016 ; 1.358 ; +; 3.615 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.015 ; 1.357 ; +; 3.626 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[25] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.041 ; 1.320 ; +; 3.628 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[20] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.015 ; 1.344 ; +; 3.647 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[29] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.041 ; 1.299 ; +; 3.650 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[26] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[6] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.040 ; 1.297 ; +; 3.662 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[24] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.031 ; 1.294 ; +; 3.681 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[23] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.011 ; 1.295 ; +; 3.685 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[27] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.032 ; 1.270 ; +; 3.685 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[30] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[30] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.040 ; 1.262 ; +; 3.685 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[16] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.015 ; 1.287 ; +; 3.690 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[28] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.015 ; 1.282 ; +; 3.697 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.015 ; 1.275 ; +; 3.697 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[6] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[14] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.027 ; 1.263 ; +; 3.697 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[23] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[31] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.011 ; 1.279 ; +; 3.698 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.015 ; 1.274 ; +; 3.701 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[29] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.041 ; 1.245 ; +; 3.713 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[5] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.028 ; 1.246 ; +; 3.715 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[30] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.040 ; 1.232 ; +; 3.726 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[6] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[18] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.027 ; 1.234 ; +; 3.739 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[25] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.041 ; 1.207 ; +; 3.747 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[19] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[31] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.011 ; 1.229 ; +; 3.749 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[31] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.019 ; 1.219 ; +; 3.750 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[24] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.031 ; 1.206 ; +; 3.753 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.024 ; 1.210 ; +; 3.754 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.025 ; 1.208 ; +; 3.757 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.025 ; 1.205 ; +; 3.758 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.025 ; 1.204 ; +; 3.758 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.025 ; 1.204 ; +; 3.763 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[29] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.025 ; 1.199 ; +; 3.764 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[25] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.025 ; 1.198 ; +; 3.767 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.024 ; 1.196 ; +; 3.768 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[14] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.024 ; 1.195 ; +; 3.771 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[26] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.024 ; 1.192 ; +; 3.772 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[22] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.024 ; 1.191 ; +; 3.773 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[18] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.024 ; 1.190 ; +; 3.777 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[6] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.024 ; 1.186 ; +; 3.797 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[20] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.010 ; 1.180 ; +; 3.798 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[20] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[28] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.010 ; 1.179 ; +; 3.803 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[28] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.031 ; 1.153 ; +; 3.805 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[16] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[28] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.010 ; 1.172 ; +; 3.811 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[10] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[18] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.027 ; 1.149 ; +; 3.818 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.027 ; 1.142 ; +; 3.825 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[5] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[17] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.028 ; 1.134 ; +; 3.825 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[14] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[22] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.019 ; 1.143 ; +; 3.830 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[1] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.028 ; 1.129 ; +; 3.839 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.025 ; 1.123 ; +; 3.840 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[9] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.028 ; 1.119 ; +; 3.842 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[16] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[24] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.010 ; 1.135 ; +; 3.842 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[17] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.025 ; 1.120 ; +; 3.843 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[10] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[22] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.027 ; 1.117 ; +; 3.846 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[30] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.024 ; 1.117 ; +; 3.848 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[2] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[14] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.027 ; 1.112 ; +; 3.851 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[14] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[26] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.019 ; 1.117 ; +; 3.856 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[17] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[25] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.020 ; 1.111 ; +; 3.858 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[0] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.018 ; 1.111 ; +; 3.864 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[18] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[26] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.019 ; 1.104 ; +; 3.865 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[1] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.028 ; 1.094 ; +; 3.867 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[22] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.019 ; 1.101 ; +; 3.877 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[15] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[27] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.011 ; 1.099 ; +; 3.885 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[28] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.031 ; 1.071 ; +; 3.887 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[17] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[29] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.020 ; 1.080 ; +; 3.893 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[9] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[17] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.028 ; 1.066 ; +; 3.895 ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[0] ; system:inst_cpu|system_cpu:cpu|A_rot[16] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.051 ; 1.041 ; +; 3.896 ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[0] ; system:inst_cpu|system_cpu:cpu|A_rot[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.051 ; 1.040 ; +; 3.907 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[11] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.019 ; 1.061 ; +; 3.908 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[31] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.019 ; 1.060 ; +; 3.911 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[19] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.011 ; 1.065 ; +; 3.928 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[22] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[30] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.019 ; 1.040 ; +; 3.934 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[3] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[16] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.015 ; 1.038 ; +; 3.934 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[3] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[20] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.015 ; 1.038 ; +; 3.934 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[3] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.025 ; 1.028 ; +; 3.934 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[3] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[28] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.015 ; 1.038 ; +; 3.934 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[3] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.015 ; 1.038 ; +; 3.934 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[3] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[29] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.025 ; 1.028 ; +; 3.934 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[3] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.015 ; 1.038 ; +; 3.934 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[3] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.025 ; 1.028 ; +; 3.934 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[3] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[17] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.025 ; 1.028 ; +; 3.934 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[3] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.015 ; 1.038 ; +; 3.934 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[3] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[24] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.015 ; 1.038 ; +; 3.934 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[3] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[25] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.025 ; 1.028 ; +; 3.934 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[3] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.025 ; 1.028 ; +; 3.934 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[3] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.015 ; 1.038 ; +; 3.934 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[3] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.025 ; 1.028 ; +; 3.934 ; system:inst_cpu|system_cpu:cpu|M_rot_rn[3] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.025 ; 1.028 ; +; 3.937 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[29] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[29] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.041 ; 1.009 ; +; 3.937 ; system:inst_cpu|system_cpu:cpu|M_rot_step1[26] ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[26] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.040 ; 1.010 ; +-------+------------------------------------------------+-------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ @@ -3692,106 +3692,106 @@ Synchronizer Chain #6: Typical MTBF is n/a Years +-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ -; 0.110 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[10] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.227 ; 0.441 ; -; 0.113 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[5] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a0~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.228 ; 0.445 ; -; 0.141 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|data_to_uart[0] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.221 ; 0.466 ; -; 0.142 ; system:inst_cpu|system_cpu:cpu|ic_fill_valid_bits[7] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.222 ; 0.468 ; -; 0.143 ; system:inst_cpu|system_cpu:cpu|ic_fill_valid_bits[2] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.222 ; 0.469 ; -; 0.144 ; system:inst_cpu|system_cpu:cpu|A_dc_xfer_wr_data[3] ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_victim_module:system_cpu_dc_victim|altsyncram:the_altsyncram|altsyncram_r3d1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.224 ; 0.472 ; -; 0.144 ; system:inst_cpu|system_cpu:cpu|M_bht_ptr_unfiltered[0] ; system:inst_cpu|system_cpu:cpu|system_cpu_bht_module:system_cpu_bht|altsyncram:the_altsyncram|altsyncram_fhg1:auto_generated|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.223 ; 0.471 ; -; 0.144 ; system:inst_cpu|system_cpu:cpu|M_bht_ptr_unfiltered[4] ; system:inst_cpu|system_cpu:cpu|system_cpu_bht_module:system_cpu_bht|altsyncram:the_altsyncram|altsyncram_fhg1:auto_generated|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.219 ; 0.467 ; -; 0.145 ; system:inst_cpu|system_cpu:cpu|M_bht_ptr_unfiltered[3] ; system:inst_cpu|system_cpu:cpu|system_cpu_bht_module:system_cpu_bht|altsyncram:the_altsyncram|altsyncram_fhg1:auto_generated|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.223 ; 0.472 ; -; 0.145 ; system:inst_cpu|system_cpu:cpu|ic_tag_wraddress[7] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.222 ; 0.471 ; -; 0.146 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[8] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.226 ; 0.476 ; -; 0.147 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[3] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.223 ; 0.474 ; -; 0.148 ; system:inst_cpu|system_cpu:cpu|i_readdata_d1[16] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a9~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.222 ; 0.474 ; -; 0.148 ; system:inst_cpu|system_cpu:cpu|A_dc_wb_rd_addr_offset[2] ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_victim_module:system_cpu_dc_victim|altsyncram:the_altsyncram|altsyncram_r3d1:auto_generated|ram_block1a0~portb_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.224 ; 0.476 ; -; 0.149 ; system:inst_cpu|system_cpu:cpu|ic_tag_wraddress[5] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.222 ; 0.475 ; -; 0.149 ; system:inst_cpu|system_cpu:cpu|ic_fill_valid_bits[1] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.222 ; 0.475 ; -; 0.149 ; system:inst_cpu|system_cpu:cpu|ic_fill_valid_bits[4] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.222 ; 0.475 ; -; 0.149 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|data_in_shift_reg[1] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.221 ; 0.474 ; -; 0.150 ; system:inst_cpu|system_cpu:cpu|ic_fill_valid_bits[0] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.222 ; 0.476 ; -; 0.150 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|data_in_shift_reg[2] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.221 ; 0.475 ; -; 0.151 ; system:inst_cpu|system_cpu:cpu|M_bht_ptr_unfiltered[5] ; system:inst_cpu|system_cpu:cpu|system_cpu_bht_module:system_cpu_bht|altsyncram:the_altsyncram|altsyncram_fhg1:auto_generated|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.223 ; 0.478 ; -; 0.152 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[6] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a0~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.227 ; 0.483 ; -; 0.152 ; system:inst_cpu|system_cpu:cpu|A_dc_wb_rd_addr_offset[1] ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_victim_module:system_cpu_dc_victim|altsyncram:the_altsyncram|altsyncram_r3d1:auto_generated|ram_block1a0~portb_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.224 ; 0.480 ; -; 0.152 ; system:inst_cpu|system_cpu:cpu|ic_fill_valid_bits[5] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.222 ; 0.478 ; -; 0.152 ; system:inst_cpu|system_cpu:cpu|ic_fill_tag[11] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.225 ; 0.481 ; -; 0.152 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|data_in_shift_reg[5] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.221 ; 0.477 ; -; 0.153 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[14] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.226 ; 0.483 ; -; 0.153 ; system:inst_cpu|system_cpu:cpu|A_dc_xfer_wr_data[16] ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_victim_module:system_cpu_dc_victim|altsyncram:the_altsyncram|altsyncram_r3d1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.224 ; 0.481 ; -; 0.153 ; system:inst_cpu|system_cpu:cpu|ic_fill_valid_bits[6] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.222 ; 0.479 ; -; 0.154 ; system:inst_cpu|system_cpu:cpu|A_dc_xfer_wr_data[29] ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_victim_module:system_cpu_dc_victim|altsyncram:the_altsyncram|altsyncram_r3d1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.224 ; 0.482 ; -; 0.154 ; system:inst_cpu|system_cpu:cpu|ic_fill_tag[4] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.225 ; 0.483 ; -; 0.154 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|data_in_shift_reg[7] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.221 ; 0.479 ; -; 0.154 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[0] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.221 ; 0.479 ; -; 0.154 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|data_to_uart[5] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.221 ; 0.479 ; -; 0.155 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[29] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.227 ; 0.486 ; -; 0.155 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[17] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a0~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.226 ; 0.485 ; -; 0.155 ; system:inst_cpu|system_cpu:cpu|ic_fill_tag[7] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.225 ; 0.484 ; -; 0.155 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[2] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.221 ; 0.480 ; -; 0.156 ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[2] ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.222 ; 0.482 ; -; 0.156 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[30] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.226 ; 0.486 ; -; 0.156 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[20] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a0~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.226 ; 0.486 ; -; 0.156 ; system:inst_cpu|system_cpu:cpu|A_dc_xfer_wr_data[30] ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_victim_module:system_cpu_dc_victim|altsyncram:the_altsyncram|altsyncram_r3d1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.224 ; 0.484 ; -; 0.156 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[0] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.223 ; 0.483 ; -; 0.157 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[16] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a0~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.226 ; 0.487 ; -; 0.157 ; system:inst_cpu|system_cpu:cpu|ic_tag_wraddress[6] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.222 ; 0.483 ; -; 0.158 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[26] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.226 ; 0.488 ; -; 0.158 ; system:inst_cpu|system_cpu:cpu|ic_tag_wraddress[3] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.222 ; 0.484 ; -; 0.158 ; system:inst_cpu|system_cpu:cpu|ic_fill_valid_bits[3] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.222 ; 0.484 ; -; 0.158 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[1] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.221 ; 0.483 ; -; 0.158 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[3] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.221 ; 0.483 ; -; 0.159 ; system:inst_cpu|system_cpu:cpu|ic_fill_dp_offset[1] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a27~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.222 ; 0.485 ; -; 0.159 ; system:inst_cpu|system_cpu:cpu|ic_fill_tag[2] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.225 ; 0.488 ; -; 0.159 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[4] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.221 ; 0.484 ; -; 0.160 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|data_in_shift_reg[4] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.221 ; 0.485 ; -; 0.160 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|data_in_shift_reg[6] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.221 ; 0.485 ; -; 0.161 ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[0] ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.222 ; 0.487 ; -; 0.161 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[2] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a0~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.227 ; 0.492 ; -; 0.161 ; system:inst_cpu|system_cpu:cpu|ic_fill_tag[9] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.225 ; 0.490 ; -; 0.163 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonAReg[5] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.225 ; 0.492 ; -; 0.163 ; system:inst_cpu|system_cpu:cpu|ic_tag_wraddress[2] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.222 ; 0.489 ; -; 0.163 ; system:inst_cpu|system_cpu:cpu|ic_fill_tag[0] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.225 ; 0.492 ; -; 0.163 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|data_in_shift_reg[8] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.221 ; 0.488 ; -; 0.163 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|data_to_uart[1] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.221 ; 0.488 ; -; 0.164 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonAReg[7] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.225 ; 0.493 ; -; 0.164 ; system:inst_cpu|system_cpu:cpu|ic_tag_wraddress[0] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.222 ; 0.490 ; -; 0.164 ; system:inst_cpu|system_cpu:cpu|ic_tag_wraddress[1] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.222 ; 0.490 ; -; 0.165 ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[1] ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.222 ; 0.491 ; -; 0.165 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|data_to_uart[3] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.217 ; 0.486 ; -; 0.166 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[19] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a0~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.226 ; 0.496 ; -; 0.166 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[22] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a0~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.226 ; 0.496 ; -; 0.166 ; system:inst_cpu|system_cpu:cpu|M_bht_ptr_unfiltered[1] ; system:inst_cpu|system_cpu:cpu|system_cpu_bht_module:system_cpu_bht|altsyncram:the_altsyncram|altsyncram_fhg1:auto_generated|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.223 ; 0.493 ; -; 0.166 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|data_in_shift_reg[3] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.221 ; 0.491 ; -; 0.167 ; system:inst_cpu|system_cpu:cpu|ic_fill_tag[12] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.225 ; 0.496 ; -; 0.167 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|data_to_uart[6] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.217 ; 0.488 ; -; 0.168 ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[4] ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.222 ; 0.494 ; -; 0.168 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[27] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.226 ; 0.498 ; -; 0.168 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[2] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.223 ; 0.495 ; -; 0.169 ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[3] ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.222 ; 0.495 ; -; 0.169 ; system:inst_cpu|system_cpu:cpu|ic_tag_wraddress[4] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.222 ; 0.495 ; -; 0.170 ; system:inst_cpu|system_cpu:cpu|ic_fill_dp_offset[0] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a27~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.222 ; 0.496 ; -; 0.171 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[25] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.226 ; 0.501 ; -; 0.171 ; system:inst_cpu|system_cpu:cpu|ic_fill_tag[3] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.225 ; 0.500 ; -; 0.172 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[11] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.227 ; 0.503 ; -; 0.172 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|data_to_uart[4] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.217 ; 0.493 ; -; 0.173 ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[5] ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.222 ; 0.499 ; -; 0.173 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|data_to_uart[7] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.217 ; 0.494 ; -; 0.175 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[4] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.223 ; 0.502 ; -; 0.175 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[6] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.221 ; 0.500 ; -; 0.176 ; system:inst_cpu|system_cpu:cpu|A_dc_wb_rd_addr_offset[0] ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_victim_module:system_cpu_dc_victim|altsyncram:the_altsyncram|altsyncram_r3d1:auto_generated|ram_block1a0~portb_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.224 ; 0.504 ; -; 0.177 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|data_to_uart[2] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.217 ; 0.498 ; -; 0.178 ; system:inst_cpu|system_cpu:cpu|ic_fill_tag[5] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.225 ; 0.507 ; -; 0.182 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonAReg[2] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.225 ; 0.511 ; -; 0.182 ; system:inst_cpu|system_cpu:cpu|ic_fill_dp_offset[2] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a27~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.222 ; 0.508 ; -; 0.183 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonAReg[6] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.225 ; 0.512 ; -; 0.185 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonAReg[9] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.225 ; 0.514 ; -; 0.185 ; system:inst_cpu|system_cpu:cpu|ic_fill_tag[1] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.225 ; 0.514 ; -; 0.186 ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entries[1] ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entries[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.307 ; +; 0.102 ; system:inst_cpu|system_cpu:cpu|ic_fill_valid_bits[0] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.220 ; 0.426 ; +; 0.103 ; system:inst_cpu|system_cpu:cpu|ic_fill_valid_bits[5] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.220 ; 0.427 ; +; 0.104 ; system:inst_cpu|system_cpu:cpu|ic_fill_valid_bits[2] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.220 ; 0.428 ; +; 0.143 ; system:inst_cpu|system_cpu:cpu|M_bht_ptr_unfiltered[0] ; system:inst_cpu|system_cpu:cpu|system_cpu_bht_module:system_cpu_bht|altsyncram:the_altsyncram|altsyncram_fhg1:auto_generated|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.219 ; 0.466 ; +; 0.144 ; system:inst_cpu|system_cpu:cpu|i_readdata_d1[18] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a18~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.222 ; 0.470 ; +; 0.144 ; system:inst_cpu|system_cpu:cpu|M_bht_ptr_unfiltered[1] ; system:inst_cpu|system_cpu:cpu|system_cpu_bht_module:system_cpu_bht|altsyncram:the_altsyncram|altsyncram_fhg1:auto_generated|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.219 ; 0.467 ; +; 0.145 ; system:inst_cpu|system_cpu:cpu|i_readdata_d1[31] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a22~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.221 ; 0.470 ; +; 0.146 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|data_to_uart[6] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.221 ; 0.471 ; +; 0.146 ; system:inst_cpu|system_cpu:cpu|i_readdata_d1[0] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.221 ; 0.471 ; +; 0.147 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[2] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.222 ; 0.473 ; +; 0.147 ; system:inst_cpu|system_cpu:cpu|i_readdata_d1[20] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a18~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.222 ; 0.473 ; +; 0.147 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[28] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.222 ; 0.473 ; +; 0.148 ; system:inst_cpu|system_cpu:cpu|i_readdata_d1[21] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a18~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.222 ; 0.474 ; +; 0.148 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[4] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a0~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.224 ; 0.476 ; +; 0.148 ; system:inst_cpu|system_cpu:cpu|i_readdata_d1[1] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.221 ; 0.473 ; +; 0.148 ; system:inst_cpu|system_cpu:cpu|i_readdata_d1[2] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.225 ; 0.477 ; +; 0.149 ; system:inst_cpu|system_cpu:cpu|i_readdata_d1[3] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.226 ; 0.479 ; +; 0.150 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|data_in_shift_reg[1] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.223 ; 0.477 ; +; 0.150 ; system:inst_cpu|system_cpu:cpu|i_readdata_d1[19] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a18~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.222 ; 0.476 ; +; 0.150 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[8] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.226 ; 0.480 ; +; 0.150 ; system:inst_cpu|system_cpu:cpu|M_bht_ptr_unfiltered[3] ; system:inst_cpu|system_cpu:cpu|system_cpu_bht_module:system_cpu_bht|altsyncram:the_altsyncram|altsyncram_fhg1:auto_generated|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.219 ; 0.473 ; +; 0.151 ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[2] ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.220 ; 0.475 ; +; 0.151 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[25] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.222 ; 0.477 ; +; 0.151 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[26] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.222 ; 0.477 ; +; 0.152 ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[3] ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.220 ; 0.476 ; +; 0.152 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[3] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.221 ; 0.477 ; +; 0.152 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[1] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.222 ; 0.478 ; +; 0.152 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[4] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.222 ; 0.478 ; +; 0.152 ; system:inst_cpu|system_cpu:cpu|ic_fill_valid_bits[7] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.220 ; 0.476 ; +; 0.153 ; system:inst_cpu|system_cpu:cpu|M_bht_ptr_unfiltered[4] ; system:inst_cpu|system_cpu:cpu|system_cpu_bht_module:system_cpu_bht|altsyncram:the_altsyncram|altsyncram_fhg1:auto_generated|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.219 ; 0.476 ; +; 0.154 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[1] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.221 ; 0.479 ; +; 0.154 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|data_in_shift_reg[4] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.223 ; 0.481 ; +; 0.154 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|data_in_shift_reg[7] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.223 ; 0.481 ; +; 0.154 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[6] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a0~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.225 ; 0.483 ; +; 0.154 ; system:inst_cpu|system_cpu:cpu|ic_fill_valid_bits[1] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.220 ; 0.478 ; +; 0.156 ; system:inst_cpu|system_cpu:cpu|ic_fill_valid_bits[4] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.220 ; 0.480 ; +; 0.157 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[0] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.221 ; 0.482 ; +; 0.157 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|data_in_shift_reg[8] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.223 ; 0.484 ; +; 0.157 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[22] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a0~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.222 ; 0.483 ; +; 0.158 ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[5] ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.220 ; 0.482 ; +; 0.158 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[12] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.224 ; 0.486 ; +; 0.159 ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[1] ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.227 ; 0.490 ; +; 0.159 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|data_in_shift_reg[5] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.223 ; 0.486 ; +; 0.159 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[31] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.222 ; 0.485 ; +; 0.159 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[0] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a0~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.225 ; 0.488 ; +; 0.160 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[9] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.224 ; 0.488 ; +; 0.160 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[14] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.226 ; 0.490 ; +; 0.160 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[3] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a0~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.224 ; 0.488 ; +; 0.160 ; system:inst_cpu|system_cpu:cpu|M_bht_ptr_unfiltered[7] ; system:inst_cpu|system_cpu:cpu|system_cpu_bht_module:system_cpu_bht|altsyncram:the_altsyncram|altsyncram_fhg1:auto_generated|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.219 ; 0.483 ; +; 0.161 ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[4] ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.220 ; 0.485 ; +; 0.161 ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[0] ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.227 ; 0.492 ; +; 0.161 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[6] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.221 ; 0.486 ; +; 0.161 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|data_in_shift_reg[2] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.223 ; 0.488 ; +; 0.161 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[6] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.222 ; 0.487 ; +; 0.161 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[7] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a0~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.222 ; 0.487 ; +; 0.162 ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[4] ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.227 ; 0.493 ; +; 0.162 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[2] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.221 ; 0.487 ; +; 0.162 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|data_to_uart[2] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.224 ; 0.490 ; +; 0.162 ; system:inst_cpu|system_cpu:cpu|ic_fill_valid_bits[3] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.220 ; 0.486 ; +; 0.163 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|data_in_shift_reg[3] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.223 ; 0.490 ; +; 0.163 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonAReg[2] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.221 ; 0.488 ; +; 0.164 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[29] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.227 ; 0.495 ; +; 0.164 ; system:inst_cpu|system_cpu:cpu|ic_fill_valid_bits[6] ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.220 ; 0.488 ; +; 0.165 ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[1] ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.220 ; 0.489 ; +; 0.165 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[5] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a0~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.222 ; 0.491 ; +; 0.165 ; system:inst_cpu|system_cpu:cpu|M_bht_ptr_unfiltered[2] ; system:inst_cpu|system_cpu:cpu|system_cpu_bht_module:system_cpu_bht|altsyncram:the_altsyncram|altsyncram_fhg1:auto_generated|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.223 ; 0.492 ; +; 0.166 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[13] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.224 ; 0.494 ; +; 0.166 ; system:inst_cpu|system_cpu:cpu|M_bht_ptr_unfiltered[5] ; system:inst_cpu|system_cpu:cpu|system_cpu_bht_module:system_cpu_bht|altsyncram:the_altsyncram|altsyncram_fhg1:auto_generated|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.219 ; 0.489 ; +; 0.167 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[30] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.222 ; 0.493 ; +; 0.168 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|data_in_shift_reg[6] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.223 ; 0.495 ; +; 0.168 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[3] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.222 ; 0.494 ; +; 0.168 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|data_to_uart[0] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.219 ; 0.491 ; +; 0.168 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|data_to_uart[1] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.219 ; 0.491 ; +; 0.168 ; system:inst_cpu|system_cpu:cpu|A_dc_xfer_wr_offset[2] ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_victim_module:system_cpu_dc_victim|altsyncram:the_altsyncram|altsyncram_r3d1:auto_generated|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.219 ; 0.491 ; +; 0.168 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[20] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a0~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.224 ; 0.496 ; +; 0.171 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[11] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.226 ; 0.501 ; +; 0.171 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[21] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a0~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.222 ; 0.497 ; +; 0.172 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[1] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a0~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.222 ; 0.498 ; +; 0.173 ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[3] ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.227 ; 0.504 ; +; 0.173 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[16] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a0~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.222 ; 0.499 ; +; 0.174 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[5] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.222 ; 0.500 ; +; 0.174 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[2] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a0~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.225 ; 0.503 ; +; 0.174 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[18] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a0~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.222 ; 0.500 ; +; 0.175 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonAReg[5] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a0~portb_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.219 ; 0.498 ; +; 0.177 ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|cntr_1ob:wr_ptr|counter_reg_bit[5] ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.227 ; 0.508 ; +; 0.177 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[5] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.221 ; 0.502 ; +; 0.177 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[15] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.224 ; 0.505 ; +; 0.178 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[17] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a0~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.224 ; 0.506 ; +; 0.180 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[27] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.222 ; 0.506 ; +; 0.183 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[4] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.221 ; 0.508 ; +; 0.184 ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|cntr_0ab:wr_ptr|counter_reg_bit[0] ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_address_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.222 ; 0.510 ; +; 0.184 ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|MonDReg[19] ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a0~portb_datain_reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.222 ; 0.510 ; +; 0.186 ; system:inst_cpu|system_cpu:cpu|A_dc_wr_data_cnt[1] ; system:inst_cpu|system_cpu:cpu|A_dc_wr_data_cnt[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.307 ; +; 0.186 ; system:inst_cpu|system_cpu:cpu|A_dc_wr_data_cnt[2] ; system:inst_cpu|system_cpu:cpu|A_dc_wr_data_cnt[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.307 ; +; 0.186 ; system:inst_cpu|system_cpu:cpu|A_dc_wb_wr_active ; system:inst_cpu|system_cpu:cpu|A_dc_wb_wr_active ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.307 ; +; 0.186 ; system:inst_cpu|system_cpu:cpu|A_dc_wb_active ; system:inst_cpu|system_cpu:cpu|A_dc_wb_active ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.307 ; +; 0.186 ; system:inst_cpu|system_cpu:cpu|A_dc_wb_rd_addr_offset[1] ; system:inst_cpu|system_cpu:cpu|A_dc_wb_rd_addr_offset[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.307 ; +; 0.186 ; system:inst_cpu|system_cpu:cpu|A_dc_wb_rd_addr_offset[2] ; system:inst_cpu|system_cpu:cpu|A_dc_wb_rd_addr_offset[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.307 ; ; 0.186 ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.307 ; ; 0.186 ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|b_full ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|b_full ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.307 ; -; 0.186 ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[13] ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.037 ; 0.307 ; +-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ @@ -3908,215 +3908,215 @@ Synchronizer Chain #6: Typical MTBF is n/a Years +-------+-------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +-------+-------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ -; 3.339 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.034 ; 1.614 ; -; 3.339 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[6] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.035 ; 1.613 ; -; 3.339 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.034 ; 1.614 ; -; 3.339 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[22] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.035 ; 1.613 ; -; 3.339 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.035 ; 1.613 ; -; 3.339 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[26] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.035 ; 1.613 ; -; 3.339 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[18] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.035 ; 1.613 ; -; 3.339 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[28] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.034 ; 1.614 ; -; 3.339 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[20] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.034 ; 1.614 ; -; 3.339 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.034 ; 1.614 ; -; 3.339 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.031 ; 1.617 ; -; 3.339 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[17] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.031 ; 1.617 ; -; 3.339 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[29] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.031 ; 1.617 ; -; 3.339 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.031 ; 1.617 ; -; 3.339 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.034 ; 1.614 ; -; 3.339 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[16] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.034 ; 1.614 ; -; 3.339 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.031 ; 1.617 ; -; 3.339 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[25] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.031 ; 1.617 ; -; 3.339 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.031 ; 1.617 ; -; 3.339 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[24] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.034 ; 1.614 ; -; 3.339 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.031 ; 1.617 ; -; 3.339 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.035 ; 1.613 ; -; 3.339 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[30] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.035 ; 1.613 ; -; 3.339 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[14] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.035 ; 1.613 ; -; 3.339 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.028 ; 1.620 ; -; 3.339 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.028 ; 1.620 ; -; 3.339 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.028 ; 1.620 ; -; 3.339 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[27] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.028 ; 1.620 ; -; 3.339 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.028 ; 1.620 ; -; 3.339 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[23] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.028 ; 1.620 ; -; 3.339 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.028 ; 1.620 ; -; 3.339 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[31] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.028 ; 1.620 ; -; 8.054 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.106 ; 1.777 ; -; 8.054 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.107 ; 1.776 ; -; 8.055 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.107 ; 1.775 ; -; 8.055 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[14] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.105 ; 1.777 ; -; 8.055 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.105 ; 1.777 ; -; 8.055 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.109 ; 1.773 ; -; 8.055 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.105 ; 1.777 ; -; 8.055 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.105 ; 1.777 ; -; 8.055 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.105 ; 1.777 ; -; 8.087 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.060 ; 1.793 ; -; 8.087 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[6] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.060 ; 1.793 ; -; 8.088 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.063 ; 1.789 ; -; 8.088 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.063 ; 1.789 ; -; 8.089 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.114 ; 1.735 ; -; 8.089 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[6] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.114 ; 1.735 ; -; 8.090 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.117 ; 1.731 ; -; 8.090 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.117 ; 1.731 ; -; 8.090 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.074 ; 1.776 ; -; 8.090 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.069 ; 1.781 ; -; 8.090 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.074 ; 1.776 ; -; 8.090 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.066 ; 1.784 ; -; 8.090 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.066 ; 1.784 ; -; 8.091 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.070 ; 1.779 ; -; 8.092 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.128 ; 1.718 ; -; 8.092 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.068 ; 1.780 ; -; 8.092 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.068 ; 1.780 ; -; 8.092 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.120 ; 1.726 ; -; 8.092 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.120 ; 1.726 ; -; 8.098 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.072 ; 1.770 ; -; 8.099 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.060 ; 1.780 ; -; 8.099 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.060 ; 1.780 ; -; 8.099 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.061 ; 1.779 ; -; 8.099 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.061 ; 1.779 ; -; 8.099 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.060 ; 1.780 ; -; 8.100 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.060 ; 1.779 ; -; 8.100 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.058 ; 1.781 ; -; 8.100 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[6] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.060 ; 1.779 ; -; 8.100 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.063 ; 1.776 ; -; 8.100 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.061 ; 1.778 ; -; 8.100 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.059 ; 1.780 ; -; 8.100 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.059 ; 1.780 ; -; 8.100 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.059 ; 1.780 ; -; 8.100 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.063 ; 1.776 ; -; 8.100 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.059 ; 1.780 ; -; 8.100 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[14] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.059 ; 1.780 ; -; 8.100 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_dqm[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.063 ; 1.776 ; -; 8.100 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_dqm[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.063 ; 1.776 ; -; 8.100 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_bank[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.061 ; 1.778 ; -; 8.100 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_bank[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.060 ; 1.779 ; -; 8.188 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_2 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.060 ; 1.680 ; -; 8.188 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_5 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.068 ; 1.672 ; -; 8.188 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_6 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.068 ; 1.672 ; -; 8.188 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_8 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.059 ; 1.681 ; -; 8.189 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_15 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.071 ; 1.668 ; -; 8.189 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_4 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.071 ; 1.668 ; -; 8.189 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_7 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.060 ; 1.679 ; -; 8.189 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_9 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.058 ; 1.681 ; -; 8.189 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_10 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.058 ; 1.681 ; -; 8.189 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_11 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.058 ; 1.681 ; -; 8.189 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_12 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.062 ; 1.677 ; -; 8.189 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_13 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.058 ; 1.681 ; -; 8.189 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_14 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.058 ; 1.681 ; -; 8.191 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_3 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.082 ; 1.655 ; -; 8.191 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.074 ; 1.663 ; -; 8.191 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_1 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.074 ; 1.663 ; -; 8.205 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_cmd[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.064 ; 1.671 ; -; 8.205 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_cmd[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.064 ; 1.671 ; -; 8.210 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_cmd[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.061 ; 1.668 ; +; 3.214 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[16] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.034 ; 1.739 ; +; 3.214 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.035 ; 1.738 ; +; 3.214 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[20] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.034 ; 1.739 ; +; 3.214 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.044 ; 1.729 ; +; 3.214 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[27] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.035 ; 1.738 ; +; 3.214 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[28] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.034 ; 1.739 ; +; 3.214 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.034 ; 1.739 ; +; 3.214 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.035 ; 1.738 ; +; 3.214 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[29] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.044 ; 1.729 ; +; 3.214 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.034 ; 1.739 ; +; 3.214 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.035 ; 1.738 ; +; 3.214 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.044 ; 1.729 ; +; 3.214 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[17] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.044 ; 1.729 ; +; 3.214 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.034 ; 1.739 ; +; 3.214 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[24] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.034 ; 1.739 ; +; 3.214 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[23] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.035 ; 1.738 ; +; 3.214 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[6] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.043 ; 1.730 ; +; 3.214 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[31] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.035 ; 1.738 ; +; 3.214 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.035 ; 1.738 ; +; 3.214 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[26] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.043 ; 1.730 ; +; 3.214 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.043 ; 1.730 ; +; 3.214 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[22] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.043 ; 1.730 ; +; 3.214 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[25] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.044 ; 1.729 ; +; 3.214 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.044 ; 1.729 ; +; 3.214 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.034 ; 1.739 ; +; 3.214 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.035 ; 1.738 ; +; 3.214 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[21] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.044 ; 1.729 ; +; 3.214 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.044 ; 1.729 ; +; 3.214 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[14] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.043 ; 1.730 ; +; 3.214 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[30] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.043 ; 1.730 ; +; 3.214 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[18] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.043 ; 1.730 ; +; 3.214 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|Mn_rot_step2[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 5.000 ; -0.043 ; 1.730 ; +; 7.928 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.109 ; 1.900 ; +; 7.929 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.108 ; 1.900 ; +; 7.929 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.111 ; 1.897 ; +; 7.929 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.109 ; 1.899 ; +; 7.930 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.107 ; 1.900 ; +; 7.930 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[14] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.107 ; 1.900 ; +; 7.930 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.107 ; 1.900 ; +; 7.930 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.107 ; 1.900 ; +; 7.930 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.107 ; 1.900 ; +; 7.966 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.070 ; 1.904 ; +; 7.966 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.076 ; 1.898 ; +; 7.966 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.072 ; 1.902 ; +; 7.966 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.070 ; 1.904 ; +; 7.966 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.076 ; 1.898 ; +; 7.968 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.130 ; 1.840 ; +; 7.969 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.065 ; 1.906 ; +; 7.969 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.062 ; 1.909 ; +; 7.969 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[6] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.062 ; 1.909 ; +; 7.969 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.065 ; 1.906 ; +; 7.971 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.119 ; 1.848 ; +; 7.971 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.116 ; 1.851 ; +; 7.971 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[6] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.116 ; 1.851 ; +; 7.971 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.119 ; 1.848 ; +; 7.972 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.062 ; 1.905 ; +; 7.972 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[6] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.062 ; 1.905 ; +; 7.973 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.063 ; 1.903 ; +; 7.973 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.071 ; 1.896 ; +; 7.973 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.074 ; 1.893 ; +; 7.974 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.062 ; 1.903 ; +; 7.974 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.062 ; 1.903 ; +; 7.974 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.063 ; 1.902 ; +; 7.974 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.065 ; 1.900 ; +; 7.974 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.063 ; 1.902 ; +; 7.974 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.062 ; 1.903 ; +; 7.974 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.065 ; 1.900 ; +; 7.974 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_dqm[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.065 ; 1.900 ; +; 7.974 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_dqm[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.065 ; 1.900 ; +; 7.974 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_bank[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.062 ; 1.903 ; +; 7.975 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_addr[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.060 ; 1.904 ; +; 7.975 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.061 ; 1.903 ; +; 7.975 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.061 ; 1.903 ; +; 7.975 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.061 ; 1.903 ; +; 7.975 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.061 ; 1.903 ; +; 7.975 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[14] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.061 ; 1.903 ; +; 7.975 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_bank[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.063 ; 1.901 ; +; 7.983 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.058 ; 1.899 ; +; 7.983 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.058 ; 1.899 ; +; 7.985 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.112 ; 1.841 ; +; 7.985 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_data[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.112 ; 1.841 ; +; 8.062 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_7 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.062 ; 1.804 ; +; 8.063 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_2 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.062 ; 1.803 ; +; 8.063 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_8 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.061 ; 1.804 ; +; 8.063 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_12 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.064 ; 1.801 ; +; 8.064 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_9 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.060 ; 1.804 ; +; 8.064 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_10 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.060 ; 1.804 ; +; 8.064 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_11 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.060 ; 1.804 ; +; 8.064 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_13 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.060 ; 1.804 ; +; 8.064 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_14 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.060 ; 1.804 ; +; 8.067 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_3 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.084 ; 1.777 ; +; 8.070 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_15 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.073 ; 1.785 ; +; 8.070 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_4 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.073 ; 1.785 ; +; 8.070 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_5 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.070 ; 1.788 ; +; 8.070 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_6 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.070 ; 1.788 ; +; 8.084 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.066 ; 1.778 ; +; 8.084 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|oe~_Duplicate_1 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.066 ; 1.778 ; +; 8.085 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_cmd[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.063 ; 1.791 ; +; 8.086 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_cmd[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.066 ; 1.788 ; +; 8.086 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_cmd[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 10.000 ; -0.066 ; 1.788 ; +-------+-------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Fast 1200mV 0C Model Removal: 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[0]' ; -+-------+-------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+-------+-------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ -; 1.171 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_rx:the_system_uart_wifi_rx|altera_std_synchronizer:the_altera_std_synchronizer|dreg[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.212 ; 1.467 ; -; 1.171 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_rx:the_system_uart_wifi_rx|delayed_unxsync_rxdxx1 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.212 ; 1.467 ; -; 1.171 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_rx:the_system_uart_wifi_rx|baud_rate_counter[15] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.212 ; 1.467 ; -; 1.171 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_rx:the_system_uart_wifi_rx|baud_clk_en ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.212 ; 1.467 ; -; 1.171 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_rx:the_system_uart_wifi_rx|do_start_rx ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.212 ; 1.467 ; -; 1.337 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_slave_translator:cpu_jtag_debug_module_translator|av_readdata_pre[17] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.046 ; 1.467 ; -; 1.337 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|i_readdata_d1[17] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.046 ; 1.467 ; -; 1.337 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_slave_translator:cpu_jtag_debug_module_translator|waitrequest_reset_override ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 1.464 ; -; 1.337 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_slave_translator:cpu_jtag_debug_module_translator|av_readdata_pre[23] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.046 ; 1.467 ; -; 1.337 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|d_readdata_d1[23] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.046 ; 1.467 ; -; 1.337 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_slave_translator:cpu_jtag_debug_module_translator|av_readdata_pre[28] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.046 ; 1.467 ; -; 1.337 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.046 ; 1.467 ; -; 1.337 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.046 ; 1.467 ; -; 1.337 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_slave_translator:sys_clk_timer_s1_translator|read_latency_shift_reg[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.046 ; 1.467 ; -; 1.337 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|i_readdata_d1[28] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.046 ; 1.467 ; -; 1.337 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|i_readdatavalid_d1 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.046 ; 1.467 ; -; 1.337 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|d_readdata_d1[17] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.046 ; 1.467 ; -; 1.337 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|d_readdata_d1[16] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.046 ; 1.467 ; -; 1.337 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_slave_translator:sysid_control_slave_translator|wait_latency_counter[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.046 ; 1.467 ; -; 1.337 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_slave_translator:sysid_control_slave_translator|wait_latency_counter[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.046 ; 1.467 ; -; 1.337 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_slave_translator:cpu_jtag_debug_module_translator|av_readdata_pre[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.046 ; 1.467 ; -; 1.337 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_slave_translator:sys_clk_timer_s1_translator|av_readdata_pre[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.046 ; 1.467 ; -; 1.337 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_slave_translator:uart_wifi_s1_translator|av_readdata_pre[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.046 ; 1.467 ; -; 1.337 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|d_readdata_d1[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.046 ; 1.467 ; -; 1.337 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|ic_fill_ap_offset[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.042 ; 1.463 ; -; 1.337 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_slave_translator:cpu_jtag_debug_module_translator|wait_latency_counter[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 1.464 ; -; 1.337 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_slave_translator:cpu_jtag_debug_module_translator|wait_latency_counter[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 1.464 ; -; 1.337 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_slave_translator:cpu_jtag_debug_module_translator|end_begintransfer ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 1.464 ; -; 1.337 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|A_ienable_reg_irq14 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.046 ; 1.467 ; -; 1.337 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|A_ienable_reg_irq6 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.046 ; 1.467 ; -; 1.337 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|A_ienable_reg_irq4 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.046 ; 1.467 ; -; 1.337 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|i_readdata_d1[23] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.046 ; 1.467 ; -; 1.337 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|i_readdata_d1[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.046 ; 1.467 ; -; 1.337 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][102] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.046 ; 1.467 ; -; 1.337 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:sys_clk_timer_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[0][102] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.046 ; 1.467 ; -; 1.337 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux|altera_merlin_arbitrator:arb|top_priority_reg[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.042 ; 1.463 ; -; 1.337 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux|altera_merlin_arbitrator:arb|top_priority_reg[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.042 ; 1.463 ; -; 1.337 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux|saved_grant[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.042 ; 1.463 ; -; 1.337 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|ic_fill_ap_cnt[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.042 ; 1.463 ; -; 1.337 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|ic_fill_ap_cnt[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.042 ; 1.463 ; -; 1.337 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|ic_fill_ap_cnt[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.042 ; 1.463 ; -; 1.337 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|ic_fill_ap_cnt[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.042 ; 1.463 ; -; 1.337 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|i_read ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.042 ; 1.463 ; -; 1.337 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_traffic_limiter:limiter|pending_response_count[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.046 ; 1.467 ; -; 1.337 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_traffic_limiter:limiter|pending_response_count[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.046 ; 1.467 ; -; 1.337 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_traffic_limiter:limiter|pending_response_count[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.046 ; 1.467 ; -; 1.337 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_traffic_limiter:limiter|pending_response_count[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.046 ; 1.467 ; -; 1.337 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_traffic_limiter:limiter|has_pending_responses ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.042 ; 1.463 ; -; 1.337 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux|packet_in_progress ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 1.464 ; -; 1.337 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux|saved_grant[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.042 ; 1.463 ; -; 1.337 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_slave_translator:cpu_jtag_debug_module_translator|av_readdata_pre[16] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.046 ; 1.467 ; -; 1.337 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|i_readdata_d1[16] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.046 ; 1.467 ; -; 1.342 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|refresh_counter[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 1.482 ; -; 1.342 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|refresh_counter[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 1.482 ; -; 1.342 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|refresh_counter[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 1.482 ; -; 1.342 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|refresh_counter[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.056 ; 1.482 ; -; 1.343 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|entries[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.038 ; 1.465 ; -; 1.343 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 1.462 ; -; 1.343 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[4] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 1.462 ; -; 1.343 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 1.462 ; -; 1.343 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem_used[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.035 ; 1.462 ; -; 1.343 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_slave_translator:cpu_jtag_debug_module_translator|av_readdata_pre[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.039 ; 1.466 ; -; 1.343 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|rst2 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.038 ; 1.465 ; -; 1.343 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.042 ; 1.469 ; -; 1.343 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|a_fefifo_7cf:fifo_state|b_full ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.042 ; 1.469 ; -; 1.343 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|fifo_wr ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 1.470 ; -; 1.343 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|d_readdata_d1[31] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.046 ; 1.473 ; -; 1.343 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_slave_translator:cpu_jtag_debug_module_translator|av_readdata_pre[30] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.046 ; 1.473 ; -; 1.343 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|d_readdata_d1[30] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 1.470 ; -; 1.343 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_slave_translator:cpu_jtag_debug_module_translator|av_readdata_pre[29] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.046 ; 1.473 ; -; 1.343 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|d_readdata_d1[29] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.046 ; 1.473 ; -; 1.343 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[13] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.046 ; 1.473 ; -; 1.343 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|d_readdata_d1[28] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 1.470 ; -; 1.343 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_slave_translator:jtag_uart_0_avalon_jtag_slave_translator|av_readdata_pre[18] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.042 ; 1.469 ; -; 1.343 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_slave_translator:cpu_jtag_debug_module_translator|av_readdata_pre[26] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.046 ; 1.473 ; -; 1.343 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|d_readdata_d1[26] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.046 ; 1.473 ; -; 1.343 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_slave_translator:cpu_jtag_debug_module_translator|av_readdata_pre[27] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.046 ; 1.473 ; -; 1.343 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|d_readdata_d1[27] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.046 ; 1.473 ; -; 1.343 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_slave_translator:jtag_uart_0_avalon_jtag_slave_translator|av_readdata_pre[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.042 ; 1.469 ; -; 1.343 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_slave_translator:cpu_jtag_debug_module_translator|av_readdata_pre[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.046 ; 1.473 ; -; 1.343 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|d_readdata_d1[19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.046 ; 1.473 ; -; 1.343 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_slave_translator:cpu_jtag_debug_module_translator|av_readdata_pre[24] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.046 ; 1.473 ; -; 1.343 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_slave_translator:jtag_uart_0_avalon_jtag_slave_translator|av_readdata_pre[22] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.042 ; 1.469 ; -; 1.343 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_slave_translator:uart_wifi_s1_translator|av_readdata_pre[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.039 ; 1.466 ; -; 1.343 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.046 ; 1.473 ; -; 1.343 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_slave_translator:sys_clk_timer_s1_translator|av_readdata_pre[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.039 ; 1.466 ; -; 1.343 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_slave_translator:jtag_uart_0_avalon_jtag_slave_translator|av_readdata_pre[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.039 ; 1.466 ; -; 1.343 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 1.470 ; -; 1.343 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|d_readdata_d1[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.039 ; 1.466 ; -; 1.343 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|i_readdata_d1[30] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.046 ; 1.473 ; -; 1.343 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|i_readdata_d1[29] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.046 ; 1.473 ; -; 1.343 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|ic_fill_line[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 1.470 ; -; 1.343 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|ic_fill_line[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 1.470 ; -; 1.343 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|ic_fill_line[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 1.470 ; -; 1.343 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|i_readdata_d1[27] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.046 ; 1.473 ; -; 1.343 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_regs:the_system_uart_wifi_regs|baud_divisor[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.042 ; 1.469 ; -; 1.343 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_slave_translator:uart_wifi_s1_translator|av_readdata_pre[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 1.470 ; -; 1.343 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|jupdate1 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.038 ; 1.465 ; -; 1.343 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|jupdate2 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.038 ; 1.465 ; -; 1.343 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|t_pause~reg0 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.038 ; 1.465 ; -+-------+-------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Removal: 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[0]' ; ++-------+-------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+-------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ +; 1.443 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|i_addr[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.046 ; 1.573 ; +; 1.444 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux_001|altera_merlin_arbitrator:arb|top_priority_reg[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.038 ; 1.566 ; +; 1.444 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux_001|altera_merlin_arbitrator:arb|top_priority_reg[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.038 ; 1.566 ; +; 1.444 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux_001|saved_grant[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.038 ; 1.566 ; +; 1.444 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|system_sdram_input_efifo_module:the_system_sdram_input_efifo_module|rd_address ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 1.571 ; +; 1.444 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_state.000000010 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.045 ; 1.573 ; +; 1.444 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_next.000001000 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.044 ; 1.572 ; +; 1.444 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_state.000001000 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 1.571 ; +; 1.444 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_state.000100000 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.045 ; 1.573 ; +; 1.444 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_next.000000001 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.044 ; 1.572 ; +; 1.444 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_next.000010000 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.044 ; 1.572 ; +; 1.444 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_state.000010000 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 1.571 ; +; 1.444 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|f_pop ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.045 ; 1.573 ; +; 1.444 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|byteen_reg[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.040 ; 1.568 ; +; 1.444 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|byteen_reg[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.040 ; 1.568 ; +; 1.444 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|count[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.039 ; 1.567 ; +; 1.444 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|use_reg ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.039 ; 1.567 ; +; 1.444 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|i_next.000 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.044 ; 1.572 ; +; 1.444 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|i_state.000 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.044 ; 1.572 ; +; 1.444 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|i_next.010 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.045 ; 1.573 ; +; 1.444 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|i_count[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.045 ; 1.573 ; +; 1.444 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|i_count[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.045 ; 1.573 ; +; 1.444 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|i_next.111 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.044 ; 1.572 ; +; 1.444 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|i_state.111 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.045 ; 1.573 ; +; 1.444 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|i_count[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.045 ; 1.573 ; +; 1.444 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|i_state.010 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.045 ; 1.573 ; +; 1.444 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|i_cmd[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.044 ; 1.572 ; +; 1.444 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_cmd[0]~_Duplicate_1 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.044 ; 1.572 ; +; 1.444 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|i_cmd[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.044 ; 1.572 ; +; 1.444 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_cmd[2]~_Duplicate_1 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.044 ; 1.572 ; +; 1.444 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|i_cmd[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.045 ; 1.573 ; +; 1.444 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_cmd[1]~_Duplicate_1 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.044 ; 1.572 ; +; 1.444 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|rd_valid[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.044 ; 1.572 ; +; 1.444 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|endofpacket_reg ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.039 ; 1.567 ; +; 1.444 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][84] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.042 ; 1.570 ; +; 1.444 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][84] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.042 ; 1.570 ; +; 1.444 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux_001|packet_in_progress ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.039 ; 1.567 ; +; 1.444 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cmd_xbar_mux:cmd_xbar_mux_001|saved_grant[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.038 ; 1.566 ; +; 1.444 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][83] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.042 ; 1.570 ; +; 1.444 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][83] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.042 ; 1.570 ; +; 1.444 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[7][54] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.039 ; 1.567 ; +; 1.444 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][53] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.042 ; 1.570 ; +; 1.444 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][53] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.042 ; 1.570 ; +; 1.444 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][56] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.042 ; 1.570 ; +; 1.444 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][56] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.042 ; 1.570 ; +; 1.444 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.042 ; 1.570 ; +; 1.444 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.042 ; 1.570 ; +; 1.444 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[5][55] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.042 ; 1.570 ; +; 1.444 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[4][55] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.042 ; 1.570 ; +; 1.444 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|i_state.001 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.044 ; 1.572 ; +; 1.444 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|i_state.011 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.045 ; 1.573 ; +; 1.444 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|i_next.101 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.045 ; 1.573 ; +; 1.444 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|i_state.101 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.045 ; 1.573 ; +; 1.444 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|init_done ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.044 ; 1.572 ; +; 1.444 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|ack_refresh_request ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.044 ; 1.572 ; +; 1.444 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|refresh_request ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.044 ; 1.572 ; +; 1.444 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_state.100000000 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 1.571 ; +; 1.444 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|address_reg[11] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.040 ; 1.568 ; +; 1.444 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|address_reg[12] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.040 ; 1.568 ; +; 1.444 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|address_reg[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.040 ; 1.568 ; +; 1.444 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|address_reg[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.040 ; 1.568 ; +; 1.444 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|address_reg[23] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.040 ; 1.568 ; +; 1.444 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_state.000000100 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.045 ; 1.573 ; +; 1.444 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter|data_reg[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.040 ; 1.568 ; +; 1.444 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[1]~_Duplicate_1 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 1.571 ; +; 1.444 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[4]~_Duplicate_1 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 1.571 ; +; 1.444 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[5]~_Duplicate_1 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 1.571 ; +; 1.444 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[6]~_Duplicate_1 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 1.571 ; +; 1.444 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|m_data[11]~_Duplicate_1 ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.043 ; 1.571 ; +; 1.444 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|i_cmd[3] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.044 ; 1.572 ; +; 1.447 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.044 ; 1.575 ; +; 1.447 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|d_writedata[9] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.044 ; 1.575 ; +; 1.447 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|d_writedata[8] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.044 ; 1.575 ; +; 1.447 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[10] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.044 ; 1.575 ; +; 1.447 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[5] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.044 ; 1.575 ; +; 1.447 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_width_adapter:width_adapter_001|data_reg[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.044 ; 1.575 ; +; 1.447 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|d_readdata_d1[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.044 ; 1.575 ; +; 1.447 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|rd_valid[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.051 ; 1.582 ; +; 1.447 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|rd_valid[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.051 ; 1.582 ; +; 1.447 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_sdram:sdram|za_valid ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.050 ; 1.581 ; +; 1.447 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[2][84] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.049 ; 1.580 ; +; 1.447 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][84] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.049 ; 1.580 ; +; 1.447 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|d_writedata[30] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.044 ; 1.575 ; +; 1.447 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|d_writedata[29] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.044 ; 1.575 ; +; 1.447 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|d_writedata[27] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.044 ; 1.575 ; +; 1.447 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|d_writedata[26] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.044 ; 1.575 ; +; 1.447 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|d_writedata[24] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.044 ; 1.575 ; +; 1.447 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|d_writedata[23] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.044 ; 1.575 ; +; 1.447 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|d_writedata[17] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.044 ; 1.575 ; +; 1.447 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|system_cpu:cpu|i_readdata_d1[7] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.044 ; 1.575 ; +; 1.447 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[2][83] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.049 ; 1.580 ; +; 1.447 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][83] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.049 ; 1.580 ; +; 1.447 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[2][53] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.049 ; 1.580 ; +; 1.447 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][53] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.049 ; 1.580 ; +; 1.447 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[2][56] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.049 ; 1.580 ; +; 1.447 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][56] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.049 ; 1.580 ; +; 1.447 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_address_offset[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.050 ; 1.581 ; +; 1.447 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[2][19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.049 ; 1.580 ; +; 1.447 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_avalon_sc_fifo:sdram_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|mem[1][19] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.049 ; 1.580 ; +; 1.447 ; system:inst_cpu|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; system:inst_cpu|altera_merlin_slave_agent:sdram_s1_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_address_offset[1] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.050 ; 1.581 ; ++-------+-------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+--------------+------------+------------+ +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ @@ -4124,18 +4124,50 @@ Synchronizer Chain #6: Typical MTBF is n/a Years +-------+--------------+----------------+-----------------+----------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; +-------+--------------+----------------+-----------------+----------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; 4.749 ; 4.979 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_bht_module:system_cpu_bht|altsyncram:the_altsyncram|altsyncram_fhg1:auto_generated|ram_block1a0~porta_address_reg0 ; +; 4.749 ; 4.979 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_bht_module:system_cpu_bht|altsyncram:the_altsyncram|altsyncram_fhg1:auto_generated|ram_block1a0~porta_we_reg ; +; 4.749 ; 4.979 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_data_module:system_cpu_dc_data|altsyncram:the_altsyncram|altsyncram_2jf1:auto_generated|ram_block1a16~porta_address_reg0 ; +; 4.749 ; 4.979 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_data_module:system_cpu_dc_data|altsyncram:the_altsyncram|altsyncram_2jf1:auto_generated|ram_block1a16~porta_we_reg ; +; 4.749 ; 4.979 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_data_module:system_cpu_dc_data|altsyncram:the_altsyncram|altsyncram_2jf1:auto_generated|ram_block1a24~porta_address_reg0 ; +; 4.749 ; 4.979 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_data_module:system_cpu_dc_data|altsyncram:the_altsyncram|altsyncram_2jf1:auto_generated|ram_block1a24~porta_we_reg ; +; 4.749 ; 4.979 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_data_module:system_cpu_dc_data|altsyncram:the_altsyncram|altsyncram_2jf1:auto_generated|ram_block1a8~porta_address_reg0 ; +; 4.749 ; 4.979 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_data_module:system_cpu_dc_data|altsyncram:the_altsyncram|altsyncram_2jf1:auto_generated|ram_block1a8~porta_we_reg ; ; 4.749 ; 4.979 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a22~porta_address_reg0 ; ; 4.749 ; 4.979 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a22~porta_we_reg ; +; 4.749 ; 4.979 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a4~porta_address_reg0 ; +; 4.749 ; 4.979 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a4~porta_we_reg ; +; 4.749 ; 4.979 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a0~porta_address_reg0 ; +; 4.749 ; 4.979 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a0~porta_we_reg ; +; 4.749 ; 4.979 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~porta_address_reg0 ; +; 4.749 ; 4.979 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~porta_we_reg ; +; 4.749 ; 4.979 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_register_bank_a_module:system_cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_fvf1:auto_generated|ram_block1a0~porta_address_reg0 ; +; 4.749 ; 4.979 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_register_bank_a_module:system_cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_fvf1:auto_generated|ram_block1a0~porta_we_reg ; +; 4.749 ; 4.979 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_register_bank_b_module:system_cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_gvf1:auto_generated|ram_block1a0~porta_address_reg0 ; +; 4.749 ; 4.979 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_register_bank_b_module:system_cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_gvf1:auto_generated|ram_block1a0~porta_we_reg ; ; 4.749 ; 4.979 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_address_reg0 ; ; 4.749 ; 4.979 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_we_reg ; ; 4.749 ; 4.979 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_address_reg0 ; ; 4.749 ; 4.979 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_we_reg ; -; 4.750 ; 4.980 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a27~porta_address_reg0 ; -; 4.750 ; 4.980 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a27~porta_we_reg ; -; 4.750 ; 4.980 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a9~porta_address_reg0 ; -; 4.750 ; 4.980 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a9~porta_we_reg ; -; 4.750 ; 4.980 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~porta_address_reg0 ; -; 4.750 ; 4.980 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~porta_we_reg ; +; 4.750 ; 4.980 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|D_bht_data[0] ; +; 4.750 ; 4.980 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|D_bht_data[1] ; +; 4.750 ; 4.980 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_bht_module:system_cpu_bht|altsyncram:the_altsyncram|altsyncram_fhg1:auto_generated|ram_block1a0~portb_address_reg0 ; +; 4.750 ; 4.980 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_bht_module:system_cpu_bht|altsyncram:the_altsyncram|altsyncram_fhg1:auto_generated|ram_block1a0~portb_re_reg ; +; 4.750 ; 4.980 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_data_module:system_cpu_dc_data|altsyncram:the_altsyncram|altsyncram_2jf1:auto_generated|ram_block1a0~porta_address_reg0 ; +; 4.750 ; 4.980 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_data_module:system_cpu_dc_data|altsyncram:the_altsyncram|altsyncram_2jf1:auto_generated|ram_block1a0~porta_we_reg ; +; 4.750 ; 4.980 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_victim_module:system_cpu_dc_victim|altsyncram:the_altsyncram|altsyncram_r3d1:auto_generated|ram_block1a0~porta_address_reg0 ; +; 4.750 ; 4.980 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_victim_module:system_cpu_dc_victim|altsyncram:the_altsyncram|altsyncram_r3d1:auto_generated|ram_block1a0~porta_we_reg ; +; 4.750 ; 4.980 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a0~porta_address_reg0 ; +; 4.750 ; 4.980 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a0~porta_we_reg ; +; 4.750 ; 4.980 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a11~porta_address_reg0 ; +; 4.750 ; 4.980 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a11~porta_we_reg ; +; 4.750 ; 4.980 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a18~porta_address_reg0 ; +; 4.750 ; 4.980 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a18~porta_we_reg ; +; 4.750 ; 4.980 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a0~portb_address_reg0 ; +; 4.750 ; 4.980 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a0~portb_we_reg ; +; 4.750 ; 4.980 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_address_reg0 ; +; 4.750 ; 4.980 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_we_reg ; +; 4.750 ; 4.980 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_register_bank_a_module:system_cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_fvf1:auto_generated|ram_block1a0~portb_address_reg0 ; +; 4.750 ; 4.980 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_register_bank_b_module:system_cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_gvf1:auto_generated|ram_block1a0~portb_address_reg0 ; ; 4.750 ; 4.980 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|rdata[0] ; ; 4.750 ; 4.980 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|rdata[1] ; ; 4.750 ; 4.980 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|rdata[2] ; @@ -4144,86 +4176,54 @@ Synchronizer Chain #6: Typical MTBF is n/a Years ; 4.750 ; 4.980 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|rdata[5] ; ; 4.750 ; 4.980 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|rdata[6] ; ; 4.750 ; 4.980 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|rdata[7] ; -; 4.751 ; 4.981 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_bht_module:system_cpu_bht|altsyncram:the_altsyncram|altsyncram_fhg1:auto_generated|ram_block1a0~porta_address_reg0 ; -; 4.751 ; 4.981 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_bht_module:system_cpu_bht|altsyncram:the_altsyncram|altsyncram_fhg1:auto_generated|ram_block1a0~porta_we_reg ; -; 4.751 ; 4.981 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a0~porta_address_reg0 ; -; 4.751 ; 4.981 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a0~porta_we_reg ; +; 4.750 ; 4.980 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_address_reg0 ; +; 4.750 ; 4.980 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_we_reg ; +; 4.751 ; 4.981 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_bht_module:system_cpu_bht|altsyncram:the_altsyncram|altsyncram_fhg1:auto_generated|ram_block1a0~porta_datain_reg0 ; +; 4.751 ; 4.981 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_data_module:system_cpu_dc_data|altsyncram:the_altsyncram|altsyncram_2jf1:auto_generated|ram_block1a16~porta_bytena_reg0 ; +; 4.751 ; 4.981 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_data_module:system_cpu_dc_data|altsyncram:the_altsyncram|altsyncram_2jf1:auto_generated|ram_block1a16~porta_datain_reg0 ; +; 4.751 ; 4.981 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_data_module:system_cpu_dc_data|altsyncram:the_altsyncram|altsyncram_2jf1:auto_generated|ram_block1a24~porta_bytena_reg0 ; +; 4.751 ; 4.981 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_data_module:system_cpu_dc_data|altsyncram:the_altsyncram|altsyncram_2jf1:auto_generated|ram_block1a24~porta_datain_reg0 ; +; 4.751 ; 4.981 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_data_module:system_cpu_dc_data|altsyncram:the_altsyncram|altsyncram_2jf1:auto_generated|ram_block1a8~porta_bytena_reg0 ; +; 4.751 ; 4.981 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_data_module:system_cpu_dc_data|altsyncram:the_altsyncram|altsyncram_2jf1:auto_generated|ram_block1a8~porta_datain_reg0 ; +; 4.751 ; 4.981 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_victim_module:system_cpu_dc_victim|altsyncram:the_altsyncram|altsyncram_r3d1:auto_generated|ram_block1a0~portb_address_reg0 ; +; 4.751 ; 4.981 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_victim_module:system_cpu_dc_victim|altsyncram:the_altsyncram|altsyncram_r3d1:auto_generated|ram_block1a0~portb_re_reg ; ; 4.751 ; 4.981 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a22~porta_datain_reg0 ; -; 4.751 ; 4.981 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_address_reg0 ; -; 4.751 ; 4.981 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_we_reg ; -; 4.751 ; 4.981 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_register_bank_a_module:system_cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_fvf1:auto_generated|ram_block1a0~porta_address_reg0 ; -; 4.751 ; 4.981 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_register_bank_a_module:system_cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_fvf1:auto_generated|ram_block1a0~porta_we_reg ; +; 4.751 ; 4.981 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a4~porta_datain_reg0 ; +; 4.751 ; 4.981 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a6~porta_address_reg0 ; +; 4.751 ; 4.981 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a6~porta_we_reg ; +; 4.751 ; 4.981 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a0~porta_bytena_reg0 ; +; 4.751 ; 4.981 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a0~porta_datain_reg0 ; +; 4.751 ; 4.981 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~porta_bytena_reg0 ; +; 4.751 ; 4.981 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~porta_datain_reg0 ; +; 4.751 ; 4.981 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_register_bank_a_module:system_cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_fvf1:auto_generated|ram_block1a0~porta_datain_reg0 ; +; 4.751 ; 4.981 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_register_bank_b_module:system_cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_gvf1:auto_generated|ram_block1a0~porta_datain_reg0 ; ; 4.751 ; 4.981 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_datain_reg0 ; ; 4.751 ; 4.981 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~porta_datain_reg0 ; -; 4.752 ; 4.982 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|D_bht_data[0] ; -; 4.752 ; 4.982 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|D_bht_data[1] ; -; 4.752 ; 4.982 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_bht_module:system_cpu_bht|altsyncram:the_altsyncram|altsyncram_fhg1:auto_generated|ram_block1a0~portb_address_reg0 ; -; 4.752 ; 4.982 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_bht_module:system_cpu_bht|altsyncram:the_altsyncram|altsyncram_fhg1:auto_generated|ram_block1a0~portb_re_reg ; -; 4.752 ; 4.982 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_data_module:system_cpu_dc_data|altsyncram:the_altsyncram|altsyncram_2jf1:auto_generated|ram_block1a0~porta_address_reg0 ; -; 4.752 ; 4.982 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_data_module:system_cpu_dc_data|altsyncram:the_altsyncram|altsyncram_2jf1:auto_generated|ram_block1a0~porta_we_reg ; -; 4.752 ; 4.982 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_data_module:system_cpu_dc_data|altsyncram:the_altsyncram|altsyncram_2jf1:auto_generated|ram_block1a16~porta_address_reg0 ; -; 4.752 ; 4.982 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_data_module:system_cpu_dc_data|altsyncram:the_altsyncram|altsyncram_2jf1:auto_generated|ram_block1a16~porta_we_reg ; -; 4.752 ; 4.982 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_data_module:system_cpu_dc_data|altsyncram:the_altsyncram|altsyncram_2jf1:auto_generated|ram_block1a24~porta_address_reg0 ; -; 4.752 ; 4.982 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_data_module:system_cpu_dc_data|altsyncram:the_altsyncram|altsyncram_2jf1:auto_generated|ram_block1a24~porta_we_reg ; +; 4.752 ; 4.982 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_data_module:system_cpu_dc_data|altsyncram:the_altsyncram|altsyncram_2jf1:auto_generated|ram_block1a0~porta_bytena_reg0 ; +; 4.752 ; 4.982 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_data_module:system_cpu_dc_data|altsyncram:the_altsyncram|altsyncram_2jf1:auto_generated|ram_block1a0~porta_datain_reg0 ; +; 4.752 ; 4.982 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_data_module:system_cpu_dc_data|altsyncram:the_altsyncram|altsyncram_2jf1:auto_generated|ram_block1a16~portb_address_reg0 ; ; 4.752 ; 4.982 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_tag_module:system_cpu_dc_tag|altsyncram:the_altsyncram|altsyncram_d9g1:auto_generated|ram_block1a0~porta_address_reg0 ; ; 4.752 ; 4.982 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_tag_module:system_cpu_dc_tag|altsyncram:the_altsyncram|altsyncram_d9g1:auto_generated|ram_block1a0~porta_we_reg ; -; 4.752 ; 4.982 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_victim_module:system_cpu_dc_victim|altsyncram:the_altsyncram|altsyncram_r3d1:auto_generated|ram_block1a0~porta_address_reg0 ; -; 4.752 ; 4.982 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_victim_module:system_cpu_dc_victim|altsyncram:the_altsyncram|altsyncram_r3d1:auto_generated|ram_block1a0~porta_we_reg ; -; 4.752 ; 4.982 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a18~porta_address_reg0 ; -; 4.752 ; 4.982 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a18~porta_we_reg ; -; 4.752 ; 4.982 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a22~portb_address_reg0 ; -; 4.752 ; 4.982 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a22~portb_re_reg ; -; 4.752 ; 4.982 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a27~porta_datain_reg0 ; -; 4.752 ; 4.982 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a4~porta_address_reg0 ; -; 4.752 ; 4.982 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a4~porta_we_reg ; -; 4.752 ; 4.982 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a9~porta_datain_reg0 ; +; 4.752 ; 4.982 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_victim_module:system_cpu_dc_victim|altsyncram:the_altsyncram|altsyncram_r3d1:auto_generated|ram_block1a0~porta_datain_reg0 ; +; 4.752 ; 4.982 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a0~porta_datain_reg0 ; +; 4.752 ; 4.982 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a11~porta_datain_reg0 ; +; 4.752 ; 4.982 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a18~porta_datain_reg0 ; +; 4.752 ; 4.982 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a27~porta_address_reg0 ; +; 4.752 ; 4.982 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a27~porta_we_reg ; +; 4.752 ; 4.982 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a9~porta_address_reg0 ; +; 4.752 ; 4.982 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a9~porta_we_reg ; ; 4.752 ; 4.982 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_address_reg0 ; ; 4.752 ; 4.982 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~porta_we_reg ; -; 4.752 ; 4.982 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a0~porta_address_reg0 ; -; 4.752 ; 4.982 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a0~porta_we_reg ; -; 4.752 ; 4.982 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~porta_bytena_reg0 ; -; 4.752 ; 4.982 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~porta_datain_reg0 ; -; 4.752 ; 4.982 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_register_bank_a_module:system_cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_fvf1:auto_generated|ram_block1a0~portb_address_reg0 ; -; 4.752 ; 4.982 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_register_bank_b_module:system_cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_gvf1:auto_generated|ram_block1a0~porta_address_reg0 ; -; 4.752 ; 4.982 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_register_bank_b_module:system_cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_gvf1:auto_generated|ram_block1a0~porta_we_reg ; -; 4.752 ; 4.982 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_w:the_system_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~portb_address_reg0 ; +; 4.752 ; 4.982 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a0~portb_datain_reg0 ; +; 4.752 ; 4.982 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_datain_reg0 ; ; 4.752 ; 4.982 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_address_reg0 ; ; 4.752 ; 4.982 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_in_deserializer:RS232_In_Deserializer|altera_up_sync_fifo:RS232_In_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_we_reg ; -; 4.752 ; 4.982 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_address_reg0 ; -; 4.752 ; 4.982 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_we_reg ; -; 4.753 ; 4.983 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_bht_module:system_cpu_bht|altsyncram:the_altsyncram|altsyncram_fhg1:auto_generated|ram_block1a0~porta_datain_reg0 ; -; 4.753 ; 4.983 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_data_module:system_cpu_dc_data|altsyncram:the_altsyncram|altsyncram_2jf1:auto_generated|ram_block1a8~porta_address_reg0 ; -; 4.753 ; 4.983 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_data_module:system_cpu_dc_data|altsyncram:the_altsyncram|altsyncram_2jf1:auto_generated|ram_block1a8~porta_we_reg ; +; 4.752 ; 4.982 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_rs232_wifi:rs232_wifi|altera_up_rs232_out_serializer:RS232_Out_Serializer|altera_up_sync_fifo:RS232_Out_FIFO|scfifo:Sync_FIFO|scfifo_a341:auto_generated|a_dpfifo_tq31:dpfifo|altsyncram_je81:FIFOram|ram_block1a0~porta_datain_reg0 ; +; 4.753 ; 4.983 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_data_module:system_cpu_dc_data|altsyncram:the_altsyncram|altsyncram_2jf1:auto_generated|ram_block1a0~portb_address_reg0 ; +; 4.753 ; 4.983 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_data_module:system_cpu_dc_data|altsyncram:the_altsyncram|altsyncram_2jf1:auto_generated|ram_block1a24~portb_address_reg0 ; +; 4.753 ; 4.983 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_data_module:system_cpu_dc_data|altsyncram:the_altsyncram|altsyncram_2jf1:auto_generated|ram_block1a8~portb_address_reg0 ; ; 4.753 ; 4.983 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_tag_module:system_cpu_dc_tag|altsyncram:the_altsyncram|altsyncram_d9g1:auto_generated|ram_block1a0~portb_address_reg0 ; -; 4.753 ; 4.983 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_victim_module:system_cpu_dc_victim|altsyncram:the_altsyncram|altsyncram_r3d1:auto_generated|ram_block1a0~portb_address_reg0 ; -; 4.753 ; 4.983 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_victim_module:system_cpu_dc_victim|altsyncram:the_altsyncram|altsyncram_r3d1:auto_generated|ram_block1a0~portb_re_reg ; -; 4.753 ; 4.983 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a0~porta_datain_reg0 ; -; 4.753 ; 4.983 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a11~porta_address_reg0 ; -; 4.753 ; 4.983 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a11~porta_we_reg ; -; 4.753 ; 4.983 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a6~porta_address_reg0 ; -; 4.753 ; 4.983 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a6~porta_we_reg ; -; 4.753 ; 4.983 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a9~portb_address_reg0 ; -; 4.753 ; 4.983 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a9~portb_re_reg ; -; 4.753 ; 4.983 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~portb_address_reg0 ; -; 4.753 ; 4.983 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_tag_module:system_cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_qtg1:auto_generated|ram_block1a0~portb_re_reg ; -; 4.753 ; 4.983 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a0~portb_address_reg0 ; -; 4.753 ; 4.983 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a0~portb_we_reg ; -; 4.753 ; 4.983 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_nios2_ocimem:the_system_cpu_nios2_ocimem|system_cpu_ociram_lpm_dram_bdp_component_module:system_cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_jt72:auto_generated|ram_block1a8~portb_datain_reg0 ; -; 4.753 ; 4.983 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_register_bank_a_module:system_cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_fvf1:auto_generated|ram_block1a0~porta_datain_reg0 ; -; 4.753 ; 4.983 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_register_bank_b_module:system_cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_gvf1:auto_generated|ram_block1a0~portb_address_reg0 ; -; 4.753 ; 4.983 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|system_jtag_uart_0_scfifo_r:the_system_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_jr21:auto_generated|a_dpfifo_q131:dpfifo|dpram_nl21:FIFOram|altsyncram_r1m1:altsyncram1|ram_block2a0~portb_address_reg0 ; -; 4.754 ; 4.984 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_data_module:system_cpu_dc_data|altsyncram:the_altsyncram|altsyncram_2jf1:auto_generated|ram_block1a0~porta_bytena_reg0 ; -; 4.754 ; 4.984 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_data_module:system_cpu_dc_data|altsyncram:the_altsyncram|altsyncram_2jf1:auto_generated|ram_block1a0~porta_datain_reg0 ; -; 4.754 ; 4.984 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_data_module:system_cpu_dc_data|altsyncram:the_altsyncram|altsyncram_2jf1:auto_generated|ram_block1a16~porta_bytena_reg0 ; -; 4.754 ; 4.984 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_data_module:system_cpu_dc_data|altsyncram:the_altsyncram|altsyncram_2jf1:auto_generated|ram_block1a16~porta_datain_reg0 ; -; 4.754 ; 4.984 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_data_module:system_cpu_dc_data|altsyncram:the_altsyncram|altsyncram_2jf1:auto_generated|ram_block1a24~porta_bytena_reg0 ; -; 4.754 ; 4.984 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_data_module:system_cpu_dc_data|altsyncram:the_altsyncram|altsyncram_2jf1:auto_generated|ram_block1a24~porta_datain_reg0 ; -; 4.754 ; 4.984 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_tag_module:system_cpu_dc_tag|altsyncram:the_altsyncram|altsyncram_d9g1:auto_generated|ram_block1a0~porta_datain_reg0 ; -; 4.754 ; 4.984 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_dc_victim_module:system_cpu_dc_victim|altsyncram:the_altsyncram|altsyncram_r3d1:auto_generated|ram_block1a0~porta_datain_reg0 ; -; 4.754 ; 4.984 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a0~portb_address_reg0 ; -; 4.754 ; 4.984 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a0~portb_re_reg ; -; 4.754 ; 4.984 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a18~porta_datain_reg0 ; -; 4.754 ; 4.984 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a27~portb_address_reg0 ; +; 4.753 ; 4.983 ; 0.230 ; Low Pulse Width ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_ic_data_module:system_cpu_ic_data|altsyncram:the_altsyncram|altsyncram_sjd1:auto_generated|ram_block1a0~portb_address_reg0 ; +-------+--------------+----------------+-----------------+----------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ @@ -4250,112 +4250,112 @@ Synchronizer Chain #6: Typical MTBF is n/a Years +--------+--------------+----------------+------------------+----------+------------+--------------------------------------------------------------------+ -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Fast 1200mV 0C Model Minimum Pulse Width: 'altera_reserved_tck' ; -+--------+--------------+----------------+------------------+---------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; -+--------+--------------+----------------+------------------+---------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; 49.482 ; 49.698 ; 0.216 ; High Pulse Width ; altera_reserved_tck ; Fall ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; -; 49.482 ; 49.698 ; 0.216 ; High Pulse Width ; altera_reserved_tck ; Fall ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|tdo~reg0 ; -; 49.484 ; 49.700 ; 0.216 ; High Pulse Width ; altera_reserved_tck ; Fall ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|jupdate ; -; 49.525 ; 49.709 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_mode_reg[1] ; -; 49.525 ; 49.709 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[0] ; -; 49.525 ; 49.709 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[1] ; -; 49.525 ; 49.709 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[2] ; -; 49.525 ; 49.709 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_shift_reg[3] ; -; 49.525 ; 49.709 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[0] ; -; 49.525 ; 49.709 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[1] ; -; 49.525 ; 49.709 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[2] ; -; 49.525 ; 49.709 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|identity_contrib_update_reg[3] ; -; 49.525 ; 49.709 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[5] ; -; 49.525 ; 49.709 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[0] ; -; 49.525 ; 49.709 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[1] ; -; 49.525 ; 49.709 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[2] ; -; 49.525 ; 49.709 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[3] ; -; 49.525 ; 49.709 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|mixer_addr_reg[4] ; -; 49.525 ; 49.709 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; -; 49.525 ; 49.709 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[2]~reg0 ; -; 49.525 ; 49.709 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[8] ; -; 49.525 ; 49.709 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[0] ; -; 49.525 ; 49.709 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[1] ; -; 49.525 ; 49.709 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[2] ; -; 49.525 ; 49.709 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo_bypass_reg ; -; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[0] ; -; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[1] ; -; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[2] ; -; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|design_hash_reg[3] ; -; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[0] ; -; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[1] ; -; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[2] ; -; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|hub_minor_ver_reg[3] ; -; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irsr_reg[6] ; -; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[0] ; -; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1] ; -; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2] ; -; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[3] ; -; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[4] ; -; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[5] ; -; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[6] ; -; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[7] ; -; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[8] ; -; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[9] ; -; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[0] ; -; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[1] ; -; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[2] ; -; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|WORD_SR[3] ; -; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[0] ; -; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[1] ; -; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[2] ; -; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[3] ; -; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_rom_sr:hub_info_reg|word_counter[4] ; -; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; -; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[10] ; -; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[11] ; -; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[12] ; -; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[13] ; -; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[14] ; -; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[15] ; -; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[1] ; -; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[2] ; -; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; -; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[4] ; -; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[5] ; -; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[6] ; -; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[7] ; -; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[9] ; -; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_dr_scan_reg ; -; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; -; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|din_s1 ; -; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer1|dreg[0] ; -; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 ; -; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|altera_std_synchronizer:the_altera_std_synchronizer|dreg[0] ; -; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|ir_out[0] ; -; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|ir_out[1] ; -; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[0] ; -; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[10] ; -; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[11] ; -; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[12] ; -; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[13] ; -; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[14] ; -; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[15] ; -; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[1] ; -; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[27] ; -; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[28] ; -; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[29] ; -; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[2] ; -; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[30] ; -; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[32] ; -; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[33] ; -; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[34] ; -; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[35] ; -; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[36] ; -; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[37] ; -; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[3] ; -; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[4] ; -; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[5] ; -; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[6] ; -; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[8] ; -+--------+--------------+----------------+------------------+---------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fast 1200mV 0C Model Minimum Pulse Width: 'altera_reserved_tck' ; ++--------+--------------+----------------+------------------+---------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; ++--------+--------------+----------------+------------------+---------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; 49.484 ; 49.700 ; 0.216 ; High Pulse Width ; altera_reserved_tck ; Fall ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo ; +; 49.484 ; 49.700 ; 0.216 ; High Pulse Width ; altera_reserved_tck ; Fall ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|jupdate ; +; 49.485 ; 49.701 ; 0.216 ; High Pulse Width ; altera_reserved_tck ; Fall ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|tdo~reg0 ; +; 49.526 ; 49.710 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|tck_t_dav ; +; 49.527 ; 49.711 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[10] ; +; 49.527 ; 49.711 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[11] ; +; 49.527 ; 49.711 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[12] ; +; 49.527 ; 49.711 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[13] ; +; 49.527 ; 49.711 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[14] ; +; 49.527 ; 49.711 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[1] ; +; 49.527 ; 49.711 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[2] ; +; 49.527 ; 49.711 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[3] ; +; 49.527 ; 49.711 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[4] ; +; 49.527 ; 49.711 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[5] ; +; 49.527 ; 49.711 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[6] ; +; 49.527 ; 49.711 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[8] ; +; 49.527 ; 49.711 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[9] ; +; 49.527 ; 49.711 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|count[1] ; +; 49.527 ; 49.711 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|count[2] ; +; 49.527 ; 49.711 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|count[3] ; +; 49.527 ; 49.711 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|count[4] ; +; 49.527 ; 49.711 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|count[5] ; +; 49.527 ; 49.711 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|count[6] ; +; 49.527 ; 49.711 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|count[7] ; +; 49.527 ; 49.711 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|count[8] ; +; 49.527 ; 49.711 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|count[9] ; +; 49.527 ; 49.711 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|read ; +; 49.527 ; 49.711 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|read_req ; +; 49.527 ; 49.711 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|state ; +; 49.527 ; 49.711 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|td_shift[0] ; +; 49.527 ; 49.711 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|td_shift[10] ; +; 49.527 ; 49.711 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|td_shift[8] ; +; 49.527 ; 49.711 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|td_shift[9] ; +; 49.527 ; 49.711 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|user_saw_rvalid ; +; 49.527 ; 49.711 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|wdata[0] ; +; 49.527 ; 49.711 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|wdata[1] ; +; 49.527 ; 49.711 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|wdata[2] ; +; 49.527 ; 49.711 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|wdata[3] ; +; 49.527 ; 49.711 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|wdata[4] ; +; 49.527 ; 49.711 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|wdata[5] ; +; 49.527 ; 49.711 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|wdata[6] ; +; 49.527 ; 49.711 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|wdata[7] ; +; 49.527 ; 49.711 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|write ; +; 49.527 ; 49.711 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|write_stalled ; +; 49.527 ; 49.711 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_jtag_uart_0:jtag_uart_0|alt_jtag_atlantic:system_jtag_uart_0_alt_jtag_atlantic|write_valid ; +; 49.528 ; 49.712 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|clr_reg ; +; 49.528 ; 49.712 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][0] ; +; 49.528 ; 49.712 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][2] ; +; 49.528 ; 49.712 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[1][4] ; +; 49.528 ; 49.712 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][0] ; +; 49.528 ; 49.712 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][1] ; +; 49.528 ; 49.712 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][2] ; +; 49.528 ; 49.712 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][3] ; +; 49.528 ; 49.712 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|irf_reg[2][4] ; +; 49.528 ; 49.712 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[0] ; +; 49.528 ; 49.712 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[1] ; +; 49.528 ; 49.712 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[2] ; +; 49.528 ; 49.712 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[3] ; +; 49.528 ; 49.712 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[4] ; +; 49.528 ; 49.712 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[5] ; +; 49.528 ; 49.712 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[6] ; +; 49.528 ; 49.712 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[7] ; +; 49.528 ; 49.712 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[8] ; +; 49.528 ; 49.712 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|jtag_ir_reg[9] ; +; 49.528 ; 49.712 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][0] ; +; 49.528 ; 49.712 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][2] ; +; 49.528 ; 49.712 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[1][4] ; +; 49.528 ; 49.712 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][0] ; +; 49.528 ; 49.712 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][1] ; +; 49.528 ; 49.712 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][2] ; +; 49.528 ; 49.712 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][3] ; +; 49.528 ; 49.712 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|shadow_irf_reg[2][4] ; +; 49.528 ; 49.712 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[0] ; +; 49.528 ; 49.712 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[10] ; +; 49.528 ; 49.712 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[11] ; +; 49.528 ; 49.712 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[12] ; +; 49.528 ; 49.712 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[13] ; +; 49.528 ; 49.712 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[14] ; +; 49.528 ; 49.712 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[15] ; +; 49.528 ; 49.712 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[1] ; +; 49.528 ; 49.712 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[2] ; +; 49.528 ; 49.712 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[3] ; +; 49.528 ; 49.712 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|state[9] ; +; 49.528 ; 49.712 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[0] ; +; 49.528 ; 49.712 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[1] ; +; 49.528 ; 49.712 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|sld_shadow_jsm:shadow_jsm|tms_cnt[2] ; +; 49.528 ; 49.712 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|tdo_bypass_reg ; +; 49.528 ; 49.712 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_dr_scan_reg ; +; 49.528 ; 49.712 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; +; 49.528 ; 49.712 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[15] ; +; 49.528 ; 49.712 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[16] ; +; 49.528 ; 49.712 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[17] ; +; 49.528 ; 49.712 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[18] ; +; 49.528 ; 49.712 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[19] ; +; 49.528 ; 49.712 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[20] ; +; 49.528 ; 49.712 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[21] ; +; 49.528 ; 49.712 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[22] ; +; 49.528 ; 49.712 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[23] ; +; 49.528 ; 49.712 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[24] ; +; 49.528 ; 49.712 ; 0.184 ; Low Pulse Width ; altera_reserved_tck ; Rise ; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_tck:the_system_cpu_jtag_debug_module_tck|sr[25] ; ++--------+--------------+----------------+------------------+---------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ @@ -4471,8 +4471,8 @@ Synchronizer Chain #6: Typical MTBF is n/a Years +---------------------+---------------------+-------+-------+------------+----------------------------------------------------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +---------------------+---------------------+-------+-------+------------+----------------------------------------------------------+ -; altera_reserved_tdi ; altera_reserved_tck ; 0.788 ; 1.031 ; Rise ; altera_reserved_tck ; -; altera_reserved_tms ; altera_reserved_tck ; 2.580 ; 3.008 ; Rise ; altera_reserved_tck ; +; altera_reserved_tdi ; altera_reserved_tck ; 0.965 ; 1.157 ; Rise ; altera_reserved_tck ; +; altera_reserved_tms ; altera_reserved_tck ; 2.611 ; 3.093 ; Rise ; altera_reserved_tck ; ; DRAM_DQ[*] ; CLOCK_50 ; 0.584 ; 0.963 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; DRAM_DQ[0] ; CLOCK_50 ; 0.576 ; 0.955 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; DRAM_DQ[1] ; CLOCK_50 ; 0.576 ; 0.955 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; @@ -4490,15 +4490,15 @@ Synchronizer Chain #6: Typical MTBF is n/a Years ; DRAM_DQ[13] ; CLOCK_50 ; 0.564 ; 0.941 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; DRAM_DQ[14] ; CLOCK_50 ; 0.564 ; 0.941 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; DRAM_DQ[15] ; CLOCK_50 ; 0.573 ; 0.952 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; GPIO_0[*] ; CLOCK_50 ; 2.854 ; 3.574 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; GPIO_0[31] ; CLOCK_50 ; 2.854 ; 3.574 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; KEY[*] ; CLOCK_50 ; 1.462 ; 1.778 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; KEY[1] ; CLOCK_50 ; 1.462 ; 1.778 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; SW[*] ; CLOCK_50 ; 1.457 ; 1.727 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; SW[0] ; CLOCK_50 ; 1.417 ; 1.703 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; SW[1] ; CLOCK_50 ; 1.150 ; 1.451 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; SW[2] ; CLOCK_50 ; 1.193 ; 1.483 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; SW[3] ; CLOCK_50 ; 1.457 ; 1.727 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_0[*] ; CLOCK_50 ; 2.797 ; 3.492 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_0[31] ; CLOCK_50 ; 2.797 ; 3.492 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; KEY[*] ; CLOCK_50 ; 1.330 ; 1.652 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; KEY[1] ; CLOCK_50 ; 1.330 ; 1.652 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; SW[*] ; CLOCK_50 ; 1.572 ; 1.798 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; SW[0] ; CLOCK_50 ; 1.146 ; 1.460 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; SW[1] ; CLOCK_50 ; 1.572 ; 1.798 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; SW[2] ; CLOCK_50 ; 1.368 ; 1.643 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; SW[3] ; CLOCK_50 ; 1.233 ; 1.520 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +---------------------+---------------------+-------+-------+------------+----------------------------------------------------------+ @@ -4507,8 +4507,8 @@ Synchronizer Chain #6: Typical MTBF is n/a Years +---------------------+---------------------+--------+--------+------------+----------------------------------------------------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +---------------------+---------------------+--------+--------+------------+----------------------------------------------------------+ -; altera_reserved_tdi ; altera_reserved_tck ; 1.007 ; 0.710 ; Rise ; altera_reserved_tck ; -; altera_reserved_tms ; altera_reserved_tck ; 0.047 ; -0.239 ; Rise ; altera_reserved_tck ; +; altera_reserved_tdi ; altera_reserved_tck ; 1.007 ; 0.708 ; Rise ; altera_reserved_tck ; +; altera_reserved_tms ; altera_reserved_tck ; 0.221 ; -0.107 ; Rise ; altera_reserved_tck ; ; DRAM_DQ[*] ; CLOCK_50 ; -0.259 ; -0.636 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; DRAM_DQ[0] ; CLOCK_50 ; -0.270 ; -0.649 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; DRAM_DQ[1] ; CLOCK_50 ; -0.270 ; -0.649 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; @@ -4526,15 +4526,15 @@ Synchronizer Chain #6: Typical MTBF is n/a Years ; DRAM_DQ[13] ; CLOCK_50 ; -0.259 ; -0.636 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; DRAM_DQ[14] ; CLOCK_50 ; -0.259 ; -0.636 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; DRAM_DQ[15] ; CLOCK_50 ; -0.266 ; -0.645 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; GPIO_0[*] ; CLOCK_50 ; -2.213 ; -2.883 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; GPIO_0[31] ; CLOCK_50 ; -2.213 ; -2.883 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; KEY[*] ; CLOCK_50 ; -0.952 ; -1.241 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; KEY[1] ; CLOCK_50 ; -0.952 ; -1.241 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; SW[*] ; CLOCK_50 ; -0.793 ; -1.090 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; SW[0] ; CLOCK_50 ; -1.048 ; -1.331 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; SW[1] ; CLOCK_50 ; -0.793 ; -1.090 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; SW[2] ; CLOCK_50 ; -0.834 ; -1.121 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; SW[3] ; CLOCK_50 ; -1.087 ; -1.354 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_0[*] ; CLOCK_50 ; -2.270 ; -2.954 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_0[31] ; CLOCK_50 ; -2.270 ; -2.954 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; KEY[*] ; CLOCK_50 ; -0.813 ; -1.117 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; KEY[1] ; CLOCK_50 ; -0.813 ; -1.117 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; SW[*] ; CLOCK_50 ; -0.788 ; -1.098 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; SW[0] ; CLOCK_50 ; -0.788 ; -1.098 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; SW[1] ; CLOCK_50 ; -1.193 ; -1.410 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; SW[2] ; CLOCK_50 ; -0.974 ; -1.240 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; SW[3] ; CLOCK_50 ; -0.872 ; -1.156 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +---------------------+---------------------+--------+--------+------------+----------------------------------------------------------+ @@ -4543,7 +4543,7 @@ Synchronizer Chain #6: Typical MTBF is n/a Years +---------------------+---------------------+-------+-------+------------+----------------------------------------------------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +---------------------+---------------------+-------+-------+------------+----------------------------------------------------------+ -; altera_reserved_tdo ; altera_reserved_tck ; 6.202 ; 6.678 ; Fall ; altera_reserved_tck ; +; altera_reserved_tdo ; altera_reserved_tck ; 6.271 ; 6.729 ; Fall ; altera_reserved_tck ; ; DRAM_ADDR[*] ; CLOCK_50 ; 1.812 ; 1.831 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; DRAM_ADDR[0] ; CLOCK_50 ; 1.812 ; 1.831 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; DRAM_ADDR[1] ; CLOCK_50 ; 1.768 ; 1.771 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; @@ -4584,20 +4584,20 @@ Synchronizer Chain #6: Typical MTBF is n/a Years ; DRAM_DQM[0] ; CLOCK_50 ; 1.765 ; 1.768 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; DRAM_DQM[1] ; CLOCK_50 ; 1.765 ; 1.768 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; DRAM_RAS_N ; CLOCK_50 ; 1.817 ; 1.836 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; DRAM_WE_N ; CLOCK_50 ; 1.822 ; 1.841 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; GPIO_0[*] ; CLOCK_50 ; 3.517 ; 3.753 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; GPIO_0[33] ; CLOCK_50 ; 3.517 ; 3.753 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; GPIO_1[*] ; CLOCK_50 ; 2.858 ; 2.798 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; GPIO_1[0] ; CLOCK_50 ; 2.664 ; 2.798 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; GPIO_1[33] ; CLOCK_50 ; 2.858 ; 2.718 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; LED[*] ; CLOCK_50 ; 3.729 ; 3.951 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; LED[0] ; CLOCK_50 ; 2.802 ; 2.944 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; LED[1] ; CLOCK_50 ; 2.939 ; 3.099 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; LED[2] ; CLOCK_50 ; 2.708 ; 2.840 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; LED[3] ; CLOCK_50 ; 2.777 ; 2.912 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; LED[4] ; CLOCK_50 ; 3.531 ; 3.830 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; LED[5] ; CLOCK_50 ; 3.729 ; 3.951 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; LED[6] ; CLOCK_50 ; 3.537 ; 3.768 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_WE_N ; CLOCK_50 ; 1.816 ; 1.835 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_0[*] ; CLOCK_50 ; 3.060 ; 3.228 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_0[33] ; CLOCK_50 ; 3.060 ; 3.228 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_1[*] ; CLOCK_50 ; 3.199 ; 3.436 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_1[0] ; CLOCK_50 ; 3.199 ; 3.436 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_1[33] ; CLOCK_50 ; 3.113 ; 2.945 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[*] ; CLOCK_50 ; 3.690 ; 3.882 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[0] ; CLOCK_50 ; 3.102 ; 3.298 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[1] ; CLOCK_50 ; 3.456 ; 3.693 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[2] ; CLOCK_50 ; 3.254 ; 3.446 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[3] ; CLOCK_50 ; 2.883 ; 3.038 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[4] ; CLOCK_50 ; 2.740 ; 2.893 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[5] ; CLOCK_50 ; 3.690 ; 3.882 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[6] ; CLOCK_50 ; 2.557 ; 2.679 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; DRAM_CLK ; CLOCK_50 ; 0.085 ; ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[1] ; ; DRAM_CLK ; CLOCK_50 ; ; 0.115 ; Fall ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[1] ; ; LED[*] ; CLOCK_50 ; 2.917 ; 3.016 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; @@ -4610,7 +4610,7 @@ Synchronizer Chain #6: Typical MTBF is n/a Years +---------------------+---------------------+--------+--------+------------+----------------------------------------------------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +---------------------+---------------------+--------+--------+------------+----------------------------------------------------------+ -; altera_reserved_tdo ; altera_reserved_tck ; 5.028 ; 5.503 ; Fall ; altera_reserved_tck ; +; altera_reserved_tdo ; altera_reserved_tck ; 5.095 ; 5.554 ; Fall ; altera_reserved_tck ; ; DRAM_ADDR[*] ; CLOCK_50 ; 1.513 ; 1.513 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; DRAM_ADDR[0] ; CLOCK_50 ; 1.571 ; 1.591 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; DRAM_ADDR[1] ; CLOCK_50 ; 1.526 ; 1.529 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; @@ -4651,20 +4651,20 @@ Synchronizer Chain #6: Typical MTBF is n/a Years ; DRAM_DQM[0] ; CLOCK_50 ; 1.523 ; 1.526 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; DRAM_DQM[1] ; CLOCK_50 ; 1.523 ; 1.526 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; DRAM_RAS_N ; CLOCK_50 ; 1.575 ; 1.595 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; DRAM_WE_N ; CLOCK_50 ; 1.580 ; 1.600 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; GPIO_0[*] ; CLOCK_50 ; 3.161 ; 3.387 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; GPIO_0[33] ; CLOCK_50 ; 3.161 ; 3.387 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; GPIO_1[*] ; CLOCK_50 ; 2.342 ; 2.398 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; GPIO_1[0] ; CLOCK_50 ; 2.342 ; 2.472 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; GPIO_1[33] ; CLOCK_50 ; 2.533 ; 2.398 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; LED[*] ; CLOCK_50 ; 2.385 ; 2.512 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; LED[0] ; CLOCK_50 ; 2.475 ; 2.612 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; LED[1] ; CLOCK_50 ; 2.606 ; 2.760 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; LED[2] ; CLOCK_50 ; 2.385 ; 2.512 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; LED[3] ; CLOCK_50 ; 2.451 ; 2.581 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; LED[4] ; CLOCK_50 ; 3.178 ; 3.467 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; LED[5] ; CLOCK_50 ; 3.404 ; 3.620 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; LED[6] ; CLOCK_50 ; 3.182 ; 3.404 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_WE_N ; CLOCK_50 ; 1.574 ; 1.594 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_0[*] ; CLOCK_50 ; 2.722 ; 2.884 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_0[33] ; CLOCK_50 ; 2.722 ; 2.884 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_1[*] ; CLOCK_50 ; 2.778 ; 2.616 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_1[0] ; CLOCK_50 ; 2.856 ; 3.084 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_1[33] ; CLOCK_50 ; 2.778 ; 2.616 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[*] ; CLOCK_50 ; 2.241 ; 2.358 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[0] ; CLOCK_50 ; 2.763 ; 2.951 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[1] ; CLOCK_50 ; 3.103 ; 3.330 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[2] ; CLOCK_50 ; 2.909 ; 3.093 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[3] ; CLOCK_50 ; 2.553 ; 2.702 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[4] ; CLOCK_50 ; 2.418 ; 2.567 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[5] ; CLOCK_50 ; 3.366 ; 3.553 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[6] ; CLOCK_50 ; 2.241 ; 2.358 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; DRAM_CLK ; CLOCK_50 ; -0.188 ; ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[1] ; ; DRAM_CLK ; CLOCK_50 ; ; -0.158 ; Fall ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[1] ; ; LED[*] ; CLOCK_50 ; 2.623 ; 2.720 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; @@ -4780,7 +4780,7 @@ Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. Number of Synchronizer Chains Found: 6 Shortest Synchronizer Chain: 2 Registers Fraction of Chains for which MTBFs Could Not be Calculated: 0.333 -Worst Case Available Settling Time: 18.234 ns +Worst Case Available Settling Time: 18.472 ns Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8 @@ -4822,7 +4822,7 @@ Synchronizer Chain #1: Typical MTBF is Greater than 1 Billion Years ; Method of Synchronizer Identification ; User Specified ; ; ; ; ; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; ; Number of Synchronization Registers in Chain ; 2 ; ; ; ; -; Available Settling Time (ns) ; 18.234 ; ; ; ; +; Available Settling Time (ns) ; 18.472 ; ; ; ; ; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 12.5 ; ; ; ; ; Source Clock ; ; ; ; ; ; Unknown ; ; ; ; ; @@ -4830,8 +4830,8 @@ Synchronizer Chain #1: Typical MTBF is Greater than 1 Billion Years ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; 10.000 ; 100.0 MHz ; ; ; Asynchronous Source ; ; ; ; ; ; Synchronization Registers ; ; ; ; ; -; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_rx:the_system_uart_wifi_rx|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 ; ; ; ; 9.503 ; -; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_rx:the_system_uart_wifi_rx|altera_std_synchronizer:the_altera_std_synchronizer|dreg[0] ; ; ; ; 8.731 ; +; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_rx:the_system_uart_wifi_rx|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 ; ; ; ; 9.510 ; +; system:inst_cpu|system_uart_wifi:uart_wifi|system_uart_wifi_rx:the_system_uart_wifi_rx|altera_std_synchronizer:the_altera_std_synchronizer|dreg[0] ; ; ; ; 8.962 ; +-----------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ @@ -4857,7 +4857,7 @@ Synchronizer Chain #2: Typical MTBF is Greater than 1 Billion Years ; Method of Synchronizer Identification ; User Specified ; ; ; ; ; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; ; Number of Synchronization Registers in Chain ; 2 ; ; ; ; -; Available Settling Time (ns) ; 18.820 ; ; ; ; +; Available Settling Time (ns) ; 18.831 ; ; ; ; ; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 12.5 ; ; ; ; ; Source Clock ; ; ; ; ; ; Unknown ; ; ; ; ; @@ -4866,8 +4866,8 @@ Synchronizer Chain #2: Typical MTBF is Greater than 1 Billion Years ; Asynchronous Source ; ; ; ; ; ; GPIO_1[31] ; ; ; ; ; ; Synchronization Registers ; ; ; ; ; -; system:inst_cpu|system_uart_mc:uart_mc|system_uart_mc_rx:the_system_uart_mc_rx|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 ; ; ; ; 9.367 ; -; system:inst_cpu|system_uart_mc:uart_mc|system_uart_mc_rx:the_system_uart_mc_rx|altera_std_synchronizer:the_altera_std_synchronizer|dreg[0] ; ; ; ; 9.453 ; +; system:inst_cpu|system_uart_mc:uart_mc|system_uart_mc_rx:the_system_uart_mc_rx|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 ; ; ; ; 9.379 ; +; system:inst_cpu|system_uart_mc:uart_mc|system_uart_mc_rx:the_system_uart_mc_rx|altera_std_synchronizer:the_altera_std_synchronizer|dreg[0] ; ; ; ; 9.452 ; +---------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ @@ -4893,7 +4893,7 @@ Synchronizer Chain #3: Typical MTBF is Greater than 1 Billion Years ; Method of Synchronizer Identification ; User Specified ; ; ; ; ; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; ; Number of Synchronization Registers in Chain ; 2 ; ; ; ; -; Available Settling Time (ns) ; 19.143 ; ; ; ; +; Available Settling Time (ns) ; 19.132 ; ; ; ; ; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 1.25 ; ; ; ; ; Source Clock ; ; ; ; ; ; altera_reserved_tck ; ; 100.000 ; 10.0 MHz ; ; @@ -4904,8 +4904,8 @@ Synchronizer Chain #3: Typical MTBF is Greater than 1 Billion Years ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; ; ; ; ; ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; ; ; ; ; ; Synchronization Registers ; ; ; ; ; -; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3|din_s1 ; ; ; ; 9.576 ; -; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3|dreg[0] ; ; ; ; 9.567 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3|din_s1 ; ; ; ; 9.570 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer3|dreg[0] ; ; ; ; 9.562 ; +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ @@ -4931,7 +4931,7 @@ Synchronizer Chain #4: Typical MTBF is Greater than 1 Billion Years ; Method of Synchronizer Identification ; User Specified ; ; ; ; ; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ; ; Number of Synchronization Registers in Chain ; 2 ; ; ; ; -; Available Settling Time (ns) ; 19.149 ; ; ; ; +; Available Settling Time (ns) ; 19.133 ; ; ; ; ; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 1.25 ; ; ; ; ; Source Clock ; ; ; ; ; ; altera_reserved_tck ; ; 100.000 ; 10.0 MHz ; ; @@ -4942,8 +4942,8 @@ Synchronizer Chain #4: Typical MTBF is Greater than 1 Billion Years ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|virtual_ir_scan_reg ; ; ; ; ; ; sld_hub:auto_hub|sld_jtag_hub:\jtag_hub_gen:sld_jtag_hub_inst|node_ena[1]~reg0 ; ; ; ; ; ; Synchronization Registers ; ; ; ; ; -; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer2|din_s1 ; ; ; ; 9.578 ; -; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer2|dreg[0] ; ; ; ; 9.571 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer2|din_s1 ; ; ; ; 9.570 ; +; system:inst_cpu|system_cpu:cpu|system_cpu_nios2_oci:the_system_cpu_nios2_oci|system_cpu_jtag_debug_module_wrapper:the_system_cpu_jtag_debug_module_wrapper|system_cpu_jtag_debug_module_sysclk:the_system_cpu_jtag_debug_module_sysclk|altera_std_synchronizer:the_altera_std_synchronizer2|dreg[0] ; ; ; ; 9.563 ; +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+ @@ -5025,10 +5025,10 @@ Synchronizer Chain #6: Typical MTBF is n/a Years +-----------------------------------------------------------+--------+-------+----------+---------+---------------------+ ; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ; +-----------------------------------------------------------+--------+-------+----------+---------+---------------------+ -; Worst-case Slack ; 1.944 ; 0.110 ; 2.156 ; 1.171 ; 4.693 ; +; Worst-case Slack ; 2.068 ; 0.102 ; 1.948 ; 1.443 ; 4.694 ; ; CLOCK_50 ; N/A ; N/A ; N/A ; N/A ; 9.587 ; -; altera_reserved_tck ; N/A ; N/A ; N/A ; N/A ; 49.482 ; -; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 1.944 ; 0.110 ; 2.156 ; 1.171 ; 4.693 ; +; altera_reserved_tck ; N/A ; N/A ; N/A ; N/A ; 49.484 ; +; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 2.068 ; 0.102 ; 1.948 ; 1.443 ; 4.694 ; ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 97.388 ; 0.193 ; N/A ; N/A ; 49.744 ; ; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; ; CLOCK_50 ; N/A ; N/A ; N/A ; N/A ; 0.000 ; @@ -5043,8 +5043,8 @@ Synchronizer Chain #6: Typical MTBF is n/a Years +---------------------+---------------------+-------+-------+------------+----------------------------------------------------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +---------------------+---------------------+-------+-------+------------+----------------------------------------------------------+ -; altera_reserved_tdi ; altera_reserved_tck ; 2.187 ; 2.325 ; Rise ; altera_reserved_tck ; -; altera_reserved_tms ; altera_reserved_tck ; 6.453 ; 6.601 ; Rise ; altera_reserved_tck ; +; altera_reserved_tdi ; altera_reserved_tck ; 2.358 ; 2.500 ; Rise ; altera_reserved_tck ; +; altera_reserved_tms ; altera_reserved_tck ; 6.520 ; 6.737 ; Rise ; altera_reserved_tck ; ; DRAM_DQ[*] ; CLOCK_50 ; 1.016 ; 1.180 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; DRAM_DQ[0] ; CLOCK_50 ; 1.002 ; 1.166 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; DRAM_DQ[1] ; CLOCK_50 ; 1.002 ; 1.166 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; @@ -5062,15 +5062,15 @@ Synchronizer Chain #6: Typical MTBF is n/a Years ; DRAM_DQ[13] ; CLOCK_50 ; 0.975 ; 1.137 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; DRAM_DQ[14] ; CLOCK_50 ; 0.975 ; 1.137 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; DRAM_DQ[15] ; CLOCK_50 ; 1.001 ; 1.165 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; GPIO_0[*] ; CLOCK_50 ; 4.886 ; 5.468 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; GPIO_0[31] ; CLOCK_50 ; 4.886 ; 5.468 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; KEY[*] ; CLOCK_50 ; 2.462 ; 2.621 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; KEY[1] ; CLOCK_50 ; 2.462 ; 2.621 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; SW[*] ; CLOCK_50 ; 2.412 ; 2.539 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; SW[0] ; CLOCK_50 ; 2.344 ; 2.476 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; SW[1] ; CLOCK_50 ; 1.905 ; 2.019 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; SW[2] ; CLOCK_50 ; 1.971 ; 2.081 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; SW[3] ; CLOCK_50 ; 2.412 ; 2.539 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_0[*] ; CLOCK_50 ; 4.763 ; 5.286 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_0[31] ; CLOCK_50 ; 4.763 ; 5.286 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; KEY[*] ; CLOCK_50 ; 2.250 ; 2.395 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; KEY[1] ; CLOCK_50 ; 2.250 ; 2.395 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; SW[*] ; CLOCK_50 ; 2.528 ; 2.577 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; SW[0] ; CLOCK_50 ; 1.904 ; 2.082 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; SW[1] ; CLOCK_50 ; 2.528 ; 2.577 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; SW[2] ; CLOCK_50 ; 2.263 ; 2.391 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; SW[3] ; CLOCK_50 ; 2.034 ; 2.152 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +---------------------+---------------------+-------+-------+------------+----------------------------------------------------------+ @@ -5079,8 +5079,8 @@ Synchronizer Chain #6: Typical MTBF is n/a Years +---------------------+---------------------+--------+--------+------------+----------------------------------------------------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +---------------------+---------------------+--------+--------+------------+----------------------------------------------------------+ -; altera_reserved_tdi ; altera_reserved_tck ; 1.158 ; 1.079 ; Rise ; altera_reserved_tck ; -; altera_reserved_tms ; altera_reserved_tck ; 0.047 ; -0.239 ; Rise ; altera_reserved_tck ; +; altera_reserved_tdi ; altera_reserved_tck ; 1.171 ; 1.085 ; Rise ; altera_reserved_tck ; +; altera_reserved_tms ; altera_reserved_tck ; 0.221 ; -0.107 ; Rise ; altera_reserved_tck ; ; DRAM_DQ[*] ; CLOCK_50 ; -0.259 ; -0.525 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; DRAM_DQ[0] ; CLOCK_50 ; -0.270 ; -0.547 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; DRAM_DQ[1] ; CLOCK_50 ; -0.270 ; -0.547 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; @@ -5098,15 +5098,15 @@ Synchronizer Chain #6: Typical MTBF is n/a Years ; DRAM_DQ[13] ; CLOCK_50 ; -0.259 ; -0.525 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; DRAM_DQ[14] ; CLOCK_50 ; -0.259 ; -0.525 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; DRAM_DQ[15] ; CLOCK_50 ; -0.266 ; -0.544 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; GPIO_0[*] ; CLOCK_50 ; -2.213 ; -2.883 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; GPIO_0[31] ; CLOCK_50 ; -2.213 ; -2.883 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; KEY[*] ; CLOCK_50 ; -0.952 ; -1.241 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; KEY[1] ; CLOCK_50 ; -0.952 ; -1.241 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; SW[*] ; CLOCK_50 ; -0.793 ; -1.090 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; SW[0] ; CLOCK_50 ; -1.048 ; -1.331 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; SW[1] ; CLOCK_50 ; -0.793 ; -1.090 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; SW[2] ; CLOCK_50 ; -0.834 ; -1.121 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; SW[3] ; CLOCK_50 ; -1.087 ; -1.354 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_0[*] ; CLOCK_50 ; -2.270 ; -2.954 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_0[31] ; CLOCK_50 ; -2.270 ; -2.954 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; KEY[*] ; CLOCK_50 ; -0.813 ; -1.117 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; KEY[1] ; CLOCK_50 ; -0.813 ; -1.117 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; SW[*] ; CLOCK_50 ; -0.788 ; -1.098 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; SW[0] ; CLOCK_50 ; -0.788 ; -1.098 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; SW[1] ; CLOCK_50 ; -1.193 ; -1.410 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; SW[2] ; CLOCK_50 ; -0.974 ; -1.240 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; SW[3] ; CLOCK_50 ; -0.872 ; -1.156 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +---------------------+---------------------+--------+--------+------------+----------------------------------------------------------+ @@ -5115,7 +5115,7 @@ Synchronizer Chain #6: Typical MTBF is n/a Years +---------------------+---------------------+--------+--------+------------+----------------------------------------------------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +---------------------+---------------------+--------+--------+------------+----------------------------------------------------------+ -; altera_reserved_tdo ; altera_reserved_tck ; 10.825 ; 11.491 ; Fall ; altera_reserved_tck ; +; altera_reserved_tdo ; altera_reserved_tck ; 10.941 ; 11.609 ; Fall ; altera_reserved_tck ; ; DRAM_ADDR[*] ; CLOCK_50 ; 3.071 ; 3.042 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; DRAM_ADDR[0] ; CLOCK_50 ; 3.070 ; 3.041 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; DRAM_ADDR[1] ; CLOCK_50 ; 2.995 ; 2.967 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; @@ -5156,20 +5156,20 @@ Synchronizer Chain #6: Typical MTBF is n/a Years ; DRAM_DQM[0] ; CLOCK_50 ; 2.992 ; 2.964 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; DRAM_DQM[1] ; CLOCK_50 ; 2.992 ; 2.964 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; DRAM_RAS_N ; CLOCK_50 ; 3.079 ; 3.050 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; DRAM_WE_N ; CLOCK_50 ; 3.085 ; 3.056 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; GPIO_0[*] ; CLOCK_50 ; 6.024 ; 6.145 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; GPIO_0[33] ; CLOCK_50 ; 6.024 ; 6.145 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; GPIO_1[*] ; CLOCK_50 ; 4.729 ; 4.710 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; GPIO_1[0] ; CLOCK_50 ; 4.585 ; 4.674 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; GPIO_1[33] ; CLOCK_50 ; 4.729 ; 4.710 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; LED[*] ; CLOCK_50 ; 6.156 ; 6.335 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; LED[0] ; CLOCK_50 ; 4.856 ; 4.934 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; LED[1] ; CLOCK_50 ; 5.079 ; 5.159 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; LED[2] ; CLOCK_50 ; 4.657 ; 4.730 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; LED[3] ; CLOCK_50 ; 4.783 ; 4.843 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; LED[4] ; CLOCK_50 ; 6.068 ; 6.293 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; LED[5] ; CLOCK_50 ; 6.114 ; 6.335 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; LED[6] ; CLOCK_50 ; 6.156 ; 6.186 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_WE_N ; CLOCK_50 ; 3.075 ; 3.046 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_0[*] ; CLOCK_50 ; 5.296 ; 5.355 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_0[33] ; CLOCK_50 ; 5.296 ; 5.355 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_1[*] ; CLOCK_50 ; 5.510 ; 5.696 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_1[0] ; CLOCK_50 ; 5.510 ; 5.696 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_1[33] ; CLOCK_50 ; 5.155 ; 5.166 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[*] ; CLOCK_50 ; 6.097 ; 6.222 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[0] ; CLOCK_50 ; 5.276 ; 5.428 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[1] ; CLOCK_50 ; 5.942 ; 6.107 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[2] ; CLOCK_50 ; 5.578 ; 5.664 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[3] ; CLOCK_50 ; 5.000 ; 5.053 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[4] ; CLOCK_50 ; 4.739 ; 4.787 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[5] ; CLOCK_50 ; 6.097 ; 6.222 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[6] ; CLOCK_50 ; 4.461 ; 4.532 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; DRAM_CLK ; CLOCK_50 ; 1.207 ; ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[1] ; ; DRAM_CLK ; CLOCK_50 ; ; 1.166 ; Fall ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[1] ; ; LED[*] ; CLOCK_50 ; 4.715 ; 4.828 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; @@ -5182,7 +5182,7 @@ Synchronizer Chain #6: Typical MTBF is n/a Years +---------------------+---------------------+--------+--------+------------+----------------------------------------------------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +---------------------+---------------------+--------+--------+------------+----------------------------------------------------------+ -; altera_reserved_tdo ; altera_reserved_tck ; 5.028 ; 5.503 ; Fall ; altera_reserved_tck ; +; altera_reserved_tdo ; altera_reserved_tck ; 5.095 ; 5.554 ; Fall ; altera_reserved_tck ; ; DRAM_ADDR[*] ; CLOCK_50 ; 1.513 ; 1.513 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; DRAM_ADDR[0] ; CLOCK_50 ; 1.571 ; 1.591 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; DRAM_ADDR[1] ; CLOCK_50 ; 1.526 ; 1.529 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; @@ -5223,20 +5223,20 @@ Synchronizer Chain #6: Typical MTBF is n/a Years ; DRAM_DQM[0] ; CLOCK_50 ; 1.523 ; 1.526 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; DRAM_DQM[1] ; CLOCK_50 ; 1.523 ; 1.526 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; DRAM_RAS_N ; CLOCK_50 ; 1.575 ; 1.595 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; DRAM_WE_N ; CLOCK_50 ; 1.580 ; 1.600 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; GPIO_0[*] ; CLOCK_50 ; 3.161 ; 3.387 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; GPIO_0[33] ; CLOCK_50 ; 3.161 ; 3.387 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; GPIO_1[*] ; CLOCK_50 ; 2.342 ; 2.398 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; GPIO_1[0] ; CLOCK_50 ; 2.342 ; 2.472 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; GPIO_1[33] ; CLOCK_50 ; 2.533 ; 2.398 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; LED[*] ; CLOCK_50 ; 2.385 ; 2.512 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; LED[0] ; CLOCK_50 ; 2.475 ; 2.612 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; LED[1] ; CLOCK_50 ; 2.606 ; 2.760 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; LED[2] ; CLOCK_50 ; 2.385 ; 2.512 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; LED[3] ; CLOCK_50 ; 2.451 ; 2.581 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; LED[4] ; CLOCK_50 ; 3.178 ; 3.467 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; LED[5] ; CLOCK_50 ; 3.404 ; 3.620 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; -; LED[6] ; CLOCK_50 ; 3.182 ; 3.404 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; DRAM_WE_N ; CLOCK_50 ; 1.574 ; 1.594 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_0[*] ; CLOCK_50 ; 2.722 ; 2.884 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_0[33] ; CLOCK_50 ; 2.722 ; 2.884 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_1[*] ; CLOCK_50 ; 2.778 ; 2.616 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_1[0] ; CLOCK_50 ; 2.856 ; 3.084 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; GPIO_1[33] ; CLOCK_50 ; 2.778 ; 2.616 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[*] ; CLOCK_50 ; 2.241 ; 2.358 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[0] ; CLOCK_50 ; 2.763 ; 2.951 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[1] ; CLOCK_50 ; 3.103 ; 3.330 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[2] ; CLOCK_50 ; 2.909 ; 3.093 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[3] ; CLOCK_50 ; 2.553 ; 2.702 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[4] ; CLOCK_50 ; 2.418 ; 2.567 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[5] ; CLOCK_50 ; 3.366 ; 3.553 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; +; LED[6] ; CLOCK_50 ; 2.241 ; 2.358 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; ; DRAM_CLK ; CLOCK_50 ; -0.188 ; ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[1] ; ; DRAM_CLK ; CLOCK_50 ; ; -0.158 ; Fall ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[1] ; ; LED[*] ; CLOCK_50 ; 2.623 ; 2.720 ; Rise ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; @@ -5861,7 +5861,7 @@ Synchronizer Chain #6: Typical MTBF is n/a Years ; altera_reserved_tck ; altera_reserved_tck ; false path ; 0 ; false path ; false path ; ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; altera_reserved_tck ; false path ; 0 ; 0 ; 0 ; ; altera_reserved_tck ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; false path ; false path ; 0 ; 0 ; -; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 301552 ; 64 ; 224 ; 0 ; +; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 301680 ; 64 ; 224 ; 0 ; ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 253 ; 0 ; 0 ; 0 ; +----------------------------------------------------------+----------------------------------------------------------+------------+------------+------------+------------+ Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. @@ -5875,7 +5875,7 @@ Entries labeled "false path" only account for clock-to-clock false paths and not ; altera_reserved_tck ; altera_reserved_tck ; false path ; 0 ; false path ; false path ; ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; altera_reserved_tck ; false path ; 0 ; 0 ; 0 ; ; altera_reserved_tck ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; false path ; false path ; 0 ; 0 ; -; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 301552 ; 64 ; 224 ; 0 ; +; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] ; 301680 ; 64 ; 224 ; 0 ; ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] ; 253 ; 0 ; 0 ; 0 ; +----------------------------------------------------------+----------------------------------------------------------+------------+------------+------------+------------+ Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. @@ -5935,7 +5935,7 @@ No dedicated SERDES Receiver circuitry present in device or used in design Info: ******************************************************************* Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer Info: Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Full Version - Info: Processing started: Sun Mar 02 18:54:51 2014 + Info: Processing started: Mon Mar 03 16:13:07 2014 Info: Command: quartus_sta de0_nano_system -c de0_nano_system Info: qsta_default_script.tcl version: #1 Info (11104): Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead. @@ -5987,30 +5987,30 @@ Info (332104): Reading SDC File: 'system/synthesis/submodules/system_cpu.sdc' Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON Info: Analyzing Slow 1200mV 85C Model -Info (332146): Worst-case setup slack is 1.944 +Info (332146): Worst-case setup slack is 2.068 Info (332119): Slack End Point TNS Clock Info (332119): ========= ============= ===================== - Info (332119): 1.944 0.000 inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] + Info (332119): 2.068 0.000 inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] Info (332119): 97.388 0.000 inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] -Info (332146): Worst-case hold slack is 0.246 +Info (332146): Worst-case hold slack is 0.230 Info (332119): Slack End Point TNS Clock Info (332119): ========= ============= ===================== - Info (332119): 0.246 0.000 inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] + Info (332119): 0.230 0.000 inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] Info (332119): 0.361 0.000 inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] -Info (332146): Worst-case recovery slack is 2.156 +Info (332146): Worst-case recovery slack is 1.948 Info (332119): Slack End Point TNS Clock Info (332119): ========= ============= ===================== - Info (332119): 2.156 0.000 inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] -Info (332146): Worst-case removal slack is 2.023 + Info (332119): 1.948 0.000 inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] +Info (332146): Worst-case removal slack is 2.524 Info (332119): Slack End Point TNS Clock Info (332119): ========= ============= ===================== - Info (332119): 2.023 0.000 inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] -Info (332146): Worst-case minimum pulse width slack is 4.693 + Info (332119): 2.524 0.000 inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] +Info (332146): Worst-case minimum pulse width slack is 4.694 Info (332119): Slack End Point TNS Clock Info (332119): ========= ============= ===================== - Info (332119): 4.693 0.000 inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] + Info (332119): 4.694 0.000 inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] Info (332119): 9.835 0.000 CLOCK_50 - Info (332119): 49.624 0.000 altera_reserved_tck + Info (332119): 49.640 0.000 altera_reserved_tck Info (332119): 49.747 0.000 inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] Info (332114): Report Metastability: Found 6 synchronizer chains. Info (332114): Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. @@ -6018,7 +6018,7 @@ Info (332114): Report Metastability: Found 6 synchronizer chains. Info (332114): Number of Synchronizer Chains Found: 6 Info (332114): Shortest Synchronizer Chain: 2 Registers Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 0.333 - Info (332114): Worst Case Available Settling Time: 16.778 ns + Info (332114): Worst Case Available Settling Time: 17.228 ns Info (332114): Info (332114): Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. Info (332114): - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8 @@ -6026,30 +6026,30 @@ Info: Analyzing Slow 1200mV 0C Model Info (334003): Started post-fitting delay annotation Info (334004): Delay annotation completed successfully Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. -Info (332146): Worst-case setup slack is 2.250 +Info (332146): Worst-case setup slack is 2.461 Info (332119): Slack End Point TNS Clock Info (332119): ========= ============= ===================== - Info (332119): 2.250 0.000 inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] + Info (332119): 2.461 0.000 inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] Info (332119): 97.707 0.000 inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] -Info (332146): Worst-case hold slack is 0.242 +Info (332146): Worst-case hold slack is 0.227 Info (332119): Slack End Point TNS Clock Info (332119): ========= ============= ===================== - Info (332119): 0.242 0.000 inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] + Info (332119): 0.227 0.000 inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] Info (332119): 0.320 0.000 inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] -Info (332146): Worst-case recovery slack is 2.469 +Info (332146): Worst-case recovery slack is 2.272 Info (332119): Slack End Point TNS Clock Info (332119): ========= ============= ===================== - Info (332119): 2.469 0.000 inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] -Info (332146): Worst-case removal slack is 1.807 + Info (332119): 2.272 0.000 inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] +Info (332146): Worst-case removal slack is 2.259 Info (332119): Slack End Point TNS Clock Info (332119): ========= ============= ===================== - Info (332119): 1.807 0.000 inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] -Info (332146): Worst-case minimum pulse width slack is 4.719 + Info (332119): 2.259 0.000 inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] +Info (332146): Worst-case minimum pulse width slack is 4.716 Info (332119): Slack End Point TNS Clock Info (332119): ========= ============= ===================== - Info (332119): 4.719 0.000 inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] + Info (332119): 4.716 0.000 inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] Info (332119): 9.818 0.000 CLOCK_50 - Info (332119): 49.604 0.000 altera_reserved_tck + Info (332119): 49.608 0.000 altera_reserved_tck Info (332119): 49.744 0.000 inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] Info (332114): Report Metastability: Found 6 synchronizer chains. Info (332114): Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. @@ -6057,36 +6057,36 @@ Info (332114): Report Metastability: Found 6 synchronizer chains. Info (332114): Number of Synchronizer Chains Found: 6 Info (332114): Shortest Synchronizer Chain: 2 Registers Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 0.333 - Info (332114): Worst Case Available Settling Time: 17.094 ns + Info (332114): Worst Case Available Settling Time: 17.489 ns Info (332114): Info (332114): Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. Info (332114): - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8 Info: Analyzing Fast 1200mV 0C Model Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. -Info (332146): Worst-case setup slack is 3.218 +Info (332146): Worst-case setup slack is 3.368 Info (332119): Slack End Point TNS Clock Info (332119): ========= ============= ===================== - Info (332119): 3.218 0.000 inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] + Info (332119): 3.368 0.000 inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] Info (332119): 98.512 0.000 inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] -Info (332146): Worst-case hold slack is 0.110 +Info (332146): Worst-case hold slack is 0.102 Info (332119): Slack End Point TNS Clock Info (332119): ========= ============= ===================== - Info (332119): 0.110 0.000 inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] + Info (332119): 0.102 0.000 inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] Info (332119): 0.193 0.000 inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] -Info (332146): Worst-case recovery slack is 3.339 +Info (332146): Worst-case recovery slack is 3.214 Info (332119): Slack End Point TNS Clock Info (332119): ========= ============= ===================== - Info (332119): 3.339 0.000 inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] -Info (332146): Worst-case removal slack is 1.171 + Info (332119): 3.214 0.000 inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] +Info (332146): Worst-case removal slack is 1.443 Info (332119): Slack End Point TNS Clock Info (332119): ========= ============= ===================== - Info (332119): 1.171 0.000 inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] + Info (332119): 1.443 0.000 inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] Info (332146): Worst-case minimum pulse width slack is 4.749 Info (332119): Slack End Point TNS Clock Info (332119): ========= ============= ===================== Info (332119): 4.749 0.000 inst_pll_sys|altpll_component|auto_generated|pll1|clk[0] Info (332119): 9.587 0.000 CLOCK_50 - Info (332119): 49.482 0.000 altera_reserved_tck + Info (332119): 49.484 0.000 altera_reserved_tck Info (332119): 49.782 0.000 inst_pll_sys|altpll_component|auto_generated|pll1|clk[2] Info (332114): Report Metastability: Found 6 synchronizer chains. Info (332114): Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds. @@ -6094,15 +6094,15 @@ Info (332114): Report Metastability: Found 6 synchronizer chains. Info (332114): Number of Synchronizer Chains Found: 6 Info (332114): Shortest Synchronizer Chain: 2 Registers Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 0.333 - Info (332114): Worst Case Available Settling Time: 18.234 ns + Info (332114): Worst Case Available Settling Time: 18.472 ns Info (332114): Info (332114): Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. Info (332114): - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8 Info (332102): Design is not fully constrained for setup requirements Info (332102): Design is not fully constrained for hold requirements Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 1 warning - Info: Peak virtual memory: 563 megabytes - Info: Processing ended: Sun Mar 02 18:54:57 2014 + Info: Peak virtual memory: 569 megabytes + Info: Processing ended: Mon Mar 03 16:13:13 2014 Info: Elapsed time: 00:00:06 Info: Total CPU time (on all processors): 00:00:07 diff --git a/MCandWifiTestDE0/output_files/de0_nano_system.sta.summary b/MCandWifiTestDE0/output_files/de0_nano_system.sta.summary index d413fe18..022836ba 100644 --- a/MCandWifiTestDE0/output_files/de0_nano_system.sta.summary +++ b/MCandWifiTestDE0/output_files/de0_nano_system.sta.summary @@ -3,7 +3,7 @@ TimeQuest Timing Analyzer Summary ------------------------------------------------------------ Type : Slow 1200mV 85C Model Setup 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[0]' -Slack : 1.944 +Slack : 2.068 TNS : 0.000 Type : Slow 1200mV 85C Model Setup 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[2]' @@ -11,7 +11,7 @@ Slack : 97.388 TNS : 0.000 Type : Slow 1200mV 85C Model Hold 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[0]' -Slack : 0.246 +Slack : 0.230 TNS : 0.000 Type : Slow 1200mV 85C Model Hold 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[2]' @@ -19,15 +19,15 @@ Slack : 0.361 TNS : 0.000 Type : Slow 1200mV 85C Model Recovery 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[0]' -Slack : 2.156 +Slack : 1.948 TNS : 0.000 Type : Slow 1200mV 85C Model Removal 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[0]' -Slack : 2.023 +Slack : 2.524 TNS : 0.000 Type : Slow 1200mV 85C Model Minimum Pulse Width 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[0]' -Slack : 4.693 +Slack : 4.694 TNS : 0.000 Type : Slow 1200mV 85C Model Minimum Pulse Width 'CLOCK_50' @@ -35,7 +35,7 @@ Slack : 9.835 TNS : 0.000 Type : Slow 1200mV 85C Model Minimum Pulse Width 'altera_reserved_tck' -Slack : 49.624 +Slack : 49.640 TNS : 0.000 Type : Slow 1200mV 85C Model Minimum Pulse Width 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[2]' @@ -43,7 +43,7 @@ Slack : 49.747 TNS : 0.000 Type : Slow 1200mV 0C Model Setup 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[0]' -Slack : 2.250 +Slack : 2.461 TNS : 0.000 Type : Slow 1200mV 0C Model Setup 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[2]' @@ -51,7 +51,7 @@ Slack : 97.707 TNS : 0.000 Type : Slow 1200mV 0C Model Hold 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[0]' -Slack : 0.242 +Slack : 0.227 TNS : 0.000 Type : Slow 1200mV 0C Model Hold 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[2]' @@ -59,15 +59,15 @@ Slack : 0.320 TNS : 0.000 Type : Slow 1200mV 0C Model Recovery 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[0]' -Slack : 2.469 +Slack : 2.272 TNS : 0.000 Type : Slow 1200mV 0C Model Removal 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[0]' -Slack : 1.807 +Slack : 2.259 TNS : 0.000 Type : Slow 1200mV 0C Model Minimum Pulse Width 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[0]' -Slack : 4.719 +Slack : 4.716 TNS : 0.000 Type : Slow 1200mV 0C Model Minimum Pulse Width 'CLOCK_50' @@ -75,7 +75,7 @@ Slack : 9.818 TNS : 0.000 Type : Slow 1200mV 0C Model Minimum Pulse Width 'altera_reserved_tck' -Slack : 49.604 +Slack : 49.608 TNS : 0.000 Type : Slow 1200mV 0C Model Minimum Pulse Width 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[2]' @@ -83,7 +83,7 @@ Slack : 49.744 TNS : 0.000 Type : Fast 1200mV 0C Model Setup 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[0]' -Slack : 3.218 +Slack : 3.368 TNS : 0.000 Type : Fast 1200mV 0C Model Setup 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[2]' @@ -91,7 +91,7 @@ Slack : 98.512 TNS : 0.000 Type : Fast 1200mV 0C Model Hold 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[0]' -Slack : 0.110 +Slack : 0.102 TNS : 0.000 Type : Fast 1200mV 0C Model Hold 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[2]' @@ -99,11 +99,11 @@ Slack : 0.193 TNS : 0.000 Type : Fast 1200mV 0C Model Recovery 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[0]' -Slack : 3.339 +Slack : 3.214 TNS : 0.000 Type : Fast 1200mV 0C Model Removal 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[0]' -Slack : 1.171 +Slack : 1.443 TNS : 0.000 Type : Fast 1200mV 0C Model Minimum Pulse Width 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[0]' @@ -115,7 +115,7 @@ Slack : 9.587 TNS : 0.000 Type : Fast 1200mV 0C Model Minimum Pulse Width 'altera_reserved_tck' -Slack : 49.482 +Slack : 49.484 TNS : 0.000 Type : Fast 1200mV 0C Model Minimum Pulse Width 'inst_pll_sys|altpll_component|auto_generated|pll1|clk[2]' diff --git a/MCandWifiTestDE0/output_files/greybox_tmp/cbx_args.txt b/MCandWifiTestDE0/output_files/greybox_tmp/cbx_args.txt new file mode 100644 index 00000000..d915da54 --- /dev/null +++ b/MCandWifiTestDE0/output_files/greybox_tmp/cbx_args.txt @@ -0,0 +1,70 @@ +BANDWIDTH_TYPE=AUTO +CLK0_DIVIDE_BY=1 +CLK0_DUTY_CYCLE=50 +CLK0_MULTIPLY_BY=2 +CLK0_PHASE_SHIFT=0 +CLK1_DIVIDE_BY=1 +CLK1_DUTY_CYCLE=50 +CLK1_MULTIPLY_BY=2 +CLK1_PHASE_SHIFT=-1500 +CLK2_DIVIDE_BY=5 +CLK2_DUTY_CYCLE=50 +CLK2_MULTIPLY_BY=1 +CLK2_PHASE_SHIFT=0 +COMPENSATE_CLOCK=CLK0 +INCLK0_INPUT_FREQUENCY=20000 +INTENDED_DEVICE_FAMILY="Cyclone IV E" +LPM_TYPE=altpll +OPERATION_MODE=NORMAL +PLL_TYPE=AUTO +PORT_ACTIVECLOCK=PORT_UNUSED +PORT_ARESET=PORT_UNUSED +PORT_CLKBAD0=PORT_UNUSED +PORT_CLKBAD1=PORT_UNUSED +PORT_CLKLOSS=PORT_UNUSED +PORT_CLKSWITCH=PORT_UNUSED +PORT_CONFIGUPDATE=PORT_UNUSED +PORT_FBIN=PORT_UNUSED +PORT_INCLK0=PORT_USED +PORT_INCLK1=PORT_UNUSED +PORT_LOCKED=PORT_USED +PORT_PFDENA=PORT_UNUSED +PORT_PHASECOUNTERSELECT=PORT_UNUSED +PORT_PHASEDONE=PORT_UNUSED +PORT_PHASESTEP=PORT_UNUSED +PORT_PHASEUPDOWN=PORT_UNUSED +PORT_PLLENA=PORT_UNUSED +PORT_SCANACLR=PORT_UNUSED +PORT_SCANCLK=PORT_UNUSED +PORT_SCANCLKENA=PORT_UNUSED +PORT_SCANDATA=PORT_UNUSED +PORT_SCANDATAOUT=PORT_UNUSED +PORT_SCANDONE=PORT_UNUSED +PORT_SCANREAD=PORT_UNUSED +PORT_SCANWRITE=PORT_UNUSED +PORT_clk0=PORT_USED +PORT_clk1=PORT_USED +PORT_clk2=PORT_USED +PORT_clk3=PORT_UNUSED +PORT_clk4=PORT_UNUSED +PORT_clk5=PORT_UNUSED +PORT_clkena0=PORT_UNUSED +PORT_clkena1=PORT_UNUSED +PORT_clkena2=PORT_UNUSED +PORT_clkena3=PORT_UNUSED +PORT_clkena4=PORT_UNUSED +PORT_clkena5=PORT_UNUSED +PORT_extclk0=PORT_UNUSED +PORT_extclk1=PORT_UNUSED +PORT_extclk2=PORT_UNUSED +PORT_extclk3=PORT_UNUSED +SELF_RESET_ON_LOSS_LOCK=ON +WIDTH_CLOCK=5 +DEVICE_FAMILY="Cyclone IV E" +CBX_AUTO_BLACKBOX=ALL +inclk +inclk +clk +clk +clk +locked diff --git a/MCandWifiTestDE0/output_files/pll_sys.qip b/MCandWifiTestDE0/output_files/pll_sys.qip new file mode 100644 index 00000000..e69de29b diff --git a/MCandWifiTestDE0/system.html b/MCandWifiTestDE0/system.html index 9741376a..76a883bc 100644 --- a/MCandWifiTestDE0/system.html +++ b/MCandWifiTestDE0/system.html @@ -67,7 +67,7 @@ - +
2014.03.02.17:35:472014.03.03.15:46:04 Datasheet
@@ -747,22 +747,22 @@

cpu

altera_nios2_qsys v12.1 - data_master   + d_irq   -   avalon_rs232_slave +   interrupt - d_irq   + data_master   -   interrupt +   avalon_rs232_slave @@ -1411,7 +1411,7 @@

Parameters

timestamp - 1393806947 + 1393886764 AUTO_CLK_CLOCK_RATE @@ -1444,7 +1444,7 @@

Software Assignments

TIMESTAMP - 1393806947 + 1393886764 @@ -3127,16 +3127,16 @@

rs232_wifi

altera_up_avalon_rs232 v12.0   clock_reset_reset - data_master   + d_irq   -   avalon_rs232_slave +   interrupt - d_irq   + data_master   -   interrupt +   avalon_rs232_slave @@ -3200,8 +3200,8 @@

Software Assignments

(none) - - + +
generation took 0.00 secondsrendering took 0.10 secondsgeneration took 0.01 secondsrendering took 0.11 seconds
diff --git a/MCandWifiTestDE0/system.qsys b/MCandWifiTestDE0/system.qsys index 19cca989..dadcc069 100644 --- a/MCandWifiTestDE0/system.qsys +++ b/MCandWifiTestDE0/system.qsys @@ -22,6 +22,11 @@ } element rs232_wifi.avalon_rs232_slave { + datum _lockedAddress + { + value = "0"; + type = "boolean"; + } datum baseAddress { value = "33558704"; @@ -113,51 +118,51 @@ type = "int"; } } - element sdram.s1 + element sys_clk_timer.s1 { datum baseAddress { - value = "16777216"; + value = "33558624"; type = "String"; } } - element pio_led.s1 + element sdram.s1 { datum baseAddress { - value = "33558560"; + value = "16777216"; type = "String"; } } - element pio_sw.s1 + element pio_key_left.s1 { datum baseAddress { - value = "33558672"; + value = "33558688"; type = "String"; } } - element uart_wifi.s1 + element pio_led.s1 { datum baseAddress { - value = "33558592"; + value = "33558560"; type = "String"; } } - element pio_key_left.s1 + element pio_sw.s1 { datum baseAddress { - value = "33558688"; + value = "33558672"; type = "String"; } } - element sys_clk_timer.s1 + element uart_wifi.s1 { datum baseAddress { - value = "33558624"; + value = "33558592"; type = "String"; } } @@ -237,7 +242,7 @@ - + @@ -835,14 +840,6 @@ version="12.1" start="cpu.jtag_debug_module_reset" end="rs232_wifi.clock_reset_reset" /> - - - - + + + + diff --git a/MCandWifiTestDE0/system.sopcinfo b/MCandWifiTestDE0/system.sopcinfo index d9b15be1..0d6d5b88 100644 --- a/MCandWifiTestDE0/system.sopcinfo +++ b/MCandWifiTestDE0/system.sopcinfo @@ -1,11 +1,11 @@ - + java.lang.Integer - 1393806947 + 1393886764 false true false @@ -2975,7 +2975,7 @@ the requested settings for a module instance. --> embeddedsw.CMacro.TIMESTAMP - 1393806947 + 1393886764 int @@ -2987,7 +2987,7 @@ the requested settings for a module instance. --> int - 1393806947 + 1393886764 false false false @@ -12247,27 +12247,11 @@ parameters are a RESULT of the module parameters. --> clock_reset_reset - - int - 1 - false - true - true - true - - - java.math.BigInteger - 0x020010b0 - false - true - true - true - + start="clk_sys.clk" + end="rs232_wifi.clock_reset"> java.lang.String UNKNOWN @@ -12284,17 +12268,25 @@ parameters are a RESULT of the module parameters. --> true true - cpu - data_master + clk_sys + clk rs232_wifi - avalon_rs232_slave + clock_reset + start="cpu.d_irq" + end="rs232_wifi.interrupt"> + + int + 6 + false + true + true + true + java.lang.String UNKNOWN @@ -12311,20 +12303,28 @@ parameters are a RESULT of the module parameters. --> true true - clk_sys - clk + cpu + d_irq rs232_wifi - clock_reset + interrupt - + start="cpu.data_master" + end="rs232_wifi.avalon_rs232_slave"> + int - 6 + 1 + false + true + true + true + + + java.math.BigInteger + 0x020010b0 false true true @@ -12347,33 +12347,41 @@ parameters are a RESULT of the module parameters. --> true cpu - d_irq + data_master rs232_wifi - interrupt + avalon_rs232_slave + + 6 + interrupt + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IConnection + Interrupt Connection + 12.1 + 1 - clock_source + nios_custom_instruction_master com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - Clock Source + com.altera.entityinterfaces.IMutableConnectionPoint + Custom Instruction Master 12.1 3 - reset_sink + clock_sink com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint - Reset Input + Clock Input 12.1 - 10 - reset_sink + 6 + conduit com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint - Reset Input - 12.1 + Conduit Endpoint + 7.1 2 @@ -12384,187 +12392,179 @@ parameters are a RESULT of the module parameters. --> 12.1 - 1 - altera_avalon_timer + 9 + avalon_slave com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - Interval Timer + com.altera.entityinterfaces.IMutableConnectionPoint + Avalon Memory Mapped Slave 12.1 - 3 - avalon_slave + 5 + interrupt_sender com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint - Avalon Memory Mapped Slave + Interrupt Sender 12.1 - 4 - altera_avalon_pio + 3 + avalon_slave com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - PIO (Parallel I/O) + com.altera.entityinterfaces.IMutableConnectionPoint + Avalon Memory Mapped Slave 12.1 - 12 - clock + 10 + reset_sink com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IConnection - Clock Connection + com.altera.entityinterfaces.IMutableConnectionPoint + Reset Input 12.1 1 - conduit_end + altera_avalon_jtag_uart com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Conduit + com.altera.entityinterfaces.IModule + JTAG UART 12.1 1 - altera_avalon_new_sdram_controller + altera_nios2_qsys com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IModule - SDRAM Controller + Nios II Processor 12.1 - 6 - interrupt + 1 + clock_source com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IConnection - Interrupt Connection + com.altera.entityinterfaces.IModule + Clock Source 12.1 - 24 - reset + 1 + altera_avalon_new_sdram_controller com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IConnection - Reset Connection + com.altera.entityinterfaces.IModule + SDRAM Controller 12.1 1 - interrupt_sender + altera_up_avalon_rs232 com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Interrupt Sender - 12.1 + com.altera.entityinterfaces.IModule + RS232 UART + 12.0 - 3 - clock_sink + 1 + interrupt_receiver com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint - Clock Input + Interrupt Receiver 12.1 - 1 - altera_nios2_qsys + 14 + avalon com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - Nios II Processor + com.altera.entityinterfaces.IConnection + Avalon Memory Mapped Connection 12.1 - 9 - avalon_slave + 1 + reset_source com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint - Avalon Memory Mapped Slave + Reset Output 12.1 1 - nios_custom_instruction_master + interrupt_sender com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint - Custom Instruction Master + Interrupt Sender 12.1 - 6 - conduit + 1 + reset_source com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint - Conduit Endpoint - 7.1 + Reset Output + 12.1 - 5 - interrupt_sender + 1 + altera_avalon_sysid_qsys com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Interrupt Sender + com.altera.entityinterfaces.IModule + System ID Peripheral 12.1 - 14 - avalon + 12 + clock com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IConnection - Avalon Memory Mapped Connection + Clock Connection 12.1 - 10 - clock_sink + 1 + clock_source com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint - Clock Input + Clock Output 12.1 1 - altera_avalon_sysid_qsys + altera_avalon_timer com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IModule - System ID Peripheral + Interval Timer 12.1 1 - reset_source + conduit_end com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint - Reset Output + Conduit 12.1 - 1 - clock_source + 3 + reset_sink com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint - Clock Output + Reset Input 12.1 - 2 - altera_avalon_uart + 4 + altera_avalon_pio com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IModule - UART (RS-232 Serial Port) + PIO (Parallel I/O) 12.1 - 1 - altera_up_avalon_rs232 - com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - RS232 UART - 12.0 - - - 1 - reset_source + 24 + reset com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Reset Output + com.altera.entityinterfaces.IConnection + Reset Connection 12.1 @@ -12576,19 +12576,19 @@ parameters are a RESULT of the module parameters. --> 12.1 - 1 - altera_avalon_jtag_uart + 10 + clock_sink com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IModule - JTAG UART + com.altera.entityinterfaces.IMutableConnectionPoint + Clock Input 12.1 - 1 - interrupt_receiver + 2 + altera_avalon_uart com.altera.entityinterfaces.IElementClass - com.altera.entityinterfaces.IMutableConnectionPoint - Interrupt Receiver + com.altera.entityinterfaces.IModule + UART (RS-232 Serial Port) 12.1 12.1sp1 243 diff --git a/MCandWifiTestDE0/system/synthesis/submodules/system_sysid.v b/MCandWifiTestDE0/system/synthesis/submodules/system_sysid.v index 52f1e1eb..79421175 100644 --- a/MCandWifiTestDE0/system/synthesis/submodules/system_sysid.v +++ b/MCandWifiTestDE0/system/synthesis/submodules/system_sysid.v @@ -36,7 +36,7 @@ module system_sysid ( wire [ 31: 0] readdata; //control_slave, which is an e_avalon_slave - assign readdata = address ? 1393806947 : 0; + assign readdata = address ? 1393886764 : 0; endmodule diff --git a/MCandWifiTestDE0/system/synthesis/system.qip b/MCandWifiTestDE0/system/synthesis/system.qip index addea882..e54bfa1a 100644 --- a/MCandWifiTestDE0/system/synthesis/system.qip +++ b/MCandWifiTestDE0/system/synthesis/system.qip @@ -2,7 +2,7 @@ set_global_assignment -entity "system" -library "system" -name IP_TOOL_NAME "qsy set_global_assignment -entity "system" -library "system" -name IP_TOOL_VERSION "12.1sp1" set_global_assignment -entity "system" -library "system" -name IP_TOOL_ENV "qsys" set_global_assignment -library "system" -name SOPCINFO_FILE [file join $::quartus(qip_path) "../../system.sopcinfo"] -set_instance_assignment -entity "system" -library "system" -name SLD_INFO "QSYS_NAME system HAS_SOPCINFO 1 GENERATION_ID 1393806947" +set_instance_assignment -entity "system" -library "system" -name SLD_INFO "QSYS_NAME system HAS_SOPCINFO 1 GENERATION_ID 1393886764" set_global_assignment -library "system" -name MISC_FILE [file join $::quartus(qip_path) "../../system.cmp"] set_global_assignment -name SYNTHESIS_ONLY_QIP ON set_global_assignment -library "system" -name MISC_FILE [file join $::quartus(qip_path) "../../system.qsys"] diff --git a/MCandWifiTestDE0/system/synthesis/system.v b/MCandWifiTestDE0/system/synthesis/system.v index d3e02492..dbeff66c 100644 --- a/MCandWifiTestDE0/system/synthesis/system.v +++ b/MCandWifiTestDE0/system/synthesis/system.v @@ -1,6 +1,6 @@ // system.v -// Generated using ACDS version 12.1sp1 243 at 2014.03.02.17:35:49 +// Generated using ACDS version 12.1sp1 243 at 2014.03.03.15:46:06 `timescale 1 ps / 1 ps module system ( diff --git a/MCandWifiTestDE0/system_generation_28.rpt b/MCandWifiTestDE0/system_generation_28.rpt new file mode 100644 index 00000000..a87b3e88 --- /dev/null +++ b/MCandWifiTestDE0/system_generation_28.rpt @@ -0,0 +1,246 @@ +Info: Starting: Create block symbol file (.bsf) +Info: ip-generate --project-directory=C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/ --output-directory=C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/ --report-file=bsf:C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system.bsf --system-info=DEVICE_FAMILY="Cyclone IV E" --system-info=DEVICE=EP4CE22F17C6 --system-info=DEVICE_SPEEDGRADE=6 --component-file=C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system.qsys +Progress: Loading MCandWifiTestDE0/system.qsys +Progress: Reading input file +Progress: Adding clk_sys [clock_source 12.1] +Progress: Parameterizing module clk_sys +Progress: Adding cpu [altera_nios2_qsys 12.1] +Progress: Parameterizing module cpu +Progress: Adding sysid [altera_avalon_sysid_qsys 12.1] +Progress: Parameterizing module sysid +Progress: Adding sdram [altera_avalon_new_sdram_controller 12.1] +Progress: Parameterizing module sdram +Progress: Adding sys_clk_timer [altera_avalon_timer 12.1] +Progress: Parameterizing module sys_clk_timer +Progress: Adding uart_wifi [altera_avalon_uart 12.1] +Progress: Parameterizing module uart_wifi +Progress: Adding pio_led [altera_avalon_pio 12.1] +Progress: Parameterizing module pio_led +Progress: Adding pio_key_left [altera_avalon_pio 12.1] +Progress: Parameterizing module pio_key_left +Progress: Adding pio_sw [altera_avalon_pio 12.1] +Progress: Parameterizing module pio_sw +Progress: Adding jtag_uart_0 [altera_avalon_jtag_uart 12.1] +Progress: Parameterizing module jtag_uart_0 +Progress: Adding pio_ir_emitter [altera_avalon_pio 12.1] +Progress: Parameterizing module pio_ir_emitter +Progress: Adding uart_mc [altera_avalon_uart 12.1] +Progress: Parameterizing module uart_mc +Progress: Adding rs232_wifi [altera_up_avalon_rs232 12.0] +Progress: Parameterizing module rs232_wifi +Progress: Building connections +Progress: Parameterizing connections +Progress: Validating +Progress: Done reading input file +Info: system.sysid: System ID is not assigned automatically. Edit the System ID parameter to provide a unique ID +Info: system.sysid: Time stamp will be automatically updated when this component is generated. +Info: system.pio_key_left: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. +Info: system.pio_sw: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. +Info: ip-generate succeeded. +Info: Finished: Create block symbol file (.bsf) +Info: +Info: Starting: Create HDL design files for synthesis +Info: ip-generate --project-directory=C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/ --output-directory=C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/ --file-set=QUARTUS_SYNTH --report-file=sopcinfo:C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system.sopcinfo --report-file=html:C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system.html --report-file=qip:C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.qip --report-file=cmp:C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system.cmp --system-info=DEVICE_FAMILY="Cyclone IV E" --system-info=DEVICE=EP4CE22F17C6 --system-info=DEVICE_SPEEDGRADE=6 --component-file=C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system.qsys +Progress: Loading MCandWifiTestDE0/system.qsys +Progress: Reading input file +Progress: Adding clk_sys [clock_source 12.1] +Progress: Parameterizing module clk_sys +Progress: Adding cpu [altera_nios2_qsys 12.1] +Progress: Parameterizing module cpu +Progress: Adding sysid [altera_avalon_sysid_qsys 12.1] +Progress: Parameterizing module sysid +Progress: Adding sdram [altera_avalon_new_sdram_controller 12.1] +Progress: Parameterizing module sdram +Progress: Adding sys_clk_timer [altera_avalon_timer 12.1] +Progress: Parameterizing module sys_clk_timer +Progress: Adding uart_wifi [altera_avalon_uart 12.1] +Progress: Parameterizing module uart_wifi +Progress: Adding pio_led [altera_avalon_pio 12.1] +Progress: Parameterizing module pio_led +Progress: Adding pio_key_left [altera_avalon_pio 12.1] +Progress: Parameterizing module pio_key_left +Progress: Adding pio_sw [altera_avalon_pio 12.1] +Progress: Parameterizing module pio_sw +Progress: Adding jtag_uart_0 [altera_avalon_jtag_uart 12.1] +Progress: Parameterizing module jtag_uart_0 +Progress: Adding pio_ir_emitter [altera_avalon_pio 12.1] +Progress: Parameterizing module pio_ir_emitter +Progress: Adding uart_mc [altera_avalon_uart 12.1] +Progress: Parameterizing module uart_mc +Progress: Adding rs232_wifi [altera_up_avalon_rs232 12.0] +Progress: Parameterizing module rs232_wifi +Progress: Building connections +Progress: Parameterizing connections +Progress: Validating +Progress: Done reading input file +Info: system.sysid: System ID is not assigned automatically. Edit the System ID parameter to provide a unique ID +Info: system.sysid: Time stamp will be automatically updated when this component is generated. +Info: system.pio_key_left: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. +Info: system.pio_sw: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. +Info: system: Generating system "system" for QUARTUS_SYNTH +Info: pipeline_bridge_swap_transform: After transform: 13 modules, 56 connections +Info: No custom instruction connections, skipping transform +Info: merlin_translator_transform: After transform: 27 modules, 112 connections +Info: merlin_domain_transform: After transform: 54 modules, 296 connections +Info: merlin_router_transform: After transform: 68 modules, 352 connections +Info: merlin_traffic_limiter_transform: After transform: 70 modules, 362 connections +Info: merlin_burst_transform: After transform: 71 modules, 366 connections +Info: reset_adaptation_transform: After transform: 72 modules, 286 connections +Info: merlin_network_to_switch_transform: After transform: 99 modules, 342 connections +Info: merlin_width_transform: After transform: 101 modules, 348 connections +Info: limiter_update_transform: After transform: 101 modules, 350 connections +Info: merlin_interrupt_mapper_transform: After transform: 102 modules, 353 connections +Warning: system: "No matching role found for uart_wifi:s1:dataavailable (dataavailable)" +Warning: system: "No matching role found for uart_wifi:s1:readyfordata (readyfordata)" +Warning: system: "No matching role found for uart_mc:s1:dataavailable (dataavailable)" +Warning: system: "No matching role found for uart_mc:s1:readyfordata (readyfordata)" +Info: cpu: Starting RTL generation for module 'system_cpu' +Info: cpu: Generation command is [exec C:/altera/12.1sp1/quartus/../ip/altera/nios2_ip/altera_nios2/eperl.exe -I C:/altera/12.1sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/12.1sp1/quartus/sopc_builder/bin/europa -I C:/altera/12.1sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/12.1sp1/quartus/sopc_builder/bin -I C:/altera/12.1sp1/quartus/../ip/altera/nios2_ip/altera_nios2/cpu_lib -I C:/altera/12.1sp1/quartus/../ip/altera/nios2_ip/altera_nios2/nios_lib -I C:/altera/12.1sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -I C:/altera/12.1sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -- C:/altera/12.1sp1/quartus/../ip/altera/nios2_ip/altera_nios2/generate_rtl.epl --name=system_cpu --dir=C:/Users/gongal/AppData/Local/Temp/alt6132_778045434417866752.dir/0001_cpu_gen/ --quartus_dir=C:/altera/12.1sp1/quartus --verilog --config=C:/Users/gongal/AppData/Local/Temp/alt6132_778045434417866752.dir/0001_cpu_gen//system_cpu_processor_configuration.pl --do_build_sim=0 --bogus ] +Info: cpu: # 2014.03.03 15:19:21 (*) Starting Nios II generation +Info: cpu: # 2014.03.03 15:19:21 (*) Checking for plaintext license. +Info: cpu: # 2014.03.03 15:19:22 (*) Couldn't query license setup in Quartus directory C:/altera/12.1sp1/quartus +Info: cpu: # 2014.03.03 15:19:22 (*) Defaulting to contents of LM_LICENSE_FILE environment variable +Info: cpu: # 2014.03.03 15:19:22 (*) Plaintext license not found. +Info: cpu: # 2014.03.03 15:19:22 (*) Checking for encrypted license (non-evaluation). +Info: cpu: # 2014.03.03 15:19:22 (*) Couldn't query license setup in Quartus directory C:/altera/12.1sp1/quartus +Info: cpu: # 2014.03.03 15:19:22 (*) Defaulting to contents of LM_LICENSE_FILE environment variable +Info: cpu: # 2014.03.03 15:19:22 (*) Encrypted license found. SOF will not be time-limited. +Info: cpu: # 2014.03.03 15:19:22 (*) Elaborating CPU configuration settings +Info: cpu: # 2014.03.03 15:19:22 (*) Creating all objects for CPU +Info: cpu: # 2014.03.03 15:19:22 (*) Testbench +Info: cpu: # 2014.03.03 15:19:22 (*) Instruction decoding +Info: cpu: # 2014.03.03 15:19:22 (*) Instruction fields +Info: cpu: # 2014.03.03 15:19:23 (*) Instruction decodes +Info: cpu: # 2014.03.03 15:19:23 (*) Signals for RTL simulation waveforms +Info: cpu: # 2014.03.03 15:19:23 (*) Instruction controls +Info: cpu: # 2014.03.03 15:19:23 (*) Pipeline frontend +Info: cpu: # 2014.03.03 15:19:23 (*) Pipeline backend +Info: cpu: # 2014.03.03 15:19:26 (*) Generating RTL from CPU objects +Info: cpu: # 2014.03.03 15:19:29 (*) Creating encrypted RTL +Info: cpu: # 2014.03.03 15:19:30 (*) Done Nios II generation +Info: cpu: Done RTL generation for module 'system_cpu' +Info: cpu: "system" instantiated altera_nios2_qsys "cpu" +Info: sysid: "system" instantiated altera_avalon_sysid_qsys "sysid" +Info: Starting classic module elaboration. +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6132_778045434417866752.dir/0003_sopclgen --no_splash --refresh C:/Users/gongal/AppData/Local/Temp/alt6132_778045434417866752.dir/0003_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +Info: Finished elaborating classic module. +Executing: C:/altera/12.1sp1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/Users/gongal/AppData/Local/Temp/alt6132_778045434417866752.dir/0003_sopclgen/yysystem.ptf +Info: Running sopc_builder... +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6132_778045434417866752.dir/0003_sopclgen --generate C:/Users/gongal/AppData/Local/Temp/alt6132_778045434417866752.dir/0003_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +No .sopc_builder configuration file(!) +. +. +# 2014.03.03 15:19:34 (*) Running Test Generator Program for system_sdram +# 2014.03.03 15:19:35 (*) Success: sopc_builder finished. +Info: sdram: "system" instantiated altera_avalon_new_sdram_controller "sdram" +Info: Starting classic module elaboration. +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6132_778045434417866752.dir/0004_sopclgen --no_splash --refresh C:/Users/gongal/AppData/Local/Temp/alt6132_778045434417866752.dir/0004_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +Info: Finished elaborating classic module. +Executing: C:/altera/12.1sp1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/Users/gongal/AppData/Local/Temp/alt6132_778045434417866752.dir/0004_sopclgen/yysystem.ptf +Info: Running sopc_builder... +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6132_778045434417866752.dir/0004_sopclgen --generate C:/Users/gongal/AppData/Local/Temp/alt6132_778045434417866752.dir/0004_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +No .sopc_builder configuration file(!) +. +# 2014.03.03 15:19:40 (*) Success: sopc_builder finished. +Info: sys_clk_timer: "system" instantiated altera_avalon_timer "sys_clk_timer" +Info: Starting classic module elaboration. +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6132_778045434417866752.dir/0005_sopclgen --no_splash --refresh C:/Users/gongal/AppData/Local/Temp/alt6132_778045434417866752.dir/0005_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +Info: Finished elaborating classic module. +Executing: C:/altera/12.1sp1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/Users/gongal/AppData/Local/Temp/alt6132_778045434417866752.dir/0005_sopclgen/yysystem.ptf +Info: Running sopc_builder... +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6132_778045434417866752.dir/0005_sopclgen --generate C:/Users/gongal/AppData/Local/Temp/alt6132_778045434417866752.dir/0005_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +No .sopc_builder configuration file(!) +. +# 2014.03.03 15:19:44 (*) Success: sopc_builder finished. +Info: uart_wifi: "system" instantiated altera_avalon_uart "uart_wifi" +Info: Starting classic module elaboration. +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6132_778045434417866752.dir/0006_sopclgen --no_splash --refresh C:/Users/gongal/AppData/Local/Temp/alt6132_778045434417866752.dir/0006_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +Info: Finished elaborating classic module. +Executing: C:/altera/12.1sp1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/Users/gongal/AppData/Local/Temp/alt6132_778045434417866752.dir/0006_sopclgen/yysystem.ptf +Info: Running sopc_builder... +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6132_778045434417866752.dir/0006_sopclgen --generate C:/Users/gongal/AppData/Local/Temp/alt6132_778045434417866752.dir/0006_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +No .sopc_builder configuration file(!) +. +# 2014.03.03 15:19:49 (*) Success: sopc_builder finished. +Info: pio_led: "system" instantiated altera_avalon_pio "pio_led" +Info: Starting classic module elaboration. +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6132_778045434417866752.dir/0007_sopclgen --no_splash --refresh C:/Users/gongal/AppData/Local/Temp/alt6132_778045434417866752.dir/0007_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +Info: Finished elaborating classic module. +Executing: C:/altera/12.1sp1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/Users/gongal/AppData/Local/Temp/alt6132_778045434417866752.dir/0007_sopclgen/yysystem.ptf +Info: Running sopc_builder... +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6132_778045434417866752.dir/0007_sopclgen --generate C:/Users/gongal/AppData/Local/Temp/alt6132_778045434417866752.dir/0007_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +No .sopc_builder configuration file(!) +. +# 2014.03.03 15:19:53 (*) Success: sopc_builder finished. +Info: pio_key_left: "system" instantiated altera_avalon_pio "pio_key_left" +Info: Starting classic module elaboration. +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6132_778045434417866752.dir/0008_sopclgen --no_splash --refresh C:/Users/gongal/AppData/Local/Temp/alt6132_778045434417866752.dir/0008_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +Info: Finished elaborating classic module. +Executing: C:/altera/12.1sp1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/Users/gongal/AppData/Local/Temp/alt6132_778045434417866752.dir/0008_sopclgen/yysystem.ptf +Info: Running sopc_builder... +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6132_778045434417866752.dir/0008_sopclgen --generate C:/Users/gongal/AppData/Local/Temp/alt6132_778045434417866752.dir/0008_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +No .sopc_builder configuration file(!) +. +# 2014.03.03 15:19:57 (*) Success: sopc_builder finished. +Info: pio_sw: "system" instantiated altera_avalon_pio "pio_sw" +Info: Starting classic module elaboration. +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6132_778045434417866752.dir/0009_sopclgen --no_splash --refresh C:/Users/gongal/AppData/Local/Temp/alt6132_778045434417866752.dir/0009_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +Info: Finished elaborating classic module. +Executing: C:/altera/12.1sp1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/Users/gongal/AppData/Local/Temp/alt6132_778045434417866752.dir/0009_sopclgen/yysystem.ptf +Info: Running sopc_builder... +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6132_778045434417866752.dir/0009_sopclgen --generate C:/Users/gongal/AppData/Local/Temp/alt6132_778045434417866752.dir/0009_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +No .sopc_builder configuration file(!) +. +# 2014.03.03 15:20:02 (*) Success: sopc_builder finished. +Info: jtag_uart_0: "system" instantiated altera_avalon_jtag_uart "jtag_uart_0" +Info: Starting classic module elaboration. +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6132_778045434417866752.dir/0010_sopclgen --no_splash --refresh C:/Users/gongal/AppData/Local/Temp/alt6132_778045434417866752.dir/0010_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +Info: Finished elaborating classic module. +Executing: C:/altera/12.1sp1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/Users/gongal/AppData/Local/Temp/alt6132_778045434417866752.dir/0010_sopclgen/yysystem.ptf +Info: Running sopc_builder... +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6132_778045434417866752.dir/0010_sopclgen --generate C:/Users/gongal/AppData/Local/Temp/alt6132_778045434417866752.dir/0010_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +No .sopc_builder configuration file(!) +. +# 2014.03.03 15:20:06 (*) Success: sopc_builder finished. +Info: pio_ir_emitter: "system" instantiated altera_avalon_pio "pio_ir_emitter" +Info: Starting classic module elaboration. +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6132_778045434417866752.dir/0011_sopclgen --no_splash --refresh C:/Users/gongal/AppData/Local/Temp/alt6132_778045434417866752.dir/0011_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +Info: Finished elaborating classic module. +Executing: C:/altera/12.1sp1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/Users/gongal/AppData/Local/Temp/alt6132_778045434417866752.dir/0011_sopclgen/yysystem.ptf +Info: Running sopc_builder... +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6132_778045434417866752.dir/0011_sopclgen --generate C:/Users/gongal/AppData/Local/Temp/alt6132_778045434417866752.dir/0011_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +No .sopc_builder configuration file(!) +. +# 2014.03.03 15:20:10 (*) Success: sopc_builder finished. +Info: uart_mc: "system" instantiated altera_avalon_uart "uart_mc" +Info: rs232_wifi: Starting Generation of RS232 UART +Info: rs232_wifi: "system" instantiated altera_up_avalon_rs232 "rs232_wifi" +Info: cpu_instruction_master_translator: "system" instantiated altera_merlin_master_translator "cpu_instruction_master_translator" +Info: cpu_jtag_debug_module_translator: "system" instantiated altera_merlin_slave_translator "cpu_jtag_debug_module_translator" +Info: cpu_instruction_master_translator_avalon_universal_master_0_agent: "system" instantiated altera_merlin_master_agent "cpu_instruction_master_translator_avalon_universal_master_0_agent" +Info: cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent: "system" instantiated altera_merlin_slave_agent "cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent" +Info: cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo: "system" instantiated altera_avalon_sc_fifo "cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo" +Info: addr_router: "system" instantiated altera_merlin_router "addr_router" +Info: addr_router_001: "system" instantiated altera_merlin_router "addr_router_001" +Info: id_router: "system" instantiated altera_merlin_router "id_router" +Info: id_router_001: "system" instantiated altera_merlin_router "id_router_001" +Info: id_router_002: "system" instantiated altera_merlin_router "id_router_002" +Info: limiter: "system" instantiated altera_merlin_traffic_limiter "limiter" +Info: burst_adapter: "system" instantiated altera_merlin_burst_adapter "burst_adapter" +Info: rst_controller: "system" instantiated altera_reset_controller "rst_controller" +Info: cmd_xbar_demux: "system" instantiated altera_merlin_demultiplexer "cmd_xbar_demux" +Info: cmd_xbar_demux_001: "system" instantiated altera_merlin_demultiplexer "cmd_xbar_demux_001" +Info: cmd_xbar_mux: "system" instantiated altera_merlin_multiplexer "cmd_xbar_mux" +Info: rsp_xbar_demux: "system" instantiated altera_merlin_demultiplexer "rsp_xbar_demux" +Info: rsp_xbar_demux_002: "system" instantiated altera_merlin_demultiplexer "rsp_xbar_demux_002" +Info: rsp_xbar_mux: "system" instantiated altera_merlin_multiplexer "rsp_xbar_mux" +Info: Reusing file C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_arbitrator.sv +Info: rsp_xbar_mux_001: "system" instantiated altera_merlin_multiplexer "rsp_xbar_mux_001" +Info: Reusing file C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_arbitrator.sv +Info: width_adapter: "system" instantiated altera_merlin_width_adapter "width_adapter" +Info: Reusing file C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_burst_uncompressor.sv +Info: Reusing file C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_address_alignment.sv +Info: irq_mapper: "system" instantiated altera_irq_mapper "irq_mapper" +Info: system: Done system" with 35 modules, 140 files, 2721838 bytes +Info: ip-generate succeeded. +Info: Finished: Create HDL design files for synthesis diff --git a/MCandWifiTestDE0/system_generation_29.rpt b/MCandWifiTestDE0/system_generation_29.rpt new file mode 100644 index 00000000..5da5a61c --- /dev/null +++ b/MCandWifiTestDE0/system_generation_29.rpt @@ -0,0 +1,246 @@ +Info: Starting: Create block symbol file (.bsf) +Info: ip-generate --project-directory=C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/ --output-directory=C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/ --report-file=bsf:C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system.bsf --system-info=DEVICE_FAMILY="Cyclone IV E" --system-info=DEVICE=EP4CE22F17C6 --system-info=DEVICE_SPEEDGRADE=6 --component-file=C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system.qsys +Progress: Loading MCandWifiTestDE0/system.qsys +Progress: Reading input file +Progress: Adding clk_sys [clock_source 12.1] +Progress: Parameterizing module clk_sys +Progress: Adding cpu [altera_nios2_qsys 12.1] +Progress: Parameterizing module cpu +Progress: Adding sysid [altera_avalon_sysid_qsys 12.1] +Progress: Parameterizing module sysid +Progress: Adding sdram [altera_avalon_new_sdram_controller 12.1] +Progress: Parameterizing module sdram +Progress: Adding sys_clk_timer [altera_avalon_timer 12.1] +Progress: Parameterizing module sys_clk_timer +Progress: Adding uart_wifi [altera_avalon_uart 12.1] +Progress: Parameterizing module uart_wifi +Progress: Adding pio_led [altera_avalon_pio 12.1] +Progress: Parameterizing module pio_led +Progress: Adding pio_key_left [altera_avalon_pio 12.1] +Progress: Parameterizing module pio_key_left +Progress: Adding pio_sw [altera_avalon_pio 12.1] +Progress: Parameterizing module pio_sw +Progress: Adding jtag_uart_0 [altera_avalon_jtag_uart 12.1] +Progress: Parameterizing module jtag_uart_0 +Progress: Adding pio_ir_emitter [altera_avalon_pio 12.1] +Progress: Parameterizing module pio_ir_emitter +Progress: Adding uart_mc [altera_avalon_uart 12.1] +Progress: Parameterizing module uart_mc +Progress: Adding rs232_wifi [altera_up_avalon_rs232 12.0] +Progress: Parameterizing module rs232_wifi +Progress: Building connections +Progress: Parameterizing connections +Progress: Validating +Progress: Done reading input file +Info: system.sysid: System ID is not assigned automatically. Edit the System ID parameter to provide a unique ID +Info: system.sysid: Time stamp will be automatically updated when this component is generated. +Info: system.pio_key_left: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. +Info: system.pio_sw: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. +Info: ip-generate succeeded. +Info: Finished: Create block symbol file (.bsf) +Info: +Info: Starting: Create HDL design files for synthesis +Info: ip-generate --project-directory=C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/ --output-directory=C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/ --file-set=QUARTUS_SYNTH --report-file=sopcinfo:C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system.sopcinfo --report-file=html:C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system.html --report-file=qip:C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/system.qip --report-file=cmp:C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system.cmp --system-info=DEVICE_FAMILY="Cyclone IV E" --system-info=DEVICE=EP4CE22F17C6 --system-info=DEVICE_SPEEDGRADE=6 --component-file=C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system.qsys +Progress: Loading MCandWifiTestDE0/system.qsys +Progress: Reading input file +Progress: Adding clk_sys [clock_source 12.1] +Progress: Parameterizing module clk_sys +Progress: Adding cpu [altera_nios2_qsys 12.1] +Progress: Parameterizing module cpu +Progress: Adding sysid [altera_avalon_sysid_qsys 12.1] +Progress: Parameterizing module sysid +Progress: Adding sdram [altera_avalon_new_sdram_controller 12.1] +Progress: Parameterizing module sdram +Progress: Adding sys_clk_timer [altera_avalon_timer 12.1] +Progress: Parameterizing module sys_clk_timer +Progress: Adding uart_wifi [altera_avalon_uart 12.1] +Progress: Parameterizing module uart_wifi +Progress: Adding pio_led [altera_avalon_pio 12.1] +Progress: Parameterizing module pio_led +Progress: Adding pio_key_left [altera_avalon_pio 12.1] +Progress: Parameterizing module pio_key_left +Progress: Adding pio_sw [altera_avalon_pio 12.1] +Progress: Parameterizing module pio_sw +Progress: Adding jtag_uart_0 [altera_avalon_jtag_uart 12.1] +Progress: Parameterizing module jtag_uart_0 +Progress: Adding pio_ir_emitter [altera_avalon_pio 12.1] +Progress: Parameterizing module pio_ir_emitter +Progress: Adding uart_mc [altera_avalon_uart 12.1] +Progress: Parameterizing module uart_mc +Progress: Adding rs232_wifi [altera_up_avalon_rs232 12.0] +Progress: Parameterizing module rs232_wifi +Progress: Building connections +Progress: Parameterizing connections +Progress: Validating +Progress: Done reading input file +Info: system.sysid: System ID is not assigned automatically. Edit the System ID parameter to provide a unique ID +Info: system.sysid: Time stamp will be automatically updated when this component is generated. +Info: system.pio_key_left: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. +Info: system.pio_sw: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. +Info: system: Generating system "system" for QUARTUS_SYNTH +Info: pipeline_bridge_swap_transform: After transform: 13 modules, 56 connections +Info: No custom instruction connections, skipping transform +Info: merlin_translator_transform: After transform: 27 modules, 112 connections +Info: merlin_domain_transform: After transform: 54 modules, 296 connections +Info: merlin_router_transform: After transform: 68 modules, 352 connections +Info: merlin_traffic_limiter_transform: After transform: 70 modules, 362 connections +Info: merlin_burst_transform: After transform: 71 modules, 366 connections +Info: reset_adaptation_transform: After transform: 72 modules, 286 connections +Info: merlin_network_to_switch_transform: After transform: 99 modules, 342 connections +Info: merlin_width_transform: After transform: 101 modules, 348 connections +Info: limiter_update_transform: After transform: 101 modules, 350 connections +Info: merlin_interrupt_mapper_transform: After transform: 102 modules, 353 connections +Warning: system: "No matching role found for uart_wifi:s1:dataavailable (dataavailable)" +Warning: system: "No matching role found for uart_wifi:s1:readyfordata (readyfordata)" +Warning: system: "No matching role found for uart_mc:s1:dataavailable (dataavailable)" +Warning: system: "No matching role found for uart_mc:s1:readyfordata (readyfordata)" +Info: cpu: Starting RTL generation for module 'system_cpu' +Info: cpu: Generation command is [exec C:/altera/12.1sp1/quartus/../ip/altera/nios2_ip/altera_nios2/eperl.exe -I C:/altera/12.1sp1/quartus/common/ip/altera/common/perl/5.8.3 -I C:/altera/12.1sp1/quartus/sopc_builder/bin/europa -I C:/altera/12.1sp1/quartus/sopc_builder/bin/perl_lib -I C:/altera/12.1sp1/quartus/sopc_builder/bin -I C:/altera/12.1sp1/quartus/../ip/altera/nios2_ip/altera_nios2/cpu_lib -I C:/altera/12.1sp1/quartus/../ip/altera/nios2_ip/altera_nios2/nios_lib -I C:/altera/12.1sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -I C:/altera/12.1sp1/quartus/../ip/altera/nios2_ip/altera_nios2 -- C:/altera/12.1sp1/quartus/../ip/altera/nios2_ip/altera_nios2/generate_rtl.epl --name=system_cpu --dir=C:/Users/gongal/AppData/Local/Temp/alt6132_5962037963892639434.dir/0001_cpu_gen/ --quartus_dir=C:/altera/12.1sp1/quartus --verilog --config=C:/Users/gongal/AppData/Local/Temp/alt6132_5962037963892639434.dir/0001_cpu_gen//system_cpu_processor_configuration.pl --do_build_sim=0 --bogus ] +Info: cpu: # 2014.03.03 15:46:07 (*) Starting Nios II generation +Info: cpu: # 2014.03.03 15:46:07 (*) Checking for plaintext license. +Info: cpu: # 2014.03.03 15:46:07 (*) Couldn't query license setup in Quartus directory C:/altera/12.1sp1/quartus +Info: cpu: # 2014.03.03 15:46:07 (*) Defaulting to contents of LM_LICENSE_FILE environment variable +Info: cpu: # 2014.03.03 15:46:08 (*) Plaintext license not found. +Info: cpu: # 2014.03.03 15:46:08 (*) Checking for encrypted license (non-evaluation). +Info: cpu: # 2014.03.03 15:46:08 (*) Couldn't query license setup in Quartus directory C:/altera/12.1sp1/quartus +Info: cpu: # 2014.03.03 15:46:08 (*) Defaulting to contents of LM_LICENSE_FILE environment variable +Info: cpu: # 2014.03.03 15:46:08 (*) Encrypted license found. SOF will not be time-limited. +Info: cpu: # 2014.03.03 15:46:08 (*) Elaborating CPU configuration settings +Info: cpu: # 2014.03.03 15:46:08 (*) Creating all objects for CPU +Info: cpu: # 2014.03.03 15:46:08 (*) Testbench +Info: cpu: # 2014.03.03 15:46:08 (*) Instruction decoding +Info: cpu: # 2014.03.03 15:46:08 (*) Instruction fields +Info: cpu: # 2014.03.03 15:46:08 (*) Instruction decodes +Info: cpu: # 2014.03.03 15:46:09 (*) Signals for RTL simulation waveforms +Info: cpu: # 2014.03.03 15:46:09 (*) Instruction controls +Info: cpu: # 2014.03.03 15:46:09 (*) Pipeline frontend +Info: cpu: # 2014.03.03 15:46:09 (*) Pipeline backend +Info: cpu: # 2014.03.03 15:46:12 (*) Generating RTL from CPU objects +Info: cpu: # 2014.03.03 15:46:15 (*) Creating encrypted RTL +Info: cpu: # 2014.03.03 15:46:16 (*) Done Nios II generation +Info: cpu: Done RTL generation for module 'system_cpu' +Info: cpu: "system" instantiated altera_nios2_qsys "cpu" +Info: sysid: "system" instantiated altera_avalon_sysid_qsys "sysid" +Info: Starting classic module elaboration. +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6132_5962037963892639434.dir/0003_sopclgen --no_splash --refresh C:/Users/gongal/AppData/Local/Temp/alt6132_5962037963892639434.dir/0003_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +Info: Finished elaborating classic module. +Executing: C:/altera/12.1sp1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/Users/gongal/AppData/Local/Temp/alt6132_5962037963892639434.dir/0003_sopclgen/yysystem.ptf +Info: Running sopc_builder... +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6132_5962037963892639434.dir/0003_sopclgen --generate C:/Users/gongal/AppData/Local/Temp/alt6132_5962037963892639434.dir/0003_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +No .sopc_builder configuration file(!) +. +. +# 2014.03.03 15:46:20 (*) Running Test Generator Program for system_sdram +# 2014.03.03 15:46:21 (*) Success: sopc_builder finished. +Info: sdram: "system" instantiated altera_avalon_new_sdram_controller "sdram" +Info: Starting classic module elaboration. +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6132_5962037963892639434.dir/0004_sopclgen --no_splash --refresh C:/Users/gongal/AppData/Local/Temp/alt6132_5962037963892639434.dir/0004_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +Info: Finished elaborating classic module. +Executing: C:/altera/12.1sp1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/Users/gongal/AppData/Local/Temp/alt6132_5962037963892639434.dir/0004_sopclgen/yysystem.ptf +Info: Running sopc_builder... +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6132_5962037963892639434.dir/0004_sopclgen --generate C:/Users/gongal/AppData/Local/Temp/alt6132_5962037963892639434.dir/0004_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +No .sopc_builder configuration file(!) +. +# 2014.03.03 15:46:26 (*) Success: sopc_builder finished. +Info: sys_clk_timer: "system" instantiated altera_avalon_timer "sys_clk_timer" +Info: Starting classic module elaboration. +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6132_5962037963892639434.dir/0005_sopclgen --no_splash --refresh C:/Users/gongal/AppData/Local/Temp/alt6132_5962037963892639434.dir/0005_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +Info: Finished elaborating classic module. +Executing: C:/altera/12.1sp1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/Users/gongal/AppData/Local/Temp/alt6132_5962037963892639434.dir/0005_sopclgen/yysystem.ptf +Info: Running sopc_builder... +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6132_5962037963892639434.dir/0005_sopclgen --generate C:/Users/gongal/AppData/Local/Temp/alt6132_5962037963892639434.dir/0005_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +No .sopc_builder configuration file(!) +. +# 2014.03.03 15:46:31 (*) Success: sopc_builder finished. +Info: uart_wifi: "system" instantiated altera_avalon_uart "uart_wifi" +Info: Starting classic module elaboration. +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6132_5962037963892639434.dir/0006_sopclgen --no_splash --refresh C:/Users/gongal/AppData/Local/Temp/alt6132_5962037963892639434.dir/0006_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +Info: Finished elaborating classic module. +Executing: C:/altera/12.1sp1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/Users/gongal/AppData/Local/Temp/alt6132_5962037963892639434.dir/0006_sopclgen/yysystem.ptf +Info: Running sopc_builder... +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6132_5962037963892639434.dir/0006_sopclgen --generate C:/Users/gongal/AppData/Local/Temp/alt6132_5962037963892639434.dir/0006_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +No .sopc_builder configuration file(!) +. +# 2014.03.03 15:46:35 (*) Success: sopc_builder finished. +Info: pio_led: "system" instantiated altera_avalon_pio "pio_led" +Info: Starting classic module elaboration. +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6132_5962037963892639434.dir/0007_sopclgen --no_splash --refresh C:/Users/gongal/AppData/Local/Temp/alt6132_5962037963892639434.dir/0007_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +Info: Finished elaborating classic module. +Executing: C:/altera/12.1sp1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/Users/gongal/AppData/Local/Temp/alt6132_5962037963892639434.dir/0007_sopclgen/yysystem.ptf +Info: Running sopc_builder... +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6132_5962037963892639434.dir/0007_sopclgen --generate C:/Users/gongal/AppData/Local/Temp/alt6132_5962037963892639434.dir/0007_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +No .sopc_builder configuration file(!) +. +# 2014.03.03 15:46:39 (*) Success: sopc_builder finished. +Info: pio_key_left: "system" instantiated altera_avalon_pio "pio_key_left" +Info: Starting classic module elaboration. +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6132_5962037963892639434.dir/0008_sopclgen --no_splash --refresh C:/Users/gongal/AppData/Local/Temp/alt6132_5962037963892639434.dir/0008_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +Info: Finished elaborating classic module. +Executing: C:/altera/12.1sp1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/Users/gongal/AppData/Local/Temp/alt6132_5962037963892639434.dir/0008_sopclgen/yysystem.ptf +Info: Running sopc_builder... +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6132_5962037963892639434.dir/0008_sopclgen --generate C:/Users/gongal/AppData/Local/Temp/alt6132_5962037963892639434.dir/0008_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +No .sopc_builder configuration file(!) +. +# 2014.03.03 15:46:44 (*) Success: sopc_builder finished. +Info: pio_sw: "system" instantiated altera_avalon_pio "pio_sw" +Info: Starting classic module elaboration. +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6132_5962037963892639434.dir/0009_sopclgen --no_splash --refresh C:/Users/gongal/AppData/Local/Temp/alt6132_5962037963892639434.dir/0009_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +Info: Finished elaborating classic module. +Executing: C:/altera/12.1sp1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/Users/gongal/AppData/Local/Temp/alt6132_5962037963892639434.dir/0009_sopclgen/yysystem.ptf +Info: Running sopc_builder... +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6132_5962037963892639434.dir/0009_sopclgen --generate C:/Users/gongal/AppData/Local/Temp/alt6132_5962037963892639434.dir/0009_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +No .sopc_builder configuration file(!) +. +# 2014.03.03 15:46:48 (*) Success: sopc_builder finished. +Info: jtag_uart_0: "system" instantiated altera_avalon_jtag_uart "jtag_uart_0" +Info: Starting classic module elaboration. +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6132_5962037963892639434.dir/0010_sopclgen --no_splash --refresh C:/Users/gongal/AppData/Local/Temp/alt6132_5962037963892639434.dir/0010_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +Info: Finished elaborating classic module. +Executing: C:/altera/12.1sp1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/Users/gongal/AppData/Local/Temp/alt6132_5962037963892639434.dir/0010_sopclgen/yysystem.ptf +Info: Running sopc_builder... +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6132_5962037963892639434.dir/0010_sopclgen --generate C:/Users/gongal/AppData/Local/Temp/alt6132_5962037963892639434.dir/0010_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +No .sopc_builder configuration file(!) +. +# 2014.03.03 15:46:52 (*) Success: sopc_builder finished. +Info: pio_ir_emitter: "system" instantiated altera_avalon_pio "pio_ir_emitter" +Info: Starting classic module elaboration. +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6132_5962037963892639434.dir/0011_sopclgen --no_splash --refresh C:/Users/gongal/AppData/Local/Temp/alt6132_5962037963892639434.dir/0011_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +Info: Finished elaborating classic module. +Executing: C:/altera/12.1sp1/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/Users/gongal/AppData/Local/Temp/alt6132_5962037963892639434.dir/0011_sopclgen/yysystem.ptf +Info: Running sopc_builder... +"c:/altera/12.1sp1/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/12.1sp1/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder -d"c:/altera/12.1sp1/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/gongal/AppData/Local/Temp/alt6132_5962037963892639434.dir/0011_sopclgen --generate C:/Users/gongal/AppData/Local/Temp/alt6132_5962037963892639434.dir/0011_sopclgen/yysystem.v --quartus_dir="c:/altera/12.1sp1/quartus" --sopc_perl="c:/altera/12.1sp1/quartus/bin/perl" --sopc_lib_path="++c:/altera/12.1sp1/quartus/../ip/altera/sopc_builder_ip+c:/altera/12.1sp1/quartus/../ip/altera/nios2_ip" +No .sopc_builder configuration file(!) +. +# 2014.03.03 15:46:57 (*) Success: sopc_builder finished. +Info: uart_mc: "system" instantiated altera_avalon_uart "uart_mc" +Info: rs232_wifi: Starting Generation of RS232 UART +Info: rs232_wifi: "system" instantiated altera_up_avalon_rs232 "rs232_wifi" +Info: cpu_instruction_master_translator: "system" instantiated altera_merlin_master_translator "cpu_instruction_master_translator" +Info: cpu_jtag_debug_module_translator: "system" instantiated altera_merlin_slave_translator "cpu_jtag_debug_module_translator" +Info: cpu_instruction_master_translator_avalon_universal_master_0_agent: "system" instantiated altera_merlin_master_agent "cpu_instruction_master_translator_avalon_universal_master_0_agent" +Info: cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent: "system" instantiated altera_merlin_slave_agent "cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent" +Info: cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo: "system" instantiated altera_avalon_sc_fifo "cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo" +Info: addr_router: "system" instantiated altera_merlin_router "addr_router" +Info: addr_router_001: "system" instantiated altera_merlin_router "addr_router_001" +Info: id_router: "system" instantiated altera_merlin_router "id_router" +Info: id_router_001: "system" instantiated altera_merlin_router "id_router_001" +Info: id_router_002: "system" instantiated altera_merlin_router "id_router_002" +Info: limiter: "system" instantiated altera_merlin_traffic_limiter "limiter" +Info: burst_adapter: "system" instantiated altera_merlin_burst_adapter "burst_adapter" +Info: rst_controller: "system" instantiated altera_reset_controller "rst_controller" +Info: cmd_xbar_demux: "system" instantiated altera_merlin_demultiplexer "cmd_xbar_demux" +Info: cmd_xbar_demux_001: "system" instantiated altera_merlin_demultiplexer "cmd_xbar_demux_001" +Info: cmd_xbar_mux: "system" instantiated altera_merlin_multiplexer "cmd_xbar_mux" +Info: rsp_xbar_demux: "system" instantiated altera_merlin_demultiplexer "rsp_xbar_demux" +Info: rsp_xbar_demux_002: "system" instantiated altera_merlin_demultiplexer "rsp_xbar_demux_002" +Info: rsp_xbar_mux: "system" instantiated altera_merlin_multiplexer "rsp_xbar_mux" +Info: Reusing file C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_arbitrator.sv +Info: rsp_xbar_mux_001: "system" instantiated altera_merlin_multiplexer "rsp_xbar_mux_001" +Info: Reusing file C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_arbitrator.sv +Info: width_adapter: "system" instantiated altera_merlin_width_adapter "width_adapter" +Info: Reusing file C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_burst_uncompressor.sv +Info: Reusing file C:/Users/gongal/NewRepARCap/MCandWifiTestDE0/system/synthesis/submodules/altera_merlin_address_alignment.sv +Info: irq_mapper: "system" instantiated altera_irq_mapper "irq_mapper" +Info: system: Done system" with 35 modules, 140 files, 2721838 bytes +Info: ip-generate succeeded. +Info: Finished: Create HDL design files for synthesis